Patent Publication Number: US-2022231056-A1

Title: Display device

Description:
TECHNICAL FIELD 
     The present invention relates to a display device including an oxide semiconductor. 
     BACKGROUND ART 
     A thin film transistor formed over a flat plate such as a glass substrate is manufactured using amorphous silicon or polycrystalline silicon, as typically seen in a liquid crystal display device. A thin film transistor manufactured using amorphous silicon has low field effect mobility, but such a transistor can be formed over a glass substrate with a larger area. On the other hand, a thin film transistor manufactured using polycrystalline silicon has high field effect mobility, but a crystallization step such as laser annealing is necessary and such a transistor is not always suitable for a larger glass substrate. 
     In view of the foregoing, attention has been drawn to a technique by which a thin film transistor is manufactured using an oxide semiconductor, and such a transistor is applied to an electronic device or an optical device. For example, Patent Document 1 and Patent Document 2 disclose a technique by which a thin film transistor is manufactured using zinc oxide (ZnO) or an In—Ga—Zn—O based oxide semiconductor as an oxide semiconductor film and such a transistor is used as a switching element or the like of an image display device.
     [Patent Document 1] Japanese Published Patent Application No. 2007-123861   [Patent Document 2] Japanese Published Patent Application No. 2007-96055   

     DISCLOSURE OF INVENTION 
     A thin film transistor in which a channel formation region is formed using an oxide semiconductor has characteristics as follows: the operation speed is higher than that of a thin film transistor including amorphous silicon and the manufacturing process is simpler than that of a thin film transistor including polycrystalline silicon. That is, the use of an oxide semiconductor makes it possible to manufacture a thin film transistor with high field effect mobility even at low temperatures of 300° C. or lower. 
     In order to take advantage of the features of a display device including an oxide semiconductor, which is superior in operating characteristics and capable of manufacture at low temperatures, a protective circuit and the like including appropriate structures are necessary. Moreover, it is important to ensure the reliability of the display device including an oxide semiconductor. 
     An object of an embodiment of the present invention is to provide a structure which is suitable as a protective circuit. 
     In a display device intended for a variety of purposes manufactured by stacking, in addition to an oxide semiconductor, an insulating film and a conductive film, an object of an embodiment of the present invention is to prevent a defect due to peeling of a thin film. 
     An embodiment of the present invention is a display device in which a protective circuit is formed using a non-linear element including an oxide semiconductor. This non-linear element includes a combination of oxide semiconductors with different oxygen contents. 
     An illustrative embodiment of the present invention is a display device which includes scan lines and signal lines provided over a substrate having an insulating surface so as to intersect with each other, a pixel portion in which pixel electrodes are arranged in matrix, and a non-linear element formed from an oxide semiconductor in a region outside the pixel portion. The pixel portion includes a thin film transistor in which a channel formation region is formed in a first oxide semiconductor layer. The thin film transistor in the pixel portion includes a gate electrode connected to the scan line, a first wiring layer which is connected to the signal line and which is in contact with the first oxide semiconductor layer, and a second wiring layer which is connected to the pixel electrode and which is in contact with the first oxide semiconductor layer. Moreover, the non-linear element is provided between the pixel portion and a signal input terminal disposed at the periphery of the substrate. The non-linear element includes a gate electrode; a gate insulating layer covering the gate electrode; a pair of a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and whose end portions overlap with the gate electrode over the gate insulating layer; and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with the gate insulating layer, side face portions and part of top face portions of the conductive layer and side face portions of the second oxide semiconductor layer in the first wiring layer and the second wiring layer. The gate electrode of the non-linear element is connected to the scan line or the signal line and the first wiring layer or the second wiring layer of the non-linear element is connected to the gate electrode via a third wiring layer so that the potential of the gate electrode is applied to the first wiring layer or the second wiring layer. 
     An illustrative embodiment of the present invention is a display device which includes scan lines and signal lines provided over a substrate having an insulating surface so as to intersect with each other, a pixel portion including pixel electrodes arranged in matrix, and a protective circuit in a region outside the pixel portion. The pixel portion includes a thin film transistor in which a channel formation region is formed in a first oxide semiconductor layer. The thin film transistor in the pixel portion includes a gate electrode connected to the scan line, a first wiring layer which is connected to the signal line and which is in contact with the first oxide semiconductor layer, and a second wiring layer which is connected to the pixel electrode and which is in contact with the first oxide semiconductor layer. In the region outside the pixel portion, a protective circuit for connecting the scan line and a common wiring to each other and a protective circuit for connecting the signal line and a common wiring to each other are provided. The protective circuit includes a non-linear element, which includes a gate electrode; a gate insulating layer covering the gate electrode; a pair of a first wiring layer and a second wiring layer which is formed by stacking a conductive layer and a second oxide semiconductor layer and whose end portions overlap with the gate electrode over the gate insulating layer; and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with the gate insulating layer, side face portions and part of top face portions of the conductive layer and side face portions of the second oxide semiconductor layer in the first wiring layer and the second wiring layer. Moreover, the gate electrode of the non-linear element is connected to the first wiring layer or the second wiring layer via a third wiring layer. 
     Here, the first oxide semiconductor layer includes oxygen at higher concentration than the second oxide semiconductor layer. That is, the first oxide semiconductor layer is oxygen-excess type, while the second oxide semiconductor layer is oxygen-deficiency type. The second oxide semiconductor layer has n-type conductivity and the first oxide semiconductor layer has lower electrical conductivity than the second oxide semiconductor layer. The first oxide semiconductor layer and the second oxide semiconductor layer are non-single-crystal; preferably, the first oxide semiconductor layer has an amorphous structure and the second oxide semiconductor layer includes a crystal grain (nanocrystal) in an amorphous structure in some cases. 
     Note that the ordinal numbers such as “first” and “second” in this specification are used for convenience and do not denote the order of steps and the stacking order of layers. In addition, the ordinal numbers in this specification do not denote particular names which specify the invention. 
     In this specification, a semiconductor film formed from an oxide semiconductor including In, Ga, and Zn is also referred to as “an IGZO semiconductor film” and a semiconductor layer formed from such an oxide semiconductor is also referred to as “an IGZO semiconductor layer.” 
     According to an embodiment of the present invention, a display device having a structure suitable as a protective circuit can be provided by forming the protective circuit with use of a non-linear element including an oxide semiconductor. When the non-linear element has a stacked structure where the gate insulating layer and the oxide semiconductor layer are in contact with each other, a defect of a protective circuit which is caused by peeling of a thin film can be prevented. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  illustrates a positional relationship among signal input terminals, scan lines, signal lines, protective circuits including non-linear elements, and a pixel portion in a display device. 
         FIG. 2  illustrates an example of a protective circuit. 
         FIG. 3  illustrates an example of a protective circuit. 
         FIGS. 4A and 4B  are plan views illustrating an example of a protective circuit. 
         FIG. 5  is a cross-sectional view illustrating an example of a protective circuit. 
         FIGS. 6A to 6C  are cross-sectional views illustrating a process for manufacturing a protective circuit. 
         FIGS. 7A to 7C  are cross-sectional views illustrating a process for manufacturing a protective circuit. 
         FIGS. 8A and 8B  are plan views illustrating an example of a protective circuit. 
         FIGS. 9A and 9B  are plan views illustrating an example of a protective circuit. 
         FIG. 10  is a cross-sectional view of electronic paper. 
         FIGS. 11A and 11B  are each a block diagram of a semiconductor device. 
         FIG. 12  illustrates a structure of a signal line driver circuit. 
         FIG. 13  is a timing chart of operation of a signal line driver circuit. 
         FIG. 14  is a timing chart of operation of a signal line driver circuit. 
         FIG. 15  is a diagram illustrating a structure of a shift register. 
         FIG. 16  illustrates a connection structure of a flip-flop of  FIG. 14 . 
         FIGS. 17A-1 and 17A-2  are top views and  FIG. 17B  is a cross-sectional view, each illustrating a semiconductor device of Embodiment 5. 
         FIG. 18  is a cross-sectional view illustrating a semiconductor device of Embodiment 5. 
         FIG. 19  illustrates an equivalent circuit of a pixel in a semiconductor device of Embodiment 6. 
         FIGS. 20A to 20C  each illustrate a semiconductor device of Embodiment 6. 
         FIG. 21A  is a top view and  FIG. 21B  is a cross-sectional view, both describing a semiconductor device of Embodiment 6. 
         FIGS. 22A and 22B  illustrate examples of applications of electronic paper. 
         FIG. 23  is an external view illustrating an example of an electronic book device. 
         FIG. 24A  is an external view of an example of a television device and  FIG. 24B  is an external view of an example of a digital photo frame. 
         FIGS. 25A and 25B  are external views illustrating examples of game machines. 
         FIG. 26  is an external view illustrating an example of a cellular phone. 
     
    
    
     BEST MODE FOR CARRYING OUT THE INVENTION 
     Hereinafter, embodiments of the present invention are described below with reference to the drawings. The present invention is not limited to the description below and it is easily understood by those skilled in the art that the mode and details can be changed variously without departing from the scope and spirit of the present invention. Therefore, the present invention should not be interpreted as being limited to what is described in the embodiments described below. Note that a reference numeral denoting the same portion in all figures is used in common in the structures of the present invention which is explained below. 
     Embodiment 1 
     In Embodiment 1, an example of a display device including a pixel portion and a protective circuit including a non-linear element provided around the pixel portion is described with reference to drawings. 
       FIG. 1  illustrates a positional relationship among signal input terminals, scan lines, signal lines, protective circuits including non-linear elements, and a pixel portion in a display device. Over a substrate  10  having an insulating surface, scan lines  13  and signal lines  14  intersect with each other to form a pixel portion  17 . 
     The pixel portion  17  includes a plurality of pixels  18  arranged in matrix. The pixel  18  includes a pixel transistor  19  connected to the scan line  13  and the signal line  14 , a storage capacitor portion  20 , and a pixel electrode  21 . 
     In the pixel structure illustrated here, one electrode of the storage capacitor portion  20  is connected to the pixel transistor  19  and the other electrode is connected to a capacitor line  22 . Moreover, the pixel electrode  21  forms one electrode which drives a display element (such as a liquid crystal element, a light-emitting element, or a contrast medium (electronic ink)). The other electrode of such a display element is connected to a common terminal  23 . 
     A protective circuit is provided between the pixel portion  17 , and a scan line input terminal  11  and a signal line input terminal  12 . In Embodiment 1, a plurality of protective circuits is provided. Therefore, even though surge voltage due to static electricity and the like is applied to the scan line  13 , the signal line  14 , and a capacitor bus line  27 , the pixel transistor  19  and the like are not broken. Accordingly, the protective circuit has a structure for releasing charge to a common wiring  29  or a common wiring  28  when surge voltage is applied to the protective circuit. 
     In Embodiment 1, a protective circuit  24  is provided on the scan line  13  side, a protective circuit  25  is provided on the signal line  14  side, and a protective circuit  26  is provided on the capacitor bus line  27  side. Needless to say, the structures of the protective circuits are not limited to those above. 
       FIG. 2  illustrates an example of the protective circuit. This protective circuit includes a non-linear element  30  and a non-linear element  31  which are arranged in parallel to each other with the scan line  13  interposed therebetween. Each of the non-linear element  30  and the non-linear element  31  includes a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, the non-linear element can be formed through the same steps as the pixel transistor of the pixel portion. For example, characteristics similar to those of a diode can be achieved by connecting a gate terminal to a drain terminal of the non-linear element. 
     A first terminal (gate) and a third terminal (drain) of the non-linear element  30  are connected to the scan line  13 , and a second terminal (source) thereof is connected to the common wiring  29 . A first terminal (gate) and a third terminal (drain) of the non-linear element  31  are connected to the common wiring  29 , and a second terminal (source) thereof is connected to the scan line  13 . That is, the protective circuit illustrated in  FIG. 2  includes two transistors whose rectifying directions are opposite to each other along the scan line  13  and which connect the scan line  13  and the common wiring  29  to each other. In other words, between the scan line  13  and the common wiring  29 , there are a transistor whose rectifying direction is from the scan line  13  to the common wiring  29  and a transistor whose rectifying direction is from the common wiring  29  to the scan line  13 . 
     In the protective circuit illustrated in  FIG. 2 , in the case where the scan line  13  is charged positively or negatively with respect to the common wiring  29  due to static electricity or the like, current flows in a direction that cancels the charge. For example, if the scan line  13  is positively charged, current flows in a direction in which the positive charge is released to the common wiring  29 . Owing to this operation, the electrostatic breakdown or the shift in threshold voltage of the pixel transistor  19  connected to the charged scan line  13  can be prevented. Moreover, it is possible to prevent dielectric breakdown of the insulating film between the charged scan line  13  and another wiring that intersects with the charged scan line  13  with an insulating layer interposed therebetween. 
     Note that in  FIG. 2 , a pair of the non-linear element  30  whose first terminal (gate) is connected to the scan line  13  and the non-linear element  31  whose first terminal (gate) is connected to the common wiring  29  is used; that is, the rectifying directions of the non-linear element  30  and the non-linear element  31  are opposite to each other. The common wiring  29  and the scan line  13  are connected in parallel to each other via the second terminal (source) and the third terminal (drain) of each non-linear element. As another structure, a non-linear element may be further added in parallel connection, so that the operation stability of the protective circuit may be enhanced. For example,  FIG. 3  illustrates a protective circuit including a non-linear element  30   a  and a non-linear element  30   b , and a non-linear element  31   a  and a non-linear element  31   b , which is provided between the scan line  13  and the common wiring  29 . This protective circuit includes four non-linear elements in total: two non-linear elements ( 30   b  and  31   b ), a first terminal (gate) of each of which is connected to the common wiring  29  and two non-linear elements ( 30   a  and  31   a ), a first terminal (gate) of each of which is connected to the scan line  13 . That is to say, two pairs of non-linear elements are connected between the common wiring  29  and the scan line  13 , each pair including two non-linear elements provided so that their rectifying directions are opposite to each other. In other words, between the scan line  13  and the common wiring  29 , there are two transistors the rectifying direction of each of which is from the scan line  13  to the common wiring  29  and two transistors the rectifying direction of each of which is from the common wiring  29  to the scan line  13 . When the common wiring  29  and the scan line  13  are connected to each other with the four non-linear elements in this manner, it is possible to prevent, even if surge voltage is applied to the scan line  13  and moreover even if the common wiring  29  is charged by static electricity or the like, the charge from directly flowing through the scan line  13 . Note that  FIG. 9A  illustrates an example in which four non-linear elements  740   a ,  740   b ,  740   c , and  740   d  are provided over a substrate and  FIG. 9B  is an equivalent circuit diagram thereof. Note that reference numerals  650  and  651  in  FIGS. 9A and 9B  denote a scan line and a common wiring, respectively. 
       FIG. 8A  illustrates an example of providing a protective circuit which is formed using an odd number of non-linear elements over a substrate, and  FIG. 8B  is an equivalent circuit diagram thereof. In this circuit, a non-linear element  730   b  and a non-linear element  730   a  are connected to a non-linear element  730   c  as switching elements. By the serial connection of the non-linear elements in this manner, instantaneous load applied to the non-linear elements of the protective circuit can be deconcentrated. Note that reference numerals  650  and  651  in  FIGS. 8A and 8B  denote a scan line and a common wiring, respectively. 
       FIG. 2  illustrates an example of the protective circuit which is provided on the scan line  13  side; however, a protective circuit with a similar structure can be provided on the signal line  14  side. 
       FIG. 4A  is a plan view illustrating an example of a protective circuit and  FIG. 4B  is an equivalent circuit diagram thereof.  FIG. 5  is a cross-sectional view taken along line Q 1 -Q 2  of  FIG. 4A . A structure example of the protective circuit is described below with reference to  FIGS. 4A and 4B  and  FIG. 5 . 
     The non-linear element  30   a  and the non-linear element  30   b  include a gate electrode  15  and a gate electrode  16 , respectively, which are formed using the same layer as the scan line  13 . A gate insulating layer  37  is formed over the gate electrode  15  and the gate electrode  16 . A first wiring layer  38  and a second wiring layer  39  are provided over the gate insulating film  37  so as to face with each other over the gate electrode  15 . Note that the non-linear element  30   a  and the non-linear element  30   b  have the same structure in the main portion. 
     A first oxide semiconductor layer  36  is provided so as to cover a region between the first wiring layer  38  and the second wiring layer  39  which face with each other. That is, the first oxide semiconductor layer  36  is provided so as to overlap with the gate electrode  15  and be in contact with the gate insulating layer  37 , and side face portions and part of top face portions of and the first wiring layer  38  and the second wiring layer  39 . Here, the first wiring layer  38  and the second wiring layer  39  each have a structure in which a second oxide semiconductor layer  40  and a conductive layer  41  are stacked in that order from the gate insulating layer  37  side. The gate insulating layer  37  is formed from an oxide such as silicon oxide or aluminum oxide. 
     The first oxide semiconductor layer  36  has higher oxygen concentration than the second oxide semiconductor layer  40 . In other words, the first oxide semiconductor layer  36  is oxygen-excess type, while the second oxide semiconductor layer  40  is oxygen-deficiency type. Since the donor-type defects can be reduced by increasing the oxygen concentration of the first oxide semiconductor layer  36 , there are advantageous effects of longer carrier lifetime and higher mobility. On the other hand, when the oxygen concentration of the second oxide semiconductor layer  40  is made lower than that of the first oxide semiconductor layer  36 , the carrier concentration can be increased and the second oxide semiconductor layer  40  can be utilized for forming a source region and a drain region. 
     An oxide semiconductor is non-single-crystal, and preferably, the first oxide semiconductor layer  36  has an amorphous structure and the second oxide semiconductor layer  40  includes a crystal grain (nanocrystal) in an amorphous structure in some cases. Then, the first oxide semiconductor layer  36  has a characteristic that the electrical conductivity thereof is lower than that of the second oxide semiconductor layer  40 . Therefore, the second oxide semiconductor layers  40  used as the components of the first wiring layer  38  and the second wiring layer  39  in the non-linear element  30   a  and the non-linear element  30   b  of Embodiment 1 can have functions similar to those of a source region and a drain region of a transistor. 
     The first oxide semiconductor layer  36  and the second oxide semiconductor layer  40  are formed from a non-single-crystal oxide semiconductor, typically, zinc oxide (ZnO), or an oxide semiconductor material including In, Ga, and Zn. 
     End portions of the first wiring layer  38  and the second wiring layer  39  overlap with the gate electrode  15 , and the first wiring layer  38  and the second wiring layer  39  each have a structure in which the second oxide semiconductor layer  40  and the conductive layer  41  are stacked in that order from the gate insulating layer  37  side. The second oxide semiconductor layer  40  is provided in contact with the gate insulating layer  37  and the first oxide semiconductor layer  36  is provided in contact with side face portions of the second oxide semiconductor layer  40  and side face portions and part of top face portions of the conductive layer  41 . Over the gate insulating layer  37 , the oxide semiconductor layers having different physical properties as above are bonded to each other. When the non-linear element  30   a  and the non-linear element  30   b  have such a bonding structure, the operation can be made stable as compared to a non-linear element having Schottky junction formed in the case where the first wiring layer  38  and the second wiring layer  39  are formed using only metal layers. Moreover, the amount of junction leakage can be reduced and the characteristics of the non-linear element  30   a  and the non-linear element  30   b  can be improved. 
     The adhesion between the gate insulating layer  37 , and the first oxide semiconductor layer  36  and the second oxide semiconductor layer  40  is favorable and peeling of a thin film does not easily occur. That is, the first wiring layer  38  and the second wiring layer  39  are in close contact with each other as compared with the case where a metal wiring of aluminum or the like is directly formed in contact with the gate insulating layer  37 ; therefore, a defect of a protective circuit which is caused by peeling of a thin film can be prevented. 
     An interlayer insulating layer  42  is provided over the first oxide semiconductor layer  36 . The interlayer insulating layer  42  is formed from an oxide such as silicon oxide or aluminum oxide. When silicon nitride, aluminum nitride, silicon oxynitride, or aluminum oxynitride is stacked over silicon oxide or aluminum oxide, the function as the protective film can be enhanced. 
     In any case, when the interlayer insulating layer  42  being in contact with the first oxide semiconductor layer  36  is an oxide, it is possible to prevent oxygen from being extracted from the first oxide semiconductor layer  36  and prevent the first oxide semiconductor layer  36  from changing into an oxygen-deficiency type. 
     The interlayer insulating layer  42  is provided with a contact hole  43  where the scan line  13  formed using the same layer as the gate electrode  15  is connected to a third terminal (drain) of the non-linear element  30   a . This connection is made by a third wiring layer  44  formed using the same material as the pixel electrode of the pixel portion. The third wiring layer  44  is formed from a material which is used for forming a transparent electrode, for example, from indium tin oxide (ITO), zinc oxide (ZnO), tin oxide (SnO 2 ), or the like. Thus, the third wiring layer  44  has higher resistance than a wiring formed from a metal material. When the protective circuit includes the wirings including such a resistance component, it is possible to prevent an excessive amount of current from flowing through the non-linear element  30   a  and the non-linear element  30   a  from being destroyed. 
     Although  FIGS. 4A and 4B  and  FIG. 5  illustrate the example of the protective circuit provided at the scan line  13 , a similar protective circuit can be applied to a signal line, a capacitor bus line, or the like. 
     According to Embodiment 1, by the provision of the protective circuit including the non-linear element formed from the oxide semiconductor in this manner, a display device having a structure which is suitable as a protective circuit can be provided. Further, a defect of a protective circuit which is caused by peeling of a thin film can be prevented. 
     Embodiment 2 
     In Embodiment 2, an embodiment of a process for manufacturing the protective circuit illustrated in  FIG. 4A  in Embodiment 1 is described with reference to  FIGS. 6A to 6C  and  FIGS. 7A to 7C .  FIGS. 6A to 6C  and  FIGS. 7A to 7C  are cross-sectional views taken along line Q 1 -Q 2  of  FIG. 4A . 
     In  FIG. 6A , a glass substrate of barium borosilicate glass, aluminoborosilicate glass, aluminosilicate glass, or the like available in the market can be used as the substrate  100  having a light-transmitting property. For example, a glass substrate which includes more barium oxide (BaO) than boric acid (B 2 O 3 ) in composition ratio and whose strain point is 730° C. or higher is preferable. This is because the glass substrate is not strained even in the case where the oxide semiconductor layer is thermally processed at high temperatures of about 700° C. 
     Next, a conductive layer is formed entirely over the substrate  100 . After that, a resist mask is formed by a first photolithography process, and an unnecessary portion is removed by etching to form wirings and an electrode (such as a gate wiring including a gate electrode  101 , a capacitor wiring, and a terminal). At this time, the etching is performed so that at least an end portion of the gate electrode  101  is tapered. Also, a scan line  108  is formed using the same layer as the gate electrode  101 . 
     The gate wiring including the gate electrode  101 , the capacitor wiring, and the terminal of a terminal portion are desirably formed from a low-resistance conductive material such as aluminum (Al) or copper (Cu); however, since aluminum alone has disadvantages such as low heat resistance and a tendency to be corroded, it is used in combination with a conductive material having heat resistance. As the conductive material having heat resistance, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), and neodymium (Nd), an alloy containing the above element as its component, an alloy film in which some of the above elements are combined, or a nitride containing the above element as its component may be used.  FIG. 6A  is a cross-sectional view at this stage. 
     Subsequently, a gate insulating layer  102  is formed entirely over the gate electrode  101 . The gate insulating layer  102  is formed by a sputtering method or the like to a thickness of 50 to 250 nm. 
     For example, a silicon oxide film is formed by a sputtering method to a thickness of 100 nm as the gate insulating layer  102 . Needless to say, the gate insulating layer  102  is not limited to such a silicon oxide film and may be a single layer or a stack of layers including another insulating film such as a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, or a tantalum oxide film. 
     Next, a second oxide semiconductor film is formed over the gate insulating layer  102  by a sputtering method. Here, sputtering deposition is performed under the condition where a target includes indium oxide (In 2 O 3 ), gallium oxide (Ga 2 O 3 ), and zinc oxide (ZnO) at a composition ratio of 1:1:1 (=In 2 O 3 :Ga 2 O 3 :ZnO), the pressure in a deposition chamber is set at 0.4 Pa, the electric power is set at 500 W, the deposition temperature is set to room temperature, and the argon gas flow rate is set at 40 sccm. Thus, a semiconductor film including In, Ga, Zn, and oxygen is formed as the second oxide semiconductor film. Although the target where the composition ratio is In 2 O 3 :Ga 2 O 3 :ZnO=1:1:1 is used intentionally, an oxide semiconductor film including a crystal grain which has a size of 1 nm to 10 nm just after the deposition is often obtained. It can be said that the presence or absence of crystal grains and the density of crystal grains can be controlled and the diameter of the crystal grain can be adjusted within 1 nm to 10 nm, all by adjusting as appropriate, the deposition condition of reactive sputtering, such as the target composition ratio, the deposition pressure (0.1 Pa to 2.0 Pa), the electric power (250 W to 3000 W: 8 inchesϕ), the temperature (room temperature to 100° C.), and the like. The thickness of the second oxide semiconductor film is set to 5 nm to 20 nm. Needless to say, in the case where the film includes crystal grains, the size of the crystal grain does not exceed the film thickness. In Embodiment 2, the second oxide semiconductor film has a thickness of 5 nm. 
     Next, a conductive film is formed from a metal material over the second oxide semiconductor film by a sputtering method or a vacuum evaporation method. As the material of the conductive film, there are an element selected from Al, Cr, Ta, Ti, Mo, and W, an alloy including the above element, an alloy film in which some of the above elements are combined, and the like. Here, the conductive film has a three-layer structure in which a Ti film is formed, an aluminum (Al) film is stacked over the Ti film, and another Ti film is stacked over the Al film. Alternatively, the conductive film may have a two-layer structure in which a titanium film is stacked over an aluminum film. Further alternatively, the conductive film may have a single-layer structure of an aluminum film including silicon or a titanium film. 
     The gate insulating layer, the second oxide semiconductor film, and the conductive film can be formed by a sputtering method successively without exposure to the air by changing the gas introduced to the chamber and the target set in the chamber as appropriate. The successive deposition without exposure to the air can prevent impurity mixture. In the case of successive deposition without exposure to the air, a manufacturing apparatus of multichamber type is preferable. 
     Next, a second photolithography process is performed to form a resist mask, and an unnecessary portion of the conductive film is removed by etching. Thus, a source electrode layer  105   a  and a drain electrode layer  105   b  are formed. The etching may be wet etching or dry etching. Here, dry etching is performed using as a reactive gas, a mixed gas of SiCl 4 , Cl 2 , and BCl 3  to etch the conductive film in which the Ti film, the Al film, and the Ti film are stacked in this order. Thus, the source electrode layer  105   a  and the drain electrode layer  105   b  are formed. 
     Next, the second oxide semiconductor film is etched in a self-aligning manner by using the source electrode layer  105   a  and the drain electrode layer  105   b  as masks. Here, wet etching is performed using ITO07N (product of Kanto Chemical Co., Inc.) to remove an unnecessary portion; thus, a source region  106   a  and a drain region  106   b  are formed. Note that the etching performed here may be dry etching instead of wet etching. A cross-sectional view after the resist mask is removed is shown in  FIG. 6B . 
     Next, plasma treatment is performed. Here, reverse sputtering where plasma is generated after introduction of an oxygen gas and an argon gas into a deposition chamber is performed, so that the exposed gate insulating layer is irradiated with oxygen radicals or oxygen. Thus, dust adhering to the surface is removed and moreover the surface of the gate insulating layer is modified into an oxygen-excess region. It is effective to perform the oxygen radical treatment on the surface of the gate insulating layer so that the surface is made into an oxygen-excess region, in point of that an oxygen source for modifying the interface of the first oxide semiconductor layer is made in thermal treatment (200° C. to 600° C.) for increasing the reliability in a later step. A cross-sectional view when this step is completed is shown in  FIG. 6C . 
     Next, the first oxide semiconductor film is formed in such a manner that the substrate on which the plasma treatment has been performed is not exposed to the air. The first oxide semiconductor film formed in such a manner that the substrate on which the plasma treatment has been performed is not exposed to the air can avoid the trouble that dust or moisture adheres to the interface between the gate insulating layer and the semiconductor film. Here, the first oxide semiconductor film is formed in an oxygen atmosphere under the condition where the target is an oxide semiconductor target including In, Ga, and Zn (composition ratio is In 2 O 3 :Ga 2 O 3 :ZnO=1:1:1) with a diameter of 8 inches, the distance between the substrate and the target is set at 170 mm, the pressure is set at 0.4 Pa, and the direct current (DC) power supply is set at 0.5 kW. Note that a pulse direct current (DC) power supply is preferable because dust can be reduced and the film thickness can be uniform. The thickness of the first oxide semiconductor film is set to 5 nm to 200 nm. The thickness of the first oxide semiconductor film in Embodiment 2 is 100 nm. 
     When the first oxide semiconductor film is formed under a condition different from that of the second oxide semiconductor film, the first oxide semiconductor film has a different composition from that of the second oxide semiconductor film; for example, the first oxide semiconductor film has higher oxygen concentration than the second oxide semiconductor film. In this case, the ratio of the oxygen gas flow rate to the argon gas flow rate in the deposition condition of the first oxide semiconductor film is set higher than that of the second oxide semiconductor film. Specifically, the second oxide semiconductor film is formed in a rare gas (such as argon or helium) atmosphere (or a gas including oxygen at 10% or less and argon at 90% or more), while the first oxide semiconductor film is formed in an oxygen atmosphere (or a mixed gas of oxygen and argon with the flow rate of oxygen being more than that of argon). When the first oxide semiconductor film includes more oxygen than the second oxide semiconductor film, the first oxide semiconductor film can have lower electrical conductivity than the second oxide semiconductor film. Moreover, when the first oxide semiconductor film includes a large amount of oxygen, the amount of off current can be reduced; therefore, a thin film transistor with a high on/off ratio can be provided. 
     The first oxide semiconductor film may be formed in the same chamber as the chamber where the reverse sputtering is performed previously, or may be formed in a different chamber from the chamber where the reverse sputtering is performed previously as long as the deposition can be performed without exposure to the air. 
     Next, thermal treatment at 200° C. to 600° C., typically 300° C. to 500° C., is preferably performed. Here, thermal treatment is performed in a furnace at 350° C. for an hour in a nitrogen atmosphere. This thermal treatment allows atoms of the IGZO semiconductor films to be rearranged. Since the distortion that interrupts carrier movement is released by this thermal treatment, the thermal treatment here (including photo-annealing) is important. There is no particular limitation on when to perform the thermal treatment as long as it is performed after the formation of the first oxide semiconductor film; for example, it may be performed after the formation of the pixel electrode. 
     Next, a third photolithography process is performed to form a resist mask, and an unnecessary portion is removed by etching. Thus, the first oxide semiconductor layer  103  is formed. Here, wet etching is performed using ITO07N (product of Kanto Chemical Co., Inc.); thus, the first oxide semiconductor layer  103  is formed. Note that since the first oxide semiconductor film and the second oxide semiconductor film are dissolved in the same etchant, the etching performed here removes part of the second oxide semiconductor film. A portion of the second oxide semiconductor film (IGZO semiconductor film), which is covered with the resist mask and the first oxide semiconductor film, is protected; however, an end portion of the second oxide semiconductor film which is exposed is slightly etched. Therefore, the shape of the end portion thereof changes. Note that the etching of the first oxide semiconductor layer  103  is not limited to wet etching and may be dry etching. Then, the resist mask is removed. Through these steps, the non-linear element  30   a  in which the first oxide semiconductor layer  103  is a channel formation region is completed. A cross-sectional view at this point is shown in  FIG. 7A . 
     Next, a protective insulating film  107  covering the non-linear element  30   a  is formed. The protective insulating film  107  can be formed using a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or the like which can be deposited by a sputtering method or the like. 
     Next, a fourth photolithography process is performed to form a resist mask, and the protective insulating film  107  is etched. Thus, a contact hole  125  that reaches the drain electrode layer  105   b  is formed. It is preferable that a contact hole  126  that reaches the gate electrode be formed by etching the gate insulating layer  102  with the use of the same resist mask, because the number of photomasks can be reduced. The resist mask is removed and a cross-sectional view at this point is shown in  FIG. 7B . 
     Next, a third wiring layer  128  is formed. When the third wiring layer  128  is formed using a transparent conductive film, a pixel electrode can be formed together with a film to be the third wiring layer  128 . As the material of the transparent conductive film, there are indium oxide (In 2 O 3 ), indium oxide-tin oxide alloy (In 2 O 3 —SnO 2 , abbreviated as ITO), and the like and the third wiring layer is formed by a sputtering method, a vacuum evaporation method, or the like. Etching treatment of such materials is performed using a chlorinated acid based solution. However, since etching of ITO particularly tends to leave residue, an alloy of indium oxide and zinc oxide (In 2 O 3 —ZnO) may be used in order to improve etching processability. The transparent conductive film is etched in this manner to be the third wiring layer  128 . 
     Next, a fifth photolithography process is performed to form a resist mask, and an unnecessary portion of the transparent conductive film is removed by etching. Thus, a pixel electrode is formed in a pixel portion which is not shown. 
     In the fifth photolithography process, a storage capacitor is formed by the capacitor wiring and the pixel electrode in a capacitor portion which is not shown, using the gate insulating layer  102  and the protective insulating film  107  as dielectrics. 
     In the fifth photolithography process, the terminal portion is covered with the resist mask so that the transparent conductive film formed in the terminal portion remains. The transparent conductive film is used for an electrode or a wiring for connection with an FPC or used for a terminal electrode or the like for connection which functions as an input terminal of a source wiring. 
     Moreover, in Embodiment 2, the drain electrode layer  105   b  of the non-linear element  30   a  is connected to the scan line  108  in the contact holes  125  and  126  via the third wiring layer  128  formed using the transparent conductive film. 
     Next, the resist mask is removed. A cross-sectional view at this point is shown in  FIG. 7C . 
     Through the five photolithography processes performed in the above manner, the protective circuit having the plurality of non-linear elements (in Embodiment 2, the two non-linear elements  30   a  and  30   b ) can be completed by using the five photomasks. According to Embodiment 2, a plurality of TFTs can be completed by a similar method together with the non-linear elements. Therefore, a pixel portion including bottom-gate n-channel TFTs and a protective circuit can be manufactured at the same time. In other words, a board for an active matrix display device, on which a protective diode having few defects in a protective circuit due to peeling of a thin film is mounted, can be manufactured in accordance with the steps described in Embodiment 2. 
     Embodiment 3 
     Embodiment 3 illustrates an example of electronic paper in which a protective circuit and a TFT in a pixel portion are provided over one substrate, as a display device to which an embodiment of the present invention is applied. 
       FIG. 10  illustrates active matrix type electronic paper as an example of a display device to which an embodiment of the present invention is applied. A thin film transistor  581  used for a display device can be manufactured in a manner similar to the non-linear element described in Embodiment 2. The thin film transistor  581  has high electrical characteristics and includes a gate insulating layer on which plasma treatment has been performed, a source region and a drain region which are formed using an IGZO semiconductor film of oxygen-deficiency type, a source electrode layer and a drain electrode layer which are in contact with the source region and the drain region respectively, and an IGZO semiconductor layer of oxygen-excess type which is in contact with the source region and the drain region. 
     The electronic paper in  FIG. 10  is an example of a display device in which a twisting ball display system is employed. The twisting ball display system refers to a method in which spherical particles each colored in black and white are arranged between a first electrode layer and a second electrode layer which are electrode layers used for a display element, and a potential difference is generated between the first electrode layer and the second electrode layer to control orientation of the spherical particles, so that display is performed. 
     The thin film transistor  581  has a bottom-gate structure in which the source electrode layer or the drain electrode layer is electrically connected to a first electrode layer  587  in an opening formed in an insulating layer  585 . Between the first electrode layer  587  and a second electrode layer  588 , spherical particles  589  are provided. Each spherical particle  589  includes a black region  590   a , a white region  590   b , and a cavity  594  filled with liquid around the black region  590   a  and the white region  590   b . The circumference of the spherical particle  589  is filled with filler  595  such as a resin or the like (see  FIG. 10 ). Note that reference numerals  580 ,  583 ,  584  and  596  in  FIG. 10  denote a substrate, interlayer insulating layer, protective film and a substrate, respectively. 
     Further, instead of the twisting ball, an electrophoretic element can be used. A microcapsule having a diameter of about 10 μm to 200 μm, which is filled with transparent liquid, positively-charged white microparticles and negatively-charged black microparticles, is used. In the microcapsule which is provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white microparticles and the black microparticles move to opposite sides to each other, so that white or black can be displayed. A display element using this principle is an electrophoretic display element, and is called electronic paper in general. The electrophoretic display element has higher reflectance than a liquid crystal display element, and thus, an assistant light is unnecessary. Moreover, power consumption is low and a display portion can be recognized in a dusky place. Furthermore, an image which is displayed once can be retained even when power is not supplied to the display portion. Accordingly, a displayed image can be stored even though a semiconductor device having a display function (which is also referred to simply as a display device or a semiconductor device provided with a display device) is distanced from an electric wave source which serves as a power supply. 
     According to Embodiment 3, a display device having a structure suitable as a protective circuit can be provided by forming the protective circuit with use of the non-linear element including the oxide semiconductor. In the connection structure between the first oxide semiconductor layer of the non-linear element and the wiring layers, the provision of the region which is bonded with the second oxide semiconductor layer, which has higher electrical conductivity than the first oxide semiconductor layer, allows stable operation as compared with the case of using only metal wirings. Accordingly, a defect due to peeling of a thin film does not easily occur. In this manner, according to Embodiment 3, electronic paper with high reliability as a display device can be completed. 
     Embodiment 3 can be implemented in combination with the structure described in another Embodiment as appropriate. 
     Embodiment 4 
     Embodiment 4 describes an example of manufacturing at least a protective circuit, part of a driver circuit, and a thin film transistor of a pixel portion over one substrate in a display device which is an example of a semiconductor device according to an embodiment of the present invention. 
     The thin film transistor in the pixel portion is formed in a manner similar to the non-linear element described in Embodiment 2. The thin film transistor is formed to be an n-channel TFT; therefore, part of a driver circuit, which can be formed using an n-channel TFT, is formed over the same substrate as the thin film transistor in the pixel portion. 
       FIG. 11A  illustrates an example of a block diagram of an active matrix liquid crystal display device which is an example of a semiconductor device according to an embodiment of the present invention. The display device illustrated in  FIG. 11A  includes over a substrate  5300 , a pixel portion  5301  including a plurality of pixels each provided with a display element; a scan line driver circuit  5302  that selects each pixel; and a signal line driver circuit  5303  that controls a video signal input to a selected pixel. 
     The pixel portion  5301  is connected to the signal line driver circuit  5303  with a plurality of signal lines Si to Sm (not shown) extending in a column direction from the signal line driver circuit  5303  and connected to the scan line driver circuit  5302  with a plurality of scan lines G 1  to Gn (not shown) extending in a row direction from the scan line driver circuit  5302 . The pixel portion  5301  includes a plurality of pixels (not shown) arranged in matrix corresponding to the signal lines Si to Sm and the scan lines G 1  to Gn. In addition, each of the pixels is connected to a signal line Sj (any one of the signal lines Si to Sm) and a scan line Gi (any one of the scan lines G 1  to Gn). 
     The thin film transistor can be formed as an n-channel TFT by a method similar to that of the non-linear element described in Embodiment 2, and a signal line driver circuit including an n-channel TFT is described with reference to  FIG. 12 . 
     The signal line driver circuit in  FIG. 12  includes a driver IC  5601 , switch groups  5602 _ 1  to  5602 _M, a first wiring  5611 , a second wiring  5612 , a third wiring  5613 , and wirings  5621 _ 1  to  5621 _M. Each of the switch groups  5602 _ 1  to  5602 _M includes a first thin film transistor  5603   a , a second thin film transistor  5603   b , and a third thin film transistor  5603   c.    
     The driver IC  5601  is connected to the first wiring  5611 , the second wiring  5612 , the third wiring  5613 , and the wirings  5621 _ 1  to  5621 _M. Each of the switch groups  5602 _ 1  to  5602 _M is connected to the first wiring  5611 , the second wiring  5612 , the third wiring  5613 , and one of the wirings  5621 _ 1  to  5621 _M corresponding to the switch groups  5602 _ 1  to  5602 _M, respectively. Each of the wirings  5621 _ 1  to  5621 _M is connected to three signal lines through the first thin film transistor  5603   a , the second thin film transistor  5603   b , and the third thin film transistor  5603   c . For example, the wiring  5621 _J of the J-th column (one of the wirings  5621 _ 1  to  5621 _M) is connected to a signal line Sj−1, a signal line Sj, and a signal line Sj+1 through the first thin film transistor  5603   a , the second thin film transistor  5603   b , and the third thin film transistor  5603   c  of the switch group  5602 _J. 
     Note that a signal is input to each of the first wiring  5611 , the second wiring  5612 , and the third wiring  5613 . 
     Note that the driver IC  5601  is preferably formed on a single-crystal substrate. The switch groups  5602 _ 1  to  5602 _M are preferably formed over the same substrate as the pixel portion. Therefore, the driver IC  5601  is preferably connected to the switch groups  5602 _ 1  to  5602 _M through an FPC or the like. 
     Next, operation of the signal line driver circuit in  FIG. 12  is described with reference to a timing chart of  FIG. 13 .  FIG. 13  illustrates the timing chart where a scan line Gi in the i-th row is selected. A selection period of the scan line Gi in the i-th row is divided into a first sub-selection period T 1 , a second sub-selection period T 2 , and a third sub-selection period T 3 . In addition, the signal line driver circuit in  FIG. 12  operates similarly to  FIG. 13  even when a scan line of another row is selected. 
     Note that the timing chart in  FIG. 13  shows the case where the wiring  5621 _J in the J-th column is connected to the signal line Sj−1, the signal line Sj, and the signal line Sj+1 through the first thin film transistor  5603   a , the second thin film transistor  5603   b , and the third thin film transistor  5603   c.    
     The timing chart of  FIG. 13  shows timing when the scan line Gi in the i-th row is selected, timing  5703   a  when the first thin film transistor  5603   a  is turned on/off, timing  5703   b  when the second thin film transistor  5603   b  is turned on/off, timing  5703   c  when the third thin film transistor  5603   c  is turned on/off, and a signal  5721 _J input to the wiring  5621 _J in the J-th column. 
     In the first sub-selection period T 1 , the second sub-selection period T 2 , and the third sub-selection period T 3 , different video signals are input to the wirings  5621 _ 1  to  5621 _M. For example, a video signal input to the wiring  5621 _J in the first sub-selection period T 1  is input to the signal line Sj−1, a video signal input to the wiring  5621 _J in the second sub-selection period T 2  is input to the signal line Sj, and a video signal input to the wiring  5621 _J in the third sub-selection period T 3  is input to the signal line Sj+1. The video signals input to the wiring  5621 _J in the first sub-selection period T 1 , the second sub-selection period T 2 , and the third sub-selection period T 3  are denoted by Data_j−1, Data_j, and Data_j+1, respectively. 
     As shown in  FIG. 13 , in the first sub-selection period T 1 , the first thin film transistor  5603   a  is on, and the second thin film transistor  5603   b  and the third thin film transistor  5603   c  are off. At this time, Data_j−1 input to the wiring  5621 _J is input to the signal line Sj−1 through the first thin film transistor  5603   a . In the second sub-selection period T 2 , the second thin film transistor  5603   b  is on, and the first thin film transistor  5603   a  and the third thin film transistor  5603   c  are off. At this time, Data_j input to the wiring  5621 _J is input to the signal line Sj through the second thin film transistor  5603   b . In the third sub-selection period T 3 , the third thin film transistor  5603   c  is on, and the first thin film transistor  5603   a  and the second thin film transistor  5603   b  are off. At this time, Data_j+1 input to the wiring  5621 _J is input to the signal line Sj+1 through the third thin film transistor  5603   c.    
     As described above, in the signal line driver circuit of  FIG. 12 , one gate selection period is divided into three; thus, video signals can be input to three signal lines from one wiring  5621  in one gate selection period. Therefore, in the signal line driver circuit of  FIG. 12 , the number of connections between the substrate provided with the driver IC  5601  and the substrate provided with the pixel portion can be reduced to approximately one third of the number of signal lines. When the number of connections is reduced to approximately one third of the number of signal lines, the reliability, yield, and the like of the signal line driver circuit in  FIG. 12  can be improved. 
     Note that there is no particular limitation on the arrangement, number, driving method, and the like of the thin film transistors, as long as one gate selection period is divided into a plurality of sub-selection periods and video signals are input to a plurality of signal lines from one wiring in each of the plurality of sub-selection periods as shown in  FIG. 12 . 
     For example, when video signals are input to three or more signal lines from one wiring in each of three or more sub-selection periods, a thin film transistor and a wiring for controlling the thin film transistor may be added as needed. Note that when one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes short. Therefore, one gate selection period is preferably divided into two or three sub-selection periods. 
     As another example, as shown in a timing chart of  FIG. 14 , one selection period may be divided into a precharge period Tp, the first sub-selection period T 1 , the second sub-selection period T 2 , and the third sub-selection period T 3 . The timing chart of  FIG. 14  shows timing when the scan line Gi in the i-th row is selected, timing  5803   a  when the first thin film transistor  5603   a  is turned on/off, timing  5803   b  when the second thin film transistor  5603   b  is turned on/off, timing  5803   c  when the third thin film transistor  5603   c  is turned on/off, and a signal  5821 _J input to the wiring  5621 _J in the J-th column. As shown in  FIG. 14 , the first thin film transistor  5603   a , the second thin film transistor  5603   b , and the third thin film transistor  5603   c  are on in the precharge period Tp. At this time, precharge voltage Vp input to the wiring  5621 _J is input to the signal line Sj−1, the signal line Sj, and the signal line Sj+1 through the first thin film transistor  5603   a , the second thin film transistor  5603   b , and the third thin film transistor  5603   c , respectively. In the first sub-selection period T 1 , the first thin film transistor  5603   a  is on, and the second thin film transistor  5603   b  and the third thin film transistor  5603   c  are off. At this time, Data_j−1 input to the wiring  5621 _J is input to the signal line Sj−1 through the first thin film transistor  5603   a . In the second sub-selection period T 2 , the second thin film transistor  5603   b  is on, and the first thin film transistor  5603   a  and the third thin film transistor  5603   c  are off. At this time, Data_j input to the wiring  5621 _J is input to the signal line Sj through the second thin film transistor  5603   b . In the third sub-selection period T 3 , the third thin film transistor  5603   c  is on, and the first thin film transistor  5603   a  and the second thin film transistor  5603   b  are off. At this time, Data_j+1 input to the wiring  5621 _J is input to the signal line Sj+1 through the third thin film transistor  5603   c.    
     As described above, in the signal line driver circuit of  FIG. 12 , to which the timing chart of  FIG. 14  is applied, the signal line can be precharged by providing the precharge period before the sub-selection periods. Thus, a video signal can be written to a pixel with high speed. Note that portions in  FIG. 14  which are similar to those in  FIG. 13  are denoted by the same reference numerals, and detailed description of the same portions or portions having similar functions is omitted. 
     Now, a constitution of the scan line driver circuit is described. The scan line driver circuit includes a shift register and a buffer. Also, a level shifter may be included in some cases. In the scan line driver circuit, when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register, a selection signal is produced. The generated selection signal is buffered and amplified by the buffer, and the resulting signal is supplied to a corresponding scan line. Gate electrodes of transistors in pixels corresponding to one line are connected to the scan line. Further, since the transistors in the pixels of one line have to be turned on at the same time, a buffer which can feed a large amount of current is used. 
     An example of a shift register used as part of the scan line driver circuit is described with reference to  FIG. 15  and  FIG. 16 . 
       FIG. 15  illustrates a circuit configuration of the shift register. The shift register shown in  FIG. 15  includes a plurality of flip-flops (flip-flops  5701 _ 1  to  5701 _ n ). Further, the shift register is operated by inputting a first clock signal, a second clock signal, a start pulse signal, and a reset signal. 
     Connection relationships of the shift register in  FIG. 15  are described. In the flip-flop  5701 _ i  (one of the flip-flops  5701 _ 1  to  5701 _ n ) of the i-th stage in the shift register of  FIG. 15 , a first wiring  5501  shown in  FIG. 16  is connected to a seventh wiring  5717 _ i −1; a second wiring  5502  shown in  FIG. 16  is connected to a seventh wiring  5717 _ i +1; a third wiring  5503  shown in  FIG. 16  is connected to a seventh wiring  5717 _ i ; and a sixth wiring  5506  shown in  FIG. 16  is connected to a fifth wiring  5715 . 
     Further, a fourth wiring  5504  shown in  FIG. 16  is connected to a second wiring  5712  in flip-flops of odd-numbered stages, and is connected to a third wiring  5713  in flip-flops of even-numbered stages. A fifth wiring  5505  shown in  FIG. 16  is connected to a fourth wiring  5714 . 
     Note that the first wiring  5501  shown in  FIG. 16  of the flip-flop  5701 _ 1  of a first stage is connected to a first wiring  5711 , and the second wiring  5502  shown in  FIG. 16  of the flip-flop  5701 _ n  of an n-th stage is connected to a sixth wiring  5716 . 
     The first wiring  5711 , the second wiring  5712 , the third wiring  5713 , and the sixth wiring  5716  may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. The fourth wiring  5714  and the fifth wiring  5715  may be referred to as a first power supply line and a second power supply line, respectively. 
       FIG. 16  illustrates the detail of the flip-flop shown in  FIG. 15 . A flip-flop shown in  FIG. 16  includes a first thin film transistor  5571 , a second thin film transistor  5572 , a third thin film transistor  5573 , a fourth thin film transistor  5574 , a fifth thin film transistor  5575 , a sixth thin film transistor  5576 , a seventh thin film transistor  5577 , and an eighth thin film transistor  5578 . Note that the first thin film transistor  5571 , the second thin film transistor  5572 , the third thin film transistor  5573 , the fourth thin film transistor  5574 , the fifth thin film transistor  5575 , the sixth thin film transistor  5576 , the seventh thin film transistor  5577 , and the eighth thin film transistor  5578  are n-channel transistors, and are brought into conduction when a voltage (V gs ) between a gate and a source exceeds a threshold voltage (V th ). 
     Now, a connection structure of the flip-flop shown in  FIG. 16  is described below. 
     A first electrode (one of a source electrode or a drain electrode) of the first thin film transistor  5571  is connected to the fourth wiring  5504 , and a second electrode (the other of the source electrode or the drain electrode) of the first thin film transistor  5571  is connected to the third wiring  5503 . 
     A first electrode of the second thin film transistor  5572  is connected to the sixth wiring  5506 . A second electrode of the second thin film transistor  5572  is connected to the third wiring  5503 . 
     A first electrode of the third thin film transistor  5573  is connected to the fifth wiring  5505 . A second electrode of the third thin film transistor  5573  is connected to a gate electrode of the second thin film transistor  5572 . A gate electrode of the third thin film transistor  5573  is connected to the fifth wiring  5505 . 
     A first electrode of the fourth thin film transistor  5574  is connected to the sixth wiring  5506 . A second electrode of the fourth thin film transistor  5574  is connected to the gate electrode of the second thin film transistor  5572 . A gate electrode of the fourth thin film transistor  5574  is connected to a gate electrode of the first thin film transistor  5571 . 
     A first electrode of the fifth thin film transistor  5575  is connected to the fifth wiring  5505 . A second electrode of the fifth thin film transistor  5575  is connected to the gate electrode of the first thin film transistor  5571 . A gate electrode of the fifth thin film transistor  5575  is connected to the first wiring  5501 . 
     A first electrode of the sixth thin film transistor  5576  is connected to the sixth wiring  5506 . A second electrode of the sixth thin film transistor  5576  is connected to the gate electrode of the first thin film transistor  5571 . A gate electrode of the sixth thin film transistor  5576  is connected to the gate electrode of the second thin film transistor  5572 . 
     A first electrode of the seventh thin film transistor  5577  is connected to the sixth wiring  5506 . A second electrode of the seventh thin film transistor  5577  is connected to the gate electrode of the first thin film transistor  5571 . A gate electrode of the seventh thin film transistor  5577  is connected to the second wiring  5502 . A first electrode of the eighth thin film transistor  5578  is connected to the sixth wiring  5506 . A second electrode of the eighth thin film transistor  5578  is connected to the gate electrode of the second thin film transistor  5572 . A gate electrode of the eighth thin film transistor  5578  is connected to the first wiring  5501 . 
     Note that the point at which the gate electrode of the first thin film transistor  5571 , the gate electrode of the fourth thin film transistor  5574 , the second electrode of the fifth thin film transistor  5575 , the second electrode of the sixth thin film transistor  5576 , and the second electrode of the seventh thin film transistor  5577  are connected is referred to as a node  5543 . The point at which the gate electrode of the second thin film transistor  5572 , the second electrode of the third thin film transistor  5573 , the second electrode of the fourth thin film transistor  5574 , the gate electrode of the sixth thin film transistor  5576 , and the second electrode of the eighth thin film transistor  5578  are connected is referred to as a node  5544 . 
     The first wiring  5501 , the second wiring  5502 , the third wiring  5503 , and the fourth wiring  5504  may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. The fifth wiring  5505  and the sixth wiring  5506  may be referred to as a first power supply line and a second power supply line, respectively. 
     Alternatively, the signal line driver circuit and the scan line driver circuit can be manufactured using only n-channel TFTs, which can be manufactured by a method similar to the method for manufacturing the non-linear element and together with the non-linear element described in Embodiment 2. Since the n-channel TFTs which can be formed by a method similar to the method for manufacturing the non-linear element described in Embodiment 2 have high mobility, the driving frequency of the driver circuits can be increased. Further, the n-channel TFTs which can be formed by a method similar to the method for manufacturing the non-linear element and together with the non-linear element described in Embodiment 2 include source regions or drain regions which are formed using an oxygen-deficiency oxide semiconductor layer including indium, gallium, and zinc. Therefore, the parasitic capacitance is decreased and the frequency characteristic (called f-characteristic) is increased. For example, the scan line driver circuit including the n-channel TFTs which can be formed by a method similar to the method for manufacturing the non-linear element and together with the non-linear element described in Embodiment 2 can operate at high speed; therefore, it is possible to increase the frame frequency or to achieve insertion of a black screen, for example. 
     In addition, when the channel width of the transistor in the scan line driver circuit is increased or a plurality of scan line driver circuits is provided, for example, higher frame frequency can be realized. When a plurality of scan line driver circuits is provided, a scan line driver circuit for driving even-numbered scan lines is provided on one side and a scan line driver circuit for driving odd-numbered scan lines is provided on the opposite side; thus, increase in frame frequency can be realized. 
     In the case of manufacturing an active matrix type light-emitting display device, which is an example of a semiconductor device to which an embodiment of the present invention is applied, a plurality of scan line driver circuits is preferably arranged because a plurality of thin film transistors is arranged in at least one pixel. An example of a block diagram of an active matrix light-emitting display device is illustrated in  FIG. 11B . 
     The light-emitting display device illustrated in  FIG. 11B  includes, over a substrate  5400 , a pixel portion  5401  including a plurality of pixels each provided with a display element; a first scan line driver circuit  5402  and a second scan line driver circuit  5404  that select each pixel; and a signal line driver circuit  5403  that controls a video signal input to a selected pixel. 
     In the case of inputting a digital video signal to the pixel of the light-emitting display device of  FIG. 11B , the pixel is put in a light-emitting state or non-light-emitting state by switching on/off of the transistor. Thus, grayscale can be displayed using an area ratio grayscale method or a time ratio grayscale method. An area ratio grayscale method refers to a driving method by which one pixel is divided into a plurality of subpixels and the respective subpixels are driven separately based on video signals so that grayscale is displayed. Further, a time ratio grayscale method refers to a driving method by which a period during which a pixel is in a light-emitting state is controlled so that grayscale is displayed. 
     Since the response time of light-emitting elements is shorter than that of liquid crystal elements or the like, the light-emitting elements are suitable for a time ratio grayscale method. Specifically, in the case of displaying by a time grayscale method, one frame period is divided into a plurality of subframe periods. Then, in accordance with video signals, the light-emitting element in the pixel is put in a light-emitting state or a non-light-emitting state in each subframe period. By dividing a frame into a plurality of subframes, the total length of time in which pixels actually emit light in one frame period can be controlled with video signals to display grayscales. 
     Note that in the light-emitting display device of  FIG. 11B , in the case where one pixel includes a switching TFT and a current control TFT, a signal which is input to a first scan line serving as a gate wiring of the switching TFT is generated from the first scan line driver circuit  5402  and a signal which is input to a second scan line serving as a gate wiring of the current control TFT is generated from the second scan line driver circuit  5404 . However, the signal which is input to the first scan line and the signal which is input to the second scan line may be generated together from one scan line driver circuit. In addition, for example, there is a possibility that a plurality of the first scan lines used for controlling the operation of the switching element be provided in each pixel depending on the number of transistors included in the switching element. In this case, the signals which are input to the plurality of the first scan lines may be generated all from one scan line driver circuit or may be generated from a plurality of scan line driver circuits. 
     Even in the light-emitting display device, part of the driver circuit which can be formed using the n-channel TFT can be provided over one substrate together with the thin film transistor of the pixel portion. Moreover, the signal line driver circuit and the scan line driver circuit can be manufactured using only the n-channel TFTs which can be formed by a method similar to the method for manufacturing the non-linear element and together with the non-linear element described in Embodiment 2. 
     The aforementioned driver circuit may be used for not only a liquid crystal display device or a light-emitting display device but also electronic paper in which electronic ink is driven by utilizing an element electrically connected to a switching element. The electronic paper is also called an electrophoretic display device (electrophoretic display) and has advantages in that it has the same level of readability as regular paper, it has less power consumption than other display devices, and it can be set to have a thin and light form. 
     There are a variety of modes of electrophoretic displays. The electrophoretic display is a device in which a plurality of microcapsules each including first particles having positive charge and second particles having negative charge are dispersed in a solvent or a solute, and an electrical field is applied to the microcapsules so that the particles in the microcapsules move in opposite directions from each other, and only a color of the particles gathered on one side is displayed. Note that the first particles or the second particles include a colorant, and does not move when there is not electric field. Also, a color of the first particles is different from a color of the second particles (the particles may also be colorless). 
     Thus, the electrophoretic display utilizes a so-called dielectrophoretic effect, in which a substance with high dielectric constant moves to a region with high electric field. The electrophoretic display does not require a polarizing plate and a counter substrate, which are necessary for a liquid crystal display device, so that the thickness and weight thereof are about half. 
     That which the microcapsules are dispersed in a solvent is called electronic ink, and this electronic ink can be printed on a surface of glass, plastic, fabric, paper, or the like. Color display is also possible with the use of a color filter or particles including a coloring matter. 
     In addition, an active matrix type display device can be completed by providing as appropriate, a plurality of the microcapsules over an active matrix substrate so as to be interposed between two electrodes, and can perform display by application of electric field to the microcapsules. For example, the active matrix substrate obtained using the thin film transistors which can be formed by a method similar to the method for manufacturing the non-linear element and together with the non-linear element described in Embodiment 2 can be used. 
     Note that the first particles and the second particles in the microcapsule may be formed from one of a conductive material, an insulating material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, and a magnetophoretic material or a composite material thereof. 
     According to Embodiment 4, the protective circuit is formed using the non-linear element including an oxide semiconductor. Thus, a display device having a structure suitable as a protective circuit can be provided. In the connection structure between the first oxide semiconductor layer of the non-linear element and the wiring layers, the provision of the region which is bonded with the second oxide semiconductor layer, which has higher electrical conductivity than the first oxide semiconductor layer, allows stable operation as compared with the case of using only metal wirings. Accordingly, a defect due to peeling of a thin film does not easily occur. In this manner, according to Embodiment 4, a display device with high reliability can be manufactured. 
     Embodiment 4 can be combined with the structure disclosed in another Embodiment as appropriate. 
     Embodiment 5 
     A thin film transistor can be manufactured together with a non-linear element according to an embodiment of the present invention, and the thin film transistor can be used for a pixel portion and further for a driver circuit, so that a semiconductor device having a display function (also called a display device) can be manufactured. Moreover, a thin film transistor and a non-linear element according to an embodiment of the present invention can be used for part of a driver circuit or an entire driver circuit formed over one substrate together with a pixel portion, so that a system-on-panel can be formed. 
     The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. A light-emitting element includes, in its scope, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic electroluminescent (EL) element, an organic EL element, and the like. Further, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used. 
     In addition, the display device includes a panel in which a display element is sealed, and a module in which an IC and the like including a controller are mounted on the panel. An embodiment of the present invention relates to one mode of an element substrate before the display element is completed in a process for manufacturing the display device, and the element substrate is provided with a means for supplying current to the display element in each of a plurality of pixels. Specifically, the element substrate may be in a state provided with only a pixel electrode of the display element, a state after a conductive film to be a pixel electrode is formed and before the conductive film is etched to form the pixel electrode, or any other states. 
     A display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Further, the display device includes any of the following modules in its category: a module including a connector such as an flexible printed circuit (FPC), a tape automated bonding (TAB) tape, or a tape carrier package (TCP); a module having a TAB tape or a TCP which is provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) which is directly mounted on a display element by a chip-on-glass (COG) method. 
     The appearance and a cross section of a liquid crystal display panel, which corresponds to one mode of a display device according to an embodiment of the present invention, will be described in Embodiment 5 with reference to  FIGS. 17A-1, 17A-2 and 17B . Each of  FIGS. 17A-1 and 17A-2  is a top view of a panel in which thin film transistors  4010  and  4011  with high electrical characteristics which can be manufactured by a method similar to the method for manufacturing the non-linear element and together with the non-linear element, and a liquid crystal element  4013  are sealed with a sealant  4005  between a first substrate  4001  and a second substrate  4006 .  FIG. 17B  corresponds to a cross section thereof along M-N of  FIGS. 17A-1 and 17A-2 . 
     The sealant  4005  is provided so as to surround a pixel portion  4002  and a scan line driver circuit  4004  which are provided over the first substrate  4001 . The second substrate  4006  is provided over the pixel portion  4002  and the scan line driver circuit  4004 . Thus, the pixel portion  4002  and the scan line driver circuit  4004  as well as a liquid crystal layer  4008  are sealed with the sealant  4005  between the first substrate  4001  and the second substrate  4006 . A signal line driver circuit  4003  that is formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate which is prepared separately is mounted in a region that is different from the region surrounded by the sealant  4005  over the first substrate  4001 . 
     Note that there is no particular limitation on a connection method of the driver circuit which is separately formed, and a known COG method, wire bonding method, TAB method, or the like can be used.  FIG. 17A-1  illustrates an example in which the signal line driver circuit  4003  is mounted by a COG method and  FIG. 17A-2  illustrates an example in which signal line driver circuit  4003  is mounted by a TAB method. 
     Each of the pixel portion  4002  and the scan line driver circuit  4004  which are provided over the first substrate  4001  includes a plurality of thin film transistors.  FIG. 17B  illustrates the thin film transistor  4010  included in the pixel portion  4002  and the thin film transistor  4011  included in the scan line driver circuit  4004 . Insulating layers  4020  and  4021  are provided over the thin film transistors  4010  and  4011 . 
     Each of the thin film transistors  4010  and  4011  has high electrical characteristics and includes a gate insulating layer on which plasma treatment has been performed, a source region and a drain region which include an IGZO semiconductor film of oxygen-deficiency type, a source electrode layer and a drain electrode layer which are in contact with the source region and the drain region respectively, and an IGZO semiconductor layer of oxygen-excess type which is in contact with the source region and the drain region. The thin film transistors  4010  and  4011  can be manufactured by a method similar to the method for manufacturing the non-linear element and together with the non-linear element described in Embodiment 2. In Embodiment 5, the thin film transistors  4010  and  4011  are n-channel thin film transistors. 
     A pixel electrode layer  4030  included in the liquid crystal element  4013  is electrically connected to the thin film transistor  4010 . A counter electrode layer  4031  of the liquid crystal element  4013  is formed on the second substrate  4006 . A portion where the pixel electrode layer  4030 , the counter electrode layer  4031 , and the liquid crystal layer  4008  overlap with each other corresponds to the liquid crystal element  4013 . Note that the pixel electrode layer  4030  and the counter electrode layer  4031  are provided with an insulating layer  4032  and an insulating layer  4033  serving as orientation films, respectively, and hold the liquid crystal layer  4008  with the insulating layers  4032  and  4033  interposed therebetween. 
     Note that the first substrate  4001  and the second substrate  4006  can be formed from glass, metal (typically, stainless steel), ceramic, or plastic. As plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used. In addition, a sheet with a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used. 
     A columnar spacer  4035 , which is formed by etching an insulating film selectively, is provided to control a distance (a cell gap) between the pixel electrode layer  4030  and the counter electrode layer  4031 . Alternatively, a spherical spacer may be used. 
     Alternatively, a blue phase liquid crystal without an orientation film may be used. A blue phase is a type of liquid crystal phase, which appears just before a cholesteric liquid crystal changes into an isotropic phase when the temperature of the cholesteric liquid crystal is increased. A blue phase appears only within narrow temperature range; therefore, the liquid crystal layer  4008  is formed using a liquid crystal composition in which a chiral agent of 5 wt. % or more is mixed in order to expand the temperature range. The liquid crystal composition including a blue phase liquid crystal and a chiral agent has a short response time of 10 μs to 100 μs, and is optically isotropic; therefore, orientation treatment is not necessary and viewing angle dependence is small. 
     Note that Embodiment 5 describes an example of a transmissive liquid crystal display device; however, an embodiment of the present invention can be applied to a reflective liquid crystal display device or a semi-transmissive liquid crystal display device. 
     Although a liquid crystal display device of Embodiment 5 has a polarizer provided outer than the substrate (the viewer side) and a color layer and an electrode layer of a display element provided inner than the substrate, which are arranged in that order, the polarizer may be inner than the substrate. The stacked structure of the polarizer and the color layer is not limited to that shown in Embodiment 5 and may be set as appropriate in accordance with the materials of the polarizer and the color layer and the condition of the manufacturing process. Further, a light-blocking film serving as a black matrix may be provided. 
     In Embodiment 5, in order to reduce the unevenness of the surface of the thin film transistors and to improve the reliability of the thin film transistors, the non-linear element described in Embodiment 2 and the thin film transistors which can be formed by a method similar to the method for manufacturing the non-linear element are covered with protective films or insulating layers (the insulating layers  4020  and  4021 ) serving as planarizing insulating films. Note that the protective film is provided to prevent entry of a contaminant impurity such as an organic substance, a metal substance, or moisture floating in the atmosphere, and therefore a dense film is preferable. The protective film may be formed using a single layer or a stack of layers of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film by a sputtering method. Although the protective film is formed by a sputtering method in Embodiment 5, the method is not limited to a particular method and may be selected from a variety of methods. 
     Here, the insulating layer  4020  is formed to have a stacked structure as the protective film. Here, a silicon oxide film is formed by a sputtering method as a first layer of the insulating layer  4020 . The use of a silicon oxide film for the protective film provides an advantageous effect of preventing hillock of an aluminum film used for a source electrode layer and a drain electrode layer. 
     Moreover, a silicon nitride film is formed by a sputtering method as a second layer of the insulating layer  4020 . When a silicon nitride film is used for the protective film, it is possible to prevent movable ions such as sodium from entering a semiconductor region to vary the electrical characteristics of the TFT. 
     Further, after the protective film is formed, the oxide semiconductor layer may be annealed (at 300° C. to 400° C.). 
     Further, the insulating layer  4021  is formed as the planarizing insulating film. The insulating layer  4021  can be formed from an organic material having heat resistance, such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. As an alternative to such organic materials, it is possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like. A siloxane-based resin may include as a substituent at least one of fluorine, an alkyl group, and an aryl group, as well as hydrogen. Note that the insulating layer  4021  may be formed by stacking a plurality of insulating films formed of these materials. 
     Note that a siloxane-based resin is a resin formed from a siloxane-based material as a starting material and having the bond of Si—O—Si. The siloxane-based resin may include as a substituent at least one of fluorine, an alkyl group, and aromatic hydrocarbon, as well as hydrogen. 
     The method for the formation of the insulating layer  4021  is not limited to a particular method and the following method can be used depending on the material of the insulating layer  4021 : a sputtering method, an SOG method, spin coating, dip coating, spray coating, a droplet discharge method (e.g., an inkjet method, screen printing, or offset printing), a doctor knife, a roll coater, a curtain coater, a knife coater, or the like. In the case of forming the insulating layer  4021  with the use of a material solution, annealing (300° C. to 400° C.) may be performed on the oxide semiconductor layer at the same time as a baking step. When the baking of the insulating layer  4021  and the annealing of the oxide semiconductor layer are performed at the same time, a semiconductor device can be manufactured efficiently. 
     The pixel electrode layer  4030  and the counter electrode layer  4031  can be formed from a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added. 
     A conductive composition including a conductive high molecule (also referred to as a conductive polymer) can be used for the pixel electrode layer  4030  and the counter electrode layer  4031 . The pixel electrode formed of the conductive composition has preferably a sheet resistance of 10000 ohm/square or less and a transmittance of 70% or more at a wavelength of 550 nm. Further, the resistivity of the conductive high molecule included in the conductive composition is preferably 0.1 Ω·cm or less. 
     As the conductive high molecule, a so-called t-electron conjugated conductive polymer can be used. As examples thereof, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more kinds of them, and the like can be given. 
     Further, a variety of signals and potentials are supplied from an FPC  4018  to the signal line driver circuit  4003  which is formed separately, the scan line driver circuit  4004 , and the pixel portion  4002 . 
     In Embodiment 5, a connecting terminal electrode  4015  is formed using the same conductive film as the pixel electrode layer  4030  included in the liquid crystal element  4013 . A terminal electrode  4016  is formed using the same conductive film as the source and drain electrode layers included in the thin film transistors  4010  and  4011 . 
     The connecting terminal electrode  4015  is electrically connected to a terminal of the FPC  4018  through an anisotropic conductive film  4019 . 
     Although  FIGS. 17A-1, 17A-2, and 17B  show an example in which the signal line driver circuit  4003  is formed separately and mounted on the first substrate  4001 , Embodiment 5 is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted. 
       FIG. 18  illustrates an example in which a liquid crystal display module is formed as a semiconductor device using a TFT substrate  2600  manufactured according to an embodiment of the present invention. 
       FIG. 18  illustrates an example of a liquid crystal display module, in which the TFT substrate  2600  and a counter substrate  2601  are fixed to each other with a sealant  2602 , and a pixel portion  2603  including a TFT and the like, a display element  2604  including a liquid crystal layer, and a color layer  2605  are provided between the substrates to form a display region. The color layer  2605  is necessary to perform color display. In the case of the RGB system, respective color layers corresponding to colors of red, green, and blue are provided for respective pixels. Polarizing plates  2606  and  2607  and a diffuser plate  2613  are provided outside the TFT substrate  2600  and the counter substrate  2601 . A light source includes a cold cathode tube  2610  and a reflective plate  2611 , and a circuit board  2612  is connected to a wiring circuit portion  2608  of the TFT substrate  2600  through a flexible wiring board  2609  and includes an external circuit such as a control circuit and a power source circuit. The polarizing plate and the liquid crystal layer may be stacked with a retardation plate interposed therebetween. 
     For the liquid crystal display module, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode or the like can be used. 
     According to Embodiment 5, a protective circuit is formed using a non-linear element including an oxide semiconductor; thus, a display device having a structure suitable as a protective circuit can be provided. In the connection structure between the first oxide semiconductor layer of the non-linear element and the wiring layers, the provision of the region which is bonded with the second oxide semiconductor layer, which has higher electrical conductivity than the first oxide semiconductor layer, allows stable operation as compared with the case of using only metal wirings. Moreover, a defect due to peeling of a thin film does not easily occur. In this manner, according to Embodiment 5, a liquid crystal display panel with high reliability can be manufactured. 
     Embodiment 5 can be combined with the structure disclosed in another Embodiment as appropriate. 
     Embodiment 6 
     Embodiment 6 describes an example of a light-emitting display device as a display device according to an embodiment of the present invention. As an example of a display element of the display device, here, a light-emitting element utilizing electroluminescence is used. Light-emitting elements utilizing electroluminescence are classified according to whether a light emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, the latter as an inorganic EL element. 
     In an organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and thus current flows. Then, those carriers (i.e., electrons and holes) are recombined, and thus, the light-emitting organic compound is excited. When the light-emitting organic compound returns to a ground state from the excited state, light is emitted. Owing to such a mechanism, such a light emitting element is referred to as a current-excitation light emitting element. 
     The inorganic EL elements are classified according to their element structures into a dispersion type inorganic EL element and a thin-film type inorganic EL element. A dispersion type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film type inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that an organic EL element is used as a light-emitting element in this example. 
       FIG. 19  illustrates an example of a pixel structure to which digital time grayscale driving can be applied, as an example of a semiconductor device to which an embodiment of the present invention is applied. 
     A structure and operation of a pixel to which digital time grayscale driving can be applied are described. In this example, one pixel includes two n-channel transistors in each of which a channel formation region includes a first oxide semiconductor layer and which can be formed by a method similar to the method for manufacturing the non-linear element described in Embodiment 2. 
     A pixel  6400  includes a switching transistor  6401 , a driver transistor  6402 , a light-emitting element  6404 , and a capacitor  6403 . A gate of the switching transistor  6401  is connected to a scan line  6406 , a first electrode (one of a source electrode and a drain electrode) of the switching transistor  6401  is connected to a signal line  6405 , and a second electrode (the other of the source electrode and the drain electrode) of the switching transistor  6401  is connected to a gate of the driver transistor  6402 . The gate of the driver transistor  6402  is connected to a power supply line  6407  through the capacitor  6403 , a first electrode of the driver transistor  6402  is connected to the power supply line  6407 , and a second electrode of the driver transistor  6402  is connected to a first electrode (pixel electrode) of the light-emitting element  6404 . A second electrode of the light-emitting element  6404  corresponds to a common electrode  6408 . 
     The second electrode (common electrode  6408 ) of the light-emitting element  6404  is set to a low power supply potential. The low power supply potential is a potential satisfying the low power supply potential &lt;a high power supply potential when the high power supply potential set to the power supply line  6407  is a reference. As the low power supply potential, GND, 0 V, or the like may be employed, for example. A potential difference between the high power supply potential and the low power supply potential is applied to the light-emitting element  6404  and current is supplied to the light-emitting element  6404 , so that the light-emitting element  6404  emits light. Here, in order to make the light-emitting element  6404  emit light by feed of current, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is greater than or equal to a forward threshold voltage. 
     Gate capacitance of the driver transistor  6402  may be used as a substitute for the capacitor  6403 , so that the capacitor  6403  can be omitted. The gate capacitance of the driver transistor  6402  may be formed between the channel region and the gate electrode. 
     In the case of a voltage-input voltage driving method, a video signal is input to the gate of the driver transistor  6402  so that the driver transistor  6402  is in either of two states of being sufficiently turned on and turned off That is, the driver transistor  6402  operates in a linear region. Since the driver transistor  6402  operates in a linear region, a voltage higher than the voltage of the power supply line  6407  is applied to the gate of the driver transistor  6402 . Note that a voltage higher than or equal to (voltage of the power supply line+Vth of the driver transistor  6402 ) is applied to the signal line  6405 . 
     In the case of performing analog grayscale driving instead of digital time grayscale driving, the same pixel structure as that in  FIG. 19  can be used by changing signal input. 
     In the case of performing analog grayscale driving, a voltage higher than or equal to (forward voltage of the light-emitting element  6404 +Vth of the driver transistor  6402 ) is applied to the gate of the driver transistor  6402 . The forward voltage of the light-emitting element  6404  indicates a voltage at which a desired luminance is obtained, and includes at least forward threshold voltage. The video signal by which the driver transistor  6402  operates in a saturation region is input, so that current can be supplied to the light-emitting element  6404 . In order for the driver transistor  6402  to operate in a saturation region, the potential of the power supply line  6407  is set higher than the gate potential of the driver transistor  6402 . When an analog video signal is used, it is possible to feed current to the light-emitting element  6404  in accordance with the video signal and perform analog grayscale driving. 
     The pixel structure shown in  FIG. 19  is not limited thereto. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added to the pixel shown in  FIG. 19 . 
     Next, structures of a light-emitting element are described with reference to  FIGS. 20A to 20C . A cross-sectional structure of a pixel is described here by taking an n-channel driver TFT as an example. Driver TFTs  7001 ,  7011 , and  7021  used for a semiconductor device, which are illustrated in  FIGS. 20A, 20B, and 20C , can be formed by a method similar to the method for manufacturing the non-linear element and together with the non-linear element described in Embodiment 2. The driver TFTs  7001 ,  7011 , and  7021  have high electrical characteristics and each include a gate insulating layer on which plasma treatment has been performed, a source region and a drain region which include an IGZO semiconductor film of oxygen-deficiency type, a source electrode layer and a drain electrode layer which are in contact with the source region and the drain region respectively, and an IGZO semiconductor layer of oxygen-excess type which is in contact with the source region and the drain region. 
     In addition, in order to extract light emitted from the light-emitting element, at least one of an anode and a cathode is required to transmit light. A thin film transistor and a light-emitting element are formed over a substrate. A light-emitting element can have a top-emission structure in which light emission is extracted through the surface opposite to the substrate; a bottom-emission structure in which light emission is extracted through the surface on the substrate side; or a dual-emission structure in which light emission is extracted through the surface opposite to the substrate and the surface on the substrate side. The pixel structure according to an embodiment of the present invention can be applied to a light-emitting element having any of these emission structures. 
     A light-emitting element with a top-emission structure is described with reference to  FIG. 20A . 
       FIG. 20A  is a cross-sectional view of a pixel in a case where the driver TFT  7001  is an n-channel TFT and light generated in a light-emitting element  7002  is emitted to an anode  7005  side with respect to a light-emitting layer  7004  (the side opposite to the substrate side). In  FIG. 20A , a cathode  7003  of the light-emitting element  7002  is electrically connected to the driver TFT  7001 , and the light-emitting layer  7004  and the anode  7005  are stacked in this order over the cathode  7003 . The cathode  7003  can be formed using any of a variety of conductive materials as long as it has a low work function and reflects light. For example, Ca, Al, CaF, MgAg, AlLi, or the like is preferably used. The light-emitting layer  7004  may be formed using a single layer or by stacking a plurality of layers. When the light-emitting layer  7004  is formed using a plurality of layers, the light-emitting layer  7004  is formed by stacking an electron-injecting layer, an electron-transporting layer, a light-emitting layer, a hole-transporting layer, and a hole-injecting layer in this order over the cathode  7003 . It is not necessary to form all of these layers. The anode  7005  is formed using a light-transmitting conductive film such as a film of indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide (hereinafter, referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added. 
     The light-emitting element  7002  corresponds to a region where the cathode  7003  and the anode  7005  sandwich the light-emitting layer  7004 . In the case of the pixel shown in  FIG. 20A , light is emitted from the light-emitting element  7002  to the anode  7005  side as indicated by an arrow. 
     Next, a light-emitting element having the bottom-emission structure is described with reference to  FIG. 20B .  FIG. 20B  is a cross-sectional view of a pixel in the case where a driver TFT  7011  is n-channel, and light is emitted from a light-emitting element  7012  to a cathode  7013  side with respect to a light-emitting layer  7014  (the substrate side). In  FIG. 20B , the cathode  7013  of the light-emitting element  7012  is formed over a light-transmitting conductive film  7017  which is electrically connected to the driver TFT  7011 , and the light-emitting layer  7014  and an anode  7015  are stacked in this order over the cathode  7013 . A light-blocking film  7016  for reflecting or blocking light may be formed so as to cover the anode  7015  when the anode  7015  has a light-transmitting property. For the cathode  7013 , a variety of materials can be used as in the case of  FIG. 20A  as long as the cathode  7013  is a conductive film having a low work function. Note that the cathode  7013  is formed to have a thickness that can transmit light (preferably, approximately from 5 nm to 30 nm). For example, an aluminum film with a thickness of 20 nm can be used as the cathode  7013 . The light-emitting layer  7014  may be formed of a single layer or by stacking a plurality of layers as in the case of  FIG. 20A . The anode  7015  is not required to transmit light, but can be formed using a light-transmitting conductive material as in the case of  FIG. 20A . For the light-blocking film  7016 , metal or the like that reflects light can be used; however, it is not limited to a metal film. For example, a resin or the like to which black pigment is added can be used. 
     The light-emitting element  7012  corresponds to a region where the cathode  7013  and the anode  7015  sandwich the light-emitting layer  7014 . In the case of the pixel shown in  FIG. 20B , light is emitted from the light-emitting element  7012  to the cathode  7013  side as indicated by an arrow. 
     Next, a light-emitting element having a dual-emission structure is described with reference to  FIG. 20C . In  FIG. 20C , a cathode  7023  of a light-emitting element  7022  is formed over a light-transmitting conductive film  7027  which is electrically connected to the driver TFT  7021 , and a light-emitting layer  7024  and an anode  7025  are stacked in this order over the cathode  7023 . As in the case of  FIG. 20A , the cathode  7023  can be formed of any of a variety of conductive materials as long as it is conductive and has low work function. Note that the cathode  7023  is formed to have a thickness that can transmit light. For example, an Al film having a thickness of 20 nm can be used as the cathode  7023 . The light-emitting layer  7024  may be formed using a single layer or by stacking a plurality of layers as in the case of  FIG. 20A . In a manner similar to  FIG. 20A , the anode  7025  can be formed using a light-transmitting conductive material. 
     The light-emitting element  7022  corresponds to a region where the cathode  7023 , the light-emitting layer  7024 , and the anode  7025  overlap with each other. In the pixel illustrated in  FIG. 20C , light is emitted from the light-emitting element  7022  to both the anode  7025  side and the cathode  7023  side as denoted by arrows. 
     Although an organic EL element is described here as a light-emitting element, an inorganic EL element can be alternatively provided as a light-emitting element. 
     Note that Embodiment 6 describes the example in which a thin film transistor (driver TFT) which controls the driving of a light-emitting element is electrically connected to the light-emitting element, but a structure may be employed in which a current control TFT is connected between the driver TFT and the light-emitting element. 
     The semiconductor device described in Embodiment 6 is not limited to the structures illustrated in  FIGS. 20A to 20C , and can be modified in various ways based on the spirit of techniques according to the present invention. 
     Next, the appearance and cross section of a light-emitting display panel (also referred to as a light-emitting panel) which corresponds to one mode of a semiconductor device according to the present invention will be described with reference to  FIGS. 21A and 21B .  FIG. 21A  is a top view of a panel in which a light-emitting element and a thin film transistor having high electrical characteristics that can be manufactured over a first substrate by a method similar to the method for manufacturing a non-linear element and together with the non-linear element according to an embodiment of the present invention is sealed between the first substrate and a second substrate with a sealant, and 
       FIG. 21B  is a cross-sectional view along H-I of  FIG. 21A . 
     A sealant  4505  is provided so as to surround a pixel portion  4502 , signal line driver circuits  4503   a  and  4503   b , and scan line driver circuits  4504   a  and  4504   b , which are provided over a first substrate  4501 . In addition, a second substrate  4506  is formed over the pixel portion  4502 , the signal line driver circuits  4503   a  and  4503   b , and the scan line driver circuits  4504   a  and  4504   b . Accordingly, the pixel portion  4502 , the signal line driver circuits  4503   a  and  4503   b , and the scan line driver circuits  4504   a  and  4504   b  are sealed, together with filler  4507 , with the first substrate  4501 , the sealant  4505 , and the second substrate  4506 . In this manner, it is preferable that the pixel portion  4502 , the signal line driver circuits  4503   a  and  4503   b , and the scan line driver circuits  4504   a  and  4504   b  be packaged (sealed) with a protective film (such as an attachment film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the pixel portion  4502 , the signal line driver circuits  4503   a  and  4503   b , and the scan line driver circuits  4504   a  and  4504   b  are not exposed to external air. 
     The pixel portion  4502 , the signal line driver circuits  4503   a  and  4503   b , and the scan line driver circuits  4504   a  and  4504   b  formed over the first substrate  4501  each include a plurality of thin film transistors, and the thin film transistor  4510  included in the pixel portion  4502  and the thin film transistor  4509  included in the signal line driver circuit  4503   a  are illustrated as an example in  FIG. 21B . 
     Each of the thin film transistors  4509  and  4510  has high electrical characteristics and includes a gate insulating layer on which plasma treatment has been performed, a source region and a drain region which are formed using an IGZO semiconductor film of oxygen-deficiency type, a source electrode layer and a drain electrode layer which are in contact with the source region and the drain region respectively, and an IGZO semiconductor layer of oxygen-excess type which is in contact with the source region and the drain region. The thin film transistors  4509  and  4510  can be manufactured in a manner similar to the method for manufacturing the non-linear element and together with the non-linear element described in Embodiment 2. In Embodiment 6, the thin film transistors  4509  and  4510  are n-channel thin film transistors. 
     Moreover, reference numeral  4511  denotes a light-emitting element. A first electrode layer  4517  which is a pixel electrode included in the light-emitting element  4511  is electrically connected to source and drain electrode layers of the thin film transistor  4510 . Note that although the light-emitting element  4511  has a stacked structure of the first electrode layer  4517 , an electroluminescent layer  4512 , and a second electrode layer  4513 , the structure of the light-emitting element  4511  is not limited to the structure shown in Embodiment 6. The structure of the light-emitting element  4511  can be changed as appropriate depending on a direction in which light is extracted from the light-emitting element  4511 , or the like. 
     A partition wall  4520  is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that the partition wall  4520  be formed using a photosensitive material to have an opening portion on the first electrode layer  4517  so that a sidewall of the opening portion is formed as a tilted surface with continuous curvature. 
     The electroluminescent layer  4512  may be formed using a single layer or a plurality of layers stacked. 
     In order to prevent entry of oxygen, hydrogen, moisture, carbon dioxide, or the like into the light-emitting element  4511 , a protective film may be formed over the second electrode layer  4513  and the partition wall  4520 . As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC (diamond like carbon) film, or the like can be formed. 
     In addition, a variety of signals and potentials are supplied from FPCs  4518   a  and  4518   b  to the signal line driver circuits  4503   a  and  4503   b , the scan line driver circuits  4504   a  and  4504   b , or the pixel portion  4502 . 
     In Embodiment 6, a connecting terminal electrode  4515  is formed using the same conductive film as the first electrode layer  4517  included in the light-emitting element  4511 . A terminal electrode  4516  is formed using the same conductive film as the source and drain electrode layers included in the thin film transistors  4509  and  4510 . 
     The connecting terminal electrode  4515  is electrically connected to a terminal included in the FPC  4518   a  through an anisotropic conductive film  4519 . 
     The second substrate  4506  located in the direction in which light is extracted from the light-emitting element  4511  needs to have a light-transmitting property. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used. 
     As the filler  4507 , an ultraviolet curable resin or a thermosetting resin as well as inert gas such as nitrogen or argon can be used. For example, polyvinyl chloride (PVC), acrylic, polyimide, an epoxy resin, a silicone resin, polyvinyl butyral (PVB), or ethylene vinyl acetate (EVA) can be used. In Embodiment 6, nitrogen is used for the filler  4507 . 
     In addition, if needed, optical films such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retarder plate (a quarter-wave plate, a half-wave plate), and a color filter may be provided on an emission surface of the light-emitting element, as appropriate. Further, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment can be performed by which reflected light is diffused in the depression/projection of the surface and glare can be reduced. 
     As the signal line driver circuits  4503   a  and  4503   b  and the scan line driver circuits  4504   a  and  4504   b , driver circuits formed by using a single crystal semiconductor film or polycrystalline semiconductor film over a substrate separately prepared may be mounted. In addition, only the signal line driver circuit or only part thereof, or only the scan line driver circuit or only part thereof may be separately formed to be mounted. 
     Embodiment 6 is not limited to the structure shown in  FIGS. 21A and 21B . 
     According to Embodiment 6, a protective circuit is formed using a non-linear element including an oxide semiconductor; thus, a display device having a structure suitable as a protective circuit can be provided. In the connection structure between the first oxide semiconductor layer of the non-linear element and the wiring layers, the provision of the region which is bonded with the second oxide semiconductor layer, which has higher electrical conductivity than the first oxide semiconductor layer, allows stable operation as compared with the case of using only metal wirings. Moreover, a defect due to peeling of a thin film does not easily occur. In this manner, according to Embodiment 6, a light-emitting display device (display panel) with high reliability can be manufactured. 
     Embodiment 6 can be combined with the structure disclosed in another Embodiment as appropriate. 
     Embodiment 7 
     A display device according to an embodiment of the present invention can be applied as electronic paper. Electronic paper can be used for electronic appliances of every field for displaying information. For example, electronic paper can be used for electronic book (e-book), posters, advertisement in vehicles such as trains, display in a variety of cards such as credit cards, and so on. Examples of such electronic appliances are illustrated in  FIGS. 22A and 22B  and  FIG. 23 . 
       FIG. 22A  illustrates a poster  2631  formed using electronic paper. If the advertizing medium is printed paper, the advertisement is replaced by manpower; however, when electronic paper to which an embodiment of the present invention is applied is used, the advertisement display can be changed in a short time. Moreover, a stable image can be obtained without display deterioration. Further, the poster may send and receive information wirelessly. 
       FIG. 22B  illustrates an advertisement  2632  in a vehicle such as a train. If the advertizing medium is printed paper, the advertisement is replaced by manpower; however, when electronic paper to which an embodiment of the present invention is applied is used, the advertisement display can be changed in a short time without much manpower. Moreover, a stable image can be obtained without display deterioration. Further, the advertisement in vehicles may send and receive information wirelessly. 
       FIG. 23  illustrates an example of an electronic book device  2700 . For example, the electronic book device  2700  includes two housings  2701  and  2703 . The housings  2701  and  2703  are bound with each other by an axis portion  2711 , along which the electronic book device  2700  is opened and closed. With such a structure, operation as a paper book is achieved. 
     A display portion  2705  is incorporated in the housing  2701  and a display portion  2707  is incorporated in the housing  2703 . The display portion  2705  and the display portion  2707  may display a series of images, or may display different images. In the structure where different images are displayed in different display portions, for example, the right display portion (the display portion  2705  in  FIG. 23 ) displays text and the left display portion (the display portion  2707  in  FIG. 23 ) displays images. 
       FIG. 23  illustrates an example in which the housing  2701  is provided with an operation portion and the like. For example, the housing  2701  is provided with a power supply  2721 , an operation key  2723 , a speaker  2725 , and the like. The page can be turned with the operation key  2723 . Note that a keyboard, a pointing device, and the like may be provided on the same plane as the display portion of the housing. Further, a rear surface or a side surface of the housing may be provided with an external connection terminal (an earphone terminal, a USB terminal, a terminal which can be connected with a variety of cables such as an AC adopter or a USB cable, and the like), a storage medium inserting portion, or the like. Moreover, the electronic book device  2700  may have a function of an electronic dictionary. 
     Further, the electronic book device  2700  may send and receive information wirelessly. Desired book data can be purchased and downloaded from an electronic book server wirelessly. 
     As described in Embodiment 7, when a display device including a protective circuit whose function has been improved by the use of a non-linear element including an oxide semiconductor and whose operation has been made stable is mounted on an electronic appliance, it is possible to manufacture an electronic appliance including a display device with high reliability, on which a protective circuit including a non-linear element in which a defect due to peeling of a thin film does not easily occur is mounted. 
     Embodiment 7 can be combined with the structure disclosed in another Embodiment as appropriate. 
     Embodiment 8 
     A semiconductor device according to an embodiment of the present invention can be applied to a variety of electronic appliances (including game machines). As the electronic appliances, there are, for example, a television device (also called TV or a television receiver), a monitor for a computer or the like, a digital camera, a digital video camera, a digital photo frame, a cellular phone (also called a mobile phone or a portable telephone device), a portable game machine, a portable information terminal, an audio playback device, and a large game machine such as a pachinko machine. 
       FIG. 24A  illustrates an example of a television device  9600 . A display portion  9603  is incorporated in a housing  9601  of the television device  9600 . The display portion  9603  can display images. Here, the housing  9601  is supported on a stand  9605 . 
     The television device  9600  can be operated by an operation switch of the housing  9601  or a separate remote controller  9610 . The channel and volume can be controlled with operation keys  9609  of the remote controller  9610  and the images displayed in the display portion  9603  can be controlled. Moreover, the remote controller  9610  may have a display portion  9607  in which the information outgoing from the remote controller  9610  is displayed. 
     Note that the television device  9600  is provided with a receiver, a modem, and the like. With the use of the receiver, general television broadcasting can be received. Moreover, when the display device is connected to a communication network with or without wires via the modem, one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers) information communication can be performed. 
       FIG. 24B  illustrates an example of a digital photo frame  9700 . For example, a display portion  9703  is incorporated in a housing  9701  of the digital photo frame  9700 . The display portion  9703  can display a variety of images, for example, displays image data taken with a digital camera or the like, so that the digital photo frame can function in a manner similar to a general picture frame. 
     Note that the digital photo frame  9700  is provided with an operation portion, an external connection terminal (such as a USB terminal or a terminal which can be connected to a variety of cables including a USB cable), a storage medium inserting portion, and the like. These structures may be incorporated on the same plane as the display portion; however, they are preferably provided on the side surface or rear surface of the display portion because the design is improved. For example, a memory including image data taken with a digital camera is inserted into the storage medium inserting portion of the digital photo frame and the image data is imported. Then, the imported image data can be displayed in the display portion  9703 . 
     The digital photo frame  9700  may send and receive information wirelessly. In this case, desired image data can be wirelessly imported into the digital photo frame  9700  and can be displayed therein. 
       FIG. 25A  illustrates a portable game machine including a housing  9881  and a housing  9891  which are jointed with a connector  9893  so as to be able to open and close. A display portion  9882  and a display portion  9883  are incorporated in the housing  9881  and the housing  9891 , respectively. The portable game machine illustrated in  FIG. 25A  additionally includes a speaker portion  9884 , a storage medium inserting portion  9886 , an LED lamp  9890 , an input means (operation keys  9885 , a connection terminal  9887 , a sensor  9888  (including a function of measuring force, displacement, position, speed, acceleration, angular speed, the number of rotations, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, tilt angle, vibration, smell, or infrared ray), a microphone  9889 , and the like). Needless to say, the structure of the portable game machine is not limited to the above, and may be any structure as long as a semiconductor device according to an embodiment of the present invention is provided. Moreover, another accessory may be provided as appropriate. The portable game machine shown in  FIG. 25A  has a function of reading out a program or data stored in a storage medium to display it on the display portion, and a function of sharing information with another portable game machine by wireless communication. The portable game machine in  FIG. 25A  can have a variety of functions other than those above. 
       FIG. 25B  illustrates an example of a slot machine  9900 , which is a large game machine. A display portion  9903  is incorporated in a housing  9901  of the slot machine  9900 . The slot machine  9900  additionally includes an operation means such as a start lever or a stop switch, a coin slot, a speaker, and the like. Needless to say, the structure of the slot machine  9900  is not limited to the above, and may be any structure as long as at least a semiconductor device according to an embodiment of the present invention is provided. Moreover, another accessory may be provided as appropriate. 
       FIG. 26  illustrates an example of a cellular phone  1000 . The cellular phone  1000  includes a housing  1001  in which a display portion  1002  is incorporated, and moreover includes an operation button  1003 , an external connection port  1004 , a speaker  1005 , a microphone  1006 , and the like. 
     Information can be input to the cellular phone  1000  illustrated in  FIG. 26  by touching the display portion  1002  with a finger or the like. Moreover, making a call or text messaging can be performed by touching the display portion  1002  with a finger or the like. 
     There are mainly three screen modes of the display portion  1002 . The first mode is a display mode mainly for displaying an image. The second mode is an input mode mainly for inputting information such as text. The third mode is a display-and-input mode in which two modes of the display mode and the input mode are mixed. 
     For example, in the case of making a call or text messaging, the display portion  1002  is set to a text input mode where text input is mainly performed, and text input operation can be performed on a screen. In this case, it is preferable to display a keyboard or number buttons on almost the entire screen of the display portion  1002 . 
     When a detection device including a sensor for detecting inclination, such as a gyroscope or an acceleration sensor, is provided inside the cellular phone  1000 , display in the screen of the display portion  1002  can be automatically switched by judging the direction of the cellular phone  1000  (whether the cellular phone  1000  is placed horizontally or vertically for a landscape mode or a portrait mode). 
     Further, the screen modes are switched by touching the display portion  1002  or operating the operation button  1003  of the housing  1001 . Alternatively, the screen modes can be switched depending on kinds of images displayed in the display portion  1002 . For example, when a signal for an image displayed in the display portion is data of moving images, the screen mode is switched to the display mode. When the signal is text data, the screen mode is switched to the input mode. 
     Moreover, in the input mode, when input by touching the display portion  1002  is not performed within a specified period while a signal detected by an optical sensor in the display portion  1002  is detected, the screen mode may be controlled so as to be switched from the input mode to the display mode. 
     The display portion  1002  can also function as an image sensor. For example, an image of a palm print, a fingerprint, or the like is taken by touching the display portion  1002  with the palm or the finger, whereby personal authentication can be performed. Moreover, when a backlight which emits near-infrared light or a sensing light source which emits near-infrared light is provided in the display portion, a finger vein, a palm vein, or the like can be taken. 
     As described in Embodiment 8, when a display device including a protective circuit whose function has been improved by the use of a non-linear element including an oxide semiconductor and whose operation has been made stable is mounted on an electronic appliance, it is possible to manufacture an electronic appliance including a display device with high reliability, on which a protective circuit including a non-linear element in which a defect due to peeling of a thin film does not easily occur is mounted. 
     Embodiment 8 can be combined with the structure disclosed in another Embodiment as appropriate. 
     This application is based on Japanese Patent Application serial no. 2008-235105 filed with Japan Patent Office on Sep. 12, 2008, the entire contents of which are hereby incorporated by reference.