Patent Publication Number: US-7723193-B2

Title: Method of forming an at least penta-sided-channel type of FinFET transistor

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a divisional of, and claims priority under 35 U.S.C. §120 to application Ser. No. 10/986,018 filed on Nov. 12, 2004 now U.S. Pat. No. 7,385,247, which claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2004-3568 filed on Jan. 17, 2004 in the Korean Intellectual Property Office, the entire contents of both of which are incorporated herein by reference. 

   BACKGROUND OF THE PRESENT INVENTION 
   The need to reduce transistor size is a perennial problem to be solved in the art of integrated circuits. One way that the Background Art reduced transistor size was to reduce the length of the channel. Doing so effectively reduced the overall footprint of the transistor. But then a minimum channel length (relative to other physical parameters of the transistor) was achieved below which problems were created, e.g., short channel effects. 
   The Background Art responded by developing a transistor architecture that reduced the transistor&#39;s footprint size while maintaining at least the minimum channel length. The solution can be explained via analogy to an inchworm.  FIGS. 5A-5B  are side views that depict stages of the peculiar form of locomotion used by an inchworm  602 . In  FIG. 5A , a head  604  and a tail  606  of inchworm  602  are close together while a middle section  608  thereof is hunched upward (or, in other words, folded almost in half). In  FIG. 5B , inchworm  602  has moved its head  604  forward while keeping its tail  606  in the same position as in  FIG. 5A , which causes middle section  608  to be stretched horizontally relative to  FIG. 5A . In  FIG. 5C , inchworm  602  has kept its head  604  in the same position as in  FIG. 5B , but has moved its tail  606  to again be located near its head  604 . As such, inchworm  602  has adopted in  FIG. 5C  the same posture as in  FIG. 5A . 
   The larger footprint transistor architecture according to the Background Art is analogous to the posture of inchworm  602  in  FIG. 5B , where the channel corresponds to the horizontally stretched middle section  608  of inchworm  602 . The smaller footprint transistor architecture according to the Background Art is analogous to the posture of inchworm  602  in  FIGS. 5A and 5C , where the channel corresponds to the hunched-upward or folded middle section  608 . 
     FIG. 6  is a three-quarter perspective view of the smaller footprint architecture according to the Background Art, which is generally referred to as a FinFET and particularly here as a triple gate FinFET  700 , i.e., FET having a channel in the shape of a fin  702   b  (obscured in  FIG. 6  but see  FIG. 7 ) formed on a buried oxide (BOX) structure  701  between a source region  702   a  and a drain region  702 C. Gate electrode  706  conforms (as does interposed gate oxide layer  704 ) to the shape of channel  704   
     FIG. 7  is a cross-sectional view of Background Art FinFET  700  taken along line VII-VII′ of  FIG. 6 . Recall that the inversion layer induced in a channel is located next to gate oxide  704  and tends to be rather shallow. An idealized effect of the fin-shaped channel  704  gate electrode  706  is as if three separate inversion layers are induced, namely a first inversion layer  708   a , a second inversion layer  708   b  and a third inversion layer  708 C. Hence, FinFET  700  is referred to as a triple-gate FinFET. 
     FIGS. 8A-8B  are cross-sectional views of two stages in the manufacture of a multi-gate FinFET according to the Background Art. More particularly,  FIGS. 8A-8B  depict stages in the formation of the fin of the FinFET. In  FIG. 8A , a silicon layer  220  is formed on a buried oxide (BOX) structure  210 , which is formed on a silicon substrate  220 . A silicon plug  810  is formed to fill an opening in oxide layer  510 . Plug  810  is grown by selective epitaxial growth (SEG). In  FIG. 8B , the portion of plug  810  extending above oxide  510  has been removed by CMP. 
   Returning to  FIG. 7 , as a practical matter, the electrostatic field induced by a voltage on gate electrode, e.g.,  706 , is not uniform along gate electrode  706 . Rather, the electrostatic field tends to be concentrated in the corners, as indicated by the shaded regions  710   a  and  710   b  in  FIG. 7 . Consequently, inversion layers form in the corners before forming all along gate electrode  706 . This lowers a threshold voltage for the corners relative to the sides, leading to higher current flow at the corners and generally non-uniform performance of the FinFET. 
   The Background Art recognized that such a corner phenomenon could be mitigated if the corners could be rounded. Accordingly, efforts have been made to remove material from the substantially square corners, e.g., by dry etching, in order to achieve an approximation of rounded corners. Despite many attempts, the Background Art has not been able to develop a technique to remove material from square corners of triple-gate FinFET  700  (or a double-gate version thereof that does not irreparably damage the remaining portion of fin  702   b  or result in a non-uniform width thereof. 
   SUMMARY OF THE PRESENT INVENTION 
   At least one embodiment of the present invention provides an at least penta-sided-channel type of FinFET transistor. Such a FinFET may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, where at least the channel, in cross-section transverse to the long dimension, has at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator. 
   At least one other embodiment of the present invention provides a method of forming an at least penta-sided-channel type of FinFET transistor. Such a method may include: providing a base; forming a fin on the base; epitaxially growing a body of semiconductor material, which includes a channel region, on the base, where at least the channel region, in cross-section transverse to a long dimension of the body, having five or more planar surfaces above the base; selectively doping the semiconductor body to produce, in the long dimension, source/drain regions sandwiching the channel region, forming a gate insulator on the channel region of the body; and forming a gate electrode formed on the gate insulator. 
   Additional features and advantages of the invention will be more fully apparent from the following detailed description of example embodiments, the accompanying drawings and the associated claims. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be described more fully with reference to the accompanying drawings, in which example embodiments of the present invention are shown. 
     Those figures not labeled as Background Art are intended to depict example embodiments of the present invention and should not be interpreted to limit the scope thereof. In the figures, the relative thicknesses and positioning of layers or regions may be reduced or exaggerated for clarity. In other words, the figures are not drawn to scale. Further, a layer is considered as being formed “on” another layer or a substrate when formed either directly on the referenced layer or the substrate or formed on other layers or patterns overlaying the referenced layer. 
     It should be understood that example embodiments of the present invention described herein can be modified in form and detail without departing from the spirit and scope of the invention. Accordingly, the embodiments described herein are provided by way of example and not of limitation, and the scope of the present invention is not restricted to the particular embodiments described herein. 
       FIG. 1  is a three-quarter perspective view of an at least penta-sided-channel type of FinFET transistor, according to at least one embodiment of the present invention. 
       FIG. 2A  is a cross-sectional view (taken along line II-II′ of  FIG. 1 ) of a first variety  1   a  of FinFET transistor  1 , according to at least one other embodiment of the present invention. 
       FIGS. 2B-2E  are cross-sectional views (also taken along line II-II′ of  FIG. 1 ) of other varieties  1 X (where Xε{B,C,D,E}) of FinFET transistor  1 , according to other embodiments of the present invention, respectively. 
       FIGS. 3A-3H  are cross-sectional views (from the same perspective of  FIG. 2B ) that depict various stages of a method, according to at least one embodiment of the present invention, of making the FinFET of  FIG. 2B . 
       FIGS. 4A-4C  are cross-sectional views (from the same perspective of  FIG. 2E ) that depict various stages of a method, according to at least one embodiment of the present invention, of making the FinFET of  FIG. 2E . 
       FIGS. 5A-5C  are side views that depict stages of the peculiar form of locomotion used by an inchworm, which are presented as background information for an analogy to a FinFET according to the Background Art. 
       FIG. 6  is a three-quarter perspective view of a FinFET according to the Background Art. 
       FIG. 7  is a cross-sectional view of the Background Art FinFET of  FIG. 6 , taken along line VII-VII′. 
       FIGS. 8A-8B  are cross-sectional views of two stages in the manufacture of a multi-gate FinFET, according to the Background Art. 
   

   DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS 
   In developing the present invention, the following problem with the Background Art was recognized and a path to a solution identified. The Background Art assumes that mitigation (by rounded-corner approximation) of the problematic corner effect (again, caused by substantially square corners of the fin-shaped channel) of a Background Art FinFET can only be accomplished subtractively by removing material representing the substantially square portion of the corners. It is now recognized that an obtuse angle significantly larger than 90° can significantly reduce the corner effect. Such an obtuse angle approximates the rounding of corners, but can be achieved additively by growing the fin rather than subtractively by removing material from a fin having substantially square corners. For example, epitaxial growth of silicon can achieve the desired approximation of a rounded-corner fin without the negative consequential effects upon other aspects of the inchoate FinFET that are consequences of the Background Art techniques for subtractively approximating rounded corners of a fin. At least one embodiment of the present invention provides a multiple sided channel FinFET having approximated rounded corners for the fin-shaped body (in which the channel is induced) by additively constructing, e.g., growing, a body of semiconductor material into the desired shape. 
     FIG. 1  is a three-quarter perspective view of an at least penta-sided-channel type of FinFET transistor  1 , according to at least one embodiment of the present invention.  FIG. 2A  is a cross-sectional view (taken along line II-II′ of  FIG. 1 ) of a first variety  1   a  of at least the penta-sided-channel-type FinFET transistor  1 , according to at least one other embodiment of the present invention.  FIGS. 2B-2E  are cross-sectional views (also taken along line II-II′ of  FIG. 1 ) of other varieties  1 X (where Xε{B,C,D,E}) of FinFET transistor  1 , according to other embodiments of the present invention, respectively, that will be discussed below. 
   Transistor  1  includes: a substrate  10 ; an isolation region  12 ; a fin  14  (obscured in  FIG. 1 , but see, e.g.,  FIG. 2A ); a body  20  of semiconductor material, the body having two substantially vertical (relative to substantially horizontal isolation region  12 ) facets  22 , a substantially horizontal facet  24 , and two beveled (again, relative to isolation region  12 ) facets  26 ; a channel  28  (obscured in  FIG. 1 , but see, e.g.,  FIG. 2A ); a gate insulating layer  40 ; source/drain regions  44 ; a gate electrode  50  having two instances of a first gate regions  50   a , two instances of a second gate region  50   b , and one instance of a third gate region  50   c.    
   In  FIG. 2A , a penta-sided inversion layer (or, in other words, a penta-sided channel) is induced in the mushroom-shaped portion  20   a  of body  20  of FinFET transistor  1   a . In the cross-sectional perspective of  FIG. 2A  (and  FIGS. 2B-2E  as well), it is to be noted that channel  20   a  is depicted as being transverse to a long dimension of body  20 , where body  20  also contains source/drain regions  44 . Portion  20   a  of body  20  has a penta-sided head portion  27   p  (where the suffix “p” is suggestive of the prefix penta-) and a stalk portion  29 A. Stalk portion  29 A extends down into and fills a recess defined by sidewalls  12 L and  12 R of isolation region  12  and an upper surface  14   u  of fin  14 . As part of body  20 , penta-sided head portion  27   p  exhibits five facets that can be described as being located above isolation region  12 , namely: two instances of substantially vertical facet  22 ; one instance of substantially horizontal facet  24 ; and two instances of beveled facet  26 . The five gate electrode regions  50   a ,  50   b ,  50   c ,  50   b  and  50   a  can induce five inversion regions in body  20   a , which in effect represent five channels. Obtuse angles between facets  22  &amp;  26  and  26  &amp;  24  are substantially greater, respectively, than the 90° angles exhibited by the corners according to Background Art FinFET  700 , hence the problems associated with the corner effect are at least substantially reduced. 
   Substrate  10  can include, e.g., one or more of {100} bulk Si, Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, InP, etc. Semiconductor body  20  can include, e.g., one or more of Si, Ge, SiGe, SiC, SiGeC, etc. (discussed further below). Gate insulating layer  40  can include, e.g., one or more of SiO2, SiON, Si 3 N 4 , Ge x O y N z , Ge x Si y O z , high-k metal oxide (e.g., HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , Ta 2 O 5 , etc.), etc. or a stacked structure thereof. And gate  50  can include one or more of doped poly-Si, metal (e.g., Al, W, Pt, etc.), metal nitride (e.g., TiN) metal (e.g., Co, Ni, Ti, Hf, Pt) silicide alloy, etc. or a stacked structure thereof. 
     FIG. 2B  is a cross-sectional view (again, taken along line II-II′ of  FIG. 1 ) of a second variety  1   b  of at the at-least-penta-sided-channel-type FinFET transistor  1 , according to at least one other embodiment of the present invention. FinFET  1   b  is similar to FinFET  1   a , so minimal discussion of similarities is presented for the sake of brevity. For example, while stalk portion  29   a  of FinFET  1   a  is substantially rectangular in cross-section, stalk  29   b  of FinFET  1   b  is tapered by contrast. Sidewall spacers  60  partially fill the recess defined by sidewalls of isolation region  12  and upper surface  14   u  of fin  14 . However, a portion of upper surface  14   u  is not covered by sidewall spacers  60 , but instead is covered by the smaller end of stalk portion  29 A. 
   The five facets of head portion  27   p  of FinFETs  1   a  and  1   b  are obtained by growing bodies  20   a  and  20   b , e.g., via selective epitaxial growth (SEG). Faceting morphology of head portion  27   p , in terms of Miller indices, can include: horizontal facet  24  exhibiting plane ( 100 ); and beveled facets  26  exhibiting plane ( 311 ) or ( 111 ). Together, the five facets define a silhouette in  FIG. 2B  (and  FIG. 2A ) that approximates a fin having substantially rounded corners, as contrasted with fin  702   b  according to the Background Art. In other words, above isolation region  12 , head portion  27   p  has a polygonal silhouette having five or more sides. 
     FIGS. 3A-3H  are cross-sectional views (from the same perspective of  FIG. 2B ) that depict various stages of a method, according to at least one embodiment of the present invention, of making FinFET  1   b . In  FIG. 3A , substrate  10  as been provided. An oxide layer  102  has been formed on substrate  10 . A silicon nitride layer  104  has been formed on oxide layer  102 . Together, layers  102  and  104  define a mask layer  105 . A photo-resist (PR) material has been deposited on mask layer  105  and patterned into PR pattern  106 . 
   Between what is depicted in  FIGS. 3A and 3B , mask layer  105  is selectively removed everywhere except for underneath PR pattern  106 . Then PR pattern  106  is itself removed.  FIG. 3B  depicts what remains thereafter, namely a mask  105   a  formed of layer segments  104   a  and  102   a . Next, in  FIG. 3C , portions of substrate  10  have been selectively removed, causing substrate  10  to take on an inverted-T shape having a horizontal portion and fin  14  extending perpendicularly therefrom. As a result, one or more trenches T have been formed above the horizontal portion of substrate  10  and around the sides of fin  14 . 
   In  FIG. 3D , isolation region  112  has been formed, e.g., by deposition of material to fill one or more trenches T. Also, optionally, isolation region  112  and mask  105   a  have been planarized. In  FIG. 3E , mask  105   a  has been removed, e.g., by wet etching, leaving a recess  113  defined by the exposed sidewalls of isolation region  12  and an upper surface of fin  14 . 
   In  FIG. 3F , optional sidewall spacers  60  have been formed against the formerly exposed sidewalls of isolation region  12  and on portions of the upper surface of fin  14 . This can be done by filling recess  113  with a nitride or oxide material and then partially removing the material. The remaining filler material  60  takes on the appearance of sidewall spacers. 
   Between sidewall spacers  60 , there remains an exposed upper surface of fin  14 , which is the seed from which portion  20   b  (and thus body  20 ) of semiconductor material will be grown, e.g., via SEG. In  FIG. 3G , portion  20   b  (and thus body  20 ) has been grown, e.g., (again) via SEG, such that it has penta-sided head portion  27   p  (with facets  22 ,  24  and  26 ) and stalk portion  29   b . Also, ion implantation has been performed to obtain source/drain regions  44  (not shown in  FIG. 3G , but see  FIG. 1 ). 
   Generally, after the intermediate stage of  FIG. 3G , standard CMOS processing occurs by which FinFET  1   b  is completed. For example, in  FIG. 3H , a layer of insulating material has been formed on outer surfaces of penta-sided head portion  27   p  of portion  20   b  of body  20  that are located above isolation region  12  as well as on portions of the upper surface of isolation region  12 . Those portions of the insulating material not contiguous with penta-sided head portion  27   p  have been selectively removed, which results in gate insulating layer  40 . Also, gate electrode layer  150  has then been formed on gate insulating layer  40  and on portions of the upper surface of isolation region  12 . Accordingly, the stage of FinFET manufacture depicted in  FIG. 3H  corresponds to  FIG. 2B . 
   As noted, sidewall spacers  60  are optional. If sidewall spacers  60  are not formed (or, in other words, the stage depicted in  FIG. 3F  is omitted), then SEG can be performed on the intermediate structure of  FIG. 3E , so that the subsequent processing associated with  FIGS. 3G and 3H  would produce FinFET  1   a  instead of FinFET  1   b.    
   While SEG-process parameters can be controlled to manipulate the growth of body  20   a  or  20   b  so that penta-sided head portion of  27   p  results, different measures are needed to control an overall size of body  20  (and thus a scale of FinFET  1   a  or  1   b ). The surface area of the seed upon which SEG takes place is proportional to the overall size of resulting body  20 . Accordingly, the use of sidewall spacers  60  represents a technique to reduce an overall size that body  20  (and therefore FinFET  1   b ) can obtain. More particularly, the seed area of  FIG. 3E  is larger than the seed area of  FIG. 3F , hence for similar SEG parameters, portion  20   b  of body  20  would be expected to be smaller than portion  20   a  of body  20 . 
   Regardless of whether or not sidewall spacers  60  are used, the SEG process can include the following. The exposed upper surface  14   u  of fin  14  is cleaned via, e.g., the RCA cleaning technique, which uses a mixture of H2SO 4 , HCl, NH 4 OH, HF and H 2 O 2  to remove native oxide from the seed. Then the SEG process can begin. For example, temperatures can range between about 500° C. to about 900° C., pressures can range between about 5 to about 100 Torr, and dichlorosilane (DCS) gas can be used as the atmosphere in which growth takes place. When inchoate bodies  20   a  and  20   b  respectively grow beyond the confines of the sidewalls of isolation region  12 , the surfaces of crystal lattice growth are substantially planar. For SEG conditions in which the temperature is T&lt;800°, beveled facet  26  will typically exhibit plane ( 111 ). For SEG conditions in which the temperature is T&gt;900°, beveled facet  26  will typically exhibit plane ( 311 ). For temperatures T in the range 800°≦T≦900°, see the discussion below of  FIG. 2D . 
     FIG. 2C  is a cross-sectional view (again, taken along line II-II′ of  FIG. 1 ) of a third variety  1   c  of the at-least-penta-sided-channel-type FinFET transistor  1 , according to at least one other embodiment of the present invention. FinFET  1   c  is similar to FinFET  1   b , so minimal discussion of similarities is presented for the sake of brevity. For example, while portion  20   b  of body  20  of FinFET  1   b  is formed of substantially one material, corresponding portion  20   c  of body  20  of FinFET  1   c  includes two materials, namely a mound  16  of strain-inducing semiconductor material and a layer  18  of strained semiconductor material. As is known, an advantage of strained semiconductor material, e.g., silicon, is that it exhibits reduced resistance to electron/hole mobility. 
   Mound  16  of strain-inducing material can be described as a smaller version of portion  20   b  of body  20 . Gas components of the atmosphere provided for the SEG process are changed once mound  16  has reached a desired size, resulting in the formation of a heterogeneous border  17  and then the formation of layer  18  of the strained semiconductor material. Appropriate selection of the respective materials for mound  16  and layer  18  can induce either tensile or compressive stress in layer  18 . 
   To induce tensile stress in layer  18 , the following combinations of semiconductor materials can be used. 
   
     
       
         
             
             
             
           
             
                 
                 
             
             
                 
               strain-inducing 
               strained 
             
             
                 
               (mound 16) 
               (layer 18) 
             
             
                 
                 
             
           
          
             
                 
               SiGe 
               Si 
             
             
                 
               Si 
               SiC 
             
             
                 
               SiGe 
               SiC 
             
             
                 
               Si 1−X1−Y1 Ge X1 C Y1 , 
               Si 1−X2−Y2 Ge X2 C Y2 , 
             
             
                 
               where 0 &lt; X1 &lt; 1 and 
               where 0 &lt; X2 &lt; 1, 0 &lt; Y2 &lt; 1, 
             
             
                 
               0 &lt; Y1 &lt; 1 
               X1 &gt; X2 and Y1 &lt; Y2 
             
             
                 
                 
             
          
         
       
     
   
   To induce compressive stress in layer  18 , e.g., in the circumstance of forming a PMOS FinFET, the following combinations of semiconductor materials can be used. 
   
     
       
         
             
             
             
           
             
                 
                 
             
             
                 
               strain-inducing 
               strained 
             
             
                 
               (mound 16) 
               (layer 18) 
             
             
                 
                 
             
           
          
             
                 
               Si 
               SiGe 
             
             
                 
               SiC 
               Si 
             
             
                 
               SiC 
               SiGe 
             
             
                 
               Si 1−X2−Y2 Ge X2 C Y2 , 
               Si 1−X1−Y1 Ge X1 C Y1 , 
             
             
                 
               where 0 &lt; X2 &lt; 1, 0 &lt; Y2 &lt; 1, 
               where 0 &lt; X1 &lt; 1 and 
             
             
                 
               X1 &gt; X2 and Y1 &lt; Y2 
               0 &lt; Y1 &lt; 1 
             
             
                 
                 
             
          
         
       
     
   
   In the alternative, FinFET  1   b  of  FIG. 2B  can be constructed with a strained channel. There, fin  14  could be formed of strain-inducing material and body  20  could be formed of strained material. 
     FIG. 2D  is a cross-sectional view (again, taken along line II-II′ of  FIG. 1 ) of a fourth variety  1   d  of FinFET transistor  1 , according to at least one other embodiment of the present invention. FinFET  1   d  is similar to FinFET  1   b , so minimal discussion of similarities is presented for the sake of brevity. FinFET  1  has been described as an at-least-penta-sided-channel type of FinFET. Inspection of  FIG. 2D  reveals that FinFET  1   d  is an at least hepta-sided-channel-type of FinFET. 
   As noted above in the discuss above of FinFET  1   b , when inchoate body  20   d  grows using the sidewalls of isolation region  12 , the growth surfaces are substantially planar. For SEG conditions in which the temperature T is in the range 800°≦T≦900°, hepta-sided head region  27   h  results (where the suffix “h” is suggestive of the prefix hepta-). More particularly, instead of having beveled facets  26  as with penta-sided head region  27   p  of FinFET  1   b , hepta-sided head region  27   h  instead includes beveled facets  25   a  and  25   b . In other words, faceting morphology of head portion  27   h , in terms of Miller indices, can include: horizontal facet  24  exhibiting plane ( 100 ); first beveled facets  25   a  exhibiting one of plane ( 311 ) or ( 111 ); and second beveled facets  25   b  exhibiting the other of plane ( 311 ) or ( 111 ), respectively. Just as FinFETs  1   a ,  1   b  and  1   c  are described as having five channels, FinFET  1   d  can be described as having seven channels beneath its seven facets, namely,  22 ,  25   a ,  25   b ,  24 ,  25   b ,  25   a  and  22 . Above isolation region  12 , head portion  27   h  has a polygonal silhouette having six or more sides. 
   By appropriately adjusting temperature during the SEG process, hepta-sided head region  27   h  (and consequently FinFET  1   d ) can be formed. The ordinarily-skilled artisan can easily adapt the method illustrated in  FIGS. 3A-3G  to obtain FinFET  1   d . It is noted that at least hepta-sided-channel-type alternative versions of FinFET  1   a  (again, no spacers  60 ) and FinFET  1   c  (strained semiconductor architecture) can also be formed. The ordinarily-skilled artisan can easily adapt the method illustrated in  FIGS. 3A-3G  to obtain such at least hepta-sided-channel-type alternative FinFETs. 
     FIG. 2E  is a cross-sectional view (again, taken along line II-II′ of  FIG. 1 ) of a fifth variety  1   e  of the at-least-penta-sided-channel-type FinFET transistor  1 , according to at least one other embodiment of the present invention. Varieties  1   a - 1   d  of FinFET  1  can be described as bulk silicon process types of FinFET, FinFET  1   e  can be described as a silicon on insulator (SOI) type of FinFET. 
   FinFET  1   e  is similar to FinFET  1   a , so minimal discussion of similarities is presented for the sake of brevity. While FinFET  1   a  has a substrate  10  configured like an inverted-T shape having a horizontal portion and fin  14  extending perpendicularly therefrom, etc., by contrast FinFET  1   e  instead includes: a substantially planar substrate  10   e ; and buried oxide (BOX) layer  12   e ; a semiconductor fin  14   e ; and a penta-sided head region  27   p  that (in the example of  FIG. 2   e ) substantially constitutes the entirety of a portion  20   e  of body  20 . Faceting morphology of head portion  27   p  in  FIG. 2E  again includes the same five facets, namely: vertical facets  22 ; horizontal facet  24 ; and beveled facets  26 . 
   It is noted that, for both FinFET  1   e  and FinFET  1   a , fin  14  and  14   e  can be described as having been formed upon a base. In FinFET  1   a , the base is a bulk silicon base. In FinFET  1   e , the base is an SOI base. 
     FIGS. 4A-4C  are cross-sectional views (from the same perspective of  FIG. 2E ) that depict various stages of a method, according to at least one embodiment of the present invention, of making FinFET  1   e . In  FIG. 4A , semiconductor, e.g., silicon, substrate  10   e  has been provided. BOX  12   e  has been formed on substrate  10   e . And fin  14   e  has been formed on BOX  12   e . For example, fin  14   e  could be obtained by forming a silicon layer on BOX  12   e  and selectively removing a portion thereof, with the remainder being fin  14   e . Similar to how the relative scale of FinFET  1   a  versus  1   d  is controlled by selecting the size of sidewall spacers  60  relative to a width of recess  113 , a scale of FinFET  1   e  can be controlled by appropriately establishing a size of the footprint of fin  14   e . In the cross-sectional view that is  FIG. 2E , changing the footprint of fin  14   e  could be manifested as differing widths of fin  14   e.    
   In  FIG. 4B , head region  14   e  has been grown via, e.g., an SEG process similar to what has been discussed above regarding, e.g.,  FIG. 3G . Unlike portion  20   b  of body  20  of  FIG. 3G , however, portion  20   e  of body  20  in  FIG. 4B  does not have a stalk  29   b . Rather, fin  14   e  extends upward into penta-sided head region  29   e . As noted, penta-sided head region  27   p  substantially constitutes the entirety of a portion  20   e  of body  20  (indicated in  FIG. 2E  with a lead line having the label  27   e = 20   e ). Alternatively, portion  20   e  could be implemented as a strained structure such as portion  20   c  of  FIG. 2C  and/or to instead include a hepta-sided head region  27   h  (not depicted) similar to head region  27   h  of  FIG. 2D . The ordinarily-skilled artisan can adapt the explanation provided above to easily obtain such alternatives. 
   More particularly in  FIG. 4C , body  20   e  has been grown, e.g., (again) via SEG, such that it has penta-sided head portion  27   p . Also, ion implantation has been performed to obtain source/drain regions  44  (not shown in  FIG. 4B , but see  FIG. 1 ). 
   Generally, after the intermediate stage of  FIG. 4B , standard CMOS processing occurs by which FinFET  1   e  is completed. As this is similar to what is described above regarding  FIG. 3G , such discussion will not be repeated her for the sake of brevity. Accordingly, the stage of FinFET manufacture depicted in  FIG. 4C  corresponds to  FIG. 2E . 
   To reiterate, embodiments of the present invention provide various multiple-sided-channel FinFETs that exhibit reduced symptoms of the corner effect, which can be achieved (according to other embodiments of the present invention) by additively constructing or building up, e.g., growing, a body of semiconductor material into an approximation of a fin having rounded corners. An advantage of such additive techniques is that they do not suffer the negative consequential effects, e.g., surface roughness arising from dry etching, upon the inchoate FinFET that are consequences of the Background Art techniques for subtractively obtaining an approximation of a rounded corner of a fin. 
   Another advantage of such additive techniques (according to embodiments of the present invention) is that the scale of the resulting FinFET is relatively easier to control as contrasted with the Background Art techniques mentioned above. 
   Of course, although several variances and example embodiments of the present invention are discussed herein, it is readily understood by those of ordinary skill in the art that various additional modifications may also be made to the present invention. Accordingly, the example embodiments discussed herein are not limiting of the present invention.