Patent Publication Number: US-6906366-B2

Title: Single transistor ferroelectric transistor structure with high-k insulator

Description:
CROSS-REFERENCE 
     This application is a divisional of application Ser. No. 09/820,023, filed Mar. 28, 2001, entitled “Single Transistor Ferroelectric Transistor Structure with High-k Insulator and Method of Fabricating Same,” invented by Sheng Teng Hsu, and Fengyan Zhang, now U.S. Letters Patent No. 6,602,720, which is hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates generally to semiconductor technology and more particularly to metal-ferroelectric-insulator semiconductor (MFIS) transistor structures, and methods of fabrication. An MFIS transistor is similar to an MFOS transistor, but is not limited to structures that use oxide as the insulator material. 
     Previously, single transistor ferroelectric memory transistors have utilized a ferroelectric electrode stack, comprising a ferroelectric gate with a top electrode. The device would be formed by depositing a ferroelectric material, followed by an overlying metal layer. The layers would then be plasma etched. Plasma etching degrades the ferroelectric properties of the ferroelectric gate, thereby reducing the reliability of the memory transistor. The ferroelectric material also needed to be passivated to prevent contamination from hydrogen. Passivation was also used to reduce unwanted interactions between the ferroelectric material and underlying oxide. 
     SUMMARY OF THE INVENTION 
     A ferroelectric transistor structure is provided comprising a ferroelectric gate overlying a semiconductor substrate. The ferroelectric gate has a bottom and sides surrounded by high-k material, and a top covered with a top electrode. The top electrode and the high-k material serve to encapsulate the ferroelectric gate, thereby reducing, or eliminating, contamination due to oxygen, hydrogen or other contaminants. The high-k material along the bottom of the ferroelectric gate also serves as a gate dielectric. 
     A method of forming the ferroelectric gate structure of the present invention is also provided. A sacrificial gate structure is formed overlying a substrate and removed to produce an open gate region. A high-k insulator is deposited over the substrate, including the open gate region. A ferroelectric material is deposited over the high-k insulator and then polished using CMP. A top electrode is then formed over the remaining ferroelectric material. The combination of the top electrode and the high-k insulator serve to encapsulate and protected the ferroelectric material. 
     The high-k insulator is preferably ZrO 2 , zirconium silicate, Zr—Al—Si—O, HfO 2 , hafnium silicate, Hf—Al—O, La—Al—O, lanthanum oxide Ta 2 O 5 , or other suitable material 
     The ferroelectric material is preferably PGO, PZT, SBT, SBO, SBTO, SBTN, STO, BTO, BLT, LNO, YMnO 3 , or other suitable material. 
     The top electrode is preferably iridium, platinum, ruthenium, iridium oxide, platinum oxide, ruthenium oxide, or other suitable material. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional view of a semiconductor substrate ready for further processing. 
         FIG. 2  is a cross-sectional view of the semiconductor substrate with a sacrificial layer overlying the dielectric layer. 
         FIG. 3  is a cross-sectional view of the semiconductor substrate with a sacrificial gate structure overlying the dielectric layer. 
         FIG. 4  is a cross-sectional view of the semiconductor substrate with the sacrificial gate structure surrounded by oxide. 
         FIG. 5  is a cross-sectional view of the semiconductor substrate after the sacrificial gate is removed. 
         FIG. 6  is a cross-sectional view of the semiconductor substrate following deposition of a high-k insulator layer. 
         FIG. 7  is a cross-sectional view of the semiconductor substrate following deposition of a ferroelectric material layer. 
         FIG. 8  is a cross-sectional view of the semiconductor substrate following chemical-mechanical polishing of the ferroelectric material layer. 
         FIG. 9  is a cross-sectional view of the semiconductor substrate following deposition of a top electrode layer. 
         FIG. 10  is a cross-sectional view of the semiconductor substrate showing a top electrode after etching. 
         FIG. 11  is a cross-sectional view of the semiconductor substrate showing a passivation layer and metal contacts to the device structures. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  shows a semiconductor structure  10  that has been prepared using state of the art processes. Shallow trench isolation (STI) has been used to produce isolation regions  12 , and an active device region  14  on a substrate  16 . Although an STI structure is shown, it would also be possible to use LOCOS isolation instead of STI. The semiconductor substrate is preferably silicon or silicon on insulator (SOI). A sacrificial oxide  18  has been grown or deposited over the substrate  16  to a thickness of between approximately 2 nm and 20 nm. 
       FIG. 2  shows a sacrificial layer  20  deposited overlying the sacrificial oxide  18 . The sacrificial layer is deposited to a thickness of between approximately 200 nm and 400 nm. The sacrificial layer is preferably silicon nitride or polysilicon. The sacrificial layer is preferably easy to remove by selective etching without affecting underlying or adjacent materials. 
       FIG. 3  shows a sacrificial gate structure  22  formed by patterning the sacrificial layer using an overlying photoresist layer (not shown), and plasma etching the sacrificial layer. A source region  24  and a drain region  26  are formed adjacent to the sacrificial gate structure  22 . The source region  24  and the drain region  26  may be formed by any state of the art process, but preferably by ion implantation. Ion implantation may be done through the sacrificial oxide. 
       FIG. 4  shows the semiconductor structure  10  following deposition and polishing of an oxide layer  30 . The oxide layer  30  is deposited overlying the sacrificial gate structure  22  and surrounding regions. The oxide layer  30  is deposited to a thickness at which the lowest portion of the oxide is at least as high as the sacrificial gate structure  22 . This thickness is preferably 1 to 2 times the height of the sacrificial gate structure  22  above the substrate  16 . Following deposition of the oxide layer  30  it is polished using chemical-mechanical polishing (CMP) to expose the sacrificial gate structure  22 . The CMP process is preferably stopped at the top of the sacrificial gate structure  22 , without removing a significant portion of the sacrificial gate structure  22 . 
       FIG. 5  shows the semiconductor structure  10  following removal of the sacrificial gate structure  22  and the underlying sacrificial oxide. The removal of the sacrificial gate structure  22  and underlying sacrificial oxide leaves an open gate region  32 . The sacrificial gate structure  22  and sacrificial oxide are preferably removed using a wet etch process. Other suitable etch processes may also be used. 
       FIG. 6  shows the semiconductor structure  10  following deposition of a high-k insulator  34 . The high-k insulator  34  is preferably between 2 nm and 100 nm thick. The high-k insulator  34  is preferably selected from materials that will reduce, or eliminate, diffusion of oxygen or hydrogen through it. The high-k insulator  34  is also preferably a material that will act as a suitable gate dielectric. The high-k insulator  34  is preferably ZrO 2 . Although ZrO 2  is preferred, other suitable materials including zirconium silicate, Z—Al—Si—O, HfO 2 , hafnium silicate, Hf—Al—O, La—Al—O, lanthanum oxide and Ta 2 O 5  may be used. 
     A variety of methods are available for depositing the high-k insulator  34 . The available deposition methods include chemical vapor deposition, including pulsed CVD, sputtering, or evaporation. 
     For example, ZrO 2  may be deposited using atomic layer deposition, also referred to as “pulsed CVD”. Atomic layer deposition is used to deposit an extremely thin layer of material onto the substrate. Atomic layer deposition employs a chemical phenomenon known as chemisorption. In chemisorption, a material in a gas phase will adsorb to a surface saturating it, forming a monolayer. Most conventional deposition techniques employ physisorption processes, which produce multilayer deposition regions with a surface coverage that is purely statistical. By taking advantage of chemisorption, films can be grown that are extremely uniform in thickness and composition. For instance, ZrO 2  films have reportedly been grown this way on silicon by using zirconium chloride (ZrCl 4 ) to form the first monolayer, purging the system of ZrCl 4 , and then exposing the surface to water vapor (H 2 O). Other precursors for producing zirconium oxide layers include zirconium propoxide (Zr(iOPr) 4 ) and zirconium tetramethyl heptanedionato (Zr(tmhd) 4 ). Chemisorption occurs over a very limited range of temperature and pressures for a given gas-solid combination. For example, zirconium oxide has reportedly been deposited on silicon substrates at a temperature of 300 degrees Celsius using ZrCl 4  and H 2 O. As the process produces a monolayer, thicker layers of zirconium oxide would be produced by adding additional monolayers. An efficient tool for preparing such ultrathin, atomic layers depositions on semiconductor substrates does not currently exist, although experimental depositions have demonstrated that atomic layer deposition is workable. 
     ZrO 2  may also be deposited using the precursors identified above, as well as other precursors, in a more conventional CVD process. 
     An alternative deposition technique using conventional systems is to sputter targets to lay down a thin layer of high-k material. A sputtering target of high purity metal is used. A wafer is prepared and placed into a deposition chamber. The wafer is then heated to a temperature between room temperature and 500 degrees Celsius. A mixture of argon (Ar) and oxygen (O 2 ) is then introduced into the deposition chamber. A plasma with a sputtering power of between approximately 500 W and 5 kW is produced within the chamber. The zirconium shutter is opened to deposit zirconium over the wafer, and then closed. The presence of oxygen within the chamber will cause the target material to form ZrO 2  concurrently with the deposition on the wafer 
     In another alternative embodiment of the deposition method of the present invention, evaporation of targets is used to deposit the thin layer. The basic process is substantially identical to the description provided above with regard to sputtering, except that instead of exposing the targets to a plasma, the targets are heated to a temperature of between approximately 1,000 and 2,000 degrees Celsius. As described above, shutters can be used to control the duration of the deposition. 
       FIG. 7  shows the semiconductor structure  10  following deposition of a ferroelectric material  38 . The ferroelectric material fills the open gate region. Preferably, the ferroelectric material  38  is deposited to a thickness greater than the depth of the open gate region. The ferroelectric material  38  may be deposited by metal-organic chemical vapor deposition (MOCVD) or a chemical-solution deposition (CSD) process. The ferroelectric material is preferably selected from PGO, PZT, SBT, SBO, SBTO, SBTN, STO, BTO, BLT, LNO, and YMnO 3 . 
     For example a PGO material, which may also be referred to as Pb 5 Ge 3 O 11 , may be deposited using the following preferred method. The PGO material is deposited by metal organic vapor deposition (MOCVD) and RTP (Rapid Thermal Process) annealing techniques. The PGO material may be deposited at temperatures between 450 and 550° C. 
     An EMCORE oxide MOCVD reactor with liquid delivery system was used for the growth of PGO material. The precursors for the PGO material are listed in Table 1. 
     
       
         
           
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                  The properties of precursors for PGO thin films 
               
            
           
           
               
               
               
               
            
               
                   
                   
                 Vapor Pressure 
                 Decomposition 
               
               
                 Precursors 
                 Formula 
                 (mm Hg) 
                 Temperature(° C.) 
               
               
                   
               
               
                 Pb(TMHD) 2   
                 Pb(C 11 H 19 O 2 ) 2   
                 180° C./0.05 
                 325° C. 
               
               
                 Ge(ETO) 4   
                 Ge(C 2 H 5 O) 4   
                 b.p. 185.5° C. 
               
               
                   
               
            
           
         
       
     
     Liquid precursors such as germanium alkoxides, germanium halides, lead alkyls, and lead halides use a bubbler with a controlled temperature to generate precursor vapors. Solid precursors, such as lead B-diketonates, are dissolved in a solvent and use a liquid delivery system coupled with a flash vaporizer to generate precursor vapors. Table 2 is a list of PGO precursors that may be used in some aspects of the present invention. 
     
       
         
           
               
             
               
                 TABLE 2 
               
             
            
               
                   
               
               
                 The properties of precursors for PGO films 
               
            
           
           
               
               
               
               
               
               
            
               
                   
                   
                 Appearance 
                   
                 Vapor 
                 Decom- 
               
               
                   
                   
                 at 
                 Mois- 
                 Pressure 
                 position 
               
               
                   
                   
                 room 
                 ture 
                 (mm 
                 Temp. 
               
               
                 Precursor 
                 Formula 
                 temperature 
                 stability 
                 Hg) 
                 (° C.) 
               
               
                   
               
               
                   
                 GeH 4   
                   
                   
                   
                   
               
               
                   
                 Ge 2 H 6   
               
               
                   
                 Ge 3 H 8   
               
               
                 Ge(ETO) 4   
                 Ge(OC 2 H 5 ) 4   
                 colorless 
                 sensi- 
                 185° C. 
               
               
                   
                   
                 liquid 
                 tive 
               
               
                   
                 GeCl 4   
               
               
                   
                 (C 2 H 5 ) 2 GeCl 2   
               
               
                 Pb 
                 Pb(C6H5)4 
                 white 
                   
                 230° 
                 325° C. 
               
               
                 Tetraphenyl 
                   
                 powder 
                   
                 C./0.05 
               
               
                 Pb(TMHD) 2   
                 Pb(C 11 H 19 O 2 ) 2   
                 white 
                   
                 180° 
                 325° C. 
               
               
                   
                   
                 powder 
                   
                 C./0.05 
               
               
                   
                 Pb(C 2 H 5 ) 4   
               
               
                   
               
            
           
         
       
     
     Table 3 is a list of solvents that are alternately available for use in some aspects of the present invention. 
     
       
         
           
               
             
               
                 TABLE 3 
               
             
            
               
                   
               
               
                  The properties of solvents for PGO films 
               
            
           
           
               
               
               
            
               
                 Solvents 
                 Formula 
                 Boiling Temp. (° C.) 
               
               
                   
               
               
                 Tetrahydrofuran 
                 C 4 H 8 O 
                 65-67° C. 
               
               
                 (THF) 
               
               
                 Iso-propanol 
                 C 3 H 7 OH 
                  97° C. 
               
               
                 Tetraglyme 
                 C 10 H 22 O 5   
                 275° C. 
               
               
                 Xylene 
                 C 6 H 4 (CH 3 ) 2   
                 137-144° C. 
               
               
                 Toluene 
                 C 6 H 5 CH 3   
                 111° C. 
               
               
                 Butyl ether 
                 [CH 3 (CH 2 ) 3 ] 2 O 
                 142-143° C. 
               
               
                 Butyl acetate 
                 CH 3 CO 2 (CH 2 ) 3 CH 3   
                 124-126° C. 
               
               
                 2-Ethyl-1-hexanol 
                 CH 3 (CH 2 ) 3 CH(C 2 H 6 )CH 2   
                 183-186° C. 
               
               
                   
                 OH 
               
               
                   
               
            
           
         
       
     
     [Pb(thd) 2 ] and [Ge(ETO) 4 ] with a molar ratio of 5:3 were dissolved in a mixed solvent of tetrahydrofuran, isopropanol and tetraglyme in the molar ratio of 8:2:1. The precursor solutions have a concentration of 0.1 to 0.3 M/L of Pb 5 Ge 3 O 11 . The solution was injected into a vaporizer (150° C.) by a pump at a rate of 0.1 ml/min to form precursor gases. The precursor gases were brought into the reactor using a preheated argon flow at 150-170° C. The deposition temperatures and pressure are 500° C. and 5-10 Torr separately. The shroud flow (Ar 4000 sccm) with oxygen (1000-2000 sccm) was led into the reactor. After deposition, the PGO material was cooled down to room temperature in an oxygen atmosphere. The PGO material may be annealed using RTP. 
     Alternatively, a CSD process may be used to deposit the ferroelectric material instead of MOCVD. One form of CSD process is a spin on method. For example, a PGO thin film may be deposited using the spin on method. The precursors are lead acetate and germanium iopropoxide in di (ethylene glycol)ethyl ether solution. The precursors are spun over the substrate and any overlying structures forming a film. The film is baked at 50 to 350 degrees Celsius for 1 to 10 minutes and pre-annealed after each spin coating at 400 to 500 degrees Celsius for 1 to 15 minutes to evaporate the solvent and eliminate the organic components. Each spin coating layer has a thickness of between about 10 nm and 100 nm. After several repetitions, the PGO film can be produced with a desired thickness. The PGO film is crystallized at 500 to 600 degrees Celsius for 5 minutes to 3 hours in oxygen ambient. Optimization of the process can be achieved for a desired film-thickness, without undue experimentation. 
       FIG. 8  shows the semiconductor structure  10  following CMP of the ferroelectric material to produce a ferroelectric gate  40 . The CMP process preferably stops at the top of the oxide layer  30 . 
       FIG. 9  shows the semiconductor structure  10  following deposition of an electrode layer  42 . The electrode layer  42  comprises iridium, platinum, ruthenium, or their oxides. The electrode layer  42  is patterned and etched to form a top electrode  44 , as shown in FIG.  10 . The electrode layer  42  may be patterned using photoresist or a hard mask material, such as TiN, TiO 2 , TiAlO 3 , SiO 2 , SiN, or other suitable material. The electrode layer may be etched by plasma etching or other suitable etching process. 
     In an alternative embodiment, an inlaid, or damascene, method may be used to form the top electrode  44 . A trench would be formed using a method similar to that used in forming the ferroelectric gate, which was described in detail above. A metal, such as iridium, platinum, ruthenium, or their oxides, would then be deposited into the trench and polished using CMP to form the top electrode  44 . 
       FIG. 10  shows the semiconductor structure  10  with a ferroelectric gate structure  46 . The ferroelectric gate structure  46  comprises the ferroelectric gate  40  protected by the high-k insulator  34  along the bottom and sides, where the high-k insulator forms sidewalls  48 , and the top electrode  44  above. This will reduce, or eliminate, contamination of the ferroelectric gate  40  from oxygen or hydrogen diffusing into the ferroelectric gate  40 . In some embodiments, the high-k insulator  34  may eliminate the need for passivation of the ferroelectric material. 
       FIG. 11  shows the semiconductor structure  10  following passivation and metallization using state of the art methods. Connections  50  to the source region  24 , the drain region  26 , and the top electrode  44  extend through a passivation layer  52 . The connections  50  are shown as simplified structures. Any state of the art metallization scheme may be used, including copper metallization. The metallization may include barrier layers and other layers that are used in connection with various metallization schemes. 
     Although, metallization using deposition followed by etching is described above, it would also be possible to use an inlaid, or damascene, metallization process instead as described above in connection with the top electrode  44 . Use of the damascene metallization process is preferred for copper metallization for example.