Patent Publication Number: US-6212249-B1

Title: Data separation circuit and method

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a data separation operation performed by a floppy disk controller and, more particularly, to a data separation circuit and method which use a digital phase locked loop (DPLL). 
     2. Discussion of Related Art 
     With reference to the attached drawings, a conventional data separation circuit will be described below. FIG. 1 is a block diagram of a conventional data separation circuit. A conventional internal data separation circuit roughly includes an analog PLL part and its related circuits. As shown in FIG. 1, the circuit has a prescaler  1  for leveling the magnitude of the signal output from a reference crystal XTAL, which has a predetermined reference frequency of 24 MHz, into a specific size; a reference clock generating part  2  for receiving the frequency levelled by the prescaler  1  and generating a system reference clock; a first frequency divider  3  for dividing the frequency levelled by the prescaler  1 ; a ¼ cycle delaying part  4  for delaying by ¼ cycle of the system reference clock the data read out of the disk driver in synchronization with the reference clock of the reference clock generating part  2 ; and a MUX  5  for multiplexing the frequency-divided signal output by the first frequency divider  3  and the delayed read data signal output by the ¼ cycle delaying part  4  based on a signal indicative of a read gate&#39;s logic state. The read gate becomes logic high when the read data is applied (See FIGS.  4 C and  4 D). 
     A zero-phase error detecting part  6  also receives the signal indicative of the read gate&#39;s logic state and the delayed read data signal, and detects the zero phase error. An enable logic part  7  outputs an enable signal in accordance with the read data and the read gate&#39;s logic state to an analog phase locked loop circuit (PLL)  14 . 
     As shown in FIG. 1, the analog PLL  14  includes a phase comparing part  8  for comparing, in accordance with the enable signal, the output signal from the MUX  5  with the frequency-divided signal fed-back by the analog PLL  14  to thereby detect the phase difference between these signals and generate an up/down signal. The analog PLL  14  further includes an electric charge pump  9  for outputting a control voltage which varies with the frequency and phase of the clock signal by charging/discharging in response to the up/down signal output by the phase comparing part  8 ; a loop filter  10  for controlling the width and magnitude of the control voltage, which has a ripple form, produced by the charge/discharge currents of the electric charge pump  9 ; a voltage controlled oscillator (VCO)  11  for generating, in synchronization with the reference clock, a signal whose frequency varies in accordance with the control voltage; and a second frequency divider  12  for determining a frequency-dividing ratio according to the data rate to thereby frequency-divide the oscillating frequency of the signal output from the VCO  11 . 
     The circuit of FIG. 1 also includes a data/clock signal outputting part  13  for dividing a data and a clock signal from the delayed read data signal output by the ¼ cycle delaying part  4  based on the frequency-dividing signal output by the second frequency divider  12 . The data/clock signal outputting part  13  then outputs the divided clock and data signals. 
     The thus-structured conventional data separation circuit divides data by controlling the VCO frequency, gain, and current applied to the circuit according to various conditions such as the data rate. While the conventional data separation circuit effectively retrieves data, designing such a circuit is quite difficult. If the data separation circuit design includes an analog PLL, as in the conventional art, the size of the circuit increases. As a result, additional controls, for instance, for VCO frequency, gain, and component current are thus needed for the data separation operation. Consequently, external influences can make the circuit unstable. 
     SUMMARY OF THE INVENTION 
     One object of the present invention is to provide a data separation circuit and method that substantially obviate one or more of the problems and/or disadvantages discussed above with respect to the conventional art. 
     Another object of the present invention is to provide a data separation circuit which maintains its stability by using a digital phased locked loop (DPLL). 
     These and other objects, in accordance with the purpose of the present invention and as embodied and broadly described, are achieved by providing a data separation circuit, comprising: generating means for generating a reference clock according to a data rate at which data is being read; a digital phase locked loop generating a window signal based on said reference clock; and output means for outputting a data signal and a clock signal based on said read data and said window signal. 
     These and other objects are further achieved by providing a method of separating data, comprising the steps of: (a) generating a reference clock according to a data rate at which data is being read; (b) generating a window signal based on said reference clock; and (c) outputting a data signal and a clock signal based on said read data and said window signal. 
     Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. 
    
    
     BRIEF DESCRIPTION OF THE ATTACHED DRAWINGS 
     The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the drawings. 
     In the drawings: 
     FIG. 1 is a block diagram of a conventional data separation circuit; 
     FIG. 2 illustrates a data separation circuit according to the present invention; 
     FIG. 3A illustrates the read data bits determined based on the delayed read data stream illustrated in FIG.  3 B and the window signal illustrated in FIG. 3C; 
     FIG. 3B illustrates an example of a delayed read data stream; 
     FIG. 3C illustrates a window signal corresponding to the delayed read data stream of FIG. 3B; 
     FIG. 4A illustrates the read data bit stream of FIG. 3A; 
     FIG. 4B illustrates the output of the frequency divider illustrated in FIG. 2; 
     FIG. 4C illustrates the read data stream and the delayed read data signal from which the frequency divider produced the frequency divided signal of FIG. 4B; 
     FIG. 4D illustrates the read gate signal generated when the delayed read data signal is as shown in FIG. 4C; 
     FIG. 4E illustrates the output signal of the multiplexer that serves as an operation clock for the digital phase locked loop illustrated in FIG. 2; 
     FIG. 5A illustrates the gate logic determining part and the ¼ cycle delaying part of FIG. 2 in greater detail; 
     FIG. 5B illustrates a read data stream; 
     FIG. 5C illustrates the delayed read data stream for the read data stream of FIG. 5B; 
     FIG. 5D illustrates the output of the OR gate in FIG. 5A when the read data stream is as shown in FIG. 5B; 
     FIG. 5E illustrates the read gate signal when the read data stream is as shown in FIG. 5B; 
     FIG. 6 illustrates the state diagram for generating phase error signals implemented by the phase detecting part of FIG. 2; 
     FIG. 7A illustrates the output of the multiplexer illustrated in FIG. 2; 
     FIG. 7B illustrates a window signal having transition pulses lagging the transition pulses of the reference clock of FIG.  7 A and the resulting phase error signals; 
     FIG. 7C illustrates a window signal having transition pulses leading the transition pulse of the reference clock of FIG.  7 A and the resulting phase error signals; 
     FIG. 8 illustrates a table of the control signals generated based on the phase control values; 
     FIG. 9 illustrates the operation state achieved in accordance with the control signal output by the phase/frequency controlling part illustrated in FIG. 2; 
     FIG. 10A illustrates a variation length shift register; 
     FIG. 10B illustrates the generation of the next transition pulse for the window signal in the fast state; 
     FIG. 10C illustrates the generation of the next transition pulse for the window signal in the normal state; and 
     FIG. 10D illustrates the generation of the next transition pulse for the window signal in the slow state. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENT 
     FIG. 2 illustrates a data separation circuit according to the present invention. As shown in FIG. 2, a sampling frequency generating part  21  receives an oscillator OSC signal having a predetermined oscillation frequency, and generates a sampling frequency having a fixed reference frequency therefrom. The sampling frequency signal serves as a synchronizing signal, and is received by a gate logic determining part  20 , a ¼ cycle delaying part  23 , a digital phase locked loop (DPLL)  29 , and a data/clock signal outputting part  28 . Based on the sampling frequency signal, the operation of these components is synchronized. 
     The ¼ cycle delaying part  23  and the gate logic determining part  20  also receive the data read from a floppy disk by the floppy disk drive. The ¼ cycle delaying part  23  delays the read data by ¼ of a cycle. A cycle is the minimum interval for changing the next pulse of the window signal, and as discussed in detail below depends on the data rate of the floppy disk being driven by the floppy disk drive. The output of the ¼ cycle delaying part  23  is applied to the frequency divider  22  as a reset signal to synchronize the output of the frequency divider  22  with the output of the ¼ cycle delaying part  23 . The frequency divider  22  frequency divides the sampling frequency signal by a predetermined dividing ratio. 
     As shown in FIG. 2, a multiplexer  24  receives both the delayed read data and the output of the frequency divider  22 . The multiplexer  24  multiplexes these two signals based on a gate signal received from the gate logic determining part  20 . The gate logic determining part  20  determines, in synchronization with the sampling frequency signal, a logic state of the read gate based on the read data. 
     FIG. 5A illustrates the gate logic determining part  20  and the ¼ cycle delaying part  23  in greater detail. As shown, the gate logic determining part  20  and the ¼ cycle delaying part  23  are jointly constructed of a plurality of serially connected D-flipflops  30  which are enabled by the sampling frequency signal. The first one of the plurality of serially connected D-flipflops  30  receives the read data stream, and the delayed read data is output from a fourth one of the plurality of serially connected D-flipflops  30 . The output of the first one and the last one of the plurality of serially connected D-flipflops  30  is connected to an OR gate  32 . The output of the OR gate  32  enables a D-flipflop  34  having its inverted output connected to its input. The non-inverted output of the D-flipflop  34  outputs the read gate signal. 
     The output of the multiplexer  24  serves a reference clock for the DPLL  29 . Based on this reference clock and the read gate signal, the DPLL  29  generates a window signal. As shown in FIG. 2, the operation of the DPLL  29  is synchronized in accordance with the sampling frequency signal. 
     The DPLL  29  includes a phase detecting part  25 , a phase/frequency controlling part  26 , and a digital control oscillator  27 . The phase detecting part  25  detects the phase error between the reference clock output by the multiplexer  24  and the window signal. The phase detecting part  25  outputs a first and second error signal wherein the first error signal indicates phase error in a first direction and the second error signal indicates phase error in a second direction opposite to the first direction. The phase/frequency controlling part  26  receives both the first and second phase error signals, and generates a first and second count. The first count represents a total amount of time the phase error in the first direction exists during a predetermined period of time, and the second count represents a total amount of time the phase error in the second direction exists during a second predetermined period of time. The phase/frequency controlling part  26  establishes the predetermined period of time as a time period between edges of the read gate signal. Based on the first and second count, the phase/frequency controlling part  26  generates a control signal to the digital control oscillator  27  in synchronization with the sampling frequency signal. The digital control oscillator  27 , also in synchronization with the sampling frequency signal, generates the window signal. Specifically, based on the control signal, the digital control oscillator  27  increases, decreases, or maintains the length of time between pulses of the window signal. 
     As shown in FIG. 2, a data/clock signal outputting part  28  receives the delayed read signal and the window signal, and divides the delayed read data signal into a data signal and a clock signal based on the window signal. 
     The operation of the data separation circuit according to the present invention will now be described in detail with respect to FIGS. 3A-10D. Referring to FIGS. 3A-3C, the operation of the data/clock signal outputting part  28  will be described. FIG. 3B illustrates an example of a delayed read data stream which the data/clock signal outputting part  28  receives from the ¼ cycle delaying part  23 , and FIG. 3C illustrates a window signal corresponding to the delayed read data stream which the data/clock signal outputting part  28  receives from the DPLL  29 . Based on the window signal, the data/clock signal outputting part  28  divides the delayed read data stream into a data signal and a clock signal. 
     As shown in FIG. 3C, the window signal includes a data area c and a clock area d. When a transition pulse, such as transition pulses a in FIG. 3B, in the delayed read data stream occur within the data area c of the window signal, the data/clock signal outputting part  28  determines, as shown in FIG. 3A, a read data bit of “1”. If no transition pulse appears in the data area c of the window signal, then, as shown in FIG. 3A, the data/clock signal outputting part  28  determines a read data bit of “0”. Furthermore, if a transition pulse of the read data stream, such as transition pulse b in FIG. 3B, occurs during the clock area d of the window signal, then the data/clock signal outputting part  28  determines that the transition pulse of the read data stream is a clock pulse. 
     By determining read data bits and clock pulses in the above manner, the data/clock signal outputting part  28  divides the data and clock signal from the read data stream, and outputs separate data and clock signals. 
     As further shown in FIG. 3B, during operation of the floppy disk drive, the transition pulse of the read data stream may occur earlier or later because of, for example, irregularities in the rotation of the floppy disk drive motor or the diameter of the floppy disk. As a result, the period of time between transition pulses may decrease or increase as shown by arrows e in FIG.  3 B. Stated another way, the data rate with which the data is read from the floppy disk may increase (i.e., a fast state) or decrease (i.e., a slow state). For the data/clock signal outputting part  28  to continue operating properly, the window signal must change in a similar manner. As discussed in detail below, the DPLL  29  increases or decreases the length of time between pulses of the window signal in accordance with changes in the data rate based on a reference clock received from the multiplexer  24 . 
     The generation of this reference clock will now be described with reference to FIGS. 4A-4E and  5 A-SE. For purposes of discussion, the read data bit stream of FIG. 3A will be used. Accordingly, FIG. 4A illustrates the read data bit stream of FIG. 3A with the data area c and clock area d for each bit illustrated. 
     The sampling frequency generating part  21  receives the OSC signal having a predetermined oscillating frequency, and frequency divides the OSC signal according to the predetermined data rate of the floppy disks upon which the floppy disk drive operates. For instance, if the data of the floppy disk has a data rate of modified frequency modulation (MFM), the frequency of the sampling frequency signal becomes 16 MHz. If the data rate of the floppy disk is 300 k MFM, the sampling frequency generating part  21  generates a sampling frequency signal having a frequency of 9.6 MHz. For a floppy disk with a data rate of 250 k MFM, the sampling frequency generating part  21  generates a sampling frequency signal having a frequency of 8 MHz. Accordingly, when the floppy disk has a data rate of c MFM, the minimum interval for changing the next pulse of the window signal is 2 μs. Consequently, the sampling frequency signal will have 16 sample clock pulses every 2 μs period. As described in detail below with respect to the DPLL  29 , each one of these sixteen pulses defines one slice, and the sampling frequency signal serves as an operation clock for the DPLL  29 . 
     For the purposes of discussion, it will be assumed for the remainder of this application that the data rate of the floppy disk is c MFM such that the length of one cycle is 2 μs, and sixteen pulses of the sample frequency signal occur each 2μ cycle. Accordingly, FIGS. 3A-10D have been produced assuming a 2 μs cycle. As such, FIG. 3A illustrates that each data bit is determined in one cycle (i.e., 2 μs) and the data area c and clock area d of the window signal each have a length of one-half of a cycle (i.e., 1 μs). 
     The ¼ cycle delaying part  23  receives the data read from the floppy disk by the floppy disk drive, and delays the read data stream by ¼ cycle. Accordingly, as shown in FIG. 5A, the read data stream is delayed by four pulses of the sampling frequency signal by extracting, as the delayed read data, the output from the fourth one of the plurality of serially connected D-flipflops  30  wherein the read data stream is input to the first one of the plurality of serially connected D-flipflops  30 . 
     As shown in FIG. 5B, if the read data stream has a transition pulse at a first pulse of the sampling frequency signal, the delayed read data stream has a corresponding pulse at the fifth transition pulse of the sampling frequency signal as shown in FIG.  5 C. As further shown in FIG. 5A, the output of the first one of the D-flipflops  30 , and the output of the last one of the D-flipflops  30  is received by the OR gate  32 . Accordingly, the OR gate  32  receives the read data stream and the read data stream delayed by ½ a cycle. The output of the OR gate  32  is illustrated in FIG.  5 D. The output of the OR gate  32  serves as an enable signal for the D-flipflop  34 . As shown in FIG. 5A, the inverted output of the D-flipflop  34  is connected to the input of the D-flipflop  34 , while the non-inverted output of the D-flipflop  34  serves as the output of the read gate signal. FIG. 5E illustrates the read gate signal when the read data stream is as shown in FIG.  5 B. 
     Both the delayed read data stream and the read gate signal are supplied to the multiplexer  24 . The delayed read data stream is also supplied to the frequency divider  22  as a reset signal to synchronize the output of the frequency divider  22  with the delayed read data. In accordance with this synchronization, the frequency divider  22  frequency divides the sampling frequency by a predetermined dividing ratio. For instance, the signal output from the frequency divider  22  has a cycle of 1 μs when the data rate is 500 Kbps. FIG. 4B illustrates the output of the frequency divider  22 . As shown in FIG. 4B, the frequency divider  22  outputs a signal having transition pulses h. FIG. 4C illustrates the read data stream and the delayed read data signal from which the frequency divider  22  produced the frequency divided signal of FIG.  4 B. FIG. 4D illustrates the read gate signal generated when the delayed read data signal is as shown in FIG.  4 C. The duration of the transition pulses of the read gate signal are about 1 μs. As shown in FIGS. 4C and 4D, the delayed read data signal has transition pulses f, while the read gate signal has transition pulses g. 
     The multiplexer  24  multiplexes the frequency divided signal output by the frequency divider  22  and the delayed read data signal output by the ¼ cycle delaying part  23  in accordance with the read gate signal output by the gate logic determining part  20 . In operation, the multiplexer  24  will output the delayed read data signal during a transition pulse g of the read gate signal; otherwise, the multiplexer  24  outputs the frequency divided signal. Accordingly, the multiplexer  24  produces an output signal such as shown in FIG. 4E comprised of transition pulses from the delayed read data signal and the frequency divided signal. As discussed in detail above, the output of the multiplexer  24  serves as a reference clock for the DPLL  29 . 
     The operation of the DPLL  29  will now be described in detail. The phase detecting part  25  of the DPLL  29  receives both the window signal and the output of the multiplexer  24 . The phase detecting part  25  produces a first error signal i and a second error signal j indicative of phase error in a first and second direction, respectively. The phase detecting part  25  generates the error signal i and the second error signal j by determining a phase difference state between the reference clock and the window signal as shown in FIG.  6 . 
     State II in FIG. 6 represents the normal operation state. In the normal operation state, the phase detecting part  25  outputs a first error signal i of “1” (i.e., logic level high) and a second error signal j of “0” (i.e., logic level low). The phase detecting part  25  changes state based on the receipt of transition pulses of the reference clock and the window signal. Receipt of a transition pulse of the reference clock from the multiplexer  24  is indicated as condition B in FIG. 6, while receipt of a transition pulse of the window signal is indicated as condition A in FIG.  6 . 
     In state II, if the phase detecting part  25  receives a transition pulse of the reference clock, the phase detecting part  25  switches to state III. In state III, the phase detecting part  25  outputs “1” as both the first error signal i and the second error signal j. In state III, if the phase detecting part  25  receives a transition pulse from the multiplexer  24 , then the phase detecting part  25  remains in state III. If, however, the phase detecting part  25  receives a transition pulse of the window signal, then the phase detecting part  25  changes from state III to state II. 
     In state II, if the phase detecting part  25  receives a transition pulse of the window signal, the phase detecting part  25  switches to state I. In state I, the phase detecting part outputs “0” as both the first error signal i and the second error signal j. While in state I, if the phase detecting part  25  receives a transition pulse of the window signal, then the phase detecting part  25  remains in state I. If, however, the phase detecting part  25  receives a transition pulse from the multiplexer  24 , the phase detecting part  25  switches from state I to state II. As indicated in FIG. 6, state III represents the fast state wherein the data rate of data being read from the floppy disk has increased, while state I represents the slow state wherein the data rate of data being read from the floppy disk has decreased. 
     The phase/frequency controlling part  26  receives both the first error signal i and the second error signal j. The phase/frequency controlling part  26  measures the total amount of time the phase detecting part  25  achieves state III during a predetermining period of time, and also measures the total amount of time the phase detecting part  25  achieves state I during the predetermined period of time. The phase/frequency controlling part  26  establishes the predetermined period of time as the time period between leading edges of consecutively received read gate signals. This operation will be described in greater detail with respect to FIGS. 7A-7C. 
     FIG. 7A illustrates the output of the multiplexer  24 . As shown in FIG. 7A, the predetermined period of time referred to as the counting section coincides with the leading edge of consecutively received transition pulses f in the output of the multiplexer  24 . For purposes of discussion, it has been assumed that the leading edges of the transition pulses f coincide with the leading edges of consecutively received transition pulses of the read gate signal. 
     When the fast state occurs, the transition pulses of the window signal such as shown in FIG. 7B lag behind the transition pulses of the reference clock output by the multiplexer  24  shown in FIG.  7 A. Consequently, the phase detecting part  25  produces the first error signal i and the second error signal j as shown in FIG.  7 B. 
     During the counting section, the phase/frequency controlling part  26  measures the number of transition pulses of the sampling frequency signal (i.e., slices) which occur when the first error signal i is low to produce a first count, and measures the number of slices during the counting section when the second error signal j is high to produce a second count. For instance, in FIG. 7B, the first count will be 0, while the second count will be 13. 
     FIG. 7C illustrates the slow state where the transition pulses of the window signal lead the transition pulses of the reference clock output by the multiplexer  24 . In this instance, the phase detecting part  25  generates first error signal i and a second error signal j as shown in FIG.  7 C. In the case of FIG. 7C, the phase/frequency controlling part  26  will generate a first count of 15, and a second count of 0. 
     After generating the first and second count, the phase/frequency controlling part  26  then generates a control signal. The control signal may be a no change (NC) control signal, an increment change (IC) control signal, and a decrement change (DC) control signal. The control signal is generated by summing the first and second counts to produce a phase control value. Then, in accordance with FIG. 8, the phase/frequency controlling part  26  determines whether or not to produce an NC control signal, IC control signal, or DC control signal. As shown in FIG. 8, when the phase control value is between +2 and −2, the phase/frequency controlling part  26  generates an NC control signal. When the phase control value exceeds +2, the phase/frequency controlling part  26  generates an IC control signal, and when the phase control value is below −2, the phase/frequency controlling part  26  generates a DC control signal. 
     FIG. 9 illustrates the operation state achieved in accordance with the control signal output by the phase/frequency controlling part  26 . As shown in FIG. 9, in the normal operation state, if an NC control signal is received, the normal operation state is maintained. If, however, an IC control signal is received, then the fast operation state (i.e., the state when the data rate has increased) is achieved. While in the fast state, if an NC or IC control signal is received, the fast state is maintained, while if a DC control signal is received, the state changes from the fast state to the normal state. 
     When in the normal state, if a DC control signal is received, the slow state is achieved. While in the slow state, if an NC or DC control signal is received, the slow state is maintained. If an IC control signal is received, then the state changes from the slow state to the normal state. 
     The digital control oscillator  27  receives the control signal from the phase/frequency controlling part  16 . The operation of the digital control oscillator  27  will be described with respect to FIGS. 10A-10D. As shown in FIG. 10A, the digital control oscillator  27  includes a variation length shift register. For purposes of discussion, FIG. 10C will be assumed to represent the normal operation state such as shown in FIG.  9 . FIG. 10C illustrates the time period between the previously generated transition pulse o and a next transition pulse p of the window signal, the relationship between consecutively generated pulses with respect to the variation length shift register, the relationship with respect to the phase control value to be determined by the phase/frequency controlling part  26 , and the control signal generation ranges. Accordingly, as long as the NC control signal is received by the digital control oscillator  27 , the digital control oscillator  27  will continue to generate a next transition pulse p at the frequency established in  10 C. 
     If, however, the digital control oscillator  27  receives an IC control signal indicating the fast state, the digital control oscillator  27  decrements the period between consecutively generated transition pulses of the window signal by one cycle of the sampling frequency signal. This earlier generation of the next transition pulse p of the window signal is illustrated in FIG.  10 B. FIG. 10B also illustrates the new relationship between the window signal and the phase control values and the relationship between the window signal and the control signal generation ranges. In accordance with subsequently received IC signals, the digital control oscillator  27  will further decrement the time period between consecutively generated transition pulses of the window signal. 
     If the digital control signal  27 , however, receives a DC signal, then the digital control oscillator  27  will lengthen the time period between the previously generated transition pulse  0  and the next transition pulse p of the window signal as shown in FIG.  10 D. The time period between consecutively generated transition pulses of the window signal will be incremented by one cycle of the sampling frequency signal. FIG. 10D further illustrates the relationship between the window signal and the phase control values, and the relationship between the window signal and the control signal generation ranges. 
     In this manner, the digital control oscillator  27  locks the frequency of the window signal to the reference clock such as shown in FIGS. 7A-7C. Therefore, even when the data rate with which data is read from the floppy disk changes as shown by arrows e in FIG. 3B, a corresponding change in the window signal is achieved such that the data/clock signal outputting part  28  can continue to generate a data signal and clock signal from the delayed read data signal. 
     Because the data separation circuit of the present invention includes the DPLL  29 , the data separation circuit does not require the use of a VCO. As such, there is no need to control the frequency, gain, and current component of the VCO. In this manner, the present invention removes the unstable properties resident in conventional data separation circuits utilizing voltage control oscillators. Consequently, even in the face of variations which occur during the manufacturing process, the data separation circuit according to the present invention can stably and more reliably retrieve data read out by a floppy disk drive. 
     In addition, using the DPLL  29  according to the present invention allows for the data separation circuit to be reduced, and because the DPLL  29  simultaneously controls phase and frequency, the data separation characteristic is enhanced. 
     While the invention has been described in connection with what is presently considered the most practical and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.