Patent Publication Number: US-8981839-B2

Title: Power source multiplexer

Description:
RELATED APPLICATIONS 
     This application claims the benefit of U.S. provisional patent application No. 61/658,013, filed Jun. 11, 2012, the disclosure of which is incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE DISCLOSURE 
     Embodiments of the present disclosure relate to circuits that are powered using power sources and circuits that interface the power sources to the circuits that are powered using the power sources. 
     BACKGROUND 
     Certain circuits may be powered from different power sources depending upon specific operating conditions. For example, a circuit may be powered from one power source when operating within a certain input power range and may be powered from another power source when operating within another input power range. Thus, there is a need for a circuit, which is used to direct power from at least one of at least two power sources to a circuit based upon specific operating conditions. 
     SUMMARY 
     Circuitry, which includes a first switching transistor element having a first gate, a second switching transistor element having a second gate, a third switching transistor element having a third gate, and a fourth switching transistor element having a fourth gate, is disclosed. The first switching transistor element and the third switching transistor element are coupled in series between a first power source and a first downstream circuit. The second switching transistor element and the fourth switching transistor element are coupled in series between a second power source and the first downstream circuit. A voltage swing at the first gate is about equal to a first voltage magnitude. A voltage swing at the second gate is about equal to the first voltage magnitude. A voltage swing at the third gate is about equal to a second voltage magnitude. A voltage swing at the fourth gate is about equal to the second voltage magnitude. 
     In one embodiment of the circuitry, the first voltage magnitude is about equal to a magnitude of an output voltage from the first power source, and the second voltage magnitude is about equal to a magnitude of an output voltage from the second power source. In one embodiment of the circuitry, the first switching transistor element, the second switching transistor element, the third switching transistor element, and the fourth switching transistor element form a power source multiplexer. 
     Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
         FIG. 1  shows circuitry according to one embodiment of the present disclosure. 
         FIG. 2  shows the circuitry according to an alternate embodiment of the circuitry. 
         FIG. 3  shows details of a first power source multiplexer illustrated in  FIG. 1  according to an alternate embodiment of the first power source multiplexer. 
         FIG. 4  shows details of a second power source multiplexer illustrated in  FIG. 1  according to an alternate embodiment of the second power source multiplexer. 
         FIG. 5  shows details of the first power source multiplexer illustrated in  FIG. 1  according to an additional embodiment of the first power source multiplexer. 
         FIG. 6  shows details of the first power source multiplexer and the second power source multiplexer illustrated in  FIG. 1  according to another embodiment of the first power source multiplexer and the second power source multiplexer. 
         FIG. 7  shows the circuitry according to an additional embodiment of the circuitry. 
         FIG. 8  shows the circuitry according to another embodiment of the circuitry. 
         FIG. 9  shows the circuitry according to a further embodiment of the circuitry. 
         FIG. 10  shows the circuitry according to a supplemental embodiment of the circuitry. 
         FIG. 11  shows radio frequency (RF) circuitry according to one embodiment of the present disclosure. 
         FIG. 12  shows the RF circuitry according to an alternate embodiment of the RF circuitry. 
         FIG. 13  shows details of an envelope tracking power supply illustrated in  FIG. 11  according to one embodiment of the envelope tracking power supply. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
       FIG. 1  shows circuitry  10  according to one embodiment of the present disclosure. The circuitry  10  includes a first power source multiplexer  12  and a second power source multiplexer  14 . As such, structures of the first power source multiplexer  12  and the second power source multiplexer  14  are presented. The first power source multiplexer  12  includes a first switching transistor element  16 , a second switching transistor element  18 , a third switching transistor element  20 , and a fourth switching transistor element  22 . The first switching transistor element  16  has a first gate  24 , the second switching transistor element  18  has a second gate  26 , the third switching transistor element  20  has a third gate  28 , and the fourth switching transistor element  22  has a fourth gate  30 . The first gate  24  receives a first gate signal GS 1 , the second gate  26  receives a second gate signal GS 2 , the third gate  28  receives a third gate signal GS 3 , and the fourth gate  30  receives a fourth gate signal GS 4 . 
     The second power source multiplexer  14  includes a fifth switching transistor element  32 , a sixth switching transistor element  34 , a seventh switching transistor element  36 , and an eighth switching transistor element  38 . The fifth switching transistor element  32  has a fifth gate  40 , the sixth switching transistor element  34  has a sixth gate  42 , the seventh switching transistor element  36  has a seventh gate  44 , and the eighth switching transistor element  38  has an eighth gate  46 . The fifth gate  40  receives a fifth gate signal GS 5 , the sixth gate  42  receives a sixth gate signal GS 6 , the seventh gate  44  receives a seventh gate signal GS 7 , and the eighth gate  46  receives an eighth gate signal GS 8 . 
     A first power source  48  is coupled to both the first power source multiplexer  12  and the second power source multiplexer  14 . A second power source  50  is coupled to both the first power source multiplexer  12  and the second power source multiplexer  14 . The first power source multiplexer  12  is coupled to a first downstream circuit  52 . The second power source multiplexer  14  is coupled to a second downstream circuit  54 . In another embodiment of the circuitry  10 , the second power source multiplexer  14  and the second downstream circuit  54  are both omitted. 
     The first switching transistor element  16  and the third switching transistor element  20  are coupled in series between the first power source  48  and the first downstream circuit  52 . The second switching transistor element  18  and the fourth switching transistor element  22  are coupled in series between the second power source  50  and the first downstream circuit  52 . The fifth switching transistor element  32  and the seventh switching transistor element  36  are coupled in series between the first power source  48  and the second downstream circuit  54 . The sixth switching transistor element  34  and the eighth switching transistor element  38  are coupled in series between the second power source  50  and the second downstream circuit  54 . 
     The first power source  48  provides a first power source output signal PS 1  to both the first power source multiplexer  12  and the second power source multiplexer  14 . The second power source  50  provides a second power source output signal PS 2  to both the first power source multiplexer  12  and the second power source multiplexer  14 . The first power source multiplexer  12  provides a first multiplexer output signal MUX 1  to the first downstream circuit  52 . The second power source multiplexer  14  provides a second multiplexer output signal MUX 2  to the second downstream circuit  54 . 
     In one embodiment of the first power source multiplexer  12 , each of the first switching transistor element  16 , the second switching transistor element  18 , the third switching transistor element  20 , and the fourth switching transistor element  22  is a P-type field effect transistor (PFET) transistor element, as shown. Further, in one embodiment of the first power source multiplexer  12 , each of the first switching transistor element  16 , the second switching transistor element  18 , the third switching transistor element  20 , and the fourth switching transistor element  22  is an enhancement mode field effect transistor element. 
     In one embodiment of the second power source multiplexer  14 , each of the fifth switching transistor element  32 , the sixth switching transistor element  34 , the seventh switching transistor element  36 , and the eighth switching transistor element  38  is a PFET transistor element, as shown. Further, in one embodiment of the second power source multiplexer  14 , each of the fifth switching transistor element  32 , the sixth switching transistor element  34 , the seventh switching transistor element  36 , and the eighth switching transistor element  38  is an enhancement mode field effect transistor element. 
     In this regard, in one embodiment of an enhancement mode PFET transistor element, the enhancement mode PFET transistor element is in an ON state when a gate voltage of the enhancement mode PFET transistor element is negative with respect to a source voltage of the enhancement mode PFET transistor element. Conversely, the enhancement mode PFET transistor element is in an OFF state when the gate voltage of the enhancement mode PFET transistor element is about equal to the source voltage of the enhancement mode PFET transistor element. 
     In one embodiment of the first power source  48 , the first power source output signal PS 1  provides a first output voltage having a first voltage magnitude. As such, the first power source  48  provides the first output voltage having the first voltage magnitude. Similarly, in one embodiment of the second power source  50 , the second power source output signal PS 2  provides a second output voltage having a second voltage magnitude. As such, the second power source  50  provides the second output voltage having the second voltage magnitude. 
     In one embodiment of the first power source multiplexer  12 , the first power source multiplexer  12  receives and forwards a selected one of the first power source output signal PS 1  and the second power source output signal PS 2  to provide the first multiplexer output signal MUX 1  to the first downstream circuit  52 . Similarly, in one embodiment of the second power source multiplexer  14 , the second power source multiplexer  14  receives and forwards a selected one of the first power source output signal PS 1  and the second power source output signal PS 2  to provide the second multiplexer output signal MUX 2  to the second downstream circuit  54 . 
     In order to properly forward the first power source output signal PS 1  to the first downstream circuit  52 , both the first switching transistor element  16  and the third switching transistor element  20  must be in the ON state, and either the second switching transistor element  18  or the fourth switching transistor element  22 , or both, must be in the OFF state. Conversely, in order to properly forward the second power source output signal PS 2  to the first downstream circuit  52 , either the first switching transistor element  16  or the third switching transistor element  20 , or both, must be in the OFF state, and both the second switching transistor element  18  and the fourth switching transistor element  22  must be in the ON state. 
     To provide the proper functionality as described above, a voltage swing at the first gate  24  is about equal to the first voltage magnitude, a voltage swing at the second gate  26  is about equal to the first voltage magnitude, a voltage swing at the third gate  28  is about equal to the second voltage magnitude, and a voltage swing at the fourth gate  30  is about equal to the second voltage magnitude. In general, when the first gate signal GS 1  is presented to the first gate  24 , the voltage swing at the first gate  24  is about equal to the first voltage magnitude. When the second gate signal GS 2  is presented to the second gate  26 , the voltage swing at the second gate  26  is about equal to the first voltage magnitude. When the third gate signal GS 3  is presented to the third gate  28 , the voltage swing at the third gate  28  is about equal to the second voltage magnitude. When the fourth gate signal GS 4  is presented to the fourth gate  30 , the voltage swing at the fourth gate  30  is about equal to the second voltage magnitude. 
     In order to properly forward the first power source output signal PS 1  to the second downstream circuit  54 , both the fifth switching transistor element  32  and the seventh switching transistor element  36  must be in the ON state, and either the sixth switching transistor element  34  or the eighth switching transistor element  38 , or both, must be in the OFF state. Conversely, In order to properly forward the second power source output signal PS 2  to the second downstream circuit  54 , either the fifth switching transistor element  32  or the seventh switching transistor element  36 , or both, must be in the OFF state, and both the sixth switching transistor element  34  and the eighth switching transistor element  38  must be in the ON state. 
     To provide the proper functionality as described above, a voltage swing at the fifth gate  40  is about equal to the first voltage magnitude, a voltage swing at the sixth gate  42  is about equal to the first voltage magnitude, a voltage swing at the seventh gate  44  is about equal to the second voltage magnitude, and a voltage swing at the eighth gate  46  is about equal to the second voltage magnitude. In general, when the fifth gate signal GS 5  is presented to the fifth gate  40 , the voltage swing at the fifth gate  40  is about equal to the first voltage magnitude. When the sixth gate signal GS 6  is presented to the sixth gate  42 , the voltage swing at the sixth gate  42  is about equal to the first voltage magnitude. When the seventh gate signal GS 7  is presented to the seventh gate  44 , the voltage swing at the seventh gate  44  is about equal to the second voltage magnitude. When the eighth gate signal GS 8  is presented to the eighth gate  46 , the voltage swing at the eighth gate  46  is about equal to the second voltage magnitude. 
     Detailed operation of the first power source multiplexer  12  under different operating conditions is presented. In a first embodiment of the circuitry  10 , the first voltage magnitude is about equal to the second voltage magnitude and the first power source output signal PS 1  is forwarded to the first downstream circuit  52 . As such, both the first switching transistor element  16  and the third switching transistor element  20  must be in the ON state, and either the second switching transistor element  18  or the fourth switching transistor element  22 , or both, must be in the OFF state. Both the first gate  24  and the third gate  28  are driven to about ground, thereby forcing both the first switching transistor element  16  and the third switching transistor element  20  into the ON state. The second gate  26  is driven to about the first voltage magnitude. However, since the first voltage magnitude is about equal to the second voltage magnitude, the second switching transistor element  18  is in the OFF state. The fourth gate  30  is driven to the second voltage magnitude, thereby forcing the fourth switching transistor element  22  into the OFF state. 
     In a second embodiment of the circuitry  10 , the first voltage magnitude is about equal to the second voltage magnitude and the second power source output signal PS 2  is forwarded to the first downstream circuit  52 . As such, either the first switching transistor element  16  or the third switching transistor element  20 , or both, must be in the OFF state, and both the second switching transistor element  18  and the fourth switching transistor element  22  must be in the ON state. Both the second gate  26  and the fourth gate  30  are driven to about ground, thereby forcing both the second switching transistor element  18  and the fourth switching transistor element  22  into the ON state. The first gate  24  is driven to about the first voltage magnitude, thereby forcing the first switching transistor element  16  into the OFF state. The third gate  28  is driven to about the second voltage magnitude. However, since the first voltage magnitude is about equal to the second voltage magnitude, the third switching transistor element  20  is in the OFF state. 
     In one embodiment of the circuitry  10 , the first voltage magnitude is not equal to the second voltage magnitude. As such, in a third embodiment of the circuitry  10 , the first voltage magnitude is greater than the second voltage magnitude and the first power source output signal PS 1  is forwarded to the first downstream circuit  52 . As such, both the first switching transistor element  16  and the third switching transistor element  20  must be in the ON state, and either the second switching transistor element  18  or the fourth switching transistor element  22 , or both, must be in the OFF state. Both the first gate  24  and the third gate  28  are driven to about ground, thereby forcing both the first switching transistor element  16  and the third switching transistor element  20  into the ON state. The second gate  26  is driven to about the first voltage magnitude. However, since the first voltage magnitude is greater than the second voltage magnitude, the second switching transistor element  18  is in the OFF state. The fourth gate  30  is driven to the second voltage magnitude, thereby forcing the fourth switching transistor element  22  into the OFF state. 
     In a fourth embodiment of the circuitry  10 , the first voltage magnitude is greater than the second voltage magnitude and the second power source output signal PS 2  is forwarded to the first downstream circuit  52 . As such, either the first switching transistor element  16  or the third switching transistor element  20 , or both, must be in the OFF state, and both the second switching transistor element  18  and the fourth switching transistor element  22  must be in the ON state. Both the second gate  26  and the fourth gate  30  are driven to about ground, thereby forcing both the second switching transistor element  18  and the fourth switching transistor element  22  into the ON state. The first gate  24  is driven to about the first voltage magnitude, thereby forcing the first switching transistor element  16  into the OFF state. The third gate  28  is driven to about the second voltage magnitude. However, since the first voltage magnitude is greater than the second voltage magnitude, the third switching transistor element  20  may not be in the OFF state. Therefore, the first switching transistor element  16  isolates the first power source  48  from the first downstream circuit  52 . 
     In a fifth embodiment of the circuitry  10 , the first voltage magnitude is less than the second voltage magnitude and the first power source output signal PS 1  is forwarded to the first downstream circuit  52 . As such, both the first switching transistor element  16  and the third switching transistor element  20  must be in the ON state, and either the second switching transistor element  18  or the fourth switching transistor element  22 , or both, must be in the OFF state. Both the first gate  24  and the third gate  28  are driven to about ground, thereby forcing both the first switching transistor element  16  and the third switching transistor element  20  into the ON state. The second gate  26  is driven to about the first voltage magnitude. However, since the first voltage magnitude is less than the second voltage magnitude, the second switching transistor element  18  may not be in the OFF state. The fourth gate  30  is driven to the second voltage magnitude, thereby forcing the fourth switching transistor element  22  into the OFF state. Therefore, the fourth switching transistor element  22  isolates the second power source  50  from the first downstream circuit  52 . 
     In a sixth embodiment of the circuitry  10 , the first voltage magnitude is less than the second voltage magnitude and the second power source output signal PS 2  is forwarded to the first downstream circuit  52 . As such, either the first switching transistor element  16  or the third switching transistor element  20 , or both, must be in the OFF state, and both the second switching transistor element  18  and the fourth switching transistor element  22  must be in the ON state. Both the second gate  26  and the fourth gate  30  are driven to about ground, thereby forcing both the second switching transistor element  18  and the fourth switching transistor element  22  into the ON state. The first gate  24  is driven to about the first voltage magnitude, thereby forcing the first switching transistor element  16  into the OFF state. The third gate  28  is driven to about the second voltage magnitude. However, since the first voltage magnitude is less than the second voltage magnitude, the third switching transistor element  20  is in the OFF state. 
       FIG. 2  shows the circuitry  10  according to an alternate embodiment of the circuitry  10 . The circuitry  10  illustrated in  FIG. 2  is similar to the circuitry  10  illustrated in  FIG. 1 , except the circuitry  10  illustrated in  FIG. 2  further includes the first power source  48 , the second power source  50 , the first downstream circuit  52 , and the second downstream circuit  54 . In a first exemplary embodiment of the circuitry  10 , the first power source  48  is provided external to the circuitry  10 . In a second exemplary embodiment of the circuitry  10 , the second power source  50  is provided external to the circuitry  10 . In a third exemplary embodiment of the circuitry  10 , the first downstream circuit  52  is provided external to the circuitry  10 . In a fourth exemplary embodiment of the circuitry  10 , the second downstream circuit  54  is provided external to the circuitry  10 . In a fifth exemplary embodiment of the circuitry  10 , any or all of the first power source  48 , the second power source  50 , the first downstream circuit  52 , and the second downstream circuit  54  are provided external to the circuitry  10 . 
     In one embodiment of the first power source  48 , the first power source  48  is a battery. In one embodiment of the second power source  50 , the second power source  50  is a DC-DC converter. In one embodiment of the DC-DC converter, the DC-DC converter uses charge pump based DC-DC conversion. In an alternate embodiment of the DC-DC converter, the DC-DC converter uses inductor based DC-DC conversion. In an additional embodiment of the DC-DC converter, the DC-DC converter uses both charge pump based DC-DC conversion and inductor based DC-DC conversion. 
     In an alternate embodiment of the first power source  48 , the first power source  48  is a supplemental DC-DC converter. In one embodiment of the supplemental DC-DC converter, the supplemental DC-DC converter uses charge pump based DC-DC conversion. In an alternate embodiment of the supplemental DC-DC converter, the supplemental DC-DC converter uses inductor based DC-DC conversion. In an additional embodiment of the supplemental DC-DC converter, the supplemental DC-DC converter uses both charge pump based DC-DC conversion and inductor based DC-DC conversion. 
     In another embodiment of the circuitry  10 , the second power source multiplexer  14  and the second downstream circuit  54  are both omitted. As such, the fifth switching transistor element  32 , the sixth switching transistor element  34 , the seventh switching transistor element  36 , and the eighth switching transistor element  38  are omitted. 
       FIG. 3  shows details of the first power source multiplexer  12  illustrated in  FIG. 1  according to an alternate embodiment of the first power source multiplexer  12 . The first power source multiplexer  12  illustrated in  FIG. 3  is similar to the first power source multiplexer  12  illustrated in  FIG. 1 , except the first power source multiplexer  12  illustrated in  FIG. 3  further includes a first gate driver  56 , a second gate driver  58 , a third gate driver  60 , and a fourth gate driver  62 . 
     The first gate driver  56  is coupled to the first gate  24 . The second gate driver  58  is coupled to the second gate  26 . The third gate driver  60  is coupled to the third gate  28 . The fourth gate driver  62  is coupled to the fourth gate  30 . The first gate driver  56  and the third gate driver  60  receive a first enable signal EN 1 . The second gate driver  58  and the fourth gate driver  62  receive a second enable signal EN 2 . Additionally, the first gate driver  56  and the second gate driver  58  receive the first power source output signal PS 1 . The third gate driver  60  and the fourth gate driver  62  receive the second power source output signal PS 2 . A voltage swing of the first enable signal EN 1  is about equal to a logic level voltage swing. Similarly, a voltage swing of the second enable signal EN 2  is about equal to the logic level voltage swing. 
     The first gate driver  56  provides the first gate signal GS 1  to the first gate  24  based on the first enable signal EN 1  and the first power source output signal PS 1 . Specifically, in one embodiment of the first gate driver  56 , a logic level of the first gate signal GS 1  is based on a logic level of the first enable signal EN 1 . In one embodiment of the first power source  48 , the first power source output signal PS 1  provides the first output voltage having the first voltage magnitude. As such, a voltage swing of the first gate signal GS 1  is about equal to the first voltage magnitude. Therefore, the voltage swing at the first gate  24  is about equal to the first voltage magnitude. In one embodiment of the first gate driver  56 , a voltage swing of the first enable signal EN 1  is not equal to the voltage swing of the first gate signal GS 1 . Therefore, the first gate driver  56  provides appropriate level translation to the first enable signal EN 1  for proper operation. In a first embodiment of the first gate driver  56 , the first gate driver  56  applies a logic inversion to the first enable signal EN 1  to provide the first gate signal GS 1 . In a second embodiment of the first gate driver  56 , the first gate driver  56  does not apply a logic inversion to the first enable signal EN 1  to provide the first gate signal GS 1 . 
     The second gate driver  58  provides the second gate signal GS 2  to the second gate  26  based on the second enable signal EN 2  and the first power source output signal PS 1 . Specifically, in one embodiment of the second gate driver  58 , a logic level of the second gate signal GS 2  is based on the logic level of the second enable signal EN 2 . In one embodiment of the first power source  48 , the first power source output signal PS 1  provides the first output voltage having the first voltage magnitude. As such, a voltage swing of the second gate signal GS 2  is about equal to the first voltage magnitude. Therefore, the voltage swing at the second gate  26  is about equal to the first voltage magnitude. In one embodiment of the second gate driver  58 , a voltage swing of the second enable signal EN 2  is not equal to the voltage swing of the second gate signal GS 2 . Therefore, the second gate driver  58  provides appropriate level translation to the second enable signal EN 2  for proper operation. In a first embodiment of the second gate driver  58 , the second gate driver  58  applies a logic inversion to the second enable signal EN 2  to provide the second gate signal GS 2 . In a second embodiment of the second gate driver  58 , the second gate driver  58  does not apply a logic inversion to the second enable signal EN 2  to provide the second gate signal GS 2 . 
     The third gate driver  60  provides the third gate signal GS 3  to the third gate  28  based on the first enable signal EN 1  and the second power source output signal PS 2 . Specifically, in one embodiment of the third gate driver  60 , a logic level of the third gate signal GS 3  is based on a logic level of the first enable signal EN 1 . In one embodiment of the second power source  50 , the second power source output signal PS 2  provides the second output voltage having the second voltage magnitude. As such, a voltage swing of the third gate signal GS 3  is about equal to the second voltage magnitude. Therefore, the voltage swing at the third gate  28  is about equal to the second voltage magnitude. In one embodiment of the third gate driver  60 , a voltage swing of the first enable signal EN 1  is not equal to the voltage swing of the third gate signal GS 3 . Therefore, the third gate driver  60  provides appropriate level translation to the first enable signal EN 1  for proper operation. In a first embodiment of the third gate driver  60 , the third gate driver  60  applies a logic inversion to the first enable signal EN 1  to provide the third gate signal GS 3 . In a second embodiment of the third gate driver  60 , the third gate driver  60  does not apply a logic inversion to the first enable signal EN 1  to provide the third gate signal GS 3 . 
     The fourth gate driver  62  provides the fourth gate signal GS 4  to the fourth gate  30  based on the second enable signal EN 2  and the second power source output signal PS 2 . Specifically, in one embodiment of the fourth gate driver  62 , a logic level of the fourth gate signal GS 4  is based on the logic level of the second enable signal EN 2 . In one embodiment of the second power source  50 , the second power source output signal PS 2  provides the second output voltage having the second voltage magnitude. As such, a voltage swing of the fourth gate signal GS 4  is about equal to the second voltage magnitude. Therefore, the voltage swing at the fourth gate  30  is about equal to the second voltage magnitude. In one embodiment of the fourth gate driver  62 , a voltage swing of the second enable signal EN 2  is not equal to the voltage swing of the fourth gate signal GS 4 . Therefore, the fourth gate driver  62  provides appropriate level translation to the second enable signal EN 2  for proper operation. In a first embodiment of the fourth gate driver  62 , the fourth gate driver  62  applies a logic inversion to the second enable signal EN 2  to provide the fourth gate signal GS 4 . In a second embodiment of the fourth gate driver  62 , the fourth gate driver  62  does not apply a logic inversion to the second enable signal EN 2  to provide the fourth gate signal GS 4 . 
       FIG. 4  shows details of the second power source multiplexer  14  illustrated in  FIG. 1  according to an alternate embodiment of the second power source multiplexer  14 . The second power source multiplexer  14  illustrated in  FIG. 4  is similar to the second power source multiplexer  14  illustrated in  FIG. 1 , except the second power source multiplexer  14  illustrated in  FIG. 4  further includes a fifth gate driver  64 , a sixth gate driver  66 , a seventh gate driver  68 , and an eighth gate driver  70 . 
     The fifth gate driver  64  is coupled to the fifth gate  40 . The sixth gate driver  66  is coupled to the sixth gate  42 . The seventh gate driver  68  is coupled to the seventh gate  44 . The eighth gate driver  70  is coupled to the eighth gate  46 . The fifth gate driver  64  and the seventh gate driver  68  receive a third enable signal EN 3 . The sixth gate driver  66  and the eighth gate driver  70  receive a fourth enable signal EN 4 . Additionally, the fifth gate driver  64  and the sixth gate driver  66  receive the first power source output signal PS 1 . The seventh gate driver  68  and the eighth gate driver  70  receive the second power source output signal PS 2 . A voltage swing of the third enable signal EN 3  is about equal to a logic level voltage swing. Similarly, a voltage swing of the fourth enable signal EN 4  is about equal to the logic level voltage swing. 
     The fifth gate driver  64  provides the fifth gate signal GS 5  to the fifth gate  40  based on the third enable signal EN 3  and the first power source output signal PS 1 . Specifically, in one embodiment of the fifth gate driver  64 , a logic level of the fifth gate signal GS 5  is based on a logic level of the third enable signal EN 3 . In one embodiment of the first power source  48 , the first power source output signal PS 1  provides the first output voltage having the first voltage magnitude. As such, a voltage swing of the fifth gate signal GS 5  is about equal to the first voltage magnitude. Therefore, the voltage swing at the fifth gate  40  is about equal to the first voltage magnitude. In one embodiment of the fifth gate driver  64 , a voltage swing of the third enable signal EN 3  is not equal to the voltage swing of the fifth gate signal GS 5 . Therefore, the fifth gate driver  64  provides appropriate level translation to the third enable signal EN 3  for proper operation. In a first embodiment of the fifth gate driver  64 , the fifth gate driver  64  applies a logic inversion to the third enable signal EN 3  to provide the fifth gate signal GS 5 . In a second embodiment of the fifth gate driver  64 , the fifth gate driver  64  does not apply a logic inversion to the third enable signal EN 3  to provide the fifth gate signal GS 5 . 
     The sixth gate driver  66  provides the sixth gate signal GS 6  to the sixth gate  42  based on the fourth enable signal EN 4  and the first power source output signal PS 1 . Specifically, in one embodiment of the sixth gate driver  66 , a logic level of the sixth gate signal GS 6  is based on the logic level of the fourth enable signal EN 4 . In one embodiment of the first power source  48 , the first power source output signal PS 1  provides the first output voltage having the first voltage magnitude. As such, a voltage swing of the sixth gate signal GS 6  is about equal to the first voltage magnitude. Therefore, the voltage swing at the sixth gate  42  is about equal to the first voltage magnitude. In one embodiment of the sixth gate driver  66 , a voltage swing of the fourth enable signal EN 4  is not equal to the voltage swing of the sixth gate signal GS 6 . Therefore, the sixth gate driver  66  provides appropriate level translation to the fourth enable signal EN 4  for proper operation. In a first embodiment of the sixth gate driver  66 , the sixth gate driver  66  applies a logic inversion to the fourth enable signal EN 4  to provide the sixth gate signal GS 6 . In a second embodiment of the sixth gate driver  66 , the sixth gate driver  66  does not apply a logic inversion to the fourth enable signal EN 4  to provide the sixth gate signal GS 6 . 
     The seventh gate driver  68  provides the seventh gate signal GS 7  to the seventh gate  44  based on the third enable signal EN 3  and the second power source output signal PS 2 . Specifically, in one embodiment of the seventh gate driver  68 , a logic level of the seventh gate signal GS 7  is based on a logic level of the third enable signal EN 3 . In one embodiment of the second power source  50 , the second power source output signal PS 2  provides the second output voltage having the second voltage magnitude. As such, a voltage swing of the seventh gate signal GS 7  is about equal to the second voltage magnitude. Therefore, the voltage swing at the seventh gate  44  is about equal to the second voltage magnitude. In one embodiment of the seventh gate driver  68 , a voltage swing of the third enable signal EN 3  is not equal to the voltage swing of the seventh gate signal GS 7 . Therefore, the seventh gate driver  68  provides appropriate level translation to the third enable signal EN 3  for proper operation. In a first embodiment of the seventh gate driver  68 , the seventh gate driver  68  applies a logic inversion to the third enable signal EN 3  to provide the seventh gate signal GS 7 . In a second embodiment of the seventh gate driver  68 , the seventh gate driver  68  does not apply a logic inversion to the third enable signal EN 3  to provide the seventh gate signal GS 7 . 
     The eighth gate driver  70  provides the eighth gate signal GS 8  to the eighth gate  46  based on the fourth enable signal EN 4  and the second power source output signal PS 2 . Specifically, in one embodiment of the eighth gate driver  70 , a logic level of the eighth gate signal GS 8  is based on the logic level of the fourth enable signal EN 4 . In one embodiment of the second power source  50 , the second power source output signal PS 2  provides the second output voltage having the second voltage magnitude. As such, a voltage swing of the eighth gate signal GS 8  is about equal to the second voltage magnitude. Therefore, the voltage swing at the eighth gate  46  is about equal to the second voltage magnitude. In one embodiment of the eighth gate driver  70 , a voltage swing of the fourth enable signal EN 4  is not equal to the voltage swing of the eighth gate signal GS 8 . Therefore, the eighth gate driver  70  provides appropriate level translation to the fourth enable signal EN 4  for proper operation. In a first embodiment of the eighth gate driver  70 , the eighth gate driver  70  applies a logic inversion to the fourth enable signal EN 4  to provide the eighth gate signal GS 8 . In a second embodiment of the eighth gate driver  70 , the eighth gate driver  70  does not apply a logic inversion to the fourth enable signal EN 4  to provide the eighth gate signal GS 8 . 
       FIG. 5  shows details of the circuitry  10  according to one embodiment of the circuitry  10 . The circuitry  10  illustrated in  FIG. 5  is similar to the circuitry  10  illustrated in  FIG. 2 , except in the circuitry  10  illustrated in  FIG. 5 , the first power source multiplexer  12  further includes a first series coupling  72 , a second series coupling  74 , and up to and including an N TH  series coupling  76 . In general, the first power source multiplexer  12  includes a group of series couplings  72 ,  74 ,  76 . Additionally, the circuitry  10  illustrated in  FIG. 5  includes the first power source  48 , the second power source  50 , and up to and including an N TH  power source  78 . In general, the circuitry  10  illustrated in  FIG. 5  includes a group of power sources  48 ,  50 ,  78 . 
     The first series coupling  72  includes the first switching transistor element  16 , the third switching transistor element  20 , and up to and including an N TH  first coupling switching transistor element  80 . In general, the first series coupling  72  includes a first group of switching transistor elements  16 ,  20 ,  80 . The second series coupling  74  includes the second switching transistor element  18 , the fourth switching transistor element  22 , and up to and including an N TH  second coupling switching transistor element  82 . In general, the second series coupling  74  includes a second group of switching transistor elements  18 ,  22 ,  82 . The N TH  series coupling  76  includes a first N TH  coupling switching transistor element  84 , a second N TH  coupling switching transistor element  86 , and up to and including an N TH  N TH  coupling switching transistor element  88 . In general, the N TH  series coupling  76  includes an N TH  group of switching transistor elements  84 ,  86 ,  88 . 
     All of the first group of switching transistor elements  16 ,  20 ,  80  are coupled in series between the first power source  48  and the first downstream circuit  52  ( FIG. 2 ). All of the second group of switching transistor elements  18 ,  22 ,  82  are coupled between the second power source  50  and the first downstream circuit  52  ( FIG. 2 ). All of the N TH  group of switching transistor elements  84 ,  86 ,  88  are coupled between the N TH  power source  78  and the first downstream circuit  52  ( FIG. 2 ). In general, each of the group of series couplings  72 ,  74 ,  76  includes a corresponding group of switching transistor elements coupled in series between a corresponding one of the group of power sources  48 ,  50 ,  78  and the first downstream circuit  52  ( FIG. 2 ). 
     The N TH  first coupling switching transistor element  80  has a ninth gate  90 . The ninth gate  90  receives a ninth gate signal GS 9 . The N TH  second coupling switching transistor element  82  has a tenth gate  92 . The tenth gate  92  receives a tenth gate signal GS 10 . The first N TH  coupling switching transistor element  84  has an eleventh gate  94 . The eleventh gate  94  receives an eleventh gate signal GS 11 . The second N TH  coupling switching transistor element  86  has a twelfth gate  96 . The twelfth gate  96  receives a twelfth gate signal GS 12 . The N TH  N TH  coupling switching transistor element  88  has a thirteenth gate  98 . The thirteenth gate  98  receives a thirteenth gate signal GS 13 . 
     The first power source  48  provides the first power source output signal PS 1  to the first series coupling  72 . The first power source output signal PS 1  has the first voltage magnitude. In one embodiment of the first series coupling  72 , the first power source  48  provides the first power source output signal PS 1  to the first switching transistor element  16 . The second power source  50  provides the second power source output signal PS 2  to the second series coupling  74 . The second power source output signal PS 2  has the second voltage magnitude. In one embodiment of the second series coupling  74 , the second power source  50  provides the second power source output signal PS 2  to the second switching transistor element  18 . The N TH  power source  78  provides an N TH  power source output signal PSN to the N TH  series coupling  76 . The N TH  power source output signal PSN has an N TH  voltage magnitude. In one embodiment of the N TH  series coupling  76 , the N TH  power source  78  provides the N TH  power source output signal PSN to the first N TH  coupling switching transistor element  84 . In general, the group of power sources  48 ,  50 ,  78  provides a group of power source output signals PS 1 , PS 2 , PSN to the group of series couplings  72 ,  74 ,  76 . Each of the group of power source output signals PS 1 , PS 2 , PSN has a corresponding one of a group of voltage magnitudes. 
       FIG. 6  shows details of the first power source multiplexer  12  and the second power source multiplexer  14  illustrated in  FIG. 1  according to another embodiment of the first power source multiplexer  12  and the second power source multiplexer  14 . The first power source multiplexer  12  and the second power source multiplexer  14  illustrated in  FIG. 6  are similar to the first power source multiplexer  12  and the second power source multiplexer  14  illustrated in  FIG. 1 , except in the first power source multiplexer  12  and the second power source multiplexer  14  illustrated in  FIG. 6 , each of the first switching transistor element  16 , the second switching transistor element  18 , the third switching transistor element  20 , the fourth switching transistor element  22 , the fifth switching transistor element  32 , the sixth switching transistor element  34 , the seventh switching transistor element  36 , and the eighth switching transistor element  38  is an N-type field effect transistor (NFET) transistor element, as shown. 
     One potential shortcoming of the circuitry  10  illustrated in  FIG. 1  is that to provide the first multiplexer output signal MUX 1  ( FIG. 1 ) or the second multiplexer output signal MUX 2  ( FIG. 1 ), the first power source output signal PS 1  ( FIG. 1 ) or the second power source output signal PS 2  ( FIG. 1 ) must be forwarded through two switching transistor elements coupled in series. For example, the first switching transistor element  16  ( FIG. 1 ) and the third switching transistor element  20  ( FIG. 1 ) are coupled in series between the first power source  48  ( FIG. 1 ) and the first downstream circuit  52  ( FIG. 1 ). A voltage drop across the first switching transistor element  16  ( FIG. 1 ) and the third switching transistor element  20  ( FIG. 1 ) may be problematic in some applications, particularly if the first switching transistor element  16  ( FIG. 1 ) and the third switching transistor element  20  ( FIG. 1 ) are power transistor elements. As such, an embodiment of the circuitry  10  that eliminates one of the voltage drops is presented. 
       FIG. 7  shows the circuitry  10  according to an additional embodiment of the circuitry  10 . The circuitry  10  illustrated in  FIG. 7  is similar to the circuitry  10  illustrated in  FIG. 3 , except in the circuitry  10  illustrated in  FIG. 7 , the first downstream circuit  52  includes a power transistor-based multiplexer  100  and a multiplexer gate driver  102 . The power transistor-based multiplexer  100  includes a first power transistor element  104  and a second power transistor element  106 . The first power transistor element  104  has a first power transistor gate  108  and the second power transistor element  106  has a second power transistor gate  110 . The multiplexer gate driver  102  provides a first power gate signal PGS 1  to the first power transistor gate  108 . Further, the multiplexer gate driver  102  provides a second power gate signal PGS 2  to the second power transistor gate  110 . 
     The first power transistor element  104  is coupled between the first power source  48  and a load  112 . The second power transistor element  106  is coupled between the second power source  50  and the load  112 . A voltage swing at the first power transistor gate  108  is about equal to a maximum voltage magnitude. A voltage swing at the second power transistor gate  110  is about equal to the maximum voltage magnitude. In general, when the first power gate signal PGS 1  is presented to the first power transistor gate  108 , the voltage swing at the first power transistor gate  108  is about equal to the maximum voltage magnitude. Also, when the second power gate signal PGS 2  is presented to the second power transistor gate  110 , the voltage swing at the second power transistor gate  110  is about equal to the maximum voltage magnitude. The maximum voltage magnitude is about equal to either the first voltage magnitude or the second voltage magnitude. If the first voltage magnitude is greater than the second voltage magnitude, then the maximum voltage magnitude is about equal to the first voltage magnitude. If the second voltage magnitude is greater than the first voltage magnitude, then the maximum voltage magnitude is about equal to the second voltage magnitude. If the first voltage magnitude is equal to the second voltage magnitude, then the maximum voltage magnitude is about equal to either the first voltage magnitude or the second voltage magnitude. 
     The first power source multiplexer  12  selects the maximum voltage magnitude based on the first enable signal EN 1  and the second enable signal EN 2 . As such, the first multiplexer output signal MUX 1  has the maximum voltage magnitude. The multiplexer gate driver  102  receives and forwards the first multiplexer output signal MUX 1  to a selected one of the first power transistor element  104  and the second power transistor element  106 . Specifically, the multiplexer gate driver  102  receives and forwards the first multiplexer output signal MUX 1  to either the first power transistor gate  108  or the second power transistor gate  110 . Conversely, the multiplexer gate driver  102  forwards a less than maximum voltage magnitude to an unselected one of the first power transistor element  104  and the second power transistor element  106 . In one embodiment of the less than maximum voltage magnitude, the less than maximum voltage magnitude is equal to about ground. 
     By forwarding the maximum voltage magnitude to the first power transistor gate  108 , the first power transistor element  104  is forced into an OFF state. By forwarding the maximum voltage magnitude to the second power transistor gate  110 , the second power transistor element  106  is forced into the OFF state. By forwarding the less than maximum voltage magnitude to the first power transistor gate  108 , the first power transistor element  104  is forced into an ON state. By forwarding the less than maximum voltage magnitude to the second power transistor gate  110 , the second power transistor element  106  is forced into the ON state. 
     The multiplexer gate driver  102  receives a first select signal SEL 1  and a second select signal SEL 2 . The multiplexer gate driver  102  selects the selected one of the first power transistor element  104  and the second power transistor element  106  based on the first select signal SEL 1  and the second select signal SEL 2 . Further, the multiplexer gate driver  102  determines the unselected one of the first power transistor element  104  and the second power transistor element  106  based on the first select signal SEL 1  and the second select signal SEL 2 . 
     When the unselected one of the first power transistor element  104  and the second power transistor element  106  is the first power transistor element  104 , the first power transistor element  104  is in the ON state, thereby forwarding the first power source output signal PS 1  to provide a load signal LDS to the load  112 . Conversely, when the unselected one of the first power transistor element  104  and the second power transistor element  106  is the second power transistor element  106 , the second power transistor element  106  is in the ON state, thereby forwarding the second power source output signal PS 2  to provide the load signal LDS to the load  112 . 
       FIG. 8  shows the circuitry  10  according to another embodiment of the circuitry  10 . The circuitry  10  illustrated in  FIG. 8  is similar to the circuitry  10  illustrated in  FIG. 7 , except in the circuitry  10  illustrated in  FIG. 8 , the first power source multiplexer  12  receives the first enable signal EN 1 , the second enable signal EN 2 , and up to and including an N TH  enable signal ENN. The multiplexer gate driver  102  receives the first select signal SEL 1 , the second select signal SEL 2 , and up to and including an N TH  select signal SELN. The power transistor-based multiplexer  100  includes the first power transistor element  104 , the second power transistor element  106 , and up to and including an N TH  power transistor element  114 . The N TH  power transistor element  114  has an N TH  power transistor gate  116 , which receives an N TH  power gate signal PGSN. 
     In general, the power transistor-based multiplexer  100  includes a group of power transistor elements  104 ,  106 ,  114 . The group of power sources  48 ,  50 ,  78  provides the group of power source output signals PS 1 , PS 2 , PSN to the first power source multiplexer  12  and to the power transistor-based multiplexer  100 . As such, the group of power sources  48 ,  50 ,  78  provides the group of power source output signals PS 1 , PS 2 , PSN to the group of power transistor elements  104 ,  106 ,  114 . The first power source multiplexer  12  receives a group of enable signals EN 1 , EN 2 , ENN from control circuitry  118  ( FIG. 9 ). The multiplexer gate driver  102  receives a group of select signals SEL 1 , SEL 2 , SELN from the control circuitry  118  ( FIG. 9 ). The multiplexer gate driver  102  provides a group of power gate signals PGS 1 , PGS 2 , PGSN to the group of power transistor elements  104 ,  106 ,  114 . The group of power transistor elements  104 ,  106 ,  114  includes a group of power transistor gates  108 ,  110 ,  116 . As such, the multiplexer gate driver  102  provides the group of power gate signals PGS 1 , PGS 2 , PGSN to the group of power transistor gates  108 ,  110 ,  116 . 
     The group of power sources  48 ,  50 ,  78  includes the first power source  48 , the second power source  50 , and up to and including the N TH  power source  78 . The first power transistor element  104  is coupled between the first power source  48  and the load  112 . The second power transistor element  106  is coupled between the second power source  50  and the load  112 . The N TH  power transistor element  114  is coupled between the N TH  power source  78  and the load  112 . In general, each of the group of power transistor elements  104 ,  106 ,  114  is coupled between a corresponding one of the group of power sources  48 ,  50 ,  78  and the load  112 . 
     Each of the group of power source output signals PS 1 , PS 2 , PSN has a corresponding one of the group of voltage magnitudes. As such, at least one of the group of power source output signals PS 1 , PS 2 , PSN has the maximum voltage magnitude. Further, each of the group of voltage magnitudes is less than or equal to the maximum voltage magnitude. In one embodiment of the multiplexer gate driver  102 , a voltage swing at each of the group of power transistor gates  108 ,  110 ,  116  is about equal to the maximum voltage magnitude. 
       FIG. 9  shows the circuitry  10  according to a further embodiment of the circuitry  10 . The circuitry  10  illustrated in  FIG. 9  is similar to the circuitry  10  illustrated in  FIG. 8 , except the circuitry  10  illustrated in  FIG. 9  further includes the control circuitry  118 , which provides the group of enable signals EN 1 , EN 2 , ENN and the group of select signals SEL 1 , SEL 2 , SELN. In one embodiment of the control circuitry  118 , the control circuitry  118  determines which of the group of voltage magnitudes has the maximum voltage magnitude. Then, the control circuitry  118  selects the maximum voltage magnitude from the group of voltage magnitudes by providing the group of enable signals EN 1 , EN 2 , ENN based on the selection of the maximum voltage magnitude. Providing the maximum voltage magnitude to the power transistor-based multiplexer  100  via the multiplexer gate driver  102  ensures proper operation of the power transistor-based multiplexer  100 . 
     In one embodiment of the control circuitry  118 , the control circuitry  118  selects one of the group of power source output signals PS 1 , PS 2 , PSN to be forwarded to the load  112  based on selection criteria. Then, the control circuitry  118  provides the group of select signals SEL 1 , SEL 2 , SELN based on the selected one of the group of power source output signals PS 1 , PS 2 , PSN to be forwarded to the load  112 . 
     In an alternate embodiment of the circuitry  10 , the N TH  power source  78 , the N TH  power source output signal PSN, the N TH  enable signal ENN, the N TH  select signal SELN, the N TH  power gate signal PGSN, and the N TH  power transistor element  114  are omitted. As such, the control circuitry  118  determines which of the first voltage magnitude and the second voltage magnitude has the maximum voltage magnitude. The control circuitry  118  provides the first enable signal EN 1  and the second enable signal EN 2  based on the selection of the maximum voltage magnitude. The control circuitry  118  selects one of the first power source output signal PS 1  and the second power source output signal PS 2  to be forwarded to the load  112  based on selection criteria. The control circuitry  118  provides the first select signal SEL 1  and the second select signal SEL 2  based on the selected one of the first power source output signal PS 1  and the second power source output signal PS 2  to be forwarded to the load  112 . 
       FIG. 10  shows the circuitry  10  according to a supplemental embodiment of the circuitry  10 . The circuitry  10  illustrated in  FIG. 10  is similar to the circuitry  10  illustrated in  FIG. 1 , except the circuitry  10  illustrated in  FIG. 10  further includes the control circuitry  118 , which provides the first enable signal EN 1 , the second enable signal EN 2 , the third enable signal EN 3 , and the fourth enable signal EN 4 . 
     In a first embodiment of the control circuitry  118 , the control circuitry  118  selects one of the first power source output signal PS 1  and the second power source output signal PS 2  to be forwarded by the first power source multiplexer  12  to provide the first multiplexer output signal MUX 1  based on selection criteria. In a second embodiment of the control circuitry  118 , the control circuitry  118  selects one of the first power source output signal PS 1  and the second power source output signal PS 2  to be forwarded by the second power source multiplexer  14  to provide the second multiplexer output signal MUX 2  based on the selection criteria. 
     In one embodiment of the selection criteria, the selection criteria includes the first voltage magnitude and the second voltage magnitude. In one embodiment of the selection criteria, the selection criteria includes a bandwidth of a radio frequency (RF) power amplifier (PA)  132  ( FIG. 11 ). In one embodiment of the selection criteria, the selection criteria includes a magnitude of an RF input signal RFI ( FIG. 11 ) to the RF PA  132  ( FIG. 11 ). In one embodiment of the selection criteria, the selection criteria includes a gain of the RF PA  132  ( FIG. 11 ). In one embodiment of the selection criteria, the selection criteria includes any or all of the first voltage magnitude, the second voltage magnitude, the bandwidth of the RF PA  132  ( FIG. 11 ), the gain of the RF PA  132  ( FIG. 11 ), and the magnitude of the RF input signal RFI ( FIG. 11 ) to the RF PA  132  ( FIG. 11 ). 
       FIG. 11  shows RF circuitry  120  according to one embodiment of the RF circuitry  120 . The RF circuitry  120  illustrated in  FIG. 11  includes the circuitry  10  illustrated in  FIG. 1  according to one embodiment of the RF circuitry  120 . The RF circuitry  120  further includes RF transmitter circuitry  122 , RF system control circuitry  124 , RF front-end circuitry  126 , an RF antenna  128 , and the first power source  48 . The RF transmitter circuitry  122  includes transmitter control circuitry  130 , the RF PA  132 , an envelope tracking power supply  134 , and PA bias circuitry  136 . In this regard, in one embodiment of the RF circuitry  120 , the RF circuitry  120  illustrated in  FIG. 11  is an RF communications system. In one embodiment of the transmitter control circuitry  130 , the transmitter control circuitry  130  includes the control circuitry  118 . 
     In one embodiment of the RF circuitry  120 , the RF front-end circuitry  126  receives via the RF antenna  128 , processes, and forwards an RF receive signal RFR to the RF system control circuitry  124 . The RF system control circuitry  124  provides an envelope power supply control signal VRMP and a transmitter configuration signal PACS to the transmitter control circuitry  130 . The RF system control circuitry  124  provides the RF input signal RFI to the RF PA  132 . The first power source  48  provides the first power source output signal PS 1  to the envelope tracking power supply  134  and to the transmitter control circuitry  130 . In one embodiment of the first power source  48 , the first power source  48  is the battery. The second power source  50  provides the second power source output signal PS 2  to the envelope tracking power supply  134  and to the transmitter control circuitry  130 . In one embodiment of the second power source  50 , the second power source  50  is the DC-DC converter. 
     The transmitter control circuitry  130  is coupled to the envelope tracking power supply  134  and to the PA bias circuitry  136 . The envelope tracking power supply  134  provides an envelope power supply signal EPS and the second multiplexer output signal MUX 2  to the RF PA  132  based on the envelope power supply control signal VRMP. In one embodiment of the envelope tracking power supply  134 , the first power source  48  and the second power source  50  provide power to the envelope tracking power supply  134  via the first power source output signal PS 1  and the second power source output signal PS 2 , respectively. As such, the envelope power supply signal EPS is based on either the first power source output signal PS 1  or the second power source output signal PS 2 . Similarly, the second multiplexer output signal MUX 2  is based on either the first power source output signal PS 1  or the second power source output signal PS 2 . 
     The envelope power supply control signal VRMP is representative of a setpoint of the envelope power supply signal EPS. The RF PA  132  receives and amplifies the RF input signal RFI to provide an RF transmit signal RFT using the envelope power supply signal EPS. The envelope power supply signal EPS and the second multiplexer output signal MUX 2  provide power for amplification. In one embodiment of the RF PA  132 , the envelope power supply signal EPS provides power for amplification to a final stage in the RF PA  132  and the second multiplexer output signal MUX 2  provides power for amplification to a driver stage in the RF PA  132 . 
     The RF front-end circuitry  126  receives, processes, and transmits the RF transmit signal RFT via the RF antenna  128 . In one embodiment of the RF transmitter circuitry  122 , the transmitter control circuitry  130  configures the RF transmitter circuitry  122  based on the transmitter configuration signal PACS. The PA bias circuitry  136  provides a PA bias signal PAB to the RF PA  132 . In this regard, the PA bias circuitry  136  biases the RF PA  132  via the PA bias signal PAB. In one embodiment of the PA bias circuitry  136 , the PA bias circuitry  136  biases the RF PA  132  based on the transmitter configuration signal PACS. In one embodiment of the RF front-end circuitry  126 , the RF front-end circuitry  126  includes at least one RF switch, at least one RF amplifier, at least one RF filter, at least one RF duplexer, at least one RF diplexer, at least one RF amplifier, the like, or any combination thereof. 
     In one embodiment of the RF system control circuitry  124 , the RF system control circuitry  124  is RF transceiver circuitry, which may include an RF transceiver IC, baseband controller circuitry, the like, or any combination thereof. In one embodiment of the RF transmitter circuitry  122 , the envelope tracking power supply  134  provides the envelope power supply signal EPS, which has switching ripple. In one embodiment of the RF transmitter circuitry  122 , the envelope power supply signal EPS provides power for amplification and envelope tracks the RF transmit signal RFT. 
       FIG. 12  shows the RF circuitry  120  according to an alternate embodiment of the RF circuitry  120 . The RF circuitry  120  illustrated in  FIG. 12  is similar to the RF circuitry  120  illustrated in  FIG. 11 , except in the RF circuitry  120  illustrated in  FIG. 12 , the RF transmitter circuitry  122  further includes a digital communications interface  138 , which is coupled between the transmitter control circuitry  130  and a digital communications bus  140 . The digital communications bus  140  is also coupled to the RF system control circuitry  124 . As such, the RF system control circuitry  124  provides the envelope power supply control signal VRMP ( FIG. 9 ) and the transmitter configuration signal PACS ( FIG. 9 ) to the transmitter control circuitry  130  via the digital communications bus  140  and the digital communications interface  138 . 
       FIG. 13  shows details of the envelope tracking power supply  134  illustrated in  FIG. 11  according to one embodiment of the envelope tracking power supply  134 . The envelope tracking power supply  134  includes the first power source multiplexer  12 , the second power source multiplexer  14 , an analog supply  142 , and a switching supply  144 . The transmitter control circuitry  130  controls the first power source multiplexer  12 , the second power source multiplexer  14 , the analog supply  142 , and the switching supply  144 . The analog supply  142  and the switching supply  144  provide the envelope power supply signal EPS, such that the analog supply  142  partially provides the envelope power supply signal EPS and the switching supply  144  partially provides the envelope power supply signal EPS. The switching supply  144  may provide power more efficiently than the analog supply  142 . However, the analog supply  142  may provide the envelope power supply signal EPS more accurately than the switching supply  144 . As such, the analog supply  142  regulates a voltage of the envelope power supply signal EPS based on the setpoint of the envelope power supply signal EPS, and the switching supply  144  operates to drive an output current from the analog supply  142  toward zero to maximize efficiency. In this regard, the analog supply  142  behaves like a voltage source and the switching supply  144  behaves like a current source. 
     Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.