Patent Publication Number: US-2013234224-A1

Title: Semiconductor storage device and manufacturing method for the same

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims benefit of priority from the Japanese Patent Application No. 2012-51780, filed on Mar. 8, 2012, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a semiconductor storage device and a manufacturing method for a semiconductor storage device. 
     BACKGROUND 
     Regarding a semiconductor storage device such as a NAND flash memory, there has been proposed a configuration where a floating gate of a memory cell transistor includes a lower floating gate, an upper floating gate, and an inter-gate insulating film provided between the lower floating gate and the upper floating gate. With such a configuration formed, it is possible to make a memory cell density higher while suppressing deterioration in writing characteristics of the memory cell transistor, an adjacent cell interfering effect, an electric charge escape and the like. 
     A select transistor of a conventional NAND flash memory has a configuration where a groove (opening) is provided in an insulating film between a first electrode layer corresponding to a floating gate and a second electrode layer corresponding to a control gate, to connect between the first electrode layer and the second electrode layer. When the floating gate of the memory cell transistor is configured to have the lower floating gate, the upper floating gate and the inter-gate insulating film provided between the lower floating gate and the upper floating gate as described above, the first electrode layer of the select transistor is similarly configured to have the lower electrode layer, the upper electrode layer and the insulating film provided between the lower electrode layer and the upper electrode layer. In the select transistor with such a configuration, since the lower electrode layer holds an electric charge as does the floating gate, a threshold voltage may change, to bring about an erroneous operation. Further, it has been necessary to apply a voltage for a total of a tunnel insulating film and the insulating film provided between the lower electrode layer and the upper electrode layer, thus increasing power consumption. Hence the higher density of the memory cell has induced deterioration in characteristics of the select transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a plan view of a semiconductor storage device according to a first embodiment; 
         FIGS. 2A and 2B  are sectional views of the semiconductor storage device according to the first embodiment; 
         FIGS. 3A and 3B  are process sectional views explaining a manufacturing method for the semiconductor storage device according to the first embodiment; 
         FIGS. 4A and 4B  are process sectional views subsequent to  FIGS. 3A and 3B ; 
         FIGS. 5A and 5B  are process sectional views subsequent to  FIGS. 4A and 4B ; 
         FIGS. 6A and 6B  are process sectional views subsequent to  FIGS. 5A and 5B ; 
         FIGS. 7A and 7B  are process sectional views subsequent to  FIGS. 6A and 6B ; 
         FIGS. 8A and 8B  are process sectional views subsequent to  FIGS. 7A and 7B ; 
         FIGS. 9A and 9B  are process sectional views explaining a manufacturing method for a semiconductor storage device according to a second embodiment; 
         FIGS. 10A and 10B  are process sectional views subsequent to  FIGS. 9A and 9B ; 
         FIGS. 11A and 11B  are process sectional views subsequent to  FIGS. 10A and 10B ; 
         FIGS. 12A and 12B  are process sectional views subsequent to  FIGS. 11A and 11B ; 
         FIGS. 13A and 13B  are sectional views of the semiconductor storage device according to the second embodiment; 
         FIGS. 14A and 14B  are sectional views of a semiconductor storage device according to a modified example; 
         FIG. 15  is a sectional view of a semiconductor storage device according to a third embodiment; 
         FIG. 16  is a sectional view of a semiconductor storage device according to a modified example; and 
         FIG. 17  is a sectional view of a semiconductor storage device according to a modified example. 
     
    
    
     DETAILED DESCRIPTION 
     According to one embodiment, a semiconductor storage device comprises a memory cell transistor including a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film and a control gate which are sequentially formed on a substrate, and a select transistor including a fourth insulating film, a first electrode layer, a fifth insulating film, a second electrode layer, a sixth insulating film and a third electrode layer which are sequentially formed on the substrate. Openings are provided in at least parts of the fifth insulating film and the sixth insulating film. The first electrode layer, the second electrode layer and the third electrode layer are electrically connected via the openings. 
     Embodiments will now be explained with reference to the accompanying drawings. 
     FIRST EMBODIMENT 
       FIG. 1  is a plan view of a semiconductor storage device according to a first embodiment. The semiconductor storage device is an NAND flash memory. 
     As shown in  FIG. 1 , the semiconductor storage device is provided with a plurality of bit lines BL extending along a first direction, a plurality of word lines WL and select lines S extending along a second direction orthogonal to the first direction. 
     A point of intersection between the bit line BL and the word line WL is provided with a memory cell transistor. Further, a point of intersection between the bit line BL and the select line S is provided with a select transistor. The memory cell transistor is electrically connected to the bit line BL and the word line WL. Moreover, the select transistor is electrically connected to the bit line BL and the select line S. 
       FIG. 2A  shows a vertical sectional view along a line A-A of  FIG. 1 , and  FIG. 2B  shows part of a vertical sectional view along a line B-B of  FIG. 1 . 
     As shown in  FIG. 2A , an impurity diffused layer  131  is formed in a surface portion of a semiconductor substrate  101 . On the semiconductor substrate  101  between the impurity diffused layers  131 , a memory cell transistor MT is formed, which is sequentially laminated with a tunnel insulating film  111   a , a lower floating gate  112   a , an IFD (Inter Floating-Gate Dielectric) film  113   a , an upper floating gate  114   a , an IPD (Inter Poly-Si Dielectric) film  115   a  and a control gate  116   a . The memory cell transistor MT has a two-layered structure where the floating gates sandwich the IFD film  113   a.    
     As shown in  FIG. 2B , in the memory cell transistor MT, a plurality of embedded element separated regions  130  are formed on the semiconductor substrate  101  along a word-line WL direction at predetermined intervals. On the semiconductor substrate  101  between the element separated regions  130 , the tunnel insulating film  111   a , the lower floating gate  112   a , the IFD film  113   a  and the upper floating gate  114   a  are sequentially formed. 
     The IPD film  115   a  is formed on the upper floating gate  114   a  and the element separated region  130 . The control gate  116   a  is formed on this IPD film  115   a.    
     As shown in  FIGS. 1 and 2A , a select transistor ST is formed at each end of the plurality of memory cell transistors MT arrayed in a bit-line BL direction. The select transistor ST includes a tunnel insulating film  111   b , a first electrode layer  112   b , a first inter-electrode insulating film  113   b , a second electrode layer  114   b , a second inter-electrode insulating film  115   b  and a third electrode layer  116   b , which are sequentially formed on the semiconductor substrate  101 . The select transistor ST has a similar configuration to the memory cell transistor MT, and the tunnel insulating film  111   b , the first electrode layer  112   b , the first inter-electrode insulating film  113   b , the second electrode layer  114   b , the second inter-electrode insulating film  115   b  and the third electrode layer  116   b  in the select transistor ST respectively correspond to the tunnel insulating film  111   a , the lower floating gate  112   a , the IFD film  113   a , the upper floating gate  114   a , the IPD film  115   a  and the control gate  116   a  in the memory cell transistor MT. 
     However, in the select transistor ST, openings are formed in part of the first inter-electrode insulating film  113   b  and part of the second inter-electrode insulating film  115   b , to connect among the first electrode layer  112   b , the second electrode layer  114   b  and the third electrode layer  116   b.    
     When the opening is not provided in the first inter-electrode insulating film  113   b , the first electrode layer  112   b  holds an electric charge as does the floating gate, which may cause a change in threshold voltage of the select transistor ST, to bring about an erroneous operation. Further, when the opening is not provided in the first inter-electrode insulating film  113   b , driving the select transistor ST necessitates application of a voltage corresponding to a total of the tunnel insulating film  111   b  and the first inter-electrode insulating film  113   b , thus increasing power consumption. 
     As opposed to this, in the present embodiment, the opening is formed in part of the first inter-electrode insulating film  113   b , to connect among the first electrode layer  112   b , the second electrode layer  114   b  and the third electrode layer  116   b , and hence the first electrode layer  112   b  does not hold an electric charge as does the floating gate, allowing prevention of a threshold voltage of the select transistor ST from changing and an erroneous operation from occurring. Further, a voltage corresponding to the tunnel insulating film  111   b  may be applied for driving the select transistor ST, thus allowing suppression of power consumption. A size of the opening of the first inter-electrode insulating film  113   b  is not particularly restricted, and the opening may have the same size as the first inter-electrode insulating film  113   b , namely, the first inter-electrode insulating film  113   b  may be omitted. 
     Further, in the present embodiment, the floating gate of the memory cell transistor MT is made up of the lower floating gate  112   a  and the upper floating gate  114   a , and the IFD film  113   a  is provided between the lower floating gate  112   a  and the upper floating gate  114   a . Thereby, a coupling ratio between the upper floating gate  114   a  and the control gate  116   a  is improved, to increase an electric field to be applied to the tunnel insulating film  111   a , thus leading to improvement in writing characteristics of the memory cell transistor MT. Further, a capacity within a cell increases and the coupling ratio thus become higher, thereby to suppress the adjacent cell interfering effect. 
     Moreover, the tunnel insulating film  111   a  and the IFD film  113   a  become FN (Fowler-Nordheim) films, thereby to suppress an escape of an electric charge within the lower floating gate  112   a  to the substrate  101  and also suppress an escape of an electric charge within the upper floating gate  114   a  to the lower floating gate  112   a . This allows the memory cell transistor MT to keep holding an electric charge for a long period of time. The memory cell transistor MT can be higher in density while suppressing deterioration in writing characteristics, the adjacent cell interfering effect, the electric charge escape and the like. 
     As thus described, according to the present embodiment, it is possible to make the density of the memory cell transistor MT higher, while suppressing deterioration in characteristics of the select transistor ST. 
     Next, a manufacturing method for such a semiconductor storage device will be described using process sectional views shown in  FIGS. 3A and 3B  to  FIGS. 8A and 8B . A and B in each figure respectively show cross sections corresponding to  FIGS. 2A and 2B . 
     First, as shown in  FIGS. 3A and 3B , an insulating film  111  to be materials for the tunnel insulating films  111   a ,  111   b , an electrode layer  112  to be materials for the lower floating gate  112   a  and the first electrode layer  112   b , an insulating film  113  to be materials for the IFD film  113   a  and the first inter-electrode insulating film  113   b , and an electrode layer  114  to be materials for the upper floating gate  114   a  and the second electrode layer  114   b  are sequentially formed on the substrate  101 . 
     The insulating film  111  is, for example, a silicon oxide film, a silicon oxy-nitride film or a silicon nitride film. The electrode layers  112 ,  114  are, for example, made up of polysilicon, polysilicon doped with boracic acid or phosphorus, metal such as TiN, TaN or W, or silicide thereof. The insulating film  113  is, for example, a silicon oxide film, a silicon oxy-nitride film, a silicon nitride film, a Al 2 O 3  film, a HfO x  film, a TaO x  film, or a La 2 O x  film. 
     Subsequently, as shown in  FIGS. 4A and 4B , a mask layer (not shown) is formed on the electrode layer  114 , and by lithography and etching, this mask layer is patterned in the form of a plurality of bands along the bit-line BL direction. The mask layer is, for example, a silicon oxide film. Then, using the patterned mask layer, the electrode layer  114 , the insulating film  113 , the electrode layer  112 , the insulating film  111  and the substrate  101  are etched, to form a plurality of grooves T 1 . The mask layer is removed and an insulating film such as a silicon oxide film is embedded in the groove T 1 , which is then smoothed by CMP (Chemical-Mechanical Polishing), to form the element separated region  130 . 
     Next, as shown in  FIGS. 5A and 5B , an insulating film  115  to be materials for the IPD film  115   a  and the second inter-electrode insulating film  115   b  is formed on the electrode layer  114  and the element separated region  130 . The insulating film  115  is, for example, a silicon oxide film, a silicon oxy-nitride film, a silicon nitride film, a Al 2 O 3  film, a HfO x  film, a TaO x  film, or La 2 O x  film. 
     Then, in the region where the select transistor ST is provided, the insulating film  115 , the electrode layer  114  and the insulating film  113  are removed by lithography and etching (e.g. RIE), to form a groove T 2 . At this time, part of the electrode layer  112  may be removed. The groove T 2  corresponds to the opening that is provided in the first inter-electrode insulating film  113   b  and the second inter-electrode insulating film  115   b  of the select transistor ST. Further, since an amount of removal is smaller in a deeper place in typical anisotropic etching, a width of the groove T 2  gets narrower toward a lower place. Hence the opening provided in the first inter-electrode insulating film  113   b  has a smaller width than that of the opening provided in the second inter-electrode insulating film  115   b.    
     Next, as shown in  FIGS. 6A and 6B , an electrode layer  116  to be materials for the control gate  116   a  and the third electrode layer  116   b  is formed on the insulating film  115 . The groove T 2  is embedded with the electrode layer  116 . The electrode layer  116  is made up of polysilicon, polysilicon doped with boracic acid or phosphorus, metal such as TiN, TaN, W, Ni or Co, or silicide thereof. 
     Next, as shown in  FIGS. 7A and 7B , a mask layer (not shown) is formed on the electrode layer  116 , and by lithography and etching, this mask layer is patterned in the form of a plurality of bands along the word-line WL direction. Then, using the patterned mask layer, the electrode layer  116 , the insulating film  115 , the electrode layer  114 , the insulating film  113 , the electrode layer  112  and the insulating film  111  are etched, to form a plurality of grooves T 3 . 
     Next, as shown in  FIGS. 8A and 8B , the impurity diffused layer  131  is formed on the substrate  101 . An inter-layer insulating film  140  is then formed on the substrate  101  such that the inter-layer insulating film  140  is embedded in the groove T 3 . Thereafter, a contact plug, a via plug, a wiring layer and the like are formed. 
     This leads to formation of the memory cell transistor MT laminated with the tunnel insulating film  111   a , the lower floating gate  112   a , the IFD film  113   a , the upper floating gate  114   a , the IPD film  115   a  and the control gate  116   a.    
     Further, the tunnel insulating film  111   b , the first electrode layer  112   b , the first inter-electrode insulating film  113   b , the second electrode layer  114   b , the second inter-electrode insulating film  115   b  and the third electrode layer  116   b  are laminated, to form the select transistor ST connected with the first electrode layer  112   b , the second electrode layer  114   b  and the third electrode layer  116   b  via the openings provided in the first inter-electrode insulating film  113   b  and the second inter-electrode insulating film  115   b . In the select transistor ST, the third electrode layer  116   b  is in contact with the first electrode layer  112   b  and the second electrode layer  114   b.    
     As described above, in the present embodiment, the opening is formed in part of the first inter-electrode insulating film  113   b  and part of the second inter-electrode insulating film  115   b , to connect among the first electrode layer  112   b , the second electrode layer  114   b  and the third electrode layer  116   b , and hence the first electrode layer  112   b  does not hold an electric charge as does the floating gate, allowing prevention of a threshold voltage of the select transistor ST from changing and an erroneous operation from occurring. Further, a voltage corresponding to the tunnel insulating film  111   b  may be applied for driving the select transistor ST, thus allowing suppression of power consumption. 
     Moreover, with the floating gate of the memory cell transistor MT made up of the lower floating gate  112   a , the IFD film  113   a  and the upper floating gate  114   a , the memory cell transistor MT can be higher in density while suppressing deterioration in writing characteristics, the adjacent cell interfering effect, the electric charge escape and the like. 
     As thus described, according to the present embodiment, it is possible to make the density of the memory cell transistor MT higher, while suppressing deterioration in characteristics of the select transistor ST. 
     SECOND EMBODIMENT 
     In the above first embodiment, in the process shown in  FIG. 5A , the groove T 2  is formed, thereby to form the openings provided in the above first inter-electrode insulating film  113   b  and the second inter-electrode insulating film  115   b  of the select transistor ST. That is, the openings provided in the first inter-electrode insulating film  113   b  and the second inter-electrode insulating film  115   b  are formed in the same process in the above first embodiment, but these may be formed in separate processes. 
     A manufacturing method for the semiconductor storage device in the case of forming the opening provided in the first inter-electrode insulating film  113   b  and the opening provided in the second inter-electrode insulating film  115   b  in separate processes will be described using process sectional views shown in  FIGS. 9A and 9B  to  12 A to  12 B. A and B in each figure respectively show cross sections corresponding to  FIGS. 2A and 2B . 
     First, as shown in  FIGS. 9A and 9B , the insulating film  111  to be materials for the tunnel insulating films  111   a ,  111   b , the electrode layer  112  to be materials for the lower floating gate  112   a  and the first electrode layer  112   b , and the insulating film  113  to be materials for the IFD film  113   a  and the first inter-electrode insulating film  113   b  are sequentially formed on the substrate  101 . 
     Then, in the region where the select transistor ST is provided, the insulating film  113  is removed by lithography and etching, to form a groove T 4 . The groove T 4  corresponds to the opening that is provided in the first inter-electrode insulating film  113   b  of the select transistor ST. 
     Next, as shown in  FIGS. 10A and 10B , the electrode layer  114  to be materials for the upper floating gate  114   a  and the second electrode layer  114   b  is formed on the insulating film  113 . The groove T 4  is embedded with the electrode layer  114 . 
     Subsequently, a mask layer (not shown) is formed on the electrode layer  114 , and by lithography and etching, this mask layer is patterned in the form of a plurality of bands along the bit-line BL direction. Then, using the patterned mask layer, the electrode layer  114 , the insulating film  113 , the electrode layer  112 , the insulating film  111  and the substrate  101  are etched, to form a plurality of grooves T 1 . The mask layer is removed and an insulating film such as a silicon oxide film is embedded in the groove T 1 , which is then smoothed by CMP (Chemical-Mechanical Polishing), to form the element separated region  130 . 
     Next, as shown in  FIGS. 11A and 11B , the insulating film  115  to be materials for the IPD film  115   a  and the second inter-electrode insulating film  115   b  is formed on the electrode layer  114  and the element separated region  130 . Then, in the region where the select transistor ST is provided, the insulating film  115  is removed by lithography and etching (e.g. RIE), to form a groove T 5 . The groove T 5  corresponds to the opening that is provided in the second inter-electrode insulating film  115   b  of the select transistor ST. 
     Next, as shown in  FIGS. 12A and 12B , the electrode layer  116  to be materials for the control gate  116   a  and a third electrode layer  116   b  is formed on the insulating film  115 . The groove T 5  is embedded wiht the electrode layer  116 . 
     Since subsequent steps are similar to those of the above first embodiment (cf.  FIGS. 7A ,  7 B,  8 A, and  8 B), descriptions thereof will be omitted. In such a manner, the semiconductor storage device as shown in  FIG. 13  is formed. In the select transistor ST shown in  FIG. 13 , the third electrode layer  116   b  is in contact with the second electrode layer  114   b , and the second electrode layer  114   b  is in contact with the first electrode layer  112   b.    
     In the above first embodiment, in the process shown in  FIG. 5A , the insulating film  115 , the electrode layer  114  and the insulating film  113  are removed, to form the groove T 2 . When film thicknesses of the insulating film  115 , the electrode layer  114 , the insulating film  113  and the electrode layer  112  are respectively referred to as d5, d4, d3 and d2, an etching film thickness is d5+d4+d3, and an etching depth variation allowance is d2 in the process shown in  FIG. 5A . 
     On the other hand, in the present embodiment, in the process of forming the groove T 4  shown in  FIG. 9A , an etching film thickness is d3, and an etching depth variation allowance is d2 in the process shown in  FIG. 9A . Further, in the process of forming the groove T 5  shown in  FIG. 11A , an etching film thickness is d5, and an etching depth variation allowance is d4+d3+d2. According to the present embodiment, the etching depth variation allowance with respect to the etching film thickness can be taken large as compared with the above first embodiment, and the opening provided in the first inter-electrode insulating film  113   b  and the opening provided in the second inter-electrode insulating film  115   b  can be stably formed. 
     In the above second embodiment, the groove T 5  may not be formed immediately above the groove T 4 . This is because, even when a position (plane position) of the opening provided in the first inter-electrode insulating film  113   b  and a position (plane position) of the opening provided in the second inter-electrode insulating film  115   b  are displaced, the first electrode layer  112   b , the second electrode layer  114   b  and the third electrode layer  116   b  are connected. 
     In the above first embodiment, the width of the opening provided in the first inter-electrode insulating film  113   b  is smaller than the width of the opening provided in the second inter-electrode insulating film  115   b . However, in the second embodiment, since these openings are formed in the separate processes, the width of the opening provided in the first inter-electrode insulating film  113   b  can be made equal to or larger than the width of the opening provided in the second inter-electrode insulating film  115   b.    
     Although the mask layer is formed on the electrode layer  114  in formation of the groove T 1  in the process shown in  FIGS. 10A and 10B  in the above second embodiment, part of the mask layer may remain in an upper portion of the groove T 4  (opening of the first inter-electrode insulating film  113   b ) even after removal of the mask layer, as shown in  FIG. 14 . Even when part of the mask layer remains as thus described, the first electrode layer  112   b , the second electrode layer  114   b  and the third electrode layer  116   b  are connected. 
     THIRD EMBODIMENT 
     In the above first and second embodiments, the IPD film  115  and the lower surface of the control gate  116  are flat. In other words, the upper surface of the upper floating gate  114  and the upper surface of the element separated region  130  have the same height. 
     As opposed to this, in the present embodiment, as shown in  FIG. 15 , the upper surface of the element separated region  130  is made to have a smaller height than the upper surface of the upper floating gate  114   a , and the IPD film  115   a  and the lower surface of the control gate  116   a  are formed in an uneven shape in accordance with shapes of the surfaces of the element separated region  130  and the upper floating gate  114   a.    
     Specifically, in the processes shown in  FIGS. 4B and 10B , the insulating film such as a silicon oxide film is embedded in the groove T 1 , which is then smoothed by CMP, to remove part of the insulating film embedded in the groove T 1  by RIE or the like. 
     Forming the configuration as shown in  FIG. 15 , opposed areas of the control gate  116   a  and the upper floating gate  114   a  can be increased, thereby to increase a coupling capacitance and a coupling coefficient. 
     In the above first to third embodiments, as shown in  FIG. 16 , a charge trap film  150   a  may be provided on the upper floating gate  114   a  of the memory cell transistor MT. The charge trap film  150   a  is, for example, a silicon nitride film or a HfOx film. The charge trap film  150   a  may be formed immediately below the IPD film  115   a  as shown in  FIG. 16 , or may be formed immediately above the IFD film  113   a  as shown in  FIG. 17 . In the case of manufacturing the configuration shown in  FIG. 17  using the manufacturing method according to the above second embodiment, the groove T 4  corresponding to the opening of the IFD film  113   a  may be formed after formation of the charge trap film  150   a  on the IFD film  113   a.    
     It is to be noted that in the case of providing the charge trap film  150   a  on the upper floating gate  114   a , a film  150   b  made of the same material as the charge trap film  150   a  is formed in the select transistor ST. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.