Patent Publication Number: US-7716398-B2

Title: Bifurcate buffer

Description:
RELATED APPLICATIONS 
   This application claims the benefit of U.S. Provisional Patent Application No. 60/870,868, filed on Dec. 20, 2006, by the same inventor, which is incorporated herein by reference in its entirety. 

   FIELD OF THE INVENTION 
   The present invention relates to bifurcate buffers and is particularly concerned with very high speed switch buffers. 
   BACKGROUND OF THE INVENTION 
   Peripheral Component Interconnect Express, PCIe 2.0 specifies 5.0 Gigbit/s symbol rate per lane. Multiple lanes can be used to fabricate larger port bandwidths. For example, x4 port would have an aggregate symbol rate of 20 G, and a bit rate of 16 G, 8b10b coding is used. A x8 port would have an aggregate symbol rate of 40 G, and a bit rate of 32 G. There are other serial interconnect protocols, for example serial rapid IO and Ethernet that have similar properties. This disclosure will focus on PICe, but is not limited to that protocol. 
   Referring to  FIG. 1 , there is illustrated a PCIe packet. The diagram is copied from PCIe specification. The PCIe packet  10  includes a framing byte  12 , a two-byte sequence number  14 , a header  16 , data  18 , a 4-byte ECRC  20 , a 4-byte LCRC  22  and a final framing byte  24 , all of which form a physical layer  26 . The two-byte sequence number  14 , the header  16 , data  18 , the 4-byte ECRC  20 , and the 4-byte LCRC  22  form a data link layer  27 . The header  16 , data  18  and the 4-byte ECRC  20  form a transaction layer  28 . The data  18  and the 4-byte ECRC  20  are optional, hence are shown in dashed line. 
   The numbers of bytes (actually a 10 bit symbol on the serial link) is shown in  FIG. 1 . The framing bytes, start  12  and stop  24  can be discarded by the internal logic as they are only useful for synchronizing the link to the symbol time at the receiver. The sequence number  14  only exists on the link. This is only useful to the data link layer  27 , to assure that all packets are received, and in order. Although the LCRC  22  (link CRC) is valid for the link, it can be useful to monitor data integrity through a switch, or other such device. 
   The simplest way to convert this serial packet to a parallel bus for on chip processing is shown in  FIG. 2 . The 10-bit symbols at 5 G/s are converted to 8-bit data at 500 Mbits/s by SERDES (serialize/de-serialize)  30 . Note that the start of packet (SOP) must always occur on lane 0. The parallel data is written  32  into a data buffer, running at the same clock rate as the 500M byte rate. It may be feasible to implement the MAC at a clock rate of 500 MHz in 90 nm The read side of the buffer, connecting to a large internal switch fabric (ISF), will not be feasible to implement at 500 MHz clock rate. Two minimum size packets are shown 32 to consume six clock ticks, and only take four ticks to write into the data buffer  36 ,  38 . 
   It is possible to have a serialize/de-serialize (SERDES)  30  that creates 16-bit wide data lanes running at half the speed. The issue then is that two packets may exist at the same time on the same clock tick. Memory management would required that different packets occupy different memory locations. 
   When a port bifurcates, prior art methods typically instantiate another buffer for that port. This buffer is wasted when a single 1×8 port is used. 
   SUMMARY OF THE INVENTION 
   An object of the present invention is to provide an improved bifurcate buffer. 
   In accordance with an aspect of the present invention there is provided a bifurcate buffer comprising a plurality of serial inputs, a plurality of de-serializers, each coupled to a respective input, a plurality n of buffers and a media access controller having inputs coupled to the plurality of de-serializers, data outputs coupled to the buffers, and two control outputs coupled to respective buffers for buffering input data at a clock rate one-nth that of the input data. 
   In accordance with another aspect of the present invention there is provided a A bifurcate buffer comprising a plurality of serial inputs, a plurality of de-serializers, each coupled to a respective input, two buffers and a media access controller having inputs coupled to the plurality of de-serializers, data outputs coupled to the buffers, and two control outputs coupled to respective buffers for buffering input data at a clock rate one-half that of the input data. 
   In accordance with a further aspect of the present invention there is provided a A bifurcate buffer comprising a plurality of serial inputs, a plurality of de-serializers, each coupled to a respective input, two buffers and two media access controllers each having inputs coupled to one-half the plurality of de-serializers, data outputs coupled to the buffers, and a control output coupled to respective buffers for buffering input data at a clock rate one-half that of the input data. 
   By paralleling the data to wider widths and creating separate memories more effective use of buffers is made. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be further understood from the following detailed description with reference to the drawings in which: 
       FIG. 1  illustrates a PCIe packet; 
       FIG. 2  illustrates a simple way to convert the serial packet of  FIG. 1  to a parallel bus; 
       FIG. 3  illustrates a bifurcate buffer in accordance with a first embodiment of the present invention; 
       FIG. 4  illustrates a bifurcate buffer in accordance with a second embodiment of the present invention; 
       FIGS. 5   a  and  5   b  illustrate packet flow for the bifurcate buffer of  FIG. 3 ; 
       FIGS. 6   a  and  6   b  illustrate packet flow for the bifurcate buffer of  FIG. 4 ; and 
       FIG. 7  illustrates an example of memory management for the bifurcate buffers. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   Referring to  FIG. 3  there is illustrated a bifurcate buffer in accordance with a first embodiment of the present invention. The 1×8 bifurcate buffer  40  includes a media access controller (MAC)  42  receiving input from serializer/de-serializer (SERDES)  30  and outputting-four 16-bit wide lanes to each of x64 RAM  44  and  46 , controlled by lines  48   a  and  48   b , respectively. 
   In operation, the data is written into two-x64 250 MHz dual port RAM  44  and  46 . The memory management generates different addresses for each bank. 
   Referring to  FIG. 4  there is illustrated a bifurcate buffer in accordance with a second embodiment of the present invention. The 2×4 bifurcate buffer  50  includes a first media access controller (MAC)  42  receiving input from serializer/de-serializer (SERDES)  30  and outputting four 16-bit wide lanes to x64 RAM  44 , controlled by line  48   a . The 2×4 bifurcate buffer  50  also includes a second media access controller (MAC)  52  receiving input from the lower four serializer/de-serializer (SERDES)  30  and outputting four 16-bit wide lanes to x64 RAM  54 , controlled by line  56 . Hence, in this example the 1×8 port  30  can bifurcate to 2×4 ports. 
   In operation, the upper x8 MAC  42  is configured to run in 4 mode. Here each buffer  44  and  54  is managed by its respective MAC  42  and  52 . 
   Referring to  FIGS. 5   a  and  5   b , there is illustrated packet flow for the bifurcate buffer of  FIG. 3 . The packet flow for 1×8 mode is shown. We can see that the two packets come in to the MAC  42  on three clock ticks  60   a  and  60   b , and are written  62   a  and  62   b  in to the buffers  44  in three clock ticks  64   a  and  64   b . The second clock tick contains data from two different packets. The framing bytes, start  12  and stop  24  and the sequence number  14  can now be discarded  66   a  and  66   b  by the internal logic. 
   Referring to  FIGS. 6   a  and  6   b , there is illustrated packet flow for the bifurcate buffer of  FIG. 4 . The packet flow for 2×4 mode is shown. We can see that the two packets, on each port  42  and  52 , come in on six clocks ticks  70   a  and  70   b , and are written  72   a  and  72   b  in to buffers  44  and  54  in six clock ticks  74   a  and  74   b . The framing bytes, start  12  and stop  24  and the sequence number  14  can now be discarded  76   a  and  76   b  by the internal logic, as is padding bytes  78 . 
   Referring to  FIG. 7 , there is illustrated an example of memory management for the bifurcate buffers of  FIGS. 3 and 4 . The memory management scheme is described below. The underlying scheme is a link list  80  of 64 byte blocks. This scheme is well known by those skilled in the art. The actual sizes are a function of cost/performance trade offs; this is simply a typical example. 
   In 1×8 mode two packet pointers  82  and  84  index each packet. The 8-bit pointer also has another bit to indicate which pointer contains the first portion of the packet. This way packets can be pulled out of the buffer in order. The packet pointers are stored in a FIFO (in this example). 
   In 2×4 mode the packet pointer FIFOs  82  and  84  are independent. 
   The free lists  80  are in one physical memory, but logically contain pointers to its respective packet buffer. 
   The preceding, example describes a x8 5 Gig PICe port that can bifurcate to 2×4 5 Gig PCIe ports. The present embodiment can be adapted to other speeds, port segmentations for example quad-furcation, and protocols, to provide the benefit there from. 
   Numerous modifications, variations and adaptations may be made to the particular embodiments described above without departing from the scope patent disclosure, which is defined in the claims.