Patent Publication Number: US-9841460-B2

Title: Integrated circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2014-0113493, filed on Aug. 28, 2014, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Technical Field 
     Embodiments of the present disclosure generally relate to an integrated circuit having a structure including a plurality of semiconductor devices that are stacked. 
     2. Related Art 
     Recently, as a packaging technology for an integrated circuit is rapidly developed, an integrated circuit, in which a plurality of semiconductor devices are stacked in a single package, has been suggested. The semiconductor devices stacked in the integrated circuit are formed with electrodes and through-silicon vias. Various internal signals and a variety of power may be transferred through the electrodes and the through-silicon vias. 
     Bump pads are used to supply the various internal signals and the different power among the plurality of semiconductor devices stacked in the integrated circuit. Such bump pads are designed to have a diameter of several tens of micrometers, for a high speed operation and high integration. 
     Because such bump pads with the size of several tens of micrometers are too small in size to be probed by the probe pins of test equipment, it is usually found that a semiconductor device is separately formed with probe pads having a size larger than the bump pads, so as to be tested. 
     SUMMARY 
     In an embodiment, an integrated circuit may include a first semiconductor device including a first through-silicon via configured for electrically coupling a first bump pad to a second bump pad. The first semiconductor device configured to buffer a first internal test signal generated by a test signal inputted through the first bump pad and configured to generate a first detection signal. The integrated circuit may include a second semiconductor device including a second through-silicon via configured for electrically coupling a third bump pad to a fourth bump pad. The second semiconductor device configured to buffer a second internal test signal generated by the test signal inputted through the third bump pad and configured to generate a second detection signal. The third bump pad may be electrically coupled with the second bump pad. 
     In an embodiment, an integrated circuit may include a first semiconductor device configured to output a first test signal through a first bump pad and output a second test signal through a second bump pad. The integrated circuit may include a second semiconductor device including a first through-silicon via configured for electrically coupling a third bump pad to a fourth bump pad. The second semiconductor device may include a second through-silicon via configured for electrically coupling a fifth bump pad to a sixth bump pad. The second semiconductor device may be configured to buffer a first internal test signal generated by the first test signal and generate a first detection signal. The second semiconductor device may be configured to buffer a second internal test signal generated by the second test signal and generate a second detection signal. The third bump pad being electrically coupled with the first bump pad and the fifth bump pad may be electrically coupled with the second bump pad. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating a representation of an example of the configuration of an integrated circuit in accordance with an embodiment. 
         FIG. 2  is a block diagram illustrating a representation of an example of the configuration of the first input circuit included in the semiconductor device illustrated in  FIG. 1 . 
         FIG. 3  is a representation of an example of a timing diagram to assist in the explanation of operations of the integrated circuit in accordance with the embodiments. 
         FIG. 4  is a block diagram illustrating a representation of an example of the configuration of an integrated circuit in accordance with an embodiment. 
         FIG. 5  illustrates a block diagram of an example of a representation of a system employing the integrated circuit in accordance with the embodiments discussed above with relation to  FIGS. 1-4 . 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, an integrated circuit will be described below with reference to the accompanying drawings through various examples of embodiments. 
     Various embodiments may be directed to an integrated circuit of a stacked structure, capable of testing electrical coupling states of bump pads and through-silicon vias. 
     According to the embodiments, advantages may be provided in that it may be possible to test electrical coupling states between bump pads and through-silicon vias included in semiconductor devices having a stacked structure. 
       FIG. 1  is a block diagram illustrating a representation of an example of the configuration of an integrated circuit in accordance with an embodiment. 
     Referring to  FIG. 1 , the integrated circuit in accordance an embodiment may include a first semiconductor device  10 , a second semiconductor device  20 , and a third semiconductor device  30 . 
     The first semiconductor device  10  may include a first bump pad  11 . The first semiconductor device  10  may output a test signal EBT through the first bump pad  11 . The first semiconductor device  10  may be configured to include a controller, a processor or a system for controlling a semiconductor device. 
     While it is illustrated that the first semiconductor device  10  is configured to include the first bump pad  11 , it is to be noted that the first semiconductor device  10  may be realized to have a configuration that includes a plurality of bump pads. The first bump pad  11  may be configured to have a diameter of several tens of micrometers. 
     The second semiconductor device  20  may be configured with a first through-silicon via  22  electrically coupling a second bump pad  21  to a third bump pad  26 . The second semiconductor device  20  may include a first input circuit  23  configured for buffering a first internal test signal IBT 1  generated by the test signal EBT inputted through the second bump pad  21 . The first input circuit  23  may generate a first detection signal IDT 1 . The second semiconductor device  20  may include a first switch unit  25  configured for electrically decoupling a first probe pad  24  from the first through-silicon via  22  as a transfer gate TG 21  is turned off when a test enable signal PTEN is enabled to a logic low level. The first switch unit  25  may be configured to drive the first internal test signal IBT 1  from the first through-silicon via  22  through the first probe pad  24  when the transfer gate TG 21  is turned on when the test enable signal PTEN is disabled to a logic high level. The test enable signal PTEN may be a signal enabled in the example when entering a test mode for testing the electrical coupling states between a plurality of bump pads and a plurality of through-silicon vias and is received from outside the integrated circuit. 
     While it is illustrated that the second semiconductor device  20  is configured to include the second and third bump pads  21  and  26  and the first probe pad  24 , it is to be noted that the second semiconductor device  20  may be realized to have a configuration that includes a plurality of bump pads and a plurality of probe pads. The second and third bump pads  21  and  26  may be realized to have a diameter of several tens of micrometers, and the first probe pad  24  may be realized to have a size allowing for the first probe pad  24  to be probed using the probe pin of test equipment. 
     The third semiconductor device  30  may be configured with a second through-silicon via  32  electrically coupling a fourth bump pad  31  to a fifth bump pad  36 . The third semiconductor device  30  may include a second input circuit  33  configured for buffering a second internal test signal IBT 2  generated by the test signal EBT inputted through the fourth bump pad  31 . The second input circuit  33  may generate a second detection signal IDT 2 . The third semiconductor device  30  may include a second switch unit  35  configured for electrically decoupling a second probe pad  34  from the second through-silicon via  32  as a transfer gate TG 31  is turned off when the test enable signal PTEN is enabled to the logic low level. The second switch unit  35  may be configured to drive the second internal test signal IBT 2  from the second through-silicon via  32  through the second probe pad  34  as the transfer gate TG 31  is turned on when the test enable signal PTEN is disabled to the logic high level. 
     While it is illustrated that the third semiconductor device  30  is configured to include the fourth and fifth bump pads  31  and  36  and the second probe pad  34 , it is to be noted that the third semiconductor device  30  may be realized to have a configuration that includes a plurality of bump pads and a plurality of probe pads. The fourth and fifth bump pads  31  and  36  may be realized to have a diameter of several tens of micrometers, and the second probe pad  34  may be realized to have a size allowing for the second probe pad  34  to be probed using the probe pin of the test equipment. Although not illustrated in the drawing, the fifth bump pad  36  may be configured to be electrically coupled with a bump pad included in another semiconductor device. 
     Referring to  FIG. 2 , the first input circuit  23  included in the second semiconductor device  20  (see  FIG. 1 ) may include a first input buffer  231 , a first delay unit  232 , and a second input buffer  233 . The first input circuit  23  may include a second delay unit  234 , and a first selective transfer unit  235 . 
     The first input buffer  231  may buffer the first internal test signal IBT 1  and may generate a first transfer signal TS 1 , in the example where a first probe select signal PTCS 1  or a first select signal CS 1  is enabled. The first probe select signal PTCS 1  may be a signal received from outside the second semiconductor device  20  to drive the first internal test signal IBT 1  from the first through-silicon via  22  through the first probe pad  24  (see  FIG. 1 ). The first select signal CS 1  may be a signal received from outside the second semiconductor device  20  to test the electrical coupling states between the bump pads  21  and  26  and the first through-silicon via  22  upon entry into the test mode. 
     The first delay unit  232  may buffer the first transfer signal TS 1  and may generate a first delayed signal DS 1 . The first delay unit  232  may drive the first delayed signal DS 1  with a driving force for securing the setup/hold time margins of the first delayed signal DS 1 . A setup time may be defined as, for example, a minimum amount of time for the logic level of the first delayed signal DS 1  to transition before a time at which the first delayed signal DS 1  is synchronized with a clock, in a synchronous semiconductor device. A hold time may be defined as, for example, a minimum amount of time for the logic level of the first delayed signal DS 1  to be retained from the time at which the first delayed signal DS 1  is synchronized with the clock. 
     The second input buffer  233  may buffer the first transfer signal TS 1  and may generate a second transfer signal TS 2 , in the examples where the first probe select signal PTCS 1  is enabled. 
     The second delay unit  234  may buffer the second transfer signal TS 2  and may generate a second delayed signal DS 2 . The second delay unit  234  may be realized by the same circuit as the first delay unit  232 , and may drive the second delayed signal DS 2  with a driving force for securing the setup/hold time margins of the second delayed signal DS 2 . 
     The first selective transfer unit  235  may be configured by a transfer gate TG 22  when turned on transfers the first delayed signal DS 1  as the first detection signal IDT 1  in the examples where the test enable signal PTEN is enabled to the logic low level. A transfer gate TG 23  when turned on transfers the second delayed signal DS 2  as the first detection signal IDT 1  in the examples where the test enable signal PTEN is disabled to the logic high level. That is to say, the first selective transfer unit  235  may transfer the first delayed signal DS 1  as the first detection signal IDT 1  in the examples where the test enable signal PTEN is enabled, and transfers the second delayed signal DS 2  as the first detection signal IDT 1  in the examples where the test enable signal PTEN is disabled. 
     Since the second input circuit  33  included in the third semiconductor device  30  is realized by the same circuit and performs the same operation as the first input circuit  23  illustrated in  FIG. 2  except that the signals inputted thereto and outputted therefrom are different, detailed descriptions thereof will be omitted herein. 
     Operations of the second semiconductor device  20  as an example of the operations of the integrated circuit configured as mentioned above will be described below with reference to  FIG. 3 , by being divided into an operation for testing the electrical coupling states of a plurality of bump pads and a plurality of through-silicon vias by not using probe pads and an operation for testing the electrical coupling states of the plurality of bump pads and the plurality of through-silicon vias by using the probe pads. 
     First, the operations of the second semiconductor device  20  for testing the electrical coupling states of the plurality of bump pads and the plurality of through-silicon vias by not using the probe pads upon entry to the test mode will be described. 
     At a time T 1 , the first semiconductor device  10  may output the test signal EBT having a logic high level through the first bump pad  11 . 
     The second semiconductor device  20  may be inputted with the test signal EBT through the second bump pad  21 , generates the first internal test signal IBT 1  of a logic high level, and outputs the test signal EBT through the first through-silicon via  22  and the third bump pad  26 . The first switch unit  25  may be inputted with the test enable signal PTEN having a logic low level, and may electrically decouple the first probe pad  24  and the first through-silicon via  22 . 
     At a time T 2 , the first input buffer  231  of the first input circuit  23  may buffer the first internal test signal IBT 1  generated at the time T 1 , and may generate the first transfer signal TS 1  having a logic high level. The second input buffer  233  may be inputted with the first probe select signal PTCS 1  (not illustrated) which may be disabled, and thus, may not be driven. 
     At a time T 3 , the first delay unit  232  may buffer the first transfer signal TS 1  generated at the time T 2 , and may generate the first delayed signal DS 1  having a logic high level. The second delay unit  234  may buffer the second transfer signal TS 2  generated at the time T 2 , and may generate the second delayed signal DS 2  having a logic low level. The first selective transfer unit  235  may be inputted with the test enable signal PTEN having a logic low level, and may transfer the first delayed signal DS 1  having the logic high level as the first detection signal IDT 1 . 
     Since the logic level of the test signal EBT is inputted having the logic high level and the logic level of the first detection signal IDT 1  are the same, it may be seen that the electrical coupling states of the second and third bump pads  21  and  26  and the first through-silicon via  22  included in the second semiconductor device  20  are good or performing as intended. In the examples where the logic level of the test signal EBT is inputted having the logic high level and the logic level of the first detection signal IDT 1  are different, it may be seen that the electrical coupling states of the second and third bump pads  21  and  26  and the first through-silicon via  22  included in the second semiconductor device  20  are not performing as intended, performing poorly, or bad. 
     Next, the operations of the second semiconductor device  20  for testing the electrical coupling states of the plurality of bump pads and the plurality of through-silicon vias by using the probe pads upon entry to the test mode will be described. 
     At a time T 4 , the first switch unit  25  is inputted with the test enable signal PTEN having a logic high level, and electrically couples the first probe pad  24  and the first through-silicon via  22 . 
     At a time T 5 , since the first through-silicon via  22  is driven to a logic high level if the first probe pad  24  is driven to a logic high level, the first internal test signal IBT 1  is generated to the logic high level. 
     At a time T 6 , the first input buffer  231  of the first input circuit  23  buffers the first internal test signal IBT 1  having a logic high level generated at the time T 5 , and generates the first transfer signal TS 1  having a logic high level. 
     At a time T 7 , the first delay section  232  buffers the first transfer signal TS 1  generated at the time T 6 , and generates the first delayed signal DS 1  having a logic high level. The second input buffer  233  is inputted with the first probe select signal PTCS 1  which is enabled, buffers the first transfer signal TS 1  generated at the time T 6 , and generates the second transfer signal TS 2  having a logic high level. 
     At a time T 8 , the second delay unit  234  buffers the second transfer signal TS 2  generated at the time T 7 , and generates the second delayed signal DS 2  having a logic high level. The first selective transfer unit  235  is inputted with the test enable signal PTEN having a logic high level, and transfers the second delayed signal DS 2  having a logic high level as the first detection signal IDT 1 . 
     Since the logic level of the first probe pad  24  driven to the logic high level and the logic level of the first detection signal IDT 1  are the same, it may be seen that the electrical coupling states of the second and third bump pads  21  and  26  and the first through-silicon via  22  included in the second semiconductor device  20  are good or performing as intended. In the example where the logic level of the first probe pad  24  driven to the logic high level and the logic level of the first detection signal IDT 1  are different, it may be seen that the electrical coupling states of the second and third bump pads  21  and  26  and the first through-silicon via  22  included in the second semiconductor device  20  are not performing as intended, performing poorly, or bad. 
     A method for testing the electrical coupling states of the second and third bump pads  21  and  26  included in the second semiconductor device  20  and the fourth and fifth bump pads  31  and  36  and the second through-silicon via  32  included in the third semiconductor device  30  by the first through-silicon via  22  driven to the logic high level may be easily performed by a person skilled in the art through referring to the above descriptions, and thus, detailed descriptions thereof will be omitted. 
     The integrated circuit according to an embodiment, configured as mentioned above, may test the electrical coupling states between the plurality of bump pads and the plurality of through-silicon vias included in semiconductor devices with a stacked structure. 
       FIG. 4  is a block diagram illustrating a representation of an example of the configuration of an integrated circuit in accordance with an embodiment. 
     Referring to  FIG. 4 , the integrated circuit in accordance with an embodiment may include a first semiconductor device  100 , a second semiconductor device  200 , and a third semiconductor device  300 . 
     The first semiconductor device  100  may include first and second bump pads  101  and  102 . The first semiconductor device  100  may output a first test signal EBT 1  through the first bump pad  101 . The first semiconductor device  100  may output a second test signal EBT 2  through the second bump  102 . The first semiconductor device  100  may be configured by a controller, a processor or a system which controls a semiconductor device. The first and second bump pads  101  and  102  may be configured to have a diameter of several tens of micrometers. 
     The second semiconductor device  200  may be configured with a first through-silicon via  204 . The first through-silicon via  204  may electrically couple a third bump pad  201  to a fourth bump pad  214 . The second semiconductor device  200  may include a second through-silicon via  205 . The second through-silicon via  205  may electrically couple a fifth bump pad  202  to a sixth bump pad  215 . The second semiconductor device  200  may include a third through-silicon via  206 . The third through-silicon via  206  may electrically couple an external pad  203  to a seventh bump pad  216 . The second semiconductor device  200  may include a first internal pad  207  to which a first test enable signal PTEN 1  generated by a test enable signal PTEN inputted through the external pad  203  may be applied. The second semiconductor device  200  may include a first input circuit  208 . The first input circuit  208  may buffer a first internal test signal IBT 1 . The first internal test signal IBT 1  may be generated by the first test signal EBT 1  received through the third bump pad  201  and the first input circuit  208  may generate a first detection signal IDT 1 . The second semiconductor device  100  may include a first switch unit  210  configured for electrically decoupling a first probe pad  209  from the first through-silicon via  204  as a transfer gate TG 201  is turned off when the first test enable signal PTEN 1  is enabled to a logic low level. The first switch unit  210  is configured for driving the first test enable signal PTEN 1  through the first through-silicon via  204  through the first probe pad  209  as the transfer gate TG 201  is turned on when the first test enable signal PTEN 1  is disabled to a logic high level. The second semiconductor device  100  may include a second input circuit  211 . The second input circuit  211  may buffer a second internal test signal IBT 2 . The second internal test signal IBT 2  may be generated by the second test signal EBT 2  received through the fifth bump pad  202  and the second input circuit  211  may generate a second detection signal IDT 2 . The second semiconductor device  100  may include a second switch unit  213  configured for electrically decoupling a second probe pad  212  from the second through-silicon via  205  as a transfer gate TG 202  is turned off when the first test enable signal PTEN 1  is enabled to the logic low level. The second switch unit  213  is configured for driving the first test enable signal PTEN 1  through the second through-silicon via  205  through the second probe pad  212  as the transfer gate TG 202  is turned on when the first test enable signal PTEN 1  is disabled to the logic high level. The test enable signal PTEN may be a signal which is enabled in the example of entering a test mode for testing the electrical coupling states between a plurality of bump pads and a plurality of through-silicon vias and is inputted through the external pad  203 . The third to seventh bump pads  201 ,  214 ,  202 ,  215  and  216  may be configured to have a diameter of several tens of micrometers, and the first and second probe pads  209  and  212  may be configured to have a size to be probed using the probe pins of test equipment. 
     The third semiconductor device  300  may be configured with a fourth through-silicon via  304 . The third semiconductor device  300  may electrically couple an eighth bump pad  301  to a ninth bump pad  314 . The third semiconductor device  300  may include a fifth through-silicon via  305 . The fifth through-silicon via  305  may electrically couple a tenth bump pad  302  to an eleventh bump pad  315 . The third semiconductor device  300  may include a sixth through-silicon via  306 . The sixth through-silicon via  306  may electrically couple a twelfth bump pad  303  to a thirteenth bump pad  316 . The third semiconductor device  300  may include a second internal pad  307  to which a second test enable signal PTEN 2  generated by the test enable signal PTEN inputted through the twelfth bump pad  303  may be applied. The third semiconductor device  300  may include a third input circuit  308 . The third input circuit  308  may buffer a third internal test signal IBT 3 . The third internal test signal IBT 3  may be generated by the first test signal EBT 1  received through the eighth bump pad  301  and the third input circuit  308  may generate a third detection signal IDT 3 . The third semiconductor device  300  may include a third switch unit  310  configured for electrically decoupling a third probe pad  309  from the fourth through-silicon via  304  as a transfer gate TG 301  is turned off when the second test enable signal PTEN 2  is enabled to a logic low level. The third switch unit  310  is configured for driving the second test enable signal PTEN 2  through the fourth through-silicon via  304  through the third probe pad  309  as the transfer gate TG 301  is turned on when the second test enable signal PTEN 2  is disabled to a logic high level. The third semiconductor device  300  may include a fourth input circuit  311 . The fourth input circuit  311  may buffer a fourth internal test signal IBT 4 . The fourth internal test signal IBT 4  may be generated by the second test signal EBT 2  received through the tenth bump pad  302  and the fourth input circuit  311  may generate a fourth detection signal IDT 4 . The third semiconductor device  300  may include a fourth switch unit  313  configured for electrically decoupling a fourth probe pad  312  from the fifth through-silicon via  305  as a transfer gate TG 302  is turned off when the second test enable signal PTEN 2  is enabled to the logic low level. The fourth switch unit  313  is configured for driving the second test enable signal PTEN 2  through the fifth through-silicon via  305  through the fourth probe pad  312  as the transfer gate TG 302  is turned on when the second test enable signal PTEN 2  is disabled to the logic high level. The eighth to thirteenth bump pads  301 ,  314 ,  302 ,  315 ,  303  and  316  may be configured to have a diameter of several tens of micrometers, and the third and fourth probe pads  309  and  312  may be configured to have a size to be probed using the probe pins of the test equipment. Although not illustrated in the drawing, the ninth bump pad  314 , the eleventh bump pad  315  and the thirteenth bump pad  316  may be configured to be electrically coupled with bump pads which are included in another semiconductor device. 
     An operation for testing the electrical coupling states of a plurality of bump pads and a plurality of through-silicon vias by not using probe pads, as an example of operations of the integrated circuit configured as mentioned above, will be described below with reference to  FIG. 4 , by being divided into the examples where the electrical coupling states between the third bump pad  201  and the first through-silicon via  204  of the second semiconductor device  200  and between the fifth bump pad  202  and the second through-silicon via  205  of the second semiconductor device  200  are performing as intended or the connection is good and the examples where the electrical coupling state between the fifth bump pad  202  and the second through-silicon via  205  of the second semiconductor device  200  is not performing as intended, performing poorly, or bad. 
     First, the case where the electrical coupling states between the third bump pad  201  and the first through-silicon via  204  of the second semiconductor device  200  and between the fifth bump pad  202  and the second through-silicon via  205  of the second semiconductor device  200  are good or performing as intended will be described. 
     The first semiconductor device  100  may output the first test signal EBT 1  of a logic high level through the first bump pad  101 , and may output the second test signal EBT 2  of a logic high level through the second bump pad  102 . 
     The second semiconductor device  200  is inputted with the first test signal EBT 1  through the third bump pad  201  and generates the first internal test signal IBT 1  of a logic high level, and is inputted with the second test signal EBT 2  through the fifth bump pad  202  and generates the second internal test signal IBT 2  of a logic high level. The first test enable signal PTEN 1 , which is generated by being inputted with the test enable signal PTEN of the logic low level through the external pad  203 , is applied to the first internal pad  207 . 
     The first switch unit  210  is inputted with the first test enable signal PTEN 1  of the logic low level and electrically decouples the first probe pad  209  and the first through-silicon via  204 . 
     The first input circuit  208  buffers the first internal test signal IBT 1  and generates the first detection signal IDT 1  of a logic high level. 
     The second switch unit  213  is inputted with the first test enable signal PTEN 1  of the logic low level and electrically decouples the second probe pad  212  and the second through-silicon via  205 . 
     The second input circuit  211  buffers the second internal test signal IBT 2  and generates the second detection signal IDT 2  of a logic high level. 
     Since the logic level of the first test signal EBT 1  inputted at the logic high level and the logic level of the first detection signal IDT 1  are the same and the logic level of the second test signal EBT 2  inputted at the logic high level and the logic level of the second detection signal IDT 2  are the same, it may be that the electrical coupling states between the third bump pad  201  and the first through-silicon via  204  included in the second semiconductor device  200  and between the fifth bump pad  202  and the second through-silicon via  205  included in the second semiconductor device  200  are performing as intended or good. 
     Next, the example where the electrical coupling state between the fifth bump pad  202  and the second through-silicon via  205  of the second semiconductor device  200  is not performing as intended, performing poorly or is bad will be described. 
     The first semiconductor device  100  may output the first test signal EBT 1  of the logic high level through the first bump pad  101 , and may output the second test signal EBT 2  of the logic high level through the second bump pad  102 . 
     The second semiconductor device  200  is inputted with the first test signal EBT 1  through the third bump pad  201  and generates the first internal test signal IBT 1  of the logic high level, and is inputted with the second test signal EBT 2  through the fifth bump pad  202  and generates the second internal test signal IBT 2  of a logic low level. Since the electrical coupling state between the fifth bump pad  202  and the second through-silicon via  205  is not performing as intended, performing poorly, or bad and thus the second test signal EBT 2  is not transferred, the second internal test signal IBT 2  is generated to the logic low level. The first test enable signal PTEN 1 , which is generated by being inputted with the test enable signal PTEN of the logic low level through the external pad  203 , is applied to the first internal pad  207 . 
     The first switch unit  210  is inputted with the first test enable signal PTEN 1  of the logic low level and electrically decouples the first probe pad  209  and the first through-silicon via  204 . 
     The first input circuit  208  buffers the first internal test signal IBT 1  and generates the first detection signal IDT 1  of the logic high level. 
     The second switch unit  213  is inputted with the first test enable signal PTEN 1  of the logic low level and electrically decouples the second probe pad  212  and the second through-silicon via  205 . 
     The second input circuit  211  buffers the second internal test signal IBT 2  and generates the second detection signal IDT 2  having a logic low level. 
     Since the logic level of the second test signal EBT 2  inputted at the logic high level and the logic level of the second detection signal IDT 2  are different, it may be seen that the electrical coupling state between the fifth bump pad  202  and the second through-silicon via  205  included in the second semiconductor device  200  is bad or not performing as intended, performing poorly. 
     As is apparent from the above descriptions, in the integrated circuit according to the embodiments, configured as mentioned above, it may be possible to test electrical coupling states between a plurality of bump pads and a plurality of through-silicon vias included in semiconductor devices including a stacked structure. 
     The integrated circuits discussed above (see  FIGS. 1-4 ) are particular useful in the design of memory devices, processors, and computer systems. For example, referring to  FIG. 5 , a block diagram of a system employing the integrated circuits in accordance with the embodiments are illustrated and generally designated by a reference numeral  1000 . The system  1000  may include one or more processors or central processing units (“CPUs”)  1100 . The CPU  1100  may be used individually or in combination with other CPUs. While the CPU  1100  will be referred to primarily in the singular, it will be understood by those skilled in the art that a system with any number of physical or logical CPUs may be implemented. 
     A chipset  1150  may be operably coupled to the CPU  1100 . The chipset  1150  is a communication pathway for signals between the CPU  1100  and other components of the system  1000 , which may include a memory controller  1200 , an input/output (“I/O”) bus  1250 , and a disk drive controller  1300 . Depending on the configuration of the system, any one of a number of different signals may be transmitted through the chipset  1150 , and those skilled in the art will appreciate that the routing of the signals throughout the system  1000  can be readily adjusted without changing the underlying nature of the system. 
     As stated above, the memory controller  1200  may be operably coupled to the chipset  1150 . The memory controller  1200  may include at least one integrated circuit as discussed above with reference to  FIGS. 1-4 . Thus, the memory controller  1200  can receive a request provided from the CPU  1100 , through the chipset  1150 . In alternate embodiments, the memory controller  1200  may be integrated into the chipset  1150 . The memory controller  1200  may be operably coupled to one or more memory devices  1350 . In an embodiment, the memory devices  1350  may include the at least one integrated circuit as discussed above with relation to  FIGS. 1-4 , the memory devices  1350  may include a plurality of word lines and a plurality of bit lines for defining a plurality of memory cell. The memory devices  1350  may be any one of a number of industry standard memory types, including but not limited to, single inline memory modules (“SIMMs”) and dual inline memory modules (“DIMMs”). Further, the memory devices  1350  may facilitate the safe removal of the external data storage devices by storing both instructions and data. 
     The chipset  1150  may also be coupled to the I/O bus  1250 . The I/O bus  1250  may serve as a communication pathway for signals from the chipset  1150  to I/O devices  1410 ,  1420  and  1430 . The I/O devices  1410 ,  1420  and  1430  may include a mouse  1410 , a video display  1420 , or a keyboard  1430 . The I/O bus  1250  may employ any one of a number of communications protocols to communicate with the I/O devices  1410 ,  1420 , and  1430 . Further, the I/O bus  1250  may be integrated into the chipset  1150 . 
     The disk drive controller  1450  (i.e., internal disk drive) may also be operably coupled to the chipset  1150 . The disk drive controller  1450  may serve as the communication pathway between the chipset  1150  and one or more internal disk drives  1450 . The internal disk drive  1450  may facilitate disconnection of the external data storage devices by storing both instructions and data. The disk drive controller  1300  and the internal disk drives  1450  may communicate with each other or with the chipset  1150  using virtually any type of communication protocol, including all of those mentioned above with regard to the I/O bus  1250 . 
     It is important to note that the system  1000  described above in relation to  FIG. 5  is merely one example of a system employing the integrated circuit as discussed above with relation to  FIGS. 1-4 . In alternate embodiments, such as cellular phones or digital cameras, the components may differ from the embodiments illustrated in  FIG. 5 . 
     While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the integrated circuit described herein should not be limited based on the described embodiments.