Patent Publication Number: US-2021183662-A1

Title: Semiconductor Device Assembly with Pillar Array

Description:
RELATED APPLICATIONS 
     The present application is a continuation patent application of U.S. patent application Ser. No. 16/513,466 entitled Semiconductor Device Assembly with Pillar Array and Test Ability filed on Jul. 16, 2019 and published as U.S. Patent App. Pub. No. 2019/0341270, which is a divisional patent application of U.S. patent application Ser. No. 15/830,839 entitled Semiconductor Device Assembly with Pillar Array filed on Dec. 4, 2017 and issued as U.S. Pat. No. 10,529,592 on Jan. 7, 2020, which are both incorporated by reference herein in their entirety. 
    
    
     FIELD 
     The embodiments described herein relate to semiconductor devices, semiconductor device assemblies, and methods of providing such semiconductor devices and semiconductor device assemblies. The present disclosure relates to a semiconductor device having a plurality of pillars extending from a bottom surface that are formed from vias filled with a conductive material, also referred to herein as a through silicon via (TSV). The vias may be filled with copper, tungsten, poly silicon, or the like. The plurality of pillars may be in a rectangular array positioned adjacent to a side of the semiconductor device. 
     BACKGROUND 
     Semiconductor device assemblies, including, but not limited to, memory chips, microprocessor chips, imager chips, and the like, typically include a semiconductor device, such as a die, mounted on a substrate. The semiconductor device assembly may include various functional features, such as memory cells, processor circuits, and imager devices, and may include bond pads that are electrically connected to the functional features of the semiconductor device assembly. The semiconductor device assembly may include semiconductor devices stacked upon and electrically connected to one another by individual interconnects between adjacent devices within a package. 
     Various methods and/or techniques may be employed to electrically interconnect adjacent semiconductor devices and/or substrates in a semiconductor device assembly. For example, individual interconnects may be formed by reflowing tin-silver (SnAg), also known as solder, to connect a pillar to a pad. Typically, the pillar may extend down from a bottom surface of a semiconductor device towards a pad formed on the top surface of another semiconductor device or substrate. A grid array of solder balls may be used to connect a semiconductor device assembly to a circuit board or other external device. However, a grid array of solder balls may not permit the connection of a semiconductor device assembly to a device in all applications. Further, it may be beneficial to provide semiconductor device assembly that permits test ability while connected to an external device. Additional drawbacks and disadvantages may exist. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional schematic of an embodiment of a semiconductor device assembly. 
         FIG. 2  is a cross-sectional schematic of an embodiment of a semiconductor device assembly. 
         FIG. 3  is a cross-sectional schematic of an embodiment of a semiconductor device assembly. 
         FIG. 4  is a cross-sectional schematic of an embodiment of a semiconductor device assembly. 
         FIG. 5  is a partial cross-section schematic of an embodiment of a semiconductor device. 
         FIG. 6  is a bottom view schematic of an embodiment of a semiconductor device. 
         FIG. 7A  is a cross-sectional schematic of an embodiment of a semiconductor device. 
         FIG. 7B  is a cross-sectional schematic of an embodiment of a semiconductor device. 
         FIG. 7C  is a cross-sectional schematic of an embodiment of a semiconductor device. 
         FIG. 7D  is a cross-sectional schematic of an embodiment of a semiconductor device. 
         FIG. 7E  is a cross-sectional schematic of an embodiment of a semiconductor device. 
         FIG. 8  is a cross-sectional schematic of an embodiment of a semiconductor device. 
         FIG. 9  is a flow chart of one embodiment of a method of making a semiconductor device assembly. 
     
    
    
     While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the intention is to cover all modifications, equivalents and alternatives falling within the scope of the disclosure as defined by the appended claims. 
     DETAILED DESCRIPTION 
     In this disclosure, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present disclosure. One of ordinary skill in the art will recognize that the disclosure can be practiced without one or more of the specific details. Well-known structures and/or operations often associated with semiconductor devices may not be shown and/or may not be described in detail to avoid obscuring other aspects of the disclosure. In general, it should be understood that various other devices, systems, and/or methods in addition to those specific embodiments disclosed herein may be within the scope of the present disclosure. 
     The term “semiconductor device assembly” can refer to an assembly of one or more semiconductor devices, semiconductor device packages, and/or substrates, which may include interposers, supports, and/or other suitable substrates. The semiconductor device assembly may be manufactured as, but not limited to, discrete package form, strip or matrix form, and/or wafer panel form. The term “semiconductor device” generally refers to a solid-state device that includes semiconductor material. A semiconductor device can include, for example, a semiconductor substrate, wafer, panel, or a single die from a wafer or substrate. A semiconductor device may refer herein to a semiconductor die, but semiconductor devices are not limited to semiconductor dies. 
     The term “semiconductor device package” can refer to an arrangement with one or more semiconductor devices incorporated into a common package. A semiconductor package can include a housing or casing that partially or completely encapsulates at least one semiconductor device. A semiconductor package can also include a substrate that carries one or more semiconductor devices. The substrate may be attached to or otherwise incorporate within the housing or casing. 
     As used herein, the terms “vertical,” “lateral,” “upper,” and “lower” can refer to relative directions or positions of features in the semiconductor devices and/or semiconductor device assemblies shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices and/or semiconductor device assemblies having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, and left/right can be interchanged depending on the orientation. 
     Various embodiments of this disclosure are directed to semiconductor devices, semiconductor device assemblies, and methods of making and/or operating semiconductor devices and/or semiconductor device assemblies. In one embodiment of the disclosure a semiconductor device assembly comprises a first substrate having a first surface and a second surface opposite the first surface with a second substrate disposed over the first substrate, the second substrate having a first surface and a second surface opposite the first surface. The semiconductor device assembly includes at least one interconnect between the second surface of the second substrate and the first surface of the first substrate and at least one pillar extending from the second surface of the first substrate, the at least one pillar being comprised of copper, or the like, being electrically connected to the at least one interconnect, and being positioned adjacent to a side of the first substrate. 
     In one embodiment of the disclosure a semiconductor device comprises a substrate having a top surface and a bottom surface opposite the top surface with at least one pad on the top surface of the substrate, the pad being configured to connect to a pillar from a semiconductor device. The semiconductor device comprising a plurality of pillars extending from the bottom surface of the substrate, each pillar being comprised of copper, or the like, being positioned in a rectangular array positioned adjacent to a side of the substrate, and being electrically connected to the at least one pad. 
     One embodiment of the disclosure is a method of making a semiconductor device comprising providing a silicon substrate having a first surface and a second surface opposite the first surface. The method comprising forming a first layer on the silicon substrate and forming a second layer on the first layer. The first layer may be comprised of a plurality of layers and the second layer may be comprised of a plurality of layers as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. The method comprises creating at least one TSV that extends from the second layer, through the first layer, and into the silicon substrate. The method comprises filling the at least one TSV with a conductive material, such as copper, or the like, with the at least on TSV being positioned adjacent to a side of the silicon substrate. The method comprises forming at least a third layer on the second layer, the third layer including at least one pad configured to connect to a semiconductor device and interconnections between the at least one filled TSV and the at least one pad. The method comprises removing silicon from the second surface of the silicon substrate to expose a portion of the at least one filed TSV. 
       FIG. 1  shows an embodiment of a semiconductor device assembly  100 A that includes a first substrate  110 A and a second substrate  120 A that is disposed over the first substrate  110 A. The first substrate  110 A includes a first or top surface  111  and a second or bottom surface  112  opposite the first surface  111 . The first substrate  110 A includes a pad  113  on the first surface  111  and a plurality of pads  116  on the second surface  112 . A plurality of pillars  115 B extend from the second surface  112  of the first substrate  110 A with a portion of the pillars  115 A positioned within the first substrate  110 A. The pillars  115 A,  115 B are formed by filling TSVs in the first substrate  110 A with a conductive material, as discussed herein. The pillars  115 A,  115 B are positioned adjacent to a side of the first substrate  110 A, as shown in  FIG. 1 . Interconnections  114  within the first substrate  110 A electrically connect the pillars  115 A,  115 B with the pad  113  on the first surface  111  of the first substrate  110 A. Likewise, the interconnections  114  within the first substrate  110 A electrically connect the pads  116  on the second surface  112  of the first substrate  110 A with the pad  113  on the first surface  111  of the first substrate  110 A. 
     The second substrate  120 A includes a first or top surface and a second or bottom surface opposite of the first surface. At least one pillar  125  extends from the second surface of the second substrate  120 A. An interconnect  140  is formed between the pillar  125  of the second substrate  120 A and the pad  113  located on the first surface  111  of the first substrate  110 A. The interconnect  140  electrically connects the first substrate  110 A with the second substrate  120 A. A third substrate  120 B is disposed over the second substrate  120 A with vias  135  and interconnects  130  electrically connecting the third substrate  120 B to the second substrate  120 A. Likewise, A fourth substrate  120 C is disposed over the third substrate  120 B with vias  135  and interconnects  130  electrically connecting the fourth substrate  120 C to the third substrate  120 B. Similarly, A fifth substrate  120 D is disposed over the fourth substrate  120 C with vias  135  and interconnects  130  electrically connecting the fifth substrate  120 D to the fourth substrate  120 C. The electrical interconnects between the substrates  110 A,  120 A,  120 B,  120 C,  120 D are shown schematically for clarity and may be varied as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. It should also be noted that semiconductor device assembly  100 A may include the first substrate  110 A and the second substrate  120 A alone. 
     As would be appreciated by one of ordinary skill in the art having the benefit of this disclosure, the interconnections  130 ,  140  electrically connect each of the substrates  110 A,  120 A,  120 B,  120 C,  120 D together. The pads  116  located on the second surface  112  of the first substrate  110 A may be test pads configured to permit testing of the semiconductor device assembly  100 A. For example, a probe may contact one of the pads  116  to test the operational functionality of any one of the substrates  110 A,  120 A,  120 B,  120 C,  120 D of the semiconductor device assembly  100 A. The first substrate  110 A may be a silicon substrate. The second substrate  120 A, third substrate  120 B, fourth substrate  120 C, and fifth substrate  120 D may be various semiconductor devices. For example, the second substrate  120 A, third substrate  120 B, fourth substrate  120 C, and fifth substrate  120 D may comprise a memory stack. The number, configuration, size, and/or location of the substrates may be varied depending on the application as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. For example, the semiconductor device assembly  100 A may comprise more or less substrates than shown. Likewise, the number, size, location, and/or configuration of the pillars, pads, and/or interconnections are shown for illustrative purposes and may be varied depending on application as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. 
       FIG. 2  shows an embodiment of a semiconductor device assembly  100 B that includes a first substrate  110 B and a second substrate  120 A that is disposed over the first substrate  110 B. The first substrate  110 B includes a first or top surface  111  and a second or bottom surface  112  opposite the first surface  111 . The first substrate  110 B includes a pad  113  on the first surface  111 . The first substrate  110 B also includes a plurality of pads  116  on the first surface  111 . A plurality of pillars  115 B extend from the second surface  112  of the first substrate  110 B with a portion of the pillars  115 A positioned within the first substrate  110 B. The pillars  115 A,  115 B are formed by filling TSVs in the first substrate  110 B with a conductive material, as discussed herein. The pillars  115 A,  115 B are positioned adjacent to a side of the first substrate  110 B, as shown in  FIG. 2 . Interconnections  114  within the first substrate  110 B electrically connect the pillars  115 A,  115 B with the pad  113  on the first surface  111  of the first substrate  110 B. Likewise, the interconnections  114  within the first substrate  110 B electrically connect the pads  116  on the first surface  111  of the first substrate  110 B with the pad  113  on the first surface  111  of the first substrate  110 B. 
     As discussed above, at least one pillar  125  extends from the second substrate  120 A to form an interconnect  140  between the pillar  125  of the second substrate  120 A and the pad  113  located on the first surface  111  of the first substrate  110 B. The interconnect  140  electrically connects the first substrate  110 B with the second substrate  120 A. Vias  135  and interconnects  130  electrically connect a third substrate  120 B, a fourth substrate  120 C, and a fifth substrate  120 D to each other and to the first substrate  110 B. As shown in  FIG. 2 , the fifth substrate  120 D may not include vias  135 . Is should be noted that semiconductor device assembly  100 B may include the first substrate  110 B and second substrate  120 A alone. 
     As would be appreciated by one of ordinary skill in the art having the benefit of this disclosure, the interconnections  130 ,  140  electrically connect each of the substrates  110 B,  120 A,  120 B,  120 C,  120 D together. The pads  116  located on the first surface  111  of the first substrate  110 B may be test pads configured to permit testing of the semiconductor device assembly  100 B. For example, a probe may contact one of the pads  116  to test the operational functionality of any one of the substrates  110 B,  120 A,  120 B,  120 C,  120 D of the semiconductor device assembly  100 B. The first substrate  110 B may be a silicon substrate. The second substrate  120 A, third substrate  120 B, fourth substrate  120 C, and fifth substrate  120 D may be various semiconductor devices. For example, the second substrate  120 A, third substrate  120 B, fourth substrate  120 C, and fifth substrate  120 D may comprise a memory stack. The number, configuration, size, and/or location of the substrates may be varied depending on the application as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. For example, the semiconductor device assembly  100 B may comprise more or less substrates than shown. Likewise, the number, size, location, and/or configuration of the pillars, pads, and/or interconnections are shown for illustrative purposes and may be varied depending on application as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. 
       FIG. 3  shows an embodiment of a semiconductor device assembly  100 C that includes a first substrate  110 C and a second substrate  120 A that is disposed over the first substrate  110 C. The first substrate  110 C includes a first or top surface  111  and a second or bottom surface  112  opposite the first surface  111 . The first substrate  110 C includes a pad  113  on the first surface  111 . Likewise, the first substrate  110 C includes two pads  116  on the first surface  111  with the second substrate  120 A positioned between the two pads  116 . A plurality of pillars  115 B extend from the second surface  112  of the first substrate  110 C with a portion of the pillars  115 A positioned within the first substrate  110 C. The pillars  115 A,  115 B are formed by filling TSVs in the first substrate  110 C with a conductive material, as discussed herein. The pillars  115 A,  115 B are positioned adjacent to a side of the first substrate  110 C, as shown in  FIG. 3 . Interconnections  114  within the first substrate  110 C electrically connect the pillars  115 A,  115 B with the pads  113 ,  116  on the first surface  111  of the first substrate  110 C. 
     As discussed above, at least one pillar  125  extends from the second substrate  120 A to form an interconnect  140  between the pillar  125  of the second substrate  120 A and the pad  113  located on the first surface  111  of the first substrate  110 C. The interconnect  140  electrically connects the first substrate  110 C with the second substrate  120 A. Vias  135  and interconnects  130  electrically connect a third substrate  120 B, a fourth substrate  120 C, and a fifth substrate  120 D to each other and to the first substrate  110 C. 
     As would be appreciated by one of ordinary skill in the art having the benefit of this disclosure, the interconnections  130 ,  140  electrically connect each of the substrates  110 C,  120 A,  120 B,  120 C,  120 D together. The pads  116  located on the first surface  111  of the first substrate  110 C may be test pads configured to permit testing of the semiconductor device assembly  100 C. For example, a probe may contact one of the pads  116  to test the operational functionality of any one of the substrates  110 C,  120 A,  120 B,  120 C,  120 D of the semiconductor device assembly  100 C. The first substrate  110 C may be a silicon substrate. The second substrate  120 A, third substrate  120 B, fourth substrate  120 C, and fifth substrate  120 D may be various semiconductor devices. For example, the second substrate  120 A, third substrate  120 B, fourth substrate  120 C, and fifth substrate  120 D may comprise a memory stack. The number, configuration, size, and/or location of the substrates may be varied depending on the application as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. For example, the semiconductor device assembly  100 C may comprise more or less substrates than shown. Likewise, the number, size, location, and/or configuration of the pillars, pads, and/or interconnections are shown for illustrative purposes and may be varied depending on application as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. It should also be noted that the semiconductor device assembly  110 C may include the first substrate  110 C and the second substrate  120 A alone. 
       FIG. 4  shows an embodiment of a semiconductor device assembly  100 D that includes a first substrate  110 D and a second substrate  120 A that is disposed over the first substrate  110 D. The first substrate  110 D includes a first or top surface  111  and a second or bottom surface  112  opposite the first surface  111 . The first substrate  110 D includes a pad  113  on the first surface  111 . A plurality of pillars  115 B extend from the second surface  112  of the first substrate  110 D with a portion of the pillars  115 A positioned within the first substrate  110 D. The pillars  115 A,  115 B are formed by filling TSVs in the first substrate  110 D with a conductive material, as discussed herein. The pillars  115 A,  115 B are positioned adjacent to a side of the first substrate  110 D, as shown in  FIG. 4 . Interconnections  114  within the first substrate  110 D electrically connect the pillars  115 A,  115 B with the pad  113  on the first surface  111  of the first substrate  110 D. 
     As discussed above, at least one pillar  125  extends from the second substrate  120 D to form an interconnect  140  between the pillar  125  of the second substrate  120 A and the pad  113  located on the first surface  111  of the first substrate  110 D. The interconnect  140  electrically connects the first substrate  110 D with the second substrate  120 A. Vias  135  and interconnects  130  electrically connect a third substrate  120 B, a fourth substrate  120 C, and a fifth substrate  120 D to each other and to the first substrate  110 D. As shown in  FIG. 4 , the fifth substrate  120 D may not include vias  135 . 
     As would be appreciated by one of ordinary skill in the art having the benefit of this disclosure, the interconnections  130 ,  140  electrically connect each of the substrates  110 D,  120 A,  120 B,  120 C,  120 D together. The portion  115 B of the pillars  115  that extends from the second surface  112  of the first substrate  110 D may include an exterior layer, or coating,  118 , as discussed herein. The exterior layer  118  may enable one or more of the exposed portion  115 B of the pillars  115  to be probed to permit testing of the semiconductor device assembly  100 D. For example, a probe may contact an exposed portion  115 B of the pillars  115  to test the operational functionality of any one of the substrates  110 D,  120 A,  120 B,  120 C,  120 D of the semiconductor device assembly  100 D. The exterior layer or coating  118  may be comprised of various materials that permit the probing of a pillar  115  that may be removed by subsequent processing. For example, the exterior layer  118  may be, but is not limited to, tantalum. The exterior layer  118  may permit the probing of the pillars  115  while preventing marking and/or damaging an inner conductive material portion, which may be copper, of the pillar  115 . 
     The first substrate  110 D may be a silicon substrate. The second substrate  120 A, third substrate  120 B, fourth substrate  120 C, and fifth substrate  120 D may be various semiconductor devices. For example, the second substrate  120 A, third substrate  120 B, fourth substrate  120 C, and fifth substrate  120 D may comprise a memory stack. The number, configuration, size, and/or location of the substrates may be varied depending on the application as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. For example, the semiconductor device assembly  100 D may comprise more or less substrates than shown. Likewise, the number, size, location, and/or configuration of the pillars, pads, and/or interconnections are shown for illustrative purposes and may be varied depending on application as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. 
       FIG. 5  is a partial cross-section schematic of an embodiment of a substrate  110 . The substrate  110  includes a plurality of vias, or TSVs,  109  (only one shown in  FIG. 5 ) that have been formed into the substrate  110 . Various methods may be used to form a TSV  109  as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. The TSV  109  may first be coated with an oxide layer  119 , which is followed by a tantalum layer  118 . An inner conductive portion  117 A,  117 B may be filled with a conductive material, such as, but not limited to, copper, or the like. A first conductive layer  117 B may first be formed in the TSV  109  followed by a second conductive layer  117 A, which may be deposited into the TSV  109  by a different process than the first conductive layer  117 B. For example, the first conductive layer  117 B may be deposited via physical vapor deposition while the second conductive layer  117 A may be deposited via electrochemical deposition. The first and second conductive layers  117 A,  117 B may comprise copper, tungsten, poly silicon, or the like. 
     A portion of the substrate  110  may be removed to expose a portion of the TSV  109 , which results in an exposed portion of pillar  115 B. A portion of the TSV  109 , also referred to as pillar portion  115 A, remains within the substrate  110 . If the substrate  110  includes test pads  116  (shown in  FIGS. 1-3 ) the oxide layer  119  and tantalum layer  118  may be removed to provide an exposed conductive pillar  115 B. However, if the substrate  110  does not include any test pads  116 , the oxide layer  119  may only be removed leaving the exposed portion  115 B of the pillar  115 , or TSV  109 , to be coated with a tantalum layer  118 . The tantalum layer  118  enables the probing of the exposed pillar  115 B to test the substrate  110 . After the substrate  110  has been tested, the tantalum layer  118  may be removed to potentially leave an unmarked exposed pillar  115 B, which may be comprised of copper. The tantalum layer  118  enables testing of the substrate  110  without marking and/or damaging the inner conductive portion  117 B of the pillar  115 B. 
       FIG. 6  is a bottom view schematic of an embodiment of a semiconductor device  110 . The bottom surface  112  of the semiconductor device  110  includes a plurality of pillars  115  arranged in a high density rectangular array. As shown in  FIG. 6 , the rectangular array of pillars  115  is positioned adjacent to a side of the bottom surface  112  of the semiconductor device  110 . The array is shown as a four (4) by fifteen (15) array of pillars  115  for clarity. The size of the array, shape of the array, and/or number of pillars  115  may be varied depending on the application as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. For example, one embodiment may include an array of eight (8) by one hundred and twenty three (12 3 ) pillars positioned adjacent to a side of the semiconductor device  110 . The array area may be thirteen (13) mm by six (6) mm, the pad size for each pillar may be fifty four (54) microns, and the pad pitch may be sixty (60) microns. 
       FIGS. 7A-7E  show the formation of one embodiment of a semiconductor device  210 . A first layer  212 A may be deposited onto a surface of a substrate  211 , which may be a silicon substrate, as shown in  FIG. 7A . The formation of the first layer  212 A may include the formation of a plurality of pads  216 , which may be test pads. The number, size, location, and/or configuration of the pads  216  may be varied as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. The first layer  212 A is shown as a single layer for clarity in  FIG. 7A . However, the first layer  212 A may be comprised of multiple layers deposited onto the surface of the silicon substrate  211  as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. 
       FIG. 7B  shows at least a second layer has been added to the surface of the silicon substrate  211 . The layers  212 B on the substrate  211  include interconnects, or the like,  214  that will provide electrical connections between various elements, such as the pillars  215  and pads  216 , of the semiconductor device  210  as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. The at least second layer is shown as a single layer for clarity in  FIG. 7B  to form layers  212 B. However, the at least second layer may be comprised of multiple layers deposited onto the surface of the silicon substrate  211  as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. A plurality of TSVs, or vias, are formed into the layers  212 B and extend into a portion of the silicon substrate  211 . The TSVs are filled with a conductive material, such as copper, or the like, to form pillars  215 , as discussed herein. Various coatings may be applied to the TSVs prior to the depositing of the conductive material, as discussed herein. 
       FIG. 7C  shows at least a third layer has been added to the surface of the silicon substrate  211 . The layers  212 C on the substrate  211  now include at least one pad  213 , which provides an electrical connection between the semiconductor device  210  and an adjacent semiconductor device as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. The at least third layer is shown as a single layer for clarity in  FIG. 7C  to form layers  212 C. However, the at least third layer may be comprised of multiple layers deposited onto the surface of the silicon substrate  211  as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. As discussed above, at least one pad  213  is formed into the layers  212 C. The interconnects  214  electrically connect the pad  213  with both the pillars  215  and the test pads  216 . 
       FIG. 7D  shows an embodiment of a semiconductor device or substrate  210 A after the formation of the pad  213  shown in  FIG. 7C . A portion of the silicon substrate  211  is removed to expose a portion of the plurality of pillars  215  while leaving a portion of the silicon substrate  211  on the bottom of the semiconductor device  210 A. Various processes may be used to remove the portion of the silicon substrate  211  as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. The silicon substrate  211  prevents probing of the pads  216 . Instead, the semiconductor device  210 A may be tested by probing one or more of the pillars  215 . The pillars  215  include an exterior coating  218 , which enables the pillars  215  to be probed without causing any marking and/or damage to the inner conductive portion of the pillar  215 , as discussed herein. The coating  218  may be various materials as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. For example, the coating  218  may comprise tantalum. The coating  218  may be removed from the exterior of the pillars  215  after adequate testing of the semiconductor device  210 A, as discussed herein. 
       FIG. 7E  shows an embodiment of a semiconductor device or substrate  210 B after the formation of the pad  213  shown in  FIG. 7C . The silicon substrate  211  has been removed from the bottom of the semiconductor device  210 B expose a portion of the plurality of pillars  215  as well as test pads  216 . Various processes may be used to remove the portion of the silicon substrate  211  as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. The semiconductor device  210 B may be tested by the probing of one or more of the pads  216 . Likewise, the pads  216  may be probed to test other semiconductor devices that may be electrically connected to the semiconductor device  210 B via pad  213  on the top surface of the semiconductor device  210 B. 
       FIG. 8  shows an embodiment of a semiconductor device or substrate  310 . The semiconductor device  310  includes a pad  313  on the top surface and a plurality of pads  316  on the bottom surface. A plurality of pillars  315  extend from the bottom surface of the semiconductor device  310  with a portion of the pillars  315  being positioned within the semiconductor device  310 . As discussed herein, the pillars  315  are formed by filling TSVs in the semiconductor device  310  with copper, or the like. The pillars  315  are positioned adjacent to a side of the semiconductor device  310 . Interconnections  314  within the semiconductor device  310  electrically connect the pillars  315  with the pad  313  on the top surface. Likewise, the interconnections  314  within the semiconductor device  310  electrically connect the pads  116  on the bottom surface of the semiconductor device  310  with the pad  113  on the top surface as well as the pillars  315 . The plurality of pillars  315  include feet  319  located at the end of each pillar  315 . The feet  319  may aid in the connection of the pillars  315  to an external device. 
       FIG. 9  is a flow chart of one embodiment of a method  400  of making a semiconductor device assembly. The method  400  includes providing a silicon substrate having a first surface and a second surface opposite the first surface, at step  410 . The method  400  includes forming a first layer on the first surface of the silicon substrate, at step  420 . The first layer may be comprised of multiple layers deposited on the surface of the silicon substrate as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. At optional step  425 , the method  400  may include forming at least one test pad in the first layer, which may be multiple layers, deposited on the surface of the substrate. The method  400  includes forming a second layer on the first surface of the silicon substrate, at step  430 . As discussed herein, the second layer may be comprised of multiple layers deposited on the first layer, or first layers, on the silicon substrate as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. 
     At step  440 , the method  400  includes creating at least one TSV that extends from the second layer, or second layers, through the first layer, or first layers, and into at least a portion of the silicon substrate. The method  400  may include forming a plurality of TSVs, which may be formed in a rectangular array positioned adjacent to a side of the silicon substrate. The method  400  may include forming interconnects within the second layer, or second layers, as discussed herein, at step  446 . The method  400  may include applying an oxide layer and applying a tantalum layer to the at least one TSV, at optional step  445 . At step  450 , the method  400  includes filling the at least one TSV, or the plurality of TSVs, with copper, or the like. 
     The method  400  includes forming at least a third layer on the second layer, the third layer including at least one pad that is configured to connect to a semiconductor device and forming interconnections between the at least one copper filled TSV and the at least one pad, at step  460 . The third layer may be comprised of multiple layers deposited on second layer, or second layers, as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure. The method  400  includes removing silicon from the second or bottom surface of the silicon substrate to expose a portion of the at least one copper, or the like, filled TSV, or a portion of the plurality of copper, or the like, filled TSVs, at step  470 . The method  400  may include removing silicon to expose the at least one test pad, at optional step  475 . The method  400  may include removing the oxide layer from the exposed portion of the at least one copper, or the like, filled TSV, at optional step  480 . The method  400  may include applying a probe to the tantalum layer of the exposed portion of the at least one copper, or the like, filled TSV, at optional step  485 . The method  400  may include removing the tantalum layer of the exposed portion of the at least one copper, or the like, filled TSV, at optional step  490 . 
     Although this disclosure has been described in terms of certain embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments that do not provide all of the features and advantages set forth herein, are also within the scope of this disclosure. The disclosure may encompass other embodiments not expressly shown or described herein. Accordingly, the scope of the present disclosure is defined only by reference to the appended claims and equivalents thereof.