Patent Publication Number: US-2023162807-A1

Title: Non-volatile memory device and programming method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0162599, filed on Nov. 23, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. 
     BACKGROUND 
     1. Field 
     The disclosure relates generally to a non-volatile memory device, and more particularly, to a non-volatile memory device of which boosting efficiency is increased by using a center dummy line transistor in a multi-stack structure, and a programming method thereof. 
     2. Description of Related Art 
     A semiconductor memory device is used to store data, and is classified into a volatile memory device and a non-volatile memory device. As an example of the non-volatile memory device, a flash memory device may be used in smartphones, personal computers (PCs), solid-state drives (SSDs), universal serial bus (USB) memory, digital cameras, mobile phones, tablet PCs, and other devices. 
     In a three-dimensional (3D) NAND flash memory having a multi-stack structure, dummy word lines exist between the multi-stacks. The dummy word line has not been used as a memory cell storing data due to process reasons or the like. Although the dummy word line occupies space in a flash memory, it is difficult to use the dummy word line to store data, and thus, the dummy word line is considered a wasted resource. There is a need to develop the performance of a flash memory by using a dummy word line 
     As the number of highly-integrated vertical flash memory devices increases, a channel of a flash memory has lengthened. As the channel lengthens, the number of word lines involved in boosting increases, and thus, boosting efficiency is reduced. 
     SUMMARY 
     Provided are a memory device in which boosting efficiency is increased by using a center dummy line transistor, and a programming method thereof. 
     Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments. 
     According to an aspect of an example embodiment, An operating method of a non-volatile memory device that includes a plurality of cell strings each including a first stack and a second stack adjacent to the first stack, may include performing a first program operation during a time period in which a plurality of program loops are performed, by applying a program voltage including a first plurality of voltage levels to a select word line connected to the first stack of each of the plurality of cell strings, applying, during the time period, second voltages including a second plurality of voltage levels to a non-select word line connected to the first stack of each of the plurality of cell strings, and maintaining, during the time period, a third voltage at a first level, the third voltage applied to a non-select word line connected to the second stack of each of the plurality of cell strings. 
     According to an aspect of an example embodiment, an operating method of a non-volatile memory device including a plurality of cell strings connected to a plurality of bit lines, where the plurality of cell strings include a plurality of string select transistors respectively connected to the plurality of bit lines, may include applying a first voltage including a first level to a first bit line and a second bit line from among the plurality of bit lines during a first time period, applying a second voltage including a second level to the first bit line during a second time period subsequent to the first time period, turning on first string select transistors, from among the plurality of string select transistors, included in a cell string connected to the first bit line during the second time period, turning off second string select transistors, from among the plurality of string select transistors, included in a cell string connected to the second bit line during the second time period, and maintaining a third voltage applied to the second bit line at the second level during the second time period. 
     According to an aspect of an example embodiment, a non-volatile memory device may include a memory cell array including a plurality of cell strings, a voltage generator configured to generate a voltage applied to a bit line connected to the plurality of cell strings, and a control circuit configured to program data received from the outside to the memory cell array. The control circuit may be configured to control an electrical connection between a select stack including a select word line and a stack adjacent to the select stack by controlling at least one transistor adjacent to a boundary between the select stack and the stack adjacent to the select stack, and controlling a voltage applied to a non-select word line connected to the stack adjacent to the select stack to maintain a first level during a time period in which a plurality of program loops for the memory cell array are performed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: 
         FIG.  1    is a flowchart of a programming method of a non-volatile memory device, according to an example embodiment; 
         FIG.  2    is a block diagram of a memory system according to an example embodiment; 
         FIG.  3    is a block diagram of the memory device of  FIG.  2    according to an example embodiment; 
         FIG.  4    is a perspective view illustrating the memory block of  FIG.  3    according to an example embodiment; 
         FIG.  5    is an equivalent circuit diagram of the memory block of  FIG.  3    according to an example embodiment; 
         FIG.  6    is a diagram illustrating an example of a program bias condition of the memory block of  FIG.  5    according to an example embodiment; 
         FIG.  7    is a circuit diagram illustrating a structure of a memory cell array having one center dummy line, according to an example embodiment; 
         FIG.  8    is a circuit diagram illustrating a structure of a memory cell array having two center dummy lines, according to an example embodiment; 
         FIG.  9    is a diagram illustrating a two-stack cell string according to an example embodiment; 
         FIG.  10    is a diagram illustrating application of a program prohibit precharge voltage to a bit line according to an example embodiment; 
         FIGS.  11 A,  11 B, and  11 C  are diagrams illustrating operations of a cell string when a first stack is programmed, according to an example embodiment; 
         FIG.  12    is a diagram illustrating an operation of a cell string when a second stack is programmed according to an example embodiment; 
         FIGS.  13 A and  13 B  are a diagram illustrating a timing of voltage levels according to an example embodiment; 
         FIGS.  14 A,  14 B, and  14 C  are diagrams illustrating an operation of a three-stack cell string according to an example embodiment; and 
         FIG.  15    is a diagram illustrating a BV NOT AND (NAND) structure according to an example embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Hereinafter, various embodiments of the disclosure are described with reference to the accompanying drawings. 
       FIG.  1    is a flowchart of a programming method of a non-volatile memory device, according to an example embodiment. The programming method of the non-volatile memory device may include a plurality of operations S 100  to S 300 . In  FIG.  1   , a plurality of cell strings may include a select cell string and at least one non-select cell string, as described with reference to  FIGS.  11 A to  11 C . The plurality of cell strings may be respectively arranged between a source line and a plurality of bit lines including a program enable bit line and at least one program prohibit bit line. Each of the cell strings may include a select stack including a select word line and non-select stacks not including a select word line. 
     The plurality of cell strings may be classified into two stacks as described with reference to  FIGS.  9  to  12   , and may be classified into three stacks as described with reference to  FIGS.  14 A to  14 C . 
     In operation S 100 , during a time period in which a plurality of program loops are performed, a program operation may be performed by applying a program voltage having a plurality of voltage levels to a select word line connected to a select stack included in each of a plurality of cell strings. The plurality of voltage levels are voltage levels of a program voltage applied to a select word line as the program loops progress by incremental step pulse programming (ISPP), and may gradually increase. 
     In operation S 200 , during the time period, voltages having a plurality of voltage levels may be applied to a non-select word line connected to the select stack included in each of the plurality of cell strings. A pass voltage applied to the non-select word line may also be gradually increased as the program voltage increases so as to reduce a program voltage disturbance. 
     In operation S 300 , during the time period, a voltage applied to a non-select word line connected to a non-select stack included in each of the plurality of cell strings is maintained at a constant voltage level. By maintaining the voltage level constant, an amount of current consumed by the non-select stack may be reduced. 
     As a degree of integration of a flash memory increases, the number of stacks in which the flash memory is vertically stacked may increase, and a channel length of a cell string may increase. As the channel length increases, the number of word lines involved in boosting the channel increases, and pass voltage disturbance, which is a disturbance to memory cells connected to the non-select word line during programming, may increase. In addition, as the channel length increases, boosting efficiency decreases, and a program voltage disturbance, which is a disturbance to memory cells of the non-select cell string connected to the select word line, may increase. 
     The programming method of the non-volatile memory device according to embodiments of the disclosure may further include controlling an electrical connection between stacks of each of the cell strings by using a center dummy line transistor disposed on a boundary layer of the stacks. Through this operation, the center dummy line transistor functions similarly to a string select transistor, thereby reducing the number of word lines involved in boosting. Accordingly, boosting efficiency may be increased, pass voltage disturbance may be reduced, and a word line voltage of the non-select stack may be maintained constant from the start of a program to a recovery period in which the word line voltage is initialized. Therefore, the amount of current consumed by the non-select stack may be reduced. 
       FIG.  2    is a block diagram of a memory system according to an example embodiment. Referring to  FIG.  2   , the memory system  100  may include a memory controller  110  and at least one memory device  120 . The memory device  120  shown in  FIG.  2    may be a non-volatile memory device, such as a flash memory device. The memory system  100  may include a data storage medium, such as a USB memory, a memory card, and a solid-state drive (SSD). 
     The memory device  120  may perform an erase, program, or read operation under the control by the memory controller  110 . The memory device  120  may receive a command CMD and an address ADDR from the memory device  120  via an input/output line and transmit and receive data DATA for the program operation or the read operation to and from the memory controller  110 . In addition, the memory device  120  may receive a control signal CTRL via a control line. The memory device  120  may include a memory cell array  121  and a control circuit  122 . 
     The memory cell array  121  may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. Hereinafter, embodiments of the disclosure are described by taking a case in which the plurality of memory cells are NAND flash memory cells as an example. The memory cell array  121  may include a three-dimensional memory cell array including a plurality of cell strings, which is described below with reference to  FIGS.  4  and  5   . 
     The control circuit  122  may perform an operation of initializing channels for the plurality of cell strings in the memory cell array  121  and perform a program operation on a select memory cell from among the plurality of memory cells. 
       FIG.  3    is a block diagram of the memory device  120  of  FIG.  2    according to an example embodiment. Referring to  FIG.  3   , the memory device  120  include the memory cell array  121 , a row decoder  124 , the control circuit  122 , a page buffer  125 , an input/output (I/O) circuit  126 , and a voltage generator  123 . 
     The memory cell array  121  may be connected to word lines WL, string select lines SSL, ground select lines GSL, and bit lines BL. The memory cell array  121  may be connected to the row decoder  124  via the word lines WL, the string select lines SSL, and the ground select lines GSL, and may be connected to the page buffer  125  via the bit lines BL. The memory cell array  121  may include a plurality of memory blocks BLK 1  to BLKn. 
     Each of the memory blocks BLK 1  to BLKn may include a plurality of memory cells and a plurality of select transistors. The memory cells may be connected to the word lines WL, and the select transistors may be connected to the string select lines SSL or the ground select lines GSL. The memory cells of each of the memory blocks BLK 1  to BLKn may include single level cells storing 1-bit data and multi-level cells storing M-bit data (M is an integer greater than or equal to 2). 
     The row decoder  124  may select one of the plurality of memory blocks BLK 1  to BLKn of the memory cell array  121 , select one of the word lines WL of the selected memory block, and select one of the plurality of string select lines SSL. 
     The control circuit  122  may output various internal control signals for performing the program, read, and erase operation on the memory cell array  121 , based on a command CMD, an address ADDR, and a control signal CTRL received from the memory controller  110 . The control circuit  122  may provide a row address R_ADDR to the row decoder  124 , provide a column address to the I/O circuit  126 , and provide a voltage control signal CTRL_VOL to the voltage generator  123 . 
     The control circuit  122  may precharge channels of the plurality of cell strings with a precharge voltage of the bit lines via string select transistors before the select memory cell is programmed. 
     The page buffer  125  may function as a write driver or a sense amplifier according to an operation mode thereof. During the read operation, the page buffer  125  may sense a bit line of a selected memory cell under the control by the control circuit  122 . The sensed data may be stored in latches provided in the page buffer  125 . The page buffer  125  may transfer the data stored in the latches to the I/O circuit  126  via a data line DL under the control by the control circuit  122 . 
     The I/O circuit  126  may temporarily store the command CMD, the address ADDR, and the data DATA received from the outside of the non-volatile memory device  120  via an input/output line I/O. The I/O circuit  126  may temporarily store read data of the non-volatile memory device  120  and output the stored read data to the outside via the input/output line I/O at a designated time point. 
     The voltage generator  123  may generate voltages of various types for performing the program, read, and erase operations on the memory cell array  121 , based on the voltage control signal CTRL_VOL. For example, the voltage generator  123  may generate a word line voltage VWL, for example, a program voltage, a read voltage, a pass voltage, an erase voltage, an erase verification voltage, and the like. In addition, the voltage generator  123  may generate precharge voltages based on the voltage control signal CTRL_VOL. 
       FIG.  4    is a perspective view illustrating the memory block BLK 1  of  FIG.  3   . Referring to  FIG.  4   , each of memory blocks included in a memory cell array (e.g.,  121  of  FIG.  3   ) may be vertically provided with respect to a substrate SUB. In  FIG.  4   , the memory block includes two select lines GSL and SSL, eight word lines WL 1  to WL 8 , and three bit lines BL 1  to BL 3 . However, the numbers thereof may be more or less than these. 
     A common source line CSL, which has a first conductivity type (e.g., p type), extends in a first direction (e.g., a D 2  direction) on the substrate SUB, and is doped with impurities of a second conductivity type (e.g., n type), may be provided on the substrate SUB. 
     A first memory stack ST 1  may be provided on the substrate SUB. In detail, in an area of the substrate SUB between two adjacent common source lines CSL, a plurality of insulation layers IL each extending in the first direction may be sequentially provided in a third direction (e.g., a D 1  direction), and the plurality of insulation layers IL may be spaced apart by a certain distance in the third direction. For example, the plurality of insulation layers IL may include an insulation material, such as silicon oxide. A plurality of pillars P, which are sequentially arranged in the first direction and provided by etching through the plurality of insulation layers IL in the third direction, may be provided in the area of the substrate SUB between two adjacent common source lines CSL. For example, the plurality of pillars P may be in contact with the substrate SUB via the plurality of insulation layers IL. For example, a surface layer S of each of the pillars P may include a silicon material having a first conductivity type and function as a channel area. An inner layer I of each of the pillars P may include an insulating material such as a silicon oxide or an air gap. 
     A charge storage layer CS may be provided in an area between two adjacent common source lines CSL along exposed surfaces of the insulation layers IL, the pillars P, and the substrate SUB. The charge storage layer CS may include a gate insulation layer (also referred to as “a tunneling insulation layer”), a charge trap layer, and a blocking insulation layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, a gate electrode GE, such as the select lines GSL and SSL and the word lines WL 1  to WL 4 , may be provided on an exposed surface of the charge storage layer CS in an area between the two adjacent common source lines CSL. 
     A second memory stack ST 2 , which is formed in the same manner as the first memory stack ST 1 , may be further provided in the memory block BLK 1  according to the disclosure. Drains or drain contacts DR may be respectively provided on the plurality of pillars P that extend in a second memory stack ST 2 . For example, the drains or drain contacts DR may include a silicon material doped with impurities having the second conductivity type. Bit lines BL 1  to BL 3 , which extend in a second direction (e.g., a D 3  direction) and are spaced apart from each other by a certain distance in the first direction, may be provided on the drains or drain contacts DR. 
       FIG.  5    is an equivalent circuit diagram of the memory block of  FIG.  3    according to an example embodiment. The memory block shown in  FIG.  5    is an example of one of the plurality of memory blocks BLK 1  to BLKn described with reference to  FIG.  3   , and shows a first memory block BLK 1 . The first memory block BLK 1  refers to a three-dimensional block having a three-dimensional structure on a substrate. A plurality of memory cell strings included in the first memory block BLK 1  may be provided in a direction D 1 , perpendicular to the substrate. 
     Referring to  FIG.  5   , the first memory block BLK 1  may include cell strings NS 11  to NS 33 , word lines WL 1  to WL 8 , bit lines BL 1  to BL 3 , ground select lines GSL 1  to GSL 3 , string select lines SSL 1  to SSL 3 , and a common source line CSL. In  FIG.  5   , each of the cell strings NS 11  to NS 33  includes eight memory cells MCs that are respectively connected to the eight word lines WL 1  to WL 8 , but the disclosure is not limited thereto. 
     Each of the cell strings (e.g., NS 11 ) may include a string select transistor SST, the plurality of memory cells MCs, and a ground select transistor GST, which are connected to each other in series. The string select transistor SST may be connected to a corresponding string select line SSL 1 . The plurality of memory cells MCs may be respectively connected to corresponding word lines WL 1  to WL 8 . The ground select transistor GST may be connected to a corresponding ground select line GSL 1 . The string select transistor SST may be connected to the corresponding bit line BL 1 , and the ground select transistor GST may be connected to the common source line CSL. 
     In the cell strings NS 11  to NS 33 , word lines (e.g., WL 1 ) of the same height may be commonly connected, and the ground select lines GSL 1 , GSL 2 , and GSL 3  and the string select lines SSL 1 , SSL 2 , and SSL 3  may be respectively separated from each other. The cell strings NS 11  to NS 33  may include a word line corresponding to a center dummy line from among the plurality of word lines, as shown in  FIG.  7    to be described below. 
       FIG.  6    is a diagram illustrating an example of a program bias condition of the memory block BLK 1  of  FIG.  5    according to an example embodiment. From among the cell strings NS 11  to NS 33  of the first memory block BLK 1 , for convenience, first and third cell strings NS 11  and NS 21  connected to the first bit line BL 1  and second and fourth cell strings NS 12  and NS 22  connected to the second bit line BL 2  are shown in  FIG.  6   . The first to fourth cell strings NS 11 , NS 12 , NS 21 , and NS 22  may include first to fourth memory cells A, B, C, and D, respectively. 
     Referring to  FIG.  6   , the first bit line BL 1  may include a program enable bit line to which a relatively low program enable voltage, for example, a ground voltage GND, is applied, and the second bit line BL 2  may include a program prohibit bit line to which a relatively high program prohibit voltage, for example, a power voltage VDD, is applied. 
     A cell string connected to a string select line to which a string turn-on voltage VSON is applied may be referred to as a select cell string, and a cell string connected to a string select line to which a string turn-off voltage VSOFF is applied may be referred to as a non-select cell string. A select cell string connected to the program enable bit line may include a memory cell to be programmed, and a select cell string connected to the program prohibit bit line may include a memory cell not to be programmed. 
     For example, the first cell string NS 11  may be selected to program the first memory cell A. To allow the first cell string NS 11  to be selected, the string turn-on voltage VSON may be applied to the first string select line SSL 1  connected to the first cell string NS 11 , and the string turn-off voltage VSOFF may be applied to the second string select line SSL 2  connected to the third cell string NS 21 . The string turn-off voltage VSOFF includes a voltage that turns off a string select transistor SST, and may be the ground voltage GND. The string turn-on voltage VSON is a voltage that turns on the string select transistor SST, and may be the power voltage VDD. 
     A turn-off voltage may be applied to the ground select lines GSL 1  and GSL 2 . The ground voltage GND, for example, a voltage of 0 V, may be applied to the source line CSL. A program voltage VPGM (e.g., 18 V) may be applied to a select word line (e.g., WL 3 ), and a pass voltage VPASS (e.g., 8 V) may be applied to non-select word lines (e.g., WL 2  and WL 4 ). 
     In the program bias condition, 18 V may be applied to a gate of the first memory cell A, and a channel voltage may be 0 V. Accordingly, a strong electric field may be provided between the gate and the channel of the first memory cell A, and the first memory cell A may be programmed. Because a channel voltage of the second memory cell B is the power voltage VDD and a strong electric field is provided between a gate and a channel of the second memory cell B, the second memory cell B may not be programmed. Channels of the third and fourth memory cells C and D are in a floating state, and thus, a channel voltage is raised up to a boosting level by the pass voltage VPASS, and the third and fourth memory cells C and D may not be programmed. 
       FIG.  7    is a circuit diagram illustrating a structure of a memory cell array having one center dummy line, according to an example embodiment. For convenience, cell strings STR 1  to STRn connected to one bit line BL and one common source line CSL from among cell strings of a memory block are shown in  FIG.  7   . However, the memory block may have a three-dimensional structure as described with reference to  FIGS.  5  and  6   . Referring to  FIG.  7   , the memory block may include a plurality of cell strings STR 1  to STRn, which are connected to each other between the same bit line BL and the same common source line CSL. The cell strings STR 1  to STRn may include string select transistors SST 1  to SSTn controlled via string select lines SSL 1  to SSLn, memory cells controlled via word lines WL, center dummy line transistors CDT 1  to CDTn controlled via a center dummy line CDL, and ground select transistors GST 1  to GSTn controlled via a ground select line GSL. 
     In  FIG.  7   , the ground select transistors GST 1  to GSTn are connected to the same ground select line GSL. However, a certain number of ground select transistors may be connected to each of a plurality of ground select lines GSL. In an embodiment, as shown in  FIG.  7   , a boundary layer BDL may include one gate line. The gate line corresponds to a center dummy line CDL and may simultaneously control the center dummy line transistors CDT 1  to CDTn connected thereto. In an embodiment, the boundary layer BDL may be disposed between a first stack ST 1  and a second stack ST 2 . For convenience of description, it is shown that the boundary layer BDL is a separate layer disposed between the first stack ST 1  and the second stack ST 2 . However, it may be understood that the boundary layer BDL is included in the first stack ST 1  or the second stack ST 2 . 
       FIG.  8    is a circuit diagram illustrating a structure of a memory cell array having two center dummy lines, according to an example embodiment. In  FIG.  8   , two center dummy lines are provided, and descriptions already provided above with reference to  FIG.  7    are omitted. The cell strings STR 1  to STRn may include first center dummy line transistors CDT 11  to CDT 1   n  controlled via a first center dummy line CDL 1  and second center dummy line transistors CDT 21  to CDT 2   n  controlled via a second center dummy line CDL 2 . In an embodiment, as shown in  FIG.  8   , the boundary layer BDL may include two gate lines. The two gate lines correspond to the first center dummy line CDL 1  and the second center dummy line CDL 2  and may control the first center dummy line transistors CDT 11  to CDT 1   n  and the second center dummy line transistors CDT 21  to CDT 2   n  respectively connected thereto. The first center dummy line CDL 1  and the second center dummy line CDL 2  may receive different voltages from each other. Accordingly, the first center dummy line transistors CDT 11  to CDT 1   n  and the second center dummy line transistors CDT 21  to CDT 2   n  may be controlled differently from each other. In addition, the first center dummy line CDL 1  and the second center dummy line CDL 2  may receive the same voltage so that the first center dummy line transistors CDT 11  to CDT 1   n  and the second center dummy line transistors CDT 21  to CDT 2   n  may be controlled the same as each other. 
     The boundary layer BDL may include at least three gate lines. The at least three gate lines correspond to center dummy lines, and center dummy line transistors connected thereto may be controlled via the respective gate lines. In an embodiment, the boundary layer BDL may be disposed between the first stack ST 1  and the second stack ST 2 . For convenience of description, it is shown that the boundary layer BDL is a separate layer disposed between the first stack ST 1  and the second stack ST 2 . However, it may be understood that a portion of the boundary layer BDL is included in the first stack ST 1  or the second stack ST 2 . 
       FIG.  9    is a diagram illustrating a two-stack cell string according to an example embodiment. In  FIG.  9   , for convenience, one cell string CST connected to one bit line BL and one common source line CSL from among cell strings of a memory block is shown. However, the memory block may have a three-dimensional structure as described with reference to  FIGS.  5    and  6 . Referring to  FIG.  9   , the cell string CST may include a string select transistor controlled via a string select line SSL, memory cells respectively controlled via word lines WL, center dummy line transistors respectively controlled via center dummy lines CDL 1  and CDL 2 , a ground select transistor controlled via the ground select line GSL, a drain electrode DRAIN connected to a bit line BL, and a channel area CHANNEL connecting transistor channels of the cell string CST to each other. In an embodiment, as shown in  FIG.  9   , the cell string CST may be classified into a first stack STACK 1  and a second stack STACK 2  with the center dummy lines CDL 1  and CDL 2  as a boundary. 
     The bit line BL may be a program enable bit line or a program prohibit bit line. When the bit line BL is a program enable bit line, a program enable voltage, e.g., the ground voltage GND, may be applied during a program operation. When the bit line BL is a program prohibit bit line, a program prohibit voltage, e.g., the power voltage VDD, may be applied during a program operation. 
     The drain electrode DRAIN is an electrode that electrically connects the bit line BL and the channel area CHANNEL to each other, and may be metal, polysilicon which is doped, and the like. 
     The string select line SSL is a gate line of a string select transistor, and different voltages may be applied thereto according to a select cell string and a non-select cell string during a program operation. A string turn-on voltage (VSON of  FIG.  11 A ) greater than or equal to a threshold voltage Vth of each string select line SSL of the select cell string may be applied to the string select line SSL. A string turn-off voltage (VSOFF of  FIG.  11 C ), for example, the ground voltage GND, may be applied to a string select line SSL of the non-select cell string. 
     The word line WL is a gate line of the memory cells, and a pass voltage (e.g., VPASS of  FIG.  11 A ), a constant pass voltage (e.g., S_VPASS of  FIG.  11 A ), or a program voltage (e.g., PGM of  FIG.  11 A ) may be applied to the word line WL. 
     The center dummy lines CDL 1  and CDL 2  are gate lines of the center dummy line transistor, and a turn-on voltage greater than or equal to a threshold voltage Vth of each of the center dummy lines CDL 1  and CDL 2 , for example, a center dummy voltage (VCD of  FIG.  11 A ) or a turn-off voltage, for example, the ground voltage (GND of  FIG.  12   ) may be applied to the center dummy lines CDL 1  and CDL 2 . 
     The ground select line GSL is a gate line of the ground select transistor, and a turn-on voltage greater than or equal to the threshold voltage Vth of each ground select line GSL, (e.g., the power voltage VDD) or a turn-off voltage (e.g., the ground voltage GND) may be applied to the ground select line GSL. 
       FIG.  10    is a diagram illustrating application of a program prohibit precharge voltage to a bit line according to an example embodiment.  FIG.  10    may correspond to a first bit line setup period BS 1  of  FIGS.  13 A and  13 B . For example, a cell string  1 P_CST of  FIG.  10    may correspond to the first to fourth cell strings NS 11 , NS 12 , NS 21 , and NS 22  of  FIG.  6    in the first bit line setup period BS 1 . Referring to  FIG.  10   , a program prohibit precharge voltage, e.g., the power voltage VDD, may be applied to a bit line. The string turn-on voltage VSON may be applied to both string select lines SSL of the select cell string and the non-select cell string, and the string select transistor may be turned on. A constant pass voltage S-VPASS may be applied to a word line WL of the second stack STACK 2 , and memory cells of the second stack STACK 2  may be turned on. 
     The ground voltage GND may be applied to the center dummy lines CDL 1  and CDL 2 , and the center dummy line transistors may be turned off A program prohibit precharge voltage VDD applied to the bit line BL may be applied to a channel of the second stack STACK 2  via the drain electrode DRAIN. By applying the program prohibit precharge voltage to all channels of the second stack STACK 2  of the select cell string and the non-select cell string in the first bit line setup period BS 1 , a channel voltage of the second stack STACK 2  of the non-select cell string may be maintained at the power voltage VDD as described below with reference to  FIG.  11 C . 
       FIGS.  11 A,  11 B, and  11 C  are diagrams illustrating operations of a cell string when a first stack is programmed, according to an example embodiment.  FIG.  11 A  may correspond to a second bit line setup period BS 2  of  FIG.  13 A . For example, a cell string  1 P_CST 1  of  FIG.  11 A  may correspond to the first cell string NS 11  of  FIG.  6    in the second bit line setup period BS 2 . A program enable bit line voltage, e.g., the ground voltage GND, may be applied to a bit line BL connected to the cell string  1 P_CST 1 . Referring to  FIG.  11 A , the string turn-on voltage VSON may be applied to the string select line SSL of the select cell string, and the string select transistor may be turned on. In some embodiments,  FIG.  11 A  may show a program execution period PGMEXE of  FIG.  13 A . 
     Referring to  FIG.  11 A , because the first stack STACK 1  includes a select word line WL to be programmed, the first stack STACK 1  may be referred to as a select stack, and because the second stack STACK 2  does not include a select word line WL, the second stack STACK 2  may be referred to as a non-select stack. The constant pass voltage S_VPASS may be applied to a non-select word line WL of the second stack STACK 2  from a time point at which a program loop is started to a time point at which all program loops end, and the memory cells of the second stack STACK 2  may be turned on. A center dummy voltage VCD may be applied to the center dummy lines CDL 1  and CDL 2 , and the center dummy line transistors may be turned on. The center dummy voltage may be a voltage satisfying Equation (1). 
         VGS 1= VG 1− VS 1&gt; V TH1  (1)
 
     In Equation (1), VGS 1  indicates a difference between a gate voltage and a source voltage of the center dummy line transistor in a select cell string connected to a program enable bit line, VG indicates the gate voltage of the center dummy line transistor, VS indicates the source voltage of the center dummy line transistor, and VTH 1  indicates a threshold voltage of the center dummy line transistor. For example, when VG 1  is the center dummy voltage VCD, and VS 1  is the ground voltage GND, Equation (1) may be expressed as VGS 1 =VCD−0&gt;VTH 1 . 
     The pass voltage VPASS may be applied to a non-select word line WL of the first stack STACK 1 , and memory cells connected to the non-select word line WL of the first stack STACK 1  may be turned on. A program voltage PGM may be applied to the select word line WL of the first stack STACK 1 , and a memory cell connected to the select word line WL may be programmed. The ground voltage GND may be applied to a ground select line GSL so that the ground select transistor is turned off. 
     Because all transistors of the first stack STACK 1  and the second stack STACK 2  are turned on, the ground voltage GND applied to the bit line BL may be applied to channels of the first stack STACK 1  and the second stack STACK 2  via the drain electrode DRAIN. 
       FIG.  11 B  may correspond to the second bit line setup period BS 2  of  FIG.  13 A . For example, the cell string  1 P_CST 2  of  FIG.  11 B  may correspond to the second cell string NS 12  of  FIG.  6    in the second bit line setup period BS 2 . The program prohibit bit line voltage, e.g., the power voltage VDD, may be applied to the bit line BL connected to the cell string  1 P_CST 2 . In some embodiments,  FIG.  11 B  may show the program execution period PGMEXE of  FIG.  13 A . Referring to  FIG.  11 B , the string turn-on voltage VSON may be applied to the string select line SSL of the select cell string, and the string select transistor may be turned on. A constant pass voltage S-VPASS may be applied to the word line WL of the second stack STACK 2 , and memory cells of the second stack STACK 2  may be turned on. 
     Because transistors disposed over the center dummy line transistor connected to the second center dummy line CDL 2  are turned on, the power voltage VDD applied to the bit line BL may be applied to the channel of the second center dummy line CDL 2  via the drain electrode DRAIN. Accordingly, the power voltage VDD may be applied to source terminals of the center dummy line transistors connected to the second center dummy line CDL 2 , and the center dummy line transistors may be turned off because a difference between the gate voltage and the source voltage of the center dummy line transistors connected to the second center dummy line CDL 2  is less than a threshold voltage VTH 2 . In other words, the center dummy voltage may be a voltage satisfying Equation (2). 
         VGS 2= VG 2− VS 2&lt; V TH2  (2)
 
     In Equation (2), VGS 2  indicates a difference between a gate voltage and a source voltage of the center dummy line transistor in a select cell string connected to the program prohibit bit line, VG 2  indicates the gate voltage of the center dummy line transistor, VS 2  indicates the source voltage of the center dummy line transistor, and VTH 2  indicates a threshold voltage of the center dummy line transistor. For example, when VG 2  is the center dummy voltage VCD, and VS 2  is the power voltage VDD, Equation (2) may be expressed as VGS 2 =VCD−VDD&lt;VTH 2 . 
     Referring to  FIG.  5   , a select cell string connected to the program enable bit line and a select cell string connected to the program prohibit bit line share a word line WL in the same memory block, and thus, VG 1  of Equation (1) and VG 2  of Equation (2) may have the same value VG. Accordingly, Equation (1) and Equation (2) may be expressed as Equation (3). 
         V TH1+ VS 1&lt; VG&lt;V TH2+ VS 2  (3)
 
     For example, when VG 2  is the center dummy voltage VCD, VS 1  is the ground voltage GND, and VS 2  is the power voltage VDD, Equation (3) may be expressed as VTH 1 &lt;VCD&lt;VDD+VTH 2 . When a threshold voltage level VTH 1  of the center dummy line transistor of the select cell string connected to the program enable bit line and a threshold voltage level VTH 2  of the center dummy line transistor of the select cell string connected to the program prohibit bit line are close to VTH, Equation (3) may be expressed as VTH&lt;VCD&lt;VDD+VTH. 
     The ground voltage GND may be applied to the ground select line GSL of the first stack STACK 1  so that the ground select transistor is turned off. The first stack STACK 1  may be floated by turning off the center dummy line transistor and the ground select transistor. Accordingly, a channel of the first stack STACK 1  may be boosted while a program operation is performed. Accordingly, a pass voltage VPASS may be applied to the non-select word line WL of the first stack STACK 1 , and even when the program voltage PGM is applied to the select word line WL of the first stack STACK 1 , the memory cell of the first stack STACK 1  may not be programmed. 
     Because the channel of the first stack STACK 1  is boosted, even when the center dummy voltage VCD is applied to the first center dummy line CDL 1  of the first stack STACK 1 , the difference between the gate voltage and the source voltage is less than the threshold voltage VTH, and thus, the center dummy line transistors connected to the first center dummy line CDL 1  may be turned off. 
       FIG.  11 C  may correspond to the second bit line setup period BS 2  of  FIG.  13 A . For example, cell strings  1 P_CST 3 / 1 P_CST 4  of  FIG.  11 C  may correspond to the third and fourth cell strings NS 21  and NS 22  of  FIG.  6    in the second bit line setup period BS 2 . For example, when the program enable bit line voltage, e.g., the ground voltage GND, is applied to the bit line BL connected to the cell string  1 P_CST 3 , the cell string  1 P_CST 3  may correspond to the third cell string NS 21  of  FIG.  6   . Alternatively, when the program prohibit bit line voltage, e.g., the power voltage VDD, is applied to the bit line BL connected to the cell string  1 P_CST 4 , the cell string  1 P_CST 4  may correspond to the fourth cell string NS 22  of  FIG.  6   . In some embodiments,  FIG.  11 C  may show the program execution period PGMEXE of  FIG.  13 A . 
     Referring to  FIGS.  10  and  11 C , after the power voltage VDD is applied to the channel of the second stack STACK 2 , the string turn-off voltage VSOFF may be applied to the string select line SSL, and the string select transistor may be turned off. The constant pass voltage S-VPASS may be applied to a word line WL of the second stack STACK 2 , and memory cells of the second stack STACK 2  may be turned on. 
     Because the transistors disposed over the center dummy line transistors of the second stack STACK 2  are turned on, the power voltage VDD applied to the bit line BL may be applied to the channel of the second stack STACK 2  via the drain electrode DRAIN, and the power voltage VDD may be applied to the source terminal of the center dummy line transistor. The center dummy voltage VCD may be applied to the center dummy lines CDL 1  and CDL 2 , but as shown in  FIG.  11 B , the center dummy line transistors may be turned off because the difference between the gate voltage and the source voltage is less than the threshold voltage VTH as described with reference to  FIG.  11 B . 
     The ground voltage GND may be applied to the ground select line GSL of the first stack STACK 1  so that the ground select transistor is turned off. The first stack STACK 1  may be floated by turning off the center dummy line transistor and the ground select transistor. Accordingly, a channel of the first stack STACK 1  may be boosted while a program operation is performed. Accordingly, a pass voltage VPASS may be applied to the non-select word line WL of the first stack STACK 1 , and even when the program voltage PGM is applied to the select word line WL of the first stack STACK 1 , the memory cell of the first stack STACK 1  may not be programmed. 
     A program voltage PGM applied to a select word line WL as program loops progress by ISPP may gradually increase. A pass voltage applied to the non-select word line WL may also be gradually increased to reduce program voltage disturbance as the program voltage increases. 
     In the related art, a pass voltage applied to a non-select word line WL is gradually increased as a program loop progresses, without distinguishing between a select stack and a non-select stack. 
     However, in the disclosure, referring to  FIGS.  11 B and  11 C , a non-select stack channel may be disconnected from a select stack by the center dummy line transistor. Accordingly, in the non-select stack, it is not necessary to increase the pass voltage as a program is executed, and thus, the pass voltage may not be changed in accordance with a change of program voltage PGM. Accordingly, the constant pass voltage S_VPASS may be applied to the word line WL of the non-select stack from the time point at which the program loop is started to a time point at which all program loops end. Because it is not necessary to increase a voltage of the word line WL of the non-select stack in accordance with ISPP, pass voltage disturbance may be reduced during a program operation, and an amount of current consumed by the non-select stack may be reduced. 
       FIG.  12    is a diagram illustrating an operation of a cell string when a second stack is programmed according to an example embodiment.  FIG.  12    may correspond to the second bit line setup period BS 2  of  FIG.  13 B . In some embodiments,  FIG.  12    may show the program execution period PGMEXE of  FIG.  13 B . For example, a cell string  2 P_CST 1  of  FIG.  12    may correspond to the first cell string NS 11  of  FIG.  6   . However, unlike the cell strings  1 P_CST 1 ,  1 P_CST 2 ,  1 P_CST 3 , and  1 P_CST 4  of  FIGS.  11 A to  11 C , the select word line WL to be programmed may be included in the second stack STACK 2  of the cell string  2 P_CST 1  of  FIG.  12   . Therefore, the second stack STACK 2  is a select stack, and the first stack STACK 1  may be referred to as a non-select stack because the first stack STACK 1  does not include the select word line WL. 
     In addition, the second bit line setup period BS 2  for the second to fourth cell strings NS 12 , NS 21 , and NS 22  may be described through  FIGS.  11 B and  11 C  except that a selected word line is included in the second stack STACK 2  in the second bit line setup period BS 2 . 
     In the second bit line setup period BS 2  of  FIG.  13 B , a program enable voltage, e.g., the ground voltage GND, may be applied to the program enable bit line. The ground voltage GND may be applied to the channel CHANNEL of the second stack STACK 2  via the drain electrode DRAIN from the program enable bit line BL. A program operation for the second stack STACK 2  may be performed by applying a program voltage PGM to the select word line WL of the second stack STACK 2  and applying a pass voltage VPASS to the other word lines WL. The ground voltage GND may be applied to the center dummy lines CDL 1  and CDL 2 , and the center dummy transistors may be turned off. Because the word lines WL of the non-select stack are not involved in channel boosting, the constant pass voltage S_VPASS may be applied to the word lines WL of the non-select stack. The ground voltage GND may be applied to a ground select line GSL so that the ground select transistor is turned off. 
       FIGS.  13 A and  13 B  are a diagram illustrating a timing of voltage levels according to an example embodiment.  FIG.  13 A  may be a timing diagram in a case where the first stack STACK 1  is programmed, and  FIG.  13 B  may be a timing diagram in a case where the second stack STACK 2  is programmed.  FIGS.  13 A and  13 B  may be timing diagrams of voltage levels during three program loops (1 st  loop, 2 nd  loop, and 3 rd  loop). Each of the loops may include a bit line setup period BL SETUP, a program execution period PGMEXE, and a verification period VFY. The bit line setup period BL SETUP may be classified into a first bit line setup period BS  1  and a second bit line setup period BS  2 . 
       FIG.  13 A  may be described with reference to  FIGS.  10  to  11 C . During the first bit line setup period BS  1 , the string turn-on voltage VSON may be applied to the string select lines SSL of the non-select cell string and the select cell string so that the respective string select transistors are turned on. A program prohibit precharge voltage, e.g., the power voltage VDD, may be applied to the program prohibit bit line BL and the program enable bit line BL. The ground voltage GND may be applied to the center dummy line CDL, and the center dummy line transistors may be turned off. The constant pass voltage S_VPASS may be applied to the word line WL of the second stack STACK 2 , which is a non-select stack, and the constant voltage level may be maintained until the third program loop ends. The constant voltage level may be a read voltage VREAD or a pass voltage VPASS that is a voltage level of the non-select word line WL of a select stack. 
     The ground voltage GND may be applied to the string select line SSL of the non-select cell string during the second bit line setup period BS  2 , and the string select transistor may be turned off so that the channel of the non-select cell string may be maintained at the power voltage VDD. A voltage applied to the program enable bit line may be reduced to the ground voltage GND by discharging the program prohibit precharge voltage. The center dummy voltage VCD may be applied to the center dummy line so that the center dummy line transistor of the select cell string connected to the program enable bit line BL is turned on. In addition, the center dummy voltage VCD may be applied to the center dummy line so that the center dummy line transistors of the non-select cell string and the select cell string connected to the program prohibit bit line BL may be maintained in a turn-off state. 
     In the program execution period PGMEXE, a memory cell may be programmed by a tunneling phenomenon due to a difference between a channel voltage and the program voltage PGM in the memory cell connected to the select word line WL of the first stack STACK 1 , which is a select stack of a select cell string connected to the program enable bit line BL. While the memory cell is programmed, a voltage of the word line WL of the second stack STACK 2 , which is a non-select stack, may be maintained constant, and a pass voltage may not be gradually increased. Therefore, pass voltage disturbance may be reduced. 
     In the verification period VFY, a verification operation may be performed on a memory cell programmed during the program execution period PGMEXE. The read voltage VREAD may be applied to the string select line SSL of the select cell string and the center dummy line CDL so that transistors respectively connected to the lines are turned on. A precharge voltage may be applied to the program enable bit line BL and the program prohibit bit line BL during the verification period. 
     A recovery operation of initializing voltages of the word line WL at a time point at which a program loop ends may be performed. At a time point at which all program loops end, a voltage of the word line WL of the non-select stack may also be initialized to the ground voltage GND from the constant pass voltage S_VPASS. 
       FIG.  13 B  may be described with reference to  FIGS.  10  and  12   . Descriptions already provided above with reference to  FIG.  13 A  are omitted. The ground voltage GND may be applied to the center dummy line so that the center dummy transistors of the select cell string and the non-select cell string may be maintained in a turn-off state during the bit line setup period BL SETUP and the program execution period PGMEXE. The constant pass voltage S_VPASS may be applied to the word line WL of the first stack STACK 1 , which is a non-select stack, and the constant voltage level may be maintained until the third program loop ends. 
     In the program execution period PGMEXE, a memory cell may be programmed by a tunneling phenomenon due to a difference between a channel voltage and the program voltage PGM in the memory cell connected to the select word line WL of the second stack STACK 2 , which is a select stack of a select cell string connected to the program enable bit line BL. While the memory cell is programmed, a voltage of the word line WL of the first stack STACK 1 , which is a non-select stack, may be maintained constant, and a pass voltage may not be gradually increased. Therefore, pass voltage disturbance may be reduced. 
       FIGS.  14 A,  14 B, and  14 C  are diagrams illustrating an operation of a three-stack cell string according to an example embodiment. Cell strings  3 P_STR 1 ,  2 P_STR 1 , and  1 P_STR 1  of  FIGS.  14 A,  14 B, and  14 C  may correspond to the first cell string NS 11  of  FIG.  6   . In addition, the second to fourth cell strings NS 12 , NS 21 , and NS 22  of  FIG.  6    may be described through  FIGS.  11 B and  11 C  except that the number of stacks is three. In  FIG.  14 A , the select cell string  3 P_CST 1  connected to the program enable bit line BL when a third stack STACK 3  is programmed in the three-stack cell string may be shown. Because the third stack STACK 3  includes the select word line WL to be programmed, the third stack STACK 3  may be referred to as a select stack, and because the first stack STACK 1  and the second stack STACK 2  do not include the select word line WL, the first stack STACK 1  and the second stack STACK 2  may be referred to as non-select stacks. During the program execution period PGMEXE, a program enable voltage, e.g., the ground voltage GND, may be applied to the program enable bit line BL. The ground voltage GND may be applied to the channel CHANNEL of the third stack STACK 3  from the program enable bit line BL via the drain electrode DRAIN. A program operation for the third stack STACK 3  may be performed by applying the program voltage PGM to the select word line WL of the third stack STACK 3  and applying the pass voltage VPASS to the other word lines WL. The ground voltage GND may be applied to the first to fourth center dummy lines CDL 1  to CDL 4 , and the center dummy line transistors may be turned off. Because the word lines WL of the non-select stack are not involved in channel boosting, the constant pass voltage S_VPASS may be applied to the word lines WL of the non-select stack. The ground voltage GND may be applied to a ground select line GSL so that the ground select transistor is turned off. 
     In  FIG.  14 B , the select cell string  2 P_CST 1  connected to the program enable bit line BL when the second stack STACK 2  is programmed in the three-stack cell string may be shown. Referring to  FIG.  14 B , because the second stack STACK 2  includes the select word line WL to be programmed, the second stack STACK 2  may be referred to as a select stack, and because the first stack STACK 1  and the third stack STACK 3  do not include the select word line WL, the first stack STACK 1  and the third stack STACK 3  may be referred to as non-select stacks. Because the word lines WL of the non-select stack are not involved in channel boosting, the constant pass voltage S_VPASS may be applied to the word lines WL of the non-select stack, and the memory cells connected to the non-select word line WL may be turned on. The center dummy voltage VCD may be applied to center dummy lines CDL 3  and CDL 4 , which are adjacent to the boundary in a direction to the bit line BL of the select stack, and the center dummy transistors may be turned on. On the other hand, the ground voltage GND may be applied to the center dummy lines CDL 1  and CDL 2 , which are adjacent to the boundary in a direction to the common source line of the select stack, and the center dummy transistors may be turned off. 
     In  FIG.  14 C , the select cell string  1 P_CST 1  connected to the program enable bit line BL when the first stack STACK 1  is programmed in the three-stack cell string may be shown. Referring to  FIG.  14 C , because the first stack STACK 1  includes the select word line WL to be programmed, the first stack STACK 1  may be referred to as a select stack, and because the second stack STACK 2  and the third stack STACK 3  do not include the select word line WL, the second stack STACK 2  and the third stack STACK 3  may be referred to as non-select stacks. Because the word lines WL of the non-select stack are not involved in channel boosting, the constant pass voltage S_VPASS may be applied to the word lines WL of the non-select stack, and the memory cells connected to the non-select word line WL may be turned on. The center dummy voltage VCD may be applied to the center dummy lines CDL 1  and CDL 2 , which are adjacent to the boundary in the direction to the bit line BL of the select stack, and the center dummy lines CDL 3  and CDL 4  located between the select stack and the bit line BL, and the center dummy transistors may be turned on. 
       FIG.  15    is a diagram illustrating a BV NOT AND (NAND) structure according to an example embodiment. A memory device of  FIG.  15    may include at least two upper chips each including a cell area. For example, the non-volatile memory device of  FIG.  15    may have a structure in which a first upper chip including a first cell area CELL 1 , a second upper chip including a second cell area CELL 2 , and a lower chip including a peripheral circuit area PERI connected to each other by a bonding technique. The non-volatile memory device of  FIG.  15    may be a bonding vertical NAND (BVNAND) memory device having a chip-to-chip (C2C) structure. The C2C structure may be developed by manufacturing the second upper chip including a cell region CELL 2  on a first wafer, manufacturing a lower chip including a peripheral circuit region PERI on a second wafer, which is different from the first wafer, and connecting the upper chip to the lower chip by using the bonding technique. As an example, the bonding technique may refer to a method of electrically connecting a bonding metal formed on an uppermost metal layer of the second upper chip to a bonding metal formed on an uppermost metal layer of the lower chip. Likewise, the first upper chip and the second upper chip can also be bonded in the same way. The number of upper chips is not limited thereto. Hereinafter, the cell area CELL may refer to at least one of the first cell area CELL 1  and the second cell area CELL 2 . 
     Each of the peripheral circuit region PERI and the cell region CELL of the memory device may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. 
     The peripheral circuit region PERI may include a first substrate  810 , an interlayer insulating layer  815 , a plurality of circuit elements  820   a ,  820   b , and  820   c  formed on the first substrate  810 , first metal layers  830   a ,  830   b , and  830   c  respectively connected to the plurality of circuit elements  820   a ,  820   b , and  820   c , and second metal layers  840   a ,  840   b , and  840   c  formed on the first metal layers  830   a ,  830   b , and  830   c . In an example embodiment, the first metal layers  830   a ,  830   b , and  830   c  may be formed of tungsten having relatively high electrical resistivity, and the second metal layers  840   a ,  840   b , and  840   c  may be formed of copper having relatively low electrical resistivity. 
     In the example embodiment illustrated in  FIG.  15   , although only the first metal layers  830   a ,  830   b , and  830   c  and the second metal layers  840   a ,  840   b , and  840   c  are shown and described, embodiments of the inventive concept are not limited thereto. For example, one or more additional metal layers may be further formed on the second metal layers  840   a ,  840   b , and  840   c . At least a portion of the one or more additional metal layers formed on the second metal layers  840   a ,  840   b , and  840   c  may be formed of aluminum or another metal having a lower electrical resistivity than those of copper forming the second metal layers  840   a ,  840   b , and  840   c.    
     The interlayer insulating layer  815  may be disposed on the first substrate  810  and cover the plurality of circuit elements  820   a ,  820   b , and  820   c , the first metal layers  830   a ,  830   b , and  830   c , and the second metal layers  840   a ,  840   b , and  840   c . The interlayer insulating layer  815  may include an insulating material such as silicon oxide or silicon nitride. 
     Lower bonding metals  871   b  and  872   b  may be formed on the second metal layer  840   b  in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals  871   b  and  872   b  in the peripheral circuit region PERI may be electrically bonded to upper bonding metals  771   b  and  772   b  of the cell region CELL. The lower bonding metals  871   b  and  872   b  and the upper bonding metals  771   b  and  772   b  may be formed of aluminum, copper, or tungsten. Further, the upper bonding metals  771   b  and  772   b  in the cell region CELL may be referred as first metal pads and the lower bonding metals  871   b  and  872   b  in the peripheral circuit region PERI may be referred as second metal pads. 
     The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate  610  and a common source line  620 . On the second substrate  610 , a plurality of word lines  631  to  638  (i.e.,  630 ) and  731  to  738  (i.e.,  730 ) may be stacked in a direction (a Z-axis direction), perpendicular to an upper surface of the second substrate  610 . At least one string select line and at least one ground select line may be arranged on and below the plurality of word lines  630  and  730 , respectively, and the plurality of word lines  630  and  730  may be disposed between the at least one string select line and the at least one ground select line. 
     In the bit line bonding area BLBA, a channel structure CH may extend in a direction (a Z-axis direction), perpendicular to the upper surface of the second substrate  610 , and pass through the plurality of word lines  630  and  730 , the at least one string select line, and the at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to a first metal layer  750   c  and a second metal layer  660   c . For example, the first metal layer  750   c  may be a bit line contact, and the second metal layer  660   c  may be a bit line. In an example embodiment, the bit line  660   c  may extend in a first direction (a Y-axis direction), parallel to the upper surface of the second substrate  610 . 
     In the example embodiment illustrated in  FIG.  15   , an area in which the channel structure CH, and the bit line  660   c  are disposed may be defined as the bit line bonding area BLBA. In the bit line bonding area BLBA, the bit line  660   c  may be electrically connected to the circuit elements  820   c  including a page buffer  793  in the peripheral circuit region PERI. The bit line  660   c  may be connected to upper bonding metals  771   c ,  772   c ,  871   c  and  872   c  in the cell region CELL, and the upper bonding metals  771   c ,  772   c ,  871   c  and  872   c  may be connected to lower bonding metals  771   c ,  772   c ,  871   c  and  872   c  connected to the circuit elements  820   c  of the page buffer  793 . 
     In the word line bonding area WLBA, the plurality of word lines  630  and  730  may extend in a second direction (an X-axis direction), parallel to the upper surface of the second substrate  610  and perpendicular to the first direction, and may be connected to a plurality of cell contact plugs  641  to  647  (i.e.,  640 ) and  741  to  747  (i.e.,  740 ). The plurality of word lines  630  and  730  and the plurality of cell contact plugs  640  may be connected to each other in pads provided by at least a portion of the plurality of word lines  630  and  730  extending at different lengths in the second direction. A first metal layer  750   b  and a second metal layer  760   b  may be connected to an upper portion of the plurality of cell contact plugs  640  connected to the plurality of word lines  630  and  730 , sequentially. The plurality of cell contact plugs  640  may be connected to the peripheral circuit region PERI by the upper bonding metals  771   b  and  772   b  of the cell region CELL and the lower bonding metals  871   b  and  872   b  of the peripheral circuit region PERI in the word line bonding area WLBA. 
     The plurality of cell contact plugs  640  may be electrically connected to the circuit elements  820   b  forming a row decoder  794  in the peripheral circuit region PERI. In an example embodiment, operating voltages of the circuit elements  820   b  of the row decoder  794  are different than operating voltages of the circuit elements  820   c  forming the page buffer  793 . For example, operating voltages of the circuit elements  820   c  forming the page buffer  793  may be greater than operating voltages of the circuit elements  820   b  forming the row decoder  794 . 
     A common source line contact plug  780  may be disposed in the external pad bonding area PA. The common source line contact plug  780  may be formed of a conductive material such as a metal, a metal compound, or polysilicon, and may be electrically connected to the common source line  620 . A first metal layers  650   a  and  750   a  and a second metal layers  660   a  and  760   a  may be stacked on an upper portion of the common source line contact plug  780 , sequentially. For example, an area in which the common source line contact plug  780 , the first metal layers  650   a  and  750   a , and the second metal layer  660   as  and  760   a  are disposed may be defined as the external pad bonding area PA. 
     Input-output pads  805  and  505  may be disposed in the external pad bonding area PA. Referring to  FIG.  15   , a lower insulating film  801  covering a lower surface of the first substrate  810  may be formed below the first substrate  810 , and a first input-output pad  805  may be formed on the lower insulating film  801 . The first input-output pad  805  may be connected to at least one of the plurality of circuit elements  820   a ,  820   b , and  820   c  disposed in the peripheral circuit region PERI through a first input-output contact plug  803 , and may be separated from the first substrate  810  by the lower insulating film  801 . In addition, a side insulating film may be disposed between the first input-output contact plug  803  and the first substrate  810  to electrically separate the first input-output contact plug  803  and the first substrate  810 . 
     Referring to  FIG.  15   , an upper insulating film  601  covering the upper surface of the second substrate  610  may be formed on the second substrate  610 , and a second input-output pad  505  may be disposed on the upper insulating layer  601 . The second input-output pad  505  may be connected to at least one of the plurality of circuit elements  820   a ,  820   b , and  820   c  disposed in the peripheral circuit region PERI through a second input-output contact plugs  603 ,  604 ,  703 ,  704  and  705 . In an example embodiment, the second input-output pad  505  is electrically connected to a circuit element  820   a.    
     According to an example embodiment, the second substrate  610  and the common source line  620  are not disposed in an area in which the second input-output contact plugs  603 ,  604 ,  703 ,  704  and  705  is disposed. Also, the second input-output pad  505  does not overlap the word lines  630  and  730  in the third direction (the Z-axis direction). Referring to  FIG.  15   , the second input-output contact plugs  603 ,  604 ,  703 ,  704  and  705  may be separated from the second substrate  610  in a direction, parallel to the upper surface of the second substrate  610 , and may pass through the interlayer insulating layers  615  and  715  of the cell region CELL to be connected to the second input-output pad  505 . 
     According to an example embodiment, the first input-output pad  805  and the second input-output pad  505  are selectively formed. For example, the memory device may include only the first input-output pad  805  disposed on the first substrate  810  or the second input-output pad  505  disposed on the second substrate  610 . Alternatively, the memory device may include both the first input-output pad  805  and the second input-output pad  505 . 
     A metal pattern provided on an uppermost metal layer may be provided as a dummy pattern or the uppermost metal layer may be absent, in each of the external pad bonding area PA and the bit line bonding area BLBA, respectively included in the cell region CELL and the peripheral circuit region PERI. 
     In the external pad bonding area PA, the memory device may include a lower metal patterns  871   a ,  872   a  and  873   a  corresponding to an upper metal patterns  671   a ,  672   a ,  771   a  and  772   a  formed in an uppermost metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal patterns  671   a ,  672   a ,  771   a  and  772   a  of the cell region CELL so as to be connected to each other, in an uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, in an embodiment, the lower metal patterns  871   a ,  872   a  and  873   a  formed in the uppermost metal layer of the peripheral circuit region PERI is not connected to a contact. Similarly, in the external pad bonding area PA, an upper metal patterns  671   a ,  672   a ,  771   a  and  772   a , corresponding to the lower metal patterns  871   a ,  872   a  and  873   a  formed in an uppermost metal layer of the peripheral circuit region PERI, and having the same shape as a lower metal patterns  871   a ,  872   a  and  873   a  of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. 
     The lower bonding metals  871   b  and  872   b  may be formed on the second metal layer  840   b  in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals  871   b  and  872   b  of the peripheral circuit region PERI may be electrically connected to the upper bonding metals  771   b  and  772   b  of the cell region CELL by a Cu-to-Cu bonding. 
     Further, in the bit line bonding area BLBA, an upper metal pattern  892 , corresponding to a lower metal pattern  852  formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same cross-sectional shape as the lower metal pattern  852  of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. In an embodiment, a contact is not formed on the upper metal pattern  892  formed in the uppermost metal layer of the cell region CELL. 
     In an example embodiment, corresponding to a metal pattern formed in an uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI, a reinforcement metal pattern having the same cross-sectional shape as the metal pattern may be formed in an uppermost metal layer in the other one of the cell region CELL and the peripheral circuit region PERI. In an embodiment, a contact is not formed on the reinforcement metal pattern. 
     In a bit line bonding area BLBA, the cell area CELL may include a lower channel LCH and an upper channel UCH that are connected to each other. The lower channel LCH and the upper channel UCH may be connected to each other to form one channel structure CH. The channel structure CH of  FIG.  15    may be provided through a process for the lower channel LCH and a process for the upper channel UCH. In the first cell area CELL, the lower channel LCH may extend in a direction perpendicular to an upper surface of a third substrate  610  and penetrate through a common source line  620  and lower word lines  631  to  634 . The lower channel LCH may include a data storage layer, a channel layer, and a buried insulation layer and may be connected to the upper channel UCH. The upper channel UCH may penetrate through upper word lines  635  to  638 . The upper channel UCH may include a data storage layer, a channel layer, and a buried insulation layer, and the channel layer of the upper channel UCH may be electrically connected to a first metal layer  650   c  and a second metal layer  660   c . As a channel length increases, it may be difficult to form a channel having a constant width due to process reasons. The memory device  120  according to an embodiment of the disclosure may include a channel having improved width uniformity through the lower channel LCH and the upper channel UCH that are formed in a sequential process. 
     A string select line and a ground select line may be respectively disposed on upper and lower portions of each of the word lines  630  and  730 . According to an embodiment of the disclosure, a word line adjacent to the string select line or a word line adjacent to the ground select line may be dummy word lines. In the memory device  120  according to an embodiment, a word line located near a boundary of the lower channel LCH and the upper channel UCH may be a dummy word line. For example, the word line  634  and the word line  635  that form the boundary of the lower channel LCH and the upper channel UCH may be center dummy lines. 
     As described above with reference to  FIGS.  9  to  12   , by applying the center dummy voltage VCD or the ground voltage GND to the center dummy line, a switching operation of a transistor connected to the center dummy line may be controlled. By controlling the word lines of the non-select stack not to be involved in channel boosting during a program operation through the center dummy line, boosting efficiency may be increased, and pass voltage disturbance may be reduced. 
     In the bit line bonding area BLBA, the first cell area CELL 1  may include a first through electrode THV 1 , and the second cell area CELL 2  may include a second through electrode THV 2 . The first through electrode THV 1  may penetrate through the common source line  620  and the plurality of word lines  630 . The first through electrode THV 1  may further penetrate through the third substrate  610 . The first through electrode THV 1  may include a conductive material. Alternatively, the first through electrode THV 1  may include a conductive material surrounded by an insulating material. The second through electrode THV 2  may be the same as the first through electrode THV 1 . The first through electrode THV 1  and the second through electrode THV 2  may be electrically connected to each other by a first through upper metal pattern  672   b  and a second through lower metal pattern  771   d . The first through upper metal pattern  672   b  may be formed at an upper end of a first upper chip including the first cell area CELL 1 , and the second through lower metal pattern  771   d  may be formed at a lower end of a second upper chip including the second cell area CELL 2 . The first through electrode THV 1  may be electrically connected to the first metal layer  650   c  and the second metal layer  660   c . A first through via  671   b  may be provided between the second metal layer  660   c  and the first through upper metal pattern  672   b , and a second through via  772   d  may be provided between the second through electrode THV 2  and the second through lower metal pattern  771   d . The first through upper metal pattern  672   b  and the second through lower metal pattern  771   d  may be connected to each other by a bonding method. 
     According to an embodiment of the disclosure, a first upper metal pattern  672   a  may be provided at an upper end of the first cell area CELL 1 , and a first lower metal pattern  771   e  may be provided at a lower end of the second cell area CELL 2 . The first upper metal pattern  672   a  of the first cell area CELL 1  and the first lower metal pattern  771   e  of the second cell area CELL 2  may be connected to each other by the bonding method in an external pad bonding area PA. A second upper metal pattern  772   a  may be provided at an upper end of the second cell area CELL 2 , and a second lower metal pattern  873   a  may be provided at a lower end of the peripheral circuit area PERI. The second upper metal pattern  772   a  of the second cell area CELL 2  and the second lower metal pattern  873   a  of the peripheral circuit area PERI may be connected to each other in the external pad bonding area PA by the bonding method. 
     As disclosed herein, the performance of the flash memory may be improved by using the dummy word line to function similarly to an SSL. The dummy word line may function similar to SSL by turning on a select cell string connected to a program enable bit line and turning off a select cell string and a non-select cell string connected to a program prohibit bit line. By controlling an electrical connection of a transistor connected to the dummy word line, a stack to be programmed and a stack not to be programmed may be disconnected from each other. Because word lines of the stack not to be programmed do not participate in channel boosting since the electrical connection between the stacks is released, a constant voltage level may be maintained while a program loop is in progress. In addition, a length of a boosted channel is decreases to enable localized boosting, thereby increasing boosting efficiency. 
     As described above, embodiments are disclosed in the drawings and the specification. Although embodiments have been described using specific terms in the present specification, these are only used for the purpose of explaining the technical spirit of the disclosure and not used to limit the meaning or the scope of the disclosure described in the claims. Therefore, it will be understood by those of ordinary skill in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the disclosure should be defined by the technical spirit of the appended claims. 
     At least one of the components, elements, modules or units (collectively “components” in this paragraph) represented by a block in the drawings such as  FIGS.  2 - 3   , may be embodied as various numbers of hardware, software and/or firmware structures that execute respective functions described above. At least one of these components may use a direct circuit structure, such as a memory, a processor, a logic circuit, a look-up table, etc. that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Also, at least one of these components may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions, and executed by one or more microprocessors or other control apparatuses. Further, at least one of these components may include or may be implemented by a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Two or more of these components may be combined into one single component which performs all operations or functions of the combined two or more components. Also, at least part of functions of at least one of these components may be performed by another of these components. Functional aspects of the above example embodiments may be implemented in algorithms that execute on one or more processors. Furthermore, the components represented by a block or processing steps may employ any number of related art techniques for electronics configuration, signal processing and/or control, data processing and the like. 
     While the disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.