Patent Publication Number: US-10334193-B2

Title: Read-out circuits of image sensors and image sensors including the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     A claim for priority under 35 U.S.C. § 119 is made to Korean Patent Application No. 10-2016-0015505, filed on Feb. 11, 2016 and to Korean Patent Application No. 10-2017-0004055, filed on Jan. 11, 2017 in the Korean Intellectual Property Office (KIPO), the entire contents of which are hereby incorporated by reference. 
     BACKGROUND 
     The present inventive concepts herein relate to image sensors, and more particularly to read-out circuits of image sensors capable of reducing noise and image sensors including the same. 
     An image sensor is a semiconductor device that converts a photo image, such as light reflected by a subject for example, into an electric signal. Image sensors are widely used in portable electronic devices such as digital cameras, cellular phones, and the like. Image sensors can be generally classified into charged coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors. Recently, CMOS image sensors have received more attention compared to CCD image sensors due to advantages such as low manufacturing costs, low power consumption, ease of integration with peripheral circuits, and the like. CMOS image sensors may be classified generally into rolling shutter CMOS image sensors and global shutter CMOS image sensors. 
     SUMMARY 
     Embodiments of the inventive concept provide a read-out circuit of an image sensor capable of reducing influence of power supply noise. 
     Embodiments of the inventive concept provide an image sensor including the read-out circuit, capable of enhancing performance. 
     Embodiments of the inventive concept provide a read-out circuit of an image sensor, the read-out circuit including a ramp signal generator, a bias voltage generator and a conversion circuit. The ramp signal generator is configured to generate a ramp signal that linearly varies with a constant slope. The bias voltage generator is configured to generate a bias voltage based on a power supply voltage, the power supply voltage having a first noise component. The conversion circuit is configured to generate a reference voltage based on the bias voltage and the ramp signal, and configured to perform an analog-to-digital conversion on an analog signal from a pixel to generate a digital signal corresponding to the analog signal. The analog signal has a second noise component. The bias voltage generator is further configured to adjust an alternating current (AC) component included in the bias voltage so that a magnitude of a third noise component in the reference voltage is substantially the same as a magnitude of the second noise component. 
     Embodiments of the inventive concept provide an image sensor including a pixel array, a ramp signal generator, a bias voltage generator, and a plurality of conversion circuits. The pixel array is connected to a power supply voltage, the pixel array including a plurality of unit pixels configured to sense an incident light and to generate analog signals. The ramp signal generator is configured to generate a ramp signal that changes with a constant slope. The bias voltage generator is configured to generate a bias voltage based on a power supply voltage, the power supply voltage having a first noise component. The plurality of conversion circuits are each configured to generate a reference voltage based on the bias voltage and the ramp signal, and are configured to perform an analog-to-digital conversion on respective different ones of the analog signals to generate digital signals corresponding to the analog signals. The analog signals have a second noise component. The bias voltage generator is configured to adjust an alternating current (AC) component included in the bias voltage so that a magnitude of a third noise component in the reference voltage is substantially the same as a magnitude of the second noise component. 
     Embodiments of the inventive concept provide an image sensor including a pixel connected to a power supply voltage and configured to generate an analog signal responsive to incident light, the power supply voltage having a first noise component and the analog signal having a second noise component; and a read-out circuit configured to generate a bias voltage based on the power supply voltage, to generate a reference voltage based on the bias voltage and a ramp signal, to convert the analog signal to a digital signal, and to adjust an alternating current (AC) component in the bias voltage so that a magnitude of a third noise component in the reference voltage is substantially the same as a magnitude of the second noise component. 
     Accordingly, the read-out circuit and the image sensor including the read-out circuit may cancel a noise component by adjusting the noise component of the reference voltage to have substantially the same magnitude as a magnitude of a noise component of the analog signal which is output from a unit pixel. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Illustrative, non-limiting embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. 
         FIG. 1  illustrates a block diagram of an image sensor according to an embodiment of the inventive concept. 
         FIG. 2  further illustrates the image sensor of  FIG. 1  according to an embodiment of the inventive concept. 
         FIG. 3  illustrates a circuit diagram of an example of a unit pixel included in the pixel array in  FIG. 2 . 
         FIG. 4  illustrates a circuit diagram of another example of a unit pixel included in the pixel array in  FIG. 2 . 
         FIG. 5  illustrates a circuit diagram of an example of the ramp signal generator in  FIG. 2 . 
         FIG. 6  illustrates a block diagram of one of the conversion circuits in  FIG. 2 . 
         FIG. 7  illustrates an example of the correlated double sampling circuit in  FIG. 6  according to an embodiment of the inventive concept. 
         FIG. 8  illustrates a circuit diagram of the ramp buffer in the conversion circuit of  FIG. 6  according an embodiment of the inventive concept. 
         FIG. 9  illustrates a circuit diagram of an example of the bias voltage generator in  FIG. 2  according to an embodiment of the inventive concept. 
         FIG. 10  illustrates a circuit diagram of another example of the bias voltage generator in  FIG. 2  according an embodiment of the inventive concept. 
         FIG. 11  illustrates a circuit diagram of another example of the bias voltage generator in  FIG. 2  according to an embodiment of the inventive concept. 
         FIG. 12  illustrates a circuit diagram of another example of the bias voltage generator in  FIG. 2  according to an embodiment of the inventive concept. 
         FIG. 13  illustrates a diagram for explaining a concept of the inventive concept. 
         FIG. 14  illustrates a timing diagram explanatory of operation of the row driver and the pixel array in the image sensor of  FIG. 2 . 
         FIG. 15  illustrates a timing diagram explanatory of the operation of the image sensor of  FIG. 1 . 
         FIG. 16  illustrates a block diagram of one of the conversion circuits in  FIG. 2 . 
         FIG. 17  illustrates an example of the correlated double sampling circuit in  FIG. 16  according to an embodiment of the inventive concept 
         FIG. 18  illustrates a circuit diagram of the pixel bias circuit in the conversion circuit of  FIG. 16  according to an embodiment of the inventive concept. 
         FIG. 19  illustrates a circuit diagram of another example of the bias voltage generator in  FIG. 2  according to an embodiment of the inventive concept. 
         FIG. 20  illustrates a circuit diagram of another example of the bias voltage generator in  FIG. 2  according to an embodiment of the inventive concept. 
         FIG. 21  illustrates a circuit diagram of another example of the bias voltage generator in  FIG. 2  according to an embodiment of the inventive concept. 
         FIG. 22  illustrates a diagram for explaining operation of the comparator in  FIG. 17  according to the present inventive concept. 
         FIG. 23  illustrates a block diagram of an example of a camera including the image sensor according to an embodiment of the inventive concept. 
     
    
    
     DETAILED DESCRIPTION 
     Various embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings. 
     As is traditional in the field of the inventive concepts, embodiments may be described and illustrated in terms of blocks which carry out a described function or functions. These blocks, which may be referred to herein as units or modules or the like, are physically implemented by analog and/or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits and the like, and may optionally be driven by firmware and/or software. The circuits may, for example, be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards and the like. The circuits constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block. Each block of the embodiments may be physically separated into two or more interacting and discrete blocks without departing from the scope of the inventive concepts. Likewise, the blocks of the embodiments may be physically combined into more complex blocks without departing from the scope of the inventive concepts. 
       FIG. 1  illustrates a block diagram of an image sensor according to an embodiment of the inventive concept. 
     Referring to  FIG. 1 , an image sensor  10  includes a pixel array  100 , a control circuit  200  and a read-out circuit ROC. The read-out circuit ROC includes a ramp signal generator  250 , a bias voltage generator  400 , a conversion block  300 , and a buffer  190 . 
     The pixel array  100  detects incident light to generate an analog signal AS. The pixel array  100  may include a plurality of unit pixels arranged in the form of a matrix and each unit pixel may detect the incident light to generate the analog signal AS. Each unit pixel may convert incident light to an electric signal and may store the electric signal. 
     The ramp signal generator  250  generates a ramp signal VR which linearly varies at a constant slope. 
     The bias voltage generator  400  generates a bias voltage VBP or VBN based on a power supply voltage, and an alternating current (AC) component of the power supply voltage may include a first noise component. Therefore, the bias voltage VBP or VBN may include an AC component, and the bias voltage generator  400  may adjust a magnitude (or, a characteristic) of the AC component of the bias voltage VBP or VBN and provide the bias voltage VBP or VBN to the conversion block  300 . 
     The conversion block  300  generates a reference voltage based on the bias voltage VBP and the ramp signal VR, and performs a single-slope analog-to-digital conversion on the analog signal AS by using the reference voltage to generate a digital signal DGS. In addition, the conversion block  300  performs a single-slope analog-to-digital conversion on the analog signal AS by using the ramp signal VR to generate the digital signal DGS. That is, the conversion block  300  may be an analog-to-digital conversion block or an analog-to-digital conversion circuit. The unit pixels that provide the analog signal AS are also coupled to the power supply voltage to which the bias voltage generator  400  is connected. Therefore, a second noise component due to the first noise component of the power supply voltage may be added to the analog signal AS. The bias voltage generator  400  may adjust the magnitude of the AC component of the bias voltage VBP so that a magnitude of a third noise component added to (or created in) the reference voltage is substantially the same as a magnitude of the second noise component. In addition, the bias voltage generator  400  may adjust the magnitude of the AC component of the bias voltage VBN so that a magnitude of a third noise component provided to the analog signal AS is substantially the same as a magnitude of the second noise component, and a phase of the third noise component is substantially opposite to a phase of the second noise component. 
     The control circuit  400  may control operation of the pixel array  100  through a first control signal CTL 1 , may control operation of the ramp signal generator  250  through a second control signal CTL 2 , may control operation of the bias voltage generator  400  through a third control signal CTL 3 , may control operation of the conversion block  300  through a fourth control signal CTL 4 , and may control operation of the buffer  190  through a fifth control signal CTL 5 . 
     The buffer  190  temporarily stores the digital signal DGS from the conversion block  300  and may perform sensing and amplification operations on the digital signal DGS to generate corresponding image data IDTA to be output. 
       FIG. 2  further illustrates the image sensor of  FIG. 1  according to an embodiment of the inventive concept. 
     Referring to  FIG. 2 , the image sensor  10  includes as in  FIG. 1  the pixel array  100 , the control circuit  200 , the ramp signal generator  250 , the bias voltage generator  400 , the conversion block  300 , and the buffer  190 . 
     The control circuit  200  includes a timing controller  210  and a row driver  220 . The pixel array  100  may include a plurality of unit pixels (UP)  110  arranged in a matrix that includes a plurality of rows and a plurality of columns. The conversion block  300  may include a plurality of conversion circuits  310 , and each of the conversion circuits  310  are coupled to respective ones of the columns of the unit pixels  110  through a corresponding column line CL. The buffer  190  includes a column memory block  191  and a sense amplifier  192 . The column memory block  191  includes a plurality of individual memories  193 . The plurality of memories  193  store the digital signals DGS provided from the conversion circuits  310 . The sense amplifier  192  senses and amplifies the digital signals DGS stored in the column memory block  191  and then outputs the image data IDTA. 
     The timing controller  210  may provide the row driver  220  with a first internal control signal ICTL 1  and an address signal ADDR, and the row driver  220  may control operation of the unit pixels  110  of the pixel array  100  on a row by row basis based on the first internal control signal ICTL 1  and the address signal ADDR. For example, the row driver  220  controls operation of the unit pixels  110  of the pixel array  100  on a row by row basis by applying a (row) selection control signal SEL, a reset control signal RST and a transfer control signal TX to the pixel array  100 . The selection control signal SEL, the reset control signal RST and the transfer control signal TX may be collectively characterized as the first control signal CTL 1 . 
     Each of the unit pixels  110  of the pixel array  100  may generate a first analog signal AS 1  representing a reset component and a second analog signal AS 2  representing an image component based on the selection control signal SEL, the reset control signal RX and the transfer control signal TX provided from the row driver  220 . Since each of the unit pixels  110  included in the pixel array  100  has their own pixel property or logic property which influences the analog signal AS output therefrom, variation may occur in amplitude of the analog signal AS generated from the unit pixels based on the same incident light. Thus, it is necessary to extract the effective component of the incident light based on the difference between the reset component generated from each unit pixel and the image component according to the incident light. 
     To this end, each of the unit pixels  110  included in the pixel array  100  sequentially generates the first analog signal AS 1  representing the reset component and the second analog signal AS 2  representing the image component according to the incident light based on the selection control signal SEL, the reset control signal RST and the transfer control signal TX provided from the row driver  220 . The conversion block  300  generates a first digital signal corresponding to the first analog signal AS 1  and a second digital signal corresponding to the second analog signal AS 2 , to output the digital signal DGS based on the difference between the first and second digital signals. Therefore, the digital signal DGS may represent the effective component of the incident light. 
       FIG. 3  illustrates a circuit diagram of an example of a unit pixel included in the pixel array in  FIG. 2 . 
     Referring to  FIG. 3 , a unit pixel  110   a  includes a photo detector (or, a photo sensitive device) (PD)  111 , a transfer transistor  113 , a reset transistor  115 , a sensing transistor  117  and a selection transistor  119 . 
     The photo detector  111  has a first terminal coupled to a ground voltage GND and converts an incident light to an electric signal. The transfer transistor  113  is coupled to a second terminal of the photo detector  111  and a floating diffusion node FD, and has a gate connected to the transfer control signal TX. The reset transistor  115  is coupled between a power supply voltage VDD (which includes the first noise component NP) and the floating diffusion node FD, and has a gate connected to the reset control signal RST. The sensing transistor  117  is coupled to the power supply voltage VDD and has a gate coupled to the floating diffusion node FD. The selection transistor  119  is coupled to the sensing transistor  117  and a corresponding column line CL, and has a gate connected to the selection control signal SEL. In  FIG. 3 , the first analog signal AS 1  and the second analog signal AS 2  include the second noise component denoted as N_AS. 
       FIG. 4  illustrates a circuit diagram of another example of a unit pixel included in the pixel array in  FIG. 2 . Unit pixel  110   b  of  FIG. 4  includes similar components as unit pixel  110   a  of  FIG. 3 . The following will therefore focus on differences between unit pixel  110   a  and unit pixel  110   b , and description of like components will be omitted. 
     Unit pixel  110   b  of  FIG. 4  differs from the unit pixel  110   a  in that the unit pixel  110   b  further includes a transistor  121 . The transistor  121  has a first terminal coupled to a gate of the transfer transistor  113 , a gate coupled to a gate of the selection transistor  119  and the selection control signal SEL, and a second terminal connected to the transfer control signal TX. 
     Hereinafter, the operation of the unit pixel  110   a  will be described with reference to  FIGS. 2 and 3 . In the following, although operation of one of the unit pixels  110   a  of a selected row is described, it should be understood that the selection control signal SEL, the reset control signal RST and the transfer control signal TX are provided from the row driver  220  to all the pixel units  100  of the selected row. 
     The photo detector  111  detects the incident light to generate electron-hole pairs (EHP), and the EHPs are accumulated at a source node of the transfer transistor  113 . 
     The row driver  220  provides an activated select control signal SEL to the pixel array  100  to turn on the row selection transistor  119  to select one of the rows included in the pixel array  100 , and provides an activated reset control signal RST to the selected row to turn on the reset transistor  115 . Therefore, an electric potential of the floating diffusion node FD may have a level of the power supply voltage VDD, and the sensing transistor  117  is consequently turned on so that the first analog signal AS 1  representing the reset component is output from the unit pixel  110   a . Then, the row driver  220  deactivates the reset control signal RST. 
     Thereafter, the row driver  220  provides an activated transfer control signal TX to the pixel array  100  to turn on the transfer transistor  113  so that the electrons of the EHPs accumulated in the source node of the transfer transistor  113  are transferred to the floating diffusion node FD. The electric potential of the floating diffusion node FD may vary depending on the quantity of the electrons of the EHPs, and the electric potential of a gate of the sensing transistor  117  may consequently also vary. If the selection transistor  119  is in a turn-on state, the second analog signal AS 2  corresponding to the electric potential of the floating diffusion node FD is output from the unit pixel  110   a.    
     The row driver  220  controls the unit pixels  110   a  of the pixel array  100  to sequentially output the first and second analog signals AS 1  and AS 2  row by row (i.e., by units of rows) by repeating the above operation with respect to subsequent rows. For example, the first and second analog signals AS 1  and AS 2  of unit pixels  110   a  of a first row are output, thereafter the first and second analog signals AS 1  and AS 2  of unit pixels  110   a  of a second row are output, and so on. 
     Referring again to  FIG. 2 , the timing controller  210  provides a count enable signal CNT_EN (second control signal CTL 2 ) to the ramp signal generator  250  to control the operation of the ramp signal generator  250 . The ramp signal generator  250  may generate the ramp signal VR which descends (decreases) with a constant slope during an active interval when the count enable signal CNT_EN is enabled. 
       FIG. 5  illustrates a circuit diagram of an example of the ramp signal generator in  FIG. 2 . 
     Referring to  FIG. 5 , the ramp signal generator  250  includes a resistor  260  and a current generating unit  270 . The resistor  260  is connected between the power supply voltage VDD and the current generating unit  270  and may have a constant resistance value R. 
     The current generating unit  270  is connected between the resistor  260  and the ground voltage GND (not shown). The current generating unit  270  is connected to the count enable signal CNT_EN provided from the control circuit  200 . The current generating unit  270  may generate the reference current Iref, which increases at a constant rate during the active interval where the count enable signal CNT_EN is enabled. The current generating unit  270  includes a constant current source  271 , a current amplification unit  280  and a current control unit (CIU)  275 . 
     The constant current source  271  generates a constant current Io having a constant magnitude. The current amplification unit  280  amplifies the constant current Io based on amplifying control signals SCS 1  supplied from the current control unit  275 . Although not illustrated in  FIG. 5 , the current amplification unit  280  may include a plurality switches and a plurality of current mirrors. 
     The current control unit  275  generates the amplifying control signals SCS 1  based on the count enable signal CNT_EN and supplies the amplifying control signals SCS 1  to the switches in the current amplification unit  280  to adjust the amplitude of the reference current Iref flowing through the resistor  260  by selectively turning on/off the switches. 
     The ramp signal generator  250  outputs the ramp signal VR from the node where the resistor  260  is connected to the current amplification unit  280 . 
     The current control unit  275  opens all of the switches in the current amplification unit  280  to output the ramp signal VR having a maximum value and sequentially short-circuits the switches during the active interval when the count enable signal CNT_EN is enabled to descend (decrease) the magnitude of the ramp signal VR. 
     Referring again to  FIG. 2 , the timing controller  210  provides the third control signal CTL 3  to the bias voltage generator  400  to control the operation of the bias voltage generator  400 . The bias voltage generator  400  may adjust the magnitude of the AC component in the bias voltage VBP or VBN in response to the third control signal CTL 3 . The third control signal CTL may include a plurality of switching control signals and/or a sampling control signal as described below. In addition, the bias voltage generator  400  may generate a cascode voltage VCP or VCN in response to the third control signal CTL 3  and may provide the cascode voltage VCP or VCN to the conversion block  300 . 
     The timing controller  210  provides a count clock signal CLKC to the conversion block  300  to control the operation of the conversion block  300 . The count clock signal CLKC may be a signal toggling during the active interval when the count enable signal CNT_EN is enabled. The count clock signal CLKC may be included in the fourth control signal CTL 4 . 
     The conversion block  300  generates the digital signal DGS representing the effective component of the incident light based on the first and second analog signals AS 1  and AS 2  sequentially provided from the pixel array  100 . 
     The buffer sequentially outputs the digital signal DGS which are received from the conversion block  300  as image data IDTA and correspond to one row, based on the fifth control signal CTL 5  received from the timing controller  210 . The image data IDTA sequentially output from the buffer  190  may be provided to a digital signal processor. 
       FIG. 6  illustrates a block diagram of one of the conversion circuits in  FIG. 2 . 
     Referring to  FIG. 6 , the conversion circuit  310  includes a correlated double sampling (CDS) circuit  320 , a ramp buffer  330  and a counter  340 . 
     The ramp buffer  330  receives the ramp signal VR and the bias voltage VBP, and generates a reference voltage VREF based on the ramp signal VR and the bias voltage VBP. 
     The CDS circuit  320  generates a reset signal corresponding to the reset component and an image signal corresponding to the signal component by performing the correlated double sampling on the first and second analog signals AS 1  and AS 2 , respectively based on the reference voltage VREF. In addition, the CDS circuit  320  generates a comparison signal CMP by comparing the reset signal and the image signal with the reference voltage VREF, respectively. For example, the CDS circuit  320  may output the comparison signal CMP with a logic high level when the reset signal or the image signal is smaller than the reference voltage VREF. The CDS circuit  320  may output the comparison signal CMP with a logic low level when the reset signal or the image signal is equal to or greater than the reference voltage VREF. As will be described subsequently, the bias generator  400  adjusts the AC component of the bias voltage VBP to in turn adjust the third noise component added to the reference voltage VREF may be adjusted to have a same magnitude as the magnitude of the second noise component in the first and second analog signals AS 1  and AS 2 , respectively. 
     The counter  340  generates the digital signal DGS based on the comparison signal CMP and the count clock signal CLKC. For example, when the CDS circuit  320  outputs the comparison signal CMP by performing the correlated double sampling on the reset component, the counter  340  generates a first counting value by performing a counting operation in synchronization with the count clock signal CLKC until the comparison signal CMP transits to a logic low level. When the CDS circuit  320  outputs the comparison signal CMP by performing the correlated double sampling on the signal component, the counter  340  generates a second counting value by performing a counting operation in synchronization with the count clock signal CLKC until the comparison signal CMP transits to a logic low level. The counter  340  generates the digital signal DGS by subtracting the first counting value from the second counting value. 
       FIG. 7  illustrates an example of the correlated double sampling circuit in  FIG. 6  according to an embodiment of the inventive concept. 
     Referring to  FIG. 7 , the CDS circuit  320  includes a comparator  325 , a first capacitor C 1 , a second capacitor C 2 , a first switch  321  and a second switch  323 . 
     The first switch  321  samples the first analog signal AS 1  or the second analog signal AS 2  in response to a first switching control signal S 1 , and selectively provides the first and second analog signals AS 1  and AS 2  to the first capacitor C 1 . The first capacitor C 1  is connected between the first switch  321  and a negative input terminal of the comparator  325 . The second switch  323  is connected between the negative input terminal of the comparator  325  and output terminal of the comparator  325 , and is opened/closed in response to a second switching control signal S 2 . The second capacitor C 2  is connected in parallel with the second switch  323 . 
     The reference voltage VREF is applied to a positive input terminal of the comparator  325 . The CDS circuit  320  may determine voltage levels of the reset signal RSTS and the image signal IMGS, or in other words the comparison signal, based on the reference voltage VREF. 
       FIG. 8  illustrates a circuit diagram of the ramp buffer in the conversion circuit of  FIG. 6  according to an embodiment of the inventive concept. 
     Referring to  FIG. 8 , the ramp buffer  330  includes first through third p-channel metal oxide semiconductor (PMOS) transistors  331 ,  333  and  335  which are connected in series between the power supply voltage VDD (which includes the first noise component NP) and the ground voltage GND. 
     The first PMOS transistor  331  includes a source coupled to the power supply voltage VDD, a gate coupled to the bias voltage VBP and a drain coupled to the second PMOS transistor  333 . The second PMOS transistor  333  includes a source coupled to the first PMOS transistor  331 , a gate coupled to the cascode voltage VCP and a drain coupled to the third PMOS transistor  335 . The third PMOS transistor  335  includes a source coupled to the second PMOS transistor  333  at an output node NO, a gate coupled to the ramp signal VR and a drain coupled to the ground voltage GND. A body of the third PMOS transistor  335  is coupled to the source of the third PMOS transistor  335  and the reference voltage VREF is output at the output node NO. 
     Therefore, a first noise component NP in the power supply voltage VDD is represented as a third noise component N_VREF in the reference voltage VREF after going through the first PMOS transistor  331  and the second PMOS transistor  333 . The third noise component N_VREF in the reference voltage VREF may be adjusted by adjusting a magnitude (or a swing range) of a noise component N_VBP of the bias voltage VBP applied to the gate of first PMOS transistor  331 . The third noise component N_VREF in the reference voltage VREF may be adjusted to have a same magnitude as the magnitude of the second noise component in the analog signal AS from the unit pixel  110   a  or  110   b.    
       FIG. 9  illustrates a circuit diagram of an example of the bias voltage generator in  FIG. 2  according to an embodiment of the inventive concept. In  FIG. 9 , the ramp buffer  330  of  FIG. 8  is also illustrated with the bias voltage generator  400   a  for convenience of explanation. 
     Referring to  FIG. 9 , the bias voltage generator  400   a  includes a first current source  401 , a current mirror  410   a  and a PMOS transistor  403 . 
     The first current source  401  is connected between the power supply voltage VDD and a first node N 11 , and generates a first current I 1  having a constant magnitude. The first current source  401  may be implemented with a resistor R 2 . The current mirror  410   a  is connected to the first node N 11 , the ground voltage GND and a second node N 12 , and outputs a second current I 2  to the second node N 12 . The second current I 2  corresponds to a sum of the first sub-current I 21  and a second sub-current I 22 , and the first sub-current I 21  is proportional to the first current I 1 . The PMOS transistor  403  is coupled between the power supply voltage VDD and the second node N 12 , and provides the ramp buffer  330  with the bias voltage VBP based on the second current I 2 . The current mirror  410   a  adjusts the AC component N_VBP of the bias voltage VBP by adjusting a ratio of the first sub-current I 21  and the second sub-current I 22 . 
     The PMOS transistor  403  includes a source coupled to the power supply voltage VDD, and a drain and a gate which are coupled to the second node N 12 . The bias voltage VBP is output at the second node N 12 . 
     The current mirror  410   a  includes a first n-channel metal oxide semiconductor (NMOS) transistor  411 , a first current generation circuit  420  and a second current generation circuit  430 . 
     The first NMOS transistor  411  has a drain and a gate coupled to the first node N 11 , and a source coupled to the ground voltage GND. The first current generation circuit  420  is connected between the first node N 11 , the second node N 12  and the ground voltage GND, and generates the first sub-current I 21  whose magnitude varies in response to a first switching control signal SCS 2 . The second current generation circuit  430  is connected in parallel with the first current generation circuit  420  between the second node N 12  and the ground voltage GND, and generates the second sub-current I 22  whose magnitude varies in response to a second switching control signal SCS 3 . 
     The first current generation circuit  420  includes a plurality of first switches SW 2   l ˜SW 2   k  each connected in series with corresponding ones of a plurality of second NMOS transistors  42   l ˜ 42   k . Each series connected pair of the plurality of first switches SW 2   l ˜SW 2   k  and the plurality of second NMOS transistors  42   l ˜ 42   k  are connected in parallel to the second node N 12  and the ground voltage GND. The plurality of first switches SW 2   l ˜SW 2   k  are connected to the second node N 12 , and the plurality of second NMOS transistors  42   l ˜ 42   k  are connected to the ground voltage GND. Each of the first switches SW 2   l ˜SW 2   k  are coupled to a corresponding bit of the first switching control signal SCS 2  and each gate of the second NMOS transistors  42   l ˜ 42   k  is coupled to the gate of the first NMOS transistor  411  at the first node N 11 . 
     The second current generation circuit  430  includes a plurality of second switches SW 3   l ˜SW 3   k  each connected in series with corresponding ones of a plurality of second current sources  43   l ˜ 43   k . Each series connected pair of the plurality of second switches SW 3   l ˜SW 3   k  and the plurality of second current sources  43   l ˜ 43   k  are connected in parallel to the second node N 12  and the ground voltage GND. The plurality of second switches SW 3   l ˜SW 3   k  are connected to the second node N 12 , and the plurality of second current sources  43   l ˜ 43   k  are connected to the ground voltage GND. Each of the switches SW 3   l ˜SW 3   k  are coupled to a corresponding bit of the second switching control signal SCS 3  and each of the second current sources  43   l ˜ 43   k  generates a same constant current. 
     Therefore, the magnitude of the first sub-current I 21  is proportional to the magnitude of the first current I 1 , and the sum of the first sub-current I 21  and the second sub-current I 22  corresponds to the second current I 2 . Accordingly, the magnitude of the first sub-current I 21  and the magnitude of the second sub-current I 22  are adjustable according to bit values of the first switching control signal SCS 2  and the second switching control signal SCS 3 . The first and second switching control signals SCS 2  and SCS 3  may be part of the third control signal CTL 3  provided from timing controller  210 . 
     A voltage V 11  of the first node N 11  based on the first current I 1  may include a direct current (DC) component and an AC component N_V 11 . Since the first current generation circuit  420  includes the second NMOS transistors  42   l ˜ 42   k  and the second current generation circuit  430  includes the second current sources  43   l ˜ 43   k  which generate constant currents, the AC component N_V 11  of the voltage V 11  may be adjusted by the magnitude of the first sub-current I 21 . Therefore, the AC component N_VBP of the bias voltage VBP based on the second current I 2  may be adjusted by the ratio of the first sub-current I 21  and the second sub-current I 22 , and the third noise component N_VREF of the reference voltage VREF may also be adjusted by the ratio of the first sub-current I 21  and the second sub-current I 22 . 
       FIG. 10  illustrates a circuit diagram of another example of the bias voltage generator in  FIG. 2  according to an embodiment of the inventive concept. In  FIG. 10 , the ramp buffer  330  of  FIG. 8  is also illustrated with a bias voltage generator  400   b  for convenience of explanation. 
     Referring to  FIG. 10 , the bias voltage generator  400   b  includes a current source  401 , a current mirror  410   b , a PMOS transistor  403 , a sampling switch  405 , a first sampling bank  440  and a second sampling bank  450 . 
     The current source  401  is connected between the power supply voltage VDD and a first node N 21 , and generates a first current I 1  having a constant magnitude. The current mirror  410   b  is connected to the first node N 21 , the ground voltage GND and a second node N 22 , and outputs a second current I 2  having a same magnitude as the first current I 1  to the second node N 22  by mirroring the first current I 1 . The current mirror  410   b  includes NMOS transistors  413  and  414 . The drain and the source of NMOS transistor  413  are respectively connected to the first node N 21  and the ground voltage GND. The drain and the source of NMOS transistor  414  are respectively connected to the second node N 22  and the ground voltage GND. The gates of NMOS transistors  413  and  414  are connected together to first node N 21 . A voltage V 11  of the first node N 21  is based on the first current I 1 . The PMOS transistor  403  includes a drain coupled to the power supply voltage VDD, and a source and a gate coupled to the second node N 22 . The PMOS transistor  403  provides the sampling switch  405  with the bias voltage VBP based on the second current I 2 . 
     The sampling switch  405  is connected between the second node N 22  (a gate of the PMOS transistor  403 ) and a third node N 23 , and connects the bias voltage VBP to the third node N 23  in response to a sampling control signal SPC 1 . The first sampling bank  440  is connected between the power supply voltage VDD and the third node N 23 , and samples a first portion of the bias voltage VBP therein in response to a first switching control signal SCS 4 . The second sampling bank  450  is connected between the third node N 23  and the ground voltage GND, and samples a second portion of the bias voltage VBP therein in response to a second switching control signal SCS 5 . 
     The first sampling bank  440  includes a plurality of first capacitors  44   l ˜ 44   k  each connected in series with corresponding ones of a plurality of first switches SW 4   l ˜SW 4   k . Each series connected pair of the plurality of first capacitors  44   l ˜ 44   k  and the plurality of first switches SW 4   l ˜SW 4   k  are connected in parallel to the power supply voltage VDD and the third node N 23 . The plurality of first capacitors  44   l ˜ 44   k  are connected to the power supply voltage VDD, and the plurality of first switches SW 4   l ˜SW 4   k  are connected to the third node N 23 . Each of the first switches SW 4   l ˜SW 4   k  are coupled to a corresponding bit of the first switching control signal SCS 4  and each of the first capacitors  44   l ˜ 44   k  may have a same capacitance. 
     The second sampling bank  450  includes a plurality of second switches SW 5   l ˜SW 5   k  each connected in series with corresponding ones of a plurality of second capacitors  45   l ˜ 45   k . Each series connected pair of the plurality of second switches SW 5   l ˜SW 5   k  and the plurality of second capacitors  45   l ˜ 45   k  are connected in parallel to the third node N 23  and the ground voltage GND. The plurality of second switches SW 5   l ˜SW 5   k  are connected to the third node N 23 , and the plurality of second capacitors  45   l ˜ 45   k  are connected to the ground voltage GND. Each of the second switches SW 5   l ˜SW 5   k  are coupled to a corresponding bit of the second switching control signal SCS 5  and each of the second capacitors  45   l ˜ 45   k  may have a same capacitance. 
     In other embodiments, each of the first sampling bank  440  and the second sampling bank  450  may be implemented with a variable capacitor. 
     The ratio of the first portion of the bias voltage VBP stored in the first capacitors  44   l ˜ 44   k  and the second portion of the bias voltage VBP stored in the second capacitors  45   l ˜ 45   k  may be varied according to the combination of bits of the first switching control signal SCS 4  and bits of the second switching control signal SCS 5 . When it is assumed that the ground voltage GND includes little noise component because the ground voltage GND is stable, the magnitude of the AC component N_VBP of the bias voltage VBP may be adjusted by the ratio of the first portion of the bias voltage VBP stored in the sampling bank  440  and the second portion of the bias voltage VBP stored in the second sampling bank  450 . Since the magnitude of the AC component N_VBP of the bias voltage VBP may be increased or decreased by the ratio of the first portion of the bias voltage VBP stored in the sampling bank  440  and the second portion of the bias voltage VBP stored in the second sampling bank  450 , the magnitude of the third noise component N_VREF of the reference voltage VREF may be also adjusted accordingly. 
     In  FIG. 10 , the sampling control signal SPC 1 , the first switching control signal SCS 4  and the second switching control signal SCS 5  may be included in the third control signal CTL 3  provided from the control circuit  200 . 
       FIG. 11  illustrates a circuit diagram of another example of the bias voltage generator in  FIG. 2  according to an embodiment of the inventive concept. In  FIG. 11 , the ramp buffer  330  of  FIG. 8  is also illustrated with a bias voltage generator  400   c  for convenience of explanation. 
     Referring to  FIG. 11 , the bias voltage generator  400   c  includes a current source  401 , a switched current mirror  410   c , and a PMOS transistor  417 . 
     The current source  401  is connected between the power supply voltage VDD and a first node N 31 , and generates a first current I 1  having a constant magnitude. The switched current mirror  410   c  is connected to the first node N 31 , the power supply voltage VDD and a third node N 33 , and outputs a second current I 2  proportional to the first current I 1  to the third node N 33  by mirroring first current I 1  when a sampling switch  407  therein is turned on. The PMOS transistor  417  includes a source connected to the power supply voltage VDD, and a gate and a drain connected to the third node N 33 , and provides the ramp buffer  330  with the bias voltage VBP based on the second current I 2 . 
     The switched current mirror  410   c  includes a first NMOS transistor  415 , the sampling switch  407 , a first sampling bank  460 , a second sampling bank  470  and a second NMOS transistor  416 . 
     The first NMOS transistor  415  includes a drain and a gate coupled to the first node N 31 , and a source coupled to the ground voltage GND. The sampling switch  407  is connected between the first node N 31  (a gate of the first NMOS transistor  415 ) and the second node N 32 , and provides a secondary bias voltage VBN at the second node N 32  in response to a sampling control signal SPC 2 . The first sampling bank  460  is connected between the power supply voltage VDD and the second node N 32 , and samples a first portion of the secondary bias voltage VBN therein in response to a first switching control signal SCS 6 . The second sampling bank  470  is connected between the second node N 32  and the ground voltage GND, and samples a second portion of the secondary bias voltage VBN therein in response to a second switching control signal SCS 7 . The second NMOS transistor  416  includes a gate coupled to the second node N 32 , a drain coupled to the third node N 33  and a source coupled to the ground voltage GND. The gate of the second NMOS transistor  416  is connected to the secondary bias voltage VBN and draws the second current I 2  in response to the secondary bias voltage VBN. 
     The first sampling bank  460  includes a plurality of first capacitors  46   l ˜ 46   k  each connected in series with corresponding ones of a plurality of first switches SW 6   l ˜SW 6   k . Each series connected pair of the plurality of first capacitors  46   l ˜ 46   k  and the plurality of first switches SW 6   l ˜SW 6   k  are connected in parallel to the power supply voltage VDD and the second node N 32 . The plurality of first capacitors  46   l ˜ 46   k  are connected to the power supply voltage VDD, and the plurality of first switches SW 6   l ˜SW 6   k  are connected to the second node N 32 . Each of the first switches SW 6   l ˜SW 6   k  are coupled to a corresponding bit of the first switching control signal SCS 6  and each of the first capacitors  46   l ˜ 46   k  may have a same capacitance. 
     The second sampling bank  470  includes a plurality of second switches SW 7   l ˜SW 7   k  each connected in series with corresponding ones of a plurality of second capacitors  47   l ˜ 47   k . Each series connected pair of the plurality of second switches SW 7   l ˜SW 7   k  and the plurality of second capacitors  47   l ˜ 47   k  are connected in parallel to the second node N 32  and the ground voltage GND. The plurality of second switches SW 7   l ˜SW 7   k  are connected to the second node N 32 , and the plurality of second capacitors  47   l ˜ 47   k  are connected to the ground voltage GND. Each of the second switches SW 7   l ˜SW 7   k  are coupled to a corresponding bit of the second switching control signal SCS 7  and each of the second capacitors  47   l ˜ 47   k  may have a same capacitance. 
     In other embodiments, each of the first sampling bank  460  and the second sampling bank  470  may be implemented with a variable capacitor. 
     The ratio of the first portion of the secondary bias voltage VBNS stored in the first capacitors  46   l ˜ 46   k  and the second portion of the secondary bias voltage VBNS stored in the second capacitors  47   l ˜ 47   k  may be varied according to the combination of bits of the first switching control signal SCS 6  and bits of the second switching control signal SCS 7 . When it is assumed that the ground voltage GND includes little noise component because the ground voltage GND is stable, the magnitude of the AC component N_VBP of the bias voltage VBP may be adjusted by the ratio of the first portion of the secondary bias voltage VBNS stored in the sampling bank  460  and the second portion of the secondary bias voltage VBNS stored in the second sampling bank  470 . 
     Since the magnitude of the AC component N_VBP of the bias voltage VBP may be increased or decreased by the ratio of the first portion of the secondary bias voltage VBNS stored in the sampling bank  460  and the second portion of the secondary bias voltage VBNS stored in the second sampling bank  470 , the magnitude of the AC component N_VBP of the bias voltage VBP based on the second current I 2  is also increased or decreased, and the third noise component N_VREF of the reference voltage VREF may also be adjusted accordingly. 
     In  FIG. 11 , the sampling control signal SPC 2 , the first switching control signal SCS 6  and the second switching control signal SCS 7  may be included in the third control signal CTL 3  provided from the control circuit  200 . 
       FIG. 12  illustrates a circuit diagram of another example of the bias voltage generator in  FIG. 2  according to an embodiment of the inventive concept. In  FIG. 12 , the ramp buffer  330  of  FIG. 8  is also illustrated with a bias voltage generator  400   d  for convenience of explanation. 
     Referring to  FIG. 12 , the bias voltage generator  400   d  includes a current source  401 , a switched current mirror  410   d , a current mirror  510  and a PMOS transistor  512 . 
     The current source  401  is connected between a first node N 41  and the ground voltage GND, and draws a first current I 1  having a constant magnitude. The switched current mirror  410   d  is connected to the power supply voltage VDD, the first node N 41 , the ground voltage GND and a third node N 43 , and outputs a second current I 2  proportional to the first current I 1  to the third node N 43  by mirroring first current I 1  when a sampling switch  409  therein is switched on. The current mirror  510  is connected to the third node N 43 , the ground voltage GND and the fourth node N 44 , and mirrors the second current I 2  to output the third current I 3  proportional to the second current I 2  to the fourth node N 44 . The PMOS transistor  512  includes a source connected to the power supply voltage VDD, and a gate and a drain connected to the fourth node N 44 . The PMOS transistor  512  provides the ramp buffer  330  with the bias voltage VBP based on the third current I 3 . 
     The switched current mirror  410   d  includes a PMOS transistor  418 , the sampling switch  409 , a first sampling bank  480 , a second sampling bank  490  and a PMOS transistor  419 . 
     The PMOS transistor  418  has a source coupled to the power supply voltage VDD, and a gate and a drain coupled to the first node N 41 . The sampling switch  409  is connected between the first node N 41  (a gate of the PMOS transistor  418 ) and the second node N 42 , and connects a voltage of the first node N 41  to the second node N 42  in response to a sampling control signal SPC 3 . The first sampling bank  480  is connected between the power supply voltage VDD and the second node N 42 , and samples a first portion of a voltage of the second node N 42  therein in response to a first switching control signal SCS 8 . The second sampling bank  490  is connected between the second node N 42  and the ground voltage GND, and samples a second portion of the voltage of the second node N 42  therein in response to a second switching control signal SCS 9 . The PMOS transistor  419  includes a gate coupled to the second node N 42 , a source coupled to the power supply voltage VDD and a drain coupled to the third node N 43 . 
     The first sampling bank  480  includes a plurality of first capacitors  48   l ˜ 48   k  each connected in series with corresponding ones of a plurality of first switches SW 8   l ˜SW 8   k . Each series connected pair of the plurality of first capacitors  48   l ˜ 48   k  and the plurality of first switches SW 8   l ˜SW 8   k  are connected in parallel to the power supply voltage VDD and the second node N 42 . The plurality of first capacitors  48   l ˜ 48   k  are connected to the power supply voltage VDD, and the plurality of first switches SW 8   l ˜SW 8   k  are connected to the second node N 42 . Each of the first switches SW 8   l ˜SW 8   k  are coupled to a corresponding bit of the first switching control signal SCS 8  and each of the first capacitors  48   l ˜ 48   k  may have a same capacitance. 
     The second sampling bank  490  includes a plurality of second switches SW 9   l ˜SW 9   k  each connected in series with corresponding ones of a plurality of second capacitors  49   l ˜ 49   k . Each series connected pair of the plurality of second switches SW 91 -SW 9   k  and the plurality of second capacitors  49   l ˜ 49   k  are connected in parallel to the second node N 42  and the ground voltage GND. The plurality of second switches SW 9   l ˜SW 9   k  are connected to the second node N 42 , and the plurality of second capacitors  49   l ˜ 49   k  are connected to the ground voltage GND. Each of the second switches SW 9   l ˜SW 9   k  are coupled to a corresponding bit of the second switching control signal SCS 9  and each of the second capacitors  49   l ˜ 49   k  may have a same capacitance. 
     In other embodiments, each of the first sampling bank  480  and the second sampling bank  490  may be implemented with a variable capacitor. 
     The current mirror  510  includes NMOS transistors  511  and  513 . The NMOS transistor  511  has a drain and a gate coupled to the third node N 43 , and a source coupled to the ground voltage GND. The NMOS transistor  513  has a drain coupled to the fourth node N 44 , a gate coupled to the third node N 43  and a source coupled to the ground voltage GND. 
     The ratio of a first portion of the voltage of the second node N 42  stored in the first capacitors  48   l ˜ 48   k  and a second portion of the voltage of the second node N 42  stored in the second capacitors  49   l ˜ 49   k  may be varied according to the combination of bits of the first switching control signal SCS 8  and bits of the second switching control signal SCS 9 . When it is assumed that the ground voltage GND includes little noise component because the ground voltage GND is stable, a magnitude of a noise component of the voltage of the second node N 42  may be adjusted by the ratio of the first portion of the voltage of the second node N 42  stored in the sampling bank  480  and the second portion of the voltage of the second node N 42  stored in the second sampling bank  490 . Since the magnitude of the noise component of the voltage of the second node N 42  may be increased or decreased by the ratio of the first portion of the voltage of the second node N 42  stored in the sampling bank  480  and the second portion of the voltage of the second node N 42  stored in the second sampling bank  490 , the magnitude of the AC component N_VBP of the bias voltage VBP based on the third current I 3  is also increased or decreased, and the third noise component N_VREF of the reference voltage VREF may also be adjusted accordingly. 
       FIG. 13  illustrates a diagram for explaining a concept of the present inventive concept. 
     In  FIG. 13 , the unit pixel  110   a  of  FIG. 3 , the ramp buffer  330  of  FIG. 8  and the comparator  325  of the CDS circuit  320  shown in  FIG. 7  are illustrated. 
     Referring to  FIG. 13 , the power supply voltage VDD to which the ramp buffer  330  is coupled includes the first noise component NP, and the bias voltage VBP which is applied to the first PMOS transistor  331  includes the AC component N_VBP. As described with reference to  FIGS. 9 through 12 , the bias voltage generator  400  adjusts the AC component N_VBP of the bias voltage VBP such that the magnitude of the third noise component N_VREF added to the reference voltage VREF which is output at the output node NO is substantially similar with the magnitude of a second noise component N_AS of the analog signal AS which is output from the unit pixel  110   a . The comparator  325  of the CDS circuit  320  compares the reference voltage VREF and the analog signal AS to output the comparison signal CMP, and the third noise component N_VREF added to the reference voltage VREF and the a second noise component N_AS of the analog signal AS cancel each other. Therefore, the comparison signal CMP includes none of the noise components. 
       FIG. 14  illustrates a timing diagram of operation of the row driver and the pixel array in the image sensor of  FIG. 2 . 
     Referring to  FIGS. 2, 3 and 14 , the row driver  220  may sequentially scan a plurality of rows of unit pixels  110  based on the first internal control signal ICTL 1  and the address signal ADDR, and may sequentially perform an electronic shutter operation to reset an electric signal already stored in each of the unit pixels  110  and a read-out operation to read-out the electric signal stored in each of the unit pixels  110 . The row driver  220  performs the electronic shutter operation and the read-out operation by applying the transfer control signal TX, the reset control signal RST and the selection control signal SEL. The electronic shutter operation may include a preliminary shutter operation and a main shutter operation which are sequentially performed on one row. The row driver  220  may overlap a period of the main shutter operation on a first row of the plurality of rows and a period of the preliminary shutter operation on a second row, different from the first row, of the plurality of rows. For example, at least a portion of the main shutter operation of the first row and the preliminary shutter operation on the second row may be overlapped, or the main shutter operation of the first row and the preliminary shutter operation on the second row may be overlapped with each other. The row driver  220  performs the electronic shutter operation to eliminate (reset) signal charges accumulated in the photo detector before performing the read-out operation. 
     In  FIG. 14 , each time interval t 11 ˜t 12 , t 12 ˜t 13 , t 13 ˜t 14  and t 14 ˜t 15  may correspond to one horizontal scanning time ( 1 H) required for the row driver  220  to scan one row. The row driver  220  may perform a preliminary shutter operation on one row within a first  1 H time and perform a main shutter operation on the one row within a second  1 H time after the first  1 H time. 
     In  FIG. 14 , an interval between times t 11 ˜t 13  may correspond to an electronic shutter interval during which the electronic shutter operation is performed, an interval between times t 13 ˜t 14  may correspond to an integration interval INT 3  during which electric signal is accumulated in the unit pixel  110 , and an interval between times t 14 ˜t 15  may correspond to a read-out interval INT 4  during which the read-out operation is performed. The electronic shutter interval includes a preliminary shutter interval INT 1  during which the preliminary shutter operation is performed and a main shutter interval INT 2  during which the main shutter operation is performed. 
       FIG. 15  illustrates a timing diagram for explaining the operation of the image sensor of  FIG. 1 . Hereinafter, the operation of the image sensor  10  of  FIG. 1  will be described with reference to  FIGS. 1 through 15 . 
     At a time t 21 , the row driver  220  provides the selection control signal SEL, which is activated to have a logic high level, to the pixel array  100  to select one of the rows included in the pixel array  100 . 
     At a time t 22 , the row driver  220  provides the reset control signal RST to the selected row. At this time, a pixel voltage signal Vpix output from the pixel array  100  may be the first analog signal AS 1  representing the reset component. 
     At a time t 23 , the timing controller  210  provides the count enable signal CNT_EN having the logic high level to the ramp signal generator  250 , and the ramp signal generator  250  starts to reduce the voltage level of the ramp signal VR at a constant slope (a). In addition, the timing controller  210  provides the count clock signal CLKC to the counter  340 , and the counter  340  performs the counting operation in synchronization with the count clock signal CLKC. 
     At a time t 24 , the ramp signal VR and the reset signal (i.e., the first analog signal AS 1  representing the reset component) have the same voltage level, and the comparison signal CMP output from the comparator  325  transits to a logic low level so that the counting operation is terminated. At this time, the counter  340  generates a first counting value CNT 1  corresponding to the reset signal RSTS. 
     At a time t 25 , the count enable signal CNT_EN is deactivated to have a logic low level, and the ramp signal generator  250  is disabled. The interval from the time t 23  to the time point t 25  may represent a maximum interval to count the reset signal, and may be appropriately set to correspond to a number of clock cycles according to the characteristics of the image sensor  10 . 
     At a time t 26 , the row driver  220  provides the transfer control signal TX to the selected row. At this time, a pixel voltage signal Vpix output from the pixel array  100  may be the second analog signal AS 2  representing the image component (i.e., the image signal). 
     At a time t 27 , the timing controller  210  provides again the count enable signal CNT_EN having a logic high level to the ramp signal generator  250 , and the ramp signal generator  250  starts to reduce the voltage level of the ramp signal VR at a constant slope (a) identical to the slope at the time t 23 . In addition, the timing controller  210  provides the count clock signal CLKC to the counter  340 , and the counter  340  performs the counting operation in synchronization with the count clock signal CLKC. 
     At a time t 28 , the ramp signal VR and the image signal have the same voltage level, and the comparison signal CMP output from the comparator  325  transits to a logic low level so that the counting operation is terminated. At this time, the counter  340  generates a second count value CNT 2  corresponding to the image signal IMGS. At this time, the comparison signal CMP includes none of noise components due to operations of the bias voltage generator  400  and the ramp buffer  330 . The counter  340  may output the digital signal DGS representing the effective component of the incident light by subtracting the first count value CNT 1  from the second count value CNT 2 . 
     At a time point t 29 , the count enable signal CNT_EN is deactivated to have a logic low level, the ramp signal generator  250  is disabled. The interval from the time t 27  to the time t 29  may represent a maximum interval to count the image signal, and may be appropriately set to correspond to a number of clock cycles according to the characteristics of the image sensor  10 . 
     At a time t 30 , the row driver  220  provides the selection control signal SEL, which is deactivated to have a logic low level, to the pixel array  100  to cancel the selection for the selected row. 
     After the time t 30 , the image sensor  10  repeats the above operation with respect to other rows to output the digital signal DGS in units of row. 
     As described above, the read-out circuit and the image sensor including the read-out circuit may cancel noise components by adjusting the noise component of the reference voltage to have a substantially the same magnitude as a magnitude of a noise component of the analog signal which is output from the unit pixel. 
       FIG. 16  illustrates a block diagram of one of the conversion circuits in  FIG. 2 . 
     Referring to  FIG. 16 , a conversion circuit  310   a  includes a CDS circuit  320   a , a pixel bias circuit  350  and a counter  340   a.    
     The pixel bias circuit  350  receives the bias voltage VBN and the cascade voltage VCN and generates a bias current IB for driving the unit pixel  110  and a third noise component N_ASB for cancelling the second noise component N_AS based on the bias voltage VBN. The pixel bias circuit  350  provides the bias current IB to the unit pixel  110  and provides the third noise component N_ASB to a pixel node to which the unit pixel  110  is coupled. 
     The CDS circuit  320   a  generates a reset signal corresponding to the reset component and an image signal corresponding to the signal component by performing the correlated double sampling on the first and second analog signals AS 1  and AS 2 , respectively based on the ramp signal VR. The pixel bias circuit  350  adjust an AC component of the bias voltage VBN such that the third noise component N_ASB cancels the second noise component N_AS. 
       FIG. 17  illustrates an example of the correlated double sampling circuit in  FIG. 16  according to an embodiment of the inventive concept. 
     Referring to  FIG. 17 , the CDS circuit  320   a  includes a comparator  321 , a first capacitor C 1 , a second capacitor C 2 , a first switch  321  and a second switch  323 . 
     The first switch  321  is connected to a pixel node PN and samples the first analog signal AS 1  or the second analog signal AS 2  in response to a first switching control signal S 1 , and selectively provides the first and second analog signals AS 1  and AS 2  to the first capacitor C 1 . The first capacitor C 1  is connected between the first switch  321  and a negative input terminal of the comparator  327 . The second switch  323  is connected between the negative input terminal of the comparator  327  and output terminal of the comparator  327 , and is opened/closed in response to a second switching control signal S 2 . The second capacitor C 2  is connected in parallel with the second switch  323 . 
     The ramp signal VR is applied to a positive input terminal of the comparator  327 . The CDS circuit  320   a  may determine voltage levels of the reset signal RSTS and the image signal IMGS, or in other words the comparison signal, based on the ramp signal VR. The third noise component N_ASB is provided to the pixel node PN and the second noise component N_AS of the first analog signal AS 1  or the second analog signal AS 2  is cancelled by the third noise component N_ASB at the pixel node PN. 
       FIG. 18  illustrates a circuit diagram of the pixel bias circuit in the conversion circuit of  FIG. 16  according to an embodiment of the inventive concept. 
     Referring to  FIG. 18 , the pixel bias circuit  350  includes NMOS transistors  351  and  353  connected in series between the pixel node PN and the ground voltage GND. 
     The NMOS transistor  351  includes a drain coupled to the pixel node PN, a gate coupled to the cascode voltage VCN and a source coupled to the NMOS transistor  353 . The NMOS transistor  353  has a drain coupled to the NMOS transistor  351 , a gate coupled to the bias voltage VBN and a source coupled to the ground voltage GND. 
     When the cascode voltage VCN is at a high level, a magnitude of the bias current IB which flows through the NMOS transistor  353  may be adjusted by the bias voltage VBN. In addition, the magnitude of the third noise component N_ASB may be adjusted by an AC component of the bias voltage VBN. Since a phase of the third noise component N_ASB is opposite to a phase of the second noise component N_AS, the third noise component N_ASB is adjusted to calcel the second nosie component N_AS. The pixel node PN is coupled to the unit pixel  110  through a column line CL. 
       FIG. 19  illustrates a circuit diagram of another example of the bias voltage generator in  FIG. 2  according to an embodiment of the inventive concept. 
     In  FIG. 19 , the pixel bias circuit  350  of  FIG. 18  is also illustrated with a bias voltage generator  400   e  for convenience of explanation. 
     Referring to  FIG. 19 , the bias voltage generator  400   e  includes a current source  401 , a current mirror  520   a , an NMOS transistor  523 , a sampling switch  524  and a tuning bank  530 . 
     The current source  401  is connected between a first node N 51  and the ground voltage GND, and draws a first current I 1  having a constant magnitude. The current mirror  520   a  is connected to the power supply voltage VDD, the first node N 51 , and a second node N 52  and outputs a second current I 2  having a same magnitude as the first current I 1  to the second node N 52  by mirroring the first current I 1 . The drain and gate of the NMOS transistor  523  are coupled to the second node N 52  and the source of the NMOS transistor  532  is coupled to the ground voltage GND. 
     The sampling switch  524  is connected between the second node N 52  and a third node N 53 , and connects a voltage V 52  due to the second current I 2  to the third node N 53 , in response to a sampling control signal SPC 4 . The tuning bank  530  is connected to the power supply voltage VDD, the ground voltage GND and the third node N 53 , stores a portion of the voltage V 52  therein in response to a tuning control signal TCS 1  and provides the pixel bias circuit  350  with the stored voltage as the bias voltage VBN. 
     The tuning bank  530  includes a plurality of PMOS transistors  531 ,  533 , and  535 , a plurality of NMOS transistors  532 ,  534  and  536  and a plurality of capacitors  537 ,  538  and  539 . The capacitors  537 ,  538  and  539  may be connected in parallel between the third node N 53  and each of nodes (or, connection nodes) N 54 , N 55  and N 56 . Each of the PMOS transistors  531 ,  533 , and  535  is connected to the power supply voltage VDD and to each of the nodes N 54 , N 55  and N 56 , and each of the NMOS transistors  532 ,  534  and  536  is connected to the ground voltage GND and to each of the nodes N 54 , N 55  and N 56 . Each parallel connected pair of PMOS transistors  531 ,  533 , and  535  and the NMOS transistors  532 ,  534  and  536  are alternatively turned-on/off in response to respective bit of the tuning control signal TCS 1  and thus, the voltage V 52  is stored in at least some of the capacitors  537 ,  538  and  539 . 
     The capacitors  537 ,  538  and  539  have respective capacitances with a ratio of 1:2:4 with respect to one another and each parallel connected pair of PMOS transistors  531 ,  533 , and  535  and the NMOS transistors  532 ,  534  and  536  are alternatively turned-on/off in response to respective bit of the tuning control signal TCS 1 . Therefore, the tuning bank  530  adjusts the magnitude of the bias voltage VBN stored therein according to bits of the tuning control signal TCS 1 , and adjusts the magnitude of an AC component N_VBN of the bias voltage VBN. Therefore, the pixel bias circuit  350  may adjust the magnitude of the third nose component N_ASB substantially same as the magnitude of the second nose component N_AS. 
     The tuning bank  530  may further include a reserve capacitor CDEF connected between the third node N 53  and the ground voltage GND. The reserve capacitor CDEF stores the voltage V 52  without regard to the tuning control signal TCS 1 . 
     In  FIG. 19 , the sampling control signal SPC 4  and the tuning control signal TCS 1  may be included in the third control signal CTL 3  provided from the control circuit  200 . 
       FIG. 20  illustrates a circuit diagram of another example of the bias voltage generator in  FIG. 2  according to an embodiment of the inventive concept. 
     In  FIG. 20 , the pixel bias circuit  350  of  FIG. 18  is also illustrated with a bias voltage generator  400   f  for convenience of explanation. 
     Referring to  FIG. 20 , the bias voltage generator  400   f  includes a current source  401 , a switched current mirror  520   b , an NMOS transistor  528  and a second tuning bank  550 . 
     The current source  401  is connected between a first node N 61  and the ground voltage GND, and draws a first current I 1  having a constant magnitude. 
     The switched current mirror  520   b  is connected to the power supply voltage VDD, the first node N 61 , and a seventh node N 67  and outputs a second current I 2  having a same magnitude as the first current I 1  to the seventh node N 67  by mirroring the first current I 1  when a sampling switch  526  therein is connected. The switched current mirror  520   b  includes a PMOS transistor  525 , the sampling switch  526 , a first tuning bank  540  and a PMOS transistor  527 . 
     The PMOS transistor  525  includes a source coupled to the power supply voltage VDD and a gate and a drain coupled to the first node N 61 . The sampling switch  526  is coupled to the first node N 61  and a second node N 62 , and provides a voltage of the first node N 61  to the second node N 62  in response to the sampling control signal SPC 5 . The first tuning bank  540  is connected to the power supply voltage VDD, the ground voltage GND, the second node N 62  and a gate of the PMOS transistor  527 , stores a portion of the voltage at the second node N 62  therein in response to a tuning control signal TCS 2  and provides the gate of the PMOS transistor  527  with the stored voltage as a secondary bias voltage VBPS. 
     The first tuning bank  540  includes a plurality of PMOS transistors  541 ,  543 , and  545 , a plurality of NMOS transistors  542 ,  544  and  546  and a plurality of capacitors  547 ,  548  and  549 . The capacitors  547 ,  548  and  549  may be connected in parallel between the second node N 62  and each of nodes N 63 , N 64  and N 65 . Each of the PMOS transistors  541 ,  543 , and  545  is connected to the power supply voltage VDD and to each of the nodes N 63 , N 64  and N 65 , and each of the NMOS transistors  542 ,  544  and  546  is connected to the ground voltage GND and to each of the nodes N 63 , N 64  and N 65 . Each parallel connected pair of PMOS transistors  541 ,  543 , and  545  and the NMOS transistors  542 ,  544  and  546  are alternatively turned-on/off in response to respective bit of the tuning control signal TCS 2  and thus, the voltage of the second node N 62  is stored in at least some of the capacitors  547 ,  548  and  549 . 
     The capacitors  547 ,  548  and  549  have respective capacitances with a ratio of 1:2:4 with respect to each other and each parallel connected pair of PMOS transistors  541 ,  543 , and  545  and the NMOS transistors  542 ,  544  and  546  are alternatively turned-on/off in response to respective bit of the tuning control signal TCS 2 . Therefore, the first tuning bank  540  adjusts the magnitude of the secondary bias voltage VBPS stored therein according to bits of the tuning control signal TCS 2 , and adjusts the magnitude of an AC component N_VBPS of the secondary bias voltage VBPS. Therefore, the pixel bias circuit  350  may adjust the magnitude of the third nose component N_ASB substantially same as the magnitude of the second nose component N_AS. 
     The PMOS transistor  527  includes a source coupled to the power supply voltage VDD, a gate coupled to the first tuning bank  540  and a drain coupled to the seventh node N 67 . The PMOS transistor  527  provides the second current I 2  at the drain. 
     The drain and gate of the NMOS transistor  528  are coupled to the seventh node N 67  and the source of the NMOS transistor  538  is coupled to the ground voltage GND. 
     The second tuning bank  550  is connected to the power supply voltage VDD, the ground voltage GND and the pixel bias circuit  350 , stores a portion of a voltage of the seventh node N 67  therein in response to a tuning control signal TCS 3  and provides the pixel bias circuit  350  with the stored voltage as the bias voltage VBN. 
     The second tuning bank  550  includes a plurality of PMOS transistors  551 ,  553 , and  535 , a plurality of NMOS transistors  552 ,  554  and  556  and a plurality of capacitors  557 ,  558  and  559 . The capacitors  557 ,  558  and  559  may be connected in parallel between the seventh node N 67  and each of nodes (connection nodes) N 671 , N 672  and N 673 . Each of the PMOS transistors  551 ,  553 , and  555  is connected to the power supply voltage VDD and to each of the nodes N 671 , N 672  and N 673  and each of the NMOS transistors  552 ,  554  and  556  is connected to the ground voltage GND and to each of the nodes N 671 , N 672  and N 673 . Each parallel connected pair of PMOS transistors  551 ,  553 , and  555  and the NMOS transistors  552 ,  554  and  556  are alternatively turned-on/off in response to respective bit of the tuning control signal TCS 3  and thus, the voltage of the seventh node N 67  caused by the second current I 2  is stored in at least some of the capacitors  557 ,  558  and  559 . 
     The capacitors  557 ,  558  and  559  have respective capacitances with a ratio of 1:2:4 with respect to each other and each parallel connected pair of PMOS transistors  551 ,  553 , and  555  and the NMOS transistors  552 ,  554  and  556  are alternatively turned-on/off in response to respective bit of the tuning control signal TCS 3 . Therefore, the second tuning bank  550  adjusts the magnitude of the bias voltage VBN stored therein according to bits of the tuning control signal TCS 1 , and adjusts a phase of an AC component of the bias voltage VBN. Therefore, the pixel bias circuit  350  may adjust the phase of the third nose component N_ASB substantially opposite to the phase of the second nose component N_AS. 
     That is, in the bias voltage generator  400   f  of  FIG. 20 , the first tuning bank  540  adjusts the magnitude of the third nose component N_ASB and the second tuning bank  550  adjusts the phase of the third nose component N_ASB such that the second noise component N_AS is cancelled by the third nose component N_ASB. 
     In  FIG. 20 , the sampling control signal SPC 5  and the tuning control signals TCS 2  and TCS 3  may be included in the third control signal CTL 3  provided from the control circuit  200 . 
       FIG. 21  illustrates a circuit diagram of another example of the bias voltage generator in  FIG. 2  according to an embodiment of the inventive concept. 
     In  FIG. 21 , the pixel bias circuit  350  of  FIG. 18  is also illustrated with a bias voltage generator  400   g  for convenience of explanation. 
     Referring to  FIG. 21 , the bias voltage generator  400   g  includes a current source  401 , a switched current mirror  560 , a current mirror  270 , an NMOS transistor  581 , and a third tuning bank  582 . 
     The current source  401  is connected between the power supply voltage VDD and a first node N 71 , and provides a first current I 1  having a constant magnitude to the first node N 71 . 
     The switched current mirror  560  is connected to the first node N 71 , the ground voltage GND and the second node N 72 , and draws a second current I 2  having a same magnitude as the first current I 1  from the second node N 72  by mirroring the first current I 1  when a sampling switch  562  therein is connected. The switched current mirror  560  includes an NMOS transistor  561 , the sampling switch  562 , a first tuning bank  563  and an NMOS transistor  564 . 
     The NMOS transistor  561  has a drain and a gate coupled to the first node N 71  and a source connected to the ground voltage GND. The sampling switch  562  is coupled to the first node N 71  and the first tuning bank  563 , and provides a voltage of the first node N 71  to the first tuning bank  563  in response to the sampling control signal SPC 6 . The first tuning bank  563  is connected to the sampling switch  562  and a gate of the NMOS transistor  564 , stores a portion of the voltage at the first node N 71  therein in response to a tuning control signal TCS 4  and provides the gate of the NMOS transistor  564  with the stored voltage as a first secondary bias voltage VBNS. 
     The first tuning bank  563  may have a same configuration as the first tuning bank  540  in  FIG. 20 . Therefore, the portion of the voltage of the first node N 71  is stored in the first tuning bank  563  according to the bits of the tuning control signal TCS 4 , a magnitude of an AC component N_VBNS of the first secondary bias voltage VBNS is adjusted according to the tuning control signal TCS 4 , and a magnitude of the third noise component N_ASB is adjusted. 
     The NMOS transistor  564  includes a drain coupled to the second node N 72 , a gate coupled to the first tuning bank  563  and a drain coupled to the ground voltage GND. The NMOS transistor draws the second current I 2  from the second node N 72 . 
     The current mirror  570  is connected to the power supply voltage VDD, the second node N 72  and a third node N 73 . The current mirror  570  includes a PMOS transistor  571 , a second tuning bank  572  and a PMOS transistor  573 . The current mirror  570  provides a third current I 3  having a same magnitude as the second current I 2  to the third node N 73  by mirroring the second current I 2 . 
     The PMOS transistor  571  includes a source coupled to the power supply voltage VDD, and a gate and a drain coupled to the second node N 72 . Therefore, a voltage of the second node N 72  caused by the second current I 2  is provided to the second tuning bank  572 . The second tuning bank  572  is connected to the second node N 72  and a gate of the PMOS transistor  573 , stores a portion of the voltage of the second node N 72  therein in response to a tuning control signal TCS 5  and provides the gate of the PMOS transistor  573  with the stored voltage as a second secondary bias voltage VBPS. The second tuning bank  572  may have a same configuration as the second tuning bank  550  in  FIG. 20 . Therefore, the portion of the voltage of the second node N 72  is stored in the second tuning bank  572  according to the bits of the tuning control signal TCS 5 , a magnitude of an AC component of the second secondary bias voltage VBPS is adjusted according to the tuning control signal TCS 5 , and a phase of the third noise component N_ASB is adjusted. 
     The PMOS transistor  573  includes a source coupled to the power supply voltage VDD, a gate coupled to the second tuning bank  572  and a drain coupled to the third node N 73 . The PMOS transistor  573  provides the third current I 3  at the drain to the third node N 73 . 
     The drain and gate of the NMOS transistor  581  are coupled to the third node N 73  and the source of the NMOS transistor  581  is coupled to the ground voltage GND. Therefore, a voltage of the third node N 73  caused by the third current I 3  is provided to the third tuning bank  582 . 
     The third tuning bank  582  is connected to the third node N 73 , the ground voltage GND and the pixel bias circuit  350 , stores a portion of a voltage of the third node N 73  therein in response to a tuning control signal TCS 6  and provides the pixel bias circuit  350  with the stored voltage as the bias voltage VBN. The third tuning bank  582  may have a same configuration as the second tuning bank  550  in  FIG. 20 . Therefore, the portion of the third node N 73  is stored in the third tuning bank  582  according to the bits of the tuning control signal TCS 6 , a magnitude of an AC component of the bias voltage VBN is adjusted according to the tuning control signal TCS 6 , and a phase of the third noise component N_ASB is adjusted. Therefore, the pixel bias circuit  350  may adjust the phase of the third nose component N_ASB substantially opposite to the phase of the second nose component N_AS. 
     That is, in the bias voltage generator  400   g  of  FIG. 21 , the first tuning bank  563  adjusts the magnitude of the third nose component N_ASB and the second and third tuning banks  572  and  582  adjust the phase of the third nose component N_ASB such that the second noise component N_AS is cancelled by the third nose component N_ASB. 
     In  FIG. 21 , the sampling control signal SPC 6  and the tuning control signals TCS 4 , TCS 5  and TCS 6  may be included in the third control signal CTL 3  provided from the control circuit  200 . 
       FIG. 22  illustrates a diagram for explaining operation of the comparator in  FIG. 17  according to the present inventive concept. 
     In  FIG. 22 , the unit pixel  110   a  of  FIG. 3 , the comparator  327  in  FIG. 17  and the pixel bias circuit  330  of  FIG. 18  are illustrated. 
     Referring to  FIG. 22 , the power supply voltage VDD to which unit pixel  110   a  is coupled includes the first noise component NP, and the analog signal AS output from the unit pixel  110   a  includes the second noise component N_AS. As described with reference to  FIGS. 19 through 21 , the bias voltage generator  400   e ,  400   f  or  400   g  adjusts the AC component N_VBN of the bias voltage VBN to adjust the magnitude and/or the phase of the third noise component N_ASB which is output from the pixel bias circuit  350  to the pixel node PN such that the second noise component N_AS output from the unit pixel  110   a  is cancelled by the third noise component N_ASB. The comparator  327  of the CDS circuit  320   a  compares the ramp signal VR and the analog signal AS to output the comparison signal CMP, and the second noise component N_AS added to the analog signal AS and the second noise component N_ASB from the pixel bias circuit  350  cancel each other. Therefore, the comparison signal CMP includes none of the noise components. 
       FIG. 23  illustrates a block diagram of an example of a camera including the image sensor according to an embodiment of the inventive concept. 
     Referring to  FIG. 23 , a camera  600  includes a receiving lens  610 , an image sensor chip  605  and a control engine  640 . The image sensor chip  605  includes an image sensor  620  and a light source module  630 . The light source module  630  includes a light source  631  and a lens  632 . 
     The image sensor  620  may employ the image sensor  10  of  FIG. 2 . The receiving lens  610  may focus incident light on a photo-receiving region (e.g., the pixel array  100  in  FIG. 2 ) of the image sensor  620 . The image sensor  620  may generate data DATA 1  including depth information and/or color image information based on the incident light passing through the receiving lens  610 . The image sensor  620  may provide the data DATA 1  to the control engine  640  in response to a clock signal CLK. In some embodiments, the image sensor  620  may interface with the control engine  640  using a mobile industry processor interface (MIPI) and/or a camera serial interface (CSI). 
     The control engine  640  may control the image sensor chip  605 . The control engine  640  may process the data DATA 1  received from the image sensor  620 . For example, the control engine  640  may generate color data based on the received data DATA 1 . The control engine  640  may be coupled to a host/application  650 , and may provide data DATA 2  to the host/application  650  based on a master clock signal MCLK. In some embodiments, the control engine  640  may interface with the host/application  650  using a serial peripheral interface (SPI) and/or an inter integrated circuit (I2C) interface. 
     Embodiments of the inventive concept can be applied to various image sensor and various imaging systems. For instance, embodiments of the inventive concept can be applied to a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a personal computer, a server computer, a workstation, a notebook, a digital television, a set-top box, a music player, a portable game console and a navigation system, or the like. 
     The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.