Patent Publication Number: US-2005122134-A1

Title: Level shifter and flat panel display

Description:
CROSS REFERENCE TO RELATED APPLICATION  
      This application claims priority to and the benefit of Korea Patent Application No. 10-2003-0085082 filed on Nov. 27, 2003 in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.  
     BACKGROUND OF THE INVENTION  
      (a) Field of the Invention  
      The present invention relates to a level shifter and a flat panel display.  
      (b) Description of the Related Art  
      A voltage level shifter is required in the design of a semiconductor integrated circuit (IC) so as to provide an interface between circuits which need different voltage levels. For example, an IC such as a DRAM operates within the range of a given voltage, but it may further require a signal voltage of greater than the range of a given voltage in order to interface with external circuits or provide signals to other circuits.  
      The level shifter used for the above-described case is a circuit which is provided between two systems with different magnitudes of signal voltages, and modifies the magnitudes of signal voltages to thus couple the two systems. In particular, the level shifter is used when modifying the magnitudes of the signal voltages from a range of a small voltage to that of a large voltage.  
       FIG. 1  shows a circuit diagram of a conventional level shifter.  
      As shown, the conventional level shifter comprises two PMOS transistors MP 1  and MP 2 , two NMOS transistors MN 1  and MN 2 , two output terminals OUTA and OUTB, and two input terminals INA and INB.  
      The voltage levels of signals outputted through the output terminals OUTA and OUTB differ according to variation of logic states of signals inputted through the input terminals INA and INB in the above-configured level shifter.  
      The conventional level shifter requires an additional ground line since sources (or drains) of the NMOS transistors MN 1  and MN 2  operable by the input signals INA and INB are grounded. Also, power consumption is increased when the NMOS transistors MN 1  and MN 2  are turned off since Off currents flow to the ground terminal through the NMOS transistors MN 1  and MN 2 . It is therefore desirable to provide a level shifter that overcomes the above-described shortcomings of the prior art while retaining their advantages.  
     SUMMARY OF THE INVENTION  
      It is an aspect of the present invention to minimize power consumption in a level shifter.  
      It is another aspect of the present invention to provide a flat panel display using a level shifter of the present invention.  
      In one exemplary embodiment according to the present invention, a level shifter is provided. The level shifter includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is operable by an applied first input signal and is for supplying a second input signal to a first main electrode of the first transistor. The second transistor is operable by an applied second input signal and is for supplying a first input signal to a first main electrode of the second transistor. The third transistor has a first main electrode coupled to a second main electrode of the first transistor and is operable by a signal outputted by the second transistor. The fourth transistor has a first main electrode coupled to a second main electrode of the second transistor and is operable by a signal output by the first transistor. A first output signal is outputted through a first node where the second main electrode of the second transistor and the first main electrode of the fourth transistor are coupled, and a second output signal is outputted through a second node where the second main electrode of the first transistor and the first main electrode of the third transistor are coupled.  
      When the second transistor is turned off, the first and second main electrodes of the second transistor may change with each other according to the first input signal, and the Off current of the second transistor may be outputted to the direction of the first node. When the first transistor is turned off, the first and second main electrodes of the first transistor may change with each other according to the second input signal, and the Off current of the first transistor may be outputted in the direction of the second node.  
      The first and second transistors may be NMOS transistors, and the third and fourth transistors may be PMOS transistors, or the first and second transistors may be CMOS transistors, and the third and fourth transistors may be PMOS transistors. The second main electrodes of the third and fourth transistors may be coupled to a power supply voltage.  
      The first and second transistors may be PMOS transistors, and the third and fourth transistors may be NMOS transistors, or the first and second transistors may be CMOS transistors, and the third and fourth transistors may be NMOS transistors. The second main electrodes of the third and fourth transistors may be grounded.  
      The second input signal may be an inverted signal of the first input signal. The first and second output signals may have an inverted relationship. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
      The accompanying drawings, together with the specification, illustrate exemplary embodiments of the present invention, and, together with the description, serve to explain the principles of the present invention:  
       FIG. 1  shows a circuit diagram of a conventional level shifter;  
       FIG. 2  shows a circuit diagram of a level shifter according to a first exemplary embodiment of the present invention;  
       FIG. 3  shows a circuit diagram of a level shifter according to a second exemplary embodiment of the present invention;  
       FIG. 4  shows a circuit diagram of a level shifter according to a third exemplary embodiment of the present invention;  
       FIG. 5  shows a circuit diagram of a level shifter according to a fourth exemplary embodiment of the present invention; and  
       FIG. 6  shows a configuration diagram of a flat panel display using a level shifter according to an exemplary embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION  
      In the following detailed description, only certain exemplary embodiments of the present invention are shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive.  
       FIG. 2  shows a circuit diagram of a level shifter according to a first exemplary embodiment of the present invention.  
      As shown, the level shifter includes two PMOS transistors MP 21  and MP 22 , two NMOS transistors MN 21  and MN 22 , two output terminals OUT 2 A and OUT 2 B, and two input terminals IN 2 A and IN 2 B.  
      In detail, a drain of the transistor MP 21  is coupled to a gate of the transistor MP 22  and a first main electrode (a drain or a source) of the transistor MN 21 , and a drain of the transistor MP 22  is coupled to a gate of the transistor MP 21  and a first main electrode (a drain or a source) of the transistor MN 22 . A power supply voltage VDD 2  is supplied to a source of the transistor MP 21  and a source of the transistor MP 22 .  
      In these coupled states of the first exemplary embodiment, a first input signal of the input terminal IN 2 A can be provided to the gate of the transistor MN 21  and a second main electrode (a source or a drain) of the transistor MN 22 , and a second input signal of the input terminal IN 2 B, which is an inverted signal of the first input signal of the input terminal IN 2 A, can be provided to the gate of the transistor MN 22  and a second main electrode (a source or a drain) of the transistor MN 21 . A first output signal of the output terminal OUT 2 A can be outputted through the drain of the transistor MP 22 , and a second output signal of the output terminal OUT 2 B can be outputted through the drain of the transistor MP 21  coupled to the gate of the transistor MP 22 .  
      An operation of the level shifter of  FIG. 2  according to the first exemplary embodiment of the present invention will now be described.  
      When an external first input signal of the input terminal IN 2 A is applied to the gate of the transistor MN 21 , and a second input signal of the input terminal IN 2 B, which is an inverted signal of the first input signal of the input terminal IN 2 A, is applied to the gate of the transistor MN 22 , output signals of the output terminals OUT 2 A and OUT 2 B (having undergone the level shift process) are outputted from the drains of the transistors MP 22  and MP 21 , respectively.  
      In detail, since the second input signal of the input terminal IN 2 B is a low level “L” signal when the first input signal of the input terminal IN 2 A is a high level “H” signal (the first operation mode), the transistor MN 21  is turned on and the transistor MN 22  is turned off. Hence, a low level signal is applied to the gate of the transistor MP 22 ; the transistor MP 22  is turned on; the current corresponding to the power supply voltage VDD 2  flows through the transistor MP 22 ; and accordingly, a high level first output signal of the output terminal OUT 2 A is outputted, and a low level second output signal of the output terminal OUT 2 B is outputted through a node  200  at which the drain of the transistor MP 21  and the first main electrode of the transistor MN 21  are coupled.  
      Since the gate of the transistor MN 21  and the second main electrode of the transistor MN 22  are coupled to the input terminal IN 2 A, the first and second main electrodes of the transistor MN 22  are changed with each other when the first input signal of the input terminal IN 2 A is a high level “H” signal and the second input signal of the input terminal IN 2 B is a low level “L” signal. That is, when the first main electrode of the transistor MN 22  is the drain and the second main electrode thereof is the source, the first main electrode is changed to become a source and the second main electrode is changed to become a drain. Accordingly, when the transistor MN 22  is turned off because of the low level second input signal of the input terminal IN 2 B, the Off current of the transistor MN 22  flows in the direction to a second node  210  where the output terminal OUT 2 A is coupled. As a result, since the Off current is added to the first output signal of the output terminal OUT 2 A, and they are outputted, the power consumption caused by the Off current is reduced.  
      By contrast, since the second input signal of the input terminal IN 2 B is a high level “H” signal when the first input signal of the input terminal IN 2 A is a low level “L” signal the transistor MN 21  is turned off and the transistor MN 22  is turned on. Thus, since now a low level signal is applied to the gate of the transistor MP 21  and the transistor MP 21  is turned on, the current corresponding to the power supply voltage VDD 2  flows through the transistor MP 21 ; a high level second output signal of the output terminal OUT 2 B is outputted; and a low level first output signal of the output terminal OUT 2 A′ is outputted through the second node  210  at which the drain of the transistor MP 22  and the first main electrode of the transistor MN 22  are coupled.  
      Similar to the first operation mode, since the gate of the transistor MN 22  and the second main electrode of the transistor MN 21  are coupled to the input terminal IN 2 B, the first and second main electrodes of the transistor MN 21  are changed with each other when the first input signal of the input terminal IN 2 A is a low level “L” signal and the second input signal of the input terminal IN 2 B is a high level “H” signal. Accordingly, when the transistor MN 21  is turned off because of the low level first input signal of the input terminal IN 2 A, the Off current of the transistor MN 21  flows in the direction to the node  200  where the output terminal OUT 2 B is coupled. As a result, since the Off current is added to the second output signal of the output terminal OUT 2 B, and they are outputted, the power consumption caused by the Off current is reduced.  
       FIG. 3  shows a circuit diagram of a level shifter according to a second exemplary embodiment of the present invention.  
      As shown, the level shifter includes two PMOS transistors MP 31  and MP 32 , two NMOS transistors MN 31  and MN 32 , two output terminals OUT 3 A and OUT 3 B, and two input terminals IN 3 A and IN 3 B.  
      In operation, a first input signal of the input terminal IN 3 A is provided to a gate of the transistor MP 31  and a first main electrode (a drain or a source) of the transistor MP 32 , and a second input signal of the input terminal IN 3 B is provided to a gate of the transistor MP 32  and a first main electrode (a drain or a source) of the transistor MP 31 . A source of the transistor MN 31  is coupled to the gate of the transistor MN 32  and a second main electrode (a source or a drain) of the transistor MP 31 , and a source of the transistor MN 32  is coupled to the gate of the transistor MN 31  and a second main electrode (a source or a drain) of the transistor MP 32 . In these coupled states of the second exemplary embodiment, a first output signal of the output terminal OUT 3 A is outputted through the second main electrode of the transistor MP 32  coupled to the gate of the transistor MN 31 , and a second output signal of the output terminal OUT 3 B is outputted through the second main electrode of the transistor MP 31  coupled to the gate of the transistor MN 32 .  
      When the first input signal of the input terminal IN 3 A is a low level signal, the first and second main electrodes of the transistor MP 32  are changed, and hence, when the transistor MP 32  is turned off according to the high level second input signal of the input terminal IN 3 B, the Off current of the transistor MP 32  flows in the direction to a node  300  where the output terminal OUT 3 A is coupled and is added to the first output signal of the output terminal OUT 3 A. Therefore, the power consumption caused by the Off current is reduced.  
      By contrast, when the second input signal of the input terminal IN 3 B is a low level signal, the first and second main electrodes of the transistor MP 31  are changed, and hence, when the transistor MP 31  is turned off according to the high level first input signal of the input terminal IN 3 A, the Off current of the transistor MP 31  flows in the direction to a second node  310  where the output terminal OUT 3 B is coupled and is added to the second output signal of the output terminal OUT 3 B. Therefore, the power consumption caused by the Off current is reduced.  
       FIG. 4  shows a circuit diagram of a level shifter according to a third exemplary embodiment of the present invention.  
      The configuration of the level shifter according to the third exemplary embodiment substantially corresponds to the level shifter of  FIG. 1  according to the first exemplary embodiment except, for example, that first and second input signals of the input terminals IN 4 A and IN 4 B are provided to CMOS (complementary metal oxide semiconductor) transistors. Hence, the level shifter of  FIG. 4  according to the third exemplary embodiment includes four PMOS transistors MP 41 , MP 42 , MP 43 , and MP 44  and two NMOS transistors MN 41  and MN 42 . The transistors MN 41  and MP 43  are referred to as first CMOS transistors, and the transistors MN 42  and MP 44  are referred to as second CMOS transistors.  
      In detail, drains of the transistors MP 41  and MP 42  are respectively coupled to first main electrodes (drains or sources) of the transistors MP 43  and MP 44  and Second main electrodes (drains or sources) of the transistors MP 43  and MP 44  are respectively coupled to first main electrodes (drains or sources) of the transistors MN 41  and MN 42 . A gate of the transistor MP 42  is coupled to a node  400  where the second main electrode of the transistor MP 43  and the first electrode of the transistor MN 41  are coupled. A gate of the transistor MP 41  is coupled to a second node  410  where the second main electrode of the transistor MP 44  and the first electrode of the transistor MN 42  are coupled. Also, the input terminal IN 4 A is coupled to the gates of the transistors MP 43  and MN 41  and a second main electrode of the transistor MN 42 , and the input terminal IN 4 B is coupled to the gates of the transistors MP 44  and MN 42  and a second main electrode of the transistor MN 41 .  
      In these coupled states of the third exemplary embodiment, when the first input signal of the input terminal IN 4 A is high level, the transistor MN 41  is turned on, the transistor MP 43  is turned off, and a low level signal is applied to the gate of the transistor MP 42 , and hence, the transistor MP 42  is turned on and a high-level first output signal of the output terminal OUT 4 A is outputted. The transistor MN 42  is turned off and the transistor MP 44  is turned on according to the low-level second input signal of the input terminal IN 4 B, and accordingly, a high level signal is applied to the gate of the transistor MP 41  and a low-level second output signal of the output terminal OUT 4 B is outputted at the drain of the transistor MP 41 . Since the high-level first input signal of the input terminal IN 4 A is coupled to the second main electrode of the transistor MN 42 , the first and second main electrodes of the transistor MN 42  are changed with each other, and the Off current of the transistor MN 42  flows in the direction to where the output terminal OUT 4 A is coupled  420  and is added to the first output signal of the output terminal OUT 4 A.  
      When the first input signal of the input terminal IN 4 A is low level, the transistor MP 41  is turned on, the transistor MP 42  is turned off, and a high-level second output signal OUT 4 B and a low-level first output signal OUT 4 A are outputted. Since the high-level second input signal of the input terminal IN 4 B is coupled to the second main electrode of the transistor MN 41 , the first and second main electrodes of the transistor MN 41  are changed with each other, and the Off current of the transistor MN 41  flows in the direction to where the output terminal OUT 4 B is coupled  430  and is added to the second output signal of the output terminal OUT 4 B.  
       FIG. 5  shows a circuit diagram of a level shifter according to a fourth exemplary embodiment of the present invention.  
      The configuration of the level shifter according to the fourth exemplary embodiment substantially corresponds to that of the level shifter of  FIG. 2  according to the second exemplary embodiment, and first and second input signals of respective input terminals IN 5 A and IN 5 B are inputted to CMOS transistors in substantially the same manner at the first and second input signals of respective input terminals IN 4 A and IN 4 B of  FIG. 4  of the third exemplary embodiment. Hence, the level shifter according to the fourth exemplary embodiment comprises four NMOS transistors MN 51 , MN 52 , MN 53 , and MN 54  and two PMOS transistors MP 51  and MP 52 .  
      In detail, first main electrodes (drains or sources) of the transistors MN 53  and MN 54  are coupled to sources of the transistors MN 51  and MN 52  with drains coupled to the ground voltage, and coupling nodes  500 ,  510  of the transistors MN 53  and MP 51  and the transistors MN 54  and MP 52  forming the CMOS transistors are respectively coupled to gates of the transistors MN 52  and MN 51 .  
      In these coupled states of the fourth exemplary embodiment, when the first input signal of the input terminal IN 5 A is high level, the transistor MN 53  is turned on, the transistor MP 51  is turned off, a low level signal is applied to the gate of the transistor MN 52 , and hence, the transistor MN 52  is turned off and the high-level first output signal of the output terminal OUT 5 A is outputted. The transistor MN 54  is turned off and the transistor MP 52  is turned on according to the low-level second input signal of the input terminal IN 5 B, and accordingly, a high level signal is applied to the gate of the transistor MN 51 , and a low-level second output signal of the output terminal OUT 5 B is outputted at the drain of the transistor MN 53 . Since the high-level first output signal of the output terminal OUT 5 A is coupled to the second main electrode of the transistor MP 52 , the Off current of the transistor MN 54  flows in the direction to where the output terminal OUT 5 A is coupled  520  and is added to the first output signal of the output terminal OUT 5 A.  
      When the first input signal of the input terminal IN 5 A is low level, the transistor MN 52  is turned on, the transistor MN 51  is turned off, and a low-level first output signal of the output terminal OUT 5 A and a high-level second output signal of the output terminal OUT 5 B are outputted. Since the high-level second input signal of input terminal IN 5 B is coupled to the second main electrode of the transistor MP 51 , the first and second main electrodes of the transistor MN 53  are changed with each other, and the Off current of the transistor MN 53  flows in the direction to where the output terminal OUT 5 B is coupled  530  and is added to the second output signal of output terminal OUT 5 B.  
      In the above described level shifters, it should be apparent to those skilled in the art that the voltage levels between ICs can be modified by applying the level shifters to the flat panel display using ICs with different voltage levels.  
       FIG. 6  shows a configuration diagram of a flat panel display using a level shifter according to an exemplary embodiment of the present invention.  
      The flat panel display comprises a timing controller Tcon  100 ′, a shift register S/R  200 ′, a data driver  300 ′, and a display panel  400 ′. The timing controller  100 ′ generates timing signals CLK, /CLK, and SP for driving the shift register  200 ′ and the data driver  300 ′. The shift register  200 ′ receives timing signals from the timing controller  100 ′ to sequentially apply scan signals to scan lines X 1  through Xm formed on the display panel  400 ′. The data driver  300 ′ applies data signals to data lines Y 1  through Yn of the display panel  400 ′ according to the timing signals.  
      For example, assuming that the voltage ranges used by the timing controller  100 ′ and the shift register  200 ′ are different, a level shifter L/S  500 ′ according to an embodiment is coupled between the timing controller  100 ′ and the shift register  200 ′ so that the output voltage range of the timing controller  100 ′ may be modified to a voltage range used by the shift register  200 ′.  
      In the like manner, assuming that the voltage ranges used by the shift register  200 ′ and the display panel  400 ′ are different, a level shifter L/S or level shifter L/Ss  600 ′ is (or are) formed between the shift register  200 ′ and the scan lines X 1  through Xm of the display panel  400 ′ so that the output voltage range of the shift register  200 ′ may be modified to a voltage range used by the display panel  400 ′. A buffer (not illustrated) which follows the voltage range used by the display panel  400 ′ may also be formed between the level shifter  500 ′ and the display panel  400 ′.  
       FIG. 6  shows a case for respectively using a level shifter or shifters between the timing controller  100 ′ and the shift register  200 ′ and between the shift register  200 ′ and the display panel  400 ′ for exemplary purposes only, and the invention is not restricted to this case, and the invention and the above description may be applied to other cases for modifying voltage ranges of the flat panel display.  
      In addition, it should be apparent to those skilled in the art that, in certain embodiments of the present invention, the power consumption caused by the Off current is minimized since the Off current of the transistor in the level shifter is included in the output signal. Also, simpler signal lines are formed since no additional ground line for the transistor operable by the input signal is required.  
      While this invention has been described in connection with certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalents included within the spirit and scope of the appended claims, and equivalent thereof.