Patent Publication Number: US-2009231045-A1

Title: Frequency-locking device and frequency-locking method thereof

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
     This application is a continuation-in-part of U.S. patent application Ser. No. 11/706,199, filed Feb. 15, 2007, now pending. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a frequency-locking device and, more particularly, to a frequency-locking device applied to universal serial bus. 
     2. Description of the Related Art 
     As shown in  FIG. 1 , a frequency-locking device  10  applied to data communication of a universal serial bus was disclosed in U.S. Pat. No. 6,297,705. When the frequency-locking device  10  is used, the output clock of an oscillator  142  is locked to the rate of incoming data stream which input to the frequency-locking device  10 . The object of this technology is to precisely lock the output clock of the oscillator  142  to the rate of the incoming data stream without utilizing any external precision timing element such as a crystal or a resonator, and provide multiple tuning phases during inputting a single data packet via coarse and/or fine tuning. 
     Referring to  FIG. 1 , the frequency-locking device  10  includes a control circuit  102  and an oscillator logic circuit  104 . The control circuit  102  receives an incoming data stream DATA and an input signal PACKET, and outputs a control signal CNTR and a correction signal FACTOR. The incoming data stream DATA are a series of data packets. The frequency-locking device  10  measures the incoming data stream DATA in advance to generate the correction signal FACTOR, and then the correction signal FACTOR is used to alter the oscillation frequency of the output signal OUT so that the frequency is locked to the rate of the incoming data stream DATA. 
     The control circuit  102  includes a control logic unit  103  and a counter circuit  106 . The control logic unit  103  outputs an adjustment signal C/F and a control signal CNTRS/S to the counter circuit  106 . Herein, the frequency-locking device  10  coarsely or finely tunes the oscillation frequency of the output signal OUT according to the adjustment signal C/F and the entire packet signal (the input signal PACKET). The control signal CNTRS/S is used to start or stop the counter circuit  106 . The counter circuit  106  includes a calibration circuit such as the start/stop counter  150  and a look-up table  152 . The look-up table  152  stores a fixed table of known characters in relation to adjustment of the oscillation frequency of the output signal OUT, and generates the correction signal FACTOR according to the adjustment signal C/F and the counts of the start/stop counter  150 . The correction signal FACTOR is then used to control an adjustment in the oscillation frequency of the output signal OUT. 
     The oscillator logic circuit  104  includes an oscillator control circuit  140  and an oscillator  142 . The oscillator logic circuit  104  receives the control signal CNTR and the correction signal FACTOR and generates the output signal OUT. The control signal CNTR is used in determination of whether the oscillation frequency of the output signal OUT is to be adjusted. The correction signal FACTOR represents an offset value (a multi-bit digital value) of a coarse tuning or a fine tuning for the oscillating signal DIGOUT. The oscillator  142  generates the output signal OUT according to the oscillating signal DIGOUT. 
     The coarse and fine tuning approach for the conventional frequency-locking device  10  is described as follows. First, the start/stop counter  150  performs a coarse tuning by counting a pre-determined number of edges of the input signal PACKET, feeding the counting value to the look-up table  152  for finding out a correction factor corresponding to the counting value so as to generate the correction signal FACTOR to an adder  163 . The adder  163  adds the value of the correction signal FACTOR to the originally set value ST and then sends the sum value to the oscillator setting unit  160  to generate the oscillating signal DIGOUT. Then, fine tuning is recurrently applied to the output signal OUT for a longer period of time to gain more precise adjustment. In other words, the start/stop counter  150  starts fine tuning when the coarse tuning is completed, and generates offset value by referring to the fine-tuning factors from the look-up table  152 , and adds or subtracts the value of the signal DIGOUT with the offset value according to the correction signal FACTOR. Thereby, the obtained oscillating frequency for the output signal OUT of the oscillator  142  fits the requirement, and the frequency of the output signal OUT is precisely locked to the rate of the incoming data stream. 
     However, the way of generating the correction signal FACTOR according to the data packets of the universal serial bus makes the actual design and operation of circuit more complicated and defective. Besides, the great amount of memory space occupied by the look-up table inside the frequency-locking device  10  increases the memory cost for the frequency-locking device  10 . The above-mentioned problems highly raise the manufacturing cost and the electricity consumption of the whole device. 
     SUMMARY OF THE INVENTION 
     In view of the above-mentioned problems, the present invention provides a frequency-locking device with advantages of low-producing cost, less-complicated design, and low electricity consumption. The frequency-locking device according to one embodiment of the invention includes a digitally-controlled oscillator and a comparing unit. The digitally-controlled oscillator is used to generate an output frequency signal. The comparing unit receives a KEEP ALIVE signal or a start of a frame and the output frequency signal, and then compares the KEEP ALIVE signal or the start of a frame with the output frequency signal to generate a calibration signal. The digitally-controlled oscillator performs an adjustment according to the calibration signal to lock the frequency of the output frequency signal to a specific or predetermined frequency for data communication. 
     On the other hand, a frequency-locking method is also provided. The method comprises the following steps. The first step is to receive a KEEP ALIVE signal. Then, it is the step of filtering noises of the KEEP ALIVE signal. Next, it is the step of comparing the filtered KEEP ALIVE signal with an output frequency signal to generate a calibration signal. Finally, it is the step of adjusting the output frequency signal according to the calibration signal so as to lock the frequency of the output frequency signal to a specific or predetermined frequency applied to data communication. 
     In the embodiments of the invention, the frequency-locking device and method thereof takes a KEEP ALIVE signal or a start of a frame as a reference for the calibration signal rather than takes a more complicated packet data as references for correction, and which shows a more precise frequency-locking effect. Also, the present invention does not need any look-up table. Consequently, the circuit design for the present invention becomes easier and the effect of reduced complexity in design, lowered production cost, and lowered electricity consumption can be obtained. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a schematic diagram illustrating a conventional frequency-locking device. 
         FIG. 2  shows a schematic diagram illustrating a universal serial bus device according to one embodiment of the invention. 
         FIG. 3A  shows a schematic diagram illustrating a frequency-locking device according to one embodiment of the invention. 
         FIG. 3B  shows a waveform diagram illustrating a standard KEEP ALIVE signal according to the low-speed USB 2.0 specification. 
         FIG. 3C  shows a schematic diagram illustrating a comparing unit according to one embodiment of the invention. 
         FIG. 3D  shows a schematic diagram illustrating a digitally-controlled oscillator according to one embodiment of the invention. 
         FIG. 4  shows a waveform diagram illustrating a real KEEP ALIVE signal according to low-speed USB 2.0 specification. 
         FIG. 5  shows a schematic diagram illustrating a frequency-locking device according to another embodiment of the invention. 
         FIG. 6  shows a flowchart illustrating a frequency-locking method according to one embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Reference will now be made to the drawings in which the various elements of the present invention will be given numerical designations and in which the invention will be discussed so as to enable one skilled in the art to make and use the invention. 
     Referring to  FIG. 2 , the universal serial bus device  20  according to one embodiment of the present invention receives the KEEP ALIVE signal KAS or the start of a frame SOF generated by a calculator such as a computer, and has data communication with the calculator. The universal serial bus device  20  includes a serial interface engine (SIE)  21  and a frequency-locking device  22 . Both the serial interface engine  21  and the frequency-locking device  22  receive a KEEP ALIVE signal KAS or a start of a frame SOF, and the frequency-locking device  22  generates an output frequency signal OF according to the KEEP ALIVE signal KAS or the start of a frame SOF. The frequency of the output frequency signal OF is locked to a specific or a predetermined frequency applied to the data communication between the calculator and the universal serial bus device  20 . The specific or the predetermined frequency is such as the communication frequency according to the low speed universal serial bus (USB) specification. Then, the output frequency signal OF is served as the operation frequency of data communication between the serial interface engine  21  and the calculator. It is to be noted that the generated output frequency signal OF has 1.5% frequency accuracy conforming to the low-speed USB 2.0 specification when the frequency-locking device  22  operates. 
     Referring to  FIG. 3A , the frequency-locking device  22  according to one embodiment of the invention includes a comparing unit  221  and a digitally-controlled oscillator  222 . The comparing unit  221  receives a KEEP ALIVE signal KAS or a start of a frame SOF and an output frequency signal OF generated by the digitally-controlled oscillator  222 , and generates a calibration signal S according to the comparison of the KEEP ALIVE signal KAS or the start of a frame SOF and the output frequency signal OF. The digitally-controlled oscillator  222  adjusts the frequency of the output frequency signal OF according to the calibration signal S. 
     Referring to  FIG. 3B , the standard KEEP ALIVE signal KAS used in the frequency-locking device  20  of the invention is based on the low-speed USB 2.0 specification and provided by the calculator for serving as a reference signal in the comparison to generate the calibration signal S. In this way, the frequency of the output frequency signal OF generated by the digitally-controlled oscillator  222  can be locked to a specific or predetermined frequency applied to communication of the universal serial bus device  20 . In another embodiment, the frequency-locking device of the invention can even be used to deal with signals based on present or future USB specification. For example, the frequency-locking device of the invention can be used to deal with signals based on a full-speed USB 2.0 specification. 
     Referring to  FIG. 3C , the comparing unit  221  according to one embodiment of the invention includes a counter  221   a , a registering unit  221   b , and a judging circuit  221   c . The counter  221   a  receives the KEEP ALIVE signal KAS or the start of a frame SOF and the output frequency signal OF, and starts or stops counting according to the KEEP ALIVE signal KAS, or counting one period of the frame. In one embodiment, referring to  FIG. 3B , the counter  221   a  starts or stops counting when the voltage level of the KEEP ALIVE signal KAS varies. For example, the counter  221   a  starts clock counting of the output frequency signal OF when voltage level of the KEEP ALIVE signal KAS changes from 1 to 0 at time t 0 , and the counter  221   a  stops clock counting of the output frequency signal OF when voltage level of the KEEP ALIVE signal KAS changes from 1 to 0 at time t 1 . In this way, the clock number V of the output frequency signal OF can be calculated out in one period of the KEEP ALIVE signal KAS. It is to be noted that the control way of starting and stopping the counter  221   a  is not limited to the voltage level change between 1 and 0 of the KEEP ALIVE signal KAS but can be another method such as employing an external control signal. 
     The registering unit  221   b  is used for temporarily storing the clock number V. The judging circuit  221   c  receives the clock number V, and determines whether the calibration signal S is to be updated according to the clock number V and a predetermined threshold value TH. It is to be noted that the threshold value TH is designed to positively correlate with the specific or predetermined frequency applied to data communication of the universal serial bus device  20 , the KEEP ALIVE signal KAS, and the operation frequency of the calculator. 
     For example, the threshold value TH is preset as 100 and a calibration range is set as 10. The value can be calibrated within the calibration range. At first, the counter  221   a  counts and the counted clock number V of the output frequency signal OF is 92 in one period of the KEEP ALIVE signal KAS. Then, the judging circuit  221   c  receives the clock number V from the registering unit  221   b  and compares the clock number V with the threshold value TH. The result shows there is a difference of 8. The judging circuit  221   c  compares the difference value with the calibration range, and, since the difference value of 8 is within the calibration range of 10, the output frequency signal OF is qualified to be calibrated. Accordingly, the judging circuit  221   c  updates the calibration signal S by increasing its value such as adding a value of 2 and outputs the calibration signal S to the digitally-controlled oscillator  222 . The clock number V of the output frequency signal OF then can be adjusted to be equal to the threshold value TH by repeating the above steps. Consequently, the frequency of the output frequency signal OF is locked to the specific or predetermined frequency applied to data communication of the universal serial bus device  20 , and thereby the operation frequency of the serial interface engine  21  is synchronized with the operation frequency of the calculator so as to normalize data communication between the universal serial bus  20  and the calculator. Further, in one embodiment, the judging circuit  221   c  may include two judging units  221   c   1  and  221   c   2 . The first judging unit  221   c   1  determines whether to update the calibration signal S according to the comparison result of the clock number V and the threshold value TH. The second judging unit  221   c   2  determines whether to update the calibration signal S according to the comparison result of the clock number V and the calibration range. The judging circuit  221   c  may include two judging units  221   c   1  and  221   c   2  in the same module as described above, or alternatively, the judging unit  221   c  may include only one judging unit in the same module to determine whether to update the calibration signal S according to the clock number V and the predetermined threshold value, based upon the designer&#39;s demand, concern over fabrication cost, or other factors. 
     Referring to  FIG. 3D , the digitally-controlled oscillator  222  according to one embodiment of the invention is a current controlled oscillator (ICO), including N (a positive integer) current sources, N switches, and at least one oscillator  222   a . The current sources provide N current flows of same or different magnitude such as the seven current sources of different magnitude  1 I 0 ,  2 I 0 ,  4 I 0 ,  8 I 0 ,  16 I 0 ,  32 I 0 ,  64 I 0  in  FIG. 3D . The switches B 0  to B 6  each is turned ON or turned OFF according to the calibration signal S. The oscillator  222   a  generates the output frequency signal OF according to the sum of current flows passing the switch B 0  to B 6 . 
     In some situations, the KEEP ALIVE signal KAS output from the calculator may includes noises such as the marked area NS of the KEEP ALIVE signal KAS′ shown in  FIG. 4 , and these noises NS may cause the comparing unit  221  to error. Therefore, as shown in  FIG. 5 , the frequency-locking device  22 ′ according to another embodiment of the invention is provided with a filtering unit  51  before the comparing unit  221 . The filtering unit  51  is used to filter the noises such as the marked area NS in  FIG. 4 , so that the KEEP ALIVE signal KAS′ becomes standard KEEP ALIVE signal KAS shown in  FIG. 3B , and the comparing unit  221  can be free from the noise interference. Thereby, a more precise comparison can be achieved. 
       FIG. 6  shows a flowchart illustrating a frequency-locking method according to one embodiment of the invention. The method includes the steps described below. 
     Step S 602 : Start. 
     Step S 604 : Receive a KEEP ALIVE signal.
 
Step S 606 : Filter noises of the KEEP ALIVE signal.
 
Step S 608 : Compare the filtered KEEP ALIVE signal with an output frequency signal to generate a calibration signal.
 
Step S 609 : Checking whether the frequency of the calibration signal is within a preset calibration range. If yes, jump to Step S 610 ; if no, go back to Step S 604 .
 
Step S 610 : Adjust the output frequency signal according to the calibration signal, and lock the frequency of the output frequency signal to a specific or predetermined frequency applied to data communication of a universal serial bus device.
 
     Step S 612 : End. 
     Please note that the above-mentioned KEEP ALIVE signal or SOF (Start of frame) satisfies the low-speed USB 2.0 specification or the full-speed USB 2.0. 
     To summarize, the frequency-locking device and the locking method according to the invention is accomplished by taking a KEEP ALIVE signal or a start of a frame as the reference target for the comparing unit to generate the calibration signal. In this way, the frequency-locking effect can be achieved without using complicated packet data as reference for correction. On the other hand, the frequency-locking device according to the invention only needs a registering unit with smaller memory space to temporarily store counting values rather than a look-up table used in prior art. Therefore, the frequency-locking device according to the invention is designed with simpler circuit, reduced cost, and lowered electricity consumption. 
     While the invention has been described by way of examples and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.