Patent Publication Number: US-2005129131-A1

Title: Memory storage method for improving efficiency of image processing

Description:
BACKGROUND OF INVENTION  
      1. Field of the Invention  
      The invention relates to memory, and more particularly, to a memory storage method for improving efficiency of image processing.  
      2. Description of the Prior Art  
      Along with the improvement of the operating speed of digital circuitry, the video/audio processing requiring huge amount of operations has become a crucial issue nowadays while users require higher image resolution. Regarding a high-definition television (HDTV) specification, the resolution (of the picture) typically may contain 1920(horizontal)*1088(vertical) pixels in one frame. In addition, during image processing related to the MPEG (Moving Picture Experts Group) specification or the procedure requiring motion compensation operation, various accesses towards block-based images of different motion vectors in a memory, such as a DRAM (Dynamic Random access Memory), are required. However, when the width of a picture stored in a row of the memory is less than the width of a high-resolution picture (HDTV specification), a crossing-row reading operation toward the memory becomes inevitable during the above-mentioned image processing to acquire the desired motion vector. For instance, each row in a DRAM includes 256 words corresponding to a width of 1024 pixels in the picture, and thus the related MPEG operation under a 1920*1088-pixel resolution will lead to a crossing-row reading operation. Any delay in the (RAS/CAS) control signal caused by the crossing-row reading operation tends to reduce the efficiency of the image processing.  
     SUMMARY OF INVENTION  
      It is therefore one of the many objectives of the claimed invention to provide a memory storage method for improving efficiency of image processing.  
      According to the claimed invention, a memory storage method for improving efficiency of image processing includes storing a plurality of first blocks corresponding to a first picture region of a picture into a first storage region of a memory, storing a plurality of second blocks corresponding to a second picture region of the picture into a second storage region of the memory, and storing at least one second block corresponding to a part of the second picture region adjacent to the first picture region into the first storage region.  
      These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       FIG. 1  is a flow chart showing a memory storage method for improving the efficiency of the image processing according to an embodiment of the present invention.  
       FIG. 2  is a schematic diagram of a portion of a picture.  
       FIG. 3  is a schematic diagram of a storage region. 
    
    
     DETAILED DESCRIPTION  
      Please refer to  FIG. 1 ,  FIG. 2 , and  FIG. 3 .  FIG. 1  is a flow chart showing the memory storage method for improving the efficiency of the image processing according to an embodiment of the present invention,  FIG. 2  is a schematic diagram of a portion of a picture, and  FIG. 3  is a schematic diagram of storage regions of a memory, wherein  FIG. 2  and  FIG. 3  are illustrated in an attempt of assisting the explanation of the method in  FIG. 1 . Please note that the order of the following steps is not meant to serve as limitation of the invention. The memory storage method includes: 
          Step  10 : Store a plurality of first blocks ( 1 , 1 ), ( 1 , 2 ), . . . , ( 68 , 60 ) corresponding to the first picture region  210  of a picture  200  into a first storage region  310  of a memory  300 , which, in the present embodiment, is implemented with a DRAM, while not limited thereto;     Step  20 : store a plurality of second blocks ( 1 , 61 ), ( 1 , 62 ), . . . , ( 68 , 120 ) corresponding to the second picture region  220  of the picture  200  into a second storage region  320  of the memory  300 ; and     Step  30 : store at least one second block ( 1 , 61 ), ( 2 , 61 ), . . . , ( 68 , 61 ) corresponding to the portion  222  of the second picture region  220 , wherein such portion  222  is adjacent to the first picture region  210 , into the first storage region  310 .        

      In the present embodiment, the plurality of blocks ( 1 , 1 ), ( 1 , 2 ), . . . , ( 68 , 120 ) shown in  FIG. 2  and  FIG. 3  are macroblocks conforming to the MPEG (Moving Picture Experts Group) specification, wherein each block corresponds to 16(horizontal)*16(vertical) pixels in the picture  200 . The picture  200  of the present embodiment can be a picture of the HDTV (High-Definition Television), and its resolution is 1920 (horizontal)*1088(vertical) pixels. Therefore, the picture  200  includes 120(horizontal)*68(vertical) blocks. The sequence of the first blocks ( 1 , 1 ), ( 1 , 2 ), . . . , ( 68 , 60 ) and the second blocks ( 1 , 61 ), ( 2 , 61 ), . . . , ( 68 , 61 ) being stored in the first storage region  310  corresponds to the sequence of the blocks ( 1 , 1 ), ( 1 , 2 ), . . . , ( 68 , 61 ) being arranged in the picture  200 . In addition, the sequence of the second blocks ( 1 , 61 ), ( 1 , 62 ), . . . , ( 68 , 120 ) being stored in the second storage region  320  corresponds to the sequence of the blocks ( 1 , 61 ), ( 1 , 62 ), . . . , ( 68 , 120 ) being arranged the picture  200 .  
      In the present embodiment, the width of the picture  200 , or  120  blocks corresponding to 1920 pixels, is greater than the width L 0  of each row of the memory  300 , or  64  blocks corresponding to 1024 pixels. The width L 1  of the first storage region  310  ( 61  blocks corresponding to 976 pixels) and the width L 2  of the second storage region  320  (60 blocks corresponding to 960 pixels) are both less than or equal to the width L 0  of each row of the memory  300 . As shown in  FIG. 3  and  FIG. 2 , the width L 1  of the first storage region  310  is equal to the width of the first picture region  210  (60 blocks corresponding to 960 pixels) added with the width (corresponding to 16 pixels) of a block, which is the width of the block ( 1 , 61 ), ( 2 , 61 ), . . . , or ( 68 , 61 ).  
      In image processing techniques such as, but not limited to, motion estimation or motion compensation, it is common to have pixel data read from a memory, such as a DRAM, in blocks. In order to maximize the effectiveness of the method depicted above in the embodiment of the invention, the width of duplication (i.e., the number of columns of pixels) of the second storage region in the first storage region is preferrably designated the width of the block of the underlying block-read process, as shown in the earlier embodiment by a duplication of one macroblock wide, or 16 pixels wide. However, as should be understood by those of ordinary skill in the art, the width of duplication may also be designated larger or smaller than the block width of the block-read process without altering the merits of the invention. Furthermore, as a person of ordinary skill in the art should also be able to appreciate, the concept of “block” herein can range from a 1×1 block, i.e., a single pixel, to a block composed of multiple pixels with any given height and any given width, and should not be limited to a narrowly construed 8×8 or 16×16 “macroblock”.  
      One of the advantages of the present invention is that no crossing-row reading operation towards the memory is needed and the motion vector for motion compensation operation can be acquired when the width of the picture corresponding to a row of the memory is less than the width of a high-resolution picture. Therefore, the method depicted in the embodiment of the present invention can improve the efficiency of the image processing.  
      Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.