Patent Publication Number: US-9407208-B2

Title: Class AB amplifier with programmable quiescent current

Description:
BACKGROUND 
     1. Field of the Invention 
     The present invention relates to electronics and, more specifically, to Class AB amplifiers. 
     2. Description of the Related Art 
     This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art. 
     Class AB amplifiers offer a tradeoff between the linearity of Class A amplifiers and the power efficiency of Class B amplifiers. Class AB amplifiers are widely used as an output stage to provide a sufficiently linear rail-to-rail output signal with good power efficiency. 
       FIG. 1  shows a schematic circuit diagram of a conventional Class AB amplifier  100  that receives an input voltage signal V IN  and generates an amplified output voltage signal V OUT  to drive a load current i L  across a load resistor R L . In amplifier  100 , transistors M 1  and M 2  are in a complementary source-follower configuration, where M 1  is a p-type (e.g., PMOS) source-follower, and M 2  is an n-type (e.g., NMOS) source-follower. This complementary source-follower configuration needs a supply voltage Vdd of at least 2*Vgs+2*Vdsat to operate properly, where Vgs is the gate-to-source voltage and Vdsat is the difference between Vgs and the threshold voltage Vth for the transistor devices used to implement amplifier  100 . As such, amplifier  100  is not suitable for low-voltage supply scenarios. Furthermore, it has relatively high power consumption. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements. 
         FIG. 1  shows a schematic circuit diagram of a conventional Class AB amplifier; 
         FIG. 2  shows a schematic circuit diagram of an exemplary Class AB amplifier of the present disclosure; 
         FIG. 3  shows a op-amp circuit in which the Class AB amplifier of  FIG. 2  forms the output driver for a differential operational amplifier (op-amp) used as unit-gain voltage follower; 
         FIG. 4  shows a schematic block diagram of a circuit employing a conventional Miller compensation scheme for two-stage amplifiers; and 
         FIG. 5  shows a schematic block diagram of a circuit employing a new Miller compensation scheme for two serially-connected amplifiers. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 2  shows a schematic circuit diagram of an exemplary Class AB amplifier  200  of the present disclosure. Class AB amplifier  200  has two stages: a control stage  210  and a push-pull stage  220 . 
     Control stage  210  comprises a programmable resistor  212  consisting of three independently programmable resistor legs  214 ( 1 )- 214 ( 3 ) connected in parallel and sandwiched between two constant-current transistor devices: PMOS current-source device MPbias and NMOS current-sink device MNbias. Each programmable resistor leg  214 (i) has a resistor Ri connected in series with a switch device SELi. Switch devices SEL 1 -SEL 3  can be selectively turned on or off to provide different effective levels of resistance connected between MPbias and MNbias. Programmable resistor  212  is used to control quiescent current I through devices MPbias and MNbias in amplifier  200 . 
     Push-pull stage  220  comprises a PMOS device  222  and an NMOS device  224 . 
     Control stage  210  uses resistors R 1 -R 3  and constant-current devices MPbias and MNbias to apply a floating constant-voltage source VAB between the gates of PMOS device  222  and NMOS device  224  equal to the product of (i) the current level I through devices MPbias and MNbias and (ii) the effective resistance Reff of programmable resistor  212 . 
     The voltage at node IN can have a dc component Vin(dc) and an ac component Vin(ac). When the ac component Vin(ac) is negative, the voltage at node IN will be below the dc component Vin(dc). When the ac component Vin(ac) is positive, the voltage at node IN will be above the dc component Vin(dc). 
     When the ac component Vin(ac) is zero, amplifier  200  is at its dc operation point. Programmable resistor  212  is configured such that devices  222  and  224  are both near cutoff, so that, when Vin(ac) is zero, only a small amount of current (referred to as the quiescent current) is conducted in push-pull stage  220 , and the output ac current flowing through load resistor Rload is zero. 
     When the ac component Vin(ac) is negative, then the voltage at node IN is below the dc operation point of amplifier  200 , and the net voltages at nodes A and B (which voltages are referred to as Net A and Net B, respectively) decrease from their dc values. Net A decreases to let PMOS device  222  conduct more current (i.e., become more open), and Net B decreases to let NMOS device  224  conduct less current (i.e., become more closed), making the output of push-pull stage  220  sink current. 
     When the ac component Vin(ac) is positive, then the voltage at node IN is above the dc operation point of amplifier  200 , and both Net A and Net B increase from their dc values. Net A increases to let PMOS device  222  conduct less current (i.e., become more closed), and Net B increases to let NMOS device  224  conduct more current (i.e., become more open), making the output of push-pull stage  220  source current. 
     The resistor control scheme of  FIG. 2  makes amplifier  200  suitable for relatively low-voltage supplies, e.g., Vdd=VAB+2*Vdsat rather than 2*Vgs+2*Vdsat as in amplifier  100 . Resistor control is direct and consumes low-voltage headroom. This results in much lower power consumption. Providing the ability to program the quiescent current to a suitable level avoids degrading the bandwidth of the amplifier. A higher quiescent current enables devices  222  and  224  to switch states faster in response to changes in Vin and provides better linearity, but at a cost of higher power for amplifier  200 . A lower quiescent current reduces power for the amplifier, but at a cost of a slower response by devices  222  and  224  to changes in Vin and worse linearity. 
     Although programmable resistor  212  of amplifier  200  has been described as having three programmable resistor legs  214  connected parallel, those skilled in the art will understand that any suitable programmable resistor may be used in alternative embodiments, including (without limitation) programmable resistors having fewer than or more than three parallel legs. Although  FIG. 2  is a single-ended amplifier, those skilled in the art will understand that the present invention can also be implemented in the context of differential amplifiers. 
       FIG. 3  shows a op-amp circuit  300  in which Class AB amplifier  200  of  FIG. 2  forms the output driver for an operational amplifier (op-amp)  310  used as unit-gain voltage follower. Op-amp  310  is a differential input, single-ended output op-amp. The output of op-amp  310  is net IN, which also is the input to Class AB amplifier  200 . In  FIG. 3 , one input of op-amp  310  is vref. The other input of op-amp  310  is net OUT, which is the output of Class AB amplifier  200 . Net OUT may be used as a power supply voltage, as indicated by its application to Rload. Class AB amplifier  200  and op-amp  310  form a negative feedback, unit gain, voltage follower. This is just one application of Class AB amplifier  200  as the output stage in op-amp circuit  300 . 
     In addition to the control stage/push-pull stage architecture of  FIG. 2 , op-amp circuit  300  includes a Miller compensation scheme comprising a compensation feedback path from the output node OUT to the source of PMOS device PM 0  of op-amp  310  via compensation capacitor Cmiller. The Miller compensation scheme of  FIG. 3  employs device PM 0  as the current-mirror loading device of op-amp  310 , instead of a resistor, as in a conventional Miller compensation scheme. By connecting the compensation capacitor Cmiller to an internal, low-impedance node (i.e., the source of PM 0 ), no AC current feedback is allowed from the output node OUT to the internal high-impedance input node IN. This results in pole splitting being achieved with a lower capacitance value of the compensation capacitor Cmiller, which results in Class AB amplifier  200  having a much larger unity-gain frequency, while consuming less power and having a smaller layout compared to other Miller compensated op-amps. Op-amp  300  thus functions as a voltage regulator with a Class AB output stage providing an output voltage OUT, in which indirect Miller compensation is applied for reduced capacitance and higher speed. 
       FIG. 4  shows a schematic block diagram of a circuit  400  employing a conventional Miller compensation scheme for two-stage amplifiers  410  and  420 . In this conventional configuration, Miller compensation is achieved by connecting the output of the second amplifier  420  to the output of the first amplifier through a feedback path consisting of a compensation capacitor Cmiller connected in series with a resistor Rs. 
       FIG. 5  shows a schematic block diagram of a circuit  500  employing the new Miller compensation scheme for two serially-connected amplifiers  510  and  520 . In this new configuration, Miller compensation is achieved by (i) eliminating resistor Rs of  FIG. 4  and (ii) using PMOS device PM 0  of  FIG. 5  as both (a) a current-mirror loading device for amplifier  510  and (b) the resistance for Miller compensation by connecting the output of the second amplifier  520  to the source of PM 0  through a feedback path consisting of only a compensation capacitor Cmiller. 
     Embodiments of the invention may be implemented as (analog, digital, or a hybrid of both analog and digital) circuit-based processes, including possible implementation as a single integrated circuit (such as an ASIC or an FPGA), a multi-chip module, a single card, or a multi-card circuit pack. As would be apparent to one skilled in the art, various functions of circuit elements may also be implemented as processing blocks in a software program. Such software may be employed in, for example, a digital signal processor, micro-controller, general-purpose computer, or other processor. 
     Also for purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements. 
     Also, for purposes of this disclosure, it is understood that all gates are powered from a fixed-voltage power domain (or domains) and ground unless shown otherwise. Accordingly, all digital signals generally have voltages that range from approximately ground potential to that of one of the power domains and transition (slew) quickly. However and unless stated otherwise, ground may be considered a power source having a voltage of approximately zero volts, and a power source having any desired voltage may be substituted for ground. Therefore, all gates may be powered by at least two power sources, with the attendant digital signals therefrom having voltages that range between the approximate voltages of the power sources. 
     Signals and corresponding nodes, ports, or paths may be referred to by the same name and are interchangeable for purposes here. 
     Transistors are typically shown as single devices for illustrative purposes. However, it is understood by those with skill in the art that transistors will have various sizes (e.g., gate width and length) and characteristics (e.g., threshold voltage, gain, etc.) and may consist of multiple transistors coupled in parallel to get desired electrical characteristics from the combination. Further, the illustrated transistors may be composite transistors. 
     As used in this specification and claims, the term “channel node” refers generically to either the source or drain of a metal-oxide semiconductor (MOS) transistor device (also referred to as a MOSFET), the term “channel” refers to the path through the device between the source and the drain, and the term “control node” refers generically to the gate of the MOSFET. Similarly, as used in the claims, the terms “source,” “drain,” and “gate” should be understood to refer either to the source, drain, and gate of a MOSFET or to the emitter, collector, and base of a bi-polar device when an embodiment of the invention is implemented using bi-polar transistor technology. 
     It should be appreciated by those of ordinary skill in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the invention. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. 
     Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value or range. 
     It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain embodiments of this invention may be made by those skilled in the art without departing from embodiments of the invention encompassed by the following claims. 
     In this specification including any claims, the term “each” may be used to refer to one or more specified characteristics of a plurality of previously recited elements or steps. When used with the open-ended term “comprising,” the recitation of the term “each” does not exclude additional, unrecited elements or steps. Thus, it will be understood that an apparatus may have additional, unrecited elements and a method may have additional, unrecited steps, where the additional, unrecited elements or steps do not have the one or more specified characteristics. 
     The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures. 
     It should be understood that the steps of the exemplary methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely exemplary. Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined, in methods consistent with various embodiments of the invention. 
     Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence. 
     Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.” 
     The embodiments covered by the claims in this application are limited to embodiments that (1) are enabled by this specification and (2) correspond to statutory subject matter. Non-enabled embodiments and embodiments that correspond to non-statutory subject matter are explicitly disclaimed even if they fall within the scope of the claims.