Patent Publication Number: US-7592791-B2

Title: High efficiency DC-DC converter using pulse skipping modulation with programmable burst duration

Description:
BACKGROUND 
     1. Technical Field 
     The embodiments herein generally relate to electrical converter circuits and, more particularly, to utilizing a pulse skipping modulation (PSM) circuits to control a direct current to direct current (DC-DC) converter of an integrated circuit (IC) chip. 
     2. Description of the Related Art 
     Various types of electronic equipment, more particularly, portable or handheld electronic devices such as cellular telephones, personal digital assistants (PDAs), etc., are capable of being powered from a self-contained power source such as a battery, which may be recharged by an external power source. Moreover, these devices typically contain an integrated circuit chip(s) embedded in the device. Additionally, some interfaces may provide a power source through an interface itself such as a Universal Serial Bus (USB). A DC-DC converter may be utilized to convert the battery voltage, external voltage, or both voltages to a DC value which will supply power to various circuits of the integrated circuit chip(s). The converted voltage may be a supply voltage (rail voltage) provided to a load. However, because the load at the output of the DC-DC converter may vary substantially, the load current may also vary considerably. Furthermore, in some instances it is desirable for the DC-DC converter to be as efficient as possible in the low power state to extend the device&#39;s battery life. 
     However, when switched DC-DC converters are used, the converters are inherently less efficient when driving light loads because the power needed to switch the large power field-effect-transistors (FETs) is comparable or greater than the energy transferred to the load. Moreover, when driving a heavy load, the energy needed to switch the FETs is less relative to energy transferred to the load, so the efficiency is higher. A conventional technique to improve light load efficiency is to implement a pulse-frequency modulation (PFM) converter, which modulates the frequency that the DC-DC converter operates to optimize efficiency by enabling the power FETs to bring the output voltage level to a high threshold, then disabling the FETs until the voltage drops to a low threshold. This well-known technique improves efficiency by reducing the number of times the FETs are toggled to transfer power to the load. 
     Typically, the architecture of these PSM converters implements some form of current mode control. However, current mode control is generally difficult because it requires sensing currents, which is difficult to sense due to noise, offsets and circuit complexity. Also, sensing a current typically requires a sensing resistor, which may negatively impact efficiency. Thus, sensing current in a switched DC-DC converter may be difficult to do or may be undesirable. Accordingly, there remains a need for a new DC-DC converter having improved efficiency characteristics at low load current levels. 
     SUMMARY 
     In view of the foregoing, an embodiment provides a DC-DC converter comprising a pair of switches; a load capacitor operatively connected to the pair of switches; a pulse width modulator adapted to generate pulse signals for driving the pair of switches; an analog comparator with hysteresis adapted to control an output voltage level within a specified range, wherein as the output voltage level rises above a high threshold level, an analog comparator output becomes low and starts skipping clock pulses, wherein as the output voltage level drops below a low threshold level, the analog comparator output becomes high and a clock signal is passed to the pair of switches to charge the load capacitor, and wherein the analog comparator is further adapted to compare the output voltage level with either the low threshold level or the high threshold level; a first counter; a first register operatively connected to the first counter, wherein when the analog comparator output becomes low the first counter stops and stores its last value Non in the first register; a first digital comparator operatively connected to the first register; and an up-down counter operatively connected to the first digital comparator and the pulse width modulator, wherein during turn-on of the pair of switches, a load current at a load resistor is supplied by the pair of switches, and the load capacitor charges, wherein a turn-on time is a time when the output voltage level discharges from the low threshold level to the high threshold level through the load capacitor, wherein the turn-on time is measured by the first counter and the first register, wherein the first counter starts counting when the analog comparator output becomes high, which occurs when the output voltage level reaches the low threshold level and the pair of switches turn on, and wherein when the output voltage level reaches the high threshold level, the analog comparator output becomes low and the first counter stops counting and stores its last value, which represents the measured turn-on time, in the first register. 
     Preferably, the high threshold level minus the low threshold level defines a hysteresis width of the analog comparator. Moreover, a voltage coming out of the pair of switches preferably has a duty cycle controlled by the pulse width modulator. Additionally, the Non value is compared with a desired value Non_ref using the first digital comparator, wherein if Non&lt;Non_ref, the up-down counter counts down to decrease a duty cycle of the pulse waves, and wherein if Non&gt;Non_ref, the up-down counter counts up to increase the duty cycle of the pulse waves. Furthermore, a turn-on duration of the pair of switches is represented by the Non value preferably converges to the Non_ref at steady state. Also, once the output voltage level exceeds the high threshold level, the analog comparator output preferably becomes low and the pair of switches turn off. Preferably, when the output voltage level is lower than the low threshold level, the analog comparator output is high and the pulse signals are passed through the pair of switches. Moreover, the DC-DC converter may further comprise a second counter and a second register operatively connected to the second counter, wherein when the output voltage level reaches the low threshold level, the second counter stops counting and stores its value Noff in the second register, and wherein the value Noff is a measure of the load current. 
     Another embodiment provides a method of controlling voltage in a DC-DC converter, wherein the method comprises electrically connecting a pair of switches to a load capacitor; generating pulse signals with a pulse width modulator for driving the pair of switches; controlling an output voltage level within a specified range using an analog comparator with hysteresis, wherein as the output voltage level rises above a high threshold level, an analog comparator output becomes low and starts skipping clock pulses, wherein as the output voltage level drops below a low threshold level, the analog comparator output becomes high and a clock signal is passed to the pair of switches to charge the load capacitor, and wherein the analog comparator is further adapted to compare the output voltage level with either the low threshold level or the high threshold level; sending a clock signal to a first counter, wherein when the analog comparator output becomes low the first counter stops and stores its last value Non in a first register, wherein the first register is operatively connected to a first digital comparator, wherein the first digital comparator is operatively connected to an up-down counter, wherein the up-down counter is operatively connected to the pulse width modulator; turning on the pair of switches such that a load current at a load resistor is supplied by the pair of switches, causing the load capacitor to charge; and measuring a turn-on time using the first counter and the first register, wherein the turn-on-time is a time when the output voltage level discharges from the low threshold level to the high threshold level through the load capacitor, wherein the first counter starts counting when the analog comparator output becomes high, which occurs when the output voltage level reaches the low threshold level and the pair of switches turn on, and wherein when the output voltage level reaches the high threshold level, the analog comparator output becomes low and the first counter stops counting and stores its last value, which represents the measured turn-on time, in the first register. 
     Preferably, the high threshold level minus the low threshold level defines a hysteresis width of the analog comparator. Additionally, a voltage coming out of the pair of switches preferably has a duty cycle controlled by the pulse width modulator. Also, the Non value is preferably compared with a desired value Non_ref using the first digital comparator. Preferably, if Non&lt;Non_ref, the up-down counter counts down to decrease a duty cycle of the pulse waves, and if Non&gt;Non_ref, the up-down counter counts up to increase the duty cycle of the pulse waves. Moreover, a turn-on duration of the pair of switches represented by the Non value preferably converges to the Non_ref at steady state. Preferably, once the output voltage level exceeds the high threshold level, the analog comparator output becomes low and the pair of switches turn off. Additionally, when the output voltage level is lower than the low threshold level, the analog comparator output is preferably high and the pulse signals are passed through the pair of switches. The method may further comprise operatively connecting a second register to a second counter, wherein when the output voltage level reaches the low threshold level, the second counter stops counting and stores its value Noff in the second register, and wherein the value Noff is a measure of the load current. 
     Another embodiment provides a DC-DC converter comprising a pair of switches; a load capacitor operatively connected to the pair of switches; a pulse width modulator adapted to generate pulse signals for driving the pair of switches; an analog comparator with hysteresis adapted to control an output voltage level within a specified range, wherein as the output voltage level rises above a high threshold level, an analog comparator output becomes low and starts skipping clock pulses, wherein as the output voltage level drops below a low threshold level, the analog comparator output becomes high and a clock signal is passed to the pair of switches to charge the load capacitor, and wherein the analog comparator is further adapted to compare the output voltage level with either the low threshold level or the high threshold level; a first counter; a first register operatively connected to the first counter, wherein when the analog comparator output becomes low the first counter stops and stores its last value Non in the first register; a first digital comparator operatively connected to the first register; an up-down counter operatively connected to the first digital comparator and the pulse width modulator; a second counter; and a second register operatively connected to the second counter, wherein when the output voltage level reaches the low threshold level, the second counter stops counting and stores its value Noff in the second register, wherein the value Noff is a measure of the load current and controls the size of the pair of switches, wherein for low load current levels, the value of the Noff is high and the size of the pair of switches is decreased to reduce capacitive power losses, and wherein for high load current levels, the value of the Noff is low and the size of the pair of switches is increased to reduce resistive power losses. 
     These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the spirit thereof, and the embodiments herein include all such modifications. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The embodiments herein will be better understood from the following detailed description with reference to the drawings, in which: 
         FIG. 1  illustrates a schematic diagram of a DC-DC converter according to an embodiment herein; 
         FIG. 2  are graphical representations illustrating waveforms of V sw , inductor current, and V out  according to the embodiments herein; 
         FIG. 3  is a graphical representation illustrating an analog comparator output switching from low to high and vice versa according to the embodiments herein; and 
         FIG. 4  is a flow diagram illustrating a preferred method according to an embodiment herein. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein. 
     As mentioned, there remains a need for a new DC-DC converter having improved efficiency characteristics at low load current levels. The embodiments herein achieve this by using pulse skipping modulation (PSM) with controllable burst durations. Referring now to the drawings, and more particularly to  FIGS. 1 through 4 , where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments. 
     As mentioned, the embodiments herein provide a new technique to improve DC-DC converter efficiency at low load current levels. The new technique uses PSM with controllable burst duration NT clk , where T clk  is the clock cycle interval.  FIG. 1  illustrates a DC-DC converter  100  according to an embodiment herein. As average load current increases, the time between bursts decreases so that average inductor current I L  matches the load current. The burst duration is kept at approximately NT clk  by controlling the duty cycle at the output of the PWM generator  104  that drives the output switches  103 . The higher the load current, the higher the duty cycle of the output switches  103 . No current sensing is needed in the technique provided by the embodiments herein. Moreover, there is a maximum limit on the burst duration for a best efficiency curve is a function of the load capacitor  108 . This can be explained as follows: the average inductor current equals the load current as expressed below: 
                     I     ind   ,   av       =         Q     T   ON       +     I   Load       =         C   ⁢           ⁢   Δ   ⁢           ⁢   V       T   ON       +     I   Load                 (   1   )               
where ΔV is the hysteresis width of the analog comparator  101 . To keep inductor current unidirectional for best efficiency, the following condition applies:
 
                     I   av     =           C   ⁢           ⁢   Δ   ⁢           ⁢   V       T   ON       +     I   Load       &gt;       Δ   ⁢           ⁢   I     2               (   2   )               
where ΔI is the inductor ripple current which is given by:
 
     
       
         
           
             
               
                 
                   
                     Δ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     I 
                   
                   = 
                   
                     
                       
                         
                           D 
                           ⁡ 
                           
                             ( 
                             
                               1 
                               - 
                               D 
                             
                             ) 
                           
                         
                         ⁢ 
                         
                           T 
                           clk 
                         
                         ⁢ 
                         
                           V 
                           DD 
                         
                       
                       L 
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     To ensure condition (2) at all current levels, its must be current when I load =0. Therefore: 
                     T   ON     &lt;       2   ⁢   C   ⁢           ⁢   Δ   ⁢           ⁢   V   ⁢           ⁢   L         D   ⁡     (     1   -   D     )       ⁢     T   clk     ⁢     V   DD                 (   4   )               
The N ON  is expressed as:
 
     
       
         
           
             
               
                 
                   
                     N 
                     ON 
                   
                   = 
                   
                     
                       
                         T 
                         ON 
                       
                       
                         T 
                         clk 
                       
                     
                     &lt; 
                     
                       
                         2 
                         ⁢ 
                         C 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         Δ 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         VL 
                       
                       
                         
                           D 
                           ⁡ 
                           
                             ( 
                             
                               1 
                               - 
                               D 
                             
                             ) 
                           
                         
                         ⁢ 
                         
                           T 
                           clk 
                           2 
                         
                         ⁢ 
                         
                           V 
                           DD 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     An analog comparator  101  with hysteresis is used to control the output voltage level within a specified range. When the output rises above a high threshold voltage level, V TH , the comparator output becomes low to start skipping clock pulses. However, at this moment, the inductor current, I L , is still high. The switch S n  is kept ON until the inductor current, I L , goes to zero. After switch S n  turns OFF, switch S damp  turns ON to damp the residual small inductor current, I L . If the output drops below the low threshold voltage level, V TL , the comparator output becomes low and the clock signal V CLK  is passed to the switches S p  and S n  to charge the load capacitor  108  and the switch S damp  is turned OFF. Moreover, the S damp  and R damp  dampen LC oscillations when the switches S n  and S p  are turned OFF. 
     The analog comparator  101  compares the output voltage level, vout, with either a low threshold voltage level, V TL  or high threshold voltage level, V TH . In this regard, V TH −V TL  defines the hysteresis width (and therefore, the output voltage ripple). Moreover, in the context of the embodiments herein V TL  equals −1 to −5% of the target threshold voltage level and V TH  equals 1 to 5% of the target threshold voltage level. If a smaller output voltage ripple is required, then smaller V TH −V TL  should be used, which will have an impact on the maximum N ON  that can be used according to equation (5). If the output voltage level, vout, is lower than V TL , the comparator output will be high and the pwm (pulse width modulated) pulses from PWM control  104  are passed through the driver switches  103 . 
     The voltage at vsw will be toggling between 0 and VDD (as shown in  FIG. 2 ) with a duty cycle controlled by PWM control  104 . The output voltage level starts increasing ( FIG. 2 ) and the counter  106  starts counting up. Once the output voltage level exceeds the V TH , the comparator  101  output becomes low and the switches  103  turn off. Counter  106  stops and stores its last value Non in a register  105 . Non is compared with a desired value Non_ref using a digital comparator  102 . If Non&lt;Non_ref, this means that the vout ramps up faster than desired. The up/dn counter  107  counts down which causes the duty cycle of the output of PWM control  104  to be decreased. If Non&gt;Non_ref, then vout ramps up slower than desired, and up/dn counter  107  counts up to increase the duty cycle of PWM control  104 . It should be appreciated that block  107  does not have to be configured as an up/dn counter as other methods of digital control are also possible within the context of the embodiments herein. 
     The turn-on duration, represented by Non converges to the desired Non_ref at steady state. During turn-off, the current at the load R Load  is only supplied by the filter capacitor  108 . The higher the load current, the quicker the output voltage level will discharge. Therefore, the load current is sensed by measuring the turn-off time. That is, the time when the output voltage level, vout, discharges from V TH  to V TL  through the capacitor  108 . This time is measured by counter  109 , register  111 , and comparator  110 . The counter  109  starts counting when comparator  101  output becomes low (i.e., vout reaches V TH  and switches  103  turn off). When the output voltage level reaches V TL , counter  109  stops and stores its value Noff in the register  111 . The value Noff is a measure of the load current. Moreover, Noff can be related to the load current according to the following equation: 
     
       
         
           
             
               
                 
                   
                     N 
                     off 
                   
                   = 
                   
                     
                       C 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       Δ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       V 
                     
                     
                       
                         I 
                         Load 
                       
                       ⁢ 
                       
                         T 
                         clk 
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     Conventional approaches to measure load current use small series resistance to convert current to voltage then measure the voltage. However, the series resistance significantly degrades the DC-DC converter efficiency. Conversely, according to the embodiments herein, the current is measured by measuring the turn-off period, represented by N off . Information about load current can be used to optimize DC-DC converter efficiency at different load currents. There are two main sources of power loss in DC-DC converters: (1) resistive losses due to the series resistances of the switches and the inductor, and (2) capacitive (switching) power loss due to the large size of the switch drivers (switches  103 ). 
     Larger switch size results in low series resistance (lower resistive losses) but high capacitance (higher capacitive losses). At low load currents, resistive losses are smaller than capacitive losses. Therefore, it is better to reduce switch size to reduce its capacitance and increase its resistance in low current levels. At high current levels, resistive losses are dominant and it is better to increase switch size to optimize efficiency. The value of N off , which is proportional to the load current, is used to control the size of the switches  103  to optimize its efficiency at all current levels. 
       FIG. 3  illustrates the output of the analog comparator  101  (of  FIG. 1 ) when the switches S p  and S n  turn ON and OFF (i.e., go from low to high and vice versa). When the output of the analog comparator  101  causes the switches S p  and S n  to turn ON, the first counter  106  starts and the second counter  109  stops. Also, the second register  111  stores the content of the second counter  109  and the second digital comparator  110  compares Noff with Noff_ref. When the output of the analog comparator  101  causes the switches S p  and S n  to turn OFF, the second counter  109  starts and the first counter  106  stops. Also, the first register  105  stores the content of the first counter  106  and the first digital comparator  102  compares Non with Non_ref. 
       FIG. 4 , with reference to  FIGS. 1 through 3 , is a flow diagram illustrating a method of controlling voltage in a DC-DC converter  100  according to an embodiment herein, wherein the method comprises electrically connecting ( 301 ) a pair of switches  103  to a load capacitor  108 ; generating ( 303 ) pulse signals with a pulse width modulator  104  for driving the pair of switches  103 ; controlling ( 305 ) an output voltage level, vout, within a specified range using an analog comparator  101  with hysteresis, wherein as the output voltage level, vout, rises above a high threshold level, V TH , an analog comparator output becomes low and starts skipping clock pulses, wherein as the output voltage level, vout, drops below a low threshold level, V TL , the analog comparator output becomes high and a clock signal, clk, is passed to the pair of switches  103  to charge the load capacitor  108 , and wherein the analog comparator  101  is further adapted to compare the output voltage level, vout, with either the low threshold level, V TL , or the high threshold level, V TH ; sending ( 307 ) a clock signal, clk, to a first counter  106 , wherein when the analog comparator output becomes low the first counter  106  stops and stores its last value Non in a first register  105 , wherein the first register  105  is operatively connected to a first digital comparator  102 , wherein the first digital comparator  102  is operatively connected to an up-down counter  107 , wherein the up-down counter  107  is operatively connected to the pulse width modulator  104 ; turning ( 309 ) on the pair of switches  103  such that a load current at a load resistor, R Load , is supplied by the pair of switches  103 , causing the load capacitor  108  to charge; and measuring ( 311 ) a turn-on time using the first counter  106  and the first register  105 , wherein the turn-on-time is a time when the output voltage level, vout, discharges from the low threshold level, V TL , to the high threshold level, V TH , through the load capacitor  108 , wherein the first counter  106  starts counting when the analog comparator output becomes high, which occurs when the output voltage level, vout, reaches the low threshold level, V TL , and the pair of switches turn on  103 , and wherein when the output voltage level, vout, reaches the high threshold level, V TH , the analog comparator output becomes low and the first counter  106  stops counting and stores its last value, which represents the measured turn-on time, in the first register  105 . 
     Preferably, the high threshold level, V TH , minus the low threshold level, V TL , defines a hysteresis width of the analog comparator  101 . Additionally, a voltage, vsw, coming out of the pair of switches  103  preferably has a duty cycle controlled by the pulse width modulator  104 . Also, the Non value is preferably compared with a desired value Non_ref using the first digital comparator  102 . Preferably, if Non&lt;Non_ref, the up-down counter  107  counts down to decrease a duty cycle of the pulse waves, and if Non&gt;Non_ref, the up-down counter  107  counts up to increase the duty cycle of the pulse waves. Moreover, a turn-on duration of the pair of switches  103  represented by the Non value preferably converges to the Non_ref at steady state. Preferably, once the output voltage level, vout, exceeds the high threshold level, V TH , the analog comparator output becomes low and the pair of switches  103  turn off. Additionally, when the output voltage level, vout, is lower than the low threshold level, V TL , the analog comparator output is preferably high and the pulse signals are passed through the pair of switches  103 . The method may further comprise operatively connecting a second register  111  to a second counter  109 , wherein when the output voltage level, vout, reaches the low threshold level, V TL , the second counter  109  stops counting and stores its value Noff in the second register  111 , and wherein the value Noff is a measure of the load current. 
     The techniques provided by the embodiments herein may be implemented on an IC chip or using printable electronic technologies (not shown). The chip or printable electronic circuit design is created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or printable electronic circuits or the photolithographic masks used to fabricate chips or printable electronic circuits, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII or CIF) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer or printed on a suitable substrate. The photolithographic masks are utilized to define areas of the wafer or printable electronic circuits (and/or the layers thereon) to be etched or otherwise processed or printed. 
     The resulting integrated circuit chips or printable electronic circuits can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form or as individual printed circuits or in a sheet or roll of printed circuits. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip might then be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a mother or daughter-board, or (b) an end product. The end product can be any product that includes integrated circuit chip or chips and/or printed circuits, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
     The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.