Patent Publication Number: US-7915638-B2

Title: Symmetric bidirectional silicon-controlled rectifier

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a silicon-controller rectifier, particularly to a symmetric bidirectional silicon-controlled rectifier, which has a small area and a high electrostatic-discharge protection capability. The present invention applies to an ESD protection element for I/O signals with both positive and negative voltage level. 
     2. Description of the Related Art 
     With the advance of semiconductor technology, the dimensions of MOS (Metal Oxide Semiconductor) devices have been reduced to a submicron or even deep-submicron scale. The submicron or deep-submicron technology uses so thin a gate oxide layer that only a few volts higher voltage is enough to cause gate oxide damage. In general environments, electrostatic voltage maybe reach thousands or even several ten thousands volts, which will damage integrated circuits (IC). Therefore, once having accumulated to a given amount in IC, electrostatic charge should be released by ESD device. The silicon-controlled rectifier, which has a low turn-on resistance, low capacitance, low power consumption and high-power current conduction capability, is exactly an effective ESD (Electro-Static Discharge) protection element for IC. 
     Currently, the bidirectional silicon-controlled rectifier (SCR) has become the mainstream in the market of the ESD protection circuits for I/O signals with both positive and negative voltage level, and many researches are also dedicated to the bidirectional silicon-controlled rectifier. U.S. Pat. Nos. 6,258,634, 6,365,924 and 7,034,363 all disclosed symmetric bidirectional silicon-controlled rectifiers. As the silicon-controlled rectifiers disclosed in the abovementioned patents are all directly fabricated on a silicon substrate, they have lower breakdown voltages and can only apply to generic IC processes. A U.S. Pat. No. 6,960,792 disclosed an symmetric bidirectional silicon-controlled rectifier with annular layout, which consumes a larger layout area. Furthermore, the trigger speed is also deeply influenced by the structure thereof. Therefore, the device proposed in U.S. Pat. No. 6,960,7922 cannot provide an effective ESD protection function. A U.S. Pat. No. 5,072,273 disclosed a low trigger voltage silicon-controlled rectifier. However, it can only operate unidirectionally. The proposed structure cannot apply to an ESD protection circuit for I/O signal with both positive and negative voltage level. 
     Accordingly, the present invention proposes a novel symmetric bidirectional silicon-controlled rectifier to overcome the abovementioned problems and drawbacks. 
     SUMMARY OF THE INVENTION 
     The primary objective of the present invention is to provide a symmetric bidirectional silicon-controlled rectifier, which can prevent electrostatic charge from damaging a semiconductor element. 
     Another objective of the present invention is to provide a symmetric bidirectional silicon-controlled rectifier, which has a small area and a high electrostatic discharge (ESD) protection capability. 
     Yet another objective of the present invention is to provide a symmetric bidirectional silicon-controlled rectifier, which has an adjustable trigger voltage and an adjustable holding voltage to implement a better design and a better protection. 
     Still another objective of the present invention is to provide a symmetric bidirectional silicon-controlled rectifier, which has an embedded MOS structure to enhance the turn-on speed and high ESD robustness. 
     Further another objective of the present invention is to provide a symmetric bidirectional silicon-controlled rectifier, which applies to a high-voltage technology to function as an ESD protection device for I/O signals with both positive and negative voltage level. 
     Still further another objective of the present invention is to provide a symmetric bidirectional silicon-controlled rectifier, which has a small parasitic capacitance to reduce signal loss. 
     To achieve the abovementioned objectives, the present invention proposes a symmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type buried layer formed on the substrate; a second conduction type first well, a first conduction type middle region and a second conduction type second well, which are side-by-side formed on the first buried layer; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas, and the first gate, the first semiconductor area and the second semiconductor area are connected to an anode; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas, and the second gate, the fourth semiconductor area and the fifth semiconductor area are connected to a cathode. 
     The present invention also proposes another embodiment of a symmetric bidirectional silicon-controlled rectifier, wherein the first and fourth semiconductor areas are of the first conduction type, and the second, third, fifth and sixth semiconductor areas are of the second conduction type. 
     The present invention also proposes yet another embodiment of a symmetric bidirectional silicon-controlled rectifier, wherein the first and fourth semiconductor areas are of the second conduction type, and the second, third, fifth and sixth semiconductor areas are of the first conduction type. 
     The present invention also proposes still another embodiment of a symmetric bidirectional silicon-controlled rectifier, wherein the first, third, fourth and sixth semiconductor areas are of the second conduction type, and the second and fifth semiconductor areas are of the first conduction type. 
     The present invention also proposes further another embodiment of a symmetric bidirectional silicon-controlled rectifier, wherein the first, third, fourth and sixth semiconductor areas are of the first conduction type, and the second and fifth semiconductor areas are of the second conduction type. 
     Below, various embodiments as described would allow a better understanding the objectives, technical contents, characteristics and accomplishments of the present invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram schematically showing an embodiment of a symmetric silicon-controlled rectifier according to the present invention; 
         FIG. 2  is a diagram schematically showing another embodiment of a symmetric silicon-controlled rectifier according to the present invention; 
         FIG. 3  is a diagram schematically showing yet another embodiment of a symmetric silicon-controlled rectifier according to the present invention; 
         FIG. 4  is a diagram schematically showing still another embodiment of a symmetric silicon-controlled rectifier according to the present invention; and 
         FIG. 5  is a diagram schematically showing further another embodiment of a symmetric silicon-controlled rectifier according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Refer to  FIG. 1  a diagram schematically showing an embodiment of a symmetric silicon-controlled rectifier according to the present invention. In this embodiment, the symmetric silicon-controlled rectifier of the present invention comprises: a P-type substrate  10 ; an N-type first buried layer  12  formed on the substrate  10 ; and P-type second and third buried layer  14  and  16  respectively formed at two sides of the first buried layer  12 . 
     A P-type first well  18 , a middle region  22  and a P-type second well  20  are side-by-side formed on the first buried layer  12 . The middle region  22  is interposed between the first and second wells  18  and  20  and may be an undoped epitaxial region or an arbitrary N-type region, such as an N-type epitaxial region or an N-type well. An N-type first semiconductor area  24  and a P-type second semiconductor area  26  are both formed inside the first well  18 . A P-type third semiconductor area  28  is formed in a junction between the first well  18  and the middle region  22 . A gate  30  is formed over a region between the second and third semiconductor areas  26  and  28 . The first and second semiconductor areas  24  and  26  are connected to an anode  34 , and the gate  30  is also connected to the anode  34  via a resistor  32  cascaded to the gate  30 . 
     An N-type fourth semiconductor area  36  and a P-type fifth semiconductor area  38  are both formed inside the second well  20 . A P-type sixth semiconductor area  40  is formed in a junction between the second well  20  and the middle region  22 . A gate  42  is formed over a region between the fifth and sixth semiconductor areas  38  and  40 . The fourth and fifth semiconductor areas  36  and  38  are connected to a cathode  46 , and the gate  42  is also connected to the cathode  46  via a resistor  44  cascaded to the gate  42 . 
     A P-type third well  48  is formed on the second buried layer  14 . A P-type seventh semiconductor area  50  is formed inside the third well  48  for grounding. An N-type undoped epitaxial layer  52  is formed in between the first and third wells  18  and  48 . A P-type fourth well  54  is formed on the third buried layer  16 . A P-type eighth semiconductor area  56  is formed inside the fourth well  54  for grounding. An N-type undoped epitaxial layer  58  is formed in between the second and fourth wells  20  and  54 . A fifth well (not shown in the drawing) and a sixth well (not shown in the drawing) may further be formed in the epitaxial layer  52  and the epitaxial layer  58  respectively. 
     The critical breakdown voltage of this embodiment can be lowered by one MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) which includes the gate  30 , the second semiconductor area  26  and the third semiconductor area  28  and the other MOSFET which includes the gate  42 , the fifth semiconductor area  38  and the sixth semiconductor area  40 . Thereby, the trigger voltage of the embodiment is regulated, and the turn-on speed is improved. 
     The embodiment described above adopts a P-type substrate, and the conduction types of other elements vary with the conduction type of the substrate. For example, the N-type first buried layer, the N-type middle region, etc., are adopted to match with the P-type substrate. If a N-type substrate may also be adopted, the conduction types of other elements should be varied with the conduction type of the substrate. The characteristic of conduction type interchangeability also applies to the following embodiments. Further, separation structures, such as oxide layers, shallow trenches, or undoped semiconductor areas, may also be formed in between nearby semiconductor area. 
     Refer to  FIG. 2  a diagram schematically showing another embodiment of a symmetric silicon-controlled rectifier according to the present invention, wherein a floating gate  60  is formed over a region between the third and sixth semiconductor areas  28  and  40  shown in  FIG. 1  to reduce the spacing between the third and sixth semiconductor areas  28  and  40  so as to regulate the holding voltage. 
     Refer to  FIG. 3  a diagram schematically showing yet another embodiment of a symmetric silicon-controlled rectifier according to the present invention, wherein the conduction type of the first semiconductor area  24  shown in  FIG. 1  is changed from N-type to P-type; the conduction types of the second and third semiconductor areas  26  and  28  are changed from P-type to N-type; the conduction type of the fourth semiconductor area  36  is changed from N-type to P-type; the conduction types of the fifth and sixth semiconductor areas  38  and  40  are changed from P-type to N-type. 
     Further, a floating gate for regulating the holding voltage (not shown in the drawing) may also be formed over a region between the third and sixth semiconductor areas  28  and  40 . 
     In this embodiment, the breakdown voltage will be lowered by one MOSFET which includes the gate  30 , the second semiconductor area  26  and the third semiconductor area  28  and the other MOSFET which includes the gate  42 , the fifth semiconductor area  38  and the sixth semiconductor area  40 . Thereby, the trigger voltage of the embodiment can be regulated. 
     Refer to  FIG. 4  a diagram schematically showing still another embodiment of a symmetric silicon-controlled rectifier according to the present invention, wherein the conduction type of the first semiconductor area  24  shown in  FIG. 1  is changed from N-type to P-type; the conduction type of the second semiconductor area  26  is changed from P-type to N-type; the conduction type of the fourth semiconductor area  36  is changed from N-type to P-type; the conduction type of the fifth semiconductor area  38  is changed from P-type to N-type. 
     In this embodiment, a floating gate (not shown in the drawing) may also be formed over a region between the third and sixth semiconductor areas  28  and  40 . 
     Refer to  FIG. 5  a diagram schematically showing further another embodiment of a symmetric silicon-controlled rectifier according to the present invention. The structure of this embodiment is basically similar to that of the embodiment shown in  FIG. 1  except the conduction types of the third and sixth semiconductor areas  28  and  40  are changed from P-type to N-type. In this embodiment, a floating gate may also be formed over a region between the third and sixth semiconductor areas  28  and  40 . 
     In conclusion, the present invention proposes a symmetric bidirectional silicon-controlled rectifier having a small-area and a high ESD protection capability. Further, a MOSFET is embedded in the SCR of the present invention to improve the turn-on speed and the ESD protection capability. Besides, the MOSFET enables the symmetric bidirectional SCR of the present invention to have an adjustable holding voltage and an adjustable trigger voltage so as to apply to various I/O circuits. Consequently, the present invention also can apply to a high-voltage CMOS chip and function as a protection element for I/O signals with both positive and negative voltage level. Furthermore, the present invention with low leakage current and low parasitic capacitance can reduce signal loss in normal operation condition. 
     Those described above are only the preferred embodiments to exemplify the present invention but not to limit the scope of the present invention. Any equivalent modification or variation according to the spirit of the present invention is to be also included within the scope of the present invention.