Patent Publication Number: US-6906930-B2

Title: Structure and method for an isolated boost converter

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to power converters (e.g., boost converters). In particular, the present invention relates to isolated power converters, such as boost converters. 
   2. Discussion of the Related Art 
   Boost converter topologies have been extensively used in various AC/DC and DC/DC power conversion applications. In fact, virtually all the front ends of today&#39;s AC/DC power supplies that include a power-factor correction (PFC) feature are implemented using a boost converter topology. Boost converter topologies are also used in numerous applications where a relatively low battery-powered input voltage is used to generate a high output voltage. The vast majority of conventional power converters that use a boost topology are non-isolated. However, in some applications, boost converters with galvanically-isolated input and output are required. 
   Isolated boost converter having one or more isolation transformers are known and studied. Typically, an isolated boost converter may have one or more switches and one or more boost inductors. For example,  FIG. 1  shows a current-fed push-pull converter  100 , which was disclosed in U.S. Pat. No. 3,938,024 to P. W. Clarke, entitled “Converter Regulation by Controlled Conduction Overlap,” and issued on Feb. 10, 1976. As shown in  FIG. 1 , push-pull converter  100  includes an isolated boost converter with boost inductor  101  and switches  102   a  and  102   b . As another example,  FIG. 2  shows isolated boost converter  200 , which was disclosed in the article “A Current-Sourced Dc—Dc Converter Derived via the Duality Principle from the Half-Bridge Converter” by P. J. Wolfs,  IEEE Trans. Industrial Electronics , vol. 40, pp. 139-144, February 1993, uses boost inductors  101   a  and  101   b , and switches  102   a  and  102   b.    
   Isolated boost converter  200  has a simpler transformer design than single-inductor boost converter  100 , in that primary winding  204  and secondary winding  205  in transformer  203  each require only a single winding. By contrast, single-inductor boost converter  100  requires tapped primary and secondary windings  104  and  105  (i.e., essentially two windings each in the primary and secondary windings). In addition, the voltage stress on each of switches  102   a  and  102   b  in isolated boost converter  200  is one-half the voltage stress on each of switches  102   a  and  102   b  of single-inductor isolated boost converter  100 . In particular, the voltage stress on each of primary switches  102   a  and  102   b  of isolated boost converter  200  equals the reflected output voltage to primary winding  204 , whereas the voltage stress on each primary switch  102   a  and  102   b  in isolated boost converter  100  equals twice the reflected output voltage. In either isolated boost converters, however, an increased voltage stress on the primary switches results from ringing between the parasitic leakage inductance of the transformer and the output capacitance of the primary switch (i.e., primary switch  102   a  or  102   b ) that is being turned off. 
     FIG. 3  shows isolated boost converter  300 , which does not suffer from the increased voltage stress on the primary switches discussed above. Isolated boost converter  300  was disclosed in the article “New Single-stage PFC Regulator Using Sheppard-Taylor Topology,” by C. K. Tse and M. H. L. Chow,  IEEE Trans. Power Electronics , vol. 13, pp. 842-851, September 1998. In isolated boost converter  300 , the maximum voltage stress on each of primary switches  102   a  and  102   b —which are turned on and off simultaneously—is clamped to the voltage of energy-storage capacitor  306  by clamp rectifiers  307   a  and  307   b . However, isolated converter  300  suffers from severe parasitic ringing across the primary winding  204  of transformer  203  due to the parasitic resonance in the leakage inductance of transformer  203  and the junction capacitance of rectifier  308 . The parasitic resonance degrades the performance isolation boost converter  300 . 
   SUMMARY OF THE INVENTION 
   The present invention provides a method and an isolated boost converter that exhibit substantially ringing-free waveforms across all semiconductor devices on both the primary side and the secondary side of a transformer. These ringing-free waveforms in the presence of the transformer&#39;s leakage inductance are achieved by (a) clamping the voltages of the primary switches and the rectifier or rectifiers to the voltage of the primary-side energy-storage capacitor, and (by using a capacitive filter that directly connects the rectifier output to the load to clamp the voltage across a secondary-side rectifier to the output voltage. 
   In a first embodiment of the present invention, an isolated boost converter includes a single boost inductor, two primary switches, primary-side clamping rectifiers, a primary-side energy-storage capacitor, an isolation transformer, a secondary-side rectifier, and a capacitive filter. The primary switches are turned on and off (i.e., conducting and non-conducting, respectively) simultaneously by a control circuit. When the switches are closed (i.e., rendered conducting), the energy stored in the boost inductor increases, while the energy stored in the primary-side energy-storage capacitor supplies the load. When the primary switches are open (i.e., rendered non-conducting), the input terminals are decoupled from the output terminals, and the energy stored in the boost inductor is transferred to the primary-side energy-storage capacitor. During this time (i.e., when the primary switches are open), the output filter capacitor supplies the load current. 
   According to a second embodiment of the present invention, an isolated boost converter includes three primary switches, two of which are simultaneously closed and opened, while the third switch is closed and opened before the opening and closing of the other two primary switches. Under this arrangement, the current stress on the secondary side components is substantially reduced because energy is transferred from the input to the output for a longer time than the first embodiment that has only the two primary switches. Specifically, in this second embodiment, the input-to-output energy transfer takes place when the third switch is closed, as well as during the subsequent period when the other two primary switches are closed. 
   Other embodiments of the present invention can be provided in numerous ways. Specifically, the secondary-side can be implemented either with a full-wave rectifier or a half-wave rectifier. In addition, in AC/DC applications, such as power-factor correction (PFC) applications, the isolated boost converters of this invention can be implemented without an input rectifier. 
   The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows current-fed push-pull DC/DC converter  100  in the prior art. 
       FIG. 2  shows two-inductor isolated boost converter  200  in the prior art. 
       FIG. 3  shows isolated boost converter  300  in the prior art. 
       FIG. 4  shows isolated boost converter  400 , in accordance to a first embodiment of the present invention. 
       FIG. 5  shows simplified circuit model  500  of isolated boost converter  400  of FIG.  4 . 
     FIGS.  6 ( a )- 6 ( h ) are topological stages illustrating the operations of isolated boost convertor  400  of  FIG. 4  during a switching cycle, using circuit model  500 . 
     FIGS.  7 ( a )- 7 ( l ) show waveforms of key signals in isolated boost converter  400  during the switching cycle of FIGS.  6 ( a )- 6 ( h ). 
       FIG. 8  shows key waveforms of converter  400  in  FIG. 4 , under discontinuous boost inductor current operation. 
       FIG. 9  shows isolated boost converter  900 , in accordance with a second embodiment of the present invention. 
       FIG. 10  shows simplified model  1000  of circuit in  FIG. 9 , showing reference directions of currents and voltages. 
     FIGS.  11 ( a )- 11 ( l ) are topological stages illustrating the operations of isolated boost converter  900  of  FIG. 9  during a switching cycle, using circuit model  1000 . 
     FIGS.  12 ( a )-( m ) show key waveforms of signals of converter  900  of FIG.  9 . 
       FIG. 13  shows isolated boost converter  1300 , which is an alternative implementation of converter  900  of  FIG. 9 , using a ground-referenced third switch. 
       FIG. 14  shows isolated boost converter  1400 , which is an alternative implementation of converter  400  of  FIG. 4 , using a half-wave rectifier. 
       FIG. 15  shows isolated boost converter  1500 , which is an alternative implementation of converter  900  of  FIG. 9 , using a full-wave rectifier and a center-tap transformer. 
       FIG. 16  shows isolated boost converter  1600 , which is an alternative implementation of converter  1300  of  FIG. 13 , using a full-wave rectifier and a center-tap transformer. 
       FIG. 17  shows isolated boost converter  1700 , having an AC input, but without input rectifier and full-bridge, full-wave output rectifier, in accordance with one embodiment of the present invention. 
       FIG. 18  shows isolated boost converter  1800 , having an AC input, but without input rectifier and full-wave output rectifier with center-tap transformer, in accordance with one embodiment of the present invention. 
   

   For clarity and for simplification of the detailed description below, like elements in the figures are provided like reference numerals. 
   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 4  shows a first embodiment of the present invention in isolated boost converter  400 . As shown in  FIG. 4 , on the input side, isolated boost converter  400  includes voltage source  417  at voltage V IN , boost inductor  401  with an inductance value L B , switches  402   a  and  402   b  (controlled respectively by signals S 1  and S 2 ), primary-side energy-storage capacitor  406  with a capacitance value C B , rectifiers  407   a ,  407   b  and  407   c  (D 1  through D 3 ), and primary winding  404  of transformer  403  (TR). On the output side, isolated boost converter  400  includes the secondary winding  405  of transformer  403 , which is connected to the full-bridge rectifier  408  implemented with rectifiers  409   a - 409   d  (D R1  through D R4 ), and filter capacitor  410  with capacitance value C F  connected across load  411  (resistance value R L ). 
   To illustrate the operation of isolated boost converter  400 ,  FIG. 5  provides simplified circuit model  500  of isolated boost converter  400  of FIG.  4 . In simplified circuit model  500 , energy-storage capacitor  406  and filter capacitor  410  are modeled by voltage sources  406   a  (V B ) and  410   a  (V O ), respectively, since capacitance value C F  of filter capacitor  410  is large enough, so that the voltage ripples (V r ) across capacitors  410  and  406  are small relative to their DC voltages. In addition, in  FIG. 5 , isolation boost transformer  403  is modeled by leakage inductor  403   a  (inductance value L LK ), magnetizing inductor  403   m  (inductance value L M ), and ideal transfermer  403   i  with a turns ratio n=N P /N S , where N P  is the number of turns in the primary winding and N S  is the number of turns in the secondary winding. In circuit model  500 , all semiconductor components are assumed to have no impedance, when conducting, and infinite impedance, when not conducting. 
   FIGS.  6 ( a )- 6 ( h ) are topological stages showing the operation of isolated boost conductor  400  of  FIG. 4  during a switching cycle, illustrated using circuit model  500 . FIGS.  7 ( a )- 7 ( l ) show waveforms of key signals in isolated boost converter  400  during the switching cycle of FIGS.  6 ( a )- 6 ( h ). In the operation of FIGS.  6 ( a )- 6 ( h ), the inductance value LB of boost inductor  401  is assumed to be large enough, so that input current i IN  does not flow to zero during the switching cycle. The reference directions of currents and voltages in FIGS.  7 ( a )- 7 ( l ) are indicated in FIG.  5 . 
   As illustrated by waveform  701  of FIG.  7 ( a ), control signals S 1  and S 2 , controlling primary switches  402   a  and  402   b , respectively, are simultaneously switched to render switches  402   a  and  402   b  to be in “on” and “off” states. The duty cycle D of isolated boost converter  400  is defined by the relative times of signals S 1  and S 2  in the “on” and “off” states of switches  402   a  and  402   b.    
   When switches  402   a  and  402   b  are open (e.g., during time interval T 0  and T 1 ), input current i IN  flows in diodes  407   a  and  407   b , as shown in FIG.  6 ( a ). Assuming that transformer  403  is in completely reset state at time To (i.e., magnetizing current i M  is zero), no other current flows in isolated boost converter  400  between times T 0  and T 1 , at which time switches  402   a  and  402   b  are switched to conducting states by signals S 1  and S 2 . Because voltage V B  across capacitor  406  is greater than voltage V IN  during time interval [T 0 , T 1 ], input current i IN  decreases with a substantially constant slope, as illustrated by waveform  705  of FIG.  7 ( e ). As a result, diode currents i D1  and i D2  (waveforms  709  and  710  of  FIG. 7 ) in rectifiers  407   a  and  407   b  each also decrease at the same rate as input current I IN  (waveform  705  of FIG.  7 ( e )): 
                 ⅆ     i   D1         ⅆ   t       =         ⅆ     i   D2         ⅆ   t       =         ⅆ     i   IN         ⅆ   t       =           V   IN     -     V   B         L   B       &lt;   0                 (   1   )             
 
   At time T 1 , when switches  402   a  and  402   b  both close, input current i IN  is diverted from diodes  407   a  and  407   b  to flow in switches  402   a  and  402   b , as illustrated in FIG.  6 ( b ). At the same time, primary current i PRIM  (waveform  706  of FIG.  7 ( f )) and secondary current i SEC  (waveform  711  of FIG.  7 ( k )) begin to flow because, after switches S 1  and S 2  close, voltage source  406   a  (which models energy storage capacitor  406 , at voltage V B ) appears in parallel with primary winding  404  of transformer  403 , so that voltages V PRIM  across primary winding  404  of transformer  403  equals voltage V B  across capacitor  406 . As secondary voltage V SEC  (waveform  712 , FIG.  7 ( l )) across secondary winding  405  of transformer  403  is positive during time interval [T 1 −T 2 ], secondary current i SEC  (waveform  711 , FIG.  7 ( k )) flows in rectifiers  409   b  (D R1 ) and  409   c  (D R4 ). As shown in FIG.  6 ( b ), during the [T 1 −T 2 ] interval, secondary current i SEC  is given by:
 
 i   SEC   =n·[i   PRIM   −i   M ]  (2)
 
In this model, primary current i PRIM  (waveform  706 , FIG.  7 ( f )) and magnetizing current i M  (waveform  707 , FIG.  7 ( g )) are given, respectively, by: 
               i   PRIM     =           V   B     -     nV   O         L   LK       ·   t             (   3   )                 i   M     =         nV   O       L   M       ·   t             (   4   )             
 
Thus, substituting the relevant expressions from equations (3) and (4) into equation (2), secondary current i SEC  is given by: 
               i   SEC     =     n   ·     [           V   B     -     nV   O         L   LK       -       nV   O       L   M         ]     ·     t   .               (   5   )             
 
   Therefore, during time interval [T 1 , T 2 ], primary current i PRIM , magnetizing current i M , and secondary current i SEC  each increase linearly from zero value, beginning at time T 1 , as illustrated by waveforms  706 ,  707  and  711  FIGS.  7 ( f ), ( g ), and ( k ), respectively. In addition, during this time interval (i.e., time interval [T 1 , T 2 ]), input current i N  (waveform  705 , FIG.  7 ( e )) also increases with a slope di IN /dt given by: 
                 ⅆ     i   IN         ⅆ   t       =           V   IN     +     V   B         L   B       .             (   6   )             
 
   At time T 2 , as shown in FIG.  7 ( a ), signals S 1  and S 2  open switches  402   a  and  402   b  simultaneously, so that the current flowing through switches  402   a  and  402   b  begins to charge output capacitors  413   a  (with capacitance C OSS1 ) and  413   b  (with capacitance C OSS2 ) of switches  402   a  and  402   b , as illustrated by the circuit model of FIG.  6 ( c ). During time interval [T 2 , T 3 ], voltages V S1  and V S2  (each illustrated by waveform  702  of FIG.  7 ( b )) across switches  402   a  and  402   b , respectively, increase toward voltage V B  across capacitor  406 . At the same time, voltages V D1  and V D2  across diodes  407   a  and  407   b  decrease toward zero at the same rate, as illustrated by waveforms  702  and  703  in FIGS.  7 ( b ) and ( c ). Due to the decreasing primary voltage V PRIM  across the primary windings  404  of transformer  403 , the rate of rise in primary current i PRIM  also decreases, to result in a corresponding decrease in the rate of current increase in secondary current i SEC . Magnetizing current i M  continues to increase at the same rate it has increased since time T 1  because the voltage across magnetizing inductor  403   m  remains unchanged at nV O . At time T 3 , output capacitors  413   a  and  413   b  of switches  402   a  and  402   b , respectively, are charged to voltage V B , so that diodes  407   a  and  407   b  begin to conduct, as illustrated by FIG.  6 ( d ). 
   After time T 3 , voltage source  406   a  is connected in opposite polarity to input voltage source  417 , so that input current i IN  decreases linearly with the slope given by equation (1). In addition, as primary voltage V PRIM  across the primary windings of transformer  403  is negative (i.e., V PRIM =−V B ), primary current i PRIM  (waveform  706 , FIG.  7 ( f )) also decreases linearly with a slope: 
                 ⅆ     i   PRIM         ⅆ   t       =     -           V   B     +     nV   O         L   LK       .               (   7   )             
 
Because both current i IN  and current i PRIM  decrease linearly, currents i D1  and i D2  in rectifiers  407   a  and  407   b , respectively, also decrease linearly, as illustrated by waveforms  709  and  710  of FIGS.  7 ( i ) and ( j ), until time T 4 , when primary current i PRIM  in the primary winding of transformer  403  equals magnetizing current i M . Thus, at time T 4 , secondary current i SEC  in the secondary winding of transformer  403  falls to zero.
 
   As illustrated by FIG.  6 ( e ), after time T 4 , secondary current i SEC  becomes negative, and rectifiers  409   a  and  409   d  (i.e., rectifiers D R2  and D R3 ) are conducting. At this time, primary current I PRIM  continues to flow through diode  407   c  (i.e., diode D 3 ). During time interval [T 4 , T 5 ], as the voltage across the secondary winding of transformer  403  is negative, the rate at which the primary current decreases toward zero is reduced to 
                 ⅆ     i   PRIM         ⅆ   t       =       -         V   B     -     nV   O         L   LK         &lt;   0.             (   8   )             
 
   At time T 5 , when primary current I PRIM  falls to zero, diode  407   c  ceases to conduct, so that diode&#39;s junction capacitance C D3  starts resonating with leakage inductor  403   a  (inductance L LK ), as illustrated in FIG.  6 ( f ). During this time, primary current I PRIM  charges junction capacitor  414  (capacitance C D3 ) of rectifier of diode  407   c  toward V B , as illustrated in FIG.  7 ( d ). The negative peak of primary current I PRIM  occurs at time T 6 , when voltage V D3  across rectifier  407   c  reaches V B , and clamp diode  408   b  (D 4 ) begins to conduct, thus providing a current path for primary current i PRIM , as illustrated in FIG.  6 ( g ). The magnitude of current I PRIM &#39;s negative peak is given by: 
               i   PRIM     PK   ⁡     (   NEG   )         =           V   B     -     nV   O             L   LK     /     C   D3           .             (   9   )             
 
   During time interval [T 6 , T 7 ], primary current i PRIM  increases linearly from the peak negative current of equation (9) toward zero, which is reached time T 7 . At time T 7 , diode  408   b  becomes non-conducting, and residual magnetizing current i M  is dissipated through the secondary winding of transformer  403 , as illustrated by FIG.  6 ( h ), until time T 8 ; when magnetizing inductor  403   m  is fully reset, as illustrated by waveform  707  of FIG.  7 ( g ). The next switching cycle is initiated at time T 9 , when signals S 1  and S 2  closes switches  402   a  and  402   b.    
   According to the detailed description of operation presented above, in converter  400  (FIG.  4 ), the energy stored in primary energy-storage capacitor  406  is transferred to load  411  during time interval [T 1 , T 2 ], when switches  402   a  and  402   b  are both close. In addition, during this time interval, the energy stored in boost inductor  401  is increasing. When signals S 1  and S 2  open switches  402   a  and  402   b , the energy stored in boost inductor  401  is transferred to primary-side energy-storage capacitor  406 , while load current in load  411  is supplied from output filter capacitor  410 . 
   Based on the volt-second balance on boost inductor  401 , voltage V B  of energy-storage capacitor  406  relates to input voltage V IN  (voltage source  417 ) by: 
                 V   B     =       1     1   -     2   ⁢   D         ·     V   IN         ,           (   10   )             
 
where D is the duty cycle of switches  402   a  and  402   b , defined as D=T ON /T S , where T ON  is the length of time during which switches  402   a  and  402   b  are conducting, and T S  is the length of the switching period of switches  402   a  and  402   b , as illustrated in FIG.  7 ( a ). According to equation (10), duty cycle D of converter  400  is less than or equal to 0.5.
 
   The relationship between output voltage V O  across load  411  and voltage V B  at energy storage capacitor  406  is derived by recognizing that load current I O  in load  411  equals the average rectified secondary current &lt;|i SEC |&gt;. That is,
 
 V   O   =R   L   I   O   =R   L   &lt;|i   SEC |&gt;  (11)
 
where R L  is the resistance of load  411 .
 
   Neglecting magnetizing current i M  by assuming that magnetizing inductance L M  of magnetizing inductor  403   m  is very (infinitely) large, and by assuming that time interval [T 2 , T 4 ] is much shorter than “on” time T ON  of switches  402   a  and  402   b , the average secondary current is given by 
               I   O     =       〈          i   SEC          〉     =           n   2     ⁢     D   2         2   ⁢     L   LK     ⁢     f   S         ·     [         V   B     n     -     V   O       ]                 (   12   )             
 
where f S =1/T S  is the switching frequency.
 
   From equations (10)-(12), the approximate voltage conversion ratio of the circuit in  FIG. 4  can be calculated as 
                     nV   O       V   IN       ≈       1     1   -     2   ⁢   D         -       2     nD   2       ·         I   O     ⁢     L   LK     ⁢     f   S         nV   IN             =       1     1   -     2   ⁢   D         -       2     nD   2       ⁢     I   ON           ⁢           ⁢   where           (   13   )                 I   ON     =         I   O     ⁢     L   LK     ⁢     f   S         nV   IN               (   14   )             
 
is the normalized output current. The expression for the voltage conversion ratio in equation (13) is valid for
 
0&lt;D&lt;0.5  (15)
 
and 
               I   ON     ≤       nD   3       1   -     2   ⁢   D                 (   16   )             
 
since nV O /V IN ≧1
 
   Equation (13) shows that the voltage conversion ratio depends not only on duty cycle D of switches  402   a  and  403   b , and turns ratio n of transformer  403 , but also on load current I O  in load  411 , as well as switching frequency f 5  of switches  402   a  and  402   b  and leakage inductance L LK  of transformer  403 . 
   In the operations described above, input current i IN  in boost inductor  401  does not decrease to zero during the “off” period when switches  402   a  and  402   b  are not conducting. However, converter  400  can operate in a mode where input current in boost conductor can fall to zero (i.e., “discontinuous boost inductor current”) during the “off” period, as illustrated by FIGS.  8 ( a )- 8 ( l ). Under discontinuous boost inductor current operation, when input current i IN  becomes zero at time T 9 , rectifiers  407   a  and  407   b  cease conducting and the reverse voltages in rectifiers  407   a  and  407   b  (i.e., V D1  and V D2 ) for the remainder of the switching period are each 0.5 (V B −V IN ), as illustrated in FIGS.  8 ( c ) and  8 ( e ), respectively. In addition, during time interval [T 9 , T 10 ], the voltages V S1  and V S2  across primary switches  402   a  and  402   b  each equal 0.5 (V B +V IN ), and voltage V D3  of rectifier  407   c  equals V IN . 
   In converter  400  of  FIG. 4 , substantial secondary current i SEC  flows in the secondary winding of transformer  400  when switches  402   a  and  402   b  are conducting, and, during a portion of the “off” period of switches  402   a  and  402   b , a relatively small magnetizing current i m  of magnetizing inductor  403   m  flows through the secondary winding of transformer  403  until the magnetizing inductance of magnetizing inductor  403   m  is reset. Because of the short duration of the secondary current flow (i.e., less than T S /2), as well as its triangular current waveform, a current stress exists in the secondary side of converter  400 . Providing an auxiliary switch  901  across rectifier  407   c , as shown in converter  900  of  FIG. 9 , can significantly reduce this secondary-side current stress in converter  400 . Switch  901  allows secondary current i SEC  to flow in both directions, thereby decreasing the peak current through the secondary side of converter  900 . 
   To facilitate the explanation of the operations of converter  900  in  FIG. 9 ,  FIG. 10  provides simplified circuit model  1000  of converter  900 . FIGS.  11 ( a )- 11 ( l ) are topological stages illustrating the operations of isolated boost converter  900  of  FIG. 9  during a switching cycle, using circuit model  1000 . FIGS.  12 ( a )-( m ) show key waveforms of signals of converter  900  during a switching cycle. The reference directions of currents and voltages used in FIGS.  12 ( a )-( m ) are shown in FIG.  10 . 
   As shown in FIGS.  12 ( a ) and ( b ), switch  901  is turned on by signal S 3  (waveform  1202 ) substantially before switches  402   a  and  402   b  are turned on by signals S 1  and S 2  (waveform  1201 ) simultaneously. Switch  901  is turned off before switches  402   a  and  402   b  are turned off. For proper operation, i.e., to avoid saturating transformer  403 , the time interval between switch  901  becomes conducting and switches  402   a  and  402   b  become conducting should be substantially equal to the time during which switches  402   a  and  402   b  are conducting. In converter  900 , to prevent transformer  403  from saturating due to a timing mismatch in drive signals S 1 , S 2  and S 3 , capacitor  902  (with a capacitance value C P ) is connected in series with primary winding  404  of transformer  404 . Since the DC voltage across blocking capacitor  902  is zero for ideally matched drive signals, and relatively small for slightly mismatched drive signals, the voltage across capacitor  902  can be neglected (i.e., assumed zero) in the following analysis. 
   As shown in FIGS.  12 ( a )-( b ), at time T 0 , switches  402   a ,  402   b  and  901  are in the “off” state, so that input current i IN  flows in rectifiers  407   a  and  407   b  (i.e., diodes D 1  and D 2 ), as illustrating in FIG.  11 ( a ). Assuming that at time T 0 , transformer  403  is completely reset (i.e. magnetizing current i M  is zero at time T 0 ), no other current is flowing in converter  900  until time T 1 , when switch  901  becomes conducting. As voltage V B  in a boost converter is greater than input voltage V IN , during time interval [T 0 , T 1 ], input current i N  decreases with a constant slope, as illustrated by waveform  1206  in FIG.  12 ( f ). As a result, currents i D1  and i D2  of rectifiers  407   a  and  407   b  also decrease with the slope given in equation (1) above. 
   At time T 1 , after switch  901  becomes conducting, primary current i PRIM  in primary winding  404  of transformer  403 , and secondary current i SEC  in secondary winding  405  of transformer  403  begin to flow because voltage V B  of voltage source  406   a , which models energy storage capacitor  406 , appears in parallel with primary winding  404  of transformer  403  (i.e., V PRIM =−V B ). During time interval [T 1 , T 2 ] secondary voltage V SEC  across secondary winding  405  of transformer  403  is negative, and secondary current I SEC  is carried by rectifiers  409   a  and  409   d  (i.e., diodes D R2  and D R3 ). As illustrated in FIG.  11 ( b ), secondary current i SEC  in secondary winding  405  of transformer  403  during time interval [T 1 , T 2 ] is given by:
 
 i   SEC   =n·[i   PRIM   +i   M ],  (17)
 
where primary current i PRIM  in primary winding  404  of transformer  403  and magnetizing current i M  in magnetizing inductor  403   m  are provided, respectively, by: 
               i   PRIM     =       -         V   B     -     nV   O         L   LK         ·   t             (   18   )                   i   M     =         nV   O       L   M       ·   t       ⁢     
     ⁢     Thus   ,             (   19   )                 i     S   ⁢           ⁢   EC       =     n   ·     [       -         V   B     -     nV   O         L   LK         +       nV   O       L   M         ]     ·   t             (   20   )             
 
   Equations (18) and (20) show that, during time interval [T 1 , T 2 ], primary current i PRIM  and secondary current i SEC  increase linearly in the negative direction from a zero value at time T 1 , as illustrated by waveforms  1207  and  1212  in FIGS.  12 ( g ) and ( l ). Also, during this time interval, input current i IN  (waveform  1206 ) and diode currents i D1  and i D2  (waveforms  1210  and  1211 , FIGS.  12 ( j ) and ( k )) continue to flow. The rate of decrease in input current i IN  is given by equation (1), and the rates of current decrease in diode currents i D1  and i D2  are given by: 
                 ⅆ     i   D1         ⅆ   t       =         ⅆ     i   D2         ⅆ   t       =           V   IN     -     V   B         L   B       -         V   B     -     nV   O         L   LK                   (   21   )             
 
   At time T 2 , when diode currents i D1  and i D2  of rectifiers  407   a  and  407   b  respectively become zero, as illustrated in FIG.  11 ( c ), input current i IN  and primary current i PRIM  (waveform  1207 , FIG.  12 ( g )) in primary winding  404  of transformer  403  are equal, and continue to decrease with the same rate, as given by equation (1), until switches  402   a  and  402   b  are simultaneously turned on by signals S 1  and S 2  (waveform  1201 , FIG.  12 ( a )) at time T 3 . As seen from FIG.  11 ( c ), during time interval [T 2 , T 3 ], voltages V D1  and V D2  across rectifiers  407   a  and  407   b  are given by: 
               V   D1     =       V   D2     =       1   2     ⁢     (       nV   O     -     V   B     +       L   LK     ⁢       ⅆ     i   PRIM         ⅆ   t           )                 (   22   )             
 
   At the beginning of time interval [T 3 , T 4 ], primary voltage V PRIM  across primary winding  404  of transformer  403  changes polarity (i.e., V PRIM =V B ), and primary current i PRIM  begins to increase, thereby causing corresponding increases in switch currents i S1  and i S2  (waveform  1209 , FIG.  12 ( i )) of switches  402   a  and  402   b , and in secondary current i SEC  (waveform  1212 , FIG.  12 ( l )) in secondary winding  405  of transformer  403 . The rate of increase in primary current i PRIM  is given by 
                 ⅆ     i   PRIM         ⅆ   t       =         V   B     +     nV   O         L   LK               (   23   )             
 
   At time T 4 , as illustrated in FIG.  11 ( e ), secondary current i SEC  becomes zero, so that rectifiers  409   a  and  409   d  (i.e., D R2  and D R3 ) stop conducting and secondary current i SEC  starts flowing through rectifiers  409   b  and  409   c  (i.e., D R1  and D R4 ). At time T 4 , secondary voltage V SEC  (waveform  1213 , FIG.  12 ( m )) changes polarity, so that the rate of change of primary current i PRIM  changes to 
                 ⅆ     i   PRIM         ⅆ   t       =         V   B     -     nV   O         L   LK               (   24   )             
 
thereby causing corresponding changes in the rates of change in currents is i S1 , i S2 , and i SEC , as shown in waveforms  1209  and  1212 , FIGS.  12 ( i ) and ( l ), respectively.
 
   After primary current i PRIM  changes polarity at time T 5 , switch  901  is turned off by signal S 3  under zero voltage switching (“ZVS”) condition. As illustrated in FIG.  12 ( b ), switch  901  is turned off by signal S 3  at time T 6 , just before switches  402   a  and  402   b  are turned off by signals S 1  and S 2  to minimize the conduction time of the body diodes in these switches. Once switch  901  is turned off, and primary current i PRIM  is diverted to the body diodes of the switches, the operations of converter  900  for the remainder of the switching cycle are substantially the same as those of converter  400  of FIG.  4 . Specifically, the operations of converter  900  of  FIG. 9  between times T 6  and T 12  are substantially the same as the operations of converter of  FIG. 4  between times T 2  and time T 8 . To simplify this detailed description, the operations of converter  900  of  FIG. 9  between times T 6  and T 12  are not described, but disclosed graphically in FIGS.  11 ( g )-( l ). The operations of converter  900 , as illustrated in FIGS.  11 ( g )-( l ) are substantially similar, therefore comparable, to the operations of converter  400 , as illustrated in FIGS.  6 ( c )-( h ). 
   Converter  900  of  FIG. 9  can also be implemented with a ground-referenced third switch  1301 , as shown in FIG.  13 . In isolated boost converter  900 , switch  901  requires a high-side driver. In isolated boost converter  1300 , a more cost-effective low-side driver is used to for switch  1301 . 
   Isolated boost converters  900  and  1300  of  FIGS. 9 and 13 , respectively, can also each be implemented with a different drive-signal timing. Specifically, switches  402   a  and  402   b  can be turned on simultaneously before switch  901  or  1301  is turned on and switches  402   a  and  402   b  can be turned off substantially before switch  901  or  1301  is turned off. Such switching sequence in the main and auxiliary switches allows switch  901  or  1301  to achieve ZVS conditions, and to extended the range of operation of the circuit when boost inductor  401  operates in the discontinuous current mode (“DCM”). The switching pattern shown in FIGS.  12 ( a ) and  12 ( b ) is preferred when elimination of the reverse-recovery-related losses and EMC problems of rectifiers  407   a  and  407   b  (i.e., diodes D 1  and D 2 ) is a priority. 
   The waveforms of secondary current i SEC  of converters  900  and  1300 , respectively shown in FIGS.  7 ( k ) and  12 ( l ), show that, for the same average rectified secondary current i SEC , the peak of secondary current i SEC  in converter  900  of  FIG. 9  is approximately one-half of that of converter  400  of FIG.  4 . Further, the voltage conversion ratio of converter  900  of  FIG. 9  is given by 
                 nV   O       V   IN       ≈       1     1   -     2   ⁢   D         -       1     nD   2       ⁢     I   ON                 (   25   )             
 
where I ON  is defined in equation (14) and the range of duty cycles D is 0 to 0.5.
 
   Isolated boost converters of the present invention can be implemented with a different types of rectifiers. For example,  FIG. 14  shows converter  1400 , which is an alternative implementation of converter  400  of  FIG. 4 , using half-wave rectifier  409 . Similarly,  FIGS. 15 and 16  show isolated boost converters  1500  and  1600 , respectively, which are alternative implementations of isolated boost converter  900  of  FIG. 9 , using full-wave rectifier consisting of rectifiers  1501   a  and  1501   b , and transformer  1503  having a center-tap secondary winding. 
   When used in AC/DC applications, such as PFC applications, the isolated boost converters of the present invention can be implemented without an input rectifier. For example,  FIG. 17  shows isolated boost converter  1700  for use in an AC/DC application, without requiring an input rectifier that employs full-bridge, full-wave output. As shown in  FIG. 17 , the primary side of converter  1700  includes primary switches  402   a - 402   f , and can be viewed as a combination of two three-switch boost converters, such as converters  900  and  1300  of  FIGS. 9 and 13  by replacing rectifiers  407   a  and  407   b  by switches  402   a  and  402   d . During each line half cycle, isolated boost converter of  FIG. 17  operates in a manner similar to converter  900  of FIG.  9 . Specifically, during the positive line half cycles, switches  402   a ,  402   c  and  402   e  are periodically turned on and off while switches  402   b ,  402   d , and  402   f  are kept continuously off. Similarly, during the negative line half cycles, switches  402   b ,  402   d , and  402   f  are periodically turned on and off while switches  402   a ,  402   c  and  402   e  are kept continuously off. Isolated boost converter  1700  can also be implemented using different output rectifiers. For example, isolated boost converter  1800  of  FIG. 18  shows an alternative implementation of isolated boost converter  1700 , using full-wave rectifier  1501 , consisting of rectifiers  1501   a  and  1501   b , and transformer  1503  with a center-tap secondary winding. 
   In addition, isolated boost converters of the present invention can be implemented with, for example, passive snubbers to optimize circuit performance. Generally, any known snubber can be employed. 
   The detailed description above is provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is set forth in the following claims.