Patent Publication Number: US-2021167775-A1

Title: Multi-channel multiplexer

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 16/700,444, filed Dec. 2, 2019, which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     Some applications include a sensor processing system and a multiplexer. One or more sensors may be coupled to the multiplexer. The sensors are coupled to the processing system through the multiplexer. The multiplexer includes multiple channels, with each channel potentially coupled to a separate sensor. The processing system processes the signal from one sensor at a time, To receive and process a signal from a given sensor coupled to one of the channels, control signals to the multiplexer enable the channel corresponding to the desired sensor while disabling the remaining channels of the multiplexer. 
     SUMMARY 
     In one example, a circuit includes first, second, and third switch assemblies, a buffer, and a bulk biasing circuit. The first switch assembly has a first input node and a first output node. The second switch assembly has a second input node and a second output node. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node. The third output node is coupled to the first output node. The third switch assembly includes a first transistor that includes a bulk. The buffer has a buffer input and a buffer output. The buffer input is coupled to the first output node, and the buffer output is coupled to the third switch assembly. The bulk biasing circuit is coupled to the bulk of the first transistor. The bulk biasing circuit is configured to bias the bulk of the first transistor at a first bias voltage responsive to a voltage on the input node being above a first voltage level, and to bias the bulk of the first transistor at a second bias voltage responsive to the voltage on the input node being below a second voltage level. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a detailed description of various examples, reference will now be made to the accompanying drawings in which: 
         FIG. 1  illustrates an example of a multi-channel system. 
         FIG. 2  shows an example implementation of a switch included within the multi-channel system. 
         FIG. 3  illustrates another example of a multi-channel system including a buffer to reduce leakage current through channels that are off. 
         FIG. 4  illustrates another example of a multi-channel system including a buffer to reduce leakage current through channels that are off. 
         FIG. 5  shows an example implementation of the buffer. 
         FIG. 6  shows an example of a circuit including a portion of the multi-channel system and including the buffer and a bulk biasing circuit to reduce leakage current through channels that are off. 
     
    
    
     DETAILED DESCRIPTION 
     A multiplexer may include a number of independent channels that pass data from respective inputs to a single output, and, in a sensing application, the multiplexer may pass data from a set of sensors coupled to the inputs to a processor coupled to the output. Control signals from a multiplexer controller enable one of the channels, while those channels corresponding to sensors not intending to be processed by a sensor processing system at a given point in time are disabled. Each channel of the multiplexer comprises solid-state switches (transistors) that are used to enable and disable the channel. When a transistor is “on,” current can be conducted through the transistor. When a transistor is “off,” the principal conducting pathway (e.g., the channel in a metal oxide semiconductor field effect transistor) is off and generally does not conduct current. However, leakage current may conduct through the transistor when the transistor is off. 
     In many applications, transistor leakage current is not problematic. In other applications, however, leakage current can be a problem. For example, in the application noted above in which multiple sensors are coupled to a processing system through a multiplexer, even when the transistors are off for a channel that has been disabled, leakage current can still flow through that channel&#39;s transistors. If the sensor connected to that channel has a large output impedance, even a small amount of leakage current can cause a significant voltage to develop across the sensor due to the sensor&#39;s large output impedance. The voltage undesirably produced in the disabled channel can modify (e.g., add to) the voltage produced by the sensor whose channel is enabled, thereby undesirably altering the sensor signal intended to be processed. 
     The examples disclosed herein are directed to a multiplexer in which each channel of the multiplexer includes multiple metal oxide semiconductor field effect transistors (MOS transistors). One or more of the multiplexer&#39;s channels biases the bulk of at least one of its MOS transistors to reduce the leakage current that might otherwise be present for a low amplitude voltage generated by the sensor on the channel that is enabled. Further, a buffer is provided whose input coupled to the output of the multiplexer. The output of the buffer is coupled to one or more of the multiplexer&#39;s channels. When a given channel is off, rather than grounding an internal node of the given channel, the internal node is coupled to the multiplexer&#39;s output voltage level via the buffer. As such, the drain-to-source potential difference across a MOS transistor in each ‘off’ channel is approximately 0 V and thus very little, if any leakage current will flow between the drain and source of the transistor. 
       FIG. 1  shows an example of a system  100  comprising a multiplexer (“mux”) circuit  110  coupled to an operational amplifier (“op amp”)  130 . The mux circuit  110  comprises multiple channels. In this example, the mux circuit  110  includes five channels shown at  101 ,  102 ,  103 ,  104 , and  105 . Each channel is coupled to a respective input, and the inputs of channels  101 - 105  are designated inp 1 , inp 2 , inp 3 , inp 4 , and inp 5 , respectively. A device such as a sensor can be connected to each channel input. In this example, five sensors (S 1 , S 2 , S 3 , S 4 , S 5 ) can be coupled to the op amp  130  through the mux circuit  110 . Via control signals from a mux controller  140  (in response to a channel selection signal  139 ) to the mux circuit  110 , one channel at a time is enabled (on), and the remaining four channels are disabled (off). The signal from the sensor whose channel is enabled is provided through the mux circuit  110  to node N 1  and thus to the non-inverting (+) input of the op amp  130 . The op-amp  130  has its output connected to its inverting (−) input, and thus the op-amp  130  is configured for unity gain. Other configurations of the op-amp (e.g., gain greater than 1) are possible as well. The output from the op-amp  130  is coupled to a processing system  150  to process the op-amp&#39;s output signal. The processing system  150  may include a microprocessor, a filter, or other types of processing electronics. 
     The mux circuit  110  includes a switch assembly for each channel. Channel  101  has switch assembly  111 , and channels  102 - 105  have switch assemblies  112 - 115 , respectively. Input inp 1  can be coupled to node N 1  when switch assembly  111  is “on”. Similarly, any of inputs inp 2 -inp 5  can be coupled to node N 1  when their respective switch assemblies  111 - 115  are on. Node N 1  is connected to the op amp&#39;s non-inverting input. In this example, only one switch assembly  111 - 115  is turned on at a time, and the remaining switch assemblies are turned off. 
     In the example of  FIG. 1 , each switch assembly  111 - 115  comprises three switches S 1 , S 2 , and S 3 . S 1  and S 2  are connected in series between their associated channel input and node N 1 . The mux controller  140  generates the control signals to the switches S 1 -S 3  of the switch assemblies  111 - 115  to turn on or off each respective switch. The node between S 1  and S 2  is designated node N 2 . S 3  of each switch assembly is coupled between node N 2  and ground. When S 3  is on, the respective node N 2  is coupled to the ground potential. To turn a switch assembly on and thereby enable the channel, its switches S 1  and S 2  are turned on and its switch S 3  is turned off. To turn a switch assembly off and thereby disable the channel, its switches S 1  and S 2  are turned off and its switch S 3  is turned on. As shown in the example of  FIGS. 1 , S 1  and S 2  of switch assembly  111  are on and the corresponding switch S 3  is off. S 1  and S 2  of the remaining four switch assemblies  112 - 115  are off, and their switches S 3  are on. As such, channel  101  is enabled in this example, and channels  102 - 105  are off. 
     Even when a channel&#39;s switch assembly is configured to be off (its S 1  and S 2  are off, and its S 3  is on), leakage current can still flow through S 2 . Leakage currents Ileak 1 , Ileak 2 , Ileak 3 , and Ileak 4  are shown in  FIG. 1  to represent the leakage current through S 2  of off switch assemblies  112 - 115 . Part of the reason for the leakage current stems from the fact that the channel that is on (channel  101  in this example) provides the voltage from its input inp 1  through switch assembly  111  to node N 1 , and all of the switch assemblies  111 - 115  are coupled to node N 1  as shown. Thus, the voltage on node N 1  from channel  101  is also provided to one terminal of S 2  of the four off switch assemblies  112 - 115 . As the output impedance of a sensor connected to a channel input can be relatively high (e.g., hundreds of mega-ohms), even a small amount of leakage current can generate a voltage across the output impedance of that channel. The voltage due to leakage current from an off channel is additive (or subtractive depending on the direction of the leakage current) to the voltage generated by the sensor from the on channel, and thus distorts that sensor&#39;s signal. 
       FIG. 2  shows an example implementation of switch S 2  of each of the switch assemblies  111 - 115 . The reason for the leakage current can be identified through a discussion of  FIG. 2 . Referring to  FIG. 2 , S 2  of each switch assembly  111 - 115  includes a p-type MOS (PMOS) transistor MP 1  coupled to an n-type MOS (NMOS) transistor MN 1 . The drains of MP 1  and MN 1  are connected together at node N 1 , and the sources of MP 1  and MN 1  are connected together at node N 2 . The gates of MP 1  and MN 1  are driven by control signals to turn the transistors of S 2  on and off. To turn S 2  on, both MP 1  and MN 1  are turned on. To turn S 2  off, both MP 1  and MN 1  are turned off. In the example configuration shown in  FIG. 2 , the gate of MN 1  is driven by a low (e.g., ground) control signal, and the gate of MP 1  is driven by a high control signal (shown as Vdda, which is a supply voltage). With the gate of MN 1  driven low and the gate of MP 1  driven high, both MP 1  and MN 1  are off. As such,  FIG. 2  shows the off state for S 2 . 
     A MOS transistor has parasitic bulk diodes.  FIG. 2  shows a drain-to-bulk diode D 1  and a bulk-to-source diode D 2  of MP 1 . As explained above, the voltage on node N 1  is driven by the sensor whose switch assembly is on. S 2  in  FIG. 2  represents an S 2  switch of a switch assembly that is off. The voltage labeled Vin represents the voltage on node N 1  from a sensor of another channel that is on (e.g., channel  101 ). Node N 2  of S 2  in  FIG. 2  receives the ground potential through S 3  (which is on) of the respective switch assembly. The bulk of S 2 &#39;s MP 1  is biased to Vdda. 
     S 2  has multiple sources of leakage current when S 2  is off. First, when Vin is 0 V (e.g., the voltage from the sensor coupled to the on-channel  101 ), D 1  is reverse biased, thereby causing a current Ib 1  to flow through D 1 . As such, the leakage current Ileak (when Vin is low, e.g. 0 V) is equal to −Ib 1 +Idsn (Idsn is the leakage current through MN 1 ). However, Idsn may be substantially smaller than Ib 1 , and thus Ileak is approximately equal to −Ib 1 . Second, when Vin is higher (e.g., Vdda), Ileak is equal to the sum of the drain-to-source leakage currents of MP 1  and MN 1  (Idsp+Idsn). Both Idsp and Idsn are proportional to Vin (e.g., the larger is Vin, the larger will be Idsp and Idsn). Some examples described herein reduce the leakage current Ileak through S 2  of the switch assemblies, when such switch assemblies are off, by the use of a buffer (e.g., buffer  310  in  FIG. 3  and buffer  410  in  FIG. 4 ) as well as a bulk biasing circuit  610  ( FIG. 6 ) 
       FIG. 3  shows an example of a system  300  including mux circuit  110 , op amp  130 , and a buffer  310 . The sensors S 1 -S 5 , mux controller  140 , and processing system  150  are not shown for simplicity. The architecture of system  300  is largely the same as that of system  100  of  FIG. 1 , except for the inclusion of buffer  310 . In system  100  of  FIG. 1 , each switch S 3  is coupled between its respective node N 2  and ground. When S 3  is on in  FIG. 1 , the respective node N 2  is grounded. Grounding node N 2  results in leakage current through the MP 1  and MN 1  transistors of S 2  when node N 1  is of a sufficiently high voltage relative to ground. Buffer  310  of  FIG. 3  is coupled between node N 1  and switches S 3  of switch assemblies  112 - 115  at node N 3 . The buffer  310  is configured for unity gain, and thus the buffer&#39;s output voltage (node N 3 ) is equal to its input voltage (node N 1 ). The voltage on N 1  is approximately equal to the voltage produced by the sensor whose switch assembly is on (switch assembly  111  in the example of  FIG. 3 ). As such, the voltage on N 3  also is equal to the voltage on N 1 . 
     In the example of  FIG. 2 , N 2  is coupled to ground when S 3  is turned on. By grounding N 2 , a large enough drain-to-source voltage develops across MP 1  and MN 1  to cause leakage currents Idsp and Idsn to flow through MP 1  and MN 1 . In  FIG. 3 , instead of grounding N 2  in switch assemblies  112 - 115 , N 2  is coupled N 3 , which has approximately the same voltage as on N 1 . As such, a much lower drain-to-source voltage (approximately 0 V) develops across MP 1  and MN 1  for S 2  of switch assemblies  112 - 115 . Advantageously, when channel  101  is enabled and channels  102 - 105  are disabled much lower leakage current results through MP 1  and MN 1  of S 2  of switch assemblies  112 - 115  by the use of buffer  310  when Vin is significantly greater than 0 V (as might be caused by the use of enabled channel  101 ). 
     Because buffer  310  drives all of switches S 3  of switch assemblies  112 ,  113 ,  114 , and  115 , buffer  310  is sized to be large enough to power all four switches S 3  of switch assemblies  112 ,  113 ,  114 , and  115 . 
       FIG. 4  shows an example system  400  including a mux circuit  402 , op amp  130 , buffer  410 , switch assembly  430 , and switch S 4 . The sensors S 1 -S 5 , mux controller  140 , and processing system  150  are not shown for simplicity. Mux circuit  402  has an architecture similar to that of mux circuit  110  described above. Mux circuit  402  includes switch assemblies  111 - 115 . The node interconnecting all switches S 2  of switch assemblies  112 - 115  is labeled N 4  in  FIG. 4 . Switch assembly  430  is coupled between node N 4  and the output of buffer  410 . Switch assembly  430  has a similar architecture as that of switch assemblies  111 - 115 . Switch assembly  430  includes switches S 5 , S 6 , and S 7  as shown. Switches S 5  and S 6  are coupled in series between nodes N 1  and N 4 . The node between S 5  and S 6  is designated the intermediate node (INT). S 7  is coupled between INT and the output of buffer  410 . 
     Buffer  410  generates an output voltage which is approximately equal to its input voltage (voltage on node N 1 ). Buffer  410  in  FIG. 4  drives switch assembly  430 , rather than directly driving switch assemblies  112 - 115 . As a result of driving one switch assembly  430 , buffer  410  can have a lower output current requirement and thus be smaller than buffer  310  of  FIG. 3 . 
     When switch assembly  111  is to be on (as is the case in the example of  FIG. 4 ), switch assemblies  112 - 115  and  430  are turned off, and switch S 4  is turned on. S 4  is coupled between node N 4  and ground. By turning S 4  on, node N 4  is grounded. Little or no leakage current flows through switch assemblies  112 - 115  as well as  430  when switch assembly  111  is enabled and switch assemblies  112 - 115 ,  430  are off. Buffer  410  provides the same benefit to switch assembly  430  to reduce its leakage current as described above regarding buffer  310 . If any of inputs inp 2 -inp 4  are to be used, then the switch assembly of that particular input is turned on, and the remaining switch assemblies from among switch assemblies  111 - 115  as well as S 4  are turned off and switch assembly  430  is turned on. 
       FIG. 5  shows an example implementation of buffer  410  (or  310 ) coupled to an input stage  510  of op amp  130 . The input stage  510  includes transistors M 1 -M 5 . In this example input stage, M 1 , M 2 , and M 5  are PMOS transistors, and M 3  and M 4  are NMOS transistors. M 5  is a current source device, whose gate is biased at a voltage labeled BIAS 1  and produces a tail current, Itail. M 1  and M 2  comprise a differential transistor pair. The sources of M 1  and M 2  are connected together and to the drain of M 5 . The positive (+) input of op amp  130  is coupled to the gate of M 1  and is designated IN_P. The negative (−) input of op amp  130  is coupled to the gate of M 2  and is designated IN_M. The gates of transistors M 3  and M 4  are biased at a voltage labeled BIAS 2 . 
     The buffer  410  comprises transistors M 6 , M 7 , and M 8 . M 6  and M 8  in this example comprise PMOS transistors, and M 7  comprises an NMOS transistor. The gate of M 8  is biased a voltage labeled BIAS 3 , and the source of M 8  is connected to the supply voltage, Vdda. In one example, BIAS 3  equals BIAS 1 . The drain of M 8  is connected to the source of M 6  and to node N 5 . As such, the M 8  drain and M 6  source are connected to the op amp input stage  510  at node N 5 . The drains of M 6  and M 7  are connected together and to the gate of M 6  at node N 6 . Node N 6  represents the output of the buffer  410 , which is connected to node N 3  in  FIG. 3  and, in the case of buffer  410 , to switch S 3  of switch assembly  430  in  FIG. 4 . The gate of M 7  is biased at a voltage labeled BIAS 4 , and the source of M 7  is connected to ground. In one example, BIAS 4  equals BIAS 2 . 
     The current through M 8  is labeled I 1 . Current I 1  is a function, in part, of the size of M 8  (ratio of its channel width (W) to channel length (L)) and the gate-to-source voltage (Vgs) of M 8 . The source of M 8  is tied to Vdda, and the gate of M 8  is BIAS 3 . As such, BIAS 3  and the ratio of channel width to length of M 8  define the magnitude of current I 1 . If BIAS 3  equals BIAS 1 , I 1  will be one-sixteenth Itail if W/L of M 8  is one-sixteenth W/L of M 5 . In one example, BIAS 3  and the channel width to length ratio of M 8  result in a magnitude of I 1  that is one-sixteenth the magnitude of Itail, and that fraction can be different than one-sixteenth in other examples. Further, the ratio of channel width to length of M 6  is one-eighth the size of the ratio of channel width to length of M 1  or M 2  (which are themselves of equal size). The sources of M 1 , M 2 , and M 6  are connected together at node N 5 . The current density through M 6  is the same as that of M 1  and M 2 . That is, while I 1  through M 6  is Itail/ 16 , W/L of M 6  is one-eighth the W/L of M 1  or M 2 . Due to the output of the op amp  130  being connected to its negative input (IN_M) as shown in  FIG. 4 , IN_P remains generally equal to IN_M. Because the source voltage of M 6  is equal to the source voltage of M 1  and M 2 , and the current densities are the same, the gate voltage of M 6  will be equal to the gate voltages IN_P or IN_M of M 1  and M 2 , respectively. As such, the output voltage of buffer  410  on node N 6  will be approximately equal to IN_P. 
     As explained above regarding  FIG. 2 , when Vin is a relatively low voltage, if the bulk of the MP 1  transistor is biased at the supply voltage (Vdda), the drain-to-bulk parasitic diode D 1  of switches S 2  of the switch assemblies  112 - 115  are reversed biased, thereby causing a leakage current to flow through each such switch S 2 . 
       FIG. 6  shows a system  600  in which the bulk of the PMOS transistors of the switches S 2  is biased at a voltage lower than Vdda when Vin is a low voltage. 
     The example system  600  in  FIG. 6  includes the input stage  510  of op amp  130 , the buffer  410 , a bulk biasing circuit  610 , switches S 1 , S 2 , and S 4 , and switch assembly  430 . ISRC 1  in buffer  410  represents M 8  in  FIG. 5 . In this example, switch S 6  of switch assembly  430  comprises transistors M 10  and M 11 . Further, switch S 5  comprises transistors M 12  and M 13 . Switch assembly  430  is shown in its off state, and thus switch S 7  is on. S 7  is shown in its symbolic form. In some implementations, S 7  comprises a single transistor or a pair of PMOS/NMOS transistors. M 10  and M 12  comprise PMOS transistors, and M 11  and M 13  comprise NMOS transistors. The sources of M 10  and M 11  are connected together, and connect to the IN_P input (gate of M 1 ) of the op amp&#39;s input stage  510 . The drains of M 10  and M 11  are connected together at node INT. S 7  is shown in its closed (on) state to couple INT to the output of the buffer  410  (node N 6 ). The sources of M 12  and M 13  are also connected to INT. The drains of M 12  and M 13  are connected together at node N 4 , which is provided to the switch assemblies  112 - 115  as shown in  FIG. 4 . Switch S 4  is coupled between node N 4  and ground, and is closed (on) when switch assembly  430  is off. When switch assembly  430  is off, S 5  and S 6  are off. For S 5  and S 6  to be off, the gates of PMOS transistors M 10  and M 12  are provided with the supply voltage (Vdda) as shown, and NMOS transistors M 11  and M 13  are provided with a ground voltage as shown. 
     S 1  comprises transistors M 14  and M 15 , and S 2  comprises transistors M 16  and M 17 . In this example, M 14  and M 16  comprise PMOS transistors, and M 15  and M 17  comprise NMOS transistors. The drains of M 15  and M 16  are connected together at the input inp 1  of channel  101 . The sources of M 16  and M 17  are connected together at node N 1  to which the gate of M 1  within the op amp&#39;s input stage  510  is connected. The configuration of  FIG. 6  illustrates switch assembly  111  in its on state, and thus the gates of PMOS transistors M 14  and M 16  are grounded to turn on M 14  and M 16 , and the gates of NMOS transistors M 15  and M 17  receive the supply voltage, Vdda, to turn on M 15  and M 17 . Further, switch S 3  ( FIG. 4 ) of switch assembly  111  is turned off, and thus node N 2  is not pulled to ground. S 3  is not shown in  FIG. 5 . 
     Example bulk biasing circuit  610  includes transistors M 18  and M 19 . In this implementation, M 18  and M 19  are PMOS transistors. The source of M 18  is connected to Vdda, and the drain of M 18  is connected to the source of M 19  at node N 7 . The drain of M 19  is connected to ground. The bulk of M 19  is connected to M 19 &#39;s source. With M 19  configured as a source-follower, current I 2  flows in the branch from Vdda through M 18  and M 19  to ground. The voltage on the source of M 19  is one threshold voltage (approximately 1 V) above the gate voltage of M 19 . The signal on the gate of M 19  is the voltage on node N 1 . The voltage on N 1  will be low when switch assembly  111  is on (S 1  and S 2  are on) and the voltage on inp 1  is low, Current I 2  flows through M 19  resulting in the voltage on the source of M 19  being approximately 1 V greater than its gate voltage (N 1 ). Node N 7  is coupled to the bulks of M 1  and M 2  within the op amp&#39;s input stage and to the bulk of M 10  within switch S 6 , as well as the bulk of M 16  of S 2  within switch assembly  111 . The corresponding bulk of PMOS transistor of S 2  of the other switch assemblies  112 - 115  also may be coupled to node N 7  as well. The voltage on node N 7  is used to bias the bulks of M 1  M 2 , and M 10 . When the input inp 1  is low enough so as to turn on M 10 , the voltage on node N 7  will be pulled down to approximately 1 V above the voltage on inp 1 , and thus the bulks of M 1 , M 2 , and M 10  are biased to a voltage much lower than Vdda (e.g., 1 V). With the bulk of M 10  biased to a voltage substantially lower than Vdda, the bulk-to-source parasitic diode D 3  of M 10  will be biased with a voltage much closer to 0 V than if the bulk of M 10  were biased to Vdda. With D 3  biased to 0 V, or a relatively small voltage, the leakage current through D 3  will be much smaller than would be the case if D 3  were biased by a larger voltage. By biasing the bulk of PMOS M 10  within switch assembly  430  to a lower voltage when the voltage on inp 1  is small (than when inp 1  has a larger voltage), the leakage current through switch assembly  430  is reduced compared to persistently biasing the bulk of M 10  at Vdda. 
     The term “couple” is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with the description of the present disclosure. For example, if device A generates a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.