Patent Publication Number: US-8974024-B2

Title: Liquid discharge apparatus

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to Japanese Patent Application No. 2013-059503 filed on Mar. 22, 2013. The entire disclosure of Japanese Patent Application No. 2013-059503 is hereby incorporated herein by reference. 
     BACKGROUND 
     1. Technical Field 
     The present invention relates to a liquid discharge apparatus. 
     2. Related Art 
     One known inkjet printer for discharging ink to print an image or document uses piezoelectric elements (for example, piezo elements). The piezoelectric elements are provided so as to respectively correspond to a plurality of nozzles in a print head and each, by being driven in conformity with a control signal, causes a predetermined amount of ink to be discharged from the nozzles at a predetermined timing. The piezoelectric elements, when viewed electrically, are a capacitive load similar to a capacitor, and therefore a sufficient electrical current needs to be supplied in order to actuate the piezoelectric elements of each of the nozzles. 
     For this reason, a conventional configuration has been to amplify an original signal with an amplifier circuit and supply the amplified control signal to the print head to drive the piezoelectric elements. Electrical current amplifier circuits include a format where the original signal undergoes electrical current amplification with a class AB or the like (linear amplification; see Japanese laid-open patent publication 2009-190287), or a format where the original signal is modulated by pulse width modulation, pulse density modulation, or the like, and then demodulated with a low-pass filter (class D amplification; see Japanese laid-open patent publication 2010-114711), and so forth. 
     Beyond amplifying the original signal with an amplifier circuit, a format in which the voltage applied to the piezoelectric elements is switched at a plurality of stages (voltage switching format; see Japanese laid-open patent publication 2004-153411) has also been proposed. 
     SUMMARY 
     However, linear amplification consumes a considerable amount of power, and has poor energy efficiency. Class D amplification does have better energy efficiency compared to linear amplification, but is problematic in that switching a large current at a high frequency creates electromagnetic interference (EMI). The voltage switching format described above, too, makes it possible to conserve power, but because of the stepwise switching of the voltage applied to the piezoelectric elements every time a pulse signal (CK) is inputted, a voltage other than a plurality of voltages that are prepared in advance cannot be selected for the start voltage and end voltage of the voltage waveform applied to the piezoelectric elements. For this reason, the voltage switching format described above is problematic in that it is difficult to finely control the piezoelectric elements. 
     Therefore, one objective of several aspects of the present invention is to provide a liquid discharge apparatus with which energy efficiency is high, the occurrence of EMI is reduced, a capacitive load such as piezoelectric elements is finely controlled, and the power consumed in a print head is reduced. 
     A liquid discharge apparatus according to one aspect includes a discharge section, a charge supply source, first and second signal paths, and a connection path selection section. The discharge section includes a nozzle configured and arranged to discharge a liquid, a pressure chamber in communication with the nozzle, and a piezoelectric element provided for the pressure chamber. A first voltage is applied by the charge supply source through the first signal path. A second voltage higher than the first voltage is applied by the charge supply source through the second signal path. The connection path selection section is configured to use the first signal path or the second signal path to electrically connect the piezoelectric element and the charge supply source. The charge supply source include a number n (where n is a plurality) of capacitive elements, and a switching section configured and arranged to switch between a series state where the n capacitive elements are electrically connected in series and a parallel state where the n capacitive elements are electrically connected in parallel. In the series state, a given first point out of connection points between the n capacitive elements is connected to the first signal path, and a second point higher than the first point out of the connection points of the n capacitive elements is connected to the second signal path. 
     According to the liquid discharge apparatus as in the above one aspect, charging or discharging of the piezoelectric element is executed by electrically connecting the piezoelectric element to the first signal path or the second signal path; also, this electrical connection is defined taking not only the voltage of the control signal into account but also the holding voltage of the piezoelectric element. Therefore, the piezoelectric element can be finely controlled. Also, the charging and discharging of the piezoelectric element proceeds in a stepwise manner, and therefore the energy efficiency can be increased compared to a conventional configuration where charging and discharging are performed all at once between power source voltages. It is also possible to minimize the power consumed, because the charge that is discharged from the piezoelectric element to the first signal path is recovered, and also reused in generating another voltage, e.g., a second voltage, by switching between the series state and the parallel state in the charge supply source. The occurrence of EMI can also be minimized, because a large current is not switched, as in class D amplification. 
     The liquid discharge apparatus as in the above aspect may also have a configuration in which, in the series state, a predetermined power source voltage is applied to both ends of the n capacitive elements that are connected in series. According to this configuration, multiplication factors that are a factor of one to n of a voltage obtained when the power source voltage is split in n can be used as the first voltage and the second voltage. 
     The liquid discharge apparatus as in the above aspect may have a configuration in which a predetermined power source voltage is applied to both ends of any one capacitive element out of the n capacitive elements in the series state, and may have a configuration in which a predetermined power source voltage is applied to both ends of two or more consecutive capacitive elements out of the n capacitive elements. According to this configuration, the piezoelectric element can be driven with a voltage that exceeds the power source voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Referring now to the attached drawings which form a part of this original disclosure: 
         FIG. 1  is a drawing illustrating a schematic configuration of a print apparatus; 
         FIG. 2  is a drawing illustrating the principal configuration of a discharge section in a print head; 
         FIG. 3  is a waveform diagram illustrating one example of, inter alia, a control signal COM supplied to a print head; 
         FIG. 4  is a block diagram illustrating the principal configuration of a print apparatus; 
         FIG. 5  is a drawing illustrating one example of the configuration of a driver in a print head; 
         FIGS. 6A and 6B  are diagrams for describing the operation of a driver; 
         FIGS. 7A to 7C  are drawings for describing the operation of a level shifter in a driver; 
         FIG. 8  is a drawing for describing the flow of an electrical current (charge) in a driver; 
         FIG. 9  is a drawing for describing the flow of an electrical current (charge) in a driver; 
         FIG. 10  is a drawing for describing the flow of an electrical current (charge) in a driver; 
         FIG. 11  is a drawing for describing the flow of an electrical current (charge) in a driver; 
         FIGS. 12A and 12B  are drawings for describing loss during charging and discharging of a driver; 
         FIG. 13  is a drawing illustrating one example of the configuration of an auxiliary power source circuit; 
         FIGS. 14A and 14B  are drawings for describing the operation of an auxiliary power source circuit; 
         FIGS. 15A and 15B  are drawings illustrating a voltage modification of an auxiliary power source circuit; 
         FIG. 16  is a drawing illustrating the configuration of a (first) other embodiment of an auxiliary power source circuit; 
         FIGS. 17A and 17B  are drawings for describing the operation of the (first) other embodiment of an auxiliary power source circuit; 
         FIG. 18  is a drawing illustrating the configuration of a (second) other embodiment of an auxiliary power source circuit; 
         FIGS. 19A and 19B  are drawings for describing the operation of the (second) other embodiment of an auxiliary power source circuit; and 
         FIG. 20  is a drawing illustrating an exemplary configuration of a print head. 
     
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     Embodiments for carrying out the present invention shall be described below with reference to the accompanying drawings. 
     Overall Configuration of Print Apparatus 
     A print apparatus as in an embodiment of the present invention is an inkjet printer, i.e., a liquid discharge apparatus, which forms groups of ink dots on a recording medium such as paper, by discharging a liquid ink so as to correspond to image data supplied from a host computer, and thereby prints an image (includes text, graphics, and the like) corresponding to the image data. 
       FIG. 1  is a drawing illustrating a schematic configuration of a print apparatus  1 . 
     As is illustrated in  FIG. 1 , the print apparatus  1  has a configuration comprising a control unit  10  for executing a computation process for printing an image on the basis of image data supplied from a host computer, and a print head  20  having a plurality of nozzles. The control unit  10  and the print head  20  are electrically connected together via a flexible cable  190 . The print head  20  is mounted onto a carriage (not shown) that can be moved in a direction (main scanning direction) substantially orthogonal to a direction of feeding (secondary scanning direction) of the recording medium. 
     The control unit  10  comprises a main control section  120 , a digital-to-analog converter (DAC)  160 , and a main power source circuit  180 . 
     The main control section  120  generates a plurality of types of signals for causing ink to be discharged from the nozzles of the print head  20 , by executing computation processes for printing, such as an image development process, color conversion process, ink color separation process, or halftoning process, on the basis of image data acquired from the host computer. Included in the plurality of types of signals are digital control data dCOM supplied from the DAC  160  and a variety of signals supplied to a head control section  220  (described below). 
     The contents of each of the computation processes for printing executed by the main control section  120  are well-known matters in the technical field of print apparatuses, and thus a description is omitted. The print apparatus  1 , in turn, comprises a carriage motor for moving the carriage onto which the print head  20  is mounted in the main scanning direction, a conveyance motor for conveying the recording medium in the secondary scanning direction, and the like, while the control unit  10  comprises a configuration for supplying drive signals to the motors; these configurations are likewise well-known matters, and thus a description is omitted. 
     The DAC  160  converts the control data dCOM to an analog drive signal COM, which is then supplied to the print head  20 . 
     The main power source circuit  180  supplies a power source voltage to each of the parts of the control unit  10  and to the print head  20 . In particular, the main power source circuit  180 , with respect to the print head  20 , supplies a V H  and G as power source voltages to the print head  20 . 
     G (ground) is a ground potential, and serves as a reference of voltage zero in this description, unless otherwise noted. The voltage V H  serves as a high side with respect to the ground G in the embodiment. 
     Though not depicted, one color or a plurality of colors of ink are supplied from an ink container via a flow path to the print head  20 . The print head  20  comprises an auxiliary power source circuit  50 , the head control section  220 , and a selection section  230 , in addition to a plurality of sets of drivers  30  and piezoelectric elements (piezo elements)  40 . 
     The head control section  220  is for controlling the selection of the selection section  230  in conformity with the variety of signals supplied from the main control section  120 . 
     The selection section  230  has switches  232  corresponding to each of the plurality of sets of drivers  30  and piezoelectric elements  40 , each of the switches  232  being connected to one another at one end, with a communally supplied control signal COM, while the other ends are connected to input ends of the respectively corresponding drivers  30 . Each of the switches  232  turns on and off in conformity with the control by the head control section  220 , and supplies the control signals COM to the drivers  30  when turned on but blocks the control signals COM when turned off. For this reason, the selection section  230  selects the control signals COM supplied from the control unit  10  in conformity with the head control section  220 , and supplies same to the drivers  30 . For the sake of convenience of description, the notation Vin is used for those control signals, of the control signals COM, that are selected in conformity with the head control section  220  and supplied to the drivers  30 . 
     The drivers  30  use the plurality of voltages supplied from the auxiliary power source circuit  50 , and the power source voltages V H , G, to drive the piezoelectric elements  40  in conformity with the control signals Vin supplied from the selection section  230 . 
     One end of the piezoelectric elements  40  is connected to an output end of the corresponding driver  30 , while the other ends of the piezoelectric elements  40  are communally connected to the ground G. For this reason, the voltage held in the piezoelectric elements  40  has a double meaning as output voltage of the drivers  30 , and is therefore denoted as a voltage Vout. 
     The auxiliary power source circuit  50 , the specific configuration of which shall be described below, uses a charge pump circuit to divide and reallocate the power source voltages V H , G supplied from the main power source circuit  180 , and thereby generates voltages V H /6, 2V H /6, 3V H /6, 4V H /6, and 5V H /6, which are then communally supplied across the plurality of drivers  30 . 
     As was described above, the piezoelectric elements  40  are provided so as to correspond to each of the plurality of nozzles in the print head  20 , and driving thereof causes the ink to be discharged. Therefore, the configuration for causing the ink to be discharged by driving the piezoelectric elements  40  shall be described next. 
       FIG. 2  is a drawing illustrating the schematic configuration of a discharge section  400  corresponding to one nozzle worth in the print head  20 . 
     As illustrated in  FIG. 2 , the discharge section  400  comprises a piezoelectric element  40 , a diaphragm  421 , a cavity (pressure chamber)  431 , a reservoir  441 , and a nozzle  451 . Of these, the diaphragm  421  is deformed by the piezoelectric element  40 , which is provided to an upper surface in  FIG. 2 , and expands or reduces the internal volume of the cavity  431 , which is filled with ink. The nozzle  451  is an opening that communicates with the cavity  431 . 
     The piezoelectric element  40  illustrated in  FIG. 2  is typically a structure called a unimorph (monomorph) type, in which a piezoelectric body  401  is interposed between a pair of electrodes  411 ,  412 . In the piezoelectric body  401  of this structure, a middle portion in  FIG. 2  is warped in the vertical direction, with respect to both end portions, along with the electrodes  411 ,  412  and the diaphragm  421  in accordance with a voltage applied between the electrodes  411 ,  412 , i.e., the voltage of the control signal Vin. More specifically, the piezoelectric element  40  is warped in the upward direction when the voltage of the control signal Vin rises, but is warped in the downward direction when the voltage of the control signal Vin lowers. According to this configuration, when the piezoelectric element  40  is warped in the upward direction, the volume of the cavity  431  expands and the ink is drawn in from the reservoir  441 , but when the piezoelectric element  40  is warped in the downward direction, the volume of the cavity  431  is reduced and the ink is discharged from the nozzle  451 . 
     The piezoelectric element  40  is not limited to being the unimorph type, however, and need only be a type, such as a bimorph type or laminated type, with which the piezoelectric element can be deformed to discharge a liquid such as ink. 
       FIG. 3  is a drawing illustrating one example of, inter alia, the control signal COM supplied to the print head  20 . 
     As is illustrated in  FIG. 3 , in the control signal COM, drive pulses from PCOM 1  to PCOM 4 , which are the smallest unit of the signal for driving the piezoelectric element  40 , are continuous in time series during a print cycle Ta. The control signal COM is, in fact, a repetitive waveform for which the print cycle Ta represents one cycle. 
     In the print duration Ta, the drive pulse PCOM 1  is positioned at an initial first duration T 1 , the drive pulse PCOM 2  is positioned at a subsequent second duration T 2 , the drive pulse PCOM 3  is positioned at a third duration T 3 , and the drive pulse PCOM 4  is positioned at a fourth duration T 4 . 
     In the present embodiment, the drive pulses PCOM 2  and PCOM 3  are waveforms that are substantially identical to one another and are waveforms that, when provisionally understood to each be supplied to a piezoelectric element  40 , cause a predetermined amount, e.g., a moderate amount of ink to be respectively discharged from the nozzles. The drive pulse PCOM 4  takes a waveform that is different from the drive pulse PCOM 2  (PCOM 3 ), and is a waveform that, when the drive pulse PCOM 4  is provisionally understood to be supplied to a piezoelectric element  40 , causes an amount of ink lesser than the predetermined amount to be discharged from the nozzle. The drive pulse PCOM 1 , however, is a waveform for minutely vibrating the ink near the opening of the nozzle and preventing an increase in the viscosity of the ink. For this reason, even were the drive pulse PCOM 1  to be supplied to the piezoelectric element  40 , ink droplets would not be discharged from the nozzle. 
     In turn, the variety of signals supplied from the main control section  120  supply two-bit print data with which the amount of ink (gradation) to be discharged from the nozzles is defined for every pixel, pulses for defining the start timing of the print cycle Ta, pulses for defining the start time of the durations T 2 , T 3 , T 4 , and the like. 
     The head control section  220  selects the control signals COM in the following manner for every driver  30 , in conformity with the variety of signals supplied from the main control section  120 , and supplies the selected control signals COM as the control signals Vin. 
       FIG. 3  also illustrates how, with respect to the two-bit print data, the control signals COM are selected by the head control section  220  and the selection section  230 , and supplied as the control signals Vin. 
     More specifically, when print data corresponding to a given nozzle is, for example, (11), then the head control section  220  turns the switch  232  corresponding to the relevant nozzle on during the durations T 2 , T 3 . For this reason, out of the control signals COM, the drive pulses PCOM 2 , PCOM 3  are selected and serve as the control signals Vin. As shall be described below, the driver  30  outputs a voltage Vout so as to track the voltages of the control signals Vin, and drive the piezoelectric element  40  corresponding to the relevant nozzle. For this reason, moderate amounts of ink corresponding respectively thereto are discharged in two rounds from the relevant nozzle. As such, the ink lands and merges together on the recording medium, as a result of which a large-sized dot is formed. 
     When the print data corresponding to a given nozzle is (01), then the head control section  220  turns the switch  232  corresponding to the relevant nozzle on during the durations T 3 , T 4 . For this reason, out of the control signals COM, the drive pulses PCOM 3 , PCOM 4  are selected and serve as the control signals Vin. Because the piezoelectric element  40  is driven by the voltage Vout tracking the control signals Vin, a moderate and small amount of ink are discharged in two rounds in respective correspondence thereto from the relevant nozzle. As such, the ink lands and merges together on the recording medium, as a result of which a medium-sized dot is formed. 
     In turn, when the print data corresponding to a given nozzle is (10), then the head control section  220  turns the switch  232  corresponding to the relevant nozzle on only during the duration T 4 . For this reason, out of the control signals COM, the drive pulse PCOM 4  is selected and serves as the control signals Vin. Because the piezoelectric element  40  is driven by the voltage Vout tracking the control signals Vin, a small amount of ink is discharged in one round from the relevant nozzle. As such, a small-sized dot is formed on the recording medium. 
     When the print data corresponding to a given nozzle is (00), then the head control section  220  turns the switch  232  corresponding to the relevant nozzle on during only the duration T 1 . For this reason, out of the control signals COM, the drive pulse PCOM 1  is selected and serves as the control signals Vin. The piezoelectric element  40  is driven by the voltage Vout tracking the control signals Vin, but it is only that the ink near the opening of the nozzle is minutely vibrated during the duration T 1 . As such, no ink is discharged, and therefore no dot is formed on the recording medium, i.e., the state is one of non-recording. 
     Selecting the control signals COM and supplying same as the control signals Vin in accordance with such print data causes four gradations—large-sized dots, medium-sized dots, small-sized dots, and non-recording—to be represented. The selection operation of such description is executed simultaneously and in parallel for every nozzle. The waveforms and the like illustrated in  FIG. 3  are merely provided by way of example. 
       FIG. 4  is a block diagram illustrating the principal configuration of when the focus is on one set of a driver  30  and piezoelectric element  40  in the print apparatus  1 . 
     The control signals Vin supplied to the driver  30  are signals obtained when the drive signals COM, having been converted by the DAC  160 , are extracted out by turning on the switch  232  that corresponds to the relevant driver  30 , as described above. For this reason, the control signals Vin could be said to be supplied to the relevant driver  30  from a control signal generation section  15 , one block of which would be the main control section  120 , the DAC  160 , and the selection section  230  (switch  232 ), which are a previous stage of the driver  30 . 
     In turn, the auxiliary power source circuit  50  generates the voltages V H /6, 2V H /6, 3V H /6, 4V H /6, and 5V H /6 from the power source voltages V H , G and supplies same to the driver  30 , and the driver  30  uses the power source voltages V H , G and the voltages V H /6, 2V H /6, 3V H /6, 4V H /6, 5V H /6 to supply the voltages Vout tracking the voltages of the control signals Vin to the piezoelectric element  40 , as has been described above. The voltage V H /6 is supplied to the driver  30  from the auxiliary power source circuit  50  via a power source wiring  511  and, similarly, the voltages 2V H /6, 3V H /6, 4V H /6, 5V H /6 are supplied via power source wirings  512 ,  513 ,  514 ,  515 . 
     As is noted by the parentheses in  FIG. 4 , the auxiliary power source circuit  50  is equivalent to a charge supply source, and the driver  30  is equivalent to a connection path selection section. The power source wirings  511 ,  512 , and so forth are then equivalent to a first signal path, second signal path, and so forth, where the voltages V H /6, 2V H /6, and so forth are a first voltage, a second voltage, and so forth. 
     Driver 
     The piezoelectric elements  40  are provided so as to correspond to each of the plurality of nozzles in the print head  20 , and are driven by the drivers  30  with which each is respectively paired. 
       FIG. 5  is a drawing illustrating one example of the configuration of a driver  30  for driving one piezoelectric element  40 . 
     As is illustrated in  FIG. 5 , the driver  30  comprises an operational amplifier  32 , unit circuits  34   a  to  34   f , and comparators  38   a  to  38   e , and has a configuration for driving the piezoelectric element  40  in conformity with the control signals Vin. 
     When voltage zero is included, the driver  30  uses seven types of voltages, which, when stated in ascending order, namely are voltage zero (ground G) and V H /6, 2V H /6, 3V H /6, 4V H /6, 5V H /6, and V H . 
     Of these, five types of voltages, excluding voltage zero and the voltage V H , are supplied from the auxiliary power source circuit  50  via the power source wirings  511 ,  512 ,  513 ,  514 ,  515 , respectively. 
     The control signals Vin, which are outputted from the selection section  230 , are supplied to an input end (+) of the operational amplifier  32 , which is an input end of the driver  30 . Output signals of the operational amplifier  32  are supplied to the unit circuits  34   a  to  34   f , negatively fed back to an input end (−) of the operational amplifier  32  via a resistor Rf, and also grounded to the ground G via a resistor Rin. For this reason, the operational amplifier  32  non-invertingly amplifies the control signals Vin by a factor of (1+Rf/Rin). 
     The voltage amplification factor of the operational amplifier  32  can be set by the resistors Rf, Rin, but for the sake of convenience, Rf is understood to be zero and Rin is understood to be infinite below. That is to say, the following description understands the voltage amplification factor of the operational amplifier  32  to have been set to “1” and understands the control signals Vin to be supplied to the unit circuits  34   a  to  34   f  without alteration. The voltage amplification factor may be a number other than “1”. 
     The unit circuits  34   a  to  34   f  are provided in ascending order of voltage so as to correspond to two mutually adjacent voltages out of the aforementioned types of voltages. More specifically, the unit circuit  34   a  is provided so as to correspond to voltage zero and the voltage V H /6, the unit circuit  34   b  is provided so as to correspond to the voltage V H /6 and the voltage 2V H  6, the unit circuit  34   c  is provided so as to correspond to the voltage 2V H /6 and the voltage 3V H /6, the unit circuit  34   d  is provided so as to correspond to the voltage 3V H /6 and the voltage 4V H /6, the unit circuit  34   e  is provided so as to correspond to the voltage 4V H /6 and the voltage 5V H /6, and the unit circuit  34   f  is provided so as to correspond to the voltage 5V H /6 and the voltage V H . 
     The circuitry configurations of the unit circuit  34   a  to  34   f  are mutually identical, and comprise whichever one respectively corresponds out of level shifters  36   a  to  36   f , a bipolar NPN transistor  341 , and a PNP transistor  342 . 
     Where the unit circuits  34   a  to  34   f  are described in general rather than specific terms, then the description shall simply relate to a reference numeral “ 34 ”; likewise, where the level shifters  36   a  to  36   f  are described in general rather than specific terms, then the description shall simply relate to a reference numeral “ 36 ”. 
     The level shifters  36  take either an enable state or a disable state. More specifically, the level shifters  36  are in the enable state when the signal supplied to a negative control end, marked with a circle, is an L level and the signal supplied to a positive control end, not marked with a circle, is an H level; at all other times, the level shifters  36  are in the disable state. 
     As will be described below, out of the aforementioned seven types of voltages, each of the comparators  38   a  to  38   e  is associated by pairs with five types of voltages, excluding voltage zero and the voltage V H . Focusing herein on a given unit circuit  34 , the output signal of the comparator associated with a high-side voltage out of the two voltages associated with the relevant unit circuit  34  is supplied to the negative control end of the level shifter  36  in the relevant unit circuit  34 , and the output signal of the comparator associated with a low-side voltage out of the two voltages associated with the relevant unit circuit is supplied to the positive control end of the level shifter  36 . The negative control end of the level shifter  36   f  in the unit circuit  34   f  is grounded to the ground G of voltage zero, equivalent to the L level, and the positive control end of the level shifter  36   a  in the unit circuit  34   a  is connected to the power source wiring  516 , which supplies the voltage V H , equivalent to the H level. 
     The level shifters  36 , when in the enable state, shift the voltage of the inputted control signals Vin by a predetermined value in a minus direction and supply the shifted voltage to a base terminal of the transistors  341 , and in turn shift the voltage of the control signals Vin by a predetermined value in a plus direction and supply the shifted voltage to a base terminal of the transistor  342 . Irrespective of the control signals Vin, the level shifters  36  when in the disable state supply a voltage for turning the transistors  341  off, e.g., the voltage V 11  to the base terminals of the relevant transistors  341 , and supply a voltage for turning the transistors  342  off, e.g., voltage zero to the base terminals of the relevant transistors  342 . 
     The predetermined value is understood to be a voltage (bias voltage, about 0.6 V) between a base and emitter, at which a current begins to flow to an emitter terminal. For this reason, the predetermined value is a quality determined in accordance with the properties of the transistors  341 ,  342 , and is zero provided that the transistors  341 ,  342  are ideal. 
     A collector terminal of the transistor  341  is connected to the power source wiring that supplies the high-side voltage out of the two corresponding voltages, and a collector terminal of the transistor  342  is connected to the power source wiring that supplies the low-side voltage. In, for example, the unit circuit  34   a , which corresponds to voltage zero and the voltage V H /6, the collector terminal of the transistor  341  is connected to the power source wiring  511 , which supplies the voltage V H /6, and the collector terminal of the transistor  342  is grounded to the ground G of voltage zero. In another example, in the unit circuit  34   b , which corresponds to the voltage V H /6 and the voltage 2V H /6, the collector terminal of the transistor  341  is connected to the power source wiring  512 , which supplies the voltage 2V H /6, and the collector terminal of the transistor  342  is connected to the power source wiring  511 , which supplies the voltage V H /6. In the unit circuit  34   f , which corresponds to the voltage 5V H /6 and the voltage V H , the collector terminal of the transistor  341  is connected to the power source wiring  516 , which supplies the voltage V H , and the collector terminal of the transistor  342  is connected to the power source wiring  515 , which supplies the voltage 5V H /6. 
     In turn, in the unit circuits  34   a  to  34   f , emitter terminals of the transistors  341 ,  342  share a connection to one end of the piezoelectric element  40 . For this reason, the common connection point of the emitter terminals of the transistors  341 ,  342  is connected to the one end of the piezoelectric element  40  as an output end of the driver  30 . 
     Out of the aforementioned seven types of voltages, the comparators  38   a  to  38   e  correspond to five types of voltages V H /6, 2V H /6, 3V H /6, 4V H /6, 5V H /6, V H , excluding voltage zero and the voltage V H , and compare the relative levels of voltages supplied to the two input ends and output a signal indicative of the comparison result. Herein, out of the two input ends in the comparators  38   a  to  38   e , one end is connected to the power source wiring that supplies the voltage that corresponds thereto, and the other end shares a connection to the one end of the piezoelectric element  40 , along with each of the emitter terminals of the transistors  341 ,  342 . For example, in the comparator  38   a , which corresponds to the voltage V H /6, one end out of the two input ends is connected to the power source wiring  511 , which supplies the voltage V H /6 corresponding thereto; in another example, in the comparator  38   b , which corresponds to the voltage 2V H /6, one end of the two input ends is connected to the power source wiring  512 , which supplies the voltage 2V H /6 corresponding thereto. 
     Each of the comparators  38   a  to  38   e  outputs a signal which takes the H level when the voltage Vout of the other end at the input end is not less than the voltage of the one end, and takes the L level when the voltage Vout is less than the voltage of the one end. 
     More specifically, for example, the comparator  38   a  outputs a signal which takes the H level when the voltage Vout is not less than the voltage V H /6, and takes the L level when the voltage Vout is less than the voltage V H /6. As another example, the comparator  38   b  outputs a signal which takes the H level when the voltage Vout is not less than the voltage 2V H /6, and takes the L level when the voltage Vout is less than the voltage 2V H /6. 
     To focus now on one out of the five types of voltages, the output signal of the comparator corresponding to the relevant voltage of interest is supplied to both the negative input end of the level shifter  36  of the unit circuit for which the relevant voltage is the high-side voltage, and the positive input end of the level shifter  36  of the unit circuit for which the relevant voltage is the low-side voltage. 
     For example, the output signal of the comparator  38   a , which corresponds to the voltage V H /6, is supplied to the negative input end of the level shifter  36   a  of the unit circuit  34   a , for which the relevant voltage V H /6 is associated as the high-sigh voltage, and to the positive input end of the level shifter  36   b  of the unit circuit  34   b , for which the relevant voltage V H /6 is associated as the low-side voltage. As another example, the output signal of the comparator  38   b , which corresponds to the voltage 2V H /6, is supplied to the negative input end of the level shifter  36   b  of the unit circuit  34   b , for which the relevant voltage 2V H /6 is associated as the high-sigh voltage, and to the positive input end of the level shifter  36   c  of the unit circuit  34   c , for which the relevant voltage 2V H /6 is associated as the low-side voltage. 
     Next, the operation of the driver  30  shall now be described. 
     First, the states reached by the comparators  38   a  to  38   e  and the level shifters  36  with respect to the voltage Vout, held by the piezoelectric element  40 , shall be described. 
     In a state (first state) where the voltage Vout is between voltage zero and less than the voltage V H /6, then the output signals of the comparators  38   a  to  38   e  are all at the L level. For this reason, in the first state, only the level shifter  36   a  is in the enable state, and the other level shifters  36   b  to  36   f  are in the disable state 
     In a state (second state) where the voltage Vout is not less than the voltage V H /6 but is less than the voltage 2V H /6, then the output signal of the comparator  38   a  is at the H level, and the output signals of the other comparators  38   b  to  38   e  are at the L level. For this reason, in the second state, only the level shifter  36   b  is in the enable state, and the other level shifters  36   a ,  36   c  to  36   f  are in the disable state. 
     In a state (third state) where the voltage Vout is not less than the voltage 2V H /6 but is less than the voltage 3V H /6, then the output signals of the comparators  38   a ,  38   b  are at the H level, and the output signals of the other comparators  38   c  to  38   e  are at the L level. For this reason, in the third state, only the level shifter  36   c  is in the enable state, and the other level shifters  36   a ,  36   b ,  36   d  to  36   f  are in the disable state. 
     In a state (fourth state) where the voltage Vout is not less than the voltage 3V H /6 but is less than the voltage 4V H /6, then the output signals of the comparators  38   a ,  38   b ,  38   c  are at the H level, and the output signals of the other comparators  38   d  to  38   e  are at the L level. For this reason, in the fourth state, only the level shifter  36   d  is in the enable state, and the other level shifters  36   a  to  36   c ,  36   e ,  36   f  are in the disable state. 
     In a state (fifth state) where the voltage Vout is not less than the voltage 4V H /6 but is less than the voltage 5V H /6, then the output signals of the comparators  38   a  to  38   d  are at the H level, and the output signal of the other comparator  38   e  is at the L level. For this reason, in the fifth state, only the level shifter  36   e  is in the enable state, and the other level shifters  36   a  to  36   d ,  36   f  are in the disable state. 
     In a state (sixth state) where the voltage Vout is not less than the voltage 5V H /6 but is less than the voltage V H , then the output signals of the comparators  38   a  to  38   e  are all at the H level. For this reason, in the sixth state, only the level shifter  36   f  is in the enable state, and the other level shifters  36   a  to  36   d  are in the disable state. 
     Thus, in the first state, only the level shifter  36   a  is in the enable state. This continues in a similar manner, where only the level shifter  36   b  is in the enable state in the second state, only the level shifter  36   c  is in the enable state in the third state, only the level shifter  36   d  is in the enable state in the fourth state, only the level shifter  36   e  is in the enable state in the fifth state, and only the level shifter  36   f  is in the enable state in the sixth state. 
     The first state through sixth state have been defined with the voltage Vout, but this could also be stated in terms of the state of charge held (stored) in the piezoelectric element  40 . 
     When the level shifter  36   a  is in the enable state in the first state, then the relevant level shifter  36   a  supplies a voltage signal obtained when the control signal Vin has been level-shifted by a predetermined value in the minus direction to the base terminal of the transistor  341  in the unit circuit  34   a , and supplies a voltage signal obtained when the control signal Vin has been level-shifted by a predetermined value in the plus direction to the base terminal of the transistor  342  in the relevant unit circuit  34   a.    
     Herein, when the voltage of the control signal Vin is higher than the voltage Vout (connection point voltage between the emitter terminals), then a current corresponding to the difference thereof (the voltage between base and emitter; in a stricter sense, a voltage reduced by a predetermined value from the voltage between base and emitter) flows to the emitter terminal from the collector terminal of the transistor  341 . For this reason, the voltage Vout gradually rises and approaches the voltage of the control signal Vin, and when the voltage Vout eventually matches the voltage of the control signal Vin, then the current flowing to the transistor  341  at this point in time is zero. 
     In turn, when the voltage of the control signal Vin is less than the voltage Vout, then a current corresponding to the difference flows to the collector terminal from the emitter terminal of the transistor  342 . For this reason, the voltage Vout gradually lowers and approaches the voltage of the control signal Vin, and when the voltage Vout eventually matches the voltage of the control signal Vin, then the current flowing to the transistor  342  at this point in time is zero. 
     As such, in the first state, the transistors  341 ,  342  of the unit circuit  34   a  will execute such a control as to match the voltage Vout to the control signal Vin. 
     In the first state, because the level shifters  36  are in the disable state in the unit circuits  34   b  to  34   f  other than the unit circuit  34   a , the voltage V H  is supplied to the base terminals of the transistors  341 , and voltage zero is supplied to the base terminals of the transistors  342 . For this reason, in the first state, the transistors  341 ,  341  are off in the unit circuits  34   b  to  34   f , and therefore are not involved in the control of the voltage Vout. 
     The description herein is of when the first state is in effect, but the operation will be similar in the second state through sixth state, as well. More specifically, one of the unit circuits  34   a  to  34   f  is enabled, depending on the voltage Vout held by the piezoelectric element  40 , and the transistors  341 ,  342  of the enabled unit circuit implement a control so as to match the voltage Vout to the control signal Vin. For this reason, when the driver  30  is viewed as a whole, the operation is one where the voltage Vout tracks the voltage of the control signal Vin. 
     As such, as illustrated in  FIG. 6A , when the control signal Vin rises, for example, from voltage zero to the voltage V H , then the voltage Vout also tracks the control signal Vin and changes from voltage zero to the voltage V H . As illustrated in  FIG. 6B , when the control signal Vin lowers from the voltage V H  to voltage zero, then the voltage Vout also tracks the control signal Vin and changes from the voltage V H  to voltage zero. 
       FIGS. 7A to 7C  are drawings for describing the operation of the level shifters. 
     When the voltage of the control signal Vin changes, rising from voltage zero to the voltage V H , the voltage Vout also tracks the control signal Vin and rises. In the course of this rise, the level shifter  36   a  is in the enable state when the first state, where the voltage Vout is between voltage zero and less than the voltage V H /6, is in effect. For this reason, as illustrated in  FIG. 7A , the voltage (denoted by “P-type”) that is supplied to the base terminal of the transistor  341  by the level shifter  36   a  is a voltage obtained when the control signal Vin has been shifted by a predetermined value in the minus direction, and the voltage (denoted by “N-type”) that is supplied to the base terminal of the transistor  342  is a voltage obtained when the control signal Vin has been shifted by a predetermined value in the plus direction. When a state other than the first state is in effect, however, then the level shifter  36   a  is in the disable state, and therefore the voltage that is supplied to the base terminal of the transistor  341  is V H , and the voltage that is supplied to the base terminal of the transistor  342  is zero. 
       FIG. 7B  illustrates a voltage waveform outputted by the level shifter  36   b , and  FIG. 7C  illustrates a voltage waveform outputted by the level shifter  36   f . No special description shall be needed provided that one remembers that the level shifter  36   b  is in the enable state when the second state, where the voltage Vout is between the voltage 2V H /6 and less than the voltage 2V H /6, is in effect, and that the level shifter  36   f  is in the enable state when the sixth state, where the voltage Vout is between the voltage 5V H /6 and less than the voltage V H , is in effect. 
     The description shall also forgo describing the operation of the level shifters  36   c  to  36   e  in the course of rising of the voltage of the control signal Vin (or the voltage Vout), and describing the operation of the level shifters  36   a  to  36   f  in the course of lowering of the voltage of the control signal Vin (or the voltage Vout). 
     Next, the flow of current (charge) in the unit circuits  34   a  to  34   f  shall be described, taking the unit circuits  34   a ,  34   b  by way of example, and divided between during charging and during discharging. 
       FIG. 8  is a drawing illustrating the operation of when the piezoelectric element  40  is charged when the first state (a state where the voltage Vout is between voltage zero and less than the voltage V H /6) is in effect. 
     In the first state, the level shifter  36   a  is in the enable state and the other level shifters  36   b  to  36   f  are in the disable state, and therefore it suffices to focus only on the unit circuit  34   a.    
     When the voltage of the control signal Vin is higher than the voltage Vout in the first state, then a current corresponding to the voltage between base and emitter flows through the transistor  341  of the unit circuit  34   a . As such, the transistor  341  of the unit circuit  34   a  will function as a first transistor. At this time, the transistor  342  of the unit circuit  34   a  is off. 
     At this time, the electrical current flows in a path that goes from the power source wiring  511 →the transistor  341  (of the unit circuit  34   a )→the piezoelectric element  40 , as illustrated by the arrow in  FIG. 8 , thus charging the piezoelectric element  40  with a charge. This charging causes the voltage Vout to rise. 
     When the voltage Vout matches the voltage of the control signal Vin, the transistor  341  of the unit circuit  34   a  is off, and therefore the charging of the piezoelectric element  40  is stopped. 
     However, in a case where the control signal Vin rises to the voltage V H /6 or higher, then the voltage Vout also tracks the control signal Vin and therefore reaches the voltage V H /6 or higher as well, and a transition is made from the first state to the second state (a state where the voltage Vout is between the voltage V H /6 and less than the voltage 2V H /6). 
       FIG. 9  is a drawing illustrating the operation of when the piezoelectric element  40  is charged in the second state. 
     In the second state, the level shifter  36   b  is in the enable state and the other level shifters  36   a ,  36   c  to  36   f  are in the disable state, and therefore it suffices to focus only on the unit circuit  34   b.    
     When the voltage of the control signal Vin is higher than the voltage Vout in the second state, then a current corresponding to the voltage between base and emitter flows through the transistor  341  of the unit circuit  34   b . As such, the transistor  341  of the unit circuit  34   b  will function as a third transistor. At this time, the transistor  342  of the unit circuit  34   b  is off. 
     At this time, the electrical current flows in a path that goes from the power source wiring  512 →the transistor  341  (of the unit circuit  34   b )→the piezoelectric element  40 , as illustrated by the arrow in  FIG. 9 , thus charging the piezoelectric element  40  with a charge. That is to say, in a case where the piezoelectric element  40  is charged in the second state, one end of the piezoelectric element  40  is electrically connected to the auxiliary power source circuit  50  via the power source wiring  512 . 
     Thus, when a transition is made from the first state to the second state during rising of the voltage Vout, then the source of supply of the electric current is switched from the power source wiring  511  to the power source wiring  512 . 
     When the voltage Vout matches the voltage of the control signal Vin, the transistor  341  of the unit circuit  34   b  is off, and therefore the charging of the piezoelectric element  40  is stopped. 
     However, in a case where the control signal Vin rises to the voltage 2V H /6 or higher, then the voltage Vout also tracks the control signal Vin and therefore reaches the voltage 2V H /6 or higher as well, as a result of which a transition is made from the second state to the third state (a state where the voltage Vout is between the voltage 2V H /6 and less than the voltage 3V H /6). 
     In the charging operation from the third state to the sixth state, though not shown, the source of supply of the electrical current is switched in a stepwise manner to the power source wirings  513 ,  514 ,  515 ,  516 . 
       FIG. 10  is a drawing illustrating the operation of when the piezoelectric element  40  is discharged when the second state is in effect. 
     In the second state, the level shifter  36   b  is in the enable state. When the voltage of the control signal Vin is lower than the voltage Vout in this state, then a current corresponding to the voltage between base and emitter flows through the transistor  342  of the unit circuit  34   b . As such, the transistor  341  of the unit circuit  34   b  will function as a second transistor. At this time, the transistor  341  of the unit circuit  34   b  is off. 
     At this time, the electrical current flows in a path that goes from the piezoelectric element  40 →the transistor  342  (of the unit circuit  34   b )→the power source wiring  511 , as illustrated by the arrow in  FIG. 10 , thus discharging the charge from the piezoelectric element  40 . That is to say, in a case where the piezoelectric element  40  is charged with a charge in the first state, and in a case where a charge is discharged from the piezoelectric element  40  in the second state, then one end of the piezoelectric element  40  is electrically connected to the auxiliary power source circuit  50  via the power source wiring  511 . Further, the power source wiring  511  supplies a current (charge) during charging in the first state, and recovers a current (charge) during discharging of the second state. 
     The recovered charge is redistributed for reuse by the auxiliary power source circuit  50  (described below). 
     When the voltage Vout matches the control signal Vin, the transistor  342  of the unit circuit  34   b  is off and therefore discharging of the piezoelectric element  40  is stopped. 
     However, in a case where the control signal Vin falls to less than the voltage V H /6, then the voltage Vout also tracks the control signal Vin and therefore reaches less than the voltage V H /6 as well, and a transition is made from the second state to the first state. 
       FIG. 11  is a drawing illustrating the operation of when the piezoelectric element  40  is discharged when the first state is in effect. 
     In the first state, the level shifter  36   a  is in the enable state. When the voltage of the control signal Vin is lower than the voltage Vout in this state, then a current corresponding to the voltage between base and emitter flows through the transistor  342  of the unit circuit  34   a.    
     At this time, the transistor  341  of the unit circuit  34   a  is off. 
     At this time, the electrical current flows in a path that goes from the piezoelectric element  40 →the transistor  342  (of the unit circuit  34   a )→the ground G, as illustrated by the arrow in  FIG. 11 , thus discharging the charge from the piezoelectric element  40 . 
     The description herein is of the unit circuits  34   a ,  34   b  by way of example, divided between during charging and during discharging, but the operation is substantially similar for the unit circuits  34   c  to  34   f  as well, except for the fact that the transistors  341 ,  342  controlling the current are different. 
     That is to say, 
     the power source wiring  512  supplies the current (charge) during charging in the second state, and recovers the current (charge) during discharging in the third state, 
     the power source wiring  513  supplies the current (charge) during charging in the third state, and recovers the current (charge) during discharging in the fourth state, 
     the power source wiring  514  supplies the current (charge) during charging in the fourth state, and recovers the current (charge) during discharging in the fifth state, 
     the power source wiring  515  supplies the current (charge) during charging in the fifth state, and recovers the current (charge) during discharging in the sixth state, and 
     the power source wiring  516  supplies the current (charge) during charging in the sixth state. 
     The recovered charge is redistributed for reuse by the auxiliary power source circuit  50 . 
     In the charge path and discharge path in each of the state, there is a common path from the one end of the piezoelectric element  40  to the connection points between emitter terminals in the transistors  341 ,  342 . 
     Typically, the energy P that is stored in a capacitive load is represented by
 
 P =( C·E   2 )/2
 
     where C is the capacitance of a capacitive load such as the piezoelectric element  40 , and E is the voltage amplitude. 
     The piezoelectric element  40  works by being deformed by the energy P, but the amount of working for discharging the ink is 1% or less in relation to the energy P. As such, the piezoelectric element  40  can be regarded as a simple capacitance. When a capacitance C is charged at a constant power supply, energy equivalent to (C·E 2 )/2 is consumed by the charge circuit. During discharging, too, an equivalent energy is consumed by the discharge circuit. 
     Advantage of Driver 
     In the present embodiment, when the piezoelectric element  40  is charged from voltage zero to the voltage V H , then charging takes place through six stages of: 
     from voltage zero to the voltage V H /6, 
     from the voltage V H /6 to the voltage 2V H /6, 
     from the voltage 2V H /6 to the voltage 3V H /6, 
     from the voltage 3V H /6 to the voltage 4V H /6, 
     from the voltage 4V H /6 to the voltage 5V H /6, and from the voltage 5V H /6 to the voltage V H . 
     For this reason, in the present embodiment, the loss during charging is merely an amount corresponding to the surface area of the region that has hatching in  FIG. 12A . More specifically, in the present embodiment, the loss during charging in the piezoelectric element  40  is merely 6/36=(16.7%), compared to the linear amplification for charging from voltage zero to the voltage V H  in a single burst. 
     In turn, because discharging is also stepwise in the present embodiment, the loss during discharging is likewise merely 6/36 (=16.7%), compared to the linear format for discharging from the voltage V H  to voltage zero in one burst, as illustrated with the amount equivalent to the surface area of the region that has hatching in  FIG. 12B . 
     The present embodiment also enables a further reduction of power consumption because of the redistribution and reuse of charge recovered by the auxiliary power source circuit  50  (described below), excluding cases of discharging from the voltage V H /6 to voltage zero, out of the charge recorded as a loss during discharging. 
       FIGS. 12A and 12B  are merely conceptual diagrams for describing the operation of driving of the piezoelectric element  40  by the driver  30 . The piezoelectric element  40  is, in fact, driven by whichever control signal COM is selected out of the drive pulses PCOM 1  to PCOM 4 , and thus driving is not necessarily always performed at an amplitude from voltage zero to the voltage V H . 
     Class D amplification has a higher energy efficiency compared to linear amplification. This is due in part to the fact that that an active element of an output stage operates at a saturated state and consumes substantially no power, the fact that the exchange of magnetic energy created by an inductor L constituting a low-pass filter and energy created by a capacitance C prevent, during charging, the occurrence of such loss as with linear amplification, and the fact that the electrical current is regenerated to the power source with current switching during discharging. 
     However, actual class D amplification does have problems, among which the fact that the resistance of the active element of the output stage is not zero, even in the saturated state, the fact that there is leakage of the magnetic field, the fact that the resistance component of the inductor L causes loss to occur, and the fact that in some instances the inductor L is saturated during modulation. In particular in a configuration where, in the print head  20 , a selection is made at the selection section  230  from shared control signals COM for supply to a plurality of piezoelectric elements  40 , the unsaturated inductors L are increased because there is not a constant total amount of negative charge as seen from the control signals COM. 
     Class D amplification also has problems in that the waveform quality is poor and EMI countermeasures are necessary. Though waveform quality can be improved by adding a dummy capacitance or filter, the increase entails a commensurate increase in power consumption and rise in costs. EMI derives from the fundamental problem of switching in class D amplification. That is to say, when a switch is made, not only does the current that flows during an on-time reach up to about a factor of several times or several tens of times that of linear amplification, but also the amount of magnetic field emitted in association therewith increases as well. Counteracting EMI requires adding a filter and the like, and entails higher costs. 
     The drivers  30  of the print apparatus as in the present embodiment do not suffer the problems of poor waveform quality and the need to counteract EMI, because the transistors  341 ,  342 , which are equivalent to an output stage, do not engage in such switching as in class D amplification, and also because inductors L are not used. 
     Also, the present embodiment involves an operation where the voltage Vout tracks the voltage of the control signals Vin, and therefore the piezoelectric elements  40  can be finely controlled. That is to say, the start voltage and end voltage of the voltage Vout applied to the piezoelectric elements  40  are unrelated to the voltages V H /6, 2V H /6, 3V H /6, 4V H /6, and 5V H /6 used for driving. 
     Auxiliary Power Source Circuit 
     Next, an auxiliary power source circuit  50  that is preferred for the print apparatus  1  as in the present embodiment shall be described. 
       FIG. 13  is a drawing illustrating one example of the configuration of the auxiliary power source circuit  50 . 
     As illustrated in  FIG. 13 , the auxiliary power source circuit  50  has a configuration comprising: switches Sw 1   d , Sw 1   u , Sw 2   d , Sw 2   u , Sw 3   d , Sw 3   u , Sw 4   d , Sw 4   u , Sw 5   d , and Sw 5   u ; and capacitive elements C 12 , C 23 , C 34 , C 45 , C 56 , C 1 , C 2 , C 3 , C 4 , C 5 , and C 6 . 
     Of these, the switches are all single-pole double-throw, and a shared terminal is connected to a terminal a or b in conformity with control signals A/B. When described in a simplified manner, the control signals A/B are pulse signals for which, for example, the duty ratio is about 50%, and the frequency thereof is set to, for example, a factor of about 20 in relation to the frequency of the control signals COM. The control signals A/B of such description may be generated by an internal oscillator (not shown) in the auxiliary power source circuit  50 , and may be supplied to the control unit  10  via the flexible cable  190 . 
     The capacitive elements C 12 , C 23 , C 34 , C 45 , C 56  are for charge transfer. The capacitive elements C 1 , C 2 , C 3 , C 4 , C 5  are for backup. The capacitive element C 6  is for supplying the power source voltage V H . 
     The switches are in fact configured by combining transistors in a semiconductor integrated circuit, and the capacitive elements are mounted externally with respect to this semiconductor integrated circuit. Preferably, the semiconductor integrated circuit also has the configuration formed with respect to the plurality of drivers  30  described above. 
     Next, the power source wiring  516  that supplies the voltage V H  in the auxiliary power source circuit  50  is connected to one end of the capacitive element C 6  and to a terminal a of the switch Sw 5   u . A shared terminal of the switch Sw 5   u  is connected to one end of the capacitive element C 56 , and the other end of the capacitive element C 56  is connected to a shared terminal of the switch Sw 5   d . The terminal a of the switch Sw 5   d  is connected to one end of the capacitive element C 5  and to the terminal a of the switch Sw 4   u . The shared terminal of the switch Sw 4   u  is connected to one end of the capacitive element C 45 , and the other end of the capacitive element C 45  is connected to the shared terminal of the switch Sw 4   d . The terminal a of the switch Sw 4   d  is connected to one end of the capacitive element C 4  and to the terminal a of the switch Sw 3   u . The shared terminal of the switch Sw 3   u  is connected to one end of the capacitive element C 34 , and the other end of the capacitive element C 34  is connected to the shared terminal of the switch Sw 3   d . The terminal a of the switch Sw 3   d  is connected to one end of the capacitive element C 3  and to the terminal a of the switch Sw 2   u . The shared terminal of the switch Sw 2   u  is connected to one end of the capacitive element C 23 , and the other end of the capacitive element C 23  is connected to the shared terminal of the switch Sw 2   d . The terminal a of the switch Sw 2   d  is connected to one end of the capacitive element C 2  and to the terminal a of the switch Sw 1   u . The shared terminal of the switch Sw 1   u  is connected to one end of the capacitive element C 12 , and the other end of the capacitive element C 12  is connected to the shared terminal of the switch Sw 1   d . The terminal a of the switch Sw 1   d  is connected to one end of the capacitive element C 1 . 
     One end of the capacitive element C 5  is connected to the power source wiring  515 . Similarly, one end of the capacitive elements C 4 , C 3 , C 2 , C 1  is connected to the power source wirings  514 ,  513 ,  512 ,  511 , respectively. 
     Each of the terminals b of the switches Sw 5   u , Sw 4   u , Sw 3   u , Sw 2   u , Sw 1   u  is connected to one end of the capacitive element C 1  along with the terminal a of the switch Sw 1   d . Each of the other ends of the capacitive elements C 6 , C 5 , C 4 , C 3 , C 2 , C 1  and each of the terminals b of the switches Sw 5   d , Sw 4   d , Sw 3   d , Sw 2   d , Sw 1   d  are grounded alike to the ground G. 
       FIGS. 14A and 14B  are drawings illustrating a state of connection of the switches in the auxiliary power source circuit  50 . 
     Each of the switches takes one of two states, a state (state A) where the shared terminal is connected to the terminal a or a state (state B) where the shared terminal is connected to the terminal b, depending on the control signals A/B.  FIGS. 14A and 14B  provide a simplified illustration, with equivalent circuitry, of the connections in the state A and the connections in the state B, respectively, in the auxiliary power source circuit  50 . 
     In the state A, the capacitive elements C 56 , C 45 , C 34 , C 23 , C 12 , C 1  are connected in series, between the voltage V H  and the ground G. For this reason, the state A may also be termed a series state. In the state B, the one ends of the capacitive elements C 56 , C 45 , C 34 , C 23 , C 12 , C 1  are connected to one another. For this reason, the state B may also be termed a parallel state. In the state B, the holding voltage is equalized because the one ends of the capacitive elements C 56 , C 45 , C 34 , C 23 , C 12 , C 1  are connected to one another in parallel, 
     The switches Sw 1   d , Sw 1   u , Sw 2   d , Sw 2   u , Sw 3   d , Sw 3   u , Sw 4   d , Sw 4   u , Sw 5   d , Sw 5   u  will function as a switching section for switching between the state A (series state) and the state B (parallel state). 
     As such, when the states A, B are alternately repeated, then the voltage V H /6, which was equalized during the state B, is increased by a factor of one to five by the series connection of the state A and respectively held in the capacitive elements C 1  to C 5 ; the holding voltage of this time is supplied to the drivers  30  via the power source wirings  511  to  515 . 
     Herein, when the piezoelectric elements  40  are charged by the drivers  30 , a decrease in the holding voltages does appear among the capacitive elements C 1  to C 5 . The capacitive elements for which the holding voltage has dropped are resupplied with charge from the power source by the series connection of the state A, along with equalization with redistribution by the parallel connection of the state B, and therefore a balance is struck so as to stay at the voltages V H /6, 2V H /6, 3V H /6, 4V H /6, 5V H /6 when viewed in terms of the auxiliary power source circuit  50  overall. 
     In turn, when the piezoelectric elements  40  are discharged by the drivers  30 , a rise in the holding voltage does appear among the capacitive elements C 1  to C 5 , but the charge is sent out by the series connection of the state A, along with equalization with redistribution by the parallel connection of the state B, and therefore a balance is struck so as to stay at the voltages V H /6, 2V H /6, 3V H /6, 4V H /6, 5V H /6 when viewed in terms of the auxiliary power source circuit  50  overall. When the charge that is sent out cannot be absorbed by the capacitive elements C 56 , C 45 , C 34 , C 23 , C 12 , C 1  and remains in excess, the excess charge is absorbed by the capacitive element C 6 , i.e., is regenerated to the power supply system. For this reason, when there is any other load beyond the piezoelectric elements  40 , the charge is used to drive this load. When there is no other load, the charge is absorbed by the other capacitive elements, including the capacitive element C 6 , and therefore the power source voltage V H  rises, i.e., rippling occurs, but increasing the capacitance of the coupling capacitors, including the capacitive element C 6 , makes it possible to avoid this in practical usage. 
     When the voltages V H /6, 2V H /6, 3V H /6, 4V H /6, 5V H /6 generated by the auxiliary power source circuit  50  of such description are supplied to the drivers  30 , power consumption can be reduced, in addition to the following advantages as well. Namely, even when the voltage V H  supplied from the main power source circuit  180  is modified, the voltages V H /6, 2V H /6, 3V H /6, 4V H /6, 5V H /6 are modified in accordance with the modified voltage V H . 
     The amplitude of the power source voltage V H  has the quality of needing to be set according to the individual performance of the piezoelectric elements  40 . For this reason, with high-performing (high-efficiency) piezoelectric elements  40 , it suffices to drive at a relatively low amplitude, as illustrated by the rank A in  FIG. 15A . By contrast, with low-performing (low-efficiency) piezoelectric elements  40 , it is necessary to drive at a relatively large amplitude, as illustrated by the rank B. 
     In order to drive piezoelectric elements  40  of both ranks A and B, the loss is increased when the voltage V H  is fixed to a higher state in accordance with the rank B. It is particularly wasteful when the rank A, which is adequate at a low amplitude, is being driven. 
     Accordingly, when the voltage V H  is properly set according to the performance (efficiency) of the piezoelectric elements  40 , as illustrated in  FIG. 15B , wasteful loss can be minimized, in particular even when the rank A is being driven. 
     With the auxiliary power source circuit  50 , when the piezoelectric elements  40  are being discharged by the drivers  30 , the holding voltage of any of the capacitive elements C 1  to C 6  corresponding to the power source wiring being used for this discharging may temporarily rise, but repeating between the states A and B strikes a balance so as to hold a multiplication voltage of a factor of one to six of the voltage V H /6. Similarly, when the piezoelectric elements  40  are being charged by the drivers  30 , the holding voltage of any of the capacitive elements C 1  to C 6  corresponding to the power source wiring being used for this charging may temporarily lower, but repeating between the states A and B strikes a balance so as to hold a multiplication voltage of a factor of one to six of the voltage V H /6. 
     As will be understood by viewing the voltage waveform of the control signals COM (Vin) in  FIG. 3 , the voltage rise for drawing in the ink and the voltage drop for discharging the ink are a set, and this set is repeated in the print operation. For this reason, with the auxiliary power source circuit  50 , the charge that is recovered by the discharging of the piezoelectric element  40  is used in charging in the next and subsequent rounds. 
     As such, in the present embodiment, when the print apparatus  1  is viewed as a whole, the recovery, redistribution, and reuse of the charge discharged from the piezoelectric elements  40  and the stepwise charging and discharging in the drivers  30  (see  FIGS. 15A and 15B ) making it possible to keep power consumption low. 
     In the state A (series state), as illustrated in  FIG. 14 , the power source voltages (V H , G) are applied to one end of the capacitive element C 56  and the other end of the capacitive element C 1 , i.e., to both ends of the six capacitive elements C 56 , C 45 , C 34 , C 23 , C 12 , C 1  that are connected in series; the connection point (*1) between the one end of the capacitive element  1  and the other end of the capacitive element C 12  is connected to the power source wiring  511 , which is the first signal path; and the connection point (*2) between the one end of the capacitive element C 12  and the other end of the capacitive element C 23  is connected to the power source wiring  512 , which is the second signal path. 
     In the auxiliary power source circuit  50 , when the shared terminals of each of the switches are switched from connection to one of the terminals a, b to the other, should there be a property variance in a plurality of (in  FIG. 13 , ten) switches, then in some instances there could be a state where the switching is not done in unison, resulting in a short-circuiting of both ends of the capacitive elements. For example, when the terminals a are connected to the shared terminal at the switches Sw 1   u , Sw 1   d , Sw 2   d  during switching, should there occur a state where the terminal b is connected to the shared terminal at the switch Sw 2   u , then both ends of the series connection between the capacitive elements C 12 , C 23  would end up short-circuiting. 
     For this reason, the configuration is preferably such that during switching of the switches, the occurrence of such short-circuiting is minimized through a neutral state in which there is temporarily no connection to the terminals a, b. 
     The auxiliary power source circuit  50  illustrated in  FIG. 13  ( FIG. 14 ) has a configuration in which the capacitive elements C 12 , C 23 , C 34 , C 45 , C 56  for charge transfer and the capacitive element C 1  for backing up the voltage V H /6 are electrically connected in series between the voltages (V H , G) in the state A, and the power source voltages (V H , G) are split into six. 
     With this configuration, however, it would not be possible to drive the capacitive elements  40  at a high voltage amplitude not less than the power source voltages (V H , G). For example, when the power source V H  is 42 V (volts), the voltages V H /6, 2V H /6, 3V H /6, 4V H /6, 5V H /6 that are generated in the auxiliary power source circuit  50  will be 7 V, 14 V, 21 V, 28 V, and 35 V, respectively, and therefore the piezoelectric elements  40  cannot be driven beyond 42 V. In other words, driving the piezoelectric elements  40  at maximum at 42 V necessitates 42 V as the power source voltage V H . 
     Therefore, the description shall now relate to several embodiments of the auxiliary power source circuit  50  with which the power source voltages (V H , G) and higher voltages can be generated. Hereinbelow, the power source voltage V H  supplied from the main power source circuit  180  shall be denoted by VA, for the purpose of differentiation from the voltages V H /6, 2V H /6, 3V H /6, 4V H /6, 5V H /6 generated in the auxiliary power source circuit  50 . 
       FIG. 16  is a drawing illustrating one example of a (first) other embodiment of the auxiliary power source circuit  50 .  FIG. 16  differs from  FIG. 13  firstly in that the voltage V H  is supplied to the driver  30  via the power source wiring  516  not by the main power source circuit  180  but rather by the auxiliary power source circuit  50 , and secondly in that in the auxiliary power source circuit  50 , the power source voltage VA coming from the main power source circuit  180  is supplied to one end of the capacitive element C 1 , i.e., to the power source wiring  511 . 
     A capacitive element C 0  is connected between the power source voltage VA and the ground G in parallel with the capacitive element C 1 , and is for playing the roles of a coupling capacitor of the power source coming from the main power source circuit  180  and a charge-regenerating capacitor to which the piezoelectric element  40  is discharged via the power source wiring  511 . 
       FIGS. 17A and 17B  are drawings illustrating a state of connection of the switches in the auxiliary power source circuit  50  illustrated in  FIG. 16 . In this (first) other embodiment, as well, similarly with respect to the configuration illustrated in  FIG. 13 , each of the switches adopts the two states, namely, the state A and the state B, depending on the control signals A/B. More specifically, as illustrated in  FIG. 17A , the capacitive elements C 56 , C 45 , C 34 , C 23 , C 12 , C 1  are connected in series in the state A, and the capacitive elements C 56 , C 45 , C 34 , C 23 , C 12 , C 1  are connected in parallel in the state B. When the states A, B are alternately repeated, then the voltage VA, which was equalized during the state B in each of the capacitive elements, is increased by a factor of 1, 2, 3, 4, 5, 6 by the series connection of the state A and respectively held in the capacitive elements C 1  to C 6 ; the holding voltage of this time is supplied to the drivers  30  via the power source wirings  511  to  516 . 
     For this reason, even when, for example, the voltage VA is 7 V, one-sixth compared to the configuration illustrated in  FIG. 13 , then 7 V, 14 V, 21 V, 28 V, 35 V, 42 V can be supplied to the drivers  30  as the voltages V H /6, 2V H /6, 3V H /6, 4V H /6, 5V H /6, V H , respectively. In other words, the power source voltage VA supplied by the main power source circuit  180  is merely 7 V, even in a case where the piezoelectric elements  40  are being driven at a maximum at 42 V. 
     In the auxiliary power source circuit  50  illustrated in  FIGS. 16 and 17 , in the state A (series state), the power source voltages (VA, G) will be applied to both ends of the capacitive element C 1  out of the six capacitive elements that are connected in series. 
       FIG. 18  is a drawing illustrating one example of a (second) other embodiment of the auxiliary power source circuit  50 .  FIG. 18  differs from  FIG. 16  in that the power source voltage VA coming from the main power source circuit  180  is supplied not to one end of the capacitive element C 1  but rather to one end of the capacitive element C 3 , i.e., to the power source wiring  513 . 
       FIGS. 19A and 19B  are drawings illustrating the state of connection of the switches in the auxiliary power source circuit  50  illustrated in  FIG. 18 . This (second) other embodiment, too, similarly with respect to the configuration illustrated in  FIG. 16 , repeats alternately between the state A where the capacitive elements C 56 , C 45 , C 34 , C 23 , C 12 , C 1  are connected in series, and the state B where the capacitive elements C 56 , C 45 , C 34 , C 23 , C 12 , C 1  are connected in parallel. The voltage VA, which was equalized during the state B in each of the capacitive elements, is increased by a factor of 1/3, 2/3, 3/3 (=1), 4/3, 5/3, 2 by the series connection of the state A and respectively held in the capacitive elements C 1  to C 6 ; the holding voltage of this time is supplied to the drivers  30  via the power source wirings  511  to  516 . 
     For this reason, even when, for example, the voltage VA is 21 V, one-half compared to the configuration illustrated in  FIG. 13 , then 7 V, 14 V, 21 V, 28 V, 35 V, 42 V can be supplied to the drivers  30  as the voltages V H /6, 2V H /6, 3V H /6, 4V H /6, 5V H /6, V H , respectively. 
     In the auxiliary power source circuit  50  illustrated in  FIGS. 18 and 19 , in the state A (series state) the power source voltages (VA, G) will be applied to both ends of when the three capacitive elements C 23 , C 12 , C 1  that are coupled to one another, out of the six capacitive elements that are connected in series, are viewed as a single combined capacitor. 
     The destination of supply of the power source voltage VA may be one end of the capacitor elements C 1 , C 3 , or otherwise may be one end of the capacitor elements C 2 , C 4 , C 5 . For example, as illustrated by the dashed line in  FIG. 18 , the destination of supply of the voltage VA may be one end of the capacitive element C 4 , i.e., the power supply wiring  514 . When the destination of supply of the power source voltage V H  is the power source wiring  514 , then voltages that are a factor of 1/4, 2/4, 3/4, 4/4 (=1), 5/4, 6/4 of the voltage VA are outputted as the voltages V H /6, 2V H /6, 3V H /6, 4V H /6, 5V H /6, V H , respectively. For this reason, even when, for example, the voltage VA is 42 V, the same as the configuration illustrated in  FIG. 13 , then 10.5 V, 21 V, 31.5 V, 42 V, 52.5 V, 63 V can be supplied to the drivers  3  as the voltages V H /6, 2V H /6, 3V H /6, 4V H /6, 5V H /6, V H , respectively. As such, the piezoelectric elements  40  can be driven at voltages exceeding the 42 V of the power source voltage VA. 
     When the destination of supply of the power source voltage VA is the power source wiring  514 , then in the state A (series state) the power source voltages (VA, G) will be applied to both ends of when the four capacitive elements C 34 , C 23 , C 12 , C 1  that are coupled to one another, out of the six capacitive elements that are connected in series, are viewed as a single combined capacitor. 
     As described with the (first, second) other embodiments of the auxiliary power source circuit  50 , when the destination of supply of the power source voltage VA is any of the power source wirings  511  to  515 , then the piezoelectric elements  40  can be driven at voltages exceeding the power source voltage VA coming from the main power source circuit  180 . The auxiliary power source circuit  50  illustrated in  FIGS. 13 and 14  is no other than a configuration in which the destination of supply of the power source voltage VA is the power source wiring  516 . 
       FIG. 20  is a drawing illustrating the principal configuration in the print head  20  as in an example of application; more specifically, one example of a configuration in which the driver  30  and the auxiliary power source circuit  50  are integrated into a semiconductor circuit. As described in  FIGS. 16 and 18 , the power source voltage VA coming from the main power source circuit  180  can be supplied to any of the power source wirings  511  to  516  (one end of the capacitive elements C 1  to C 6 ). 
     The configuration may therefore be one where externally connecting terminals V 1  to V 6  that are connected to the power source wirings  511  to  516 , respectively, are provided as illustrated in  FIG. 20 , and for any of the terminals V 1  to V 6 , a selection can be made to supply the power source voltage coming from an external power source circuit  52  or to supply the power source voltage VA coming from the main power source circuit  180 , as illustrated by the dashed lines in  FIG. 20 . 
     Herein, regarding the external power source circuit  52 , an arbitrary direct current voltage may be generated from a direct current power source by the DC-DC converter, or, for example, as per an auxiliary power source circuit  50  such as was described in  FIG. 16 , the configuration may be one where the power source voltage is supplied to one end of the capacitive element C 1  to thereby generate multiplication voltages (1×V H  to 6×VX) of a factor of one to six of the power source voltage, and any of the voltages is connected and supplied to any of the terminals V 1  to V 6 . 
     When the external power source circuit  52  is provided in this manner separately from the auxiliary power source circuit  50 , then the voltages V H /6, 2V H /6, 3V H /6, 4V H /6, 5V H /6, V H , which are unstable directly after start-up in the auxiliary power source circuit  50 , can be rapidly stabilized. Also, the external power source circuit  52  of such description has a smaller power source capacity, and therefore a single external power source circuit  52  can be shared among a plurality of drivers  30 . 
     Application/Modification Examples 
     The present invention is not limited by the embodiment described above, but rather, a variety of applications and modifications, such as shall be described below by way of example, are possible. One or a plurality of arbitrarily selected embodiments of application or modification described below can also be combined as appropriate. 
     Driven Objects 
     The embodiment described the example of piezoelectric elements  40  for discharging ink as the driven objects of the drivers  30 . The present invention is not limited to the piezoelectric elements  40  as the driven objects, and may be applied to any and all loads that have a capacitive component, such as, for example, an ultrasonic motor, a touch panel, a flat speaker, or a liquid crystal or other kind of display. 
     Number of Stages of Unit Circuits 
     The embodiment had a configuration in which six stages of unit circuits  34   a  to  34   f  are provided in ascending order of voltage, so as to correspond to two mutually adjacent voltages out of the seven types of voltages, but in the present invention, the number of stages of unit circuits  34  is not limited thereto, and need only be two stages or more. Typically, where the number of stages of unit circuits  34  is n, the configuration in terms of  FIG. 13  for the auxiliary power source circuit  50  need only be one where (n−1) intermediate voltages, excluding the power source voltage coming from the main power source circuit  180 , are supplied. More specifically, the configuration need only be one where switching is alternately done between the series connection of the n capacitive elements in the state A and the parallel connection of the n capacitive elements in the state B, and each of the connection points of the capacitive elements in the state A is supplied as (n−1) intermediate voltages. 
     The configuration may also be one where the number of stages of unit circuits  34  in the drivers  30  is reduced to lower than the number of capacitive elements that are connected in series in the state A in the auxiliary power source circuit  50 , and several out of the connection points of the capacitive elements are selected and then supplied as intermediate voltages. With this configuration, however, the voltages would be at irregular intervals. 
     General Interpretation of Terms 
     In understanding the scope of the present invention, the term “comprising” and its derivatives, as used herein, are intended to be open ended terms that specify the presence of the stated features, elements, components, groups, integers, and/or steps, but do not exclude the presence of other unstated features, elements, components, groups, integers and/or steps. The foregoing also applies to words having similar meanings such as the terms, “including”, “having” and their derivatives. Also, the terms “part,” “section,” “portion,” “member” or “element” when used in the singular can have the dual meaning of a single part or a plurality of parts. Finally, terms of degree such as “substantially”, “about” and “approximately” as used herein mean a reasonable amount of deviation of the modified term such that the end result is not significantly changed. For example, these terms can be construed as including a deviation of at least ±5% of the modified term if this deviation would not negate the meaning of the word it modifies. 
     While only selected embodiments have been chosen to illustrate the present invention, it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made herein without departing from the scope of the invention as defined in the appended claims. Furthermore, the foregoing descriptions of the embodiments according to the present invention are provided for illustration only, and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.