Patent Publication Number: US-2017365489-A1

Title: System and method for manufacturing a cavity down fabricated carrier

Description:
RELATED APPLICATIONS 
     This application claims priority from U.S. patent application 61/912,745, filed Dec. 6, 2013. Priority is claimed to this earlier filed application and the contents of this earlier filed application are incorporated herein, in its entirety, by reference. 
    
    
     FIELD OF INVENTION 
     The present invention relates generally to integrated circuit packaging and more particularly to a system and method for fabricating a ball grid array carrier. 
     BACKGROUND 
     Various processes exist for forming a fabricated carrier. For example, fabrication can be done by means of fabricating a polyimide carrier laminated with metal foil with the aid of an adhesive layer, followed by patterning the metal and selectively plating the metal portion followed by laminating the polyimide carrier onto a thick metal piece where there is a partially etched cavity aligning with the opening of the polyimide carrier to form the die receptacle. This is not a cost effective way to make such a carrier since the polyimide is relatively expensive. Moreover, polyimide is relatively thin, and in order to create a deep enough receptacle to receive a semiconductor device, a relatively thick metal piece with partially etched cavity is needed and therefore an additional etching step is needed. 
     SUMMARY 
     It is an object of an aspect of the invention to provide a novel system and method for fabricating a ball grid array carrier that obviates and mitigates at least one of the above-identified disadvantages of the prior art. 
     These, together with other aspects and advantages which will be subsequently apparent, reside in the details of construction and operation as more fully hereinafter described and claimed, reference being had to the accompanying drawings forming a part hereof, wherein like numerals refer to like parts throughout. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIGS. 1( a )-( c )  show diagrams of a ball grid array carrier in accordance with an embodiment; 
         FIG. 2  is a flow chart showing a method of ball grid carrier fabrication in accordance with an embodiment; 
         FIGS. 3( a )-( d )  show cross-sectional views of a ball grid carrier being fabricated, in accordance with an embodiment; 
         FIGS. 4( a )-( c )  show cross-sectional views of a ball grid carrier being fabricated, in accordance with an embodiment; 
         FIGS. 5( a )-( d )  show cross-sectional views of a ball grid carrier being assembled with a semiconductor die, in accordance with an embodiment; 
         FIGS. 6( a )-( g )  show cross-sectional views of a ball grid carrier being fabricated and assembled with a semiconductor die, in accordance with another embodiment; and 
         FIGS. 7( a ) and ( b )  show cross-sectional views of and assembled ball grid array carrier in accordance with alternative embodiments. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1( a )  shows a perspective top view of a ball grid array (BGA) carrier  125  in accordance with one implementation.  FIG. 1( b )  shows a top view and  FIG. 1 ( c )  is a cross-sectional view of carrier  125  across lines A-A in  FIG. 1( b ) . 
     Referring now to  FIG. 2 , a method of fabricating a cavity down BGA carrier is indicated generally at  200 . It is to be understood that method  200  can be varied, and need not be performed exactly as discussed herein, and that such variations are within the scope of the invention. 
     At  210 , a dielectric portion is combined with a conductive portion, as illustrated in  FIG. 3( a ) , where a conductive portion  105 , which can be made of metals such as copper, is combined directly with a dielectric portion  120 . The dielectric portion  120  may be molded from a polymerized molding compound based, for example, on a binding material such as an epoxy and filled with inorganic fillers such as silicon dioxide or silicon carbide, or it may be any suitable plastic compound molded into a predetermined shape suitable to fabricate BGA carriers. The dielectric portion  120  can be formed into any predetermined thickness. An example thickness for dielectric portion  120  is approximately 0.1 mm. As shown in  FIG. 3( a ) , the dielectric portion can be shaped so as to form a cavity or receptacle  110  in the middle such that the conductive portion  105  is exposed from both the top surface  135  and the bottom surface  140  of carrier  125  at the cavity  110 . 
     Cavity  110  for receiving a die can be formed by an inner surface  111  of dielectric portion  120  which intersects the bottom surface  140  and the top surface  135  forming a top portal  112  and a bottom portal  113 . In some implementations, such as the one shown in  FIG. 3 , inner surface  111  can be substantially orthogonal to the top and bottom surfaces. In other implementations, inner surface  111  can be angled in a manner that differs from orthogonal, namely non-orthogonally, such that the top portal  112  and the bottom portal  113  can have different circumferential dimensions. For example, inner surface  111  may be at an angle greater than 90 with respect to the bottom surface  135  allowing the bottom portal  113  to have a smaller circumference size with respect to the top portal  112 . In this example, the inner surface  111  would intersect the top surface  135  at an angle less than 90 degrees. The inner surface  111  can be arranged in any predetermined manner to allow forming portals of any predetermined circumferential shape as defined by inner surface  111 &#39;s intersection with a top and/or a bottom surface. Examples of circumferential shapes include a square, a rectangle, a triangle, a circle or an irregular shape. Moreover, top portal  112  can be of a different circumferential shape from the bottom portal  113  by forming the inner surface  111  in a manner to allow the shape difference. In some implementations, cavity  110  can have only one portal where the inner surface intersects one of the top surface  135  or the bottom surface  140 , but not both. 
     In some implementations, as shown in  FIG. 3( a )  conductive portion  105  can be a metal foil such as a copper foil. The thickness of the foil can vary, for example, to be 18 um, 10 um or thinner. In further implementations, dielectric portion  120  is composed of a molding compound that can be molded by being exposed to high temperatures to reduce viscosity, for allowing the molding compound to be molded by a molding tool. In further implementations, dielectric portion  120  can be combined directly with the foil as the molding portion  120  can bind directly to the foil without the aid of an additional adhesive layer between the dielectric portion  120  and the foil. For example, in some variations, a binding material included in the molding material can facilitate the direct binding of dielectric portion  120  and the foil. In other implementations, as shown in  FIG. 3( b ) , the conductive portion can be formed by metalizing the top surface of the dielectric portion  120 . The metallization can be achieved by either sputtering on the dielectric portion  120  a metal seed layer  115  (such as copper or chromium or titanium) or by immersion metal plating using metals such as copper. The seed layer  115  or the immersion plating can be followed by further electrolytic plating with copper or similar metals to achieve the required thickness. 
     At  220 , the exposed the top surface of conductive portion  105 , namely the top surface  135  of carrier  125 , can be selectively plated as illustrated  FIG. 3( c ) , where the selective plating is indicated at  155 . Metal plating  155  can be selectively deposited on at least portions of conductive portion  105 , which in the illustrated embodiment is a metal foil. In some implementations, the plating  155  can be shaped to form bonding fingers and BGA pads. In some variations, to carry out selective plating, a photo-imageable plating resist is applied to the top surface of the carrier  125 . The top surface  135  is then exposed to a predetermined or selected image pattern. Next, the plating resist is developed and the specified metal pattern is plated as indicated at  155 . The metal used can be Ag, Ni/Au, Pd or others that will be known to a person of skill in the art. Finally, the plating resist is stripped away. 
     At  230 , at least some of conductive portion  105  is selectively etched away as indicated at  145  in  FIG. 3( d ) . In some implementations, in order to carry out selectively etching of the conductive portion  105  in accordance with a predetermined pattern, photo imageable etching resist is applied to the top surface  135  and a selected image pattern is exposed. Then, the etching resist is developed and the metal pattern defined by the etching resist is exposed. Finally, the etching resist on the top surface  135  is stripped away. 
     At  240 , solder resist can be applied selectively in accordance with a predetermined shape or pattern to the top surface  135  using traditional methods.  FIG. 4( a )  shows solder resist as applied to the top surface  135  of carrier portion  125 , indicated at  160 . In some implementations, the solder resist application is shaped such that areas of the conductive portion forming BGA pads  163  and bonding fingers  166  are left exposed at the top surface  135  of carrier  125 . 
     At  250  of method  200 , and as indicated at  170  in  FIG. 4( b ) , an adhesive layer such as thermoset epoxy or film is applied to the exposed bottom surface  140  of the dielectric portion  120 . At  260 , a heat spreader  175  such as copper, Kovar® or material with high thermal conductivity and low CTE mismatch with the semiconductor device to be attached, is subsequently applied to the bottom surface  140  of the adhesive layer as shown in  FIG. 4( c )  completing the formation of a carrier  125  as shown in  FIG. 1 . 
     The carrier  125 , as shown in  FIG. 1  can be assembled as shown in  FIG. 5 . First, a die attach adhesive or epoxy  180  can be placed on the top surface  135  of the cavity, to which a die  185  can be attached, as shown in  FIG. 5( a ) . Next, bonded wires  190  can be applied to the die and to the bonding fingers  166  to connect the pad bond pads on the die to the bonding traces on the carrier  125 , as shown in  FIG. 5( b ) . Bonded wires can be composed of Au, Cu or Ag, for example. An encapsulant  195  can then encapsulate or passivate the die  185 , the bonded wires  190  and at least a portion of bonding fingers  166  as shown in  FIG. 5( c ) , using for example, over molding or dispensing liquid type encapsulant followed by temperature curing. Solder balls  197  can also be attached to the BGA pads  163  using flux followed by reflow, for example, as shown in  FIG. 5( d ) . Solder metal used can include SnAg, Cu, SnCu and others that will be known to a person of skill in the art. 
     In variations, following the application of solder resist as illustrated in  FIG. 4( a )  and repeated in  FIG. 6( a ) , a temporary tape  198  having adhesive on one side, for example, can be laminated onto the bottom surface  140  of carrier portion  125 , as indicated at  FIG. 6( b ) . A die  185  can be attached to the top surface of the temporary tape  198  with adhesive or epoxy, as shown in  FIG. 6( c ) . Next, bonded wires  190  can be applied to the die and the bonding fingers  166  to connect the pad bond pads on the die to the bonding traces on the carrier portion  125 , as shown in  FIG. 6( d ) . 
     An encapsulant  195  can then encapsulate or passivate the die  185 , the bonded wires  190  and at least a portion of bonding fingers  166  as shown in  FIG. 6( e ) , using for example, over molding or dispensing liquid type encapsulant followed by temperature curing. Solder balls  197  can also be attached to the BGA pads  163  using flux followed by reflow, for example as shown in  FIG. 6( f ) . At this point, the temporary tape  198  can be removed using known methods as indicated in  FIG. 6( g ) . 
     Finally, referring to  FIG. 7 , a heat sink  199  can be attached. The heat sink  199  can be attached with or without a heat spreader  175  as indicated in  FIGS. 7( a ) and 7( b ) , respectively. In some implementations, the heat sink  199  can be applied using a thermal interface material  191  such as thermal compound. 
     The above-described embodiments are intended to be examples and alterations and modifications may be effected thereto, by those of skill in the art, without departing from the scope which is defined solely by the claims appended hereto. For example, methods, systems and embodiments discussed can be varied and combined, in full or in part.