Patent Publication Number: US-7587697-B1

Title: System and method of mapping memory blocks in a configurable integrated circuit

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
   This Application is related to the following applications: U.S. patent application Ser. No. 11/371,214, filed Mar. 8, 2006; U.S. patent application Ser. No. 11/609,875, filed Dec. 12, 2006; U.S. patent application Ser. No. 11/371,191, filed Mar. 8, 2006; U.S. patent application Ser. No. 11/371,194, filed Mar. 8, 2006; U.S. patent application Ser. No. 11/371,352, filed Mar. 8, 2006; and U.S. patent application Ser. No. 11/371,198, filed Mar. 8, 2006. 
   FIELD OF THE INVENTION 
   The present invention is directed towards configurable integrated circuits with memory ports and offset connections. 
   BACKGROUND OF THE INVENTION 
   Integrated circuits (“ICs”, often called “chips”) are typically grown on and etched into semiconductor substrates. The transistors that make up the majority of their circuitry are generally confined to a two dimensional plane on the surface of the substrate. Almost any integrated circuit design requires connections from transistors on one part of the substrate to transistors on other parts of the substrate. These transistors are connected by tiny metal wires. The wires are not free wires, but are rather laid down in rigid layers (wiring planes) over the transistors. Unlike the transistors, the wired connections can use three dimensions, moving among different wiring planes by use of “vias”. Vias are implements at which connections can pass from one layer to another. 
   The confinement of transistors to a single, two-dimensional plane means that connections through transistors alone cannot go over each other, but must instead go around. The freedom of wired connectors to change layers means that one wire can go over another wire, rather than going around it. 
   Configurable ICs are ICs that can be “programmed” to provide different integrated circuit configurations. Configurable ICs can be thought of as general purpose chips. The logical blocks within them can be re-assigned to different tasks as needed. For instance, acting as a logical “AND” gate in one set up and as a logical “OR” gate in another setup. The importance of the difference between transistor connections and wire connections to configurable ICs will be explained below. 
   The use of configurable ICs (e.g. field programmable gate arrays, “FPGAs”) has dramatically increased in recent years. Configurable ICs usually have logic circuits, interconnect circuits, and input/output (I/O) circuits. The logic circuits (also called logic blocks) are typically arranged as an internal array of circuits. These logic circuits are connected together through numerous interconnect circuits (also called interconnects). The logic and interconnect circuits are typically surrounded by the I/O circuits. 
     FIG. 1  illustrates an example of a configurable logic circuit  100 . This logic circuit can be configured to perform a number of different functions. As shown in  FIG. 1 , the logic circuit  100  receives a set of input data  105  and a set of configuration data  110 . The configuration data set can be stored in a set of SRAM cells  115 . From the set of functions that the logic circuit  100  can perform, the configuration data set specifies a particular function that this circuit is to perform on the input data set. Once the logic circuit performs its function on the input data set, it provides the output of this function on a set of output lines  120 . The logic circuit  100  is said to be configurable, as the configuration data set “configures” the logic circuit to perform a particular function, and this configuration data set can be modified by writing new data in the SRAM cells. Multiplexers and look-up tables are two examples of configurable logic circuits. 
     FIG. 2  illustrates an example of a configurable interconnect circuit  200 . This interconnect circuit  200  connects a set of input data  205  to a set of output data  210 . This circuit receives configuration data bits  215  that are stored in a set of SRAM cells  220 . The configuration bits specify how the interconnect circuit should connect the input data set to the output data set. The interconnect circuit  200  is said to be configurable, as the configuration data set “configures” the interconnect circuit to use a particular connection scheme that connects the input data set to the output data set in a desired manner. Moreover, this configuration data set can be modified by writing new data in the SRAM cells. Multiplexers are one example of interconnect circuits. 
     FIG. 3  illustrates a portion of a prior art configurable IC  300 . As shown in this figure, the IC  300  includes an array of configurable logic circuits  305  and configurable interconnect circuits  310 . The IC  300  has two types of interconnect circuits  310   a  and  310   b . Interconnect circuits  310   a  connect interconnect circuits  310   b  and logic circuits  305 , while interconnect circuits  310   b  connect interconnect circuits  310   a  to other interconnect circuits  310   a . In some cases, the IC  300  has hundreds or thousands of logic circuits  305  and interconnect circuits  310 . 
   The arrangement of interconnect circuits illustrated in  FIG. 3  allows configurations in which the output of one chosen logic circuit can be sent through a series of interconnect circuits to an input of any other single chosen logic circuit. The connection would be made though a succession of interconnect circuits. However, it is usually the case that multiple logic circuits must be made to connect to each other. 
   One reason that multiple logic circuits must be connected is that ICs commonly need to deal with multiple bit “words”, not just single bits. For example, a user might want to invert a 4-bit number, and then perform another operation on the resulting 4-bit number. Each logic circuit in the configurable IC can perform an operation on one bit, and then pass the result on to another logic circuit to perform the next operation. 
   Such a set of operations results in a “data path” that, in this example, is 4 bits wide. Each logic circuit does an operation on one data bit, so a 4-bit set of operations requires 4 logic circuits in a row. In order to perform a series of operations on a particular 4-bit set of data, all 4 bits must be sent to another row of 4 logic circuits. The simplest way of doing this is to send all 4 bits to the next row down. 
   Another way of doing this is shown in  FIG. 4 . In  FIG. 4 , the output from logic circuits  405   a , goes through the interconnect circuits  410   a  and  410   b  to the inputs of logic circuits  405   b.    
     FIG. 4  demonstrates that in the prior art multiple logic circuits could be connected in parallel to multiple other logic circuits. However, this set of connections came at a price; because each interconnect circuit can only be used to make one connection at a time. Thus, the figure also shows that logic circuits  405   c  and interconnect circuits  410   c  are completely isolated from other circuits. The figure also shows that any circuits on opposite sides of the connected circuits can only connect to each other if they go around the connected block. 
   The problem of blocked circuits gets worse if a user wants to shift a data path over, as shown in  FIG. 5 . This figure shows an attempt to shift a 3-bit data path from the logic circuits shown in tile set  520   a  over to the logic circuits in tile set  520   b . Unless otherwise noted a “tile set” in this specification defines a group of tiles in the diagram, and is not itself an actual physical object. Circuit  505   a  connects to circuit  505   d , and circuit  505   b  connects to circuit  505   e , but each interconnect circuit can only be used once. Each interconnect circuit used in those two connections is unavailable for making a connection between circuit  505   c  and circuit  505   f . Once the path between those circuits reaches dead end  530 , it has no available interconnect circuit to go to. In some cases, long routes could connect circuits  505   c  and  505   f , rather than the path simply being blocked outright. The long route would use interconnect circuits that are outside the illustrated area (below those shown in  FIG. 5 ). However, data following such a route would pass through a greater number of interconnect circuits than data following the routes shown in  FIG. 5  and would thus take longer to reach the destination circuit than data following the illustrated routes. In addition to creating timing problems, such long routes also become more and more complicated the greater the number of tiles in the tile sets. 
   Other configurable ICs of the prior art attempted to solve this problem by making direct connections between interconnect circuits in distant rows or columns. Here, a direct connection is one which does not pass through any routing circuitry other than that associated with the individual logic circuits it connects.  FIG. 6  shows available direct connections  610  between a group of circuits  620   a  and several groups of circuits  620   b - 620   e  below. 
   Having distant interconnects in the same row or column is only a partial solution. Often a user may want a long sequence of operations performed on a multi-bit set, each operation taking one logic circuit per bit. Vertical and horizontal direct connections still confine wide data paths to stay within one set of columns or rows, and if a large number of operations needs to be performed, there may not be enough available space in a set of columns to allow for individual rows to be skipped by long direct connections. 
   As  FIG. 7  shows, because of the blocking effects of a row of occupied circuits, such a sequence of operations may result in a large section of the chip being occupied by a wall  730  of in-use circuits. With such a wall in place, circuit  705   a  has no path to reach circuit  705   b.    
   One type of circuitry found on some configurable ICs is memory circuitry, sometimes called “digital memory” or just “memory”. Digital memory is accessed according to a system of addresses and words. Memory typically has a set of n addresses which specify the location of memory words that are m-bits long (where m and n are integers). The total number of bits stored in such a memory is the product of the number of addresses (sometimes called the depth of the memory) and the length of the words (sometimes called the width of the memory. A memory with n addresses that is m-bits wide contains n times m bits of information. 
   Memory is typically accessed through memory “ports” that specify the address of the memory word to be read or written over. Such ports have pre-configured word widths. Digital circuits typically operate on some time scale, each operation of such circuits takes place in one time period, or “clock cycle”. A memory port can perform one access to a memory per clock cycle of the memory. One access means reading or writing one word to the memory. 
   Some memories have multiple ports. These ports enable the memory to be accessed multiple times per clock cycle. This allows data to be written to and read from the memory about twice as fast. However, multiple ports accessing the memory at the same time creates the possibility that two or more ports may try to read from or write to the same address at the same time. Attempts to write to the same address at the same time with multiple memory ports at best result in an ambiguous result about which port “wins” and has its word written to that address. Attempts to read the memory through one port and write to the memory from another port create an ambiguity about whether the word previously written in that address or the word currently being written to that address will be read from the memory. 
   Therefore, there is a need in the art for a configurable IC with behavioral descriptions for dealing with the issues raised by multiple ports accessing the same memory. 
   SUMMARY OF THE INVENTION 
   Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user. 
   Some embodiments provide a method of configuring a configurable IC with a set of memory ports. The method receives a user design. The user design includes a multi-port memory and specifies multiple accesses to a particular location in the memory in one user cycle through at least two ports. The multiple accesses are specified based on a particular port priority hierarchy. The method maps the multi-port memory to a physical memory in the configurable IC using the port priority hierarchy to specify access priority to the physical memory based on the access port priority hierarchy. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates an example of a prior art configurable logic circuit. 
       FIG. 2  illustrates an example of a prior art configurable interconnect circuit. 
       FIG. 3  illustrates a portion of a prior art configurable IC. 
       FIG. 4  illustrates connections of a data path in a prior art configurable IC. 
       FIG. 5  illustrates connections of another data path in a prior art configurable IC. 
       FIG. 6  illustrates long connections within a column of tiles in a prior art configurable IC. 
       FIG. 7  illustrates circuits blocked by an extended data path in a prior art configurable IC. 
       FIG. 8  illustrates an example of a tile in a configurable IC. 
       FIG. 9  illustrates an example of a non-neighboring offset connection. 
       FIG. 10  illustrates an example of a set of parallel non-neighboring offset connections. 
       FIG. 11  illustrates a close up of two tiles from the previous figure. 
       FIG. 12  illustrates an example of data path shifting. 
       FIG. 13  illustrates a more detailed example of data path shifting. 
       FIG. 14  illustrates the results of the logical operations from the previous figures. 
       FIG. 15  illustrates an example of actual wire paths for parallel non-neighboring offset connectors where each wire path is identical. 
       FIG. 16  illustrates an example of actual wire paths for parallel non-neighboring offset connectors where some wire paths are not identical to the other wire paths. 
       FIG. 17  illustrates a different topological layout of the set of tiles illustrated in  FIG. 10 . 
       FIG. 18  illustrates a close up of four tiles from the previous figure. 
       FIG. 19  illustrates an example of longer non-neighboring offset connections shifting a horizontal 8-bit data path by eight bits. 
       FIG. 20  illustrates two sets of parallel NNOCs starting on different rows ending on the same row. 
       FIG. 21  illustrates two sets of parallel NNOCs with each set ending on a different input locus of the same tile set. 
       FIG. 22  illustrates two successive rows of tiles with a set of NNOCs connecting them to two other successive rows of tiles. 
       FIG. 23  illustrates two successive rows of tiles with two sets of NNOCs connecting them to another rows of tiles. 
       FIG. 24  illustrates parallel NNOCs shifting a vertical data path. 
       FIG. 25  illustrates non-parallel NNOCs re-orienting a data path from horizontal to vertical. 
       FIG. 26  illustrates two sets of parallel NNOCs interlacing data from different sets of tiles. 
       FIG. 27  illustrates direct connections, parallel offset connections and non-parallel NNOCs consolidating an 8-bit data path into a 4-bit data path. 
       FIG. 28  illustrates a set of four tiles with two sets of NNOCs coming out of it and going to two other sets of four tiles. 
       FIG. 29  illustrates multiple sets of NNOCs going from one output locus on a tile set to multiple input loci on another tile set. 
       FIG. 30  illustrates multiple sets of NNOCs going from multiple output loci on a tile set to multiple input loci on another tile set. 
       FIG. 31  illustrates intra-tile connections. 
       FIG. 32  illustrates an example of a logic circuit with three input multiplexers. 
       FIG. 33  illustrates a user design implemented with the logic circuit and multiplexers of the previous figure. 
       FIG. 34  illustrates a more detailed user design implemented with the logic circuit and multiplexers of the previous figure. 
       FIG. 35  illustrates a 4-bit barrel shifter. 
       FIG. 36  illustrates some of the connections used in a 16-bit barrel shifter. 
       FIG. 37  illustrates a 16-to-1 multiplexer. 
       FIG. 38  illustrates a 16 bit barrel shifter. 
       FIG. 39  illustrates a 16-bit barrel set to shift a 16 bit word by one bit to the left. 
       FIG. 40  illustrates a 16-bit barrel set to shift a 16 bit word by six bits to the left. 
       FIG. 41  illustrates a 16-bit barrel set to shift a 16 bit word by eleven bits to the left. 
       FIG. 42  illustrates a 16-bit barrel set to shift a 16 bit word by twelve bits to the left. 
       FIG. 43  illustrates a topological wiring diagram to implement a 16-bit barrel shifter for shifting to the left and a 16 bit barrel shifter for shifting to the right. 
       FIG. 44  illustrates use of multiple sets of parallel NNOCs passing a signal through an interconnect circuit on a set of tiles. 
       FIG. 45  illustrates use of a set of parallel NNOCs coupled with use of parallel intra-tile connections. 
       FIG. 46  illustrates the use of subcycles in a reconfigurable integrated circuit. 
       FIG. 47  illustrates memory and a memory port. 
       FIG. 48  illustrates a memory with more logical ports than physical ports. 
       FIG. 49  illustrates multiple accesses of a memory location during one user cycle. 
       FIG. 50  illustrates a virtual memory presented as narrower and deeper than the physical memory. 
       FIG. 51  illustrates a flowchart of an example of virtual memory presented as being narrower and deeper than the physical memory. 
       FIG. 52  illustrates a barrel shifter and outputs presenting a narrowed memory. 
       FIG. 53  illustrates a conceptual diagram of an example of a memory with two ports. 
       FIG. 54  illustrates a user design with multiple memory blocks. 
       FIG. 55  illustrates a conceptual diagram of multiple memory blocks and memory ports for those memory blocks. 
       FIG. 56  illustrates a conceptual diagram of an example of user design memory blocks mapped to different locations is a physical memory. 
       FIG. 57  illustrates a flow chart for mapping user design memories to a physical memory accessed on a subcycle basis. 
       FIG. 58  illustrates a flow chart for determining the subcycles in which to map memory port accesses. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   In the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the invention may be practiced without the use of these specific details. For instance, not all embodiments of the invention need to be practiced with the specific number of bits and/or specific devices (e.g. multiplexers) referred to below. In other instances, well known structures and devices are shown in block diagram form in order to not obscure the description of the invention with unnecessary detail. 
   I. Overview 
   A. Brief Overview 
   Some embodiments provide novel wiring architectures for configurable integrated circuits (ICs). In some embodiments, the configurable resources of the IC include configurable logic circuitry and configurable interconnect circuitry. In some embodiments such configurable circuitry can be conceptually grouped into tiles that are arranged in some arrangement such as an array with a number of rows and columns of tiles. The configurable IC includes a first tile and a second tile that is offset from the first tile by at least one row and at least two columns or by at least one column and at least two rows. The configurable IC also includes a non-neighboring offset connection (NNOC) that directly connects an output of the first tile to an input of the second tile. Some embodiments use multiple parallel NNOCs to directly connect a first set of tiles to a second set of tiles that are offset from the first set of tiles in a similar manner to the one described above for individual tiles. 
   Some embodiments use NNOCs to implement a variety of useful circuit designs. For example, NNOCs, along with other connections and circuits, can be used to implement barrel shifters which shift data words by specified numbers of bits. In some embodiments, barrel shifters that shift by increments of one bit (which allow precise shifts) are placed before or after barrel shifters that shift by increments of multiple bits (which allow long shifts). These embodiments allow shifts that are both long and precise, with the multi-bit increment shifters providing long shifts and the one-bit increment shifters providing precise shifts. 
   In some embodiments, the logic circuitry of the configurable ICs mentioned above may include look up tables (LUTs) and input-select multiplexers (IMUXs) that select the inputs of the LUTs. These LUTs can themselves be configured to act as multiplexers. Such LUTs can be used along with the IMUXs to implement multiplexers with larger numbers of inputs. For example, a 3-input LUT can be configured as a two-input multiplexer with the first two inputs of the LUT receiving data bits a third input of the LUT receiving the selection bit. The IMUXs connected to the first two inputs can be configured as two-input multiplexers. The combination of these elements would act as a 4×1 multiplexer. Such LUT and IMUX multiplexers can be used to implement barrel shifters like the ones mentioned above. 
   Barrel shifters are used in some embodiments to present digital memories as being narrower and deeper than they are. Some embodiments provide novel techniques for accessing memory multiple times per user cycle. These embodiments may map virtual ports onto the multiple accesses. A more detailed overview of some features starts below. 
   B. Detailed Overview 
   Some embodiments of the invention provide architectures for configurable ICs that have configurable computational units (e.g., configurable logic circuits) and configurable routing circuits for configurably routing signals between the configurable computational units. For instance, some embodiments provide a configurable IC that can be thought of as having numerous configurable computational tiles (e.g., hundreds, thousands, hundreds of thousands, etc. of tiles) that are laid out on the IC according to a particular arrangement. These tiles are an abstraction used to represent sections of the IC rather than any sort of physical object. In some embodiments, the configurable computational tiles include configurable logic circuits and configurable interconnect circuits. In other embodiments, the only configurable circuits in the configurable computational tiles are configurable logic circuits or configurable interconnect circuits. 
   The computational tiles in some embodiments are arranged in numerous rows and columns that form a tile array. Also, the tile arrangement in some embodiments results in one or more sets of the configurable circuits (e.g., the configurable logic circuits and/or configurable interconnect circuits) being arranged in an array with several aligned rows and columns. Alternatively, some embodiments might organize the configurable circuits in an arrangement that is not an array. 
   For simplicity of explanation, the embodiments below are generally described and illustrated as being in arrays. However, some arrangements may have configurable circuits or tiles arranged in one or more arrays, while other arrangements may not have the configurable circuits or tiles arranged in an array. In the tile or circuit arrangement, some embodiments intersperse several other circuits, such as memory blocks, processors, macro blocks, IP blocks, SERDES controllers, clock management units, etc. Alternatively, some embodiments arrange some of these other circuits (e.g., memory blocks) within the tile structure. 
   In some embodiments, each routing interconnect circuit can receive several input signals and distribute output signals to several different types of circuits, such as routing or input select interconnect(s) of the same tile, or routing and input-select interconnects of other tiles. Also, routing interconnects can have a fan out greater than one in some embodiments. 
   In some embodiments, sets of multiple parallel connections directly connect sets of tiles with other sets of tiles. As further described below, a direct connection between two circuits is an electrical connection between the two circuits that is achieved by (1) a set of wire segments that traverse through a set of the wiring layers of the IC, and (2) a set of vias when two or more wiring layers are involved. In some embodiments, a direct connection between two circuits might also include a set of buffer circuits. 
   A particular computational tile&#39;s input select interconnect(s) can receive input signals from circuits outside or inside of the particular tile, and pass a set of these received signals to a logic circuit in the particular computational tile. In some of these embodiments, the particular computational tile&#39;s input select interconnects have direct connections with circuits in tiles that are several tiles away from the particular tile. In some of these embodiments, one or more of these other tiles are not vertically or horizontally aligned with the particular computational tile in the tile arrangement. In other words, some embodiments have several long direct offset connections for connecting the inputs of some input select interconnects with circuits that are in computational tiles that are offset from the particular computational tile by at least two rows and at least one column or by at least two columns and at least one row. 
   Some embodiments also have several offset connections between interconnects in different computational tiles. For instance, in some embodiments, the output of a routing interconnect in a particular computational tile can be supplied through an offset connection to the input of the routing interconnect of another computational tile. Such an offset connect can also be used to provide the output of a routing interconnect in one computational tile to the input select interconnect in another computational tile. Some embodiments use long offset connections to connect two interconnects that are neither in neighboring computational tiles nor in vertically or horizontally aligned computational tiles. Some embodiments also use long offset connections to provide the output of logic circuits to circuits that are in computational tiles that do not neighbor the computational tiles of the logic circuits. 
   The use of direct offset connections in the configurable IC of some embodiments increases the interconnectivity between the circuits of the configurable IC. In addition to computational tiles, some embodiments include other types of tiles (e.g., tiles that embed memory arrays) that do not include some or all of the circuits of a computational tile. In some embodiments, these other tiles connect to each other and/or to computational tiles in the same manner as was described above for connections between computational tiles. The configurable IC of some embodiments is a reconfigurable IC. In some of these embodiments, the reconfigurable IC is a subcycle reconfigurable IC. 
   Some embodiments use sets of non-neighboring offset connections to establish wide paths for data. In some such sets, the connectors are topologically parallel to one another, that is, parallel on a topological representation of the tiles and/or connectors. More detailed descriptions of such embodiments can be found below. 
   Some embodiments implement a user design that includes the tiles configured as four-to-one multiplexers. These embodiments allow the user&#39;s design to select which input of the four-to-one multiplexer is active. One type of device that may use such multiplexers is a barrel shifter. A barrel shifter is a device that can shift a data word by some number of bits. Some embodiments use barrel shifters to present the physical memory of the configurable IC as being narrower and deeper than it really is. 
   Some embodiments use a configurable IC that operates on a subcycle time scale. The configurable IC of such embodiments implements a user design that is treated as being run on a user design clock cycle (sometimes called “user cycle”) time scale. Multiple subcycles occur for each user design clock cycle. In some embodiments, the configurable IC can be re-configured once per subcycle, thus more than once per user cycle. Some such embodiments use the ability to access memory multiple times per user cycle to present the memory to the user design as having more logical memory ports than there are physical memory ports. 
   In some embodiments, a user is provided with a configurable IC and a set of behavioral descriptions about how to use multiple ports with different priority levels to write to the same memory address. More detailed descriptions of such embodiments can be found below. 
   II. Terms and Concepts 
   A configurable IC is an IC that has configurable circuits. In addition to configurable circuits, a configurable IC also typically includes non-configurable circuits (e.g., non-configurable logic circuits, interconnect circuits, memories, etc.). 
   A configurable circuit is a circuit that can “configurably” perform a set of operations. Specifically, a configurable circuit receives “configuration data” that selects an operation that the configurable circuit will perform out of a set of operations that it can perform. 
   In some embodiments, configuration data is generated outside of the configurable IC. In some embodiments, a set of software tools converts a high-level IC design (e.g., a circuit representation or a hardware description language design) into a set of configuration data that can configure the configurable IC (or more accurately, the configurable ICs configurable circuits) to implement the IC design. 
   Configurable circuits may include logic circuits and interconnect circuits. A logic circuit is a circuit that can perform a function (e.g. AND, OR, or XOR) on a set of input data that it receives. A configurable logic circuit is a logic circuit that can be configured to perform different functions on its input data set (see  FIG. 1  above). 
   One type of logic circuit is a look-up table (LUT) circuit. A LUT accepts a set of one or more input bits, and provides a set of one or more output bits. The output bits corresponding to a particular set of input bits are set before the input bits are received. A LUT performs the function its name indicates. It acts like a table with the input bits identifying the desired “row” in the table and the output bits being the entries in the output “column(s)” that intersect with the desired “row”. A configurable LUT allows the output “column(s)” to be set to whatever values are needed for the function the configurable IC is performing at the time. Unless otherwise specified, all LUTs in the embodiments described in this specification are configurable LUTs. However, other embodiments may use non-configurable LUTs. 
   A configurable interconnect circuit is a circuit that can configurably connect an input set to an output set in a variety of manners. One example of a configurable interconnect circuit is described in relation to  FIG. 2  above. Some interconnect circuits described in embodiments below are multiplexers. 
   A multiplexer (“MUX”) is a circuit that accepts a set of data inputs (sometimes called “data bits” or simply “inputs”) and a set of selection inputs (sometimes called “selection bits”). The multiplexer passes a subset of the data inputs to a set of data outputs. The particular subset that the multiplexer passes on is determined by the selection inputs. Different embodiments of multiplexers may implement this passing through of data in different ways. The passing through might be by establishing an electrical path between the selected input set and the output set of the multiplexer. The passing through could also be by indirectly passing the value of the data at the input set to the output set. Any means of providing the same values at the output set as at the selected input set would be within the definition of passing through used herein. 
   An input-select multiplexer (IMUX) is a multiplexer that supplies one input signal of the LUTs described in the embodiments below. In other words, an IMUX receives several input signals and passes one of these input signals to its LUT. 
   A routing multiplexer (RMUX) is an interconnect circuit that can receive signals from and supply signals to interconnect and logic circuits in its own or other tiles in the arrangement. Unlike an IMUX that only provides its output to a single logic circuit (i.e., that only has a fan out of 1), a routing multiplexer in some embodiments, either provides its output to several logic and/or interconnect circuits (i.e., has a fan out greater than 1), or provides its output to one other interconnect or logic circuit. 
   A user-design signal within a configurable IC is a signal that is generated by a circuit (e.g., logic circuit) of the configurable IC, or in some cases is received by a circuit in the configurable IC from input lines coming into the IC from outside. The word “user” in the term “user-design signal” connotes that the signal is a signal that the configurable IC generates (or receives from the outside) for a particular application that a particular user has configured the IC to perform. User-design signal is abbreviated to user signal in some of the discussion below. 
   In some embodiments, a user signal is not a configuration or clock signal that is generated by or supplied to the configurable IC. In some embodiments, a user signal is a signal that is a function of at least a portion of the configuration data received by the configurable IC and at least a portion of the inputs to the configurable IC. In these embodiments, the user signal can also be dependent on (i.e., can also be a function of) the state of the configurable IC. The initial state of a configurable IC is a function of the configuration data received by the configurable IC and the inputs to the configurable IC. Subsequent states of the configurable IC are functions of the configuration data received by the configurable IC, the inputs to the configurable IC, and the prior states of the configurable IC. 
   Some embodiments have “UMUXs”. A UMUX is a multiplexer that receives user-design signals for at least one of its data inputs and one of its selection inputs. A UMUX might receive a user-design signal directly from a configurable logic circuit or indirectly through one or more intermediate configurable interconnect circuits. Some UMUXs are “hybrid” UMUXs. A hybrid UMUX is one which can be set by the configuration data either to receive all its selection inputs from the configuration data or to receive one or more selection bit from user signals and the rest (if any) from the configuration data. 
   A direct connection is an electrical connection between two nodes that is achieved by (1) a set of wire segments that traverse through a set of the wiring layers of the IC, and (2) a set of vias when two or more wiring layers are involved. 
   In some embodiments, a direct connection might also include a set of buffer circuits in some cases. In other words, two nodes are directly connected in some embodiments by a set of wire segments that possibly traverse through a set of buffer circuits and a set of vias. Buffer circuits are not logic or interconnect circuits. In some embodiments, buffer circuits are part of some or all direct connections. Buffer circuits might be used to achieve one or more objectives (e.g., maintain the signal strength, reduce noise, delay signal, etc.) along the wire segments that establish the direct connections. Inverting buffer circuits also allow an IC design to reconfigure logic circuits less frequently and/or use fewer types of logic circuits. In some embodiments, buffer circuits are formed by one or more inverters (e.g., two or more inverters that are connected in series). A via is an opening in the insulation between wiring layers that allows wires on different wiring layers to form an electrical connection. 
   In the embodiments described below, most of the interconnect circuits are multiplexers, each with eight inputs and one output. Multiplexers in other embodiments may have other numbers of inputs and/or outputs. Also in the embodiments described below, most of the logic circuits are LUTs, each with three inputs and one output. One of ordinary skill in the art will realize that other embodiments may have different types of interconnect or logic circuits, and that other embodiments can have interconnect or logic circuits with different numbers of inputs. It will also be clear to one of ordinary skill in the art that the configurable ICs may extend considerably farther than the regions shown, and that the tiles on the edge of the illustrated regions may not be on the edges of the configurable ICs. 
   A non-neighboring offset connection (NNOC) is a direct connection that connects two tiles that are not in the same column or row as each other and are either at least two rows or at least two columns apart. 
   A virtual memory port (sometimes referred to as a “logical memory port”) is a port in a user design that the user design treats as though it is a physical port, but that is not a physical port. In some embodiments a virtual memory port may be associated with a specific physical port, but accesses to the memory using the virtual port would be limited to specific fractions of the available time of the physical memory port. In other embodiments a virtual port may be assigned to various physical ports using some assignment plan. 
   A clock domain is the time of operation. Integrated circuits typically use clocks to tell them when to perform an operation. Such clocks typically provide a square wave or other repeating function. Some integrated circuits have all or substantially all their digital circuits perform an operation within a time period specified by the clock. Some circuits perform one set of operations per clock cycle, some perform a set of operations each time the repeating function is high, some perform a set of operations each time the repeating function is low, some perform a set of operation when the repeating function switches from high to low or from low to high, or both. A single integrated circuit may have components that use different sets of signals. In each case, a set of operations that are supposed to take place simultaneously with each other are said to occur within a single clock domain. Clock domains are represented for some embodiments in tables with a “0” for operations supposed to occur when the repeating function is high, a “1” for operations supposed to occur when the repeating function is low and with an arrow for operations supposed to occur when the repeating function switches from high to low or vice versa. More detailed descriptions of several embodiments can be found below. 
   A user is anyone who operates something or causes it to be operated. Providing something to a user includes any way of providing it, including, but not limited to, giving, leasing or selling the thing to the user, giving, leasing or selling the thing to a third party who will give or sell it to the user or to a chain of people or entities that will ultimately result in the item being in the user&#39;s custody or possession. Providing information may include providing it in text form, in some magnetic, optical, or other digital media form, providing a download of the information or any other way of transmitting it. Parameters chosen by a user may include, but are not limited to parameters that are set by another person or a computer program on the user&#39;s behalf. 
   III. Configurable Integrated Circuit Architecture 
   A. Example of a Tile 
   Some embodiments of the invention are implemented in configurable ICs. The configurable ICs have configurable interconnect and logic circuits. These interconnect and logic circuits can be conceptually grouped in configurable “tiles”. Such tiles may be arranged in arrays of rows and columns or in other groupings. The tiles themselves are not physical objects, but are a way of describing sections of the array or grouping of circuits.  FIG. 8  illustrates a tile of some embodiments. In this figure, the interconnects are multiplexers and the logic circuits are look up tables. This figure shows a tile with eight routing multiplexers (“RMUXs”)  810 , three input-multiplexers (“IMUXs”)  820  and one look-up table  805 . Each of these multiplexers selects one among several inputs and allows data coming in on that input to pass through to the output of that multiplexer. The selected input can be called the “active input”. The IMUXs select among their various inputs and pass the selected input on to the look-up table. A particular input line on a particular multiplexer can be called an “input locus”. Thus there are sixty-four input loci of the eight RMUXs  810  and twenty-four input loci of the three IMUXs  820  of the tile in  FIG. 8 . 
   In some embodiments, multiple tiles may each have circuits identical to each other. Two input loci, one on each tile, that occupy the same position relative to their tiles can be referred to as “corresponding inputs”. For example, the leftmost input of the middle IMUX on one tile is the corresponding input to the leftmost input of the middle IMUX on another tile. Selecting an input locus for a set of tiles means that the input at that locus on each tile in the set becomes an active input. 
   In some embodiments, each RMUX, IMUX, and LUT has a single output. However, for RMUXs and LUTs, this output may fan out to directly connect to several other inputs. That is, one output value can be sent to many input loci. A direct connection is not itself configurable, but if the input is one of the inputs of a multiplexer, then the multiplexer can be used to select which of several direct connections to receive data from and which ones to ignore. This type of selection is accomplished by making the appropriate input active. 
   The outputs (not shown) of the RMUXs  810  may connect to inputs on IMUXs  820  or other RMUXs  810  on the same tile, or to IMUXs or other RMUXs on other tiles (not shown). The output of the look-up table  805  may connect to inputs on IMUXs  820  or RMUXs  810  on the same tile, or to IMUXs or RMUXs on other tiles (not shown). In several of the figures, some of these features may be omitted for clarity, but those skilled in the art will realize that they may be present in some embodiments. In particular, several figures have some or all of the RMUXs not shown in order to reduce confusion. 
   B. Connections Between Tiles 
   Connections between tiles in a configurable IC affect the function of the configurable IC. These connections will be illustrated in some of the following figures using an array of squares, such as that shown in  FIG. 9 . Each small square represents a tile. Tiles drawn with thick lines (such as tiles  905   a  and  905   b ) are used to illustrate concepts of the invention. Tiles drawn with thin lines are used to illustrate the point that there are more tiles in a configurable IC than the few that are specifically identified in the descriptions of the figures. A line from one thick tile to another thick tile, such as line  910 , represents a direct connection. The connection connects an output of the tile at the arrow&#39;s tail to an input of the tile with the arrow head. Unless otherwise indicated, connection lines are topological only, and not necessarily the physical paths that the wires take. It will be clear to one of ordinary skill in the art that any of the connection types described below can be present in the same embodiment as other types of the connections, including the types described below and any connection type found in the prior art. 
   C. Non-Neighboring Offset Connections 
   Some embodiments include direct connections between tiles not in the same row or column and not neighboring each other. These connections can be called non-neighboring offset connections (“NNOC”). NNOCs can be further characterized by providing two integers indicating the amount of offset along each direction, in the format NNOC (m,n). One example is that an NNOC (1,2) is a direct connection between an output of a first tile and an input of a second tile one column to the left and two rows down from the first. For NNOCs connecting from an output of a first tile to an input of a tile above or to the right of the first circuit, negative numbers are used. One example is NNOC (−3,−1) is a direct connection between an output of a first tile and the input of a second tile three columns to the right of it and one row above it. The use of these two integers is a shorthand for this specification and leaves out information about which output locus, in the first tile, and which input locus, in the second tile, the NNOC connects. It will be clear to those skilled in the art that this means of characterizing the connections is a way of explaining some embodiments and other embodiments also lie within the scope of the invention. 
   An illustration of an NNOC is found in  FIG. 9 . In this figure an output of tile  905   a  is connected to an input of tile  905   b . The tile  905   b  is one column to the left and two rows down from tile  905   a , so the NNOC  910  that connects them can be described as an NNOC (1,2). This is the shortest possible NNOC. Any tiles closer to tile  905   a  are either neighbors or in the same row, or in the same column as tile  905   a.    
   D. Parallel Non-Neighboring Offset Connections 
   Some embodiments include multiple parallel NNOCs. These are NNOCs that connect outputs of a set of successive tiles to inputs of another set of successive tiles. Parallel NNOCs are illustrated in  FIG. 10 .  FIG. 10  shows tiles  1000 - 1031 . The figure also shows that NNOCs  1045   a - 1045   d  connect the outputs of the look up tables of tiles  1027 - 1030 , in tile set  1040 , to inputs of tiles  1004 - 1007 , in tile set  1050 . 
   As described above, a tile of a configurable IC often has multiple inputs. In some embodiments, each tile in the configurable IC has inputs that are identical to the inputs of other tiles. In a set of parallel NNOCs, each NNOC connects to an input on its destination tile that corresponds to inputs on the destination tiles of the other NNOCs in that set of parallel NNOCs.  FIG. 11  illustrates this by showing a close up of tiles  1006  and  1007 . NNOC  1045   c  connects to input locus  1106   c  on tile  1006  and NNOC  1045   d  connects to input locus  1107   c  on tile  1007 . Though not shown, NNOC  1045   a  and  1045   b  also connect to the corresponding input loci on their respective destination tiles (not shown). 
   It will be clear to those skilled in the art that in some embodiments, the correspondence is topological rather than physical. Thus, in some embodiments, the corresponding input may be on a different part of the tile. In such embodiments, correspondence means that the input the NNOC connects to serves an identical function to the inputs other parallel NNOCs connect to, including its logical relationships to the other inputs. The corresponding input is not necessarily physically in the same place on the IC. 
   E. Data Paths and Data Words 
   Some embodiments allow for chains of logical operations, one after another. Some such embodiments allow for multiple bit “words” to be used, in which all bits in the word are subject to similar or identical operations. In some embodiments, a tile can only perform logical operations on one bit of that word at a time. So in order to perform an operation on a multi-bit word, multiple tiles must be used. When several operations need to be performed on a multi-bit word, this occupies whole sets of tiles, generally with a width equal to the number of bits in the word, and length equal to the number of operations to be performed (not counting skipped rows or columns in the length or width). Such sets of used tiles can be called a “data path”. In some embodiments, data paths can be oriented horizontally or vertically. A horizontal data path is one in which the multi-bit words are oriented horizontally, such that an operation on the word takes place in one row of tiles. A vertically oriented data path is one in which the multi-bit word is oriented vertically, such that an operation on the word takes place in one column of tiles. 
   1. Data Path Shifting 
   Multiple NNOCs, parallel to each other, can be used to shift later parts of a data path to a different set of columns. An embodiment is illustrated in  FIG. 12 . Tile set  1230  contains 8 tiles,  1205   a - 1205   h . Tile set  1240  also contains 8 tiles  1215   a - 1215   h . The data path includes the tiles in those tile sets, along with the tiles above tile set  1230  and the tiles below tile set  1240 . Connections between the tiles above tile set  1230  and connections between tiles below tile set  1250  go vertically from one row to the next and are not shown, for clarity. 
   The output of each look up table (not shown) in tile set  1230  is directly connected to an input of an IMUX (not shown) in tile set  1240  through an NNOC (2,3). Tile  1205   a  is connected to tile  1215   a  through NNOC (2,3)  1210   a . Tile  1205   b  is connected to tile  1215   b  through NNOC (2,3)  1210   b , and so forth. Each of the parallel NNOCs (2,3) has the effect of moving the data path of one bit two columns to the left. The combined effect of all 8 NNOCs (2,3) is to move the 8-bit data path two columns to the left. 
   2. Example of Using NNOCS 
   One example of a specific application accomplished with the use of NNOCs is an adding operation followed by a logical AND operation. In  FIG. 12 , the tiles  1205   a - 1205   h  in tile set  1230  can be configured as an 8-bit adder (inputs not shown), and the tiles  1215   a - 1215   h  in tile set  1240  can take the results of that addition, and perform a logical AND operation on each bit along with a separate set of 8 bits from some other source (not shown). 
   A more detailed picture of such an arrangement can be found in  FIG. 13 . Though more detailed, it will be clear to those skilled in the art that details have been omitted for the purpose of clarity, including carry-over logic for the adder and the source of some inputs. The tile set configured as a group of eight 1-bit adders  1230  of  FIG. 13  takes inputs of two 8-bit numbers  1330 - 1337  and  1340 - 1347 . These inputs come in as two sets of eight 1-bit numbers to the individual 1-bit adders  1205   a - 1205   h . The tile set configured as a group of eight 1-bit adders  1230  outputs the sum of the two numbers. The NNOCs  1210   a - 1210   h  connect the outputs of the tile set configured as a group of eight 1-bit adders to inputs of the individual AND gates  1215   a - 1215   h  in the tile set configured as a group of eight logical AND gates  1240 . 
   The combined result of the tiles and connections produces the same result as using a single 8-bit adder and eight logical AND-gates. A single 8-bit adder and eight logical and gates are represented in conceptual form in  FIG. 14 . In this figure, only one logical AND-gate  1440  is shown, but it represents a group of eight logical and gates. Input lines  1407   a  and  1407   b  each represent eight input wires going into the 8-bit adder  1430  and connection line  1410  represents the eight parallel NNOCs from the previous figure. 
   F. Layouts 
   1. Actual Wire Paths 
   The NNOCs previously shown are topological representations of connections, rather than actual wire paths. In some embodiments, actual wire paths for topologically identical connections are themselves identical, such as those shown in  FIG. 15 . Here, the tiles in tile set  1530  are connected to the tiles in tile set  1540  by identical wire connections  1510   a - 1510   h . Some other embodiments implement NNOCs with non-identical wiring connections, such as shown in  FIG. 16 . This figure shows wire connections  1610   a - 1610   h  that are not all identical. It will be clear to those skilled in the art that these are merely some examples of actual wiring. Other examples may contain vias, multiple wire layers, buffer circuits, or even diagonal wires, while all still being within the scope of the invention. 
   2. Topological Sequence of Tiles 
   In addition to the illustrated connections being topological, rather than physical paths of wires, the arrangement of successive tiles may also be topological rather than physical. For example, the array shown in  FIG. 10  might be a topological representation of a set of tiles whose physical arrangement matches that shown in  FIG. 17 . In both  FIG. 10  and  FIG. 17  there are tiles  1000 - 1031 . Each row of eight tiles shown in  FIG. 10  is a topological representation of a double row of tiles shown in  FIG. 17 . Note that the numbering of the tiles is the same in  FIG. 10  and  FIG. 17 . In some embodiments, the tiles in  FIG. 17  may have that physical arrangement to make fabrication easier, or to make it easier for sets of four tiles to share resources. In those embodiments, the topological model shown in  FIG. 10  may make it easier for a layman to understand the parallelism of the NNOC tile connections. The NNOCs of these embodiments are considered topologically parallel. They are topologically parallel (i.e. shown as parallel in the topological representation) because they connect corresponding outputs on one set of tiles with corresponding inputs on another set of tiles. In some embodiments, the NNOCs shown in  FIG. 17  connect to corresponding input loci on their respective tiles. This is illustrated in  FIG. 18 . This figure shows an enlarged view of tiles  1004 - 1007 . The NNOCs  1045   a - 1045   d  all go to the corresponding inputs  1107   c ,  1106   c ,  1805   c  and  1804   c  on their respective tiles. 
   G. Variations of NNOCS 
   There are several variations on parallel NNOCs illustrated in the following figures. Parallel NNOCs can be long, such as the ones shown in  FIG. 19 . This figure shows the tiles in tile set  1930  connecting to the tiles in tile set  1940  through NNOCs (8,12)  1910   a - 1910   h . In this figure, the parallel NNOCs shift the data path by as many columns as the length of the word. Those skilled in the art will realize that NNOCs can also shift a data path by more than the length of the word or less than the length of the word. 
     FIG. 20  shows two sets of parallel NNOCs bringing two 4-bit data paths together into one 8-bit data path. Here, the tiles in tile set  2030  are connected to the tiles in tile set  2040  by NNOCs (8,12)  2010   a - 2010   d  and the tiles in tile set  2035  are connected to the tiles in tile set  2040  by NNOCs (−2,7)  2015   a - 2015   d . This figure also shows that multiple sets of parallel NNOCs can exist within one configurable IC. The parallel NNOCs  2015   a - 2015   d  and  2010   a - 2010   d  are the same within each set, but the NNOCs in one set are not necessarily the same as the NNOCs of another set. 
     FIG. 21  shows multiple sets of parallel NNOCs connecting to different inputs on the same set of tiles. The tiles in tile set  2130  are connected to one set of inputs of the tiles  2120   a - 2120   d  by NNOCs (5,6)  2110   a - 2110   d . The tiles in tile set  2140  are connected to a second set of inputs of the tiles  2120   a - 2120   d  by NNOCs (−4,4)  2115   a - 2115   d . The figure also shows an expanded view of tile  2120   d . This expanded view shows NNOC (5,6)  2110   d  connecting to one input and NNOC (−4,4)  2115   d  connecting to a second input. This wiring arrangement could be used, for example, to implement a 4-bit adder. The 4-bit adder would include the look-up table  805 , and the look-up tables (not shown) in tiles  2120   b - 2120   d  configured as 1-bit adders, and additional circuitry (not shown) used to accommodate carried values. Accordingly, with the appropriate pairs of inputs on each tile selected, this wiring arrangement would allow two 4-bit words to be added to each other, one 4-bit word from tile set  2130  and another from tile set  2140 . 
     FIG. 22  illustrates an embodiment in which successive rows of tiles  2210  and  2220  have a set of parallel NNOCs that lead to successive rows of tiles  2230  and  2240 . In some embodiments, this arrangement of parallel NNOCs is repeated for several rows. Some other embodiments repeat this type of arrangement of parallel NNOCs over substantially the entire configurable IC. Successive rows of tiles can also have multiple sets of parallel NNOCs.  FIG. 23  illustrates an embodiment with successive rows of tiles  2310  and  2320  with sets of parallel NNOCs that lead to different sets of tiles  2330  and  2340 . 
   When tiles in several successive rows have parallel NNOCs, a word in the data path can be oriented and shifted vertically.  FIG. 24  illustrates this, as the 8-bit wide data path is oriented vertically, and the tiles in tile set  2410  have NNOCs  2420  connecting them to the tiles in tile set  2430 . The NNOCs shift the data path four tiles downward. 
   Some embodiments allow for both vertically and horizontally oriented data paths. Some embodiments use non-parallel connections to re-orient data paths from horizontal orientation to vertical orientation.  FIG. 25  illustrates an example of non-parallel offset connections that can be used to re-orient a data path from a horizontal orientation to a vertical orientation. In this figure, the data path is oriented horizontally when it enters tile set  2510 . The data path connects through non-parallel NNOCs  2511 - 2518  to the tiles in tile set  2530 , and in the process, the data path is re-oriented to a vertical orientation, which it maintains as it leaves tile set  2530 . 
   Some embodiments allow a word to be constructed from every other bit of two other words, with alternating bits.  FIG. 26  shows how parallel NNOCs can be used to interlace data from different rows. In this figure, tiles  2610   a ,  2610   b ,  2610   c , and  2610   d , connect to tiles  2630   a ,  2630   c ,  2630   e , and  2630   g  respectively. Tiles  2620   a ,  2620   b ,  2620   c , and  2620   d  connect to tiles  2630   b ,  2630   d ,  2630   f , and  2630   h  respectively. The net result of these connections is to interlace the bits from tiles  2610   a - d  and  2620   a - d.    
   Some embodiments allow parallel offsets that bring together successive bits of a word, in operations such as adding, or other operations that have two input bits and one output bit.  FIG. 27  shows how parallel offset connections  2710  can be used to combine successive bits in a data word in such operations. The figure also shows how non-parallel NNOCs  2721 - 2724  bring data from tiles  2730  together in tile set  2740 , completing a change from an 8-bit data path to a 4-bit data path. 
   Some embodiments allow multiple direct connections to leave one tile.  FIG. 28  illustrates that multiple sets of parallel NNOCs  2810  and  2815  can leave one set of tiles  2820  for multiple other sets of tiles  2830  and  2840 . In some embodiments, multiple NNOCs fan out from a single output to inputs on several other tiles. In some embodiments, multiple NNOCs come from multiple outputs on a single tile and terminate on inputs of multiple tiles. 
   Some embodiments use multiple sets of parallel NNOCs that go from one or more output loci on a set of tiles to more than one input loci on another tile.  FIG. 29  illustrates multiple sets of parallel NNOCs  2911 ,  2912 , and  2913  going from one output loci  2910  of a set of tiles to multiple input loci  2930 ,  2940 , and  2950  of another set of tiles. This figure demonstrates that direct connections can start from RMUXs, such as RMUXs  2970  rather than simply being limited to starting from LUTs  850 . The figure also demonstrates that direct connections can terminate at inputs to RMUXs, such as RMUXs  2980  and  2990 . Taken together, these features allow data to enter and leave a tile using only RMUXs, without passing through the LUT at all, as will be further illustrated in  FIG. 44 , below. 
     FIG. 30  shows multiple sets of parallel NNOCs  3011 ,  3012 , and  3013  going from multiple output loci  2910 ,  3020 , and  3030  of a set of tiles to multiple input loci  3040 ,  3050 , and  3060  of another set of tiles. It will be clear to one of ordinary skill in the art that multiple NNOCs from one tile to another can be present in the same embodiment as other direct connections to or from the same tiles, whether NNOCs or other types of connections. 
   H. Parallel Intra-Tile Connections 
   Some embodiments include intra-tile connections, for example, a connection from the output of an RMUX to one of the inputs of an IMUX in the same tile or to another RMUX in the same tile. Such parallel intra-tile connections are illustrated in  FIG. 31 . In this figure, parallel connections  3115  connect RMUXs  3120  to inputs of IMUXs  3130 . Parallel connections  3145  connect RMUXs  3150  to inputs of IMUXs  3160 . In some embodiments, where multiple parallel NNOCs from other chips provide inputs to RMUXs  3120  or  3150 , parallel connections  3115  and  3145  (respectively) may provide a step of the data path on its way from one set of tiles to another. 
   I. Four-Input Multiplexer 
   Some embodiments include tiles that can be configured in the user design as four input multiplexers. An example of such embodiments is illustrated in  FIG. 32 .  FIG. 32  illustrates part of a tile; the illustrated part includes a LUT  805  and three IMUXs  3210 ,  3220  and  3230 . The IMUXs  3210 ,  3220  and  3230  each have eight inputs. IMUXs  3210 ,  3220 , and  3230  each require three selection bits,  3211 - 3213 ,  3221 - 3223 , and  3231 - 3233  (respectively) to select which of the eight inputs will be active. Selection bits  3211 ,  3212 ,  3221 ,  3222 , and  3231 - 3233  for IMUXs  3210 ,  3220  and  3230  are provided by configuration data. Selection bits  3213  and  3223  are provided by user signals. 
   The two selection bits  3211 - 3212  provided by the configuration data for IMUX  3210  narrow down the set of potential active inputs of that IMUX from eight inputs to two inputs. The third selection bit  3213  is provided by a user signal. This selection bit  3213  determines which of the two remaining inputs is the active one. From the perspective of the user, the eight-input IMUX  3210  acts as a two-input multiplexer controlled by the user signal. IMUX  3220  and its inputs are set up in a similar fashion. 
   The three selection bits for IMUX  3230  select one input. The bit coming in on that selected input is provided by a user signal, effectively turning IMUX  3230  into a pass-through for a bit provided by the user signal. The effective components defined by this configuration are illustrated in  FIG. 33 . 
   In  FIG. 33  the IMUX  3210  operates as a two-input multiplexer, with selection bit  3213  selecting between inputs  3314  and  3315 . Similarly, IMUX  3220  operates as a two-input multiplexer, with selection bit  3223  selecting between inputs  3324  and  3325 . The input  3335 , which was selected by selection inputs  3231 - 3233  is passed through directly to the LUT  805 . 
   The LUT  805  can also be configured as a two-input multiplexer.  FIG. 34  illustrates a conceptual diagram of the circuit when the LUT  805  is configured as a two-input multiplexer, with the third input  3335  acting as the selection bit. The LUT  805  remains physically a LUT but acts as a two input multiplexer. The values for the table of the LUT  805  necessary to configure the LUT  805  as a two-input multiplexer will be obvious to one of ordinary skill in the art. In  FIG. 34 , two IMUXs  3210  and  3220  are set up as two-input multiplexers and the outputs of the multiplexers are fed into the inputs  3406  and  3407  of LUT  805  configured as a two-input multiplexer  805 . In that configuration, the tile will act as a four-input multiplexer. User signals on selection inputs  3213  and  3223  select among the four inputs  3314 ,  3315 ,  3324 ,  3325  and another user signal on selection input  3335  selects between inputs  3406  and  3407 , and passes the result to the output  3450 . Note that in some embodiments, the user signals on selection inputs  3213  and  3223  may come from a single source (or a have a single value), and the user signal on selection input  3335  may come from a second source. In other embodiments, the selection bits on selection inputs  3213 ,  3223 , and  3335  may come from separate sources. 
   For example, a selection bit with a value “0” sent to IMUXs  3210  and  3220  activates input  3314  of IMUX  3210  and input  3324  of IMUX  3220 . A second selection bit with a value of “0” is sent to look-up table  805 , activating input  3406 . The net result of these two selection bits is that data coming in to input  3314  is passed through to output  3450 . 
   J. Barrel Shifting 
   One application of parallel NNOCs allows a section of a configurable IC to be configured as a barrel shifter. A barrel shifter is a device that can shift a data word by some number of bits. Some barrel shifters allow shifts of amounts ranging from zero to one less than the length of the word. For example, a four-bit barrel shifter can take as its input a four-bit word, “ABCD” (each letter representing one bit) and shift it to the left by zero, one, two, or three positions, resulting in (respectively) “ABCD”, “BCD0”, “CD00”, or “D000”. A four-bit barrel shifter that shifts bits to the right by zero, one, two, or three positions would result in (respectively) “ABCD”, “0ABC”, “00AB”, or “000A”. In each case, bits that are shifted outside the range of the word (left of the leftmost, or right of the rightmost) are lost. In the preceding example, positions that don&#39;t have a corresponding bit before the shift are filled in with zeros, however it will be clear to one of ordinary skill in the art that those bits could be filled in with ones, or with random bits, or with the bits they started with, or with inversions of the bits they started with, or by any other method of determining which values to fill the vacated positions. 
   1. 4-Bit Barrel Shifter 
   Barrel shifters are known to those skilled in the art, though applying NNOCs in a configurable IC to create a barrel shifter is not. Some embodiments create a barrel shifter with NNOCs and multiplexers such as the four input multiplexer described above.  FIG. 35  illustrates the implementation of a four-bit barrel shifter by use of four-input multiplexers, NNOC connections, and non-NNOC connections. Tiles  3500 - 3503  act as four-input multiplexers. Connections  3510   a ,  3511   a ,  3512   a , and  3513   a  each connect an output on one tile to an input of a tile three rows below (intermediate rows omitted for clarity) and in the same column as the starting tile. Specifically, they connect outputs of tiles  3528 - 3531  to inputs  3500   a ,  3501   a ,  3502   a , and  3503   a  on tiles  3500 - 3503 . As a result of these connections, selecting in tandem the inputs  3500   a ,  3501   a ,  3502   a , and  3503   a  “shifts” the data bits originally in tiles  3528 - 3531  by zero. Selecting a set of inputs in tandem may be done by sending a common value to corresponding multiplexers on each tile, or in other embodiments by ganging the selection bits together so that they receive their user signals from a common source. If the original data word, in tiles  3528 - 3531  was “ABCD” the resulting word in tiles  3500 - 3503  would be “ABCD”. 
   NNOCs  3511   b ,  3512   b , and  3513   b  each connect an output on one tile to an input of a tile three rows below and one column to the left of the starting tile. As a result of these NNOCs, selecting in tandem the inputs  3500   b ,  3501   b ,  3502   b , and  3503   b  shifts the data bits originally in tiles  3528 - 3531  by one position to the left. If the original data word, in tiles  3528 - 3531  was “ABCD” the resulting word in tiles  3500 - 3503  would be “BCD0”. 
   NNOCs  3512   c  and  3513   c  each connect an output on one tile to an input of a tile three rows below and two columns to the left of the starting tile. As a result of these NNOCs, selecting in tandem, the inputs  3500   c ,  3501   c ,  3502   c , and  3503   c  shifts the data bits originally in tiles  3528 - 3531  by two positions to the left. If the original data word, in tiles  3528 - 3531  was ABCD the resulting word in tiles  3500 - 3503  would be “CD00”. 
   NNOC  3513   d  connects an output on one tile to an input of a tile three rows below and three columns to the left of the starting tile. As a result of this NNOC, selecting in tandem, the inputs  3500   d ,  3501   d ,  3502   d , and  3503   d  shifts the data bits originally in tiles  3527 - 3531  by three positions to the left. If the original data word, in tiles  3527 - 3531  was ABCD the resulting word in tiles  3500 - 3503  would be “D000”. 
   In some embodiments, the barrel shifter might be characterized as including the top row of tiles. In other embodiments, it might be characterized as only including the lower row (or rows in multi-layer barrel shifters) of tiles and the connections between the upper row and the lower row(s). In such embodiments the tiles in the upper row could be replaced with a block of memory with outputs where the outputs of the logic circuits are in  FIG. 35 . A more detailed description of this may be found in sub-section K.2 below. 
   2. Multi Layer Barrel Shifter 
   In some embodiments, each multiplexer in a barrel shifter can select one out of n signals, where n is the number of selectable inputs of the multiplexer. A barrel shifter implemented with that type of multiplexer can choose n different shift amounts, each shift amount corresponding to one input of the multiplexers. Appropriate wiring would allow each of the specific n shift amounts allowed by a barrel shifter to be any arbitrary number of bits. For example, a one level barrel shifter could be implemented (with four bit multiplexers and words of more than forty bits) that would allow shifts of five, twelve, thirteen and forty bits, but would not allow shifts of any other number of bits. 
   Some barrel shifters allow shifts from zero to some set number of bits (in increments of one bit). Some embodiments implement barrel shifters allowing shifts from zero to more than n−1 bits (in increments of one bit). Some such embodiments use two or more layers. One layer shifts the word by zero, one, two, . . . , or n−1 bits. The second layer would shift the word by zero, n, 2n, . . . , or n(n−1) bits. Each layer of such an implementation is itself a barrel shifter. Each layer chooses from n possible shift amounts, and by using various combinations of shift amounts, a total shift of any amount between zero and n 2 −1 can be chosen. It will be clear to one of ordinary skill in the art that still larger barrel shifter can be implemented by increasing the number of layers, or by using multiplexers with larger numbers of inputs in one or more layers. 
   3. 16-Bit Barrel Shifter 
   In the figures below, the multiplexers have four inputs. The two layered barrel shifters implemented with such multiplexers allow shifts from zero to fifteen bits. Even a topological diagram of such an arrangement is complicated, so the next few figures provide subsets of the wiring required for an entire 16-bit barrel shifter. The barrel shifter diagrams also omit the intermediate tiles, this is for clarity of drawing, and not because these tiles are missing from the embodiment. Also for clarity, the relevant tiles in the next several diagrams will be numbered, but not drawn in thick lines like the thick lined tiles drawn in some previous figures. 
     FIG. 36  illustrates one set of connections that can be used to send output from tile  40  to any selected tile  0 - 15 . Each of the dotted lines between two tiles is a topological representation of a direct connection from one tile to another. An expanded view of tile  15  shows the inputs as shown in the previous description of 4-input multiplexers. As further described below by reference to  FIG. 37 , up to four connections of the barrel shifter terminate on each tile  0 - 15 , where each of those connections goes to one input of the four-input multiplexer. 
   A data bit starts out as an output of tile  40 . This output of tile  40  fans out through connection  3620  and NNOCs,  3624 ,  3628 , and  3632  to multiplexer inputs (not shown) on tiles  20 ,  24 ,  28 , and  32 . Each of the connections  3620 - 3632  leads to a different input locus on their respective destination tiles, in the same manner as the connections in the 4-bit barrel shifter in  FIG. 35 . By selecting the appropriate input, tiles  20 ,  24 ,  28 , and  32  can pass on or not pass on data from tile  40 . For example, if tiles  20 ,  24 ,  28 , and  32  all select the rightmost input locus, then only tile  32  will pass on the data from tile  40 , because tile  40  connects to the rightmost input locus only on tile  32 . Once the data bit has passed through (in this example) tile  32 , it comes out an output of tile  32  and fans out to tiles  12 - 15 . Again, each output goes to a different input locus on its destination tile, and again, by selecting the appropriate input, any of the tiles  12 - 15  can receive the data bit that originally started with tile  40 . 
   Some embodiments use NNOCs, non-NNOC connections, and tiles set up as four-input multiplexers to select one bit out of a 16-bit word, effectively creating a 16-input multiplexer. This is illustrated in  FIG. 37 . Tiles  40 - 43  send their outputs via parallel NNOCs to tiles  32 - 35 , respectively. These connections all go to the same input locus on their respective tiles, in this illustration, the rightmost input. Similarly, tiles  44 - 47  send their outputs via another set of parallel NNOCs to tiles  32 - 35 . However, these NNOCs all go to the second input locus from the right, on their respective tiles. Similar connections go from the outputs of tiles  48 - 51  and  52 - 55  to their respective input loci on tiles  32 - 35 . By selecting appropriate inputs on tiles  32 - 35  and tile  15 , any data bit from tiles  40 - 55  can be received by tile  15 . 
   Some embodiments use NNOCs to create 16-bit barrel shifters, such as the one illustrated in  FIG. 38 . In this figure, a 16-bit word starts in tiles  40 - 55 , is shifted zero, four, eight, or twelve bits to the left by selecting the appropriate set of corresponding inputs on tiles  20 - 35  and is then shifted a further zero, one, two, or three bits to the left by selecting the appropriate set of corresponding inputs in tiles  0 - 15 . In some embodiments, the selection of appropriate sets of corresponding inputs is done using parallel NNOCs or parallel non-NNOC connections. In some other embodiments, multiple selection inputs (not shown) of the MUXs (not shown) on the tiles come from common sources of user signals. In some of these embodiments, all the tiles in a particular row of the barrel shifter receive the same values (sometimes from the same sources ganged together) for the two one-bit user signals that select the corresponding inputs. 
   Examples of the connections selected to implement various word-shifts are illustrated in  FIGS. 39-41 . In these figures, the thick solid lines with arrows connecting tiles are topological representations of direct connections going to active inputs, the dotted lines with arrows connecting tiles are topological representations of direct connections to inactive inputs. In  FIG. 39  the leftmost input of each tile  20 - 35  is selected. The leftmost input of each destination tile  20 - 35  is connected to the output of a tile  40 - 55  four rows above and in the same column as the destination tile. Selecting the leftmost input of each tile  20 - 35  thus shifts the 16-bit word by zero bits, leaving the same 16-bit word on tiles  20 - 35  as were originally on tiles  40 - 55 . Subsequently, the second input from the left is selected for tiles  0 - 15 . The second input from the left of each destination tile  0 - 15  is connected to the output of a tile  20 - 35  three rows above and one column to the right of the destination tile. Selecting the second from the left input of each tile  0 - 15  thus shifts the 16-bit word by one bit to the left. Thus the net result of passing through the selected connectors is to shift the 16-bit word one bit to the left from where it had been on tiles  40 - 55 . Representing each bit as a letter, with gaps for clarity, the results of the shifts would be: 
   
     
       
         
             
             
             
           
             
                 
                 
             
           
          
             
                 
               Tiles 40-55: 
               ABCD EFGH IJKL MNPQ 
             
             
                 
               Tiles 20-35: 
               ABCD EFGH IJKL MNPQ 
             
             
                 
               Tiles  0-15: 
               BCDE FGHI JKLM NPQ0 
             
             
                 
                 
             
          
         
       
     
   
   The zero in the bit streams indicated above indicates a position that has no original bit to shift into it. The zeros in the bit streams indicated below are there for the same reason. As stated above, other fill in methods besides putting in zeros are also within the scope of the present invention. 
   In  FIG. 40  the second from the left input of each tile  20 - 35  is selected. Selecting the second from the left input of each tile  20 - 35  shifts the 16-bit word by four bits to the left. Subsequently, the third input from the left is selected for tiles  0 - 15 . Selecting the third from the left input of each tile  0 - 15  shifts the 16-bit word by two bits to the left. Thus the net result of passing through the selected connectors is to shift the 16-bit word six bits to the left from where it had been on tiles  40 - 55 . Representing each bit as a letter, with gaps for clarity, the results of the shifts would be: 
   
     
       
         
             
             
             
           
             
                 
                 
             
           
          
             
                 
               Tiles 40-55: 
               ABCD EFGH IJKL MNPQ 
             
             
                 
               Tiles 20-35: 
               EFGH IJKL MNPQ 0000 
             
             
                 
               Tiles  0-15: 
               GHIJ KLMN PQ00 0000 
             
             
                 
                 
             
          
         
       
     
   
   In  FIG. 41  selecting the third from the left input of each tile  20 - 35  shifts the 16-bit word by eight bits to the left. Selecting the rightmost input of each tile  0 - 15  shifts the 16-bit word by three bits to the left. Thus the net result of passing through the selected connectors is to shift the 16-bit word eleven bits to the left from where it had been on tiles  40 - 55 . Representing each bit as a letter, with gaps for clarity, the results of the shifts would be: 
   
     
       
         
             
             
             
           
             
                 
                 
             
           
          
             
                 
               Tiles 40-55: 
               ABCD EFGH IJKL MNPQ 
             
             
                 
               Tiles 20-35: 
               IJKL MNPQ 0000 0000 
             
             
                 
               Tiles  0-15: 
               LMNP Q000 0000 0000 
             
             
                 
                 
             
          
         
       
     
   
   In  FIG. 42  selecting the rightmost input of each tile  20 - 35  shifts the 16-bit word by twelve bits to the left. Selecting the leftmost input of each tile  0 - 15  shifts the 16-bit word by zero bits to the left. Thus the net result of passing through the selected connectors is to shift the 16-bit word twelve bits to the left from where it had been on tiles  40 - 55 . Representing each bit as a letter, with gaps for clarity, the results of the shifts would be: 
   
     
       
         
             
             
             
           
             
                 
                 
             
           
          
             
                 
               Tiles 40-55: 
               ABCD EFGH IJKL MNPQ 
             
             
                 
               Tiles 20-35: 
               MNPQ 0000 0000 0000 
             
             
                 
               Tiles  0-15: 
               MNPQ 0000 0000 0000 
             
             
                 
                 
             
          
         
       
     
   
   By combining appropriate selections of inputs in tiles  20 - 35  and  0 - 15  the 16-bit word on tiles  40 - 55  can be shifted by any number of bits from zero to 16. It will be clear to those skilled in the art that by adding additional layers of multiplexers and parallel connections, that barrel shifting can be performed on still longer words. For example, a 64-bit wide barrel shifter can be implemented by taking four, side by side 16 bit barrel shifters, and adding another layer with connections offset by zero, sixteen, thirty-two, and forty-eight columns. The added layer could be added above, below or between the already described layers of the 16-bit barrel shifter. 
   The barrel shifter shown in the preceding figures is capable of providing shifts to the left (or a shift of zero), but it will be clear to those skilled in the art that similar barrel shifters can be created that provide shifts to the right, and barrel shifters that optionally provide shifts in either direction. One example of a barrel shifter that optionally provides shifts in either direction is illustrated in  FIG. 43 . 
   4. Alternate Embodiments of Barrel Shifters 
   The figures illustrating the previously described embodiments of barrel shifters showed the set of tiles containing the shifted word as being directly beneath the set of tiles containing the original word. The tile corresponding to the most significant bit in the shifted word was directly below the tile corresponding to the most significant bit in the original word, and so on. However, in other embodiments the set of tiles containing the shifted word may itself be offset by one or more columns, such that the tile corresponding to the most significant bit of the shifted word is no longer directly beneath the tile corresponding to the most significant bit of the original word, and so on. Thus, in some embodiments, a shift of a word within a data path may coincide with a shift of the data path itself. 
   The figures indicated above also showed the larger shift first, followed by a smaller shift. It will be clear to one of ordinary skill in the art that other embodiments may have the smaller shift first followed by the larger shift. 
   The figures illustrating the previously described embodiments also showed (among others) parallel NNOCs (12,4) that directly connected distant tiles. In some other embodiments, distant tiles may be connected by combinations of shorter sets of NNOCs, such as those shown in  FIG. 44 . This figure shows four parallel NNOCs (6,2)  4415 , connecting tile set  4410  to tile set  4420 , and four parallel NNOCs (6,3)  4425  connecting tile set  4420  to tile set  4430 . The figure shows exploded views of one tile in tile set  4410 , one tile in tile set  4420  and one tile in tile set  4430 . The connection passes through an RMUX  4440  in the exploded tile  4420   a . In some embodiments, where a barrel-shifter uses direct NNOCs for shorter connections and pairs of NNOCs (as shown in  FIG. 44 ) for longer connections, RMUXs and parallel intra-tile connections are used in the destination tiles of the shorter connections, such as those shown in  FIG. 45 . The use of such RMUXs and intra-tile connections insures that the time it takes for data to get from one layer to another is close to the same. 
   Most of the delay in passing a signal from one tile to another comes from the logic and routing circuits rather than the direct connections. Therefore adding an extra multiplexer to one data path (as shown in  FIG. 44 ) but not to another data path may result in longer delays for one path than another. In some embodiments where such disparities are to be avoided, an extra multiplexer may be placed in a path that would otherwise not need one. 
     FIG. 45  illustrates the addition of a multiplexer to a data path of some embodiments. The figure shows NNOCs (4,5)  4515  connecting tile set  4510  to tile set  4530 . The exploded view of tile  4530   a  shows that the NNOC (4,5)  4515  from tile set  4510  connects to RMUX  4540 . The exploded view also shows that the outputs of RMUX  4540  connects to IMUX  4550  through intra-tile connection  4545  (connection  4545  is repeated as a parallel intra-tile connection on each tile of tile set  4530 , but not shown in the figure). The set of connections (NNOCs  4515  and intra tile connections  4545 ) ensures that data coming from tile set  4510  passes through one RMUX before reaching an IMUX in tile set  4530 , just as the data in  FIG. 44  passed through one RMUX on its way from tile set  4410  to tile set  4430 . This is one way of ensuring that the amount of time it takes for data to reach tile set  4530  is very close to the same as it takes data to reach tile set  4430  whether the data originates with tile set  4410  or tile set  4510 . 
   K. Memory Ports 
   Reconfigurable ICs are one type of configurable ICs. Specifically, reconfigurable ICs are configurable ICs that can reconfigure during runtime.  FIG. 46  conceptually illustrates an example of a subcycle reconfigurable IC (i.e., an IC that is reconfigurable on a subcycle basis). In this example, the subcycle reconfigurable IC implements a user design  4605  that operates at a clock speed of X MHz. Typically, an IC design is initially specified in a hardware description language (HDL), and a synthesis operation is used to convert this HDL representation into a circuit representation. After the synthesis operation, the IC design includes numerous electronic circuits, which are referred to below as “components.” As further illustrated in  FIG. 46 , the operations performed by the components in the IC design  4605  can be partitioned into four sets of operations  4610 - 4625 , with each set of operations being performed at a clock speed of X MHz. 
     FIG. 46  then illustrates that these four sets of operations  4610 - 4625  can be performed by one subcycle reconfigurable IC  4630  that operates at 4X MHz. In some embodiments, four cycles of the 4X MHz clock correspond to four subcycles within a cycle of the X MHz clock. Accordingly, this figure illustrates the reconfigurable IC  4630  reconfiguring four times during four cycles of the 4X MHz clock (i.e., during four subcycles of the X MHz clock). During each of these reconfigurations (i.e., during each subcycle), the reconfigurable IC  4630  performs one of the identified four sets of operations. In other words, the faster operational speed of the reconfigurable IC  4630  allows this IC to reconfigure four times during each cycle of the X MHz clock, in order to perform the four sets of operations sequentially at a 4X MHz rate instead of performing the four sets of operations in parallel at an X MHz rate. Other embodiments perform even faster, with more subcycles per user cycle. 
   One possible operation during a subcycle is accessing memory on the IC. Typically, electronic memory is stored in memory circuits as binary data. Data is put into the memory circuits as “words” of data of a set length, dependent on the design of the memory circuits. The length of the words is referred to as the “width” of the memory. An example of a memory width is 16-bits. Each word of data is stored at a particular memory address. A memory address is an n-bit binary number. The total number of memory addresses in a piece of memory is 2 n . The number of memory addresses in a piece of memory is referred to as the “depth” of the memory. Accordingly, such memory is 2 n -bits “deep”. 
   Typically, memory is much deeper than it is wide. For example, a block of memory could have words 16-bits long and 1024 memory locations (2 10 ) to store the words in. Such a memory would be 16-bits wide and 1024-bits deep. 
   Memory is accessed by use of memory ports. A memory port for a block of memory allows memory words to be written to or read from the memory, once per time unit. Some memory ports are read/write memory ports that handle both read and write operations.  FIG. 47  is a representation of a physical memory port. The memory  4750  has a single memory port. The port has (1) data input lines  4710  (represented by one line) to write data to the memory, (2) memory address input lines  4720  (represented by one line) to specify the address to be accessed, (3) a read/write input line  4730  to specify whether to read to or write from the memory, (4) a clock input  4740 , and (5) a data out line  4760  to read data from the memory. 
   1. Multiple Logical Memory Ports 
   In some embodiments, memory can be accessed every subcycle. Because this can be done in a subcycle, the memory can be accessed as many times per user cycle as there are subcycles per user cycle. For example, an embodiment with 4 subcycles per user cycle can access the memory 4 times per user cycle. 
   In some embodiments, multiple accesses per user cycle are presented to the user as multiple logical memory ports. Though the memory may have only one physical port, the repeated accesses manifest as independent logical memory ports, all accessing the same memory address in the same user cycle. Each logical port corresponds to a single physical port, plus a subcycle time slot. 
   It should be noted that in some embodiments, the user might perceive each logical memory port of a memory of the reconfigurable IC as an actual physical memory port of a memory in the user design. Irrespective of whether the user perceives multiple logical memory ports or multiple physical memory ports, the user specifies a design that includes a memory that has multiple memory ports. The software tool provided by some embodiments takes the user&#39;s design and maps accesses to a user-design memory through multiple ports during one user design cycle to multiple subcycle accesses to a memory in subcycle reconfigurable IC. 
     FIG. 48  illustrates memory access from the physical point of view of the reconfigurable IC and the effective memory access as seen by the user&#39;s design. The user&#39;s design can operate as though there are four ports, all four accessible in one clock cycle. These four ports are referred to as logical ports as they do not correspond to four physical ports in the reconfigurable IC. The reconfigurable IC operates as though there is one port, accessible once per subcycle. Data-in lines  4810   a - d  correspond to data-in line  4810  during each of four clock subcycles, data-out lines  4860   a - d  correspond to data-out line  4810  during each of four clock cycles. Memory address inputs  4820   a - d  correspond to memory address  4820  during each of four clock subcycles. Read/write command inputs  4830   a - d  correspond to read/write command input  4830  during each of four clock subcycles. Clock input  4840  receives the clock signals at the frequency used by the reconfigurable IC; clock input  4840   a  receives the clock signals at the frequency used by the user&#39;s design. The clock signals used by the reconfigurable IC are four times the frequency of the clock signals used by the user design. The memory  4850  accessed by the physical ports and the memory  4855  accessed by the logical ports correspond to each other. In some embodiments they are physically the same. In some embodiments they may be construed as different from each other. 
     FIG. 48  illustrates that the memories receive clock signals that operate at user design cycle rate and at a subcycle rate. One of ordinary skill will realize that these presentations merely conceptually illustrate the effective operational speeds of the memories in the user design and in the reconfigurable IC. To get these memories to operate at these rates, they might receive one or more other clock signals that specify that they operate at the user design cycle rate or at the subcycle rate. 
     FIG. 49  illustrates the operation of multiple memory accesses, from the point of view of the IC and the point of view of the user, for a four subcycle per user cycle IC.  FIG. 49  illustrates the mapping of two read operations through two logical ports of a memory in the user design to two read operations through one physical port of a memory in the reconfigurable IC during the first two subcycles. This figure also illustrates the mapping of two write operations through two logical ports of the memory in the user design to two write operations through the physical port of the memory in the reconfigurable IC during the last two subcycles. In the figure, two read operations and two write operations are performed, however, any combination of read and write operations can be performed. 
   2. Narrowing Memory 
   In some cases, the user&#39;s requirements for the way the IC memory is arranged may be different from the physical memory arrangement on the IC. Some embodiments use a barrel shifter to present the memory on the configurable IC to the user as being narrower and deeper than it actually is. In the example illustrated in  FIG. 50  the actual memory  5010  uses 16-bit words and is 32 memory addresses deep (using 5 bits to provide 2 5 =32 memory addresses). Note that the use of the letter Z for memory location “31” does not indicate that there are only 26 words in the memory. These embodiments can present the memory to the user as being a memory arrangement 5020 2-bits wide and 256 memory addresses deep (using 8 bits to provide 28=256 memory addresses). 
   In this example, the configurable IC receives from the user a read command for a 2-bit word with 8-address bits. This includes 5-bits that tell the configurable IC what the actual memory location is, and 3-bits that tell the configurable IC which part of the 16-bit word at that memory location is required. Memory  5010  includes a 16-bit word  5030  at binary memory location “00000”. If the user&#39;s design wants to read a 2-bit word such as the one at memory location  5040  it would provide the binary address “00000 100” (note, that the space is for clarity, not a required part of these embodiments) to the configurable IC. 
     FIG. 51  illustrates an example of the process of extracting the specified 2-bit word from the actual memory. In  5110 , the configurable IC receives the address from the user&#39;s design. In  5120 , the configurable IC uses the first 5-bits, “00000”, to find and read word  5030  out of the configurable IC memory. In  5130 , the word is shifted to the right using a barrel shifter. The length of the shift is determined by the width of the word (2 bits) the user&#39;s memory arrangement uses and the last 3-bits of the provided 8-bit binary address. 
   The number of bits that the word is shifted by is equal to the product of the width of the word the user&#39;s design seeks, times the value of the last 3-bits of the user provided address. In binary, “100” means “4”, and the width of the word the user seeks is 2-bits, so the word  5030  is shifted 8-bits to the right. In  5140  the configurable IC passes only the final two bits A 9 A 8  on to the user&#39;s design. As seen in  FIG. 50 , this is the word found in memory address  5040 , which is what the design was trying to read. 
     FIG. 52  illustrates use of a barrel shifter to narrow the memory of some embodiments. A simplified barrel shifter  5210  is shown in the figure. In some embodiments this barrel shifter may be the type illustrated earlier in this specification, in other embodiments it may be a variation of that type of barrel shifter or some other type of barrel shifter entirely. 
   The barrel shifter takes as its input the word selected by the first five bits of the 8-bit memory address. In this example, the 8-bit address was “00000100” (as indicated in  FIG. 51 ). The first five bits are “00000”, which is an address in the physical memory that holds the word “A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 ”. 
   The barrel shifter  5210  shifts the word by the required number of bits. The size of the required shift depends on the width of the narrowed memory and the number indicated by the last part of the address. The number of bits in the last part of the address is dependent on the ratio of the width of the words in the physical memory to the width of the words in the narrowed memory. In this example, the width of the physical memory is sixteen bits and the width of the narrowed memory is two bits, so the ratio is eight-to-one. Each 16-bit word in the physical memory contains eight 2-bit words. Therefore to specify any particular 2 bit word within a particular 16-bit word requires a number between zero and seven. When shifting to get to the specified 2-bit word, the shifts must be in multiples of two. A shift of zero provides the first narrow word, a shift of two (2=2*1) provides the second narrow word, a shift of four (4=2*2) provides the third narrow word, and so on. 
   Expressing numbers from zero to seven in binary requires three bits. In this example, the 3-bit binary number is “100”. In binary, “100” means four. Thus the shift here must be eight (8=2*4). In this illustration, the shift is eight bits to the right. The barrel shifter then passes the two least significant bits out of outputs  5220  to another set of tiles  5230 . The amount of the shift, here, by 8 bits determines what bits show up at the set of tiles  5230 . 
   In some embodiments, as mentioned previously the top tiles shown in the barrel shifter may be replaced with the physical memory itself, with the outputs of the memory taking the place of the outputs of the tiles. This would reduce the number of connections necessary to perform such memory shifts. In some embodiments (with or without such reduced connection sets) memory narrowing may be performed in a single user cycle. 
   L. Memory Port Hierarchies 
   1. Overview 
   As described previously, some embodiments provide multiple memory ports for accessing one digital memory on the configurable IC. As indicated in the background section, problems arise when two or more ports are trying to access the same memory location at the same time. For example, without some way of deciding which memory port has priority over the other(s), there is no way to decide which memory port will have its word written to the memory address when more than one port is trying to write to that address during the same clock domain. Another example is that without some specified priority, there is no way to decide whether a port that is reading a memory address will read the data written to that address by the other port, or will read the data as it was before the other port wrote to that address. Some embodiments that deal with these issues are described below. 
   In some embodiments the configurable IC has multiple physical memory ports for one memory. In other embodiments the configurable IC may have one physical memory port for one memory and have multiple memory ports in the user design, either implemented as described in the previous section or otherwise. 
   2. Behavioral Descriptions 
   Some embodiments provide a user with a set of behavioral descriptions that specify the results of multiple accesses to the same memory address by multiple ports. This enables the user to predict the results of setting particular priority levels for different ports. For purposes of illustration,  FIG. 53  illustrates a conceptual diagram of an example of a memory with two ports and Table 1 provides a set of behavioral descriptions that specify the results of accesses to the memory port. The memory illustrated in  FIG. 53  has two ports, port A and port B. Port A has a set of data inputs  5310 , a set of memory address inputs  5320 , a read command input  5330 , a write command input  5340 , and a set of data outputs  5350 . Port B has a set of data inputs  5311 , a set of memory address inputs  5321 , a read command input  5331 , a write command input  5341 , and a set of data outputs  5351 . In the illustrated embodiment, the two ports share a common clock input  5360 , other embodiments may have a separate clock input for each port. 
   In some embodiments, the behavioral descriptions may include a truth table such as Table 1 below. Other embodiments may use different truth tables, or provide the behavioral description in ways that are not truth tables. The table shows what happens, in some embodiments, under the assumption that two ports are able to access the same memory during the same clock domain. It assumes that each port is trying to access the same memory address as the other. In other words the memory address coming in on port A&#39;s memory address inputs  5320  is the same as the memory address coming in on port B&#39;s memory address inputs  5321 . In cases where those assumptions do not hold there is no conflict between the ports. 
   Given that set of assumptions, the table takes a set of independent variables and describes the results of each possible combination of those variables. In Table 1 the independent variables are: 1) the relative priority levels of the ports, represented in the table by the column headed m,n; 2) the state of port A&#39;s write command input  5340 , represented in the table by the column headed WRTA; 3) the state of port B&#39;s write command input  5341 , represented in the table by WRTB; 4) the state of port A&#39;s read command input  5330 , represented in the table by the column headed RDA; and 5) the state of port B&#39;s read command input  5331 , represented in the table by the column headed RDB. In Table 2 the dependent variables are: 1) the state of the memory address that the ports are trying to access (if any access is happening at all) as of the end of the user cycle; 2) the output on port A&#39;s data outputs; and 3) the output on port B&#39;s data outputs. 
   3. Detailed Description of Example Table 
   In the table, the relative priority levels of the ports are represented by a relationship between m and n. The priority level of port A is represented by m and the priority level of port B is represented by n. The relative priority levels of ports affect which port will have its word written to the memory address first when more than one port is trying to write to that address during the same user design clock cycle. 
   When port A has a higher priority than port B, that condition is represented in the table by “m&gt;n” similarly, when port A has a lower priority level than port B or an equal priority level those conditions are represented by “m&lt;n” and “m=n” respectively. Some combinations of independent variables make the relative priorities of the ports irrelevant to the determination of the dependent variables. For example, in situations represented by rows in which no port is writing to the memory, there can be no conflict. Where the relative priorities do not affect any dependent variables an “X” is used in the “m,n” column. 
   The values in the “WRTA” and “WRTB” columns indicate the signal coming in on the write command inputs  5340  and  5341 , respectively, and thus whether the port will be written using port A and/or port B. A “1” in one of these columns indicates that the corresponding port will be used in the current cycle to write data to the selected address in the memory. A “0” in one of these columns indicates that the corresponding port will not be used in the current cycle to write data to the corresponding port. 
   The values in the “RDA” and “RDB” columns indicate the signal coming in on the read command inputs  5330  and  5331 , respectively, and thus whether the port will be read using port A and/or port B. A “1” in one of these columns indicates that the corresponding port will be used in the current cycle to read data from the selected address in the memory. A “0” in one of these columns indicates that the corresponding port will not be used in the current cycle to read data from the corresponding port. 
   The “MEM” column indicates the value that will be in the selected memory address at the end of the current cycle. A “HOLD” in this column indicates that the memory address will retain the value that it had at the beginning of the cycle. A “DINA” in the column indicates that the value at the end of the cycle will be the same as the data being written through port A. A “DINB” in the column indicates that the value at the end of the cycle will be the same as the data being written through port B. An “ERR” stands for “error”. An “ERR” in the column means that the value at the end of the cycle is indeterminate. Note that within the table, these errors only occur in rows where 1) both ports are written to, and 2) the priorities set for the ports are equal. In some embodiments these rows serve as a warning to the user to not allow the set of independent variables to have those combinations of values. 
   The “Output on A” and “Output on B” columns indicate what values will be read from the data outputs  5350  and  5351  respectively. A “HOLD” indicates that the memory is not being read through the particular port in that cycle, “HOLDs” correspond to the particular port receiving a “do not read” signal on its read command input. In some embodiments, “HOLD” may mean that the output lines are outputting zeros. In other embodiments “HOLD” may mean that the outputs maintain the values they had from the previous cycle. In other embodiments, “HOLD” may mean the outputs are allowed to float or that they have some other method of determining the output. 
   A “MEM[ADDR]” in these columns indicates that the output is the value that was previously stored in the specified memory address, before the current cycle. A “DINA” indicates that the value of the outputs is the value that is being written on port A. A “DINB” indicates that the value of the outputs is the value that is being written on port B. 
   
     
       
         
             
             
             
             
             
             
             
             
           
             
                 
             
             
               m,n 
               WRTA 
               WRTB 
               RDA 
               RDB 
               MEM 
               Output on A 
               Output on B 
             
             
                 
             
           
          
             
               X 
               0 
               0 
               0 
               0 
               HOLD 
               HOLD 
               HOLD 
             
             
               X 
               0 
               0 
               0 
               1 
               HOLD 
               HOLD 
               MEM[ADDR] 
             
             
               X 
               0 
               0 
               1 
               0 
               HOLD 
               MEM[ADDR] 
               HOLD 
             
             
               X 
               0 
               0 
               1 
               1 
               HOLD 
               MEM[ADDR] 
               MEM[ADDR] 
             
             
               X 
               0 
               1 
               0 
               0 
               DINB 
               HOLD 
               HOLD 
             
             
               X 
               0 
               1 
               0 
               1 
               DINB 
               HOLD 
               DINB 
             
             
               m&gt;n 
               0 
               1 
               1 
               0 
               DINB 
               DINB 
               HOLD 
             
             
               m&lt;n 
               0 
               1 
               1 
               0 
               DINB 
               MEM[ADDR] 
               HOLD 
             
             
               m=n 
               0 
               1 
               1 
               0 
               DINB 
               DINB 
               HOLD 
             
             
               m&gt;n 
               0 
               1 
               1 
               1 
               DINB 
               DINB 
               DINB 
             
             
               m&lt;n 
               0 
               1 
               1 
               1 
               DINB 
               MEM[ADDR] 
               DINB 
             
             
               m=n 
               0 
               1 
               1 
               1 
               DINB 
               DINB 
               DINB 
             
             
               X 
               1 
               0 
               0 
               0 
               DINA 
               HOLD 
               HOLD 
             
             
               m&gt;n 
               1 
               0 
               0 
               1 
               DINA 
               HOLD 
               MEM[ADDR] 
             
             
               m&lt;n 
               1 
               0 
               0 
               1 
               DINA 
               HOLD 
               DINA 
             
             
               m=n 
               1 
               0 
               0 
               1 
               DINA 
               HOLD 
               DINA 
             
             
               X 
               1 
               0 
               1 
               0 
               DINA 
               DINA 
               HOLD 
             
             
               m&gt;n 
               1 
               0 
               1 
               1 
               DINA 
               DINA 
               MEM[ADDR] 
             
             
               m&lt;n 
               1 
               0 
               1 
               1 
               DINA 
               DINA 
               DINA 
             
             
               m=n 
               1 
               0 
               1 
               1 
               DINA 
               DINA 
               DINA 
             
             
               m&gt;n 
               1 
               1 
               0 
               0 
               DINA 
               HOLD 
               HOLD 
             
             
               m&lt;n 
               1 
               1 
               0 
               0 
               DINB 
               HOLD 
               HOLD 
             
             
               m=n 
               1 
               1 
               0 
               0 
               ERR 
               HOLD 
               HOLD 
             
             
               m&gt;n 
               1 
               1 
               0 
               1 
               DINA 
               HOLD 
               DINB 
             
             
               m&lt;n 
               1 
               1 
               0 
               1 
               DINB 
               HOLD 
               DINB 
             
             
               m=n 
               1 
               1 
               0 
               1 
               ERR 
               HOLD 
               ERR 
             
             
               m&gt;n 
               1 
               1 
               1 
               0 
               DINA 
               DINA 
               HOLD 
             
             
               m&lt;n 
               1 
               1 
               1 
               0 
               DINB 
               DINA 
               HOLD 
             
             
               m=n 
               1 
               1 
               1 
               0 
               ERR 
               ERR 
               HOLD 
             
             
               m&gt;n 
               1 
               1 
               1 
               1 
               DINA 
               DINA 
               DINB 
             
             
               m&lt;n 
               1 
               1 
               1 
               1 
               DINB 
               DINA 
               DINB 
             
             
               m=n 
               1 
               1 
               1 
               1 
               ERR 
               ERR 
               ERR 
             
             
                 
             
          
         
       
     
   
   Table 1 shows the outcomes of many different sets of input options. For example, when only one port is set to write, the value in the memory at the end of the cycle is the value written using that port. The table also shows that the ports have what is called “writethrough” in embodiments represented by the table. Writethrough means that when a port performs both a read and a write operation in the same clock domain, the value read by the port at the output is the same as the value written by the port at the input. 
   Table 1 also shows that for some combinations of inputs, the results of reading and writing through multiple ports may be counter-intuitive. For example when the higher priority port writes and the lower priority port does not, the value stored in the memory at the end of the user cycle is the value written by the higher priority port. However, if the lower priority port reads during the same user cycle it reads the value that was already in the memory before the user cycle began. This is in contrast with the results when the lower priority port writes and the higher priority port does not. In that case, the value stored in the memory at the end of the clock cycle is the value written by the lower priority port. If the higher priority port reads during the same user cycle it reads the value written by the lower priority port. In other words, the lower priority port does not “see” writes made to the memory by the higher priority port during the same user cycle, but the higher priority port does “see” writes made by the lower priority port during the same user cycle, so long as the higher priority port is not also writing. 
   4. Alternate Embodiments of Port Hierarchies 
   Some embodiments use this type of hierarchy to provide the user with a description that matches a configurable IC that uses subcycles to provide multiple ports. It will be clear to one of ordinary skill in the art that hierarchies for configurable ICs that implement multiple-ports without using subcycles are also within the scope of the present invention. 
   Table 1 is the truth table for a two-port memory, it will be clear to one of ordinary skill in the art that truth tables detailing a memory-port hierarchy for memories with four, eight, sixteen, or any other number of ports could be provided. The number of bits used in each word could be four, eight, ten, eighteen or any other number. 
   The embodiments described by Table 1 uses separate write and read command signals. Other embodiments use alternative sets of command signals. For example, some embodiments use a single input that determines whether the port will read or write in one clock domain. Some embodiments read whole words from the memory, but write half words to the memory. Each port of such embodiments would have an input to command the port to read a whole word, an input to command the port to write the most significant half of the bits of a word, and a second input to command the port to write the least significant half of the bits of the a word. Some embodiments have ports operating in different clock domains to minimize the number of potential conflicts. 
   5. Alternate Embodiments of Port Hierarchies 
   Some integrated circuits have multiple blocks of memory circuits (sometimes referred to as “memory blocks”). Instead of using one large block of physical memory circuits in one location in the integrated circuit, the circuits have more than one block of physical memory circuits on the integrated circuit. This may be done to put memory blocks close to the circuits that need the information stored in those memory blocks, or because no single location in the IC was available for a large memory, or for some other reason.  FIG. 54  illustrates an integrated circuit design with four separate physical memory blocks. The figure includes a physical integrated circuit  5400 , with memory blocks  5411 - 5414 . All other circuit elements are omitted for clarity. Memory blocks  5411 - 5414  are placed in assorted physical locations within the circuit and are of assorted sizes. The positioning and sizes of the memory blocks are intended to illustrate that different memories blocks within an integrated circuit are not necessarily the same size or positioned in an obvious pattern. 
   In an integrated circuit with several physically independent memory blocks, the separate memory blocks tend to have separate circuits for accessing each memory block. Each memory block has its own port or ports.  FIG. 55  provides a simplified illustration of separate inputs and outputs of four memory blocks  5511 - 5514 . 
   In a configurable IC, there may be one large physical memory block in place of several smaller memory blocks. If a large memory block has at least as much storage capacity as the total of multiple memory blocks in a user design circuit, then each smaller memory block in the user design can be assigned its own section of the storage capacity of the large memory block. So a large memory block in a configurable IC can be used to replace the storage capacity of several small blocks.  FIG. 56  illustrates this conceptually. User design memory blocks  5611  to  5614  represent memory capacities demanded for various locations in the user design circuit. In the figure, the individual memory capacities are proportional to the size of the memory blocks. The user design memory blocks  5611  to  5614  can each be mapped to a set of memory locations within a physical memory block  5600 . With each user design memory block assigned to a different, non-overlapping, set of memory locations in the physical memory block  5600 , a process or program that accesses one of the blocks can do so without overwriting a physical memory location assigned to another user design memory block. 
   The user design in this example was created under the assumption that the memory blocks, being physically separate, each had separate access ports. Given that assumption, a program or process designed to access the individual user design memory blocks would have no reason to wait for an access of one memory block to be complete before trying to access another. Some programs and processes are designed with the assumption that the user design memory blocks are separate entities within an IC. Such programs or processes could try to access multiple user design memory blocks within the same user cycle. Attempting multiple accesses during one clock cycle would normally cause errors, unless there were either multiple physical ports or multiple virtual ports implemented using subcycles. 
   Some embodiments of the present invention use subcycles to provide multiple user design ports though there may be as few as one physical port on the large physical memory block.  FIG. 48 , as described above illustrates the physical ports of the physical memory and the user design ports operating on a subcycle basis. The combination of using a larger memory and using multiple user design memory ports to access that memory allows a configurable IC to accurately provide the same apparent environment that the user design describes, with no overlap in memory space or access times. 
     FIG. 57  illustrates a flowchart of some embodiments of this method. At  5710 , a user design is received. At  5720 , multiple user design memories in the user design are mapped to memory locations (sets of memory addresses) within a physical memory of a configurable IC. At  5730 , the memory access ports of the user design memory blocks are each mapped to a particular subcycle and memory port of a physical memory on the configurable IC. 
   In some embodiments, the user design is set up under the assumption that multiple events occur within one user cycle, as for example in an IC with asynchronous memory where, for example, data bits can be read from a memory, added to other data bits, and sent into a register within the same user cycle. In such embodiments, it may be necessary to determine how many subcycles are needed before or after a given block or user design memory is accessed in order to assign data access for a particular user design memory block to an appropriate subcycle. Selecting an appropriate subcycle for actions that need to be performed after a memory access would mean setting the user design memory to use a subcycle early enough to do any needed operations in later subcycles within the same user cycle. Selecting an appropriate subcycle for actions that need to be performed before a memory access would mean setting the user design memory to use a subcycle late enough to do any needed operations in earlier subcycles within the same user cycle. The following description mentions embodiments that use a particular code language to describe the user design; however it will be clear to one of ordinary skill in the art that other embodiments could just as easily use some other encoding system while still allowing the analysis as described. 
   In some embodiments, the user design is expressed in register transfer level code (RTL code). In such embodiments, the RTL code can be analyzed in relation to each user design memory block to determine the maximum number of possible operations that could potentially take place (within a user cycle) before a memory access of that user design memory block and the maximum number of operations that could possibly take place after a memory access of that user design memory block. Given a set of such numbers of operations, it would be possible to determine an assignment of subcycle number for accessing each memory block. 
     FIG. 58  illustrates a flowchart of some embodiments for mapping user design memory ports to subcycles when there are possible operations during a given user design clock cycle, but before or after accessing user design memory blocks. At  5810 , a user design memory block is selected. At  5820  and  5830 , the maximum possible number of operations before and after (respectively) a user design memory block access are determined from the user design. At  5840 , if there are remaining user design memory blocks to be evaluated, the flowchart repeats from  5810 . If there are no remaining user design memory blocks to be evaluated, then a set of subcycle assignments are made that accounts for the needs of each user design memory block. 
   For example, in accessing four user design memory blocks, A-D, if memory block A could have as many as two operations before it, then accesses to memory block A cannot be assigned to a subcycle earlier than the third subcycle of the user cycle. Assigning accesses of memory block A to the third subcycle would ensure two user cycles in which to perform the two operations before accessing memory block A. It should be noted that in actual operation, the combination of factors that would cause two operations to happen before an access of memory block A might never occur. The assignment of accesses of memory block A to the third subcycle must account for the worst case scenario, in this case, two possible preceding operations. 
   Similar determinations can be made for operations before and after each of the other blocks. However, in some scenarios, there may be no combination of assignments that will satisfy the worst case scenario for all memory blocks. For example, in an embodiment with eight subcycles per user cycle, if four separate user design memory blocks could each have five operations before a memory access in the same user cycle, then the earliest subcycle assigned for accessing a memory block would be the sixth subcycle. This would leave only three open subcycles (sixth, seventh and eighth) to accommodate four memory blocks. In such a scenario either the user design must be redesigned, or (for this example, and in some embodiments) the memory block least likely to have five operations occur before it is assigned to the fourth subcycle. 
   In some embodiments, if it can be proven that two user design memory blocks are never accessed in the same user cycle for a particular user design, then accesses of those two blocks could safely be assigned to the same subcycle. For example two memory blocks could both use the fifth subcycle, so long as they would never have to use it in the same user cycle. In such a case, this would solve the conflict described above. In other embodiments, multiple physical ports would allow multiple accesses to the physical memory in each subcycle. 
   While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Thus, one of ordinary skill in the art would understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.