Patent Publication Number: US-11378598-B2

Title: Semiconductor integrated circuit device and current detection circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-37780, filed on Mar. 5, 2020; the entire contents of which are incorporated herein by reference. 
     FIELD 
     The present embodiment generally relates to a semiconductor integrated circuit device and a current detection circuit. 
     BACKGROUND 
     A current detection circuit has conventionally been disclosed where a voltage drop that is generated by a current that flows through a load and a voltage drop that is generated by a minute current with a predetermined ratio to a load current are compared by a differential amplifier and a current that flows through a switching element that cooperates with the differential amplifier to compose a negative feedback circuit is detected. A voltage drop is generated by, for example, an external resistance element for a semiconductor integrated circuit device where a differential amplifier is formed therein. A resistance value of an external resistance element is provided with a high degree of accuracy, so that it is possible to improve an accuracy of current detection. However, a resistance element with a high degree of accuracy and a low resistance value is expensive. A needed accuracy of current detection is different according to a field of application where a current detection circuit is used therein. A semiconductor integrated circuit device and a current detection circuit are desired that are applicable to any of needs of a high accuracy and a low accuracy and capable of suppressing costs thereof. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING(S) 
         FIG. 1  is a diagram that illustrates a configuration of a current detection circuit according to a first embodiment. 
         FIG. 2  is a diagram that illustrates a configuration of a current detection circuit according to a second embodiment. 
         FIG. 3  is a diagram that illustrates a configuration of a current detection circuit according to a third embodiment. 
         FIG. 4  is a diagram that illustrates a configuration of a current detection circuit according to a fourth embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     According to one embodiment, a semiconductor integrated circuit device includes a first switching element that is provided with a main current path that is connected between a first node and a second node, and outputs a first output current, a second switching element that is provided with a main current path that is connected between the first node and a third node, and outputs a second output current that is one K-th times as much as the first output current (where K is any positive number that is greater than 1), a third switching element that is provided with a main current path that is connected between a fourth node and a fifth node, and a differential amplifier that outputs a signal provided by amplifying a voltage difference that is generated between the third node and the fourth node to control a conduction state of the third switching element. 
     Hereinafter, a semiconductor integrated circuit device and a current detection circuit according to embodiments will be explained in detail, with reference to the accompanying drawings. Additionally, the present invention is not limited by such an embodiment(s) 
     First Embodiment 
       FIG. 1  is a diagram that illustrates a configuration of a current detection circuit according to a first embodiment. A current detection circuit according to the present embodiment detects a current that flows thorough a load that is connected between a power source and ground. A current detection circuit in  FIG. 1  includes a semiconductor integrated circuit device  10 . The semiconductor integrated circuit device  10  is integrally integrated on, for example, a (non-illustrated) printed-wiring board. The semiconductor integrated circuit device  10  has a node N 1  to a node N 5  that are connected to an external element or the like. Each node N 1  to N 5  is a connection terminal, for example, a (non-illustrated) bonding pad. Alternatively, each node N 1  to N 5  represents a connection point of wirings. One end of a load  30  is connected to the node N 1 . The other end of the load  30  is grounded.  FIG. 1  illustrates a configuration in a case where the load  30  is connected to the semiconductor integrated circuit device  10  on a lower potential side thereof. 
     The semiconductor integrated circuit device  10  has PMOS transistors MP 1  and MP 2 . A source-drain path of the transistor MP 1  that is a main current path thereof is connected between the nodes N 1  and N 2 . A source-drain path of the transistor MP 2  is connected between the node N 1  and the node N 3 . A ratio of output currents that are output by the transistors MP 1  and MP 2 , that is, a ratio of drain currents thereof, is set at K:1. It is possible to set a ratio of output currents by providing a ratio of sizes of the transistors MP 1  and MP 2  as K:1. For example, a value of K is set at 10000. 
     The semiconductor integrated circuit device  10  has a differential amplifier A 1  and a PMOS transistor SP 1 . 
     A non-inverting input end (+) of the differential amplifier A 1  is connected to the node N 3  and an inverting input end (−) thereof is connected to the node N 4 . A source-drain path of the PMOS transistor SP 1  that is a main current path thereof is connected between the nodes N 4  and N 5 . The differential amplifier A 1  amplifies a voltage difference between the nodes N 3  and N 4  and supplies it to a gate of the transistor SP 1 . An output of the differential amplifier A 1  controls a conduction state of the transistor SP 1 . The differential amplifier A 1  and the transistor SP 1  compose a negative feedback circuit that is operated in such a manner that voltages at the node N 3  and the node N 4  are equalized. 
     The nodes N 2  and N 3  are connected to one end of a detection resistor Rs 1 . The other end of the detection resistor Rs 1  is connected to a power source terminal  20  where a power source voltage VB is applied thereto. The detection resistor Rs 1  is set at, for example, a resistance value of several mΩ to several hundred mΩ. The node N 4  is connected to one end of a detection resistor Rs 2 . The other end of the detection resistor Rs 2  is connected to the power source terminal  20 . The detection resistor Rs 2  is set at a resistance value that is K times as much as that of the detection resistor Rs 1 . 
     That is, a negative feedback circuit that is composed of the differential amplifier A 1  and the transistor SP 1  is operated in such a manner that a voltage drop that is generated at the detection resistor Rs 1  and a voltage drop that is generated at the detection resistor Rs 2  are equalized. Therefore, in a case where a resistance value of the detection resistor Rs 2  is K times as much as a resistance value of the detection resistor Rs 1 , a load current IL flows through the detection resistor Rs 1  and a current IL/K flows through the detection resistor Rs 2 . 
     A current that flows through the detection resistor Rs 2  is output from the node N 5  through the transistor SP 1  and is supplied to one end of a monitor resistor Rm 1 . The other end of the monitor resistor Rm 1  is grounded. A current that flows through the monitor resistor Rm 1  is nearly equal to a current that flows through the detection resistor Rs 2 . Therefore, it is possible to detect a voltage drop that is generated at the monitor resistor Rm 1  by detecting a voltage at the node N 5 , and hence, it is possible to detect a load current IL. 
     A voltage at the node N 5  is supplied to a control circuit  11 . The control circuit  11  controls on/off of the transistors MP 1 , MP 2 . As the transistors MP 1 , MP 2  are turned on, a load current IL is supplied to the load  30 . For example, in a case where a voltage at the node N 5  rises through a predetermined threshold value, the control circuit  11  executes control to turn off the transistors MP 1 , MP 2 . By such control, it is possible to protect the load  30  from an overcurrent state thereof. 
     According to a first embodiment, the detection resistors Rs 1  and Rs 2  are respectively connected between the node N 2  of the semiconductor integrated circuit device  10  and the power source terminal  20  and between the node N 4  thereof and the power source terminal  20 . The detection resistor Rs 2  is set at a resistance value that is K times as much as that of the detection resistor Rs 1 , so that it is possible to compose a current detection circuit that detects a current that is 1/K times as much as a load current IL. The differential amplifier A 1  and the transistor SP 1  execute a negative feedback operation in such a manner that voltages at the node N 3  and the node N 4  are equalized. Voltages at the nodes N 3 , N 4  depend on the detection resistors Rs 1  and Rs 2 . Therefore, the detection resistor Rs 1  with a high degree of accuracy where a tolerance is ± several % is connected thereto, so that it is possible to provide a current detection circuit with a high degree of accuracy. Additionally, a recommended resistance element (the detection resistor Rs 1 , Rs 2 ) is provided to a user of the semiconductor integrated circuit device  10  as a standard specification, so that selection of a resistance element that is used at a time when such a user composes a current detection circuit with a high degree of accuracy by using the semiconductor integrated circuit device  10  is facilitated and hence it is possible to attain convenience of such a user. Furthermore, a current IL/K flows through the detection resistor Rs 2 . Therefore, even if a resistance value of the detection resistor Rs 2  is increased, a square of suppression of a current value contributes to power consumption at the detection resistor Rs 2 , and hence, it is possible to suppress an increase in power consumption greatly. 
     Second Embodiment 
       FIG. 2  is a diagram that illustrates a configuration of a current detection circuit according to a second embodiment. A component that corresponds to that of an embodiment as already described is provided with an identical sign and a duplicative description is provided only in a case of need. Hereinafter, the same applies. A current detection circuit in  FIG. 2  has a connection means Rp 1  that connects a node N 2  to a power source terminal  20 . The connection means Rp 1  is, for example, a wiring or a bonding wire that connects a source of a transistor MP 1  to the power source terminal  20  on a (non-illustrated) printed-wiring board. The connection means Rp 1  has, for example, a resistance value that is provided by a wiring, and is conveniently illustrated as a resistor that has a resistance value Rp 1  in the present embodiment. Additionally, the connection means Rp 1  may be configured to include a resistance element that has a predetermined resistance value. 
     A node N 3  is connected to one end of a detection resistor Rs 3 . The other end of the detection resistor Rs 3  is connected to the power source terminal  20 . The detection resistor Rs 3  is set at a resistance value that is K times as much as that of the connection means Rp 1 . A node N 4  is connected to one end of a detection resistor Rs 4 . The other end of the detection resistor Rs 4  is connected to the power source terminal  20 . The detection resistor Rs 4  is similarly set at a resistance value that is K times as much as that of the connection means Rp 1 . 
     A current ratio between transistors MP 1  and MP 2  is set at K:l. Therefore, a current IL·K/(K+ 1 ) flows through the connection means Rp 1  and a current IL/(K+ 1 ) flows through the detection resistor Rs 3 . Thereby, voltage drops at the connection means Rp 1  and the detection resistor Rs 3  are equalized, and hence, source-drain voltages and gate-source voltages of the transistors MP 1 , MP 2  are equalized respectively. Hence, it is possible to divide a load current IL into currents on the transistors MP 1  and MP 2  accurately. 
     A negative feedback circuit is composed of a differential amplifier A 1  and a transistor SP 1 . A negative feedback circuit is operated in such a manner that voltages at the node N 3  and the node N 4  are equalized. Therefore, in a case where resistance values of the detection resistor Rs 3  and the detection resistor Rs 4  are identical, a current with a value that is identical to that of a current that flows through the detection resistor Rs 3 , that is, a current IL/(K+1), flows through the detection resistor Rs 4 . A current that flows through a monitor resistor Rm 1  is nearly equal to a current that flows through the detection resistor Rs 4 . Hence, it is possible to detect a current that is 1/(K+1) times as much as a load current IL by detecting a voltage at a node N 5 . 
     According to the present embodiment, a current that flows through the detection resistor Rs 3  is suppressed so as to be 1/(K+1) times as much as a load current IL. For example, as a value of K is set at 10000, a current that is approximately 1/10000 times as much as a load current IL flows through the detection resistor Rs 3 . The connection means Rp 1  is, for example, of a resistance of a wiring, and is several mΩ to several dozen mΩ. Therefore, in a case where a value of K is 10000, it is possible to use a resistance element with approximately several dozen Ω to several hundred Ω as the detection resistor Rs 3 . The same also applies to the detection resistor Rs 4 . A resistance element with a high resistance value and a low accuracy is comparatively inexpensive. Therefore, it is possible to use a comparatively inexpensive resistance element as the detection resistor Rs 3 , Rs 4 , and hence, it is possible to suppress a cost thereof. 
     Even if resistance values of the detection resistors Rs 3 , Rs 4  are increased, a square of suppression of a current value contributes to power consumption at the detection resistors Rs 3 , Rs 4 , and hence, it is possible to suppress an increase in power consumption greatly. Furthermore, a semiconductor integrated circuit device  10  has a configuration that is identical to that of the semiconductor integrated circuit device  10  in  FIG. 1 . Therefore, it is possible for the semiconductor integrated circuit device  10  to compose a desired current detection circuit by changing connection of a resistance element or the like, and hence, volume discount that is provided by mass production is allowed. 
     Third Embodiment 
       FIG. 3  is a diagram that illustrates a configuration of a current detection circuit according to a third embodiment. A current detection circuit in  FIG. 3  represents a configuration in a case where a load  30  is connected to a semiconductor integrated circuit device  10  on a higher potential side thereof. 
     The semiconductor integrated circuit device  10  has NMOS transistors MN 1  and MN 2 . A source-drain path of the NMOS transistor MN 1  is connected between nodes N 1  and N 2 . A source-drain path of the transistor MN 2  is connected between the node N 1  and a node N 3 . A ratio of output currents that are output by the transistors MN 1  and MN 2  (a ratio of drain currents) is set at K:1. It is possible to set a ratio of output currents by providing a ratio of sizes of the transistors MN 1  and MN 2  as K:1. For example, a value of K is set at 10000. 
     The semiconductor integrated circuit device  10  has a differential amplifier A 1  and a NMOS transistor SN 1 . A non-inverting input end (+) of the differential amplifier A 1  is connected to the node N 3  and an inverting input end (−) thereof is connected to a node N 4 . A source-drain path of the transistor SN 1  is connected between nodes N 4  and N 5 . The differential amplifier A 1  amplifies a voltage difference between the nodes N 3  and N 4  and supplies it to the transistor SN 1 . An output of the differential amplifier A 1  controls a conduction state of the transistor SN 1 . The differential amplifier A 1  and the transistor SN 1  compose a negative feedback circuit that is operated in such a manner that voltages at the node N 3  and the node N 4  are equalized. 
     The node N 2  is connected to one end of a detection resistor Rs 1 . The other end of the detection resistor Rs 1  is grounded. A resistance value of the detection resistor Rs 1  is set at, for example, several mΩ to several hundred mΩ. The node N 4  is connected to one end of a detection resistor Rs 2 . The other end of the detection resistor Rs 2  is grounded. The detection resistor Rs 2  is set at a resistance value that is K times as much as that of the detection resistor Rs 1 . 
     A negative feedback circuit that is composed of the differential amplifier A 1  and the transistor SN 1  is operated in such a manner that voltage drops that are generated at the detection resistor Rs 1  and the detection resistor Rs 2  are equalized. Therefore, in a case where a resistance value of the detection resistor Rs 2  is K times as much as that of the detection resistor Rs 1 , a load current IL flows through the detection resistor Rs 1  and a current IL/K flows through the detection resistor Rs 2 . 
     The node N 5  is connected to one end of a monitor resistor Rm 1 . The other end of the monitor resistor Rm 1  is connected to a power source terminal  22  where a voltage VR is applied thereto. A voltage VR is set at, for example, a voltage value that is lower than a power source voltage VB. A power source voltage VB is set at a high voltage of approximately 40 V in a case where the load  30  is, for example, a motor. A voltage VR is provided as a low voltage of approximately 5 V that is needed to operate the differential amplifier A 1 , so that it is possible to provide a configuration to suppress power consumption. 
     As the transistor SN 1  is turned on, a current that is nearly equal to a current that flows through the detection resistor Rs 2  is supplied to the monitor resistor Rm 1 . A current that flows through the detection resistor Rs 2  is proportional to a load current IL, and hence, it is possible to detect a voltage drop that is generated at the monitor resistor Rm 1  by detecting a voltage at the node N 5 . That is, it is possible to detect a load current IL by monitoring a voltage at the node N 5 . 
     A voltage at the node N 5  is supplied to a control circuit  11 . The control circuit  11  controls on/off of the transistors MN 1 , MN 2 . As the transistors MN 1 , MN 2  are turned on, a load current IL is supplied to the load  30 . For example, in a case where a voltage at the node N 5  falls through a predetermined threshold value, the control circuit  11  executes control to turn off the transistors MN 1 , MN 2 . By such control, it is possible to protect the load  30  from an overcurrent state thereof. 
     According to a third embodiment, the detection resistors Rs 1  and Rs 2  are respectively connected between the node N 2  of the semiconductor integrated circuit device  10  and a ground terminal and between the node N 4  thereof and such a ground terminal. A resistance value of the detection resistor Rs 2  is set at a resistance value that is K times as much as that of the detection resistor Rs 1 , so that it is possible to compose a current detection circuit that detects a current that is 1/K times as much as a load current IL. The differential amplifier A 1  and the transistor SN 1  that are integrated in the semiconductor integrated circuit device  10  execute a negative feedback operation in such a manner that a voltage at the node N 3  and a voltage at the node N 4  are equalized. A voltage at the node N 3  and a voltage at the node N 4  depend on the detection resistors Rs 1  and Rs 2 . Therefore, in a case where current detection with a high degree of accuracy is needed, the detection resistor Rs 1  with a high degree of accuracy where a tolerance is ± several % is connected thereto, so that it is possible to provide a current detection circuit with a high degree of accuracy. Additionally, a recommended resistance element (the detection resistor Rs 1 , Rs 2 ) is provided to a user of the semiconductor integrated circuit device  10  as a standard specification, so that selection of a resistance element that is used at a time when such a user composes a current detection circuit with a high degree of accuracy by using the semiconductor integrated circuit device  10  is facilitated, and hence, it is possible to attain convenience of such a user. Furthermore, a current IL/K flows through the detection resistor Rs 2 . Therefore, even if a resistance value of the detection resistor Rs 2  is increased, a square of suppression of a current value contributes to power consumption at the detection resistor Rs 2 , and hence, it is possible to suppress an increase in power consumption greatly. 
     Fourth Embodiment 
       FIG. 4  is a diagram that illustrates a configuration of a current detection circuit according to a fourth embodiment. A current detection circuit in  FIG. 4  has a connection means Rp 1  that connects a node N 2  to a ground terminal. The connection means Rp 1  is, for example, a wiring that grounds a source of a transistor MN 1  on a (non-illustrated) printed-wiring board. The connection means Rp 1  is conveniently illustrated as a resistor that has a resistance value Rp 1 . 
     A node N 3  is connected to one end of a detection resistor Rs 3 , and the other end of the detection resistor Rs 3  is grounded. A resistance value of the detection resistor Rs 3  is set at a resistance value that is K times as much as that of the connection means Rp 1 . A node N 4  is connected to one end of a detection resistor Rs 4 , and the other end of the detection resistor Rs 4  is grounded. A resistance value of the detection resistor Rs 4  is set at a resistance value that is K times as much as that of the connection means Rp 1 . 
     A current ratio between transistors MN 1  and MN 2  is set at K:1. Therefore, a current IL·K/(K 30  1) flows through the connection means Rp 1  and a current IL/(K+ 1 ) flows through the detection resistor Rs 3 . Thereby, voltage drops at the connection means Rp 1  and the detection resistor Rs 3  are equalized, and hence, source-drain voltages and gate-source voltages of the transistors MN 1 , MN 2  are equalized respectively. Hence, it is possible to divide a load current IL into currents on the transistors MN 1  and MN 2  accurately. 
     A negative feedback circuit is composed of a differential amplifier A 1  and a transistor SN 1 . A negative feedback circuit is operated in such a manner that voltages at the node N 3  and the node N 4  are equalized. Therefore, in a case where a resistance value of the detection resistor Rs 3  and a resistance value of the detection resistor Rs 4  are identical, a current with a value that is identical to that of a current that flows through the detection resistor Rs 3 , that is, a current IL/(K+1), flows through the detection resistor Rs 4 . A current that flows through a monitor resistor Rm 1  is nearly equal to a current that flows through the detection resistor Rs 4 . Hence, it is possible to detect a current that is 1/(K+1) times as much as a load current IL by detecting a voltage at a node N 5 . 
     According to the present embodiment, a current that flows through the detection resistor Rs 3  that is connected to the node N 3  is suppressed so as to be a value that is 1/(K+1) times as much as a load current IL. For example, as a value of K is set at 10000, a current that is approximately 1/10000 times as much as a load current IL flows through the detection resistor Rs 3 . The connection means Rp 1  is, for example, of a resistance of a wiring, and is several mΩ to several dozen mΩ. Therefore, in a case where a value of K is 10000, it is possible to use a resistance element with approximately several dozen Ω to several hundred Ω as the detection resistor Rs 3 . The same also applies to the detection resistor Rs 4 . A resistance element with a high resistance value and a low accuracy is comparatively inexpensive. Therefore, it is possible to use a comparatively inexpensive resistance element as the detection resistor Rs 3 , Rs 4 , and hence, it is possible to suppress a cost thereof. 
     Even if resistance values of the detection resistors Rs 3 , Rs 4  are increased, a factor of a square of suppression of a current value contributes to power consumption at the detection resistors Rs 3 , Rs 4 , and hence, it is possible to suppress an increase in power consumption. Furthermore, a semiconductor integrated circuit device  10  has a configuration that is identical to that of the semiconductor integrated circuit device  10  in  FIG. 3 . Therefore, it is possible for the semiconductor integrated circuit device  10  to compose a desired current detection circuit by changing connection of a resistance element or the like, and hence, volume discount that is provided by mass production is allowed. 
     It is possible to use a GaN transistor, an SiC transistor, or an IGBT that is a high-voltage switching element as the transistor MP 1 , MP 2 , MN 1 , MN 2 . In a case where a GAN transistor or an SiC transistor is used, a source-drain path that is a main current path is composed of GaN or SiC. Furthermore, in a case where an IGBT is used, an emitter-collector path composes a main current path. A high-voltage switching element is preferable in a case where a high-voltage power source is used in order to drive the load  30 . Additionally, a high-voltage switching element is formed as, for example, a separate semiconductor chip and connected to a (non-illustrated) semiconductor chip where the differential amplifier A 1  is formed thereon, by a predetermined wiring, so that it is possible to form the semiconductor integrated circuit device  10  on a common printed-wiring board integrally. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.