Patent Publication Number: US-10767224-B2

Title: High data rate integrated circuit with power management

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. application Ser. No. 14/965,568 filed Dec. 20, 2015, which claims the benefit of U.S. Provisional Application No. 62/093,611 filed Dec. 18, 2014. The entire contents of all applications referenced in this section are incorporated by reference herein, each in their entirety. 
    
    
     BACKGROUND 
     Field of the Invention 
     This disclosure, in general, relates to thermal and power management of integrated circuit sensors operating at high data rates, such as used in DNA sequencing technologies, and to systems utilizing such sensors. 
     Description of Related Art 
     A variety of types of sensors have been used in the detection of chemical and/or biological processes. One type is a chemically-sensitive field effect transistor (chemFET). A chemFET includes a gate, a source, a drain separated by a channel region, and a sensitive area, such as a surface on the gate adapted for contact with a fluid, coupled to the channel region. The operation of the chemFET is based on the modulation of channel conductance caused by changes, such as changes in voltage, at the sensitive area which can be due to a chemical and/or biological reaction occurring in the fluid, for example. The modulation of the channel conductance can be sensed to detect and/or determine characteristics of the chemical and/or biological reaction that cause changes at the sensitive area. One way to measure the channel conductance is to apply appropriate bias voltages to the source and drain, and measure a resulting current flowing through the chemFET. A method of measuring channel conductance can include driving a known current through the chemFET and measuring a resulting voltage at the source or drain. 
     An ion-sensitive field effect transistor (ISFET) is a type of chemFET that includes an ion-sensitive layer at the sensitive area. The presence of ions in a fluid containing an analyte alters the surface potential at the interface between the ion-sensitive layer and the analyte fluid which can be due to the protonation or deprotonation of surface charge groups caused by the ions present in the fluid (i.e. an analyte solution). The change in surface potential at the sensitive area of the ISFET affects the gate voltage of the device, and thereby channel conductance, which change can be measured to indicate the presence and/or concentration of ions within the solution. Arrays of ISFETs can be used for monitoring chemical and/or biological reactions, such as DNA sequencing reactions based on the detection of ions present, generated, or used during the reactions. (See, for example, U.S. Pat. No. 7,948,015 to Rothberg et al., filed Dec. 14, 2007, which is incorporated by reference herein in its entirety.) More generally, large arrays of chemFETs or other types of sensors and detectors can be employed to detect and measure static and/or dynamic amounts or concentrations of a variety of analytes in a variety of processes. For example, the processes can be chemical and/or biological reactions, cell or tissue cultures or monitoring neural activity, nucleic acid sequencing, etc. 
     It may be desirable to provide a power and temperature management technology supporting very high data rate DNA sequencing systems, and other systems involving complex electrodynamic and thermodynamic interfaces to integrated circuits. 
     SUMMARY 
     Technology is described for managing power and temperature suitable for use with complex DNA sequencing technologies, and other technologies employing complex sensor arrays. 
     One aspect of the technology comprises a sensor system. The sensor system includes a sensor array that can include rows and columns of sensors. A reactant flow cell may be in contact with the sensor array, and may be configured to apply a sequence of alternating flows of reactant solutions during active intervals and flows of wash solutions during wash intervals to the sensor array. Bias circuitry can apply bias arrangements to the sensor array to produce sensor data. Peripheral circuitry may be coupled to the bias circuitry to produce streams of data from the sensor array. The peripheral circuitry may be configured to have an active mode and an idle mode. Logic may be provided to switch the peripheral circuitry between the active mode and idle mode to control power consumption. During the idle mode, operational readiness of the sensor array may be maintained, while reducing power consumption. Thus, electrical circuitry supporting electro-fluidic conditions of the sensor array remain active during the idle mode. Likewise, transmission of the streams of data may be maintained, to maintain communication links during the idle mode to maintain operational readiness. 
     According to another aspect, the temperature sensors provided which senses a temperature that correlates with temperature of the sensor array. In this example, the logic can include the feedback circuit responsive to the temperature sensor to switch between the active mode and the idle mode to maintain the temperature within an operating range. 
     In one architecture described herein, the peripheral circuitry includes conversion circuitry responsive to configuration parameters to convert the sensor data into a plurality of streams of data, and a plurality of transmitters configured to receive the corresponding streams of data from the plurality of streams from the conversion circuitry and transmit the data to corresponding receivers. Also, a sequencer may be included which operates the bias circuitry to produce frames of sensor data at a frame rate, operates the conversion circuitry to convert the sensor data at a frame rate, and operates the transmitters to transmit the streams of data at the frame rate. In this configuration, the logic may be configured to apply a first set of one or more configuration parameters to the conversion circuitry in the active mode, and a second set of one or more configuration parameters to the conversion circuitry in idle mode. Also, the logic may be configured to apply a third set of one or more configuration parameters to the bias circuitry in the active mode, and a fourth set of one or more configuration parameters to the bias circuitry in idle mode. 
     In one control operation described herein, the peripheral circuitry operates in the active mode for a first number of frames in a time interval overlapping with the active interval, and for a second number of frames in the idle mode in a time interval overlapping with an immediately following wash interval. Logic can adjust the first and second numbers of frames to control power consumption and temperature of the device. 
     An integrated circuit sensor for use in a sensor system is described as well. 
     A method for operating a sensor system in order to conserve power and control temperature is described as well. 
     Other aspects and advantages of the technology described herein may be seen on review of the drawings, the detailed description and the claims, which follow. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of components of a sensor system for nucleic acid sequencing according to an exemplary embodiment. 
         FIG. 2  illustrates a cross-sectional view of a portion of the integrated circuit device and flow cell according to an exemplary embodiment. 
         FIG. 3  illustrates a cross-sectional view of representative sensors/detectors and corresponding reaction regions according to an exemplary embodiment. 
         FIG. 4  is a simplified diagram of a portion of an integrated circuit including a sensor array and phase locked loop coupled transmitter pair configuration. 
         FIG. 5  is a simplified diagram of a clock distribution network for an integrated circuit like that shown in  FIG. 4 . 
         FIG. 6  is a simplified diagram of a clock input buffer for a clock distribution network like that of  FIG. 5 . 
         FIG. 7  illustrates a phase locked loop coupled transmitter pair according to an embodiment of the technology described herein. 
         FIG. 8  is a simplified diagram of a transmit path for an integrated circuit like that shown in  FIG. 4 . 
         FIG. 9  is a simplified diagram of a phase locked loop that may be used in an integrated circuit like that shown in  FIG. 4 . 
         FIGS. 10A and 10B  illustrate a layout of power supply traces and pads for a multiple power domain integrated circuit as described herein. 
         FIG. 11  is an expanded view of the power supply trace and pad layout for a portion of the integrated circuit shown in  FIGS. 10A and 10B . 
         FIG. 12  illustrates a part of an electrostatic discharge protection network which may be used for the multiple power domain integrated circuit described herein. 
         FIG. 13  illustrates another part of an electrostatic discharge protection network which may be used for the multiple power domain integrated circuit described herein. 
         FIG. 14  is a simplified schematic diagram showing peripheral circuitry on a sensor device, subject of power control as described herein. 
         FIG. 15  is a simplified diagram of sequencer control logic which may be used for management of power consumption and temperature as described herein. 
         FIG. 16  is a flowchart showing a method of operating a sensor system as described herein. 
         FIG. 17  is a flowchart showing an alternative method of operating a sensor system as described herein. 
     
    
    
     DETAILED DESCRIPTION 
     A detailed description of embodiments of the sensor technology and components thereof, is provided with reference to the  FIGS. 1-17 . 
       FIG. 1  is a block diagram of components of a system for nucleic acid sequencing according to some embodiments. Such systems include device  100 , which acts as a source of data that produces over 50 Gb per second of digital data, and in examples described herein, produces over 100 Gb per second, and more. As illustrated schematically, a communication bus  127  supporting over 100 Gb per second may be desired in embodiments of the technology described herein. In an example system, a sensor chip includes over 600 million sensors, producing multiple bits per sensor, and senses at high frame rates. A massively parallel system for transmitting data from a sensor array, or other high data rate source of data, on an integrated circuit, to a destination processor is described herein. 
     The nucleic acid sequencing system not only includes a source of huge amounts of data, but also presents design issues that arise because of the nature of the sensing and sequencing technology. Thus, the technology presented herein may be adapted for deployment in such systems, and an example of such a system is described herein. The components include flow cell  101  on integrated circuit device  100 , reference electrode  108 , a plurality of reagents  114  for sequencing, valve block  116 , wash solution  110 , valve  112 , fluidics controller  118 , lines  120 / 122 / 126 , passages  104 / 109 / 111 , waste container  106 , array controller  124 , a reference clock  128  and user interface  129 . Integrated circuit device  100  includes microwell array  107  overlying a sensor array that includes devices as described herein. Flow cell  101  includes inlet  102 , outlet  103 , and flow chamber  105  defining a flow path of reagents over microwell array  107 . Reference electrode  108  may be of any suitable type or shape, including a concentric cylinder with a fluid passage or a wire inserted into a lumen of passage  111 . Reagents  114  may be driven through the fluid pathways, valves, and flow cell  101  by pumps, gas pressure, or other suitable methods, and may be discarded into waste container  106  after exiting outlet  103  of flow cell  101 . Fluidics controller  118  can control driving forces for reagents  114  and operation of valve  112  (for wash fluid) and valve block  116  (for reagents) with a suitable processor executing software-implemented logic, other controller circuitry or combinations of controller circuitry and software-implemented logic. In some embodiments, fluidics controller  118  can control delivery of individual reagents  114  to flow cell  101  and integrated circuit device  100  in a predetermined sequence, for predetermined durations, and/or at predetermined flow rates. 
     Microwell array  107  includes an array of reaction regions which are operationally associated with corresponding sensors in the sensor array. For example, each reaction region may be coupled to one sensor or more than one sensor suitable for detecting an analyte or reaction property of interest within that reaction region. Microwell array  107  may be integrated in integrated circuit device  100 , so that microwell array  107  and the sensor array are part of a single device or chip. Flow cell  101  can have a variety of configurations for controlling the path and flow rate of reagents  114  over microwell array  107 . 
     Array controller  124  provides bias voltages and timing and control signals to integrated circuit device  100  for reading the sensors of the sensor array. Array controller  124  also provides a reference bias voltage to the reference electrode  108  to bias reagents  114  flowing over microwell array  107 . 
     Array controller  124  includes a reader to collect output signals from the sensors of the sensor array through output ports on integrated circuit device  100  via bus  127 , which comprises a plurality of high-speed serial channels for example, carrying sample data at speeds on the order of 100 gigabits per second or greater. In one example, twenty four serial channels, each of which nominally operates at 5 Gb per second, are implemented in the bus  127 . A reference clock  128  may be coupled with the device  100  to provide a stable reference clock for use in controlling high-speed serial channels. In embodiments described herein, the reference clock  128  can operate at relatively low frequencies, on the order of 100 MHz or 200 MHz, as compared to the Gb data rates desired to support the high-speed serial channels. Array controller  124  can include a data processing system, with a reader board including a set of field programmable gate arrays (FPGAs), having a plurality of receivers in support of the transmitters on the device  100 . Array controller  124  can include memory for storage of data and software applications, a processor for accessing data and executing applications, and components that facilitate communication with the various components of the system in  FIG. 1 . 
     The values of the output signals of the sensors can indicate physical and/or chemical parameters of one or more reactions taking place in the corresponding reaction regions in microwell array  107 . For example, in some exemplary embodiments, the values of the output signals may be processed using the techniques disclosed in Rearick et al., U.S. Pat. Pub. No. 2012/0172241 (application Ser. No. 13/339,846, filed Dec. 29, 2011), and in Hubbell, U.S. Pat. Pub. No. 2012/0173158 (application Ser. No. 13/339,753, filed Dec. 29, 2011), which are all incorporated by reference herein in their entirety. User interface  129  can display information about flow cell  101  and the output signals received from sensors in the sensor array on integrated circuit device  100 . User interface  129  can also display instrument settings and controls, and allow a user to enter or set instrument settings and controls. 
     Array controller  124  can collect and analyze the output signals of the sensors related to chemical and/or biological reactions occurring in response to the delivery of reagents  114 . A management bus  134  may be connected between the array controller  124  and the integrated circuit  100 , and used for controlling operation of the sensor array and other control functions. The array controller  124  can also be coupled to the fluidics controller, to provide for coordinated operation of the array and the fluid flow dynamics. The system can also monitor and control the temperature of integrated circuit device  100  using a temperature sensor  133  on the integrated circuit, so that reactions take place and measurements are made at a regulated temperature. The temperature sensor  133  may be integrated on the integrated circuit device  100 , or otherwise coupled to the integrated circuit substrate or package (i.e. chip) or the flow cell  101  to sense a temperature that correlates with the temperature of the sensor array such that it may be used in a process to control temperature of the array. The system may be configured to let a single fluid or reagent contact reference electrode  108  throughout an entire multi-step reaction during operation. Valve  112  may be shut to prevent any wash solution  110  from flowing into passage  109  as reagents  114  are flowing. Although the flow of wash solution may be stopped, there can still be uninterrupted fluid and electrical communication between reference electrode  108 , passage  109 , and microwell array  107 . The distance between reference electrode  108  and the junction between passages  109  and  111  may be selected so that little or no amount of the reagents flowing in passage  109 , and possibly diffusing into passage  111 , reach reference electrode  108 . In some embodiments, wash solution  110  may be selected as being in continuous contact with reference electrode  108 , which may be especially useful for multi-step reactions using frequent wash steps. 
       FIG. 2  illustrates a cross-sectional view of a portion of an exemplary integrated circuit device  200 , flow cell  201  and reference electrode  208 . The device includes a sensor array (schematically  205 ) coupled to a microwell array (schematically  207 ). During operation, flow chamber  204  of flow cell  201  confines reagent flow  206  of delivered reagents across open ends of the reaction regions in microwell array  207 . The volume, shape, aspect ratio (such as base width-to-well depth ratio), and other dimensional characteristics of the reaction regions may be selected based on the nature of the reaction taking place, as well as the reagents, products/byproducts, or labeling techniques (if any) that are employed. The sensors of sensor array  205  may be responsive to (and generate output signals related to) chemical and/or biological reactions within associated reaction regions in microwell array  207  to detect an analyte or reaction property of interest. The sensors of sensor array  205  may be chemically sensitive field-effect transistors (chemFETs), such as ion-sensitive field effect transistors (ISFETs). Examples of sensors and array configurations that may be used in embodiments are described in U.S. Patent Application Publication No. 2010/0300559, filed May 24, 2010, No. 2010/0197507, filed Oct. 5, 2012, No. 2010/0301398, filed Oct. 5, 2012, No. 2010/0300895, May 4, 2010, No. 2010/0137143, filed May 29, 2009, and No. 2009/0026082, filed Dec. 17, 2007, and U.S. Pat. No. 7,575,865, filed Aug. 1, 2005, each of which are incorporated by reference herein in their entirety. The interfacial fluid dynamics proximal to the microwell involve flow rate, electrolytic potential relative to the sensor array, temperature and other complex factors which can influence the sensor array in ways that may not relate to the analyte (such as a base on a DNA string) being measured. It may be desirable to maintain stability of the interfacial fluid dynamics during a sequencing operation. The system includes a power and temperature controller  212 , which may be a part of the array controller described with reference to  FIG. 1 . The power and temperature controller  212  can communicate with the circuitry on the integrated circuit  200  to control electrical and thermal configuration of the integrated circuit, and assist in maintaining stability of the interfacial fluid dynamics, in coordination with the fluidic controller which can manage flow rates and temperatures of the fluids. 
     The integrated circuit device  200  includes a large number of serial ports supporting connection to a massively parallel reader  211  via a set of serial channels  210 . The reagent flow  206 , coupled with a large array of ISFETs, presents a complex electrical and mechanical environment in which such a system can operate with high integrity. 
     In some embodiments, other types of sensor arrays may be used in systems like that of  FIG. 1 , including but not limited to arrays of thermistors and arrays of optical sensors. 
       FIG. 3  illustrates a cross-sectional view of representative sensors/detectors and corresponding reaction regions according to an exemplary embodiment. In some embodiments the sensors may be chemical sensors. Fig. shows 3 two exemplary sensors  350 ,  351 , representing a small portion of a sensor array that can include millions of sensors; even billions of sensors are contemplated. For example, the sensor array can comprise between 100 and 1,000 sensors, between 100 and 10,000 sensors, between 10,000 and 100,000 sensors, between 100,000 and 1,000,000 sensors, between 1,000,000 and 40,000,000 sensors, between 10,000,000 and 165,000,000 sensors, between 100,000,000 and 660,000,000 sensors, between 1,000,000,000 and 5,000,000,000 sensors, between 5,000,000,000 and 9,000,000,000 sensors, and up to 10,000,000,000 sensors. Windowing of the array is contemplated such that data can be obtained from all or fewer than all of the sensors. Sensor  350  is coupled to corresponding reaction region  301 , and sensor  351  is coupled to corresponding reaction region  302 . The two illustrated reaction regions are chemically and electrically isolated from one another and from neighboring reaction regions. The dielectric material  303  defines the reaction regions  301 / 302  which may be within an opening defined by an absence of dielectric material. Dielectric material  303  can comprise one or more layers of material, such as silicon dioxide or silicon nitride or any other suitable material or mixture of materials. The dimensions of the openings, and their pitch, can vary from embodiment to embodiment. In some embodiments, the openings can have a characteristic diameter, defined as the square root of 4 times the plan view cross-sectional area (A) divided by Pi (e.g., sqrt(4*A/π), of not greater than 5 micrometers, such as not greater than 3.5 micrometers, not greater than 2.0 micrometers, not greater than 1.6 micrometers, not greater than 1.0 micrometers, not greater than 0.8 micrometers, not greater than 0.6 micrometers, not greater than 0.4 micrometers, not greater than 0.2 micrometers or not greater than 0.1 micrometers. The plan view area of the sensor is determined in part by the width (or diameter) of reaction regions and may be made small to provide a high density array. The footprint of a sensor may be determined and/or reduced by modifying the width (e.g. diameter) of the reaction region. In some embodiments, the density of the array may be increased or decreased based on the diameter selected for the reaction region. Low noise sensors may be provided in a high density array by reducing device and interconnect overhead, including gate area and contact area. Additional examples of sensors and their corresponding reaction regions according to additional exemplary embodiments are described in Fife et al., U.S. patent application Ser. No. 14/198,382, filed Mar. 5, 2014, based on U.S. Prov. Pat. Appl. Nos. 61/868,739, filed Aug. 22, 2013, and 61/790,866, filed Mar. 15, 2013; Fife et al., U.S. patent application Ser. No. 14/197,710, filed Mar. 5, 2014, based on U.S. Prov. Pat. Appl. Nos. 61/868,736, filed Aug. 22, 2013, and 61/790,866, filed Mar. 15, 2013; Fife et al., U.S. patent application Ser. No. 14/198,402, filed Mar. 5, 2014, based on U.S. Prov. Pat. Appl. Nos. 61/868,942, filed Aug. 22, 2013, and 61/790,866, filed Mar. 15, 2013; Fife et al., U.S. patent application Ser. No. 14/197,741, filed Mar. 5, 2014, based on U.S. Prov. Pat. Appl. Nos. 61/868,947, filed Aug. 22, 2013, and 61/790,866, filed Mar. 15, 2013; and Fife et al., U.S. patent application Ser. No. 14/198,417, filed Mar. 5, 2014, based on U.S. Prov. Pat. Appl. Nos. 61/900,907, filed Aug. 22, 2013, and 61/790,866, filed Mar. 15, 2013, which are all incorporated by reference herein in their entirety. 
     Sensor  350  is representative of the sensors in the sensor array. In the illustrated example, sensor  350  is a chemically-sensitive field effect transistor (chemFET), more specifically an ion-sensitive field effect transistor (ISFET) in this example. Sensor  350  includes floating gate structure  318  having sensor plate  320  coupled to reaction region  301  by electrode  307  which can have a surface adapted for contact with an electrolyte (an ionic conducting liquid). Sensor plate  320  is the uppermost floating gate conductor in floating gate structure  318 . In the illustrated example, floating gate structure  318  includes multiple patterned layers of conductive material within layers of dielectric material  319 . Sensor  350  also includes conduction terminals including source/drain region  321  and source/drain region  322  within semiconductor substrate  354 . Source/drain region  321  and source/drain region  322  comprise doped semiconductor material having a conductivity type different from the conductivity type of substrate  354 . For example, source/drain region  321  and source/drain region  322  can comprise doped P-type semiconductor material, and the substrate can comprise doped N-type semiconductor material. Channel region  323  separates source/drain region  321  and source/drain region  322 . Floating gate structure  318  overlies channel region  323 , and is separated from substrate  354  by gate dielectric  352 . Gate dielectric may be silicon dioxide, for example. Alternatively, other suitable dielectrics may be used for gate dielectric  352  such as, for example materials with higher dielectric constants, silicon carbide (SiC), silicon nitride (Si 3 N 4 ), Oxynitride, aluminum nitride (AlN), hafnium dioxide (HfO 2 ), tin oxide (SnO 2 ), cesium oxide (CeO2), titanium oxide (TiO2), tungsten oxide (WO3), aluminum oxide (Al2O3), lanthanum oxide (La2O3), gadolinium oxide and others, and any combination thereof. 
     In some embodiments, sensor  350  includes electrode  307  overlying and in communication with an uppermost floating gate conductor in the plurality of floating gate conductors. Upper surface  308  of electrode  307  defines a bottom surface of a reaction region for the sensor. Upper surface  308  of electrode  307  can act as the sensor surface of the sensitive area for sensor  350 . Electrode  307  can comprise one or more of a variety of different materials to facilitate sensitivity to particular ions. For example, silicon nitride or silicon oxynitride, as well as metal oxides such as silicon oxide, aluminum or tantalum oxides, generally provide sensitivity to hydrogen ions, whereas sensing materials comprising polyvinyl chloride containing valinomycin provide sensitivity to potassium ions. Materials sensitive to other ions such as sodium, silver, iron, bromine, iodine, calcium, hydroxide, phosphate, and nitrate can also be used. In the illustrated example, electrode  307  is shown as a single layer of material. More generally, the electrically electrode can comprise one or more layers of a variety of electrically conductive materials, such as metals or ceramics, or any other suitable conductive material or mixture of materials, depending upon the implementation. The conductive material may be any suitable metallic material or alloy thereof, or may be any suitable ceramic material, or a combination thereof. Examples of metallic materials include aluminum, copper, nickel, titanium, silver, gold, platinum, hafnium, lanthanum, tantalum, tungsten, iridium, zirconium, palladium, or any suitable material or combination thereof. Examples of ceramic materials include one of titanium nitride, titanium aluminum nitride, titanium oxynitride, tantalum nitride, or any suitable combination thereof. In some embodiments, an additional sensing material (not shown) is deposited on upper surface  308  of electrode  307 . In some embodiments, the electrode may be titanium nitride, and titanium oxide or titanium oxynitride may be grown on the upper surface  308  during manufacturing and/or during exposure to fluids during use. Whether an oxide is formed on the upper surface depends on the conductive material used, the manufacturing processes performed, and/or the conditions under which the sensor is operated. The electrode may be formed in various shapes (width, height, etc.) depending on the materials and/or etch techniques and/or fabrication processes etc. used during the manufacture process. 
     In some embodiments, reactants, wash solutions, and other reagents can move in and out of reaction region  301  by diffusion mechanism. Sensor  350  is responsive to (and can generate an output signal related to) charge  324  proximate to electrode  307 . For example, when the sensor is coupled to an electrolyte, the sensor may be responsive to an electrolytic potential at the sensor surface. The responsiveness of the sensor can relate to the amount of charge that is present proximate to the electrode  307 . The presence of charge  324  in an analyte solution can alter the surface potential at the interface between the analyte solution and upper surface  308  of electrode  307 . For example, the surface potential may be altered by protonation or deprotonation of surface groups caused by the ions present in the analyte solution. In another example, the charge of surface functionality or absorbed chemical species may be altered by analytes in solution. Changes in the amount of charge present can cause changes in the voltage on floating gate structure  318 , which in turn can cause an effective change in the threshold voltage of the transistor of sensor  350 . The potential at the interface may be measured by measuring the current in channel region  323  between source region  321  and drain region  322 . As a result, sensor  350  may be used directly to provide a current-based output signal on an array line connected to source region  321  or drain region  322 , or indirectly with additional circuitry to provide a voltage-based output signal. Charge may be more highly concentrated near the bottom of reaction region  301 . Accordingly, in some embodiments variations in the dimensions of the electrode can have an effect on the amplitude of the signal detected in response to charge  324 . 
     In some embodiments, reactions carried out in reaction region  301  may be analytical reactions to identify or determine characteristics or properties of an analyte of interest. Such reactions can generate directly or indirectly products/byproducts that affect the amount of charge adjacent to electrode  307 . If such products/byproducts are produced in small amounts or rapidly decay or react with other constituents, multiple copies of the same analyte may be analyzed in reaction region  301  at the same time in order to increase the output signal generated. In some embodiments, multiple copies of an analyte may be attached to solid phase support  312 , either before or after being deposited into reaction region  301 . Solid phase support  312  may be a particle, a microparticle, a nanoparticle. In some embodiments, the analyte may be attached to a bead which may be solid or porous and can further comprise a gel, or the like, or any other suitable solid support that may be introduced to a reaction region. In some embodiments, copies of an analyte may be located in a solution proximal to a sensor of a reaction region. Alternatively, copies of an analyte can bind directly to the surface of the sensor to capture agents includes the material on the surface or if there are pores on the surface (for example, copies of an analyte can bind directly to electrode  307 ). The solid phase support may be of varied size, for example, in a range of 100 nm to 10 micrometers. Further, the solid support may be positioned in the opening at various places. For a nucleic acid analyte, multiple, connected copies may be made by rolling circle amplification (RCA), exponential RCA, polymerase chain reaction (PCR) or like techniques, to produce an amplicon without the need of a solid support. 
     In various exemplary embodiments, the methods, and systems described herein can advantageously be used to process and/or analyze data and signals obtained from a biological reaction, including amplification or electronic or charged-based nucleic acid sequencing. In electronic or charged-based sequencing (such as pH-based sequencing), a nucleotide incorporation event may be determined by detecting ions (e.g., hydrogen ions) that are generated as natural products of polymerase-catalyzed nucleotide extension reactions. This may be used to sequence a sample or template nucleic acid, which may be a fragment of a nucleic acid sequence of interest, for example, and which may be directly or indirectly attached as a clonal population to a solid support, such as a particle, microparticle, bead, etc. The sample or template nucleic acid may be operably associated to a primer and polymerase and may be subjected to repeated cycles or “flows” of deoxynucleoside triphosphate (“dNTP”) addition (which may be referred to herein as “nucleotide flows” from which nucleotide incorporations can result) and washing. The primer may be annealed to the sample or template so that the primer&#39;s  3 ′ end may be extended by a polymerase whenever dNTPs complementary to the next base in the template are added. Based on the known sequence of nucleotide flows and on measured output signals of the sensors indicative of ion concentration during each nucleotide flow, the identity of the type, sequence and number of nucleotide(s) associated with a sample nucleic acid present in a reaction region coupled to a sensor may be determined. 
       FIG. 4  is a simplified block diagram of part of the circuitry on an integrated circuit sensor array used for DNA sequencing. The integrated circuit includes a 660 megapixel ISFET sensor array  401  on a substrate  400 . An upper set of column bias/select circuits  402 U and an upper row decoder  531  are configured for access to an upper half of the array  401 . A lower set of column bias/select circuits  402 L and a lower row decoder  521  are configured for access to a lower half of the array  401 . 
     An upper set of analog-to-digital converter (ADC) circuits  403 U is coupled to the upper set of column bias and select circuits  402 U. An upper register array  404 U is coupled to the upper set of analog-to-digital converter (ADC) circuits  403 U. The upper register array  404 U is configured to provide a plurality of streams of digital data through serializers (e.g.  511 ,  512 ) to corresponding transmitters (e.g.  405 - 23 ,  405 - 22 ). Each of the transmitters is coupled to a corresponding pair (a pair for D[ 23 ], a pair for D[ 22 ]) of output pads, which in turn are connected to transmission lines (not shown). 
     Likewise, a lower set of analog-to-digital converter circuits  403 L is coupled to the lower set of column bias and select circuits  402 L. A lower register array  404 L is coupled to the lower set of analog-to-digital converter circuits  403 L. The lower register array  404 L is configured to provide a plurality of streams of digital data through serializers (e.g.  501 ,  502 ) to corresponding transmitters (e.g.  405 - 0 ,  405 - 1 ). Each of the transmitters is coupled to a corresponding pair (D[ 0 ], D[ 1 ]) of output pads, which in turn are connected to transmission lines (not shown). 
     The array may include a number of reference cells, which are not coupled to the fluidics. The gates of the reference cells are coupled to a reference voltage circuit, and provide reference readings used in analysis of the data from the ISFETs that are coupled to the fluidics. 
     The configurations described herein support a device having a large number of gigabit per second transmitters, such as at least 20 transmitters capable of transmission at a data rate greater than 1 Gb per second, and configured in at least 10 pairs. For one example, the device includes 24 transmitters capable of transmitting data at 5 Gb per second each, or faster, supporting throughput from a high speed data source of 120 Gb per second or more. Large numbers of gigabit per second transmitters present a context in which a class of implementation problems arises which is not apparent in configurations with small numbers of transmitters. 
     Supporting peripheral circuitry including a sequencer (seq)  532 , a digital-to-analog converter (DAC)  533 , a gray code counter (grey)  534 , and bias circuitry (bias)  535  is coupled to the upper circuitry. Also, supporting circuitry including a sequencer  522 , a digital-to-analog converter  523 , a gray code counter  524 , and bias circuitry  525  is coupled to the lower circuitry. The chip includes a serial peripheral interface control block (spi ctrl)  540  including configuration registers and providing an interface of a management bus used in configuration and control of the device, and a fuse array (fuse)  541  used in configuration of the device. The sequencer  522 ,  532  operates the sensor array (or other data source), the peripheral circuitry and the plurality of transmitters to sample frames of data at a frame rate according an active mode and an idle mode, wherein the sequencer operates in the active mode for a first number of frames in a first time interval and in the idle mode for a second number of frames in a second time interval. The operation of the sequencer  522 ,  532  is coordinated in the sensing system with the fluidics controller, so that the first time interval overlaps with a flow of reactant solution, and the second time interval overlaps with an immediately following flow of wash solution. 
     In one example operating technique, sequencer  522 ,  532  causes the circuitry to perform a frame sensing sequence. In a frame sensing sequence, a row of ISFETs in each of the upper and lower halves of the array may be selected and biased using the column bias/select circuits  402 U/ 402 L so that a current that is a function of the charge in that corresponding sensor well may be produced on each column line. The analog-to-digital converter circuits  403 U/ 403 L receive a ramp signal from the digital-to-analog converter  533 ,  523 , and produce an output signal when the current on the corresponding column line matches the level of the ramp signal. The gray code counter  524 ,  534  may be sampled in response to the output signal, and the results are stored in the register array  404 U/ 404 L. Data in the register array  404 U/ 404 L are assembled into packets, and applied in a plurality of digital data streams to the transmitters on the chip. 
     The illustrated part of the circuitry in  FIG. 4  includes four transmitters out of a set of 24 transmitters on the substrate  400 . The four transmitters illustrated include a first pair of transmitters  405 - 0 ,  405 - 1 , and a second pair of transmitters  405 - 22 ,  405 - 23 . As shown, one phase locked loop  406 - 0 , including a low pass filter, is coupled to the first pair of transmitters  405 - 0 ,  405 - 1 . Also, one phase locked loop  406 - 11 , including a low pass filter, is coupled to the second pair of transmitters  405 - 22 ,  405 - 23 . The phased locked loops operate as clock multipliers, each of which produces a local transmit clock and provides the local transmit clock to the transmitter on its left and to the transmitter on its right via clock lines (e.g.  407   a ,  407   b  at phase locked loop  406 - 0 ). 
     Each phase locked loop/low pass filter,  406 - 0 ,  406 - 11 , is coupled with corresponding phase locked loop control block  503 ,  513  which stores parameters used to control and calibrate phase locked loop. 
     This pattern may be repeated across the 24 transmitters on the chip, so that there are 12 phase locked loop blocks, and 24 transmitters. The transmitters are grouped into pairs which are coupled to individual phase locked loops. The phase locked loops are disposed on the substrate between the transmitters, so that the transmission distance from the phase locked loop to the transmitter using the clock produced in the phase locked loop may be small. 
     As illustrated, each of the phase locked loops  406 - 0 ,  406 - 11  is coupled to an individual power pad VDDP and an individual ground pad GNDP. Also, the individual power pad VDDP and the individual ground pad GNDP for each phase locked loop are disposed on the chip adjacent the phase locked loop, and between the output pads for the transmitter on the left, and the output pads for the transmitter on the right in the corresponding transmitter pair. 
     The individual power pad VDDP and the individual ground pad GNDP are connected to an off-chip voltage supply, which may be configured with bypass capacitors and other circuitry, to create a low noise power configuration for the phase locked loop circuits, and to reduce coupling of noise between the high-frequency phase locked loop circuits and other circuits on the substrate  400 . 
     A low-speed reference clock (not shown, see  FIG. 5 ) may be distributed on the chip and connected to each of the phase locked loops. 
     The clock multipliers in the illustrated embodiment are implemented using phase locked loops. Clock multipliers may be implemented using other circuitry as well, such as delay locked loops, phase interpolators, and combinations of phase locked loops, phase interpolators and/or delay locked loops. 
     In this example, the integrated circuit substrate  400  includes on-chip temperature sensors  537 ,  538 , configured on each of the four corners of the chip. The temperature readings are sampled by the SPI control block  540 , and stored for access by off-chip controllers via the management bus. Also, the temperature readings are utilized by the sequencers to control power consumption and temperature on the device. In other embodiments, the temperature sensor or sensors may be configured differently. In yet other embodiments, a temperature sensor may be coupled to the microwell array structure, in addition to or in the alternative to the temperature sensor or sensors on chip. 
       FIG. 5  illustrates clock distribution circuitry which may be utilized with a device like that shown in  FIG. 4 . The clock distribution circuitry includes a clock input buffer  570  which includes CLKP and CLKN inputs configurable to receive a differential clock signal or a single ended clock signal from an off-chip clock reference. The output of the clock buffer  570  may be distributed in a daisy chain fashion to the phase locked loops  580 - 0  through  580 - 5  disposed along a lower side of the chip, and through a duty cycle correction DCC chain  571 , which includes a group of cascaded DCC buffers to support transmission of the reference clock across the large chip, to the phase locked loops  580 - 6  through  580 - 11  along an upper side of the chip. In this example, the reference clock may be distributed to the transmitter units xmt 0  to xmtl  1  on the lower side and via the DCC chain  571  to transmitter units xmt 12  to xmt 23  on the upper side. Each of the transmitter units includes a duty cycle correction DCC buffer, and passes the reference clock from the DCC buffer in the transmitter unit to its adjacent phase locked loop, or adjacent transmitter unit. An example of the transmitter unit circuitry including this DCC buffer is illustrated with reference to  FIG. 7 . In alternatives, the reference clock may be coupled directly to the phase locked loop circuit, and DCC buffers may be disposed on the chip in other configurations as desired. 
     The clock distribution circuit provides a reference clock at a relatively low frequency, such as 125 MHz, with a 50% duty cycle to each of the phase locked loops. In this example, the reference clock may be distributed asynchronously to the phase locked loops. 
       FIG. 6  is a block diagram of the clock input buffer  570  shown in  FIG. 5 . The clock input buffer  570  in this example includes a multiplexer  991 . The CLKP pad is connected to both the “0” and “1” inputs of the multiplexer  991 . The CLKN pad is connected to the “0” input of the multiplexer  991 . A parameter set on the device, labeled cmos_sel in the figure, controls the multiplexer  991  so that it converts the differential input in one mode to a single ended output, or provides the single ended input as the single ended output. The single ended output of the multiplexer  991  may be supplied through a NAND gate  992  to a DCC buffer  993 . The NAND gate  992  may be controlled by a control signal labeled ref sel in this example. The output of the DCC buffer  993  is the reference clock to be distributed on the chip. 
     A duty cycle correction circuit, such as that used for the DCC buffer  993 , or used in the DCC chain  571  described with reference to  FIG. 5 , may be implemented using a variety of circuit structures. Examples are described in the literature, including Ogawa, et al., “A 50% DUTY-CYCLE CORRECTION CIRCUIT FOR PLL OUTPUT,” IEEE International Symposium on Circuits and Systems (Volume:4) ISCAS 2002; M. Ragavan, et al. “DUTY CYCLE CORRECTOR WITH SAR FOR DDR DRAM APPLICATION,” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 2, Issue 5, May 2013, which are incorporate by reference in their entirety. 
       FIG. 7  illustrates a configuration of a transmitter pair according to embodiments of the technology described herein. Each transmitter pair includes first transmitter XMT  610  and second transmitter XMT  611 , which in this example correspond to the transmitter for output D[ 0 ] and the transmitter for output D[ 1 ] on the chip. A phase locked loop/low pass filter circuit (PLL/LPF)  612  may be disposed between the transmitters  610 ,  611  in the pair. Transmitter control blocks  620 ,  621  are coupled to the corresponding transmitters  610 ,  611 . Corresponding data streams  630 ,  631  are input to the transmit control block  620 ,  621  from the register array on the chip. A phase locked loop control block  622  is coupled to the phase locked loop/low pass filter  612 . 
     Three power domains are implemented in the transmitter pair configuration shown in  FIG. 7 . Control blocks  620 ,  621 ,  622  receive power in a digital power domain based on the supply terminals VDDD and GNDD. The transmitters  610 ,  611  receive power in a transmitter power domain (output “0” power) based on supply terminals VDDO, GNDO. The phase locked loop/low pass filter circuits are disposed in individual power domains based on supply terminals VDDP, GNDP that are directly connected to the phase locked loop/low pass filter circuitry. 
     The reference clock RCLK is coupled to the phase locked loop from clock distribution circuitry, like that described above. A system clock SCLK is coupled to the control blocks  620 ,  621 ,  622 . The system clock can operate nominally at the same frequency as the reference clock in some embodiments, but may be a different frequency. 
     The phase locked loop  612  operates as a clock multiplier, producing a high speed, local transmit clock on line  650 . 
     In one example, the system clock and reference clock operate at 125 MHz. The high-speed, local transmit clock may be produced at 2.5 GHz ( 20   x  multiplication). The transmitters in this example transmit on both the rising and falling edges of the local transmit clock, resulting in a transmission rate of 5 Gb per second. In a chip having 24 transmitters operating at 5 Gb per second, a throughput of 120 Gb per second may be achieved. 
     High data integrity of the transmitted data may be supported using techniques including distribution of a low-speed reference clock, the configuration of the phase locked loops in individual power domains, the placement of the phase locked loops between corresponding pairs of transmitters, and local use of the locally produced high-speed transmit clocks. 
       FIG. 8  is a block diagram of a transmitter and transmitter control block  700  which may be used in the configuration shown in  FIGS. 5 and 7 . A reference clock refclk may be supplied as input to a single output, DCC buffer  710 . The output of the DCC buffer  710  may be applied as an output refclk 0  for connection in daisy chain fashion as illustrated in  FIG. 5 . Also, the output of DCC buffer  710  may be supplied to a clock selector  711 , which also includes a differential output DCC buffer. Clock selector  711  is capable of selecting between the local high-speed transmit clock, labeled PLLclk in this example, and the reference clock output from the DCC buffer  710 . A control signal rclk_sel may be used to determine the selection. The ability to select the reference clock output from DCC buffer  710  supports testing the chip. In operating mode, the local high-speed transmit clock PLLclk may be selected. The output of the clock selector  711  may be a duty cycle-corrected, differential clock on lines  720 , at the local transmit clock frequency. 
     The differential clock on lines  720  may be supplied to a synchronizer circuit (sync)  701 , a serializer circuit  702 , a pre-driver  703 , and an off-chip driver  704 . The output of the off-chip driver may be connected to the pads OUTP and OUTN, which are in turn connected to a transmission line. The synchronizer circuit  701  also receives the system clock, and produces a synchronized system clock for the serializer  702 . The data stream from the register arrays are applied in this example in 20 bit packets to the serializer  702 . The output of the serializer, which may be scrambled to maintain signal transition rates for the communication links, may be applied to the pre-driver  703 , and then off chip via the off-chip driver  704 . 
       FIG. 9  is a block diagram of a phase locked loop  800  including a low pass filter, which may be utilized in the configuration of  FIGS. 5 and 7 . The phase locked loop  800  includes a phase frequency detector PFD ( 801 ) connected to the reference clock, a charge pump  802 , a low pass filter  803 , and a ring voltage controlled oscillator (VCO)  804 . A programmable divider  805  may be connected between the output of the ring VCO  804 , and the input of the phase and frequency detector  801 . The programmable divider  805  in this example includes a clock selector  811 , a first divider  810 , and a second divider  812 . The clock selector  811  receives the output of the ring VCO  804  at one input, and the output of the divider  810  on a second input. The divider  810  in this example may be a divide-by-two block. A control signal div&lt;0&gt; controls the clock selector  811 . The output of the clock selector  811  may be applied as the local high-speed transmit clock pllclk. The output of the divider  810  may be applied to the input of the second divider  812 . The second divider is configurable to divide by five (O:/5), or to divide by 10 1:/10, in response to a control signal div&lt;1&gt;. In combination, during operation, combination of the first divider  810  and the second divider  812  provides a divide-by-20 (VCO/20) operation in the 5 Gb per second example described above so that, in effect, the local high-speed transmit clock can operate at 20 times the frequency of the reference clock. 
     A variety of control parameters are coupled to the various blocks in the phase locked loop  800 . Parameters “fast, lock, slow” are provided from the phase and frequency detector  801  to control circuitry. Charge pump bias parameters bias_CP&lt;3:0&gt; are applied to the charge pump  802 . Low pass filter parameters C1&lt;5:0&gt; and C2&lt;4:0&gt; are applied to the low pass filter  803 . VCO control parameters band_ctl&lt;3:0&gt; are applied to the ring VCO  804 . The phase locked loop may be digitally controlled using basic phase locked loop management for calibration and configuration, driven by link control logic on the reader board in one example. In other embodiments, phase locked loop calibration and configuration may be locally driven, or a combination of local and remote operations may be utilized. 
     The low pass filter in the phase locked loop may be configured with a transfer function that rejects jitter in the reference clock. This may be implemented in the charge pump and filter circuitry in the loop as it operates on the output of the phase and frequency detector nominally at the frequency of the reference clock. 
       FIGS. 10A and 10B  illustrate a layout of the transmitter circuits and power traces of an example sensor integrated circuit, in support of a multiple power domain system. The reference numerals used in  FIG. 4  are used again for like components. Thus, the device includes a substrate  400 . A 660 megapixel ISFET sensor array  401  may be implemented on the substrate. Upper and lower column bias and select circuits  402 U,  402 L, upper and lower analog-to-digital converter circuits  403 U,  403 L, and upper and lower register arrays  404 U,  404 L are implemented in the central region of the chip. Twelve transmitter pairs are disposed around the perimeter of the chip, with six pairs on the lower side of the chip, and six pairs on the upper side of the chip. The plurality of transmitter pairs includes first transmitter pair  405 - 0 ,  405 - 1 , and second transmitter pair  405 - 2 ,  405 - 3 , illustrated in  FIG. 10A ; and transmitter pair  405 - 8 ,  405 - 9 , transmitter pair  405 - 10 ,  405 - 11  illustrated in  FIG. 10B  on the lower edge. Also, the plurality of transmitter pairs includes transmitter pair  405 - 12 ,  405 - 13  and transmitter pair  405 - 14 ,  405 - 15  illustrated in  FIG. 10B  and transmitter pair  405 - 20   405 - 21  transmitter pair  405 - 22   405 - 23  illustrated in  FIG. 10A  on the upper edge. Four additional transmitter pairs are implemented on the chip along the upper and lower edges, but are omitted from the drawing because of the cutout. Thus, 12 transmitter pairs are implemented on the substrate  400 , for a total of 24 transmitters. As described above, each transmitter pair includes a local clock multiplier, implemented in this example by a phase locked loop with a low pass filter. Thus,  FIGS. 10A and 10B  show phase locked loops  406 - 0 ,  406 - 1 ,  406 - 4 ,  406 - 5 ,  406 - 6 ,  406 - 7 ,  406 - 10 , and  406 - 11  each of which may be placed on the substrate between the transmitters in a corresponding pair of transmitters. 
       FIGS. 10A and 10B  illustrate an example of a substrate that includes one or more power domains for a high data rate data source, such as the array of ISFETs illustrated, for the transmitters and for peripheral logic including reference clock distribution circuitry. In the layout of  FIGS. 10A and 10B , the clock multipliers are disposed on the substrate in individual power domains separate from one another and from the other one or more power domains. 
       FIGS. 10A and 10B  illustrate a configuration of power pads and power traces on the chip to support multiple power domains. The power domains include an analog power domain GNDA, VDDA, a digital power domain GNDD, VDDD, and a transmitter power domain GNDO, VDDO. In addition, the power domains include 12 individual power domains, one for each phase locked loop. The power pads are conductive pads on the substrate  400  adapted for connection to a pin or other connector structure for an electrical connection to off-chip structures. Such power pads often include a pad of patterned metal in the highest metal layer on the device. The power traces are conductive traces on the substrate adapted for distributing power across a region of the substrate. Such power traces are often implemented in the highest patterned metal layer on the device, and have relatively large width dimensions to support carrying a significant amount of current. 
     The analog power domain includes power pads labeled GNDA, VDDA on each of the four corners of the substrate  400 . The analog power domain includes a power bus including a trace  411 V connected to the VDDA power pads (e.g.  420 V in the lower left), and a trace  411 G connected to the GNDA power pads (e.g.  420 G in the lower left). Traces  411 V and  411 G are configured on the device as the inside power traces, and surround the analog core of the device, which includes the sensor array  401 , and portions of the other circuitry. 
     The digital power domain includes power pads labeled GNDD, VDDD distributed in pairs around the perimeter of the chip, including one pair between each transmitter. The digital power domain includes a power bus including a trace  412 V connected to the VDDD power pads, and a trace  412 G connected to the GNDD power pads. The traces  412 V and  412 G are placed on the device just outside the analog power domain traces  411 V and  411 G, and are placed adjacent digital circuitry surrounding the analog core of the chip. 
     The transmitter power domain includes power pads labeled GNDO, VDDO distributed in pairs around the perimeter of the chip, with one pair for every transmitter. Each pair of transmitter power domain power pads includes a GNDO pad on one side of the corresponding transmitter, and a VDDO pad on the opposite side of the corresponding transmitter. The transmitter power domain includes a power bus including trace  413 V connected to the VDDO power pads and a trace  413 G connected to the GNDO power pads. The traces  413 V and  413 G are configured on the device just outside the digital power domain traces  412 V and  412 G, and are placed for distribution of power supply voltages to the transmitters on the perimeter of the chip. 
     In this example, each phase locked loop may be disposed in an individual power domain. Thus, for the chip including 12 phase locked loops (or other clock multipliers) coupled with 24 transmitters, there are 12 clock multiplier power domains. Each local clock multiplier power domain includes a pair of power pads labeled GNDP, VDDP in the figure. The power pads GNDP and VDDP are disposed between the output pads for the transmitters. Thus, the power pads GNDP and VPPD for the phase locked loop  406 - 0  are disposed between the output pads for serial channel D[ 0 ] and the output pads for serial channel D[ 1 ]. Each local clock multiplier power domain includes a power trace and a ground trace confined to the phase locked loop circuitry. Thus, phase locked loop  406 - 0  includes a power trace  414 V and a ground trace  414 G. Likewise, phase locked loop  406 - 7  in  FIG. 10B  includes a power trace  415 V and a ground trace  415 G connected to the local power pad VDDP and ground pad GNDP respectively. 
     As may be seen from  FIGS. 10A and 10B , the substrate  400  may include 12 pairs of transmitters having individual clock multipliers disposed in individual power domains between the transmitters in the pair. 
     The circuits in each power domain, in addition to having separate power traces, and separate power and ground pads, are isolated electrically in the substrate from one another. This isolation may be implemented using deep n-well technology, for example, in which the active regions of the circuitry are implemented within one or more doped wells separated from the bulk substrate by a deep n-well. The deep n-well may be biased using a selected power supply voltage so that it remains reverse biased relative to the substrate and relative to the active region during operation. In this manner, noise produced in the ground and power circuitry is not coupled directly into the circuitry of other power domains via the substrate. 
     Some or all of the power domains may be isolated using other technologies, such as by formation of the active regions in semiconductor layers deposited over layers of insulating material, so the insulating material electrically separates the active regions from the substrate. 
       FIG. 11  illustrates two transmitter pairs taken from the layout of  FIGS. 10A and 10B .  FIG. 11  illustrates a transmitter pair  405 - 2 ,  405 - 3 , with an individual phase locked loop  406 - 1  in between. Also, transmitter pair  405 - 8 ,  405 - 9  is shown, with an individual phase locked loop  406 - 4  in between. The phase locked loops have individual power pads and power traces. Thus, phase locked loop  406 - 1  includes the VDDP power pad connected to the power trace  417 V, and the GNDP ground pad connected to the ground trace  417 G. Phase locked loop  406 - 4  includes the VDDP power pad connected to the power trace  418 V, and the GNDP ground pad connected to the ground trace  418 G. 
     The pattern of power pads and output pads includes a set of 14 pads for each transmitter pair disposed around the substrate in a repeating sequence. The order from right to left for the set of 14 pads for the transmitter pair including transmitters  405 - 2  and  405 - 3 , and phase locked loop  406 - 1  of the pads in this example is as follows: transmitter power domain ground pad GNDO, output pad pair D[ 2 ], transmitter power domain power pad VDDO, digital power domain power pad VDDD, digital power domain ground pad GNDD, local clock multiplier power pad VDDP, local clock multiplier ground pad GNDP, transmitter power domain ground pad GNDO, output pad pair D[ 3 ], transmitter power domain power pad VDDO, digital power domain power pad VDDD and digital power domain ground pad GNDD. 
     As mentioned above, in other embodiments one clock multiplier may be associated with only one transmitter, or with groups of more than two transmitters, as suits a particular need. One clock multiplier may be configured to provide a transmit clock to one or more transmitters, where the one or more transmitters are in a separate power domain than the power domain of the clock multiplier. A configuration in transmitter pairs can provide an advantage in that the length of a transmission line carrying the transmit clock from the clock multiplier to the adjacent transmitters in the transmitter pair may be configured locally and have short and uniform transmission paths, without traversing circuitry other than the clock multiplier and the connect transmitter. 
       FIG. 12  and  FIG. 13  illustrate an electrostatic discharge ESD protection configuration for the plurality of power domains on a device such as that shown in  FIGS. 10A and 10B . In each of  FIGS. 12 and 13 , the power and ground traces  411 V,  411 G for the analog power domain, the power and ground traces  412 V,  412 G for the digital power domain, and the power and ground traces  413 V,  413 G for the transmitter power domain are shown using the reference numbers of  FIGS. 10A and 10B . 
     Referring to  FIG. 12 , an ESD protection array for protecting the ground and power pads and ground and power traces of each of the major power traces on the device is shown. The ESD circuits used include circuit  900  between the power and ground power pads (VDDA, GNDA) and traces ( 411 V,  411 G) for the analog power domain, circuits  901 ,  902  between the power and ground power pads (VDDD, GNDD) and traces ( 412 V,  412 G) for the digital power domain, and circuits  903 ,  904 ,  905  for the power and ground power pads (VDDO, GNDO) and traces ( 413 V,  413 G) in the transmitter power domain. The ESD circuits  900 - 905  may be implemented for example, utilizing reversed-biased diode configurations in a grounded gate NMOS (ggNMOS) technology connected between the power and the ground traces in the corresponding power domain. Other ESD circuit implementations may be used as well. 
     Referring to  FIG. 13 , an ESD protection array is illustrated for protecting the local clock multiplier power domains, and for cascading protection among the power traces of different power domains. In  FIG. 13 , the power trace  414 V for an individual phase locked loop, and the ground trace  414 G for the individual phase locked loop are shown. An ESD protection circuit  925  is connected between traces  414 G and  414 V and the corresponding pads VDDP, GNDP. Circuit  925  may be implemented using a reversed biased diode configuration in a grounded gate NMOS technology as well. 
     ESD protection circuits  910 ,  911 ,  912 , and  913  are connected on one terminal to the power trace  411 V connected to VDDA for the analog power domain. Circuit  910  is connected on its opposing terminal to the power trace  412 V connected to VDDD in the digital power domain. Circuit  911  is connected on its opposing terminal to the power trace  413 V connected to VDDO in the transmitter power domain. 
     A similar pattern may be distributed around the periphery of the chip, so that circuit  912  is connected on its opposing terminal to the power trace  413 V connected to VDDO in the transmitter power domain. Circuit  913  may be connected on its opposing terminal to the power trace  412 V connected to VDDD in the digital power domain. 
     A second tier of ESD circuits includes circuits  914 ,  915 ,  916  and  917 , connected on one terminal to the analog ground trace  411 G which may be connected to the analog ground pad GNDA for the analog power domain. Circuit  914  may be connected on its opposing terminal to the ground trace  412 G connected to GNDD in the digital power domain. Circuit  915  may be connected on its opposing terminal to the ground trace  413 G connected to GNDO in the transmitter power domain. A similar pattern may be distributed around the chip, so that circuit  916  is connected on its opposing terminal to the ground trace  413 G connected to GNDO in the transmitter power domain. Circuit  917  is connected on its opposing terminal to the ground trace  412 G connected to GNDD in the digital power domain. 
     The third tier of ESD circuits includes circuits  918  and  919 . Circuits  918 ,  919  each include one terminal coupled to the power trace  412 V that is connected to VDDD in the digital power domain. Both of the circuits  918 ,  919  have opposing terminals connected to the power trace  413 V that is connected to VDDO in the transmitter power domain. 
     A fourth tier of ESD circuits includes circuits  920  and  921 . Circuits  920  and  921  are both connected between the ground trace  412 G that is connected to GNDD in the digital power domain, and the ground trace  413 G that is connected to GNDO in the transmitter power domain. 
     Individual clock multiplier power domains are also protected by ESD circuits  926 ,  927  and  930 . ESD circuits  926  and  927  have one terminal connected to the power trace  414 V that is connected to the VDDP for the local clock multiplier power domain. Circuit  926  has an opposing terminal connected to the trace  411 V that is connected to VDDA in the analog power domain. Circuit  927  has an opposing terminal connected to ground trace  413 G in the transmitter power domain. 
     The ESD circuit  930  has one terminal connected to the ground trace  414 G that is connected to GNDP of the local clock multiplier power domain, and an opposing terminal connected to the ground trace  413 G that is connected to GNDO in the transmitter power domain. 
     Circuit  927  which is connected between a ground trace and a power trace, may be implemented using a reverse biased diode configuration in a grounded gate NMOS technology, consistent with the example given above for protection between power and ground traces. 
     The circuits which protect between power traces in different power domains, including the circuits  910  through  913 ,  918 ,  919  and  926 , may be implemented using a reverse biased diode configuration in a grounded gate NMOS technology, consistent with the example given above for protection between power and ground traces. 
     Circuits which protect between ground traces in different power domains, including the circuits  914  through  917 ,  920 ,  921  and  930  may be implemented using back-to-back parallel diodes. 
       FIG. 14  is a schematic illustration showing components of the peripheral circuitry on an integrated circuit sensor like that shown in  FIG. 4 , which may be parts of the column bias/select circuits  402 L/ 402 U, analog-to-digital converter circuits  403 L/ 403 U, and register arrays  404 L/ 404 U. The circuit includes, schematically, a reference cell  1005  and an ISFET  1006  having drain terminals coupled to the analog power supply potential VDDA. The source terminals in the simplified illustration of the reference cell  1005  and the ISFET  1006  are coupled to matched current sources  1007 ,  1008  respectively. The current source  1007  coupled to the reference cell  1005  includes cascode transistor  1014  in series with a current source transistor  1015  which are biased using reference voltages V 3  and V 4 , respectively. A node at the drain terminal of the cascode transistor  1014  is connected to the input of a comparator  1020 . The current source  1008  coupled to the ISFET  1006  includes cascode transistor  1016  and current source transistor  1017  in series, which are biased using reference voltages V 3  and V 4 , respectively. A node at the drain terminal of the cascode transistor  1016  is connected to the input of a comparator  1021 . 
     A ramp voltage may be applied to second inputs of the comparators  1020 ,  1021 . The ramp voltage may be generated by a digital-to-analog converter (DAC)  1010  and a ramp driver  1009 . The ramp driver  1009  includes transistors  1011 ,  1012 , and  1013  in series between the digital power supply voltage VDDD and ground. The gate of the transistor  1011  may be controlled by the output of the digital-to-analog converter  1010 . Transistor  1012  may be configured as a cascode transistor controlled by the bias voltage V 1 . The transistor  1013  may be a current source transistor controlled by the bias voltage V 2 . A node at the drain of transistor  1012  is connected to the second inputs of the comparators  1020  and  1021 . A capacitor  1030  may be coupled to the node to stabilize the ramping voltage. Digital-to-analog converter  1010  may be digitally controlled to produce a ramp voltage connected to the gate of the transistor  1011 , having a desired ramp shape, timed with the frame sequences. Also, the output of the digital-to-analog converter  1010  may be coupled to a switch  1032 . The switch  1032  may be operated to connect the output of the digital-to-analog converter  1010  to a capacitor  1031  during a selected part of the ramp cycle. The voltage on the capacitor  1031  may be used as the reference voltage on the gate of the reference cells  1005 . 
     The outputs of the comparators  1020  and  1021  are coupled to respective latches  1022 ,  1023 . Latches  1022 ,  1023  are reset at the beginning of each cycle, and are operated to capture a transition on the output of the respective comparators  1020 ,  1021 . The outputs of the latches are coupled to corresponding registers  1024 ,  1025 . A gray code counter  1026  is connected to the registers  1024 ,  1025 , and may be cycled in time with the ramp voltage. 
     The comparators  1020 ,  1021  transition when the ramp voltage on the capacitor  1030  matches the voltage produced by the reference cell  1005  or ISFET  1006  to which they are coupled. When the latches  1022 ,  1023  capture the transition of the comparators  1020 ,  1021 , the output of a gray code counter  1026  may be captured in a corresponding register  1024 ,  1025 . The gray code values captured in the registers  1024 ,  1025  are provided as a stream of data to the transmitters. 
     Using the circuitry shown, streams of data are provided to the transmitters which represents pixels from the sensor array. 
     The circuitry illustrated in  FIG. 14 , with the exception of the reference cell  1005  and ISFET  1006  and their corresponding current sources  1007 ,  1008 , may be implemented in the digital power domain, and thereby isolated from the analog power domain, the transmitter power domain, and the clock multiplier power domains. 
     The dynamics of the incorporation event for DNA sequencing using ISFETs may occur ar approximately 15 frames per second. The sensor may run at a higher frame rate for oversampling in order to improve the signal-to-noise ratio. The capture window of interest can typically be a few seconds. Due to reagent flow producing skewed reactions times across the chip, active and idle intervals may be adjusted to achieve good results. In one example, 7 seconds of data may be captured in a 20 second cycle time. Chips that produce larger amounts of data may have longer cycle times in order to process the data. Energy may be wasted in the sensor during the period where data is not captured. 
     Power management may be used to reduce the power consumption during the idle periods. 
     In addition, power management can enable paused or reduced flow cycles during the wash cycles, where reagents are conserved. Power states and flow rates may be tuned to optimize reagent use and the temperature of the chip under variable flow. 
     Power management in the fluidic systems as described herein may be constrained by a variety of factors. For example, typically reagents are continuously flowing in order to keep the chip temperature stable. The chip interfaces to the fluidics through capacitive coupling. Changes in signal level, pixel timing and readout sequence (control) affect the electro fluidics, which can change the parameters of the capacitive coupling and destabilize the readout process. 
     The chip interfaces to a reader board through high speed links. The high speed links are initially synchronized as a transmitter-receiver pair and may lock. Changing the transmission protocol or the readout parameters may invalidate the initial pairing. Link loss takes time to recover, and may make high data rate readout impossible. 
     In some embodiments, the power management may be provided with no disruption to the electro fluidics. However, the pixel array may create capacitive feedback into the fluidics and may be signal dependent. 
     In some embodiments, power management and thermal management may be enabled using a simple interface. The system may be busy with processing data and may require a simple interaction to initiate a capture sequence. Thus, synchronous power states may be used, in which the duty cycle between active and sleep states may be consistent or managed to avoid variation in average heat dissipation. 
     One example of a power management parameter is an effective number of bits for the output digital-to-analog converter. Converting an analog to a digital signal may require a certain amount of energy based on the noise floor and dynamic range of the signal, the conversion rate (MegaSamples per second), conversion cycle time (e.g. frame rate) architecture (not a fundamental noise source), and the output drive power from the ADC. As shown in  FIG. 4 , and similar systems, the electro fluidics may not see the data conversion. Also, the data transmitted from the chip may use scrambling (i.e. in the transmitter serializer block) and the data link integrity may be unaware of the quality of the data conversion. Also, the ADC sequence may be synchronous to the row time/frame time. 
     During the capture sequence, the ADC can run with a 12-bit effective number of bits (ENOB). During the idle period, the ADC can run at an 8-bit (or N-bit) ENOB. A 4-bit ENOB can save up to 16 times in power consumption at the ADC and yet nothing in the system may be aware of the change in ENOB (no listeners). Thus, during the idle mode, ADC may be configured by control parameters to operate at lower ENOB values. 
     Circuitry illustrated in  FIG. 14  may be operated in active and idle modes to adjust power consumption and to control temperature during active and idle periods using a set of parameters on a frame by frame basis. The circuitry can implement for example, a proportional-integral-derivative PID control algorithm to manage power consumption, and temperature of the chip. 
     The controllable parameters for circuitry in the digital power domain include parameters for the digital-to-analog converter “DAC PARAMETER(S)” such as a DAC head parking address, gray code counter parameters “GC PARAMETER(S)” such as a gray code parking address, ramp driver parameters V 1 , V 2  which set of comparator power levels, the timing of the signal VSW controlling the switch  1032 , in this example. In other circuitry implementations, other types of parameters may be controlled on a frame-by-frame basis. Likewise, in the illustrated circuitry other parameters may be controlled to manage power consumption by the peripheral circuitry. Other parameters include for example, bias levels for the comparators  1020 ,  1021  and bias levels for the latches  1022 ,  1023 . 
     In addition, parameters controlling the current sources  1007 ,  1008  may be used to control power consumption on a frame-by-frame basis of circuitry in the analog power domain. These parameters include the bias voltages V 3  and V 4  in the illustrated example which set pixel column bias levels. The control of the current sources  1007 ,  1008  is optional. In preferred examples, the current sources  1007 ,  1008  are controlled so as to avoid destabilizing the interfacial fluid dynamics and electrical operation of the sensor array. For example, the parameters may be changed slowly or only in small amounts, and transitions from the idle mode to the active mode may be executed well in advance of the readout of active data in order to maintain consistent electrofluidics from frame to frame. 
     Other parameters can include latch control states, configured to prevent latch transitions in the low power mode. The latch control states may be specified to set latch output values during the idle modes, in a pattern that facilitates maintenance of the transmission links and low transition counts (and thus reduced power consumption) for the data paths to the transmitters. 
     Embodiments are envisioned in which any one of the frame power parameters, or more than one of the frame power parameters, described above are adjusted in idle mode to reduce power consumption. 
       FIG. 15  is a simplified illustration of control logic in the sequencer on a chip like that shown in  FIG. 4 . The control logic includes a set of frame power parameter registers  1050  and a sequencer control logic block  1040 . The sequencer control logic block  1040  is connected to an input signal provided by a pin  1041  on the integrated circuit, at which a control signal may be applied to activate sample sequences, in some embodiments. Alternatively, the sequencer control logic block  1040  may be activated by control signals generated on-chip or written to a register set using the SPI interface or other management interface on the device. Sequencer control logic block  1040  also receives input from the temperature sensors on the chip on line  1042 , and produces timing signals for addressing to capture a frame of pixels on line  1043 . Sequencer control logic  1040  produces frame settings (represented by line  1044 ) for the active and idle modes in response to the value stored in the frame power parameter registers  1050 , such as discussed above in connection with  FIG. 14 . 
     A representative set of parameters can include the following: 
     
       
         
           
               
               
             
               
                   
               
             
            
               
                 reg.set(‘lp_trigger’, 0) 
                 #control setting to trigger the start of a capture. 
               
               
                 reg.set(‘lp_mode.en’, 0) 
                 #control setting to enable low power time sequencing. 
               
               
                 reg.set(‘lp_mode.force’, 0) 
                 #control setting force the low power phase to run 
               
               
                   
                 continuously. 
               
               
                 reg.set(‘lp_frame_count’, 0) 
                 #control setting to set duration of active period specified by 
               
               
                   
                 frame count. 
               
               
                 reg.set(‘lp_status’, 0) 
                 #status parameter indicating low power state. 
               
               
                 reg.set(‘lp_bias.enI_vbn_cb’, 0) 
                 #vbn_cb : bias current sink for cb pixel column line (e.g. 
               
               
                   
                 V4). 
               
               
                 reg.set(‘lp_bias.enI_vbn_ct’, 0) 
                 #vbn_ct : bias current sink for ct pixel column line (e.g. V4). 
               
               
                 reg.set(‘lp_bias.enI_vbn_rmp’, 0) 
                 #vbn_rmp : bias current sink for ramp bias (e.g. V2). 
               
               
                 reg.set(‘lp_bias.enI_vbp_cmp’, 0) 
                 #vbp_cmp : bias current source for 1st stage comparator bias 
               
               
                   
                 (two stage comparator). 
               
               
                 reg.set(‘lp_bias.enI_vbp_smp’, 0) 
                 #vbp_smp : bias current source for 2nd stage comparator 
               
               
                   
                 bias (two stage comparator). 
               
               
                 reg.set(‘lp_bias.mask’, 0) 
                 #mask for {vbp_smp,vbp_cmp,vbn_rmp,vbn_ct,vbn_cb} 
               
               
                   
                 (selecting circuit parameters to apply in low-power mode). 
               
               
                 reg.set(‘lp_ctrl.latch_rst0’, 0) 
                 #low power state for latch_rst0. 
               
               
                 reg.set(‘lp_ctrl.latch_set0’, 1) 
                 #low power state for latch_set0. 
               
               
                 reg.set(‘lp_ctrl.latch_rst1’, 1) 
                 #low power state for latch_rst1. 
               
               
                 reg.set(‘lp_ctrl.latch_set1’, 0) 
                 #low power state for latch_set1. 
               
               
                 reg.set(‘lp_ctrl.mask’, 0) 
                 #mask for {gray code, dacbuf_en_sf, dac_head, latch} 
               
               
                   
                 selecting control settings to apply in low-power mode). 
               
               
                 reg.set(‘mode.stall_pin’, 1) 
                 #set to 0 to configure the stall pin (e.g. pin 1041) as an 
               
               
                   
                 lp_trigger. 
               
               
                 reg.set(‘gray fixed’, 0) 
                 #fixed value for gray code input (e.g. constant input to 
               
               
                   
                 register set). 
               
               
                   
               
            
           
         
       
     
     In example processes, the chip may be notified of the start of a capture sequence by activation of a pin input, by register write or otherwise. The chip runs active for a certain period, which may be fixed, programmable or dynamically adjusted, and then transitions to a low-power state. The low-power state is configurable by selecting parameters and levels of control values to control. The active and idle periods may be programmable, and may be set by the chip in a manner that may not be synchronous with the reactant flows and wash cycles. 
     The state of the chip may be embedded in the metadata in the register set, or may be in the data streams transmitted to the reader. The state of the chip may be available over the SPI interface or other management bus interface in some embodiments. The system may capture data during the active cycles of the chip, and may continue transmitting data not based on the sensors, during idle cycles to maintain the communication links. The start and stop times for the active and idle cycles may be determined based on a number of timing parameters, including a number of clock cycles, a number of row cycles or a number of frame cycles. Also and/or optionally using the number of frame cycles to determine start and stop times may be useful because second order effects may be captured at frame intervals rather than during some random time during capture. For fine timing control, a combination of timing parameters may be utilized. 
       FIG. 16  is a simplified flowchart for control of a flow cycle using a system like that shown in  FIG. 1  utilizing power management techniques as described herein. The process includes initializing the fluidics for delivering reactant and wash fluids, and initializing the transmitters on the chip to establish communication links with a reader ( 1600 ). Also, the process includes loading frame power parameters on the chip, or in the system so that they may be provided to the chip as needed ( 1601 ). The frame power parameters in this example provide power settings for each frame sensing cycle, including active mode frame settings and idle mode frame settings. The process includes setting the active frame count “N” and the idle frame count “M” for a particular flow cycle including a reactant flow and a wash flow. The system then controls the fluidics in a cycle that includes flowing a reactant for an active interval ( 1603 ) and flowing a wash for an idle interval ( 1604 ). In parallel with the fluidics, the sensor chip may be controlled to execute active frame sequencing for “N” frames ( 1605 ), followed by executing idle frame sequencing for “M” frames ( 1606 ). The process includes determining whether a control temperature may be within an operating range ( 1607 ). If not, then the active frame count “N” and the idle frame count “M” are changed ( 1608 ). After, in the illustrated flow diagram, the active frame count “N” and the idle frame count “M” are changed, or if the control temperature is within the operating range at block ( 1607 ), then the process determines whether the flow sequence is complete ( 1609 ). If the sequence is not complete, then the process loops back to block  1602 , and performs a following flow cycle. If the sequence is complete, then the process is ended ( 1610 ). 
       FIG. 17  is a simplified flowchart for an alternative control process for a flow cycle using a system like that shown in  FIG. 1  utilizing power management techniques as described herein. The process includes initializing the fluidics for delivering reactant and wash fluids, and initializing the transmitters on the chip to establish communication links with a reader ( 1700 ). Also, the process includes loading frame power parameters on the chip, or in the system so that they may be provided to the chip as needed ( 1701 ). The frame power parameters in this example provide power settings for each frame sensing cycle, including active mode frame settings and idle mode frame settings. The process includes setting the active frame count “N” and the idle frame count “M” for a particular flow cycle including a reactant flow and a wash flow. The system then controls the fluidics in a cycle that includes flowing a reactant for an active interval at an active flow rate ( 1703 ) and flowing a wash for an idle interval at a wash flow rate which may be less than the active flow rate ( 1704 ). Next, for transition to a next flow cycle, the wash flow rate may be increased to the active flow rate in order to stabilize the electric fluidics in advance of the active sensing cycles ( 1705 ). In parallel with the fluidics, the sensor chip may be controlled to execute active frame sequencing for “N” frames ( 1706 ), followed by executing idle frame sequencing for “X” frames ( 1707 ). Next, for transition to a next mode, a transition frame sequencing may be executed for “M-X” frames ( 1708 ). The process includes determining whether a control temperature is within an operating range ( 1709 ). If not, then the active frame count “N” and the idle frame count “M” are changed ( 1710 ). In some embodiments, the transition parameter “M-X” may be changed as well. If the active frame count “N” and the idle frame count “M” are changed, or if the control temperature is within the operating range at block ( 1709 ), then the process determines whether the flow sequence is complete ( 1711 ). If the sequence is not complete, then the process loops back to block  1702 , and performs a following flow cycle. If the sequence is complete, then the process is ended ( 1712 ). In this manner, transitional control is provided so that the electro fluidics and thermodynamics of the interface region may be stabilized in advance of switching to the active mode, even if the electro fluidics and thermodynamics may be changed during the idle mode, due to, for example, the reduced flow rate during the wash flow and changes in biasing levels in the sensor array that may occur during the idle frame sequencing. It may be desirable however that the electric fluidics and thermodynamics remain stable throughout a flow cycle, so that the transitional flow and transition frame sequencing may not be necessary. 
       FIGS. 16 and 17  are flowcharts illustrating logic executed by the sequencing system. The logic may be implemented using on-chip circuitry such as state machines, processors programmed using computer programs stored in memory accessible to the computer systems and executable by the processors, by dedicated logic hardware, including field programmable integrated circuits, and by combinations of dedicated logic hardware and computer programs. As with all flowcharts herein, it will be appreciated that many of the steps may be combined, performed in parallel or performed in a different sequence without affecting the functions achieved. In some cases, as the reader will appreciate, a rearrangement of steps will achieve the same results only if certain other changes are made as well. In other cases, as the reader will appreciate, a rearrangement of steps will achieve the same results only if certain conditions are satisfied. Furthermore, it will be appreciated that the flow charts herein show only steps that are pertinent to an understanding of the invention, and it will be understood that numerous additional steps for accomplishing other functions may be performed before, after and between those shown. 
     A method for operating a sensor array is described therefore, which includes applying a sequence of alternating flows of reactant solutions during active intervals and flows of wash solutions during wash intervals; applying bias arrangements to the sensor array to produce sensor data; producing streams of sensor data from the sensor array using peripheral circuitry having an active mode and an idle mode; and switching the peripheral circuitry between the active mode and the idle mode to control power consumption. The method can include using feedback responsive to temperature of the array to switch between the active mode and the idle mode to maintain the temperature within an operating range. 
     The peripheral circuitry can include conversion circuitry, responsive to configuration parameters, to convert the sensor data into a plurality of streams of digital data; a plurality of transmitters configured to receive corresponding streams of data from the plurality of streams from the conversion circuitry and transmit the data to corresponding receivers; and a sequencer which operates the bias circuitry to produce frames of sensor data at a frame rate, operates the conversion circuitry to convert the sensor data at the frame rate. In support of this configuration, the method can include applying a first set of one or more configuration parameters to the conversion circuitry in the active mode, and a second set of one or more configuration parameters to the conversion circuitry in the idle mode and maintaining transmission of data using the plurality of transmitters during the idle mode. The second set of configuration parameters may be adapted to preserve operational readiness and to reduce power consumption. Also, the method can include applying a third set of one or more configuration parameters to the bias circuitry in the active mode, and a fourth set of one or more configuration parameters to the bias circuitry in the idle mode. 
     Also, the method can include maintaining communication links with remote receivers during the active mode and the idle mode. 
     In one example, the method includes operating in the active mode for a first number of frames in a time interval overlapping with the active interval and for a second number of frames in the idle mode in a time interval overlapping with an immediately following idle interval; and adjusting the first and second numbers to control power consumption. 
     The system can provide an average flow rate during the active interval which may be greater than an average flow rate during the idle interval, the reduced flow rates being offset by idle mode power settings on the sensor array, and reducing consumption of reaction fluids. 
     In examples in which the peripheral circuitry includes an analog-to-digital ADC converter, the method can include setting a first effective number of bits parameter for the analog-to-digital converter in the active mode, and a second effective number of bits parameter, lower than the first, for the analog-to-digital converter in the idle mode. 
     In examples in which the peripheral circuitry includes a digital-to-analog DAC converter to produce a reference ramp signal, the method can include setting a DAC parking address parameter for the digital-to-analog converter in the idle mode. 
     In examples in which the peripheral circuitry includes a gray code counter to produce a digital count value, the method can include setting a gray code counter parking address parameter in the idle mode. 
     In examples in which the peripheral circuitry includes a comparator, the method can include setting a first comparator power level parameter in the active mode, and a second comparator power level parameter, lower than the first, in the idle mode. 
     In examples in which the peripheral circuitry includes a latch for each column of the array, the method can include setting a latch state in the idle mode. 
     The technology described herein provides for tunable ADC power consumption for bandwidth and thermal noise, mode selectable gray code capture for continuous or pulse mode sampling, and automatic power management configured for N-number of frame sequences. 
     Power management may be used to reduce the power consumption during the idle periods. 
     In addition, power management can enable paused flow cycles where reagents are conserved. Typically reagents are continuously flowing in order to keep the chip temperature stable. Power states and flow rates may be tuned to optimize reagent use and the temperature of the chip under variable flow. 
     A configuration for implementing an array of high-speed transmitters on an integrated circuit is described. Features of the implementation include local high-speed transmit clock generation, and provide a clock multiplier such as a phase locked loop, between each pair of transmitters which provides a local high speed transmit clock over short connectors to the adjacent transmitters. Another feature of the implementation includes low speed reference clock distribution, allowing for the distribution of the reference clock to the transmitter array at low power and low frequency, minimizing disturbance of the transmitters from reference clock noise. Also, features of the implementation include power supply separation, providing individual power domains for the clock multiplier circuitry, separate from the transmitters, from digital circuitry and from analog circuitry on the device minimizing disturbance of the transmitter from noise arising in other portions of the chip which operate on separate clocks and introduce additional noise sources. Power consumption and temperature may be managed by controlling power utilized in the digital domain only, while maintaining operational readiness of the circuitry in the analog domain, transmitter domain and clock multiplier domain. 
     In some embodiments, an integrated circuit is described which includes a substrate having a data source, with peripheral circuitry on the substrate coupled to the data source to produce a stream of digital data. To support high speed transmission of the data stream, a clock multiplier may be provided on the substrate which produces a transmit clock. The clock multiplier may be disposed in an individual power domain on the substrate to reduce noise and improve quality of the transmit clock. A transmitter may be on the substrate and configured to receive the stream of data from the data source. The transmitter is connected to transmit the stream of data on an output pad using the transmit clock. The transmitter may be disposed in a transmitter power domain on the substrate separate from the individual power domain of the clock multiplier. In other aspects of the technology, the data source and the peripheral circuitry are disposed in a power domain or power domains separate from the individual power domain. The integrated circuit can include a plurality of transmitters on the substrate connected to, and thereby sharing, the clock multiplier. In other aspects, a plurality of clock multipliers may be disposed on the substrate which produce respective local transmit clocks, in which each clock multiplier may be disposed in an individual power domain on the substrate. In this aspect, a plurality of transmitters on the subset are arranged in sets having one or more members, and wherein each set may be placed in proximity to, and connected to, one clock multiplier in the plurality of the clock multipliers. Power consumption and temperature may be managed dynamically without disturbing operational readiness using the techniques described herein. 
     While the claimed invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.