Patent Publication Number: US-9419623-B2

Title: Semiconductor component and an operating method for a protective circuit against light attacks

Description:
PRIORITY CLAIM 
     This application is a continuation of U.S. patent application Ser. No. 13/450,907 filed on 19 Apr. 2012, which in turn claims priority to German Patent Application No. 10 2011 018 450.3 filed on 21 Apr. 2011, the content of both of said applications incorporated herein by reference in their entirety. 
    
    
     TECHNICAL FIELD 
     The present invention relates to a semiconductor component and an operating method for a protective circuit against light attacks. 
     BACKGROUND 
     Semiconductor components comprising a logic circuit, such as are used in a CPU, for example, are often constructed with CMOS (complementary metal oxide semiconductor) gates. CMOS gates contain p-channel transistors arranged in an n-conductively doped well. The n-type wells are fixedly connected to the highest electrical potential provided (supply voltage V DD ). The pn junction between the n-conductively doped well and the source-drain regions becomes non-conducting. Defined transistor properties are obtained as a result. Moreover, this arrangement prevents the well potential from falling below a value at which a so-called latch-up occurs that is to say a transition of the semiconductor component to a low-impedance state that can lead to an electrical short circuit and thus to thermal destruction of the component. 
     One problem in the case of semiconductor components for security-critical applications is also required safeguarding against light attacks by which functional disturbances of the component can be brought about or an undesirable external analysis of the circuit construction is intended to be made possible. There are already a number of proposals as to how a semiconductor component can be protected against light attacks. 
     In the case of light attacks, a distinction is made between global light attacks and local light attacks. In the case of global light attacks, the chip is exposed to light or ionizing radiation over a large area. This attack is not restricted to delimited regions. It is known that global light attacks can be detected by light sensors arranged in a scattered manner on the chip. 
     Local light attacks are locally highly delimited attacks on a semiconductor component and can be carried out by means of a laser, for example. By means of local light attacks, it is possible to change individual bits in sensitive regions. They generally require the chip housing to be opened and the circuit structure to be exposed. Local light attacks can be detected by means of a dual CPU (central processing unit) arrangement, for example. 
     US 2011/0043245 A1 discloses a semiconductor component including a parasitic activation structure for protection against light attacks, wherein the energy limit value for activating the parasitic structure is lower than the energy limit value for changing the status of a storage flip-flop of the semiconductor component. In this case, a current limiting circuit limits the current flowing in the semiconductor component. 
     The known measures are not only very complex and make the component considerably more expensive, but, as in the case of the dual CPU arrangement, may also result in an increase in the current consumption/demand and the area requirement. The additional area requirement of the components of a protective circuit readily exceeds the area available for the entire integrated circuit. 
     SUMMARY 
     Therefore, it is an object of the present invention to provide a semiconductor component having a cost-effective construction and improved protective properties against local light attacks. 
     The semiconductor component according to the invention comprises a semiconductor substrate, wherein a doped well having a well terminal and a transistor structure having at least one potential terminal are formed in the semiconductor substrate. A supply potential, for example V DD , can be present at the potential terminal. The transistor structure has a parasitic thyristor, which is partly arranged in the doped well, wherein the potential terminal and the well terminal are connected via a resistor. 
     According to the invention, unlike what is customary in the prior art, the well is not fixedly connected to the highest electrical potential, rather a resistor is arranged between the well terminal and the potential terminal. As a result of this arrangement, the highest electrical potential, for example the positive supply voltage V DD , can be present at the potential terminal, while, in the case of a light attack, a lower potential, reduced by the voltage drop across the resistor, is present at the well terminal. 
     Instead of the positive supply voltage V DD  a negative supply voltage V SS  can also be present at the potential terminal. 
     The sensitivity of the parasitic thyristor towards a light attack can be adjusted by means of the value of the resistor. The parasitic thyristor can be adjusted such that it triggers under specific conditions and thus initiates a latch-up or a latch-up preliminary stage. As a result of the high currents which flow in the case of a latch-up or a latch-up preliminary stage, data stored on the semiconductor component can be destroyed or erased. Furthermore, the function of the semiconductor component can be destroyed or the semiconductor component can be thermally damaged or destroyed. 
     The resistor can be embodied in such a way that a light attack triggers the parasitic thyristor before a functional disturbance for external analysis of the circuit construction or for reading out data stored on the semiconductor component is possible. The resistor advantageously has a value of between 50 and 500 ohms. 
     The resistor can be an adjustable resistor, wherein the resistor can be adjusted after the end of the manufacturing process. The sensitivity of the parasitic thyristor to light attacks can be changed by the adjustment of the resistor. 
     The resistor can be a polysilicon resistor or a metal resistor, which can be arranged outside the semiconductor substrate. 
     In a further exemplary embodiment, the resistor is formed in the semiconductor substrate, for example in a doped well and/or in a diffusion region. 
     The resistor can also be a regulable resistor, wherein the semiconductor component is embodied such that the resistor can be regulated in a manner dependent on a physical variable measured in the semiconductor component. By way of example, temperature and/or other ambient conditions and/or an ageing-dictated change of the semiconductor component can be taken into account by means of a regulable resistor. 
     The semiconductor component can furthermore comprise a temperature sensor, wherein the semiconductor component is embodied such that it can regulate the resistor in a manner dependent on a temperature measured by the temperature sensor. 
     The semiconductor component can be a semiconductor component constructed using CMOS technology. The semiconductor component can also comprise a plurality of transistor structures each having a parasitic thyristor. 
     In a further exemplary embodiment, the resistor can be connected to the potential terminals of a plurality of transistor structures. In this case, the transistor structures can be a part or the totality of a logic circuit constructed generally with CMOS transistors. 
     In one exemplary embodiment, the doped well is an n-type well and the electrical potential present at the potential terminal is a positive supply voltage V DD , wherein the potential terminal and the well terminal are connected via the resistor, which can be arranged outside the doped well. However, the doped well can also be a p-type well and the electrical potential present at the potential terminal can be a negative supply voltage V SS . 
     Furthermore, the semiconductor component can comprise a current limiting circuit, wherein the current limiting circuit can be designed such that the semiconductor component is not damaged when the parasitic thyristor is triggered. Even though the semiconductor component is not damaged by the current limiting, the function of the semiconductor component can be disturbed in such a way that it is no longer possible to read out data stored on the semiconductor component and/or to conduct an external analysis of the circuit construction. 
     Furthermore, the semiconductor component can comprise an alarm circuit, wherein the alarm circuit is designed such that a function of the semiconductor component is blocked at least temporarily when the parasitic thyristor is triggered. The semiconductor component can be blocked such that an undesirable external analysis of the semiconductor component or the data content thereof is prevented. Such function can be enabled by a reset, for example. 
     The semiconductor component according to the invention achieves area-covering protection against light attacks both from the front side and from the rear side (substrate) of the semiconductor component. No further measures are required within the circuit to be protected. The entire circuit integrated into the chip, in particular a complete logic circuit, can be protected. The sensitivity can be preset by the choice of the resistor or by the layer construction of the semiconductor component. 
     The arrangement of the resistor between the potential terminal and the well terminal and utilization of the latch-up effect make it possible to effectively protect the semiconductor component against light and radiation attacks, virtually without increasing the overall area requirement. Moreover, the arrangement of the resistor between the well terminal and the potential terminal, in contrast to other, known solutions against light attacks, consumes no additional current. Even the subsequent implementation of such a resistor into existing logic circuits, designs and IP blocks is possible without high outlay. 
     An operating method for a protective circuit and a semiconductor component enables the semiconductor component to be effectively protected against light attacks. In this case, the semiconductor component comprises a semiconductor substrate having a doped well having a well terminal and a transistor structure arranged at least partly in the well and having at least one potential terminal and having a parasitic thyristor, wherein the potential terminal and the well terminal are connected by a resistor. Upon exposure to light or radiation, the parasitic thyristor turns on, as a result of which it is no longer possible to read out data stored on the semiconductor component, or the semiconductor component is functionally disturbed or damaged or destroyed. 
     Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Exemplary embodiments of the semiconductor component are described in more detail below with reference to the accompanying Figures. The drawings serve to illustrate the basic principle, so that only aspects necessary for understanding the basic principle are illustrated. The drawings are not to scale. In the drawings the same reference characters denote like features. 
         FIG. 1  shows an exemplary embodiment of a semiconductor component in cross section. 
         FIG. 2  shows an exemplary embodiment of a logic circuit. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows an exemplary embodiment of a semiconductor component  100  using CMOS technology in cross section. The semiconductor component  100  comprises an n-channel field effect transistor  34  and a p-channel field effect transistor  32 . The two field effect transistors  32 ,  34  together form a transistor structure  30 . While the n-channel field effect transistor  34  is arranged in a p-doped semiconductor substrate  20  of the semiconductor component  100 , the p-channel field effect transistor  32  is arranged in an n-doped well  10  formed in the semiconductor substrate  20 . The n-doped well  10  has a well terminal  5  with an n + -doped diffusion region. The p-channel field effect transistor  32  has a potential terminal  35 . A supply voltage V DD  is present at the potential terminal  35 . The supply voltage V DD  of a semiconductor component  100  can be approximately 1.5 V. 
     The layer construction of the individual dopings of the transistor structure  30  results in a parasitic npn bipolar transistor  44  and a parasitic pnp bipolar transistor  42 . The npn bipolar transistor  44  and the pnp bipolar transistor  42  correspond to a parasitic thyristor  40  in terms of their mutual interconnection. 
     The parasitic thyristor  40  has a lateral npn bipolar transistor  44  and a vertical pnp bipolar transistor  42 . The source-drain regions of the p-channel field effect transistor  32  are the emitter and the n-doped well  10  is the base of the resultant pnp bipolar transistor  42 , while the p-doped semiconductor substrate  20  constitutes the collector. Correspondingly, the source-drain regions of the n-channel field effect transistor  34 , the p-doped semiconductor substrate  20  and the n-doped well  10  form the emitter, base and collector of the npn bipolar transistor  44 . The potential terminal  35  and the well terminal  5  are connected to one another via a resistor R. The resistor R, as illustrated schematically in this exemplary embodiment is arranged outside the semiconductor substrate  20  or outside the doped well  10 . The sensitivity of the parasitic thyristor  40  towards a light attack can be adjusted by the value of the resistor R. The parasitic thyristor  40  can be adjusted such that it triggers under specific conditions and thus initiates a latch-up or a latch-up preliminary stage. 
     The npn bipolar transistor  44  and the pnp bipolar transistor  42  are turned off under normal operating conditions. If, on account of external conditions, for example as a result of a light attack, a voltage drop occurs at one of the two base-emitter diodes of one of the two parasitic bipolar transistors  42 ,  44 , then a collector current flows through this bipolar transistor. This collector current produces a voltage drop across the complementary bipolar transistor. If, in the latter as well, the base-emitter voltage is exceeded, both bipolar transistors  42 ,  44  are now in the on-state. The consequence is a positive feedback between the two bipolar transistors  42 ,  44 , thus giving rise to a permanent low-impedance connection between the supply voltage V DD  and ground V SS . This low-impedance connection can then be disconnected only by removal of the supply voltage V DD . 
     If the current supply of one of the two parasitic bipolar transistors  42 ,  44  is high enough, then the arrangement remains in an active state even after the disappearance of the currents injected, for example by a light attack. This state is called latch-up or latching state. The latch-up leads to a malfunction of the semiconductor component  100  since the outputs of the field effect transistors  32 ,  34  are at a fixed potential and no longer react to changes at the gate terminal. As a result of the high currents flowing during a latch-up or a latch-up preliminary stage, data stored on the semiconductor component  100  can be erased or altered. In the case of very high currents, thermal destruction or melting of the feeding metal tracks or underlying structures of the semiconductor component  100  can occur. Even if the semiconductor component  100  is not damaged by the latch-up or its preliminary stage, the function of the semiconductor component  100  can be lastingly disturbed. 
       FIG. 2  shows a plurality of semiconductor components  100  arranged in the form of a logic circuit  200 . In this exemplary embodiment, the resistor R is an adjustable or regulable resistor. The resistor R is arranged between the potential terminals  35  of a plurality of transistor structures  30 - 1 ,  30 - 2 , . . .  30 - n  and the well terminals  5  of the transistor structures  30 - 1 ,  30 - 2 , . . .  30 - n . In this case, each transistor structure  30 - 1 ,  30 - 2 , . . .  30 - n  has a parasitic thyristor. In this case, the transistor structures  30 - 1 ,  30 - 2 , . . .  30 - n  are part of a synthesized logic/logic circuit. 
     A positive supply voltage V DD  is present at the potential terminals  35  and a voltage V WELL  is present at the well terminals  5 . In the normal operating state, the voltage V WELL  at the well terminals  5  is equal to the positive supply voltage V DD . In the case of a light attack, the supply voltage V DD  remains constant, while the voltage V WELL  decreases by the voltage drop across the resistor R. 
     The sensitivity of the parasitic thyristors of the transistor structures  30 - 1 ,  30 - 2 , . . .  30 - n  towards a light attack can be adjusted by the value of the resistor R. The parasitic thyristors can be adjusted such that they trigger under specific conditions and thus initiate a latch-up or a latch-up preliminary stage. As a result of the high currents which flow during a latch-up or a latch-up preliminary stage, data stored on the semiconductor components  100  can be destroyed or erased. Furthermore, the function of the semiconductor components  100  can be disturbed or the semiconductor components  100  can be thermally damaged or destroyed. 
     The construction of the logic circuit  200  with the semiconductor components  100  according to the invention makes it possible to effectively protect the entire logic circuit  200  against light or radiation attacks, without additional design measures, sensors or area expenditure. 
     If the resistor R is an adjustable resistor, the resistor R can be adjusted after the end of the manufacturing process. By way of example, the sensitivity of the parasitic thyristors to light attacks can be adjusted by the adjustment of the resistor R. 
     If the resistor R is a regulable resistor, then the resistor R can be embodied such that the resistor R can be regulated in a manner dependent on a physical variable measured in the semiconductor component  100 . By way of example, temperature and/or other ambient conditions and/or an ageing dictated change of the semiconductor component  100  can be taken into account by a regulable resistor R. 
     Spatially relative terms such as “under”, “below”, “lower”, “over”, “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first”, “second”, and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description. 
     As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. 
     With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.