Patent Publication Number: US-11652083-B2

Title: Processed stacked dies

Description:
PRIORITY CLAIM AND CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 15/960,179, filed Apr. 23, 2018, which claims the benefit under 35 U.S.C. § 119(e)(1) of U.S. Provisional Application No. 62/504,834, filed May 11, 2017, both of which are hereby incorporated by reference in their entirety. 
    
    
     FIELD 
     The following description relates to processing of integrated circuits (“ICs”). More particularly, the following description relates to techniques for processing singulated dies in preparation for bonding. 
     BACKGROUND 
     Dies may be stacked in a three-dimensional arrangement as part of various microelectronic packaging schemes. This can include stacking a layer of one or more dies on a larger base die, stacking multiple dies in a vertical arrangement, and various combinations of both. Dies may also be stacked on wafers or wafers may be stacked on other wafers prior to singulation. The dies or wafers may be bonded in a stacked arrangement using various bonding techniques, including using direct dielectric bonding, non-adhesive techniques, such as a ZiBond® direct bonding technique or a DBI® hybrid bonding technique, both available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), a subsidiary of Xperi Corp (see for example, U.S. Pat. Nos. 6,864,585 and 7,485,968, which are incorporated herein in their entirety). 
     When bonding stacked dies using a direct bonding technique, it is desirable that the surfaces of the dies to be bonded be extremely flat and smooth. For instance, the surfaces should have a very low variance in surface topology, such that the surfaces can be closely mated to form a lasting bond. It is also desirable that the surfaces be clean and free from impurities, particles, and/or other residue. The presence of undesirable particles for instance, can cause the bond to be defective or unreliable at the location of the particles. For instance, some particles and residues remaining on bonding surfaces can result in voids at the bonding interfaces between the stacked dies. If the voids are substantially smaller than the metallic electrical interconnect size, they may be acceptable. However, particles that cause bonding defects in sizes that are close to or exceed the electrical interconnect size often cannot be tolerated, since they can negatively impact the electrical conductivity of the interconnect. 
     Since semiconductor wafers (e.g., silicon wafers, for example) are brittle, it is common for defects or particles to be created at the edges of dies as they are singulated. As an example, silicon can crack during cutting, forming loose particles. Mechanical cutting or sawing often leaves a rough edge and can also leave particles or shards of silicon on or near the edges of cut dies. In addition, mechanical saw dicing typically transfers materials from the dicing sheet to the side wall and edge of the singulated dies. Laser cutting can also leave particles on the surface or edge of the dies. Various processes can be used to clean the surfaces of the dies after cutting. However, the processes can often leave some particles at the periphery of the die or at an edge wall of the die. Even when die surfaces are polished, shards may still be present on the edges or sidewalls of the dies. The loose particles and shards left behind can be problematic to forming reliable bonds. Additionally, these loose or partially loose particles may re-contaminate the bonding surfaces of interest or the bonding tool, etc. in subsequent operations. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The detailed description is set forth with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items. 
       For this discussion, the devices and systems illustrated in the figures are shown as having a multiplicity of components. Various implementations of devices and/or systems, as described herein, may include fewer components and remain within the scope of the disclosure. Alternately, other implementations of devices and/or systems may include additional components, or various combinations of the described components, and remain within the scope of the disclosure. 
         FIG.  1 (A)  is a profile view showing defects on a top surface of a die, according to an embodiment.  FIG.  1 (B)  is a profile view showing a section of bonded dies with defects.  FIG.  1 (C)  is a profile view showing a section of bonded dies without defects. 
         FIG.  2    is a graphical flow diagram illustrating an example process of processing stacked dies, according to an embodiment. 
         FIG.  3    is a graphical flow diagram illustrating an example process of processing stacked dies, according to another embodiment. 
         FIG.  4    is a graphical flow diagram illustrating an example process of processing stacked dies, according to a further embodiment. 
         FIG.  5 (A)  is a profile view of a die with a recessed oxide region, according to an embodiment.  FIG.  5 (B)  is a magnified view of the profile view of the die with a recessed oxide region.  FIG.  5 (C)  is an example of a bonded die arrangement having a recessed oxide region. 
         FIG.  6    is a flow diagram illustrating example processes for processing stacked dies, according to an embodiment. 
     
    
    
     SUMMARY 
     Various embodiments and techniques can be used to process singulated dies in preparation for bonding. The embodiments comprise techniques to remedy the accumulation of defects found on dies, and includes removing, dissolving or etching particles at the edges of dies to provide a smooth bonding surface. The dies may be comprised of a semiconductor or a non-semiconductor material. Semiconductor materials may, for example, comprise direct band gap or indirect band gap semiconductors and their combinations thereof. Non-semiconductor materials may comprise, for example, a dielectric material for example, glass, ceramic, glass ceramics, silicon carbide, silicon oxycarbides, silicon nitrides or silicon oxynitrides, diamond, silicon oxide, or the like, or combinations thereof. 
     A microelectronic system can include at least a first microelectronic component comprising a base semiconductor layer and a dielectric layer, the dielectric layer having a substantially planar surface. Additionally, a second microelectronic component may be directly bonded without adhesive to the dielectric layer of the first microelectronic component, the dielectric layer having an undercut at a periphery of the dielectric layer, such that an area of the dielectric layer is less than an area of a footprint of the first and/or second microelectronic components. Alternatively, the second microelectronic component may comprise at least a second base semiconductor layer and a second dielectric layer, the second dielectric layer having a substantially planar surface. Additionally, the second dielectric layer may be directly bonded without adhesive to the first dielectric layer, at the first and second substantially planar surfaces, the first base semiconductor layer and the second base semiconductor layer having an undercut at a periphery of the first and second base semiconductor layers, respectively, such that an area of a footprint of the first base semiconductor layer and an area of a footprint of the second base semiconductor layer is less than an area of the first and/or second dielectric layers. 
     In a first embodiment, an undercut at a periphery of the base semiconductor layer of the first microelectronic component and/or the second microelectronic component may correspond to an undercut at the periphery of the dielectric layer of the first microelectronic component and/or the second microelectronic component. 
     In a second embodiment, the second microelectronic component may include at least a base semiconductor layer and a dielectric layer with a substantially planar surface, the dielectric layer of the first microelectronic component being directly bonded to the dielectric layer of the second microelectronic component, and the dielectric layer of the second microelectronic component having an undercut at a periphery of the dielectric layer of the second microelectronic component, such that an area of the dielectric layer of the second microelectronic component is less than the area of the footprint of the first and/or second microelectronic components. 
     A method for forming a microelectronic system can include singulating a plurality of semiconductor die components from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die components. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface. 
     In a third embodiment, the particles and shards of material may be removed by etching the edges of the plurality of semiconductor die components. The edges of the plurality of semiconductor die components may be etched while the plurality of semiconductor die components are on a dicing carrier (such as a dicing sheet, dicing tape, etc.). Additionally, the edges of the plurality of semiconductor die components may be etched using a chemical etchant. In an implementation, the chemical etchant can comprise hydrofluoric acid and nitric acid with Benzotriazole (BTA) or other chemicals that inhibit Cu dissolution in the etchant. Further, the edges of the plurality of semiconductor die components may be etched using a plasma etch. Additionally, the edges of the plurality of semiconductor die components may be etched to reduce a thickness of the plurality of semiconductor die components such that a space is created at one or more of the edges of each of the plurality of semiconductor die components. The semiconductor die components may include an oxide layer as the substantially planar surface, and the etching may include removing at least a portion of the oxide layer at the edges of the plurality of semiconductor die components. Still yet, the substantially planar surface of the plurality of semiconductor die components may be etched. The substantially planar surface may be etched to a preselected depth or for a preselected duration. 
     In a fourth embodiment, a protective coating may be applied to the substantially planar surface of the plurality of semiconductor die components prior to etching to protect the substantially planar surface from the etchant. 
     In a fifth embodiment, the plurality of semiconductor die components may be heated after singulating to cause the protective coating to recede from a periphery of the plurality of semiconductor die components. Additionally, the periphery of the plurality of semiconductor die components may be etched to a preselected depth. Further, the plurality of semiconductor die components may include a dielectric layer over a base semiconductor layer. Additionally, the periphery of the plurality of semiconductor die components may be etched to remove the dielectric layer and expose the base semiconductor layer at the periphery of the plurality of semiconductor die components. 
     In a sixth embodiment, the one or more of the plurality of semiconductor die components may be bonded by either a direct bonding technique without adhesive or a metal to metal diffusion bond. 
     In a seventh embodiment, particles and shards of material may be removed from a sidewall of the plurality of semiconductor die components, wherein the particles and shards are removed from the sidewall by etching the sidewall of the plurality of semiconductor die components. 
     In one embodiment, after a singulation step, particles and shards of material may be removed from a sidewall of a die by means of ultrasonic or megasonic radiation in one or more an alkaline fluids. Following the particle removal, the sidewall of the die may be further etched to remove portions of the sidewall and portions of a planar dielectric layer of the die. 
     Some of the disclosed processes may be illustrated using block flow diagrams, including graphical flow diagrams and/or textual flow diagrams. The order in which the disclosed processes are described is not intended to be construed as a limitation, and any number of the described process blocks can be combined in any order to implement the processes, or alternate processes. Additionally, individual blocks may be deleted from the processes without departing from the spirit and scope of the subject matter described herein. Furthermore, the disclosed processes can be implemented in any suitable manufacturing or processing apparatus or system, along with any hardware, software, firmware, or a combination thereof, without departing from the scope of the subject matter described herein. 
     Implementations are explained in more detail below using a plurality of examples. Although various implementations and examples are discussed here and below, further implementations and examples may be possible by combining the features and elements of individual implementations and examples. 
     DETAILED DESCRIPTION 
     Overview 
     Various embodiments and techniques can be used to process singulated dies in preparation for bonding. The embodiments comprise techniques to remedy the accumulation of particles found on dies, including particles created during the singulation of the dies, and includes removing, dissolving or etching shards at the edges of dies to provide a smooth bonding surface. 
       FIG.  1 (A)  is a profile view showing defects on a top surface of a die, according to an embodiment. As shown, a first die  102  is shown without any defects. In contrast, a second die  104  is shown with defects  106 . Of course, it is to be appreciated that defects  106  may occur on any surface, sidewall, and/or edge of the first die  102  and/or second die  104 . 
     The first die  102  and/or the second die  104  may be singulated from and/or removed from wafers, such as GaAs, diamond coated substrates, silicon carbide, silicon oxide, Silicon Nitride, silicon wafers, Lithium Niobate, Lithium Tantalate, flat panels, glasses, ceramics, circuit boards, packages, an interposer, structures with or without an embedded metallic layer, conductive interconnects  108 , device or devices, etc. In one embodiment, defects  106  may include particles and/or shards and may result from die cutting, dicing, and/or singulating the first die  102  and/or the second die  104 . For example, mechanical cutting (i.e. sawing) of the first die  102  and/or the second die  104  may cause defects such as particles  106 , particularly at the edges and/or sidewalls. Additionally, when the first die  102  and/or the second die  104  is cut (even using a laser), the first die  102  and/or the second die  104  may crack and/or generate particles  106  (such as silicon oxide particles). Further, after polishing the first die  102  and/or the second die  104 , shards of particles  106  may still be present on the edges and/or sidewalls of the first die  102  and/or the second die  104 . 
       FIG.  1 (B)  is a profile view showing a section of bonded dies with defects such as particles  106 . As shown, with defects  106  present at a portion of the bonding surface of the second die  104 , the first die  102  cannot be fully bonded to the second die  104 . This is shown by the gap  110  (or void) found between the first die  102  and the second die  104 . This gap  110  may be intolerable if the integrity of the bond is compromised, or if the gap  110  is large enough to negatively impact the electrical conductivity of mating electrical interconnects  108  if present at the bonding surfaces of the dies  102  and  104 . As discussed above, although the defects  106  may be found on the bonding surface of the second die  104 , additional or other defects (such as particles) may be found along another surface and/or sidewall of the first die  102  and/or the second die  104 . 
       FIG.  1 (C)  is a profile view showing a section of intimately bonded dies without defects. As shown, the first die  102  is fully and completely bonded to the second die  104 . Any conductive interconnects  108  at the surfaces of the dies  102  and  104  are bonded as well, with reliable electrical conductivity between the interconnects  108 .  FIG.  1 (C)  shows the first die  102  and the second die  104  after each has been properly prepared for bonding. For example, the edges and sidewalls of the first die  102  and/or the second die  104  may be cleaned and etched to remove particles and shards of silicon. The edges of the first die  102  and/or the second die  104  may be etched with a dry (plasma) etch and/or wet (chemical) etch while the first die  102  and/or the second die  104  are still on a carrier (e.g., a dicing sheet or tape, grip ring, etc.) after singulation. A protective coating may be applied to the bonding surface of the first die  102  and/or the second die  104  to protect the surface during the singulation and etching. In one example, the surface and sidewalls of the first die  102  and/or the second die  104  may be etched, while, in another example, the etching may be limited to the sidewalls of the first die  102  and/or the second die  104 . It is noted that the interconnects  108  are shown simplistically and not to scale. For example, the interconnects  108  may comprise one or more layers that together form the interconnect  108 . Moreover, the interconnects  108  may extend partially or completely through either or both dies  102  and  104  or may even be provided only at or along the surface(s) of the dies  102  and  104  as a pattern of traces interconnecting devices within the die(s)  102  and  104 . 
     Example Embodiments 
       FIG.  2    illustrates an example process  200  of processing stacked dies, according to an embodiment. At (A), a substrate  202  (which may be a silicon wafer, for example) may include an bonding layer  204 , which may comprise an insulator or dielectric layer, such as an oxide, or a hybrid bonding layer, e.g., a combination of insulative material (such as oxide) and electrically conductive interconnect layers. This bonding layer  204  may be formed on one or both sides of the substrate  202 . Layer(s)  204  may be protected by a first protective layer  206  and/or a second protective layer  208 . Alternatively, the substrate  202  may be exposed and/or have any number of protective layers. 
     At (B), the substrate  202  may be singulated on a carrier  212 , into a plurality of singulated dies  210 . In one embodiment, the carrier  212  may include a processing sheet, a dicing sheet or tape, grip ring, etc. Additionally, the substrate  202  may be singulated using saw dicing, wet etch or dry etch or laser methods or combinations of thereof. In one embodiment, the singulated dies  210  may have a substantially planar surface. 
     At (C), the singulated dies  210  may be exposed to ultra-violet light (UV) (for example, to cure the adhesive layer on the tape used as a carrier  212  for the substrate  202 , to reduce the adhesion between the die  210  surface contacting the tape, or the like). Additionally, in one embodiment, the carrier  212  may be stretched while the singulated dies  210  are on the carrier  212 , in preparation for cleaning and further processing the singulated dies  210 . Further processing can include reducing the thickness of the singulated dies  210 , for example. 
     At (D), the singulated dies  210  may be cleaned and the sidewalls of the singulated dies  210  may be etched. For example, the cleaning may remove one or more protective layers, including the protective layer  206  and/or the protective layer  208 . In an embodiment, the etching may dissolve silicon oxide, silicon nitride, and/or silicon to eliminate the particles and/or shards. Chemical etchants  211 , including acids, may be used to etch the periphery of the surface of the dies  210 , including the bonding layer  204 , and may also be used to etch the sidewalls of the singulated dies  210 . In an example where the surface and/or sidewalls of the singulated dies  210  are etched (for silicon dies  210 , for instance), the etchant  211  may comprise a chemical mixture of hydrofluoric acid and a suitable oxidizing agent, for example nitric acid. In some applications, a wet etchant may be comprised of a mixture of buffered hydrofluoric acid and a suitable organic acid in combination with an oxidizing agent. In other applications, a suitable metal complexing agent may be added to the etching solution to protect the metals on the die  210  bonding surface from the etchant. In one example, a metal complexing or passivating agent may be comprised of molecules with triazole moieties, for example Benzotriazole (BTA), or the like. In one embodiment, the BTA may protect copper on the surface of the singulated dies  210  from corrosion or dissolution by the etching solution. 
     After etching the surface (and sidewalls) of the die  210  and stripping off the protective layer  206  and/or  208 , the complexing agent is cleaned off of the bonding surface of the die  210 . As an alternative to a wet etch, the sidewalls of the die  210  may also be cleaned using dry etch methods, including using plasma processing similar to processes used in etching silicon. After a dry sidewall etching step, the protective layer  206  can be stripped from the bonding surface of the sidewalls of the die  210 . Cleaning the protective layer  206  may also include cleaning any organic material residues resulting from the dry etching. In one embodiment, the organic residue on the side wall of the processed die  210  may be left intact. Strongly adhering side wall organic residue may minimize subsequent particles shedding from the die  210 . 
     Additionally, cleaning and/or further processing of the singulated dies  210  may occur on a spin fixture  214  (or the like). The chemical etchant  211  is sprayed onto the diced wafer surface and forms a thin layer over the top surface of the dies  210  and fills the gaps between the dies  210 . In one embodiment, etching the sidewalls of the singulated dies  210  may cause defects on the sidewalls of the dies  210  to be removed. 
     Optionally, in an embodiment, the sidewalls of the dies  210  may be selectively coated to coat to the sidewalls and any particles and/or shards that may be present on the sidewalls. For example, a selective coating  218  may be applied to the sidewalls, using a spin coating process, an electrocoating process, or the like. The particles and/or shards are coated to the sidewalls with the coating  218  to adhere the particles and/or shards to the sidewalls, preventing the particles and/or shards from contaminating other areas of the dies  210 , including the bonding surfaces of the dies  210 . In various embodiments, the coating layer  218  comprises a material such as a glass, a boron doped glass, a phosphorus doped glass, or the like, that adheres to the silicon of the sidewalls, and won&#39;t generally adhere to any other surfaces. 
     In various embodiments, the coating layer  218  comprises a layer that is approximately 50 nm or less, that traps the particles and shards to the sidewalls of the dies  210 , and prevents their shedding off the sidewalls. The coating layer  218  may be heat cured to the dies  210  for stabilization, for a predefined duration at a predefined temperature (e.g., approximately 80 degrees C., or the like). While the coating layer  218  can be added after cleaning the dies  210  as discussed, in various embodiments, the coating layer  218  may be deposited to the sidewalls at other steps in the process  200 . 
     At (E), the singulated dies  210  may undergo plasma processes (such as ashing, for example) to remove any residue of the protective layer  206 . At (F), the singulated dies  210  may be cleaned to remove any residues or particles of debris resulting from step (E). At (G), the singulated dies  210  (including one or both of the oxide layers  204 ) may be plasma-activated (surface activation) to prepare the singulated dies  210  for direct bonding. At (H), the plasma-activated singulated dies  210  may be cleaned. At (I), one or more of the singulated dies  210  may be bonded to a prepared surface of a second substrate  216 . In particular, a bonding layer  204  (e.g., an oxide or dielectric layer with or without conductive layers) of the singulated dies  210  may be bonded directly to the prepared surface of the second substrate  216 . In one embodiment, the singulated dies  210  (via the bonding layer  204 ) may be bonded to the second substrate  216  using a ZIBOND® direct bonding, or DBI® hybrid bonding, technique, or the like, wherein the singulated dies  210  are directly bonded (and, in some instances, electrically connected) to portions of the surface of the second substrate  216  without the use of adhesives. 
     In various implementations, the substrate  216  may comprise another prepared surface of a silicon wafer, GaAs, diamond coated substrate, silicon carbide, silicon oxide, Silicon Nitride, Lithium Niobate, Lithium Tantalate, flat panel, glass, ceramic, circuit board, package, an interposer, a structure with or without an embedded device or devices, and so forth. In one embodiment, the prepared substrate  216  comprises the surface of another die  210  or another bonded die  304 , as discussed further below. 
       FIG.  3    illustrates an example process  300  of processing stacked dies, according to an embodiment. As described hereinabove, steps (A)-(D) of process  300  function in a manner consistent with steps (A)-(D) of process  200 . This includes etching the surface and periphery of the dies  210  (in a same or separate process step) to remove particles and shards of silicon or oxide from the surface and periphery of the dies  210 . 
     Optionally, in an embodiment, the sidewalls of the dies  210  may be selectively coated to coat to the sidewalls and any particles and/or shards that may be present on the sidewalls, as described above. For example, a selective coating  218  may be applied to the sidewalls, using a spin coating process, an electrocoating process, or the like. The particles and/or shards are coated to the sidewalls with the coating  218  to adhere the particles and/or shards to the sidewalls, preventing the particles and/or shards from contaminating other areas of the dies  210 , including the bonding surfaces of the dies  210 . In various embodiments, the coating layer  218  comprises a material such as a glass, a boron doped glass, a phosphorus doped glass, or the like, that adheres to the silicon of the sidewalls, and won&#39;t generally adhere to any other surfaces. 
     In various embodiments, the coating layer  218  comprises a layer that is approximately 50 nm or less, that traps the particles and shards to the sidewalls of the dies  210 , and prevents their shedding off the sidewalls. The coating layer  218  may be heat cured to the dies  210  for stabilization, for a predefined duration at a predefined temperature (e.g., approximately 80 degrees C., or the like). While the coating layer  218  can be added after cleaning the dies  210  as discussed, in various embodiments, the coating layer  218  may be deposited to the sidewalls at other steps in the process  300 . 
     With continuing reference to process  300 , at (E), the singulated dies  210  may be transferred to a spin fixture  214  (or the like) and processed/cleaned while on a single carrier, such as the spin plate  214  or the like, for all of the described process steps (including singulation, in some embodiments). Alternately, the singulated dies  210  can be transferred between different carriers (such as spin plate  302 ) for one or more processes at each station. At (F), the singulated dies  210  may undergo plasma treatment to remove any residue of the protective layer  206  (in a similar manner to step (E) of process  200 ) while still on the spin plate  302 . 
     At (G), the singulated dies  210  may be cleaned to remove the residue resulting from the plasma process at (F). At (H), the singulated dies  210  may be plasma-activated (surface activation) to prepare the singulated dies  210  (including the bonding layer(s)  204 ) for direct bonding. At (I), the plasma-activated singulated dies  210  may be cleaned. 
     At (J), one or more of the singulated dies  210  may be bonded to the prepared surface of a second substrate  216 . In particular, a bonding layer  204  (e.g., an oxide or dielectric layer with or without conductive layers) may be bonded to the prepared surface of the second substrate  216 . In one embodiment, the singulated dies  210  (via the oxide layer  204 ) may be directly bonded to the second substrate  216  using a ZIBOND® direct bonding, or DBI® hybrid bonding, technique, or the like (e.g., without adhesive or an intervening layer). 
     At (K), one or more additional singulated dies  304 , prepared similarly to the singulated dies  210  (e.g., the dies  304  may also be singulated from the substrate  202 ), may be bonded to the exposed second surface of one or more of the singulated dies  210 , forming one or more die stacks. In particular, a bonding layer  306  (e.g., an oxide or dielectric layer with or without conductive layers) of the singulated dies  304  may be directly bonded to the second surface of the singulated dies  210 , which has also been prepared for bonding. Preparation for bonding can include one or more cleaning, surface planarizing, and plasma treating process steps as desired. Additionally, the second surface (including the periphery) of the dies  210  may also be etched to remove undesirable particles and shards, etc. 
     Additional singulated dies  304  may be added in like manner to form die stacks with a desired quantity of die layers. In some embodiments, the singulated dies  210  and the second substrate  216  may be thermally treated after bonding, with additional thermal treatment after each layer of the singulated dies  304  is added. Alternately, the singulated dies  210 , the singulated dies  304 , and the second substrate  216  are thermally treated once several or all layers of the stacked dies ( 210 ,  304 ) are in place and bonded. 
       FIG.  4    illustrates another example process  400  of processing stacked dies, according to an embodiment. At (A), a resist layer  402  is coated on the singulated dies  210 , which include a bonding layer  204  (e.g., an insulating or dielectric layer with or without conductive layers or structures) and a substrate region  202  (e.g., silicon). In an implementation, the resist layer  402  may be patterned, for example to expose the periphery of the singulated dies  210  while protecting the rest of the surface of the singulated dies  210 . In various embodiments, the singulated dies  210  may be singulated using dicing and/or scribing. 
     At (B), the exposed edges and sidewalls of the singulated dies  210  may be cleaned and etched, resulting in an undercut or recess at the periphery of the singulated dies  210 . For example, the rough-cut edges of the singulated dies  210  may be smoothed by the etching. Additionally, the periphery of the singulated dies  210  may be recessed to have a reduced overall thickness of the singulated dies  210  at the periphery, creating a space at the edges of the singulated dies  210 . For instance, the singulated dies  210  with the bonding layer  204  (e.g., dielectric, oxide, etc.) on the substrate  202  (e.g. silicon) may be etched to remove some of the oxide of the bonding layer  204  at the periphery of the singulated dies  210 , and in some cases, part of the silicon of the substrate  202  as well. The etching causes the dielectric oxide of the bonding layer  204  to recess back from the edge of the singulated dies  210 , exposing the silicon of the substrate  202  below in the recess. In one embodiment, the space formed by the recess may allow for some tolerance to the bonding surfaces during direct bonding, to improve the reliability of the direct bonding technique and to remove stress from the bond. 
     In one embodiment, the singulated dies  210  may be processed at a raised temperature (e.g., 120 degrees C.) such that the resist layer  402  disposed on the oxide layer  204  flows and pulls back from the edges of the singulated dies  210 . When the edges of the singulated dies  210  are etched, the exposed portion of the oxide layer  204  may be removed. Additionally, some of the silicon of the substrate  202  may additionally be removed, depending on the duration and the formulary used for the etching. For example, the longer the duration, the greater the amount of substrate  202  may be removed. In some cases, the dielectric oxide layer  204  may have a sloped profile as a result of the etching of the singulated dies  210 . This sloped profile may extend into the substrate  202  (e.g. silicon), if the etching is performed to a depth of the substrate  202 . 
     In some embodiments, the process of etching back the dielectric layer  204  may be performed using a lithographic method in combination with dry etching wet etching or both as needed. For example, the surface of the die  210  may be patterned, and unwanted portions of the dielectric layer  204  removed by dry etching methods, and any unwanted exposed conductive features removed by wet etch methods, for instance. In other applications, it may be preferable to remove unwanted dielectric and conductive portions in one operation. In one example, a wet etchant containing halide ions, for example, buffered hydrofluoric acid and formularies containing hydrogen peroxide or nitric acid (or the like) that can oxidize the conductive features, may be applied to the surface of the dies  210  to remove the unwanted dielectric and conductive features. After the removal of the unwanted dielectric and conductive features, a protective layer may be applied for singulation operations. 
     At (C), the resist layer  402  may be removed from the surface of the singulated dies  210 . Additionally, at (D), the singulated dies  210  may be cleaned. 
     At (E) and (F), the singulated dies  210  may be bonded to a second substrate  404  (such as another die  210  or  304 , the second substrate  216 , or the like) that has been prepared for bonding as discussed above. In one embodiment, the singulated dies  210  may be bonded to a prepared surface of the substrate  404  using a ZIBOND® or hybrid DBI® technique, or the like (e.g., without adhesive or an intervening layer). In the illustration of  FIG.  4    at (E) and (F), only the die  210  is shown with an oxide layer  204 . However, in some embodiments, both of the components to be bonded (e.g., the die  210 , die  304 , or the substrate  216 ) may include an oxide region (such as oxide layer  204 , for example) at the bonding surface. In other words, the components are bonded at respective oxide regions. In some applications, the dielectric or oxide layer  204  of the die  210  and the prepared surface of the substrate  202  may include conductive features (not shown). The dielectric portions of the prepared surface of the die  210  and the substrate  202  can be bonded initially at lower temperatures. Any conductive features can be joined at higher temperatures between 150 to 350° C. In other applications, the dielectric portion and conductive feature bonding are formed at the same temperature. 
     In an implementation shown at (E), as a result of the etching of step (D), the edges of the oxide layer  204  of the singulated dies  210  may include an undercut  408 . In the implementation, the singulated dies  210  may include an undercut  408  at a periphery of the singulated dies  210 , such that an area of the oxide layer  204  is less than an area of a footprint of the substrate  202  and/or the substrate  404 . Additionally, or alternately, in an implementation shown at (F), as a result of the etching of step (D), the edges of the substrate  202  and the substrate  404  may include an undercut  410 . In this implementation, the singulated dies  210  may include an undercut  410  at a periphery of the singulated dies  210 , such that an area of the oxide layer  204  is greater than an area of a footprint of the substrate  202  and/or the substrate  404 . In the implementations, substrate  202  and substrate  404  may correspond with a first and second bonded microelectronic components, respectively. 
     According to various embodiments, edge or sidewall etching techniques described herein may provide a reduction of the complexity and cost of direct bond processes for high volume manufacturing of the singulated dies  210 . Additionally, removal of dicing particles and shards from a periphery and/or edges of the singulated dies  210  may reduce process-related defects in wafer-to-wafer, die-to-wafer, die-to-die, and die-to-system packaging. Further, stress may be reduced in packaged singulated dies  210  stacked in three-dimensional arrangements by rounding the edges of the stacked singulated dies  210 . The techniques described herein may also result in fewer die processing steps, higher manufacturing through-put, and improved profit margin for ZiBond® and direct bond interconnect (DBI®) manufactured devices. Other advantages of the disclosed techniques will also be apparent to those having skill in the art. 
       FIG.  5 (A)  is a profile view of a portion of an example die  210  with a recessed bonding layer  204  (e.g., insulating or dielectric layer with or without conductive layers), according to an embodiment. Additionally,  FIG.  5 (B)  is a magnified view of the profile view of the die  210  with a recessed bonding layer  204  (e.g., oxide region). As shown, the die  210  may include the bonding layer  204  that is recessed back from the substrate  202 . The profile view of  FIG.  5 (B)  may correspond with the profile view shown in step (D) of  FIG.  4   , for example. Additionally,  FIG.  5 (B)  includes a recess on one side of the bonding layer  204 , however, as shown in step (D) of  FIG.  4    and at  FIG.  5 (C) , the recess may be also located on both (or other) sides of the bonding layer  204 . 
     In particular, the sloped profile  502  of the oxide layer  204  may extend into the substrate  202  due to etching (for example, as described with reference to step (D) of  FIG.  4   ). Additionally, the sloped profile  502  may provide clearance at the perimeter of the substrate  202  such that a close and intimate bond may be achieved between, for example, the singulated dies  210  and a prepared surface of the second substrate  216  (or the like), even in the presence of any particles at the perimeter of the substrate  202 . 
     For instance this is illustrated in  FIG.  5 (C) , wherein an example die  210  is shown bonded to another example die  210 ′, forming an example die stack or example microelectronic assembly  500  (or the like). As shown in the illustration of  FIG.  5 (C) , the bonding layer  204 , which includes an insulating or dielectric material such as oxide and may also include one or more conductive layers or structures  504 , is directly bonded to the bonding layer  204 ′, which also includes an insulating or dielectric material such as oxide and may also include one or more conductive layers or structures  504 ′. Conductive features  504  and  504 ′ may extend only into respective bonding layers  204  and  204 ′ or may extend partially or entirely through dies  210  and  210 ′. The recess at the bonding layer  204  and the recess at the bonding layer  204 ′ (if present) may form a gap  506  at the periphery of the assembly  500 , where the die  210  is bonded to the die  210 ′. In various embodiments, the gap  506  may be of such size that any particles  508  remaining in the gap  506  may not hinder the formation of a close and intimate bond between the bonding surfaces  204  and  204 ′, including close and electrically conductive reliable bonds between conductive structures  504  and  504 ′. In various embodiments, the gap  506  may be filled as desired, for instance with an encapsulant, a dielectric material, an underfill material, or the like. In other embodiments, the gap  506  may remain unfilled, or may be filled with other inert or active materials as desired. Similar profiles as shown in  FIGS.  5 (A) and  5 (B)  may be created on the backsides of dies  210  and  210 ′ and more than two dies may be stacked together. 
       FIG.  6    is a flow diagram  600  illustrating example processes for processing stacked dies, according to an embodiment. At  602 , the process includes singulating a plurality of semiconductor die components (such as the singulated dies  210  or the singulated dies  304 , for example) from a wafer component (such as the substrate  202 , for example). In an embodiment, each of the semiconductor die components has a substantially planar surface. In another embodiment, the process includes depositing a protective coating (such as the protective coating  206 , for example) over the substantially planar surface of the semiconductor die components (either before or after singulation). 
     In one embodiment, the process includes heating the plurality of semiconductor die components, after singulating, to cause the protective coating (such as the protective coating  206 ) to recede from a periphery of the plurality of semiconductor die components. Additionally, the periphery of the plurality of semiconductor die components and/or the substantially planar surface of the plurality of semiconductor die components may be etched to a preselected depth. 
     Alternatively, the plurality of semiconductor die components may include a dielectric layer over a base semiconductor layer. Additionally, the dielectric layer may have a substantially planar surface and as described above, the dielectric layer may include one or more conductive features. In one embodiment, the process includes etching the periphery of the plurality of semiconductor die components such that at least a portion of the dielectric layer is removed and the base semiconductor layer at the periphery of the plurality of semiconductor die components is exposed. 
     At  604 , the process includes removing the particles and shards of material from the edges the plurality of semiconductor die components. Alternatively, the particles and shards may be removed from the sidewalls of the plurality of semiconductor die components. In one embodiment, the particles and shards may be removed by etching the edges and/or sidewalls of the plurality of semiconductor die components. Optionally, the etching of the edges and/or sidewalls occurs while the plurality of semiconductor die components are on a dicing carrier. Additionally, the etching may use plasma etch and/or a chemical etchant comprising hydrofluoric acid and nitric acid with Benzotriazole (BTA). In an alternative implementation, a protective coating (such as the protective coating  206 ) may be applied to the substantially planar surface of the plurality of semiconductor die components to protect the substantially planar surface from an etchant. 
     At  606 , the process includes bonding the one or more of the plurality of semiconductor die components to a prepared bonding surface, via the substantially planar surface. For example, the bonding may occur by a direct bond using a ZIBOND® or DBI® bonding technique, or the like, without adhesive or an intervening layer. The bonding may include electrically coupling opposing conductive features at the bonding surfaces of the die(s) and the prepared bonding surface. 
     The disclosed processes described herein are illustrated using block flow diagrams. The order in which the disclosed processes are described is not intended to be construed as a limitation, and any number of the described process blocks can be combined in any order to implement the processes, or alternate processes. Additionally, individual blocks may be deleted from the processes without departing from the spirit and scope of the subject matter described herein. Furthermore, the disclosed processes can be implemented in any suitable manufacturing or processing apparatus or system, along with any hardware, software, firmware, or a combination thereof, without departing from the scope of the subject matter described herein. 
     Although various implementations and examples are discussed herein, further implementations and examples may be possible by combining the features and elements of individual implementations and examples. 
     CONCLUSION 
     Although the implementations of the disclosure have been described in language specific to structural features and/or methodological acts, it is to be understood that the implementations are not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as representative forms of implementing example devices and techniques. 
     Each claim of this document constitutes a separate embodiment, and embodiments that combine different claims and/or different embodiments are within the scope of the disclosure and will be apparent to those of ordinary skill in the art upon reviewing this disclosure.