Patent Publication Number: US-7715254-B2

Title: Data output circuit of semiconductor memory apparatus and method of controlling the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 11/646,351, filed Dec. 28, 2006, the subject matter of which application is incorporated herein by reference in its entirety. 
   This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2006-0030933 filed on Apr. 5, 2006, the entire contents of which are hereby incorporated by reference. 

   BACKGROUND 
   1. Technical Field 
   The present invention relates to a semiconductor memory apparatus, and more particularly, to a data output circuit for a semiconductor memory apparatus. 
   2. Related Art 
   A semiconductor memory apparatus according to the related art having the configuration shown in  FIG. 1  has first to third unit data output modes (hereinafter, referred to as an X32 mode, an X16 mode, and an X8 mode) in which the number of data bits output according to a one-time read command are 32, 16, and 8, respectively. 
   The semiconductor memory apparatus according to the related art shown in  FIG. 1  includes a memory bank  10 , a plurality of data lines GIO&lt; 0 &gt; to GIO&lt; 31 &gt;, a data output unit  20 , and a pad unit  30 . The memory bank  10  includes cell array  11  and a sense amplifier array  12  that includes a plurality of data bus sense amplifiers (hereinafter, simply referred to as sense amplifier), the plurality of data lines GIO&lt; 0 &gt; to GIO&lt; 31 &gt; corresponding to the respective sense amplifiers of the sense amplifier array  12  such that cell data inside the memory bank  10  corresponding to a row address and a column address is output to the outside of the memory bank  100 , the data output unit  20  stores or drives the data of the data lines GIO&lt; 0 &gt; to GIO&lt; 31 &gt; so as to be output to the outside of the semiconductor memory apparatus, and the pad unit  30  has thirty-two pads that output the data driven by the data output unit  20  to the outside of the semiconductor memory apparatus. 
   The plurality of data lines GIO&lt; 0 &gt; to GIO&lt; 31 &gt; correspond to the zero to thirty-first pads of the pad unit  30  through the data output unit  20 , respectively. 
   Further, all of the thirty-two pads are used when the semiconductor memory apparatus operates in the X32 mode, sixteen pads are used when the semiconductor memory apparatus operates in the X16 mode, and eight pads are used when the semiconductor memory apparatus operates in the X8 mode. Accordingly, the thirty-two pads may be divided into pads used only in the X32 mode, pads commonly used in both the X32 mode and the X16 mode, and pads commonly used in all of the X32 mode, the X16 mode, and the X8 mode, which is determined in advance when designing the semiconductor memory apparatus. 
   The sense amplifiers of the sense amplifier array  12  are disposed in a repeating pattern in the order of a sense amplifier DBSA_X 8 , a sense amplifier DBSA_X 32 , a sense amplifier DBSA_X 16 , and a sense amplifier DBSA_X 32 , as shown in  FIG. 1 . 
   The sense amplifier DBSA_X 8  operates in the X32 mode, the X16 mode, and the X8 mode, the sense amplifier DBSA_X 32  operates only in the X32 mode, and the sense amplifier DBSA_X 16  operates in both the X32 mode and the X16 mode. 
   When the semiconductor memory apparatus operates in the X32 mode, all of the sense amplifiers of the sense amplifier array  12  operate, and the data is outputted through the data lines GIO&lt; 0 &gt; to GIO&lt; 31 &gt; corresponding to the sense amplifiers. 
   When the semiconductor memory apparatus operates in the X16 mode, all of the sense amplifiers DBSA_X 8  and DBSA_X 16  of the sense amplifier array  12  operate, and the data is output through the data lines GIO&lt; 0 &gt;, GIO&lt; 2 &gt;, . . . , GIO&lt; 28 &gt;, GIO&lt; 29 &gt;, and GIO&lt; 30 &gt; corresponding to the sense amplifiers. 
   When the semiconductor memory apparatus operates in the X8 mode, all of the sense amplifiers DBSA_X 8  of the sense amplifier array  12  operate, and the data is output through the data lines GIO&lt; 0 &gt;, GIO&lt; 4 &gt;, . . . , and GIO&lt; 28 &gt; corresponding to the sense amplifiers. 
   However, the sense amplifiers that detect and amplify data in cells corresponding to the row address and the column address do not completely match with the sense amplifiers corresponding to the X32 mode, the X16 mode, and the X8 mode. 
   For example, when the semiconductor memory apparatus operates in the X8 mode, first bit data among eight-bit data needs to be output through the data line GIO&lt; 0 &gt;. 
   However, when one of the sense amplifiers that detects and amplifies data in cells corresponding to the row address and the column address is a sense amplifier DBSA_X 32  that is coupled to data buses Lio&lt; 1 &gt; and Liob&lt; 1 &gt; inside the memory bank, data cannot be output in a normal state. 
   For this reason, according to the related art as shown in  FIG. 1 , the local data bus lines ldb_X 16 &lt; 1 &gt;, ldb_X 16 &lt; 3 &gt;, and ldb_X 8 &lt;1:3&gt; are coupled to the sense amplifiers that are coupled to the GIO lines and used in respective modes including the X32 mode, the X16 mode, and the X8 mode, such that the data is transmitted to the sense amplifiers. 
   Accordingly, when the semiconductor memory apparatus operates in the X8 mode, even if the sense amplifier that senses and amplifies the data in the cells corresponding to the row address and the column address corresponds to any one of the sense amplifiers DBSA_X 8 , DBSA_X 32 , DBSA_X 16 , and DBSA_X 32 , the corresponding data is transmitted to the sense amplifier DBSA_X 8 , and the data can be output in a normal state. 
   By the same principle, even when the semiconductor memory apparatus operates in the X16 mode, data can be normally output to the sense amplifiers DBSA_X 8  and DBSA_X 16  by the local data bus lines ldb_X 16 &lt; 1 &gt; and ldb_X 16 &lt; 3 &gt;. 
   However, the semiconductor memory apparatus according to the related art that is used in each of the X32 mode, the X16 mode, and the X8 mode has the following problems. 
   First, in order to transmit the data among the sense amplifiers used in the respective X32, X16, and X8 modes, the local data bus lines are coupled to the sense amplifiers. As a result, a layout area is increased, and it becomes difficult to design a circuit. This problem may become intensified as a memory capacity is increased. 
   Second, since it takes time for the data to be transmitted through the local data bus lines coupled among the sense amplifiers; a data output time is increased. 
   SUMMARY 
   An embodiment of the present invention provides a data output circuit for a semiconductor memory apparatus that may be capable of reducing a layout area and simplifying a circuit design. 
   Another embodiment of the present invention provides an output circuit for a semiconductor memory apparatus that may be capable of reducing a data output time. 
   An embodiment of the present invention provides a data output circuit for a semiconductor memory apparatus that may include; a first control signal generating unit configured to generate a first control signal according to a row address and a read command; and a data selecting unit configured to select data from a data line corresponding to a presently selected unit data output mode among data lines according to the first control signal or a second control signal, and output the data. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram illustrating the configuration of a data output circuit of a semiconductor memory apparatus according to the related art; 
       FIG. 2  is a block diagram illustrating the configuration of a data output circuit of a semiconductor memory apparatus according to an embodiment of the present invention; 
       FIG. 3  is a block diagram illustrating the internal configuration of the exemplary data output control unit of  FIG. 2 ; 
       FIG. 4  is a circuit diagram illustrating the configuration of the exemplary first control signal generating unit of  FIG. 3 ; 
       FIG. 5  is a circuit diagram illustrating the internal configuration of the exemplary first selecting unit of  FIG. 3 ; 
       FIG. 6  is a circuit diagram illustrating the internal configuration of the exemplary second selecting unit of  FIG. 3 ; 
       FIG. 7  is a circuit diagram illustrating the internal configuration of the exemplary third selecting unit of  FIG. 3 ; and 
       FIG. 8  is an exemplary data table illustrating an address specification of a semiconductor memory apparatus. 
   

   DESCRIPTION OF EXEMPLARY EMBODIMENTS 
   Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. 
   As shown in  FIG. 2 , a data output circuit of a semiconductor memory apparatus according to an embodiment of the invention may include a memory bank  100 , a plurality of data lines GIO&lt; 0 &gt; to GIO&lt; 31 &gt;, a pad unit  500 , a data output control unit  300 , and a data output unit  400 . The memory bank  100  may include cell array  110  and a sense amplifier array  120  that may include a plurality of data bus sense amplifiers (hereinafter, simply referred to as sense amplifier). The plurality of data lines GIO&lt; 0 &gt; to GIO&lt; 31 &gt; may correspond to the respective sense amplifiers of the sense amplifier array  120  such that cell data inside the memory bank  100  corresponding to a row address and a column address may be output to the outside of the memory bank  100 . The pad unit  500  may include a plurality of pads in which pads are determined to be used for at least one of first to third unit data output modes (that is, an X32 mode, an X16 mode, and an X8 mode). The data output control unit  300  may output data from a data line among the plurality of data lines GIO&lt; 0 &gt; to GIO&lt; 31 &gt;, corresponding to a currently set unit data output mode according to a first control signal or a second control signal, to a data output unit  400 . The data output unit  400  may store and drive the data output by the data output unit  300  and output it to the pad unit  500  so it may be output to the outside of the semiconductor memory apparatus. 
   The plurality of data lines GIO&lt; 0 &gt; to GIO&lt; 31 &gt; may be commonly used in all memory banks and divided into a plurality of groups, each of which may have at least four data lines, and the number of used data lines may be determined for each of the X32 mode, the X16 mode, and the X8 mode in each group. For example, if referring to a first group GIO&lt;0:3&gt; among groups of all of the data lines shown in  FIG. 2 , all of the data lines of the first group GIO&lt;0:3&gt; are used in the X32 mode, one of either the data line GIO&lt; 0 &gt; or the data line GIO&lt; 1 &gt; and one of either the data line GIO&lt; 2 &gt; or the data line GIO&lt; 3 &gt; are used in the X16 mode, and any one of the data lines of the first group GIO&lt;0:3&gt; may be freely used in the X8 mode. This may be applicable to the other groups. 
   The first control signal may be a row address GAX_rd of a memory bank corresponding to a read command, and the second control signal may be a column address GAY_rd. 
   As shown in  FIG. 3 , the data output control unit  300  may include a first control signal generating unit  310  that may generate the row address GAX_rd using a row address BAX&lt;0:3&gt; stored for each memory bank; and a command recognition signal cast 12 &lt;0:3&gt; that may be enabled only when a read command is input for each memory bank, and a data selecting unit  320  that selects data from a data line corresponding to the currently set unit data output mode according to the row address GAX_rd or the column address GAY_rd, and may output the data to the data output unit  400 . 
   The data selecting unit  320  may include a first selecting unit  321  that may output, when a read/write classification signal wtrbt is at a level for a read operation and a signal X 32  for selecting the X32 mode is enabled, data from a data line coupled to the first selecting unit  321  to a signal line corresponding to a pad used in the X32 mode; a second selecting unit  322  that may output, when the read/write classification signal wtrbt is at a level for a read operation and one among signals X 32  and X 16  for selecting the X32 and X16 modes is enabled, data from a data line according to the row address GAX_rd among data lines coupled to the second selecting unit  322  to a signal line corresponding to a pad used in the X32 mode and the X16 mode; and a third selecting unit  323  that may output, when the read/write classification signal wtrbt is at a level for a read operation and one among signals for selecting the X32 mode, the X16 mode, and the X8 mode is enabled, data from a data line according to the row address GAX_rd and the column address GAY_rd among data lines coupled to the third selecting unit  323  to a signal line corresponding to a pad used in the X32 mode, the X16 mode, and the X8 mode. 
   As shown in  FIG. 4 , the first control signal generating unit  310  may include a plurality of first NAND gates ND 11  to ND 14 , each of which may receive one signal pair according to a sequence in the same memory bank among the row addresses BAX&lt;0:3&gt; and the command recognition signals cast 12 &lt;0:3&gt;, and a second NAND gate ND 15  that may receive the outputs of the plurality of first NAND gates ND 11  to ND 14  and output the row address GAX_rd. 
   As shown in  FIG. 5 , the first selecting unit  321  may include a first inverter IV 21  that may receive the read/write classification signal wtrbt, a NAND gate ND 21  that may receive the output of the first inverter IV 21  and the X32 mode selecting signal X 32 , a second inverter IV 22  that may receive the output of the NAND gate ND 21 , and a tri-state inverter TIV 21  that may output data from a data line GIO_X 32  coupled to the tri-state inverter TIV 21  according to the output of the NAND gate ND 21  and the output of the second inverter IV 22 . 
   As shown in  FIG. 6 , the second selecting unit  322  may include a first mode selecting unit  322 - 1  that may output, when a read/write classification signal wtrbt is at a level for a read operation and the X32 mode selecting signal X 32  is enabled, data from a data line GIO_X 32  coupled to the first mode selecting unit  322 - 1  to a signal line corresponding to a pad used in the X32 mode; and a second mode selecting unit  322 - 2  that may output, when the read/write classification signal wtrbt is at a level for a read operation and the X16 mode selecting signal X 16  is enabled, data from a data line according to the row address GAX_rd among a plurality of data lines GIO_X 16 &lt; 0 &gt; and GIO_X 16 &lt; 1 &gt; coupled to the second mode selecting unit  322 - 2  to a signal line corresponding to a pad used in the X16 mode. 
   As shown in  FIG. 6 , the first mode selecting unit  322 - 1  may include a first inverter IV 31  that may receive the read/write classification signal wtrbt, a NAND gate ND 31  that may receive the output of the first inverter IV 31  and the X32 mode selecting signal X 32 , a second inverter IV 32  that may receive the output of the first NAND gate ND 31 , and a tri-state inverter TIV 31  that may output data from a data line GIO_X 32  according to the output of the first NAND gate ND 31  and the output of the second inverter IV 32 . 
   As shown in  FIG. 6 , the second mode selecting unit  322 - 2  may include a third inverter IV 33  that may receive the row address GAX_rd; a second NAND gate ND 32  that may receive the output of the third inverter IV 33 , the read/write classification signal; and the X16 mode selecting signal, a fourth inverter IV 34  that may receive the output of the second NAND gate ND 32 ; a second tri-state inverter TIV 32  that may receive data from a data line GIO_X 16 &lt; 0 &gt; according to the output of the second NAND gate ND 32  and the output of the fourth inverter IV 34 ; a fifth inverter IV 35  that may receive the row address GAX_rd; a sixth inverter IV 36  that may receive the output of the fifth inverter IV 35 ; a third NAND gate ND 33  that may receive the output of the sixth inverter IV 36 , the read/write classification signal wtrbt, and the X16 mode selecting signal X 16 ; a seventh inverter IV 37  that may receive the output of the third NAND gate ND 33 , and a third tri-state inverter TIV 33  that may output data from a data line GIO_X 16 &lt; 1 &gt; according to the output of the third NAND gate ND 33  and the output of the seventh inverter IV 37 . 
   As shown in  FIG. 7 , the third selecting unit  323  may include a first mode selecting unit  323 - 1  that may output, when the read/write classification signal wtrbt is at a level for a read operation and the X32 mode selecting signal is enabled, data from a data line GIO_X 32  to a signal line corresponding to a pad used in the X32 mode; a second mode selecting unit  323 - 2  that may output, when the read/write classification signal wtrbt is at a level for a read operation and the X16 mode selecting signal X 16  is enabled, data from a data line according to the row address GAX_rd among a plurality of data lines GIO_X 16 &lt; 0 &gt; and GIO_X 16 &lt; 1 &gt; coupled to the second mode selecting unit  323 - 2  to a signal line corresponding to a pad used in the X16 mode; and a third mode selecting unit  323 - 3  that may output, when the read/write classification signal wtrbt is at a level for a read operation and the X8 mode selecting signal is enabled, data from a data line according to the row address GAX_rd and the column address GAY_rd among a plurality of data lines GIO_X 8 &lt;0:3&gt; coupled to the third mode selecting unit  323 - 3  to a signal line corresponding to a pad used in the X8 mode. 
   As shown in  FIG. 7 , the first mode selecting unit  323 - 1  may include a first inverter IV 41  that may receive the read/write classification signal wtrbt, a first NAND gate ND 41  that may receive the output of the first inverter IV 41  and the X32 mode selecting signal X 32 , a second inverter IV 42  that may receive the output of the first NAND gate ND 41 , and a tri-state inverter TIV 41  that may output data from a data line GIO_X 32  according to the output of the NAND gate ND 41  and the output of the second inverter IV 42 . 
   As shown in  FIG. 7 , the second mode selecting unit  323 - 2  may include a third inverter IV 43  that may receive the row address GAX_rd; a second NAND gate ND 42  that may receive the output of the third inverter IV 43 , the read/write discriminating signal wtrbt, and the X16 mode selecting signal X 16 ; a fourth inverter IV 44  that may receive the output of the second NAND gate ND 42 ; a second tri-state inverter TIV 42  that may output data from a data line GIO_X 16 &lt; 0 &gt; according to the output of the second NAND gate ND 42  and the output of the fourth inverter IV 44 ; a fifth inverter IV 45  that may receive the row address GAX_rd; a sixth inverter IV 46  that may receive the output of the fifth inverter IV 45 ; a third NAND gate ND 43  that may receive the output of the sixth inverter IV 46 , the read/write classification signal wtrbt, and the X16 mode selecting signal X 16 ; a seventh inverter IV 47  that may receive the output of the third NAND gate ND 43 ; and a third tri-state inverter TIV 43  that may output data from a data line GIO_X 16 &lt; 1 &gt; according to the output of the third NAND gate ND 43  and the output of the seventh inverter IV 47 . 
   As shown in  FIG. 7 , the third mode selecting unit  323 - 3  may include a fourth NAND gate ND 44  that may receive the row address GAX_rd and the column address GAY_rd; an eighth inverter IV 48  that may receive the output of the fourth NAND gate ND 44 ; a fifth NAND gate ND 45  that may receive the output of the eighth inverter IV 48 , the read/write discriminating signal wtrbt, and the X8 mode selecting signal X 8 ; a ninth inverter IV 49  that may receive the output of the fifth NAND gate ND 45 ; a fourth tri-state inverter TIV 44  that may output data from a data line GIO_X 8 &lt; 3 &gt; coupled to the fourth tri-state inverter TIV 44  according to the output of the fifth NAND gate ND 45  and the output of the ninth inverter IV 49 ; a tenth inverter IV 50  that may receive the row address GAX_rd; a sixth NAND gate ND 46  that may receive the output of the tenth inverter IV 50  and the column address GAY_rd; an eleventh inverter IV 51  that may receive the output of the sixth NAND gate ND 46 ; a seventh NAND gate ND 47  that may receive the output of the eleventh inverter IV 51 , the read/write classification signal wtrbt, and the X8 mode selecting signal X 8 ; a twelfth inverter IV 52  that may receive the output of the seventh NAND gate ND 47 ; a fifth tri-state inverter TIV 45  that may output data from a data line GIO_X 8 &lt; 2 &gt; coupled to the fifth tri-state inverter TIV 45  according to the output of the seventh NAND gate ND 47  and the output of the twelfth inverter IV 52 ; a thirteenth inverter IV 53  that may receive the column address GAY_rd; an eighth NAND gate ND 48  that may receive the row address GAX_rd and the output of the thirteenth inverter IV 53 ; a fourteenth inverter IV 54  that may receive the output of the eighth NAND gate ND 48 ; a ninth NAND gate ND 49  that may receive the output of the fourteenth inverter IV 54 , the read/write discriminating signal wtrbt, and the X8 mode selecting signal X 8 ; a fifteenth inverter IV 55  that may receive the output of the ninth NAND gate ND 49 ; a sixth tri-state inverter TIV 46  that may output data from a data line GIO_X 8 &lt; 1 &gt; coupled to the sixth tri-state inverter TIV 46  according to the output of the ninth NAND gate ND 49  and the output of the fifteenth inverter IV 55 ; a sixteenth inverter IV 56  that may receive the row address GAX_rd; a seventeenth inverter IV 57  that may receive the column address GAY_rd; a tenth NAND gate ND 50  that may receive the output of the sixteenth inverter IV 56  and the seventeenth inverter IV 57 ; an eighteenth inverter IV 58  that may receive the output of the tenth NAND gate ND 50 ; an eleventh NAND gate ND 51  that may receive the output of the eighteenth inverter IV 58 , the read/write classification signal wtrbt, and the X8 mode selecting signal X 8 ; a nineteenth inverter IV 59  that may receive the output of the eleventh NAND gate ND 51 ; and a seventh tri-state inverter TIV 47  that may output data from a data line GIO_X 8 &lt; 0 &gt; coupled to the seventh tri-state inverter TIV 47  according to the output of the eleventh NAND gate ND 51  and the output of the nineteenth inverter IV 59 . 
   In a device having the above-described configuration, the number of pads that are used in each of the X32 mode, the X16 mode, and the X8 mode can be freely determined. However, for convenience of description, it is assumed that among the thirty-two pads of the pad unit  500  of  FIG. 2 , the zero to seventh pads are used in the X8 mode, the zero to fifteenth pads are used in the X16 mode, and the zero to thirty-first pads are used in the X32 mode. 
   The first selecting unit  321  of  FIG. 5  may be coupled to the respective signal lines that correspond to the sixteenth to thirty-first pads used only in the X32 mode, the second selecting unit  322  of  FIG. 6  may be coupled to the respective signal lines that correspond to the eighth to fifteenth pads used in both the X32 mode and the X16 mode, and the third selecting unit  323  of  FIG. 7  may be coupled to the respective signal lines that correspond to the zero to seventh pads used commonly in the X32 mode, the X16 mode, and the X8 mode. 
   Accordingly, the sixteen data lines GIO_X 32 , which may correspond to the sixteenth to thirty-first pads and may be coupled to the first selecting unit  321 , correspond to data lines GIO&lt; 16 &gt; to GIO&lt; 31 &gt;. 
   Further, the eight data lines GIO_X 32 , which may correspond to the eighth to fifteenth pads and may coupled to the second selecting unit  322 , correspond to GIO&lt; 8 &gt; to GIO&lt; 15 &gt;, the data lines GIO_X 16 &lt; 0 &gt; correspond to GIO&lt; 16 &gt;, GIO&lt; 18 &gt;, GIO&lt; 20 &gt;, . . . , and GIO&lt; 30 &gt; or GIO&lt; 17 &gt;, GIO&lt; 19 &gt;, GIO&lt; 21 &gt;, . . . , and GIO&lt; 31 &gt;, and the data lines GIO_X 16 &lt; 1 &gt; correspond to GIO&lt; 17 &gt;, GIO&lt; 19 &gt;, GIO&lt; 21 &gt;, . . . , and GIO&lt; 31 &gt; or GIO&lt; 16 &gt;, GIO&lt; 18 &gt;, GIO&lt; 20 &gt;, . . . , and GIO&lt; 30 &gt;. 
   Furthermore, the eight data lines GIO_X 32 , which may correspond to the zero to seventh pads and may be coupled to the third selecting unit  323 , correspond to GIO&lt; 0 &gt; to GIO&lt; 7 &gt;, the data lines GIO_X 16 &lt; 0 &gt; correspond to GIO&lt; 0 &gt;, GIO&lt; 2 &gt;, GIO&lt; 4 &gt; . . . , and GIO&lt; 14 &gt; or GIO&lt; 1 &gt;, GIO&lt; 3 &gt;, GIO&lt; 5 &gt;, and GIO&lt; 15 &gt;, the data lines GIO_X 16 &lt; 1 &gt; correspond to GIO&lt; 1 &gt;, GIO&lt; 3 &gt;, GIO&lt; 5 &gt;, . . . , and GIO&lt; 15 &gt; or GIO&lt; 0 &gt;, GIO&lt; 2 &gt;, . . . , GIO&lt; 4 &gt;, and GIO&lt; 14 &gt;, and GIO_X 8 &lt;0:3&gt; correspond to GIO&lt;0:3&gt;, GIO&lt;4:7&gt;, . . . , GIO&lt;8:11&gt;, and GIO&lt;28:31&gt;. 
   An exemplary operation of the data output circuit of the semiconductor memory apparatus having the above-described configuration will be described below. 
   As for the memory specifications shown in  FIG. 8 , an exemplary row address and an exemplary column address that may be used for the memory capacities and data output modes X 8 , X 16 , and X 32  are defined. An exemplary memory having a capacity of 256 Mb and a memory having a capacity of 1 Gb may add one bit of row addresses A 12  and A 13  in the X16 mode and the X8 mode as compared with the X32 mode so as to be used as a control signal for selecting a data line in each corresponding mode. 
   Accordingly, as shown in  FIGS. 6 and 7 , a data line may be selected according to a row address GAX_rd corresponding to one bit of a row address A 12  in the X16 mode, and a data line may be selected according to the row address GAX_rd and the column address GAY_rd in the X8 mode. 
   Hereinafter, examples of the operation of the data output circuit of the semiconductor memory apparatus in each of the X32 mode, the X16 mode, and the X8 mode will be described. 
   —X32 Mode— 
   When a read command is input and the X32 mode is selected, the read/write classification signal wtrbt becomes a level for a read operation (low level), the X32 mode selecting signal is enabled at high level, and the X16 and X8 mode selecting signals are disabled at low level. 
   Since the X32 mode selecting signal is at high level and the read/write classification signal wtrbt is at low level, the tri-state inverters TIV 21 , TIV 31 , and TIV 41  of the first selecting unit  321  of  FIG. 5 , the first mode selecting unit  322 - 1  of the second selecting unit  322  of  FIG. 6 , and the first mode selecting unit  323 - 1  of the third selecting unit  323  of  FIG. 7  are turned on. 
   Accordingly, 32-bit data of the data lines GIO&lt;0:31&gt; that correspond to the data lines GIO_X 32  is output from the first selecting unit  321  of  FIG. 5 , the first mode selecting unit  322 - 1  of the second selecting unit  322  of  FIG. 6 , and the first mode selecting unit  323 - 1  of the third selecting unit  323  of  FIG. 7 , passes through the data output unit  400 , and is then output to the outside of the semiconductor memory apparatus through the pad unit  500 . 
   —X16 Mode— 
   When a read command is input and the X16 mode is selected, the read/write classification signal wtrbt becomes a level for a read operation (low level), the X16 mode selecting signal is enabled at high level, and the X32 and X8 mode selecting signals are disabled at low level. 
   Since the X16 mode selecting signal is at high level and the read/write classification signal wtrbt is at low level, one of either the second tri-state inverter TIV 32  or the third tri-state inverter TIV 33  of the second mode selecting unit  322 - 2  of the second selecting unit  322  of  FIG. 6  is turned on according to the row address GAX_rd, and one of either the second tri-state inverter TIV 42  or the third tri-state inverter TIV 43  of the second mode selecting unit  323 - 2  of the third selecting unit  323  of  FIG. 7  is turned on according to the row address GAX_rd. For example, when the row address GAX_rd is at high level, the tri-state inverters TIV 33  and TIV 43  are turned on, and when the row address GAX_rd is at low level, the tri-state inverters TIV 32  and TIV 42  are turned on. 
   Accordingly, when the row address GAX_rd is at high level, the data lines GIO_X 16 &lt; 1 &gt; are selected by the second mode selecting unit  322 - 2  of the second selecting unit  322  of  FIG. 6  and the second mode selecting unit  323 - 2  of the third selecting unit  323  of  FIG. 7 , and 16-bit data of the selected data lines passes through the data output unit  400 , and is then output to the outside of the semiconductor memory apparatus through the pad unit  500 . 
   Meanwhile, when the row address GAX_rd is at low level, the data lines GIO_X 16 &lt; 0 &gt; are selected by the second mode selecting unit  322 - 2  of the second selecting unit  322  of  FIG. 6  and the second mode selecting unit  323 - 2  of the third selecting unit  323  of  FIG. 7 , and 16-bit data of the selected data lines passes through the data output unit  400 , and is then output to the outside of the semiconductor memory apparatus through the pad unit  500 . 
   At this time, the data lines GIO_X 16 &lt; 0 &gt; correspond to GIO&lt; 1 &gt;, GIO&lt; 3 &gt;, GIO&lt; 5 &gt; . . . , and GIO&lt; 31 &gt; or GIO&lt; 0 &gt;, GIO&lt; 2 &gt;, GIO&lt; 4 &gt;, . . . , and GIO&lt; 30 &gt;, and the data lines GIO_X 16 &lt; 1 &gt; correspond to GIO&lt; 0 &gt;, GIO&lt; 2 &gt;, GIO&lt; 4 &gt;, . . . , and GIO&lt; 30 &gt; or GIO&lt; 1 &gt;, GIO&lt; 3 &gt;, GIO&lt; 5 &gt; . . . , and GIO&lt; 31 &gt;. 
   —X8 Mode— 
   When a read command is input and the X8 mode is selected, the read/write classification signal wtrbt becomes a level for a read operation (low level), the X8 mode selecting signal X 8  is enabled at high level, and the X32 and X16 mode selecting signals are disabled at low level. 
   Since the X8 mode selecting signal is at high level and the read/write classification signal wtrbt is at low level, one of the fourth to seventh tri-state inverters TIV 44  to TIV 47  of the third mode selecting unit  323 - 3  of the third selecting unit  323  of  FIG. 7  is turned on according to the result of a logical product of the number of all cases (00, 01, 10, or 11) of the row address GAX_rd and the column address GAY_rd. 
   For example, when the column address GAY_rd and the row address GAX_rd are at low level (00), the seventh tri-state inverter TIV 47  is turned on. When the column address GAY_rd is at low level and the row address GAX_rd is at high level (01), the sixth tri-state inverter TIV 46  is turned on. When the column address GAY_rd is at high level and the row address GAX_rd is at low level (10), the fifth tri-state inverter TIV 45  is turned on. When the column address GAY_rd and the row address GAX_rd are at high level (11), the fourth tri-state inverter TIV 44  is turned on. 
   When the column address GAY_rd and the row address GAX_rd are at low level (00), the data lines GIO_X 8 &lt; 0 &gt; are selected by the third mode selecting unit  323 - 3  of the third selecting unit  323  of  FIG. 7 , and 8-bit data of the data lines GIO_X 8 &lt; 0 &gt; passes through the data output unit  400 , and is then output to the outside of the semiconductor memory apparatus through the pad unit  500 . 
   When the column address GAY_rd is at low level and the row address GAX_rd is at high level (01), the data lines GIO_X 8 &lt; 1 &gt; are selected by the third mode selecting unit  323 - 3  of the third selecting unit  323  of  FIG. 7 , and 8-bit data of the data lines GIO_X 8 &lt; 1 &gt; passes through the data output unit  400 , and is then output to the outside of the semiconductor memory apparatus through the pad unit  500 . 
   When the column address GAY_rd is at high level and the row address GAX_rd is at low level (10), the data lines GIO_X 8 &lt; 2 &gt; are selected by the third mode selecting unit  323 - 3  of the third selecting unit  323  of  FIG. 7 , and 8-bit data of the data lines GIO_X 8 &lt; 2 &gt; passes through the data output unit  400 , and is then output to the outside of the semiconductor memory apparatus through the pad unit  500 . 
   When the column address GAY_rd and the row address GAX_rd are at high level (11), the data lines GIO_X 8 &lt; 3 &gt; are selected by the third mode selecting unit  323 - 3  of the third selecting unit  323  of  FIG. 7 , and 8-bit data of the data lines GIO_X 8 &lt; 3 &gt; passes through the data output unit  400 , and is then output to the outside of the semiconductor memory apparatus through the pad unit  500 . 
   At this time, the data lines GIO_X 8 &lt;0:3&gt; correspond to GIO&lt; 0 &gt;, GIO&lt; 4 &gt;, GIO&lt; 8 &gt; . . . , and GIO&lt; 28 &gt;, GIO&lt; 1 &gt;, GIO&lt; 5 &gt;, GIO&lt; 9 &gt;, . . . , and GIO&lt; 29 &gt;, GIO&lt; 2 &gt;, GIO&lt; 6 &gt;, GIO&lt; 10 &gt;, . . . , and GIO&lt; 30 &gt;, or GIO&lt; 3 &gt;, GIO&lt; 7 &gt;, GIO&lt; 11 &gt; . . . , and GIO&lt; 31 &gt;. 
   Instead of using the row address stored in the peripheral circuit or the row address stored in the bank, the row address GAX_rd may be generated by using the first control signal generating unit  310  of  FIG. 4 , and may be used for selecting data lines in the X16 mode and the X8 mode. The reason may be as follows. 
   For example, in a case where the zero memory bank and the first memory bank are sequentially activated and a read operation is sequentially performed thereon, when it is assumed that the row address corresponding to the bit A 12  of  FIG. 8  is at low level in the zero memory bank and is at high level in the first memory bank, the row address stored in the peripheral circuit of the semiconductor memory apparatus after the first memory bank is activated is maintained at high level. 
   When the data of the zero memory bank is read using the row address stored in the peripheral circuit, the row address may be changed, which causes a read error of word line data. 
   Accordingly, as shown in  FIG. 4 , a row address GAX_rd of a memory bank corresponding to an actual read command among the row addresses BAX&lt;0:3&gt; stored in the respective memory banks may be determined by using a command recognition signal cast 12 &lt;0:3&gt; enabled only when a read command is actually input for each memory bank. A data line may be selected by using the row address GAX_rd. Therefore, reliable data output control can be made. 
   It will be apparent to those skilled in the art that various modifications and changes may be made without departing from the scope and spirit of the present invention. Therefore, it should be understood that the above embodiments are not limiting, but illustrative in all aspects. The scope of the present invention is defined by the appended claims rather than by the description preceding them, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalents of such metes and bounds, are therefore intended to be embraced by the claims. 
   According to the data output circuit of the semiconductor memory apparatus according to an embodiment of the present invention, the following effects may be obtained. 
   First, since it may be unnecessary to provide local data bus lines to transmit data among sense amplifiers inside a memory bank, a layout area can be reduced, and a circuit design can be simplified. 
   Second, since data may be directly output through the data lines outside the memory bank without transmitting the data among the sense amplifiers, a data output time can be reduced, and thus the operation speed of the semiconductor memory apparatus can be increased. 
   Third, since a data output control operation may be performed in a state where an address of a memory bank according to a read command may be accurately detected, the reliability of the semiconductor memory apparatus can be improved.