Patent Publication Number: US-9907203-B2

Title: Fan control circuit

Description:
FIELD 
     The subject matter herein generally relates to fan control circuits. 
     BACKGROUND 
     In a computer system, a plurality of modules, such as a CPU and disks, generate heat when in operation. A fan control circuit may be used to control fans to cool modules. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Implementations of the present technology will now be described, by way of example only, with reference to the attached figures. 
         FIG. 1  is a block diagram of one embodiment of a fan control circuit. 
         FIG. 2  is a circuit diagram of one embodiment of the fan control circuit. 
     
    
    
     DETAILED DESCRIPTION 
     It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure. 
     Several definitions that apply throughout this disclosure will now be presented. 
     The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like. 
     The present disclosure is described in relation to a fan control circuit to control power provision to fans. 
       FIG. 1  illustrates an embodiment of a fan control circuit. The fan control circuit comprises a power supply module  10 , a timing circuit  20 , and a switching circuit  30  coupled to the timing circuit  20 . The power supply module  10  is configured to supply power to the timing circuit  20  and the switching circuit  30 . 
     The switching circuit  30  is configured to couple to a fan module  50  via an interface  40 , thereby enabling the power supply module  10  to supply power to the fan module  50  via the switching circuit  30  and the interface  40 . The fan module  50  comprises a plurality of fans (not shown). The timing circuit  20  is configured to receive a starting signal S from a computer system  60 . The starting signal S is a power on signal for powering on the computer system  60 . 
       FIG. 2  illustrates that the power supply module  10  comprises a first power supply  11  and a second power supply  13 . In one embodiment, the first power supply  11  is configured to provide a 3V voltage and the second power supply  13  is configured to provide a 12V voltage. 
     The timing circuit  20  comprises a timer chip  21 , a first resistor R 1 , and a first capacitor C 1 . The timer chip  21  comprises a ground terminal GND, a trigger terminal TRIG, an output terminal OUT, a reset terminal RESET, a control terminal CONT, a threshold terminal THRES, a discharging terminal DISCH, and a power supply terminal VCC. In one embodiment, a type of the timer chip  21  is NE555DR. 
     The switching circuit  30  comprises a first field effect transistor (FET) Q 1 , a second FET Q 2 , and a third FET Q 3 . Each of the first FET Q 1 , the second FET Q 2 , and the third FET Q 3  comprises a control terminal G, a first connecting terminal S, and a second connecting terminal D. In one embodiment, each of the first FET Q 1  and the second FET Q 2  is an n-channel metal oxide semiconductor (MOS), the third FET Q 3  is a p-channel MOS, each control terminal G is a gate terminal, each first connecting terminal S is a source terminal, and each second connecting terminal D is a drain terminal. 
     The ground terminal GND of the timer chip  21  is grounded. The ground terminal GND of the timer chip  21  is coupled to the control terminal CONT of the timer chip  21  via a second capacitor C 2 . The trigger terminal TRIG of the timer chip  21  is coupled to the first power supply  11  via a second resistor R 2 . The trigger terminal TRIG of the timer chip  21  is configured to receive the starting signal S via a third capacitor C 3 . The output terminal OUT of the timer chip  21  is coupled to the control terminal G of the first FET Q 1 . Each of the reset terminal RESET of the timer chip  21  and the power supply terminal VCC of the timer chip  21  is coupled to the first power supply  11 . Each of the threshold terminal THRES of the timer chip  21  and the discharging terminal DISCH of the timer chip  21  is coupled to a node  15 . The node  15  is coupled to the first power supply  11  via the first resistor R 1 . The node  15  via the first capacitor C 1  is grounded. 
     The source terminal S of the first FET Q 1  is grounded. The drain terminal D of the first FET Q 1  is coupled to the control terminal G of the second FET Q 2 . The control terminal G of the second FET Q 2  is coupled to the first power supply  11  via a third resistor R 3 . The source terminal S of the second FET Q 2  is grounded. The drain terminal D of the second FET Q 2  is coupled to the control terminal G of the third FET Q 3 . The control terminal G of the third FET Q 3  is coupled to the second power supply  13  via a fourth resistor R 4 . The source terminal S of the third FET Q 3  is coupled to the second power supply  13 . The drain terminal D of the third FET Q 3  is coupled to the second power supply  13 . The drain terminal D of the third FET Q 3  is coupled to the interface  40 . The interface  40  is coupled to the fan module  50 . 
     In use, when a computer is turned on, the trigger terminal TRIG of the timer chip  21  receives the starting signal S from the computer system  60 . The output terminal OUT of the timer chip  21  outputs a first control signal to the control terminal G of the first FET Q 1  to turn on the first FET Q 1 . The first control signal keeps a time T and the time T=1.1*R 1 *C 1 . During the time T, the first FET Q 1  is switched on, the second FET Q 2  is switched off, and the third FET Q 3  is switched off, thereby disabling the second power supply  13  from supplying power to the fan module  50 . After the time T, the output terminal OUT of the timer chip  21  outputs a second control signal to the control terminal G of the first FET Q 1  to turn off the first FET Q 1 , thereby enabling the second FET Q 2  to be switched on, thus the third FET Q 3  is switched on, and the second power supply  13  can supply power to the fan module  50 . In one embodiment, the first control signal is a high level signal and the second control signal is a low level signal. 
     In the fan control circuit, the timer chip  21  outputs the first control signal to the first FET Q 1  after receiving the starting signal S. During the time T, the first FET Q 1  is switched on, the second FET Q 2  is switched off, and the third FET Q 3  is switched off, thereby disabling the power supply module  10  from supplying power to the fan module  50 , thus decreasing energy consumption. 
     It is to be understood that even though numerous characteristics and advantages have been set forth in the foregoing description of embodiments, together with details of the structures and functions of the embodiments, the disclosure is illustrative only and changes may be made in detail, including in the matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.