Patent Publication Number: US-5894143-A

Title: Solid-state image pick-up device for the charge-coupled device type synchronizing drive signals for a full-frame read-out

Description:
This is a divisional of application Ser. No. 08/372,667 filed Jan. 13, 1995, now U.S. Pat. No. 5,705,837 which is a divisional of application Ser. No. 08/169,769, filed Dec. 20, 1993, now U.S. Pat. No. 5,410,349, which is a continuation of application Ser. No. 07/725,105, filed Jul. 3, 1991, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates generally to a solid-state image pick-up device of the charge-coupled device (CCD) type. More specifically, the present invention relates to solid-state image pick-up devices which may be fabricated with high density integration and high pixel density. According to one aspect of the present invention, a solid-state image pick-up device is provided with an improved vertical overflow drain structure. According to another aspect of the present invention, a solid-state image pick-up device provides an electronic shutter function having improved vertical resolution. In particular, the present invention employs a shift register for producing improved vertical resolution. The present invention is particularly advantageous for solid-state image pick-up devices providing functions for photographing a motion picture in an interlace scan read mode and photographing a still picture in a noninterlace/frame scan read mode. 
     BACKGROUND OF THE INVENTION 
     Solid-state image pick-up devices of the interline transfer type are used for electronic cameras, copying machines, and other video devices. In this type of image pick-up device, a plurality of photodiodes, each defining a pixel, are vertically and horizontally arrayed in a matrix. Vertical charge transfer paths are disposed between adjacent linear arrays of photodiodes, which extend in the column or vertical direction. A horizontal charge transfer path is disposed at one end of the vertical charge transfer paths. The area of the device where the photodiodes and the vertical charge transfer paths are formed is called the photodetecting area. Light shield layers for shielding light incident on the surfaces of the vertical and horizontal charge transfer paths are normally provided on these surfaces. 
     FIG. 1 is a plan view showing a selected portion of the photodetecting area A, shown in FIG. 3. A plurality of n +  impurity layers are arrayed in a matrix and are buried in a P-well layer, which is formed in the surface region of a semiconductor substrate, to form a plurality of photodiodes, e.g., photodiodes Pd 1  and Pd 2 . Vertical charge transfer paths such as paths L 1 , L 2  and L 3 , which are formed between adjacent columns of the matrix of the photodiodes Pd 1  and Pd 2 , are provided for transferring signal charges in the direction of arrow Y. The other area of the device than the photodetecting area including those photodiodes and the vertical charge transfer paths, forms the channel stop area. A plurality of gate electrodes G 1  -G 4 , for example, which are made of polycrystalline silicon layers, are formed on the surfaces of the vertical charge transfer paths L 1 , L 2  and L 3 . The image pick-up device provides a four-phase drive system based on each quartet of gate electrodes, which receive clock signals φ 1 , φ 2 , φ 3 , and φ 4 . 
     As shown in FIG. 1, a photodiode Pd 1  is formed from the two parallel gate electrodes G 1  and G 2 , and the photodiode Pd 2  is formed from the two parallel gate electrodes G 3  and G 4 . The same structure is correspondingly applied for the remaining photodiodes and gate electrodes (not shown). The photodiodes Pd 1  and Pd 2  are connected via transfer gates Tg 1  and Tg 2 , respectively, to the vertical charge transfer paths L 1 , L 2  and L 3 . The clock signals φ 1  -φ 4 , which are set at a predetermined high voltage, permit the charge from the photodiodes to be transferred to the vertical charge transfer paths. 
     With voltage variations of the clock signals φ 1 , φ 2 , φ 3 , and φ 4  according to the four-phase drive system, potential wells and potential barriers are sequentially generated at predetermined times t 0  to t 4 , as shown in FIG. 2. The vertical charge transfer paths L 1 , L 2  and L 3  transfer signal charges in the direction Y toward the horizontal charge transfer path (see FIG. 3). The horizontal charge transfer path transfers the signal charges from the respective vertical charge transfer paths at predetermined times so that the signal charges are read out sequentially. 
     The solid-state CCD image pick-up device thus arranged provides a so-called interlace/two-field scan read system for reading the signal charges. In the read system, odd-numbered groups, i.e., linear arrays of photodiodes, define an odd-numbered field, and even-numbered groups define an even-numbered field. The signal charges generated in the odd-numbered field are first read out of the photodiodes and then the signal charges of the even-numbered field are read out. Consequently, the signal charges for one frame are read out. However, when photographing a still picture using the conventional image pick-up device, because the even-numbered field and the odd-numbered field are combined to form one frame of an image, the time difference between the fields deteriorates the quality of the image. 
     FIG. 3 illustrates a solid-state image pick-up device of the frame transfer type (FT-CCD), which provides a scan read function based on the accordion transfer system. See Theuwissen, A. J. P. et al., &#34;The Accordion Imager, A New Solid-State Image Sensor,&#34; PHILIPS TECHNICAL REVIEW VOL. 43, No. 1/2, 1986. This solid-state image pick-up device will be described with reference to FIGS. 3 through 9. 
     As shown in FIG. 3, the device is made up of a photo-detecting portion A consisting of a number m of vertical transfer paths L 1  to L m  providing optoelectric transducing and charge transfer functions, a storage portion B consisting of charge transfer paths, which is disposed adjoining the vertical charge transfer paths L 1  to L m  and a horizontal charge transfer path C, which is coupled to one end of the group of the charge transfer paths in the storage portion B. Portions B and C generally have surfaces which are covered with a light shield film. Transfer gate electrodes, extending in the charge transfer direction Y, are disposed side by side on the upper surfaces of the vertical charge transfer paths L 1  to L m  in a manner such that the gate electrodes correspond to the pixels. 
     Gate signals are applied to the gate electrodes at times characteristic of the accordion transfer system. In an exposure mode, potential wells and potential barriers corresponding to the pixels are generated in the vertical charge transfer paths L 1  to L m . In a transfer mode, the signal charges are transferred in the Y direction by varying the potential wells and the potential barriers at predetermined times. The gate signals are generated in such a way that a shift register, denoted as D, shifts a start pulse IM in synchronism with clock signals φ 1  and φ 2 . Gate electrodes are likewise provided for the charge transfer paths in the storage portion B. The signal charges are transferred in the Y direction by gate signals generated in such a way that a shift register E transfers a start pulse ST in synchronism with clock signals φ 1  and φ 2 . 
     The vertical charge transfer paths L 1  to L m  and the charge transfer paths in the storage portion B synchronously transfer pixel signals generated in the photodetecting portion A to the storage portion B, where the pixel signals are temporarily stored. Then, the pixel signals are transferred line by line from the storage portion B to the horizontal charge transfer path C. Every time the horizontal charge transfer path C receives the pixel signal, it horizontally transfers the pixel signal in synchronism with a gate signal generated by a shift register F (not shown). In this way, all of the pixel signals are read out. 
     The timing of the related signals for the scan read operation are illustrated in FIGS. 4(a) through 4(c). As shown in FIG. 4(a), the start pulses IM and ST are supplied to the shift registers D and E. Those start pulses are transferred in synchronism with the two-phase clock signals φ 1  and φ 2 . Then, as shown in FIG. 4(b), gate signals A 1 , B 1 , C 1 , . . . , and H 1 , which are derived from the bit output contacts of the shift register D, are sequentially supplied to the gate electrodes of the vertical charge transfer paths L 1  to L m  in photodetecting area A. Similarly, as shown in FIG. 4(c), gate signals A s , B s , C s , . . . , H s , which are derived from the bit output contacts of the shift register E, are sequentially supplied to the gate electrodes of the charge transfer paths in the storage portion B. For simplicity, only the gate signals corresponding to eight gate electrodes are illustrated. 
     When the voltage of the gate signals A 1 , B 1 , C 1 , . . . , H 1  and A s , B s , C s , . . . , H s  is varied, the potential wells and the potential barriers, as shown in FIG. 5, are progressively changed so that the pixels signals are transferred, in order from pixel signals q a  closest to the horizontal charge transfer path C, to the charge transfer paths under the gate electrodes in the photodetecting area A and the storage portion B (the even-numbered gate electrodes and the odd-numbered gate electrodes being denoted Ev and Od, respectively). 
     The charge transfer through a vertical charge transfer path and the charge transfer path adjacent to the former in the storage portion B can best be understood by referring to FIG. 6. Assuming that the exposure takes place at time t 0 , potential wells (marked as hatched squares) and potential barriers (white squares) are alternately generated, according to a layout of the gate electrodes, in the vertical charge transfer paths in the photodetecting area A. Pixel signals q a , q b , q c , and q d  are generated along with the potential wells of pixels. The pixel signals are progressively transferred to portion B, starting from the pixel signal q a  closest to portion B. The generation of the potential wells and the potential barriers resembles the gradual expansion and contraction of the bellows of an accordion, hence the reason for referring to the charge transfer system under discussion as the accordion transfer system. 
     After all of the pixel signals have been temporarily stored in the storage portion B, the pixel signals are transferred in the accordion transfer mode and time sequentially read out through the horizontal charge transfer path C. 
     The solid-state image pick-up device based on this scan read system is advantageous in that a minimal number of transfer gate electrodes are required, which is favorable for high density integration. 
     In the image pick-up device just described, the shift register circuitry is constructed with CMOS transistors, and this circuitry, the photodetecting area A, the storage portion B, and the horizontal charge transfer path C are all fabricated into a semiconductor substrate. 
     The shift register is arranged as shown in FIG. 7 while a longitudinal sectional view of it in the semiconductor substrate is shown in FIG. 8. In FIG. 7, the shift register is constructed between power source voltages Vcc and V DD  (VCC&gt;V DD ). The bit stages of the shift register are constructed with inverting circuits each consisting of a p-channel MOS transistor connected to the power source Vcc and an n-channel MOS transistor. Both transistors are complimentarily coupled with one another. A MOS transistor, which is made conductive and nonconductive by clock signals φ 1  and φ 2 , is connected between the input and output contacts. In FIG. 7, capacitive elements ε are constructed utilizing interline capacitance. If the start pulse IM (or ST) is applied to the first bit stage, the shift register shifts the start signal in synchronism with the clock signal φ 1  and φ 2 , and produces gate signals at the bit output contacts in synchronism with the clock signal φ 1  and φ 2 . 
     When the shift register and the charge transfer paths are fabricated into a single semiconductor chip, the structure is as shown in FIG. 8. For example, a plurality of n-type impurity layers are formed in the region to serve as a photo-detecting area in the p-type semiconductor substrate so as to form the vertical charge transfer paths L 1  to L m . A gate oxide film (not shown) is formed on the upper surfaces of the vertical charge transfer paths L 1  to L m , and gate electrodes are layered on that oxide film. An n-well layer is buried in a drive region where the circuitry of the shift register is to be formed. A pair of p +  -type impurity layers are provided in the n-well layer. Gate electrodes η p  are layered with a gate oxide film, not shown, to form a p-channel MOS transistor. An n +  -type impurity layer is buried in the semiconductor substrate (p-Sub), and gate electrodes η n  are formed on the surface to form an n-channel MOS transistor. Those gates η p  and η n , and predetermined nodes are connected to form the CMOS inverting circuit (see FIG. 8). 
     In the solid-state image pick-up device of the CCD type thus constructed, the power source voltage Vcc is set at approximately 10 V and another power source voltage V DD  is set at 0 V. The gate signal voltage at the gate electrode also varies between 0 V and 10 V. 
     In the solid-state image pick-up device, the peripheral circuitry, including the shift registers controlling charge transfer, is constructed of CMOS transistors. Accordingly, it is extremely difficult to provide the image pick-up device with improved functions such as a so-called overflow drain, which drains unnecessary or excessive charges to the semiconductor substrate. In addition, it is difficult to implement an electronic shutter function. These difficulties are due to both the structure of the device and breakdown voltage. 
     With respect to the structural limitations, the conventional image pick-up device is based on the frame transfer type in which the vertical charge transfer paths include the mechanism for producing pixel signals. If the electronic shutter function is introduced into the image pick-up device, the smear component of the pixel signals is inevitably increased in the resultant reproduced picture. Therefore, the introduction of the electronic shutter function into the conventional image pick-up device is impractical. 
     With respect to the breakdown voltage limitation, if the vertical overflow drain function is introduced into the conventional image pick-up device, high voltage in the range of about 15 to 25 V must be applied to the semiconductor substrate. This voltage range is high enough to potentially destroy the impurity regions corresponding to the nodes of the CMOS transistors and to cause the gate oxide films to break down. 
     If the electronic shutter function is realized in the conventional image pick-up device, a much higher voltage must be applied to the semiconductor substrate than in the case of introducing the vertical overflow drain. 
     These problems can best be understood by referring to FIG. 9, which shows additional details of the conventional image pick-up device. To introduce the electronic shutter function into the image pick-up device, an interline transfer system is necessarily used for the charge transfer. In the photodetecting area, a plurality of n +  -type impurity layers are arrayed in matrix in a p-well layer buried in an n-type semiconductor substrate (n-Sub), thereby to form photodiodes. A plurality of n-type impurity layers, which serve as the vertical charge transfer paths L 1  to L m , are formed adjoining the n +  -type impurity layers. Further, p-type impurity layers are buried around them, and gate electrodes are layered, to form channel stoppers. 
     In a drive region, a p-well layer is buried, and a pair of n +  -type impurity layers are formed in the p-well. A gate oxide film layer (not shown) is layered thereon, and a gate electrode η n  is layered on the oxide film layer to form an n-channel MOS transistor. A p +  -type impurity layer is buried in the semiconductor substrate (n-Sub), a gate electrode η p  is formed on the surface to form a p-channel MOS transistor. A CMOS inverting circuit for the shift register shown in FIG. 7 is formed by properly connecting gate electrodes η n  and η p  and predetermined nodes. 
     To provide the structure of the so-called vertical overflow drain, a voltage in the range of 15 to 25 V is applied to the semiconductor substrate. To also provide the electronic shutter function, a structure is required so that, when a shutter voltage SS is applied to the p-well layer in the photodetecting area, which drains the charges generated by the photodiodes to the semiconductor substrate, an npn transistor is formed between the photodiode and the substrate to allow the charge to flow to the substrate. 
     To transfer the pixel signals, which are generated in the photodiodes by exposure to light, to the vertical charge transfer paths, a high voltage of approximately 12 V is applied to the transfer gates. To provide the normal charge transfer operation by the vertical charge transfer paths, the voltages of the respective signals are set so that the gate signal of 0 V for generating potential wells and the gate signal of approximately -8 V for generating potential barriers are supplied from the CMOS shift register to the gate electrodes. In FIG. 9, the substrate voltage Vs is in the range of 15 to 25 V, the power source voltage Vcc is about 0 V, and the voltage V L  is about -8 V. 
     Where the CMOS structure is used and the voltages are set up as just mentioned, the gate signal voltage at the gate electrode varies from -8 to 12 V. Under this condition, high voltages ranging from 23 to 33 V are sometimes applied to the gate oxide films under the gate electrodes η p  of the p-channel MOS transistors of CMOS in the drive regions. This high voltage is in excess of a nominal breakdown voltage and can damage the oxide film. 
     The image pick-up device can also provide a frame storage mode, in which an exposure state is set up and continued, and a field scan read for the odd-numbered field and a field scan read for the even-numbered field are alternately repeated at predetermined periods to produce an interlace scan read. In the field storage mode, the pixel signals of the odd-numbered and even-numbered fields are mixed and subjected to a one-time field scan read. This sequence is repeated twice to produce an image corresponding to one frame. At this time, if a moving object is photographed in a still picture photographing mode, the time of reading one field is different from the time of reading the succeeding field, so that the images of the fields read out are different from each other. Therefore, the picture quality of the reproduced image is deteriorated because the reproduced image is the combination of off-center images. In the field storage mode, the pixel signals of one line are formed using two lines of pixel signals. Accordingly, the vertical resolution is reduced to a value corresponding to approximately one-half of the number of pixels. 
     Referring to FIG. 3, the conventional CCD image pick-up device of the accordion transfer type is based on the so-called frame transfer (FT) system in which the vertical charge transfer paths in the photodetecting area provide both the charge transfer function and the optoelectric transducing function. For this reason, the reproduced image suffers from smear. In the CCD image pick-up device, the vertical charge transfer paths are formed in the p-type substrate. Because of this, the overflow drain function and the so-called substrate-free electronic shutter cannot be brought into full play. This makes it difficult to apply the image pick-up device to a built-in camera in a video tape recorder, electronic still camera, and other types of image pick-up devices. 
     In the image pick-up device employing the p-well structure having the above functions, a shift register circuit arrangement shown in FIG. 10 is used to form gate signals in order to realize the charge transfer by the accordion transfer system. However, the circuit arrangement involves the following problems. 
     As shown in FIG. 10, each bit of the shift register consists of a cell structure enclosed by the dotted line. The required number of the cells are connected in a cascade fashion to make up the shift register. The cell structure of the first stage will typically be described. Three NMOS transistors u 11 , u 12 , and u 13  are inserted between a signal line for a second clock signal φ 2  and an earth contact such that the source-drain paths of those transistors are connected in series. A capacitance C 11  made by using a gate oxide film is connected between the gate contact and the source contact of the transistor u 11 . The gate contact and the drain contact of the transistor u 12  are short circuited. The source-drain path of an additional transistor u 14  is inserted between the source contact of the transistor u 11  and ground while the gate contact is connected to a signal line for clock signal φ 1 . NMOS transistors u 15  to u 18 , and a capacitor C 12  make up a similar circuit. The drain contact of the transistor u 13  of the first circuit of the cell structure is connected to the gate contact of the transistor u 15  of the second circuit. 
     The gate contact of the transistor u 11  constitutes an input contact of the cell structure. The drain contact of the transistor u 17  comprises an output contact and the gate contacts of the transistors u 13  and u 17  comprise reset contacts. A plurality of these cells are connected such that the input contacts and the output contacts of the cells are connected so as to form a cascade connection. A start pulse IM (or ST) is applied to the gate contact of the transistor u 11  of the first stage cell by way of an NMOS transistor u 00 , which turns on and off in synchronism with the first clock signal φ 1 . 
     In the cascade connection of the cells, the adjacent cells, for example, cells SE1 and SE2, are interconnected as shown. The gate contact of the transistor u 13  in the first circuit of the cell SE1 is connected to the source contact of the transistor u 11  in the first circuit of the succeeding cell SE2. The gate contact of the transistor u 17  in the second circuit of the cell SE1 is connected to the source contact of the transistor u 15  in the second circuit of the succeeding cell SE2. The cell of the last stage is followed by a terminal circuit, as shown. 
     Bit output signals A 1 , B 1 , C 1 , . . . , H 1  or A s , B s , C s , . . . , H s  generated at the source contacts of the transistors u 15  of the respective cells are applied to the transfer gates of the photodetecting area A and the storage portion B, as shown in FIG. 3. The timing of the bit output signals, clock signals φ 1  and φ 2  and the start signal are as shown in FIG. 11. 
     In the conventional shift register thus constructed, as seen when watching times t 0 , t 1 , and t 2 , the bit output signals A 1 , B 1 , C 1 , . . . , H 1  or A s , B s , C s , . . . , H s  are output during every other period of clock signal φ 1  or φ 2 . Therefore, the transfer speed provided by the shift register is only 1/2 the transfer speed as defined by the frequency of the clock signal φ 1  or φ 2 . In other words, the frequency of the clock signal φ 1  or φ 2  must be twice the transfer frequency when the charge is transferred in the vertical direction. This fact indicates that to realize the solid-state image pick-up device of high pixel density, a high frequency oscillator is required, making it difficult to design the shift register. 
     Further, the conventional shift register cannot be reset until the start pulse reaches the cell of the last stage. Therefore, the propensity of the shift register rejects the resetting of the shift register at desired times by an external controller. In this respect, the control performance of the shift register is not optimal. 
     SUMMARY OF THE INVENTION 
     The principal object of the present invention is to provide a solid-state image pick-up device of the charge-coupled device (CCD) type which can provide a clear reproduced image by using a so-called noninterlace/full-frame read system which reads out all of the pixel signals through one-time frame read operation using a system different from the interlace/two-field scan read system employed in the prior art. 
     Another object of the present invention is to provide a solid-state CCD image pick-up device which, when the image pick-up device incorporates an electronic shutter in place of a mechanical shutter, can provide a clear reproduced image by using a so-called noninterlace/full-frame read system which reads out all of the pixel signals through one-time frame read operation. 
     A further object of the present invention is to provide a solid-state CCD image pick-up device which is free from unwanted blooming in which a vertical overflow drain structure is employed to drain excessive charges of the photodiodes into the substrate. The overflow drain structure advantageously can incorporate an electronic shutter function, which is operable independent of the substrate, because of the charge drainage to the substrate, and is operable in the full frame scan read mode suitable for photographing a still picture because the image pick-up device is of the interline type and yet is capable of the full frame scan read. 
     Still another object of the present invention is to provide a solid-state CCD image pick-up device providing a function suitable for photographing a motion picture in an interlace scan read mode and a function suitable for photographing a still picture in a noninterlace/frame scan read mode. 
     Another object of the present invention is to provide a solid-state CCD image pick-up device having an electronic shutter function and which is provided with a shift register capable of generating gate signals for a scan read having increased vertical resolution. 
     These and other objects, features and advantages of the present invention are achieved by a solid-state image pick-up device of the charge-coupled device type, comprising a plurality of optoelectric transducing elements corresponding to pixels, the elements being vertically and horizontally arrayed in a matrix fashion so as to form column linear arrays and row linear arrays, the column linear arrays defining a column direction and a plurality of vertical charge transfer paths, at least one of the vertical charge transfer paths being associated with a corresponding adjacent column linear array. Pixel signals are vertically transferred from each of the column linear arrays to a corresponding one of the vertical charge transfer paths in a manner such that, after pixel signals generated in the pixels are transferred to the vertical charge transfer paths, gate signals occurring at predetermined times are applied to gate electrodes of the vertical charge transfer paths so as to permit the pixel signals to be scan read from the column linear arrays by the horizontal charge transfer paths. The image pick-up device further comprises switching elements provided for each of a plurality of transfer gate electrodes coupled between a drive signal electrode and a pair of vertical transfer gate electrodes disposed adjacent to each of the optoelectric transducing elements so that the gate electrodes are combined in an order starting from the gate electrode disposed closest to the horizontal charge transfer path into groups each consisting of a predetermined number of gate electrodes. A drive circuit sequentially generates a plurality of drive signals for the groups of the gate electrodes during every period during which the switching elements are rendered conductive and the pixel signals are transferred to the horizontal charge transfer paths from the column linear arrays so as to allow a full frame scan read to be performed through the vertical charge transfer paths by supplying a predetermined number of timing signals, the predetermined number corresponding to the number of gate electrodes, to the gate electrodes as the drive signals from the drive circuit. 
     According to another embodiment of the present invention, a solid-state CCD image pick-up device comprises a vertical overflow drain structure for draining excessive charges in a photodetecting area into a semiconductor substrate, a plurality of charge transfer paths formed in first well layers buried in the semiconductor substrate and a plurality of drive circuits formed in second well layers, the second well layers being formed at least one of separately from and integrally with the first well layers in the semiconductor substrate, wherein each of the drive circuits comprises a plurality of transistors having a single MOS structure. 
     According to another embodiment of the present invention, a solid-state CCD image pick-up device comprises a plurality of optoelectric transducing elements corresponding to pixels, the elements being vertically and horizontally arrayed in a matrix fashion, a plurality of vertical charge transfer paths each disposed between the adjacent linear arrays of optoelectric transducing elements which extend in the column direction and a pair of gate electrodes for each of the vertical charge transfer paths adjacent to the optoelectric transducing elements. Pixel signals are vertically transferred from each of the column linear arrays to a corresponding one of the vertical charge transfer paths such that, after pixel signals generated in the pixels are transferred to the vertical charge transfer paths, gate signals occurring at predetermined times are applied to the gate electrodes of the vertical charge transfer paths so as to permit the pixel signals to be scan read from the column linear arrays by a horizontal charge transfer path. The image pick-up device photographs a motion picture by an interlace/2 field scan read such that, by application of the gate signals to the gate electrodes at the predetermined times, the field scan read is performed twice while the pixel signals from two lines of pixel signals are mixed in the horizontal charge transfer path. 
     Further, another embodiment of the present invention provides a solid-state CCD image pick-up device comprising a plurality of optoelectric transducing elements corresponding to pixels, the elements being vertically and horizontally arrayed in a matrix fashion, the vertically arrayed elements defining a column direction, a plurality of vertical charge transfer paths, each of the paths being operatively coupled to a corresponding one of the linear arrays of optoelectric transducing elements extending in the column direction, a pair of gate electrodes coupled to each of the vertical charge transfer paths adjacent to the optoelectric transducing elements and circuitry for supplying a field shift signal for transferring pixel signals generated in the optoelectric transducing elements to the vertical charge transfer paths at different times for odd-numbered fields and even-numbered fields. Pixel signals are vertically transferred from the column linear arrays to the vertical charge transfer paths such that, after pixel signals generated in the pixels are transferred to the vertical charge transfer paths, application of gate signals occurring at predetermined times to the gate electrodes of the vertical charge transfer paths provides a scan read of the pixel signals from each of the column linear arrays by the horizontal charge transfer path. The image pick-up device photographs a motion picture in an interlace/2 field scan read mode such that a field scan read is performed two times by application of the gate signals to the gate electrodes to allow transfer of pixel charges to the vertical charge transfer paths in an order starting from one of the pixel signals corresponding to the one of the pixels closest to the horizontal charge transfer path. 
     Additionally, the present invention provides a solid-state CCD image pick-up device comprising a plurality of optoelectric transducing elements corresponding to pixels, the elements being vertically and horizontally arrayed in a matrix fashion to provide column linear arrays and row linear arrays of the elements, the column linear arrays defining a column direction, a plurality of vertical charge transfer paths, each of the paths being operatively coupled to a corresponding one of the optoelectric transducing elements and a pair of gate electrodes for each of the vertical charge transfer paths adjacent to the optoelectric transducing elements. A plurality of pixel signals are vertically transferred from each of the column linear arrays to a corresponding one of the vertical charge transfer paths such that, after the pixel signals are transferred to the vertical charge transfer paths, application of gate signals occurring at predetermined times to the gate electrodes of the vertical charge transfer paths permit a scan read of the pixel signals for each of the column linear arrays by a horizontal charge transfer path. The image pick-up device provides at least one photograph of motion picture in an interlace/2 field scan read mode such that the field scan read is performed responsive to two applications of the gate signals to the gate electrodes to allow transfer of pixel charges to the vertical charge transfer paths in an order starting from one of the pixel signals provided by the pixel closest to the horizontal charge transfer path. 
     To achieve the above objects, the present invention is directed to a solid-state CCD image pick-up device in which a plurality of optoelectric transducing elements corresponding to pixels are vertically and horizontally arrayed in a matrix fashion, and in which vertical charge transfer paths are each disposed between adjacent column linear arrays of optoelectric transducing elements defining a column direction, wherein pixel signals are vertically transferred from each of the column linear arrays to a corresponding one of the vertical charge transfer paths to permit, after pixel signals generated in the optoelectric transducing elements are transferred to the vertical charge transfer paths, application of gate signals generated at predetermined times from a shift register to gate electrodes of the vertical charge transfer paths at predetermined times, wherein the pixel signals are scan read from the column linear arrays by a horizontal charge transfer path. 
     More specifically, the shift register comprises first, second and third transistors having source-drain paths connected in series between a first line providing a first timing signal and a predetermined voltage line, a bootstrap capacitor connected between the gate and source of the first transistor and a fourth transistor having a gate contact connected to receive a second timing signal and having a drain contact connected to both a gate contact and the drain contact of the second transistor and having a source contact connected to the predetermined voltage line. The shift register further comprises fifth, sixth and seventh transistors having source-drain paths connected in series between a line providing a second timing signal and the predetermined voltage line, a bootstrap capacitor connected between the gate and source of the fifth transistor and an eight transistor having a gate contact connected to receive the first timing signal, having a drain contact connected to both the gate and drain contacts of the sixth transistor and having a source contact connected to the predetermined voltage line. The shift register further comprises a plurality of bit circuits each having a cell structure in which a node between the second and third transistors is connected to the gate contact of the fifth transistor, the gate contact of the first transistor forms an input contact, and a node between sixth and seventh transistors forms an output contact, wherein the plurality of bit circuits are connected in a cascade fashion to permit the output contact of one bit circuit to be coupled to the input contact of the succeeding bit circuit. 
     According to one aspect of the present invention, a start pulse is applied to the input contact of the least significant bit circuit through a switching element to be turned on and off in synchronism with the second timing signal and a reset signal is applied to the gate contacts of the third and seventh transistors and bit signals appearing at the output contacts of the bit circuits are applied to transfer gate electrodes. 
     These and other objects, features and advantages of the invention are disclosed in or apparent from the following description of preferred embodiments. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The preferred embodiments are described with reference to the drawings, in which like elements are generally denoted by like or similar numbers, and in which: 
     FIG. 1 is a plan view showing the structure of a key portion of a conventional solid-state image pick-up device of the CCD type; 
     FIG. 2 is a diagram showing the charge transfer operation by the conventional device in terms of potential profiles. 
     FIG. 3 is a plan view showing the structure of a key portion of a conventional solid-state image pick-up device of the CCD type; 
     FIGS. 4(a) through 4(c) are diagrams showing the timing pattern of the device of FIG. 3; 
     FIGS. 5 and 6 are diagrams showing the transfer operations by the conventional device; 
     FIGS. 7 to 9 are circuit and schematic diagrams useful in explaining the problems of the conventional device; 
     FIG. 10 is a circuit diagram showing a conventional shift register; 
     FIG. 11 is a timing chart showing the operation of the shift register of FIG. 10; 
     FIG. 12 is a block and schematic diagram showing an electronic still camera incorporating a solid-state image pickup device of the CCD type according to an embodiment of the present invention; 
     FIG. 13 is a block and schematic diagram showing the solid-state image pick-up device of the invention; 
     FIG. 14 is a diagram showing the construction of a key portion of a photodetecting area of the image pick-up device, and its periphery circuit arrangement; 
     FIGS. 15 and 16 are sectional views showing key portions of the structure shown in FIG. 14; 
     FIG. 17 is a waveform roughly showing a scan read operation of the image pick-up device; 
     FIGS. 18 through 23 are timing charts showing in detail the scan read operation of the image pick-up device of the embodiment; 
     FIG. 24 is a circuit diagram showing a drive circuit used in another embodiment of the present invention; 
     FIGS. 25 through 32 are timing charts showing in detail the scan read operation of the image pick-up device of the embodiment of FIG. 24; 
     FIG. 33 is a diagram showing the construction of a photodetecting area of the image pick-up device, and its periphery circuit arrangement according to another embodiment of the invention; 
     FIGS. 34 to 37 are timing charts showing in detail the scan read operation of the image pick-up device of the embodiment shown in FIG. 33; 
     FIG. 38 is a circuit diagram showing a circuit arrangement of a shift register incorporated into another embodiment of the image pick-up device; and 
     FIGS. 39 and 40 are timing charts useful in explaining the operation of the shift register shown in FIG. 38. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A first embodiment of a solid-state image pick-up device of the charge-coupled device type according to the present invention will be described with reference to the accompanying drawings. In this embodiment, the image pick-up device is particularly suited for electronic still cameras. 
     As shown in FIG. 12, the overall construction of the electronic still camera includes a pick-up optical system 1, a stop mechanism 2, and a solid-state image pick-up device 3 of the CCD type incorporating the present invention. These components are disposed side by side in alignment with one another with respect to an optical axis of the pick-up optical system 1. With the combination of those components, an image of an object is incident on the photodetecting area of the solid-state image pick-up device 3. Preferably, the electronic still camera includes a signal processor 4 and a recording mechanism 5. The signal processor 4 applies color separation, γ-correction, white balance adjustment, and the like to the pixel signals generated by the solid-state image pick-up device 3. The recording mechanism 5 advantageously applies modulation processing to the luminance signal and the color difference signal generated from the recording mechanism 5, thereby converting them into a signal format advantageously suited to recording operations. A sync control circuit 6 synchronously controls the operation of the stop mechanism 2, read times of the solid-state image pick-up device 3, and the operation of the signal processor 4 and the recording mechanism 5. The still camera, under the control of the sync control circuit 6, provides a sequence of operations including the image pick-up and recording. 
     The construction of the solid-state image pick-up device 3 is as shown in FIG. 13, and it includes a photodetecting area 7 including a plurality of matrix-arrayed photodiodes, generally denoted P, corresponding to pixels and vertical charge transfer paths L 1  to L m  each disposed between the adjacent linear arrays of photodiodes, which extend in the column direction Y. A horizontal charge transfer path 8 is formed and located at one end of the vertical charge transfer paths L 1  to L m . An output amplifier 9 is formed and located at one end of the horizontal charge transfer path 8. 
     In connection with the vertical charge transfer paths L 1  to L m , gate electrodes are provided as discussed in greater detail below. A light shield layer advantageously is provided over the structure to shield light incident on the upper surface. First, second and third drive circuits 10, 11 and 12, respectively, supply signals to the gate electrodes to cause the vertical charge transfer paths L 1  to L m  to transfer charges at predetermined times. The sync control circuit 6 of FIG. 12 generates a start pulse and timing signals φ L , φ G , φ FS , φ S , φ 1 , φ 2 , φ 3 , and φ 4 , which are supplied to the drive circuits 10, 11, and 12. 
     The horizontal charge transfer path 8, which receives signal charges transferred from the vertical charge transfer paths L 1  to L m , is provided with gate electrodes for horizontally transferring the received signal charges to an output amplifier 9. Gate signals a1, a2, a3, and a4, supplied from the sync control circuit 6, are applied to the gate electrodes, causing the horizontal transfer of signal charges. 
     The structure of the photodetecting area 7 and the circuit arrangements of the drive circuits 10, 11, and 12 coupled with the area will be described with reference to FIGS. 14, 15 and 16. FIG. 14 is a plan view showing a key portion of the photodetecting area 7, as viewed from the photodetecting surface. FIG. 15 is a sectional view taken along line x--x in FIG. 14, while FIG. 16 is a sectional view taken along line y--y in FIG. 14. 
     In these figures, p-well layers 14, 15 and 16 are formed in the surface region of an n-type semiconductor substrate 13. The p-well layer 14 is provided for forming the photodetecting area 7. The p-well layer 14 is also used in forming the first drive circuit 10. The p-well layer 16 is used in forming the second and third drive circuits 11 and 12. The related circuits advantageously are formed in p-well layers 14, 15, and 16. 
     In the photodetecting area 7, a plurality of impurity layers 17 made of n +  impurity are formed in the column direction Y and the row direction X into a matrix array of photodiodes denoted as P in FIG. 13. A plurality of n-type impurity layers 18 (indicated by dotted lines in FIG. 16) are formed between the adjacent linear arrays of impurity layers 17, which extend in the column direction Y to form the vertical charge transfer paths L 1  to L m  shown in FIG. 13. A plurality of p +  impurity layers 19 are formed, in a surrounding fashion, in the portions exclusive of the portions to serve as transfer gates denoted as Tg (only one portion is typically illustrated in FIG. 14), the photodiode portions, and the portions of the vertical charge transfer paths to form channel stopper regions (shaded portions enclosed by dotted lines in FIG. 14). 
     In FIG. 14, the horizontal linear arrays of photodiodes P (FIG. 13) are denoted, in order from the bottom, as P 1 , P 2 , P 3 , . . . , P 6 , respectively. Gate electrodes G 11  to G 41 , G 12  to G 13  to G 43 , . . . G 1n  to G 4n , each consisting of paired polycrystalline silicon layers, are layered on the upper surfaces of the vertical charge transfer paths L 1  to L n , while being respectively adjacent to the horizontal linear arrays of photodiodes P 1 , P 2 , P 3 , . . . P 6 . As shown in FIGS. 14 and 15, the odd-numbered gate electrodes, G 11 , G 31 , G 12 , G 32 , G 13  and G 33 , for example, are designed to have a narrow width W1, while the even-numbered gate electrodes, such as G 21 , G 41  G 22 , G 42 , G 23  and G 43 , are designed to have a wide width W2. Here, those gate electrodes are counted, with the gate electrode G 11 , as the first gate electrode. 
     Gate signals φ 11 , φ 21 , φ 31 , φ 41 , φ 12 , φ 22 , φ 32 , and φ 42  are applied at predetermined times (discussed below) to the gate electrodes so that potential wells (referred to as transfer pixels) and potential barriers, which are for charge transfer, are generated in the vertical charge transfer paths under the gate electrodes. When a predetermined high voltage is applied to the even-numbered gate electrodes G 21 , G 41 , G 22 , G 42 , G 23  and G 43 , the transfer gates Tg become conductive. The transfer pixels, which are generated under the even-numbered gate electrodes G 21 , G 41 , G 22 , G 42 , G 23  and G 43  located adjacent to the horizontal linear arrays of photodiodes P 1 , P 2 , P 3 , . . , P 6  become conductive. Under this condition, transfer of signal charges from the photodiodes to the transfer pixels is allowed. 
     As shown in FIG. 14, the horizontal charge transfer path 8 is formed in the location at the end of the vertical charge transfer paths L 1  to L m , and gate electrodes are provided for horizontally transferring signal charges at the times providing either a four- or a two-phase drive system. 
     A circuit arrangement of the first drive circuit 10 will be described with reference to FIGS. 14 and 16. The leading end of the odd-numbered gate electrodes G 11 , G 31 , G 12 , G 32 , G 13  and G 33  are connected to a signal line providing a V L , through NMOS transistors M 11 , M 31 , M 12 , M 32 , M 13  and M 33 . The leading ends of the even-numbered gate electrodes G 21 , G 41 , G 22 , G 42 , G 23  and G 43  are connected to a signal line providing a drive signal φ H , through NMOS transistors M 21 , M 41 , M 22 , M 42 , M 23  and M 43 . It will be apparent that the gate electrode G 11  closest to the horizontal charge transfer path 8 is counted as the first gate electrode. A drive signal φ G  is applied to the gate contacts of those transistors. 
     The leading ends of the even-numbered gate electrodes G 21 , G 41 , G 22  G 42 , G 23  and G 43  are connected to the emitter contacts of npn transistors Q 21 , Q 41 , Q 22 , Q 42 , Q 23  and Q 43 , respectively. A drive signal φ FS  is applied to the base contacts of those transistors, and voltage V s  is applied to the collector contacts. 
     Each NMOS transistor is constructed from a pair of n +   impurity layers 20 and 21, and a gate electrode layered on the surface portion, as shown in the structure within the p-well layer 15 in FIG. 16. A drive signal φ H  is coupled with the n +   impurity layer 20 to serve as a drain contact. The n +  impurity layer 21 to serve as a source contact is connected to the gate electrode on the vertical charge transfer path. The signal V L  is applied to a p +   impurity layer 22 buried in the p-well layer 15. The npn transistor includes a p +  impurity layer 23 buried in the p-well layer 15, an n +  impurity layer 24 and an n-type semiconductor substrate 13. The n +  impurity layer 24 serving as an emitter contact is connected to the gate electrodes. A timing signal φ FS  is applied to the p-well layer 15, serving as the base contact and the p +   impurity layer 23. A bias voltage Vs for the substrate 13 is applied to the n-type semiconductor substrate 13 serving as the collector contact. The second drive circuit 11 includes NMOS transistors m 11  to m 4n  which select the timing signals φ 1  to φ 4  from the sync control circuit 6 in synchronism with drive signals S 1  to S n  generated from the third drive circuit 12. The NMOS transistors are grouped into quartets of transistors. The drive signals S 1 , S 2 , S 3  and S 4  are sequentially applied to their gate contacts. The timing signal φ 1  is applied to the drain contacts of the first NMOS transistors m 11 , m 12 , m 13  and m 14 , timing signal φ 2  is applied to the drain contacts of the second NMOS transistors m 21 , m 22 , m 23  and m 24 , timing signal φ 3  is applied to the drain contacts of the third NMOS transistors m 31 , m 32 , m 33  and m 34  and timing signal φ 4  is applied to the drain contacts of the fourth NMOS transistors m 41 , m 42 , m 43  and m 44 . The signals φ 11 , φ 21 , φ 31  and φ 41  coupled with the source contacts of the NMOS transistors m 11 , m 21 , m 31  and m 41  in FIG. 14, respectively, correspond to the timing signals φ 1 , φ 2 , φ 3 , and φ 4 . 
     As shown, gate electrodes are connected, starting with gate electrode G 11  closest to the horizontal charge transfer path 8, to the source contacts of the NMOS transistors. 
     The third drive circuit 12 includes a shift register for producing drive signals S 1  to S n  at predetermined times, as discussed in greater detail below. 
     Second and third drive circuits 11 and 12 are each composed of an NMOS transistor formed in the p-well layer 16 shown in FIG. 16, and other electronic components. A plurality of n +   impurity layers 25 and 26 forming an NMOS transistor and a gate contact, by way of example, are formed in the p-well layer 16, as shown in FIG. 16. 
     The operation of the image pick-up device when it takes a still picture will be described with reference to FIG. 17. It is assumed that the period T VB  corresponds to the vertical blanking period of a standard television system, i.e., an NTSC television system. At a predetermined time during the period T VB , a so-called field shift is performed to shift the pixel charges from the photodiodes to the vertical charge transfer paths. For the electronic shutter function, the time of the field shift operation corresponds to a time at which a shutter is closed, i.e., exposure completion. Accordingly, the exposure operation starts at a time after the shutter close time, and the device operates so that the exposure time ranges from the exposure start time to a time of starting the field shift operation. The unnecessary charges possibly causing the smear component and the dark current component in the vertical charge transfer paths L 1  to L m  and the horizontal charge transfer path 8, are discharged by the charge transfer operation before the field shift starts. Further, immediately before the exposure starts, the unnecessary charges in the photodiodes are drained by the vertical overflow drain structure. 
     During the period T VB  corresponding to the vertical blanking period of the standard television system, the pixel signals of all of the photodiodes are simultaneously transferred to the transfer pixels of the vertical charge transfer paths L 1  to L m . During the period T HB  corresponding to the horizontal blanking period, a pixel signal of the transfer pixel closest to the horizontal charge transfer path 8 is transferred to the transfer path 8. During a period T 1H  corresponding to the horizontal scan period (called a 1 H period), the pixel signals of one line are horizontally transferred through the horizontal charge transfer path 8. As a result, the pixel signals of the first line are read out. 
     Then, during the period T HB  corresponding to the next horizontal blanking period, the vertical charge transfer paths L 1  to L m  feed the pixel signals of the next line to the horizontal charge transfer path 8. During a period T 1H  corresponding to the next horizontal scan period, the pixel signals are horizontally transferred through the horizontal charge transfer path 8. In this way, the pixel signals of the second line are read out. 
     The pixel signals of the third line are likewise read out of the photodiodes during periods T HB  and T 1H . The pixel signals of the remaining lines are successively read out while repeating this sequence of operations. Finally, all of the pixel signals of one frame are read out. 
     The scan read operation will be described in greater detail with reference to FIG. 18, which shows a timing chart for drive signals and timing signals. In FIG. 18, the period T VB  corresponds to the vertical blanking period, period T HB  corresponds to the horizontal blanking period and period T 1H  corresponds to the horizontal scan period. Further, &#34;H&#34; indicates a voltage of about 12 V, &#34;M&#34; indicates a voltage of about 0 V, &#34;L&#34; indicates a voltage of about -8 V and &#34;HH&#34; indicates approximately 15 to 25 V, which is equal to the substrate voltage. 
     During the period T VB  corresponding to the vertical blanking period, the timing signal φ H  goes high (H) only at a predetermined time t2, and remains at a level &#34;M&#34; during the remaining time. The timing signal φ G  is always at the &#34;M&#34; level. The timing signal φ FS  goes high as the timing signal φ H  goes high, and is kept at the &#34;L&#34; level during the remaining time. The drive signals S 1  to S n  generated from the third drive circuit 12 are always at the &#34;L&#34; level. 
     During the period T VB , all of the NMOS transistors of the first drive circuit 10 are rendered conductive by the timing signal φ G  at the &#34;M&#34; level, while at the same time all of the drive signals S 1  to S n  of the third drive circuit 12 are set at the &#34;L&#34; level. Accordingly, all of the NMOS transistors in the second drive circuit 11 become conductive. All of the gate electrodes G 11 , G 21 , G 31 , G 41  to G 1n , G 2n , G 4n  are controlled by the first drive circuit 10. 
     More specifically, when the timing signals φ H  and φ FS  are not at the &#34;H&#34; level, the gate signals φ 11 , φ 31 , φ 12 , φ 32  to φ 1n , φ 3n , which are applied to the odd-numbered gate electrodes G 11 , G 31  , G 12 , G 32  to G 1n , G 3n , are each equal in voltage level to the signal V L  (constantly set at -8 V). Under this condition, potential barriers are generated in the vertical charge transfer paths L 1  to L m  under those gate electrodes. 
     The gate signals φ 21 , φ 41 , φ 22 , φ 42  to φ 2n , φ 4n , which are applied to the even-numbered gate electrodes G 21 , G 41 , G 22 , G 42  to G 2n , G 4n , are each equal in voltage to the signal φ H  at the &#34;M&#34; level. Under this condition, transfer pixels are generated in the vertical charge transfer paths L 1  to L m  under those gate electrodes. 
     Accordingly, all of the portions adjacent to the transfer gates Tg (see FIG. 14) serve as the transfer pixels being separated from one another by the potential barriers. 
     Under this condition, when the timing signals φ H  and φ FS  go high at time t2, all of the npn transistors Q 21 , Q 41 , Q 61 , etc., become conductive and the &#34;H&#34; level voltage of approximately 12 V is applied to only the even-numbered gate electrodes G 21 , G 41 , G 22 , G 42  to G 2n , G 4n . Accordingly, all of the transfer gates Tg become conductive, and all of the pixel signals of the photodiodes are transferred to the adjacent transfer pixels. 
     As already described referring to FIG. 17, the exposure process has been completed just before the time t 2 , and the removal of the unnecessary charges has also been completed. During the period T VB , a so-called field shift operation is performed, so that at the time t 2  in FIG. 22, the pixel signals (marked as shaded squares) are transferred to the vertical charge transfer paths. FIG. 22 is a view showing the charge transfer operation of one vertical charge transfer path. During the period T HB  corresponding to the first horizontal blanking period, the timing signal φ G  is always at the &#34;L&#34; level. Accordingly, all of the NMOS transistors in the first drive circuit 10 become nonconductive and are separated from all of the gate electrodes. 
     Only the drive signal S 1  at the first output terminal of the third drive circuit 12 is set at the &#34;M&#34; level, while the remaining drive signals S 2  to S n , are at the &#34;L&#34; level. This renders only the first set of NMOS transistors m 11 , m 21 , m 31 , m 41  conductive due to the drive signal S 1  of the second drive circuit 11. 
     During the period when only the drive signal S 1  is set at the &#34;M&#34; level, the timing signals φ 1 , φ 2 , φ 3 , and φ 4  of four phases for the vertical charge transfer are supplied to the second drive circuit 11. Accordingly, only the first set of gate signals φ 11 , φ 21 , φ 31 , and φ 41  are equal in level to the timing signals φ 1 , φ 2 , φ 3 , and φ 4 . The charge transfer is performed by the first set of gate electrodes G 11 , G 21 , G 31 , and G 41 . The enlarged signal waveforms during the period T HB  are shown in FIG. 19. 
     As a consequence, the signal charges are transferred to the horizontal charge transfer path 8 at the times (indicated by numerals 1, 2, 3, 4, 5, 6, and 7) of the gate signals φ 11 , φ 21 , φ 31 , and φ 41  in FIG. 19, as in the first transfer shown in FIG. 22. A pixel signal q 1j  of the first line closest to the horizontal charge transfer path 8 is transferred to the transfer path 8. A pixel signal q 2j  of the second line moves to the first line position. 
     Then, during the first horizontal scan period T 1H  (between times t 4  and t 5 ), the variation of the signal applied to each gate electrode stops, and the horizontal charge transfer path 8 vertically transfers signal charges in synchronism with the gate signals α 1  to α 4  recurring at predetermined times according to the four- or two-phase drive system. As a result, pixel signals of the first line are read out. 
     During a period between times t 5  to t 7 , a sequence of operations, which is similar to that during the period between times t 3  to t 5 , is repeated to read the pixel signals of the next line out of the image pick-up device. During the horizontal blanking period T HB  between times t 3  to t 4 , the drive signals S 1  and S 2  of the third drive circuit 12 are simultaneously set to the &#34;M&#34; level and the remaining drive signals S 3  to S n  are set to the &#34;L&#34; level. The enlarged signal waveforms during this period T HB  are shown in FIG. 20. 
     Consequently, a set of the first to fourth gate electrodes G 11  to G 41 , and two sets of fifth to eighth gate electrodes G 12  to G 42  are driven by the gate signals φ 11  to φ 41  and φ 12  to φ 42 , which are equal to the timing signals φ 1 , φ 2 , φ 3 , and φ 4 . The result is the vertical transfer of the pixel signals under those gate electrodes. 
     The timing chart shown in FIG. 20 shows that as indicated by the second vertical scan in FIG. 22, the pixel signal q 2j  of the second line is transferred to the horizontal charge transfer path 8. Two lines of the pixel signals q 3j  of the third line and one line of the pixel signal q 4j  of the fourth line are transferred to the horizontal charge transfer path 8. 
     During the horizontal scan period T 1H  between times t 6  and t 7 , the horizontal charge transfer path 8 reads out the pixel signal q 2j  of the second line. 
     The third scan read starts at time t 7 . Then, the drive signals S 1 , S 2 , and S 3  are set at the &#34;M&#34; level, while the remaining drive signals S 4  to S n  of the third drive circuit 12 are set at the &#34;L&#34; level. The first to third sets of first to 12th gate electrodes G 11  to G 41 , G 12  to G 42  to G 42 , and G 13  to G 42  are driven for the vertical charge transfer. Accordingly, as in the third transfer of FIG. 22, the pixel signal q 3j  of the third line is transferred to the horizontal charge transfer path 8. The pixel signals q 4j  to q 7j  of the 4th to 7th lines are transferred every line to the horizontal charge transfer path 8. 
     Then, the pixel signal q 3j  is read out of the photodiodes by the horizontal charge transfer path 8. 
     Subsequently, the drive signals S 4  to S n  of the third drive circuit 12 are progressively inverted to &#34;M&#34; level every time the pixel signal of each line is read out. The gate electrodes to be driven are increased every four gate electrodes. During the horizontal blanking period T HB  (between times t 9  and t 10 ), all of the gate signals φ 11  to φ 4n  have the same waveforms as those of the timing signals φ 1  to φ 4 , as shown in FIG. 21. The pixel signals of the last line are read out by the final scan read operation. 
     FIG. 23 shows the K-th and (K+1)th vertical charge transfer operations, for example, in terms of potential profiles. As shown, in order from the transfer pixel closest to the horizontal charge transfer path 8, the intervals of the idle transfer pixels progressively increase. With this the pixel signals are progressively read out in the order from the pixel signal closest to the transfer path 8 to the succeeding ones. 
     It will be appreciate that, in the present embodiment, the pixel signals of one frame can be read out by a single frame scan read operation. 
     The width of the odd-numbered gate electrodes is wider than that of the even-numbered gate electrodes. This feature advantageously allows an increase in a charge retaining capacitance of the transfer pixels adjacent to the transfer gates. Additionally, during the vertical charge transfer, the transfer pixels under the even-numbered gate electrodes are used for the charge transfer, thereby improving the charge transfer efficiency. 
     It will also be apparent that the charge transfer is performed in synchronism with the four-phase timing signals φ 1 , φ 2 , φ 3 , and φ 4  during the period T HB  corresponding to each horizontal blanking period. If necessary, timing signals having four or more phases may be used for driving the gate electrodes corresponding to the number of phases. 
     The solid-state image pick-up device thus arranged can read all of the pixel signals of one frame through one-time frame scan read operation. Therefore, exposure through the electronic shutter can be applied to all of the pixel signals under the same conditions. Accordingly, the image pick-up device can reproduce a clear image having a high vertical resolution. 
     As described above, in the solid-state image pick-up device of the CCD type according to the invention, the exposure is performed at the grouped optoelectric transducing elements corresponding to the pixels allowing the pixel signals generated in the optoelectric transducing elements to be read out through the vertical and horizontal charge transfer paths by a full-frame scan read operation. Accordingly, still picture reproduction is clear. 
     It will be appreciated that the solid-state CCD image pick-up device provides a so-called electronic shutter function such that a predetermined voltage applied to the semiconductor substrate to drain excessive or unnecessary charges into the substrate, and the exposure starts at the time of completing the excessive charge drainage. 
     Additionally, the paired gate electrodes adjacent to each other cause the transfer paths to generate therein the transfer pixels and potential barriers. Accordingly, the transfer paths can transfer charges while preventing the charges from being mixed. This realizes the most efficient charge transfer and provides a means to effectively improve the vertical resolution. 
     Another preferred embodiment of the present invention, which includes a third drive circuit 12, will be described with reference to FIG. 24. The third drive circuit 12 consists of a shift register for shifting a start pulse φ S  in synchronism with two-phase clock signal φ A  and φ B  to sequentially generate drive signals of logic &#34;H&#34; in the order from the low- order bit to the high-order bit. In the first period, only the first drive signal S 1  goes high (&#34;H&#34;), while the remaining high-order bits are all low (&#34;L&#34;) in logic level. In the second period, two low-order bits S 1  and S 2  go high, while the remaining high-order bits are low. In the third period, three low-order bits S 1 , S 2 , and S 3  go high, while the remaining high-order bits are low. Thus, the number of high drive signals progressively increases in order from the low-order bits to the high-order bits. 
     As shown in FIG. 24, each bit has a corresponding cell structure, and hence the circuit of the first bit will be typically described. The source-drain paths of three MOS u 11 , u 12 , u 13 , and u 14  are connected in series between a signal line of the voltage V L  and a signal line of the clock signal φ B . A signal line for the reset signal RS is connected to the gate contact of the transistor u 13 . A bootstrap capacitor .di-elect cons. 11  is connected between the gate contact and the drain contact of the transistor u 11 . The gate contact and the source contact of the transistor u 12  are connected to each other, and to the source contact of the transistor u 14 . The transistor u 14  is connected at the drain contact to the signal line for the voltage V L  and at the gate contact to the signal line for the clock signal φ A . 
     Transistors MOS u 22 , u 22 , u 23 , and u 24  make up the same circuit as that made up of the transistors MOS u 11 , u 12 , u 13 , and u 14 . The drain contact (output point) of the transistor u 12  is connected to the gate contact (input point) of the transistor u 22 . However, the connection of the signals φ A  and φ B  thereto is inverted. 
     The bit input corresponds to the gate contact of the gate contact of the transistor u 11 . The bit output corresponds to the drain contact of the transistor u 22 . An n-bit shift register is formed by connecting the inputs and outputs of those bit cells in a cascade fashion. A start pulse φ S  is inputted to the least significant bit cell through an analog switch u 00  which is rendered conductive in synchronism with the clock signal φ A . 
     The second and third drive circuits 11 and 12 are each composed of an NMOS transistor formed in the p-well layer 16 shown in FIG. 16, and other electronic components. A plurality of n +   impurity layers 25 and 26 forming an NMOS transistor and a gate contact, by way of example, are formed in the p-well layer 15 shown in FIG. 6. 
     The scan read operation will be described in detail with reference to FIG. 18 showing a timing chart of drive signals and timing signals. In the figure, the period T VB  corresponds to the vertical blanking period, the period T HB  corresponds to the horizontal blanking period, and the period T 1H  corresponds to the horizontal scan period. Further, &#34;H&#34; indicates a voltage of 12 V, &#34;M&#34; is a voltage of about 0 V, &#34;L&#34; is a voltage of about -8 V, and &#34;HH&#34; is approximately 15 to 25 V, which is equal to the substrate voltage. The operation of this preferred embodiment will be discussed while referring generally to FIGS. 17-23. 
     During the period T VB  corresponding to the vertical blanking period, the timing signal φ H  goes high (H) at a predetermined time t2, and is at the &#34;M&#34; level at the remaining time. The timing signal φ G  is always at the &#34;M&#34; level. The timing signal φ FS  goes high (H) as the timing signal φ H  goes high, and is kept at the &#34;L&#34; level at the remaining time. The drive signals S 1  to S n  generated from the third drive circuit 12 are always at the &#34;L&#34; level. 
     During the period T VB , all of the NMOS transistors of the first drive circuit 10 are rendered conductive by the timing signal φ G  at the &#34;M&#34; level, while at the same time all of the drive signals S 1  to S n  of the third drive circuit 12 are set to the &#34;L&#34; level. Accordingly, all of the NMOS transistors in the second drive circuit 11 become conductive. All of the gate electrodes G 11 , G 21 , G 31 , G 41 , to G 1n , G 2n , G 4n  are controlled by the first drive circuit 10. 
     More specifically, when the timing signals φ H  and φ FS  are not at the &#34;H&#34; level, the gate signals φ 11 , φ 31 , φ 12 , φ 32  to φ 1n , φ 3n , which are applied to the odd-numbered gate electrodes G 11 , G 31 , G 12 , G 32  to G 1n , G 3n , are each equal in voltage level to the signal V L  (constantly set at -8 V). Under this condition, potential barriers are generated in the vertical charge transfer paths L 1  to L m  under those gate electrodes. 
     The gate signals φ 21 , φ 41 , φ 22 , φ 42  to φ 2n , φ 4n , which are applied to the even-numbered gate electrodes G 21 , G 41 , G 22 , G 42  to G 2n , G 4n , are each equal in voltage to the signal φ H  at the &#34;M&#34; level. Under this condition, transfer pixels are generated in the vertical charge transfer paths L 1  to L m  under those gate electrodes. 
     Accordingly, all of the portions adjacent to the transfer gates Tg (see FIG. 14) serve as the transfer pixels being separated from one another by the potential barriers. 
     Under this condition, when the timing signals φ H  and φ FS  go high at time t2, all of the npn transistors Q 21 , Q 41 , Q 61 , . . . become conductive, and the &#34;H&#34; level voltage of approximately 15 to 25 V is applied to only the even-numbered gate electrodes G 21 , G 41 , G 22 , G 42  to G 2n , G 4n . Accordingly, all of the transfer gates Tg become conductive, and all of the pixel signals of the photodiodes are transferred to the adjacent transfer pixels. 
     During the period T VB , a so-called field shift operation is performed, so that as at the time t 2  shown in FIG. 22, the pixel signals (marked as black squares) are transferred to the vertical charge transfer paths. 
     During the period T HB  corresponding to the first horizontal blanking period, the timing signal φ G  is always at the &#34;L&#34; level. Accordingly, all of the NMOS transistors in the first drive circuit 10 become nonconductive and are separated from all of the gate electrodes. 
     Only the drive signal S 1  at the first output terminal of the third drive circuit 12 is set at the &#34;M&#34; level, while the remaining drive signals S 2  to S n , are at the &#34;L&#34; level. This renders conductive only the first set of NMOS transistors m 11 , m 21 , m 31 , m 41  concerning the drive signal S 1  of the second drive circuit 11. 
     During the period that only the drive signal S 1  is set to &#34;M&#34; level, the timing signals φ 1 , φ 2 , φ 3 , and φ 4  of four phases for the vertical charge transfer are inputted to the second drive circuit 11. Accordingly, only the first set of first to fourth gate signals φ 11 , φ 21 , φ 31 , and φ 41  are equal in level to the timing signals φ 1 , φ 2 , φ 3 , and φ 4 . The charge transfer is performed by the first set of first to fourth gate electrodes G 11 , G 21 , G 31 , and G 41 . The enlarged signal waveforms during the period T HB  are shown in FIG. 19. 
     Consequently, the signal charges are transferred to the horizontal charge transfer path 8 at the times (indicated by numerals 1, 2, 3, 4, 5, 6, and 7) of the gate signals φ 11 , φ 21 , φ 31 , and φ 41  in FIG. 9, as in the first transfer shown in FIG. 22. A pixel signal q 1j  of the first line closest to the horizontal charge transfer path 8 is transferred to the transfer path 8. A pixel signal q 2j  of the second line moves to the first line position. 
     Then, during the first horizontal scan period T 1H  (between times t 4  and t 5 ), the variation of the signal applied to each gate electrode stops, and the horizontal charge transfer path 8 vertically transfers signal charges in synchronism with the gate signals α 1  to α 4  recurring at predetermined times according to the four- or two-phase drive system. As a result, pixel signals of the first one line are read out. 
     During a period between times t 5  to t 7 , a sequence of operations, which is similar to that during the period between times t 3  to t 5 , is repeated to read the pixel signals of the next line out of the image pick-up device. During the horizontal blanking period T HB  between times t 3  to t 4 , the drive signals S 1  and S 2  of the third drive circuit 12 are simultaneously set to &#34;M&#34; level, and the remaining drive signals S 3  to S n  are set to &#34;L&#34; level. The enlarged signal waveforms during this period T HB  are shown in FIG. 20. 
     As a result, a set of the first to fourth gate electrodes G 11  to G 41 , and two sets of fifth to eighth G 12  to G 42  are driven by the gate signals φ 11  to φ 41  and φ 12  to φ 42 , which are equal to the timing signals φ 1 , φ 2 , φ 3 , and φ 4 . The result is the vertical transfer of the pixel signals under those gate electrodes. 
     The timing chart shown in FIG. 20 shows that as indicated by the second vertical scan in FIG. 22, the pixel signal q 2j  of the second line is transferred to the horizontal charge transfer path 8. Two lines of the pixel signals q 1j  of the third line and one line of the pixel signal of the fourth line are transferred to the horizontal charge transfer path 8. During the horizontal scan period T 1H  between times t 6  and t 7 , the horizontal charge transfer path 8 reads out the pixel signal q 2j  of the second line. 
     The third scan read starts at time t 7 . Then, the drive signals S 1 , S 2 , and S 3  are set to &#34;M&#34; level, while the remaining drive signals S 4  to S n  of the third drive circuit 12 are set to &#34;L&#34; level. The first to third sets of first to 12th gate electrodes G 11  to G 41 , G 12  to G 42  to G 42 , and G 13  to G 42  are driven for the vertical charge transfer. Accordingly, as in the third transfer of FIG. 12, the pixel signal q 3j  of the third line is transferred to the horizontal charge transfer path 8. The pixel signals q 4j  to q 5j  of the 4th to 6th lines are transferred every two lines to the horizontal charge transfer path 8. The pixel signal q 6j  of one line is transferred to there. 
     Then, the pixel signal q 3j  is read out of the photodiodes by the horizontal charge transfer path 8. 
     Subsequently, the drive signals S 4  to S n  of the third drive circuit 12 are progressively inverted to &#34;M&#34; level every time the pixel signal of each line is read out. The gate electrodes to be driven are increased every four gate electrodes. During the horizontal blanking period T HB  (between times t 9  and t 10 ), all of the gate signals φ 11  to φ 4n  have the same waveforms as those of the timing signals φ 1  to φ 4 , as shown in FIG. 11. The pixel signals of the last line are read out by the final scan read operation. 
     FIG. 23 shows the K-th and (K+1)th vertical charge transfer operations, for example, in terms of potential profiles. As shown, in order from the transfer pixel closest to the horizontal charge transfer path 8, the intervals of the idle transfer pixels progressively increase. With this, the pixel signals are progressively read out in the order from the pixel signal closest to the transfer path 8 to the succeeding ones. 
     The preferred embodiment of the present embodiment discussed immediately above comprises a drive circuit for supplying the gate signal to the gate electrode constructed with MOS transistors of the NMOS structure, not CMOS structure, and transistors of the bipolar structure. Accordingly, the resultant drive circuits have a high breakdown voltage, and allow the vertical overflow drain and the electronic shutter function to be advantageously incorporated. 
     With provision of the vertical overflow drain structure, the excessive charges of the photodiodes can be drained into the substrate, removing unwanted phenomenon including blooming. Preferably, an electronic shutter which does not use the substrate is formed, and with the electronic shutter, the noninterlace/full frame read is possible. In this respect, the image pick-up device is suitable for photographing a still picture. 
     In the image pick-up device thus constructed, high breakdown performance is realized because the impurity concentration of the semiconductor substrate and the well layer is relatively low. The breakdown performance realized is enough to withstand the high voltage needed to realize the vertical overflow drain function, and also the high voltage needed to operate the electronic shutter. 
     According to the present invention, a well layer is formed in the semiconductor substrate, a circuit using MOS transistors of a single structure is formed in the well layer. Therefore, the resultant image pick-up device is improved in breakdown voltage performance, and the vertical overflow drain structure and the electronic shutter function may be introduced into the device. 
     Another preferred embodiment of the present invention, including a modified form of the third drive circuit 12, will be described with reference to FIG. 24. The third drive circuit 12 includes a shift register for shifting a start pulse φ S  in synchronism with two-phase clock signal φ A  and φ B  to sequentially generate drive signals of logic &#34;H&#34; in the order from the low- order bit to the high-order bit. In the first period, only the first drive signal S 1  goes high (&#34;H&#34;), while the remaining high-order bits are all low (&#34;L&#34;) in logic level. In the second period, two low-order bits S 1  and S 2  go high, while the remaining high-order bits are low. In the third period, three low-order bits S 1 , S 2 , and S 3  go high, while the remaining high-order bits are low. Thus, the number of high drive signals progressively increases in order from the low-order bits to the high-order bits. 
     As shown in FIG. 24, each bit has a cell structure, and hence the circuit of the first bit will be typically described. The source-drain paths of three MOS u 11 , u 12 , u 13 , and u 14  are connected in series between a signal line of the voltage V L  and a signal line of the clock signal φ B . A signal line for the reset signal RS is connected to the gate contact of the transistor u 13 . A bootstrap capacitor .di-elect cons. 11  is connected between the gate contact and the drain contact of the transistor u 11 . The gate contact and the source contact of the transistor u 12  are connected to each other, and to the source contact of the transistor u 14 . The transistor u 14  is connected at the drain contact to the signal line for the voltage V L  and at the gate contact to the signal line for the clock signal φ A . 
     Transistors MOS u 22 , u 22 , u 23 , and u 24  make up the same circuit as that made up of the transistors MOS u 11 , u 12 , u 13 , and u 14 . The drain contact (output point) of the transistor u 12  is connected to the gate contact (input point) of the transistor u 22 . However, the connection of the signals φ A  and φ B  thereto is inverted. The bit input corresponds to the gate contact of the gate contact of the transistor u 11 . The bit output corresponds to the drain contact of the transistor u 22 . An n-bit shift register is formed by connecting the inputs and outputs of those bit cells in a cascade fashion. A start pulse φ S  is inputted to the least significant bit cell through an analog switch u 00  which is rendered conductive in synchronism with the clock signal φ A . 
     The third drive circuit 12 includes a shift register for producing drive signals S 1  to S n  at predetermined times, as described above. 
     The scan read operation will be described in detail with reference to FIG. 18. The period T VB  corresponds to the vertical blanking period, the period T HB  corresponds to the horizontal blanking period, period T 1H  corresponds to the horizontal scan period. Further, &#34;H&#34; indicates 12 V, &#34;M&#34; indicates 0 V, &#34;L&#34; indicates -8 V, and &#34;HH&#34; is approximately 12 V, which is equal to the substrate voltage. 
     During the period T VB , the timing signal φ H  goes high (H) at a predetermined time t2, and is at the &#34;M&#34; level during the remaining time. The timing signal φ G  is always at the &#34;M&#34; level. The timing signal φ FS  goes high (H) as the timing signal φ H  goes high, and is kept at the &#34;L&#34; level during the remaining time. The drive signals S 1  to S n  generated from the third drive circuit 12 are always in &#34;L&#34; level. 
     During the period T VB , all of the NMOS transistors of the first drive circuit 10 are rendered conductive by the timing signal φ G  at the &#34;M&#34; level, while all of the drive signals S 1  to S n  of the third drive circuit 12 are set to the &#34;L&#34; level. Accordingly, all of the NMOS transistors in the second drive circuit 11 become conductive. All of the gate electrodes G 11 , G 21 , G 31 , G 41  to G 1n , G 2n , G 4n  are controlled by the first drive circuit 10. 
     More specifically, when the timing signals φ H  and φ FS  are not at the &#34;H&#34; level, the gate signals φ 11 , φ 31 , φ 12 , φ 32  to φ 1n , φ 3n , which are applied to the odd-numbered gate electrodes G 11 , G 31 , G 12 , G 32  to G 1n , G 3n , are each equal in voltage level to the signal V L  (constantly set at -8 V). Under this condition, potential barriers are generated in the vertical charge transfer paths L 1  to L m  under those gate electrodes. 
     The gate signals φ 21 , φ 41 , φ 22 , φ 42  to φ 2n , φ 4n , which are applied to the even-numbered gate electrodes G 21 , G 41 , G 22 , G 42  to G 2n , G 4n , are each equal in voltage to the signal φ H  at the &#34;M&#34; level. Under this condition, transfer pixels are generated in the vertical charge transfer paths L 1  to L m  under those gate electrodes. 
     Accordingly, all of the portions adjacent to the transfer gates Tg (see FIG. 14) serve as the transfer pixels being separated from one another by the potential barriers. 
     Under this condition, when the timing signals φ H  and φ FS  go high at time t2, all of the npn transistors Q 21 , Q 41 , Q 61 , . . . become conductive, and the &#34;H&#34; level voltage of approximately 15 to 25 V is applied to only the even-numbered gate electrodes G 21 , G 41 , G 22 , G 42  to G 2n , G 4n . Accordingly, all of the transfer gates Tg become conductive, and all of the pixel signals of all of the photodiodes are transferred to the adjacent transfer pixels. 
     During the period T VB , a so-called field shift operation is performed, so that as at time t 1  in FIG. 22, the pixel signals (marked as shaded squares) are transferred to the vertical charge transfer paths. During the period T HB  corresponding to the first horizontal blanking period, the timing signal φ G  is always in &#34;L&#34; level. Accordingly, all of the NMOS transistors in the first drive circuit 10 become nonconductive and are separated from all of the gate electrodes. 
     Only the drive signal S 1  at the first output terminal of the third drive circuit 12 is set at the &#34;M&#34; level, while the remaining drive signals S 2  to S n , are at the &#34;L&#34; level. This renders conductive only the first set of NMOS transistors m 11 , m 21 , m 31 , m 41  concerning the drive signal S 1  of the second drive circuit 11. 
     During the period that only the drive signal S 1  is set to &#34;M&#34; level, the timing signals φ 1 , φ 2 , φ 3 , and φ 4  of four phases for the vertical charge transfer are inputted to the second drive circuit 11. Accordingly, only the first set of first to fourth gate signals φ 11 , φ 21 , φ 31 , and φ 41  are equal in level to the timing signals φ 1 , φ 2 , φ 3 , and φ 4 . The charge transfer is performed by the first set of first to fourth gate electrodes G 11 , G 21 , G 31 , and G 41 . The enlarged signal waveforms during the period T HB  are shown in FIG. 19. 
     As a consequence, the signal charges are transferred to the horizontal charge transfer path 8 at the times (indicated by numerals 1, 2, 3, 4, 5, 6, and 7) of the gate signals φ 11 , φ 21 , φ 31 , and φ 41  in FIG. 19, as in the first transfer shown in  -10 FIG. 22. A pixel signal q 1j  of the first line closest to the horizontal charge transfer path 8 is transferred to the transfer path 8. A pixel signal q 2j  of the second line moves to the first line position. 
     Then, during the first horizontal scan period T 1H  (between is times t 4  and t 5 ), the variation of the signal applied to each gate electrode stops, and the horizontal charge transfer path 8 vertically transfers signal charges in synchronism with the gate signals α 1  to α 4  recurring at predetermined times according to the four-phase drive system. As a result, pixel signals of the first one line are read out. 
     During a period between times t 5  to t 7 , a sequence of operations, which is similar to that during the period between times t 3  to t 5 , is repeated to read the pixel signals of the next line out of the image pick-up device. During the horizontal blanking period T HB  between times t 3  to t 4 , the drive signals S 1  and S 2  of the third drive circuit 12 are simultaneously set to &#34;M&#34; level, and the remaining drive signals S 3  to S n  are set to &#34;L&#34; level. The enlarged signal waveforms during this period T HB  are shown in FIG. 20. 
     As a result, a set of the first to fourth gate electrodes G 11  to G 41 , and two sets of fifth to eighth G 12  to G 42  are driven by the gate signals φ 11  to φ 41  and φ 12  to φ 42 , which are equal to the timing signals φ 1 , φ 2 , φ 3 , and φ 4 . The result is the vertical transfer of the pixel signals under those gate electrodes. 
     The timing chart shown in FIG. 20 shows that as indicated by the second vertical scan in FIG. 22, the pixel signal q 2j  of the second line is transferred to the horizontal charge transfer path 8. Two lines of the pixel signals q 3j  of the third line and the pixel signal q 4j  of the fourth line are transferred to the horizontal charge transfer path 8. 
     During the horizontal scan period T 1H  between times t 6  and t 7 , the horizontal charge transfer path 8 reads out the pixel signal q 2j  of the second line. 
     The third scan read starts at time t 7 . Then, the drive signals S 1 , S 2 , and S 3  are set to &#34;M&#34; level, while the remaining drive signals S 4  to S n  of the third drive circuit 12 are set to &#34;L&#34; level. The first to third sets of first to 12th gate electrodes G 11  to G 41 , G 12  to G 42  to G 42 , and G 13  to G 42  are driven for the vertical charge transfer. Accordingly, as in the third transfer of FIG. 22, the pixel signal q 3j  of the third line is transferred to the horizontal charge transfer path 8. The pixel signals q 4j  to q 5j  of the 4th to 7th lines are transferred every two lines to the horizontal charge transfer path 8. The pixel signal q 6j  of one line is transferred to there. 
     Then, the pixel signal q 3j  is read out of the photodiodes by the horizontal charge transfer path 8. 
     Subsequently, the drive signals S 4  to S n  of the third drive circuit 12 are progressively inverted to the &#34;M&#34; level every time the pixel signal of each line is read out. The gate electrodes to be driven are increased every four gate electrodes. During the horizontal blanking period T HB  (between times t 9  and t 10 ), all of the gate signals φ 11  to φ 4n  have the same waveforms as those of the timing signals φ 1  to φ 4 , as shown in FIG. 21. The pixel signals of the last line are read out by the final scan read operation. 
     FIG. 23 shows the K-th and (K+1)th vertical charge transfer operations, for example, in terms of potential profiles. As shown, in order from the transfer pixel closest to the horizontal charge transfer path 8, the intervals of the idle transfer pixels progressively increase. With this, the pixel signals are progressively read out in the order from the pixel signal closest to the transfer path 8 to the succeeding ones. 
     Thus, in the still picture photographing mode, all of the pixel signals can be generated by one-time frame scan read, and the pixel signals may be scan read without mixing them. Accordingly, the image pick-up device of the embodiment can reproduce a still picture at a high resolution, which is free from flicker, pseudocolor and the like. 
     The operation of the image pick-up device when it is in the motion picture photographing mode will be described. In this mode, the odd-numbered field and the even-numbered field, which are shifted by one line one from the other, are field scan read, to complete the interlace scan read. 
     The basic times of scan reading the respective fields are substantially the same as those shown in FIGS. 17 and 18 except the signal times during the period T HB  corresponding to the horizontal blanking period. 
     For the scan read of the odd-numbered field, the times during the period from t 3  to t 4  in FIG. 18 is replaced by the times shown in FIG. 25, the times during the period from t 5  to t 6  in FIG. 18 are replaced by the times shown in FIG. 26, and the times during the period from t 9  to t 10  in FIG. 18 are replaced by the times shown in FIG. 27. The times during the horizontal scan period T 1H  remains unchanged. 
     For the scan read of the even-numbered field, the times during the period from t 3  to t 4  in FIG. 18 are replaced by the times shown in FIG. 28, the times during the period from t 5  to t 6  in FIG. 18 are replaced by the times shown in FIG. 29, and the times during the period from t 9  to t 10  in FIG. 18 are replaced by the times shown in FIG. 30. The times during the horizontal scan period T 1H  remains unchanged. 
     To start the scan read of the odd-numbered field, the exposure is set up and continued, and during the vertical blanking period T VB , the pixel signals of all of the photodiodes are shifted to the transfer pixels under the even-numbered gate electrodes G 21 , G 41 , G 22 , G 42 , . . . , G 2n , G 4n  of the vertical charge transfer paths L 1  to L m . 
     Then, during the first horizontal blanking period (see FIG. 25), the first and second drive signals S 1  and S 2  of the third drive circuit 12 vary over two periods as shown. The timing signals φ 1 , φ 2 , φ 3 , and φ 4  of the second drive circuit 11 are supplied two times for each period. Accordingly, during the first period of the period from t 3  to t 4 , the gate signals φ 11  to φ 41  are applied to only the first set of gate electrodes G 11  to G 41 . During the next period, the gate signals φ 11  to φ 41  and φ 12  to φ 42  are respectively applied to the first set of gate electrodes G 11  to G 41  and the second set of gate electrodes G 12  to G 42 . 
     As shown in FIG. 25, the pixel signals of the transfer pixels under the first set of the gate electrodes G 21  and the pixel signals of the transfer pixels under the second set of the gate electrodes G 22  are shifted to the transfer pixels of the horizontal charge transfer path 8 where those pixel signals are mixed. 
     During the first horizontal scan period T 1H , the horizontal charge transfer path 8 horizontally scans to time sequentially output the mixed pixel signals. 
     Then, during the second horizontal blanking period (see FIG. 26), the first to fourth drive signals S 1  to S 4  from the third drive circuit 12 vary over the two periods as shown. As a result, the pixel signals under the third and fourth gate electrodes G 13  to G 43  and G 14  to G 44  are transferred to and mixed in the horizontal charge transfer path 8. 
     During the next horizontal scan period T 1H , the horizontal charge transfer path 8 horizontally scans to time sequentially output the mixed pixel signals of the second line. 
     The above sequence of operations is repeated during the respective horizontal blanking periods and horizontal scan periods, so that the drive signals S 1  to S n  from the third drive circuit 12 are generated progressively expanding. As in the above case, the horizontal charge transfer path 8 outputs all of the pixel signals while mixing them. 
     FIG. 27 shows times of reading out the pixel signals of the last line. 
     FIG. 31 is a diagram of potential profiles showing charge transfer operations by the first to sixth gate electrodes during the first horizontal blanking period T HB  (times t 3  to t 4 ). At times 0 to 8 and 0 to 6, the potential variations with respect time are profiled as shown. 
     The scan read of the even-numbered field will be described. To start, the exposure is set up and continued, and during the vertical blanking period T VB  in FIG. 18, the pixel signals of all of the photodiodes are shifted to the transfer pixels under the even-numbered gate electrodes G 21 , G 41 , G 22 , G 42 , G 2n , G 4n , of the vertical charge transfer paths L 1  to L m . 
     Then, during the first horizontal blanking period (see FIG. 28), the first drive signal S 1  of the third drive circuit 12 vary over two periods as shown. The timing signals φ 1 , φ 2 , φ 3 , and φ 4  of the second drive circuit 11 are supplied for the later period. Accordingly, during the period from t 3  to t 4 , the gate signals φ 11  to φ 41  are applied to only the gate electrodes G 11  to G 41 . 
     As shown in FIG. 28, the pixel signals of the transfer pixels under the first set of the gate electrodes G 21  are shifted to the transfer pixels of the horizontal charge transfer path 8. During the first horizontal scan period T 1H , the horizontal charge transfer path 8 horizontally scans to time sequentially output the mixed pixel signals. The signals read out by the first scan read are discharged as unnecessary signals. 
     Then, during the second horizontal blanking period (see FIG. 29), the first to third drive signals S 1  to S 3  from the third drive circuit 12 vary over the two periods as shown. As a result, the pixel signals under the first and second gate electrodes G 31  to G 41  and G 12  to G 42  are transferred to and mixed in the horizontal charge transfer path 8. The pixel signals under the third set of gate electrodes G 13  to G 23  are transferred to under the first set of gate electrodes. 
     During the next horizontal scan period T 1H , the horizontal charge transfer path 8 horizontally scans to time sequentially output the mixed pixel signals of the second line. 
     The above sequence of operations is repeated during the respective horizontal blanking periods and horizontal scan periods, so that the drive signals S 1  to S n  from the third drive circuit 12 are generated progressively expanding. As in the above case, the horizontal charge transfer path 8 outputs all of the pixel signals while mixing them. 
     FIG. 30 shows times of reading out the pixel signals of the last line. 
     FIG. 32 is a diagram of potential profiles showing charge transfer operations by the first to sixth gate electrodes during the first horizontal blanking period T HB  (times t 5  to t 6 ) in FIG. 29. At times 0 to 8 and 0 to 6, the potential variations with respect time are profiled as shown. 
     As seen from FIGS. 31 and 32, in the motion picture photographing mode as mentioned above, the mixing and combination of the pixel signals in the odd-numbered field are shifted by one line from those in the even-numbered field. Therefore, the interlace scan read is realized. 
     Another embodiment of a solid-state image pick-up device of the CCD type will be described. The structure of the image pick-up device is illustrated in FIG. 33 corresponding to FIG. 14. The differences between the FIG. 33 structure and the FIG. 14 structure is primarily that npn transistors Q 41 , Q 42 , Q 43  . . . are controlled by the first field shift signal φ FSA , and npn transistors Q 21 , Q 22 , Q 23 , . . . by the second shift signal φ FSB . Those shift signals φ FSA  and φ FSB  are generated by the sync control circuit 6. The remaining structure of the second embodiment resembles that shown in FIGS. 13-16 and 23. When the image pick-up device is applied to a camera, for example, the structure is substantially the same as that of FIG. 12. 
     The still picture photographing mode proceeds at the same times as those in FIGS. 17 through 21 with some exceptions. 
     The shift signal φ FSA  and φ FSB  shown in FIG. 33 are substituted by the signal φ FS . All of the transistors Q 21 , Q 41 , Q 22 , Q 42 , Q 23 , Q 43  . . . in FIG. 33 are controlled by the signal φ FS . The operation of the still picture photographing mode proceeds is equal to that of the first embodiment. The transfer of the pixel signals is performed as shown in FIGS. 22 and 23, realizing the noninterlace/full frame scan read. 
     In the motion picture photographing mode, all of the output signals S 1  to S n  of the third drive circuit 12 are set to &#34;M&#34; level, and all of the transistors m 11 , m 21 , m 31 , m 41  to m 1n , m 2n , m 3n , m 4n  are made conductive. In the scan read mode of the odd-numbered field, the first field shift signal φ FSA  is set to &#34;H&#34; level, and the second shift signal φ FSB  is set to &#34;L&#34;. Under this condition, the odd-numbered field is shifted to scan read pixel signals according to the four-phase drive system of the timing signals φ 1 , φ 2 , φ 3 , and φ 4 . In the scan read mode of the even-numbered field, the first field shift signal φ FSA  is set to &#34;L&#34; level, and the second shift signal φ FSB  is set to &#34;H&#34;. Under this condition, the odd-numbered field is shifted to scan read pixel signals according to the four-phase drive system of the timing signals φ 1 , φ 2 , φ 3 , and φ 4 . In this way, the motion picture is photographed in the interlace scan read mode. 
     Still another embodiment of a solid-state image pick-up device of the CCD type will be described. The structure of the image pick-up device shown in FIGS. 13, 14 and 23 is available for that of the image pick-up device of this embodiment. The still picture photographing mode is equal to that of the first embodiment. 
     The operation of the picture photographing mode will described. The times of the respective signals are similar to those in FIG. 18, but the times of the vertical blanking period T VB  shown in FIG. 18 are replaced by the times shown in FIG. 34 in the scan read mode for the odd-numbered field, and the times shown in FIG. 35 in the scan read mode for the even-numbered field. 
     In the scan read mode for the odd-numbered field, during the vertical blanking period T VB , as shown in FIG. 18, the field shift signal φ FSA  is set to &#34;H&#34; level, so that the pixel signals corresponding to all of the pixels are transferred to the transfer pixels under the even-numbered gate electrodes of each set. Then, the signal φ G  is set to &#34;L&#34; level, and all of the output signals S 1  to S n  of the third drive circuit 12 are set to &#34;M&#34; level, to render all of the transistors m 11 , m 21 , m 31 , m 41  to m 1n , m 2n , m 3n , m 4n  conductive. Under this condition, at times 0, 1, 2, 3, 0 the gate signals φ 11  to φ 4n  corresponding to the timing signals φ 1 , φ 2 , φ 3 , and φ 4  are applied to the gate electrodes G 11  to G 4n . Then, according to the potential profile as shown in FIG. 36, a pair of pixel signals are mixed and retained in the transfer pixels the second gate electrodes of each set. The transfer pixels under the fourth gate electrodes of each set are empty. 
     The scan read is applied at the times (see FIG. 8) similar to those in the still picture photographing mode of the first embodiment, thereby to perform the scan read for the odd-numbered field. 
     In the scan read mode for the even-numbered field, during the vertical blanking period T VB  as shown in FIG. 35, the field shift signal φ FS  is set to &#34;H&#34; level, so that the pixel signals corresponding to all of the pixels are transferred to the transfer pixels under the even-numbered gate electrodes of each set. Then, the signal φ G  is set at the &#34;L&#34; level, and all of the output signals S 1  to S n  of the third drive circuit 12 are set to &#34;M&#34; level, to render all of the transistors m 11 , m 21 , m 31 , m 41  to m 1n , m 2n , m 3n , m 4n  conductive. Under this condition, at times 0, 1, 2, 3, 0 the gate signals φ 11  to φ 4n  corresponding to the timing signals φ 1 , φ 2 , φ 3 , and φ 4  are applied to the gate electrodes G 11  to G 4n . Then, according to the potential profile as shown in FIG. 37, a pair of pixel signals are mixed and retained in the transfer pixels under the second gate electrodes of each set. The transfer pixels under the fourth gate electrodes of each set are empty. Here, in the even-numbered field, the combinations of the mixed pixel signals in the even-numbered field are shifted by one line. 
     The scan read is applied at the times (see FIG. 8) similar to those in the still picture photographing mode of the first embodiment, thereby to perform the scan read for the even-numbered field. 
     Thus, in the motion picture photographing mode of the third embodiment, the pixel signals are mixed in the transfer pixels of the vertical charge transfer paths L1 to Lm, and the 2 field scan read is applied to realize the interlace scan read. 
     Those embodiments thus far described, in the still picture photographing mode, can provide a clear image by the noninterlace scan read. The motion picture photographing mode can also be performed by the interlace scan read. Further, the image pick-up devices are inventive in the structure and the drive system. 
     As described above, the present invention successfully provides a solid-state CCD image pick-up device, which is operable in either of two scan read modes, an interlace scan read mode for photographing a motion picture and a noninterlace/frame scan read mode for photographing a still picture. 
     In another embodiment of the present invention, the third drive circuit 12 will be described with reference to FIGS. 38 to 40. The third drive circuit 12 consists of a shift register for shifting a start pulse φ S  in synchronism with two-phase timing signal φ A  and φ B  to sequentially generate drive signals of logic &#34;H&#34; in the order from the low- order bit to the high-order bit. In the first period, only the first drive signal S 1  goes high (&#34;H&#34;), while the remaining high-order bits are all low (&#34;L&#34;) in logic level. In the second period, two low-order bits S 1  and S 2  go high, while the remaining high-order bits are low. In the third period, three low-order bits S 1 , S 2 , and S 3  go high, while the remaining high-order bits are low. Thus, the number of high drive signals progressively increases in order from the low-order bits to the high-order bits. 
     As shown in FIG. 38, each bit has a cell structure, and hence the circuit of the first bit will be typically described. The source-drain paths of three MOS u 11 , u 12 , u 13 , and u 14  are connected in series between a signal line of the voltage V L  and a signal line of the clock signal φ B . A signal line for the reset signal RS is connected to the gate contact of the transistor u 13 . A bootstrap capacitor .di-elect cons. 11  is connected between the gate contact and the source contact of the transistor u 11 . The gate contact and the drain contact of the transistor u 12  are connected to each other, and to the drain contact of the transistor u 14 . The transistor u 14  is connected at the drain contact to the signal line for the voltage V L  and at the gate contact to the signal line for the timing signal φ A . 
     Transistors MOS u 22 , u 22 , u 23 , and u 24  make up the same circuit as that made up of the transistors MOS u 11 , u 12 , u 13 , and u 14 . The drain contact (output point) of the transistor u 12  is connected to the gate contact (input point) of the transistor u 22 . However, the connection of the signals φ A  and φ B  thereto is inverted. 
     The bit input corresponding to the gate contact of the gate contact of the transistor u 11 . The bit output corresponding to the source contact of the transistor u 22 . An n-bit shift register is formed by connecting the inputs and outputs of those bit cells in a cascade fashion. A start pulse φ S  is inputted to the least significant bit cell through an analog switch u 00  which is rendered conductive in synchronism with the clock signal φ A . 
     The shift register thus arranged will operate in the following. As shown in FIG. 39, during a period between t 0  to t n , when the start pulse φ S  is set to &#34;H&#34; level, the bit output signals are successively set to &#34;H&#34; level from the low-order bit output signal S1 to the most significant bit output signal Sn. If a reset signal φ RS  is set to &#34;H&#34; level at a desired timing, then the bit output signals S1 to Sn are all reset to &#34;L&#34; level. Signals appearing at contacts i 1  to i 9  in the internal circuits forming bits shown in FIG. 38 take waveforms as shown in FIG. 40. As shown, the voltages at the gate contacts i 1 , i 3 , i 7 , i 9 , . . . of the transistors u 11 , u 21 , . . . are raised through the functions of the bootstrap capacitors .di-elect cons. 11 , .di-elect cons. 12 , . . . Therefore, those voltages of satisfactory amplitudes are wave shaped to form rectangular bit output signals S1 to Sn. 
     The operation of the CCD image pick-up device thus constructed will be described using an electronic still camera for photographing a still picture into which the image pick-up device is incorporated. 
     The operation of the image pick-up device when it takes a still picture will be described with reference to FIG. 18. It is assumed that the period T VB  corresponds to the vertical blanking period of a standard television system. At a predetermined time during the period T VB , a so-called field shift to shift the pixel charges from the photodiodes to the vertical charge transfer paths is performed. The electronic shutter function is realized if the time for the field shift operation is made to correspond to a time of closing a shutter (time of an exposure completion). Accordingly, the exposure operation starts at a time after the shutter close time, and the device is so controlled that the exposure time ranges from the exposure start time to a time of starting the field shift operation. 
     The excessive charges possibly causing the smear component and the dark current component in the vertical charge transfer paths L 1  to L m  and the horizontal charge transfer path 8, are discharged by the charge transfer operation before the field shift starts. Further, immediately before the exposure starts, the unnecessary charges in the photodiodes have been drained by the vertical overflow drain structure. 
     During the period T VB  corresponding to the vertical blanking period, the pixel signals of all of the photodiodes are simultaneously transferred to the transfer pixels of the vertical charge transfer paths L 1  to L m . During the period T HB  corresponding to the horizontal blanking period, a pixel signal of the transfer pixel closest to the horizontal charge transfer path 8 is transferred to the transfer path 8. During a period T 1H  corresponding to the horizontal scan period (called a 1 H period), the pixel signals of one line are horizontally transferred through the horizontal charge transfer path 8. As a result, the pixel signals of the first line are read out. 
     Then, during the period T HB  corresponding to the next horizontal blanking period, the vertical charge transfer paths L 1  to L m  feed the pixel signals of the next line to the horizontal charge transfer path 8. During a period T 1H  corresponding to the next horizontal scan period, the pixel signals are horizontally transferred through the horizontal charge transfer path 8. In this way, the pixel signals of the second line are read out. 
     The pixel signals of the third line are likewise read out of the photodiodes by using periods T HB  and T 1H . The pixel signals of the remaining lines are successively read out while repeating a similar sequence of operations. Finally, all of the pixel signals of one frame are read out. 
     The scan read operation will be described in detail with reference to FIG. 18 showing a timing chart of drive signals and timing signals. In the figure, the period T VB  corresponds to the vertical blanking period, the period T HB  corresponds to the horizontal blanking period, period T 1H  corresponds to the horizontal scan period. Further, &#34;H&#34; indicates 12 V, &#34;M&#34; indicates 0 V, &#34;L&#34; indicates -8 V, and &#34;HH&#34; indicates approximately 15 to 25 V equal to the substrate voltage. 
     During the period T VB  corresponding to the vertical blanking period, the timing signal φ H  and φ G  go high (H) only at a predetermined time t2, while remains &#34;M&#34; in level at the remaining times. The timing signal φ G  is always at the &#34;M&#34; level. The timing signal φ FS  goes high (H) as the timing signal φ H  goes high, while being kept at the &#34;L&#34; level during the remaining times. The drive signals S 1  to S n  generated from the third drive circuit 12 are always at the &#34;L&#34; level. 
     During the period T VB , all of the NMOS transistors of the first drive circuit 10 are rendered conductive by the timing signal φ G  of &#34;H&#34; and &#34;M&#34; level, while at the same time all of the drive signals S 1  to S n  of the third drive circuit 12 are placed at the &#34;L&#34; level. Accordingly, all of the NMOS transistors in the second drive circuit 11 become conductive. All of the gate electrodes G 11 , G 21 , G 31 , G 41  to G 1n , G 2n , G 4n  are controlled by the first drive circuit 10. 
     More specifically, when the timing signals φ H  and φ FS  are not at the &#34;H&#34; level, the gate signals φ 11 , φ 31 , φ 12 , φ 32  to φ 1n , φ 3n , which are applied to the odd-numbered gate electrodes G 11 , G 31 , G 12 , G 32  to G 1n , G 3n , are each equal in voltage level to the signal V L  (constantly set at -8 V). Under this condition, potential barriers are generated in the vertical charge transfer paths L 1  to L m  under those gate electrodes. 
     The gate signals φ 21 , φ 41 , φ 22 , φ 42  to φ 2n , φ 4n , which are applied to the even-numbered gate electrodes G 21 , G 41 , G 22 , G 42  to G 2n , G 4n , are each equal in voltage to the signal φ H  at the &#34;M&#34; level. Under this condition, transfer pixels are generated in the vertical charge transfer paths L 1  to L m  under those gate electrodes. 
     Accordingly, all of the portions adjacent to the transfer gates Tg (see FIG. 14) serve as the transfer pixels being separated from one another by the potential barriers. 
     Under this condition, when the timing signals φ H  and φ FS  go high at time t2, all of the npn transistors Q 21 , Q 41 , Q 61 , . . . become conductive, and the &#34;H&#34; level voltage of approximately 12 V is applied to only the even-numbered gate electrodes G 21 , G 41 , G 22 , G 42  to G 2n , G 4n . Accordingly, all of the transfer gates Tg become conductive, and all of the pixel signals of all of the photodiodes are transferred to the adjacent transfer pixels. 
     As already described referring to FIG. 17, the exposure process has been completed just before the time t 2 , and the removal of the unnecessary charges has also been completed. During the period T VB , a so-called field shift operation is performed, so that as at the time t 1  shown in FIG. 22, the pixel signals (shaded squares) are transferred to the vertical charge transfer paths. During the period T HB  corresponding to the first horizontal blanking period, the timing signal φ G  is always at the &#34;L&#34; level. Accordingly, all of the NMOS transistors in the first drive circuit 10 become nonconductive and are separated from all of the gate electrodes. 
     Only the drive signal S 1  at the first output terminal of the third drive circuit 12 is placed at the &#34;M&#34; level, while the remaining drive signals S 2  to S n  are at the &#34;L&#34; level. This renders conductive only the first set of NMOS transistors m 11 , m 21 , m 31 , m 41  concerning the drive signal S 1  of the second drive circuit 11. 
     During the period that only the drive signal S 1  is set to &#34;M&#34; level, the timing signals φ 1 , φ 2 , φ 3 , and φ 4  of four phases for the vertical charge transfer are inputted to the second drive circuit 11. Accordingly, only the first set of first to fourth gate signals φ 11 , φ 21 , φ 31 , and φ 41  are equal in level to the timing signals φ 1 , φ 2 , φ 3 , and φ 4 . The charge transfer is performed by the first set of first to fourth gate electrodes G 11 , G 21 , G 31 , and G 41 . The enlarged signal waveforms during the period T HB  are shown in FIG. 19. 
     As a consequence, the signal charges are transferred to the horizontal charge transfer path 8 at the times (indicated by numerals 1, 2, 3, 4, 5, 6, and 7) of the gate signals φ 11 , φ 21 , φ 31 , and φ 41  in FIG. 19, as in the first transfer shown in FIG. 22. A pixel signal q 1j  of the first line closest to the horizontal charge transfer path 8 is transferred to the transfer path 8. A pixel signal q 2j  of the second line moves to the first line position. 
     Then, during the first horizontal scan period T 1H  (between times t 4  and t 5 ), the variation of the signal applied to each gate electrode stops, and the horizontal charge transfer path 8 vertically transfers signal charges in synchronism with the gate signals α 1  to α 4  recurring at predetermined times according to the four- or two-phase drive system. As a result, pixel signals of the first one line are read out. 
     During a period between times t 5  to t 7 , a sequence of operations, which is similar to that during the period between times t 3  to t 5 , is repeated to read the pixel signals of the next line out of the image pick-up device. During the horizontal blanking period T HB  between times t 3  to t 4 , the drive signals S 1  and S 2  of the third drive circuit 12 are simultaneously set to &#34;M&#34; level, and the remaining drive signals S 3  to S n  are set to &#34;L&#34; level. The enlarged signal waveforms during this period T HB  are shown in FIG. 20. 
     Consequently, a set of the first to fourth gate electrodes G 11  to G 41 , and two sets of fifth to eighth G 12  to G 42  are driven by the gate signals φ 11  to φ 41  and φ 12  to φ 42 , which are equal to the timing signals φ 1 , φ 2 , φ 3 , and φ 4 . The result is the vertical transfer of the pixel signals under those gate electrodes. 
     The timing chart shown in FIG. 20 shows that as indicated by the second vertical scan in FIG. 22, the pixel signal q 2j  of the second line is transferred to the horizontal charge transfer path 8. Two lines of the pixel signals q j3  of the third line and one line of the pixel signal q j4  of the fourth line are transferred to the horizontal charge transfer path 8. 
     During the horizontal scan period T 1H  between times t 6  and t 7 , the horizontal charge transfer path 8 reads out the pixel signal q 2j  of the second line. 
     The third scan read starts at time t 7 . Then, the drive signals S 1 , S 2 , and S 3  are set to &#34;M&#34; level, while the remaining drive signals S 4  to S n  of the third drive circuit 12 are set to &#34;L&#34; level. The first to third sets of first to 12th gate electrodes G 11  to G 41 , G 12  to G 42  to G 42 , and G 13  to G 42  are driven for the vertical charge transfer. Accordingly, as in the third transfer of FIG. 22, the pixel signal q 3j  of the third line is transferred to the horizontal charge transfer path 8. The pixel signals q 4j  to q 7j  of the 4th to 7th lines are transferred every line to the horizontal charge transfer path 8. 
     Then, the pixel signal q 3j  is read out of the photodiodes by the horizontal charge transfer path 8. 
     Subsequently, the drive signals S 4  to S n  of the third drive circuit 12 are progressively inverted to &#34;M&#34; level every time the pixel signal of each line is read out. The gate electrodes to be driven are increased every four transfer pixels under the gate electrodes. During the horizontal blanking period T HB  (between times t 9  and t 10 ), all of the gate signals φ 11  to φ 4n  have the same waveforms as those of the timing signals φ 1  to φ 4 , as shown FIG. 21. The pixel signals of the last line are read out by the final scan read operation. 
     FIG. 23 shows the K-th and (K+1)th vertical charge transfer operations, for example, in terms of potential profiles. As shown, in order from the transfer pixel closest to the horizontal charge transfer path 8, the intervals of the idle transfer pixels progressively increase. With this, the pixel signals are read out in the order from the pixel signals of the pixel closed to the transfer path 8 to the succeeding ones. 
     Thus, in the present embodiment, the pixel signals of one frame can be read out by one-time frame scan read operation. 
     Also in the embodiment, the width of the odd-numbered gate electrodes is wider than that of the even-numbered gate electrodes. This feature allow increase of a charge retaining capacitance of the transfer pixels adjacent to the transfer gates. Additionally, during the vertical charge transfer, the transfer pixels under the even-numbered gate electrodes are, of necessity, used for the charge transfer, thereby improving the charge transfer efficiency. 
     The shift register corresponding to the third drive circuit produces the respective bit output signals at the frequency equal to that of the timing signal. Therefore, there is no need for increasing the frequency of the timing signal, although the prior shift register needs the increase of it. Further, the shift register can be reset at a desired timing. In the embodiment, the charge transfer is performed in synchronism with the four-phase timing signals φ 1 , φ 2 , φ 3 , and φ 4  during the period T HB  corresponding to each horizontal blanking period. If necessary, the timing signals of 4 or more phases may be used for driving the gate electrodes corresponding to the number of phases. 
     The solid-state image pick-up device having the thus constructed shift register operates in synchronism with the timing signal in a manner that the number of the bit output signals of &#34;H&#34; level gradually increases in the order from the low-order bit to the high-order bit. That is, during a first period, only the first bit output signal is at the &#34;H&#34; level, while the remaining high-order bits are all at the &#34;L&#34; level. During the next period, the bit output signals at the two low-order bits are at the &#34;H&#34; level, while the remaining high-order bits are at the &#34;L&#34; level. During the succeeding period, the bit output signals at the three low-order bits are at the &#34;H&#34; level, while the remaining high-order bits are at the &#34;L&#34; level. 
     The bit output signals vary in synchronism with the frequency of the timing signal. Additionally, the shift register can be reset at any time by a reset signal. 
     Other modifications and variations to the invention will be apparent to those skilled in the art from the foregoing disclosure and teachings. Thus, while only certain embodiments of the invention have been specifically described herein, it will be apparent that numerous modifications may be made thereto without departing from the spirit and scope of the invention.