Patent Publication Number: US-8975899-B2

Title: Inverter device comprising a topology surveying a series of capacitors

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation in part of U.S. patent application Ser. No. 12/557,660 entitled “Topology Surveying a Series of Capacitors” and filed on Sep. 11, 2009. 
    
    
     FIELD 
     The present disclosure relates generally to surveying the integrity of a plurality of capacitors connected in series between a pair of bus lines designed and arranged to be connected to a DC-power source. More particular, the present disclosure relates to an inverter device comprising a topology for surveying the integrity of a plurality of capacitors connected in series between a pair of bus lines configured to be connected to the DC-power source such as, for example, a photovoltaic panel, a plurality of photovoltaic panels, one or more photovoltaic panels combined with a DC/DC-converter, an electric generator, or an electric generator combined with a DC/DC-converter or a AC/DC-inverter. At their other ends, the bus lines are connected to a DC/AC-inverter or a DC/DC-converter at the input end of a DC/AC-inverter for feeding electrical energy from the power source into a power grid. For example, the embodiments of the present disclosure may be used in an inverter device for feeding electric energy from an array of photovoltaic panels into a public power grid. 
     BACKGROUND 
     The plurality of capacitors connected in series between a pair of bus lines of a DC circuit of a topology serves to stabilize and smooth a voltage applied between the bus lines which may otherwise be subject to unwanted dynamic changes due to variable input or output currents. In principle, the electric capacitance between the bus lines required for stabilizing and smoothing the voltage applied between the bus lines may be provided by a single capacitor or even by single capacitors connected in parallel between the bus lines. However, such a single capacitor would then be subjected to the full voltage applied between the bus lines. In modern photovoltaic power plants this voltage typically ranges from 400 to 600 V but may reach or even exceed 1,000 volt. A single capacitor connected between the bus lines must have a working voltage clearly above the maximum voltage applied between the bus lines. Capacitors of a suitable capacitance and a high working voltage, such as on the order of 1,000 volt and higher are very expensive. For this reason, it is usual practice to connect two or more low cost capacitors having a lower working voltage in series to provide the necessary capacitance between the bus lines. Each of these capacitors is only subjected to a fraction of the total voltage applied between the bus lines. If one of these capacitors fails, however, the remaining capacitors are additionally subjected to the fraction of the voltage between the bus lines previously covered by the failing capacitor. Particularly with a low overall number of capacitors connected in series, such as for example only two, the remaining capacitors may thus be subjected to a voltage much higher than their working voltage. As a result, they may also break down so that the full voltage between the bus lines is shortcut by the failing and broken down capacitors. 
     To avoid applying such an excess voltage to the remaining capacitors of a plurality of capacitors connected in series between the bus lines from a failing capacitor of the series, the integrity of the plurality of capacitors has to be surveyed continuously. 
     US Patent Application Publication 2007/0291522 A1 discloses an interconnection inverter device in which the voltages dropping over each of two capacitors connected in series between two bus lines leading to the inverter are monitored. A controller controls opening or closing of an opening/closing unit connected to either one of the bus lines based on the monitored voltages. If a short-circuit fault occurs in one of the capacitors, a high voltage applied between the two bus lines is prevented from being applied to the remaining capacitor in that the one bus line in which the opening/closing unit is connected is interrupted towards the DC-power source, i.e. in that one end of the plurality of capacitors is disconnected from the DC-power source. 
     According to US 2007/0291522 A1, surveying the integrity of the plurality of capacitors requires great effort. One voltage meter is required for each capacitor. Further, the voltage drops over the capacitors have to be monitored carefully and compared to each other or to the total voltage applied between the bus lines. 
     EP 1 463 188 A2 discloses a circuitry arrangement for limiting the voltage applied between two bus lines by one or a plurality of photovoltaic panels, which is arranged at the input side of an inverter comprising a buffer capacitance arranged between the two bus lines and feeding electric energy from the photovoltaic panel or the plurality of photovoltaic panels into a public power grid. This circuitry arrangement includes a pulsed switch arranged in one of the bus lines, and a voltage meter measuring the voltage between the two bus lines behind the pulsed switch. By pulsing the switch the effective voltage between the two bus lines behind the switch can be limited to a smaller value than the output voltage of the photovoltaic panel or photovoltaic panels. 
     There is a need for a simpler but nevertheless effective device for surveying securely the integrity of a plurality of capacitors connected in series between a pair of bus lines arranged to be connected to a DC-power source. 
     SUMMARY 
     The present disclosure relates to an inverter device for feeding electrical energy from a DC-power source into a power grid. This inverter device comprises a pair of bus lines configured to be connected to the DC-power source, a plurality of capacitors connected in series between the pair of bus lines, and a surveying topology configured to survey an integrity of the plurality of capacitors, and provide a signal indicating a loss of integrity of one capacitor of the plurality of capacitors. The inverter further comprises a voltmeter configured to measure a voltage drop over the plurality of capacitors, a DC/AC-inverter; and a controller. The controller is configured to, upon the signal indicating a loss of integrity of one capacitor of the plurality of capacitors, compare the voltage drop over the plurality of capacitors measured by the voltmeter to a lost integrity threshold voltage value, and reduce a current load to the plurality of capacitors by reducing the power uptake of the DC/AC-inverter, when the voltage drop over the plurality of capacitors exceeds the lost integrity threshold voltage value. 
     The present disclosure also relates to another inverter device for feeding electrical energy from a DC-power source into a power grid. This inverter device comprises a pair of bus lines configured to be connected to the DC-power source, a plurality of capacitors connected in series between the pair of bus lines, and a surveying topology configured to survey an integrity of the plurality of capacitors, and provide a signal indicating a loss of integrity of one capacitor of the plurality of capacitors. The inverter further comprises a voltmeter configured to measure a voltage drop over the plurality of capacitors, a DC/AC-inverter, a voltage limiter, and a controller. The voltage limiter is configured to limit the voltage drop over the plurality of capacitors, wherein the voltage limiter operates a pulsed switch connected between the DC-power source, on the one hand, and the plurality of capacitors and the plurality of resistors, on the other hand, in one of the bus lines. Further, the voltage limiter is configured to, upon the signal indicating a loss of integrity of one capacitor of the plurality of capacitors, limit the voltage drop over the plurality of capacitors to the lost integrity threshold voltage value. The controller is configured to, upon the signal indicating a loss of integrity of one capacitor of the plurality of capacitors, compare the voltage drop over the plurality of capacitors to a lost integrity threshold voltage value, and reduce a current load to the plurality of capacitors by reducing the power uptake of the DC/AC-inverter, when the voltage drop over the plurality of capacitors exceeds the lost integrity threshold voltage value 
     Other features and advantages of the present disclosure will become apparent to one with skill in the art upon examination of the following drawings and the detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present disclosure, as defined by the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. In the drawings, like reference numerals designate corresponding parts throughout the several views. 
         FIG. 1  is a diagram illustrating a first embodiment of the inverter device connected to a photovoltaic generator at its input end. 
         FIG. 2  is a diagram illustrating major parts of a second embodiment of the inverter device connected to a photovoltaic generator at its input end. 
         FIG. 3  is a diagram illustrating a third embodiment of the inverter device connected to a photovoltaic generator at its input end. 
         FIG. 4  is a diagram illustrating a fourth embodiment of the inverter device comprising a DC/DC-converter at its input end; and 
         FIG. 5  is a diagram illustrating a fifth embodiment of the inverter device comprising an optional DC/DC-converter at the input of its DC/AC-inverter. 
     
    
    
     DETAILED DESCRIPTION 
     In the present description, the term topology is used to refer to a general construction of an electric circuit. Thus, the term topology may also be replaced by the terms “electric circuit” or “circuitry arrangement”. 
     Further, in the present description, the expression “connected (in series) between a or the pair of bus lines” is used to refer to a connection to the one bus line of the pair of bus lines on the one hand and to the other bus line of the pair of bus lines on the other hand. 
     Further, the term “power uptake of the DC/AC-inverter” is used to refer to the electric power drawn by the DC/AC-inverter from a DC voltage link including the plurality of capacitors. 
     In the inverter device of the present disclosure, the controller, upon the signal from the surveying topology indicating a loss of integrity of one capacitor of the plurality of capacitors, compares the voltage drop over the plurality of capacitors measured by the voltmeter to a lost integrity threshold voltage value. When the voltage drop over the plurality of capacitors exceeds the lost integrity threshold voltage value, the controller reduces a current load to the plurality of capacitors by reducing the power uptake of the DC/AC-inverter. This reduction in power uptake does not necessarily reduce the voltage drop over the plurality of capacitors. Instead, the reduced current load to the plurality of capacitors reduces the stress to the remaining capacitors, i.e. to those capacitors not having lost their integrity which now have to bear the entire voltage drop over the plurality of capacitors. At a reduced current load, the danger of damaging a capacitor subjected to an overvoltage is strongly reduced. Thus, despite not reducing the voltage drop over the plurality of capacitors, reducing the power uptake of the DC/AC-inverter effectively protects the remaining capacitors against damage. 
     The lost integrity voltage value is a predetermined value which may be that voltage at which the plurality of capacitors connected in series minus the capacitor which has lost its integrity may still be operated at a full current load. This full current load refers to the maximum current load occurring in standard operation of the inverter device. 
     Reducing the current load to the plurality of capacitors means that a ripple of a current drawn from the capacitors towards the DC/AC-inverter is reduced in one embodiment. 
     Reducing the power uptake of the DC/AC-inverter does not only relate to a partial reduction of the power uptake. It may also include completely stopping the power uptake of the DC/AC-inverter. 
     The reduction of the power uptake of the DC/AC-inverter may be provided in that the controller directly controls the DC/AC-inverter for a reduced power uptake. Alternatively or additionally the inverter may control a DC/DC-converter connected between the plurality of capacitors and the DC/AC-inverter for reducing its power uptake which automatically means that also the power uptake of the downstream DC/AC-inverter is reduced. 
     The controller may additionally output a failure signal to an operator of the inverter device, when the voltage drop over the plurality of capacitors exceeds the lost integrity voltage value. 
     In the surveying topology according to one embodiment of the present disclosure, the additional plurality of resistors connected in parallel to the plurality of capacitors is used as a voltage divider dividing the voltage applied between the two bus lines in the same ratios as it is dropping over the plurality of capacitors as long as all capacitors work properly. As a result, it is possible to survey the proper function of the single capacitors in that the electric potential of an intermediate point between two capacitors of the plurality of capacitors is compared with the electric potential of an intermediate point between two resistors of the plurality of resistors. As long as the ratios of the voltages dropping over the capacitors and over the resistances on both sides of the intermediate points are equal, there is no difference in electrical potential between the intermediate points. Any failure of a capacitor of the plurality of capacitors, however, will have a strong impact on the ratio of the voltages dropping over the capacitors on both sides of their intermediate point as the voltage dropping over the failing capacitor brakes down. This directly results in a difference in potential between the two intermediate points. The surveying topology may be implemented using the series of resistors connected in parallel to the capacitors and the comparator. 
     As small differences in electric potential between the two intermediate points may be due to tolerances in the absolute values of the voltages dropping over the single capacitors and the resistances of the single resistors which may even change with temperature or other environmental conditions without a failure occurring, the comparator provides in one embodiment a signal signaling whether a difference between the two electric potentials exceeds a predetermined threshold value. This threshold value is suitably predetermined in such a way that it is in only exceeded with a failure of one of the capacitors. 
     In a simple embodiment of the surveying topology the capacitors on both sides of the intermediate point between the two capacitors of the plurality of capacitors are of equal total capacitance and of ideal, i.e. infinite, internal resistances, and the resistors on both sides of the intermediate point between the two resistors of the plurality of resistors are of equal total resistance. In a basic embodiment of the present disclosure there are only two capacitors of equal capacitance and of infinite internal resistance, and two resistors of equal resistance connected in series between the two bus lines. 
     Most actual capacitors, however, display finite internal resistances. Thus, in some embodiments of the present disclosure, the voltages dropping over the capacitors on both sides of the intermediate point between the two capacitors of the plurality of capacitors are defined by means of further resistors connected in parallel to these capacitors. At least one of these further resistors is then connected in parallel to each capacitor, and shortcut by a failure of this capacitor. If a ratio of resistances of these further resistors on both sides of the intermediate point between the two capacitors, and a ratio of resistances of the resistors of the plurality of resistors on both sides of the intermediate point between the two resistors of the plurality of resistors are equal, there is no difference in electrical potential between the intermediate points between the two capacitors of the plurality of capacitors and between the two resistors of the plurality of resistors, even if the ratios differ from 1 to 1. Such a difference may be due to a plurality of capacitors of three or more capacitors or to different voltages dropping over the single voltages. 
     In the present disclosure the signal provided by the comparator may directly operate a switch when the difference in electric potential exceeds the threshold value. Generally, this switch could, for example, be arranged in one of the bus lines at a point located from the capacitors and resistors towards the DC-power source. Such a switch might simply be opened by the signal provided by the comparator and indicate a loss of integrity of one of the capacitors to cut off the connection to the DC-power source which applies the voltage between the bus lines. This would mean, however, that the inverter device could no longer feed any electric energy from the DC-power source into the power grid. 
     In a slightly more sophisticated embodiment of the surveying topology which, however, allows for further electric energy to be forwarded from the DC-power source via the bus lines despite a failure of one of the capacitors, the switch operated by the signal provided by the comparator and indicating a failure of a capacitor is connected in parallel to a resistor of a second plurality of resistors connected in series between the bus lines and in parallel to the capacitors. This second plurality of resistors is used in combination with a voltage limiter that is arranged to limit a voltage drop of at least one resistor of the second plurality of resistors in that the voltage limiter operates a pulsed switch arranged in one of the bus lines at a point located from the capacitors and resistors towards a DC-power source. This pulsed switch may, for example, be part of a second DC/DC-converter connected between the DC-power source, on the one hand, and the plurality of capacitors and the plurality of resistors, on the other hand. 
     As long as the switch is not operated by the signal from the comparator, the second plurality of resistors divides the voltage between the bus lines according to a first ratio of resistances of its resistors, and the voltage limiter is adjusted in such a way that it limits the voltage drop over the at least one resistor to a fraction of a total maximum voltage between the bus lines which is equal to the fraction of the resistance of the at least one resistor as compared to the overall resistance of the second plurality of resistors. If, for example, the maximum allowable voltage between the two bus lines is 1,000 volt, if the total resistance of the second plurality of resistors is 10 megohm, and if the resistance of the other resistor is 10 kohm, then the limiter limits the voltage drop over the other resistor to 1,000 volt. 
     In that the signal provided by the comparator and signaling a failure of one of the capacitors, for example, shortcircuits one of the resistors of the second plurality of resistors which does not contribute to the limited voltage drop, the total effective resistance of the second plurality of resistors drops. If, for example, the resistance of the shortcircuited resistor is 4 megohm, the total resistance of the second plurality of resistors in the above example is reduced to 6 megohm. If the limiter then still limits the voltage drop over the at least one resistor to 1,000 volt, the total voltage between the two bus lines is limited to 600 volt which may still be acceptable, if only one of two capacitors connected in series between the two bus lines is working properly. 
     When the signal provided by the comparator and signaling a failure of one of the capacitors, for another example, opens a switch that previously shortcircuited one resistor potentially contributing to the limited voltage drop, the total effective resistance of the second plurality of resistors may essentially remain the same, but the voltage drop will be increased. If, for example, the resistance of the no longer shortcut resistor is 6⅔ kohm, the limited voltage in the above example now drops over 16⅔ kohm, i.e. it is increased by a factor of 5/3. If the limiter then still limits the voltage drop to 1,000 volt, the total voltage between the two bus lines is also limited to 600 volt. Operating a switch connected in parallel to a resistor potentially contributing to the limited voltage drop has the advantage that such a switch is only subject to a low voltage as compared to a switch connected in parallel to a resistor not contributing to the limited voltage when the same change in the small limited voltage drop is to be achieved. 
     The aforesaid embodiments of the surveying topology do not require any alteration to the limiter as it automatically limits the voltage between the two bus lines to a reduced value, when the signal provided by the comparator and indicating a capacitor failure operates the switch connected in parallel to one resistor of appropriate resistance of the second plurality of resistors. It has to be noted here that the two pluralities of resistors serve different functions and may thus be made of totally different resistors in totally different ratios of resistances. 
     In a particular embodiment of the surveying topology, the comparator comparing the electric potentials of the two intermediate points may comprise a light emitting diode (LED) connected to the intermediate points between the two capacitors of the plurality of capacitors and between the two resistors of the plurality of resistors via a current rectifier H-bridge. Thus, the LED will emit light independently of the direction of the difference in electric potential between the two intermediate points, but only if the difference in electric potential exceeds the on-voltage of the LED. Thus, the on-voltage of the LED may define the predetermined threshold value for the difference in the two electric potentials of the two intermediate points. The light emitted by the LED may be used to close a photo-activated switch directly in a so-called opto-coupler. 
     The current rectifier H-bridge of one embodiment of the topology according to the present disclosure may be made in a conventional way of four rectifying diodes. Further, the LED may be connected in series with a Zener-diode oriented in opposite direction to the LED. The Zener-diode defines the threshold value for the difference in electric potential between the two intermediate points at a much higher value than possible by means of the LED on-voltage. 
     The current through the LED is automatically limited by those resistors of the plurality of resistors through which this current is actually flowing. These resistors will be of relatively high resistances to avoid a high parasitic current flowing through them between the pair of bus lines. 
     In one embodiment, the inverter device comprises a second voltmeter measuring a voltage drop over the pulsed switch which is operated by the voltage limiter. The controller reducing the power uptake of the DC/AC-inverter may then evaluate both the voltage drop over the plurality of capacitors measured by the voltmeter and the voltage drop over the pulsed switch measured by the second voltmeter. The sum of these voltage drops equals the voltage provided by the DC-power source. The relation between the voltage drop over the plurality of capacitors and the voltage drop over the pulsed switch including the absolute values of these voltage drops may even be evaluated by the controller to determine whether the signal indicating a loss of integrity of one capacitor of the plurality of capacitors has been provided by the surveying topology. For example, the co-occurrence of (i) a voltage drop over the pulsed switch, and (ii) a voltage drop over the plurality of capacitors not yet exceeding a maximum voltage acceptable if no capacitors has lost its integrity, clearly indicates that the signal has been provided by the surveying topology. The controller may then only be used as a backup protection for the plurality of capacitors. i.e. only reduce the power uptake of the DC/AC-inverter, if the voltage limiter is unable to limit the voltage drop over the plurality of capacitors to the lost integrity threshold voltage value. 
     The surveying topology may particularly be used in an input circuit of a DC/AC-inverter or a DC/DC-converter. The DC/DC-converter may itself be an input circuit of a following DC/AC-inverter. And any of these DC/AC-inverters may be used to feed electric energy from the DC-power source into a power grid, for example. 
     In a further embodiment of the topology according to the present disclosure, the comparator may comprise a voltage meter measuring the difference in the electric potential between the two intermediate points between the two capacitors of the plurality of capacitors and between the two resistors of the plurality of resistors. Then, the output signal of the voltage meter is the signal of the comparator which signals a difference between the two electric potentials indicating a loss of integrity of one capacitor of the plurality of capacitors when exceeding small values which are only due to tolerances. This signal of the voltage meter can be used by a controller opening the switch in parallel to a resistor of the second plurality of resistors as explained above. The controller may also operate a pulsed switch in one of the bus lines in such a way known from EP 1 463 188 A2 that the voltage between the two bus lines behind the switch drops to a level acceptable with regard to the present condition of the capacitors. If all capacitors are working properly, the full nominal voltage may be the voltage to which the controller limits the voltage between the bus lines by operating the switch. If one of two capacitors fails, the voltage may be reduced to 60% of the nominal voltage, for example, which is still acceptable with only one capacitor working between the bus lines. In one embodiment, a further voltage meter is provided for directly measuring the voltage between the two bus lines to provide a further input signal to the controller operating the switch. 
     As a security measure the controller of the surveying topology may be directly powered by the DC-power source, so that it is always powered when it may be necessary to limit the voltage applied by the DC-power source between the bus lines by means of operating the switch. 
     A further switch cutting the plurality of capacitors off the DC-power source, if the voltage drop over the capacitors cannot be limited otherwise, may be connected directly in front of the plurality of capacitors and the plurality of resistors. Instead, it may be provided between the DC-power source and a DC/DC-converter used for adjusting the voltage drop over the plurality of capacitors. 
     The DC-power source may be selected from photovoltaic panels, electric generators, photovoltaic panels combined with DC/DC-converters, electric generators combined with DC/DC-converters and electric generators combined with AC/DC-inverters. 
     The switch arranged in one of the bus lines and opened by the signal from the comparator may be a relay having a relay solenoid biased into its open state so that it may open very quickly in response to excess voltages due to failures of capacitors or other reasons. The relay solenoid may be automatically biased, when the voltage between the bus lines exceeds a lower threshold value, as only then an excess voltage may occur at all. Further, a capacitor, or a transistor which is switched on during opening of the relay may be arranged in parallel to the relay to avoid the formation of an electric arc between the contacts of the relay. Such a relay may also be opened when an additional current meter measures a current through one of the DC bus lines exceeding a current threshold value. Thus, the relay has multiple security purposes and protects against excess currents, excess voltages between the bus lines and excess voltages over the remaining capacitors after one or more capacitors of a plurality of capacitors in series failed. 
     Referring now in greater detail to the drawings,  FIG. 1  illustrates an inverter device comprising a surveying topology  1  arranged between a photovoltaic panel  2  and an inverter  3 . The inverter  3  may be used for feeding electric energy from the photovoltaic panel  2  into an AC-power grid (not shown). The photovoltaic panel  2  is connected to two bus lines  4  and  5  leading to the inverter  3 . A pulsed switch  6  is arranged in the bus line  5  and controlled by a controller  7 . The controller  7  defines the ratio of the on-times and the off-times of the pulsed switch  6 . During regular use this is done to limit the voltage between the bus lines  4  and  5  behind the switch  6  to a maximum input value of the inverter  3 . The voltage between the bus lines  4  and  5  at the input end of the inverter  3  is measured by a voltage meter  8  providing a voltage signal  19  to the controller  7 . 
     If the voltage measured by the voltage meter  8  exceeds the maximum input voltage of the inverter  3 , the on-times of the switch  6  are reduced which means that the ratio between the on-times and the off-times of the switch decreases. This results in a decrease of the effective voltage between the bus lines  4  and  5  which is buffered by two capacitors  9  and  10  connected in series between the bus lines  4  and  5 . The capacitors  9  and  10  provide a buffer capacitance between the bus lines  4  and  5 . Two capacitors  9  and  10  are used for providing this buffer capacitance as each of these capacitors  9  and  10  only has to stand one half of the voltage between the bus lines  4  and  5  with the capacitors  9  and  10  connected in series. 
     However, if one of the capacitors  9  and  10  fails, the other capacitor is subjected to the full voltage between the bus lines  4  and  5 . This voltage, even if reduced to the maximum input voltage of the inverter  3 , may be much higher than the breakdown voltage of only one of the capacitors  9  and  10 , as the breakdown voltage of a capacitors is a cost relevant factor, which is a main reason for using two capacitors  9  and  10  instead of one capacitor of the double breakdown voltage for providing the desired buffer capacitance between the bus lines  4  and  5 . 
     To the end of surveying the integrity of the capacitors  9  and  10 , the topology  1  according to  FIG. 1  comprises a further voltage meter  11  connected between an intermediate point  12  between the two capacitors  9  and  10  and an intermediate point  13  between two resistors  14  and  15  connected in series between the bus lines  4  and  5  and thus connected in parallel to the two capacitors  9  and  10 . Assuming that both capacitors  9  and  10  are exactly of the same capacitance and of infinite or the same internal resistance, and that both resistors  14  and  15  are of the same resistance, and that both capacitors  9  and  10  are working properly, the voltage meter  11  should always indicate a difference in electric potential between the intermediate points  12  and  13  of zero. Thus, such a difference in electric potential of zero or of a small value only deviating from zero due to tolerances of the capacitors  9  and  10  and of the resistors  14  and  15  signaled to the controller via a signal  16  indicates to the controller that both capacitors  9  and  10  are working properly. Likewise, any voltage measured by the voltage meter  11  and exceeding a value, which is due to tolerances, indicates a failure of one of the components  9 ,  10 ,  14  or  15 . The most probable failure will be a failure of one of the capacitors  9  and  10  resulting in that the full voltage between the bus lines  4  and  5  now drops over the remaining capacitor with the risk of a breakdown of this capacitor. To avoid any danger occurring from this situation, the controller may simply permanently open the switch  6  to detach the capacitors  9  and  10  from the photovoltaic panel  2 . In one embodiment of the new topology  1 , however, the controller  7  still pulses the switch  6 , although the signal  16  signals a loss of integrity of one of the capacitors  9  and  10 . The switch  6  is then pulsed in a different way with a decreased ratio of on-times to off-times, i e. with a decreased duty cycle, which reduces the effective voltage between the bus lines  4  and  5  behind the switch  6  to a voltage smaller than the breakdown voltage of the remaining capacitor  9  or  10 . The voltage signal  19  of the voltage meter  8  is used for achieving the desired effective voltage between the bus line  4  and  5 . Thus, the inverter  3  may further feed electric energy in a power grid or to another load despite one of the capacitors  9  and  10  failing. 
     If one of the resistors  14  and  15 , which are both of very high resistance as they are not intended to guide a working current but only to divide the voltage between the bus lines  4  and  5 , fails in the topology  1  according to  FIG. 1 , the controller handles this situation in the same way as described above and thus avoids any possible damage from this failure. Further, the controller normally does not differentiate between a failure of capacitor  9  or a failure of capacitor  10 , i.e. it does normally not differentiate between the direction of the difference in electric potential between the two intermediate points  12  and  13  measured by the voltage meter  11 . 
     If the controller  7  fails in limiting the voltage drop over the remaining intact capacitor  10  or  9  to a lost integrity threshold voltage value which the still intact capacitor  9  or  10  may withstand alone, the controller  7  may permanently open the switch  6  to cut the capacitor off from the DC voltage source  2 . Prior to that, however, the controller  7  may reduce the power uptake of the DC/AC-inverter  3  as this power uptake determines the current load to the capacitors  9  and  10  and as this current load poses the highest danger to the integrity of a capacitor subjected to an overvoltage. 
       FIG. 2  depicts a variant of the surveying topology  1  without showing the inverter  3  according to  FIG. 1 . In this variant, there is no further voltage meter  11  between the intermediate points  12  and  13 , but instead a rectifier H-bridge  17  is provided that is made of four rectifying diodes  18  and provides a rectified current between the intermediate points  12  and  13  to a light emitting diode (LED)  20  connected in series with a Zener-diode  21 . The Zener-diode  21  is oriented in the opposite direction to the LED  20  and thus provides for a threshold value to be exceeded by the difference in electric potential between the intermediate points  12  and  13 , before the Zener-diode breaks down and lets pass a current to the LED  20 . As a result, the LED  20  emits light when the threshold value defined by the Zener-diode  21  is exceeded by the difference in electric potential between the intermediate points  12  and  13  independently of the direction of this difference in electric potential. The current through the LED  20  is limited by that resistor  14  or  15  through which this current is actually flowing. The LED  20  is part of an opto-coupler  22  closing a switch  23 , when the light emitting diode  20  emits light. 
     This switch  23  shortcircuits a resistor  24  of a plurality of resistors  24  to  26  connected in series between the bus lines  4  and  5  and in parallel with the resistors  14  and  15 . Here, a voltage meter  80  for measuring the voltage between the bus lines  4  and  5  is arranged to only measure the voltage dropping over one resistor  26  belonging to the plurality of resistors  24  to  26 . Thus, the voltage meter  80  does not measure the total voltage between the bus lines  4  and  5  but a defined fraction of this total voltage from which the total voltage may be easily calculated, as long as the resistance of the resistor  26  and the total resistance of the plurality of resistors  24  to  26  are fixed. When the switch  23  shortcircuits the resistor  24  this results in a reduction of the total resistance of the plurality of resistors of which only the resistors  25  and  26  are still working. 
     Thus, the voltage meter  80  measures a higher voltage drop over the resistor  26  than before, assuming that the total voltage between the bus lines  4  and  5  is still the same. This effect can be used to get the controller  7  to reduce the voltage dropping over the resistor  26  by means of pulsing the switch  6  to such an extent that the effective voltage between the bus lines  4  and  5  is decreased to such a value acceptable for only one of the capacitors  9  and  10 . Thus, this embodiment does not actually notify the controller  7  that one of the capacitors  9  and  10  failed. Instead, a voltage signal  81  output by the voltage meter  80  is manipulated by shortcircuiting the resistor  24  in such a way that the controller  7  believes that the voltage between the bus lines  4  and  5  is higher than the maximum input voltage of a following inverter, for example. As a result, the controller  7  reduces this effective voltage between the bus lines  4  and  5 . If the resistances of the resistors  24  to  26  are selected in an appropriate way, this reduction will be of such an extent that the remaining voltage between the bus lines  4  and  5  will not damage the remaining capacitor  9  or  10 . 
     Further, the embodiment of the topology  1  depicted in  FIG. 2  comprises resistors  27  and  28  of a same high resistance which is nevertheless much smaller than the internal resistances of the capacitors  9  and  10 . These resistors  27  and  28  distribute the voltage drop between the bus lines  4  and  5  in two identical halves over the capacitors  9  and  10  independently of any tolerances of the capacitors  9  and  10 , particularly independently of any differences in the internal resistances of the capacitors  9  and  10 . If one of the capacitors  9  and  10  fails, the corresponding resistor  27  or  28 , which is connected in parallel to the respective capacitor, is shortcircuited. The resistors  27  and  28  also allow for the compensation of small dynamic deviations of the electric potential of the intermediate point  12  from the average of the electric potentials of the bus lines  4  and  5 , which are not due to failures of the capacitors  9  and  10 . 
     The embodiment of the surveying topology  1  of the inverter device depicted in  FIG. 3  differs from that one in  FIG. 2  with regard to the following points. First, a DC/DC-converter  30  is arranged at the output end of the topology. This converter may be the input stage of a further DC/AC-inverter not depicted here. Second, the switch  23  being part of the opto-coupler  22  does not shortcircuit one of the pluralities of resistors  25 ,  26  and  29 , here, but operates a transistor  31 . The transistor  31  is a switch normally shortcircuiting a resistor  29  which potentially contributes by the voltage drop measured by the voltage meter  80  in the same way as the resistor  26 . As long as the resistor  29  is shortcircuited by the transistor  31 , it does not contribute to the voltage drop measured by the voltage meter  80 . If the transistor  31 , however, is operated via the switch  23  due to a difference in electric potential between the intermediate points  12  and  13 , the transistor  31  stops shortcircuiting the resistor  29 . As a result, the voltage drop measured by the voltage meter  80  now comprises contributions by both resistors  26  and  29 , i.e., with a constant difference in voltage between the bus lines  4  and  5 . It increases to a predetermined extent. Thus, the controller  7  receives a higher voltage signal  81  and reduces the difference in voltage between the bus lines  4  and  5  by a pulsed opening of the switch  6 . As an appropriate resistor  29  is of much smaller resistance than an appropriate resistor  24  according to  FIG. 2 , the switch  23  and the transistor  31  according to  FIG. 3  may be kept much simpler than the switch  23  in the embodiment of the topology according to  FIG. 2 . 
     Third, the embodiment of the topology  1  according to  FIG. 3  comprises a more sophisticated circuitry to distribute the difference in voltage between the bus lines  4  and  5  evenly over the capacitors  9  and  10 , in that the electric potential between the resistors  27  and  28  is used to drive two transistors  32  and  33  for adjusting the electric potential of the intermediate point  12  via a current limiting resistor  37 . Further, a bidirectional Zener-diode  38  ensures that the gate voltage of the transistors  32  and  33  is limited, particularly if one of the capacitors  9  and  10  fails. With such a failure the additional circuitry for having a symmetric distribution of the voltage drops over the capacitors  9  and  10  becomes inactive. The transistors  32  and  33  are also protected by diodes  35  and  36 , respectively. 
     The embodiment of the inverter device comprising the surveying topology  1  depicted in  FIG. 4  is another variant of the inverter device according to  FIG. 1 . In  FIG. 4  the photovoltaic panel  2  according to  FIG. 1  is not shown. The inverter device according to  FIG. 4  comprises a DC/DC-converter  27  arranged between the switch  34  and the capacitors  9  and  10  connected in series between the bus lines  4  and  5 . This DC/DC-converter  27  includes the pulsed switch  34  similar to switch  6  according to the previous figures and is operated by the controller  7 . Further,  FIG. 4  indicates that the power supply of the controller  7  is directly provided for at the input side of the topology  1 . That is, the controller  7  is supplied with electric energy by means of a DC-power source to which the topology  1  is connected. This ensures that the controller  7  is always working as soon as an input voltage is applied between the bus lines  4  and  5  at the input side of the topology  1 . Further, the controller  7  may also be used to open the switch  34  connected between the DC-power source  2  and the DC/DC-converter  27  in the input line  5 . This may be done, if the DC/DC-converter  27  is unable to limit the voltage drop over the capacitors  9  and  10  in case of a failure of one of the capacitors  9  and  10 , or if another failure is detected, like for example a lack in symmetry of an intermediate circuit, a shortcircuit towards ground, a current exceeding a predetermined threshold and so on. According to  FIG. 4 , the switch  34  is an opening relay. The opening speed of the relay is increased by pre-magnetizing the relay solenoid. This is effected by a DC pre-magnetizing current which is activated as soon as the input voltage exceeds a lower threshold value. To the end of avoiding the formation of an electric arc between the contacts of the switch  34  upon opening, a transistor which is switched on during opening the relay or a capacitor may be connected in parallel to the relay. 
     The inverter device according to  FIG. 5  basically comprises the same surveying topology  1  as depicted in  FIG. 2 . However, the inverter device according to  FIG. 5  comprises two controllers  71  and  72 . The first controller  71  works as a voltage limiter operating the pulsed switch  6  to limit the voltage drop over the resistor  26  measured by the voltmeter  80  to actually limit the voltage drop over the capacitors  9  and  10  in the same way as described with reference to  FIG. 2 . The second controller  72  receives the voltage signal  19  from the voltage meter  8  measuring the actual voltage drop over the capacitors  9  and  10  and a further voltage signal  82  from a voltmeter  83  measuring the voltage drop over the pulsed switch  6 . The sum of these two voltage drops corresponding to the voltage signals  19  and  82  equals the output voltage of the DC-power source  2 . From the relation of these two voltage drops, including their absolute values, the controller  72  determines whether the pulsed switch  6  is operated by the controller  71  to keep the voltage drop over the capacitors  9  to  10  below the lost integrity threshold voltage value. In this case, the voltage drop over the switch  6  as compared to the absolute value of the voltage drop over the capacitors  9  and  10  is higher than in case of no capacitor  9  or  10  having lost its integrity. Further, the controller  72  may monitor, whether the controller  71  is successful in limiting the voltage drop over the capacitors  9  and  10  to the lost integrity threshold voltage value. If not, the controller  72  will reduce the power uptake of the DC/AC-inverter  3 . This is effected by either directly controlling the DC/AC-inverter  3  or by controlling an optional DC/DC-converter  37  connected between the surveying topology  1  and the DC/AC-inverter  3 . Already prior to that, i.e. when the controller  72  just notices that the controller  71  operates the switch  6  as to limit the voltage drop over the capacitors to the lost integrity threshold voltage value, the controller  72  may display a failure signal via a display  35  or via a communication interface  36  to the operator of the inverter device according to  FIG. 5 . 
     Many variations and modifications may be made to the preferred embodiments of the disclosure without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of the present disclosure, as defined by the following claims.