Patent Publication Number: US-7719489-B2

Title: Driving waveform and circuit for plasma display panel

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   The present application claims the benefit of priority from U.S. Provisional Patent Application No. 60/595,307, filed on Jun. 22, 2005, which is hereby incorporated by reference as if set forth in full in this document for all purposes. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a driving waveform and circuit, and more particular, to a driving waveform and circuit for a plasma display panel (PDP). 
   2. Description of the Prior Art 
     FIG. 1  is a prior art driving circuit  100  of a PDP. An equivalent capacitor of the plasma display panel is marked as C panel . The X-side of the PDP is electrically connected to a switch Sw 1  that is connected to voltage Va, a switch Sw 3  that is electrically connected to ground, and to an energy recovery circuit  110 . The energy recovery circuit  110  comprises inductor L 1 , which is electrically connected in parallel to diodes D 5  and D 6  as shown. Diodes D 5  and D 6  are respectively electrically connected to switches Sw 5  and Sw 6 , both of which are electrically connected to ground via a capacitor C 1 . 
   Similarly, the Y-side of the PDP is electrically connected to a switch Sw 2  that is connected to voltage Vb, a switch Sw 4  that is electrically connected to ground, and to an energy recovery circuit  120 . The energy recovery circuit  120  comprises inductor L 2 , which is electrically connected in parallel to diodes D 7  and D 8  as shown. Diodes D 7  and D 8  are respectively electrically connected to switches Sw 7  and Sw 8 , both of which are electrically connected to ground via a capacitor C 2 . 
   The X-side circuit and the Y-side circuit together form the panel equivalent capacitor C panel . Details of exact functioning of the driving circuit  100  are well known in the art and will be omitted here for brevity. However, it is important to notice that the driving circuit  100  requires quite a few components making it expensive to make. Cost conscious consumers desiring a PDP demand lower prices and thus make PDPs comprising similar circuits uncompetitive in today&#39;s market. 
   SUMMARY OF THE INVENTION 
   It is therefore an objective of the claimed invention to provide a driving waveform and circuit for a PDP at a lower cost by reducing the number of components in the driving circuit. 
   A driving circuit for a PDP according to the claimed invention includes an equivalent capacitor having X and Y terminals with the X terminal coupled directly to ground. A first switch is coupled between a first voltage source and a first terminal of a Scan IC, a second switch is coupled between a second voltage source and the first terminal of the Scan IC, an inductor is coupled between a bi-directional third switch and the first terminal of the Scan IC with the third switch coupled to ground, a fourth switch is coupled between a positive terminal of a third voltage source and the Y terminal, a negative terminal of the third voltage source is coupled to the first terminal of the Scan IC, and a fifth switch is coupled between the first terminal of the Scan IC and the Y terminal. 
   The driving circuit of the claimed invention can make the waveforms for a PDP display in each period, not just focusing on a sustain period. The advantages of the claimed invention are that the fewer components can accomplish the driving waveforms, reducing the cost. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a prior art PDP driving circuit. 
       FIG. 2  is a over-view functional block diagram of a PDP driving circuit according to the present invention. 
       FIG. 3  is detailed view of a PDP driving circuit according to the present invention. 
       FIG. 4  is another detailed view of a PDP driving circuit according to the present invention. 
       FIG. 5  is a detailed view of another PDP driving circuit according to the present invention. 
       FIG. 6  is a waveform diagram showing possible switch setting in a PDP driving circuit according to the present invention. 
       FIG. 7  is a detailed view of another PDP driving circuit according to the present invention. 
       FIG. 8  is a detailed view of another PDP driving circuit according to the present invention. 
   

   DETAILED DESCRIPTION 
   Please refer to  FIG. 2 , which is a overview functional block diagram of a PDP driving circuit  200  according to the present invention. A plasma display panel is marked as a panel equivalent capacitor Cp. There are an X-terminal and a Y-terminal electrically connected to the two sides of the panel equivalent capacitor Cp as shown in  FIG. 2 . Unlike the prior art driving circuit  100  that requires circuitry on both sides of the panel equivalent capacitor C panel , the present invention only requires circuitry to be electrically connected to the Y-terminal and the X-terminal is electrically connected directly to ground. The Block  200  of  FIG. 2  represents the Y-side circuits electrically connected to the Y-terminal and comprise Scan ICs and driving circuits. Block  200  is also electrically connected to ground as will be seen. 
   Please refer now to  FIG. 3 , which is a block diagram of the circuitry Block  200  in  FIG. 2 . Block  200  comprises switches S 1 , S 2 , S 3 , S 4 , and S 5 , where S 3  is a bidirectional switch and is electrically connected in series between ground and an inductor L. Switches S 1 , S 2 , and S 4  are electrically connected to voltage sources V 1 , V 2 , and V 3  respectively. V 1  is a positive voltage source and V 2  and V 3  are negative voltage sources where the voltage potential of V 2  is higher than the voltage potential of V 3 . Switches S 1  and S 2  and the inductor L are all electrically connected to each other and to S 5 . The switches S 1 , S 2 , S 4 , and S 5  can each function as fully ON, OFF, a large resistor, and a variable resistor. Transistors QL and QH are in the Scan IC  99  and respectively coupled to first and second terminals of the Scan IC  99 . A voltage source Vys respectively couples to the first and second terminals of the Scan IC  99  in parallel with positive and negative terminals of Vys coupling to QH and QL, respectively. The transistors QH and QL of the Scan IC  99  of block  200  couple to the Y side of the panel equivalent capacitor Cp. The first terminal of the Scan IC  99  couples to the switches S 5  and S 4 . The X side of the panel equivalent capacitor Cp couples to ground. Cp is the panel equivalent capacitor of a PDP. 
     FIG. 4  is a driving circuit  400  that is one detailed embodiment of the driving circuit  200  shown  FIG. 3 . All like numbered components have the same connectivities and functionalities in  FIG. 4  as in  FIG. 3 . Switches S 11 , S 12 , S 21 , S 22 , S 33 , S 34 , S 41 , S 42 , S 51 , and S 52  are all n-channel MOSFETs. R 11 , R 21 , R 41 , and R 51  are resistors. S 1  in  FIG. 4  comprises serially connected MOSFET S 12  and resistor R 11  that are coupled to MOSFET S 11  in parallel. Switch S 2  in  FIG. 4  comprises serially connected MOSFET S 22  and resistor R 21  that are coupled to MOSFET S 21  in parallel. FIG.  4 &#39;s switch S 3  comprises serially connected MOSFETS S 33  and S 34 . Switch S 4  comprises serially connected MOSFET S 42  and resistor R 41  that are coupled to MOSFET S 41  in parallel. Switch S 5  comprises serially connected MOSFET S 52  and resistor R 51  that are coupled to MOSFET S 51  in parallel. According to the different driving waveforms, it is possible to generate the waveforms even though some elements in  FIG. 4  may be removed as will be shown. 
     FIG. 5  is a driving circuit  500  that is another embodiment of the driving circuit  200  of  FIG. 3 . All like numbered components have the same connectivities and functionalities in  FIG. 5  as in  FIG. 3 . The switches S 13 , S 23 , S 33 , S 34 , S 43  and S 53  are all n-channel MOSFETs. Here in  FIG. 5 , S 1  comprises MOSFET S 13  and switch S 2  comprises MOSFET S 23 . Switch S 3  comprises serially coupled MOSFETs S 33  and S 34 . Switch S 4  comprises MOSFET S 43 . Switch S 5  comprises MOSFET S 53 . The MOSFETs S 13 , S 23 , S 43 , and S 53  can each operate in fully ON-mode, OFF-mode, large resistor mode, or variable resistor mode. 
     FIG. 6  illustrates one of the PDP driving waveforms that the driving circuit  500  in  FIG. 5  can realize. In  FIG. 6 , a high level of the signals for all switches indicates an ON-state and a low level of the signals for all switches indicates an OFF-state. If the switch can be operated in either the ON-state or the OFF-state, the signals will be marked as X. The switches can either be fully ON or act as large resistors or variable resistors in ON-state. The operations are as follows. Please refer to  FIG. 5  and  FIG. 6  for examples. 
   Referring to  FIG. 6 , a positive ramp or exponential waveform such as found in time periods ta 1  and ta 2  can be formed as follows. Charge the Y side of the panel equivalent capacitor Cp from low voltage potential to high voltage potential exponentially or linearly by turning on the MOSFETs S 13 , S 53 , and transistor QL or alternatively turning on the MOSFETs S 13 , S 53 , and transistor QH of the scan IC. If the path is through the MOSFETs S 13 , S 53 , and transistor QL of the Scan IC  99 , the highest voltage potential can reach V 1 . If the path is through the MOSFETs S 13 , S 53 , transistor QH of the Scan IC  99 , and the voltage potential Vys, the highest voltage potential can reach (V 1 +Vys). At t=ta 1  and t=ta 2  periods in  FIG. 6 , the MOSFET S 13  and/or S 53  acts as a large resistor or a variable resistor. 
   A negative ramp or exponential waveform such as found in time period tb can be formed in the following manner. Discharge the Y side of the panel equivalent capacitor Cp from high voltage potential to low voltage potential exponentially or linearly by turning on the MOSFET S 23  and either transistor QH or QL of the Scan IC  99 , or alternatively turning on the MOSFET S 43  and either transistor QH or QL of the Scan IC  99 . The MOSFET S 23  or the MOSFET S 43  acts as a large resistor or a variable resistor at this period. If MOSFET S 23  is used, the lowest voltage potential can reach V 2 . If MOSFET S 43  is used, the lowest voltage potential can reach V 3 . At t=tb period in  FIG. 6 , the Y side of the panel equivalent capacitor Cp is pulled down from the voltage potential V 1  to the voltage potential V 3 . The MOSFET S 43  and transistor QL of the Scan IC  99  are turned on and MOSFET S 43  acts as a large resistor or a variable resistor. 
   The clamping waveforms found at time periods tc 1 , tc 2 , and tc 3  can be generated as follows. The Y side of the panel equivalent capacitor Cp is clamped to the voltage potential V 1  by fully turning on the MOSFETs S 13 , S 53 , and transistor QL of the Scan IC  99  (t=tc 3 ). The Y side of the panel equivalent capacitor Cp is clamped to the voltage potential V 2  by fully turning on the MOSFETs S 23 , S 53 , and transistor QL of the Scan IC  99  (t=tc 2 ). The Y side of the panel equivalent capacitor Cp is clamped to the voltage potential V 3  by fully turning on the MOSFET S 43  and transitor QL of the Scan IC  99  (t=tc 1 ). The MOSFETs S 13 , S 23 , S 43 , and S 53  act as short circuits at these periods. At t=tc 1 , t=tc 2  and t=tc 3  periods in  FIG. 6 , the Y side of the panel equivalent capacitor Cp is clamped to the voltage potentials V 3 , V 2  and V 1 , respectively. 
   Sustain pulse waveforms such as found in time periods td 1 , tc 3 , and td 2  are formed as follows. At t=td 1  period in  FIG. 6 , the Y side of the panel equivalent capacitor Cp is charged from V 2  to V 1  through the MOSFETs S 33 , S 34 , and S 53 , transistor QL of the scan IC  99 , and the inductor L. The MOSFETs S 33 , S 34 , and S 53  are fully on and act as short circuits. At t=tc 3  period in  FIG. 6 , the Y side of the panel equivalent capacitor Cp is clamped to the voltage potential V 1  by fully turning on the MOSFETs S 13 , S 53 , and the transistor QL of the Scan IC  99 . The MOSFETs S 13  and S 53  act as short circuits. At t=td 2  period in  FIG. 6 , the Y side of the panel equivalent capacitor Cp is discharged from V 1  to V 2  through the MOSFETs S 33 , S 34 , and S 53 , the transistor QL of the Scan IC  99 , and the inductor L. The MOSFET S 33 , S 34  and S 53  are fully on and act as short circuits. 
   Please refer to t=te period in  FIG. 6 . A scanning waveform such as is found in time period te can be formed with the MOSFET S 43  fully turned on during this period. The transistor QH of the Scan IC  99  is turned on except during the period of producing a scan pulse. At the period of producing the scan pulse, the transistor QL of the Scan IC  99  is turned on instead of the transistor QH of the Scan IC  99 . 
   Please refer to  FIG. 7 . If the voltage potential of V 2  and the voltage potential of V 3  are the same, the switches S 43 /S 4  and S 53 /S 5  in  FIG. 5  can be removed. Remaining connections remain the same as in  FIG. 5 . The abbreviated driving circuit  700  in  FIG. 7  can also generate waveforms similar to those in  FIG. 6  similarly. 
   Please refer to  FIG. 8 . If the voltage potential of V 2  and the voltage potential of V 3  are the same, the switches S 4  and S 5  in  FIG. 4  can be removed. Remaining connections remain the same as in  FIG. 4 . The abbreviated driving circuit  800  in  FIG. 8  can also generate waveforms similar to those in  FIG. 6  similarly. 
   The waveforms in  FIG. 6  of the Y side of the panel equivalent capacitor Cp can be rearranged to adjust the specific timing or the shapes. It is not necessary for the driving waveforms to clamp or stay at ground potential. The waveforms illustrated in  FIG. 6  are merely examples. It is possible to rearrange the waveforms generated according to the above descriptions according to design considerations. 
   In a practical PDP driving circuit, it is possible to parallel more than one switch for sharing the current. For example, switch S 13  in  FIG. 5  can comprise two paralleled n-channel MOSFETs for sharing the current. These two n-channel MOSFETs can be designed for the different slopes. Additionally, an Integrated Gate Bipolar Transistor (IGBP) can replace one or more of the above-described MOSFETS without departing from the spirit of the invention. 
   The driving circuit of the present invention can make appropriate waveforms for a PDP display in each period, not just focusing on a sustain period. The advantages of the claimed invention include fewer components accomplishing the driving waveforms, reducing the cost. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.