Patent Publication Number: US-7897445-B2

Title: Fabrication methods for self-aligned LDD thin-film transistor

Description:
This is a Divisional of U.S. patent application Ser. No. 10/833,487, filed Apr. 27, 2004, now U.S. Pat. No. 7,238,963, which is commonly assigned to the assignee of the present invention, and which is incorporated by reference herein as if fully set forth herein. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a TFT, and more particularly to a TFT with a self-aligned LDD and a method for fabricating the same. 
     2. Description of the Related Art 
     Thin-film transistors (TFTs) are widely used in active matrix liquid crystal display (AMLCD). A leakage current occurs, however, when the TFT is turned off, and the charges in the active matrix liquid crystal display are thereby lost. A lightly doped drain (LDD) structure has been used to reduce the electric field of the surface of the drain, such that the leakage current can be reduced. 
     In  FIGS. 1A to 1B  are cross-sections of the conventional method for fabricating a TFT with a self-aligned LDD. 
     In  FIG. 1A , a transparent insulating substrate  101  is provided, a semiconductor layer  102  and a gate insulating layer  104  formed on the substrate  101 , and the semiconductor layer  102  is covered by the gate insulating layer  104 . 
     A patterned photoresist layer  106  is formed on the gate insulating layer  104 . Heavy doping is performed on the semiconductor layer  102  to form a heavily doped region  108  as a source/drain (S/D) region except in the region covered by the photoresist layer  106 . 
     In  FIG. 1B , the photoresist layer  106  is removed. A gate layer  120  (e.g., a conductive layer) is formed on the gate insulating layer  104 , and the gate layer  120  covers a portion of the undoped region of the semiconductor layer  102 . Light doping is performed on the undoped region of the semiconductor layer  102  to form a LDD region using the gate layer  120  as a mask. The region of the semiconductor layer  102   a  that is covered by the gate layer  120  is a channel. 
     The pattern in the photoresist layer  106  defined by an additional mask in the conventional method results in a process that requires a separate masking step and doping procedure for forming the LDD region, which region is easily shifted by misalignment of the mask such that the electrical properties of TFT are affected. 
     SUMMARY OF THE INVENTION 
     The present invention provides a process of forming a semiconductor device, which comprises heavily doped and lightly doped regions in a semiconductor layer formed in a single doping operation. This is accomplished by providing a masking layer having a relatively thicker section that corresponds to a region to be lightly doped, in comparison to a region that is heavily doped. 
     In one embodiment of the present invention, a masking layer covers the region of the semiconductor layer to be lightly doped and exposes the region of the semiconductor layer to be heavily doped during the doping process. The masking layer is permeable to dopant, but provides a barrier to the dopant such that the covered region is lightly doped compared to the heavily doped region. The thickness of the mask is chosen in relation to the doping parameters (e.g., time, dopant, concentration, etc.) to result in the desired doping levels in the lightly doped region and the heavily doped region in a single doping operation. 
     In another aspect of the present invention, it is directed to a self-aligned LDD TFT and a method for fabricating the same. LDD region of the present invention is formed by controlling the width and/or width of the gate insulating layer using only one mask. 
     In another aspect, the present invention provides a LDD TFT having a multi-gate structure, in which LDD regions are formed laterally adjacent to two sidewalls of each gate layer in the multi-gate structure. Each gate structure is formed with LDD and highly doped regions in accordance with the present invention, and two adjacent gate structures are interconnected by a common doped region having a different dopant concentration as the LDD region. In one embodiment, the common doped region is higher dope concentration than the LDD region, but lower dope concentration as the highly doped region. The common doped region may be formed by applying a shielding mask during an intermediate doping step between formation of LDD and highly doped regions. 
     Accordingly, the present invention provides a self-aligned LDD TFT. The TFT comprises a substrate, a semiconductor layer, a gate insulating layer, and a gate. The semiconductor layer having a channel is formed on the substrate, a first doping region is formed on both sides of the channel region, and a second doping region is formed on both sides of the first doping region. The gate insulating layer is formed, covering the semiconductor layer, and the gate insulating layer covers the channel region and the first doping region. The gate is formed on the gate insulating layer corresponding to the channel region. 
     Accordingly, the present invention also provides a LDD TFT having a multi-gate structure. An active layer is formed on a substrate and comprises a first lightly doped region, a second lightly doped region, and a third lightly doped region formed laterally adjacent to the first lightly doped region respectively, a first channel region and a second channel region extending laterally away from the second lightly doped region and the third lightly doped region respectively, a fourth lightly doped region and a fifth lightly doped region extending laterally away from the first channel region and the second channel region respectively, and a first heavily doped region and a second heavily doped region extending laterally away from the fourth lightly doped region and the fifth lightly doped region, respectively. A first gate insulating layer is formed on the active layer and comprises a central region covering the first channel region of the active layer, a first shielding region covering the fourth lightly doped region of the active layer, and a second shielding region covering the second lightly doped region of the active layer. A second gate insulating layer is formed on the active layer and comprises a central region covering the second channel region of the active layer, a first shielding region covering the third lightly doped region of the active layer, and a second shielding region covering the fifth lightly doped region of the active layer. A first gate layer covers the central region of the first gate insulating layer, and a second gate layer covers the central region of the second gate insulating layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a better understanding of the present invention, reference is made to a detailed description to be read in conjunction with the accompanying drawings, in which: 
         FIGS. 1A to 1B  are cross-sections illustrating the steps of the conventional method for fabricating a self-aligned LDD TFT; 
         FIGS. 2A to 2F  are cross-sections illustrating the steps of the method for fabricating a self-aligned LDD TFT in accordance with the first embodiment of the present invention; 
         FIGS. 3A to 3E  are cross-sections of a fabrication method for a LDD TFT having a dual-gate structure according to the second embodiment of the present invention; 
         FIG. 4  is a schematic diagram of a display device comprising the LDD TFT in accordance with one embodiment of the present invention; and 
         FIG. 5  is a schematic diagram of an electronic device comprising the display device in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention provides a process for forming a semiconductor device, in which heavily doped and lightly doped regions are simultaneously formed in a semiconductor layer during doping operation. This is accomplished by providing a masking layer having a relatively thicker section that correspond to a region to be lightly doped, in comparison to a region that is heavily doped. By way of example and not limitations, the present invention is described below in connection with the formation of an LDD TFT. 
     In one embodiment of the present invention, a masking layer covers the region of the semiconductor layer to be lightly doped and exposes the region of the semiconductor layer to be heavily doped during the doping process. The masking layer is permeable to dopant, but provides a barrier to the dopant such that the covered region is lightly doped compared to the heavily doped region. The thickness of the masking layer is chosen in relation to the doping parameters (e.g., doping time, concentration, dopant, etc.) to result in the desired doping levels in the lightly doped region and the heavily doped region. This embodiment is illustrated in reference to  FIGS. 2A to 2F  below. It is noted that intermediate and/or additional steps and structures maybe included without departing from the scope and spirit of the present invention, but they are omitted from the drawings to avoid obscuring the disclosure of the present invention. 
     First Embodiment 
       FIGS. 2A to 2F  are cross-sections illustrating the steps of the method for fabricating a self-aligned LDD TFT in accordance with the first embodiment of the present invention. 
     In  FIG. 2A , a substrate  201 , such as a transparent insulating substrate or glass substrate, is provided. A buffer layer  202 , such as a silicon oxide layer, and a semiconductor layer  203 , such as a polysilicon layer, are sequentially formed on the substrate  201 . The buffer layer  202  helps the formation of the semiconductor layer  203  on the substrate  201 . 
     In  FIG. 2B , a gate insulating layer  204 , such as an oxide layer or a nitride layer, a conductive layer  205 , such as a metal layer, and a patterned photoresist layer  206  for forming a gate, are sequentially formed on the semiconductor layer  203 . The thickness of the gate insulating layer  204  is about 200 to 10000 Å. 
     In  FIG. 2C , the conductive layer  205  and the gate insulating layer  204  are sequentially etched until the semiconductor layer  203  is exposed to form a conducting layer  205   a  and a gate insulating layer  204   a . The etching can be plasma etching. 
     In  FIG. 2D , the conductive layer  205   a  is etched by a gas mixture of oxygen-containing gas and other gas, such as chlorine-containing gas, to form a conductive layer  205   b  as a gate so as to expose a portion of the gate insulating layer  204   a  synchronously. 
     The flow rate of the oxygen in the gas mixture can be adjusted, and the etching step shown in  FIG. 2C  can be omitted or combined with the etching step shown in  FIG. 2D  to reduce processing time. In this case, the conductive layer  205   a  and the gate insulating layer  204   a  are etched by a minimum flow of oxygen, and the conductive layer  205   a  is etched to form a trapezoid gate, by increasing the flow rate of oxygen, even a maximum oxygen flow. 
     In  FIG. 2E , the patterned photoresist layer  206   b  is removed. The semiconductor layer  203  is ion implanted with about 30 to 100 kev energy using the conducting layer  205   b  and the gate insulating layer  204   a  as masks to form a first doped region  203   b  as lightly doped drain (LDD) and a second doped region  203   c  as source/drain (S/D). 
     In  FIG. 2F , the first doped region  203   b  is formed in the semiconductor layer  203 , covered by the gate insulating layer  204   a  but not the conductive layer  205   b . The second doped region  203   c  is formed in the semiconductor layer  203  covered by the gate insulating layer  204   a  and the conductive layer  205   b.    
     The concentration of the first doped region  203   b  is lower than in the second doped region  203   c  because the first doped region  203   b  is covered by the gate insulating layer  204   a  and the second doped region  203   c  is not covered by the gate insulating layer  204   a . By appropriately defining the thickness of the gate insulating layer  204   a  in relation to the doping process parameters (e.g., dopant, doping time, concentration, etc.), the desired doping concentrations in the first and second doped regions  203   b  and  203   c  may be achieved when they are exposed to the same doping operation, e.g., using the same doping process parameters. 
     For certain applications, it may be desired to alter the doping process parameters and/or using a different or additional mask during the doping process. For example, after initial doping to form the lightly and heavily doped regions using a particular dopant concentration, a mask may be applied to cover the lightly doped region. Such variation is well within the scope and spirit of the present invention. 
       FIG. 2F  is a simplified basic LDD TFT configuration, including a drain, source and a channel. Further steps to complete the may include steps to form, for example, electrodes, metalization, interconnect structures, passivation layers, etc. known in the art. 
     In a case of a TFT with CMOS, the semiconductor layer  203  is heavily implanted with P or As ions to form S/D, a second doped area  203   c , and a first doped region  203   b . The concentration of S/D and the second doped region  203   c  are about 1×10 14 ˜1×10 16  atom/cm 2 , and the concentration of the first doped region  203   b  is about 1×10 12 ˜1×10 14  atom/cm 2 . 
     The present invention also provides a LDD TFT having a multi-gate structure and a fabrication method thereof. A gate insulating layer comprises two shielding regions laterally exposed to agate layer and used as a mask, such that LDD regions and source/drain regions can be completed in an ion implantation process simultaneously. Also, the LDD regions are formed laterally adjacent to two sidewalls of each gate layer in the multi-gate structure, thus effectively restraining leakage current and eliminating placement shifting and length-asymmetry problems caused by the photo misalignment. A LDD TFT having a dual-gate structure is described below for example. 
     Second Embodiment 
       FIGS. 3A to 3E  are cross-sections of a fabrication method for a LDD TFT having a dual-gate structure according to this embodiment. 
     In  FIG. 3A , a substrate  30  is provided with a buffer layer  32  and a semiconductor layer  34  successively formed thereon. The substrate  30  is a transparent insulating substrate, such as a glass substrate. The buffer layer  32  is a dielectric layer, such as a silicon oxide layer, for improving the formation of the semiconductor layer  34  on the substrate  30 . The semiconductor layer  34  is a polysilicon layer. In order to adjust threshold voltage of transistor, B +  or P +  ion implantation process may be performed thereon. 
     In  FIG. 3B , an insulating layer  36  and a conductive layer  38  are successively deposited on the semiconductor layer  34 .  30  The insulating layer  36  may be made of silicon oxide, silicon nitride, silicon-oxide-nitride or a combination thereof. The conductive layer  38  (not shown) may be a metal layer or a polysilicon layer. Dry etching with a patterned photoresist mask then forms the conductive layer  38  as a first gate layer  38 I and a second gate layer  38 II. In  FIG. 3C , plasma etching or reactive ion etching is employed with a reactive gas mixture of an oxygen-containing gas and a chlorine-containing gas, whereby the gate layers  38 I and  38 II of a trapezoid profile and two isolated gate insulating layers  40  and  42  are completed by adjusting the individual flow of the oxygen-containing gas or the chlorine-containing gas in a timely manner. For example, during the etching process for the gate layers  38 I and  38 II, the flow of the chlorine-containing gas is gradually tuned to a maximum, even if chlorine-containing gas is the only gas used. During the etching process for the insulating layer  36 , the flow of the oxygen-containing gas is gradually increased to a maximum, such that a part of the patterned photoresist mask is removed and the gate layers  38 I and  38 II exposed again by the patterned photoresist mask is etched simultaneously. The photoresist mask is then removed. 
     The first gate insulating layer  40  comprises a central region  40   a  and two shielding regions  40   b   1  and  40   b   2 . The central region  40   a  is covered by the bottom of the first gate layer  38 I. The two shielding regions  40   b   1  and  40   b   2  extend laterally away from the central region  40   a , respectively, without being covered by the first gate layer  38 I. The first gate insulating layer  40  exposes a predetermined source/drain region. The first shielding region  40   b   1  has a lateral length W 1  of 0.1 μm˜2.0 μm, and the second shielding region  40   b   2  a lateral length W 2  of 0.1 μm˜2.0 μm. Depending on requirements for circuit designs, the size and symmetry of the lateral lengths W 1  and W 2  may be adequately modified. 
     The second gate insulating layer  42  comprises a central region  42   a  and two shielding regions  42   b   1  and  42   b   2 . The central region  42   a  is covered by the bottom of the second gate layer  38 II. The two shielding regions  42   b   1  and  42   b   2  extend laterally away from the central region  42   a , respectively, without being covered by the second gate layer  38 II. The second gate insulating layer  42  exposes a predetermined source/drain region. The first shielding region  42   b   1  has a lateral length D 1  of 0.1 μm˜2.0 μm, and the second shielding region  42   b   2  has a lateral length D 2  of 0.1 μm˜2.0 μm. Depending on requirements for circuit designs, the size and symmetry of the lateral lengths W 1 , W 2 , D 1  and D 2  may be adequately modified. For example, W 1 =W 2  and D 1 =D 2 . 
     The second shielding region  40   b   2  of the first gate insulating layer  40  is located adjacent to the first shielding. region  42   b   1  of the second gate insulating layer  42 , and a space between the second shielding region  40   b   2  and the first shielding region  42   b   1  exposes the active layer  34 . Also, the active layer  34  outside the first shielding region  40   b   1  of the first gate insulating layer  40  and the second shielding region  42   b   2  of the second gate insulating layer  42  is exposed. 
     In  FIG. 3D , a lightly doped ion implantation process  44  is employed, and the gate layers  38 I and  38 II and the shielding regions  40   b   1 ,  40   b   2 ,  42   b   1  and  42   b   2  are used as masks, such that a plurality of regions  341 ˜ 349  with various doping concentrations is formed in the active layer  34 . The first region  341  and the second region  342  are undoped, correspondingly located underlying the central regions  40   a  and  42   a , respectively. The third region  343  and the fourth region  344  are N −−  regions, correspondingly located underlying the shielding regions  40   b   1  and  40   b   2 , respectively. The fifth region  345  and the sixth region  346  are N −−  regions, correspondingly located underlying the shielding regions  42   b   1  and  42   b   2 , respectively. The seventh region  347  is an N −  region exposed laterally adjacent to the first shielding region  40   b   1  of the first gate insulating layer  40 . The eighth region  348  is an N −  region exposed laterally adjacent to the second shielding region  42   b   2  of the second gate insulating layer  42 . The ninth region  349  is an N −  region exposed in the space between the shielding regions  40   b   2  and  42   b   1 . Since the shielding regions  40   b   1  and  40   b   2  are used as masks, the margins of the regions  343  and  344  are substantially aligned to the edges of the shielding regions  40   b   1  and  40   b   2 , respectively. Since the shielding regions  42   b   1  and  42   b   2 are used as masks, the margins of the regions  345  and  346  are substantially aligned to the edges of the shielding regions  42   b   1  and  42   b   2  respectively. In addition, by adjusting accelerated voltage and dosage of the lightly doped ion implantation process  44 , the doping concentrations of the regions  343 ,  344 ,  345  and  346  can be modified to become N −−  regions or intrinsic regions (offset regions). 
     In  FIG. 3E , a photoresist layer  46  is formed to cover the second shielding region  40   b   2  of the first gate insulating layer  40 , the first shielding region  42   b   1  of the second gate insulating layer  42 , and the ninth region  349  exposed in the space between the shielding regions  40   b   2  and  42   b   1 . Finally, a heavily-doped ion implantation process  48  is performed, and the photoresist layer  46 , the gate layers  38 I and  38 II, and the shielding regions  40   b   1  and  42   b   2  are used as masks, such that the doping concentrations of the regions  343  and  346  are increased to become N −  regions and the doping concentrations of the regions  347  and  348  are increased to become N +  regions. 
     Accordingly, the seventh region  347  and the eighth region  348  are N +  regions, serving as a source region and a drain region respectively. The third region  343  and the sixth region  346  are N −  regions, serving as two LDD regions. The fourth region  344  and the fifth region  345  are N −−  regions, serving as another two LDD regions, located between the two gate layers  38 I and  38 II. The ninth region  349  is an N −  region, serving as common source/drain region. The first region  341  and the second region  342  are undoped, serving as two channel regions of the dual-gate structure. Preferably, the doping concentration for regions  347  and  348  is 1×10 14 ˜1×10 16  atom/cm 2 , for regions  343 ,  346  and  349 , 1×10 12 ˜1×10 14  atom/cm 2 , and for regions  344  and  345 , less than 1×10 13  atom/cm 2 . 
     The LDD TFT may be used in a N-MOS TFT, such that the lightly doped regions are N −  regions, and heavily doped regions are N +  regions. Alternatively, the LDD TFT is used in a P-MOS TFT, such that the lightly doped regions are P −  regions, and heavily doped regions are P +  regions. Subsequent interconnect process including formation of inter-dielectric layers, contact holes and interconnects on the thin film transistor is omitted herein. 
     The LDD TFT and the fabrication method thereof have the following advantages. 
     First, two symmetrical LDD regions outside the two gate layers  38 I and  38 II and two symmetrical LDD regions between the two gate layers  38 I and  38 II are formed simultaneously, thus effectively reducing current leakage. 
     Second, the ion implantation process uses the shielding regions  40   b   1 ,  40   b   2 ,  42   b   1  and  42   b   2  as masks, thus completing self-aligned LDD regions and source/drain regions simultaneously. 
     Third, by adjusting parameters of the etching process, the lateral lengths W 1 , W 2 , D 1  and D 2  of the shielding regions  40   b   1 ,  40   b   2 ,  42   b   1  and  42   b   2  can be accurately controlled, thus ensuring proper positioning of the LDD structure and electric performance of the LDD TFT. 
     Fourth, since an extra photomask or a spacer structure for defining the LDD regions are not used, shifting of the LDD regions due to photo misalignment in exposure is prevented, further improving accuracy in positioning the LDD regions. 
     Fifth, the heavily doped ion implantation process  48  uses the photoresist layer  46  as a mask without a high-accuracy pattern, thus simplifying a photolithography process for the photoresist layer  46 . 
       FIG. 3E  is a simplified basic LDD TFT having a multi-gate structure configuration. Further steps to complete the LDD TFT may include steps to form, for example, electrodes, metalization, interconnect structures, passivation layers, etc. known in the art. 
       FIG. 4  is a schematic diagram of a display device  3  comprising the LDD TFT in accordance with one embodiment of the present invention. The display panel  1  can be couple to a controller  2 , forming a display device  3  as shown in  FIG. 4 . The controller  3  can comprise a source and a gate driving circuits (not shown) to control the display panel  1  to render image in accordance with an input. 
       FIG. 5  is a schematic diagram of an electronic device  5 , incorporating a display comprising the LDD TFT in accordance with one embodiment of the present invention. An input device  4  is coupled to the controller  2  of the display device  3  shown in  FIG. 4  can include a processor or the like to input data to the controller  2  to render an image. The electronic device  5  may be a portable device such as a PDA, notebook computer, tablet computer, cellular phone, or a desktop computer. 
     The present invention provides a method for accurately forming LDD structure of TFT by adjusting the width and thickness of the gate insulating layer and the energy of the implantation. Additional masks to define a pattern of LDD are not required, and errors from misalignment of the mask are avoided. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.