Patent Publication Number: US-2023146693-A1

Title: Display panel

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 17/406,632 filed on Aug. 19, 2021, which is a continuation of U.S. patent application Ser. No. 16/860,164 filed on Apr. 28, 2020, issued as U.S. Pat. No. 11,100,881 on Aug. 24, 2021, which is a continuation application of U.S. application Ser. No. 16/553,642 filed on Aug. 28, 2019, issued as U.S. Pat. No. 10,770,020 on Sep. 8, 2020, which is a continuation of U.S. application Ser. No. 15/613,698 filed Jun. 5, 2017, issued as U.S. Pat. No. 10,403,221 on Sep. 3, 2019, which is a continuation of U.S. application Ser. No. 12/949,931 filed Nov. 19, 2010, issued as U.S. Pat. No. 9,672,782 on Jun. 6, 2017, which claims priority to and the benefit of Korean Patent Application No. 10-2009-0115171 filed in the Korean Intellectual Property Office on Nov. 26, 2009, the entire contents of which are incorporated by reference herein. 
    
    
     BACKGROUND 
     (a) Technical Field 
     The present disclosure relates to display panels, and, more particularly, to a display panel having a gate driver integrated therein. 
     (b) Discussion of the Related Art 
     As one of a group of widely used display panels, a liquid crystal display (LCD) includes two display panels provided with field generating electrodes such as pixel electrodes and a common electrode, and a liquid crystal layer interposed therebetween. The LCD displays images by applying voltages to the field-generating electrodes to generate an electric field in the LC layer that determines the orientation of LC molecules therein to adjust the polarization of incident light. Organic light emitting devices, plasma display devices, and electrophoretic displays, as well as LCDs, are examples of such widely used display panels. 
     These display devices include a gate driver and a data driver. The gate driver can be integrated on the panel by being patterned along with a gate line, a data line, and a thin film transistor. A separate gate driving chip can be avoided by forming an integrated gate driver, thereby reducing manufacturing cost. However, thin film transistors formed inside the integrated gate driver can generate leakage current while the gate off signal is output such that undesired increased power consumption occurs. 
     Also, the characteristics of the semiconductor particularly an amorphous semiconductor) of the thin film transistor are changeable according to temperature, and as a result, gate voltage output at high temperature does not have a uniform waveform and noise is generated. 
     SUMMARY 
     In accordance with an exemplary embodiment of the present invention power consumption of a gate driver integrated in a display panel is reduced and a gate voltage having a uniform waveform at high temperature is output. 
     According to an exemplary embodiment a display panel includes a display area having a gate line. A gate driver is connected to one end of the gate line, the gate driver including a plurality of stages and integrated on a substrate. The stages receive a clock signal, a first low voltage and a second low voltage that is lower than the first low voltage, at least one transmission signal from a previous stage, and at least two transmission signals from a next stage to output a gate voltage having a first low voltage as a gate-off voltage. 
     The gate voltage when the transmission signal is low may be the second low voltage. 
     At least one transmission signal applied to a first stage may be a scanning start signal. 
     The display area may include a data line. The display panel may include a data driver that supplies a data voltage which is applied to the data line. The data driver may be formed at an upper side or a lower side of the display panel. 
     The stages may include an input section, a pull-up driver, a pull-down driver, an output section, and a transmission signal generator. 
     The input section, the pull-down driver, the output section, and the transmission signal generator may be connected to a first node. 
     The input section may be connected between a first input terminal input that receives at least one transmission signal from the previous stage and the first node. 
     The output section may be connected between a gate voltage output terminal that outputs the gate voltage, a clock input terminal input with the clock signal, and the first node, such that the gate voltage is output according to the voltage of the first node. 
     The transmission signal generator may be connected between a transmission signal output terminal that outputs the transmission signal, the clock input terminal, and the first node, such that the transmission signal is output according to the voltage of the first node. 
     The pull-up driver and the pull-down driver may be connected to a second node. 
     The pull-down driver may be connected to each terminal that inputs at least two transmission signals from the next stage, which are the first low voltage and the second low voltage, the transmission signal output terminal, and the gate voltage output terminal, and is also connected to the first node and the second node. 
     The pull-down driver may include an element that pulls down the first node, an element that pulls down the second node, an element that pulls down the transmission signal output terminal, and an element that pulls down the gate voltage output terminal. 
     The element that pulls down the first node may decrease the voltage of the first node to the second low voltage according to one of at least two transmission signals from the next stage and the voltage of the second node voltage. 
     Decreasing of the voltage of the first node to the second low voltage according to one transmission signal of at least two transmission signals from the next stage may be executed through a first transistor having a control terminal that receives one transmission signal of at least two transmission signals from the next stage and an input terminal connected to the first node, and a second transistor having a control terminal and an input terminal connected to an output terminal of the first transistor and an output terminal connected to the second low voltage. 
     The element that pulls down the second node may decrease the voltage of the second node to the second low voltage according to at least one transmission signal from the previous stage or the transmission signal of the corresponding stage. 
     The element that pulls down the second node may decrease the voltage of the second node to the second low voltage according to at least one transmission signal from the previous stage, and decreases the voltage of the second node to the first low voltage according to the transmission signal of the corresponding stage. 
     The element that pulls down the transmission signal output terminal ma decrease the voltage of the transmission signal output terminal to the second low voltage according to the voltage of the second node. 
     The element that pulls down the transmission signal output terminal ma decrease the voltage of the transmission signal output terminal to the second low voltage according to one of at least two transmission signals from the next stage. 
     The element that pulls down the gate voltage output terminal may decrease the voltage of the gate voltage output terminal to the first low voltage according to the voltage of the second node or one of at least two transmission signals from the next stage. 
     The pull-up driver may be connected to the clock input terminal, the pull-down driver, and the second node. 
     At least one transmission signal from the previous stage may the transmission signal of the neighboring previous stage, or at least two transmission signals from the next stage may be the transmission signals of two next stages that continuously neighbor each other. 
     According to an exemplary embodiment of the present invention, the circuit of each stage is decreased to a lower potential than the gate-off voltage such that the current leakage is reduced, thereby obtaining the low power consumption, and a ripple applied through the transmission signal may be reduced at a high temperature such that a uniform gate-on voltage may be output at a high temperature. Also, although the further lower voltage is applied at the low temperature, it is possible to operate it and the lifespan is increased. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a plan view of a display panel according to an exemplary embodiment of the present invention. 
         FIG.  2    is a block diagram showing the gate driver and the gate line of  FIG.  1    in further detail. 
         FIG.  3    is a circuit diagram of one stage and one gate line in  FIG.  2   . 
         FIG.  4    is a graph comparing power consumption when using the exemplary embodiment of  FIG.  3    with power consumption according to the conventional art. 
         FIG.  5    is a plan view of a display panel according to an exemplary embodiment of the present invention. 
         FIG.  6    is a block diagram showing the gate driver and the gate line of  FIG.  5    in further detail. 
         FIG.  7    is a circuit diagram of one stage and one gate line in  FIG.  6   . 
         FIG.  8    is a graph comparing power consumption when using the exemplary embodiment of  FIG.  7    with power consumption according to the conventional art. 
         FIG.  9    is a graph showing current flowing in the first transistor that outputs a gate voltage in a gate driver according to the conventional art with reference to a clock signal CKV. 
         FIG.  10    is a graph showing current flowing in the first transistor that outputs a gate voltage in a gate driver according to the exemplary embodiment of  FIG.  7    with reference to a clock signal CKV. 
         FIGS.  11 ,  12  and  13    are graphs showing characteristics at high temperature, characteristics at low temperature, and characteristics for a lifespan when using the exemplary embodiment of  FIG.  7    as compared with the conventional art. 
     
    
    
     DETAILED DESCRIPTION 
     The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present invention. 
     Like reference numerals designate like elements throughout the specification and drawings. 
     Referring to  FIG.  1   , a display panel  100  according to an exemplary embodiment of the present invention includes a display area  300  displaying images, and a gate driver  500  applying a gate voltage to a gate line of the display area  300 . A data line of the display area  300  receives a data voltage from a data driver IC  460  formed on a flexible printed circuit film (FPC)  450  attached to the display panel  100 . The gate driver  500  and the data driver IC  460  are controlled by a signal controller  600 . A printed circuit board (PCB)  400  is formed outside the flexible printed circuit film  450 , and transmits the signal from the signal controller  600  to the data driver IC  460  and the gate driver  500 . The signal provided from the signal controller  600  may include a signal such as a first clock signal CKV, a second clock signal CKVB, a scan start signal STVP, and a signal providing low voltages Vss 1 , Vss 2  of a particular level. 
       FIG.  1    shows an example of the liquid crystal panel. When the display area  300  is a liquid crystal panel, the display area includes a thin film transistor Trsw, a liquid crystal capacitor Clc, and a storage capacitor Cst, and. On the other hand, the display area  300  for an organic light emitting panel includes a thin film transistor and an organic light emitting diode, and the display area  300  for other display panels includes elements such as a thin film transistor. Hereinbelow, an exemplary embodiment of a liquid. crystal panel will be described in more detail. 
     The display area  300  includes a plurality of gate lines G 1 , . . . Gn and a plurality of data lines D 1 , . . . Dm. The plurality of gate lines G 1 , . . . Gn and the plurality of data lines D 1 , . . . Dm are insulated from and intersect each other. 
     Each pixel PX includes the thin film transistor Trsw, the liquid crystal capacitor Clc, and the storage capacitor Cst. The control terminal of the thin film transistor Trsw is connected to one gate line, the input terminal of the thin film transistor Trsw is connected to one data line, and the output terminal of the thin film transistor Trsw is connected to one terminal of the liquid crystal capacitor Clc and one terminal of the storage capacitor Cst. The other terminal of the liquid crystal capacitor Clc is connected to the common electrode, and the other terminal of the storage capacitor Cst receives a storage voltage Vcst applied from the signal controller  600 . 
     The plurality of data lines D 1 , . . . Dm receive the data voltages from the data driver IC  460 , and the plurality of gate lines G 1 , . . . Gn receive the gate voltage from the gate driver  500 . 
     The data driver IC  460  is formed at the upper side or the lower side of the display panel  100  thereby being connected to the data lines D 1 , . . . Dm extended in the longitudinal direction. In the exemplary embodiment depicted in  FIG.  1    the data driver IC  460  is positioned at the upper side of the display panel  100 . 
     The gate driver  500  receives the clock signals CKV, CKVB, the scan start signal STVP, the first low voltage Vss 1  conforming to the gate-off voltage, and the second low voltage Vss 2  that is less than the gate-off voltage to generate gate voltages (a gate-on voltage and a gate-off voltage) and sequentially apply the gate-on voltage to the gate lines G 1 , . . . Gn. 
     The clock signals CKV, CKVB, the scan start signal STVP, the first low voltage Vss 1 , and the second low voltage Vss 2  applied to the gate driver  500  are applied to the gate driver  500  through the flexible printed circuit film  450  positioned at the outmost side and the side of the gate driver  500 , as shown in  FIG.  1   . These signals are transmitted to the flexible printed circuit film  450  through the printed circuit board PCB  400  from the signal controller  600 , or, in an alternative embodiment, from externally. 
     Next, the detailed description will focus on an exemplary embodiment of the gate driver  500  and the gate lines G 1 , . . . Gn.  FIG.  2    is a block diagram showing the gate driver and the gate lines of  FIG.  1    in further detail. The display area  300  is shown to have a resistor Rp and a capacitor Cp. The gate lines G 1 , . . . Gn, the liquid crystal capacitor Clc, and the storage capacitor Cst respectively have resistances and capacitances, and their sums are represented as one resistance Rp and one capacitance Cp. The gate voltage output from the stage SR is transmitted through the gate lines. As shown in  FIG.  2   , the gate line may be represented as the resistance Rp and the capacitance Cp in a circuit diagram. These values depict a representative value for one gate line, but may change according to the structure and the characteristics of the display area  300 . 
     The gate driver  500  includes a plurality of stages SR 1 , SR 2 , SR 3 , SR 4 , . . . that are dependently connected to each other. Each of the stages SR 1 , SR 2 , SR 3 , SR 4 , . . . includes three input terminals IN 1 , IN 2 , IN 3 , one clock input terminal CK, two voltage input terminals Vin 1 , Vin 2 , a gate voltage output terminal OUT that outputs the gate voltage, and a transmission signal output terminal CRout. 
     The first input terminal IN 1  is connected to the transmission signal output terminal CRout of the previous stage thereby receiving the transmission signal CR of the previous stage. However, the first stage does not have a previous stage such that the scan start signal STVP at the first input terminal IN 1  is applied. 
     The second input terminal IN 2  is connected to the transmission signal output terminal CRout of the next stage thereby receiving the transmission signal CR of the next stage. Also, the third input terminal IN 3  is connected to the transmission signal output terminal CRout of the second next stage thereby receiving the transmission signal CR of the second next stage. 
     A stage SRn (not shown) connected to the n-th gate line tin may have two dummy stages to receive the transmission signal CR from the next stage and the second next stage. The dummy stages (SRn+1, SRn+2; not shown) are stages that generate and output a dummy gate voltage, different from the stages SR 1 , SR 2 , SR 3 , SR 4 , . . . SRn. 
     That is, the gate voltage output from the stages SR 1 , SR 2 , SR 3 , SR 4 , . . . SRn is transmitted though the gate lines such that the data voltage is applied to the pixel for the display of the images, however the dummy stages SRn+1, SRn+2 would not be connected to the gate lines, although when they are connected to the gate lines, they are connected to the gate lines of a dummy pixel (not shown) that do not display the image such that they would not be used for the display of the image. 
     The clock terminals CK are applied with a clock signal, and among the plurality of stages, the clock terminals CK of the odd-numbered stages are applied with the first clock signal CKV and the clock terminals CK of the even-numbered stages are applied with the second clock signal CKVB, The first clock signal CKV and the second clock signal CK VB have opposite phases to each other. 
     The first voltage input terminal Vin 1  is applied with the first low voltage Vss 1  corresponding to the gate-off voltage, and the second voltage input terminal Vin 2  is applied with the second low voltage Vss 2  that is lower than the first low voltage Vss 1 . The voltage values of the first low voltage Vss 1  and the second low voltage Vss 2  may vary according to the particular exemplary embodiment. In the present exemplary embodiment the value of the first low voltage Vss 1  is −5V and the value of the second low voltage Vss 2  is −10V. 
     The operation of the gate driver  500  will now be described in more detail. The first stage SRI receives the first clock signal CKV provided from outside to the clock input terminal CK, the scan start signal STVP through the first input terminal IN 1 , the first and second low voltages Vss 1 , Vss 2  through the first and second voltage input terminals Vin 1 , Vin 2 , and the transmission signals CR respectively provided from the second stage SR 2  and the third stage SR 3  through the second and third input terminals IN 2 , IN 3  such that the gate-on voltage is output to the first gate line through the gate voltage output terminal OUT. Also, the transmission signal output terminal CRout outputs the transmission signal CR, and it is transmitted to the first input terminal IN 1  of the second stage SR 2 . 
     The second stage SR 2  receives the second clock signal CKVB provided from outside to the clock input terminal CK, the transmission signal CR of the first stage SR 1  through the first input terminal IN 1 , the first and second low voltages Vss 1 , Vss 2  through the first and second voltage input terminals Vin 1 , Vin 2 , and the transmission signals CR respectively provided from the third stage SR 3  and the fourth stage SR 4  through the second and third input terminals IN 2 , IN 3  such that the gate-on voltage is output to the second gate line through the gate voltage output terminal OUT. Also, the transmission signal CR is output through the transmission signal output terminal CRout thereby being transmitted to the first input terminal IN 1  of the third stage SR 3  and the second input terminal IN 2  of the first stage SR 1 . 
     The third stage SR 3  receives the first clock signal CKV provided from outside to the clock input terminal CK, the transmission signal CR of the second stage SR 2  through the first input terminal IN 1 , the first and second low voltages Vss 1 , Vss 2  through the first and second voltage input terminals Vin 1 , Vin 2 , and the transmission signals CR respectively provided from the fourth stage SR 4  and the fifth stage SRS through the second and third input terminals IN 2 , IN 3  such that the gate-on voltage is output to the third gate line through the gate voltage output terminal OUT. Also, the transmission signal CR is output through the transmission signal output terminal CRout thereby being transmitted to the first input terminal IN 1  of the fourth stage SR 4 , the third input terminal IN 3  of the first stage SR 1 , and the second input terminal IN 2  of the second stage SR 2 . 
     Through the above method, the nth stage SRn receives the second clock signal CKVB provided from the outside to the clock input terminal CK, the transmission signal CR of the n-1-th stage SRn−1 through the first input terminal IN 1 , the first and second low voltages Vss 1 , Vss 2  through the first and second voltage input terminals Vin 1 , Vin 2 , and the transmission signals CR respectively provided from the (n+1)-th stage SRn+1 (the dummy stage) and the (n+2)-th stage SRn+2 (the dummy stage) through the second and third input terminals IN 2 , IN 3  such that the gate-on voltage is output to the n-th gate line through the gate voltage output terminal OUT. Also, the transmission signal CR is output through the transmission signal output terminal CRout thereby being transmitted to the first input terminal IN 1  of the (n+1)-th stage SRn+1 (the dummy stage), the third input terminal IN 3  of the (n−2)-th stage SRn−2, and the second input terminal IN 2  of the (n−1)-th stage SRn−1. 
     The connection structure of the stages SR of the gate driver  500  has been described with reference to  FIG.  2   . Next, the structure of an exemplary embodiment of a representative stage SR of a gate driver connected to one gate line will be described in further detail with reference to  FIG.  3   . 
       FIG.  3    is a circuit diagram of one stage SR and one gate line in  FIG.  2   . Each stage SR of the gate driver  500  according to the present exemplary embodiment includes an input section  511 , a pull-up driver  512 , a transmission signal generator  513 , an output section  514 , and a pull-down driver  515 . 
     The input section  511  includes one transistor (the fourth transistor Tr 4 ). The input terminal and the control terminal of the fourth transistor Tr 4  are commonly connected (diode-connected) to the first input terminal IN 1 . The output terminal thereof is connected to a node Q (hereinafter referred to as the first node). The input section  511  has the function of transmitting the high voltage to the node Q when the first input terminal IN 1  is applied with the high voltage. 
     The pull-up driver  512  includes two transistors (the seventh transistor Tr 7  and the twelfth transistor Tr 12 . The control terminal and the input terminal of the twelfth transistor Tr 12  are diode-connected thereby receiving the first clock signal CKV or the second clock signal CKVB through the clock terminal CK, and the output terminal is connected to the control terminal of the seventh transistor Tr 7  and the pull-down driver  515 . The input terminal of the seventh transistor Tr 7  is also connected to the clock terminal CK. The output terminal is connected to the node Q′ (hereinafter referred to as the second node) and is passed through the node Q′ thereby being connected to the pull-down driver  515 . The control terminal of the seventh transistor Tr 7  is connected to the output terminal of the twelfth transistor Tr 12  and the pull-down driver  515 . Here, a parasitic capacitor (not shown) may be respectively formed between the input terminal and the control terminal, and the control terminal and the output terminal, of the seventh transistor Tr 7 . If the pull-up driver  512  is applied with the high signal at the clock terminal CK, the high signal is transmitted to the control terminal of the seventh transistor Tr 7  and the pull-down driver  515  through the twelfth transistor Tr 12 . The high signal transmitted to the seventh transistor Tr 7  turns on the seventh transistor Tr 7 , and as a result the high signal applied from the clock terminal CK is applied to the node 
     The transmission signal generator  513  includes one transistor (the fifteenth transistor Tr 15 ). The input terminal of the fifteenth transistor Tr 15  is connected to the clock terminal CK thereby receiving the first clock signal CKV or the second clock signal CKVB. The control terminal thereof is connected to the output terminal of the input section  511 , that is, the node Q. The output terminal thereof is connected to the transmission signal output terminal CRout that outputs the transmission signal CR. Here, a parasitic capacitor (not shown) may be formed between the control terminal and the output terminal. The output terminal of the fifteenth transistor Tr 15  is connected to the pull-down driver  515  as well as the transmission signal output terminal CRout, thereby receiving the second low voltage Vss 2 . As a result, the voltage value when the transmission signal CR is low is the second low voltage Vss 2 . 
     The output section  514  includes one transistor (the first transistor Tr 1 ) and one capacitor (the first capacitor C 1 ). The control terminal of the first transistor Tr 1  is connected to the node Q. The input terminal thereof receives the first clock signal CKV or the second clock signal CKVB through the clock terminal CK. The first capacitor C 1  is formed between the control terminal and the output terminal. The output terminal thereof is connected to the gate voltage output terminal OUT. Also, the output terminal is connected to the pull-down driver  515  thereby receiving the first low voltage Vss 1 . As a result, the value of the voltage of the gate-off voltage is the first low voltage Vss 1 . This output section  514  outputs the gate voltage according to the voltage of the node Q and the first clock signal CKV. 
     The pull-down driver  515  removes charges remaining at the stage SR as a portion to smoothly output the gate-off voltage and the low voltage of the transmission signal CR thereby executing functions of decreasing the potential of the node Q, the potential of the node Q′, the voltage output to the transmission signal CRout, and the voltage output to the gate line. The pull-down driver  515  includes ten transistors (the second transistor Tr 2 , the third transistor Tr 3 , the fifth transistor Tr 5 , the sixth transistor Tr 6 , the eighth transistor Tr 8  to the eleventh transistor Tr 11 , the thirteenth transistor Tr 13  and the sixteenth transistor Tr 16 ). 
     The transistors that pull down the node Q will be first described. The transistors that pull down the node Q are the sixth transistor Tr 6 , the ninth transistor Tr 9 , the tenth transistor Tr 10 , and the sixteenth transistor Tr 16 . 
     The control terminal of the sixth transistor Tr 6  is connected to the third input terminal IN 3 . The output terminal thereof is connected to the second voltage input terminal Vin 2 . The input terminal thereof is connected to the node Q. Therefore, the sixth transistor Tr 6  is turned on according to the transmission signal CR applied from the second next stage, thereby having the function of decreasing the voltage of the node Q to the second low voltage Vss 2 . 
     The ninth transistor Tr 9  and the sixteenth transistor Tr 16  are operated together thereby pulling down the node Q. The control terminal of the ninth transistor Tr 9  is connected to the second input terminal IN 2 . The input terminal thereof is connected to the node Q. The output terminal thereof is connected to the input terminal and the control terminal of the sixteenth transistor Tr 16 . The control terminal and the input terminal of the sixteenth transistor Tr 16  are diode-connected to the output terminal of the ninth transistor Tr 9 . The output terminal thereof is connected to the second voltage input terminal Vin 2 . Therefore, the ninth transistor Tr 9  and the sixteenth transistor Tr 16  are turned on according to the transmission signal CR applied from the next stage, thereby executing the function of decreasing the voltage of the node Q to the second low voltage Vss 2 . 
     The input terminal of the tenth transistor Tr 10  is connected to the node Q, the output terminal thereof is connected to the second voltage input terminal Vin 2 , and the control terminal thereof is connected to the node Q′ (which has the reverse voltage to the node Q such that it is referred to as a reverse terminal). Therefore, the tenth transistor Tr 10  has the function of continuously decreasing the voltage of the node Q to the second low voltage Vss 2  in the general period when the node Q′ has the high voltage and then not decreasing the voltage of the node Q when the voltage of the node Q′ is only the low voltage. When the voltage of the node Q is not decreased, the corresponding stage outputs the gate-on voltage and the transmission signal CR. 
     The transistors that pull down the node Q′ in the pull-down driver  515  will now be described. The transistors that pull down the node Q′ are the fifth transistor Tr 5 , the eighth transistor Tr 8 , and the thirteenth transistor Tr 13 . 
     The control terminal of the fifth transistor Tr 5  is connected to the first input terminal IN 1 , the input terminal thereof is connected to the node Q′, and the output terminal thereof is connected to the second voltage input terminal Vin 2 . As a result, the fifth transistor Tr 5  decreases the voltage of the node Q′ to the second low voltage Vss 2  according to the transmission signal CR of the previous stage. 
     The eighth transistor Tr 8  has the control terminal connected to the transmission signal output terminal CRout of the corresponding stage, the input terminal connected to the node Q′, and the output terminal connected to the second voltage input terminal Vin 2 . As a result, the eighth transistor Tr 8  functions to decrease the voltage of the node Q′ to the second low voltage Vss 2  according to the transmission signal CR of the corresponding stage. 
     The thirteenth transistor Tr 13  has the control terminal connected to the transmission signal output terminal CRout of the corresponding stage, the input terminal connected to the output terminal of the twelfth transistor Tr 12  of the pull-up driver  512 , and the output terminal connected to the second voltage input terminal Vin 2 . As a result, the thirteenth transistor Tr 13  functions to decrease the inner potential of the pull-up driver  512  to the second low voltage Vss 2  and decrease the voltage of the node Q′ connected to the pull-up driver  512  to the second low voltage Vss 2  according to the transmission signal CR of the corresponding stage. That is, the thirteenth transistor Tr 13  strictly functions to discharge the inner charges of the pull-up driver  512  to the second low voltage Vss 2 . However, the pull-up driver  512  is also connected to the node Q′ for the voltage of the node Q′ to not he pulled up such that the thirteenth transistor Tr 13  assists to decrease the voltage of the node Q′ to the second low voltage Vss 2 . 
     The transistor decreasing the voltage output to the transmission signal CRout in the pull-down driver  515  will now be described. The transistor decreasing the voltage output to the transmission signal CRout is the eleventh transistor Tr 11 . 
     The eleventh transistor Tr 11  has the control terminal connected to the node Q′, the input terminal connected to the transmission signal output terminal CRout, and the output terminal connected to the second voltage input terminal Vin 2 . As a result, when the voltage of the node is high, the voltage of the transmission signal output terminal CRout is decreased to the second low voltage Vss 2  such that the transmission signal CR is changed to the low level. 
     The transistors decreasing the voltage output to the gate line from the pull-down driver  515  will now be described. The transistors decreasing the voltage output to the gate line are the second transistor Tr 2  and the third transistor Tr 3 . 
     The second transistor Tr 2  has the control terminal connected to the second input terminal IN 2 , the input terminal connected to the gate voltage output terminal OUT, and the output terminal connected to the first voltage input terminal Vin 1 . As a result, the gate voltage output when the transmission signal CR of the next stage is output is changed to the first low voltage Vss 1 . 
     The third transistor Tr 3  has the control terminal connected to the node Q′, the input terminal connected to the gate voltage output terminal OUT and the output terminal connected to the first voltage input terminal Vin 1 . As a result, the gate voltage output when the voltage of the node Q′ is high is changed to the first low voltage Vss 1 . 
     In the pull-down driver  515 , the gate voltage output terminal OUT is only decreased to the first low voltage Vss 1 , and the node Q, the node Q′ and the transmission signal output terminal CRout are decreased to the second low voltage Vss 2  that is lower than the first low voltage Vss 1 . As a result, although the gate-on voltage and the high voltage of the transmission signal CR may have the same voltage, the gate-off voltage and the low voltage of the transmission signal CR have different voltages. That is, the gate-off voltage has the first low voltage Vss 1 , and the low voltage of the transmission signal CR has the second low voltage Vss 2 . 
     The gate voltage and transmission signal CR may have various voltage values. However, in the present exemplary embodiment, the gate-on voltage is 25V. The gate-off voltage and the first low voltage Vss 1  are −5V. The high voltage of the transmission signal CR is 25V. The low voltage and the second low voltage Vss 2  are −10V. 
     In summary, the transmission signal generator  513  and the output section  514  are operated by the voltage of the node Q such that one stage SR outputs the high voltage of the transmission signal CR and the gate-on voltage, the transmission signal CR is decreased from the high voltage to the second low voltage Vss 2  by the previous, the next, and the second next transmission signals CR, and the gate-on voltage is decreased to the first low voltage Vss 1  thereby being the gate-off voltage. Here, one stage SR decreases the voltage of the node Q to the second low voltage Vss 2  by the second next transmission signal CR as well as the next transmission signal CR to reduce the power consumption. 
     The second low voltage Vss 2  is lower than the first low voltage Vss 1  as the gate-off voltage such that the second low voltage Vss 2  is sufficiently low and the transistors included in the stage hardly flow out any leakage current. There is thereby the benefit that the power consumption is decreased although the transmission signal CR applied in the different stage includes a ripple or noise such that the voltage is changed. 
       FIG.  4    is a graph showing power consumption of the gate driver  500  according to the exemplary embodiment of  FIG.  3   . “A” depicts power consumption of the exemplary embodiment of  FIG.  3   , and “B” depicts power consumption of the conventional art. “A” is represented as a plurality of bar graphs, which means the results are measured through a plurality of exemplary embodiments, and 189 mW is average power consumption of the exemplary embodiment of  FIG.  3   . On the other hand, it is typically known that the power consumption of the gate driver according to the conventional art is 430 mW. Accordingly, the power consumption can be reduced by more than half when implementing the exemplary embodiment of the present invention. The transistors Tr 1 -Tr 13 , Tr 15 , Tr 16  formed in the stage SR may be NMOS transistors, when the transistors Tr 1 -Tr 13 , Tr 15 , Tr 16  are formed as PMOS transistors. The transistors Tr 1 -Tr 13 , Tr 15 , Tr 16  may be on when the voltage applied to the control terminal is low. 
     Next, a display device according to an exemplary embodiment of the present invention will be described with reference to  FIGS.  5  to  7   . 
       FIG.  5    is a plan view of a display device according to an exemplary embodiment of the present invention and shows an exemplary embodiment in which the data driver IC  460  is formed at the lower side of the display panel  100 , differently from that in  FIG.  1   . This does not mean that the exemplary embodiments of  FIG.  6    and  FIG.  7    is limited to the exemplary embodiment of  FIG.  5   , since the exemplary embodiments of  FIG.  6    and  FIG.  7    can be both applied to the exemplary embodiments of  FIG.  1    and  FIG.  5   , 
     Except for the data driver IC  460  being formed at the lower side of the display panel  100 ,  FIG.  5    is the same as  FIG.  1   . In the exemplary embodiment of  FIG.  1   , the data driver IC  460  is formed at the upper side of the display panel  100 . The gate driver of  FIG.  2    and  FIG.  3    and the gate driver of  FIG.  6    and  FIG.  7    may be applied to all display devices of  FIG.  1    and  FIG.  5   . 
       FIG.  6    is a block diagram showing the gate driver and the gate line of  FIG.  5    in further detail, and has the same signal characteristics as that of  FIG.  2   . That is, the signals input and output to each stage SR formed in the gate driver  500  are the same as those of  FIG.  2   . 
       FIG.  6    shows the connection relationship and the operation of the gate driver  500 , and will be described again as follows. 
     The gate driver  500  includes a plurality of stages SR 1 , SR 2 , SR 3 , SR 4 , . . . that are dependently connected to each other. Each of the stages SR 1 , SR 2 , SR 3 , SR 4 , . . . includes three input terminals IN 1 , IN 2 , IN 3 , one clock input terminal CK, two voltage input terminals Vin 1 , Vin 2 , a gate voltage output terminal OUT that outputs the gate voltage, and a transmission signal output terminal CRout. 
     The first input terminal IN 1  is connected to the transmission signal output terminal CRout of the previous stage thereby receiving the transmission signal CR of the previous stage. The first stage does not have the previous stage such that the scan start signal STVP of the first input terminal IN 1  is applied. 
     The second input terminal IN 2  is connected to the transmission signal output terminal CRout of the next stage, thereby receiving the transmission signal CR of the next stage. Also, the third input terminal IN 3  is connected to the transmission signal output terminal CRout of the second next stage, thereby receiving the transmission signal CR of the second next stage. 
     The stage SRn (not shown) connected to the nth gate line Gn may have two dummy stages to receive the transmission signal CR from the next stage and the second next stage. The dummy stages (SRn+1, SRn+2, not shown) are stages that generate and output a dummy gate voltage, differently from the stages SR 1 , SR 2 , SR 3 , SR 4 , . . . SRn. That is, the gate voltage output from the stages SR 1 , . . . SRn is transmitted though the gate line thereby the data voltage is applied to the pixel for the display of the images, however the dummy stages SRn+1, SRn+2 would not be connected to the gate lines, and even if they are connected to the gate lines, they are connected to the gate lines of dummy pixels (not shown) that do not display the image such that they would not be used for the display of the image. 
     The clock terminal CK is applied with a clock signal. Among the plurality of stages, the clock terminals CK of the odd-numbered stages are applied to the first clock signal CKV. The clock terminals CK of the even-numbered stages are applied with the second clock signal CKVB. The first clock signal CKV and the second clock signal CKVB are clock signals having opposite phases to each other. The first voltage input terminal Vin 1  is applied with the first low voltage Vss 1  corresponding to the gate-off voltage. The second voltage input terminal Vin 2  is applied with the second low voltage Vss 2  that is lower than the first low voltage Vss 1 . The voltage values of the first low voltage Vss 1  and the second low voltage Vss 2  may vary according to the exemplary embodiment. The value of the first low voltage Vss 1  is −5V and the value of the second low voltage Vss 2  is −10V in the present exemplary embodiment. 
     Next, the operation of the gate driver  500  will be described in more detail. 
     The first stage SR 1  receives the first clock signal CKV provided from outside external to the clock input terminal CK, the scan start signal STVP through the first input terminal IN 1 , the first and second low voltages Vss 1 , Vss 2  through the first and second voltage input terminals Vin 1 , Vin 2 , and the transmission signals CR respectively provided from the second stage SR 2  and the third stage SR 3  through the second and third input terminals IN 2 , IN 3  such that the gate-on voltage is output to the first gate line through the gate voltage output terminal OUT. Also, the transmission signal output terminal CRout outputs the transmission signal CR, and it is transmitted to the first input terminal IN 1  of the second stage SR 2 . 
     The second stage SR 2  receives the second clock signal CKVB provided from the outside to the clock input terminal CK, the transmission signal CR of the first stage SRI through the first input terminal IN 1 , the first and second low voltages Vss 1 , Vss 2  through the first and second voltage input terminals Vin 1 , Vin 2 , and the transmission signals CR respectively provided from the third stage SR 3  and the fourth stage SR 4  through the second and third input terminals IN 2 , IN 3  such that the gate-on voltage is output to the second gate line through the gate voltage output terminal OUT. Also, the transmission signal CR is output through the transmission signal output terminal CRout, thereby being transmitted to the first input terminal IN 1  of the third stage SR 3  and the second input terminal IN 2  of the first stage SR 1 . 
     The third stage SR 3  receives the first clock signal CKV provided from the outside to the clock input terminal CK, the transmission signal CR of the second stage SR 2  through the first input terminal IN 1 , the first and second low voltages Vss 1 , Vss 2  through the first and second voltage input terminals Vin 1 , Vin 2 , and the transmission signals CR respectively provided from the fourth stage SR 4  and the fifth stage SR 5  through the second and third input terminals IN 2 , IN 3  such that the gate-on voltage is output to the third gate line through the gate voltage output terminal OUT. Also, the transmission signal CR is output through the transmission signal output terminal CRout thereby being transmitted to the first input terminal IN 1  of the fourth stage SR 4 , the third input terminal IN 3  of the first stage SR 1 , and the second input terminal IN 2  of the second stage SR 2 . 
     Through the above method, The nth stage SRn receives the second clock signal CKVB provided from the outside to the clock input terminal CK, the transmission signal CR of the n−1-th stage SRn−1 through the first input terminal IN 1 , the first and second low voltages Vss 1 , Vss 2  through the first and the second voltage input terminals Vin 1 , Vin 2 , and the transmission signals CR respectively provided from the (n+1)-th stage SRn+1 (the dummy stage) and the (n+2)-th stage SRn+2 (the dummy stage) through the second and third input terminals IN 2 , IN 3  such that the gate-on voltage is output to the n-th gate line through the gate voltage output terminal OUT. Also, the transmission signal CR is output through the transmission signal output terminal CRout thereby being transmitted to the first input terminal IN 1  of the (n+1)-th stage SRn+1 (the dummy stage), the third input terminal IN 3  of the (n−2)-th stage SRn−2, and the second input terminal IN 2  of the n−1-th stage SRn−1. 
     The connection structure of the stages SR of the whole gate driver  500  has been described with reference to  FIG.  6   . Next, a structure of a stage SR of a gate driver connected to one gate line will be described in further detail with reference to  FIG.  7   . 
       FIG.  7    is a circuit diagram of one stage SR and one gate line in  FIG.  6   . Each stage SR of the gate driver  500  according to the present exemplary embodiment includes an input section  511 , a pull-up driver  512 , a transmission signal generator  513 , an output section  514 , and a pull-down driver  515 . 
     The input section  511  includes one transistor (the fourth transistor Tr 4 ). The input terminal and the control terminal of the fourth transistor Tr 4  are commonly connected (diode-connected) to the first input terminal IN 1 . The output terminal thereof is connected to a node Q (hereinafter referred to as the first node). The input section  511  has a function of transmitting the high voltage to the node Q when the first input terminal IN 1  is applied with the high voltage. 
     The pull-up driver  512  includes two transistors (the seventh transistor Tr 7  and the twelfth transistor Tr 12 ). The control terminal and the input terminal of the twelfth transistor Tr 12  are diode-connected thereby receiving the first clock signal CKV or the second clock signal CKVB through the clock terminal CK. The output terminal is connected to the control terminal of the seventh transistor Tr 7  and the pull-down driver  515 . The input terminal of the seventh transistor Tr 7  is also connected to the clock terminal CK. The output terminal is connected to the node Q′ (hereinafter referred to as the second node) and is passed through the node Q′ thereby being connected to the pull-down driver  515 . The control terminal of the seventh transistor Tr 7  is connected to the output terminal of the twelfth transistor Tr 12  and the pull-down driver  515 . Here, a parasitic capacitor (not shown) may be respectively formed between the input terminal and the control terminal, and the control terminal and the output terminal, of the seventh transistor Tr 7 . If the pull-up driver  512  is applied with the high signal at the clock terminal CK, and the high signal is transmitted to the control terminal of the seventh transistor Tr 7  and the pull-down driver  515  through the twelfth transistor Tr 12 . The high signal transmitted to the seventh transistor Tr 7  turns on the seventh transistor Tr 7 , and as a result the high signal applied from the clock terminal CK is applied to the node Q′. 
     The transmission signal generator  513  includes one transistor (the fifteenth transistor Tr 15 ). The input terminal of the fifteenth transistor Tr 15  is connected to the clock terminal CR thereby receiving the first clock signal CKV or the second clock signal CKVB. The control terminal thereof is connected to the output terminal of the input section  511 , that is, the node Q, and the output terminal thereof is connected to the transmission signal output terminal CRout that outputs the transmission signal CR. Here, a parasitic capacitor (not shown) may be formed between the control terminal and the output terminal. The output terminal of the fifteenth transistor Tr 15  is connected to the pull-down driver  515  as well as the transmission signal output terminal CRout, thereby receiving the second low voltage Vss 2 . As a result, the voltage value when the transmission signal CR is low is the second low voltage Vss 2 . 
     The output section  514  includes one transistor (the first transistor Tr 1 ) and one capacitor (the first capacitor C 1 ). The control terminal of the first transistor Tr 1  is connected to the node Q, the input terminal thereof receives the first clock signal CKV or the second clock signal CKVB through the clock terminal CK, the first capacitor C 1  is formed between the control terminal and the output terminal, and the output terminal thereof is connected to the gate voltage output terminal OUT. Also, the output terminal is connected to the pull-down driver  515  thereby receiving the first low voltage Vss 1 . As a result, the value of the voltage of the gate-off voltage is the first low voltage Vss 1 . This output section  514  outputs the gate voltage according to the voltage of the node Q and the first clock signal CKV. 
     The pull-down driver  515  removes charges remaining at the stage SR as the portion to smoothly output the gate-off voltage and the low voltage of the transmission signal CR thereby executing functions of decreasing the potential of the node Q, the potential of the node Q′, the voltage output to the transmission signal CRout, and the voltage output to the gate line. The pull-down driver  515  includes eleven transistors (the second transistor Tr 2 , the third transistor Tr 1 , the fifth transistor Tr 5 , the sixth transistor Tr 6 , the eighth transistor Tr 8  to the eleventh transistor Tr 11 , the thirteenth transistor Tr 13 , the sixteenth transistor Tr 16 , and the seventeenth transistor Tr 17 ). 
     First, the transistors that pull down the node Q will be described. The transistors that pull down the node Q are the sixth transistor Tr 6 , the ninth transistor Tr 9 , the tenth transistor Tr 10 , and the sixteenth transistor Tr 16 . 
     The control terminal of the sixth transistor Tr 6  is connected to the third input terminal IN 3 . The output terminal thereof is connected to the second voltage input terminal Vin 2 . The input terminal thereof is connected to the node Q. Therefore, the sixth transistor Tr 6  is turned on according to the transmission signal CR applied from the second next stage, thereby having the function of decreasing the voltage of the node Q to the second low voltage Vss 2 . 
     The ninth transistor Tr 9  and the sixteenth transistor Tr 16  are operated together thereby pulling down the node Q. The control terminal of the ninth transistor Tr 9  is connected to the second input terminal IN 2 . The input terminal thereof is connected to the node Q. The output terminal thereof is connected to the input terminal and the control terminal of the sixteenth transistor Tr 16 . The control terminal and the input terminal of the sixteenth transistor Tr 16  are diode-connected to the output terminal of the ninth transistor Tr 9 . The output terminal thereof is connected to the second voltage input terminal Vin 2 . Therefore, the ninth transistor Tr 9  and the sixteenth transistor Tr 16  are turned on according to the transmission signal CR applied from the next stage, thereby executing the function of decreasing the voltage of the node Q to the second low voltage Vss 2 . 
     The input terminal of the tenth transistor Tr 10  is connected to the node Q. The output terminal thereof is connected to the second voltage input terminal Vin 2 . The control terminal thereof is connected to the node Q′ (that has the reverse voltage to the node Q such that it is referred to as a reverse terminal). Therefore, the tenth transistor Tr 10  has the function of continuously decreasing the voltage of the node Q to the second low voltage Vss 2  in the general period that the node Q′ has the high voltage and then not decreasing the voltage of the node Q when the voltage of the node Q′ is only the low voltage. When the voltage of the node Q is not decreased, the corresponding stage outputs the gate-on voltage and the transmission signal CR. 
     The transistor that pulls-down the node Q′ in the pull-down driver  515  will now be described. The transistors that pull down the node Q′ are the fifth transistor Tr 5 , the eighth transistor Tr 8 , and the thirteenth transistor Tr 13 . 
     The control terminal of the fifth transistor Tr 5  is connected to the first input terminal IN 1 . The input terminal thereof is connected to the node Q′. The output terminal thereof is connected to the second voltage input terminal Vin 2 . As a result, the fifth transistor Tr 5  decreases the voltage of the node Q′ to the second low voltage Vss 2  according to the transmission signal CR of the previous stage. 
     The eighth transistor Tr 8  has the control terminal connected to the transmission signal output terminal CRout of the corresponding stage, the input terminal connected to the node Q′. and the output terminal connected to the first voltage input terminal Vin 1 . As a result, the eighth transistor Tr 8  functions to decrease the voltage of the node Q′ to the first low voltage Vss 1  according to the transmission signal CR of the corresponding stage. 
     The thirteenth transistor Tr 13  has the control terminal connected to the transmission signal output terminal CRout of the corresponding stage, the input terminal connected to the output terminal of the twelfth transistor Tr 12  of the pull-up driver  512 , and the output terminal connected to the first voltage input terminal Vin 1 . As a result, the thirteenth transistor Tr 13  functions to decrease the inner potential of the pull-up driver  512  to the first low voltage Vss 1  and to decrease the voltage of the node Q′ connected to the pull-up driver  512  to the first low voltage Vss 1  according to the transmission signal CR of the corresponding stage. That is, the thirteenth transistor Tr 13  strictly functions to discharge the inner charges of the pull-up driver  512  to the first low voltage Vss 1 . However, the pull-up driver  512  is also connected to the node Q′ for the voltage of the node Q′ to not be pulled up such that the thirteenth transistor Tr 13  assists to decrease the voltage of the node Q′ to the first low voltage Vss 1 . Different from the exemplary embodiment of  FIG.  3   , the eighth transistor Tr 8  and the thirteenth transistor Tr 13  are connected to the first voltage input terminal Vin 1  applied with the first low voltage Vss 1  in the exemplary embodiment of  FIG.  7   . 
     The transistors decreasing the voltage output to the transmission signal CRout in the pull-down driver  515  will now be described. The transistors decreasing the voltage output to the transmission signal CRout are the eleventh transistor Tr 11  and the seventeenth transistor Tr 17 . 
     The eleventh transistor Tr 11  has the control terminal connected to the node Q′, the input terminal connected to the transmission signal output terminal CRout, and the output terminal connected to the second voltage input terminal Vin 2 . As a result, when the voltage of the node Q′ is high, the voltage of the transmission signal output terminal CRout is decreased to the second low voltage Vss 2 , and as a result the transmission signal CR is changed to the low level. 
     The seventeenth transistor Tr 17  that is not included in the exemplary embodiment of  FIG.  3    has the control terminal connected to the second input terminal IN 2 , the input terminal connected to the transmission signal output terminal CRout, and the output terminal connected to the second voltage input terminal Vin 2 . As a result, it has the function of decreasing the voltage of the transmission signal output terminal CRout to the second low voltage Vss 2  according to the transmission signal CR of the next stage. To assist the operation of the eleventh transistor Tr 11 , the seventeenth transistor Tr 17  is operated based upon the transmission signal CR of the next stage. The transistors decreasing the voltage output to the gate line from the pull-down driver  515  will now be described. The transistors decreasing the voltage output to the gate line are the second transistor Tr 2  and the third transistor Tr 3 . 
     The second transistor Tr 2  has the control terminal connected to the second input terminal IN 2 , the input terminal connected to the gate voltage output terminal OUT, and the output terminal connected to the first voltage input terminal Vin 1 . As a result, the gate voltage output when the transmission signal CR of the next stage is output is changed to the first low voltage Vss 1 . 
     The third transistor Tr 3  has the control terminal connected to the node Q′, the input terminal connected to the gate voltage output terminal OUT, and the output terminal connected to the first voltage input, terminal Vin 1 . As a result, the gate voltage output when the voltage of the node Q′ is high is changed to the first low voltage Vss 1 . 
     In pull-down driver  515 , the operation of decreasing the voltage output to the transmission signal CRout and the operation of decreasing the voltage output to the gate line are executed through two transistors, and they are connected to the second input terminal IN 2  such that they are operated according to the transmission signal CR of the next stage or the voltage of the node Q′, thereby may be operated with the same timing. However, the voltage output to the transmission signal CRout is decreased to the second low voltage Vss 2 , and the gate-off voltage is decreased to the first low voltage Vss 1  such that the voltage when the transmission signal CR is low is lower than the gate-off voltage. 
     In the pull-down driver  515 , the gate voltage output terminal OUT is only decreased to the first low voltage Vss 1 , and the node Q and the transmission signal output terminal CRout are decreased to the second low voltage Vss 2  that is lower than the first low voltage Vss 1 . As a result, although the gate-on voltage and the high voltage of the transmission signal CR may by the same voltage, the gate-off voltage and the low voltage of the transmission signal CR are different voltages. That is, the gate-off voltage is the first low voltage Vss 1 , and the low voltage of the transmission signal CR is the second low voltage Vss 2 . On the other hand, the node Q′ is decreased to the first low voltage Vss 1  by the eighth transistor Tr 8  and the thirteenth transistor Tr 13 , and to the second low voltage Vss 2  by the fifth transistor Tr 5 . 
     The gate voltage and transmission signal CR may have the various voltage values, however in the present exemplary embodiment, the gate-on voltage is 25V, the gate-off voltage and the first low voltage Vss 1  are −5V, the high voltage of the transmission signal CR is 25V, and the low voltage and the second low voltage Vss 2  are −10V. 
     In summary, the transmission signal generator  513  and the output section  514  are operated by the voltage of the node Q such that one stage SR outputs the high voltage of the transmission signal CR and the gate-on voltage. The transmission signal CR is decreased from the high voltage to the second low voltage Vss 2  by the previous, the next, and the second next transmission signal CR, and the gate-on voltage is decreased to the first low voltage Vss 1  thereby being the gate-off voltage. Here, one stage SR decreases the voltage of the node Q to the second low voltage Vss 2  by the second next transmission signal CR as well as the next transmission signal CR to reduce the power consumption. 
     The second low voltage Vss 2  is lower than the first low voltage Vss 1  as the gate-off voltage such that the second low voltage Vss 2  is sufficiently low such that the transistors included in the stage hardly flow out any leakage current such that there is the benefit that the power consumption is decreased although the transmission signal CR applied in the different stage includes a ripple or noise and the voltage is changed. 
       FIG.  8    is a graph showing power consumption of the gate driver  500  according to the exemplary embodiment of  FIG.  7   . “A′” depicts power consumption of the exemplary embodiment of  FIG.  7   , and “B” is power consumption of the conventional art. “A′” is represented as a plurality of bar graphs, which means the results are measured through a plurality of exemplary embodiments, and 183.5 mW is an average power consumption of the exemplary embodiment of  FIG.  7   . On the other hand, it is typically known that the power consumption of the gate driver according to the conventional art is 430 mW. Accordingly, the power consumption can be reduced by more than half in accordance with the exemplary embodiment of the present invention. 
     As compared with  FIG.  4   , the average power consumption of the exemplary embodiment of  FIG.  7    is 183.5 mW wherein the average power consumption is less than that of the exemplary embodiment of  FIG.  3    whose average power consumption is 189 mW. The transmission signal output terminal CRout is changed to the low voltage at the same timing as the gate voltage output terminal Out by adding the seventeenth transistor Tr 17  such that the leakage current may be further reduced inside the circuit. The transistors Tr 1 -Tr 13 , and Tr 15  to Tr 17  formed in the stage SR may be NMOS transistors. When the transistors Tr 1 -Tr 13 , and Tr 15  to Tr 17  are formed as PMOS transistors, the transistors Tr 1 -Tr 13 , and Tr 15  to Tr 17  may be on when the voltage applied to the control terminal is low. 
     As described above, the exemplary embodiment of  FIG.  3    may be applied to both the exemplary embodiments (the case that the data driver is disposed at the upper side of the panel) of  FIG.  1    and the exemplary embodiment (the case that the data driver is disposed at the lower side of the panel) of  FIG.  5   , and the exemplary embodiment of  FIG.  7    may be applied to both the exemplary embodiment of  FIG.  1    and the exemplary embodiment of  FIG.  5   . However, in the structure of the exemplary embodiment of  FIG.  5   , the first clock signal (CKV), the second clock signal (CKVB), the scan start signal (STVP), the first low voltage Vss 1 , and the second low voltage Vss 2  applied according to the flexible printed circuit film FPC are moved from the lower side to the upper side. The gate-on voltage is applied from the first gate line G 1  disposed at the upper side such that noise may be generated when the display panel is used for a long time at a high temperature. When respectively using the exemplary embodiment of  FIG.  3    and the exemplary embodiment of  FIG.  5   , noise may be generated relatively more at the high temperature in the exemplary embodiment of  FIG.  3    as compared with the exemplary embodiment of  FIG.  5   . This is the reason that the transmission signal CR is not again changed to the second low voltage Vss 2  like the seventeenth transistor Tr 17  such that the possibility of the generation of the ripple is high in the transmission signal CR. However, the possibility of the generation of noise at the high temperature in the exemplary embodiment of  FIG.  3    is remarkably low as compared with the conventional gate driver. 
     Next, power consumption, a high temperature characteristic, a low temperature characteristic, and a lifespan will be described focusing on the exemplary embodiment of  FIG.  7    as compared with the conventional art. 
       FIG.  9    is a graph showing current flow in the first transistor that outputs a gate voltage in a gate driver according to the conventional art with reference to a clock signal CKV voltage.  FIG.  10    is a graph showing current flow in the first transistor that outputs a gate voltage in a gate driver according to the exemplary embodiment of  FIG.  7    with reference to a clock signal CKV voltage. 
     As shown in  FIG.  9   , the current of the first transistor Tr 1  of the gate driver according to the conventional art varies to a lower limit of about −45 μA in correspondence with a varying clock signal CKV. However, the current of the first transistor Tr 1  of the gate driver of  FIG.  7    as shown in  FIG.  10    varies to a lower limit of about −15 μA. As a result, the current used at each stage SR is considerably smaller in the exemplary embodiment according to the present invention, and as a result the power consumption can be reduced by more than half. The reduction of power consumption by more than half is shown through  FIGS.  4  and  8   . 
     Next, the high temperature characteristics, the low temperature characteristics, and the lifespan characteristics will be described. 
       FIG.  11    is a graph showing characteristics at high temperature of the gate driver according to the conventional art and according to the exemplary embodiment of  FIG.  7   . The horizontal axis represents a normalization value of a voltage* a temperature, and the vertical axis represents a noise ratio, In  FIG.  11   , a value α is the reference available as the gate driver. 
     As shown in  FIG.  11   , there is no noise for the general reference of the value a in the conventional art and the exemplary embodiment according to the present invention. However, if the values of the high temperature and the voltage used for the gate driver according to the conventional art are slightly over the reference α, the noise is steeply increased, In contrast, the gate driver according to  FIG.  7    still does not include the noise in the predetermined range. The exemplary embodiment of  FIG.  3    has the characteristics corresponding to the exemplary embodiment of  FIG.  7   . Therefore, the gate driver according to the present invention can improve the high temperature characteristics. 
       FIG.  12    is a graph comparing the low temperature characteristics of e gate drivers of the conventional art and of the exemplary embodiment of  FIG.  7   . 
     In  FIG.  12   , the horizontal axis represents temperature and the vertical axis represents a margin of the gate-on voltage Von. That is, it is shown that the gate driver is not operated at the voltage below the position represented in the graph. 
     As shown in  FIG.  12   , the conventional gate driver and the gate driver of  FIG.  7    have the same margin of the gate-on voltage Von at room temperature. However, a difference of the margins of the gate-on voltage Von is generated further closer to the low temperature and driving only by the low voltage is possible at the low temperature in the exemplary embodiment of  FIG.  7   . However, a relatively high voltage must be applied for the driving of the conventional gate driver. The exemplary embodiment of  FIG.  3    has the characteristics corresponding to the exemplary embodiment of  FIG.  7   . Therefore, the gate driver according to the present invention may improve the low temperature characteristics as compared with the conventional art. 
       FIG.  13    is a graph comparing the lifespan characteristics of the gate drivers of the conventional art and of the exemplary embodiment of  FIG.  7   . The horizontal axis represents an aging time and the vertical axis represents a margin of the gate-on voltage Von. In  FIG.  13   , a Von setting value represents a voltage setting value that is generally used in the gate driver. If the voltage of the graph is higher than the Von setting value, the gate driver can not be operated by the general applied voltage, and as a result the lifespan of the gate driver is over. 
     In an experiment to obtain the graph of  FIG.  13   , a higher voltage (of about 130%) than the general voltage is applied to the gate driver to easily finish the lifespan, and the experiment is executed at a high temperature. As a result, experimental results of a long time can be obtained in short time. 
     In  FIG.  13   , the gate-on voltages Von of the conventional gate driver and the gate driver of the exemplary embodiment of  FIG.  7    are both increased toward the Von setting value as time passes. However, the gate driver according to the conventional art after the passage of the time has a high value such that it may be predicted that the lifespan is finished quickly. Particularly, compared with the setting values after the passage of 200 hours in  FIG.  13   , although the setting value of the exemplary embodiment of  FIG.  7    is low, a large difference of about 10% is generated. As a result, the lifespan is remarkably increased as compared with the gate driver according to the conventional art. 
     Although not shown in  FIG.  13   , the gate driver of  FIG.  3    and  FIG.  7    according to the exemplary embodiments of the present invention passes the lifespan test at more than 5000 hours. 
     While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to also cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.