Patent Publication Number: US-2023153604-A1

Title: Performing simulations using machine learning

Description:
CLAIM OF PRIORITY 
     This application claims the benefit of U.S. Provisional Application No. 63/278,947 (Attorney Docket No. NVIDP1343+/21-SC-2166U501) titled “PHYSICS INFORMED RECURRENT DCT NETWORK FOR TIME-DEPENDENT PARTIAL DIFFERENTIAL EQUATIONS,” filed Nov. 12, 2021, the entire contents of which is incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to physical systems modelling, and more particularly to modelling complex physical systems utilizing a machine learning environment. 
     BACKGROUND 
     The modelling of physical systems through simulations (such as numerical simulations, physics simulations, etc.) has enabled significant advancements in engineering and scientific discovery. However, as the complexity of these simulations increases, so does a required amount of computational hardware resources, power, and time to implement them. 
     To help address this, machine learning has been applied to the domain of physical system modelling by approximating traditional simulations with faster, less resource-intensive machine learning implementations. However, current machine learning approaches can only address physical systems with low dimensionality and time-independent physics, and systems with high dimensionality and time dependence still require traditional (non-ML) simulations. 
     There is therefore a need to improve the computational abilities of machine learning implementations so that they may solve complex (e.g., high-dimensionality, time-dependent) computation problems instead of using traditional simulations. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    illustrates a flowchart of a method for performing simulations using machine learning, in accordance with an embodiment. 
         FIG.  2    illustrates a parallel processing unit, in accordance with an embodiment. 
         FIG.  3 A  illustrates a general processing cluster within the parallel processing unit of  FIG.  2   , in accordance with an embodiment. 
         FIG.  3 B  illustrates a memory partition unit of the parallel processing unit of  FIG.  2   , in accordance with an embodiment. 
         FIG.  4 A  illustrates the streaming multi-processor of  FIG.  3 A , in accordance with an embodiment. 
         FIG.  4 B  is a conceptual diagram of a processing system implemented using the PPU of  FIG.  2   , in accordance with an embodiment. 
         FIG.  4 C  illustrates an exemplary system in which the various architecture and/or functionality of the various previous embodiments may be implemented. 
         FIG.  5    illustrates an exemplary simulation solution environment, in accordance with an embodiment. 
         FIG.  6    illustrates an exemplary machine learning environment, in accordance with an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     To assist a machine learning environment in modelling a complex physical simulation (such as a numerical simulation or physics simulation), a correlation between input coordinates is determined. For example, a discrete solution (e.g., the correlation between the plurality of input coordinates) may be obtained from a non-discrete (e.g., continuous) physics space by performing a conversion from the physics space to a grid space. This correlation is input along with the coordinates into a machine learning environment to obtain results from the simulation. As a result, instead of implementing resource and power-intensive simulations to solve these computation problems, a machine learning environment implemented using less power and computing resources may solve these computation problems in a faster and more efficient manner. 
       FIG.  1    illustrates a flowchart of a method  100  for performing simulations using machine learning, in accordance with an embodiment. Although method  100  is described in the context of a processing unit, the method  100  may also be performed by a program, custom circuitry, or by a combination of custom circuitry and a program. For example, the method  100  may be executed by a GPU (graphics processing unit), CPU (central processing unit), or any processing element. Furthermore, persons of ordinary skill in the art will understand that any system that performs method  100  is within the scope and spirit of embodiments of the present invention. 
     As shown in operation  102 , a correlation between a plurality of input coordinates is determined. In one embodiment, the plurality of input coordinates may be associated with a simulation. For example, the plurality of input coordinates may include position information within the simulation (e.g., a physics simulation, etc.). In another example, the plurality of input coordinates may be two-dimensional. For instance, the plurality of input coordinates may include an X value indicative of a first dimension, a Y value indicative of a second dimension different from the first dimension, etc. In another embodiment, a physics simulation may include a mathematical model having variables that define a state of a system at a predetermined time, where each variable within the model represents a position or velocity of some part of the system. 
     Additionally, in one embodiment, the correlation may be determined by querying the input coordinates within a physics space. For example, the physics space may include a multi-resolution latent context grid. In another embodiment, the correlation may be determined by performing interpolation within the physics space. For example, queried points (e.g., the input coordinates) are interpolated from neighboring points within the multi-resolution latent context grid. In this way, a discrete solution (e.g., the correlation and the plurality of input coordinates) may be obtained from a non-discrete (e.g., continuous) physics space by performing a conversion from the physics space to a grid space. In another example, the correlation may include an interpolated context vector. 
     Further, in one embodiment, the physics space may be created utilizing a machine learning environment. For example, the machine learning environment may include a first machine learning environment that performs latent context generation. In another example, the first machine learning environment may be different from a second machine learning environment that takes the correlation and input coordinates as input and outputs a result. 
     Further still, in one embodiment, the machine learning environment may take an initial condition (IC) and a boundary condition (BC) as inputs. For example, the initial condition may include a first timestep (at time t=0). In another example, the initial condition may include a first state at the first timestep (t=0). In yet another example, the boundary condition may include boundary areas within a predetermined space (e.g., in x, y coordinates). 
     Also, in one embodiment, the machine learning environment may include a latent grid network. In another embodiment, the latent grid network may perform one or more operations in a spatial domain, and one or more operations in a frequency domain. In yet another embodiment, within the spatial domain, the machine learning environment may perform recurrent neural network (RNN) propagation on a single initial condition input to create additional states. For example, the initial condition may be input into a convolutional gated recurrent unit (GRU). In another example, the GRU may create one or more states at subsequent timesteps (e.g., a second timestep at time t=1, a third timestep at time t=2, etc.). 
     In addition, in one embodiment, within the spatial domain, a linear transformation may be performed on these additional states, utilizing the boundary condition. For example, additional variables (e.g., W and B variables) may be created from the boundary condition input utilizing convolutional layers of the machine learning environment. In another example, the boundary condition input may be transformed into the additional variables, utilizing the machine learning environment. In yet another example, these variables may be used to perform a linear transformation on each of the additional states. In still another embodiment, this linear transformation may bound each of the additional initial conditions to fit within the boundary condition. 
     Furthermore, in one embodiment, the spatial domain results may include IC and BC values for each of a plurality of timesteps. In another embodiment, within the frequency domain, the machine learning environment may transform IC and BC input utilizing a discrete cosine transform (DCT). For example, the DCT may convert the IC and BC input from the spatial domain to the frequency domain. In another example, both the IC and BC input may be divided into patches (e.g., spatial patches). In yet another embodiment, a DCT may be applied to these patches to obtain DCT patches. In yet another example, the DCT patches may be reordered and truncated to remove redundant/unnecessary patches. In still another example, the transformed input may include the reordered/truncated DCT patches. 
     Further still, in one embodiment, within the frequency domain, recurrent neural network (RNN) propagation may be performed on the transformed input to create additional states, and a linear transformation may be performed on these additional states, utilizing the transformed boundary condition. For example, the RNN propagation may be the same as that performed within the spatial domain. In another embodiment, an inverse discrete cosine transform (IDCT) may be applied to the results of the RNN propagation. This transform may convert the results from the frequency domain back to the spatial domain. 
     Also, in one embodiment, the frequency domain results may include IC and BC values for each of a plurality of timesteps. In another embodiment, the spatial domain results and the frequency domain results may then be combined. In yet another embodiment, additional layers of the machine learning environment (e.g., convoluted neural network (CNN) layers, etc.) may decode the combined domain results. In still another embodiment, results of the decoding may be upsampled by additional layers of the machine learning environment to determine the physics space (e.g., the multi-resolution latent context grid). For example, the upsampling may be performed over multiple stages to create the multiple resolutions for the multi-resolution latent context grid. 
     Additionally, as shown in operation  104 , the plurality of input coordinates as well as the correlation are input into a machine learning environment to obtain a result. In one embodiment, the plurality of input coordinates and the correlation may be input into a trained machine learning environment (e.g., a neural network, etc.). In another embodiment, the machine learning environment may be trained utilizing one or more physics model loss functions. 
     For example, the loss functions may be constructed based on a predetermined physics model. In another example, the loss functions may be minimized based on partial differential equations (PDEs), ICs, and BCs. In yet another example, weights within the machine learning environment may be learned utilizing the one or more physics model loss functions. 
     Further, in one embodiment, the trained machine learning environment may take the plurality of input coordinates and the correlation as input and may output a solution as the result. For example, the solution may include one or more values (e.g., pressure, velocity, temperature, etc.) indicated within the physics model being implemented via the machine learning environment. 
     In this way, results may be determined for complex computation problems (e.g., multi-variable time-dependent physics problems, etc.) using a machine learning environment instead of one or more complex hardware-implemented simulations. Determining the correlation between the input coordinates (e.g., according to time, etc.) may allow for knowledge about dimensionality and interrelationships between the input coordinates to be considered as input by the machine learning environment, which may simplify the analysis being performed by the machine learning environment, thereby enabling the machine learning environment to understand and solve complex computation problems. As a result, instead of implementing resource and power-intensive simulations to solve these computation problems, a machine learning environment implemented using less power and computing resources may solve these computation problems in a faster and more efficient manner, which may improve a performance of computing hardware tasked with solving such computation problems. 
     In yet another embodiment, the aforementioned operations may be performed utilizing a parallel processing unit (PPU) such as the PPU  200  illustrated in  FIG.  2   . 
     More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing framework may be implemented, per the desires of the user. It should be strongly noted that the following information is set forth for illustrative purposes and should not be construed as limiting in any manner. Any of the following features may be optionally incorporated with or without the exclusion of other features described. 
     Parallel Processing Architecture 
       FIG.  2    illustrates a parallel processing unit (PPU)  200 , in accordance with an embodiment. In an embodiment, the PPU  200  is a multi-threaded processor that is implemented on one or more integrated circuit devices. The PPU  200  is a latency hiding architecture designed to process many threads in parallel. A thread (i.e., a thread of execution) is an instantiation of a set of instructions configured to be executed by the PPU  200 . In an embodiment, the PPU  200  is a graphics processing unit (GPU) configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data in order to generate two-dimensional (2D) image data for display on a display device such as a liquid crystal display (LCD) device. In other embodiments, the PPU  200  may be utilized for performing general-purpose computations. While one exemplary parallel processor is provided herein for illustrative purposes, it should be strongly noted that such processor is set forth for illustrative purposes only, and that any processor may be employed to supplement and/or substitute for the same. 
     One or more PPUs  200  may be configured to accelerate thousands of High Performance Computing (HPC), data center, and machine learning applications. The PPU  200  may be configured to accelerate numerous deep learning systems and applications including autonomous vehicle platforms, deep learning, high-accuracy speech, image, and text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimizations, and personalized user recommendations, and the like. 
     As shown in  FIG.  2   , the PPU  200  includes an Input/Output (I/O) unit  205 , a front end unit  215 , a scheduler unit  220 , a work distribution unit  225 , a hub  230 , a crossbar (Xbar)  270 , one or more general processing clusters (GPCs)  250 , and one or more partition units  280 . The PPU  200  may be connected to a host processor or other PPUs  200  via one or more high-speed NVLink  210  interconnect. The PPU  200  may be connected to a host processor or other peripheral devices via an interconnect  202 . The PPU  200  may also be connected to a local memory comprising a number of memory devices  204 . In an embodiment, the local memory may comprise a number of dynamic random access memory (DRAM) devices. The DRAM devices may be configured as a high-bandwidth memory (HBM) subsystem, with multiple DRAM dies stacked within each device. 
     The NVLink  210  interconnect enables systems to scale and include one or more PPUs  200  combined with one or more CPUs, supports cache coherence between the PPUs  200  and CPUs, and CPU mastering. Data and/or commands may be transmitted by the NVLink  210  through the hub  230  to/from other units of the PPU  200  such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). The NVLink  210  is described in more detail in conjunction with  FIG.  4 B . 
     The I/O unit  205  is configured to transmit and receive communications (i.e., commands, data, etc.) from a host processor (not shown) over the interconnect  202 . The I/O unit  205  may communicate with the host processor directly via the interconnect  202  or through one or more intermediate devices such as a memory bridge. In an embodiment, the I/O unit  205  may communicate with one or more other processors, such as one or more the PPUs  200  via the interconnect  202 . In an embodiment, the I/O unit  205  implements a Peripheral Component Interconnect Express (PCIe) interface for communications over a PCIe bus and the interconnect  202  is a PCIe bus. In alternative embodiments, the I/O unit  205  may implement other types of well-known interfaces for communicating with external devices. 
     The I/O unit  205  decodes packets received via the interconnect  202 . In an embodiment, the packets represent commands configured to cause the PPU  200  to perform various operations. The I/O unit  205  transmits the decoded commands to various other units of the PPU  200  as the commands may specify. For example, some commands may be transmitted to the front end unit  215 . Other commands may be transmitted to the hub  230  or other units of the PPU  200  such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). In other words, the I/O unit  205  is configured to route communications between and among the various logical units of the PPU  200 . 
     In an embodiment, a program executed by the host processor encodes a command stream in a buffer that provides workloads to the PPU  200  for processing. A workload may comprise several instructions and data to be processed by those instructions. The buffer is a region in a memory that is accessible (i.e., read/write) by both the host processor and the PPU  200 . For example, the I/O unit  205  may be configured to access the buffer in a system memory connected to the interconnect  202  via memory requests transmitted over the interconnect  202 . In an embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU  200 . The front end unit  215  receives pointers to one or more command streams. The front end unit  215  manages the one or more streams, reading commands from the streams and forwarding commands to the various units of the PPU  200 . 
     The front end unit  215  is coupled to a scheduler unit  220  that configures the various GPCs  250  to process tasks defined by the one or more streams. The scheduler unit  220  is configured to track state information related to the various tasks managed by the scheduler unit  220 . The state may indicate which GPC  250  a task is assigned to, whether the task is active or inactive, a priority level associated with the task, and so forth. The scheduler unit  220  manages the execution of a plurality of tasks on the one or more GPCs  250 . 
     The scheduler unit  220  is coupled to a work distribution unit  225  that is configured to dispatch tasks for execution on the GPCs  250 . The work distribution unit  225  may track a number of scheduled tasks received from the scheduler unit  220 . In an embodiment, the work distribution unit  225  manages a pending task pool and an active task pool for each of the GPCs  250 . The pending task pool may comprise a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular GPC  250 . The active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by the GPCs  250 . As a GPC  250  finishes the execution of a task, that task is evicted from the active task pool for the GPC  250  and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC  250 . If an active task has been idle on the GPC  250 , such as while waiting for a data dependency to be resolved, then the active task may be evicted from the GPC  250  and returned to the pending task pool while another task in the pending task pool is selected and scheduled for execution on the GPC  250 . 
     The work distribution unit  225  communicates with the one or more GPCs  250  via XBar  270 . The XBar  270  is an interconnect network that couples many of the units of the PPU  200  to other units of the PPU  200 . For example, the XBar  270  may be configured to couple the work distribution unit  225  to a particular GPC  250 . Although not shown explicitly, one or more other units of the PPU  200  may also be connected to the XBar  270  via the hub  230 . 
     The tasks are managed by the scheduler unit  220  and dispatched to a GPC  250  by the work distribution unit  225 . The GPC  250  is configured to process the task and generate results. The results may be consumed by other tasks within the GPC  250 , routed to a different GPC  250  via the XBar  270 , or stored in the memory  204 . The results can be written to the memory  204  via the partition units  280 , which implement a memory interface for reading and writing data to/from the memory  204 . The results can be transmitted to another PPU  200  or CPU via the NVLink  210 . In an embodiment, the PPU  200  includes a number U of partition units  280  that is equal to the number of separate and distinct memory devices  204  coupled to the PPU  200 . A partition unit  280  will be described in more detail below in conjunction with  FIG.  3 B . 
     In an embodiment, a host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU  200 . In an embodiment, multiple compute applications are simultaneously executed by the PPU  200  and the PPU  200  provides isolation, quality of service (QoS), and independent address spaces for the multiple compute applications. An application may generate instructions (i.e., API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU  200 . The driver kernel outputs tasks to one or more streams being processed by the PPU  200 . Each task may comprise one or more groups of related threads, referred to herein as a warp. In an embodiment, a warp comprises 32 related threads that may be executed in parallel. Cooperating threads may refer to a plurality of threads including instructions to perform the task and that may exchange data through shared memory. Threads and cooperating threads are described in more detail in conjunction with  FIG.  4 A . 
       FIG.  3 A  illustrates a GPC  250  of the PPU  200  of  FIG.  2   , in accordance with an embodiment. As shown in  FIG.  3 A , each GPC  250  includes a number of hardware units for processing tasks. In an embodiment, each GPC  250  includes a pipeline manager  310 , a pre-raster operations unit (PROP)  315 , a raster engine  325 , a work distribution crossbar (WDX)  380 , a memory management unit (MMU)  390 , and one or more Data Processing Clusters (DPCs)  320 . It will be appreciated that the GPC  250  of  FIG.  3 A  may include other hardware units in lieu of or in addition to the units shown in  FIG.  3 A . 
     In an embodiment, the operation of the GPC  250  is controlled by the pipeline manager  310 . The pipeline manager  310  manages the configuration of the one or more DPCs  320  for processing tasks allocated to the GPC  250 . In an embodiment, the pipeline manager  310  may configure at least one of the one or more DPCs  320  to implement at least a portion of a graphics rendering pipeline. For example, a DPC  320  may be configured to execute a vertex shader program on the programmable streaming multiprocessor (SM)  340 . The pipeline manager  310  may also be configured to route packets received from the work distribution unit  225  to the appropriate logical units within the GPC  250 . For example, some packets may be routed to fixed function hardware units in the PROP  315  and/or raster engine  325  while other packets may be routed to the DPCs  320  for processing by the primitive engine  335  or the SM  340 . In an embodiment, the pipeline manager  310  may configure at least one of the one or more DPCs  320  to implement a neural network model and/or a computing pipeline. 
     The PROP unit  315  is configured to route data generated by the raster engine  325  and the DPCs  320  to a Raster Operations (ROP) unit, described in more detail in conjunction with  FIG.  3 B . The PROP unit  315  may also be configured to perform optimizations for color blending, organize pixel data, perform address translations, and the like. 
     The raster engine  325  includes a number of fixed function hardware units configured to perform various raster operations. In an embodiment, the raster engine  325  includes a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, and a tile coalescing engine. The setup engine receives transformed vertices and generates plane equations associated with the geometric primitive defined by the vertices. The plane equations are transmitted to the coarse raster engine to generate coverage information (e.g., an x,y coverage mask for a tile) for the primitive. The output of the coarse raster engine is transmitted to the culling engine where fragments associated with the primitive that fail a z-test are culled, and transmitted to a clipping engine where fragments lying outside a viewing frustum are clipped. Those fragments that survive clipping and culling may be passed to the fine raster engine to generate attributes for the pixel fragments based on the plane equations generated by the setup engine. The output of the raster engine  325  comprises fragments to be processed, for example, by a fragment shader implemented within a DPC  320 . 
     Each DPC  320  included in the GPC  250  includes an M-Pipe Controller (MPC)  330 , a primitive engine  335 , and one or more SMs  340 . The MPC  330  controls the operation of the DPC  320 , routing packets received from the pipeline manager  310  to the appropriate units in the DPC  320 . For example, packets associated with a vertex may be routed to the primitive engine  335 , which is configured to fetch vertex attributes associated with the vertex from the memory  204 . In contrast, packets associated with a shader program may be transmitted to the SM  340 . 
     The SM  340  comprises a programmable streaming processor that is configured to process tasks represented by a number of threads. Each SM  340  is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently. In an embodiment, the SM  340  implements a SIMD (Single-Instruction, Multiple-Data) architecture where each thread in a group of threads (i.e., a warp) is configured to process a different set of data based on the same set of instructions. All threads in the group of threads execute the same instructions. In another embodiment, the SM  340  implements a SIMT (Single-Instruction, Multiple Thread) architecture where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but where individual threads in the group of threads are allowed to diverge during execution. In an embodiment, a program counter, call stack, and execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within the warp diverge. In another embodiment, a program counter, call stack, and execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. When execution state is maintained for each individual thread, threads executing the same instructions may be converged and executed in parallel for maximum efficiency. The SM  340  will be described in more detail below in conjunction with  FIG.  4 A . 
     The MMU  390  provides an interface between the GPC  250  and the partition unit  280 . The MMU  390  may provide translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In an embodiment, the MMU  390  provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses into physical addresses in the memory  204 . 
       FIG.  3 B  illustrates a memory partition unit  280  of the PPU  200  of  FIG.  2   , in accordance with an embodiment. As shown in  FIG.  3 B , the memory partition unit  280  includes a Raster Operations (ROP) unit  350 , a level two (L2) cache  360 , and a memory interface  370 . The memory interface  370  is coupled to the memory  204 . Memory interface  370  may implement 32, 64, 128, 1024-bit data buses, or the like, for high-speed data transfer. In an embodiment, the PPU  200  incorporates U memory interfaces  370 , one memory interface  370  per pair of partition units  280 , where each pair of partition units  280  is connected to a corresponding memory device  204 . For example, PPU  200  may be connected to up to Y memory devices  204 , such as high bandwidth memory stacks or graphics double-data-rate, version 5, synchronous dynamic random access memory, or other types of persistent storage. 
     In an embodiment, the memory interface  370  implements an HBM2 memory interface and Y equals half U. In an embodiment, the HBM2 memory stacks are located on the same physical package as the PPU  200 , providing substantial power and area savings compared with conventional GDDR5 SDRAM systems. In an embodiment, each HBM2 stack includes four memory dies and Y equals 4, with HBM2 stack including two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits. 
     In an embodiment, the memory  204  supports Single-Error Correcting Double-Error Detecting (SECDED) Error Correction Code (ECC) to protect data. ECC provides higher reliability for compute applications that are sensitive to data corruption. Reliability is especially important in large-scale cluster computing environments where PPUs  200  process very large datasets and/or run applications for extended periods. 
     In an embodiment, the PPU  200  implements a multi-level memory hierarchy. In an embodiment, the memory partition unit  280  supports a unified memory to provide a single unified virtual address space for CPU and PPU  200  memory, enabling data sharing between virtual memory systems. In an embodiment the frequency of accesses by a PPU  200  to memory located on other processors is traced to ensure that memory pages are moved to the physical memory of the PPU  200  that is accessing the pages more frequently. In an embodiment, the NVLink  210  supports address translation services allowing the PPU  200  to directly access a CPU&#39;s page tables and providing full access to CPU memory by the PPU  200 . 
     In an embodiment, copy engines transfer data between multiple PPUs  200  or between PPUs  200  and CPUs. The copy engines can generate page faults for addresses that are not mapped into the page tables. The memory partition unit  280  can then service the page faults, mapping the addresses into the page table, after which the copy engine can perform the transfer. In a conventional system, memory is pinned (i.e., non-pageable) for multiple copy engine operations between multiple processors, substantially reducing the available memory. With hardware page faulting, addresses can be passed to the copy engines without worrying if the memory pages are resident, and the copy process is transparent. 
     Data from the memory  204  or other system memory may be fetched by the memory partition unit  280  and stored in the L2 cache  360 , which is located on-chip and is shared between the various GPCs  250 . As shown, each memory partition unit  280  includes a portion of the L2 cache  360  associated with a corresponding memory device  204 . Lower level caches may then be implemented in various units within the GPCs  250 . For example, each of the SMs  340  may implement a level one (L1) cache. The L1 cache is private memory that is dedicated to a particular SM  340 . Data from the L2 cache  360  may be fetched and stored in each of the L1 caches for processing in the functional units of the SMs  340 . The L2 cache  360  is coupled to the memory interface  370  and the XBar  270 . 
     The ROP unit  350  performs graphics raster operations related to pixel color, such as color compression, pixel blending, and the like. The ROP unit  350  also implements depth testing in conjunction with the raster engine  325 , receiving a depth for a sample location associated with a pixel fragment from the culling engine of the raster engine  325 . The depth is tested against a corresponding depth in a depth buffer for a sample location associated with the fragment. If the fragment passes the depth test for the sample location, then the ROP unit  350  updates the depth buffer and transmits a result of the depth test to the raster engine  325 . It will be appreciated that the number of partition units  280  may be different than the number of GPCs  250  and, therefore, each ROP unit  350  may be coupled to each of the GPCs  250 . The ROP unit  350  tracks packets received from the different GPCs  250  and determines which GPC  250  that a result generated by the ROP unit  350  is routed to through the Xbar  270 . Although the ROP unit  350  is included within the memory partition unit  280  in  FIG.  3 B , in other embodiment, the ROP unit  350  may be outside of the memory partition unit  280 . For example, the ROP unit  350  may reside in the GPC  250  or another unit. 
       FIG.  4 A  illustrates the streaming multi-processor  340  of  FIG.  3 A , in accordance with an embodiment. As shown in  FIG.  4 A , the SM  340  includes an instruction cache  405 , one or more scheduler units  410 (K), a register file  420 , one or more processing cores  450 , one or more special function units (SFUs)  452 , one or more load/store units (LSUs)  454 , an interconnect network  480 , a shared memory/L1 cache  470 . 
     As described above, the work distribution unit  225  dispatches tasks for execution on the GPCs  250  of the PPU  200 . The tasks are allocated to a particular DPC  320  within a GPC  250  and, if the task is associated with a shader program, the task may be allocated to an SM  340 . The scheduler unit  410 (K) receives the tasks from the work distribution unit  225  and manages instruction scheduling for one or more thread blocks assigned to the SM  340 . The scheduler unit  410 (K) schedules thread blocks for execution as warps of parallel threads, where each thread block is allocated at least one warp. In an embodiment, each warp executes 32 threads. The scheduler unit  410 (K) may manage a plurality of different thread blocks, allocating the warps to the different thread blocks and then dispatching instructions from the plurality of different cooperative groups to the various functional units (i.e., cores  450 , SFUs  452 , and LSUs  454 ) during each clock cycle. 
     Cooperative Groups is a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads are communicating, enabling the expression of richer, more efficient parallel decompositions. Cooperative launch APIs support synchronization amongst thread blocks for the execution of parallel algorithms. Conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (i.e., the syncthreads( ) function). However, programmers would often like to define groups of threads at smaller than thread block granularities and synchronize within the defined groups to enable greater performance, design flexibility, and software reuse in the form of collective group-wide function interfaces. 
     Cooperative Groups enables programmers to define groups of threads explicitly at sub-block (i.e., as small as a single thread) and multi-block granularities, and to perform collective operations such as synchronization on the threads in a cooperative group. The programming model supports clean composition across software boundaries, so that libraries and utility functions can synchronize safely within their local context without having to make assumptions about convergence. Cooperative Groups primitives enable new patterns of cooperative parallelism, including producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks. 
     A dispatch unit  415  is configured to transmit instructions to one or more of the functional units. In the embodiment, the scheduler unit  410 (K) includes two dispatch units  415  that enable two different instructions from the same warp to be dispatched during each clock cycle. In alternative embodiments, each scheduler unit  410 (K) may include a single dispatch unit  415  or additional dispatch units  415 . 
     Each SM  340  includes a register file  420  that provides a set of registers for the functional units of the SM  340 . In an embodiment, the register file  420  is divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file  420 . In another embodiment, the register file  420  is divided between the different warps being executed by the SM  340 . The register file  420  provides temporary storage for operands connected to the data paths of the functional units. 
     Each SM  340  comprises L processing cores  450 . In an embodiment, the SM  340  includes a large number (e.g., 128, etc.) of distinct processing cores  450 . Each core  450  may include a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes a floating point arithmetic logic unit and an integer arithmetic logic unit. In an embodiment, the floating point arithmetic logic units implement the IEEE 754-2008 standard for floating point arithmetic. In an embodiment, the cores  450  include 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores. 
     Tensor cores configured to perform matrix operations, and, in an embodiment, one or more tensor cores are included in the cores  450 . In particular, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In an embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices. 
     In an embodiment, the matrix multiply inputs A and B are 16-bit floating point matrices, while the accumulation matrices C and D may be 16-bit floating point or 32-bit floating point matrices. Tensor Cores operate on 16-bit floating point input data with 32-bit floating point accumulation. The 16-bit floating point multiply requires 64 operations and results in a full precision product that is then accumulated using 32-bit floating point addition with the other intermediate products for a 4×4×4 matrix multiply. In practice, Tensor Cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements. An API, such as CUDA 9 C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use Tensor Cores from a CUDA-C++ program. At the CUDA level, the warp-level interface assumes 16×16 size matrices spanning all 32 threads of the warp. 
     Each SM  340  also comprises M SFUs  452  that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like). In an embodiment, the SFUs  452  may include a tree traversal unit configured to traverse a hierarchical tree data structure. In an embodiment, the SFUs  452  may include texture unit configured to perform texture map filtering operations. In an embodiment, the texture units are configured to load texture maps (e.g., a 2D array of texels) from the memory  204  and sample the texture maps to produce sampled texture values for use in shader programs executed by the SM  340 . In an embodiment, the texture maps are stored in the shared memory/L1 cache  370 . The texture units implement texture operations such as filtering operations using mip-maps (i.e., texture maps of varying levels of detail). In an embodiment, each SM  240  includes two texture units. 
     Each SM  340  also comprises N LSUs  454  that implement load and store operations between the shared memory/L1 cache  470  and the register file  420 . Each SM  340  includes an interconnect network  480  that connects each of the functional units to the register file  420  and the LSU  454  to the register file  420 , shared memory/L1 cache  470 . In an embodiment, the interconnect network  480  is a crossbar that can be configured to connect any of the functional units to any of the registers in the register file  420  and connect the LSUs  454  to the register file and memory locations in shared memory/L1 cache  470 . 
     The shared memory/L1 cache  470  is an array of on-chip memory that allows for data storage and communication between the SM  340  and the primitive engine  335  and between threads in the SM  340 . In an embodiment, the shared memory/L1 cache  470  comprises 128 KB of storage capacity and is in the path from the SM  340  to the partition unit  280 . The shared memory/L1 cache  470  can be used to cache reads and writes. One or more of the shared memory/L1 cache  470 , L2 cache  360 , and memory  204  are backing stores. 
     Combining data cache and shared memory functionality into a single memory block provides the best overall performance for both types of memory accesses. The capacity is usable as a cache by programs that do not use shared memory. For example, if shared memory is configured to use half of the capacity, texture and load/store operations can use the remaining capacity. Integration within the shared memory/L1 cache  470  enables the shared memory/L1 cache  470  to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data. 
     When configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. Specifically, the fixed function graphics processing units shown in  FIG.  2   , are bypassed, creating a much simpler programming model. In the general purpose parallel computation configuration, the work distribution unit  225  assigns and distributes blocks of threads directly to the DPCs  320 . The threads in a block execute the same program, using a unique thread ID in the calculation to ensure each thread generates unique results, using the SM  340  to execute the program and perform calculations, shared memory/L1 cache  470  to communicate between threads, and the LSU  454  to read and write global memory through the shared memory/L1 cache  470  and the memory partition unit  280 . When configured for general purpose parallel computation, the SM  340  can also write commands that the scheduler unit  220  can use to launch new work on the DPCs  320 . 
     The PPU  200  may be included in a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and the like. In an embodiment, the PPU  200  is embodied on a single semiconductor substrate. In another embodiment, the PPU  200  is included in a system-on-a-chip (SoC) along with one or more other devices such as additional PPUs  200 , the memory  204 , a reduced instruction set computer (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), and the like. 
     In an embodiment, the PPU  200  may be included on a graphics card that includes one or more memory devices  204 . The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In yet another embodiment, the PPU  200  may be an integrated graphics processing unit (iGPU) or parallel processor included in the chipset of the motherboard. 
     Exemplary Computing System 
     Systems with multiple GPUs and CPUs are used in a variety of industries as developers expose and leverage more parallelism in applications such as artificial intelligence computing. High-performance GPU-accelerated systems with tens to many thousands of compute nodes are deployed in data centers, research facilities, and supercomputers to solve ever larger problems. As the number of processing devices within the high-performance systems increases, the communication and data transfer mechanisms need to scale to support the increased bandwidth. 
       FIG.  4 B  is a conceptual diagram of a processing system  400  implemented using the PPU  200  of  FIG.  2   , in accordance with an embodiment. The exemplary system  465  may be configured to implement the method  100  shown in  FIG.  1   . The processing system  400  includes a CPU  430 , switch  410 , and multiple PPUs  200  each and respective memories  204 . The NVLink  210  provides high-speed communication links between each of the PPUs  200 . Although a particular number of NVLink  210  and interconnect  202  connections are illustrated in  FIG.  4 B , the number of connections to each PPU  200  and the CPU  430  may vary. The switch  410  interfaces between the interconnect  202  and the CPU  430 . The PPUs  200 , memories  204 , and NVLinks  210  may be situated on a single semiconductor platform to form a parallel processing module  425 . In an embodiment, the switch  410  supports two or more protocols to interface between various different connections and/or links. 
     In another embodiment (not shown), the NVLink  210  provides one or more high-speed communication links between each of the PPUs  200  and the CPU  430  and the switch  410  interfaces between the interconnect  202  and each of the PPUs  200 . The PPUs  200 , memories  204 , and interconnect  202  may be situated on a single semiconductor platform to form a parallel processing module  425 . In yet another embodiment (not shown), the interconnect  202  provides one or more communication links between each of the PPUs  200  and the CPU  430  and the switch  410  interfaces between each of the PPUs  200  using the NVLink  210  to provide one or more high-speed communication links between the PPUs  200 . In another embodiment (not shown), the NVLink  210  provides one or more high-speed communication links between the PPUs  200  and the CPU  430  through the switch  410 . In yet another embodiment (not shown), the interconnect  202  provides one or more communication links between each of the PPUs  200  directly. One or more of the NVLink  210  high-speed communication links may be implemented as a physical NVLink interconnect or either an on-chip or on-die interconnect using the same protocol as the NVLink  210 . 
     In the context of the present description, a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit fabricated on a die or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip operation and make substantial improvements over utilizing a conventional bus implementation. Of course, the various circuits or devices may also be situated separately or in various combinations of semiconductor platforms per the desires of the user. Alternately, the parallel processing module  425  may be implemented as a circuit board substrate and each of the PPUs  200  and/or memories  204  may be packaged devices. In an embodiment, the CPU  430 , switch  410 , and the parallel processing module  425  are situated on a single semiconductor platform. 
     In an embodiment, the signaling rate of each NVLink  210  is 20 to 25 Gigabits/second and each PPU  200  includes six NVLink  210  interfaces (as shown in  FIG.  4 B , five NVLink  210  interfaces are included for each PPU  200 ). Each NVLink  210  provides a data transfer rate of 25 Gigabytes/second in each direction, with six links providing 300 Gigabytes/second. The NVLinks  210  can be used exclusively for PPU-to-PPU communication as shown in  FIG.  4 B , or some combination of PPU-to-PPU and PPU-to-CPU, when the CPU  430  also includes one or more NVLink  210  interfaces. 
     In an embodiment, the NVLink  210  allows direct load/store/atomic access from the CPU  430  to each PPU&#39;s  200  memory  204 . In an embodiment, the NVLink  210  supports coherency operations, allowing data read from the memories  204  to be stored in the cache hierarchy of the CPU  430 , reducing cache access latency for the CPU  430 . In an embodiment, the NVLink  210  includes support for Address Translation Services (ATS), allowing the PPU  200  to directly access page tables within the CPU  430 . One or more of the NVLinks  210  may also be configured to operate in a low-power mode. 
       FIG.  4 C  illustrates an exemplary system  465  in which the various architecture and/or functionality of the various previous embodiments may be implemented. The exemplary system  465  may be configured to implement the method  100  shown in  FIG.  1   . 
     As shown, a system  465  is provided including at least one central processing unit  430  that is connected to a communication bus  475 . The communication bus  475  may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s). The system  465  also includes a main memory  440 . Control logic (software) and data are stored in the main memory  440  which may take the form of random access memory (RAM). 
     The system  465  also includes input devices  460 , the parallel processing system  425 , and display devices  445 , i.e. a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light emitting diode), plasma display or the like. User input may be received from the input devices  460 , e.g., keyboard, mouse, touchpad, microphone, and the like. Each of the foregoing modules and/or devices may even be situated on a single semiconductor platform to form the system  465 . Alternately, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user. 
     Further, the system  465  may be coupled to a network (e.g., a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, or the like) through a network interface  435  for communication purposes. 
     The system  465  may also include a secondary storage (not shown). The secondary storage includes, for example, a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, digital versatile disk (DVD) drive, recording device, universal serial bus (USB) flash memory. The removable storage drive reads from and/or writes to a removable storage unit in a well-known manner. 
     Computer programs, or computer control logic algorithms, may be stored in the main memory  440  and/or the secondary storage. Such computer programs, when executed, enable the system  465  to perform various functions. The memory  440 , the storage, and/or any other storage are possible examples of computer-readable media. 
     The architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and/or any other desired system. For example, the system  465  may take the form of a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, a mobile phone device, a television, workstation, game consoles, embedded system, and/or any other type of logic. 
     While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. 
     Machine Learning 
     Deep neural networks (DNNs) developed on processors, such as the PPU  200  have been used for diverse use cases, from self-driving cars to faster drug development, from automatic image captioning in online image databases to smart real-time language translation in video chat applications. Deep learning is a technique that models the neural learning process of the human brain, continually learning, continually getting smarter, and delivering more accurate results more quickly over time. A child is initially taught by an adult to correctly identify and classify various shapes, eventually being able to identify shapes without any coaching. Similarly, a deep learning or neural learning system needs to be trained in object recognition and classification for it get smarter and more efficient at identifying basic objects, occluded objects, etc., while also assigning context to objects. 
     At the simplest level, neurons in the human brain look at various inputs that are received, importance levels are assigned to each of these inputs, and output is passed on to other neurons to act upon. An artificial neuron or perceptron is the most basic model of a neural network. In one example, a perceptron may receive one or more inputs that represent various features of an object that the perceptron is being trained to recognize and classify, and each of these features is assigned a certain weight based on the importance of that feature in defining the shape of an object. 
     A deep neural network (DNN) model includes multiple layers of many connected perceptrons (e.g., nodes) that can be trained with enormous amounts of input data to quickly solve complex problems with high accuracy. In one example, a first layer of the DLL model breaks down an input image of an automobile into various sections and looks for basic patterns such as lines and angles. The second layer assembles the lines to look for higher level patterns such as wheels, windshields, and mirrors. The next layer identifies the type of vehicle, and the final few layers generate a label for the input image, identifying the model of a specific automobile brand. 
     Once the DNN is trained, the DNN can be deployed and used to identify and classify objects or patterns in a process known as inference. Examples of inference (the process through which a DNN extracts useful information from a given input) include identifying handwritten numbers on checks deposited into ATM machines, identifying images of friends in photos, delivering movie recommendations to over fifty million users, identifying and classifying different types of automobiles, pedestrians, and road hazards in driverless cars, or translating human speech in real-time. 
     During training, data flows through the DNN in a forward propagation phase until a prediction is produced that indicates a label corresponding to the input. If the neural network does not correctly label the input, then errors between the correct label and the predicted label are analyzed, and the weights are adjusted for each feature during a backward propagation phase until the DNN correctly labels the input and other inputs in a training dataset. Training complex neural networks requires massive amounts of parallel computing performance, including floating-point multiplications and additions that are supported by the PPU  200 . Inferencing is less compute-intensive than training, being a latency-sensitive process where a trained neural network is applied to new inputs it has not seen before to classify images, translate speech, and generally infer new information. 
     Neural networks rely heavily on matrix math operations, and complex multi-layered networks require tremendous amounts of floating-point performance and bandwidth for both efficiency and speed. With thousands of processing cores, optimized for matrix math operations, and delivering tens to hundreds of TFLOPS of performance, the PPU  200  is a computing platform capable of delivering performance required for deep neural network-based artificial intelligence and machine learning applications. 
     Exemplary Simulation Environment 
       FIG.  5    illustrates a simulation solution environment  500 , according to one exemplary embodiment. As shown, a plurality of input coordinates  502  are queried within a physics space  504 . In one embodiment, the input coordinates may be associated with a simulation. In another embodiment, the physics space  504  may include a multi-resolution latent context grid created utilizing a machine learning environment. 
     Additionally, in response to the querying of the input coordinates  502 , the physics space  504  returns a correlation  506  between the plurality of input coordinates  502 . In one embodiment, the correlation may be determined by performing interpolation within the physics space  504 . 
     Further, both the input coordinates  502  and correlation  506  are provided as input into a machine learning environment  508 . In one embodiment, the machine learning environment  508  may be trained utilizing one or more physics model loss functions. In response to the input, the machine learning environment  508  produces a result  510  (e.g., a solution to the simulation at the plurality of input coordinates  502 , etc.). 
     In this way, the machine learning environment  508  may be used to implement a simulation (instead of performing a complete implementation of the simulation itself). As a complete implementation of the simulation utilized more power and hardware computing resources than the machine learning implementation, an amount of power and computing resources necessary to implement the simulation may be reduced. 
     Physics Space Creation Environment 
       FIG.  6    illustrates a machine learning environment  600  for creating a physics space, according to one exemplary embodiment. As shown, an initial condition (IC) input  602  and a boundary condition (BC) input  604  are sent to both a spatial domain  606  and a frequency domain  608 . In one embodiment, the machine learning environment  600  may include one or more convolutional neural networks (CNNs) that take the IC input  602 , BC input  604 , an IC DCT  610 , and a BC DCT  612  and return extracted low-resolution features. 
     Within the spatial domain  606 , a machine learning environment may perform recurrent neural network (RNN) propagation on the initial condition input  602  to create additional states. A linear transformation may be performed on these additional states, utilizing the boundary condition input  604 . Results of this transformation may include IC and BC values for each of a plurality of timesteps. 
     The IC input  602  and the BC input  604  may be transformed utilizing respective discrete cosine transforms (DCTs)  610  and  612 . The transformed input may then be sent to the frequency domain  608 , where a machine learning environment may perform RNN propagation on the transformed input to create additional initial conditions, and a linear transformation may be performed on these additional initial conditions, utilizing the transformed boundary condition input, to obtain IC and BC values for each of a plurality of timesteps in the frequency domain  608 . An inverse DCT transform  614  may then be applied to these IC and BC values in the frequency domain to convert the values back to the spatial domain. 
     Further, a summation module  616  may combine results of the spatial domain  606  and the frequency domain  608 , and these combined results may be decoded and upsampled to obtain a physics space  618  (e.g., a multi-resolution latent context grid). 
     In this way, a physics space  618  may be created that may be queried to obtain a correlation between a plurality of input coordinates. It should be noted that the machine learning environment  600  may include, but is not limited to, any combination of hardware and/or software that is or is not part of the aforementioned non-transitory memory, instructions, hardware processors, and/or devices, etc. 
     Physics Informed RNN-DCT Networks for Time-Dependent Partial Differential Equations 
     Physics-informed neural networks allow models to be trained by physical laws described by general nonlinear partial differential equations. However, traditional architectures struggle to solve more challenging time-dependent problems. In one embodiment, a physics-informed framework is provided for solving time-dependent partial differential equations. This framework utilizes discrete cosine transforms to encode spatial frequencies and recurrent neural networks to process the time evolution, achieving improved performance relative to other physics-informed baseline models. 
     Numerical simulations have become an indispensable tool for modeling physical systems, which in turn drive advancements in engineering and scientific discovery. However, as the physical complexity or spatio-temporal resolution of a simulation increases, the computational resources and run times required to solve the governing partial differential equations (PDEs) often grow drastically. 
     Machine learning approaches may be applied to the domain of physical simulation to ameliorate these issues by approximating traditional solvers with faster, less resource-intensive ones. These methods may include data-driven supervision or physics-informed neural networks (PINNs). PINN-based solvers parameterize the solution function directly as a neural network. This is typically done by passing a set of query points through a feed-forward fully-connected neural network (or multilayer perceptrons (MLPs)) and minimizing a loss function based on the governing PDEs, initial conditions (ICs) and boundary conditions (BCs). This allows the simulation to be constrained by physics alone and does not require any training data. 
     However, the accuracy of traditional PINN-based approaches is limited to problems in low dimensions and with simpler time-independent physics. Although PINNs provide a well-principled machine learning approach that promises to revolutionize numerical simulations, their current constraints to problems with simple geometries and short times severely limits their real-world impact. These shortcomings are addressed by introducing a design that improves the simulation accuracy and efficiency of PINN solvers on more challenging problems, particularly in the regime of long time evolution where current PINNs severely struggle. 
     Exemplary contributions are as follows: (1) A new approach is provided for generating a grid of latent context vectors to condition the spatio-temporal query points entering the MLP. This method requires no additional data and enables PINNs to learn complex time-dependent physics problems. (2) This approach is the first to directly address space-time-dependent physics end-to-end in PINNs with RNNs. 
     Unlike previous approaches, the current model does not need a separate method to handle the time dimension. This is achieved by utilizing convolutional gated recurrent units (ConvGRUs) for learning the spatio-temporal dynamics of simulations. (3) The spatial and frequency domains may be separated, which may increase flexibility for the network to learn more diverse physical problems. (4) This model demonstrates improved accuracy and performance when compared to earlier implementations. 
     In one embodiment, a new model is provided that enables PINN-based neural solvers to learn temporal dynamics in both the spatial and frequency domains. Using no additional data, this architecture may generate a latent context grid that efficiently represents more challenging spatio-temporal physical problems. The architecture includes latent context generation, decoding, and physics-informing. 
     Latent Grid Network 
     In one embodiment, a latent grid network may generate context grids which efficiently represent the entire spatio-temporal domain of a physical problem without the need for additional data. 
     This network may require two inputs for the problem-specific constraints: ICs and BCs. The ICs are defined as u 0 =u(x 1, . . . , N ; t=0) for each PDE solution function u over N spatial dimensions. The BCs are defined based on the geometry of the problem for each spatial dimension. An additional spatial weighting by signed distance functions (SDFs) can also be applied to avoid discontinuities at, e.g., physical boundaries, but may not be necessary for, e.g., periodic BCs. Each tensor undergoes an encoding step in either the frequency or spatial domain. 
     After compression, the representations enter the RNN propagation stage, in which the BCs are split into an additive (B bc ) and multiplicative (W bc ) components and combined with an IC-informed state matrix (H t ). The final output at each timestep is computed as S t =W bc H t +B bc . This implementation offers flexibility and efficiency in learning the dynamics of compressed simulations. 
     To predict the simulation state at each successive timestep, the previous hidden state H t−1  is passed through a convolutional GRU (ConvGRU) along with the previous output S t−1 ; for timestep 0, the initial state H 0  is set to zero and ICs are used as inputs. This occurs in a recurrent manner until the final time T. Thus, for each timestep, the RNN propagation stage outputs S t  which is then sent to a decoding step corresponding to the original frequency or spatial encoding: 
         S   0   =u   0   ;H   0 =0; H   t =ConvGRU( S   t−1   ;H   t−1 ); S   t   =W   bc   H   t   +B   bc   ;t∈{ 1, . . . , T}.    
     The RNN propagation stage is duplicated across two branches: frequency and spatial. The frequency branch transforms the spatial inputs to frequencies via the discrete cosine transform (DCTs). When implementing a patch-wise DCT encoding step, first, the ICs and BCs are separately split into spatial patches of size p×p. DCTs are performed on each patch to yield the corresponding p×p frequency coefficient array. The tensor is then reshaped such that the same coefficient across all patches forms each channel, and the channels are reordered by increasing coefficient (i.e., decreasing energy). After the reordering, the channels are truncated by n %, so the lowest n % of frequency coefficients (largest energies) are kept. This outputs highly compressed representations for the ICs and BCs, which are used as inputs for an RNN propagation branch that occurs completely in the frequency domain. 
     The spatial branch may include a ResNet architecture, in which the ICs and BCs each pass through separate convolutional encoders consisting of sets of convolutional blocks with residual connections. The inputs are downsampled with strided convolutions before entering the RNN propagation stage in the spatial domain. 
     After RNN propagation, the outputs are combined to form the latent grid. In the frequency branch, the output state at each timestep from the RNN is converted back into the spatial domain. This is done by reshaping the frequencies from coefficients to patches, performing IDCTs, and then merging the patches to reconstruct the spatial domain. The output of the frequency branch is denoted as O t   f . 
     The representation in the spatial domain O t   s  is then added with learnable weights W t   o . Thus, the final output is computed as: 
     
       
      
       O 
       t 
       =W 
       t 
       o 
       O 
       t 
       s 
       +O 
       t 
       f  
      
     
     These combined outputs O t  for each timestep are used to form the spatio-temporal latent context grids. Finally, grids at multiple resolutions are generated by upsampling the outputs O t  using transpose convolutional blocks. 
     Decoding Step 
     The multi-resolution latent context grids generated from the previous step are then used to query points input to the MLP. Given a random query point x:=(x,y,t), k neighboring vertices of the query point at each dimension are selected. Using these neighboring vertices, the final values of the context vector are then interpolated using Gaussian interpolation. This process is repeated for each of the multi-resolution grids allowing the PINN framework to learn multi-scale spatio-temporal quantities. 
     Physics-Informed Loss 
     The MLP outputs predictions that are subject to a loss function determined by the ICs, BCs, and the PDEs. The losses are backpropagated through the entire combined decoding and latent grid network and minimized via stochastic gradient descent. This end-to-end training allows the two-branch convGRU model to learn accurate time-evolution of the spatial and frequency domains in complex physical problems. 
     While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. 
     The disclosure may be described in the general context of computer code or machine-useable instructions, including computer-executable instructions such as program modules, being executed by a computer or other machine, such as a personal data assistant or other handheld device. Generally, program modules including routines, programs, objects, components, data structures, etc., refer to code that perform particular tasks or implement particular abstract data types. The disclosure may be practiced in a variety of system configurations, including hand-held devices, consumer electronics, general-purpose computers, more specialty computing devices, etc. The disclosure may also be practiced in distributed computing environments where tasks are performed by remote-processing devices that are linked through a communications network. 
     As used herein, a recitation of “and/or” with respect to two or more elements should be interpreted to mean only one element, or a combination of elements. For example, “element A, element B, and/or element C” may include only element A, only element B, only element C, element A and element B, element A and element C, element B and element C, or elements A, B, and C. In addition, “at least one of element A or element B” may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B. Further, “at least one of element A and element B” may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B. 
     The subject matter of the present disclosure is described with specificity herein to meet statutory requirements. However, the description itself is not intended to limit the scope of this disclosure. Rather, the inventors have contemplated that the claimed subject matter might also be embodied in other ways, to include different steps or combinations of steps similar to the ones described in this document, in conjunction with other present or future technologies. Moreover, although the terms “step” and/or “block” may be used herein to connote different elements of methods employed, the terms should not be interpreted as implying any particular order among or between various steps herein disclosed unless and except when the order of individual steps is explicitly described.