Patent Publication Number: US-10778242-B2

Title: Analog-to-digital converter device

Description:
RELATED APPLICATIONS 
     This application claims priority to U.S. Provisional Application Ser. No. 62/791,128, filed Jan. 11, 2019, and also claims priority of U.S. Provisional Application Ser. No. 62/806,026, filed Feb. 15, 2019, all of which are herein incorporated by reference in their entireties. 
    
    
     BACKGROUND 
     Technical Field 
     The present disclosure relates to an analog-to-digital converter (ADC) device. More particularly, the present disclosure relates to a time interleaved successive approximation register ADC having a noise shaping function. 
     Description of Related Art 
     An analog-to-digital converter (ADC) has been widely applied to various electronic devices, in order to covert an analog signal to a digital signal for subsequent signal processing. As the need of processing data with high resolution (for example, video data) rises, the ADC is often the key component in the system. However, in practical applications, performance of the ADC is affected by serval non-ideal factors, such as process variations, quantization noise, thermal noise, and so on. 
     SUMMARY 
     Some aspects of the present disclosure are to provide an analog-to-digital converter (ADC) device that includes capacitor arrays, a successive approximation register (SAR) circuitry, and a switching circuitry. The capacitor arrays are configured to sample an input signal by turns, in which when a first capacitor array of the capacitor arrays is configured to sample the input signal in a first phase, a second capacitor array of the capacitor arrays is configured to output the input signal sampled in a second phase as a sampled input signal. The first phase is a current phase, and the second phase is prior to the first phase. The SAR circuitry is configured to perform an analog-to-digital conversion on a combination of the sampled input signal and a residue signal generated in the second phase according to a conversion clock signal, in order to generate a digital output. The switching circuitry includes a first capacitor configured to store the residue signal generated in the second phase. The switching circuitry is configured to couple the second capacitor array and the first capacitor to an input terminal of the SAR circuitry, in order to provide the combination of the sampled input signal and the residue signal. 
     As described above, the ADC device of embodiments of the present disclosure are able to provide a circuit architecture that has a noise-shaping function and time-interleaved conversion. As a result, the overall performance of the ADC device can be improved. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a schematic diagram of an analog-to-digital converter (ADC) device according to some embodiments of the present disclosure. 
         FIG. 1B  is a schematic diagram illustrating waveforms of signals in  FIG. 1A  according to some embodiments of the present disclosure. 
         FIG. 2  is a schematic diagram of the ADC device according to some embodiments of the present disclosure. 
         FIG. 3A  is a schematic diagram of the ADC device in phase k−1 according to some embodiments of the present disclosure. 
         FIG. 3B  is a schematic diagram illustrating waveforms of signals in  FIG. 3A  according to some embodiments of the present disclosure. 
         FIG. 3C  is a schematic diagram of the ADC device in  FIG. 3A  in phase k according to some embodiments of the present disclosure. 
         FIG. 3D  is a schematic diagram of the ADC device in  FIG. 3A  in phase k+1 according to some embodiments of the present disclosure. 
         FIG. 4  is a circuit diagram of the switched-capacitor in  FIGS. 3A, 3C , and/or  3 D according to some embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following embodiments are disclosed with accompanying diagrams for detailed description. For illustration clarity, many details of practice are explained in the following descriptions. However, it should be understood that these details of practice do not intend to limit the present disclosure. That is, these details of practice are not necessary in parts of embodiments of the present embodiments. Furthermore, for simplifying the drawings, some of the conventional structures and elements are shown with schematic illustrations. 
     In this document, the term “coupled” may also be termed as “electrically coupled,” and the term “connected” may be termed as “electrically connected.” “Coupled” and “connected” may mean “directly coupled” and “directly connected” respectively, or “indirectly coupled” and “indirectly connected” respectively. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other. 
     In this document, the term “circuitry” may indicate a system formed with one or more circuits. The term “circuit” may indicate an object, which is formed with one or more transistors and/or one or more active/passive elements based on a specific arrangement, for processing signals. 
     For ease of understanding, like elements in each figure are designated with the same reference number. 
       FIG. 1A  is a schematic diagram of an analog-to-digital converter (ADC) device  100  according to some embodiments of the present disclosure. In some embodiments, the ADC device  100  operates as a time interleaved successive approximation register (SAR) ADC. 
     The ADC device  100  includes binary capacitor arrays CT 1  and CT 2 , a switching circuitry  120 , and a SAR circuitry  140 . The SAR circuitry  140  includes a comparator circuit  142 , control logic circuits  144  and  146 , and switches M 1 -M 2 . In some embodiments, the binary capacitor arrays CT 1  and CT 2  cooperate with the switching circuitry  120 , in order to provide a noise shaping function to the ADC device  100 . 
     The binary capacitor arrays CT 1  and CT 2  samples an input signal V in  by turns, in order to provide the sampled input signal V in  to the SAR circuitry  140 . The SAR circuitry  140  performs a binary search algorithm based on the sampled input signal V in  and common voltages V refn  and V refp . In some embodiments, the binary search algorithm is performed under control of one of the control logic circuits  144  and  146 . The comparator circuit  142  and the control logic circuits  144  and  146  are enabled by a clock signal ϕ c  (e.g., a conversion clock signal) to perform the binary search algorithm, in order to execute an analog-to-digital (A/D) conversion on the sampled input signal V in  to decide a digital output D out . 
     The switch M 1  is conducted (e.g., closed) in response to an enabling level of a clock signal ϕ s1′ , in order to transmit the clock signal ϕ c  to the control logic circuit  144 . The switch M 2  is conducted in response to an enabling level of a clock signal ϕ s2′ , in order to transmit the clock signal ϕ c  to the control logic circuit  146 . The clock signal ϕ s1′  is an inverse of a clock signal ϕ s1 , and the clock signal ϕ s2′  is an inverse of a clock signal ϕ s2 . 
     Each of the binary capacitor arrays CT 1  and CT 2  includes capacitors and switches that are controlled by a corresponding one of the control logic circuits  144  and  146 . A first terminal of each of capacitors in the binary capacitor array CT 1  is configured to receive the input signal V in  and is coupled to a node N 1 . A second terminal of each of capacitors in the binary capacitor array CT 1  is configured to selectively receive common mode voltage V refn  or V refp  under the control of the control logic circuit  144 . A first terminal of each of capacitors in the binary capacitor array CT 2  is configured to receive the input signal V in  and is coupled to a node N 2 . A second terminal of each of capacitors in the binary capacitor array CT 2  is configured to selectively receive common mode voltage V refn  or V refp  under the control of the control logic circuit  146 . 
     The switching circuitry  120  is configured to couple the binary capacitor arrays CT 1  and CT 2  to the comparator circuit  142  according to at least one clock signal. 
     The switching circuitry  120  includes switches S 1 -S 9  and capacitors C 2 -C 3 . A first terminal of the switch S 1  receives the input signal V in . A second terminal of the switch S 1  is coupled to the node N 1 . The switch S 1  is closed in response to an enabling level (e.g., high level) of the clock signal ϕ s1 , in order to transmit the input signal V in  to the binary capacitor array CT 1 . A first terminal of the switch S 2  receives the input signal V in . A second terminal of the switch S 2  is coupled to the first terminal of the binary capacitor array CT 2 . The switch S 2  is conducted in response to an enabling level of the clock signal ϕ s2 . 
     The switch S 3  is coupled between the node N 1  and a first terminal of the capacitor C 2 . The switch S 3  is conducted in response to an enabling level of a clock signal ϕ T1C . Under this condition, the sampled input signal V in  is provided from the binary capacitor array CT 1  to the capacitor C 2  for the A/D conversion. 
     The switch S 4  is coupled between the node N 2  and the first terminal of the capacitor C 2 . The switch S 4  is conducted in response to an enabling level (e.g., high level) of a clock signal ϕ T2C . Under this condition, the sampled input signal V in  is provided from the binary capacitor array CT 2  to the capacitor C 2  for the A/D conversion. 
     The switch S 5  is coupled between the node N 1  and a first terminal of the capacitor C 3 . A second terminal of the capacitor C 3  is coupled to ground. The switch S 5  is conducted in response to an enabling level of a clock signal ϕ s5 . Under this condition, a residue signal on the binary capacitor array CT 1  is transferred to the capacitor C 3 . In some embodiments, the residue signal on the binary capacitor array CT 1  is generated in the A/D conversion or after the A/D conversion is completed. In some embodiments, the clock signal ϕ s5  may be a result of logic AND operation of a clock signal ϕ cs0  and an inverse of the clock signal ϕ s1 . For example, as shown in  FIG. 1B , when the clock signal ϕ cs0  has the enabling level, and when the clock signal ϕ s1  has a disabling level (e.g., a low level), the clock signal ϕ s5  has the enabling level. 
     The switch S 6  is coupled between the node N 2  and the first terminal of the capacitor C 3 . The switch S 6  is conducted in response to an enabling level of a clock signal ϕ s6 . Under this condition, a residue signal on the binary capacitor array CT 2  is transferred to the capacitor C 3 . In some embodiments, the residue signal on the binary capacitor array CT 2  is generated in the A/D conversion or after the A/D conversion is completed. In some embodiments, the clock signal ϕ s6  may be a result of logic AND operation of a clock signal ϕ cs0  and an inverse of the clock signal ϕ s2 . For example, as shown in  FIG. 1B , when the clock signal ϕ cs0  has the enabling level and the clock signal ϕ s2  has a disabling level, the clock signal ϕ s6  has the enabling level. 
     The switch S 7  is coupled between the first terminal of the capacitor C 2  and ground. A second terminal of the capacitor C 2  is coupled to one input terminal (e.g., positive input terminal) of the comparator circuit  142 . Another one input terminal (e.g., negative input terminal) of the comparator circuit  142  is coupled to ground. The switch S 8  is coupled between the second terminal of the capacitor C 2  and the first terminal of the capacitor C 3 . The switches S 7 -S 8  are conducted in response to an enabling level of a clock signal ϕ cs1 . Under this condition, the capacitor C 3  is coupled to the capacitor C 2 . After the charge sharing of the capacitors C 2 -C 3  is settled, the capacitor C 2  stores a residue signal Vres 2 . The residue signal Vres 2  is a charge sharing result of the capacitor C 2  and the residue signal previously stored on the capacitor C 3 . 
     The switch S 9  is coupled between the first terminal of the capacitor C 3  and ground. The switch S 9  is conducted in response to an enabling level of a clock signal ϕ clean , in order to reset the capacitor C 3  to ground. In some embodiments, the ground mentioned above may be an AC ground. 
     Reference is made to both of  FIGS. 1A and 1B .  FIG. 1B  is a schematic diagram illustrating waveforms of signals in  FIG. 1A  according to some embodiments of the present disclosure. 
     As shown in  FIG. 1B , in some embodiments, a time interval of the clock signal ϕ c  having the enabling level is within a time interval of the clock signal ϕ s1  or φ s2  having the enabling level. In other words, when the SAR circuitry  140  performs the A/D conversion, one of the switches S 1 -S 2  is conducted, and the one of the binary capacitor arrays CT 1 -CT 2  samples the input signal V in  for the corresponding A/D conversion. 
     In some embodiments, in a conversion phase k−1, a time interval of the clock signal ϕ T1C  having the enabling level is within a portion T 2 - 1  of the time interval of the clock signal ϕ S2  having the enabling level. The portion T 2 - 1  is overlapped with the time interval of the clock signal ϕ c  having the enabling level. Time intervals of the clock signals ϕ cs0 , ϕ s5 , ϕ cs1 , and ϕ clean  having the enabling levels are within a portion T 2 - 2  of the time interval of the clock signal ϕ S2  having the enabling level. The portion T 2 - 2  follows the portion T 2 - 1 . 
     Similarly, in a conversion phase k, a time interval of the clock signal ϕ T2C  having the enabling level is within a portion T 1 - 1  of the time interval of the clock signal ϕ s1  having the enabling level. The portion T 1 - 1  is overlapped with the time interval of the clock signal ϕ c  having the enabling level. Time intervals of the clock signals ϕ cs0 , ϕ s5 , ϕ cs1 , and ϕ clean  having the enabling level are within a portion T 1 - 2  of the time interval of the clock signal ϕ S1  having the enabling level. The portion T 1 - 2  follows the portion T 1 - 1 . 
     The time interval of the clock signal ϕ cs0  (or ϕ s5 /ϕ s6 ) having the enabling level follows the time interval of the clock signal ϕ c  having the enabling level. In other words, in phase k−1, after the A/D conversion is completed, the switch S 5  is conducted to couple the capacitor C 3  to the binary capacitor array CT 1 . In phase k, after the A/D conversion is completed, the switch S 6  is conducted to couple the capacitor C 3  to the binary capacitor array CT 2 . 
     The time interval of the clock signal ϕ cs1  having the enabling level follows the time interval of the clock signal ϕ cs0  (or ϕ s5 /ϕ s6 ) having the enabling level. In other words, in phase k−1, after the charge sharing of the binary capacitor array CT 1  and the capacitor C 3  is settled, the switches S 7 -S 8  are conducted, such that the capacitors C 2 -C 3  are connected. In phase k, after the charge sharing of the binary capacitor array CT 2  and the capacitor C 3  is settled, the switches S 7 -S 8  are conducted, such that the capacitors C 2 -C 3  are connected. 
     The time interval of the clock signal ϕ clean  having the enabling level follows the time interval of the clock signal ϕ cs1  having the enabling level. In other words, after the charge sharing of the capacitors C 2 -C 3  is settled, the switches S 9  is conducted to reset the capacitor C 3 . 
     In some embodiments, the clock signal ϕ s1  is an inverse to the clock signal ϕ s2 . For example, in phase k, the clock signal ϕ s1  has the enabling level, and the clock signal ϕ s2  has the disabling level. Under this condition, as shown in  FIG. 1A , the switch S 1  is conducted, and the binary capacitor array CT 1  samples the input signal V in  in phase k (hereinafter “V in (k)”). The switch S 2  is not conducted, and the switch M 2  is conducted. Accordingly, the SAR circuitry  140  performs the A/D conversion, under the control of the control logic circuit  146 , based on the input signal V in (k−1) previously sampled on the binary capacitor array CT 2  and a residue signal Vres 2 ( k −1) previously stored on the capacitor C 2 . Equivalently, the comparator circuit  142  quantizes the combination of the input signal V in (k−1) and the residue signal Vres 2 ( k −1) to generate the corresponding digital output D out (k). In response to the enabling level of the clock signal ϕ cs1 , the capacitors C 2 -C 3  are connected, and thus the residue signal Vres 2 ( k ) is stored by the capacitor C 2  at the end of phase k−1. In some embodiments, the residue signal Vres 2 ( k ) may indicate quantization error(s) corresponding to the A/D conversion in the phase k−1. 
     In phase k+1, the clock signal ϕ s2  has the enabling level, and the clock signal ϕ s1  has the disabling level. Under this condition, the switch S 2  is conducted, and the binary capacitor array CT 2  samples the input signal V in (k+1). The switch S 1  is not conducted, and the switch M 1  is conducted. Accordingly, the SAR circuitry  140  performs the A/D conversion, under the control of the control logic circuit  144 , based on the input signal V in (k) sampled on the binary capacitor array CT 1  and the residue signal Vres 2 ( k ). Equivalently, the comparator circuit  142  quantizes the combination of the input signal V in (k) and the residue signal Vres 2 ( k ) to generate the corresponding digital output D out (k+1). In response to the enabling level of the clock signal ϕ cs1 , the capacitors C 2 -C 3  are connected, and thus the residue signal Vres 2 ( k +1) is stored by the capacitor C 2  at the end of phase k+1. 
     With this analogy, in each conversion phase, the A/D conversion is executed based on a combination of the input signal V in , and the residue signal Vres 2  that indicates quantization error(s) in a previous phase. As a result, a noise transfer function having the characteristic of noise shaping of the ADC device  100  can be obtained. Accordingly, a signal-to-noise ratio of the output of the ADC device  100  can be increased. 
     Reference is made to  FIG. 2  and  FIG. 1B .  FIG. 2  is a schematic diagram of the ADC device  100  according to some embodiments of the present disclosure. 
     Compared with  FIG. 1A , in this example, the switching circuitry  120  only utilizes the switches S 1 -S 7  and the capacitor C 2 , and the switch S 7  is controlled by the clock signal ϕ cs0 . In this example, as operation(s) of the switches S 8 -S 9  are omitted, the time interval of the conversion phase (e.g., phase k−1, k, k+1, . . . ) can be further reduced. 
     In phase k−1, when the clock signal ϕ cs0  and the clock signal ϕ s5  has the enabling level, the switches S 5  and S 7  are conducted. Under this condition, the binary capacitor array CT 1  is connected to the capacitor C 2 . After the charge sharing of the binary capacitor array CT 1  and the capacitor C 2 . The capacitor C 2  stores the residue signal Vres 2 ( k −1). 
     In phase k, when the clock signal ϕ c  has the enabling level, the A/D conversion is performed based on a combination of the sampled input signal V in (k−1) and the residue signal Vres 2 ( k −1). When the clock signal ϕ cs0  and the clock signal ϕ s6  has the enabling level, the switches S 6  and S 7  are turned on. Under this condition, the binary capacitor array CT 2  is connected to the capacitor C 2 . After the charge sharing of the binary capacitor array CT 2  and the capacitor C 2  is settled, the capacitor C 2  stores the residue signal Vres 2 ( k ). In other words, the switch S 6  is conducted to transfer a residue signal generated in the A/D conversion in phase k from the capacitor array CT 2  to the capacitor C 2 . As a result, the capacitor C 2  stores the residue signal Vres 2 ( k ). 
     In phase k+1, when the clock signal ϕ c  has the enabling level, the A/D conversion is performed based on a combination of the sampled input signal V in (k) and the residue signal Vres 2 ( k ). As a result, a noise transfer function having the characteristic of noise shaping of the ADC device  100  can be obtained as well. 
     In the above embodiments, both of the time interval of the SAR circuitry  140  performing the A/D conversion (e.g., time interval of the clock signal ϕ c  having the enabling level) and the time interval of the switching circuitry  120  performing the charge sharing (e.g., time intervals of the clock signals ϕ cs0 , ϕ cs1 , and ϕ clean  having the enabling level, or time interval of clock signal ϕ cs0 ) are within the time interval of the conversion phase (e.g., phase k−1, k, k+1, . . . ). In some embodiments, during the charge sharing, the first terminal of the capacitor C 2  may be open. 
     The above configurations of each clock signal and the switching circuitry  120  are given for illustrative purposes, and the present disclosure is not limited thereto. 
     Reference is made to  FIG. 3A  to  FIG. 3D .  FIG. 3A  is a schematic diagram of the ADC device  100  in phase k−1 according to some embodiments of the present disclosure.  FIG. 3B  is a schematic diagram illustrating waveforms of signals in  FIG. 3A  according to some embodiments of the present disclosure.  FIG. 3C  is a schematic diagram of the ADC device  100  in phase k according to some embodiments of the present disclosure.  FIG. 3D  is a schematic diagram of the ADC device  100  in phase k+1 according to some embodiments of the present disclosure. 
     In this example, the switching circuitry  120  includes switches S 1 -S 4 , in which the switch S 3  is controlled by the clock signal ϕ s1′ , and the switch S 4  is controlled by the clock signal ϕ s2′ . The switching circuitry  120  further includes switched-capacitors Cex 1 -Cex 3  In some embodiments, the switched-capacitors Cex 1 -Cex 3  are configured to be coupled to the binary capacitor array CT 1 , CT 2 , and the capacitor C 2  by turns, in order to provide a residue signal in a corresponding phase to the SAR circuitry  140 . In greater detail, in each conversion phase, two of the switched-capacitors Cex 1 -Cex 3  operate as capacitors in the binary capacitor arrays CT 1  and CT 2  respectively, and a remaining capacitor of the switched-capacitors Cex 1 -Cex 3  is coupled in parallel with the capacitor C 2  to transfer the residue signal. 
     For example, as shown in  FIG. 3A  and  FIG. 3B , in phase k−1, the switched-capacitor Cex 1  is coupled between switch(es) of the binary capacitor array CT 1  and the node N 1  for the A/D conversion. The switched-capacitor Cex 3  is coupled in parallel with the capacitor C 2  for charge sharing. Under this condition, the switched-capacitor Cex 1  stores the residue signal Vres 2 ( k −1) in the A/D conversion or after the A/D conversion is completed. The switched-capacitor Cex 2  is coupled between switch(es) of the binary capacitor array CT 2  and the node N 2 , in order to sample the input signal V in (k−1). 
     As shown in  FIG. 3B  and  FIG. 3C , in phase k, the switched-capacitor Cex 2  is coupled between the switch(es) of the binary capacitor array CT 2  and the node N 2  for the A/D conversion. The switched-capacitor Cex 1  is coupled in parallel with the capacitor C 2  for charge sharing. Under this condition, the A/D conversion is made based on a combination of the sampled input signal V in (k−1) and the residue signal Vres 2 ( k −1) shared by the switched-capacitor Cex 1 . The switched-capacitor Cex 2  stores the residue signal Vres 2 ( k ) in the A/D conversion or after the A/D conversion is completed. The switched-capacitor Cex 3  is coupled between the switch(es) of the binary capacitor array CT 1  and the node N 1 , in order to sample the input signal V in (k). 
     As shown in  FIG. 3B  and  FIG. 3D , in phase k+1, the switched-capacitor Cex 3  is coupled between the switch(es) of the binary capacitor array CT 1  and the node N 1  for the A/D conversion. The switched-capacitor Cex 2  is coupled in parallel with the capacitor C 2  for charge sharing. Under this condition, the A/D conversion is made based on a combination of the sampled input signal V in (k) and the residue signal Vres 2 ( k ) shared by the capacitor Cex 2 . The switched-capacitor Cex 3  stores the residue signal Vres 2 ( k +1) in the A/D conversion or after the A/D conversion is completed. The switched-capacitor Cex 1  is coupled between the switch(es) of the binary capacitor array CT 2  and the node N 2 , in order to sample the V in (k+1). 
     With this configuration, as shown in  FIG. 3B , only the time interval of the SAR circuitry  140  performing the A/D conversion (e.g., time interval of the clock signal ϕ c  having the enabling level) is within the time interval of the conversion phase (e.g., phase k−1, k, k+1, . . . ). Accordingly, the time interval of the conversion phase in this example can be further reduced, and the ADC device  100  equivalently operates in a higher clock rate. 
     In some embodiments, the clock signal ϕ c  may be a group of synchronous clock signals. In some embodiments, the clock signal ϕ c  may be a group of asynchronous clock signals. Various settings of the clock signal ϕ c  are within the contemplated scope of the present disclosure. 
     Reference is made to  FIG. 4 .  FIG. 4  is a circuit diagram of the switched-capacitor Cex 1  in  FIGS. 3A, 3C , and/or  3 D according to some embodiments of the present disclosure. 
     As shown in  FIG. 4 , the switched-capacitor Cex 1  includes a capacitor C and a switching circuit  410 . The switching circuit  410  operates as a multiplexer circuit based on a combination of the clock signals ϕ s1  and ϕ s2 , in order to couple the capacitor C to different terminals of the binary capacitor array CT 1  or CT 2 , or the nodes N 1  or N 2 , or the capacitor C 2 . Thus, in different phases, the switched-capacitor Cex 1  may be set to provide different functions, as discussed in  FIGS. 3A, 3C, and 3D . 
     The implementations of the switched-capacitors Cex 2  and Cex 3  can be understood with reference to  FIG. 4 . The implementations of the switched-capacitors Cex 1 -Cex 3  are given for illustrative purposes, and the present disclosure is not limited thereto. 
     In some embodiments, the comparator circuit  142  in  FIGS. 1A, 2, 3A, 3C , and  3 D may be implemented with two comparators that are configured to operate with the control logic circuits  144  and  146  respectively. 
     As described above, the ADC devices of embodiments of the present disclosure are able to provide a circuit architecture that has a noise-shaping function and time-interleaved conversion. As a result, the overall performance of the ADC device can be improved. 
     Various functional components or blocks have been described herein. As will be appreciated by persons skilled in the art, in some embodiments, the functional blocks will preferably be implemented through circuits (either dedicated circuits, or general purpose circuits, which operate under the control of one or more processors and coded instructions), which will typically comprise transistors or other circuit elements that are configured in such a way as to control the operation of the circuitry in accordance with the functions and operations described herein. As will be further appreciated, the specific structure or interconnections of the circuit elements will typically be determined by a compiler, such as a register transfer language (RTL) compiler. RTL compilers operate upon scripts that closely resemble assembly language code, to compile the script into a form that is used for the layout or fabrication of the ultimate circuitry. Indeed, RTL is well known for its role and use in the facilitation of the design process of electronic and digital systems. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.