Patent Publication Number: US-11646343-B2

Title: Capacitor structure and method for manufacturing the same

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates in general to a capacitor structure and a method for manufacturing the same, and more particularly to a deep trench capacitor structure and a method for manufacturing the same. 
     Description of the Related Art 
     A capacitor structure plays a critical role in a semiconductor device. In particular, the capacitor structure having a high capacitance is in highly demands. For example, a higher storage capacitance in DRAM can increase its stability; a higher capacitance in a decoupling capacitor can filter more noise. Accordingly, it is urged to develop a capacitor structure having a high capacitance. 
     SUMMARY OF THE INVENTION 
     In a comparison example, a capacitor structure may include a deep trench capacitor (DTC) formed on a single side of a substrate. In order to increase the capacitance of the capacitor structure, depths of the trenches for the capacitor are desired to be increased. However, if depths of the trenches for the capacitor are too deep, insulating layer(s) and conductive layer(s) included in the capacitor may not be properly formed in the trenches, and problems of the current leakage or dielectric breakdown may be occurred. Therefore, there is a need for developing a capacitor structure to improve the problems described above. 
     The present invention is directed to a capacitor structure and a method for manufacturing the capacitor structure. 
     According to an embodiment of the present invention, a capacitor structure is provided. A capacitor structure comprises a substrate having a first side and a second side opposite to the first side; a plurality of first trenches formed on the first side of the substrate; a plurality of second trenches formed on the second side of the substrate; a first capacitor extending along the first side and into the first trenches; and a second capacitor extending along the second side and into the second trenches. 
     According to another embodiment of the present invention, a method for manufacturing a capacitor structure is provided. The method comprises: providing a substrate having a first side and a second side opposite to the first side; forming a plurality of first trenches on the first side; forming a first capacitor extending along the first side and into the first trenches; forming a plurality of second trenches on the second side; and forming a second capacitor extending along the second side and into the second trenches. 
     The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1 A  is a cross-sectional view illustrating a capacitor structure according to a first embodiment of the present invention. 
         FIG.  1 B  is a top view illustrating a plurality of first trenches and a plurality of second trenches in the capacitor structure of  FIG.  1   . 
         FIG.  2    is a cross-sectional view illustrating a capacitor structure according to a second embodiment of the present invention. 
         FIG.  3    is a cross-sectional view illustrating a capacitor structure according to a third embodiment of the present invention. 
         FIG.  4    is a cross-sectional view illustrating a capacitor structure according to a fourth embodiment of the present invention. 
         FIG.  5    is a cross-sectional view illustrating a capacitor structure according to a fifth embodiment of the present invention. 
         FIGS.  6 A- 6 C  illustrate a method for manufacturing the capacitor structure according to an embodiment of the present application. 
         FIG.  7    illustrates the capacitor structure applied in an interposer according to an embodiment of the present application. 
         FIG.  8    illustrates the capacitor structure applied in an interposer according to another embodiment of the present application. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the structures, processes, and contents of the embodiments are merely illustrative, and the scope of the present application is not limited to the aspects described. It is to be understood that the present application dose not show all possible embodiments, and is not to be construed as being limited by the scope of the application, and the structure and process of the embodiments may be varied and modified to meet the needs of the application for one of ordinary skill in the art. Therefore, other implementations not presented in this application may also be applicable. 
     Further, in the embodiments, the same or similar elements are designated by the same or similar reference numerals for clarity. In addition, the drawings have been simplified to clearly illustrate the contents of the embodiments, and the scale ratios in the drawings are not drawn to scale in accordance with the actual products, and thus are not intended to limit the scope of the application. 
       FIG.  1 A  is a cross-sectional view illustrating a capacitor structure  10  according to a first embodiment of the present invention.  FIG.  1 B  is a top view illustrating a plurality of first trenches  102   a  and a plurality of second trenches  102   b  in the capacitor structure  10  of  FIG.  1 A .  FIG.  1 A  shows a plane formed by a first direction (i.e. X direction) and a third direction (i.e. Z direction) and corresponding to line  1 A- 1 A′ of  FIG.  1 B .  FIG.  1 B  shows a plane formed by the first direction (i.e. X direction) and a second direction (i.e. Y direction), and the elements formed in/on the first trenches  102   a  and the second trenches  102   b  are omitted in  FIG.  1 B . 
     Referring to  FIGS.  1 A and  1 B , a capacitor structure  10  comprises a substrate  100  having a first side  100   a  and a second side  100   b  opposite to the first side  100   a ; a plurality of first trenches  102   a  formed on the first side  100   a  of the substrate  100 ; a plurality of second trenches  102   b  formed on the second side  100   b  of the substrate  100 ; a first capacitor  110   a  extending along the first side  100   a  and into the first trenches  102   a ; and a second capacitor  110   b  extending along the second side  100   b  and into the second trenches  102   b.    
     As shown in  FIG.  1 A , the substrate  100  has an upper surface  100 U corresponding to the first side  100   a  of the substrate  100 . As shown in  FIG.  1 B , the first trenches  102   a  are disposed along the first direction (i.e. X direction) and the second direction (i.e. Y direction) on the first side  100   a  of the substrate, the first direction and the second direction are intersected with each other and parallel to the upper surface  100 U of the substrate  100 . That is, the first side  100   a  corresponds to the upper surface  100 U of the substrate  100 , and the second side  100   b  corresponds to a lower surface of the substrate  100 . The first trenches  102   a  and the second trenches  102   b  penetrate portions of the substrate  100  along the third direction (i.e. Z direction). More specifically, the first trenches  102   a  extend from an upper surface  100 U of the substrate  100  to the inner portion of the substrate  100 , and the second trenches  102   b  extend from a lower surface of the substrate  100  to the inner portion of the substrate  100 . In some embodiments, the extending directions of the first trenches  102   a  and the second trenches  102   b  are parallel to the third direction (i.e. Z direction). 
     In the present embodiment, as shown in  FIG.  1 A , an angle α formed between a sidewall of the first trench  102   a  and a bottom of the first trench  102   a  is 90 degrees, and an angle β formed between a sidewall of the second trench  102   b  and a bottom of the second trench  102   b  is 90 degrees. In other embodiments, the angle α formed between the sidewall of the first trench  102   a  and the bottom of the first trench  102   a  may be greater than 90 degrees, or/and the angle β formed between the sidewall of the second trench  102   b  and the bottom of the second trench  102   b  may be greater than 90 degrees, such that the first trench  102   a  or/and the second trench  102   b  may have a tapered sidewall. 
     Referring to  FIGS.  1 A and  1 B , the first trenches  102   a  and the second trenches  102   b  are separated in the third direction (i.e. Z direction), and are alternatively disposed in the substrate  100 , such that the first capacitor  110   a  formed in the first trenches  102   a  and the second capacitor  110   b  formed in the second trenches  102   b  are alternatively disposed in the substrate  100 . In the present embodiment, the first trenches  102   a  and the second trenches  102   b  are overlapped in the first direction (i.e. X direction), that is, a first depth D 1  of each of the first trenches  102   a  and a second depth D 2  of each of the second trenches  102   b  may be greater than half of a thickness of the substrate  100 , respectively, but the present application is not limited thereto. In other embodiments, the first trenches  102   a  and the second trenches  102   b  may be separated in the first direction (i.e. X direction). In some embodiments, the first depth D 1  may be equal to the second depth D 2 . 
     In some embodiments, referring to  FIGS.  1 A and  1 B , each of the first trenches  102   a  and each of the second trenches  102   b  may have a first critical dimension CD 1  and a second critical dimension CD 2  along the first direction (i.e. X direction), respectively. A first pitch P 1  may be formed between two neighboring first trenches  102   a  along the first direction (i.e. X direction). A second pitch P 2  may be formed between two neighboring second trenches  102   b  along the first direction (i.e. X direction). An aspect ratio of the first trenches  102   a  of the first critical dimension CD 1  to the first depth D 1  (CD 1 :D 1 ) may be equal to or smaller than 1:15, for example, CD 1 :D 1 =1:10. An aspect ratio of the second trenches  102   b  of the second critical dimension CD 2  to the second depth D 2  (CD 2 :D 2 ) may be equal to or smaller than 1:15, for example, CD 2 :D 2 =1:10. A ratio of the first critical dimension CD 1  to the first pitch P 1  may be equal to or greater than 1:2.2, for example, CD 1 :P 1 =1:3. A ratio of the second critical dimension CD 2  to the second pitch P 2  may be equal to or greater than 1:2.2, for example, CD 2 :P 2 =1:3. 
     As shown in  FIG.  1 A , a first insulating film  104   a  extends along the first side  100   a  and into the first trenches  102   a  and a second insulating film  104   b  extends along the second side  100   b  and into the second trenches  102   b . The first insulating film  104   a  is formed between the substrate  100  and the first capacitor  110   a . The second insulating film  104   b  is formed between the substrate  100  and the second capacitor  110   b . That is, portions of the upper surface  100 U of the substrate  100 , the sidewalls of the first trenches  102   a  and the bottoms of the first trenches  102   a  are covered by the first insulating film  104   a  and the first capacitor  110   a , and portions of the lower surface of the substrate  100 , the sidewalls of the second trenches  102   b  and the bottoms of the second trenches  102   b  are covered by the second insulating film  104   b  and the second capacitor  110   a . In the present embodiment, the first capacitor  110   a  comprises a first conductive layer  111   a , a first dielectric layer  113   a , a second conductive layer  115   a , a second dielectric layer  117   a  and a third conductive layer  119   a  sequentially stacked on the first side  110   a  of the substrate  100  and into the first trenches  102   a ; and the second capacitor  110   b  comprises a first conductive layer  111   b , a first dielectric layer  113   b , a second conductive layer  115   b , a second dielectric layer  117   b  and a third conductive layer  119   b  sequentially stacked on the second side  110   b  of the substrate  100  and into the second trenches  102   b . The first capacitor  110   a  and the second capacitor  110   b  include a “MIMIM (metal-insulator-metal-insulator-metal)” structure, respectively. However, the amounts of the dielectric layer(s) and the conductive layers in the first capacitor  110   a  and the second capacitor are not limited thereto. 
     In the present embodiment, the first trenches  102   a  are disposed in a first region A 1  on the first side  100   a  of the substrate  100 , and the second trenches  102   b  are disposed in a second region B 1  on the second side  100   b  of the substrate  100 . The first region A 1  corresponds to the second region B 1 ; in other words, the first region A 1  and the second region B 1  are overlapped in the third direction (i.e. Z direction), but the present invention is not limited thereto. 
     In some embodiments, the substrate  100  may be a silicon-based substrate. The first conductive layers  111   a  and  111   b , the second conductive layers  115   a  and  115   b  and the third conductive layers  119   a  and  119   b  may include a material formed of copper, titanium nitride (TiN) or any other suitable conductive materials. The first dielectric layers  113   a  and  113   b  and the second dielectric layers  117   a  and  117   b  may include a material formed of the thermal oxide, oxide-nitride-oxide (ONO) composite film or other suitable dielectric materials. 
     In some embodiments, the substrate  100  may be applied in an interposer, a Silicon on Insulator (SOI) wafer or other suitable substrate. In some embodiments, the substrate  100  may have a thickness in a range of 50-100 μm along the third direction (i.e. Z direction), but the present application is not limited thereto. 
     In some embodiments, the first capacitor  110   a  and the second capacitor  110   b  may be electrically connected to different elements/devices. In some embodiments, the first capacitor  110   a  and the second capacitor  110   b  may be electrically connected together as one capacitor, for example, by the through silicon via (TSV), as shown in  FIG.  7   . 
     In a first comparative example, a capacitor structure has only a first capacitor formed on a single side of a substrate and formed into first trenches, the other side of the substrate has no trenches and the capacitor, and the pitch, the depth, and the critical dimension of the first trenches are respectively the same as the pitch, the depth, and the critical dimension of the first trenches  102   a  shown in  FIG.  1 A  of the present invention. 
     Since the capacitor structure  10  of the present invention has double-sided deep trench capacitors (capacitors  110   a  and  110   b ), the surface area of the capacitors  110   a  and  110   b  in the present invention is higher than the surface area of the capacitor in the first comparative example having the single-sided deep trench capacitor, the capacitor structure  10  of the present invention may have higher capacitance (such as 1.7 times). If the capacitance of the capacitor structure in the first comparative example is desired to achieve the capacitance of the capacitor structure in the present invention, a depth of the first trenches has to be increased (such as 21 μm) and a pitch of the first trenches has to be decreased (such as 2 μm), such that the process window and the process cost have to be increased; the aspect ratio of the first trenches may be too high (such as 1:21) and the critical dimension to the pitch may be too low (such as 1:2), the dielectric layers and the conductive layers of the capacitor in the first trenches may not be properly formed, thereby increasing the risk of current leakage or dielectric breakdown. Further, the process for forming the first capacitor and the second capacitor may be identical or similar, so that the process for forming the capacitor structure  10  is simple. Accordingly, the capacitor structure  10  according to an embodiment of the present invention may achieve a higher capacitance in a low process cost while maintaining a good electrical property without sacrificing process window and can also avoid process complexity. 
       FIG.  2    is a cross-sectional view illustrating a capacitor structure  20  according to a second embodiment of the present invention, and shows a plane formed by the first direction (i.e. X direction) and the third direction (i.e. Z direction). The configuration of the capacitor structure  20  and the configuration of the capacitor structure  10  shown in  FIG.  1    are similar, and the difference between the capacitor structure  20  and the capacitor structure  10  is in that the depths of the first trenches  202   a  and the second trenches  202   b  are smaller than the depths of the first trenches  102   a  and the second trenches  102   b , and the identical/similar features are not repeated here. 
     Referring to  FIG.  2   , the first trenches  202   a  and the second trenches  202   b  are separated in the third direction (i.e. Z direction), and are separated in the first direction (i.e. X direction). In the present embodiment, a gap G 1  may be formed between the first trenches  202   a  and the second trenches  202   b  projected on a plane perpendicular to the upper surface  100 U of the substrate  100 . In other embodiments, there may be no gap between the first trenches  202   a  and the second trenches  202   b  projected on a plane perpendicular to the upper surface  100 U of the substrate  100 ; the bottoms of the first trenches  202   a  and the bottoms of the second trenches  202   b  may be aligned along the first direction (i.e. X direction). A first insulating film  204   a  and a first capacitor  210   a  comprising a first conductive layer  211   a , a first dielectric layer  213   a , a second conductive layer  215   a , a second dielectric layer  217   a  and a third conductive layer  219   a  extend along the first side  100   a  and into the first trenches  102   a ; a second insulating film  204   b  and a second capacitor  210   a  comprising a first conductive layer  211   b , a first dielectric layer  213   b , a second conductive layer  215   b , a second dielectric layer  217   b  and a third conductive layer  219   b  extend along the second side  100   b  and into the second trenches  202   b . The materials and properties of the first insulating film  204   a , the first capacitor  210   a , the second insulating film  204   b  and the second capacitor  210   b  are respectively identical or similar to the materials and properties of the first insulating film  104   a , the first capacitor  110   a , the second insulating film  104   b  and the second capacitor  110   b.    
     In the present embodiment, the first trenches  202   a  and the second trenches  202   b  are disposed in a first region A 2  on the first side  100   a  of the substrate  100  and a second region B 2  on the second side  100   b  of the substrate  100 , respectively, and the first region A 2  and the second region B 2  are overlapped in the third direction (i.e. Z direction), but the present invention is not limited thereto. 
       FIG.  3    is a cross-sectional view illustrating a capacitor structure  30  according to a third embodiment of the present invention, and shows a plane formed by the first direction (i.e. X direction) and the third direction (i.e. Z direction). The difference between the capacitor structure  30  and the capacitor structure  10  is in that the depths of the first trenches  302   a  and the second trenches  302   b  are smaller than the depths of the first trenches  102   a  and the second trenches  102   b ; the arrangement of the first trenches  302   a  and the second trenches  302   b  and the arrangement of the first trenches  102   a  and the second trenches  102   b  are different; the identical/similar features are not repeated here. 
     Referring to  FIG.  3   , the first trenches  302   a  and the second trenches  302   b  are separated in the first direction (i.e. X direction), and are overlapped in the third direction (i.e. Z direction). In the present embodiment, a gap G 3  may be formed between the first trenches  302   a  and the second trenches  302   b  projected on a plane perpendicular to the upper surface  100 U of the substrate  100 . A first insulating film  304   a  and a first capacitor  310   a  comprising a first conductive layer  311   a , a first dielectric layer  313   a , a second conductive layer  315   a , a second dielectric layer  317   a  and a third conductive layer  319   a  extend along the first side  100   a  and into the first trenches  302   a ; a second insulating film  304   b  and a second capacitor  310   a  comprising a first conductive layer  311   b , a first dielectric layer  313   b , a second conductive layer  315   b , a second dielectric layer  317   b  and a third conductive layer  319   b  extend along the second side  100   b  and into the second trenches  302   b . The materials and properties of the first insulating film  304   a , the first capacitor  310   a , the second insulating film  304   b  and the second capacitor  310   b  are respectively identical or similar to the materials and properties of the first insulating film  104   a , the first capacitor  110   a , the second insulating film  104   b  and the second capacitor  110   b.    
     In the present embodiment, the first trenches  302   a  and the second trenches  302   b  are disposed in a first region A 3  on the first side  100   a  of the substrate  100  and a second region B 3  on the second side  100   b  of the substrate  100 , respectively, and the first region A 3  and the second region B 3  are overlapped in the third direction (i.e. Z direction), but the present invention is not limited thereto. 
       FIG.  4    is a cross-sectional view illustrating a capacitor structure  40  according to a fourth embodiment of the present invention, and shows a plane formed by the first direction (i.e. X direction) and the third direction (i.e. Z direction). The arrangement of the first trenches  402   a  and the second trenches  402   b  in the capacitor structure  40  and the arrangement of the first trenches  102   a  and the second trenches  102   b  in the capacitor structure  10  are different, and the identical/similar features are not repeated here. 
     Referring to  FIG.  4   , a first insulating film  404   a  and a first capacitor  410   a  comprising a first conductive layer  411   a , a first dielectric layer  413   a , a second conductive layer  415   a , a second dielectric layer  417   a  and a third conductive layer  419   a  extend along the first side  100   a  and into the first trenches  402   a ; a second insulating film  404   b  and a second capacitor  410   b  comprising a first conductive layer  411   b , a first dielectric layer  413   b , a second conductive layer  415   b , a second dielectric layer  417   b  and a third conductive layer  419   b  extend along the second side  100   b  and into the second trenches  402   b . The materials and properties of the first insulating film  404   a , the first capacitor  410   a , the second insulating film  404   b  and the second capacitor  410   b  are respectively identical or similar to the materials and properties of the first insulating film  104   a , the first capacitor  110   a , the second insulating film  104   b  and the second capacitor  110   b.    
     In the present embodiment, the first trenches  402   a  are disposed in a first region A 4  on the first side  100   a  of the substrate  100 , and the second trenches  402   b  are disposed in a second region B 4  on the second side  100   b  of the substrate  100 , and the first region A 4  and the second region B 4  are separated from each other in the third direction (i.e. Z direction). The first trenches  402   a  and the second trenches  402   b  are overlapped in the first direction (i.e. X direction). 
       FIG.  5    is a cross-sectional view illustrating a capacitor structure  50  according to a fifth embodiment of the present invention, and shows a plane formed by the first direction (i.e. X direction) and the third direction (i.e. Z direction). The depths of the first trenches  402   a  and the second trenches  402   b  in capacitor structure  50  are smaller than the depths of the first trenches  102   a  and the second trenches  102   b  in capacitor structure  10 ; the arrangement of the first trenches  402   a  and the second trenches  402   b  are different from the arrangement of the first trenches  102   a  and the second trenches  102   b , and the identical/similar features are not repeated here. 
     Referring to  FIG.  5   , a first insulating film  504   a  and a first capacitor  510   a  comprising a first conductive layer  511   a , a first dielectric layer  513   a , a second conductive layer  515   a , a second dielectric layer  517   a  and a third conductive layer  519   a  extend along the first side  100   a  and into the first trenches  502   a ; a second insulating film  504   b  and a second capacitor  510   a  comprising a first conductive layer  511   b , a first dielectric layer  513   b , a second conductive layer  515   b , a second dielectric layer  517   b  and a third conductive layer  519   b  extend along the second side  100   b  and into the second trenches  502   b . The materials and properties of the first insulating film  504   a , the first capacitor  510   a , the second insulating film  504   b  and the second capacitor  510   b  are respectively identical or similar to the materials and properties of the first insulating film  104   a , the first capacitor  110   a , the second insulating film  104   b  and the second capacitor  110   b.    
     In the present embodiment, the first trenches  502   a  and the second trenches  502   b  are disposed in a first region A 5  and a second region B 5  of the substrate  100 , respectively, and the first region A 5  and the second region B 5  are separated in the third direction (i.e. Z direction). The first trenches  502   a  and the second trenches  502   b  are also separated in the third direction (i.e. Z direction). The first trenches  502   a  and the second trenches  502   b  are separated in the first direction (i.e. X direction). A gap G 5  may be formed between the first trenches  502   a  and the second trenches  502   b  projected on a plane perpendicular to the upper surface  100 U of the substrate  100 . In other embodiments, there is no gap formed between the first trenches  502   a  and the second trenches  502   b  projected on a plane perpendicular to the upper surface  100 U of the substrate  100 . 
       FIGS.  6 A- 6 C  illustrate a method for manufacturing the capacitor structure  10  according to an embodiment of the present application. The capacitor structure  10  may be manufactured according to the following steps, but the invention is not limited thereto. Other capacitor structures  20 - 50  may be manufactured by a method similar to the method for manufacturing the capacitor structure  10 . 
     Referring to  FIG.  6 A , a substrate  100  is provided. The substrate  100  has a first side  100   a  and a second side  100   b  opposite to the first side  100   a . The substrate  100  may be applied in an interposer, a Silicon on Insulator (SOI) wafer or other suitable substrate. Then, a plurality of first trenches  102   a  are formed on the first side  100   a . The first trenches  102   a  are disposed along a first direction (X direction) and a second direction (Y direction) on the first side  100   a  of the substrate  100 . Each of the first trenches  102   a  penetrates a portion of the substrate  100 , and extends from an upper surface  100 U of the substrate  100  into the inner portion of the substrate  100  along the third direction (i.e. Z direction). In the present embodiment, an angle α formed between a sidewall of the first trench  102   a  and a bottom of the first trench  102   a  is 90 degrees. In other embodiments, the angle α formed between the sidewall of the first trench  102   a  and the bottom of the first trench  102   a  may be greater than 90 degrees, such that the first trench  102   a  may have a tapered sidewall. 
     Referring to  FIG.  6 B , a first insulating film  104   a  and a first capacitor  110   a  comprising a first conductive layer  111   a , a first dielectric layer  113   a , a second conductive layer  115   a , a second dielectric layer  117   a  and a third conductive layer  119   a  are formed extending along the first side  110   a  of the substrate  100  and into the first trenches  102   a . For example, the first insulating film  104   a , the first conductive layer  111   a , the first dielectric layer  113   a , the second conductive layer  115   a , the second dielectric layer  117   a  and the third conductive layer  119   a  are sequentially deposited on the first side  110   a  of the substrate  100  and into the first trenches  102   a.    
     Referring to  FIG.  6 C , a plurality of second trenches  102   b  are formed on the second side  100   b . Each of the second trenches  102   b  penetrates a portion of the substrate  100 , and extends from a bottom surface of the substrate  100  into the inner portion of the substrate  100  along the third direction (i.e. Z direction). In the present embodiment, an angle β formed between a sidewall of the second trench  102   b  and a bottom of the second trench  102   b  is 90 degrees. In other embodiments, the angle β formed between the sidewall of the second trench  102   b  and the bottom of the second trench  102   b  may be greater than 90 degrees, such that the second trench  102   b  may have a tapered sidewall. 
     Afterwards, referring back to  FIG.  1 A , a second insulating film  104   b  and a second capacitor  110   b  comprising a first conductive layer  111   b , a first dielectric layer  113   b , a second conductive layer  115   b , a second dielectric layer  117   b  and a third conductive layer  119   b  are formed extending along the second side  110   b  of the substrate  100  and into the second trenches  102   b . For example, the second insulating film  104   b , the first conductive layer  111   b , the first dielectric layer  113   b , the second conductive layer  115   b , the second dielectric layer  117   b  and the third conductive layer  119   b  are sequentially deposited on the second side  110   b  of the substrate  100  and into the second trenches  102   b . In this way, the capacitor structure  10  having double-sided deep trench capacitors (first capacitor  110   a  and second capacitor  110   b ) is formed. 
       FIG.  7    illustrates the capacitor structure  10  applied in an interposer according to an embodiment of the present application. 
     Referring to  FIG.  7   , a first via V 1  and a second via V 2  penetrate through the substrate  100  along the third direction, respectively. The first capacitor  110   a  comprises a first conductive layer  111   a , a first dielectric layer  113   a , a second conductive layer  115   a , a second dielectric layer  117   a  and a third conductive layer  119   a  sequentially stacked on the first side of the substrate, the second capacitor  110   b  comprises a first conductive layer  111   b , a first dielectric layer  113   b , a second conductive layer  115   b , a second dielectric layer  117   b  and a third conductive layer  119   b  sequentially stacked on the second side  110   b  of the substrate  100 . That is, the first capacitor  110   a  and the second capacitor  110   b  include a “MIMIM (metal-insulator-metal-insulator-metal) structure”, respectively. The first insulating film  104   a  and the first capacitor  110   a  extend along the first side  100   a  and into the first trenches  102   a . The second insulating film  104   b  and the second capacitor  110   b  extend along the second side  100   b  and into the second trenches  102   b . The first conductive layer  111   a  of the first capacitor  110   a , the first conductive layer  111   b  of the second capacitor  110   b , the third conductive layer  119   a  of the first capacitor  110   a  and the third conductive layer  119   b  of the second capacitor  110   b  are electrically connected to the first via V 1 ; the second conductive layer  115   a  of the first capacitor  110   a , the second conductive layer  115   b  of the second capacitor  110   b  are electrically connected to the second via V 2 , such that the first capacitor  110   a  and the second capacitor  110   b  are electrically connected to each other as one capacitor through the first via V 1  and the second via V 2 . 
       FIG.  8    illustrates the capacitor structure  10 ′ applied in an interposer according to another embodiment of the present application. The difference between the capacitor structure  10 ′ and  10  is in that the structure of the first capacitor  110   a ′ and the second capacitor  110   b ′ are different from the structure of the first capacitor  110   a  and the second capacitor  110   b.    
     Referring to  FIG.  8   , a first via V 1  and a second via V 2  penetrate through the substrate  100  along the third direction, respectively. The first capacitor  110   a ′ comprises a first conductive layer  111   a , a first dielectric layer  113   a  and a second conductive layer  115   a  sequentially stacked on the first side  100   a  of the substrate  100 , the second capacitor  110   b ′ comprises a first conductive layer  111   b , a first dielectric layer  113   b  and a second conductive layer  115   b  sequentially stacked on the second side  100   b  of the substrate  100 . That is, the first capacitor  110   a ′ and the second capacitor  110   b ′ include a “MIM (metal-insulator-metal) structure”, respectively. The first insulating film  104   a  and the first capacitor  110   a ′ extend along the first side  100   a  and into the first trenches  102   a . The second insulating film  104   b  and the second capacitor  110   b ′ extend along the second side  100   b  and into the second trenches  102   b . The first conductive layer  111   a  of the first capacitor  110   a ′, the first conductive layer  111   b  of the second capacitor  110   b ′ are electrically connected to a first via V 1 ; the second conductive layer  115   a  of the first capacitor  110   a ′, the second conductive layer  115   b  of the second capacitor  110   b ′ are electrically connected to a second via V 2 , such that the first capacitor  110   a ′ and the second capacitor′  110   b  are electrically connected together as one capacitor through the first via V 1  and the second via V 2 . 
     In sum, the present invention provides a capacitor structure and a method for manufacturing the capacitor structure. According to one embodiment of the present invention, a capacitor structure comprises a substrate having a first side and a second side opposite to the first side; a plurality of first trenches formed on the first side of the substrate; a plurality of second trenches formed on the second side of the substrate; a first capacitor extending along the first side and into the first trenches; and a second capacitor extending along the second side and into the second trenches. 
     Since the capacitor structure of the present invention has double-sided deep trench capacitors (i.e. first capacitor and the second capacitor), the surface area of the capacitors in the present invention is higher than the surface area of the capacitor in a comparative example having the single-sided deep trench capacitor, and the capacitor structure of the present invention may have higher capacitance. Further, the high capacitance of the present application can be achieved without making the first trenches and the second trenches too deep, so that the risk of current leakage or dielectric breakdown in the capacitor may be decreased. Additionally, the process for forming the first capacitor and the second capacitor may be identical or similar, so that the process for forming the capacitor structure of the present invention is simple. Accordingly, the capacitor structure according to an embodiment of the present invention may achieve a higher capacitance in a low process cost while maintaining a good electrical property without sacrificing process window and can also avoid process complexity. 
     While the invention has been described by way of example and in terms of the preferred embodiment(s), it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.