Patent Publication Number: US-2022238687-A1

Title: Transistor Gate Structures and Methods of Forming the Same

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application claims the benefit of U.S. Provisional Application No. 63/142,549, filed on Jan. 28, 2021, which application is hereby incorporated herein by reference. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. 
     The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  illustrates an example of a nanostructure field-effect transistor (nano-FET) in a three-dimensional view, in accordance with some embodiments. 
         FIGS. 2-20B  are views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments. 
         FIGS. 21A-21B  are views of nano-FETs, in accordance with some embodiments. 
         FIGS. 22A-22B  are views of nano-FETs, in accordance with some embodiments. 
         FIGS. 23A-23B  are views of nano-FETs, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     According to various embodiments, gate structures for p-type devices include work function tuning layers that are formed of a tungsten-containing work function material (WFM). For example, the tungsten-containing WFM may be pure tungsten (e.g., fluorine-free tungsten), tungsten nitride, tungsten carbide, tungsten carbonitride, or the like, which may be deposited by one of several deposition processes. Tungsten is suitable for tuning the work function of p-type devices. Advantageously, p-type devices with work function tuning layers formed of a tungsten-containing WFM may have a lower resistance than p-type devices with work function tuning layers formed of a WFM that contains other metals (such as tantalum). Device performance may thus be improved. 
     Embodiments are described in a particular context, a die including nano-FETs. Various embodiments may be applied, however, to dies including other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, or the like) in lieu of or in combination with the nano-FETs. 
       FIG. 1  illustrates an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs, or the like), in accordance with some embodiments.  FIG. 1  is a three-dimensional view, where some features of the nano-FETs are omitted for illustration clarity. The nano-FETs may be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate-all-around field-effect transistors (GAAFETs), or the like. 
     The nano-FETs include nanostructures  66  (e.g., nanosheets, nanowires, or the like) over fins  62  on a substrate  50  (e.g., a semiconductor substrate), with the nanostructures  66  acting as channel regions for the nano-FETs. The nanostructures  66  may include p-type nanostructures, n-type nanostructures, or a combination thereof. Isolation regions  70 , such as shallow trench isolation (STI) regions, are disposed between adjacent fins  62 , which may protrude above and from between adjacent isolation regions  70 . Although the isolation regions  70  are described/illustrated as being separate from the substrate  50 , as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although a bottom portion of the fins  62  are illustrated as being single, continuous materials with the substrate  50 , the bottom portion of the fins  62  and/or the substrate  50  may include a single material or a plurality of materials. In this context, the fins  62  refer to the portion extending above and from between the adjacent isolation regions  70 . 
     Gate dielectrics  122  are over top surfaces of the fins  62  and along top surfaces, sidewalls, and bottom surfaces of the nanostructures  66 . Gate electrodes  124  are over the gate dielectrics  122 . Epitaxial source/drain regions  98  are disposed on the fins  62  at opposing sides of the gate dielectrics  122  and the gate electrodes  124 . The epitaxial source/drain regions  98  may be shared between various fins  62 . For example, adjacent epitaxial source/drain regions  98  may be electrically connected, such as through coalescing the epitaxial source/drain regions  98  by epitaxial growth, or through coupling the epitaxial source/drain regions  98  with a same source/drain contact. 
       FIG. 1  further illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of a gate electrode  124  and in a direction, for example, perpendicular to a direction of current flow between the epitaxial source/drain regions  98  of a nano-FET. Cross-section B-B′ is along a longitudinal axis of a fin  62  and in a direction of, for example, a current flow between the epitaxial source/drain regions  98  of the nano-FET. Cross-section C-C′ is parallel to cross-section A-A′ and extends through epitaxial source/drain regions  98  of the nano-FETs. Subsequent figures refer to these reference cross-sections for clarity. 
     Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs, or in fin field-effect transistors (FinFETs). For example, FinFETs may include fins on a substrate, with the fins acting as channel regions for the FinFETs. Similarly, planar FETs may include a substrate, with portions of the substrate acting as channel regions for the planar FETs. 
       FIGS. 2-20B  are views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.  FIGS. 2, 3, 4, 5, and 6  are three-dimensional views showing a similar three-dimensional view as  FIG. 1 .  FIGS. 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A  illustrate reference cross-section A-A′ illustrated in  FIG. 1 .  FIGS. 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, and 20B  illustrate reference cross-section B-B′ illustrated in  FIG. 1 .  FIGS. 9C and 9D  illustrate reference cross-section C-C′ illustrated in  FIG. 1 . 
     In  FIG. 2 , a substrate  50  is provided for forming nano-FETs. The substrate  50  may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type impurity) or undoped. The substrate  50  may be a wafer, such as a silicon wafer. Generally, a SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate  50  may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; combinations thereof; or the like. 
     The substrate  50  has an n-type region  50 N and a p-type region  50 P. The n-type region  50 N can be for forming n-type devices, such as NMOS transistors, e.g., n-type nano-FETs, and the p-type region  50 P can be for forming p-type devices, such as PMOS transistors, e.g., p-type nano-FETs. The n-type region  50 N may be physically separated from the p-type region  50 P (not separately illustrated), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region  50 N and the p-type region  50 P. Although one n-type region  50 N and one p-type region  50 P are illustrated, any number of n-type regions  50 N and p-type regions  50 P may be provided. 
     The substrate  50  may be lightly doped with a p-type or an n-type impurity. An anti-punch-through (APT) implantation may be performed on an upper portion of the substrate  50  to form an APT region. During the APT implantation, impurities may be implanted in the substrate  50 . The impurities may have a conductivity type opposite from a conductivity type of source/drain regions that will be subsequently formed in each of the n-type region  50 N and the p-type region  50 P. The APT region may extend under the source/drain regions in the nano-FETs. The APT region may be used to reduce the leakage from the source/drain regions to the substrate  50 . In some embodiments, the doping concentration in the APT region may be in the range of about 10 18  cm −3  to about 10 19  cm −3 . 
     A multi-layer stack  52  is formed over the substrate  50 . The multi-layer stack  52  includes alternating first semiconductor layers  54  and second semiconductor layers  56 . The first semiconductor layers  54  are formed of a first semiconductor material, and the second semiconductor layers  56  are formed of a second semiconductor material. The semiconductor materials may each be selected from the candidate semiconductor materials of the substrate  50 . In the illustrated embodiment, the multi-layer stack  52  includes three layers of each of the first semiconductor layers  54  and the second semiconductor layers  56 . It should be appreciated that the multi-layer stack  52  may include any number of the first semiconductor layers  54  and the second semiconductor layers  56 . 
     In the illustrated embodiment, and as will be subsequently described in greater detail, the first semiconductor layers  54  will be removed and the second semiconductor layers  56  will patterned to form channel regions for the nano-FETs in both the n-type region  50 N and the p-type region  50 P. The first semiconductor layers  54  are sacrificial layers (or dummy layers), which will be removed in subsequent processing to expose the top surfaces and the bottom surfaces of the second semiconductor layers  56 . The first semiconductor material of the first semiconductor layers  54  is a material that has a high etching selectivity from the etching of the second semiconductor layers  56 , such as silicon germanium. The second semiconductor material of the second semiconductor layers  56  is a material suitable for both n-type and p-type devices, such as silicon. 
     In another embodiment (not separately illustrated), the first semiconductor layers  54  will be patterned to form channel regions for nano-FETs in one region (e.g., the p-type region  50 P), and the second semiconductor layers  56  will be patterned to form channel regions for nano-FETs in another region (e.g., the n-type region  50 N). The first semiconductor material of the first semiconductor layers  54  may be a material suitable for p-type devices, such as silicon germanium (e.g., Si x Ge 1-x , where x can be in the range of 0 to 1), pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The second semiconductor material of the second semiconductor layers  56  may be a material suitable for n-type devices, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The first semiconductor material and the second semiconductor material may have a high etching selectivity from the etching of one another, so that the first semiconductor layers  54  may be removed without removing the second semiconductor layers  56  in the n-type region  50 N, and the second semiconductor layers  56  may be removed without removing the first semiconductor layers  54  in the p-type region  50 P. 
     Each of the layers of the multi-layer stack  52  may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like. Each of the layers may have a small thickness, such as a thickness in a range of about 5 nm to about 30 nm. In some embodiments, some layers (e.g., the second semiconductor layers  56 ) are formed to be thinner than other layers (e.g., the first semiconductor layers  54 ). For example, in embodiments in which the first semiconductor layers  54  are sacrificial layers (or dummy layers) and the second semiconductor layers  56  are patterned to form channel regions for the nano-FETs in both the n-type region  50 N and the p-type region  50 P, the first semiconductor layers  54  can have a first thickness and the second semiconductor layers  56  can have a second thickness, with the second thickness being from about 30% to about 60% less than the first thickness. Forming the second semiconductor layers  56  to a smaller thickness allows the channel regions to be formed at a greater density. 
     In  FIG. 3 , trenches are patterned in the substrate  50  and the multi-layer stack  52  to form fins  62 , first nanostructures  64 , and second nanostructures  66 . The fins  62  are semiconductor strips patterned in the substrate  50 . The first nanostructures  64  and the second nanostructures  66  include the remaining portions of the first semiconductor layers  54  and the second semiconductor layers  56 , respectively. The trenches may be patterned by any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. 
     The fins  62  and the nanostructures  64 ,  66  may be patterned by any suitable method. For example, the fins  62  and the nanostructures  64 ,  66  may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used as masks to pattern the fins  62  and the nanostructures  64 ,  66 . In some embodiments, the mask (or other layer) may remain on the nanostructures  64 ,  66 . 
     The fins  62  and the nanostructures  64 ,  66  may each have widths in a range of about 8 nm to about 40 nm. In the illustrated embodiment, the fins  62  and the nanostructures  64 ,  66  have substantially equal widths in the n-type region  50 N and the p-type region  50 P. In another embodiment, the fins  62  and the nanostructures  64 ,  66  in one region (e.g., the n-type region  50 N) are wider or narrower than the fins  62  and the nanostructures  64 ,  66  in another region (e.g., the p-type region  50 P). 
     In  FIG. 4 , STI regions  70  are formed over the substrate  50  and between adjacent fins  62 . The STI regions  70  are disposed around at least a portion of the fins  62  such that at least a portion of the nanostructures  64 ,  66  protrude from between adjacent STI regions  70 . In the illustrated embodiment, the top surfaces of the STI regions  70  are coplanar (within process variations) with the top surfaces of the fins  62 . In some embodiments, the top surfaces of the STI regions  70  are above or below the top surfaces of the fins  62 . The STI regions  70  separate the features of adjacent devices. 
     The STI regions  70  may be formed by any suitable method. For example, an insulation material can be formed over the substrate  50  and the nanostructures  64 ,  66 , and between adjacent fins  62 . The insulation material may be an oxide, such as silicon oxide, a nitride, such as silicon nitride, the like, or a combination thereof, which may be formed by a chemical vapor deposition (CVD) process, such as high density plasma CVD (HDP-CVD), flowable chemical vapor deposition (FCVD), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In some embodiments, the insulation material is silicon oxide formed by FCVD. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material is formed such that excess insulation material covers the nanostructures  64 ,  66 . Although the STI regions  70  are each illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not separately illustrated) may first be formed along surfaces of the substrate  50 , the fins  62 , and the nanostructures  64 ,  66 . Thereafter, a fill material, such as those previously described may be formed over the liner. 
     A removal process is then applied to the insulation material to remove excess insulation material over the nanostructures  64 ,  66 . In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. In embodiments in which a mask remains on the nanostructures  64 ,  66 , the planarization process may expose the mask or remove the mask. After the planarization process, the top surfaces of the insulation material and the mask (if present) or the nanostructures  64 ,  66  are coplanar (within process variations). Accordingly, the top surfaces of the mask (if present) or the nanostructures  64 ,  66  are exposed through the insulation material. In the illustrated embodiment, no mask remains on the nanostructures  64 ,  66 . The insulation material is then recessed to form the STI regions  70 . The insulation material is recessed such that at least a portion of the nanostructures  64 ,  66  protrude from between adjacent portions of the insulation material. Further, the top surfaces of the STI regions  70  may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions  70  may be formed flat, convex, and/or concave by an appropriate etch. The insulation material may be recessed using any acceptable etching process, such as one that is selective to the material of the insulation material (e.g., selectively etches the insulation material of the STI regions  70  at a faster rate than the materials of the fins  62  and the nanostructures  64 ,  66 ). For example, an oxide removal may be performed using dilute hydrofluoric (dHF) acid. 
     The process previously described is just one example of how the fins  62  and the nanostructures  64 ,  66  may be formed. In some embodiments, the fins  62  and/or the nanostructures  64 ,  66  may be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate  50 , and trenches can be etched through the dielectric layer to expose the underlying substrate  50 . Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins  62  and/or the nanostructures  64 ,  66 . The epitaxial structures may include the alternating semiconductor materials previously described, such as the first semiconductor material and the second semiconductor material. In some embodiments where epitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and/or subsequent implantations, although in situ and implantation doping may be used together. 
     Further, appropriate wells (not separately illustrated) may be formed in the nanostructures  64 ,  66 , the fins  62 , and/or the substrate  50 . The wells may have a conductivity type opposite from a conductivity type of source/drain regions that will be subsequently formed in each of the n-type region  50 N and the p-type region  50 P. In some embodiments, a p-type well is formed in the n-type region  50 N, and an n-type well is formed in the p-type region  50 P. In some embodiments, a p-type well or an n-type well is formed in both the n-type region  50 N and the p-type region  50 P. 
     In embodiments with different well types, different implant steps for the n-type region  50 N and the p-type region  50 P may be achieved using mask (not separately illustrated) such as a photoresist. For example, a photoresist may be formed over the fins  62 , the nanostructures  64 ,  66 , and the STI regions  70  in the n-type region  50 N. The photoresist is patterned to expose the p-type region  50 P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region  50 P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region  50 N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration in the range of about 10 13  cm −3  to about 10 14  cm −3 . After the implant, the photoresist may be removed, such as by any acceptable ashing process. 
     Following or prior to the implanting of the p-type region  50 P, a mask (not separately illustrated) such as a photoresist is formed over the fins  62 , the nanostructures  64 ,  66 , and the STI regions  70  in the p-type region  50 P. The photoresist is patterned to expose the n-type region  50 N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region  50 N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region  50 P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration in the range of about 10 13  cm −3  to about 10 14  cm −3 . After the implant, the photoresist may be removed, such as by any acceptable ashing process. 
     After the implants of the n-type region  50 N and the p-type region  50 P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments where epitaxial structures are epitaxially grown for the fins  62  and/or the nanostructures  64 ,  66 , the grown materials may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together. 
     In  FIG. 5 , a dummy dielectric layer  72  is formed on the fins  62  and the nanostructures  64 ,  66 . The dummy dielectric layer  72  may be formed of a dielectric material such as silicon oxide, silicon nitride, a combination thereof, or the like, which may be deposited or thermally grown according to acceptable techniques. A dummy gate layer  74  is formed over the dummy dielectric layer  72 , and a mask layer  76  is formed over the dummy gate layer  74 . The dummy gate layer  74  may be deposited over the dummy dielectric layer  72  and then planarized, such as by a CMP. The mask layer  76  may be deposited over the dummy gate layer  74 . The dummy gate layer  74  may be formed of a conductive or non-conductive material, such as amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), a metal, a metallic nitride, a metallic silicide, a metallic oxide, or the like, which may be deposited by physical vapor deposition (PVD), CVD, or the like. The dummy gate layer  74  may be formed of material(s) that have a high etching selectivity from the etching of insulation materials, e.g., the STI regions  70  and/or the dummy dielectric layer  72 . The mask layer  76  may be formed of a dielectric material such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer  74  and a single mask layer  76  are formed across the n-type region  50 N and the p-type region  50 P. In the illustrated embodiment, the dummy dielectric layer  72  covers the fins  62 , the nanostructures  64 ,  66 , and the STI regions  70 , such that the dummy dielectric layer  72  extends over the STI regions  70  and between the dummy gate layer  74  and the STI regions  70 . In another embodiment, the dummy dielectric layer  72  covers only the fins  62  and the nanostructures  64 ,  66 . 
     In  FIG. 6 , the mask layer  76  is patterned using acceptable photolithography and etching techniques to form masks  86 . The pattern of the masks  86  is then transferred to the dummy gate layer  74  by any acceptable etching technique to form dummy gates  84 . The pattern of the masks  86  may optionally be further transferred to the dummy dielectric layer  72  by any acceptable etching technique to form dummy dielectrics  82 . The dummy gates  84  cover portions of the nanostructures  64 ,  66  that will be exposed in subsequent processing to form channel regions. Specifically, the dummy gates  84  extend along the portions of the nanostructures  66  that will be patterned to form channel regions  68 . The pattern of the masks  86  may be used to physically separate adjacent dummy gates  84 . The dummy gates  84  may also have lengthwise directions substantially perpendicular (within process variations) to the lengthwise directions of the fins  62 . The masks  86  can optionally be removed after patterning, such as by any acceptable etching technique. 
       FIGS. 7A-20B  illustrate various additional steps in the manufacturing of embodiment devices.  FIGS. 7A-13B and 18A-20B  illustrate features in either of the n-type region  50 N and the p-type region  50 P. For example, the structures illustrated may be applicable to both the n-type region  50 N and the p-type region  50 P. Differences (if any) in the structures of the n-type region  50 N and the p-type region  50 P are described in the text accompanying each figure.  FIGS. 14A-16B  illustrate features in the p-type region  50 P.  FIG. 17A-17B  illustrates features in the n-type region  50 N. 
     In  FIGS. 7A and 7B , gate spacers  90  are formed over the nanostructures  64 ,  66 , on exposed sidewalls of the masks  86  (if present), the dummy gates  84 , and the dummy dielectrics  82 . The gate spacers  90  may be formed by conformally depositing one or more dielectric material(s) and subsequently etching the dielectric material(s). Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which may be formed by a conformal deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or the like. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the gate spacers  90  each include multiple layers, e.g., a first spacer layer  90 A and a second spacer layer  90 B. In some embodiments, the first spacer layers  90 A and the second spacer layers  90 B are formed of silicon oxycarbonitride (e.g., SiO x N y C 1-x-y , where x and y are in the range of 0 to 1), with the first spacer layers  90 A formed of a similar or a different composition of silicon oxycarbonitride than the second spacer layers  90 B. Any acceptable etch process, such as a dry etch, a wet etch, the like, or a combination thereof, may be performed to pattern the dielectric material(s). The etching may be anisotropic. The dielectric material(s), when etched, have portions left on the sidewalls of the dummy gates  84  (thus forming the gate spacers  90 ). As will be subsequently described in greater detail, the dielectric material(s), when etched, may also have portions left on the sidewalls of the fins  62  and/or the nanostructures  64 ,  66  (thus forming fin spacers  92 , see  FIGS. 9C and 9D ). After etching, the fin spacers  92  and/or the gate spacers  90  can have straight sidewalls (as illustrated) or can have curved sidewalls (not separately illustrated). 
     Further, implants may be performed to form lightly doped source/drain (LDD) regions (not separately illustrated). In the embodiments with different device types, similar to the implants for the wells previously described, a mask (not separately illustrated) such as a photoresist may be formed over the n-type region  50 N, while exposing the p-type region  50 P, and appropriate type (e.g., p-type) impurities may be implanted into the fins  62  and/or the nanostructures  64 ,  66  exposed in the p-type region  50 P. The mask may then be removed. Subsequently, a mask (not separately illustrated) such as a photoresist may be formed over the p-type region  50 P while exposing the n-type region  50 N, and appropriate type impurities (e.g., n-type) may be implanted into the fins  62  and/or the nanostructures  64 ,  66  exposed in the n-type region  50 N. The mask may then be removed. The n-type impurities may be any of the n-type impurities previously described, and the p-type impurities may be any of the p-type impurities previously described. During the implanting, the channel regions  68  remain covered by the dummy gates  84 , so that the channel regions  68  remain substantially free of the impurity implanted to form the LDD regions. The LDD regions may have a concentration of impurities in the range of about 10 15  cm −3  to about 10 19  cm −3 . An anneal may be used to repair implant damage and to activate the implanted impurities. 
     It is noted that the previous disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized, additional spacers may be formed and removed, and/or the like. Furthermore, the n-type devices and the p-type devices may be formed using different structures and steps. 
     In  FIGS. 8A and 8B , source/drain recesses  94  are formed in the nanostructures  64 ,  66 . In the illustrated embodiment, the source/drain recesses  94  extend through the nanostructures  64 ,  66  and into the fins  62 . The source/drain recesses  94  may also extend into the substrate  50 . In various embodiments, the source/drain recesses  94  may extend to a top surface of the substrate  50  without etching the substrate  50 ; the fins  62  may be etched such that bottom surfaces of the source/drain recesses  94  are disposed below the top surfaces of the STI regions  70 ; or the like. The source/drain recesses  94  may be formed by etching the nanostructures  64 ,  66  using an anisotropic etching processes, such as a RIE, a NBE, or the like. The gate spacers  90  and the dummy gates  84  collectively mask portions of the fins  62  and/or the nanostructures  64 ,  66  during the etching processes used to form the source/drain recesses  94 . A single etch process may be used to etch each of the nanostructures  64 ,  66 , or multiple etch processes may be used to etch the nanostructures  64 ,  66 . Timed etch processes may be used to stop the etching of the source/drain recesses  94  after the source/drain recesses  94  reach a desired depth. 
     Optionally, inner spacers  96  are formed on the sidewalls of the remaining portions of the first nanostructures  64 , e.g., those sidewalls exposed by the source/drain recesses  94 . As will be subsequently described in greater detail, source/drain regions will be subsequently formed in the source/drain recesses  94 , and the first nanostructures  64  will be subsequently replaced with corresponding gate structures. The inner spacers  96  act as isolation features between the subsequently formed source/drain regions and the subsequently formed gate structures. Further, the inner spacers  96  may be used to substantially prevent damage to the subsequently formed source/drain regions by subsequent etching processes, such as etching processes used to subsequently remove the first nanostructures  64 . 
     As an example to form the inner spacers  96 , the source/drain recesses  94  can be laterally expanded. Specifically, portions of the sidewalls of the first nanostructures  64  exposed by the source/drain recesses  94  may be recessed. Although sidewalls of the first nanostructures  64  are illustrated as being straight, the sidewalls may be concave or convex. The sidewalls may be recessed by any acceptable etching process, such as one that is selective to the material of the first nanostructures  64  (e.g., selectively etches the material of the first nanostructures  64  at a faster rate than the material of the second nanostructures  66 ). The etching may be isotropic. For example, when the second nanostructures  66  are formed of silicon and the first nanostructures  64  are formed of silicon germanium, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH), or the like. In another embodiment, the etching process may be a dry etch using a fluorine-based gas such as hydrogen fluoride (HF) gas. In some embodiments, the same etching process may be continually performed to both form the source/drain recesses  94  and recess the sidewalls of the first nanostructures  64 . The inner spacers  96  can then be formed by conformally forming an insulating material and subsequently etching the insulating material. The insulating material may be silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The insulating material may be deposited by a conformal deposition process, such as ALD, CVD, or the like. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etch such as a RIE, a NBE, or the like. Although outer sidewalls of the inner spacers  96  are illustrated as being flush with respect to the sidewalls of the gate spacers  90 , the outer sidewalls of the inner spacers  96  may extend beyond or be recessed from the sidewalls of the gate spacers  90 . In other words, the inner spacers  96  may partially fill, completely fill, or overfill the sidewall recesses. Moreover, although the sidewalls of the inner spacers  96  are illustrated as being straight, the sidewalls of the inner spacers  96  may be concave or convex. 
     In  FIGS. 9A and 9B , epitaxial source/drain regions  98  are formed in the source/drain recesses  94 . The epitaxial source/drain regions  98  are formed in the source/drain recesses  94  such that each dummy gate  84  (and corresponding channel regions  68 ) is disposed between respective adjacent pairs of the epitaxial source/drain regions  98 . In some embodiments, the gate spacers  90  and the inner spacers  96  are used to separate the epitaxial source/drain regions  98  from, respectively, the dummy gates  84  and the first nanostructures  64  by an appropriate lateral distance so that the epitaxial source/drain regions  98  do not short out with subsequently formed gates of the resulting nano-FETs. A material of the epitaxial source/drain regions  98  may be selected to exert stress in the respective channel regions  68 , thereby improving performance. 
     The epitaxial source/drain regions  98  in the n-type region  50 N may be formed by masking the p-type region  50 P. Then, the epitaxial source/drain regions  98  in the n-type region  50 N are epitaxially grown in the source/drain recesses  94  in the n-type region  50 N. The epitaxial source/drain regions  98  may include any acceptable material appropriate for n-type devices. For example, the epitaxial source/drain regions  98  in the n-type region  50 N may include materials exerting a tensile strain on the channel regions  68 , such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions  98  in the n-type region  50 N may be referred to as “n-type source/drain regions.” The epitaxial source/drain regions  98  in the n-type region  50 N may have surfaces raised from respective surfaces of the fins  62  and the nanostructures  64 ,  66 , and may have facets. 
     The epitaxial source/drain regions  98  in the p-type region  50 P may be formed by masking the n-type region  50 N. Then, the epitaxial source/drain regions  98  in the p-type region  50 P are epitaxially grown in the source/drain recesses  94  in the p-type region  50 P. The epitaxial source/drain regions  98  may include any acceptable material appropriate for p-type devices. For example, the epitaxial source/drain regions  98  in the p-type region  50 P may include materials exerting a compressive strain on the channel regions  68 , such as silicon germanium, boron doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions  98  in the p-type region  50 P may be referred to as “p-type source/drain regions.” The epitaxial source/drain regions  98  in the p-type region  50 P may have surfaces raised from respective surfaces of the fins  62  and the nanostructures  64 ,  66 , and may have facets. 
     The epitaxial source/drain regions  98 , the nanostructures  64 ,  66 , and/or the fins  62  may be implanted with impurities to form source/drain regions, similar to the process previously described for forming LDD regions, followed by an anneal. The source/drain regions may have an impurity concentration in the range of about 10 19  cm −3  to about 10 21  cm −3 . The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously described. In some embodiments, the epitaxial source/drain regions  98  may be in situ doped during growth. 
     As a result of the epitaxy processes used to form the epitaxial source/drain regions  98 , upper surfaces of the epitaxial source/drain regions have facets which expand laterally outward beyond sidewalls of the fins  62  and the nanostructures  64 ,  66 . In some embodiments, these facets cause adjacent epitaxial source/drain regions  98  to merge as illustrated by  FIG. 9C . In some embodiments, adjacent epitaxial source/drain regions  98  remain separated after the epitaxy process is completed as illustrated by  FIG. 9D . In the illustrated embodiments, the spacer etch used to form the gate spacers  90  is adjusted to also form fin spacers  92  on sidewalls of the fins  62  and/or the nanostructures  64 ,  66 . The fin spacers  92  are formed to cover a portion of the sidewalls of the fins  62  and/or the nanostructures  64 ,  66  that extend above the STI regions  70 , thereby blocking the epitaxial growth. In another embodiment, the spacer etch used to form the gate spacers  90  is adjusted to not form fin spacers, so as to allow the epitaxial source/drain regions  98  to extend to the surface of the STI regions  70 . 
     The epitaxial source/drain regions  98  may include one or more semiconductor material layers. For example, the epitaxial source/drain regions  98  may each include a liner layer  98 A, a main layer  98 B, and a finishing layer  98 C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source/drain regions  98 . Each of the liner layer  98 A, the main layer  98 B, and the finishing layer  98 C may be formed of different semiconductor materials and may be doped to different impurity concentrations. In some embodiments, the liner layer  98 A may have a lesser concentration of impurities than the main layer  98 B, and the finishing layer  98 C may have a greater concentration of impurities than the liner layer  98 A and a lesser concentration of impurities than the main layer  98 B. In embodiments in which the epitaxial source/drain regions  98  include three semiconductor material layers, the liner layers  98 A may be grown in the source/drain recesses  94 , the main layers  98 B may be grown on the liner layers  98 A, and the finishing layers  98 C may be grown on the main layers  98 B. 
     In  FIGS. 10A-10B , a first inter-layer dielectric (ILD)  104  is deposited over the epitaxial source/drain regions  98 , the gate spacers  90 , the masks  86  (if present) or the dummy gates  84 . The first ILD  104  may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, or the like. Acceptable dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. 
     In some embodiments, a contact etch stop layer (CESL)  102  is formed between the first ILD  104  and the epitaxial source/drain regions  98 , the gate spacers  90 , and the masks  86  (if present) or the dummy gates  84 . The CESL  102  may be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a high etching selectivity from the etching of the first ILD  104 . The CESL  102  may be formed by an any suitable method, such as CVD, ALD, or the like. 
     In  FIGS. 11A-11B , a removal process is performed to level the top surfaces of the first ILD  104  with the top surfaces of the masks  86  (if present) or the dummy gates  84 . In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process may also remove the masks  86  on the dummy gates  84 , and portions of the gate spacers  90  along sidewalls of the masks  86 . After the planarization process, the top surfaces of the gate spacers  90 , the first ILD  104 , the CESL  102 , and the masks  86  (if present) or the dummy gates  84  are coplanar (within process variations). Accordingly, the top surfaces of the masks  86  (if present) or the dummy gates  84  are exposed through the first ILD  104 . In the illustrated embodiment, the masks  86  remain, and the planarization process levels the top surfaces of the first ILD  104  with the top surfaces of the masks  86 . 
     In  FIGS. 12A-12B , the masks  86  (if present) and the dummy gates  84  are removed in an etching process, so that recesses  106  are formed. Portions of the dummy dielectrics  82  in the recesses  106  are also removed. In some embodiments, the dummy gates  84  are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates  84  at a faster rate than the first ILD  104  or the gate spacers  90 . During the removal, the dummy dielectrics  82  may be used as etch stop layers when the dummy gates  84  are etched. The dummy dielectrics  82  are then removed. Each recess  106  exposes and/or overlies portions of the channel regions  68 . Portions of the second nanostructures  66  which act as the channel regions  68  are disposed between adjacent pairs of the epitaxial source/drain regions  98 . 
     The remaining portions of the first nanostructures  64  are then removed to expand the recesses  106 , such that openings  108  are formed in regions  501  between the second nanostructures  66 . The remaining portions of the first nanostructures  64  can be removed by any acceptable etching process that selectively etches the material of the first nanostructures  64  at a faster rate than the material of the second nanostructures  66 . The etching may be isotropic. For example, when the first nanostructures  64  are formed of silicon germanium and the second nanostructures  66  are formed of silicon, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH), or the like. In some embodiments, a trim process (not separately illustrated) is performed to decrease the thicknesses of the exposed portions of the second nanostructures  66 . As illustrated more clearly in  FIGS. 14A-16B  (subsequently described in greater detail), the remaining portions of the second nanostructures  66  can have rounded corners. 
     In  FIGS. 13A-13B , a gate dielectric layer  112  is formed in the recesses  106 . A gate electrode layer  114  is formed on the gate dielectric layer  112 . The gate dielectric layer  112  and the gate electrode layer  114  are layers for replacement gates, and each wrap around all (e.g., four) sides of the second nanostructures  66 . 
     The gate dielectric layer  112  is disposed on the sidewalls and/or the top surfaces of the fins  62 ; on the top surfaces, the sidewalls, and the bottom surfaces of the second nanostructures  66 ; and on the sidewalls of the gate spacers  90 . The gate dielectric layer  112  may also be formed on the top surfaces of the first ILD  104  and the gate spacers  90 . The gate dielectric layer  112  may include an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, combinations thereof, multi-layers thereof, or the like. The gate dielectric layer  112  may include a dielectric material having a k-value greater than about 7.0, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although a single-layered gate dielectric layer  112  is illustrated in  FIGS. 13A-13B , as will be subsequently described in greater detail, the gate dielectric layer  112  may include any number of interfacial layers and any number of main layers. 
     The gate electrode layer  114  may include a metal-containing material such as titanium nitride, titanium oxide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multi-layers thereof, or the like. Although a single-layered gate electrode layer  114  is illustrated in  FIGS. 13A-13B , as will be subsequently described in greater detail, the gate electrode layer  114  may include any number of work function tuning layers, any number of barrier layers, any number of glue layers, and a fill material. 
     The formation of the gate dielectric layers  112  in the n-type region  50 N and the p-type region  50 P may occur simultaneously such that the gate dielectric layers  112  in each region are formed of the same materials, and the formation of the gate electrode layers  114  may occur simultaneously such that the gate electrode layers  114  in each region are formed of the same materials. In some embodiments, the gate dielectric layers  112  in each region may be formed by distinct processes, such that the gate dielectric layers  112  may be different materials and/or have a different number of layers, and/or the gate electrode layers  114  in each region may be formed by distinct processes, such that the gate electrode layers  114  may be different materials and/or have a different number of layers. Various masking steps may be used to mask and expose appropriate regions when using distinct processes. In the following description, at least portions of the gate electrode layers  114  in the n-type region  50 N and the gate electrode layers  114  in the p-type region  50 P are formed separately. 
       FIGS. 14A-16B  illustrate a process in which gate dielectric layers  112  and gate electrode layers  114  for replacement gates are formed in the recesses  106  in the p-type region  50 P.  FIGS. 14A, 15A, and 16A  illustrate features in a region  50 A in  FIG. 13A .  FIGS. 14B, 15B, and 16B  illustrate features in a region  50 B in  FIG. 13B . The gate electrode layers  114  in the p-type region  50 P include work function tuning layer(s) formed of a tungsten-containing material. Tungsten is suitable for tuning the work function of the devices in the p-type region  50 P. Advantageously, forming the work function tuning layer(s) of a tungsten-containing material may allow the gate electrode layers  114  in the p-type region  50 P to have a lower resistance than gate electrode layers with work function tuning layers formed of a material that contains other metals (such as tantalum). Device performance may thus be improved. The n-type region  50 N may be masked at least while forming portions of the gate electrode layers  114  in the p-type region  50 P. 
     In  FIGS. 14A-14B , the gate dielectric layer  112  is formed in the recesses  106 . The gate dielectric layer  112  may also be deposited on the top surfaces of the first ILD  104  and the gate spacers  90  (see  FIG. 13B ). The formation methods of the gate dielectric layer  112  may include molecular-beam deposition (MBD), ALD, PECVD, and the like. The gate dielectric layer  112  wraps around all (e.g., four) sides of the second nanostructures  66 . The gate dielectric layer  112  fills portions of the regions  501  between the second nanostructures  66  in the p-type region  50 P (e.g., portions of the openings  108  in the p-type region  50 P). In the illustrated embodiment, the gate dielectric layer  112  is multi-layered, including an interfacial layer  112 A (or more generally, a first gate dielectric sub-layer) and an overlying high-k dielectric layer  112 B (or more generally, a second gate dielectric sub-layer). The interfacial layer  112 A may be formed of silicon oxide and the high-k dielectric layer  112 B may be formed of hafnium oxide. The gate dielectric layer  112  may include any acceptable quantity and combination of sub-layers. 
     In  FIGS. 15A-15B , a first work function tuning layer  114 A is optionally formed on the gate dielectric layer  112 , around the second nanostructures  66  in the p-type region  50 P. As will be subsequently described in greater detail, in some embodiments the first work function tuning layer  114 A is omitted. A second work function tuning layer  114 B is then formed on the first work function tuning layer  114 A (if present) or the gate dielectric layer  112 , around the second nanostructures  66  in the p-type region  50 P. 
     The first work function tuning layer  114 A (if present) is formed of a p-type work function material (PWFM) that is acceptable to tune a work function of a device to a desired amount given the application of the device to be formed, and may be deposited using any acceptable deposition process. Specifically, the first work function tuning layer  114 A is formed of a tungsten-free PWFM such as titanium nitride (TiN), tantalum nitride (TaN), combinations thereof, or the like, which may be deposited by ALD, CVD, PVD, or the like. The first work function tuning layer  114 A may also be referred to as a “tungsten-free work function tuning layer.” The first work function tuning layer  114 A may be included or omitted based on the desired work function of the result devices. The first work function tuning layer  114 A can have a thickness in the range of about 5 Å to about 60 Å. In the illustrated embodiment, the first work function tuning layer  114 A is a single continuous layer of a tungsten-free PWFM. In other embodiments, the first work function tuning layer  114 A is a multi-layer of tungsten-free PWFMs. The first work function tuning layer  114 A fills portions of the regions  501  between the second nanostructures  66  in the p-type region  50 P (e.g., portions of the openings  108  in the p-type region  50 P). 
     The second work function tuning layer  114 B is formed of a p-type work function material (PWFM) that has a low resistivity, and may be deposited using any acceptable deposition process. Specifically, the second work function tuning layer  114 B is formed of a tungsten-containing PWFM such as pure tungsten (e.g., fluorine-free tungsten), tungsten nitride, tungsten carbide, tungsten carbonitride, or the like, which may be deposited by ALD, CVD, PVD, or the like. The second work function tuning layer  114 B may also be referred to as a “tungsten-containing work function tuning layer.” The second work function tuning layer  114 B can have a thickness in the range of about 5 Å to about 60 Å. In the illustrated embodiment, the second work function tuning layer  114 B is a single continuous layer of a tungsten-containing PWFM. In other embodiments (subsequently described for  FIGS. 22A-23B ), the second work function tuning layer  114 B is a multi-layer of tungsten-containing PWFMs. The material of the second work function tuning layer  114 B may also be acceptable to tune a work function of a device to a desired amount (in a similar manner as the first work function tuning layer  114 A), but may have a lower resistivity than the material of the first work function tuning layer  114 A. Device performance may be improved by the use of PWFMs that have a low resistivity. 
     In some embodiments, the second work function tuning layer  114 B is formed of fluorine-free tungsten, which is deposited by an ALD process. Specifically, the second work function tuning layer  114 B may be formed by placing the substrate  50  in a deposition chamber and cyclically dispensing different source precursors into the deposition chamber. The source precursors include one or more tungsten source precursor(s) and one or more precursor(s) that react with the tungsten source precursor(s) to form fluorine-free tungsten. Fluorine-free tungsten is tungsten that is free of fluorine, and is deposited with a fluorine-free tungsten source precursor, e.g., a tungsten source precursor that is free of fluorine. Depositing tungsten with a fluorine-free tungsten source precursor avoids the undesired production of corrosive fluoride byproducts during deposition, which may increase manufacturing yield. 
     A first pulse of an ALD cycle is performed by dispensing a first precursor into the deposition chamber. The first precursor is a fluorine-free tungsten source precursor. Acceptable fluorine-free tungsten source precursors include tungsten(V) chloride (WCl 5 ) or the like. The first precursor can be kept in the deposition chamber for a duration in the range of about 0.2 seconds to about 5 seconds. The first precursor is then purged from the deposition chamber, such as by any acceptable vacuuming process and/or by flowing an inert gas into the deposition chamber. 
     A second pulse of the ALD cycle is performed by dispensing a second precursor into the deposition chamber. The second precursor is any acceptable precursor that reacts with the first precursor (e.g., the fluorine-free tungsten source precursor) to deposit fluorine-free tungsten. For example, when the first precursor is tungsten(V) chloride the second precursor may be hydrogen (H 2 ) or the like. The second precursor can be kept in the deposition chamber for a duration in the range of about 0.2 seconds to about 5 seconds. The second precursor is then purged from the deposition chamber, such as by any acceptable vacuuming process and/or by flowing an inert gas into the deposition chamber. 
     Each ALD cycle results in the deposition of an atomic layer (sometimes called a monolayer) of fluorine-free tungsten. For example, when the first precursor is tungsten(V) chloride and the second precursor is hydrogen, they may repeatedly react according to equations (1) and (2) to form gas-phase byproducts (which are purged from the deposition chamber) and fluorine-free tungsten. 
       WCl* X +H 2 →W−H*+HCl  (1)
 
       W−H*+WCl 5 →W−WCl* X +HCl  (2)
 
     The ALD cycles are repeated until fluorine-free tungsten is deposited to a desired thickness (previously described). For example, the ALD cycles can be repeated from about 1 to about 500 times. Further, the ALD process can be performed at a temperature in the range of about 300° C. to about 500° C. and at a pressure in the range of about 0.5 torr to about 50 torr, e.g., by maintaining the deposition chamber at such a temperature and pressure. Performing the ALD process with parameters in these ranges allows the fluorine-free tungsten to be formed to a desired thickness (previously described) and quality. Performing the ALD process with parameters outside of these ranges may not allow the fluorine-free tungsten to be formed to the desired thickness or quality. 
     In some embodiments, the second work function tuning layer  114 B is formed of tungsten nitride, which is deposited by ALD. The tungsten nitride may be formed by a similar ALD process as that previously described for forming fluorine-free tungsten, except different precursors may be used. For example, the first precursor may be a tungsten source precursor (which may or may not be fluorine-free), and the second precursor may be a nitrogen source precursor that reacts with the first precursor (e.g., the tungsten source precursor) to deposit tungsten nitride. Acceptable tungsten source precursors for depositing tungsten nitride include bis(tert-butylimino)-bis-(dimethylamido)tungsten (( t BuN) 2 (Me 2 N) 2 W) or the like. Acceptable nitrogen source precursors for depositing tungsten nitride include ammonia (NH 3 ) or the like. 
     The ALD cycles are repeated until tungsten nitride is deposited to a desired thickness (previously described). For example, the ALD cycles can be repeated from about 1 to about 500 times. Further, the ALD process can be performed at a temperature in the range of about 200° C. to about 450° C. and at a pressure in the range of about 0.1 torr to about 60 torr, e.g., by maintaining the deposition chamber at such a temperature and pressure. Performing the ALD process with parameters in these ranges allows the tungsten nitride to be formed to a desired thickness (previously described) and quality. Performing the ALD process with parameters outside of these ranges may not allow the tungsten nitride to be formed to the desired thickness or quality. 
     The second work function tuning layer  114 B fills the remaining portions of the regions  501  between the second nanostructures  66  in the p-type region  50 P (e.g., the remaining portions of the openings  108  in the p-type region  50 P). Specifically, the second work function tuning layer  114 B is deposited on the first work function tuning layer  114 A (if present) or the gate dielectric layer  112  until it is thick enough to merge and seam together. In embodiments where the first work function tuning layer  114 A is present, it can have a lesser thickness than the second work function tuning layer  114 B, which may avoid merging of the first work function tuning layer  114 A and promote merging of the second work function tuning layer  114 B. Interfaces  118  may be formed by the contacting of adjacent portions of the second work function tuning layer  114 B (e.g., those portions around the second nanostructures  66  in the p-type region  50 P). The openings  108  in the p-type region  50 P are thus completely filled by respective portions of the gate dielectric layer  112 , the first work function tuning layer  114 A (if present), and the second work function tuning layer  114 B. Specifically, respective portions of the gate dielectric layer  112  wrap around respective second nanostructures  66  in the p-type region  50 P, respective portions of the first work function tuning layer  114 A wrap around the respective portions of the gate dielectric layer  112 , and respective portions of the second work function tuning layer  114 B wrap around the respective portions of the first work function tuning layer  114 A, thereby completely filling areas between the respective second nanostructures  66 . When the second work function tuning layer  114 B is a single continuous layer of a tungsten-free PWFM, the tungsten-free PWFM extends continuously between the respective portions of the first work function tuning layer  114 A (if present) or the respective portions of the dielectric layer  112 . As noted above, the first work function tuning layer  114 A is a tungsten-free layer. No tungsten-containing layers are disposed between the second work function tuning layer  114 B and the second nanostructures  66  in the p-type region. 
     In  FIGS. 16A-16B , a fill layer  114 E is deposited on the second work function tuning layer  114 B. Optionally, a glue layer  114 D is formed between the fill layer  114 E and the second work function tuning layer  114 B. After formation is complete, the gate electrode layers  114  in the p-type region  50 P includes the first work function tuning layer  114 A, the second work function tuning layer  114 B, the glue layer  114 D, and the fill layer  114 E. 
     The glue layer  114 D includes any acceptable material to promote adhesion and prevent diffusion. For example, the glue layer  114 D may be formed of a metal or metal nitride such as titanium nitride, titanium aluminide, titanium aluminum nitride, silicon-doped titanium nitride, tantalum nitride, or the like, which may be deposited by ALD, CVD, PVD, or the like. 
     The fill layer  114 E includes any acceptable material of a low resistance. For example, the fill layer  114 E may be formed of a metal such as tungsten, aluminum, cobalt, ruthenium, combinations thereof or the like, which may be deposited by ALD, CVD, PVD, or the like. The fill layer  114 E fills the remaining portions of the recesses  106 . 
       FIG. 17A-17B  illustrate gate dielectric layers  112  and gate electrode layers  114  for replacement gates, which are formed in the recesses  106  in the n-type region  50 N.  FIG. 17A  illustrates features in a region  50 A in  FIG. 13A .  FIG. 17B  illustrates features in a region  50 B in  FIG. 13B . In some embodiments, the gate dielectric layers  112  in the n-type region  50 N and the p-type region  50 P may be formed simultaneously. Further, at least portions of the gate electrode layers  114  in the n-type region  50 N may be formed either before or after forming the gate electrode layers  114  in the p-type region  50 P, and at least portions of the gate electrode layers  114  in the n-type region  50 N may be formed while the p-type region  50 P is masked. As such, the gate electrode layers  114  in the n-type region  50 N may include different materials than the gate electrode layers  114  in the p-type region  50 P. For example, the gate electrode layers  114  in the n-type region  50 N may include a third work function tuning layer  114 C, a glue layer  114 D, and a fill layer  114 E. As will be subsequently described in greater detail, the third work function tuning layer  114 C has a different material composition from the first work function tuning layer  114 A and the second work function tuning layer  114 B. The glue layer  114 D in the n-type region  50 N may (or may not) have a same material composition as (and be deposited concurrently with) the glue layer  114 D in the p-type region  50 P. The fill layer  114 E in the n-type region  50 N may (or may not) have a same material composition as (and be deposited concurrently with) the fill layer  114 E in the p-type region  50 P. 
     The third work function tuning layer  114 C is formed of an n-type work function material (NWFM) that is acceptable to tune a work function of a device to a desired amount given the application of the device to be formed, and may be deposited using any acceptable deposition process. Specifically, the third work function tuning layer  114 C is formed of a tungsten-free NWFM such as titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, or the like, which may be deposited by ALD, PEALD, PVD, CVD, PECVD, or the like. The material of the third work function tuning layer  114 C is different than the material of the first work function tuning layer  114 A and the material of the second work function tuning layer  114 B. In some embodiments, the first work function tuning layer  114 A may be formed of titanium nitride, the second work function tuning layer  114 B may be formed of fluorine-free tungsten or tungsten nitride, and the third work function tuning layer  114 C may be formed of titanium aluminum. 
     The material of the third work function tuning layer  114 C may also have a low resistivity (in a similar manner as the second work function tuning layer  114 B). The material of the third work function tuning layer  114 C may have a lower resistivity than the material of the first work function tuning layer  114 A. Device performance may be improved by the use of NWFMs that have a low resistivity. The material of the third work function tuning layer  114 C may have a higher resistivity or a lower resistivity than the material of the second work function tuning layer  114 B. In some embodiments, the material of the third work function tuning layer  114 C has a lower resistivity than the material of the first work function tuning layer  114 A and a higher resistivity than the material of the second work function tuning layer  114 B. 
     The third work function tuning layer  114 C fills the remaining portions of the regions  501  between the second nanostructures  66  in the n-type region  50 N (e.g., the remaining portions of the openings  108  in the n-type region  50 N). Specifically, the third work function tuning layer  114 C is deposited on the gate dielectric layer  112  until it is thick enough to merge and seam together. Interfaces  120  may be formed by the contacting of adjacent portions of the third work function tuning layer  114 C (e.g., those portions around the second nanostructures  66  in the n-type region  50 N). Respective portions of the gate dielectric layer  112  wrap around respective second nanostructures  66  in the n-type region  50 N, and respective portions of the third work function tuning layer  114 C wrap around the respective portions of the gate dielectric layer  112 , thereby completely filling areas between the respective second nanostructures  66 . 
     In  FIGS. 18A-18B , a removal process is performed to remove the excess portions of the materials of the gate dielectric layer  112  and the gate electrode layer  114 , which excess portions are over the top surfaces of the first ILD  104  and the gate spacers  90 , thereby forming gate dielectrics  122  and gate electrodes  124 . In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The gate dielectric layer  112 , when planarized, has portions left in the recesses  106  (thus forming the gate dielectrics  122 ). The gate electrode layer  114 , when planarized, has portions left in the recesses  106  (thus forming the gate electrodes  124 ). The top surfaces of the gate spacers  90 ; the CESL  102 ; the first ILD  104 ; the gate dielectrics  122  (e.g., the interfacial layers  112 A and the high-k dielectric layers  112 B, see  FIGS. 14A-17B ); and the gate electrodes  124  (e.g., the work function tuning layers  114 A,  114 B,  114 C, the glue layer  114 D (if present), and the fill layer  114 E, see  FIGS. 14A-17B ) are coplanar (within process variations). The gate dielectrics  122  and the gate electrodes  124  form replacement gates of the resulting nano-FETs. Each respective pair of a gate dielectric  122  and a gate electrode  124  may be collectively referred to as a “gate structure.” The gate structures each extend along top surfaces, sidewalls, and bottom surfaces of a channel region  68  of the second nanostructures  66 . 
     In  FIGS. 19A-19B , a second ILD  134  is deposited over the gate spacers  90 , the CESL  102 , the first ILD  104 , the gate dielectrics  122 , and the gate electrodes  124 . In some embodiments, the second ILD  134  is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD  134  is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, which may be deposited by any suitable method, such as CVD, PECVD, or the like. 
     In some embodiments, an etch stop layer (ESL)  132  is formed between the second ILD  134  and the gate spacers  90 , the CESL  102 , the first ILD  104 , the gate dielectrics  122 , and the gate electrodes  124 . The ESL  132  may include a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a high etching selectivity from the etching of the second ILD  134 . 
     In  FIGS. 20A-20B , gate contacts  142  and source/drain contacts  144  are formed to contact, respectively, the gate electrodes  124  and the epitaxial source/drain regions  98 . The gate contacts  142  are physically and electrically coupled to the gate electrodes  124 . The source/drain contacts  144  are physically and electrically coupled to the epitaxial source/drain regions  98 . 
     As an example to form the gate contacts  142  and the source/drain contacts  144 , openings for the gate contacts  142  are formed through the second ILD  134  and the ESL  132 , and openings for the source/drain contacts  144  are formed through the second ILD  134 , the ESL  132 , the first ILD  104 , and the CESL  102 . The openings may be formed using acceptable photolithography and etching techniques. A liner (not separately illustrated), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD  134 . The remaining liner and conductive material form the gate contacts  142  and the source/drain contacts  144  in the openings. The gate contacts  142  and the source/drain contacts  144  may be formed in distinct processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the gate contacts  142  and the source/drain contacts  144  may be formed in different cross-sections, which may avoid shorting of the contacts. 
     Optionally, metal-semiconductor alloy regions  146  are formed at the interfaces between the epitaxial source/drain regions  98  and the source/drain contacts  144 . The metal-semiconductor alloy regions  146  can be silicide regions formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed of a metal germanide (e.g. titanium germanide, cobalt germanide, nickel germanide, etc.), silicon-germanide regions formed of both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy regions  146  can be formed before the material(s) of the source/drain contacts  144  by depositing a metal in the openings for the source/drain contacts  144  and then performing a thermal anneal process. The metal can be any metal capable of reacting with the semiconductor materials (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source/drain regions  98  to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys. The metal can be deposited by a deposition process such as ALD, CVD, PVD, or the like. After the thermal anneal process, a cleaning process, such as a wet clean, may be performed to remove any residual metal from the openings for the source/drain contacts  144 , such as from surfaces of the metal-semiconductor alloy regions  146 . The material(s) of the source/drain contacts  144  can then be formed on the metal-semiconductor alloy regions  146 . 
       FIGS. 21A-21B  are views of nano-FETs, in accordance with some other embodiments. This embodiment is similar to the embodiment described for  FIGS. 16A-16B , except the first work function tuning layer  114 A is omitted. Thus, the openings  108  in the p-type region  50 P are completely filled by respective portions of the gate dielectric layer  112  and the second work function tuning layer  114 B. In the illustrated embodiment, the second work function tuning layer  114 B is a single continuous layer of a tungsten-containing PWFM such that the tungsten-containing PWFM extends continuously between the respective portions of the dielectric layer  112 . 
       FIGS. 22A-23B  are views of nano-FETs, in accordance with some other embodiments. These embodiments are similar to the embodiment described for  FIGS. 21A-21B , except the second work function tuning layer  114 B is a multi-layer of tungsten-containing PWFMs. Although  FIGS. 22A-23B  show embodiments where the first work function tuning layer  114 A is omitted, it should be appreciated that in other embodiments the first work function tuning layer  114 A is included. In some embodiments, the second work function tuning layer  114 B is a bi-layer of tungsten-containing PWFMs, including a first work function tuning sub-layer  114 B 1  and a second work function tuning sub-layer  114 B 2  on the first work function tuning sub-layer  114 B 1 , as illustrated by  FIGS. 22A-22B . In some embodiments, the second work function tuning layer  114 B is a tri-layer of tungsten-containing PWFMs, which is similar to a bi-layer but further includes a third work function tuning sub-layer  114 B 3  on the second work function tuning sub-layer  114 B 2 , as illustrated by  FIGS. 23A-23B . Each of the sub-layers is a single continuous layer of a different tungsten-containing PWFM. The tungsten-containing material of the first work function tuning sub-layer  114 B 1  may (or may not) be the same as the tungsten-containing material of the third work function tuning sub-layer  114 B 3 . In some embodiments, the first work function tuning sub-layer  114 B 1  is fluorine-free tungsten, the second work function tuning sub-layer  114 B 2  is tungsten nitride, and the third work function tuning sub-layer  114 B 3  (if present) is fluorine-free tungsten. In some embodiments, the first work function tuning sub-layer  114 B 1  is tungsten nitride, the second work function tuning sub-layer  114 B 2  is fluorine-free tungsten, and the third work function tuning sub-layer  114 B 3  (if present) is tungsten nitride. 
     When the second work function tuning layer  114 B is a multi-layer of tungsten-containing PWFMs, the sub-layers of tungsten-containing PWFMs are deposited so that the lower sub-layer of the second work function tuning layer  114 B (e.g., the first work function tuning sub-layer  114 B 1 ) merges and seams together. For example, the lower sub-layer of the second work function tuning layer  114 B may have a greater thickness than each of the upper sub-layer(s) of the second work function tuning layer  114 B (e.g., the third work function tuning sub-layer  114 B 3  (if present) and the second work function tuning sub-layer  114 B 2 ), which may avoid merging of the upper sub-layer(s) and promote merging of the lower sub-layer. 
     Some embodiments contemplate the use of other tungsten-containing PWFMs. For example, although some of the previously-described embodiments use tungsten nitride for a tungsten-containing PWFM, carbides of tungsten may also be used. In some embodiments, tungsten carbide and/or tungsten carbonitride may be used in lieu of (or in addition to) tungsten nitride. 
     Embodiments may achieve advantages. Tungsten is suitable for tuning the work function of the devices in the p-type region  50 P. Forming the second work function tuning layer  114 B of a tungsten-containing PWFM allows the threshold voltages of the resulting devices to be tuned. Further, tungsten-containing PWFMs have a low resistivity. Forming the second work function tuning layer  114 B of a tungsten-containing PWFM allows the gate electrodes  124  in the p-type region  50 P to have a lower resistance than gate electrodes with work function tuning layers formed of a PWFM that contains other metals (such as tantalum). Device performance may thus be improved. 
     In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric layer wrapped around the first nanostructure and the second nanostructure; a tungsten-free work function tuning layer wrapped around the gate dielectric layer; a tungsten-containing work function tuning layer wrapped around the tungsten-free work function tuning layer, an area between the first nanostructure and the second nanostructure being completely filled by respective portions of the tungsten-containing work function tuning layer, the tungsten-free work function tuning layer, and the gate dielectric layer; and a fill layer on the tungsten-containing work function tuning layer. In some embodiments of the device, a first material of the tungsten-containing work function tuning layer has a lower resistivity than a second material of the tungsten-free work function tuning layer. In some embodiments of the device, the tungsten-containing work function tuning layer includes fluorine-free tungsten. In some embodiments of the device, the tungsten-containing work function tuning layer includes tungsten nitride, tungsten carbide, or tungsten carbonitride. In some embodiments of the device, the tungsten-containing work function tuning layer is a single continuous layer of a tungsten-containing material. In some embodiments of the device, the tungsten-containing work function tuning layer includes: a first layer of a first tungsten-containing material wrapped around the tungsten-free work function tuning layer; and a second layer of a second tungsten-containing material wrapped around the first layer of the first tungsten-containing material, the second tungsten-containing material different from the first tungsten-containing material. In some embodiments of the device, the tungsten-containing work function tuning layer further includes: a third layer of the first tungsten-containing material wrapped around the second layer of the second tungsten-containing material. 
     In an embodiment, a device includes: a p-type transistor including: a first channel region; a first gate dielectric layer on the first channel region; a tungsten-containing work function tuning layer on the first gate dielectric layer; and a first fill layer on the tungsten-containing work function tuning layer; and an n-type transistor including: a second channel region; a second gate dielectric layer on the second channel region; a tungsten-free work function tuning layer on the second gate dielectric layer; and a second fill layer on the tungsten-free work function tuning layer. In some embodiments of the device, no tungsten-containing layers are disposed between the first channel region and the tungsten-containing work function tuning layer. In some embodiments of the device, the tungsten-containing work function tuning layer includes fluorine-free tungsten or tungsten nitride, and the tungsten-free work function tuning layer includes titanium aluminum. 
     In an embodiment, a method includes: forming a gate dielectric layer having a first portion wrapped around a first nanostructure; depositing a first tungsten-free work function material on the first portion of the gate dielectric layer; depositing a tungsten-containing work function material on the first tungsten-free work function material, the tungsten-containing work function material having a lower resistivity than the first tungsten-free work function material; and depositing a fill layer on the tungsten-containing work function material. In some embodiments of the method, depositing the tungsten-containing work function material includes: depositing fluorine-free tungsten by an ALD process, the ALD process performed with tungsten(V) chloride and hydrogen, the ALD process performed at a temperature in a range of 300° C. to 500° C., the ALD process performed at a pressure in a range of 0.5 torr to 50 torr. In some embodiments of the method, depositing the tungsten-containing work function material includes: depositing tungsten nitride by an ALD process, the ALD process performed with bis(tert-butylimino)-bis-(dimethylamido)tungsten and ammonia, the ALD process performed at a temperature in a range of 200° C. to 450° C., the ALD process performed at a pressure in a range of 0.1 torr to 60 torr. In some embodiments of the method, depositing the tungsten-containing work function material includes: depositing a single continuous layer of the tungsten-containing work function material. In some embodiments of the method, depositing the tungsten-containing work function material includes: depositing a multi-layer of tungsten-containing work function materials. In some embodiments of the method, the gate dielectric layer has a second portion wrapped around a second nanostructure, the method further including: depositing a second tungsten-free work function material on the second portion of the gate dielectric layer, the second tungsten-free work function material different from the first tungsten-free work function material; and depositing the fill layer on the second tungsten-free work function material. In some embodiments, the method further includes: growing p-type source/drain regions on a substrate, the first nanostructure disposed between the p-type source/drain regions; and growing n-type source/drain regions on the substrate, the second nanostructure disposed between the n-type source/drain regions. In some embodiments of the method, the second tungsten-free work function material has a lower resistivity than the first tungsten-free work function material and a higher resistivity than the tungsten-containing work function material. In some embodiments of the method, the first tungsten-free work function material includes titanium nitride, the tungsten-containing work function material includes fluorine-free tungsten or tungsten nitride, and the second tungsten-free work function material includes titanium aluminum. In some embodiments of the method, the first tungsten-free work function material is deposited to a first thickness, and the tungsten-containing work function material is deposited to a second thickness, the second thickness greater than the first thickness. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.