Patent Publication Number: US-10326416-B2

Title: Amplifier

Description:
TECHNICAL FIELD 
     An aspect of the present invention relates to an amplifier that amplifies an input signal. 
     BACKGROUND 
     An optical receiver for use in an optical communication system includes, for example, a photodetector, a transimpedance amplifier (TIA), and a feedback amplifier (amplifier). As the photodetector, a photodiode is used. The photodetector converts an optical signal into an electrical signal (photocurrent). The TIA converts the photocurrent (a current signal) output from the photodetector into a voltage signal. The feedback amplifier automatically controls an offset of the TIA (automatic offset control). U.S. Pat. No. 7,230,476 discloses a feedback amplifier including a diode, a differential amplifier (operational amplifier), and a capacitor. The diode is reverse-biased and connected between an input terminal of the feedback amplifier and the operational amplifier. The capacitor is connected between an input and an output of the operational amplifier to configure a feedback loop. Large resistance of the reverse-biased diode and large capacitance of the feedbacked capacitor provides a low pass filter with a low cutoff frequency. The low pass filter stabilizes automatic control of an offset of the feedback amplifier. Further increasing of an input impedance of the feedback amplifier to lower the cutoff frequency reduces an input current of the operational amplifier. The differential amplifier with a Darlington connection has the advantage of amplifying such a small input current, but requires a relatively large supply voltage that prevents the differential amplifier from reducing power dissipation thereof. 
     SUMMARY 
     An amplifier according to an aspect of the present invention is an amplifier that amplifies a differential signal between two input signals, and includes a first input terminal for receiving one of the two input signals; a second input terminal for receiving another of the two input signals; a first diode having an anode and a cathode, the anode being electrically coupled to the first input terminal; a second diode having an anode and a cathode, the anode being electrically coupled to the second input terminal; a first bias current source electrically connected to the cathode of the first diode, the first bias current source being configured to supply a first current to the first diode element; a second bias current source electrically connected to the cathode of the second diode, the second bias current source being configured to supply a second current to the second diode element; an operational amplifier including a non-inverting input, an inverting input, and a non-inverting output, the non-inverting input being connected to the cathode of the first diode, the inverting input being connected to the cathode of the second diode, the operational amplifier being configured to amplify a differential signal between a signal generated at the cathode of the first diode and a signal generated at the cathode of the second diode, the non-inverting output being configured to output an amplified differential signal; a feedback capacitive element electrically connected between the inverting input and the non-inverting output of the operational amplifier; and a differential amplifier being provided between the operational amplifier and the first input terminal and the second input terminal, the differential amplifier including a bipolar transistor pair amplifying the two input signals, wherein the first and second bias current sources include a current mirror circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of a transimpedance amplifier including an amplifier according to an embodiment. 
         FIG. 2  is a circuit diagram illustrating a detailed configuration of the amplifier according to the embodiment. 
         FIG. 3  is a circuit diagram illustrating a detailed configuration of an amplifier according to a variation of the amplifier according to the embodiment. 
         FIG. 4  is a circuit diagram of an amplifier according to a comparative example. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and duplicate description thereof is omitted. 
       FIG. 1  is a circuit diagram of a transimpedance amplifier including an amplifier according to an embodiment. The transimpedance amplifier  1  illustrated in  FIG. 1  is used for an optical receiver in an optical communication system. The transimpedance amplifier  1  is a circuit that converts a current signal (photocurrent) output from a photodetector into a voltage signal. The photodetector is, for example, a photodiode. The transimpedance amplifier  1  includes an input terminal IN, a conversion circuit  10 , a differential amplifier  20 , a feedback amplifier (an amplifier)  30 , a low pass filter  40 , a current source (a bypass circuit)  50 , and output terminals OUTP and OUTN. 
     The conversion circuit  10  includes an amplifier  10   a  and a resistive element  10   b . The input terminal IN is electrically connected to an input of the amplifier  10   a , and the resistive element  10   b  is connected between the input and an output of the amplifier  10   a . The amplifier  10   a  is, for example, an inverting amplifier circuit. The resistive element  10   b  feeds back an output signal of the amplifier  10   a  to the input of the amplifier  10   a . The conversion circuit  10  converts the input current signal into a voltage signal. The input current signal is described later 
     The differential amplifier  20  includes two inputs and two outputs. One input (for example, an inverting input) of the differential amplifier  20  is electrically connected to the output of the amplifier  10   a  and receives the voltage signal from the amplifier  10   a . A reference voltage Vref is input to another input (for example, a non-inverting input) of the differential amplifier  20 . One output (for example, a non-inverting output) of the differential amplifier is electrically connected to the output terminal OUTP. Another output (for example, an inverting output) of the differential amplifier is electrically connected to the output terminal OUTN. The differential amplifier  20  amplifies a differential signal and outputs a differential output signal to the output terminals OUTP and OUTN. The differential signal corresponds to a difference in voltage between the voltage signal output from the conversion circuit  10  and the reference voltage Vref. For example, the signal output from the output terminal OUTP is a positive phase component (a positive phase signal) of the differential output signal, and the signal output from the output terminal OUTN is a negative phase component (a negative phase signal) of the differential output signal. The positive phase signal has a phase opposite to a phase of the negative phase signal. That is, when the positive phase signal increases, the negative phase signal decreases, and conversely, when the positive phase signal decreases, the negative phase signal increases. In addition, when one of the signals has a peak value (or a high level of a binary signal), another has a bottom value (or a low level of the binary signal). An amplitude of the positive phase signal is substantially equal to an amplitude of the negative phase signal. 
     The feedback amplifier  30  amplifies the differential output signal and outputs the amplified differential signal as a control signal for the current source  50  (a bypass circuit) via the low pass filter  40 . 
     The current source  50  generates a variable current (a bypass current) according to the amplified differential signal generated by the feedback amplifier  30 , and subtracts (bypasses) the bypass current from the input current (the photocurrent) input to the input terminal IN. A remainder after subtracting the bypass current from the input current (the photocurrent) is the above-mentioned input current signal. The input current signal is input to the conversion circuit  10 . 
     With such a circuit configuration, automatic offset control for reducing an offset (an output offset) between the positive phase signal and the negative phase signal output from the output terminals OUTP and OUTN is provided. Here, reducing the output offset in the transimpedance amplifier  1  and amplifying a broadband signal requires a large gain of the feedback amplifier  30  (for example, to 60 dB or more) and a lower cutoff frequency thereof (for example, to about 10 to 100 Hz). 
     Next, a detailed configuration of the feedback amplifier  30  will be described.  FIG. 2  is a circuit diagram illustrating a configuration of the feedback amplifier  30  according to the embodiment. The feedback amplifier  30  illustrated in  FIG. 2  is, for example, a circuit formed through a semiconductor process for SiGe bipolar complementary metal oxide semiconductor (BiCMOS). The feedback amplifier  30  includes input terminals INP and INN, an output terminal OUT, an input filter  51 , a differential amplifier  52 , a diode pair  53 , a bias current source  54 , a current mirror circuit portion  55 , an operational amplifier  56 , and a capacitive element (miller capacitance)  57 . 
     The input terminals INP and INN receive a differential signal. For example, the input terminal INP receives a positive phase component (a positive phase signal) of the differential signal, and the input terminal INN receives a negative phase component (a negative phase signal) of the differential signal. 
     The input filter  51  is, for example, an RC filter including a resistive element and a capacitor. The RC filter is a low pass filter. 
     The output terminal OUT outputs an output signal generated according to a difference between the positive phase signal input to the input terminal INP and the negative phase signal input to the input terminal INN. The output signal may be a positive phase component of a differential output signal output from the operational amplifier. 
     The input filter  51  is provided between the input terminals INP and INN and the diode pair  53 . The input filter  51  includes, for example, resistive elements  61   a  and  61   b  and a capacitive element  62 . One end of the resistive element  61   a  is electrically connected to the input terminal INP, and one end of the resistive element  61   b  is electrically connected to the input terminal INN. The capacitive element  62  is electrically connected between another end of the resistive element  61   a  and another end of the resistive element  61   b . The input filter  51  functions as a low pass filter that passes low-frequency components of the positive phase signal and the negative phase signal. 
     The differential amplifier  52  is, for example, a differential amplifier including a bipolar transistor pair. The differential amplifier  52  is provided between the operational amplifier  56  and the input terminals INP and INN. The differential amplifier  52  includes, for example, bipolar transistors  63   a  and  63   b , resistive elements  64   a ,  64   b ,  64   c , and  64   d , and a current source  65 . A base of the bipolar transistor  63   a  is electrically connected to the other end of the resistive element  61   a . A collector of the bipolar transistor  63   a  is electrically connected to a supply line (a first supply line) via a resistive element  64   a , and a positive supply voltage VCC (a first supply voltage) is applied to the collector. A base of the bipolar transistor  63   b  is electrically connected to the other end of the resistive element  61   b . A collector of the bipolar transistor  63   b  is electrically connected to the supply line via the resistive element  64   b  and the supply voltage VCC is applied thereto. Further, the respective emitters of the bipolar transistors  63   a  and  63   b  are electrically connected to one end of the current source  65 . Another end of the current source  65  is electrically connected to the-supply line (a second supply line), and a negative power supply voltage VEE (a second supply voltage) is applied thereto. It should be noted that the other end of the current source  65  may be electrically connected to a ground line in place of the negative power supply voltage VEE. 
     This differential amplifier  52  amplifies the difference (the differential signal) in voltage between the positive phase signal and the negative phase signal each passing through the input filter  51  and outputs the negative phase signal of the amplified differential signal from the collector of the transistor  63   a . One end of the resistive element  64   c  is electrically connected to the collector of the transistor  63   a , and one end of the resistive element  64   d  is electrically connected to the collector of the transistor  63   b . The respective other ends of the resistive elements  64   c  and  64   d  are connected to each other and output an average value of the negative phase signal output from the collector of the transistor  63   a  and the positive phase signal output from the collector of the transistor  63   b.    
     A positive phase signal is input from the input terminal INP to the base of the transistor  63   a  via the resistive element  61   a . When a voltage of the positive phase signal increases and the transistor  63   a  turns on, a collector current flows, a voltage drop of the resistive element  64   a  increases, and a potential of the collector of the transistor  63   a  decreases (falls). Therefore, a signal output from the collector of the transistor  63   a  corresponds to a signal obtained by inverting the signal input to the base of the transistor  63   a . For example, when the positive phase signal is input to the base of the transistor  63   a , the signal output from the collector of the transistor  63   a  corresponds to the negative phase signal. 
     On the other hand, the negative phase signal is input from the input terminal INN to the base of the transistor  63   b  via the resistive element  61   b . When a voltage of the negative phase signal increases and the transistor  63   b  turns on, a collector current flows, a voltage drop of the resistive element  64   b  increases, and a potential of the collector of the transistor  63   b  decreases (falls). Therefore, a signal output from the collector of the transistor  63   b  corresponds to a signal obtained by inverting the signal input to the base of the transistor  63   b . For example, when the negative phase signal is input to the base of the transistor  63   b , the signal output from the collector of the transistor  63   b  corresponds to the positive phase signal. Accordingly, the differential amplifier  52  behaves like an inverting amplifier in the configuration. 
     It should be noted that the resistive elements  64   c  and  64   d  are set to have the same resistance value. With such a configuration, the collector of the transistor  63   b  generates the positive phase signal that has a phase opposite to a phase of the negative phase signal output from the collector of the transistor  63   a . Therefore, the other ends of the resistive elements  64   c  and  64   d  connected to each other generate an intermediate potential between the positive phase signal and the negative phase signal, which corresponds to the average value of the positive phase signal and the negative phase signal. 
     It should be noted that a smaller voltage difference between the supply voltage VCC and the supply voltage VEE causes a lower power dissipation of the amplifier  30 , and therefore, in order to reduce the power dissipation of the amplifier  30 , it is preferable for the voltage difference between the supply voltage VCC and the power supply voltage VEE to be set to a smaller value as long as the amplifier  30  operates normally. 
     The diode pair  53  includes two bipolar transistors  66   a  and  66   b . A base and a collector of the bipolar transistor  66   a  are electrically connected to the collector of the bipolar transistor  63   a  in common. Further, a base and a collector of the bipolar transistor  66   b  are electrically connected to the other ends of the resistive elements  64   c  and  64   d  in common. The bipolar transistors  66   a  and  66   b  both behave as diode elements due to a connection form (a diode connection) in which a base of a certain bipolar transistor is connected to a collector of the bipolar transistor as described above, the base and the collector of the bipolar transistors  66   a  and  66   b  function as an anode of the diode element, and an emitter of the bipolar transistors  66   a  and  66   b  functions as a cathode of the diode element. When a minute current is supplied from the bias current source  54  to the bipolar transistors  66   a  and  66   b , the bipolar transistors  66   a  and  66   b  provide high resistances like reversed-biased diode elements. 
     An emitter of the bipolar transistor  66   a  outputs a voltage signal shifted downward from the negative phase signal output from the bipolar transistor  63   a  by a voltage drop generated between the collector and the emitter of the bipolar transistor  66   a . Further, an emitter of the bipolar transistor  66   b  outputs a voltage signal shifted downward from the average value output from the other end of the resistive elements  64   c  and  64   d  by a voltage drop generated between the collector and the emitter of the bipolar transistor  66   b . It should be noted that the bipolar transistors  66   a  and  66   b  are set to have the same electrical characteristics for providing the same voltage drop. 
     The bias current source  54  includes two bipolar transistors  67   a  and  67   b . A collector of the bipolar transistor  67   a  is electrically connected to the emitter (corresponding to the cathode of the diode) of the bipolar transistor  66   a . The supply voltage VEE is applied to the emitter of the bipolar transistor  67   a . A collector of the bipolar transistor  67   b  is electrically connected to the emitter (corresponding to the cathode of the diode) of the bipolar transistor  66   b . The supply voltage VEE is applied to an emitter of the bipolar transistor  67   b . The bipolar transistors  67   a  and  67   b  operate as bias current sources. The bipolar transistors  67   a  supplies a minute current that flows from the collector to the emitter of the bipolar transistors  66   a  with the diode connection. The bipolar transistors  67   b  supplies a minute current that flows from the collector to the emitter of the bipolar transistors  66   b  with the diode connection. Each minute current is adjusted in accordance with a control signal generated by the current mirror circuit portion  55  by connecting bases of the bipolar transistors  67   a  and  67   b  to a base of a bipolar transistor  70  in the current mirror circuit portion  55 . 
     It should be noted that the voltage of the supply voltage VEE (a second supply voltage) may be lower than the voltage of the supply voltage VCC (a first supply voltage), and does not necessarily have to be a negative voltage. For example, when the supply voltage VCC is positive, the supply voltage VEE may be a ground potential. 
     The current mirror circuit portion  55  includes a pair of transistors  68   a  and  68   b  which are n-type metal oxide semiconductor field effect transistors (MOSFETs), a pair of transistors  69   a  and  69   b  which are p-type MOSFETs, and a bipolar transistor  70 . 
     A gate and a drain of the transistor  68   a  are connected to an input terminal IN 0  in common, and the supply voltage VEE is applied to a source of the transistor  68   a . A reference current I 0  is input from the outside to the input terminal IN 0  (a current setting terminal). A gate of the transistor  68   b  is electrically connected to the gate and the drain of the transistor  68   a  to constitute a current mirror circuit (first current mirror circuit). The supply voltage VEE is applied to a source of the transistor  68   b.    
     Further, a gate and a drain of the transistor  69   a  are electrically connected to the drain of the transistor  68   b  in common. The supply voltage VCC is applied to a source of the transistor  69   a . A gate of the transistor  69   b  is electrically connected to the gate and the drain of the transistor  69   a  to constitute another current mirror circuit (second current mirror circuit). The supply voltage VCC is applied to a source of the transistor  69   b.    
     In addition, a base and a collector of the bipolar transistor  70  are electrically connected to the drain of the transistor  69   b  in common. The supply voltage VEE is applied to an emitter of the bipolar transistor  70 . Further, the base and the collector of the bipolar transistor  70  are also connected to the bases of the bipolar transistors  67   a  and  67   b  of the bias current source  54  to duplicate the respective minute currents from a collector current (mirror current) of the bipolar transistor  70 . 
     In the current mirror circuit portion  55  having such a configuration, a first current mirror circuit is constituted by the transistors  68   a  and  68   b . A second current mirror circuit is constituted by the transistors  69   a  and  69   b . A third current mirror circuit is constituted by the bipolar transistor  70  and each of the bipolar transistors  67   a  and  67   b . As a result, a three-stage current mirror circuit is configured. Specifically, the minute currents I 0a  and I 0b  corresponding to a size ratio between the transistors  68   a  and  68   b , a size ratio between the transistors  69   a  and  69   b , and a size ratio between the bipolar transistor  70  and the bipolar transistors  67   a  and  67   b  are generated between the collector and the emitter of the bipolar transistors  67   a  and  67   b  in response to the reference current I 0  by the current mirror circuit portion  55 . 
     For example, when the size ratio of the transistor  68   a  to the transistor  68   b  is set to p:1 (p is a positive real number), the size ratio of the transistor  69   a  to the transistor  69   b  is set to q:1 (q is a positive real number), and the size ratio of the bipolar transistor  70  to each of the bipolar transistors  67   a  and  67   b  is set to r:1 (r is a positive real number), a direct current having a magnitude 1/(p×q×r) times as large as the reference current I 0  is supplied to each of the bipolar transistors  66   a  and  66   b  with respective diode connections. In particular, it is preferable for the size ratios to be set such that p, q, and r are real numbers greater than 1 to generate a minute current. Thus, the current mirror circuit portion  55  causes a minute current based on a current value of the reference current I 0  and the size ratios of the current mirror circuits. In the case of MOSFETs, the size ratio can be easily set by using a gate width ratio of the respective MOSFETs. 
     The operational amplifier  56  is, for example, a differential amplifier (an operational amplifier) comprised of a complementary metal-oxide-semiconductor (CMOS) circuit. The operational amplifier  56  is a circuit portion that amplifies a difference (a differential signal) in voltage between the signals input to two input terminals  56   a  and  56   b  and outputs the amplified difference in voltage from an output terminal  56   c . In the operational amplifier  56 , the input terminal  56   a  (a non-inverting input terminal) is connected to the emitter (the cathode) of the bipolar transistor  66   b  with the diode connection in the diode pair  53 . The input terminal  56   b  (an inverting input terminal) is connected to the emitter (the cathode) of the bipolar transistor  66   a  with the diode connection in the diode pair  53 . The output terminal  56   c  is electrically connected to the output terminal OUT of the feedback amplifier  30 . With such a configuration, the operational amplifier  56  amplifies the differential signal between the negative phase signal generated at the cathode of one of the diode pair  53  and the average value generated at the cathode of another of the diode pair  53  with a high gain and outputs a resultant signal. 
     The capacitive element (Miller capacitive element)  57  is connected between the output terminal  56   c  and the input terminal  56   b  (the inverting input terminal) of the operational amplifier  56 . Here, the signal output from the output terminal  56   c  is a signal obtained by performing inverting amplification on the signal input to the input terminal  56   b . For example, when the signal input to the input terminal  56   b  increases, the signal output from the output terminal  56   c  decreases, and reversely, when the signal input to the input terminal  56   b  decreases, the signal output from the output terminal  56   c  increases. The capacitive element  57  is connected between the input terminal and the output terminal in which the inverting amplification is performed in this manner. Connecting the capacitive element  57  in this manner allows the operational amplifier  56  to equivalently obtain a large capacitance value (Miller capacitance) due to a Miller effect, as will be described below. A low pass filter that passes only low frequency components of the input signal is configured in a combination of the capacitive element  57  having the Miller capacitance and the diode pair  53  functioning as a resistive element with high resistance. 
     According to the feedback amplifier  30  described above, the positive phase signal and the negative phase signal input to the input terminals INP and INN are input to the operational amplifier  56  comprised of a CMOS circuit in which the capacitive element  57  is connected between the input and the output thereof, via the differential amplifier  52  including the bipolar transistor pair and the diode pair  53  in which the minute current flows from the anode to the cathode. As a result, the differential signal between the positive phase signal and the negative phase signal is amplified with a large gain and output by the operational amplifier  56 . In this case, an input offset is reduced by the differential amplifier  52  including the bipolar transistor pair being connected to the input terminals INP and INN. Specifically, if the feedback amplifier  30  has no differential amplifier  52 , the input offset of the feedback amplifier  30  becomes relatively large due to mismatch (characteristic variation) between threshold voltages of the MOSFETs of the CMOS circuit constituting the operational amplifier  56 . On the other hand, as the feedback amplifier  30  includes the differential amplifier  52 , the input offset of the feedback amplifier  30  is caused by mismatch (for example, manufacturing variation) between base-emitter voltages VBE of the NPN bipolar transistor pair of the differential amplifier  52 , but this mismatch is smaller than the mismatch between the threshold voltages of the CMOS. Therefore, the feedback amplifier  30  allows the input offset thereof to be more reduced. Specifically, for example, the input offset can be reduced from about 50 mV to about several mV by including the differential amplifier  52 . In addition, since the diode pair  53  and the capacitive element  57  constitute a low pass filter with a low cutoff frequency. The low pass filter allows automatic offset control to be stably performed when the transimpedance amplifier  1  amplifies a broadband signal. 
     In addition, according to such a configuration, lowering the supply voltage (a voltage difference between the supply voltage VCC and the power supply voltage VEE) allows the power dissipation to be reduced. For example, a supply current of the feedback amplifier  30  flowing from a supply line for the supply voltage VCC to a supply line for the supply voltage VEE is equal to a sum of currents flowing through the current source  65 , the bias current source  54 , and the current mirror circuit portion  55 . The currents flowing through the current source  65 , the bias current source  54 , and the current mirror circuit portion  55  do not depend much on the voltage difference between the supply voltage VCC and the supply voltage VEE or the currents become smaller as the voltage difference becomes smaller. Therefore, the power dissipation that is calculated by multiplying the supply voltage difference by the sum of the supply currents is reduced by lowering the supply voltage. 
     Further, in the feedback amplifier  30  described above, the input filter  51  is provided between the input terminals INP and INN and the diode pair  53 . With such a configuration, the automatic offset control can be more stable, as the input filter  51  has a sufficient low cutoff frequency for a broadband input signal. Further, in the feedback amplifier  30 , since the diode pair  53  acts as a peak hold circuit for the input signal, an offset may be generated, but this offset is reduced by providing the input filter  51 . 
     In addition, the minute current is supplied to the diode pair  53  by the current mirror circuit having a three-stage configuration. In this case, since the minute current is supplied to the diodes (the bipolar transistors  66   a  and  66   b  with the diode connections) included in the diode pair  53  such that the reverse-biased diodes provides a large resistance, and circuit elements having a Darlington connection that needs a relatively high supply voltage are removable, power dissipation of the feedback amplifier  30  can be reduced. 
     Here, an example of the cutoff frequency in the feedback amplifier  30  of the embodiment will be shown. First, when a capacitance value of the capacitive element  57  alone is C and a voltage gain of the operational amplifier  56  is −A (the negative value means the inverting amplification), a miller capacitance Cm of the capacitive element  57  in the operational amplifier  56  is calculated as Cm=C×(1+A). Accordingly, when the voltage gain is set to 60 dB (corresponding to A=1000) and the capacitance value C is set to 50 pF, the miller capacitance Cm becomes approximately 50 nF. Next, when a resistance value of one of the diodes is R, the cutoff frequency fc is estimated as in the following equation:
 
 fc= 1/(2π· R·Cm )
 
Accordingly, when the resistance value R is set 500 KΩ, the resistance value R=500 KΩ and the miller capacitance Cm=50 nF make the cutoff frequency fc≈6 Hz. The capacitance value C=50 pF of the capacitive element  57  is a typical value available on a semiconductor chip using metal-insulator-metal (MIM) capacitance. In a case in which the feedback amplifier  30  is used for negative feedback in the transimpedance amplifier as illustrated in  FIG. 1 , it is preferable for the voltage gain A, the capacitance value C, and the resistance value R to be set such that fc falls within a range of 10 to 100 Hz. The cutoff frequency fc≈6 Hz is a sufficient value.
 
     Further, advantageous effects obtained by adopting the feedback amplifier  30  in the embodiment will be described through a comparison with a comparative example. 
       FIG. 4  is a circuit diagram illustrating a configuration of a feedback amplifier  930  according to a comparative example. The feedback amplifier  930  according to the comparative example illustrated in  FIG. 4  is a circuit formed through a semiconductor process for an InP heterojunction bipolar transistor (HBT). The feedback amplifier  930  does not include the differential amplifier  52  between the input filter  51  and the diode pair  53 , but includes a Darlington-connected bipolar transistor pair  81  as a circuit portion that supplies the minute current to the diode pair  53 , and includes two stages of differential amplifiers  82  and  84  in order to differentially amplify two input signals (a differential input signal), unlike the feedback amplifier  30 . 
     Specifically, the bipolar transistor pair  81  includes two sets of two-stage Darlington-connected configuration. The bipolar transistors  81   a  and  81   b  constitute one of the two sets and bipolar transistors  81   c  and  81   d  constitute another of the two sets. A set of bipolar transistors  81   a  and  81   b  are provided between an emitter of a bipolar transistor  66   a  and one input of a differential amplifier  82 . A pair of bipolar transistors  81   c  and  81   d  are provided between an emitter of a bipolar transistor  66   b  and another input of the differential amplifier  82 . In the transistors  81   a  and  81   b  which are Darlington-connected in a two-stage configuration, a base of the transistor  81   a  is electrically connected to the emitter of the transistor  66   a , an emitter of the transistor  81   a  is electrically connected to a base of the transistor  81   b  (the first stage), and an emitter of the transistor  81   b  is electrically connected to a base of a transistor  82   a  (the second stage). 
     A potential difference greater than 0.6 to 0.8 V is required between the base and the emitter of each of the transistors  81   a ,  81   b , and  82   a , and a collector of the transistor  81   a  is required to be set to a higher potential than that of the base of the transistor  81   a . Therefore, such a two-stage Darlington-connection (the transistors  81   a  and  81   b ) connected to a differential amplifier (the differential amplifier  82 ) requires a large supply voltage to secure proper operation. 
     The differential amplifier  82  includes a pair of bipolar transistors  82   a  and  82   b , resistive elements  82   c  and  82   d  provided on collector sides of the bipolar transistors  82   a  and  82   b , and a current source  82   e  connected to emitters of the bipolar transistors  82   a  and  82   b . Similarly, a differential amplifier  84  includes a pair of bipolar transistors  84   a  and  84   b , resistive elements  84   c  and  84   d  provided on collector sides of the bipolar transistors  84   a  and  84   b , and a current source  84   e  connected to emitters of the bipolar transistors  84   a  and  84   b.    
     The differential amplifiers  82  and  84  are connected in series at a stage after the Darlington-connected bipolar transistor pair  81 , with an emitter follower circuit  83  interposed therebetween. 
     The emitter follower circuit  83  includes a circuit portion including a bipolar transistor  83   a  and a current source  83   c  and a circuit portion including a bipolar transistor  83   b  and a current source  83   d . A base of the bipolar transistor  83   a  is electrically connected to one output of the differential amplifier  82 . An emitter the bipolar transistor  83   a  is electrically connected to one-input of differential amplifier  84 . A base of the bipolar transistor  83   b  is electrically connected to another output of the differential amplifier  82 . An emitter the bipolar transistor  83   b  is electrically connected to another input of differential amplifier  84 . 
     Further, the feedback amplifier  930  includes capacitive elements (miller capacitances)  57   a  and  57   b . One end of the capacitive element  57   a  is connected to one output of the differential amplifier  84  via an emitter follower circuit including a bipolar transistor  85   a  and a current source  85   c , and another end of the capacitive element  57   a  is connected to the base of the bipolar transistor  81   a . One end of the capacitive element  57   b  is connected to the other output of the differential amplifier  84  via an emitter follower circuit including a bipolar transistor  85   b  and a current source  85   d , and another end of the capacitive element  57   b  is connected to the base of the bipolar transistor  81   c.    
     The one output of the differential amplifier  84  is connected to an output terminal OUT via an emitter follower circuit including a bipolar transistor  86   a  and a current source  86   b.    
     In the comparative example having the above configuration, since the diode pair  53  supplies a minute current to the Darlington-connected transistor pair  81  in which two transistors are vertically stacked, a large supply voltage is required as described above. Further, since high-gain differential amplification is implemented by using two stages of differential amplifiers in which the currents supplied by the current sources  82   e  and  84   e  constantly flow, it is difficult to greatly reduce current dissipation. As a result, the power dissipation of the feedback amplifier  930  tends to increase as compared with the configuration of the embodiment. 
     It should be noted that the present invention is not limited to the above-described embodiment. 
       FIG. 3  is a circuit diagram illustrating a configuration of a variation of the amplifier according to the embodiment. The feedback amplifier  30 A illustrated in  FIG. 3  is different from the feedback amplifier  30  illustrated in  FIG. 2  in that a differential amplifier  52  amplifies a differential signal between two input signals (a positive phase signal and a negative phase signal) input to input terminals INP and INN and outputs a positive phase signal and a negative phase signal of the amplified differential signal, and in that an operational amplifier  56 A having a differential output is included. It should be noted that in  FIG. 3 , the resistive elements  64   c  and  64   d  illustrated in  FIG. 1  are omitted since the average value of the positive phase signal and the negative phase signal amplified by the differential amplifier  52  are not output. 
     The operational amplifier  56 A includes two output terminals  56   c  and  56   d , amplifies a differential signal between signals input to two input terminals  56   a  and  56   b  to generate two complementary signals of which phases are inverted from each other, and outputs the complementary signals from output terminals OUTP and OUTN via output terminals  56   c  and  56   d , respectively. 
     Further, the feedback amplifier  30 A includes two capacitive elements  57   a  and  57   b  corresponding to a differential output configuration. The capacitive element  57   a  is connected between an output terminal  56   c  and an input terminal  56   b  of an operational amplifier  56 A, and the capacitive element  57   b  is connected between an output terminal  56   d  and an input terminal  56   a  of the operational amplifier  56 A. Thus, an output terminal for outputting the inverted and amplified signal is connected to the inverting amplification input terminal via the capacitive element  57   a  (or  57   b ), such that large Miller capacitance can be obtained. 
     The variation of the amplifier according to the embodiment provides stable automatic offset control for amplification of a broadband signal and reduced power dissipation as a result of lowering the power supply voltage. 
     Although the principle of the invention has been illustrated and described in the preferred embodiment, it will be appreciated by those skilled in the art that the present invention may be changed in an arrangement and details without departing from a such principle. The present invention is not limited to the specific configuration disclosed in the embodiment. Accordingly, all modifications and changes within the scope of the claims and the spirit thereof are claimed.