Patent Publication Number: US-2010118614-A1

Title: Semiconductor apparatus, data write circuit of semiconductor apparatus, and method of controlling data write circuit

Description:
CROSS-REFERENCES TO RELATED PATENT APPLICATION 
     The present application claims priority under 35 U.S.C 119(a) to Korean Patent Application No. 10-2008-0112687, filed on Nov. 13, 2008, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full. 
     BACKGROUND 
     The present invention relates generally to a semiconductor apparatus, and more particularly, to a semiconductor apparatus, a data write circuit of a semiconductor apparatus, and a method of controlling the data write circuit. 
       FIG. 1  is a circuit diagram showing a data write circuit of a semiconductor apparatus according to the related art. 
     Referring to  FIG. 1 , The data write circuit of the semiconductor integrated circuit according to the related art includes first to fourth multiplexers  11  to  14 , first to fourth latches  15  to  18 , and first to fourth drivers  19  to  22 . 
     Each of the first to fourth multiplexers  11  to  14  selectively outputs data D 0  to D 3 , which are arranged according to signals synchronized with a rising edge and a falling edge of a data strobe signal ‘DQS’, that is, according to control signals ‘SOSEB&lt;0:3&gt;’ and ‘SSEL&lt;0:3&gt;’. 
     The first to fourth latches  15  to  18  latch the output signals ‘DINR 0 ’, DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ of the first to fourth multiplexers  11  to  14 , respectively, according to a data clock signal ‘DCLK’. 
     The first to fourth drivers  19  to  22  drive the output signals of the first to fourth latches  15  to  18  and transmit the signals to global input/output lines ‘GIO_Q 0 ’ to GIO_Q 3 ’. 
       FIG. 2  is a timing chart shown for illustrating the operation of the data write circuit shown in  FIG. 1 . 
     Referring to  FIG. 2 , in the data write circuit according to the related art, the signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ that are output by the first to fourth multiplexers  11  to  14  are simultaneously carried to the global input/output lines ‘GIO_Q 0 ’ to ‘GIO_Q 3 ’ in accordance with the data clock signal ‘DCLK’. 
       FIG. 2  shows an example of when four data DO to D 3  are carried to the corresponding global input/output lines ‘GIO_Q 0 ’ to ‘GIO_Q 3 ’. In actuality, a very large number of the global input/output lines will exist. For example, 64 global input/output lines exist in the case of DDR2, and 128 global input/output lines exist in the case of DDR3, and data is simultaneously carried to the very large number of global data lines. 
     Typically, when the size of a semiconductor apparatus is decreased, the ratio of global data lines to the entire area of the semiconductor apparatus increases and the width of the global data line is narrowed. Consequently, the distance between adjacent global data lines decreases. 
     When a large amount of data is simultaneously carried to the global input/output lines, the data carried in adjacent global input/output lines will often have different logical levels. 
     When the data carried in adjacent global input/output lines have opposite logical levels, a data transmission delay is caused by an increase in a parasitic capacitance that is generated by a coupling effect between the data. As a consequence, the transmission characteristics of the semiconductor apparatus are deteriorated and it is possible for errors to be caused during the operation of the semiconductor apparatus. 
     SUMMARY 
     Embodiments of the present invention include a semiconductor apparatus, a data write circuit of the semiconductor apparatus, and a method of controlling the data write circuit that can minimize a coupling effect between data carried in adjacent global input/output lines. 
     In one aspect, a data write circuit of a semiconductor apparatus includes a plurality of latches configured to latch a plurality of data in response to activation of a plurality of control signals and output the latched data to data lines; and a control unit configured to generate the plurality of control signals to be activated at different timings, such that partial data input at relatively earlier timing among the plurality of data is latched at earlier timing than the other data by a portion of the plurality of latches. 
     In another aspect, a data write circuit of a semiconductor apparatus includes a plurality of latches configured to latch partial data among a plurality of data at earlier timing than the other data in response to a plurality of control signals; and a control unit configured to determine the partial latches that receive the partial data among the plurality of latches, and activate the control signals input to the partial latches at earlier timing than the other control signals. 
     In another aspect, a method of controlling a data write circuit of a semiconductor apparatus that includes a plurality of latches includes determining the latches that receive data input at relatively earlier timing among the plurality of latches; and activating the latches, which receive the data input at relatively earlier timing among the plurality of latches, at earlier timing than the other latches. 
     In another aspect, a method of controlling a data write circuit of a semiconductor apparatus that includes a plurality of latches includes arranging a plurality of data input sequentially in different order in accordance with a data transmission mode to generate arranged data; and latching the data, which is input at relatively earlier timing among the arranged data, at earlier timing than the other data. 
     In another aspect, a semiconductor apparatus includes a plurality of latches configured to latch a plurality of data in response to activation of a plurality of control signals; a control unit configured to generate the plurality of control signals to be activated at different timings, such that partial data input at relatively earlier timing among the plurality of data is latched at earlier timing than the other data by a portion of the plurality of latches; and a plurality of drivers configured to drive the data latched by the plurality of latches and transmit the data to global input/output lines. 
     A semiconductor apparatus, a data write circuit of the semiconductor apparatus, and a method of controlling the data write circuit according to an embodiment of the present invention can minimize a coupling effect and prevent lowering of a data transmission speed. 
     These and other features, aspects, and embodiments are described below in the section “Detailed Description.” 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
         FIG. 1  is a circuit diagram showing a data write circuit of a semiconductor apparatus according to the related art; 
         FIG. 2  is a timing chart shown for illustrating the operation of the data write circuit shown in  FIG. 1 ; 
         FIG. 3  is a circuit diagram of a data write circuit of an exemplary semiconductor apparatus according to an embodiment of the present invention; 
         FIG. 4  is a circuit diagram showing the internal structure of the exemplary control unit shown in  FIG. 3 ; and 
         FIGS. 5 to 8  are timing charts shown for illustrating the operation in a sequential mode/interleave mode of the exemplary data write circuit shown in  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 3  is a circuit diagram of a data write circuit of an exemplary semiconductor apparatus according to an embodiment of the present invention. 
     As shown in  FIG. 3 , the data write circuit of the semiconductor apparatus according to an embodiment of the present invention can include first to fourth multiplexers  110  to  140 , first to fourth latches  150  to  180 , first to fourth drivers  190  to  220 , and a control unit  300 . 
     Each of the first to fourth multiplexers  110  to  140  can selectively output data D 0  to D 3 , which are arranged according to signals synchronized with a rising edge and a falling edge of a data strobe signal ‘DQS’ (that is, according to first selection signals ‘SOSEB&lt;0:3&gt;’ and second selection signals ‘SSEL&lt;0:3&gt;)’. 
     The first selection signals ‘SOSEB&lt;0:3&gt;’ can be obtained by decoding lower addresses A 0  and A 1  among a plurality of addresses that are input according to a write command or a read command, and define the arranged data D 0  to D 3  and a memory area (for example, a quarter block of a bank) where the arranged data D 0  to D 3  are written. 
     The second selection signals ‘SSEL&lt;0:3&gt;’ can be set in a mode register set and define the arranged data D 0  to D 3  according to a data transmission method (sequential/interleave method) and a memory area (for example, a quarter block of a bank) where the arranged data D 0  to D 3  are written. 
     The first to fourth latches  150  to  180  can latch the output signals ‘DINR 0 ’, DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ of the first to fourth multiplexers  110  to  140  according to a plurality of latch timing control signals ‘DCLK_Q 0 ’ to ‘DCLK_Q 3 ’, respectively. 
     The first to fourth drivers  190  to  220  can drive the output signals of the first to fourth latches  150  to  180  and transmit the signals to global input/output lines ‘GIO_Q 0 ’ to GIO_Q 3 ’. 
     The control unit  300  can generate the latch timing control signals ‘DCLK_Q 0 ’ to ‘DCLK_Q 3 ’ according to address signals ‘A&lt;0:1&gt;’, a data clock signal ‘DCLK’, a reset signal ‘RST’, and a data transmission mode signal ‘SEQ’. 
     The data transmission mode signal ‘SEQ’ can be used to define one of a sequential mode and an interleave mode, which are data transmission modes of the semiconductor apparatus. For example, the data transmission mode of the semiconductor apparatus can be defined as the sequential mode or the interleave mode based on whether the data transmission mode signal ‘SEQ’ is at a high level or a low level. 
       FIG. 4  is a circuit diagram showing the internal structure of an embodiment of the control unit shown in  FIG. 3 . 
     Referring to  FIG. 4 , the control unit  300  can include a divider  310  and a control signal generator  320 . 
     The divider  310  can divide the data clock signal ‘DCLK’ by a predetermined division ratio to generate a data clock division signal ‘DCLKCNT’ and initialize the data clock division signal ‘DCLKCNT’ in response to the reset signal ‘RST’. 
     The divider  310  can generate the data clock division signal ‘DCLKCNT’ by, for example, dividing the data clock signal ‘DCLK’ by two. The divider  310  can include a plurality of inverters IV 1  and IV 2  and a plurality of tri-state inverters TSIV 1  to TSIV 3 . 
     The control signal generator  320  can generate the latch timing control signals ‘DCLK_Q 0 ’ to ‘DCLK_Q 3 ’ in a manner such that the output signals (for example, signals ‘DINR 0 ’ and ‘DINF 0 ’) of the multiplexers (among the first to fourth multiplexers  110  to  140 ) that select data D 0  and D 1  input at an earlier timing, and the output signals (for example, signals ‘DINR 1 ’ and ‘DINF 1 ’) of the multiplexers (among the first to fourth multiplexers) that select the data D 2  and D 3  input at later timing among the first to fourth multiplexers  110  to  140 , are latched by the first to fourth latches  150  to  180  with a predetermined time difference. 
     In more detail, the control signal generator  320  shown in  FIG. 4  can generate the latch timing control signals ‘DCLK_Q 0 ’ to ‘DCLK_Q 3 ’ in a manner such that output signals (for example, signals ‘DINR 0 ’ and ‘DINF 0 ’) of the multiplexers that select the data D 0  and D 1  input at earlier timing are latched by the first to fourth latches  150  to  180  before the output signals (for example, signals ‘DINR 1 ’ and ‘DINF 1 ’) of the multiplexers that select the data D 2  and D 3  input at later timing. The respective data D 0  to D 3  corresponding to the respective output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ (which is output from the first to fourth multiplexers  110  to  140 ) can be changed according to the data transmission mode (sequential mode/interleave mode) and the address signals ‘A&lt;0:1&gt;’. 
     For example, when in sequential mode (SEQ=‘1’), the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ (which are output from the first to fourth multiplexers  110  to  140 ) can be D 0 , D 1 , D 2 , and D 3  when the address signals ‘A&lt;0:1&gt;’ are ‘00’; the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ can be D 1 , D 2 , D 3 , and D 0  when the address signals ‘A&lt;0:1&gt;’ are ‘01’; the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ can be D 2 , D 3 , D 0 , and D 1  when the address signals ‘A&lt;0:1&gt;’ are ‘10’; and the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ can be D 3 , D 0 , D 1 , and D 2  when the address signals ‘A&lt;0:1&gt;’ are ‘11’. 
     As a further example, when in interleave mode (SEQ=‘0’), the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ (output from the first to fourth multiplexers  110  to  140 ) can be D 0 , D 1 , D 2 , and D 3  when the address signals ‘A&lt;0:1&gt;’ are ‘00’; the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ can be D 1 , D 0 , D 2 , and D 3  when the address signals ‘A&lt;0:1&gt;’ are ‘01’; the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’ and ‘DINF 1 ’ can be D 2 , D 3 , D 0 , and D 1  when the address signals ‘A&lt; 0 : 1 &gt;’ are ‘ 10 ’; and the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ can be D 3 , D 2 , D 1 , and D 0  when the address signals ‘A&lt;0:1&gt;’ are ‘11’. 
     Referring to the example in which the device is in sequential mode (SEQ =‘1’), and the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ (which are from the first to fourth multiplexers  110  to  140 ) are D 0 , D 1 , D 2 , and D 3  when the address signals ‘A&lt;0:1&gt;’ are ‘00’; according to an embodiment of the present invention, the control signal generator  320  can be configured such that the first latch  150  and the second latch  160  latch the input data before the third latch  170  and the fourth latch  180  by activating the latch timing control signals ‘DCLK_Q 0 ’ and ‘DCLK_Q 1 ’ at a timing earlier than the activation timing of the latch timing control signals ‘DCLK_Q 2 ’ and ‘DCLK_Q 3 ’. 
     At this time, the arrangement of the data ‘DO to D 3  with respect to the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ (that is, the manner in which the respective data D 0  to D 3  corresponds to the respective output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ of the first to fourth multiplexers  110  to  140 ) can be recognized through the data transmission mode signal ‘SEQ’ and the address signals ‘A&lt;0:1&gt;’, as described above. 
     Accordingly, the control signal generator  320  can combine the data transmission mode signal ‘SEQ’, the address signals ‘A&lt;0:1&gt;’, and the data clock signal ‘DCLK’ using logical elements to thereby generate the latch timing control signals ‘DCLK_Q 0 ’ to ‘DCLK_Q 3 ’ of which activation timings are different from each other according to the arrangement of the data D 0  to D 3 . The control signal generator  320  can be configured to include an XNOR gate XNOR 11 , a plurality of AND gates AND 11  to AND 15 , a NOR gate NOR 11 , an OR gate OR 11 , a plurality of inverters IV 11  to IV 16 , and a plurality of pass gates PG 11  to PG 18 . 
     The operation of the data write circuit according to an embodiment of the present invention having the above-described structure will now be described. 
       FIG. 5  is a timing chart shown for illustrating the operation during sequential mode of the exemplary data write circuit shown in  FIG. 3 . In this case, the address signals ‘A&lt;0&gt;=0’ and ‘A&lt;1&gt;=0’ are input 
     This case corresponds to when a corresponding mode is the sequential mode (SEQ=1) and the address signals ‘A&lt;0&gt;=0’ and ‘A&lt;1&gt;=0’ are input. Thus, the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ from the first to fourth multiplexers  110  to  140  are D 0 , D 1 , D 2 , and D 3 . 
     Since the control signal generator  320  that is shown in  FIG. 4  receives the address signals ‘A&lt;0&gt;=0’ and ‘A&lt;1&gt;=0’, a high-level signal is output from the OR gate OR 11  and the pass gates PG 11 , PG 13 , PG 16 , and PG 18  can be turned on. 
     The AND gates AND 12  and AND 13  perform an AND logical operation on a power supply voltage VDD passed by respective pass gates PG 11  and PG 13  and the data clock signal ‘DCLK’ to generate the latch timing control signals ‘DCLK_Q 0 ’ and ‘DCLK_Q 1 ’. 
     The AND gates AND 14  and AND 15  perform an AND logical operation on the data clock division signal ‘DCLKCNT’ passed by the respective pass gates PG 16  and PG  18  and the data clock signal ‘DCLK’ to the generate latch timing control signals ‘DCLK_Q 2 ’ and ‘DCLK_Q 3 ’. 
     Accordingly, as shown in  FIG. 5 , the latch timing control signals ‘DCLK_Q 0 ’ and ‘DCLK_Q 1 ’ can be activated and output before the latch timing control signals ‘DCLK_Q 2 ’ and ‘DCLK_Q 3 ’. 
     The first to fourth latches  150  to  180  shown in  FIG. 3  can therefore latch the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ from the first to fourth multiplexers  110  to  140  in accordance with the latch timing control signals ‘DCLK_Q 0 ’ to ‘DCLK_Q 3 ’ shown in  FIG. 5  and can output the latched signals. 
     The first to fourth drivers  190  to  220  can thus output the output signals from the first to fourth latches  150  to  180  to the global input/output lines ‘GIO_Q 0 ’ to ‘GIO_Q 3 ’. 
     The data that is transmitted through the global input/output lines ‘GIO_Q 0 ’ to ‘GIO_Q 3 ’ can be written to a memory area by a circuit block (not shown) that is related to data write. 
       FIG. 6  is a timing chart shown for illustrating the operation during sequential mode of an exemplary data write circuit shown in  FIG. 3 . In this case, the address signals ‘A&lt;0&gt;=0’ and ‘A&lt;1&gt;=0’ are input. 
     This case corresponds to when a corresponding mode is the sequential mode (SEQ=1) and the address signals ‘A&lt;0&gt;=0’ and ‘A&lt;1&gt;=1’ are input. Thus, the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ from the first to fourth multiplexers  110  to  140  are D 2 , D 3 , D 0 , and D 1 . 
     Since the control signal generator  320  that is shown in  FIG. 4  receives the address signals ‘A&lt;0&gt;=0’ and ‘A&lt;1&gt;=1’, a low-level signal is output from the OR gate OR 11  and the pass gates PG 12 , PG 14 , PG 15 , and PG 17  can be turned on. 
     The AND gates AND 12  and AND 13  perform an AND logical operation on the data clock division signal ‘DCLKCNT’ passed by the respective pass gates PG 12  and PG 13  and the data clock signal ‘DCLK’ to generate the latch timing control signals ‘DCLK_Q 0 ’ and ‘DCLK_Q 1 ’. 
     The AND gates AND 14  and AND 15  perform an AND logical operation on a power supply voltage VDD passed by the respective pass agates PG 15  and PG 17  and the data clock signal ‘DCLK’ to generate the latch timing control signals ‘DCLK_Q 2 ’ and ‘DCLK_Q 3 ’. 
     Accordingly, as shown in  FIG. 6 , the latch timing control signals ‘DCLK_Q 2 ’ and ‘DCLK_Q 3 ’ can be activated and output before the latch timing control signals ‘DCLK_Q 0 ’ and ‘DCLK_Q 1 ’. 
     The first to fourth latches  150  to  180  shown in  FIG. 3  can therefore latch the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ from the first to fourth multiplexers  110  to  140  in accordance with the latch timing control signals ‘DCLK_Q 0 ’ to ‘DCLK_Q 3 ’ shown in  FIG. 5  and can output the latched signals. 
     The first to fourth drivers  190  to  220  can thus output the output signals from the first to fourth latches  150  to  180  to the global input/output lines ‘GIO_Q 0 ’ to ‘GIO_Q 3 ’. 
     The data that is transmitted through the global input/output lines ‘GIO_Q 0 ’ to ‘GIO_Q 3 ’ can be written to the memory area by a circuit block (not shown) that is related to data write. 
       FIG. 7  is a timing chart shown for illustrating the operation during interleave mode of an exemplary data write circuit shown in  FIG. 3 . In this case, the address signals ‘A&lt;0&gt;=1’ and ‘A&lt;1&gt;=0’ are input. 
     This case corresponds to when a corresponding mode is the interleave mode (SEQ=0) and the address signals ‘A&lt;0&gt;=1’ and ‘A&lt;1&gt;=0’ are input. Thus, the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ from the first to fourth multiplexers  110  to  140  are D 1 , D 0 , D 2 , and D 3 . 
     Since the control signal generator  320  that is shown in  FIG. 4  receives the address signals ‘A&lt;0&gt;=1’ and ‘A&lt;1&gt;=0’, a high-level signal is output from the OR gate OR 11  and the pass gates PG 11 , PG 13 , PG 16 , and PG 18  are turned on. 
     The AND gates AND 12  and AND 13  perform an AND logical operation on a power supply voltage VDD passed by the respective pass gates PG 11  and PG 13  and the data clock signal ‘DCLK’ to generate the latch timing control signals ‘DCLK_Q 0 ’ and ‘DCLK_Q 1 ’. 
     The AND gates AND 14  and AND 15  perform an AND logical operation on the data clock division signal ‘DCLKCNT’ passed by the respective pass gates PG  16  and PG  18  and the data clock signal ‘DCLK’ to generate the latch timing control signals ‘DCLK_Q 2 ’ and ‘DCLK_Q 3 ’. 
     Accordingly, as shown in  FIG. 7 , the latch timing control signals ‘DCLK_Q 0 ’ and ‘DCLK_Q 1 ’ can be activated and output before the latch timing control signals ‘DCLK_Q 2 ’ and ‘DCLK_Q 3 ’. 
     The first to fourth latches  150  to  180  shown in  FIG. 3  can therefore latch the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ from the first to fourth multiplexers  110  to  140  in accordance with the latch timing control signals ‘DCLK_Q 0 ’ to ‘DCLK_Q 3 ’ shown in  FIG. 7  and can output the latched signals. 
     The first to fourth drivers  190  to  220  can thus output the output signals from the first to fourth latches  150  to  180  to the global input/output lines ‘GIO_Q 0 ’ to ‘GIO_Q 3 ’. 
     The data that is transmitted through the global input/output lines ‘GIO _Q 0 ’ to ‘GIO_Q 3 ’ can be written to the memory area by a circuit block (not shown) that is related to data write. 
       FIG. 8  is a timing chart shown for illustrating the operation during interleave mode of an exemplary data write circuit shown in  FIG. 3 . In this case, the address signals ‘A&lt;0&gt;=0’ and ‘A&lt;1&gt;=1’ are input. 
     This case corresponds to when a corresponding mode is the interleave mode (SEQ=0) and the address signals ‘A&lt;0&gt;=0’ and ‘A&lt;1&gt;=1’ are input. Thus, the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ from the first to fourth multiplexers  110  to  140  are D 2 , D 3 , D 0 , and D 1 . 
     Since the control signal generator  320  that is shown in  FIG. 4  receives the address signals ‘A&lt;0&gt;=0’ and ‘A&lt;1&gt;=1’, a low-level signal is output from the OR gate OR 11  and the pass gates PG 12 , PG 14 , PG 15 , and PG 17  can be turned on. 
     The AND gates AND 12  and AND 13  can perform an AND logical operation on the data clock division signal ‘DCLKCNT’ passed by the respective pass gates PG 12  and PG  14  and the data clock signal ‘DCLK’ to generate the latch timing control signals ‘DCLK_Q 0 ’ and ‘DCLK_Q 1 ’. 
     The AND gates AND 14  and AND 15  perform an AND logical operation on a power supply voltage VDD passed by the respective pass gates PG 15  and PG  17  and the data clock signal ‘DCLK’ to generate the latch timing control signals ‘DCLK_Q 2 ’ and ‘DCLK_Q 3 ’. 
     Accordingly, as shown in  FIG. 8 , the latch timing control signals ‘DCLK_Q 2 ’ and ‘DCLK_Q 3 ’ can be activated and output before the latch timing control signals ‘DCLK_Q 0 ’ and ‘DCLK_Q 1 ’. 
     The first to fourth latches  150  to  180  shown in  FIG. 3  can therefore latch the output signals ‘DINR 0 ’, ‘DINF 0 ’, ‘DINR 1 ’, and ‘DINF 1 ’ from the first to fourth multiplexers  110  to  140  in accordance with the latch timing control signals ‘DCLK_Q 0 ’ to ‘DCLK_Q 3 ’ shown in  FIG. 8  and can output the latched signals. 
     The first to fourth drivers  190  to  220  can thus output the output signals from the first to fourth latches  150  to  180  to the global input/output lines ‘GIO_Q 0 ’ to ‘GIO_Q 3 ’. 
     The data that is transmitted through the global input/output lines ‘GIO_Q 0 ’ to ‘GIO_Q 3 ’ can be written to the memory area by a circuit block (not shown) that is related to data write. 
     As described above, in the data write circuit and the method of controlling the data write circuit according to embodiments of the present invention, even though the arrangement of data is changed according to whether the sequential mode is used or the interleave mode is used, data input at earlier timing can be latched before data input at later timing and output to the global input/output lines ‘GIO_Q 0 ’ to ‘GIO_Q 3 ’. Accordingly, it is possible to minimize a coupling effect between data carried in adjacent global input/output lines. 
     While certain embodiments have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the device and method described herein should not be limited based on the described embodiments. Rather, the devices and methods described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.