Patent Publication Number: US-8984320-B2

Title: Command paths, apparatuses and methods for providing a command to a data block

Description:
TECHNICAL FIELD 
     Embodiments of the invention relate generally to semiconductor memory, and more specifically, in one or more described embodiments, to timing internal clock and command signals for executing memory commands in a high-speed memory clock system. 
     BACKGROUND OF THE INVENTION 
     In semiconductor memory, proper operation of the memory is based on the correct timing of various internal command and clock signals. For example, in reading data from the memory, internal clock signals that clock data block circuitry to provide (e.g. output) the read data may need to be provided substantially concurrently with internal read command signals to properly enable the data block circuitry to output the read data. If the timing of the internal read command signal is not such that the data block circuitry is enabled at the time the internal clock signal clocks the data block circuitry to output the read data at an expected time, the read command may be inadvertently ignored or the read data provided by the memory may not be correct (i.e., the data associated with another read command). 
     Moreover, as known, a “latency” may be programmed to set a time, typically in numbers of clock periods tCK, between receipt of a read command by the memory and when the data is output by the memory. The latency may be programmed by a user of the memory to accommodate clock signals of different frequencies (i.e., different clock periods). Other examples of commands that may require that the correct timing of internal clock signals and the command for proper operation include, for example, write commands and on-die termination enable commands. 
     Complicating the generating of correctly timed internal clock and command signals is the relatively high frequency of memory clock signals. For example, memory clock signals can exceed 1 GHz. Further complicating the matter is that multi-data rate memories may provide and receive data at a rate higher than the memory clock signal, which may represent the rate at which commands may be executed. As a result, the timing domains of command and clock signals may need to be crossed in order to maintain proper timing. An example of a multi-data rate memory is one that outputs read data at a rate twice that of the clock frequency, such as outputting data synchronized with clock edges of the memory clock signal. 
     An example conventional approach of timing internal command and clock signals is modeling both the clock path and the command path to have the same propagation delay. This may require, however, that delays and/or counter circuitry run continuously. As a result, power consumption may be higher than desirable. Additionally, the propagation delay of the various internal clock and command paths can often vary due to power, voltage, and temperature conditions. For clock and command paths having relatively long propagation delay or additional delay circuitry, the variations due to operating conditions may negatively affect the timing of the internal signals to such a degree that the memory does not operate properly. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a simplified block diagram of clock and command paths according to an embodiment of the invention. 
         FIG. 2  is a timing diagram of various signals during operation of the clock and command paths of  FIG. 1 . 
         FIG. 3  is a simplified block diagram of a timing calibration block according to an embodiment of the invention. 
         FIG. 4  is a simplified block diagram of a feedback path for a delay-lock loop according to an embodiment of the invention. 
         FIG. 5  is a timing diagram of various signals during operation of the timing calibration block of  FIG. 3 . 
         FIG. 6  is a simplified block diagram of a timing adjustment block according to an embodiment of the invention. 
         FIG. 7  is a simplified block diagram of a shift adjustment block according to an embodiment of the invention. 
         FIG. 8  is a simplified block diagram of clock and ODT command paths according to an embodiment of the invention. 
         FIG. 9  is a simplified block diagram of a memory including clock and command paths according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention. 
       FIG. 1  illustrates clock path  100  and command path  150  according to an embodiment of the invention. The clock path  100  may be configured to provide a distributed clock signal DLL 2 DQOUT that is based at least in part on the timing of input clock signal CLK, for example, a system clock, to various circuitry. The DLL 2 DQOUT signal may be used to clock the various circuitry during operation. The clock path  100  includes a clock receiver  110  configured to receive a clock signal CLK and provide an output clock signal CLKOUT to a clock buffer  114 . The clock receiver  110  may drive the signal levels of the CLK signal to a full clock signal voltage before providing the resulting CLKOUT signal to the clock buffer  114 . The clock buffer  114  may be configured to buffer the CLKOUT signal and provide an output clock signal CLK 2 DLL to delay lock loop (DLL)  118 . The clock buffer  114  may also be configured to provide output clock signals CLK 2 DEC and CLK 2 ALSH to the command path  150 . As will be explained in more detail below, the CLK 2 DEC and CLK 2 ALSH signals may be used during operation of the command path  150 . The CLK 2 DLL, CLK 2 DEC, and CLK 2 ALSH signals provided by the clock buffer  114  may be based at least in part on the CLKOUT signal from the clock receiver  110 . 
     The DLL  118  provides an output clock signal DLL 2 TREE to a DLL tree circuit  122 , which is configured to distribute the DLL 2 TREE signal as distributed clock signals DLL 2 DQOUT, for example, to a plurality of data input/output circuits  174  of data block  170 . The DLL 2 DQOUT signals may be used to clock the data input/output circuits  174  to input and output data DQ, such as that retrieved (e.g., read data) from a memory array to the data receiver/transmitter  178 . A data circuit path delay may be defined to include at least some of the propagation delays due to the DLL tree circuit  122 , and the data input/output circuits  174  and the data receiver/transmitter  178 . In some embodiments, the data circuits  174  are configured to provide and receive data at a frequency twice the frequency of the DLL 2 DQOUT signal (i.e., twice the frequency of the CLK signal). 
     As known, electronic circuitry have inherent propagation delays which may result in signal delays as a signal is received and provided by the circuitry. For example, as the CLK signal propagates through the clock path  100  to be output by the DLL tree  122 , the phase of the DLL 2 DQOUT signals may be different than the CLK signal. This is problematic where the propagation delay of the circuitry is significant enough to cause errors or negatively affect memory performance, for example, where it is desirable for the DQ to be output corresponding to (e.g., coincident with) the CLK signal. The DLL  118 , however, may be configured to output the DLL 2 TREE signal having a delay relative to the CLK signal (received from the clock buffer  114  as the CLK 2 DLL signal) such that the timing of the DLL 2 DQOUT clocking the data circuits  174  results in DQ received or provided by the data receiver/transmitter  178  to be substantially in phase with the CLK signal. 
     The command path  150  may be configured to provide a command CMD, for example, a read command, from an input to various circuitry for use during operation. The command path  150  has a command path delay. That is, the command path  150  takes a finite time, as known, to propagate a command from the input to the circuitry using the command. The signal provided to the various circuitry may be used, for example, to enable operation of the circuitry. The command path  150  of  FIG. 1  includes a command receiver  154  that is configured to receive the CMD and provide an output command signal CMDOUT to a command latch and decoder  158 . The command latch and decoder  158  latches, decodes, and outputs the CMDOUT signal responsive to the CLK 2 DEC signal from the clock buffer  114  of the clock path  100 . That is, the command latch and decoder  158  outputs decoded command signal CMD 2 ALSH to an additive latency (AL) shifter  162  responsive to the CLK 2 DEC signal. The AL shifter  162  is configured to shift the CMD 2 ALSH signal through it responsive to the CLK 2 ALSH signal from the clock buffer  114  of the clock path  100 . The shifting adds clock cycles tCK of the CLK signal (by virtue of the CLK 2 ALSH signal) to provide additive latency to the propagation of the CMD signal through the command path  100 . As known, AL may be added to accommodate the timing of internal operations of the memory and may be programmed or set by a user or manufacture, for example, by an additive latency value (typically in terms of the number of tCKs). The AL shifter  162  may provide a crossing point between a clock timing domain of the CLK signal and a command timing domain of the CMD signal. 
     After the CMD 2 ALSH signal is shifted to provide the additive latency, it is output by the AL shifter  162  as output command signal CMDXCLK to command buffer and timing adjustment block  164  which is configured to provide additional delay to the propagation of the CMD signal through the command path  150 . Following the delay provided by the timing adjustment block  164 , the CMDXCLK signal is output as the CMD 2 QED signal to command block  166 . The command block  166  provides the CMD 2 QED signal as a QED 2 TREE signal to a command tree  168  responsive to the DLL 2 TREE signal from the DLL block  118  from the clock path  100 . 
     As will be described in more detail below, the timing adjustment block  164  may provide delay, for example, to align command signals to provide timing margin and to accommodate changes in the delay through the clock path  100 , for example, changes resulting from changes in the delay provided by the DLL block  118  in order to maintain synchronicity of the CLK and DLL 2 DQOUT signals. In some embodiments, the delay added by the timing adjustment block  164  may be used to align a leading clock edge of CMD 2 QED signal with a falling clock edge of the DLL 2 TREE signal, which may improve timing margin for receipt of the CMD 2 QED signal by the command block responsive to the DLL 2 TREE signal. For example, where the CMD 2 QED signal has a signal width of approximately one tCK (i.e., one period of the CLK signal), a rising clock edge of the DLL 2 TREE signal will be substantially aligned with the center of the CMD 2 QED signal thereby providing a timing margin of approximately one-half tCK to receive the CMD 2 QED signal. In some embodiments, timing adjustment circuit  164  may perform a delay determination in response to changes to the timing of the signals in the clock path  100 , for example, responsive to changes to the timing made by the DLL block  118 . The DLL block  118  may make changes to the timing of the DLL 2 TREE signal to maintain the synchronization between the CLK and the output of data DQ. 
     As will also be described in greater detail below, the command block  166  may output the QED 2 TREE signal following a delay that is based at least in part on a shift count CLCOUNTADJ provided by a timing calibration block  180 . For example, in some embodiments, the command block  166  provides a delay based at least in part on a difference between a CAS latency (e.g., programmed by a user) and a path delay measured in a number of tCKs by the timing calibration block  180 . The path delay may include delays attributed to various circuits in the clock path  100  and command path  150 , as will be described in more detail below. 
     With further reference to  FIG. 1 , the command tree  168  is configured to distribute the QED 2 TREE signal as QED 2 DQOUT signals to a plurality of data circuits  174  of data block  170 . The QED 2 TREE signals may, for example, be used to control operation of the data circuits  174  such that unless an active QED 2 DQOUT signal is provided to a data circuit  174  at a time the DLL 2 DQOUT signal clocks it, data will not be output by the data circuit  174 . 
     In the embodiment of  FIG. 1 , a power savings benefit may be provided because there is not continuously running upstream and downstream counters. Instead, there is a shifter that runs on a need basis, which as a result, may reduce power consumption. 
     For convenience, the signals previously discussed that have common phases are identified by common phase symbols in  FIG. 1 . For example, the CLK, CMD, and DQ signals are generally “in phase,” as represented by having the common phase symbol of “***”. In another example, DLL 2 TREE and QED 2 TREE signals are also generally in phase, as represented by the common phase symbol “#”. 
     Operation of the clock path  100  and command path  150  ( FIG. 1 ) according to an embodiment of the invention will be described with reference to the timing diagram of  FIG. 2 .  FIG. 2  illustrates a timing diagram of various signals during the operation of the clock and command paths  100 ,  150  of  FIG. 1 . The example operation will be described with reference to a read command. Additionally, for the purpose of the example operation, it is assumed that the CAS latency is equal to seven tCK, that is, data will expected to be output seven tCK following the input, for example, of a read command. 
     At time T 0 , the DLL 2 TREE signal has a rising clock edge that precedes time T 1  by a time equal to a propagation delay through the DLL tree  122 , and the data circuits  174  and data receiver/transmitter  178  of the data block  170 . As will be understood, the time between T 0  and T 1  is approximately equal to a path delay through DLL tree  122 , data circuits  174  and data receiver/transmitter  178 . As also previously discussed, the DLL block  118  may be used to adjust the timing of the DLL 2 TREE signal relative to the CLK signal so that rising clock edges of the DLL 2 TREE signal provided to DLL tree  122  will propagate to the data circuits  174  to clock data out of the data block  170  coincident with a rising clock edge of the CLK signal. 
     At time T 1 , a read command (not shown) is provided to the command receiver  154  as the CMD substantially coincident with a rising clock edge of the CLK signal, that is, a leading clock edge of the command is substantially coincident with the rising clock edge of the CLK signal. Time T 2  represents a time after the input of the CMD at which the CMD propagates through the command latch and decoder  158 , the AL shifter  162 , and the command buffer and timing adjustment block  164  to be output as the CMD 2 QED signal to the command block  166 , but without any additional delay provided by the command buffer and timing adjustment block  164 . Time T 3  represents a propagation delay through the command latch and decoder  158 , the AL shifter  162 , and the command buffer and timing adjustment block  164 , but with additional delay added by the command buffer and timing adjustment block  164 . As will be understood, the time between T 1  and T 3  is approximately equal to a path delay from the command receiver  154  through the command buffer and timing adjustment block  164 . 
     As previously discussed, additional delay may be added by the command buffer and timing adjustment block  164  to align the CMD 2 QED signal with a falling clock edge of the DLL 2 TREE signal so that the CMD 2 QED signal (assuming one tCK wide) is substantially center aligned with a rising clock edge of the DLL 2 TREE signal. The substantial center alignment of the CMD 2 QED signal is illustrated by the rising clock edge of the DLL 2 TREE signal at time T 4 . The difference between times T 2  and T 3  represents the delay added by the command buffer and timing adjustment block  164  before outputting the CMD 2 QED signals to the command block  166 . 
     As also previously discussed, the command block  166  may further add delay (e.g., in number of tCKs) to the CMD 2 QED signals before being output to the command tree  168  responsive to the DLL 2 TREE signal. The addition delay may be based at least in part on the CLCOUNTADJ shift count from the timing calibration block  180 . In the example operation of the timing diagram of  FIG. 2 , the CLCOUNTADJ shift count is assumed to be two tCKs. That is, the command block  166  waits two tCKs after the time the CMD 2 QED signal is latched (i.e., time T 4 ) before outputting the CMD 2 QED signal as the QED 2 TREE signal to the DLL 2 TREE, as illustrated in  FIG. 2  by the two tCKs between time T 4  and time T 5 . At time T 5 , the rising clock edge of the DLL 2 TREE coincides with the QED 2 TREE signal (not shown) as it is output to the command tree  168 . After a propagation delay through the command tree  168 , the QED 2 TREE signal is provided as the QED 2 DQOUT signal to the data circuits  174  to enable the output of data responsive to the DLL 2 DQOUT signal (i.e., the DLL 2 TREE signal distributed by the DLL tree  122 ). The data, after the propagation delay of the data receiver/transmitter  178 , is output coincident with the CLK signal, as illustrated at time T 6  by the DQ signal and the CLK signal being substantially aligned (i.e., in phase). The time between T 5  and T 6  is substantially equal to the time between T 0  and T 1 , both of which represent a propagation delay through the DLL tree  122  (and command tree  168 ), and through the data circuits  174  and data receiver/transmitter  178  of the data block  170 . 
     It will be appreciated from the example operation that the rising clock edge of the DLL 2 TREE signal at time T 5  is used to clock the command block  166  to output the QED 2 TREE signal, and after being distributed through the DLL tree  122 , to further clock the data circuits  174 . The timing of the DLL 2 TREE signal is such that upon arrival of the QED 2 DQOUT signal at the data circuits  174  data is output to the data receiver/transmitter  178 , to in turn be output coincident with the seventh rising clock edge following the rising clock edge coincident with the input of the CMD signal to the command receiver  154  (i.e., CAS latency of seven tCKs). 
     Although the previous example was described with specific reference to a read command, embodiments of the invention may be applied to other types of commands as well. For example, an on-die termination (ODT) command which is used to activate ODT circuitry when data is written to memory. Other types of commands may be used as well. 
       FIG. 3  illustrates a timing calibration block  200  according to an embodiment of the invention. In some embodiments, the timing calibration block  200  may be used for the timing calibration block  180  of  FIG. 1 . The timing calibration block  200  provides a CLCOUNTADJ shift count of the number of tCKs a command block, for example, command block  166 , should delay CMD 2 QED signals before being provided to the command tree  168  responsive to the DLL 2 TREE signal. 
     The CLCOUNTADJ shift count is based at least in part on the number of tCKs of path delay of various circuits in the clock path  100  and command path  150 . For example, in the embodiment of the timing calibration block  200  of  FIG. 3 , a CLCOUNTADJ shift count is equal to the difference between a CAS latency value and the number of tCKs of path delay attributable to (1) the clock receiver  110  through the command buffer and timing adjustment block  164  and (2) the DLL tree  122  through the data receiver/transmitter  178 . The blocks in the timing calibration block in the embodiment of  FIG. 3  are included because the sum propagation delay through the blocks represents a minimum asynchronous path delay of the command signal CMD from input through to the data circuits  174  (i.e., path delay (1) from above), and the output of data (in response to the CMD signal) through the data receiver/transmitter  178  (i.e., path delay (2) from above). 
     The timing calibration block  200  includes a ring counter  210  that is configured to receive the DLL 2 TREE clock signal output by the DLL  118  and output a ring count RINGCOUNT. The RINGCOUNT is split so that at least some of the bits (i.e., binary digits) are provided to a path delay measurement circuit  220  and at least some one of the remaining bits are provided through a model delay path  230 ,  240 . The model delay path  230  models at least a portion of a data circuit path delay, and in the embodiment of  FIG. 3 , includes DLL tree model delay  232 , data circuit model delay  234  and data receiver/transmitter model delay  236  to model the propagation delay attributable to the DLL tree  122  though the data receiver/transmitter  178 . The model delay path  240  includes clock receiver model delay  242 , clock buffer model delay  244 , AL shifter model delay  246 , and command buffer and timing adjustment block model delay  248  to model at least a portion of a command path delay of the command path  150 . The model delay path  240  models the path delay for a CMD input to the command receiver  154  through to the command buffer and timing adjustment block  164 . The output from the model delay path  240  is provided to the path delay measurement circuit  220 , which is configured to determine (e.g., calculate) the CLCOUNTADJ shift count that represents a difference between a CAS latency value and the number of tCKs of path delay through the model delay paths  230 ,  240  (which model the path delay through the clock and command paths  100 ,  150 ). 
     Although the timing calibration block  200  of  FIG. 3  illustrates particular blocks of model delays, in other embodiments of a timing calibration block may include greater or fewer model delays. For example, in some embodiments, a timing calibration block may include a model delay to model propagation delay of a command block of a command path. In some embodiments of a timing calibration block, some of the model delays described with reference to  FIG. 3  may not be included. In some embodiments, a model delay included in a timing calibration block may have a different delay than the corresponding block of the clock or command paths which it is modeling. For example, the command buffer and timing adjustment block model delay  248  may have a longer delay than the command buffer and timing adjustment block  164 . In this manner, the propagation delay of another block of the clock or command paths, such as the propagation delay of the command block  166  which does not have a corresponding model delay in the timing calibration block  200 , may be considered in the calculation by the timing calibration block. 
     In some embodiments, circuitry of another circuit block may be used as model delays for a timing calibration block. For example, the DLL block  118  may include various circuitry that may be used to model propagation delay of blocks of the clock or command paths. The feedback path of the DLL block  118  may include blocks that can be used to model delays in the model delay path  230 ,  240 . For example, a feedback path  400  for a DLL according to an embodiment of the invention is illustrated in  FIG. 4 . The feedback path  400  includes DLL tree model delay  432 , data input/output circuit model delay  434  and data receiver/transmitter model delay  436 . The feedback path  300  further includes clock receiver model delay  442  and clock buffer model delay  444 . The output of the feedback path  400  is provided to a phase detector  450 . The phase detector  450  may be included in a DLL block, for example, DLL  118  of  FIG. 1 . Some or all of the model delays of the feedback path  400  may be used by a timing calibration block, such as the timing calibration block  200  of  FIG. 3 . For example, instead of the timing calibration block  200  having dedicated DLL tree model delay  232 , data circuit model delay  234  and data receiver/transmitter model delay  236 , the model delays  432 - 444  of the feedback path  400  may be used instead. Other common models delays may be used as well instead of having a separate and dedicated model delay in the timing calibration block  200 . 
       FIG. 5  illustrates a timing diagram of various signals during operation of the timing calibration block  200  according to an embodiment of the invention. At time T 0 , the ring counter  210  begins generating the RINGCOUNT responsive to a rising clock edge of the DLL 2 TREE signal, as illustrated in  FIG. 5  by the leading clock edge of RINGCOUNT&lt; 0 &gt;. The ring counter  210  is configured to provide (e.g., generate, output, etc.) a sequence of RINGCOUNT signals where each succeeding RINGCOUNT signal has a rising clock edge corresponding to a falling clock edge of the previous RINGCOUNT signal. For example, as illustrated in  FIG. 5 , at time T 2  the RINGCOUNT&lt; 1 &gt; signal has a rising clock edge that corresponds to a falling clock edge of RINGCOUNT&lt; 0 &gt; and at time T 5  the RINGCOUNT&lt; 2 &gt; signal has a rising clock edge that corresponds to a falling clock edge of RINGCOUNT&lt; 1 &gt;. To begin the sequence of the RINGCOUNT signals again, the RINGCOUNT&lt; 0 &gt; signal will have a next rising clock edge corresponding to (e.g., coincident with) a falling clock edge of the last RINGCOUNT signal, and each succeeding RINGCOUNT signal will transition as previously described. 
     With reference to  FIG. 5 , at time T 1 , the rising clock edge of RINGCOUNT&lt; 0 &gt; signal has propagated through the model delay path  230  (representing the propagation delay through data circuitry) and is output to the model delay path  240 . At time T 3 , the rising clock edge of the RINGCOUNT&lt; 0 &gt; signal is output from the model delay path  240  as a QED 2 CAL signal to the path delay measurement circuit  220  so that the CLCOUNTADJ shift count may be calculated. The additional delay from time T 1  to time T 3  is due to the delay of model delays  242 - 248 , and represents a minimum propagation delay of a CMD signal from input to the command receiver  154  to output as the CMD 2 QED signal to the command block  166 . 
     The total delay of the RINGCOUNT&lt; 0 &gt; signal from time T 0  to T 3  represents the minimum propagation delay (i.e., without any additional delay added by the command buffer and timing adjustment block model delay  248 ) through the model delay paths  230 ,  240 . That is, the delay of RINGCOUNT&lt; 0 &gt; through the model delay paths  230 ,  240 , as represented by the difference in time between times T 0  and T 3 , models the delay from, for example, the input of the CMD signal to the command receiver  154  to when data is output from the data receiver/transmitter  178 , but without any additional delay added by the command buffer and timing adjustment block  164  of  FIG. 1 . 
     As will be described in more detail below, additional delay through the model delay paths  230 ,  240  may be added by the command buffer and timing adjustment block model delay  248 . The delay added by block  248  mirrors additive delay added by the command buffer and timing adjustment block  164  of the command path  150  ( FIG. 1 ). The CMD 2 QED signal (i.e., RINGCOUNT&lt; 0 &gt; plus delay of the model delay paths  230 ,  240 ) with additive delay added by the command buffer and timing adjustment block model delay  248  is shown in  FIG. 5  as well. The additionally delayed CMD 2 QED signal is illustrated with a rising clock edge at time T 4 , which corresponds with a falling clock edge of the DLL 2 TREE signal. The delay between times T 3  and T 4  represents the additional delay provided by the command buffer and timing adjustment block model delay  248 . 
     In determining the CLCOUNTADJ shift count, the path delay measurement circuit  220  uses RINGCOUNT&lt; 1 : n &gt; signals to determine the number of tCKs of delay through the model delay paths  230 ,  240 . The number of tCKs of path delay may be a next higher whole number for any fractional tCK of delay through the model delay paths  230 ,  240 . For example, as shown in  FIG. 5 , the delay through the model delay paths  230 ,  240  (with the additive delay from the command buffer and timing adjustment block model delay  248 ) is greater than one tCK (i.e., represented by a rising clock edge of the DLL 2 TREE signal at time T 2 ) but less than two tCKs (i.e., represented by a rising clock edge of the DLL 2 TREE signal at time T 5 ). As a result, the path delay measurement circuit  220  uses a path delay of two tCKs in calculating the CLCOUNTADJ shift count. 
       FIG. 6  illustrates a timing adjustment block  600  according to an embodiment of the invention, and a timing diagram of various signals during operation of the same. The timing adjustment block  600  may be included in the command buffer and timing adjustment block  164  ( FIG. 1 ). The timing adjustment block  600  is configured to determine an amount of additive delay to add to a path delay of the command path  150 , for example, to align a leading clock edge of the CMD 2 QED signal with a clock edge of the DLL 2 TREE signal. As previously discussed, the additive delay provided by the timing adjustment block  600  (i.e., command buffer and timing adjustment block  164 ) may be mirrored by a command buffer and timing adjustment block model delay in a timing calibration block  180 , for example, command buffer and timing adjustment block model delay  248  of timing calibration block  200  of  FIG. 3 . 
     The timing adjustment block  600  includes a plurality of unit delays and comparators  610 ( 0 )- 610 ( n ) that may be used to selectively add delay to the command path  150 . For example, in the embodiment illustrated in  FIG. 6 , the additive delay is added to the CMDXCLK signal output by the AL shifter  162  ( FIG. 1 ) of the command path  150  in units of unit delay. The length of delay of the unit delays are typically one tCK or less (i.e., one clock period of the CLK signal) so that sufficient delay resolution is provided by the incremental delay added by a unit delay. In some embodiments, the number of unit delays and comparators  610 ( 0 )- 610 ( n ) is based at least in part on providing a total delay that is approximately equal to the slowest tCK at a fastest operating condition for the memory in which the timing and adjustment block  600  is included. In a particular example, the maximum delay of the timing adjustment block  600  is 2.5 ns, and includes 12 unit delays and comparators  610 , each unit delay 225 ps. 
     The determination (e.g., selection) of the number of unit delays to add to the path delay is made at least in part through the use of the comparators of the unit delays and comparators  610 ( 0 )- 610 ( n ). The comparators are configured to compare the DLL 2 TREE signal and the delayed CMDXCLK signal output by the respective unit delay. For example, in some embodiments of the invention, the comparator that detects a transition of the DLL 2 TREE signal (e.g., a falling clock edge) is the comparator of the unit delay and comparators  610  that is selected as the last unit delay added by the command buffer and timing adjustment block  164  to the path delay of the command path  150 . 
     An example of the operation of the timing and adjustment block  600  will be described with reference to the timing diagram of  FIG. 6 . The timing diagram of  FIG. 6  illustrates a leading clock edge (i.e., a rising clock edge) of the CMDXCLK signal at time T 0  input to a first unit delay and comparator  610 ( 0 ). The delayed CMDXCLK signal output by the unit delay and comparator  610 ( 0 ) is illustrated by the delayed rising clock edge at time T 1  output by the unit delay and comparator  610 ( 1 ). The further delayed CMDXCLK signal is illustrated as well, and has a rising clock edge output by the unit delay and comparator  610 ( 2 ) at time T 3 . As illustrated in example of  FIG. 6 , the DLL 2 TREE signal, which is provided to the unit delays and comparators  610 ( 0 )- 610 ( n ), has a falling clock edge that is detected by the unit delay and comparator  610 ( 1 ). As a result, the unit delay and comparator  610 ( 1 ) represents the last unit delay to be added to the CMDXCLK signal (i.e., add two unit delays) by the timing adjustment block  600  before being output by the command buffer and timing adjustment block  164  to the command block as the CMD 2 QED signal. 
       FIG. 7  illustrates logic  700  included in a path delay measurement circuit according to an embodiment of the invention. The logic  700  may be, for example, included in the path delay measurement circuit  220  ( FIG. 3 ). The logic  700  includes a plurality of logic blocks  710 ( 0 )- 710 ( n −1). Each of the logic blocks  710  receive signals LAT&lt;n&gt; indicative of the CAS latency value “n” for the memory, as well as signals CPIstCK&lt;m&gt; indicative of the number “m” of tCKs of delay through, for example, model delay paths  230 ,  240 . A shift count CMDSHIFT&lt;n-m&gt; based at least in part on the LAT&lt;n&gt; and CPIstCK&lt;m&gt; signals is determined by the logic blocks  710 . The CMDSHIFT&lt;n-m&gt; shift count is provided to the command block  166  as the CLCOUNTADJ shift count to be used in setting the number (n-m) of tCKs the CMD 2 QED signal is delayed before being output to the command tree  168  responsive to the DLL 2 TREE signal. 
     In operation, in the embodiment of  FIG. 7  each of the logic blocks  710  compares pairs of LAT&lt;n&gt; and CPIstCK&lt;m&gt; signals to determine if a true condition exits. The logic block  710  that determines a true condition of one of its LAT&lt;n&gt;-CPIstCK&lt;m&gt; pairs outputs its respective CMDSHIFT&lt;n-m&gt; shift count. For example, the logic block  710 ( 0 ) receives LAT&lt;n&gt;-CPIstCK&lt;m&gt; pairs of LAT&lt; 5 &gt;-CPIstCK&lt; 5 &gt;, LAT&lt; 6 &gt;-CPIstCK&lt; 6 &gt;, . . . LAT&lt;n&gt;-CPIstCK&lt;m&gt;. The logic block  710 ( 0 ) will output a CMDSHIFT&lt; 0 &gt; signal indicating a CLCOUNTADJ of zero tCKs (i.e., the CMD 2 QED signals are not shifted by any tCKs before being output) when any of the LAT&lt;n&gt;-CPIstCK&lt;m&gt; signals it receives is true, that is, if the latency value is 5 and the delay through the model delay paths is 5 tCKs; if the latency value is 6 and the delay through the model delay paths is 6 tCKs; and if the latency value is n and the delay through the model delay paths is m tCKs, where n=m. The LAT&lt;n&gt;-CPIstCK&lt;m&gt; signal pairs provided to the logic block  710 ( 1 ) are different combinations where (m-n)=1. Although not expressly illustrated in  FIG. 7 , additional logic blocks  710  are included for different combinations of (m-n), for example, (m-n)=2, (m-n)=3, until (m-n)=(n−1). As a result, the logic blocks  710  of the logic  700  may provide CMDSHIFT signals over a range of zero through (m-n) tCKs to set the command block  166  to add delay between zero tCKs through (m-n) tCKs to the CMD 2 QED signals. 
       FIG. 8  illustrates a clock path  800  and a command path  850  according to an embodiment of the invention. A data block  870  including a plurality of data circuits  874  and a data receiver/transmitter  878  is coupled to the clock path  800  and the command path  850 . A timing calibration block  880  is coupled to the command path  850  and provides a shift count CLCOUNTADJ to the command path  850 . The clock path  800 , data block  870 , and the timing calibration block  880  may be the same as the clock path  100 , the data block  170 , and the timing calibration block  180  of  FIG. 1 . The command path  850  is similar to the command path  150 , however, as shown in  FIG. 8 , the command path  850  is for an on-die termination (ODT) command. As known an ODT command is used to enable on-die termination circuits included in the data block  870  for impedance matching, for example, to reduce signal reflection and interference of data signals on external signal lines coupled to the data block  870 . The ODT command should be provided to enable the termination circuits at an appropriate time, for example, after expiration of a CAS write latency and at the same time write data is received by the data block  870 . 
     The command path  850  may be configured to provide an ODT command CMD, from an input to the data block  870 . The command path  850  includes a command receiver  854  that is configured to receive the CMD and provide an output command signal CMDOUT to a command latch  858 . The command latch  858  latches the CMDOUT signal and outputs it as an CMD 2 ALSH signal to an additive latency (AL) shifter  862  responsive to the CLK 2 DEC signal from the clock buffer  814  of the clock path  800 . The AL shifter  862  is configured to shift the CLK 2 ALSH signal through it responsive the CLK 2 ALSH signal from the clock buffer  814  of the clock path  800 . After the CMD 2 ALSH signal is shifted to provide the additive latency, it is output by the AL shifter  862  as output command signal CMDXCLK to command buffer and timing adjustment block  864  which is configured to provide additional delay to the propagation of the CMD signal through the command path  850 . Following the delay provided by the timing adjustment block  864 , the CMDXCLK signal is output as a CMD 2 QSH signal to ODT command block  866 . The ODT command block  866  provides the CMD 2 SH signal as a ODTEN 2 TREE signal to a ODT tree  868  responsive to the DLL 2 TREE signal from the DLL block  818  from the clock path  800 . 
     The ODT command block  866  may output the ODTEN 2 TREE signal following a delay that is based at least in part on a shift count CLCOUNTADJ provided by timing calibration block  880 . For example, in some embodiments, the ODT command block  866  provides a delay based at least in part on a difference between a CAS write latency (e.g., programmed by a user) and a path delay measured in a number of tCKs by the timing calibration block  880 . The ODT tree  868  is configured to distribute the ODTEN 2 TREE signal as ODTEN 22 DQOUT signals to a plurality of data input/output circuits  874  of data block  870 . The ODTEN 2 DQOUT signals may, for example, be used to enable ODT circuits of the data input/output circuits  874  such that the ODT circuits are enabled at the appropriate time, for example, to match impedance. As appreciate by those ordinarily skilled in the art, operation of the command path  850  may be similar to the operation of the command path  850 , as previously described. 
       FIG. 9  illustrates a portion of a memory  900  according to an embodiment of the present invention. The memory  900  includes an array  902  of memory cells, which may be, for example, DRAM memory cells, SRAM memory cells, flash memory cells, or some other types of memory cells. The memory  900  includes a command decoder  906  that receives memory commands through a command bus  908  and provides (e.g. generates) corresponding control signals within the memory  900  to carry out various memory operations. Row and column address signals are provided (e.g., applied) to the memory  900  through an address bus  920  and provided to an address latch  910 . The address latch then outputs a separate column address and a separate row address. 
     The row and column addresses are provided by the address latch  910  to a row address decoder  922  and a column address decoder  928 , respectively. The column address decoder  928  selects bit lines extending through the array  902  corresponding to respective column addresses. The row address decoder  922  is connected to word line driver  924  that activates respective rows of memory cells in the array  902  corresponding to received row addresses. The selected data line (e.g., a bit line or bit lines) corresponding to a received column address are coupled to a read/write circuitry  930  to provide read data to an input/output data block  934  via an input-output data bus  940 . Write data are provided to the memory array  902  through the I/O data block  934  and the memory array read/write circuitry  930 . the I/O data block  934  may include clocked circuitry that operate responsive to an internal clock signal DLL 2 DQOUT and an internal command signal QED 2 DQOUT, for example. 
     The memory  900  further includes clock path  912  and command path  914 . The clock path  912  receives a input clock signal CLK and propagates the internal clock signal DLL 2 DQOUT which is based at least in part on the CLK signal to the I/O data block  934 . The command path  914  may be implemented using a command path according to an embodiment of the invention. The command path  914 , which is shown in  FIG. 9  as being included in the command decoder  906 , but is not limited to such a configuration, provides the internal command signal QED 2 DQOUT to the I/O data block  934 . The command decoder  906  responds to memory commands provided to the command bus  908  to perform various operations on the memory array  902 . In particular, the command decoder  906  is used to provide internal control signals to read data from and write data to the memory array  902 . 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.