Patent Publication Number: US-9431249-B2

Title: Edge termination for super junction MOSFET devices

Description:
BACKGROUND 
     There are different types of edge terminations used in metal-oxide semiconductor field-effect transistor (MOSFET) devices. For example, in conventional MOSFETs the edge termination consists of a set of floating field rings/field plates across which the potential drops in a step wise fashion from the source potential to the drain potential. Recently a new type of MOSFET, commonly known as Super Junction MOSFET (SJMOSFET), has been designed that employs order of magnitude higher drift layer concentration resulting in very low on resistance for a given breakdown voltage. This is accomplished by the incorporation of P type vertical junction regions in the core drift region. The field ring based edge termination used for a conventional MOSFET is deemed unsuitable for the SJMOSFET. Its breakdown voltage will be much lower than the core breakdown voltage. As such, different edge termination schemes are generally employed. 
     For example, one of the edge terminations used for the SJMOSFET is a source field plate running over a thick low temperature oxide (LTO) layer over the termination region. The source field plate together with the floating P columns underneath it supports the source drain potential. While this is an acceptable edge termination for the SJMOSFET and is used commonly, it has the drawback of causing electric arcing between the unexposed areas of the source metal field plate and the drain for breakdown voltage higher than the potential at which air breakdown takes place (around 400V). In order to avoid electric arcing between the source field plate and the drain, the field plate is covered with a passivation layer, such as silicon nitrogen (SiN). However, because of the brittle characteristics of SiN and also the sharp features of the etched metal field plate edges, passivation cracks occur leading to the generation of arcing to air. To avoid such arcing potential it is necessary to cover the metal with a crack free passivation layer. 
     Therefore, while there are advantages associated with Super Junction MOSFET devices, there are also disadvantages associated with them when it comes to the edge termination areas. As explained earlier, one of the disadvantages is that when a field plate is incorporated into a Super Junction MOSFET device, a thick oxide (e.g., approximately 5-6 micrometers thick for a 600V device) is utilized. It is also necessary to coat the field plate with passivation material, such as SiN and Polyimide in order to prevent electrical arcing between the edge of the metal field plate and the drain (the scribe line). 
     SUMMARY 
     Given the disadvantages associated with the edge termination areas of Super Junction MOSFET devices, it is desirable that a field ring based edge termination be designed which drops the potential gradually from that of the source potential to the drain potential which does not stress the source metal above the ionizing potential of air. 
     In one embodiment, a Super Junction MOSFET device can include a substrate and a charge compensation region located above the substrate. The charge compensation region can include a plurality of columns of P type dopant within an N type dopant region. In addition, the Super Junction MOSFET can include a termination region located above the charge compensation region and the termination region can include an N− type dopant. Furthermore, the Super Junction MOSFET can include an edge termination structure. The termination region includes a portion of the edge termination structure. 
     In an embodiment, the Super Junction MOSFET device described above can further include a field effect transistor, wherein the termination region includes a portion of the field effect transistor. In accordance with various embodiments, the edge termination structure mentioned above can include, but is not limited to, a field ring, a field plate, and/or a junction termination extension. In addition, in various embodiments, the edge termination structure mentioned above can include, but is not limited to, a set of field rings and field plates. In one embodiment, the edge termination structure mentioned above can include, but is not limited to, a set of field plates. In an embodiment, the edge termination structure mentioned above can include, but is not limited to, a junction termination extension region. In one embodiment, the field effect transistor described above can include a P type dopant region that merges with one of the plurality of columns of P type dopant. In an embodiment, the field effect transistor described above includes a junction field effect transistor. 
     In another embodiment, a Super Junction MOSFET device can include a substrate and a charge compensation region located above the substrate. The charge compensation region can include a plurality of columns of N type dopant within a P type dopant region. Additionally, the Super Junction MOSFET can include a termination region located above the charge compensation region and the termination region can include a P− type dopant. Moreover, the Super Junction MOSFET can include an edge termination structure, wherein the termination region includes a portion of the edge termination structure. 
     In one embodiment, the Super Junction MOSFET device described in the previous paragraph can further include a field effect transistor, wherein the termination region includes a portion of the field effect transistor. In accordance with various embodiments, the edge termination structure mentioned in the previous paragraph can include, but is not limited to, a field ring, a field plate, and/or a junction termination extension. Furthermore, in various embodiments, the edge termination structure mentioned above can include, but is not limited to, a set of field rings and field plates. In one embodiment, the edge termination structure mentioned above can include, but is not limited to, a set of field plates. In an embodiment, the edge termination structure mentioned above can include, but is not limited to, a junction termination extension region. In an embodiment, the field effect transistor described in the previous paragraph can include an N type dopant region that merges with one of the plurality of columns of N type dopant. In one embodiment, the field effect transistor described in the previous paragraph includes a junction field effect transistor. 
     In yet another embodiment, a method can include generating a charge compensation region of a Super Junction MOSFET device. Note that the charge compensation region is located above a substrate and includes a plurality of columns of first type dopant within a second type dopant region. Furthermore, the method can include generating a termination region located above the charge compensation region and including a lower concentration of the second type dopant than the second type dopant layer. Additionally, the method can include generating an edge termination structure such that the termination region includes at least a portion of the edge termination structure. 
     In one embodiment, the first type dopant described in the previous paragraph includes a P type dopant and the second type dopant includes an N type dopant. In an embodiment, the first type dopant described in the previous paragraph includes an N type dopant and the second type dopant includes a P type dopant. In accordance to various embodiments, the edge termination structure described in the previous paragraph can be selected from the group of a field ring, a field plate, and a junction termination extension. Additionally, in various embodiments, the edge termination structure described in the previous paragraph can include, but is not limited to, a set of field rings and field plates. In one embodiment, the edge termination structure described in the previous paragraph can include, but is not limited to, a set of field plates. In an embodiment, the edge termination structure described in the previous paragraph can include, but is not limited to, a junction termination extension region. In one embodiment, the method described in the previous paragraph can further include generating a field effect transistor such that the termination region includes at least a portion of the field effect transistor. In an embodiment, the generating the field effect transistor further includes generating the field effect transistor that includes a region of the first type dopant that merges with one of the plurality of columns of first type dopant. 
     While particular embodiments in accordance with the invention have been specifically described within this Summary, it is noted that the invention and the claimed subject matter are not limited in any way by these embodiments. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Within the accompanying drawings, various embodiments in accordance with the invention are illustrated by way of example and not by way of limitation. It is noted that like reference numerals denote similar elements throughout the drawings. 
         FIG. 1  is a side sectional view of an edge termination area of a Super Junction MOSFET device in accordance with various embodiments of the invention. 
         FIG. 2  is side sectional view of another edge termination area of a Super Junction MOSFET device in accordance with various embodiments of the invention. 
         FIG. 3  is a graph of the current/voltage breakdown characteristic of a simulated Super Junction MOSFET device including an edge termination area in accordance with various embodiments of the invention. 
         FIG. 4  illustrates a potential distribution at the breakdown voltage of a simulated Super Junction MOSFET device including an edge termination area in accordance with various embodiments of the invention. 
         FIG. 5  illustrates an impact ionization distribution at the breakdown voltage of a simulated Super Junction MOSFET device including an edge termination area in accordance with various embodiments of the invention. 
         FIGS. 6-8  illustrate a process for fabricating a junction termination extension (JTE) within an edge termination area of a Super Junction MOSFET device in accordance with various embodiments of the invention. 
         FIG. 9  is a side sectional view of a planar Junction Field Effect Transistor (JFET) implemented as part of a termination area of a Super Junction MOSFET device in accordance with various embodiments of the invention. 
         FIG. 10  is a side sectional view of an edge termination area of a trench Super Junction MOSFET device in accordance with various embodiments of the invention. 
         FIG. 11  is flow diagram of a method in accordance with various embodiments of the invention. 
         FIGS. 12-24  illustrate a process for fabricating multiple P regions or columns as part of a Super Junction MOSFET device in accordance with various embodiments of the invention. 
     
    
    
     The drawings referred to in this description should not be understood as being drawn to scale except if specifically noted. 
     DETAILED DESCRIPTION 
     Reference will now be made in detail to various embodiments in accordance with the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with various embodiments, it will be understood that these various embodiments are not intended to limit the invention. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the scope of the invention as construed according to the Claims. Furthermore, in the following detailed description of various embodiments in accordance with the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be evident to one of ordinary skill in the art that the invention may be practiced without these specific details or with equivalents thereof. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the invention. 
     Some portions of the detailed descriptions that follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations for fabricating semiconductor devices. These descriptions and representations are the means used by those skilled in the art of semiconductor device fabrication to most effectively convey the substance of their work to others skilled in the art. In the present application, a procedure, logic block, process, or the like, is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present application, discussions utilizing terms such as “generating,” “creating,” “forming,” “performing,” “producing,” “depositing,” “etching” or the like, refer to actions and processes of semiconductor device fabrication. 
     The figures are not drawn to scale, and only portions of the structures, as well as the various layers that form those structures, may be shown in the figures. Furthermore, fabrication processes and steps may be performed along with the processes and steps discussed herein; that is, there may be a number of process steps before, in between and/or after the steps shown and described herein. Importantly, embodiments in accordance with the invention can be implemented in conjunction with these other (perhaps conventional) processes and steps without significantly perturbing them. Generally speaking, embodiments in accordance with the invention can replace portions of a conventional process without significantly affecting peripheral processes and steps. 
     As used herein, the letter “N” refers to an N− type dopant and the letter “P” refers to a P− type dopant. A plus sign “+” or a minus sign “−” is used to represent, respectively, a relatively high or relatively low concentration of the dopant. 
     The term “channel” is used herein in the accepted manner. That is, current moves within a FET in a channel, from the source connection to the drain connection. A channel can be made of either n-type or p-type semiconductor material; accordingly, a FET is specified as either an n-channel or p-channel device. Note that the figures are discussed in the context of an n-channel device, specifically an n-channel Super Junction MOSFET. However, embodiments in accordance with the invention are not so limited. The discussion of the figures can be readily mapped to a p-channel device by substituting n-type dopant and materials for corresponding p-type dopant and materials, and vice versa. 
       FIG. 1  is a side sectional view of an edge termination area of a Super Junction metal-oxide semiconductor field-effect transistor (MOSFET) device  100  in accordance with various embodiments of the invention. In one embodiment, the Super Junction MOSFET device  100  can include a substrate  102  and a charge compensation region  118  located above and coupled to the substrate  102 . The charge compensation region  118  can include multiple P regions or columns  106  within an N epitaxial region  104 . As such, the charge compensation region  118  can include alternating N and P regions which form what is known as a Super Junction. In addition, the Super Junction MOSFET device  100  can include a termination region  108  located above and coupled to the charge compensation region  118 , wherein the termination region  108  can be implemented as an N− epitaxial layer. Within the present embodiment, the Super Junction MOSFET device  100  can include one or more field rings  110 , one or more field plates  112 , a source  114 , and a drain  116 . In addition, in one embodiment the drain  116  is connected to a drain (not shown) located beneath the substrate  102 . It is pointed out that the termination region  108  of the Super Junction MOSFET device  100  can include at least a portion of the one or more field rings  110  and the one or more field plates  112 . 
     Note that the Super Junction MOSFET device  100  can be implemented in a wide variety of ways in accordance with embodiments of the invention. For example in an embodiment, the Super Junction MOSFET device  100  can include one or more edge termination structures, wherein the termination region  108  can include at least a portion of each of the edge termination structures. It is pointed out that the edge termination structures of the Super Junction MOSFET device  100  can be implemented in a wide variety of ways. For example, the edge termination structures can include, but are not limited to, one or more field rings  110 , one or more field plates  112 , and/or one or more junction termination extensions (JTEs). In one embodiment, the edge termination structures can include, but are not limited to, a set of field rings  110  and field plates  112 . In an embodiment, the edge termination structures can include, but are not limited to, a set of field plates  112 . In an embodiment, the edge termination structures can include, but are not limited to, one or more junction termination extension regions. 
     Within  FIG. 1 , it is noted that the P regions  106  can be generated or created in a wide variety of ways in accordance with embodiments of the invention. For example, as shown in the present embodiment, the P regions  106  can be generated by forming multiple heavier doped N epitaxial layers  104  above substrate  102  and implanting within each layer multiple P regions (e.g., boron) such that the resulting implanted P regions are vertically stacked. Next, an N− epitaxial layer  108  can be formed above the multiple N epitaxial layers  104  implanted with vertically stacked P regions. Subsequently, when the stacked implanted P regions of the different epitaxial layers  104  are thermally defused, the stacked implanted P regions vertically merge together to form multiple P regions or columns  106  as shown in the present embodiment. It is pointed out that additional figures and description are included herein involving the generation of the P columns  106  in this manner. 
     Within  FIG. 1 , in one embodiment of the Super Junction MOSFET device  100 , it is noted that the doping of the top termination region  108  (e.g., N− epitaxial layer) is lighter or has a lower concentration than the doping of the N epitaxial region  104 . In an embodiment, one way of forming the termination region  108  is by implanting an N− dopant into the top surface of the N epitaxial region  104  thereby creating the termination layer  108  having an N− epitaxial layer. Moreover, note that the top termination layer  108  can be implemented in a wide variety of ways. For example in one embodiment, the net doping of the N− epitaxial layer  108  can be implemented at approximately 2.6×10 14 /cm 3  while the net doping of the N epitaxial region  104  can be implemented at approximately 3×10 15 /cm 3 . 
     Furthermore, in an embodiment, note that the thickness of the edge termination layer  108  can be chosen and implemented such that any P body regions of the MOSFET section may merge with one or more of the P columns  106  of the charge compensation region  118 . In addition, field rings  110 , field plates  112 , and/or JTEs (not shown in  FIG. 1 ) can each be constructed as part of the edge termination section  108 . Within the present embodiment of the Super Junction MOSFET device  100 , two of the field rings  110  along with the field plate  112  touch the P columns  106  of the charge compensation region  118 . However, it is noted that in one embodiment, the Super Junction MOSFET device  100  can be implemented such that none of the P regions  106  touch any field rings  110  and/or any field plates  112 . 
     Within  FIG. 1 , in an embodiment, the Super Junction MOSFET device  100  can be implemented such that the charge compensation region  118  extends all the way into the termination region or layer  108 . Moreover, the termination layer  108  can include any MOS gate structures in the active region in addition to any field rings  110 , field plates  112 , and/or any JTE regions. One of the advantages of the Super Junction MOSFET device  100  is that the surface electric field is substantially lower than the bulk electric field at the breakdown voltage, which increases the ruggedness of the device  100 . Additionally, another advantage of the edge termination region of the Super Junction MOSFET device  100  is that it does not involve the use of implementing metal field plate over thick low temperature oxide (LTO) and it also does not involve utilizing polyimide passivation to prevent arcing. 
     It is pointed out that  FIG. 1  includes both an X-axis and Y-axis that illustrate the cross sectional size of the Super Junction MOSFET device  100 . Specifically, the X-axis of  FIG. 1  includes a micron (or micrometer) scale while the Y-axis includes a micron (or micrometer) scale. 
     Note that the Super Junction MOSFET device  100  may not include all of the elements illustrated by  FIG. 1 . Additionally, the Super Junction MOSFET device  100  can be implemented to include one or more elements not illustrated by  FIG. 1 . It is pointed out that the Super Junction MOSFET device  100  can be utilized or implemented in any manner similar to that described herein, but is not limited to such. 
       FIG. 2  is a side sectional view of an edge termination area of a Super Junction MOSFET device  200  in accordance with various embodiments of the invention. Note that the Super Junction MOSFET device  200  of  FIG. 2  is similar to the Super Junction MOSFET device  100  of  FIG. 1 . However, the P regions or columns  106 ′ of the Super Junction MOSFET device  200  are fabricated in a different manner than that shown within the Super Junction MOSFET device  100  of  FIG. 1 . 
     Specifically, the P regions  106 ′ of the Super Junction MOSFET device  200  can be generated by forming a heavier doped N epitaxial region  104  above and coupled to the substrate  102 . Subsequently, a deep trench etch process can be performed to create or generate multiple trenches within the N epitaxial region  104 . Afterward, a P type dopant material is filled or formed within the multiple trenches of the N epitaxial region  104  thereby generating or creating the P regions or columns  106 ′. Next, an N− epitaxial layer can be formed above a charge compensation region  118 ′ to generate or create the termination region  108  which also encapsulates the P regions or columns  106 ′. It is pointed out that additional figures and description are included herein involving the generation of the P columns  106 ′ in this manner. Note that in one embodiment, just one set of masks is used to create the P regions  106 ′ within the N channel Super Junction MOSFET device  200 . 
     It is noted that the Super Junction MOSFET device  200  may not include all of the elements illustrated by  FIG. 2 . Moreover, the Super Junction MOSFET device  200  can be implemented to include one or more elements not illustrated by  FIG. 2 . Note that the Super Junction MOSFET device  200  can be utilized or implemented in any manner similar to that described herein, but is not limited to such. 
       FIG. 3  is a graph  300  that illustrates the current/voltage breakdown characteristic of the simulated Super Junction MOSFET device  200  which includes an edge termination area in accordance with various embodiments of the invention. Specifically, the X-axis of the graph  300  represents the source voltage (V) of the simulated Super Junction MOSFET device  200  while the Y-axis of the graph  300  represents the substrate current (A) of the simulated Super Junction MOSFET device  200 . In addition, curve  302  of the graph  300  represents the current/voltage breakdown characteristic of the simulated Super Junction MOSFET device  200 . 
       FIG. 4  illustrates a potential distribution at the breakdown voltage of the simulated Super Junction MOSFET device  200  which includes an edge termination area in accordance with various embodiments of the invention. Within  FIG. 4 , it can be seen that the charge compensation area is depleted both vertically and laterally. For example, the vertical depletion region width is approximately 45 microns (or micrometers) and the lateral depletion width is approximately 120 microns (or micrometers) from the edge of the P body which is at the Source potential. As such, the size of the Super Junction MOSFET device  200  can be reduced when implemented in accordance with an embodiment of the invention. It is pointed out that reference numeral  410  indicates the bulk breakdown of the Super Junction MOSFET device  200 , which is a desirable result. 
     It is pointed out that reference numeral  402  indicates the area of the simulated Super Junction MOSFET device  200  that is at the breakdown voltage of approximately 740 V, reference numeral  404  indicates the area of the simulated Super Junction MOSFET device  200  that is at approximately 648 V, and reference numeral  406  indicates the area that is at approximately 463 V. Furthermore, reference numeral  408  indicates the area of the simulated Super Junction MOSFET device  200  that is at approximately 277 V while reference numeral  410  indicates the area that is at approximately 175 V. Moreover, reference numeral  412  indicates the area of the simulated Super Junction MOSFET device  200  that is at approximately 65 V while reference numeral  414  indicates the area that is at approximately 0.629 V. 
     It is pointed out that  FIG. 4  includes both an X-axis and Y-axis. Specifically, the X-axis of  FIG. 4  includes a micron (or micrometer) scale while the Y-axis also includes a micron (or micrometer) scale. 
       FIG. 5  illustrates an impact ionization distribution at the breakdown voltage of the simulated Super Junction MOSFET device  200  which includes an edge termination area in accordance with various embodiments of the invention. Note that within  FIG. 5 , as indicated by reference numeral  502 , the impact ionization occurs inside the bulk away from the surface as can be seen from the distribution of the impact ionization rate at the breakdown voltage. As such, this improves the ruggedness of the Super Junction MOSFET devices  100  and  200 . 
     More specifically within an embodiment, it is noted that reference numeral  502  indicates an area of the simulated Super Junction MOSFET device  200  that has an impact generation rate of approximately 20.7/cm 3 s while reference numeral  504  indicates an area having an impact generation rate of approximately 20.1/cm 3 s. In addition, reference numeral  506  indicates an area of the simulated Super Junction MOSFET device  200  having an impact generation rate of approximately 19.7/cm 3 s while reference numeral  508  indicates an area having an impact generation rate of approximately 19/cm 3 s. Additionally, reference numeral  510  indicates an area of the simulated Super Junction MOSFET device  200  that has an impact generation rate of approximately 18.7/cm 3 s while reference numeral  512  indicates an area having an impact generation rate of approximately 18/cm 3 s. 
     Note that  FIG. 5  includes both an X-axis and Y-axis. Specifically, the X-axis of  FIG. 5  includes a micron (or micrometer) scale while the Y-axis also includes a micron (or micrometer) scale. 
       FIGS. 6-8  illustrate a process for fabricating a junction termination extension (JTE)  800  within the edge termination area  108  of a Super Junction MOSFET device (e.g.,  100  or  200 ) in accordance with various embodiments of the invention. 
     Specifically,  FIG. 6  is a side sectional view of a mask  602  that has been implemented above or onto the edge termination area  108  of the Super Junction MOSFET device in accordance with various embodiments of the invention. The mask  602  can be implemented in a wide variety of ways. For example in an embodiment, the mask  602  can be implemented with a photoresist, but is not limited to such. It is pointed out that the mask  602  can include multiple holes or openings  604  that extend through the mask  602 . Note that within the present embodiment there are more holes  604  within the mask  602  towards its left end while there are less holes  604  within the mask  602  towards its right end. 
       FIG. 7  is a side sectional view of a P implant  702  directed towards the mask  602  and the edge termination area  108  of the Super Junction MOSFET device in accordance with various embodiments of the invention. It is noted that the P implant  702  can be implemented in a wide variety of ways. For example in one embodiment, the P implant  702  can be implemented as a boron implant, but is not limited to such. Note that some of the P implant  702  may pass through the holes  604  of the mask  602  while some of the P implant  702  may be blocked by the remaining portions of the mask  602 . As such, the P implant  702  that pass through the holes  604  create P doping  704  of the N− edge termination area  108 . In addition, given the spacing of the holes  604  within the mask  602  of the present embodiment, the P doping  704  results in a laterally varying doping within the edge termination area  108 . Specifically, there is a higher concentration of P doping  704  within the N− edge termination area  108  where there are more holes  604  within the mask  602  that allow the P implant  702  to pass through and a lower concentration of P doping  704  within the edge termination area  108  where there are less holes  604  within the mask  602 . 
       FIG. 8  is a side sectional view of a junction termination extension (JTE)  800  within the edge termination area  108  of the Super Junction MOSFET device in accordance with various embodiments of the invention. More specifically, after the completion of the P implant  702  shown within  FIG. 7 , the mask  602  can be removed from the upper surface of the edge termination area  108 . Note that the removal of the mask  602  can be performed in a wide variety of ways. For example in one embodiment, the mask  602  can be removed by an etching process, but is not limited to such. After the mask  602  has been removed, junction termination extension  800  remains within the edge termination area  108 . It is noted that the junction termination extension  800  can be referred to as an edge termination structure. Note that the junction termination extension  800  can be utilized or implemented in any manner similar to that described herein, but is not limited to such. 
       FIG. 9  is a side sectional view of a planar Junction Field Effect Transistor (JFET)  900  implemented as part of the termination area  108  of the Super Junction MOSFET device  100  in accordance with various embodiments of the invention. The JFET  900  can include, but is not limited to, a gate  902 , N+ dopant regions  904 , P dopant regions  906 , P+ dopant regions  908 , a contact  910 , an N dopant region  912 , and an N− dopant region of the termination area  108 . It is pointed out that the P+ dopant regions  908  of the JFET  900  are each in contact with a P region or column  106 . Note that the N dopant region  912  located between the P dopant regions  906  is the channel of the JFET  900 . When implemented in this manner, the resistance can be optimized of the JFET  900 . 
     It is pointed out that the JFET  900  may not include all of the elements illustrated by  FIG. 9 . In addition, the JFET  900  can be implemented to include one or more elements not illustrated by  FIG. 9 . Note that the JFET  900  can be utilized or implemented in any manner similar to that described herein, but is not limited to such. 
       FIG. 10  is a side sectional view of an edge termination area  108  of a trench Super Junction MOSFET device  1000  in accordance with various embodiments of the invention. The trench Super Junction MOSFET device  1000  can include, but is not limited to, a trench gate  1002 , N+ dopant regions  1006 , P dopant regions  1008 , an N dopant region  1010 , an N− dopant regions of the termination area  108 , and borophosphosilicate glass (BPSG)  1004 . Note that the P dopant regions  1008  contact a P region or column  106  while the N dopant regions  1010  are in contact with the N epitaxial region  104 . In addition, the trench Super Junction MOSFET device  1000  includes a source  1012  that can be implemented with a metal, but is not limited to such. 
     It is noted that the trench Super Junction MOSFET device  1000  may not include all of the elements illustrated by  FIG. 10 . Moreover, the trench Super Junction MOSFET device  1000  can be implemented to include one or more elements not illustrated by  FIG. 10 . It is pointed out that the trench Super Junction MOSFET device  1000  can be utilized or implemented in any manner similar to that described herein, but is not limited to such. 
       FIG. 11  is a flow diagram of a method  1100  in accordance with various embodiments of the invention. Although specific operations are disclosed in  FIG. 11 , such operations are examples. The method  1100  may not include all of the operations illustrated by  FIG. 11 . Also, method  1100  may include various other operations and/or variations of the operations shown. Likewise, the sequence of the operations of flow diagram  1100  can be modified. It is appreciated that not all of the operations in flow diagram  1100  may be performed. In various embodiments, one or more of the operations of method  1100  can be controlled or managed by software, by firmware, by hardware or by any combination thereof, but is not limited to such. Method  1100  can include processes of embodiments of the invention which can be controlled or managed by a processor(s) and electrical components under the control of computer or computing device readable and executable instructions (or code). The computer or computing device readable and executable instructions (or code) may reside, for example, in data storage features such as computer or computing device usable volatile memory, computer or computing device usable non-volatile memory, and/or computer or computing device usable mass data storage. However, the computer or computing device readable and executable instructions (or code) may reside in any type of computer or computing device readable medium or memory. 
       FIG. 11  is a flow diagram of a method  1100  in accordance with various embodiments of the invention for fabricating a Super Junction MOSFET. For example, method  1100  can include generating a charge compensation region of a Super Junction MOSFET device, wherein the charge compensation region is coupled to a substrate and includes a plurality of columns of a first type dopant within a second type dopant region. In addition, a termination region can be generated that is located above and coupled to the charge compensation region and that includes a lower concentration of the second type dopant than the second type dopant region. Furthermore, an edge termination structure can be generated such that the termination region includes at least a portion of the edge termination structure. Moreover, one or more field effect transistors can be generated such that the termination region includes at least a portion of each of the field effect transistors. In this manner, a Super Junction MOSFET can be fabricated in accordance with various embodiments of the invention. 
     At operation  1102  of  FIG. 11 , a charge compensation region (e.g.,  118 ) can be generated or created of a Super Junction MOSFET device (e.g.,  100  or  200 ), wherein the charge compensation region is located above a substrate (e.g.,  102 ) and includes a plurality of columns (e.g.,  106  or  106 ′) of a first type dopant within a second type dopant region (e.g.,  104 ). It is pointed out that operation  1102  can be implemented in a wide variety of ways. 
     For example in one embodiment, at operation  1102  the generating of the plurality of columns of the charge compensation region can include forming the second type dopant region above and coupled to the substrate. Subsequently, a deep trench etch process can be performed in order to create or generate multiple trenches within the second type dopant region. Afterward, the first type dopant material can be filled or formed within the multiple trenches of the second type dopant region thereby generating or creating the plurality of columns. 
     In an embodiment, at operation  1102  the generating of the plurality of columns of the charge compensation region can include forming multiple layers of second type dopant above the substrate and implanting within each layer multiple regions of first type dopant such that the resulting implanted first type dopant regions are vertically stacked. Accordingly, when the implanted first type dopant regions of the different second type dopant layers are subsequently defused (e.g., thermally diffused), the stacked implanted first type dopant regions vertically merge together in order to form multiple first type dopant regions or columns. Note that operation  1102  can be implemented in any manner similar to that described herein, but is not limited to such. 
     At operation  1104 , a termination region (e.g.,  108 ) can be generated that is located above and coupled to the charge compensation region and that includes a lower concentration of the second type dopant than the second type dopant region (e.g.,  104 ). It is noted that operation  1104  can be implemented in a wide variety of ways. For example, operation  1104  can be implemented in any manner similar to that described herein, but is not limited to such. 
     At operation  1106  of  FIG. 11 , one or more edge termination structures (e.g.,  110 ,  112  and/or  800 ) can be generated such that the termination region (e.g.,  108 ) includes at least a portion of each of the edge termination structures. Note that operation  1106  can be implemented in a wide variety of ways. For example, operation  1106  can be implemented in any manner similar to that described herein, but is not limited to such. 
     At operation  1108 , one or more field effect transistors (e.g.,  900 ) can be generated such that the termination region (e.g.,  108 ) includes at least a portion of each of the field effect transistors. It is noted that operation  1108  can be implemented in a wide variety of ways. For example, operation  1108  can be implemented in any manner similar to that described herein, but is not limited to such. In this manner, a Super Junction MOSFET can be fabricated in accordance with various embodiments of the invention. 
       FIGS. 12-24  illustrate a process for fabricating multiple P regions or columns (e.g.,  106 ) as part of a Super Junction MOSFET device (e.g.,  100 ) in accordance with various embodiments of the invention. For example, the process can begin in  FIG. 12  which is a side sectional view of a substrate  1202  that can be utilized to fabricate a Super Junction MOSFET device in accordance with various embodiments of the invention. It is pointed out that the substrate  1202  can be implemented in a wide variety of ways. For example in one embodiment, the substrate  1202  can be implemented as a silicon substrate, but is not limited to such. 
       FIG. 13  is a side sectional view of an N doped epitaxial layer  1304  that can be formed or grown above or on top of the substrate  1202  in accordance with various embodiments of the invention. 
       FIG. 14  is a side sectional view of a mask  1406  that has been implemented above or on top of the N doped epitaxial layer  1304  in accordance with various embodiments of the invention. The mask  1406  can be implemented in a wide variety of ways. For example in one embodiment, the mask  1406  can be implemented with a photoresist, but is not limited to such. It is noted that the mask  1406  can include multiple holes or openings  1408  that extend through the mask  1406 . Note that the holes  1408  within the mask  1406  are positioned in the desired location for fabricating the P regions or columns (e.g.,  106 ) within the Super Junction MOSFET device (e.g.,  100 ). 
       FIG. 15  is a side sectional view of a P implant  1508  directed towards the mask  1406  and the N doped epitaxial layer  1304  in accordance with various embodiments of the invention. Note that the P implant  1508  can be implemented in a wide variety of ways. For example in an embodiment, the P implant  1508  can be implemented as, but is not limited to, a boron implant. It is pointed out that some of the P implant  1508  may pass through the holes  1408  of the mask  1406  while some of the P implant  1508  may be blocked by the remaining portions of the mask  1406 . Accordingly, the P implant  1508  that pass through the holes  1408  create implanted P doping regions  1510  within the N doped epitaxial layer  1304 . 
     After the completion of the P implant  1508  shown within  FIG. 15 ,  FIG. 16  illustrates that the mask  1406  can be removed from the upper surface of the N doped epitaxial layer  1304  in accordance with various embodiments of the invention. Note that the removal of the mask  1406  can be performed in a wide variety of ways. For example, the mask  1406  can be removed by an etching process or Chemical Mechanical Polishing (CMP), but is not limited to such. 
       FIG. 17  is a side sectional view of a second N doped epitaxial layer  1304   a  that can be formed or grown above or on top of the N doped epitaxial layer  1304  implanted with the P doping regions  1510  in accordance with various embodiments of the invention. 
       FIG. 18  is a side sectional view of a mask  1406 ′ that has been implemented above or on top of the N epitaxial layer  1304   a  in accordance with various embodiments of the invention. The mask  1406 ′ can be implemented in a wide variety of ways. For example in an embodiment, the mask  1406 ′ can be implemented with, but is not limited to, a photoresist. It is pointed out that the mask  1406 ′ can include multiple holes or openings  1408 ′ that extend through the mask  1406 ′. Note that the holes  1408 ′ within the mask  1406 ′ are positioned above the implanted P doping regions  1510  located within the N epitaxial layer  1304 . 
       FIG. 19  is a side sectional view of a P implant  1508 ′ directed towards the mask  1406 ′ and the N epitaxial layer  1304   a  in accordance with various embodiments of the invention. It is pointed out that the P implant  1508 ′ can be implemented in a wide variety of ways. For example in one embodiment, the P implant  1508 ′ can be implemented as a boron implant, but is not limited to such. It is noted that some of the P implant  1508 ′ may pass through the holes  1408 ′ of the mask  1406 ′ while some of the P implant  1508 ′ may be blocked by the remaining portions of the mask  1406 ′. Therefore, the P implant  1508 ′ that pass through the holes  1408 ′ create implanted P doping regions  1510   a  within the N epitaxial layer  1304   a.    
     After the completion of the P implant  1508 ′ shown within  FIG. 19 ,  FIG. 20  illustrates that the mask  1406 ′ can be removed from the upper surface of the N epitaxial layer  1304   a  in accordance with various embodiments of the invention. It is pointed out that the removal of the mask  1406 ′ can be performed in a wide variety of ways. For example, the mask  1406 ′ can be removed from the upper surface of the N epitaxial layer  1304   a  by an etching process or CMP, but is not limited to such. 
     It is noted that after the completion of the removal of the mask  1406 ′ as shown within  FIG. 20 , the operations associated with  FIGS. 17-20  can be repeated one or more times in order to fabricate more stacked layers of N epitaxial layers implanted with P doping regions. For example,  FIG. 21  is a side sectional view of vertically stacked N epitaxial layers  1304 ,  1304   a ,  1304   b ,  1304   c ,  1304   d ,  1304   e ,  1304   f , and  1304   g  each implanted with P doping regions  1510 ,  1510   a ,  1510   b ,  1510   c ,  1510   d ,  1510   e ,  1510   f , and  1510   g , respectively, in accordance with various embodiments of the invention. In various embodiments, note that a greater or lesser number of vertically stacked N epitaxial layers implanted with P doping regions can be fabricated than are currently shown in the present embodiment of  FIG. 21 . Within the present embodiment, it is pointed out that the N epitaxial layer  1304   g  includes two dashed P doping regions  1510   g  which indicate that they may or may not be implanted within the N epitaxial layer  1304   g . For example in an embodiment, it may be desirable to implant less P doping regions within one or more of the N epitaxial layers (e.g.,  1304   g ) as implanted within the other N epitaxial layers (e.g.,  1304 - 1304   f ). 
     After the desired number of stacked N epitaxial layers implanted with P doping regions are fabricated above the substrate  1202  as shown in  FIG. 21 ,  FIG. 22  illustrates that an N− epitaxial layer  2204  can be formed above the multiple N epitaxial layers (e.g.,  1304 - 1304   g ) implanted with vertically stacked P regions (e.g.,  1510 - 1510   g ) in accordance with various embodiments of the invention. It is noted that the N− epitaxial layer  2204  can be formed in a wide variety of ways. For example in an embodiment, an N doped epitaxial layer can be formed or grown above or on top of the N doped epitaxial layer  1304   g . Next, an N− dopant can be implanted into that N doped epitaxial layer thereby creating the N− epitaxial layer  2204 , which can be referred to as a termination layer. It is pointed out that while the substrate  1202  and N epitaxial layers  1304 - 1304   c  are not shown within  FIG. 22 , they remain beneath the N epitaxial layers  1304   d  as shown within  FIG. 21 . 
     After the N− epitaxial layer  2204  is formed,  FIG. 23  illustrates the thermal diffusion of the implanted P doping regions  1510 - 1510   g  thereby causing them to vertically merge together to form multiple P regions or columns  2310  and  2310 ′ in accordance with various embodiments of the invention. Within the present embodiment of  FIG. 23 , it is noted that the dashed P doping regions  1510   g  were not implanted within the N epitaxial layer  1304   g  so that the P regions or columns  2310 ′ did not thermally diffuse into the N− epitaxial layer  2204 . However, during the thermal diffusion the implanted P doping regions  1510   g  diffused into the N− epitaxial layer  2204 . In addition, during the thermal diffusion the multiple N epitaxial layers  1304 - 1304   g  vertically merged together to form N epitaxial region  1304 ′. It is noted that while the substrate  1202  and N epitaxial layers  1304 - 1304   c  are not shown within  FIG. 23 , they remain beneath the N epitaxial layers  1304   d . Furthermore, the thermal diffusion can cause the vertically stacked P doping regions  1510 - 1510   c  to vertically merge together to form multiple P regions or columns  2310  in a manner similar to that shown within  FIG. 23 . Moreover, the thermal diffusion can cause the multiple N epitaxial layers  1304 - 1304   c  to vertically merge together to form N epitaxial region  1304 ′ in a manner similar to that shown within  FIG. 23 . 
       FIG. 24  illustrates additional area  2402  available for fabricating one or more semiconductor devices within the N− epitaxial layer or termination layer  2204  in accordance with various embodiments of the invention. It is pointed out that in one embodiment, the additional area  2402  was created by specifically not implanting the dashed P doping regions  1510   g  within the N epitaxial layer  1304   g  as shown in  FIGS. 21 and 22  so that the P regions or columns  2310 ′ did not thermally diffuse into the N− epitaxial layer  2204  as shown within  FIG. 24 . 
     The foregoing descriptions of various specific embodiments in accordance with the invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and many modifications and variations are possible in light of the above teaching. The invention is to be construed according to the Claims and their equivalents.