Patent Publication Number: US-10771023-B2

Title: Amplifier

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 107114470, filed on Apr. 27, 2018. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     BACKGROUND 
     Technical Field 
     The present disclosure relates to an amplifier, and particularly to an amplifier mainly used for wireless communication and designed with low-noise function. 
     Description of Related Art 
     An amplifier can be applied in various technical fields. In communication system, a receiver can amplify a signal received from antenna via an amplifier (e.g., low-noise amplifier (LNA)) so as for the signal to be processed by back-end stage electronic facility. Generally speaking, the signal from antenna is very weak, and thus the amplifier is disposed at a position close to the antenna to reduce the loss of signal while passing through a transmission line. Since the amplifier is disposed at the first stage of the overall receiver close to the antenna, the property of the amplifier (e.g., signal gain, noise processing, power consumption, etc.) directly affects the quality of the signal received by the overall receiver. In order to ensure the quality of the signal received by the antenna, a good amplifier should generate noise that is as low as possible while amplifying signal and reduce the signal from being distorted. 
     Conventional amplifier is realized as one or more differential amplifiers, and the differential amplifiers are used to improve signal gain of an output signal. However, such amplifier has larger power consumption. Additionally, since the transistors of the differential amplifiers are configured in pairs, and each of the transistors generates noise inherently, causing that the noises generated by each of the transistors in the amplifier are summed due to their opposite phases. In other words, the circuit structures of conventional amplifiers not only make it difficult for noises to be eliminated mutually, but also increases the interference of the output signal by the noises. Moreover, the signal gain in differential amplifiers is conventionally realized by the means of amplifying the gain of one of gate/source terminal in the transistors, which makes it difficult to obtain higher signal gain. 
     In view of the above, it is an objective for practitioners of the field to find out how to design a new amplifier with higher signal gain, more capable of processing noise while reduce signal from being distorted as much as possible. 
     SUMMARY 
     In the disclosure, an amplifier includes a first signal input terminal, at least one signal output terminal, a first cascode amplifier circuit, a second cascode amplifier circuit, a first capacitor and a loading circuit. The first signal input terminal receives a first input signal. The first cascode amplifier circuit includes a first input terminal, a second input terminal, a first output terminal and a second output terminal. The first input terminal is coupled to the first signal input terminal to receive the first input signal. The second cascode amplifier circuit includes a third input terminal, a fourth input terminal and a third output terminal. The third input terminal is coupled to the first output terminal, and the third output terminal is coupled to the second input terminal. Two terminals of the first capacitor are respectively coupled to the fourth input terminal and the first output terminal. The loading circuit includes a first terminal and a second terminal. The first terminal of the loading circuit is coupled to the third output terminal. The second terminal of the loading circuit is coupled to the second output terminal. At least one of the first terminal and the second terminal of the loading circuit is further coupled to at least one signal output terminal. 
     To make the foregoing features of the present disclosure clearer and more comprehensible, embodiments are described below in detail with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of an amplifier  100  according to a first embodiment of the disclosure. 
         FIG. 2  is a circuit diagram of an amplifier  200  according to a second embodiment of the disclosure. 
         FIG. 3  is a circuit diagram of an amplifier  300  according to a third embodiment of the disclosure. 
         FIGS. 4A, 4B, 4C, 4D, and 4E  are circuit structure diagrams of different types of loading circuits in different embodiments of the disclosure. 
         FIG. 5  is a circuit diagram of an amplifier  500  according to a fourth embodiment of the disclosure. 
         FIG. 6  is a circuit diagram of an amplifier  600  according to a fifth embodiment of the disclosure. 
         FIG. 7  is a circuit diagram of an amplifier  700  according to a sixth embodiment of the disclosure. 
         FIG. 8A  and  FIG. 8B  are schematic views of comparison between the amplifier  100  in  FIG. 1  and a conventional amplifier. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
       FIG. 1  is a circuit diagram of an amplifier  100  according to a first embodiment of the disclosure. The amplifier  100  may be a LNA used in a receiver for wireless communication. Those who adopt the present embodiment may apply the amplifier  100  to other electronic facilities or a signal amplifying facility of other technical fields, the disclosure provides no limitation to the application field of the amplifier  100 . The amplifier  100  in  FIG. 1  belongs to a single-ended input, double-ended output amplifier. The double-ended output amplifier in the embodiment may be referred to as a differential output amplifier. 
     The amplifier  100  includes a signal input terminal RF_In, at least one signal output terminal (e.g., signal output terminal RF_OUT, RF_OUT 180 ), a cascode amplifier circuit  110 , a cascode amplifier circuit  120 , a capacitor C 1  and a loading circuit  130 . The signal input terminal RF_In receives a first input signal (e.g., radio-frequency (RF) signal). The “cascode amplifier circuit” is an amplifier circuit structure that is formed by stacking two or more transistors, which makes it possible to obtain a better signal gain and improves frequency response. 
     The cascode amplifier circuit  110  includes an input terminal IN 1 , an input terminal IN 2 , an output terminal OUT 1  and an output terminal OUT 2 . The input terminal IN 1  is coupled to the signal input terminal RF_In to receive the first input signal. The cascode amplifier circuit  120  includes an input terminal IN 3 , an input terminal IN 4  and an output terminal OUT 3 . Additionally, the input terminal IN 1  may be further coupled to a bias terminal DC_bias 2  to supply a stable direct current (DC) bias voltage to the input terminal IN 1 . 
     The input terminal IN 3  is coupled to the output terminal OUT 1 . The output terminal OUT 3  is coupled to the input terminal IN 2 . Additionally, the input terminal IN 4  may be further coupled to a bias terminal DC_bias 1  to supply a stable DC bias voltage to the input terminal IN 4 . In the embodiment, the DC bias voltage on the bias terminal DC_bias 1  is greater than the DC bias voltage on the bias terminal DC_bias 2 . Those who adopt the present embodiment may adjust the DC bias voltage on the bias terminals DC_bias 1  and DC_bias 2  depending on the need, for example, by adjusting the DC bias voltage on the bias terminal DC_bias 1  to be less than or equal to the DC bias voltage on the bias terminal DC_bias 2 . 
     Two terminals of the capacitor C 1  are respectively coupled to the input terminal IN 4  and the output terminal OUT 1 . The capacitor C 1  is used for performing alternating current (AC) coupling effect. The capacitor C 1  of the embodiment, a capacitor C 21  and/or a capacitor C 22  in the following embodiment may include one of a junction capacitor, a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor and a transistor capacitor or a combination thereof. 
     The loading circuit  130  includes a first terminal E 1  and a second terminal E 2 . The first terminal E 1  is coupled to the output terminal OUT 3 . The second terminal E 2  is coupled to the output terminal OUT 2 . 
     One of the first terminal E 1  and the second terminal E 2  of the loading circuit  130  is further coupled to at least one signal output terminal. Specifically, the amplifier  100  of the embodiment is a double-ended output amplifier. Therefore, the first terminal E 1  is coupled to the signal output terminal RF_OUT 180  via the capacitor C 21 , the second terminal E 2  is coupled to the signal output terminal RF_OUT via the capacitor C 22 . In other words, the amplifier  100  further includes at least two capacitors C 21  and C 22 . Two terminals of the capacitor C 21  are respectively coupled to the first terminal E 1  and the signal output terminal RF_OUT 180 , and two terminals of the capacitor C 22  are respectively coupled to the second terminal E 2  and the signal output terminal RF_OUT. The capacitors C 21  and C 22  are mainly used for blocking the DC signal being output from the signal output terminals RF_OUT 180  and RF_OUT to a back-end electronic facility, that is, also referred to as DC blocking. The signal on the signal output terminal RF_OUT 180  and the signal on the signal output terminal RF_OUT are differential to each other. 
     The circuit structure of the cascode amplifier circuit  110  is described in details below. The cascode amplifier circuit  110  mainly includes a transistor T 1  and a transistor T 2 . Transistors T 1  and T 2  in  FIG. 1  as well as transistors T 3 -T 8  and TL 1 -TL 2  described below may include one of a bipolar junction transistor (BJT), a complementary metal-oxide-semiconductor (CMOS) transistor or a field-effect transistor (FET) or a combination thereof. The transistors T 1 -T 8  as well as transistors TL 1  and TL 2  in the embodiment and the following embodiments are realized as N-type transistor. Those who adopt the present embodiment may realize each of the transistors as P-type transistor. Additionally, the first terminal of the N-type transistor in the embodiment is a source terminal, the second terminal of the N-type transistor is a drain terminal, and the control terminal of the N-type transistor is a gate terminal; similar descriptions are omitted in the following embodiment. The control terminal of the transistor T 1  is coupled to the input terminal IN 1 . The first terminal of the transistor T 1  receives a reference voltage Vref 1 . The second terminal of the transistor T 1  is coupled to the output terminal OUT 1 . The control terminal of the transistor T 2  is coupled to the input terminal IN 2 . The first terminal of the transistor T 2  is coupled to the second terminal of the transistor T 1 . The second terminal of the transistor T 2  is coupled to the output terminal OUT 2 . 
     The circuit structure of the cascode amplifier circuit  120  is described in details below. The cascode amplifier circuit  120  includes a transistor T 3  and a transistor T 4 . The control terminal of the transistor T 3  is coupled to the input terminal IN 3 . The first terminal of the transistor T 3  receives the reference voltage Vref 1 . The control terminal of the transistor T 4  is coupled to the input terminal IN 4 , the first terminal of the transistor T 4  is coupled to the second terminal of the transistor T 3 , and the second terminal of the transistor T 4  is coupled to the output terminal OUT 3 . 
     The circuit structure of the loading circuit  130  is described below. The loading circuit  130  in the embodiment may mainly include loading elements  132  and  134 . The first terminal of the loading element  132  is coupled to the first terminal E 1  of the loading circuit  130 . The first terminal of the loading element  134  is coupled to the second terminal of the loading element  132 , the second terminal of the loading element  134  is coupled to the second terminal E 2  of the loading circuit  130 . The second terminal of the loading element  132  and the first terminal of the loading element  134  receive a reference voltage Vref 2 . It should be specifically indicated that, when the embodiment of the disclosure realizes each of the transistors as the N-type transistor, the reference voltage Vref 1  is exemplified as a ground voltage, and the reference voltage Vref 2  is exemplified as a power voltage. 
     The loading elements  132  and  134  in  FIG. 1  respectively include inductors L 1  and L 2 . In other embodiments, the loading element  132  and/or the loading element  134  may be realized as one of the inductor, resistor and transistor or a combination thereof, and examples are provided in the embodiments below as well as the drawings. 
     With the circuit structure shown in  FIG. 1 , it is possible that the noise on the two signal output terminals RF_OUT and RF_OUT 180  of the amplifier  100  generated by the noise with the transistors T 1 , T 2 , T 3  or T 4  has the same phase with the noise, such that the two noises are mutually eliminated and reduced because they have the same phase; in this manner, the signal on the signal output terminals RF_OUT and RF_OUT 180  are not easily affected by the noise generated by the transistor. 
     In the amplifier circuit structure realized through conventional means, the signal gain in the differential amplifier is realized by the means of amplifying the gain of one of gate/source terminal in the transistor. Relatively, the amplifier  100  in the embodiment amplifies the signal gain of the AC RF signal received by the signal input terminal RF_In mainly through the transistors T 1  and T 2  in the cascode amplifier circuit  110 , and inputs the signal related to the RF signal to the gate terminal of the transistors T 3  and T 4  in the cascode amplifier circuit  120 , such that the cascode amplifier circuit  120  feedbacks the signal to the input terminal IN 2  of the cascode amplifier circuit  110 . By using the circuit structure in the embodiment, the source terminal and the gate terminal of the transistor T 2  respectively receive the signal related to the RF signal, so as to increase the strength of signal gain of the amplifier  100  for the RF signal. In other words, the signal gain of the amplifier  100  in  FIG. 1  is greater than the signal gain of the amplifier structure realized as conventional differential amplifier. Additionally, the circuit structure that mainly consumes power in the amplifier  100  is the cascode amplifier circuit  110 . The cascode amplifier circuit  120  is mainly used to assist the cascode amplifier circuit  110  for consuming less power. Accordingly, the power consumed in the amplifier  100  is less than that consumed in the amplifier structure realized as conventional differential amplifier. 
     In  FIG. 1 , the signal gain Gain of the cascode amplifier circuit  110  in the amplifier  100  may be represented by the equation (1) below: 
     
       
         
           
             
               
                 
                   Gain 
                   = 
                   
                     
                       
                         - 
                         gm 
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                       × 
                       Zl 
                       × 
                       
                         ( 
                         
                           1 
                           + 
                           
                             gm 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                         ) 
                       
                     
                     
                       1 
                       - 
                       
                         gm 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                         × 
                         s 
                         × 
                         M 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         12 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     In equation (1), the symbol “gm1” refers to gain of transistor T 1 ; symbol “gm2” refers to gain of transistor T 2 ; symbol “Z1” refers to RLC resonant impedance of the signal output terminal in the amplifier  100 ; symbol “s” refers to complex frequency of Laplace transform; symbol “M12” refers to mutual inductance value between the inductors L 1  and L 2  in the loading circuit  130 . 
       FIG. 2  is a circuit diagram of an amplifier  200  according to a second embodiment of the disclosure. The difference between the amplifier  200  in  FIG. 2  and the amplifier  100  in  FIG. 1  is that the amplifier  200  in  FIG. 2  is a single-ended output amplifier. The amplifier  200  only has one signal output terminal RF_OUT 180 . The signal output terminal RF_OUT 180  is coupled to the first terminal E 1  of the loading circuit  130  via the capacitor C 21 . Those who adopt the present embodiment may change the amplifier circuit structure in the embodiment into a single-ended output amplifier by reference the example in  FIG. 2  according to their needs. 
       FIG. 3  is a circuit diagram of an amplifier  300  according to a third embodiment of the disclosure. The difference between the amplifier  300  in  FIG. 3  and the amplifier  100  in  FIG. 1  is that the amplifier  300  in  FIG. 3  is a single-ended output amplifier. The amplifier  300  only has one signal output terminal RF_OUT. The signal output terminal RF_OUT is coupled to the second terminal E 2  of the loading circuit  130  via the capacitor C 22 . Those who adopt the present embodiment may change the amplifier circuit structure in the embodiment into a single-ended output amplifier by reference the example in  FIG. 3  according to their needs. 
       FIG. 4A - FIG. 4E  are circuit structure diagrams of different types of loading circuits  430 A- 430 E in different embodiments of the disclosure. The main difference between loading circuits  430 A- 430 E in  FIG. 4A - FIG. 4E  and the loading circuit  130  in  FIG. 1  is that their circuit structures are different. Those who adopt the present embodiment may selectively apply the circuit structure of one of the loading circuits  130 ,  430 A- 430 E to the circuit structure of each of the amplifiers in the embodiment depending on the need. 
     The circuit structure of the loading circuits  430 A- 430 E are described below. In  FIG. 4A , loading elements  432 A and  434 A of the loading circuit  430 A respectively include a transistor TL 1  and a transistor TL 2 . The first terminal of the transistor TL 1  is coupled to the first terminal E 1  of the loading circuit  430 A, the second terminal of the transistor TL 1  is coupled to the second terminal of the transistor TL 2  and the reference voltage Vref 2 , and the first terminal of the transistor TL 2  is coupled to the second terminal E 2  of the loading circuit  430 A. 
     In  FIG. 4B , loading elements  432 B and  434 B of the loading circuit  430 B respectively include resistors RL 1  and RL 2 . The first terminal of the resistor RL 1  is coupled to the first terminal E 1  of the loading circuit  430 B. The second terminal of the resistor RL 1  is coupled to the reference voltage Vref 2 . The first terminal of the resistor RL 2  is coupled to the reference voltage Vref 2 , the second terminal of the resistor RL 2  is coupled to the second terminal E 2  of the loading circuit  430 B. 
     In  FIG. 4C , when loading elements  432 C and  434 C of the loading circuit  430 C are realized as the transistors TL 1  and TL 2 , the loading circuit  430 C may further include loading inductors LL 1  and LL 2 . The first terminal of the loading inductor LL 1  is coupled to the second terminal of the transistor TL 1 , and the second terminal of the loading inductor LL 1  is coupled to the reference voltage Vref 2 . The first terminal of the loading inductor LL 2  is coupled to the reference voltage Vref 2 , and the second terminal of the loading inductor LL 2  is coupled to the second terminal of the transistor TL 2 . The second terminal of the transistors TL 1  and TL 2  receive the reference voltage Vref 2  via the loading inductors LL 1  and LL 2  respectively. 
     In  FIG. 4D , when loading elements  432 D and  434 D of the loading circuit  430 D are realized as the transistors TL 1  and TL 2 , the loading circuit  430 D may further include loading resistors RL 3  and RL 4 . The first terminal of the loading resistor RL 3  is coupled to the second terminal of the transistor TL 1 , and the second terminal of the loading resistor RL 3  is coupled to the reference voltage Vref 2 . The first terminal of the loading resistor RL 4  is coupled to the reference voltage Vref 2 , and the second terminal of the loading resistor RL 4  is coupled to the second terminal of the transistor TL 2 . The second terminal of the transistors TL 1  and TL 2  receive the reference voltage Vref 2  via the loading resistors RL 3  and RL 4  respectively. 
     In  FIG. 4E , the loading circuit  430 E may further include two variable capacitors VCL 1  and VCL 2  other than two loading elements  432 E and  434 E. Specifically, the first terminal of the variable capacitor VCL 1  is coupled to the first terminal E 1  of the loading circuit  430 E. The first terminal of the variable capacitor VCL 2  is coupled to the second terminal of the variable capacitor VCL 1 , and the second terminal of the variable capacitor VCL 2  is coupled to the second terminal E 2  of the loading circuit  430 E. Those who adopt the present embodiment may apply the circuit structure of the loading elements  432 A- 432 B and  434 A- 434 B in  FIG. 4A - FIG. 4B  to the circuit structure of the loading elements  432 E and  434 E in the present embodiment. 
       FIG. 5  is a circuit diagram of an amplifier  500  according to a fourth embodiment of the disclosure. The difference between the amplifier  500  in  FIG. 5  and the amplifier  100  in  FIG. 1  is that the amplifier  500  in  FIG. 5  further includes a matching circuit  540 , and the two signal output terminals RF_OUT and RF_OUT 180  of the amplifier  500  may be connected to a double balanced mixer  550  outside the amplifier  500 . Specifically, the matching circuit  540  includes an inductor LC 1  and a capacitor CL 1 . One terminal of the inductor LC 1  is coupled to the signal input terminal RF_In, and the other terminal of the inductor LC 1  is coupled to one terminal of the capacitor CL 1 . The other terminal of the capacitor CL 1  is coupled to the input terminal IN 1  of the cascode amplifier circuit  110 . The function of the matching circuit  540  is to eliminate the DC bias voltage on the signal input terminal RF_In, and also serves to adjust the matching of input impedance. The matching circuit  540  may also be applied to all amplifier structures in the embodiment of the disclosure. 
     The amplifier  500  in  FIG. 5  is a double-ended output/differential output amplifier. Two terminals of the capacitor C 21  is coupled to the first terminal E 1  of the loading circuit  130  and one of the signal output terminals RF_OUT and RF_OUT 180  of the amplifier  500 . Two terminals of the capacitor C 22  is coupled to the second terminal E 2  of the loading circuit  130  and the other one of the signal output terminals RF_OUT and RF_OUT 180  of the amplifier  500 . In order to make the two signals on the signal output terminals RF_OUT and RF_OUT 180  to be mutually adjusted and achieve balance of output amplitude, the two signal output terminals RF_OUT and RF_OUT 180  of the amplifier  500  may be connected to the double balanced mixer  550  outside the amplifier  500 . The double balanced mixer  550  is capable of balancing the output amplitude of the two signals on the signal output terminals RF_OUT and RF_OUT 180 . Since the double balanced mixer  550  is not disposed within the amplifier  500  but outside the amplifier  500 , the double balanced mixer  550  is shown as a square frame illustrated in dashed line. 
       FIG. 6  is a circuit diagram of an amplifier  600  according to a fifth embodiment of the disclosure. The amplifier  600  is a double-ended input and double-ended output amplifier. Other than the original configuration (i.e., signal input terminal RF_In 1 , signal output terminal RF_OUT, RF_OUT 180 , cascode amplifier circuit  110 , cascode amplifier circuit  120 , capacitor C 1  and loading circuit  130 ) of the amplifier  100  shown in  FIG. 1 , the amplifier  600  further includes a signal input terminal RF_In 2 , a cascode amplifier circuit  610 , a cascode amplifier circuit  620  and a capacitor C 3 . The signal input terminal RF_In 2  receives a second input signal (e.g., RF signal). The first input signal received by the signal input terminal RF_In 1  and the second input signal received by the signal input terminal RF_In 2  are differential to each other. 
     The cascode amplifier circuit  610  includes an input terminal IN 5 , an input terminal IN 6 , an output terminal OUT 4  and an output terminal OUT 5 . The input terminal IN 5  is coupled to the signal input terminal RF_In 2  to receive the second input signal, and the output terminal OUT 5  is coupled to the first terminal E 1  of the loading circuit  130 . The input terminal IN 1  and the input terminal IN 5  may be further coupled to the bias terminal DC_bias 2  to supply stable DC bias voltage to the input terminals IN 1  and IN 5 . 
     Specifically, the cascode amplifier circuit  610  includes a transistor T 5  and a transistor T 6 . The control terminal of the transistor T 5  is coupled to the input terminal IN 5 . The first terminal of the transistor T 5  receives the reference voltage Vref 1 . The second terminal of the transistor T 5  is coupled to the output terminal OUT 4 . The control terminal of the transistor T 6  is coupled to the input terminal IN 6 . The first terminal of the transistor T 6  is coupled to the second terminal of the transistor T 5 . The second terminal of the transistor T 6  is coupled to the output terminal OUT 5 . 
     The cascode amplifier circuit  620  includes an input terminal IN 7 , an input terminal IN 8  and an output terminal OUT 6 . The input terminal IN 7  is coupled to the output terminal OUT 4 . The output terminal OUT 6  is coupled to the input terminal IN 6  and the second terminal E 2  of the loading circuit  130 . Specifically, the cascode amplifier circuit  620  includes a transistor T 7  and a transistor T 8 . The control terminal of the transistor T 7  is coupled to the input terminal IN 7 , and the first terminal of the transistor T 7  receives the reference voltage Vref 1 . The control terminal of the transistor T 8  is coupled to the input terminal IN 8 . The first terminal of the transistor T 8  is coupled to the second terminal of the transistor T 7 , and the second terminal of the transistor T 8  is coupled to the output terminal OUT 6 . Two terminals of the capacitor C 3  are respectively coupled to the input terminal IN 8  and the output terminal OUT 4 . 
     The amplifier  600  further includes a frequency band adjusting circuit  660 . The first terminal and the second terminal of the frequency band adjusting circuit  660  are respectively coupled to the first terminal E 1  and the second terminal E 2  of the loading circuit  130 . Specifically, the frequency band adjusting circuit  660  includes a capacitor C 4 , a switch SW 1  and a capacitor C 5 . The first terminal of the capacitor C 4  is coupled to the first terminal E 1  of the loading circuit  130 . The first terminal of the switch SW 1  is coupled to the second terminal of the capacitor C 4 . The first terminal of the capacitor C 5  is coupled to the second terminal of the switch SW 1 . The second terminal of the capacitor C 5  is coupled to the second terminal E 2  of the loading circuit  130 . In this manner, the central frequency of the amplifier  600  can be adjusted through the on/off state of the switch SW 1  in the frequency band adjusting circuit  660 . 
     In the embodiment, the amplifier  600  is a double-ended input, double-ended output amplifier, and may be adjusted as a double-ended input, single-ended output amplifier (e.g., when the amplifier only includes one of signal output terminal RF_OUT or RF_OUT 180 ) according to the need of those who adopt the present embodiment. When the amplifier  600  is a double-ended output amplifier, the signal output terminals RF_OUT and RF_OUT 180  may be coupled to the double-balanced mixer outside the amplifier  600  to balance the output amplitude of the two signals on the signal output terminals RF_OUT and RF_OUT 180 . 
     The transistors shown in  FIG. 1 - FIG. 6  are realized as a plurality of N-type transistors. In order to make the embodiment of the disclosure to be clearer, a P-type transistor is used herein to realize the amplifier that complies with the disclosure.  FIG. 7  is a circuit diagram of an amplifier  700  according to a sixth embodiment of the disclosure. The amplifier  700  belongs to a single-ended input, double-ended output amplifier. 
     The amplifier  700  includes a signal input terminal RF_In, at least one signal output terminal (e.g., signal output terminals RF_OUT, RF_OUT 180 ), a cascode amplifier circuit  710 , a cascode amplifier circuit  720 , a capacitor C 6  and a loading circuit  730 . The signal input terminal RF_In receives a first input signal. The cascode amplifier circuit  710  mainly includes transistors M 1  and M 2 . The cascode amplifier circuit  720  mainly includes transistors M 3  and M 4 . The transistors M 1 -M 4  of the embodiment are P-type transistors. Additionally, the first terminal of the P-type transistor in the embodiment is a source terminal, the second terminal of the P-type transistor is a drain terminal, and the control terminal of the P-type transistor is a gate terminal. The connection relationship of the transistors T 1 -T 4  of the amplifier  100  in  FIG. 1  is similar to the connection relationship of the transistors M 1 -M 4  of the amplifier  700  in  FIG. 7 ; the difference between the two is that the reference voltage Vref 1  coupled to the transistors M 1  and M 3  of the amplifier  700  in  FIG. 7  is exemplified as power voltage, and the reference voltage Vref 2  coupled to a loading circuit  730  of the amplifier  700  in  FIG. 7  is exemplified as ground voltage. 
     The cascode amplifier circuit  710  includes an input terminal IN 1 , an input terminal IN 2 , an output terminal OUT 1  and an output terminal OUT 2 . The input terminal IN 1  is coupled to the signal input terminal RF_In to receive the first input signal. The cascode amplifier circuit  720  includes an input terminal IN 3 , an input terminal IN 4  and an output terminal OUT 3 . Additionally, the input terminal IN 1  may be further be coupled to a bias terminal DC_bias 4  to supply stable DC bias voltage to the input terminal IN 1 . 
     The input terminal IN 3  is coupled to the output terminal OUT 1 . The output terminal OUT 3  is coupled to the input terminal IN 2 . Additionally, the input terminal IN 4  may be further coupled to a bias terminal DC_bias 3  to supply stable DC bias voltage to the input terminal IN 4 . In the embodiment, the DC bias voltage on the bias terminal DC_bias 4  is greater than the DC bias voltage on the bias terminal DC_bias 3 . Those who adopt the present embodiment may adjust the DC bias voltage on the bias terminals DC_bias 3  and DC_bias 4  depending on the need, for example, by adjusting the DC bias voltage on the bias terminal DC_bias 4  to be less than or equal to the DC bias voltage on the bias terminal DC_bias 3 . The loading circuit  730  includes loading elements  732  and  734 , and the loading circuit  730  may be realized similarly as various aspects of the loading circuits shown in  FIG. 1 - FIG. 4E . The circuit structure and the function of the amplifier  700  in  FIG. 7  are similar to the amplifier  100  in  FIG. 1 ; and thus related descriptions are omitted hereinafter. 
       FIG. 8A  and  FIG. 8B  are schematic views of comparison between the amplifier  100  in  FIG. 1  and the conventional amplifier.  FIG. 8A  shows comparisons between signal gains of the amplifier  100  in  FIG. 1  and conventional amplifier realized as differential amplifier. A curve  810  in  FIG. 8A  represents signal gain under the frequency of different input signals of the amplifier  100  in  FIG. 1 ; a curve  820  represents signal gain under the frequency of different input signals of a conventional amplifier.  FIG. 8A  shows that, under the frequency of each of the input signals, the amplifier  100  in  FIG. 1  achieves better signal gain as compared with conventional amplifier. 
       FIG. 8B  shows comparisons of noise figures (NF) between the amplifier  100  in  FIG. 1  and the conventional amplifier. Higher noise figure represents that the amplifier has more noise under the input signal of relative frequency (i.e., less capable of eliminating noise); lower noise figure represents that the amplifier has less noise under the input signal of relative frequency (i.e., more capable of eliminating noise). A curve  830  in  FIG. 8B  represents the noise figure under the frequency of different input signal of the amplifier  100  in  FIG. 1 . A curve  840  represents the noise figure under the frequency of different input signal of conventional amplifier.  FIG. 8B  shows that, under the frequency of each of the input signals, the amplifier  100  in  FIG. 1  has better noise processing capability than conventional amplifier, and improves noise eliminating effect. 
     In summary, the amplifier of the disclosure uses two sets of cascode amplifier circuits as a single-ended amplifier to increase signal gain, such that the amplifier has good noise processing capability and reduces the signal from being distorted, e.g., eliminating noise generated by transistor, using the structure of cascode amplifier to increase signal gain. Additionally, it is possible to combine two single-ended input amplifiers to form a differential input/double-ended input amplifier to broaden the application range of the amplifier of the disclosure. 
     Although the disclosure has been disclosed by the above embodiments, the embodiments are not intended to limit the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosure without departing from the scope or spirit of the disclosure. Therefore, the protecting range of the disclosure falls in the appended claims.