Patent Publication Number: US-9430984-B2

Title: Display panel driving circuit, driving method thereof, and display device

Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of display technology, and particularly relates to a display panel driving circuit, a driving method thereof, and a display device. 
     BACKGROUND OF THE INVENTION 
     A TFT-LCD (Thin Film Transistor Liquid Crystal Display) is a flat panel display device and has the characteristics of small size, low power consumption, no radiation, relatively low manufacturing cost and the like, so that it is increasingly applied in the field of high-performance display. 
     In the prior art, a structure of the TFT-LCD is generally as shown in  FIG. 1  and includes a display panel  10  and a driving unit comprising a timing controller (hereinafter referred to as “T/CON”)  100 , a gate driver  101  and a source driver  102 . Specifically, under the control of the timing controller  100 , the gate driver  101  controls signal outputs of gate lines (G 1  . . . Gn) to sequentially turn on the thin film transistors, which are connected to respective gate lines, line by line; and the source driver  102  controls signal outputs of data lines (S 1  . . . Sn) to display different pictures on the display panel  10 , the gate lines and the data lines are intersected with each other to define a plurality of pixel units arranged in a matrix form. 
     In this case, in the control time sequence outputted by the timing controller  100 , the turn-on and turn-off of gates of each row are controlled by a clock pulse vertical (hereinafter referred to as “CPV”). The specific control process is as follows: transmitting a start vertical (hereinafter referred to as “STV”) signal which is a high level signal indicating that gates may be turned on. Then when the CPV is at a rising edge, the gates of TFTs (Thin Film Transistor) of the first row are turned on, and a data signal, by the source driver  102 , is loaded to storage capacitors CS 1  at two terminals of the TFTs of the first row via the sources of the TFTs, and the TFTs of the first row start to charge; and when the next rising edge of the CPV arrives, the gates of TFTs of the first row are turned off, loading of the corresponding data signal is completed, charging of the TFTs of the first row is completed, meanwhile, the gates of the TFTs of the second row are turned on, a data signal is loaded to storage capacitors CS 2  at two terminals of the TFTs of the second row via the sources of the TFTs, and the TFTs of the following rows act as the same way. 
     With the development of display technology, a TFT-LCD display panel is required to have increasingly large screen size and increasingly high resolution and PPI (Pixels Per Inch). However, when the capability of driving a liquid crystal load is insufficient, pixel units cannot be charged within a short period of time, so that the LCD cannot meet the requirements of high resolution and high PPI, and thus the performance and quality of a product are decreased. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a display panel driving circuit, a driving method thereof and a display device, which can increase the charging voltage of pixel units, so that the charging time can be shortened and the capability of driving a display panel load can be enhanced. 
     To achieve the above-mentioned object, the embodiments of the present invention adopt technical solutions as below. 
     An aspect of the embodiments of the present invention provides a driving circuit for a display panel which comprises a plurality of pixel units defined by intersected gate lines and data lines and arranged in a matrix form. The driving circuit includes a pixel charging unit for combining voltages outputted from a clock pulse vertical terminal and a data voltage signal terminal to serve as a driving voltage for a data line. 
     Another aspect of the embodiments of the present invention provides a display device, including the above-mentioned display panel driving circuit. 
     Still another aspect of the embodiments of the present invention provides a driving method of a driving circuit for a display panel which comprises a plurality of pixel units defined by intersected gate lines and data lines and arranged in a matrix form, and the driving method includes steps of: 
     inputting voltage signals outputted from a clock pulse vertical terminal and a data voltage signal terminal to a pixel charging unit; and 
     combining, by the pixel charging unit, voltages outputted from the clock pulse vertical terminal and the data voltage signal terminal to serve as a driving voltage for a data line. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       To illustrate technical solutions in the embodiments of the present invention or in the prior art more clearly, a brief introduction on the accompanying drawings which are required in the description of the embodiments or the prior art is given below. Apparently, the accompanying drawings in the description below are merely some of the embodiments of the present invention, based on which other drawings may be obtained by the person skilled in the art without creative effort. 
         FIG. 1  is a schematic diagram of a structure of a display device according to the prior art; 
         FIG. 2  is a schematic diagram of a structure of a display panel driving circuit according to an embodiment of the present invention; 
         FIG. 3  is a schematic diagram of a structure of another display panel driving circuit according to an embodiment of the present invention; 
         FIG. 4  is a schematic diagram illustrating working principle of an adder according to an embodiment of the present invention; 
         FIG. 5  is a schematic diagram of a structure of a still another display panel driving circuit according to an embodiment of the present invention; 
         FIG. 6  is a schematic diagram of a structure of still another display panel driving circuit according to an embodiment of the present invention; 
         FIG. 7  is a schematic diagram illustrating working principle of an inverter according to an embodiment of the present invention; 
         FIG. 8  is a timing diagram of a display panel driving circuit according to an embodiment of the present invention; 
         FIG. 9  is a timing diagram of another display panel driving circuit according to an embodiment of the present invention; and 
         FIG. 10  is a flow chart of a driving method of a display panel driving circuit according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Technical solutions in the embodiments of the present invention will be clearly and completely described below, in combination with the accompanying drawings in the embodiments of the present invention. Apparently, the embodiments described are merely a part but not all of the embodiments of the present invention. All other embodiments which, based on the embodiments of the present invention, are obtained by the person skilled in the art without inventive efforts are within the protection scope of the present invention. 
       FIG. 2  is a schematic diagram of a driving circuit for a display panel which comprises gate lines  111  and data lines  110  according to an embodiment of the present invention. Here, the gate lines  111  and the data lines  110  are intersected with each other to define a plurality of pixel units  112  arranged in a matrix form. The display panel driving circuit may include pixel charging units  113 , each of which is used for combining a voltage outputted from a clock pulse vertical terminal (CPV) and a voltage outputted from a data voltage signal terminal (AVDDS) to serve as a driving voltage for a data line  110 . 
     It should be noted that, turning on the TFTs of each row requires a signal in which the turn-on time is long enough, and the signal is useless after the TFTs are turned on, and therefore, the signal outputted from the clock pulse vertical terminal may be preferably adopted. Other existing signals in the display panel driving circuit such as a gate driving circuit start vertical may also be used, but the STV signal needs to be lengthened, and the length of the CPV signal may maintain unchanged. In addition, the above-mentioned pixel charging unit  113  may be provided on the display panel  10  or on a D-IC (Driver-Integrated circuit) for driving the display panel to display. For example, the pixel charging unit  113  may be provided on the source driver  102  as shown in  FIG. 1 . The above description of the setting positions of the pixel charging unit  113  is merely given as an exemplarily example for illustrating, but the present invention is not limited thereto; the pixel charging unit  113  may also be provided at other positions, which should belong to the protection scope of the present invention. 
     Each of the pixel charging units  113  according to the embodiment of the present invention may combine a voltage outputted from the clock pulse vertical terminal and a voltage outputted from the data voltage signal terminal to serve as the driving voltage for a data line. Therefore, an auxiliary charging voltage outputted from the clock pulse vertical terminal may improve the charging voltage of pixel units, so that the charging time may be shortened, and the capability of driving a display panel load can be enhanced. 
     Optionally, each data line  110  is connected with one pixel charging unit  113 . That is, the pixel charging unit  113  may independently provide a driving voltage for each data line  110 , which facilitates independent driving control of each data line  110 . Thus, the pixel units defined by the data line of this column may be quickly charged under the action of the auxiliary charging voltage outputted from the clock pulse vertical terminal, so that the charging time of liquid crystal may be shortened. 
     Optionally, as shown in  FIG. 3 , the pixel charging unit  113  may include a pixel charging switch  200  and an adder  201 . 
     The first electrode of the pixel charging switch  200  is connected with a clock pulse vertical terminal; and the gate of the pixel charging switch  200  is connected with a data voltage signal terminal. 
     The input terminal of the adder  201  is connected with the data voltage signal terminal and the second electrode of the pixel charging switch  200 , respectively; and the output terminal of the adder  201  is connected with a data line  110 . 
     While a data voltage signal is outputted from the data voltage signal terminal to the adder  201 , the pixel charging switch  200  may be turned on, so that a clock pulse vertical outputted from the clock pulse vertical terminal may be inputted to the adder  201  as an auxiliary charging voltage. Under the action of the adder  201 , the voltage outputted from the clock pulse vertical terminal and the voltage outputted from the data voltage signal terminal are added to serve as a driving voltage for the data line  110 , so that the charging voltage of the pixel unit  112  is increased. 
     Optionally, the above-mentioned adder  201  includes a first resistor R 1 , a second resistor R 2 , a third resistor R 3  and a first operational amplifier  210 . 
     One terminal of the first resistor R 1  is connected with the second electrode of the pixel charging switch  200 , and the other terminal of the first resistor is connected with the inverting input terminal of the first operational amplifier  210 . 
     One terminal of the second resistor R 2  is connected with the data voltage signal terminal, and the other terminal of the second resistor is connected with the inverting input terminal of the first operational amplifier  210 . 
     One terminal of the third resistor R 3  is connected with the data voltage signal terminal, and the other terminal of the third resistor is connected with the output terminal of the first operational amplifier  210 . 
     The non-inverting input terminal of the first operational amplifier  210  is grounded. 
     Specifically, the working principle of the adder  201  may be as shown in  FIG. 4 , and it could be obtained that: 
     
       
         
           
             
               
                 
                   U 
                   
                     i 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
                 
                   R 
                   1 
                 
               
               + 
               
                 
                   U 
                   
                     i 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                 
                 
                   R 
                   2 
                 
               
             
             = 
             
               - 
               
                 
                   U 
                   0 
                 
                 
                   R 
                   3 
                 
               
             
           
         
       
     
     it could be further obtained that, 
     
       
         
           
             
               U 
               0 
             
             = 
             
               - 
               
                 
                   R 
                   3 
                 
                 ⁡ 
                 
                   ( 
                   
                     
                       
                         U 
                         
                           i 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                       
                         R 
                         1 
                       
                     
                     + 
                     
                       
                         U 
                         
                           i 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                       
                         R 
                         2 
                       
                     
                   
                   ) 
                 
               
             
           
         
       
     
     wherein U i1  may be the voltage outputted from the clock pulse vertical terminal, and U i2  may be the voltage outputted from the data voltage signal terminal. When R 3 =R 1 =R 2 , the voltage provided from the adder  201  to the data line  110  is U 0 =−(U i1 +U i2 ). It should be noted that, the above-mentioned adder is an inverting adder. 
     Optionally, when the adder  201  is an inverting adder, as shown in  FIG. 5 , the above-mentioned pixel charging unit  113  may further include an inverter  202 . 
     The inverter  202  is connected with the adder  201  and the data line  110 , respectively, and is configured to inverse the polarity of the voltage signal outputted by the adder  201 . 
     Optionally, as shown in  FIG. 6 , the above-mentioned inverter  202  includes a fourth resistor R 4 , a fifth resistor R 5  and a second operational amplifier  211 . 
     One terminal of the fourth resistor R 4  is connected with the output terminal of the first operational amplifier  210 , and the other terminal of the fourth resistor is connected with the inverting input terminal of the second operational amplifier  211 . 
     One terminal of the fifth resistor R 5  is connected with the inverting input terminal of the second operational amplifier  211 , and the other terminal of the fifth resistor is connected with the output terminal of the second operational amplifier  211 . 
     The non-inverting input terminal of the second operational amplifier  211  is grounded. 
     Specifically, the working principle of the inverter  202  may be as shown in  FIG. 7 , and it could be obtained that: 
     
       
         
           
             
               
                 U 
                 0 
               
               
                 R 
                 4 
               
             
             = 
             
               - 
               
                 U 
                 
                   R 
                   5 
                 
               
             
           
         
       
     
     when R 4 =R 5 , U=−U 0 ; 
     accordingly, U=−(−(U i1 +U i2 ))=U i1 +U i2 . 
     Therefore, when the polarity of a voltage signal output by the adder  201  is negative, the polarity of the voltage signal provided to the data line  110  may be changed to be positive by the inverter  202 . Thus, the polarity may be consistent with the conventional polarity of the voltage signal transmitted on the data line in the existing display control timing diagram, so as to facilitate drawing and analyzing the above-mentioned timing diagram by the person skilled in the art. Of course, when the polarity of a voltage signal outputted from the adder  201  is positive, the polarity of the voltage signal provided to the data line  110  may be changed to be negative by the inverter  202 . Thus, different requirements for the polarity of the voltage signals on the data lines may be met. 
     Optionally, the above-mentioned voltage outputted from the clock pulse vertical terminal (i.e., U i1 ) may be 3.3V. 
     It should be noted that, for each data line  110  on the display panel  10 , a gamma value needs to be adjusted at the initial stage of display, and a voltage of 3.3V (the above-mentioned voltage outputted from the clock pulse vertical terminal) may be additionally applied to the data line  110 , but the voltage is applied for a very short time, and therefore, the previous data only needs to be slightly adjusted when adjusting the gamma value. So the above-mentioned voltage of 3.3V outputted from the clock pulse vertical terminal may also be used for gamma adjustment. Of course, the above description only illustrates an example of the amplitude of the voltage outputted from the clock pulse vertical terminal, and voltages of other amplitudes are not listed one by one herein but should belong to the protection scope of the present invention. 
     Optionally, the above-mentioned voltage outputted from the data voltage signal terminal (i.e., U i2 ) is 6-10V. 
     Specifically, as shown in  FIG. 8 , when the voltage outputted from the clock pulse vertical terminal (i.e., U i1 ) is 3.3V and the voltage outputted from the data voltage signal terminal (i.e., U i2 ) is 10V, the two voltages are added by the adder  201 , so that the voltage (i.e., U 0 ) provided to the data line  110  is 3.3V+10V. 
     The working process of the pixel charging unit  200  will be described in detail below in combination with  FIGS. 6 and 9 . 
     At a T1 stage, a voltage of about 3.3V is outputted from the clock pulse vertical terminal before a voltage signal is outputted from the data voltage signal terminal. At this point, the pixel charging switch  200  is off since no signal is outputted from the data voltage signal terminal. Therefore, the pixel charging unit  113  cannot charge the display panel  10  at the T1 stage. 
     At a T2 stage, a voltage signal is outputted from the data voltage signal terminal under the control of the D-IC to charge the display panel  10 . At this point, the pixel charging switch  200  is turned on accordingly, and both the voltage (i.e., U i1 ) outputted from the clock pulse vertical terminal and the voltage (i.e., U i2 ) outputted from the data voltage signal terminal are inputted to the adder  201 . The voltage outputted from the adder  201  is U 0 =−(U i1 +U i2 ), and its polarity is negative. After the voltage U 0  is processed by the inverter  202 , the voltage on the data line  110  is U=U i1 +U i2 , and its polarity is positive. 
     At a T3 stage, clock pulse vertical terminal stops outputting the voltage signal, and then the auxiliary charging process for increasing the charging voltage is terminated. At this point, the voltage outputted from the adder  201  is the voltage outputted from the data voltage signal terminal, i.e., U 0 =−U i2 , and its polarity is negative. After the voltage U 0  is processed by the inverter  202 , the voltage on the data line  110  is U=U i2 , and its polarity is positive. 
     At a T4 stage, data voltage signal terminal stops outputting the voltage signal, and the charging process is terminated. 
     With the above steps, the voltage outputted from the clock pulse vertical terminal assists in charging the display panel  10 , so that the driving capacity of the D-IC is improved, and the charging time of each pixel unit is shortened. Thus, the display device may meet the requirements for high PPI and high resolution. 
     A display device according to an embodiment of the present invention includes the above-mentioned display panel driving circuit. The display device achieves the same beneficial effects as the display panel driving circuit according to the aforementioned embodiment of the present invention. Because the display panel driving circuit has been described in detail in the aforementioned embodiment, it will not be repeated herein. 
     It should be noted that, in the embodiment of the present invention, specifically, the display device may include a liquid crystal display device, for example, the display device may be any product or component with a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer or the like. 
     As shown in  FIG. 10 , a driving method of the display device driving circuit is provided, wherein the display device comprises a plurality of pixel units  200  defined by intersected gate lines  111  and data lines  110  and arranged in a matrix form, and the driving method comprises steps of: 
     S 101 , inputting voltage signals outputted from a clock pulse vertical terminal and a data voltage signal terminal to a pixel charging unit  113 ; and 
     S 102 , combining, by the pixel charging unit, voltages outputted from the clock pulse vertical terminal and the data voltage signal terminal to serve as a driving voltage for a data line  110 . 
     Optionally, the above-mentioned driving method of the display device driving circuit may further comprise a step of: 
     when a pixel charging switch  200  is turned on, combining, by an adder  201 , the voltages outputted from the clock pulse vertical terminal and the data voltage signal terminal to serve as the driving voltage for the data line  110 . 
     When a data voltage signal is outputted from the data voltage signal terminal to the adder  201 , the pixel charging switch  200  may be turned on, so that a clock pulse vertical signal outputted from the clock pulse vertical terminal is inputted to the adder  201  as an auxiliary charging voltage. Under the action of the adder  201 , the voltages outputted from the clock pulse vertical terminal and the data voltage signal terminal are added to serve as the driving voltage for the data line  110 , so that the charging voltage of the pixel unit  112  is increased. 
     Optionally, the above-mentioned driving method of the display device driving circuit may further include a step of: 
     inversing the polarity of the voltage signal output by the adder  201  by an inverter  202 . In this way, when the polarity of a voltage signal output by the adder  201  is negative, the polarity of the voltage signal provided to the data line  110  may be changed to be positive by the inverter  202 . Thus, the polarity may be consistent with the conventional polarity of the voltage signal transmitted on the data line in the existing display control timing diagram, thus facilitating drawing and analyzing above-mentioned timing diagram by the person skilled in the art. Of course, when the polarity of a voltage signal output by the adder  201  is positive, the polarity of the voltage signal provided to the data line  110  may be changed to be negative by the inverter  202 . Thus, different requirements for the polarity of the voltage signal on the data line can be met. 
     The foregoing descriptions are merely specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any skilled one familiar with this art of variations or substitutions that could readily conceived by the person skilled in the art within the disclosed technical scope of the present invention shall be covered by the protection scope of the present invention. Accordingly, the protection scope of the present invention should be subject to the protection scope of the claims.