Patent Publication Number: US-2012032941-A1

Title: Liquid crystal display device with low power consumption and method for driving the same

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to a liquid crystal display device and related driving method, and more particularly, to a liquid crystal display device with low power consumption by charge sharing and related driving method. 
     2. Description of the Prior Art 
     Liquid crystal display (LCD) devices, characterized in low radiation, thin appearance and low power consumption, have gradually replaced traditional cathode ray tube display (CRT) devices and are widely used in electronic products such as notebook computers, personal digital assistants (PDAs), flat-panel TVs, or mobile phones. In a traditional LCD device, images are displayed by scanning the pixels of the panel using external source drivers and gate drivers. However, gate driver-on-array (GOA) technique has been developed in order to reduce the number of devices and manufacturing costs by fabricating driving circuits directly on the substrate of the panel. 
       FIG. 1  is a diagram of a prior art LCD device  100  with GOA structure. The LCD device  100  includes a display panel  110 , a timing controller  120 , a source driver  130 , and a gate driver  140 . A plurality of data lines DL 1 -DL m , a plurality of gate lines GL 1 -GL n , and a pixel array are disposed on the display panel  110 . The pixel array includes a plurality of pixel units PX each having a thin film transistor switch TFT, a liquid crystal capacitor C LC  and a storage capacitor C ST  and coupled to a corresponding data line, a corresponding gate line, and a common voltage V COM . The timing controller  120  is configured to generate signals for operating the source driver  130  and the gate driver  140 , such as a start pulse signal VST and input clock signals CK 1  and CK 2 , etc. The source driver  130  is configured to generate data driving signals SD 1 -SD m , corresponding to display images, thereby charging corresponding pixel units PX. The gate driver  140  is a two-phase shift register which includes a plurality of shift register units SR 1 -SR n  coupled in series. The gate driver  140  is configured to sequentially output the gate driving signals SG 1 -SG n  to the corresponding gate lines GL 1 -GL n  according to the input clock signals CK 1 , CK 2  and the start pulse signal VST, thereby turning on the thin film transistors TFT in the corresponding pixel units PX. 
       FIG. 2  is a diagram illustrating a prior art driving method of the LCD device  100 . In  FIG. 2 , the waveforms of the input clock signals CK 1  and CK 2 , the start pulse signal VST, and the gate driving signals SG 1 -SG n  are depicted. In GOA structure, the input clock signals CK 1  and CK 2  with large voltage differential are directly applied to the glass substrate, and the parasitic capacitance of the panel is larger than that of a conventional driving chip. Therefore, although GOA technique may reduce manufacturing costs, it increases the overall power consumption of the LCD device  100 . Other devices on the control circuit board may be burned out more easily due to increased power consumption, resulting in a shortened life time of the product. 
     SUMMARY OF THE INVENTION 
     It is one of the objectives of the claimed invention to provide an LCD device with low power consumption and a related method to solve the abovementioned problems. 
     According to one embodiment, a method of driving an LCD device is provided. The method includes providing a first to an N th  input clock signals each having a duty cycle of 1/N, wherein N is an integer larger than 2; for a specific input clock signal among the first to the N th  input clock signals, allowing charge-sharing to occur between the specific input clock signal and two other input clock signals among the first to the N th  input clock signals during a signal rising period and a signal falling period of the specific input clock signal, respectively, thereby providing a first to an N th  output clock signals accordingly; and generating a plurality of gate driving signals according to the first to the N th  output clock signals. 
     According to one embodiment, an LCD device with low power consumption is provided. The LCD device includes a timing controller configured to provide a first to an N th  input clock signals each having a duty cycle of 1/N, wherein N is an integer larger than 2; a charge-sharing circuit configured to allow charge-sharing to occur between a specific input clock signal and two other input clock signals among the first to the N th  input clock signals during a signal rising period and a signal falling period of the specific input clock signal, respectively, thereby providing a first to an N th  output clock signals accordingly; and an N-phase shift register configured to generate a plurality of gate driving signals according to the corresponding first to the N th  output clock signals. 
     According to one embodiment, an LCD device with low power consumption is provided. The LCD device includes a timing controller configured to provide a first to a third input clock signals and a first to a fourth control signals, wherein a duty cycle of each input clock signal does not exceed ⅓; a shift register having a first to a third input ends; and a charge-sharing circuit. The charge-sharing circuit includes a first switch coupled between the first and second ends of the shift register and configured to selectively allow charge-sharing to occur between the first input clock signal and the second clock signal according to the first control signal; a second switch coupled between the second and third ends of the shift register and configured to selectively allow charge-sharing to occur between the second input clock signal and the third clock signal according to the second control signal; a first charge-sharing switch coupled between the timing controller and the shift register and configured to selectively transmit the first input clock signal from the timing controller to the first input end according to the fourth control signal; a second charge-sharing switch coupled between the timing controller and the shift register and configured to selectively transmit the second input clock signal from the timing controller to the second input end according to the fourth control signal; and a third charge-sharing switch coupled between the timing controller and the shift register and configured to selectively transmit the third input clock signal from the timing controller to the third input end according to the fourth control signal. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of a prior art LCD device with GOA structure. 
         FIG. 2  is a diagram illustrating a prior art driving method of the LCD device. 
         FIG. 3  and  FIG. 4  are diagrams of an LCD device with GOA structure according to embodiments of the present invention. 
         FIG. 5  is a diagram illustrating a charge-sharing circuit adopted prior to all control signals according to an embodiment of the present invention. 
         FIG. 6  and  FIG. 7  are diagrams illustrating a driving method of the LCD device according to embodiments of the present invention. 
         FIG. 8A  and  FIG. 8B  are diagrams illustrating a charge-sharing circuit according to embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 3  and  FIG. 4  are diagrams of an LCD device  300  and an LCD device  400  with GOA structure according to the present invention. The LCD devices  300  and  400  each include a display panel  310 , a timing controller  320 , a source driver  330 , and a gate driver  340 . The LCD device  300  includes a charge-sharing circuit  350  and the LCD device  400  includes a charge-sharing circuit  450 . A plurality of data lines DL 1 -DL m , a plurality of gate lines GL 1 -GL n , and a pixel array are disposed on the display panel  310 . The pixel array includes a plurality of pixel units PX each having a thin film transistor switch TFT, a liquid crystal capacitor C LC  and a storage capacitor C ST , and coupled to a corresponding data line, a corresponding gate line, and a common voltage V COM . The timing controller  320  is configured to generate signals required for operating the source driver  330 , the gate driver  340  and the charge-sharing circuit  350  or  450 , such as a start pulse signal VST, input clock signals CK 1 -CK 4 , and control signals S 0 -S 4 , etc. The source driver  330  is configured to generate data driving signals SD 1 -SD m  corresponding to display images, thereby charging the corresponding pixel units PX. The gate driver  340  is an n-phase shift register which includes a plurality of shift register units SR 1 -SR n  coupled in series. The gate driver  340  is configured to sequentially output the gate driving signals SG 1 -SG n  to the corresponding gate lines GL 1 -GL n  according to the input clock signals CK 1 -CKN and the start pulse signal VST, thereby turning on the thin film transistors TFT in the corresponding pixel units PX, wherein N and n are positive integers and 3≦N≦n). The charge-sharing circuit  350  or  450  is configured to allow charge-sharing to occur between each specific input clock signal and two other input clock signals among the input clock signals CK 1 -CKN respectively during the signal rising period and the signal falling period of each specific input clock signal, thereby providing corresponding output clock signals CK 1 ′-CKN′. 
       FIG. 3  illustrates an embodiment when N=3 (assuming n is a multiple of 3). In  FIG. 3 , the gate driver  340  is a tri-phase shift register capable of sequentially outputting the gate driving signals SG 1 -SG n  for turning on the thin film transistor switches TFTs according to the output clock signals CK 1 ′-CK 3 ′ and the start pulse signal VST. The charge-sharing circuit  350  includes input ends IN 1 -INn, output ends OUT 1 -OUTn (which may also represent the n input ends of the gate driver  340 ), a plurality of switches QP and QN 1 -QN 3 . Each of the switches QP is respectively coupled between one of the input ends IN 1 -INn and the corresponding one of the output ends OUT 1 -OUTn, and is configured to operate according to the control signal S 0  received from the timing controller  320 . The switches QN 1 -QN 3  are respectively coupled between two corresponding output ends among the output ends OUT 1 -OUTn, and are configured to operate according to the control signals S 1 -S 3  received from the timing controller  320 . In this embodiment, the switches QP and the switches QN 1 -QN 3  are implemented with different doping. For example, the switches QP may be P-type metal oxide semiconductor (PMOS) transistor switches, and the switches QN 1 -QN 3  may be N-type metal oxide semiconductor (NMOS) transistor switches. 
       FIG. 4  illustrates an embodiment when N=4 (assuming n is a multiple of 4). In  FIG. 4 , the gate driver  340  is a quad-phase shift register capable of sequentially outputting the gate driving signals SG 1 -SG n  for turning on the thin film transistor switches TFTs according to the output clock signals CK 1 ′-CK 4 ′ and the start pulse signal VST. The charge-sharing circuit  450  includes input ends IN 1 -INn, output ends OUT 1 -OUTn (which may also represent the n input ends of the gate driver  340 ), a plurality of switches QP and QN 1 -QN 4 . Each of the switches QP is respectively coupled between one of the input ends IN 1 -INn and the corresponding one of the output ends OUT 1 -OUTn, and is configured to operate according to the control signal S 0  received from the timing controller  320 . The switches QN 1 -QN 4  are respectively coupled between two corresponding output ends among the output ends OUT 1 -OUTn, and are configured to operate according to the control signals S 1 -S 4  received from the timing controller  320 . In this embodiment, the switches QP and the switches QN 1 -QN 4  are implemented with different doping. For example, the switches QP may be PMOS transistor switches, and the switches QN 1 -QN 4  maybe NMOS transistor switches. 
     Furthermore, in the embodiments illustrated in  FIG. 3  and  FIG. 4 , the charge-sharing circuits are disposed prior to the input of each shift register unit. However, it is not a limitation of the present invention. Please refer to  FIG. 5 .  FIG. 5  is a diagram illustrating the charge-sharing circuit which is disposed prior to all control signals according to another embodiment of the present invention. 
       FIG. 6  is a diagram illustrating a driving method of the LCD device  300  according to the present invention. In  FIG. 6 , the waveforms of the input clock signals CK 1 -CK 3 , the output clock signals CK 1 ′-CK 3 ′, the control signals S 0 -S 3 , the start pulse signal VST, and the gate driving signals SG 1 -SG n  are depicted. According to the driving method illustrated in  FIG. 6 , the duty cycle of the clock signals CK 1 -CK 3  is ⅓. When the control signals S 0 -S 3  are at low level, the switches QP are turned on and the switches QN 1 -QN 3  are turned off. The input clock signals CK 1 -CK 3  generated by the timing controller  320  may thus be supplied as the output clock signals CK 1 ′-CK 3 ′. When two specific control signals among the control signals S 0 -S 3  simultaneously switch to high level, charge-sharing may occur between two specific input clock signals among the input clock signals CK 1 -CK 3 . For instance, during the signal rising period of the input clock signal CK 2 , the control signals S 0  and S 1  simultaneously switch to high level. The switches QP are then turned off and the switch QN 1  is turned on, thereby allowing charge-sharing to occur between the input clock signal CK 2  and the input clock signal CK 1  through the conducting switch QN 1 . During the signal falling period of the input clock signal CK 2 , the control signals S 0  and S 2  simultaneously switch to high level. The switches QP are then turned off and the switch QN 2  is turned on, thereby allowing charge-sharing to occur between the input clock signal CK 2  and the input clock signal CK 3  through the conducting switch QN 2 . Similarly, during the signal rising period of the input clock signal CK 1  when the control signals S 0  and S 3  simultaneously switch to high level, charge-sharing may occur between the input clock CK 1  and the input clock signal CK 3 ; during the signal falling period of the input clock signal CK 1  when the control signals S 0  and S 1  simultaneously switch to high level, charge-sharing may occur between the input clock signal CK 1  and the input clock signal CK 2 . During the signal rising period of the input clock signal CK 3  when the control signals S 0  and S 2  simultaneously switch to high level, charge-sharing may occur between the input clock signal CK 3  and the input clock signal CK 2 ; during the signal falling period of the input clock signal CK 3  when the control signals S 0  and S 3  simultaneously switch to high level and may occur between the input clock signal CK 3  and the input clock signal CK 1 . 
       FIG. 7  is a diagram illustrating a driving method of the LCD device  400  according to the present invention. In  FIG. 7 , the waveforms of the input clock signals CK 1 -CK 4 , the output clock signals CK 1 ′-CK 4 ′, the control signals S 0 -S 4 , the start pulse signal VST, and the gate driving signals SG 1 -SG n  are depicted. According to the driving method illustrated in  FIG. 7 , the duty cycle of the clock signals CK 1 -CK 4  is ¼. When the control signals S 0 -S 4  are at low level, the switches QP are turned on and the switches QN 1 -QN 4  are turned off. The input clock signals CK 1 -CK 4  generated by the timing controller  320  may thus be supplied as the output clock signals CK 1 ′-CK 4 ′. When two specific control signals among the control signals S 0 -S 4  simultaneously switch to high level, charge-sharing may occur between two specific input clock signals among the input clock signals CK 1 -CK 4 . As mentioned before, during the signal rising period of the input clock signal CK 1  when the control signals S 0  and S 4  simultaneously switch to high level charge-sharing may occur between the input clock CK 1  and the input clock signal CK 4 ; during the signal falling period of the input clock signal CK 1  when the control signals S 0  and S 1  simultaneously switch to high level, charge-sharing may occur between the input clock signal CK 1  and the input clock signal CK 2 . During the signal rising period of the input clock signal CK 2  when the control signals S 0  and S 1  simultaneously switch to high level, charge-sharing may occur between the input clock signal CK 2  and the input clock signal CK 1 ; during the signal falling period of the input clock signal CK 2  when the control signals S 0  and S 2  simultaneously switch to high level, charge-sharing may occur between the input clock signal CK 2  and the input clock signal CK 3 . During the signal rising period of the input clock signal CK 3  when the control signals S 0  and S 2  simultaneously switch to high level, charge-sharing may occur between the input clock signal CK 3  and the input clock signal CK 2 ; during the signal falling period of the input clock signal CK 3  when the control signals S 0  and S 3  simultaneously switch to high level, charge-sharing may occur between the input clock signal CK 3  and the input clock signal CK 4 . During the signal rising period of the input clock signal CK 4  when the control signals S 0  and S 3  simultaneously switch to high level, charge-sharing may occur between the input clock signal CK 4  and the input clock signal CK 3 ; during the signal falling period of the input clock signal CK 4  when the control signals S 0  and S 4  simultaneously switch to high level, charge-sharing may occur between the input clock signal CK 4  and the input clock signal CK 1 . 
       FIG. 8A  and  FIG. 8B  are diagrams illustrating a charge-sharing circuit according to another embodiment of the present invention. In the embodiments illustrated  FIG. 8A  and  FIG. 8B , the charge-sharing circuit  350  further includes resistors R 1 -R 3 , and the charge-sharing circuit  450  further includes resistors R 1 -R 4 . Each of the resistors is coupled in series to a corresponding switch and configured to limit current during charge-sharing. 
     In the LCD devices according to the present invention, charge-sharing is performed between each specific input clock signal among the input clock signals and two other different input clock signals during its signal rising period and its signal falling period, respectively. Therefore, the present invention can reduce power consumption and provide a flexible driving method for operating multi-phase shift registers. 
     The abovementioned embodiments are presented merely for describing features of the present invention, and in no way should be considered to be limitations of the scope of the present invention. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.