Patent Publication Number: US-9406250-B2

Title: Display panel and method of detecting defects thereof

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a display panel and a method of detecting defects of a display panel. 
     2. Description of the Prior Art 
     Due to their slim shapes, low power dissipation and low radiation, liquid crystal displays (LCDs) are widely applied in mobile electronic devices such as notebooks, monitors, and PDAs (personal digital assistants). For reducing the manufacturing cost and improving yield rate of displays, the manufacturer would be likely to detect defects on the displays before shipping them, e.g. detect whether the displays have bright spots and dark spots. 
     However in the related art defect detecting method, if adjacent data lines electrically connected to the pixels are short circuited, damaged pixels electrically connected to the short circuited data lines may still emit light. Therefore, the related art method can not effectively detect all of the damaged pixels in the display, resulting in a reduced yield rate. 
     SUMMARY OF THE INVENTION 
     An embodiment of the present invention relates to a display panel. The display panel comprises a first substrate, a plurality of pixel units, a plurality of first signal lines, a first testing line and a second testing line. The first substrate has a display area and a peripheral area. The plurality of pixel units is arranged on the display area in an array. The plurality of first signal lines are disposed on the peripheral area and electrically connected to corresponding pixel units. The plurality of first signal lines comprise a plurality of first sets of sub-signal lines and a plurality of second sets of sub-signal lines alternatively arranged. Each first set of sub-signal lines have a first sub-signal line and a second sub-signal line. Each second set of sub-signal lines have a first sub-signal line and a second sub-signal line. The first sub-signal lines of the first sets of sub-signal lines and of the second sets of sub-signal lines and second sub-signal lines of the first sets of sub-signal lines and of the second sets of sub-signal lines are formed on different layers. The first testing line is electrically connected to the first and second sub-signal lines of the first sets of sub-signal lines. The second testing line is electrically connected to the first and second sub-signal lines of the second sets of sub-signal lines. 
     Another embodiment of the present invention relates to a method of detecting defects of a display panel. The display panel comprises a first substrate, a plurality of pixel units, a plurality of first signal lines, a first testing line and a second testing line. The first substrate has a display area and a peripheral area. The plurality of pixel units is arranged on the display area in an array. The plurality of first signal lines are disposed on the peripheral area and are electrically connected to corresponding pixel units. The plurality of first signal lines comprise a plurality of first sets of sub-signal lines and a plurality of second sets of sub-signal lines alternatively arranged. Each first set of sub-signal lines have a first sub-signal line and a second sub-signal line. Each second set of sub-signal lines have a first sub-signal line and a second sub-signal line. The first sub-signal lines of the first sets of sub-signal lines and of the second sets of sub-signal lines and second sub-signal lines of the first sets of sub-signal lines and of the second sets of sub-signal lines are formed on different layers. The first testing line is electrically connected to the first and second sub-signal lines of the first sets of sub-signal lines. The second testing line is electrically connected to the first and second sub-signal lines of the second sets of sub-signal lines. The method comprises lighting up pixel units electrically connected to the first sets of sub-signal lines to detect whether the pixel units electrically connected to the first sets of sub-signal lines have defects, and lighting up pixel units electrically connected to the second sets of sub-signal lines to detect whether the pixel units electrically connected to the second sets of sub-signal lines have defects. 
     Another embodiment of the present invention relates to a display panel. The display panel comprises a first substrate, a plurality of pixel units, a plurality of first signal lines, a driving element, a first testing line, a second testing line and a slit. The first substrate has a display area and a peripheral area. The plurality of pixel units is arranged on the display area in an array. The plurality of first signal lines are disposed on the peripheral area and are electrically connected to corresponding pixel units. The plurality of first signal lines comprise a plurality of first sets of sub-signal lines and a plurality of second sets of sub-signal lines alternatively arranged. Each first set of sub-signal lines have a first sub-signal line and a second sub-signal line, each second set of sub-signal lines have a first sub-signal line and a second sub-signal line. The first sub-signal lines of the first sets of sub-signal lines and of the second sets of sub-signal lines and second sub-signal lines of the first sets of sub-signal lines and of the second sets of sub-signal lines are formed on different layers. The driving element is disposed on the first signal lines and is electrically connected to the first signal lines. The first testing line is disposed corresponding to the first and second sub-signal lines of the first sets of sub-signal lines. The second testing line is disposed corresponding to the first and second sub-signal lines of the second sets of sub-signal lines. The slit is formed between the first testing line and the first sets of sub-signal lines, and between the second testing line and the second sets of sub-signal lines, for isolating the first testing line from the first sets of sub-signal lines, and isolating the second testing line from the second sets of sub-signal lines. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a display panel according to the first embodiment of the present invention. 
         FIG. 2  shows a cross sectional view of the display panel along the section line in  FIG. 1 . 
         FIG. 3  shows a structure of the display panel in  FIG. 1 . 
         FIG. 4  is a flowchart of detecting defects of the display panel in  FIG. 1 . 
         FIG. 5  shows configuring a cut trench in the display panel in  FIG. 1 . 
         FIG. 6  shows configuring a driving element in the display panel in  FIG. 1 . 
         FIG. 7  shows a display panel according to the second embodiment of the present invention. 
         FIG. 8  shows a display panel according to the third embodiment of the present invention. 
         FIG. 9  shows a display panel according to the fourth embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Some phrases are referred to specific elements in the present specification and claims, please notice that the manufacturer might use different terms to refer to the same elements. However, the definition between elements is based on their functions instead of their names. Further, in the present specification and claims, the term “comprising” is open type and should not be viewed as the term “consisted of.” Besides, the term “electrically couple” can be referred to either directly connecting or indirectly connecting between elements. 
     The embodiments and figures are provided as follows in order to illustrate the present invention in detail, but please notice that the claimed scope of the present invention is not limited by the provided embodiments and figures. 
     Please refer to  FIG. 1 , which shows a display panel  100  according to the first embodiment of the present invention. As shown in  FIG. 1 , the display panel comprises a first substrate  20 , a plurality of display units  90 , a plurality of first signal lines  40 , a plurality of pixel control lines CA and testing lines T 1  and T 2 . Each display unit  90  comprises a plurality of pixel units  30 . The first substrate  20  has a display area  110  and a peripheral area  120 . The peripheral device  120  surrounds the display area  110 . The display area  110  is a part of the display panel  100  for displaying images. The peripheral device  120  is the part of the display panel  100  other than the display area  110  and is the area inside the frame of the display panel  100  for disposing circuitries electrically connected to the plurality of pixel units  30 . The plurality of pixel units  30  are arranged on the first substrate  20  of the display area  110  in an array or a matrix structure. The pixel control lines CA comprise a plurality of data lines DA and a plurality of gate lines GA configured in the display area  110 . The pixel units  30  are electrically connected to the pixel control lines CA. Each pixel unit  30  can be a red, green or blue sub-pixel, but is not limit to these three primary colors. Each pixel unit  30  can also be a cyanine, yellow, magenta or white sub-pixel, for example. Besides, the sub-pixels in the same row or column can be sub-pixels of the same color, and are electrically connected to the same gate line or data line. The sub-pixels in the same row or column are electrically connected to the same sub-signal line. And three sub-pixels marked with R, G and B can form a display unit. 
     Please refer to both  FIGS. 1 and 2 .  FIG. 2  shows a cross sectional view of the display panel  100  along the section line  2 - 2 ′ in  FIG. 1 . The plurality of first signal lines  40  are disposed on the peripheral area  120  and electrically connected to corresponding pixel units  30 . The plurality of first signal lines  40  comprise a plurality of first sets of sub-signal lines S 1  and a plurality of second sets of sub-signal lines S 2  alternatively arranged. Each first set of sub-signal lines S 1  has a first sub-signal line S 11  and a second sub-signal line S 12 . Each second set of sub-signal lines S 2  has a first sub-signal line S 21  and a second sub-signal line S 22 . The first sub-signal lines S 11  and the second sub-signal lines S 12  are formed in the peripheral area  120  and on different layers. That is, the first sub-signal lines S 11  and the second sub-signal lines S 12  are disposed on different conducting layers, e.g. the first sub-signal lines S 11  are formed on the first conducting layer M 1 , and the second sub-signal lines S 12  are formed on the second conducting layer M 2 . Similarly, the first sub-signal lines S 21  and the second sub-signal lines S 22  are formed on different conducting layers. 
     The first dielectric layer L 1  is formed on the first substrate  20 , and formed between the first conducting layer M 1  and the second conducting layer M 2 . For example, the first dielectric layer L 1  overlays the first sub-signal lines S 11  and S 21  on the first conducting layer M 1 , and the second sub-signal lines S 21  and S 22  on the second conducting layer M 2  are formed on the first dielectric layer L 1 . The second dielectric layer L 2  overlays the second sub-signal lines S 21  and S 22  on the second conducting layer M 2 . The testing line T 1  is electrically connected to the first sub-signal lines S 11  and the second sub-signal lines S 12  of the first sets of sub-signal lines S 1 . The testing line T 2  is electrically connected to the first sub-signal lines S 21  and the second sub-signal lines S 22  of the second sets of sub-signal lines S 2 . The testing lines T 1  and T 2  are electrically connected to the testing pads D 1  and D 2  respectively, for providing the pixel units  30  with signals transmitted from the testing pads D 1  and D 2 . In the display panel  100 , the first sub-signal line S 11 , the second sub-signal line S 12 , the first sub-signal line S 21  and the second sub-signal line S 22  can be arranged in sequence. 
     Please refer to  FIG. 3 , which shows a structure of the display panel  100  in  FIG. 1 . The display panel  100  can be a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) display panel, a light emitting diode (LED) display panel, an electrophoresis display panel, an electro-wetting display panel or a field emitting display panel, and so on, but not limited thereto. In addition to the first substrate  20 , the display panel  100  can further comprises a second substrate  22  and a display medium  24 . Taking the LCD for example, the previously mentioned pixel units  30  and the first signal lines  40  can be disposed on the first substrate  20  of an LCD panel, to compose an active element matrix substrate. A color filter layer and a black matrix can be disposed on the inner surface of the second substrate  22  or the first substrate  20  to form a color filter substrate. The display medium  24  can be various types of liquid crystal layer so as to form a required LCD panel. Some detailed parts will not be further described because they can be equivalently modified by one skilled in the art. 
     Please refer to  FIG. 4 .  FIG. 4  is a flowchart of detecting defects of the display  100  in  FIG. 1 . The descriptions of  FIG. 4  are as follows: 
     Step  152 : light up pixel units  30  electrically connected to the first sets of sub-signal lines S 1  to detect whether the pixel units  30  electrically connected to the first sets of sub-signal lines S 1  have defects; and 
     Step  154 : light up pixel units  30  electrically connected to the second sets of sub-signal lines S 2  to detect whether the pixel units  30  electrically connected to the second sets of sub-signal lines S 2  have defects. 
     In Steps  152  and  154 , when lighting the pixel units  30  electrically connected to the first sets of sub-signal lines S 1 , the pixel units  30  electrically connected to the second sets of sub-signal lines S 2  are not lighted, or can be lighted with low grey levels, to utilize the grey level difference to detect whether the pixel units  30  electrically connected to the first sets of sub-signal lines S 1  have defects, e.g. bright spots or dark spots. For example, the test signal F 2  inputted to the test pad D 2  can be assigned to be no signal to make the pixel units  30  electrically connected to the second sets of sub-signal lines S 2  not lighted, or the test signals F 1 , F 2  inputted to the test pads D 1 , D 2  can be assigned to be different from each other to make the brightness of the pixel units  30  electrically connected to the first sets of sub-signal lines S 1  different from the brightness of those electrically connected to the second sets of sub-signal lines S 2 . 
     After performing the above testing procedures, only display panels passing the test can be configured with driving circuitries. Please refer to  FIGS. 5 and 6 .  FIG. 5  shows configuring a cut trench  350  in the display panel  100  in  FIG. 1 .  FIG. 6  shows configuring a driving element  300  in the display panel  100  in  FIG. 1 . As shown in  FIG. 5 , the cut trench  350  is disposed between the testing line T 1  and the first sets of sub-signal lines S 1  and between the testing line T 2  and the second sets of sub-signal lines S 2 , to isolate the testing line T 1  from the first sets of sub-signal lines S 1 , and to isolate the testing line T 2  from the second sets of sub-signal lines S 2 . The cut trench  350  can be formed with the laser cutting technology. It can be seen from  FIG. 5  that the first sets of sub-signal lines S 1  and the second sets of sub-signal lines S 2  are cut, and the cut positions are near the testing pads D 1  and D 2 . 
     Please refer to  FIG. 6 , after isolating the testing lines T 1  and T 2 , the driving element  300  is electrically connected to a plurality of first signal lines  40  for driving the pixel units  30 . The driving element  300  can be an integrated circuit chip  330  disposed on the first signal lines  40  and electrically connected to the first signal lines  40 . The driving element  300  can also be a chip on glass (COG), a chip on film (COF), a chip on board (COB), a tape automatic carrier bonding, a flexible printed circuit, and so on. Besides, as shown in  FIG. 5 , a plurality of connecting pads  320  can be configured on the first signal lines  40 , so that each first signal line  40  is formed with at least one connecting pad  320 . With the connecting pads  320 , the driving element  300  can be more easily configured on the first signal line  40 , strengthening the connection. 
     In the configuration of the first embodiment, two adjacent first sub-signal lines on the first conducting layer M 1 , such as S 11  and S 21 , might be short circuited due to developing defects or conductive particles. If the first sub-signal lines S 11 , S 21  are short circuited, when the testing signals F 1 , F 2  inputted to the testing lines T 1 , T 2  are different from one another, pixel units  30  coupled to the first sub-signal lines S 11 , S 21  will unexpectedly emit the same brightness of light due to short circuit effect. Thus, the approach can effectively identify the short circuit defects of the first sub-signal lines S 11  and S 21  on the same layer. Similarly, the above method can be applied to detect whether two adjacent second sub-signal lines S 12  and S 22  on the second conducting layer M 2  have defects. Compared with the present invention, the prior art display panel is configured to connect signal lines on the same conducting layers to the same testing line, thus the prior art is unable to detect short circuit defects of signal lines formed in the same layer. Besides, in the present embodiment, since the first sub-signal line S 11  and the second sub-signal line S 12  of the first set of sub-signal lines S 1  are disposed on different layers, the aforementioned short circuit effects of the first sub-signal line S 11  and the second sub-signal line S 12  can be greatly reduced. Similarly, the short circuit effect in the second set of sub-signal line S 2  can be greatly reduced as well. Therefore, with the first embodiment, even high resolution displays having high density signal lines can still be effectively detected, improving the yield rate and reducing the manufacturing cost. 
     Please refer to  FIG. 7 , which shows a display panel  600  according to the second embodiment of the present invention. The difference between the display panels  600  and  100  is that, in the display panel  600 , each first set of sub-signal lines S 1  further comprises a third sub-signal line S 13 , and each second set of sub-signal lines S 2  further comprises a third sub-signal line S 23 . The third sub-signal lines S 13  and S 23  can be formed on a third conducting layer. The first sub-signal line S 11 , the second sub-signal line S 12  and the third sub-signal line S 13  are formed on different layers in the peripheral area  120 . The first sub-signal line S 21 , the second sub-signal line S 22  and the third sub-signal line S 23  are also formed on different layers in the peripheral area  120 . 
     The first sub-signal line S 21 , second sub-signal line S 22  and third sub-signal line S 23  can be electrically connected to the pixel units  30  through data lines DA. According to another embodiment of the present invention, the data lines DA can be disposed on a layer different from the layers the first sub-signal line S 21 , second sub-signal line S 22  and third sub-signal line S 23  are disposed on. Besides, According to another embodiment of the present invention, all of the data lines DA can be disposed on the second conducting layer M 2 , and be electrically connected to first and third sub-signal lines  40  of different layers through the contact holes V 1  and V 2 . For example, the first sub-signal line S 21  is formed on the first conducting layer M 1 , the second sub-signal line S 22  is formed on the second conducting layer M 2 , and the third sub-signal line S 23  is formed on the third conducting layer M 3 . If the data lines DA are formed on the second conducting layer M 2 , the data lines DA can be electrically connected to the first sub-signal line S 21  through the contact hole V 1 , electrically connected to the second sub-signal line S 22  directly, and electrically connected to the third sub-signal line S 23  through the contact hole V 2 . 
     Through the second embodiment, the first sub-signal lines S 11 , S 21 , the second sub-signal lines S 12 , S 22  and the third sub-signal lines S 13 , S 23  in the peripheral area  120  are formed on different layers, thus the adjacent first sub-signal line S 11 , the second sub-signal line S 12  and the third sub-signal line S 13  will not be short circuited to one another, because they are electrically connected to different conducting layers. Further, even if defects exist in the same layer, the defects can still be easily detected because two adjacent pixels in the same row are electrically connected to different testing lines T 1  and T 2 , thus improving the yield rate of manufacturing the display panel  600 . 
     Please refer to  FIG. 8 .  FIG. 8  shows a display panel  700  according to the third embodiment of the present invention. The difference between the third and first embodiments is that, in the third embodiment, the sub-pixels are not limited to be arranged in the sequence of “ . . . , R, G, B, . . . ” but can be adjusted according to users&#39; needs. For example, the sub-pixels are arranged in the sequence of “ . . . , R, R, G, G, B, B . . . . ” Moreover, the direction of “ . . . , R, G, B, . . . ” or “ . . . , R, R, G, G, B, B . . . ” can be changed from vertical to horizontal, namely perpendicularly adjusting the arrangement. 
     Besides the testing pads D 1  and D 2 , the display panel  700  further comprises a plurality of second signal lines  50 , the testing lines T 4  and T 5 , and the testing pads D 4  and D 5 , to provide the pixel units  30  with the signals transmitted from testing pads D 4  and D 5 . Further, the second signal lines  50  of the display panel  700  comprise fourth sets of sub-signal lines S 4  and fifth sets of sub-signal lines S 5 . The fourth sets of sub-signal lines S 4  and the fifth sets of sub-signal lines S 5  are arranged alternatively. Each fourth set of sub-signal lines S 4  comprises a fourth sub-signal line S 41  and a fifth sub-signal line S 42 . Each fifth set of sub-signal lines S 5  comprises a fourth sub-signal line S 51  and a fifth sub-signal line S 52 . The fourth sub-signal lines S 41 , S 51  and the fifth sub-signal lines S 42 , S 52  are of different layers, but are all in the peripheral area  120 . The testing line T 4  is electrically connected to the fourth sub-signal lines S 41  and the fifth sub-signal lines S 42 . The testing line T 5  is electrically connected to the fourth sub-signal lines S 51  and the fifth sub-signal lines S 52 . Similar to the first sub-signal lines S 11  and the second sub-signal lines S 12 , the fourth sub-signal lines S 41  and the fifth sub-signal lines S 42  can be disposed on the first conducting layer M 1  and the second conducting layer M 2  respectively. The arrangement of the fourth sub-signal lines S 51  and the fifth sub-signal lines S 52  is similar to the arrangement of the fourth sub-signal lines S 41  and the fifth sub-signal lines S 42 . The method of detecting the row sub-pixels can be implemented in the similar manner as detecting the column sub-pixels by providing the testing signals F 1  and F 2 , and will not be further described. 
     Besides testing the column sub-pixels, the third embodiment further tests the row sub-pixels. Thus, in the third embodiment, the first sub-pixel lines S 11 , S 21  and the second sub-pixel lines S 12 , S 22  are disposed on different layers in the peripheral area  120 , making the adjacent first sub-pixel line S 11 , S 21  and the second sub-pixel line S 12 , S 22  unable to be short circuited to one another. Similarly, the fourth sub-pixel lines S 41 , S 51  and the fifth sub-pixel lines S 42 , S 52  are disposed on different layers in the peripheral area  120 , making the adjacent fourth sub-pixel line S 41 , S 51  and the fifth sub-pixel line S 42 , S 52  unable to be short circuited to one another. Moreover, if two adjacent sub-pixel lines in the same conducting layer are short circuited, the defects can be effectively detected for the adjacent sub-pixel lines are electrically connected to different testing lines. Thus, the yield rate of the display panel  700  can be improved. 
     Please refer to  FIG. 9 .  FIG. 9  shows a display panel  800  according to the fourth embodiment of the present invention. The difference between the fourth and third embodiments is that, in the fourth embodiment, each fourth set of sub-pixel lines S 4  further comprises a sixth sub-pixel line S 43 , and each fifth set of sub-pixel lines S 5  further comprises a sixth sub-pixel line S 53 . The fourth sub-pixel lines S 41 , S 51 , the fifth sub-pixel lines S 42 , S 52  and the sixth sub-pixel lines S 43 , S 53  are disposed in the peripheral area  120 . The fourth sub-pixel lines S 41 , S 51 , the fifth sub-pixel lines S 42 , S 52  and the sixth sub-pixel lines S 43  and S 53  are formed on different layers. The testing line T 4  is electrically connected to the fourth sub-pixel line S 41 , the fifth sub-pixel line S 42  and the sixth sub-pixel line S 43 . The testing line T 5  is electrically connected to the fourth sub-pixel line S 51 , the fifth sub-pixel line S 52  and the sixth sub-pixel line S 53 . 
     The sixth sub-pixel lines S 43 , S 53  can be disposed on a third conducting layer. Similar to that the first sub-pixel lines S 11 , S 21  and the second sub-pixel lines S 12 , S 22  are disposed on conducting layers M 1  and M 2  respectively, the fourth sub-pixel lines S 41 , S 51 , the fifth sub-pixel lines S 42 , S 52  and the sixth sub-pixel lines S 43 , S 53  can be disposed on three different conducting layers. Moreover, according to another embodiment of the present invention, the “R, G, B” arrangement of the sub-pixels can be changed from vertical to horizontal. In a modified embodiment of the present invention, the data lines DA and the gate lines GA can be exchanged according to design requirements. It is well known by a person skilled in the art and will not be described in detail herein. 
     In the fourth embodiment, the first sub-pixel lines S 11 , S 21  and the second sub-pixel lines S 12 , S 22  are disposed on different layers in the peripheral area  120 , making the adjacent first sub-pixel line S 11 , S 21  and the second sub-pixel line S 12 , S 22  unable to be short circuited to one another. Similarly, the fourth sub-pixel lines S 41 , S 51 , the fifth sub-pixel lines S 42 , S 52  and the sixth sub-pixel lines S 43 , S 53  are disposed on different layers in the peripheral area  120 , making the adjacent fourth sub-pixel line S 41 , S 51 , the fifth sub-pixel lines S 42 , S 52  and the sixth sub-pixel lines S 43 , S 53  unable to be short circuited to one another. Moreover, if two adjacent sub-pixel lines in the same conducting layer are short circuited, the defects can be effectively detected for the adjacent sub-pixel lines are electrically connected to different testing lines. Thus, the yield rate of the display panel  800  can be improved. 
     In view of above, with the configuration of the first signal lines  40  and the second signal lines  50 , the defects of display panels can be effectively detected to improve the yield rate of the display panels. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.