Patent Publication Number: US-7711881-B2

Title: Method for restoring system configuration information of a network attached storage

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention generally related to methods for restoring system configuration information of a network attached storage. 
   2. Description of Related Art 
   Most network attached storage (NAS) devices are embedded systems. NAS generally refers to a data storage element or device that is connected to a network allowing access to computers on the network, thus providing more storage space for users. 
   The NAS often resides in a machine that is expected to run continuously for years without errors. Therefore software for NAS is usually tested more thoroughly than general purpose operating systems or applications software. When systems errors or other critical errors occur in the NAS, system configuration information of the NAS may be destroyed or altered. The current method for restoring the NAS is to reload new system configuration information on a Flash ROM of the NAS. However, the current method for restoring the NAS has disadvantages, such as some data of the original system configuration information are lost because the new system configuration information is not the same as the original system configuration information. 
   What is needed is a method for restoring a network attached storage, which can restore system configuration information of the NAS. 
   SUMMARY OF THE INVENTION 
   One preferred embodiment provides a method for restoring a network attached storage. The network attached storage includes a general purpose input/output (GPIO) device, the GPIO device comprises a first pin, a power switch, a light emitting diode (LED) and a second pin connected in turn. The method includes the steps of: setting system configuration information of the network attached storage as a backup file; registering an interrupt handler; pressing down an input key connected to the power switch to turn off the power switch and generate an interrupt signal in the first pin; invoking the interrupt handler to process the interrupt signal and returning interrupt GPIO information; determining whether an operating system of the network attached storage receives the interrupt GPIO information from the interrupt handler; sending a periodical voltage to the second pin for blinking the LED if the operating system receives the interrupt GPIO information from the interrupt handler; invoking the backup file to restore the system configuration information of the network attached storage; and sending a high voltage command to the second pin for powering off the LED, which indicates that the system configuration information has been restored. 
   Other systems, methods, features, and advantages will be or become apparent to one skilled in the art upon examination of the following drawings and detailed description. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a network attached storage in accordance with one preferred embodiment; 
       FIG. 2  is a circuit diagram of part of a GPIO device in  FIG. 1 ; 
       FIG. 3  is a flowchart of a method for restoring system configuration information of a network attached storage in accordance with one preferred embodiment; 
       FIG. 4  is a flowchart of step S 12  in  FIG. 3 , namely initializing GPIO system setting; 
       FIG. 5  is a flowchart of processing an interrupt signal by the top half stack of an interrupt handler; and 
       FIG. 6  is a flowchart of processing an interrupt signal by the bottom half stack of the interrupt handler. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  is a block diagram of a network attached storage (NAS) in accordance with one preferred embodiment. The NAS typically includes a Flash-ROM  11 , a general purpose input/output (GPIO) device  12 , a central processing unit (CPU)  13 , a bus  15 , and an input key  16  connected to the GPIO device  12 . The Flash-ROM  11 , the GPIO device  12 , and the CPU  13  are connected to the bus  15 . An operating system and a backup file are stored in different partitions of the Flash-ROM  14 . 
     FIG. 2  is a circuit diagram of part of the GPIO device  12  in  FIG. 1 . The circuit diagram typically includes a power switch K 1 , a first resistance R 1 , a second resistance R 2 , a third resistance R 3 , a capacitance C 1 , a light emitting diode (LED) L 1 , a first pin P 1 , a second pin P 2 , and a node V 1  that is connected to 3.3 volts power supply. The first pin P 1 , the first resistance R 1 , the switch K 1  which is further connected with the input key  16 , the third resistance R 3 , the LED L 1 , and the second pin P 2  are connected in the order written. The anode of the LED L 1  is connected with the third resistance R 3 , and the cathode of the LED L 1  is connected with the second pin P 2 . The second resistance R 2  is connected parallel with the capacitance C 1 , one end of the parallel connection is connected to the end between the first pin P 1  and the first resistance R 1 , the other end of the parallel connection is connected to the ground. The anode of the capacitance C 1  is connected with the end between the first pin P 1  and the first resistance R 1 , and the cathode of the capacitance C 1  is connected to the ground. The node V 1  is connected between the switch K 1  and the third resistance R 3 . Once the input key  16  is pressed down, the switch K 1  is closed to complete the circuit therein, which generates a 3.3 volts high voltage in the first pin P 1 , thus, generating a hardware interrupt. Once a high voltage is sent to the second pin P 2 , the LED L 1  is powering off. Once a low voltage is sent to the second pin P 2 , the LED L 1  is luminescing. Once a periodical voltage is sent to the second pin P 2 , the LED L 1  is blinking. 
     FIG. 3  is a flowchart of a method for restoring system configuration information of a NAS in accordance with one preferred embodiment. The method of steps S 11 , S 12  and S 14  are performed on the kernel layer of the NAS. The method of steps S 15 , S 16 , S 17  and S 18  are performed on the application layer of the NAS. 
   In step S 11 , system configuration information of the NAS is set as a backup file in the Flash-ROM  14 . The system configuration information includes startup information, user information, and start services of restoring the NAS. 
   In step S 12 , GPIO system setting is initialized. The details of initializing GPIO system setting are described in  FIG. 4 . 
   In step S 13 , when the system configuration of the NAS is destroyed, the input key  16  is pressed down to turn off the power switch K 1  and generate a hardware interrupt and an interrupt signal. 
   In step S 14 , the interrupt handler is invoked to process the interrupt signal. The details of processing the interrupt signal by the interrupt handler are described in  FIG. 5  and  FIG. 6 . 
   In step S 15 , it is to determine whether the operating system receives interrupt GPIO information sent from the interrupt handler. 
   In step S 16 , if the operating system receives the interrupt GPIO information from the interrupt handler, a periodical voltage is sent to the second pin P 2  of the GPIO device  12  for blinking the LED, which indicates that the system configuration information is in a restoring state. 
   In step S 17 , the backup file is invoked to restore the system configuration information of the NAS. 
   In step S 18 , a high voltage is sent to the second pin P 2  for powering off the LED L 1 , which indicates that the system configuration information has been restored. 
   In the step S 15 , if the operating system hasn&#39;t received the interrupt GPIO information from the interrupt handler, repeat step S 15  to determining whether the operating system receives interrupt GPIO information sent from the interrupt handler. 
     FIG. 4  is a flowchart of step S 12  in  FIG. 3 , namely initializing GPIO system setting. Step S 12  in  FIG. 3  mainly includes the steps of: setting the first pin P 1  as an input port, and setting the second pin P 2  as an output port (Step S 121 ); registering an interrupt handler as to assign a corresponding interrupt number (Step S 122 ); setting the operating system to receive the interrupt signal (Step S 123 ). Generally, the GPIO device  12  has twenty-six input port pins, and each of the pins has a corresponding interrupt number between 32 and 64. The interrupt number assigned to the interrupt handler should be the same as the interrupt number of the first pin P 1  of the GPIO device  12 . The interrupt handler includes a top half stack which is executed by preempting tasks of the kernel of the operating system and masking other interrupts, and a bottom half stack which is executed when the operating system is idled. 
     FIG. 5  is a flowchart of processing the interrupt signal by the top half stack of an interrupt handler. 
   In step S 161 , the high voltage signal from the first pin P 1  is read, and the interrupt signal is received. 
   In step S 162 , it is to determine whether the interrupt signal is GPIO interrupt signal. If the interrupt number of the interrupt signal is between 32 and 64, the interrupt signal is GPIO interrupt signal; otherwise, if the interrupt number of the interrupt signal is not between 32 and 64, the interrupt signal is not GPIO interrupt signal. 
   In step S 163 , an interrupt symbol of the interrupt signal is configured with a global variable N if the interrupt signal is GPIO interrupt signal. The initial value of the global variable N is zero. 
   In step S 164 , the bottom half stack of the interrupt handler is dispatched to process the interrupt signal. 
   If the interrupt signal is GPIO interrupt signal in step S 162 , the procedure ends. 
     FIG. 6  is a flowchart of processing the interrupt signal by the bottom half stack of the interrupt handler. 
   In step S 165 , the interrupt symbol N is reset as zero. 
   In step S 166 , interrupt GPIO information is returned to the application layer of the NAS, and then the procedure returns to step S 15  to process the interrupt GPIO information. 
   It should be emphasized that the above-described embodiments of the preferred embodiments, particularly, any “preferred” embodiments, are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the invention. Many variations and modifications may be made to the above-described preferred embodiment(s) without departing substantially from the spirit and principles of the invention. All such modifications and variations are intended to be included herein within the scope of this disclosure and the above-described preferred embodiment(s) and protected by the following claims.