Patent Publication Number: US-2006002162-A1

Title: Single inductor capacitor charger

Description:
FIELD OF THE INVENTION  
      The present invention is related generally to a capacitor charger and more particularly to a single inductor capacitor charger.  
     BACKGROUND OF THE INVENTION  
      As shown in  FIG. 1 , a typical capacitor charger  10  comprises a transformer  12  having a primary winding L 1  and a secondary winding L 2  with a turn ratio of N1:N therebetween to transform a primary current I 1  to a secondary current I 2 . The primary winding L 1  is connected between an input voltage Vin and a transistor  14  switched by a signal Vs, and the secondary winding L 2  is connected between an output capacitor Co and ground GND.  FIG. 2  shows a structure of the transformer  12 , which comprises a ferrite core  122  with the primary and secondary windings L 1  and L 2  wound thereon for mutually magnetic coupling between the primary and secondary windings L 1  and L 2 . Referring to  FIGS. 1 and 2 , when the transistor  14  turns on, the primary current I 1  flowing through the primary winding L 1  produces magnetic lines of force  124 , and energy is stored in the ferrite core  122  of the transformer  12 . When the transistor  14  turns off, the stored energy is released to produce the secondary current I 2  flowing through the secondary winding L 2  and a boost diode D 1  to charge the output capacitor Co to produce an output voltage Vout.  
      Since two windings L 1  and L 2  are used in the transformer  12 , the capacitor charger  10  has a large volume, and there is always a parasitic capacitor Cs present between the primary and secondary windings L 1  and L 2 , as shown in  FIG. 1 . When the transistor  14  is switched, the induced voltage V D  on the secondary winding L 2  changes violently, and the voltage and current of the parasitic capacitor Cs change accordingly, thereby inducing impact to the operation of the capacitor charger  10  to reduce its charging efficiency and performance.  
      Therefore, it is desired a capacitor charger having reduced parasitic capacitive effect and volume.  
     SUMMARY OF THE INVENTION  
      One object of the present invention is to provide a novel capacitor charger.  
      Another object of the present invention is to provide a capacitor charger having less parasitic capacitive effect.  
      Still another object of the present invention is to provide a small size capacitor charger.  
      Yet another object of the present invention is to provide a capacitor charger having faster charging speed.  
      Still yet another object of the present invention is to provide a low cost capacitor charger.  
      A capacitor charger according to the present invention comprises a single inductor tapped to separate the inductor to two segments arranged such that the first segment is connected between an input voltage and the taper and the second segment is connected between the taper and an output capacitor, and a switch connected between the taper and ground to be switched to produce a current to charge the output capacitor to produce an output voltage. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
      These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:  
       FIG. 1  shows a circuit diagram of a conventional capacitor charger;  
       FIG. 2  shows a structure of the transformer in  FIG. 1 ;  
       FIG. 3  shows a circuit diagram of a first embodiment according to the present invention;  
       FIG. 4  shows a structure of the inductor in  FIG. 3 ;  
       FIG. 5  shows waveforms of various signals in the conventional capacitor charger of  FIG. 1 ;  
       FIG. 6  shows waveforms of various signals in the capacitor charger of the present invention shown in  FIG. 3 ;  
       FIG. 7  shows a circuit diagram of a second embodiment according to the present invention;  
       FIG. 8  shows a circuit diagram of a third embodiment according to the present invention;  
       FIG. 9  shows a circuit diagram of a fourth embodiment according to the present invention;  
       FIG. 10  shows a circuit diagram of a fifth embodiment according to the present invention; and  
       FIG. 11  shows a circuit diagram of a sixth embodiment according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
       FIG. 3  shows a first embodiment according to the present invention. In a capacitor charger  20 , an inductor L is connected between an input voltage Vin and a boost diode D 2 . The inductor L has N turns winding, and a taper  26  is drawn from the inductor L to separate the inductor L to two segments  22  and  24 . The segment  22  has N1 turns winding, and therefore the other segment  24  has the turns of 
   N 2 =N−N 1.  [EQ-1] 
 A transistor  28  is connected between the taper  26  and ground GND to serve as a switch controlled by a signal Vs.  FIG. 4  shows a structure of the inductor L in  FIG. 3 , which has a ferrite core  29  with N turns winding wound thereon. Referring to  FIGS. 3 and 4 , when the transistor  28  turns on, a current I 1  is produced to flow through the segment  22  of the inductor L and transistor  28  to ground GND, thereby producing magnetic lines of force  222  to store energy to the ferrite core  29  of the inductor L. When the transistor  28  turns off, the stored energy is released to produce a voltage V D  on the segment  24  and a current I 2  to charge the output capacitor Co to produce an output voltage Vout. 
 
      For comparison, the waveforms of various signals in the conventional capacitor charger  10  of  FIG. 1  and in the capacitor charger  20  of  FIG. 3  according to the present invention are shown in  FIGS. 5 and 6 , respectively. In  FIG. 5 , for the conventional capacitor charger  10 , waveform  30  represents the signal Vs, waveform  32  represents the primary current I 1 , waveform  34  represents the voltage drop V ds1  across the transistor  14 , waveform  36  represents the secondary current I 2 , and waveform  38  represents the voltage V D  on the winding L 2 . In  FIG. 6 , for the capacitor charger  20  of the present invention, waveform  40  represents the signal Vs, waveform  42  represents the current I 1  flowing through the segment  22  of the inductor L, waveform  44  represents the voltage drop V ds2  across the transistor  28 , waveform  46  represents the current I 2  to charge the output capacitor Co, and waveform  30  represents the voltage V D  on the segment  24 . It is assumed that the capacitor chargers  10  and  20  use the same property and type of ferrite cores and windings for the transformer  12  and inductor L to produce the same output voltage Vout from the same input voltage Vin. Referring to  FIGS. 1, 3 ,  5  and  6 , the transistors  14  and  28  have the same on-time Ton, and therefore the currents I 1  of the chargers  10  and  20  have the same maximum value. In other words, the ferrite cores  122  and  29  will store the same magnetic energy, resulting in the currents I 2  of the chargers  10  and  20  to have the maximum value 
 
 X 1 =X 2 =X,   [EQ-2]
 
 where X1 is the maximum value of the current I 2  in the charger  10 , and X2 is the maximum value of the current I 2  in the charger  20 . 
 
      It is known to those skilled ones in the art that the charger  10  has the charging time, i.e., the off-time of the transistor  14 , of  
               Toff1   =         N   2     ×   Vin         N1   2     ×   Vout         ,           [     EQ   ⁢     -     ⁢   3     ]             
 
 and the charger  20  has the charging time, i.e., the off-time of the transistor  28 , of  
             Toff2   =           N   2     ×   Vin         N1   2     ×     (     Vout   -   Vin     )         .             [     EQ   ⁢     -     ⁢   4     ]             
 
 By comparing the equations EQ-3 and EQ-4, it is shown that the charging time Toff2 of the charger  20  is larger than the charging time Toff1 of the charger  10 . Namely, the charger  10  will have more switching times for the transistor  14  than that for the transistor  28  of the charger  20 . Therefore, the charger  20  of the present invention has reduced switching loss and improved efficiency. 
 
      Moreover, the charger  10  has the average charging current  
               Iavg1   =         X1   ×     Toff1   2         Ton   +   Toff1       =       X1   ×   Toff1       2   ⁢     (     Ton   +   Toff1     )             ,           [     EQ   ⁢     -     ⁢   5     ]             
 
 while the charger  20  has the average charging current  
             Iavg2   =         X2   ×     Toff2   2         Ton   +   Toff2       =         X2   ×   Toff2       2   ⁢     (     Ton   +   Toff2     )         .               [     EQ   ⁢     -     ⁢   6     ]             
 
 From the equations EQ-2, EQ-3, and EQ-5, it is obtained  
               Iavg1   =         X   ×         N   2     ×   Vin         N1   2     ×   Vout           2   ⁢     (     Ton   +         N   2     ×   Vin         N1   2     ×   Vout         )         =       X   ×     N   2     ×   Vin       2   ⁢     (       Ton   ×     N1   2     ×   Vout     +       N   2     ×   Vin       )             ,           [     EQ   ⁢     -     ⁢   7     ]             
 
 and from the equations EQ- 2 , EQ- 4 , and EQ- 6 , it is obtained  
             Iavg2   =         X   ×         N   2     ×   Vin         N1   2     ×     (     Vout   -   Vin     )             2   ⁢     (     Ton   +         N   2     ×   Vin         N1   2     ×     (     Vout   -   Vin     )           )         =         X   ×     N   2     ×   Vin       2   ⁡     [       Ton   ×     N1   2     ×     (     Vout   -   Vin     )       +       N   2     ×   Vin       ]         .               [     EQ   ⁢     -     ⁢   8     ]             
 
 The equations EQ-7 and EQ-8 show that 
 
Iavg2&gt;Iavg1. [EQ-9]
 
 Therefore, the charger  20  of the present invention has faster charging speed than the conventional charger  10 . 
 
      On the other hand, when the transistors  14  and  28  turn off, the transistor  14  of the conventional charger  10  will withstand the voltage drop  
                 V   ds1     =         N1   ×   Vout     +     N   ×   Vin       N       ,           [     EQ   ⁢     -     ⁢   10     ]             
 
 and the transistor  28  of the charger  20  according to the present invention will withstand the voltage drop  
                 V   ds2     =         N1   ×   Vout     +     N2   ×   Vin       N       ,           [     EQ   ⁢     -     ⁢   11     ]             
 
 which shows that V ds2  is smaller than V ds1 . Therefore, the voltage required for the transistor  28  of the charger  20  in the present invention to be capable of withstanding is smaller, and the cost of the transistor  28  is less. When the transistors  14  and  28  turn on, the boost diode D 1  of the conventional charger  10  has the voltage drop  
               V1   =     Vout   +       N   N1     ⁢   Vin         ,           [     EQ   ⁢     -     ⁢   12     ]             
 
 and the boost diode D 2  of the charger  20  according to the present invention has the voltage drop  
               V2   =     Vout   +       N2   N1     ⁢   Vin         ,           [     EQ   ⁢     -     ⁢   13     ]             
 
 which shows that V 2  is smaller than V 1 . Therefore, the voltage required for the boost diode D 2  of the charger  20  in the present invention to be capable of withstanding is smaller, and the cost of the boost diode D 2  is less. From  FIGS. 1 and 3 , it is also shown that the inductor L of the charger  20  is less N1 turns than that of the conventional charger  10 , and therefore the charger  20  will have a smaller volume. Even a parasitic capacitor Cs is present between the segments  22  and  24  of the inductor L in the charger  20 , the capacitive effect induced therefrom is reduced, since the segments  22  and  24  are connected to each other and will have zero voltage drop therebetween. 
 
       FIG. 7  shows a second embodiment according to the present invention. This capacitor charger  50  has a basic scheme the same as that of the capacitor charger  20  shown in  FIG. 3 , but is introduced additionally with means for the control of the output voltage Vout, in which two resistors R 1  and R 2  are connected between the output voltage Vout and ground GND to serve as a sensor to produce a sense signal VFB by dividing the output voltage Vout, as in the following relationship  
             Vout   =     VFB   ×         R1   +   R2     R2     .               [     EQ   ⁢     -     ⁢   14     ]               
 Since the sense signal VFB is proportional to the output voltage Vout, it could easily monitor the output voltage Vout from the sense signal VFB. Once the output voltage Vout is sensed equal to or larger than a predetermined threshold such that the sense signal is equal to or larger than the reference Vref provided for the comparator  52 , a comparison signal So produced by a comparator  52  will signal a controller  54  to stop charging the output capacitor Co. 
 
      The capacitor charger  50  shown in  FIG. 7  is modified to be a third embodiment as shown in  FIG. 8 . Hereof a capacitor charger  60  has the sensor composed of the resistors R 1  and R 2  connected to the inductor L such that the boost diode D 2  is arranged between the resistors R 1  and R 2  and output capacitor Co, by which the output capacitor Co is prevented from a leakage current inversely flowing therefrom to the resistors R 1  and R 2  during the off-time of the transistor  28 .  
       FIG. 9  shows a fourth embodiment according to the present invention. In a capacitor charger  70  having a basic scheme the same as that of the capacitor charger  20  shown in  FIG. 3 , a sensor  72  is provided to sense the input voltage Vin and the tapped voltage V ds2  on the taper  26  for the control of the output voltage Vout. In the sensor  72 , the input voltage Vin and tapped voltage V ds2  are multiplied by two coefficients at two multipliers  722  and  724 , respectively, and combined by a summing circuit  726  to produce a sense signal  
               Vc   =             K   ×   N     N1     ⁢     V   ds2       -         K   ×   N2     N1     ⁢   Vin       =       K   N1     ⁢     (       N   ×     V   ds2       -     N2   ×   Vin       )           ,           [     EQ   ⁢     -     ⁢   15     ]               
 where K is a constant. It is known to those skilled ones in the art that the taper  26  will has the tapped voltage  
                 V   ds2     =         N1   ×   Vout     +     N2   ×   Vin       N       ,           [     EQ   ⁢     -     ⁢   16     ]               
 and by substituting the equation EQ-16 to the equation EQ-15, it is obtained 
   Vc=K×Vout. [EQ- 17] 
 Since the sense signal Vc is proportional to the output voltage Vout, it may be used to monitor the output voltage Vout. The sense signal Vc is compared with a reference Vref by a comparator  74  to produce a comparison signal So for a controller  76  to switch the transistor  28 . Once the output voltage Vout is sensed equal to or larger than a predetermined threshold such that the sense signal is equal to or larger than the reference Vref provided for the comparator  52 , the comparison signal So produced by the comparator  52  will signal the controller  54  to stop charging the output capacitor Co. 
 
       FIG. 10  shows a fifth embodiment according to the present invention. In a capacitor charger  80  having a basic scheme the same as that of the capacitor charger  20  shown in  FIG. 3 , a sense resistor Rs is connected in series to the transistor  28  such that the current I 1  flowing through the segment  22  of the inductor L flows through the sense resistor Rs to produce a voltage drop V 3  across the sense resistor Rs, and a comparator  82  compares the voltage V 3  with a reference Vref to produce a comparison signal So for a controller  84  to switch the transistor  28 . Alternatively, the conductive resistance of the transistor  28  may be used for the sense resistor, and the voltage drop across the transistor  28  is compared with the reference Vref by the comparator  82  to produce the comparison signal So.  
       FIG. 11  shows a sixth embodiment according to the present invention. In a capacitor charger  90  having a basic scheme the same as that of the capacitor charger  20  shown in  FIG. 3 , a comparator  92  and a sample and hold circuit  94  constitute a sensor to sense if the current I 2  flows during the off-time of the transistor  28 . It is known to those skilled ones in the art that the tapped voltage V ds2  follows the equation EQ-16 when the current I 2  flows during the off-time of the transistor  28 , and drops down to the input voltage Vin after the current I 2  stops flowing. When the transistor  28  turns off and the current I 2  flows, the sample and hold circuit  94  samples and holds the tapped voltage V ds2  to produce a sample signal V ds2 ′. The tapped voltage V ds2  and sample signal V ds2 ′ are compared by the comparator  92 . When the tapped voltage V ds2  is smaller than the sample signal V ds2 ′, the comparison signal Ss produced by the comparator  92  will signal a controller  96  to turn on the transistor  28 .  
      While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.