Patent Publication Number: US-4547751-A

Title: System for frequency modulation

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a frequency modulation system which assigns different frequencies f 0  and f 1  to logical values 0 and 1 and generates signals having those two frequencies in a switching manner in accordance with the logical value of an input. 
     2. Description of the Prior Art 
     FIG. 1 is a block diagram showing a system for frequency modulation according to the prior art. An oscillator 101 generating an output F 0  of a frequency f 0  corresponding to the logical value 0 has its output terminal connected to an input terminal 104 of a switching device 103, whereas an oscillator 102 generating an output F 1  of a frequency f 1  corresponding to the logical value 1 has its output terminal connected to an input terminal 105 of the switching device 103. Input data Din to the modulation system is applied directly to a switching input terminal 106 of the switching device 103. Output data D out  from an output terminal 107 of the switching device 103 is applied to a filter 108 limiting its frequency band, the output of which becomes a modulated output M out . 
     The output signal F 0  from the oscillator 101 and the output signal F 1  from the oscillator 102 are not synchronized with each other. Because the input data D in  to the modulation system is applied to the switching input terminal 106 of the switching device 103, the output of the switching device 103 is switched between signal F 1  and signal F 0  independently of the respective phases of signals F 0  and F 1  in accordance with changes in the input signal D in  to the modulation system. 
     FIG. 2 illustrates the waveforms at different parts of the modulation system shown in FIG. 1. In FIG. 2, reference numerals 201 and 202 respectively show output signals F 0  and F 1  of the oscillators 101 and 102, numeral 203 the input signal D in , numeral 204 the output signal D out  from the switching device 103, and numeral 205 the output signal M out  from the filter 108. The signal waveforms of the different parts when an input data D in  having the waveform illustrated by 203 in FIG. 2 is applied to the switching input terminal 106 of the switching device 103 are illustrated by 201, 202, 204, and 205. The input signal D in  203 changes from logical value 0 to logical value 1 at a time T 1 . The output signal from the switching device 103 is switched by that input data D in . More specifically, before time T 1  signal F 0 , the waveform of which is illustrated by 201, is generated as the output signal 107 from the switching device 103, and after time T 1  signal F 1 , the waveform of which is illustrated by 202, is generated. In other words, since the signals F 0  and F 1  and the input data D in  to the input terminal 106 of the switching device 103 are not synchronized with each other, the output signal D out  from the output terminal 107 of the switching device 103 has a waveform whose phase changes abruptly at time T 1 , as shown by 204. The modulated signal M out , which is obtained by filtering the output signal 204 through the filter 108, has a waveform whose amplitude and phase are very distorted in the vicinity of time T 1 , as shown by 205 in FIG. 2. Because of the incompleteness of this modulation system, the time during which there is an indefinite output during the interchange between the logical values 1 and 0 is extended in the prior art within a predetermined band width at the demodulator, so that the bit rate obtainable is lower than the theoretical value determined by the band width. In other words, in order to obtain a predetermined bit rate and bit error rate, it is necessary in the prior art to enlarge the band width of the transmission line sufficiently more than the theoretical value. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to provide a modulation system for generating a modulated signal whose phase does not change abruptly when the frequency is switched. 
     In order to achieve the above object, the present invention is characterized in that the signal F 1  with the frequency f 1  corresponding to the logical value 1 and the signal F 0  with the frequency f 0  corresponding to the logical value 0 are synchronized with each other, and in that the frequency of the output is switched only at an instant when the phase of the signals F 1  and F 0  are coincident. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing the construction of a modulation system according to the prior art; 
     FIG. 2 is a timing chart illustrating the example of the operations of the modulation system of FIG. 1; 
     FIG. 3 is a block diagram showing one embodiment of the modulation system according to the present invention; 
     FIG. 4 is a timing chart illustrating one example of the operations of the modulation system of FIG. 3; and 
     FIGS. 5 to 7 are block diagrams each showing other embodiments of the modulation system according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention will be described in more detail in the following in connection with the embodiments thereof with reference to the accompanying drawings. 
     FIG. 3 shows one embodiment of the modulation system according to the present invention. As shown in FIG. 3, the output F osc  of an output terminal 302 of an oscillator 301 with an oscillatory frequency f osc  is applied to input terminals of a 1/l frequency divider 303 and a 1/m frequency divider 306. An output signal F 0  with a frequency f 0  =f osc  ×1/l from an output terminal 305 of the 1/l frequency divider, and an output signal F 1  with a frequency f 1  =f osc  ×1/m from an output terminal 307 of the 1/m frequency divider are each applied to the input terminals of a switching device 308. The frequency of the output signal F 1  is further divided by n by the action of a 1/n frequency divider 313. The value of n is the smallest integer such that the product m×n is a multiple of the integer l. A timing signal F T  at an output terminal 314 of the 1/n frequency divider 313, which has a frequency f T  =f 1  ×1/n=f osc  ×1/mn which is obtained by dividing the frequency of the output signal F 1  by n in the 1/n frequency divider 313, is input to a sampling device 315 and a reset input terminal 304 of the 1/l frequency divider 303. Input data D in , which has been sampled by the sampling device 315 in response to the timing signal F T , is input to a switching input terminal of the switching device 308. A signal D out  from a terminal 310 of the switching device 308 is applied through a filter 311 to an output terminal 312 to generate a modulated output M out . 
     FIG. 4 illustrates the signal waveforms of the different parts of the modulation system of FIG. 3 when l=6,m=4 and n=3. In FIG. 4, reference numeral 401 illustrates the output signal F osc  from the oscillator 301, numerals 402 and 403 the output signals F 0  and F 1  of the 1/l frequency divider 303 and the 1/n frequency divider 313, respectively, numeral 404 the output signal F T  from the 1/n frequency divider 313, numeral 405 the input data D in , numeral 406 an output signal D s  from the sampling device 315, numeral 407 the output signal D out  from the switching device 308; and numeral 408 the output signal M out  from the filter 311. Both output signals F 0  and F 1  of the 1/l frequency divider 303 and the 1/m frequency divider 306, which are illustrated by 402 and 403 respectively in FIG. 4, are prepared by dividing the frequency of the output signal F osc  of the same oscillator 301 illustrated by, 401 in FIG. 4, so that they are synchronized with each other. Since the ratio of the frequency f 0  of signal F 0  to the frequency f 1  of signal F 1  is set at 2:3, the signals F 0  and F 1  are in phase with each other every two cycles of the signal F 0  and every three cycles of the signal F 1 . In short, the two signals F 0  and F 1  fall simultaneously with each other. Specifically, the timing signal F T , which is obtained by dividing the frequency of the signal F 1  by n, i.e., three, falls once every three cycles of the signal F 1 . The 1/l frequency divider 303 is reset by the timing signal F T  thus obtained. In other words, when the timing signal F T  falls, the output of the 1/l frequency divider 303 is also made to fall. As a result, when the timing signal F T  falls, both signals F 0  and F 1  fall, which makes their phases coincident with each other. Similar results can be obtained by resetting the 1/n frequency divider 306 by detecting when both the outputs of the 1/l frequency divider 303 and the 1/m frequency divider 306 falls. 
     The operations will be described in the following by taking as an example the case in which the data D in  having a waveform illustrated by 405 in FIG. 4 is input to the modulation system. The input data D in  is sampled by the sampling device 315, when the timing signal F T  illustrated by 404 in FIG. 4 falls, so that a sampled value is generated at the output terminal of the sampling device 315. The signal thus generated at the output terminal of the sampling device 315 holds its value until the next time the timing signal F T  falls. As a result, the signal D s , which is obtained by sampling the input data D in  with the timing signal F T , has a waveform the value of which can change, as illustrated by 406 in FIG. 4, only when the timing signal F T  falls. In the example under discussion, the value of the signal D s  changes from 0 to 1 at time T 1  so that the signal generated at the output terminal 310 of the switching device 308 is switched from the signal F 0  to the signal F 1  at the time T 1  in accordance with the change in the signal D s . At time T 1 , the phases of both signals F 0  and F 1  are at 0 (i.e., at the fall) so that the output signal D out  obtained from the switching device 308 has a waveform such that its phase has no discontinuity even at the frequency change, as illustrated by 407 in FIG. 4. Thus, the modulated signal M out , which is obtained by filtering the output signal D out  from the switching device 308 through the filter 310, becomes a signal that always has a predetermined amplitude, has no abrupt change in phase, and has little distortion, as illustrated by 408 in FIG. 4. As a result, at the demodulator, the transient period of time during the interchange between the logical values 1 and 0 is so reduced that a higher bit rate than that of the prior art can be obtained within a predetermined band width . 
     Since there are no unnecessary spectral components, and, thus, the power ratio occupied by the signal component in the signal wave is increased , the S/N ratio can be increased on the reception side. 
     FIG. 5 is a block diagram showing another embodiment of the modulation system according to the present invention. In this embodiment, the input data D in  is sampled by the output signal of the 1/l frequency divider 303, and the 1/m frequency divider 306 and the 1/n frequency divider 313 are reset. This time, incidentally, l is the least common multiple of the integers m and n. 
     FIG. 6 is a block diagram showing a third embodiment of the modulation system according to the present invention. The 1/l frequency divider 303 is reset by the output signal of the 1/n frequency divider 313, and the timing signal F T  is generated so that input data D in  synchronized with that timing signal F T  by a synchronizer 316 is input to the switching device 308. In this case, the multiple m×n is the least common multiple of both the integers m and l. 
     FIG. 7 is a block diagram showing a fourth embodiment of the modulation system according to the present invention. the 1/m frequency divider 306 and the 1/n frequency divider 313 are reset by the output of the 1/l frequency divider 303, and the timing signal F T  is generated so that input data D in  synchronized with the timing signal F T  by a synchronizer 316 is input to the switching device 308. In this embodiment, l is the least common multiple of the integers m and n. 
     As has been described hereinbefore, according to the present invention it is possible to generate a FSK (i.e., Frequency Shift Keying) signal, the phase of which changes continuously even at the interchanges of the frequencies, and which has few unnecessary spectral components, thereby providing signals with a narrower band and higher quality than those of the prior art.