Patent Publication Number: US-2023152929-A1

Title: Display panel and display apparatus

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation-in-part of International Application No. PCT/CN2020/107770, filed Aug. 7, 2020. Each of the forgoing applications is herein incorporated by reference in its entirety for all purposes. 
    
    
     TECHNICAL FIELD 
     The present invention relates to display technology, more particularly, to a display panel and a display apparatus. 
     BACKGROUND 
     Various types of touch panels have been developed. Examples of touch panels include one-glass-solution (OGS) touch panels, on-cell touch panels, and in-cell touch panels. The on-cell touch panels provide high touch control accuracy. The on-cell touch panels can be classified into single-layer-on-cell (SLOC) touch panels and multi-layer-on-cell (MLOC) touch panels. In particular, multiple point touch control can be achieved in the MLOC touch panels with superior touch control accuracy and blanking effects. 
     SUMMARY 
     In one aspect, the present disclosure provides a display panel, in a display region configured to display an image, comprising a base substrate; thin film transistors and display elements on the base substrate; an encapsulating layer encapsulating the display elements; and a touch electrode layer comprising mesh electrodes on a side of the encapsulating layer away from the base substrate; wherein, in a transition region adjacent to the display region, the touch electrode layer and the encapsulating layer are at least partially present; and in a first window region adjacent to the transition region, at least the display elements, the touch electrode layer, and the encapsulating layer are absent; wherein the encapsulating layer comprises at least an organic encapsulating sub-layer having a first thickness in at least a sub-region of the transition region, and a second thickness in the display region, the first thickness being smaller than the second thickness; and mesh electrode lines of the mesh electrodes have a first line width in at least the sub-region of the transition region, and a second line width in the display region, the first line width being greater than the second line width. 
     Optionally, a periphery of the first window region is at least partially surrounded by a combination of the display region and the transition region; and a thickness of the organic encapsulating sub-layer in the sub-region of the transition region gradually decreases along a direction from the sub-region of the transition region toward the first window region. 
     Optionally, a respective boundary between the transition region and the display region comprises transition points at which line widths of the mesh electrode lines transition from the first line width to the second line width. 
     Optionally, the first thickness is smaller than the second thickness by at least 30%; and the first line width is greater than the second line width by at least 15%. 
     Optionally, a difference between the first line width at a point in at least the sub-region of the transition region and the second line width is expressed as Δw=−0.0016 x 4 +0.073 x 3 −1.2112 x 2 +8.8493 x−23.268; wherein Δw stands for the difference between the first line width and the second line width; and x stands for a thickness of the organic encapsulating sub-layer at the point in at least the sub-region of the transition region. 
     Optionally, in a second window region adjacent to the transition region, at least the display elements, the touch electrode layer, and the encapsulating layer are absent; the transition region comprises an inter-window region between the first window region and the second window region; the organic encapsulating sub-layer has the first thickness in at least the sub-region of the inter-window region, and the second thickness in the display region; and mesh electrode lines of the mesh electrodes have the first line width in at least the sub-region of the inter-window region, and the second line width in the display region. 
     Optionally, a periphery of the first window region is at least partially surrounded by a combination of the display region and the inter-window region; a periphery of the second window region is at least partially surrounded by a combination of the display region and the inter-window region; a periphery of the inter-window region is at least partially surrounded by a combination of the display region, the first window region, and the second window region; a respective boundary between the inter-window region and the display region comprises transition points at which line widths of the mesh electrode lines transition from the first line width to the second line width; and a thickness of the organic encapsulating sub-layer in the sub-region of the transition region gradually decreases along a direction from the sub-region of the inter-window region toward the first window region or toward the second window region. 
     Optionally, the mesh electrode lines comprises an inter-region mesh electrode line extending from the transition region into the display region; the inter-region mesh electrode line comprises a first sub-line in the transition region and a second sub-line in the display region, the first sub-line directly being connected with the second sub-line; the first sub-line has a first sub-line width; the second sub-line has a second sub-line width; and the first sub-line width is greater than the second sub-line width. 
     Optionally, the inter-region mesh electrode line is directly adjacent to an inter-region gap extending from the transition region into the display region; the inter-region gap comprises a first sub-gap in the transition region and a second sub-gap in the display region, the first sub-gap directly being connected with the second sub-gap; the first sub-gap has a first sub-gap width; the second sub-gap has a second sub-gap width; and the first sub-gap width is greater than the second sub-gap width. 
     Optionally, at least a first portion of a boundary of the first sub-gap in the transition region is formed by virtually connecting outer edges of the first sub-line of the inter-region mesh electrode line; at least a second portion of a boundary of the second sub-gap in the display region is formed by virtually connecting outer edges of the second sub-line of the inter-region mesh electrode line; and the first portion and the second portion are directly connected. 
     Optionally, the touch electrode layer comprises a plurality of first touch electrodes and a plurality of second touch electrodes; wherein, in the transition region, a first respective one of the plurality of first touch electrodes and a second respective one of the plurality of second touch electrodes directly adjacent to each other are spaced apart by a first gap having a first gap width; in the display region, a third respective one of the plurality of first touch electrodes and a fourth respective one of the plurality of second touch electrodes directly adjacent to each other are spaced apart by a second gap having a second gap width; and the first gap width is greater than the second gap width. 
     Optionally, a fifth respective one of the plurality of first touch electrodes and a sixth respective one of the plurality of second touch electrodes directly adjacent to each other are spaced apart by an inter-region gap extending from the transition region into the display region; the inter-region gap comprises a first sub-gap in the transition region and a second sub-gap in the display region, the first sub-gap being directly connected with the second sub-gap; the first sub-gap has a first sub-gap width; the second sub-gap has a second sub-gap width; and the first sub-gap width is greater than the second sub-gap width. 
     Optionally, the plurality of first touch electrodes and the plurality of second touch electrodes are mesh electrodes comprising mesh electrode lines; multiple mesh electrode lines directly adjacent to the first sub-gap have a line width greater than multiple mesh electrode lines directly adjacent to the second sub-gap. 
     Optionally, the plurality of first touch electrodes are a plurality of first mesh electrodes, each of which comprising a plurality of first mesh electrode lines; the plurality of second touch electrodes are a plurality of second mesh electrodes, each of which comprising a plurality of second mesh electrode lines; the first gap has a first boundary formed by virtually connecting outer edges of multiple first mesh electrode lines of the first respective one of the plurality of first touch electrodes, and a second boundary formed by virtually connecting outer edges of multiple second mesh electrode lines of the second respective one of the plurality of second touch electrodes; the second gap has a third boundary formed by virtually connecting outer edges of multiple first mesh electrode lines of the third respective one of the plurality of first touch electrodes, and a fourth boundary formed by virtually connecting outer edges of multiple second mesh electrode lines of the fourth respective one of the plurality of second touch electrodes; the first gap width is a first shortest distance between the first boundary and the second boundary; and the second gap width is a second shortest distance between the third boundary and the fourth boundary. 
     Optionally, the touch electrode layer comprises a plurality of first touch electrodes and a plurality of second touch electrodes; a respective one of the plurality of first touch electrodes comprises a plurality of first touch electrode blocks arranged along a first direction; a respective one of the plurality of second touch electrodes comprises a plurality of second touch electrode blocks arranged along a second direction; the plurality of first touch electrode blocks are electrically connected to form a first conductive channel along the first direction, adjacent first touch electrode blocks of the plurality of first touch electrode blocks are connected through a first electrode bridge; the plurality of second touch electrode blocks are electrically connected to form a second conductive channel along the second direction, adjacent second touch electrode blocks of the plurality of second touch electrode blocks are connected through a second electrode bridge; the plurality of first touch electrode blocks, the plurality of second touch electrode blocks, and one of the first electrode bridge and the second electrode bridge are in a first touch material layer, and made of a same material; and another of the first electrode bridge and the second electrode bridge is in a second touch material layer different from the first touch material layer. 
     Optionally, the display panel further comprises a plurality of thin film transistors in the display region and in the transition region; wherein the display panel comprises a base substrate; an insulating layer on the base substrate; an active layer of a respective one of the plurality of thin film transistors on a side of the insulating layer away from the base substrate; a first gate insulating layer on a side of the active layer away from the base substrate; a gate electrode and a first capacitor electrode on a side of the first gate insulating layer away from the insulating layer; a second gate insulating layer on a side of the gate electrode and the first capacitor electrode away from the first gate insulating layer; a second capacitor electrode on a side of the second gate insulating layer away from the first gate insulating layer; an inter-layer dielectric layer on a side of the second capacitor electrode away from the second gate insulating layer; a source electrode and a drain electrode on a side of the inter-layer dielectric layer away from the second gate insulating layer; a passivation layer on a side of the source electrode and the drain electrode away from the inter-layer dielectric layer; a first planarization layer on a side of the passivation layer away from the inter-layer dielectric layer; a second planarization layer on side of the first planarization layer away from the passivation layer; a relay electrode on a side of the second planarization layer away from the first planarization layer; and a pixel definition layer on a side of the second planarization layer away from the base substrate. 
     Optionally, the display panel further comprises a plurality of display elements in the display region and at least a dummy light emitting element in the transition region; wherein the display panel comprises an anode on a side of a second planarization layer away from a first planarization layer, the anode is limited in the display region and absent in the transition region; a light emitting layer in the display region and in the transition region, the light emitting layer in the display region being on a side of the anode away from the second planarization layer, the light emitting layer in the transition region being on a side of the second planarization layer away from the first planarization layer; a cathode layer in the display region and in the transition region, the cathode layer being on a side of the light emitting layer away from the second planarization layer; and an encapsulating layer on a side of the cathode layer away from the light emitting layer, the encapsulating layer encapsulating the plurality of display elements in the display region and the dummy light emitting element in the transition region. 
     Optionally, the encapsulating layer further comprises a first inorganic encapsulating sub-layer on a side of an organic encapsulating sub-layer closer to the base substrate, and a second inorganic encapsulating sub-layer on a side of an organic encapsulating sub-layer away from the base substrate; wherein the display panel further comprises a buffer layer on a side of the second inorganic encapsulating sub-layer away from the base substrate and in direct contact with the second inorganic encapsulating sub-layer; a first touch material layer on a side of the buffer layer away from the base substrate and in direct contact with the buffer layer; a touch insulating layer comprising touch electrode bridges on a side of the first touch material layer away from the base substrate and in direct contact with the buffer layer; and a second touch material layer comprises mesh electrode blocks on a side of the touch insulating layer away from the base substrate. 
     Optionally, an organic material is absent in an inter-layer space between the touch insulating layer and the buffer layer. 
     Optionally, the display panel further comprises a first accessory installed in a first hole in the first window region. 
     In another aspect, the present disclosure provides a display apparatus, comprising the display panel described herein or fabricated by a method described herein, and an integrated circuit connected to the display panel. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present invention. 
         FIG.  1    illustrates a display region, a first window region, and a transition region in a display panel in some embodiments according to the present disclosure. 
         FIG.  2    illustrates a display region, a first window region, a second window region, and a transition region in a display panel in some embodiments according to the present disclosure. 
         FIG.  3 A  is a plan view of a display panel in some embodiments according to the present disclosure. 
         FIG.  3 B  is a cross-sectional view along an A-A′ line in  FIG.  3 A . 
         FIG.  3 C  is a cross-sectional view along a B-B′ line in  FIG.  3 A . 
         FIG.  3 D  is a cross-sectional view along a C-C′ line in  FIG.  3 A . 
         FIG.  3 E  is a schematic diagram of a first window region, a second window region, and an inter-window region in a display panel depicted in  FIG.  1 A . 
         FIG.  3 F  illustrates a detailed structure in a region transitioning from a display region to a window region in a display panel in some embodiments according to the present disclosure. 
         FIG.  3 G  illustrates a detailed structure in an inter-window region in a display panel in some embodiments according to the present disclosure. 
         FIG.  3 H  illustrates a detailed structure in a display region in a display panel in some embodiments according to the present disclosure. 
         FIG.  3 I  illustrates a detailed structure in a display region in a display panel in some embodiments according to the present disclosure. 
         FIG.  3 J  is a schematic diagram illustrating barrier structures defining window regions and an inter-window region in a display panel in some embodiments according to the present disclosure. 
         FIG.  3 K  illustrates a correlation between decreases in values of the critical dimension of the mesh electrode lines and the thickness of the underlying organic encapsulating sub-layer in a portion of a display panel in which mesh electrode lines are fabricated using a mask plate with openings having a uniform opening width. 
         FIG.  3 L  illustrates a correlation between the values of critical dimensions of the mesh electrode lines and the thickness of the underlying organic encapsulating sub-layer in a portion of a display panel in which mesh electrode lines are fabricated using a mask plate with openings having a uniform opening width. 
         FIG.  4    is a cross-sectional view of a region of a display panel in some embodiments according to the present disclosure. 
         FIG.  5    is a cross-sectional view of a region of a display panel in some embodiments according to the present disclosure. 
         FIG.  6    illustrates a sub-region in a transition region in a display panel in some embodiments according to the present disclosure. 
         FIG.  7    illustrates a sub-region in a transition region in a display panel in some embodiments according to the present disclosure. 
         FIG.  8    illustrates a sub-region in a transition region in a display panel in some embodiments according to the present disclosure. 
         FIG.  9    illustrates an inter-region boundary of an inter-window region in some embodiments according to the present disclosure. 
         FIG.  10 A  illustrates the structure of mesh electrodes lines adjacent to a first inter-region boundary of an inter-window region in some embodiments according to the present disclosure. 
         FIG.  10 B  illustrates the structure of mesh electrodes lines adjacent to a second inter-region boundary of an inter-window region in some embodiments according to the present disclosure. 
         FIG.  11    illustrates a correlation between compensation values of critical dimensions of the mesh electrode lines and the thickness of the underlying organic encapsulating sub-layer in a portion of a display panel in some embodiments according to the present disclosure. 
         FIG.  12 A  is a zoom-in view of two adjacent touch electrodes in an inter-window region of a display panel in some embodiments according to the present disclosure. 
         FIG.  12 B  is a zoom-in view of two adjacent touch electrodes in a display region of a display panel in some embodiments according to the present disclosure. 
         FIG.  13 A  is a zoom-in view of multiple touch electrodes in an inter-window region of a display panel in some embodiments according to the present disclosure. 
         FIG.  13 B  is a zoom-in view of multiple touch electrodes in a display region of a display panel in some embodiments according to the present disclosure. 
         FIG.  14    is a zoom-in view of a region surrounding an inter-window region of a display panel in some embodiments according to the present disclosure. 
         FIG.  15    is a zoom-in view of a first zoom-in region ZR 1  in  FIG.  14   . 
         FIG.  16    is a zoom-in view of a second zoom-in region ZR 2  in  FIG.  14   . 
         FIG.  17    is a zoom-in view of a third zoom-in region ZR 3  in  FIG.  14   . 
         FIG.  18    is a zoom-in view of a fourth zoom-in region ZR 4  in  FIG.  14   . 
         FIG.  19    is a zoom-in view of a fifth zoom-in region ZR 5  in  FIG.  14   . 
         FIG.  20    illustrates a first gap in an inter-window region in a display panel in some embodiments according to the present disclosure. 
         FIG.  21    illustrates a second gap in a display region in a display panel in some embodiments according to the present disclosure. 
         FIG.  22    is a zoom-in view of a region surrounding a boundary between an inter-window region and a display region of a display panel in some embodiments according to the present disclosure. 
         FIG.  23 A  is a partial cross-sectional view of a display panel in an inter-window region in some embodiments according to the present disclosure. 
         FIG.  23 B  is a partial cross-sectional view of a display panel in a display region in some embodiments according to the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The disclosure will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of some embodiments are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. 
     The present disclosure provides, inter alia, a display panel and a display apparatus that substantially obviate one or more of the problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides a display panel. In some embodiments, in a display region configured to display an image, the display panel includes a base substrate; thin film transistors and display elements on the base substrate; an encapsulating layer encapsulating the display elements; and a touch electrode layer comprising mesh electrodes on a side of the encapsulating layer away from the base substrate. In some embodiments, in a transition region adjacent to the display region, at least the touch electrode layer and the encapsulating layer are at least partially present. In some embodiments, in a first window region adjacent to the transition region, at least the display elements, the touch electrode layer, and the encapsulating layer are absent. Optionally, the encapsulating layer includes at least an organic encapsulating sub-layer having a first thickness in at least a sub-region of the transition region, and a second thickness in the display region, the first thickness smaller than the second thickness. Optionally, mesh electrode lines of the mesh electrodes have a first line width in at least the sub-region of the transition region, and a second line width in the display region, the first line width being greater than the second line width. 
       FIG.  1    illustrates a display region, a first window region, and a transition region in a display panel in some embodiments according to the present disclosure. Referring to  FIG.  1   , the display panel in some embodiments includes a display region DA configured to display an image, a first window region WR 1 , and a transition region TR between the display region DA and the first window region WR 1 . In some embodiments, as discussed in further details below, the display panel in the display region DA includes a base substrate; thin film transistors and display elements on the base substrate; an encapsulating layer encapsulating the display elements; and a touch electrode layer comprising mesh electrodes on a side of the encapsulating layer away from the base substrate. In the transition region TR adjacent to the display region DA, at least the touch electrode layer and the encapsulating layer are at least partially present. In the first window region WR 1  adjacent to the transition region TR, at least the display elements, the touch electrode layer, and the encapsulating layer are absent. 
     As used herein, the term “display region” refers to an area of a display panel where image is actually displayed. Optionally, the display region may include both a subpixel region and an inter-subpixel region. A subpixel region refers to a light emission region of a subpixel, such as a region corresponding to a pixel electrode in a liquid crystal display or a region corresponding to a light emissive layer in an organic light emitting diode display panel. An inter-subpixel region refers to a region between adjacent subpixel regions, such as a region corresponding to a black matrix in a liquid crystal display or a region corresponding a pixel definition layer in an organic light emitting diode display panel. Optionally, the inter-subpixel region is a region between adjacent subpixel regions in a same pixel. Optionally, the inter-subpixel region is a region between two adjacent subpixel regions from two adjacent pixels. 
     In some embodiments, and referring to  FIG.  1   , a periphery of the first window region WR 1  is at least partially surrounded by a combination of the display region DA and the transition region TR. 
       FIG.  2    illustrates a display region, a first window region, a second window region, and a transition region in a display panel in some embodiments according to the present disclosure. Referring to  FIG.  2   , the display panel in some embodiments includes a display region DA configured to display an image, a first window region WR 1 , a second window region WR 2 , and a transition region TR between the first window region WR 1  and the second window region WR 2 . In some embodiments, as discussed in further details below, the display panel in the display region DA includes a base substrate; thin film transistors and display elements on the base substrate; an encapsulating layer encapsulating the display elements; and a touch electrode layer comprising mesh electrodes on a side of the encapsulating layer away from the base substrate. In the transition region TR adjacent to the display region DA, at least the touch electrode layer and the encapsulating layer are at least partially present. In the first window region WR 1  adjacent to the transition region TR, at least the display elements, the touch electrode layer, and the encapsulating layer are absent. In a second window region adjacent to the transition region, at least the display elements, the touch electrode layer, and the encapsulating layer are absent. The transition region TR in some embodiments is an inter-window region (as discussed in further details below) between the first window region WR 1  and the second window region WR 2 . 
     In some embodiments, and referring to  FIG.  2   , a periphery of the first window region WR 1  is at least partially surrounded by a combination of the display region DA and the transition region TR (e.g., the inter-window region); a periphery of the second window region WR 2  is at least partially surrounded by a combination of the display region DA and the transition region TR (e.g., the inter-window region); a periphery of the transition region TR (e.g., the inter-window region) is at least partially surrounded by a combination of the display region DA, the first window region WR 1 , and the second window region WR 2 . 
     The inter-window region is a small region between two window regions. In encapsulating the display panel, the encapsulating layer in the inter-window region is typically formed unevenly, resulting in an uneven surface. When forming the touch electrode layer in the inter-window region using related techniques, due to the uneven surface underneath, adjacent touch electrodes (particularly mesh electrode lines from adjacent touch electrodes) are prone to short and various other issues. However, the present disclosure adopts a novel and advantageous touch electrode design that obviate these issues. 
       FIG.  3 A  is a plan view of a display panel in some embodiments according to the present disclosure.  FIG.  3 B  is a cross-sectional view along an A-A′ line in  FIG.  3 A .  FIG.  3 C  is a cross-sectional view along a B-B′ line in  FIG.  3 A .  FIG.  3 D  is a cross-sectional view along a C-C′ line in  FIG.  3 A . Referring to  FIG.  3 A  to  FIG.  3 D , the display panel in some embodiments includes an array substrate AS and a counter substrate CS. The display panel has a display region DA configured to display an image, a first window region WR 1 , a second window region WR 2 , and an inter-window region IWR between the first window region WR 1  and the second window region WR 2 . The inter-window region IWR is directly adjacent to the first window region WR 1  and directly adjacent to the second window region WR 2 . Optionally, as shown in  FIG.  3 A , the first window region WR 1 , the second window region WR 2 , and the inter-window region IWR are surrounded by the display region DA. For example, the first window region WR 1 , the second window region WR 2 , and the inter-window region IWR together form an island region, which is surrounded by the display region DA. 
     Referring to  FIG.  3 B  and  FIG.  3 C , the display panel in some embodiments includes a first hole H 1  in the first window region WR 1  and a second hole H 2  in the second window region WR 2 . In some embodiments, at least one of the first hole H 1  and the second hole H 2  is a blind hole that does not completely extends through at least one layer of the array substrate AS or the counter substrate CS. Optionally, the first hole H 1  is a blind hole that does not extend through the base substrate BS of the array substrate AS (as shown in  FIG.  3 B ). Optionally, the second hole H 2  is a blind hole that does not extend through the base substrate BS of the array substrate AS (as shown in  FIG.  3 B ). In some embodiments, at least one of the first hole H 1  and the second hole H 2  is a through-hole that completely extends through the array substrate AS and the counter substrate CS. Optionally, the first hole H 1  extends through the array substrate AS and the counter substrate CS. Optionally, the second hole H 2  extends through the array substrate AS and the counter substrate CS. 
     Referring to  FIG.  3 B  and  FIG.  3 C , the display panel in some embodiments further includes a first accessory AY 1  installed in the first hole H 1  and a second accessory AY 2  installed in a second hole H 2 . Examples of accessories include a camera lens and a fingerprint sensor. 
     In some embodiments, display elements and thin film transistors are absent in the first window region WR 1  and the second window region WR 2 . Optionally, the display elements includes a plurality of light emitting diodes, for example, in an organic light emitting diode display panel. Optionally, the display elements include a liquid crystal layer in a plurality of subpixels, for example, in a liquid crystal display panel. Referring to  FIG.  3 B  to  FIG.  3 D , in some embodiments, the array substrate AS includes a base substrate BS, a plurality of thin film transistors TFT on the base substrate BS, and a plurality of light emitting elements LE on the base substrate BS and respectively connected to the plurality of thin film transistors TFT. Optionally, the plurality of thin film transistors TFT are absent in the first window region WR 1 . Optionally, the plurality of thin film transistors TFT are absent in the second window region WR 2 . Optionally, the plurality of light emitting elements LE are absent in the first window region WR 1 . Optionally, the plurality of light emitting elements LE are absent in the second window region WR 2 . 
     Referring to  FIG.  3 B  to  FIG.  3 D , in some embodiments, the array substrate AS further includes an encapsulating layer EN encapsulating the plurality of light emitting elements LE. Optionally, the encapsulating layer EN is absent in the first window region WR 1 . Optionally, the encapsulating layer EN is absent in the second window region WR 2 . Optionally, the encapsulating layer EN is present in the display region DA and the inter-window region IWR. 
     Referring to  FIG.  3 B  to  FIG.  3 D , in some embodiments, the counter substrate CS includes a buffer layer BUF. Optionally, the buffer layer BUF is absent in the first window region WR 1 . Optionally, the buffer layer BUF is absent in the second window region WR 2 . Optionally, the buffer layer BUF is present in the display region DA and the inter-window region IWR. 
     Referring to  FIG.  3 B  to  FIG.  3 D , in some embodiments, the counter substrate CS further includes a touch insulating layer TI. Optionally, the touch insulating layer TI is absent in the first window region WR 1 . Optionally, the touch insulating layer TI is absent in the second window region WR 2 . Optionally, the touch insulating layer TI is present in the display region DA and the inter-window region IWR. 
     Optionally, the inter-window region IWR is capable of displaying an image. In one example, the display panel in the inter-window region IWR includes one or more light emitting elements. In another example, the display panel in the inter-window region IWR includes one or more thin film transistors. 
     Optionally, the inter-window region IWR is incapable of displaying an image. In one example, the plurality of light emitting elements LE are absent in the inter-window region IWR. In another example, the plurality of thin film transistors TFT are absent in the inter-window region IWR. 
     Referring to  FIG.  3 A  to  FIG.  3 D , the display panel in some embodiments further includes a touch electrode layer in the display region DA and in the inter-window region IWR. The touch electrode layer includes a plurality of first touch electrodes TE 1  and a plurality of second touch electrodes TE 2 , for example, the display panel is a mutual capacitance type touch control display panel. Optionally, the plurality of first touch electrodes TE 1  are a plurality of touch scanning electrodes, and the plurality of second touch electrodes TE 2  are a plurality of touch sensing electrodes. Optionally, the plurality of first touch electrodes TE 1  are a plurality of touch sensing electrodes, and the plurality of second touch electrodes TE 2  are a plurality of touch scanning electrodes. Optionally, a respective one of the plurality of first touch electrodes TE 1  includes a plurality of first touch electrode blocks, e.g., in a respective row. Adjacent first touch electrode blocks of the plurality of first touch electrode blocks are connected through a first electrode bridge BR 1 . Optionally, a respective one of the plurality of second touch electrodes TE 2  includes a plurality of second touch electrode blocks, e.g., in a respective column. Adjacent second touch electrode blocks of the plurality of second touch electrode blocks are connected through a respective one of a plurality of second electrode bridges BR 2 . 
     Optionally, the plurality of first touch electrodes TE 1  and the plurality of second touch electrodes TE 2  are in a same layer. 
     Optionally, the plurality of first touch electrodes TE 1  and the plurality of second touch electrodes TE 2  are in different layers. 
     Optionally, the plurality of first touch electrodes TE 1 , the plurality of second touch electrodes TE 2 , and the first electrode bridge BR 1  are in a same layer. Optionally, the plurality of second electrode bridges BR 2  are on a side of the buffer layer BUF away from the encapsulating layer EN. Optionally, the plurality of first touch electrodes TE 1 , the plurality of second touch electrodes TE 2 , and the first electrode bridge BR 1  are on a side of the touch insulating layer TI away from the plurality of second electrode bridges BR 2 . 
     Optionally, the first electrode bridge BR 1  is a part of a unitary structure of a respective one of the plurality of first touch electrodes TE 1  For example, a respective one of the plurality of first touch electrodes TE 1  has a unitary structure including a plurality of first touch electrode blocks and first electrode bridges respectively connecting adjacent first touch electrode blocks. The plurality of first touch electrode blocks and the first electrode bridges are made of a same material and formed in a same patterning process. 
       FIG.  3 A  depicts an example in which two window regions are present in the display panel. The present disclosure may be implemented in display panels having two window regions, or in display panels having any number of window regions (e.g., 1, 2, 3, 4, or 5 window regions). The transition region TR in the context of display panels having two window regions may be understood to include an inter-window region IWR. In one example, the transition region TR in the context of display panels having two window regions refers to the inter-window region IWR in display panels having two window regions. 
       FIG.  3 E  is a schematic diagram of a first window region, a second window region, and an inter-window region in a display panel depicted in  FIG.  1   . Referring to  FIG.  3 E , in some embodiments, the inter-window region IWR is defined by boundaries on at least four sides including a first side S 1 , a second side S 2 , a third side S 3 , and a fourth side S 4 . Optionally, the first side S 1  and the second side S 2  are arranged along a first direction D 1  from the first window region WR 1  to the second window region WR 2 . Optionally, the third side S 3  and the fourth side S 4  are arranged along a second direction D 2  substantially perpendicular to the first direction D 1 . 
     Optionally, a first region boundary RB 1  of the inter-window region IWR on the first side S 1  does not exceed a first outer boundary O 1  of the first window region WR 1  directly adjacent to the inter-window region IWR. In one example, the first region boundary RB 1  of the inter-window region IWR on the first side S 1  is between the first outer boundary O 1  of the first window region WR 1  directly adjacent to the inter-window region IWR and a second outer boundary O 2  of the second window region WR 2  directly adjacent to the inter-window region IWR. In another example, the first region boundary RB 1  of the inter-window region IWR on the first side S 1  at least partially or completely overlaps with the first outer boundary O 1  of the first window region WR 1  directly adjacent to the inter-window region IWR. In another example, the first region boundary RB 1  of the inter-window region IWR on the first side S 1  is non-overlapping with the first outer boundary O 1  of the first window region WR 1  directly adjacent to the inter-window region IWR. 
     Optionally, a second region boundary RB 2  of the inter-window region IWR on the second side S 2  does not exceed a second outer boundary O 2  of the second window region WR 2  directly adjacent to the inter-window region IWR. In one example, the second region boundary RB 2  of the inter-window region IWR on the second side S 2  is between the first outer boundary O 1  of the first window region WR 1  directly adjacent to the inter-window region IWR and the second outer boundary O 2  of the second window region WR 2  directly adjacent to the inter-window region IWR. In another example, the second region boundary RB 2  of the inter-window region IWR on the second side S 2  at least partially or completely overlaps with the second outer boundary O 2  of the second window region WR 2  directly adjacent to the inter-window region IWR. In another example, the second region boundary RB 2  of the inter-window region IWR on the second side S 2  is non-overlapping with the second outer boundary O 2  of the second window region WR 2  directly adjacent to the inter-window region IWR. 
     Optionally, a third region boundary RB 3  of the inter-window region IWR on the third side S 3  does not exceed a first imaginary connecting line C 1  virtually connecting outer edges of the first window region WR 1  and the second window region WR 2  on the third side S 3 . 
     Optionally, a fourth boundary RB 4  of the inter-window region IWR on the fourth side S 4  does not exceed a second imaginary connecting line C 2  virtually connecting outer edges of the first window region WR 1  and the second window region WR 2  on the fourth side S 4 . 
     In one example, the third region boundary RB 3  of the inter-window region IWR on the third side S 3  is between the first imaginary connecting line C 1  and the second imaginary connecting line C 2 . In another example, the third region boundary RB 3  of the inter-window region IWR on the third side S 3  at least partially or completely overlaps with the first imaginary connecting line C 1 . In another example, the third region boundary RB 3  of the inter-window region IWR on the third side S 3  is non-overlapping with the first imaginary connecting line C 1 . 
     In one example, the fourth boundary RB 4  of the inter-window region IWR on the fourth side S 4  is between the first imaginary connecting line C 1  and the second imaginary connecting line C 2 . In another example, the fourth boundary RB 4  of the inter-window region IWR on the fourth side S 4  at least partially or completely overlaps with the second imaginary connecting line C 2 . In another example, the fourth boundary RB 4  of the inter-window region IWR on the fourth side S 4  is non-overlapping with the second imaginary connecting line C 2 . 
       FIG.  3 F  illustrates a detailed structure in a region transitioning from a display region to a window region in a display panel in some embodiments according to the present disclosure. Referring to  FIG.  3 F , in some embodiments, the region transitioning from a display region to a window region WR (e.g., a first window region WR 1  or a second window region WR 2 ) includes a base substrate BS (e.g., a flexible base substrate); an insulating layer IN on the base substrate BS; a first gate insulating layer GI 1  on a side of the insulating layer IN away from the base substrate BS; a first gate metal layer GM 1  on a side of the first gate insulating layer GI 1  away from the insulating layer IN; a second gate insulating layer GI 2  on a side of the first gate metal layer GM 1  away from the first gate insulating layer GI 1 ; a second gate metal layer GM 2  on a side of the second gate insulating layer GI 2  away from the first gate insulating layer GI 1 ; an inter-layer dielectric layer ILD on a side of the second gate metal layer GM 2  away from the second gate insulating layer GI 2 ; a second SD metal layer SD 2  on a side of the inter-layer dielectric layer ILD away from the second gate insulating layer GI 2 ; a planarization layer PLN on a side of the second SD metal layer SD 2  away from the inter-layer dielectric layer ILD, a pixel definition layer PDL defining a plurality of subpixel regions for the plurality of light emitting elements LE, the pixel definition layer PDL on a side of the planarization layer PLN away from the base substrate BS; a cathode layer CD on a side the pixel definition layer PDL, the planarization layer PLN, and the second SD metal layer SD 2  away from the base substrate BS; an encapsulating layer EN encapsulating the plurality of light emitting elements, and on a side of the cathode layer CD away from the base substrate BS. The encapsulating layer EN in some embodiments includes a first inorganic encapsulating sub-layer CVD 1  on a side of the cathode layer CD away from the base substrate BS, an organic encapsulating sub-layer UP on a side of the first inorganic encapsulating sub-layer CVD 1  away from the base substrate BS, and a second inorganic encapsulating sub-layer CVD 2  on a side of the organic encapsulating sub-layer UP away from the first inorganic encapsulating sub-layer CVD 1 . Optionally, the display panel, in the region transitioning from the display region DA to the window region WR, further includes a passivation layer between the inter-layer dielectric layer ILD and the planarization layer PLN. 
     In some embodiments, the display panel, in the region transitioning from the display region DA to the window region WR, includes a barrier structure DAM completely surrounding a hole H (e.g., the first hole H 1  or the second hole H 2 ). In some embodiment, the barrier structure DAM includes a first barrier layer BL 1  and a second barrier layer BL 2  sequentially surrounding the hole H. Optionally, the first barrier layer BL 1  includes a first barrier sub-layer BL 1 - 1  and a second barrier sub-layer BL 1 - 2 . Optionally, the second barrier layer BL 2  includes a third barrier sub-layer BL 2 - 1  and a fourth barrier sub-layer BL 2 - 2 . Optionally, the first barrier sub-layer BL 1 - 1  and the third barrier sub-layer BL 2 - 1  are in a same layer and formed in a single patterning process. Optionally, the second barrier sub-layer BL 1 - 2  and the fourth barrier sub-layer BL 2 - 2  are in a same layer and formed in a single patterning process. Optionally, the first barrier sub-layer BL 1 - 1  has a thickness less than a thickness of the third barrier sub-layer BL 2 - 1 . Optionally, the first barrier sub-layer BL 1 - 1 , the third barrier sub-layer BL 2 - 1  and the planarization layer PLN, are in a same layer and formed in a single patterning process. Optionally, the second barrier sub-layer BL 1 - 2 , the fourth barrier sub-layer BL 2 - 2 , and the pixel definition layer PDL are in a same layer and formed in a single patterning process. 
     In some embodiments, the display panel, in the region transitioning from the display region DA to the window region WR, further includes a spacer layer SL (as shown in  FIG.  3 F ) on a side of the pixel definition layer PDL away from the base substrate BS. Optionally, the first barrier layer BL 1  further includes another sub-layer in a same layer as the spacer layer. Optionally, the second barrier layer BL 2  further includes another sub-layer in a same layer as the spacer layer. 
     In some embodiments, the first barrier layer BL 1  only includes the second barrier sub-layer BL 1 - 2  but does not include the first barrier sub-layer BL 1 - 1 . 
     In some embodiments, the display panel further includes a plurality of internal isolation walls IWi in a region between the barrier structure DAM and the display region DA. A respective one of the plurality of internal isolation walls IWi includes a first internal wall sub-layer IWi- 1  and a second internal wall sub-layer IWi- 2 . Optionally, the first internal wall sub-layer IWi- 1  is a part of the second SD metal layer SD 2 . Optionally, the second internal wall sub-layer IWi- 2  is in a same layer as, and optionally formed in a single patterning process as, the cathode layer CD. Optionally, a total number of the plurality of internal isolation walls Iwi is in a range of 2 to 6, e.g., 2, 3, 4, 5, or 6. 
     In some embodiments, the display panel further includes a plurality of external isolation walls IWe in a region between the barrier structure DAM and the window region WR. A respective one of the plurality of external isolation walls IWe includes a first external wall sub-layer IWe- 1 , a second external wall sub-layer IWe- 2 , a third external wall sub-layer IWe- 3 , and a fourth external wall sub-layer IWe- 4 . Optionally, the first external wall sub-layer IWe- 1  is a part of the first gate metal layer GML. Optionally, the second external wall sub-layer IWe- 2  is a part of the second gate metal layer GM 2 . Optionally, the third external wall sub-layer IWe- 3  is a part of the second SD metal layer SD 2 . Optionally, the fourth external wall sub-layer IWe- 4  is in a same layer as, and optionally formed in a single patterning process as, the cathode layer CD. Optionally, a total number of the plurality of external isolation walls IWe is in a range of 2 to 8, e.g., 2, 3, 4, 5, 6, 7, or 8. 
     In some embodiments, the display panel further includes a plurality of first signal lines SL 1  and a plurality of second signal lines SL 2  in the region transitioning from the display region DA to the window region WR. The plurality of first signal lines SL 1  and the plurality of second signal lines SL 2  are on a side of the plurality of internal isolation walls IWi away from the barrier structure DAM. Optionally, the plurality of first signal lines SL 1  are in a same layer as the second gate metal layer GM 2 . Optionally, the plurality of second signal lines SL 2  are in a same layer as the second SD metal layer SD 2 . In some embodiments, the display panel, in the region transitioning from the display region DA to the window region WR, further includes a plurality of third signal lines in a same layer as the first gate metal layer GM 1 . 
       FIG.  3 G  illustrates a detailed structure in an inter-window region in a display panel in some embodiments according to the present disclosure. Referring to  FIG.  3 G , the display panel in the inter-window region in some embodiments includes a base substrate BS (e.g., a flexible base substrate); an insulating layer IN on the base substrate BS; an active layer ACT of a respective one of a plurality of thin film transistors TFT on a side of the insulating layer IN away from the base substrate BS; a first gate insulating layer GI 1  on a side of the active layer ACT away from the base substrate BS; a gate electrode G and a first capacitor electrode Ce 1  (both are parts of a first gate metal layer) on a side of the first gate insulating layer GI 1  away from the insulating layer IN; a second gate insulating layer GI 2  on a side of the gate electrode G and the first capacitor electrode Ce 1  away from the first gate insulating layer GI 1 ; a second capacitor electrode Ce 2  (a part of a second gate metal layer) on a side of the second gate insulating layer GI 2  away from the first gate insulating layer GI 1 ; an inter-layer dielectric layer ILD on a side of the second capacitor electrode Ce 2  away from the second gate insulating layer GI 2 ; a source electrode S and a drain electrode D (parts of a first SD metal layer) on a side of the inter-layer dielectric layer ILD away from the second gate insulating layer GI 2 ; a passivation layer PVX on a side of the source electrode S and the drain electrode D away from the inter-layer dielectric layer ILD; a first planarization layer PLN 1  on a side of the passivation layer PVX away from the inter-layer dielectric layer ILD; a second planarization layer PLN 2  on side of the first planarization layer PLN 1  away from the passivation layer PVX; a relay electrode RE (part of a second SD metal layer) on a side of the second planarization layer PLN 2  away from the first planarization layer PLN 1 ; a pixel definition layer PDL defining a dummy subpixel aperture and on a side of the second planarization layer PLN 2  away from the base substrate BS; and a dummy light emitting element DLE in the dummy subpixel aperture. The dummy light emitting element DLE includes a light emitting layer EL on a side of the second planarization layer PLN 2  away from the first planarization layer PLN 1 ; and a cathode layer CD on a side of the light emitting layer EL away from the second planarization layer PLN 2 . In the inter-window region, the dummy light emitting element DLE does not include an anode, and thus is not capable of emitting light. The display panel in the inter-window region further includes an encapsulating layer EN encapsulating the dummy light emitting element DLE, and on a side of the cathode layer CD away from the base substrate BS. The encapsulating layer EN in some embodiments includes a first inorganic encapsulating sub-layer CVD 1  on a side of the cathode layer CD away from the base substrate BS, an organic encapsulating sub-layer UP on a side of the first inorganic encapsulating sub-layer CVD 1  away from the base substrate BS, and a second inorganic encapsulating sub-layer CVD 2  on a side of the organic encapsulating sub-layer IP away from the first inorganic encapsulating sub-layer CVD 1 . The display panel in the inter-window region further includes a buffer layer BUF on a side of the encapsulating layer EN away from the base substrate BS; a plurality of second electrode bridges BR 2  on a side of the buffer layer BUF away from the encapsulating layer EN; a touch insulating layer TI on a side of the plurality of second electrode bridges BR 2  away from the buffer layer BUF; a plurality of first touch electrodes TE 1  on a side of the touch insulating layer TI away from the buffer layer BUF; and an overcoat layer OC on a side of the plurality of first touch electrodes TE 1  away from the touch insulating layer TI. Optionally, the display panel in the inter-window region does not include the passivation layer PVX, e.g., the inter-layer dielectric layer ILD is in direct contact with the first planarization layer PLN 1 . 
       FIG.  3 H  illustrates a detailed structure in a display region in a display panel in some embodiments according to the present disclosure. Referring to  FIG.  3 H , the display panel in the display region in some embodiments includes a base substrate BS (e.g., a flexible base substrate); an insulating layer IN on the base substrate BS; an active layer ACT of a respective one of a plurality of thin film transistors TFT on a side of the insulating layer IN away from the base substrate BS; a first gate insulating layer GI 1  on a side of the active layer ACT away from the base substrate BS; a gate electrode G and a first capacitor electrode Ce 1  (both are parts of a first gate metal layer) on a side of the first gate insulating layer GI 1  away from the insulating layer IN; a second gate insulating layer GI 2  on a side of the gate electrode G and the first capacitor electrode Ce 1  away from the first gate insulating layer GI 1 ; a second capacitor electrode Ce 2  (a part of a second gate metal layer) on a side of the second gate insulating layer GI 2  away from the first gate insulating layer GI 1 ; an inter-layer dielectric layer ILD on a side of the second capacitor electrode Ce 2  away from the second gate insulating layer GI 2 ; a source electrode S and a drain electrode D (parts of a first SD metal layer) on a side of the inter-layer dielectric layer ILD away from the second gate insulating layer GI 2 ; a passivation layer PVX on a side of the source electrode S and the drain electrode D away from the inter-layer dielectric layer ILD; a first planarization layer PLN 1  on a side of the passivation layer PVX away from the inter-layer dielectric layer ILD; a second planarization layer PLN 2  on side of the first planarization layer PLN 1  away from the passivation layer PVX; a relay electrode RE (part of a second SD metal layer) on a side of the second planarization layer PLN 2  away from the first planarization layer PLN 1 ; a pixel definition layer PDL defining a subpixel aperture and on a side of the second planarization layer PLN 2  away from the base substrate BS; and a light emitting element LE in the subpixel aperture. The light emitting element LE includes an anode AD on a side of the second planarization layer PLN 2  away from the first planarization layer PLN 1 ; a light emitting layer EL on a side of the anode AD away from the second planarization layer PLN 2 ; and a cathode layer CD on a side of the light emitting layer EL away from the anode AD. The display panel in the display region further includes an encapsulating layer EN encapsulating the dummy light emitting element DLE, and on a side of the cathode layer CD away from the base substrate BS. The encapsulating layer EN in some embodiments includes a first inorganic encapsulating sub-layer CVD 1  on a side of the cathode layer CD away from the base substrate BS, an organic encapsulating sub-layer IP on a side of the first inorganic encapsulating sub-layer CVD 1  away from the base substrate BS, and a second inorganic encapsulating sub-layer CVD 2  on a side of the organic encapsulating sub-layer IJP away from the first inorganic encapsulating sub-layer CVD. The display panel in the display region further includes a buffer layer BUF on a side of the encapsulating layer EN away from the base substrate BS; a plurality of second electrode bridges BR 2  on a side of the buffer layer BUF away from the encapsulating layer EN; a touch insulating layer TI on a side of the plurality of second electrode bridges BR 2  away from the buffer layer BUF; a plurality of first touch electrodes TE 1  on a side of the touch insulating layer TI away from the buffer layer BUF; and an overcoat layer OC on a side of the plurality of first touch electrodes TE 1  away from the touch insulating layer TI. Optionally, the display panel in the display region does not include the passivation layer PVX, e.g., the inter-layer dielectric layer ILD is in direct contact with the first planarization layer PLN 1 . 
       FIG.  3 I  illustrates a detailed structure in a display region in a display panel in some embodiments according to the present disclosure. Referring to  FIG.  3 I , the display panel in the display region in some embodiments includes a base substrate BS (e.g., a flexible base substrate); an insulating layer IN on the base substrate BS; an active layer ACT of a respective one of a plurality of thin film transistors TFT on a side of the insulating layer IN away from the base substrate BS; a first gate insulating layer GI 1  on a side of the active layer ACT away from the base substrate BS; a gate electrode G and a first capacitor electrode Ce 1  (both are parts of a first gate metal layer) on a side of the first gate insulating layer GI 1  away from the insulating layer IN; a second gate insulating layer GI 2  on a side of the gate electrode G and the first capacitor electrode Ce 1  away from the first gate insulating layer GI 1 ; a second capacitor electrode Ce 2  (a part of a second gate metal layer) on a side of the second gate insulating layer GI 2  away from the first gate insulating layer GI 1 ; an inter-layer dielectric layer ILD on a side of the second capacitor electrode Ce 2  away from the second gate insulating layer GI 2 ; a source electrode S and a drain electrode D on a side of the inter-layer dielectric layer ILD away from the second gate insulating layer GI 2 ; a planarization layer PLN on a side of the source electrode S and the drain electrode D away from the inter-layer dielectric layer ILD; a pixel definition layer PDL defining a subpixel aperture and on a side of the planarization layer PLN away from the base substrate BS; and a light emitting element LE in the subpixel aperture. The light emitting element LE includes an anode AD on a side of the planarization layer PLN away from the inter-layer dielectric layer ILD; a light emitting layer EL on a side of the anode AD away from the planarization layer PLN; and a cathode layer CD on a side of the light emitting layer EL away from the anode AD. The display panel in the display region further includes an encapsulating layer EN encapsulating the dummy light emitting element DLE, and on a side of the cathode layer CD away from the base substrate BS. The encapsulating layer EN in some embodiments includes a first inorganic encapsulating sub-layer CVD 1  on a side of the cathode layer CD away from the base substrate BS, an organic encapsulating sub-layer UP on a side of the first inorganic encapsulating sub-layer CVD 1  away from the base substrate BS, and a second inorganic encapsulating sub-layer CVD 2  on a side of the organic encapsulating sub-layer UP away from the first inorganic encapsulating sub-layer CVD 1 . The display panel in the display region further includes a buffer layer BUF on a side of the encapsulating layer EN away from the base substrate BS; a plurality of second electrode bridges BR 2  on a side of the buffer layer BUF away from the encapsulating layer EN; a touch insulating layer TI on a side of the plurality of second electrode bridges BR 2  away from the buffer layer BUF; a plurality of first touch electrodes TE 1  on a side of the touch insulating layer TI away from the buffer layer BUF; and an overcoat layer OC on a side of the plurality of first touch electrodes TE 1  away from the touch insulating layer TI. 
       FIG.  3 J  is a schematic diagram illustrating barrier structures defining window regions and inter-window region in a display panel in some embodiments according to the present disclosure. Referring to  FIG.  3 J , the display panel includes a first barrier structure DAM 1  and a second barrier structure DAM 2 . The first barrier structure DAM 1  completely surrounds the first hole H 1 , and a second barrier structure DAM 2  completely surrounds the second hole H 2 . The first region boundary RB 1  of the inter-window region IWR is a boundary adjacent to the first barrier structure DAM 1 , the second region boundary RB 2  of the inter-window region IWR is a boundary adjacent to the second barrier structure DAM 2 . 
     In some embodiments, the organic encapsulating sub-layer of the encapsulating layer has a first thickness in at least a sub-region of the transition region, and a second thickness in the display region, the first thickness smaller than the second thickness.  FIG.  4    is a cross-sectional view of a region of a display panel in some embodiments according to the present disclosure.  FIG.  5    is a cross-sectional view of a region of a display panel in some embodiments according to the present disclosure.  FIG.  4    may be representative of cross-sectional views along, for example, an A-A′ line in  FIG.  1   , a C-C′ line and a D-D′ line in  FIG.  2   .  FIG.  5    may be representative of cross-sectional views along, for example, a B-B′ line in  FIG.  1   , and an E-E′ line in  FIG.  2   . 
     Referring to  FIG.  4   ,  FIG.  1   , and  FIG.  2   , in some embodiments, the organic encapsulating sub-layer IP of the encapsulating layer has a second thickness t 2  in at least a sub-region of the transition region TR. Referring to  FIG.  5   ,  FIG.  1   , and  FIG.  2   , in some embodiments, the organic encapsulating sub-layer JP of the encapsulating layer has a first thickness t 1  in the display region DA. The first thickness t 1  is smaller than the second thickness t 2 . Optionally, the first thickness t 1  is smaller than the second thickness t 2  by at least 5%, e.g., by at least 10%, by at least 15%, by at least 20%, by at least 25%, by at least 30%, by at least 35%, by at least 40%, by at least 45%, by at least 50%, by at least 55%, by at least 60%, by at least 65%, by at least 70%, by at least 75%, or by at least 80%. Optionally, the first thickness t 1  is in a range of 2 μm to 9 μm, e.g., 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, or 8 μm to 9 μm. Optionally, the second thickness t 2  is in a range of 9 μm to 15 μm, e.g., 9 μm to 10 μm, 10 μm to 11 μm, 11 μm to 12 μm, 12 μm to 13 μm, 13 μm to 14 μm, or 14 μm to 15 μm. Optionally, the second thickness t 2  is in a range of 10 μm to 12 μm, e.g., 10.77 μm or 11 μm. 
     In some embodiments, the transition region TR includes at least a sub-region.  FIG.  6    illustrates a sub-region in a transition region in a display panel in some embodiments according to the present disclosure. Referring to  FIG.  6   , the sub-region SUBR is a sub-region in the transition region TR adjacent to the first window region WR 1 . Optionally, the transition region TR further includes a substantially flat region FR adjacent to the sub-region SUBR. Optionally, the organic encapsulating sub-layer IJP of the encapsulating layer has a first thickness t 1  in the substantially flat region FR and/or in the display region DA, and a second thickness t 2  in the sub-region SUBR. The first thickness t 1  is smaller than the second thickness t 2 . 
       FIG.  7    illustrates a sub-region in a transition region in a display panel in some embodiments according to the present disclosure. Referring to  FIG.  7   , in some embodiments, the transition region TR consists of the sub-region SUBR. Optionally, the organic encapsulating sub-layer IJP of the encapsulating layer has a first thickness t 1  in the display region DA, and a second thickness t 2  in the sub-region SUBR (or the transition region TR). The first thickness t 1  is smaller than the second thickness t 2 . 
       FIG.  8    illustrates a sub-region in a transition region in a display panel in some embodiments according to the present disclosure. Referring to  FIG.  8   , in a display panel having a first window region WR 1  and a second window region WR 2 , the transition region TR between the first window region WR 1  and the second window region WR 2  includes at least a sub-region SUBR. Optionally, the display panel further includes a substantially flat region FR between at least a portion of the sub-region SUBR and one of the first window region WR 1  and the second window region WR 2 . In one example, the sub-region SUBR includes a first portion SUBR 1  between the first window region WR 1  and the substantially flat region FR, and a second portion SUBR 2  between the second window region WR 2  and the substantially flat region FR. Optionally, the organic encapsulating sub-layer IP of the encapsulating layer has a first thickness t 1  in the substantially flat region FR and/or in the display region DA, and a second thickness t 2  in the sub-region SUBR. The first thickness t 1  is smaller than the second thickness t 2 . The transition region in  FIG.  8    may also refers to as an inter-window region in the context of display panels having two or more window regions. 
     As used herein, the term sub-region SUBR may be defined as a portion of the transition region TR in which a thickness of the organic encapsulating sub-layer IP gradually decreases along a direction from the sub-region SUBR of the transition region TR toward a window region (e.g., the first window region WR 1  or the second window region WR 2 ). For example, the thickness of the organic encapsulating sub-layer UP in the sub-region SUBR of the transition region TR gradually decreases along a direction from the sub-region SUBR of the transition region TR toward the first window region WR 1 , and the thickness of the organic encapsulating sub-layer IP in the sub-region SUBR of the transition region TR gradually decreases along a direction from the sub-region SUBR of the transition region TR toward the second window region WR 2 . In one example, the thickness of the organic encapsulating sub-layer IJP in the sub-region SUBR of the transition region TR gradually decreases along a direction from the substantially flat region FR of the transition region TR toward the first window region WR 1 , and the thickness of the organic encapsulating sub-layer UP in the substantially flat region FR of the transition region TR gradually decreases along a direction from the sub-region SUBR of the transition region TR toward the second window region WR 2 . As used herein, the term substantially flat region FR may be defined as a portion of the transition region TR in which a thickness of the organic encapsulating sub-layer UP is substantially the same, e.g., within an error of 5%, e.g., 4%, 3%, 2%, or 1%. 
       FIG.  3 F  depicts a substantially flat region FR and a sub-region SUBR in a transition region TR in some embodiments according to the present disclosure. Referring to  FIG.  3 F , a thickness of the organic encapsulating sub-layer IP in the substantially flat region FR remains substantially the same, whereas the thickness of the organic encapsulating sub-layer IP in the sub-region SUBR of the transition region TR gradually decreases along a direction from the sub-region SUBR of the transition region TR toward a window region WR (e.g., the first window region WR 1  or the second window region WR 2 ). As shown in  FIG.  3 F , layers in the sub-region SUBR and on top of the organic encapsulating sub-layer IP are conformally shaped in accordance with the organic encapsulating sub-layer IJP. For example, in the sub-region SUBR, the second inorganic encapsulating sub-layer CVD 2 , the buffer layer BUF, and the touch insulating layer TI are conformally shaped in accordance with the organic encapsulating sub-layer IJP. Because the organic encapsulating sub-layer UP in the sub-region SUBR has a large slope, the layers in the sub-region SUBR and on top of the organic encapsulating sub-layer IJP also have a large slope. 
     The inventors of the present disclosure discover that, due to the large slope in the sub-region SUBR, mesh electrodes are difficult to fabricate in the transition region TR. For example, when forming a photoresist in the transition region TR, it is difficult to maintain the photoresist material on the surface of the touch insulating layer TI in the sub-region SUBR of the transition region TR, due to the large slope in this sub-region. Because the photoresist material in the sub-region SUBR is insufficiently applied, when fabricated using a mask plate with openings having a uniform opening width, the mesh electrode lines have a critical dimension in the sub-region SUBR (where the photoresist material is insufficiently applied) smaller than a critical dimension in the display region DA.  FIG.  3 K  illustrates a correlation between decreases in values of the critical dimension of the mesh electrode lines and the thickness of the underlying organic encapsulating sub-layer in a portion of a display panel in which mesh electrode lines are fabricated using a mask plate with openings having a uniform opening width.  FIG.  3 L  illustrates a correlation between the values of critical dimensions of the mesh electrode lines and the thickness of the underlying organic encapsulating sub-layer in a portion of a display panel in which mesh electrode lines are fabricated using a mask plate with openings having a uniform opening width. Table 1 summarizes decreases in values of the critical dimensions and values of the critical dimensions of the mesh electrode lines at positions corresponding to various thicknesses of the underlying organic encapsulating sub-layer. The decreases in values of the critical dimension of the mesh electrode lines in  FIG.  3 K  and Table 1 are relative to a value of critical dimension of the mesh electrode lines in display region. 
     Table 1 summarizes decreases in values of the critical dimensions and values of the critical dimensions of the mesh electrode lines at positions corresponding to various thicknesses of the underlying organic encapsulating sub-layer. 
     
       
         
           
               
               
            
               
                   
                   
               
               
                   
                 Thicknesses of the underlying organic encapsulating sub-layer (μm) 
               
            
           
           
               
               
               
               
               
               
               
               
               
               
            
               
                   
                 15.48 
                 15.28 
                 14.89 
                 14.53 
                 14.08 
                 13.65 
                 12.35 
                 10.69 
                 9.04 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
               
               
               
               
               
            
               
                 Decreases in values 
                 0.09 
                 0.15 
                 0.28 
                 0.38 
                 0.47 
                 0.49 
                 0.51 
                 0.53 
                 0.55 
               
               
                 of the critical 
               
               
                 dimensions of the 
               
               
                 mesh electrode lines 
               
               
                 (μm) 
               
               
                 Values of the critical 
                 2.71 
                 2.65 
                 2.52 
                 2.42 
                 2.33 
                 2.31 
                 2.29 
                 2.27 
                 2.25 
               
               
                 dimensions of the 
               
               
                 mesh electrode lines 
               
               
                 (μm) 
               
               
                   
               
            
           
         
       
     
     The organic encapsulating sub-layer JP in the portion of the display panel has a large slope, corresponding to the sub-region SUBR. Data points in  FIG.  3 L  and Table 1 represent critical dimensions of the mesh electrode lines in various positions in the sub-region SUBR. As shown in  FIG.  3 L , the critical dimension of the mesh electrode lines increases as the thickness of the organic encapsulating sub-layer IP increases, until the thickness of the organic encapsulating sub-layer IP stabilizes. Because the critical dimensions of the mesh electrode lines in the sub-region SUBR is relatively small, the mesh electrode lines formed in this sub-region is prone to line break due to overexposure in this sub-region. The inventors of the present disclosure discover that, surprisingly and unexpectedly, the line break issue may be obviated by adopting an intricate mesh electrode structure described in the present disclosure. 
     Based on  FIG.  3 K , the correlation between decreases in values of the critical dimension of the mesh electrode lines and the thickness of the underlying organic encapsulating sub-layer may be expressed as Equation (1): 
         D=− 0.0016 x   4 +0.0717 x   3 −1.1873 x   2 +8.659 x− 22.908  (1);
 
     wherein D stands for the decreases in values of the critical dimension of the mesh electrode lines; and x stands for the thickness of the underlying organic encapsulating sub-layer. 
     Based on  FIG.  3 L , the correlation between values of the critical dimension of the mesh electrode lines and the thickness of the underlying organic encapsulating sub-layer may be expressed as Equation (2): 
         V= 0.0016 x   4 −0.0717 x   3 +1.1873 x   2 −8.659 x+ 25.708  (2);
 
     wherein V stands for the values of the critical dimension of the mesh electrode lines; and x stands for the thickness of the underlying organic encapsulating sub-layer. 
     In some embodiments, mesh electrode lines of the mesh electrodes have a first line width in at least the sub-region of the transition region, and a second line width in the display region, the first line width being greater than the second line width.  FIG.  9    illustrates an inter-region boundary of an inter-window region in some embodiments according to the present disclosure. Referring to  FIG.  9   , the transition region in some embodiments is equivalent to an inter-window region IWR between a first window region WR 1  and a second window region WR 2 . An inter-region boundary in some embodiments includes a first inter-region boundary BL 1  between one side of the inter-window region IWR and the display region DA, and a second inter-region boundary BL 2  between another side of the inter-window region IWR and the display region DA. 
       FIG.  10 A  illustrates the structure of mesh electrodes lines adjacent to a first inter-region boundary of an inter-window region in some embodiments according to the present disclosure.  FIG.  10 B  illustrates the structure of mesh electrodes lines adjacent to a second inter-region boundary of an inter-window region in some embodiments according to the present disclosure. Referring to  FIG.  10 A  and  FIG.  10 B , mesh electrode lines of the mesh electrodes have a first line width w 1  in at least the sub-region of the inter-window region IWR, and a second line width w 2  in the display region DA, the first line width w 1  being greater than the second line width w 2 . 
     Optionally, the first line width w 1  is greater than the second line width w 2  by at least 5%, e.g., by at least 10%, by at least 15%, by at least 20%, by at least 25%, by at least 30%, by at least 35%, by at least 40%, by at least 45%, or by at least 50%. Optionally, the first line width w 1  is in a range of 2 μm to 10 μm, e.g., 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, or 9 μm to 10 μm. Optionally, the first line width w 1  is 3.5 μm. Optionally, the first line width w 1  is 4.0 μm. Optionally, the second line width w 2  is in a range of 1 μm to 5 μm, e.g., 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, or 4 μm to 5 μm. Optionally, the second line width w 2  is 3 μm. 
     Referring to  FIG.  10 A  and  FIG.  10 B , a respective boundary (e.g., the first inter-region boundary BL 1  or the second inter-region boundary BL 2 ) between the inter-window region IWR and the display region DA includes transition points TP at which line widths of the mesh electrode lines transition from the first line width w 1  to the second line width w 2 . In one example, the respective boundary is an imaginary line connecting the transition points TP. 
     In some embodiments, the mesh electrode lines of the mesh electrodes have the first line width w 1  in at least the sub-region of the transition region TR (e.g., the inter-window region IWR). Optionally, the mesh electrode lines of the mesh electrodes have the first line width w 1  throughout the transition region TR (e.g., the inter-window region IWR). 
     In some embodiments, the first line width w 1  of the mesh electrode lines of the mesh electrodes is compensated at least in part based on a thickness of the underlying organic encapsulating sub-layer in at least the sub-region of the transition region TR (e.g., the inter-window region IWR). The compensation value relative to the second line width w 2  in some embodiments may be correlated to the thickness of the underlying organic encapsulating sub-layer in at least the sub-region of the transition region TR (e.g., the inter-window region IWR).  FIG.  11    illustrates a correlation between compensation values of critical dimensions of the mesh electrode lines and the thickness of the underlying organic encapsulating sub-layer in a portion of a display panel in some embodiments according to the present disclosure. Referring to  FIG.  11   , the compensation value of critical dimension of the mesh electrode line in at least the sub-region of the transition region is a difference between the first line width w 1  at a point in at least the sub-region of the transition region and the second line width w 2  in the display region. 
     Based on  FIG.  11   , the compensation value of critical dimension of the mesh electrode line in at least the sub-region of the transition region may be expressed as Equation (3): 
       Δ w =( w 1− w 2)=−0.0016 x   4 +0.073 x   3 −1.2112 x   2 +8.8493 x− 23.268  (3);
 
     wherein Δw stands for the compensation value of critical dimension of the mesh electrode line; w 1  stands for the first line width of the mesh electrode line at a point in at least the sub-region of the transition region; w 2  stands for the second line width of the mesh electrode line in the display region; and x stands for the thickness of the underlying organic encapsulating sub-layer. As shown in  FIG.  11   , in some embodiments, the compensation value is a variable value depending on the thickness of the underlying organic encapsulating sub-layer. In one example, the second line width w 2  is 3 μm, and the first line width w 1  is (3+Δw) μm. 
     In some embodiments, the compensation value of critical dimension of the mesh electrode line in at least the sub-region of the transition region is a constant value. In one example, the compensation value is 0.5 μm. In another example, the compensation value is 1.0 μm. In another example, the compensation value is a constant value in a range of 0.29 μm to 0.75 μm. In another example, the compensation value is an average value of the compensation values corresponding to data points in  FIG.  11   . 
       FIG.  12 A  is a zoom-in view of two adjacent touch electrodes in an inter-window region of a display panel in some embodiments according to the present disclosure. Referring to  FIG.  12 A , in the inter-window region, a first respective one of the plurality of first touch electrodes TE 1  and a second respective one of the plurality of second touch electrodes TE 2  directly adjacent to each other are spaced apart by a first gap G 1  having a first gap width d 1 . 
       FIG.  12 B  is a zoom-in view of two adjacent touch electrodes in a display region of a display panel in some embodiments according to the present disclosure. In the display region, a third respective one of the plurality of first touch electrodes TE 1  and a fourth respective one of the plurality of second touch electrodes TE 2  directly adjacent to each other are spaced apart by a second gap G 2  having a second gap width d 2 . 
     Optionally, the first gap width d 1  is greater than the second gap width d 2 . Optionally, the first gap width d 1  is greater than the second gap width d 2  by at least 20%, e.g., by at least 30%, by at least 40%, by at least 50%, by at least 60%, by at least 70%, by at least 80%, by at least 90%, by at least 100%, by at least 110%, by at least 120%, by at least 130%, by at least 140%, by at least 150%, by at least 160%, by at least 170%, by at least 180%, by at least 190%, by at least 200%, by at least 225%, by at least 250%, or by at least 300%. Optionally, the first gap width d 1  is in a range of 5 μm to 50 μm, e.g., 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm, or 45 μm to 50 μm. Optionally, the second gap width d 2  is in a range of 1 μm to 10 μm, e.g., 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, or 9 μm to 10 μm. In one example, the first gap width d 1  is approximately 10 μm, and the second gap width d 2  is approximately 5.2 μm. 
     In some embodiments, the display panel further includes a plurality of fill patterns in a same layer as the plurality of first touch electrodes or as the plurality of second touch electrodes. The plurality of fill patterns are insulated from the plurality of first touch electrodes and the plurality of second touch electrodes.  FIG.  13 A  is a zoom-in view of multiple touch electrodes in an inter-window region of a display panel in some embodiments according to the present disclosure.  FIG.  13 B  is a zoom-in view of multiple touch electrodes in a display region of a display panel in some embodiments according to the present disclosure. Referring to  FIG.  13 A  and  FIG.  13 B , in some embodiments, the plurality of fill patterns DE are limited in the display region DA, and absent in the inter-window region IWR, the first window region WR 1 , and the second window region WR 2 . 
     As used herein, the term “same layer” refers to the relationship between the layers simultaneously formed in the same step. In one example, the plurality of fill patterns DE and the plurality of first touch electrodes TE 1  are in a same layer when they are formed as a result of one or more steps of a same patterning process performed in a material deposited in a same deposition process. In another example, the plurality of fill patterns DE and the plurality of first touch electrodes TE 1  can be formed in a same layer by simultaneously performing the step of forming the plurality of fill patterns DE and the step of forming the plurality of first touch electrodes TEL. The term “same layer” does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same. 
       FIG.  14    is a zoom-in view of a region surrounding an inter-window region of a display panel in some embodiments according to the present disclosure. In some embodiments, the plurality of first touch electrodes and the plurality of second touch electrodes are mesh electrodes comprising mesh electrode lines. For example, the plurality of first touch electrodes have a mesh pattern, e.g., a net-shaped pattern, and the plurality of second touch electrodes have a mesh pattern. The mesh electrode lines typically have a line width in a range of 1 μm to 50 μm, e.g., 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm, or 45 μm to 50 μm. 
       FIG.  15    is a zoom-in view of a first zoom-in region ZR 1  in  FIG.  14   .  FIG.  16    is a zoom-in view of a second zoom-in region ZR 2  in  FIG.  14   . Referring to  FIG.  15    and  FIG.  16   , in some embodiments, the plurality of first touch electrodes TE 1  are a plurality of first mesh electrodes, each of which comprising a plurality of first mesh electrode lines ML 1 , the plurality of second touch electrodes TE 2  are a plurality of second mesh electrodes, each of which comprising a plurality of second mesh electrode lines ML 2 . The first zoom-in region ZR 1  is in the inter-window region IWR in  FIG.  14   . The second zoom-in region ZR 2  is in the display region DA in  FIG.  14   . A first respective one of the plurality of first touch electrodes TE 1  and a second respective one of the plurality of second touch electrodes TE 2  directly adjacent to each other are spaced apart by a first gap G 1  having a first gap width d 1 . A third respective one of the plurality of first touch electrodes TE 1  and a fourth respective one of the plurality of second touch electrodes TE 2  directly adjacent to each other are spaced apart by a second gap G 2  having a second gap width d 2 . The first gap width d 1  is greater than the second gap width d 2 . The first gap G 1  has a first boundary B 1  formed by virtually connecting outer edges of multiple first mesh electrode lines of the first respective one of the plurality of first touch electrodes TE 1 , and a second boundary B 2  formed by virtually connecting outer edges of multiple second mesh electrode lines of the second respective one of the plurality of second touch electrodes TE 2 . The second gap G 2  has a third boundary B 3  formed by virtually connecting outer edges of multiple first mesh electrode lines of the third respective one of the plurality of first touch electrodes TE 1 , and a fourth boundary B 4  formed by virtually connecting outer edges of multiple second mesh electrode lines of the fourth respective one of the plurality of second touch electrodes TE 2 . Optionally, the first gap width d 1  is a first shortest distance between the first boundary B 1  and the second boundary B 2 . Optionally, the second gap width d 2  is a second shortest distance between the third boundary B 3  and the fourth boundary B 4 . 
     In some embodiments, as shown in  FIG.  15    and  FIG.  16   , a respective one of the plurality of first mesh electrode lines ML 1  in the inter-window region IWR has a first line width w 1 , a respective one of the plurality of second mesh electrode lines ML 2  in the display region DA has a second line width w 2 . Optionally, the first line width w 1  is greater than the second line width w 2 . Optionally, the first line width w 1  is greater than the second line width w 2  by at least 5%, e.g., by at least 10%, by at least 15%, by at least 20%, by at least 25%, by at least 30%, by at least 35%, by at least 40%, by at least 45%, or by at least 50%. Optionally, the first line width w 1  is in a range of 2 μm to 10 μm, e.g., 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, or 9 μm to 10 μm. Optionally, the second line width w 2  is in a range of 1 μm to 5 μm, e.g., 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, or 4 μm to 5 μm. In one example, the first line width w 1  is approximately 4 μm, and the second line width w 2  is approximately 3 μm. 
       FIG.  17    is a zoom-in view of a third zoom-in region ZR 3  in  FIG.  14   . The third zoom-in region ZR 3  crosses over the inter-window region IWR to the display region DA in  FIG.  14   . Referring to  FIG.  17   , an inter-region boundary BL between the inter-window region IWR and the display region DA is defined by an imaginary line through which line widths of the mesh electrode lines transition from the first line width w 1  to the second line width w 2 . At least a portion of the inter-region boundary BL in  FIG.  17    is an undulating virtual line along a continuous edge of a respective one of the plurality of second mesh electrode lines ML 2 . 
     In some embodiments, the display panel further includes a plurality of blanking mesh breaks. As used herein, the term “blanking mesh break” refers to a break in a mesh electrode line in an individual mesh electrode block (i.e., not a gap separating adjacent mesh electrode blocks) for achieving an excellent blanking effect in the display panel. Mesh electrode lines are otherwise inter-connected elsewhere in the individual mesh electrode block except for positions having the plurality of blanking mesh breaks.  FIG.  18    is a zoom-in view of a fourth zoom-in region ZR 4  in  FIG.  14   .  FIG.  19    is a zoom-in view of a fifth zoom-in region ZR 5  in  FIG.  14   . Referring to  FIG.  18    and  FIG.  19   , in some embodiments, the plurality of blanking mesh breaks BMR are limited in mesh electrode blocks in the display region DA, and absent in the inter-window region IWR, the first window region WR 1 , and the second window region WR 2 . 
     Optionally, both the plurality of fill patterns DE and the plurality of blanking mesh breaks BMR are limited in mesh electrode blocks in the display region DA; and both the plurality of fill patterns DE and the plurality of blanking mesh breaks BMR are absent in the inter-window region IWR, the first window region WR 1 , and the second window region WR 2 . 
     Optionally, the plurality of blanking mesh breaks BMR are randomly distributed in the display region DA. The plurality of blanking mesh breaks BMR themselves do not form a pattern so that an excellent blanking effect can be achieved. For example, the plurality of blanking mesh breaks BMR do not have a repeating pattern, and do not have rotational or translational symmetry between mesh electrode blocks. 
       FIG.  20    illustrates a first gap in an inter-window region in a display panel in some embodiments according to the present disclosure. Referring to  FIG.  20   , in some embodiments, the first gap (denoted as “G 1 ” in  FIG.  15   ) includes a plurality of first portions G 1 - 1 , each of which oriented along a first orientation OR 1 ; and a plurality of second portions G 1 - 2 , each of which oriented along a second orientation OR 2 . Optionally, a respective one of the plurality of first portions G 1 - 1  has a first portion gap width d 1 - 1 , and a respective one of the plurality of second portions G 1 - 2  has a second portion gap width d 1 - 2 . The first portion gap width d 1 - 1  and the second portion gap width d 1 - 2  may be the same (as it is the case in  FIG.  15   ). Optionally, the first portion gap width d 1 - 1  and the second portion gap width d 1 - 2  are different from each other. Optionally, the first portion gap width d 1 - 4  is greater than the second portion gap width d 1 - 2 . Optionally, the first portion gap width d 1 - 1  is in a range of 5 μm to 50 μm, e.g., 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm, or 45 μm to 50 μm. Optionally, the second portion gap width d 1 - 2  is in a range of 5 μm to 50 μm, e.g., 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm, or 45 μm to 50 μm. 
       FIG.  21    illustrates a second gap in a display region in a display panel in some embodiments according to the present disclosure. Referring to  FIG.  21   , in some embodiments, the second gap (denoted as “G 2 ” in  FIG.  16   ) includes a plurality of third portions G 2 - 1 , each of which oriented along the first orientation OR 1 ; and a plurality of fourth portions G 2 - 2 , each of which oriented along the second orientation OR 2 . Optionally, a respective one of the plurality of third portions G 2 - 1  has a third portion gap width d 2 - 1 , and a respective one of the plurality of fourth portions G 2 - 2  has a fourth portion gap width d 2 - 2 . The third portion gap width d 2 - 1  and the fourth portion gap width d 2 - 2  may be the same (as it is the case in  FIG.  15   ). Optionally, the third portion gap width d 2 - 1  and the fourth portion gap width d 2 - 2  are different from each other. Optionally, the third portion gap width d 2 - 1  is greater than the fourth portion gap width d 2 - 2 . Optionally, the third portion gap width d 2 - 1  is in a range of 1 μm to 10 μm, e.g., 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, or 9 μm to 10 μm. Optionally, the fourth portion gap width d 2 - 2  is in a range of 1 μm to 10 μm, e.g., 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, or 9 μm to 10 μm. 
     In some embodiments, portion gap widths of portion gaps of the first gap along each orientation are greater than portion gap widths of portion gaps of the second gap along a same respective orientation. Optionally, a portion gap width of a portion gap of the first gap along a first orientation is greater than a portion gap width of a portion gap of the second gap along the first orientation, and a portion gap width of a portion gap of the first gap along a second orientation is greater than a portion gap width of a portion gap of the second gap along the second orientation. In one example, and referring to  FIG.  20    and  FIG.  21   , the first portion gap width d 1 - 1  is greater than the third portion gap width d 2 - 1 , and the second portion gap width d 1 - 2  is greater than the fourth portion gap width d 2 - 2 . In another example, the first portion gap width d 1 - 1  is greater than the third portion gap width d 2 - 1  and greater than the fourth portion gap width d 2 - 2 ; and the second portion gap width d 1 - 2  is greater than the third portion gap width d 2 - 1  and greater than the fourth portion gap width d 2 - 2 . 
     In some embodiments, the term “the first gap width is greater than the second gap width” means that a smallest portion gap width (e.g., the second portion gap width d 1 - 2 ) in the first gap is greater than a smallest portion gap width (e.g., the fourth portion gap width d 2 - 2 ) in the second gap G 2 . Optionally, the smallest portion gap width in the first gap is greater than the smallest portion gap width in the second gap by at least 20%, e.g., by at least 30%, by at least 40%, by at least 50%, by at least 60%, by at least 70%, by at least 80%, by at least 90%, by at least 100%, by at least 110%, by at least 120%, by at least 130%, by at least 140%, by at least 150%, by at least 160%, by at least 170%, by at least 180%, by at least 190%, by at least 200%, by at least 225%, by at least 250%, or by at least 300%. 
     In some embodiments, the term “the first gap width is greater than the second gap width” means that a smallest portion gap width (e.g., the second portion gap width d 1 - 2 ) in the first gap is greater than a smallest portion gap width (e.g., the fourth portion gap width d 2 - 2 ) in the second gap G 2 ; and that a largest portion gap width (e.g., the first portion gap width d 1 - 1 ) in the first gap is greater than a largest portion gap width (e.g., the third portion gap width d 2 - 1 ) in the second gap G 2 . Optionally, the smallest portion gap width in the first gap is greater than the smallest portion gap width in the second gap by at least 20%, e.g., by at least 30%, by at least 40%, by at least 50%, by at least 60%, by at least 70%, by at least 80%, by at least 90%, by at least 100%, by at least 110%, by at least 120%, by at least 130%, by at least 140%, by at least 150%, by at least 160%, by at least 170%, by at least 180%, by at least 190%, by at least 200%, by at least 225%, by at least 250%, or by at least 300%; and the largest portion gap width in the first gap is greater than the largest portion gap width in the second gap by at least 20%, e.g., by at least 30%, by at least 40%, by at least 50%, by at least 60%, by at least 70%, by at least 80%, by at least 90%, by at least 100%, by at least 110%, by at least 120%, by at least 130%, by at least 140%, by at least 150%, by at least 160%, by at least 170%, by at least 180%, by at least 190%, by at least 200%, by at least 225%, by at least 250%, or by at least 300%. 
     In some embodiments, the term “the first gap width is greater than the second gap width” means that a smallest portion gap width (e.g., the second portion gap width d 1 - 2 ) in the first gap is greater than any portion gap width (e.g., the third portion gap width d 2 - 1  or the fourth portion gap width d 2 - 2 ) in the second gap G 2 . Optionally, the smallest portion gap width in the first gap is greater than any portion gap width in the second gap by at least 20%, e.g., by at least 30%, by at least 40%, by at least 50%, by at least 60%, by at least 70%, by at least 80%, by at least 90°/c, by at least 100%, by at least 110%, by at least 120%, by at least 130%, by at least 140%, by at least 150%, by at least 160%, by at least 170%, by at least 180%, by at least 190%, by at least 200%, by at least 225%, by at least 250%, or by at least 300%. 
     In some embodiments, the term “the first gap width is greater than the second gap width” means that an average portion gap width (e.g., an average of the first portion gap width d 1 - 1  and the second portion gap width d 1 - 2 ) in the first gap is greater than an average gap width (e.g., an average of the third portion gap width d 2 - 1  and the fourth portion gap width d 2 - 2 ) in the second gap G 2 . Optionally, the average portion gap width in the first gap is greater than the average portion gap width in the second gap by at least 20%, e.g., by at least 30%, by at least 40%, by at least 50%, by at least 60%, by at least 70%, by at least 80%, by at least 90%, by at least 100%, by at least 110%, by at least 120%, by at least 130%, by at least 140%, by at least 150%, by at least 160%, by at least 170%, by at least 180%, by at least 190%, by at least 200%, by at least 225%, by at least 250%, or by at least 300%. 
       FIG.  22    is a zoom-in view of a region surrounding a boundary between an inter-window region and a display region of a display panel in some embodiments according to the present disclosure. Referring to  FIG.  22   , a portion of the inter-region boundary BL in  FIG.  17    is a straight virtual line. 
     Referring to  FIG.  17    and  FIG.  22   , in some embodiments, the mesh electrode lines includes an inter-region mesh electrode line IML extending from the inter-window region IWR into the display region DA. The inter-region mesh electrode line IML includes a first sub-line SL 1  in the inter-window region IWR and a second sub-line SL 2  in the display region DA, the first sub-line SL 1  directly connected with the second sub-line SL 2 . Optionally, the first sub-line SL 1  has a first sub-line width sw 1 . Optionally, the second sub-line has a second sub-line width sw 2 . Optionally, the first sub-line width sw 1  is greater than the second sub-line width sw 2 . Optionally, the first sub-line width sw 1  is the same as the first line width w 1 , and the second sub-line width sw 2  is the same as the second line width w 2 . Optionally, the first sub-line width sw 1  is greater than the second sub-line width sw 2  by at least 5%, e.g., by at least 10%, by at least 15%, by at least 20%, by at least 25%, by at least 30%, by at least 35%, by at least 40%, by at least 45%, or by at least 50%. Optionally, the first sub-line width sw 1  is in a range of 2 μm to 10 μm, e.g., 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, or 9 μm to 10 μm. Optionally, the second sub-line width sw 2  is in a range of 1 μm to 5 μm, e.g., 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, or 4 μm to 5 μm. In one example, the first sub-line width sw 1  is approximately 4 μm, and the second sub-line width sw 2  is approximately 3 μm. 
     Referring to  FIG.  17    and  FIG.  22   , in some embodiments, a fifth respective one of the plurality of first touch electrodes TE 1  and a sixth respective one of the plurality of second touch electrodes TE 2  directly adjacent to each other are spaced apart by an inter-region gap IG extending from the inter-window region IWR into the display region DA. Optionally, the inter-region gap IG includes a first sub-gap SG 1  in the inter-window region IWR and a second sub-gap SG 2  in the display region DA, the first sub-gap SG 1  directly connected with the second sub-gap SG 2 . Optionally, the first sub-gap SG 1  has a first sub-gap width sd 1 . Optionally, the second sub-gap SG 2  has a second sub-gap width sd 2 . Optionally, the first sub-gap width sd 1  is greater than the second sub-gap width sd 2 . Optionally, the first sub-gap width sd 1  is the same as the first gap width d 1 , and the second sub-gap width sd 2  is the same as the second gap width d 2 . Optionally, the first sub-gap width sd 1  is greater than the second sub-gap width sd 2  by at least 20%, e.g., by at least 30%, by at least 40%, by at least 50%, by at least 60%, by at least 70%, by at least 80%, by at least 90%, by at least 100%, by at least 110%, by at least 120%, by at least 130%, by at least 140%, by at least 150%, by at least 160%, by at least 170%, by at least 180%, by at least 190%, by at least 200%, by at least 225%, by at least 250%, or by at least 300%. Optionally, the first sub-gap width sd 1  is in a range of 5 μm to 50 μm, e.g., 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm, or 45 μm to 50 μm. Optionally, the second sub-gap width sd 2  is in a range of 1 μm to 10 μm, e.g., 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, or 9 μm to 10 μm. In one example, the first sub-gap width sd 1  is approximately 10 μm, and the second sub-gap width sd 2  is approximately 5.2 μm. Optionally, multiple mesh electrode lines directly adjacent to the first sub-gap SG 1  have a line width greater than multiple mesh electrode lines directly adjacent to the second sub-gap SG 2 . 
     Referring to  FIG.  22   , in some embodiments, the mesh electrode lines includes an inter-region mesh electrode line IML directly adjacent to the inter-region gap IG extending from the inter-window region IWR into the display region DA, and the inter-region mesh electrode line IML also extends from the inter-window region IWR into the display region DA. Optionally, the inter-region gap IG includes a first sub-gap SG 1  in the inter-window region IWR and a second sub-gap SG 2  in the display region DA, the first sub-gap SG 1  directly connected with the second sub-gap SG 2 . Optionally, the first sub-gap has a first sub-gap width sd 1 . Optionally, the second sub-gap has a second sub-gap width sd 2 . Optionally, the first sub-gap width sd 1  is greater than the second sub-gap width sd 2 . Optionally, the first sub-gap width sd 1  is the same as the first gap width d 1 , and the second sub-gap width sd 2  is the same as the second gap width d 2 . Optionally, at least a first portion of a boundary of the first sub-gap SG 1  in the inter-window region IWR is formed by virtually connecting outer edges of the first sub-line SL 1  of the inter-region mesh electrode line IML, and at least a second portion of a boundary of the second sub-gap SG 2  in the display region DA is formed by virtually connecting outer edges of the second sub-line SL 2  of the inter-region mesh electrode line IML. Optionally, the first portion and the second portion are directly connected. 
       FIG.  23 A  is a partial cross-sectional view of a display panel in an inter-window region in some embodiments according to the present disclosure.  FIG.  23 B  is a partial cross-sectional view of a display panel in a display region in some embodiments according to the present disclosure. Referring to  FIG.  23 A  and  FIG.  23 B , in some embodiments, the display panel includes a touch insulating layer TI underneath (e.g., directly underneath) the touch electrode layer and in contact with the touch electrode layer (e.g., the plurality of first touch electrodes TE 1 ). Optionally, the touch insulating layer TI has a first contacting surface CS 1  in contact with the touch electrode layer in the inter-window region IWR and a second contacting surface CS 2  in contact with the touch electrode layer in the display region DA. Optionally, the first contacting surface CS 1  has a first degree of unevenness. Optionally, the second contacting surface CS 2  has a second degree of unevenness. Optionally, the first degree of unevenness is greater than the second degree of unevenness. The higher degree of unevenness in the inter-window region IWR is due to the higher degree of unevenness in the encapsulating layer EN underneath the touch electrode layer, the touch insulating layer TI, and the buffer layer BUF. It is discovered in the present disclosure that it is more difficult to form an even surface in the inter-window region IWR as compared to in the display region DA when forming the encapsulating layer EN. As a result, the first contacting surface CS 1  has a higher degree of unevenness than the second contacting surface CS 2 . The touch electrode layer in the inter-window region IWR are prone to line break or short. Having the mesh electrode blocks spacing apart by a wider gap in the inter-window region IWR and having a greater line width in the inter-window region IWR greatly help preventing these issues. 
     In another aspect, the present disclosure provides a display apparatus including a display panel described herein or fabricated by a method described herein, and one or more integrated circuits connected to the display panel. Examples of appropriate display apparatuses include, but are not limited to, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital album, a GPS, etc. Optionally, the display apparatus is an organic light emitting diode display apparatus. Optionally, the display apparatus is a liquid crystal display apparatus. 
     In another aspect, the present disclosure provides a method of fabricating a display panel. In some embodiments, the method includes forming thin film transistors and display elements on a base substrate; forming an encapsulating layer encapsulating the display elements; and forming a touch electrode layer comprising mesh electrodes on a side of the encapsulating layer away from the base substrate. Optionally, in a transition region adjacent to the display region, at least the touch electrode layer and the encapsulating layer are at least partially present. Optionally, in a first window region adjacent to the transition region, at least the display elements, the touch electrode layer, and the encapsulating layer are absent. Optionally, forming the encapsulating layer includes forming at least an organic encapsulating sub-layer having a first thickness in at least a sub-region of the transition region, and a second thickness in the display region, the first thickness being smaller than the second thickness. Optionally, mesh electrode lines of the mesh electrodes are formed to have a first line width in at least the sub-region of the transition region, and a second line width in the display region, the first line width being greater than the second line width. 
     The foregoing description of the embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. Therefore, the term “the invention”, “the present invention” or the like does not necessarily limit the claim scope to a specific embodiment, and the reference to exemplary embodiments of the invention does not imply a limitation on the invention, and no such limitation is to be inferred. The invention is limited only by the spirit and scope of the appended claims. Moreover, these claims may refer to use “first”, “second”, etc. following with noun or element. Such terms should be understood as a nomenclature and should not be construed as giving the limitation on the number of the elements modified by such nomenclature unless specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.