Patent Publication Number: US-9905181-B2

Title: Array substrate and scan driving circuit thereon

Description:
FIELD OF THE INVENTION 
     The present disclosure relates to the technical field of displays, and in particular it relates to an array substrate and scan driving circuit thereof. 
     BACKGROUND OF THE INVENTION 
     Recently, due to the advantages of high contrast, fast response time, high transmittance, and so on, vertical alignment (VA) liquid crystal technology has been widely used. 
     Typically, each pixel of the VA liquid crystal is divided into two regions, wherein one region (main-region) is the same with an ordinary pixel, and another region (sub-region) generates a voltage difference to the first region through circuit designs, the wide viewing angle performance of the VA liquid crystal is thereby improved. A pixel with such design is typically adopting two scan lines, wherein a first scan line charges normally to the two regions, respectively, a second scan line controls a TFT for charge sharing in the sub-region, such that the voltage difference between two pixel electrodes in the two regions is obtained. 
     Since the two scan lines occupied a partial space, and reduce the aperture ratio, therefore in the subsequent improvement, the second scan line is merged into the scan line of a next stage pixel, so as to improve the aperture ratio. However, under this design, the two scan lines cannot be opened at the same time, otherwise the voltage difference between the main-region and the sub-region cannot be generated, hence the purpose of improving the viewing angle cannot be achieved. In view of the GOA circuit designs to the existing large-size panel, due to the electrical load and other factors, the circuit is generally adopts multi-clock signals design such as fourth clock signals, sixth clock signals, or even eighth clock signals, such that the waveforms of current stage scanning signals between two adjacent stages are overlapped, as shown in  FIG. 1 , which means that the scan lines of two adjacent stages will both turn on at the same time, it is hardly to meet the driving demand for the VA liquid crystal with wide viewing angle as mentioned above. 
     SUMMARY OF THE INVENTION 
     In order to solve the above problems, the present disclosure provides a scan driving circuit on an array substrate. The scan driving circuit on an array substrate comprises: a multi-stage cascade circuit, each stage of the cascade circuit inputs a clock signal corresponding to a current stage, and outputs a current stage scanning signal and a current stage cascade signal, different stages of the cascade circuit are connected with each other via the cascade signal; a plurality of cancellation circuits, each cancellation circuit is corresponding to one stage of the cascade circuit, the cancellation circuit corresponding to a current stage cascade circuit inputs a clock signal corresponding to an adjacent stage cascade circuit, and outputs a cancellation signal, the cancellation signal offsets a part of the current stage scanning signal outputted from the current stage cascade circuit, so that the scanning signals outputted from two adjacent stages of the cascade circuit are not overlapped; a total group of the clock signals are m, wherein m is an even number, an average duty cycle of each clock signal is 50%, the current stage cascade circuit is a n-th stage, wherein n is a positive integer, the current stage cascade circuit is connected to a cascade signal ST (n−m/2) outputted from a (n−m/2) stage cascade circuit, and a cascade signal ST (n+m/2) outputted from a (n+m/2) stage cascade circuit; the cancellation circuit comprises a first transistor, a control terminal of the first transistor is connected a clock signal corresponding to the adjacent stage cascade circuit, a first connecting terminal of the first transistor is connected to a low constant potential Vss, a second connecting terminal of the first transistor is connected to the current stage scanning signal; the cascade circuit comprises an output transistor, a control terminal of the output transistor is connected to a control node, a first connecting terminal of the output transistor is connected to the clock signal corresponding to the current stage, a second connecting terminal of the output transistor is connected to the current stage scanning signal; configuring an on-resistance ratio of the output transistor and the first transistor, so that a potential of the current stage scanning signal cannot turn on a TFT that is connected to the current stage scanning signal and used for charge sharing, in a pulse duration when the clock signals corresponding to the adjacent stage and the current stage are overlapped. 
     In order to solve one of the above problems, the present disclosure provides a scan driving circuit on an array substrate. The scan driving circuit on the array substrate comprises: a multi-stage cascade circuit, each stage of the cascade circuit inputs a clock signal corresponding to a current stage, and outputs a current stage scanning signal and a current stage cascade signal, different stages of the cascade circuit are connected with each other via the cascade signal; a plurality of cancellation circuits, each cancellation circuit is corresponding to one stage of the cascade circuit, the cancellation circuit corresponding to a current stage cascade circuit inputs a clock signal corresponding to an adjacent stage cascade circuit, and outputs a cancellation signal, the cancellation signal offsets a part of the current stage scanning signal outputted from the current stage cascade circuit, so that the scanning signals outputted from two adjacent stages of the cascade circuit are not overlapped. 
     Wherein, the cancellation circuit comprises a first transistor, a control terminal of the first transistor is connected a clock signal corresponding to the adjacent stage cascade circuit, a first connecting terminal of the first transistor is connected to a low constant potential Vss, a second connecting terminal of the first transistor is connected to the current stage scanning signal. 
     Wherein, the cascade circuit comprises an output transistor, a control terminal of the output transistor is connected to a control node, a first connecting terminal of the output transistor is connected to the clock signal corresponding to the current stage, a second connecting terminal of the output transistor is connected to the current stage scanning signal; configuring an on-resistance ratio of the output transistor and the first transistor, so that in a pulse duration when the clock signals corresponding to the adjacent stage and the current stage are overlapped, a potential of the current stage scanning signal cannot turn on a TFT that being connected to the current stage scanning signal and used for charge sharing. 
     Wherein, the cancellation circuit comprises a second transistor, a third transistor, a fourth transistor, and a fifth transistor; a first connecting terminal of the second transistor is connected to the clock signal corresponding to the adjacent stage cascade circuit, a control terminal of the second transistor is connected to a first control signal, a second connecting terminal of the second transistor is connected to a control terminal of the third transistor, a first connecting terminal of the third transistor is connected to a low constant potential Vss, a second connecting terminal of the third transistor is connected to the current stage scanning signal; a first connecting terminal of the fourth transistor is connected to the clock signal corresponding to the adjacent stage cascade circuit, a control terminal of the fourth transistor is connected to a second control signal, a second connecting terminal of the fourth transistor is connected to a control terminal of the fifth transistor, a first connecting terminal of the fifth transistor is connected to the low constant potential Vss, a second connecting terminal of the fifth transistor is connected to the current stage scanning signal; wherein a phase of the first control signal and a phase of the second control signal are opposite, frequencies of the first control signal and the second control signal are smaller than that of the clock signal. 
     Wherein, the cascade circuit comprises an output transistor, a control terminal of the output transistor is connected to a control node, a first connecting terminal of the output transistor is connected to the clock signal corresponding to the current stage, a second connecting terminal of the output transistor is connected to the current stage scanning signal; configuring on-resistance ratios of the output transistor, the third transistor, and the fifth transistor, so that in a pulse duration when the clock signals corresponding to the adjacent stage and the current stage are overlapped, a potential of the current stage scanning signal cannot turn on a TFT that being connected to the current stage scanning signal and used for charge sharing. 
     Wherein, the cancellation circuit comprises a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; a first connecting terminal of the sixth transistor is connected to the clock signal corresponding to the adjacent stage cascade circuit, a control terminal of the sixth transistor is connected to a forward scanning signal, a second connecting terminal of the sixth transistor is connected to a control terminal of the seventh transistor, a first connecting terminal of the seventh transistor is connected to a low constant potential Vss, a second connecting terminal of the seventh transistor is connected to the current stage scanning signal; a first connecting terminal of the eighth transistor is connected to a clock signal corresponding to another adjacent stage cascade circuit, a control terminal of the eighth transistor is connected to a reverse scanning signal, a second connecting terminal of the eighth transistor is connected to a control terminal of the ninth transistor, a first connecting terminal of the ninth transistor is connected to the low constant potential Vss, a second connecting terminal of the ninth transistor is connected to the current stage scanning signal. 
     Wherein, the cascade circuit comprises an output transistor, a control terminal of the output transistor is connected to a control node, a first connecting terminal of the output transistor is connected to the clock signal corresponding to the current stage, a second connecting terminal of the output transistor is connected to the current stage scanning signal; configuring on-resistance ratios of the output transistor, the seventh transistor, and the ninth transistor, so that in a pulse duration when the clock signals corresponding to the adjacent stage and the current stage are overlapped, a potential of the current stage scanning signal cannot turn on a TFT that being connected to the current stage scanning signal and used for charge sharing. 
     Wherein, a total group of the clock signals are m, wherein m is an even number, an average duty cycle of each clock signal is 50%, the current stage cascade circuit is a n-th stage, wherein n is a positive integer, the current stage cascade circuit is connected to a cascade signal ST (n−m/2) outputted from a (n−m/2) stage cascade circuit and a cascade signal ST (n+m/2) outputted from a (n+m/2) stage cascade circuit. 
     In order to solve one of the above problems, the present disclosure provides an array substrate. The array substrate comprises: a scan driving circuit which comprises a multi-stage cascade circuit, each stage of the cascade circuit inputs a clock signal corresponding to a current stage, and outputs a current stage scanning signal and a current stage cascade signal, different stages of the cascade circuit are connected with each other via the cascade signal; a plurality of cancellation circuits, each cancellation circuit is corresponding to one stage of the cascade circuit, the cancellation circuit corresponding to a current stage cascade circuit inputs a clock signal corresponding to an adjacent stage cascade circuit, and outputs a cancellation signal, the cancellation signal offsets a part of the current stage scanning signal outputted from the current stage cascade circuit, so that the scanning signals outputted from two adjacent stages of the cascade circuit are not overlapped. 
     Wherein, the cancellation circuit of the scan driving circuit comprises a first transistor, a control terminal of the first transistor is connected a clock signal corresponding to the adjacent stage cascade circuit, a first connecting terminal of the first transistor is connected to a low constant potential Vss, a second connecting terminal of the first transistor is connected to the current stage scanning signal. 
     Wherein, the cascade circuit of the scan driving circuit comprises an output transistor, a control terminal of the output transistor is connected to a control node, a first connecting terminal of the output transistor is connected to the clock signal corresponding to the current stage, a second connecting terminal of the output transistor is connected to the current stage scanning signal; configuring an on-resistance ratio of the output transistor and the first transistor, so that in a pulse duration when the clock signals corresponding to the adjacent stage and the current stage are overlapped, a potential of the current stage scanning signal cannot turn on a TFT that being connected to the current stage scanning signal and used for charge sharing. 
     Wherein, the cancellation circuit of the scan driving circuit comprises a second transistor, a third transistor, a fourth transistor, and a fifth transistor; a first connecting terminal of the second transistor is connected to the clock signal corresponding to the adjacent stage cascade circuit, a control terminal of the second transistor is connected to a first control signal, a second connecting terminal of the second transistor is connected to a control terminal of the third transistor, a first connecting terminal of the third transistor is connected to a low constant potential Vss, a second connecting terminal of the third transistor is connected to the current stage scanning signal; a first connecting terminal of the fourth transistor is connected to the clock signal corresponding to the adjacent stage cascade circuit, a control terminal of the fourth transistor is connected to a second control signal, a second connecting terminal of the fourth transistor is connected to a control terminal of the fifth transistor, a first connecting terminal of the fifth transistor is connected to the low constant potential Vss, a second connecting terminal of the fifth transistor is connected to the current stage scanning signal; wherein a phase of the first control signal and a phase of the second control signal are opposite, frequencies of the first control signal and the second control signal are smaller than that of the clock signal 
     Wherein, the cascade circuit of the scan driving circuit comprises an output transistor, a control terminal of the output transistor is connected to a control node, a first connecting terminal of the output transistor is connected to the clock signal corresponding to the current stage, a second connecting terminal of the output transistor is connected to the current stage scanning signal; configuring on-resistance ratios of the output transistor, the third transistor, and the fifth transistor, so that in a pulse duration when the clock signals corresponding to the adjacent stage and the current stage are overlapped, a potential of the current stage scanning signal cannot turn on a TFT that being connected to the current stage scanning signal and used for charge sharing. 
     Wherein, the cancellation circuit of the scan driving circuit comprises a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; a first connecting terminal of the sixth transistor is connected to the clock signal corresponding to the adjacent stage cascade circuit, a control terminal of the sixth transistor is connected to a forward scanning signal, a second connecting terminal of the sixth transistor is connected to a control terminal of the seventh transistor, a first connecting terminal of the seventh transistor is connected to a low constant potential Vss, a second connecting terminal of the seventh transistor is connected to the current stage scanning signal; a first connecting terminal of the eighth transistor is connected to a clock signal corresponding to another adjacent stage cascade circuit, a control terminal of the eighth transistor is connected to a reverse scanning signal, a second connecting terminal of the eighth transistor is connected to a control terminal of the ninth transistor, a first connecting terminal of the ninth transistor is connected to the low constant potential Vss, a second connecting terminal of the ninth transistor is connected to the current stage scanning signal. 
     Wherein, the cascade circuit of the scan driving circuit comprises an output transistor, a control terminal of the output transistor is connected to a control node, a first connecting terminal of the output transistor is connected to the clock signal corresponding to the current stage, a second connecting terminal of the output transistor is connected to the current stage scanning signal; configuring on-resistance ratios of the output transistor, the seventh transistor, and the ninth transistor, so that in a pulse duration when the clock signals corresponding to the adjacent stage and the current stage are overlapped, a potential of the current stage scanning signal cannot turn on a TFT that being connected to the current stage scanning signal and used for charge sharing. 
     Wherein, a total group of the clock signals are m, wherein m is an even number, an average duty cycle of each clock signal is 50%, the current stage cascade circuit is a n-th stage, wherein n is a positive integer, the current stage cascade circuit is connected to a cascade signal ST (n−m/2) outputted from a (n−m/2) stage cascade circuit and a cascade signal ST (n+m/2) outputted from a (n+m/2) stage cascade circuit. 
     Wherein, the array substrate further comprises a plurality of pixels arranged in array, each of the pixels comprises a main-region and a sub-region, the main-region comprises a first pixel electrode and a first TFT, the sub-region comprises a second pixel electrode, a coupling capacitor, a second TFT, and a third TFT; in the main-region of each pixel, a control terminal of the first TFT is connected to the current stage scanning signal outputted from the cascade circuit corresponding to a row where the pixel is disposed, a first connecting terminal of the first TFT is connected to a data line corresponding to a column where the pixel is disposed, a second connecting terminal of the first TFT is connected to the first pixel electrode; in the sub-region of each pixel, a control terminal of the second TFT is connected to the current stage scanning signal outputted from the cascade circuit corresponding to the row where the pixel is disposed, a first connecting terminal of the second TFT is connected to the data line corresponding to the column where the pixel is disposed, a second connecting terminal of the second TFT is connected to the second pixel electrode and a first connecting terminal of the third TFT, a control terminal of the third TFT is connected to a scanning signal outputted from a cascade circuit corresponding to a row next to the row where the pixel is disposed, a second connecting terminal of the third TFT is connected to the coupling capacitor. 
     Wherein, the array substrate further comprises scan lines corresponding to the pixels, the control terminal of the first TFT in each pixel and the control terminal of the third TFT in all the pixels on a row previous to the row where the pixel is disposed are connected to the current stage scanning signal outputted from the cascade circuit corresponding to the row where the pixel is disposed, via the same scan line. 
     The beneficial effect of the present disclosure is: in a pulse duration when the clock signals corresponding to the current stage cascade circuit and the adjacent stage cascade circuit are overlapped, that is, the cancellation signal outputted from the cancellation circuit offsets the current stage scanning signal when the clock signal corresponding to the current stage cascade circuit and the clock signal corresponding to the adjacent stage cascade circuit are both high potentials, i.e., the current stage scanning signal is dropped down from a high potential to a low potential, so that the scanning signals outputted from the two adjacent stages of the cascade circuit will not be overlapped, therefore, a VA liquid crystal with wide viewing angle can be driven without changing the clock signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a timing diagram of a GOA circuit having four clock signals provided by the present disclosure. 
         FIG. 2  is a schematic diagram of a scan driving circuit according to a first preferred embodiment of the present disclosure. 
         FIG. 3  is a circuit diagram of a scan driving circuit according to a second preferred embodiment of the present disclosure 
         FIG. 4  is a timing diagram of a cancellation circuit being accessed to CK(i−1) according to a second preferred embodiment of a scan driving circuit in the present disclosure. 
         FIG. 5  is a timing chart of a cancellation circuit being accessed to CK(i+1) according to a second preferred embodiment of a scan driving circuit in the present disclosure. 
         FIG. 6  is a circuit diagram of a scan driving circuit according to a third preferred embodiment of the present disclosure. 
         FIG. 7  is a circuit diagram of a scan driving circuit according to a fourth preferred embodiment of the present disclosure. 
         FIG. 8  is a timing diagram of a scan driving circuit according to a fourth preferred embodiment of the present disclosure. 
         FIG. 9  is a schematic diagram of an array substrate according to a first preferred embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The following descriptions of the respective embodiments are specific embodiments capable of being implemented as illustrations of the present disclosure. 
     As shown in  FIG. 2 , the scan driving circuit according to a first preferred embodiment of the present disclosure comprises: a multi-stage cascade circuit  1 , a plurality of cancellation circuits  2 , each cancellation circuits is corresponding to one stage of the cascade circuit  1 . The scan driving circuit of the present embodiment is disposed on an array substrate, and used for inputting a current stage cascade scanning signal to pixels via scan lines. Each stage of the cascade circuit  1  inputs a clock signal CK(i) corresponding to the current stage, and outputs a current stage scanning signal G(n) and a current stage cascade signal ST(n), different stages of the cascade circuit are connected with each other via a cascade signal. 
     The clock signal is typically a square wave, the current stage scanning signal G(n) is used to control the pixels, during a scanning process of a one frame image, the current stage scanning signal only requires one pulse, thus the cascade circuit is necessary to access a previous stage cascade signal and a next stage cascade signal to control the current stage scanning signal G(n). The previous stage cascade signal is a cascade signal ST(n−j) outputted from the n−j stage cascade circuit, the next stage cascade signal is a cascade circuit signal ST(n+j) outputted from the n+j stage cascade circuit, wherein j is calculated based on the group number and the duty cycle of the clock signal. 
     In one embodiment of the present disclosure, a total group of the clock signals are m, wherein m is an even number, an average duty cycle of each clock signal is 50%, it can be calculated that j=m/2. The previous stage cascade signal is ST (n−m/2), the next stage cascade signal is ST (n+m/2), wherein n is a positive integer. For example, when six groups of clock signals are adopted, the previous cascade signal is ST (n−3), the next cascade signal is ST (n+3). 
     The cancellation circuit  2  inputs a clock signal corresponding to an adjacent stage cascade circuit, the cancellation circuit offsets a part of the current stage cascade scanning signal outputted from the current stage cascade circuit, so that the scanning signals outputted from two adjacent stages of the cascade circuit are not overlapped. 
     As shown in the  FIG. 2 , the clock signal corresponding to the adjacent stage cascade circuit is refer to the clock signal corresponding to the previous stage cascade circuit, that is CK(i−1), or CK(i+1). Take the cancellation circuit  2  that inputs CK(i−1) for example, the pulses of CK(i−1) and CK(i) are partially overlapped, generally, in one pulse cycle, the time that CK(i−1) being increased from low potential to high potential, and the time that CK(i−1) being lowered from high potential to low potential are both earlier than that of CK(i). The cancellation signal outputted from the cancellation circuit  2  offsets the current stage scanning signal G(n) in a front half of the pulse duration when the pulses of CK(i) and CK(i−1) are overlapped. When the cancellation circuit inputs CK(i+1), then the current stage scanning signal G(n) is offset in a last half of the pulse duration when the pulses of CK(i) and CK(i−1) are overlapped. 
     The clock signal accesses to the cascade circuit  1  sequentially. Suppose a total group of the clock signals are m, when CK(i) is set for the first group of the clock signal, CK(i−1) is refer to a m-th group of clock signal; when CK (i) set for the m-th group of the clock signal, CK(i+1) is refer to the first group of the clock signal. 
     In a pulse duration when the clock signals corresponding to the current stage cascade circuit and the adjacent stage cascade circuit are overlapped, i.e., when the clock signal corresponding to the current stage cascade circuit and the clock signal corresponding to the adjacent stage cascade circuit are both high potentials, the cancellation signal outputted from the cancellation circuit offsets the current stage scanning signal, that is, the current stage scanning signal is lowered from high potential to low potential, the scanning signals outputted from two adjacent stages of the cascade circuit are not overlapped, the VA liquid crystal with wide viewing angle can be driven without changing the clock signals by implementing the above-described embodiment. 
     Please link to  FIGS. 3, 4, and 5 , the second preferred embodiment of the scan driving circuit in the present disclosure comprises a multi-stage cascade circuit and the corresponding cancellation circuits,  FIGS. 3 to 5 , only show a cascade circuit  11  and a corresponding cancellation circuit  12 , please refer to  FIG. 2  for the connections between different stages of the cascade circuit. 
     The cascade circuit  11  comprises a eleventh transistor T 11 , a twelfth transistor T 12 , a thirteenth transistor T 13 , a fourteenth transistor T 14 , a fifteenth transistor T 15 , and a bootstrap capacitor. A first connecting terminal and a control terminal of the eleventh transistor T 11  are connected to a previous stage cascade signal, a second connecting terminal of the eleventh transistor T 11  is connected to a control node Q 1 . A control terminal of the twelfth transistor T 12  is connected to the control node Q 1 , a first connecting terminal of the twelfth transistor T 12  is connected to a clock signal CK(i), a second connecting terminal of the twelfth transistor T 12  outputs a current stage cascade signal ST(n). 
     A control terminal of the thirteenth transistor T 13  is connected to the control node Q 1 , a first connecting terminal of the thirteenth transistor T 13  is connected to the clock signal CK(i), a second connecting terminal of the thirteenth transistor T 13  outputs a current stage scanning signal G(n). One end of the bootstrap capacitor C 1  is connected to the control node Q 1 , another end of the bootstrap capacitor C 1  is connected to the current stage scanning signal G(n). There are four groups of the clock signals being used in the present embodiment, an average duty cycle is 50%, it can be calculated that j=2, and a previous stage cascade signal is ST(n−2). 
     A control terminal of the fourteenth transistor T 14  is connected to a next stage cascade signal ST(n+2), a first connecting terminal of the fourteenth transistor T 14  is connected to a low constant potential Vss, a second connecting terminal of the fourteenth transistor T 14  is connected to the control node Q 1 . A control terminal of the fifteenth transistor T 15  is connected to the next stage cascade signal ST(n+2), a first connecting terminal of the fifteenth transistor T 15  is connected to the low constant potential Vss, a second connecting terminal of the fifteenth transistor T 15  is connected to the current stage scanning signal G(n). 
     The cancellation circuit  12  comprises a first transistor T 1 , a control terminal of the first transistor T 1  is connected to CK(i−1), a first connecting terminal of the first transistor T 1  is connected to the low constant potential Vss, a second connecting of the first transistor T 1  is connected to the current stage scanning signal G(n). The corresponding timing diagram is shown in  FIG. 4 . 
     Wherein the control terminals of the transistors are gates. If the transistors are symmetrical, then the first connecting terminals are sources, the second connecting terminals are drains; or the first connecting terminals are drains, and the second connecting terminals are sources. If the transistors are not symmetrical, then the first connecting terminals are sources, the second connecting terminals are drains. 
     As shown in  FIG. 4 , take G(n+2) for example, a front half of the positive pulse of CK 3  and a last half of the positive pulse of CK 2  are overlapped, in the overlapping pulse duration, the current stage scanning signal G(n+2) is dropped down to Vss by the first transistor, hence, G(n+2) and G(n+1) are not overlapped. The scanning signals outputted from the other adjacent stages of the cascade circuit are also operated in the same manner. 
     As shown in  FIG. 4 , the cancellation circuit  12  can be connected to CK(i−1), as well as being connected to CK(i+1), the current stage scanning signal G(n) is dropped down to Vss during the last half of CK(i). In the meantime, the fifteenth transistor T 15  which is used to drop down the current stage scanning signal can be removed, a corresponding timing diagram is shown in  FIG. 5   
     As shown in  FIG. 6 , a third preferred embodiment of the scan driving circuit in the present disclosure is based on the first preferred embodiment of the scan driving circuit in the present disclosure, and by further accessing the first control signal LC 1  and the second control signal LC 2  to the cancellation circuit  22 . There are only one cascade circuit  21  and one corresponding cancellation circuit  22  being illustrated in  FIG. 6 , please refer to  FIG. 2  for the connections between different stages of the cascade circuit. 
     The elements and their connections in the cascade circuit  21  please refer to the description of the second preferred embodiment of the scan driving circuit in the present disclosure. The present embodiment also adopts four groups of the clock signals, an average duty cycle is 50%. The cancellation circuit  22  comprises a second transistor T 2 , a third transistor T 3 , a fourth transistor T 4 , and a fifth transistor T 5 . 
     A first connecting terminal of the second transistor T 2  is connected to CK(i−1), a control terminal of the second transistor T 2  is connected to the first control signal LCL, a second connecting terminal of the second transistor T 2  is connected to a control terminal of the third transistor T 3 . A first connecting terminal of the third transistor T 3  is connected to a low constant potential Vss, a second connecting terminal of the third transistor T 3  is connected to a current stage scanning signal G(n). 
     A first connecting terminal of the fourth transistor T 4  is connected to CK(i−1), a control terminal of the fourth transistor T 4  is connected to a second control signal LC 2 , a second terminal of the fourth transistor T 4  is connected to a control terminal of the fifth transistor T 5 . A first connecting terminal of the fifth transistor T 5  is connected to the low constant potential Vss, a second connecting terminal of the fifth transistor T 5  is connected to the current scanning signal G(n). 
     Wherein, the control terminals of the transistors are gates. If the transistors are symmetrical, then the first connecting terminals are sources, the second connecting terminals are drains; or the first connecting terminals are drains, and the second connecting terminals are sources. If the transistors are not symmetrical, then the first connecting terminals are sources, the second connecting terminals are drains. 
     The phase of the first control signal LC 1  and the phase of the second control signal LC 2  are opposite, the frequencies of the first control signal LC 1  and the second control signal LC 2  are smaller than that of the clock signal. For example, the high/low potential of the LC 1  and LC 2  are switched once per frame duration, the LC 1  is dropped down by T 3  when it is in high potential, in this moment, LC 2  is in low potential, T 5  is off and will not carry out any action. In next frame, LC 1  is in low potential, T 3  is off, and LC 1  is dropped down by T 5 . Please refer to  FIG. 4  for the timing diagram. 
     The cancellation circuit  22  in the  FIG. 6  can be connected to CK(i−1), as well as being connected to CK(i+1), at this time the twenty-fifth transistor T 25  used to drop down the current stage scanning signal G(n) can be removed, please refer to  FIG. 5  for the timing diagram. 
     The control terminal in any one of the transistors of the cancellation circuit  22  will not directly connected to a high frequency clock signal, thus it will not be influenced by the high frequency signal, the reliability of the circuit can therefore be improved by implementing the above-described embodiment. 
     Please link to  FIGS. 7 and 8 , a fourth preferred embodiment of the scan driving circuit in the present disclosure is based the first preferred embodiment of the scan driving circuit in the present disclosure, and by further accessing a forward scanning signal Vsf and a reverse scanning signal Vsr. The present embodiment also adopts four groups of the clock signals, an average duty cycle is 50%.  FIGS. 7 and 8  only show a cascade circuit  31  and a corresponding cancellation circuit  32 , please refer to  FIG. 2  for the connections between different stages of the cascade circuit. 
     The cascade circuit  31  comprises a thirty-first transistor T 31 , a thirty-second transistor T 32 , a thirty-third transistor T 33 , a thirty-fourth transistor T 34 , a thirty-fifth transistor T 35 , a thirty-sixth transistor T 36 , a thirty-seventh transistor T 37 , a thirty-eighth transistor T 38 , and a bootstrap capacitor C 2 . 
     A first connecting terminal of the thirty-first transistor T 31  is connected to a previous stage cascade signal ST(n−2), a control terminal of the thirty-first transistor T 31  is connected to the forward scanning signal Vsf, a second connecting terminal of the thirty-first transistor T 31  is connecting to a control node Q 3 . A first connecting terminal of the thirty-second transistor T 32  is connected to a next stage cascade signal ST(n+2), a control terminal of the thirty-second transistor T 32  is connected to the reverse scanning signal Vsr, a second connecting terminal of the thirty-second transistor T 32  is connected to the control node Q 3 . 
     A control terminal of the thirty-third transistor T 33  is connected to the control node Q 3 , a first connecting terminal of the thirty-third transistor T 33  is connected to the clock signal CK(i), a second connecting terminal of the thirty-third transistor T 33  outputs a current stage cascade signal ST(n). A control terminal of the thirty-fourth transistor T 34  is connected to the control node Q 3 , a first connecting terminal of the thirty-fourth transistor T 34  is connected to a clock signal CK(i), a second connecting terminal of the thirty-fourth transistor T 34  is connected to the current stage scanning signal G(n). One end of the bootstrap capacitor C 3  is connected to the control node Q 3 , another end of the bootstrap capacitor is connected to the current stage scanning signal G(n). 
     A first connecting terminal of the third-fifth transistor T 35  is connected to the next stage cascade signal ST(n+2), a control terminal of the third-fifth transistor T 35  is connected to the forward scanning signal Vsf, a second connecting terminal of the third-fifth transistor T 35  is connected to a control terminal of the thirty-sixth transistor T 36 . A first connecting terminal of the thirty-sixth transistor T 36  is connected to a low constant potential Vss, a second connecting terminal of the thirty-sixth transistor T 36  is connected to the control node Q 3 . A first connecting transistor of the thirty-seventh transistor T 37  is connected to the previous stage cascade signal ST(n−2), a control signal of the thirty-seventh transistor T 37  is connected to the reverse scanning signal Vsr, a second connecting terminal of the thirty-seventh transistor T 37  is connected to a control terminal of the thirty-eighth transistor T 38 . A first connecting terminal of the thirty-eighth transistor T 38  is connected to the low constant potential Vss, a second connecting terminal of the thirty-eighth transistor T 38  is connected to the current stage scanning signal G(n). 
     The cancellation circuit  32  comprises a sixth transistor T 6 , a seventh transistor T 7 , a eighth transistor T 8 , and a ninth transistor T 9 . A first connecting terminal of the sixth transistor T 6  is connected to CK(i−1), a control terminal of the sixth transistor T 6  is connected to the scanning signal Vsf, a second connecting terminal of the sixth transistor T 6  is connected to a control terminal of the seventh transistor T 7 . A first connecting terminal of the seventh transistor T 7  is connected to the low constant potential Vss, a second connecting terminal of the seventh transistor T 7  is connected to the current stage scanning signal G(n). A first connecting terminal of the eighth transistor T 8  is connected to CK(i+1), a control terminal of the eighth transistor T 8  is connected to the reverse scanning signal Vsr, a second connecting terminal of the eighth transistor T 8  is connected to a control terminal of the ninth transistor T 9 . A first connecting terminal of the ninth transistor T 9  is connected to the low constant potential Vss, a second connecting terminal of the ninth transistor T 9  is connected to the current stage scanning signal G(n) 
     Wherein the control terminals of the transistors are gates. If the transistors are symmetrical, then the first connecting terminals are sources, the second connecting terminals are drains; or the first connecting terminals are drains, and the second connecting terminals are sources. If the transistors are not symmetrical, then the first connecting terminals are sources, the second connecting terminals are drains. 
     Please refer to  FIG. 7 , a GOA circuit is turned on according to an order of G(n)→G(n+1)→G(n+2) . . . , when the forward scanning signal Vsf is a high potential, and the reverse scanning signal Vsr is a low potential. Yet the GOA circuit is turned on according to an order of G(n+2)→G(n+1)→G(n) . . . , when the forward scanning signal Vsf is a low potential, and the reverse scanning signal is a high potential. The scanning directions can be switched by controlling the potentials of the forward scanning signal Vsf and the reverse scanning signal Vsr. 
     In  FIG. 7 , the first connecting terminal of the sixth transistor T 6  is connected to CK(i−1), the control terminal of the sixth transistor T 6  is connected to the forward scanning signal Vsf, the first connecting terminal of the eighth transistor T 8  is connected to CK(i+1), the control terminal of the eighth transistor T 8  is connected to the reverse scanning signal Vsr, which means that the cancellation circuit  32  is dropped down by CK(i−1) during the forward scanning process, and is dropped down by CK(i+1) during the reverse scanning process. 
     The first connecting terminal of the sixth transistor T 6  can also be connected to CK(i+1), making the control terminal of the sixth transistor T 6  being connected to the forward scanning signal Vsf, the first connecting terminal of the eighth transistor T 8  being connected to CK(i−1), the control terminal of the eighth transistor T 8  being connected to the reverse scanning signal Vsr, and the other connections remain the same; or the first connecting terminal of the sixth transistor T 6  can also be connected to CK(i−1), making the control terminal of the sixth transistor T 6  being connected to the reverse scanning signal Vsr, the first connecting terminal of the eighth transistor being connected to CK(i+1), the control terminal of the eighth transistor T 8  being connected to the forward scanning signal Vsf, and th other connections remain the same. At this time, the cancellation circuit  32  is dropped down by CK(i+1) during the forward scanning process, and is dropped down by CK(i−1) during the reverse scanning process. 
     In one embodiment of the present disclosure, the cascade circuit comprises an output transistor, a control terminal of the output transistor is connected to a control node, a first connecting terminal of the output transistor is connected to a clock signal corresponding to a current stage, the second connecting terminal of the output transistor is connecting to a current stage scanning signal. Configuring an on-resistance ratio of the output transistor and the transistor connected to a low constant potential Vss and a current stage scanning signal in a cancellation circuit corresponding to the cascade circuit, so that in a pulse duration when the clock signals corresponding to the adjacent stage and the current stage are overlapped, a potential of the current stage scanning signal cannot turn on a TFT that being connected to the current stage scanning signal and used for charge sharing. 
     The present embodiment can be combined with any one of the embodiments from the second to the fourth embodiments according to the scan driving circuit in the present disclosure. When the present embodiment is combined with the scan driving circuit as descripted in the second embodiment, the output transistor is the thirteenth transistor T 13 , the control node is Q 1 , the transistor that connects with the low constant potential Vss and the current stage scanning signal is the first transistor T 1 . 
     In a pulse duration when the clock signals corresponding to the current stage and the adjacent stage cascade circuit are overlapped, the thirteenth transistor T 13  and the first transistor T 1  are both turned on, the clock signal CK(i) corresponding to the current stage is a high potential, at this time, the potential of the current stage scanning signal G(n) is (VssR 13 +VHR 1 )/(R 1 +R 13 ), wherein VH represents high potential of CK(i), R 13  represents the on-resistance of the thirteenth transistor T 13 , R 1  represents the on-resistance of the first transistor T 1 . It can be seen that, when the R 13 /R 1  ratio getting greater, the potential of G(n) is more close to Vss. In order to drive the VA liquid crystal with wide viewing angle, the potential of G(n) has to be smaller than the turn-on voltage of the TFT used for charge sharing that is connected to G(n), the threshold of R 13 /R 1  can be calculated according to the turn-on voltage of the TFT used for charge sharing. When the thirteenth transistor T 13  and the first transistor T 1  are FET, the on-resistance can be changed by adjusting the size of channel dimensions. 
     When the present embodiment is combined with the scan driving circuit as descripted in the third embodiment, the output transistor is the twenty-third transistor T 23 , the control node is Q 2 , the transistor that connects with the low constant potential Vss and the current stage scanning signal is the third transistor T 3  and the fifth transistor T 5 . R 23 /R 3  and R 23 /R 5  should all meet the potential requirement of G(n) in the overlapping pulse duration, for details please refer to the description of the combination of the present embodiment and the second preferred embodiment. When the present embodiment is combined with the scan driving circuit as descripted in the fourth embodiment, the output transistor is the thirty-fourth transistor T 34 , the control node is Q 3 , the transistor that connects with the low constant potential Vss and the current stage scanning signal is the seventh transistor T 7  and the ninth transistor T 9 . R 34 /R 7  and R 34 /R 9  should all meet the potential requirement of G(n) in the overlapping pulse duration, for details please refer to the description of the combination of the present embodiment and the second preferred embodiment. 
     As shown in  FIG. 9 , a first embodiment of an array substrate in the present disclosure comprises: a plurality of pixels arranged in array, a scan driving circuit  200 , and a scan line  300  corresponding to a row where the pixels are disposed. 
     Take the pixel  100  for example, the pixel  100  comprises a main-region  110  and a sub-region  120 , the main-region  110  comprises a first pixel electrode  112  and a first TFT  111 , the sub-region  120  comprises a second pixel electrode  122 , a coupling capacitor  124 , a second TFT  121 , and a third TFT  123 . The structure of the other pixels is the same as the pixel  100 . 
     In the main-region  110  of the pixel  100 , a control terminal of the first TFT  111  is connected to a current scanning signal G(n) outputted from the n-th stage cascade circuit  20   n  corresponding to n-th row where the pixel  100  is disposed via the scan line  300 , a first connecting terminal of the first TFT  111  is connected to a data line corresponding a column where the pixel  100  is disposed, a second connecting terminal of the first TFT  111  is connected to the first pixel electrode  112 . 
     In the sub-region  120  of the pixel  100 , a control terminal of the second TFT  121  is connected to the current scanning signal G(n) via the scan line, a first connecting terminal of the second TFT  121  is connected to the data line corresponding to the column where the pixel  100  is disposed, a second connecting terminal of the second TFT  121  is connected to the second pixel electrode  122  and a first connecting terminal of the third TFT  123 ; a control terminal of the third TFT  123  is connected to a current stage scanning signal G(n+1) outputted from a cascade circuit corresponding to a row next to the n-th row where the pixel is disposed, a second connecting terminal of the third TFT  123  is connected to the coupling capacitor  124 . 
     Wherein the control terminal of the TFT is a gate. If the TFT is symmetrical, then the first connecting terminal is source, the second connecting terminal is drain; or the first connecting terminal is drain, the second connecting terminal is source. If the TFT is not symmetrical, then the first connecting terminal is source, the second connecting terminal is drain. 
     The scan driving circuit  200  can be any one of the embodiments and their combinations as descripted in the present disclosure, the scan driving circuit comprises a multi-stage cascade circuit and a plurality of cancellation circuits corresponding to each stage of the cascade circuit, the scanning signals outputted from two adjacent stages of the cascade circuit are not overlapped 
     The working principle of the main-region  110  in each pixel  100  is the same as an ordinary pixel, which will be not repeated herein. For the sub-region  120 , the potentials of the second pixel electrode and the data line are different after being charged. Later on, the control line of a next stage is turned on, where G(n+1) is high potential, G(n) is low potential, the third TFT is on, so as to connect the second pixel electrode  122  and the coupling capacitor  124 , the potential of the second pixel electrode  122  is more close to that of a common electrode by the effect of the coupling capacitor, therefore a voltage difference is generated between two regions, a wide viewing angle is obtained. 
     In one embodiment of the array substrate of the present disclosure, the control terminal of the first TFT in each pixel and the control terminal of the third TFT in all the pixel on a row previous to the row where the pixel is disposed are connected to the current stage scanning signal outputted from the cascade circuit corresponding to the row where the pixel is disposed, via the same scan line. 
     The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to activate others skilled in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present disclosure pertains without departing from its spirit and scope. Accordingly, the scope of the present disclosure is defined by the appended claims rather than the foregoing description and the exemplary embodiments described therein.