Patent Publication Number: US-7723178-B2

Title: Shallow and deep trench isolation structures in semiconductor integrated circuits

Description:
FIELD OF THE INVENTION 
   The present invention relates generally to trench isolation structures and more particularly to shallow and deep trench isolation structures formed in the same semiconductor integrated circuit. 
   BACKGROUND OF THE INVENTION 
   In a conventional integrated circuit which includes NFETs (N-channel field effect transistors) and PFETs, shallow trench isolation regions are usually formed to electrically isolate the NFETs from one another and to electrically isolate the PFETs from one another. These same shallow trench isolation regions, in combination with well doping, also electrically isolate the NFETs and the PFETs. As the spacing requirements of integrated circuits become more exacting, formation of deep wells perfectly aligned with the very narrow shallow trench isolation becomes impractical. Therefore, there is a need for a method for forming deep trench and shallow trench isolation regions in the integrated circuit. 
   SUMMARY OF THE INVENTION 
   The present invention provides a semiconductor structure fabrication method, comprising providing a semiconductor structure which includes a first semiconductor layer and a dielectric bottom portion in the first semiconductor layer, wherein the first semiconductor layer comprises a semiconductor material; forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer comprises the semiconductor material; and after said forming the second semiconductor layer is performed, forming a dielectric top portion and a first STI (Shallow Trench Isolation) region in the second semiconductor layer, wherein the dielectric top portion is in direct physical contact with the dielectric bottom portion. 
   The present invention provides a method for forming deep trench and shallow trench isolation regions in the integrated circuit. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1A  shows a cross-section view of a fabrication process of a semiconductor structure, in accordance with embodiments of the present invention. 
       FIG. 1B  shows a cross-section view of a semiconductor structure resulting from forming a semiconductor layer on the structure of  FIG. 1A , in accordance with embodiments of the present invention. 
       FIG. 1C  shows a cross-section view of a semiconductor structure resulting from creating trenches in the structure of  FIG. 1B , in accordance with embodiments of the present invention. 
       FIG. 1D  shows a cross-section view of a semiconductor structure resulting from forming a photoresist layer on the structure of  FIG. 1C , in accordance with embodiments of the present invention. 
       FIG. 1E  shows a cross-section view of a semiconductor structure resulting from forming holes in the photoresist layer of the structure of  FIG. 1D , in accordance with embodiments of the present invention. 
       FIG. 1F  shows a cross-section view of a semiconductor structure resulting from creating trenches in the structure of  FIG. 1E , in accordance with embodiments of the present invention. 
       FIG. 1G  shows a cross-section view of a semiconductor structure resulting from removing the photoresist layer of the structure of  FIG. 1F , in accordance with embodiments of the present invention. 
       FIG. 1H  shows a cross-section view of a semiconductor structure resulting from forming dielectric regions on the structure of  FIG. 1G , in accordance with embodiments of the present invention. 
       FIG. 1I  shows a cross-section view of a semiconductor structure resulting from forming PFETs and NFETs on the structure of  FIG. 1H , in accordance with embodiments of the present invention. 
       FIG. 2A  shows a cross-section view of a fabrication process of another semiconductor structure, in accordance with embodiments of the present invention. 
       FIG. 2B  shows a cross-section view of a semiconductor structure resulting from forming dielectric regions on the structure of  FIG. 2A , in accordance with embodiments of the present invention. 
       FIG. 2C  shows a cross-section view of a semiconductor structure resulting from forming PFETs and NFETs on the structure of  FIG. 2B , in accordance with embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1A-1I  show cross-section views that illustrate a fabrication process of a semiconductor structure  100 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , the fabrication process of the semiconductor structure  100  can start with a substrate  110 . The substrate  110  can comprise silicon. 
   Next, in one embodiment, alignment mark regions  112  and dielectric regions  114   a  and  114   b  are formed in the substrate  110 . The widths  114   a ′ and  114   b ′ of the dielectric regions  114   a  and  114   b,  respectively, can be around 50 nm. The alignment mark regions  112  and the dielectric regions  114   a  and  114   b  can comprise a dielectric material such as silicon dioxide. The alignment mark regions  112  and the dielectric regions  114   a  and  114   b  can be formed by (i) creating trenches  112 ,  114   a,  and  114   b  and then (ii) filling the trenches  112 ,  114   a,  and  114   b  with silicon dioxide resulting in the alignment mark regions  112  and the dielectric regions  114   a  and  114   b  of  FIG. 1A . More specifically, the trenches  112 ,  114   a,  and  114   b  can be created by selectively etching the substrate  110  in a direction defined by an arrow  111  (hereafter can be referred to as the direction  111 ). The direction  111  is perpendicular to the top surface  110 ′ of the substrate  110 . 
   Next, with reference to  FIG. 1B , in one embodiment, a semiconductor layer  120  is formed on top of the substrate  110 . The semiconductor layer  120  can comprise silicon. The semiconductor layer  120  can be formed by a conventional Smart-Cut® process. The semiconductor layer  120  and the substrate  110  can be collectively referred to as semiconductor substrate  110 + 120 . 
   Next, with reference to  FIG. 1C , in one embodiment, trenches  122  are created in the semiconductor layer  120  and the substrate  110  such that the top surfaces  112 ′ of the alignment mark regions  112  are exposed to the surrounding ambient through the trenches  122 . More specifically, the trenches  122  of the semiconductor layer  120  can be created by conventional lithographic and etching processes. 
   Next, with reference to  FIG. 1D , in one embodiment, a photoresist layer  130  is formed on top of the structure  100  of  FIG. 1C  such that the photoresist layer  130  completely fills the trenches  122 . The photoresist layer  130  can be formed by a conventional spin-on process. 
   Next, in one embodiment, the photoresist layer  130  is patterned resulting in holes  132 ,  134 ,  136 , and  138  in the photoresist layer  130  of  FIG. 1E . With reference to  FIG. 1E , the top surfaces  112 ′ of the alignment mark regions  112  are exposed to the surrounding ambient through the holes  132 . In one embodiment, the width  136 ′ of the hole  136  is different from the width  114   a ′ of the dielectric region  114   a.  For example, the width  136 ′ is greater than the width  114   a′.    
   In one embodiment, the photoresist layer  130  is patterned as follows. The semiconductor structure  100  of  FIG. 1D  is exposed to light of a first wavelength to align a reticle  140  that contains the patterns to be transferred to the photoresist layer  130 . The first wavelength is selected such that the light of the first wavelength is transparent to the photoresist layer  130  but is appropriately reflected by the alignment mark regions  112 . As a result, the reticle  140  can be aligned to the alignment mark regions  112  of  FIG. 1D . Next, in one embodiment, after the alignment of the reticle  140  to the alignment mark regions  112  is performed, the exposure process of the photoresist layer  130  is performed. More specifically, the photoresist layer  130  is exposed to light of a second wavelength from the light source  150  through the reticle  140 . Finally, in one embodiment, after the exposure process is performed, the photoresist layer  130  is developed resulting in the holes  132 ,  134 ,  136 , and  138  in the photoresist layer  130  of  FIG. 1E . 
   Next, in one embodiment, the semiconductor layer  120  is etched with the patterned photoresist layer  130  as a blocking mask resulting in trenches  124 ,  126 , and  128  in the semiconductor layer  120  and the substrate  110 , as shown in  FIG. 1F , such that the top surface  114   a ″ of the dielectric region  114   a  is exposed to the surrounding ambient through the trench  126  and the hole  136 . It should be noted that the substrate  110  is also etched resulting in the trenches  113  in the substrate  110  as shown in  FIG. 1F . With reference to  FIG. 1F , the dielectric region  114   b  remains being buried in the semiconductor layer  120  and the substrate  110  (i.e., the dielectric region  114   b  is surrounded by the semiconductor material of the layers  120  and  110  such as silicon). In one embodiment, the etching of the semiconductor layer  120  is performed such that the bottom surfaces  126 ″ and  128 ″ of the trenches  126  and  128 , respectively, are at lower levels than the top surface  110 ′ of the substrate  110  (i.e., at lower levels than the top surfaces  114   a ″ and  114   b ″ of the dielectric regions  114   a  and  114   b,  respectively) in the direction  111 . The etching of the semiconductor layer  120  can be performed in the direction  111  using the photoresist layer  130  as a blocking mask. 
   Next, in one embodiment, the photoresist layer  130  is removed resulting in the semiconductor structure  100  of  FIG. 1G . The photoresist layer  130  can be removed by a conventional wet etching process. 
   Next, with reference to  FIG. 1H , in one embodiment, dielectric regions  122 ′,  124 ′,  126 ′, and  128 ′ are formed in the trenches  122 ,  124 ,  126 , and  128 , respectively. The dielectric regions  122 ′,  124 ′,  126 ′, and  128 ′ can comprise silicon dioxide. If silicon dioxide is used, the dielectric regions  122 ′,  124 ′,  126 ′, and  128 ′ can be formed by (i) depositing a silicon dioxide layer (not shown) on top of the semiconductor structure  100  of  FIG. 1G  such that the trenches  122 ,  124 ,  126 , and  128  are filled with silicon dioxide and then (ii) removing silicon dioxide outside the trenches  122 ,  124 ,  126 , and  128  resulting in the dielectric regions  122 ′  124 ′,  126 ′, and  128 ′ of FIG. H. More specifically, this deposited silicon dioxide layer can be formed by CVD (Chemical Vapor Deposition) of silicon dioxide on top of the semiconductor structure  100  of  FIG. 1G . Then, a CMP (Chemical Mechanical Polishing) process is performed on top of this silicon dioxide layer until the top surface  120 ′ of the semiconductor layer  120  is exposed to the surrounding ambient resulting in the dielectric regions  122 ′  124 ′,  126 ′, and  128 ′ of  FIG. 1H . 
   It should be noted that the bottom surfaces  126 ″ and  128 ″ of the dielectric regions  126 ′ and  128 ′, respectively, are at lower levels than the top surface  110 ′ of the substrate  110  in the direction  111 . 
   It should be noted that, as shown in  FIG. 1G , the top surface  114   a ″ of the dielectric region  114   a  is exposed to the surrounding ambient through the trench  126 . Therefore, as a result of the filling of the trench  126  with the dielectric region  126 ′, the dielectric region  114   a  is in direct physical contact with the dielectric region  126 ′. The dielectric region  114   a  and the dielectric region  126 ′ constitute a deep trench isolation region  114   a + 126 ′. The deep trench isolation region  114   a + 126 ′ has a top portion  126 ′ and a bottom portion  114   a.  In the example described above, the width  136 ′ of the top portion  126 ′ is greater than the width  114   a ′ of the bottom portion  114   a.    
   Next, in one embodiment, with reference to  FIG. 1I , N-well regions and P-well regions are formed in the semiconductor substrate  110 + 120 . The N-well regions and P-well regions can be formed by conventional ion implantation processes. Next, PFETs (P-channel Field Effect Transistors)  140   a  are formed in the N-well regions and NFETs (N-channel FETs)  140   b  are formed in the P-well regions. The PFETs  140   a  are electrically isolated from one another by the dielectric region  124 ′ (the left one). Similarly, the NFETs  140   b  are also electrically isolated from one another by the dielectric region  124 ′ (the right one). The dielectric regions  124 ′ hereafter can be called STI (Shallow Trench Isolation) regions  124 ′. The PFETs  140   a  are electrically isolated from the NFETs  140   b  by the deep trench isolation region  114   a + 126 ′. The PFETs  140   a  and NFETs  140   b  can be formed by conventional processes. 
   In summary, with reference to  FIG. 1F , the trenches  124 ,  126 , and  128  are created such that the dielectric region  114   a  is exposed to the surrounding ambient through the trench  126 . This requires that the hole  136  created in the photoresist layer  130  overlaps the dielectric region  114   a  in the direction  111 . A first region is said to overlap a second region in a reference direction if and only if there exits at least one point inside the first region such that a straight line going through that point and being parallel to the reference direction would intersect the second region. The creation of the hole  136  which overlaps the dielectric region  114   a  in the direction  111  is performed by the use of the alignment mark regions  112  as described above. Later, after the trenches  124 ,  126 , and  128  are created, the trenches  124 ,  126 , and  128  are filled with a dielectric material resulting in STI regions  124  and  128  and the deep trench isolation region  114   a + 126 ′, as shown in  FIG. 1H . It should be noted that the width  136 ′ of the top portion  126 ′ of the deep trench isolation region  114   a + 126 ′ is greater than the width  114   a ′ of the bottom portion  114   a  of the deep trench isolation region  114   a + 126 ′. 
   In the embodiments described above, with reference to  FIG. 1E , the photoresist layer  130  is patterned such that the top surfaces  112 ′ of the alignment mark regions  112  are exposed to the surrounding ambient through the holes  132 . Alternatively, the photoresist layer  130  is patterned as described above except that the holes  132  are not created. 
     FIGS. 2A-2C  show cross-section views that illustrate a fabrication process of a semiconductor structure  200 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 2A , the fabrication process can start with the semiconductor structure  200  of  FIG. 2A . The semiconductor structure  200  is similar to the semiconductor structure  100  of  FIG. 1A  except that the width  514 ′ of the dielectric region  514  is greater than the width  114   a ′ of the dielectric region  114   a  of  FIG. 1A . The formation of the semiconductor structure  200  of  FIG. 2A  is similar to the formation of the semiconductor structure  100  of  FIG. 1A . 
   Next, with reference to  FIG. 2B , in one embodiment, the semiconductor layer  120  is formed on top of the substrate  110  and then the STI regions  122 ′,  124 ′,  126 ′, and  128 ′ are formed in the semiconductor layer  120  and the substrate  110 . The STI regions  122 ′,  124 ′,  126 ′, and  128 ′ can comprise silicon dioxide. In one embodiment, the width  514 ′ of the dielectric region  514  is greater than the width  136 ′ of the STI region  126 ′. The semiconductor layer  120  and the STI regions  122 ′,  124 ′,  126 ′, and  128 ′ can be formed in a manner similar to the manner in which the semiconductor layer  120  and the STI regions  122 ′,  124 ′,  126 ′, and  128 ′ ( FIG. 1H ) are formed on the semiconductor structure  100  of  FIG. 1A . 
   It should be noted that the dielectric region  514  and the dielectric region  126 ′ constitute a deep trench isolation region  514 + 126 ′. The deep trench isolation region  514 + 126 ′ has a top portion  126 ′ and a bottom portion  514 . In the example described above, the width  136 ′ of the top portion  126 ′ is smaller than the width  514 ′ of the bottom portion  514 . 
   Next, with reference to  FIG. 2C , N-well regions and P-well regions are formed in the semiconductor substrate  110 + 120 . The N-well regions and P-well regions can be formed by conventional ion implantation processes. Next, PFETs (P-channel Field Effect Transistors)  140   a  are formed in the N-well regions and NFETs (N-channel FETs)  140   b  are formed in the P-well regions. The PFETs  140   a  are electrically isolated from one another by the STI region  124 ′ (the left one). Similarly, the NFETs  140   b  are also electrically isolated from one another by the STI region  124 ′ (the right one). The PFETs  140   a  are electrically isolated from the NFETs  140   b  by the deep trench isolation region  514 + 126 ′. The PFETs  140   a  and NFETs  140   b  can be formed by conventional processes. 
   In summary, with reference to  FIG. 2C , the deep trench isolation region  514 + 126 ′ is formed by separately forming the dielectric region  514  and the dielectric region  126 ′. The dielectric region  514  is formed in the substrate  110 , whereas the dielectric region  126 ′ is formed in the semiconductor layer  120 . The width  136 ′ of the top portion  126 ′ is smaller than the width  514 ′ of the bottom portion  514 . 
   In one embodiment, with reference to  FIG. 1A , the alignment mark regions  112  are formed in the dicing channels of the wafer such that after chips (integrated circuits) are formed on the wafer, the wafer can be cut along the dicing channels into separate chips 
   While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.