Patent Publication Number: US-11026309-B2

Title: LED drive circuit with a programmable input for LED lighting

Description:
This application is a continuation of application Ser. No. 16/521,834, filed Jul. 25, 2019, which is a continuation of application Ser. No. 14/725,459, filed May 29, 2015, now U.S. Pat. No. 10,412,796, issued Sep. 10, 2019, which is a continuation of application Ser. No. 14/261,613, filed Apr. 25, 2014, now U.S. Pat. No. 9,049,764, issued Jun. 2, 2015, which is a continuation of application Ser. No. 12/978,836, filed Dec. 27, 2010, now U.S. Pat. No. 8,742,677, which was based on Provisional Application No. 61,335,749, filed Jan. 11, 2010. 
    
    
     BACKGROUND 
     Field of the Disclosure 
     The present invention relates to a LED lighting, and more particularly, the present invention relates to a switching regulator with programmable input. 
     Description of Related Art 
     The LED driver is used to control the brightness of the LED in accordance with its characteristics. The LED driver is also utilized to control the current that flows through the LED. The present invention provides a primary-side controlled switching regulator with a programmable input for a LED driver. One object of this invention is to improve the power factor (PF) of the LED driver. The programmable input can also be used for the dimming control. It is another object of the invention. 
     SUMMARY OF THE INVENTION 
     It is an objective of the present invention to provide a LED drive circuit with programmable input. It can modulate the switching signal to regulate the output current for improving the power factor (PF) of the LED drive circuit. 
     It is an objective of the present invention to provide a LED drive circuit with programmable input. The programmable input can be used for the dimming control. 
     The LED drive circuit according to the present invention comprises a controller and a programmable signal. The controller generates a switching signal coupled to switch a magnetic device for generating an output current to drive a plurality of LEDs. The programmable signal is coupled to regulate a current-control signal of the controller. The switching signal is modulated in response to the current-control signal for regulating the output current. The level of the output current is correlated to the current-control signal. Further, the programmable signal is coupled to control a reference signal of the controller. The switching signal is modulated in response to the reference signal. The level of the output current is correlated to the reference signal. 
     The LED driver according to the present invention comprises a controller and a programmable signal. The controller generates a switching signal coupled to switch a transformer for generating a current input signal coupled to the controller and an output current connected to drive a plurality of LEDs. The programmable signal is coupled to modulate the current input signal. The current input signal is further coupled to generate a current-control signal. The current input signal is correlated to a switching current of the transformer. The switching signal is controlled in response to the current-control signal. The level of the output current is correlated to the current-control signal. 
    
    
     
       BRIEF DESCRIPTION OF ACCOMPANIED DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. In the drawings, 
         FIG. 1  shows a circuit diagram of a preferred embodiment of a LED drive circuit in accordance with the present invention. 
         FIG. 2  is another preferred embodiment of the LED drive circuit in accordance with the present invention. 
         FIG. 3  is a preferred embodiment of the controller in accordance with the present invention. 
         FIG. 4  is a preferred embodiment of the integrator in accordance with the present invention. 
         FIG. 5  shows a preferred embodiment of the maximum duty circuit in accordance with the present invention. 
         FIG. 6  is another preferred embodiment of the controller in accordance with the present invention. 
         FIG. 7  shows a preferred embodiment of the voltage-to-current converter in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       FIG. 1  is a circuit diagram of a preferred embodiment of a LED drive circuit in accordance with the present invention. The LED drive circuit, which is presently preferred to be a LED circuit or a LED driver. An offline transformer  10  is a magnetic device including a primary winding N P , an auxiliary winding N A  and a secondary winding N S . One terminal of the primary winding N P  is coupled to receive an input voltage V IN . The other terminal of the primary winding N P  is coupled to a drain terminal of a power transistor  20 . The power transistor  20  is utilized to switch the offline transformer  10 . One terminal of the secondary winding N S  connects one terminal of a rectifier  40 . A filter capacitor  45  is coupled between the other terminal of the rectifier  40  and the other terminal of the secondary winding N S . A plurality of LEDs  101  . . .  109  are connected in series and connected to the filter capacitor  45  in parallel. 
     A controller  70  comprises a supply terminal VCC, a voltage-detection terminal VDET, a ground terminal GND, a current-sense terminal VS, an input terminal VCNT and an output terminal V PWM . The controller  70  is a primary-side controller that is coupled to control the power transistor  20  for switching the primary winding N P  of the magnetic device. The voltage-detection terminal VDET is coupled to the auxiliary winding N A  via a resistor  50  to receive a voltage-detection signal V DET  for detecting a reflected voltage V AUX . The voltage-detection signal V DET  is correlated to the reflected voltage V AUX . The reflected voltage V AUX  further charges a capacitor  65  via a rectifier  60  for powering the controller  70 . The capacitor  65  is coupled to the supply terminal VCC of the controller  70 . 
     The current-sense terminal VS is coupled to a current-sense resistor  30 . The current-sense resistor  30  is coupled from a source terminal of the power transistor  20  to a ground for converting a switching current I P  of the magnetic device to a current input signal V IP . The switching current I P  flows the power transistor  20 . The output terminal V PWM  outputs a switching signal V PWM  to switch the offline transformer  10 . The controller  70  generates the switching signal V PWM  to switch the magnetic device through the power transistor  20  for generating an output current I O  and controlling the switching current I P . The output current I O  is coupled to drive LEDs  101  . . .  109 . The input terminal VCNT receives a programmable signal V CNT  to control the switching current I P  and the output current I O . 
       FIG. 2  is another preferred embodiment of the LED drive circuit in accordance with the present invention. Comparing with  FIG. 1  and  FIG. 2 , the primary winding N P  is coupled to receive the input voltage V IN  rectified and filtered by a bridge rectifier  80  and a bulk capacitor  89  from an AC input V AC . The AC input V AC  is coupled to an input of the bridge rectifier  80 . The bulk capacitor  89  is coupled between an output of the bridge rectifier  80  and the ground. Moreover, the programmable signal V CNT  is generated at the input terminal VCNT in response to the AC input V AC  of the LED drive circuit through diodes  81  and  82 , a voltage divider formed by resistors  85  and  86 , a filter capacitor  87 . Anodes of the diodes  81  and  82  are coupled to receive the AC input V AC . One terminal of the resistor  85  is coupled to cathodes of the diodes  81  and  82 . The resistor  86  is connected between the other terminal of the resistor  85  and the ground. The filter capacitor  87  is connected to the resistor  86  in parallel. The filter capacitor  87  is further coupled to the input terminal VCNT. Other circuits of this embodiment are the same as the embodiment of  FIG. 1 , so there is no need to describe them again. 
       FIG. 3  is a preferred embodiment of the controller in accordance with the present invention. The controller  70  is a primary-side controller coupled to switch the primary winding N P  of the offline transformer  10 . The detail description of the primary-side controlled regulator can be found in a prior art “Control circuit for controlling output current at the primary side of a power converter” U.S. Pat. No. 6,977,824. 
     A waveform detector  300  detects the witching switching current I P  (as shown in  FIG. 1 ) and generates current-waveform signals V A  and V B  by sampling the current input signal V IP  through the current-sense terminal VS. The waveform detector  300  further receives the switching signal V PWM , a pulse signal PLS and a clear signal CLR. A discharge-time detector  100  receives the voltage-detection signal V DET  via the auxiliary winding N A  (as shown in  FIG. 1 ) to detect the discharge-time of a secondary side switching current I S  and generate a discharge-time signal S DS . The secondary side switching current I S  is proportional to the switching current I P . The pulse width of the discharge-time signal S DS  is correlated to the discharge-time of the secondary side switching current I S . The output current I O  is correlated to the secondary side switching current I S . An oscillator (OSC)  200  generates the pulse signal PLS coupled to a PWM circuit  400  to determine the switching frequency of the switching signal V PWM . The oscillator  200  further generates the clear signal CLR that is coupled to the waveform detector  300  and an integrator  500 . 
     The integrator  500  is used to generate a current signal V Y  by integrating an average current signal I AVG  (as shown in  FIG. 4 ) with the discharge-time signal S DS . The average current signal I AVG  is produced in response to the current-waveform signals V A  and V B . A time constant of the integrator  500  is correlated with a switching period T of the switching signal V PWM . The current signal V Y  is therefore related to the output current I O . A n operational amplifier  71  and a reference signal V REF1  develop an error amplifier for output current control. A positive input of the operational amplifier  71  is coupled to receive the reference signal V REF1 . A negative input of the operational amplifier  71  is coupled to receive the current signal V Y . The error amplifier amplifies the current signal V Y  and provides a loop gain for output current control. 
     A comparator  75  is associated with the PWM circuit  400  for controlling the pulse width of the switching signal V PWM  in response to an output of the error amplifier. A positive input and a negative input of the comparator  75  are coupled to receive the output of the error amplifier and a ramp signal RMP respectively. The ramp signal RMP is provided by the oscillator  200 . An output of the comparator  75  generates a current-control signal S I  for controlling the pulse width of the switching signal V PWM . A current control loop is formed from detecting the switching current I P  to modulate the pulse width of the switching signal V PWM . The current control loop controls the magnitude of the switching current I P  in response to the reference signal V REF1 . 
     The PWM circuit  400  outputs the switching signal V PWM  for switching the offline transformer  10 . The PWM circuit  400  according to one embodiment of the present invention comprises a D flip-flop  95 . an inverter  93 , an AND gate  91  and an AND gate  92 . AD input of the D  95  is supplied with a supply voltage V CC . An output of the inverter  93  is coupled to a clock input CK of the D flip-flop  95 . The pulse signal PLS sets the D flip-flop  95  through the inverter  93 . An output Q of the D flip-flop  95  is coupled to a first input of the AND gate  92 . A second input of the AND gate  92  is coupled to the output of the inverter  93  and receives the pulse signal PLS through the inverter  93 . An output of the AND gate  92  is also an output of the PWM circuit  400  that generates the switching signal V PWM . The D flip-flop  95  is reset by an output of the AND gate  91 . 
     A first input of the AND gate  91  is supplied with a voltage-control signal S V . The voltage-control signal S V  is generated by a voltage control loop, in which the voltage control loop is utilized to regulate the output voltage V O . A second input of the AND gate  91  is coupled to receive the current-control signal S I  for achieving output current control. A third input of the AND gate  91  is coupled to receive a maximum-duty signal S M . The voltage-control signal S V , the current-control signal S I  and the maximum-duty signal S M  can reset the D flip-flop  95  for shorten the pulse width of the switching signal V PWM  so as to regulate the output voltage V O  and the output current I O . The maximum-duty signal S M  is generated by a maximum duty circuit (DMAX)  650 . The maximum duty circuit  650  can be utilized to limit the maximum-duty of the switching signal V PWM  under 50%. 
     A positive input of a comparator  700  is coupled to receive a detect signal α V IN . A low-voltage threshold V TH  is supplied with a negative input of the comparator  700 . An enable signal S EN  is generated at an output of the comparator  700  by comparing the detect signal α V IN  with the low-voltage threshold V IN . The detect signal α V IN  is correlated to the input voltage V IN . The output of the comparator  700  generates the enable signal S EN  coupled to control an AND gate  710 . Two inputs of the AND gate  710  receives the pulse signal PLS and the enable signal S EN  respectively. An output of the AND gate  710  generates a sample signal S P  coupled to the integrator  500 . The detail description for input voltage V IN  detection can be found in prior arts “Control method and circuit with indirect input voltage detection by switching current slope detection” U.S. Pat. No. 7,616,461 and “Detection circuit to detect input voltage of transformer and detection method for the same” U.S. 2008/0048633 A1. 
     The programmable signal V CNT  generated at the input terminal VCNT is supplied to a positive input of a buffer amplifier  720 . A negative input of the buffer amplifier  720  is connected to its output. A resistor  730  is coupled between the output of the buffer amplifier  720  and a reference voltage device  750 . The reference voltage device  750  is connected to the reference signal V REF1  to clamp the maximum voltage of the reference signal V REF1 . The reference voltage device  750  can be implemented by a zener diode. The programmable signal V CNT  is coupled to regulate the current-control signal S I  of the controller  70  through controlling the reference signal V REF1  of a current-loop. Furthermore, the programmable signal V CNT  is coupled to control the reference signal V REF1  of the current-loop of the controller  70 . The switching signal V PWM  is modulated in response to the current-control signal S I  for regulating the output current I O , and the level of the output current I O  is correlated to the current-control signal S I . In other words, the switching signal V PWM  is modulated in response to the reference signal V REF1 , and the level of the output current I O  is correlated to the reference signal V REF1 . 
       FIG. 4  is a preferred embodiment of the integrator in accordance with the present invention. An amplifier  510 , a resistor  511  and a transistor  512  construct a first V-to-I converter to generate a first current I 512  in response to the current-waveform signal V B . A positive input of the amplifier  510  is supplied with the current-waveform signal V B . A negative input of the amplifier  510  is coupled to a source terminal of the transistor  512  and one terminal of the resistor  511 . The other terminal of the resistor  511  is coupled to the ground. An output of the amplifier  510  is coupled to a gate terminal of the transistor  512 . A drain terminal of the transistor  512  generates the first current I 512 . 
     Transistors  514 ,  515  and  519  form a first current mirror for producing a current I 515  and a current I 519  by mirroring the first current I 512 . Source terminals of the transistors  514 ,  515  and  519  of the first current mirror are coupled to the supply voltage V CC . Gate terminals of the transistors  514 ,  515 ,  519  and drain terminals of the transistors  512 ,  514  are connected together. Drain terminals of the transistors  515  and  519  generate the current I 515  and I 519  respectively. Transistors  516  and  517  form a second current mirror for generating a current I 517  by mirroring the current I 515 . Source terminals of the transistors  516  and  517  of the second current mirror are coupled to the ground. Gate terminals of the transistors  516 ,  517  and drain terminals of the transistors  516 ,  515  are connected together. A drain terminal of the transistor  517  generates the current I 517 . 
     An amplifier  530 , a resistor  531  and a transistor  532  form a second V-to-I converter for generating a second current I 532  in response to the current-waveform signal V A . A positive input of the amplifier  530  is supplied with the current-waveform signal V A . A negative input of the amplifier  530  is coupled to a source terminal of the transistor  532  and one terminal of the resistor  531 . The other terminal of the resistor  531  is coupled to the ground. An output of the amplifier  530  is coupled to a gate terminal of the transistor  532 . A drain terminal of the transistor  532  generates the second current I 532 . Transistors  534  and  535  form a third current mirror for producing a current I 535  by mirroring the second current I 532 . Source terminals of the transistors  534  and  535  of the third current mirror are coupled to the supply voltage V CC . Gate terminals of the transistors  534 ,  535  and drain terminals of the transistors  532 ,  534  are connected together. A drain terminal of the transistor  535  generates the current I 535 . 
     Transistors  536  and  537  develop a fourth current mirror for producing a current I 537  in response to the current I 535  and the current I 517 . Source terminals of the transistors  536  and  537  of the fourth current mirror are coupled to the ground. Gate terminals of the transistors  536 ,  537  and drain terminals of the transistors  536 ,  535  are connected together. The drain terminal of the transistor  536  and a drain terminal of the transistor  537  generate a current I 536  and the current I 537  respectively. The current I 536  can be expressed by I 536 =I 535 −I 517 . The geometric size of the transistor  536  is twice the size of the transistor  537 . Therefore the current I 537  is the current I 536  divided by 2. Transistors  538  and  539  form a fifth current mirror for generating a current I 539  by mirroring the current I 537 . Source terminals of the transistors  538  and  539  of the fifth current mirror are coupled to the supply voltage V CC . Gate terminals of the transistors  538 ,  539  and drain terminals of the transistors  538 ,  537  are connected together. A drain terminal of the transistor  539  generates the current I 539 . The drains of the transistor  519  and the transistor  539  are coupled together for generating the average current signal I AVG  by summing the current I 519  and the current I 539 . A current feedback signal V X  is therefore generated at the drain terminals of the transistor  519  and the transistor  539 . The resistor  511 , the resistor  531  and a capacitor  570  determine the time constant of the integrator  500 , and the resistor  531  is correlated to the resistor  511 . 
     A switch  550  is coupled between the drain terminal of the transistor  519  and the capacitor  570 . The switch  550  is controlled by the discharge-time signal S DS  and turned on only during the period of the discharge-time of the secondary side switching current I S . A transistor  560  is coupled to the capacitor  570  in parallel to discharge the capacitor  570 . The transistor  560  is turned on by the clear signal CLR. The integrator  500  further includes a sample-and-hold circuit formed by a sample switch  551  and an output capacitor  571 . The sample switch  551  is coupled between the capacitor  570  and the output capacitor  571 . The switch  551  controlled by the sample signal S P  serves to periodically sample the voltage across the capacitor  570  to the output capacitor  571 . The current signal V Y  is therefore generated across the output capacitor  571 . The sample-and-hold circuit is coupled to sample the current feedback signal V X  for generating the current-control signal S I  (as shown in  FIG. 3 ). The current feedback signal V X  is correlated to the switching current I P  of the offline transformer  10  (as shown in  FIG. 1 ). In other words, the sample-and-hold circuit is coupled to sample the current input signal V IP  (as shown in  FIG. 1 ) for generating the current-control signal S I . As shown in  FIG. 3 , the sample-and-hold circuit will stop sampling the current feedback signal V X  once the input voltage V IN  of the drive circuit is lower than the low-voltage threshold V TH . In other words, the sample-and-hold circuit will stop sampling the current feedback signal V X  once the AC input V AC  (as shown in  FIG. 2 ) is lower than the low-voltage threshold V TH . The AND gate  710  generates the sample signal S P  for sampling of the current feedback signal V X . 
       FIG. 5  shows a preferred embodiment of the maximum duty circuit  650  in accordance with the present invention. The maximum duty circuit  650  includes an inverter  670 , a transistor  671 , a current source  675 , a capacitor  680  and a comparator  690 . A gate terminal of the transistor  671  receives the switching signal V PWM  through the inverter  670 . The switching signal V PWM  is coupled to control the transistor  671 . The current source  675  is coupled between the supply voltage V CC  and a drain terminal of the transistor  671 . A source terminal of the transistor  671  is coupled to the ground. The capacitor  680  is connected between the drain terminal of the transistor  671  and the ground. The transistor  671  is coupled to the capacitor  680  in parallel to discharge the capacitor  680  when the switching signal V PWM  is disabled. The current source  675  is connected to the supply voltage V CC  and is used to charge the capacitor  680  when the switching signal V PWM  is enabled. The current source  675  and the capacitance of the capacitor  680  determine the pulse-width and the amplitude of the voltage across the capacitor  680 . A negative input of the comparator  690  is coupled to the drain terminal of the transistor  671  and the capacitor  680 . A reference signal V REF3  is supplied to a positive input of the comparator  690 . An output of the comparator  690  generates the maximum duty signal S M . To set up the reference signal V REF3  appropriately, the maximum duty circuit  650  can be utilized to limit the maximum-duty of the switching signal V PWM  under 50%. 
       FIG. 6  is another preferred embodiment of the controller  70  in accordance with the present invention. The controller  70  generates the switching signal V PWM  coupled to switch the offline transformer  10  for generating the current input signal V IP  (as shown in  FIG. 1 ). A positive input of a buffer amplifier  780  receives the current input signal V IP . A negative input of the buffer amplifier  780  is coupled to its output. A voltage-to-current converter  800  receives the programmable signal V CNT  to generate a programmable current I CNT . A resistor  790  is coupled between the output of the buffer amplifier  780  and the output of the voltage-to-current converter  800 . The resistor  790  and the output of the voltage-to-current converter  800  are further coupled to the input of the waveform detector  300 . The programmable current I CNT  is further coupled to the current-sense terminal VS (as shown in  FIG. 1 ) via the resistor  790  and the buffer amplifier  780  for modulating the current input signal V IP . Hence, the programmable signal V CNT  generated at the input terminal VCNT is coupled to modulate the current input signal V IP . Referring to the  FIG. 3 , the current input signal V IP  is further coupled to generate the current-control signal S I . The current input signal V IP  is correlated to the switching current I P  of the offline transformer  10  and the programmable signal V CNT . The switching signal V PWM  is controlled in response to the current-control signal S I , thus the level of the output current I O  is correlated to the current-control signal S I . 
       FIG. 7  shows a preferred embodiment of the voltage-to-current converter  800  in accordance with the present invention. The voltage-to-current converter  800  comprises an amplifier  810 . a resistor  825 , a transistor  820 , a first current mirror formed by transistors  830 ,  831 , a current source  850 , a second current mirror formed by transistors  832 .  833 . A positive input of the amplifier  810  receives the programmable signal V CNT . A negative input of the amplifier  810  is coupled to a source terminal of the transistor  820  and one terminal of the resistor  825 . The other terminal of the resistor  825  is coupled to the ground. An output of the amplifier  810  is coupled to agate terminal of the transistor  820 . A drain terminal of the transistor  820  is coupled to the first current mirror and generates a current I 820 . 
     The first current mirror generates a current I 831  by mirroring the current I 820 . Source terminals of the transistors  830  and  831  of the first current mirror are coupled to the supply voltage V CC . Gate terminals of the transistors  830 .  831  and drain terminals of the transistors  830 ,  820  are connected together. A drain terminal of the transistor  831  generates the current I 831 . The second current mirror is coupled to the drain terminal of the transistor  831  to generate a current I 833  by mirroring the current I 831 . Source terminals of the transistors  832  and  833  of the second current mirror are coupled to the ground. Gate terminals of the transistors  832 ,  833  and drain terminals of the transistors  832 ,  831  are connected together. A drain terminal of the transistor  833  generates the current I 833 . The current source  850  is coupled from the supply voltage V CC  to the drain terminal of the transistor  833 . The drain terminal of the transistor  833  further outputs the programmable current I CNT . As shown in  FIG. 6 , the programmable current I CNT  is to modulate the current input signal V IP . The current input signal V IP  is correlated to the switching current I P  of the offline transformer  10  and the programmable signal V CNT . 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.