Patent Publication Number: US-5838524-A

Title: Current limit circuit for inhibiting voltage overshoot

Description:
FIELD OF THE INVENTION 
     The present invention relates to a current limit circuit for inhibiting voltage overshoot in a driver circuit. 
     BACKGROUND OF THE INVENTION 
     To provide a reference voltage to a load in which the reference voltage is obtained from a voltage source or circuit with a high output impedance, it is often required to interpose a driver circuit between the reference voltage source and the load, where the driver circuit has a high input impedance and a low output impedance. Such driver circuits contain feedback or control loop circuitry to control or regulate the load voltage (or a scaled version of it) to be as close as possible to the reference voltage. However, in some situations the load voltage may exceed the reference voltage for short durations of time, which we refer to as voltage overshoots. 
     Voltage overshoot may occur during startup or during large power supply voltage transients. For example, at the startup of many circuits with feedback, the node at which the load voltage is being controlled may display a voltage overshoot in its transient response. The voltage overshoot is directly related to the control loop&#39;s phase response and gain, which are derived from the circuit&#39;s poles and zeroes. 
     Voltage overshoots can be a problem for a number of reasons. It can be a source of high frequency noise in a system. Also, the node at which the load voltage is being controlled may achieve a voltage that can be destructive for some particular circuits. 
     FIG. 1 shows a simplified circuit diagram for a typical driver circuit, or high-side voltage control circuit, for controlling the output voltage V 0  at terminal 10 to be as close as possible to a reference voltage applied to terminal 20. Another reference voltage is applied to terminal 20&#39; to provide bias current Ib, and in general it is different from the reference voltage applied to terminal 20. 
     To simplify the explanation of FIG. 1, let us first assume that diode D 1  is not forward biased, so that no current is flowing on line 30. With no current on line 30, bias control circuit 40 behaves as an error amplifier and provides an error signal at the base of transistor Q9 in response to the difference between V 0  and V ref . The error signal applied to the base of transistor Q9 controls the collector current of transistor Q9, which is mirrored by current mirror Q8 to the base of transistors Q6 and Q7. An increase in the error signal applied to transistor Q9 increases the base current to transistor Q7, which in turn increases the emitter current I 0  of transistor Q7 to thereby increase the load voltage V 0 . Negative feedback from terminal 10 to bias control circuit 40 is simply provided by line 50, so that the error signal applied to transistor Q9 increases in voltage as V 0  decreases below V ref  and decreases in voltage as V 0  increases toward V ref . 
     In this way, bias control circuit 40 in conjunction with the control loop comprising transistor Q9, current mirror Q8, transistor Q7, emitter resistor R 3 , and load R L  tries to maintain V 0  equal to V ref . 
     We now consider the more general case in which D 1  may be forward biased, and consider the current limit function of the remainder of the circuit in FIG. 1. 
     The function of diode D 1  in conjunction with bias control circuit 40, along with transistor Q6, current mirror Q5, and the current mirror comprising transistors Q3 and Q4, is to limit the emitter current I 0  so that it does not exceed a current limit threshold, where the current limit threshold is set by reference or bias current I b . We define the current limit threshold as the value of I 0  for which I s  equals I b . The current limit threshold also depends upon the relationship between I s  and I 0 , which in turn depends upon the ratio of emitter areas between transistors Q6 and Q7, as well as the resistances of resistors R 2  and R 3 . The effect of current on line 30 upon bias control circuit 40 is to decrease the voltage (and current) of the error signal applied to the base of transistor Q9, which thereby reduces the emitter current I 0  provided to load R L . Transistors Q6 and Q7 are configured so that the emitter current I s  of transistor Q6 is indicative of emitter current I 0 . Emitter current I s  may be considered a sense current. Current I s  is mirrored by current mirror Q5 to node 60. 
     The current mirror comprising transistors Q3 and Q4 is biased by reference current I b  and is coupled to node 60 via the collector of transistor Q4. The collector current of transistor Q4 is denoted as I c . The current mirror comprising transistors Q3 and Q4 clamps the collector current I c  so as not to exceed I b . When I s  &lt;I b , the arrangement of current mirror Q5 and transistors Q3 and Q4 is such that collector current I c  is clamped at I s , and diode D 1  is not forward biased. However, if I s  &gt;I b , then I c  is clamped at I b  and diode D 1  will be forward biased. Thus, only when I s  exceeds I b  is diode D 1  forward biased, and the circuit of FIG. 1 tries to prevent the current I 0  supplied to load R L  from exceeding the current limit threshold. 
     However, the circuit of FIG. 1 may be ineffective in limiting the output voltage V 0  to V ref  at startup for several reasons. At start up, the output voltage is initially at approximately zero volts, and bias control circuit 40 will place a voltage at the base of transistor Q9 to start up the circuit. Consequently, transistor Q7 will conduct and V 0  will begin to rise. Because V 0  is initially less than V ref , bias control circuit 40 will continue to increase the voltage at the base of transistor Q9 until transistor Q7 is fully turned on (overdriven but not in saturation) and conducting its maximum current. When V 0  finally does reach V ref , the control loop is, in general, too slow to reduce base current to the base of transistor Q7. Consequently, pass transistor Q7 will remain on and will transfer charge to the reservoir capacitor C L  and cause overshoot. The amount of time required to remove the build up of charge at the base of transistor Q7 is the amount of time that the circuit will slew past the ideal constant settling voltage V ref . 
     As discussed above, the current limiting function provided by transistors Q6, Q3, Q4, current mirror Q5, and diode D 1 , sets the maximum load current, and consequently, this current limiting function will try to keep transistor Q7 from going into saturation. However, the circuit of FIG. 1 does not necessarily limit voltage overshoots at the output because when V 0  reaches V ref , transistor Q7 is still supplying too much current to the load. 
     In the past, voltage clamps have been used to limit the peak voltage at the output of driver circuits. However, voltage clamps are not always effective at eliminating voltage overshoots because the voltage damp must be fast enough to &#34;catch&#34; the rising edge of a voltage overshoot. Furthermore, voltage clamps generally are not effective for high current outputs because of the difficulty of disabling the driver circuit in time to limit the voltage overshoot to a reasonable level. 
     SUMMARY OF THE INVENTION 
     It is an aspect of the present invention to prevent voltage overshoot at the output of a driver circuit. 
     It is another aspect of the present invention to control the output current of the driver circuit by smartly reducing the current through a pass transistor as the output current rises and by preventing the pass transistor from being fully turned on. 
     In an embodiment of the present invention, a diode is coupled to the output terminal of a driver circuit and its junction capacitance is utilized to reduce a current limit threshold depending upon the rate of change of the output voltage at the output terminal. A bias control circuit regulates a pass transistor to prevent load current provided by the driver circuit from exceeding the current limit threshold. The cathode of the diode is coupled to the output terminal so that the voltage at the cathode of the diode is responsive to the output voltage of the driver terminal. The base of a transistor is coupled to the anode of the diode so that the transistor conducts current at its collector when there is a sufficiently large rate of change in the output voltage. The collector current of the transistor reduces a reference current applied to a current mirror. The current mirror is coupled to a bias control circuit so that when the reference current is reduced, the current limit threshold of the driver circuit is also reduced. The diode, transistor, current mirror, and bias control circuit prevent overshoots by reducing the current limit threshold when a sufficiently large rate of change in the output voltage is detected, which prevents the pass transistor from fully turning on. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a high-level circuit diagram of a prior art driver circuit; 
     FIG. 2 is a high-level circuit diagram of an embodiment of the present invention; 
     FIG. 3 is a circuit diagram of an embodiment of the present invention; 
     FIG. 4 is a plot exhibiting voltage overshoot for a prior art driver circuit; and 
     FIG. 5 is a plot exhibiting output voltage vs. time for an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A high-level circuit diagram of an embodiment of the present invention is shown in FIG. 2, where corresponding components in FIGS. 1 and 2 are labeled with the same alpha-numeric reference. In comparing FIGS. 1 and 2, we see that diode C 1 , transistors Q1 and Q2, and resistor R 1  have been added. 
     The junction capacitance of diode C 1  is utilized to reduce the current limit threshold of the circuit of FIG. 2. A qualitative explanation of the circuit of FIG. 2 is as follows: The junction capacitance of diode C 1  will transfer a rapid increase in the output voltage V 0  to the base of transistor Q1. More precisely, letting all transistor base-emitter forward voltage drops be equal to each other and denoted by V be , if the output voltage V 0  is greater than 2V be  and if the rate of change of V 0  is large enough so that dV 0  /dt≧V be  /((β+1)(R 1 )(C 1 )), where the beta value of transistor Q1 is β, the resistance of resistor R 1  is also denoted by the symbol R 1 , and the capacitance of diode C 1  is also denoted by the symbol C 1 , then the junction capacitance of diode C 1  will cause transistor Q1 to go into conduction, which in turn will bring transistor Q2 into conduction. When brought into conduction, transistor Q2 will sink a current I 3  at its collector, which will reduce the current I C  conducted by transistor Q3. Current I c  is mirrored by the current mirror comprising transistors Q3 and Q4. Thus, from the previous discussion regarding FIG. 1, we see that a reduction in I c  results in a reduction of the current limit threshold. A sufficient reduction in the current limit threshold will cause bias control circuit 40 to prevent pass transistor Q7 from being completely turned on when the output voltage V 0  is rapidly increasing. In this way, the embodiment illustrated in FIG. 2 prevents voltage overshoot at output terminal 10. 
     An expression for the maximum slew rate, dV/ 0  /dt, is derived as follows. Referring to FIG. 2, the voltage V b  at the base of transistor Q1 is two base-emitter voltage drops above ground, 
     
         V.sub.b =2V.sub.be .                                       (1) 
    
     Denoting the potential voltage drop across the junction capacitance of diode C 1  by V C , the output voltage V 0  is 
     
         V.sub.0 =V.sub.C +V.sub.b .                                (2) 
    
     From the transistor action of transistor Q1 with a beta value of β, we have (assuming that it is not in saturation) 
     
         I.sub.1 =I.sub.2 /β=V.sub.be /(R.sub.1 *B).           (3) 
    
     The rate of change of the potential difference V C  is 
     
         I.sub.1 =C.sub.1 * d(V.sub.C)/dt.                          (4) 
    
     Because Vb is approximately constant, d(V C )/dt=d(V O )/dt, and therefore we obtain an approximate expression for the maximum slew rate, 
     
         d(V.sub.0)/dt=I.sub.1 /C.sub.1 =V.sub.be /(C.sub.1 *R.sub.1.β). (5) 
    
     The collector current of Q2 is determined by the following analysis. First, we determine the current I 0  based upon d(V 0 )/dt as follows. At node 70, we have 
     
         I.sub.0 =I.sub.CL +I.sub.L +I.sub.1.                       (6) 
    
     The current I 1  in terms of d(V 0 )/dt has already been given in equation (5). Currents I CL  and I L  are given by: 
     
         I.sub.L =V.sub.O /R.sub.L, and                             (7) 
    
     
         I.sub.CL =C.sub.L *d(V.sub.0)/dt.                          (8) 
    
     Using equations (5), (7), and (8) with equation (6) yields: 
     
         I.sub.0 =V.sub.O /R.sub.L +(C.sub.L +C.sub.1)d(V.sub.0)/dt. (9) 
    
     Second, we determine the current limit I C  based upon I 0  in equation (9) as follows. Denoting the ratio of the emitter area of transistor Q7 to the emitter area of transistor Q6 by A, and the resistances of resistors R 2  and R 3  by, respectively, R 2  and R 3 , we obtain from the Ebers-Moll relationship: 
     
         I.sub.s = (V.sub.T /R.sub.2) * ln(D/A)!+I.sub.0 *(R.sub.3 /R.sub.2 !, (10) 
    
     where V T  is the thermal voltage kT/q (25.3 mV at room temperature) and D is the ratio of I 0  to I s . 
     Current limit is involved when I s  is slightly greater than I c , and therefore we set: 
     
         I.sub.s =I.sub.c.                                          (11) 
    
     From node 80 of FIG. 2, we have 
     
         I.sub.3 =I.sub.b ·I.sub.c.                        (12) 
    
     Therefore from equations (9) through (12) we obtain the following expression for I 3  : 
     
         I.sub.3 =I.sub.b - (V.sub.T /R.sub.3)In(D/A)!- V.sub.C /R.sub.1 +(C.sub.L +C.sub.1)d(V.sub.0)/dt!(R.sub.2 /R.sub.3).                (13) 
    
     In a preferred embodiment, values for R 1 , R 2 , R 3 , C 1 , C L , D, and A will be such that first two terms on the right hand side of eq. (13) are significantly larger than the remaining terms when d(V 0 )/dt is bounded as in eq. (5), so that a good approximation for I 3  is 
     
         I.sub.3 =I.sub.b - (V.sub.T /R.sub.3)In(D/A)!, 
    
     and therefore in a preferred embodiment I 3  will stay fairly constant over changes in V 0 . 
     It is possible to remove transistor Q1 and resistor R 1  and connect the base terminal of transistor Q2 to the node V b  in FIG. 3. However, transistor Q1 and resistor R 1  serve the purpose of keeping transistor Q2 off when V 0  is constant and the junction capacitance C 1  is leaky. Any leakage current through junction capacitance C 1  will be multiplied by transistor&#39;s Q1 beta and shunted to ground through resistor R 1 , thereby maintaining transistor Q2 as nonconducting. 
     It is also interesting to note that junction capacitance C 1  is a diode that is connected in a fashion as to utilize its reverse bias junction capacitance. This is useful for the case when V 0  is suddenly pulled to ground by any number of events, such as a short to ground or a disable, because diode C 1  becomes forward biased and presents a drain path for the charge accumulated at the node V b . If junction capacitance C 1  was a true parallel plate capacitor, there would be a time constant associated with the discharge of the parallel plate capacitor through the base-collector junction of transistor Q1 to output terminal 10. This would limit the performance of the circuit when the parallel plate capacitor was not fully discharged and the circuit was restarted. 
     Another embodiment of the present invention is illustrated in FIG. 3. Some of the components in FIG. 3 are labeled with the same symbol as corresponding components in FIG. 2. Resistors R 23  and R 24  and transistor N3 have been added to the current limit section so as to improve the stability of the circuit. Diode D 4  has been added to ensure that diode C 1  does not breakdown at high output voltages and clamp the output. Terminals 10&#39; and 10&#34; are connected together outside the chip package, and together they serve the function of output terminal 10 of FIG. 2. 
     The bias control circuit is comprised of transistors N8, N9, P10, P11, P12, and P13, resistors R 3 , R 4 , R 5 , and R 6 , diode C6, and current mirror transistor P. It is recognized as a difference or error amplifier. Transistor N17, which serves as diode D 1  of FIG. 2, is connected to the base of transistor N9. When diode D 1  is not forward biased, the bias control circuit amplifies the difference in voltages at the base of transistors P10 and P14. When diode D 1  is forward biased (indicating that the too much current is flowing to the load), transistor N9 is brought toward saturation and the voltage at its collector decreases, which in turn decreases the current conducted by transistor Q9 via the two emitter followers comprising transistors P14 and P15, which in turn decreases the load current provided by pass transistor Q7 as explained in connection with FIG. 2. The junction capacitance of diode C6 and resistors R 5  and R 6  provide stability. 
     An example of the improvement of an embodiment of the present invention over the prior art can been seen from FIGS. 4 and 5. Both FIGS. 4 and 5 are plots providing output voltage vs. time for a prior art driver and an embodiment of the present invention, respectively, in which the output voltage of the two drivers are programmed to quickly transition from LOW to HIGH. As can be seen from FIG. 4, the output voltage of a prior art driver exhibits an overshoot before settling down to its steady state HIGH value. However, from FIG. 5, we see that for an embodiment of the present invention, there is no overshoot in output voltage as it transitions from LOW to HIGH.