Patent Publication Number: US-11656675-B2

Title: Application processor performing a dynamic voltage and frequency scaling operation, computing system including the same, and operation method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation application of U.S. patent application Ser. No. 16/994,894 filed Aug. 17, 2020, which is a continuation of U.S. patent application Ser. No. 15/797,383 filed Oct. 30, 2017, issued as U.S. Pat. No. 10,747,297 on Aug. 18, 2020, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0181444, filed on Dec. 28, 2016 in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entirety. 
    
    
     TECHNICAL FIELD 
     Exemplary embodiments of the inventive concept relate to an application processor, and more particularly, to an application processor capable of efficiently performing a dynamic voltage and frequency scaling (DVFS) operation, a computing system including the same, and an operation method thereof. 
     DISCUSSION OF RELATED ART 
     As the number of cores increases in computing systems such as mobile devices to increase multi-thread performance in a mobile environment and patented master intellectual properties (IPs) are continuously added for various multimedia scenarios in an application processor therein, power management may be used to optimize resource allocation among different components. For example, the application processor may perform a dynamic voltage and frequency scaling (DVFS) operation to adjust a frequency and a voltage therein to control performance and power consumption. 
     SUMMARY 
     According to an exemplary embodiment of the inventive concept, a method of operating an application processor, which includes a central processing unit (CPU) with at least one core and a memory interface, including measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a dynamic voltage and frequency scaling (DVFS) operation on the at least one core using the calculated load on the at least one core. 
     According to an exemplary embodiment of the inventive concept, a method of operating a computing system, which includes a plurality of master intellectual properties (IPs), a memory device, and a memory interface, including measuring, during a predetermined period, a memory active cycle including a data transaction cycle of a period in which the memory interface performs a data input/output operation using the memory device in response to a request from at least one of the master IPs and a ready operation cycle of a period in which an operation required to perform the data input/output operation is performed, calculating a load on a memory clock domain including the memory device and the memory interface using the memory active cycle, and performing a DVFS operation on the memory interface and the memory device using the load on the memory clock domain. 
     According to an exemplary embodiment of the inventive concept, an application processor includes a memory interface connected to at least one external memory device, an input/output interface connected to at least one external master IP, a multi-core CPU including a plurality of cores, and a memory configured to store a DVFS program. Each of the plurality of cores is configured to correct a core active cycle of a period in which an operation is performed to execute instructions during a first period by using information about a memory access stall cycle of a period in which each core accesses the memory interface within the core active cycle and to execute a program stored in the memory to perform a DVFS operation using the corrected core active cycle. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features of the inventive concept will be more clearly understood by describing in detail exemplary embodiments thereof with reference to the accompanying drawings. 
         FIG.  1    is a block diagram showing a computing system according to an exemplary embodiment of the inventive concept. 
         FIG.  2    is a block diagram showing a central processing unit (CPU) according to an exemplary embodiment of the inventive concept. 
         FIG.  3    is a timing diagram illustrating a dynamic voltage and frequency scaling (DVFS) operation with respect to the CPU of  FIG.  2   , according to an exemplary embodiment of the inventive concept. 
         FIGS.  4 A and  4 B  are views showing mathematical expressions to obtain a load on core in a DVFS operation, according to an exemplary embodiment of the inventive concept. 
         FIG.  5    is a block diagram showing a CPU according to an exemplary embodiment of the inventive concept. 
         FIG.  6    is a timing diagram illustrating a DVFS operation with respect to the CPU of  FIG.  5    according to an exemplary embodiment of the inventive concept. 
         FIG.  7    is a flowchart of an operation method of an application processor, according to an exemplary embodiment of the inventive concept. 
         FIG.  8    is a flowchart of a method of operating an application processor to generate information about a memory access stall cycle, according to an exemplary embodiment of the inventive concept. 
         FIG.  9    is a flowchart of a method of operating an application processor to calculate a load on a core, according to an exemplary embodiment of the inventive concept. 
         FIGS.  10  and  11    are a flowchart and a table, respectively, showing a method of generating a threshold cycle per instruction (CPI), according to an exemplary embodiment of the inventive concept. 
         FIG.  12    is a block diagram showing a CPU according to an exemplary embodiment of the inventive concept. 
         FIG.  13    is a view showing a mathematical expression to obtain a load on a memory interface in a DVFS operation with respect to the memory interface, according to an exemplary embodiment of the inventive concept. 
         FIGS.  14 A and  14 B  are timing diagrams showing a memory active cycle with respect to a memory clock domain, according to exemplary embodiments of the inventive concept. 
         FIG.  15    is a flowchart of a method of performing a DVFS operation with respect to a memory clock domain, according to an exemplary embodiment of the inventive concept. 
         FIG.  16    is a block diagram showing a computing system according to an exemplary embodiment of the inventive concept. 
         FIG.  17    is a block diagram showing a method of operating the computing system of  FIG.  16   , according to an exemplary embodiment of the inventive concept. 
         FIG.  18    is a block diagram showing an application processor including multiple cores, according to an exemplary embodiment of the inventive concept. 
         FIG.  19    is a block diagram showing an application processor including multiple cores, according to an exemplary embodiment of the inventive concept. 
         FIG.  20    is a block diagram showing a communication apparatus including an application processor, according to an exemplary embodiment of the inventive concept. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Hereinafter, exemplary embodiments of the inventive concept will be explained in detail with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout this application. 
     Exemplary embodiments of the inventive concept provide an application processor capable of enhancing user experience and optimizing power consumption, a computing system including the same, and an operation method thereof. 
       FIG.  1    is a block diagram showing a computing system according to an exemplary embodiment of the inventive concept. 
     Referring to  FIG.  1   , a computing system  10  may include an application processor  100  and a memory device MD. The computing system  10  shown in  FIG.  1    may correspond to various types of data processing devices, and as an example, the computing system  10  may be a mobile device employing the application processor  100 . In addition, the computing system  10  may be a laptop computer, a mobile phone, a smart phone, a tablet personal computer (PC), a Personal Digital Assistant (PDA), an Enterprise Digital Assistant (EDA), a digital still camera, a digital video camera, a Portable Multimedia Player (PMP), a Personal Navigation Device or a Portable Navigation Device (PND), a handheld game console, a Mobile Internet Device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an e-book, etc. 
     The computing system  10  may include various kinds of memory devices MD. For instance, the memory device MD may correspond to various kinds of semiconductor memory devices. According to an exemplary embodiment of the inventive concept, the memory device MD may be a Dynamic Random Access Memory (DRAM), such as a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), a Low Power Double Data Rate (LPDDR) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, a Rambus Dynamic Random Access Memory (RDRAM), etc. In addition, the memory device MD may be one of a flash memory, a Phase-change RAM (PRAM), a Magnetoresistive RAM (MRAM), a Resistive RAM (ReRAM), or a Ferroelectric RAM (FeRAM). 
     The application processor  100  may be implemented by a System-on-Chip (SoC). The SoC may include a system bus to which a protocol having a predetermined standard bus specification is applied and various Intellectual Properties (IPs) connected to the system bus. As a standard specification of the system bus, an Advanced Microcontroller Bus Architecture (AMBA) protocol of Advanced RISC Machine (ARM) may be applied. A bus type of the AMBA protocol may include Advanced High-performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI), AXI4, AXI Coherency Extensions (ACE), or the like. In addition, other types of protocols, such as uNetwork of SONICs Inc., CoreConnect of IBM, Open Core Protocol of OCP-IP, etc., may be used. 
     The application processor  100  may include a central processing unit (CPU)  110 , a memory interface  120 , a clock management unit (CMU)  130 , a power management integrated circuit (PMIC)  140 , an internal memory  150 , and peri blocks  160 . In the present exemplary embodiment shown in  FIG.  1   , the PMIC  140  is implemented in the application processor  100 , but may instead be implemented outside the application processor  100 . In addition, the application processor  100  may include a power management unit instead of the PMIC  140  to control a power supplied to functional blocks in the application processor  100 . 
     The CPU  110  may include at least one core  112  and may be implemented by a multi-core processor. The core  112  may be an independent processor, and the core  112  may read and execute instructions. The core  112  may load a dynamic voltage and frequency scaling (hereinafter, referred to as “DVFS”) module  114  from the internal memory  150  and execute the DVFS module  114  to perform a DVFS operation. The term “module” used hereinafter may mean hardware or computer program code capable of performing a function or an operation. However, the term “module” used hereinafter should not be limited thereto, and may mean an electronic recording medium, e.g., a processor, with computer program code therein that performs a specific function and operation. In other words, the term “module” may mean a functional and/or structural combination of hardware configured to achieve a technical idea of the inventive concept and/or software configured to instruct the hardware to operate. 
     The peri blocks  160  may correspond to a peripheral block other than the CPU  110 , and as an example, the peri blocks  160  may include various functional blocks, such as an input/output (IO) interface block, a universal serial bus (USB) host block, a universal serial bus (USB) slave block, etc., which communicate with at least one master intellectual property (IP). 
     The DVFS module  114  may determine an operation state of various functional blocks in the application processor  100  and provide control signals to the CMU  130  and the PMIC  140  to control a frequency and/or a power of the various functional blocks based on a determined result. As an example, the DVFS module  114  may control a frequency and a power of a clock signal applied to the CPU  110  and may separately control a frequency and a power of a clock signal applied to the memory interface  120 . 
     The memory interface  120  may access the memory device MD to write data in the memory device MD or to read out data from the memory device MD. The memory interface  120  may interface with the memory device MD and provide various commands, e.g., a write command, a read command, etc., to the memory device MD to perform a memory operation. Accordingly, the memory interface  120  and the memory device MD may be included in a same memory clock domain M_CLK_Domain, and the memory interface  120  and the memory device MD, which are included in the memory clock domain M_CLK_Domain, may perform the memory operation based on clock signals having substantially the same frequency. 
     When an L2 cache miss occurs when the core  112  processes instructions, the core  112  temporarily stops a calculation operation and accesses the memory interface  120  to write data, which is required to process the instructions, in the memory device MD or to read the data from the memory device MD. Hereinafter, the operation in which the core  112  accesses the memory interface  120  may comprehensively refer to an operation in which the core  112  accesses the memory device MD. The operation in which the core  112  stops the calculation operation with respect to the instructions and accesses the memory interface  120  may be referred to as a “memory access stall”. 
     The DVFS module  114  according to the present exemplary embodiment may perform the DVFS operation by taking into account a cycle of a memory access stall period in which the core  112  substantially does not perform the calculation operation. The term “cycle” used hereinafter may indicate a time of a predetermined period and may be changed depending on the frequency of the clock signals that are the basis for the operation of the core  112  or the memory interface  120 . For instance, when a cycle value is “n”, the cycle may correspond to a time corresponding to n periods of the clock signals that are the basis for the operation of the core  112  or the memory interface  120 . As an example, the DVFS module  114  may correct a core active cycle of the period in which the core  112  processes the instructions within a first period based on information on the memory access stall cycle, such that the core active cycle includes only the cycle in which the core  112  substantially performs the calculation operation. The DVFS module  114  may correct the core active cycle by subtracting the memory access stall cycle from the core active cycle. 
     The DVFS module  114  may calculate a load on the core  112  using the corrected core active cycle and a core idle cycle of a period in which the core  112  is in an idle state within the first period. The DVFS module  114  may provide a clock control signal CTR_CC to the CMU  130  or provide a power control signal CTR_CP to the PMIC  140  based on the load on the core  112 . 
     The CMU  130  may provide a clock signal CLK_C having a scaled frequency to the CPU  110  in response to the clock control signal CTR_CC. In addition, the PMIC  140  may provide a power PW_C having a scaled level to the CPU  110  in response to the power control signal CTR_CP. 
     The DVFS module  114  according to the present exemplary embodiment may perform the DVFS operation on the memory interface  120  separately from the CPU  110 . The DVFS module  114  may collect a memory active cycle M_T act  from the memory interface  120 . The memory active cycle M_T act  indicates a cycle in which the memory interface  120  and the memory device MD, which are included in the memory clock domain M_CLK_Domain, perform the memory operation in response to a predetermined request from the CPU  110  or another master IP. 
     As an example, in a second period, the memory active cycle M_T act  may include a data transaction cycle of a period in which the memory interface  120  performs a data input/output operation using the memory device MD and a ready operation cycle of a period in which the memory interface  120  performs an operation required for the data input/output operation in response to the request from the CPU  110  or another master IP. 
     The DVFS module  114  may calculate the load with respect to the memory interface  120  by taking into account the period required to perform the data input/output operation using the memory device MD in addition to the data transaction cycle corresponding to a bandwidth of data input and output through the memory interface  120  and the memory device MD. 
     The DVFS module  114  may calculate a load on the memory clock domain M_CLK_Domain including the memory interface  120  and the memory device MD, based on the collected memory active cycle M_T act  and perform the DVFS operation on the memory interface  120  based on the calculated load. As described above, since the memory interface  120  and the memory device MD are included in the same memory clock domain M_CLK_Domain, the memory device MD may receive the same clock signal CLK_M as the memory interface  120  according to the result of the DVFS operation and may also receive the same power PW_M as the memory interface  120 . 
     The application processor  100  according to the present exemplary embodiment individually performs the DVFS operation by taking into account the load on each of the CPU  110  and the memory interface  120 , and thus, performance of the application processor  100  may be increased. 
       FIG.  2    is a block diagram showing a CPU according to an exemplary embodiment of the inventive concept,  FIG.  3    is a timing diagram illustrating a DVFS operation with respect to the CPU of  FIG.  2   , according to an exemplary embodiment of the inventive concept, and  FIGS.  4 A and  4 B  are views showing mathematical expressions to obtain a load on a core in a DVFS operation, according to exemplary embodiments of the inventive concept. 
     Referring to  FIG.  2   , a CPU  110   a  may include a DVFS module  114   a  and a performance monitoring unit  116   a . For convenience of explanation, an internal memory  150   a  may include a memory interface  120   a  and a threshold cycle per instruction (CPI) store area  150 _ 1   a . The performance monitoring unit  116   a  is hardware implemented in the CPU  110  and measures performance parameters of a core. The performance monitoring unit  116   a  according to the present exemplary embodiment may include an active cycle counter  116 _ 1   a  and an instruction retired counter  116 _ 3   a . The active cycle counter  116 _ 1   a  counts a time of a period in which the core processes instructions during a first period to measure a core active cycle. The first period may be a governor window set by a DVFS governor module  114 _ 1   a , and a length of the first period may be changed depending on a DVFS operation scheme with respect to the core. The instruction retired counter  116 _ 3   a  may count the number of instructions processed in the core active cycle period. 
     The DVFS module  114   a  may include the DVFS governor module  114 _ 1   a , a CMU device driver  114 _ 2   a , and a PMIC device driver  114 _ 3   a . The DVFS governor module  114 _ 1   a  may control the DVFS operation. For example, the DVFS governor module  114 _ 1   a  may collect first count information Count_ 1  including the core active cycle and second count information Count_ 2  including the number of executed instructions from the performance monitoring unit  116   a , and collect a threshold CPI TH_CPI from the internal memory  150   a . The DVFS governor module  114 _ 1   a  may use the threshold CPI TH_CPI to generate information on the memory access stall cycle of the core. The threshold CPI TH_CPI may be a value obtained by measuring the active cycle required for the core to execute a plurality of instructions that do not need to access the memory interface  120   a  and converting the measured active cycle to a cycle required to execute one instruction. In other words, the DVFS governor module  114 _ 1   a  may derive a ratio of the memory access stall cycle included in the core active cycle using the threshold CPI TH_CPI. The threshold CPI TH_CPI will be described in more detail below. In addition, as an example, information, which is generated by the DVFS governor module  114 _ 1   a , on the memory access stall cycle may include an SPI (memory access Stall cycle Per Instruction). The SPI will be described in detail below. 
     Referring to  FIGS.  2  and  3   , a first period IV_ 1  includes a core active cycle T act  and a core idle cycle T idle . The core active cycle T act  measured by the active cycle counter  116 _ 1   a  may include a cycle C in which the core performs the calculation operation and a memory access stall cycle S of a period in which the core accesses the memory interface  120   a  (as indicated by ‘A’ in  FIG.  3   ). As described above, since the core may temporarily stop the calculation operation in the memory access stall cycle S, the memory access stall cycle S may be excluded when the load on the core is accurately calculated. Hereinafter, an example of calculating the load on the core by taking into account the memory access stall cycle S will be described. 
     Referring to  FIG.  4 A , the DVFS governor module  114 _ 1   a  may generate the CPI (Cycle Per Instruction) indicating the cycle required to execute one instruction during the core active cycle T act  using the core active cycle T act  and the number of executed instructions. Since the core active cycle T act  may include the memory access stall cycle S when the core accesses the memory interface  120   a  to execute the instruction, the DVFS governor module  114 _ 1   a  may correct the core active cycle T act  by taking into account the memory access stall cycle S. 
     As an example, the DVFS governor module  114 _ 1   a  may compare the CPI with the threshold CPI TH_CPI and may assume that a predetermined memory access stall cycle is included in the core active cycle T act  when the CPI exceeds the threshold CPI (Case  1 ). Accordingly, the DVFS governor module  114 _ 1   a  may generate the SPI (memory access Stall cycle Per Instruction) indicating the cycle required to access the memory interface  120   a  by one instruction during the core active cycle T act  by subtracting the threshold CPI TH_CPI from the CPI. The DVFS governor module  114 _ 1   a  may correct the core active cycle T act  using the CPI and the SPI. The DVFS governor module  114 _ 1   a  may calculate a load CL core  of the core using a ratio between a corrected core active cycle T act ′ and a sum (T act ′+T idle ) of the corrected core active cycle and the core idle cycle. The DVFS governor module  114 _ 1   a  may control each of the CMU device driver  114 _ 2   a  and the PMIC device driver  114 _ 3   a  based on the load CL core  of the core. The CMU device driver  114 _ 2   a  may provide the clock control signal CTR_CC to the CMU  130  based on the DVFS operation of the DVFS governor module  114 _ 1   a . Accordingly, the CMU  130  may provide the clock signal, having the scaled frequency resulting from the DVFS operation, to the CPU  110   a . In addition, the PMIC device driver  114 _ 3   a  may provide the power control signal CTR_CP to the PMIC  140  based on the DVFS operation of the DVFS governor module  114 _ 1   a . Thus, the PMIC  140  may provide the power, having the scaled level resulting from the DVFS operation, to the CPU  110   a.    
     Referring to  FIG.  4 B , the DVFS governor module  114 _ 1   a  may compare the CPI with the threshold CPI and may not generate the SPI when the CPI is less than or equal to the threshold CPI TH_CPI (Case  2 ). In other words, the DVFS governor module  114 _ 1   a  may assume that the memory access stall cycle S is not included in the core active cycle T act  when the CPI is less than or equal to the threshold CPI TH_CPI and may not generate information on the memory access stall cycle S including the SPI. Accordingly, the DVFS governor module  114 _ 1   a  may calculate the load CL core  of the core using a ratio between the core active cycle T act  and a sum (T act +T idle ) of the core active cycle and the core idle cycle. 
     The DVFS module  114   a  according to the present exemplary embodiment may determine whether the memory access stall cycle S is included in the core active cycle T act  through a simple comparison operation using the threshold CPI TH_CPI. In addition, since the SPI is generated and the core active cycle T act  is corrected using a simple calculation operation, the DVFS operation may be efficiently performed, and the performance of the application processor (e.g., the application processor  100  of  FIG.  1   ) may be increased. 
       FIG.  5    is a block diagram showing a CPU according to an exemplary embodiment of the inventive concept, and  FIG.  6    is a timing diagram illustrating a DVFS operation with respect to the CPU of  FIG.  5    according to an exemplary embodiment of the inventive concept. 
     Referring to  FIG.  5   , a CPU  110   b  may be substantially the same as the CPU  110   a  of  FIG.  2   , except for a memory access stall cycle counter  116 _ 3   b . For example, the CPU  110   b  may include a DVFS module  114   b  and a performance monitoring unit  116   b . The performance monitoring unit  116   b  may include an active cycle counter  116 _ 1   b  and the memory access stall cycle counter  116 _ 3   b . The DVFS module  114   b  may include a DVFS governor module  114 _ 1   b , a CMU device driver  114 _ 2   b , and a PMIC device driver  114 _ 3   b . The DVFS governor module  114 _ 1   b  may be connected to a memory interface  120   b . Hereinafter, differences between the CPU  110   a  of  FIG.  2    and the CPU  110   b  will be described. 
     The memory access stall cycle counter  116 _ 3   b  may count a period in which the core accesses the memory interface  120   b  within the core active cycle to measure the memory access stall cycle. The DVFS governor module  114 _ 1   b  may collect first count information Count_ 1  including the core active cycle and third count information Count_ 3  including the memory access stall cycle from the performance monitoring unit  116   b.    
     Referring to  FIGS.  5  and  6   , the DVFS governor module  114 _ 1   b  may generate the corrected core active cycle T act ′ including only the cycle C in which the core performs a calculation operation by subtracting the memory access stall cycle S from the core active cycle T act  using the first count information Count_ 1  and the third count information Count_ 3 . The DVFS governor module  114 _ 1   b  may accurately calculate the load CL core  of the core using a ratio between the corrected core active cycle T act ′ and a sum (T act ′+T idle ) of the corrected core active cycle and the core idle cycle. The DVFS governor module  114 _ 1   b  may control each of the CMU device driver  114 _ 2   b  and the PMIC device driver  114 _ 3   b  based on the load CL core  of the core. 
     The DVFS module  114   b  according to the present exemplary embodiment may accurately count and generate the memory access stall cycle S included in the core active cycle T act  and calculate the load on the core using the generated memory access stall cycle S, and thus, the DVFS operation may be efficiently performed. 
       FIG.  7    is a flowchart of an operation method of an application processor, according to an exemplary embodiment of the inventive concept. 
     Referring to  FIGS.  2  and  7   , the active cycle counter  116 _ 1   a  may count and measure the core active cycle of the period in which the core performs the operation of executing the instructions within the first period set by the DVFS governor module  114 _ 1   a , and the DVFS governor module  114 _ 1   a  may subtract the core active cycle from the length of the first period to measure the core idle cycle of the period in which the core is in the idle state (S 100 ). Then, the DVFS governor module  114 _ 1   a  may generate the information on the memory access stall cycle that is the period in which the core accesses the memory interface within the core active cycle (S 110 ). The DVFS governor module  114 _ 1   a  may correct the core active cycle based on the information on the memory access stall cycle and calculate the load on the core based on the corrected core active cycle (S 120 ). The DVFS governor module  114 _ 1   a  may perform the DVFS operation on the core based on the load on the core (S 130 ). 
       FIG.  8    is a flowchart of a method of operating an application processor to generate information on a memory access stall cycle, according to an exemplary embodiment of the inventive concept. 
     Referring to  FIGS.  2  and  8   , the DVFS governor module  114 _ 1   a  may collect the core active cycle and the number of executed instructions in the core active cycle from the performance monitoring unit  116   a  and may generate the CPI indicating the cycle required to execute one instruction during the core active cycle (S 111 ). The DVFS governor module  114 _ 1   a  may compare the generated CPI with the threshold CPI provided from the internal memory  150   a  (S 112 ). The DVFS governor module  114 _ 1   a  may determine whether the CPI exceeds the threshold CPI (S 113 ). When the CPI exceeds the threshold CPI (S 113 , YES), the DVFS governor module  114 _ 1   a  may subtract the threshold CPI from the CPI and generate the SPI corresponding to the information on the memory access stall cycle (S 114 ). When the CPI does not exceed the threshold CPI (S 113 , NO), the DVFS governor module  114 _ 1   a  may not generate the SPI (S 115 ). 
       FIG.  9    is a flowchart of a method of operating an application processor to calculate a load on a core according to an exemplary embodiment of the inventive concept. 
     Referring to  FIGS.  2  and  9   , when the SPI is generated by the DVFS governor module  114 _ 1   a  (from S 114  of  FIG.  8   ), the DVFS governor module  114 _ 1   a  may correct the core active cycle, which is measured by the active cycle counter  116 _ 1   a , using the CPI and SPI (S 121 ). When the SPI is not generated (from S 115  of  FIG.  8   ), the DVFS governor module  114 _ 1   a  may maintain the core active cycle measured by the active cycle counter  116 _ 1   a  without correcting the core active cycle (S 123 ). Then, the DVFS governor module  114 _ 1   a  may calculate the load on the core using the core active cycle, which is corrected or not corrected, and the core idle cycle (S 125 ). 
       FIGS.  10  and  11    are a flowchart and a table, respectively, showing a method of generating a threshold CPI, according to an exemplary embodiment of the inventive concept. 
     Referring to  FIG.  10   , the core included in the application processor may perform an N-th executing operation on predetermined instructions in a computing phase boundary to set the threshold CPI used to perform the DVFS operation (S 200 ). The core may consecutively perform the calculation operation to execute the predetermined instructions in the computing phase boundary without the period in which the core accesses the memory interface. The core may measure an N-th candidate active cycle required to execute the predetermined instructions and store the measured N-th candidate active cycle (S 210 ). The core may determine whether the number of the generated candidate active cycles according to the measured result is M (S 220 ). “M” may be an arbitrary value that is previously determined to set the threshold CPI. When the number of the generated candidate active cycles according to the measured result is M (S 220 , YES), e.g., when an M-th executing operation is performed on the predetermined instructions in the computing phase boundary, the core may set the threshold CPI using at least one of the measured M candidate active cycles (S 240 ). When the number of the generated candidate active cycles according to the measured result is not M (S 220 , NO), the core may increment N by 1 (S 230 ) and again perform the executing operation on the predetermined instructions. 
     As shown in  FIG.  11   , a table shows CPKIs (Cycle Per Kilo Instructions) corresponding to the candidate active cycles. 
     The CPKIs represent a cycle taken to execute 1,000 instructions in the computing phase boundary. The CPKIs corresponding to the candidate active cycles may have different values from one another due to factors, such as a floating calculation, a branch prediction fail, etc., when the instructions are executed. According to the present exemplary embodiment, a candidate active cycle C M_1  having the longest length among the M candidate active cycles may be selected, and the threshold CPI may be set using the selected candidate active cycle C M_1 . However, according to an exemplary embodiment of the inventive concept, any one of the M candidate active cycles may be selected based on the DVFS operation scheme, and the threshold CPI may be set using the selected candidate active cycle. 
       FIG.  12    is a block diagram showing a CPU according to an exemplary embodiment of the inventive concept, and  FIG.  13    is a view showing a mathematical expression to obtain a load on a memory interface in a DVFS operation with respect to the memory interface according to an exemplary embodiment of the inventive concept. 
     Referring to  FIG.  12   , a CPU  110   c  may operate a DVFS module  114   c , and the DVFS module  114   c  may include a DVFS governor module  114 _ 1   c , a CMU device driver  114 _ 2   c , and a PMIC device driver  114 _ 3   c . The memory clock domain M_CLK_Domain may include a memory interface  120   c  and the memory device MD. The DVFS governor module  114 _ 1   c  may collect the memory active cycle M_T act , which includes a transaction cycle of a period in which a data input/output operation is performed using the memory device MD and a ready operation cycle of a period in which an operation required by the memory device MD to perform the data input/output operation is carried out, from the memory interface  120   c  during a second period in response to a request from the CPU  110   c  or another master IP. The second period may be a governor window set by the DVFS governor module  114 _ 1   c . A length of the second period may be changed depending on the DVFS operation scheme with respect to the memory interface  120   c , and the length of the second period may be equal to or different from the length of the first period described in  FIG.  2   . 
     Referring to  FIGS.  12  and  13   , the DVFS governor module  114 _ 1   c  may calculate a load CL M  of the memory clock domain M_CLK_Domain using the memory active cycle M_T act , including a data transaction cycle M_T data  and a ready operation cycle M_T RO , and the length M_T total  of the second period. The DVFS governor module  114 _ 1   c  according to the present exemplary embodiment may control each of the CMU device driver  114 _ 2   c  and the PMIC device driver  114 _ 3   c  based on the load CL M  of the memory clock domain M_CLK_Domain. The CMU device driver  114 _ 2   c  may provide the clock control signal CTR_MC to a CMU based on the DVFS operation of the DVFS governor module  114 _ 1   c . Accordingly, the CMU may provide a clock signal, having a scaled frequency resulting from the DVFS operation, to the memory interface  120   c . In addition, the PMIC device driver  114 _ 3   c  may provide the power control signal CTR_MP to a PMIC based on the DVFS operation of the DVFS governor module  114 _ 1   c . Thus, the PMIC may provide a power, having a scaled level resulting from the DVFS operation, to the memory interface  120   c.    
     The DVFS module  114   c  according to the present exemplary embodiment performs the DVFS operation on the memory interface  120   c  and the memory device MD by taking into account the load on the memory interface  120   c  and/or the memory device MD, e.g., the memory clock domain M_CLK_Domain, and thus, the performance of the application processor may be increased. 
       FIGS.  14 A and  14 B  are timing diagrams showing a memory active cycle with respect to a memory clock domain, according to exemplary embodiments of the inventive concept. 
     Referring to  FIGS.  12  and  14 A , the memory active cycle M_T act _a of the memory clock domain M_CLK_Domain may be changed depending on the type of the memory device MD connected to the memory interface  120   c . According to an exemplary embodiment of the inventive concept, when the memory device MD corresponds to a first memory device, the memory device MD may perform predetermined ready operations RO_ 1   a  and RO_ 2   a  in advance to allow the memory interface  120   c  to perform output operations D_ 1   a  and D_ 2   a  for read data in response to readout requests R 1  and R 2 . Accordingly, the memory active cycle M_T act _a of the memory clock domain M_CLK_Domain in a second period IV_ 2   a  may include data transaction cycles M_T data _ 1   a  and M_T data _ 2   a  of a period in which the data input/output operation is performed using the memory device MD and ready operation cycles M_T RO _ 1   a  and M_T RO _ 2   a  of a period in which an operation required to perform the data input/output operation is carried out by the memory device MD so as to allow the memory device MD to output the read data. A period other than the memory active cycle M_T act _a in the second period IV_ 2   a  may correspond to a memory idle cycle M_T idle _a. 
     Referring to  FIGS.  12  and  14 B , when the memory device MD corresponds to a second memory device, the memory device MD may perform more ready operations (e.g., RO_ 1   a , RO_ 1   b , RO_ 2   a , and RO_ 2   b ) than those in  FIG.  14 A  to allow the memory interface  120   c  to perform output operations D_ 1   b  and D_ 2   b  for read data in response to readout requests R 1  and R 2 . Accordingly, a memory active cycle M_T act _b of the memory clock domain M_CLK_Domain in a second period IV_ 2   b  may include data transaction cycles M_T data _ 1   b  and M_T data _ 2   b  of a period in which the data input/output operation is performed using the memory device MD and ready operation cycles M_T RO _ 1   a , M_T RO _ 1   b , M_T RO _ 2   a , and M_T RO _ 2   b  of a period in which an operation required to perform the data input/output operation is carried out by the memory device MD so as to allow the memory device MD to output the read data, and thus, the memory active cycle M_T act _b of the memory clock domain M_CLK_Domain in the second period IV_ 2   b  may have a value greater than that of the memory active cycle M_T act _a shown in  FIG.  14 A . A period other than the memory active cycle M_T act _b in the second period IV_ 2   b  may correspond to a memory idle cycle M_T idle _b. 
     As an example, assuming that the memory device MD is a DRAM, the memory device MD may perform the ready operation RO_ 1   a  that amplifies the read data using a sense amplifier included in the memory device MD to output the read data before performing the output operation D_ 1   b , and the memory device MD may perform the ready operation RO_ 1   b  that precharges memory cells from which the data are read out after performing the output operation D_ 1   b . In addition, the memory device MD may perform the ready operation RO_ 2   a  that amplifies the read data using the sense amplifier included in the memory device MD to output the read data before performing the output operation D_ 2   b , and the memory device MD may perform the ready operation RO_ 2   b  that precharges the memory cells from which the data are read out after performing the output operation D_ 2   b.    
     As described above, the DVFS module  114   c  according to the present exemplary embodiment may calculate the load to which an actual operation state of the memory is reflected by taking into account not only the data transaction cycle that is the period in which the data input/output operation is performed but also a cycle that is required depending on different ready operations according to the type of the memory device MD. 
       FIG.  15    is a flowchart of a method of performing a DVFS operation with respect to a memory clock domain according to an exemplary embodiment of the inventive concept. 
     Referring to  FIGS.  12  and  15   , the memory interface  120   c  may measure the memory active cycle M_T act , which includes the data transaction cycle of the period in which the memory interface  120   c  performs the data input/output operation using the memory device MD in response to the request from at least one of the master IPs and the ready operation cycle of the period in which the operation required to perform the data input/output operation is carried out, in a predetermined period (S 300 ). The DVFS module  114   c  may calculate the load on the memory clock domain M_CLK_Domain based on the memory active cycle M_T act  (S 310 ). The DVFS governor module  114 _ 1   c  may perform the DVFS operation on the memory clock domain M_CLK_Domain based on the load on the memory clock domain M_CLK_Domain (S 320 ). 
       FIG.  16    is a block diagram showing a computing system according to an exemplary embodiment of the inventive concept. 
     Referring to  FIG.  16   , a computing system  20  may include a plurality of master IPs  210 ,  220 ,  230 , and  240 , a RAM  250 , a ROM  260 , a memory interface  270 , a memory device  280 , and a bus  290 . The master IPs may include a CPU  210 , a graphics processing unit (GPU)  220 , a display IP  230 , and a multimedia IP  240 , but the master IPs are not limited thereto. For instance, the computing system  20  may further include various master IPs. 
     Programs and/or data stored in the RAM  250 , the ROM  260 , and the memory device  280  may be loaded into memories of the master IPs  210 ,  220 ,  230 , and  240 , if necessary. The RAM  250  may temporarily store the programs, data, or instructions. For instance, the programs and/or data may be temporarily stored in the RAM  250  in response to a control of one of the master IPs  210 ,  220 ,  230 , and  240 , or a booting code stored in the ROM  260 . The RAM  250  may be implemented by a DRAM or a static RAM (SRAM). The ROM  260  may store permanent programs and/or data. The ROM  260  may be implemented by an erasable programmable read-only memory (EPROM) or an electrically erasable programmable read-only memory (EEPROM). 
     The memory interface  270  may interface with the memory device  280  and control an overall operation of the memory device  280 . In addition, the memory interface  270  may control a data transaction between the master IPs  210 ,  220 ,  230 , and  240  and the memory device  280  via the bus  290 . For instance, the memory interface  270  may write or read the data in or from the memory device  280  in response to a request from the CPU  210 . 
     According to the present exemplary embodiment, the bus  290  may include a traffic monitoring unit  295 , and the memory interface  270 , the memory device  280 , and the traffic monitoring unit  295  may be included in the same memory clock domain M_CLK_Domain. The traffic monitoring unit  295  may measure the memory active cycle M_T act , which includes the data transaction cycle of the period in which the memory interface  270  performs the data input/output operation using the memory device  280  in response to a request from at least one of the master IPs and the ready operation cycle of the period in which an operation required to perform the data input/output operation is carried out, in the predetermined period. 
     According to an exemplary embodiment of the inventive concept, the traffic monitoring unit  295  may measure a cycle, from a time point at which the request from the at least one of the master IPs reaches the memory clock domain M_CLK_Domain to a time point at which the data input/output operation is completed, as the memory active cycle M_T act . 
     The CPU  210  performing a DVFS program may collect the memory active cycle M_T act  from the traffic monitoring unit  295 , and the CPU  210  may perform the DVFS operation on the memory interface  270  and the memory device  280  based on the memory active cycle M_T act . 
     The traffic monitoring unit  295  is included in the bus  290  as shown in  FIG.  16   , but is not limited thereto. For example, the traffic monitoring unit  295  may be located at an arbitrary position in the memory clock domain M_CLK_Domain that is able to precisely detect the time point at which the request reaches the memory interface  270  and the time point at which the data input/output operation is completed in response to the request. For example, the traffic monitoring unit  295  may be included in the memory interface  270 . 
       FIG.  17    is a block diagram showing a method of operating the computing system of  FIG.  16    according to an exemplary embodiment of the inventive concept. 
     Referring to  FIG.  17   , the GPU  220  may access the memory interface  270  to perform a graphic processing operation. In this case, the traffic monitoring unit  295  according to the present exemplary embodiment may measure the memory active cycle M_T act  by counting the cycle from the time point at which a request (Req.) to access the memory interface  270  reaches the traffic monitoring unit  295  from the GPU  220  to the time point at which the data is output to the GPU  220  from the traffic monitoring unit  295  as a response (Res.) to the request (Req.). 
     The CPU  210  may collect the memory active cycle M_T act  measured by the traffic monitoring unit  295 , and the CPU  210  may perform the DVFS operation on the memory interface  270  and the memory device  280  based on the memory active cycle M_T act . 
       FIG.  18    is a block diagram showing an application processor including multiple cores according to an exemplary embodiment of the inventive concept. 
     Referring to  FIG.  18   , an application processor  300  may include a first cluster  310 , a second cluster  320 , an internal memory  330 , a CMU  340 , a PMIC  350 , and a memory interface  360 . For convenience of explanation, each of the first cluster  310  and the second cluster  320  shown in  FIG.  18    includes four cores  312  to  318  and  322  to  328 , respectively, but the number of cores in each of the first and second clusters  310  and  320  is not limited thereto. 
     The first cluster  310  may include first, second, third, and fourth cores  312 ,  314 ,  316 , and  318 , and the second cluster  320  may include fifth, sixth, seventh, and eighth cores  322 ,  324 ,  326 , and  328 . The cores  312  to  318  included in the first cluster  310  may have a performance equal to or different from that of the cores  322  to  328  included in the second cluster  320 . Hereinafter, the application processor  300  will be described under the assumption that a calculation amount per unit time of the cores  312  to  318  included in the first cluster  310  is greater than a calculation amount per unit time of the cores  322  to  328  included in the second cluster  320 . 
     The first cluster  310  may receive a first threshold CPI TH_CPI_ 1  from the internal memory  330 , and the second cluster  320  may receive a second threshold CPI TH_CPI_ 2  from the internal memory  330 . Since the first threshold CPI TH_CPI_ 1  and the second threshold CPI TH_CPI_ 2  may have different values from each other and the performance of the cores  312  to  318  included in the first cluster  310  is better than the performance of the cores  322  to  328  included in the second cluster  320 , the first threshold CPI TH_CPI_ 1  may have a value smaller than that of the second threshold CPI TH_CPI_ 2 . 
     Each of the cores  312  to  318  of the first cluster  310  may perform the DVFS operation based on the DVFS program using the first threshold CPI TH_CPI_ 1 . In detail, each of the cores  312  to  318  may measure a core active cycle of a period in which each core executes instructions and a core idle cycle of a period in which each core is in an idle state, and may generate information on a memory access stall cycle of a period in which each core accesses the memory interface  360  in the core active cycle. Each of the cores  312  to  318  may correct the core active cycle based on the information on each memory access stall cycle and calculate a load on each core based on the corrected core active cycle. 
     In this case, the DVFS operation may be performed on the first cluster  310  based on a core having the largest load among the cores  312  to  318  included in the first cluster  310 . For instance, in a case that the load on the first core  312  is the largest among the cores  312  to  318  of the first cluster  310 , e.g., the load on the first core  312  is in a heavy load state, the DVFS operation may be performed on the first cluster  310  based on the load on the first core  312 . 
     The first cluster  310  may provide a first clock control signal CTR_CC 1  to the CMU  340  based on the load on the first core  312  and receive a first clock signal CLK_C 1  of which the frequency is scaled in response to the first clock control signal CTR_CC 1 . In addition, the first cluster  310  may provide a first power control signal CTR_CP 1  to the PMIC  350  based on the load on the first core  312  and receive a first power PW_C 1  of which the level is scaled in response to the first power control signal CTR_CP 1 . 
     Each of the cores  322  to  328  of the second cluster  320  may perform the DVFS operation based on the DVFS program using the second threshold CPI TH_CPI_ 2 . In this case, the DVFS operation may be performed on the second cluster  320  based on a core having the largest load among the cores  322  to  328  included in the second cluster  320 . For instance, in a case that the load on the sixth core  324  is the largest among the cores  322  to  328  of the second cluster  320 , e.g., the load on the sixth core  324  is in a heavy load state, the DVFS operation may be performed on the second cluster  320  based on the load on the sixth core  324 . 
     The second cluster  320  may provide a second clock control signal CTR_CC 2  to the CMU  340  based on the load on the sixth core  324  and receive a second clock signal CLK_C 2  of which the frequency is scaled in response to the second clock control signal CTR_CC 2 . In addition, the second cluster  320  may provide a second power control signal CTR_CP 2  to the PMIC  350  based on the load on the sixth core  324  and receive a second power PW_C 2  of which the level is scaled in response to the second power control signal CTR_CP 2 . 
       FIG.  19    is a block diagram showing an application processor including multiple cores according to an exemplary embodiment of the inventive concept. 
     Referring to  FIG.  19   , an application processor  400  may include a first cluster  410 , a second cluster  420 , a CMU  440 , a PMIC  450 , a memory interface  460 , and a traffic monitoring unit  470 . The first cluster  410  and the second cluster  420  have substantially the same configuration as the first cluster  310  and the second cluster  320 , respectively, shown in  FIG.  18   , and thus, detailed descriptions of the first and second clusters  410  and  420  will be omitted. The memory interface  460  and the traffic monitoring unit  470  may be included in the same memory clock domain. According to an exemplary embodiment of the inventive concept, one of cores  412  to  428  included in the first and second clusters  410  and  420  may perform the DVFS operation on the memory interface  460  based on the DVFS program. For instance, each of the cores  412  to  428  may receive a predetermined signal (or an interrupt signal) before performing the DVFS operation on the memory interface  460 , and a core that receives the signal first or responds to the predetermined signal first may be selected to perform the DVFS operation on the memory interface  460 . Hereinafter, it is assumed that the eighth core  428  of the second cluster  420  is selected to perform the DVFS operation on the memory interface  460 . 
     The eighth core  428  may collect the memory active cycle M_T act  generated by the traffic monitoring unit  470  and provide the clock control signal CTR_MC to the CMU  440  and the power control signal CTR_MP to the PMIC  450  based on the memory active cycle M_T act . The CMU  440  may provide the clock signal CLK_M having a scaled frequency to the memory interface  460  in response to the clock control signal CTR_MC, and the PMIC  450  may provide the power PW_C having a scaled level to the memory interface  460  in response to the power control signal CTR_MP. 
       FIG.  20    is a block diagram showing a communication apparatus including an application processor according to an exemplary embodiment of the inventive concept. 
     Referring to  FIG.  20   , a communication device  1000  may include an application processor  1010 , a memory device  1020 , a display  1030 , an input device  1040 , and a radio transceiver  1050 . 
     The radio transceiver  1050  may transmit or receive a radio signal through an antenna  1060 . For instance, the radio transceiver  1050  may convert the radio signal provided through the antenna  1060  to a signal that may be processed by the application processor  1010 . 
     Accordingly, the application processor  1010  may process a signal output from the radio transceiver  1050  and transmit the processed signal to the display  1030 . In addition, the radio transceiver  1050  may convert a signal output from the application processor  1010  to a radio signal and output the converted radio signal to an external device via the antenna  1060 . 
     The input device  1040  may be a device that inputs a control signal to control an operation of the application processor  1010  or data to be processed by the application processor  1010 , and may be implemented by a pointing device (such as a touch pad, a computer mouse, etc.), a keypad, or a keyboard. 
     According to an exemplary embodiment of the inventive concept, the application processor  1010  may separately perform a DVFS operation with respect to a CPU clock domain of a CPU included in the application processor  1010  and a DVFS operation with respect to a memory clock domain including a memory interface included in the application processor  1010  and the memory device  1020 . When the application processor  1010  performs the DVFS operation with respect to the CPU clock domain, the application processor  1010  may perform the DVFS operation by taking into account a memory access stall cycle of a period in which the CPU accesses the memory interface. In addition, when the application processor  1010  performs the DVFS operation with respect to the memory clock domain, the application processor  1010  may perform the DVFS operation by taking into account not only a cycle of a period in which the data is transacted, but also a cycle of a period in which an operation required to input/output the data is performed. To perform the DVFS operation, the application processor  1010  may further include a DVFS controller. 
     The communication device  1000  may further include a PMIC to provide power to various components included in the communication device  1000 . 
     While the inventive concept has been described with reference to exemplary embodiments thereof, it is to be understood by those of ordinary skill in the art that various modifications, substitutions, and equivalent arrangements may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the following claims.