Patent Publication Number: US-6987476-B2

Title: Method for matching rise and fall times of drive signals in a digital to analog converter

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. Ser. No. 10/665,618, filed Sep. 22, 2003, (now U.S. Pat. No. 6,836,234 that issued Dec. 28, 2004), which is incorporated herein by reference in its entirety. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention is related to current-switched digital to analog converters. 
   2. Background Art 
   An analog section of digital-to-analog converters (DACs) usually receives complementary drive signals that are generated using a switch driver circuit. The switch driver circuit receives digital signals and generates the drive signals therefrom. The analog section uses the received drive signals to generate analog signals representative of the digital signals. 
   Ideally, the drive signals have rise and fall times that are substantially equal (e.g., a rise time of a first drive signal is substantially equal to a fall time of a second drive signal, and vice versa). This is because matching of the rise and fall times of the drive signals is critical to linearity performance of the DAC circuit, especially when a high speed sampling clock is required. Therefore, mismatches of the rise and fall times of the drive signals should be kept as small as possible. However, conflicts between elements in the switch driver circuit typically result in some mismatch between rise and fall times of the drive signals, which often results in a mismatch that is above threshold level. 
   Therefore, what is needed is a system and method that generate drive signals having rise and fall times that are substantially equal. 
   BRIEF SUMMARY OF THE INVENTION 
   Embodiments of the present invention provide a system including a digital section and an analog section. For example, the system can be a one or more bit current-switched digital-to-analog converter (DAC), or the like. The digital section includes first and second driving devices. The first driving device has a switch and a logic gate. The first driving device is configured to receive a first digital signal and generate a first drive signal therefrom. The second driving device has a switch and a logic gate. The second driving device is configured to receive a second digital signal and generate a second drive signal therefrom. The rise and fall times of the first and second drive signals are substantially equal. The analog signal section is configured to receive the first and second drive signals and generate first and second respective analog signals therefrom. 
   Other embodiments of the present invention provide a system including a digital section and an analog section. The digital section is configured to receive digital signals and includes a system for generating first and second drive signals having substantially equal rise and fall times therefrom. The analog section is configured to receive the first and second drive signals and generate first and second analog signals therefrom. 
   Further embodiments, features, and advantages of the present inventions, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES 
     The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention. 
       FIG. 1  is a schematic diagram of one element of current-switched digital-to-analog converter (DAC) arrays. 
       FIGS. 2 ,  3 ,  4 , and  5  are schematic diagrams of various drivers in a digital section of  FIG. 1  driving switches in an analog section of the system of FIG.  1 . 
   

   The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers may indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number may identify the drawing in which the reference number first appears. 
   DETAILED DESCRIPTION OF THE INVENTION 
   Overview 
   While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present invention. It will be apparent to a person skilled in the pertinent art that this invention can also be employed in a variety of other applications. 
   Embodiments of the present invention provide a system (e.g., a current-switched digital-to-analog converter (DAC)) including a digital section and an analog section. The digital section has a driver portion that generates drive signals based on received respective digital input signals. The drive signals are received at respective switches in the analog section. The driver portion includes logic gates that are used to generate the drive signals, such that a rise and fall time of complementary pairs of drive signals are substantially equal. The driver portion can optionally include an acceleration system to accelerate the rise and fall times of the drive signals. The switches generate respective analog signals from the drive signals. 
   Current-Switched Digital to Analog Converter 
     FIG. 1  is a schematic diagram of a system  100  (e.g., one element of the current-switched digital-to-analog converter (DAC), or the like). Complementary digital signals d  102  and db  104  are received at drivers  106  and  108 , respectively. Drivers  106  and  108  generate complementary drive signals sp  110  and sn  112 , respectively, therefrom. Switches  114  and  116  (e.g., metal oxide semiconductor field effect transistors (MOSFETS) M 1  and M 2 , or any other switching device) receive drive signals sp  110  and sn  112 , respectively, at a control terminal (e.g., a gate), and generate analog signals iop  118  and ion  120 , respectively, therefrom. In the example shown, switches  114  and  116  are PMOS devices. A current source  122  is coupled between the sources of M 1   114  and M 2   116  and a power supply Vdd. 
   It is to be appreciated an array of systems  100  can be used to form a multi-bit DAC, as would be apparent to one of ordinary skill in the art. Also, although switches are shown as MOSFETS, all other known devices that can function as switches can also be used, and are contemplated within the scope of the present invention. 
   Exemplary Driver for a Switch of a DAC 
     FIG. 2  is a schematic diagram of a digital section  200  (e.g., a driver portion) that replaces drivers  106  or  108 , i.e., to produce signals sn  110  and sp  112 . Along with driver portion  200 , system  100  includes an analog section  202 . 
   Driver portion  200  includes first and second switches M 5   220  and M 6   222  that receive digital signals d  102  and db  104 , respectively, and are driven via clock signal  204  (CLK). For this description and the description of  FIGS. 3 ,  4 , and  5  below, it is assumed CLK is high so that switches M 5   220  and M 6   222  allow data flow. Driver  200  also includes switches M 3   224  and M 4   226  coupled between nodes  206  and  208 , respectively, and ground (GND). A latch  210  is also coupled between nodes  206  and  208 . Latch  210  includes inverters inv 1   212  and inv 2   214 . Driving signals sn  110  and sp  112  are output nodes  206  and  208 , respectively. There are at least two states of operation for system  100 . 
   In a first state, initially sn  110  is high, sp  112  is low. Then d  102  becomes high and db  104  becomes low, turning M 3   224  ON and turning M 4   226  OFF. When M 3   224  is ON (or active), M 3   224  begins pulling sn  110  to ground, while inv 1   212  starts pulling sp  112  high (e.g., to a power supply level). M 3   224  must compete against inv 2   214 , which tries to keep sn  110  high. In order for M 3   224  to pull sn  110  low, M 3   224  must be stronger (e.g., larger, allow more current flow, etc.) than inv 2   214 . The competition between M 3   224  and inv 2   214  can affect fall time of sn  110  and rise time of sp  112 . 
   In a second state, initially sn  110  is high, sp  112  is low. Then d  102  becomes low and db  104  becomes high, turning M 3   224  OFF and turning M 4   226  ON. When M 4   226  is ON (or active), M 4   226  begins pulling sp  112  to ground, while inv 2   214  starts pulling sn  110  high (e.g., to a power supply level). M 4   226  must compete against inv 1   212 , which tries to keep sp  112  high. In order for M 4   226  to pull sp  112  low, M 4   226  must be stronger (e.g., larger, allow more current flow, etc.) than inv 1   212 . The competition between M 4   226  and inv 1   212  can affect fall time of sp  112  and rise time of sn  110 . 
   The configuration above usually results in rise and fall times of sn  110  and sp  112  to be mismatched. For example, a rise time of sn  110  can be substantially different from a fall time of sp  112 , and vice versa. 
   These mismatches can be substantially resolved using the driver configurations in  FIGS. 3 ,  4 , and  5 . 
   Drivers for a Switch of a DAC Allowing for Substantially Matched Rise and Fall Times 
     FIG. 3  shows a schematic diagram of a driver portion  300  in system  100  according to embodiments of the present invention. In driver portion  300 , a first “driver” includes switch M 5   220  and a logic gate  302  (e.g., a NOR gate) and a second “driver” includes switch M 6   222  and a logic gate  304  (e.g., a NOR gate). The first and second “drivers” are used to generate signals sn  110  and sp  112 , respectively. Logic gate  302  receives inputs from switch M 5   220  and an output terminal of logic gate  304  (e.g., sp  112 ). Logic gate  304  receives inputs from switch M 6   222  and an output terminal of logic gate  302  (e.g., sn  110 ). 
   In this embodiment, logic gates  302  and  304  directly control rise and fall times of sn  110  and sp  112 , respectively, without the individual signals sn  110  and sp  112  having any effect on the other&#39;s signals rise and fall time. Also, no other circuit elements in driver  300  effect rise and fall times of sn  110  and sp  112 . Thus, through the configuration shown, sn  110  rise time is allowed to be substantially equal to sp  112  rise time, and vice versa. 
   Using equal strength logic gates  302  and  304  allows flexibility in design because a designer can use logic gates  302  and  304  having any value required for specific applications. For example, devices  302  and  304  can be chosen to comply with specified rise and fall times for sn  110  and sp  112 . 
     FIG. 4  is a schematic diagram of a system  100 ′ according to embodiments of the present invention. System  100 ′ includes a digital section  400  and an analog section  402 . A main difference between analog section  202  and analog section  402  is that analog section  402  replaces PMOS devices M 1   14  and M 2   116  with NMOS devices M 7   404  and M 8   408  to generate iop  408  and ion  410 , respectively. In order to adjust for this change, a current source  422  is coupled between sources of M 7   404  and M 8   408  and a ground node, and digital section  400  replaces NOR gates  302  and  304  in digital section  200  with NAND gates  412  and  414 . However, the functionality of system  100 ′ remains similar to that of system  100  described above. 
     FIG. 5  is a schematic diagram showing system  100  including digital section  300 ′ having an acceleration system  502  (e.g., a latch) according to embodiments of the present invention. Acceleration system  502  is coupled to the first and second “drivers” between nodes  508  and  510 . Acceleration system  502  includes a first inverter inv 1   504  and a second inverter inv 2   506 . First inverter inv 1   504  has its input coupled to node  508  and its output coupled to node  510 . Oppositely, second inverter inv 2   506  has an input coupled to node  510  and an output coupled to node  508 . 
   In this configuration, latch  502  pulls and pushes current through nodes  508  and  510  along with switches M 5   220  and M 6   222 . Using both latch  502  and switches M 5   220  and M 6   222  increases current flow through nodes  508  and  510 . This increase in the rate of current flow through nodes  508  and  510  accelerates rise and fall times of sn  110  and sp  112 . 
   In operation, when an application requires smaller rise and fall times than can be provided using only logic gates, acceleration system  502  can be used to meet those requirements. 
   CONCLUSION 
   While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.