Patent Publication Number: US-5894215-A

Title: Shunt voltage regulator utilizing a floating reference voltage

Description:
BACKGROUND OF THE INVENTION 
     This invention relates generally to a voltage regulator and more particularly, to a shunt voltage regulator utilizing a reference voltage generator which generates a floating output voltage with respect to the voltage of the power supply. 
     Referring to FIG. 1, there is shown a prior art shunt voltage regulator 10. In FIG. 1, a power supply V 1  generates a voltage such as 15 volts which due to temperature or load variations might have some fluctuations. In order to create a constant voltage, the shunt voltage regulator 10 is needed. In this example, in addition to regulating the voltage (creating a constant voltage), the output voltage V OUT1  is also lowered to 5 volts in order to supply a constant 5 volts to a CMOS circuitry. 
     The shunt voltage regulator 10 comprises a reference voltage generator 14, an Op-Amp 16, a Metal Oxide Silicon Field Effect Transistor (MOSFET) T 1  and two resistors R 2  and R 3 . The negative terminal of the reference voltage generator 14 is grounded and the positive terminal of the reference voltage generator 14 is connected to the inverting input (-) of the Op-Amp 16. The output of the Op-Amp 16 is connected to the gate of the of transistor T 1 . The source of transistor T 1  is grounded and the drain of transistor T 1  is connected to an output node 12. The non-inverting (+) input of the Op-Amp 16 is connected to node 12 through resistor R 2  and also grounded through resistor R 3 . In addition, the power supply V 1  is connected to the output node 12 through resistor R 1 . 
     In FIG. 1, the output voltage V OUT1  at node 12 is equal to: 
     
         V.sub.OUT1 =(R.sub.2 +R.sub.3)I.sub.1 = (R.sub.2 +R.sub.3).V.sub.3 /R.sub.3 !=(1+R.sub.2 /R.sub.3)V.sub.3. 
    
     Also, since Op-Amp 16 is used in linear mode, the voltage of the non-inventing input is set to be equal to the voltage of the inverting input which is equal to the output voltage of the reference voltage generator 14. The reference voltage generator 14 generates a reference voltage V R  of 1 volt. Therefore, both voltages of the inverting and the non inverting inputs of the Op-Amp 16 are equal to 1 volt. Therefore, since 
     
         V.sub.3 =V.sub.R, 
    
     then 
     
         V.sub.OUT1 =(1+R.sub.2 /R.sub.3)V.sub.3 =(1+R.sub.2 /R.sub.3)V.sub.R. 
    
     The above relationship indicates that the shunt voltage regulator 10 keeps the output voltage V OUT1  independent of input voltage V 1  and proportional to the reference voltage V R  from the reference voltage generator 14. The shunt voltage regulator 10 regulates the output voltage V OUT1  and compensates for any variation in the voltage of the power supply. 
     For example, if the power supply V 1  fluctuates from 15 volts to 16 volts, the output voltage V OUT1  tends to increase. Once the output voltage V OUT1  momentarily changes, the voltage of the non-inverting input of the Op-Amp 16 increases. The difference between the two inputs of the Op-Amp 16 increases the gate voltage of the transistor T 1  which in turn increases the current drawn from T 1  and R 1 . The increase in the current of T 1  and resistor R 1  will decrease the voltage of node 12. This continues until the voltage V 1  and hence the output voltage V OUT1  return back to original values. 
     By selecting proper R 2  and R 3 , a desired output voltage V OUT1  can be selected. For example in FIG. 1, R 2  and R 3  are selected to set the output voltage at node 12 to 5 volts. In this circuit, since the reference voltage V R  of the reference voltage generator 14 is temperature insensitive, the output voltage V OUT1  is also temperature insensitive. 
     Typically, shunt voltage regulators utilize reference voltage generators to create a fixed voltage at the inverting and the non-inverting inputs of the Op-Amp to generate a fixed voltage at the output node. However, due to the popularity of the CMOS process and in particular P-substrate CMOS process, it is desirable to design a reference voltage generator using bipolar transistors fabricated with P-substrate CMOS technology. Fabricating a bipolar transistor in P-substrate CMOS technology is well known in the industry. Yet, designing a reference voltage generator with bipolar transistors in P-substrate CMOS technology creates a temperature dependent reference voltage with respect to the power supply. 
     The transient variation of the voltage of the power supply causes the output of the reference voltage generator to vary (float). A typical voltage generator is designed to generate a reference voltage with respect to the ground of the integrated circuit and therefore, the voltage is substantially fixed as the power supply voltage or the temperature varies. 
     The reason a reference voltage generated by P-substrate CMOS technology has a floating voltage is that the bipolar transistors fabricated by P-substrate CMOS technology are PNP transistors. In order to generate a reference voltage with respect to the ground, NPN transistors are required which can be easily fabricated in N-substrate CMOS technology. 
     Referring to FIG. 2, there is shown a bipolar transistor 20 fabricated with P-substrate CMOS technology. In P-substrate CMOS technology, the substrate which is a P-substrate is typically connected to ground or the most negative voltage used in the integrated circuit. Therefore, in P-substrate CMOS technology, in order to create a bipolar transistor, the bipolar transistor has to be created in a well. Since the substrate is a p-substrate, the well has to be n-well which then dictates that the bipolar transistor to be a PNP transistor. In this type of configuration, n-well is used as the base B, one of the p+ regions is used as collector C and the other p+ region is used as the emitter E of the bipolar transistor 20. 
     In FIG. 2, layer 22 is an insulator and layer 24 is a material such as aluminum to be used for the gate G of a P-substrate CMOS transistor. Since the transistor 20 is used as a bipolar transistor, gate G is connected to a voltage above 5 volts which does not affect the function of bipolar transistor 20. 
     Referring to FIG. 3, there is shown a block diagram of a reference voltage generator 30 built with NPN transistors which generates a fixed 1 volt reference voltage. The reference voltage 1 volt is generated with respect to ground and since the voltage of ground is designated as zero, the output voltage V R1  of the reference voltage generator 30 is a fixed 1 volt. 
     Referring to FIG. 4, there is shown a block diagram of a reference voltage generator 40 built with PNP transistors which generates 1 volt. The reference voltage generator 40 generates a fixed 1 volt reference voltage with respect to power supply V 2  and since the voltage of the power supply V 2  is typically 5 volts, the output V R2  of the reference voltage generator 40 is 5-1=4 Volts. The output of the reference voltage generator 40 is floating since any transient change in the power supply causes the output voltage V R2  to vary. For example, if the voltage of the power supply changes to 5.2, then the output V R2  is 5.2-1=4.2 Volts. 
     Therefore, in this specification the term &#34;floating&#34; shall mean &#34;a voltage which is a fixed voltage below the voltage of a power supply and therefore follows the transient changes of the power supply&#34;. Furthermore, in this specification &#34;floating reference voltage generator&#34; shall mean a reference voltage generator which generates a floating output voltage such that the difference between the voltage of the power supply and the floating output voltage is a fixed voltage independent of temperature variations. 
     It is an object of this invention to provide a shunt voltage regulator which utilizes a floating reference voltage generator. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a shunt voltage regulator is disclosed which utilizes a reference voltage generator which generates a floating output voltage with respect to a voltage to be regulated. The floating output voltage is a fixed voltage below the voltage to be regulated. Furthermore, the shunt voltage regulator of this invention regulates the voltage to be regulated while utilizing the voltage to be regulated as a power supply to the reference voltage generator and the shunt voltage regulator. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a prior art shunt voltage regulator; 
     FIG. 2 shows a bipolar transistor fabricated in P-substrate CMOS technology; 
     FIG. 3 shows a block diagram of a reference voltage built with NPN transistors which generates a voltage with respect to ground; 
     FIG. 4 shows a block diagram of a reference voltage built with PNP transistors which generates a floating voltage with respect to the power supply; 
     FIG. 5 shows a circuit diagram of the first approach of this invention in designing a shunt voltage regulator which utilizes a floating reference voltage generator; and 
     FIG. 6 shows a circuit diagram of the preferred embodiment of the shunt voltage regulator of this invention which utilizes a floating reference voltage generator. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 5, there is shown a circuit diagram 50 of the first approach of this invention to design a shunt voltage regulator which is fabricated in P-substrate CMOS technology and utilizes a floating reference voltage generator. 
     This invention is designed for the purpose of generating and regulating a voltage V DD  such as 5 volts from a power supply V P  which generates a voltage such as 15 volts. The voltage V DD  at node 52 will be used as a 5 volts power supply for the entire circuit of the integrated circuit (micro-chip). Since the voltage V DD  is used as a power supply for the entire micro-chip, it is also connected to the power input of the reference voltage generator. If the shunt voltage regulator 50 was not present, any fluctuation of the voltage of the power supply V P  would cause the voltage V DD  to fluctuate and therefore, the power supplied to the entire micro-chip including the reference voltage generator would also fluctuate. Therefore, the shunt voltage regulator 50 has to regulate the voltage V DD  which is also the power to its reference voltage generator. 
     Hereinafter, since V DD  is the voltage that the shunt voltage regulator is regulating, it is referred to as &#34;output voltage V DD  &#34; and since node 52 is the node which provides the output voltage V DD , it is referred to as &#34;output node&#34;. 
     The shunt voltage regulator 50 comprises an Op-Amp 54, a MOSFET T 2 , two resistors R 4  and R 5  and a floating reference voltage generator 56. The non inverting input of the Op-Amp 54 is connected to the output node 52 through resistor R 4  and also connected to ground through resistor R 5 . The output of the Op-Amp 54 is connected to the gate of the transistor T 2 . The drain of the transistor T 2  is connected to the output node 52 and its source is grounded. The floating output voltage V FR  of the reference voltage generator 56 is connected to the inverting input of the Op-Amp 54. Also, in order to supply power, the output node 52 is connected to the power input P IN1  of the reference voltage generator 56 and the power input P IN2  of the to the Op-Amp 54. 
     Typically, the power supply of the reference voltage generator is independent of the voltage needed to be regulated (V DD ). However, in this invention, due to the nature of the floating reference voltage generator 56, it is necessary to utilize the output voltage V DD  of the shunt voltage regulator 50 as the power supply for the reference voltage generator 56 for the following reason. 
     The voltage of the node 58 is critical in determining the value of the output voltage V DD . A fixed voltage applied to node 58 will determine the amount of fixed current I 2  which will flow through the resistors R 4  and R 5 . The fixed current I 2 , will cause a fixed voltage drop across resistors R 4  and R 5  since node 59 is directly connected to the output node 52, this voltage drop across resistors R 4  and R 5  determines the output voltage V DD  at node 52. 
     Typically, a fixed reference voltage is used to apply a fixed voltage to node 58. However, since the reference voltage generator 56 is built in P-substrate CMOS technology, it generates a fixed floating reference voltage between its power input P IN1  and the floating voltage V FR . The Op-Amp 54 operates in linear mode and therefore, its non-inverting input has the same voltage as its inverting input. As a result, the non-inverting input has a voltage equal to V FR . Since V FR  is a floating voltage, the voltage of node 58 is not a fixed voltage which causes the voltage drop across resistor R 4  to fluctuate. The solution to provide a fixed voltage across resistor R 4  is to connect node 59 to the power input P IN1  of the reference voltage generator 56. Since for the purpose of regulating the output voltage V DD , node 52 has to be connected to node 59, the solution is to connect the output voltage V DD  as a power supply to the power input P IN1  of the reference voltage generator 56. 
     The floating reference voltage generator 56 generates a fixed voltage V REF  between the voltage of its power input P IN1  and its floating output voltage V FR  : 
     
         V.sub.REF =V.sub.DD -V.sub.FR. 
    
     V REF  is a fixed voltage regardless of the temperature variations and the fluctuations of the power supply and the floating reference voltage. In this circuit, the fixed voltage V REF  is transferred across resistor R 4 . Since the inverting and non-inverting inputs of the Op-Amp 54 have equal voltages, the voltage of the node 58 is equal to V FR  and since node 59 is connected to node 52, the voltage at node 59 is equal to the output voltage V DD . As a result, the voltage V R4  across resistor R 4  is the difference between the output voltage V DD  and the floating reference voltage V FR  : 
     
         V.sub.R4 =V.sub.DD -V.sub.FR =V.sub.REF. 
    
     Therefore, the voltage V R4  across R 4  is a fixed voltage. 
     The fixed voltage V REF  across resistor R 4  generates a fixed current I 2  which causes a fixed voltage drop across the two resistors R4 and R5 which determines the output voltage V DD . If the voltage of the power supply V P  fluctuates, any excess current generated by the fluctuation of the voltage of the power supply V P  will flow through transistor T 2 . The function of transistor T 2  will be described in more detail in the description of FIG. 6. 
     However, circuit 50 of FIG. 5 is not a proper solution. Typically the output voltage V FR  of the floating reference voltage generator 54 is about 4 volts and due to the input common mode range limitation of the Op-Amps, a 4 volts voltage can not be connected to any one of the inputs of Op-Amp 54. 
     Referring to FIG. 6, there is shown a circuit 60 which is an improved version of circuit 50 of the FIG. 5. In FIG. 6, all the elements that are the same and serve the same purpose as the elements of circuit 50 of FIG. 5 are designated by the same reference numerals. 
     In FIG. 6, the output voltage V FR  from the reference voltage generator 56 is connected to the non-inverting input of the Op-Amp 54 through an n-channel MOSFET (NMOS) T 3 . Transistor T 3  is used as a level shifter to lower the voltage V FR  to match the input requirement of the Op-Amp 54. The voltage V FR  is connected to the gate of transistor T 3 , the source of transistor T 3  is connected to the non-inverting input of the Op-Amp 54 and the drain of transistor T 3  is connected to the output voltage V DD . 
     Transistor T 3  shifts down its gate voltage V G3  by its gate to source voltage V GS3  to its source voltage V S3 . Therefore, the source voltage V S3  or the shifted down voltage is: 
     
         V.sub.S3 =V.sub.FR(shifted down) =V.sub.G3 -V.sub.GS3 
    
     and since 
     
         V.sub.G3 =V.sub.FR, 
    
     then 
     
         V.sub.S3 =V.sub.(-) =V.sub.FR(shifted down) =V.sub.FR -V.sub.GS3. 
    
     Since the Op-Amp 54 works in the linear mode due to the negative feedback, the inverting and non inverting inputs of the Op-Amp 54 have equal voltages. Thus, the voltage V.sub.(+) of the non-inverting input of the Op-Amp 54 is: 
     
         V.sub.(+) =V.sub.(-) =V.sub.FR(shifted down) =V.sub.FR -V.sub.GS3. 
    
     In circuit 50 of FIG. 5, node 58 needs to have a voltage equal to V FR . For the same reason, the voltage of node 62 has to be equal to V FR . Therefore, the voltage of the non-inverting input of the Op-Amp 54 has to be shifted up to its original value of the V FR  prior to its connection to node 62. However, the level shifting has to be highly precise to substantially restore the value of the V FR . 
     In order to have a precise level shift up, a NMOS transistor T 4  is utilized. The source of transistor T 4  is connected to the inverting input of the Op-Amp 54, its gate is connected to node 62 and its drain is connected to the output voltage V DD . The voltage of the gate of transistor T 4  is: 
     
         V.sub.G4 =V.sub.S4 +V.sub.GS4. 
    
     Since the voltage of the source of the transistor T 4  is equal to the voltage of the inverting input of the Op-Amp 54 which is equal to the shifted down V FR (Shifted down), then: 
     
         V.sub.G4 =V.sub.FR(Shifted down) +V.sub.GS4. 
    
     Substituting V FR  -V GS3  for V FR (Shifted down), 
     
         V.sub.G4 =V.sub.FR -V.sub.GS3 +V.sub.GS4. 
    
     In order to have a precise level shift up, V GS3  and V GS4  have to be substantially equal to cancel each other. To provide equal V GS3  and V GS4 , the two transistors, T 3  and T 4  are selected to be NMOS to have similar properties and they are placed close to each other on the layout of the integrated circuit to receive similar process. Furthermore, the current flowing through the transistors T 3  and T 4  have to be identical. Therefore, a current mirror 64 is used to provide identical currents for transistors T 3  and T 4 . 
     The current mirror 64 has three MOSFET transistors T 5 , T 6  and T 7 . The gates of transistors T 5 , T 6  and T 7  are connected to each other and the sources of transistors T 5 , T 6  and T 7  are grounded. The drain of transistor T 5  is connected to the source of transistor T 4  and the drain of transistor T 6  is connected to the source of transistor T 3 . The drain of transistor T 7  is connected to its gate and also to the output voltage V DD  through resistor R 7 . In the current mirror 64, the current I 5  of the drain of transistor T 5  and the current I 6  of the drain of transistor T 6  are identical to the current I 7  of the drain of the transistor T 4 . Therefore, the two currents I 5  and I 6  flowing through the two transistors T 4  and T 3  are equal. 
     By designing the two transistors T 3  and T 4  identical and keeping their currents the same, the gate to source voltages V GS3  and V GS4  will be substantially the same. As a result, the shifted up voltage V FR  &#39; at the gate of transistor T 4  will be substantially equal to V FR  which in turn keeps the voltage across resistor R 4  fixed: 
     
         V.sub.DD -V.sub.FR &#39;=V.sub.DD -V.sub.FR =V.sub.REF (fixed voltage) 
    
     Therefore, the output voltage V DD  will be set to a fixed voltage: 
     
         V.sub.DD =(R.sub.4 +R.sub.5)I.sub.2 
    
     where 
     
         I.sub.2 =(V.sub.DD -V.sub.FR &#39;)/R.sub.4 =V.sub.REF /R.sub.4 
    
     Therefore, 
     
         V.sub.DD =(R.sub.4 +R.sub.5)V.sub.REF /R.sub.4 =(1+R.sub.5 /R.sub.4)V.sub.REF. 
    
     In this circuit, since V REF  is typically around 1 volt, in order to generate a desired value for V DD , the proportion between the two resistors R4 and R5 has to be equal to: 
     R5/R4=a desired value for V DD  -1. 
     For example if V DD  needs to be 5 volts, then the ratio of R 5  to R 4  has to be: 
     
         5-1=4. 
    
     So, by selecting R 5  to be 4 times larger than R 4 , a V DD  of 5 volts can be generated: 
     
         V.sub.DD =(1+4)V.sub.REF =5 when V.sub.REF =1 volt. 
    
     In addition, transistor T 2  is selected to be large enough to accommodate any excess current generated by the fluctuations of the voltage of the power supply V P  or by the fluctuations in the load current (the current drawn by the circuitry connected to V DD ). 
     In operation, if the voltage of the power supply V P  increases for example from 15 volts to 16 volts, the voltage of V DD  also momentarily increases for example from 5 volts to 5.2 volts. Circuit 60 is designed in such a manner that voltage of node 62 is substantially equal to V FR  when V DD  is substantially 5 volts. However, once V DD  increases, the proportion of R 4  /R 5  causes the voltage of node 62 to be slightly lower than V FR . The difference between V FR  and the voltage of node 62 will be transferred to the inputs of Op-Amp 54 which causes the output voltage of the Op-Amp 54 to increase and hence increase the current of transistor T 2  and current of resistor R 6 . More current in resistor R 6  causes the voltage of V DD  to decrease. This trend continues until the voltage of V DD  returns back to its original value (desired value) where the inverting input voltage of Op-Amp 54 becomes equal to the non-inverting input voltage of the Op-Amp 54. 
     Similarly if the voltage V P  of the power supply decreases or the load current (the current drawn by the circuitry connected to V DD ) changes, the shunt voltage regulator 60, returns the momentarily changed V DD  back to its original value (desired value). Therefore, the shunt voltage regulator of this invention regulates any voltage changes in V DD  due to the variations in the voltage of the power supply or the load current. Therefore, the output voltage stays constant regardless of the fluctuations of the voltage of the power supply. 
     Also, since the output voltage V DD  is equal to: 
     V DD  =(1+R 5  /R 4 ) V REF  and since V REF  is temperature independent, thus the output voltage V DD  is also temperature independent. 
     In conclusion, the disclosed embodiment of this invention utilizes a temperature independent floating reference voltage generator to provide a temperature independent and regulated output voltage V DD  from an unregulated and temperature sensitive power supply. 
     It should be noted that circuits 50 and 60 can be built as a stand alone circuit to be used in conjunction with a floating reference voltage generator or each can be built as an integrated circuit in conjunction with a floating reference voltage generator on a common substrate. 
     It should further be noted that numerous changes in details of construction and the combination and arrangement of elements may be resorted to without departing from the true spirit and scope of the invention as hereinafter claimed.