Patent Publication Number: US-10777505-B2

Title: Method of fabricating integrated circuit having staggered conductive features

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This is a Divisional Application of U.S. application Ser. No. 15/171,862, filed on Jun. 2, 2016, which is herein incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     Computer-aided cell-based design has been developed for designing large scale ICs such as application specific integrated circuits (ASICs) and gate arrays. The cell is a circuit that has been pre-designed and pre-verified as a building block. In a standard cell design, each distinct cell in a library may have geometries of active, gate, and metal levels. Examples of a standard cell or gate array cell include an inverter, a NAND gate, a NOR gate, a flip flop, and other similar logic circuits. 
     Integrated circuit design includes two steps: placement and routing. During the placement step, the positions and orientations of cells are determined. During the routing step, interconnects or conductive features are added to connect ports on the cells. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1A  to  FIG. 1C  respectively are schematic top views of different stages of a method of designing a cell layout having staggered conductive features in accordance with some embodiments of the present disclosure. 
         FIG. 2  is a schematic top view of a cell in accordance with some embodiments of the present disclosure. 
         FIG. 3A  and  FIG. 3B  respectively are schematic top views of different stages of a method of designing a cell layout having staggered conductive features in accordance with some embodiments of the present disclosure. 
         FIG. 4A  to  FIG. 4C  respectively are schematic top views of cell layouts in accordance with different embodiments of the present disclosure. 
         FIG. 5  is a schematic top view of an integrated circuit in accordance with some embodiments of the present disclosure. 
         FIG. 6  is a schematic top view of an integrated circuit in accordance with some other embodiments of the present disclosure. 
         FIG. 7A  to  FIG. 7C  respectively are schematic views of different steps of a method of fabricating a cell in accordance with some embodiments of the present disclosure. 
         FIG. 8  is a processing system to generate one or more of the above described layout embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Reference is made to  FIG. 1A  to  FIG. 1C , which respectively are schematic top views of different stages of a method of designing a cell layout having staggered conductive features in accordance with some embodiments of the present disclosure. The designing method begins from  FIG. 1A , in which a cell layout  100 , such as a layout of a standard cell, is obtained from a cell library. The cell layout  100  has a boundary  110 . The boundary  110  is substantially in a shape of rectangular. The boundary  110  includes a top edge  112 , a bottom edge  114 , and opposite side edges  116  and  118 . A cell height H is defined between the top edge  112  and the bottom edge  114 . (Note that while the top edge  112  of the boundary  110  is depicted facing upwards in the figures, rotating the cell layout  100  does not change the functions and relative positions of the elements shown. As depicted in the figures, the bottom edge  114  of the boundary  110  is shown oriented facing downwards; however, this does not change which portion is the bottom edge  114 , even when the orientation is different.) 
     The cell layout  100  includes a plurality of standard conductive features  120  defined within the boundary  110 . In some embodiments, the standard conductive features  120  are arranged substantially parallel to each other and are arranged substantially equally spaced apart. For example,  FIG. 1A  illustrates four standard conductive features  120  defined within the boundary  110  of the cell layout  100 . In some other embodiments, the number of the standard conductive features  120  may vary according to different design requirements. A distance between adjacent standard conductive features  120  may be determined according to the design rule. 
     In some embodiments, the standard conductive features  120  have substantially the same length L 1 . The standard conductive features  120  may be aligned with each other. That is, the standard conductive features  120  are arranged at substantially the same level. As shown in  FIG. 1A , top ends  122  of the standard conductive features  120  are aligned with a line LT, and bottom ends  124  of the standard conductive features  120  are aligned with a line LB. 
     In some embodiments, the standard conductive features  120  are for 5-pitch conductive feature routing, which refers to each of the standard conductive features  120  having five access points. The access point is a position where a conductive feature (e.g., a metal-2 line) can be connected to another conductive feature (e.g., a metal-1 line). The number of the access points plays a role to determine the routing ability, such as routing density and routing flexibility. 
     Reference is made to  FIG. 1B . The standard conductive features  120  of  FIG. 1A  are shrunk and become shrunk standard conductive features  120 ′. As shown in  FIG. 1B , the shrunk standard conductive features  120 ′ are shortened. Thus, a distance between the top edge  122  and the bottom edge  124  of at least one of the shrunk standard conductive features  120 ′ is smaller than a distance between the line LT and the line LB. The shrunk standard conductive features  120 ′ are present within a space between the line LT and the line LB. Therefore, some extra spaces are created by shrinking the standard conductive features  120  of  FIG. 1A . In some embodiments, the shrunk standard conductive features  120 ′ still have substantially the same length L 2 , in which the length L 2  of the shrunk standard conductive features  120  is smaller than the length L 1  (as shown in  FIG. 1A ) of the standard conductive features  120  (as shown in  FIG. 1A ). 
     Reference is made to  FIG. 1C . Upper extension portions  126  and lower extension portions  128  are respectively added to the shrunk standard conductive features  120 ′. In some embodiments, each of the shrunk standard conductive features  120 ′ is added with an extension portion, such as the upper extension portions  126  and the lower extension portions  128 . As shown in  FIG. 1C , the upper extension portions  126  are added to some of the shrunk standard conductive features  120 ′, and the lower extension portions  128  are added to the other shrunk standard conductive features  120 ′. The shrunk standard conductive features  120 ′ added with the lower extension portions  128  are referred to herein as first conductive features  130 . The shrunk standard conductive features  120 ′ added with the upper extension portions  126  are referred to herein as second conductive features  140 . 
     In some embodiments, the first conductive features  130  and second conductive features  140  have substantially the same length L 3 . The length L 3  of the first conductive features  130  and second conductive features  140  can be similar to the length L 1  of the standard conductive features  120  (as shown in  FIG. 1A ) or be longer than or shorter than the length L 1  of the standard conductive features  120  (as shown in  FIG. 1A ). The length L 3  of the first conductive features  130  and second conductive features  140  is smaller than the cell height H of the boundary  110 . 
     In some embodiments, the first conductive feature  130  can be present closer to the bottom edge  114  of the boundary  110 , and the second conductive feature  140  can be present closer to the top edge  112  of the boundary  110 . That is, a first distance d 1  from the top ends  132  of the first conductive features  130  to the top edge  112  of the boundary  110  is greater than a second distance d 2  from the top ends  142  of the second conductive features  140  to the top edge  112  of the boundary  110 . A third distance d 3  from the bottom ends  134  of the first conductive features  130  to the bottom edge  114  of the boundary  110  is less than a fourth distance d 4  from the bottom ends  144  of the second conductive features  140  to the bottom edge  114  of the boundary  110 . In some embodiments, the first conductive feature  130  is protruded from the bottom end  144  of the second conductive feature  140  since the second conductive feature  140  is protruded from the top end  132  of the first conductive features  130 . In some embodiments, both the top end  132  and the bottom end  134  of each first conductive feature  130  are located within the boundary  110 , and both the top end  142  and the bottom end  144  of each second conductive feature  140  are located within the boundary  110 . 
     Reference is made to both  FIG. 1A  and  FIG. 1C . The first conductive features  130  and the second conductive features  140  are staggered, such that the capacity between the conductive features formed according a layout including the first conductive features  130  and the second conductive features  140  is smaller that between the conductive features formed according to the layout including the standard conductive features  120 . 
     Referring to  FIG. 2 , which is a schematic top view of a cell in accordance with some embodiments of the present disclosure. The cell  200  is fabricated according to the cell layout  100  designed as discussed from  FIG. 1A  to  FIG. 1C . The cell  200  includes a boundary  210 , at least one first conductive feature  220 , and at least one second conductive feature  230 . The boundary  210  has a top edge  212 , a bottom edge  214 , and opposite side edges  216 ,  218 . 
     The first conductive features  220  and the second conductive features  230  are arranged parallel to each other in the boundary  210 , and the first conductive features  220  and the second conductive features  230  are staggered. In some embodiments, the first conductive features  220  and the second conductive features have substantially the same length. The first conductive features  220  and the second conductive features  230  are made of a conductive material. In some embodiments, the first conductive features  220  and the second conductive features  230  are made of metal, such as copper, tungsten, aluminum, or combinations thereof. The first conductive features  220  and the second conductive features  230  are linear-shaped. 
     In some embodiments, the first conductive features  220  and the second conductive features  230  are alternately arranged. Each of the first conductive features  220  is disposed between two of the second conductive features  230 . Each of the second conductive features  230  is disposed between two of the first conductive features  220 . The first conductive features  220  and the second conductive features  230  are staggered when viewed from the top. In some other embodiments, the sequence of the first conductive features  220  and the second conductive features  230  is not alternating. 
     In some embodiments, each of the first conductive features  220  has a first main portion  226  and a first extension portion  228 , and each of the second conductive features  230  a second main portion  236  and a second extension portion  238 . Ends (e.g. the top ends  222 ) of the first conductive features  220  have projections on the second conductive features  230 , and the second extension portions  238  of the second conductive features  230  protrude from the projections of the ends of the first conductive features  220  on the second conductive features  230 . Ends (e.g. the bottom ends  234 ) distal to the second extension portions  238  of the second conductive features  230  have projections on the first conductive feature  220   s , and the first extension portions  228  distal to the ends (e.g. the top ends  222 ) of the first conductive features  220  protrude from the projections of the ends of the second conductive features  230  on the first conductive features  220 . 
     The number of the access points provided by the cell  200  can be increased by inducing the extension portions  228  and  238 . For example, each of the first conductive features  220  may have five access points, and each of the second conductive features  230  may have five access points. Since the first conductive features  220  are arranged closer to the bottom edge  214 , and the second conductive features  230  are arranged closer to the top edge  212  in the cell  200 , the parts of the first conductive features  220  protruding from the second conductive features  230 , such as the first extension portions  228 , and the parts of the second conductive features  230  protruding from the first conductive features  220 , such as the second extension portions  238 . Such arrangement may increase the number of access points. 
     For example, each first main portion  226  may have four access points, and each first extension portion  228  may have one access point. Each second main portion  236  may have four access points, and each second extension portion  238  may have one access point. Therefore, the cell  200  provides six-pitch access points (e.g. including one access point provided by each first extension portion  228 , four access points provided by each first (second) main portion  226  ( 236 ), and one access point provided by each second extension portion  238 ), which is more than the number of the access points of each first conductive feature  220  or each second conductive feature  230  itself. 
     Reference is made to  FIG. 3A  and  FIG. 3B , which respectively are schematic top views of different stages of a method of designing a cell layout having staggered conductive features in accordance with some embodiments of the present disclosure. The method begins at  FIG. 3A , in which a cell layout  300 , such as a layout of a standard cell, is obtained from a cell library. The cell layout  300  has a boundary  310  and a plurality of standard conductive features  320   a - 320   f  present within the boundary  310 . In some embodiments, the standard conductive features  320   a - 320   f  in the cell layout  300  may have different lengths respectively. For example, the standard conductive features  320   a  may have a longest length among the standard conductive features  320   a - 320   f , and the standard conductive feature  320   e  may have a shortest length among the standard conductive features  320   a - 320   f . In some embodiments, at least two of the standard conductive features  320   a - 320   f , e.g. the standard conductive features  320   c  and  320   f  may have substantially the same length. In some embodiments, the standard conductive features  320   a - 320   f  are not aligned with each other, i.e. the standard conductive features  320   a - 320   f  are staggered arranged in the cell layout  300 . 
     Referring to  FIG. 3B , at least one extension portion  330  is added to at least one of the standard conductive features  320  according to a desired routing layout. The extension portions  330  are added to some of the standard conductive features  320  to provide additional access points at positions to where metal-2 lines are connected. For example, a top extension portion  330   a  is added to the standard conductive feature  320   a , a bottom extension portion  330   b  is added to the standard conductive feature  320   b , and a bottom extension portion  330   e  is added to the standard conductive features  320   e . The length of each of the extension portions  330  can be the same or different. Since the length, the position, and the number of the extension portions  330  may vary according to the desired routing layout, the design flexibility and routing efficiency can be increased accordingly. 
     In some embodiment, the conductive features  340   a - 340   f  including the standard conductive features  320   a - 320   f  and the corresponding extension portions  330   a ,  330   b , and  330   e  are located within the boundary of the cell layout  300 . The conductive features  340   a - 340   f  are arranged between the top edge  312  and the bottom edge  314  of the cell layout  300 . In some embodiments, the conductive features  340   a - 340   f  are arranged parallel and are substantially equally spaced apart from each other. In some embodiments, the length of each of the conductive features  340   a - 340   f  can be different, and the conductive features  340   a - 340   f  are not aligned with each other. In some embodiments, the conductive features  340   a - 340   f  may be arranged in a staggered manner. Therefore, the capacitance present between the adjacent conductive features  340   a - 340   f  can be reduced accordingly. 
     Reference is made to  FIG. 4A  to  FIG. 4C , which respectively are schematic top views of a cell layout in accordance with different embodiments of the present disclosure. For example, the cell layout  400   a  includes six conductive features  421   a - 426   a  sequentially arranged in the boundary  410 , as shown in  FIG. 4A . In some embodiments, the conductive features  421   a - 426   a  have substantially the same length, and the conductive features  421   a - 426   a  are in a parallel arrangement. The conductive features  421   a - 426   a  may respective include a main portion  430  and a top extension portion  432  or a bottom extension portion  434 . In some embodiments, the main portions  430  are arranged at the same level and have substantially the same length. The top extension portion  432  and the bottom extension portion  434  are selectively added to the corresponding main portions  430  according to the desired routing layout. As a result, some of the conductive features  421   a - 426   a  are protruded from others. For example, the conductive features  421   a  and  424   a  are present closer to the top edge  412  of the boundary  410 , and top portions of the conductive features  421   a  and  424   a  are protruded from other conductive features (e.g. conductive features  422   a ,  423   a ,  425   a , and  426   a ). Namely, the conductive features  422   a ,  423   a ,  425   a , and  426   a  are present closer to the bottom edge  414  of the boundary  410 , and the bottom portion of the conductive features  422   a ,  423   a ,  425   a , and  426   a  are protruded from other (e.g. the conductive features  421   a  and  424   a ). 
     In some other embodiment, such as the cell layout  400   b  in  FIG. 4B , the cell layout  400   b  includes six conductive features  421   b - 426   b  sequentially arranged in the boundary  410 . In some embodiments, the cell layout  400   b  is a standard cell obtained from a cell library, and the staggered conductive features  421   b - 426   b  are original conductive features in the cell layout  400   b.    
     In yet other embodiments, the conductive features are randomly arranged in the boundary, as shown in  FIG. 4C . The cell layout  400   c  may have six conductive features  421   c - 426   c  sequentially arranged in the boundary  410  in a parallel arrangement. The conductive features  421   c - 426   c  may have different lengths, and the conductive features  421   c - 426   c  may be arranged at different levels. In some embodiments, at least one of the conductive features  421   c - 426   c  extends across the edge of boundary  410 . For example, the bottom portion of the conductive feature  424   c  extends across the bottom edge  414  of the boundary  410 , and the top portion of the conductive feature  425   c  extends across the top edge  412  of the boundary  410 . In some embodiments, the cell layout  400   c  is a standard cell obtained from a cell library, and the staggered conductive features  421   c - 426   c  are original conductive features in the cell layout  400   c.    
     It is to be understood that the embodiments discusses from  FIG. 4A  to  FIG. 4C  are by examples, such that those skilled in the art can better understand the detailed description that follows. Those skilled in the art can readily use the present disclosure as a basis for designing or modifying other processes and structures. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure. 
     Reference is made to  FIG. 5 , which is a schematic top view of an integrated circuit in accordance with some embodiments of the present disclosure. The integrated circuit  500  includes a plurality of cells. For example, the integrated circuit  500  includes a first cell  510  and a second cell  550 . The second cell  550  is abutted vertically on the first cell  510 . In some embodiments, the first cell  510  and the second cell  550  have substantially the same layout. 
     The first cell  510  has a first boundary  520 , a plurality of first conductive features  530 , and a plurality of second conductive features  540 . The first boundary  520  has a first top edge  522  and a first bottom edge  524  for defining a cell height therebetween. The first conductive features  530  and the second conductive features  540  are disposed in the first boundary  520 . The first conductive features  530  and the second conductive features  540  have the same length. The first conductive features  530  are arranged closer to the first top edge  522  since the second conductive features  540  are arranged closer to the first bottom edge  524 . 
     The second cell  550  includes a second boundary  560 , a plurality of third conductive features  570 , and a plurality of fourth conductive features  580 . The second boundary  560  has a second top edge  562  and a second bottom edge  564  for defining the cell height there between. The second bottom edge  564  overlaps the first top edge  522 . Namely, a common boundary between the first cell  510  and the second cell  550  can be regarded as both the second bottom edge  564  and the first top edge  522 . The third conductive features  570  and the fourth conductive features  580  are disposed in the second boundary  560 . The third conductive features  570  and the fourth conductive features  580  have the same length. The third conductive features  570  are arranged closer to the second top edge  562  since the fourth conductive features  580  are arranged closer to the second bottom edge  564 . 
     The first conductive features  530 , the second conductive features  540 , the third conductive features  570 , and the fourth conductive features  580  are in a shape of rectangular. The first conductive features  530 , the second conductive features  540 , the third conductive features  570 , and the fourth conductive features  580  are in a parallel arrangement. 
     In some embodiments, the first conductive features  530  may extend across the first top edge  522 , and the second conductive features  540  may extend across the first bottom edge  524 . The third conductive features  570  may extend across the second top edge  562 , and the fourth conductive features  580  may extend across the second bottom edge  564 . The distance d 3 ′ from the second bottom edge  564  to the bottom ends  574  of the third conductive features  570  is greater than the distance d 1 ′ from the top ends  532  of the first conductive features  530  to the first top edge  522 , such that the third conductive features  570  are spaced from the first conductive features  530 . The distance d 2 ′ from the top ends  542  of the second conductive features  540  to the first top edge  522  is greater than the distance d 4 ′ from the second bottom edge  564  to the bottom ends  584  of the fourth conductive features  580 , such that the second conductive features  540  are spaced from the fourth conductive features  580 . 
     In some embodiments, the first conductive features  530 , the second conductive features  540 , the third conductive features  570 , and the fourth conductive features  580  can be original conductive features from the standard cell stored in the cell library. In some other embodiments, the first conductive features  530 , the second conductive features  540 , the third conductive features  570 , and the fourth conductive features  580  can include main portions and extension portions, in which the main portion can be standard conductive features from the standard cell or shrunk standard conductive features. The number, the ratio, and the arrangement of the first conductive features  530 , the second conductive features  540 , the third conductive features  570 , and the fourth conductive features  580  may vary according to different design rules and different requirements. 
     Reference is made to  FIG. 6 , which is a schematic top view of an integrated circuit in accordance with some other embodiments of the present disclosure. The integrated circuit, such as the integrated circuit  500  as discussed in  FIG. 5 , further includes a plurality of lateral conductive features  600   a - 600   c  and conductive vias  610   a - 610   d  for interconnecting the lateral conductive features  600   a - 600   d  and the conductive features  530 ,  540 ,  570 , and  580 . The layout of the lateral conductive features  600   a - 600   d  and the conductive vias  610   a - 610   d  can be design by tools, such as by electronic design automation (EDA) tools. The first conductive features  530 , the second conductive features  540 , the third conductive features  570 , and the fourth conductive features  580  are present in metal one lines. The lateral conductive features  600   a - 600   d  are present in metal two lines. 
     The lateral conductive feature  600   a  is utilized to interconnect at least two of the second conductive features  540  at the extension portions of the second conductive features  540  (e.g. the portions of the second conductive features  540  protruding from the first conductive features  530 ). The extension portions of the second conductive features  540  and the lateral conductive features  600   a  are cross at the conductive vias  610   a , and the conductive vias  610   a  electrically connected the second conductive features  540  to the lateral conductive feature  600   a . In some embodiments, the lateral conductive features  600   b  interconnects at least any two of the first conductive features  530  and the second conductive features  540 , for example, the first conductive features  530  and the lateral conductive features  600   b  are cross at the conductive vias  610   b , and the conductive vias  610   b  electrically connected the first conductive features  530  to the lateral conductive feature  600   b . The lateral conductive feature  600   c  is utilized to interconnect at least any two of the third conductive features  570  and the fourth conductive features  580 , for example, one of the third conductive features  570  and the one of the fourth conductive features  580  are respectively cross the lateral conductive features  600   c  at the conductive vias  610   c , and the conductive vias  610   c  electrically connected the third conductive feature  570 , the fourth conductive feature  580 , and the lateral conductive feature  600   c . The lateral conductive feature  600   d  is utilized to interconnect at least two of the third conductive features  570  at the extension portions of the third conductive features  570  (e.g. the portions of the third conductive features  570  protruding from the fourth conductive features  580 ). The extension portions of the third conductive features  570  and the lateral conductive features  600   d  are cross at the conductive vias  610   d , and the conductive vias  610   d  electrically connected the third conductive features  570  to the lateral conductive feature  600   d.    
     In some embodiments, the length of the protruding portions of the conductive features  530 ,  540 ,  570 ,  580  are greater than or equal to a pitch P between adjacent two of the lateral conductive features  600   a - 600   d . The pitch P can be regarded as the minimum distance between wires of layers above the pin layer, such as the center line of  610   d  and the center line of  610   c . In some embodiments, the pitch P is not greater than 64 nm. In some embodiments, the distance d 5  between the bottom ends of the third conductive features  570  and the top ends of the second conductive features  540  is greater than or equal to a sum of the gap g between the first conductive features  530  and the third conductive features  570  and the pitch P between the conductive feature  600   d  and conductive feature  600   e , e.g., d 5 ≥(g+P). 
     However, the cell layouts of integrated circuit are only by examples, those skilled in the art can realize that other cell layouts, such as cell layouts discussed in  FIG. 3A ,  FIG. 4A  to  FIG. 4C , or any other suitable cell layouts having staggered conductive feature arrangement, can be utilized in the integrated circuit for providing extra routing resources and improving routing flexibility. 
     Reference is made to  FIG. 7A  to  FIG. 7C , in which  FIG. 7A  to  FIG. 7C  respectively are schematic views of different steps of a method of fabricating a cell in accordance with some embodiments of the present disclosure. Referring to  FIG. 7A , a cell layout is provided. For easily understanding, the cell layout  700  is designed as described from  FIG. 1A  to  FIG. 1C , for example. In some embodiments, two masks are utilized for fabricating the conductive features since the distance between the conductive features is tiny. For example, in  FIG. 7B , a first mask is utilized for fabricating the odd rows (or the even rows) of the conductive features  710 . After the odd rows (or the even rows) of conductive features  710  are formed, a second mask is utilized for fabricating the even rows (or the odd rows) of the conductive features  710 , as shown in  FIG. 7C . 
     Referring to  FIG. 8 , which is a processing system to generate one or more of the above described layout embodiments. Processing system  800  includes a processor  802 , which may include a central processing unit, an input/output circuitry, a signal processing circuitry, and a volatile and/or a non-volatile memory. Processor  802  receives input, such as user input, from input device  804 . The input device  804  may include one or more of a keyboard, a mouse, a tablet, a contact sensitive surface, a stylus, a microphone, and the like. The processor  802  may also receive input, such as standard cells, cell libraries, models, and the like, from a machine readable permanent storage medium  808 . The machine readable permanent storage medium may be located locally to the processor  802 , or may be remote from the processor  802 , in which communications between the processor  802  and the machine readable permanent storage medium  808  occur over a network, such as a telephone network, the Internet, a local area network, wide area network, or the like. The machine readable permanent storage medium  808  may include one or more of a hard disk, magnetic storage, optical storage, non-volatile memory storage, and the like. Included in the machine readable permanent storage medium  808  may be database software for organizing data and instructions stored on the machine readable permanent storage medium  808 . The processing system  800  may include an output device  806 , such as one or more of a display device, speaker, and the like for outputting information to a user. As described above, the processor  802  generates a layout for an integrated circuit. The layout may be stored in the machine readable permanent storage medium  808 . One or more integrated circuit manufacturing machines, such as a photomask generator  810  may communicate with the machine readable permanent storage medium  808 , either locally or over a network, either directly or via an intermediate processor such as processor  802 . In some embodiments, the photomask generator  810  generates one or more photomasks to be used in the manufacture of an integrated circuit, in conformance with a layout stored in the machine readable permanent storage medium  808 . 
     The conductive features are not arranged at the same level in the cell, in which some of the conductive features have portions protruding from other conductive features, such that the access points of cell can be increased since the extension portions of the conductive features can be regarded as extra access points. 
     According to some embodiments of the present disclosure, a method includes using a processor to placing a cell having a first conductive feature and a second conductive feature on an integrated circuit layout. A length of the first conductive feature is extended, by using the processor, to form a staggered configuration. A set of instructions for manufacturing an integrated circuit based upon the integrated circuit layout is generated, and the set of instructions is stored in a non-transitory machine readable storage medium. 
     According to some embodiments, a method includes using a processor to place a cell having a first conductive feature and a second conductive feature on an integrated circuit layout. The lengths of the first conductive feature and the second conductive feature are shrunk, by using the processor. The first conductive feature is configure, by using the processor, such that a first edge of the first conductive feature is not aligned with a first edge of the second conductive feature. An integrated circuit based on the integrated circuit layout is fabricated. 
     According to some embodiments, a method includes using a processor to place a cell having a first conductive feature and a second conductive feature on an integrated circuit layout. The first conductive feature is configured, by using the processor, such that the first conductive feature is across a first edge of the cell. A set of instructions for manufacturing an integrated circuit based upon the integrated circuit layout is generated, and the set of instructions is stored in a non-transitory machine readable storage medium. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.