Patent Publication Number: US-9837331-B1

Title: Semiconductor device having overlapped via apertures

Description:
The present application is a continuation of U.S. patent application Ser. No. 14/028,290, filed Sep. 16, 2013, and titled “SEMICONDUCTOR DEVICE HAVING OVERLAPPED VIA APERTURES”; which is a continuation of U.S. patent application Ser. No. 12/959,911, filed Dec. 3, 2010, and titled “SEMICONDUCTOR DEVICE HAVING OVERLAPPED VIA APERTURES”; the contents of each of which are hereby incorporated herein by reference in their entirety. 
    
    
     TECHNICAL FIELD 
     The present application relates to a semiconductor device having an overlapped via aperture. 
     BACKGROUND 
     In order to integrate a logic device including a baseband, application, an image processor, and the like, and a high performance memory of a mobile product such as a smart phone handset or a digital camera, a package-on-package (PoP) has come into the spotlight. One exemplary PoP is generally constructed such that a logic device is implemented on a printed circuit board by wire bonding or flip chip bonding and a memory device is electrically connected to the logic device by solder balls. 
     Recently, considerations for POP are an increased number of pins and higher electrical performance. Moreover, future trends required for POP include increased interconnect density, a reduced pitch, reduced package size and thickness, improved warpage controllability, a reduction in the tooling cost, a variety of interconnect architectures, and so on. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a cross-sectional view of a semiconductor device according to an embodiment; 
         FIG. 1B  is an enlarged cross-sectional view of a portion  1 B of the semiconductor device of  FIG. 1A ; 
         FIG. 2A  is a top plan view of the semiconductor device of  FIG. 1A  according to an embodiment; 
         FIG. 2B  is an enlarged top plan view of a portion  2 B of the semiconductor package of  FIG. 2A ; 
         FIG. 3  is a cross-sectional view of a package-on-package using the semiconductor device according to an embodiment; 
         FIGS. 4A, 4B, 4C, 4D  are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment; and 
         FIG. 5  is a cross-sectional view illustrating a state in which the semiconductor device of  FIG. 1A  is connected to another semiconductor device according to another embodiment. 
     
    
    
     Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. 
     DETAILED DESCRIPTION 
     As an overview and in accordance with one embodiment, referring to  FIGS. 1A, 1B, 2A, 2B , a semiconductor device  100  includes overlapped via apertures  151  formed in an encapsulant  150  to outwardly expose solder balls  140 . Referring now to  FIG. 5 , when different types of semiconductor devices  201  are electrically connected to the solder balls  140  through the overlapped via apertures  151 , flux or solder paste  203  is unlikely to contact sidewall portions  151   b  of the overlapped via apertures  151 . Therefore, different types of semiconductor devices  201  can be mounted with improved efficiency. 
     Now in more detail,  FIG. 1A  is a cross-sectional view of a semiconductor device  100  according to an embodiment.  FIG. 1B  is an enlarged cross-sectional view of a portion  1 B of the semiconductor device  100  of  FIG. 1A . 
     As illustrated in  FIGS. 1A and 1B , the semiconductor device  100 , sometimes called an assembly, includes a printed circuit board  110 , a semiconductor die  120 , a plurality of conductive bumps  130 , a plurality of first solder balls  140 , an encapsulant  150 , and a plurality of second solder balls  160 . 
     The printed circuit board  110 , sometimes called a substrate, includes an insulation layer  111 , a first circuit pattern  112 , a first solder mask  113 , a second circuit pattern  114 , a second solder mask  115 , and conductive vias  116 . The insulation layer  111  has a substantially planar first surface  111   a , and a substantially planar second surface  111   b  opposite to the first surface  111   a . In addition, the insulation layer  111  may be made of a rigid or flexible material, but is not limited thereto. 
     The first circuit pattern  112  is formed on the first surface  111   a  of the insulation layer  111 , and may be generally formed of a copper pattern. The first solder mask  113  covers the first circuit pattern  112  and the first surface  111   a  around the first circuit pattern  112 . However, the first solder mask  113  is not formed on a predetermined area, e.g., on bond fingers and/or terminals, of the first circuit pattern  112  requiring an electrical connection. For example, the first solder mask  113  is not formed at an area of the first circuit pattern  112 , where the conductive bumps  130  and the first solder balls  140  are connected to the first circuit pattern  112 , which will later be described. 
     The second circuit pattern  114  is formed on the second surface  111   b  of the insulation layer  111 , and is generally formed of a copper pattern. The second solder mask  115  covers the second circuit pattern  114  and the second surface  111   b  around the second circuit pattern  114 . However, the second solder mask  115  is not formed at a predetermined area, e.g., terminals, of the second circuit pattern  114  requiring an electrical connection. For example, the second solder mask  115  is not formed at an area, e.g., terminals, of the second circuit pattern  114  connected to the second solder balls  160 , which will later be described. 
     The semiconductor die  120  is positioned on the printed circuit board  110 . In addition, the semiconductor die  120  includes a plurality of bond pads  121  that face toward the printed circuit board  110 . The semiconductor die  120  may be a general memory semiconductor, a logic semiconductor, or the like, but is not limited thereto. A width of the semiconductor die  120  is generally smaller than the width of the printed circuit board  110 . 
     The conductive bumps  130  are formed between the printed circuit board  110  and the semiconductor die  120  to electrically connect the printed circuit board  110  and the semiconductor die  120  to each other. That is to say, the conductive bumps  130  electrically connect the bond pad  121  of the semiconductor die  120  to the first circuit pattern  112 , e.g., bond fingers thereof, of the printed circuit board  110 . The conductive bumps  130  may be made of any one selected from gold (Au), silver (Ag), solder, and equivalents thereof, but are not limited thereto. 
     The first solder balls  140  are electrically connected to the first circuit pattern  112 , e.g., terminals thereof, of the printed circuit board  110 . That is to say, the first solder balls  140  are electrically connected to the first circuit pattern  112  formed at the outer periphery of the semiconductor die  120 . In addition, the first solder balls  140  may be made of any one selected from tin-lead (Sn—Pb), tin-lead-silver (Sn—Pb—Ag), tin-lead-bismuth (Sn—Pb—Bi), tin-copper (Sn—Cu), tin-silver (Sn—Ag), tin-bismuth (Sn—Bi), tin-silver-copper (Sn—Ag—Cu), tin-silver-bismuth (Sn—Ag—Bi), tin-zinc (Sn—Zn), and equivalents thereof, but are not limited thereto. 
     The encapsulant  150  covers the semiconductor die  120  mounted on the printed circuit board  110  and the conductive bumps  130 , thereby, protecting the same from the outside environments. The encapsulant  150  also covers lower regions of the first solder balls  140 . 
     Meanwhile, overlapped via apertures  151  are formed in the encapsulant  150  to allow the plurality of first solder balls  140  to be exposed outwardly together. In an exemplary embodiment, the overlapped via apertures  151  formed in the encapsulant  150  expose the plurality of first solder balls  140  upwardly together. 
     In more detail, the overlapped via aperture  151  is defined by a bottom portion  151   a  of the encapsulant  150 . Accordingly, the overlapped via aperture  151  is sometimes said to have a bottom portion  151   a . The bottom portion  151   a  covers the first solder ball  140  and is generally shaped as an annulus. 
     The overlapped via aperture  151  is further defined by a sidewall portion  151   b  of the encapsulant  150 . Accordingly, the overlapped via aperture  151  is sometimes said to have a sidewall portion  151   b . The sidewall portion  151   b  is separated from the plurality of first solder balls  140  and upwardly extends from the bottom portion  151   a  to a top portion  150   f  of the encapsulant  150 . A first protrusion  151   e  of the encapsulant  150  is formed substantially in the middle of (between) adjacent bottom portions  151   a  and protrudes upwards from the bottom portions  151   a.    
     The bottom portions  151   a  are formed to be substantially planar and cover lower portions of the first solder balls  140 , as described above. In addition, the sidewall portions  151   b  are formed at an angle in a range of approximately 70° to approximately 90° with respect to the bottom portions  151   a  and are spaced a predetermined distance apart from the first solder balls  140 . In addition, the first protrusion  151   e  is formed at the center between each of the bottom portion  151   a  and/or the center between each of the plurality of first solder balls  140 . 
     A thickness of the first protrusion  151   e  is smaller than that of the encapsulant  150 . In practice, the thickness of the first protrusion  151   e  may be smaller than a diameter of the first solder balls  140 . In one embodiment, the height of a top end  151   g  of the first protrusion  151   e  above the printed circuit board  110  may be lower than the height of the center of the first solder balls  140  above the printed circuit board  110 . 
     However, in other embodiments, the height of the top end  151   g  of the first protrusion  151   e  above the printed circuit board  110  may be lower than, equal to, or greater than, the height of the first solder balls  140  above the printed circuit board  110 . Generally, the greater the overlap between overlapped via aperture  151 , the lower the height of top end  151   g  of the first protrusion  151   e  above the printed circuit board  110 . 
     A width of the overlapped via aperture  151  is greater than a pitch between the first solder balls  140 . The pitch is the center to center spacing between adjacent first solder balls  140 . The width of the overlapped via apertures  151  is greater than the pitch of the first solder balls  140  such the overlapped via apertures  151  overlap each other. A second protrusion  152  is formed inward of the first protrusions  151   e , which will further be described below. 
     The second solder balls  160  are electrically connected to the second circuit pattern  114  of the printed circuit board  110 . The second solder balls  160  are to be later mounted on an external device (not shown) such as a larger circuit board. Therefore, the second solder balls  160  practically electrically connect the semiconductor device  100  to the external device while mechanically fixing the semiconductor device  100  to the external device. 
       FIG. 2A  is a top plan view of the semiconductor device  100  of  FIG. 1A  according to an embodiment.  FIG. 2B  is an enlarged top plan view of a portion  2 B of the semiconductor device  100  of  FIG. 2A . As illustrated in  FIGS. 2A and 2B , a plurality of overlapped via apertures  151  collectively shaped as a substantially square dual-stacked line are formed in the encapsulant  150 . In addition, a plurality of first solder balls  140  are outwardly exposed together through the overlapped via apertures  151 . In the illustrated embodiment, the overlapped via apertures  151  collectively have a substantially square, two lined shape. 
     In alternative embodiments, however, overlapped via apertures  151  collectively have a substantially square shape of two or more lines, or have several disconnected overlapped via apertures. That is to say, the shapes of the overlapped via apertures  151  are not limited to that illustrated in the exemplary embodiment. 
     The overlapped via apertures  151  outwardly exposing the plurality of first solder balls  140  together according to the illustrated embodiment will now be described in detail. Generally, each overlapped via aperture  151  is defined by an imaginary circle  155  in the plane of top portion  150   f  of encapsulant  150 . The imaginary circles  155  of adjacent overlapped via apertures  151  overlap each other such that the sidewall portions  151   b  and sides  152   a , which lie upon the imaginary circle  155 , of the overlapped via apertures  151  are separated from one another. 
     Where two imaginary circles  155  overlap each other, the first protrusion  151   e  is formed. At a central area defined by four imaginary circles  155 , the second protrusion  152  is formed. The second protrusion  152  is a portion of the encapsulant  150  that was not removed during formation of overlapped via apertures  151 , but is surrounded by the overlapped via apertures  151 . 
     The overlapped via apertures  151  have the sidewall portions  151   b  each having a substantially arc-shaped curve  151   c  partially corresponding to the circumference of each of the first solder balls  140 . The arc-shaped curve  151   c  is a portion of the imaginary circle  155 . 
     The arc-shaped curves  151   c  and imaginary circles  155  overlap each other, forming overlapped areas  151   d . Each of the first solder balls  140  is positioned within the arc-shaped curve  151   c  and imaginary circle  155 . In addition, a predetermined area of the bottom portion  151   a , extending from the first solder balls  140  to the sidewall portion  151   b , is exposed. 
     The first protrusion  151   e  is formed at the overlapped area  151   d  between one of the first solder balls  140  and the other adjacent to the one of the first solder balls  140 , i.e., between adjacent solder balls  140 . That is to say, the first protrusion  151   e  having a height smaller than the encapsulant  150  is formed in each of the overlapped areas  151   d.    
     A second protrusion  152 , sometimes called a central protrusion  152 , having a predetermined thickness is formed at the center of an area formed by, for example, four of the first solder balls  140 . The thickness of the second protrusion  152  is the same as that of the encapsulant  150 , i.e., a top end  152   f  of the second protrusion  152  is parallel to and coplanar with the top portion  150   f  of the encapsulant  150 . 
     The second protrusion  152  may be shaped of a diamond or rhombus having a plurality of sides  152   a . In addition, centers of the respective sides  152   a  of the second protrusion  152  are recessed or bent, i.e., curved, toward of the center of the second protrusion  152 . The center of the respective sides  152   a  of the second protrusion  152  face the center of the first solder balls  140  corresponding thereto. In addition, the second protrusion  152  has four vertices  152   b , which face between the center of two, for example, of the first solder balls  140 . Further, each of the vertices  152   b  of the second protrusion  152  faces the overlapped area  151   d  of the arc-shaped curve  151   c  and the first protrusion  151   e  formed in the overlapped area  151   d.    
       FIG. 3  is a cross-sectional view of a package-on-package  200  using the semiconductor device  100  according to an embodiment. As illustrated in  FIG. 3 , a semiconductor device  201  is mounted on the semiconductor device  100 , thereby achieving the package-on-package  200 , sometimes called an assembly. Here, the semiconductor device  201  different from the semiconductor device  100  may be a memory semiconductor, a logic semiconductor, and equivalents thereof, but is not limited thereto. In an exemplary embodiment, if the semiconductor device  100  is a memory semiconductor, the semiconductor device  201  may be a logic semiconductor. 
     The semiconductor device  201  according to the illustrated embodiment may also include solder balls  202 , which are electrically connected to first solder balls  140  through the exposed overlapped via apertures  151 . In practice, the solder balls  202  and the first solder balls  140  of different types of the semiconductor devices  100  and  201  are reflown, followed by cooling, thereby being electrically connected to each other as integral solder columns  204 . 
       FIGS. 4A, 4B, 4C, 4D  are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment. As illustrated in  FIG. 4A , the semiconductor die  120  is attached to the printed circuit board  110  using the conductive bumps  130 . In addition, a plurality of first solder balls  140  are also attached to the printed circuit board  110 . 
     The semiconductor die  120  having the conductive bumps  130  attached thereto is placed on the printed circuit board  110 , e.g., to bond fingers of the first circuit pattern  112 , to then perform a general reflow process to attach the semiconductor die  120  to the printed circuit board  110 . In addition, the first solder balls  140  are placed on the printed circuit board  110 , e.g., on terminals of the first circuit pattern  112 , using flux to then perform a general reflow process to attach the first solder balls  140  to the printed circuit board  110 . 
     Here, a die attaching process may first be performed and a solder ball attaching process may then be performed, and vice versa. Alternatively, the die attaching process and the solder ball attaching process may be performed at the same time. 
     As illustrated in  FIG. 4B , the semiconductor die  120 , the conductive bumps  130  and the first solder balls  140  are encapsulated using the encapsulant  150 . In an exemplary embodiment, the semiconductor device shown in  FIG. 4A  is positioned inside a mold and the encapsulant  150  in a liquid phase is injected into the mold. Subsequently, if the encapsulant  150  injected into the mold is cured, the encapsulated semiconductor device  100  is taken out from the mold. After the encapsulation, a curing process may further be performed. 
     As illustrated in  FIG. 4C , a predetermined area of the encapsulant  150  corresponding to the plurality of first solder balls  140  is removed by a laser beam, e.g., using laser-ablation, thereby forming the overlapped via apertures  151 . Here, the laser beam is supplied to a predetermined area of the encapsulant  150  corresponding to one first solder ball  140 . 
     Additionally, a width or area of the encapsulant  150  removed by the laser beam is greater than that of the one first solder ball  140 . Therefore, if the laser beam is supplied to four first solder balls  140 , like in an exemplary embodiment, the planar overlapped via apertures  151  according to the illustrated embodiment may have a first protrusion  151   e  having a thickness smaller than that of the encapsulant  150 , and a second protrusion  152  having a thickness equal to that of the encapsulant  150 . 
     The first protrusion  151   e  is formed at a boundary area between one of the four first solder balls  140  (and a first overlapped via aperture  151 ) and the other adjacent to the one first solder ball  140  (and an adjacent second overlapped via aperture  151 ). The second protrusion  152  is formed at a central area formed by, for example, four first solder balls  140  (and four adjacent overlapped via apertures  151 ). 
     Here, the overlapped via apertures  151  formed by the laser beam includes a substantially planar bottom portion  151   a  formed around the solder balls  140 , a sidewall portion  151   b  separated from the solder balls  140 , and a side  152   a  also separated from the solder balls  140 . In addition, the laser beam makes the bottom portion  151   a  remain on the printed circuit board  110  to a predetermined thickness, thereby allowing the first solder balls  140  to be tightly interlocked with the bottom portion  151   a.    
     As illustrated in  FIG. 4D , a plurality of second solder balls  160  are attached to the printed circuit board  110 , e.g., to terminals of the second circuit pattern  114 . In an exemplary embodiment, the second solder balls  160  are placed on the printed circuit board  110  using flux to then perform a general reflow process to attach the second solder balls  160  to the printed circuit board  110 . In practice, since the semiconductor device shown in  FIG. 4D  is processed upside down, the printed circuit board  110  and the second solder balls  160  are not separated from each other due to a gravitational action. 
       FIG. 5  is a cross-sectional view illustrating a state in which the semiconductor device  100  of  FIG. 1A  is connected to another semiconductor device  201  according to another embodiment to form the package-on-package  200 . As illustrated in  FIG. 5 , the semiconductor device  201  may be electrically connected to the semiconductor device  100  according to one embodiment. Here, commonly used flux  203  or solder paste may be used as a connection medium. 
     In the illustrated embodiment, an overlapped via aperture  151  having a relatively large width or area is formed on the semiconductor device  100 . Thus, when solder balls  202  of another semiconductor device  201  are temporarily attached onto the semiconductor device  100  using, for example, flux  203 , the flux  203  is unlikely to touch sidewall portions  151   b  of the overlapped via apertures  151 . 
     Therefore, during a reflow process, the first solder balls  140  formed in the semiconductor device  100  and the solder balls  202  formed in another semiconductor device  201  are uniformly melted and cooled, so that the semiconductor device  201  is not tilted. Since the overlying semiconductor device  201  is not tilted, a good package-on-package  200  can be obtained. 
     Although specific embodiments were described herein, the scope of the invention is not limited to those specific embodiments. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of the invention is at least as broad as given by the following claims.