Patent Publication Number: US-7904660-B2

Title: Page descriptors for prefetching and memory management

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation of U.S. application Ser. No. 10/326,634 filed on Dec. 20, 2002, now U.S. Pat. No. 7,334,088, which are each incorporated by reference herein in their entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present disclosure relates generally to a computer system having a processor, a main memory, and a cache, and more particularly to a computer system and a method for enhancing cache prefetch behavior. 
     2. Discussion of Related Art 
     A common problem in computer design is the increasing latency, in terms of processor cycles, required for transferring data or information between the processor (or processors) and the main memory of a computer system. The increasing number of processor cycles has led to ever-larger caches on the processor chip, but this approach is yielding diminishing returns. Another approach to decreasing memory latency is to attempt to prefetch data into the cache or caches. There have been a large number of proposed mechanisms for prefetching, and prefetching is employed in numerous computer systems. One common approach is (given a cache fault to a line L(i,j), denoting the i th  line in page j) to not only fetch the desired line but to also fetch the next line. In the paper entitled “Special Section on High Performance Memory Systems,” (IEEE Transactions on Computers, Vol. 50, No. 11, November 2001) the paper includes a description of the overall problem and various approaches to its alleviation. 
     In the prefetching schemes mentioned above and in current prefetching schemes, these schemes operate by observing current access behavior, for example which lines are being fetched, and possibly their relation to other lines currently in the cache. 
     In the paper entitled “Adaptive Variation of the Transfer Unit in a Storage Hierarchy,” (P. A Franaszek and B. T. Bennett, IBM J. Res. Develop, Vol. 22, No. 4, July 1978, pp. 405-412) the paper discusses a scheme where prefetching in a storage hierarchy is based on information stored in memory on references to individual pages. For example, information is stored and updated which determines, given a fault to a page, whether just the page should be fetched, or the page and a fixed set of other pages should also be fetched. The method in the paper discussed above applies to fetching pages into main memory from disk storage rather than cache lines from main memory. 
     The prior art prefetching methods do not take into account access pattern behavior useful for improving prefetching performance. 
     A need therefore exists for improving prefetching performance by storing and updating relevant information on access patterns, as well as software-provided prefetch directives, for each individual page in memory. 
     SUMMARY OF THE INVENTION 
     In a computer system, cache prefetch behavior is enhanced by maintaining a Page History Tag (or PHT) for each page in the system, which determines prefetch behavior. This history tag may be updated by either the cache hardware, the operating system, or other suitable software. Given a cache fault to a line L(i,j), the PHT for page j, denoted by H(j), is accessed. H(j) then determines which lines or pages are prefetched. 
     In an embodiment of the present invention, a tag for each page is maintained which holds information for cache accesses and prefetching to a plurality of lines in the page and other pages. Thus, given a fault to a line, tag information can be used to prefetch selected variable subsets of lines from the page, where the desired line is located, and from additional pages. Another embodiment of the present invention provides the insertion in the page tags of software-provided directives for prefetching. 
     Another embodiment of the present invention provides a computer system comprising a processor, a main memory, wherein each page in the main memory has associated with it a tag, which is used for prefetching of a variable subset of lines from this page as well as lines from at least one other page, a cache memory coupled to the processor and the main memory, wherein a block of data or page of information is read from the main memory and stored in the cache memory, a prefetch controller coupled to the processor, wherein the prefetch controller responds to the processor determining a fault (or miss) line has been found in the page being held in the cache memory, and a prefetch buffer coupled to the prefetch controller, the cache memory, and the main memory, wherein the prefetch controller responds to the detection of the faulted line by fetching a corresponding line of data with the corresponding tag to be stored in the prefetch buffer and sending the corresponding line of data to the cache memory. 
     The computer system also provides updating of the prefetch buffer by deleting a tag that has been held in the prefetch buffer for the longest amount of time, and storing the updated version of the tag in the main memory. 
     Further, the updating of tags may be determined by the occurrence of accesses to individual lines within a page. 
     Also, the prefetching of lines in a page may be a function of the information stored in its corresponding tag and the accessing to lines in the page. 
     In addition, the computer system above provides a means for storing tags and a processor for processing tags, wherein the processor includes updating the tags for prefetching and determining which tags should be held in the prefetch buffer. 
     Further, the computer system above provides a means for modifying and updating the tags based upon a monitoring of accesses to cache lines. 
     Another embodiment of the present invention provides a prefetch method for transferring information (data) within a computer system includes detecting a faulted line within a given page, accessing a page history tag associated with the given page, and determining from the page history tag which lines or pages are to be prefetched. 
     In addition, the method above may include replacing selected tags and lines within the prefetch buffer. 
     Further, the step of detecting a faulted line in the method above may include placing the faulted line into the cache memory, determining if the faulted line is currently in the prefetch buffer, fetching the associated selected tag into the prefetch buffer from the main memory if the tag is not currently in the prefetch buffer, and replacing a pre-existing selected tag with the associated selected tag prefetched from the main memory, and updating the information associated with this tag and page into the main memory. 
     Also, the method step of accessing the tag in the method above may include storing information, corresponding to accesses to a page, on the tag, wherein the tag includes at least a first and second history vectors, and denoting an ith bit of the at least first and second vectors to determine whether a line corresponding to the tag in the prefetch buffer was accessed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Detailed exemplary embodiments of the invention will become more apparent when read with reference to the attached drawings in which: 
         FIG. 1  is a block diagram illustrating the structure of a computer system, according to an embodiment of the present invention. 
         FIG. 1A  is a block diagram illustrating the structure of a computer system, according to another embodiment of the present invention. 
         FIG. 2  is a chart illustrating the format for Page History Tags or PHTs, according to another embodiment of the present invention. 
         FIG. 3  is a flow chart illustrating the control flow for prefetch decisions, according to another embodiment of the present invention. 
         FIGS. 4   a  and  4   b  are flow charts illustrating the control flow for updating page history tags, according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     It is to be understood that systems and methods described herein in accordance with the present invention may be implemented in various forms of hardware, software, firmware, special purpose processors, or any combination thereof. Preferably, the present invention is implemented in software as an application comprising program instructions that are tangibly embodied on one or more program storage devices (e.g. magnetic floppy disk, RAM, CD Rom, Rom and flash memory), and executable by any device or machine comprising suitable architecture. 
     It is to be further understood that since the constituent system modules and method steps depicted in the accompanying figures are preferably implemented in software, the actual connection between the system components (or the flow of the process steps) may differ depending upon the manner in which the present invention is programmed. Given the teachings herein, one of ordinary skill in the related art will be able to contemplate these and similar implementations or configurations of the present invention. 
       FIG. 1  shows a block diagram of a computer system. The computer system comprises a processor  101 , a cache  102 , a prefetch buffer  104  which holds prefetch lines  105  and tags  106 , a prefetch controller  103 , and a main memory  107  which stores a tag H(j)  109  for each page j in memory and stores each page j in memory  108 . The tags can be addressed individually by the processor, and thus by the software. For purposes of illustration, each line in this system is of 128 bytes, and each page contains 32 such lines, or 4K bytes. The prefetch buffer may be divided into two parts, a part  105  that holds prefetched lines, and another part  106  to hold tags. In the present embodiment, each of the prefetched lines and tags are replaced by a first-in-first-out or FIFO basis (or any other suitable method). For example, when some set of n lines is prefetched from page j, the n lines presently in the prefetch buffer which have been there longest are deleted. Similarly, If there is a fault to a page j whose tag is not currently in the prefetch buffer, the associated tag is fetched into the buffer from the main memory  107 . The associated tag which has been there the longest is deleted, and its updated value, as described below and in  FIG. 4 , is stored back into main memory  107 . 
       FIG. 1   a  shows a block diagram illustrating the structure of a computer system, according to another embodiment of the present invention. More specifically,  FIG. 1A  shows the computer system of  FIG. 1  with the added feature that the prefetch  104  may be separated into at least two prefetch buffers. In this embodiment, a prefetch lines buffer  105 A and a tags buffer  106 A. 
       FIG. 2  shows the format for information stored in a tag H(j). For purposes of illustration in this embodiment, the tag includes two history vectors used to store relevant information on accesses to this page. Each vector has 32 entries, each of one bit, where the ith bit denotes whether or not the ith line in this page was accessed during some visit of the tag in the prefetch buffer  106 . Vector V 1  has an entry of 1 for each cache line referenced during the most recent visit of H(j) into  106 . Vector V 2  is used to collect this information for a current visit. And, the ith entry in vector V 2  is set to 1 if line L(i,j) is referenced in the current visit of tag H(j) into buffer  106 . Also included in the tag is a 32 bit vector VS which can be set by the software to mandate prefetching as well as the address of a page g which is to be prefetched given an access to the present page, and given that a decision bit D d  is set to 1 by the software or computer system. If D d  is set to zero by the software or the computer system, the page g is not to be prefetched. In the present embodiment, the address of page g is set by the software, as is the decision bit D d . 
     Another embodiment of the present invention provides the prefetch controller processor executing a program loaded by the operating system.  FIG. 3  illustrates a method in relation to the system illustrated in  FIG. 1A . In this embodiment, as shown in  FIG. 3 , a reference is given to a line L(i,j) not currently in the cache  102  (referred to as a fault line), Step  31 . The desired line is fetched into the cache from buffer  105 A or main memory  107 , step  32 . If the desired line is not located in the buffer  105 A, then the desired line is fetched from the main memory  107 . Next, the location of the associated tag needs to be ascertained, step  33 . If the associated tag is not located in the buffer  106 A, then the associated tag is fetched into the buffer  106 A from the main memory  107 , step  34 . Upon fetching the tag H(j) into buffer  106 A (step  34 ), the controller examines the bit vectors stored in the tags to determine which lines or pages to prefetch. In this embodiment, those lines corresponding to 1 entries in the vectors V 1  and V s  are prefetched and placed in the buffer  105 A, step  35 . Next, if the decision bit D d  in the tag is set to 1, e.g. the tag indicates that a page g is to be prefetched, step  36 . Then, the tag for that page is fetched, those lines are prefetched which correspond, in H(g), to 1 entries in vectors V 1  and V s , Steps  37 - 39 . It is noted that steps  37 - 39  are similar to steps  33 - 35  except the decision and prefetching steps  37 - 39  pertain to H(g). Furthermore, in this implementation, if the decision bit D d  in H(g) is set to zero the H(g) is not examined, and there is no further page prefetch (step  36 ). 
       FIG. 4A  illustrates the updating of the vector V 2 . If a line L(i,j) not currently in the cache  102  is referenced (Step  41 ), e.g. there is a fault to L(i,j), a 1 is entered into the ith component of vector V 2  in the tag H(j), step  42 . 
     Referring to  FIG. 4B ,  FIG. 4B  illustrates a method for updating a tag in the buffer  106 , e.g. H(j). Separately, as each tag H(j) is ejected from buffer  106  (step  401 ), Vector V 2  is substituted for V 1  in this tag, entries in V 2  are set to zero, step  402 . Then, H(j) is written back to main memory  107 , step  403 . 
     While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.