Patent Publication Number: US-2017350012-A1

Title: Semiconductor manufacturing apparatus

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation-in-part under 35 U.S.C. §120 of U.S. application Ser. No. 15/227,089, filed Aug. 3, 2016, which claims the benefit of priority under 35 U.S.C. §119 from Korean Patent Application No. 10-2015-0110234, filed on Aug. 4, 2015, in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein in its entirety by reference. 
    
    
     BACKGROUND 
     Field 
     Example embodiments of the inventive concepts relate to a semiconductor manufacturing apparatus, and more particularly, to a semiconductor manufacturing apparatus, by which a material layer having good step coverage may be stably manufactured despite variations in other process parameters. 
     Related Art 
     As semiconductor devices have been increasingly downscaled, it has become more difficult to conformally form thin layers. In particular, with the downscaling of semiconductor devices, aspect ratios of structures in semiconductor devices may greatly increase. Thus, it becomes increasingly difficult for thin layers to maintain high step coverages, and process conditions become more complicated. Accordingly, it is imperatively necessary to develop a method of forming a thin layer having good step coverage under eased conditions. 
     SUMMARY 
     Example embodiments of the inventive concepts provide a semiconductor manufacturing apparatus, by which a material layer having good step coverage may be stably manufactured in spite of variations in other process parameters. 
     According to an aspect of the inventive concept, there is provided a semiconductor manufacturing apparatus including a reaction chamber that is configured such that a substrate is loaded and unloaded, a source material supply apparatus configured to supply a source material to the reaction chamber and including a vaporizer for the source material, a modifier supply apparatus configured to supply an ether-based modifier to the reaction chamber, a vaporizer for the modifier disposed between the modifier supply apparatus and the reaction chamber, a reaction material supply apparatus configured to supply a reaction material to the reaction chamber, and a purge gas supply apparatus configured to supply a purge gas to the reaction chamber. 
     The modifier supply apparatus may be configured to supply the modifier in liquid phase to the vaporizer for the modifier. 
     The modifier supply apparatus may include a canister capable of containing the modifier, a pressurizing nozzle for supplying a pressurizing fluid into the canister, and a discharge nozzle for discharging the modifier in the canister out of the canister. 
     An end portion of the pressurizing nozzle may be disposed higher than a liquid level of the modifier, and an end portion of the discharge nozzle may be disposed lower than the liquid level of the modifier. 
     The other end portion of the discharge nozzle may be connected to a mass flow controller, and the mass flow controller may be connected to the vaporizer for the modifier. 
     The ether-based modifier may be indicated by R—O—R′, each of R and R′ being independently selected from the group consisting of C1-C10 alkyl, C1-C10 alkenyl, C6-C12 aryl, C6-C12 arylalkyl, C6-C12 alkylaryl, C3-C12 cycloalkyl, C3-C12 cycloalkenyl, C3-C12 cycloalkynyl, and C3-C12 heterocycloalkyl containing at least one of N and O in rings. 
     The ether-based modifier may have a polarizability higher than an alcohol-based modifier selected from a methanol-based modifier, an ethanol-based modifier, a propanol-based modifier, a butanol-based modifier, a formic acid-based modifier, an acetic acid-based modifier, a propanoic acid-based modifier, a butanoic-acid based modifier, a pentanoic-acid based modifier, a phenol-based modifier and a benzoic-acid based modifier. 
     The flow rate of the source material from the vaporizer for the source material to the reaction chamber may be controlled by a flow rate control device interposed therebetween. 
     The reaction material supply apparatus may be configured to supply the reaction material to the reaction chamber while the source material supply apparatus does not supply the source material to the reaction chamber. 
     The modifier supply apparatus may be configured to supply the ether-based modifier to the reaction chamber after the supplying of the reaction material is terminated and before the supplying of the source material begins. 
     The modifier supply apparatus may be configured to supply the ether-based modifier to the reaction chamber after the supplying of the source material is terminated and before the supplying of the reaction material begins. 
     The modifier supply apparatus may be configured to supply the ether-based modifier to the reaction chamber while the source material is supplied to the reaction chamber by the source material supply apparatus. 
     The modifier supply apparatus may be configured to begin supplying the ether-based modifier to the reaction chamber after the source material supply apparatus begins supplying the source material to the reaction chamber, and the modifier supply apparatus may be configured to stop supplying the ether-based modifier to the reaction chamber after the source material supply apparatus stops supplying the source material to the reaction chamber. 
     The source material supply apparatus may be configured to begin supplying the source material to the reaction chamber as soon as the modifier supply apparatus stops a first supplying the ether-based modifier to the reaction chamber in a cycle. The modifier supply apparatus may be configured to begin a second supplying the ether-based modifier to the reaction chamber again as soon as the source material supply apparatus stops supplying the source material to the reaction chamber in the cycle. 
     The modifier supply apparatus may be configured to supply the ether-based modifier to the reaction chamber while the reaction material is supplied to the reaction chamber by the reaction material supply apparatus. 
     The modifier supply apparatus may be configured to begin supplying the ether-based modifier to the reaction chamber before the reaction material supply apparatus begins supplying the reaction material to the reaction chamber. The modifier supply apparatus may be configured to stop supplying the ether-based modifier to the reaction chamber before the reaction material supply apparatus stops supplying the reaction material to the reaction chamber. 
     According to another aspect of the inventive concept, there is provided a semiconductor manufacturing apparatus including a reaction chamber that is configured such that a substrate is loaded and unloaded, a source material supply apparatus configured to supply a source material to the reaction chamber, a modifier supply apparatus configured to supply an ether-based modifier to the reaction chamber, a vaporizer for the modifier disposed between the modifier supply apparatus and the reaction chamber, and a purge gas supply apparatus configured to supply a purge gas to the reaction chamber. The source material may be a precursor of a metal or semimetal having a ligand. The metal or semimetal of the precursor may include at least one selected from the group consisting of zirconium (Zr), lithium (Li), beryllium Be), boron (B), sodium (Na), magnesium (Mg), aluminum (Al), potassium (K), calcium (Ca), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), germanium (Ge), rubidium (Rb), strontium (Sr), yttrium (Y), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), antimony (Sb), cesium (Cs), barium (Ba), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), mercury (Hg), lead (Pb), bismuth (Bi), polonium (Po), Francium (Fr), radium (Ra), actinium (Ac), and silicon (Si). 
     The semiconductor manufacturing apparatus may further include a reaction material supply apparatus configured to supply a reaction material to the reaction chamber. 
     The reaction material supply apparatus may be configured to supply an oxidizer as the reaction material such that an oxide layer of the metal or semimetal is formed, the oxidizer being selected from the group consisting of O 3 , H 2 O, O 2 , NO 2 , NO, N 2 O, H 2 O, alcohol, a metal alkoxide, plasma O 2 , remote plasma O 2 , plasma N 2 O, plasma H 2 O, and a combination thereof. 
     According to another aspect of the inventive concept, there is provided a semiconductor manufacturing apparatus including a reaction chamber that is configured such that a substrate is loaded and unloaded, a source material supply apparatus configured to supply a source material to the reaction chamber, a modifier supply apparatus configured to supply an ether-based modifier to the reaction chamber, a vaporizer for the modifier disposed between the modifier supply apparatus and the reaction chamber, a reaction material supply apparatus configured to supply an oxidizer to the reaction chamber to form an oxide layer, and a purge gas supply apparatus configured to supply a purge gas to the reaction chamber. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG. 1  is a flowchart of a method of forming a material layer according to some example embodiments; 
         FIG. 2  is a detailed flowchart of an operation of forming a material layer on the substrate according to some example embodiments; 
         FIG. 3  is a schematic diagram of a semiconductor apparatus configured to perform a method of forming a material layer according to some example embodiments; 
         FIG. 4A  is a schematic diagram of a semiconductor apparatus configured to perform a method of forming a material layer according to other example embodiments; 
         FIG. 4B  is a schematic diagram of a modifier supply apparatus configured to uniformly supply a modifier; 
         FIG. 4C  is a schematic diagram of a modifier supply apparatus according to a typical related art; 
         FIGS. 5A to 5G  are timing diagrams of a method and process of supplying a modifier, a source material, and a reaction material in  FIG. 2 ; 
         FIG. 6  is a detailed flowchart of an operation of forming a material layer on the substrate, according to some example embodiments; 
         FIGS. 7A to 7D  are timing diagrams of a method and order of supplying a modifier, a source material, and a reaction material in  FIG. 6 ; 
         FIG. 8  is a graph of a deposition rate of a material layer relative to a purge time; 
         FIG. 9  is a graph of a deposition rate of a material layer relative to a feeding time; 
         FIGS. 10A to 10J  are cross-sectional views of sequential process operations of a method of manufacturing an IC device according to some example embodiments; 
         FIG. 11A  is a plan view of an integrated circuit (IC) device according to some example embodiments; 
         FIG. 11B  is a perspective view of the IC device of  FIG. 11A ; 
         FIG. 11C  is a cross-sectional view taken along lines X-X′ and Y-Y′ of  FIG. 11A ; 
         FIG. 12  is a cross-sectional view of another example of a semiconductor device manufactured by a method of manufacturing a semiconductor device, according to some example embodiments; 
         FIG. 13  is a schematic block diagram of a display device including a display driver integrated circuit (DDI), according to some example embodiments; 
         FIG. 14  is a block diagram of an electronic system according to some example embodiments; and 
         FIG. 15  is a block diagram of an electronic system according to some example embodiments. 
     
    
    
     DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS 
     Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. Thus, the invention may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein. Therefore, it should be understood that there is no intent to limit example embodiments to the particular forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope. 
     In the drawings, the thicknesses of layers and regions may be exaggerated for clarity, and like numbers refer to like elements throughout the description of the figures. 
     Although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     It will be understood that, if an element is referred to as being “connected” or “coupled” to another element, it can be directly connected, or coupled, to the other element or intervening elements may be present. In contrast, if an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” if used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. 
     Spatially relative terms (e.g., “beneath,” “below,” “lower,” “above,” “upper” and the like) may be used herein for ease of description to describe one element or a relationship between a feature and another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation that is above, as well as, below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. 
     Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient (e.g., of implant concentration) at its edges rather than an abrupt change from an implanted region to a non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation may take place. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope. 
     It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved. 
     Although corresponding plan views and/or perspective views of some cross-sectional view(s) may not be shown, the cross-sectional view(s) of device structures illustrated herein provide support for a plurality of device structures that extend along two different directions as would be illustrated in a plan view, and/or in three different directions as would be illustrated in a perspective view. The two different directions may or may not be orthogonal to each other. The three different directions may include a third direction that may be orthogonal to the two different directions. The plurality of device structures may be integrated in a same electronic device. For example, when a device structure (e.g., a memory cell structure or a transistor structure) is illustrated in a cross-sectional view, an electronic device may include a plurality of the device structures (e.g., memory cell structures or transistor structures), as would be illustrated by a plan view of the electronic device. The plurality of device structures may be arranged in an array and/or in a two-dimensional pattern. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     In order to more specifically describe example embodiments, various features will be described in detail with reference to the attached drawings. However, example embodiments described are not limited thereto. 
       FIG. 1  is a flowchart of a method of forming a material layer according to some example embodiments. 
     Referring to  FIG. 1 , a substrate may be provided into a reaction chamber (S 1 ). The substrate may include a semiconductor substrate including a semiconductor element (e.g., silicon (Si) or germanium (Ge)) or a compound semiconductor (e.g., silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)). In some example embodiments, the substrate may include a structure including a semiconductor substrate, at least one insulating layer formed on the semiconductor substrate, and/or at least one conductive region. The conductive region may include, for example, a doped well, a doped structure, and/or a metal-containing conductive layer. Also, the substrate may have one of various device isolation structures, such as a shallow trench isolation (STI) structure. 
     A material layer may be formed on the substrate loaded into the reaction chamber (S 2 ). The material layer may include a metal oxide, a metal nitride, a semimetal oxide, and/or a semimetal nitride. 
     More specifically, the metal or semimetal may be, for example, at least one selected from the group consisting of zirconium (Zr), lithium (Li), beryllium Be), boron (B), sodium (Na), magnesium (Mg), aluminum (Al), potassium (K), calcium (Ca), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), germanium (Ge), rubidium (Rb), strontium (Sr), yttrium (Y), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), antimony (Sb), cesium (Cs), barium (Ba), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), mercury (Hg), lead (Pb), bismuth (Bi), polonium (Po), Francium (Fr), radium (Ra), actinium (Ac), and silicon (Si). 
     In particular, the material layer may be a Zr oxide layer, an Al oxide layer, a Hf oxide layer, a La oxide layer, a Si oxide layer, a Ta oxide layer, a Nb oxide layer, a Zr nitride layer, an Al nitride layer, a Hf nitride layer, a La nitride layer, a Si nitride layer, a Ta nitride layer, a Nb nitride layer, or a combination thereof. Alternatively, the material layer may be a composite oxide thin layer or composite nitride thin layer including at least two kinds of central atoms selected from zinc, aluminum, hafnium, lanthanum, silicon, tantalum, and niobium. 
     The material layer manufactured by a method of forming a material layer according to example embodiments may be used for various purposes. For example, the material layer manufactured by the method of forming the material layer according to the example embodiments may be used for a dielectric layer included in a capacitor of a semiconductor memory device, a gate dielectric layer of a transistor, a conductive barrier layer used for an interconnection, a resistive layer, a magnetic layer, a liquid-crystal (LC) barrier metal layer, a member for a thin-film solar cell, a member for semiconductor equipment, a nanostructure, a hydrogen storage alloy, and a microelectromechanical (MEMS) actuator, but example embodiments of the inventive concepts are not limited thereto. 
     Thereafter, it may be determined whether the material layer is formed to a desired thickness (S 3 ). When the material layer is formed to a thickness smaller than the desired thickness, an operation S 2  of forming the material layer may be repeated. When the material layer is formed to a thickness equal to or greater than the desired thickness, an additional operation of forming a material layer may be interrupted. 
       FIG. 2  is a detailed flowchart of an operation of forming the material layer on the substrate, according to some example embodiments. 
     Referring to  FIG. 2 , a source material and a modifier may be provided on a substrate (S 21   a ). 
     The source material may be a precursor material of the material layer to be deposited. The source material may be an arbitrary material that may be denoted by MLn. Here, M denotes a central atom of the source material, and L denotes a ligand bonded to M, that is the central atom of the source material. Also, n denotes a number determined by the central atom M and the ligand L and is, for example, an integer ranged from  2  to  6 . Since the central atom M is metal or a semimetal as described above, additional descriptions thereof are omitted. 
     In a method of forming a thin layer according to some example embodiments, compounds, which may be used as the source material, and organic coordination compounds, which may be included as ligands in the source material, will be described in detail later. 
     The modifier may be an ether-based material that may be indicated by R—O—R′. Here, each of R and R′ may be independently selected from the group consisting of C1-C10 alkyl, C1-C10 alkenyl, C6-C12 aryl, C6-C12 arylalkyl, C6-C12 alkylaryl, C3-C12 cycloalkyl, C3-C12 cycloalkenyl, C3-C12 cycloalkynyl, and C3-C12 heterocycloalkyl containing at least one of N and O in rings. Optionally, R and R′ are connected to each other to form a ring. 
     According to some example embodiments, the modifier may be an ether-based modifier having a polarizability higher than an alcohol-based modifier selected from a methanol-based modifier, an ethanol-based modifier, a propanol-based modifier, a butanol-based modifier, a formic acid-based modifier, an acetic acid-based modifier, a propanoic acid-based modifier, a butanoic-acid based modifier, a pentanoic-acid based modifier, a phenol-based modifier and a benzoic-acid based modifier. 
     When the source material and the modifier are supplied onto the substrate in the reaction chamber, a layer of the source material may be formed on the substrate. Also, the source material may be excessively physisorbed on portions of the substrate to form two or more layers of the source material. 
     Thereafter, after the source material and the modifier are provided on the substrate, the reaction chamber may be purged with a purge gas (S 22   a ). The source material and the modifier that are excessively adsorbed on the substrate may be removed due to the purge process, and the layer of the source material may uniformly form one monolayer on the substrate. 
     For example, the purge gas may be an inert gas, such as argon (Ar), helium (He), or neon (Ne), and/or a gas having very low activity, such as nitrogen (N 2 ). 
     Thereafter, a reaction material may be supplied into the reaction chamber (S 23   a ). The reaction material may include a material (e.g., an oxidizer or a nitrifier) that may be reacted with the source material to form a material layer. 
     The oxidizer may include, for example, O 3 , H 2 O, O 2 , NO 2 , NO, N 2 O, H 2 O, alcohol, a metal alkoxide, plasma O 2 , remote plasma O 2 , plasma N 2 O, plasma H 2 O, or a combination thereof. The nitrifier may include, for example, N 2 , NH 3 , hydrazine (N 2 H 4 ), plasma N 2 , remote plasma N 2 , or a combination thereof. 
     The material layer may be grown in an apparatus capable of performing an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The semiconductor apparatus may include the reaction chamber. The reaction chamber may be a chamber into which a substrate is loaded to perform an ALD process or a CVD process. 
       FIG. 3  is a schematic diagram of a semiconductor apparatus configured to perform a method of forming a material layer according to some example embodiments. 
     Referring to  FIG. 3 , a semiconductor apparatus  1  may include a process material supply system  20   a  capable of independently supplying the modifier  14 , the source material  16 , a purge gas  19 , and a reaction material  18  into a reaction chamber  10 . The process material supply system  20   a  may be configured to independently supply the modifier  14 , the source material  16 , the purge gas  19 , and the reaction material  18  into the reaction chamber  10  in pulse for different time periods. Alternatively, the process material supply system  20   a  may be configured to supply at least two of the modifier  14 , the source material  16 , the purge gas  19 , and the reaction material  18  into the reaction chamber  10  at the same time. The reaction chamber  10  may be a chamber into and from which a substrate  100  may be loaded and unloaded. 
     The process material supply system  20   a  may include a source material supply apparatus  30   a , a modifier supply apparatus  60   a , a purge gas supply apparatus  90   a , and a reaction material supply apparatus  80   a . The source material supply apparatus  30   a  may be an apparatus configured to supply the source material  16  into the reaction chamber  10 . 
     The source material supply apparatus  30   a  may include a source material storage container  40  and a vaporizer  50 . The source material storage container  40  and the vaporizer  50  may be connected to each other by a conduit  42 , and the conduit  42  may include a flow rate control device  44 . The vaporizer  50  and the process chamber  10  may be connected to each other by a conduit  52 , and the conduit  52  may include a flow rate control device  54 . 
     The source material  16  in the source material storage container  40  may be transported to the vaporizer  50  and vaporized in the vaporizer  50 . Also, the source material vaporized by the vaporizer  50  may be supplied to the reaction chamber  10 . 
     The modifier supply apparatus  60   a  may be an apparatus configured to supply the modifier  14  into the reaction chamber  10 . The modifier  14  may be stored in the modifier supply apparatus  60   a  and supplied from the modifier supply apparatus  60   a  into the reaction chamber  10  through a conduit  62 . 
     The modifier supply apparatus  60   a  may be connected to the reaction chamber  10  by the conduit  62 , and the conduit  62  may include a flow rate control device  64  capable of controlling a flow rate of the modifier  14 . 
     The reaction material supply apparatus  80   a  may be an apparatus configured to supply the reaction material  18  into the reaction chamber  10 . The reaction material  18  may be stored in the reaction material supply apparatus  80   a  and supplied from the reaction material supply apparatus  80   a  into the reaction chamber  10  through a conduit  82 . 
     The reaction material supply apparatus  80   a  may be connected to the reaction chamber  10  by the conduit  82 , and the conduit  82  may include a flow rate control device  84  capable of controlling a flow rate of the reaction material  18 . 
     The purge gas supply apparatus  90   a  may be an apparatus configured to supply the purge gas  19  into the reaction chamber  10 . The purge gas  19  may be stored in the purge gas supply apparatus  90   a  and supplied from the purge gas supply apparatus  90   a  into the reaction chamber  10  through a conduit  92 . 
     The purge gas supply apparatus  90   a  may be connected to the reaction chamber  10  by the conduit  92 , and the conduit  92  may include a flow rate control device  94  capable of controlling a flow rate of the purge gas  19 . 
     The conduits  42 ,  52 ,  62 ,  82 , and  92  may be conduits through which fluids may flow, and the flow rate control devices  44 ,  54 ,  64 ,  84 , and  94  may include valve systems capable of controlling the flows of the fluids. 
     The process material supply system  20   a  may be a system capable of independently supplying the modifier  14 , the source material  16 , the purge gas  19 , and the reaction material  18  into the reaction chamber  10 . The process material supply system  20   a  may be configured to supply the modifier  14 , the source material  16 , the purge gas  19 , and the reaction material  18  into the reaction chamber  10  for different time durations or at the same time. 
     The source material may be a material indicated by MLn as described above. The source material may be a material that may be indicated by M(La)n(Lb)m. Here, La may be a first ligand combined with the central atom M, and Lb may be a second ligand that is combined with the central atom M and different from the first ligand. Here, n may be a number that is determined by the central atom M and the ligand La, and m may be a number that is determined by the central atom M and the ligand Lb. 
     When the central atom M is zirconium (Zr), the source material may be, for example, at least one selected from the group consisting of (cyclopentadienyl)tris(dimethylamino)zirconium (CpZr(NMe 2 ) 3 ), tetrakis-ethylmethylamido-zirconium (TEMAZ), tetrakis-diethylamido-zirconium (TDEAZ), tetrakis-dimethylamido-zirconium (TDMAZ), tetrakis-ethyldimethylamido-zirconium, tetrakis-diethylmethylamido-zirconium, tetrakis-triethylamido-zirconium, tetrakis-triethylamido-zirconium, bis-diisopropylamido-bis-dimethylamido-zirconium, bis-di-t-butylamido-bis-dimethylamido-zirconium, bis-ethylmethylamido-bis-diisopropylamido-zirconium, bis-diethylamido-bis-diisopropylamido-zirconium, tris-diisopropylamido-dimethylamido-zirconium, zirconium t-butoxide (Zr(OtBu) 4 , abbreviated as ZTB), tetrakis(1-methoxy-2-methyl-2-propoxy) hafnium (Zr(mmp) 4 ), tetrakis(1-methoxy-2-methyl-2-propoxy) zirconium (Zr(mmp) 4 ), zirconium tetrachloride (ZrCl 4 ), ZrCp 2 Me 2 , Zr(tBuCp) 2 Me 2 , Zr(N(iProp) 2 ) 4 , and tris-diethylamido-diisopropylamido-zirconium, but is not limited thereto. 
     When the central atom M is aluminum (Al), the source material may be, for example, at least one selected from the group consisting of trimethyl aluminum (TMA), triethyl aluminum (TEA), 1-methylpyrrolidine alane (MPA), dimethylethylamine alane (DMEAA), dimethyl aluminum hydride (DMAH), and trimethylaminealane borane (TMAAB), but is not limited thereto. 
     When the central atom M is titanium (Ti), the source material may be, for example, at least one selected from the group consisting of titanium tetrakis(isopropoxide) (Ti(O-iProp) 4 ), a titanium halide, cyclopentadienyl titanium, titanium bis(isopropoxide)bis(2,2,6,6-tetramethyl-3,5-heptanedionate) (Ti(O-iProp) 2 (thd) 2 ), titanium bis(4-(2-methylethoxy)imino-2-pentanoate)(Ti(2meip) 2 ), titanium bis[4-(ethoxy)imino-2-pentanoate](Ti(eip) 2 ), and titanium bis [2,2-dimethyl-5-(2-methylethoxy)imino-3-heptanoate](Ti(22dm2meih) 2 ), but is not limited thereto. 
     When the central atom M is hafnium (Hf), the source material may be, for example, at least one selected from the group consisting of hafnium t-butoxide (Hf(OtBu) 4 , abbreviated as HTB), tetrakis(diethylamido)hafnium, (Hf(NEt 2 ) 4 , abbreviated as TDEAH), tetrakis(ethylmethylamido)hafnium, (Hf(NEtMe) 4 , abbreviated as TEMAH), and tetrakis(dimethylamido)hafnium (Hf(NMe 2 ) 4 , abbreviated as TDMAH), but is not limited thereto. 
     As described above, the modifier may be a material denoted by R—O—R′. For example, the modifier may include at least one selected from the group consisting of dimethylether, diethylether, methylethylether, propylether, methylpropylether, isopropylether, methylisopropylether, dichloroethyl ether, di-n-butyl ether, isoamyl ether, methylphenyl ether, di-n-propylether, diisopropylether, di-sec-butylether, diphenylether, ethylbutylether, butylvinylether, anisole, ethylphenylether, ethyleneglycol dimethylether, ethyleneglycol diethylether, ethyleneglycol dibutylether, diethyleneglycol dimethylether, diethyleneglycol diethylether, furan, tetrahydrofuran, α-methoxytetrahydrofuran, pyran, tetrahydropyran, dioxane, ethyleneglycol monomethylether, and ethyleneglycol mono ethylether, but is not limited thereto. 
     A kind of source material that may be used in a method of forming a material layer according to example embodiments is not limited to the above-described examples. For example, the source material  16  that may be used in operation S 21   a  of  FIG. 2  may include a compound of any one of a metal and a semimetal and at least one organic coordination compound selected from the group consisting of an alcohol compound, a glycol compound, a β-diketone compound, a cyclopentadiene compound, and an organic amine compound. 
     An organic amine compound that may be used as the organic coordination compound of the source material  16  used in operation S 21   a  of  FIG. 2  may be, for example, methylamine, ethylamine, propylamine, isopropylamine, dimethylamine, diethylamine, dipropylamine, diisopropylamine, ehtylmethylamine, propylmethylamine, or isopropylmethylamine, but example embodiments of the inventive concepts are not limited thereto. 
     An alcohol compound that may be used as the organic coordination compound of the source material  16  used in operation S 21   a  of  FIG. 2  may be, for example, alkyl-alcohols such as methanol, ethanol, propanol, isopropyl alcohol, butanol, sec-butyl alcohol, isobutyl alcohol, tert-butyl alcohol, pentyl alcohol, isopentyl alcohol, tert-pentyl alcohol; ether-alcohols such as 2-methoxyethanol, 2-ethoxyethanol, 2-butoxyethanol, 2-(2-methoxyethoxy)ethanol, 2-methoxy-1-methylethanol, 2-methoxy-1,1-dimethylethanol, 2-ethoxy-1,1-dimethylethanol, 2-propoxy-1,1-diethylethanol, 2-butoxy-1,1-diethylethanol, 2-(2-methoxyethoxy)-1,1-dimethylethanol, 2-propoxy-1,1-diethylethanol, 2-s-butoxy-1,1-diethylethanol, and 3-methoxy-1,1-dimethylpropanol; and dialkylaminoalcohol, but example embodiments of the inventive concepts are not limited thereto. 
     A glycol compound that may be used as the organic coordination compound of the source material  16  used in operation S 21   a  of  FIG. 2  may be, for example, 1,2-ethanediol, 1,2-propanediol, 1,3-propanediol, 2,4-hexanediol, 2,2-dimethyl-1,3-propanediol, 2,2-diethyl-1,3-propanediol, 1,3-butanediol, 2,4-butanediol, 2,2-diethyl-1,3-butanediol, 2-ethyl-2-butyl-1,3-propanediol, 2,4-pentanediol, 2-methyl-1,3-propanediol, 2-methyl-2,4-pentanediol, 2,4-hexanediol, and 2,4-dimethyl-2,4-pentanediol, but example embodiments of the inventive concepts are not limited thereto. 
     A β-diketone compound that may be used as the organic coordination compound of the source material  16  used in operation S 21   a  of  FIG. 2  may be, for example, alkyl-substituted β-diketones such as acetylacetone, hexane-2,4-dione, 5-methylhexane-2,4-dione, heptane-2,4-dione, 2-methylheptane-3,5-dione, 5-methylheptane-2,4-dione, 6-methylheptane-2,4-dione, 2,2-dimethylheptane-3,5-dione, 2,6-dimethyl heptane-3,5-dione, 2,2,6-trimethylheptane-3,5-dione, 2,2,6,6-tetramethylheptane-3,5-dione, octane-2,4-dione, 2,2,6-trimethyloctane-3,5-dione, 2,6-dimethyloctane-3,5-dione, 2,9-dimethyl nonane-4,6-dione, 2-methyl-6-ethyldecane-3,5-dione, and 2,2-dimethyl-6-ethyldecane-3,5-dione; fluorine-substituted alkyl β-diketones such as 1,1,1-trifluoropentane-2,4-dione, 1,1,1-trifluoro-5,5-dimethylhexane-2,4-dione, 1,1,1,5,5,5-hexafluoropentane-2,4-dione, and 1,3-diperfluorohexylpropane-1,3-dione; and ether-substituted β-diketones such as 1,1,5,5-tetramethyl-1-methoxyhexane-2,4-dione, 2,2,6,6-tetramethyl-1-methoxyheptane-3,5-dione, and 2,2,6,6-tetramethyl-1-(2-methoxyethoxy)heptane-3,5-dione, but example embodiments of the inventive concepts are not limited thereto. 
     A cyclopentadiene compound that may be used as the organic coordination compound of the source material  16  used in operation S 21   a  of  FIG. 2  may be, for example, cyclopentadiene, methylcyclopentadiene, ethylcyclopentadiene, propylcyclopentadiene, isopropylcyclopentadiene, butylcyclopentadiene, sec-butylcyclopentadiene, isobutyl cyclopentadiene, tert-butylcyclepentadiene, dimethyl cyclopentadiene, or tetramethylcyclopentadiene, but example embodiments of the inventive concepts are not limited thereto. 
     As described with reference to  FIGS. 1 to 3 , according to example embodiments, the modifier  14  and the source material  16  may be supplied into the reaction chamber  10  and the reaction material  18  may be then supplied into the reaction chamber  10 , thereby growing a material layer. 
       FIG. 4A  is a schematic diagram of a semiconductor apparatus  2  configured to perform a method of forming a material layer according to other example embodiments. The semiconductor apparatus  2  shown in  FIG. 4A  may be the same as the semiconductor apparatus  1  shown in  FIG. 3  except that a vaporizer  70   a  is used to supply a modifier  14 . Accordingly, repeated descriptions will be omitted, and differences between the semiconductor apparatus  2  shown in  FIG. 4A  and the semiconductor apparatus  1  shown in  FIG. 3  will mainly be described. 
     Referring to  FIG. 4A , a modifier supply apparatus  60   a  may be an apparatus configured to supply the modifier into a reaction chamber  10 . The modifier supply apparatus  60   a  may include a canister configured to supply the modifier  14 . The canister may be configured to uniformly supply the modifier  14  into the reaction chamber  10 . 
       FIG. 4B  is a schematic diagram of the modifier supply apparatus  60   a  configured to uniformly supply the modifier  14 . 
     Referring to  FIG. 4B , the modifier supply apparatus  60   a  may include a canister  60   c  configured to contain the modifier  14 , a pressurizing nozzle  61  capable of supplying a pressurizing fluid into the canister  60   c , and a discharge nozzle  63  capable of discharging the modifier  14  pressurized by the pressurizing fluid out of the canister  60   c.    
     An end portion  61 E of the pressurizing nozzle  61  may be configured not to be immersed in the modifier  14 . In other words, the end portion  61 E of the pressurizing nozzle  61  may be disposed higher than a liquid level L of the modifier  14 . 
     The pressurizing fluid supplied through the pressurizing nozzle  61  may be an arbitrary fluid, which may be neither reactive with the modifier  14  nor easily mixed with the modifier  14  but have a lower specific gravity than the modifier  14  to form 2-phase system with the modifier  14 . In some example embodiments, the pressurizing fluid may be a low reactive gas or a non-reactive gas, such as nitrogen (N 2 ), helium (He), neon (Ne), argon (Ar), and carbon dioxide (CO 2 ). 
     The pressurizing fluid supplied through the pressurizing nozzle  61  may pressurize a liquid-level surface of the modifier  14 , so that the pressurized modifier  14  may be supplied into a flow rate control device  64  through the discharge nozzle  63 . For this reason, an end portion  63 E of the discharge nozzle  63  may be configured to be immersed in the modifier  14 . In other words, the end portion  63 E of the discharge nozzle  63  may be disposed lower than the liquid level L of the modifier  14 . 
     In conclusion, the liquid level L of the modifier  14  may be controlled to be between a level of the end portion  61 E of the pressurizing nozzle  61  and a level of the end portion  63 E of the discharge nozzle  63 . 
     The modifier supply apparatus  60   a  may supply the modifier  14  in liquid phase to the flow rate control device  64 . After a flow rate of the modifier  14  is uniformly controlled by the flow rate control device  64 , the modifier  14  may be vaporized by the vaporizer  70   a . Accordingly, the amount of the modifier  14  supplied into the reaction chamber  10  may be uniformly controlled. In some embodiments, the flow rate of the modifier  14  can be uniformly controlled even without the flow rate control device  64  if only the pressurizing fluid is uniformly supplied. 
       FIG. 4C  is a schematic diagram of a modifier supply apparatus according to a conventional art. Referring to  FIG. 4C , a carrier gas may be supplied through a supply nozzle  61 B. In this case, an end portion  64 BE of the supply nozzle  61 B is immersed in the modifier  14 . The carrier gas is supplied in the form of bubbles into the modifier  14  through the end portion  64 BE of the supply nozzle  61 B. While the carrier gas passes through the modifier  14  and moves to a free surface of the modifier  14 , the modifier  14  vaporizes into the bubbles. The vaporized modifier  14  is supplied along with the carrier gas into a reaction chamber  10  through a discharge nozzle  63 B. Here, an end portion of the discharge nozzle  63 B is not immersed in the modifier  14  so as to discharge the vaporized modifier  14  and the carrier gas. 
     As shown in  FIG. 4C , the carrier gas supplied through the end portion  61 BE of the supply nozzle  61 B may move by a height Δh and reach the free surface of the modifier  14 . The height Δh may vary depending on a liquid level of the modifier  14 . That is, when the liquid level of the modifier  14  is high, the height Δh may be great, whereas when the liquid level of the modifier  14  is low, the height Δh may be small. When the height Δh is relatively great, the time taken to vaporize the modifier  14  into the bubbles may be relatively long so that the modifier  14  may be supplied into the reaction chamber  10  at a relatively high concentration. Conversely, when the height Δh is relatively small, the time taken to vaporize the modifier  14  into the bubbles may be relatively short so that the modifier  14  may be supplied into the reaction chamber  10  at a relatively low concentration. This difference in concentration may be one cause of instability of step coverage in a subsequent process of depositing a material layer having a fine thickness. 
     Therefore, the modifier supply apparatus  60   a  shown in  FIG. 4B , according to an example embodiment, may provide a better step coverage than the modifier supply apparatus shown in  FIG. 4C . 
       FIGS. 5A to 5G  are timing diagrams of the order of methods of supplying the modifier, the source material, and the reaction material as described with reference to  FIG. 2 . 
     In  FIGS. 5A to 5G , each of feed materials may be pulse-supplied. Flow rates and feeding times of the respective feed materials may not be proportional to the heights and widths of pulses shown in  FIGS. 5A to 5G . 
     Referring to  FIG. 5A , after a modifier  14  is supplied into a reaction chamber  10 , a source material  16  may be supplied into the reaction chamber  10 . 
     When the modifier  14  is supplied into the reaction chamber  10 , the modifier  14  may be physisorbed on a surface of a substrate  100 . The reaction chamber  10  may be purged with a purge gas  19  so that the physisorbed modifier  14  may be one monolayer or less. 
     Thereafter, when the source material  16  is supplied, the source material  16  may be physisorbed on the surface of the substrate  100  while the chemisorption of the source material  16  on the substrate  100  is being controlled. Although the source material  16  may be directly chemisorbed on the substrate  100 , since a considerable portion of the surface of the substrate  100  is covered with the modifier  14 , the source material  16  may be physisorbed on the substrate  100  via the modifier  14 . When the reaction chamber  10  is purged with the purge gas  19  again, an adsorption layer may be obtained by adsorbing the source material  16  on the level of one monolayer or less. In particular, excessive adsorption of the source material  16  may be considerably controlled at an entrance of a structure. 
     Thereafter, when the reaction material  18  is supplied, the reaction material  18  may be reacted with the adsorbed source material  16  to form a material layer, and the modifier  14  may be reacted with the reaction material  18  and removed. When the reaction chamber  10  is purged with a purge gas  19 , excessive amounts of reaction material  18  and the reaction byproducts may be removed from the reaction chamber  10 . 
     Referring to  FIG. 5B , after the source material  16  is supplied into the reaction chamber  10 , the modifier  14  may be supplied. 
     When the source material  16  is supplied into the reaction chamber  10 , the source material  16  may be adsorbed on the surface of the substrate  100 . In this case, although the source material  16  may be physisorbed on the substrate  100 , a considerable amount of source material  16  may be chemisorbed on the substrate  100 . In other words, the source material  16  may be directly chemisorbed on the substrate  100 , while additional source materials  16  may be physisorbed on the substrate  100  via the chemisorbed source material  16 . 
     When the reaction chamber  10  is purged with the purge gas  19 , at least two layers of the source material  16  physisorbed on the substrate  100  may be partially removed, while the physisorbed source material  16  may still remain on the source material  16  that is directly chemisorbed on the substrate  100 . Since the physisorbed source material  16  is an excessively adsorbed source material, it may be necessary to remove the physisorbed source material  16  to form a conformal material layer. 
     Subsequently, when the modifier  14  is supplied, the modifier  14  may be combined with the source material  16  due to van der Waals attraction. More specifically, when the modifier  14  is an ether-based material, oxygen contained in ether may be combined with the central atom of the source material. The physisorbed source material  16  may be released due to the combination, and the excessively adsorbed source material  16  may be mostly removed. When the reaction chamber  10  is purged with the purge gas  19  again, the excessive modifier  14  and the reaction byproducts may be removed from the reaction chamber  10 , and a layer at which the source material  16  is chemisorbed on the level of one monolayer or less may be obtained. The reaction byproducts may include a combination of the modifier  14  with the source material  16 . 
     Subsequently, when the reaction material  18  is supplied, the reaction material  18  may be reacted with the source material  16  that is chemisorbed in a monolayered state to form a material layer, and the modifier  14  may be reacted with the reaction material  18  and removed. When the reaction chamber  10  is purged with the purge gas  19 , excessive amounts of reaction material  18  and the reaction byproducts may be removed from the reaction chamber  10 . 
     Referring to  FIG. 5C , the source material  16  and the modifier  14  may be simultaneously supplied into the reaction chamber  10 . 
     Due to characteristics of the source materials  16 , the source materials  16  may be combined with each other and form a dimer or trimer. When the dimer or trimer is adsorbed on the surface of the substrate  100 , at least two layers of the source material  16  may be excessively adsorbed. When the modifier  14  and the source material  16  are simultaneously supplied, a probability of the source material  16  forming the dimer or trimer may be reduced so that the excessive adsorption of the source material  16  may be alleviated. 
     Furthermore, mechanisms described with reference to  FIGS. 5A and 5B  may be dynamically performed to prevent excessive adsorption of the source material  16 . 
     When the reaction chamber  10  is purged with the purge gas  19 , excessive amounts of the source material  16  and the modifier  14  may be removed from the reaction chamber  10 . Also, unnecessary byproducts may be removed from the reaction chamber  10 . 
     Thereafter, when the reaction material  18  is supplied, the reaction material  18  may be reacted with the adsorbed source material  16  to form a material layer, and the modifier  14  in the reaction chamber  10  may be reacted with the reaction material  18  and removed. When the reaction chamber  10  is purged with the purge gas  19 , excessive amounts of the reaction material  18  and the reaction byproducts may be removed from the reaction chamber  10 . 
     Referring to  FIG. 5D , after the source material  16  is supplied into the reaction chamber  10 , the modifier  14  may be supplied into the reaction chamber  10 . In this case, a time duration for which the source material  16  is supplied may overlap with a time duration for which the modifier  14  is supplied for a predetermined (or, alternatively, set) time OL. 
     In this case, excessive adsorption of the source material  16  may be prevented due to the reaction mechanism described above with reference to  FIG. 5B  during a time duration for which the supplying of the source material  16  does not overlap with the supplying of the modifier  14 . Also, excessive adsorption of the source material  16  may be prevented due to the reaction mechanisms described with reference to  FIGS. 5A and 5B  during a time duration for which the supplying of the source material  16  overlaps with the supplying of the modifier  14 . 
     Other detailed descriptions are the same as described with reference to  FIGS. 5A to 5C  and will be omitted here. 
     Referring to  FIG. 5E , the modifier  14  may be supplied all around a time duration for which the source material  16  is supplied into the reaction chamber  10 . Excessive adsorption of the source material  16  may be prevented due to the modifier  14  supplied before the source material  16 , as described with reference to  FIG. 5A . Also, excessive adsorption of the source material  16  may be prevented due to the modifier  15  supplied after the source material  16 , as described with reference to  FIG. 5B . 
     Other detailed descriptions are the same as described with reference to  FIGS. 5A to 5C  and will be omitted here. 
     Referring to  FIG. 5F , the present example embodiments differ from the example embodiments shown in  FIG. 5A  in that a first source material and a second source material, which are different source materials, are used. 
     To begin with, a modifier  14  may be supplied into a reaction chamber  10 , and the reaction chamber  10  may be purged to form a monolayer of a physisorbed modifier  14 . A first source material and a reaction material may be supplied to form a first material layer. Since a specific reaction mechanism is the same as described with reference to  FIG. 5A , additional descriptions thereof are omitted here. 
     Thereafter, the modifier  14  may be supplied again into the reaction chamber  10 , and the reaction chamber  10  may be purged to form a monolayer of a physisorbed modifier  14 . A second source material and a reaction material may be supplied to form a second material layer. Since a specific reaction mechanism is the same as described with reference to  FIG. 5A , additional descriptions thereof are omitted here. 
     Referring to  FIG. 5G , the present example embodiments differ from the example embodiments shown in  FIG. 5B  in that a first source material and a second source material, which are different source materials, are used. 
     To begin with, the first source material may be supplied into the reaction chamber  10 , and the reaction chamber  10  may be purged to form a first source material layer, which is adsorbed on the surface of a substrate. The modifier  14  may be supplied to remove an excessively adsorbed first source material. Thereafter, a reaction material may be supplied to form a first material layer. Since a specific reaction mechanism is the same as described with reference to  FIG. 5B , additional descriptions thereof are omitted here. 
     Subsequently, the second source material may be supplied into the reaction chamber  10 , and the reaction chamber  10  may be purged to form a second source material layer, which is adsorbed on the surface of the substrate. The modifier  14  may be supplied to remove an excessively adsorbed second source material. Thereafter, a reaction material may be supplied to form a second material layer. Since a specific reaction mechanism is the same as described with reference to  FIG. 5B , additional descriptions thereof are omitted here. 
       FIG. 6  is a detailed flowchart of an operation of forming a material layer on the substrate, according to some example embodiments. 
     Referring to  FIG. 6 , a source material  16  may be provided on a substrate  100  (S 21   b ). The source material  16  may be adsorbed on the substrate  100 . In this case, the source material may be excessively physisorbed on portions of the substrate to form two or more layers of the source material. 
     Subsequently, the reaction chamber  10  may be purged with a purge gas (S 22   b ). An excessive amount of source material adsorbed on the substrate  100  may be removed due to the purge process. 
     Thereafter, a reaction material  18  and a modifier  14  may be supplied into the reaction chamber  10 . Since the reaction material  18  and the modifier  14  are described in detail above, detailed descriptions thereof are omitted. 
       FIGS. 7A to 7D  are timing diagrams of a method and order of supplying the modifier, the source material, and the reaction material as in  FIG. 6 . 
     Referring to  FIG. 7A , the reaction material  18  and the modifier  14  may be supplied such that the supplying of the reaction material  18  temporally overlaps with the supplying of the modifier  14 . 
     To begin, when the source material  16  is supplied into a reaction chamber  10 , the source material  16  may be adsorbed on the surface of a substrate  100 . The reaction chamber  10  may be purged with a purge gas  19  to remove an excessive amount of the source material  16 . 
     Thereafter, the reaction material  18  and the modifier  14  may be simultaneously supplied for the same time duration. After that, the reaction chamber  10  may be purged with the purge gas  19  so that excessive amounts of the reaction material  18  and the modifier  14  and the reaction byproducts may be removed from the reaction chamber  10 . 
     Referring to  FIG. 7B , after the modifier  15  is fed into the reaction chamber  10 , the reaction material  18  may be supplied into the reaction chamber  10 . In this case, a time duration for which the modifier  15  is supplied may overlap with a time duration for which the reaction material  18  is supplied for a predetermined (or, alternatively, set) time OL. 
     To begin, when the source material  16  is supplied into the reaction chamber  10 , the source material  16  may be adhered on the surface of the substrate  100 . The reaction chamber  10  may be purged with the purge gas  19  to remove an excessive amount of the source material  16 . 
     Thereafter, the modifier  14  may be supplied to induce the reaction mechanism described with reference to  FIG. 5B , the reaction material  18  may be then supplied to form a material layer. 
     Thereafter, the reaction chamber  10  may be purged with the purge gas  19  so that excessive amounts of the reaction material  18  and the modifier  14  and the reaction byproducts may be removed from the reaction chamber  10 . 
     Referring to  FIG. 7C , after the reaction material  18  is supplied into the reaction chamber  10 , the modifier  14  may be supplied into the modifier  14 . In this case, a time duration for which the reaction material  18  is supplied may overlap with a time duration for which the modifier  14  is supplied for a predetermined (or, alternatively, set) time OL. 
     To begin with, when the source material  16  is supplied into the reaction chamber  10 , the source material  16  may be adsorbed on the surface of the substrate  100 . The reaction chamber  10  may be purged with the purge gas  19  to remove an excessive amount of the source material  16 . 
     Thereafter, the reaction material  18  may be supplied to form a material layer. Subsequently, the modifier  14  may be supplied to induce the reaction mechanism described with reference to  FIG. 5A  and contribute toward preventing excessive adsorption. 
     Thereafter, the reaction chamber  10  may be purged with the purge gas  19  so that excessive amounts of the reaction material  18  and the modifier  14  and the reaction byproducts may be removed from the reaction chamber  10 . 
     Referring to  FIG. 7D , a time period for which the reaction material  18  is supplied into the reaction chamber  10  may be nested in a time period for which the modifier  14  is supplied. 
     To begin, when the source material  16  is supplied into the reaction chamber  10 , the source material  16  may be adsorbed on the surface of the substrate  100 . The reaction chamber  10  may be purged with the purge gas  19  to remove an excessive amount of the source material  16 . 
     Thereafter, the modifier  14  may be continuously supplied into the reaction chamber  10  from before the supplying of the reaction material  18  has started to after the supplying of the reaction material  18  is ended. Thus, excessive adsorption of the source material  16  may be prevented due to the reaction mechanisms described with reference to  FIGS. 5A to 5C . 
     Thereafter, the reaction chamber  10  may be purged with a purge gas  19  so that byproducts of a reaction of the excessive reaction material  18  with the modifier  14  may be removed from the reaction chamber  10 . 
     Experimental Example 1 
     A zirconium oxide (ZrO 2 ) material layer was formed on a bare silicon substrate without a modifier by using TEMAZ as a source material and using ozone (O 3 ) serving as an oxidizer as a reaction material. 
     Also, ZrO 2  material layers were respectively formed by using methanol and tetrahydrofuran (THF) as modifiers according to a timing scheme shown in  FIG. 5A . 
     In particular, after the material layer was adsorbed on a silicon substrate by supplying the modifier, a deposition rate (Å/cycle) of the material layer was calculated while varying a purge time.  FIG. 8  is a graph of the deposition rate of the material layer relative to the purge time. 
     As a result, when methanol was used as the modifier, even if a purge time of about 400 seconds elapsed, a deposition rate of the ZrO 2  material layer was not saturated. By comparison, when THF was used as the modifier, after an initial purge time of about 5 seconds elapsed, it could be confirmed that the deposition rate of the ZrO 2  material layer was immediately stabilized. 
     While not wishing to be bound to a specific theory, it is believed that when methanol was used as the modifier, the deposition rate of the material layer was rapidly reduced before an elapse of about 100 seconds due to the desorption of a modifier. 
     Experimental Example 2 
     A ZrO 2  material layer was formed on a bare silicon substrate without a modifier by using TEMAZ as a source material and using ozone serving as an oxidizer as a reaction material. 
     Also, ZrO 2  material layers were respectively formed by using methanol and THF as modifiers according to the timing scheme shown in  FIG. 5A . 
     In particular, a deposition rate (Å/cycle) of the material layer was calculated while varying a feeding time of the modifier.  FIG. 9  is a graph of the deposition rate of the material layer relative to the feeding time of the modifier. 
     As a result, when methanol was used as the modifier, it was confirmed that the deposition rate of the ZrO 2  material layer was continuously reduced until a feeding time reached about 60 seconds. When THF was used as the modifier, the deposition rate of the ZrO 2  material layer was continuously reduced for about 3 seconds. However, when a feeding time became more than 3 seconds, it was confirmed that the deposition rate of the ZrO 2  material layer was immediately stabilized. 
     While not wishing to be bound to a specific theory, it is believed from Experimental Examples 1 and 2 that the above-described results were obtained because THF serving as an ether-based modifier is less sensitive to process parameters, such as a process pressure, a purge time, and a process temperature, than methanol serving as an alcohol-based modifier. 
     Experimental Example 3 
     To observe whether or not a step coverage is improved when an oxide layer is deposited using a modifier in an actual trench structure, ALD experiments were conducted by using methanol and THF as modifiers. A trench having a width of about 50 nm, a depth of about 350 nm, and an aspect ratio of about 7 was used as a target trench structure, and a ZrO 2  material layer was formed by using TEMAZ as a source material and using ozone (O 3 ) serving as an oxidizer as a reaction material. 
     A feeding scheme of each feed material was carried out according to the feeding scheme shown in  FIG. 5A . By supplying the modifier for about 5 seconds and 400 seconds, thicknesses of formed ZrO 2  material layers were measured at a top and a bottom portion of a trench. 
     As a result, Table 1 was obtained. 
     
       
         
           
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                   
                 Methanol 
                 THF 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 Modifier 
                 5 sec 
                 400 sec 
                 5 sec 
                 400 sec 
               
               
                 feeding time 
                   
                   
                   
                   
               
               
                 Top of trench 
                 85 Å 
                 70 Å 
                 90 Å 
                 94 Å 
               
               
                 Bottom of 
                 79 Å 
                 49 Å 
                 83 Å 
                 89 Å 
               
               
                 trench 
                   
                   
                   
                   
               
               
                 Step coverage 
                 93% 
                 70% 
                 92% 
                 95% 
               
               
                   
               
            
           
         
       
     
     When methanol was used as the modifier and supplied for a short feeding time duration of about 5 seconds, it was possible to ensure a step coverage of about 93%. However, when the feeding time duration was increased to about 400 seconds, a thickness of a ZrO 2  material layer formed on a bottom surface of a trench became much smaller than a thickness of a ZrO 2  material layer formed on an upper portion of the trench. As a result, the step coverage was reduced to about 70%. 
     When THF was used as the modifier and supplied for a feeding time duration of about 5 seconds, it was possible to ensure a step coverage of about 92%. Also, even if the feeding time duration was increased to about 400 seconds, it was still possible to ensure a good step coverage of about 95%. 
     While not wishing to be bound to a specific theory, it is believed that an ether-based modifier is a more stable modifier than an alcohol-based modifier based on the results of Table 1. When the ether-based modifier is used, a good step coverage may be stably obtained despite variations in other process parameters. 
     By using a method of forming a material layer according to some example embodiments, a material layer having a good step coverage may be stably formed despite variations in other process parameters. 
     Experimental Example 4 
     A modifier was supplied into a reaction chamber by using a bubbler shown in  FIG. 4C  as a modifier supply apparatus. In this case, since the modifier was supplied in gaseous phase from the discharge nozzle  63   b , the modifier was directly supplied into the reaction chamber without a vaporizer. 
     After one day elapsed since a change of canister, a step coverage SC 1  was measured when a liquid level of the modifier was about 80% of a height of the canister. Also, after 14 days elapsed since a change of canister, a step coverage SC 2  was measured when the liquid level of the modifier was about 20% of a height of the canister. As a result, it was detected that the step coverage SC 2  was about 2% poorer than the step coverage SC 1 . 
     Experimental Example 5 
     A modifier was supplied into a reaction chamber by using the modifier supply apparatus shown in  FIG. 4B  as a modifier supply apparatus. In this case, since the modifier was supplied in liquid phase from the discharge nozzle  63 , the modifier was supplied into the reaction chamber through a vaporizer. 
     After one day elapsed since a change of canister, a step coverage SC 3  was measured when a liquid level of the modifier was about 80% of a height of the canister. Also, after 14 days elapsed since a change of canister, a step coverage SC 4  was measured when the liquid level of the modifier was about 20% of a height of the canister. As a result, there was no substantial difference between the step coverage SC 3  and the step coverage SC 4 . 
     As examined in Experimental Example 4, when a bubbler method was used, it was discovered that a liquid level varied with respect to time and a variation in liquid level affected a step coverage of a material layer deposited in the reaction chamber. 
     It was confirmed via Experimental Example 5 that the above-described problem could be solved by supplying the modifier in liquid phase, vaporizing the modifier by using the vaporizer, and supplying the vaporized modifier into the reaction chamber. 
       FIGS. 10A to 10J  are cross-sectional views of sequential process operations of a method of manufacturing an IC device (refer to  FIG. 10J ) according to example embodiments. 
     Referring to  FIG. 10A , an interlayer insulating layer  320  may be formed on a substrate  310  including a plurality of active regions AC. Thereafter, a plurality of conductive regions  324  may be formed through the interlayer insulating layer  320  and connected to the plurality of active regions AC. 
     The substrate  310  may include a semiconductor (e.g., silicon or germanium) or a compound semiconductor (e.g., SiGe, SiC, GaAs, InAs, or InP). In some example embodiments, the substrate  310  may include at least one of a Group III-V material and a Group IV material. The Group III-V material may be a binary compound, a ternary compound, or a quaternary compound including at least one Group III atom and at least one Group V atom. The Group III-V material may be compound including a Group III atom (e.g., at least one atom of In, Ga, and Al) and a Group V atom (e.g., at least one atom of As, P, and Sb). For example, the Group III-V material may be selected from InP, In z Ga 1-z As (0≦z≦1), and Al z Ga 1-z As (0≦z≦1). The binary compound may be, for example, any one of InP, GaAs, InAs, InSb, and GaSb. The ternary compound may be any one of InGaP, InGaAs, AlInAs, InGaSb, GaAsSb, and GaAsP. The Group IV material may be silicon or germanium. However, the Group III-V material and the group IV material that may be used for an IC device according to example embodiments are not limited to the above-described examples. In some example embodiments, the substrate  310  may have a silicon-on-insulator (SOI) structure. The substrate  310  may include a conductive region, for example, a doped well or a doped structure. 
     The plurality of active regions AC may be defined by a plurality of device isolation regions  312  formed in the substrate  310 . The device isolation regions  312  may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. 
     The interlayer insulating layer  320  may include a silicon oxide layer. 
     The plurality of conductive regions  324  may be connected to one terminal of switching devices (not shown) (e.g., field-effect transistors (FETs)) formed on the substrate  310 . The plurality of conductive regions  324  may include poly-Si, a metal, a conductive metal nitride, a metal silicide, or a combination thereof, but example embodiments of the inventive concepts are not limited thereto. 
     Referring to  FIG. 10B , an insulating layer  328  may be formed to cover the interlayer insulating layer  320  and the plurality of conductive regions  324 . The insulating layer  328  may be used as an etch stop layer. 
     The insulating layer  328  may include an insulating material having an etch selectivity with respect to the interlayer insulating layer  320  and a mold layer  330  (refer to  FIG. 10C ) formed during a subsequent process. In some example embodiments, the insulating layer  328  may include silicon nitride, silicon oxynitride, or a combination thereof. 
     In some example embodiments, the insulating layer  328  may be formed to a thickness of about 100 Å to about 600 Å, but example embodiments of the inventive concepts are not limited thereto. 
     Referring to  FIG. 10C , the mold layer  330  may be formed on the insulating layer  328 . 
     In some example embodiments, the mold layer  330  may include an oxide layer. For example, the mold layer  330  may include an oxide layer, such as a boro phospho silicate glass (BPSG) layer, a phospho silicate glass (PSG) layer, an undoped silicate glass (USG) layer, a spin on dielectric (SOD) layer, or an oxide layer formed by using a high-density-plasma chemical vapor deposition (HDP CVD) process. The mold layer  130  may be formed by using a thermal CVD process or a plasma CVD process. In some example embodiments, the mold layer  330  may be formed to a thickness of about 1000 Å to about 20000 Å, but example embodiments of the inventive concepts are not limited thereto. 
     In some example embodiments, the mold layer  330  may include a support layer (not shown). The support layer may include a material having an etch selectivity with respect to the mold layer  330  and have a thickness of about 50 Å to about 3000 Å. When the mold layer  330  is subsequently removed by using a limulus amoebocyte lysate (LAL) lift-off process in an etching atmosphere of, for example, ammonium fluoride (NH 4 F), hydrofluoric acid (HF), and water, the support layer may include a material having a relatively low etch rate with respect to LAL. In some example embodiments, the support layer may include silicon nitride, silicon carbonitride, tantalum oxide, titanium oxide, or a combination thereof, but a material forming the support layer is not limited thereto. 
     Referring to  FIG. 10D , a sacrificial layer  342  and a mask pattern  344  may be sequentially formed on the mold layer  330 . 
     The sacrificial layer  342  may include an oxide layer, such as a BPSG layer, a PSG layer, an USG layer, a SOD layer, or an oxide layer formed by using an HDP CVD process. The sacrificial layer  342  may have a thickness of about 500 Å to about 2000 Å. The sacrificial layer  342  may serve to protect the support layer included in the mold layer  330 . 
     The mask pattern  344  may include an oxide layer, a nitride layer, a poly-Si layer, a photoresist layer, or a combination thereof. A region where a lower electrode of a capacitor will be formed may be defined by the mask pattern  344 . 
     Referring to  FIG. 10E , the sacrificial layer  342  and the mold layer  330  may be dry etched by using the mask pattern  344  as an etch mask and using the insulating layer  328  as an etch stop layer, thereby forming a sacrificial pattern  342 P and a mold pattern  330 P to define a plurality of holes H 1 . 
     In this case, the insulating layer  328  may also be etched due to excessive etching, thereby forming an insulating pattern  328 P to expose a plurality of conductive regions  324 . 
     Referring to  FIG. 10F , after the mask pattern  344  is removed from the resultant structure of  FIG. 10E , a conductive layer  350  for forming a lower electrode may be formed to cover inner sidewalls of the respective holes H 1 , an exposed surface of the insulating pattern  328 P, surfaces of the plurality of conductive regions  324  exposed in the respective holes H 1 , and an exposed surface of the sacrificial pattern  342 P. 
     The conductive layer  350  for forming the lower electrode may be conformally formed on the inner sidewalls of the plurality of holes H to leave partial inner spaces of the respective holes H 1 . 
     In some example embodiments, the conductive layer  350  for forming the lower electrode may include a doped semiconductor, a conductive metal nitride, a metal, a metal silicide, a conductive oxide, or a combination thereof. For instance, the conductive layer  350  for forming the lower electrode may include TiN, TiAlN, TaN, TaAlN, W, WN, Ru, RuO 2 , SrRuO 3 , Ir, IrO 2 , Pt, PtO, SRO (SrRuO 3 ), BSRO ((Ba,Sr)RuO 3 ), CRO (CaRuO 3 ), LSCo ((La,Sr)CoO 3 ), or a combination thereof, but a material forming the conductive layer  350  for forming the lower electrode is not limited thereto. 
     The conductive layer  350  for forming the lower electrode may be formed by using a CVD process, a metal organic CVD (MOCVD) process, or an ALD process. The conductive layer  350  for forming the lower electrode may be formed to a thickness of about 20 nm to about 100 nm, but example embodiments of the inventive concepts are not limited thereto. 
     Referring to  FIG. 10G , an upper portion of the conductive layer  350  for forming the lower electrode may be partially removed so that the conductive layer  350  for forming the lower electrode may be separated into a plurality of lower electrodes LE. 
     To form the plurality of lower electrodes LE, the portion of the upper portion of the conductive layer  350  for forming the lower electrode and the sacrificial pattern  342 P (refer to  FIG. 10F ) may be removed by using an etchback process or a chemical mechanical polishing (CMP) process until a top surface of the mold pattern  330 P is exposed. 
     The plurality of lower electrodes LE may penetrate the insulating pattern  328 P and be connected to the conductive regions  324 . 
     Referring to  FIG. 10H , the mold pattern  330 P may be removed to expose outer wall surfaces of the plurality of lower electrodes LE having cylindrical shapes. 
     The mold pattern  330 P may be removed by a lift-off process using LAL or hydrofluoric acid. 
     Referring to  FIG. 10I , a dielectric layer  360  may be formed on the plurality of lower electrodes LE. 
     The dielectric layer  360  may be formed to conformally cover exposed surfaces of the plurality of lower electrodes LE. 
     The dielectric layer  360  may be formed by using an ALD process. The dielectric layer  360  may be formed by the method of forming the material layer as described with reference to  FIGS. 1 and 2 or 6 . 
     The dielectric layer  360  may include oxide, a metal oxide, nitride, or a combination thereof. In some example embodiments, the dielectric layer  360  may include a ZrO 2  layer. For example, the dielectric layer  360  may include a single ZrO 2  layer or a multilayered structure including a combination of at least one ZrO 2  layer and at least one of Al 2 O 3  layer. 
     In some example embodiments, the dielectric layer  360  may have a thickness of about 50 Å to about 150 Å, but example embodiments of the inventive concepts are not limited thereto. 
     Referring to  FIG. 10J , an upper electrode UE may be formed on the dielectric layer  360 . 
     A capacitor  370  may be configured by the lower electrode LE, the dielectric layer  360 , and the upper electrode UE. 
     The upper electrode UE may include a doped semiconductor, a conductive metal nitride, a metal, a metal silicide, a conductive oxide, or a combination thereof. For example, the upper electrode UE may include TiN, TiAlN, TaN, TaAlN, W, WN, Ru, RuO 2 , SrRuO 3 , Ir, IrO 2 , Pt, PtO, SRO (SrRuO 3 ), BSRO ((Ba,Sr)RuO 3 ), CRO (CaRuO 3 ), LSCo ((La,Sr)CoO 3 ), or a combination thereof, but a material forming the upper electrode UE is not limited thereto. 
     The upper electrode UE may be formed by using a CVD process, an MOCVD process, a physical vapor deposition (PVD) process, or an ALD process. 
     Thus far, the method of manufacturing the IC device  300  including the process of forming the dielectric layer  360  to cover the surfaces of the cylindrical lower electrodes LE has been described with reference to  FIGS. 10A to 10J , but example embodiments of the inventive concepts are not limited thereto. For example, pillar-type lower electrodes having no inner spaces may be formed instead of the cylindrical lower electrodes LE. The dielectric layer  360  may be formed on the pillar-type lower electrodes. 
     In the method of manufacturing the IC device as described with reference to  FIGS. 10A to 10J , the formation of the dielectric layer  360  may include forming an adsorption layer of an ether-based modifier and an adsorption layer of a source material on the lower electrode LE according to a method of forming a material layer according to an example embodiment and forming a material containing central atoms by supplying a reaction material, such as an oxidizer or a reducer. 
     Referring to  FIGS. 11A to 11C , an IC device  400  may include a fin-type active region FA, which may protrude from a substrate  402 . 
     Since the substrate  402  is substantially the same as the substrate  310  described with reference to  FIG. 10A , detailed descriptions thereof are omitted here. 
     The substrate  402  may include a Group III-V material or a Group IV material and be used as a material for a channel of a high-power high-speed transistor. When an NMOS transistor is formed on the substrate  402 , the substrate  402  may include any one of Group III-V materials. For example, the substrate  402  may include GaAs. When a PMOS transistor is formed on the substrate  402 , the substrate  402  may include a semiconductor material (e.g., germanium) having a higher hole mobility than a silicon substrate. 
     The fin-type active region FA may extend in one direction (refer to Y direction in  FIGS. 11A and 11B ). A device isolation layer  410  may be formed on the substrate  402  to cover a lower sidewall of the fin-type active region FA. The fin-type active region FA may protrude as a fin type on the device isolation layer  410 . In some example embodiments, the device isolation layer  410  may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof, but example embodiments of the inventive concepts are not limited thereto. 
     A gate structure  420  may be formed on the substrate  410  and extend over the fin-type active region FA in a direction (X direction) that intersects an extension direction of the fin-type active region FA. One pair of source and drain regions  430  may be formed in the fin-type active region FA on both sides of the gate structure  420 . 
     The one pair of source and drain regions  430  may include a semiconductor layer that is epitaxially grown from the fin-type active region FA. Each of the one pair of source and drain regions  430  may have an embedded silicon germanium (SiGe) structure including a plurality of epitaxially grown silicon germanium layers, an epitaxially grown silicon layer, or an epitaxially grown silicon carbide (SiC) layer.  FIG. 11B  illustrates a case in which the one pair of source and drain regions  430  have a specific shape, but a sectional shape of each of the one pair of source and drain regions  430  is not limited to that shown in  FIG. 11B  and have various shapes. For example, the one pair of source and drain regions  430  may have various sectional shapes, such as a circular sectional shape, an elliptical sectional shape, or a polygonal sectional shape. 
     A MOS transistor TR may be formed at an intersections between the fin-type active region FA and the gate structure  420 . The MOS transistor TR may include a three-dimensional (3D) MOS transistor having channels formed on a top surface and two side surfaces of the fin-type active region FA. The MOS transistor TR may constitute an NMOS transistor or a PMOS transistor. 
     As shown in  FIG. 11C , the gate structure  420  may include an interface layer  412 , a high-k dielectric layer  414 , a first metal-containing layer  426 A, a second metal-containing layer  426 B, and a gap-fill metal layer  428 , which may be sequentially formed on the surface of the fin-type active region FA. Among the gate structure  420 , the first metal-containing layer  426 A, the second metal-containing layer  426 B, and the gap-fill metal layer  428  may constitute a gate electrode  420 G. 
     Insulating spacers  442  may be formed on both side surfaces of the gate structure  420 . An interlayer insulating layer  444  may be formed opposite to the gate structure  420  across the insulating spacers  442  to cover the insulating spacers  442 . 
     The interface layer  412  may be formed on the surface of the fin-type active region FA. The interface layer  412  may include an insulating material, such as an oxide layer, a nitride layer, or an oxynitride layer. The interface layer  412  may constitute a gate insulating layer along with the high-k dielectric layer  414 . 
     The high-k dielectric layer  414  may include a material having a higher dielectric constant than a silicon oxide layer. For example, the high-k dielectric layer  414  may have a dielectric constant of about 10 to about 25. The high-k dielectric layer  414  may include a material selected from the group consisting of zirconium oxide, zirconium silicon oxide, hafnium oxide, hafnium oxynitride, hafnium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and a combination thereof, but a material forming the high-k dielectric layer  414  is not limited thereto. 
     The high-k dielectric layer  414  may be formed by using an ALD process. The high-k dielectric layer  414  may be formed by the method of forming the material layer as described with reference to  FIGS. 1 and 2 or 6 . 
     In some example embodiments, the first metal-containing layer  426 A may include titanium nitride, tantalum nitride, titanium oxynitride, or tantalum oxynitride. For example, the first metal-containing layer  426 A may include TiN, TaN, TiAlN, TaAlN, TiSiN, or a combination thereof. The first metal-containing layer  426 A may be formed by using various deposition methods, such as an ALD process, a CVD process, or a PVD process. 
     In some example embodiments, the second metal-containing layer  426 B may include an N-type metal-containing layer required for an NMOS transistor including an aluminum compound containing titanium or tantalum. For example, the second metal-containing layer  426 B may include TiAlC, TiAlN, TiAlCN, TiAl, TaAlC, TaAlN, TaAlCN, TaAl, or a combination thereof. 
     In some example embodiments, the second metal-containing layer  426 B may include a p-type metal-containing layer required for a PMOS transistor. For example, the second metal-containing layer  426 B may include at least one of Mo, Pd, Ru, Pt, TiN, WN, TaN, Ir, TaC, RuN, and MoN. 
     The second metal-containing layer  426 B may include a single layer or a multilayered structure. 
     The second metal-containing layer  426 B may serve to control a work function of a gate structure  120  along with the first metal-containing layer  426 A. A threshold voltage of the gate structure  120  may be controlled by adjusting work functions of the first metal-containing layer  426 A and the second metal-containing layer  426 B. In some example embodiments, any one of the first metal-containing layer  426 A and the second metal-containing layer  426 B may be omitted. 
     When the gate structure  420  is formed by a replacement metal gate (RMG) process, the gap-fill metal layer  428  may be formed to fill the remaining gate space on the second metal-containing layer  426 B. After the second metal-containing layer  426 B is formed, when there is no remaining gate space on the second metal-containing layer  426 B, the gap-fill metal layer  428  may not be formed on the second metal-containing layer  426 B but omitted. 
     The gap-fill metal layer  428  may include a material selected from the group consisting of tungsten (W), a metal nitride (e.g., TiN and TaN), aluminum (Al), a metal carbide, a metal silicide, a metal aluminum carbide, a metal aluminum nitride, and a metal silicon nitride. 
     In the method of manufacturing the IC device  400  as described with reference to  FIGS. 1A to 11C , the high-k dielectric layer  414  may be formed by using a method of forming a material layer according to example embodiments. That is, the formation of the high-k dielectric layer  414  may include forming an adsorption layer of an ether-based modifier and an adsorption layer of a source material on the fin-type active region FA in which the interface layer  412  is formed, and supplying a reaction material, such as an oxidizer or a reducer, to form a material containing central atoms. 
     The method of manufacturing the IC device including the FinFET including the 3D channel has been described with reference to  FIGS. 11A to 11C , but example embodiments of the inventive concepts are not limited thereto. For example, it will be clearly understood by one of ordinary skill in the art that methods of manufacturing IC devices including planar MOSFETs having characteristics according to example embodiments may be provided by making various changes in form and details to the above-described example embodiments within the spirit and scope of the inventive concepts. 
       FIG. 12  is a cross-sectional view of another example of a semiconductor device formed by a method of manufacturing a semiconductor device according to some example embodiments. 
     Referring to  FIG. 12 , interlayer insulating layers  510  may be vertically stacked on a semiconductor substrate  501 . Conductive patterns  570  may be interposed between the interlayer insulating layers  510 . 
     Vertical structures  540  may penetrate the conductive patterns  570  and the interlayer insulating layers  510 . Each of the vertical structures  540  may include a core pattern  525 , a pad pattern  530 , and an outer pattern  520  that surrounds a side surface of the core pattern  525  and extends on a side surface of the pad pattern  530 . 
     The core pattern  525  may include an insulating material, such as silicon oxide. When the core pattern  525  include a dielectric material formed by using an ALD process, the core pattern  525  may be formed by a method of forming a material layer according to example embodiments. 
     The pad pattern  530  may be located on the core pattern  525  at a higher level than an uppermost conductive pattern of the conductive patterns  570 . The pad pattern  530  may include a conductive material, such as doped poly-Si. 
     The outer pattern  520  may include a semiconductor pattern that may serve as a channel of a transistor. For example, the outer pattern  520  may include a semiconductor material, such as silicon. A portion of the outer pattern  520 , which is near to the conductive patterns  570 , may include a dielectric material. The dielectric material may include a material (e.g., silicon oxide) that may serve as a tunnel oxide layer of a transistor. The dielectric material may include a material (e.g., silicon nitride or a high-k dielectric material) capable of storing information of a flash memory device. The dielectric material may be formed by a method of forming a material layer according to example embodiments. 
     Meanwhile, the conductive patterns  570  may include a metal nitride layer and/or a metal layer. For example, each of the conductive patterns  570  may include a metal layer and a metal nitride layer interposed between the metal layer and the interlayer insulating layers  510 . Also, the metal nitride layer may extend between the metal layer and the vertical structure  540 . The conductive patterns  570  may be formed by a method of forming a material layer according to example embodiments. 
     A capping insulating layer  550  may be provided to cover the interlayer insulating layer  510  and the vertical structure  540 . 
       FIG. 13  is a schematic block diagram of a display device including a display driver integrated circuit (DDI) according to some example embodiments. 
     Referring to  FIG. 13 , a DDI  1500  may include a controller  1502 , a power supply circuit  1504 , a driver block  1506 , and a memory block  1508 . The controller  1502  may receive a command applied from a main processing unit (MPU)  1522 , decode the command, and control respective blocks of the DDI  1500  to perform an operation in response to the command. The power supply circuit  1504  may generate a driving voltage in response to the control of the controller  1502 . The driver block  1506  may drive the display panel  1524  by using the driving voltage generated by the power supply circuit  1504  in response to the control of the controller  1502 . The display panel  1524  may be a liquid crystal display (LCD) panel, a plasma display panel (PDP), or an organic light emitting diode (OLED) display panel. The memory block  1508  may temporarily store the command input to the controller  1502  or control signals output by the controller  1502  or store required data. The memory block  1508  may include a memory, such as RAM or ROM. At least one of the power supply circuit  1504  and the driver block  1506  may include a thin layer formed by the method of forming the material layer as described with reference to  FIGS. 10A to 12 . 
       FIG. 14  is a block diagram of an electronic system according to some example embodiments. 
     Referring to  FIG. 14 , an electronic system  1900  may include a memory  1910  and a memory controller  1920 . The memory controller  1920  may control the memory  1910  to read data from the memory  1910  and/or write data to the memory  1910  in response to a request of a host  1930 . At least one of the memory  1910  and the memory controller  1920  may include a thin layer formed by the method of forming the material layer as described with reference to  FIGS. 1 and 2 or 6  or the IC devices  300 ,  400 , and  500  manufactured by the methods described with reference to  FIGS. 10A to 12 . 
       FIG. 15  is a block diagram of an electronic system according to some example embodiments. 
     Referring to  FIG. 15 , an electronic system  2000  may include a controller  2010 , and input/output (I/O)  2020 , a memory  2030 , and an interface  2040 , which may be connected to one another via a bus  2050 . 
     The controller  2010  may include at least one of a microprocessor (MP), a digital signal processor (DSP), or a processing device similar thereto. The I/O device  2020  may include at least one of a keypad, a keyboard, or a display device. The memory  2030  may be used to store commands executed by the controller  2010 . For example, the memory  2030  may be used to store user data. 
     The electronic system  2000  may constitute a wireless communication device or a device capable of transmitting and/or receiving information in a wireless environment. In the electronic system  2000 , the interface  2040  may include a wireless interface to transmit/receive data via a wireless communication network. The interface  2040  may include an antenna and/or a wireless transceiver. In some embodiments, the electronic system  2000  may be used for a communication interface protocol of a third-generation communication system, for example, code division multiple access (CDMA), global system for mobile communications (GSM), north American digital cellular (NADC), extended-time division multiple access (E-TDMA), and/or wide band code division multiple access (WCDMA). The electronic system  2000  may include a thin layer formed by the method of forming the material layer as described with reference to  FIGS. 1 and 2 or 6  or the IC devices  300 ,  400 , and  500  manufactured by the methods described with reference to  FIGS. 10A to 12 . 
     While the inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.