Patent Publication Number: US-7907450-B2

Title: Methods and apparatus for implementing bit-by-bit erase of a flash memory device

Description:
RELATED APPLICATIONS INFORMATION 
     This application claims priority under 35 U.S.C. 119(e) to U.S. Provisional Application Ser. No. 60/746,722, entitled “A Bit-by-Bit Program/Erase Method for NAND Flash Memory Device Using SOI or TFT Technology,” filed May 8, 2006, and which is incorporated herein by reference as if set forth in full. 
    
    
     BACKGROUND 
     1. Field 
     The embodiments described herein relate generally to Flash memory devices, and more particularly to methods for operating a Flash memory device that allow the device to be programmed and erased on a bit-by-bit basis and that allow for tight control of the programmed threshold voltage enabling multi-level cell applications. 
     2. Background 
     Conventional Flash memory devices are either NOR or NAND-type devices. In a conventional NOR device, each cell comprises a well known single transistor architecture. The single transistor comprising each cell is similar to a standard MOSFET, except that it comprises a two-gate structure. One gate is referred to as the control gate, which operates similar to the gate in a conventional MOSFET transistor. The second gate is referred to as the floating gate, which is separated from the control gate by an insulating layer. The gate structure is fabricated on top of a silicon substrate. The floating gate is also separated from this substrate by an insulating layer. Any electrons placed on the floating gate are trapped there due to the surrounding insulating layers. Thus, these electrons can be used to store information. When electrons are placed on the floating gate, the electrons modify, e.g., partially cancel out, the electric field being generated by a voltage supplied to the control gate, thereby modifying the threshold voltage (V t ) of the cell. When the cell is read by placing a specific voltage on the control gate, electrical current will either flow or not flow, depending on the threshold voltage (V t ) of the cell. The presence or absence of current can then be sensed and translated into a data “1” or data “0.” Accordingly, a cell can be programmed by storing electrons on the floating gate and thereby changing the threshold voltage (V t ) of the cell. 
     A NOR Flash cell is programmed via a process known as Channel Hot Electron (CHE) injection. During a CHE programming operation, the appropriate voltages are applied to the source, drain, and gate of the cell to produce a current flowing from the source to the drain in the channel under the gate structure. A large voltage placed on the control gate provides a strong enough electric field to cause some of the electrons to tunnel through the lower insulating layer onto the floating gate. A NOR Flash cell is then erased by applying a large voltage differential between the control gate and the source, which causes the electrons to tunnel through the lower insulating layer. 
     NAND devices use tunnel injection for programming and tunnel release for erasing. The tunneling mechanism is referred to as Fowler-Nordheim tunneling, which is well-known in the art. 
     Both NOR and NAND-type Flash memory devices can be programmed on a bit-by-bit basis. In other words, programming methods exist that allow a single bit to be programmed, while prohibiting program disturb of surrounding cells; however, both NOR and NAND-type devices must be erased by blocks. In other words, the cells are grouped into sectors, or blocks and all of the cells in a particular sector or block are erased at the same time. 
     More recently, multi-level cell (MLC) approaches have been used to store multiple bits per cell in both NOR and NAND type devices. MLC techniques allow for increased density in a smaller area and are therefore beneficial as it increases the amount of data being stored in Flash applications. In an MLC cell, the threshold is varied between multiple discreet levels by storing varying amounts of charge on the floating gate. The amount of current flowing when a voltage is applied to the control gate can then be sensed to determine how much charge is stored on the floating gate. In other devices, e.g., a nitride read only memory device, multiple bits can be stored in each cell by storing charge in different areas of the charged trapping structure. Accordingly, charge can be stored near the source on one side of the gate structure, and charge can be stored near the drain on the other side of the gate structure. These charges can then be independently sensed in order to determine the programming status of each bit. 
     MLC devices require a very tight threshold voltage (V t ) distribution control. Unfortunately, conventional Flash memory techniques do not always allow this type of distribution control. 
     Conventionally, NOR-type devices have been more reliable than their NAND counterparts, and therefore are used for data critical application such as for storing executable software code. NAND-type devices, on the other hand, have higher densities and are therefore more attractive when the application requires the storage of large amounts of data. More recently, the reliability of NAND-type devices has improved such that it now rivals, or even surpasses that of NOR-type devices. Accordingly, NAND-type devices are becoming more popular because they provide the high storage capacity of conventional NAND devices with the reliability normally associated with NOR devices. 
     Even so, conventional NAND-type memory devices still suffer the drawback of being restricted to block erase operations, and the difficulty in controlling the threshold voltage (V t ) with sufficient precision to enable MLC operation. 
     SUMMARY 
     A NAND-type Flash memory device is capable of being programmed and erased on a bit-by-bit basis, which enables tight threshold voltage (V t ) distribution control. Accordingly, the NAND memory device can be configured for MLC operation. 
     In one aspect, a NAND memory device is constructed using Silicon On Insulator (SOI) techniques. In particular, Thin Film Transistor (TFT) techniques can be used to fabricate a NAND Flash memory device described herein. In both SOI and TFT structures, the body, or well, is isolated. This can be used to enable the bit-by-bit programming and erasing of individual cells and allows the tight control of the threshold voltage, which can enable MLC operation. 
     These and other features, aspects, and embodiments of the invention are described below in the section entitled “Detailed Description.” 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features, aspects, and embodiments of the inventions are described in conjunction with the attached drawings, in which: 
         FIG. 1  is a diagram illustrating an example NAND memory array in accordance with one embodiment; 
         FIG. 2  is a schematic diagram illustrating the schematic equivalent of the array of  FIG. 1 ; 
         FIG. 3  is a diagram illustrating a cross sectional view of the array of  FIG. 1 ; 
         FIG. 4  is a diagram illustrating another cross sectional view of the array of  FIG. 1 ; 
         FIG. 5A  is a diagram illustrating an example programming operation for the array of  FIG. 1 ; 
         FIG. 5B  is a graph illustrating example programming characteristics for the array of  FIG. 1  for varying programming voltages; 
         FIG. 5C  is a graph illustrating example program prohibit effects for the array of  FIG. 1  for varying programming voltages; 
         FIG. 6A  is a diagram illustrating an example bit-by-bit erase operation for the array of  FIG. 1  in accordance with one embodiment; 
         FIG. 6B  is a diagram illustrating the timing and results for the operation illustrated in  FIG. 6A ; 
         FIG. 7  is a diagram illustrating a cross sectional view of a 3-dimensional NAND memory array in accordance with one embodiment; 
         FIG. 8  is a diagram illustrating a top view of the array of  FIG. 7 ; 
         FIGS. 9A-9G  are diagrams illustrating a cross sectional view of a plurality of example gate structures that can be used in the arrays of  FIGS. 1 and 7 ; 
         FIGS. 10A-10   b  are band diagrams for the gate structure of  FIG. 9B  under low and high electric fields respectively; and 
         FIG. 11  is a diagram illustrating a cross sectional view of still another example gate structure that can be used in the arrays of  FIGS. 1 and 7 . 
     
    
    
     DETAILED DESCRIPTION 
     It will be understood that any dimensions, measurements, ranges, test results, numerical data, etc., presented below are approximate in nature and unless otherwise stated not intended as precise data. The nature of the approximation involved will depend on the nature of the data, the context, and the specific embodiments or implementations being discussed. 
     The embodiments described below are directed to methods for operating a NAND flash memory device in a manner that allows for both program-to-high and program-to-low operation. This allows the device to be both programmed and erased on a bit-by-bit basis. The device can also be configured to program and erase simultaneously. Further, since each cell in the device can be bit-by-bit corrected, a tight threshold voltage (V 1 ) distribution control required for MLC operation can be achieved. 
       FIG. 1  is a diagram illustrating a top view of the various layers comprising a NAND flash memory array  100  configured in accordance with the embodiments described herein. As will be explained in more detail below, the layers illustrated in  FIG. 1  are formed over an insulating material using Silicon-on-Insulator (SOI) techniques. More particularly, in certain embodiments, Thin-Film-Transistor (TFT) fabrication technique can be used to form memory array  100 . The SOI and TFT structures share the similar feature that the body, or well, for each cell  110  is isolated from the body, or well of other cells in the device. This isolation is illustrated in  FIGS. 3 and 4 . 
     As can be seen in  FIG. 1 , word lines  102  are formed over bit lines  104 . Bit lines  104  are separated by Shallow Trench Isolation (STI) structures  108 . STI structures are well-known and will not be described in detail here; however, it will be clear that STI structures  108  provide isolation between adjacent bit lines  104 . Source/drain regions  106  can then be implanted into bit lines  104  in the areas not covered by word lines  102 . The areas under word lines  102  can then act as the channel regions for a particular cell, such as cell  110  illustrated in the middle of array  100 . 
     With reference to cell  110 , the source/drain regions  106  on either side of word line  102  act as the source/drain regions for cell  110  and the region of bit line  104  under word line  102  acts as the channel region for cell  110 . As explained in more detail below, by applying the appropriate voltages to source/drain regions  106  and word lines  102 , cell  110  can be programmed and erased on a bit-by-bit basis relative to the other cells within array  100 . It should be noted that cell  110  can be an N-channel or P-channel cell depending on the embodiment. But regardless of whether cell  110  is an N-channel or P-channel cell, cell  110  can be programmed and erased on a bit-by-bit basis relative to the other cells in array  100  using the methods described herein. 
     Unlike conventional EEPROM which typically also allow bit-by-bit program and erase operations, cells of array  100  can be made very small. For example, an EEPROM often requires two transistors, and the cell size is often relatively large, e.g., greater than 20 F 2 . In contrast, a cell such as cell  110  in array  100  can use the single transistor NAND architecture and thus the cell size can be minimal, e.g. approximately 4 F 2 . Moreover, as explained in more detail below, using a TFT NAND architecture can also facilitate the use of a three-dimensional, stacked architecture, which can significantly increase density. 
       FIG. 2  is a schematic diagram of array  100 . As can be seen, word lines  102  are attached to the gates of cell transistors  110 . The bit lines  104  are then attached to source/drain regions  106  via bit line transistors  114 . The gates of bit line transistors  114  are controlled via bit line transistor control line  116 . The other side of cell transistors  110  is controlled via source line  126  which is interfaced with cell transistors  110  via source line transistors  112 . The gates of source line transistors  112  are controlled via source line transistor control line  122 . 
       FIGS. 3 and 4  are diagrams illustrating cross-sectional views of the layers illustrated in  FIG. 1  along the lines AA′ and BB′ respectively. As can be seen in  FIG. 3 , array  100  is formed on an insulating layer  144 . For example, insulating layer  144  can be sapphire or a silicon dioxide (SiO 2 ) layer. Bit lines  104  can then be formed over insulating layer  144  by depositing a semiconductor material  142  over layer  144 , the semiconductor material  142  can then be patterned and etched using conventional photolithography techniques in order to produce bit lines  104 . Word lines  102  can then be formed over bit lines  104  by sequentially forming layers of the appropriate material over bit lines  104  and patterning and etching the layers to produce word lines  102 . Once word lines  102  are formed, source/drain regions  106  can then be implanted into bit lines  104 , e.g., using a self-aligned process. This will leave channel regions  142  under word lines  102  and between source and drain regions  106 . 
     As illustrated in  FIG. 1 , STI structures  108  can be formed between bit lines  104 . This is also illustrated in  FIG. 4  which is a cross-sectional view along the line BB′ from  FIG. 1 . Thus, channel regions  142  under word lines  102  are separated from each other by STI structures  108 . 
     Referring to  FIG. 3 , word lines  102  form the gate structures for each cell  110  in array  100 . As explained in more detail below, a variety of gate structures can be used in accordance with the embodiments described herein. In the example of  FIG. 3 , a Bandgap Engineered-Silicon-Oxide-Nitride-Oxide-Silicon (BE-SONOS) gate structure is used for cells  110 . Accordingly, each gate structure comprises an ONO structure  134 , nitride layer  133 , oxide layer  132 , and a polysilicon layer  130  sequentially formed over bit lines  104 . As will be understood, ONO layer  134  can comprise an oxide layer  140 , nitride layer  138 , and oxide layer  136  sequentially formed over bit line  104 . 
     A BE-SONOS gate structure is described in more detail below, as are other possible gate structures that can be used in accordance with the embodiments described herein. 
       FIG. 5A  is a diagram illustrating voltages that can be applied to array  100  during a programming operation in accordance with one embodiment. In the example of  FIG. 5A , cell  504  is the target cell. Further, in the example of  FIG. 5A , array  100  comprises N-channel cells  110 , although as explained above, the embodiments described herein can also be used for P-channel cells. 
     Referring to  FIG. 5A , programming of cell  504  can be achieved by applying a high voltage (e.g., 17 V) to word line  118  associated with cell  504  (WL N-1 ) and a medium voltage (e.g., 9 V) to the unselected word lines  102 . For example, in certain embodiments a voltage in the range of approximately 14 V to 20 V can be applied to word line  118  associated with cell  504 , while a medium voltage in the range of 6 to 12 V is applied to the other word line  102 . In one specific example, a high voltage of approximately 17 V can be applied to word line  118  associated with cell  504 , while voltage of approximately 9 V is applied to word lines  118  associated with the unselected cell  502 . 
     The selected bit line  122 , in this case BL 1 , is tied to a low voltage, or grounded so as to create a sufficient voltage drop across selected cell  504 . For example, if a high voltage of 17 V is applied to the associated word line  118 , then the voltage drop across cell  504  will be approximately 17 V.  FIG. 5B  is a diagram illustrating example programming characteristics for cell  504  for varying word line voltages. As can be seen, by applying a word line voltage of between 16 V and 19 V, while grounding the associated bit line  122 , the threshold of cell  504  can be raised to a high threshold voltage of between approximately 2 V and 3.5 V. In the example of  FIG. 5B , the programming voltages were applied for a duration of approximately 50 μsec. 
     During the programming operation, a high bit-line voltage (e.g., 8 V) is applied to the unselected bit line  104 , in this case BL 2 , such that the voltage drop across adjacent, unselected cell  506  is relatively small. For example, a voltage in the range from approximately 5 V to 11 V can be applied to the unselected bit line  104 . In one specific implementation, a voltage of approximately 8 V is applied to the unselected bit line  104 . 
     Applying the high bit-line voltage to the unselected bit line, and thereby creating a relatively small drop across adjacent cell  506 , inhibits program disturb of adjacent cell  506 .  FIG. 5C  is a diagram illustrating the program inhibit effects for various voltages applied to word lines  102  and bit lines  104  and  122 . In the example of  FIG. 5C , a high word-line voltage of 17V is applied to word line  118  associated with cell  504 , while medium word-line voltages of approximately 9V are applied to the unselected word lines  102 . A low bit-line voltage of approximately 0V is applied to selected bit line  122  associated with cell  504 , while a high bit-line voltage of approximately 8V is applied to the unselected bit line  104 . As can be seen, the threshold voltage for unselected cells  502  and  506  remains low at around −1 volts, and change by less than 0.5 Volts. 
     Accordingly, cells  110  of array  100  can be programmed on a bit-by-bit basis, i.e., using the methods described above. Array  100  can also be erased in either a block or sector erase operation or, as explained below, on a cell-by-cell basis. With reference to  FIG. 2 , a sector erase can be implemented by applying a low voltage (e.g., −18 V) to all of the word lines  102  while applying a grounding voltage (e.g., 0 V) to all of the bit lines  104 . This allows the threshold voltage for each cell  110  to be lowered. 
     Additionally, however, cells  110  can be erased on a cell-by-cell basis.  FIG. 6A  illustrates an example embodiment for a cell-by-cell erase operation. In the example of  FIG. 6A , cell  604  is the target cell being erased. In order to erase target cell  604  without affecting, e.g., adjacent cells  602  and  606 , a medium low word-line voltage (e.g., −10 V) is applied to word line  118  associated with cell  604  (WL N-1 ), while a medium high word-line voltage (e.g., 10 V) is applied to the unselected word lines  102 . For example, in one embodiment, a low word-line voltage in the range of approximately −7 V to −13 V can be applied to word line  118  associated with cell  604 , while a medium word-line voltage in the range of approximately 7 V to 13 V can be applied to the unselected word lines  102 . In one specific example, a low word-line voltage of approximately −10 V is applied to the selected word line  118 , while a medium word-line voltage of approximately 10 V is applied to the unselected word lines  102 . 
     A high bit-line voltage (e.g., 8 V) can then be applied to the selected bit line  122  (BL 1 ), while the unselected bit lines  104  are tied to approximately 0 volts. A high bit-line voltage should be applied to bit line transistor control line  116  in order to turn on pass transistors  114  and allow the voltage applied to the selected bit lines  104  and  122  to pass through to cells  110 . Pass transistors  112 , on the other hand, can be turned off by tying source line transistor control line  120  to approximately 0 volts. Source line  126  can be allowed to float through the operation. 
     The total gate voltage applied to cell  604  will be equal to the voltage applied to word line  118  minus the voltage applied to the selected bit line  122 . Accordingly, if −10 V is applied to the selected word line  118  and 8 V is applied to the selected bit line  122 , then the total gate voltage will be −18 V, which should be sufficient to erase cell  604 . At the same time, the total gate voltage applied to the unselected cells, e.g., cells  602  and  606  will only be −10 V, which provides a very good erase disturb margin. 
       FIG. 6B  is a diagram illustrating the timing and results for the operation illustrated in  FIG. 6A . Curves  608  illustrate that a cell can be effectively erased by either applying a large negative word-line voltage, e.g., −18V, to the selected word line, while tying the selected bit line to approximately 0 volts, or by applying a medium negative word-line voltage, e.g., −10V, to the selected word line  118 , and a high bit-line voltage, e.g., +8V to the selected bit line  122 . In other words, whether erasing an entire sector, or an individual cell, the erase operation can be performed with approximately the same efficiency and results. As can be seen in curve  608  of  FIG. 6B , the threshold voltage of the selected cell decreases by at least 1 Volt. 
     Curve  606  illustrates that the erase disturb effects for unselected cells, e.g., cells  602  and  606 , can be kept to a minimum using the operation described in  FIG. 6A . As can be seen in curve  606  of  FIG. 6B , the threshold voltage of unselected cell  606  changes by less than 0.5 Volts. As described, a negative voltage is applied to the gates so as to prevent the formation of an inversion channel in each cell. As a result, a positive voltage applied to a selected bit line cannot raise the well as needed to achieve erase of an individual unselected cell. 
     When using an SOI or TFT architecture, the body of each cell is effectively floating relative to each bit line. This is because the STI structures isolate the body for each cell. Under such conditions, the body potential for an individual cell can be controlled using a bit line voltage as described in relation to  FIG. 6A . The bit line voltage will raise the body potential to a voltage very close to that applied to the bit line. This produces the net gate voltage needed to erase a particular cell. Again, as described in relation to  FIG. 6B , the erase result can be similar, or even the same as that achieved for a sector erase. 
     It should be noted that the operations described above can also be implemented for a P-channel NAND structure by creating inverse programming and erase voltage conditions. 
     The ability to program and erase on an individual cell basis allows for a very tight threshold voltage (V t ) distribution. The threshold voltage (V t ) distribution can enable MLC applications. This can be achieved by adjusting the amount of charge stored in an individual cell  1110 . 
     Further, a review of the voltages applied in  FIGS. 5A and 6A  make clear that a certain cell can be programmed, while another cell is being erased. For example, a cell in the same row as cell  506  can be being erased, while cell  504  is being programmed. 
     Further, as noted above, the density of a device configured to implement the operations described herein can be increased by using a 3-dimensional, stacked architecture.  FIG. 7  is a diagram illustrating an exemplary TFT, stacked NAND memory  700  in accordance with one embodiment. In the example of  FIG. 7 , NAND memory  700  is fabricated on top of an insulating layer  702 . Accordingly, device  700  is fabricated using SOI processing techniques. For example, device  700  can be fabricated using TFT processing techniques. A TFT is a special kind of field effect transistor made by depositing thin films for the metallic contacts, semiconductor active layer, and dielectric layer on an insulating layer. The channel region of a TFT is a thin film that is deposited onto a substrate that is often glass. 
     Successive bitline layers and wordline layers can then be fabricated on insulating layer  702 . For example, in  FIG. 7  a first bitline layer  710  is fabricated on insulating layer  702 . A first wordline layer  720  is then fabricated on top of first bit line layer  710 . A second bitline layer  730  is then fabricated on top of first wordline layer  720 . Finally, a second wordline layer  740  is fabricated on top of second bitline layer  730 . 
     Further bitline and wordline layers can be successively fabricated on top of the layers illustrated in  FIG. 7 . Thus, two bitline layers and two wordline layers are shown for convenience only and the methods described herein should not be seen as limited to a certain number of bitline layers and/or wordline layers. Each bitline layer  710  and  730  comprises a plurality of bitlines  704  separated by insulating regions  706 . Each wordline layer  720  and  740  comprises a wordline conductor  705  sandwiched between trapping layers  703  and  707 . 
     By using the stacked configuration illustrated in  FIG. 7 , greater memory densities can be achieved. The density can be increased even further through MLC operation made possible by the operation methods described above. 
     An example process for fabricating device  700  is described in detail in Co-pending U.S. patent application Ser. No. 11/425,959 entitled “A Stacked Non-Volatile Memory Device and Methods for Fabricating the Same,” filed Jun. 22, 2006, which is incorporated herein by reference in the entirety as if set forth in full. 
       FIG. 8  is a top view of device  700 .  FIG. 7  is a cross sectional view of the layer illustrated in  FIG. 8  along the line AA″. As can be seen, the top layer of device  700  can comprise a plurality of word lines  740  formed over a plurality of bit lines  704 . Bit lines  704  can be separated by insulating structures  706 . Source/Drain regions  820  can be implanted in bit lines  704  in the areas not covered by word lines  740 . The areas of bit lines  704  under word lines  740  can then act as the channel regions for the associated cells. 
     Referring to  FIG. 7 , a plurality of vertically stacked memory cells  710 - 726  can then be formed within device  700 . The trapping structures  703  above or below the channel regions in bit lines  704  along with the associated gate conductor  705  form the gate structures for each cell. Cells  722 - 724  are illustrated in  FIG. 8  as are additional cells  846 - 856 . It will be understood therefore that  FIG. 8  illustrates three rows of memory cells, where each row comprises three stacked layers of cells. It will also be understood, however, that the number of rows and layers of cells illustrated in  FIGS. 7 and 8  are by way of example only and that any number of rows and/or layers can be implemented depending on the requirements of a particular implementation. 
     As discussed above, a variety of gate structures can be used in accordance with the embodiments described herein. For example, in certain embodiments a simple floating gate structure can be used. In other embodiments, however, a more complex trapping structure can be used.  FIGS. 9A-9H  are diagrams illustrating example embodiments of various trapping structures that can be used, e.g., in device  700 . 
     The first exemplary embodiment illustrated in  FIG. 9A  comprises a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) structure. This structure comprises an oxide layer  908 , nitride layer  906 , and oxide layer  904  sequentially formed over polysilicon layer  704 . Oxide region  908  acts as a tunnel dielectric layer and nitride layer  906  acts as a trapping layer for trapping charge. When the SONOS structure of  FIG. 9A  is used, charge is stored in trapping structure  906  of a particular cell by injection of holes into trapping layer  906 . A cell can be erased through the direct tunneling of holes into trapping structure  906 , where they compensate for any electrons previously stored in trapping structure  906 . The tunneling of holes in the trapping structure  906  is achieved via Fowler-Nordheim tunneling. Oxide layer  908  can be a thin oxide layer, e.g., less than 3 nanometers thick. In the example of  FIG. 9A , a polysilicon word line conductor  705  is then formed over oxide layer  904 . As explained with respect to  FIG. 11 , certain embodiments can use a metal word line conductor. 
     NAND devices constructed using the SONOS trapping structure illustrated in  FIG. 9A  retain less charge due to leakage current that results from the direct tunneling of holes into trapping layer  906  during charge retention. 
       FIG. 9B  is a diagram illustrating a band-gap engineered (BE)-SONOS structure. The BE-SONOS structure of  FIG. 9B  is fabricated by sequentially forming an ONO structure  914  followed by a nitride layer  912 , and a dielectric layer  910  over polysilicon layer  704 . ONO structure  914  is thus formed by sequentially forming an oxide layer  920 , nitride layer  918 , and an oxide layer  916  over polysilicon layer  704 . As with the SONOS structure of  FIG. 9A , the BE-SONOS structure of  FIG. 9B  uses Fowler-Nordheim hole tunneling to erase the memory cells; however, the BE-SONOS structure of  FIG. 9B  does not exhibit the poor charge retention that results from direct tunneling leakage, or device degradation that results from hot hole erase damage. 
       FIGS. 10A and 10B  are band diagrams illustrating the energy bands for ONO structure  914 , of the BE-SONOS structure illustrated in  FIG. 9B .  FIG. 10A  is a band diagram during data retention, and  FIG. 10B  is a band diagram during erase. As can be seen in  FIG. 10A , during retention holes do not have sufficient energy to overcome the potential barriers of the layers comprising ONO structure  914 . Data retention occurs when a low electric field exists across trapping structure  914 . Because tunneling of holes is blocked by structure  914 , there is little tunneling leakage during application of a low field. As illustrated in  FIG. 10B , however, when a high field exists across trapping structure  914 , the bands shift allowing holes to tunnel across structure  914 . This is because the barriers presented by layers  916  and  918  are almost eliminated from the perspective of the holes, due to the band shift when a high field is present. 
     BE-SONOS structures are describe in more detail in the article by Hang-Ting Lue et al., entitled “BE-SONOS: A Bandgap Engineered SONOS With Excellent Performance and Reliability,” IEEE, 2005, which is incorporated herein by reference in its entirety as if set forth in full. 
       FIGS. 9C-9H  illustrate other exemplary structures that can be used for the trapping layers included in device  700 . For example,  FIG. 9C  is a diagram illustrating a SONS structure that can be used for the trapping layers included in device  700 . The structure illustrated in  FIG. 9C  comprises a thin oxide layer  924  formed over polysilicon layer  704 . A nitride layer  922  is then formed over the thin oxide layer  924 . Gate conducting layer  705  can then be formed over nitride layer  922 . Thin oxide layer  924  acts as the tunnel dielectric and charge can be stored in nitride layer  922 . 
       FIG. 9D  is an example of a top BE-SONOS structure that can be used for trapping layers included in device  700 . Accordingly, the structure illustrated in  FIG. 9D  comprises an oxide layer  936  formed over polysilicon layer  704 . A nitride layer  934  is then formed over oxide layer  936 , and ONO structure  926 , comprising an oxide layer  932 , nitride layer  930  and oxide layer  928 , is then formed over nitride layer  934 . In the example of  FIG. 9D , ONO layer  926  acts as the tunnel dielectric layer and charge can be trapped in nitride layer  930 . 
       FIG. 9E  is a diagram illustrating a bottom SONOSOS structure that can be used for the trapping layers included in device  700 . The structure illustrated in  FIG. 9E  comprises an oxide layer  948  formed over polysilicon layer  704 , and a nitride layer  946  formed over oxide layer  948 . A thin oxide layer  944  is then formed over nitride layer  946  followed by a thin polysilicon layer  942 . Another thin oxide layer  940  is then formed then over polysilicon layer  942 . Accordingly, layers  940 ,  942 , and  944  form an OSO structure  938  near gate conductor  705 . In the example of  FIG. 9E , oxide layer  948  can act as the tunnel dielectric and charge can be stored in nitride layer  946 . 
       FIG. 9F  is a diagram illustrating a bottom SOSONOS structure. Here, a thin OSO structure  954  is formed over polysilicon layer  704 . OSO structure  954  comprises thin oxide layer  960 , a thin polysilicon layer  958 , and a thin oxide layer  956 . A nitride layer  952  can then be formed over OSO structure  954 , and an oxide layer  950  can be formed over nitride layer  954 . In the example of  FIG. 9F , OSO structure  954  can act as the tunnel dielectric and charge can be stored in nitride layer  952 . 
       FIG. 9G  is a diagram illustrating an exemplary SONONS structure that can be used for the trapping structures included in device  700 . Here, an oxide layer  970  is formed over polysilicon layer  704  and a nitride layer  968  is formed over oxide layer  970 . An ON structure  962  is then formed over nitride layer  968 . ON structure  962  comprises a thin oxide layer  966  formed over nitride layer  968 , and a thin nitride layer  964  formed over thin oxide layer  966 . In the example of  FIG. 9G , oxide layer  970  can act as the tunnel dielectric and charge can be trapped in nitride layer  968 . 
     In other embodiments, the trapping structure can comprise a SiN or a SiON, or a Hi-K material such as HfO 2 , Al 2 O 3 , AIN, etc. In general, any trapping structure or material can be used as long as it meets the requirements of a particular implementation. 
     In certain embodiments, a metal word line conductor  705  can be used in conjunction with a MONOS trapping structure. An example MONOS trapping structure that can be used in accordance with the embodiments described herein is illustrated in  FIG. 11 . Here, a dielectric layer, such as an oxide layer  1102  is formed over polysilicon region  704  and acts as the tunnel dielectric. A Nitride layer  1104  is then formed over layer  1102  and is configured to trap charge. Another dielectric layer  1106  is then formed over nitride layer  1104 . Metal word line conductor  705  is then formed over dielectric  1106 . 
     For example, as explained in the article by Yoocheol Shin et al. entitled, “A Novel-type MONOS Memory Suing 63 nm Process Technology For Multi-Gigabit Flash EEPROMS,” IEEE, 2005, which is incorporated herein by reference as if set forth in full, metal conductor  705  can comprise TaN. Further, dielectric layer  1106  can comprise Al 2 O 3 . 
     While certain embodiments of the inventions have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the inventions should not be limited based on the described embodiments. Rather, the scope of the inventions described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.