Patent Publication Number: US-11043274-B2

Title: Nonvolatile memory device, storage device, and operating method of nonvolatile memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0104615 filed on Aug. 26, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein. 
     BACKGROUND 
     1. Technical Field 
     Embodiments of the inventive concept described herein relate to a semiconductor circuit, and more particularly, relate to a nonvolatile semiconductor memory, a storage device, and an operating method of the nonvolatile memory device. 
     2. Discussion of Related Art 
     A nonvolatile memory device is a type of memory capable of retaining stored data even when power is turned off. Examples of nonvolatile memory devices include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, a phase-change memory (PRAM), a magnetic memory (MRAM), a resistive memory (RRAM), and a ferroelectric RAM (FRAM). 
     A capacity of the nonvolatile memory device may be increased by arranging memory cells of the device into three-dimensional stacks. However, the reliability of some memory cells in the three-dimensional stacks have a lower reliability than other memory cells in the three-dimensional stacks. 
     When data is not written in the memory cells of the low reliability, the capacity of the nonvolatile memory device decreases. When data is written in the memory cells of the low reliability, the probability of a data loss increases. 
     SUMMARY 
     At least one exemplary embodiment of the inventive concept provides a nonvolatile memory device, a storage device, and an operating method of the nonvolatile memory device, which are capable of performing program operations increasing the reliability of data written in memory cells of low reliability. 
     According to an exemplary embodiment of the inventive concept, a nonvolatile memory device includes a memory cell array, a row decoder, and a pager buffer. The memory cell array is disposed on a substrate. The memory cell array includes memory blocks. The row decoder is connected to the memory cell array through word lines, and the page buffer block is connected to the memory cell array through bit lines. Each of the memory blocks includes a pillar having a first portion disposed on the substrate and a second portion stacked on the first portion. A width of the first portion increases as a distance from the substrate increases, and first conductive materials and first insulating layers surround the first portion and are stacked in turn on the substrate. A width of the second portion increases as a distance from the substrate increases, and second conductive materials and second insulating layers surround the second portion and are stacked in turn on the substrate. A first boundary is located between the first portion and the second portion. The first conductive materials form first memory cells together with the first portion and the second conductive materials form second memory cells together with the second portion. When performing program operations based on consecutive addresses in a selected memory block of the memory blocks, the row decoder and the page buffer are configured to complete a second program operation of an adjacent memory cell adjacent to the first boundary after sequentially completing first program operations of non-adjacent memory cells not adjacent to the first boundary from among the first and second memory cells. 
     According to an exemplary embodiment of the inventive concept, a storage device includes a nonvolatile memory device including a plurality of memory blocks, and a controller that controls a write operation for a selected memory block of the memory blocks of the nonvolatile memory device. Each of the memory blocks includes first memory cells corresponding to a first portion of a pillar extending in a direction perpendicular to a substrate, and second memory cells corresponding to a second portion of the pillar extending in the direction perpendicular to the substrate and disposed on the first portion. The first memory cells and the second memory cells are classified into at least one first adjacent memory cell adjacent to a first boundary between the first portion and the second portion and first non-adjacent memory cells being remaining memory cells other than the at least one first adjacent memory cell. In the write operation of the selected memory block, the controller controls the nonvolatile memory device such that the number of bits to be written in the at least one first adjacent memory cell is smaller than the number of bits to be written in each of the first non-adjacent memory cells when program operations of the first memory cells and the second memory cells are completed. 
     According to an exemplary embodiment of the inventive concept, an operating method of a nonvolatile memory device which includes memory cells connected in series between a string selection transistor and a ground selection transistor includes completing first program operations of first memory cells of the memory cells, and completing a second program operation of at least one second memory cell located between the first memory cells, after completing the first program operations of the first memory cells. The memory cells are stacked in a direction perpendicular to a substrate, based on a first portion of a pillar extending in the direction perpendicular to the substrate and a second portion of the pillar extending in the direction perpendicular to the substrate and disposed on the first portion. The at least one second memory cell is adjacent to a boundary between the first portion and the second portion. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       The inventive concept will become apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings. 
         FIG. 1  is a block diagram illustrating a nonvolatile memory device according to an exemplary embodiment of the inventive concept. 
         FIG. 2  illustrates an example of one memory block according to an exemplary embodiment of the inventive concept. 
         FIG. 3  is a perspective cross-sectional view illustrating an example of cell strings corresponding to second and third bit lines of a memory block of  FIG. 2 . 
         FIG. 4  is a cross-sectional view schematically illustrating a memory block of  FIG. 3 . 
         FIG. 5  illustrates an operating method of a nonvolatile memory device according to an exemplary embodiment of the inventive concept. 
         FIG. 6  illustrates examples of schemes in which a nonvolatile memory device performs program operations. 
         FIG. 7  illustrates an example in which pillars of a memory block are composed of first to third portions. 
         FIG. 8  illustrates examples in which a nonvolatile memory device performs program operations in a memory block of  FIG. 7 . 
         FIG. 9  illustrates an operating method of a nonvolatile memory device according to an exemplary embodiment of the inventive concept. 
         FIG. 10  illustrates an example of a single step program operation. 
         FIG. 11  illustrates an example of a multi-step program operation. 
         FIGS. 12 and 13  illustrate examples in which a nonvolatile memory device performs program operations depending on an operating method of  FIG. 9 . 
         FIG. 14  illustrates a storage device including a nonvolatile memory device. 
         FIG. 15  illustrates an operating method of a storage device according to an exemplary embodiment of the inventive concept. 
         FIG. 16  illustrates a storage device according to an exemplary embodiment of the inventive concept. 
     
    
    
     DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS 
     Below, embodiments of the inventive concept are described in detail and clearly to such an extent that one of ordinary skill in the art can implement the inventive concept. 
       FIG. 1  is a block diagram illustrating a nonvolatile memory device  100  according to an embodiment of the inventive concept. Referring to  FIG. 1 , the nonvolatile memory device  100  includes a memory cell array  110 , a row decoder block  120  (e.g., a row decoding circuit), a page buffer block  130  (e.g., one or more page buffers), a data input and output block  140  (e.g., an input/output circuit), a buffer block  150  (e.g., one or more buffers), and a control logic block  160  (e.g., a control circuit). 
     The memory cell array  110  includes a plurality of memory blocks BLK 1  to BLKz. Each of the memory blocks BLK 1  to BLKz includes a plurality of memory cells. Each of the memory blocks BLK 1  to BLKz may be connected to the row decoder block  120  through at least one ground selection line GSL, word lines WL, and at least one string selection line SSL. Some of the word lines WL may be used as dummy word lines. Each memory block may be connected to the page buffer block  130  through a plurality of bit lines BL. The plurality of memory blocks BLK 1  to BLKz may be connected in common to the plurality of bit lines BL. 
     In an embodiment, each of the plurality of memory blocks BLK 1  to BLKz corresponds to a unit of an erase operation. The memory cells belonging to each memory block may be erased at the same time. In another example, each of the plurality of memory blocks BLK 1  to BLKz may be divided into a plurality of sub-blocks. Each of the plurality of sub-blocks may correspond to a unit of the erase operation. 
     The row decoder block  120  is connected to the memory cell array  110  through ground selection lines GSL, the word lines WL, and string selection lines SSL. The row decoder block  120  operates under control of the control logic block  160 . 
     The row decoder block  120  may decode a row address RA received from the buffer block  150  and may control voltages to be applied to the string selection lines SSL, the word lines WL, and the ground selection lines GSL based on the decoded row address. 
     The page buffer block  130  is connected to the memory cell array  110  through the plurality of bit lines BL. The page buffer block  130  is connected with the data input and output block  140  through a plurality of data lines DL. The page buffer block  130  operates under control of the control logic block  160 . 
     In a write operation, the page buffer block  130  may store data to be written in memory cells. The page buffer block  130  may apply voltages to the plurality of bit lines BL based on the stored data. In a read operation or in a verify read operation that is performed in the write operation or an erase operation, the page buffer block  130  may sense voltages of the bit lines BL to generate a sensing result and may store the sensing result. 
     The data input and output block  140  is connected with the page buffer block  130  through the plurality of data lines DL. The data input and output block  140  may receive a column address CA from the buffer block  150 . The data input and output block  140  may output data read by the page buffer block  130  to the buffer block  150  depending on the column address CA. The data input and output block  140  may provide data received from the buffer block  150  to the page buffer block  130 , based on the column address CA. 
     The buffer block  150  may receive a command CMD and an address ADDR from an external device through a first channel CH 1  and may exchange data “DATA” with the external device. The buffer block  150  may operate under control of the control logic block  160 . The buffer block  150  may transfer the command CMD to the control logic block  160 . The buffer block  150  may transfer the row address RA of the address ADDR to the row decoder block  120  and may transfer the column address CA of the address ADDR to the data input and output block  140 . The buffer block  150  may exchange the data “DATA” with the data input and output block  140 . 
     The control logic block  160  may exchange a control signal CTRL from the external device through a second channel CH 2 . The control logic block  160  may control the buffer block  150  to route the command CMD, the address ADDR, and the data “DATA”. 
     The control logic block  160  may decode the command CMD received from the buffer block  150  and may control the nonvolatile memory device  100  depending on the decoded command. In an exemplary embodiment of the inventive concept, the control logic block  160  specifies an order of program operations, in which the row decoder block  120  and the page buffer block  130  program memory cells, based on differences of structures and distinct characteristics of the memory cells. 
       FIG. 2  illustrates an example of one memory block BLK 1  according to an exemplary embodiment of the inventive concept. Referring to  FIG. 2 , a plurality of cell strings CS are arranged on a substrate SUB in a first direction, a second direction, and a third direction. The plurality of cell strings CS may be connected in common to a common source line CSL formed on (or in) the substrate SUB. In  FIG. 2 , a location of the substrate SUB is illustrated to aid in understanding a structure of the memory block BLK 1 . 
     Cell strings of the rows may be connected in common to the ground selection line GSL, and cell strings of each row may be connected to a corresponding one of first to fourth upper string selection lines SSLu 1  to SSLu 4  and a corresponding one of first to fourth lower string selection lines SSLl 1  to SSLl 4 . Cell strings of each column may be connected to a corresponding one of first to fourth bit lines BL 1  to BL 4 . For brief illustration, cell strings connected to the second and third string selection lines SSL 2   l , SSL 2   u , SSL 3   l , and SSL 3   u  are depicted to be blurred. 
     Each cell string may include at least one ground selection transistor GST connected to the ground selection line GSL, a first dummy memory cell DMC 1  connected to a first dummy word line DWL 1 , first to tenth memory cells MC 1  to MC 10  respectively connected to first to tenth word lines WL 1  to WL 10 , a second dummy memory cell DMC 2  connected to a second dummy word line DWL 2 , and lower and upper string selection transistors SSTl and SSTu respectively connected to the corresponding lower and upper string selection lines. 
     In each cell string, the ground selection transistor GST, the first dummy memory cell DMC 1 , the first to tenth memory cells MC 1  to MC 10 , the second dummy memory cell DMC 2 , and the lower and upper string selection transistors SSTl and SSTu may be serially connected along a third direction perpendicular to the substrate SUB and may be sequentially stacked along the third direction perpendicular to the substrate SUB. 
     The memory block BLK 1  may be provided as a 3D memory array. The 3D memory array is monolithically formed in one or more physical levels of arrays of memory cells MC having an active area disposed above the substrate SUB (e.g., silicon) and a circuit associated with the operation of those memory cells MC. The circuit associated with an operation of memory cells MC may be located above or within the substrate SUB. The term “monolithic” means that layers of each level of the array are directly deposited on the layers of each underlying level of the 3D memory array. 
     In an embodiment of the inventive concept, the 3D memory array includes vertical cell strings CS (or NAND strings) that are vertically oriented such that at least one memory cell is located over another memory cell. The at least one memory cell may include a charge trap layer. Each cell string may further include at least one selection transistor placed over the memory cells MC. The at least one selection transistor may have the same structure as the memory cells MC and may be formed uniformly with the memory cells MC. 
     The following patent documents, which are hereby incorporated by reference, describe suitable configurations for three-dimensional memory arrays, in which the three-dimensional memory array is configured as a plurality of levels, with word lines and/or bit lines shared between levels: U.S. Pat. Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and US Pat. Pub. No. 2011/0233648. 
       FIG. 3  is a perspective cross-sectional view illustrating an example of cell strings CS corresponding to the second and third bit lines BL 2  and BL 3  of the memory block BLK 1  of  FIG. 2 . Referring to  FIGS. 2 and 3 , common source regions CSR that extend along a first direction and are spaced from each other along a second direction are disposed on the substrate SUB. 
     The common source regions CSR may be connected in common to form a common source line CSL. In an embodiment, a substrate  101  includes a P-type semiconductor material. The common source regions CSR may include an N-type semiconductor material. For example, a conductive material for increasing conductivity of the common source line CSL may be disposed on the common source region CSR. 
     Pillars PL are located between the common source regions CSR. In an exemplary embodiment, the pillars PL are perpendicular to the substrate  101  or parallel to the third direction. Each of the pillars PL includes an inner material  114 , a channel layer  115 , and a first insulating layer  116 . 
     The inner material  114  may include an insulating material or an air gap. The channel layer  115  may include a P-type semiconductor material or an intrinsic semiconductor material. The first insulating layer  116  may include one or more of insulating layers (e.g., different insulating layers) such as a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer. 
     Insulating layers  112  and conductive materials CM 1  to CM 15  may be in turn stacked on the substrate  101  along the third direction perpendicular to the substrate  101 , so as to surround the pillars PL. In an embodiment, the insulating layers  112  may include silicon oxide or silicon nitride. 
     A second insulating layer  117  may be located between the pillars PL and the conductive materials CM 1  to CM 15  and between the conductive materials CM 1  to CM 15  and the insulating layers  112 . In each of the pillars PL, portions, which are adjacent to each other, of the first insulating layer  116  and the second insulating layer  117  may be coupled to form an information storage layer. For example, the first insulating layer  116  and the second insulating layer  117  may include an oxide-nitride-oxide (ONO) or oxide-nitride-aluminum (ONA). The first insulating layer  116  and the second insulating layer  117  may form a tunneling insulating layer, a charge trap layer, or a blocking insulating layer. 
     Drains  118  are disposed on the pillars PL. In an embodiment, the drains  118  include an N-type semiconductor material (e.g., silicon). The bit lines BL 2  and BL 3  that extend along the second direction and are spaced from each other along the first direction are disposed on the drains  118 . The bit lines BL 2  and BL 3  are connected with the drains  118 . 
     The pillars PL form the cell strings CS together with the first and second insulating layers  116  and  117  and the conductive materials CM 1  to CM 15 . Each of the pillars PL forms a cell string together with the first and second insulating layers  116  and  117  and the conductive materials CM 1  to CM 15 , which are adjacent thereto. The first conductive material CM 1  may form the ground selection transistors GST together with the first and second insulating layers  116  and  117  and the channel layers  115  adjacent thereto. The first conductive material CM 1  may extend along the first direction to form the ground selection line GSL. 
     The second conductive material CM 2  may form first dummy memory cells DMC 1  together with the adjacent first and second insulating layers  116  and  117  and the channel layers  115 . The second conductive material CM 2  may extend along the first direction to form the first dummy word line DWL 1 . 
     The third to twelfth conductive materials CM 3  to CM 12  may form the first to tenth memory cells MC 1  to MC 10  together with adjacent layers, that is, the first and second insulating layers  116  and  117  and the channel layers  115 . The third to twelfth conductive materials CM 3  to CM 12  may extend along the first direction to form the first to tenth word lines WL 1  to WL 10 . 
     The thirteenth conductive material CM 13  may form the second dummy memory cells DMC 2  together with adjacent layers, that is, the first and second insulating layers  116  and  117  and the channel layers  115 . The thirteenth conductive material CM 13  may extend along the first direction to form the second dummy word line DWL 2 . 
     The fourteenth and fifteenth conductive materials CM 14  and CM 15  may form the lower and upper string selection transistors SSTl and SSTu together with adjacent layers, that is, the first and second insulating layers  116  and  117  and the channel layers  115 . The fourteenth and fifteenth conductive materials CM 14  and CM 15  may extend along the first direction to form lower and upper string selection lines. 
     As illustrated in  FIG. 3 , each of the pillars PL may include a first portion adjacent to the substrate  101  and a second portion disposed on the first portion. For example, the first portion is disposed on the substrate and the second portion is stacked on the first portion. Because of a process of manufacturing a nonvolatile memory device, for example, a flash memory device, in the first portion corresponding to the first to seventh conductive materials CM 1  to CM 7 , the width or cross-sectional area of the pillars PL may become smaller as a distance from the substrate  101  decreases and may become larger as a distance from the substrate  101  increases. A boundary layer SP may be present between the first portion and the second portion. In an exemplary embodiment, the boundary layer SP includes a same material as a channel layer  115 . 
     Likewise, in the second portion corresponding to the eighth to fifteenth conductive materials CM 8  to CM 15 , the width or cross-sectional area of the pillars PL may become smaller as a distance from the substrate  101  decreases and may become larger as a distance from the substrate  101  increases. For example, outer walls of the pillars PL may include slanted portions. 
       FIG. 4  is a cross-sectional view schematically illustrating the memory block BLK 1  of  FIG. 3 . Referring to  FIGS. 1 to 4 , the pillars PL include first portions PL 1  adjacent to the substrate  101  and second portions PL 2  disposed on the first portions PL 1 . 
     The fourteenth conductive materials CM 14  and the fifteenth conductive materials CM 15  may be separated by a selection line cut SC between the second portions PL 2  of the pillars PL. The first to fifteenth conductive materials CM 1  to CM 15  may be separated from different conductive materials by word line cuts WC at opposite sides of the pillars PL. 
     The seventh conductive materials CM 7  and the eighth conductive materials CM 8  are adjacent to a boundary between the first portions PL 1  and the second portions PL 2 . The seventh conductive materials CM 7  and the eighth conductive materials CM 8  located at the boundary between the first portions PL 1  and the second portions PL 2  may cause a decrease in reliability. For example, a conductive material may be considered adjacent to the boundary when its distance from the boundary is less than or equal a certain threshold distance and considered non-adjacent to the boundary when the distance is greater than the threshold distance. For example, a first conductive material may be considered adjacent to the boundary when there is no intervening second conductive material in a given portion (e.g., PL 1 , PL 2 , etc.) between the boundary and the first conductive material. 
     For example, as the cross-sectional area of the pillar PL increases, a program speed (or efficiency) decreases. Accordingly, as the cross-sectional area of the pillar PL increases, a level of a program voltage for programming the same data may increase. 
     Accordingly, a level of a program voltage for programming memory cells (e.g., MC 5 ) corresponding to the seventh conductive materials CM 7  may be higher than a level of a program voltage for programming different memory cells. That is, a program operation associated with the seventh conductive materials CM 7  adjacent to the boundary may act as a strong aggressor causing disturbance at data written at different memory cells adjacent thereto. 
     In an exemplary embodiment, a distance between the eighth conductive materials CM 8  and the first portions PL 1  of the pillars PL is smaller than distances between the remaining conductive materials (i.e., conductive materials above the eighth conductive materials CM 8 ) and the pillars PL. That is, when a program voltage is applied to the eighth conductive materials CM 8 , the program voltage may have a strong influence on the first portions PL 1  of the pillars PL. 
     For example, lateral spreading may occur at the first portions PL 1  of the pillars PL. The lateral spreading indicates a phenomenon in which charges trapped in the first insulating layers  116  of the pillars PL are spread in the third direction or in a direction opposite to the third direction. In the case where the lateral spreading occurs, threshold voltages of memory cells (e.g., MC 5 ) corresponding to the seventh conductive materials CM 7  may change, thereby reducing the reliability of data. 
     As described above, a program operation of memory cells (e.g., adjacent memory cells) adjacent to the boundary of the first portions PL 1  and the second portions PL 2  of the pillars PL may reduce the reliability of data written in surrounding memory cells. 
     The reliability of the nonvolatile memory device  100  according to an exemplary embodiment of the inventive concept may be improved by adjusting orders of program operations of adjacent memory cells and memory cells (e.g., non-adjacent memory cells) not adjacent to the boundary. Also, by considering the reliability of the adjacent memory cells having low reliability, the nonvolatile memory device  100  may use the adjacent memory cells for data storage and may prevent a decrease of a capacity. 
       FIG. 5  illustrates an operating method of the nonvolatile memory device  100  according to an exemplary embodiment of the inventive concept. In an embodiment, in  FIG. 5 , there is illustrated an example in which, when program operations are consistently (or consecutively) requested with respect to a particular memory block (e.g., a selected memory block) of the nonvolatile memory device  100 . For example, the nonvolatile memory device  100  performs program operations under the condition that adjacent memory cells adjacent to the boundary between the first portions PL 1  and the second portions PL 2  of the pillars PL and non-adjacent memory cells are distinguished. For example, the nonvolatile memory device  100  may re-order the program operations so that some or all of the program operations of the non-adjacent memory cells are performed or complete before the program operations of the adjacent memory cells are performed. 
     Referring to  FIGS. 1, 4, and 5 , in operation S 110 , when program operations are consecutively requested with respect to a selected memory block, the nonvolatile memory device  100  preferentially performs program (e.g., write) operations on non-adjacent memory cells in the selected memory block. 
     After the program operations of the non-adjacent memory cells in the selected memory block have completed, in operation S 120 , the nonvolatile memory device  100  performs program operations on adjacent memory cells. That is, the nonvolatile memory device  100  preferentially programs non-adjacent memory cells and then programs adjacent memory cells. 
     In an exemplary embodiment, when first to third memory cells of a given memory block are initially scheduled to be sequentially programmed, the second memory cell is an adjacent memory cell (e.g., nearest a boundary between portions of a pillar), and the first and third memory cells are non-adjacent memory cells, the control logic  160  controls the memory device  100  to program the first memory cell during a first time, program the third memory cell during a second time after the first time and program the second memory cell during a third time after the second time. In another embodiment, the control logic  160  is configured to schedule program operations of the first memory cell, the third memory cell and then the second memory cell sequentially based on adjacency of the first through third memory cells to the boundary layer SP. 
     Adjacent memory cells may be designated differently depending on whether any of an influence of a strong aggressor and an influence of the lateral spreading is more dominant at the boundary of the pillars PL of the nonvolatile memory device  100 . 
     In an embodiment, that a program (or a program operation) of particular memory cells has completed may mean that a nonvolatile memory device completes the writing of all data to be stored in the particular memory cells. That is, the nonvolatile memory device  100  may inhibit additional program operations of program-completed memory cells until the program-completed memory cells are erased. 
       FIG. 6  illustrates examples of schemes in which the nonvolatile memory device  100  performs program operations. Referring to  FIGS. 1, 4, and 6 , locations of adjacent memory cells are depicted with a dot-filled box or shading. In a 1st scheme, the memory cells MC 5  of the fifth word line WL 5 , which belongs to the first portions PL 1  of the pillars PL and is the closest to the boundary, are designated as adjacent memory cells. 
     In operation S 211 , the nonvolatile memory device  100  first performs program operations on the non-adjacent memory cells MC 6  to MC 10  of the sixth to tenth word lines WL 6  to WL 10  of the second portions PL 2  of the pillars PL. Afterwards, in operation S 212 , the nonvolatile memory device  100  performs program operations on the non-adjacent memory cells MC 1  to MC 4  of the first to fourth word lines WL 1  to WL 4  of the first portions PL 1  of the pillars PL. 
     Afterwards, in operation S 213 , the nonvolatile memory device  100  performs program operations on the adjacent memory cells MC 5  of the fifth word line WL 5  of the first portions PL 1  of the pillars PL. In an embodiment, the 1st scheme is selected in the case where the influence of the lateral spreading is determined to be dominant at the boundary. 
     In a 2nd scheme, the memory cells MC 5  of the fifth word line WL 5 , which belongs to the first portions PL 1  of the pillars PL and is the closest to the boundary, and the memory cells MC 6  of the sixth word line WL 6 , which belongs to the second portions PL 2  of the pillars PL and is the closest to the boundary, are designated as adjacent memory cells. In operation S 221  and operation S 222 , the nonvolatile memory device  100  completes program operations of the non-adjacent memory cells. 
     Afterwards, in operation S 223 , the nonvolatile memory device  100  completes program operations of the adjacent memory cells. For example, the nonvolatile memory device  100  may perform program operations in the order of the memory cells MC 5  of the fifth word line WL 5  and the memory cells MC 6  of the sixth word line WL 6  or in the order of the memory cells MC 6  of the sixth word line WL 6  and the memory cells MC 5  of the fifth word line WL 5 . In an exemplary embodiment, the 2nd scheme is selected in the case where the influence of the strong aggressor and the influence of the lateral spreading are similar. 
     In a 3rd scheme, the memory cells MC 6  of the sixth word line WL 6 , which belongs to the second portions PL 2  of the pillars PL and is the closest to the boundary, is designated as adjacent memory cells. In operation S 231  and operation S 232 , the nonvolatile memory device  100  completes program operations of non-adjacent memory cells. 
     Afterwards, in operation S 233 , the nonvolatile memory device  100  completes program operations of the adjacent memory cells MC 6  of the sixth word line WL 6 . In an exemplary embodiment, the 3rd scheme is selected in the case where the influence of the strong aggressor is dominant. 
     In an exemplary embodiment of the inventive concept, the nonvolatile memory device  100  designates addresses of memory cells depending on orders of program operations. That is, in the nonvolatile memory device  100 , addresses of non-adjacent memory cells may be followed by addresses of adjacent memory cells. For example, during a given program period in which a given memory block is programmed, the row decoder block  120  may receive the addresses (e.g., row addresses) of the non-adjacent memory cells, and then receive the addresses (e.g., row addresses) of the adjacent memory cells from the buffer block  150 . 
     The nonvolatile memory device  100  may designate orders of program operations of non-adjacent memory cells reversely. For example, as illustrated in  FIG. 6 , the nonvolatile memory device  100  may perform program operations on non-adjacent memory cells in a direction from the bit lines BL 1  to BL 4  to the substrate  101 ; in contrast, the nonvolatile memory device  100  may perform program operations on non-adjacent memory cells in a direction from the substrate  101  to the bit lines BL 1  to BL 4 . 
       FIG. 7  illustrates an example in which the pillars PL of a memory block are composed of first to third portions PL 1  to PL 3 . Referring to  FIGS. 1, 2, and 7 , the pillars PL includes first portions PL 1  disposed on the substrate  101 , second portions PL 2  disposed on the first portions PL 1 , and third portions PL 3  disposed on the second portions PL 2 . 
     A first boundary between the first portions PL 1  and the second portions PL 2  is located between the fifth and sixth conductive materials CMS and CM 6 . A second boundary between the second portions PL 2  and the third portions PL 3  is located between the tenth and eleventh conductive materials CM 10  and CM 11 . The nonvolatile memory device  100  may designate adjacent memory cells at the first boundary and the second boundary. 
       FIG. 8  illustrates examples in which the nonvolatile memory device  100  performs program operations in a memory block of  FIG. 7 . Referring to  FIGS. 1, 2, 7, and 8 , the nonvolatile memory device  100  may select one of 1st to 9th schemes. 
     In the 4th scheme, the memory cells MC 3  of the third word line WL 3 , which belongs to the first portions PL 1  of the pillars PL and is the closest to the first boundary, and the memory cells MC 8  of the eighth word line WL 8 , which belongs to the second portions PL 2  of the pillars PL and is the closest to the second boundary, are designated as adjacent memory cells. In operation S 311  to operation S 313 , the nonvolatile memory device  100  completes program operations of the non-adjacent memory cells. 
     Afterwards, in operation S 314 , the nonvolatile memory device  100  performs a program operations on the adjacent memory cells MC 8  of the eighth word line WL 8  of the second portions PL 2  of the pillars PL. Afterwards, in operation S 315 , the nonvolatile memory device  100  performs program operations on the adjacent memory cells MC 3  of the third word line WL 3  of the first portions PL 1  of the pillars PL. 
     The adjacent memory cells designated in the 5th scheme are the same as the adjacent memory cells designated in the 4th scheme. In operation S 321  and operation S 322 , the nonvolatile memory device  100  completes program operations of non-adjacent memory cells belonging to the third portions PL 3  and the second portions PL 2  of the pillars PL. Then, in operation S 323 , the nonvolatile memory device  100  performs program operations on the adjacent memory cells MC 8  of the eighth word line WL 8  of the second portions PL 2  of the pillars PL. 
     In operation S 324 , the nonvolatile memory device  100  completes program operations of non-adjacent memory cells belonging to the first portions PL 1  of the pillars PL. Afterwards, in operation S 325 , the nonvolatile memory device  100  performs program operations on the adjacent memory cells MC 3  of the third word line WL 3  belonging to the first portions PL 1  of the pillars PL. 
     That is, in the case of the 4th scheme, adjacent memory cells are completely programmed after all non-adjacent memory cells are completely programmed. In the case of the 5th scheme, after memory cells surrounding a particular boundary have been completely programmed, corresponding non-adjacent memory cells are completely programmed. 
     In the 6th scheme, the memory cells MC 3  of the third word line WL 3 , which belongs to the first portions PL 1  of the pillars PL and is the closest to the first boundary, the memory cells MC 4  of the fourth word line WL 4 , which belongs to the second portions PL 2  and is the closest to the first boundary, the memory cells MC 8  of the eighth word line WL 8 , which belongs to the second portions PL 2  and is the closest to the second boundary, and the memory cells MC 9  of the ninth word line WL 9 , which belongs to the third portions PL 3  and is the closest to the second boundary, are designated as adjacent memory cells. In operation S 331  to operation S 333 , the nonvolatile memory device  100  completes program operations of non-adjacent memory cells. 
     Afterwards, in operation S 334 , the nonvolatile memory device  100  completes program operations of the adjacent memory cells MC 8  and MC 9  of the eighth and ninth word lines WL 8  and WL 9  adjacent to the second boundary. Program operations may be performed in the order of the memory cells MC 8  of the eighth word line WL 8  and the memory cells MC 9  of the ninth word lines WL 9  or in the order of the memory cells MC 9  of the ninth word lines WL 9  and the memory cells MC 8  of the eighth word line WL 8 . 
     Afterwards, in operation S 335 , the nonvolatile memory device  100  completes program operations of the adjacent memory cells MC 3  and MC 4  of the third and fourth word lines WL 3  and WL 4  adjacent to the first boundary. Program operations may be performed in the order of the memory cells MC 3  of the third word line WL 3  and the memory cells MC 4  of the fourth word lines WL 4  or in the order of the memory cells MC 4  of the fourth word lines WL 4  and the memory cells MC 3  of the third word line WL 3 . 
     The adjacent memory cells designated in the 7th scheme are the same as the adjacent memory cells designated in the 6th scheme. In operation S 341  and operation S 342 , the nonvolatile memory device  100  completes program operations of non-adjacent memory cells belonging to the third portions PL 3  and the second portions PL 2  of the pillars PL. 
     Afterwards, in operation S 343 , the nonvolatile memory device  100  completes program operations of the adjacent memory cells MC 8  and MC 9  of the eighth and ninth word lines WL 8  and WL 9  adjacent to the second boundary. Program operations may be performed in the order of the memory cells MC 8  of the eighth word line WL 8  and the memory cells MC 9  of the ninth word lines WL 9  or in the order of the memory cells MC 9  of the ninth word lines WL 9  and the memory cells MC 8  of the eighth word line WL 8 . 
     Afterwards, in operation S 344 , the nonvolatile memory device  100  completes program operations of non-adjacent memory cells belonging to the first portions PL 1  of the pillars PL. Afterwards, in operation S 345 , the nonvolatile memory device  100  completes program operations of the adjacent memory cells MC 3  and MC 4  of the third and fourth word lines WL 3  and WL 4  adjacent to the first boundary. Program operations may be performed in the order of the memory cells MC 3  of the third word line WL 3  and the memory cells MC 4  of the fourth word lines WL 4  or in the order of the memory cells MC 4  of the fourth word lines WL 4  and the memory cells MC 3  of the third word line WL 3 . 
     Operation S 351  to operation S 355  of the 8th scheme are identical to those of the 4th scheme except that the memory cells MC 9  of the ninth word line WL 9  are selected as adjacent memory cells instead of the eighth word line WL 8  with regard to the second boundary and the memory cells MC 4  of the fourth word line WL 4  are selected as adjacent memory cells instead of the memory cells MC 3  of the third word line WL 3  with regard to the first boundary. 
     Operation S 361  to operation S 365  of the 9th scheme are identical to those of the 5th scheme except that the memory cells MC 9  of the ninth word line WL 9  are selected as adjacent memory cells instead of the memory cells MC 8  of the eighth word line WL 8  with regard to the second boundary, and the memory cells MC 4  of the fourth word line WL 4  are selected as adjacent memory cells instead of the memory cells MC 3  of the third word line WL 3  with regard to the first boundary. 
     As described with reference to  FIG. 6 , the nonvolatile memory device  100  may designate addresses of memory cells depending on an order of program operations. Also, the nonvolatile memory device  100  may change the orders of the program operations of the non-adjacent memory cells reversely. 
     Boundary characteristics of the pillars PL may vary depending on a manufacturing process. Accordingly, orders of program operations that are applied to boundaries in the same pillar may be varied. For example, an order of programming memory cells of two word lines in operation S 334  (or operation S 343 ) may be different from an operation of programming memory cells of two word lines in operation S 335  (or operation S 345 ). 
     For example, with regard to the first boundary, adjacent memory cells of a word line relatively close to a substrate are completely programmed, and then, adjacent memory cells of a word line relatively distant from the substrate are completely programmed. In contrast, with regard to the second boundary, adjacent memory cells of a word line relatively distant from the substrate are completely programmed, and then, adjacent memory cells of a word line relatively close to the substrate are completely programmed. 
     Locations of adjacent memory cells to be designated with regard to each boundary and a program scheme to be applied with regard to each boundary, for example, orders of program operations may be set through an option (e.g., a fuse option) after the nonvolatile memory device  100  is manufactured. For example, the memory device may include one or more fuses or anti-fuses set during manufacturing to indicate which of the schemes to use. For example, the control logic block  160  may analyze the settings (e.g., open or closed) of the fuses or anti-fuses to determine which of the schemes to implement. 
       FIG. 9  illustrates an operating method of a nonvolatile memory device according to an exemplary embodiment of the inventive concept. Referring to  FIGS. 1, 2, and 9 , in operation S 410 , the nonvolatile memory device  100  performs single step program operations on non-adjacent memory cells of a selected memory block. In the single step program operation, selected memory cells targeted for a program operation are completely programmed through one program operation. 
     In operation S 420 , the nonvolatile memory device  100  perform multi step program operations on adjacent memory cells of the selected memory block. In the multi-step program operation, selected memory cells targeted for a program operation are completely programmed through two or more program operations. Between two or more program operations, a program operation (e.g., a single or multi step program operation) may be performed on memory cells of an adjacent word line. 
       FIG. 10  illustrates an example of a single step program operation. In a first block B 1  and a third block B 3  of  FIG. 10 , a horizontal axis represents threshold voltages VTH of memory cells, and a vertical axis represents the number of memory cells. In a second block B 2  of  FIG. 10 , a horizontal axis represents a time “T”, and a vertical axis represents a voltage “V” to be applied to memory cells through a word line. 
     As illustrated in the first block B 1 , memory cells of an erase state have threshold voltages belonging to one threshold voltage range (e.g., state). A program operation for memory cells may include two or more program loops. The second block B 2  illustrates an exemplary program loop. 
     In each program loop, a program voltage VPGM may be applied to memory cells through a word line. The program voltage VPGM may increase threshold voltages of the memory cells. Afterwards, verify voltages VFYs may be applied to the memory cells. The verify voltages VFYs may be used to verify whether the threshold voltages of the memory cells reach a target state. 
     For example, when four bits are written in each memory cell, program-completed memory cells may have one of 16 states. In this case, 15 verify voltages VFYs may be used. The 15 verify voltages VFYs may be used to verify whether the threshold voltages of the memory cells reach a target state of one of 15 states (e.g., program states) higher than the erase state. 
       FIG. 11  illustrates an example of a multi-step program operation. In a fourth block B 4 , a sixth block B 6 , and an eighth block B 8  of  FIG. 11 , a horizontal axis represents threshold voltages VTH of memory cells, and a vertical axis represents the number of memory cells. In a fifth block B 5  and a seventh block B 7  of  FIG. 11 , a horizontal axis represents a time “T”, and a vertical axis represents a voltage “V” to be applied to memory cells through a word line. 
     In an exemplary embodiment, the multi-step program operation includes a 1-step program operation and a 2-step program operation. Each of the 1-step program operation and the 2-step program operation may include two or more program loops. The fifth block B 5  illustrates an example of a program loop of the 1-step program operation. 
     A program loop may include a program voltage VPGM and verify voltages VFYs. For example, the number of verify voltages VFYs may be 7. In the case where the 1-step program operation has completed, as illustrated in the fourth block B 4  and the sixth block B 6 , memory cells may be programmed from an erase state to one of the erase state and 7 program states. 
     The seventh block B 7  illustrates an example of a program loop of the 2-step program operation. A program loop may include a program voltage VPGM and verify voltages VFYs. For example, the number of verify voltages VFYs may be 15. In the case where the 2-step program operation has completed, the memory cells in the 8 states of the sixth block B 6  may be programmed to one of 16 states of the eighth block B 8 . 
     As illustrated in  FIG. 11 , bits may be written in respective memory cells through the 1-step program operation, and additional bits may be further written in the memory cells through the 2-step program operation. That is, the number of bits stored in each memory cell when the 1-step program operation has completed may be different from the number of bits stored in each memory cell when the 2-step program operation has completed. 
     For example, bits may be coarsely written in memory cells through the 1-step program operation. The bits coarsely written in the memory cells may be finely written through the 2-step program operation. That is, the number of bits stored in each memory cell when the 1-step program operation has completed may be identical to the number of bits stored in each memory cell when the 2-step program operation has completed. 
     In an embodiment, threshold voltages of the dummy memory cells DMC 1  and DMC 2  illustrated in  FIG. 2  are different from threshold voltages of the third block B 3  and the eighth block B 8 . The dummy memory cells DMC 1  and DMC 2  may have threshold voltages belonging to one distribution range widely formed between the lowest state and the highest state of the third block B 3  and the eighth block B 8 . 
       FIGS. 12 and 13  illustrate examples in which the nonvolatile memory device  100  performs program operations depending on the operating method of  FIG. 9 . Referring to  FIGS. 1, 2, 7, and 12 , the nonvolatile memory device  100  selects one of 10th to 18th schemes. 
     In the 10th scheme, the memory cells MC 8  of the eighth word line WL 8 , which belongs to the second portions PL 2  of the pillars PL and is the closest to the second boundary, and the memory cells MC 3  of the third word line WL 3 , which belongs to the first portions PL 1  of the pillars PL and is the closest to the first boundary, are designated as adjacent memory cells. 
     Through operation S 511  to operation S 515 , the nonvolatile memory device  100  may sequentially program memory cells in a direction from the bit lines BL 1  to BL 4  to the substrate  101 . In this case, the nonvolatile memory device  100  completes program operations of non-adjacent memory cells and partially performs program operations of adjacent memory cells. For example, the nonvolatile memory device  100  completes only 1-step program operations of the adjacent memory cells (operation S 512  and operation S 514 ). 
     Afterwards, the nonvolatile memory device  100  completes the program operations of the adjacent memory cells by completing 2-step program operations of the adjacent memory cells (operation S 516  and operation S 517 ). 
     The adjacent memory cells designated in the 11th scheme are the same as the adjacent memory cells designated in the 10 th  scheme. Through operation S 521  to operation S 523 , the nonvolatile memory device  100  completes program operations of non-adjacent memory cells in a direction from the bit lines BL 1  to BL 4  to the substrate  101  and then completes a 1-step program operation of the adjacent memory cells. 
     Afterwards, in operation S 524 , the nonvolatile memory device  100  completes a 2-step program operation of adjacent memory cells between the program-completed non-adjacent memory cells. Afterwards, in operation S 525  and operation S 526 , the nonvolatile memory device  100  completes a 1-step program operation of non-adjacent memory cells in the same direction and completes a 1-step program operations of adjacent memory cells. 
     Afterwards, in operation S 527 , the nonvolatile memory device  100  completes a 2-step program operation of adjacent memory cells between the program-completed non-adjacent memory cells. 
     In an embodiment, the nonvolatile memory device  100  divides operation S 523  into portions or sub-operations. For example, the nonvolatile memory device  100  may perform operation S 524  after completing a program operation of non-adjacent memory cells MC 7  closest to the second boundary (e.g., a portion of operation S 523 ). Afterwards, the nonvolatile memory device  100  may perform the remaining portions of operation S 523 . 
     The adjacent memory cells designated in the 12th scheme are the same as the adjacent memory cells designated in the 10 th  scheme. Through operation S 531  to operation S 534 , the nonvolatile memory device  100  completes program operations of non-adjacent memory cells in a direction from the bit lines BL 1  to BL 4  to the substrate  101  and completes a 1-step program operation of the adjacent memory cells. 
     Afterwards, in operation S 535 , the nonvolatile memory device  100  completes a 2-step program operation of adjacent memory cells between the program-completed non-adjacent memory cells. Afterwards, in operation S 536 , the nonvolatile memory device  100  completes program operations of non-adjacent memory cells. Afterwards, in operation S 537 , the nonvolatile memory device  100  completes a 2-step program operation of adjacent memory cells between the program-completed non-adjacent memory cells. 
     In the 13th scheme, the memory cells MC 9  of the ninth word line WL 9 , which belongs to the third portions PL 3  of the pillars PL and is the closest to the second boundary, the memory cells MC 8  of the eighth word line WL 8 , which belongs to the second portions PL 2  and is the closest to the second boundary, the memory cells MC 4  of the fourth word line WL 4 , which belongs to the second portions PL 2  and is the closest to the first boundary, and the memory cells MC 3  of the third word line WL 3 , which belongs to the first portions PL 1  and is the closest to the first boundary, are designated as adjacent memory cells. 
     Through operation S 541  to operation S 545 , the nonvolatile memory device  100  sequentially programs memory cells in a direction from the bit lines BL 1  to BL 4  to the substrate  101 . In this case, the nonvolatile memory device  100  completes program operations of non-adjacent memory cells and partially performs program operations of adjacent memory cells. 
     For example, the nonvolatile memory device  100  completes only 1-step program operations of the adjacent memory cells (operation S 542  and operation S 544 ). Afterwards, the nonvolatile memory device  100  completes the program operations of the adjacent memory cells by completing 2-step program operations of the adjacent memory cells (operation S 546  and operation S 547 ). 
     For example, in two word lines connected to adjacent memory cells, an order of 1-step program operations or 2-step program operations may be a direction from the bit lines BL 1  to BL 4  to the substrate  101  or in a direction from the substrate  101  to the bit lines BL 1  to BL 4 . 
     The adjacent memory cells designated in the 14th scheme are the same adjacent memory cells designated in the 13 th  scheme. Through operation S 551  to operation S 553 , the nonvolatile memory device  100  completes program operations of non-adjacent memory cells in a direction from the bit lines BL 1  to BL 4  to the substrate  101  and completes 1-step program operations of the adjacent memory cells. 
     Afterwards, in operation S 554 , the nonvolatile memory device  100  completes 2-step program operations of adjacent memory cells between the program-completed non-adjacent memory cells. Afterwards, in operation S 555  and operation S 556 , the nonvolatile memory device  100  completes program operations of non-adjacent memory cells in the same direction and completes 1-step program operations of adjacent memory cells. 
     Afterwards, in operation S 557 , the nonvolatile memory device  100  completes 2-step program operations of adjacent memory cells between the program-completed non-adjacent memory cells. 
     In an embodiment, the nonvolatile memory device  100  divides operation S 553  into portions or sub-operations. For example, the nonvolatile memory device  100  may perform operation S 554  after completing a program operation of non-adjacent memory cells MC 7  closest to the second boundary (e.g., a portion of operation S 553 ). Afterwards, the nonvolatile memory device  100  may perform the remaining portions of operation S 553 . 
     In the 15th scheme, the adjacent memory cells may be designated to be identical to the adjacent memory cells designed in the 13th scheme. Through operation S 561  to operation S 564 , the nonvolatile memory device  100  completes program operations of non-adjacent memory cells in a direction from the bit lines BL 1  to BL 4  to the substrate  101  and completes 1-step program operations of the adjacent memory cells. 
     Afterwards, in operation S 565 , the nonvolatile memory device  100  completes 2-step program operations of adjacent memory cells between the program-completed non-adjacent memory cells. Afterwards, in operation S 566 , the nonvolatile memory device  100  completes program operations of non-adjacent memory cells. Afterwards, in operation S 567 , the nonvolatile memory device  100  completes 2-step program operations of adjacent memory cells between the program-completed non-adjacent memory cells. 
     Referring to  FIGS. 1, 2, 7, 12, and 13 , the 16th scheme is identical to the 10th scheme except that the memory cells MC 9  of the ninth word line WL 9  are selected as adjacent memory cells instead of the memory cells MC 8  of the eighth word line WL 8  with regard to the second boundary and the memory cells MC 4  of the fourth word line WL 4  are selected as adjacent memory cells instead of the memory cells MC 3  of the third word line WL 3  with regard to the first boundary. 
     The 17th scheme is identical to the 11th scheme except that the memory cells MC 9  of the ninth word line WL 9  are selected as adjacent memory cells instead of the memory cells MC 8  of the eighth word line WL 8  with regard to the second boundary and the memory cells MC 4  of the fourth word line WL 4  are selected as adjacent memory cells instead of the memory cells MC 3  of the third word line WL 3  with regard to the first boundary. 
     The 18th scheme is identical to the 12th scheme except that the memory cells MC 9  of the ninth word line WL 9  are selected as adjacent memory cells instead of the memory cells MC 8  of the eighth word line WL 8  with regard to the second boundary and the memory cells MC 4  of the fourth word line WL 4  are selected as adjacent memory cells instead of the memory cells MC 3  of the third word line WL 3  with regard to the first boundary. 
     As described with reference to  FIG. 6 , the nonvolatile memory device  100  may designate addresses of memory cells depending on an order of program operations. Also, the nonvolatile memory device  100  may change the orders of the program operations of the non-adjacent memory cells reversely. Also, as described with reference to  FIG. 8 , at different boundaries, adjacent memory cells may be programmed in different orders. 
     Locations of adjacent memory cells to be designated with regard to each boundary and a program scheme to be applied with regard to each boundary, for example, orders of program operations may be set through an option (e.g., a fuse option) after the nonvolatile memory device  100  is manufactured. 
       FIG. 14  illustrates a storage device  200  including a nonvolatile memory device  210  according to an exemplary embodiment of the inventive concept. Referring to  FIG. 14 , the storage device  200  includes the nonvolatile memory device  210  and a controller  220  (e.g., a memory controller or control circuit). The nonvolatile memory device  210  may be configured and operate as described with reference to  FIGS. 1 to 13 . 
     A controller  220  may control a read operation, a write operation, and an erase operation of the nonvolatile memory device  210 . The controller  220  may include a host interface block  221  (e.g., a host interface circuit), a main control block  222  (e.g., a control circuit), and a memory manager block  223  (e.g., a memory manager or a control circuit). 
     The host interface block  221  may transfer a request or a command received from an external host device to the main control block  222 . The main control block  222  may generate a command CMD and an address ADDR for accessing the nonvolatile memory device  210  depending on a request of the external host device or an internal schedule and may transfer the command CMD and the address ADDR to the memory manager block  223 . 
     The memory manager block  223  may exchange the command CMD, the address ADDR, and the data “DATA” with the nonvolatile memory device  210  through the first channel CH 1  (refer to  FIG. 1 ). The memory manager block  223  may exchange a control signal CTRL with the nonvolatile memory device  210  through a second channel. 
       FIG. 15  illustrates an example of an operating method of the storage device  200  according to an exemplary embodiment of the inventive concept. Referring to  FIGS. 14 and 15 , in operation S 610 , the controller  220  performs a program operation of “n” pages (n being a positive integer of 2 or more) on non-adjacent memory cells. The controller  220  may control the nonvolatile memory device  210  such that a program operation is completed by writing “n” bits in each of the non-adjacent memory cells. 
     In operation S 620 , the controller  220  performs a program operation of “m” pages (m and n being positive integers) on adjacent memory cells. The controller  220  may control the nonvolatile memory device  210  such that a program operation is completed by writing “m” bits in each of the non-adjacent memory cells. In an exemplary embodiment, “m” is less than “n”. 
     In an exemplary embodiment, even if some or all of the “m” pages are initially scheduled to be programmed before some of the “n” pages, the controller  220  adjusts the program order so that all the “n” pages are first programmed, and then after the programming of the “n” pages have completed, all of the “m” pages are programmed. 
     The storage device  200  may improve the reliability of data written in an adjacent memory cell by writing data, the amount of which is less than the amount of data written in the non-adjacent memory cells, in the adjacent memory cells. In an embodiment, the adjacent memory cells are designated as illustrated in  FIGS. 6, 8, 12, and 13 . 
     In an exemplary embodiment, during a given programming period, a first amount of data is written to the non-adjacent memory cells during a first time of the period and a second amount of data is written to the adjacent memory cells during a second time of the period after the first time, where the second amount is less than the first amount. 
       FIG. 16  illustrates a storage device  300  according to an exemplary embodiment of the inventive concept. Referring to  FIGS. 1 and 16 , the storage device  300  includes a nonvolatile memory device  310  and a controller  320 . The controller  320  includes a host interface block  321 , a main control block  322 , a memory manager block  323 , a user cycle count block  324  (e.g., a counting circuit), and an adjacent memory cell manager block  325  (e.g., a memory manager or a control circuit). 
     The nonvolatile memory device  310 , the host interface block  321 , the main control block  322 , and the memory manager block  323  are identical to those described with reference to  FIG. 14 . Thus, additional description will be omitted to avoid redundancy. 
     The user cycle count block  324  receives operation information OI from the main control block  322 . The operation information OI may include information of operations directed to the nonvolatile memory device  310 . The user cycle count block  324  may count use cycles of the respective memory blocks BLK 1  to BLKz depending on the operation information OI. 
     For example, a use cycle of each memory block may include a program and erase count. The use cycle of each memory block may be calculated by applying weights to various parameters such as a program and erase count, a read count, and a left-along time after a program operation. 
     The user cycle count block  324  transfers use cycle information UC of the memory blocks BLK 1  to BLKz to the adjacent memory cell manager block  325 . The adjacent memory cell manager block  325  determines whether a use cycle of a particular memory block reaches a given threshold value. When it is determined that the use cycle of the particular memory block reaches the given threshold value, the adjacent memory cell manager block  325  transfers a threshold notification TI to the main control block  322 . 
     In an exemplary embodiment, the main control block  322  decreases the number of pages to be written in adjacent memory cells in response to the threshold notification TI. For example, two or more threshold values may be set for each of the memory blocks BLK 1  to BLKz. The two or more threshold values may correspond to boundaries of different heights (heights in the third direction) in each memory block. That is, the controller  320  may decrease the number of pages to be written in adjacent memory cells of boundaries of different heights at different timings, based on different threshold values. For example, if a first memory block is written, erased, and/or read from too often, the reliability of its adjacent memory cells may be lower than the adjacent memory cells of a second memory block that is written, erased, or read from less often. For example, the main control block  322  could initially allow all pages of the adjacent memory cells of the given block to be written, and then upon determining that the given memory block has been written, erased, and/or read too often, could only allow half of the pages to be written in the future. 
     The storage device  300  may use adjacent memory cells for the purpose of storing user data transferred from the external host device, storing internally generated meta data, or improving performance. In the case where adjacent memory cells are used to store user data and the number of pages to be written in the adjacent memory cells decreases, the storage device  300  may notify the host device of a decrease of a capacity. 
     In the above disclosure, components of the inventive concept are described by using blocks. The blocks may be implemented with various hardware devices, such as an integrated circuit, an application specific IC (ASCI), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD), firmware driven in hardware devices, software such as an application, or a combination of a hardware device and software. Also, the blocks may include circuits implemented with semiconductor elements in an integrated circuit or circuits implemented as an intellectual property (IP) block or core. 
     According to at least one embodiment of the inventive concept, a program operation of adjacent memory cells are performed after program operations of non-adjacent memory cells have completed. Accordingly, there are provided a nonvolatile memory device, a storage device, and an operating method of the nonvolatile memory device, which are capable of securing reliability while preventing the reliability of data from decreasing through the program operation of the non-adjacent memory cells and preventing a capacity from decreasing. 
     While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept.