Patent Publication Number: US-8988104-B2

Title: Multiple-time configurable non-volatile look-up-table

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention is related to the Look-Up-Table (LUT) in Logic Element (LE), the basic building block for Field Programmable Gate array (FPGA). In particular, the configuration data for the Non-Volatile LUT (NV-LUT) of the invention are non-volatile in contrast to the conventional SRAM based volatile LUT. In comparison with the Complex Programmable Logic Device (CPLD) having separated on-chip non-volatile memory units for storing configuration data, the NV-LUT of the invention stores non-volatile configuration data in each LE unit for direct accessing in configurable digital circuitries. 
     2. Description of the Related Art 
     FPGA has been broadly applied for configuring digital circuitries. FPGA is more economical than ASIC (Application Specific Integrated Circuit) for digital circuit development especially in advanced technology nodes for their pricy mask set and process costs. The demands for higher logic gate counts and performance have been driving FPGA toward the advanced process technology nodes. The combination logic functions are configured with the SRAM-based LUTs in Logic Elements (LEs) in FPGA. Application specific functions of digital circuitries are accomplished by connecting the multiple configured LEs through interconnection matrixes in FPGA. Since the SRAM-based LUTs are volatile the configurations are lost after power off. The applications of FPGA are required to have non-volatile memory for storing non-volatile configuration data and to load back to the SRAM cells in the LUTs after turning on the FPGA chip. FPGA (low LE counts) integrated with on-chip non-volatile memory units is the CPLD. In contrast to the development of FPGA for large numbers of LEs processed with the state of art nano-meter CMOS technology, CPLD has stayed in low LE numbers for the sub-micron process technology. The main reason for CPLD lagging far behind the FPGA development is due to lack of cost effective and scalable non-volatile memory devices available for digital circuitries processed with the standard CMOS technology. 
     Furthermore since the conventional embedded NVM cells for storing configuration data used in CPLD are arranged in separated arrays fetching the configuration data requires sensing circuitry to convert NVM current signals into the digital signals and to write the converted digital signals into the SRAM cells in each LE. The data fetching and loading processes not only consume more chip power but also slow down the chip initialization speed. The requirements for NVM sensing circuitry and SRAM writing circuitry for non-volatile configuration data loading also economically hinder direct incorporating NVM devices in each LE unit. With the applications of complementary NVM devices (U.S. patent application Ser. Nos. 13/399,753 and 13/454,871, the disclosures of which are incorporated herein by reference in their entirety), a pair of complementary SGLNVM devices can store non-volatile digital data and direct output the digital signals without going through sensing amplifiers. Capable of outputting digital data signals direct from plural pairs of complementary SGLNVM devices storing non-volatile configuration data makes a fully integrated NV-LUT possible. 
     For the completion of the configurable digital circuitries, the configurable interconnection matrix using SGLNVM devices processed with standard CMOS logic process has been disclosed (U.S. patent application Ser. No. 13/683,721, the disclosure of which is incorporated herein by reference in its entirety). 
     In summary, we have demonstrated the new invention of NV-LUT using SGLNVM devices processed with standard CMOS logic process. Without adding process cost we have provided good solutions for configurable digital circuitries in the following aspects: 1) NV-LUT omits the requirement of non-volatile memory for non-volatile configuration data storage; 2) NV-LUT has faster circuit initialization speeds and less power consumption from the saving of external configuration loading; 3) NV-LUT is multiple-time configurable (proven 20 k-time configurations for the SGLVNM devices fabricated by a foundry); 4) NV-LUT is scalable according to the standard logic process technology nodes. The NV-LUT of the invention can meet the demands for high logic gate counts and high performance in configurable digital circuitries from the benefits of the advanced logic process technology. 
     SUMMARY OF THE INVENTION 
     In this invention we have substituted the volatile LUT SRAM cells with the novel Single Gate Logic NVM (SGLNVM) cell devices to form Non-Volatile LUT (NV-LUT) in the LE, the basic FPGA building block. The scalable SGLNVM devices processed with the standard CMOS logic process are the non-volatile memory using the minimal logic gate length as the floating gate for charge storage with control gates embedded in the P-type substrate. The minimal SGLNVM device size of 0.2157 μm 2  has been demonstrated with foundry&#39;s standard 55 nm CMOS logic process. The threshold voltages of SGLNVM devices are shifted to a higher voltage state after programmed by injecting electrons to the single floating gate while the threshold voltages of SGLNVM devices can be erased to a low voltage state by removing the electrons from the floating gates or slightly injecting holes in the floating gates. Examples of the programmed and erased SGLNVM device characteristic curves are shown in  FIGS. 1   a  and  1   b.    
     The schematic of a pair  200  of complementary SGLNVM cell devices  210  and  220  is shown in  FIG. 2 . The two drain electrodes  211  and  221  of complementary SGLNVM devices  210  and  220  are the two input nodes to be applied with digital voltage rail (V DD  and V SS ) for read and with the voltage bias V DH  for programming. The common source electrode of the pair  200  of complementary SGLNVM devices is the output node  230  for the digital signals. The common control gates  240  of the complementary devices are applied with voltage biases for reading, programming, and erasing. Storing a non-volatile bit in NV-LUT is accomplished by a pair  200  of complementary SGLNVM cell devices. In respect of the pair  200  of complementary SGLNVM devices, one device  210  is programmed to the high threshold voltage state V tH  while the other device  220  remains in the low threshold voltage state V tL  for storing a digital “0”. For storing a digital “1”, one device  220  of the pair  200  of complementary SGLNVM devices is programmed to the high threshold voltage state while the other device  210  remains in the low threshold voltage state. In normal operation mode, the digital voltage rail V DD  and V SS  are applied to the input nodes  211  and  221 , respectively. With the applied control gate voltage V CG  lower than the high threshold voltage V tH  and higher than the low threshold voltage (V tL +V DD ) to the control gate  240 , the pair  200  of complementary SGLNVM devices passes the digital signals either V DD  (“1”) or V SS  (“0”) at the output node  230 . 
     An N-bit LUT  300  includes 2 N  pairs of complementary SGLNVM cell devices  200  and an N-bit digital switching multiplexer  350  as shown in  FIG. 3 . The control gates  240  of the 2 N  pairs  200  of complementary SGLNVM cells form a single control gate line  340  to be applied with the same voltage biases for reading, programming, and erasing. The common source electrodes  230  of the complementary pairs are the output nodes  230  connected to the data input nodes  351  of the N-bit digital switching multiplexer  350 . With the two electrodes  211  and  221  of each complementary pair  200  biased with V DD  and V SS  respectively for all the 2 N  pairs, the control gate line  340  is biased with the control gate voltage bias V CG , where V tH &gt;V CG &gt;(V tL +V DD ), to cause the complementary pairs  200  to output the digital signals. The digital signal input nodes  355  of the N-bit digital switching multiplexer receive N-bit digital signals to turn on a corresponding switch to connect one of the data input nodes  351  to the output node  352 . The N signal input bits (at nodes  355 ) act like the address code for accessing the non-volatile digital contents in the 2 N  pairs of complementary SGLNVM cells  200 . 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a better understanding of the present invention and to show how it may be carried into effect, reference will now be made to the following drawings, which show the preferred embodiment of the present invention, in which: 
         FIG. 1   a  shows the examples of SGLNVM device characteristic curves with drain voltage bias at 0.05V in logarithm scale processed with foundry&#39;s standard 55 nm CMOS logic process. 
         FIG. 1   b  shows the examples of SGLNVM device characteristic curves with drain voltage bias at V DD =1.2 V in linear scale processed with foundry&#39;s standard 55 nm CMOS logic process. 
         FIG. 2  shows the schematic for a pair of complementary SGLNVM devices according to an embodiment the invention. 
         FIG. 3  shows the schematics of N-bit Non-Volatile Look-Up-Table (NV-LUT) including 2 N  pairs of complementary SGLNVM devices and N-bit digital switching multiplexer according to one embodiment of the invention. 
         FIG. 4  shows a 4-bit NV-LUT according to one embodiment of the invention. 
         FIG. 5  shows the digital output signals (from node  452 ) of a 4-bit NV-LUT for a pre-configured codes of “1010010110100101 (A5A5h)” by decrementally varying 4-bit input signals at nodes  455  from “1111” to “0000” according to one embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following detailed description is meant to be illustrative only and not limiting. It is to be understood that other embodiment may be utilized and element changes may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. Those of ordinary skill in the art will immediately realize that the embodiments of the present invention described herein in the context of methods and schematics are illustrative only and are not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefits of this disclosure. 
     The 4-bit LUT is the standard configuration unit in LE in FPGA. Depending on the various architectures from different vendors for combination logic and arithmetic operations, an LE could consist of 1˜4 LUTs, control switches, and one D-flip flop for storing static memory bit. In the preferred embodiment, we have constructed a 4-bit NV-LUT  400  using 16 pairs ( 200 ) of N-type complementary SGLNVM cell devices and a 4-bit digital switching multiplexer  450  as shown in  FIG. 4 . The 16 pairs ( 200 ) of N-type complementary SGLNVM cells in 4-bit NV-LUT  400  have been substituted for the 16 bits of SRAM cells in the conventional 4-bit LUT. 
     Before configuring the NV-LUTs  400 , all the SGLNVM cell devices on the chip are initially erased to the low threshold voltage state V tL  by the conventional Fowler-Nordheim tunneling method. In configuring the NV-LUTs  400 , a high voltage pulse with amplitudes of several volts is applied to the selected control gate line  440  for several micro-seconds with a programming voltage V DH  (3.5V˜5V) biased to the drain electrodes of the selected programming SGLNVM cell devices. The configuration for a 4-bit NV-LUT  400  is done by programming all the 16 pairs of complementary SGLNVM cell devices (32 SGLNVM cell devices) in parallel. To form the complementary pairs (one in the programmed high voltage state V tH  and the other in the erased low voltage state V tL ), one half of the 32 SGLNVM cell devices are thus programmed to the high threshold voltage state V tH  and the other half of the 32 SGLNVM cell devices remain in the low threshold voltage state V tL  for the 4-bit NV-LUT. Each 4-bit NV-LUT in plural LEs of the Non-Volatile FPGA (NV-FPGA) can be individually configured according to the specific requirements of digital circuitries. 
     In normal operation mode after configuration, all the pairs  200  of complementary SGLNVM cells are biased to the digital voltage rail V DD  and V SS  respectively. A control gate voltage bias V CG , where V tH &gt;V CG &gt;(V tL +V DD ), is applied to the control gate lines  450  to output the digital signals, V DD  “1” and V SS  “0”, from the NV-LUTs  400  in LEs.  FIG. 5  shows a pre-programmed pattern of the digital output signals (at node  452 ) from the 16 pairs of complementary SGLNVM cells  200  of a 4-bit NV-LUT  400  by decrementally changing the 4 input bits (at nodes  455 ) from “1111” to “0000” in the embodiment. 
     Please note that the pairs  200  of complementary SGLNVM cell devices in the above embodiments are provided by way of examples and not limitations of the invention. In an alternative embodiment, the pairs  200  of complementary SGLNVM cell devices can be replaced with pairs of complementary NVM cell devices of other types. 
     The aforementioned description of the preferred embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations of non-volatile memory elements including the types of non-volatile memory device made of different non-volatile material and the types of reset transistors will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.