Patent Publication Number: US-2022238474-A1

Title: Electronic component embedded substrate and circuit module using the same

Description:
TECHNICAL FIELD 
     The present invention relates to an electronic component embedded substrate and a circuit module using the same and, more particularly, to an electronic component embedded substrate for mounting an electronic component having large heat generation, such as a laser diode or a power supply inductor, and a circuit module using such an electronic component embedded substrate. 
     BACKGROUND ART 
     When an electronic component having large heat generation is mounted on the front surface of a multilayer substrate, the multilayer substrate may sometimes be provided with a heat dissipation path so as to dissipate heat toward the back surface side thereof. For example, Patent Document 1 proposes a multilayer substrate having a structure in which a metal block is embedded in a position overlapping in a plan view an electronic component having large heat generation with the front surface of the thus embedded metal block and the electronic component connected through a plurality of via conductors and with the back surface of the metal block and a heat dissipation pattern provided on the back surface of the multilayer substrate connected through another plurality of via conductors. The heat dissipation pattern provided on the back surface of the multilayer substrate is connected to a heat dissipation path on a motherboard through a solder or the like. The heat dissipation path on the motherboard is typically a ground pattern. This allows heat generated from the electronic component to be dissipated to the motherboard through the metal block, so that high heat dissipation efficiency can be achieved even for an electronic component having large heat generation. 
     CITATION LIST 
     Patent Document 
     
         
         [Patent Document 1] JP 2019-046954A 
       
    
     SUMMARY OF THE INVENTION 
     Problem to be Solved by the Invention 
     However, when an electronic component of a type not only having large heat generation but also being prohibited from connecting to the ground pattern, such as a laser diode or a power supply inductor, is used, the structure described in Patent Document 1 cannot be employed. 
     It is therefore an object of the present invention to improve heat dissipation efficiency in an electronic component embedded substrate for mounting an electronic component of a type having large heat generation and being prohibited from connecting to a ground pattern and a circuit module using such an electronic component embedded substrate. 
     Means for Solving the Problem 
     An electronic component embedded substrate according to the present invention has: a substrate including a plurality of wiring layers including at least first and second wiring layers and a plurality of insulating layers including at least a first insulating layer positioned between the first and second wiring layers, the plurality of wiring layers and the plurality of insulating layers being alternately stacked; a first electronic component and a heat transfer block which are embedded in the first insulating layer; a first wiring pattern positioned in the first wiring layer and facing one surface of the heat transfer block; a second wiring pattern positioned in the second wiring layer and facing the other surface of the heat transfer block; a first via conductor connecting the first wiring pattern and the one surface of the heat transfer block; and a second via conductor connecting the second wiring pattern and the other surface of the heat transfer block. The first wiring pattern is connected to the first electronic component and is positioned in an electronic component mounting area for mounting a second electronic component. The one surface and the other surface of the heat transfer block are insulated from each other, and whereby the first and second wiring patterns are insulated from each other. 
     According to the present invention, the one surface and the other surface of the heat transfer block are insulated from each other, so that even when an electronic component of a type having large heat generation and being prohibited from connecting to a ground pattern is mounted as the second electronic component, the second wiring pattern functioning as a heat dissipation pattern can be connected to a ground pattern on a motherboard. This can achieve high heat dissipation performance. 
     In the present invention, the heat transfer block may be formed of an SOI (Silicon On Insulator) chip, may be composed of a metal body part and an insulating film formed on one or both surface of the metal body part, or may be made of a ceramic material. That is, the heat transfer block is not particularly limited in terms of material and structure as long as one and the other surfaces thereof are insulated from each other and it has a high heat conductivity. 
     A circuit module according to the present invention includes the above electronic component embedded substrate and a second electronic component mounted in the electronic component mounting area. The first and second electronic components are connected to each other through the first wiring pattern. 
     According to the present invention, the first and second wiring patterns are insulated from each other, thus allowing signals to be exchanged between the first and second electronic components through the first wiring pattern. 
     In the present invention, the second electronic component may be a laser diode or a power supply inductor. Although the laser diode and power supply inductor are each an electronic component of a type having large heat generation and being prohibited from connecting to a ground pattern, such an electronic component still can efficiently dissipate heat through the electronic component embedded substrate. 
     Advantageous Effects of the Invention 
     As described above, according to the present invention, heat dissipation efficiency can be improved in an electronic component embedded substrate for mounting an electronic component of a type having large heat generation and being prohibited from connecting to a ground pattern and a circuit module using such an electronic component embedded substrate. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a schematic cross-sectional view for explaining the structure of an electronic component embedded substrate  1  according to a preferred embodiment of the present invention. 
         FIG. 2  is a schematic diagram for explaining a structure of a heat transfer block  40 A according to a first example. 
         FIG. 3  is a schematic diagram for explaining a structure of a heat transfer block  40 B according to a second example. 
         FIG. 4  is a schematic diagram for explaining a structure of a heat transfer block  40 C according to a third example. 
         FIG. 5  is a schematic diagram for explaining a structure of a heat transfer block  40 D according to a fourth example. 
         FIG. 6  is a schematic diagram for explaining a structure of a heat transfer block  40 E according to a fifth example. 
         FIG. 7  is a schematic diagram for explaining a structure of a heat transfer block  40 F according to a sixth example. 
         FIG. 8  is a schematic diagram for explaining a structure of a heat transfer block  40 G according to a seventh example. 
         FIG. 9  is a schematic diagram for explaining a structure of a heat transfer block  40 H according to an eighth example. 
         FIG. 10  is a schematic cross-sectional view for explaining the structure of a circuit module  2  using the electronic component embedded substrate  1 . 
         FIG. 11  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 12  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 13  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 14  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 15  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 16  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 17  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 18  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 19  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 20  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 21  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 22  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 23  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 24  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 25  is a process view for explaining the manufacturing method for the electronic component embedded substrate  1 . 
         FIG. 26  is a schematic diagram for explaining a first example in which an electronic component  30  and a heat transfer block  40  are positioned at mutually different layers. 
         FIG. 27  is a schematic diagram for explaining a second example in which an electronic component  30  and a heat transfer block  40  are positioned at mutually different layers. 
     
    
    
     MODE FOR CARRYING OUT THE INVENTION 
     Preferred embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. 
       FIG. 1  is a schematic cross-sectional view for explaining the structure of an electronic component embedded substrate  1  according to a preferred embodiment of the present invention. 
     As illustrated in  FIG. 1 , the electronic component embedded substrate  1  according to the present embodiment includes a substrate  10 , an electronic component  30 , and a heat transfer block  40 . The electronic component  30  and heat transfer block  40  are embedded in the substrate  10 . An electronic component mounting area A is provided on the side of an upper surface  10   a  of the substrate  10 , and the electronic component  30  controls an electronic component mounted in the electronic component mounting area A. The electronic component  30  has a pair of signal terminals  31  and  32 , a power supply terminal  33 , and the like. 
     The substrate  10  has a structure in which four insulating layers  11  to  14  are stacked one on another, and wiring layers L 1  to L 4  are provided on the surfaces of the insulating layers  11  to  14 , respectively. Although not particularly limited, the uppermost insulating layer  11  and the lowermost insulating layer  14  may each be a core layer obtained by impregnating a core material such as glass fiber with a resin material such as glass epoxy. On the other hand, the insulating layers  12  and  13  may each be made of a resin material not containing a core material such as glass cloth. Particularly, the insulating layers  11  and  14  are preferably smaller in thermal expansion coefficient than the insulating layers  12  and  13 . 
     The wiring layer L 1  has wiring patterns P 11  to P 13 , the wiring layer L 2  has wiring patterns P 21  to P 24 , the wiring layer L 3  has a wiring pattern P 34 , and the wiring layer L 4  has wiring patterns P 41  and P 44 . The wiring layer L 1  is positioned on the upper surface  10   a  side of the substrate  10  and is partly covered with a solder resist  21 . The entire surface of the wiring pattern P 11  and a part of the wiring pattern P 12  are each not covered with the solder resist  21  but with an ENEPIG coating  19 . The wiring pattern P 11  not covered with the solder resist  21  is positioned in the electronic component mounting area A. A part of the wiring pattern P 12  that is not covered with the solder resist  21  constitutes a bonding pad B. The wiring layer L 4  is positioned on the side of a back surface  10   b  of the substrate  10  and is partly covered with a solder resist  22 . A part of each of the wiring patterns P 41  and P 44  is not covered with the solder resist  22  but with the ENEPIG coating  19 . 
     The heat transfer block  40  is a chip component constituting a heat dissipation path for dissipating heat from the upper surface  10   a  side toward the back surface  10   b  side and has a surface  41  facing the upper surface  10   a  side and a surface  42  facing the back surface  10   b  side. The surfaces  41  and  42  of the heat transfer block  40  are insulated from each other. The heat transfer block  40  is not particularly limited in terms of material and structure as long as it has a sufficiently higher heat conductivity than those of the insulating layers  12  and  13 , and the surfaces  41  and  42  are insulated from each other. 
     For example, it is possible to employ a heat transfer block  40 A formed of an SOI (Silicon On Insulator) chip as illustrated in  FIG. 2  as a first example. The SOI chip has a structure in which an insulating film  45  made of silicon oxide is interposed between a silicon substrate  43  constituting the surface  41  and a silicon substrate  44  constituting the surface  42 . In this case, since the heat conductivity of the silicon is high, it is possible to increase the heat conductivity of the heat transfer block as a whole by sufficiently reducing the film thickness of the insulating film  45  while insulating the surfaces  41  and  42  from each other. 
     Alternatively, it is possible to employ a heat transfer block  40 B having a structure in which an insulating film  47  is formed on the upper surface of a main body part  46  made of metal such as copper (Cu) as illustrated in  FIG. 3  as a second example, a heat transfer block  40 C having a structure in which an insulating film  48  is formed on the lower surface of a main body part  46  made of metal such as copper (Cu) as illustrated in  FIG. 4  as a third example, and a heat transfer block  40 D having a structure in which insulating films  47  and  48  are formed respectively on the upper and lower surfaces of a main body part  46  made of metal such as copper (Cu) as illustrated in  FIG. 5  as a fourth example. In these cases, since the heat conductivity of the main body part  46  is high, it is possible to increase the heat conductivity of the heat transfer block as a whole by sufficiently reducing the film thicknesses of the insulating films  47  and  48  while insulating the surfaces  41  and  42  from each other. The insulating films  47  and  48  can be made using silicon nitride (SiN) and deposited by a sputtering method or the like. 
     Besides, it is possible to employ a heat transfer block  40 E having a structure in which addition parts  46   a  and  46   b  are added to the heat transfer block  40 D of  FIG. 5  as illustrated in  FIG. 6  as a fifth example. The addition parts  46   a  and  46   b  are provided on the surfaces of the insulating films  47  and  48 , respectively, and are each made of metal such as copper (Cu) like the main body part  46 . Providing such addition parts  46   a  and  46   b  makes the heat conductivity higher than that of the heat transfer block  40 D of  FIG. 5 . Further, it is possible to employ a heat transfer block  40 F having a structure in which the surfaces of the main body part  46  having recesses and protrusions are covered with the insulating films  47  and  48 , respectively, and the addition parts  46   a  and  46   b  are embedded in the recesses as illustrated in  FIG. 7  as a sixth example. Since the surfaces  41  and  42  of the heat transfer block  40 F of  FIG. 7  each have almost a flat shape, voids are unlikely to occur when the heat transfer block  40 F is embedded in the insulating layers  12  and  13 . In the examples of  FIGS. 6 and 7 , the addition parts  46   a  and  46   b  constitute parts of the surfaces  41  and  42 , respectively. The via conductors V 20  and V 30  illustrated in  FIG. 1  are preferably formed so as to contact the addition parts  46   a  and  46   b , respectively. 
     Further, it is possible to employ a heat transfer block  40 G having a structure in which two main body parts  46   c  and  46   d , one surface of each of which has a flat shape and the other surface of each of which has recesses and protrusions, are fitted to each other through an insulating film  45   a  as illustrated in  FIG. 8A  as a seventh example. The heat transfer block  40 G having such a structure can be fabricated by preparing the main body parts  46   c  and  46   d  illustrated in  FIG. 8B , forming the insulating film  45   a  on one or both of the recess/protrusion surfaces of the main body parts  46   c  and  46   d , and bonding the main body parts  46   c  and  46   d  such that the recesses and projections of one main body part mesh with those of the other main body part. 
     Further, it is possible to employ a heat transfer block  40 H made of a ceramic  49  as illustrated in  FIG. 9  as an eighth example. As the ceramic  49 , such a material having an insulating property and a high heat conductivity as aluminum nitride (AlN) and silicon nitride (SiN) may be used. Using such a material allows the surfaces  41  and  42  to be insulated from each other without the need to form the insulating film. 
     Referring back to  FIG. 1 , the wiring layers L 1  and L 2  are connected through a plurality of via conductors penetrating the insulating layer  11 . For example, the wiring patterns P 11  and P 21  are connected through a via conductor V 11 , the wiring patterns P 12  and P 22  are connected through a via conductor V 12 , the wiring patterns P 13  and P 23  are connected through a via conductor V 13 , and the wiring patterns P 13  and P 24  are connected through a via conductor V 14 . 
     The wiring layer L 2 , wiring layer L 3 , electronic component  30 , and heat transfer block  40  are connected to one another through a plurality of via conductors. For example, the wiring pattern P 21  and the surface  41  of the heat transfer block  40  are connected through a via conductor V 20 , the wiring pattern P 21  and the signal terminal  31  of the electronic component  30  are connected through a via conductor V 21 , the wiring pattern P 22  and the signal terminal  32  of the electronic component  30  are connected through a via conductor V 22 , the wiring pattern P 23  and the power supply terminal  33  of the electronic component  30  are connected through a via conductor V 23 , and the wiring patterns P 24  and P 34  are connected through a via conductor V 24  penetrating the insulating layers  12  and  13 . 
     The wiring layer L 4 , wiring layer L 3 , and heat transfer block  40  are connected to one another through a plurality of via conductors. For example, the wiring pattern P 41  and the surface  42  of the heat transfer block  40  are connected through a via conductor V 30 , and the wiring patterns P 44  and P 34  are connected through a via conductor V 34  penetrating the insulating layer  14 . 
       FIG. 10  is a schematic cross-sectional view for explaining the structure of a circuit module  2  using the electronic component embedded substrate  1 . 
     As illustrated in  FIG. 10 , the circuit module  2  includes the electronic component embedded substrate  1  illustrated in  FIG. 1  and an electronic component  50  mounted in the electronic component mounting area A of the electronic component embedded substrate  1 . Although not particularly limited, the electronic component  50  is, for example, a laser diode. The laser diode has large heat generation and is prohibited from connecting to the ground pattern because of its characteristics, so that it cannot dissipate its heat by connecting to the ground pattern, unlike common electronic components. Another example of the same type of electronic component includes a power supply inductor. 
     The electronic component  50  illustrated in  FIG. 10  has a two-terminal configuration including signal terminals  51  and  52 . The signal terminal  51  is formed on the back surface of the electronic component  50  and connected to the wiring pattern P 11  positioned in the electronic component mounting area A through a solder  60 . The signal terminal  51  is formed over the entire back surface of the electronic component  50 , so that heat generated by the operation of the electronic component  50  is efficiently transmitted to the wiring pattern P 11 . The signal terminal  52  is formed on the upper surface of the electronic component  50  and connected to the bonding pad B constituted by the wiring pattern P 12  through a bonding wire  61 . When a laser diode is mounted as the electronic component  50 , laser light is generated by a signal applied to the signal terminals  51  and  52 . The signal terminal  51  is connected to the signal terminal  31  of the electronic component  30  through the solder  60 , wiring pattern P 11 , via conductor V 11 , wiring pattern P 21 , and via conductor V 21 . The signal terminal  52  is connected to the signal terminal  32  of the electronic component  30  through the bonding wire  61 , wiring pattern P 12 , via conductor V 12 , wiring pattern P 22 , and via conductor V 22 . 
     Heat transmitted from the electronic component  50  to the wiring pattern P 11  is transmitted to the heat transfer block  40  through the plurality of via conductors V 11 , the wiring pattern P 21 , and the plurality of via conductors V 20 . The heat thus transmitted to the heat transfer block is then transmitted to the wiring pattern P 41  functioning as a heat dissipation pattern through the plurality of via conductors V 30 . In actual use, the wiring pattern P 41  is connected to a ground pattern G of a motherboard  3  through a solder  62 . Thus, the heat generated by the operation of the electronic component  50  is efficiently dissipated to the motherboard  3  through the heat transfer block  40 . 
     In the present embodiment, since the surfaces  41  and  42  of the heat transfer block  40  are insulated from each other, insulation between the via conductors V 20  and V 30  can be ensured even though they both contact the heat transfer block  40 . This allows the wiring patterns P 11  and P 41  to serve as a signal line and a ground pattern, respectively. In addition, in the present embodiment, the heat transfer block  40  is embedded in the same layer as the electronic component  30 , so that there is no need to increase the number of layers for the purpose of embedding the heat transfer block  40 . 
     The following describes a manufacturing method for the electronic component embedded substrate  1  according to the present embodiment. 
       FIGS. 11 to 25  are process views for explaining the manufacturing method for the electronic component embedded substrate  1  according to the present embodiment. 
     As illustrated in  FIG. 11 , a base material (work board) composed of the insulating layer  14  containing a core material such as glass fiber, a metal film L 3   a  formed on one surface of the insulating layer  14 , and a laminated structure of metal films L 4   a  and L 4   b  formed on the other surface of the insulating layer  14  is prepared and bonded to a support member  70  made of stainless steel or the like through a release layer  71 . 
     Then, as illustrated in  FIG. 12 , the metal film L 3   a  is patterned using a photolithography method to form the wiring layer L 3 . Then, as illustrated in  FIG. 13 , for example, an uncured (B stage) resin sheet is laminated by vacuum pressure bonding or the like on the surface of the insulating layer  14  so as to embed therein the wiring layer L 3  to thereby form the insulating layer  13 . 
     Subsequently, as illustrated in  FIG. 14 , the heat transfer block  40  is placed on the surface of the insulating layer  13 , and then the electronic component  30  is placed on the surface of the insulating layer  13  as illustrated in  FIG. 15 . The electronic component  30  is, for example, a bare chip semiconductor IC and is face-up mounted such that the terminal formation surface faces upward. The order of placing the heat transfer block  40  and electronic component  30  may be reversed; however, by placing the heat transfer block  40  first, contacting between the terminal formation surface of the electronic component  30  and the heat transfer block  40  can be prevented. 
     Then, as illustrated in  FIG. 16 , the insulating layer  12  and a metal film L 2   a  are formed so as to cover the electronic component  30  and heat transfer block  40 . Preferably, the insulating layer  12  is formed as follows: after application of an uncured or semi-cured thermosetting resin, the resin (when it is uncured resin) is semi-cured by heating, and then the semi-cured resin and metal film L 2   a  are pressed together by a pressing means to obtain a cured insulating layer  12 . The insulating layer  12  is preferably a resin sheet which does not contain fiber that would hinder the electronic component  30  and heat transfer block  40  from being embedded. 
     Then, as illustrated in  FIG. 17 , a part of the metal film L 2   a  is etching-removed by using a known method such as a photolithography method, and then known blasting or laser processing is applied to a predetermined position where the metal film L 2   a  is removed to form via holes  80  to  82 . The via hole  80  penetrates the insulating layers  12  and  13  and exposes the wiring layer L 3  at its bottom. The via hole  81  exposes the surface  41  of the heat transfer block  40 , and the via hole  82  exposes the signal terminals  31  and  32  and power supply terminal  33  of the electronic component  30 . 
     Then, as illustrated in  FIG. 18 , electroless plating and electrolytic plating are applied to form a metal film L 2   b  on the surface of the insulating layer  12  and to form the via conductors V 20  to V 24  inside the via holes  80  to  82 . As a result, the via conductor V 20  contacts the surface  41  of the heat transfer block  40 , the via conductors V 21  and V 22  contact the signal terminals  31  and  32  of the electronic component  30 , respectively, the via conductor V 23  contacts the power supply terminal  33  of the electronic component  30 , and the via conductor V 24  contacts the wiring layer L 3 . After that, as illustrated in  FIG. 19 , the metal film L 2   b  is patterned using a photolithography method or the like to form the wiring layer L 2 . 
     Then, as illustrated in  FIG. 20 , a sheet having the insulating layer  11  and metal films L 1   a  and L 1   b  laminated thereon is hot-pressed under vacuum so as to embed therein the wiring layer L 2 . The material and thickness of the insulating layer  11  may be the same as those of the insulating layer  14 . Then, as illustrated in  FIG. 21 , the metal film L 1   b  is peeled off at the boundary between the metal films L 1   a  and L 1   b , and the metal film L 4   b  is peeled off at the boundary between the metal films L 4   a  and L 4   b  to separate the substrate from the support member  70 . 
     Then, as illustrated in  FIG. 22 , a part of the metal film L 1   a  and a part of the metal film L 4   a  are etching-removed by using a known method such as a photolithography method, and then known blasting or laser processing is applied to predetermined positions where the metal films L 1   a  and L 4   a  are removed to form via holes  91  to  94  in the insulating layer  11  and to form via holes  95  and  96  in the insulating layer  14 . The via holes  91  to  94  penetrate the insulating layer  11  and expose the wiring patterns P 21  to P 24 , respectively, at their bottoms. The via hole  95  penetrates the insulating layers  14  and  13  and exposes the surface  42  of the heat transfer block  40  at its bottom. The via hole  96  penetrates the insulating layer  14  and exposes the wiring pattern P 34  at its bottom. 
     Then, as illustrated in  FIG. 23 , electroless plating and electrolytic plating are applied to form metal films L 1   c  and L 4   c  on the surfaces of the insulating layers  11  and  14 , respectively, and to form the via conductors V 11  to V 14 , V 30 , and V 34  inside the via holes  91  to  96 , respectively. As a result, the via conductors V 11  to V 14  contact the wiring patterns P 11  to P 14 , respectively, the via conductor V 30  contacts the surface  42  of the heat transfer block  40 , and the via conductor V 34  contacts the wiring pattern P 34 . After that, as illustrated in  FIG. 24 , the metal films L 1   c  and L 4   c  are patterned using a photolithography method or the like to form the wiring layers L 1  and L 4 . 
     Then, as illustrated in  FIG. 25 , the solder resists  21  and  22  are formed on the surfaces of the insulating layers  11  and  14 , respectively, and surface treatment for component mounting is applied to the wiring patterns P 11 , P 12 , P 41 , and P 44  which are exposed from the solder resists  21  and  22  to form the ENEPIG coating  19 , whereby the electronic component embedded substrate  1  illustrated in  FIG. 1  is completed. 
     Although the electronic component  30  and heat transfer block  40  are embedded in the same layer in the above embodiment, this is not essential in the present invention, and they may be embedded in mutually different layers. In this case, the electronic component  30  and heat transfer block  40  may partly overlap each other in a plan view as illustrated in  FIG. 26 , or the whole part of the electronic component  30  may overlap a part of the heat transfer block  40  in a plan view as illustrated in  FIG. 27 . 
     It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention. 
     For example, in the above embodiment, the signal terminal  51  of the electronic component  50  mounted on the electronic component embedded substrate  1  is positioned on the back surface side of the electronic component  50 , and the signal terminal  52  is positioned on the upper surface side; however, the electronic component to be mounted on the electronic component embedded substrate  1  may not necessarily have such a configuration, but both of the signal terminals may be positioned together on the upper surface side or lower surface side. 
     Further, the number of the heat transfer blocks to be embedded the substrate  10  is not limited to one, but a plurality of the heat transfer blocks may be embedded in the substrate  10 . 
     REFERENCE SIGNS LIST 
     
         
           1  electronic component embedded substrate 
           2  circuit module 
           3  motherboard 
           10  substrate 
           10   a  upper surface of substrate 
           10   b  back surface of substrate 
           11 - 14  insulating layer 
           19  ENEPIG coating 
           21 ,  22  solder resist 
           30  electronic component 
           31 ,  32  signal terminal 
           33  power supply terminal 
           40 ,  40 A- 40 H heat transfer block 
           41 ,  42  surface of heat transfer block 
           43 ,  44  silicon substrate 
           45 ,  45   a  insulating film 
           46 ,  46   c ,  46   d  main body part 
           46   a ,  46   b  addition part 
           47 ,  48  insulating film 
           49  ceramic 
           50  electronic component 
           51 ,  52  signal terminal 
           60 ,  62  solder 
           61  bonding wire 
           70  support member 
           71  release layer 
           80 - 82 ,  91 - 96  via hole 
         A electronic component mounting area 
         B bonding pad 
         G ground pattern 
         L 1 -L 4  wiring layer 
         L 1   a -L 1   c , L 2   a , L 2   b , L 3   a , L 4   a -L 4   c  metal film 
         P 11 -P 14 , P 21 -P 24 , P 34 , P 41 , P 44  wiring pattern 
         V 11 -V 14 , V 20 -V 24 , V 30 , V 34  via conductor