Patent Publication Number: US-10319686-B2

Title: Radiation-hard electronic device and method for protecting an electronic device from ionizing radiation

Description:
BACKGROUND 
     Technical Field 
     The present disclosure relates to a radiation-hard electronic device and to a method for protecting an electronic device from ionizing radiation. 
     Description of the Related Art 
     As is known, electronic devices may generally undergo damage of a various nature and seriousness from exposure to ionizing radiation. Damage may derive both from the total dose of radiation absorbed and from single events, and may range from a disturbance of a minor degree to a catastrophic breakdown, which causes destruction of the devices. 
     Damage deriving from the total dose of radiation absorbed presents progressively and usually may be put down to phenomena of trapping of the charge generated by interaction with the incident radiation. A typical effect is drift of the threshold voltages of MOS transistors as a result of the charge trapped in the gate insulating regions. 
     Single events are instead due to impact of high-energy particles on the semiconductor substrates in which the devices are formed. Interaction with the substrate gives rise to an intense generation of charge carriers along the paths of the high-energy particles. In turn, the charge carriers are at the origin of drift and diffusion currents that may cause phenomena equivalent to electrostatic discharge, such as triggering of parasitic components or the phenomena of junction breakdown. In some conditions, the phenomena may have intensities such as to cause permanent damage to, or even destruction of, the devices. 
     Devices designed for operating in environments exposed to ionizing radiation should evidently be provided with protection structures or arrangements that enable mitigation of the adverse effects both of accumulation of radiation doses over time and of single events. Operating conditions that require adoption of measures against damage from ionizing radiation are encountered regularly in space applications (e.g., satellites, spacecraft, space stations) or else in nuclear sites. 
     The structural, circuit, and process solutions adopted for preserving devices from radiation offer a certain degree of protection, but not always are sufficiently robust to prevent malfunctioning and breakdown, especially in critical applications. 
     It would thus be desirable to have available more effective protection systems for reducing the risk of temporary and/or permanent damage of electronic devices. 
     BRIEF SUMMARY 
     The present disclosure provides a radiation-hard electronic device and a method for protecting an electronic device from ionizing radiation that will enable some or all of the limitations described above to be overcome or at least attenuated. 
     According to embodiments of the present disclosure, a radiation-hard electronic device and a method for protecting an electronic device from ionizing radiation are provided. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       For a better understanding of the disclosure, embodiments thereof will now be described, purely by way of non-limiting example and with reference to the attached drawings, wherein: 
         FIG. 1  is a simplified cross-section through an electronic device according to an embodiment of the present disclosure; 
         FIG. 2  is a cross-section of an enlarged detail of the device of  FIG. 1 ; 
         FIG. 3  is a top plan view of the detail of  FIG. 2 ; 
         FIG. 4  is a graph that shows first quantities corresponding to the device of  FIG. 1  and to a known device; 
         FIG. 5  is a graph that shows second quantities corresponding to the device of  FIG. 1  and to a known device; and 
         FIG. 6  is a simplified block diagram of an electronic system incorporating at least one electronic device according to embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     With reference to  FIG. 1 , a radiation-hard electronic semiconductor device according to one embodiment of the present disclosure is designated as a whole by  1  and comprises a package structure  2  and a semiconductor chip  3  integrated in which are electronic components (here not illustrated). 
     The electronic semiconductor device  1  is provided with structures for protection from radiation at the level of the package structure  2  and of the semiconductor chip  3 . The package structure  2  itself is of the flat-hermetic-package type, which is particularly suited to offering protection from radiation because it has a high lead density. 
     The package structure  2  comprises a ceramic substrate  5 , a frame-like spacer structure  6 , and a cover  7 . The spacer structure  6  is arranged between the ceramic substrate  5  and the cover  7  and delimits laterally a cavity  8  housed in which is the semiconductor chip  3 . The semiconductor chip  3  is bonded to the ceramic substrate  5  by a bonding layer  9  and is coupled to external contacts  10  by wire bonds  11 . 
     The semiconductor chip  3  is coated by a protective layer  12  of gel, which incorporates also the wire bonds  11 . The protective layer  12 , which forms part of the protection structures, fills the cavity  8  at least partially, surrounding the semiconductor chip  3  on all sides, except obviously for the lower face  3   a  bonded to the ceramic substrate  5 . The portion of the protective layer  12  that coats the free face  3   b  of the semiconductor chip  3  has a thickness not greater than 700 μm. The gel that forms the protective layer  12  is a silicone gel and, in one embodiment, contains hydrogen. The cover  7  seals the cavity  8 . 
     The protective layer  12  may advantageously be deposited in low-pressure conditions (for example, at 50 mbar) to prevent formation of bubbles that might reduce the effectiveness of the protection. 
     With reference to  FIG. 2 , the semiconductor chip  3  is provided with further structures for protection from radiation and comprises a substrate  13 , of a SOI type, and electronic components  15 ,  16 , which are housed in the substrate  13  and form an integrated circuit  17 . The integrated circuit  17  may be of any type and may perform any function. In particular, the integrated circuit  17  may be an analog circuit (by way of non-limiting example, an amplifier, a filter, or a power supply), a digital circuit (by way of non-limiting example, a logic circuit or a memory), a low-voltage circuit, or a power circuit. 
     The substrate  13 , as mentioned above, is of a SOI type and comprises a first semiconductor layer  18  and a second semiconductor layer  19 , for example of a P type, separated and insulated from one another by a dielectric layer  20 . Further, the substrate  13  comprises trench-insulation structures  21  that extend from a face  19   a  of the second semiconductor layer  19  as far as the dielectric layer  20  through the entire second semiconductor layer  19 . The trench-insulation structures  21  are bonded to the dielectric layer  20  and delimit laterally respective portions or cells  19   b  of the second semiconductor layer  19 , electrically insulated from the other cells  19   b  and from the remaining portions of the second semiconductor layer  19  (see also  FIG. 3 ). The dielectric layer  20  and the trench-insulation structures  21  form a structure for protection from radiation, in particular from isolated latch-up events, as clarified hereinafter. 
     Represented by way of example in  FIG. 2  are a PMOS transistor  15  and an NMOS transistor  16  of a circuit obtained in CMOS technology, which are formed in respective cells  19   b  of the second semiconductor layer  19  and are operatively coupled to one another. 
     The PMOS transistor  15  is provided in a body well  25  of an N type and comprises a source region  15   a , a drain region  15   b , both of a P type, and a body-contact region  15   c , of an N type. A polysilicon gate region  15   d  is separated from the body well  25  by a gate-oxide region  15   e  and extends between the source region  15   a  and the drain region  15   b . The gate-oxide region  15   e  has a thickness of less than 7 nm for minimizing the accumulation of charge trapped as a result of ionizing radiation. 
     The NMOS transistor  16  comprises a source region  16   a , and a drain region  16   b , both of an N type, and a body-contact region  16   c , of a P type. A polysilicon gate region  16   d  is separated from the second semiconductor layer  19  by a gate-oxide region  16   e  and extends between the source region  16   a  and the drain region  16   b . Also the gate-oxide region  16   e  has a thickness of less than 7 nm. 
     The source region  15   a  and the body-contact region  15   c  of the PMOS transistor  15  are connected to a first power-supply line  26 , for example a positive supply line. The source region  16   a  and the body-contact region  16   c  of the NMOS transistor  15  are connected to a second power-supply line  27 , for example a negative supply line. The drain regions  15   b ,  16   b  of the PMOS transistor  15  and of the NMOS transistor  16  are connected to a common output terminal  28 . The gate regions  15   d ,  16   d  of the PMOS transistor  15  and of the NMOS transistor  16  are connected to a common input terminal  30 . 
     Represented with a dashed line in  FIG. 2  are also parasitic components, in particular a parasitic PNP transistor in the cell  19   b  of the PMOS transistor  15  and a parasitic NPN transistor in the cell  19   b  of the NMOS transistor  16 . Thanks to the insulation provided by the structure for protection from radiation defined by the dielectric layer  20  and by the trench-insulation structures  21 , any accidental triggering of the parasitic components as a result of incident ionizing radiation is prevented from being stabilized by the passage of currents through the second semiconductor layer  19 . In practice, the structure for protection from radiation defined by the dielectric layer  20  and by the trench-insulation structures  21  breaks up the parasitic thyristors typical of circuits in CMOS technology. 
     Other measures of protection from radiation integrated in the semiconductor chip  3  may regard: 
     auxiliary circuits that prevent triggering of parasitic components; 
     circuits for detection and correction of errors; 
     circuits for compensation of the thresholds; 
     redundant circuits; and 
     circuits with modular redundancy or with voting logic so that different identical circuits perform the same function, the outputs are compared, and, in the case of disagreement, the output supplied by the majority of the circuits is selected. 
     The electronic device  1  described integrates various protection structures at the level of the package structure  2  and at the level of the semiconductor chip  3  that enable mitigation of the harmful effects of ionizing radiation. 
     Use of the protective layer  12  of silicone gel, in particular, enables significant reduction of the energy of the incident particles and consequent attenuation of the effects of collisions. In particular, the protective layer  12  of silicone gel has proven effective in preventing damage deriving from single events of the so-called “snap-back” type, from which also the devices made in SOI substrates might otherwise be affected. When a high-energy particle impinges on a semiconductor substrate, the interaction with the atoms of the lattice gives rise to an intense generation of charge carrier pairs along the path of the particle itself. Part of the charge produced is removed very rapidly by a drift mechanism, in particular when the collision affects a reversely biased PN junction. The drift mechanism depends upon the modifications of the electrical field at the PN junction following upon collision of ionizing particles and gives rise to currents that tend to vanish rapidly, but reach very high intensity peaks and represent a serious risk of damage (see the current profiles illustrated in the graph of  FIG. 4 , in particular in the initial portion on the left). In a MOS transistor, for example, activation of parasitic components resulting from isolated snap-back events may cause a short circuit between the drain and source regions also in circuits obtained in SOI substrates. In this case, damage and the current intensity may depend also upon the drain-to-source voltage. In practice, the higher the drain-to-source voltage, the lower the robustness in regard to damage from ionizing radiation. Another fraction of charge gives instead rise to diffusion currents and tends to recombine. The contribution of drift current vanishes more slowly (right-hand part of the graph of  FIG. 4 ), but does not reach high values and generally represents a lower risk. 
     The use of the protective layer  12  of silicone gel enables drastic attenuation of the energy of the incident particles and reduces accordingly both generation of charge carriers pairs and the intensity of the current deriving from collision, in particular the drift current. In the graph of  FIG. 4 , the top dashed line and the solid line represent the currents induced from ionizing radiation in the absence and in the presence, respectively, of the protective layer  12  of silicone gel. 
     Tests have also shown that the capacity of penetration of ionizing radiation within the semiconductor material is markedly reduced by the presence of the protective layer  12 .  FIG. 5  shows the linear transfer of energy as a function of the depth of penetration of ionizing particles within the semiconductor. In the graph, the dashed line regards a device without protection with layers of gel, whereas the solid line regards the electronic device  1  provided with protective layer  12  of silicone gel. As emerges clearly, the energy transferred to the semiconductor is much lower in the presence of the protective layer  12 . Consequently, also the generation of charge carriers pairs and the currents caused by impact of the ionizing particles are reduced accordingly, and thus likewise the risk of damage to the device. Given the same biasing conditions, the risk of damage may thus be reduced thanks to the protective layer  12 . Conversely, the protective layer  12  enables use of devices of higher voltage classes without increasing the risk of damage, given the same exposure to ionizing radiation. 
     Advantageously, the protective layer  12  occupies a space normally left empty in conventional devices. The solution described thus enables marked improvement of the robustness of the electronic device  1  in regard to radiation, without affecting the structure and the overall dimensions. Further, the silicone gel may be deposited or dispensed easily, and the step of formation of the protective layer may be integrated in the normal process flows, in particular in the steps of packaging of the semiconductor chip  3 . Integration of the protective layer  12  of silicone gel is thus also far from costly. 
       FIG. 6  illustrates a portion of an electronic system  100  according to one embodiment of the present disclosure. The system  100  may be used in, or in combination with, devices such as sensors, actuators, computers, possibly with wireless connection capacity, a mobile or satellite communication device, a digital camera, or other devices designed to process, store, transmit, or receive information. 
     The electronic system  100  may comprise a control unit  110 , an input/output (I/O) device  120  (for example, a keyboard or a display), a wireless interface  140  and a memory  160 , of a volatile or non-volatile type, coupled together through a bus  150 . In one embodiment, a battery  180  may be used for supplying the system  100 . It should be noted that the scope of the present disclosure is not limited to embodiments having necessarily one or all of the devices listed. 
     The control unit  110 , the wireless interface  140 , and the memory  160  may be provided in distinct semiconductor chips or else some of these may be integrated in a same semiconductor chip. Further, one or more of the devices listed is incorporated in a package structure with a protective layer of silicone gel. Represented schematically by way of example in  FIG. 6  are protective layers  112 ,  142 ,  162  for the control unit  110 , the wireless interface  140 , and the memory  160 , respectively. 
     The control unit  110  may comprise, for example, one or more microprocessors, microcontrollers, and the like. Each of these may be incorporated in a package structure with a respective protective layer of silicone gel. 
     The I/O device  120  may be used for generating a message. The system  100  may use the wireless interface  140  for transmitting and receiving messages to and from a wireless communication network with a radiofrequency (RF) signal. Examples of wireless interface may comprise an antenna, a wireless transceiver, such as a dipole antenna, even though the scope of the present disclosure is not limited from this standpoint. Further, the I/O device  120  may supply a voltage representing what is stored either in the form of digital output (if digital information is stored) or in the form of analog output (if analog information is stored). 
     Finally, it is clear that modifications and variations may be made to the electronic device and to the method described, without thereby departing from the scope of the present disclosure, as defined in the annexed claims. 
     The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.