Patent Publication Number: US-2002013031-A1

Title: Method of improving the reliability of gate oxide layer

Description:
BACKGROUND OF THE INVENTION  
       [0001] 1. Field of the Invention  
       [0002] The invention relates to a method to improve the reliability of a gate oxide layer, and more particularly to a method to modify the inter-metal dielectric (IMD) stack, thereby improving the reliability of the gate oxide layer.  
       [0003] 2. Description of the Related Art  
       [0004] Referring to FIG. 1, in the fabrication of gate structure  100  of MOS, a thin gate oxide layer  104  is formed on a semiconductor substrate  102 . A layer of polysilicon is then formed on the gate oxide layer  104  for use as a gate  106 . To manufacture multilevel interconnects  108   a,    108   b,  a dielectric layer  110  is necessarily deposited over the gate  106  to serve as an insulator between the gate  106  and the interconnects  108   a,    108   b,  and the gate is electrically connected with the interconnects  108   a  by the formation of a via  112 . Since the high density plasma chemical vapor deposition (HDPCVD) is good for depositing a dielectric material with high aspect ratio metal spacing, it is generally employed to form an IMD  114  to cover the interconnects  108   a,    108   b.  However, the gate oxide layer  104  is damaged after the IMD  114  is deposited by HDPCVD. FIG. 2 illustrates the frequency of breakdown charge (Q BD ) of the gate oxide layer  104  and the IMD  114  formed by HDPCVD. As shown in FIG. 2, when the breakdown charge is lower than 1 coul/cm 2 , the frequency of the gate oxide layer  104  defect is relatively high.  
       [0005] The major reason that causes the gate oxide layer  104  to be damaged includes an antenna effect. The charged particles in the high density plasma are attracted by the gate  106  and penetrate the IMD  114  to reach to the gate  104 . A part of the charged particles even reach the gate oxide layer  104  and destroy the dense structure of the gate oxide layer  104 . As a result, this behavior causes the gate oxide layer  104  breakdown to occur.  
       [0006] In addition, the charged particles in the plasma produce strong ultra-violet rays and short wave length rays when the deposition is carried out by the HDPCVD. These rays are capable of penetrating through the surrounding dielectric material of the gate oxide layer  104  and being absorbed by the gate oxide layer  104 . The ultra-violet rays and short wave length rays with high energy activate the charged particles trapped in the gate oxide layer  104 , in the interface between the gate oxide layer  104  and the substrate  104 , and between the gate oxide layer  104  and the gate  106 , such that the excited electron-hole pair destroy the structure of the gate oxide layer  104 . Therefore, the quality of the device is decreased and the productivity is lower while the gate oxide layer  104  is damaged.  
       SUMMARY OF THE INVENTION  
       [0007] Therefore, the invention is directed towards a method of improving the reliability of the gate oxide layer. A dielectric layer is formed on a substrate at least having a gate. An interconnect is then formed on the dielectric layer. The interconnect and the dielectric layer are covered with a liner insulated layer, which is formed by low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) or plasma enhanced chemical vapor deposition (PECVD), for example. An IMD layer is formed on the liner insulated layer by HDPCVD.  
       [0008] The liner insulated layer enables the charge particles to be blocked and prevented from reaching the gate oxide layer while the IMD is carried out by HDPCVD. Accordingly, the defect of the gate oxide layer can be avoided, to thereby enhance the reliability of the gate oxide layer.  
       [0009] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0010] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,  
     [0011]FIG. 1 is schematic, cross-sectional view illustrating a semiconductor device structure with an inter-metal dielectric formed by HDPCVD as known in prior art;  
     [0012]FIG. 2 shows a frequency of breakdown charge for a gate oxide layer of a semiconductor device structure as known in prior art;  
     [0013]FIG. 3 is a schematic, cross-sectional view illustrating a semiconductor device structure in a preferred embodiment according to the invention; and  
     [0014]FIG. 4 shows a frequency of breakdown charge for a gate oxide layer of the semiconductor device structure in a preferred embodiment according to the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     [0015] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.  
     [0016] This invention includes forming a liner insulated layer on interconnects by LPCVD or APCVD prior to the formation of the IMD formed by HDPCVD. Since the liner insulated layer is not formed in a high density plasma environment, the antenna effect cannot be induced. The IMD layer with a better deposition performance can be subsequently formed in the high density plasma environment due to the fabrication of the liner insulated layer. As a result, the breakdown of the gate oxide layer is prevented by the insulation of the insulated layer.  
     [0017]FIG. 3 is a schematic, cross-sectional view of a semiconductor device structure in a preferred embodiment according to the invention. Referring to FIG. 3, a substrate  300  has isolation structures (not shown) formed thereon to define the active area. A gate oxide layer  302  is formed on the substrate  300  by thermal oxidation and a gate  304  is formed on the gate oxide layer  302 . The gate  304  is made of conductive materials, such as polysilicon or polycide. An insulated spacer  306 , such as oxide, is formed on the sidewall of the gate  304 , and a source/drain region (not shown) is formed in the substrate  300 . The gate  304  and the insulated spacer  306  are used as a gate structure  308 .  
     [0018] A dielectric layer  310  is formed on the substrate  300 . For example, chemical vapor deposition (CVD) is used to form TEOS oxide or planarized material, such as PSG or BPSG. Referring to FIG. 3 again, a via  312  is formed within the dielectric layer  310  and metal interconnects  314   a,    314   b  are formed on the dielectric layer  310 . The via  310  allows the gate  304  to be electrically connected with the metal interconnect  314   a.  The via  312  and the metal interconnects  314   a,    314   b  can be formed by damascene or another conventional process well known to those skilled in the art.  
     [0019] A liner insulated layer  316  conformal to the substrate  300  with the device structure is formed on the dielectric layer  310  and the metal interconnects  314   a,    314   b.  The liner insulated layer  316  has a thickness of about 10-10000 angstroms and can be formed by LPCVD, APCVD or PECVD to obtain an insulated material, such as oxide, nitride, borate, or a composite film formed from two of the above materials, such as nitride-borate, silicon-oxy-nitride (SiO x N y ). Since the liner insulated layer  316  is not formed in a high density plasma condition, the deposition chamber does not generate charged particles. Therefore, the gate oxide layer  302  cannot be destroyed by the charges to cause breakdown.  
     [0020] The high density plasma chemical vapor deposition (HDPCVD), for example, is utilized to formed an inter-metal dielectric layer  318  on the liner insulated layer  316  to obtain a better deposition performance. Though the IMD layer  318  is formed in a high density plasma environment, the charged particles in the plasma are screened by the liner insulated layer  316 . Therefore, the charged particles cannot reach the gate oxide layer  302  through the metal interconnects  314   a,    314   b,  via  312  and gate  306 . The breakdown of the gate oxide layer  302  is avoided, thereby improving the reliability of the gate oxide layer  302 .  
     [0021]FIG. 4 shows the frequency of a gate oxide breakdown, in which a semiconductor device structure having the gate oxide layer is formed by the foregoing process. According to this invention, the liner insulated layer  316  is formed over the substrate  300  by PECVD prior to the formation of the IMD layer  318 . When the breakdown charge is lower than 1 coul/cm 2 , the frequency of the gate oxide layer  302  breakdown is far less than that of prior art (FIG. 2) without the liner insulated layer. The fabricating process of this invention dramatically reduces the frequency of the gate oxide breakdown; thus the reliability of the gate oxide layer is improved.  
     [0022] This invention forms a liner insulated layer conformal to the structure on the substrate before HDPCVD is performed, such that the particles generated in plasma can be prevented from penetrating the gate oxide layer to cause breakdown. The reliability of the gate oxide layer is ameliorated, the yield of the devices is increased and the life of the device is prolonged.  
     [0023] Other embodiment of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.