Patent Publication Number: US-10761807-B2

Title: Floating-point number operation circuit and method

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to floating-point number operations, and, more particularly, to the multiplication operation, conventional multiplication and accumulation (mac) operations, and fused multiplication and accumulation (fused mac) operations of floating-point numbers. 
     2. Description of Related Art 
     The floating-point arithmetic operations of a processor often involve operations of addition, subtraction, multiplication, division, multiplication and accumulation (mac), and fused multiplication and accumulation (fused mac). Although the mac operation and the fused mac operation both calculate A*B+C (A, B, and C are floating-point numbers), the fused mac operation gives a relatively accurate result compared to the mac operation since two rounding operations are conducted in each mac operation (one for the multiplication operation and the other for the addition operation) whereas only one rounding operation is conducted in each fused mac operation (for the addition operation). For conventional processors, operations are often optimized separately, which can only slightly improve the overall performance of the processor. Therefore, there is a need for an optimized circuit that takes into consideration multiple operations simultaneously to simplify the circuit and improve the processor performance. 
     SUMMARY OF THE INVENTION 
     In view of the issues of the prior art, an object of the present invention is to provide a floating-point number operation circuit and its associated method, so as to simplify the circuit and improve the performance of the processor. 
     Note that “multiply”, “add”, and “accumulate” are respectively equivalent to “multiplication”, “addition”, and “accumulation”. In this disclosure, the latter group is used. 
     A floating-point number operation circuit is provided. The floating-point number operation circuit is configured to perform a fused multiplication and accumulation (fused mac) operation or a multiplication and accumulation (mac) operation on a first operand, a second operand, and a third operand, or perform a multiplication operation on the first operand and the second operand. The floating-point number operation circuit includes a multiplication circuit, a selection circuit, a control circuit, and an addition circuit. The multiplication circuit is configured to receive the first operand and the second operand and perform the multiplication operation on the first operand and the second operand to generate an unrounded product and a rounded product. The selection circuit is coupled to the multiplication circuit and configured to receive the unrounded product and the rounded product and output either the unrounded product or the rounded product. The control circuit is coupled to the selection circuit and configured to control the selection circuit to output the rounded product when the floating-point number operation circuit performs the mac operation, and control the selection circuit to output the unrounded product when the floating-point number operation circuit performs the fused mac operation. The addition circuit is coupled to the selection circuit and configured to receive the third operand and either the unrounded product or the rounded product, and add the third operand and either the unrounded product or the rounded product to obtain an operation result of the fused mac operation or the mac operation. A total number of input bits of the addition circuit is greater than twice the number of bits of the first, second or third operand. 
     A floating-point number operation method is also provided. The floating-point number operation method performs a fused mac operation or a mac operation on a first operand, a second operand, and a third operand, or performs a multiplication operation on the first operand and the second operand. The method includes steps of: using a multiplication circuit to receive the first operand and the second operand, and using the multiplication circuit to perform the multiplication operation on the first operand and the second operand to generate an unrounded product and a rounded product; using a selection circuit to receive the unrounded product and the rounded product, and outputting either the unrounded product or the rounded product; controlling the selection circuit to output the rounded product when the mac operation is performed, and controlling the selection circuit to output the unrounded product when the fused mac operation is performed; and using an addition circuit to receive the third operand and either the unrounded product or the rounded product, and using the addition circuit to perform an addition operation on the third operand and either the unrounded product or the rounded product to obtain an operation result of the fused mac operation or the mac operation. A total number of input bits of the addition circuit is greater than twice the number of bits of the first, second or third operand. 
     The floating-point number operation circuit and its associated method of the present invention integrate the multiplication operation, the multiplication and accumulation (mac) operation, and the fused multiplication and accumulation (fused mac) operation for floating-point numbers. These three operations are optimized at the same time for the floating-point number operation circuit and the method thereof disclosed in the present invention. Therefore, this invention has better processor performance and a simpler circuit in comparison with the conventional technology. 
     These and other objectives of the present invention no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments with reference to the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a circuit diagram of a computing section of a floating-point number operation circuit according to the present invention. 
         FIG. 2  illustrates a flowchart of a computing section of a floating-point number operation method according to the present invention. 
         FIG. 3  illustrates a circuit diagram of a detection section of a floating-point number operation circuit according to an embodiment of the present invention. 
         FIG. 4  illustrates a flowchart of a detection section of a floating-point number operation method according to an embodiment of the present invention. 
         FIG. 5  illustrates a circuit diagram of a detection section of a floating-point number operation circuit according to another embodiment of the present invention. 
         FIG. 6  illustrates a flowchart of a detection section of a floating-point number operation method according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The following description is written by referring to terms of this technical field. If any term is defined in this specification, such term should be explained accordingly. In addition, the connection between objects or events in the below-described embodiments can be direct or indirect provided that these embodiments are practicable under such connection. Said “indirect” means that an intermediate object or a physical space exists between the objects, or an intermediate event or a time interval exists between the events. 
     The disclosure herein includes a floating-point number operation circuit and its associated method. On account of that some or all elements of the floating-point number operation circuit could be known, the detail of such elements is omitted provided that such detail has little to do with the features of this disclosure and this omission nowhere dissatisfies the specification and enablement requirements. In addition, some or all of the processes of the floating-point number operation method can be performed by the floating-point number operation circuit or its equivalent. A person having ordinary skill in the art can choose components or steps equivalent to those described in this specification to carry out the present invention, which means that the scope of this invention is not limited to the embodiments in the specification. 
       FIG. 1  is a circuit diagram of a computing section of a floating-point number operation circuit according to the present invention. In the figure, double precision (with one bit representing the sign, 11 bits representing the biased exponent, and 52 bits representing the trailing significand) is used as an example, but the present invention may also be applied to other precisions defined by IEEE 754-2008. The computing architecture  100  of the floating-point number operation circuit is configured to perform general computations of floating-point numbers (including multiplication operations, multiplication and accumulation (mac) operations, and fused multiplication and accumulation (fused mac) operations) and includes a multiplication circuit  110 , a rounding circuit  112 , a selection circuit  120 , an addition circuit  130 , a rounding circuit  132 , and a control circuit  140 . The computing architecture  100  of the floating-point number operation circuit optimizes these three operations simultaneously by repeating the use of or sharing the multiplication circuit  110  and the addition circuit  130  to improve circuit performance and reduce circuit area. 
       FIG. 2  is a flowchart of a computing section of a floating-point number operation method according to the present invention. This flowchart corresponds to the circuit diagram of  FIG. 1  First, the multiplication circuit  110  receives the operands A and B in stage  1  (step S 210 ) and then multiplies the operands A and B to thereby generate a product D and a product D_r (step S 220 ). The product D is the result which is not trimmed (normalized, or rounded/truncated), while the product D_r is the trimmed (normalized, or rounded/truncated) counterpart of the product D by the rounding circuit  112 . The number of bits of the product D_r is the same as that of the operands A and B. The rounding circuit  112  performs rounding according to a preset rounding mode, such as round-to-nearest, round-toward-positive, round-toward-negative or round-toward-zero. The rounding circuit  112  may be incorporated in multiplication circuit  110 , or the multiplication circuit  110  and the rounding circuit  112  may be separate circuits. 
     The operation result R_no 1 =D_r of the multiplication operation of the computing architecture  100  is outputted in stage  1  (step S 230 ). The product D and the product D_r are inputted to the selection circuit  120  in stage  2  (step S 235 ). Next, the control circuit  140  determines whether the mac operation or the fused mac operation is performed on the operands A, B, and C by the computing architecture  100  of the floating-point number operation circuit (step S 240 ) and correspondingly controls the selection circuit  120  to output the product D or the product D_r. When the mac operation is performed, the control circuit  140  controls the selection circuit  120  to output the product D_r, and the addition circuit  130  accordingly adds the operand C and the product D_r in stage  2  (step S 250 ). When the fused mac operation is performed, the control circuit  140  controls the selection circuit  120  to output the product D, and the addition circuit  130  accordingly adds the operand C and the product D in stage  2  (step S 260 ). Note that the addition circuit  130  may receive the operand C in stage  1  or stage  2 . Finally, the rounding circuit  132  rounds the sum outputted by the addition circuit  130  (step S 270 ) to thereby generate an operation result R_no 2 . More specifically, according to the selection of the selection circuit  120 , the rounding circuit  132  rounds the result of C+D or the result of C+D_r. The number of bits of the operation result R_no 2  is the same as that of the operands A, B, and C. The computing architecture  100  of the floating-point number operation circuit outputs the operation result R_no 2  as the outcome of the mac operation or the fused mac operation (step S 280 ). The rounding circuit  132  may be incorporated in the addition circuit  130 , or the addition circuit  130  and the rounding circuit  132  may be separate circuits. Stage  2  follows stage  1 . 
     The computing architecture  100  of the floating-point number operation circuit operates according to a working clock. More specifically, the multiplication circuit  110 , the rounding circuit  112 , the selection circuit  120 , the addition circuit  130 , the rounding circuit  132 , and the control circuit  140  operate according to the working clock. The multiplication circuit  110  is a pipelined circuit and takes at least one cycle of the working clock; that is, from the reception of the operands A, B to the generation of the operation result R_no 1 , the multiplication circuit  110  needs at least one cycle of the working clock. Similarly, the addition circuit  130  is a pipelined circuit and takes at least one cycle of the working clock; that is, from the reception of the operand C and the product (D or D_r) to the generation of the operation result R_no 2 , the addition circuit  130  needs at least one cycle of the working clock. 
     As shown in  FIG. 1 , the multiplication circuit  110  is responsible for not only the multiplication operation (A*B) but also the multiplication part of the mac operation (A*B+C) and the fused mac operation (A*B+C). Furthermore, since the addition circuit  130  is responsible for the addition part of the mac operation and the fused mac operation, the addition circuit  130  assigns a general number of bits (depending on the designed precision of the computing architecture  100  of the floating-point number operation circuit) to one of the operands (operand C) and assigns the unrounded number of bits to the other operand (D or D_r). Taking double precision as an example, the total number of input bits of the addition circuit  130  is 64 bits+119 bits, in which 1, 12 and 106 bit(s) of the 119 bits represent(s) the sign, the biased exponent, and the trailing significand, respectively. As a comparison, the total number of input bits of an addition circuit applied exclusively to a mac operation (i.e., the addition circuit is not shared by a fused mac operation) is 64 bits+64 bits. 
       FIG. 3  is a circuit diagram of a detection section of a floating-point number operation circuit according to an embodiment of the present invention. The detection architecture  300  of the floating-point number operation circuit is configured to detect special values in a floating-point number operation and includes the detection circuit  310 , the detection circuit  320 , the detection circuit  330 , the union circuit  340 , the selection circuit  350 , and the control circuit  360 . The control circuit  360  may share circuits with the control circuit  140  of  FIG. 1 , or the control circuit  360  and the control circuit  140  may be implemented with separate circuits. The detection architecture  300  of the floating-point number operation circuit is configured to detect whether the operands A, B, and C are special values. When part or all of the operands A, B, and C are special values, the operation results of the multiplication operation, the mac operation, and the fused mac operation may be generated by the detection architecture  300  of the floating-point number operation circuit, and these operations do not require the computing architecture  100  of the floating-point number operation circuit to operate or compute. Special values include ±0, ±∞, not a number (NaN), subnormal, and so on. For example, the results of the following operations can be determined by the detection architecture  300  of the floating-point number operation circuit and do not require the computing architecture  100  of the floating-point number operation circuit to operate or compute:
 
±∞*0=NaN  (1)
 
±∞* F 1=±∞  (2)
 
±0 *F 1=±0  (3)
 
±0 +F 1= F 1  (4)
 
 F 1* F 2+NaN=NaN  (5)
 
Where F1 and F2 are normal floating-point numbers (i.e., F1 and F2 are not special values) or are subnormal. Examples (1) to (5) are for the purpose of explanation, not for limiting the scope of the present invention.
 
     The detection circuit  310  corresponds to the multiplication operation, the detection circuit  320  corresponds to the fused mac operation, and the detection circuit  330  corresponds to the addition operation. The detection circuit  310 , the detection circuit  320 , and the detection circuit  330  further correspondingly output the status flag of their respective operations. According to the definition of IEEE 754-2008, the status flags include (1) invalid operation, (2) divided by zero, (3) overflow, (4) underflow, and (5) inexact. In addition to these five types, the status flags may also include user-defined flags. 
       FIG. 4  is a flowchart of a detection section of a floating-point number operation method according to an embodiment of the present invention. This flowchart corresponds to the circuit diagram of  FIG. 3 . The detection architecture  300  of the floating-point number operation circuit receives in stage  1  the operands A and B (received by the detection circuit  310 ) or the operands A, B, and C (received by the detection circuit  320 ) (step S 410 ). The detection circuit  310  generates in stage  1  a detection result R_sp 1  and a flag flag 1  according to the operands A and B (step S 420 ). The detection result R_sp 1  and the flag flag 1  correspond to the multiplication operation. The detection result R_sp 1  is, for example, one of the special values mentioned above. More specifically, if at least one of the operands A and B is a special value, the multiplication operation becomes an invalid operation or does not require any operation or computation. In this case, the multiplication operation does not require the multiplication circuit  110  to operate or compute; instead, the operation result of the multiplication operation is generated by the detection circuit  310  in stage  1 . 
     The detection circuit  320  generates in stage  1  a detection result R_sp 2  and a flag flag 2  according to the operands A, B, and C (step S 430 ). The detection result R_sp 2  and the flag flag 2  correspond to the fused mac operation. The detection result R_sp 2  is, for example, one of the special values mentioned above. More specifically if at least one of the operands A, B, and C is a special value, the fused mac operation may become an invalid operation or does not require any operation. In this case, the fused mac operation does not require the multiplication circuit  110  and the addition circuit  130  to operate or compute; instead, the operation result of the fused mac operation is generated by the detection circuit  320  in stage  1 . 
     The detection circuit  330  generates in stage  2  a detection result R_sp 3  and an intermediate flag flag′ according to the detection result R_sp 1  and the operand C (step S 440 ). The union circuit  340  generates the flag flag 3  according to the flag flag 1  and the intermediate flag flag (step S 450 ). More specifically, the union circuit  340  performs bitwise OR operation on the flag flag 1  and the intermediate flag flag to generate the flag flag 3 . The detection result R_sp 3  and the flag flag 3  correspond to the mac operation. 
     In stage  2 , the selection circuit  350  receives the detection result R_sp 2  and the flag flag 2  from the detection circuit  320 , receives the detection result R_sp 3  from the detection circuit  330 , and receives the flag flag 3  from the union circuit  340  (step S 455 ). Next, the control circuit  360  determines whether the mac operation or the fused mac operation is performed on the operands A, B, and C by the detection architecture  300  of the floating-point number operation circuit (step S 460 ), and controls the selection circuit  350  to output (R_sp 2 , flag 2 ) or (R_sp 3 , flag 3 ) as the final detection result R_sp 4  and the final flag flag 4 . When the mac operation is performed, the control circuit  360  controls the selection circuit  350  to output the detection result R_sp 3  and the flag flag 3  in stage  2  (step S 470 ). When the fused mac operation is performed, the control circuit  360  controls the selection circuit  350  to output the detection result R_sp 2  and the flag flag 2  in stage  2  (step S 480 ). 
       FIG. 5  is a circuit diagram of a detection section of a floating-point number operation circuit according to another embodiment of the present invention. The detection architecture  500  of the floating-point number operation circuit is configured to detect special values in a floating-point number operation and includes the detection circuit  510 , the detection circuit  520 , the detection circuit  530 , the union circuit  540 , the selection circuit  550 , and the control circuit  560 . The control circuit  560  may share circuits with the control circuit  140  of  FIG. 1 , or the control circuit  560  and the control circuit  140  may be implemented with separate circuits. The detection architecture  500  of the floating-point number operation circuit is configured to detect whether the operands A, B, and C are special values. When part or all of the operands A, B, and C are special values, the operation results of the multiplication operation, the mac operation, and the fused mac operation may be generated by the detection architecture  500  of the floating-point number operation circuit, and these operations do not require the computing architecture  100  of the floating-point number operation circuit to operate or compute. The detection circuit  510  corresponds to the multiplication operation, the detection circuit  520  corresponds to the fused mac operation, and the detection circuit  530  corresponds to the addition operation. The detection circuit  510 , the detection circuit  520 , and the detection circuit  530  further correspondingly output the status flag of their respective operations. 
       FIG. 6  is a flowchart of a detection section of a floating-point number operation method according to another embodiment of the present invention. This flowchart corresponds to the circuit diagram of  FIG. 5 . The detection architecture  500  of the floating-point number operation circuit receives in stage  1  the operands A and B (received by the detection circuit  510 ) or the operands A, B, and C (received by the detection circuit  520 ) (step S 610 ). The detection circuit  510  generates in stage  1  a detection result R_sp 1  and a flag flag 1  according to the operands A and B (step S 620 ). The detection result R_sp 1  and the flag flag 1  correspond to the multiplication operation. The detection result R_sp 1  is, for example, one of the special values mentioned above. More specifically, if at least one of the operands A and B is a special value, the multiplication operation becomes an invalid operation or does not require any operation. In this case, the multiplication operation does not require the multiplication circuit  110  to operate or compute; instead, the operation result of the multiplication operation is generated by the detection circuit  510  in stage  1 . 
     The detection circuit  520  generates in stage  1  a detection result R_sp 2  and a flag flag 2  according to the operands A, B, and C (step S 630 ). The detection result R_sp 2  and the flag flag 2  correspond to the fused mac operation. The detection result R_sp 2  is, for example, one of the special values mentioned above. More specifically, if at least one of the operands A, B, and C is a special value, the fused mac operation may become an invalid operation or does not require any operation. In this case, the fused mac operation does not require the multiplication circuit  110  and the addition circuit  130  to operate or compute; instead, the operation result of the fused mac operation is generated in stage  1  by the detection circuit  520 . 
     In stage  1 , the selection circuit  550  receives the detection result R_sp 1  and the flag flag 1  from the detection circuit  510  and receives the detection result R_sp 2  and the flag flag 2  from the detection circuit  520  (step S 635 ). Next, the control circuit  560  determines whether the multiplication operation or the fused mac operation is performed on the operands A, B, and C by the detection architecture  500  of the floating-point number operation circuit (step S 640 ), and controls the selection circuit  550  to output (R_sp 1 , flag 1 ) or (R_sp 2 , flag 2 ) as the detection result R_sp 4  of stage  1  and the flag flag 4  of stage  1 . When the multiplication operation is performed, the control circuit  560  controls the selection circuit  550  to output the detection result R_sp 1  and the flag flag 1  in stage  1  (step S 650 ). When the fused mac operation is performed, the control circuit  560  controls the selection circuit  550  to output the detection result R_sp 2  and the flag flag 2  in stage  1  (step S 660 ). 
     The detection circuit  530  generates a detection result R_sp 3  and an intermediate flag flag′ in stage  2  according to the detection result R_sp 1  and the operand C (step S 670 ). The union circuit  540  generates the flag flag 3  according to the flag flag 1  and the intermediate flag flag′ (step S 680 ). More specifically, the union circuit  540  performs bitwise OR operation on the flag flag 1  and the intermediate flag flag′ to generate the flag flag 3 . The detection result R_sp 3  and the flag flag 3  correspond to the mac operation and are outputted in stage  2  (step S 690 ). 
     The detection circuits  310 - 330  and the detection circuits  510 - 530  can be implemented with logic circuits. Details as to how these detection circuits generate the detection results and flags according to the input values are well-known to those skilled in the art and are thus omitted for brevity. 
     The computing architecture  100  of the floating-point number operation circuit of  FIG. 1  may be combined with the detection architecture  300  of  FIG. 3  or the detection architecture  500  of  FIG. 5  to form the floating-point number operation circuit of the present invention. In the embodiment in which  FIG. 1  and  FIG. 3  are combined, the result of the multiplication operation (the result R_no 1  for general calculations or the detection result R_sp 1  for special values) is outputted in stage  1 , and the result of the mac operation or the fused mac operation (the result R_no 2  for general calculations or the detection result R_sp 4  for special values) is outputted in stage  2 . In the embodiment in which  FIG. 1  and  FIG. 5  are combined, the result of the multiplication operation (the result R_no 1  for general calculations or the detection result R_sp 1  for special values) and the detection result R_sp 2  of the fused mac operation for special values are outputted in stage  1 , and the result R_no 2  of the fused mac operation or the mac operation for general calculations and the detection result R_sp 3  of the mac operation for special values are outputted in stage  2 . Therefore, compared with the embodiment of the combination of  FIG. 1  and  FIG. 3 , in the embodiment of the combination of  FIG. 1  and  FIG. 5 , there is a chance to obtain the outcome of the fused mac operation earlier (in stage  1  instead of stage  2 ). 
     The foregoing control circuits  140 ,  360 , and  560  are respectively in electrical connection with other circuits in  FIGS. 1, 3, and 5  (for brevity, these connections are not shown) to control the scheduling of various operations and the use of resources on each calculation path. The control circuits  140 ,  360 , and  560  can be implemented, for example but not limited thereto, with finite-state machines (FSM). 
     In the computing architecture  100  of the floating-point number operation circuit, the control circuit  140  may (1) respond to multiplication instructions to control the multiplication circuit  110  to perform operations (corresponding steps S 210  to S 230 ); (2) respond to the mac operation instructions to control the multiplication circuit  110  and the addition circuit  130  to perform operations and control the selection circuit  120  to select the product D_r rather than the product D (corresponding to steps S 210 -S 250 , S 270 -S 280 ); and (3) respond to the fused mac operation instructions to control the multiplication circuit  110  and the addition circuit  130  to perform operations and control the selection circuit  120  to select the product D rather than the product D_r (corresponding to steps S 210 -S 240 , S 260 -S 280 ). 
     In the detection architecture  300  of the floating-point number operation circuit, the control circuit  360  may (1) respond to the multiplication instructions to control the detection circuit  310  to perform detection (corresponding to steps S 410  to S 420 ); (2) respond to the fused mac operation instructions to control the detection circuit  320  to perform detection (corresponding to steps S 410 , S 430 ) and to control the selection circuit  350  to select (R_sp 2 , flag 2 ) (corresponding to steps S 460 , S 480 ); and (3) respond to the mac operation instructions to control the detection circuit  310  and the detection circuit  330  to perform detection (corresponding to steps S 410  to S 420 , S 440  to S 450 ) and to control the selection circuit  350  to select (R_sp 3 , flag 3 ) (corresponding to steps S 460  to S 470 ). 
     In the detection architecture  500  of the floating-point number operation circuit, the control circuit  560  may (1) respond to the multiplication instructions to control the detection circuit  510  to perform detection (corresponding to steps S 610  to S 620 ) and to control the selection circuit  550  to select (R_sp 1 , flag 1 ) (corresponding to steps S 640  to S 650 ); (2) respond to the fused mac operation instructions to control the detection circuit  520  to perform detection (corresponding to steps S 610 , S 630 ) and to control the selection circuit  550  to select (R_sp 2 , flag 2 ) (corresponding to steps S 640 , S 660 ); and (3) respond to the mac operation instructions to control the detection circuit  510  and the detection circuit  530  to perform detection (corresponding to steps S 610  to S 620 , S 670  to S 690 ). 
     The present invention provides two embodiments of a floating-point number operation circuit: (1) the combination of  FIG. 1  and  FIG. 3  (corresponding to the flows of  FIG. 2  and  FIG. 4 ); and (2) the combination of  FIG. 1  and  FIG. 5  (corresponding to the flows of  FIG. 2  and  FIG. 6 ). Both embodiments integrate the multiplication operation, the mac operation, and the fused mac operation and optimize the three operations at the same time. Therefore, the floating-point number operation circuit of the present invention can improve the processor performance in terms of the processing of these three operations and simplify the circuit. It should be noted that the computing architecture  100  of the floating-point number operation circuit of the present invention can operate independently to complete the general calculations of the floating-point numbers, or work with other detection architectures to complete both the general calculations of the floating-point numbers and the detections of special values in the operations of floating-point numbers. Similarly, the detection architectures  300  and  500  of the floating-point number operation circuit can also operate independently or work with other computing architectures. 
     Since a person having ordinary skill in the art can appreciate the implementation detail and the modification thereto of the present method invention through the disclosure of the device invention, repeated and redundant description is thus omitted. Please note that there is no step sequence limitation for the method inventions as long as the execution of each step is applicable. Furthermore, the shape, size, and ratio of any element and the step sequence of any flowchart in the disclosed figures are exemplary for understanding, not for limiting the scope of this invention. Moreover, in the foregoing embodiments, double precision is used for the purpose of explanation, not for limiting the scope of this invention, and a person having ordinary skill in the art can apply this invention to other precisions based on the disclosure of this invention. 
     The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of the present invention are all consequently viewed as being embraced by the scope of the present invention.