Patent Publication Number: US-8536645-B2

Title: Trench MOSFET and method for fabricating same

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is generally in the field of transistors. More specifically, the present invention is in the field of trench-based field-effect transistors. 
     2. Background Art 
     Power semiconductor devices, such as trench field-effect transistors (trench FETs), are widely used in a variety of electronic devices and systems. Examples of such electronic devices and systems are power converters, such as DC to DC converters, in which vertically conducting trench type silicon FETs, for instance, may be implemented as power switches. In power converters, power losses within the power switches, as well as factors affecting switching speed, are becoming increasingly important. For example, for optimal performance, it is desirable to reduce overall gate charge Q g , gate resistance R g , and ON-resistance R dson  the power switches. 
     However, designing trench FETs to optimize performance for particular applications often involves tradeoffs, where improving one performance parameter degrades another. For example, reducing trench dimensions in a substrate can improve gate charge Q g  and ON-resistance R dson  at the expense of increased gate resistance R g . More particularly, reducing trench dimensions can also reduce the effective conductive area of a gate electrode in the trench, thereby increasing gate resistance R g . Thus, conventional trench FETs can be limited by trench dimensions in order to achieve acceptable overall performance. As such, it would be desirable to provide trench FETs which can have relatively improved gate resistance R g , while achieving other performance parameters. 
     Thus, there is a need for trench FETs that can overcome the drawbacks and deficiencies in the art and a method for fabricating the same. 
     SUMMARY OF THE INVENTION 
     A trench MOSFET and method for fabricating same, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a flowchart illustrating the steps taken to implement an embodiment of the present invention. 
         FIG. 2A  illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an initial step in the flowchart in  FIG. 1 . 
         FIG. 2B  illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart in  FIG. 1 . 
         FIG. 2C  illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart in  FIG. 1 . 
         FIG. 2D  illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart in  FIG. 1 . 
         FIG. 2E  illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart in  FIG. 1 . 
         FIG. 2F  illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to a final step in the flowchart in  FIG. 1 . 
         FIG. 2G  is a cross-sectional view showing trench field-effect transistors fabricated according to one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is directed to a trench MOSFET and method for fabricating the same. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order to not obscure the invention. The specific details not described in the present application are within the knowledge of a person of ordinary skill in the art. 
     The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the invention, which use the principles of the present invention, are not specifically described in the present application and are not specifically illustrated by the present drawings. 
       FIG. 1  shows a flow chart illustrating a method according to an embodiment of the present invention. Certain details and features have been left out of flowchart  100  that are apparent to a person of ordinary skill in the art. For example, a step may consist of one or more substeps or may involve specialized equipment or materials, as known in the art. Steps  170  through  180  indicated in flowchart  100  are sufficient to describe one embodiment of the present invention; however, other embodiments of the invention may utilize steps different from those shown in flowchart  100 . While steps  170  through  180  will be described with respect to fabricating an N channel device, it will be appreciated that the present invention is also applicable to P channel devices. It is noted that the processing steps shown in flowchart  100  are performed on a portion of processed wafer, which, prior to step  170 , includes, among other things, a substrate, such as a silicon substrate and a TEOS layer formed over the substrate. The wafer may also be referred to simply as a wafer or a semiconductor die or simply a die in the present application. 
     Moreover, structures  270  through  280  in  FIGS. 2A through 2F  illustrate the result of performing steps  170  through  180  of flowchart  100 , respectively. For example, structure  270  shows a semiconductor structure after processing step  170 , structure  272  shows structure  270  after the processing of step  172 , structure  274  shows structure  272  after the processing of step  174 , and so forth. 
     Referring now to  FIG. 2A , structure  270  of  FIG. 2A  shows a structure including a substrate, after completion of step  170  of flowchart  100  in  FIG. 1 . Structure  270  includes substrate  202 , which can be, for example, an N type silicon substrate, and TEOS material  204   a ,  204   b , and  204   c  formed over substrate  202 . 
     As shown in  FIG. 2A , structure  270  further includes trenches  206   a  and  206   b  and respective openings  208   a  and  208   b  formed over trenches  206   a  and  206   b . In structure  270 , opening  208   a  is formed between TEOS material  204   a  and  204   b  and opening  208   b  is formed between TEOS material  204   b  and  204   c . Trenches  206   a  and  206   b  and openings  208   a  and  208   b  can be formed, for example, by depositing a TEOS layer over a substrate. Photoresist can be deposited and patterned over the TEOS layer and openings can be formed in the TEOS layer (not shown in  FIG. 2A ). Thus, the TEOS layer can be used as a hard mask to form trenches  206   a  and  206   b  in substrate  202 . 
     According to one embodiment, thermal oxide layers are grown in each trench  206   a  and  206   b . Subsequently, a wet etch can be performed to remove the thermal oxide layers and to laterally extend the openings in the TEOS layer to widths  210   a  and  210   b , thereby forming respective openings  208   a  and  208   b , which are notably wider than respective trenches  206   a  and  206   b . More particularly, because the etch rate of the thermal oxide layers is lower than the etch rate of the TEOS layer, the openings in the TEOS layer will etch at a faster rate than the thermal oxide layers during the wet etch. The wet etch can include an over etch, which can further extend the openings in the TEOS layer. Thus, gate dielectrics  212   a  and  212   b  can be formed in respective trenches  206   a  and  206   b , each including respective portions  214   a  and  214   b  extending laterally in respective openings  208   a  and  208   b  over substrate  202 . Gate dielectrics  212   a  and  212   b  can comprise, for example, silicon oxide (SiO2) formed by thermal oxidation. The result of step  170  of flowchart  100  is illustrated by structure  270  in  FIG. 2A . 
     Referring to step  172  in  FIG. 1  and structure  272  in  FIG. 2B , at step  172  of flowchart  100 , gate electrodes  216   a  and  216   b  are formed in respective trenches  206   a  and  206   b  and openings  208   a  and  208   b . In structure  272 , gate electrode  216   a  includes lower portion  216   a   1  formed in substrate  202  and proud portion  216   a   2  formed in opening  208   a . Similarly, gate electrode  216   b  includes lower portion  216   b   1  formed in substrate  202  and proud portion  216   b   2  formed in opening  208   b . Thus, proud portions  216   a   2  and  216   b   2  have respective widths  211   a  and  211   b , which are greater than the widths of respective trenches  206   a  and  206   b.    
     Gate electrodes  216   a  and  216   b  can be formed, for example, by depositing electrode material, such as, polysilicon into trenches  206   a  and  206   b  and openings  208   a  and  208   b , and etching back the deposited polysilicon. In a specific example, the polysilicon can be etched back such that proud portions  216   a   2  and  216   b   2  each have a thickness greater than approximately 3000 Angstroms. The polysilicon can be highly doped and in some embodiments can be doped in-situ while in other embodiments it can be doped after being deposited. For example, for an N channel transistor, the polysilicon can be N++ in-situ doped polysilicon. The result of step  172  of flowchart  100  is illustrated by structure  272  in  FIG. 2B . 
     Referring now to step  174  in  FIG. 1  and structure  274  in  FIG. 2C , at step  174  of flowchart  100 , TEOS material  204   a ,  204   b , and  204   c  is removed using, for example, a TEOS etch-back. Notably, in removing TEOS material  204   a ,  204   b , and  204   c , gate dielectrics  212   a  and  212   b  are substantially maintained. More particularly, because proud portions  216   a   2  and  216   b   2  have respective widths  211   a  and  211   b , which are greater than the uppermost width of respective trenches  206   a  and  206   b , proud portions  216   a   2  and  216   b   2  can protect respective gate dielectrics  212   a  and  212   b  during removal of TEOS material  204   a ,  204   b , and  204   c . In one particular example, the uppermost width of trenches  206   a  and  206   b  can be approximately 0.2 to 0.3 microns and widths  211   a  and  211   b  of respective proud portions  216   a   2  and  216   b   2  can be approximately 0.3-0.4 microns. 
     As shown in  FIG. 2C , channel regions  218  and source regions  220  are formed in structure  274 . Channel regions  218  and source regions  220  can be formed, for example, by dopant implantation into substrate  202 . For an N channel transistor, channel regions  218  can comprise P type regions and source regions  220  can comprise highly doped N type regions. Channel regions  218  are shown formed adjacent respective trenches  206   a  and  206   b  and below respective source regions  220 . It is noted that, in the present example, widths  211   a  and  211   b  of respective proud portions  216   a   2  and  216   b   2  can be selected such that source regions  220  can substantially form under portions  214   a  and  214   b  of respective gate dielectrics  212   a  and  212   b  using dopant implantation. 
     Furthermore, in the present example, because channel regions  218  and source regions  220  are formed after trenches  206   a  and  206   b , gate dielectrics  212   a  and  212   b , and gate electrodes  216   a  and  216   b , channel regions  218  and source regions  220  are not exposed to related process temperatures in forming those features and thus can be formed using more controlled temperatures if desired. However, it is reiterated that other embodiments of the invention may utilize steps different from those shown in flowchart  100 . The result of step  174  of flowchart  100  is illustrated by structure  274  in  FIG. 2C . 
     Now referring to step  176  in  FIG. 1  and structure  274  in  FIG. 2D , at step  176  of flowchart  100 , spacer material  222  is formed over substrate  202 . For example, spacer material  222  can be formed by conformally depositing silicon oxide (SiO2) over substrate  202 . The result of step  176  of flowchart  100  is illustrated by structure  276  in  FIG. 2D . 
     Referring to step  178  in  FIG. 1  and structure  278  in  FIG. 2E , at step  278  of flowchart  100 , spacer material  222  is etched-back to form spacers  222   a  and  222   b  and to expose gate electrodes  216   a  and  216   b  and source regions  220 . As shown in  FIG. 2E , proud portions  216   a   2  and  216   b   2  of gate electrodes  216   a  and  216   b  are exposed. Also shown in  FIG. 2E , spacers  222   a  are formed adjacent respective sidewalls of proud portion  216   a   2  and spacers  222   b  are formed adjacent respective sidewalls of proud portion  216   b   2 . 
     Also in step  178 , source regions  220  are etched to form source regions  220   a  and  220   b  and to expose channel regions  218 , which, in the present example, can be accomplished using a self-aligned process with spacers  222   a  and  222   b . As shown in  FIG. 2E , source regions  220   a  are adjacent respective sidewalls of trench  206   a  and source regions  220   b  are adjacent respective sidewalls of trench  206   b . Source regions  220   a  and  220   b  are further shown situated below respective proud portions  216   a   2  and  216   b   2  of gate electrodes  216   a  and  216   b  and above respective channel regions  218 . 
     Also in step  278 , contact regions  224   a ,  224   b , and  224   c  can be formed over respective channel regions  218 . In one embodiment contact regions  224   a ,  224   b , and  224   c  can comprise highly doped P type regions formed, for example, using dopant implantation into channel regions  218 . The result of step  178  of flowchart  100  is illustrated by structure  278  in  FIG. 2E . 
     Referring to step  180  in  FIG. 1  and structure  280  in  FIG. 2F , at step  180  of flowchart  100 , silicide gate contacts  228   a  and  228   b  are formed over respective gate electrodes  216   a  and  216   b  and silicide source contacts  226   a ,  226   b , and  226   c  are formed over respective channel regions  218 . Silicide source contacts  226   a ,  226   b , and  226   c  and silicide gate contacts  228   a  and  228   b  can be formed, for example, by depositing a metal over substrate  202 , annealing the metal, and removing unreacted material. In one embodiment, for example, the metal can comprise titanium and silicide source contacts  226   a ,  226   b , and  226   c  and silicide gate contacts  228   a  and  228   b  can comprise titanium silicide, however, other metals can be used to form other silicides. 
     In the embodiment shown in  FIG. 2F , silicide source contacts  226   a ,  226   b , and  226   c  extend laterally on respective contact regions  224   a ,  224   b , and  224   c . Also shown in  FIG. 2F , silicide source contact  226   a  extends vertically on a sidewall of source region  220   a , silicide source contact  226   b  extends vertically on a respective sidewall of source regions  220   a  and  220   b , and silicide source contact  226   c  extends vertically on a sidewall of source region  220   c.    
     Also in structure  280 , silicide gate contact  228   a  is formed on proud portion  216   a   2  of gate electrode  216   a  and silicide gate contact  228   b  is formed on proud portion  216   b   2  of gate electrode  216   b . The result of step  180  of flowchart  100  is illustrated by structure  280  in  FIG. 2F . 
     Additional steps can be performed on structure  280  to form structure  290  including trench FETs  240   a  and  240   b  as shown in  FIG. 2G . In some embodiments a dielectric layer comprising, for example, SiO2, can be conformally deposited over structure  280  and a photomask can be used to etch the dielectric layer to form dielectric caps  230   a  and  230   b . In  FIG. 2G  dielectric caps  230   a  and  230   b  are formed over respective proud portions  216   a   2  and  216   b   2  of gate electrodes  216   a  and  216   b . Subsequently, source metal  232  can be deposited over substrate  202 , where dielectric caps  230   a  and  230   b  insulate respective gate electrodes  216   a  and  216   b  from source metal  232 . 
     As shown in  FIG. 2G , source metal  232  contacts source regions  220   a  and  220   b  through silicide source contacts  226   a ,  226   b , and  226   c . In the embodiment shown, each silicide source contact  226   a ,  226   b , and  226   c  extends vertically on a sidewall of source region  220   a  and/or  220   b , and laterally on respective contact regions  224   a ,  224   b , and  224   c . Thus, as shown in  FIG. 2G , source metal  232  can contact source regions  220   a  and  220   b  in embodiments where, for example, dielectric caps  230   a  and  230   b  extend laterally over contact regions  224   a ,  224   b , and  224   c.    
     In transistors  240   a  and  240   b , silicide gate contacts  228   a  and  228   b  provide a low resistance path for a signal from a gate contact (not shown in the Figures). Furthermore, silicide-gate contacts  228   a  and  228   b  extend along the length of respective gate electrodes  216   a  and  216   b  and are coupled to the gate contact (not shown in the Figures). In one specific example, the cross-section shown in  FIG. 2G  can be remote from the location at which the gate contact is coupled to silicide gate contacts  228   a  and  228   b , while silicide gate contacts  228   a  and  228   b  provide a low resistance signal path along the length of gate electrodes  216   a  and  216   b  to the cross-section. Thus, silicide gate contacts  228   a  and  228   b  can reduce sheet resistance in transistors  240   a  and  240   b.    
     Furthermore, as discussed above, the invention can provide for, for example, trench FET  240   a  including gate electrode  216   a  having lower portion  216   a   1  formed in substrate  202  and proud portion  216   a   2  formed over lower portion  216   a   1 . As shown in  FIG. 2G , proud portion  216   a   2  is situated above source regions  220   a . Thus, proud region  216   a   2  can increase the effective conductive area of gate electrode  216   a . Furthermore, proud region  216   a   2  can have a width  211   a  greater than lower portion  216   a   2 , which can further increase the effective conductive area of gate electrode  216   a . As such, proud portion  216   a   2  can significantly reduce gate resistance R g , even when dimensions of trench  206   a  are maintained. 
     From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would appreciate that changes can be made in form and detail without departing from the spirit and the scope of the invention. Thus, the described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.