Patent Publication Number: US-11048631-B2

Title: Maintaining cache hit ratios for insertion points into a cache list to optimize memory allocation to a cache

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a computer program product, system, and method for maintaining cache hit ratios for insertion points into a cache list to optimize memory allocation to a cache. 
     2. Description of the Related Art 
     A cache management system buffers tracks in a storage device recently accessed as a result of read and write operations in a faster access storage device, such as memory, than the storage device storing the requested tracks. Subsequent read requests to tracks in the faster access cache memory are returned at a faster rate than returning the requested tracks from the slower access storage, thus reducing read latency. The cache management system may also return complete to a write request when the modified track directed to the storage device is written to the cache memory and before the modified track is written out to the storage device, such as a hard disk drive. The write latency to the storage device is typically significantly longer than the latency to write to a cache memory. Thus, using cache also reduces write latency. 
     A cache management system may maintain a linked list having one entry for each track stored in the cache, which may comprise write data buffered in cache before writing to the storage device or read data. In the commonly used Least Recently Used (LRU) cache technique, if a track in the cache is accessed, i.e., a cache “hit”, then the entry in the LRU cache list for the accessed track is moved to a Most Recently Used (MRU) end of the list. If the requested track is not in the cache, i.e., a cache miss, then the track in the cache whose entry is at the LRU end of the list may be removed and demoted and an entry for the track data staged into cache from the storage is added to the MRU end of the LRU list. With this LRU cache technique, tracks that are more frequently accessed are likely to remain in cache, while data less frequently accessed will more likely be removed from the LRU end of the list to make room in cache for newly accessed tracks. 
     In order to move a track to the MRU end when it is accessed, the process managing the cache needs to obtain a lock on the LRU cache list. Since this lock is highly sought by many processes, there may be substantial lock contention to obtain the lock. 
     One technique to address lock contention is to batch the tracks that need to be moved to the MRU end in an MRU array. When the MRU array is full, all the tracks in the MRU array are moved to the MRU end of the cache list. Another technique to address lock contention is cache partitioning where multiple LRU lists are maintained for different partitions of track where each partition has its own LRU lock. 
     There is a need in the art for improved techniques for managing tracks in the cache to maintain cache hit ratio. 
     SUMMARY 
     Provided are a computer program product, system, and method for maintaining cache hit ratios for insertion points into a cache list to optimize memory allocation to a cache. There are a plurality of insertion points to a cache list for the cache having a least recently used (LRU) end and a most recently used (MRU) end. Each insertion point of the insertion points identifies a track in the cache list. Insertion points to tracks in the cache list are used to determine locations in the cache list at which to indicate tracks in the cache in the cache list that are to be indicated at the MRU end of the cache list. Indication is made of cache hits for each of the insertion points used to indicate locations in the cache list for tracks accessed while indicated in the cache list. The cache hits indicated for the insertion points are to indicate whether to increase or decrease a size of the cache. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an embodiment of a computing environment. 
         FIG. 2  illustrates an embodiment of a Least Recently Used (LRU) list. 
         FIG. 3  illustrates an embodiment of a cache control block. 
         FIG. 4  illustrates an embodiment of an insertion point. 
         FIG. 5  illustrates an embodiment of operations to process a read request to a track. 
         FIG. 6  illustrates an embodiment of operations to initiate a demote scan to demote tracks from the LRU end of the cache list. 
         FIG. 7  illustrates an embodiment of operations to process tracks added to the cache but not added to the cache list that are maintained in an MRU array. 
         FIG. 8  illustrates an embodiment of operations to move a track to an insertion point in the cache list. 
         FIG. 9  illustrates an embodiment of operations to adjust the insertion points after moving a track above an insertion point. 
         FIG. 10  illustrates an embodiment of operations to adjust the insertion points after moving a track below an insertion point. 
         FIG. 11  illustrates an embodiment of operations to adjust the insertion points after multiple tracks are moved to insertion points. 
         FIG. 12  illustrates an embodiment of operations to determine cache hit ratios for insertion points for tracks accessed in the cache. 
         FIG. 13  illustrates an embodiment of operations to determine whether to adjust a cache size of the cache based on the cache hit ratios for the insertion points. 
         FIG. 14  illustrates a computing environment in which the components of  FIG. 1  may be implemented. 
     
    
    
     DETAILED DESCRIPTION 
     In current art, tracks that are accessed may be batched and then the batch of tracks are repositioned at the MRU end of the cache list. However, because a period of time may have lapsed since the accessed tracks in a batch are processed, their appropriate position in the LRU list based on the time they were last accessed may not be at the MRU end, which may have tracks more recently accessed. 
     Described embodiments provide improvements to computer caching technology to use insertion points to determine where to position accessed tracks in the LRU list when their movement to the MRU end is delayed to process in a batch. With described embodiments, there are a plurality of insertion points to a cache list where each insertion point of the insertion points identifies a track in the cache list at different intervals of tracks. When a track is ready to move to the MRU end, a determination is made of an insertion point of the insertion points at which to move the processed track, which may be an insertion point having a timestamp closest to the time the track was last accessed. The track is then indicated at a position in the cache list with respect to the determined insertion point. 
     The described embodiments place accessed tracks that are delayed in moving to the MRU end at a location in the cache list that includes other entries having a last accessed time closest to the time the track was last accessed. This use of insertion points maintains the temporal integrity of the cache list to ensure that tracks having similar last accessed times are demoted together, which improves the cache hit ratio. 
     One issue with cache management is that tracks at the LRU end may be infrequently accessed and not contribute to improving the cache hit ratio even though they consume cache space. Described embodiments provide further improvements to computer technology to optimize the allocation of memory space to cache by maintaining cache hit ratios for insertion points indicating a percentage of accesses to tracks added to insertion points while in cache. This information on cache hit ratios may then be used to determine whether insertion points near the LRU end have a relatively high or low cache hit ratio indicating their contribution to the overall cache hit ratio of the cache. 
     If an insertion point at the LRU end, which would more often be the location in cache contributing least to the cache hit ratio, has a relatively high cache hit ratio and contributes to an improved cache hit ratio, then this indicates the cache may be expanded in size to add further tracks that may also contribute to improvements in the cache hit ratio. 
     On the other hand, if one or more insertion points closest to the LRU end have relatively low cache hit ratios and are not contributing to an overall improved cache hit ratio, then this indicates these regions of the cache storing tracks for the insertion points having the relatively lower cache hit may be deallocated from the cache without negatively impacting the cache hit ratio and deployed to more urgent uses. 
       FIG. 1  illustrates an embodiment of a computing environment. A plurality of hosts  102   1 ,  102   2  . . .  102   n  may submit Input/Output (I/O) requests to a storage controller  104  over a network  106  to access data at volumes  108  (e.g., Logical Unit Numbers, Logical Devices, Logical Subsystems, etc.) in a storage  110 . The storage controller  104  includes one or more processors  112  and a memory  114 , including a cache  116  to cache data for the storage  110 . The processor  112  may comprise a separate central processing unit (CPU), one or a group of multiple cores on a single CPU, or a group of processing resources on one or more CPUs. The cache  116  buffers data transferred between the hosts  102   1 ,  102   2  . . .  102   n  and volumes  108  in the storage  110 . 
     The memory  114  further includes a storage manager  118  for managing the transfer of tracks transferred between the hosts  102   1 ,  102   2  . . .  102   n  and the storage  110  and a cache manager  120  that manages data transferred between the hosts  102   1 ,  102   2  . . .  102   n  and the storage  110  in the cache  116 . A track may comprise any unit of data configured in the storage  110 , such as a track, Logical Block Address (LBA), storage cell, group of cells (e.g., column, row or array of cells), sector, segment, etc., which may be part of a larger grouping of tracks, such as a volume, logical device, etc. 
     The cache manager  120  maintains cache management information  122  in the memory  114  to manage read (unmodified) and write (modified) tracks in the cache  116 . The cache management information  122  may include a least recently used (LRU) cache list  200  in which to indicate tracks in the cache  116 ; a track index  124  providing an index of tracks in the cache  116  to cache control blocks in a control block directory  300   n , where there is one cache control block for each track in the cache  116  providing metadata on the track in the cache  116  and the cache list  200  may indicate cache control blocks  300   i  in the directory  300 ; insertion points  400  that point to tracks in the cache list  200 , such as every Nth track; a most recently used (MRU) array  126 , also referred to as an MRU list, having tracks added to the cache  116  that have not yet been indicated in the cache list  200  to allow batches of tracks to be added to the cache list  200  at once to improve cache processing efficiency because a single lock request may be used to add multiple newly added tracks to the cache  116  in the cache list  200 ; and a demote ready list  128  indicating tracks removed from an LRU end of the cache list  200  that are ready to demote from the cache  116 . 
     The processor  112  executes a demote scan task  130  to scan the cache list  200  to determine unmodified tracks to add to the demote ready list  128 . The processor  112  may further execute a cache optimizer  132  that performs analysis operations on gathered hit ratio statistics to determine whether to recommend or initiate a change in cache  116  size based on hit ratio statistics. 
     The storage manager  118 , cache manager  120 , and demote scan task  130  are shown in  FIG. 1  as program code loaded into the memory  114  and executed by one or more of the processors  112 . Alternatively, some or all of the functions may be implemented as microcode or firmware in hardware devices in the storage controller  104 , such as in Application Specific Integrated Circuits (ASICs). 
     The storage  110  may comprise one or more storage devices known in the art, such as a solid state storage device (SSD) comprised of solid state electronics, NAND storage cells, EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, flash disk, Random Access Memory (RAM) drive, storage-class memory (SCM), Phase Change Memory (PCM), resistive random access memory (RRAM), spin transfer torque memory (STM-RAM), conductive bridging RAM (CBRAM), magnetic hard disk drive, optical disk, tape, etc. The storage devices may further be configured into an array of devices, such as Just a Bunch of Disks (JBOD), Direct Access Storage Device (DASD), Redundant Array of Independent Disks (RAID) array, virtualization device, etc. Further, the storage devices may comprise heterogeneous storage devices from different vendors or from the same vendor. 
     The memory  114  may comprise a suitable volatile or non-volatile memory devices, including those described above. 
     The network  106  may comprise a Storage Area Network (SAN), a Local Area Network (LAN), a Wide Area Network (WAN), the Internet, and Intranet, etc. Alternatively, the hosts  102   1 ,  102   2  . . .  102   n  may connect to the storage controller  104  over a bus interface, such as a Peripheral Component Interconnect (PCI) bus interface and other interfaces known in the art. 
       FIG. 2  illustrates an embodiment of the cache list  200  as a Least Recently Used (LRU) list  200 , having a most recently used (MRU) end  202  identifying a track most recently added to the cache  116  or most recently accessed in the cache  116  and a least recently used (LRU) end  204  from which the track identified at the LRU end  204  is selected to demote from the cache  116 . The MRU end  202  may also be associated with a first insertion point  400   1 . Subsequent insertion points  400   2 ,  400   3  . . .  400   n−1 ,  400   n  are added as the cache list  200  fills up as tracks are added to the cache  116 . There may be an insertion point  400   i  added every N number of tracks, so as a next Nth track is added/indicated to the cache list  200 , a new insertion point  400   i  is added. For instance, upon adding the (i*N)th track, insertion point (i+1) is added to point to the (i*N)th track in the cache list  200 . 
     As a track is added to the MRU end  202 /first insertion point  400   1 , other tracks move downward toward the LRU end  204 . If there is not sufficient space for the track being added to the MRU end  202 , then a track may be demoted from the LRU end  204  to make room for the new track being added to the cache list  200 . 
       FIG. 3  illustrates an embodiment of an instance of a cache control block  300   i  for one of the tracks in the cache  116 , including, but not limited to, a cache control block identifier  302 , such as an index value of the cache control block  300   i ; the cache list  304  in which the track associated cache control block  300   i  is indicated; a position in the LRU cache list  306  where the track is indicated; a last accessed timestamp  308  indicating a time the track was last accessed in the cache  116 , such as read; a re-MRU flag  310  indicating whether the track needs to be added toward the MRU end  202  of the cache list  200 , such as if the track is accessed while indicated in the cache list  200 ; last MRU&#39;d timestamp  312  indicating timestamp of when the track was last MRU&#39;d or moved to an insertion point  400   i  in the cache list  200 ; and a demote status  314  indicating whether the track identified by the cache control block  300   i  is to be demoted from the cache  116  and indicated in the demote ready list  128 . Additional information may be included in the cache control block  300   i  not mentioned herein that is used to manage the track in the cache  116 . 
     In certain embodiments, the timestamps  308 ,  312  may be set to a sequence number that that is periodically incremented, such as at every clock cycle or couple of milliseconds. 
       FIG. 4  illustrates an embodiment of an insertion point  400   i , where there may be an insertion point  400   1  pointing to the MRU end  202  of the cache list  200  and a further insertion point  400   i  added to point to every Nth number of tracks in the cache list  200 , so that there are N tracks indicated in the cache list  200  between any two insertion points  400   i  and  400   i+1 . Each insertion point  400   i  may include an insertion point number  402  indicating the number of the insertion point, such that an ith number may point to an (i−1)*Nth track in the cache list  200 ; an entry number  404  in the cache list  200  to which the insertion point points, e.g., (i−1)*Nth entry or other entry if adjusted; a cache control block  406  identifying a track addressed/pointed to by the insertion point  400   i ; a number of hits  408  for the insertion point  400   i  indicating a number of times a track accessed in cache was moved to that insertion point when being moved toward the MRU end, i.e., re-MRY&#39;d; and a hit ratio  410  comprising the number of hits  408  at the insertion point  402  divided by a number of access requests, e.g., reads, received during a measurement period. 
     The hit ratios  410  of the insertion points near the LRU end  204 , where fewer access requests are received, may be used to determine whether to increase the cache size if the insertion points  400   i  at the LRU end  204  have a relatively high cache hit ratio for tracks at the LRU end  204 , such as a cache hit ratio above ½ of the average hit ratios for insertion points in the cache list  200 . Further, if insertion points  400   i  at the LRU end  204  have a relatively lower hit ratio, such as less than ¼ of an average hit ratio of the insertion points, then the cache portion including the insertion points at the LRU end with the relatively lower hit ratio may be removed to reduce the cache  116  size because the tracks at insertion points at the LRU end  204  with relatively low cache hit ratios are not contributing to a higher hit ratio and thus not needed to maintain the overall cache hit ratio. 
       FIG. 5  illustrates an embodiment of operations performed by the cache manager  120  to process a read request to a track. Upon receiving (at block  500 ) a read request, if (at block  502 ) the track is in the cache  116 , then the last accessed timestamp  308  in the cache control block  300   i  for the read track is set (at block  504 ) to a current system timestamp and the re-MRU flag  310  is set (at block  506 ) to indicate the track needs to be moved toward the MRU end  202 , or to an appropriate insertion point  400   i . If (at block  502 ) the track to read is not in the cache  116 , the track is staged (at block  508 ) from the volume  108  to the cache  116 . A cache control block  300   i  for the staged track is added (at block  510 ) to the MRU array  126 , the last re-MRU&#39;d timestamp  312  and the last accessed timestamp  308  are set to a current timestamp, and the re-MRU flag  310  is set to indicate to not re-MRU. 
     With the embodiment of  FIG. 5 , a requested track indicated in the cache list  200  is not immediately moved to the MRU end  202 , but instead the moving of the track to the MRU end  202  is delayed until a later time when multiple tracks can be moved to the appropriate insertion point  400   i  in the cache list  200 . This avoids the latency and lock contention required to immediately move an accessed track to the MRU end  202  after access. Instead, the accessed track is indicated through the flag  310  as needing to be re-MRU&#39;d and may be moved to a higher insertion point in the cache list  200  in batch where the lock to the cache list  200  may be accessed once to use to re-MRU multiple tracks to higher insertion points  400   i  in the cache list  200  towards the MRU end  202 . This reduces lock contention and latency in processing the cache list  200 , which reduces latency for processing I/O requests. Further, new tracks staged into cache  116  are added to the MRU array  126  so that they may in batch be indicated in the cache list  200  at insertion points  400   i  having timestamps close to the time the new track was added to the cache  116 . 
       FIG. 6  illustrates an embodiment of operations performed by the demote scan task  130  periodically invoked to process tracks from the LRU end  204  of the cache list  200  to demote from cache. Upon processing (at block  600 ) a track to demote at the LRU end  204 , if (at block  602 ) the re-MRU flag  310  indicates to re-MRU or move the track toward the MRU end  202 , then control proceeds (at block  604 ) to  FIG. 8  to re-MRU the processed track. If (at block  602 ) the re-MRU flag  310  is not set, indicating the track was not recently accessed since last added to the cache  116  or re-MRU&#39;d to an insertion point  400   i , then the processed track is removed (at block  606 ) from the cache list  200  and demoted, such as added to the demote ready list  128 , from where tracks are removed from cache  116 . 
     With the embodiment of  FIG. 6 , only tracks are removed from the LRU end  204  that do not have the re-MRU flag  310  set, which indicates the track was not accessed since being added to the cache list  200  or re-MRU&#39;d to an insertion point  400   i  in the cache list  200 . If a track was accessed while in the cache list  200  and indicated as needing to be re-MRU&#39;d, i.e., moved upward toward an insertion point  400   i , then that track is not demoted and re-MRU&#39;d according to  FIG. 8 . Since the demote scan task  130  is holding the lock to the cache list  200 , tracks can be re-MRU&#39;d to an insertion point  400   i  without having to incur latency from lock contention for each track to obtain the lock to access the cache list  200 , but instead the lock is obtained once to re-MRU multiple tracks. 
       FIG. 7  illustrates an embodiment of operations performed by the cache manager  120  and/or demote scan task  130  to process the MRU array  126  to add tracks to an insertion point  400   i  based on when they were added to the cache  116 , but not yet added to the cache list  200 . The MRU array  126  may be processed when the number of tracks equals a threshold or the array  126  is full. Upon initiating (at block  700 ) processing of tracks in the MRU array  126 , control proceeds to perform operations of  FIG. 6  until the demote scan task  130  demotes a number of tracks equal to the number of tracks in the MRU array  126  to add to the cache list  200 . Control then proceeds (at block  704 ) to  FIG. 8  to re-MRU each of the tracks in the MRU array  126 . 
     With the embodiment of  FIG. 7 , tracks added to the cache  116  are not immediately indicated to the MRU end  202 , which would cause latency delays to obtain a lock to the cache list  200 . Instead, tracks added to the cache  116  are indicated in the MRU array  126  and batched processed to move to an insertion point  400   i , i.e., re-MRU&#39;d, while the lock is held for the cache list  200 , to avoid lock contention to move a track to the MRU end  202  immediately when adding to the cache  116 . 
       FIG. 8  illustrates an embodiment of operations performed by the cache manager  120  and/or demote scan task  130  to re-MRU a track to an insertion point  400   i  in the cache list  200 . Upon processing (at block  800 ) a track, a variable i is set (at block  802 ) to n for the first insertion point above the LRU end  204  of the cache list  200 . The insertion point  400   i  timestamp is determined (at block  804 ) as the last re-MRU&#39;d timestamp  312  for the track/entry in the cache list  200  pointed to by insertion point  400   i . If (at block  806 ) the last accessed timestamp  308  of the processed track is less than the insertion point  400   i  timestamp, then the processed track is indicated (at block  808 ) in the cache list  200  with respect to the entry  404  pointed to by the insertion point  400   i . The track may be inserted above or below the entry  404  pointed to by the determined insertion point  400   i . For the processed track cache control block  300   i , the last re-MRU&#39;d timestamp  312  is set (at block  810 ) to the last accessed timestamp  308  of the processed track and the re-MRU flag  310  is reset to indicate to not re-MRU the track. 
     If (at block  806 ) the last accessed timestamp  308  of the processed track is greater than insertion point  400   i  timestamp, then if (at block  812 ) i is equal to one, i.e., the first insertion point  400   1  pointing to the MRU end  202 , then the track is indicated (at block  814 ) above the first insertion point  400   1  at the MRU end  202 . From block  814 , control proceeds to block  810  to update the last re-MRU&#39;d timestamp  312  and the re-MRU flag  310 . If i is not the first insertion point or one, then i is decremented (at block  816 ) and control proceeds to block  804  to process the next insertion point  400   i−1  in the cache list  200  toward the MRU end  202 . 
     At blocks  808  and  814 , when indicating a track with respect to the insertion point when processing tracks in a processor array  132  (as in  FIG. 7 ), if the track is not indicated in the cache list  200 , then a new indication is made of the track in the cache list  200 . Otherwise, if the track to indicate in the cache list  200  at blocks  808  and  814  is already in the cache list  200 , then indication of that track is moved to the location associated with the insertion point  400   i . 
     With the embodiment of  FIG. 8 , a track is added to a position in the cache list  200  with respect to an insertion point  400   i  having a timestamp closest to the last time the track was accessed in the cache. In this way, a track is added to a position in the cache list  200  toward the MRU end  202  based on its time of last access so the track is added to a location with respect to other tracks having a similar last time accessed, so it remains in the cache list  200  for a time commensurate with the last accessed timestamps of other tracks. This allows tracks to be moved toward the MRU end  202  in a batch and ensure that the track is added to a location in the cache list  200  adjacent to tracks having a similar last accessed time, tracks in temporal proximity. This improves the cache hit ratio because tracks are added to the cache list  200  at a location based on the length of time the track was last accessed, so a track accessed a relatively longer time ago is added to a position closer to the LRU end  204  than a track accessed relatively more recently is added to a position closer to the MRU end  202 . This allows the adjustment of an accessed track in the cache list  200  to be delayed to allow batching of moving tracks toward the MRU end  202  so the tracks are demoted at the same time as tracks last accessed at a similar time, to maintain the cache hit ratio. 
       FIG. 9  illustrates an embodiment of operations performed by the demote scan task  130  and/or cache manager  120  to adjust one insertion point  400   k  immediately after adding a track above insertion point k. Upon initiating (at block  900 ) the adjustment immediately after adding the track above insertion point  400   k , insertion points  400   n  through  400   k  are each moved (at block  902 ) one entry up toward MRU end  202  and, for each moved insertion point  400   i  the entry  404  and cache control block  406  are adjusted to point to the new entry and cache control block  300   i  for the added track. 
       FIG. 10  illustrates an embodiment of operations performed by the demote scan task  130  and/or cache manager  120  to adjust one insertion point  400   k  immediately after adding a track below insertion point k. Upon initiating (at block  1000 ) the adjustment immediately after adding the track below insertion point  400   k , insertion points  400   n  through  400   k+1  are each moved (at block  1002 ) one entry up toward the MRU end  202  and, for each moved insertion point, the entry  404  and cache control block  406  are adjusted to point to the new entry and cache control block  300   i  for the added track. 
       FIG. 11  illustrates an embodiment of operations performed by the demote scan task  130  and/or cache manager  120  to adjust one or more of the insertion points after moving multiple tracks to insertion points according to  FIG. 8 . Upon initiating (at block  1100 ) to adjust the insertion points after moving multiple tracks, one or more of the insertion points are adjusted (at block  1102 ) to ensure that there are only N entries, such as a fixed number of entries, between each pair of insertion points, that the first insertion point  400   1  points to the MRU end  202  of the cache list  200 , and that there are N entries between the LRU end  204  and the last insertion point  400   n . Insertion points  400   i  may be moved upward toward the MRU end  202  to adjust. 
     With the embodiment of  FIG. 11 , the adjustment of the insertion points  400   i  is delayed until a plurality of tracks are moved to insertion points, i.e., re-MRU&#39;d, to batch the adjustment of insertion points. The operations of  FIG. 11  optimize the insertion pointer adjustment operations by moving the insertion point multiple entries at once to batch the processing which improves performance. 
       FIG. 12  illustrates an embodiment of operations performed by the cache manager  120  to maintain hit ratio  410  information for the insertion points  400   1  . . .  400   n  that may be used to adjust the cache size. The cache manager  120  initiates (at block  1200 ) a measurement period to gather number of hits  408  for tracks at insertion points  400   1  during a measurement period which may comprise a time period or a number of times tracks are added to insertion points after having access requests, as shown in the embodiment of  FIG. 12 . An access request counter is set (at block  1202 ) to zero. Upon completing (at block  1204 ) the operations in  FIG. 8  to re-MRU a track previously accessed in the cache list  200  but was not moved to the MRU end  202  at the time, the access request counter is incremented (at block  1206 ) because that track was previously accessed while in the cache list  200 , but remained at its current position in the cache list  200  until re-MRU&#39;d during demotion according to  FIG. 8 . The cache manager  120  increments (at block  1208 ) the number of hits  408  for the determined insertion point  400   1  at which the processed track was indicated, i.e., moved, during the re-MRU operation of  FIG. 8 , i.e., at blocks  808  or  814 . If (at block  1210 ) the measurement period of hits has completed, such as if the access request counter equals a predetermined measurement threshold or a measurement time period has experienced, then for each insertion point  400   1  . . .  400   n , the hit ratio  410  is calculated by dividing the number of hits  408  by the access request counter measured during the measurement period. 
     With the embodiment of  FIG. 12 , a cache hit ratio is determined for each of the insertion points  400   i  at which tracks are added after being accessed while in cache  116  to indicate which insertion points are receiving the most and fewest number of hits. The calculated hit ratio  410  may be saved for later analysis, such as described in  FIG. 13 , or aggregated with previous calculated hit ratios for the insertion points  400   i  . . .  400   n  to provide an average or time weighted average of cache hit ratios  410  for insertion points  400   1  . . .  400   n . 
       FIG. 13  illustrates an embodiment of operations performed by the cache optimizer  132  routine to use the gathered hit ratios  410  for the insertion points  400   1  . . .  400   n  to indicate or initiate a change in the  116  cache size based on whether cache hit ratio  410  at insertion points near the LRU end  204  are contributing to an improved overall cache hit ratio. Upon initiating (at block  1300 ) the operation to determine whether to adjust the cache  116  size, the cache optimizer  132  sets (at block  1302 ) a variable i to a last added insertion point number n closest to the LRU end  204 . A last insertion point below a low cache hit ratio threshold is set to 0. If (at block  1306 ) the cache hit ratio  410  for insertion point i is greater than a high cache hit ratio threshold, which may comprise a relatively high cache hit ratio for insertion points/tracks at the LRU end  204 , e.g., ½ an average cache hit ratio across insertion points, then an indication is made (at block  1308 ) to increase the cache size by some amount, such as a fixed amount, because the tracks at the LRU end  204 , which is generally the least accessed end, are receiving a relatively high number of hits so extending the cache  116  size to store more tracks at the LRU end can improve the cache hit ratio and cache performance. 
     If (at block  1306 ) the cache hit ratio for the insertion point i is less than a low hit ratio threshold, which may comprise a relatively low cache hit ratio for insertion points/tracks at the LRU end  204 , e.g., ¼ an average cache hit ratio across insertion points, then the last insertion point below the low cache hit ratio threshold is set (at block  1312 ) to i, indicating the last determined insertion point  400   i  having a relatively low cache hit ratio  410 . The variable i is decremented (at block  1314 ) to process the next insertion point  400   i−1  toward the MRU end  202  and control proceeds back to block  1310  to consider whether a next insertion point  400   i−1  closer to the MRU end  202  also has a cache hit ratio  410  below the low cache hit ratio threshold, indicating the lower tracks at insertion point  400   i+1  do not contribute to an improved cache hit ratio because they have a relatively low cache hit ratio even for tracks at the LRU end  204 . 
     If (at block  1310 ) the cache hit ratio for insertion point  400   i  is not less than the low cache hit ratio threshold, then a determination is made (at block  1316 ) whether the last insertion point below the low cache hit ratio threshold is greater than 0, indicating at least one insertion point  400   i  was found to have a cache hit ratio  410  below the low cache hit ratio threshold. If there is at least one insertion point  400   i  having a low cache hit ratio  410 , then a determination is made (at block  1318 ) of all tracks in the cache list  200  between the last determined insertion point below the low cache hit ratio threshold, set at the most recent execution of block  1312 , and the LRU end  204 . A determination is made (at block  1320 ) of the cache  116  size of the determined number of tracks. Indication is then made (at block  1322 ) to decrease the cache size by the determined cache size. 
     When the cache optimizer  132  determines whether the cache size should be increased or decreased, the cache optimizer  132  may report that finding to an administrator to take further action. In a further embodiment, the cache optimizer  132  may modify the cache size automatically or upon an administrator selecting the cache optimizer  132  to implement the cache adjustment operation. If the indication is made to increase the cache size, then the cache optimizer  132  may reconfigure the memory  114  to assign a fixed amount of additional memory space to the cache  116 . If the indication is made to decrease the cache  116  size, then the cache optimizer  132  may reconfigure the memory  114  to reallocate the determined cache size reduction from the cache  116  to the memory  114 . 
     With the described embodiment of  FIG. 13 , the cache  116  size may be increased or reduced to maximize optimal usage of memory space  114  and maximize the cache hit ratio. If portions of the cache  116  space are not caching tracks that contribute to an improved hit ratio, then that portion of the cache  116  space may be reallocated to the memory  114  for other operations because the use of such space in the cache  116  does not contribute significantly to an improved cache hit ratio. However, if the lowest insertion point region of the cache  116  at the LRU end  204  has a relatively high cache hit ratio for tracks at the LRU end  204 , then caching tracks at the LRU end is contributing to an improved cache hit ratio, which justifies extending the size of the cache  116  to allow for more tracks to be cached that may also positively contribute to the overall cache hit ratio given the cache hit ratio of the current tracks at the LRU end  204 . 
     The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention. 
     The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire. 
     Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device. 
     Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user&#39;s computer, partly on the user&#39;s computer, as a stand-alone software package, partly on the user&#39;s computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user&#39;s computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention. 
     Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions. 
     These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks. 
     The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks. 
     The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions. 
     The computational components of  FIG. 1 , including the hosts  102   1 ,  102   2  . . .  102   n  and storage controller  104 , may be implemented in one or more computer systems, such as the computer system  1402  shown in  FIG. 14 . Computer system/server  1402  may be described in the general context of computer system executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, and so on that perform particular tasks or implement particular abstract data types. Computer system/server  1402  may be practiced in distributed cloud computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices. 
     As shown in  FIG. 14 , the computer system/server  1402  is shown in the form of a general-purpose computing device. The components of computer system/server  1402  may include, but are not limited to, one or more processors or processing units  1404 , a system memory  1406 , and a bus  1408  that couples various system components including system memory  1406  to processor  1404 . Bus  1408  represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnects (PCI) bus. 
     Computer system/server  1402  typically includes a variety of computer system readable media. Such media may be any available media that is accessible by computer system/server  1402 , and it includes both volatile and non-volatile media, removable and non-removable media. 
     System memory  1406  can include computer system readable media in the form of volatile memory, such as random access memory (RAM)  1410  and/or cache memory  1412 . Computer system/server  1402  may further include other removable/non-removable, volatile/non-volatile computer system storage media. By way of example only, storage system  1413  can be provided for reading from and writing to a non-removable, non-volatile magnetic media (not shown and typically called a “hard drive”). Although not shown, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a “floppy disk”), and an optical disk drive for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media can be provided. In such instances, each can be connected to bus  1408  by one or more data media interfaces. As will be further depicted and described below, memory  1406  may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention. 
     Program/utility  1414 , having a set (at least one) of program modules  1416 , may be stored in memory  1406  by way of example, and not limitation, as well as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data or some combination thereof, may include an implementation of a networking environment. The components of the computer  1402  may be implemented as program modules  1416  which generally carry out the functions and/or methodologies of embodiments of the invention as described herein. The systems of  FIG. 1  may be implemented in one or more computer systems  1402 , where if they are implemented in multiple computer systems  1402 , then the computer systems may communicate over a network. 
     Computer system/server  1402  may also communicate with one or more external devices  1418  such as a keyboard, a pointing device, a display  1420 , etc.; one or more devices that enable a user to interact with computer system/server  1402 ; and/or any devices (e.g., network card, modem, etc.) that enable computer system/server  1402  to communicate with one or more other computing devices. Such communication can occur via Input/Output (I/O) interfaces  1422 . Still yet, computer system/server  1402  can communicate with one or more networks such as a local area network (LAN), a general wide area network (WAN), and/or a public network (e.g., the Internet) via network adapter  1424 . As depicted, network adapter  1424  communicates with the other components of computer system/server  1402  via bus  1408 . It should be understood that although not shown, other hardware and/or software components could be used in conjunction with computer system/server  1402 . Examples, include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc. 
     The terms “an embodiment”, “embodiment”, “embodiments”, “the embodiment”, “the embodiments”, “one or more embodiments”, “some embodiments”, and “one embodiment” mean “one or more (but not all) embodiments of the present invention(s)” unless expressly specified otherwise. 
     The terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless expressly specified otherwise. 
     The enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise. 
     The terms “a”, “an” and “the” mean “one or more”, unless expressly specified otherwise. 
     Devices that are in communication with each other need not be in continuous communication with each other, unless expressly specified otherwise. In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries. 
     A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary a variety of optional components are described to illustrate the wide variety of possible embodiments of the present invention. 
     When a single device or article is described herein, it will be readily apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device/article may be used in place of the more than one device or article or a different number of devices/articles may be used instead of the shown number of devices or programs. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments of the present invention need not include the device itself. 
     The foregoing description of various embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto. The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims herein after appended.