Patent Publication Number: US-9425119-B2

Title: Package structure and fabrication method thereof

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application claims under 35 U.S.C. §119(a) the benefit of Taiwanese Application No. 102145517, filed Dec. 11, 2013, the entire contents of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to package structures and fabrication methods thereof, and more particularly, to a package structure having a MEMS (Micro-Electro-Mechanical System) element and a fabrication method thereof. 
     2. Description of Related Art 
     MEMS elements have integrated electrical and mechanical functions and can be fabricated through various micro-fabrication technologies. A MEMS element is generally disposed on a substrate and protected by a cover or an encapsulant from being damaged by external environment. 
       FIG. 1  is a schematic cross-sectional view of a conventional package structure having a MEMS element. Referring to  FIG. 1 , a MEMS element  11 , such as a pressure sensing element, is disposed on an LGA (Land Grid Array) substrate  10 , and electrical contacts  111  of the MEMS element  11  are electrically connected to electrical contacts  101  of the LGA substrate  10  by wire bonding. Then, a metal lid  12  is disposed on the substrate  10  to encase the MEMS element  11  therein, thus protecting the MEMS element  11  from being contaminated or damaged by external environment. However, such a package structure has a large size, which fails to meet the miniaturization requirement of end products. 
     Accordingly,  FIG. 2  shows a wafer-level pressure sensing package structure as disclosed by US Patent Application Publication No. 2006/0185429. Referring to  FIG. 2 , a MEMS element  21 , such as a pressure sensing element, is directly fabricated on a silicon substrate  23  and a glass lid  24  is bonded to the MEMS element  21  by anodic bonding. 
     However, in the silicon substrate  23 , a sensing cavity  231  and a plurality of through holes  232  need to be formed. Therefore, a through silicon via (TSV) technique is required, which uses KOH as an etchant to form vias or grooves. 
     Compared with the previous package structure, the package structure disclosed by US Patent Application Publication No. 2006/0185429 has a greatly reduced size. However, the TSV technique is costly and requires a high degree of accuracy, thereby complicating the fabrication process and increasing the fabrication cost. 
     Therefore, there is a need to provide a package structure and a fabrication method thereof so as to overcome the above-described drawbacks. 
     SUMMARY OF THE INVENTION 
     In view of the above-described drawbacks, the present invention provides a method for fabricating a package structure, which comprises the steps of: preparing a first wafer and a chip disposed on the first wafer, wherein the first wafer has opposite first and second surfaces and the first surface of the first wafer has a groove, a thin film closing an open end of the groove and a plurality of electrical contacts, and the chip has a third surface with a conductive layer and an opposite fourth surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the first surface of the first wafer in a manner that the seal ring surrounds the thin film of the first wafer and the electrical contacts are located outside the seal ring; electrically connecting the electrical contacts of the first wafer and the conductive layer of the chip through a plurality of first conductive wires; forming an encapsulant on the first surface of the first wafer for encapsulating the chip, the electrical contacts and the first conductive wires; removing a portion of the encapsulant and a portion of the first conductive wires from a top surface of the encapsulant so as to form a plurality of sub-conductive wires, wherein one ends of the sub-conductive wires are exposed from the encapsulant and the other ends of the sub-conductive wires are in electrical connection with the electrical contacts of the first wafer; and forming a through hole penetrating the first surface and the second surface of the first wafer and communicating with the concave portion of the chip. 
     In the above-described method, preparing the first wafer and the chip can comprise: preparing the first wafer and a second wafer disposed on the first wafer; thinning the second wafer; forming the conductive layer on the second wafer; and removing a portion of the second wafer to form the chip. 
     The present invention provides another method for fabricating a package structure, which comprises the steps of: preparing a first wafer, a chip disposed on the first wafer, and a lid member disposed on the chip, wherein the first wafer has opposite first and second surfaces and the first surface of the first wafer has a groove, a thin film closing an open end of the groove and a plurality of electrical contacts, and the chip has a third surface with a plurality of electrode pads and an opposite fourth surface with a concave portion and a seal ring located at a periphery of the concave portion, such that the chip is disposed on the first surface of the first wafer in a manner that the seal ring surrounds the thin film of the first wafer and the electrical contacts are located outside the seal ring, and the lid member is disposed on the third surface of the chip and has a conductive layer formed on a top surface thereof; electrically connecting the electrical contacts of the first wafer and the conductive layer of the lid member through a plurality of first conductive wires, and electrically connecting the electrical contacts of the first wafer and the electrode pads of the chip through a plurality of second conductive wires; forming an encapsulant on the first surface of the first wafer for encapsulating the chip, the lid member, the electrical contacts, the first conductive wires and the second conductive wires; removing a portion of the encapsulant and a portion of the first conductive wires from a top surface of the encapsulant so as to form a plurality of sub-conductive wires, wherein one ends of the sub-conductive wires are exposed from the encapsulant and the other ends of the sub-conductive wires are in electrical connection with the electrical contacts of the first wafer; and forming a through hole penetrating the first surface and the second surface of the first wafer and communicating with the concave portion of the chip. 
     In the above-described method, preparing the first wafer and the chip can comprise: preparing the first wafer and a second wafer disposed on the first wafer; thinning the second wafer; and removing a portion of the second wafer to form the chip. Further, the chip can be a motion sensor. 
     In an embodiment, after forming the through hole, the above-described two methods further comprise performing a singulation process. 
     After forming the sub-conductive wires, the above-described methods can further comprise forming a redistribution layer on the encapsulant, wherein the redistribution layer is electrically connected to the sub-conductive wires. Before forming the through hole, the above-described methods can further comprise mounting a carrier on the redistribution layer; and after forming the through hole, the above-described methods can further comprise removing the carrier. The carrier can be made of a transparent material. 
     After forming the through hole, the above-described methods can further comprise forming a plurality of conductive elements on the redistribution layer, wherein the conductive elements are electrically connected to the sub-conductive wires. In the above-described methods, the seal ring can be made of polymer, eutectic metal alloy or glass frit, and the first wafer can be a pressure sensor wafer or a temperature sensor wafer. 
     The present invention further provides a package structure, which comprises: a wafer having opposite first and second surfaces, wherein the first surface of the wafer has a groove, a thin film closing an open end of the groove and a plurality of electrical contacts; a chip disposed on the first surface of the wafer, wherein the chip has a third surface with a conductive layer and an opposite fourth surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the first surface of the wafer in a manner that the seal ring surrounds the thin film of the wafer and the electrical contacts are located outside the seal ring; an encapsulant formed on the first surface of the wafer for encapsulating the chip and the electrical contacts; a plurality of sub-conductive wires embedded in the encapsulant, wherein one ends of the sub-conductive wires are exposed from a top surface of the encapsulant and the other ends of sub-conductive wires are in electrical connection with the electrical contacts of the wafer; and a through hole penetrating the first surface and the second surface of the wafer and communicating with the concave portion of the chip. 
     The present invention provides another package structure, which comprises: a wafer having opposite first and second surfaces, wherein the first surface of the wafer has a groove, a thin film closing an open end of the groove and a plurality of electrical contacts; a chip disposed on the first surface of the wafer, wherein the chip has a third surface with a plurality of electrode pads and an opposite fourth surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the first surface of the wafer in a manner that the seal ring surrounds the thin film of the wafer and the electrical contacts are located outside the seal ring; a lid member disposed on the third surface of the chip and having a conductive layer formed on a top surface thereof; an encapsulant formed on the first surface of the wafer for encapsulating the chip and the electrical contacts; a plurality of sub-conductive wires embedded in the encapsulant, wherein one ends of the sub-conductive wires are exposed from a top surface of the encapsulant and the other ends of sub-conductive wires are in electrical connection with the electrical contacts of the wafer; a plurality of conductive wires embedded in the encapsulant for electrically connecting the electrical contacts of the wafer and the electrode pads of the chip; and a through hole penetrating the first surface and the second surface of the wafer and communicating with the concave portion of the chip. 
     In the above-described package structure, the chip can be a motion sensor. 
     The above-described two package structures can further comprise a redistribution layer formed on the encapsulant and electrically connected to the sub-conductive wires. The above-described package structures can further comprise a plurality of conductive elements formed on the redistribution layer and electrically connected to the sub-conductive wires. 
     In the above-described package structures, the wafer can be a pressure sensor wafer or a temperature sensor wafer, and the seal ring can be made of polymer, eutectic metal alloy or glass frit. 
     Therefore, the present invention eliminates the need to form through holes penetrating a silicon substrate as in the prior art, thereby reducing equipment and fabrication costs. Further, the present invention can integrate two types of sensors in a SiP (System in Package) package so as to achieve low power consumption, low cost and high performance. Furthermore, the package structure of the present invention has a reduced size so as to meet the miniaturization requirement. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a schematic cross-sectional view of a conventional package structure having a MEMS element; 
         FIG. 2  is a schematic cross-sectional view of another conventional package structure having a MEMS element; 
         FIGS. 3A to 3J  are schematic cross-sectional views showing a package structure and a fabrication method thereof according to a first embodiment of the present invention; and 
         FIGS. 4A to 4I  are schematic cross-sectional views showing a package structure and a fabrication method thereof according to a second embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification. 
     It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as “first”, “second”, “top”, “on”, “a” etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention. 
     First Embodiment 
       FIGS. 3A to 3J  are schematic cross-sectional views showing a package structure and a fabrication method thereof according to a first embodiment of the present invention. 
     Referring to  FIG. 3A , a first wafer  30  having opposite first and second surfaces  30   a ,  30   b  is provided. The first surface  30   a  of the first wafer  30  has a groove  300 , a thin film  301  closing an open end of the groove  300 , and a plurality of electrical contacts  302 . A plurality of upper electrodes  3011  are formed in the thin film  301  and a plurality of lower electrodes  3001  are formed on a bottom of the groove  300 . The first wafer  30  can be a pressure or temperature sensor wafer having a MEMS element. The closed groove  300  is in a vacuum state. 
     Referring to  FIG. 3B , a second wafer  31  is disposed on the first wafer  30 . The second wafer  31  has opposite third and fourth surfaces  31   a ,  31   b , and the fourth surface  31   b  of the second wafer  31  has a concave portion  310  and a seal ring  311  located at a periphery of the concave portion  310 . The second wafer  31  is disposed on the first surface  30   a  of the first waver  30  in a manner that the seal ring  311  surrounds the thin film  301  of the first wafer  30  and the electrical contacts  302  are located outside the seal ring  311 . The seal ring  311  can be made of polymer, eutectic metal alloy or glass frit. 
     Referring to  FIG. 3C , the second wafer  31  is thinned by, for example, grinding. Then, a conductive layer  312  is formed on the third surface  31   a  of the second wafer  31  to facilitate a subsequent wire bonding process. Thereafter, a portion of the second wafer  31  is removed by etching to form a chip  31 ′. 
     Referring to  FIG. 3D , a plurality of first conductive wires  32  are formed to electrically connect the electrical contacts  302  of the first wafer  30  and the conductive layer  312  of the chip  31 ′. 
     Referring to  FIG. 3E , an encapsulant  33  is formed on the first surface  30   a  of the first wafer  30  for encapsulating the chip  31 ′, the electrical contacts  302  and the first conductive wires  32 . 
     Referring to  FIG. 3F , a portion of the encapsulant  33  and a portion of the first conductive wires  32  are removed from a top surface of the encapsulant  33  by, for example, grinding so as to form a plurality of sub-conductive wires  32 ′. One ends of the sub-conductive wires  32 ′ are exposed from the top surface of the encapsulant  33  and the other ends of the sub-conductive wires  32 ′ are in electrical connection with the electrical contacts  302 . In the present embodiment, the conductive layer  312  can also be removed to expose the chip  31 ′, but it is not necessary. 
     Referring to  FIG. 3G , a redistribution layer  34  is formed on the encapsulant  33  and electrically connected to the sub-conductive wires  32 ′ so as to meet fan-out or fan-in requirements of conductive pads. 
     Referring to  FIG. 3H , a carrier  36  is mounted on the redistribution layer  34  through an adhesive layer  35 . The carrier  36  is made of a transparent material. Then, the overall structure is turned upside down. A double side aligner (not shown) is used to assist positioning and exposure, and a dry etching technique such as DRIE (Deep Reactive Ion Etching) is used to form a through hole  303  penetrating the first surface  30   a  and the second surface  30   b  of the first wafer  30  and communicating with the concave portion  310 . Before forming the through hole  303 , a portion of the first wafer  30  can be removed by grinding according to the practical need (not shown). 
     Referring to  FIG. 3I , the adhesive layer  35  and the carrier  36  are removed. 
     Referring to  FIG. 3J , a plurality of conductive elements  37  are formed on the redistribution layer  34  and electrically connected to the sub-conductive wires  32 ′. The conductive elements  37  can be, for example, solder balls. Further, a singulation process is performed to form a package structure  3 . 
     Second Embodiment 
       FIGS. 4A to 4I  are schematic cross-sectional views showing a package structure and a fabrication method thereof according to a second embodiment of the present invention. 
     Referring to  FIG. 4A , a first wafer  30  having opposite first and second surfaces  30   a ,  30   b  is provided. The first surface  30   a  of the first wafer  30  has a groove  300 , a thin film  301  closing an open end of the groove  300 , and a plurality of electrical contacts  302 . A plurality of upper electrodes  3011  are formed in the thin film  301  and a plurality of lower electrodes  3001  are formed on a bottom of the groove  300 . The first wafer  30  can be a pressure or temperature sensor wafer having a MEMS element. The closed groove  300  is in a vacuum state. 
     Referring to  FIG. 4B , a chip  41  is disposed on the first wafer  30 . The chip  41  can be a motion sensor. The chip  41  has a third surface  41   a  with a plurality of electrode pads  411  and an opposite fourth surface  41   b  with a concave portion  410  and a seal ring  412  located at a periphery of the concave portion  410 . A lid member  42  is disposed on the third surface  41   a  of the chip  41 . Further, the lid member  42  has a conductive layer  421  formed on a top surface thereof so as to facilitate a subsequent wire bonding process. The chip  41  is disposed on the first surface  30   a  of the first wafer  30  in a manner that the seal ring  412  surrounds the thin film  301  of the first wafer  30  and the electrical contacts  302  are located outside the seal ring  412 . The seal ring  412  can be made of polymer, eutectic metal alloy or glass frit. 
     Referring to  FIG. 4C , a plurality of first conductive wires  32  are formed to electrically connect the electrical contacts  302  of the first wafer  30  and the conductive layer  421  of the lid member  42 , and a plurality of second conductive wires  43  are formed to electrically connect the electrical contacts  302  of the first wafer  30  and the electrode pads  411  of the chip  41 . 
     Referring to  FIG. 4D , an encapsulant  33  is formed on the first surface  30   a  of the first wafer  30  for encapsulating the chip  41 , the lid member  42 , the electrical contacts  302 , the first conductive wires  32  and the second conductive wires  43 . 
     Referring to  FIG. 4E , a portion of the encapsulant  33  and a portion of the first conductive wires  32  are removed from a top surface of the encapsulant  33  by, for example, grinding so as to form a plurality of sub-conductive wires  32 ′. One ends of the sub-conductive wires  32 ′ are exposed from the top surface of the encapsulant  33  and the other ends of the sub-conductive wires  32 ′ are in electrically connection with the electrical contacts  302 . In the present embodiment, the conductive layer  421  can also be removed to expose the lid member  42 , but it is not necessary. 
     Referring to  FIG. 4F , a redistribution layer  34  is formed on the encapsulant  33  and electrically connected to the sub-conductive wires  32 ′ so as to meet fan-out or fan-in requirements of conductive pads. 
     Referring to  FIG. 4G , a carrier  36  is mounted on the redistribution layer  34  through an adhesive layer  35 . The carrier  36  is made of a transparent material. Then, the overall structure is turned upside down. A double side aligner (not shown) is used to assist positioning and exposure, and a dry etching technique such as DRIE is used to form a through hole  303  penetrating the first surface  30   a  and the second surface  30   b  of the first wafer  30  and communicating with the concave portion  310 . Before forming the through hole  303 , a portion of the first wafer  30  can be removed by grinding according to the practical need (not shown). 
     Referring to  FIG. 4H , the adhesive layer  35  and the carrier  36  are removed. 
     Referring to  FIG. 4I , a plurality of conductive elements  37  are formed on the redistribution layer  34  and electrically connected to the sub-conductive wires  32 ′. The conductive elements  37  can be, for example, solder balls. Further, a singulation process is performed to form a package structure  4 . 
     The present invention further provides a package structure  3 , which has: a first wafer  30  having opposite first and second surfaces  30   a ,  30   b , wherein the first surface  30   a  of the first wafer  30  has a groove  300 , a thin film  301  closing an open end of the groove  300  and a plurality of electrical contacts  302 ; a chip  31 ′ disposed on the first surface  30   a  of the first wafer  30 , wherein the chip  31 ′ has a third surface  31   a  with a conductive layer  312  and an opposite fourth surface  31   b  with a concave portion  310  and a seal ring  311  located at a periphery of the concave portion  310 , the chip  31 ′ being disposed on the first surface  30   a  of the first wafer  30  in a manner that the seal ring  311  surrounds the thin film  301  of the first wafer  30  and the electrical contacts  302  are located outside the seal ring  311 ; an encapsulant  33  formed on the first surface  30   a  of the first wafer  30  for encapsulating the chip  31 ′ and the electrical contacts  302 ; a plurality of sub-conductive wires  32 ′ embedded in the encapsulant  33 , wherein one ends of the sub-conductive wires  32 ′ are exposed from a top surface of the encapsulant  33  and the other ends of sub-conductive wires  32 ′ are in electrical connection with the electrical contacts  302  of the first wafer  30 ; and a through hole  303  penetrating the first surface  30   a  and the second surface  30   b  of the first wafer  30  and communicating with the concave portion  310  of the chip  31 ′. 
     The present invention further provides another package structure  4 , which has: a first wafer  30  having opposite first and second surfaces  30   a .  30   b , wherein the first surface  30   a  of the first wafer  30  has a groove  300 , a thin film  301  closing an open end of the groove  300  and a plurality of electrical contacts  302 ; a chip  41  disposed on the first surface  30   a  of the first wafer  30 , wherein the chip  41  has a third surface  41   a  with a plurality of electrode pads  411  and an opposite fourth surface  41   b  with a concave portion  410  and a seal ring  412  located at a periphery of the concave portion  410 , the chip  41  being disposed on the first surface  30   a  of the first wafer  30  in a manner that the seal ring  412  surrounds the thin film  301  of the first wafer  30  and the electrical contacts  302  are located outside the seal ring  412 ; a lid member  42  disposed on the third surface  41   a  of the chip  41  and having a conductive layer  421  formed on a top surface thereof; an encapsulant  33  formed on the first surface  30   a  of the first wafer  30  for encapsulating the chip  41  and the electrical contacts  302 ; a plurality of sub-conductive wires  32 ′ embedded in the encapsulant  33 , wherein one ends of the sub-conductive wires  32 ′ are exposed from a top surface of the encapsulant  33  and the other ends of sub-conductive wires  32 ′ are in electrical connection with the electrical contacts  302  of the first wafer  30 ; a plurality of conductive wires  43  embedded in the encapsulant  33  for electrically connecting the electrical contacts  302  of the first wafer  30  and the electrode pads  411  of the chip  41 ; and a through hole  303  penetrating the first surface  30   a  and the second surface  30   b  of the first wafer  30  and communicating with the concave portion  410  of the chip  41 . 
     The above-described package structures can further have a redistribution layer  34  formed on the encapsulant  33  and electrically connected to the sub-conductive wires  32 ′, and a plurality of conductive elements  37  formed on the redistribution layer  34  and electrically connected to the sub-conductive wires  32 ′. 
     In the above-described package structures, the first wafer  30  can be a pressure sensor wafer or a temperature sensor wafer, the chip  42  can be a motion sensor, and the seal ring  311 ,  412  can be made of polymer, eutectic metal alloy or glass frit. 
     Therefore, the present invention eliminates the need to form through holes penetrating a silicon substrate as in the prior art, thereby reducing equipment and fabrication costs. Further, the present invention can integrate two types of sensors (for example, a pressure sensor and a motion sensor) in a SiP (System in Package) package so as to achieve low power consumption, low cost and high performance. Furthermore, the package structure of the present invention has a reduced size so as to meet the miniaturization requirement. 
     The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.