Patent Publication Number: US-2023145744-A1

Title: Semiconductor wafer and testing module

Description:
BACKGROUND 
     Field of Invention 
     The present disclosure relates to a semiconductor wafer and a testing module. More particularly, the present disclosure relates to a probe pad. 
     Description of Related Art 
     In semiconductor technology, test element groups (TEGs) can be used to evaluate various circuit characteristics of a semiconductor device. In general, TEG includes a conductive material that connects to a certain circuit desired to be tested. TEG is commonly formed on a scribe line of a semiconductor wafer, and the wafer would be formed into chips after TEG is diced. 
     However, in the dicing operation, chips would suffer cracking or peeling at chip edges because of the conductive or other material in TEG. The cracking or peeling would decrease the dicing performance. Therefore, there is a need to solve the above problems. 
     SUMMARY 
     One aspect of the present disclosure is to provide a semiconductor wafer including a scribe line and a probe pad. The scribe line extends along a first direction. The probe pad is disposed on the scribe line and is configured to contact a probe needle. The probe pad includes a first metal layer, a dielectric layer, and a second metal layer. The dielectric layer is disposed on the first metal layer, in which the dielectric layer includes a first recess and a second recess. The second metal layer is configured to connect to the first metal layer, in which the second metal layer includes a first portion and a second portion, and the first portion and the second portion are separated by a distance in a second direction perpendicular to the first direction. The first portion is disposed on the first recess and a top surface of the dielectric layer to form a first via, and the second portion is disposed on the second recess and the top surface of the dielectric layer to form a second via. 
     In some embodiments, a diameter of the probe needle is greater than the distance between the first portion and the second portion of the second metal layer. 
     In some embodiments, the diameter of the probe needle is in a range from 15 μm to 30 μm. 
     In some embodiments, the distance between the first portion and the second portion is less than 15 μm. 
     In some embodiments, a width in the second direction of the probe pad is in a range from 50 μm to 68 μm. 
     In some embodiments, a height of the second metal layer from the top surface of the dielectric layer to a top surface of the second metal layer is in a range from 3 μm to 6 μm. 
     In some embodiments, each of the first portion and the second portion of the second metal layer has a rectangular shape. 
     One aspect of the present disclosure is to provide a semiconductor wafer including a scribe line and a probe pad. The scribe line extends along a first direction. The probe pad is disposed on the scribe line and is configured to contact a probe needle. The probe pad includes a first metal layer, a dielectric layer, and a second metal layer. The dielectric layer is disposed on the first metal layer, in which the dielectric layer includes a first recess. The second metal layer is configured to connect to the first metal layer, in which the second metal layer includes a first portion and a second portion. The first portion includes a trench exposing the dielectric layer, and the second portion is disposed on the first recess and a top surface of the dielectric layer to form a first via. 
     In some embodiments, the first portion of the second metal layer has a width measured from an outer sidewall to an inner sidewall of the first portion, and the width is in a range from 2 μm to 10 μm. 
     In some embodiments, the first portion of the second metal layer has a width measured from an outer sidewall to an inner sidewall of the first portion, and the width is 5 μm. 
     In some embodiments, the dielectric layer includes a second recess, and the second metal layer includes a third portion disposed on the second recess and the top surface of the dielectric layer to form a second via. 
     In some embodiments, a width in a second direction of the probe pad is in a range from 50 μm to 68 μm, in which the second direction is perpendicular to the first direction. 
     In some embodiments, a height of the second metal layer from the top surface of the dielectric layer to a top surface of the second metal layer is in a range from 3 μm to 6 μm. 
     In some embodiments, a material of the second metal layer includes Al. 
     One aspect of the present disclosure is to provide a testing module including a wafer and a probe head. The wafer includes a scribe line and a probe pad. The scribe line extends along a direction. The probe pad is disposed on the scribe line. The probe pad includes a first metal layer, a dielectric layer, and a second metal layer. The dielectric layer is disposed on the first metal layer, in which the dielectric layer includes a first recess. The second metal layer is configured to connect to the first metal layer, in which the second metal layer includes a first portion and a second portion. The first portion includes a trench exposing the dielectric layer, and the second portion is disposed on the first recess and a top surface of the dielectric layer to form a first via. The probe head includes multiple probe needles and is configured to correspond to a shape of the first portion of the probe pad. 
     In some embodiments, the first portion of the second metal layer has a width measured from an outer sidewall to an inner sidewall of the first portion, and the width is in a range from 2 μm to 10 μm. 
     In some embodiments, a diameter of each of the plurality of probe needles is the same as or smaller than the width of the first portion of the second metal layer. 
     In some embodiments, multiple probe needles are arranged in a rectangular shape. 
     In some embodiments, multiple probe needles are arranged in an array. 
     In some embodiments, the dielectric layer includes a second recess, and the second metal layer includes a third portion disposed on the second recess and the top surface of the dielectric layer to form a second via. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    is a top partial view of a semiconductor wafer in accordance with some embodiments of the present disclosure. 
         FIG.  2    is a cross-sectional view of the semiconductor wafer taken along a line A-A′ in  FIG.  1   . 
         FIG.  3    is a schematic view of a probe head in accordance with some embodiments of the present disclosure. 
         FIG.  4    is a top partial view of a semiconductor wafer in accordance with some embodiments of the present disclosure. 
         FIG.  5 A  is a cross-sectional view of the semiconductor wafer taken along a line B-B′ in  FIG.  4   . 
         FIG.  5 B  is a cross-sectional view of the semiconductor wafer taken along a line C-C′ in  FIG.  4   . 
         FIG.  6    is a schematic view of a probe card in accordance with some embodiments of the present disclosure. 
         FIG.  7 A  to  FIG.  7 E  are bottom views of the probe card in  FIG.  6   . 
         FIG.  8    is a top partial view of a semiconductor wafer in accordance with alternative embodiments of the present disclosure. 
         FIG.  9    is a cross-sectional view of the semiconductor wafer taken along a line D-D′ in  FIG.  8   . 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be understood that the number of any elements/components is merely for illustration, and it does not intend to limit the present disclosure. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     In the package process of manufacturing integrated circuit (IC) chips, a dicing operation could be used to make the IC from a wafer level to a chip level. Blade saw dicing has been widely applied in the dicing operation. However, semiconductor chips would suffer cracking or peeling at chip edges by the blade saw dicing, which decreases the dicing performance in a scribe line. It is understood that the cracking or peeling of semiconductor chips may be caused by a conductive material and/or oxide in a probe pad of a test element group (TEG). For example, an excess of metal content of the probe pad tends to affect the dicing performance. Therefore, there is a demand for a novel structure to solve the problems mentioned above. The present disclosure provides various testing modules that can reduce the metal content of the probe pad, thereby achieving improved dicing performance in the scribe line. 
       FIG.  1    to  FIG.  3    illustrate a first testing module.  FIG.  4   ,  FIG.  5 A ,  FIG.  5 B ,  FIG.  6   , and  FIG.  7 A  to  FIG.  7 E  illustrate a second testing module.  FIG.  8    and  FIG.  9    illustrate an alternative module of the second testing module, in which  FIG.  7 A  to  FIG.  7 E  also can be applied in the alternative module. 
       FIG.  1    to  FIG.  3    illustrate a first testing module. With reference to  FIG.  1   ,  FIG.  1    is a top partial view of a semiconductor wafer  100  in accordance with some embodiments of the present disclosure. The semiconductor wafer  100  includes a scribe line  110  and a probe pad  120 . The scribe line  110  extends along a first direction d 1 . The probe pad  120  is disposed on the scribe line  110  and is configured to contact a probe needle  310  of a probe head  300  (see  FIG.  3   ). As shown in  FIG.  1   , the probe pad  120  includes a first portion  230   a  and a second portion  230   b , and the first portion  230   a  and the second portion  230   b  are arranged in a second direction d 2  perpendicular to the first direction d 1 . In some embodiments, a width W 1  in the second direction d 2  of the probe pad  120  is in a range from 50 μm to 68 μm, for example, 55, 60, or 65 μm. The detailed structure of the probe pad  120  will be described in  FIG.  2    below, and the detailed structure of the probe head  300  will be described in  FIG.  3    below. 
     With reference to  FIG.  2   ,  FIG.  2    is a cross-sectional view of the semiconductor wafer  100  taken along a line A-A′ in  FIG.  1   . As shown in  FIG.  2   , the probe pad  120  includes a first metal layer  210 , a dielectric layer  220 , and a second metal layer  230 . The first metal layer  210  can also be referred to as a down layer metal. The first metal layer  210  includes any component prepared to be tested. For example, a resistance of a doped region, a junction leakage, a resistance of source/drain resistance, and so on could be tested by the component. The dielectric layer  220  is disposed on the first metal layer  210 , in which the dielectric layer  220  includes a first recess  222   a  and a second recess  222   b . Specifically, the first recess  222   a  exposes a top surface  212   a  of the first metal layer  210  and forms an inner surface  224   a . Similarly, the second recess  222   b  exposes a top surface  212   b  of the first metal layer  210  and forms an inner surface  224   b . The top surface  212   a  and the top surface  212   b  of the first metal layer  210  have a coplanar surface. 
     Still refer to  FIG.  2   . The second metal layer  230  is configured to connect to the first metal layer  210 . In some embodiments, a material of the second metal layer  230  includes Al. The second metal layer  230  includes the first portion  230   a  and the second portion  230   b , and the first portion  230   a  and the second portion  230   b  are separated by a distance D 1  in the second direction d 2 . Specifically, the distance D 1  is measured from a sidewall  232   a  of the first portion  230   a  to a sidewall  232   b  of the second portion  230   b , as shown in  FIG.  1    and  FIG.  2   . In some embodiments, the sidewall  232   a  of the first portion  230   a  is parallel to the sidewall  232   b  of the second portion  230   b . In some embodiments, the distance D 1  is less than 15 μm, for example, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, or 3 μm. The first portion  230   a  of the second metal layer  230  is disposed on the first recess  222   a  and a top surface  226  of the dielectric layer  220  to form a first via  250   a . The second portion  230   b  of the second metal layer  230  is disposed on the second recess  222   b  and the top surface  226  of the dielectric layer  220  to form a second via  250   b . More specifically, a lower part of the first portion  230   a  is disposed on the top surface  212   a  of the first metal layer  210  and the inner sidewall  224   a  of the first recess  222   a . A lower part of the second portion  230   b  is disposed on the top surface  212   b  of the first metal layer  210  and the inner sidewall  224   b  of the second recess  222   b . A height H 1  of the first portion  230   a  from the top surface  226  of the dielectric layer  220  to a top surface  234   a  of the first portion  230   a  is in a range from 3 μm to 6 μm, for example, 3.5, 4, 4.5, 5.5 μm. A height H 2  of the second portion  230   b  from the top surface  226  of the dielectric layer  220  to a top surface  234   b  of the second portion  230   b  is in a range from 3 μm to 6 μm, for example, 3.5, 4, 4.5, 5.5 μm. In some embodiments, the height H 1  is the same as the height H 2 . In some embodiments, each of the first portion  230   a  and the second portion  230   b  of the second metal layer  230  has a rectangular shape, as shown in  FIG.  1   . 
     It is noticed that  FIG.  1    illustrates the first portion  230   a  and the second portion  230   b  of the second metal layer  230  of the probe pad  120  for clarity, and the detailed structure of the probe pad  120  please refer to  FIG.  2   . It should be understood that the first metal layer  210  could be any component in the IC depending on the design requirement of the semiconductor wafer  100 , and the characteristics of the component would be tested through the second metal layer  230 . 
     With reference to  FIG.  3   ,  FIG.  3    is a schematic view of a probe head  300  in accordance with some embodiments of the present disclosure. The probe head  300  includes a probe needle  310 . A diameter D 2  of the probe needle  310  is greater than the distance D 1  between the first portion  230   a  and the second portion  230   b  of the second metal layer  230 . In some embodiments, the diameter D 2  of the probe needle  310  is in a range from 15 μm to 30 μm, for example, 16, 18, 20, 22, 24, 26, 28 μm. 
     In a method of the first testing module, the probe head  300  moves along the scribe line  110 , in which the probe needle  310  of the probe head  300  contacts a part of the first portion  230   a  and a part of the second portion  230   b  of the second metal layer  230 . For example, the second metal layer  230  adjacent to the distance D 1  is contacted by the probe needle  310 . Therefore, the characteristics of the component in the first metal layer  210  would be tested through the second metal layer  230 . After testing the component in the first metal layer  210 , the dicing operation is performed along the scribe line  110 . The semiconductor wafer  100  has the distance D 1  between the first portion  230   a  and the second portion  230   b  of the second metal layer  230 , and so it provides reduced the metal content of the probe pad  120  during the dicing operation, thereby improving dicing performance in the scribe line  110 . 
       FIG.  4   ,  FIG.  5 A ,  FIG.  5 B ,  FIG.  6    and  FIG.  7 A  to  FIG.  7 E  illustrate a second testing module. With reference to  FIG.  4   ,  FIG.  4    is a top partial view of a semiconductor wafer  400  in accordance with some embodiments of the present disclosure. The semiconductor wafer  400  includes a scribe line  410  and a probe pad  420 . The scribe line  410  extends along the first direction d 1 . The probe pad  420  is disposed on the scribe line  410  and is configured to contact a probe needle  610  of a probe head  620  (see  FIG.  6    and  FIG.  7 A  to  FIG.  7 E ). As shown in  FIG.  4   , the probe pad  420  includes a first portion  530   a  and a second portion  530   b . In some embodiments, each of the first portion  530   a  and the second portion  530   b  of the second metal layer  530  has a rectangular shape, and the first portion  530   a  is greater than the second portion  530   b . In some embodiments, each of the first portion  530   a  and the second portion  530   b  of the second metal layer  530  has a ring shape, and the first portion  530   a  is greater than the second portion  530   b . In some embodiments, the width W 1  in the second direction d 2  of the probe pad  120  is in a range from 50 μm to 68 μm, for example, 55, 60, or 65 μm. The detailed structure of the probe pad  420  will be described in  FIG.  5 A  and  FIG.  5 B  below, and the detailed structure of the probe head  620  will be described in  FIG.  6    and  FIG.  7 A  to  FIG.  7 E  below. 
       FIG.  5 A  is a cross-sectional view of the semiconductor wafer  400  taken along a line B-B′ in  FIG.  4   , and  FIG.  5 B  is a cross-sectional view of the semiconductor wafer  400  taken along a line C-C′ in  FIG.  4   . As shown in  FIG.  5 A  and  FIG.  5 B , the probe pad  420  includes a first metal layer  510 , a dielectric layer  520 , and a second metal layer  530 . The first metal layer  510  includes the first portion  530   a  (see  FIG.  4    and  FIG.  5 A ) and the second portion  530   b  (see  FIG.  4    and  FIG.  5 B ). The first metal layer  510  can also be referred to as a down layer metal. The first metal layer  510  includes any component prepares to be tested. For example, a resistance of a doped region, a junction leakage, a resistance of source/drain resistance, and so on could be tested by the component. The dielectric layer  520  is disposed on the first metal layer  510 , in which the dielectric layer  520  includes a first recess  522 , as shown in  FIG.  5 B . Specifically, the first recess  522  exposes a top surface  512  of the first metal layer  510  and forms an inner surface  524 . The second portion  530   b  of the first metal layer  510  is configured to connect to the first metal layer  510 . In some embodiments, a material of the second metal layer  530  includes Al. The second portion  530   b  is disposed on the first recess  522  and a top surface  526  of the dielectric layer  520  to form a first via  550 . 
     Please refer to  FIG.  4    and  FIG.  5 A , the first portion  530   a  of the second metal layer  530  includes a trench  540 , and the trench  540  exposes the top surface  526  of the dielectric layer  520  and an inner sidewall  532  of the first portion  530   a . The first portion  530   a  of the second metal layer  530  has a width W 2  measured from an outer sidewall  534  to the inner sidewall  532  of the first portion  530   a . In some embodiments, the width W 2  is in a range from 2 μm to 10 μm, for example, 3, 4, 5, 6, 7, 8, or 9 μm. 
     Still refer to  FIG.  4   . The probe pad  420  further includes a third portion  530   c . It should be understood that the third portion  530   c  is the same as the second portion  530   b  of the probe pad  420 , and the cross-sectional view of the third portion  530   c  can refer to  FIG.  5 B . In other words, the dielectric layer  520  further includes a second recess, and the third portion  530   c  is disposed on the second recess and the top surface  526  of the dielectric layer  520  to form a second via. In addition, the position of the second portion  530   b  and the third portion  530   c  are arranged connecting to outer sidewall  534  of the first portion  530   a  of the probe pad  530 . 
     Please refer to  FIG.  5 A  again. A height H 3  of the first portion  530   a  from the top surface  526  of the dielectric layer  520  to a top surface  536  of the first portion  530   a  is in a range from 3 μm to 6 μm, for example, 3.5, 4, 4.5, 5.5 μm. Please refer to  FIG.  5 B  again. A height H 4  of the second portion  530   b  from the top surface  526  of the dielectric layer  520  to a top surface  538  of the second portion  530   b  is in a range from 3 μm to 6 μm, for example, 3.5, 4, 4.5, 5.5 μm. In some embodiments, the height H 3  is the same as the height H 4 . 
     With reference to  FIG.  6   ,  FIG.  6    is a schematic view of a probe card  600  in accordance with some embodiments of the present disclosure. The probe card includes the probe head  620 , the probe head  620  includes multiple probe needles  610  disposed on the probe head  620 . The probe head  620  has a planar surface. Multiple probe needles  610  are configured to correspond to a shape of the first portion  530   a  of the probe pad  420 . A diameter of each of multiple probe needles  610  is the same as or smaller than the width W 2  of the first portion  530   a  of the second metal layer  530 . Specifically, the probe needles  610  are configured to contact the first portion  530   a  of the probe pad  420  to test the characteristics of the component in the semiconductor wafer  400 . 
     In a method of the second testing module, the probe head  620  of the probe head  600  aligns with the first portion  530   a  of the second metal layer  530 , in which the probe needled  610  of the probe head  600  contacts a part of the first portion  530   a  of the second metal layer  530 . Due to the first portion  530   a  of the second metal layer  530  connects to the second portion  530   b  and/or the third portion of the second metal layer  530 , therefore, the characteristics of the component in the first metal layer  510  would be tested through the second metal layer  530 . After testing the component in the first metal layer  510 , the dicing operation is performed along the scribe line  410 . The semiconductor wafer  400  has the trench  540  in the first portion  530   a  of the second metal layer  530 , and so it provides reduced the metal content of the probe pad  420  during the dicing operation, thereby improving dicing performance in the scribe line  410 . 
     With reference to  FIG.  7 A  to  FIG.  7 E ,  FIG.  7 A  to  FIG.  7 E  are bottom views of the probe card  600  of in  FIG.  6   . Specifically, the probe card  600  can be any one of the probe card  600   a  to the probe card  600   e  in  FIG.  7 A  to  FIG.  7 E . The bottom views include the probe needles  610  and the probe head  620  of the probe card  600 . 
     In  FIG.  7 A  to  FIG.  7 C , the probe head  620  has a rectangular shape. In  FIG.  7 A , the probe needles  610  are disposed on the four corners of the probe head  620 . In  FIG.  7 B , the probe needles  610  are disposed along the four sidewalls of the probe head  620 . In  FIG.  7 C , the probe needles  610  are disposed on a whole surface of the probe head  620 . 
     In  FIG.  7 D  and  FIG.  7 E , the probe head  620  has an inner rectangular shape and an outer rectangular shape, and the probe needles  610  are disposed between the inner rectangular and the outer rectangular. In  FIG.  7 D , the probe needles  610  are disposed on the four corners of the probe head  620 . In  FIG.  7 E , the probe needles  610  are disposed along the four sidewalls of the probe head  620 . 
     In some embodiments, multiple probe needles  610  are arranged in a rectangular shape, as shown in  FIG.  7 A ,  FIG.  7 B ,  FIG.  7 D , and  FIG.  7 E . In some embodiments, multiple probe needles  610  are arranged in an array, as shown in  FIG.  7 C . It should be noticed that the amount of the probe needles  610  illustrated in  FIG.  7 B ,  FIG.  7 C , and  FIG.  7 E  is merely illustrated for clarity, and more number of the probe needles  610  is also included in the present disclosure. The arrangement of the probe needles  610  is to contact the first portion  530   a  the probe pad  420  to test the characteristics of the component in the semiconductor wafer  400 , and so the amount of the probe needle  610  is not limited. For example, the amount of the probe needle  610  can be only one, two, or three. In other examples, if the probe head  620  has a ring shape, the probe head  620  also has a ring shape. 
       FIG.  8    and  FIG.  9    illustrate an alternative module of the second testing module, in which  FIG.  7 A  to  FIG.  7 E  also can be applied in the alternative module.  FIG.  8    is a top partial view of a semiconductor wafer  800  in accordance with alternative embodiments of the present disclosure, and  FIG.  9    is a cross-sectional view of the semiconductor wafer  800  taken along a line D-D′ in  FIG.  8   . The difference between the semiconductor wafer  400  in  FIG.  4    and the semiconductor wafer  800  in  FIG.  8    is that the amount of the via. Specifically, the semiconductor wafer  800  further includes a fourth portion  930   d  and a fifth portion  930   e  of the probe pad  820 . Similar features are labeled by similar numerical references and descriptions of the similar features are not repeated herein. In addition, the position of the second portion  930   b , the third portion  930   c , the fourth portion  930   d , and the fifth portion  930   e  are arranged connecting to the fourth corners of the first portion  930   a  of the probe pad  820 . 
     In the first testing module, the semiconductor wafer  100  has the distance D 1  between the first portion  230   a  and the second portion  230   b  of the second metal layer  230 . In the second testing module, the semiconductor wafer  400  has the trench  540  of the first portion  530   a  of the second metal layer  530 . In the third testing module, the semiconductor wafer  800  has the trench  940  in the first portion  930   a  of the second metal layer  930 . Therefore, the various testing modules of the present disclosure can reduce the metal content of the probe pad, thereby achieving improved dicing performance in the scribe line. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.