Patent Publication Number: US-7583557-B2

Title: Multi-port memory device with serial input/output interface and control method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   The present invention claims priority of Korean patent application number 10-2006-0033766, filed on Apr. 13, 2006, which is incorporated by reference in its entirety. 
   BACKGROUND OF THE INVENTION 
   The present invention relates to a design technique for a semiconductor device; and, more particularly, to an apparatus and method for controlling a mode register determining an operation mode of a multi-port memory device with serial input/output interface for performing multiple concurrent processes. 
   Generally, a memory device such as a random access memory has one port, i.e., a set including plural input/output pins. That is, for interchanging data with an external device such as a chipset, the memory device include one pin set constituted with plural input/output pins. This single-port memory device uses a parallel input/output interface that multi-bit data are parallel transmitted through each line coupled to each of the plural input/output pins. Accordingly, for increasing an operation speed, plural data are parallel interchanged with the external device. 
   The I/O interface is an electrical and mechanical scheme to connect unit devices having different functions through signal lines and transmit transmission/reception data precisely. An I/O interface, described below, must have the same precision. The signal line is a bus to transmit an address signal, a data signal, and a control signal. A signal line, described below, will be referred as a bus. 
   The parallel I/O interface has high data processing efficiency (speed) because it can simultaneously transmit multi-bit data through a plurality of buses. Therefore, the parallel I/O interface is widely used in a short distance transmission that requires a high speed. In the parallel I/O interface, however, the number of buses for transmitting I/O data increases. Consequently, as distance increases, the manufacturing cost increases. Due to the limitation of the single port, a plurality of memory devices are independently configured so as to support various multi-media functions in terms of hardware of a multi-media system. When an operation for a certain function is carried out, an operation for another function cannot be concurrently carried out. 
   Considering the disadvantage of the parallel I/O interface, many attempts to change the parallel I/O interface into serial I/O interface have been made. Also, considering compatible expansion with devices having other serial I/O interfaces, the change to serial I/O interface in an I/O environment of the semiconductor memory device is required. Moreover, appliance devices for audio and video are embedded into display devices, such as a high definition television (HDTV) and a liquid crystal display (LCD) TV. Because these appliance devices require independent data processing, there is a demand for multi-port memory devices having a serial I/O interface using a plurality of ports. 
   Accordingly, there is suggested a semiconductor memory device described in a commonly owned copending application, U.S. Ser. No. 11/528,970, filed on Sep. 27, 2006, entitled “MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT/OUTPUT INTERFACE”. 
     FIG. 1  illustrates a block diagram of a conventional semiconductor memory device disclosed in a commonly owned copending application, U.S. Ser. No. 11/528,970, filed on Sep. 27, 2006, entitled “MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT/OUTPUT INTERFACE”, which is incorporated herein by reference. 
   For convenience of explanation, the multi-port memory device having four ports and eight banks is illustrated. Particularly, it is assumed that the multi-port memory device has a 16-bit data frame and performs a 64-bit prefetch operation. 
   As shown, the multi-port memory device includes first to fourth ports PORT 0  and PORT 3 , first to eighth banks BANK 0  to BANK 7 , first and second global input/output (I/O) data buses GIO_OUT and GIO_IN, and first to eighth bank control units BC 0  to BC 7 . 
   Each of the first to fourth ports PORT 0  and PORT 3  located at a center of the multi-port memory device is arranged in a row direction, and performs a serial data communication with its own external device independent of each other. The first to eighth banks BANK 0  to BANK 7  are divided into upper banks BANK 0  to BANK 3  and lower banks BANK 4  to BANK 7  based on the first to fourth ports PORT 0  to PORT 3  and arranged in the row direction. 
   The first global I/O bus GIO_OUT is arranged in the row direction between the upper banks BANK 0  to BANK 3  and the first to fourth ports PORT 0  to PORT 3 , and transmits output data in parallel. The second global I/O bus GIO_IN is arranged in the row direction between the lower banks BANK 4  to BANK 7  and the first to fourth ports PORT 0  to PORT 3 , and transmits input data in parallel. 
   The first to eighth bank control units BC 0  to BC 7  control a signal transmission between the first and second global I/O buses GIO_OUT and GIO_IN and the first to eighth banks BANK 0  to BANK 7 . 
     FIG. 2  illustrates a detailed block diagram of the first bank BANK 0  shown in  FIG. 1 . 
   As shown, each bank, e.g., the first bank BANK 0 , includes a memory cell array  10 , row &amp; column decoders  11  and  12 , a write driver (W/D)  13 , a data bus sense amplifier (DBSA)  14 , and an equalizer (not shown). The other banks BANK 1  to BANK 7  have the same structure with that of the first bank BANK 0 . 
   The memory cell array  10  includes a plurality of memory cells MCs arranged with an N by M matrix form, M and N being positive integers. Each of the row &amp; column decoders  11  and  12  selects one of the memory cells MCs by a row and a column. 
   The first to eighth banks BANK 0  to BANK 7  having such a constitution divide the multi-port memory device by half based on the first to fourth ports PORT 0  to PORT 3  so that the upper banks BANK 0  to BANK 3  and the lower banks BANK 4  to BANK 7  are symmetrically located at the row direction. 
     FIG. 3  illustrates a detailed block diagram of the first port PORT 0  shown in  FIG. 1 . 
   Each port PORT 0  to PORT 3  located at the center of the multi-port memory device is connected to the first and second global I/O data buses GIO_OUT and GIO_IN so as to independently access all banks. The other ports PORT 1  to PORT 3  have the same structure with that of the first port PORT 0 , and thus, the first port PORT 0  is explained as an example. 
   The first port PORT 0  includes a reception unit  41  and a transmission unit  42 . The reception unit  41  receives signals inputted from the external devices (hereinafter, referred to as “input signals”) through a reception pad RX, and the transmission unit  42  outputs signals outputted from the first to eighth banks (hereinafter, referred to as “output signals”) through a transmission pad TX. The reception unit  41  and the transmission unit  42  operate independently so that the input signals and the output signals are simultaneously transferred. 
   The reception unit  41  deserializes 20-bit input signals, which are inputted from the external devices through the reception pad RX in series, to convert and output the deserialized input signals as 26-bit valid signals effective for an operation of the DRAM device. Herein, the 26-bit valid signals include an 8-bit port/bank selection signal group P 0 _BK&lt; 0 : 7 &gt;, and a 18-bit input valid data signal group P 0 _RX&lt; 0 : 17 &gt;. The 18-bit input valid data signal group P 0 _RX&lt; 0 : 17 &gt; includes a command flag signal, a row address strobe/data mask (RAS/DM) signal, and 16-bit command/address/data signals. Herein, the 16-bit command/address/data signals may be addresses, commands or data signals. 
     FIGS. 4A to 4F  illustrate a frame form of the input signals input to the first port shown in  FIG. 3 .  FIG. 4A  is a basic frame form,  FIG. 4B  is a write command frame form,  FIG. 4C  is a write data frame form,  FIG. 4D  is a read command frame form,  FIG. 4E  is a read data frame form, and  FIG. 4F  is a command frame form. 
   As an example, the write command frame and the write data frame shown in  FIGS. 4B and 4C  are described in detail. 
   Referring to  FIG. 4B , the write command frame is a unit of 20-bit serialized signals inputted from the external devices. 18 th  and 19 th  bits PHY among the 20-bit serialized signals correspond to a physical link coding bit, a 17 th  bit CMD means a command start point, a 16 th  bit ACT means an internal active state, a 15 th  bit WT corresponds to an internal write command, and a 14 th  bit PCG means an internal inactive state. For example, during a normal write operation, 17 th  to 14 th  bits become “1010”. During an auto-precharge write operation, 17 th  to 14 th  bits become “1011”. 13 th  to 10 th  bits UDM are used as an upper-byte write data mask signal of write data applied over four clocks, 9 th  to 6 th  bits BANK mean bank data written during a write operation, and the 5 th  to 0 th  bits COLUMN ADDRESS mean a column address. 
   Referring to  FIG. 4C , the write data frame is 16-bit write data applied over four clocks after the write command frame shown in  FIG. 5B  are inputted. Herein, a 17 th  bit CMD becomes a logic level “LOW”, a 16 th  bit LDM are used as a lower-byte write data mask signal of the write data, and each of 15 th  to 8 th  bits UPPER BYTE and 7 th  to 0 th  bits LOWER BYTE means an upper byte and a lower byte of the write data, respectively. 
   Referring to  FIGS. 3 to 4F , detailed constitutions of the reception unit  41  and the transmission unit  42  are described. 
   The reception unit  41  includes a parallelizer  411 , a command generating unit  412 , a bank address generating unit  413 , a bank address output unit  414 , and an input valid data output unit  415 . 
   The parallelizer  411  deserializes the 20-bit input signals (one frame) inputted from the external devices through the reception pad RX in series and outputs the deserialized input signals as 20-bit parallel signals. 
   The command generating unit  412  determines an operation of the 20-bit parallel signals by using the 17 th  bit CMD of the 20-bit parallel signals outputted from the parallelizer  411 . That is, if the 17 th  bit CMD of the write command frame shown in  FIG. 4B  is a logic level “LOW”, the command generating unit  412  determines that the 20-bit parallel signals performed a write operation; and if the 17 th  bit CMD is a logic level “HIGH”, the command generating unit  412  determines that the 20-bit parallel signals performed a read operation. Further, the command generating unit  412  outputs a bank information bit utilized as bank data of the 20-bit parallel signals. Herein, the number of the bank information bit is three because the number of banks is eight, and this bit is included in a frame payload shown in  FIG. 4A . 
   The bank address generating unit  413  outputs 8-bit bank addresses for selecting a corresponding bank of the first to eighth banks BANK 0  to BANK 7  based on the 3-bit bank information bit. The bank address generating unit  413  may include a 3 by 8 decoder which outputs 8-bit output signals by receiving 3-bit input signals. 
   The bank address output unit  414  outputs the 8-bit port/bank selection signal group P 0 _BK&lt; 0 : 7 &gt; to the second global I/O data bus GIO_IN based on the 8-bit bank addresses inputted from the bank address generating unit  413 . The bank address output unit  414  may include a plurality of output drivers. 
   The input valid data output unit  415  outputs the 18-bit input valid data signal group P 0 _RX&lt; 0 : 17 &gt; to the second global I/O data bus GIO_IN based on output signals from the parallelizer  411 . The input valid data output unit  415  may include a plurality of output drivers. 
   The transmission unit  42  receives and serializes as an output a valid data signal group P 0 _DATA&lt; 0 : 15 &gt; inputted from the banks through the first global data bus GIO_OUT in parallel to output the serialized signals to the transmission pad TX. 
   In detail, the transmission unit  42  includes a serializer  421  and an output valid data input unit  422 . 
   The output valid data input unit  422  receives the 16-bit output valid data signal group P 0 _DATA&lt; 0 : 15 &gt; inputted from the banks through the first global data bus GIO_OUT, and packets them for a transfer protocol under the control of the command generating unit  412 , i.e., according to the read or write operation. As a result, 20-bit frame output signals are outputted. The output valid data input unit  422  may include a plurality of input drivers. 
   The serializer  421  serializes the 20-bit frame output signals inputted from the output valid data input unit  422  in parallel, and outputs the serialized signals to the transmission pad TX in series. 
   Meanwhile, the first global I/O data bus GIO_OUT includes 64-bit buses, i.e., 16 (the number of data bits) by 4 (the number of ports), for transferring the output valid data signal group Pi_DATA&lt; 0 : 15 &gt; inputted from the banks to each port independently. 
   The second global I/O data bus GIO_IN includes 104-bit buses, i.e., 26 (the number of data bits) by 4 (the number of ports), for transferring the input valid data signal group Pi_RX&lt; 0 : 17 &gt; and the port/bank selection signal group Pi_BK&lt; 0 : 7 &gt; inputted from the ports to each bank independently. Herein, the “i” corresponds to the number of ports as an integer from 0 to 3. 
   The first and second global I/O data buses GIO_OUT and GIO_IN are connected to a plurality of local data buses for transferring signals with each bank control unit or each port. The local data buses connect the first and second global I/O data buses GIO_OUT and GIO_IN to the first to eighth bank control units BC 0  to BC 7  or the first to fourth ports PORT 0  to PORT 3 . For convenience of explanation, the local data buses are classified into first to fourth local data buses. 
     FIG. 5  illustrates a circuit diagram of the first bank control unit BC 0  shown in  FIG. 1 . Each of the first to eighth bank control units BC 0  to BC 7  is arranged for a corresponding one of the first to eighth banks BANK 0  to BANK 7  to thereby control transferring signals between the corresponding bank and each port PORT 0  to PORT 3 . The bank control units BC 1  to BC 7  have the same structure with that of the first bank control unit BC 0 , and thus, the first bank control unit BC 0  is explained as an example. 
   Referring to  FIG. 5 , the first bank control unit BC 0  includes a parallelizer  61 , a serializer  62 , a state machine unit  63 , an input signal state discrimination unit  64 , a bank selection unit  65 , and a port selection unit  66 . 
   The bank selection unit  65  selects one signal group of a plurality of the 18-bit input valid data signal groups Pi_RX&lt; 0 : 17 &gt; outputted from each port in response to a 4-bit bank selection signal group BK 0 _P&lt; 0 : 3 &gt; and transfers it as a 18-bit bank valid data signal group B 0 _RX&lt; 0 : 17 &gt; to the first bank BANK 0 . Herein, the 4-bit bank selection signal group BK 0 _P&lt; 0 : 3 &gt; is part of the 8-bit port/bank selection signal group Pi—BK&lt; 0 : 7 &gt;. That is, the bank selection unit  65  receives 22-bit signals including the 4-bit bank selection signal group BK 0 _P&lt; 0 : 3 &gt; and the 18-bit input valid data signal group Pi_RX&lt; 0 : 17 &gt; from all ports through the second global I/O data bus GIO_IN to thereby output the 18-bit bank valid data signal group B 0 _RX&lt; 0 : 17 &gt; corresponding to the first bank BANK 0 . 
   A 16-bit signal group of the 18-bit bank valid data signal group B 0 _RX&lt; 0 : 17 &gt; is used as data, addresses or commands such as a bank mode determination signal, a 1-bit signal is used as an active flag signal, and a residuary 1-bit signal is used as a command flag signal for discriminating whether the 16-bit signal group is data signals or not. For instance, a seventeenth bank valid data signal B 0 _RX&lt; 16 &gt; of the 18-bit bank valid data signal group B 0 _RX&lt; 0 : 17 &gt; is used as the active flag signal and an eighteenth bank valid data signal B 0 _RX&lt; 17 &gt;, i.e., a most significant bit (MSB), is used as the command flag signal. Herein, the seventeenth bank valid data signal B 0 _RX&lt; 16 &gt; is used as the row address strobe/data mask (RAS/DM) signal, and the eighteenth bank valid data signal B 0 _RX&lt; 17 &gt; is used as an enable signal of the state machine unit  63 . For reference, the RAS signal is an initial signal of the DRAM device as a chip enable signal for controlling an operation of the DRAM device. 
   The input signal state discrimination unit  64  receives the 18-bit bank valid data signal group B 0 _RX&lt; 0 : 17 &gt; and discriminates whether it is data, addresses or commands. In detail, the input signal state discrimination unit  64  discriminates whether the 16-bit signal group B 0 _RX&lt; 0 : 15 &gt; is data, addresses or commands based on status of the most significant bit (MSB) B 0 _RX&lt; 17 &gt;. When the 16-bit signal group B 0 _RX&lt; 0 : 15 &gt; is discriminated as data, the 16-bit signal group B 0 _RX&lt; 0 : 15 &gt; is transferred to the parallelizer  61 . Otherwise, the 18-bit bank valid data signal group B 0 _RX&lt; 0 : 17 &gt; is transferred to the state machine unit  63 . 
   The state machine unit  63  outputs an address/command signal ADD/CON based on the 18-bit bank valid data signal group B 0 _RX&lt; 0 : 17 &gt;. The address/command signal ADD/CON controls the operation of the DRAM device and includes internal command signals, internal address signals, and internal control signals. The internal command signals include an internal active signal ACT, an internal inactive state PCG, an internal read command signal READ, and an internal write command signal WRITE. The internal address signals include a row address XADD and a column address YADD. The internal control signals include an input data strobe signal such as DSTROBE 16 &lt; 0 : 3 &gt; and DSTROBE 64 , a driving enable signal group DRVEN_P&lt; 0 : 3 &gt;, a pipe input strobe signal PINSTROBE, and a pipe output control signal group POUT&lt; 0 : 3 &gt;. 
   The parallelizer  61  converts the 16-bit signal group B 0 _RX&lt; 0 : 15 &gt; into 64-bit parallel output data and outputs it to the write driver (W/D)  13  of the corresponding bank. Herein, though the 16-bit signal group B 0 _RX&lt; 0 : 15 &gt; has a parallel form, it has to be converted into the 64-bit parallel output data because each memory cell of the banks performs a read or write operation with 64-bit data. 
   The serializer  62  converts 64-bit data signals outputted from the plurality of the DBSAs  14  into a 16-bit output data signal group DO&lt; 0 : 15 &gt;_B 0  in response to the pipe input strobe signal PINSTROBE and the pipe output control signal group POUT&lt; 0 : 3 &gt;. 
   The port selection unit  66  sequentially receives the 16-bit output data signal group DO&lt; 0 : 15 &gt;_B 0  outputted from the serializer  62  in units of 16-bit and outputs the valid data signal group Pi_DATA&lt; 0 : 15 &gt; to a corresponding port selected by decoding a 4-bit port selection signal group BRX_P&lt; 0 : 3 &gt;. Herein, the 4-bit port selection signal group BRX_P&lt; 0 : 3 &gt; is parts of the 8-bit port/bank selection signal group Pi_BK&lt; 0 : 7 &gt;. 
   The port selection unit  66  has plural demultiplexers. Each demultiplexer is allocated to each port so as to independently perform a signal transmission with all ports PORT 0  to PORT 3 . Further, each demultiplexer includes sixteen drivers for processing the 16-bit output data signal group DO&lt; 0 : 15 &gt;. 
   Each driver may includes a tri-state buffer for preventing any collision because all banks BANK 0  to BANK 7  hold the first global data bus GIO_OUT in common, wherein the first global data bus GIO_OUT transmits signals outputted from each bank BANK 0  to BANK 7  to each of the ports PORT 0  to PORT 3 . 
     FIG. 6  illustrates a circuit diagram of the state machine unit  63  shown in  FIG. 5 . 
   The state machine unit  63  includes a command generating unit  631 , an input data strobe generating unit  632 , a row address generating unit  633 , a column address generating unit  634 , a read data pipe controller  635 , and a data output controller  636 . 
   The command generating unit  631  is enabled in response to two MSB bank valid data signals B 0 _RX&lt; 16 : 17 &gt;, and generates the internal command signals such as the internal active signal ACT, the internal inactive state PCG, the internal read command signal READ, and the internal write command signal WRITE by decoding the other 16-bit signal group B 0 _RX&lt; 0 : 15 &gt;. The command generating unit  631  includes a decoder for generating 2 n  digital signals by receiving n digital signals, n being a positive integer. 
   The input data strobe generating unit  632  generates the input data strobe signal such as DSTROBE 16 &lt; 0 : 3 &gt; and DSTROBE 64  in response to the eighteenth bank valid data signal B 0 _RX&lt; 17 &gt; and the internal write command signal WRITE. Herein, the input data strobe signal such as DSTROBE 16 &lt; 0 : 3 &gt; and DSTROBE 64  are control signals for controlling an operation of the parallelizer  61 . 
   The row address generating unit  633  receives the bank valid data signal group BRX&lt; 0 :m&gt; to generate a row address group XADD&lt; 0 :m&gt; in response to the internal active signal ACT, m being a positive integer. 
   The column address generating unit  634  receives the bank valid data signal group BRX&lt; 0 :n&gt; to generate a column address group YADD&lt; 0 :n&gt; in response to the internal read command signal READ and the internal write command signal WRITE, n being a positive integer. 
   The read data pipe controller  635  generates the pipe input strobe signal PINSTROBE and the pipe output control signal group POUT&lt; 0 : 3 &gt; in response to the internal read command signal READ. 
   The data output controller  636  receives the port selection signal group BRX_P&lt; 0 : 3 &gt; to generate the driving enable signal group DRVEN_P&lt; 0 : 3 &gt; in response to the internal read command signal READ. Herein, the driving enable signal group DRVEN_P&lt; 0 : 3 &gt; is a control signal for controlling an operation of the port selection unit  66 . 
   Hereinafter, referring to  FIGS. 1 to 6 , an operation of the multi-port memory device in accordance with the present invention will be explained in detail. 
     FIG. 7  illustrates a signal diagram of a signal input path from the ports to the banks, and  FIG. 8  illustrates a signal diagram of a signal output path from the banks to the ports. Herein, an 8-bit port/bank selection signal group Pi_BK&lt; 0 : 7 &gt; (i=0,1,2,3) is converted into a 4-bit bank selection signal group BKi_P&lt; 0 : 3 &gt; (i=0,1,2,3,4,5,6,7,8). 
   First, the signal input path from the first port PORT 0  to the second bank BANK 1  is described. 
   Referring to  FIG. 7 , the 20-bit input signals are inputted from the external devices to each port through the reception pad RX in series. Each port converts the 20-bit input signals into the 26-bit valid signals including the 8-bit port/bank selection signal group Pi_BK&lt; 0 : 7 &gt; and the 18-bit input valid data signal group Pi_RX&lt; 0 : 17 &gt;, and outputs them to the second global I/O data bus GIO_IN. At this time, the second global I/O data bus GIO_IN is connected to the other banks, i.e., BANK 0  and BANK 2  to BANK 7 , as well as the second bank BANK 1  through a second local I/O data bus LIO_BIN shown in  FIG. 2 . As a result, the 26-bit valid signals are transferred to the bank selection unit  65  of all bank control units BC 0  to BC 7  through the second local I/O data bus LIO_BIN. 
   At this time, because the 18-bit input valid data signal group P 0 _RX&lt; 0 : 17 &gt; among 26-bit valid signals outputted from the first port PORT 0  is only transferred to the second bank BANK 1 , the 8-bit port/bank selection signal group P 0 _BK&lt; 0 : 7 &gt; is required to prevent the 18-bit input valid data signal group P 0 _RX&lt; 0 : 17 &gt; from being transferred to the other banks BANK 0  and BANK 2  to BANK 7 . 
   The port/bank selection signal group Pi_BK&lt; 0 : 7 &gt; and the input valid data signal group Pi_RX&lt; 0 : 17 &gt; are contained in the 26-bit valid signals provided from the each port. Both the port/bank selection signal group Pi_BK&lt; 0 : 7 &gt; and the input valid data signal group Pi_RX&lt; 0 : 17 &gt; are inputted to the bank selection unit  65  of each bank through the second global data bus GIO_IN. 
   The bank selection unit  65  of the second bank control unit BC 1  receives the 18-bit input valid data signal group P 0 _RX&lt; 0 : 17 &gt; in response to the 4-bit bank selection signal group BK 1 _P&lt; 0 : 3 &gt;, and transfers it as the 18-bit bank valid data signal group B 1 _RX&lt; 0 : 17 &gt; to the second bank BANK 1 . At this time, the other bank selection signal groups BK 0 _P&lt; 0 : 3 &gt; and BK 2 _P&lt; 0 : 3 &gt; to BK 7 _P&lt; 0 : 3 &gt; are inactivated so that the bank selection unit  65  of the other bank control units, i.e., BC 0  and BC 2  to BC 7 , does not operate. As a result, the 18-bit input valid data signal group P 0 _RX&lt; 0 : 17 &gt; is not transferred to the other banks BANK 0  and BANK 2  to BANK 7 . 
   Second, the signal output path from the second bank BANK 1  to the first port PORT 0  is described. 
   Referring to  FIG. 8 , the serializer  62  of the second bank control unit BC 1  serializes the 64-bit data signals outputted from the second bank BANK 1  and outputs the 16-bit output data signal group DO&lt; 0 : 15 &gt;_B 1  to the demultiplexers of port selection unit  66 . The demultiplexers receives the 16-bit output data signal group DO&lt; 0 : 15 &gt;_B 1  to output it as the 16-bit output valid data signal group P 0 _DATA&lt; 0 : 15 &gt; to the first global I/O data bus GIO_OUT in response to a first driving enable signal DRVEN_P&lt;D&gt; of the driving enable signal group DRVEN_P&lt; 0 : 3 &gt;. 
   The 16-bit output valid data signal group P 0 _DATA&lt; 0 : 15 &gt; loaded to the first global I/O data bus GIO_OUT is transferred to the first port PORT 0  through a third local I/O data bus LIO_P 1 . 
   Third, a normal read operation of the multi-port memory device is explained. The normal read operation means to fetch data from a specific address of a corresponding bank. 
   If the read command frame form or the read data frame form shown in  FIGS. 4D and 4E  is inputted to the first port PORT 0  through the reception port RX in series, the first port PORT 0  parallelizes and converts the inputted signals into the 26-bit valid signals. 
   The 26-bit valid signals are inputted to the bank selection unit  65  of the second bank control unit BC 1  through the second global I/O data bus GIO_IN. At this time, because the bank selection unit  65  is connected with the second global I/O data bus GIO_IN and the second local I/O data bus LIO_BIN shown in  FIG. 2 , the bank selection unit  65  of the second bank control unit BC 1  receives the 26-bit valid signals from the other parts PORT 1  to PORT 3  as well as the first port PORT 0 . 
   Accordingly, the 26-bit valid signals includes the 8-bit port/bank selection signal group Pi_BK&lt; 0 : 7 &gt; to select a required bank, and each bank selection unit  65  selects the required bank based on the 8-bit port/bank selection signal group Pi_BK&lt; 0 : 7 &gt;. Herein, a bank selection signal corresponding to the second bank BANK 1  is only activated, and thus, the bank selection unit  65  of the second bank control unit BC 1  receives the 18-bit input valid data signal group P 0 _RX&lt; 0 : 17 &gt; from the first port PORT 0 . 
   The state machine unit  63  of the second bank control unit BC 1  actives the internal active signal ACT and the internal read command signal READ based on the 18-bit input valid data signal group P 0 _RX&lt; 0 : 17 &gt;. The row and column address generating units  633  and  634  of the state machine unit  63  generate the row and column addresses XADD and YADD of the second bank BANK 1  based on the internal active signal ACT and the internal read command signal READ. The read data pipe controller  635  activates the pipe input strobe signal PINSTROBE and the pipe output control signal group POUT&lt; 0 : 3 &gt;, and the data output controller  636  activates the driving enable signal group DRVEN_P&lt; 0 : 3 &gt;. 
   The 64-bit data signals are amplified by the plurality of the DBSAs  14  of the second bank BANK 1  and are outputted to the serializer  62  according to the column address YADD in response to the internal read command signal READ. 
   The serializer  62  serializes the 64-bit data signals outputted from the plurality of the DBSAs  14  to output the 16-bit output data signal group DO&lt; 0 : 15 &gt;_B 1  in response to the pipe input strobe signal PINSTROBE and the pipe output control signal group POUT&lt; 0 : 3 &gt;. That is, the serializer  62  converts the 64-bit data signals into the 16-bit output data signal group DO&lt; 0 : 15 &gt;_B 1  in units of four, and sequentially outputs the 16-bit output data signal group DO&lt; 0 : 15 &gt;_B 1  to the port selection unit  66 . 
   The port selection unit  66  receives the 16-bit output data signal group DO&lt; 0 : 15 &gt;_B 1  and outputs the valid data signal group Pi_DATA&lt; 0 : 15 &gt; to the first port PORT 0  through the first global I/O data bus GIO_OUT in units of 16-bit based on the driving enable signal group DRVEN_P&lt; 0 : 3 &gt; which is generated by decoding the 4-bit port selection signal group BRX_P&lt; 0 : 3 &gt;. 
   The first port PORT 0  shown in  FIG. 3  serializes and outputs the valid data signal group Pi_DATA&lt; 0 : 15 &gt; to the external devices through the transmission pad TX by the serializer  421 . 
   Fourth, a normal write operation of the multi-port memory device is explained. The normal write operation means to write data to a specific address of a corresponding bank. In accordance with the embodiment of the present invention, input signals having five frame forms are inputted through the reception pad RX during the normal write operation. A first frame is a command frame shown in  FIG. 5B , and the other frames are data frames shown in  FIG. 5C . Each frame includes 16-bit data, and thus, a total frame includes 64-bit data. 
   The command and data frame forms are consecutively inputted to the first port PORT 0 , the parallelizer  411  of the first port PORT 0  parallelizes and converts each frame form into the 26-bit valid signals. 
   The bank selection unit  65  of the second bank control unit BC 1  receives the 26-bit valid signals inputted from the first port PORT 0  through the second global I/O data bus second global I/O data bus GIO_IN. At this time, because the bank selection unit  65  of the second bank control unit BC 1  is connected with the second global I/O data bus GIO_IN and the second local I/O data bus LIO_BIN shown in  FIG. 2 , the bank selection unit  65  of the second bank control unit BC 1  receives the 26-bit valid signals from the other ports PORT 1  to PORT 3  as well as the first port PORT 0 . 
   Accordingly, the 26-bit valid signals includes the 8-bit port/bank selection signal group Pi_BK&lt; 0 : 7 &gt; to select a required bank, and each bank selection unit  65  selects the required bank based on the 8-bit port/bank selection signal group Pi_BK&lt; 0 : 7 &gt;. Herein, a bank selection signal corresponding to the second bank BANK 1  is only activated, and thus, the bank selection unit  65  of the second bank control unit BC 1  receives the 18-bit input valid data signal group P 0 _RX&lt; 0 : 17 &gt; from the first port PORT 0 . 
   The state machine unit  63  of the second bank control unit BC 1  activates the internal active signal ACT and the internal write command signal WRIRE based on the 18-bit input valid data signal group P 0 _RX&lt; 0 : 17 &gt;. The row and column address generating units  633  and  634  of the state machine unit  63  generate the row and column addresses XADD and YADD of the second bank BANK 1 , and the input data strobe generating unit  632  generates the input data strobe signals DSTROBE 16 &lt; 0 : 3 &gt; and DSTROBE 64  in response to the eighteenth bank valid data signal BRX&lt; 17 &gt;, the internal active signal ACT and the internal write command signal WRITE. 
   Then, after the other data frames are consecutively inputted, the parallelizer  61  of the second bank control unit BC 1  converts the 16-bit signal group B 1 _RX&lt; 0 : 15 &gt; relating to the 18-bit input valid data signal group P 0 _RX&lt; 0 : 17 &gt; into the 64-bit parallel output data. The write driver (W/D)  13  of the second bank BANK 1  writes the 64-bit parallel output data to the memory cell array  10 . 
   During the normal write operation, if four frames including a data frame are consecutively inputted, 64 data bits are written to the memory cell array at the same time. However, before all of the four frames are inputted, another command can be performed by an interrupt. At this time, data inputted before the interrupt is performed are only written to the memory cell array. 
   However, for above described multi-port memory device interchanging a data or a signal with an external device in a serial input/output interface manner, there is suggested no specification or a method for setting a mode register which controls detailed operations based on a CAS latency or a burst length determined by control and address signals inputted through command and address pins like a general dynamic random access memory (DRAM). 
   SUMMARY OF THE INVENTION 
   Embodiments of the present invention are directed to provide an apparatus and a method for operating a mode register controlling an inner operation mode in a multi-port semiconductor device with a serial input/output interface. 
   Embodiments of the present invention are directed to provide an apparatus and a method for providing both a serial access mode and a parallel access mode in a multi-port semiconductor device with a serial input/output interface during a data access and a test operation. 
   In accordance with an aspect of the present invention, there is provided a semiconductor memory device, including plural ports for transmitting an input data serial-interfaced with an external device into a global data bus, plural banks for parallel-interfacing with the plural ports through the global data bus, plural input signal transmission blocks, responsive to a mode register enable signal, for transmitting an input signal parallel-interfaced with the external device into the global data bus, and a mode register set for determining one of a data access mode and a test mode based on the input signal inputted through the global data bus. 
   In accordance with another aspect of the present invention, there is provided a method for supporting serial and parallel interfaces of a semiconductor memory device with an external device, wherein the semiconductor memory device includes plural ports for transmitting an input data serial-interfaced with an external device into a global data bus and plural banks for parallel-interfacing with the plural ports through the global data bus, including transmitting an input signal parallel-interfaced with the external device into the global data bus in response to a mode register enable signal and determining one of a data access mode and a test mode based on the input signal inputted through the global data bus in response to the mode register enable signal. 
   In accordance with a further another aspect of the present invention, there is provided a method for supporting serial and parallel interfaces of semiconductor memory device with an external device, including: transmitting an input signal parallel-interfaced with the external device into the global data bus in response to a mode register enable signal; determining one of a data access mode and a test mode based on the input signal inputted through the global data bus in response to the mode register enable signal; serially interfacing with the external device if the data access mode is performed; and parallel interfacing with the external device if the test mode is performed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates a block diagram of a conventional semiconductor memory device disclosed in a commonly owned copending application, U.S. Ser. No. 11/528,970, filed on Sep. 27, 2006, entitled “MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT/OUTPUT INTERFACE”, which is incorporated herein by reference. 
       FIG. 2  illustrates a detailed block diagram of a bank shown in  FIG. 1 . 
       FIG. 3  illustrates a detailed block diagram of a port shown in  FIG. 1 . 
       FIGS. 4A to 4F  illustrate a frame form of input signals input to the port shown in  FIG. 3 . 
       FIG. 5  illustrates a circuit diagram of a bank control unit shown in  FIG. 1 . 
       FIG. 6  illustrates a circuit diagram of state machine unit shown in  FIG. 5 . 
       FIG. 7  illustrates a signal diagram of a signal input path from the ports to the banks. 
       FIG. 8  illustrates a signal diagram of a signal output path from the banks to the ports. 
       FIG. 9  illustrates a block diagram of a multi-port semiconductor memory device in accordance with an embodiment of the present invention. 
       FIG. 10  illustrates a frame format of input signals setting a mode register set (MRS). 
       FIG. 11  illustrates a frame format of input signals setting an extended MRS (EMRS). 
       FIG. 12  illustrates a flow chart showing a control operation of the multi-port semiconductor memory device shown in  FIG. 9 . 
       FIG. 13  illustrates a waveform showing the control operation of the multi-port semiconductor memory device shown in  FIG. 12 . 
   

   DESCRIPTION OF SPECIFIC EMBODIMENTS 
   Hereinafter, a multi-port semiconductor memory device in accordance with specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
     FIG. 9  illustrates a block diagram of a multi-port semiconductor memory device in accordance with an embodiment of the present invention. 
   For convenience of explanation, a multi-port memory device having four ports and eight banks is illustrated. 
   The multi-port semiconductor memory device includes ports PORT 0  to PORT 3  for transmitting an input data serial-interfaced with an external device into a global data bus GIO_out and GIO_in, banks BANK 0  to BANK 7  for parallel-interfacing with the ports PORT 0  to PORT 3  through the global data bus GIO_out and GIO_in, input signal transmission blocks  91  to  94 , responsive to a mode register enable signal MRE (‘MREb’ means an inverse signal of ‘MRE’), for transmitting an input signal parallel-interfaced with the external device into the global data bus GIO_out and GIO_in, and a mode register set MRS, responsive to the mode register enable signal MRE, for determining one of a data access mode and a test mode based on the input signal inputted through the global data bus GIO_out and GIO_in. 
   Herein, the ports PORT 0  to PORT 3  and the input signal transmission blocks  91  to  94  are coupled to transmission pads (TX 0   + , TX 0   − , RX 0   + , and RX 0   − ) to (TX 3   + , TX 3   − , RX 3   + , and RX 3   − ). In detail, a first port PORT 0  and a first input signal transmission block  91  are coupled to the transmission pad TX 0   + , TX 0   − , RX 0   + , and RX 0   −  and one port. That is, one input signal transmission block holds one transmission pad in common. The global data bus GIO_out and GIO_in includes the first data bus GIO_out for delivering the input data inputted through the transmission pads (TX 0   + , TX 0   − , RX 0   + , and RX 0   − ) to (TX 3   + , TX 3   − , RX 3   + , and RX 3   − ) and the second data bus GIO_in for delivering an output signal outputted from the banks BANK 0  to BANK 7  into the ports PORT 0  to PORT 3 . 
   If the semiconductor memory device switchovers a serial interface to a parallel interface in response to the mode register enable signal MREb, the input signal transmission blocks  91  to  94  transfers a 4-bit input signal, each bit inputted through each transmission pad, i.e., each of (RXO +  and RX 0   − ) to (RX 3   +  and RX 3   − ) into a first data bus GIO_out. Referring to  FIG. 9 , the 4-bit input signal transferred by the input signal transmission blocks  91  to  94  is delivered into a first line of the first data bus GIO_out, which is coupled to the first port PORT 0 . However, in other embodiments of the present invention, the 4-bit input signal can be transferred by another line of the first data bus GIO_out. 
   In the above described embodiment of the present invention, there are four input signal transmission blocks  91  to  94  corresponding to four ports PORT 0  to PORT 3 . However, in another embodiment of the present invention, one input signal transmission block can receive plural-bit test signals inputted through plural transmission pads. 
   Not shown in figures, each of the input signal transmission blocks  91  to  94  includes an input driver for receiving the input signal from each of the transmission pads (TX 0   + , TX 0   − , RX 0   + , and RX 0   − ) to (TX 3   + , TX 3   − , RX 3   + , and RX 3   − ) and an output driver for transferring the input signal output from the input driver into the first data bus GIO_out. Further, each of the input signal transmission blocks  91  to  94  can have a buffer located between the input driver and the output driver for buffering the input signal. 
   Referring to  FIG. 9 , the semiconductor memory device further includes a test input/output control block  95  for delivering input information into the global data bus GIO_out and GIO_in through test pads DQ 0  to DQ 3  during the test mode in response to the mode register enable signal MREb. 
   Moreover, the test input/output control block can transmit output information outputted from the banks BANK 0  to BANK 7  through the global data bus GIO_out into the test pads DQ 0  to DQ 3  in response to the mode register enable signal MREb. 
   The mode register set MRS shown in  FIG. 9  determines how to operate the semiconductor memory device according to one of a serial interface and a parallel interface in response to the mode register enable signal MREb. For example, when the mode register enable signal MREb is inputted as a logic low level, the mode register set MRS switchovers the serial interface of the semiconductor memory device to the parallel interface. 
   Also, the mode register set MRS receives the input signal, loaded on the first data bus GIO_in, transferred by the input signal transmission blocks  91  to  94  in response to the mode register enable signal MREb. Then, in response to a least significant bit (LSB) of the input signal, the mode register set MRS determines the serial interface for the data access mode or the parallel interface for the test mode in the semiconductor memory device. For example, the test mode is performed if the least significant bit of the input signal is a logic high level. Otherwise, in another embodiment of the present invention, the test mode can be performed if the least significant bit of the input signal is a logic high level. Further, the data access mode can be performed if the least significant bit of the input signal is a logic low level. 
   Further, the mode register set MRS generates a bank selection signal which is used for selecting one of the banks based on an inputted bank information signal during the test mode. Then, the bank corresponding to the bank selection signal operates in response to a test signal and the input information transmitted through the global data bus. 
   During the test mode, the ports PORT 0  to PORT 3  are disconnected from the transmission pads (TX 0   + , TX 0   − , RX 0   + , and RX 0   − ) to (TX 3   + , TX 3   − , RX 3   + , and RX 3   − ) in response to the mode register enable signal MREb during the test mode. As above described, the input signal inputted through the input signal transmission blocks  91  to  94  is delivered into the mode register set MRS through the first data bus GIO_in. 
   During the data access mode, the input data inputted through the ports PORT 0  to PORT 3  is delivered into the banks BANK 0  to BANK 3  through the first data bus GIO_in. Also, the output signal outputted from the banks BANK 0  to BANK 3  is delivered into the ports PORT 0  to PORT 3  through the second data bus GIO_out. 
     FIG. 10  illustrates a frame format of input signals setting a mode register set (MRS). Herein, the input signal has a frame format for the parallel interface. 
   Referring to  FIG. 10 , if the mode register enable signal MREb having a logic low level is inputted, the mode register set MRS uses the input signal transferred through the first data bus GIO_in for determining an internal operation mode of the semiconductor memory device. 
   The input signal is constituted with plural bits. Each bit of the input signal is used for defining an operation mode of the semiconductor memory device as shown in Tables 1 to 3. 
   
     
       
         
             
             
             
           
             
                 
               TABLE 1 
             
             
                 
                 
             
             
                 
               A0(RX0 + ) 
               Direct DRAM core test mode 
             
             
                 
                 
             
           
          
             
                 
               L 
               Disable(D) 
             
             
                 
               H 
               Enable(E) 
             
             
                 
                 
             
          
         
       
     
   
   
     
       
         
             
             
             
           
             
                 
               TABLE 2 
             
             
                 
                 
             
             
                 
               A4(RX1 + ) 
               Internal CAS latency 
             
             
                 
                 
             
           
          
             
                 
               L 
               CL4 (4 clock delay) 
             
             
                 
               H 
               CL3 (3 clock delay) 
             
             
                 
                 
             
          
         
       
     
   
   
     
       
         
             
             
             
             
           
             
                 
               TABLE 3 
             
             
                 
                 
             
             
                 
               A5(RX1 − ) 
               A6(TX1 + ) 
               Data transfer type (DTT) 
             
             
                 
                 
             
           
          
             
                 
               L 
               L 
               QDR0 (Quadruple Data Rate 0) 
             
             
                 
               L 
               H 
               QDR1 (Quadruple Data Rate 1) 
             
             
                 
               H 
               L 
               DDR (Double Data Rate) 
             
             
                 
               H 
               H 
               SDR (Single Data Rate) 
             
             
                 
                 
             
          
         
       
     
   
   As shown in table 1, in response to a least significant bit ‘A 0 ’ of the input signal, the mode register set MRS determines that the semiconductor memory device operates in the serial interface or in the parallel interface for direct DRAM core test mode. 
   For example, if the ‘A 0 ’ is logic high level, the parallel interface is selected; otherwise, if the ‘A 0 ’ is logic low level, the semiconductor memory device operates in the serial interface. 
   Meanwhile, as described in Table 2, the ‘A 4 ’ indicates a CAS latency, i.e., a delay time required for outputting a valid data from unit cells of the semiconductor memory device. Herein, if the ‘A 4 ’ is logic low level, the CAS latency is 4 (that is, the valid data is outputted after 4 clock cycles); otherwise, if the ‘A 4 ’ is logic high level, the CAS latency is 3. 
   Further, the ‘A 5 ’ and ‘A 6 ’ of the input signal determine a data transfer type DTT of the semiconductor memory device. As the data transfer type DTT, the semiconductor memory device can support a quadruple data rate  0  (QDR 0 ), a quadruple data rate  1  (QDR 1 ), a double data rate (DDR), and a single data rate (SDR). Herein, the data transfer type DTT means a type of input/output information transmitted through the test pad DQ 0  to DQ 3  during the test mode (particularly, the DRAM core test mode). During the test mode, the semiconductor memory device outputs the input/output information in synchronization with a rising edge, a falling edge, or both of two internal clock signals. 
   Referring to  FIG. 10 , the ‘A 2 ’ and ‘A 3 ’ of the input signal is for selecting a screen (or monitor) between two coupled monitors during the DRAM core test mode. For example, a monitor corresponding to a logic high level bit between the ‘A 2 ’ and ‘A 3 ’ is selected. Also, the ‘A 1 ’ is used for a logic check, e.g., the logic check is enabled if the ‘A’ is logic high level. 
   Moreover, the ‘M 0 ’ to ‘M 2 ’ of the input signal are inputted through additional pads, not the transmission pads (TX 0   + , TX 0   − , RX 0   + , and RX 0   − ) to (TX 3   + , TX 3   − , RX 3   + , and RX 3   − ). Herein, the ‘M 0 ’ to ‘M 2 ’ inputted as a bank information signal are used for selecting one or more banks of the banks BANK 0  to BANK 7  during the test mode. The mode register set MRS decodes the ‘M 0 ’ to ‘M 2 ’ by using a 4×8 decoder to thereby generate 8 number of bank selection signals. 
   In addition, the ‘M 0 ’ to ‘M 2 ’ are used for setting values in the mode register set MRS during the test mode or deciding values in an extended MRS (EMRS) during the data access mode. For example, if the ‘M 0 ’ to ‘M 2 ’ are all inputted as logic low level, i.e., ‘L’ ‘L’ ‘L’, values of the mode register set are set; otherwise, the extended MRS can be set. 
     FIG. 11  illustrates a frame format of input signals setting an extended MRS (EMRS). 
   As shown, the EMRS can be split into ‘EMRS 1 ’, ‘EMRS 2 ’, and ‘EMRS 3 ’ which are selected by the ‘M 0 ’ to ‘M 2 ’. Herein, the ‘EMRS 1 ’ used for supporting an operation of delay lock loop in the semiconductor memory device is set up when the ‘M 0 ’ to ‘M 2 ’ are inputted as ‘L’ ‘L’ ‘H’. If the ‘M 0 ’ to ‘M 2 ’ are inputted as ‘L’ ‘H’ ‘L’, the ‘EMRS 2 ’ is set up for supporting a serial and deserial operation SerDes such as a control of serializer or parallelizer included in the ports PORT 0  to PORT 3 . Also, the ‘EMRS 3 ’ related to an operation of phase lock loop PLL is set up when the ‘M 0 ’ to ‘M 2 ’ are inputted as ‘L’ ‘H’ ‘H’. 
   Above EMRS set up is not necessarily required for performing a direct DRAM core test mode, but there is no disadvantage though the EMRS set up is performed during the direct DRAM test mode. Further, in another embodiment of the present invention, above EMRS set up can be changed. 
   Similar to the input signal shown in  FIG. 10 , a least significant bit ‘A’ is referred by the mode register set MRS for operating the semiconductor memory device according to one of the serial interfaces for the data access mode and the parallel interface of the test mode. 
   For example, when the ‘M 0 ’ to ‘M 2 ’ are logic low level, if the ‘A 10 ’ is logic low level, the ‘AC 11 ’ is logic high level, and the ‘AC 12 ’, ‘AC 13 ’, ‘C 14 ’, and ‘C 15 ’ are logic low level, a DTM enable signal DTMEN shown in  FIG. 9  is determined based on a logic level of the ‘A 0 ’. That is, in above case, the DTM enable signal DTMEN is enabled if the ‘A 0 ’ is logic high level. However, for performing a data access during the data access mode, all bits except for the ‘A 4 ’ are set up to logic low level. 
   Herein, data inputted through the ‘AC 10 ’ to ‘AC 13 ’ are recognized as an address or a command. On the contrary, data inputted through the ‘C 14 ’ to ‘C 16 ’ are considered as only command, and data inputted through the ‘A 0 ’ to ‘A 9 ’ are considered as only address. 
   During the test mode (particularly, the DRAM core test mode), a test input/output control block  95  is required for inputting or outputting a test information. 
   During the test mode, the test input/output control block  95  decodes the input signal transferred through the first data bus GIO_in in response to the DTM enable signal DTMEN outputted from the mode register enable signal MREb to generate internal command signals such as a write instruction or a read instruction. Then, if the write instruction is generated, the test input/output control block  95  transmits the test information inputted through the test pads DQ 0  to DQ 3  into the first data bus GIO_in; otherwise, if the read instruction is generated, the test input/output control block  95  transfers the test information outputted from the banks BANK 0  to BANK 7  through the global data bus GIO_out into the test pads DQ 0  to DQ 3 . 
   Hereinafter, referring to  FIGS. 12 and 13 , there are described how to power up a semiconductor memory device in accordance with an embodiment of the present invention and how to perform an initialization sequence of the semiconductor memory device. 
     FIG. 12  illustrates a flow chart showing a control operation of the multi-port semiconductor memory device shown in  FIG. 9 .  FIG. 13  illustrates a waveform showing the control operation of the multi-port semiconductor memory device shown in  FIG. 12   
   First, the mode register enable signal MREb is inputted as a logic low level, and accordingly the semiconductor memory device initially operates in the parallel interface, i.e., a parallel input/output interface. 
   Then, a power lamp is up and a power voltage is supplied to internal functional blocks of the semiconductor memory device (S 131 ). An external clock CLK is inputted and stabilizes the internal functional blocks (S 132 ). The steps S 131  and S 132  are performed during about 200 μs. At this time, the input signal (‘A 0 ’ to ‘A 9 ’, ‘AC 10 ’ to ‘AC 13 ’, and ‘C 14 ’ to ‘C 16 ’) inputted through the transmission pads (TX 0   + , TX 0   − , RX 0   + , and RX 0   − ) to (TX 3   + , TX 3   − , RX 3   + , and RX 3   − ) and the bank information signals ‘M 0 ’ to ‘M 2 ’ are logic low level. 
   After the steps S 131  and S 132 , the mode register set MRS is set up (S 133 ). As above described, the mode register set MRS is set up based on the input signal (‘A 0 ’ to ‘A 9 ’, ‘AC 10 ’ to ‘AC 13 ’, and ‘C 14 ’ to ‘C 16 ’) inputted through the transmission pads (TX 0   + , TX 0   − , RX 0   + , and RX 0   − ) to (TX 3   + , TX 3   − , RX 3   + , and RX 3   − ) and the bank information signals ‘M 0 ’ to ‘M 2 ’. Further, if necessary, the extended MRS EMRS is also set up. 
   In a following step S 134 , if the least significant bit ‘A 0 ’ of the input signal is logic high, the DTM enable signal DTMEN (test enable signal) are enabled and the semiconductor memory device performs the DRAM core test mode. 
   After the DTM enable signal DTMEN is enabled, the semiconductor memory device waits for about six clock cycles. After about 20 ns from a timing of generating a precharge command PCGA for performing a pre-charge operation to all banks BANK 0  to BANK 7 , the semiconductor memory device generates an auto self refresh command AREF for automatically refreshing two or more than two banks among the banks BANK 0  to BANK 7  (S 136  and S 137 ). 
   After about 100 ns, the DRAM core test mode (DTM) starts in a selected bank (S 138 ). Herein, the bank can be randomly or sequentially selected for the test. 
   After finishing the test to all banks, the pre-charge operation is performed to all banks BANK 0  to BANK 7  (S 139 ). 
   Then, whether or not the semiconductor memory device operates, the serial interface is decided (S 140 ). Herein, the serial interface (SAM) is determined by the mode register enable signal (MREb). For example, if the mode register enable signal (MREb) is transited from logic low level to logic high level, the semiconductor memory device terminates the DRAM core test mode and enters into the serial interface. In the serial interface, the semiconductor memory device receives data or signal inputted from an external device through input pads RX 0   +  and RX 0   −  to RX 3   +  and RX 3   −  of the transmission pads. 
   Meanwhile, if the ‘A 0 ’ of the input signal is logic low level in the step S 134 , the semiconductor memory device operates in the serial interface mode for data access mode, not the DRAM core test mode (S 141  and S 142 ). In the data access mode, the semiconductor memory device inputs or outputs data/signal transmitted from an external device in the serial interface. 
   Hereinafter, a write or read operation during the DRAM core test mode in the semiconductor memory device according to the embodiments of the present invention is described in detail, referring to  FIG. 9 . 
   First, the write operation is described as follows. 
   During the DRAM core test mode (DTM), the mode register enable signal MREb is maintained as logic low level ‘0’. When the mode register enable signal MREb is inputted as logic low level, the mode register set MRS determines that the semiconductor memory device enters into the parallel interface for the DRAM core test mode. 
   In the DRAM core test mode begun by the mode register et MRS, an input signal of which each bit is parallel inputted through the transmission pads (TX 0   + , TX 0   − , RX 0   + , and RX 0   − ) to (TX 3   + , TX 3   − , RX 3   + , and RX 3   − ) and a dummy pad (S 1 ) is transferred into the first data bus GIO_in by the input signal transmission blocks  91  to  94 . At this time, i.e., during the DRAM core test mode, the ports PORT 0  to PORT 3  do not receive any signal or data. However, during the data access mode, signals or data can be inputted to the ports PORT 0  to PORT 3  if the mode register enable signal MREb is logic high level ‘1’. 
   The mode register set MRS receives an input signal transferred through the first data bus GIO_in by the input signal transmission blocks  91  to  94 . According to a predetermined bit of the input signal, the DTM enable signal DTMEN is activated as logic low level. 
   Also, the mode register set MRS decodes a bank information signal M 0  to M 2  to generate a bank selection signal T_BKEN&lt; 0 : 7 &gt;. Herein, the bank selection signal T_BKEN&lt; 0 : 7 &gt; is inputted to bank controllers BC 0  to BC 7 , each included in each of the banks BANK 0  to BANK 7 . The bank selection signal T_BKEN&lt; 0 : 7 &gt; is delivered into the bank controllers BC 0  to BC 7  through an additional bus, not the first and second data buses GIO_in and GIO_out. 
   In response to the DTM enable signal DTMEN, the test input/output control block  95  decodes the input signal transferred through the first data bus GIO_in to generate an internal write instruction, and transmits the test information inputted through the test pads DQ 0  to DQ 3  to the first data bus GIO_in. 
   The bank controllers BC 0  to BC 7  receive the bank selection signal T_BKEN&lt; 0 : 7 &gt; and, according to the bank selection signal T_BKEN&lt; 0 : 7 &gt;, determine what bank the input signal and the test information inputted through the first data bus GIO_in are inputted to. 
   For example, if the test information and the input signal delivered through the first data bus GIO_in are for testing a first bank BANK 0 , only ‘T_BKEN&lt; 0 &gt;’ of the bank selection signal T_BKEN&lt; 0 : 7 &gt; has a logic high level. Then, the bank controller BC 0  in the first bank BANK 0  is only enabled, and inputs the test information and the input signal to the first BANK 0 . At this time, the bank controller BC 0  decodes the input signal to generate a write instruction and controls the first bank BANK 0  by using the write instruction and an address signal included in the input signal. Lastly, in the first bank BANK 0 , the test information is stored in unit cells corresponding to the address signal by a write driver W/D (not shown in figures), in response to the write instruction. 
   Next, the read operation is described as follows. 
   During the DRAM test mode (DTM), the read operation is similar to the write operation described above. However, in the read operation, the semiconductor memory device receives the input signal containing a read command through the transmission pads(TX 0   + , TX 0   − , RX 0   + , and RX 0   − ) to (TX 3   + , TX 3   − , RX 3   + , and RX 3   − ), and outputs output information corresponding to the input signal to the test pads DQ 0  to DQ 3 . 
   Similar to the write operation, the mode register enable signal MREb is maintained as logic low level ‘0’. An input signal of which each bit is parallel inputted through the transmission pads (TX 0   + , TX 0   − , RX 0   + , and RX 0   − ) to (TX 3   + , TX 3   − , RX 3   + , and RX 3   − ) and a dummy pad (S 1 ) is transferred into the first data bus GIO_in by the input signal transmission blocks  91  to  94 . The test input/output controller  95  generates an internal read instruction by decoding the input signal transferred through the first data bus GIO_in in response to the DTM enable signal DTMEN. At this time, a test information is not transmitted to the first data bus GIO_in by the internal read instruction. 
   The bank controllers BC 0  to BC 7  receive the bank selection signal T_BKEN&lt; 0 : 7 &gt; and, according to the bank selection signal T_BKEN&lt; 0 : 7 &gt;, determine what bank the input signal and the test information inputted through the first data bus GIO_in are inputted to. The selected bank outputs output information to the second data bus GIO_out, wherein the output information is corresponding to the read instruction and an address signal included in the input signal. 
   The test input/output controller  95  receives the output information loaded on the second data bus, and outputs the output information to the test pads DQ 0  to DQ 3  in response to the read instruction decoded from the input signal. 
   The semiconductor memory device in accordance with the embodiments of the present invention is described by using an exemplary embodiment of the multi-port semiconductor memory device having four ports, eight banks, and 16-bit frame structure, but the present invention cannot be limited by the above specific structure of the semiconductor memory device. The present invention can apply to a semiconductor memory device supporting both a serial data interface and a parallel data interface with an external device. 
   The semiconductor memory device which can supports both the serial data interface and the parallel data interface with the external device in accordance to the present invention operates in the parallel data interface initially, and then selects one of the serial data interface for a data access mode and the parallel data interface for a test mode to thereby evaluate a performance of the semiconductor memory device. 
   While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.