Patent Publication Number: US-6657502-B2

Title: Multiphase voltage controlled oscillator

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to voltage controlled oscillators and, more particularly to a quadrature voltage controlled oscillator formed on an integrated circuit chip. 
     2. Background Description 
     Voltage Controlled Oscillators (VCOs) are well known. A typical prior art VCO is a tunable tank circuit, i.e., an inductor (L) in parallel with a capacitor (C) driving a buffer, e.g., an inverter, that oscillates at a base frequency (T 0 ) and has a voltage tunable operating range. Ideally, the VCO output frequency is directly and linearly proportional to a control voltage applied to the oscillator. Oscillator operating frequency may be varied by varying L or C. Generally, tunable tank circuit VCOs are the most reliable VCOs. 
     Completely integrated LC tank VCO&#39;s typically require band switching techniques or even multiple VCO&#39;s to achieve very wide tuning ranges. Discrete components, such as inductors and capacitors, are expensive and bulky. Further, attaching these discrete components to an integrated circuit complicates the integrated circuit. Accordingly, typical integrated circuit chip VCOs are based on simple oscillators or other circuits that may be built and contained on-chip, e.g., ring oscillators. However, ring oscillators are not particularly stable and are very sensitive to chip ambient and operating conditions. 
     Further, the output voltage swing of such ring oscillator based integrated VCOs is not constant but, is linearly related to output frequency. In order to achieve a large tuning range, the designer must accept small output signals at the low frequency end of the VCO operating spectrum. These low output signal levels degrade oscillator performance and increase noise sensitivity. 
     Thus, there is a need for a fully integrated quadrature VCO with a large tuning range and a large output signal level throughout the tuning range. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, aspects and advantages will be better understood from the following detailed preferred embodiment description with reference to the drawings, in which: 
     FIG. 1 shows a functional block diagram of the preferred embodiment quadrature VCO; 
     FIG. 2 shows the basic structure of the voltage controllable transconductance phase drivers used for constructing the VCO in FIG. 1; 
     FIGS. 3A-B show the relationship of input vectors V 1  and V 2  provided to transconductance amplifiers to the resulting current vectors V 1 gm 1  and V 2 gm 2  at the current summing output node; 
     FIGS. 4A-B show Bode plots of the magnitude and phase components of the single pole summing the impedance; 
     FIG. 4C shows the transfer function of the summing impedance in polar coordinates for an individual voltage controllable transconductance phase driver; 
     FIGS. 5A-B show the vector transfer function for the voltage controllable transconductance phase driver that is obtained by overlaying the summing impedance polar graph of FIG. 4C onto the phasor diagram of FIGS. 3A-B; 
     FIG. 6 is a block diagram in further detail of a preferred embodiment quadrature VCO; 
     FIGS. 7A-C are examples of voltage controllable transconductance inverters; and 
     FIGS. 8A-D show simple schematic examples of multiple phase voltage control oscillators, representing  4 ,  5 ,  6  and  9  phases, respectively. 
    
    
     DESCRIPTION OF A PREFERRED EMBODIMENT 
     The present invention is a multiphase Voltage Controlled Oscillator (VCO) that does not include an inductor, preferably of the type known as a quadrature VCO, which is fully integratable onto a single integrated circuit chip. In particular, the quadrature VCO of the present invention may be implemented in the complementary insulated gate field effect transistor (FET) technology that is commonly referred to as CMOS. A quadrature VCO typically produces at least two output signals 90 degrees out of phase with each other, i.e. a sine phase and a cosine phase. 
     Thus, the VCO of present invention is a low noise, wide frequency range, fully integratable CMOS quadrature VCO with a large output voltage swing over the full frequency range. The preferred tuning range for the VCO extends from 1200 MHz to 2000 MHz and the output voltage swing is sufficiently large over the entire range to drive digital circuits. In addition the VCO includes dual tuning ports to support a unique synthesizer loop. 
     FIG. 1 shows a block diagram of the preferred embodiment quadrature VCO  100 , which includes voltage controllable transconductance phase drivers  102 ,  104 ,  106  and  108 . In this embodiment, the output of each voltage controllable transconductance phase driver  102 ,  104 ,  106 ,  108  supplies one of 4 oscillator phases. Each voltage controllable transconductance phase driver  102 ,  104 ,  106 ,  108  receives 2 of the 4 phases as block inputs. The present invention is not restricted in use as a quadrature VCO, but may be used to implement an oscillator with N phases, each phase generated by a controllable transconductance functional block, appropriately selecting block inputs from output phases as described hereinbelow. 
     FIG. 2 shows the basic phase driver  110  for constructing a VCO  100  corresponding to the voltage controllable transconductance phase drivers  102 ,  104 ,  106  and  108  in FIG.  1 . Each basic phase driver  110  includes dual transconductance inverting amplifiers  112 ,  114 . Resistor  116  and capacitor  118  form a single pole and phase shifting impedance at the current summing output node  120 . Transconductance amplifiers  112 ,  114  generate currents V 1 gm 1 , V 2 gm 2  in response to input control voltages V 1 , V 2 . 
     As can be seen from FIGS. 3A-B, the input voltages V 1  and V 2  provided to transconductance amplifiers  112 ,  114  can be considered as vectors with phase and magnitude. Current vectors V 1 gm 1  and V 2 gm 2  result therefrom and are summed at the current summing node  120 , which is the phase driver output. For simplicity, taking the capacitor  118  to be zero and, therefore, X c =4, the current vectors sum in the output impedance (R), resulting in the output voltage vector (V 1 gm 1 +V 2 gm 2 )R. As shown in FIG. 3A, if the input voltage vectors are of equal amplitude and are in quadrature, then, the resultant output voltage vector is 45 degrees out of quadrature and inverted. In addition, as shown in FIG. 3B, both the magnitude and the phase of the output vector can be controllably varied by controlling the transconductance amplifier gain gm 1  and gm 2 . 
     FIGS. 4A-B show the magnitude and phase, respectively, of single pole summing impedance in polar form. Phase shift is zero (0) at zero (0) radians and approaches negative ninety degrees (−90°) or −B/2 radians as the frequency approaches infinity. The magnitude is maximum and equal to R at 0 radians and falls to 0 as frequency increases towards infinity. The 3 db point occurs at T=1/RC, which also corresponds to a 45 degree phase shift. FIG. 4C shows the transfer function of the summing impedance (including the capacitor  118 ) in polar coordinates for an individual controllable transconductance functional block. The vector impedance at any frequency originates at the origin and terminates on the arc  122  at a point corresponding to that particular frequency. 
     FIGS. 5A-B show the vector transfer function for the voltage controllable transconductance phase drivers  102 ,  104 ,  106 ,  108  that is obtained by overlaying the summing impedance polar graph of FIG. 4C onto the phasor diagram of FIGS. 3A-B. The phase shift vector at 0° for the summing impedance is mapped to the magnitude and phase of the output voltage vector (V 1 gm 1 +V 2 gm 2 )R with arcs  124 ,  126  corresponding to arc  122 . For any specific combination of quadrature input vectors and values of gm 1  and gm 2 , there exists a unique frequency on the polar graph of the summing impedance that corresponds to a quadrature output vector. So, as indicated above for gm 1 =gm 2 , the quadrature output vector corresponds to 45 degree phase shift at T C =1/RC as in FIG.  5 A. Thus, by controlling the values of gm 1  and gm 2  the quadrature frequency of the phase drivers is controlled, and the quadrature frequency may be varied from 0 to infinity. So, for each phase driver  102 ,  104 ,  106 ,  108  in the example of FIG. 1, the input vector V 1  is 180 degrees out of phase and the input V 2  is −90 degrees out of phase with the resulting output vector. From this analysis, it is a simple matter to select which block output signals are passed to which block input. 
     FIG. 6 is a block diagram of a preferred embodiment quadrature VCO  130  corresponding to and in further detail of the block diagram  100  of FIG.  1 . Each of the voltage controllable transconductance phase drivers  102 ,  104 ,  106  and  108  corresponds to a pair of controllable transconductance inverting amplifiers  132 ,  134 ,  136  and  138  respectively. Further, each of the pairs of controllable transconductance inverting amplifiers  132 ′,  132 ″,  134 ′,  134 ″,  136 ′,  136 ″ and  138 ′,  138 ″, corresponds to one of the pair of inverting transconductance amplifiers  112 ,  114  of FIG. 2, the subscript indicating correspondence. Thus, each pair  132 ,  134 ,  136 ,  138  provides a respective current and phase which is summed at the respective individual output  140 ,  142 ,  144  or  146  as described hereinabove for FIG.  2 . 
     FIGS. 7A-C show examples of controllable transconductance inverting amplifiers. FIG. 7A shows a simple inverter  150  that includes N-type FET (NFET)  152  and P-type FET (PFET)  154 . The source of the NFET  152  is connected to a low or negative supply voltage, e.g., ground, V low  or V ss . The source of the PFET  154  is connected to a high or positive supply voltage, V hi  or V dd . The drain of the NFET  152  is connected to the drain of PFET  154  at the inverter output  156 . The input to the inverter is connected to the common connection of the gate of NFET  152  and the gate of PFET  154 . Transconductance of this inverter  150  may be varied by varying supply voltages and, in particular, V dd . 
     For using the simple inverter  150  of FIG. 7A as a transconductance amplifier for small signals, the output current is given by:        I   =             (     u   ×     c   0       )     p     2     ×         z   p     ×   k     l     ×       (       V     i                 n       -     V     D                 D       +     V   t       )     2       -           (     u   ×     c   0       )     n     2     ×       z   n     l     ×       (       V     i                 n       -     V   t       )     2                         
     Where k is the ratio of the mobility-oxide capacitance product between the PFET  154  and NFET  152 . Normalizing these products as:                (     u   ×     c   0       )     p     2     ×         z   p     ×   k     l       =             (     u   ×     c   0       )     n     2     ×       z   n     l       =         (     u   ×     c   0       )     2     ×     z   l                         
     The transconductance gain of the inverter  150  is given by:          g                 m     =         (     u   ×     c   0       )     2     ×     z   l     ×     (       -     V     D                 D         +     2        V   t         )                       
     Thus, the transconductance gain of the inverter  150  is linearly proportional to the normalized width to length ratio of the inverter devices  152 ,  154 . Care must be taken that the topology restriction (gm 2 /gm 1 )#2 is not violated to avoid saturating the VCO&#39;s output at the rail voltages (V dd  and V ss ). This is accomplished by selecting different device sizes for the gm 1  and gm 2  inverters, sizing devices in the gm 2  inverters twice as large (i.e., twice as wide or half as long) as the gm 1  inverters and fixing the supply voltage for the gm 1  inverters at V dd . Then, by limiting the supply voltage of the gm 2  inverters to the rail voltage or below, the resulting VCO will be stable. The output impedance that each of the inverters see is the parasitic capacitance at the output in parallel with the inverter output conductances as described by:          Z        (   s   )       =     1       (       g   n     +     g   p       )     +     s                 C                         
     So, for this example, four of the inverters  132 ′,  134 ′,  136 ′ and  138 ′, have a gm fixed at gm 1 , while the remaining 4 inverters  132 ″,  134 ″,  136 ″ and  138 ″ have a variable gm of gm 2 , controlled by adjusting their supply voltage. Using the simple inverter  150  for the gm 2  inverters  132 ″,  134 ″,  136 ″, 138 ″, connected between V hi  and V lo  has both an advantage and a disadvantage. The advantage is that the VCO output voltage swing remains large, i.e., full range to the supply voltage levels, provided the gm 2  inverter gain does not over drive the output signal. The disadvantage is that, particularly at low frequencies, the large signal swing at the output of the gm 2  inverter is out of phase with the signal at the input of the gm 1  inverter. When the source (control) voltage V hi  for the PFET  154  of the gm 2  inverter is below V dd , the output from the gm 1  inverter can exceed V hi  such that current from the output signal flows into the gm 2  inverter output and from drain to source of PFET  154 , clamping the output voltage. To avoid this, the minimum supply voltage for the gm 1  inverter must be limited. Another drawback of using this simple inverter  150  for the quadrature VCO is that the control voltage is also the supply voltage. Therefore, the control voltage must also be able to supply oscillator current because it is, essentially, the oscillator power supply. This can be resolved by replacing the gm 2  inverters  132 ″,  134 ″,  136 ″ and  138 ″ with the inverters  160  of FIG.  7 B. 
     FIG. 7B shows a second controllable transconductance inverting amplifier  160 , similar to that of FIG. 7A, includes NFET  162  and PFET  164  corresponding to NFET  152  and PFET  154 . In addition, PFET  166  is connected drain to source in series with PFET  164 , between the source of PFET  164  and high supply voltage V dd . The gate of PFET  166  is controlled by a bias control voltage V CON . For this controllable transconductance inverting amplifier  160 , supply voltages may be held constant and transconductance may be varied by varying the current of PFET  166 , i.e., by varying V CON . The voltage at the source of PFET  164  is a function of the current supplied by PFET  166  and, correspondingly, the bias control voltage V CON  at the gate of PFET  166 . 
     The above described low frequency limitation can be overcome with switchable capacitors (not shown) at the summing nodes of each functional block. Since the phase shift of each summing node is a function of the total capacitance at that node, increasing the capacitance causes the phase shift to occur at a lower frequency and therefore reduces the oscillation frequency. 
     FIG. 7C shows a third controllable transconductance inverting amplifier  170 . NFET  172  corresponds to NFETS  152 ,  162 . The controllable transconductance inverting amplifier  170  of FIG. 7C is similar to the controllable transconductance inverting amplifier  160  of FIG. 7B with each of the series PFETs  164 ,  166  replaced by a parallel PFET pair. PFET  164  corresponds to parallel PFETs  174 ,  176  and PFET  166  corresponds to parallel PFETs  178 ,  180 . PFETs  174 ,  178  are connected in series between V dd  and the output. PFETs  176 ,  180  are also connected in series between V dd  and the output transconductance controlled by two separate transconductance control bias voltages V CON1  and V CON2  connected to the gates of PFETs  178 ,  180  respectively. Optionally, the connection point between PFETs  174  and  178  may be connected to the connection point  182  between PFETs  176  and  180 . With that optional connection, PFETs  174  and  176  may be replaced by a single PFET (not shown). 
     The multiple control voltage, controllable transconductance inverting amplifier  170  of FIG. 7C is useful for applications where multi-port steering control of the VCO is desired. As described hereinabove, the gm of the particular inverter is a function of device sizes in combination with supply voltages which produce the resulting inverter current. From the above oscillator analysis, using superposition and the current vectors of parallel PFETs  174 ,  176  and  178 ,  180 , the effective transconductance can be found by summing individual transconductances of the parallel devices. By maintaining the effective device size ratio of parallel PFETs  174 ,  176  and PFETs  178 ,  180  identical to that of PFETs  164 ,  166  of inverter  160 : 
     
       
         
           Z 
           p166 
           =Z 
           p178 
           +Z 
           p180 
         
       
     
     Thus, by controlling the device size ratio of PFETs  174 ,  176  to PFETs  178 ,  180 , the relative sensitivity of each port is controlled. Additional sensitivity control is available by selectively connecting the common drain/source connection of PFETs  174 ,  178  to PFETs  176 ,  180  at  182 . 
     It should be noted that for the above described embodiments, while each phase driver&#39;s quadrature output will vary virtually from 0 to infinity, oscillator topology places restrictions on the frequency range of the quadrature VCO. These frequency range restrictions are more apparent from more rigorous mathematical analysis of the VCO. The normalized, frequency-dependent transfer function of each functional block, input vectors and output vectors being described in exponential form, is:            V     (     n   +   2     )            (          -     j        (       2        π        (     n   +   2     )         N     )           )       =           V     (   n   )            (          -     j        (       2      π     N     )           )            (     g                     m     (   n   )            (     |     z        (   ω   )       |          -     j        (     ∠                   L        (   ω   )                   )         )       +         V     (     n   +   1     )            (          -     j        (       2        π        (     n   +   1     )         N     )           )            (     g                     m     (     n   +   1     )            (     |     z        (   ω   )       |          -     j        (     ∠                   L        (   ω   )                   )         )                         
     Where N is the number of oscillator phases and n=1,2,3, . . . N. 
     For the above described preferred quadrature oscillator N=4 and the required phase shift is B/2 radians. Since all of the functional blocks are identical, the case where n=1 is described. The phase requirement can be reduced to:          -     π   2       =         -   a                     tan        (       g                   m   1         g                   m   2         )         +     ∠                   Z        (     ω   0     )                           
     The ArcTangent term        (     a                   tan        (       g                   m   1         g                   m   2         )         )                   
     is the phase shift associated with the variation in the gm&#39;s and the second term (∠Z(ω 0 )) is the phase shift associated with the summing impedance pole. The latter phase shift is found to be: 
     
       
         ∠ Z (ω 0 )= a  tan(−ω RC ) 
       
     
     Substituting, the frequency which satisfies the conditions of oscillation is where:          ω   0     =                ω   c     ×     (       g                   m   2         g                   m   1         )                   w                 h                 e                 r                 e                   ω   c       =     1     R                 C                         
     and so,            ω   0       ω   c       =         g                   m   2         g                   m   1         .                     
     For a quadrature oscillator, input and output voltage vectors are all of equal amplitude, and gain requirements can be determined from: 
     
       
         1≦(( gm   1 ) 2 +( gm   2 ) 2 )×| Z (ω 0 )| 2   
       
     
     Thus, in terms of the corner summing impedance frequency:        1   ≤       (         (     g                   m   1       )     2     +       (     g                   m   2       )     2       )     ×     R   2     ×     (     1         (       ω   0     /     ω   c       )     2     +   1       )                       
     Then, using the above gm ratio to frequency ratio identity, the requirement for oscillation is given by: 
     
       
         1≦ gm   1   ×R  and 
       
     
     
       
         
           
             
               ω 
               0 
             
             = 
             
               
                 g 
                  
                 
                     
                 
                  
                 
                   m 
                   2 
                 
               
               C 
             
           
         
         
         
             
         
       
     
     Next analyzing the oscillator loop, the transfer function for each basic functional block input is:          H        (   s   )       =       g                     m     (   n   )            (     |     Z        (   S   )       |          -     j        (     ∠                   L        (   s   )         )             )         =     g                   m     (   n   )       ×     (     R       s     ω   c       +   1       )                         
     The sole difference between the two block inputs are gm 1  and gm 2 , which are described by the ratio M=gm 2 /gm 1 . The transfer function of the block may be described in terms of the general transfer function H(s), the quadrature inputs I(s) and Q(s) and their complements. Thus, the oscillator function may be described in terms of the 4 simultaneous equations: 
     
       
           I ( s )=− H ( s )×({overscore ( I ( s ))}+ M×{overscore (Q(s))})   
       
     
     
       
           Q ( s )=− H ( s )×({overscore ( Q ( s ))}+ M×I ( s )) 
       
     
     
       
         {overscore ( I ( s ))}=− H ( s )×( I ( s )+ M×Q ( s )) 
       
     
     
       
         {overscore ( Q ( s ))}=− H ( s )×( Q ( s )+ M×{overscore (I(s))})   
       
     
     The output mode transfer function may be determined by injecting an input signal, X(s) at the complement of Q(s) to obtain:            I        (   s   )         X        (   s   )         =         -   M                       H   1          (   s   )            (         M   2            H   3          (   s   )         -       H   2          (   s   )       +   1     )               H   4          (   s   )            (     1   -     M   4       )       +     4        M   2            H   3          (   s   )         -     2          H   2          (   s   )         +   1                       
     Substituting H(s) above and solving, the transfer function poles are given by: 
     
       
           s=ω   c ( gm   (n)   R× ( M− 1)−1) 
       
     
     
       
           s=−ω   c ( gm   (n)   R× ( M+ 1)+1) 
       
     
     
       
           s=ω   c (( gm   (n)   R− 1)+(± j ) Mgm   (n)   R ) 
       
     
     So, from the gain requirement for stable oscillation, 1=gm 1 R, the poles determined hereinabove occur at: 
     
       
           s=ω   c ( M− 2   ) 
       
     
     
       
           s=−ω   c ( M+ 2) 
       
     
     
       
           s=ω   c ((± j ) M ) 
       
     
     An additional restriction arises from the preferred topology as a simple real pole exists in the right half s-plane when (gm 2 /gm 1 )&gt;2. To avoid the instability of having the poles in the right half s-plane the restriction gm 2 /gm 1 , #2 must be met which limits the upper oscillation frequency to 2/RC. 
     The Q of the preferred quadrature VCO may be determined from the open loop 3 dB bandwidth. So, considering the topology of the VCO  100  of FIG. 1 as a 2-stage differential circuit with feedback, the above quadrature equations, I(s) and {overscore (I(s))} can be used to determine the open loop transfer function for each stage. 
     Taking Q(s) and its complement ({overscore (Q(s))}) as differential inputs and I(s) and its compliment ({overscore (I(s))}) as outputs the transfer function for a single stage is:              I        (   s   )       -       I        (   s   )       _           Q        (   s   )       -       Q        (   s   )       _         =       M   ×     H        (   s   )           (     1   -     H        (   s   )         )                       
     Substituting H(s) from above the equation becomes:              I        (   s   )       -       I        (   s   )       _           Q        (   s   )       -       Q        (   s   )       _         =       (       ω   c        g                   m   2        R     )       (     s   +       ω   c          (     1   -     g                   m   1        R       )         )                       
     So, the open loop transfer function for 2 cascaded differential blocks is:          O                   L        (   s   )         =         (       ω   c        g                   m   2        R     )     2       (       s   2     +     s        (     2          ω   c          (     1   -     g                   m   1        R       )         )       +       (       ω   c          (     1   -     g                   m   1        R       )       )     2       )                       
     Thus, the Q of the quadratic in the denominator is ½ when gm 1 R&gt;1. However this is not particularly informative as the natural frequency is not the frequency of the VCO. When gm 1 R=1, the circuit essentially is a pair of cascaded integrators of the form:          O                   L        (   s   )         =       (       1   s     ×       g                   m   2       C       )     2                     
     By cross coupling and feeding the differential output to the input, the circuit oscillates at the unity gain frequency, in this case gm 2 /C radians. 
     FIGS. 8A-D are simple schematic examples of multiple phase voltage control oscillators, representing  4 ,  5 ,  6  and  9  phases, respectively. In particular, the four phase VCO  130  of FIG. 8A corresponds directly to quadrature VCO  130  of FIG.  6 . Individual transconductance amplifiers are represented by arrowheads  190 , and each may be inverting or non-inverting, depending upon the particular application. Further, cross-coupled transconductance amplifiers are represented by double headed arrows  192  and other, individual transconductance amplifiers are represented by single headed arrows  194 . It should be noted that for a VCO providing an even number of phases as in FIGS. 8A and 8C, cross-coupled transconductance amplifiers are included; whereas, for a VCO providing an odd number of phases as in the examples of FIGS. 8B and 8D, cross-coupled transconductance amplifiers are not included. 
     As can be seen from FIGS. 8A-D, the VCO structure becomes more complicated as the number of oscillator phases increases. Further, it is possible that more than one configuration may be available that each yield a particular number of phases. 
     In general, each phase driver drives one of the N phases, the phases being separated by 360°/N. These phases can be assigned values of k for k=0 to N−1, where ι 0  is assigned a value of 0° and          Ø   k     =       k   N     ×   360        °   .                       
     Thus, the phase driver input/output space is the set {0, 1, . . . , N−1} and designating the possible values for the phase driver inputs x and y, x and y are constrained to solutions of 
     
       
           M=x+y  Mod  N  and 0&lt; M&lt;   
       
     
     for phase driver output k=0. The phase shift due to the summing impedance is            2   N     =       -     M     2      N         ×   360      °       ,                   
     e.g., −45 degrees in the 4 phase oscillator example of FIGS. 6 and 8A and −36 degrees in the 5 phase oscillator example of FIG.  8 B. Phase drivers may be either inverting or non-inverting transconductance amplifiers. Thus, for any phase driver output k, the corresponding inputs are: 
     
       
           x+k  Mod  N  and  y+k  Mod  N.   
       
     
     Advantageously, the preferred embodiment oscillator does not require an inductor and, therefore, does not have a conventional tuned circuit Q. The circuit Q may be described by the simple definition that Q equals stored energy divided by the dissipated energy for the passive elements, i.e. R and C. For a parallel RC circuit Q=T 0 RC. T 0 =M/RC and, so, Q=M or the transconductance ratio of the inverter. 
     While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.