Patent Publication Number: US-2003227306-A1

Title: Low voltage Vcc detector

Description:
RELATED APPLICATIONS  
       [0001] This application claims priority to Italian Patent Application Serial No. RM2002A000322, filed Jun. 7, 2002, entitled “LOW VOLTAGE VCC DETECTOR,” and which is incorporated herein by reference.  
       FIELD  
       [0002] The present invention relates generally to low voltage detectors, and more specifically to an improved low voltage detector.  
       BACKGROUND  
       [0003] Electronic circuits are contained in many devices, including by way of example only and not by way of limitation, integrated circuits, microchips, circuit boards, cellular telephones, computers, and the like, require power supplies of some sort. To start up such circuits, a reliable threshold voltage in the power supply must be met. Typical circuitry to measure the threshold voltages and to trigger a signal indicating that the threshold voltage has been reached are known as power on reset (POR) circuits.  
       [0004] POR circuits become increasingly important in low-voltage devices, such as in Flash memories, where supply voltages V cc  are typically in the range of 1.65 volts to 1.95 volts. There is the need, during a power on phase, to detect if the supply voltage (V cc ) has reached a certain threshold value, so that when the threshold value is reached, a reset signal can be deasserted.  
       [0005] Low voltage circuits cannot use traditional voltage threshold detectors, such as Zener diode detectors, since such circuits operate at higher voltages and consume a great deal of power compared to the power and voltages present in low voltage circuits.  
       [0006] In the past, the reset signal in lower voltage circuits has been obtained using bandgap circuits having a comparator, a resistive ladder, and a voltage reference, as is shown in U.S. Pat. No. 6,268,764, entitled BANDGAP VOLTAGE COMPARATOR USED AS A LOW VOLTAGE DETECTION CIRCUIT, issued Jul. 31, 2001 to Eagar et al. Such components require valuable silicon real estate and still consume a relatively large amount of power.  
       [0007] Further, in low voltage circuits, during power-on, the voltage reference grows with a slope similar to the supply voltage VCC slope. This can cause a false detection of the threshold voltage, thus resulting in the reset signal being deasserted too early.  
       [0008] For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a smaller area threshold voltage detector, and a more reliable low voltage detector not relying on a voltage reference or voltage comparator.  
       SUMMARY  
       [0009] The above-mentioned problems with supply voltage detectors and other problems are addressed by the embodiments of the present invention and will be understood by reading and studying the following specification.  
       [0010] In one embodiment, a method for operating a reset signal on a supply voltage includes providing the supply voltage to first and second transistors to generate first and second currents, and mirroring the first and the second currents with third and fourth transistors. The mirrored currents are compared with a current comparator, and the current comparator output is switched to deassert a reset signal through an inverter when the supply voltage reaches a predetermined threshold.  
       [0011] In another embodiment, a method for deasserting a reset signal includes maintaining a node voltage for an inverter input below the inverter voltage threshold until a supply voltage reaches a predetermined level, and deasserting the reset signal at the inverter output when the supply voltage reaches the predetermined level.  
       [0012] In still another embodiment, a method for indicating a predetermined threshold voltage condition for a supply voltage has been reached includes providing the supply voltage to a detection circuit, and drawing first and second currents through first and second distinct current paths in the circuit. The current paths have characteristics to cause the currents therein to move from a first current situation in which the first current is greater than the second current to a second situation in which the second current equals and exceeds the first current. The first and second currents are mirrored in third and fourth current paths in the circuit, and a reset signal is deasserted when the second current exceeds the first current.  
       [0013] In yet another embodiment, a method of detecting sufficiency of a ramped supply voltage includes providing the supply voltage to a detection circuit, and deasserting a detection circuit reset signal when the ramped supply voltage reaches a minimum voltage.  
       [0014] In another embodiment, a low voltage detector includes first and second transistors diode connected between a supply voltage and ground, first and second resistors connected in series with each other and in series with the first transistor, and a third resistor connected in series with the second transistor. Third and fourth transistors are connected to mirror current in the first and second transistors, a current comparator is connected between the supply voltage and the third and fourth transistors to compare the currents in the third and the fourth transistors, and an inverter has an input connected between the current comparator and the fourth transistor. The inverter generates a logic high signal until the voltage at its input exceeds a threshold voltage of the inverter.  
       [0015] In another embodiment, a circuit includes first, second, third, and fourth current paths between a supply voltage and ground, the third and fourth current paths mirroring current in the first and second current paths, a current comparator to compare the currents in the third and the fourth current paths, and an inverter having an input connected between the current converter and the fourth current path. The current comparator raises a voltage in the fourth current path above a threshold value of the inverter when the supply voltage reaches a predetermined level.  
       [0016] Other embodiments are described and claimed. 
     
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
     [0017]FIG. 1 is a circuit diagram of an embodiment of the present invention;  
     [0018]FIG. 2 is a diagram of a typical ramp voltage used in embodiments of the present invention;  
     [0019]FIG. 3 is a diagram of a reset signal generated by embodiments of the present invention; and  
     [0020]FIG. 4 is a timing diagram of the embodiment of FIG. 1. 
    
    
     DETAILED DESCRIPTION  
     [0021] In the following detailed description of the embodiments, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims.  
     [0022]FIG. 1 is a circuit diagram of a low voltage V cc  detector  100  according to one embodiment of the present invention. V cc  detector  100  comprises a circuit connected between a supply voltage V cc  and ground. A first path between V cc  and ground comprises an n-channel transistor  102  diode connected in series with first and second resistors  124  and  126 . A current I 1 , indicated by arrow  130 , flows through this branch in operation. A second path between V cc  and ground contains another n-channel transistor  104  diode connected in series with resistor  128 . A current I 2 , indicated by arrow  132 , flows in the second path during operation.  
     [0023] The gate of transistor  102  is connected to the gate of transistor  106 . Transistor  106  mirrors the current I 1  in current path I 3  indicated by arrow  134 . The gate of transistor  104  is connected to the gate of transistor  108 . Transistor  108  mirrors the current I 2  in current path I 4  indicated by arrow  138 . The currents I 3  and I 4  are drawn through current comparator  140 . Current comparator  140  comprises four p-channel transistors, connected as shown in FIG. 1 to compare currents I 3  and I 4 . Current comparator  140  compares the currents I 3  and I 4 . In this embodiment, in operation, when a ramping up supply voltage V cc  is supplied to the circuit, while current  13 , which mirrors current I 1 , remains above current I 4 , which mirrors current I 2 , transistor  118  of current comparator  140  remains off and transistor  116  of current comparator  140  remains on. This keeps the voltage at node  110  below the threshold voltage of the inverter  112 . Therefore, the reset signal  142 , at the output of the inverter  112 , remains at a logical high, that is, it is asserted. When the reset signal is asserted, a circuit or device connected to the reset signal  142  at the output of inverter  112  that requires a certain V cc  threshold to be met is not available for startup.  
     [0024] Inverter  112  is connected at node  110  to generate the reset signal. In operation, a power on sequence provides a voltage ramp to the supply (for example, a voltage ramp over 5 milliseconds) as is shown in FIG. 2 is applied to V cc . When V cc  reaches the threshold voltage of an n-channel metal oxide semiconductor field effect transistor (MOSFET) (V thn ) having characteristics similar to those of transistors  102  and  104 , both MOSFETS  102  and  104  begin to conduct. In one embodiment the transistors are of different dimension. In this embodiment, W 102 /L 102 &gt;W 104 /L 104 . When conduction begins in transistors  102  and  104 , the current I 1 , indicated by arrow  130 , is greater than the current I 2 , indicated by arrow  132 , due to the characteristics of the transistors. Current I 3 , indicated by arrow  134 , mirrored by transistor  106 , is therefore initially greater than current I 4 , indicated by arrow  138 , mirrored by transistor  108 .  
     [0025] For this reason, until I 1 =I 2  (and therefore I 3 =I 4 ), the current comparator keeps the voltage at node  110  low since transistor  118  is off and transistor  116  is on. Therefore, the node voltage at node  110  stays lower than the threshold voltage of the inverter  112  (V thinv ), and the reset signal  142  at the output of inverter  112  remains high, or asserted. The current comparator  140 , comprising in one embodiment p-channel transistors  114 ,  116 ,  118  and  120 , does not flip, that is transistor  118  remains off, and transistor  116  remains on, and the reset signal stays at a logic high level, while current I 3  is greater than current I 4 .  
     [0026] As V cc  continues to increase, in one embodiment according to the ramp shown in FIG. 2, the V cc  voltage increase reduces the gap between currents  11  and  12 , because of a current limiting effect of resistor  124 . At a certain point, indicated generally in the timing diagram of FIG. 4, as V cc  continues to increase, current I 2  becomes greater than current I 1 . At this point, mirrored current I 4  becomes greater than mirrored current I 3 , and the current comparator  140  flips. Transistor  116  turns off, and transistor  118  turns on. The node voltage at node  110  is raised to a point above that of the V thinv  of inverter  112 , and the reset signal is deasserted, switching to a logical low level. At this point, the circuit has indicated that the V cc  level has reached the threshold level for startup of a device or circuit connected to the reset signal.  
     [0027] The V cc  value where I 1 =I 2  represents the detector threshold voltage (V dth ), that is the voltage at which the circuit  100  deasserts the reset signal. In order to calculate V dth , in one embodiment a hypothesis and certain conditions are presumed:  
     [0028] Hypothesis:  
     [0029] For transistors  106  and  102 , W 106 /L 106 =W 102 /L 102   
     [0030] For transistors  108  and  104 , W 108 /L 108 =W 104 /L 104   
     [0031] Conditions:  
     [0032] Transistors  102 ,  104 ,  106  and  108  are the same type (for example n-channel medium voltage MOSFETS)  
     [0033] For transistor  102 , W 102 /L 102 =β*K  
     [0034] For transistor  104 , W 104 /L 104 =β 
     [0035] Resistances  126  (R 126 )=128 (R 128 )=R  
     [0036] I 1 =I 2 =I (threshold condition)  
     [0037] Under previous conditions and hypothesis, it follows that:  
       V   gs104   =V (N 144 )= V (N 146 )=R 124 * I+V   gs102   [1] 
     [0038] since the equation of  102  and  104  in the saturation region are:  
     I 1 = K *β*[( V   gs102   −V   thn ) 2 ]/2  
     I 2 =β*[( V   gs104   −V   thn ) 2 ]/2  
     [0039] Solving for V gs102  and V gs104 , and substituting:  
       V   thn+sqrt (2 I /β)=R 124 * I+V   thn+sqrt (2 I/K β)  [2] 
     [0040] Finally, solving for 1 in equation 2 yields:  
       I =I 1 =2*[(1−1/ sqrt ( K )) 2 ]/(R 124   2 *β)  [3] 
     [0041] When I 1 =I 2 =I:  
       V   cc   =V   dth   =V   gs104   +R*I=V   thn   +sqrt (2* I /β)+ R*I   [4] 
     [0042] Substituting equation 3 into equation 4 results in:  
       V   dth   =V   thn +2*(1−1/ sqrt ( K ))/(R 124 *β)+2* R *[(1−1/ sqrt ( K )) 2 /R 124   2 *β]  [5] 
     [0043] Using this last equation 5, the V dth  of the detector  100  is calculable. The V dth  of the detector is also therefore settable by choosing the various values of the length and width of the transistors (the transistor P values) and the resistances R and R 124 . Also, in another embodiment, another degree of freedom in selection of V dth  is obtained by setting β 102 &gt;β 106  (W 106 /L 106  for transistor  106 ) so that when I 1 =I 2 , the V cc  voltage is higher than in the condition I 3 =I 4 . This allows lowering V dth . In one embodiment, V dth  is raised by setting β 102 &lt;β 106 . A representative graph for the circuit  100  with β 102 &gt;β 106  is shown in FIG. 3 for the V cc  ramp of FIG. 2.  
     [0044]FIG. 4 is a timing diagram of the embodiment shown in FIG. 1. As can be seen with reference to FIGS. 1 and 2, on start of the ramp up in V cc , the reset signal is high as the voltage at node  110  is low. When V cc  reaches the threshold voltages of transistors  102  and  104 , they begin to conduct. As such, the currents conducted are mirrored in transistors  106  and  108  respectively. Because of the resistances in series with the transistors, initially, current I 1  is higher than current I 2 . As V cc  continues to increase, the current limiting factor of resistor  124  limits the current I 1  as current I 2  continues to increase. At the threshold voltage of the detector  100 , V dth , current I 2  becomes equal to current I 1 . At this point, the current I 4  becomes larger than current  13 . The current comparator flips, and the voltage at node  10  reaches a level in excess of the threshold voltage of the inverter  112 . The reset signal therefore goes low, and the circuit indicates that V cc  is at a sufficient level for startup of any connected devices or other circuits.  
     [0045] In another embodiment, the circuit  100  is temperature compensated. That is, the threshold voltage result is temperature compensated. Such temperature compensation schemes are known in the art and are within the scope of the invention, but will not be described in further detail herein.  
     [0046] The embodiments of the present invention occupy a smaller area on silicon that previous solutions. The embodiments of the invention achieve the smaller area by elimination of the need for a startup circuit and startup sequence, a voltage reference, and a voltage comparator. Because of the elimination of those elements, a smaller area and less required power are achieved. Further, the minimum supply voltage required for the circuit embodiments is lower than in previous solutions.  
     [0047] By way of example only and not by way of limitation, advantages of the various embodiments of the present invention include low voltage supply operation (1.5-1.95 Volts), minor silicon area compared to other similar circuits, and elimination of components including a voltage reference and a voltage comparator.  
     CONCLUSION  
     [0048] A low voltage supply voltage (V cc ) detector has been described. The low voltage V cc  detector draws current through a pair of transistors each having resistance in series therewith, and mirrors the currents to a second pair of transistors. The characteristics of the first pair of transistors and their series resistances results in currents that vary as supply voltage increases. When the supply voltage reaches a programmable threshold voltage, the current levels equal each other. At this point, a current comparator detects the cross in current level, and the voltage at a reset signal inverter is raised above the inverter threshold, and a reset signal which had been high is deasserted, indicating that the supply voltage has reached the threshold.  
     [0049] The V cc  detector of the present embodiments accomplishes the deassertion of the reset signal in a smaller silicon area and using fewer components than previous solutions.  
     [0050] It is to be understood that the above description is intended to be illustrative, and not restrictive. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.