Patent Publication Number: US-2011057736-A1

Title: Linear, Voltage-Controlled Ring Oscillator With Current-Mode, Digital Frequency And Gain Control

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is filed under 35 U.S.C. 111(a) as a continuation of International Patent Application Serial No. PCT/US2009/041919, entitled “Linear, Voltage-Controlled Ring Oscillator With Current-Mode, Digital Frequency And Gain Control” and filed on Apr. 28, 2009 (Applicant: Skyworks Solutions, Inc. et al.; Attorney Docket No. 19308.0164P1), which International Patent Application designates the United States and is hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     The circuitry of essentially every digital and mixed-signal integrated circuit (IC) requires one or more clock signals. Circuitry for generating clock signals commonly includes one or more oscillators. An oscillator can be of the fixed or controllable type. A fixed oscillator is an autonomous circuit that generates a signal of a single, precise frequency. A controllable oscillator produces a signal of frequency that is proportional to an external tuning signal, allowing the oscillator to cover a range of frequencies. Regardless of the type of oscillator, inevitable variations in the manufacturing process, supply voltage, and operating temperature (PVT) result in frequency error. The conventional method of compensating for these effects is to add frequency tuning to a fixed oscillator or to increase the existing tuning range of a controllable oscillator by an amount equal to the expected error. Then, a feedback or calibration system can be used to generate a tuning signal and correct the oscillator frequency. Oscillator gain, K osc , is the degree by which a tuning signal can adjust the frequency, 
     
       
         
           
             
               
                 
                   
                     
                       Oscillator 
                        
                       
                           
                       
                        
                       Gain 
                     
                     ≡ 
                     
                       K 
                       OSC 
                     
                   
                   = 
                   
                     
                       
                         Change 
                          
                         
                             
                         
                          
                         in 
                          
                         
                             
                         
                          
                         Freqeuncy 
                       
                       
                         Change 
                          
                         
                             
                         
                          
                         in 
                          
                         
                             
                         
                          
                         Tuning 
                          
                         
                             
                         
                          
                         Signal 
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     Therefore, increasing the frequency range of an oscillator for a given tuning signal also increases the gain. Depending on the application in which the oscillator is to be used, this solution may not be acceptable or create undesirable side effects. For example, in a phase-locked loop (PLL), the forward gain of the PLL is distributed between the oscillator, phase detector and loop filter. If the loop gain is to remain constant, increasing the oscillator gain must be accompanied by a decrease in phase detector or loop filter gain, which can increase in-band noise. Another drawback of increasing oscillator gain is a greater sensitivity to any noise coupling onto the tuning port. This will modulate the oscillator, causing sidebands to appear in the output spectrum that can degrade performance in many applications. Finally, most methods of frequency control are linear over a narrow range only. Nonlinear behavior resulting from increasing this range can cause the oscillator to be over or under corrected. 
     Although various oscillator circuits are known, a type known as a ring oscillator is commonly used in IC applications because ring oscillators generally occupy less IC die area than similar oscillators that are based upon inductive or capacitive elements. Ring oscillators rely on the distributed phase shift and gain of multiple amplifiers connected in a closed loop to generate oscillation. As illustrated in  FIG. 1A , an exemplary ring oscillator  10  can comprise three inverters  12 ,  14  and  16  connected in series with each other, with the output of each of inverters  12 ,  14  and  16  coupled to an input of another one of inverters  12 ,  14  and  16 , i.e., in a ring. Although three inverters  12 ,  14  and  16  are shown in this example, a ring oscillator can comprise any number of inverters. Capacitances  18 ,  20  and  22  represent the capacitances between the nodes  24 ,  26  and  28  at the outputs of the respective inverters with respect to a common node  30 . Each of capacitances  18 ,  20  and  22  has a value (i.e., a capacitance) of C 1 . That is, the total capacitance experienced by each of inverters  12 ,  14  and  16  at their respective output nodes  24 ,  26  and  28  is C 1 . 
     As illustrated by the waveform diagram of  FIG. 1B , ring oscillator  10  oscillates because a net DC phase shift of 180° is present, and an additional phase shift of 60° per inverter occurs at a frequency where the total gain around the ring is unity. The waveform shown in  FIG. 1B  is based upon several assumptions (i.e., simplifications made for explanatory clarity) about ring oscillator  10 . First, the signals at nodes  24 ,  26  and  28  do not begin to transition until the respective inverter input signal crosses the triggering threshold (indicated in dashed line), which in this example is VDD/ 2  (where VDD represents a fixed power supply voltage). Second, rise and fall times, t r  and t f , are equal. Finally, slewing is linear. 
     The frequency of the oscillator shown in  FIG. 1A  can be expressed in terms of rise and fall times by recognizing that a cycle comprises a rising edge, a falling edge, a peak and a trough. As the first of the above-mentioned assumptions or simplifications is that an inverter input signal must reach VDD/2 before any change in the inverter output signal can occur, the flat peak of the signal at node  26  can be attributed to the time need for the signal at node  24  to rise from ground to the triggering threshold. Consequently, the duration of this peak is equal to half of the rise time. Likewise, the flat trough of signal  26  is determined by the time needed for the signal at node  24  to drop from VDD to the triggering threshold and is equal to half the fall time. Summing these times yields a frequency of 
     
       
         
           
             
               
                 
                   
                     f 
                     0 
                   
                   = 
                   
                     
                       1 
                       
                         
                           t 
                           r 
                         
                         + 
                         
                           t 
                           f 
                         
                         + 
                         
                           
                             1 
                             2 
                           
                            
                           
                             t 
                             r 
                           
                         
                         + 
                         
                           
                             1 
                             2 
                           
                            
                           
                             t 
                             f 
                           
                         
                       
                     
                     = 
                     
                       
                         1 
                         
                           
                             3 
                             2 
                           
                            
                           
                             ( 
                             
                               
                                 t 
                                 r 
                               
                               + 
                               
                                 t 
                                 f 
                               
                             
                             ) 
                           
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     The frequency of ring oscillator  10  can also be expressed in terms of the delay associated with each inverter, t d  (labeled “td” in  FIG. 1B  to aid readability). The delay is defined as the interval between input and output threshold crossings. It can be noted that the delay depends on whether the inverter is driven by a rising, t dr , or falling edge, t df . The two are only equal when the rise and fall times are equal, that is, t dr =t df ≡t d  when t r =t f , as in this example. Using this definition, the frequency of ring oscillator  10  can alternatively be expressed as 
     
       
         
           
             
               
                 
                   
                     f 
                     0 
                   
                   = 
                   
                     
                       1 
                       
                         2 
                          
                         
                             
                         
                          
                         
                           nt 
                           d 
                         
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     In equation (3), n is the number of stages, and the division by two reflects the fact that the signal must circulate around the ring twice before it completes a full cycle. Equating equations (2) and (3) for n=3 gives t d =¼(t r +t f ). As linear and identical slew rates are assumed in this example, a third frequency formula can be written by substituting t r =t f =V DD C 1 /I into equation (2): 
     
       
         
           
             
               
                 
                   
                     f 
                     0 
                   
                   = 
                   
                     I 
                     
                       3 
                        
                       
                           
                       
                        
                       
                         V 
                         DD 
                       
                        
                       C 
                        
                       
                           
                       
                        
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     where I is the charging/discharging output current of each of inverters  12 ,  14  and  16 . 
     As reflected in equation (4), it is known to control ring oscillator frequency by manipulating one or more of the current, the voltage swing or the capacitance. 
     As shown in  FIG. 2 , one known method for providing increased frequency tuning range in a ring oscillator by manipulating capacitance involves including a network of binary-weighted, digitally programmable, switched capacitors  30 - 46  at the inverter output nodes to increase the tuning range. With the inclusion of capacitors  30 - 46 , the frequency of ring oscillator  10 ′ becomes 
     
       
         
           
             
               
                 
                   
                     f 
                      
                     
                       ( 
                       
                         
                           V 
                           tune 
                         
                         , 
                         d 
                       
                       ) 
                     
                   
                   = 
                   
                     
                       I 
                        
                       
                         ( 
                         
                           V 
                           tune 
                         
                         ) 
                       
                     
                     
                       3 
                        
                       
                           
                       
                        
                       
                         
                           V 
                           DD 
                         
                          
                         
                           ( 
                           
                             
                               C 
                                
                               
                                   
                               
                                
                               1 
                             
                             + 
                             
                               dC 
                               LSB 
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     where “C LSB ” corresponds to the amount of capacitance added to the output of each of inverters  12 ′,  14 ′ and  16 ′ for a unit decrease in the digital control word d (i.e., the least-significant bit (LSB) of d). This capacitance, C LSB , is represented by capacitors  34 ,  40  and  46  in  FIG. 2 . In equation (5), and with reference to  FIG. 2 , I is assumed to be a function of the analog tuning voltage, V tune , the number of capacitors in the array are m, and the digital word allowing the array to function as a programmable load is d. In  FIG. 2 , the least significant bit of this digital word d is labeled “d[ 0 ],” the next most-significant bit is labeled “d[ 1 ],” etc., through the most-significant bit “d[m−1].” Solving equation (5) for a range of values of V tune  produces a continuous range of frequencies referred to as a tuning curve. The position of the tuning curve depends on d. Tuning curves for all possible values of d in this example, i.e., d=0 through d=2 m −1, yields a “family” of curves, as illustrated in  FIG. 3 . 
     It is assumed in  FIG. 3  that the current is a linear function of V tune ; however, this is not always the case. When d=0, all of the switched capacitors  30 - 46  are disconnected, and the original tuning range, f′(max)≦f≦f(min), is retained. The gain for this setting, K vco (0), is identical to that of ring oscillator  10  described above with regard to  FIG. 1 , i.e., without switched capacitors  30 - 46 . Using the digitally controlled capacitors  30 - 46 , the tuning range is expanded to f(min)≦f≦f(max). Therefore, adding digitally programmable, switched capacitors  30 - 46  significantly increases the tuning range. Although in the example shown in  FIG. 3  the tuning curve only moves lower in frequency, in practice a ring oscillator circuit can be designed to oscillate at the desired or selected frequency when V tune  is centered and d=2 m−1 . Then the expanded tuning range that is added by the switched capacitors can be used to correct positive and negative frequency variations. 
     Although ring oscillator  10  shown in  FIG. 2  is an improvement over simply increasing the analog tuning range, there are significant drawbacks. A major drawback is the added IC die area consumed by the switched capacitors  30 - 46 . Note that a capacitor array is needed for each of the n stages, multiplying the area cost by n as well. An often overlooked but potentially serious penalty for such enormous circuit growth is the parasitic capacitance associated with interconnecting the capacitor arrays. For high frequency oscillators, this unanticipated load can be extremely problematic. 
     Another disadvantage stems from the nonlinear nature of using capacitance as a method of frequency control. As capacitance is in the denominator of equation (5), its relationship to frequency is on the order of 1/x. This causes more significant bits to produce progressively smaller frequency shifts. This behavior is reflected in  FIG. 3  by the tuning curves moving closer together as d increases. The nonlinear behavior of switching capacitance also affects the gain of the oscillator, which is determined by taking the partial derivative of the frequency with respect to the tuning voltage, 
     
       
         
           
             
               
                 
                   
                     
                       K 
                       VCO 
                     
                      
                     
                       ( 
                       d 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         ∂ 
                         
                           
                             f 
                             0 
                           
                            
                           
                             ( 
                             
                               
                                 V 
                                 tune 
                               
                               , 
                               d 
                             
                             ) 
                           
                         
                       
                       
                         ∂ 
                         
                           V 
                           tune 
                         
                       
                     
                     = 
                     
                       
                         α 
                         
                           3 
                            
                           
                               
                           
                            
                           
                             
                               V 
                               DD 
                             
                              
                             
                               ( 
                               
                                 
                                   C 
                                    
                                   
                                       
                                   
                                    
                                   1 
                                 
                                 + 
                                 
                                   dC 
                                   LSB 
                                 
                               
                               ) 
                             
                           
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     In equation (6) the assumption of linear voltage-to-current conversion is maintained, and a represents the constant transconductance. In equation (6) K vco , varies inversely with the amount of switched capacitance programmed into the circuit. In  FIG. 3  this result is expressed as a decrease in slope of tuning curves as d increases. In other words, K vco (0)&gt;K vco (2 m −1). 
     As noted above with regard to equation (4), it is also known to control ring oscillator frequency by manipulating the current. As illustrated in  FIG. 4A , a known method for providing increased frequency tuning range in a ring oscillator by manipulating current involves combining a ring oscillator  50  with a programmable switched-resistor-based voltage-to-current converter  52 . A resistance R is provided by a number of series-connected switched resistances  54 ,  56 ,  58 , etc. The resistance R is coupled to the drain of a transistor  60  and an input of an operational amplifier (op-amp)  62 . The other input of op-amp  62  receives the tuning voltage signal V tune . The drain current of transistor  60 , I D =V tune /R, can be programmed by setting the switched resistances  54 ,  56 ,  58 , etc., to result in a selected value of R. This drain current I D  is mirrored by two other transistors  64  and  66  to bias ring oscillator  50 . An advantage of this current-based approach over the above-described capacitance-based approach is that less IC die area is required due to the circuit not needing to be replicated n times. However, since the bias current is inversely proportional to the resistance, this method, in which bias current is indirectly adjusted by setting resistor values, suffers from the same nonlinearity as the capacitor-based approach described above with regard to  FIG. 2 . Furthermore, duplicating the family of tuning curves attained by using switched-capacitor networks with switched bias currents requires attention to subtle circuit design details within the ring oscillator itself, if good linearity is to be maintained. 
     It would be desirable to provide a voltage-controlled ring oscillator having a large frequency tuning range without sacrificing linearity or IC die area efficiency. The present invention addresses these concerns and others in the manner described below. 
     SUMMARY 
     Embodiments of the invention relate to a voltage-controlled ring oscillator in which one or more controllable current sources generate a ring oscillator bias current in response to a tuning voltage. Controlling current sources directly rather than controlling a resistance or capacitance can promote frequency tuning linearity. 
     In accordance with a feature that can be included in embodiments of the invention, the ring oscillator circuit transistors can be sized relative to one another to skew the rise and fall times of the ring oscillator output signal with respect to one another. For example, the rise time can be significantly greater than the fall time. Such skewing can promote frequency tuning linearity. 
     In accordance with another feature that can be included in embodiments of the invention, a peak limiter can limit the oscillation amplitude in response to the bias current. Such limiting can promote frequency tuning linearity. 
     In accordance with still another feature that can be included in embodiments of the invention, a controllable current source can include a voltage-to-current converter and one or more groups of digitally controlled current source transistors. The current source transistors can receive a current from the voltage-to-current converter and produce an output current in response. The output current produced by such a group of digitally controlled current source transistors can be used to bias the oscillator circuit, a peak limiter (in an embodiment in which a peak limiter is included), or both. 
     Other systems, methods, features, and advantages of the invention will be or become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       The components within the figures are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts throughout the different views. 
         FIG. 1A  is a circuit diagram of a ring oscillator in accordance with the prior art. 
         FIG. 1B  is a waveform diagram showing waveforms of signals during operation of the ring oscillator of  FIG. 1 . 
         FIG. 2  is a block diagram of a ring oscillator that includes switched capacitors, in accordance with the prior art. 
         FIG. 3  is a plot showing oscillation frequency (f) versus voltage (V) for various settings of the switched capacitors of the ring oscillator of  FIG. 2 . 
         FIG. 4  is a circuit diagram of a ring oscillator that includes switched resistances for generating selectable a ring oscillator bias current, in accordance with the prior art. 
         FIG. 5  is a circuit diagram of a voltage-controlled ring oscillator in accordance with an exemplary embodiment of the invention. 
         FIG. 6  is a waveform diagram showing waveforms of signals during operation of the ring oscillator of  FIG. 5 . 
         FIG. 7  is a circuit diagram showing the ring oscillator of  FIG. 5  in further detail. 
         FIG. 8A  is a waveform diagram showing the operation of the peak limiter in the ring oscillator of  FIGS. 5 and 7 . 
         FIG. 8B  is a partial circuit diagram showing currents in a first region of operation of the peak limiter in the ring oscillator of  FIGS. 5 and 7 . 
         FIG. 8C  is a partial circuit diagram showing currents in a second region of operation of the peak limiter in the ring oscillator of  FIGS. 5 and 75 . 
         FIG. 8D  is a partial circuit diagram showing currents in a third region of operation of the peak limiter in the ring oscillator of  FIGS. 5 and 7 . 
         FIG. 9A  illustrates a family of tuning curves representing various operational settings of the ring oscillator of  FIGS. 5 and 7 . 
         FIG. 9B  is similar to  FIG. 9A  and illustrates another family of tuning curves representing various other operational settings of the ring oscillator of  FIGS. 5 and 7 . 
     
    
    
     DETAILED DESCRIPTION 
     As illustrated in  FIG. 5 , in accordance with an illustrative or exemplary embodiment of the invention, a voltage-controlled ring oscillator  70 , which can be provided in integrated circuit (IC) form, provides analog and digital frequency tuning in the current domain as well as selectable combinations of gain and frequency range. As illustrated in  FIG. 5 , voltage-controlled ring oscillator  70  comprises or includes a ring oscillator circuit  72 , a bias current generator  74 , and a peak limiter  76 . Although in the exemplary embodiment ring oscillator circuit  72  includes three inverters  78 ,  80  and  82  for purposes of illustration, in other embodiments such a ring oscillator circuit can include any number of inverters or similar circuits. 
     Bias current generator  74  includes a programmable tuning current (PTC) source  84  and a programmable fixed current (PFC) source  86 . PTC source  84  includes first and second controllable, i.e., variable, full current sources  88  and  90 , and first and second controllable scaled current sources  89  and  91 . First controllable full current source  88  can be controlled in response to the analog tuning voltage signal V tune  (labeled “Vtune” in the drawing figures to aid readability). That is, first controllable full current source  88  produces a current having a magnitude that reflects the selected value of V tune . First controllable scaled current source  89  produces a scaled-down version of the current that first controllable full current source  88  produces. Similarly, second controllable full current source  90  can be controlled in response to both V tune  and a digital tuning signal V tune [k]. Second controllable scaled current source  91  produces a scaled-down or proportional version of the current that second controllable full current source  90  produces. PFC source  86  includes a controllable full current source  92  that can be controlled in response to another digital tuning signal V tune [j] and a fixed full current source  94  that produces a fixed or constant current. PFC source  86  further includes a controllable scaled current source  93  that produces a scaled-down version of the current that controllable full current source  92  produces and a fixed scaled current source  95  that produces a scaled-down or proportional version of the current that fixed full current source  94  produces. The sum of the (full) currents generated by PTC source  84  and PFC source  86  defines a bias current that is provided to each of inverters  78 ,  80  and  82  of ring oscillator circuit  70 . The sum of the scaled-down versions of those currents is provided to peak limiter  76 . The total bias current provided to peak limiter  76  is thus proportional to the total bias current provided to ring oscillator circuit  70 . 
     Both digital and analog inputs are provided so that the bias current can be adjusted or varied in a flexible manner by adjusting the analog tuning voltage signal V tune  to a selected value while holding the digital values of V tune [j] and V tune [k] constant. Although this exemplary mode of operation is contemplated and discussed in further detail below, it should be noted that any of V tune , V tune [j] and V tune [k] can be adjusted alone or in combination with each other or with other signals in any suitable manner Also, it should be noted that even though PFC source  86  can be controlled or varied in response to V tune [j], the term “fixed” is not intended to be limiting and is used only for purposes of convenience of description, in view of the exemplary mode of operation in which V tune [j] is held constant or fixed while V tune  is adjusted. 
     As ring oscillator circuit  70  is current biased, its “supply voltage,” V s  (labeled “Vs” in  FIG. 5  to aid readability), is the product of the bias current received from bias current generator  74  and the equivalent time-varying impedance of inverters  78 ,  80  and  82  in parallel. Consequently, this supply voltage and the ring oscillation amplitude tend to follow movements in the bias current. This behavior can be compared with the prior ring oscillator  10  described above with regard to  FIG. 1 , which is biased with an ideal supply voltage and will therefore oscillate at an amplitude approximately equal to that supply voltage. In the derivations described above with regard to  FIGS. 1-4 , constant oscillation amplitude is assumed irrespective of bias current. As it is desirable to maintain a constant oscillation amplitude in order to promote tuning linearity, peak limiter  76  is employed to maintain the oscillation amplitude at a level below that of the minimum V s . The operation of peak limiter  76  is described below in further detail with regard to  FIGS. 8A-8D . 
     As illustrated in  FIG. 7 , in ring oscillator circuit  72 , inverter  78  includes a PFET  96  and a corresponding NFET  98 , inverter  80  includes a PFET  100  and a corresponding NFET  102 , and inverter  82  includes a PFET  104  and a corresponding NFET  106 . The source terminal of each of PFETs  96 ,  100  and  104  is connected to the output of PTC source  84  and PFC source  86  to receive the bias current. Ring oscillator circuit  72  further includes PFETs  108 ,  110  and  112 , each of which has a source terminal connected to one of the ring oscillator nodes  114 ,  116  and  118 , respectively. 
     The transistor arrangement of ring oscillator circuit  72  in which the source terminals of PFETS  96 ,  100  and  104  receive the bias current provides control over the charging current available to each of inverters  78 ,  80  and  82  but not the discharge current. In other words, this transistor arrangement allows control of the oscillation signal rise time t r  but not the oscillation signal fall time t f . To facilitate control over the oscillation signal fall time t f , a means for skewing the oscillation signal rise and fall times can be provided such that, for example, the oscillation signal rise time t r  is substantially greater than the oscillation signal fall time t f , i.e., t r &gt;&gt;t f . It is known that the oscillation signal rise and fall times in a ring oscillator are dependent upon the sizes of the NFET and PFET, i.e., the area of the integrated circuit die on which they are formed, relative to one another. It is also known that for the oscillation signal rise time t r  and fall time t f  to be equal to one another, the ratio between PFET area and NFET area should be about 3:1, because PFET mobility and thus transconductance is approximately one-third that of an NFET. In the exemplary embodiment, rise and fall times can be skewed by sizing the NFET substantially larger than the corresponding PFET. 
     With regard to  FIG. 7 , in forming each of NFETs  98 ,  102  and  106  and PFETs  96 ,  100  and  104  on respective areas of the integrated circuit die (not shown for purposes of clarity), a ratio of the area occupied by a PFET to the area occupied by the corresponding NFET can be less than 3:1. For example, the ratio can be about 1:1. Accordingly, PFET transconductance is approximately ⅓ NFET transconductance, resulting in a longer rise time t r  than fall time t f . Although in the exemplary embodiment the PFET-to-NFET size ratio is less than about 3:1 (e.g., about 1:1), in other embodiments it can be any suitable number that results in substantially unequal or skewed rise and fall times. Thus, for example, the PFET-to-NFET size ratio can be any that is substantially less than 3:1. The term “substantially” as used herein means by an amount greater than that which would typically occur as a result of unintended, insubstantial variances in IC fabrication process, ambient temperature, etc. Also, in selecting the PFET and NFET sizes, each of inverters  78 - 82  should have a mean inverter delay, ½(t dr +t df ), that is substantially the same as the delay would be if the inverter were to have a PFET-to-NFET size ratio of about 3:1. Exemplary waveforms at nodes  114 ,  116  and  118  that can result from skewing the inverter rise and fall times in this manner are shown in  FIG. 6 . 
     In view of the skewed rise and fall times, the oscillation frequency can be expressed as 
     
       
         
           
             
               
                 
                   
                     
                       f 
                       0 
                     
                     = 
                     
                       
                         1 
                         
                           
                             3 
                             2 
                           
                            
                           
                             ( 
                             
                               
                                 t 
                                 r 
                               
                               + 
                               
                                 t 
                                 f 
                               
                             
                             ) 
                           
                         
                       
                       ≈ 
                       
                         3 
                         
                           2 
                            
                           
                               
                           
                            
                           
                             t 
                             r 
                           
                         
                       
                     
                   
                   , 
                   
                     
                       t 
                       r 
                     
                     &gt;&gt; 
                     
                       
                         t 
                         f 
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     In equation (7) the constant 3/2 becomes an approximation due to a slight lowering of the threshold voltage associated with the unequal PFET and NFET sizes. Because each cycle is now dominated by a long rise time, controlling this duration via charging current results in linear tuning As t r =V sw C/I bias , and as I bias  in the exemplary embodiment is the output of current sources  88 - 94 , V sw  in the exemplary embodiment is the peak-to-peak voltage set by peak limiter  76  at each of nodes  114 ,  116  and  118 . It can thus be appreciated that peak limiting and skewing promote linearity of current-mode frequency tuning. (It should be noted that although both peak limiting and skewing are included in the exemplary embodiment, in other embodiments including only one or the other can still promote linearity.) Substituting the above-referenced relation into (6), the oscillation frequency becomes 
     
       
         
           
             
               
                 
                   
                     f 
                     0 
                   
                   ≈ 
                   
                     
                       3 
                        
                       
                           
                       
                        
                       
                         I 
                         bias 
                       
                     
                     
                       2 
                        
                       
                           
                       
                        
                       
                         V 
                         sw 
                       
                        
                       C 
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
     An added benefit of skewing the rise and fall times emerges in considering phase noise. Popular theory suggests that the upconversion of flicker noise is increased as waveform symmetry is decreased. However the flicker noise of deep submicron NFETs is several times greater than that of similarly sized PFETs. Comparing the phase noise of a symmetric oscillator with a skewed oscillator at the same frequencies and power consumption reveals that the reduction in flicker noise achieved by increasing/decreasing the size of the NFETs/PFETs overrides any increase in upconversion due to asymmetry. Therefore, in deep submicron IC process, skewing may offer better phase noise performance than a symmetric approach. 
     With reference again to  FIG. 7 , PTC source  84  includes a voltage-to-current converter  119  comprising an operational amplifier (op-amp)  120 , resistors  122  and  124 , a capacitor  126 , and a PFET  128 . The analog tuning voltage V tune  is sensed at the positive input terminal of op-amp  120 . The output of op-amp  120  is applied to the gate terminal of PFET  120 , the drain terminal of which is connected to resistor  122 . The voltage across resistor  124  (the resistance of which can be designated “R 124 ”) is applied to the negative terminal of op-amp  120  to complete a unity gain feedback loop. The drain current I D128  of PFET  128  is linearly proportional to the tuning voltage: I D128 =V tune /R 124 . Resistor  124  can be made as large as noise specifications will permit in order to minimize current consumption. Op-amp  120 , PFET  128  and resistor  124  define a multi-pole system that is compensated by resistor  122  and capacitor  126 . Voltage-to-current converter  119  linearly converts the analog tuning voltage V tune  to a current. It is desirable to maintain linearity across the entire tuning voltage range as maintaining linearity directly affects the overall linearity of the voltage-to-frequency conversion aspect of voltage-controlled ring oscillator  70 . 
     The output of op-amp  120  is also applied to the gate of PFET  150 , which serves as first controllable full current source  88  of PTC source  84 . As described above with regard to  FIG. 5 , first controllable full current source  88  provides a current in response to the analog tuning voltage V tune . Similarly, the output of op-amp  120  is also applied to the gate of PFET  130 , which serves as second controllable scaled current source  89  of PTC source  84 . 
     Second controllable full current source  90  of PTC source  84  provides a current in response to the digital tuning signal V tune [k]. First controllable scaled current source  91  includes PFETs  132 ,  134 ,  136 ,  138 ,  140 ,  142 ,  144 ,  146  and  148 . Second controllable full current source  90  includes PFETs  152 ,  154 ,  156 ,  158 ,  160 ,  162 ,  164 ,  166  and  168 . PFETs  156 ,  162  and  168  serve as current source transistors and are indirectly connected to the output of op-amp  120  through PFETs  152 ,  154 ,  158 ,  160 ,  164  and  166 , which serve as switching transistors. These switching transistors operate in pairs in response to the 3-bit digital word k[ 2 : 0 ], which is the same as V tune [k] shown in  FIG. 5 . The pair of PFETs  152  and  154  are driven by complementary signals k*[ 0 ] and k[ 0 ], respectively. The pair of PFETs  158  and  160  are driven by complementary signals k*[ 1 ] and k[ 1 ], respectively. The pair of PFETs  164  and  166  are driven by complementary signals k*[ 2 ] and k[ 2 ], respectively. Although in the exemplary embodiment second controllable full current source  90  has three current source transistors and associated pairs of switching transistors, in other embodiments such a controllable current source can have any number of current source transistors and any number and arrangement of switching transistors. 
     Using PFETs  152 ,  154  and  156  as an example, the operation of controllable current source  90  can be described as follows: When digital signal k[ 0 ] is asserted, the gate of PFET  154  is at the supply voltage (VDD) and PFET  154  is therefore off. The digital signal k*[ 0 ] is at ground, which switches PFET  152  on, thereby connecting the output voltage of op-amp  120  to the gate of PFET  156 . In this state, PFET  156  also behaves as a voltage-controlled current source, and its output current adds to that of PFET  150 . Therefore, in the exemplary embodiment the tunable current biasing ring oscillator circuit  72  features both analog and digital controls. Conversely, when k[ 0 ] is at ground, PFET  154  is turned on, and the gate of PFET  156  is pulled to VDD, turning PFET  156  off. Simultaneously, k*[ 0 ] is at VDD, turning off PFET  152  and breaking the connection between the output of op-amp  120  and the gate of PFET  156 . In this state, PFET  156  has no effect on the circuit. PFETs  162  and  168  are similarly controlled by digital signals k[ 1 ] and k[ 2 ], respectively, through respective PFET pairs. 
     As PFETs  132 - 148  are arranged in the same manner and operate in the same manner as described above with regard to PFETs  152 - 168 , the arrangement and operation is not described herein in similar detail. However, while the “full” current that is output by second controllable full current source  90  is provided to ring oscillator circuit  70  as a bias current, the “scaled-down” current that is output by first controllable scaled current source  91  is provided to peak limiter  76  as a bias current. The operation of peak limiter  76  is described below in further detail. 
     The total output current of PTC source  84  is 
     
       
         
           
             
               
                 
                   
                     
                       
                         I 
                         tune 
                       
                        
                       
                         ( 
                         
                           
                             V 
                             tune 
                           
                           , 
                           k 
                         
                         ) 
                       
                     
                     = 
                     
                       α 
                        
                       
                           
                       
                        
                       
                         
                           V 
                           tune 
                         
                          
                         
                           ( 
                           
                             1 
                             + 
                             
                               k 
                               ρ 
                             
                           
                           ) 
                         
                       
                     
                   
                   , 
                   
                     α 
                     = 
                     
                       
                         w 
                         12 
                       
                       
                         
                           w 
                           1 
                         
                          
                         R 
                          
                         
                             
                         
                          
                         1 
                       
                     
                   
                   , 
                   
                     ρ 
                     = 
                     
                       
                         
                           w 
                           12 
                         
                         
                           w 
                           15 
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
     In equation (9), w refers to (PFET) transistor width, a is the gain or transconductance, p determines the minimum current step, and k is the digital word in decimal. The lengths of PFETs  128 ,  130 ,  136 ,  142 ,  148 ,  150 ,  156 ,  162  and  168  are equal. (The length and width are those defining the area on the die on which the transistor is formed.) 
     Like above-described PTC source  84 , PFC source  86  includes a voltage-to-current converter  174  comprising an operational amplifier (op-amp)  176 , resistors  178  and  180 , a capacitor  182 , and a PFET  184 . Indeed, in the exemplary embodiment the entire structure of PFC source  86  is identical to that of PTC source  88 , but op-amp  176  references a fixed or constant bandgap voltage V bg  (labeled “Vbg” in  FIG. 7  to aid readability), which serves as a reference voltage. Structuring PFC source  86  and PTC source  88  identically provides strong immunity to variations in process, supply voltage and temperature or “PVT.” Op-amp  174 , PFET  184  and resistor  180  (the resistance of which can be designated “R 180 ”) form a unity gain feedback loop with the drain current of PFET  184 , I D =V bg R 180 . Resistor  178  and capacitor  182  compensate the loop. In order to further reduce PVT sensitivity, resistor  178  and resistor  180  can be matched, meaning they can be of identical construction, orientation, aspect ratio, etc. Matching resistors  178  and  180  can help ensure that the ratio of fixed current to tuning current is accurate and the oscillation frequency is correct. 
     The output of op-amp  174  is also applied to the gates of PFETs  206  and  186 , which serve as fixed full current source  94  and fixed scaled current source  95 , respectively, of PFC source  86 . Fixed current sources  94  and  95  provide currents in response to the bandgap voltage V bg  alone and are thus not user-controllable, i.e., their output current is “fixed” in relation to V bg . Controllable full current source  92  of PFC source  86  provides a current in response to the digital tuning signal V tune [j].Controllable scaled current source  93  includes PFETs  188 ,  190 ,  192 ,  194 ,  196 ,  198 ,  200 ,  202  and  204 . Controllable full current source  92  includes PFETs  208 ,  210 ,  212 ,  214 ,  218 ,  220 ,  222  and  224 . Of these, PFETs  212 ,  218  and  224  serve as current source transistors and are indirectly connected to the output of op-amp  176  through PFETs  208 ,  210 ,  214 ,  216 ,  220  and  222 , which serve as switching transistors in the same manner as those of above-described controllable current source  90 , operating in pairs in response to the 3-bit digital word j[ 2 : 0 ], which is the same as V tune [j] shown in  FIG. 5 . As controllable current source  92  operates in the same manner as described above with regard to controllable current source  90 , the description of this operation is not repeated in similar detail. 
     PFETs  186 - 204  provide a bias current to peak limiter  76  in essentially the same manner as that described above with regard to PFETs  130 - 148 . Likewise, PFETs  206 - 224  provide a bias current to ring oscillator circuit  72  that is a scaled-down version of the bias current provided to peak limiter  76 . The total output current of PFC source  86  is 
     
       
         
           
             
               
                 
                   
                     
                       
                         I 
                         fixed 
                       
                        
                       
                         ( 
                         j 
                         ) 
                       
                     
                     = 
                     
                       β 
                        
                       
                           
                       
                        
                       
                         
                           V 
                           bg 
                         
                          
                         
                           ( 
                           
                             1 
                             + 
                             
                               j 
                               γ 
                             
                           
                           ) 
                         
                       
                     
                   
                   , 
                   
                     β 
                     = 
                     
                       
                         w 
                         33 
                       
                       
                         
                           w 
                           22 
                         
                          
                         
                           R 
                           4 
                         
                       
                     
                   
                   , 
                   
                     γ 
                     = 
                     
                       
                         
                           w 
                           33 
                         
                         
                           w 
                           36 
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
     Analogous to equation (8), w refers to (PFET) transistor width, β is the transconductance, determines the minimum current step, and j is the digital word in decimal. The lengths of PFETs  186 ,  188 ,  192 ,  198 ,  204 ,  206 ,  212 ,  218  and  224  are equal. 
     An added advantage of the op-amp-based voltage-to-current conversion used in both PTC source  84  and PFC source  86  is excellent power supply rejection. Noise on VDD will be attenuated by gm 184 R 124 A 1  and gm 184 R 180 A 2  in the PTC and PFC respectively (where gm 128  and gm 184  represent the transconductances of PFETs  128  and  184 , respectively, and A 1  and A 2  represent the voltage gains of op-amps  120  and  176 , respectively. The magnitude and bandwidth of the suppression is dependent on the op-amp characteristics rather than ring oscillator circuit  72 , thus facilitating optimization of power supply rejection independently of other oscillator circuit specifications. 
     Peak limiter  76 , which comprises an op-amp  230  and a PFET  232 , improves linearity by holding the oscillation amplitude in ring oscillator circuit  72  constant regardless of the bias current received by ring oscillator circuit  72 . The circuitry of peak limiter  76  forms a feedback loop that references a voltage, V ref , to set the amplitude peak and a scaled down copy of the bias current received by ring oscillator circuit  72  to detect tuning changes. This current is generated by PFETs  130 - 148  in PTC source  84  and PFETs  186 - 204  in PFC source  86 . Op-amp  230  sets the gate terminal voltage of PFET  232  such that its drain terminal voltage is equal to  V   ref . As the bias current received by ring oscillator circuit  72  varies with the analog tuning voltage V tune  and the above-described digital tuning words V tune [j] and V tune [k] the gate bias of PFET  232  adjusts to prevent any voltage change at its source terminal The output of op-amp  176  is also applied to the gates of PFETs  108 ,  112  and  112 , the source terminals of which are connected to ring oscillator nodes  114 ,  116  and  118 , respectively. Because the bias current for peak detector  76  is scaled down from the bias current received by ring oscillator circuit  72 , PFETs  108 ,  110  and  112  can be scaled up from PFET  232  by the same ratio. 
     As illustrated in  FIGS. 8A-D , inverter  78  (PFET  96  and NFET  98 ) and PFET  108  can conduct over three distinct regions  234 ,  236  and  238 . At time t=0 ( FIG. 8A ), the gate terminals of PFET  96  and NFET  98  have just transitioned to ground (GND), turning NFET  98  off. V x  starts to rise in region  234  as PFET  96  supplies current to capacitance  240 , as illustrated in  FIG. 8B . PFET  108  is off, as V x &lt;V b +V th (PMOS) (where v th (PMOS) is the triggering threshold of a P-type MOSFET such as PFET  108 ). Region  236  begins when V x ≧V b V th (PMOS). PFET  108  will gradually turn on and shunt current that would otherwise be used to charge capacitance  108 , as illustrated in  FIG. 8C . As V x  continues to rise, the conducting strength of PFET  108  increases, siphoning even more current. Region  238  is reached when V x =V ref  and PFET  108  becomes capable of conducting the current of PFET  96  in its entirety, preventing any further voltage increase, as illustrated in  FIG. 8D . 
     Tuning voltage changes vary the bias current received by ring oscillator circuit  72 , which is mirrored to peak detector  76 , allowing peak detector  76  to compensate by automatically adjusting V b . This modulates the conductive strength of PFETs  108 ,  110  and  112  and forces the oscillation amplitude to remain constant as it is tuned. Furthermore, as PFETs  108 ,  110  and  112  are only active toward the peak of the cycle, they and the rest of the circuitry of peak limiter  76  contribute little to the overall phase noise of voltage-controlled ring oscillator  70 . 
     The crowbar current of NFET  98  as it begins to turn on toward the peak of V x  can also be considered. Because this crowbar current also reduces the total current available to charge capacitance  240 , the crowbar current can be accounted for by a slight size reduction in PFETs  108 ,  110  and  112 . 
     Referring again to  FIG. 7 , the core of ring oscillator circuit  72  comprises three identical PFETs  96 ,  100  and  104  and three identical NFETs  98 ,  102  and  106 . Both types of transistors have the same length, and the PFET/NFET width ratio is less than one to produce skewed rise and fall times, as described above. The output can be buffered by an inverter or buffer  242  to reduce oscillator loading. The source terminals of PFETs  96 ,  100  and  104  are shorted together and driven by the summed currents output by PTC source  84  and PFC source  86 . 
     The above-described architecture or structure of ring oscillator  70  provides linear voltage to frequency conversion as well as a flexible means for selecting combinations of gain and frequency range. Substituting equations (9) and (10) into equation (8), the oscillation frequency is 
     
       
         
           
             
               
                 
                   
                     
                       f 
                       vco 
                     
                      
                     
                       ( 
                       
                         
                           V 
                           tune 
                         
                         , 
                         k 
                         , 
                         j 
                       
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
                           α 
                            
                           
                               
                           
                            
                           
                             
                               V 
                               tune 
                             
                              
                             
                               ( 
                               
                                 1 
                                 + 
                                 
                                   k 
                                   ρ 
                                 
                               
                               ) 
                             
                           
                         
                         + 
                         
                           β 
                            
                           
                               
                           
                            
                           
                             
                               V 
                               bg 
                             
                              
                             
                               ( 
                               
                                 1 
                                 + 
                                 
                                   j 
                                   γ 
                                 
                               
                               ) 
                             
                           
                         
                       
                       
                         
                           3 
                           2 
                         
                          
                         
                           V 
                           ref 
                         
                          
                         C 
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
     Note in equation (11) that V sw  can be represented by V ref  because of the effect of peak limiter  76 . The oscillation frequency can be expressed as a function of the analog tuning voltage V tune  and the two independent digital tuning signals  tune [j] and V tune [k]. The gain of ring oscillator  70  is found by taking the partial derivative of equation ( 10 ) with respect to V tune . 
     
       
         
           
             
               
                 
                   
                     
                       K 
                       vco 
                     
                      
                     
                       ( 
                       
                         
                           V 
                           tune 
                         
                         , 
                         k 
                       
                       ) 
                     
                   
                   = 
                   
                     
                       
                         ∂ 
                         
                           
                             f 
                             osc 
                           
                            
                           
                             ( 
                             
                               
                                 V 
                                 tune 
                               
                               , 
                               k 
                             
                             ) 
                           
                         
                       
                       
                         ∂ 
                         
                           V 
                           tune 
                         
                       
                     
                     = 
                     
                       
                         
                           α 
                            
                           
                             ( 
                             
                               1 
                               + 
                               
                                 k 
                                 ρ 
                               
                             
                             ) 
                           
                         
                         
                           
                             3 
                             2 
                           
                            
                           
                             V 
                             ref 
                           
                            
                           C 
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
     Equation (12) shows that K vco  has no dependence on V tune , indicating completely linear voltage-to-frequency transfer function, as is desirable. In addition, the presence of k allows K vco  to be digitally adjusted. Taking the partial derivative of equation (10) with respect to j gives 
     
       
         
           
             
               
                 
                   
                     K 
                     vco 
                   
                   = 
                   
                     
                       
                         ∂ 
                         
                           
                             f 
                             osc 
                           
                            
                           
                             ( 
                             
                               
                                 V 
                                 tune 
                               
                               , 
                               k 
                               , 
                               j 
                             
                             ) 
                           
                         
                       
                       
                         ∂ 
                         j 
                       
                     
                     = 
                     
                       
                         
                           
                             β 
                             γ 
                           
                            
                           
                             V 
                             bg 
                           
                         
                         
                           
                             3 
                             2 
                           
                            
                           
                             V 
                             ref 
                           
                            
                           C 
                         
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
     Equation (13) expresses the change in frequency for a least-significant bit (LSB) change in fixed current. Note that j, k and V tune  are absent from equation (13), indicating that the tuning curves generated by this architecture are identically spaced, as shown in  FIG. 9A . In other words, K vco  is constant regardless of j. This is a marked improvement over a variable K vco  resulting from, for example, prior switched-capacitor or switched-resistor approaches ( FIGS. 2-4 ). 
     As illustrated in  FIG. 9 , voltage-controlled ring oscillator  70  can be operated in a constant gain, uniform digital frequency shift mode by selecting a digital tuning signal V tune [j] while holding the digital value V tune  [k] constant. Alternatively, as illustrated in  FIG. 9B , voltage-controlled ring oscillator  70  can be operated in a programmable gain mode by selecting both digital tuning signals V tune [j] and V tune [k]. 
     Equations (11), (12) and (13) capture the flexibility of the above-described architecture or structure of voltage-controlled ring oscillator  70 . For low and constant K vco  along with a wide tuning range, k can be held constant while j is selectable. The family of tuning curves produced from this configuration is shown in  FIG. 9A . On the other hand, if variable K vco  is needed, then k can be made selectable as well, as shown in  FIG. 9B . Gain programming done this way also results in a frequency shift, which a user of voltage-controlled ring oscillator  70  may or may not desire. This frequency shift can be eliminated for any single tune voltage if k and j are adjusted simultaneously and in opposite directions. In addition, PTC and PTF expressions must be linked. For example, if programmable gain is desired independent of frequency at the center of the tuning range, then 
     
       
         
           
             
               
                 
                   
                     
                       α 
                       / 
                       ρ 
                     
                      
                     
                         
                     
                      
                     
                       
                         V 
                         tune 
                       
                        
                       
                         ( 
                         center 
                         ) 
                       
                     
                   
                   = 
                   
                     
                       β 
                       / 
                       γ 
                     
                      
                     
                         
                     
                      
                     
                       
                         V 
                         bg 
                       
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
           
         
       
     
     This equality states that the analog and digital LSBs should be identical when the tuning voltage is in the center of its range. Now, as k is incremented and j is decremented, the gain will increase and the tuning curves will pivot counter clockwise around V tune (center) and vice versa, as shown in  FIG. 9B . 
     The above-described voltage-controlled ring oscillator  70  provides a large oscillator frequency tuning range while maintaining linearity and constant gain. In addition, linearity can be promoted by controlling the charging current, skewing the rise and fall times of the oscillation signal and limiting the peak amplitude of the oscillation signal. The digital configurability or programmability of voltage-controlled ring oscillator  70  also provides a convenient means for adjusting the oscillator gain if desired, with no additional overhead. 
     While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of this invention. Accordingly, the invention is not to be restricted except in light of the following claims.