Patent Publication Number: US-4929913-A

Title: GaAs focal plane array readout

Description:
CROSS REFERENCE TO RELATED PATENT APPLICATION 
     This patent application is related to copending U.S. Patent Application S.N. 07/151,845, filed Feb. 3, 1988, R. N. Sato, entitled &#34;GaAs Capacitive Feedback Transimpedance Amplifier&#34;. This copending patent application is assigned to the assignee of the present patent application. 
     FIELD OF THE INVENTION 
     This invention relates to a Gallium Arsenide (GaAs) focal plane array (FPA) readout electronics circuit including a Capacitive feedback Transimpedance Amplifier, also referred to as a CTIA, operated at cryogenic temperatures. In particular, this invention relates to a GaAs CTIA having a novel load structure and other features that result in an improved immunity to process-related variables. 
     BACKGROUND OF THE INVENTION 
     FPAs are typically comprised of a two-dimensional array of Infrared (IR) radiation detectors. The individual IR detector elements may be organized in a regular row and column, mosaic-type fashion Such an array of IR detector elements can be comprised of, for example, HgCdTe, InSb, Multiquantum Well Superlattice (MQW SL) material or doped silicon semiconductor material. The IR detector induced signal from each of the IR detector elements is typically coupled to an electronic interface circuit such as a CTIA, a source follower direct readout or a charge coupled device, where each of the signals are integrated over an interval of time and subsequently read out by a suitable multiplexing circuit. Electronic circuits with HgCdTe detector arrays for processing IR induced signals require a significant degree of material compatibility to achieve a long lifetime and reliable operation. Also, interface electronic circuits require low device and circuit noise characteristics for obtaining a satisfactory signal-to-noise ratio. For some applications the circuits must tolerate nuclear radiation in high nuclear radiation environments and also consume low power to achieve both weight and size reduction. 
     Typically, readout chips are coupled to, or &#34;bumped&#34;, with detector arrays at room temperature using indium bump technology. When the chips are rapidly cooled from room temperature to a cryogenic operating temperature stress can build up between the readout circuit and the detector array through the bumping. This stress is most severe if the coefficients of thermal expansion between the materials are different and/or if the chips are large in area. Silicon, the conventional semiconductor material employed for readout circuits, has a poor thermal expansion match with detector materials such as HgCdTe, InSb and GaAs based MQWL SL IR detectors However, other materials such as GaAs are known to have a coefficient of thermal expansion that is closer to that of these detector materials than is the coefficient of expansion of silicon. 
     It is therefore one object of the invention to provide a GaAs FPA signal processor that exhibits a low power consumption and an improved immunity to nuclear radiation (radiation hardness). 
     It is a further object of the invention to provide a GaAs FPA signal processor that exhibits low noise when employed in a FPA signal processor 
     It is still one further object of the invention to provide a GaAs FPA signal processor array that has a coefficient of thermal expansion which is closely matched to that of the material of an associated IR detecting array. 
     Another object of the invention is to provide a GaAs FPA signal processor array that includes a differential pair having an improved load transistor circuit that is substantially insensitive to processing-related variables. 
     SUMMARY OF THE INVENTION 
     In accordance with the invention a transimpedance amplifier includes a differential amplifier constructed of GaAs transistors and has an input for coupling to an output of an infrared detector. The amplifier has an output terminal expressive of the detector signal integrated over an interval of time. A load is coupled between the amplifier output terminal and an amplifier power supply. The load includes an implant resistor having a first terminal coupled to the amplifier output terminal and a second terminal coupled to a first GaAs load transistor. The first load transistor is serially coupled to a second GaAs load transistor. A gate terminal of each of the first and the second load transistors is coupled to the amplifier output terminal. This load circuit is shown to beneficially reduce an effect of processing and transistor parameter variations upon the transimpedance amplifier circuit performance. 
     That is, and in accordance with an aspect of the invention, two transistors Q L2  and Q L3  and one implant resistor R 4  are provided as a load for an amplifier load transistor Q L1 . An amount of current flowing through Q L2  is a function of the magnitude of the resistance of the resistor R 4 , R 4  being connected from the gate terminal to the source terminal of Q L2 . The amount of current flowing is also a function of the threshold voltage, transconductance, and channel conductance of Q L2 . Any variation of this threshold voltage transconductance or channel conductance is compensated for by the resistor R 4 . The gate of Q L3  is connected in common with the gate of Q L2  to one side of the resistor R 4  such that the gate terminal senses the amplifier output voltage variation. Q L3  functions as a source follower coupled to the drain of Q L2  such that the voltage between the drain and the source of Q L2  is forced to maintain a substantially constant voltage level. Thus, both transconductance and channel conductance of Q L2  remain substantially constant. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other aspects of the invention will become more apparent herein in the detailed description of the invention taken in conjunction with the accompanying drawings wherein: 
     FIG. 1 is a block diagram showing the GaAs readout of the present invention; 
     FIG. 2 is a schematic diagram that shows in detail the circuitry of the block diagram of FIG. 1; and 
     FIG. 3 is a timing diagram that illustrates the operation of the circuitry of FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to FIG. 1 there is illustrated in block diagram form a readout unit cell 10. The unit cell 10 is comprised of a CTIA 14 coupled to a photovoltaic p-n or n-p or a photoconductive infrared (IR) detector 12. IR detector 12 is biased to a desired operating point by V det  and is coupled to an input of the CTIA 14. The CTIA 14 is controlled by a plurality of clocks, such as integration command clocks φ1A and φ1B. CTIA 14 is also biased by signals V bias , V Ibias  and V rst . The CTIA 14 is powered by a single power supply voltage (Vdd). The IR induced signal which is integrated by CTIA 14 is provided to a Sample and Hold (S/H) and Multiplexer (MUX) circuit 16. S/H and MUX 16 is controlled by clocks (φ2 and φ3). The multiplexed output of the S/H 16 is a unit cell sampled analog signal (OUTPUT). 
     Referring now to FIG. 2 there is shown a schematic diagram of a presently preferred embodiment of a FPA signal processor unit cell 10. The unit cell 10 is comprised of 13 GaAs metal-semiconductor field effect transistors (MESFETs), five implant resistors and three capacitors. Switching transistors Q 0 , Q 9  and Q 11  are enhancement mode devices. A photovoltaic or photoconductive semiconductor radiation detector, which may be an IR detector 12, senses the variation in photon flux within a specified spectral wavelength range and generates a CTIA input signal voltage that is coupled to the gate of Q 1 . During operation the GaAs CTIA circuit beneficially provides a constant bias voltage feedback signal to the IR detector 12 through a feedback capacitance C f , the feedback signal having a magnitude linearly related to a magnitude of a CTIA 14 output signal appearing at point E 1 . 
     CTIA 14 includes a differential amplifier pair Q 1  and Q 2 . In accordance with an aspect of the invention Q 1  has a load represented by transistors Q L1 , Q L2 , Q L3  and a resistive impedance represented by an implant resistor R 4 . These load devices are serially coupled to a drain terminal of Q 1 . A source terminal of each of the differential amplifier pair Q 1  and Q 2  is coupled to the drain of a transistor Q 3 . Q 3  functioning as a current source. A bias voltage signal V Ibias  has a magnitude the value of which is selected to provide a desired current flow through Q 3  to both Q 1  and Q 2 . Another source of voltage bias, V bias , is provided to the gate of load transistor Q L1  and to the drain of Q 2 . The voltage magnitude of V bias  establishes the drain voltages of both Q 1  and Q 2  at a desired level. In that both Q 1  and Q 2  have substantially identical drain, gate and source voltage levels the devices can be considered to be operated under nearly identical bias conditions, thus ensuring true differential amplifier performance. 
     In order to realize high-yield production, nonuniformity in chip fabrication must be taken into consideration. Chip fabrication typically causes variations in transistor threshold voltage, transconductance, and channel conductance. In accordance with an aspect of the invention fabrication process variations are compensated for by several different mechanisms. First, V bias  compensates for the threshold voltage variation of the differential pair transistors Q 1  and Q 2 . Second, a switching transistor Q 9  applies a bias potential V rst  to force the CTIA output voltage to a desired initial condition regardless of Q L1  transconductance, channel conductance and threshold voltage variations. Third, the CTIA 14 is designed such that the V Ibias  voltage provides for a specified low power consumption of the CTIA 14. Finally, the operation of load transistor Q L1  is substantially process independent. That is, Q L1  is required only to exhibit a relatively low channel conductance because it functions as a source follower. An amount of current flowing through Q L2  is a function of the resistance of the implant resistor R 4  connected between the gate terminal and the source terminal of Q L2  and also of the threshold voltage of Q L2 . Any variation of this threshold voltage, however, is compensated for by the resistor R 4 . 
     The voltage at the gate of Q L2  varies according to the amount of the photon-induced signal at the CTIA output due to the fact that Q 4  functions as a source follower and the gate of Q 4  is connected to the node that includes the drain of Q L1 . As a result of this voltage variation the source voltage of Q L2  varies significantly, but the drain-to-source voltage of Q L2  remains substantially constant. If such a drain-to-source voltage variation were to occur the value of both the transconductance and the channel conductance of Q L2  would vary, resulting in a nonuniformity in load resistivity. In order to maintain the Q L2  drain-to-source voltage at a substantially constant level transistor Q L3  is included as a part of the load circuit The gate of Q L3  is connected in common with the gate of Q L2  to one side of resistor R 4  such that the gate terminal senses the CTIA output voltage variation. Q L3  functions as a source follower coupled to the drain of Q L2  such that the voltage between the drain and the source of Q L2  is forced to maintain a substantially constant voltage level. Both the transconductance and channel conductance of Q L3  are not expected to be constant, but the effect of their variation does not have significant effect since the load represented by Q L3  as a source follower is a relatively high resistance. C BY  functions as a high frequency bypass capacitor for the differential pair output node. 
     Switching transistors Q 0  and Q 9 , through Q 4 , turn on to discharge the feedback capacitor, C f , at the beginning of each integration period. Transistor Q 0  provides a specified bias voltage across the infrared detector at each integration period. The switching of Q 9  is controlled by command clock φ1B coupled to the gate thereof, the drain of Q 9  being biased by V rst . The voltage level of V rst  is determined by the polarity of the associated IR detector 12. That is, the signal input to Q 1  can be either positive or negative depending on the polarity of V det  and whether detector 12 is a p-on-n device or an n-on-p type of device. Transistor Q 0  acts as a switch, similar to Q 9 , and is turned on periodically by clock φ1A according to the required integration period When both Q 9  and Q 0  are turned on, the feedback capacitance C f  is discharged to an initial condition through Q 0  to ground and through the source follower Q 4   to V rst  through Q 9 . Simultaneously with the discharging of C f , Q 0  forces the gate of Q 1  to a desired voltage potential, such as ground, to establish a specified potential across the IR detector 12. 
     The IR detector induced signal is amplified by differential pair Q 1  and Q 2  in conjunction with Q L1 , Q L2  and Q L3  after which the amplified signal is provided to buffer transistor Q 4 , which is operated in a source follower configuration. Buffer transistor Q 4  has coupled to the source terminal thereof the aforementioned feedback capacitor C f . In general, buffer transistor Q 4  provides a low-impedance source to the feedback path through C f  and also to the S/H circuit including Q 8  and signal storage capacitor C smp . 
     Transistor Q 7  functions as a load for the transistor Q 4  in conjunction with a resistor R 5 , the resistor R 5  serving to control current flow through Q 7  and hence specify power consumption. V bias  is coupled to the gate of Q 7  for controlling the conduction thereof. 
     The aforementioned S/H circuit is comprised of a GaAs MESFET switching transistor Q 8  and the signal storage capacitor C smp . The source-to-drain threshold voltage of Q 8  is sufficiently high to prevent the gate from becoming forward biased. 
     Transistor Q 10  functions as an amplifier and delivers a sampled analog signal (OUTPUT) to a chip driver (not shown). Q 10  forms part of the MUX circuit that includes a source resistor R1 and a load resistor R2. R1 and R2 typically have the same resistance value in order to achieve a unity gain feedback amplifier at the MUX output. The particular values of these resistors depends upon the desired multiplexing rate and power consumption. Q 10  senses the stored charge across the sampling capacitor C smp . Q 10  is activated by the φ3 clock which is applied to the gate of Q 11 . When φ3 is applied, Q 11  is turned on thereby providing current through R1 to the unity gain wideband amplifier Q 10 . The signal OUTPUT has a voltage magnitude substantially equal to the voltage across C smp , or the sampled analog signal. 
     Referring now to FIG. 3 a timing diagram of a single integration period illustrates, in accordance with a method of the invention, the operation of the circuitry shown in FIG. 3. The signal appearing at the CTIA 14 output, designated E 1  in FIGS. 1 and 2, is the integrated IR induced signal. The signal is integrated over an integration period and has an integration slope that is determined by a combination of the detected IR photons, the detector characteristics and the value of the feedback capacitor, C f . The clocks φ1A and φ1B occur at substantially the same time during the integration period, the φ1B signal however, having a slightly longer pulse duration A positive going pulse, φ1A, turns on transistor Q 0  thereby effectively shorting the input of CTIA 14 to circuit ground. This has the effect of discharging the feedback capacitor C f , thereby resetting the feedback capacitor. φ1B turns on transistor Q 9 , thereby establishing the desired potential, V rst , at the circuit node that comprises the drain of Q L1 , the gates of load transist Q L2  and Q L3  and the gate of buffer transistor Q 4 . The output of the CTIA 14 is thereby reset to a desired operating voltage potential at the beginning of each integration period by selecting the V rst  voltage level. 
     The clock φ1B has a longer duration than that of φ1B such that the operating point for the CTIA 14 may be established subsequent to the resetting the CTIA output voltage Shortly after the clock signal φ1B is turned off, thereby cutting off transistor Q 9  conduction, the φ2 clock is turned on which causes the voltage across capacitance, C smp , to be the same as that of the CTIA buffer output. The φ2 clock is applied at the beginning of the integration period. The clock φ3 is applied to read the initial value of the CTIA output signal which is stored by the S/H circuit at the beginning of the integration period. The S/H circuit samples the CTIA output and stores the charge across C smp . The φ2 clock is again applied to the gate of Q 8  to sample the final value of the CTIA output before the end of the integration period. Clock φ3 is once more applied to sense the voltage across C smp . Thus, the MUX circuit output provides two sampled analog pulses per integration period, the magnitude of the pulses corresponding to the beginning and end values of the CTIA output. Determining the difference between the two pulses provides for reducing the effect of amplifier noise originating in Q 1  and Q 2  (1/f noise) and also switching transient noise (kTC noise). Devices Q 1 , Q 2 , Q L1 , Q L2 , and Q L3  are designed to achieve a high open loop amplifier gain. The high gain amplifier in conjunction with feedback capacitor C f  causes the capacitive feedback to dominate, thereby minimizing the effect of any intrinsic capacitance associated with the IR detector 12 and/or any parasitic capacitance associated with the coupling between the detector 12 and the CTIA 14 input. It can be seen that the magnitude of the CTIA output voltage depends only upon the capacitance of the feedback capacitor Cf and the IR detector 12 induced current. As a result, the uniformity of the readout output voltage of the array is excellent. 
     It should be realized that the FPA readout of the invention, that is an FPA readout using GaAs semiconductor material, has a number of advantages over a FPA readout comprised of Si. As has been stated, the FPA signal processor of the invention has a similar thermal expansion coefficient as that of an associated HgCdTe, InSb, or GaAs based MQW SL IR detector array. Thus, thermal cycling between room and cryogenic temperatures does not induce mechanical stresses. Furthermore, the higher electron mobility of GaAs results in transistors having a transconductance value equivalent to that of silicon transistors but with a substantial reduction in operating power. 
     The novel load circuitry disclosed herein provides for advantageously rendering the differential amplifier pair substantially immune to process-related and other variations in circuit parameters. The circuitry also sets the operating point of the CTIA amplifier to a desired condition at the beginning of each integration period while also providing for the biasing of the associated IR detector at an optimum operating point. 
     The invention can be constructed as shown with GaAs MESFETs or with other types of GaAs transistors such as High Electron Mobility Transistors (HEMTs), Selectively Doped Heterostructure Transistors (SDHTs), Modulation Doped Field Effect Transistors (MODFETs), single quantum or double quantum well transistors, or superlattice MESFETs. 
     Thus, while the invention has been particularly shown and described with respect to a presently preferred embodiment thereof, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope and spirit of the invention.