Patent Publication Number: US-8527858-B2

Title: Systems and methods for selective decode algorithm modification

Description:
BACKGROUND OF THE INVENTION 
     The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data decoding. 
     Various storage systems include data processing circuitry implemented with a data decoding circuit. In some cases, a belief propagation based decoder circuit is used. In such cases where high rate low density parity check codes are used, an error floor is more severe because short cycles are unavoidable. Such short cycles make the messages in the belief propagation decoder correlate quickly and degrade the performance. In contrast, a maximum likelihood decoder may be used as it does not exhibit the same limitations. However, such maximum likelihood decoders are typically too complex for practical implementation. 
     Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for data processing. 
     BRIEF SUMMARY OF THE INVENTION 
     The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data decoding. 
     Various embodiments of the present invention provide data processing systems. Such systems include a combination data decoder circuit. The combination data decoder circuit includes a first decoder circuit and a second decoder circuit. The first decoder circuit is operable to apply a first data decode algorithm to a decoder input to yield a decoded output. The second decoder circuit is operable to apply a second data decode algorithm to a subset of the decoded output to modify at least one element of the decoded output to yield a modified decoded output. In some cases, the data processing system further includes a data detector circuit that is operable to apply a data detection algorithm to a data set to yield a detected output. In such cases, the decoder input is derived from the detected output. The data detection algorithm may be, but is not limited to, a maximum a posteriori data detection algorithm or a Viterbi detection algorithm. In some cases, the data processing system is implemented as part of a storage device or a receiving device. In one or more cases, the data processing system is implemented as part of an integrated circuit. 
     In some instances of the aforementioned embodiments, the decoded output is a first decoded output. In such instances, the first decoder output is operable to apply the first data decode algorithm to the decoder input guided by the modified decoded output to yield a second decoded output. In various instances of the aforementioned embodiments, the first data decode algorithm is a belief propagation data decode algorithm, and the second data decode algorithm is a maximum likelihood data decode algorithm. 
     In various instances of the aforementioned embodiments, the combination data decoder circuit further includes a controller circuit operable to selectively control generation of the modified decoded output. In some such instances, the controller circuit enables generation of the modified decoded output when: a number of iterations of the first decoder circuit applying the first data decode algorithm to a decoder input is greater than a first threshold value; a number of unsatisfied checks corresponding to the decoded output is less than a second threshold value; and the unsatisfied checks corresponding to the decoded output is the same as the unsatisfied checks corresponding to a previous decoded output. In one particular case, the first threshold value is three, and the second threshold value is ten. 
     Other embodiments of the present invention provide methods for data processing. The methods include: applying a first data decode algorithm to a decoder input to yield a first decoded output; applying a second data decode algorithm to a subset of the first decoded output to modify at least one element of the decoded output to yield a modified decoded output; and applying the first data decode algorithm to the decoder input guided by the modified decoded output to yield a second decoded output. In some cases, the methods further include applying a data detection algorithm to a data set to yield a detected output, wherein the decoder input is derived from the detected output. In particular cases, the methods further include: receiving an analog input; converting the analog input to a series of digital samples; and equalizing the series of digital samples to yield the data set. The data detection algorithm may be, but is not limited to, a maximum a posteriori data detection algorithm or a Viterbi detection algorithm. In some cases, the first data decode algorithm is a belief propagation data decode algorithm, and the second data decode algorithm is a maximum likelihood data decode algorithm. In some instances of the aforementioned embodiments, the methods further include determining that there are at least one failed checksum associated with the first decoded output. In such instances, the subset of the first decoded output includes elements of the first decoded output that correspond to the at least one failed checksum. In some cases, the methods further include determining that the same at least one failed checksum occurs for at least two consecutive applications of the first data decode algorithm to the decoder input. 
     This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals are used throughout several figures to refer to similar components. In some instances, a sub-label consisting of a lower case letter is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components. 
         FIG. 1   a  shows a data processing circuit including a combination data decoder circuit including a combination of a low complexity decoder circuit and a partial maximum likelihood decoder circuit in accordance with one or more embodiments of the present invention; 
         FIG. 1   b  depicts a controller circuit that may be used in relation to the combination decoder circuit of  FIG. 1  in accordance with various embodiments of the present invention; 
         FIG. 2  is a flow diagram showing method for selectively combined data decoding in accordance with various embodiments of the present invention; 
         FIG. 3  shows a storage device including combination data decoder circuitry in accordance with one or more embodiments of the present invention; and 
         FIG. 4  shows a data transmission system including combination data decoder circuitry in accordance with various embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data decoding. 
     Various embodiments of the present invention provide data processing systems that include a data decoder circuit that includes a low complexity decoder circuit and a partial maximum likelihood parity check decoder circuit that is selectively used to modify an output of the low complexity decoder circuit when a possible trapping set is detected. As just one of many advantages, the aforementioned approach allows for using data decoder circuits that exhibit relatively low complexity such as, for example, a belief propagation decoder circuit, while using another decoder algorithm to correct errors that are not correctable by the low complexity decoder algorithm. As the errors to be corrected are localized by the belief propagation decoder circuit, the complexity of the combination of the partial maximum likelihood parity check decoder circuit and the belief propagation decoder circuit is substantially less than that of a maximum likelihood decoder circuit. 
     Turning to  FIG. 1   a , a data processing circuit  100  is shown that includes a combination data decoder circuit  170  including a combination of a low complexity decoder circuit  166  and a partial maximum likelihood decoder circuit  168  in accordance with one or more embodiments of the present invention. Data processing circuit  100  includes an analog front end circuit  110  that receives an analog signal  105 . Analog front end circuit  110  processes analog signal  105  and provides a processed analog signal  112  to an analog to digital converter circuit  114 . Analog front end circuit  110  may include, but is not limited to, an analog filter and an amplifier circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that may be included as part of analog front end circuit  110 . In some cases, analog signal  105  is derived from a read/write head assembly (not shown) that is disposed in relation to a storage medium (not shown). In other cases, analog signal  105  is derived from a receiver circuit (not shown) that is operable to receive a signal from a transmission medium (not shown). The transmission medium may be wired or wireless. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of source from which analog input  105  may be derived. 
     Analog to digital converter circuit  114  converts processed analog signal  112  into a corresponding series of digital samples  116 . Analog to digital converter circuit  114  may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. Digital samples  116  are provided to an equalizer circuit  120 . Equalizer circuit  120  applies an equalization algorithm to digital samples  116  to yield an equalized output  125 . In some embodiments of the present invention, equalizer circuit  120  is a digital finite impulse response filter circuit as are known in the art. In some cases, equalizer  120  includes sufficient memory to maintain one or more codewords until a data detector circuit  130  is available for processing, and for multiple processes through data detector circuit  130 . 
     Data detector circuit  130  is operable to apply a data detection algorithm to a received codeword or data set, and in some cases data detector circuit  130  can process two or more codewords in parallel. In some embodiments of the present invention, data detector circuit  130  is a Viterbi algorithm data detector circuit as are known in the art. In other embodiments of the present invention, data detector circuit  130  is a maximum a posteriori data detector circuit as are known in the art. Of note, the general phrases “Viterbi data detection algorithm” or “Viterbi algorithm data detector circuit” are used in their broadest sense to mean any Viterbi detection algorithm or Viterbi algorithm detector circuit or variations thereof including, but not limited to, bi-direction Viterbi detection algorithm or bi-direction Viterbi algorithm detector circuit. Also, the general phrases “maximum a posteriori data detection algorithm” or “maximum a posteriori data detector circuit” are used in their broadest sense to mean any maximum a posteriori detection algorithm or detector circuit or variations thereof including, but not limited to, simplified maximum a posteriori data detection algorithm and a max-log maximum a posteriori data detection algorithm, or corresponding detector circuits. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detector circuits that may be used in relation to different embodiments of the present invention. Data detector circuit  130  is started based upon availability of a data set from equalizer circuit  120  or from a central memory circuit  150 . 
     Upon completion, data detector circuit  130  provides a detector output  196 . Detector output  196  includes soft data. As used herein, the phrase “soft data” is used in its broadest sense to mean reliability data with each instance of the reliability data indicating a likelihood that a corresponding bit position or group of bit positions has been correctly detected. In some embodiments of the present invention, the soft data or reliability data is log likelihood ratio data as is known in the art. Detected output  196  is provided to a local interleaver circuit  142 . Local interleaver circuit  142  is operable to shuffle sub-portions (i.e., local chunks) of the data set included as detected output and provides an interleaved codeword  146  that is stored to central memory circuit  150 . Interleaver circuit  142  may be any circuit known in the art that is capable of shuffling data sets to yield a re-arranged data set. Interleaved codeword  146  is stored to central memory circuit  150 . Interleaved codeword  146  is comprised of a number of encoded sub-codewords designed to reduce the complexity of a downstream data decoder circuit while maintaining reasonable processing ability. 
     Once a data decoding circuit  170  is available, a previously stored interleaved codeword  146  is accessed from central memory circuit  150  as a stored codeword  186  and globally interleaved by a global interleaver/de-interleaver circuit  184 . Global interleaver/De-interleaver circuit  184  may be any circuit known in the art that is capable of globally rearranging codewords. Global interleaver/De-interleaver circuit  184  provides a decoder input  152  input to low data decoder circuit  170 . 
     Data decoder circuit  170  includes low complexity decoder circuit  166 , partial maximum likelihood decoder circuit  168 , and a controller circuit  175 . Low complexity decoder circuit  166  may be any decoder circuit known in the art that is less complex to implement than a maximum likelihood decoder circuit. In some embodiments of the present invention, low complexity decoder circuit  166  is a belief propagation data decoder circuit as are known in the art. Such a belief propagation data decoder circuit may be implemented similar to that discussed in Pearl, Judea, “REVEREND BAYES ON INFERENCE ENGINES: A DISTRIBUTED HIERARCHAL APPROACH”, AAAI-82 Proceedings, 1982. The entirety of the aforementioned reference is incorporated herein by reference for all purposes Low complexity decoder circuit  166  receives decoder input  152  and applies a decoder algorithm thereto to yield a decoder output  167 . In addition, checksum indices  169  (i.e., an identification of a particular parity check equation) of any unsatisfied parity checks are generated. Decoder output  167  and checksum indices  169  are provided to controller circuit  175 . In addition, decoder output  167  is fed back to low complexity decoder circuit  166  where it can be used to guide subsequent application of the decoder algorithm to decoder input  152 . 
     Controller circuit  175  utilizes decoder output  167  and checksum indices  169  to determine if a potential trapping set condition has occurred. Where a potential trapping set condition has occurred, an LLR subset output  177  (a portion of decoder output  167 ) and corresponding index outputs  176  (i.e., a portion of checksum indices  169  corresponding to LLR subset output  177 ) are provided by controller circuit  175  to partial maximum likelihood decoder circuit  168 . Partial maximum likelihood decoder circuit  168  applies a maximum likelihood decoder algorithm to LLR subset output  177  in an effort to correct any remaining unsatisfied checks. This involves building a trellis for a local portion of the decoded output and to perform trellis based maximum likelihood decoding on the local portion of the decoded output. The following equations describe the operation of partial maximum likelihood decoder circuit  168  to generate a given soft output, L(b i ): 
                 L   ⁡     (     b   i     )       =     ln   [         ∑   b     ∈       b   i   0     ⁢     p   ⁡     (   b   )       ⁢     p   ⁡     (     L   |   b     )               ∑   b     ∈       b   i   1     ⁢     p   ⁡     (   b   )       ⁢     p   ⁡     (     L   |   b     )             ]       ,         
where b represents a bit of decoded output  167 , p(b) represents the a priori probability that the entire vector of the correct hard decision b is correct, and p(L|b) is the conditional probability given vector b that b i  is a logic ‘1’ (indicated by b i   1 ) or a logic ‘0’ (indicated by b i   0 ). The aforementioned equation may be simplified as follows:
 
                 L   ⁡     (     b   i     )       =     ln   [       ∑     max     b   ∈       b   i   0     ⁢     p   ⁡     (   b   )       ⁢     p   ⁡     (     L   |   b     )                 ∑     max     b   ∈       b   i   1     ⁢     p   ⁡     (   b   )       ⁢     p   ⁡     (     L   |   b     )                 ]       ;                   L   ⁡     (     b   i     )       =     ln   [       ∑     p   ⁡     (     L   |       b   ^     0       )           ∑     p   ⁡     (     L   |       b   ^     1       )           ]       ;   and                   L   ⁡     (     b   i     )       =       ∑     j   =   0       N   -   1       ⁢     [            l   i          ⁢     (         (     -   1     )         sign   ⁡     (     1   -     2   ⁢       b   ^     0         )       ⁢     sign   ⁡     (     l   i     )           -       (     -   1     )         sign   ⁡     (     1   -     2   ⁢       b   ^     1         )       ⁢     sign   ⁡     (     l   i     )             )       ]         ,         
where l i  is the soft data (i.e., LLR data) associated with b i . Accordingly, the probability for a given hard decision value b i  may be approximated by the following equation:
 
     
       
         
           
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     As LLR subset output  177  is localized, the complexity of partial maximum likelihood decoder circuit  168  is substantially less than the complexity of implementing a corresponding maximum likelihood decoder circuit capable of handing an entire codeword. Where a remaining unsatisfied check is corrected by partial maximum likelihood decoder circuit  168 , the corresponding elements of LLR subset output  177  are modified to corrected values  179  that are fed back to low complexity decoder circuit  166  where they are used in place of the corresponding element of decoder output  167  to guide subsequent application of the decoder algorithm to decoder input  152 . In some cases, partial maximum likelihood decoder circuit  168  is implemented using the maximum likelihood decoder approach disclosed in Viterbi, Andrew J., “ERROR BOUNDS FOR CONVOLUTION CODES AND AN ASYMPTITICALLY OPTIMUM DECODING ALGORITHM”, IEEE Transactions on Information Theory, Vol. IT-13, No. 2, April 1967. The entirety of the aforementioned reference is incorporated herein by reference for all purposes. Where a potential trapping set condition has not been identified and one or more additional local iterations remain, low complexity decoder circuit  166  is triggered to re-apply the decoder algorithm to decoder input  152  guided by decoder output  167 . 
     In one particular embodiment of the present invention, a potential trapping set condition is considered to have occurred where the number of remaining unsatisfied checks after application of the decoder algorithm to decoder input  152  is less than ten, and the indexes corresponding to the remaining unsatisfied checks have not changed for at least two local iterations (i.e., passes through low complexity decoder circuit  166 ). In addition, in some cases, controller circuit  175  is not enabled to indicate a potential trapping set condition until at least four local iterations of decoder algorithm to decoder input  152  have completed. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other indicia that may be used to define the occurrence of a potential trapping set condition and/or to trigger operation of partial maximum likelihood decoder circuit  168 . 
     In addition, controller circuit  175  determines whether the data decoding algorithm converged. Where the data decoding algorithm failed to converge and no more local iterations (iterations through low complexity decoder circuit  166 ), controller circuit  175  provides a decoder output  154  (i.e., decoder output  167 ) back to central memory circuit  150  via global interleaver/de-interleaver circuit  184 . Prior to storage of decoded output  154  to central memory circuit  150 , decoded output  154  is globally de-interleaved to yield a globally de-interleaved output  188  that is stored to central memory circuit  150 . The global de-interleaving reverses the global interleaving earlier applied to stored codeword  186  to yield decoder input  152 . Once data detector circuit  130  is available, a previously stored de-interleaved output  188  is accessed from central memory circuit  150  and locally de-interleaved by a de-interleaver circuit  144 . De-interleaver circuit  144  re-arranges decoder output  148  to reverse the shuffling originally performed by interleaver circuit  142 . A resulting de-interleaved output  197  is provided to data detector circuit  130  where it is used to guide subsequent detection of a corresponding data set receive as equalized output  125 . 
     Alternatively, where the data decoding algorithm converged, controller circuit  175  provides an output codeword  172  to a de-interleaver circuit  180 . De-interleaver circuit  180  rearranges the data to reverse both the global and local interleaving applied to the data to yield a de-interleaved output  182 . De-interleaved output  182  is provided to a hard decision output circuit  190 . Hard decision output circuit  190  is operable to re-order data sets that may complete out of order back into their original order. The originally ordered data sets are then provided as a hard decision output  192 . 
     An example of operation of controller circuit  175  is provided in the following pseudo-code: 
     
       
         
           
               
             
               
                   
               
             
            
               
                 If (number of unsatisfied checks == 0) 
               
               
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                  provide decoder output 167 as output codeword 172 
               
               
                 } 
               
               
                 Else if (number of unsatisfied checks &gt; 0 &amp;&amp; number of local 
               
               
                 iterations == maximum) 
               
               
                 { 
               
               
                  provide decoder output 167 as decoded output 154 
               
               
                 } 
               
               
                 Else if (number of unsatisfied checks &gt; 0 &amp;&amp; 
               
               
                   [number of unsatisfied checks &gt;= M OR 
               
               
                     number of local iterations is &lt; N OR 
               
               
                     indexes 169 change from one local iteration to the next]) 
               
               
                 { 
               
               
                  provide decoder output 167 as an input to low complexity decoder 
               
               
                  circuit 166 
               
               
                 } 
               
               
                 Else if (number of unsatisfied checks &gt; 0 &amp;&amp; 
               
               
                   [number of unsatisfied checks &lt; M AND 
               
               
                     number of local iterations is &gt;= N OR 
               
               
                     indexes 169 do not change from one local iteration to the next]) 
               
               
                 { 
               
               
                  provide LLR subset output 177 to partial maximum likelihood decoder 
               
               
                  circuit 168 
               
               
                 } 
               
               
                   
               
            
           
         
       
     
     Turning to  FIG. 1   b , a controller circuit  101  that may be used in place of controller circuit  175  of  FIG. 1  in accordance with various embodiments of the present invention. Controller circuit  101  includes an LLR subset register  102  that stores each element of decoder output  167  that corresponds to a non-zero value of a checksum identified as one of checksum indices  169 . An LLR subset register output  103  is provided by LLR subset register  102 . In addition, controller circuit  101  includes an unsatisfied check index register  106  that stores each index for which one or more instances of decoder output  167  stored to LLR subset register  102 . Controller circuit  101  also includes a codeword completion circuit  113  that counts decoder outputs  167  to determine whether all instances of a codeword have been received. Where a completed codeword is received, a codeword complete output  117  is asserted high. 
     An unsatisfied check counter circuit  127  counts the number of non-zero unsatisfied checks indicated by checksum indices to yield an unsatisfied check count value  128 . Unsatisfied check counter circuit  127  is reset whenever codeword complete output  117  is asserted such that a completed codeword is indicated. Hence, unsatisfied check count value  128  indicates the number of unsatisfied checks that occur for a given codeword. A count output equals zero circuit  131  indicates whether unsatisfied check count value  128  is equal to zero. Where unsatisfied check count value  128  is determined to be equal to zero, count output equals zero circuit  131  asserts a zero count output  133 . Where zero count output  133  is asserted indicating that unsatisfied check count value  128  is zero, an output codeword generator circuit  134  provides decoder output  167  as output codeword  172 . 
     In addition, a count output less than M circuit  129  determines whether unsatisfied check count value  128  is greater than zero and less than a value M. In some cases, M is ten. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of M that may be used in relation to different embodiments of the present invention. Where count output less than M circuit  129  determines that the value of unsatisfied check count value  128  is greater than zero and less than M, count output less than M circuit  129  asserts an M count output  132 . 
     A local iteration counter circuit  118  receives codeword complete output  117  and counts the number of local iterations that have been applied to the particular codeword (received as decoder output  167 ). The number of local iterations is provided as a local iteration count value  119 . A count output greater than N circuit receives local iteration count value  119  and asserts a count value greater than N output  126  whenever local iteration count value  119  is greater than N. In some cases, N is three. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of N that may be used in relation to different embodiments of the present invention. A count output equals maximum local iterations circuit  121  receives local iteration count value  119  and asserts a count value equals maximum local iterations output  122  whenever local iteration count value  119  equals the defined maximum number of local iterations. is greater than N. In some cases, N is three. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of N that may be used in relation to different embodiments of the present invention. Where M count output  132  indicates that the number of unsatisfied checks is not zero and count value equals maximum local iterations output  122  indicates the maximum number of local iterations have been performed, a decoded output generator circuit  123  provides a derivative of decoder output  167  as decoded output  154 . 
     An index buffer  108  receives index values  107  from unsatisfied check index register  106  and stores them upon completion of a codeword (e.g., codeword complete output  117  is asserted). Index values  109  from index buffer  108  are compared with index values  107  by a same indexes circuit  111  to determine whether there has been a change over the last two local iterations to determine if the same parity check equations remain unsatisfied. Where the same parity check equations remain unsatisfied, same indexes circuit  111  asserts an unchanged output  112 . In addition, index values  107  are provided as an index output  176 . LLR subset output generator circuit  104  provides LLR subset register output  103  as LLR subset output  177  whenever same indexes output  112  is asserted, count value greater than N output  126  is asserted, and M count output  132  are all asserted. 
     Turning to  FIG. 2 , a flow diagram  200  shows a method for selectively combined data decoding in accordance with various embodiments of the present invention. Following flow diagram  200 , an analog input is received (block  205 ). The analog input may be derived from, for example, a storage medium or a data transmission channel. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources of the analog input. The analog input is converted to a series of digital samples (block  210 ). This conversion may be done using an analog to digital converter circuit or system as are known in the art. Of note, any circuit known in the art that is capable of converting an analog signal into a series of digital values representing the received analog signal may be used. The resulting digital samples are equalized to yield an equalized output (block  215 ). In some embodiments of the present invention, the equalization is done using a digital finite impulse response circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of equalizer circuits that may be used in place of such a digital finite impulse response circuit to perform equalization in accordance with different embodiments of the present invention. 
     It is determined whether a data detector circuit is available (block  220 ). Where a data detector circuit is available (block  220 ), a data detection algorithm is applied to the equalized output guided by a data set derived from a decoded output where available (e.g., the second and later iterations through the data detector circuit and the data decoder circuit) from a central memory circuit to yield a detected output (block  225 ). In some embodiments of the present invention, data detection algorithm is a Viterbi algorithm as are known in the art. In other embodiments of the present invention, the data detection algorithm is a maximum a posteriori data detector circuit as are known in the art. The data set derived from the decoded output maybe a de-interleaved version of the decoded data set. A signal derived from the detected output (e.g., a locally interleaved version of the detected output) is stored to the central memory to await processing by a data decoder circuit (block  230 ). 
     In parallel to the previously discussed data detection processing, it is determined whether a data decoder circuit is available (block  240 ). Where the data decoder circuit is available (block  240 ), a previously stored derivative of a detected output is accessed from the central memory (block  245 ). A low complexity data decode algorithm is applied to the derivative of the detected output to yield a decoded output (block  250 ). The low complexity decode algorithm maybe be any data decode algorithm known in the art that is less complex to implement than a maximum likelihood decoder algorithm. In some embodiments of the present invention, the low complexity data decode algorithm is a belief propagation data decode algorithm as are known in the art. Such a belief propagation data decode algorithm may be implemented similar to that discussed in Pearl, Judea, “REVEREND BAYES ON INFERENCE ENGINES: A DISTRIBUTED HIERARCHAL APPROACH”, AAAI-82 Proceedings, 1982. 
     It is determined whether the decoded output converged (i.e., the original data set is recovered) (block  255 ). In some cases, such convergence is found where all of the checksum equations utilized as part of the low complexity decode algorithm are correct. Where the decode algorithm converged (block  255 ), the decoded output is provided as a hard decision output (block  260 ). Otherwise, where the decode algorithm failed to converge (block  255 ), it is determined whether the number of local iterations of the data decode algorithm on the current data set is exceeded a threshold value N (block  265 ). In some cases, N is four. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of N that may be used in relation to different embodiments of the present invention. Where the number of local iterations has not exceeded the threshold value N (block  265 ), the processes of blocks  250 - 265  are repeated for the same data set using the previous decoded output as a guide. 
     Otherwise, where the number of local iterations has exceeded the threshold value N (block  265 ), it is determined whether another local iteration is to be performed (block  270 ). In some cases, this is determined by comparing the number of local iterations that have been completed to a defined threshold number. Where another local iteration is not called for (e.g., the number of local iterations equals a maximum number of local iterations) (block  270 ), the decoded output is stored to the central memory circuit where it awaits processing by the data detector circuit (i.e., another global iteration) (block  275 ). Otherwise, where it is determined that another local iteration is called for (e.g., the number of local iterations is not equal to a maximum number of local iterations) (block  270 ), it is determined whether the number of remaining unsatisfied checks is less than a threshold value M (block  280 ). In some cases, M is ten. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of M that may be used in relation to different embodiments of the present invention. Where the number of unsatisfied checks is not less than the threshold value M (block  280 ), the processes of blocks  250 - 280  are repeated for the same data set using the previous decoded output as a guide. 
     Otherwise, where the number of unsatisfied checks is less than the threshold value M (block  280 ), a partial maximum likelihood data decode algorithm is applied to a subset of the decoded output corresponding to the remaining unsatisfied checks to yield a partial maximum likelihood soft data output (block  285 ). As the partial maximum likelihood data decode algorithm is only applied to a subset of the decoded output localized to the remaining unsatisfied checks, the complexity of the complexity of the partial maximum likelihood data decode algorithm is substantially less than the complexity of a corresponding maximum likelihood decoder circuit capable of handing an entire codeword. In some cases, the partial maximum likelihood data decode algorithm is implemented using the maximum likelihood decoder approach disclosed in Viterbi, Andrew J., “ERROR BOUNDS FOR CONVOLUTION CODES AND AN ASYMPTITICALLY OPTIMUM DECODING ALGORITHM”, IEEE Transactions on Information Theory, Vol. IT-13, No. 2, April 1967. The soft data of the decoded output is forced to be equal to the corresponding partial maximum likelihood soft data to yield a modified decoded output (block  290 ), and the processes of blocks  250 - 290  are repeated for the same data set using the modified decoded output as a guide. 
     Turning to  FIG. 3 , a storage device  300  including combination data decoder circuitry in accordance with one or more embodiments of the present invention. Storage device  300  may be, for example, a hard disk drive. Storage device  300  also includes a preamplifier  370 , an interface controller  320 , a hard disk controller  366 , a motor controller  368 , a spindle motor  372 , a disk platter  378 , and a read/write head assembly  376 . Interface controller  320  controls addressing and timing of data to/from disk platter  378 . The data on disk platter  378  consists of groups of magnetic signals that may be detected by read/write head assembly  376  when the assembly is properly positioned over disk platter  378 . In one embodiment, disk platter  378  includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme. 
     In a typical read operation, read/write head assembly  376  is accurately positioned by motor controller  368  over a desired data track on disk platter  378 . Motor controller  368  both positions read/write head assembly  376  in relation to disk platter  378  and drives spindle motor  372  by moving read/write head assembly to the proper data track on disk platter  378  under the direction of hard disk controller  366 . Spindle motor  372  spins disk platter  378  at a determined spin rate (RPMs). Once read/write head assembly  378  is positioned adjacent the proper data track, magnetic signals representing data on disk platter  378  are sensed by read/write head assembly  376  as disk platter  378  is rotated by spindle motor  372 . The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter  378 . This minute analog signal is transferred from read/write head assembly  376  to read channel circuit  310  via preamplifier  370 . Preamplifier  370  is operable to amplify the minute analog signals accessed from disk platter  378 . In turn, read channel circuit  310  decodes and digitizes the received analog signal to recreate the information originally written to disk platter  378 . This data is provided as read data  303  to a receiving circuit. A write operation is substantially the opposite of the preceding read operation with write data  301  being provided to read channel circuit  310 . This data is then encoded and written to disk platter  378 . 
     During operation, data decoding applied to the information received from disk platter  378  may not converge. Where it is determined that there is a possible trapping set or other impediment to convergence, a second data decoder and/or decoding algorithm may be applied to a localized portion of the information to correct one or more errors associated with the possible trapping set or other impediment to convergence. Such multi-level decoding may be performed using a data decoder circuit similar to that discussed above in relation to  FIGS. 1   a - 1   b , and/or may be done using a process similar to that discussed above in relation to  FIG. 2 . 
     It should be noted that storage system may utilize SATA, SAS or other storage technologies known in the art. Also, it should be noted that storage system  300  may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. It should also be noted that various functions or blocks of storage system  400  may be implemented in either software or firmware, while other functions or blocks are implemented in hardware. 
     Turning to  FIG. 4 , a data transmission system  400  including combination data decoder circuitry in accordance with various embodiments of the present invention. Data transmission system  400  includes a transmitter  410  that is operable to transmit encoded information via a transfer medium  430  as is known in the art. The encoded data is received from transfer medium  430  by receiver  420 . Transceiver  420  incorporates combination data decoder circuitry. While processing received data, received data is converted from an analog signal to a series of corresponding digital samples, and the digital samples are equalized to yield an equalized output. The equalized output is then provided to a data processing circuit including both a data detector circuit and a data decoder circuit. Data is passed between the data decoder and data detector circuit via a central memory allowing for variation between the number of processing iterations that are applied to different data sets. It should be noted that transfer medium  430  may be any transfer medium known in the art including, but not limited to, a wireless medium, an optical medium, or a wired medium. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of transfer mediums that may be used in relation to different embodiments of the present invention. 
     During operation, data decoding applied to the information received via transfer medium  430  may not converge. Where it is determined that there is a possible trapping set or other impediment to convergence, a second data decoder and/or decoding algorithm may be applied to a localized portion of the information to correct one or more errors associated with the possible trapping set or other impediment to convergence. Such multi-level decoding may be performed using a data decoder circuit similar to that discussed above in relation to  FIGS. 1   a - 1   b , and/or may be done using a process similar to that discussed above in relation to  FIG. 2 . 
     It should be noted that the various blocks discussed in the above application may be implemented in integrated circuits along with other functionality. Such integrated circuits may include all of the functions of a given block, system or circuit, or only a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware. 
     In conclusion, the invention provides novel systems, devices, methods and arrangements for data processing. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.