Patent Publication Number: US-2022216803-A1

Title: Cascaded pulse width modulation converter control

Description:
FIELD OF THE INVENTION 
     The invention relates to a method for operating an electrical converter as well as to an electrical converter. 
     BACKGROUND OF THE INVENTION 
     In medium voltage applications, power converters traditionally operate at rather low switching frequencies in the range of a few hundred Hertz due to the high switching losses of Si-based medium voltage switches such as IGBTs and IGCTs. Recently, the introduction of SiC-based switches with high blocking voltages and possibly fast switching speeds has led to the expectation that these switches may be employed in the near future also in medium voltage converters. 
     In low voltage applications, there have been significant improvements of SiC MOSFETs with a blocking voltage of up to 1.7 kV. Due to the low commutation loop inductance of 2-level half-bridge modules, very high switching speeds may be feasible and switching frequencies around 24 kHz may become common. However, SiC modules are still more expensive than comparable Si IGBT modules. 
     U.S. Pat. No. 2,014,016 380 A1 describes a multi-level voltage converter, which includes a multi-point converter circuit and at least one full bridge inverter circuit. The multi-point converter circuit is configured for converting a DC voltage into an intermediate multi-level voltage. The full bridge inverter circuit is electrically connected in series with the multi-point converter circuit and configured for receiving the intermediate multi-level voltage to generate a multi-level output voltage corresponding to a single phase output. 
     WO 2018/172329 A1 refers to an inverter comprising a first inverter stage having a first switching frequency and a second inverter stage connected to the first inverter stage and having a second switching frequency higher than the first switching frequency. A switching signal for the second inverter stage is generated by calculating a voltage error by subtracting an estimated output voltage of the first inverter stage from a reference voltage for the inverter and pulse width modulating the voltage error with a modulation frequency, which is higher than a modulation frequency for generating a switching signal for the first inverter stage. 
     WO 2018/029303 A1 relates to a method for controlling a two-level converter system. The method comprises determining, with a first controller stage, an output voltage reference for the converter system, generating, with the first controller stage, switching commands for a main converter based on the output voltage reference, and generating, with a second controller stage, switching commands for a floating converter cell connected to the output of the main converter. 
     DESCRIPTION OF THE INVENTION 
     It is an objective of the invention to provide an economical converter with low losses. 
     This objective is achieved by the subject-matter of the independent claims. Further exemplary embodiments are evident from the dependent claims and the following description. 
     A first aspect of the invention relates to a method for operating an electrical converter. For example, the method may be performed by a controller of the electrical converter. A further aspect of the invention relates to an electrical converter, which is adapted and/or configured for performing the method. 
     The electrical converter comprises a main converter for generating a first output voltage and a converter cell for converting the first output voltage into a second output voltage. 
     The main converter may be a two-level, three-level and/or multi-level converter, which converts a DC link voltage from a DC link, which may comprise one or more DC link capacitors, into the first output voltage. 
     It has to be noted that the electrical converter may comprise further converter cells, which are series-connected with each other and with the main converter. 
     Every such converter cell may comprise a first half-bridge and a second half-bridge, which are parallel-connected with each other via a DC link, which may comprise a DC link capacitor. The (first) converter cell may convert the first output voltage into a second output voltage. A second converter cell may convert the second output voltage into a third output voltage. A third converter cell may convert the third output voltage into a fourth output voltage, etc. 
     According to an embodiment of the invention, the method comprises: receiving a reference voltage for the electrical converter. The reference voltage may be a scalar in the case of a single-phase converter and may be a two- or three-component vector in the case of a three-phase converter. The vector may be provided in the three-phase (abc) coordinate system or in the stationary orthogonal (αβ and optional γ) coordinate system. 
     The reference voltage may be provided by an outer control loop, which, for example, controls the torque and/or speed of an electrical machine supplied by the electrical converter. 
     According to an embodiment of the invention, the method comprises: pulse width modulating the reference voltage with a first modulation frequency for generating a first switching signal for the main converter. Pulse width modulation may take place by comparing the voltage reference (or a component thereof) with one or more carrier signals with the modulation frequency. A level of the switching signal may be changed, when the reference voltage intersects the corresponding carrier signal. The first switching signal may be a multi-level switching signal having as many levels as the main converter is designed to generate. 
     According to an embodiment of the invention, the method comprises: switching the main converter with the first switching signal to generate the first output voltage. The switching signal may be transformed into switch positions of the main converter, which are applied to the switches of the main converter. 
     According to an embodiment of the invention, the method comprises: estimating the first output voltage from the first switching signal. The first output voltage may be estimated by multiplying the first switching signal with a half of the DC link voltage of the main converter. 
     According to an embodiment of the invention, the method comprises: determining a voltage error by subtracting the estimated first output voltage from the reference voltage. The voltage error, which depending on the voltage reference also may be a scalar or vector, is indicative of the difference of the desired voltage (the reference voltage) and the generated voltage (the first output voltage). The converter cell is switched in such a way to even more reduce this error. 
     According to an embodiment of the invention, the method comprises: pulse width modulating the voltage error with a second modulation frequency, which is higher than the first modulation frequency, for generating a further switching signal for the converter cell; and switching the converter cell with the further switching signal to generate the second output voltage. 
     Pulse width modulation of the voltage error (and of further voltage errors as described below) may take place as described with respect to the reference voltage. The voltage error may be compared with one or more carrier signals of the second modulation frequency and voltage levels for the further switching signal may be determined. 
     The further switching signal may be used for switching a complete converter cell. In this case, the further switching signals may have two or three levels. 
     It also may be that the further switching signal is used for solely switching a half-bridge of the converter cell. In this case, the further switching signal may have two levels. The other half-bridge of the converter cell may be switched with an additional switching signal, which may have a different frequency as the first switching signal and the further switching signal. 
     The second output voltage may be the first output voltage, optionally with the voltage of a DC link of the converter cells added or subtracted. Due to the higher switching frequency of the converter cell, the second output voltage may have a smaller second voltage error compared to the reference voltage. In such a way, there may be lower harmonics in the second output voltage. A large passive filter and/or a complicated active filter may be avoided. 
     As an example, the second modulation frequency is at least 5 times higher than the first modulation frequency. For example, the first modulation frequency may be lower than 500 Hz and/or the second modulation frequency may be higher than 2.5 kHz. 
     According to an embodiment of the invention, the reference voltage, when it refers to a three-phase electrical converter, is provided in a stationary orthogonal coordinate system (i.e. the αβ and optional γ system) and is converted into a three-phase (abc) coordinate system. The first switching signal may be generated from the reference voltage in the three-phase coordinate system and the first output voltage may be estimated in the three-phase coordinate system. 
     The estimated first output voltage may be transformed into the stationary orthogonal coordinate system and the first voltage error may be determined by subtracting the estimated first output voltage from the reference voltage in the stationary orthogonal coordinate system. In particular, when the reference voltage is provided as two-component (αβ) vector, the voltage error may be determined without generating accidentally a common mode component. 
     According to an embodiment of the invention, the reference voltage comprises a common mode reference voltage component. The common mode (i.e. γ) component may be provided by the outer control loop. A common mode component not only may be provided with the voltage reference, but also may be added to the voltage error and/or further voltage error. In such a way, additional objectives may be achieved, such as an extension of a linear modulation regime and/or an injection of a fundamental voltage component in a converter cell to balance the converter cell capacitors of different converter cells. 
     According to an embodiment of the invention, a common mode component is added to the voltage error, which may be in the stationary orthogonal coordinate system. 
     According to an embodiment of the invention, the electrical converter comprises a second converter cell for converting the second output voltage into a third output voltage. The second converter cell also may be switched based on pulse width modulation, for example with an even higher modulation frequency as the second modulation frequency. Again, this third modulation frequency may be at least 5 times higher than the second modulation frequency. 
     According to an embodiment of the invention, the method further comprises: estimating the second output voltage from the further switching signal, which is a second switching signal; determining a second voltage error by subtracting the estimated second output voltage from the first voltage error; pulse width modulating the second voltage error with a third modulation frequency, which is higher than the second modulation frequency, for generating a third switching signal for the second converter cell; and switching the second converter cell with the third switching signal to generate the third output voltage. In general, the complete second converter cell may be switched with the second switching signal and the complete third converter cell may be switched with the third switching signal. 
     According to an embodiment of the invention, the converter cell comprises a first half-bridge for receiving the first output voltage and a second half-bridge for providing the second output voltage. As a further alternative, the half-bridges of a converter cell may be switched with different switching signals, which are based on different modulation schemes. The first half-bridge may be switched with a second switching frequency and the second half-bridge may be switched with a third switching frequency higher (such as 5 times higher) than the second switching frequency. 
     According to an embodiment of the invention, the method further comprises: generating a second switching signal from the voltage error, wherein the second switching signal is 0, if the voltage error is higher than 0, and the second switching signal is 1, if the voltage error is lower than 0; and switching the first half-bridge with the second switching signal. The second switching signal may be generated with this simple pulse width modulation scheme. 
     According to an embodiment of the invention, the method further comprises: pulse width modulating the voltage error with an upper carrier signal for generating an upper third switching signal and with a lower carrier signal for generating a lower third switching signal, wherein the upper carrier signal sweeps a positive voltage range and the lower carrier signal sweeps a negative voltage range; selecting the upper third switching signal, if the voltage error is higher than 0, and selecting the lower third switching signal, if the voltage error is lower than 0; switching the second half-bridge with the selected third switching signal for generating the second output voltage. 
     In such a way, a single converter cell may be switched with two different modulation frequencies. This may have the advantage that solely the half-bridge with the higher switching frequency has to be provided with semiconductor switches having lower switching losses, such as SiC switches. 
     It has to be noted that the different switching schemes may be combined. 
     It may be that the electrical converter has a first and a second converter cell, while the complete first converter cell is switched with a second switching signal determined from the first voltage error and that the second converter cell is switched with a third and fourth switching signal determined from a second voltage error, which is the difference of the first voltage error and an estimated second output voltage. 
     A further aspect of the invention relates to a controller for an electrical converter, which is adapted and/or configured for performing the method as described in the above and in the below. Further aspects of the invention relate to a computer program, which, when being executed by a processor, performs the method as described in the above and the below, and to a computer-readable medium in which such a computer program is stored. 
     A computer-readable medium may be a floppy disk, a hard disk, an USB (Universal Serial Bus) storage device, a RAM (Random Access Memory), a ROM (Read Only Memory), an EPROM (Erasable Programmable Read Only Memory) or a FLASH memory. A computer-readable medium may also be a data communication network, e.g. the Internet, which allows downloading a program code. In general, the computer-readable medium may be a non-transitory or transitory medium. 
     For example, the controller may comprise a processor and a memory, in which such a computer program is stored and which may be executed by the processor. It has to be noted that the method at least partially may be implemented in hardware, such as in a DSP and/or FPGA. 
     It has to be understood that features of the method as described in the above and in the following may be features of the computer program, the computer-readable medium and the electrical converter as described in the above and in the following, and vice versa. 
     The electrical converter and/or the main converter may be a medium voltage converter, i.e. a converter that may be adapted for processing voltages of more than 1 kV. 
     The electrical converter furthermore may comprise a controller adapted for performing the method as described above and below, such that the main converter is switched by a first switching signal modulated with the first modulation frequency and such that the at least one converter cell is switched by the further switching signal modulated with the second modulation frequency. 
     According to an embodiment of the invention, the main converter is a two-level converter. The switching signal for a two-level converter may have two levels, such as 0 and 1. For example, the two-level converter may comprise a half-bridge connected in parallel with a DC link. 
     According to an embodiment of the invention, the main converter is a three-level converter. The switching signal for a three-level converter may have three-levels, such as −1, 0 and 1. 
     For example, the main converter may be a three-level neutral point clamped converter, which may comprise two series-connected half-bridges, which are connected in parallel to a split DC link and which midpoints are connected via a third half-bridge. The midpoint of the third half-bridge may be connected to a midpoint of the split DC link. 
     According to an embodiment of the invention, the main converter is a three-level T-type converter, which comprises a half-bridge, which is connected in parallel to a split DC link. The midpoint of the half-bridge may be connected via a bidirectional switch with a midpoint of the split DC link. 
     According to an embodiment of the invention, the electrical converter comprises a converter cell with a first half-bridge and a second half-bridge, which are interconnected via a DC link. All converter cells of the converter may be designed in this way. A half-bridge may comprise two semiconductor switches, which are series-connected. 
     According to an embodiment of the invention, the first half-bridge of the converter cell is switched with a second switching signal and the second half-bridge of the converter is switched with a third switching signal. It may be that the first half-bridge is switched with a lower switching frequency than the second half-bridge. This may be beneficial, when the switches of the second half-bridge have lower switching losses as the ones of the first half-bridge. 
     According to an embodiment of the invention, the first half-bridge comprises Si semiconductor switches, such as IGBTs and/or IGCTs and/or the second half-bridge comprises SiC semiconductor switches, such as MOSFETS. With this design, the lower switching losses of the SiC semiconductor switches may be utilized. 
     According to an embodiment of the invention, the electrical converter comprises a first converter cell and a second converter cell, each of which comprises a first half-bridge and a second half-bridge, which are interconnected via a DC link. It also is possible that the electrical converter comprises series-connected converter cells, which are switched with switching signals of different frequencies. The first converter cell may be switched with a second switching signal and the second converter cell may be switched with a third switching signal, with a higher switching frequency as the second switching signal. This may be beneficial, when the switches of the third converter cell have lower switching losses as the ones of the second half-bridge. 
     According to an embodiment of the invention, the first converter cell comprises (solely) Si semiconductor switches and the second converter cell comprises (solely) SiC semiconductor switches. 
     According to an embodiment of the invention, the main converter is a three-phase converter with three main converter phase outputs, wherein at least one converter cell is connected to every main converter output and provides a converter cell phase output. At every phase output of the main converter, one or more series-connected converter cells may be connected. The series-connected converter cells of every phase may be switched with different switching frequencies as described above and below. 
     In this case, the reference voltage, the voltage error(s), the switching signals, etc. may be vectors, which have a component in each phase. 
     According to an embodiment of the invention, the converter cell phase outputs are connected to a passive filter. A passive and/or sine filter may comprise inductors connected into the outputs and/or capacitors interconnecting the outputs, for example via a star- or delta-connection. Due to the increased switching frequency, a low cost passive filter may be used, since its components may have a lower inductivity and/or capacity. A cost reduction of the passive filter may overcompensate an increased cost of SiC semiconductor switches. 
     According to an embodiment of the invention, the converter cell phase outputs are connected with an electrical machine with three galvanically separated windings, which are connected via a further converter. With the high switching frequency, such an electrical drive may have rather low switching losses. The further converter also may be designed with SiC switches. 
     These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The subject-matter of the invention will be explained in more detail in the following text with reference to exemplary embodiments which are illustrated in the attached drawings. 
         FIG. 1  schematically shows an electrical converter according to an embodiment of the invention. 
         FIG. 2A  schematically shows a main converter for the electrical converter of  FIG. 1 . 
         FIG. 2B  schematically shows a further type of the main converter for the electrical converter of  FIG. 1 . 
         FIG. 2C  schematically shows a further type of the main converter for the electrical converter of  FIG. 1 . 
         FIG. 3A  schematically shows a converter cell for the electrical converter of  FIG. 1 . 
         FIG. 3B  schematically shows a further type of the converter cell for the electrical converter of  FIG. 1 . 
         FIG. 4  schematically shows an electrical converter according to a further embodiment of the invention. 
         FIG. 5A  schematically shows a main converter for the electrical converter of  FIG. 4 . 
         FIG. 5B  schematically shows a further type of the main converter for the electrical converter of  FIG. 4 . 
         FIG. 5C  schematically shows a further type of the main converter for the electrical converter of  FIG. 4 . 
         FIG. 6A  schematically shows a filter connectable to the electrical converter of  FIG. 4 . 
         FIG. 6B  schematically shows an electrical machine connectable to the electrical converter of  FIG. 4 . 
         FIG. 7  shows a diagram illustrating a controller and a method for controlling an electrical converter according to an embodiment of the invention. 
         FIG. 8  shows a diagram with output voltages produced by an electrical converter according to an embodiment of the invention. 
         FIG. 9  shows a diagram illustrating a controller and a method for controlling an electrical converter according to a further embodiment of the invention. 
         FIG. 10  shows a diagram illustrating a controller and a method for controlling an electrical converter according to a further embodiment of the invention. 
         FIG. 11  shows a diagram illustrating a part of  FIG. 10  in more detail. 
     
    
    
     The reference symbols used in the drawings, and their meanings, are listed in summary form in the list of reference symbols. In principle, identical parts are provided with the same reference symbols in the figures. 
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       FIG. 1  shows an electrical converter  10 , which is composed of a main converter  12  and series-connected converter cells  14   a ,  14   b ,  14   c . It may be that the converter  10  comprises solely one converter cell  14   a , two converter cells  14   a ,  14   b  and more than three converter cells. 
     The electrical converter  10  furthermore comprises a controller or modulator  16 , which generates switching signals s 1 , s 2 , s 3 , s 4 , s 5  for the main converter  12  and the respective converter cells  14   a ,  14   b ,  14   c.    
     The main converter generates, for example from a DC voltage, a first output voltage u 1  when switched by the switching signal s 1 . The first output voltage u 1  is supplied to the first converter cell  14   a , which, when switched by the switching signal s 2 , generates the second output voltage u 2 . The second output voltage u 2  is supplied to the second converter cell  14   b , which, when switched by the switching signal s 3 , generates a third output voltage u 3 . 
     As will be described below, the switching signals s 1 , s 2 , s 3 , s 4 , s 5  may be generated with pulse width modulation, wherein the modulation frequencies for the switching signals may increase. In such a way, also the frequencies of the output voltages u 1 , u 2 , u 3 , to may increase. 
       FIG. 1  shows that a converter cell  14   c  may be switched by two switching signals s 4 , s 5 , as will be described in more detail with respect to  FIG. 5C . The third output voltage u 3  may be supplied to the third converter cell  14   c , which, when switched by the switching signals s 4 , s 5 , generates a fourth output voltage u 4 . 
     It has to be noted that the converter cells  14   a  and/or  14   b  may be left out and that the main converter  12  may be directly connected to the converter cell  14   c , which is supplied by the two switching signals s 4 , s 5 . It also may be that one or more converter cells are connected to the converter cells  14   c  on the side opposite to the main converter  12 . 
       FIG. 2A  shows an example of the main converter  12 . The main converter  12  may be a two-level converter with a single DC link  18  composed of series-connected capacitors  20 . The DC link  18  is connected in parallel with a half-bridge  22 , which is composed of two series-connected semiconductor switches  24 . The output of the main converter  12  is provided by a midpoint  26  between the switches  24 . 
       FIG. 2B  shows a further example of the main converter  12 , in the form of three-level, neutral point piloted and/or T type converter. Additionally to the main converter  12  of  FIG. 2B , the main converter of  FIG. 2B  has a split DC link  18 , wherein a midpoint  28  of the DC link  18  is connected via a bidirectional switch  30  with the midpoint  26  of the half-bridge  22 . 
       FIG. 2C  shows a main converter  12  in the form of a three-level, active neutral point clamped converter. Two series-connected half-bridges  22  are connected in parallel to a split DC link and provide the output  32  of the converter between them. The midpoints  26  of the half-bridges are interconnected via a third half-bridge  22 , which midpoint  26  is directly connected to the midpoint  28  of the DC link  18 . 
       FIG. 3A  shows a converter cell  14   a ,  14   b ,  14   c , which comprises a first half-bridge  34   a , a DC link  38  (with a capacitor  40 ) and a second half-bridge  34   b  connected in parallel. The midpoint  40   a  of the first half-bridge  34   a  may be connected to the output of the main converter  12  or to a preceding converter cell. The midpoint  40   b  of the second half-bridge  34   b  may be connected to a succeeding converter cell or may provide an output of the electrical converter  10 . 
     The switches  24 ′ of the half-bridges  34   a ,  34   b  may comprise Si-based semiconductor switches, such as Si IGBTs or Si IGCTs. Also the main converter  12  may have switches  24  of this type. However, it also may be that all of the switches  24 ′ of the converter cell  14   a ,  14   b ,  14   c  comprise SiC-based semiconductor switches, such as SiC MOSFETs. 
       FIG. 3B  shows a converter cell  14   c , which has the same circuit design as the one of  FIG. 3A , however, where the switches  24 ′ of the first half-bridge  34   a  comprise Si-based semiconductor switches and the switches  24 ″ of the second half-bridge  34   b  comprise SiC-based semiconductor switches. The converter cell  14   c  of  FIG. 3A  may be composed of two modules and/or may be seen as a hybrid cell. 
       FIGS. 1 to 2C  relate to single-phase electrical converters  10 . The following  FIGS. 4 to 6B  relate to three-phase electrical converters  10 . 
       FIG. 4  corresponds to  FIG. 1  and shows an electrical converter  10 , which comprises a main converter  12  with three phase outputs. To each of these outputs three series-connected converter cells  14   a ,  14   b ,  14   c  are connected. 
     For the electrical converter  10  of  FIG. 4 , all quantities may be seen as vector-valued. The controller  16  generates switching signals s 1abc , s 2abc , s 3abc , s 4abc , s 5abc  for the phases a, b, c of the main converter  12  and the respective converter cell  14   a ,  14   b ,  14   c  of the respective phase. The corresponding output voltages are u 1abc , u 2abc , u 3abc , u 4abc . 
       FIG. 5A  corresponds to  FIG. 2A  and shows a main converter, which is a three-phase two-level converter with three half-bridges  22  connected in parallel to a DC link  18 . 
       FIG. 5B  corresponds to  FIG. 2B  and shows a main converter, which is a three-phase three-level, neutral point piloted and/or T type converter with three circuits as described with respect to  FIG. 2B  connected in parallel to a split DC link  18 . 
       FIG. 5C  corresponds to  FIG. 2C  and shows a main converter, which is a three-phase three-level, active neutral point clamped converter with three circuits as described with respect to  FIG. 2C  connected in parallel to a split DC link  18 . 
       FIG. 6A  shows that a passive filter  42  may be connected between the electrical converter  10  and a load  44 . The passive filter  42  may comprise an inductor  46  in each phase interconnecting the electrical converter  10  and the load  44 . Furthermore, the passive filter  42  may comprise capacitors  48  interconnecting the phases, for example via a star-connection. 
     In general, with the method described herein, the main converter  12  may be designed to operate at low switching frequencies, since it does not have to perform an active damping of the filter  42 . For example, active damping may be accomplished with the converter cells  14   a ,  14   b ,  14   c.    
     Due to the high switching frequency of SiC half-bridges, the filter  42  may be designed at a higher resonance frequency, requiring smaller passive components. Particularly the converter side inductance may be significantly reduced. Inductors usually applied in dv/dt filter or EMC filter circuits may be sufficient to build a sine filter. 
     The smaller filter capacitors  48  are less likely to cause problems related to interferences with the load  44 , such as self-excitation in case of use with motors, or excitation of grid harmonics in case of grid connection. 
       FIG. 6B  shows that an electrical machine  50  with three galvanically separated windings  52  may be connected to the electrical converter  10 . On the side opposite to the electrical converter  10 , the windings  52  may be connected via a further converter  54 , which may be a two-level converter as designed like the converter shown in  FIG. 5A . The converter  54  may comprise SiC switches  24 ″. 
       FIG. 7  shows a diagram illustrating a controller  16  and a method for controlling the electrical converter  10  as described with respect to the previous figures. 
     To achieve very low harmonic distortions, the method employs a modulation technique, which may be called “sequential filtering” or “repetitive filtering”. Sequentially derived switching signals s 1abc , s 2abc , s 3abc  of different switching frequencies are derived with the method. In the following, instead of a scalar signals, vector-valued signals are considered. All quantities in the following have components with respect to the phases a, b and c. In the scalar case, only one component has to be considered and, for example, the switching signals would be s 1 , s 2 , s 3 . 
     The three switching signals s 1abc , s 2abc , s 3abc  are produced by a low-frequency pulse width modulation stage  56   a , a medium-frequency pulse width modulation stage  56   b , and a high-frequency pulse width modulation stage  56   c.    
     The low-frequency switching signal s 1abc , which may have been generated with a carrier signal of 50-250 Hz, is applied to the main converter  12 . 
     The medium-frequency switching signal s 2abc , which may have been generated with a carrier signal of 350-1 kHz, is applied to the first converter cell  14   a.    
     The high-frequency switching signal s 3abc , which may have been generated with a carrier signal of about 20 kHz, is applied to the second converter cell  14   b.    
     Further pulse width modulation stages for further converter cells  14   c  may be included. In the following it is assumed that the converter  10  has two stages of converter cells  14   a ,  14   b.    
     As already mentioned, it is beneficial to use different types of semiconductor switches  24 ,  24 ′,  24 ″ in the different converter and filtering stages. For example, in the main converter  12 , one may use semiconductor switches  24  with high blocking voltages, comparatively high switching losses and preferably low conduction losses, such as IGCTs or high-voltage IGBTs. It is advantageous to operate these switches  24  at low switching frequencies, such as 50-250 Hz. 
     In the first converter cell  14   a , Si-based IGBTs may be used with a medium switching frequency of around 350 Hz-1 kHz. In the second converter cell  14   b , SiC-based switches  24 ′ may be used, enabling high switching frequencies of about 20 kHz. Using such a high switching frequency for the second converter cell  14   b  allows one to design an LC sine filter  42  with very small and low-cost inductors  46 . The corresponding resonance frequency f res  can be designed to be as high as 6 kHz. The current control bandwidth may be very high and active damping also may be easily implemented, if needed. 
     Returning to  FIG. 7 , the controller  16  receives a three-phase reference voltage ν* abc  with the phases a, b and c. The reference voltage ν* abc  may be provided by a current controller. During steady-state operation, the reference voltage ν* abc  is usually a sinusoidally varying quantity. 
     The reference voltage ν* abc  is divided by half the total DC link voltage ν 1dc  of the main converter  12 , to scale it. The resulting three-phase modulating signal u* 1abc  may be then scaled to the range [−1 1] 3 . It is fed to the first pulse width modulation stage  56   a , which produces the three-phase switching signal s 1abc , which in the case of a three-level main converter  12  may have the levels/values −1, 0 and −1. The low-frequency modulation stage  56   a  may operate at a very low pulse number, for example with fundamental frequency switching, or with a pulse width modulation with a low pulse number. 
     The three-phase terminal voltage of the main converter  12  is u 1abc . This voltage can be either measured or reconstructed based on the DC link voltage via, for example by multiplying the switching signal s 1abc  with half of the DC link voltage ν 1dc . The difference between the reference voltage ν* abc  and the estimated main converter voltage ν 1abc  is the (first) voltage error ν* 2abc =ν* 1abc −ν 1abc . 
     The voltage error ν* 2abc  is scaled by the capacitor voltage ν 2dc  of the first converter cell  14   a  and is fed to the second pulse width modulation stage  56   b . The second pulse width modulation stage  56   b  produces the three-phase switching signal s 2abc  with levels −1, 0 and 1 for the switches  24 ′ in the first converter cell  14   a.    
     It also may be that the second pulse width modulation stage  56   b  evenly distributes the switching signals to the two half-bridges  34   a ,  34   b  of the converter cell  14   a . This may be done, for example, by using two carriers for the modulation of the converter cell switches  24 ′. The carriers may be phase shifted by 180°. 
     The switching frequencies of both half-bridges  34   a ,  34   b  in the converter cell  14   a  may be equal and the switching losses may be evenly distributed between the two half-bridges  34   a ,  34   b.    
     The three-phase terminal voltage after the first converter cells  14   a  is u 2abc . The difference of this voltage with respect to the first voltage u 1abc  may again be either measured or reconstructed based on the DC link voltage ν 2dc  of the first converter cell  14   a , for example by multiplying the switching signal s 2abc  with the DC link voltage ν 2dc . The difference between the first voltage error ν* 2abc  and the second estimated converter cell voltage ν 2abc  is the second voltage error ν* 3abc =ν* 2abc −ν 2abc . 
     The second voltage error ν* 3abc  is scaled by the capacitor voltage ν 3dc  of the second converter cell  14   b  and is fed to the third pulse width modulation stage  56   c . The third pulse width modulation stage  56   c  produces the three-phase switching signal s 3abc  with levels −1, 0 and 1 for the switches  24 ′ in the second converter cell  14   b.    
     The objective of the third modulation stage may be to nearly remove the third voltage error ν* 3abc . The principle may be the same as for the second modulation stage, yielding a three-phase switching signal s 3abc  with the components −1, 0 and 1 for the switches  24 ′ in the second converter cell  14   b.    
     In  FIG. 7 , the reference voltage ν* abc  and the voltage errors ν* 2abc , ν* 3abc  are divided by scalar quantities to obtain the modulating signals u* 1abc , u* 2abc , u* 3abc . These scalar quantities may be different from the nominal (or actual) DC link voltages. For example, if the DC link voltage ν 2dc  of the first converter cell  14   a  is rather small, it may be beneficial to scale μ* 2abc  with a value that is larger than ν 2dc  to avoid the second pulse width modulation stage  56   b  entering a nonlinear modulation regime. A corresponding increase in the residual error may be compensated by the subsequent third pulse width modulation stage  56   c.    
       FIG. 8  shows a diagram with the a-component of the modulation signal u* a , i.e. the scaled reference voltage ν* a , and scaled switching signals s 1a , s 2a , s 3a . Furthermore, the sum of the scaled switching signals is shown, which can be compared to the original modulation signal u* a . All signals are shown over one fundamental period of the voltage. 
     The controller shown in  FIG. 7  may be designed to minimize a differential-mode and a common-mode voltage error, which is the difference between the reference voltage ν* abc  and the output voltage u 2abc  at the terminals of the second converter cell  14   b.    
     In  FIG. 9 , a controller  16  is shown, which may be designed to only minimize the differential-mode component of this error, by considering the voltage error in the stationary orthogonal (αβ) coordinate system. 
     The reference voltage ν* αβ  may be provided in the stationary orthogonal (αβ) coordinate system and transformed by an inverse Clark transformation (performed by block  58   a ) in the three-phase (abc) coordinate system. After that it may be processed like described with respect to  FIG. 7  and the pulse width modulation stage  56  may generate the first switching signal slab. The estimated voltage ν 1abc  can be transformed back with a Clark transformation (performed by block  58   b ) into the stationary orthogonal (αβ) coordinate system and the voltage error ν* 2αβ  can be determined by subtracting the estimated voltage ν 1αβ  from the reference voltage ν* αβ . 
     The same transformations can be performed with respect to the second pulse width modulation stage  56   b.    
     It is also possible that common-mode components ν* γ , ν* 2γ , ν* 2γ  are added to each modulation stage  56   a ,  56   b ,  56   c  in order to achieve additional objectives, such as an extension of the linear modulation regime or the injection of fundamental voltage components in the converter cells  14   a ,  14   b  to balance the converter cell DC links  38 . 
     In particular, the reference voltage ν* αβ  may comprise a common-mode component ν* γ , which is provided by an external controller. Also, to the first voltage error ν* 2αβ , a common-mode component ν* 2γ  may be added and/or to the second voltage error ν* 3βα , a common-mode component ν* 3γ  may be added. 
       FIGS. 10 and 11  describe a controller  16  and a method, in which the half-bridges of a converter cell  14   c  are switched with different switching signals s 2abc , s 3abc . The example of  FIGS. 10 and 11  refers to a controller  16  with the main converter  12  connected to a converter cell  14   c  as shown in  FIG. 3B . For one or more additional converter cells  14   a  between the main converter  12  and the converter cell  14   c , more pulse width modulation stages  56   b  may be added to the controller  16  as described with respect to  FIGS. 7 and 9 . 
     The converter cell  14   c  may be a hybrid converter cell, with different types of semiconductor switches  24 ′,  24 ″, which half-bridges  34   a ,  34   b  operate at different switching frequencies. For example, one half-bridge  34   a  may be operated at a first, for example, medium switching frequency by a switching signal s 2abc , using Si-based switches  24 ′, and the second half-bridge  34   b  may be operated at a higher switching frequency by a switching signal s 3abc , using SiC-based switches  24 ″. 
     With respect to  FIG. 10 , the first, low-frequency pulse width modulation stage  56   a  may be designed as described with respect to  FIG. 9  (or alternatively with respect to  FIG. 7 ). The pulse width modulation stage  56   d  generates two switching signals s 2abc , s 3abc . The modulating signal u* 2abc  is unevenly distributed between the two half-bridges  34   a ,  34   b  with an asymmetric modulation process, which is described for one component with respect to  FIG. 11 . 
     The modulation process of the pulse width modulation stage  56   d  may be implemented with two phase-disposition carriers. Whenever the modulating signal u* 2a  is in the upper half (u*&gt;=0), the switching signal s 2 , for the medium-frequency half-bridge  34   a  is set to 0 (add voltage), if it is in the lower half (u*&lt;0), the signal is set to 1 (subtract voltage) (see block  66 ). 
     For the modulation of the high-frequency half-bridge  34   b , the modulating signal u* 2a  is compared to high-frequency triangular carrier waveforms. The switching signal s 3a  is set to 1 if the modulating signal u* 2a  exceeds the carrier  60  in the upper half for (u*&gt;=0) or if the modulating signal u* 2a , exceeds the carrier  60  in the lower half for (u*&lt;0). Otherwise, the switching signal s 3a  is set to 0. This may be achieved by generating two switching signals  62  from the carrier signals  60  and to select the appropriate one with a selector  64 , which selects the first signal  62 , when the modulating signal u* 2a  is in the upper half (u*&gt;=0), or the second signal  62 , when the modulating signal u* 2a , is in the lower half (u*&lt;0). 
     While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art and practising the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. A single processor or controller or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.