Patent Publication Number: US-7903895-B2

Title: Data transformation device for image processing

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to image processing, and more particularly relates to a data transformation device performing discrete cosine transforms and inverse discrete cosine transforms. 
     2. Description of the Related Art 
     MPEG-4 is a multimedia video data compression standard. MPEG data is supported by a wide variety of products, including, digital televisions, set-top boxes, digital satellite systems (DSS), televisions, decoders, digital versatile disk players (DVD players), video conferencing apparatuses and web cams among others. MPEG compression reduces file size, thus, less storage is required in the described devices. Moreover, the bandwidth required for transmission of video and image data is reduced. 
       FIG. 1  is a diagram illustrating a conventional image compression device. The conventional image compression device comprises a discrete cosine transform operator (DCT operator)  13  and a quantizer  14 . The DCT operator  13  is configured to perform discrete cosine transforms (DCT). The quantizer  14  is configured to quantize the DCT factors. The conventional image compression device provides a feedback path comprising an inverse quantizer  15 , an inverse DCT operator  16 , an adder  17 , switching logic units  12  and  19 , and a subtractor  11 . The conventional image compression device is configured with an image memory  18  for extracting a motion vector V. The conventional image compression device further comprises a coding controller  10  for controlling the quantizer  14  and the switching logic units  12  and  19 . 
     The DCT operator  13  can process input image data where the image size is N×N. The DCT process of the conventional image compression device processes and transforms the data by the row-column decomposition method, as shown in  FIG. 2 . The number of multiplications is reduced by the row-column decomposition method with the property of the DCT kernel. The DCT operator  13  outputs the transformed N.times.N data square to the quantizer  14  subsequent to row-column decomposition. 
     In the row-column decomposition, the row-direction image data of the N×N image data is first provided to a first direction DCT operate  131 . The first direction DCT operate  131  applies the processed row-direction image data row-column decomposition stored in a transportation memory  132 . The image data processed by the first direction DCT operator  131  is read in the column-direction and provided to a second direction DCT operator  133  for processing by the second direction DCT operator  133  in the column-direction. 
     In the row-column decomposition of the conventional DCT calculation, the DCT factors are quantized by the quantizer subsequent to the first and the second direction DCT calculation with the N×N image block by the DCT operator. The dequantizer  15  is enabled subsequent to processing by the N×N image block. After the dequantizer  15  outputs the dequantization result, the inverse discrete cosine transform (IDCT) operator  16  starts the IDCT calculation. The DCT operator  13 , the quantizer  14 , the dequantizer  15 , and the IDCT operator  16  operate, respectively, in the different phases. 
     In the conventional method, the DCT and the IDCT are applied by the DCT operator  13  and the IDCT operator  16 , respectively, thus, higher occupation of a chip area results. 
     SUMMARY 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     The invention provides a data transformation device. An exemplary embodiment of a data transformation device comprises a pre-processing unit, a calculating unit and a post-processing unit. The pre-processing unit is configured to perform a first pre-process with received image data to generate pre-processed image data, and to perform a second pre-process with received result data to generate pre-processed result data. The calculating unit is configured to generate first calculating data and second calculating data according to the pre-processed image data and the pre-processed result data, respectively, by both a first calculating component and a second calculating component. The post-processing unit is configured to perform a first post-process to generate the result data according to the first calculating data, and to perform a second post-process to generate the image data according to the second calculating data. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is a diagram illustrating a conventional image compression device. 
         FIG. 2  is a block diagram illustrating a row-column decomposition method of the conventional DCT calculation. 
         FIG. 3  is a diagram illustrating an exemplary embodiment of a data transformation system. 
         FIG. 4A  is a diagram illustrating an exemplary embodiment of a data transformation device. 
         FIG. 4B  is a diagram illustrating an exemplary embodiment of a data transformation device. 
         FIG. 5  is a diagram illustrating an exemplary embodiment of a first calculating component. 
         FIG. 6  is a diagram illustrating an exemplary embodiment of a second calculating component. 
     
    
    
     DETAILED DESCRIPTION OF INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 3  is a diagram illustrating an exemplary embodiment of a data transformation system  300  comprising a data transformation device  310  and a memory  302 . 
     The data transformation system  300  performs a discrete cosine transform (DCT) calculation with 2-dimensional image data  322  and then generates 2-dimensional result data  324 . The data transformation system  300  also performs an inverse discrete cosine transform (IDCT) calculation with the 2-dimension result data  324  and then generates the 2-dimensional image data  322 . The 2-dimensional image data  322  and  324  may be frame data or one-dimensional processing data stored in a memory. 
       FIG. 4A  is a detailed diagram illustrating an exemplary embodiment of the data transformation system  300 . The data transformation device  310  comprises a pre-processing unit  420 , a calculating unit  420  and a post-processing unit  404 . The calculating unit  420  comprises a first calculating component  422  and a second calculating component  424 . 
     DCT calculation by the data transformation system  300  is given as an example. The pre-processing unit  402  performs a first pre-process to generate pre-processed image data  412  according to each row image data in the 2-dimensional image data  322 . The first pre-process may re-sort all the row image data or perform additions and subtractions with all the row image data in the 2-dimensional image data  322 . The calculating unit  420  generates first calculated data  414 , respectively, by both the first calculating component  422  and the second calculating component  424  according to the pre-processed image data  412 . The first calculating component  422  and the second calculating component  424  are both skew circular convolution (SCC) units for performing skew circular convolution on the pre-processed image data  412 . The post-processing unit  404  performs a first post-process to generate row result data  416  according to the first calculated data  414  and to apply the row result data  416  stored in the memory  302 . The first post-process may perform additions and subtractions with the first calculated data  414 . Further, in an exemplary embodiment of the invention, the memory  302  is a transposition random access memory (RAM). 
     After each row image data in the 2-dimensional image data  322  is processed by the data transformation device  310  to generate the row result data  416 , column image data  418  of all the row result data  416  stored in the memory  302  are transmitted to the pre-processing unit  402 . 
     The pre-processing unit  402  performs the first pre-process to generate the pre-processed image data  412  according to the column image data  418 . The calculating unit  420  generates the first calculated data  414 , respectively, by both the first calculating component  422  and the second calculating component  424  according to the pre-processed image data  412 . The post-processing unit  404  performs the first post-process to generate the 2-dimensional result data  324  according to the first calculated data  414 . The DCT calculation is then complete. 
       FIG. 5  is a diagram illustrating an exemplary embodiment of the first calculating component  422 , comprising a first multiplexer  502 , a first flip-flop  504 , a second flip-flop  506 , a first inverse unit  508 , a first gain stage  510 , a second gain stage  512  and a first adder  514 . 
     While performing the DCT calculation, the first multiplexer  502  in the first calculating component  422  selects either the pre-processed image data  412  or a first feedback signal f 11  for output according to a first selection signal C 11  and then generates a first signal S 11  and a second signal S 12 . The first flip-flop  504  is coupled to the first multiplexer and a first node N 11  for latching the first signal S 11 . The second flip-flop  506  is coupled to the first node N 11  and a second node N 12  for latching the second signal S 12 . The first inverse unit  508  changes the polarity of the second signal S 12  and outputs the first feedback signal f 11 . The first gain stage  510  coupled to the first node N 11  obtains the product of the first signal S 11  and a first gain and output a first output signal O 11 . The second gain stage  512  coupled to the second node N 12  obtains the product of the second signal S 12  and a second gain and outputs a second output signal O 12 . The first adder  514  coupled to the first gain stage  510 , and the second gain stage  512 , obtains the sum of the first output signal O 11  and the second output signal O 12  and outputs the first calculated data  414 . 
       FIG. 6  is a diagram illustrating an exemplary embodiment of the second calculating component  424 . Second calculating component comprises: a second multiplexer  602 ; a third flip-flop  604 ; a fourth flip-flop  606 ; a fifth flip-flop  608 ; a sixth flip-flop  610 ; a second inverse unit  612 ; a third gain stage  614 ; a fourth gain stage  616 ; a fifth gain stage  618 ; a sixth gain stage  620  and a second adder  622 . 
     During the DCT calculation, the second multiplexer  602  in the second calculating unit  424  selects either the pre-processed image data  412  or a third feedback signal f 21  for output according to a third selection signal C 21  and then generates a fifth signal S 21 , a sixth signal S 22 , a seventh signal S 23  and an eighth signal S 24 . The third flip-flop  604  is coupled to the second multiplexer  602  and a third node N 21  for latching the fifth signal S 21 . The fourth flip-flop  606  is coupled to the third node N 21  and a fourth node N 22  for latching the sixth signal S 22 . The fifth flip-flop  608  is coupled to the fourth node N 22  and a fifth node N 23  for latching the seventh signal S 23 . The sixth flip-flop  610  is coupled to the fifth node N 23  and a sixth node N 24  for latching the eighth signal S 24 . The second inverse unit  612  changes the polarity of the eighth signal S 24  and outputs the third feedback signal f 21 . The third gain stage  614  coupled to the third node N 21  obtains the product of the fifth signal S 21  and a third gain and outputs a fifth output signal O 21 . The fourth gain stage  616  coupled to the fourth node N 22  obtains the product of the sixth signal S 22  and a fourth gain and outputs a sixth output signal O 22 . The fifth gain stage  618  coupled to the fifth node N 23  obtains the product of the seventh signal S 23  and a fifth gain and outputs a seventh output signal O 23 . The sixth gain stage  620  coupled to the sixth node N 24  obtains the product of the eighth signal S 24  and a sixth gain and outputs an eighth output signal O 24 . The second adder coupled to the third gain stage  614 , the fourth gain stage  616 , the fifth gain stage  618  and the sixth gain stage  620  obtains the sum of the fifth output signal O 21 , the sixth output signal O 22 , the seventh output signal O 23  and the eighth output signal O 24 , and outputs the second calculated data  414 . 
       FIG. 4B  is an exemplary embodiment of IDCT calculation by the data transformation system  300 . The pre-processing unit  402  performs a second pre-process to generate pre-processed result data  452  according to each row result data in the 2-dimensional result data  324 . The second pre-process may re-sort all the row result data or perform additions and subtractions with the all the row result data in the 2-dimensional result data  324 . The calculating unit  420  generates second calculated data  454 , respectively, by both the first calculating component  422  and the second calculating component  424  according to the pre-processed result data  452 . The first calculating component  422  and the second calculating component  424  both are skew circular convolution (SCC) units for performing skew circular convolution with the pre-processed result data  452 . The post-processing unit  404  performs a second post-process to generate row image data  456  according to the second calculated data  454  and applies the row image data  456  stored in the memory  302 . The second post-process may perform additions and subtractions with the second calculated data  454 . Further, in an exemplary embodiment of the invention, the memory  302  may be a transposition random access memory (RAM). 
     After each row result data in the 2-dimensional result data  324  is processed by the data transformation device  310  to generate the row image data  456 , column result data  458  of all the row image data  456  stored in the memory  302  are transmitted to the pre-processing unit  402 . 
     The pre-processing unit  402  performs the second pre-process to generate the pre-processed result data  452  according to the column result data  458 . The calculating unit  420  generates the second calculated data  454 , respectively, by both the first calculating component  422  and the second calculating component  424  according to the pre-processed result data  452 . The post-processing unit  404  performs the second post-process to generate the 2-dimensional image data  322  according to the second calculated data  454 , the IDCT calculation is then complete. 
     According to  FIG. 5 , during the IDCT calculation, the first multiplexer  502  in the first calculating component  422  selects either the pre-processed result data  452  or a second feedback signal fl 2  for output according to a second selection signal C 12  and then generates a third signal S 13  and a fourth signal S 14 . The first flip-flop  504  latches the third signal S 13 . The second flip-flop  506  latches the fourth signal S 14 . The first inverse unit  508  changes the polarity of the fourth signal S 14  and outputs the second feedback signal f 12 . The first gain stage  510  obtains the product of the third signal S 13  and the first gain and outputs a third output signal O 13 . The second gain stage  512  obtains the product of the fourth signal S 14  and the second gain and outputs a fourth output signal O 14 . The first adder  514  obtains the sum of the third output signal O 13  and the fourth output signal O 14  and outputs the second calculated data  454 . 
     According to  FIG. 6 , during the IDCT calculation, the second multiplexer  602  in the second calculating component  424  selects either the pre-processing result data  452  or a fourth feedback signal f 22  for output according to a fourth selection signal C 22  and then generates a ninth signal S 25 , a tenth signal S 26 , an eleventh signal S 27  and a twelfth signal S 28 . The third flip-flop  604  latches the ninth signal S 25 . The fourth flip-flop  606  latches the tenth signal S 26 . The fifth flip-flop  608  latches the eleventh signal S 27 . The sixth flip-flop  610  latches the twelfth signal S 28 . The second inverse unit  612  changes the polarity of the twelfth signal S 28  and outputs the fourth feedback signal f 22 . The third gain stage  614  obtains the product of the ninth signal S 25  and the third gain and outputs a ninth output signal O 25 . The fourth gain stage  616  obtains the product of the tenth signal S 26  and the fourth gain and outputs a tenth output signal O 26 . The fifth gain stage  618  obtains the product of the eleventh signal S 27  and the fifth gain and outputs an eleventh output signal O 27 . The sixth gain stage  620  obtains the product of the twelfth signal S 28  and the sixth gain and outputs a twelfth output signal O 28 . The second adder  622  obtains the sum of the ninth output signal O 25 , the tenth output O 26 , the eleventh output  027  and the twelfth output signal O 28  and outputs the second calculated data  454 . 
     A DCT calculation with four inputs is given as an example in the exemplary embodiment. The DCT transform formulas shown in the following: 
     
       
         
           
             
               
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     Let N=4, and obtain the following formulas: 
     
       
         
           
             
               
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     According to the property that cos(x)=−cos(π−x),  X (0),  X (1),  X (2),  X (3) can be simplified as the following: 
     
       
         
           
             
               
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               . 
             
           
         
       
     
     Let (x0+x3)=e0, (x0−x3)=e1, (x1+x2)=e2, (x1−x2)=e3,  X (0),  X (1),  X (2),  X (3) can be simplified as the following: 
     
       
         
           
             
               
                 X 
                 _ 
               
               ⁡ 
               
                 ( 
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             = 
             
               
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                 2 
               
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                     ⁢ 
                     
                         
                     
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                   + 
                   
                     e 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                 
                 ] 
               
             
           
         
       
       
         
           
             
               
                 X 
                 _ 
               
               ⁡ 
               
                 ( 
                 2 
                 ) 
               
             
             = 
             
               
                 1 
                 
                   2 
                 
               
               ⁢ 
               
                 
                   cos 
                   ⁡ 
                   
                     ( 
                     
                       
                         2 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         π 
                       
                       8 
                     
                     ) 
                   
                 
                 ⁡ 
                 
                   [ 
                   
                     
                       e 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       0 
                     
                     - 
                     
                       e 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                   
                   ] 
                 
               
             
           
         
       
       
         
           
             
               
                 X 
                 _ 
               
               ⁡ 
               
                 ( 
                 1 
                 ) 
               
             
             = 
             
               
                 1 
                 
                   2 
                 
               
               ⁡ 
               
                 [ 
                 
                   
                     
                       cos 
                       ⁡ 
                       
                         ( 
                         
                           π 
                           8 
                         
                         ) 
                       
                     
                     ⁢ 
                     e 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   + 
                   
                     
                       cos 
                       ⁡ 
                       
                         ( 
                         
                           
                             3 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             π 
                           
                           8 
                         
                         ) 
                       
                     
                     ⁢ 
                     e 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                   
                 
                 ] 
               
             
           
         
       
       
         
           
             
               
                 X 
                 _ 
               
               ⁡ 
               
                 ( 
                 3 
                 ) 
               
             
             = 
             
               
                 
                   1 
                   
                     2 
                   
                 
                 ⁡ 
                 
                   [ 
                   
                     
                       
                         cos 
                         ⁡ 
                         
                           ( 
                           
                             π 
                             8 
                           
                           ) 
                         
                       
                       ⁢ 
                       
                         ( 
                         
                           
                             - 
                             e 
                           
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           3 
                         
                         ) 
                       
                     
                     + 
                     
                       
                         cos 
                         ⁡ 
                         
                           ( 
                           
                             
                               3 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               π 
                             
                             8 
                           
                           ) 
                         
                       
                       ⁢ 
                       e 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   ] 
                 
               
               . 
             
           
         
       
     
     Thus, the result data  X (0),  X (1),  X (2),  X (3) may be obtained in the output terminal of the post-processing unit  404  by setting the pre-processed image data  412  as [e3, e1], the first gain as 
             cos   ⁡     (       3   ⁢           ⁢   π     8     )           
and the second gain as
 
     
       
         
           
             
               cos 
               ⁡ 
               
                 ( 
                 
                   
                     
                         
                     
                     ⁢ 
                     π 
                   
                   8 
                 
                 ) 
               
             
             . 
           
         
       
     
     Similarly, the result of the DCT calculation with eight inputs may be obtained by setting the gains in the first calculating component  422  and the second calculating component  424 . 
     The first calculating component  422  and the second calculating component  424  in the calculating unit  420  disclosed by the exemplary embodiments of the invention may perform both the DCT calculation and the IDCT calculation. Thus, because the DCT calculation and the IDCT calculation are jointly performed by the same hardware structure, required chip area is decreased and circuit costs can be reduced. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.