Patent Publication Number: US-8542162-B2

Title: Shift register unit, gate drive circuit, and display apparatus

Description:
BACKGROUND 
     Embodiments of the present disclosure relate to a display drive technology, and in particular, relate to a shift register unit, a gate drive circuit, and a display apparatus. 
     In the display drive technology, scan lines and data lines cross each other to form an active matrix. The drive circuits for the scan lines are usually realized by shift registers. The shift registers can be categorized into dynamic shift registers and static shift registers. The structure of a dynamic shift register is relatively simple, which needs small amount of Thin Film Transistor (TFT) devices; however, the power consumption of the dynamic shift register is relatively large, and its operation bandwidth is limited. The static shift register requires more TFT devices, but its operation bandwidth is large, and it costs less power. The factors, such as power consumption, reliability, and area, need to be considered together, when the performance of a shift register is considered. However, the power consumption and reliability have become important performance parameters with the size of the display panel increasing. 
       FIG. 1A  is a schematic structure of a shift register unit in a first prior art, and  FIG. 1B  is an operating timing diagram of the shift register unit in the first prior art. As shown in  FIG. 1A  and  FIG. 1B , a feedback transistor M 4  connected between the output terminal and the reset drive transistor M 5  is used to automatically turn off M 5  in the first prior art. In particular, during a period of evaluation of the output terminal, ck 1  is in high level, the output is in low level, and thus M 4  is turned on, whereby M 5  is turned off. During a period of reset of the output terminal, ck 1  is in the low level, M 3  is turned on, and in turn M 5  is turned on to charge the output terminal.  FIG. 2A  is a schematic structure of a shift register unit in a second prior art, and  FIG. 2B  is an operating timing diagram of the shift register unit in the second prior art. As shown in  FIG. 2A  and  FIG. 2B , the feedback transistor M 5  is connected between the output terminal and VDD by the control of a phase-inverted clock. During a period of evaluation of the output terminal, the output becomes in low level, M 5  is turned on, and M 1  is turned off, which results in that the output tell final remains at the low level. During a period of reset of the output terminal, CLK becomes in low level, which turns on M 3 , and in turn turning on M 1 , whereby the output terminal is charged by VDD. 
     However, since the output terminal is connected with a load, its potential changes relatively slow. For the first prior art, during the period of evaluation of the output terminal, it needs time to change the output terminal from the high level to the low level, and only when the voltage of the output terminal is lower than a preset threshold voltage, M 4  is turned on. Before M 4  is turned on, M 5  is still in ON state, therefore, there exists a direct current (DC) path from VDD to VSS though M 5  and M 2 . For the second prior art, during the period of reset of the output terminal, it needs time to change the output terminal from the low level to the high level, so M 5  is not turned off in time, therefore, there exists a direct current (DC) path from VDD to VSS though M 5  and M 3 . The existence of the DC path results in additional transient current, and increases power consumption of the shift register. 
     SUMMARY 
     The present disclosure provides a shift register unit, a gate drive circuit and a display apparatus, in order to eliminate the DC path, decrease the transient current, and reduce the power consumption of the shift register. 
     An embodiment of the present disclosure provides a shift register unit, comprising: an input module for inputting a first clock signal, a second clock signal, a frame start signal, a high voltage signal, and a low voltage signal, wherein the first clock signal is identical with the phase-inverted signal of the second clock signal within time interval of one frame; a processing module comprising a plurality of TFTs and connected to the input module, for generating a gate drive signal according to the first clock signal, the second clock signal, and the frame start signal, and controlling to configure a positive feedback of voltage changes between a first node and a second node formed by the plurality of TFTs to cut off a transient DC path formed by the input terminal of the high voltage signal, the input terminal of the low voltage signal, and at least one TFT in time; an output module connected with the processing module for sending the gate drive signal generated by the processing module. 
     Another embodiment of the present disclosure provides a gate drive circuit, comprising n shift register units connected in sequence, wherein n is a positive integer, and the shift register units adopt the shift register unit described above; wherein the output module of the i th  shift register unit is connected to the input module of the i+1th shift register unit to input the gate drive signal outputted from the i th  shift register unit into the i+1th shift register unit as the frame start signal of the i+1th shift register unit, wherein iε[1, n) and i is a positive integer; if the first clock signal input terminal of one of the shift register units is inputted with the first clock signal, and its second clock signal input terminal is inputted with the second clock signal, then the first clock signal input terminals of the previous shift register unit and the next shift register unit adjacent to the one shift register units are both inputted with the second clock signal, and the second clock signal input terminals of the previous shift register unit and the next shift register unit adjacent to the one shift register units are both inputted with the first clock signal; and the input module of the first shift register unit of the n shift register units is coupled with the frame start input signal from the external. 
     Further another embodiment of the present disclosure provides a display apparatus comprising the gate drive circuit described above. 
     The shift register unit, the gate drive circuit, and the display apparatus control the first node and the second node formed among the TFTs while generating the gate drive signal according to the clock signals, by configuring the input module, the processing module and the output module, such that the positive feedback of voltage changes is formed between the first node and the second node to cut off the transient DC path formed by the input terminal of the high voltage signal, the input terminal of the low voltage signal, and at least one TFT in time, which decreases the transient current, and reduces the power consumption of the shift register unit. 
     Further scope of applicability of the present disclosure will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the disclosure, are given by way of illustration only, since various changes and modifications within the spirit and scope of the disclosure will become apparent to those skilled in the art from the following detailed description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure will become more fully understood from the detailed description given hereinafter and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present disclosure and wherein: 
         FIG. 1A  is a schematic structure of a shift register unit in the first prior art; 
         FIG. 1B  is an operating timing diagram of the shift register unit in the first prior art; 
         FIG. 2A  is a schematic structure of a shift register unit in the second prior art; 
         FIG. 2B  is an operating timing diagram of the shift register unit in the second prior art; 
         FIG. 3  is a schematic structure of a first embodiment of the shift register unit provided by the present disclosure; 
         FIG. 4  is a schematic structure of a second embodiment of the shift register unit provided by the present disclosure; 
         FIG. 5  is a schematic structure of a third embodiment of the shift register unit provided by the present disclosure; 
         FIG. 6  is a schematic diagram of the operating timing of the third embodiment of the shift register unit provided by the present disclosure; 
         FIG. 7  is a schematic diagram of the simulated experimental result of the transient current generated during the period of evaluation in the third embodiment of the shift register unit provided by the present disclosure; 
         FIG. 8  is a schematic diagram of the simulated experimental result of the transient current generated during the period of reset in the third embodiment of the shift register unit provided by the present disclosure 
         FIG. 9  is a schematic structure of a first embodiment of the gate drive circuit provided by the present disclosure; 
         FIG. 10  is a schematic structure of a second embodiment of the gate drive circuit provided by the present disclosure; and 
         FIG. 11  is a schematic diagram of the operating timing of the second embodiment of the gate drive circuit provided by the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     In order to make the objects, technical solutions, and advantages of the embodiments of the present disclosure more clear, a clear and complete description of the technical solutions of the embodiments of the present disclosure is made, in conjunction with the drawings accompanying the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all of them. All other embodiments obtained by those skilled in the art based on the embodiments in the present disclosure without any creative work will fall within the scope of the present disclosure. 
       FIG. 3  is a schematic structure of the first embodiment of the shift register unit provided by the present disclosure. As shown in  FIG. 3 , the embodiment provides a shift register unit that may comprise an input module  1 , a processing module  2 , and an output module  3 . The input module  1  is used to input signals, which may include a first clock signal, a second clock signal, a frame start signal, a high voltage signal, and a low voltage signal, wherein the first clock signal and the phase-inverted signal of the second clock signal are the same within the time interval of one frame. The processing module  2  comprising a plurality of TFTs is connected to input module  1 , generates a gate drive signal according to the first clock signal, the second clock signal, and the frame start signal, and controls to configure a positive feedback of voltage changes between a first node and a second node formed by the plurality of TFTs to cut off a transient DC path formed by the input terminal of the high voltage signal, the input terminal of the low voltage signal, and at least one TFT in time. The output module  3  is connected with the processing module  2 , and sends the gate drive signal generated by the processing module  2 . 
     The embodiment provides a shift register unit, wherein by configuring the input module, the processing module and the output module, the first node and the second node formed by the TFTs are controlled while the gate drive signal is generated according to the clock signals, such that the positive feedback of voltage changes is formed between the first node and the second node to cut off the transient DC path formed by the input terminal of the high voltage signal, the input terminal of the low voltage signal, and at least one TFT in time, which reduces the transient current, and reduces the power consumption of the shift register unit. 
       FIG. 4  is the schematic structure of the second embodiment of the shift register unit provided by the present disclosure. As shown in  FIG. 4 , the embodiment provides a shift register unit, wherein the processing module  2  may specifically comprise a gate drive signal generation unit  21  and a feedback control unit  22  on the basis of the structure shown in  FIG. 3 . The gate drive signal generation unit  21 , which may comprise at least an evaluation TFT and a reset TFT, is connected with the input module  1 , and generates the gate drive signal according to the first clock signal, the second clock signal, and the frame start signal. The ON and OFF of the evaluation TFT is driven by the first node, and the ON and OFF of the reset TFT is driven by the second node. The feedback control unit  22 , which may comprise a first control TFT and a second control TFT, is connected with the gate drive signal generation unit  21 , and controls to configure a positive feedback of voltage changes between the first node and the second node to cut off a transient DC path formed by the input terminal of the high voltage signal, at least one TFT, and the input terminal of the low voltage signal in time. 
       FIG. 5  is a schematic structure of the third embodiment of the shift register unit provided by the present disclosure. As shown in  FIG. 5 , the input module of the shift register unit provided by the embodiment may specifically comprise an initial signal input terminal (IN), a first clock signal input terminal (CLKB), a second clock signal input terminal (CLK), a high voltage signal input terminal (VDD), and a low voltage signal input terminal (VSS) on the basis of the embodiment described above. The initial signal input terminal (IN) is used to input the frame start signal, the first clock signal input terminal (CLKB) is used to input a first clock signal, the second clock signal input terminal (CLK) is used to input a second clock signal, the high voltage signal input terminal (VDD) is used to input the high voltage signal, and the low voltage signal input terminal (VSS) is used to input the low voltage signal. In this embodiment, the output module of the shift register unit may specifically comprise a output terminal (OUT) for sending the gate drive signal generated by the gate drive signal generation unit, and inputting the gate drive signal into the initial signal input terminal (IN) of the next adjacent shift register unit. 
     In particular, the gate drive signal generation unit of the shift register unit according to this embodiment may comprise a first TFT M 1 , a second TFT M 2 , a third TFT M 3 , a fourth TFT M 4 , and a fifth TFT M 5 . The gate of the first TFT M 1  is connected to the second clock signal input terminal (CLK), and the source of the first TFT M 1  is connected to the initial signal input terminal (IN). The second TFT M 2  may in particular be the evaluation TFT in the embodiment, the source of the second TFT M 2  is connected to the output terminal (OUT) of the output module, and the drain of the second TFT M 2  is connected to the first clock signal input terminal (CLKB). The gate of the third TFT M 3  is connected to the second clock signal input terminal (CLK), and the source of the third TFT M 3  is connected to the low voltage signal input terminal (VSS). The gate of the fourth TFT M 4  is connected to the first clock signal input terminal (CLKB). The fifth TFT M 5  may in particular be the reset TFT in this embodiment. The source of the fifth TFT M 5  is connected to the output terminal (OUT), and the drain of the fifth TFT M 5  is connected to the high voltage signal input terminal (VDD). 
     As shown in  FIG. 5 , a feedback control unit of the shift register unit provided by the embodiment may specifically comprise a sixth TFT M 6  and a seventh TFT M 7 . The source of the sixth TFT M 6  is connected to the high voltage signal input terminal (VDD), and the drain of the seventh TFT M 7  is connected to the high voltage signal input terminal (VDD). 
     Further, as shown in  FIG. 5 , in the embodiment, the drain of the first TFT M 1 , the gate of the second TFT M 2 , the drain of the sixth TFT M 6 , and the gate of the seventh TFT M 7  are connected together to form the first node N 1 . The drain of the fourth TFT M 4 , the gate of the sixth TFT M 6 , and the source of the seventh TFT M 6  are connected together to faun the second node N 2 . The drain of the third TFT M 3 , the source of the fourth TFT M 4 , and the gate of the fifth TFT M 5  are connected together to form the third node N 3 . 
       FIG. 6  is the schematic diagram of the operating timing of the third embodiment of the shift register unit provided by the present disclosure. As shown in  FIG. 6 , in this embodiment, the input signals of the shift register unit are a first clock signal XCLKB and a second clock signal XCLK, which are input into the first clock signal input terminal (CLKB) and the second clock signal input terminal (CLK), respectively. The two clock signals have a duty ratio of 50%, and their phases are opposite to each other. The phases of the clock signals of two adjacent shift registers are opposite to each other in the embodiment. That is to say, if the first clock signal input terminal (CLKB) of one shift register unit is inputted with an external first clock signal XCLKB, and its second clock signal input terminal (CLK) is inputted with an external second clock signal XCLK, then the first clock signal input terminal (CLKB) of the previous shift register unit adjacent to the one shift register unit is inputted with the external second clock signal XCLK, and its second clock signal input terminal (CLK) is inputted with the external first clock signal XCLKB. Also, the first clock signal input terminal (CLKB) of the next shift register unit adjacent to the one shift register unit is inputted with the external second clock signal XCLK, and its second clock signal terminal (CLK) is inputted with the external first clock signal XCLKB. A high voltage signal VDD is inputted into the high voltage signal input terminal (VDD) of the shift register units, a low voltage signal VSS is inputted into the low voltage signal input terminal (VSS) of the shift register units, a frame start signal STV is inputted into the initial signal input terminal (IN) of the first shift register unit, and the initial signal input terminals (IN) of all other shift register units are inputted with the output signals from the output terminals (OUT) of the respective previous shift register units adjacent to them. 
     Further, the shift register unit provided by the embodiment may comprise respective backup TFTs for those TFTs. That is to say, the first TFT M 1 , the second TFT M 2 , the third TFT M 3 , the fourth TFT M 4 , the fifth TFT M 5 , the sixth TFT M 6 , and the seventh TFT M 7  are respectively provided with corresponding backup TFTs, and the connections of the respective backup TFTs are the same as those of the corresponding TFTs. In other words, in the shift register unit, there may be arranged a corresponding backup TFT M 1 ′ with the same connection as the first TFT M 1 , i.e. the gate of M 1 ′ being connected to the second clock signal input terminal, and the source of M 1 ′ being connected to the initial signal input terminal; there maybe arranged a corresponding backup TFT M 2 ′ with the same connection as the second TFT M 2 , i.e. the source of M 2 ′ being connected to the output terminal of the output module, and the drain of M 2 ′ being connected to the first clock signal input terminal; there may be arranged a corresponding backup TFT M 3 ′ with the same connection as the third TFT M 3 , i.e. the gate of M 3 ′ being connected to the second clock signal input terminal, and the source of M 3 ′ being connected to the low voltage signal input terminal; there maybe arranged a corresponding backup TFT M 4 ′ with the same connection as the fourth TFT M 4 , i.e. the gate of M 4 ′ being connected to the first clock signal input terminal; there may be arranged a corresponding backup TFT M 5 ′ with the same connection as the fifth TFT M 5 , i.e. the source of M 5 ′ being connected to the output terminal, and the drain of M 5 ′ being connected to the high voltage signal input terminal; there may be arranged a corresponding backup TFT M 6 ′ with the same connection as the sixth TFT M 6 , i.e. the source of M 6 ′ being connected to the high voltage signal input terminal; there may be arranged a corresponding backup TFT MT with the same connection as the seventh TFT M 7 , i.e. the drain of M 7 ′ being connected to the high voltage signal input terminal. 
     Further, the shift register unit provided by the embodiment may comprise a charging capacitor C, one end of which is connected to the first node N 1 , and the other end of which is connected to the output terminal (OUT). When the size of the TFT M 2  is large enough, since Cgd may remain the voltage of the first node N 1  during one period, the function of the charging capacitor C in this embodiment can be realized by the parasitic capacitance Cgd inherent to the TFT M 2 , which further saves the area of the shift register. 
     It is noted that the first TFT M 1 , the second TFT M 2 , the third TFT M 3 , the fourth TFT M 4 , the fifth TFT M 5 , the sixth TFT M 6 , and the seventh TFT M 7  in the embodiment can all be realized by P-type transistors turned on by a low level or N-type transistors turned on by the high level. In this embodiment, the P-type transistor is taken as an example to make the description. 
     Referring to  FIG. 5  and  FIG. 6  again, TFTs M 1 -M 7  of the shift register unit in the embodiment are all turned on by the low level and turned off by the high level. Here, a description is made with the first shift register unit as an example. The first clock signal input terminal (CLKB) of the shift register unit is inputted with the first clock signal XCLKB, its second clock signal input terminal (CLK) is inputted with the second clock signal XCLK, and its initial signal input terminal (IN) is inputted with the frame start signal STV. 
     In the initial state, the signals inputted into the first clock signal input terminal (CLKB) and the second clock signal input terminal (CLK) are both in the low level, while the signal inputted into the initial signal input terminal (IN) is in the high level. During the period of t 1 , the first TFT M 1  is turned on by the low level of the second clock signal input terminal (CLK), and the initial signal input terminal (IN) is in the high level, whereby the first node N 1  is charged to the high level. The high level of the first node N 1  turns off the second TFT M 2  and the seventh TFT M 7 . The fourth TFT M 4  is turned on by the low level of the first clock signal input terminal (CLKB), and the third TFT M 3  is turned on by the low level of the second clock signal input terminal (CLK), which in turn electrically connects the third node N 3  with the low voltage signal input terminal (VSS), and makes the third node N 3  at the low level and the second node N 2  also at the low level. The fifth TFT M 5  is turned on by the low level of the third node N 3 , and the output terminal (OUT) are charged by the high voltage signal input terminal (VDD) to the high level. The sixth TFT M 6  is turned on by the low level of the second node N 2 . 
     Therefore, during the period of t 1 , the TFTs M 1 , M 3 , M 4 , M 5 , and M 6  are in ON state, while the TFTs M 2  and M 7  are in OFF state. The internal node N 1  is in the high level, the internal nodes N 2  and N 3  are in the low level, and the output is the high level. Because the TFT M 2  is in OFF state, the DC path from VDD to VSS through M 2  and M 5  is eliminated, and since the TFT M 7  is in OFF state, the DC path from VDD to VSS through M 7 , M 4 , and M 3  is eliminated as well. 
     During the period of t 2 , the first clock signal input terminal (CLKB) is inputted with a signal in high level, the second clock signal input terminal (CLK) is inputted with a signal in low level, and the initial signal input terminal (IN) is in the high level. The first TFT M 1  is turned on by the low level of the second clock signal input terminal (CLK), and the initial signal input terminal (IN) is in the high level, whereby the first node N 1  is charged to the high level. The high level of the first node N 1  turns off the second TFT M 2  and the seventh TFT M 7 . The third TFT M 3  is turned on by the low level of the second clock signal input terminal (CLK), which in turn electrically connects the third node N 3  with the low voltage signal input terminal (VSS), and makes the third node N 3  at the low level. The fifth TFT M 5  is then turned on by the low level of the third node N 3 , and the output terminal (OUT) are charged by the high voltage signal input terminal (VDD) to the high level. The signal inputted into the first clock signal input terminal (CLKB) is in the high level, which turns off the fourth TFT M 4 , resulting in the disconnection of the second node N 2  and the third node N 3 . However, since the second node N 2  still remains at the low level as in the period of t 1  at this point, the sixth TFT M 6  is turned on by the low level of N 2 , so as to accelerate the charging of the first node N 1  to the high level. Therefore, during the period of t 2 , the TFTs M 1 , M 3 , M 5 , and M 6  are in ON state, while the TFTs M 2 , M 4 , and M 7  are in OFF state. The internal node N 1  is in the high level, the internal nodes N 2  and N 3  are in the low level, and the output is the high level. Because the TFTs M 4  an M 7  are in OFF state, the DC path from VDD to VSS through M 7 , M 4 , and M 3  is eliminated as well. 
     During the period of t 3 , the first clock signal input terminal (CLKB) is inputted with a signal in low level, the second clock signal input terminal (CLK) is inputted with a signal in high level, and the initial signal input terminal (IN) is in the high level. The first TFT M 1  and the third TFT M 3  are turned off by the high level of the second clock signal input terminal (CLK). Thus the first node N 1  still remains at the high level, and the third node N 3  still remains at the low level. The low level of the third node N 3  turns on the fifth TFT M 5 , and then the output terminal (OUT) remains at the high level. The signal inputted into the first clock signal input terminal (CLKB) is in the low level, which turns on the fourth TFT M 4 , resulting in the connection of the second node N 2  and the third node N 3 , and thus the second node N 2  remains at the low level as well. The low level of the second node N 2  turns on the sixth TFT M 6 , which makes the first node N 1  remains at the high level. The high level of the first node N 1  then turns off the second TFT M 2  and the seventh TFT M 7 . The OFF state of the seventh TFT M 7  makes the second node N 2  remains at the low level. Therefore, during the period of t 3 , the TFTs M 4 , M 5 , and M 6  are in ON state, while the TFTs M 1 , M 2 , M 3 , and M 7  are in OFF state. The internal node N 1  is in the high level, the internal nodes N 2  and N 3  are in the low level, and the output is the high level. Because the TFT M 2  is in OFF state, the DC path from VDD to VSS through M 2  and M 5  is eliminated, and since the TFT M 7  is in OFF state, the DC path from VDD to VSS through M 7 , M 4 , and M 3  is eliminated as well. 
     During the period of t 4 , the first clock signal input terminal (CLKB) is inputted with a signal in high level, the second clock signal input terminal (CLK) is inputted with a signal in low level, and the initial signal input terminal (IN) is in the low level. This period is the pre-charging period of the shift register unit. The low level of the second clock signal input terminal (CLK) turns on the first TFT M 1  and the third TFT M 3 , thus the low level of the initial signal input terminal (IN) is transferred to the first node N 1 , which charges the charging capacitor C and turns on the TFT M 2 . The third node N 3  remains at the low level due to the low level of the low voltage signal input terminal (VSS). The high level of the first clock signal input terminal (CLKB) turns off the fourth TFT M 4 , which cuts off the path between the internal nodes N 2  and N 3 , and makes the second node N 2  remains at the high level. The high level of the second node N 2  turns off the sixth TFT M 6 , which further makes N 1  remains at the low level. The low level of the first node N 1  then turns on the seventh TFT M 7 , which makes the second node N 2  remains at the high level under the VDD. The low level of the third node N 3  turns on the fifth TFT M 5 , which then transfers the high level to the output terminal (OUT). Therefore, during the period of t 4 , the TFTs M 1 , M 2 , M 3 , M 5 , and M 7  are in ON state, while the TFTs M 4  and M 6  are in OFF state. The internal nodes N 1  and N 3  are in the low level, the internal node N 2  is in the high level, and the output is the high level. Because the TFT M 4  is in OFF state, the DC path from VDD to VSS through M 7 , M 4 , and M 3  is eliminated as well. 
     During the period of t 5 , the first clock signal input terminal (CLKB) is inputted with a signal in low level, the second clock signal input terminal (CLK) is inputted with a signal in high level, and the initial signal input terminal (IN) is in the high level. This period is the evaluation period of the shift register unit. The high level of the second clock signal input terminal (CLK) turns off the first TFT M 1  and the third TFT M 2 , resulting in the floating of the first node N 1 . The potential difference between the two ends of the charging capacitor C formed during the pre-charging period makes the voltage of the first node N 1  decrease, which terminates the floating state of N 1 , and thus turns on the second TFT M 2  and the seventh TFT M 7 . The ON state of the seventh TFT M 7  accelerates the second node N 2  to become at the high level. The high level of the second node N 2  then turns off the sixth TFT M 6  to cut off the path between the internal node N 1  and VDD, preventing N 1  from being charged by VDD, and also accelerating the voltage drop of N 1 . The low level of the first clock signal input terminal (CLKB) turns on the fourth TFT M 4 , which makes the path between the internal nodes N 2  and N 3 . The high level of the second node N 2  is transferred to the third node N 3  quickly, and then the high level of the third node N 3  turns off the fifth TFT M 5  quickly, which cuts off the DC path from VDD to VSS through M 2  and M 5  in time. The low level of the first clock signal input terminal (CLKB) is transferred to the output terminal (OUT) quickly due to the turning on of M 2 . Therefore, during the period of t 5 , the TFTs M 2 , M 4 , and M 7  are in ON state, while the TFTs M 1 , M 3 , M 5 , and M 6  are in OFF state. The internal node N 1  is in the low level, the internal nodes N 2  and N 3  are in the high level, and the output is the high level. Because the TFTs M 4  and M 7  are in OFF state, the DC path from VDD to VSS through M 7 , M 4 , and M 3  is eliminated as well. 
     During the period of t 6 , the first clock signal input terminal (CLKB) is inputted with a signal in high level, the second clock signal input terminal (CLK) is inputted with a signal in low level, and the initial signal input terminal (IN) is in the high level. This period is the reset period of the shift register unit. The low level of the second clock signal input terminal (CLK) turns on the first TFT M 1  and the third TFT M 3 , thus the high level of the initial signal input terminal (IN) is transferred to the first node N 1 , which turns off the TFT M 2 . After the third TFT M 3  is turned on, the third node N 3  remains at the low level due to the low level of the low voltage signal input terminal (VSS). The high level of the first clock signal input terminal (CLKB) turns off the fourth TFT M 4 , which cuts off the path between the internal nodes N 2  and N 3 , and makes the second node N 2  remain at the high level. The high level of the second node N 2  turns off the sixth TFT M 6 . The high level of the first node N 1  turns off the seventh TFT M 7 . The low level of the third node N 3  turns on the fifth TFT M 5 , which then transfers the high level to the output terminal (OUT). Therefore, during the period of t 6 , the TFTs M 1 , M 3 , and M 5  are in ON state, while the TFTs M 2 , M 4 , M 6 , and M 7  are in OFF state. The internal node N 3  is in the low level, the internal nodes N 1  and N 2  are in the high level, and the output is the high level. Because the TFTs M 4  and M 7  are in OFF state, the DC path from VDD to VSS through M 7 , M 4 , and M 3  is eliminated as well. 
     During the period of t 7 , the first clock signal input terminal (CLKB) is inputted with a signal in low level, the second clock signal input terminal (CLK) is inputted with a signal in high level, and the initial signal input terminal (IN) is in the high level. The low level of the first clock signal input terminal (CLKB) turns on the fourth TFT M 4 , which connects the path between the internal nodes N 2  and N 3 . The level of the second node N 2  is pulled down by the low level of the third node N 3 . The low level of the second node N 2  then turns on the sixth TFT M 6 , which further pulls up the level of the first node N 1 . The high level of the first node N 1  turns off the second TFT M 2  and the seventh TFT M 7 . The high level of the second clock signal input terminal (CLK) turns off the first TFT M 1  and the third TFT M 3 . The third node N 3  remains at the low level, which turns on the fifth TFT M 5 , and then transfers the high level of VDD to the output terminal (OUT) quickly. Therefore, during the period of t 7 , the TFTs M 4 , M 5 , and M 6  are in ON state, while the TFTs M 1 , M 2 , M 3 , and M 7  are in OFF state. The internal nodes N 2  and N 3  are in the low level, the internal node N 1  is in the high level, and the output is the high level. Because the TFT M 7  is in OFF state, the DC path from VDD to VSS through M 7 , M 4 , and M 3  is eliminated as well. 
       FIG. 7  and  FIG. 8  are the simulated experimental results of the transient currents generated during the evaluation period and the reset period in the third embodiment of the shift register unit provided by the present disclosure, respectively, wherein, the dashed lines represent the transient currents generated by the shift register unit in the prior art, and the solid lines represent the transient currents generated by the shift register unit in the embodiment. It can be seen that the transient currents of the shift register unit provided by the embodiment is much smaller than that in the prior art, for both the evaluation period and the reset period. By comparison of the simulated experimental results, to drive an active OLED pixel matrix of 240×320 (RGB), the average consumed currents by employing the structure of the shift register unit of the embodiment is around 18 μA per frame, while the average consumed currents by employing the structure of the shift register unit of the prior art is around 33.5 μA per frame. Therefore, 46% of the average power consumption can be saved by the present disclosure, compared with the prior art. 
     In the embodiment, by adding the sixth TFT M 6  and the seventh TFT M 7  in the shift register unit, the first node N 1  driving the second TFT M 2  and the second node N 2  driving the fifth TFT M 5  are controlled to form a positive feedback between them. That is to say, when the voltage of the first node N 1  begins to drop, the seventh TFT M 7  is turned on, and the turning on of the seventh TFT M 7  makes the level of the second node N 2  rise. The voltage rise of the second N 2  turns off the sixth TFT M 6 , and the turning off of the sixth TFT M 6  further accelerates the voltage drop of the first node N 1 , vice versa. Therefore, it is possible for the voltage of the internal nodes to be reset quickly. Moreover, in the embodiment, the positive feedback is triggered at the early stage of the voltage changing of the first node N 1  or the second node N 2  to accelerate the two node voltage&#39;s settling and cut off the transient current of the DC paths in time, which avoids the generation of the transient current due to that the voltage change of the output terminal is taken as a feedback in the prior art. Meanwhile, in the embodiment, the fourth TFT M 4  is used to isolate the internal nodes N 2  and N 3 , which also avoids the current leaking path from VDD to VSS through M 7  and M 3 . 
       FIG. 9  is the schematic structure of the first embodiment of the gate drive circuit provided by the present disclosure. As shown in  FIG. 9 , the embodiment provides a gate drive circuit, which may comprise n shift register units connected in sequence, wherein n is a positive integer. Each shift register unit in the embodiment can adopt any shift register unit described in the embodiments of  FIG. 3 ,  FIG. 4  or  FIG. 5 . The output module  3  of the i th  shift register unit SR i  is connected to the input module  1  of the i+1 th  shift register unit to input the gate drive signal outputted from the i th  shift register unit into the i+1 th  shift register unit as the frame start signal of the i+1 th  shift register unit, wherein iε[1, n) and i is a positive integer. Moreover, if the first clock signal input terminal of one shift register unit is inputted with the first clock signal, and its second clock signal input terminal is inputted with the second clock signal, then the first clock signal input terminals of the previous and the next shift register units adjacent to the one shift register unit are both inputted with the second clock signal, and the second clock signal input terminals of the previous and the next shift register units adjacent to the one shift register unit are both inputted with the first clock signal. 
       FIG. 10  is the schematic structure of the second embodiment of the gate drive circuit provided by the present disclosure. As shown in  FIG. 10 , the embodiment provides a specific gate drive circuit, which may comprise n shift register units connected in sequence, wherein n is a positive integer. Each shift register unit in the embodiment can adopt any shift register unit described in the embodiments of  FIG. 3 ,  FIG. 4  or  FIG. 5 . The high voltage signal input terminal (VDD) of each shift register unit is coupled with the high voltage signal VDD provided from the external, and the low voltage signal input terminal (VSS) of each shift register unit is coupled with the low voltage signal VSS provided from the external. 
     The first clock signal input terminal (CLKB) of the first shift register unit SR 1  is coupled with the first clock signal XCLKB provided from the external, and the second clock signal input terminal (CLK) of the first shift register unit SR 1  is coupled with the second clock signal XCLK provided from the external. The first clock signal input terminal (CLKB) of the second shift register unit SR 2  is coupled with the second clock signal XCLK provided from the external, and the second clock signal input terminal (CLK) of the second shift register unit SR 2  is coupled with the first clock signal XCLKB provided from the external. The first clock signal input terminal (CLKB) of the third shift register unit SR 3  is coupled with the first clock signal XCLKB provided from the external, and the second clock signal input terminal (CLK) of the third shift register unit SR 3  is coupled with the second clock signal XCLK provided from the external. Similarly, when j is an odd number, the first clock signal input terminal (CLKB) of the j th  shift register unit SR j  is coupled with the first clock signal XCLKB provided from the external, and the second clock signal input terminal (CLK) of the j th  shift register unit SR j  is coupled with the second clock signal XCLK provided from the external. When j is an even number, The first clock signal input terminal (CLKB) of the j th  shift register unit SR j  is coupled with the second clock signal XCLK provided from the external, and the second clock signal input terminal (CLK) of the j th  shift register unit SR j  is coupled with the first clock signal XCLKB provided from the external. However, if the first clock signal input terminal (CLKB) of the first shift register unit SR 1  is coupled with the second clock signal XCLK provided from the external, and the second clock signal input terminal (CLK) of the first shift register unit SR 1  is coupled with the first clock signal XCLK provided from the external, then the connections of the input terminals (CLKB and CLK) of the subsequent shift register units is opposite to that described above. 
     The initial signal input terminal (IN) of the first shift register unit is coupled with the frame start input signal STV provided from the external. The output terminal (OUT) of the output module of the first shift register unit is connected to the initial signal input terminal (IN) of the input module of the second shift register unit to input the gate drive signal output from the first shift register unit into the second shift register unit as the frame start signal of the second shift register unit. The output terminal (OUT) of the output module of the second shift register unit is connected to the initial signal input terminal (IN) of the input module of the third shift register unit to input the gate drive signal output from the second shift register unit into the third shift register unit as the frame start signal of the third shift register unit. Similarly, the output module of the i th  shift register unit is connected to the input module of the i+1 th  shift register unit to input the gate drive signal output from the i th  shift register unit into the i+1 th  shift register unit as the frame start signal of the i+1 th  shift register unit, wherein, iε[1, n) and i is a positive integer. The output terminal (OUT) of the output module of the n−1 th  shift register unit is connected to the initial signal input terminal (IN) of the input module of the n th  shift register unit to input the gate drive signal output from the n−1 th  shift register unit into the n th  shift register unit as the frame start signal of the n th  shift register unit. 
       FIG. 11  is the schematic diagram of the operating timing of the second embodiment of the gate drive circuit provided by the present disclosure. As shown in  FIG. 11 , the operating process of each shift register unit in the gate drive circuit provided by the embodiment is similar to the operation process of the shift register unit shown in  FIG. 5 , and will not be discussed here. 
     The present disclosure further provides a display apparatus, which can comprise the gate drive circuits shown in  FIG. 9  or  FIG. 10 . 
     Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solutions of the present disclosure, but not intended to limit the disclosure. Although the disclosure has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that the technical solutions recorded in the above-mentioned embodiments can be modified, or a part of their technical features can be replaced by equivalents thereof, and the modifications and replacements do not depart from the spirit and scope of the technical solution of each embodiment of the disclosure.