Patent Publication Number: US-6903992-B1

Title: Repair fuse box of semiconductor device

Description:
BACKGROUND 
   1. Field of the Invention 
   The present invention relates to a repair fuse box of a semiconductor device and, more specifically, to a repair fuse box having a structure in which a signal line can be drawn out from a repair fuse box without detour. 
   2. Discussion of Related Art 
   Recently, high-speed and highly integrated semiconductor devices have been developed with development of miniaturization technologies. In particular, high integration and high yield of semiconductor memory devices have been required, and in order to cope with the requirements, a redundancy technology, which improves a yield by providing redundancy circuits and repairing defective cells using the redundancy circuit, is essential. 
   In memory devices such as SRAM, DRAM, EPROM, and so on, redundancy circuits are provided in the semiconductor devices to prevent decrease of yields of the semiconductor devices due to process defects. The functions of the semiconductor devices are not damaged in spite of partial defects, by repairing defective cells using the provided redundancy circuits. That is, by providing a spare memory array as a redundancy circuit and switching a main memory array into the spare memory array when the main memory array is defective, decrease of production yield can be regulated. 
   The redundancy circuit comprises a repair address generating circuit. A conventional repair address generating circuit has a structure shown in  FIG. 1 , and its operation will be explained briefly as follows. 
   A fuse set A comprises a plurality of fuses R 0  to R 15 . 
   When an enable signal Enable is in a high state, a PMOS transistor P 1  is turned off, and thus its output Out holds a low state. 
   When the enable signal Enable is in a low state, the output Out is changed in accordance with fuse control signals Fuse &lt; 0 &gt; to Fuse &lt; 15 &gt; and cutting states of the fuses R 0  to R 15 . 
   For example, when the fuse control signal Fuse &lt; 0 &gt; is in a high state and the first fuse R 0  is not cut, the NMOS transistor Q 0  is turned on. Then, an output of a latch  10  is in a high state, and thus an output of the inverter I 1  turns to a low state, so that the output Out turns to a low state. However, when the fuse R 0  is cut, the output Out turns to a low state even if the fuse control signal Fuse &lt; 0 &gt; turns to a high state. 
   When forming the fuses in a fuse box shape to form the repair address generating circuit, metal signal lines cannot pass over the fuse box. Therefore, the metal signal line should detour around the fuse box for signal routing, and this make a chip size larger. 
   SUMMARY OF THE INVENTION 
   In order to solve the above problems, the present invention is directed to a repair fuse box of a semiconductor device. 
   According to an aspect of the present invention, there is provided a repair fuse box of a semiconductor device comprising: a plurality of fuse boxes arranged in a longitudinal direction, each fuse box comprising a plurality of fuses arranged in a transverse direction; signal connecting fuses arranged in each side portion of outermost fuses of the fuses which are selected from the fuses arranged in one or more fuse boxes of the plurality of fuse boxes to construct a unit fuse set and of which one side ends are connected mutually, the signal connecting fuses being connected to the outermost fuses; and metal lines for connecting the signal connecting fuses to the fuses selected to construct a unit fuse box in an upper or lower fuse box. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The aforementioned aspects and other features of the present invention will be explained in the following description, taken in conjunction with the accompanying drawings, wherein: 
       FIG. 1  is a circuit diagram of a conventional repair address generating circuit; 
       FIG. 2  is a circuit diagram of a repair address generating circuit according to the present invention; and 
       FIG. 3  is a layout diagram of a repair fuse box circuit according to the present invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   Now, the present invention will be described in detail with reference to the accompanying drawings. 
     FIG. 2  is a circuit diagram of a repair address generating circuit according to the present invention. 
   The repair address generating circuit according to the present invention further comprises signal connecting fuses R 16  and R 17 . The signal connecting fuses R 16  and R 17  can be made of any kind of materials as long as it is a conductive material. The operation of the circuit is not different from the operation of the conventional circuit. The operation will be described. 
   A fuse set B comprises a plurality of fuses R 0  to R 15  and signal connecting fuses R 16  and R 17 . 
   When an enable signal Enable is in a high state, a PMOS transistor P 1  is turned off, and thus an output Out of the circuit always holds a low state. 
   When the enable signal Enable is in a low state, the output Out of the circuit is changed in accordance with the fuse control signals Fuse &lt; 0 &gt; to Fuse &lt; 15 &gt; and the cutting states of the fuses R 0  to R 15 . 
   For example, when the fuse control signal Fuse &lt; 0 &gt; is in a high state and the first fuse R 0  is not cut, the NMOS transistor Q 0  is turned on. Then, an output of a latch  10  is in a high state, and thus an output of the inverter I 1  is in a low state, so that the output Out of the circuit turns to a low state. However, when the fuse R 0  is cut, the output Out of the circuit turns to a low state even if the fuse control signal fuse &lt; 0 &gt; is in a high state. 
     FIG. 3  is a layout diagram of the repair fuse box according to the present invention for explaining how the fuses of the fuse set B of  FIG. 2  are embodied in a substrate. 
   Fuse boxes  20 ,  30  and  40  are shown in FIG.  3 . The configuration of the fuse set B for constructing the circuit of  FIG. 2  will be explained as follows. 
   The fuses R 0  to R 4  are arranged in the fuse box  20 , and a signal connecting fuse R 16  is arranged to the left side of the fuse R 4 . Upper end portions of the fuses R 0  to R 4  and the signal connecting fuse R 16  are connected together through a metal, and so on. 
   In the same manner, the fuses R 5  to R 9  are arranged in the fuse box  30 , and a signal connecting fuse R 17  is arranged to the left side of the fuse R 9 . Lower end portions of the fuses R 5  to R 9  and the signal connecting fuse R 17  are connected together through a metal, and so on. 
   The signal connecting fuses R 16  and R 17  are connected together through a metal line M by using a contact process, and so on. 
   The fuses R 10  to R 15  are arranged in the fuse box  40 . Upper end portions of the fuses R 10  to R 15  are not only connected together through a metal, and so on, but also connected to the fuse box  30 . 
   As a result, one side nodes of the fuses R 0  to R 15  shown in  FIG. 2  are all connected each other through the signal connecting fuses R 16  and R 17 . 
   It should be noted that opened terminals of the fuses are connected to transistors. 
   Since the signal connecting fuses R 16  and R 17  are used for signal connection, they are not the cutting targets. 
   According to the present invention as described above, it is possible to connect the fuses without detour of the metal lines by using the fuse boxes. 
   As a result, since the signal routing can be implemented by using the fuses, it is possible to considerably reduce a chip size. 
   Although the foregoing description has been made with reference to the preferred embodiments, it is to be understood by the ordinary skilled in the art that changes and modifications of the present invention may be made without departing from the spirit and scope of the present invention and appended claims.