Patent Publication Number: US-7903010-B1

Title: Delta-sigma analog-to-digital converter (ADC) having a serialized quantizer output

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to analog-to-digital converters, and more specifically, to an analog-to-digital converter having a serialized quantizer output. 
     2. Background of the Invention 
     Delta-sigma analog-to-digital converters (ADCs) are in widespread use in consumer and industrial devices. Delta-sigma ADCs provide a very linear response and control of quantization noise. The relative simplicity of the architecture and the ability to finely control the quantization noise makes delta-sigma converter implementations very desirable. The delta-sigma modulator based analog-to-digital converter includes a loop filter that receives an input signal and a quantizer that converts the output of the loop filter to a digital representation. Feedback from the quantizer output is applied to the loop filter in feedback modulator topologies or is summed with the output of the loop filter in feed-forward modulator topologies to provide a closed-loop that causes the time-average value of the output of the quantizer to accurately represent the value of the modulator input signal. The loop filter provides shaping of the quantization noise at the output of the quantizer in response to the feedback signal applied from the quantizer to the loop filter. The feedback provided from the quantizer is typically generated by a coarse feedback DAC that receives the digital output of the quantizer and generates an analog value that is provided to the loop filter or the output summer. 
     The output of the delta-sigma ADC is generally the output of a decimation filter that is provided at a rate substantially lower than the quantization rate of the quantizer. The output decimated samples are usually provided in either a parallel or serial form. However, the input to the decimation filter, which is the output of the quantizer, is typically provided in a parallel form if the output of the quantizer has more than two levels. Since a typical quantizer may have, for example, seventeen levels, a serial bit stream at five times the quantization rate would be required to transfer the quantizer output using a typical serial interface. In some applications, for example in isolated circuits such as transformer-coupled or optically-isolated circuits, it is desirable to couple the quantizer output using a serial interface in order to transfer the data from the quantizer output to the serial interface over a single channel. However, the increased data rate required in an ADC having a number of quantizer levels greater than two comes with increased power requirements, increased component bandwidth requirements and higher generated levels of electromagnetic interference (EMI) due to the higher bit rates required. 
     Therefore, it would be desirable to provide a delta sigma ADC that has a serialized quantizer output without requiring a high serial data rate. 
     SUMMARY OF THE INVENTION 
     The above stated objective of providing a delta sigma ADC with a serialized quantizer output is achieved in an analog-to-digital converter circuit and its method of operation. 
     The analog-to-digital converter includes a loop filter that provides an output to a quantizer input. The output of the quantizer provides the output of a delta-sigma modulator and is converted using a digital-to-analog converter to provide a feedback signal to the loop filter. The output of the quantizer is coupled to a serial data circuit that serializes the output of the quantizer to produce a serial bit stream at a data rate that is higher than the quantization rate, but lower than the quantization rate multiplied by the number of bits required to represent the input to the digital-to-analog converter. 
     Additional information may be encoded in the selection among redundant codes provided in the serial bit stream and the output of the quantizer may be encoded as differences so that as few as two bits are required to represent the quantizer output, while providing two redundant codes that can be used to encode other information such as synchronization information, framing information (especially among multiple ADC channels) and an absolute value of the output of the ADC. 
     In a particular embodiment, the output of the quantizer may be provided to a digital integrator. A difference circuit generates a difference between a present value and a previous value if the output of the digital integrator provides a feedback signal to the loop filter, which may include a summing circuit for combining the feedback with a plurality of feed-forward signals provided from the loop filter. The output of the difference circuit is encoded in the serial bit stream, and the output of the digital integrator is then encoded in the selection of the redundant codes at a lower rate in order to provide the absolute output value of the ADC at the remote end of a serial interface that receives the serial bit stream. 
     The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram depicting a delta-sigma ADC in accordance with an embodiment of the present invention. 
         FIG. 2  is a block diagram depicting a delta-sigma ADC in accordance with another embodiment of the present invention. 
         FIG. 3  is a block diagram depicting a delta-sigma modulator that can be used in the ADC of  FIG. 2  in accordance with an embodiment of the present invention. 
         FIG. 4  is a timing diagram showing waveforms within the ADC converters of  FIG. 1  and  FIG. 2 . 
     
    
    
     DESCRIPTION OF ILLUSTRATIVE EMBODIMENT 
     The present invention encompasses a delta-sigma analog-to-digital converter (ADC) method and apparatus having a serialized quantizer output. The serial output provides for cost effective and simple isolation through a transformer, optical coupler, or capacitive coupling mechanism. The serial data output of the ADC of the present invention has a bit rate that is greater than the quantization rate, but less than a rate determined by the number of bits required to represent the output of the quantizer multiplied by the quantization rate. In other words, the ratio of the bit rate of the ADC output to the quantization rate is greater than unity, but less than the number of bits required to represent the output of the quantizer. Additional information such as synchronization for the samples and synchronization of a rotating pattern of multiple channels of data can be encoded in the bit stream by selecting among multiple redundant codes for one or more values of the quantizer output, which may be delta (difference) encoded. If the quantizer output is delta encoded, the additional information may include an absolute value of the quantizer output, so that the startup value can be determined from the absolute value and subsequent changes received at the remote side of the interface and any error due to a missed or erroneous transmission can be corrected. 
     Referring now to  FIG. 1 , a delta-sigma analog-to-digital converter (ADC) circuit  8 , in accordance with an embodiment of the present invention, is shown. A delta-sigma modulator  10  formed by a summer  11 , a loop filter  12  that noise-shapes the output of summer  11 , a quantizer  13  that converts the output of loop filter  12  to a digital value, and a digital-to-analog converter (DAC)  15  that provides a feedback signal to summer  11 . The time average of the output of quantizer  13  represents the value of the voltage of input signal in. A serial data circuit  14  converts the output of quantizer  13  to a serial bit stream serdat, and a modulator  16  may modulate serial bit stream serdat generated by serial data circuit  14  for transmission through transformer T 1 . In the depicted exemplary embodiment, the above described circuitry is contained within a first integrated circuit IC 1  which is coupled to a second integrated circuit IC 2  by transformer T 1 . Second integrated circuit IC 2  contains a serial receiver circuit  17  that receives modulated serial bitstream bpskdat, performs error checking and synchronization, and reconstructs serial bit stream serdat. Second integrated circuit IC 2  may also include a power supply and clock circuit  19  that superimposes or otherwise multiplexes a waveform carrying power and/or clock information on transformer T 1 . First integrated circuit IC 1  includes a rectifier circuit  27  for obtaining power supply voltage V DD  from the superimposed power waveform for operating first integrated circuit IC 1  and a clock extractor circuit  28  that generates a master clock mclk for operating quantizer  13 , serial data circuit  14  and modulator  16 . The output of serial receiver circuit  17  is provided to a digital filter  18 , which produces ADC samples at output out from a much larger number of quantizer output values reconstructed by serial receiver circuit  17  from serial bit stream serdat. The serial bit stream generated by serial data circuit  14  not only transforms the output of quantizer  13  to serial bit stream serdat, but also encodes additional information info in serial bit stream serdat. Additional information info is embedded by selecting among redundant codes, an example of which is illustrated below in Table I. 
                             TABLE I               Code   Quantizer output   info bit                                            000   −3   —       001   −2   —       010   −1   —       011   0   0       100   0   1       101   +1   —       110   +2   —       111   +3   —                    
As illustrated in Table I, in the depicted embodiment, the output of quantizer  13  has seven unique numeric values {−3, −2, −1, 0, 1, 2, 3}, but the three bits required to represent the output of quantizer  13  in binary form are capable of representing eight values. So, a redundant pair of codes can be assigned to one particular quantizer output level, which in the example are assigned to a value of 0 at the output of quantizer  13 . Therefore, when the output of quantizer  13  is 0, a bit of additional information info can be passed through transformer T 1 .
 
     The transfer rate of additional information info is dependent on the pattern of values at the output of quantizer  13 , since additional information info can only be transmitted when the value of the output of quantizer  13  is 0 in the illustrated encoding scheme, since 0 is the only value for which selection between multiple redundant codes can be made in order to encode the extra information. However, the transfer rate is sufficient for certain types of information, such as synchronization information and error correcting information that does not require a high transmission rate. Further, depending on the characteristics of input signal in and the response of loop filter  12 , the quantizer output value(s) chosen for assignment to redundant codes can be a more frequent value than other values. For example, in the embodiment illustrated in Table I, the zero code may be generated by more than 50% of samples, statistically, yielding an average bit rate of additional information info of at least ⅙ of the bit rate of the serial bit stream transmitted through transformer T 1 . 
     Referring now to  FIG. 2 , a delta-sigma ADC  8 A in accordance with another embodiment of the invention is shown. ADC  8 A of  FIG. 2  is similar to ADC  8  of  FIG. 1 , so only differences between them will be described below. A multiplexer  6  is included to select between multiple input signals in response to a selection value sel provided by a control circuit  20 , which may be for example, a microprocessor or state machine that manages the sampling of multiple input channels. Selection value sel may determine all or part of the additional information info and multiplexer  6  and control circuit  20  may also be included in the ADC of  FIG. 1 , but for the purposes of illustration, additional information info encoded by a serial data circuit  14 A will include framing information corresponding to selection value sel, as well as synchronization information indicating the location of the first bit of each serial value transmitted by serial data circuit  14 A, and an absolute value abs of the output of a limiter  21  included within delta-sigma modulator  10 A, which will be described in further detail below. 
     Limiter  21  receives the output of quantizer  13  and limits changes in the output codes generated by quantizer  13 , so that the difference between successive quantizer values can only be an increment (+1), a decrement (−1), or no change (0). A difference circuit, formed by unit delay  22  and subtractor  23  provides a serial bitstream diff, that encodes differences between the quantizer output values, and serial data circuit  14 A encodes the output of subtractor  23  in a two-bit serial bitstream as depicted in Table II below. 
                             TABLE II               Code   Quantizer output   info bit                                            00   −1   —       01   0   0       10   0   1       11   +1   —                    
Each time the output of quantizer  13  does not change, an extra bit of additional information is transmitted, which encodes the state of selection signal sel, a synchronization pattern that allows for recovery of the pattern alignment, which may be inherent in the coding of the additional information, and the absolute value abs of the output of limiter  21 . Absolute value as used in the present application indicates the full value of the output of limiter  21 , which may be signed or unsigned.
 
     Referring now to  FIG. 3 , a delta-sigma modulator  10 B with a topology in accordance with an embodiment of the present invention is shown. Delta-sigma modulator  10 B receives input in and provides a noise-shaped output abs. In delta-sigma modulator  10 B, output abs is provided from a digital integrator  40  that integrates the output of quantizer  13  that quantizes the output of the loop filter. Digital integrator includes a storage device, delay  44  that stores a previous value of the output of digital integrator  40  and an adder  42  that adds the present value of digital integrator  40  to the stored previous value, forming an accumulator. Output abs of adder  42  is serialized as a serial bit stream, transmitted, received and provided to a low-pass filter, e.g. as in ADC  8  of  FIG. 1 . 
     In order to account for the action of digital integrator  40 , a portion of the feedback signal applied to the loop filter is differentiated by a differencing circuit. In the depicted embodiment, the differencing circuit is provided by a differentiator  39  that receives an input from a DAC  36  and applied to a summer  33 C that provides the input to the final integrator stage  31 C. DAC  36  receives the output of storage device  44 . Another feedback path that is necessary for the converter to provide the correct DC and low-frequency output from the converter corresponding to the voltage of signal IN, is provided directly from DAC  36 . 
     In  FIG. 3 , a loop filter is implemented by a series of analog integrator stages  31 A- 31 C that each receive an input signal from the previous stage. Input summers  33 A and  33 C provide for combining feedback signals with the other inputs of the first and third integrator stages  31 A and  31 C, respectively. The output of integrator  31 C is combined by a summer  33 D with feed-forward signals scaled by scaling circuits  32 A- 32 D, provided from input signal in and the outputs of integrator stages  31 A-C, respectively. The output of summer  33 D provides the input to quantizer  13 . The resulting filter is a third-order filter with four tunable feed-forward paths. Combiners  33 A and  33 C- 33 D may be summing amplifiers, and scaling circuits  32 A-D may be resistors that set the gain of the summing amplifier with respect to the output of each integrator  31 A- 31 C. Alternatively, for switched-capacitor implementations, scaling circuits  32 A- 32 D will generally be the input charge-transfer capacitors and associated switching circuits. The depicted delta-sigma modulator is described in further detail and in alternative embodiments in U.S. Pat. No. 7,423,567, issued Sep. 19, 2008 to the Applicant, and which is incorporated herein by reference. The delta-sigma modulator techniques described in the above-referenced U.S. Patent are particularly useful in the context of the present invention, as the reduced number of quantizer output levels produced by the delta-sigma modulators disclosed therein can provide for serialization of the output of the quantizer with a small number of codes required. The resulting reduction in required codes enables assignment of one or more redundant codes to provide encoding of additional information in accordance with the techniques of the present invention. 
     Referring now to  FIG. 4 , a timing diagram depicting signals within the ADC circuit  8 A of  FIG. 2  is shown. Clock signal clk illustrates the quantization (sampling) period of delta-sigma modulator  10 A and serial bit stream serdat provided from the output of serial data circuit  14  is shown, encoding output diff of subtractor  23  with codes as shown in Table I with most significant bit (MSB) first. Additional information info is labeled below with an “x” and has a dashed line in the corresponding waveform in intervals during which additional information info is not present, and illustrated as having binary values 1 or 0 in intervals during which valid additional information info is present (i.e., when serial bit stream serdat is encoding “no change” or 0). Signal bpskdat is an illustrative output of modulator  16  showing bipolar phase-shift keying modulation, but it is understood that any suitable modulation technique such as frequency modulation (FM) or modified FM (MFM) may be used. Generally, suitable modulation techniques for transfer of signals through transformers, such as transformer T 1  of  FIG. 1 , are those having a zero net DC value, and unmodulated serialized outputs of quantizers in delta-sigma modulators of the present invention may also be used if the encoding is such that a net DC value is avoided in a long-term average of the serial bitstream. 
     Another encoding level as between the bits of additional information info, will generally be employed in order to synchronize the transmission of the additional information. For example, a marker can be generated by a succession of the same state of additional information info, such as two successive ones followed by a zero: “110”. Occurrence of the marker can provide synchronization information, and the codes between the markers can provide other information such as the absolute value abs of the quantizer output and channel framing information. For example if a sequence such as 1100011001100101101100 . . . is generated in additional information info and is interpreted as MOOMOM0010M0M00, where M is a marker, if the number of bits between each marker M is limited to five (or the number of codes starting with a zero is limited to 6 between successive “11” occurrences), then 18 codes are available, which can for example, encode 17 absolute quantizer levels and one extra code for indicating that other information follows in a next code, such as a channel number. 
     Table III illustrates an encoding scheme in which the coding scheme stated above is followed. The leading zero and the trailing “11” are included in the codes, so that each code includes a start bit “0” and a stop marker “11.” The unique (data-bearing) portion of each code is shown in bold. The codes shown in Table III are codes transmitted via the selection among redundant codes for the quantizer output difference information, such as codes “01” and “10” of Table II. Therefore, the Codes shown in column 1 of Table III are not bit sequences in serial bitstream serdat, but rather occurrences of the different redundant codes that indicate “0” and “1”. Further, as described above, the rate of transmission of the bits forming the codes illustrated in Table III varies with the occurrence of the codes in the quantizer difference information for which redundant code selection is possible. Therefore, the data rate of the information transmitted via the codes of Table III varies not only with the length of the code, but with the pattern of the difference information being generated by the quantizer at any given time. However, a constant average bit rate for the bits of the codes shown in Table III can be assumed, as the statistical likelihood of the difference values assigned to redundant codes should be relatively constant under normal operating conditions of the ADC. 
                             TABLE III               Code   Data Type   Value                                            01001011   Absolute Q value abs   0       0101011   Absolute Q value abs   1       01010011   Absolute Q value abs   2       0001011   Absolute Q value abs   3       00010011   Absolute Q value abs   4       00001011   Absolute Q value abs   5       010011   Absolute Q value abs   6       00100011   Absolute Q value abs   7       001011   Absolute Q value abs   8       01000011   Absolute Q value abs   9       010011   Absolute Q value abs   10       0100011   Absolute Q value abs   11       01011   Absolute Q value abs   12       0000011   Absolute Q value abs   13       000011   Absolute Q value abs   14       00011   Absolute Q value abs   15       0011   Absolute Q value abs   16       011   Channel zero sel   —                    
The first seventeen codes encode the absolute value of the quantizer at the time when the start bit is transmitted. When the receiver receives the full code, the cumulative value of the quantizer differences that have been received since the start bit was received are added to the received absolute quantizer offset value abs to determine the offset of the quantizer value at the receiver. After the initial absolute quantizer offset value abs, any differences between the computed value of quantizer offset value abs from a newly received code and the current absolute offset value at the receiver is an indication that a transmission error has occurred at some time and an indication of channel quality can be generated from the number of detected errors. The last code in Table III, NULL code 011, provides framing for multiple-channel ADCs and is emitted when the next code corresponds to channel 0. After the channel zero code, the channel values rotate from sample to sample, both in the top-level encoding of the quantizer difference output diff, and in the sub-code encoding of the absolute quantizer offset value abs via selection between the redundant difference codes.
 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.