Patent Publication Number: US-6664859-B1

Title: State machine based phase-lock-loop for USB clock recovery

Description:
BACKGROUND OF INVENTION 
     1. Field of the Invention 
     The present invention relates to clock signal generation. More specifically, the present invention relates to a state machine based phase-lock-loop generator of clock signals for a Universal Serial Bus (USB) protocol. 
     2. Description of the Prior Art 
     A Universal Serial Bus is a high-speed serial bus for communicating between a host computer and one or more USB devices, or more recently between two USB devices. The host and each USB device comprise a Serial Interface Engine (SIE) to provide an interface between the devices and to handle low-level USB functions such as error checking, hand-shaking, and token generation. 
     The SIE must generate transmit and receive clock signals to insure synchronization between the devices. Obviously for two-way communication between the devices, each device must include both a transmit clock and a receive clock. The transmit clock signal has a regular duty cycle and normally operates at 12 MHz or at 1.5 Mhz for slow devices. The receive clock cycle may be stretched or shrunk to accommodate data jitter in the USB and still latch on to the transmitting clock&#39;s signal as discussed in the USB specification. 
     One conventional clock scheme uses an analog phase-lock-loop (APLL) device. This method can introduce process dependencies, reduces re-usability, and has generally been replaced by digital state machines. 
     Early attempts at using a digital phase-lock-loop (DPLL) state machine required separate transmit and receive clocks and an outside circuit to select the appropriate clock. In an effort to eliminate possible malfunctioning of the selecting circuit and the difficulties with designing and maintaining a selecting circuit, U.S. Pat. No. 6,088,811 discloses a DPLL state machine replacing the selecting circuit with an intermediate state and is hereby included by reference. The intermediate state forms a bridge between two distinct groups of states (one for transmitting and one for receiving) and allows alternation between the two modes (groups of states) as appropriate to form a single DPLL state machine. 
     While the above-described disclosure does represent an improvement over the previous prior art, it still requires a complex design of two separate groups of states, an intermediate state, and complex circuitry to avoid entering undefined states. 
     SUMMARY OF INVENTION 
     It is therefore an objective of the claimed invention to provide a single mode state machine that uses a single group of states to simplify the complex circuitry in a state machine based phase-lock-loop (PLL) scheme for recovering the Universal Serial Bus (USB) clock from the USB. 
     The claimed state machine running at 4X speed includes only five states and generates a 1X speed clock. When transmitting, the claimed invention acts as a divide-by-four counter and divides the 4X clock into a 1X clock to be used by control logic (for example, a Serial Interface Engine). When receiving, the same state group acts as a divide-by-four counter with the received data&#39;s status being continuously monitored to dynamically adjust the duty cycle of the receiving clock. 
     The claimed invention changes from one state to another along predefined paths. 
     The exact selection of path is determined by the logical AND of a phase change within the data and a signal indicating whether the state machine is currently transmitting or receiving. 
     It is an advantage of the claimed invention that a single mode clock with a single group of 5 states is used for both transmitting and receiving USB signals. The claimed invention uses a single group of states to simplify design and reduce circuitry complexity, manufacturing costs, and power consumption in a PLL scheme to recover the Universal Serial Bus (USB) clock from the USB. The small size of the state machine facilitates implementation in only three bit registers. 
    
    
     These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings. 
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 is a block diagram of a control circuit to control a phase-lock-loop state machine according to the present invention. 
     FIG. 2 is an example of the phase-lock-loop state machine of FIG.  1 . 
     FIGS. 3-5 are charts illustrating the output of the phase-lock-loop state machine of FIG. 1 with differing bit times. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 is a block diagram of a control circuit  20  to control a phase-lock-loop state (PLL) according to the present invention. The control circuit  20  comprises a first D-flip-flop circuit  21 , a second D-flip-flop circuit  23 , an XOR operator  25 , and an AND operator  27 . 
     The first D-flip-flop circuit  21  comprises an input for receiving serial data, a second input for receiving an externally generated clock signal, and an output for the delayed serial data. In the example embodiment, the externally generated clock signal alternates at 48 MHz., but the present invention is not to be limited to this value. 
     The second D-flip-flop circuit  23  comprises an input for receiving the external clock signal, another input for receiving the serial data that has been delayed and outputted by the first D-flip-flop circuit  21 , and an output for the delayed serial data. 
     The XOR operator comprises an input for receiving the delayed serial data outputted from the first D-flip-flop circuit  21 , another input for receiving the again delayed serial data outputted from the second D-flip-flop circuit  23 , and an output that is connected to one input of the AND operator  27 . A second input of the AND operator  27  receives an Output Enable Bar (OEB) signal from a control logic device to indicate whether the present invention is to function as a receiving clock or as a transmitting clock. The output of the AND operator  27 outputs a Serial Data Change (sdchg) signal that controls the transitions between states in the PLL state machine. 
     FIG. 2 is an example of the PLL state machine  10  according to the present invention. The PLL state machine  10  comprises five states S 0 , S 1 , S 2 , S 3 , and S 4 . Immediately next to the name of each state is a set of brackets enclosing a “1” or a “0” representing the clock value that is supplied as a clock signal while in that particular state. Possible transitions from one state to another are shown in FIG. 2 as one-way arrows. Each transition in FIG. 2 has a “1” or a “0” associated with that particular transition and indicates condition of the sdchg signal at the time that the transition is begun. 
     For example, if receiving a perfect data stream, the sdchg signal may read  0 → 0 → 1 → 0 , the reset PLL state machine  10  beginning in S 1  would follow the path S 2 →S 3 →S 0 →S 1  and generate clock signals of  1 → 1 → 0 → 0  achieving a clock rate at exactly one-fourth of the external clock. Please note that when the PLL state machine  10  acts as a receiving clock, the OEB signal is always high so that the sdchg signal actually depends only on the output of the XOR operator  25 . On the other hand, when the PLL state machine functions as a transmitting clock, the OEB signal is always low so the sdchg signal is always low. This allows the PLL state machine  10  to function as a simple divide-by-four clock when transmitting and to dynamically adjust the duty cycle to latch onto a transmitting clock when serving as a receiving clock. 
     FIG. 3 is a chart illustrating the PLL state machine  10  in operation when receiving standard bit time showing how a 1X clock is derived from an externally generated 4X clock. The square wave SD_D 1  represents the serial data outputted from the first D-Flip-Flop circuit  21 . The square wave SD_D 2  represents the serial data outputted from the second D-Flip-Flop circuit  23 . The chart begins with the PLL state machine in the state S 0 . Note that the state S 0  outputs a “0” which indicates the low level of the CLK — 1X clock. Because the waves SD_D 1  and SD_D 2  are not in opposition with each other (here, both are high), the XOR operator  27  outputs a “0” to the AND operator  27 , which obviously also outputs a “0” as the sdchg signal. 
     Because the sdchg signal is a “0” , the PLL state machine  10  transits along the transition arrow marked with a “0” to state S 1 . The state S 1  also outputs a “0” for a clock signal as shown in FIG.  3 . While in the state S 1 , because SD_D 1  and SD_D 2  both remain in positive territory, the sdchg signal remains a “0” and the PLL state machine  10  transits to S 2 . The state S 2  outputs a “1” as the clock signal as shown in the CLK — 1X wave form under the state S 2 . 
     While in the state S 2 , again the SD_D 1  and SD_D 2  both remain in positive territory so the transition is made to the state S 3 . The state S 3  keeps the CLK — 1X at a high level. However, in the state S 3 , the SD_D 1  signal goes low while the SD_D 2  signal remains high, causing the XOR operator  25  to output a “1” that in turn causes the AND operator  27  to output a “1” as the sdchg signal. Therefore, the PLL state machine  10  transits to the state S 0  again, outputing a “0” as shown in the CLK — 1X wave form in FIG.  3 . 
     The above cycle repeats until, near the left side of FIG. 3, the extended duration of a low serial data signal causes the PLL state machine to dynamically adjust by transitioning in the following order; S 0 →S 1 →S 2 →S 3 →S 4 →S 1 →S 2 →S 3 , effectively temporarily exchanging the states S 0  and S 4 . Regardless, the PLL state machine  10  continues to output a perfect CLK — 1X signal. 
     FIG. 4 illustrates the PLL state machine  10  when the transmitting clock is slower than the PLL state machine  10  acting as a receiving clock. The duty cycle is dynamically adjusted to include a transition to a fifth state to compensate for the differences in timing between the clocks. The normal cycle runs S 0 →S 1 →S 2 →S 3 →S 4 →S 0 , including both the S 0  and the S 4  states. 
     FIG. 5 shows the PLL state machine  10  when the transmitting clock is faster than the present invention functioning as a receiving clock. The duty cycle again is dynamically altered to adjust to timing differences by reducing the cycle to 3 states; S 0 →S 1 →S 2 →S 0 . 
     One big advantage over the prior art of the PLL state machine  10  is that of requiring only five states to perform the dual functions of acting as a transmitting clock generator with a constant duty cycle and using the same five states to generate a variable duty receiving clock. The simplicity of requiring only five states allows the PLL state machine to be implemented in only three bit registers, the value of which indicates the current state, obviously simplifying construction and reducing manufacturing costs. 
     In contrast to the prior art, the present invention uses a single mode clock with a single group of 5 states for both transmitting and receiving USB signals. The small size of the present invention allows the use of registers to maintain the states. The claimed PLL state machine uses a single group of states to simplify design and reduce circuitry complexity, manufacturing costs, and power consumption in a PLL scheme to recover the Universal Serial Bus (USB) clock from the USB. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.