Patent Publication Number: US-9418613-B2

Title: GOA circuit of LTPS semiconductor TFT

Description:
FIELD OF THE INVENTION 
     The present invention relates to a display technology field, and more particularly to a GOA circuit of LTPS semiconductor TFT. 
     BACKGROUND OF THE INVENTION 
     GOA (Gate Drive On Array) is to manufacture the gate driver on the array substrate by utilizing the Thin Film Transistor (TFT) liquid crystal display array process for achieving the driving method of scanning line by line. 
     Generally, the GOA circuit comprises a pull-up part, a pull-up controlling part, a transfer part, a pull-down part, a pull-down holding part and a boost part in charge of boosting voltage level. The boost part generally comprises a bootstrap capacitor. 
     The pull-up part is mainly in charge of outputting the inputted clock signal (Clock) to the gate of the thin film transistor as being the driving signals of the liquid crystal display. The pull-up control part is mainly in charge of activating the pull-up part, and is generally functioned by the signal transferred from the former GOA circuit. The pull-down part is mainly in charge of rapidly pulling down the scan signal (i.e. the voltage level of the gate of the thin film transistor) to be low voltage level after outputting the scanning signal. The pull-down holding circuit part is mainly in charge of maintaining the scanning signal and the signal of the pull-up part in an off state (i.e. the set negative voltage level). The boost part in mainly in charge of performing a second boost to the voltage level of the pull-up part for ensuring the normal output of the pull-up part. 
     With the development of the LTPS semiconductor TFT, the LTPS-TFT LCD also becomes the focus that people pay lots of attentions. Because the LTPS semiconductor has better order than amorphous silicon (a-Si) and the LTPS itself has extremely high carrier mobility which can be more than 100 times of the amorphous silicon semiconductor, which the GOA skill can be utilized to manufacture the gate driver on the TFT array substrate to achieve the objective of system integration and saving the space and the cost of the driving IC. However, as considering the LTPS-TFT, the single type (single N-type or single P-type) GOA circuit has issues that the structure is complex, and the circuit property is poor, and particularly the power consumption is large. Especially, as mentioning the application in the small and medium size field, the power consumption is an important index of the performance. Therefore, how to reduce the power consumption and strengthen the circuit structure and the stability of the entire performance has become an important agenda faced by the GOA circuit of LTPS semiconductor TFT. 
     SUMMARY OF THE INVENTION 
     An objective of the present invention is to provide a GOA circuit of LTPS semiconductor TFT to solve the issues that the stability of the circuit is poor, and the power consumption is larger as concerning the LTPS with single type TFT elements; the problem of TFT leakage of the single type GOA circuit can be solved to optimize the performance of the circuit; meanwhile, the ultra narrow frame or frameless designs can be realized. 
     For realizing the aforesaid objective, the present invention provides a GOA circuit of LTPS semiconductor TFT, employed for forward scan transmission, comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit utilizes a plurality of N-type transistors and a plurality of P-type transistors and comprises a transmission part, a transmission control part, an information storage part, a data erase part, an output control part and an output buffer part; 
     the transmission part is electrically coupled to a first low frequency signal, a second low frequency signal, a driving output end of an N−1th GOA unit which is the former stage of the Nth GOA unit and the information storage part; the transmission control part is electrically coupled to a driving output end of an N+1th GOA unit which is the latter stage of the Nth GOA unit, the driving output end of the N−1th GOA unit which is the former stage of the Nth GOA unit, an M−2th sequence signal, a high voltage source, a low voltage source and the information storage part; the information storage part is electrically coupled to the transmission part, the transmission control part, the data erase part, the high voltage source and the low voltage source; the data erase part is electrically coupled to the information storage part, the output control part, the high voltage source and the reset signal end; the output control part is electrically coupled to the data erase part, the output buffer part, a driving output end, a sequence signal, the high voltage source and the low voltage source; the output buffer part is electrically coupled to the output control part, an output end, the high voltage source and the low voltage source; 
     the first low frequency signal is equivalent to a direct current high voltage level, and the second low frequency signal is equivalent to a direct current low voltage level; 
     the transmission part comprises: 
     a first P-type transistor, and a gate of the first P-type transistor is electrically coupled to the second low frequency signal, and a source is electrically coupled to the driving output end of the N−1th GOA unit which is the former stage of the Nth GOA unit, and a drain is electrically coupled to a first node; 
     a second N-type transistor, and a gate of the second N-type transistor is electrically coupled to the first low frequency signal, and a source is electrically coupled to the driving output end of the N−1th GOA unit which is the former stage of the Nth GOA unit, and a drain is electrically coupled to the first node; 
     the transmission control part comprises: 
     a fifth P-type transistor, and a gate of the fifth P-type transistor is electrically coupled to the driving output end of the N−1th GOA unit which is the former stage of the Nth GOA unit, and the source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a sixth P-type transistor; 
     the sixth P-type transistor, and a gate of the sixth P-type transistor is electrically coupled to the driving output end of the N+1th GOA unit which is the latter stage of the Nth GOA unit, and a source is electrically coupled to the drain of the fifth P-type transistor, and a drain is electrically coupled to a source of a seventh N-type transistor; 
     the seventh N-type transistor, and a gate of the seventh N-type transistor is electrically coupled to the driving output end of the N−1th GOA unit which is the former stage of the Nth GOA unit, and a source is electrically coupled to the drain of the sixth P-type transistor, and a drain is electrically coupled to the low voltage source; 
     an eighth N-type transistor, and the gate of the eighth N-type transistor is electrically coupled to the driving output end of the N+1th GOA unit which is the latter stage of the Nth GOA unit, and the source is electrically coupled to the drain of the sixth P-type transistor, and a drain is electrically coupled to the low voltage source; 
     a ninth P-type transistor, and a gate of the ninth P-type transistor is electrically coupled to the drain of the sixth P-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a tenth N-type transistor; 
     the tenth N-type transistor, and a gate of the tenth N-type transistor is electrically coupled to the drain of the sixth P-type transistor, and the source is electrically coupled to the drain of the ninth P-type transistor, and a drain is electrically coupled to the low voltage source; 
     an eleventh P-type transistor, a gate of the eleventh P-type transistor is electrically coupled to the drain of the sixth P-type transistor, and a source is electrically coupled to a source of a twelfth N-type transistor, and a drain is electrically coupled to the M−2th sequence signal; 
     the twelfth N-type transistor, and a gate of the twelfth N-type transistor is electrically coupled to the drain of the ninth P-type transistor, and the source is electrically coupled to the source of the eleventh P-type transistor, and a drain is electrically coupled to the M−2th sequence signal; 
     the information storage part comprises: 
     a thirteenth N-type transistor, and a gate of the thirteenth N-type transistor is electrically coupled to the source of the eleventh P-type transistor, and a source is electrically coupled to a drain of a fourteenth P-type transistor, and a drain is electrically coupled to the low voltage source; 
     the fourteenth P-type transistor, and a gate of the fourteenth P-type transistor is electrically coupled to the source of the eleventh P-type transistor, and a source is electrically coupled to the high voltage source, and the drain is electrically coupled to the source of the thirteenth N-type transistor; 
     a fifteenth P-type transistor, and a gate of the fifteenth P-type transistor is electrically coupled to the source of the thirteenth N-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a sixteenth P-type transistor; 
     the sixteenth P-type transistor, and a gate of the sixteenth P-type transistor is electrically coupled to the first node, and the source is electrically coupled to the drain of the fifteenth P-type transistor, and a drain is electrically coupled to a source of a seventeenth N-type transistor; 
     the seventeenth N-type transistor, and a gate of the sixteenth P-type transistor is electrically coupled to the first node, and the source is electrically coupled to the drain of the sixteenth P-type transistor, and a drain is electrically coupled to a source of an eighteenth N-type transistor; 
     the eighteenth N-type transistor, and a gate of the eighteenth N-type transistor is electrically coupled to the source of the eleventh P-type transistor, and the source is electrically coupled to the drain of the seventeenth N-type transistor, and a drain is electrically coupled to the low voltage source; 
     the data erase part comprises: 
     a twenty-third P-type transistor, and a gate of the twenty-third P-type transistor is electrically coupled to the reset signal end, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to the drain of the sixteenth P-type transistor; 
     the output control part comprises: 
     a twenty-fourth P-type transistor, and a gate of the twenty-fourth P-type transistor is electrically coupled to the drain of the sixteenth P-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to the driving output end; 
     a twenty-fifth N-type transistor, and a gate of the twenty-fifth N-type transistor is electrically coupled to the drain of the sixteenth P-type transistor, and a source is electrically coupled to the driving output end, and a drain is electrically coupled to the low voltage source; 
     a twenty-sixth P-type transistor, and a gate of the twenty-sixth P-type transistor is electrically coupled to the driving output end, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a twenty-ninth N-type transistor; 
     a twenty-seventh N-type transistor, and a gate of the twenty-seventh N-type transistor is electrically coupled to the driving output end, and a source is electrically coupled to a drain of the twenty-ninth N-type transistor, and a drain is electrically coupled to the low voltage source; 
     a twenty-eighth P-type transistor, and a gate of the sixteenth P-type transistor is electrically coupled to the sequence signal, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to the source of the twenty-ninth N-type transistor; 
     the twenty-ninth N-type transistor, and a gate of the twenty-ninth N-type transistor is electrically coupled to the sequence signal, and the source is electrically coupled to the drain of twenty-sixth P-type transistor, and a drain is electrically coupled to the source of the twenty-seventh N-type transistor; 
     the output buffer part comprises: 
     a thirtieth P-type transistor, and a gate of the thirtieth P-type transistor is electrically coupled to the source of the twenty-ninth N-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a thirty-first N-type transistor; 
     the thirty-first N-type transistor, and a gate of the thirty-first N-type transistor is electrically coupled to the source of the twenty-ninth N-type transistor, and the source is electrically coupled to the drain of the thirtieth P-type transistor, and a drain is electrically coupled to the low voltage source; 
     a thirty-second P-type transistor, and a gate of the thirty-second P-type transistor is electrically coupled to the drain of the thirtieth P-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a thirty-third N-type transistor; 
     the thirty-third N-type transistor, and a gate of the thirty-third N-type transistor is electrically coupled to the drain of the thirtieth P-type transistor, and the source is electrically coupled to the drain of the thirty-second P-type transistor, and a drain is electrically coupled to the low voltage source; 
     a thirty-fourth P-type transistor, and a gate of the thirty-fourth P-type transistor is electrically coupled to the drain of the thirty-second P-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to the output end; 
     a thirty-fifth N-type transistor, and a gate of the thirty-fifth N-type transistor is electrically coupled to the drain of the thirty-second P-type transistor, and a source is electrically coupled to the output end, and a drain is electrically coupled to the low voltage source. 
     The GOA circuit further comprises a second output control part, a second output buffer part; 
     the second output control part is electrically coupled to the output control part, the driving output end, an M+1th sequence signal, the high voltage source and the low voltage source; the second output buffer part is electrically coupled to the second output control part, an output end of the N+1th GOA unit, the high voltage source and the low voltage source; 
     the second output control part comprises: 
     a thirty-sixth P-type transistor, and a gate of the thirty-sixth P-type transistor is electrically coupled to the driving output end, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a thirty-ninth N-type transistor; 
     a thirty-seventh N-type transistor, and a gate of the thirty-seventh N-type transistor is electrically coupled to the driving output end, and a source is electrically coupled to the drain of the thirty-ninth N-type transistor, and a drain is electrically coupled to the low voltage source; 
     a thirty-eighth P-type transistor, and a gate of the thirty-eighth P-type transistor is electrically coupled to an M+1th sequence signal, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to the source of the thirty-ninth N-type transistor; 
     the thirty-ninth N-type transistor, and a gate of the thirty-ninth N-type transistor is electrically coupled to the M+1th sequence signal, and the source is electrically coupled to the drain of the thirty-sixth P-type transistor, and the drain is electrically coupled to the source of the thirty-seventh N-type transistor; 
     the second output buffer part comprises: 
     a fortieth P-type transistor, and a gate of the fortieth P-type transistor is electrically coupled to the source of the thirty-ninth N-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a forty-first N-type transistor; 
     the forty-first N-type transistor, and a gate of the forty-first N-type transistor is electrically coupled to the source of the thirty-ninth N-type transistor, and the source is electrically coupled to the drain of the fortieth P-type transistor, and a drain is electrically coupled to the low voltage source; 
     a forty-second P-type transistor, and a gate of the forty-second P-type transistor is electrically coupled to the drain of the fortieth P-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a forty-third N-type transistor; 
     the forty-third N-type transistor, and a gate of the forty-third N-type transistor is electrically coupled to the drain of the fortieth P-type transistor, and the source is electrically coupled to the drain of the forty-second P-type transistor, and a drain is electrically coupled to the low voltage source; 
     a forty-fourth P-type transistor, and a gate of the forty-fourth P-type transistor is electrically coupled to the drain of the forty-second P-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to an output end of the N+1th GOA unit; 
     a forty-fifth N-type transistor, and a gate of the forty-fifth N-type transistor is electrically coupled to the drain of the forty-second P-type transistor, and a source is electrically coupled to the output end of the N+1th GOA unit, and a drain is electrically coupled to the low voltage source. 
     In the first stage connection, all the source of the first P-type transistor, the source of the second N-type transistor, the gate of the fifth P-type transistor, the gate of the seventh N-type transistor are electrically coupled to an activation signal end of the circuit. 
     In the last stage connection, both the gate of the sixth P-type transistor and the gate of the eighth N-type transistor are electrically coupled to the activation signal end of the circuit. 
     In the transmission part, the first P-type transistor and the second N-type transistor construct a transmission gate, employed to forward transmit a driving output signal of the N−1th GOA unit to the information storage part. 
     In the transmission control part, the fifth P-type transistor, the sixth P-type transistor, the seventh N-type transistor, the eighth N-type transistor, construct a NOR gate logic unit; the ninth P-type transistor, the tenth N-type transistor construct an inverter; the eleventh P-type transistor, the twelfth N-type transistor construct a transmission gate; the transmission control part is employed to control the M−2th sequence signal and transmits it to the information storage part. 
     In the information storage part, the fifteenth P-type transistor, the sixteenth P-type transistor, the seventeenth N-type transistor, the eighteenth N-type transistor construct a sequence inverter; the thirteenth N-type transistor, the fourteenth P-type transistor construct an inverter; the information storage part is employed to save and transmit the signals from the driving output end of the N−1th GOA unit and the M−2th sequence signal. 
     The data erase part is employed to erase the voltage level of the driving output end of the circuit in due time. 
     In the output control part, the twenty-sixth P-type transistor, the twenty-seventh N-type transistor, the twenty-eighth P-type transistor and the twenty-ninth N-type construct a NAND gate logic unit; the twenty-fourth P-type transistor, twenty-fifth N-type transistor construct an inverter; the output control part is employed to control a scan signal outputted by the output end to output the scan signal according with time sequence. 
     In the output buffer part, the thirtieth P-type transistor and the thirty-first N-type transistor, the thirty-second P-type transistor and the thirty-third N-type transistor, the thirty-fourth P-type transistor and thirty-fifth N-type transistor respectively construct three inverters, employed to adjust the scan signal with a done sequence adjustment, and meanwhile, to strengthen a band loading capacity. 
     In the second output control part, the thirty-sixth P-type transistor, the thirty-seventh N-type transistor, the thirty-eighth P-type transistor, the thirty-ninth N-type transistor construct a NAND gate logic unit, employed to control the scan signal outputted by the output end of the N+1th GOA unit to output the scan signal according with time sequence; in the second output buffer part, the fortieth P-type transistor and the forty-first N-type transistor, the forty-second P-type transistor and the forty-third N-type transistor, the forty-fourth P-type transistor and the forty-fifth N-type transistor respectively construct three inverters, employed to adjust the scan signal with a done sequence adjustment, and meanwhile, to strengthen a band loading capacity; the second output control part and the second output buffer part output a scan signal of the latter stage from the output end of the N+1th GOA unit according to the outputted signal of the driving output end and the M+1th sequence signal to realize that the single stage GOA unit controls two stage circuits forward scan output. 
     The sequence signal comprises four sets of sequence signals: a first sequence signal, a second sequence signal, a third sequence signal, a fourth sequence signal, and the M−2th sequence signal is the third sequence signal when the sequence signal is the first sequence signal, and the M−2th sequence signal is the fourth sequence signal when the sequence signal is the second sequence signal, and the M+1th sequence signal is the first sequence signal when the sequence signal is the fourth sequence signal. 
     The benefits of the present invention are: the present invention provides the GOA circuit of LTPS semiconductor TFT, employed for forward scan transmission. The Nth GOA unit utilizes a plurality of N-type transistors and a plurality of P-type transistors, comprising a transmission part, a transmission control part, an information storage part, a data erase part, an output control part and an output buffer part. The transmission part comprises the transmission gate; the transmission control part comprises the NOR gate logic unit, the inverter and the transmission gate; the information storage part comprises the sequence inverter, the inverter; the output control part comprises the NAND gate logic unit, the inverter; the output buffer part comprises the inverter; the transmission gate is employed to perform the former-latter level transferring signal, and the NOR gate logic unit and the NAND gate logic unit are employed to convert the signals, and the sequence inverter and the inverter are employed to save and transmit the signals to solve the issues that the stability of the circuit is poor, and the power consumption is larger as concerning the LTPS with single type TFT elements, and the problem of TFT leakage of the single type GOA circuit to optimize the performance of the circuit; by setting the second output control part and the second output buffer part to realize sharing the driving output end to make the single stage GOA unit control two stage circuits forward scan output, the amount of the TFTs can be reduced to realize the ultra narrow frame or frameless designs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For better explaining the technical solution and the effect of the present invention, the present invention will be further described in detail with the accompanying drawings in the specific embodiments. 
       In drawings, 
         FIG. 1  is a circuit diagram of a GOA circuit of LTPS semiconductor TFT according to the first embodiment of the present invention; 
         FIG. 2  is a circuit diagram of the first stage connection of the GOA circuit of LTPS semiconductor TFT according to the first embodiment of the present invention; 
         FIG. 3  is a circuit diagram of the last stage connection of the GOA circuit of LTPS semiconductor TFT according to the first embodiment of the present invention; 
         FIG. 4  is a circuit diagram of a GOA circuit of LTPS semiconductor TFT according to the second embodiment of the present invention; 
         FIG. 5  is a waveform diagram of the key nodes in the GOA circuit of LTPS semiconductor TFT according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     For better explaining the technical solution and the effect of the present invention, the present invention will be further described in detail with the accompanying drawings and the specific embodiments. 
     Please refer to  FIG. 1 , which is a circuit diagram of a GOA circuit of LTPS semiconductor TFT according to the first embodiment of the present invention. As shown in  FIG. 1 , the GOA circuit of LTPS semiconductor TFT, employed for forward scan transmission comprises a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit utilizes a plurality of N-type transistors and a plurality of P-type transistors and comprises a transmission part  100 , a transmission control part  200 , an information storage part  300 , a data erase part  400 , an output control part  500  and an output buffer part  600 ; 
     the transmission part  100  is electrically coupled to a first low frequency signal UD, a second low frequency signal DU, a driving output end ST(N−1) of an N−1th GOA unit which is the former stage of the Nth GOA unit and the information storage part  300 ; the transmission control part  200  is electrically coupled to a driving output end ST(N+1) of an N+1th GOA unit which is the latter stage of the Nth GOA unit, the driving output end ST(N−1) of the N−1th GOA unit which is the former stage of the Nth GOA unit, an M−2th sequence signal CK(M−2), a high voltage source H, a low voltage source L and the information storage part  300 ; the information storage part  300  is electrically coupled to the transmission part  100 , the transmission control part  200 , the data erase part  400 , the high voltage source H and the low voltage source L; the data erase part  400  is electrically coupled to the information storage part  300 , the output control part  500 , the high voltage source H and the reset signal end Reset; the output control part  500  is electrically coupled to the data erase part  400 , the output buffer part  600 , a driving output end ST(N), a sequence signal CK(M), the high voltage source H and the low voltage source L; the output buffer part  600  is electrically coupled to the output control part  500 , an output end G(N), the high voltage source H and the low voltage source L; 
     the first low frequency signal UD is equivalent to a direct current high voltage level, and the second low frequency signal DU is equivalent to a direct current low voltage level; 
     the transmission part comprises  100  a first P-type transistor T 1 , and a gate of the first P-type transistor T 1  is electrically coupled to the second low frequency signal DU, and a source is electrically coupled to the driving output end ST(N−1) of the N−1th GOA unit which is the former stage of the Nth GOA unit, and a drain is electrically coupled to a first node P(N); a second N-type transistor T 2 , and a gate of the second N-type transistor T 2  is electrically coupled to the first low frequency signal UD, and a source is electrically coupled to the driving output end ST(N−1) of the N−1th GOA unit which is the former stage of the Nth GOA unit, and a drain is electrically coupled to the first node P(N); 
     the first P-type transistor T 1  and the second N-type transistor T 2  construct a transmission gate, employed to forward transmit a driving output signal ST(N−1) of the N−1th GOA unit to the information storage part  300 . 
     The transmission control part  200  comprises: a fifth P-type transistor T 5 , and a gate of the fifth P-type transistor T 5  is electrically coupled to the driving output end ST(N−1) of the N−1th GOA unit which is the former stage of the Nth GOA unit, and the source is electrically coupled to the high voltage source H, and a drain is electrically coupled to a source of a sixth P-type transistor T 6 ; the sixth P-type transistor T 6 , and a gate of the sixth P-type transistor T 6  is electrically coupled to the driving output end ST(N+1) of the N−1th GOA unit which is the latter stage of the Nth GOA unit, and a source is electrically coupled to the drain of the fifth P-type transistor T 5 , and a drain is electrically coupled to a source of a seventh N-type transistor T 7 ; the seventh N-type transistor T 7 , and a gate of the seventh N-type transistor T 7  is electrically coupled to the driving output end ST(N−1) of the N−1th GOA unit which is the former stage of the Nth GOA unit, and a source is electrically coupled to the drain of the sixth P-type transistor T 6 , and a drain is electrically coupled to the low voltage source L; an eighth N-type transistor T 8 , and the gate of the eighth N-type transistor T 8  is electrically coupled to the driving output end ST(N+1) of the N+1th GOA unit which is the latter stage of the Nth GOA unit, and the source is electrically coupled to the drain of the sixth P-type transistor T 6 , and a drain is electrically coupled to the low voltage source L; a ninth P-type transistor T 9 , and a gate of the ninth P-type transistor T 9  is electrically coupled to the drain of the sixth P-type transistor T 6 , and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to a source of a tenth N-type transistor T 10 ; the tenth N-type transistor T 10 , and a gate of the tenth N-type transistor T 10  is electrically coupled to the drain of the sixth P-type transistor T 6 , and the source is electrically coupled to the drain of the ninth P-type transistor T 9 , and a drain is electrically coupled to the low voltage source L; an eleventh P-type transistor T 11 , a gate of the eleventh P-type transistor T 11  is electrically coupled to the drain of the sixth P-type transistor T 6 , and a source is electrically coupled to a source of a twelfth N-type transistor T 12 , and a drain is electrically coupled to the M−2th sequence signal CK(M−2); the twelfth N-type transistor T 12 , and a gate of the twelfth N-type transistor T 12  is electrically coupled to the drain of the ninth P-type transistor T 9 , and the source is electrically coupled to the source of the eleventh P-type transistor T 11 , and a drain is electrically coupled to the M−2th sequence signal CK(M−2); 
     the fifth P-type transistor T 5 , the sixth P-type transistor T 6 , the seventh N-type transistor T 7 , the eighth N-type transistor T 8 , construct a NOR gate logic unit; the ninth P-type transistor T 9 , the tenth N-type transistor T 10  construct an inverter; the eleventh P-type transistor T 11 , the twelfth N-type transistor T 12  construct a transmission gate; the transmission control part  200  is employed to control the M−2th sequence signal CK(M−2) and transmits it to the information storage part  300 . 
     The information storage part  300  comprises a thirteenth N-type transistor T 13 , and a gate of the thirteenth N-type transistor T 13  is electrically coupled to the source of the eleventh P-type transistor T 11 , and a source is electrically coupled to a drain of a fourteenth P-type transistor T 14 , and a drain is electrically coupled to the low voltage source L; the fourteenth P-type transistor T 14 , and a gate of the fourteenth P-type transistor T 14  is electrically coupled to the source of the eleventh P-type transistor T 11 , and a source is electrically coupled to the high voltage source H, and the drain is electrically coupled to the source of the thirteenth N-type transistor T 13 ; a fifteenth P-type transistor T 15 , and a gate of the fifteenth P-type transistor T 15  is electrically coupled to the source of the thirteenth N-type transistor T 13 , and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to a source of a sixteenth P-type transistor T 16 ; the sixteenth P-type transistor T 16 , and a gate of the sixteenth P-type transistor T 16  is electrically coupled to the first node P(N), and the source is electrically coupled to the drain of the fifteenth P-type transistor T 15 , and a drain is electrically coupled to a source of a seventeenth N-type transistor T 17 ; the seventeenth N-type transistor T 17 , and a gate of the sixteenth P-type transistor T 17  is electrically coupled to the first node P(N), and the source is electrically coupled to the drain of the sixteenth P-type transistor T 16 , and a drain is electrically coupled to a source of an eighteenth N-type transistor T 18 ; the eighteenth N-type transistor T 18 , and a gate of the sixteenth P-type transistor T 18  is electrically coupled to the source of the eleventh P-type transistor T 11 , and the source is electrically coupled to the drain of the seventeenth N-type transistor T 17 , and a drain is electrically coupled to the low voltage source L; 
     the fifteenth P-type transistor T 15 , the sixteenth P-type transistor T 16 , the seventeenth N-type transistor T 17 , the eighteenth N-type transistor T 18  construct a sequence inverter; the thirteenth N-type transistor T 13 , the fourteenth P-type transistor T 14  construct an inverter; the information storage part  300  is employed to save and transmit the signals from the driving output end ST(N−1) of the N−1th GOA unit and the M−2th sequence signal CK(M−2). 
     The data erase part  400  comprises a twenty-third P-type transistor T 23 , and a gate of the twenty-third P-type transistor T 23  is electrically coupled to the reset signal end Reset, and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to the drain of the sixteenth P-type transistor T 16 ; the data erase part  400  is employed to erase the voltage level of the driving output end ST(N) of the circuit in due time. Mainly, the reset signal end Reset receives a pulse reset signal to discharge the driving output end ST(N), and accordingly to erase the voltage level of the driving output end ST(N) at the start of the every frame. 
     the output control part  500  comprises a twenty-fourth P-type transistor T 24 , and a gate of the twenty-fourth P-type transistor T 24  is electrically coupled to the drain of the sixteenth P-type transistor T 16 , and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to the driving output end ST(N); a twenty-fifth N-type transistor T 25 , and a gate of the twenty-fifth N-type transistor T 25  is electrically coupled to the drain of the sixteenth P-type transistor T 16 , and a source is electrically coupled to the driving output end ST(N), and a drain is electrically coupled to the low voltage source L; a twenty-sixth P-type transistor T 26 , and a gate of the twenty-sixth P-type transistor T 26  is electrically coupled to the driving output end ST(N), and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to a source of a twenty-ninth N-type transistor T 29 ; a twenty-seventh N-type transistor T 27 , and a gate of the twenty-seventh N-type transistor T 27  is electrically coupled to the driving output end ST(N), and a source is electrically coupled to a drain of the twenty-ninth N-type transistor T 29 , and a drain is electrically coupled to the low voltage source L; a twenty-eighth P-type transistor T 28 , and a gate of the sixteenth P-type transistor is electrically coupled to the sequence signal CK(M), and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to the source of the twenty-ninth N-type transistor T 29 ; the twenty-ninth N-type transistor T 29 , and a gate of the twenty-ninth N-type transistor T 29  is electrically coupled to the sequence signal CK(M), and the source is electrically coupled to the drain of twenty-sixth P-type transistor T 26 , and a drain is electrically coupled to the source of the twenty-seventh N-type transistor T 27 ; 
     the twenty-sixth P-type transistor T 26 , the twenty-seventh N-type transistor T 27 , the twenty-eighth P-type transistor T 28  and the twenty-ninth N-type T 29  construct a NAND gate logic unit; the twenty-fourth P-type transistor T 24 , twenty-fifth N-type transistor T 25  construct an inverter; the output control part  500  is employed to control a scan signal outputted by the output end G(N) to output the scan signal according with time sequence. 
     The output buffer part  600  comprises a thirtieth P-type transistor T 30 , and a gate of the thirtieth P-type transistor T 30  is electrically coupled to the source of the twenty-ninth N-type transistor T 29 , and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to a source of a thirty-first N-type transistor T 31 ; the thirty-first N-type transistor T 31 , and a gate of the thirty-first N-type transistor T 31  is electrically coupled to the source of the twenty-ninth N-type transistor T 29 , and the source is electrically coupled to the drain of the thirtieth P-type transistor T 30 , and a drain is electrically coupled to the low voltage source L; a thirty-second P-type transistor T 32 , and a gate of the thirty-second P-type transistor T 32  is electrically coupled to the drain of the thirtieth P-type transistor T 30 , and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to a source of a thirty-third N-type transistor T 33 ; the thirty-third N-type transistor T 33 , and a gate of the thirty-third N-type transistor T 33  is electrically coupled to the drain of the thirtieth P-type transistor T 30 , and the source is electrically coupled to the drain of the thirty-second P-type transistor T 32 , and a drain is electrically coupled to the low voltage source L; a thirty-fourth P-type transistor T 34 , and a gate of the thirty-fourth P-type transistor T 34  is electrically coupled to the drain of the thirty-second P-type transistor T 32 , and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to the output end G(N); a thirty-fifth N-type transistor T 35 , and a gate of the thirty-fifth N-type transistor T 35  is electrically coupled to the drain of the thirty-second P-type transistor T 32 , and a source is electrically coupled to the output end G(N), and a drain is electrically coupled to the low voltage source L. 
     The thirtieth P-type transistor T 30  and the thirty-first N-type transistor T 31 , the thirty-second P-type transistor T 32  and the thirty-third N-type transistor T 33 , the thirty-fourth P-type transistor T 34  and thirty-fifth N-type transistor T 35  respectively construct three inverters, employed to adjust the scan signal with a done sequence adjustment, and meanwhile, to strengthen a band loading capacity. 
     As shown in  FIGS. 2-3 , in the first stage connection of the GOA circuit of LTPS semiconductor TFT, all the source of the first P-type transistor T 1 , the source of the second N-type transistor T 2 , the gate of the fifth P-type transistor T 5 , the gate of the seventh N-type transistor T 7  are electrically coupled to an activation signal end STV of the circuit; in the last stage connection, both the gate of the sixth P-type transistor T 6  and the gate of the eighth N-type transistor T 8  are electrically coupled to the activation signal end STV of the circuit. 
     Please refer to  FIG. 5 , which is a waveform diagram of the key nodes in the GOA circuit of LTPS semiconductor TFT according to the present invention. As shown in  FIG. 5 , the waveforms of the respective key nodes satisfy the demands of design. The first low frequency signal UD and the second low frequency signal DU are equivalent to direct current high and low voltage levels as forward scan; the sequence signal CK(M) comprises four sets of sequence signals, which respectively are a first sequence signal CK(1), a second sequence signal CK(2), a third sequence signal CK(3), a fourth sequence signal CK(4), and the M−2th sequence signal CK(M−2) is the third sequence signal CK(3) when the sequence signal CK(M) is the first sequence signal CK(1), and the M−2th sequence signal CK(M−2) is the fourth sequence signal CK(4) when the sequence signal CK(M) is the second sequence signal CK(2), and the M+1th sequence signal CK(M+1) is the first sequence signal CK(1) when the sequence signal CK(M) is the fourth sequence signal CK(4). The pulse signals of the sequence signal CK(M) arrive in sequence of CK(1)-CK(4). The third sequence signal CK(3) corresponds to the output signal of the first stage output end G(1). The fourth sequence signal CK(4) corresponds to the output signal of the second stage output end G(2), and the first sequence signal CK(1) corresponds to the output signal of the third stage output end G(3), and the second sequence signal CK(2) corresponds to the output signal of the fourth stage output end G(4), and so on. 
     Please refer to  FIG. 4 , which is a circuit diagram of a GOA circuit of LTPS semiconductor TFT according to the second embodiment of the present invention. As shown in  FIG. 4 , the difference of the second embodiment from the first embodiment is, the GOA circuit further comprises a second output control part  501 , a second output buffer part  601 . The second output control part  501  is electrically coupled to the output control part  500 , the driving output end ST(N), an M+1th sequence signal CK(M+1), the high voltage source H and the low voltage source L; the second output buffer part  601  is electrically coupled to the second output control part  501 , an output end G(N+1) of the N+1th GOA unit, the high voltage source H and the low voltage source L. 
     the second output control part  501  comprises a thirty-sixth P-type transistor T 36 , and a gate of the thirty-sixth P-type transistor T 36  is electrically coupled to the driving output end ST(N), and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to a source of a thirty-ninth N-type transistor T 39 ; a thirty-seventh N-type transistor T 37 , and a gate of the thirty-seventh N-type transistor T 37  is electrically coupled to the driving output end ST(N), and a source is electrically coupled to the drain of the thirty-ninth N-type transistor T 39 , and a drain is electrically coupled to the low voltage source L; a thirty-eighth P-type transistor T 38 , and a gate of the thirty-eighth P-type transistor T 38  is electrically coupled to an M+1th sequence signal CK(M+1), and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to the source of the thirty-ninth N-type transistor T 39 ; the thirty-ninth N-type transistor T 39 , and a gate of the thirty-ninth N-type transistor T 39  is electrically coupled to the M+1th sequence signal CK(M+1), and the source is electrically coupled to the drain of the thirty-sixth P-type transistor T 36 , and the drain is electrically coupled to the source of the thirty-seventh N-type transistor T 37 ; 
     the second output buffer part  601  comprises a fortieth P-type transistor T 40 , and a gate of the fortieth P-type transistor T 40  is electrically coupled to the source of the thirty-ninth N-type transistor T 39 , and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to a source of a forty-first N-type transistor T 41 ; the forty-first N-type transistor T 41 , and a gate of the forty-first N-type transistor T 41  is electrically coupled to the source of the thirty-ninth N-type transistor T 39 , and the source is electrically coupled to the drain of the fortieth P-type transistor T 40 , and a drain is electrically coupled to the low voltage source L; a forty-second P-type transistor T 42 , and a gate of the forty-second P-type transistor T 42  is electrically coupled to the drain of the fortieth P-type transistor T 40 , and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to a source of a forty-third N-type transistor T 43 ; the forty-third N-type transistor T 43 , and a gate of the forty-third N-type transistor T 43  is electrically coupled to the drain of the fortieth P-type transistor T 40 , and the source is electrically coupled to the drain of the forty-second P-type transistor T 42 , and a drain is electrically coupled to the low voltage source L; a forty-fourth P-type transistor T 44 , and a gate of the forty-fourth P-type transistor T 44  is electrically coupled to the drain of the forty-second P-type transistor T 42 , and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to an output end G(N+1) of the N+1th GOA unit; a forty-fifth N-type transistor T 45 , and a gate of the forty-fifth N-type transistor T 45  is electrically coupled to the drain of the forty-second P-type transistor T 42 , and a source is electrically coupled to the output end G(N+1) of the N+1th GOA unit, and a drain is electrically coupled to the low voltage source L. 
     In the second output control part  501 , the thirty-sixth P-type transistor T 36 , the thirty-seventh N-type transistor T 37 , the thirty-eighth P-type transistor T 38 , the thirty-ninth N-type transistor T 39  construct a NAND gate logic unit, employed to control the scan signal outputted by the output end G(N+1) of the N+1th GOA unit to output the scan signal according with time sequence; in the second output buffer part  601 , the fortieth P-type transistor T 40  and the forty-first N-type transistor T 41 , the forty-second P-type transistor T 42  and the forty-third N-type transistor T 43 , the forty-fourth P-type transistor T 44  and the forty-fifth N-type transistor T 45  respectively construct three inverters, employed to adjust the scan signal with a done sequence adjustment, and meanwhile, to strengthen a band loading capacity; the second output control part  501  and the second output buffer part  601  output a scan signal of the latter stage from the output end G(N+1) of the N+1th GOA unit according to the outputted signal of the driving output end ST(N) and the M+1th sequence signal CK(M+1) to realize that the single stage GOA unit controls two stage circuits forward scan output. 
     By adding the second output control part  501 , the second output buffer part  601 , the effect that the single stage GOA unit controls two stage circuits forward scan output can be realized. Meanwhile, the second output control part  501  and the second output buffer part  601  share one driving output end ST(N). The amount of the TFTs can be reduced and realize the ultra narrow frame or frameless designs by sharing the driving output end ST(N). 
     In conclusion, the GOA circuit of LTPS semiconductor TFT according to the present invention is employed for forward scan transmission. The Nth GOA unit utilizes a plurality of N-type transistors and a plurality of P-type transistors, comprising a transmission part, a transmission control part, an information storage part, a data erase part, an output control part and an output buffer part. The transmission part comprises the transmission gate; the transmission control part comprises the NOR gate logic unit, the inverter and the transmission gate; the information storage part comprises the sequence inverter, the inverter; the output control part comprises the NAND gate logic unit, the inverter; the output buffer part comprises the inverter; the transmission gate is employed to perform the former-latter level transferring signal, and the NOR gate logic unit and the NAND gate logic unit are employed to convert the signals, and the sequence inverter and the inverter are employed to save and transmit the signals to solve the issues that the stability of the circuit is poor, and the power consumption is larger as concerning the LTPS with single type TFT elements, and the problem of TFT leakage of the single type GOA circuit to optimize the performance of the circuit; by setting the second output control part and the second output buffer part to realize sharing the driving output end to make the single stage GOA unit control two stage circuits forward scan output, the amount of the TFTs can be reduced to realize the ultra narrow frame or frameless designs. 
     Above are only specific embodiments of the present invention, the scope of the present invention is not limited to this, and to any persons who are skilled in the art, change or replacement which is easily derived should be covered by the protected scope of the invention. Thus, the protected scope of the invention should go by the subject claims.