Patent Publication Number: US-6664905-B1

Title: Device for encoding n-bit source words into corresponding m-bit channel words and decoding m-bit channel words into corresponding n-bit source words

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This is a continuation of application Ser. No. 10/102,358, filed Mar. 20, 2002, now U.S. Pat. No. 6,535,151 which issued Oct. 22, 2002, which is a continuation of application Ser. No. 10/016,168, filed Dec. 10, 2001, now abandoned which is a continuation of application Ser. No. 09/460,940, filed Dec. 14, 1999, U.S. Pat. No. 6,356,215. 
    
    
     The invention relates to a device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal, wherein the stream of databits of the source signal is divided into n-bit source words, which device comprises converting means conceived to convert said n-bit source words into corresponding m-bit channel words in accordance with a conversion of the Jacoby type, where m and n are integers, with m&gt;n. 
     The invention also relates to a method of encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal, wherein the stream of databits of the source signal is divided into n-bit source words, said source words being converted into corresponding m-bit channel words in accordance with a conversion of the Jacoby type, where m and n are integers, with m&gt;n. 
     The invention further relates to a binary channel signal comprising a stream of databits, converted from a binary source signal comprising a stream of databits, wherein the stream of databits of the source signal comprises n-bit source words, the channel signal comprising m-bit channel words, each one of said m-bit channel words corresponding to one of said n-bit source words in accordance with a conversion of the Jacoby type, where m and n are integers, with m&gt;n. 
     The invention further relates to a record carrier comprising a binary channel signal comprising a stream of databits, converted from a binary source signal comprising a stream of databits, wherein the stream of databits of the source signal comprises n-bit source words, the channel signal comprising m-bit channel words, each one of said m-bit channel words corresponding to one of said n-bit source words in accordance with a conversion of the Jacoby type, where m and n are integers, with m&gt;n. 
     The invention further relates to a device for decoding a stream of databits of a binary channel signal into a stream of databits of a binary source signal, wherein the stream of databits of the channel signal is divided into m-bit channel words, which device comprises deconverting means conceived to deconvert said m-bit channel words into corresponding n-bit source words in accordance with a deconversion of the Jacoby type, where m and n are integers, with m&gt;n. 
     An encoding device and a decoding device mentioned in the foregoing are known from U.S. Pat. No. 4,337,458 (Jacoby channel code). The document discloses a device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal, satisfying a ( 1 , 7 ) runlength constraint. This means that, in a serial datastream of the channel signal, minimally one ‘zero’ and maximally seven ‘zeroes’ are present between two consecutive ‘ones’ in the channel signal. In this respect it should be noted that, normally, an additional preceding step is applied to the ( 1 , 7 ) constrained sequence, resulting in a runlength-limited sequence with a minimum runlength of  2  and a maximum runlength of  8 . 
     The Jacoby channel code as such allows no DC-control at all. All conversions from source bits to channel bits are unambiguous. DC-control implies the reduction of the power of the channel bit stream near zero frequency. The spectral notch at DC allows retrieval of the threshold level from the detected waveform, which is essential for timing-recovery with the PLL. 
     It is an object of the invention to provide an improved device for encoding n-bit source words into corresponding m-bit channel words in accordance with a conversion of the Jacoby type, so that DC-control is made possible. 
     The encoding device in accordance with the invention is characterized in that the device further comprises control means for carrying out DC-control on said binary channel signal by introducing a freedom of choice in the source-to-channel conversion. 
     The invention is based on the recognition that DC-control will be made possible by introducing an appropriate freedom of choice in the source-to-channel conversion. Therefore, two options in the choice for some predetermined source-to-channel conversions are created. Both options are different in one extra ‘1’ in the channel stream of databits in NRZI-notation, so the difference is one extra transition in the channel stream of databits, which has the effect of transforming the pit-bits into land bits (or marks and non-marks in the case of phase change recording) and vice versa after the extra transition. Due to this extra transition, the so-called running-digital sum (RDS) value can be kept within certain bounds, which is a sufficient condition for the generation of a spectral notch at DC. This kind of DC-control will be referred to as stochastic DC-control. The RDS gives a measure of the low-frequency content as it is defined as the difference between the totals of pit and land lengths in the channel stream of databits. 
     In the parity preserve channel code, e.g. described in U.S. Pat. No. 5,477,222 (PHN 14448), DC-control is also performed by limiting the RDS within certain bounds. The main difference with the parity preserve principle is that the latter needs extra bits, the so-called parity preserve bits, before the channel encoding operation in order to control the RDS value. In this invention, no extra bits are needed, since the bits that allow control of the RDS value are implicitly present in the source-to-channel conversion with double options. The frequency of occurrence of these DC-control points in the channel bitstream depends on the actual content of the source bitstream, which makes the type of DC-control in this invention to be of a stochastical nature. This invention has as an advantage that the capacity of a record carrier can be enlarged. 
     The encoding device in accordance with the invention is characterized in that the device further comprises bit-adding means for carrying out additional DC-control. 
     The encoding device in accordance with the invention is suitable to be included in the encoding arrangement, where merging bits are inserted after every q bits in a serial channel bitstream in order to realize an extra DC-control. This may be suitable if the stochastic DC-control as introduced before is regarded to be insufficient. 
     The purpose of the bit-adding means is to add bits to the channel bitstream, so as to obtain a precoder output signal in which the power of the channel bitstream near zero frequency is further reduced, improving the DC-control. The added bits that are present in the channel bitstream are usually referred to as merging bits. The precoder output signal is recorded on a record carrier. The addition of an n-bit code word to the consecutive code words allows a change of the sign of the RDS contribution. 
     The method in accordance with the invention is characterized in that the method further carries out DC-control on the binary channel signal by introducing a freedom of choice in the source-to-channel conversion. 
     The signal in accordance with the invention is characterized in that, in said binary channel signal, a pair of blocks of p consecutive m-bit channel words, being converted from the same block of p consecutive n-bit source words, is present, the blocks of the pair differing from each other in the bit value at one bit position only in said blocks, p being an integer which is larger than 1. 
     The record carrier in accordance with the invention is characterized in that, in said binary channel signal, a pair of blocks of p consecutive m-bit channel words, being converted from the same block of p consecutive n-bit source words, is present, the blocks of the pair differing from each other in the bit value at one bit position only in said blocks, p being an integer which is larger than 1. 
     The decoding device in accordance with the invention is characterized in that said deconverting means are also conceived to deconvert a channel sequence comprising pairs of blocks of p consecutive m-bit channel words into the same blocks of p consecutive n-bit source words, the pairs of blocks of p consecutive m-bit channel words differing from each other in the bit value at one bit position only in said blocks, p being an integer which is larger than 1. 
     With this device, the binary data signal according to the invention, comprising a stream of databits, can be deconverted into a binary source signal comprising a stream of databits. 
    
    
     The invention will be further described in the following Figure description in which 
     FIG. 1 shows a first embodiment of the encoding device, 
     FIG. 2 shows a second embodiment of the encoding device, 
     FIG. 3 shows an example of the way in which the value of the RDS can be controlled by inserting merging bits in the channel bitstream, 
     FIG. 4 shows an arrangement for precoding the serial channel signal and recording the precoded signal on a record carrier, 
     FIG. 5 shows a first embodiment of the decoding device, and 
     FIG. 6 shows a second embodiment of the decoding device. 
    
    
     FIG. 1 shows an encoding device that is capable of converting 2-bit source words into 3-bit channel words. The device has an input terminal  1  for receiving a stream of databits of a binary source signal S. The terminal  1  is coupled to an input of a shift register  2  having six cells X 1  to X 6 , in the present example, so as to receive six consecutive source bits of the source signal S. The shift register  2  functions as a serial-parallel converter. The outputs of the cells are coupled to corresponding inputs i 1  to i 6 , respectively, of a logic circuit LC, for supplying the logic values (x 1 , . . . ,x 6 ) of the source bits present in the cells. The logic circuit LC forms part of the converting means CM. 
     The device further includes a second shift register  4  having nine cells Y 1 , to Y 9 . The logic circuit LC has nine outputs o 1  to o 9 . These outputs of the logic circuit LC are coupled to corresponding inputs of the nine cells Y 1  to Y 9 , respectively, of the shift register  4 . An output  6  of the shift register  4  is coupled to an output terminal  8 . The shift register  4  functions as a parallel-serial converter, so as to obtain the binary channel signal C. 
     Furthermore, a detector unit  10  is available for detecting specific sequences in the serial datastream of the source signal S. To this end, the outputs of the six cells X 1  to X 6  of the shift register  2  are coupled to corresponding inputs, denoted  12 , of the detector unit  10 . In the present embodiment, the detector unit  10  has two outputs, denoted O 1  and O 2 , for generating a first and a second control signal, respectively. These outputs are coupled to corresponding control signal inputs c 1  and c 2 , respectively, of the logic circuit LC. 
     The logic circuit LC functions as follows in response to the control signals applied to its inputs c 1  and c 2 . The logic circuit LC is capable of converting 2-bit source words SW into 3-bit channel words. As an example, the converting means LC is adapted to convert the 2-bit source words SW into 3-bit channel words CW in accordance with the following Table 1: 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 source word 
                 channel word 
               
               
                   
                   
               
             
            
               
                   
                 00 
                 101 
               
               
                   
                 01 
                 100 
               
               
                   
                 10 
                 001 
               
               
                   
                 11 
                 010 
               
               
                   
                   
               
            
           
         
       
     
     It should be noted here that the first bit in the source word is applied first to the shift register  2  and that the first bit in the channel word is supplied first from the output  6  of the shift register  4 . 
     It should be further noted here that the logic circuit LC converts 2-bit source words stored in the cells X 1 ,X 2  into 3-bit channel words and stores these channel words in the cells Y 1 ,Y 2 ,Y 3  of the shift register  4 , in response to an absence of any control signal at the control signal inputs c 1  and c 2 . Each conversion in this way is followed by a shift over two positions to the left in the shift register  2 , and a shift over three positions to the left in the shift register  4 . The shift over two positions in the shift register  2  is required to prepare the shift register  2 , and thus the converter, for a subsequent conversion. The shift over three positions in the shift register  4  is required to output the generated 3-bit channel word. 
     The device of FIG. 1 can be used to generate a channel signal C in the form of a (d,k) sequence satisfying the d=1 constraint. This means that at least one ‘zero’ is present between two subsequent ‘ones’ in the serial datastream of the channel signal. That is, a concatenation of two or more ‘ones’ in the channel signal is prohibited. 
     The unmodified conversion, such as by means of the device of FIG. 1, of combinations of two subsequent 2-bit source words might violate the d=1 constraint. These combinations are the combinations ‘00 00’, which, by unmodified conversion, would lead to the two 3-bit channel words ‘101 101’; ‘00 01’, which, by unmodified conversion, would lead to the two 3-bit channel words ‘101 100’; ‘10 00’, which, by unmodified conversion, would lead to the two 3-bit channel words ‘001 101’ and ‘10 01’, which, by unmodified conversion, would lead to the two 3-bit channel words ‘001 100’. 
     The occurrence of such combinations should be detected so that a modified encoding of blocks of two 2-bit source words into blocks of two 3-bit channel words can take place. Therefore, in addition to the ‘normal’ encoding of 2-bit source words into 3-bit channel words, the device of FIG. 1 is capable of detecting the above identified combinations and of realizing a modified encoding, such that the d=1 constraint in the channel signal is still satisfied. 
     Since the outputs of the cells X 1  to X 4  of the shift register  2  are coupled to corresponding inputs of the detector unit  10 , this detector unit  10  is capable of detecting the position in the serial bitstream of the source signal, where unmodified encoding of single 2-bit source words in the bitstream into corresponding single 3-bit channel words would lead to a violation of the d=1 constraint in the channel signal C, and is adapted to supply a control signal at its output O 1  in response to such a detection. 
     More specifically, the detector unit  10  detects whether the cells X 1  to X 4  comprise one of the 4-bit sequences that are given in Table 2, and generates a first control signal at its output O 1 . As soon as the detector unit  10  detects a combination of two 2-bit source words present in the four cell positions x 1 ,x 2 ,x 3 ,x 4 , which combination equals one of the combinations given in the left-hand column of Table 2, the logic circuit LC converts the combination in accordance with the modified coding given in Table 2: 
     
       
         
           
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                 block of 2 
                 block of 2 channel words/ 
                 block of 2 channel words/ 
               
               
                 source words 
                 unmodified coding 
                 modified coding 
               
               
                   
               
             
            
               
                 00 00 
                 101 101 
                 101 000 
               
               
                 00 01 
                 101 100 
                 100 000 
               
               
                 10 00 
                 001 101 
                 001 000 
               
               
                 10 01 
                 001 100 
                 010 000 
               
               
                   
               
            
           
         
       
     
     As can be seen from the Table, unmodified conversion of the single two 2-bit source words leads to a violation of the d=1 constraint, as two ‘ones’ occur at the boundary between the two channel words obtained. The logic circuit LC is therefore adapted to convert, in a modified coding mode, the blocks of two 2-bit source words given in the left column of the above Table into the blocks of two 3-bit channel words given in the right column in Table 2. As can be seen, no violation of the d=1 constraint occurs anymore. Furthermore, one of the two 3-bit channel words is unequal to one of the four channel words of Table 1, namely the code word  000 . The reason for this is that, on the receiver side, a detection of this 3-bit channel word not belonging to the set of four 3-bit channel words of Table 1 is possible, so that a corresponding decoding, which is the inverse of the encoding as defined with reference to Table 2, can be realized. 
     The block of two 3-bit channel words, obtained by means of the encoding in conformity with Table 2, is supplied by the logic circuit LC to its outputs o 1  to o 6 , which channel words are supplied to the six cells Y 1  to Y 6  of the shift register 4. 
     It will further be clear that a conversion of two 2-bit source words into two 3-bit channel words by the converter unit LC is followed by a shift over four positions to the left in the shift register  2  and a shift over six positions to the left in the shift register  4 . The shift over four positions in the shift register  2  is required so as to prepare the shift register  2 , and thus the converter, for a subsequent conversion. The shift over six positions in the shift register  4  is required to output the two generated 3-bit channel words. 
     As mentioned hereinbefore, the detector unit  10  is available for detecting specific sequences in the serial datastream of the source signal S. In order to make DC-control possible, the absolute value of the running-digital sum (RDS) value must be limited. Therefore, the detector unit  10  detects whether the cells X 1  to X 6  comprise one of the 6-bit sequences that are given in Table 3, and generates a second control signal at its output O 2 . 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 3 
               
               
                   
                   
               
               
                   
                 block of 3 source words 
                 block of 3 channel words 
               
               
                   
                   
               
             
            
               
                   
                 00 00 01 
                 101 000 x00 
               
               
                   
                 00 01 01 
                 100 000 x00 
               
               
                   
                 10 00 01 
                 001 000 x00 
               
               
                   
                 10 01 01 
                 010 000 x00 
               
               
                   
                   
               
            
           
         
       
     
     As soon as the detector unit  10  detects a combination of three 2-bit source words present in the six cell positions x 1 ,x 2 ,x 3 ,x 4 ,x 5 ,x 6 , which combination equals one of the combinations given in the left-hand column of Table 3, the logic circuit LC converts the combination in accordance with the coding given in Table 3, where the bit marked ‘x’ is a DC-control bit and indicates that a choice can be made between the values ‘0’ and ‘1’, depending on the RDS value of the signal and the disparity of the channel bit sequence after DC-control bit ‘x’ up to the next DC-control bit ‘x’. 
     It should be noted that the bitstream of the channel words is in NRZI (non-return to zero-inverse) notation, which means that a ‘one’ results in a transition in the write current for recording the channel signal on a record carrier. This record carrier may be a magnetic record carrier or an optical record carrier but is not limited to these two types. 
     In another embodiment, the detector unit  10  detects whether the cells X 1  to X 6  comprise one of the 6-bit sequences that are given in Table 4, and generates a second control signal at its output O 2 . For the block of  3  source words, two possible positions for the DC-control bit ‘x’ are possible. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 4 
               
               
                   
                   
               
               
                   
                 block of 3 source words 
                 block of 3 channel words 
               
               
                   
                   
               
             
            
               
                   
                 00 00 11 
                 101 000 0x0 
               
               
                   
                 00 01 11 
                 100 000 0x0 
               
               
                   
                 10 00 11 
                 001 000 0x0 
               
               
                   
                 10 01 11 
                 010 000 0x0 
               
               
                   
                   
               
            
           
         
       
     
     As soon as the detector unit  10  detects a combination of three 2-bit source words present in the six cell positions x 1 ,x 2 ,x 3 ,x 4 ,x 5 ,x 6 , which combination equals one of the combinations given in the left-hand column of Table 4, the logic circuit LC again converts the combination in accordance with the coding given in Table 4, in order to control the DC-content of the signal which is present. 
     It is also obvious to those skilled in the art that, by making a mixture of Table 3 and Table 4, line after line, other tables suited for carrying out DC-control can be constructed. Moreover, it can be shown that one entry in Table 2 can be omitted (e.g. the 4 th  entry), so that it becomes possible to perform stochastic DC-control by creating a freedom of choice in the source-to-channel conversion (e.g. 11 11 being converted into 010 0×0) and by dealing with the d=1 violations due to the omission of one entry in Table 2 by means of the adapted entries of Table 3. In this way, stochastic DC-control can also be performed when a block of  2  consecutive n-bit source words is converted into a block of  2  consecutive m-bit channel words. 
     FIG. 2 shows another embodiment of the invention, requiring  4  instead of  3  encoding tables, with an encoding device that is capable of converting 2-bit source words into 3-bit channel words. The device has an input terminal  1  for receiving a stream of databits of a binary source signal S. The terminal  1  is coupled to an input of a shift register  14  having eight cells X 1  to X 8 , in the present example, so as to receive eight consecutive source bits of the source signal S. The shift register  14  functions as a serial-parallel converter. The outputs of the cells are coupled to corresponding inputs i 1  to i 8 , respectively, of a logic circuit LC, for supplying the logic values (x 1 , . . . ,x 8 ) of the source bits present in the cells. The logic circuit LC forms part of the converting means CM. 
     The device further includes a second shift register  20  having twelve cells Y 1  to Y 12 . The logic circuit LC has twelve outputs o 1  to o 12 . These outputs of the logic circuit LC are coupled to corresponding inputs of the twelve cells Y 1  to Y 12 , respectively, of the shift register  20 . An output  22  of the shift register  20  is coupled to an output terminal  24 . The shift register  4  functions as a parallel-serial converter, so as to obtain the binary channel signal C. 
     Furthermore, a detector unit  10  is available for detecting specific sequences in the serial datastream of the source signal S. To this end, the outputs of the eight cells X 1  to X 8  of the shift register  2  are coupled to corresponding inputs, denoted  12 , of the detector unit  10 . In the present embodiment, the detector unit  10  has three outputs (for Table 2, Table 3 and Table 4), denoted O 1 , O 2  and O 3 , for generating a first, a second and a third control signal, respectively. These outputs are coupled to corresponding control signal inputs c 1 , c 2  and c 3 , respectively, of the logic circuit LC. A description of the further functioning of this device can be found in the description of FIG.  1 . 
     As mentioned hereinbefore, the detector unit  10  is available for detecting specific sequences in the serial datastream of the source signal S. In order to make DC-control possible, the running-digital sum (RDS) value must be held within certain bounds. This detector unit is able to detect the same specific sequences as the detector present in the encoding device as described in FIG.  1  and in Tables 1, 2, 3 and 4. In addition, the detector unit  10  detects whether the cells X 1  to X 8  comprise one of the 8-bit sequences that are given in Table 5, and generates a third control signal at its output O 3 . 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 5 
               
               
                   
                   
               
               
                   
                 block of 4 source words 
                 block of 4 channel words 
               
               
                   
                   
               
             
            
               
                   
                 00 00 10 01 
                 101 000 0x0 000 
               
               
                   
                 00 01 10 01 
                 100 000 0x0 000 
               
               
                   
                 10 00 10 01 
                 001 000 0x0 000 
               
               
                   
                 10 01 10 01 
                 010 000 0x0 000 
               
               
                   
                   
               
            
           
         
       
     
     As soon as the detector unit  10  detects a combination of four 2-bit source words present in the eight cell positions x 1 ,x 2 ,x 3 ,x 4 ,x 5 ,x 6 ,x 7 ,x 8 , which combination equals one of the combinations given in the left-hand column of Table 5, the logic circuit LC converts the combination in accordance with the coding given in Table 5, where the bit marked ‘x’ indicates that a choice can be made between the values ‘0’ and ‘1’, depending on the RDS value of the signal at that moment. 
     In another embodiment, the detector unit  10  detects whether the cells X 1  to X 8  comprise one of the 8-bit sequences that are given in Table 6, and generates a third control signal at its output O 3 . For the block of 4 source words, three possible positions for the DC-control bit ‘x’ are possible. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 6 
               
               
                   
                   
               
               
                   
                 block of 4 source words 
                 block of 4 channel words 
               
               
                   
                   
               
             
            
               
                   
                 00 00 00 01 
                 101 000 x00 000 
               
               
                   
                 00 01 00 01 
                 100 000 x00 000 
               
               
                   
                 10 00 00 01 
                 001 000 x00 000 
               
               
                   
                 10 01 00 01 
                 010 000 x00 000 
               
               
                   
                   
               
            
           
         
       
     
     As soon as the detector unit  10  detects a combination of four 2-bit source words present in the eight cell positions x 1 ,x 2 ,x 3 ,x 4 ,x 5 ,x 6 ,x 7 ,x 8 , which combination equals one of the combinations given in the left-hand column of Table 6, the logic circuit LC again converts the combination in accordance with the coding given in Table 6, in order to control the DC-content of the signal which is present. 
     In another embodiment, the detector unit  10  detects whether the cells X 1  to X 8  comprise one of the 8-bit sequences that are given in Table 7, and generates a third control signal at its output O 3 . 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 7 
               
               
                   
                   
               
               
                   
                 block of 4 source words 
                 block of 4 channel words 
               
               
                   
                   
               
             
            
               
                   
                 00 00 10 00 
                 101 000 00x 000 
               
               
                   
                 00 01 10 00 
                 100 000 00x 000 
               
               
                   
                 10 00 10 00 
                 001 000 00x 000 
               
               
                   
                 10 01 10 00 
                 010 000 00x 000 
               
               
                   
                   
               
            
           
         
       
     
     As soon as the detector unit  10  detects a combination of four 2-bit source words present in the eight cell positions x 1 ,x 2 ,x 3 ,x 4 ,x 5 ,x 6 ,x 7 ,x 8 , which combination equals one of the combinations given in the left-hand column of Table 7, the logic circuit LC again converts the combination in accordance with the coding as given in Table 7, in order to control the DC-content of the signal which is present. 
     It is also obvious to those skilled in the art that, by making a mixture of Table 5, Table 6 and Table 7, line after line, other tables, each with a maximum of 4 lines, suited for carrying out DC-control can be constructed. 
     As stated before, the devices described above are suitable to be included in the encoding arrangement, where merging bits are inserted after every q bits in a serial channel bitstream in order to realize an extra DC-control. This may be suitable if the stochastic DC-control as introduced before is regarded to be insufficient, depending on the envisaged specific application. 
     FIG. 3 shows an example of the way in which the value of the RDS can be controlled by inserting merging bits in the channel bitstream. At a certain position in the channel bitstream  26 , the RDS has a certain value RDS 1 . Two merging bits x and y are then inserted in the bitstream in order to control the value of the RDS. Because the Jacoby code has a d=1 constraint, a choice must be made between the merging bits ‘00’, on the one hand, and ‘01’ or ‘10’, on the other hand. The choice allows a change of the sign of the RDS contribution behind the merging bits. By means of the arrangement shown in FIG. 3, it is possible to keep the DC-content of the channel bitstream close to zero. 
     At a position in the channel bitstream  28 , q bits after position  26 , the resulting values RDS 2  are shown. It is clear from this example that, by observing the RDS 2  values, the proper choice at the position  26  can be made in order to control the DC-content of the channel signal. 
     The devices described above are very suitable to be included in the encoding arrangement, where two merging bits are inserted after every q bits in a serial channel bitstream in order to control the DC-content of the channel signal. FIG. 4 shows schematically such an arrangement for precoding the serial channel signal and recording the precoded signal on a record carrier. The source bitstream  30  is applied to an encoder  76 . The output signal of the encoder  76 , the channel bitstream  80 , is supplied to a (d+1)T merger  78  where (due to the fact that in this case d=1) two merging bits are added. The channel bitstream is then supplied to a precoder  32 . The output signal of the precoder is applied to a control signal generator  82 , which generates the control signal for the (d+1)T merger  78 , so as to control which merging bits are to be inserted in the channel bitstream  80  (see FIG.  3 ). The output signal of the precoder is supplied to a write unit  34  for writing the signal in a track on a record carrier  36 . The record carrier  36  may be a magnetic record carrier in a longitudinal or disk form. The record carrier may be alternatively an optical record carrier, such as an optical disk  36 ′. The write unit  34  comprises a write head  38 , which is a magnetic write head, when recording the signal on a magnetic record carrier, or an optical write head, when recording the signal on an optical record carrier. 
     FIG. 5 shows an embodiment of a decoding device for decoding the serial datastream obtained by the encoding device of FIG. 1, so as to obtain a binary source signal. The decoding device has an input terminal  40  for receiving the channel signal, which input terminal  40  is coupled to an input  42  of a shift register  44 , comprising nine cells Y 1  to Y 9 . The shift register  44  functions as a serial-parallel converter so that blocks of three 3-bit channel words are applied to inputs i 1  to i 9  of a logic circuit  50 . The logic circuit  50  comprises the Tables 1, 2 and 3 or the Tables 1, 2 and 4. Outputs o 1  to o 6  of the logic circuit  50  are coupled to inputs of cells X 1  to X 6  of a shift register  52 , which has an output  54  coupled to an output terminal  56 . A detector circuit  48  is present, having inputs i 1  to i 9 , schematically indicated by the reference numeral  60 , coupled to outputs of cells Y 1  to Y 9  respectively, of the shift register  44 , and outputs O 1  and O 2  coupled to control inputs c 1  and c 2 , respectively, of the logic circuit  50 . 
     In the absence of the control signals, the logic circuit  50  converts the 3-bit channel word stored in the cells Y 1 , Y 2  and Y 3  into its corresponding 2-bit source word, as per the conversion Table 1, and supplies the 2-bit source word to the cells X 1  and X 2 . In the presence of the control signal at the input c 1 , the logic circuit  50  converts the block of two 3-bit channel words stored in the cells Y 1  to Y 6  into a block of two 2-bit source words, as per the conversion Table 2, and supplies the two 2-bit source words to the cells X 1  to X 4 . In the presence of the control signal at the input c 2 , the logic circuit  50  converts the block of three 3-bit channel words stored in the cells Y 1  to Y 6  into a block of three 2-bit source words, as per the conversion Table 3 or conversion Table 4, and supplies the three 2-bit source words to the cells X 1  to X 6 . 
     In this way, the serial datastream of the channel signal is converted into the serial datastream of the source signal. 
     The encoded information supplied to the input  40  could have been obtained from reproducing the information from a record carrier, such as a magnetic record carrier  36  or an optical record carrier  36 ′. To this end, the device in FIG. 4 comprises a read unit  34  for reading the information from a track on the record carrier, where the unit  34  comprises a read/write head  38  for reading the information from said track and/or for writing the information on said track. 
     FIG. 6 shows an embodiment of a decoding device for decoding the serial datastream obtained by the encoding device of FIG. 2, so as to obtain a binary source signal. The decoding device has an input terminal  58  for receiving the channel signal, which input terminal  58  is coupled to an input  60  of a shift register  62 , comprising twelve cells Y 1  to Y 12 . The shift register  62  functions as a serial-parallel converter so that blocks of four 3-bit channel words are applied to inputs i 1  to i 12  of a logic circuit  64 . The logic circuit  64  comprises the Tables 1 and 2 and one of the Tables 3 or 4 and one of the Tables 5 or 6 or 7. Outputs o 1  to o 8  of the logic circuit  64  are coupled to inputs of cells X 1  to X 8  of a shift register  66 , which has an output  68  coupled to an output terminal  70 . A detector circuit  72  is present, having inputs i 1  to i 12 , schematically indicated by the reference numeral  74 , coupled to outputs of cells Y 1  to Y 12  respectively, of the shift register  62 , and outputs O 1 , O 2  and O 3  coupled to control inputs c 1 , c 2  and c 3 , respectively, of the logic circuit  64 . 
     In the absence of the control signals, the logic circuit  64  converts the 3-bit channel word stored in the cells Y 1 , Y 2  and Y 3  into its corresponding 2-bit source word, as per the conversion Table 1, and supplies the 2-bit source word to the cells X 1  and X 2 . In the presence of the control signal at the input c 1 , the logic circuit  64  converts the block of two 3-bit channel words stored in the cells Y 1  to Y 6  into a block of two 2-bit source words, as per the conversion Table 2, and supplies the two 2-bit source words to the cells X 1  to X 4 . In the presence of the control signal at the input c 2 , the logic circuit  64  converts the block of three 3-bit channel words stored in the cells Y 1  to Y 6  into a block of three 2-bit source words, as per the conversion Table 3 or conversion Table 4, and supplies the three 2-bit source words to the cells X 1  to X 6 . In the presence of the control signal at the input c 3 , the logic circuit  64  converts the block of four 3-bit channel words stored in the cells Y 1  to Y 12  into a block of four 2-bit source words, as per the conversion Table 5 or conversion Table 6 or conversion Table 7, and supplies the four 2-bit source words to the cells X 1  to X 8 . 
     In this way, the serial datastream of the channel signal is converted into the serial datastream of the source signal. 
     The encoded information supplied to the input  58  could have been obtained from reproducing the information from a record carrier, such as a magnetic record carrier  36  or an optical record carrier  36 ′. To this end, the device in FIG. 5 comprises a read unit  34  for reading the information from a track on the record carrier, where the unit  34  comprises a read/write head  38  for reading the information from said track and/or for writing the information on said track. 
     Whilst the invention has been described with reference to preferred embodiments, it is to be noted that these are non-limitative examples. Thus, various modifications may be apparent to those skilled in the art, without departing from the scope of the invention, as defined in the claims. 
     The invention also lies in each and every novel feature or combination of features.