Patent Publication Number: US-10311938-B2

Title: Compact system with memory and PMU integration

Description:
This application is a continuation of U.S. patent application Ser. No. 14/196,793, filed Mar. 4, 2014 and now U.S. Pat. No. 9,607,680, which is hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     Field of the Invention 
     Embodiments described herein are related to the field of integrated circuits and, more particularly, to integrating dynamic random access memory, fine-grain power management, and other logic onto an integrated circuit and/or into a module. 
     Description of the Related Art 
     Mobile electronic devices have become ubiquitous, and many people own several such devices. Mobile electronic devices can include, e.g., mobile phones (especially smart phones), personal digital assistants, tablet computers, laptop computers, net top computers, eReaders, etc. Mobile electronic devices (or more briefly, mobile devices) are designed to operate on a portable power supply, e.g. a battery. Accordingly, limiting power consumption and consuming power efficiently are key design parameters for the components of the mobile devices. Additionally, the relatively small form factors of many mobile devices call for reduced component counts, sizes, footprints, etc. 
     Counterbalancing low power and small size demands are the high performance requirements that come from the extraordinary functionality of the mobile devices. A user is able to browse the web, receive and send email, text, talk, and use other applications concurrently on modern mobile devices. The ability to provide an acceptable user experience across these different workloads is an important feature of the device. 
     SUMMARY 
     In an embodiment, an integrated circuit for use in mobile devices may be implemented using a dynamic random access memory (DRAM) fabrication process or a process having significant capacitive element capability. This capacitor may be optimized for power applications, and balanced for memory or logic operations. The technology may be an embedded DRAM (eDRAM) fabrication process in which DRAM is embedded on the same integrated circuit die as logic circuitry such as a processor or other logic components of a system. In other embodiments, the process may be a normal DRAM fabrication process and the logic circuits may operate somewhat more slowly than in an eDRAM process. The capacitors supported by the fabrication process may be high quality capacitors, e.g. as compared to those that may be formed in an advanced logic process as is typically used for integrated circuits that include processors and/or other logic components. The capacitors may be dense, and may have low non-capacitive parasitics (e.g. resistance and/or inductance) due to the DRAM process in which they are formulated. 
     In various embodiments, the capacitors may be used as decoupling capacitors (decap) and/or in voltage regulators for on-chip power management units. The high quality decap may improve response to noise and current-based supply voltage drop (e.g. IR drop). The on-chip voltage regulators may allow fine-grain PMUs on chip, which may reduce power consumption and may provide more granularity in powering up/down components on the integrated circuit. Additionally, integrating the voltage regulators may reduce component count at the system level, which may permit a more compact system. 
     In some embodiments, the integrated circuit may include an on-chip memory (e.g. a cache) formed of DRAM memory. The on-chip memory may be denser that a corresponding SRAM memory, reducing cost or permitting a larger capacity memory in the same integrated circuit die area. Additionally, leakage current in the memory may be significantly reduced in the DRAM as compared to the SRAM memory, reducing power consumption. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The following detailed description makes reference to the accompanying drawings, which are now briefly described. 
         FIG. 1  is a block diagram of one embodiment of an integrated circuit. 
         FIG. 2  is a circuit diagram of one embodiment of a switched capacitor voltage regulator. 
         FIG. 3  is a circuit diagram of one embodiment of a buck voltage regulator. 
         FIG. 4  is a block diagram of one embodiment a system including multiple integrated circuits. 
         FIG. 5  is a block diagram of another embodiment of a system including multiple integrated circuits. 
         FIG. 6  is a block diagram of one embodiment of a capacitor. 
         FIG. 7  is a block diagram of one embodiment of an integrated circuit and associated package substrate. 
         FIG. 8  is a block diagram of one embodiment of an inductor on the package substrate. 
         FIG. 9  is a block diagram of another embodiment of the inductor in the package substrate. 
         FIG. 10  is a circuit diagram of one embodiment of decap capacitors. 
         FIG. 11  is a circuit diagram of another embodiment of decap capacitors. 
         FIG. 12  is a circuit diagram of one instances of the embodiment of  FIG. 11  programmed to an exemplary configuration. 
     
    
    
     While the embodiments described herein are susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the embodiments to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include”, “including”, and “includes” mean including, but not limited to. 
     Various units, circuits, or other components may be described as “configured to” perform a task or tasks. In such contexts, “configured to” is a broad recitation of structure generally meaning “having circuitry that” performs the task or tasks during operation. As such, the unit/circuit/component can be configured to perform the task even when the unit/circuit/component is not currently on. In general, the circuitry that forms the structure corresponding to “configured to” may include hardware circuits. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.” Reciting a unit/circuit/component that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that unit/circuit/component. 
     This specification includes references to “one embodiment” or “an embodiment.” The appearances of the phrases “in one embodiment” or “in an embodiment” do not necessarily refer to the same embodiment, although embodiments that include any combination of the features are generally contemplated, unless expressly disclaimed herein. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure. 
     DETAILED DESCRIPTION OF EMBODIMENTS 
       FIG. 1  is a block diagram of one embodiment of an integrated circuit (IC)  10 . In the illustrated embodiment, the integrated circuit  10  includes a set of components  12 A- 12 D, power management units (PMUs)  14 A- 14 D, decoupling capacitors (decaps)  16 A- 16 H, and a memory  18 . The PMU  14 A is shown to include a register  20  and a voltage regulator  22 . Other PMUs  14 B- 14 C may be similar. 
     The integrated circuit  10  may be manufactured using a dynamic random access memory (DRAM) fabrication process. A DRAM fabrication process may generally be optimized for producing DRAM memories. A DRAM memory cell includes a capacitor and a transistor that acts as a switch to permit access to the cell. The voltage on the capacitor represents the value stored in the cell. Accordingly, the DRAM fabrication process may be optimized to produce high quality capacitors and to permit dense packing of the DRAM cells. A high quality capacitor may be small for a given capacitance. A high quality capacitor may have low non-capacitive parasitics (e.g. resistance or inductance). That is, a high quality capacitor may approach, as nearly as practicable, an ideal capacitor. In an embodiment, the DRAM fabrication process may be a standard DRAM process used to produce DRAM chips. Such chips may have a large array of DRAM cells and a relatively small amount of logic circuitry (to receive addresses, access the array, and provide/receive data to/from the array) and may be optimized for memory, whereas the speed, size, and other aspects of the logic circuitry may not be as optimized. The DRAM fabrication process may also be an embedded DRAM (eDRAM) process, which may more equally optimize the logic circuits and the DRAM memory circuits. The eDRAM process is largely built off a logic process. This process may be used to embed DRAM memories in integrated circuits that include significant logic circuits needing cache/memory in close proximity (e.g. processors such as central processing units (CPUs), graphics processing units (GPUs), peripherals and/or peripheral interface controllers, etc.). A more equal optimization of memory and logic circuitry may permit good DRAM density with well-performing logic circuitry on the same die. There are several methods for forming the capacitors that are included, such as in the semiconductor substrate (e.g. a trench capacitor), or as capacitors above the semiconductor substrate in the interconnect. 
     Each PMU  14 A- 14 D may provide a power supply voltage (or more briefly, “supply voltage”) to the components to which it is coupled. For example, in the embodiment of  FIG. 1 , the PMU  14 A may be coupled to the components  12 A- 12 B. The PMU  14 B may be coupled to the component  12 C, the PMU  14 C may be coupled to the component  12 D, and the PMU  14 D may be coupled to the memory  18 . The magnitude of the supply voltage may be programmed into the register  20 , and may be changed from time to time as desired during operation by reprogramming the register  20 . The PMU  14 A may be coupled to receive an input supply voltage that is provided to the IC  10 , and may be configured generate the desired supply voltage as an output using the voltage regulator  22 . 
     Because the PMUs  14 A- 14 D are on-chip, they may be physically located near the components to which they provide power. Thus, IR drops due to distance from source to consumer may be minimized. In some embodiments, the PMUs  14 A- 14 D may replace power switches. Additionally, the PMUs may be as fine grain as desired. Multiple different supply voltage magnitudes may be supported concurrently in the IC  10  based on the same input supply voltage to the IC  10 . 
     As illustrated in  FIG. 1 , a PMU may be dedicated to a component (e.g. the PMU  14 B may be dedicated to the component  12 C, and the PMU  14 C may be dedicated to the component  12 D). Alternatively, a PMU may be shared between two or more components (e.g. the PMU  14 A may be shared between the components  12 A- 12 B). A PMU may be shared, e.g., if the components would typically be powered up and powered down together. That is, one component may be required for the other component to operate. 
     The voltage regulator  22  may include one or more capacitors. The capacitors may be formed using the DRAM fabrication process, and thus may be high quality capacitors as discussed below with respect to the decaps  16 A- 16 H. Various exemplary voltage regulator circuits are described below with respect to  FIGS. 2 and 3 . 
     The decaps  16 A- 16 H may be coupled to the power supply grid at various locations in the integrated circuit  10  (not shown) to improve stability of the power supply voltage at times when local current changes and/or noise would cause the power supply voltage magnitude to vary excessively (e.g. AC droop), which may cause erroneous circuit operation. In cases in which power gating is implemented, the decaps  16 A- 16 G may be coupled to the local (switched) power grid, the global (unswitched) power supply grid, or both. Generally, the decaps  16 A- 16 G may be placed as near as practical to the source of the current/site of the expected AC voltage droop. Thus, the decaps  16 A,  16 B, and  16 E may all stabilize the memory  18 ; the decaps  16 B and  16 C may stabilize the component  12 A, the decaps  16 D and  16 H may stabilize the component  12 C, the decaps  16 E- 16 F may stabilize the component  12 B, and decaps  16 G may stabilize the component  12 D. 
     The memory  18  may be an optional part of the IC  10 . That is, there are embodiments of the IC  10  that do not include the memory  18 . The memory  18  may be formed from the DRAM or eDRAM that is supported by the DRAM fabrication process used to manufacture the IC  10 . The memory  18  may be a cache memory (and thus there may be an off-chip system memory in a system that includes the IC  10 ). Alternatively, the memory  18  may be the system memory (and the next level in the hierarchy off chip may be non-volatile storage such as disk for flash memory). There may be more than one memory  18  in various embodiments, and there may both cache memory and system memory within the IC  10 . In either case, the use of DRAM technology for the memory may lead to higher density and lower power consumption than a similar-sized SRAM memory. In various embodiments, the memory  18  may be capacitor under bit cell or capacitor over bit cell construction. The capacitors in the decaps  16 A- 16 H and the voltage regulators  22  may be the same construction as the capacitors in the memory  18 . That is, the capacitors in the decaps  16 A- 16 H and voltage regulators  22  may be formed in the same fashion as the capacitors in the memory  18 . 
     The components  12 A- 12 D may include any logic circuitry that is desired in the IC  10 . The components may include processors such as CPUs, GPUs, digital signal processors (DSPs), chip set, System on Chip (SOC), input/output (I/O) processors, etc. The components may include memory controllers for interface to off-chip memory. The components may include various peripherals such as video peripherals, audio peripherals, networking peripherals, peripheral interface controllers, etc. Any set and number of components  12 A- 12 D may be included in various embodiments, including more or fewer components than those shown in  FIG. 1 . Generally, various embodiments of the IC  10  may include any number and configuration of the various features shown in  FIG. 1 , including more or fewer than those shown and differing arrangements of those shown and/or other features. 
     Turning now to  FIG. 2 , a circuit diagram of one embodiment of the voltage regulator  22  and the register  20  is shown. The embodiment of  FIG. 2  may be a switched-capacitor regulator. In the illustrated embodiment, the voltage regulator  22  may include a switch control circuit  30 , a capacitor  32 , and switches (labeled “a” and “b” in  FIG. 2 ) all coupled as shown in  FIG. 2 . The input voltage (Vin) may be a power supply voltage supplied to the IC  10 , e.g. on one or more pins of the IC  10 . Alternatively, the input voltage may be sourced from another voltage regulator in another PMU. The output voltage (Vout) may be the power supply voltage supplied to the component(s) controlled by the PMU. For example, Vout may be the power supply voltage supplied by the PMU  14 A to the components  12 A- 12 B in  FIG. 1 , or the power supply voltage supplied by the PMU  14 B to the component  12 C in  FIG. 1 . 
     Based on the magnitude of the input voltage Vin and the desired magnitude of the output voltage Vout from register  20 , the switch control circuit  30  may be configured to control the switches a and b to produce, on average, a Vout voltage of the desired magnitude. When the switches a are closed and the switches b are open, the capacitor  32  may be charged. When the switches a are open and the switches b are closed, the capacitor  32  may provide the charge for the Vout supply voltage. Thus, the capacitor may be discharging when the switches b are closed. The switches a and b may be formed in any desired fashion. For example, the switches may be transistors, passgate circuits, etc. 
     The capacitor  32  may be formed using the DRAM fabrication process, and thus may be a high quality capacitor similar to the ones formed in DRAM memories that would be formed using the DRAM fabrication process. In an embodiment, capacitors similar to those shown in  FIG. 6  may be used. More than one capacitor may be used, in series and/or parallel, to provide the desired capacitance and stability of the supply voltage Vout. The switches implemented with the various capacitors may be controlled by the switch control circuit  30  with different timings, phases, etc. to provide a more stable, low ripple supply voltage. 
       FIG. 3  is a circuit diagram of another embodiment of the voltage regulator  22  and the register  20 . The embodiment of  FIG. 3  may be a buck regulator. In the illustrated embodiment, the voltage regulator  22  may include a switch control circuit  34 , an inductor  36 , and a capacitor  38 , and switches (labeled “a” and “b” in  FIG. 3 ) all coupled as shown in  FIG. 3 . The input voltage (Vin) may be a power supply voltage supplied to the IC  10 , e.g. on one or more pins of the IC  10 . Alternatively, the input voltage may be sourced from another voltage regulator in another PMU. The output voltage (Vout) may be the power supply voltage supplied to the component(s) controlled by the PMU. For example, Vout may be the power supply voltage supplied by the PMU  14 A to the components  12 A- 12 B in  FIG. 1 , or the power supply voltage supplied by the PMU  14 B to toe component  12 C in  FIG. 1 . 
     Based on the magnitude of the input voltage Vin and the desired magnitude of the output voltage Vout from register  20 , the switch control circuit  34  may be configured to control the switches a and b to produce, on average, a Vout voltage of the desired magnitude. When the switch a is closed and the switch b is open, current flows through the inductor  36  and a voltage drop across the inductor  36  forms in response to the changing current, thus reducing the voltage on the capacitor  38  (and Vout). When the switch a is open and the switch b is closed, the energy stored in the magnetic field of the inductor  36  may continue current flow and may help to maintain the voltage Vout. The switches a and b may be formed in any desired fashion. For example, the switches may be transistors, passgate circuits, etc. 
     The capacitor  38  may be formed using the DRAM fabrication process, and thus may be a high quality capacitor similar to the ones formed in DRAM memories that would be formed using the DRAM fabrication process. In an embodiment, capacitors similar to those shown in  FIG. 6  may be used. More than one capacitor may be used, in series and/or parallel, to provide the desired capacitance and stability of the supply voltage Vout. The inductor  36  may be formed on the IC  10  is some cases, or may be formed on or in the package substrate of the package for the IC  10 . Examples are illustrated in  FIGS. 7 to 9 . 
       FIG. 4  is a block diagram of a system including an embodiment of the IC  10  and a second IC  40 . In the illustrated embodiment, the IC  10  may be fabricated using the DRAM fabrication process, and the IC  40  may be fabricated using a different process. The IC  10  may include the memory  18 , and a corresponding PMU  14 D. The components of the IC  10  may include one or more CPUs  12 E with a corresponding PMU  14 E; one or more GPUs  12 F with a corresponding PMU  14 F; and/or one or more other components  12 G with a corresponding PMU  14 G. Decaps may be included as well, as shown in  FIG. 1 . The IC  40  may optionally include a memory controller  42  to couple to a DRAM memory  44 , and may include a controller  46  and a non-volatile memory (NVM)  48 . Any sort of non-volatile memory may be used (e.g. NAND flash, NOR flash, other non-volatile memories, etc.). 
     In the system of  FIG. 4 , if the memory  18  is large enough for the targeted work loads, the memory  18  may be used as a system memory and the memory controller  42  and DRAM  44  may not be included. The flash memory  48  may serve as a non-volatile backing storage for the memory  18 . If the memory  18  is not large enough, the memory  18  may be a cache memory and the memory controller  42  and DRAM  44  may be included, with the flash memory  48  serving as a backing store for the DRAM  44 . The system may be fairly compact, and may be power efficient due to the reduced number of components (e.g. external PMUs may be reduced or eliminated) and due to the fine-grained on-chip PMUs  14 . 
       FIG. 5  is a block diagram illustrating another embodiment of a system including an embodiment of the IC  10 , the IC  40 , and another IC  50 . The IC  10  may be fabricated using the DRAM fabrication process, and the IC  50  may be fabricated using a different process (e.g. an advanced logic process optimized for digital logic circuitry rather than DRAM). The IC  40  may be similar to the IC  40  shown in  FIG. 4 . The IC  10  may include, in the illustrated embodiment, one or more PMUs  14 , optionally the memory  18 , and decaps  16 . 
     The PMUs  14  may provide power supply voltage(s) to the components in the IC  50  (e.g. the CPU  12 E, the GPU  12 F, and/or the other components  12 G, and the decaps  16  may be coupled to power supply grids in and around the components. The decaps  16  and PMUs  14  may also serve the memory  18 , in some embodiments. The embodiment of  FIG. 5  may still support a compact system while permitting both the advanced logic process and the DRAM fabrication process to be used for their respective circuitry. In the illustrated embodiment, the IC  10  and the IC  50  may be packaged in a module  52 . For example, the module  52  may be a multi-chip module (MCM) may be used in an embodiment. In other embodiments, package-on-package packaging, chip-on-chip packaging, silicon-on-silicon packaging, system in package etc. may be used. For example the IC  10  may be implemented with through-silicon vias (TSV) to connect the IC  50  to a circuit board or package substrate, and the IC  50  may be mounted on top of the IC  10  in a chip-on-chip configuration. In another embodiment, TSVs may not be used. The IC  50  may be mounted on top of the IC  10  and wire bonds may be used to reach the package, or the IC  10  may be mounted below the IC  50  in a flip-chip configuration and solder balls may be used to reach the package. Any packaging configuration may be used. 
       FIG. 6  is a block diagram illustrating one embodiment of a DRAM-based capacitor  60  that may be used for the decaps  16  and/or PMUs  14 . That is, the capacitor  60  may be fabricated in the same fashion that capacitors for the DRAM memory  18  are fabricated, using the DRAM fabrication process. The view in  FIG. 6  may be a side view, where the semiconductor substrate would be below the capacitor  60  as illustrated in  FIG. 6 . The illustrated capacitor  60  may be formed in wiring layers above the semiconductor substrate. The bottom plate  62  and the top plate  66  of the capacitor may be formed from conductive metals used in the process (e.g. aluminum, copper, tungsten, alloys of the above, etc.). A high K dielectric  64  used in the wiring layers may be included between the top plate  66  and the bottom plate  62 , providing a compact, high quality capacitor. 
     Other embodiments may implement the capacitors in different fashion, including DRAM fabrication processes that implement the capacitor in the semiconductor substrate (e.g. “below” the bit cells). Exemplary capacitors of this type may include deep trench capacitors of various types. 
       FIGS. 7-9  illustrate various embodiments for implementing an inductor, e.g. for buck voltage regulators such as the regulator shown in  FIG. 3 . In the illustrated embodiments, the inductor is implemented separate from the IC  10  (e.g. as a discrete component), although some embodiments may implement the inductor in the IC  10  as well.  FIG. 7  illustrates an embodiment in which the inductor  36  is embedded in a package substrate  70  of a package that encapsulates the IC  10 . The PMU  14 A my thus have connections (e.g. through solder balls in the illustrated embodiment, although any conductor may be used) to the inductor  36  in the package substrate  70 . The inductor  36  may be discrete inductor embedded in the substrate  70 , or may be formed as part of the substrate  70  (e.g. using the wiring layers).  FIG. 8  is a top view of the package substrate  70  in which a spiral wound planar wire  71  forms the inductor (with connection points  72  and  74  to connect to the PMU  14 A).  FIG. 9  is side view of an embodiment of the package substrate  70  in which a coiled wire approach is used. In the embodiment of  FIG. 9 , multiple wiring layers  76 A- 76 D are coupled through vias  78  in the insulating layers  80 A- 80 C to form the coiled wire. A top view of the layer  76 A illustrates the wire  82  in the layer, wound around an “air” or magnetic core  84 . An “air” core embodiment may be an insulating material, for example. A magnetic core may be used to enhance the inductive effect, in other embodiments. 
     The decaps  16 A- 16 H may be large structures, in some cases, and thus may be more susceptible to manufacturing defects that may reduce the yield of the IC  10 . For example, the decaps  16 A- 16 H may be more likely to suffer from a short in one of the capacitors, which renders the decap in which the short occurs useless, since the short will prevent the build-up of charge on the other capacitors that are in parallel. Additionally, the short between power and ground may prevent operation of the IC  10  overall, thus reducing the yield. Defects may be reduced using other dielectric materials, modifying dielectric height, or optimizing capacitor constructions, in some embodiments. Additionally or alternatively, cascaded capacitors and/or adding switches to the capacitors may be used to reduce the effect that defects have on the structure. In an embodiment, single capacitors may be used for decaps where high transient current density exists, and thus high capacitor density may be more important. In other areas where lower transient current density occurs, the cascaded (or stacked) capacitors illustrated in  FIGS. 10 and 11  may be used. 
       FIG. 10  is a circuit diagram illustrating one embodiment of cascaded capacitors that may be used for one or more of decaps  16 A- 16 H. In the illustrated embodiment, each parallel “leg” of capacitance includes at least two capacitors in series (e.g. the capacitors  90  and  92  are in series). Any number of capacitors may be placed in series in various embodiments. 
     In the embodiment of  FIG. 10 , either of the capacitors in a leg may be defective (resulting in a short) and the decap as a whole may remain functional with slightly different overall capacitance. For example, if the capacitor  90  is defective and a short, the capacitor  92  still prevents a short from power to ground. Similarly, if the capacitor  92  is defective and a short, the capacitor  90  still prevents a short from power to ground. If both capacitors in the same leg are shorted, then a short from power to ground may occur. If more capacitors are included in each leg, the probability of having defects that make a complete short may be reduced even further. 
       FIG. 11  is a circuit diagram illustrating an embodiment in which capacitors are in series with switches to reduce defects effect on yield and decap effectiveness. A switch control register  94  may be programmable to operate the switches. Accordingly, each capacitor  98  that is defective may be switched out (inline switch open), and capacitors  98  that are not defective may be switched in (inline switch closed). The contents to be programmed in to the register  94  may be determined in a variety of ways. For example, during testing, the register  94  may be programmed to close one switch at time (or multiple switches at time) to test for defects in the capacitors. Any isolated defects may be encoded into the IC  10  (e.g. in fuses, a read-only memory, or a non-volatile memory in the IC  10 ). Alternatively, an on-chip tester may be included to test the capacitors and program the register  94  with the results. The switches may even participate in the testing (e.g. providing a high resistance path that gradually increases and the voltage may be monitored). 
       FIG. 12  illustrates an example in which the capacitor  96  is defective but other capacitors are not defective. Accordingly, the register  94  may be programmed to open the switch that is inline with the capacitor  96  and to close the other switches. 
     Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.