Patent Publication Number: US-10790274-B2

Title: SCRs with checker board layouts

Description:
This application is a continuation of U.S. patent application Ser. No. 14/844,272, filed Sep. 3, 2015, entitled “SCRs with Checker Board Layouts,” now U.S. Pat. No. 9,812,436, which is a continuation of U.S. patent application Ser. No. 14/044,601, filed Oct. 2, 2013, entitled “SCRs with Checker Board Layouts,” now U.S. Pat. No. 9,147,676, which applications are hereby incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     Silicon-Controlled Rectifier (SCR) devices have excellent Electro-Static Discharge (ESD) immunity and are good candidates for low-capacitance applications, which include Radio Frequency (RF) and high speed devices. SCRs, however, have low turn-on speed and high trigger voltages, and hence are not suitable for operations that need high turn-on speed and low trigger voltages. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  illustrates a top view of a Silicon-Controlled Rectifier (SCR) and diode string unit (referred to as SCR/diode-string unit hereinafter) in accordance with some exemplary embodiments, wherein two diodes are connected serially to form the diode string; 
         FIG. 2  illustrates a cross-sectional view of the SCR/diode-string unit in accordance with some exemplary embodiments; 
         FIG. 3  illustrates a circuit diagram of the SCR/diode-string unit in  FIG. 2 ; 
         FIG. 4  illustrates a top view of a plurality of SCR/diode-string units connected in parallel; 
         FIG. 5A  illustrates a top view of an SCR/diode-string combo unit in accordance with alternative embodiments, wherein four diodes are connected in series to form a diode string; 
         FIG. 5B  illustrates a top view of an SCR/diode-string combo unit in accordance with alternative embodiments, wherein three diodes are connected in series to form a diode string; 
         FIG. 6  illustrates a cross-sectional view of the SCR/diode-string combo unit in  FIG. 5A ; 
         FIG. 7  illustrates a circuit diagram of the SCR/diode-string combo unit in  FIG. 5A ; 
         FIG. 8A  illustrates a top view of a diode-string-free SCR unit in accordance with some embodiments; 
         FIG. 8B  illustrates a top view of a diode-string-free SCR unit in accordance with some embodiments, wherein the diode-string-free SCR unit includes a half of the diode-string-free SCR unit shown in  FIG. 8A ; 
         FIG. 9  illustrates an Electro-Static Discharge (ESD) device including a plurality of SCR/diode-string units connected in parallel; 
         FIG. 10  illustrates an ESD device including SCR/diode-string unit(s) and diode-string-free SCR units, wherein a ratio of the number of SCR/diode-string unit(s) to the number of diode-string-free SCR units is equal to 1:1; 
         FIG. 11  illustrates an ESD device including SCR/diode-string unit(s) and diode-string-free SCR units, wherein a ratio of the number of SCR/diode-string unit(s) to the number of diode-string-free SCR units is equal to 1:2; 
         FIG. 12  illustrates an ESD device including SCR/diode-string unit(s) and diode-string-free SCR units, wherein a ratio of the number of SCR/diode-string unit(s) to the number of diode-string-free SCR units is equal to 1:3; and 
         FIG. 13  illustrates a table showing the relationship between the holding voltages of SCR/diode-string units and the number of diodes in the diode string of the respective SCR/diode-string units. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure. 
     Electro-Static Discharge (ESD) protection devices comprising Silicon-Controlled Rectifiers (SCR) and diode strings are provided in accordance with various exemplary embodiments. The variations of the ESD protection devices in accordance with some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. 
       FIG. 1  illustrates a top view of a unit (referred to as an SCR/diode-string unit hereinafter) that includes an SCR and a diode string therein. SCR/diode-string unit  20  includes a plurality of semiconductor strips  22 , which are surrounded by Shallow Trench Isolation (STI) region(s)  24 . Referring to  FIG. 2 , semiconductor strips  22  include portions  22 ′ between STI regions  24 , and may, or may not, include semiconductor fins  22 ″ that are over the top surfaces of STI regions  24 . 
     Referring back to  FIG. 1 , the plurality of semiconductor strips  22  has lengthwise directions parallel to each other. The neighboring semiconductor strips  22  may have a uniform pitch. A plurality of gate stacks  28  are formed over semiconductor strips  22 , and may be formed to contact the sidewalls and the top surfaces of semiconductor strips  22 . Each of gate stacks  28  includes a gate dielectric layer and a gate electrode (not shown). 
     Well regions  26  (including  26 A and  26 B) are formed, and portions  22 B of semiconductor strips  22 , which portions  22 B are covered by gate stacks  28 , may also be portions of well regions  26 . In some embodiments, well regions  26  are n-well regions, which may have an n-type impurity concentration between about 1E14/cm 3  and about 1E17/cm 3 , for example. Accordingly, the portions  22 B of semiconductor strips  22  are of n-type. Semiconductor strips  22  include heavily doped p-type (p+) regions  22 A and heavily doped n-type (n+) regions  22 C, which have a p-type impurity concentration and an n-type impurity concentration, respectively, between about 1E19/cm 3  and about 5E21/cm 3 , for example. 
     Semiconductor strips  22  form diodes D 1  and D 2 . Each of diodes D 1  and D 2  has p-type semiconductor strip portions  22 A as the anode, and n-type semiconductor strip portions  22 B and  22 C as the cathode. The anode and the cathode of diode D 1  is on the top left part and top right part of SCR/diode-string unit  20 . The anode and the cathode of diode D 2  is on the bottom right part and bottom left part of SCR/diode-string unit  20 . Accordingly, the p+ regions  22 A and n+ regions  22 C are allocated in a checker board pattern, wherein the checker board pattern have black and white patterns allocated in an alternating layout in each row and each column of a checker board. 
     Metal connections  30 , which may be contact plugs, are formed for interconnection. Through metal connections  30 , all semiconductor strips  22 A in diode D 1  are interconnected. All semiconductor strips  22 C in diode D 1  are interconnected. All semiconductor strips  22 A in diode D 2  are interconnected. All semiconductor strips  22 C in diode D 2  are interconnected. Furthermore, semiconductor strips  22 C of diode D 1  is connected to semiconductor strips  22 A in diode D 2 , for example, through metal connections (such as metal lines, vias, and contact plugs)  32 . Accordingly, diodes D 1  and D 2  form a diode string. The anode  22 A of diode D 1  may be connected to input/output pad  34  through metal connections  32 . The cathode  22 C of diode D 2  may be connected to Vss node  36  through metal connections  32 , which may be an electrical ground. Diodes D 1  and D 2  are biased in the same direction, with the cathode of each of diodes D 1  and D 2  closer to Vss node  36  than the respective anode of the same diode. 
       FIG. 2  illustrates a cross-sectional view of the structure shown in  FIG. 1 , wherein the cross-sectional view is obtained from the plane containing A-A in  FIG. 1 . In some embodiments, substrate  38  is a p-type substrate (p-sub). Accordingly, the structure in  FIG. 2  form PNP bipolar transistor PNP 1  and NPN bipolar transistor NPN 1 . Bipolar transistor PNP 1  includes p+ strips  22 A as the emitter, n-well region  26 A as the base, and p-sub  38  as the collector. Bipolar transistor NPN 1  has n+ strips  22 C and n-well region  26 B as the emitter, p-sub  38  as the base, and n-well region  26 A as the collector. Bipolar transistors PNP 1  and NPN 1  in combination form an SCR, which is referred to as SCR 1  hereinafter. 
       FIG. 3  illustrates the circuit diagram of SCR/diode-string unit  20 , wherein diodes D 1  and D 2  and bipolar transistors PNP 1  and NPN 1  are illustrated. The SCR 1  is triggered by the currents of diode string D 1  and D 2 . SCR/diode-string unit  20  has a high ESD discharging ability due to the high ESD discharging ability of SCR 1 . On the other hand, diodes D 1  and D 2  are also coupled between pad  34  and Vss node  36 . Accordingly, SCR/diode-string unit  20  has a high turn-on speed due to the high turn-on speed of diodes D 1  and D 2 . The high turn-on speed is advantageous for the ESD protection in Charge Device Mode (CDM). 
       FIG. 4  illustrates a top view of an ESD protection device, which includes a plurality of SCR/diode-string units  20  connected in parallel. Each of SCR/diode-string units  20  is connected to pad  34  and Vss node  36 . The p+ regions  22 A and n+ regions  22 C are allocated in a checker board pattern. These embodiments have good ESD discharging ability since the ESD discharging current is multiplied. On the other hand, since the diode string in each of SCR/diode-string units  20  is coupled between pad  34  and Vss node  36 , the turn-on speed is high. 
       FIG. 5A  illustrates SCR/diode-string combo unit  44 , which includes two SCR/diode-string units  20  (including  20 A and  20 B having an identical structure) cascaded between input/output pad  34  and Vss node  36 . The p+ regions  22 A and n+ regions  22 C (refer to  FIG. 1 ) in these embodiments are also allocated in a checker board pattern. In these embodiments, metal connection  46  is formed to connect the cathode of diode D 2  in SCR/diode-string unit  20 A to the anode of diode D 3  in SCR/diode-string unit  20 B. Accordingly, SCR/diode-string unit  44  includes a diode string including four diodes D 1 , D 2 , D 3 , and D 4  biased in the same direction. With the diode string including four diodes, the holding voltage of SCR/diode-string combo unit  44  is increased over the holding voltage of a single SCR/diode-string unit  20 . 
       FIG. 5B  illustrates SCR/diode-string combo unit  44  in accordance with alternative embodiments. These embodiments are similar to the embodiments in  FIG. 5A , except that there are three diodes D 1 , D 2 , and D 3  (rather than four diodes) forming the respective diode string. 
     In alternative embodiments, more (such as 3, 4, 5, and 6) SCR/diode-string units  20  may be cascaded to form a SCR/diode-string combo unit. As can be found from  FIGS. 1 and 5 , the holding voltage of the SCR/diode-string combo units in accordance with the exemplary embodiments may be adjusted by changing the number of cascaded SCR/diode-string units  20 .  FIG. 13  illustrates the holding voltages of the SCR/diode-string combo units as a function of the number of cascaded SCR/diode-string units  20  ( FIG. 1 ). For example, when SCR/diode-string unit  20  has two to three diodes, as shown in  FIG. 1 , the holding voltage may be about 0.9 volts. The SCR/diode-string combo unit  44  as shown in  FIG. 5A , which includes two SCR/diode-string units  20 , and hence four diodes, serially connected, has a holding voltage of 1.8 volts. Three serially connected diodes may also have the holding voltage of 1.8 Volts. When the number of cascaded SCR/diode-string units  20  increases to 4˜5 or 5˜6, which correspond to 8˜10 or 10˜12 serially connected diodes, respectively, the holding voltage may increase to about 3.3 volts and about 5 volts, respectively. 
       FIG. 6  illustrates a cross-sectional view of the structure shown in  FIG. 5A , wherein the cross-sectional view is obtained from the plane containing line B-B in  FIG. 5A . As shown in  FIG. 6 , three SCRs are formed. SCR 1  is the SCR formed by SCR/diode-string unit  20 A. SCR 1  includes n-well regions  26 A and  26 B, and the overlying p+ portions  22 A and n+ portions  22 C. SCR 2  is the SCR formed by SCR/diode-string unit  20 B. SCR 2  includes n-well regions  26 C and  26 D, and the overlying p+ portions  22 A and n+ portions  22 C. SCR 3  includes n-well regions  26 A and  26 D, and the overlying p+ portions  22 A and n+ portions  22 C. The details of each of SCR 1 , SCR 2 , and SCR 3  may be found referring to the discussion of  FIG. 2 . 
       FIG. 7  illustrates a circuit diagram of SCR/diode-string combo unit  44 , wherein transistors PNP 1  and NPN 1  form SCR 1  ( FIG. 6 ), transistors PNP 2  and NPN 2  form SCR 2  ( FIG. 6 ), and transistors PNP 1  and NPN 3  form SCR 3  ( FIG. 6 ). Diodes D 1 , D 2 , D 3 , and D 4  are serially connected between pad  34  and Vss node  36 . The SCRs SCR 1 , SCR 2 , and SCR 3  are triggered by the currents of the diode string D 1 , D 2 , D 3 , and D 4 . Similarly, SCR/diode-string combo unit  44  has a high turn-on speed due to the high turn-on speed of diodes D 1 , D 2 , D 3 , and D 4 . 
       FIG. 8A  illustrates a diode-string-free SCR unit  50  in accordance with some embodiments. Diode-string-free SCR unit  50  includes SCRs that are connected between nodes  34  and  36 , and does not include any diode string that are connected directly from node  34  to node  36 , with all diodes in the diode string biased in the same direction. In these embodiments, each of semiconductor strips  22  in diode-string-free SCR unit  50  is doped to a same conductivity type, with semiconductor strips  22 A being of p-type, and semiconductor strips  22 C being of n-type. Therefore, the portions of the same semiconductor strip  22  on the opposite sides of gate stacks  28  are of the same conductivity type, and hence do not form a diode. 
     In  FIG. 8A , SCRs SCR 1 , SCR 2 , and SCR 3  are marked, wherein each of the SCRs SCR 1 , SCR 2 , and SCR 3  is formed of a p+ strip, an n+ strip, the underlying n-well regions  26 , and the p-sub  38  underlying n-well regions  26 . Accordingly, diode-string-free SCR unit  50  has a similar ability for conducting high ESD currents as SCR/diode-string combo units  44  ( FIGS. 5 through 7 ). 
       FIG. 8B  illustrates diode-string-free SCR unit  50  in accordance with alternative embodiments. These embodiments are similar to the embodiments in  FIG. 8A , except that the diode-string-free SCR unit  50  in these embodiments includes a half (the left half or the right half) of the diode-string-free SCR unit  50  in  FIG. 8A . Alternatively stated, the diode-string-free SCR unit  50  in  FIG. 8A  may be assembled by placing two of the diode-string-free SCR unit  50  in  FIG. 8B  together. 
     SCR/diode-string units  20  ( FIG. 1 ) and SCR/diode-string combo units  44  ( FIGS. 5A and 5B ) have the advantageous features of high turning-on speed, and hence are capable of reducing CDM overshoot. On the other hand, diode-string-free SCR unit  50  ( FIG. 8A or 8B ) has more SCRs, and hence can provide better ESD protection for high-ESD-current applications. Accordingly, by combining SCR/diode-string units  20  and SCR/diode-string combo units  44  with diode-string-free SCR unit  50 , the requirement of reducing CDM overshoot and conducting high ESD current may be satisfied. 
       FIGS. 9, 10, 11, and 12  illustrate the top views of portions of exemplary ESD protection circuits. It is appreciated that the ESD protection circuits may include more portions repeating the illustrated portions.  FIGS. 9, 10, 11, and 12  have different ratios of the number of SCR/diode-string combo units  44  to the number of diode-string-free SCR units  50 . The ESD protection circuit in  FIG. 9  includes SCR/diode-string combo units  44 , and does not include any diode-string-free SCR unit  50 . Accordingly the ratio is 1:0. The ESD protection circuit in  FIG. 10  includes one SCR/diode-string combo unit  44  corresponding to each diode-string-free SCR unit  50 . Accordingly, the ratio is 1:1. The ESD protection circuit in  FIG. 11  includes one SCR/diode-string combo units  44  corresponding to every two diode-string-free SCR units  50 . Accordingly, the ratio is 1:2. The ESD protection circuit in  FIG. 12  includes one SCR/diode-string combo unit  44  corresponding to every three diode-string-free SCR units  50 . Accordingly, the ratio is 1:3. 
     The embodiments of the present disclosure have several advantageous features. The formation of the ESD protection circuit is fully compatible with the manufacturing process for forming Fin Field-Effect Transistors (FinFETs), regardless of the spacing between the semiconductor strips. Furthermore, the trigger voltage and the holding voltage of the ESD protection circuit may be adjusted by changing the number of cascaded diodes in the diode string. Furthermore, the requirements for reducing CDM overshoot and conducting high ESD current may be balanced through adjusting the ratio of the number of SCR/diode-string combo units to the number of diode-string-free SCR units. 
     In accordance with some embodiments, an ESD protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips. The ESD protection circuit further includes a conductor electrically connecting a first one of the plurality of groups of p+ strips to a second one of the plurality of groups of n+ strips, wherein the first one and the second one are in a same column. 
     In accordance with other embodiments, an ESD protection circuit includes a semiconductor substrate of a first conductivity type, and a first well region and a second well region of a second conductivity type opposite to the first conductivity type. The first well region and the second well region are separated from each other by a portion of the semiconductor substrate. A first semiconductor strip extends in a row direction and overlaps and contacts the first well region. The first semiconductor strip includes a first heavily doped portion of the first conductivity type, a second heavily doped portion of the second conductivity type, and a third portion of the second conductivity type connecting the first portion to the second portion. A first gate stack overlaps the third portion of the first semiconductor strip. A second semiconductor strip extends in the row direction and overlaps and contacts the second well region. The second semiconductor strip includes a fourth heavily doped portion of the first conductivity type, a fifth heavily doped portion of the second conductivity type, and a sixth portion of the second conductivity type connecting the fourth portion to the fifth portion. The first and the fifth portions are in a same first column. The second and the fourth portions are in a same second column. A second gate stack overlaps the sixth portion of the second semiconductor strip. A first conductor electrically connects the second portion to the fourth portion. The first and the second gate stacks and the first and the second semiconductor strips are comprised in an SCR/diode-string unit. 
     In accordance with yet other embodiments, an ESD protection circuit includes a p-type semiconductor substrate, and a diode string including a first, a second, a third, and a fourth diode. The first, the second, the third, and the fourth diodes are aligned sequentially in a column. Each of the first, the second, the third, and the fourth diodes includes a p+ semiconductor strip as an anode, and an n-type semiconductor strip and a n+ semiconductor strip as a cathode. The anodes and the cathodes of the first, the second, the third, and the fourth diodes form an array. In each of rows and columns of the array, the anodes and the cathodes are allocated in an alternating layout. The ESD protection circuit further includes a gate electrode overlaps the n-type semiconductor strip, and four n-well regions, each overlapped by and in contact with one of the first, the second, the third, and the fourth diodes. The four n-well regions are separated from each other by portions of the p-type semiconductor substrate. 
     Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.