Patent Publication Number: US-8969928-B2

Title: Transistors having a control gate and one or more conductive structures

Description:
TECHNICAL FIELD 
     The present disclosure relates generally to semiconductor devices and, in particular, in one or more embodiments, the present disclosure relates to transistors. 
     BACKGROUND 
     Transistors, such as field effect transistors (FETs), having high breakdown voltages (e.g., above about 15 to about 80 volts or greater) are used in various applications, such as power management or amplification and for driver systems. For example, the breakdown voltage may be defined as the voltage at which the drain (or source) breaks down while the transistor is turned off. In addition, transistors having high breakdown voltages may be used on the periphery of a memory device. For example, these transistors can be located between charge pumps and the string drivers of a memory device that provide voltages to the access lines (e.g., word lines) and can be used in charge pump circuitry and for the string drivers. 
     One technique for creating transistors with high breakdown voltages uses a lightly doped region between a source/drain region and the control gate of the transistor. This region is sometimes referred to as a drain extension region. 
     Aside from device geometry, breakdown voltage of such transistors can be dependent upon doping levels between the source/drain region and the control gate. This region between the source/drain region and the control gate is sometimes conductively doped at the same time as doping of the source/drain region itself because doping these regions separately add process steps and thus fabrication costs. However, doping levels desirable for contacts to the source/drain region may not lead to desirable breakdown voltages. 
     For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative transistor structures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A-1G  are cross-sectional views of a transistor at various stages of fabrication in accordance with an embodiment of the disclosure. 
         FIG. 1H  is a top view of the transistor of  FIG. 1G . 
         FIG. 2A  is a top view of a transistor in accordance with another embodiment of the disclosure. 
         FIG. 2B  is a cross-sectional view of the transistor of  FIG. 2A . 
         FIG. 3A  is a top view of a transistor in accordance with another embodiment of the disclosure. 
         FIG. 3B  is a cross-sectional view of the transistor of  FIG. 3A . 
         FIG. 4A  is a top view of a transistor in accordance with another embodiment of the disclosure. 
         FIG. 4B  is a cross-sectional view of the transistor of  FIG. 4A . 
         FIG. 5A  is a top view of a transistor in accordance with another embodiment of the disclosure. 
         FIG. 5B  is a cross-sectional view of the transistor of  FIG. 5A . 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The term semiconductor can refer to, for example, a layer of material, a wafer, or a substrate, and includes any base semiconductor structure. “Semiconductor” is to be understood as including silicon on sapphire (SOS) technology, silicon on insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a semiconductor in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure. The following detailed description is, therefore, not to be taken in a limiting sense. 
     Various embodiments include transistors having a dielectric over a semiconductor, a control gate over the dielectric at a particular level, and one or more conductive structures over the dielectric at the particular level. The one or more conductive structures are between the control gate and at least one source/drain region of the transistor. The one or more conductive structures are electrically isolated from the control gate. 
       FIGS. 1A-1G  depict cross-sectional views of a transistor during various stages of fabrication taken along view line  1 G- 1 G′ of  FIG. 1H  in accordance with an embodiment.  FIG. 1A  depicts a semiconductor  100  upon which the transistor will be formed. For one embodiment, the semiconductor  100  is a monocrystalline silicon. For a further embodiment, semiconductor  100  is a conductively-doped monocrystalline silicon. Other embodiments may include amorphous silicon, polycrystalline silicon (commonly referred to as polysilicon), or other semiconductor materials. Semiconductor  100  may be conductively doped to a first conductivity type, e.g., a p-type conductivity. Doping is often performed through ion implantation techniques. Dopant sources for ion implantation techniques are often fluorine-based gases. For example, in the ion implantation of boron ions to achieve a p-type conductivity, the source gas may be boron trifluoride (BF 3 ). Thermal processing may be performed following the implantation in order to diffuse the ions and to repair surface damage caused by the ion bombardment. In addition to ion implantation techniques, other doping methods are known such as diffusion techniques using gaseous, liquid or solid dopant sources. Examples of dopant sources for the diffusion of boron include gaseous diborane (B 2 H 6 ), liquid boron tribromide (BBr 3 ) and solid boron nitride (BN). Other dopant sources and specific techniques are well known in the art of semiconductor fabrication. 
     As further depicted in  FIG. 1A , a dielectric  105  and a conductor  110  have been formed on the semiconductor  100 . These elements will form the gate dielectric and control gate of the future transistor. 
     Formation of the structure of  FIG. 1A  can include formation of the dielectric  105  over an active region of the semiconductor  100 , e.g., an area over which active integrated circuit devices will be formed. For example, the active region of the semiconductor  100  may include a conductively-doped well of a semiconductor wafer. The dielectric  105  is generally one or more dielectric materials. The dielectric  105  might be formed, for example, by thermal oxidation of the semiconductor  100 . Alternatively, the dielectric  105  could be formed by a blanket deposition of a dielectric material, such as by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). Example dielectric materials for dielectric  105  include silicon oxides (SiO x ), silicon nitride (SiN x ), silicon oxynitrides (SiO x N y ), aluminum oxides (AlO x ), hafnium oxides (HfO x ), hafnium aluminum oxides (HfAlO x ), lanthanum oxides (LaO x ), tantalum oxides (TaO x ), zirconium oxides (ZrO x ), zirconium aluminum oxides (ZrAlO x ), etc., and combinations thereof. 
     The conductor  110  is formed over the dielectric  105 . In general, the conductor  110  includes one or more conductive materials. For one embodiment, the conductor  110  contains a conductively-doped polysilicon. For another embodiment, the conductor  110  contains a metal-containing material. For a further embodiment, the conductor  110  includes a metal-containing material over polysilicon, e.g., a refractory metal silicide formed on a conductively-doped polysilicon. The metals of chromium (Cr), cobalt (Co), hafnium (Hf), molybdenum (Mo), niobium (Nb), tantalum (Ta), titanium (Ti), tungsten (W), vanadium (V), zirconium (Zr), and metal nitrides (including, for example, titanium nitride, tantalum nitride, tantalum carbon nitride, tungsten nitride) for metal gates are generally recognized as refractory metal materials. For another embodiment, the conductor  110  contains multiple metal-containing materials, e.g., a titanium nitride (TiN) barrier over the dielectric  105 , titanium (Ti) as an adhesion material over the barrier, and tungsten (W) over the adhesion material. 
     In  FIG. 1B , a doped region  120 , may be formed in the semiconductor  100  below the dielectric  105 . The doped region  120  will form the body of the future transistor, and may be referred to herein alternately as the body  120 . For one embodiment, the doped region  120  is formed through implantation of a dopant species, depicted by arrows  115 . The dopant species  115  may have a conductivity type different than the conductivity type of the semiconductor  100 . For example, where the semiconductor  100  has a p-type conductivity, the doped region  120  may have an n-type conductivity. Example dopant species  115  for an n-type conductivity include compounds or ions of antimony (Sb), arsenic (As) and phosphorus (P). While  FIG. 1B  depicts an angled implant of the dopant species  115 , such is not necessary. As is well understood, control of the power of the implant can be used to determine a depth of the dopant species  115  within the semiconductor  100 , thus allowing the doped region  120  to be localized below the dielectric  105 . 
     In  FIG. 1C , the conductor  110  is patterned to define the control gate  125  of the transistor and one or more conductive structures  130 . For example, photolithographic techniques may be used to define the control gate  125  and the conductive structures  130 . 
     The control gate  125  and the conductive structures  130  are at a particular level over the dielectric  105 . Elements occurring at a particular level, as used herein, does not require that the elements be the same distance from some reference point, such as a surface of the semiconductor  100 . Instead, this will refer to a stage of fabrication, such that elements formed on the same preceding structure (e.g., the control gate  125  and conductive structures  130  of  FIG. 1C  are each formed to be in contact with the dielectric  105 ), or elements formed concurrently, will be deemed to be formed at the same level. 
     In  FIG. 1D , spacers  135  are formed. Spacers  135  generally contain one or more dielectric materials. Example dielectric materials include a silicon oxide (SiO/SiO 2 ), silicon nitride (SiN/Si 2 N/Si 3 N 4 ) or silicon oxynitride (SiOxNy) material. Other dielectric materials are known and used in the art of semiconductor fabrication. In general, the dielectric material of spacers  135  should be chosen to generally inhibit current flow between the control gate  125  and the one or more conductive structures  130 , and to inhibit subsequent doping as described with reference to  FIG. 1F . As one example, spacers  135  may be formed by performing a blanket deposition of dielectric material over the structure of  FIG. 1C , followed by an anisotropic removal (e.g., anisotropic reactive ion etch removal) of the dielectric material from the horizontal surfaces. 
     In  FIG. 1E , portions of the dielectric  105  are removed to define the gate dielectric  140  of the future transistor. In  FIG. 1F , source/drain regions  150  are formed. Source/drain regions  150  have the same conductivity type as the body  120 , but at a higher level of doping. For one embodiment, the source/drain regions  150  are formed through implantation of a dopant species, depicted by arrows  145 . The dopant species  145  and power of the implantation for the source/drain regions  150  should be chosen such that the dopant species  145  does not penetrate into the body  120  below the control gate  125 , the conductive structures  130  or the spacers  135 . In general, breakdown voltage of the future transistor can be improved by providing a doped region between the control gate  125  and the source/drain regions  150  having a conductivity level less than the source/drain regions  150 . The use of the conductive structures  130  and spacers  135  can serve to limit the amount of dopant species  145  entering the body  120 , thereby maintaining this portion of the body  120  at a conductivity level less than the source/drain regions  150 . 
     In  FIG. 1G , bulk dielectric  155  is formed over the structure of  FIG. 1F . Bulk dielectric  155  generally is formed of one or more dielectric materials. For one embodiment, bulk dielectric  155  is a doped silicon oxide material, such as borophosphosilicate glass (BPSG), a boron- and phosphorous-doped silicon dioxide material. 
     Contacts  160 , including one or more conductive materials, are formed to be in electrical contact with the source/drain regions  150  through the bulk dielectric  155 . For example, vias may be formed in the bulk dielectric  155  to expose portions of the source/drain regions  150 , and then the vias may be filled with conductive material. For one embodiment, the contacts  160  contain a metal-containing material. For a further embodiment, the contacts  160  include a metal-containing material over polysilicon, e.g., a refractory metal silicide formed on a conductively-doped polysilicon. For another embodiment, the contacts  160  contain multiple metal-containing materials, e.g., a titanium nitride (TiN) barrier over the source/drain region  150 , titanium (Ti) as an adhesion material over the barrier, and tungsten (W) over the adhesion material. Although not shown in the figures, one or more contacts may be formed to be in electrical contact with the control gate  125  for application of gate potentials. 
     The portion of the body  120  between the control gate  125  and a source/drain region  150  defines a drain extension region  165 . The resulting structure of  FIG. 1G  is a depletion mode field-effect transistor. The drain extension region  165  generally having a conductivity level less than the conductivity level of its associated source/drain region  150  facilitates improvement in the breakdown voltage of the transistor. 
     For one or more embodiments, the conductive structures  130  are not only isolated from the control gate  125 , but are also electrically floating. For one or more alternative embodiments, one or more of the conductive structures  130  may be configured to receive a bias potential to act as a field plate of the transistor. In this manner, the effective conductivity level of the drain extension region  165  can be altered through the application of a particular bias to change the characteristics of the transistor after fabrication. For example, one or more contacts could be formed to one or more of the conductive structures  130  in a manner similar to (e.g., in the same manner as) the formation of contacts  160  to receive the bias potential. Each conductive structure  130  may be configured to receive the same bias potential, or they may receive independent bias potentials. Similarly, one or more of the conductive structures  130  may be electrically floating while one or more other conductive structures  130  are configured to receive a bias potential. 
     While the transistor of  FIG. 1G  is depicted to be symmetrical, the device need not be. For example, the conductive structure  130  on one side of the control gate  125  may be a different width (i.e., larger or smaller) than the conductive structure  130  on the other side of the control gate  125 , or it may be eliminated entirely. Similarly, the distance between the control gate  125  and the source/drain region  150  on one side of the control gate  125  may be different (i.e., longer or shorter) than the distance between the control gate  125  and the source/drain region  150  on the other side of the control gate. 
     Even for embodiments where one or more of the conductive structures  130  are electrically floating, inherent capacitive coupling between a particular conductive structure  130  and adjacent biased structures, such as the control gate  125 , a contact  160  or another conductive structure, may induce a potential on that particular conductive structure  130 . This could, in turn, result in capacitive coupling between the particular conductive structure  130  and a drain extension region  165 , thereby altering the effective conductivity level of that drain extension region  165 . To reduce such an effect, additional conductive structures  130  could be utilized, i.e., more than one conductive structure  130  between the control gate  125  and one of the source/drain regions  150 . 
       FIG. 2A  is a top view of a transistor in accordance with another embodiment of the disclosure.  FIG. 2B  is a cross-sectional view of the transistor of  FIG. 2A  taken along line  2 B- 2 B′ of  FIG. 2A . In the example of  FIGS. 2A-2B , more than one conductive structure  130  is formed between the control gate  125  and the source/drain regions  150 . Formation of the structure of  FIGS. 2A-2B  will be apparent from the fabrication described with reference to  FIGS. 1A-1G . In particular, for the example depicted in  FIGS. 2A-2B , the conductor  110  would be patterned to define more than one conductive structure  130  on each side of the control gate  125 , while the rest of the processing could remain the same. By utilizing additional conductive structures  130  over a drain extension region  165 , capacitive coupling effects can be reduced because the voltage drop between adjacent structures would be reduced compared to using a single conductive structure  130  between the control gate  125  and a contact  160 . In addition, for embodiments where one or more conductive structures  130  are configured to receive a bias potential, the use of additional conductive structures  130  can provide more flexibility for altering the characteristics of the transistor. Note that  FIG. 2A  depicts one or more conductive structures  130  configured to receive a bias potential, such as through contacts  161 . Note further that not all conductive structures  130  of this example embodiment are configured to receive a bias potential. Contacts  161  may each be coupled to receive the same bias potential, or one or more contacts  161  may be coupled to receive a different bias potential than one or more other contacts  161 . 
     While prior embodiments utilized spacers  135  to block dopant species  145  from penetrating into the body  120 , alternate embodiments may eliminate the spacers  135 .  FIGS. 3A and 3B  provide an example of such an embodiment.  FIG. 3A  is a top view of a transistor in accordance with such an embodiment of the disclosure.  FIG. 3B  is a cross-sectional view of the transistor of  FIG. 3A  taken along line  3 B- 3 B′ of  FIG. 3A . In the example of  FIGS. 3A-3B , processing could proceed as described with reference to  FIGS. 2A-2B , except that the processing described with reference to  FIG. 1D  could be eliminated such that spacers  135  are not formed. Even though spacers  135  are not present in the example embodiment of  FIGS. 3A-3B , penetration of dopant species  145  into the body  120  could be inhibited by selecting an angle of the implantation of the dopant species  145  such that the dopant species  145  would be blocked from reaching the body  120  by sidewalls of the control gate  125  or conductive structures  130 . 
     Alternatively, as represented in the example of  FIGS. 3A-3B , the angle of the implantation of the dopant species  145  could be selected to permit at least some of the dopant species  145  to reach the body  120 , thereby forming doped regions in the body  120 , referred to herein as conductive stripes  170 . The conductive stripes  170  have the same conductivity type as the source/drain regions  150 . For some embodiments, the conductive stripes  170  have the same conductivity level as the source/drain regions  150 . For other embodiments, the conductive stripes  170  have a conductivity level equal to or greater than the body  120 , and equal to or less than the source/drain regions  150 . In general, as the angle of implantation of the dopant species  145  becomes steeper, i.e., as the angle of implantation approaches an angle perpendicular to the upper surface of the semiconductor  100 , the resulting conductivity level of the conductive stripes  170  becomes closer to the resulting conductivity level of the source/drain regions  150 . This ability to alter the angle of implantation of the dopant species  145 , with embodiments lacking spacers  135 , provides additional control over the resulting characteristics of the transistor. Note that there may be one more conductive stripe  170  between the control gate  125  and a source/drain region  150  than there are conductive structures  130  between the control gate  125  and that source/drain region  150 , and that a conductive stripe  170  may merge with the source/drain region  150 . Although not shown in  FIG. 3B , it is noted that spacers  135  could alternatively be formed after formation of the conductive stripes  170 . It is also noted that conductive stripes  170  could also be formed in embodiments having spacers  135  by separating the conductive structures  130  and/or control gate  125  by a sufficient distance (e.g., greater than two times a thickness of the spacers  135 ) such that the anisotropic removal during formation of spacers  135  (see discussion of  FIG. 1D ) would expose a portion of the gate dielectric  140  between the control gate  125  and one or more adjacent conductive structures  130 , and/or between adjacent conductive structures  130 , while leaving spacers  135  on the sidewalls of these elements. 
     While embodiments depicted in previous figures have used substantially equal (e.g., equal) spacing of the conductive structures  130 , one or more embodiments can utilize spacing that varies between the control gate  125  and a source/drain region  150 .  FIGS. 4A-4B  depict an embodiment using unequal spacing of conductive structures  130 .  FIG. 4A  is a top view of a transistor in accordance with such an embodiment of the disclosure.  FIG. 4B  is a cross-sectional view of the transistor of  FIG. 4A  taken along line  4 B- 4 B′ of  FIG. 4A . In the example of  FIGS. 4A-4B , processing could proceed as described with reference to  FIGS. 3A-3B  with the exception of changing the pattern of the conductive structures  130 . 
     As shown in  FIG. 4A , the spacing  175  of an adjacent pair of conductive structures  130  is different (e.g., smaller in this example) than the spacing  180  of another adjacent pair of conductive structures  130 . As used herein, the term spacing shall refer to a center-to-center distance. Thus, different spacing can be achieved by using conductive structures  130  of different widths with equal distance between sidewalls of adjacent conductive structures  130  (e.g., as depicted in  FIGS. 4A-4B ), by using conductive structures  130  of equal widths with different distance between sidewalls of adjacent conductive structures  130  (e.g., as depicted in  FIGS. 5A-5B ), or by using some combination thereof. 
     It is believed that higher effective conductivity levels near the source/drain regions and lower effective conductivity levels near the control gate  125  will lead to improved operational characteristics of the transistor, such as higher breakdown voltages for example. While this can be achieved by applying lower biases to conductive structures  130  near the control gate  125  and higher biases to conductive structures  130  near a source/drain region, this can also be achieved by having tighter spacing of conductive stripes  170  as you approach a source/drain region  150 . As shown in  FIGS. 4A-4B , spacing  176  between two adjacent conductive stripes  170  nearer the source/drain region  150  is less than the spacing  181  between another two adjacent conductive stripes  170  nearer the control gate  125 . The embodiment depicted in  FIGS. 4A-4B  accomplishes this by reducing the spacing of conductive structures  130  nearer the source/drain regions  150 , e.g., spacing  175  is less than spacing  180 . 
     As noted above,  FIGS. 5A-5B  depict another embodiment using unequal spacing of conductive structures  130 . While the example of  FIGS. 4A-4B  depicted tighter spacing of conductive stripes  170  nearer the source/drain regions  150 , the example of  FIG. 5A-5B  achieves a higher effective conductivity level nearer the source/drain regions  150  by using conductive structures  130  of substantially equal (e.g., equal) width with greater distance between sidewalls of adjacent conductive structures  130  nearer the source/drain regions (e.g., spacing  185  may be greater than spacing  190  in this example). The result, as depicted in  FIG. 5B  can be larger (i.e., wider) conductive stripes  170  nearer the source/drain regions  150 . As further depicted in  FIG. 5B , spacing  186  between two adjacent conductive stripes  170  nearer the source/drain region  150  may be greater than the spacing  191  between another two adjacent conductive stripes  170  nearer the control gate  125 . However, due to the wider conductive stripes  170  nearer the source/drain regions  150 , higher effective conductivity levels may still be obtained. 
     The examples as described with reference to  FIGS. 1A-5B  have shown a variety of alternative structures. However, the depicted examples were not meant to be exhaustive. For example, conductive structures  130  on one side of the control gate  125  may be configured to receive a bias potential while conductive structures  130  on the other side of the control gate  125  may be electrically floating, whether or not conductive stripes  170  are utilized. For another example, unequal spacing of conductive structures  130  on one side of the control gate  125  may utilize conductive structures  130  of different widths with equal distance between sidewalls of adjacent conductive structures  130  while unequal spacing of conductive structures  130  on the other side of the control gate  125  may utilize conductive structures  130  of equal widths with different distances between sidewalls of adjacent conductive structures  130 . As a further example, spacing of conductive structures  130  can increase nearer the control gate  125 . Other combinations of elements of depicted embodiments will be apparent to one skilled in the art. 
     It is also noted that while specific materials were described with reference to  FIGS. 1A-5B , the embodiments are not limited to the example materials. Furthermore, additional layers may be also utilized in various embodiments beyond those described, such as barrier layers to inhibit diffusion between opposing layers, or adhesion layers to promote adhesion between opposing layers. 
     CONCLUSION 
     Transistors having a dielectric over a semiconductor, a control gate over the dielectric at a particular level, and one or more conductive structures over the dielectric at the particular level have been described. The one or more conductive structures can facilitate control of device characteristics of the transistor, by receiving a bias potential to act as a field plate during operation of the transistor, by acting as a mask to fully or partially inhibit penetration of a dopant species into a body of the transistor, or some combination thereof. The one or more conductive structures are between the control gate and at least one source/drain region of the transistor. The one or more conductive structures are electrically isolated from the control gate. 
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the embodiments will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the embodiments.