Patent Publication Number: US-11024724-B2

Title: Vertical FET with differential top spacer

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. application Ser. No. 15/960,078 filed on Apr. 23, 2018, now U.S. Pat. No. 10,559,676, the contents of which are incorporated by reference herein. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to vertical transport field effect transistors (VTFETs), and more particularly, to VTFETs having a differential top spacer. 
     BACKGROUND OF THE INVENTION 
     As opposed to planar complementary metal-oxide-semiconductor (CMOS) devices, vertical transport field effect transistors (VTFETs) are oriented with a vertical fin channel disposed on bottom source and drains and a top source and drain disposed on the vertical fin channel. A gate runs vertically alongside the vertical fin channel. 
     A replacement metal gate process for FETs is beneficial as it permits gate metal workfunction customization and tuning. However, there are notable challenges associated with a replacement metal gate process and the VTFET design. Namely, the device is built from the bottom up, with the top source and drains being grown in top of the channel after the gate has been formed. The elevated temperatures (e.g., exceeding 600° C.) associated with the top source and drain formation can degrade a conventional replacement metal gate. For instance, at temperatures greater than or equal to about 600° C., conventional n-channel VTFET designs undesirably experience a dramatic increase in leakage current while p-channel VTFET designs undesirably experience a threshold voltage (Vt) increase. 
     Therefore, thermally stable replacement metal gate stack designs for a VTFET architecture would be desirable. 
     SUMMARY OF THE INVENTION 
     The present invention provides vertical transport field effect transistor (VTFET) devices having a differential top spacer. In one aspect of the invention, a method of forming a VTFET device is provided. The method includes: patterning fins in a wafer, the fins including n-channel FET (NFET) fins and p-channel FET (PFET) fins; forming bottom source and drains at a base of the NFET fins and the PFET fins; forming bottom spacers on the bottom source and drains; forming gate stacks alongside the NFET fins and the PFET fins, wherein the gate stacks formed alongside the NFET fins and the PFET fins include a same workfunction metal on top of a gate dielectric; annealing the gate stacks which generates oxygen vacancies in the gate dielectric; depositing a gate fill metal over the NFET fins, the PFET fins and the gate stacks; forming top spacers over the gate stacks at tops of the NFET fins and the PFET fins, wherein the top spacers include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and forming top source and drains above the gate stacks at the tops of the NFET fins and the PFET fins. 
     In another aspect of the invention, a VTFET device is provided. The VTFET device includes: fins patterned in a wafer, the fins including NFET fins and PFET fins; bottom source and drains at a base of the NFET fins and the PFET fins; bottom spacers disposed on the bottom source and drains; gate stacks alongside the NFET fins and the PFET fins, wherein the gate stacks alongside the NFET fins and the PFET fins include a same workfunction metal disposed on top of a gate dielectric; a gate fill metal disposed over the NFET fins, the PFET fins and the gate stacks; top spacers disposed over the gate stacks at tops of the NFET fins and the PFET fins, wherein the top spacers include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins; and top source and drains above the gate stacks at the tops of the NFET fins and the PFET fins. 
     A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a cross-sectional diagram illustrating a plurality of fin hardmasks having been formed on a wafer marking the footprint and location of a plurality of n-channel field effect transistor (NFET) fins according to an embodiment of the present invention; 
         FIG. 1B  is a cross-sectional diagram illustrating a plurality of fin hardmasks having been formed on a wafer marking the footprint and location of a plurality of p-channel field effect transistor (PFET) fins according to an embodiment of the present invention; 
         FIG. 2A  is a cross-sectional diagram illustrating the fin hardmasks having been used to pattern NFET fins in the wafer according to an embodiment of the present invention; 
         FIG. 2B  is a cross-sectional diagram illustrating the fin hardmasks having been used to pattern PFET fins in the wafer according to an embodiment of the present invention; 
         FIG. 3A  is a cross-sectional diagram illustrating NFET bottom source and drains having been formed in the wafer at the base of the NFET fins, shallow trench isolation (STI) regions having been formed in the wafer to isolate the NFET bottom source and drains, and bottom spacers having been formed on the NFET bottom source and drains according to an embodiment of the present invention; 
         FIG. 3B  is a cross-sectional diagram illustrating PFET bottom source and drains having been formed in the wafer at the base of the PFET fins, STI regions having been formed in the wafer to isolate the PFET bottom source and drains, and bottom spacers having been formed on the PFET bottom source and drains according to an embodiment of the present invention; 
         FIG. 4A  is a cross-sectional diagram illustrating gate stacks having been formed alongside the NFET fins, the gate stacks including an interfacial layer, a high-κ gate dielectric and a workfunction metal according to an embodiment of the present invention; 
         FIG. 4B  is a cross-sectional diagram illustrating the gate stacks having been formed alongside the PFET fins according to an embodiment of the present invention; 
         FIG. 5A  is a cross-sectional diagram illustrating the (NFET) gate stacks having been buried in a dummy gate material according to an embodiment of the present invention; 
         FIG. 5B  is a cross-sectional diagram illustrating the (PFET) gate stacks having been buried in a dummy gate material according to an embodiment of the present invention; 
         FIG. 6A  is a cross-sectional diagram illustrating an anneal of the (NFET) gate stacks having been performed according to an embodiment of the present invention; 
         FIG. 6B  is a cross-sectional diagram illustrating an anneal of the (PFET) gate stacks having been performed according to an embodiment of the present invention; 
         FIG. 7A  is a cross-sectional diagram illustrating the dummy gate material having been selectively removed from over the NFET gate stacks and replaced with a gate fill metal according to an embodiment of the present invention; 
         FIG. 7B  is a cross-sectional diagram illustrating the dummy gate material having been selectively removed from over the PFET gate stacks and replaced with a gate fill metal according to an embodiment of the present invention; 
         FIG. 8A  is a cross-sectional diagram illustrating the gate fill metal having been recessed alongside the NFET gate stacks according to an embodiment of the present invention; 
         FIG. 8B  is a cross-sectional diagram illustrating the gate fill metal having been recessed alongside the PFET gate stacks according to an embodiment of the present invention; 
         FIG. 9A  is a cross-sectional diagram illustrating the workfunction metal having been recessed alongside the NFET gate stacks according to an embodiment of the present invention; 
         FIG. 9B  is a cross-sectional diagram illustrating the workfunction metal having been recessed alongside the PFET gate stacks according to an embodiment of the present invention; 
         FIG. 10A  is a cross-sectional diagram illustrating the high-κ gate dielectric having been recessed alongside the NFET gate stacks according to an embodiment of the present invention; 
         FIG. 10B  is a cross-sectional diagram illustrating the high-κ gate dielectric having been recessed alongside the PFET gate stacks according to an embodiment of the present invention; 
         FIG. 11A  is a cross-sectional diagram illustrating a first nitride spacer layer having been deposited over the NFET gate stacks according to an embodiment of the present invention; 
         FIG. 11B  is a cross-sectional diagram illustrating the first nitride spacer layer having been deposited over the PFET gate stacks according to an embodiment of the present invention; 
         FIG. 12A  is a cross-sectional diagram illustrating a block mask having been formed covering the first nitride spacer layer over the NFET gate stacks according to an embodiment of the present invention; 
         FIG. 12B  is a cross-sectional diagram illustrating the first nitride spacer layer having been removed from the PFET gate stacks according to an embodiment of the present invention; 
         FIG. 13A  is a cross-sectional diagram illustrating an oxide spacer layer having been deposited onto the first nitride spacer layer over the NFET gate stacks, and a second nitride spacer layer having been deposited onto the oxide spacer layer according to an embodiment of the present invention; 
         FIG. 13B  is a cross-sectional diagram illustrating the oxide spacer layer having been deposited onto the PFET gate stacks, and the second nitride spacer layer having been deposited onto the oxide spacer layer according to an embodiment of the present invention; 
         FIG. 14A  is a cross-sectional diagram illustrating the first nitride spacer layer, the oxide spacer layer and the second nitride spacer layer having been patterned into individual spacers at the tops of the NFET fins according to an embodiment of the present invention; 
         FIG. 14B  is a cross-sectional diagram illustrating the oxide spacer layer and the second nitride spacer layer having been patterned into individual spacers at the tops of the PFET fins according to an embodiment of the present invention; 
         FIG. 15A  is a cross-sectional diagram illustrating the NFET fins having been buried in an interlayer dielectric (ILD) that is then polished down to the fin hardmasks according to an embodiment of the present invention; 
         FIG. 15B  is a cross-sectional diagram illustrating the PFET fins having been buried in the ILD that is then polished down to the fin hardmasks according to an embodiment of the present invention; 
         FIG. 16A  is a cross-sectional diagram illustrating the fin hardmasks having been removed forming trenches in the ILD between the individual spacers over the NFET fins according to an embodiment of the present invention; 
         FIG. 16B  is a cross-sectional diagram illustrating the fin hardmasks having been removed forming trenches in the ILD between the individual spacers over the PFET fins according to an embodiment of the present invention; 
         FIG. 17A  is a cross-sectional diagram illustrating top source and drains having been formed in the trenches at the tops of the NFET fins according to an embodiment of the present invention; 
         FIG. 17B  is a cross-sectional diagram illustrating top source and drains having been formed in the trenches at the tops of the PFET fins according to an embodiment of the present invention; and 
         FIG. 18  is a diagram illustrating performance of samples prepared according to the present techniques after being subjected to a high temperature anneal according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     As provided above, a significant challenge to successfully implementing a replacement metal gate process for vertical transport field-effect transistor (VTFET) designs is the large thermal budget associated with the top source and drain growth post formation of the replacement metal gate. Namely, significant degradation of the replacement metal gate occurs at the elevated temperatures employed during formation of the top source and drains, which can exceed 600 degrees Celsius (° C.). 
     Advantageously, provided herein are thermally stable VTFET designs and process for formation thereof. The present techniques apply several novel aspects to VTFET fabrication. First, thermal stability can be achieved when workfunction-setting gate metals such as titanium nitride (TiN) and tantalum nitride (TaN) above a critical physical thickness (T CRIT ) are placed on top of high-κ gate dielectrics such as hafnium (Hf)- or zirconium (Zr)-based high-κ gate dielectrics even when subjected to temperatures exceeding 900° C. According to an exemplary embodiment, T CRIT  is about 3.0 nanometers (nm). The term “high-κ” as used herein refers to a material having a relative dielectric constant κ which is much higher than that of silicon dioxide (e.g., a dielectric constant κ=20 for hafnium oxide (HfO 2 ) rather than 4 for silicon dioxide (SiO 2 )). 
     Second, the workfunction can be set using different top spacer configurations for n-channel VTFET (NFET) and p-channel VTFET (PFET) devices. This notion advantageously permits the same workfunction metal (e.g., TiN or TaN) to be employed in both NFET and PFET devices, simplifying the present fabrication process (i.e., by concurrently depositing the same workfunction metal for both NFETs and PFETs) as compared to conventional process flows requiring the selective placement of different workfunction metals in NFET versus PFET devices. 
     Leveraging these unique aspects, an exemplary methodology for forming a VTFET device is now described. The process begins with the patterning of a plurality of fins in a wafer. To do so, standard lithography and etching techniques are used to pattern a plurality of fin hardmasks  102  on a wafer  104 . See  FIG. 1A  (NFET) and  FIG. 1B  (PFET). The fin hardmasks mark the footprint and location of a plurality of (NFET and PFET) fins to be patterned in the wafer. See below. Suitable materials for the fin hardmasks  102  include, but are not limited to, silicon nitride (SiN). 
     The steps involved in forming NFET and PFET devices on a common wafer will be described by way of reference to figures designated as A and B, respectively. For instance, what is shown in  FIG. 1A  applies to the NFET devices and what is shown in  FIG. 1B  applies to the PFET devices. The NFET and PFET process flows are illustrated in separate figures (e.g.,  FIG. 1A  and  FIG. 1B , respectively) merely for ease and clarity of depiction. However, it is to be understood that these processes can be performed on the same (common) wafer if so desired, with one or more of the steps being performed in both the NFET and PFET devices concurrently—as indicated below. 
     A variety of different wafer  104  configurations can be implemented in accordance with the present techniques. For instance, according to one exemplary embodiment, the starting wafer  104  is a bulk semiconductor wafer, such as a bulk silicon (Si), bulk germanium (Ge), bulk silicon germanium (SiGe) and/or bulk III-V semiconductor wafer. Alternatively, wafer  104  can be a semiconductor-on-insulator (SOI) wafer. A SOI wafer includes a SOI layer separated from an underlying substrate by a buried insulator. When the buried insulator is an oxide it is referred to herein as a buried oxide or BOX. The SOI layer can include any suitable semiconductor, such as Si, Ge, SiGe, and/or a III-V semiconductor. 
     The fin patterning can be performed concurrently for both NFET and PFET devices on the wafer  104 . Namely, as shown in  FIG. 2A  and  FIG. 2B , respectively, the fin hardmasks  102  are used to etch (NFET) fins  202   a  and (PFET) fins  202   b  concurrently in the wafer  104 . A directional (anisotropic) etching process such as reactive ion etching (RIE) can be used for the fin etch. 
     Bottom source and drains  302  (NFET) and bottom source and drains  304  (PFET) are then formed in the wafer  104  at the base of the fins  202   a  and  202   b , respectively. See  FIG. 3A  and  FIG. 3B , respectively. According to an exemplary embodiment, the bottom source and drains  302  and  304  are formed using an ion implantation process whereby an n-type dopant(s) (for NFET devices) or p-type dopant(s) (for PFET devices) is/are implanted into the wafer  104  at the base of the fins  202   a  and  202   b , respectively. Suitable n-type dopants include, but are not limited to, phosphorous (P) and/or arsenic (As), and suitable p-type dopants include, but are not limited to, boron (B). Alternatively, the bottom source and drains  302  and  304  are formed by growing an in-situ (during epitaxial growth) or ex-situ (via ion implantation) doped epitaxial material at the base of the fins  202   a  and  202   b . By way of example only, phosphorus-doped Si (Si:P) may be grown for the NFET devices and boron-doped SiGe (SiGe:B) may be grown for the PFET devices. 
     Shallow trench isolation (STI) regions  306  are then formed in the wafer  104  to isolate the bottom source and drains  302  and  304  of the NFET and PFET devices, respectively. See  FIG. 3A  and  FIG. 3B . The formation of STI regions  306  can be performed concurrently for the NFET and PFET devices. STI involves first patterning (STI) trenches in the wafer  104 , and then filling the trenches with an insulator such as an oxide (also referred to herein as an “STI oxide”). As shown in  FIG. 3A  and  FIG. 3B , the STI regions  306  extend through the bottom source and drains  302  and  304  and into the wafer  104 . 
     Bottom spacers  308   a  and  308   b  are next formed on the bottom source and drains  302  and  304 , respectively. The formation of the bottom spacers  308   a  and  308   b  can be performed concurrently for the NFET and PFET devices. Suitable materials for bottom spacers  308   a  and  308   b  include, but are not limited to, oxide spacer materials such as SiO 2  and/or silicon oxycarbide (SiOC) and/or nitride spacer materials such as silicon nitride (SiN) and/or silicon-boron-nitride (SiBN). 
     According to an exemplary embodiment, the bottom spacers  308   a  and  308   b  are formed using a directional deposition process whereby the spacer material is deposited onto the bottom source and drains  302 / 304 , fin hardmasks  102 , and fins  202   a / 202   b  with a greater amount of the material being deposited on horizontal surfaces (including on top of the bottom source and drains  302 / 304  in between the fins  202   a / 202   b , respectively), as compared to vertical surfaces (such as along sidewalls of the fins  202   a / 202   b ). Thus, when an etch is used on the spacer material, the timing of the etch needed to remove the spacer material from the vertical surfaces will leave the bottom spacers  308   a  and  308   b  shown in  FIG. 3A  and  FIG. 3B  on the bottom source and drains  302  and  304 , respectively since a greater amount of the spacer material was deposited on the bottom source and drains  302  and  304 . By way of example only, a high-density plasma (HDP) chemical vapor deposition (CVD) or physical vapor deposition (PVD) process can be used for directional film deposition, and an oxide- or nitride-selective (depending on the spacer material) isotropic etch can be used to remove the (thinner) spacer material deposited onto the vertical surfaces. 
     Gate stacks are next formed alongside the fins  202   a / 202   b  over the bottom spacers  308   a  and  308   b . According to an exemplary embodiment, the gate stacks include an interfacial layer (IL), a high-κ gate dielectric over the IL layer, and a workfunction metal over the high-κ gate dielectric. Advantageously, as provided above, the gate workfunction will be set for the NFET and PFET devices using a unique top spacer design. Accordingly, the same gate stack materials can be employed in both the NFET and PFET devices. Thus, according to an exemplary embodiment, the formation of gate stacks is performed concurrently for the NFET and PFET devices. 
     Specifically, referring first to insets  401   a  and  401   b  in  FIG. 4A  and  FIG. 4B  (which provide magnified views of the gate stacks), an IL  402  is formed on the exposed fins  202   a / 202   b . According to an exemplary embodiment, IL  402  (e.g., SiO 2  which may include other chemical elements in it such as nitrogen, germanium, etc.) is formed by an oxidation process to a thickness of from about 0.3 nm to about 5 nm, and ranges therebetween, e.g., about 1 nm. A high-κ gate dielectric  404  is then deposited onto the IL  402  using a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Suitable high-κ gate dielectrics include, but are not limited to, Hf-based and/or Zr-based dielectric materials such as HfO 2  and/or zirconium oxide (ZrO 2 ). A workfunction metal  406  is then deposited on top of the high-κ gate dielectric  404  using a conformal deposition process such as CVD or ALD. Suitable workfunction metals include, but are not limited to, TiN and/or TaN. As provided above, the workfunction metal  406  needs to be deposited to a physical thickness T that is greater than a critical thickness T CRIT  (i.e., T&gt;T CRIT ). According to an exemplary embodiment, T CRIT  is about 3.0 nm, and T is greater than about 3.0 nm, e.g., from about 3.5 nm to about 5.0 nm, and ranges therebetween. Use of the workfunction metal  406  at this thickness T imparts thermal stability to the design. See, for example, Ando et al., “Simple Gate Metal Anneal (SIGMA) Stack for FinFET Replacement Metal Gate Toward 14 nm and beyond,” 2014 Symposium on VLSI Technology Digest of Technical Papers June 2014 (2 total pages) (hereinafter “Ando”), the contents of which are incorporated by reference as if fully set forth herein. As described in Ando, it is thought that positively charged oxygen vacancies are generated in the underlying gate dielectric during the subsequent workfunction metal anneal (see below). If the workfunction metal is below T CRIT  then, over time and exposure to air, passivation of these positively charged oxygen vacancies occurs which shifts the effective workfunction (EWF). However, if the workfunction metal is thicker, i.e., greater than T CRIT , then this passivation does not occur (because the thicker workfunction metal prevents air exposure) and the EWF remains stable. 
     The fins  202   a / 202   b  and gate stacks are then buried in a dummy gate material  502 . See  FIG. 5A  and  FIG. 5B , respectively. The dummy gate material  502  serves to protect the workfunction metal  406  from oxidation during the subsequent anneal process. Suitable dummy gate materials include, but are not limited to, amorphous silicon (a-Si) and/or poly-silicon (poly-Si). The dummy gate material  502  can be blanket deposited over the fins  202   a / 202   b  and gate stacks using a process such as CVD. The dummy gate material  502  can be deposited concurrently for the NFET and PFET devices. 
     With the dummy gate material  502  in place, a reliability anneal of the gate stacks is then concurrently performed for the NFET and PFET devices. See  FIGS. 6A and 6B , respectively. The anneal serves to set the effective workfunction of the gate stack to the range appropriate for NFET and to improve the reliability. According to an exemplary embodiment, the anneal is performed at a temperature of greater than about 900° C., e.g., from about 900° C. to about 1000° C. and ranges therebetween. 
     Following the anneal, the dummy gate material  502  is selectively removed (e.g., using a Si-selective etching process) and replaced with a gate fill metal  702  that is deposited over the fins  202   a / 202   b  and gate stacks, e.g., using a process such as CVD or plating. See  FIG. 7A  and  FIG. 7B , respectively. The same gate fill metal  702  is used in both NFET and PFET devices. Thus, the dummy gate material  502  removal and gate fill metal  702  deposition can be performed concurrently for the NFET and PFET devices. Suitable gate fill metals include, but are not limited to, tungsten (W), copper (Cu) and/or aluminum (Al). The gate fill metal  702  is an additional component of the gate stacks (i.e., the gate stacks include high-κ gate dielectric  404 /workfunction metal  406 /gate fill metal  702 ). 
     As shown in  FIG. 7A  and  FIG. 7B , any overfill of the gate fill metal  702  can be removed using chemical-mechanical polishing (CMP). Based on the polish selectivity between the gate metals, a CMP of the gate fill metal  702  can also remove the workfunction metal  406  from the tops of the gate stacks over the fins  202   a / 202   b . This is inconsequential since the gate stacks will next be recessed for top differential spacer formation. 
     According to an exemplary embodiment, recessing of the gate stacks is accomplished concurrently in the NFET and PFET devices as follows. First, an etch is used to recess the gate fill metal  702  below the level of fin hardmasks  102  on fins  202   a / 202   b . See  FIG. 8A  and  FIG. 8B , respectively. This etch of the gate fill metal  702  is selective to the high-κ gate dielectric  404 /workfunction metal  406 . During the selective gate fill metal  702  etch, the fin hardmasks  102  remain protected by the high-κ gate dielectric  404 /workfunction metal  406 . 
     The depth of the gate fill metal  702  sets the overall depth for the gate stack recess. Namely, an etch is then used to recess the workfunction metal  406  to the depth set by the (recessed) gate fill metal  702  concurrently in the NFET and PFET devices. See  FIG. 9A  and  FIG. 9B , respectively. This recess etch of the workfunction metal  406  is selective to the high-κ gate dielectric  404 . According to an exemplary embodiment, a directional etching process such as RIE is employed for the workfunction metal  406  recess. As provided above, the workfunction metal  406  can include a metal nitride (e.g., TiN and/or TaN), while the high-x gate dielectric  404  can include an oxide material (e.g., HfO 2  and/or ZrO 2 ). Thus, a nitride-selective RIE would provide etch selectivity vis-à-vis the high-κ gate dielectric  404 . 
     Finally, an etch is then used to recess the IL/high-κ gate dielectric  404  concurrently in the NFET and PFET devices. See  FIG. 10A  and  FIG. 10B , respectively. According to an exemplary embodiment, a non-directional (i.e., isotropic) etching process such as a wet etching process is employed for the IL/high-κ gate dielectric  404  recess. A wet etch will remove the exposed IL and high-κ gate dielectric  404  down to the level of the (recessed) workfunction metal  406 /gate fill metal  702 . 
     It is notable that, based on the above-described process, the ends of the (recessed) high-κ gate dielectric  404  are now exposed at the tops of the fins  202   a / 202   b . As will become apparent from the description that follows, this aspect is important since an oxygen source will be provided (by way of differential top spacers) to selectively tune the workfunction of the PFET devices by introducing oxygen to fill the vacancies in the high-κ gate dielectric  404  (see above). 
     By ‘differential’ it is meant that the top spacers formed on the NFET devices are different from the top spacers formed on the PFET devices, and vice versa. Specifically, nitride/oxide/nitride spacers will be formed on the NFET devices, whereas oxide/nitride spacers will be formed on the PFET devices. This differential top spacer configuration enables the oxide component of the spacers to serve as an oxygen source for the PFET devices, while the first nitride component (present only in the NFET devices) shields the NFET devices from this oxygen source. For a general discussion of an oxygen supply from an oxide spacer for modulating PFET workfunction see, for example, Kim et al., “Novel Single Metal Gate CMOS Integration with Effective Workfunction Modulation by a Differential Spacer: Manipulation of Oxygen Vacancy,” 2009 International Conference on Solid State Devices and Materials, (October 2009) (2 total pages) (hereinafter “Kim”), the contents of which are incorporated by reference as if fully set forth herein. 
     To form the differential top spacers on the NFET and PFET devices, a (first) nitride spacer layer  1102  is deposited concurrently over the gate stacks and fins hardmasks  102  in both the NFET and PFET devices. See  FIG. 11A  and  FIG. 11B , respectively. Suitable materials for the first nitride spacer layer  1102  include, but are not limited to, SiN and/or SiBN. Preferably, the first nitride spacer layer  1102  is deposited using a process such as plasma enhanced chemical vapor deposition (PECVD) or ALD. 
     This first nitride spacer layer  1102  is to remain in the NFET devices (i.e., to shield the NFET gate stacks from the oxide spacer component that is formed next), but be removed from the PFET devices. To do so, the first nitride spacer layer  1102  is selectively masked over the NFET devices (see  FIG. 12A ) and an etch (e.g., a nitride-selective etch) is then used to remove the first nitride spacer layer  1102  from the PFET devices (see  FIG. 12B ). According to an exemplary embodiment, a standard block mask  1202  (see  FIG. 12A ) is used to cover the first nitride spacer layer  1102  over the NFET devices. Following the etch, the block mask  1202  is removed. 
     Concurrent processing of the NFET and PFET devices resumes to complete formation of the differential top spacers. Namely, an oxide spacer layer  1302  is next deposited concurrently over the first nitride spacer layer  1102  in the NFET devices (see  FIG. 13A ) and over the gate stacks and fins hardmasks  102  in the PFET devices (see  FIG. 13B ). Suitable materials for the oxide spacer layer  1302  include, but are not limited to, SiO 2  and/or SiOC. Preferably, the oxide spacer layer  1302  is deposited at a (low) temperature of less than about 400° C., e.g., from about 200° C. to about 400° C. and ranges therebetween, using a process such as PECVD or ALD. As described in Kim, low temperature deposited oxide spacers have a high O—H content which, when released, passivate the oxygen vacancies in the gate dielectric. 
     A (second) nitride spacer layer  1304  is then deposited concurrently over the oxide spacer layer  1302  in the NFET and PFET devices. Suitable materials for the second nitride spacer layer  1304  include, but are not limited to, SiN and/or SiBN. Preferably, the second nitride spacer layer  1304  is deposited using a process such as PECVD or ALD. 
     An etch is then performed, concurrently in the NFET and PFET devices, to pattern the first nitride spacer layer  1102  (only in the NFET devices)/oxide spacer layer  1302 /second nitride spacer layer  1304  into individual spacers at the tops of the fins  202   a / 202   b . See  FIG. 14A  and  FIG. 14B , respectively. A directional etching process such as RIE may be employed for the differential spacer etch. According to an exemplary embodiment, a series of nitride-selective and oxide-selective RIE steps are performed for the differential spacer etch. 
     As shown in  FIG. 14A , the differential spacers at the tops of the NFET fins  202   a  have a nitride/oxide/nitride configuration patterned from the first nitride spacer layer  1102 /oxide spacer layer  1302 /second nitride spacer layer  1304 , respectively. By comparison, as shown in  FIG. 14B , the differential spacers at the tops of the PFET fins  202   a  have an oxide/nitride configuration patterned from the oxide spacer layer  1302 /second nitride spacer layer  1304 , respectively. With regard to the NFET devices, the first nitride spacer layer  1102  shields the NFET gate stacks from the oxide spacer layer  1302 . See  FIG. 14A . However, in the PFET devices the oxide spacer layer  1302  is in direct contact with the high-κ gate dielectric  404 . See  FIG. 14B . The oxide spacer layer  1302  serves as a source for oxygen to fill the vacancies in the high-κ gate dielectric  404 , thus altering the workfunction of the PFET devices (relative to the NFET devices). See Kim. Further, as described in Ando, simply exposing the high-κ gate dielectric  404  to the oxygen source will overtime (e.g., from 0 to 1600 hours) alter the effective workfunction (EWF) of the devices (in this case the PFET devices). See, for example, Ando  FIG. 3 . 
     Top source and drains are then formed to the NFET and PFET devices. To do so, the NFET and PFET fins  202   a / 202   b  are first buried in an interlayer dielectric (ILD)  1502 . See  FIG. 15A  and  FIG. 15B , respectively. Suitable ILD materials include, but are not limited to, oxide dielectric materials such as SiO 2 . Excess ILD  1502  is removed, exposing the tops of the fin hardmasks  102 . A process such as CMP can be employed in this step to polish the ILD  1502  down to the fin hardmasks  102 . The deposition and polishing of the ILD  1502  can be performed concurrently in the NFET and PFET devices. 
     Once exposed, the fin hardmasks  102  are then removed (concurrently) from the NFET and PFET devices. See  FIG. 16A  and  FIG. 16B , respectively. The fin hardmasks  102  can be removed using a nitride-selective etching process such as a nitride-selective RIE. As shown in  FIG. 16A  and  FIG. 16B , removal of the fin hardmasks  102  forms trenches  1602  in between the top spacers over the fins  202   a / 202   b.    
     Top source and drains  1702  and  1704  are then formed in the trenches  1602  at the tops of the fins  202   a / 202   b . See  FIG. 17A  and  FIG. 17B , respectively. According to an exemplary embodiment, the top source and drains  1702  and  1704  are formed by growing an in-situ (during epitaxial growth) or ex-situ (via ion implantation) doped epitaxial material at the tops of the fins  202   a  and  202   b . As provided above, suitable n-type dopants include, but are not limited to, phosphorous (P) and/or arsenic (As), and suitable p-type dopants include, but are not limited to, boron (B). By way of example only, Si:P may be grown for the NFET devices and SiGe:B may be grown for the PFET devices. 
       FIG. 18  is a diagram illustrating gate leakage J g  as a function of inversion thickness T inv  for a reference sample (Ref.) and samples prepared according to the present techniques having a workfunction metal with T&gt;T CRIT  over a high-κ gate dielectric. As shown in  FIG. 18 , a T inv  of 1.25 nm and a J g  1 A/cm 2  (Toxgl 1.55 nm) was maintained after a rapid thermal anneal (RTA) at 970° C., thus indicating no degradation of leakage in the present samples. 
     Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope of the invention.