Patent Publication Number: US-7719304-B1

Title: Radiation hardened master-slave flip-flop

Description:
This application claims the benefit of U.S. provisional application Ser. No. 60/916,753 filed May 8, 2007, the disclosure of which is incorporated herein by reference in its entirety. 
    
    
     GOVERNMENT FUNDING 
     The invention described herein was made with government support under grant number F29601 02-2-299, awarded by the Air Force Research Laboratory. The United States Government has certain rights in the invention. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to latches, and in particular to a radiation hardened master-slave flip-flop. 
     BACKGROUND OF THE INVENTION 
     Electronic circuits, and in particular circuits that involve storing electronic states, are vulnerable to high-energy sub-atomic particles and electromagnetic radiation. Many high-altitude flight, outer space, military, and nuclear applications require that such vulnerability be reduced to an acceptable level. The techniques that are used to reduce the vulnerability of these circuits to the effects of radiation are generally referred to as radiation hardening. For the most part, radiation hardening involves employing special circuit designs, circuit layouts, the use of select materials, or any combination thereof to increase the robustness of the circuit. Long-term radiation effects that may impact the long-term functionality of the circuit are referred to as total ionizing dose (TID) effects and are often mitigated using special circuit layer techniques. 
     Another type of radiation effect that is becoming more of an issue is referred to a single event effect (SEE). When a high-energy particle passes through a semiconductor providing the electronic circuit, excess charge may be left in the semiconductor along the path through which the particle passes. If excess charge is left on or near a node that is charged to a level representing a desired logic state, the excess charge may change the level of charge at the node. The change in charge level may result in the node changing from the desired logic state to another logic state. For example, if an ionized particle of radiation passes through a bi-state storage node that is charged for a logic 1, excess electrons from the ionized particle may collect at the storage node and discharge the storage node to a charge level corresponding to a logic 0. The effect of the change in charge level of the storage node may result in a temporary transient, where the storage node returns to the charge level for a logic 1 and does not upset the overall output of the of the electronic circuit. This type of SEE is referred to as a single event transient (SET). If the effect of the change in charge level of the storage node completely changes the output of the circuit, where the output does not return to the proper state, a single event upset (SEU) is said to occur. Generally, SETs and SEUs are temporary, unlike TID effects, which are more permanent, long-term radiation effects. 
     Latches are frequently used circuits that include storage nodes and benefit from being hardened to radiation. Exemplary radiation hardened latches include the dual interlocked storage cell (DICE) latch and a classic temporal latch. A traditional DICE latch is illustrated in  FIG. 1 . The DICE latch includes two cross-coupled inverter latches formed from PMOS transistors T 1 -T 4  and complementary NMOS transistors T 5 -T 8 . The first cross-coupled inverter latch is formed from transistors T 1 , T 2 , T 5 , and T 6  while the second cross-coupled inverter latch is formed from transistors T 3 , T 4 , T 7 , and T 8 . 
     Notably, node X 0  is formed where transistors T 1  and T 5  are coupled, node X 1  is formed where transistors T 2  and T 6  are coupled, node X 2  is formed when transistors T 3  and T 7  are coupled, and node X 3  is formed where transistors T 4  and T 8  are coupled. Node X 0  is coupled to the gate of transistor T 2  as well as the gate of transistor T 8 . Node X 1  is coupled to the gates of transistors T 5  and T 3 . Node X 2  is coupled to the gates of transistors T 6  and T 4 . Node X 3  is coupled to the gates of transistors T 7  and T 1 , and provides the output Q of the DICE latch. 
     The traditional DICE latch has only two inputs, which are connected to nodes X 0  and X 2 . These two inputs are represented as nodes M 0  and M 1 , which are respectively coupled to nodes X 0  and X 2  through pass transistors T 9  and T 10 . A clock signal, CLKb, controls when the values on nodes M 0  and M 1  are written to nodes X 0  and X 2 . As illustrated, when the clock signal CLKb is asserted low, the values on nodes M 0  and M 1  are written to nodes X 0  and X 2 . 
     Generally, node X 0  is at the same state as node X 2 . Similarly, node X 1  is at the same state as node X 3 , which is the opposite state of nodes X 0  and X 2 . Accordingly, the output Q, which corresponds to node X 3 , is generally the opposite logic state that is stored on nodes X 0  and X 1 . 
     To radiation harden the DICE latch, the nodes X 0 -X 3  must be physically separated from each other to an extent that will prevent any two of the nodes X 0 -X 3  from being hit by a single radiation particle. As such, if one of the nodes X 0 -X 3  is struck by a radiation particle and as a result has its state changed, the remaining nodes X 0 -X 3  will effectively override the state change at the affected node such that the output Q is at most subjected to a transient glitch. The overall state of the DICE latch is not upset. When the affected node X 0 -X 3  changes state in response to being struck by the radiation particle, the remaining nodes X 0 -X 3  will operate to restore the affected node X 0 -X 3  to its proper state. 
     One of the drawbacks of the traditional DICE latch is that it is prone to capturing the wrong logic states if nodes M 0  and M 1  have the wrong logic state when the clock signal CLKb is asserted low and the DICE latch is in a transparent mode. Although the DICE latch is relatively compact and has been proven effective in mitigating SEUs, it is vulnerable to SETs while in a transparent mode. Accordingly, there is a need for a technique to provide radiation hardened DICE latches that are not vulnerable to SETs while in transparent modes. 
     A classic temporal latch is illustrated in  FIG. 2 . The temporal latch employs three redundant feedback paths that are separated in time by intentionally differing delays. As illustrated, the first feedback path corresponds to node N 2 , the second feedback path corresponds to the delay circuit D 1  and node MDb, and the third feedback path corresponds to delay circuits D 2  and D 3  as well as node MDDb. The delay circuits D 1 , D 2 , and D 3  each provide a fixed delay δ. Those skilled in the art will recognize that the delays provided by each of the delay circuits D 1 , D 2 , and D 3  may be different from one another, but for the purposes of illustration they are assumed to each provide the same delay δ. 
     The inputs to the temporal latch are a data input D and a clock signal CLK. The data input D is passed through a pass gate formed by transistors T 11  and T 12  to a node N 1 . The logic state of node N 1  is inverted by an inverter I 1  and presented to the beginning of each of the three redundant feedback paths. Each of the three redundant feedback paths terminates a corresponding input of an inverting majority gate MG 1 . The basic functionality of a majority gate is to provide an output corresponding to that of the majority of the inputs. 
     An exemplary majority gate is depicted in  FIG. 3 . As illustrated, the majority gate has three inputs, input A, input B, and input C. The majority gate is formed from six PMOS transistors T 15 -T 20  and six NMOS transistors T 21 -T 26 , which are arranged in three complementary inverter stacks. When any two or more of the inputs A, B, and C are a logic 1, at least one pair of series NMOS transistors T 21 -T 26  are turned on and pull the output OUT to a logic 0. Similarly, when any two or more of the inputs A, B, and C are a logic 0, at least one pair of the PMOS transistors T 15 -T 20  are turned on and pull the output OUT to a logic 1. For example, if inputs A and B are a logic 1 and input C is a logic 0, transistors T 21  and T 22  are turned on and the output OUT is pulled to a logic 0. The other two stacks that include transistors T 23 -T 26  are not pulled to a logic 0, because transistors T 24  and T 26 , which are driven by input C, are turned off. Although input C is a logic 0, this will not affect the output OUT. 
     Returning to  FIG. 2 , the majority gate MG 1  will receive three inputs from the three feedback paths and provide an output that corresponds to the majority of the three inputs. For example, if two or three of the three inputs are a logic 0, the output will be a logic 1, because the majority gate illustrated is an inverting majority gate. Similarly, if two or three of the inputs were a logic 0, the output of the majority gate MG 1  would be a logic 1. In essence, the majority gate MG 1  will filter out those inputs that are not in line with the majority of inputs. The output of the majority gate MG 1  is fed through a pass gate formed by transistors T 13  and T 14  back to node N 1 . Notably, the logic state of node M, which corresponds to the output of the majority gate MG 1  or the logic state of the input D, is alternately passed to node N 1  through the respective pass gates in response to the clock signal CLK or CLKb as inverted by inverter I 2 . 
     The temporal latch provides immunity to SETs in the following manner. If the input D temporarily transitions to the wrong logic state for a duration less than the delay δ, the resulting transient is passed to the majority gate MG 1  through the three different feedback paths at different times. In particular, a delay of δ is provided between the transients that appear on the three feedback paths. Assuming the transient is less than the delay δ, the majority gate MG 1  will only see the transient on one input at a time. Since there are three inputs, a transient on a minority input will not affect the output of the majority gate MG 1 . In other words, assuming the transient has a duration of less than the delay δ, two of the three feedback paths will always have the correct logic state and the output of the majority gate MG 1  will be based on the correct logic states. The temporal latch basically filters out any transients on the input D where the transients have a duration less than the delay δ. In a similar fashion, the temporal latch will filter out transients appearing on the clock signal CLK or CLKb through the same overall feedback loop. In addition to addressing transients on the input D and the clock signal CLK, transients appearing in the feedback paths, such as along nodes N 2 , MDb, and MDDb, are filtered out as long as no two nodes are affected at the same time. 
     One drawback of the temporal latch is that it typically cannot handle simultaneous hits on multiple nodes in the feedback paths. Further drawbacks include not being able to provide immunity to SETs that last longer than the delay δ. Unlike the DICE latch of  FIG. 1 , the temporal latch tends to be quite large due to the number of transistors and other components required for the delay circuits D 1 , D 2 , and D 3 . Accordingly, there is a need for a latch that overcomes the deficiencies of the temporal latch while maintaining its benefits. 
     SUMMARY OF THE INVENTION 
     The present invention provides a radiation hardened flip-flop formed from a modified temporal latch and a modified dual interlocked storage cell (DICE) latch. The temporal latch is configured as the master latch and provides four output storage nodes, which represent outputs of the temporal latch. The DICE latch is configured as the slave latch and is made of two cross-coupled inverter latches, which together provide four DICE storage nodes. The four outputs of the temporal latch are used to write the four DICE storage nodes of the DICE latch. The temporal latch includes at least one feedback path that includes a delay element, which provides a delay. 
     In one embodiment, a feedback configuration employs three feedback paths where each of the feedback paths drives two majority gates. One of the feedback paths includes a first delay element that provides a first delay, while another feedback path provides a second delay element that provides a second delay, which is larger, and preferably about twice that of the first delay. The output storage nodes are independent and derived from the outputs of the first and second delay elements and the outputs of the majority gates. The first delay is preferably set to last longer than a duration of a single event transient (SET) caused by a sensitive node being hit by a high energy radiation particle. 
     In a second embodiment, Muller C-gates are used in the feedback path. The first output storage node acts as a primary storage node and drives both a first input of a first delay element and a first input of a first Muller C-gate. The output of the first delay element drives the second input of the first Muller C-gate and provides the third output storage node. The output of the first Muller C-gate corresponds to the fourth storage node and drives both a first input of a second delay element and a first input of a second Muller C-gate. The output of the second delay element drives a second input of the second Muller C-gate and provides the second output storage node. Preferably, the delays provided by the first and second delay circuits are about the same. Further, each delay is preferably set to last longer than a duration of a single event transient caused by a sensitive node being hit by a high energy radiation particle. 
     In a third embodiment, the temporal latch is a cascade voltage switch logic (CVSL) latch having a central cross-coupled latch, which has a first main node and a second main node. The first main node and the second main node hold differential logic states corresponding to a latched input state. A first feedback path extends from the first main node to the second main node and includes a first delay element followed by a first transistor, which controls, at least in part, the first main node. A second feedback path extends from the second main node to the first main node and includes a second delay element followed by a second transistor, which controls, at least in part, the second main node. The first and second transistors allow the first and second main nodes to tri-state when single event transients occur on the respective feedback paths. The first output storage node is derived from the output of the second delay element; the second output storage node is derived from the first main node; the third output storage node is provided by the second main node; and the fourth output storage node is derived from the output of the first delay element. Further, each delay is preferably set to last longer than a duration of a single event transient caused by a sensitive node being hit by a high energy radiation particle. 
     In any of the above embodiments, the temporal latch and the DICE latch may be separated into segments, which include sensitive nodes. To increase radiation hardening, the segments of the temporal latch and the segments of the DICE latch may be interleaved, such that the sensitive nodes are relatively spaced apart from one another while allowing for a relatively compact layout. Preferably, the sensitive nodes are sufficiently spaced apart from one another to minimize the chance of any two of the sensitive nodes being hit by a single radiation particle. When multiple radiation hardened flip-flops are required, segments from the temporal latches and the DICE latches from each of the multiple flip-flops may be interleaved to provide even further radiation hardening while maintaining a compact layout. 
     In yet another embodiment, the output of the radiation hardened flip-flop is derived from the second and fourth DICE storage nodes of the DICE latch. Preferably, a first inverter is coupled between second DICE storage node and the output, and a second inverter is coupled between the fourth DICE storage node and the output. Notably, in any of the embodiments, elements may be provided before or after the described nodes to modify a logic state without veering from the concepts of the present invention or the definition of a particular node, as defined in the claims below. Such elements may include inverters and like logic gates. 
     Those skilled in the art will appreciate the scope of the present invention and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the invention, and together with the description serve to explain the principles of the invention. 
         FIG. 1  illustrates a DICE latch according to the prior art. 
         FIG. 2  illustrates a temporal latch according to the prior art. 
         FIG. 3  illustrates a majority gate according to the prior art. 
         FIG. 4  illustrates a master-slave flip-flop according to one embodiment of the present invention. 
         FIG. 5  illustrates a simulated signal diagram where a SET occurs on node MDb. 
         FIG. 6  illustrates a physical layout of a master-slave flip-flop according to one embodiment of the present invention. 
         FIG. 7  illustrates a slave DICE latch according to one embodiment of the present invention. 
         FIG. 8A  illustrates a first exemplary Muller C-element connected in series with a CMOS transmission gate. 
         FIG. 8B  illustrates a second exemplary Muller C-element that is tri-state-able. 
         FIG. 8C  depicts a symbol for a Muller C-element that is clock gated as in  FIGS. 8A and 8B . 
         FIG. 9  illustrates a master-slave flip-flop according to a second embodiment of the present invention. 
         FIG. 10  illustrates a simulated signal diagram for normal operation of the master-slave flip-flop of  FIG. 9 . 
         FIG. 11  illustrates a simulated signal diagram where a SET occurs on node N 1 . 
         FIG. 12  illustrates a physical layout of four interlaced master-slave flip-flop according to a second embodiment of the present invention. 
         FIG. 13  illustrates a master-slave flip-flop according to a third embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the invention and illustrate the best mode of practicing the invention. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
     The present invention provides a radiation hardened latch, and in particular, a radiation hardened flip-flop that employs modified versions of the classic DICE and temporal latches to form a D-type master-slave flip-flop (MSFF). A first embodiment of the present invention is illustrated in  FIG. 4 , where a MSFF  10  is illustrated to include a master temporal latch  12  and a slave DICE latch  14 . As noted, the master temporal latch  12  is a modified version of the classic temporal latch illustrated in  FIG. 2 . The slave DICE latch  14  is a modified version of the classic DICE latch illustrated in  FIG. 1 . In this embodiment, the traditional DICE latch is modified to have two additional inputs. Further, the output of the slave DICE latch  14  is derived from node X 1  and node X 3  instead of only node X 3 . By employing four inputs in the slave DICE latch  14 , the likelihood of two of the inputs being upset is minimized, especially given the independence of the four corresponding outputs of the master temporal latch  12 , as outlined below. 
     The basic operation of the slave DICE latch  14  is substantially the same as that described in association with the traditional DICE latch of  FIG. 1 . Notably, transistors T 31 -T 38  correspond to transistors T 1 -T 8  of  FIG. 1 . The slave DICE latch  14  includes two cross-coupled inverter latches  14 A,  14 B formed from PMOS transistors T 31 -T 34  and complementary NMOS transistors T 35 -T 38 . The first cross-coupled inverter latch is formed from transistors T 31 , T 32 , T 35 , and T 36  while the second cross-coupled inverter latch  14 B is formed from transistors T 33 , T 34 , T 37 , and T 38 . 
     Notably, node X 0  is formed where transistors T 31  and T 35  are coupled, node X 1  is formed where transistors T 32  and T 36  are coupled, node X 2  is formed when transistors T 33  and T 37  are coupled, and node X 3  is formed where transistors T 34  and T 38  are coupled. Node X 0  is coupled to the gate of transistor T 32  as well as the gate of transistor T 38 . Node X 1  is coupled to the gates of transistors T 35  and T 33 . Node X 2  is coupled to the gates of transistors T 36  and T 34 . Node X 3  is coupled to the gates of transistors T 37  and T 31 , and provides the output Q of the slave DICE latch  14 . 
     The DICE latch  14  has four inputs that are connected to nodes X 0 -X 3 . These inputs are M 0 , M 1 , MDDb, and MDb, which are all provided as outputs from the master temporal latch  12 . In particular, nodes M 0 , MDDb, M 1 , and MDb provide outputs from the master temporal latch  12  and represent inputs to the slave DICE latch  14 . The logic state of node M 0  is passed to node X 0  through PMOS pass transistor T 39 , the logic state of node MDDb is passed to node X 1  through PMOS pass transistor T 40 , the logic state of node M 1  is passed to node X 2  through PMOS pass transistor T 41 , and the logic state of node MDb is passed to node X 3  through PMOS pass transistor T 42 . Notably, the pass transistors are active when the clock signal, CLKb, is asserted low. As noted, the output Q of the slave DICE latch  14  is derived from nodes X 1  and X 3 . In particular, the nodes X 1  and X 3  are respectively coupled to inverters  18  and  19 . The outputs of the inverters  18  and  19  are coupled together to form the output Q of the slave DICE latch  14 , and the overall output of the MSFF  10 . 
     The addition of the two extra inputs for the slave DICE latch  14  provides immunity to any one of the four inputs being at an incorrect logic level during transfers from the master temporal latch  12  to the slave DICE latch  14 . To provide this immunity, the four inputs to the slave DICE latch  14 , and thus the corresponding four outputs from the master temporal latch  12 , are substantially independent of each other. The combination of nodes X 1  and X 3  to provide the output Q of the slave DICE latch  14  allows the output Q to recover more quickly in response to a SET that affects one of the two nodes X 1  and X 3 . 
     From the description of  FIG. 2 , the traditional temporal latch only provides three outputs. The master temporal latch  12  of  FIG. 4  is modified to provide a fourth output. The four outputs of the master temporal latch  12  correspond to nodes M 0 , MDDb, M 1 , and MDb. To obtain the fourth output, another majority gate is added to the master temporal latch  12 . As such, the master temporal latch  12  includes two majority gates MG 2  and MG 3 . The master temporal latch  12  still includes three feedback paths, each of which is presented to both the majority gates MG 2  and MG 3 . The first feedback path corresponds to node N 2 ; the second feedback path corresponds to node MDb, the associated inverters I 5  and I 6 , and delay circuitry D 4 ; and the third feedback path corresponds to node MDDb, the associated inverters I 5  and I 7 , and delay circuitry D 5 . Notably, delay circuitry D 4  provides a single delay δ in the second feedback path, while delay circuitry D 5  provides a double delay 2δ in the third feedback path. The operation of the three feedback paths is analogous to that described in association with  FIG. 2 . The inverter I 4  drives each of the feedback paths based on the logic state at node N 2 , which corresponds to the input D. As described above, the input D is passed through a pass gate formed by transistors T 27  and T 28  when the clock signal CLKb is asserted high. When the clock signal CLKb is asserted low, the logic state of node M 0 , which is the output of the majority gate MG 2 , is passed through a pass gate formed by transistors T 29  and T 30  to node N 1 . 
     Notably, node M 0  is used to drive node X 0  and is the output of the majority gate MG 2 . Node MDDb is the output of the third feedback path, which has a 2δ delay and drives node X 1 . Node M 1 , which is the output of the majority gate MG 3 , drives node X 2 . The output of the second feedback path corresponding to node MDb and having a single delay δ drives node X 3 . 
     As described in association with  FIG. 2 , the presence of three feedback paths that have different delays allows the master temporal latch  12  to effectively filter out transients having a duration less than a delay δ on the input D, the clock signal CLK or CLKb, as well as any one of the feedback nodes N 2 , MDb, MDDb, or any other node along the feedback paths. 
     Examples of how the MSFF  10  responds to SETs follow. For the first example, assume that there have been no SETs and that an input D has been stored at node N 1 . Further assume that node N 1  of the MSFF  10  is set at a logic 0 and has been set at a logic 0 for more than two δ delays. As such, nodes N 2 , MDb, and MDDb are also logic 1s and nodes MD and MDD are logic 0s. Since nodes N 2 , MDb, and MDDb are logic 1s, nodes M 0  and M 1 , which are the respective outputs of the majority gates MG 2  and MG 3 , are logic 0s. When the clock signal CLKb is asserted to a logic 0, the logic 0s of nodes M 0  and M 2  are passed to nodes X 0  and X 2  of the slave DICE latch  14  via pass gate transistors T 39  and T 41 , respectively. Also, the logic 1s of nodes MDDb and MDb are passed to nodes X 1  and X 3  of the slave DICE latch  14  via the pass gate transistors T 40  and T 42 , respectively. Since nodes X 1  and X 3  are logic 1s, the inverters I 8  and I 9  cause the output Q of the slave DICE latch  14  to be a logic 0. 
     After the MSFF  10  has been written as described above, assume a SET in the form of an ionizing particle of radiation strikes node N 2  of the master temporal latch  12 . The excess electrons from the ionizing particle of radiation cause the node N 2  to temporarily transition from a logic 1 to a logic 0 for less than one δ delay. Within one δ delay, node N 2  will return to a logic 1. Notably, the transient at node N 2  is propagated through the respective feedback paths provided by the one δ delay circuit D 4  and the two δ delay circuit D 5 . After one δ delay, node MDb temporarily transitions to a logic 0 for less than one δ delay. After two delay delays, node MDDb temporarily transitions to a logic 0 for less than one δ delay. Notably, node N 2  will have returned to a logic 1 before either of nodes MDb or MDDb temporarily transition to logic 0s. Similarly, node MDb will have returned to a logic 1 before node MDDb temporarily transitions to a logic 0. Since node MDb is delayed one δ delay from node N 2  and node MDDb is delayed two δ delays from node N 2 , only one of the nodes N 2 , MDb, and MDDb are a logic 0 at any given time in response to the SET event at node N 2 . 
     Since only one of the nodes N 2 , MDb, and MDDb are a logic 0 at any given time, neither of the majority gates MG 2  and MG 3  react to the spaced apart transients appearing on the respective nodes. As such, the output nodes M 0  and M 1  of the master temporal latch  12  remain logic 0s despite the SET at node N 2 . 
     The SET at N 2  may occur when the output nodes M 0 , M 1 , MDDb, and MDb of the master temporal latch  12  are being written to the slave DICE latch  14 . As noted, the output nodes M 0  and M 1  of the master temporal latch  12  are unaffected; however, a transient on either of nodes MDDb or MDb may be passed to nodes X 1  or X 3 , respectively. Since only one of the nodes X 1  or X 3  will see a transient at any given time, the remaining nodes of the slave DICE latch  14  will operate to correct the transient and not upset the proper state of the slave DICE latch  14 , and thus the output Q. 
     For the second example, assume a SET impacts node X 3  of the slave DICE latch  14 . Assume that nodes M 0  and M 1  are logic 1s and nodes MDDb and MDb are logic 0s. Nodes M 0 , MDDb, M 1 , and MDb are the outputs of the mater temporal latch  12  and drive nodes X 0 , X 1 , X 2 , and X 3 , respectively, of the slave DICE latch  14 , when the slave DICE latch is being written. As such, when the clock signal CLKb transitions from a logic 1 to a logic 0 and back to a logic 1, the logic states on nodes M 0 , MDDb, M 1 , and MDb are passed to nodes X 0 , X 1 , X 2 , and X 3 , respectively. Accordingly, after clock signal CLKb is asserted, nodes X 0  and X 2  are logic 0s and nodes X 1  and X 3  are logic 1s. 
     After the slave DICE latch  14  is written, assume a SET in the form of an ionizing particle of radiation strikes node X 3 . The excess electrons from the ionizing particle of radiation cause the node X 3  to errantly transition from a logic 1 to a logic 0. As a result, PMOS transistor T 31  turns on, when it should be turned off. Further, the NMOS transistor T 37  turns off, when it should be turned on, and will no longer drive node X 2 . However, transistor T 33  is already turned off and will allow node X 2  to remain a logic 0; and therefore, keep PMOS transistor T 34  turned on. NMOS transistor T 35  is still turned on because node X 1  is a logic 1, and PMOS transistor T 34  is still turned on because node X 2  is still a logic 0. Notably, PMOS transistor T 34  will pull off the excess negative charge on node X 3  and restore node X 3  to a logic 1, such that the slave DICE latch  14  returns to its proper state. Although the output Q will have a transient glitch due to node X 3  temporarily transitioning to a logic 0, the output Q is not upset and quickly returns to its proper state. The slave DICE latch  14  will respond in a similar fashion when any one of the nodes X 0  through X 3  are subjected to a SET event that changes the state of the affected node. 
     With reference to  FIG. 5 , simulated waveforms are provided to illustrate the effects of a SET occurring on nodes MDb in the master temporal latch  12 . The waveforms are broken into five different sections referred to as sections A through E. Section A illustrates the input D and clock signal CLK, while section B illustrates the output Q provided by the slave DICE latch  14 . Section C illustrates nodes X 0 -X 3 , section D illustrates nodes MDb and MDDb, and section E illustrates nodes M 0  and M 1 . As noted, the SET occurs on MDb, while the clock signal CLK is transparent and thus asserted low, as illustrated in section D. As such, a disturbance is seen on node X 3  that corresponds to the SET, which occurs on node MDb. Notably, nodes X 0 , X 1 , and X 2  are undisturbed. Further, the output Q only shows a minor glitch corresponding to the SET that occurs on node MDb, and maintains the correct logic state. 
     Another potentially important aspect of designing the MSFF  10  is the physical layout of the various sections of the master temporal latch  12  and the slave DICE latch  14 . As such, planning the spatial separation of the constituent circuit components of the MSFF  10  plays a significant role in the extent of radiation hardening. In one embodiment, the goal is to separate critical nodes M 0 , M 1 , MDb, and MDDb as well as interleaving the majority gates MG 2  and MG 3 . An exemplary physical layout design is provided in  FIG. 6 . Notably, the MSFF  10  is divided into seven sub-cells. The slave DICE latch  14  is separated into two halves, which correspond to the inverter latch  14 A and the inverter latch  14 B. Reference is made to  FIG. 4  to illustrate the components associated with the inverter latch  14 A and the inverter latch  14 B. As illustrated in  FIG. 6 , the inverter latches  14 A and  14 B are placed apart from one another to protect the storage nodes X 0 -X 3 . The delay circuits D 4  and D 5  of the master temporal latch  12  are placed on opposite sides of the layout, and the majority gates MG 2  and MG 3  are also separated from each other to prevent a single strike by a radiation particle from upsetting the state or inputs of the slave DICE latch  14 . The remaining portions of the master temporal latch  12  reside in the upper right-hand corner of the layout. In one embodiment, each MSFF  10  is formed in a common substrate isolated by a guard ring, which is formed from heavily doped P-type material. The guard ring helps to address single event latch-up (SEL) effects as well as helping to alleviate TID induced diffusion-to-diffusion leakage. 
     With reference to  FIG. 7 , further hardening due to physical layout considerations may be provided by breaking the slave DICE latch  14  into four separate latches  14 A′,  14 A″,  14 B′, and  14 B″. Latches  14 A′ and  14 A″ correspond to the inverter latch  14 A, while latches  14 B′ and  14 B″ correspond to the inverter latch  14 B. By separating the slave DICE latch  14  into four separate latches  14 A′,  14 A″,  14 B′, and  14 B″, each of these latches may be physically separated from the others, and interleaved with other sub-cells, to further protect the corresponding nodes X 0 -X 3  from simultaneous upset due to a single impinging radiation particle track. 
     In 1959, David E. Muller disclosed the use of a C-element in asynchronous systems. The Muller C-element generally has N inputs and one output. Unless all of the inputs are at the same logic state, the output is tri-stated, and thus will float. When the inputs agree, a corresponding output is provided. A Muller C-element, which is referred to as a C-gate, is illustrated in  FIG. 8A  according to one embodiment of the present invention. A complementary transistor stack is created with PMOS transistors T 43  and T 44  and NMOS transistors T 45  and T 46 , which are arranged in a complementary fashion. The C-gate has two inputs, A and B. Input A is coupled to the gates of the PMOS transistor T 43  and the NMOS transistor T 46 . Similarly, input B is coupled to the gates of PMOS transistor T 44  and the NMOS transistor T 45 . The output of the Muller C-Element drives a series transmission gate that is comprised of transistors T 47  and T 48 , which allows the output to change only if inputs A and B agree, and if the signals CLK and CLKb are asserted high and low, respectively. Transistors T 47  and T 48  are respectively driven by clock signals CLKb and CLK. If inputs A and B are both a logic 1(0), then the output OUT will be a logic 0(1). When input A is not at the same logic state as input B, the output OUT will be tri-stated for the duration of time that the inputs A and B differ from one another. During the tri-stated period, the output OUT may float. Accordingly, the C-gate is similar to a majority gate, such as majority gates MG 1 -MG 3 , with the exception that the majority gate will provide a driven output even if one of the three inputs does not equal the other two inputs. 
     An alternative C-gate configuration is provided in  FIG. 8B , which has an output that is explicitly tri-stated by the controlling clock inputs CLK and CLKb. It is logically equivalent to the series connected Muller C-element and CMOS transmission gate in  FIG. 8A . As illustrated, PMOS transistors T 49 -T 51  are stacked with NMOS transistors T 52 -T 54 . Clock signals CLKb and CLK are respectively coupled to the gates of transistors T 51  and T 52 . Input A is coupled to the gates of the PMOS transistor T 49  and the NMOS transistor T 54 . Input B is coupled to the gates of PMOS transistor T 50  and NMOS transistor T 53 . The operation of the C-gate in  FIG. 8B  is essentially the same as that of  FIG. 8A . As such, if inputs A and B are both a logic 1(0), then the output OUT will be a logic 0(1). When the inputs A and B differ from one another, the output OUT is tri-stated while the inputs A and B are different. The output OUT is also tri-stated if the controlling clock signals are de-asserted, such as when clock signal CLK is low and clock signal CLKb is high. A symbol for a clock controlled C-gate that is configured according to the present invention is provided in  FIG. 8C , wherein the C-gate has inputs A and B, clock signals CLK and CLKb, along with a single output OUT. 
     With reference to  FIG. 9 , an alternative master temporal latch  12 ′ is illustrated in the MSFF  10 . In particular, the master temporal latch  12 ′ employs C-gates instead of majority gates. Notably, the master temporal latch  12 ′ is coupled with a slave DICE latch  14 , which is configured in the same way as those described above. 
     In operation, the input D is transferred to node N 1  through tri-state inverter I 11  when the inverted clock signal CLKb is asserted low. Assuming the input D is a logic 1, node N 1  will fall to a logic 0 and be presented to one input of the C-gate C 1 . The logic 0 of node N 1  is also presented to a delay circuit D 6 , which provides a delay of δ. Accordingly, after aδ delay, node N 2  will fall to a logic 0. Since both inputs to the C-gate C 1  are a logic 0, the output of the C-gate, which corresponds to node N 3 , is updated to a logic 1. Node N 3  drives a second C-gate C 2 , and another delay circuit D 7 , which also provides a delay of δ. Accordingly, when node N 3  transitions to a logic 1, node N 4 , which corresponds to the output of the delay circuit D 7 , will transition to a logic 1 after a δ delay. When both inputs of the second C-gate C 2  become a logic 1, the output of the clock controlled C-gate C 2 , which corresponds to node N 1 , is driven to a logic 0 when the controlling signal clocks close the latch feedback path. Accordingly, the appropriate logic state is effectively stored at node N 1  while the clock signal CLK is de-asserted. At this point, the storage nodes N 1 , N 2 , N 3 , and N 4  are set up and stable. 
     These storage nodes N 1 , N 2 , N 3 , and N 4  represent the four outputs of the master temporal latch  12 ′, and are used to drive the four inputs of the slave DICE latch  14 . After the falling edge of the clock signal CLK, the logic states of the output nodes N 1 , N 2 , N 3 , and N 4  are written to the nodes X 0 , X 1 , X 2 , and X 3  of the slave DICE latch  14 . In particular, the logic state of storage node N 1  is passed to node X 0  through the inverter I 12  and the pass transistor T 39 ; the logic state of storage node N 2  is passed to node X 2  through the inverter I 14  and the pass transistor T 41 ; the logic state of storage node N 3  is passed to node X 3  through the inverter I 15  and the pass transistor T 42 ; and the logic state of the storage node N 4  is passed to node X 1  through inverter I 13  and pass transistor T 40 . The delay from the falling edge of the clock signal CLK to the time the output Q of the slave DICE latch  14  settles is essentially one pass gate delay plus the inverter delay. 
     A simulation of the waveforms for the clock signal CLK, output Q, storage nodes N 1 , N 2 , N 3 , and N 4 , and nodes X 0 , X 1 , X 2 , and X 3  is illustrated in  FIG. 10 . Section A illustrates the relationship between the clock signal CLK and the output Q. Section B illustrates the relationship between storage nodes N 1  and N 2 . In this example, the δ delay provided by the delay circuits D 6  and D 7  are approximately 400 picoseconds. Section C illustrates the relationship between storage nodes N 3  and N 4 . Notably, the delay between the change in logic states at storage nodes N 1  and N 2  corresponds to the delay between the change in logic states at storage nodes N 3  and N 4 . Section D depicts the change in states of nodes X 0 -X 3  of the slave DICE latch  14 . 
     With reference to  FIG. 11 , a simulated waveform is provided to illustrate the handling of a SET that occurs at the input D or storage node N 1 . Again, section A illustrates the clock signal CLK and the output Q. Notably, the output Q is not affected by the SET that occurs at the storage node N 1 . The SET that occurs at the storage node N 1  is illustrated in section B. Notably, after the logic state at storage node N 1  falls to a logic state 0, a SET occurs in the form of a short pulse. The SET occurring in storage node N 1  is propagated to storage node N 2  through the delay circuit D 6 . Accordingly, the SET appearing on storage node N 2  appears after a δ delay from the time the SET occurred at the storage node N 1 . In section C, storage node N 3 , which corresponds to the output of the C-gate C 1 , floats during the time the SET is occurring on storage node N 1  and when the SET is propagated to storage node N 2 . Again, the floating of storage node N 3  is due to the tri-state output of the C-gate C 1  when the inputs are at different logic states. 
     After both storage nodes N 1  and N 2  have recovered from the SET and the propagation of the SET, respectively, the logic value in storage node N 3  transitions to a logic 1, which is the proper logic state for the storage node N 3 . Since the output of the C-gate C 1  allows storage node N 3  to float, the state of storage node N 4  may remain relatively or completely undisturbed by the propagation of the SET. In essence, the output of the C-gate C 1  may remain sufficiently low, such that the delay circuit D 7  does not pass the transient change in logic state to storage node N 4 . Accordingly, the respective outputs provided by the storage nodes N 1 -N 4  settle at the appropriate logic state prior to being written into the corresponding nodes X 0 -X 3  of the slave DICE latch  14 . As such, the transient does not make its way to the output Q, let alone upset the overall state of the slave DICE latch  14 . 
     As with the MSFF  10  of  FIG. 4 , the MSFF  10  of  FIG. 9  also benefits from a physical layout that separates critical nodes and circuit elements. With reference to  FIG. 12 , an exemplary physical layout is provided for four MSFFs  10 . Notably, various sections of the different MSFFs  10  are interleaved amongst each other to provide significant radiation hardening for each MSFF  10  while minimizing the physical footprint required for implementing the four MSFFs  10 . In this example, each MSFF  10  is broken into essentially seven primary sub-cells. These sub-cells include the input inverter I 11   z , C-gate C 1   z , C-gate C 2   z , the delay circuitry D 6   z  and related feedback path components, the delay circuitry D 7   z  and related feedback path components, the inverter latch  14 A z , and the inverter latch  14 B z , where z identifies a unique MSFF  10 . As illustrated, z equals four (4), and as such, four unique MSFFs  10  are provided in the layout. As such, the various segments for a given MSFF  10  are isolated by one or more sub-cells of other MSFFs  10 , as depicted in  FIG. 12 . Those skilled in the art will recognize alternative ways of laying out the identified sub-cells as well as configuring more or less sub-cells to use when dividing the MSFF  10 . 
     With reference to  FIG. 13 , yet another embodiment of an MSFF  10  is illustrated. In this embodiment, the same DICE latch  14  is employed as described above; however, an alternative master temporal latch  12 ″ is used. The master temporal latch  12 ″ provides the same overall functionality as the master temporal latch  12 ′, which employed the C-gates C 1  and C 2  and was illustrated in  FIG. 9 . In particular, the master temporal latch  12 ″ employs cascade voltage switch logic (CVSL) techniques. As with the other master temporal latches  12  and  12 ′, the master temporal latch  12 ″ provides four independent outputs to drive nodes X 0 -X 3  of the slave DICE latch  14 . The master temporal latch  12 ″ only requires two delay circuits D 6  and D 7 , and only requires a relatively small number of transistors to provide the latch and feedback functions required for operation. 
     As illustrated, the master temporal latch  12 ″ includes PMOS transistors T 55 -T 62  and NMOS transistors T 63  and T 64 . The circuit also includes inverters I 10 -I 11 . The inputs to the master temporal latch  12 ″ include input D and clock signals CLK and CLKb, wherein clock signal CLKb is the inverse of clock signal CLK. When the clock signal CLK is low, transistors T 57  and T 58  turn on and allow the input D to be written into the latch formed by the cross-coupled transistors T 63  and T 64 . For example, if input D is a logic 1, transistor T 61  is turned off. The logic 1 is inverted to a logic 0 by inverter I 12 , and thus drives node DN to a logic 0, which turns transistor T 62  on. Since transistors T 58  and T 62  are on, node MD is charged to a logic 1. When node MD is a logic 1, transistor T 63  is turned on and pulls node MDN to a logic 0. As such, the latch is set where node MDN is a logic 0 and node MD is a logic 1. These states are maintained when the clock signal CLK returns to an unasserted state. 
     Nodes MDN and MD reside at the beginning of two different feedback paths. The first feedback path extends from node MDN through delay circuitry D 7 , which provides a delay δ, to transistor T 60 . Transistor T 60  is used to ensure that node MD remains at a logic 1 when node MD should be at a logic 1. When node MD is at a logic 0, transistor T 60  is turned off. Similarly, node MD resides at the beginning of a feedback path that extends through delay circuitry D 6 , which provides a delay δ, to transistor T 59 . Transistor T 59  is generally turned on when node MDN should be at a logic 1. In general, when node MD is at a logic 0, it will effectively turn transistor T 59  on, which will hold node MDN at a logic 1. A logic 1 at node MDN will turn on transistor T 64  and hold node MD at a logic 0. Further, since node MDN also controls transistor T 60 , when node MDN is a logic 0, transistor T 60  is off and thereby allows node MD to remain at a logic 0. Such operation is reversed when node MDN is a logic 0 and node MD is a logic 1. 
     As noted above, the master temporal latch  12 ″ provides four independent outputs to drive nodes X 0 -X 3  of the slave DICE latch  14 . As illustrated, these four independent outputs are derived from nodes MDQN, MQ, MQN, and MDQ. Node MDQN is derived from the output of the delay circuitry D 6 , while node MDQ is derived from the output of the delay circuitry D 7 . Notably, nodes MDQN and MDQ are generally at opposing logic states and are used to drive nodes X 0  and X 3  through pass transistors T 39  and T 42 , respectively. Together, nodes MDQN and MDQ are referred to as delayed differential outputs of the master temporal latch  12 ″. The other two outputs are provided by nodes MQ and MQN, which are referred to as differential outputs. Node MQ is derived from node MDN, and node MQN is derived from node MD. In particular, inverter I 10  couples node MDN to node MQ, and inverter I 11  couples node MD to node MQN. The pass transistors T 40  and T 41  pass the logic states of node MQ and node MQN, respectively, to nodes X 1  and X 2  of the slave DICE latch  14 . The logic states of nodes MDQN, MQ, MQN, and MDQ are passed to the nodes X 0 -X 3  of the slave DICE latch  14  when the clock signal CLKb is asserted low. 
     One aspect of radiation hardening for the master temporal latch  12 ″ involves allowing nodes MDN or MD to tri-state when SETs adversely affect the feedback paths corresponding to transistors T 59  and T 60 . As an example, assume that node MD is a logic 1 and node MDN is a logic 0. After a delay δ, node MDQN is a logic 1, node MQ is a logic 1, node MQN is a logic 0, and node MDQ is a logic 0. If node MDQ is struck by a radiation particle and temporarily transitions to a logic 1, transistor T 60  is turned off while node MDQ is at a logic 1. As a result, node MD is tri-stated and allowed to float. Since node MD is already charged to a logic 1, the node will remain at a logic 1 until the SET has passed and node MDQ returns to a logic 0, wherein transistor T 60  is turned back on. 
     When turned on, transistor T 60  will maintain node MD at a logic 1. Similarly, if node MDN is a logic 1 and node MDQN is struck by a radiation particle and changes from a logic 0 to a logic 1, transistor T 59  will turn off and allow node MDN to float in a tri-state mode. 
     The master temporal latch  12 ″ is also immune to SETs occurring on nodes MDN or MD, as long as the SETs have a duration less than the delay δ. One aspect of this embodiment is the configuration of the latch transistors T 63  and T 64  to be significantly weaker than the PMOS transistors T 55 -T 62 , and at least transistors T 59  and T 60 . If node MDN is at a logic 0 and experiences a SET that temporarily changes its state to a logic 1, transistor T 64  could be turned on. However, because the transistor T 60  is more powerful than transistor T 64 , which is easily ensured by using the appropriate MOSFET widths and lengths for the transistors, transistor T 60  will overcome the attempt of transistor T 64  to drive node M 0  low and continue to drive transistor T 63  to an on state. As such, transistor T 60  will maintain node MD at a logic 1 and also keep transistor T 63  turned on, thus returning node MDN to a logic 0. The propagation of these transients through the respective delay circuits D 6  and D 7  will keep the master temporal latch  12 ″ in the appropriate state. Notably, any SETs occurring on nodes MDQN, MQ, MQN, and MDQ are handled by the slave DICE latch  14  as described above. 
     Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present invention. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow. Notably, in any of the embodiments, elements may be provided before or after the described nodes to modify a logic state without veering from the concepts of the present invention or the definition of a particular node, as defined in the claims below. Such elements may include inverters and like logic gates.