Patent Publication Number: US-11664349-B2

Title: Stacked chip package and methods of manufacture thereof

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application is a continuation of application Ser. No. 16/225,665 filed on Dec. 19, 2018, now Pat. No. 10,840,217 issued Nov. 17, 2020, which is a continuation of U.S. patent application Ser. No. 14/919,378, entitled, “Structure and Formation Method for Chip Package,” filed on Oct. 21, 2015, now Pat. No. 10,163,859 issued Dec. 25, 2018, which application is hereby incorporated herein by reference. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. The fabrication of semiconductor devices involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using lithography and etching processes to form circuit components and elements on the semiconductor substrate. 
     The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allows more components to be integrated into a given area. The number of input and output (I/O) connections is significantly increased. Smaller package structures, that utilize less area or smaller heights, are developed to package the semiconductor devices. For example, in an attempt to further increase circuit density, three-dimensional (3D) ICs have been investigated. 
     New packaging technologies have been developed to improve the density and functionality of semiconductor devices. These relatively new types of packaging technologies for semiconductor devices face manufacturing challenges. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS.  1 A- 1 O  are cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. 
         FIGS.  2 A- 2 B  are cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. 
         FIG.  3    is a cross-sectional view of a chip package, in accordance with some embodiments. 
         FIGS.  4 A- 4 I  are cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. 
         FIGS.  5 A- 5 F  are cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. 
         FIGS.  6 A- 6 E  are cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. 
         FIG.  7    is a cross-sectional view of a package structure, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Some embodiments of the disclosure are described.  FIGS.  1 A- 1 O  are cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. Additional operations can be provided before, during, and/or after the stages described in  FIGS.  1 A- 1 O . Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order. 
     As shown in  FIG.  1 A , a substrate  10  and a semiconductor die  20  to be bonded on the substrate  10  are provided. In some embodiments, the substrate  10  includes a semiconductor wafer, a portion of a semiconductor wafer, a dielectric wafer, a portion of a dielectric wafer, another suitable substrate, or a combination thereof. The semiconductor wafer (such as a silicon wafer) may contain device elements such active devices and/or passive devices. In some other embodiments, the semiconductor wafer does not contain any device element. For example, the semiconductor wafer is a blank silicon wafer. The dielectric wafer may include a glass wafer. In some other embodiments, there are one or more other semiconductor dies (not shown) that have been bonded on the substrate  10 . 
     In some embodiments, the substrate  10  includes a semiconductor substrate  100  and an interconnection structure formed on the semiconductor substrate  100 , as shown in  FIG.  1 A . The interconnection structure includes an interlayer dielectric layer  102  and conductive pads  104 . The interlayer dielectric layer  102  includes multiple dielectric sub-layers. Multiple conductive contacts, conductive vias, and conductive lines are formed in the interlayer dielectric layer  102 . Portions of the conductive lines form the conductive pads  104 . 
     In some embodiments, the interlayer dielectric layer  102  includes a sub-layer that covers the conductive pad  104 . This sub-layer may serve as a bonding layer to facilitate a subsequent bonding with the semiconductor die  20  (through, for example a fusion bonding process). In these cases, the sub-layer on the conductive pads  104  has a subsequent planar top surface. A planarization process, such as a chemical mechanical polishing (CMP) process, may be used to provide the sub-layer with the substantially planar top surface. In some other embodiments, some or all of the conductive pads  104  are exposed without being completely buried in the interlayer dielectric layer  102 . The top surfaces of the conductive pads  104  may be substantially coplanar with the top surface of the interlayer dielectric layer  102 . 
     As shown in  FIG.  1 A , the semiconductor die  20  includes a semiconductor substrate  200  and an interconnection structure formed on the semiconductor substrate  200 . The interconnection structure includes an interlayer dielectric layer  202  and conductive pads  204 . The interconnection structure of the semiconductor die  20  may be similar to the interconnection structure of the substrate  10 . In some embodiments, the conductive pads  204  are buried in the interlayer dielectric layer  202 . In some other embodiments, the top surfaces of the conductive pads  204  are substantially coplanar with the top surface of the interlayer dielectric layer  202 . 
     Various device elements are formed in the semiconductor substrate  200 . Examples of the various device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), diodes, or other suitable elements. Various processes may be used to form the various device elements, including deposition, etching, implantation, photolithography, annealing, and/or other suitable processes. The device elements are interconnected through the interconnection structure of the semiconductor die  20  to form the integrated circuit device, such as a logic device, memory device (e.g., static random access memory, SRAM), radio frequency (RF) device, input/output (I/O) device, system-on-chip (SoC) device, combinations thereof, or other applicable types of devices. 
     As shown in  FIG.  1 B , the semiconductor die  20  is bonded on the substrate  10 , in accordance with some embodiments. A variety of bonding processes may be used to bond the semiconductor die  20  with the substrate  10 . In some embodiments, the semiconductor die  20  and the substrate  10  are bonded together through a fusion bonding. The fusion bonding may be an oxide-to oxide bonding. In some embodiments, the semiconductor die  20  is placed over the substrate  10  such that the interlayer dielectric layers  102  and  202  are in direct contact with each other. Afterwards, a heat treatment may be used to achieve the fusion bonding between the interlayer dielectric layers  102  and  202 . During the fusion bonding, the structure shown in  FIG.  1 B  may be heated at a temperature in a range from about 150 degrees C. to about 300 degrees C. 
     In some other embodiments, the semiconductor die  20  and the substrate  10  are bonded together through a hybrid bonding. The hybrid bonding may include an oxide-to-oxide bonding and a metal-to-metal bonding. In some embodiments, the semiconductor die  20  is placed over the substrate  10 . As a result, the interlayer dielectric layers  102  and  202  are in direct contact with each other, and some of the conductive pads  104  and  204  are in direct contact with each other. Afterwards, a heat treatment may be used to achieve the hybrid bonding between the interlayer dielectric layers  102  and  202  and between the conductive pads  104  and  204 . During the hybrid bonding, the structure shown in  FIG.  1 B  may be heated at a temperature in a range from about 300 degrees C. to about 450 degrees C. 
     Although the front side (wherein the interconnection structure is formed) of the semiconductor die  20  faces the substrate  10 , embodiments of the disclosure are not limited thereto. In some other embodiments, the semiconductor die  20  is arranged upside down such that the back side of the semiconductor die  20  faces the substrate  10 . In other words, the back side of the semiconductor die  20  is between the front side and the substrate  10 . In these cases, the semiconductor substrate  200  is bonded to the interlayer dielectric layer  102 . In some embodiments, a dielectric film, such as an oxide film, is formed over the semiconductor substrate  200  to facilitate bonding with the interlayer dielectric layer  102 . In some embodiments, the dielectric film is a native oxide film grown on the surface of the semiconductor substrate  200 . 
     As shown in  FIG.  1 C , the semiconductor die  20  is thinned, in accordance with some embodiments. In some embodiments, a portion of the semiconductor substrate  200  is removed such that the semiconductor die  20  is thinned. In some embodiments, a planarization process is used to achieve the thinning of the semiconductor die  20 . The planarization process may include a CMP process, a grinding process, an etching process, another applicable process, or a combination thereof. 
     As shown in  FIG.  1 D , a dielectric layer  206  is deposited over the substrate  10  to encapsulate the semiconductor die  20 , in accordance with some embodiments. The dielectric layer  206  surrounds and covers the semiconductor die  20 . The dielectric layer  206  may be used to protect the semiconductor die  20 . In some embodiments, the dielectric layer  206  is in direct contact with the semiconductor die  20 . In some embodiments, the dielectric layer  206  is in direct contact with side surfaces and back surface of the semiconductor substrate  200 . The structure shown in  FIG.  1 D  may be used as a chip package. Alternatively, the structure shown in  FIG.  1 D  may further be integrated into another package structure. 
     In some embodiments, the dielectric layer  206  is substantially made of a semiconductor oxide material. For example, the dielectric layer  206  is substantially made of silicon oxide. In some embodiments, a major portion of the dielectric layer  206  is made of a semiconductor oxide material, such as silicon oxide. In some embodiments, the dielectric layer  206  includes silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, another suitable material, or a combination thereof. In some embodiments, the dielectric layer  206  is a single layer. In some other embodiments, the dielectric layer  206  includes multiple sub-layers. In some embodiments, most of the sub-layers are made of a semiconductor oxide material. One or some of the sub-layers may be made of semiconductor nitride material, semiconductor oxynitride material, or semiconductor carbide material and may serve as an etch stop layer. 
     In some embodiments, the dielectric layer  206  is substantially free of polymer material. In some embodiments, there is no molding compound or underfill material between the dielectric layer  206  and the semiconductor die  20 . Since the dielectric layer  206  is substantially free of polymer material or molding compound material, the coefficients of thermal expansion (CTE) of the dielectric layer  206 , the semiconductor die  20 , and the substrate  10  are similar. Therefore, warpage due to CTE mismatch may be reduced or prevented. The quality and reliability of the chip package are improved. 
     In some embodiments, the dielectric layer  206  is deposited using a vapor deposition process. The vapor deposition process may include a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, another applicable process, or a combination thereof. In some embodiments, a planarization process is performed to provide the dielectric layer  206  with a substantially planar top surface. The planarization process may include a CMP process, a grinding process, an etching process, another applicable process, or a combination thereof. 
     However, embodiments of the disclosure are not limited thereto. In some other embodiments, the dielectric layer  206  is made of a molding compound. 
     Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, one or more conductive features are formed in the chip package to provide electrical connection in vertical direction. 
     As shown in  FIG.  1 E , an etch stop layer  208  and a dielectric layer  210  are deposited over the dielectric layer  206 , in accordance with some embodiments. The etch stop layer  208  may be made of silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof. The dielectric layer  210  may be made of a material that is similar to or the same as that of the dielectric layer  206 . In some embodiments, each of the etch stop layer  208  and the dielectric layer  210  is deposited using a CVD process, an ALD process, a PVD process, another applicable process, or a combination thereof. In some other embodiments, the etch stop layer  208  and/or the dielectric layer  210  are/is not formed. 
     As shown in  FIG.  1 F , a patterned mask layer  212  is formed over the dielectric layer  210 , in accordance with some embodiments. The mask layer  212  may be a photoresist layer and is patterned using a photolithography process. As shown in  FIG.  1 F , the patterned mask layer  212  includes openings corresponding to positions that are designed for forming conductive features. 
     As shown in  FIG.  1 G , a portion of the dielectric layer  210  is removed to form openings  214  that expose the etch stop layer  208 , in accordance with some embodiments. The dielectric layer  210  may be partially removed using an etching process through the openings of the patterned mask layer  212 . Afterwards, the patterned mask layer  212  is removed. 
     As shown in  FIG.  1 H , another patterned mask layer  216  is formed over the dielectric layer  210  and the etch stop layer  208  exposed by the opening  214 , in accordance with some embodiments. The material and formation method of the patterned mask layer  216  may be similar to those of the patterned mask layer  212 . The patterned mask layer  216  has smaller openings that partially expose the etch stop layer  208 . Afterwards, the exposed portion of the etch stop layer  208  is removed, as shown in  FIG.  1 H . 
     As shown in  FIG.  1 I , a portion of the dielectric layer  206  and a portion of the semiconductor substrate  200  are removed to form openings  218 , in accordance with some embodiments. Some of the openings  218  expose the interconnection structure of the semiconductor die  20 , such as the interlayer dielectric layer  202 . The openings  218  are formed using an etching process through the openings of the patterned mask layer  216 . In some embodiments, each of the openings  214  connects with a corresponding one of the openings  218 . In some embodiments, each of the openings  214  is wider than the corresponding one of the openings  218 . Afterwards, the patterned mask layer  216  is removed. 
     As shown in  FIG.  1 J , an insulating layer  220  is deposited over the dielectric layer  210  and sidewalls and bottoms of the openings  214  and  218 , in accordance with some embodiments. The insulating layer  220  may be made of silicon oxynitride, silicon oxide, silicon nitride, silicon carbide, another suitable material, or a combination thereof. The insulating layer  220  may be deposited using a CVD process, a PVD process, a spin-on process, another applicable process, or a combination thereof. 
     As shown in  FIG.  1 K , the insulating layer  220  is partially removed to form insulating elements  222   s ,  222   d , and  224 , in accordance with some embodiments. The insulating elements  222   s  may be used to provide electrical isolation between the semiconductor substrate  200  and conductive features to be subsequently formed in the openings  218 . In some embodiments, each of the insulating elements  222   s  has a thickness that is not uniform. In some embodiments, each of the insulating elements  222   s  gradually becomes wider along a direction from the top of the insulating element  222   s  towards the substrate  10 , as shown in  FIG.  1 K . In some other embodiments, the thicknesses of the insulating elements  222   s  are substantially the same. 
     In some embodiments, an etching process (such as an anisotropic etching process) is used to partially remove the insulating layer  220 . The remaining portions of the insulating layer  220  over sidewalls of the semiconductor substrate  200  in the openings  218  form the insulating elements  222   s . The remaining portions of the insulating layer  220  over sidewalls of the opening  218  that does not penetrate through the semiconductor substrate  200  form the insulating elements  222   d . The remaining portions of the insulating layer  220  over sidewalls of the opening  214  form the insulating elements  224 . In some embodiments, the portions of the insulating layer  220  over sidewalls of the opening  214  are also removed during the etching process. In these cases, there is no insulating element formed over sidewalls of the opening  214 . 
     As shown in  FIG.  1 L , an etching process is used to further extend the openings  218  towards the substrate  10 , in accordance with some embodiments. During the etching process, portions of the interlayer dielectric layers  202  and  102  are removed. As a result, some of the conductive pads  204  of the semiconductor die  20  and some of the conductive pads  104  of the substrate  10  are exposed. In some embodiments, the insulating elements  222   s  are made of a material that is different from those of the interlayer dielectric layers  202  and  102 . Therefore, the insulating elements  222   s  may still remain to cover and protect the semiconductor substrate  200  after the etching process. 
     As shown in  FIG.  1 M , conductive features  226   s  and  226   d  are formed in the openings  214  and  218 , in accordance with some embodiments. As shown in  FIG.  1 M , one of the conductive features  226   s  penetrates through the semiconductor substrate  200  and is in electrical contact with one of the conductive pads  204 . In some embodiments, one of the conductive features  226   s  penetrates through the semiconductor substrate  200  and the interconnection structure of the semiconductor die  20  and is in electrical contact with one of the conductive pads  104 . As mentioned above, the insulating elements  222   s  may be used to provide electrical isolation between the semiconductor substrate  200  and conductive features  226   s . In some embodiments, one of the conductive features  226   s  serves as a through-via that physically connects one of the conductive pads  104  of the substrate  10  (such as a semiconductor chip). In these cases, one of the conductive features  226   s  completely penetrates through the semiconductor die  20 . In some embodiments, the conductive feature  226   d  penetrates through the dielectric layers  210  and  206  and is in electrical contact with one of the conductive pads  104 , as shown in  FIG.  1 M . 
     In some embodiments, each of the conductive features  226   s  and  226   d  includes a barrier layer and a conductive layer. The barrier layer may be made of Ta, TaN, Ti, TiN, another suitable material, or a combination thereof. The barrier layer may be a stack of multiple sub-layers, such as a stack of TaN/Ta or TiN/Ti. The conductive layer may be made of Cu, Al, W, Au, Pt, another suitable material, or a combination thereof. In some embodiments, a seed layer is formed over the barrier layer before the formation of the conductive layer. The seed layer may include a Cu layer. 
     In some embodiments, the barrier layer is deposited over the dielectric layer  210 , the conductive pads  204  and  104 , and sidewalls of the openings  214  and  218 . The barrier layer may be deposited using a CVD process, a PVD process, another applicable process, or a combination thereof. Afterwards, the seed layer is deposited over the barrier layer using, for example, a PVD process (such as sputtering), a CVD process, another application process, or a combination thereof. Then, the conductive layer is deposited over the seed layer using, for example, an electroplating process. A planarization process is performed afterwards to remove the portions of the barrier layer, the seed layer, and the conductive layer outside of the openings  214  and  218 . The planarization process may include a CMP process, a grinding process, an etching process, another applicable process, or a combination thereof. As a result, the remaining portions of the barrier layer, the seed layer, and the conductive layer form the conductive features  226   s  and  226   d , as shown in  FIG.  1 M . 
     Afterwards, a bonding layer  228  is deposited over the dielectric layer  210  and the conductive features  226   s  and  226   d , as shown in  FIG.  1 M  in accordance with some embodiments. The bonding layer  228  is used to facilitate a subsequent bonding with one or more other semiconductor dies. The material and formation method of the bonding layer  228  may be similar to those of the interlayer dielectric layer  102  or  202 . In some other embodiments, the bonding layer  228  is not formed. 
     Afterwards, in a way that is similar to the operations shown in  FIGS.  1 A- 1 C , a semiconductor die  30  is bonded over the semiconductor die  20  through the bonding layer  228 , as shown in  FIG.  1 N  in accordance with some embodiments. In some embodiments, the bonding layer  228  is in direct contact with an interlayer dielectric layer  302  of the semiconductor die  30 . The bonding layer  228  and the interlayer dielectric layer  302  are bonded together through a type of fusion bonding (such as oxide-to-oxide bonding). In some other embodiments, the bonding layer  228  is not formed, and the top of one of the conductive features  226   s  is in direct contact with a conductive pad  304  of the semiconductor die  30 . In these cases, the semiconductor die  30  is bonded over the semiconductor die  20  through a type of hybrid bonding that includes, for example, an oxide-to-oxide bonding and a metal-to-metal bonding. 
     Although the front side (where the interconnection structure is formed) of the semiconductor die  30  faces the substrate  10  and/or the semiconductor die  20 , embodiments of the disclosure are not limited thereto. In some other embodiments, the back side of the semiconductor die  30  faces the substrate  10  and/or the semiconductor die  20 . In other words, the back side of the semiconductor die  30  is between the front side of the semiconductor die  30  and the substrate  10 . In these cases, a semiconductor substrate  300  of the semiconductor die  30  is bonded to the bonding layer  228 . In some embodiments, a dielectric film, such as an oxide film, is formed over the semiconductor substrate  300  to facilitate bonding with the bonding layer  228 . The dielectric film may be a native oxide film grown on the semiconductor substrate  300 . 
     Afterwards, in a way that is similar to the operations shown in  FIG.  1 D , a dielectric layer  306  is formed to encapsulate the semiconductor die  30 , as shown in FIG.  1 N in accordance with some embodiments. The material and formation method of the dielectric layer  306  may be similar to those of the dielectric layer  206 . Afterwards, in a way that is similar to the operations shown in  FIGS.  1 E- 1 L , an etch stop layer  308  and a dielectric layer  310  are formed, and openings penetrating through the semiconductor substrate  300  and the dielectric layer  306  are formed, in accordance with some embodiments. Some of the openings expose the conductive pad  304 , some of the opening exposes the conductive feature  226   s , and some of the openings expose the conductive feature  226   d . Insulating elements  322   s  and  322   d  may also be formed. 
     Afterwards, in a way that is similar to the operations shown in  FIG.  1 M , conductive features  326   s  and  326   d  are formed, as shown in  FIG.  1 N  in accordance with some embodiments. In some embodiments, one of the conductive features  326   s  and one of the conductive features  226   s  together form a conductive feature penetrating through the semiconductor dies  30  and  20 . In some embodiments, the conductive feature (including  226   s  and  326   s ) is in electrical contact with one of the conductive pads  104  of the substrate  10 . In some embodiments, one of the conductive features  326   d  and one of the conductive features  226   d  together form a conductive feature penetrating through the dielectric layers  306  and  206 . In some embodiments, the conductive feature (including  226   d  and  326   d ) is in electrical contact with one of the conductive pads  104  of the substrate  10 . 
     Afterwards, a dielectric layer  328  is deposited over the dielectric layer  310  and the conductive features  326   s  and  326   d , as shown in  FIG.  1 N  in accordance with some embodiments. The dielectric layer  328  may serve as a protection layer to protect the conductive features  326   s  and  326   d . The dielectric layer  328  may also be used as a bonding layer if more semiconductor dies are designed to be bonded on the semiconductor die  30 . The material and formation method of the dielectric layer  328  may be similar to those of the bonding layer  228 . Similar operations may be repeated to stack more semiconductor dies over the structure shown in  FIG.  1 N . 
     As shown in  FIG.  1 O , redistribution layers (RDL)  330  and a passivation layer  332  are formed over the dielectric layer  328 , in accordance with some embodiments. The redistribution layers  330  may be partially exposed to provide a landing area for connectors, such as solder bumps. In some embodiments, the redistribution layers  330  are made of Cu, Al, W, Au, Ti, Pt, Co, another suitable material, or a combination thereof. In some embodiments, the passivation layer  332  is made of silicon nitride, polyimide, another suitable material, or a combination thereof. 
     In some embodiments, the dielectric layer  328  is patterned to expose the conductive features such as the conductive features  326   s  and  326   d . Afterwards, a conductive layer is deposited and patterned to form the redistribution layers  330 . The conductive layer may be deposited using an electroplating process, a PVD process, a CVD process, an electroless plating process, another applicable process, or a combination thereof. Afterwards, a passivation layer  332  is deposited and patterned over the dielectric layer  328  and the redistribution layers  330 . A suitable deposition process, such as a CVD process or a spin-on process, may be used to deposit the passivation layer  332 . 
     Many variations and/or modification can be made to embodiments of the disclosure. For example, the conductive features penetrating through the semiconductor die may be formed before the bonding process for stacking semiconductor dies.  FIGS.  2 A- 2 B  are cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. 
     As shown in  FIG.  2 A , a semiconductor die  40  is provided to be bonded onto the substrate  10 , in accordance with some embodiments. The semiconductor die  40  includes a semiconductor substrate  400  and an interconnection structure including an interlayer dielectric layer  402  and conductive pads  404 . The semiconductor die  40  also includes one or more conductive features  426   s  that have been formed in the semiconductor substrate  400 . The conductive features  426   s  may penetrate through the semiconductor substrate  400  and be electrically connected to the conductive pads  404  correspondingly. There may be insulating elements or insulating layers (not shown) formed between the conductive features  426   s  and the semiconductor substrate  400 . 
     As shown in  FIG.  2 B , the semiconductor die  40  is bonded on the substrate  10 , in accordance with some embodiments. Although the back side of the semiconductor die  40  faces the substrate  10 , embodiments of the disclosure are not limited thereto. In some other embodiments, similar to the structure shown in  FIG.  1 B , the semiconductor die  40  is arranged such that the front side of the semiconductor die  40  faces the substrate  10 . The semiconductor die  40  may be bonded on the substrate  10  through fusion bonding or hybrid bonding, as mentioned above. 
     Afterwards, a dielectric layer  406  is formed to encapsulate the semiconductor die  40 , as shown in  FIG.  2 B  in accordance with some embodiments. The material and formation method of the dielectric layer  406  may be similar to those of the dielectric layer  206 . The structure shown in  FIG.  2 B  may be used as a chip package or may be integrated into another package structure. In some other embodiments, one or more levels of semiconductor dies are stacked over the semiconductor die  40 . Embodiments of the disclosure have many variations. In some other embodiments, the dielectric layer  406  is made of a molding compound. 
     Many variations and/or modifications can be made to embodiments of the disclosure.  FIG.  3    is a cross-sectional view of a chip package, in accordance with some embodiments.  FIG.  3    shows a chip package similar to that shown in  FIG.  1 O . In some embodiments, the substrate  10  includes conductive features  126  penetrating through the semiconductor substrate  100 . The conductive features  126  are used as through-vias and provide electrical paths between elements disposed over opposite sides of the semiconductor substrate  100 . In some embodiments, each of the conductive features  126  is electrically connected to a corresponding connector  397  that is formed over the back side of the semiconductor substrate  100 . In some embodiments, insulating elements (not shown) are formed between the semiconductor substrate  100  and the conductive features  126 . As shown in  FIG.  3   , connectors  399  are formed over the semiconductor die  30 , in accordance with some embodiments. 
     In some embodiments, a semiconductor die  20 ′ is also stacked on the substrate  10 , as shown in  FIG.  3    in accordance with some embodiments. The semiconductor die  20 ′ is positioned at substantially the same height level as the semiconductor die  20 . As shown in  FIG.  3   , a conductive feature  326 ′ is formed to penetrate through both of the dielectric layers  306  and  206 , in accordance with some embodiments. In some embodiments, the opening containing the conductive feature  326 ′ is formed after the bonding of the semiconductor die  30  and the formation of the dielectric layer  306 . 
     In some embodiments, the substrate  10  and/or the semiconductor dies  20 ,  20 ′, or  30  include testing pads such as testing pads  104 ′ and/or  204 ′. The testing pads  104 ′ and/or  204 ′ are used for electrical testing. Multiple testing operations may be performed to ensure the substrate  10  and/or the semiconductor dies  20 ,  20 ′, and/or  30  have good quality before they are bonded together. Therefore, the reliability and performance of the chip package are improved. In some embodiments, the testing pads  104 ′ and/or  204 ′ are made of Al, W, Cu, Au, Ti, another suitable material, or a combination thereof. However, it should be appreciated that embodiments of the disclosure are not limited thereto. In some other embodiments, the testing pads  104 ′ and/or  204 ′ are not formed. 
     In some embodiments, conductive features  226   s  are used as through-vias that form electrical connection to the substrate  10  (such as a semiconductor chip). In some embodiments, one or some of the conductive features  226   s  physically connect conductive pads  104  formed in the interlayer dielectric layer  102  of the substrate  10 . The substrate  10  may be a semiconductor chip or a semiconductor wafer. In some embodiments, there are insulating elements (not shown) formed between the conductive features  226   s  and the semiconductor substrate  200  of the semiconductor die  20 . In some embodiments, the insulating elements are similar to the insulating elements  222   s  illustrated in  FIG.  1 O . 
     Many variations and/or modifications can be made to embodiments of the disclosure. For example, some or all of the conductive features penetrating through the semiconductor substrate of the semiconductor die may be formed after the semiconductor die is bonded onto the substrate or another semiconductor die. Alternatively, some or all of the conductive features penetrating through the semiconductor substrate of the semiconductor die may be formed before the semiconductor die is bonded onto the substrate or another semiconductor die. The bonding between the substrate and the semiconductor die or the bonding between different semiconductor dies may be achieved through a fusion bonding or a hybrid bonding according to requirements. 
     Many variations and/or modifications can be made to embodiments of the disclosure.  FIGS.  4 A- 4 I  are cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. 
     As shown in  FIG.  4 A , one or more semiconductor dies such as the semiconductor dies  20  and  20 ′ are disposed over a carrier substrate  600 , in accordance with some embodiments. The semiconductor dies  20  and  20 ′ may be bonded onto the carrier substrate  600  through an adhesion layer  602 . In some embodiments, each of the semiconductor dies  20  and  20 ′ includes a testing pad  204 ′. The testing pads  204 ′ are used for electrical testing. Multiple testing operations may be performed to ensure good quality of the semiconductor dies  20  and  20 ′ before they are bonded onto the carrier substrate  600 . In some embodiments, the carrier substrate  600  includes a semiconductor substrate (such as a silicon wafer), a dielectric substrate (such as a glass wafer), another suitable substrate, or a combination thereof. 
     As shown in  FIG.  4 B , a dielectric layer  606  is deposited over the carrier substrate  600  to encapsulate the semiconductor dies  20  and  20 ′, in accordance with some embodiments. The dielectric layer  606  surrounds and covers the semiconductor dies  20  and  20 ′. The dielectric layer  606  may be used to protect the semiconductor dies  20  and  20 ′. In some embodiments, the dielectric layer  606  is in direct contact with the semiconductor dies  20  and  20 ′. In some embodiments, the material and formation method of the dielectric layer  606  are similar to those of the dielectric layer  206 . In some embodiments, a planarization process is used to provide the dielectric layer  606  with a substantially planar surface. 
     As shown in  FIG.  4 C , the structure as shown in  FIG.  4 B  is bonded onto the substrate  10 , in accordance with some embodiments. The structure shown in  FIG.  4 B  may be bonded onto the substrate  10  through a wafer-to-wafer bonding. In some embodiments, the dielectric layer  606  and the interlayer dielectric layer  102  of the substrate  10  are bonded together through a fusion bonding. In some embodiments, a portion of the dielectric layer  606  is sandwiched between the semiconductor dies  20  or  20 ′ and the substrate  10  that may be a semiconductor wafer or a semiconductor chip. 
     In some other embodiments, some of the conductive pads  204  or testing pads  204 ′ of the semiconductor dies  20  and  20 ′ are not covered by the dielectric layer  606 . Some of the conductive pads  104  or testing pads  104 ′ of the substrate  10  may be in direct contact with some of the conductive pads  204  or testing pads  204 ′ of the semiconductor dies  20  and  20 ′. In these cases, the structure as shown in  FIG.  4 B  is bonded onto the substrate  10  through a hybrid bonding. The hybrid bonding may include an oxide-to-oxide bonding and a metal-to-metal bonding. 
     In some embodiments, the substrate  10  is a wafer and includes the testing pads  104 ′. The testing pads  104 ′ are used for electrical testing. Multiple testing operations may be performed to ensure good quality of the substrate  10  before the bonding. 
     As shown in  FIG.  4 D , the carrier substrate  600  and the adhesion layer  602  are removed, in accordance with some embodiments. In some embodiments, the carrier substrate  600  and the adhesion layer  602  are removed simultaneously. In some other embodiments, the carrier substrate  600  is removed from the adhesion layer  602 . Afterwards, the adhesion layer  602  is removed from the semiconductor dies  20  and  20 ′. 
     As shown in  FIG.  4 E , a planarization process is performed to thin down the dielectric layer  606 , in accordance with some embodiments. After the planarization process, the surfaces of the dielectric layer  606  and the semiconductor dies  20  and  20 ′ are substantially coplanar. In some embodiments, the semiconductor dies  20  and  20 ′ are also thinned during the planarization process. The planarization process may include a CMP process, a grinding process, an etching process, another applicable process, or a combination thereof. 
     Afterwards, an isolation layer  608  is deposited over the dielectric layer  606  and the semiconductor dies  20  and  20 ′, as shown in  FIG.  4 E  in accordance with some embodiments. The isolation layer  608  may be used to electrically isolate multiple conductive features that will be formed later from each other. In some embodiments, the isolation layer  608  is made of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, another suitable material, or a combination thereof. In some embodiments, the isolation layer  608  is deposited using a CVD process, a spin-on process, a PVD process, another applicable process, or a combination thereof. 
     As shown in  FIG.  4 F , similar to the embodiments illustrated in  FIG.  1 M or  2   , the conductive features  226   s  and  226   d  are formed, in accordance with some embodiments. Similar to the embodiments illustrated in  FIG.  1 M , isolation elements (not shown) may be formed between the conductive features  226   s  and the semiconductor substrate  200  of the semiconductor dies  20  and  20 ′. The isolation elements are used to provide electrical isolation between the conductive features  226   s  and the semiconductor substrate  200  of the semiconductor dies  20  and  20 ′. 
     As shown in  FIG.  4 G , a redistribution layer  612  and a dielectric layer  610  are formed over the isolation layer  608  and the conductive features  226   s  and  226   d , in accordance with some embodiments. The formation of the redistribution layer  612  and the dielectric layer  610  may involve multiple deposition and patterning processes. 
     Similar to the embodiments illustrated in  FIG.  4 A , one or more semiconductor dies such as the semiconductor dies  30  and  30 ′ are bonded onto a carrier substrate  600 ′ using an adhesion layer  602 ′, as shown in  FIG.  4 H  in accordance with some embodiments. Afterwards, similar to the embodiments illustrated in  FIG.  4 B , a dielectric layer  606 ′ is formed to encapsulate the semiconductor dies  30  and  30 ′, in accordance with some embodiments. Then, similar to the embodiments illustrated in  FIG.  4 C , the dielectric layer  606 ′ and the structure as shown in  FIG.  4 G  are bonded through a hybrid bonding, as shown in  FIG.  4 H  in accordance with some embodiments. 
     As shown in  FIG.  4 I , similar to the embodiments illustrated in  FIGS.  4 F- 4 G , conductive features  626   s  and  626   d , an isolation layer  608 ′, a redistribution layer  612 ′, and a dielectric layer  610 ′ are formed, in accordance with some embodiments. Afterwards, passivation layers  692  and  696 , conductive pads  694 , and connectors  698  are formed, as shown in  FIG.  4 I  in accordance with some embodiments. 
     In some embodiments, the dielectric layers  606  and  606 ′ are substantially free of polymer material. In some embodiments, there is no molding compound or underfill material between the dielectric layer  606  and the semiconductor dies  20  and  20 ′ or between the dielectric layer  606 ′ and the semiconductor dies  30  and  30 ′. Since the dielectric layers  606  and  606 ′ are substantially free of polymer material or molding compound material, the coefficients of thermal expansion (CTE) of the dielectric layers  606  and  606 ′, the semiconductor dies  20 ,  20 ′,  30 , and  30 ′, and the substrate  10  are similar. Therefore, warpage due to CTE mismatch may be reduced or prevented. The quality and reliability of the chip package are improved. 
     Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, dummy pads are formed to improve the flatness of the semiconductor die or the substrate. Due to the improved flatness, the bonding process for stacking multiple semiconductor dies is improved accordingly.  FIGS.  5 A- 5 F  are cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. 
     As shown in  FIG.  5 A , a semiconductor substrate  700  is provided. In some embodiments, the semiconductor substrate  700  is a semiconductor wafer with device elements formed therein. Interconnection structure is formed over the semiconductor substrate  700 . The interconnection structure includes a dielectric layer  702   a  and conductive pads  704   a . In some embodiments, the conductive pads  704   a  are portions of top metal lines of the interconnection structure and are referred to as “top metals”. In some embodiments, the interconnection structure includes multiple dielectric layers, multiple conductive lines, and multiple conductive vias. 
     In some embodiments, the materials and formation methods of the conductive pads  704   a  and the dielectric layer  702   a  are similar to those of the conductive pads  104  and the interlayer dielectric layer  102 , respectively. In some embodiments, a barrier layer  703   a  is formed between the conductive pads  704   a  and the dielectric layer  702   a.    
     In some embodiments, a passivation layer  702   b  is formed over the dielectric layer  702   a  and the conductive pads  704   a , as shown in  FIG.  5 A . The passivation layer  702   b  has an opening that exposes one of the conductive pads  704   a . In some embodiments, the passivation layer  702   b  is made of silicon nitride, silicon oxide, silicon oxynitride, another suitable material, or a combination thereof. In some embodiments, a conductive feature such as a testing pad  704 ′ is formed over the exposed one of the conductive pads  704   a . The testing pad  704 ′ is used for electrical testing. In some embodiments, the testing pads  704 ′ is a aluminum pad. Multiple testing operations may be performed to ensure good quality of the device elements formed in the semiconductor substrate  700 . 
     Afterwards, a dielectric layer  702   c  is deposited over the passivation layer  702   b  and the testing pad  704 ′, as shown in  FIG.  5 B  in accordance with some embodiments. In some embodiments, the material and the formation method of the dielectric layer  702   c  are similar to those of the interlayer dielectric layer  102 . In some embodiments, a planarization process is used to provide the dielectric layer  702   c  with a substantially planar surface. The planarization process may include a CMP process, a grinding process, an etching process, another applicable process, or a combination thereof. 
     As shown in  FIG.  5 C , a conductive feature  704   b  is formed in the dielectric layer  702   c , in accordance with some embodiments. The conductive feature  704   b  may be used as a conductive via that is electrically connected to one of the conductive pads  704   a . In some embodiments, a barrier layer  703   b  is formed between the conductive feature  704   b  and the dielectric layer  702   c . One or more photolithography and etching processes may be used to form an opening that penetrates through the dielectric layer  702   c  and the passivation layer  702   b  and exposes one of the conductive pads  704   a . Afterwards, multiple deposition processes are used to deposit multiple layers over the bottom and sidewalls of the opening. The multiple layers may include a barrier layer, a seed layer, and a conductive layer. Then, a planarization process is performed to remove the portions of the multiple layers outside of the opening. As a result, the remaining portions of the multiple layers form the barrier layer  703   b  and the conductive feature  704   b.    
     As shown in  FIG.  5 D , an etch stop layer  702   d  and a dielectric layer  702   e  are deposited over the dielectric layer  702   c  and the conductive feature  704   b , in accordance with some embodiments. In some embodiments, the materials and formation methods of the etch stop layer  702   d  and the dielectric layer  702   e  are similar to those of the etch stop layer  208  and the dielectric layer  210 . 
     As shown in  FIG.  5 E , a conductive feature  704   c  and a dummy feature (or dummy pad)  705  are formed in the dielectric layer  702   e , in accordance with some embodiments. In some embodiments, a barrier layer  703   c  is formed between the conductive feature  704   c  and the dielectric layer  702   e  and/or between the dummy feature  705  and the dielectric layer  702   e . In some embodiments, multiple openings are formed in the dielectric layer  702   e  and the etch stop layer  702   d  using a photolithography process and an etching process. One of the openings exposes the conductive feature  704   b.    
     Afterwards, multiple deposition processes are used to deposit multiple layers over the bottom and sidewalls of the opening. The multiple layers may include a barrier layer, a seed layer, and a conductive layer. Then, a planarization process is performed to remove the portions of the multiple layers outside of the opening. As a result, the remaining portions of the multiple layers form the barrier layer  703   c , the conductive feature  704   c , and the dummy feature  705 . In some embodiments, the planarization process is a CMP process, a grinding process, another applicable process, or a combination thereof. As a result, a substrate  70  similar to the substrate  10  is formed, as shown in  FIG.  5 E . The substrate  70  may be a semiconductor wafer or a semiconductor chip. 
     The conductive feature  704   c  and the barrier layer  703   c  may be used as a bonding pad for bonding with another substrate, such as another semiconductor die. Similarly, the dummy feature  705  and the barrier layer  703   c  may be used as another bonding pad. However, embodiments of the disclosure are not limited thereto. In some other embodiments, the barrier layer  703   c  are not formed. In these cases, the conductive feature  704   c  and the dummy feature  705  are used as the bonding pads. 
     In some embodiments, the conductive feature  704   b  is underlying the bonding pad constructed by the conductive feature  704   c  and the barrier layer  703   c , as shown in  FIG.  5 F . In some embodiments, the conductive feature  704   b  physically connects the bonding pad. In some embodiments, another conductive feature (such as the testing pad  704 ′) is underlying the bonding pad constructed by the dummy feature  705  and the barrier layer  703   c , as shown in  FIG.  5 F . In some embodiments, the conductive feature (such as the testing pad  704 ′) is isolated from the bonding pad. For example, the conductive feature (such as the testing pad  704 ′) is isolated from the dummy feature  705  by the dielectric layer  702   c.    
     Due to the dummy feature  705 , the surfaces of the dummy feature  705 , the dielectric layer  702   e , and the conductive feature  704   c  are substantially coplanar after the planarization process, facilitating a subsequent bonding process. In some embodiments, multiple dummy features are formed in the dielectric layer  702   e . In some embodiments, these dummy features including the dummy feature  705  and other conductive features including the conductive feature  704   c  distribute over the semiconductor substrate  700  evenly to facilitate the planarization process. 
     In some cases, the dummy feature  705  is not formed. In these cases, some portions of the dielectric layer  702   e  may be recessed after the planarization process for forming the conductive feature  704   c  since there is no dummy feature to balance the polishing force. As a result, the subsequent bonding process may be negatively affected. 
     Afterwards, a substrate  80  is bonded onto the substrate  70 , as shown in  FIG.  5 F  in accordance with some embodiments. In some embodiments, the substrate  80  is a semiconductor wafer. In some other embodiments, the substrate  80  is a semiconductor die. In some embodiments, the substrate  80  includes a semiconductor substrate  800  and an interconnection structure. 
     Similar to the interconnection structure of the substrate  70 , the interconnection structure of the substrate  80  may include dielectric layers  802   a ,  802   c , and  802   e , a passivation layer  802   b , an etch stop layer  802   d , conductive pads  804   a , conductive features  804   b  and  804   c , barrier layers  803   a ,  803   b , and  803   c , and a dummy feature  805 . The conductive feature  804   c  and the barrier layer  803   c  may be used as a bonding pad. The dummy feature  805  and the barrier layer  803   c  may be used as another bonding pad. In some embodiments, the substrate  80  is bonded onto the substrate  70  through the bonding pads respectively formed on the substrates  70  and  80 . Similarly, due to the dummy feature  805 , the surfaces of the dummy feature  805 , the dielectric layer  802   e , and the conductive feature  804   c  are substantially coplanar. Therefore, the bonding process for bonding the substrates  70  and  80  together is improved. 
     As shown in  FIG.  5 F , similar to the embodiments illustrated in  FIG.  1 D , the dielectric layer  206  is deposited to encapsulate the substrate  80  to form a chip package, in accordance with some embodiments. In some embodiments, processes similar to those shown in  FIGS.  1 E- 1 O  are performed to form a chip package including more semiconductor dies. In some embodiments, the dummy feature  705  is not electrically connected to any conductive feature that penetrates through the dielectric layer  206 . 
     In the embodiments illustrated in  FIGS.  5 A- 5 F , bonding pads are used for bonding the substrates  70  and  80 . In some embodiments, bonding pads are used in the embodiments shown in  FIG.  1 A- 1 O or  3    to assist in the bonding process. In some embodiments, through-vias similar to the conductive features  226   s ,  226   d  are formed in the substrate  80  to form electrical connection to the substrate  70 . One of the through-vias may penetrate through the dielectric layer  206  and physically connects one of the conductive pads  704   a  of the substrate  70  (such as a semiconductor chip). One of the through-vias may penetrates through the semiconductor substrate  800  of the substrate  80  (such as a semiconductor die) and physically connects one of the conductive pads  704   a  of the substrate  70  (such as a semiconductor chip). 
     Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the dielectric layer  206  is made of a molding compound. 
     Many variations and/or modifications can be made to embodiments of the disclosure. For example, the formation of the dummy feature is not limited to those illustrate in  FIGS.  5 A- 5 F .  FIGS.  6 A- 6 E  are cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. 
     As shown in  FIG.  6 A , a seed layer  903  is deposited over the structure as shown in  FIG.  5 C , in accordance with some embodiments. In some embodiments, a barrier layer (not shown) is deposited over the structure as shown in  FIG.  5 C  before the deposition of the seed layer  903 . 
     As shown in  FIG.  6 B , a mask layer  904  is formed over the seed layer  903 , in accordance with some embodiments. The mask layer  904  has openings that expose the seed layer  903 . The openings define the positions where the conductive feature  704   c  and the dummy feature  705  are formed. In some embodiments, the mask layer  904  is made of a photoresist material. A photolithography process may be used to form the openings. Afterwards, an electroplating process or another applicable process is used to deposit conductive material over the portions of the seed layer  903  exposed by the openings. As a result, the conductive feature  704   c  and the dummy feature  705  are formed. In some embodiments, the conductive material does not fill the openings completely. 
     As shown in  FIG.  6 C , the mask layer  904  is removed, and the seed layer  903  is partially removed, in accordance with some embodiments. In some embodiments, the conductive feature  704   c  and the dummy feature  705  are used as a mask, and an etching process is performed to partially remove the seed layer  903 . In some embodiments, portions of the seed layer  903  below the conductive feature  704   c  and the dummy feature  705  are removed, as shown in  FIG.  6 C . 
     As shown in  FIG.  6 D , a dielectric layer  702   e ′ is deposited over the dielectric layer  702   c  to surround the conductive feature  704   c  and the dummy feature  705 , in accordance with some embodiments. In some embodiments, a planarization process is performed such that surfaces of the dielectric layer  702   e ′, the conductive feature  704   c , and the dummy feature  705  are substantially coplanar. Due to the dummy feature  705 , the surfaces of the dummy feature  705 , the dielectric layer  702   e ′, and the conductive feature  704   c  are substantially coplanar after the planarization process, facilitating a subsequent bonding process. In some embodiments, multiple dummy features are formed in the dielectric layer  702   e ′. In some embodiments, these dummy features including the dummy feature  705  and other conductive features including the conductive feature  704   c  distribute over the semiconductor substrate  700  evenly to facilitate the planarization process. 
     As shown in  FIG.  6 E , similar to the embodiments illustrated in  FIG.  5 F , a substrate  80 ′ is bonded onto the substrate  70 ′, as shown in  FIG.  6 E  in accordance with some embodiments. In some embodiments, the substrate  80 ′ is a semiconductor wafer. In some other embodiments, the substrate  80 ′ is a semiconductor die. In some embodiments, similar to the substrate  80 , the substrate  80 ′ includes the semiconductor substrate  800  and an interconnection structure. Similar to the interconnection structure of the substrate  70 ′ or the substrate  80 , the interconnection structure of the substrate  80 ′ may include the dielectric layers  802   a ,  802   c , and  802   e ′, the passivation layer  802   b , the etch stop layer  802   d , the conductive pads  804   a , the conductive features  804   b  and  804   c , the barrier layers  803   a ,  803   b , and  803   c , a seed layer  903 ′, and the dummy feature  805 . Similarly, due to the dummy feature  805 , the surfaces of the dummy feature  805 , the dielectric layer  802   e ′, and the conductive feature  804   c  are substantially coplanar. Therefore, the bonding process for bonding the substrates  70 ′ and  80 ′ together is improved. 
     As shown in  FIG.  6 E , similar to the embodiments illustrated in  FIG.  1 D , the dielectric layer  206  is deposited to encapsulate the substrate  80 ′ to form a chip package, in accordance with some embodiments. In some embodiments, processes similar to those shown in  FIGS.  1 E- 1 O  are performed to form a chip package including more semiconductor dies. 
     The dummy features (or dummy pads) mentioned above may be used in many embodiments of the disclosure. In some embodiments, the dummy features are formed in the embodiments illustrated in  FIG.  1 D,  1 M,  1 N,  1 O,  2 B,  3 ,  4 F , or  4 I. 
     Many variations and/or modifications can be made to embodiments of the disclosure. As mentioned above, the chip package in accordance with embodiments of the disclosure may further be integrated into another package structure. In some embodiments, the chip package illustrated in the embodiments shown in  FIG.  1 D,  1 M,  1 N,  1 O,  2 B,  3 ,  4 F,  4 I,  5 F or  6 E  is further packaged in an integrated fan-out (InFO) package structure. 
       FIG.  7    is a cross-sectional view of a package structure, in accordance with some embodiments. In some embodiments, the package structure includes a molding compound layer  1004  that partially or completely encapsulating an element  1002 . In some embodiments, the element  1002  includes a semiconductor die. In some embodiments, the element  1002  is a chip package. The chip package includes the embodiments illustrated in  FIG.  1 D,  1 M,  1 N,  1 O,  2 B,  3 ,  4 F,  4 I,  5 F or  6 E . 
     In some embodiments, the package structure includes one or more through package vias  1006  that penetrate through the molding compound layer  1004 . In some embodiments, one or more semiconductor dies  1008  are disposed over redistribution layers  1012  formed on the molding compound layer  1004  and the element  1002 , as shown in  FIG.  7   . In some embodiments, connectors  1010  are formed over other sides of the molding compound layer  1004  and the element  1002 . In some embodiments, the through package vias  1006  form electrical connections between the semiconductor dies  1008  and the connectors  1010 . In some embodiments, some of the redistribution layers  1012  form electrical connections between the semiconductor dies  1008  and the semiconductor dies in the element  1002 . 
     Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, the fan-out package structure mentioned above or the chip package illustrated in the embodiments shown in  FIG.  1 D,  1 M,  1 N,  1 O,  2 B,  3 ,  4 F,  4 I,  5 F or  6 E  is further packaged in a chip-on-wafer-on-substrate (CoWoS) package structure. 
     Embodiments of the disclosure stack one or more semiconductor dies over a substrate. Conductive features penetrating through the semiconductor die or the dielectric layer are also formed to provide electrical connection in a vertical direction. The size of the chip package is further reduced. The semiconductor dies are encapsulated using a dielectric layer substantially made of semiconductor oxide material. Therefore, the coefficients of thermal expansion of the dielectric layer, the semiconductor dies, and the substrate are similar. Warpage due to CTE mismatch may be reduced or prevented. The quality and reliability of the chip package are improved. 
     In accordance with some embodiments, a chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip. 
     In accordance with some embodiments, a chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer encapsulating the semiconductor die, and dielectric layer is substantially free of polymer material. The chip package further includes a conductive feature penetrate through a semiconductor substrate of the semiconductor chip and a connector over the semiconductor substrate and electrically connected to the conductive feature. The semiconductor chip is between the semiconductor die and the connector. 
     In accordance with some embodiments, a chip package is provided. The chip package includes a semiconductor chip and a semiconductor die bonded to the semiconductor chip. The semiconductor die is in direct contact with the semiconductor chip. The chip package also includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.