Patent Publication Number: US-7593476-B2

Title: Data scrambler generation of pseudo-random bit sequence for semi-stationary Q-mode signal

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation of U.S. patent application Ser. No. 09/906,410, filed Jul. 16, 2001 now U.S. Pat. No. 7,054,379, the complete subject matter of which is hereby incorporated herein by reference in its entirety. 
     This application makes reference to, and claims priority to and the benefit of, U.S. provisional application Ser. No. 60/241,126 filed Oct. 16, 2000. 
    
    
     INCORPORATION BY REFERENCE 
     The above-referenced U.S. provisional application Ser. No. 60/241,126 is hereby incorporated herein by reference in its entirety. 
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     N/A 
     BACKGROUND OF THE INVENTION 
     Current ADSL modem system designs do not incorporate a low power transmission mode. Such systems require high power dissipation in the modem line driver, even when no data is being transmitted. 
     Accordingly, ITU contributions have proposed a low power mode (i.e., “Q-mode,”) in the transmitter. During the proposed Q-mode, the modem is still in the ready state, but enters a low power mode during periods of no data transmission. 
     One ITU contribution, HC-029R1, formally defines a semi-stationary Q-mode signal, that employs a pair of pseudo-random bit sequence (“PRBS”) generators, each with a period of greater than 4000. One problem with this proposal, however, is that the receiver would require synchronization to two PRBS generators. In addition, requiring two PRBS generators as such correspondingly requires additional hardware in the modem, as well as additional overhead associated with the overall system. Moreover, during the non-Q-mode periods of operation, i.e., during data mode or “SHOWTIME,” the two PRBS generators sit idle. 
     Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings. 
     BRIEF SUMMARY OF THE INVENTION 
     Aspects of the present invention may be found in communication system having a data communication node. The data communication node may be, for example, a modem (such as an ADSL modem). The data communication node in turn has a transmitter, which itself has a scrambler. 
     The transmitter uses the scrambler to operate in two modes. The first mode is a data communication mode, which, in the case when the data communication node is an ADSL modem, is SHOWTIME. During the data communication mode, the scrambler is used to scramble data that is communicated by the transmitter. 
     The second mode is a non-data mode, which in the case when the data communication node is an ADSL transmitter, may be Q-mode. During the non-data mode, the scrambler is used to generate a non-data mode signal. 
     In one embodiment of the invention, a determination is made whether data is present at one or more inputs to the system. If it is determined that data is present, a determination is then made whether the scrambler is configured for the data communication mode. If it isn&#39;t, the scrambler is configured for the data communication mode, and the system operates in that mode. If it is indeed configured for the data communication mode, then the system simply operates in that mode. 
     If it is determined that no data is present, a determination is then made whether the scrambler is configured for the non-data mode. If it isn&#39;t, the scrambler is configured for the non-data mode, and the system operates in that mode. If it is indeed configured for the non-data mode, then the system simply operates in that mode. 
     In one embodiment of non-data mode operation, a non-data mode input to the scrambler is selected. A non-data mode signal is then generated, using a first output of the scrambler. Next, the non-data mode signal is output, using a second output of the scrambler, for communication by the transmitter. This process is repeated for successive outputs of the scrambler, for as long as the non-data mode input to the scrambler is selected. 
     These and other advantages and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1  is a block diagram of a generic communication system that may be employed in connection with the present invention. 
         FIG. 2  is a functional block diagram of an ADSL modem transmitter according to the present invention. 
         FIG. 3  is a schematic block diagram illustrating one embodiment by which the scrambler of  FIG. 2  performs the two functions shown in  FIG. 2 . 
         FIG. 4  is a block diagram of one embodiment of Q-mode signal generation circuitry in accordance with the present invention. 
         FIG. 5  illustrates a more detailed embodiment of the Q-mode signal generation circuitry of  FIG. 4 . 
         FIG. 6  is a flow diagram of overall control for mode selection in accordance with the present invention. 
         FIG. 7  is a depiction of a generic scrambler that may be employed in connection with the present invention. 
         FIG. 8  is one specific embodiment of a scrambler that may be employed in connection with the present invention. 
         FIG. 9  is a scrambler based on the scrambler of  FIG. 8  but with alternate outputs selected in such a way that two separate output streams are produced. 
         FIG. 10  is a depiction of a generic PRBS generator in accordance with the present invention. 
         FIG. 11  is one specific embodiment of the PRBS generator of  FIG. 10  in accordance with the present invention. 
         FIG. 12  is a PRBS generator based on the PRBS generator of  FIG. 11 , but with alternate outputs selected in such a way that two separate output streams are produced, in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  is a block diagram of a generic communication system that may be employed in connection with the present invention. The system comprises a first communication node  101 , a second communication node  111 , and a channel  109  that communicatively couples the nodes  101  and  111 . The communication nodes may be, for example, ADSL modems or any other type of transceiver device that transmits or receives data over a channel. The first communication node  101  comprises a transmitter  105 , a receiver  103  and a processor  106 . The processor  106  may comprise, for example, a microprocessor. The first communication node  101  is communicatively coupled to a user  100  (e.g., a computer) via communication link  110 , and to the channel  109  via communication links  107  and  108 . 
     Similarly, the second communication node  111  comprises a transmitter  115 , a receiver  114  and a processor  118 . The processor  118 , like processor  106 , may comprise, for example, a microprocessor. The second communication node  111  is likewise communicatively coupled to a user  120  (again a computer, for example) via communication link  121 , and to the channel  109  via communication links  112  and  113 . 
     During operation, the user  100  can communicate information to the user  120  using the first communication node  101 , the channel  109  and the second communication node  111 . Specifically, the user  100  communicates the information to the first communication node  101  via communication link  110 . The information is transformed in the transmitter  105  to match the restrictions imposed by the channel  109 . The transmitter  105  then communicates the information to the channel  109  via communication link  107 . The receiver  114  of the second communication node  111  next receives, via communication link  113 , the information from the channel  109  and transforms it into a form usable by the user  120 . Finally, the information is communicated from the second communication node  111  to the user  120  via the communication link  121 . 
     Communication of information from the user  120  to the user  100  may also be achieved in a similar manner. In either case, the information transmitted/received may also be processed using the processors  106 / 118 . 
       FIG. 2  is a functional block diagram of an ADSL modem transmitter according to the present invention. A transmitter  201  comprises a scrambler  203  and control  205 . Control  205  causes the transmitter  201  to operate in two different modes, namely a data transmission or “SHOWTIME” mode (designated functionally by block  207 ) and a non-data mode or “Q-mode” (designated functionally by block  209 ). The non-data mode may be, for example, a quiescent, low power mode. While a switch  211  is shown in  FIG. 2  as selecting between the data and non-data modes, the switch  211  is not necessarily a hardware switch per se, but rather an abstract selection mechanism, as explained more completely below. 
       FIG. 3  is a schematic block diagram illustrating one embodiment by which the scrambler of  FIG. 2  performs the two functions shown in  FIG. 2 . Similar to control  205  of  FIG. 2 , control  301  acts as a selector between Q-mode operation and data operation. In Q-mode, control  301  selects “1” as the input to scrambler  303 , employs the scrambler  303  output for Q-mode purposes, and selects the Q-mode signal as the output of multiplexor  305 . 
     In data mode, control  301  selects the input of scrambler  303  to be unscrambled data, employs the output of the scrambler  303  to be scrambled data, and selects the data mode signal as the output of multiplexor  305 . In either mode, the output of multiplexor  305  is sent to a line driver (not shown). 
     As can be appreciated from  FIGS. 2 and 3 , a single scrambler is used to scramble the data during data transmission and to control the generation of the Q-mode signal. 
       FIG. 4  is a block diagram of one embodiment of Q-mode signal generation circuitry in accordance with the present invention. When Qmode is selected (i.e., “1” at the input of scrambler  401 ), the scrambler  401  switches between generating the Q-mode signal and outputting the Q-mode signal. More specifically, for each symbol of the Q-mode signal, two successive outputs from the scrambler  401  are used. The first output selects whether the basic symbols (i.e., S 1  and S 2 ) or their inverses should be generated. In the embodiment of  FIG. 4 , if the first output is “0,” then S 1  and S 2  are presented at the input of multiplexor  403 . If instead the first output is “1,” then the inverse of S 1  and S 2  are presented at the inputs of multiplexor  403 . 
     The second output of scrambler  401  is then presented to control  405 , which selects the output of the multiplexor  403 . The output of multiplexor  403  represents the Q-mode signal. 
       FIG. 5  illustrates a more detailed embodiment of the Q-mode signal generation circuitry of  FIG. 4 . A scrambler  501  with its input clamped to one generates an output sequence of bits at a rate equal to twice the symbol rate of the system. The outputs of the scrambler  501  are alternately connected to a first input  505  and a second input  507  by means of a switch  503 . The first input  505  is used by multiplier  513  to either invert or not invert (i.e. multiply by +1 or −1) a stationary signal  509  resulting in a first signal  514 . The same first input  505  also is used by multiplier  515  to either invert or not invert a non-stationary signal  511 , resulting in a second signal  516 . The first signal  514  and the second signal  516  form the inputs to a multiplexor  517 . 
     The second input  507  is applied to the input of a serial-to-parallel convertor  531  that converts groups of bits from the second input  507  to a first 8-bit integer  535 . A duty cycle  533  (i.e. a positive number between 0 and 1) is scaled in scaler  534  to an 8-bit positive integer (i.e., an integer between 0 and 255 inclusive) to produce a second 8-bit integer  537 . A comparator  539  produces an output  518  that is 1 whenever the first 8-bit integer  535  is less than the second 8-bit integer  537 ; the output  518  is 0 otherwise. The output  518  is the select input  519  of multiplexor  517 . The output of multiplexor  517  is Q-mode signal  521 , which is comprised of first signal  514  whenever the select input  519  is “1,” and second signal  516  whenever the select input  519  is “0.” 
     A final multiplexor  525 , operating under control of Q-mode enable  527 , has an output signal  529  that is Q-mode signal  521  whenever Q-mode enable  527  is 1; the output signal  529  is the data mode signal  523  whenever Q-mode enable  527  is “0.” Subsequent processing stages in the ADSL transmitter convert the output signal  529  into a signal that is transmitted by the ADSL transmitter. 
       FIG. 6  is a flow diagram of overall control for mode selection in accordance with the present invention. First, inputs to the system are examined (block  601 ). “Inputs” may be, for example, user data, internally generated overhead data (e.g., system status or commands), etc., or no data at all. If it is determined that data is present at the inputs (block  603 ), then a determination is made whether the system is in the data mode (block  605 ). If the system is indeed in the data mode, the system simply operates in the data mode (block  607 ). If it is not in the data mode (as determined at block  605 ), the system first configures the scrambler for data mode operation (block  609 ), and then operates in the data mode (block  607 ). 
     If, on the other hand, it is determined that no data is present at the inputs (block  603 ), then a determination is made whether the system is in Q-mode (block  611 ). If the system is indeed in Q-mode, the system simply operates in Q-mode (block  613 ). If it is not in Q-mode (as determined at block  611 ), the system first configures the scrambler for Q-mode operation (block  615 ), and then operates in Q-mode (block  613 ). 
       FIG. 7  is a depiction of a generic scrambler that may be employed in connection with the present invention. Scrambler  701  outputs a pseudo random bit sequence with a period of 2 N −1, where each of j 1 , j 2 , . . . j N  comprises one of “0” or “1” and {j 1 , j 2 , . . . j N } (not all equal to “1”) represents the initial state of the scrambler  701 . {c 1 , c 2  . . . c N } represents the coefficients of a primitive polynomial. 
       FIG. 8  is one specific embodiment of the scrambler of  FIG. 7  that may be employed in connection with the present invention. Scrambler  801  is defined for ADSL data transmission in G.992.1 and G.992.2. The scrambler  801  of  FIG. 8  is based on the primitive polynomial 1⊕x −18  ⊕x −23  with the ⊕ symbol used to denote addition mod  2 . When the scrambler  801  input is clamped to “1,” the scrambler  801  output becomes a pseudo-random bit sequence with a period of 2 23 −1. 
     To consider the randomness qualities of the scrambler of  FIG. 8 , let the sequence {a j , a j+1 , a j+2 , . . . } represent the output sequence emitted by the scrambler with its input clamped to one where j is an arbitrary integer representing time. Assume further that the initial state of the scrambler is {a j+1 , a j+2 , . . . , a j+23 } for some j. Then subsequent outputs of the scrambler are defined by the above primitive polynomial to be
 
a i =1⊕a i−18 ⊕a i−23  for all integer values of i.  (1)
 
Equivalently,
 
a i ⊕a i−18 ⊕a i−23 =1,  (2)
 
it being understood that binary arithmetic is being used.
 
     Equation (2) expresses the fundamental recurrence relation for the scrambler of  FIG. 8 . Further properties of this scrambler make it attractive for generating pseudo-random sequences. Of course, a whole family of scramblers can be defined in a similar way. 
     Consider the structure of scrambler  901  of  FIG. 9 , which is based on the scrambler of  FIG. 8  but with alternate outputs selected in such a way that two separate output streams are produced. To determine the randomness properties of the resulting subsequences, let {b i } represent the output sequence obtained by selecting the even-numbered outputs of the master scrambler. That is, let
 
b i =a 2i  for all i.  (3)
 
It is asserted that the {b i } sequence defined by (3) also satisfies Equation (2), which means that {b i } is also a PRBS sequence with all the properties possessed by the {a j } sequence. That is, it is asserted that
 
b i ⊕b i−18 ⊕b i−23 =1.  (4)
 
Substituting (3) into (4), the assertion is that
 
a 2i ⊕a 2i−36 ⊕a 2i−46 =1.  (5)
 
To prove this assertion, note that from (1) we know that
 
                       a     2   ⁢   i       =     1   ⊕     a       2   ⁢   i     -   18       ⊕     a       2   ⁢   i     -   23           ,     
     ⁢             a       2   ⁢   i     -   18       =     1   ⊕     a       (       2   ⁢   i     -   18     )     -   18       ⊕     a       (       2   ⁢   i     -   18     )     -   23                     =     1   ⊕     a       2   ⁢   i     -   36       ⊕     a       2   ⁢   i     -   41                         (   6   )               
from which
 a 2i−36 =1⊕a 2i−18 ⊕a 2i−41   (7) 
Also from (1),
 
                           a       2   ⁢   i     -   23       =     1   ⊕     a       (       2   ⁢   i     -   23     )     -   18       ⊕     a       (       2   ⁢   i     -   23     )     -   23                     =     1   ⊕     a       2   ⁢   i     -   41       ⊕     a       2   ⁢   i     -   46                                       
from which
 a 2i−46 =a 2i−23 ⊕a 2i−41.   (8) 
Substituting (7) and (8) into the left-hand side of (5) we have
 
                       a     2   ⁢   i       ⊕   1   ⊕     a       2   ⁢   i     -   18       ⊕     a       2   ⁢   i     -   41       ⊕   1   ⊕     a       2   ⁢   i     -   23       ⊕     a       2   ⁢   i     -   41         =       a       2   ⁢   i     -   41       ⊕     a       2   ⁢   i     -   18       ⊕       a       2   ⁢   i     -   23       ⁢           ⁢     (   9   )                     =     1   ⁢           ⁢     (   10   )                   
from (2) with i replaced by 2i. The chain of implications just navigated shows that
 b i ⊕b i−18 ⊕b i−23 =1  (4) 
as was asserted. Therefore, the sequence, {b i } obtained by selecting the even-numbered outputs of the master scrambler is, itself, a PRBS sequence with the same randomness properties as that of the master scrambler. A similar argument proves that the sequence obtained by selecting the odd-numbered outputs of the master scrambler also is a PRBS sequence with the same randomness properties as the master scrambler.
 
     An embodiment with exactly similar properties (except that the bit sequence is inverted) obtains when a PRBS generator is substituted for the scrambler.  FIG. 10  is a depiction of a generic PRBS generator that may be employed in connection with the present invention. PRBS generator  1001  outputs a pseudo random bit sequence with a period of 2 N −1, where each of i 1 , i 2 , . . . i N  comprises one of “0” or “1” and {i 1 , i 2 , . . . i N } (not all equal to “0”) represents the initial state of the PRBS generator  1001 . {c 1 , c 2  . . . c N } represents the coefficients of a primitive polynomial. 
       FIG. 11  is one specific embodiment of the PRBS generator of  FIG. 10  in accordance with the present invention. The PRBS generator  1101  of  FIG. 11  is based on the same polynomial as that upon which  FIG. 8  is based. To consider the randomness qualities of  FIG. 11 , let the sequence {a j , a j+1 , a j+2 , . . . } represent the output sequence emitted by the PRBS where j is an arbitrary integer representing time. Assume further that the initial state of the generator is {a j+1 , a j+2 , . . . , a j+23 } for some j. Then subsequent outputs of the PRBS generator are defined by the above primitive polynomial to be
 a i =a i−18 ⊕a i−23  for all integer values of i.  (1) 
Equivalently,
 a i ⊕a i−18 ⊕a i−23 =0,  (2) 
it being understood that binary arithmetic is being used.
 
     Equation (2) expresses the fundamental recurrence relation for the PRBS generator. Further properties of. this PRBS generator make it attractive for generating pseudo-random sequences. Of course, a whole family of PRBS generators can be defined in a similar way. 
     Consider the structure of PRBS generator  1201  of  FIG. 12 , which is based on the PRBS generator of  FIG. 11 , but with alternate outputs selected in such a way that two separate output streams are produced (in accordance with the present invention). To consider the randomness qualities of the scrambler  1201  of  FIG. 12 , let {b i } represent the output sequence obtained by selecting the even-numbered outputs of the master PRBS generator. That is, let
 
b i =a 21  for all i.  (3)
 
It is asserted that the {b 1 } sequence defined by (3) also satisfies Equation (2), which means that {b i } is also a PRBS sequence with all the properties possessed by the {a i } sequence. That is, it is asserted that
 
b i ⊕b i−18 ⊕b i−23 =0.  (4)
 
Substituting (3) into (4), the assertion is that
 
a 2i ⊕a 2i−36 ⊕a 2i−46 =0.  (5)
 
To prove this assertion note that from (1) we know that
 
                       a     2   ⁢   i       =       a       2   ⁢   i     -   18       ⊕     a       2   ⁢   i     -   23           ,     
     ⁢             a       2   ⁢   i     -   18       =       a       (       2   ⁢   i     -   18     )     -   18       ⊕     a       (       2   ⁢   i     -   18     )     -   23                     =       a       2   ⁢   i     -   36       ⊕     a       2   ⁢   i     -   41                         (   6   )               
from which
 a 2i−36 =a 2i−18 ⊕a 2i−41   (7) 
Also from (1),
 
                     a       2   ⁢   i     -   23       =       a       (       2   ⁢   i     -   23     )     -   18       ⊕     a       (       2   ⁢   i     -   23     )     -   23                     =       a       2   ⁢   i     -   41       ⊕     a       2   ⁢   i     -   46                     
from which
 a 2i−46 =a 2i−23 ⊕a 2i−41   (8) 
Substituting (6), (7), and (8) into the left-hand side of (5) we have
 
                       a     2   ⁢   i       ⊕     a       2   ⁢   i     -   18       ⊕     a       2   ⁢   i     -   41       ⊕     a       2   ⁢   i     -   23       ⊕     a       2   ⁢   i     -   41         =       a     2   ⁢   i       ⊕     a       2   ⁢   i     -   18       ⊕       a       2   ⁢   i     -   23       ⁢           ⁢     (   9   )                     =     0   ⁢           ⁢     (   10   )                   
from (2) with i replaced by 2i. The chain of implications just navigated shows that
 b i ⊕b i−18 ⊕b i−23 =0  (4) 
as asserted. Therefore, the sequence, {b i }, obtained by selecting the even-numbered outputs of the master PRBS generator is, itself, a PRBS sequence with the same randomness properties as that of the master PRBS generator. A similar argument proves that the sequence obtained by selecting the odd-numbered outputs of the master PRBS generator also is a PRBS sequence with the same randomness properties as the master PRBS generator.
 
     Many modifications and variations of the present invention are possible in light of the above teachings. Thus, it is to be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as described hereinabove.