Patent Publication Number: US-8125252-B2

Title: Multi-phase signal generator and method

Description:
CROSS REFERENCE TO RELATED APPLICATION(S) 
     This application is a continuation of pending U.S. patent application Ser. No. 12/245,444, filed Oct. 3, 2008, which application is incorporated herein by reference, in its entirety, for any purpose. 
    
    
     TECHNICAL FIELD 
     Embodiments of the invention relate generally to periodic signal generating systems, and more particularly, in one or more embodiments, to methods and systems for fast initializing a multi-phase clock signal generator. 
     BACKGROUND OF THE INVENTION 
     Periodic signals are used in a variety of electronic devices. One type of periodic signals are clock signals that can be used to establish the timing of a signal or the timing at which an operation is performed on a signal. For example, data signals are typically coupled to and from memory devices, such as synchronous dynamic random access memory (“SDRAM”) devices, in synchronism with a clock signal. More specifically, read data signals are typically coupled from a memory device in synchronism with a read data strobe signal. The read data strobe signal typically has the same phase as the read data signals, and it is normally generated by the same memory device that is outputting the read data signals. Write data signals are typically latched into a memory device in synchronism with a write data strobe signal. The write data strobe signal should have a phase that is the quadrature (having a phase 90-degrees relative to the phase) of the write data signals so that a transition of the write data strobe signal occurs during a “data eye” occurring at the center of the period in which the write data signals are valid. 
     Internal clock signals generated in electronic devices, for example, memory devices or memory controllers, are often synchronized or have some other controlled phase relationships relative to external or internal clock signals. For example, with reference to a memory device, a quadrature clock signal used for latching write data and outputting read data may be generated in the memory device to which the data are being written. The quadrature clock signal is typically generated in the memory device from an internal clock signal that is also derived from the system clock signal. 
     Internal clock signals having synchronized or some other controlled phase relationships with external and internal clock signals may also be used for applications other than for use as a write data and outputting read data strobe signal. For example, a “frequency doubler” circuit, which generates an output clock signal having twice the frequency of an input clock signal, can be implemented using an appropriate logic circuit that receives the input clock signal and quadrature versions of the input clock signal. Internal clock signals may also be generated having other than a quadrature phase relationships. Generally, any phase relationship between output clock signals can be used. 
     Various techniques can be used to generate a quadrature clock signal or read/write data strobe signal. If the frequency of the internal clock signal is fixed, quadrature clock signals can be generated by a timing circuit that simply generates a transition of the quadrature clock signals a fixed time after a corresponding transition of the internal clock signal. However, synchronous memory devices are typically designed and sold to be operated over a wide range of clock frequencies. Therefore, it is generally not practical to use a fixed timing circuit to generate quadrature signals from the internal clock signal. Instead, a circuit that can adapt itself to an internal clock signal having a range of frequencies must be used. 
     An example of such a circuit is a multi-phase clock signal generator. A multi-phase clock signal generator, as known, generates multi-phase clock signals to provide several clock signals having fixed phase relationships to a reference clock signal, such as an external or internal clock signal. In operation, a multi-phase clock signal generator should be initialized to ensure the generated clock signals have the correct phase relationship. A conventional method of initializing a multi-phase clock signal generator will now be described with reference to  FIG. 1 . The conventional multi-phase clock signal generator  100  includes a delay line  105  having a plurality of delay elements  110   a - d  coupled in series with each other. Each of the delay elements  110   a - d  has two inputs, two outputs, and a control input (not shown). Each delay element  110   a - d  has two inputs and two outputs to provide for a double-ended configuration where both a clock signal  120  and its complement  121  are received and processed. A single-ended configuration may also be used. 
     Each of the delay elements  110   a - d  couples a signal from its input to its output with a delay corresponding to a delay control signal applied to its control input. The input of the initial delay element  110   a  receives a clock signal  120  and its complement  121 . The outputs of all but the last delay element  110   d  is coupled to the input of the subsequent delay element. The output of each delay element  110   a - d  forms a respective tap of the delay line  105  to provide four clock signals C 90 , C 180 , C 270 , and C 360 , respectively, C 360  is a one clock delayed version of C 0  at lock status. As indicated by their names, the C 90  signal has a 90 degree phase difference with the input clock signal  120 . The C 180  signal has a 180 degree phase difference with the input clock signal  120 , the C 270  signal a 270 degree phase difference, and the C 360  signal a 360 degree phase difference. As explained in greater detail below, the amount of voltage-controlled delay provided by each of the delay elements  110   a - d  sets a minimum and maximum amount of delay that can be achieved by the delay line  105 . 
     To ensure the proper phase relationships are maintained correctly during operation between the four provided clock signals, a two-step locking phase detector  130  receives the input clock signal  120 , the C 180  signal and the C 360  signal. The phase detector  130  will first lock the inversion of C 180  signal to the C 0  signal, and then in the second step, lock the C 360  signal with the C 0  signal. To lock the C 0  and C 180  signal, the phase detector  130  produces an error signal corresponding to a mismatch between the falling edge of the C 180  signal and the rising edge of the C 0  signal. The error signal is used to adjust the delay of the delay elements  110   a - d  such that the C 0  and C 180  signals are 180 degrees apart. As shown in  FIG. 1 , the error signal is converted to a control signal by a control signal generator, such as charge-pump and loop filter  140 . The control signal is used by a bias voltage generator  150  to couple a V BIAS  signal to the control inputs of the delay elements  110   a - d . In the second step of operation of the phase detector  130 , an error signal is generated corresponding to a mismatch between a rising edge of the C 0  signal and a rising edge of the C 360  signal. In a similar manner, the error signal is used to adjust the delay of the delay elements  110   a - d . This two-step locking process may be sufficient in some cases where the duty cycle or slow locking time is not an issue. However, difficulties occur when the incoming clock signal contains some duty cycle distortion, as will now be explained with reference to  FIG. 2 . 
       FIG. 2  is a timing diagram illustrating signals from  FIG. 1 . A clock period is shown in  FIG. 2  as t CK , between t 0  and t 2 . The incoming clock signal, C 0  has an amount of duty cycle distortion shown by t DCD . That is, in the case where the C 0  signal had an ideal, 50 percent duty cycle, the high pulse would extend from time t 0  to time t 1  in  FIG. 2 . However, as shown, the C 0  high pulse is significantly shorter. The phase detector  130  then locks the falling edge of the C 180  signal with the rising edge of the C 0  signal at time t 2 , as shown by arrow  210 . The phase detector  130  will lock the signals within a tolerance, shown by ±t PDmin  in  FIG. 2 . Due to the duty cycle distortion, the rising edge of the C 180  signal is t x1  off from time t 1 , where the signal should be for a 180 degree phase difference. Accordingly, the C 180  signal has been delayed t x1  too much. Recall that adjusting the control voltage applied to the delay elements  105  of  FIG. 1  adjusts the delay of all the delay elements  110   a - d . The C 360  signal will now be 2*t x1  off from locked with C 0 , as shown in  FIG. 2 . The second step of operation of the phase detector  130  will be to adjust the delay of the delay elements  110   a - d  such that the C 360  signal is synchronized with the C 0  signal, by matching the rising edge of the C 0  signal with the rising edge of the C 360  signal, as shown in the second timing diagram of  FIG. 2  by the arrow  220 . 
     Duty cycle distortion in incoming clock signals is not uncommon, and, taking signal jitter into consideration, could be a significant portion of reference clock period. With duty cycle distortion, the two-step locking phase detector  130  may cease to function properly. The delay line  105  may have insufficient range to accommodate the lengthy t x1  and 2*t x1  delay times that should be compensated for according to  FIG. 2 . One solution to this problem is to place a duty-cycle control element prior to and in series with the multi-phase clock signal generator  100 . This may ensure the multi-phase clock signal generator receives a clock signal with a correct duty cycle. However, a duty cycle control element also has a limited working range and takes much longer time to achieve corrected output signals. Accordingly, this solution may also become impractical as speeds increase and timing requirements tighten. 
     There is accordingly a need for an improved system and method for providing multi-phase clock signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a multi-phase clock signal generator according to the prior art. 
         FIG. 2  is a timing diagram illustrating the operation of the clock signal generator of  FIG. 1 . 
         FIG. 3  is a schematic diagram of a multi-phase clock signal generator according to an embodiment of the present invention. 
         FIG. 4  is a timing diagram illustrating the operation of the signal generator of  FIG. 3 . 
         FIG. 5  is a schematic diagram of a multi-phase clock signal generator according to an embodiment of the present invention. 
         FIG. 6  is a timing diagram illustrating the operation of the signal generator of  FIG. 5 . 
         FIG. 7  is a schematic diagram of a memory device according to an embodiment of the present invention. 
         FIG. 8  is a schematic diagram of a processor-based system according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without various of these particular details. In some instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the described embodiments of the invention. 
     An embodiment of a multi-phase clock signal generator  300  according to an embodiment of the present invention is shown schematically in  FIG. 3 . While one delay element per tap may be used in some embodiments of the present invention, as was described above with reference to  FIG. 1 , the delay line  305  of  FIG. 3  includes twelve delay elements  310   a - 1 . Three delay elements are provided for each tap  320   a - d . Using multiple delay elements per tap may allow greater flexibility in the range of delay that can be provided by the delay line  305 . For example, the bias generator  150  may produce one bias voltage, V BIAS , that adjusts each of the delay elements  310   a - 1  the same amount. However, in some embodiments, the bias generator  150  may produce several bias voltages, shown as V BIAS1 , V BIAS2 , and V BIAS3  in  FIG. 3 . Each bias voltage may adjust a different set of delay elements  310   a - 1 . For example, delay elements  310   a, d, g , and  j  may be controlled by V BIAS1  and have a large range to provide course control of the delay of the delay line  305 . Delay elements  310   b, e, h , and  k  may be controlled by V BIAS2  and have a medium range to provide medium range control of the delay of the delay line  305 . Delay elements  310   c, f, i , and  l  may be controlled by V BIAS3  and may have a small range to provide fine control of the delay of the delay line  305 . In this manner, a delay with adaptive wide range and timing delay resolution may be achieved. 
     Although four taps  320   a - d  are shown in  FIG. 3  to provide quadrature clock signals, any number of signals may be generated according to embodiments of the present invention having any phase relationship with the incoming signal, C 0 . Similarly, although three delay elements are shown in the delay line  305  for each tap  320   a - d , any number of delay elements may be used for each tap, including more than three delay elements and less than three delay elements. 
     The phase detector  330  of  FIG. 3  is configured to provide an adjustment signal to lock the C 0 , C 180  and C 360  signals in a single adjustment, in contrast to the two-step process performed by the phase detector  130  of  FIG. 1 . The operation of the phase detector  330  will now be discussed with reference to the timing diagram of  FIG. 4 . 
     The phase detector  330  utilizes the C 180  signal to guide the locking of the C 0  and C 360  signals. Accordingly, the C 180  signal serves as an enable signal in that a phase difference between the C 0  and C 360  signals may be determined based on information gathered during a time period that the C 180  signal is at a certain logic level. When the C 180  signal is at a different logic level, the information is not gathered. On receipt of a transition of the C 180  signal, the phase detector  330  initiates a lock of the C 0  and C 360  signals. By measuring the phase difference between the C 0  and C 360  signals and coupling an adjustment signal indicative of the phase difference to the control signal generator, the charge-pump and loop filter  140  as shown in  FIG. 3 . As described above, the charge-pump and loop filter  140  couples a V CONTROL  signal to the bias generator  150  to generate the V BIAS  signal applied to one or more of the delay elements  310   a - 1  to adjust the delay of the delay line  305  to minimize the phase difference between the C 0  and C 360  signals. Accordingly, the solid lines in  FIG. 4  indicate timing signals for one example of C 0 , C 180 , and C 360  signals. As the solid line example shows, the three signals having a duty cycle distortion in that the high portion of each of the signals is less than 50 percent of the clock cycle t CK . Accordingly, C 180  transitions low at time  405 . This low transition can be used by the phase detector  330  to initiate the lock of C 0  and C 360 . Accordingly, the phase detector  330  shortly detects the rising edge of C 0  at time  410  followed by the rising edge of C 360  at time  415 . The phase detector  330  couples the adjustment signal indicative of the phase difference between the two signals to the charge pump and loop filter  140 . 
     The dashed lines in  FIG. 4  illustrate a case where the three signals have a duty cycle distortion causing the signals to be high for greater than 50 percent of the clock period. In this case, the falling edge of C 180  that will enable the phase detector  330  occurs at time  420 , after the rising edges of C 0  and C 360  at times  410  and  415 , respectively. Accordingly the phase detector  330  does not obtain phase information regarding the rising edges of C 0  and C 360 . When the C 180  signal transitions high, the phase detector  330  is disabled, and the phase detector  330  accordingly does not obtain phase information regarding the rising edges of C 0  and C 360  at times  425  and  430 , and will not be able to accurately lock the C 0  and C 360  signals. Accordingly, to accurately lock the C 0  and C 360  signals when the signals have a duty cycle error resulting in a high signal over 50 percent of the clock cycle, a duty cycle distortion tolerance delay element  340  is used, as shown in  FIG. 3 . 
     The duty cycle distortion tolerance delay element  340  delays C 0  and C 360  such that the rising edges of the C 0  and C 360  signals occur while the phase detector  330  is enabled. Alternatively, in some embodiments, the duty cycle distortion tolerance delay element  340  may delay the C 180  signal such that the rising edges of the C 0  and C 360  signals occur while the phase detector  330  is enabled. The amount of delay provided by the duty cycle distortion tolerance delay element may be changed based on a frequency of the reference clock signal. In other embodiments, the amount of delay may be fixed. In  FIG. 4 , the amount of delay provided by the duty cycle distortion tolerance delay element  330  is shown as t DCD     —     Adjust . In the example of  FIG. 4  the signals are shown containing duty cycle distortion, the C 0  and C 360  signals are delayed by the duty cycle distortion tolerance delay element  340 . Accordingly, the rising edge of the delayed C 0  signal occurs at time  450 , after the falling edge of C 180  at time  420  and the rising edge of the delayed C 360  signal occurs at time  455 , again after the falling edge of the C 180  signal at time  420 . In this manner, the phase detector  330  can accurately capture the phase difference between the C 0  and C 360  signals after being enabled by the falling edge of the C 180  signal. Accordingly, the amount of delay provided by the duty cycle distortion tolerance delay element  340  may be selected based on the maximum duty cycle distortion anticipated in the C 0  and C 360  signals. In some embodiments, the duty cycle distortion tolerance delay element  340  provides a fixed amount of delay. In other embodiments, the delay provided by the duty cycle distortion tolerance delay element  340  is variable. 
     The above discussion describes a multi-phase clock signal generator using an intermediate signal as an enable signal to guide the locking of two of the generated signals. In the example described above, the 180 degree signal is used as an enable signal to facilitate the locking of the C 0  and C 360  signals. By locking the C 0  and C 360  signals, and providing delay elements  310   a - 1  having equal amounts of delay between each of the generated signals, the C 0 , C 90 , C 180 , C 270  and C 360  signals will all accordingly be locked in a fast and accurate fashion. A specific example of circuitry used to accomplish the duty cycle distortion tolerance delay and phase locking will now be described with reference to the block diagram of  FIG. 5  and the timing diagram of  FIG. 6 . 
     As shown in  FIG. 5 , the duty cycle distortion tolerance delay element  340  may be implemented by two delay elements receiving the C 0  and C 360  signals, respectively. The C 180  signal is coupled to an inverter  505 . The C 0 , C 180 , and C 360  signals are shown in the timing diagram of  FIG. 6 . The inverted C 180  signal is also shown with a rising edge at time  605 . By inverting the C 180  signal, the rising edge, at time  605 , will serve as the enable signal for the phase detector  330  of  FIG. 5 . To represent the delay of signals C 0  and C 360  by the duty cycle distortion delay elements  340 , the C 180  signal is shown advanced an amount t DCD     —     Adjust . For purposes of illustration, advancing the C 180  signal is equivalent to delaying the C 0  and C 360  signals. The advanced and inverted C 180  signal accordingly has a rising edge at time  610 , prior to the falling edges of C 0  and C 360  at times  620  and  615 , respectively. 
     Two AND gates  510 ,  515  in  FIG. 5  provide functionality for the phase detector  330 . The first AND gate  510  provides a signal indicative of a phase difference between the C 180  signal and the C 0  signal by coupling a DN signal to the charge-pump and loop filter  140 . The DN signal, as shown in  FIG. 6 , is high when both the inverted C 180  signal is high and the delayed C 0  signal is high. Accordingly, the DN signal is high from time  610  to time  620 . The second AND gate  515  provides a signal indicative of a phase difference between the C 180  signal and the C 360  signal by coupling an UP signal to the charge-pump and loop filter  140 . The UP signal, as shown in  FIG. 6  is high when both the inverted C 180  signal is high and the delayed C 360  signal is high. Accordingly, the UP signal is high from time  610  to  615 . The difference in the pulse widths of the DN and UP signals is indicative of the phase difference between the C 0  and C 360  signals. The DN and UP signals are coupled to the charge-pump and loop filter  140  as adjustment signals. 
     Note that, when the pulse widths of the UP and DN signals are equivalent, the C 0  and C 360  signals are locked, that is, the phase difference between the C 0  and C 360  signals is zero. Accordingly, the charge-pump and loop filter  140  are configured to adjust the delay based on a difference of pulse widths between the UP and DN signals to minimize the phase difference between the C 0  and C 360  signals. For example, the V CONTROL  signal may indicate to the bias generator  150  to increase the delay of the delay line  305  during a period when the UP signal is high and the DN signal low. The V CONTROL  signal may indicate to the bias generator  150  to decrease the delay of the delay line  305  during a period when the UP signal is low and the DN signal high. The V CONTROL  signal may indicate to the bias generator  150  to maintain the delay of the delay line  305  when the UP and DN signals have the same level. The charge-pump and loop filter  140  may be implemented in any of a variety of ways. For example, in one embodiment the loop filter may be implemented as a capacitance. The charge pump may include a current source which charges the capacitor responsive to the UP signal being high while the DN signal is low. The charge pump may further include a current sink which discharges the capacitor responsive to the UP signal being low while the DN signal is high. The charge pump would not effect the capacitor when the UP and DN signals had the same state. In this manner, the capacitor builds a voltage which may be, or be used to generate, the V CONTROL  signal. 
       FIG. 7  depicts a portion of a memory device  700 . The memory device receives a clock signal CK  710  and complementary clock signal CKF  730 . The CK and CKF signals may be coupled to the memory device  700  by a memory controller, processor, or other electronic element. The multi-phase clock signal generator  300  of  FIG. 3  is coupled to a delay locked loop  705  for use in locking the output signals of the multi-phase clock signal generator to the received clock signal CK  710 . The received clock signal  710  and optional complementary signal  730  are coupled to an input buffer  735 . For example, the input buffer  735  may receive the clock signals  710  and  730  from off-chip, or from another portion of a chip than the input buffer  735 . The input buffer  735  couples the buffered ClkRef signal to the delay lock loop  705 . The delay lock loop  705  includes a delay line  740  and a phase detection and shift control element  745 . The delay line is configured and controlled by the phase detection and shift control element  745  to output a clock signal CKi, and optionally a complementary clock signal CKiF that are in phase with the ClkRef signal. The phase detection and shift control element  745  couples a control signal  750  to the delay line  740  to adjust the delay of the delay line  740  to minimize a phase difference between the ClkRef signal and a feedback signal  755 . The feedback signal  755  may be based on either one of the signals generated by the multi-phase clock signal generator  300  (C 0  as shown in  FIG. 7 ), or the input signal CKi to the multi-phase clock signal generator  300 , as indicated by the dashed lines in  FIG. 7 . In this manner, the multi-phase clock signal generator  300  may be either inside of the delay-locked loop  705  (when the signal C 0  is used as the feedback signal) or outside of the delay locked loop  705  (when the CKi signal is used). 
       FIG. 7  also illustrates the output signals of the multi-phase clock signal generator  300  (the signals C 0 , C 90 , C 180 , C 270 , and C 360 ) coupled to a clock tree  715  for distribution to the DQ(s)  720  of the memory device  700 . In this manner, the clock signals generated by the multi-phase clock signal generator may be used to clock operation of the DQ(s)  720 . Although distribution to a DQ  720  is shown in  FIG. 7 , the clock signals from the multi-phase clock signal generator  300  may generally be coupled to any number of DQs. Further, output signals of the multi-phase clock signal generator  300  may additionally or instead be coupled to other elements of the memory device  700  or other electronic system employing the multi-phase clock signal generator  300 . An output buffer  725  may be provided at each destination to couple one or more of the clock signals to the destination, such as DQ  720 . 
     The feedback signal used by the phase detection and shift control element  745  may be coupled to one or more model delay elements, including the output model element  760  and the buffer delay element  765  shown in  FIG. 7 . The buffer delay element  765  models the delay of the input buffer  735 . The output model delay element  760  models the delay of an output path between the point the feedback signal was generated, and the destination of the signal generated by the multi-phase clock signal generator  300  (the clock tree  715  and the output buffer  725  in the example of  FIG. 7 ). By delaying the feedback signal by an amount equal to the delay of the output path, the delay locked-loop minimizes the phase difference between the output signal arriving at the DQ  720  and the input clock signal  710 . 
       FIG. 8  is a block diagram of a processor-based system  1000  including processor  1002  that communicates with a memory device  700 . The memory device  700  may be integral with or physically separate from the processor  1002  and communication between the two may take place in any manner. The memory device  700  may contain one or more multi-phase clock signal generators  300  to generate clock signals having various phases in accordance with embodiments of the invention described above. Typically, the processor  1002  is coupled through address, data, and control buses to the memory device  700  to provide for writing data to and reading data from one or more memory arrays in the memory device  700 . The processor  1002  may include circuitry for performing various processing functions, such as executing specific software to perform specific calculations or tasks. In addition, the processor-based system  1000  includes one or more input devices  1004 , such as a keyboard or a mouse, coupled to the processor  1002  to allow a user to interface with the processor-based system  1000 . Typically, the processor-based system  1000  also includes one or more output devices  1006  coupled to the processor  1002 , such as a printer or display. One or more data storage devices may also be coupled to the processor  1002  to store data or retrieve data from external storage media (not shown). Examples of such storage devices include hard and floppy disks, tape cassettes, compact disk read-only (“CD-ROMs”) and compact disk read-write (“CD-RW”) memories, and digital video disks (“DVDs”). 
     The processor-based system  1000  shown in  FIG. 8  may be implemented in any of a variety of products employing processors and memory including for example cameras, phones, wireless devices, displays, chip sets, set top boxes, gaming systems, vehicles, and appliances. Resulting devices employing the processor-based system  1000  may benefit from the embodiments of a multi-phase clock signal generator described above to perform their ultimate user function. 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. For example, although the generation of quadrature clock signals has been discussed and described, embodiments of the invention may generate substantially any number of clock signals having any phase relationship therebetween by, for example, altering a number of identical delay elements per tap in the delay line generating the clock signals. Further, although analog embodiments are shown and described above, other embodiments of the present invention may be implemented using one or more digital components.