Patent Publication Number: US-10784829-B2

Title: Current sense circuit stabilized over wide range of load current

Description:
RELATED APPLICATIONS 
     This application claims priority to an India Provisional Application No. 201841024891, filed Jul. 4, 2018, which is hereby incorporated by reference. 
     BACKGROUND 
     Current to a load often is sensed for one or more reasons. For example, overload protection may include turning off power to the load when the load current exceeds a threshold. The temperature of the power circuit driving a load exceeding a threshold can damage the power circuit. Consequently, as temperature begins to increase, the current to the load can be reduced to decrease the temperature. For such reasons (or other reasons), the amount of current to a load often is sensed over a range from low levels associated with reducing temperature to high levels associated with over current conditions. 
     SUMMARY 
     In one example, a circuit includes a power transistor including a first control input and first and second current terminals, the second current terminal to be coupled to a load to provide current to the load. A second transistor includes a second control input and third and fourth current terminals, and the first and second control inputs connected together and the first and third current terminals connected together. A third transistor includes a third control input and fifth and sixth current terminals. A fourth transistor includes a fourth control input and seventh and eighth current terminals, and the seventh current terminal is coupled to the fourth and fifth current terminals. An amplifier amplifies a difference between voltages on the second and fourth current terminals. An output of the amplifier is coupled to the third control input and a diode device is connected between the third and fourth control inputs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a detailed description of various examples, reference will now be made to the accompanying drawings in which: 
         FIG. 1  illustrates a sense circuit to monitor current to a load over a wide range. 
         FIG. 2  illustrates the effect on phase margin from a change in gain of the sense circuit of  FIG. 1 . 
         FIG. 3  illustrates a sense circuit to monitor current to a load over a wide range while maintaining stability across the full range. 
         FIG. 4  illustrates another sense circuit to monitor current to a load over a wide range while maintaining stability across the full range. 
         FIG. 5  illustrates the relationship of several currents in the sense circuit of  FIG. 4  with respect to an internal node voltage. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows an example of a system  40  including a power transistor, which is implemented as metal oxide semiconductor field effect transistor in this example (labeled as “HSFET” in  FIG. 1 ), coupled to a supply voltage node (VIN) and to a load  45 . The load  45  may comprise, for example, a programmable logic controller (PLC), a robotic arm, or a microcontroller. The system also includes a sense circuit  50 . By asserting a control signal to the gate of HSFET, current Iout is provided from the supply voltage node VIN through HSFET to the load  45 . 
     The sense circuit  50  senses the current Iout to the load. The sense circuit  50  generates a sense current (Isense) that is proportional to (but generally smaller than) Iout and can be used for any of a variety of purposes. For example, overcurrent protection may be implemented to protect the load  45  and/or HSFET from an excessively high output current Iout. An excessively high Iout may damage either or both of HSFET and the load  45 . In one example, overcurrent protection may be implemented by monitoring the magnitude of Isense and detecting when Isense exceeds a threshold corresponding to an Iout of, for example, 18 A. Once Isense exceeds that threshold, the gate voltage of HSFET can be reduced to cause a reduction in Iout or HSFET&#39;s gate can be pulled down to a level equal to Vout to shut off Iout altogether. Additionally, the temperature of HSFET can be monitored and, if the temperature exceeds a threshold, the level of Iout to the load  45  can be reduced by lowering the gate voltage on HSFET to cause less current to flow through HSFET. The temperature of HSFET can be monitored, for example, by using bipolar junction transistors adjacent HSFET to generate a voltage proportional to absolute temperature referred (PTAT voltage). PTAT voltage (ΔVbe) is given by 
               Δ   ⁢           ⁢     V   BE       =       (     kT   q     )     ⁢     ln   ⁡     (       A   ⁢           ⁢   2       A   ⁢           ⁢   1       )               
where k is the Boltzmann constant, T is temperature in Kelvin, q is charge of an electron, A 2  and A 1  are areas of bipolar junction transistors used to generate the PTAT voltage. The Isense current produced by the sense circuit  50  continues to be monitored as Iout is reduced. To avoid damage to HSFET, Iout may be lowered to relatively low levels (e.g., 150 mA). Thus, the sense circuit  50  should be able to monitor Iout current over a wide range from, for example, 150 mA to 18 A.
 
     The sense circuit  50  in this example includes an amplifier  52 , a capacitor CD, transistors M 1  and M 2 , and sense transistor (SNSFET). Transistors SNSFET and HSFET form a current mirror. The drains of SNSFET and HSFET are connected together, and their gates also are connected together. If the voltages on the sources of HSFET and SNSFET are forced to be approximately equal, then the current through SNSFET (Isense) will track the current through HSFET (Iout). In this example, SNSFET is smaller than HSFET. That is, the ratio of channel width (W) to channel length (L) for SNSFET is smaller than the W/L ratio of HSFET. As such, the ratio of W/L of HSFET to W/L of SNSFET is n:1, where n is greater than 1. This sense ratio means that Isense is (1/n)*Iout. In one example, the W/L ratio of SNSFET is 1/7000th of the W/L ratio of HSFET (i.e., n=7000) and thus Isense is Iout/7000. Isense also flows through M 1  to ground. M 1  and M 2  also form a current mirror. In this example, the W/L ratios of M 1  and M 2  are approximately equal, and thus the current mirror ratio of the current mirror comprising M 1  and M 2  is 1:1. As such, the current through M 2  also is equal to Isense. 
     The inputs of the amplifier  52  couple to the sources of SNSFET and HSFET, and thus the amplifier  52  amplifies the difference between the source voltages of SNSFET and HSFET to produce an output voltage (VS) to the gates of M 1  and M 2 . The amplifier  52  is part of a control loop that monitors the difference between the source voltages of SNSFET and HSFET and controls the gate voltage on M 1  to regulate the source voltage of SNSFET to be equal to the source voltage on HSFET. The source of SNSFET is connected to the drain of M 1  at a node identified as VSNS. The source of HSFET is coupled to the load  45  at a node identified as Vout (the output voltage for load  45 ). Thus, through the control loop including the amplifier  52 , VSNS is continually adjusted to be remain equal to Vout. 
     In steady state operation of the feedback control loop, the drain current through SNSFET (Isense) equals (1/n)*Iout and VSNS equals Vout. If VSNS deviates slightly from Vout due to, for example, noise coupling from adjacent circuits, a change in loading may occur which causes Vout to change relative to VSNS, and the feedback loop described herein returns VSNS back to the VOUT voltage level. If VSNS, for example, increases slightly above VOUT (e.g., due to charging of a parasitic capacitance on the VSNS node as a result of noise), the drain-to-source voltage (VDS) of SNSFET will decrease and the gate-to-source voltage of SNSFET also will decrease. The current through SNSFET will thus decrease violating the sense ratio between HSFET and SNSFET as VSNS increases. VSNS is coupled to the positive (+) input of the amplifier  52  and Vout is coupled to the negative (−) of the amplifier  52 . An increase in the positive input of the amplifier  52  will cause its output voltage VS also to increase (assuming no change in Vout). An increase in VS represents an increase in the VGS of M 1 , which in turn causes the drain current through M 1  to increase. An increase in M 1 &#39;s drain current causes the parasitic capacitance on the VSNS node to discharge thereby reducing the VSNS voltage back to a level equal to VOUT and current through SNSFET increases back to (1/n)*Iout. The speed of this correction depends on the bandwidth of the control loop. For a stable control loop, VSNS will be equal to VOUT in the steady state. 
     As noted above, the sense circuit  50  should have a wide range of sense current operation. In the example above, Isense may vary between levels corresponding to an Iout range of 150 mA to 18 A. The sense circuit  50  of  FIG. 1 , however, may experience instability at low Isense current values and also at high Isense values. At a low Isense value, instability can result from a dominant pole of the frequency response of the sense circuit  50  increasing to a higher frequency as Isense decreases, and also as the frequency of the first non-dominant pole (fnd) decreases as Isense decreases. The frequency (fd) of the dominant pole of the sense circuit  50  is given by 
               f   d     =     1     2   ⁢   π   ⁢           ⁢   RsCD             
where Rs is the impedance seen looking into the VS node. As Iout decreases, Isense reduces which means Vs also reduces. When VS reduces, the VDS of a transistor within amplifier  52  (e.g., M 362  in the example of  FIGS. 3 and 4 ) reduces which transitions that transistor from the saturation region to the linear region of operation thereby reducing Rs. As a result of the decrease in Rs, the fd frequency increases. The frequency of the first non-dominant pole of the sense circuit  50  is given by fd=1/(2π *R_VSNS*C_VSNS) where C_VSNS is the parasitic capacitance on the VSNS node and R_VSNS impedance on the VSNS node. R_VSNS is given by:
 
 R _ VSNS=R out_ M 1∥( R out_ SNSFET ∥1/ gm _ SNSFET )≈1/ gm _ SNSFET   (1)
 
where Rout_M 1  is the resistance of M 1  as seen from the VSNS node, Rout_SNSFET is the output resistance of SNSFET as seen from the VSNS node, gm_SNSFET is the transconductance value (gm) of SNSFET, and “∥” means that the components are in parallel. The value of gm_SNSFET is given by:
 
                   gm_SNSFET   =     2   *     Isense   VOV_SNSFET               (   2   )               
where VOV_SNSFET is the overdrive voltage of SNSFET, that is, the VGS voltage in excess of the transistor&#39;s threshold voltage. Per Eq. (2), as Isense decreases (which decreases at a faster rate than VOV_SNSFET decreases), the gm of SNSFET decreases and thus 1/gm of the SNSFET increases. As 1/gm of SNSFET increases, per Eq. (1) R_VSNS also increases and thus fnd decreases. As fd is increasing and fnd is decreasing (as Isense decreases) the phase margin deteriorates causing instability in the loop. An unstable sense circuit will cause oscillations in Iout during current limiting operations because the sensed current Isense itself is oscillating and similarly any other loop that is using Isense information on the same chip also will oscillate. For example, a power limiting loop that uses Isense information may cause oscillations in power delivered to the load.
 
     Instability also may occur as Isense increases and is near the upper end of the operational range of the sense circuit  50 .  FIG. 1  illustrates that the system  40  is divided into three stages—stage 1, stage 2, and stage 3. Stage 1 includes HSFET and the load. Stage 2 includes the amplifier  52 , and stage 3 includes SNSFET and M 1 . The gain of stage 3 is a function of the gm of M 1  and the on-resistance of the SNSFET when SNSFET is operating in the linear region, that is:
 
gain= gm _ M 1 *rdson _ SNSFET   (3)
 
where gm_M 1  is the gm of M 1  and rdson_SNSFET is the on-resistance of SNSFET. Per Eq. (2) above, as current through a FET increases, the gm of the transistor also increases. Thus, as Isense increases, gm_M 1  also increases, and per Eq. (3), as gm_M 1  increases, the gain of stage 3 increases. Because the gain of stage 3 increases, the overall gain of the system (gains of all three stages multiplied together).  FIG. 2  illustrates the increase in gain from gain curve  200  to  201 . The frequency locations of the poles remain the same, but the gain increases. The phase-frequency relationship remains unchanged, and as can be seen, the phase margin (phase difference between the phase and 180 degrees at unit gain) decreases from the original phase margin (PM_original) to the phase margin associated with the new gain curve (PM_new), thereby causing instability.
 
     The disclosed embodiments are directed to a sense circuit that is stable throughout a relatively wide operational range of the sense circuit. That is, the sense circuit is stable both at levels of sense current at the lower end of the operational range and at sense current at the higher levels of the operational range.  FIG. 3  is a schematic of a system  300  including a transistor HSFET M 301  coupled to a load  345 . The system  300  also includes a sense circuit  310  to sense the output current Iout to the load  345  and generate a sense current Isense that is proportional to, and thus is a proxy for, Iout. The sense circuit  310  addresses the instability problems at low and high current levels explained above regarding the sense circuit  50  of  FIG. 1 . 
     Reference is made herein to transistors. A transistor has a control input and a pair of current terminals. A metal oxide semiconductor field effect transistor&#39;s (MOSFET&#39;s) control input is its gate and its current terminals are its drain and source. A bipolar junction transistor&#39;s (BJT&#39;s) control input is its base and its current terminals are its collector and emitter. 
     The sense circuit  310  in the example of  FIG. 3  includes a two-stage amplifier  352 , a sense transistor (SNSFET) M 302 , transistors MBig M 303  and MSmall M 304 , a current clamp  370 , and capacitor CD. The two-stage amplifier  352  includes a servo pre-amplifier  351  as well as transistors M 354 , M 356 , M 358 , M 360 , and M 362  and a current source device I 1 . Transistors M 354  and M 356 , in this example, comprise p-type bipolar junction transistors (BJTs) and transistors M 358 , M 360 , and M 362  comprise n-type metal oxide semiconductor field effect transistors (n-type MOSFETS also referred to as NMOS devices). The positive and negative outputs of the servo pre-amplifier  351  are coupled to the base of M 354  and the base of M 356 , respectively. The emitters of M 354  and M 356  are connected to the current source I 1  (I 1  refers both to the current source device and the magnitude of the current it produces). The collector of M 354  is connected to the drain of M 360  and the source of M 360  is connected to the ground node. The collector of M 356  is connected to the drain of M 358  and the source of M 358  is connected to the drain of M 362 . The source of M 362  is connected to the ground node. The gates of M 360  and M 362  are connected together and to the drain of M 360 . The gate of M 358  is connected to its drain. M 358  is configured as a diode-connected transistor so that the drain of M 358  is approximately 0.7 V higher than the source of M 358 . The combination of current source I 1  and transistors M 354 , M 356 , M 358 , M 360 , and M 362  represent a transistor amplifier. 
     SNSFET M 302  is used to sense current flowing in HSFET M 301 . The gates of SNSFET M 302  and HSFET M 301  are connected together, as are their drains (which are also connected to the supply voltage node (VIN). The source of HSFET M 301  is coupled to the load  345  and to the negative input of the servo pre-amplifier  351 . The source of SNSFET M 302  is coupled to the positive input of the servo pre-amplifier  351 . The source of transistor M 302  is connected to the drains of MBig and MSmall. The source of MBig is connected to the ground node. The source of MSmall is connected to the current clamp  370 . 
     The example system of  FIG. 3  includes transistors of specific types. The system, however, can be implemented with transistors of other types. BJTs can be used in place of MOSFETs, MOSFETs in place of BJTs, NMOS devices in place of p-type MOSFETs, etc. 
     HSFET M 301  is of a size that can accommodate relatively large Iout current levels to the load (and thus may be referred to as a power transistor). In one example, the length of HSFET  301  is in the range of 1 micrometers (microns) to 2 microns and its width is in the range of 300 mm to 700 mm. In one example, the width is 570 mm and the length is 1.5 microns. SNSFET M 302 , in this example, is smaller than HSFET M 301 . That is, the W/L ratio of channel of SNSFET M 302  is smaller than that of HSFET M 301 . In one implementation, the W/L ratio of HSFET M 301  is 7000 times bigger than that of SNSFET M 302 , and thus the current mirror ratio in that example is 7000:1. The 7000:1 current mirror ratio provides an acceptable balance between power efficiency and accuracy. As the gates of HSFET M 301  and SNSFET M 302  are connected together, as are their drains, the current through SNSFET M 302  (Isense) mirrors that of Iout (albeit smaller in accordance with the current mirror ratio). 
     Referring still to  FIG. 3 , MBig M 303  also is bigger than MSmall M 304 . That is, the W/L ratio for MBig M 303  is larger than that of MSmall M 304 . In one example, the W/L ratio for MBig M 303  is 40 times larger than that of MSmall M 304 , which provides an acceptable value in light of an output current of 300 mA. The gate of MBig M 303  is the VS voltage from the drain of M 362 . VS is the output signal from the amplifier  352 . The gate of MSmall M 304  is coupled to the drain of M 358  which provides a voltage labeled as VS_D. M 358  is configured as a diode-connected transistor and thus the drain of M 358  is approximately 1V higher than its source. Thus, VS_D is approximately 0.7 V higher than VS, which means that the VGS of MSmall M 304  is larger than the VGS of MBig M 303 . At relatively low Iout current levels (e.g., 50 mA to 300 mA), the VS output from amplifier  352  is relatively low (e.g., 50 mV to 150 mV for an output current in the range of 50 mA to 300 mA), and specifically low enough that MBig M 303  is either on but conducting very little drain current, or off altogether. However, as the gate of MSmall M 304  is biased higher than the gate of MBig M 303 , MSmall is driven stronger than MBig and thus more current flows through MSmall than MBig. Isense is divided between Ismall current flowing through MSmall M 304  and Ibig flowing through MBig M 303 . At low levels of Isense, because MSmall M 304  is driven stronger than MBig M 303 , Ismall is larger than Ibig. For example, for Iout of 50 mA, more than 90% of Isense flows through Ismall instead of Ibig This low level current effect is illustrated in  FIG. 5 , which plots Isense, Ibig, and Ismall as a function of VS. At low levels of VS (e.g., VS 1 ), Ismall is larger than Ibig. 
     The sense circuit  310  is a three-stage circuit in which Stage 1 includes the servo pre-amplifier  351 , Stage 2 includes the transistor amplifier comprising current source I 1  and transistors M 354 , M 356 , M 358 , M 360 , and M 362 , and Stage 3 includes SNSFET, MBig, MSmall and current clamp  370 . The gain of Stage 3 is given by:
 
gain= R ( gm _ M Small+ gm _ M big)  (4)
 
where R is the impedance seen at the drain of MSmall M 304 , gm_MSmall is the transconductance of MSmall M 304 , and gm_MBig is the transconductance of MBig M 303 . The transconductances of MSmall and MBig are given as:
 
                   gm_Msmall   =       2   *   Ismall     VOV_MSmall             (   5   )               gm_MBig   =       2   *   Ibig     VOV_MBig             (   6   )               
where VOV_MSmall is the overdrive voltage for MSmall M 304  and VOV_MBig is the overdrive for MBig M 303 . As the gate of MSmall M 304  is biased higher (approximately 1 V higher) than the gate of MBig M 304 , the VGS of MSmall M 304  is larger than the VGS of MBig M 303  and thus the overdrive voltage for MSmall M 304  is larger than the overdrive voltage MBig M 303 . As MSmall&#39;s overdrive voltage is relatively large at low levels of Isense, the transconductance for MSmall is relatively small. Further, as relatively little current (Ibig) flows through MBig M 303  at low levels of Isense, the transconductance of MBig M 303  also is relatively small. Thus, compared to the transconductance of M 1  from  FIG. 1 , the sum of gm_MSmall and gm_MBig is less than gm_M 1 . Consequently, per the gain equations of Eq. (3) and Eq. (4), the gain of Stage 3 of  FIG. 3  is smaller (for small levels of Isense) than the gain of Stage 3 in  FIG. 1  at lower levels of Iout. For the sense circuit  310  of  FIG. 3 , the gain at low levels of Isense decreases by using Mbig and Msmall instead of M 1  ( FIG. 1 ). When the total gain, gain from the three stages combined together, decreases for a given position of poles, the loop becomes stable by increasing the phase margin.
 
     The current clamp  370  permits Ismall to increase as Isense increases up until a threshold is reached, at which point Ismall remains relatively constant with further increases in Isense. 
       FIG. 4  is a schematic of a system  400  similar to that of  FIG. 3  but with several differences. System  400  includes transistor HSFET M 301  coupled to load  345 . The system  400  also includes the sense circuit  310  to sense the output current Iout to the load  345  and generate a sense current Isense that is proportional to, and thus is a proxy for, Iout. The sense circuit  310  in the example of  FIG. 4  includes the two-stage amplifier  352 , SNSFET M 302 , transistor M 365 , transistors MBig M 303  and MSmall M 304 , current clamp  370 , capacitor CD and a compensation capacitor Cc (compensation capacitor Cc was not included in the example of  FIG. 3 ). 
     As explained above, SNSFET M 302  is used to sense current flowing in HSFET M 301 . The gates of SNSFET M 302  and HSFET M 301  are connected together, as are their drains. The source of HSFET M 301  is coupled to the load  345  and to the negative input of the servo pre-amplifier  351 . The source of SNSFET M 302  is coupled to the positive input of the servo pre-amplifier  351 , as well as to the drain of transistor M 365 . The source of transistor M 365  is connected to the drains of MBig and MSmall. The source of MBig is connected to the ground node. The source of MSmall is connected to the current clamp  370 . The current clamp  370  includes a current source device I 2  and transistors M 372  and M 374 . Transistors M 372  and M 374  comprise NMOS devices, whose gates are connected together. The sources of M 372  and M 374  are connected to the ground node. The gate of M 372  is connected to its drain and the drain of M 372  is connected to I 2 . The source of M 304  is connected to the drain of M 374 . 
     As noted above, the current clamp  370  permits Ismall to increase as Isense increases up until a threshold is reached, at which point Ismall remains relatively constant with further increases in Isense. In this example, the current clamp  370  includes a current source device I 2  coupled to transistor M 372  and M 374 . M 372  and M 374  comprise NMOS devices whose gates are connected together. The sources of M 372  and M 374  also are connected together and to the ground node. The gate and drain of M 272  are connected together and I 2  provides a current through M 372 . Before the drain current through Msmall reaches the I 2  current level, M 374  operates in the linear region and the current is controlled by Msmall. However, as the current through Msmall tries to increase above I 2 , M 374  enters the saturation region and controls the current in Msmall and Msmall itself enters the linear region of operation. 
     In  FIG. 5 , Ismall is larger than Ibig at low levels of VS. Ismall is capped as shown at I 2 . As Isense continues to increase, Ibig is permitted to increase but not Ismall. Thus, at larger levels of Isense (e.g., a level corresponding to VS 3 ), Ibig exceeds Ismall. VS 2  represents the VS voltage level for which Ibig equals Ismall. Isense is shown in  FIG. 4  as the sum of Ismall and Ibig. 
     As Iout increases, Isense also increases as described above. Once Ismall is capped at I 2 , Ibig through MBig M 303  continues to increase. At higher levels of Isense, the majority of the Isense current flow through MBig M 303  instead of MSmall M 304  (as MSmall is capped). As explained above regarding the instability problem of the sense circuit  50  of  FIG. 1 , the gain of Stage 3 increases at larger levels of Isense causing a reduction in the phase margin thereby leading to instability. The inclusion of the compensation capacitor Cc in the example sense circuit  310  of  FIG. 4  solves this problem. The compensation capacitor Cc causes the frequency associated with the dominant pole to decrease. The Cc capacitor acts similar to a Miller capacitor, however unlike a Miller capacitor (which stabilizes a circuit for a given location of poles), in the described example, the Cc capacitor helps the dominant pole to track Iout. As Iout, and hence, Isense increases, the gain across Cc increases due to increases in the transconductance (gm) of Mbig. This increased gain moves the dominant pole earlier previously at fd=1/2πRSCD to 1/2πRS(CD+AvCc) where the Av is the gain across the Cc. Av increases as Isense increases and hence the dominant pole frequency reduces as Isense increases to increase the phase margin thereby compensating the phase margin reduction due to increased gain in the loop as explained above. The sense circuit  310  thus remains stable despite an increase in its loop gain at higher sense currents. 
     The example sense circuit of  FIGS. 3 and 4  is a single circuit solution that is stable across a wide load range (e.g., 100 mA to 18 A). The gain of Stage 3 is gradually reduced as Isense tracks lower and lower levels of Iout. By reducing the gain of Stage 3, the sense circuit  310  remains stable at low levels of Iout (Isense). At higher levels of Iout (Isense), the dominant pole is increased thereby avoiding oscillations (instability) that would otherwise occur in the circuit as the gain of Stage 3 increases. The current clamp  370  effectively causes the use of MSmall M 304  to be neither a detriment nor a benefit at high levels of Iout (Isense). The progression of Isense as Iout increases or decreases is continuously—that is, there is no discontinuity in operation from a low Iout current level to a high Iout current level. Further still, compared to at least some other sense circuits, the sense circuit  310  of  FIG. 1  may be smaller and consume less power. 
     In this description, the term “couple” or “couples” means either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.