Patent Publication Number: US-4481511-A

Title: Matrix display device

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a matrix display device using a multiplex matrix display panel. 
     Various sorts of display cells for the matrix display device, such as liquid crystal cells, electrochromic cells, a plasma display, a fluorescent display tube, LED&#39;s, PLZT cells and electroluminescence cells, have been known. By way of example, the principle of a liquid crystal display device is illustrated in FIG. 1, in which the liquid crystal 103 is held between a pair of substrates 101 and 102 at least one of which is transparent, and a predetermined voltage is applied between transparent electrodes 104 and 105 formed on the opposing surfaces of the substrates 101 and 102 to cause an electrooptical change in liquid crystal molecules. The relation between an effective voltage applied across the transparent electrodes 104 and 105 and the amount of transmitted light is shown in FIG. 2, in which V S  and V NS  represent threshold voltages. In the liquid crystal matrix display device, picture cells defined at the crosspoints of the transparent electrodes 104 and 105 are generally arranged in matrix form and characters or graphic patterns are displayed by selecting the effective voltages applied to the respective picture cells. 
     In such a matrix display device, in order to fire a number of picture cells with a high contrast, a multiplex matrix system or an alternate multiplex matrix system has been proposed. By way of example, a multi-matrix or duplex matrix system display device is explained with reference to FIGS. 3 to 5. Configurations shown in FIGS. 3 and 5 are disclosed in Japanese patent application Laid-Open Nos. 120230/78 and 106189/79, respectively. 
     Referring to FIG. 3, numeral 100 denotes an image data circuit which comprises a video signal input terminal 1, an A-D converter 2 and a timing control circuit 3. Column electrode drive circuits 4 and 5 comprise line memories 41 and 51, latch registers 42 and 52 and modulators 43 and 53, respectively. Numeral 6 denotes a row electrode drive circuit. A matrix display panel 7 has an electrooptical effect material, such as a liquid crystal or an electroluminescence material, filled in between a pair of substrates 8 and 9. The first substrate 8 has I row electrodes X 1  -X I  and the second substrate 9 has J A-column electrodes Y A1  -Y AJ  and J B-column electrodes Y B1  -Y BJ . The column electrodes are electrically divided into two groups which form J display columns Y 1  -Y J . Accordingly, 2I rows by J columns of picture cells are defined at the crosspoints of the row electrodes, and the column electrodes with the i-th row electrode X i  (i=1, 2, . . . I) being connected to the (2i-1) the row picture cell and the (2i)th row picture cell. The A-column electrode Y Aj   of the i-th column Y j  (j=1, 2, . . . J) is connected to the picture cells on the odd numbered rows ((2i-1)th row) and the B-column electrode Y Bj  is connected to the picture cells on the even numbered rows ((2i)th row). 
     Referring to FIG. 4a, circled numerals under a video signal VD indicate row numbers of a scan line of the video signal. 
     The video signal VD as shown in FIG. 4a is applied to the video signal input terminal 1. The A-D converter 2 receives the video signal VD and a sampling clock CP 1  and converts the video signal VD to a digital signal SD in synchronism with the sampling clock CP 1 . The timing control circuit 3 extracts a synchronizing signal from the video signal VD to generate the sampling clock CP 1 , write clocks CP A  and CP B  and a strobe pulse STB for controlling the display device. 
     The line memory 41 receives the digital video signal SD and the write clock CP A  which is generated at the odd row period of the scan line and serially stores one scan line of video data in synchronism with the clock CP A . The line memory 51 receives the digital video signal SD and the write clock CP B  which is generated at the even row period of the scan line and stores one scan line of video data in synchronism with the clock CP B . Accordingly, the odd rows of the scan line of video data are written into the line memory 41 while the even rows of the scan line of video data are written into the line memory 51. As shown in FIG. 4a, the first row of the scan line of video data is first written into the line memory 41 and then the second row of the scan line of video data is written into the line memory 51. 
     The strobe pulse STB is generated when the even rows of the scan line of video data have been written into the line memory 51. The latch registers 42 and 52 receive the video data stored in the line memories 41 and 51, respectively, and the strobe pulse STB and parallelly latch the video data from the line memories 41 and 51, respectively, in synchronism with STB. 
     The modulator 43 receives the odd rows of the scan line of video data latched in the latch register 42 and supplies column electrode drive signals V YAj  (j=1, 2, . . . J) to the column electrodes Y Aj  for modulating the brightnesses of the picture cells. Similarly, the modulator 53 receives the even rows of the scan line of video data latched in the latch register 52 and supplies column electrode drive signal V YBj  to the column electrodes Y Bj . 
     The row electrode drive circuit 6 receives the strobe pulse STB and supplies row electrode drive signals V Xi  (i=1, 2, . . . I) to the row electrodes X i . The row electrode drive signals V Xi  are generated in such a manner that only one of the row electrodes X i  is selected and other row electrodes are not selected at a time and the row electrodes X i  are sequentially selected one at a time in synchronism with the strobe pulse STB. 
     Specific waveforms of the row electrode drive signal V Xi  and the column electrode drive signals V YAj  and V YBj  vary depending on particular electrooptical material used as the display medium. 
     The row electrode drive signal V X  and the column electrode drive signal V Y  for the liquid crystal display medium are shown in FIG. 4b. A constant a is selected to be equal to or close to √I+1 where I is the number of the row electrodes X i , and V o  is a maximum amplitude of a voltage V x  -V y  applied to the picture cell. The voltage V o  is selected to meet the following relation: ##EQU1## where V TH  is a threshold voltage of the liquid crystal. 
     Each of the scan electrodes X i  is selected in every I-th cycle. The brightness of the picture cell is determined by a ratio T A  /T of the column electrode drive signal V Y . When T A  =T, the brightness of the picture cell is maximum, and when T A  =0 it is minimum. Accordingly, by controlling the ratio T A  /T, tone of the displayed image can be controlled. 
     Referring to FIG. 4a, the video data written into the line memories 41 and 51 at the first and second rows of the scan line of video signal VD, respectively, are transferred to the latch registers 42 and 52 in response to the strobe pulse STB generated at the end of the second row of the scan line and modulated into the column electrode drive signals V YAj  and V YBj  by the modulator 43 and 53 so that the first and second rows of the video data are supplied to the column electrodes Y Aj  and Y Bj . During this period, the third and fourth rows of the scan line of video signal VD are written into the line memories 41 and 51 as the next video data. The row electrode drive circuit 6, at this time, generates the row electrode drive signal V Xi  to select the first row electrode X 1  so that the first and second rows of the picture cells on the column Y 1  are fired. 
     At the end of the fourth column of the scan line of video signal VD, the strobe pulse STB is again generated and the column electrode drive signals V YAj  and V YBj  drive the third and fourth rows of the video signal VD and the row electrode drive signal V Xi  selects the second row electrode X 2  so that the third and fourth rows of the picture cells on the column Y i  are fired. Similar operations are repeated to fire other picture cells. 
     FIG. 5 shows a prior art example in which lead terminals of the column electrodes Y Aj  and Y Bj  and the column electrode circuits 4 and 5 are collected on one side of the one substrate 9 of the matrix display panel 7 in order to reduce the size of the device shown in FIG. 3. In FIG. 5, the like numerals to those of FIG. 3 denote like elements. 
     As shown in FIG. 5, where the terminals of the different column electrodes Y Aj  and Y Bj  are arranged on the same side of the matrix display panel 7, the signal lines of the column electrodes Y Aj  and Y Bj  and the column electrode drive circuits 4 and 5 cross each other. Accordingly, they cannot be wired by a flat cable, but a multi-layer printed circuit board is required, which results in the increase of the manufacturing cost. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a matrix display device in which connecting lines of the column electrodes and the column electrode drive circuits do not cross so that the wiring is facilitated. 
     In accordance with a feature of the matrix display device of the present invention, the column electrodes opposing a line of picture cell matrix of the matrix display panel are electrically divided into a plurality of groups with a predetermined regularity for each column, and terminals of the column electrodes of at least two of the plurality of groups of column electrodes are arranged to extend to the same side of the matrix display panel, and the column electrode terminals of the at least two groups of the column electrodes on the same side are arranged in the same order or sequence as that of the output terminals of the column electrode drive circuits. 
     In accordance with another feature of the matrix display device of the present invention, the column electrodes opposing a line of picture cell matrix of the matrix display panel are electrically divided into a plurality of groups with a predetermined regularity for each column, the terminals of at least two groups of the plurality of groups of column electrodes are arranged on the same side of the matrix display panel, the column electrodes of the two groups arranged on the same side are connected to the column electrode drive circuits, and the order of the video data arrangement supplied from a video data circuit to the column electrode drive circuits is same as the order of arrangement of the terminals of the two groups of column electrodes arranged on the same side of the matrix display panel. 
     The predetermined regularity in electrically dividing the column electrodes into the plurality of groups means that when the column electrodes are divided by four times the number of row electrodes to define four rows of picture cells for each row electrode and divide the column electrodes into groups a, b, c and d, the groups are regularly arranged in the order of a, b, c, d, a, b, c, d, . . . (multiplex system) or a, b, c, d, d, c, b, a, a, b, c, d, . . . (alternate multiplex system). 
     The order of arrangement of the outputs of the column electrode drive circuit and the order of the arrangement of the video data supplied from the video data circuit to the column electrode drive circuit and the order of the arrangement of the terminals of the column electrodes of the at least two groups of column electrodes arranged on the same side of the matrix display panel are same. This means that when the column electrodes are divided into quadruplex groups and all of the terminals of the column electrodes are arranged on the same side of the matrix display panel with the order of a, b, c, d (for the first column), a, b, c, d (for the second column) and so on, the order of the arrangement of the outputs of the column electrode drive circuit and the order of storing the video data in the line memory of the column electrode drive circuit are Ia, Ib, Ic, Id (for the first column), Ia, Ib, Ic, Id (for the second column) and so on. 
     The other objects and the features of the present invention will be apparent from the following description of the preferred embodiments. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a principle of a liquid crystal display. 
     FIG. 2 shows a relation between an applied voltage and the amount of transmitted light in operating a liquid crystal display device. 
     FIG. 3 shows an example of a prior art liquid crystal matrix display device. 
     FIG. 4a shows a time chart for the operation of the circuit of FIG. 3. 
     FIG. 4b shows drive signals used in the circuit of FIG. 3. 
     FIG. 5 shows another example of a prior art liquid crystal matrix display device. 
     FIG. 6 shows a first embodiment of a liquid crystal matrix display device in accordance with the present invention. 
     FIG. 7 shows a time chart for the operation of the first embodiment. 
     FIG. 8 shows a second embodiment of the liquid crystal matrix display device in accordance with the present invention. 
     FIG. 9 shows a time chart for the operation of the second embodiment. 
     FIG. 10 shows a third embodiment of the liquid crystal matrix display device in accordance with the present invention. 
     FIG. 11 shows a time chart for the operation of the third embodiment. 
     FIG. 12 shows a fourth embodiment of the liquid crystal matrix display device in accordance with the present invention. 
     FIG. 13 shows a fifth embodiment of the liquid crystal matrix display device in accordance with the present invention. 
     FIGS. 14a and 14b show time charts for explaining the operation of the fifth embodiment. 
     FIG. 15 shows a sixth embodiment of the liquid crystal matrix display device in accordance with the present invention. 
     FIGS. 16a and 16b show time charts for the operation of the sixth embodiment. 
     FIG. 17 shows a modification of the sixth embodiment. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention will now be explained in detail in conjunction with the preferred embodiments. 
     EMBODIMENT 1 
     Referring to FIG. 6, a video data circuit 100 comprises an A-D converter 2, a timing control circuit 3, a buffer memory 11 and a switch 12. A column electrode driver 10 comprises a line memory 101, a latch register 102 and a modulator 103, and has 2J output lines so that it can drive both A-column electrodes Y Aj  and B-column electrodes Y Bj . 
     The timing control circuit 3 generates a sampling clock CP 1 , a buffer memory write clock CP 2 , a buffer memory read clock CP 3 , a switching clock CP 4 , a line memory write clock CP 5  and a strobe pulse STB. 
     The buffer memory 11 receives a digital video signal SD 1 , the buffer memory write clock CP 2  and the buffer memory read clock CP 3  and sequentially stores a scan line of video data in synchronism with CP 2  and sequentially outputs the stored scan line of video data in synchronism with CP 3 . The digital video signal outputted from the buffer memory 11 is represented by SD 2 . 
     The switch 12 receives the digital video signals SD 1  and SD 2  and the switching clock CP 4  and outputs two scan lines of video data SD 1  and SD 2  as a digital video signal SD 3 . 
     Referring to FIG. 7, the buffer memory write clock CP 2  is generated at every odd row period of the scan line so that odd rows of the scan line of video data are stored in the buffer memory 11 in synchronism with CP 2 . The buffer memory read clock CP 3  is generated at every even row period of the scan line so that the digital video signal SD 2  is outputted such that the first row of video data is produced in the second row period of the scan line, the third row of video data is produced at the fourth row period, and the (2i-1)th row video data is produced at the (2i)th row period. 
     The switch 12 receives the digital video signals SD 1  and SD 2  and the switching clock CP 4  and alternately selects SD 1  and SD 2  in the even row period of the scan line to produce SD 3 . Accordingly the digital video signal SD 3  includes two scan lines of video data in each even row of the scan line. The switch 12 is controlled by the switching clock CP 4  and SD 2  is first applied thereto. Accordingly, the digital video signal SD 3  alternately provides the odd rows and even rows of the video data with the odd rows of the scan line of video data being provided first. This sequence corresponds to the sequence of connection of the column electrodes of the matrix display panel 7 to the column electrode driver 10 in which the column electrodes are arranged in Y A1 , Y B1 , . . . with the electrodes with suffix A appearing first. 
     In FIG. 6, the line memory 101 in the column electrode driver 10 receives the digital video signal SD 3  and the line memory write clock CP 5  and sequentially stores SD 3  in synchronism with CP 5 . As shown in FIG. 7, the line memory write clock CP 5  is generated in the even row period of the scan line of video signal VD and the frequency thereof is twice as high as that of the conventional system so that two lines of video data can be written into the line memory 101 in one scan line period. 
     The latch register 102 and the modulator 103 each has 2J internal circuits which are twice as many as those of the conventional systems shown in FIGS. 3 and 5. The other aspects are identical to the conventional system. The latch register 102 latches the video data of the line memory 101 in synchronism with the strobe pulse STB and converts them to the column electrode drive signals V YAj  and V YBj . 
     The matrix display panel of the present invention employs a double matrix system in which all of the column electrodes are driven from the same side of the substrate. That is, the terminals of the A-column electrodes Y A1-Y   AJ  and the B-column electrodes Y B1  -Y BJ  are arranged on one side of the substrate with the A-column electrodes and the B-column electrodes being alternately arranged in the order such as Y A1 , Y B1 , Y A2 , Y B2 , . . . Y AJ , Y BJ . The 2J column electrode drive signals at the outputs of the modulator 103 of the column electrode driver 10 are applied to the 2J column electrodes without changing the order. 
     In the present device, since the odd rows of the scan line of video data and the even rows of the scan line of video data are alternately written in the line memory 101, the drive signals V YAj  for the odd rows of the scan line are applied to the respective A-column electrodes Y Aj  and the drive signals V YBj  for the even rows of the scan line are applied to the B-column electrodes Y Bj  so that the wirings between the column electrodes Y Aj  and Y Bj  and the column electrode drive 10 do not cross. 
     In the present embodiment, since the column electrodes connected to the picture cells on the odd rows of the display columns and the column electrodes connected to the picture cells on the even rows are alternately arranged, the order of the video data written into the line memory is selected such that the odd rows of the scan line of video data and the even rows of the scan line of video data alternate. 
     EMBODIMENT 2 
     Referring to FIG. 8, it is identical to FIG. 6 except for the matrix display panel 7. 
     The picture cells in FIG. 8 have 2I rows and J columns as is the case of FIG. 6 and the first substrate 8 and the row electrodes formed thereon are also identical to those of FIG. 6. There are I row electrodes which are designated by X 1 , X 2 , . . . X i , . . . X I . The row electrode X i  are connected to the picture cells on the (2i-1)th row and the picture cells on the (2i)th row, like in FIG. 6. 
     On the second substrate 9, there are formed J A-column electrodes and J B-column electrodes, which are designated by Y A1 , Y A2 , . . . Y Aj , . . . Y AJ  and Y B1 , Y B2 , . . . Y Bj , . . . Y BJ , as is the case of FIG. 6. 
     The manner of connection of the column electrodes to the picture cells is different from that of FIG. 6. The A-column electrodes Y Aj  are connected to the picture cells in the odd rows of the display columns Y j  at the crosspoints with the odd row electrodes X 2m-1  (m=1, 2, . . . I/2), and connected to the picture cells on the even rows at the crosspoints with the even row electrodes X 2m  (m=1, 2, . . . I/2). For example, the A-column electrode Y A1  is connected to the picture cell on the first row at the crosspoint with the row electrode X 1 , and connected to the picture cell on the fourth row at the crosspoint with the row electrode X 2 . 
     The B-column electrodes Y Bj  are connected to the picture cells on the even rows of the display columns Y j  at the crosspoints with the odd row electrodes X 2m-1   (m=1, 2, . . . I/2), and connected to the picture cells on the odd rows of the display columns Y j  at the crosspoints with the even row electrodes X 2m  (m=1, 2, . . . I/2). For example, the B-column electrode Y B1  is connected to the picture cell on the second row at the crosspoint with the row electrode X 1  and connected to the picture cell on the third row at the crosspoint with the row electrode X 2 . 
     Thus, the A-column electrodes Y Aj  and the B-column electrodes Y Bj  are connected to the picture cells on the odd rows of the display columns Y j  at certain crosspoints and connected to the picture cells on the even rows at other crosspoints. The present invention is applicable to such a system. No reconfiguration of the device is necessary. The configuration of the present embodiment is identical to that of FIG. 6 except the matrix display panel which is shown in FIG. 8. 
     A difference between the present embodiment and that of FIG. 6 resides in the manner in which the switch 12 is operated. The operation of the present embodiment is explained below with reference to FIG. 9. 
     In the present embodiment, the sampling pulse CP 1  and the digital video signal SD 1  are generated during the scan line period like in the case of FIG. 7 and they are omitted in FIG. 9. The buffer memory write clock CP 2 , the buffer memory read clock CP 3  and the digital video signal SD 2  are also identical to those shown in FIG. 7, and the buffer memory 11 stores the odd rows of the scan line of video data and outputs SD 2  during the even row periods of the scan line. 
     The switch 12 is controlled by the switching clock CP 4 . In the second row period of the scan line, it alternately selects the digital video signals SD 1  and SD 2  and outputs the digital video signal SD 3  having twice number of data like in the case of FIG. 7. The switching sequence is identical to that of FIG. 7, that is, the first row of the scan line of video data, SD 2 , is produced at the beginning of SD 3 , and then the second row of the scan line of video data, SD 2 , is produced next. 
     The signals applied to the column electrode driver 10 and the row electrode driver 6 and the operations of those circuits are identical to those in FIGS. 6 and 7. Accordingly, as shown in FIG. 9, the row electrode X 1  is selected between the third and fourth row periods of the scan line, and the column electrode drive signals V YAj  and V YBj  corresponding to the first and second rows of the scan lines are applied to the column electrodes Y Aj  and Y Bj . At the same time, the column electrode drive signals V YAj  and V YBj  corresponding to the first row and second row of the scan line of video data are applied to the A-column electrode Y Aj  and the B-column electrode Y Bj , respectively. 
     On the other hand, in the fourth row period of the scan line, the clock CP 4  is different from that in the second row period of the scan line so that the switch 12 first selects the fourth row of the video data, SD 1 , and then selects the third row of the video data, SD 2 . The digital video signal SD 3  thus produced is written into the line memory 101 and converted to the column electrode drive signals V YAj  and V YBj  between the fifth and sixth row periods of the scan line, and those signals are applied to the column electrodes Y Aj  and Y Bj . At this time, the second row electrode X 2  is in a selected state, and the column electrode drive signals V YAj  and V YBj  corresponding to the fourth row and third row of the video data are applied to the A-column electrode Y Aj  and the B-column electrode Y Bj , respectively. Referring to the matrix display panel shown in FIG. 8, the data corresponding to the third row of the scan line is displayed on the picture cells on the third row of the display column Y j  while the second row electrode X 2  is selected, and the data corresponding to the fourth row of the scan line is displayed on the picture cells on the fourth row of the display column Y j . The display operations for the fifth and following rows are repetitions of those for the first to fourth rows. 
     The feature of the present embodiment resides in that the order of writing the video data into the line memory is changed for each scan line depending on the opposing status of the row electrode and the column electrode. 
     In the present embodiment, since the order of the arrangement of the terminals of the column electrodes of the matrix display panel coincides with the order of the arrangement of the outputs of the column electrode driver, the signal connecting lines for the column electrodes and the column electrode driver do not cross. 
     EMBODIMENT 3 
     FIGS. 10 and 11 illustrate a third embodiment in which the present invention is applied to an alternate quadruplex matrix display device. In those figures, the like numerals to those shown in FIGS. 6 through 9 denote the corresponding elements. 
     In the alternate quadruplex matrix display panel 7, four rows of picture cells oppose each row electrode X i  (i=1, 2, . . . I). The column electrode of each display column Y j  (j=1, 2, . . . J) is divided into four groups to define A-column electrodes Y Aj , B-column electrodes Y Bj , C-column electrodes Y Cj  and D-column electrodes Y Dj . In FIG. 10, the picture cells opposing to the adjacent row electrodes, for example, X 1  and X 2 , are connected in such a manner that the picture cells which define the first row opposing X 1  (first row of picture cells) and the picture cells which define the last row opposing X 2  (eighth row of picture cells) are connected to the A-column electrodes Y Aj  (j=1, 2, . . . J), the picture cells which define the second row opposing X 1  (second row of picture cells) and the picture cells which define the next to the last row opposing X 2  (seventh row of picture cells) are connected to the B-column electrodes Y Bj , the third and sixth rows of picture cells are connected to the C-column electrodes Y Cj , and the fourth and fifth rows picture cells are connected to the D-column electrodes Y Dj . With this arrangement, a three dimensional wiring or detoured wiring is not necessary in connecting the picture cells (column electrodes) in the quadruplex matrix display panel. 
     In the matrix display panel 7 of the present embodiment, 4I rows by J columns of picture cells are defined. 
     The A-column electrodes Y Aj  and the B-column electrodes Y Bj  are arranged on one side of the first substrate 9 of the matrix display panel 7 and connected to the AB-column electrode driver 10, and the C-column electrodes Y Cj  and the D-column electrodes Y Dj  are arranged on the other side of the first substrate 9 and connected to a CD-column electrode driver 20. The line memory write clocks generated by the timing control circuit 3 include CP AB  and CP CD  which are supplied to the AB-column electrode driver 10 and the CD-column electrode driver 20. The other elements in FIG. 10 are identical to those of FIG. 6. 
     FIG. 11 illustrates the operation of the third embodiment of the present invention. 
     The sampling clock CP 1  and the digital video signal SD are generated during each row period of the scan line as they are generated in the first and second embodiments, and they are omitted in FIG. 11. Like in the first and second embodiments, the buffer memory write clock CP 2  is generated at each odd row ((2n-1)th row, where n=1, 2, . . . 2I) period of the scan line and the buffer memory read clock CP 3  is generated at each even row ((2n)th row) period of the scan line. Accordingly, the digital video signal SD 2  from the output of the buffer memory 11 is generated at the even row ((2n)th rows) periods of the scan line and comprise the odd rows ((2n-1)th rows) of the scan line of video data. SD 2  is omitted in FIG. 11. 
     The switch 12 receives the digital video signals SD 1  and SD 2  and the switching clock CP 4  and alternately selects SD 1  and SD 2  in the even row periods of the scan line in synchronism with the switching clock CP 4  to produce the digital video signal SD 3 . 
     Considering the first to eighth rows of the scan line, in the second row period of the scan line the first row of the scan line of video data appears first in SD 3  and the second row of the scan line of video data follows. In the fourth row period of the scan line the third row of the scan line of video data appears first in SD 3  and the fourth row of the scan line of video data follows. On the other hand, in the sixth and eighth row periods of the scan line, the even rows, that is, the sixth and eighth rows of the scan line of video data appear first in SD 3  and the odd rows, that is, the fifth and seventh rows of the scan line of video data follow. 
     The line memory write clock CP AB  is first generated at the second row period of the scan line so that the first and second rows of the video data produced in the second row period are written into the line memory of the AB-column electrode driver 10 by the digital video signal SD 3 . The line memory write clock CP CD  is first generated at the fourth row period of the scan line so that the third and fourth rows of the video data produced in the fourth row period are written into the line memory of the CD-column electrode driver 20 by the digital video signal SD 3 . 
     In the present embodiment, the strobe pulse STB is generated when the first to fourth rows of the scan line of video data have been written into the line memories so that the video data is latched and the first row electrode X 1  is selected in the fifth to eighth row periods of the scan line. The video data are modulated into the column electrode drive signals V YAj , V YBj , V YCj  and V YDj  by the modulator, and the first row of the scan line of video data is supplied to the A-column electrodes Y Aj , the second row of the scan line of video data is supplied to the B-column electrodes Y Bj , the third row of the scan line of video data is supplied to the C-column electrodes Y Cj  and the fourth row of the scan line of video data is supplied to the D-column electrodes Y Dj . Accordingly, correct video data is displayed on the first to fourth rows of the picture cells on the display columns Y j  to correspond to the arrangement of the picture cells of the matrix display panel 7 of FIG. 10. 
     During the fifth to eighth row periods of the scan line in which the first row electrode X 1  is selected and the first to fifth rows of the scan line of video data for the display columns Y j  are displayed, the next video data, that is, the fifth to eighth rows of the scan line of video data, is supplied to the column electrode drivers 10 and 20. 
     As described above, in the sixth row period of the scan line, the sixth row of the scan line of video data appears first in the digital video signal SD 3  and the fifth row of the scan line of video data follows. At this time, the line memory write clock CP CD  is generated so that the fifth and sixth rows of the scan line of video data are written into the line memory of the CD-column electrode driver 20. 
     In the eighth row period of the scan line, the eighth row of the scan line of video data appears first in the digital video signal SD 3  and the seventh row of the scan line of video data follows. At this time, the line memory write clock CP AB  is generated so that the seventh and eighth rows of the scan line of video data are written into the line memory of the AB-column electrode driver 10. 
     When the fifth to eighth rows of the scan line of video data have been written into the line memories, the strobe pulse STB is generated so that the video data is latched and the second row electrode X 2  is selected during the ninth to twelveth row periods of the scan line. The video data is modulated into the column electrode drive signals V YAj , V YBj , V YCj  and V YDj  by the modulator, and the eighth row of the scan line of video data is supplied to the A-column electrodes Y Aj , the seventh row of the scan line of video data is supplied to the B-column electrodes Y Bj , and the sixth and fifth rows of the scan line of video data are supplied to the C-column electrodes Y Cj  and the D-column electrodes Y Dj , respectively. Thus, the fifth to eighth rows of the scan line of video data are displayed on the fifth to eighth rows of picture cells on the display columns Y j  in a correct sequence. 
     It will be readily understood that the display operations for the picture cells on the ninth and following rows a repetition of the operations described above. 
     In the present embodiment, the signal connecting lines for the column electrodes Y Aj  -Y Dj  and the column electrode drivers 10 and 20 do not cross. 
     EMBODIMENT 4 
     Referring to FIG. 12, like numerals to those shown in FIGS. 6 to 10 denote the like or corresponding elements. 
     In the third embodiment shown in FIGS. 10 and 11, the column electrodes are arranged on opposite ends of the first substrate 9 of the matrix display panel 7. In the fourth embodiment shown in FIG. 12, all of the column electrodes Y Aj  -Y Dj  are arranged on the same end of the first substrate 9 in the alternate quadruplex matrix display panel. 
     In FIG. 12, the column electrode driver 10 drives 4J column electrodes Y Aj , Y Bj , Y Cj  and Y Dj . The buffer memory 11 has three rows of capacity. In the (4i)th row (i=1, 2, . . . I) periods of the scan line, the (4i-3)th to (4i-1)th rows of the scan line of video data produced from the buffer memories 111, 112 and 113 and the (4i)th rows of the scan line of data produced from the A-D converter 2 are selected by the switch 12 and written into the line memory of the column electrode driver 10. The switch 12 is controlled by the switching clock CP 4  generated in the (4i)th row periods of the scan line so that the digital video signal SD 3  writes the (4i-3)th, (4i-2)th, (4i-1)th and (4i)th rows of the scan line of video data into the line memory in the (4i)th row period of the scan line. The video data is written into the line memory in a order of (4i-3) row, (4i-2)th row, (4i-1)th row, (4i)th row when i is odd, and (4i)th row, (4i-1)th row, (4i-2)th row and (4i-3)th row, when i is even. The strobe pulse STB is generated when the four rows of the scan line of video data have been written into the line memory. 
     Accordingly, when the odd row electrodes X 1  are selected, the (4i-3)th rows of the scan line of video data are supplied to the A-column electrodes Y Aj , the (4i-2)th rows of the scan line of video data are supplied to the B-column electrodes Y Bj , the (4i-1)th rows of the scan line of video data are supplied to the C-column electrodes Y Cj  and the (4i)th rows of the scan line of video data are supplied to the D-column electrodes Y Dj . When the even row electrodes X i  are selected, the (4i)th rows of the scan line of video data are supplied to the A-column electrode Y Aj , the (4i-1)th rows of the scan line of video data are supplied to the B-column electrodes Y Bj , the (4i-2)th rows of the scan line of the C-column electrodes Y Cj  and the (4i-3)th rows of the scan line of video signal are supplied to the D-column electrodes Y Dj . In this manner, the video data is displayed in a correct order. 
     In the present embodiment, the signal connecting wires for the column electrodes Y Aj  -Y Dj  and the column electrode driver 10 do not cross. 
     EMBODIMENT 5 
     FIG. 13 shows an embodiment having a frame memory for storing one frame of video data. 
     Referring to FIG. 13, the video data circuit 100 comprises a memory driver 300 and a frame memory 301. The memory driver 300 includes an A-D converter 2, a timing control circuit 3, a write address counter 60, a read address counter 61, adders 62 and 63 and a multiplexer 64. Like numerals to those shown in FIG. 6 denote like or corresponding elements. The matrix display panel 7 has four rows by three columns of picture cells (1.1), (1.2), . . . (4.3). A circuit operation for firing the hatched picture cells in FIG. 13 is specifically explained with reference to FIGS. 14a and 14b. 
     FIG. 14a illustrates a time chart for explaining the write operation of the frame memory. The video signal VD is converted to the digital video signal SD 1  by the A-D converter 2, and the video data D 11 , . . . D 43  in one frame period corresponding to the picture cells (1.1), . . . (4.3) is stored in the frame memory 301 by the output signal WA from the write address counter 60. 
     FIG. 14b illustrates a time chart for explaining the read operation of the frame memory. An output signal CR 1  of the read address counter 61 is combined with a signal CR 2  of the adder 62 to produce a signal CR 3 . A portion of the output signal CR 3  of the adder 62 is combined with a signal CR 4  of the adder 63 to produce a signal CR 5 . The output signal CR 3  of the adder 62 and the output signal CR 5  of the adder 63 are supplied to the multiplexer 64 where they are alternately selected by a switching pulse CP R  to produce a read address signal RA. The video data D 11 , D 21 , D 12 , D 22 , D 13 , D 23  at the addresses specified by RA form the digital video signal SD 3 , which is then stored in the line memory 101. Then, the operation similar to that in the first embodiment shown in FIGS. 6 and 7 is carried out. 
     In the present embodiment, the signal connecting wires for the column electrodes Y Aj  and Y Bj  (j=1, 2, 3) and the column electrode driver 10 do not cross. 
     EMBODIMENT 6 
     Referring to FIG. 15, the video data circuit 100 comprises the memory driver 300, the frame memories 301 and 302 and the switch 12. The memory driver 300 includes the A-D converter 2, the timing control circuit 3, a switch 13, an address selector 200, a write address counter 201 and a read address counter 202. In FIG. 15, like numerals to those shown in FIGS. 6 and 13 denote like or corresponding elements. 
     In FIG. 15, the frame memories 301 and 302 are so divided that they correspond to the A-column electrodes Y Aj  (j=1, 2, 3) and the B-column electrodes Y Bj  of the matrix display panel 7. The first and third rows of the scan line of video data D 11 , D 12 , Dhd 13, D 31 , D 32 , D 33  are stored in the frame memory 301 and the second and fourth rows of the scan line of video data D 21 , D 22 , D 23 , D 41 , D 42 , D 43  are stored in the frame memory 302. The video data stored in the frame memories 301 and 302 is selected by the switch 12 and transferred to the line memory 101. 
     FIGS. 16a and 16b illustrate time charts for explaining the operation of FIG. 15. When a frame memory write/read control signal WE is logical &#34;H&#34;, the data is written, and when it is &#34;L&#34; the data is read. When a chip select signal CS is logical &#34;H&#34;, a chip is selected and the data is written at a leading edge of a frame memory write clock CP F . 
     In the write operation, the switch 13 is thrown to the &#34;H&#34; position and the address selector 200 selects the write address signal WA at the output of the write address counter 201 by the control signal CP A  to produce WA as an address output A. The write address signal WA is produced from a computer in the sequence as shown in FIG. 16a to specify the addresses in the frame memories 301 and 302 in synchronism with the digital video signal SD 1 . The chip select signal CS defines a select block in the frame memory and it is generated at a timing as shown in FIG. 16a in the write operation. Accordingly, at the leading edge of the frame memory write clock CP F , the first and third rows of the video data D 11 , D 12 , D 13 , D 31 , D 32 , D 33  are stored in the frame memory 301, and the second and fourth rows of the video data D 21 , D 22 , D 23 , D 41 , D 42 , D 43   are stored in the frame memory 302. The frame memory write pulse CP F  is generated after the write address signal has sufficiently risen to enable the discrimination. 
     In the read operation, the write/read control signal WE in FIG. 15 is set to &#34;L&#34; and the address selector 200 selects a read address signal RA at the output of the read address counter 202 by the control signal CP A  and produces RA as the address output A. The read address signal RA is produced in the sequence as shown in FIG. 16b at the double period of that of the digital video signal SD, to specify the addresses of the frame memories 301 and 302 in the read operation. 
     The chip select signal CS is generated at a timing as shown in FIG. 16b at one third of the period for the write operation and it forms a chip selection circuit together with a NOT circuit to select either the frame memory 301 or the frame memory 302. During the period of the read address signal RA, the switch 12 is switched by the clock pulse CP 4  so that the video data in the frame memories 301 and 302 are alternately transferred to the line memory 6 by the digital video signals SD 21  and SD 22 . Accordingly, the digital image signal SD 3  includes D 11 , D 21 , D 12 , D 22 , D 13 , D 23  in this sequence. 
     The operations from the parallel data conversion by the line memory 101 to the application of the voltages to the column electrodes are identical to those of the previous embodiment and hence the description thereof is omitted here. 
     In FIG. 15, the output signals of the frame memories 301 and 302 are selected by the switch 12. Where tri-state frame memories 301&#39; and 302&#39; are used as shown in FIG. 17, the switch 12 may be omitted. 
     In the embodiments of the present invention thus far described, multi-matrix or duplex, alternate duplex, and alternate quadruplex matrix systems have been explained. The present invention is also applicable to other multiplex matrix systems or alternate multiplex matrix systems or even a multi-stage matrix system having divided row electrodes so long as the column electrodes of each display column are electrically divided into a plurality of groups and the terminals of at least two groups of the divided column electrodes are arranged on the same side of the matrix display panel. 
     In the illustrated embodiments, the video signal VD is converted to the digital video signal SD 1  by the A-D converter 2. In a character display device which does not need gray levels, the digital video signal SD 1  may be a binary signal which discriminates black and white levels. 
     The memories such as the line memories and the buffer memory may be analog memories such as charge coupled device (CCD) memories. The inputs to the memories may be either digital signals or analog signals so long as they are video data signals. When an analog signal is used, the A-D converter may be omitted. 
     While all of the scan lines of the video signal VD are used for display in the illustrated embodiments, the present invention is equally applicable when every m-th row is used for display. 
     The switch 12 may be any electronic circuit which selects the video data and it may be constructed by logical gates. 
     The present invention is applicable to not only the liquid crystal display but also other displays such as electroluminescence display or plasma display. 
     As described hereinabove, according to the present invention, the signal connecting wires for the column electrodes and the column driver do not cross and the outputs of the column electrode driver and the column electrodes can be simply connected in one-to-one correspondence. Thus, a matrix display device which facilitates the wiring work can be provided.