Patent Publication Number: US-8532288-B2

Title: Selectively isolating processor elements into subsets of processor elements

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application contains subject matter which is related to the subject matter of the following documents, each of which is assigned to the same assignee as this application. Each of the below listed documents is hereby incorporated herein by reference in its entirety:
         U.S. Pat. No. 7,080,110 titled “Hardware Implementation for Modular Multiplication Using a Plurality of Almost Entirely Identical Processor Elements,” issued Jul. 18, 2006.   U.S. Pat. No. 6,978,016 titled “Circuits for Calculating Modular Multiplicative Inverse,” issued Dec. 20, 2005.       

     The above referenced issued patents are each members of a family of patent documents. The specifications of these documents are similar to the specifications of the other documents in the family. 
     TECHNICAL FIELD 
     The present invention is generally directed to encryption and decryption engines. In particular, it is directed to the use of a cryptographic engine which is constructed as a set of nearly identical processing elements which set is capable of being partitioned to operate in a variety of ways. This engine is described in detail in U.S. Pat. No. 7,080,110, which is referenced above. Even more particularly, the present invention is directed to systems and methods for carrying out multiplication modulo N, typically a large prime number. 
     BACKGROUND OF THE INVENTION 
     In the processing of cryptographic information, which includes both encryption and decryption, multiplication modulo a large prime number is a key step in the ultimately desired process of exponentiation modulo a large prime number. For purposes of this processing cryptographic keys are employed. The length of the key is the principal determiner of security. The longer the key (in bits), the greater is the security level. Because of the ever increasing capabilities of data processing hardware, the length of keys to meet desirable levels of security has steadily increased. The cryptography engine described in the referenced patent is capable of expansion to meet these needs. However, it is noted that in the field of cryptography, the keys that are employed are often of varying size. This is reflective of the fact that different users of cryptography will seek different levels of security. For example, one user might be satisfied with a key length of 1,024 bits while another might insist on using 4,096 bit keys. While a cryptographic engine that is capable of processing 4,096 bit keys could also process 1,024 bit keys, the processing power of the hardware that is applied to that problem is essentially wasted. 
     In U.S. Pat. No. 7,080,110 referenced above, there is disclosed a circuit for performing multiplication modulo N, where N is a large prime number. Such circuits are useful for carrying out exponentiation operations modulo N. As mentioned above, these mathematical operations lie at the heart of a significant number of methods for encrypting and decrypting data. The circuits disclosed therein provide a powerful and flexible method for constructing and using concatenated arrays of what are referred to as “processing elements.” The similarity in structure of these processing elements is also seen to be of value in structuring a process in which operations are pipelined, thus increasing overall throughput. Accordingly, it is seen that the referenced issued patent provides a useful cryptographic engine which is used in the present invention. However, the present application describes a method of using the processing elements in a more flexible fashion to avoid the situation in which full hardware utilization fails to be achieved when there is a mix of cryptographic tasks presented to the engine. 
     SUMMARY OF THE INVENTION 
     The shortcomings of the prior art are overcome and additional advantages are provided through a method for controlling operations in a plurality of serially connected cryptographic processor elements. The method comprises the steps of supplying data to be processed in blocks to a plurality of subsets of the processor elements; and controlling the input and output from each one of the subsets of the processor elements so as to selectively isolate the processing elements into blocks matching the supplied blocks for processing the data independently. 
     In accordance with another embodiment of the present invention there is provided a method for operating a set of serially connected processing elements configured for carrying out multiplication modulo N. The method comprises supplying data to the circuit in blocks of varying size and controllably partitioning the processing elements into blocks matching the varying sizes of the blocks in the data. 
     In both of the methods set forth above it is desirable to prepackage blocks of data into groups most of which match in size the total number of the serially connected processing elements. For example, if the total size that the serially connected processing elements can handle 4,096 bits, then the data might be grouped in packages of 2048, 1024, 512 and 512 bits. It is desired that in each group the total number of bits being processed (2048+1024+512+512, in the above example) is equal to the capacity of the collection of serially connected processing elements. While it is recognized that this grouping is desirable, it is not essential. However, it is noted that the flexible partitioning of the serially connected processing elements provides a mechanism for reaching this objective. 
     Accordingly, it is seen that it is an object of the present invention to improve the operations of cryptographic devices for encoding, decoding, signature verification and authentication. 
     It is also an object of the present invention to exploit the block structure present in a cryptographic engine which is structured as a serially connected chain of nearly identical processing elements. 
     It is yet another object of the present invention to make better use over time of cryptographic engines which are structured as a serially connected chains of processing elements. 
     It is a further object of the present invention to make the fullest possible use of hardware present in the processing of a cryptographic instruction. 
     It is a still further object of the present invention to keep the processing elements as busy as possible. 
     Additional features and advantages are realized through the systems and methods of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. 
     The recitation herein of a list of desirable objects which are met by various embodiments of the present invention is not meant to imply or suggest that any or all of these objects are present as essential features, either individually or collectively, in the most general embodiment of the present invention or in any of its more specific embodiments. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of practice, together with the further objects and advantages thereof, may best be understood by reference to the following description taken in connection with the accompanying drawings in which: 
         FIG. 1  is a block diagram illustrating how individual processor elements are connected to produce the same results as a circuit in which much larger adder and multiplier elements would need to be employed; 
         FIG. 2  is a block diagram more particularly illustrating how one might partition a group of processor elements to perform operations in parallel on smaller blocks of data; 
         FIG. 3  is a block diagram illustrating three typical ways in which a set of processor elements are may be partitioned; 
         FIG. 4  block diagram illustrating the circuit that is partitioned into a sequence of processing elements for a method and system for multiplication modulo N; 
         FIG. 5  is a block diagram providing a detailed view of the construction of one of the processing elements referred to in  FIG. 1 ; and 
         FIG. 6  is a block diagram providing a detailed view of the construction of the rightmost processing element, P 0 . 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  illustrates the overall pattern of processing element connections employed for the purpose of carrying out multiplication modulo N. In particular  FIG. 1  illustrates the connection pattern for the plurality of processing elements that are derived from the circuit structure shown in  FIG. 4 .  FIG. 4  illustrates a modified Montgomery multiplication structure for multiplication modulo N from the point of view of carrying out the processing steps in two phases. The inventors in the cited patent realized that the “wide” processing elements in  FIG. 4  can be broken up into a series of processing elements  200 . These processing elements, as shown in detail in  FIG. 5 , are arranged serially as shown in  FIG. 1  with the processing element on the right passing a Partial Product Output (PPO) and two carries, C 1  and C 2 , to the processing element on its left. For both the zeroeth and the last processing elements (100 and 300, respectively) minor changes are made in the circuitry as shown in the cited patent. 
     The structure shown in  FIG. 1  is shown in slightly more detail in  FIG. 2 . However, in  FIG. 2  processing elements  100 ,  200  and  300  are shown in a configuration in which they are arranged in blocks. In operation, even those which take advantage of pipelining, the circuit of the cited patent, for which the present application is an improvement, works in a fashion in which downstream processing elements are not fully utilized all of the time. However, by providing input register bank  400 , controlled by circuit  450 , blocks of processing elements are operated independently on smaller chunks of data to produce independent output data in output register bank  500 . 
     This is useful when the data is structured as shown in  FIG. 3 . For example, if there are 64 registers with 64 bits each, corresponding to Processing Elements PE 0  through PE 63 , the system is capable of processing a single 4,096 bit multiplication. Eventually, in the course of processing this information, the Processing elements on the left will become actively engaged in this processing. Pipelining the data eventually keeps all of the Processing Elements in an active processing state. However, if the task switches to processing two multiplications, each with 2,048 bits, the originally contemplated operation of the cited circuits processes them in a serial fashion. However, by controlling the information loaded into input register bank  400 , and isolating via control circuit  450  the Processing Elements into blocks as suggested in  FIG. 2 , it is possible to now simultaneously process two multiplications each having 2,048 bits, thus assuring that more of the Processing Elements are busier more of the time. Likewise,  FIG. 3  further extends this concept to the situation in which four blocks of isolated Processing Elements are simultaneously processing the multiplication of 1,024 bit entries. Again, by providing the data in blocks and by isolating the Processing elements, it is possible to keep more of the hardware busier more of the time. As described above, the Processing Elements are also capable of processing a single 2,048 bit multiplier and two 1,024 bit multipliers. Other processing partitions are equally possible with a natural proclivity to employ blocks whose sizes are powers of two. 
     A hardware circuit for carrying out this process is illustrated in  FIG. 4 . In particular, the factor A of n+1 bits, which is a factor which is treated as being in partitioned form, is stored in A register ( 10 ). Multiplexor  11  supplies sequential blocks of k bits from register  10  to multiplexor  31 , with k=32 bits for illustration. Multiplexors  31 ,  21 , and  52  operate in conjunction with one another selecting one of two possible input values depending upon whether or not the circuit is operating in the X-phase or the Z-phase. Accordingly, during the first phase of its operation, multiplexor  11  provides the k bits in A 0 . In the first phase of the second cycle, the next k bits A 1  in A are supplied via multiplexor  11 . A sub-block of k bits from A is provided during the initial or X phase portion of each cycle. In the third cycle, multiplexor  11 , therefore, provides the next k bits in A, namely, the bits denoted above and herein as A 2 . Accordingly, multiplexor  11  is seen to operate selectively as a function of the cycle number (namely, cycles 0 through m−1). 
     During the X-phase of each cycle, the value A 1  is selected from the A Register ( 10 ) via multiplexor  11  and correspondingly multiplexor  21  selects the contents of the B Register ( 20 ). Thus, the numbers to be multiplied are stored in registers  10  and  20 . It does not matter which number is stored in which register. It is also noted that, whether or not the circuit is operating in the initial X-phase or in the final Z-phase in each cycle, multiplexors  31  and  21  supply k bits and n+1 bits, respectively, to multiplier array  70  in each phase. It is thus seen that, during the X-phase, multiplexors  31  and  21  select contents from the B register and part of the A register. It is also noted that, in one exemplar situation, the value of n is around 512 or some other convenient power of 2 and the value of k is 32. Accordingly, it is seen that multiplier array  70  strikes a balance between 1 bit×n bit multiplication and full n bit×n bit multiplication. It is also noted that increases in the value of n are almost always, in practice, an increase by a factor of a power of two. 
     As with any binary multiplier with inputs that are n+1 bits wide and k bits wide respectively, multiplier array  70  produces an output which is n+1+k bits wide. The lower order k bits from multiplier array  70  are supplied to adder  65  which is designed to add two k bit addends at a time. In this regard, it is noted that adder  65  is present in the circuit for computing y 1 . As such, and given that the value of y 1  is dependent upon the last k bits of the value X 1  which is a sum which has not yet been fully computed, it is necessary to perform this addition which is essentially the addition for the low order k bits of X 1 . The first addend comes from the rightmost k bits in the Z register as selected by multiplexor  52 . These bits are added to the k bits in the rightmost portion of the product A 1 B. The output of adder  65  is x 1,0  which is the least significant k bits of X 1 =Z 1 +A 1 B. This output is stored in register  55  and is also supplied to multiplier  80  which multiplies two k bit numbers together. This is not, however, a multiplication modulo N. The other factor supplied to multiplier  80  is the number s from the s register ( 60 ). Since this result is required modulo R, only the rightmost k bits from multiplier  80  are supplied back to the y register ( 30 ) in this X-phase. The value stored in this register is used during the calculation carried out in the Z-phase as discussed below. 
     The rest of the X-phase calculation is devoted to calculation of the high order n+1 bits of the sum Z 1 +A 1 B. Multiplier  70  is configured as a circuit for multiplying together the bits from the B Register ( 20 ) and a sequence of m blocks of k bits each from selected k bit blocks from the A register. Multiplication of two k bit numbers generally produces a number having 2k bits and, in particular, this is the situation with respect to applicants&#39; multiplier  80 . However, it is noted that the calculation of y, is computed modulo R. The modulo requirement of the computation is easily accomplished simply by returning only the rightmost k bits from the output of multiplier  80  to the input of y register  30 . 
     As pointed out above, multiplication of numbers generally produces outputs having bit lengths greater than either of the two input number bit lengths. In particular, with respect to multiplier  70 , the output is considered to be n+1+k bits in length. The low order (rightmost) k bit output is supplied from multiplier  70  to adder  65 . However, each k bit block multiplication carried out in multiplier array  70  produces 2k bits formed as a k bit “result” and a k bit “carry” into the next position. The summation to produce the desired intermediate output A 1  is carried out in adder  75  which adds together two portions, the first portion which is n+1 bits long and the second portion which is only n+1−k bits long. The n+1−k bits represent the “carry” portion of the multiplication. Accordingly, the output of adder array  75  is the result of the high order n+1 bits of A 1 B. This result is supplied directly to adder array  85  which adds to it a shifted value of Z 1  from Z register  50 . And appropriately, these high order n+1 bits of X 1 =Z 1 +A 1 B is stored in Z register  50  in preparation for the Z-phase calculation. The low order k bits of X 1  are stored in register  55  as described above. 
     In the Z-phase of an operation cycle, multiplier array  70  and adders  75  and  85  are again employed except that now the inputs to multiplier array  70  are the contents of y register  30  as selected by multiplexor  31 . The other factor supplied to multiplier array  70  is the contents of N register  40  which is selected during the Z-phase of an operation cycle by means of multiplexor  21 . As before, multiplier array  70  computes the product of an n+1 bit number and a k bit number. Adder array  75  performs the natural addition operation associated with multiplication in which there is an effective carry-like operation from one k bit subfield to the next k bit subfield. Accordingly, the output of adder array  75  during the Z-phase of operation is the high order n+1 bits of the product y 1 N. The addition of y 1 N and the value X 1  together with its division by R in the present method is accomplished by discarding the low order k bits from the output of adder  65  and storing only the high order n+1 bits from adder  85  to register  50 . 
     Attention is now directed to a discussion of  FIG. 5  which illustrates a typical processor element and, in particular, which illustrates the form of a processor element which may be repeated in a circuit/system chain which is as long as is required to process factors which are n bits wide. Such a chain is shown in block diagram form in  FIG. 1 . 
     With reference to  FIG. 5 , it is noted that it describes a Processing Element that is similar to the zeroeth Processing Element P 0 , except that the part of the processing dealing with k bit wide operations involving s and N 0  need not be present in any processing elements except PE 0 . In particular,  FIG. 5  indicates that the generic form of a processing element PE p  bearing reference numeral  200  specifically does include register BN (reference numeral  298 ) but does not include the registers associated with P 0 . One of the significant differences between the zeroeth Processing Element P 0  and the generic Processing Element P p  is that register  220  contains only a portion of the bits for the second factor B. In particular, register  220  contains 2k bit wide chunks designated as B 2p+2  and B 2p+1 , where p ranges from 1 to d−1. Again, as above, multiplexer  221  selects either the 2k bits from register  220  or the 2k bits from register  240  which has corresponding portions (here  2   k  bits chunks) of the variable N. Accordingly, BN register  298  is 2k bits wide. In one exemplar embodiment of the present invention when n=512, register BN is 64 bits wide. 
     With specific reference to  FIG. 6 , it is seen that multiplexor  193  operates during the X-phase to supply a 2k bit augend to adder  185 . During the first or X-phase of operation, multiplexor  193  supplies a 2k bit number which has leftmost bits from register R 2  (reference numeral  192 ) and rightmost bits from register R 1  (reference numeral  191 ). During the second or Z-phase of operation, multiplexor  193  supplies a different  2   k  bits of data to adder  185 . In particular, during the Z-phase, multiplexor  193  supplies as its leftmost k bits the contents of register R 1 , and as its rightmost k bits the contents of register R 0  (reference numeral  190 ). 
     In contrast to the full-width registers  10 ,  20 ,  40 , and  50  in  FIG. 4 , the corresponding registers in a partitioned system have fewer bits. In particular, the corresponding B and N variable registers in a general processing element PE preferably employ a width equal to 2k bits. However, for the rightmost processing element, P 0 , a larger number of bits is desired. In particular, in the case in which n equals 512, registers  120  and  140  in  FIG. 4  preferably have a width of 96 bits. Multiplexor  121  selects the contents of register B (reference numeral  120 ) during the X-phase of computation and likewise selects the contents of register N (reference numeral  140 ) during the Z-phase of computation. In general, the overall n-bit wide series of computations is broken down into partitions of any convenient size. It is not even necessary that all of the processor elements are the same size or that they process data having the same width. However, for conveniences of circuit design and circuit layout, it is preferable that each of the individual processing elements (except for the rightmost element, PE 0 ) have the same data processing capability in terms of data width. Therefore, in general, for purposes of consideration and discussion herein, it is assumed that there are a total of d+1 processing elements labeled from PE 0  through PE d . Processing element PE 0  preferably has a structure such as that shown in  FIG. 6 . PE d  has the preferred structure illustrated in FIG. 6 of U.S. Pat. No. 6,978,016 referred to above. However, it is noted that a the more generic structure, such as that shown in  FIG. 5 , may also be employed for the leftmost processor element PE d  though it is not necessary that this leftmost processing element be any more complicated than that shown in the aforementioned  FIG. 6 . 
     Also, for purposes of convenience of circuit design, layout, and packaging efficiency, it is generally desirable that the data width, W, of each processing element be an integer multiple of k. In the designs presented herein for a value of n=512, processor elements PE 1  through PE d−1 , each process data in 2k bit wide chunks. Thus, in this example, W=2k, where W is the width of the data in each of the typical or generic forms of processing element. It is noted that processor element PE 0  as shown in  FIG. 6  possesses an extra k bit processing capability, as is more particularly described below. Thus, if each typical processing element PE 1  processes data in W bit wide chunks and if there are d+1 processing elements with the rightmost processing element processing an extra k bits, then it is the preferred case that n=Wd+k. Thus, in general, the output of multiplexor  121  preferably comprises W+k bits. The leftmost third of these bits are supplied to multiplier  173 , the middle third of the bits in register BN (reference numeral  198 ) are supplied to multiplier  172 , and the rightmost third bits are supplied to multiplier  171 . Multipliers  171 ,  172 , and  173  are thus each k bit by k bit multipliers. In this regard, it is noted that the original relatively large multiplier array  70  in  FIG. 4  employs an n bit by k bit multiplier. However, it is noted that the partitioning of the computation into a system employing a plurality of nearly identical processing elements results in the construction of circuits which now utilize multipliers which operate much more quickly since each multiplier now is typically only k bits by k bits. And clearly, since k is typically much less than n, processing takes place significantly faster. 
     The leftmost of the 2k bits output from multiplier  173  are supplied as a partial product out (PPO) to the next unit in the chain, here P 1 . In particular, it should be appreciated that in the discussions herein, that the natural order of processing is from the rightmost on through to the leftmost processing element in the chain. Thus, data is passed from one processing element to the processing element on its immediate left. However, it should be noted that left and right are relative terms useful essentially only for descriptive and understanding purposes. The rightmost k bits from multiplier  173  are supplied as the leftmost k bits of a 2k bit augend supplied to adder  175 . The rightmost k bits of this 2k bit augend are supplied from the lower or rightmost k bits of multiplier  172 . Thus, the rightmost k bits of multipliers  173  and  172 , respectively, are combined, as shown in  FIG. 6  to supply a 2k bit wide augend to adder  175 . Adder  175  also has as its other input a 2k bit augend which is supplied from the leftmost k bits of multipliers  172  and  171 , respectively, with multiplier  172  supplying the leftmost k bits of the 2k bit augend and with multiplier  171  supplying the rightmost k bits of the 2k bit augend supplied to adder  175 . Thus, adder  175  is a 2k bit wide adder. An equivalent but alternate connection arrangement is shown in  FIG. 4A  of the cited patent to Chen et al. 
     Multiplexor  152  operates to select, during the X-phase of computation, k bits from register R 0  (reference numeral  190 ). During the Z-phase, multiplexor  152  selects as its input the contents of temporary register  150  containing the variable x 0 . The output of multiplexor  152  is supplied to adder  165  which is k bits in width. Adder  165  receives two augends, namely, the rightmost k bits from multiplier  171  and the k bits supplied from multiplexor  152 . The output of adder  165  is stored in temporary register  150  and is also supplied to multiplier  180  which is also a k bit by k bit multiplier. The other factor supplied to multiplier  180  is the contents of register  160  which contains the variable s. (The calculation of s as −1/N 0  mod R is efficiently carried out in the circuit shown in the patent to Chen et al. for which the present invention is an improvement.) The output of multiplier  180  is supplied to register  130  which thus contains the value y as defined by the algorithm set out in the cited patent. 
     The output of register  130  is supplied to multiplexor  131  and is also supplied to the next processing element PE 1  (see  FIG. 4 ). Multiplexor  131  operates to select a portion of the variable A which is one of the factors in the multiplication operation. (Other k bit wide portions of variable A are selected from registers associated with their respective processing elements.) In particular, in PE 0  register  110  contains the rightmost k bits of the variable A. Thus, during the X-phase of operation, multiplexor  131  operates to select the contents of register  110  to be supplied to multipliers  173 ,  172 , and  171 , as shown. Likewise, during the Z-phase of computation, multiplexor  131  operates to select the variable y from register  130  to be supplied to this same set of multipliers as the other factor. 
     A carry-out signal line from adder  165  is also supplied as a carry input to the lowest order position in adder  185 , as shown. Additionally, adder  175  supplies a first carry-out signal line to the next processing element in the chain; similarly, adder  185  also supplies a second carry-out signal line to the next processing element in the chain. In particular, since  FIG. 6  illustrates processing element PE 0 , carry-out signal line  1  and carry-out signal line  2  are both provided to the specific processing element PE 1 . The connections between PE 0  and PE 1  are readily apparent simply by placing  FIG. 6  to the right of  FIG. 5 . In particular, processing element PE 0  supplies the variable y, the partial product out, and the two carry-out signal lines to the inputs shown in PE 1  of  FIG. 5 . In particular, it is also noted that the variable y (that is, the contents of register  130 ) is also supplied to each one of the individual processing elements, PE 2  through PE d . And lastly, with respect to  FIG. 6 , it is noted that the output of adder  185  is supplied to registers R 0  and R 1  shown at the top of  FIG. 6 . As indicated above, it is the register set (containing R 1  and R 0  on the right) which ultimately contains the desired calculation result. Accordingly, reference numeral  400  in  FIG. 2  does not include this register set. This register set is discussed separately above in terms of some of the other variations and structures that are employed in the present invention. 
     From an overall perspective, generic processing element PE p  (reference numeral  200  as shown in  FIG. 1 ) accepts, as input from the right, the value of y (but only from P 0 ), the partial product in (PPI), carry-in  1  (C 1 ) and carry-in  2  (C 2 ). Processor element PE p  also has as an input the corresponding portion of the k bits of the multiplier factor A from register  210  (See  FIG. 5 ). The register involvement for registers,  292 ,  291 , and  290  is as shown in  FIG. 5 . It is these registers that store intermediate values between phases and ultimately store the completed product, AB mod N. Also, from an overall perspective, processor element  200  produces, as an output, a k bit partial product out which is supplied to the processor element on its left together with carryout signals  1  and  2  (C 1  and C 2 ) which are supplied to the corresponding adders  275  and  285  in the processor element on the left. The output of adder  285  is supplied back to registers R 2p+1  and R 2p . Accordingly, other than the connections to the register sets for R, B, N, and A, the processing elements are connected simply by matching partial products in and out and carries in and out (C 1  and C 2 ). Accordingly, in systems constructed in accordance with those aspects of the present invention which employ a plurality of similar processing units, the overall system is constructed by starting with the circuit shown in  FIG. 4  or  4 A of the cited patent as a rightmost position and placing, in adjacent positions, processing elements similar to those shown in  FIG. 5  herein. The overall configuration, therefore, is seen in  FIG. 1 . 
     In particular, it is noted that cryptographic engine(s)  195  exhibit a pipelined architecture such as those disclosed in U.S. Pat. No. 7,080,110. The partitioning of large arrays in the hardware structures of modulo N arithmetic circuits in cryptographic engine(s)  195 , for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of a two-phase operation, as described in the aforementioned patent, and the chaining together of the partitioned processing elements, the overall cryptographic engine structure is operable in a pipelined fashion to provide improved throughput and speed. 
     While the invention has been described in detail herein in accordance with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit and scope of the invention.