Patent Publication Number: US-2003224604-A1

Title: Sacrificial polishing substrate for improved film thickness uniformity and planarity

Description:
BACKGROUND  
       [0001] 1. Technical Field  
       [0002] The present invention generally relates to polishing semiconductor wafers. More particularly, the present invention relates to chemical-mechanical polishing of films that have been deposited on semiconductor wafers.  
       [0003] 2. Discussion of the Related Art  
       [0004] Integrated circuits (IC) are mass-produced by the fabrication of identical circuit patterns on a single semiconductor wafer. A series of wafer masking and processing steps are used to fabricate each IC. The IC&#39;s are fabricated from various materials, including conductors (e.g., copper, aluminum and tungsten), non-conductors (e.g., silicon dioxide), and semiconductors (e.g., silicon).  
       [0005] Within an IC, thousands of devices (e.g., transistors, diodes) are formed. Typically, contacts are formed where a device interfaces to an area of doped silicon. Specifically, plugs are typically formed to connect metal layers with device active regions. Vias are typically formed to connect metal layers with other metal layers. Also, interconnects are typically formed to serve as wiring lines to interconnect the devices on the IC and the many regions within an individual device. These contacts and interconnects are formed using conductive materials.  
       [0006] The IC devices with their various conductive layers, semiconductive layers, insulating layers, contacts and interconnects are formed by fabrication processes, including doping processes, deposition processes, photolithographic processes, etching processes, etc.  
       [0007] During IC manufacturing, the various masking and processing steps typically result in the formation of topographical irregularities on the wafer surface. For example, topographical surface irregularities are created after metallization, which includes a sequence of blanketing the wafer surface with a conductive metal layer and then etching away unwanted portions of the blanket metal layer to form a metallization interconnect pattern on the IC. A common surface irregularity is known as a step which results from the resulting height differential between the metal interconnect and the wafer surface where the metal has been removed.  
       [0008] Since these geometries are photolithographically produced, it is important that the wafer surface be highly planar in order to accurately focus the illumination radiation at a single plane of focus to achieve precise imaging over the entire surface of the wafer. A wafer surface that is not sufficiently planar will result in structures that are poorly defined, with the circuits either being nonfunctional or, at best, exhibiting less than optimum performance.  
       [0009] To alleviate these problems, the wafer is “planarized” at various points in the process to minimize non-planar topography and its adverse effects. As additional levels are added to multilevel-interconnection schemes and circuit features are scaled to submicron dimensions, the required degree of planarization increases. As circuit dimensions are reduced, interconnect levels must be globally planarized to produce a reliable, high-density device. Planarization can be implemented on either the conductor or the dielectric layers.  
       [0010] One common technique to planarize a wafer is known as chemical mechanical polishing (CMP). In general, CMP processing involves holding and pressing semiconductor wafers against a polishing pad mounted to a rotating turntable in the presence of a polishing solution (slurry). A conventional rotational CMP apparatus (see FIG. 1) includes a polishing head for holding a semiconductor wafer. The wafer is typically mounted with the surface to be polished exposed, on a wafer carrier, which is part of or attached to a polishing head. The polishing head is designed to be continuously rotated by a drive mechanism. In addition, the polishing head typically is also designed for transverse movement. The rotational and transverse movement is intended to reduce variability in material removal rates over the surface of the wafer.  
       [0011] The CMP apparatus further includes a rotating platen on which is mounted the polishing pad. The platen is relatively large in comparison to the wafer, so that during the CMP process, the wafer may be moved across the surface of the polishing pad by the polishing head. A polishing slurry containing chemically-reactive solution, in which are suspended abrasive particles, is deposited through a supply tube onto the surface of the polishing pad.  
       [0012] CMP is a well-developed planarization technique. The underlying chemistry and physics of the technique are understood. Certain limitations, however, exist with CMP. Specifically, the CMP process suffers from an inherent non-uniformity of the polishing surface between the center of the surface that is polished and the perimeter of the surface that is polished. During polishing, the pliability of the polishing pad tends to wrap around the edges of the wafer. As a result, the pad pressure is applied to a smaller area near the edges and causes a higher polishing rate at the edges relative to the center. The higher polishing rate produces non-uniformity in the film thickness, which could impact subsequent lithography processes and eventually edge die yield. The significance of mitigating polishing edge roll-off effects will grow as the wafer diameter grows for future technologies.  
       [0013] Therefore, there is a need for a method and device for polishing semiconductor wafers in a uniform manner, that eliminates polishing differences between the center of the wafer that is being polished and areas of the surface that extend toward the perimeter of the wafer surface.  
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0014]FIG. 1 illustrates a prior art conventional rotational Chemical Mechanical Polishing (CMP) apparatus;  
     [0015]FIG. 2 a  illustrates a rotational CMP apparatus including a sacrificial ring according to an embodiment of the present invention;  
     [0016]FIG. 2 b  illustrates a rotational CMP apparatus including a sacrificial disc according to an embodiment of the present invention;  
     [0017]FIG. 3 illustrates a comparison of wafer profiles according to an embodiment of the present invention;  
     [0018]FIG. 4 illustrates a method of manufacturing a sacrificial ring according to an embodiment of the present invention; and  
     [0019]FIG. 5 a - d  illustrates a method of manufacturing an integrated circuit according to an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION  
     [0020] An embodiment of the present invention is targeted to improve the film thickness uniformity and planarity, especially along the edge of the wafer. One of the issues seen in the polishing area for IC manufacturing is the non-uniform film thickness and poor planarity due to edge roll-off effects caused by high polishing rates at the edge of the wafer relative to the center.  
     [0021] A sacrificial substrate in the form of a sacrificial ring, whose inner diameter matches that of the outer diameter of the wafer to be polished, allows the wafer to sit flush inside the ring and allows the sacrificial ring to act as the sacrificial extension of the wafer to be polished. Therefore, the sacrificial ring experiences the edge roll-off instead of the wafer to be polished. As a result, the wafer to be polished has an improved flatness and film thickness uniformity by shifting the edge roll-off effects beyond the edge of the wafer to be polished outwards to the sacrificial ring.  
     [0022] An alternative embodiment of the present invention uses a sacrificial substrate in the form of a sacrificial disk having a recessed pocket cut out of a center of the sacrificial disc, a diameter of the recessed pocket being approximately equal to a diameter of a wafer to be polished, and a depth of the recessed pocket being approximately equal to a thickness of the wafer to be polished. The recessed pocket allows the wafer to sit flush inside the sacrificial disc and allows a polishing surface of the sacrificial disc to act as the sacrificial extension of the wafer to be polished. Therefore, the polishing surface of the sacrificial disc experiences the edge roll-off instead of the wafer to be polished. As a result, the wafer to be polished has an improved flatness and film thickness uniformity by shifting the edge roll-off effects beyond the edge of the wafer to be polished outwards to the polishing surface of the sacrificial disc.  
     [0023]FIG. 1 illustrates a conventional rotational Chemical Mechanical Polishing (CMP) apparatus  100 . The polishing head assembly  105  consists of a retaining ring  140 , bladder  150  and wafer  130 . The polishing pad  110  sits on top of the platen  120  while the wafer  130  fits inside the retaining ring  140 , with the bladder  150  exerting downward pressure against the wafer  130  to maintain contact between the wafer  130  and the polishing pad  110 . The retaining ring  140  acts as a “holder” to prevent the wafer  130  from sliding off the polishing pad  110  during the polishing process. The slurry supply  106  dispenses polishing slurry.  
     [0024]FIG. 2 a  illustrates a polishing apparatus with a polishing head  205  including a sacrificial ring  206 , according to an embodiment of the present invention. The polishing head assembly  205  is larger in diameter to accommodate the sacrificial ring  206  plus the wafer  230  to be polished. The polishing head assembly  205  consists of a retaining ring  240 , bladder  250 , sacrificial ring  206  and wafer  230 . The polishing pad  110  sits on top of the platen  120  while the wafer  230  fits inside the sacrificial ring  206 , which fits inside the retaining ring  240 . The bladder  250  exerting downward pressure against the wafer  230  and the sacrificial ring  206  to maintain contact between the wafer  230  and the polishing pad  110 . The retaining ring  240  acts as a “holder” to prevent the sacrificial ring  206  with the wafer  230  from sliding off the polishing pad  110  during the polishing process.  
     [0025] An alternate embodiment of the present invention uses a sacrificial disc  207  in place of the sacrificial ring  206 . FIG. 2 b  illustrates a polishing apparatus with a polishing head  208  including a sacrificial disc  207  according to an alternate embodiment of the present invention. The polishing head assembly  208  is larger in diameter to accommodate the sacrificial disc  207  plus the wafer  230  to be polished. The polishing head assembly  208  includes of a retaining ring  241 , bladder  250 , sacrificial disc  207 , and wafer  230 . The polishing pad  110  sits on top of the platen  120  while the wafer  230  fits inside a recessed pocket in the sacrificial disc  207 , which fits inside the retaining ring  241 . The bladder  250  exerting downward pressure against the sacrificial disc  207  and wafer  230  to maintain contact between the wafer  230  and the polishing pad  110 . The retaining ring  241  acts as a “holder” to prevent the sacrificial disc  207  plus wafer  230  from sliding off the polishing pad  110  during the polishing process.  
     [0026] A sacrificial substrate, in the form of a sacrificial ring  206  or a sacrificial disc  207 , allows the wafer  230  to sit flush inside the sacrificial ring  206  or sacrificial disc  207  and allows the sacrificial ring  206  or sacrificial disc  207  to act as the sacrificial extension of the wafer  230  to be polished. Therefore, the sacrificial ring  206  or sacrificial disc  207  experiences the edge roll-off effect instead of the wafer  230  to be polished. As a result, the wafer  230  to be polished has an improved flatness and film thickness uniformity by shifting the edge roll-off effects beyond the edge of the wafer  230  to be polished outwards to the sacrificial ring  206  or sacrificial disc  207 .  
     [0027]FIG. 3 shows the difference in planarity and film thickness uniformity using the sacrificial ring  206  of an embodiment of the present invention vs. the conventional approach. The graphs illustrate the expected wafer profile after polishing. The center of the wafers are flat except the edges roll off due to enhanced edge polishing rate near −R and +R for the conventional approach and −R′ and +R′ for the sacrificial ring  206  approach. The graph also shows that the wafer  230  is polished flat even at −R and +R for the sacrificial ring  206  approach because the impact of the enhanced polishing rate has shifted to the sacrificial ring  206  instead of the wafer  230  itself. The sacrificial disc  207  yields similar results.  
     [0028] The ability to control the edge-polishing rate with the current conventional approach is extremely difficult and has not been successful. As an alternative approach, the sacrificial substrate in the form of a sacrificial ring  206  or a sacrificial disc  207  proves useful, for example, for 300-mm diameter wafers and even larger diameter wafers  230 .  
     [0029]FIG. 4 illustrates a method of manufacturing a sacrificial ring  206 . The substrate for the sacrificial ring  206  may be made of nearly any durable material. According to embodiments of the present invention, two materials may be used: silicon and ceramic. Silicon is the most commonly used semiconductor, and may be used in either its single crystal or polycrystalline form.  
     [0030] The fabrication of integrated circuit devices begins by producing semiconductor wafers cut from a boule of single crystal silicon that is formed by pulling a seed from a silicon melt rotating in a crucible. The boule is then sliced into individual wafers using a diamond-cutting blade. Polycrystalline silicon is often referred to as polysilicon or “poly”.  
     [0031] In path A, the substrate is illustratively silicon and the silicon boule  410  is produced through standard industry practices with Czochralski bulk growth. The wafers  420  are sliced again through standard practices with wire saw technology. The center of the wafers  420  may be cut out with a precision laser cutting tool  430  such that the inner diameter of the sacrificial ring  206  matches the diameter of the wafer  230  to be polished (150 mm, 200 mm, 300 mm wafers, etc.) to produce a silicon ring  460 . The diameter of the boule  410  is generally greater than that of the wafer  230  to be polished, but within the range of manufacturability. The cost is lower since the boule  410  does not have to be monocrystalline. The sacrificial disc  207  may be manufactured in a similar manner, wherein the diameter of the recessed pocket matches the diameter of the wafer  230  to be polished, and the depth of the recessed pocket of the sacrificial disc  207  matches the thickness of the wafer  230  to be polished.  
     [0032] In path B, the sacrificial ring  206  substrate may also be manufactured out of ceramics. A paste  440  is formed and filled into a mold or die. The material is then fired in an oven  450  through industry standard practices to produce ceramic rings  465 . The sacrificial disc  207  may be manufactured in a similar manner.  
     [0033] Finally, the silicon ring  460  or ceramic ring  465  is deposited with the same material  405  that the polishing process intends to remove from the wafer  230  to be polished so as to maintain consistent polishing performance characteristics. The material  405  may be, for example, a thin film deposited by a vacuum deposition. The total thickness of the sacrificial ring  206  matches the total thickness of the wafer  230  to be polished (within ±10 μm) to preserve polishing planarity. The sacrificial disc  207  may be manufactured in a similar manner, wherein the depth of the recessed pocket of the sacrificial disc  207  matches the total thickness of the wafer  230  to be polished (within ±10 μm).  
     [0034]FIG. 5 a - d  illustrates a method of manufacturing an integrated circuit. A semiconductor device  405  is formed on a wafer to be polished  230  with a first dielectric layer  410  formed over the surface of the wafer to be polished  230 . A first opening  415  is formed in the first dielectric layer  410 , where the first opening  415  exposes the semiconductor device  405 . A conductive material  420  is deposited over the first dielectric layer  410  filling the first opening  415 . A sacrificial substrate  206 ,  207  (see FIGS. 2 a  &amp;  2   b ) is selected with a conductive material deposited on a polishing surface that is same as the conductive material  420  deposited over the first dielectric layer  410  filling the first opening  415  on the wafer to be polished  230 .  
     [0035] Referring to FIGS. 2 a  and  2   b , the wafer to be polished  230  is mounted in the sacrificial substrate  206 ,  207 , the sacrificial substrate  206 ,  207  and the wafer to be polished  230  are mounted into the retaining ring  240 ,  241  contained within the polishing head  205 ,  208 . The polishing head  205 ,  208  containing the wafer to be polished  230 , the sacrificial substrate  206 ,  207 , and the retaining ring  240 ,  241  are positioned on a polishing pad  110  mounted to a rotating platen  120 . A polishing slurry  106  is applied to the rotating polishing pad  110  and the wafer to be polished  230  is polished to remove an amount of the conductive material  420  deposited on the wafer to be polished  230  to expose the first dielectric layer  410  and provide a planar polished surface of the conductive material  420  (see FIGS. 5 c  &amp;  5   d ). A measurement may be made to determine the amount of the conductive material  420  that is removed from the wafer to be polished  230 . The measurement may include determining a flatness of the wafer to be polished (see FIG. 3).  
     [0036] A sacrificial substrate, in the form of a sacrificial ring  206  or a sacrificial disc  207 , allows the wafer  230  to sit flush inside the sacrificial ring  206  or sacrificial disc  207  and allows the sacrificial ring  206  or sacrificial disc  207  to act as the sacrificial extension of the wafer  230  to be polished. Therefore, the sacrificial ring  206  or sacrificial disc  207  experiences the edge roll-off effect instead of the wafer  230  to be polished. As a result, the wafer  230  to be polished has an improved flatness and film thickness uniformity by shifting the edge roll-off effects beyond the edge of the wafer  230  to be polished outwards to the sacrificial ring  206  or sacrificial disc  207 .  
     [0037] While the description above refers to particular embodiments of the present invention, it will be understood that many modifications may be made without departing from the spirit thereof. The accompanying claims are intended to cover such modifications as would fall within the true scope and spirit of the present invention. The presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims, rather than the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.