Patent Publication Number: US-7908100-B2

Title: Power consumption analyzing apparatus and power consumption analyzing method

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is based upon claims the benefit of priority from the prior Japanese Patent Application No. 2007-162510, filed on Jun. 20, 2007, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a power consumption analyzing apparatus and a power consumption analyzing method that analyze a power consumption of a semiconductor integrated circuit on a design stage. 
     2. Related Art 
     When designing a digital circuit composed of a flip-flop and a combinational logic circuit, it is general to use an RTL (Register Transfer Level) to describe the circuit. The circuit described by the RTL is converted into a gate-level netlist including connection information of the circuits by using logic synthesis. The netlist is laid out on a semiconductor substrate. 
     The netlist generated by the logic synthesis of the RTL description is not necessarily one type, and a plurality of types of net lists can be generated from the same RTL description. Although the netlist includes various kinds of circuits such as a flip-flop or a clock gating cell, a power consumption of the flip-flop is considerably larger than those of other cells, and hence the power consumption of the flip-flop must be accurately estimated. 
     The power consumption of the flip-flop is calculated from toggle rates and duty ratios of a data input signal, a clock signal, and a data output signal. Among others, toggle rates of the clock signal and the data output signal have a great influence on the power consumption. Therefore, to accurately estimate the power consumption of the flip-flop, the toggle rates of the clock signal and the data output signal must be accurately obtained. 
     The flip-flop (a register) included in RTL data written by using the RTL description is also present in the netlist. The toggle rate and the duty ratio of the data output signal of the flip-flop included in both of the RTL data and net list can obtain the same results, even if an operational simulation is executed based on either of the RTL data or the netlist. 
     On the other hand, the power consumption varies depending on whether the clock signal from the flip-flop has passed through the clock gating cell before being input to the flip-flop. Even if the clock gating cell is present in the netlist, there is a possibility that it is not present in the RTL data. In such a case, an operation of the clock gating cell cannot be verified even if the RTL is used to perform the operational simulation. 
     Under the circumstances, there is a problem that the power consumption of the clock-gated flip-flop cannot be accurately estimated even though an RTL simulation is performed. This problem may possibly occur in not only the flip-flop but also in all cells to which the clock signal is input. 
     There has been proposed a technology of analyzing a power consumption based on a result of executing an operational simulation using RTL data obtained by associating the RTL data with a gate-level netlist (see Japanese Patent Application Laid-open Publication No. 2006-190149). 
     However, in the above publication, the operational simulation is executed while ignoring a clock gating cell that is not present in RTL data but present in a gate-level netlist. Therefore, according to the technique of the above publication, it is difficult to accurately analyze power consumption. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, a power consumption analyzing apparatus comprising: 
     a clock gating cell detector configured to detect a clock gating cell which is not present in RTL data but present in a gate-level netlist based on the RTL data of a target circuit and the netlist corresponding to the RTL data; 
     a test bench description generation unit configured to add a description concerning the clock gating cell detected by the clock gating cell detector to the RTL data; 
     a monitor signal generation unit configured to specify a monitor signal used for power consumption analysis from the RTL data obtained by adding the description concerning the clock gating cell; 
     an RTL simulation unit configured to execute operational simulation of the target circuit by using the RTL data obtained by adding the description concerning the clock gating cell; 
     a monitor unit configured to detect a logic of the monitor signal during the execution of the operational simulation; and 
     a power consumption analysis unit configured to analyze power consumption due to a toggle at a clock terminal of the clock synchronizing cell included in the target circuit. 
     According to one aspect of the present invention, a power consumption analyzing method comprising: 
     detecting a clock gating cell which is not present in RTL data but present in a gate-level netlist based on the RTL data of a target circuit and the netlist corresponding to the RTL data; 
     adding a description concerning the detected clock gating cell to the RTL data; 
     specifying a monitor signal used for power consumption analysis from the RTL data obtained by adding the description concerning the clock gating cell; 
     executing operational simulation of the target circuit by using the RTL data obtained by adding the description concerning the clock gating cell; 
     detecting a logic of the monitor signal during the execution of the operational simulation; and 
     analyzing power consumption due to a toggle at a clock terminal of the clock synchronizing cell included in the target circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing an outline structure of a power consumption analyzing apparatus according to an embodiment of the present invention; 
         FIG. 2  is a flowchart showing an example of a processing operation of the power consumption analyzing apparatus according to the embodiment; 
         FIG. 3  is a view showing an example of RTL data; 
         FIG. 4  is a circuit diagram showing an example of a circuit generated by using the RTL data depicted in  FIG. 3 ; 
         FIG. 5  is a circuit diagram showing an example of another circuit generated by using the RTL data depicted in  FIG. 3 ; 
         FIG. 6  is a circuit diagram showing an example of an internal structure of a clock gating cell ICG; 
         FIG. 7  is a view showing an example of a test bench description; and 
         FIG. 8  is a view showing an example of a mapping file. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     An embodiment according to the present invention will now be explained hereinafter with reference to the drawings. 
       FIG. 1  is a block diagram showing an outline configuration of a power consumption analyzing apparatus according to an embodiment of the present invention. The power consumption analyzing apparatus depicted in  FIG. 1  includes an RTL supply unit  1 , an RTL analysis unit  2 , a gate-level netlist generation unit  3 , an RTL/net list comparison unit (clock gating cell detector)  4 , a formal verification information supply unit  5 , a mapping file generation unit  6 , a monitor signal generation unit  7 , a test bench description generation unit  8 , a test data supply unit  9 , an RTL simulation unit  10 , a monitor unit  11 , and a power consumption analysis unit  12 . 
     Libraries  13  to  16  are connected with the power consumption analyzing apparatus depicted in  FIG. 1 . These libraries  13  to  16  may be integrated as one or more unit, or they may be incorporated in the power consumption analyzing apparatus. 
     The RTL supply unit  1  supplies RTL data written by an operator to the RTL analysis unit  2 , the netlist generation unit  3 , and the RTL/net list comparison unit  4 . The RTL analysis unit  2  makes reference to the library  13  to detect clock synchronizing cells such as a flip-flop or a clock buffer included in the RTL data and clock gating cells on a clock transmission paths for these clock synchronizing cells. 
     The netlist generation unit  3  makes reference to the library  14  to generate a gate-level netlist based on the RTL data. The RTL/net list comparison unit  4  makes reference to formal verification information of the RTL data supplied from the formal verification information supply unit  5  to compare the RTL data with the netlist, acquires correspondence information of respective nodes included in the RTL data and the netlist, and specifies a signal that should be monitored (which will be referred to as a monitor signal hereinafter). Based on the correspondence information, the RTL/net list comparison unit  4  detects the clock gating cell which is not present in the RTL data but present in the netlist. The monitor signal generation unit  7  determines a monitor signal to be monitored in the RTL data based on a result compared by the RTL/net list comparison unit  4 . The monitor signal is set to a node that greatly affects a power consumption. More specifically, a clock signal that is input to each clock synchronizing cell such as a flip-flop or a clock buffer, or an input/output signal of each clock gating cell that is inserted in the clock transmission path is set as the monitor signal. 
     The test bench description generation unit  8  adds a description concerning the clock gating cell detected by the RTL/net list comparison unit  4  to the RTL data. 
     The test data supply unit  9  supplies test data used to analyze a power consumption. The RTL simulation unit  10  makes reference to the library  15  to supply the test data as input data, and executes an operational simulation based on the RTL data. The monitor unit  11  detects a logic of the monitor signal during execution of the simulation by the RTL simulation unit  10 . 
     The power consumption analysis unit  12  makes reference to a detection result from the monitor unit  11  and the library  16  to analyze power consumptions of the flip-flop, the clock buffer, the clock gating cell, and others. 
       FIG. 2  is a flowchart showing an example of a processing operation of the power consumption analyzing apparatus according to this embodiment. The processing operation of the power consumption analyzing apparatus will now be explained hereinafter based on this flowchart. 
     First, the RTL analysis unit  2  analyzes RTL data of a target circuit based on the RTL data supplied from the RTL supply unit  1  (a step S 1 ). 
       FIG. 3  is a view showing an example of the RTL data. In  FIG. 3 , a circuit module MOD 1  is defined (a first line in  FIG. 3 ). This circuit module has four input signals DAT, CLK, en 1  and en 2 , and one output signal R 1  (second and third lines). In a fourth line in  FIG. 3 , a register R 1  is defined, and an operation of the register R 1  is written in fifth and subsequent lines. 
     The fifth line shows that the operation is performed at a rising edge of the clock signal CLK. A sixth line shows that the data input signal DAT is latched to output the data output signal R 1  when both the enable signals en 1  and en 2  are enabled. 
     At the step S 1 , the RTL analysis unit  2  detects each clock synchronizing cell such as a flip-flop or a clock buffer (which will be generically referred to as a flip-flop hereinafter) and also detects a clock transmission path for the clock signal that is input to the clock synchronizing cell. 
     Then, the RTL/net list comparison unit  4  compares the RTL data with a gate-level netlist generated based on this RTL data by the netlist generation unit  3 , and associates the flip-flop in the RTL data with the clock synchronizing cell in the netlist (a step S 2 ). 
     Subsequently, the monitor signal generation unit  7  determines a monitor signal that should be monitored in the RTL data based on a comparison result obtained by the RTL/net list comparison unit  4  (a step S 3 ). Here, a clock terminal of the clock synchronizing cell such as a flip-flop or a clock buffer or a node on the clock transmission path connected with the clock terminal is determined as the monitor signal. 
     Then, the test bench description generation unit  8  adds a description concerning a clock gating cell that is present in the netlist but not present in the RTL data (which will be referred to as a test bench description hereinafter) to the RTL data (a step S 4 ). 
       FIGS. 4 and 5  are circuit diagrams each showing an example of a circuit generated by using the RTL data depicted in  FIG. 3 . As can be understood from  FIGS. 4 and 5 , even if the same RTL data is used, the number of a circuit expression method is not necessarily one. Therefore, the netlist generated by the netlist generation unit  3  based on the RTL data depicted in  FIG. 3  may become like a circuit depicted in  FIG. 4  or may become like a circuit shown in  FIG. 5 , or it may possibly become any other circuit. 
     The circuit depicted in  FIG. 4  has an AND gate  21  that calculates a logical product of the enable signals en 1  and en 2 , a buffer  22  that changes over whether the input data DAT should be transmitted therethrough based on a logic of the AND gate  21 , and a flip-flop FF that fetches an output signal from the buffer in synchronization with the clock CLK. 
     On the other hand, the circuit shown in  FIG. 5  has the same AND gate  21  as that in  FIG. 4 , a clock gating cell ICG that latches an output signal from the AND gate  21  in synchronization with the clock CLK, and a flip-flop FF that changes over a logic in synchronization with an output signal from the clock gating cell ICG. The clock gating cell ICG in  FIG. 5  is a clock gating cell automatically generated by the netlist generation unit  3 . 
       FIG. 6  is a circuit diagram showing an example of an internal structure of the clock gating cell ICG. The clock gating cell ICG in  FIG. 6  has a latch  23  and an AND gate  24 . The latch  23  latches an enable signal EN when the clock CLK has a logic 1, and allows the enable signal to be transmitted therethrough when the clock CLK has a logic 0. The AND gate  24  calculates a logical product of the clock CLK and an output from the latch  23 . As a result, the AND gate  24  allows the clock CLK to be transmitted therethrough only when the enable signal EN has the logic 1. 
     It is to be noted that the circuit depicted in  FIG. 6  is just an example, and the clock gating cell ICG may be formed of a circuit other than that depicted in  FIG. 6 . 
     It is assumed that a gate-level netlist of the circuit shown in  FIG. 5  is generated by using the RTL data depicted in  FIG. 3 , for example. Since the RTL data in  FIG. 3  does not have a description concerning the clock gating cell ICG in the circuit depicted in  FIG. 5 , even if the RTL data in  FIG. 3  alone is used to execute an RTL simulation, a power consumption of the clock gating cell ICG itself or an output signal from the clock gating cell ICG, i.e., a toggle rate or a duty ratio of a clock signal of the FF cannot be analyzed. 
     Thus, at the step S 4 , the test bench description generation unit  8  adds a description of the clock gating cell ICG to the RTL data. This is called a test bench description. It is possible to set an input or output signal of the clock gating cell added by the step S 4  as the monitor signal. 
       FIG. 7  is a view showing an example of the test bench description. In a first line in  FIG. 7 , a circuit module Testbench is defined. In a fourth line, the circuit module MOD 1  in  FIG. 3  is called to be instantized. A correspondence relationship between an input/output signal in the RTL data and an input/output signal of the circuit depicted in  FIG. 5  is represented in parentheses following INST 1  in the fourth line. 
     Further, a part following “always” in a ninth line in  FIG. 7  is a description of the clock gating cell ICG that is the clock gating cell depicted in  FIG. 5 . 
     Based on such a test bench description as shown in  FIG. 7 , the clock gating cell that is not present in the original RTL data can be added to the RTL data. 
     Then, the mapping file generation unit  6  generates a mapping file indicative of a correspondence relationship between signal names in the RTL data and signal names in the netlist (a step S 5 ).  FIG. 8  is a view showing an example of the mapping file. In  FIG. 8 , a correspondence relationship of input signals that should be monitored (clocks GCLK and enable signals EN). 
     Subsequently, the RTL simulation unit  10  executes an RTL simulation based on the test bench description in  FIG. 7  (a step S 6 ). At the time of the RTL simulation, test data supplied from the test data supply unit  9  is determined as an input signal to execute the RTL simulation. As a result, an operational simulation can be executed in a state where the description concerning the clock gating cell is added to the RTL data. 
     The monitor unit  11  detects a logic of the monitor signal determined at the step S 3  during execution of the RTL simulation (a step S 7 ). The clock synchronizing cell such as a flip-flop or a clock buffer exerts a large influence on a power consumption of the circuit. Thus, an input/output signal of the clock synchronizing cell is determined as a monitor signal to detect its logic. 
     Then, the power consumption analysis unit  12  detects not only a toggle rate or a duty ratio of the clock terminal such as a flip-flop or a clock buffer but also a toggle rate or a duty ratio of an input/output signal of the clock gating cell added in the test bench description based on a result detected at the step S 7 , and analyzes power consumptions of various clock synchronizing cells such as a flip-flop or a clock buffer (a step S 8 ). 
     As explained above, according to this embodiment, the RTL data is compared with the netlist, the description concerning the clock gating cell that is not present in the RTL data but present in the netlist is added to the RTL data, the RTL simulation is executed based on the RTL data after addition, and toggle rates or duty ratios of input/output signals of the various clock gating cells are detected to analyze power consumptions of the various clock gating cells, thereby simply and accurately analyzing a power consumption of the circuit including the clock gating cells. 
     In particular, according to this embodiment, since the power consumption can be accurately analyzed without executing the simulation using the netlist that requires an enormous time for a simulation, a time required for analysis of the power consumption can be greatly reduced. 
     In the foregoing embodiment, the description has been given as to the example where the toggle rate or the duty ratio of the clock terminal of each clock synchronizing cell, e.g., the flip-flop, the clock buffer, or the clock gating cell is monitored to analyze the power consumption, but a toggle rate or a duty rate of an enable signal of the clock synchronizing cell may be monitored. Furthermore, It is unnecessary to detect both of the toggle rate and the duty ratio. Advantageous effect of the present embodiment can be obtained by either of the toggle rate or the duty ratio. 
     Moreover, a state probability or a transition probability of the clock terminal of each clock synchronizing cell may be monitored to analyze the power consumption.