Patent Publication Number: US-5831168-A

Title: Ultrasound signal processor

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation-in-part of copending U.S. patent application Ser. No. 08/572,877 filed on Dec. 18, 1995 , now abandoned, under title of&#34;ULTRASOUND SIGNAL PROCESSOR&#34; which is a divisional application of U.S. patent application Ser. No. 08/124,555 filed on Sep. 22, 1993 issued as U.S. Pat. No. 5,515,727, the disclosure of which are hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to signal processing either in an apparatus for performing non-destructive testing of a material object or in an ultrasound apparatus used for medical diagnosis and more particularly to an ultrasound signal processor suitable for digitization. 
     A conventional ultrasound receiver is comprised of analog delay circuits and adders and it radiates ultrasound to an object to be tested, then receives an echo from the object to be tested by means of a receiving element array and adjusts the delay time between receiving signals to change the direction of a receiving beam. The incident direction of the ultrasound is made to be coincident with the direction of formation of the receiving beam, and outputs of respective array receiving elements are made to be in phase and added together to thereby obtain a total output which is large. 
     The conventional ultrasound receiver is shown in FIG. 33. Echoes from an object to be tested are received by an array of transducers 23, respective received signals are fed to received signal processing units 44 so that a delay time difference between the received signals generated from the respective transducers may be adjusted, and output signals of the received signal processing units are added together by a digital adder 3. In this manner, a received beam 43 can be formed by a received beam forming unit 41. The received beam is electrically scanned to produce a tomogram of the object to be tested. 
     In order to form an optimal received beam in the course of the received beam formation, the accuracy of delay by the received signal processing unit 44 must be increased, and, to this end, various attempts have been made to eliminate disadvantages of an analog circuit (irregularities due to parts, temperature drift, saturation and the like) by changing the analog circuit to a digital circuit. However, when simple digitization of the circuit form is effected in, for example, an ultrasonic diagnostic system using ultrasound of a frequency of about 1MHz to 20MHz, high-speed ADC&#39;s (analog to digital converters) of 100MHz or more are needed. But the digitization is desired to be realized with low-speed ADC&#39;s and a method for this purpose has been proposed. 
     As an example, the present applicant has proposed an apparatus in JP-A-6-313764 &#34;Ultrasound Signal Processor&#34;. In this apparatus, each received signal is digitized, a digitized received signal is multiplied by two reference signals each having a center frequency of the received signal and being 90° out of phase from each other so that the received signal may be converted into a complex signal and a low frequency component of the complex signal may be taken out, and low frequency components corresponding to signals generated from adjacent ones of the elements (transducers) are compensated for a phase difference therebetween by phase rotation and are then subjected to time delay. 
     JP-A-4-223289 (Japanese Patent Application corresponding to U.S. Pat. No. 4,983,970) discloses a method in which each received signal is digitized, the digitized received signal is multiplied by two reference signals each having a center frequency of the received signal and being 90° out of phase from each other so that the received signal may be converted into a complex signal and a low frequency component of the complex signal may be taken out, and low frequency components corresponding to signals generated from adjacent ones of the elements are delayed in time difference therebetween by time delay and are subjected to phase rotation. 
     Japanese Patent Application JP-A-2-4355 corresponding to U.S. Pat. No. 4,886,069) discloses a method for formation of a so-called received multibeam in which received signals are digitized by a plurality of ADC&#39;s arranged in parallel, the digitized signals are converted into low frequency signals by means of mixers, and the low frequency signals are applied with different phases by means of a plurality of phase rotation circuits arranged in parallel, respectively, to simultaneously form received beams in different directions. To explain the formation of received multibeam, a transmitted beam 42 is formed in a certain direction and a received multibeam is formed including received beams 43a and 43b which are formed simultaneously in different directions a and b, as shown in FIG. 34. The number of received beams of a received multibeam is not limited to two. 
     Receiving signals from an object other than the target, which are received by the respective array receiving elements, are out of phase from each other and consequently cancelled out to thereby produce a total output which is suppressed. Since signals received by a plurality of receiving elements are made to be in phase and added together in this manner to improve resolution, accuracy of the delay time of analog delay circuits must be increased, giving rise to problems of including a complicated apparatus configuration and high cost. Accordingly, an apparatus has been proposed which simplifies the apparatus configuration and which is mainly constructed of analog circuits which are not required to have high delay time accuracy. This type of apparatus is based on ultrasound beamforming or so-called beat-down in which the center frequency of a receiving signal is shifted and delayed and thereafter subjected to adding processing. More specifically, in the beamformer of ultrasound signals, a signal from an ultrasound receiving element is mixed with a reference signal, precisely controlled with respect to time, so as to be converted into a low frequency signal, wherein the low frequency signal component is delayed by means of a delay circuit. Signals from the respective elements which are thus produced are finally added together. A configuration using this method is shown in FIG. 2. 
     In FIG. 2, reference numeral 23 designates a transducer of ultrasound, 14 denotes an analog mixer, 6 indicates an analog delay circuit whose delay time is settable, 2 represents an analog adder, 18 designates an analog reference signal generator, and 8 de notes a control circuit for analog delay. Where t represents time, a transmitting signal s(t) having a center frequency ω s  can be approximated by 
     
         S(t)=A.sub.o (t){exp(jω.sub.s t)+exp(-jω.sub.s t)}(1 ) 
    
     wherein A o  (t) indicates an envelope form of the transmitting signal and j is an imaginary unit. A receiving signal f n  (t) of a targeted echo signal generated from this transmitting signal and received by an n-th array receiving element is given by ##EQU1## where τ n  is propagation time of the ultrasound. Here A n  =k n  A o  and k n  is a coefficient determined by a propagation distance of the echo. Multiplication of this signal by a reference signal h n  (t) generated from the analog reference signal generator 18 is carried out by the analog mixer 14. For simplification, it is now assumed that h n  (t) is a signal having the same frequency as a carrier of the receiving signal, and h n  (t) is given by 
     
         h.sub.n (t)=exp{-j(ω.sub.s t-φ.sub.n)}           (3) 
    
     when a phase term φ n  is taken into consideration. A multiplication result g n  (t) is ##EQU2## When only a carrier component which is direct current is considered, the multiplication result is expressed by G n  (t) which is 
     
         G.sub.n (t)=A.sub.n (t-τ.sub.n)                        (5). 
    
     This waveform is delayed by a time of τ o  -τ n  by means of the analog delay circuit 6 to provide a signal V n  (t) which is ##EQU3## where τ o  is a constant determined by the analog delay circuit 6. As will be seen from the above formula, signal V n  (t) results from time shift of A n  (t), and A n  (t) is constant times as large as the envelope A o  of the transmitting signal. Therefore the signal V n  (t) has a common waveform whose amplitude scale depends on n. Consequently, in a final result which is obtained by adding thus processed signals by means of the analog adder 2 and which is expressed by ##EQU4## respective signals are in phase with each other and the sum Y(t) grows greatly. On the other hand, in an echo coming from a direction other than the targeted direction, respective signals have phases which are different from φn in equation (3) and a phase term remains in equation (5). This causes interference due to the phase difference occurring during addition pursuant to equation (7), and thus the sum Y(t) damps. Based on the operational principle described above, receiving signals from the targeted direction can be selected. For example, Japanese Patent Publication No. 51068/1985 and U.S. Pat. No. 4,140,022 are relevant to this type of apparatus. The configuration shown in FIG. 2 is typically realized with analog circuits but in order to improve accuracy of beamforming and further enhance the quality of the apparatus, it may preferably be realized with digitized operation units. 
     Conceivably, the conventional apparatus constructed of analog circuits may be simply digitized with, for example, an apparatus constructed as shown in FIG. 3. In FIG. 3, an analog to digital converter 5 is used and the analog mixer 14, analog delay circuit 6, analog adder 2, analog reference signal generator 18 and control circuit 8 for analog delay shown in FIG. 2 are modified for digitization to provide a digital mixer 15, a digital delay circuit 7, a digital adder 3, a digital reference signal generator 19 and a control circuit 9 for digital delay, respectively, which are used in FIG. 3. In this configuration, the analog to digital (A/D) converter is required to have many bits, for example 10 bits or more, to ensure amplitude accuracy for ordinary ultrasound applications. Under the circumstances, a configuration is conceivable wherein a so-called over-sampling technique using known fast sampling and cumulation of signals in combination is applied to increase the effective number of bits. For example, in FIG. 4, a digital adder 4 for cumulation adapted to calculate the sum of a plurality of signals is arranged between the analog to digital converter 5 and digital mixer 15 shown in FIG. 3. The effect of this over-sampling technique depends on the number of cumulating operations but the ultrasound signal has a waveform as shown in FIG. 5, with the result that the time length for permitting cumulation within an amplitude change of Δ or less is limited to T o  or less and a remarkable improvement in accuracy cannot be expected. In FIG. 5, A(t) represents an envelope having the same form as that of the envelope of the transmitting signal s(t) and this waveform is a typical example in the conventional ultrasonic apparatus. 
     In the prior art described above, when materializing a highly accurate digital beamforming processing, a problem arose in simplifying the analog to digital converter. Further, it was difficult to improve both the amplitude accuracy and the sampling frequency of the analog to digital converter in compliance with a receiving signal having a high center frequency. Further, there arose problems in dealing with a sampling frequency of the analog to digital converter that is not sufficiently higher than nearly twice the upper limit frequency of a receiving signal component. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to solve the above problems and to provide an ultrasound signal processor which can remarkably improve the accuracy of analog to digital conversion, especially for a receiving signal having a high center frequency, and can be simplified in configuration so as to be suited for cost reduction. 
     To accomplish the above object, a signal processor of the present invention comprises a circuit for digitizing a receiving signal, a circuit for mixing a resulting digital signal with a reference signal of a predetermined frequency to convert it into a low frequency signal, and a circuit for performing a cumulation processing of converted signals in series, whereby the cumulation processing is carried out after the frequency of the receiving signal is shifted to a lower frequency. 
     An ultrasound signal processor of the present invention comprises a digitizing circuit for digitizing a receiving signal, a waveform conversion circuit for converting a signal waveform by multiplying a resulting digital signal by a reference signal of a predetermined frequency, a cumulation circuit for performing a cumulation processing of converted signals in series, a delay circuit for delaying a signal subjected to the cumulation processing, and an adder circuit for adding delayed signals, whereby the cumulation processing is carried out after the frequency of the receiving signal is shifted to a lower frequency by utilizing characteristics of ultrasound signals. A plurality of groups of the waveform conversion circuits may be provided or a circuit for storing signals subjected to the cumulation processing may be provided. 
     To accomplish the above object, the ultrasound signal processor of the present invention further comprises a circuit for converting a receiving signal into a low frequency signal by analog-mixing the receiving signal with an analog reference signal of a predetermined frequency, and a filter circuit for passing a low frequency component of an analog-converted signal, whereby the frequency of the receiving signal is first shifted to a lower frequency through the analog signal processing, a resulting low frequency signal is digitized, the frequency of the resulting digital signals is then shifted further to a lower frequency through digital signal processing and thereafter resulting low frequency signals are subjected to a cumulation processing. An envelope of a transmitting signal can be reconstructed by limiting the number of cumulation operations during the cumulation processing of the digital converted signals and the frequency of the reference signal used during the analog waveform conversion. 
     In the present invention, the over-sampling technique is used for the digital processing of ultrasound signals and the cumulation processing is carried out after the frequency is shifted to a lower frequency in order that, even with a simplified configuration, the effective accuracy of analog to digital conversion can be improved greatly. Especially, by using the over-sampling technique in which an ultrasound signal having a high center frequency is shifted to a lower frequency through an analog signal processing, the frequency is further shifted to a lower frequency through a digital signal processing and thereafter a cumulation processing is carried out, the effective accuracy of analog to digital conversion can be improved greatly with a simplified configuration even for the ultrasound signal having a high center frequency. 
     In accordance with the present invention, by performing a cumulation processing after an ultrasound signal is shifted to a lower frequency, the over-sampling processing can act effectively to drastically improve the effective accuracy of analog to digital conversion. Through this, the configuration of the analog to digital converter in a digital type ultrasound apparatus operable at a high center frequency can be simplified, thus contributing to cost reduction. Especially, by shifting an ultrasound signal having a high center frequency to a lower frequency, digitizing a resulting low frequency signal, further shifting a resulting digital signal to a lower frequency through a digital processing, and cumulating low frequency signals, the over-sampling processing can act effectively to drastically improve the accuracy of analog to digital conversion. 
     Further, in order to form a received multibeam in the prior art, a plurality of received beam forming units 41 must be arranged in parallel as shown in FIG. 34. Depending on the type, a plurality of delay circuits are needed which follow a received signal processing unit. 
     Accordingly, the prior art need a plurality of circuits of received beam forming units for formation of a received multibeam, raising a problem that the circuit scale increases. 
     Another object of the present invention is to solve the above problems encountered in the prior art and provide ultrasound signal processing method and processor of the digital type suitable for formation of a received multibeam. 
     Still another object of the present invention is to provide an ultrasound signal processing method and processor of the digital type which can form a received multibeam without using a plurality of signal processing circuits, that is, received beam forming unit circuits for processing received signals received at transducers (elements) so as to decrease the circuit scale. 
     An ultrasound signal processor according to the present invention comprises an array of transducers for receiving echo signals, a digitizing circuit for setting a period of sampling in accordance with a sampling clock of a frequency which is sufficiently higher than a Nyquist sampling frequency of an upper limit frequency of a frequency band width for each of the received signals received at the transducers and sampling and digitizing each received signal, first waveform conversion units connected to each digitizing circuit in one to one relation and operative to multiply digital received signals obtained at the digitizing circuits by a reference signal of a predetermined frequency to convert the digital received signals into complex signals and shift the frequency of the digital received signals, cumulation circuits connected to each first waveform conversion unit in one to one relation and operative to cumulate received signals converted by the first waveform conversion unit for a time which is sufficiently longer than the sampling period so as to produce cumulated signals, multi-direction delay units connected to the cumulation circuits in one to one relation and operative to process the cumulated signals at a clock frequency which is lower than the sampling clock in connection with an ultrasound beam in one direction so as to form received ultrasound beams in a plurality of directions through a time sharing process, and a digital adder for adding output signals of the respective multi-direction delay units, whereby a processing is carried out in which after one transmission operation of ultrasound, a plurality of ultrasound received beams are formed from the received signal generated from each of the transducers. 
     The aforementioned ultrasound signal processor further comprises a control unit for a received beam former having a unit for detecting a phase error between output signals of multi-direction delay units corresponding to adjacent ones of the transducers in one to one relation and being operative to control each multi-direction delay unit so as to form a received ultrasound beam which makes the phase error substantially zero. 
     An ultrasound signal processor according to the present invention comprises an array of transducers for receiving echo signals, a digitizing circuit for setting a period of sampling in accordance with a sampling clock of a frequency which is sufficiently higher than a Nyquist sampling frequency of an upper limit frequency of a frequency band width for each of the received signals received at the transducers and sampling and digitizing the received signal, first waveform conversion units connected to each digitizing circuit in one to one relation and operative to multiply a digital received signal obtained at the digitizing circuit by two reference signals of a predetermined frequency which are 90° out of phase from each other to convert the digital received signal into a complex signal and shift the frequency of the digital received signal, digital cumulation circuits connected to each first waveform conversion unit in one to one relation and operative to cumulate received signals converted by the first waveform conversion units for a time which is sufficiently longer than the sampling period so as to produce a cumulated signal, a temporary memory connected to the cumulation circuit in one to one relation to temporarily store the cumulated signal, a control unit for temporary memory adapted to control delivery of the cumulated signal from the temporary memory, second waveform conversion units connected to the temporary memory in one to one relation and operative to apply phase rotation to the cumulated signal delivered out of the temporary memory, digital delay circuits connected to the second waveform conversion units in one to one relation and operative to apply a delay time to the output signals of the second waveform conversion units so as to compensate a propagation time difference of ultrasound due to a difference in distance between a target focus position and each of the transducers, a digital adder for adding output signals of the respective digital delay circuits, and a unit for converting an output signal of the digital adder into an envelope signal, whereby in order to form received ultrasound beams in a plurality of different directions in correspondence to one transmission operation of ultrasound, the temporary memory control unit controls the cumulated signal delivered out of the temporary memory to form the received ultrasound beams through a time sharing process, thereby forming ultrasound beams in the plurality of directions. 
     The aforementioned ultrasound signal processor further comprises a control unit for a received beam former having a unit for detecting a phase difference between output signals of digital delay circuits corresponding to adjacent ones of the transducers in one to one relation and being operative to control each temporary memory, each second waveform conversion unit and each digital delay circuit so as to form a received ultrasound beam which makes the phase error substantially zero. 
     Further, an ultrasound signal processor according to the present invention comprises an array of transducers for receiving echo signals, a digitizing circuit for setting a period of sampling in accordance with a sampling clock of a frequency which is sufficiently higher than a Nyquist sampling frequency of an upper limit frequency of a frequency band width for each of the received signals received at the transducers and sampling and digitizing each received signal, first waveform conversion units connected to each digitizing circuit in one to one relation and operative to multiply a digital received signal obtained at the digitizing circuit by two reference signals of a predetermined frequency which are 90° out of phase from each other to convert the digital received signal into a complex signal and shift the frequency of the digital received signal, a cumulation circuit connected to each first waveform conversion unit in one to one relation and operative to cumulate received signals converted by the first waveform conversion units for a time which is sufficiently longer than the sampling period so as to produce a cumulated signal, a digital delay circuit connected to each cumulation circuit in one to one relation and operative, for the purpose of forming received ultrasound beams in a plurality of different directions in correspondence to one transmission operation of ultrasound, to compensate a propagation time difference of ultrasound due to a difference in distance between a target focus position and each of the transducers and apply to the cumulated signal a delay time for forming the received ultrasound beams in the plurality of different directions through a time sharing process, second waveform conversion units connected to each digital delay circuit in one to one relation and operative to apply phase rotation to an output signal of each digital delay circuit, a digital adder for adding output signals of the respective second waveform conversion units, and a unit for converting an output signal of the digital adder into an envelope signal, whereby a processing is carried out in which after one transmission operation of ultrasound, the plurality of ultrasound received beams are formed from the received signal received at each of the transducers. 
     The aforementioned ultrasound signal processor further comprises a unit for shading the amplitude of the output signal of the second waveform conversion unit, and a control unit for a received beam former having a unit for detecting a phase error between output signals of digital delay circuits corresponding to adjacent ones of the transducers in one to one relation and operative to control each second waveform conversion unit and each digital delay circuit so as to form a received ultrasound beam which makes the phase error difference substantially zero. 
     An example of &#34;setting a period of sampling in accordance with a sampling clock of a frequency which is sufficiently higher than a Nyquist sampling frequency of an upper limit frequency of a frequency band width for each of the received signals&#34; will be described below. For example, given that the center frequency of ultrasound is 5 MHz and the upper limit of the frequency band width is 7.5 MHz, the sampling clock of the sufficiently high frequency has a frequency which is sufficiently higher than a Nyquist sampling frequency of 15 MHz for the 7.5 MHz upper limit of the frequency band width and which is, for example, 25 MHz. 
     An example of &#34;to cumulate received signals for a time which is sufficiently longer than the sampling period&#34; is as follows. In connection with the above example, the aforementioned 25 MHz is equivalent to a sampling period of 40ns and therefore, on the assumption that two or more cumulation (addition) operations are carried out, the cumulation processing is effected for a time sufficiently longer than the sampling period which is here 80ns or more. 
     An example of&#34;to process the cumulated signal at a clock frequency which is lower than the sampling clock in connection with one ultrasound beam&#34; is as follows. When the received signal is processed at intervals of 40ns for forming two ultrasound beams through a time sharing process, the received signal is processed at time intervals of 80ns (corresponding to a frequency of 12.5 MHz) in the processing for formation of one ultrasound beam and the cumulated signal is processed by a clock of a frequency which is half the 25 MHZ. 
     An example of&#34;the baseband signal is lowered to a frequency which is sufficiently lower than a center frequency of the first received signal&#34; is as follows. As an example, given that the center frequency of the received signal is 5 MHz and a signal component of the upper limit of the frequency band width is 7.5 MHz, a 5 MHz component of the received signal is shifted to a lower frequency of 0 MHz and the 7.5 MHz component is shifted to a lower frequency of 2.5 MHz in a baseband signal obtained after mixing is effected using reference signals having a frequency equal to the 5 MHz center frequency, indicating that the baseband signal is lowered to a frequency which is sufficiently lower than the center frequency of the first received signal. 
     Thus, the present invention has an excellent advantage that an ultrasound signal processor of the digital type suitable for formation of a received multibeam, especially, an ultrasound signal processor capable of forming a received multibeam without using a plurality of received beam forming unit circuits can be realized. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a diagram showing a configuration of an ultrasound signal processor according to a first embodiment of the present invention. 
     FIG. 2 is a diagram showing a configuration of a prior art analog type ultrasound signal processor to which the beat-down beamforming is applied. 
     FIG. 3 is a diagram showing a configuration wherein the ultrasound signal processor of FIG. 2 is digitized. 
     FIG. 4 is a diagram showing a configuration wherein the over-sampling technique is applied to the ultrasound receiver of FIG. 3. 
     FIG. 5 is a diagram showing an ultrasound waveform obtained with the prior art ultrasound signal processor. 
     FIG. 6 is a diagram showing an ultrasound waveform obtained with the ultrasound signal processor according to the first embodiment of the present invention. 
     FIG. 7 is a graph for explaining the beat-down of a receiving signal in the present invention. 
     FIG. 8 is a diagram showing a configuration of an ultrasound signal processor according to a second embodiment of the present invention. 
     FIG. 9 is a graph showing how spectra of a receiving signal change due to analog mixing. 
     FIG. 10 is a diagram showing a configuration of an ultrasound signal processor according to a third embodiment of the present invention. 
     FIG. 11 is a diagram showing a configuration for processing of a single channel signal in the third embodiment of the present invention. 
     FIG. 12 is a diagram showing timing of a control signal in the third embodiment of the present invention. 
     FIG. 13 is a diagram showing another configuration for processing of a single channel signal in the third embodiment of the present invention. 
     FIG. 14 is a diagram showing timing of a control signal in the third embodiment of the present invention. 
     FIG. 15 is a diagram showing a configuration of an ultrasound signal processor according to a fourth embodiment of the present invention. 
     FIG. 16 is a diagram showing a configuration for processing of a single channel signal in the fourth embodiment of the present invention. 
     FIG. 17 is a diagram showing another configuration for processing of a single channel signal in the fourth embodiment of the present invention. 
     FIG. 18 is a diagram showing a configuration of an ultrasound signal processor according to a fifth embodiment of the present invention. 
     FIG. 19 is a diagram showing a configuration of an ultrasound signal processor according to a sixth embodiment of the present invention. 
     FIG. 20 is a diagram showing a configuration of an ultrasound signal processor according to a seventh embodiment of the present invention. 
     FIG. 21 is a diagram showing a configuration of an ultrasound signal processor according to an eighth embodiment of the present invention. 
     FIG. 22 is a diagram showing another configuration for realizing cumulation and addition in the respective embodiments of the present invention. 
     FIG. 23 is a diagram showing a construction of an essential part of an ultrasound signal processor according to a ninth embodiment of the present invention. 
     FIG. 24 is a diagram showing a construction of an essential part of an ultrasound signal processor according to a tenth embodiment of the present invention. 
     FIG. 25 is a time sequence chart in the tenth embodiment. 
     FIG. 26 is a diagram showing an example of the construction of a first waveform conversion unit. 
     FIG. 27 is a diagram showing an example of the construction of a cumulation circuit. 
     FIG. 28 is a diagram showing an example of the construction of a second waveform conversion unit. 
     FIG. 29 is a diagram showing a construction of an essential part of an ultrasound signal processor according to an eleventh embodiment of the present invention. 
     FIG. 30 is a diagram showing a construction of the essential part of an ultrasound signal processor according to a twelfth embodiment of the present invention. 
     FIG. 31 is a diagram showing a construction of an essential part of an ultrasound signal processor according to a thirteenth embodiment of the present invention. 
     FIG. 32 is a diagram showing a construction of a fourteenth embodiment of the present invention. 
     FIG. 33 is a diagram showing a construction of an essential part of a conventional ultrasound signal processor. 
     FIG. 34 is a diagram for explaining an example of a received multibeam in a conventional ultrasound signal processor. 
     FIG. 35 is a time sequence chart in the eleventh embodiment. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiments of the present invention will now be described with reference to the accompanying drawings. 
     First Embodiment 
     FIG. 1 is a diagram showing a configuration of an ultrasound signal processor for realization of accurate digital beamforming processing according to a first embodiment of the present invention. In FIG. 1, a digital adder 4 for cumulation adapted to calculate the sum of signals in series is interposed between the digital mixer 15 and digital delay circuit 7 shown in FIG. 3. In this case, signals to be cumulated are of low frequency component G n  (t) delivered out of the digital mixer 15, that is, of an envelope form corresponding to A n  (t-τ n ) pursuant to equation (5). Therefore, as shown in FIG. 6, cumulation processing can proceed for a much longer time T l  than T o  shown in FIG. 5. The number of cumulating operations in the digital adder 4 for cumulation will be described. A spectrum as shown in FIG. 7 is an amplitude spectrum of s(t) and BW represents a band width of envelope A(t). Practically, because of sampling at the analog to digital converter, the spectrum a undergoes aliasing at a period of a sampling frequency of the analog to digital converter, but here, on the assumption that the sampling frequency of the analog to digital converter is sufficiently larger than ω s , spectrum aliasing is omitted. Since the spectrum a in FIG. 7 is subjected to multiplication by exp(-jω s  t) at the digital mixer 15 and to extraction of a low frequency component at the digital adder 4 for cumulation, an envelope spectrum centered at the zero frequency as shown at spectrum b in FIG. 7 develops as a spectrum of the adder output. In this phase, signal sampling frequency is reduced to (ADFQ/COUNT), where ADFQ is the sampling frequency of the analog to digital converter 5 and COUNT is the number of cumulation operations in the digital adder 4 for cumulation. Since the effect of improving S/N in the over-sampling technique becomes remarkable as the number of cumulation operations in the digital adder 4 for cumulation increases, aliasing at a period of the above (ADFQ/COUNT) cannot be neglected and there results a spectrum c as shown in FIG. 7. In order to completely reconstruct the envelope, duplication of the spectrum aliasing must be avoided and hence 
     
         COUNT≦(ADFQ/BW)                                     (8) 
    
     must stand. In this manner, a condition imposed on the number of cumulation operations is determined automatically from the band width of the envelope and the sampling frequency of the analog to digital converter. However, when improvement on S/N due to the number of cumulation operations is desired to predominate over slight overlapping of spectrum aliasing, equation (8) need not be satisfied. Returning to FIG. 1, the sampling theorem prescribes that the sampling frequency of the analog to digital converter 5 should be twice or more an upper limit frequency necessary for a frequency band of the transmitting signal s(t). On the assumption that the upper limit frequency is about 5MHz, the sampling frequency of the analog to digital converter 5 may be 10 MHz or more and the over-sampling can be effected satisfactorily by using an analog to digital converter 5 of, for example, 25MHz which is easily available at present. In addition, when the analog to digital converter 5 operates at 25MHz, the operation frequency of the digital mixer 15 is also 25MHz, thus permitting easy integration. Accordingly, the configuration exemplified in FIG. 1 is said to be very suitable for highly accurate digital beamforming processing. But when the aforementioned upper limit frequency is set to 15MHz, the analog to digital converter 5 needs a sampling frequency which is at least 30MHz and for the over-sampling, an analog to digital (A/D) converter of very high operation frequency (assumed to be 2.5 times larger than 30MHz, amounting up to 75MHz) is needed which is expensive and has high power consumption. The operating frequency of the digital mixer 15 also increases and integration is difficult to achieve. As will be seen from the above, the configuration example shown in FIG. 1 has difficulties in dealing with a high frequency ultrasound signal. 
     Second Embodiment 
     FIG. 8 is a diagram showing a configuration of an ultrasound signal processor according to a second embodiment of the present invention. In FIG. 8, reference numeral 14 designates an analog mixer, 11 denotes an analog low pass filter, 5 represents an analog to digital converter, 15 designates a digital mixer, 4 denotes a digital adder for cumulation, 7 designates a digital delay circuit and 3 denotes a digital adder. Reference numeral 18 designates an analog reference signal generator used when a receiving signal is subjected to analog mixing at the analog mixer 14, 19 designates a digital reference signal generator used when a receiving signal having undergone analog to digital conversion is subjected to digital mixing at the digital mixer 15, and 9 designates a control circuit for digital delay. A receiving signal at an n-th element is given by 
     
         f.sub.n (t)=A.sub.n (t-τ.sub.n) exp{j(ω.sub.s t-φ.sub.n)}+exp{-j( ω.sub.s t-φ.sub.n)}!    (9) 
    
     Real number expression of equation (9) is 
     
         f.sub.n (t)=2A.sub.n (t-τ.sub.n)COS(ω.sub.s t-φ.sub.n)(10) 
    
     Multiplication of the signal of equation (10) by a reference signal m n  (t) generated from the analog reference signal generator 18 is carried out at the analog mixer 14. For simplicity, on the assumption that the phase of m n  (t) is 0(zero) at t=0, there results 
     
         m.sub.n (t)=COS(ω.sub.a t)                           (11) 
    
     and the multiplication at the analog mixer 14 becomes multiplication of real number. Accordingly, a multiplication result O n  (t) is given by ##EQU5## and this is passed through the analog low pass filter 11 to provide 
     
         O.sub.n (t)=A.sub.n (t-τ.sub.n)COS{(ω.sub.s ω.sub.a)t-φ.sub.n }                             (13) , 
    
     which is returned to complex expression to provide 
     
         O.sub.n (t)A.sub.n (t-τ.sub.n) exp{j((ω.sub.s -ω.sub.a)t-φ.sub.n)}+exp{-j((ω.sub.s -ω.sub.a)t-φ.sub.n)}!                           (14). 
    
     In equation (14), ω s  in equation (9) is substituted by ω s  -ω a , indicating that the center frequency of the receiving signal is decreased from ω s  to ω s  -ω a  and when ω s  is large, components following the analog to digital converter 5 can be constructed easily. Then, by newly taking ω s  -ω a  for ω s , signal processings after equation (14) become identical to those explained with reference to equations (3) and (7). The reference signal from the analog reference signal generator 18 may otherwise be defined by 
     
         m.sub.n (t)=COS(ω.sub.a t-φ.sub.n)               (15). 
    
     In this case, the output of the analog low pass filter 11 is given by 
     
         O.sub.n (t)=A.sub.n (t-τ.sub.n)COS{(ω.sub.s -ω.sub.a)t}(16). 
    
     As described above, by newly taking ω s  -ω a  for ω s , multiplication at the digital mixer 15 is defined as 
     
         h.sub.n (t)=exp(-jω.sub.s t)                         (17), 
    
     which is common to the respective elements. 
     The frequency of the reference signal participating in the multiplication in the analog mixer 14 will be described. The spectrum of s(t) is assumed to be a spectrum a as shown in FIG. 9. Like FIG. 7, spectrum aliasing at a period of the sampling frequency of the analog to digital converter is omitted. BW represents a band width of an envelope. Since in the analog mixer 14 the multiplication by cos(ω a  t) is effected, the output spectrum of the analog low pass filter 11 becomes a spectrum b as shown in FIG. 9. If in this case two envelope spectra lying at positive and negative frequencies overlap, the envelope cannot be reconstructed in the ensuing operation. Accordingly, in order to completely reconstruct the envelope, a condition as expressed by 
     
         ω.sub.a ≦ω.sub.s -(BW/2)                (18) 
    
     is needed. In this case, too, if beat-down of the center frequency of s(t) has precedence over slight overlapping of the envelope spectra, equation (18) need not be satisfied. 
     The following description will proceed on the assumption that the center frequency ω s  -ω a  of the receiving signal shifted to a lower frequency by analog beat-down is taken for new ω s . The h n  (t) is defined as 
     
         h.sub.n (t)=exp{-j(ω.sub.s t-φ.sub.n)}           (19) 
    
     in equation (3), but it may not be a complex variable function but may be a real variable function. In such a case, h n  (t) is given by 
     
         h.sub.n (t)=COS(ω.sub.s t -φ.sub.n)              (20) 
    
     A multiplication result g n  (t) is given by ##EQU6## When only the low frequency component is taken into consideration, G n  (t) is given by equation (5) as in the preceding description. 
     A case where ω s  and τ n  are unknown and approximate value ω m  of ω and the time difference between the receiving signal of each element and a standard receiving signal are known will now be described. Thus, when the standard receiving signal is f l  (t), τ n  -τ l  is known. In this case, h n  (t) is given by 
     
         h.sub.n (t)=exp -j{ω.sub.m t-(ω.sub.m +ω.sub.a)(τ.sub.n -τ.sub.l)}!               (22). 
    
     The low frequency component of multiplication result g n  (t) is expressed by 
     
         G.sub.n (t)=A.sub.n (t-τ.sub.n)exp +j{(ω.sub.s -ω.sub.m)(t-τ.sub.n)-( ω.sub.m +ω.sub.a)τ.sub.l }!                                                        (23). 
    
     When a signal obtained by delaying equation (23) by τ l  -τ n  is V n  (t), there results ##EQU7## whose amplitude is proportional to a common waveform (A o  (t)), where φ l  =-(ω s  +ω a )τ l . Since equation (24) is a complex number, the envelope can be obtained in terms of an absolute value of the complex number. A real variable function form of equation (22) is 
     
         h.sub.n (t)=COS{ω.sub.m t-(ω.sub.m +ω.sub.a)(τ.sub.n -τ.sub.l)}                                            (25). 
    
     Then, V n  (t) becomes 
     
         V.sub.n (t)=A.sub.n (t-τ.sub.l)COS{(ω.sub.s -ω.sub.m)t-φ.sub.l)}                            (2 6). 
    
     In equation (26), the envelope cannot be determined when ω s  and ω m  are nearly equal to each other because φ l  is unknown. However, if ω s  and ω m  are made to differ suitably from each other so that, in spectra in equation (26), envelope spectra centered on frequencies ±(ω s  -ω m ) may not overlap, the envelope can be determined. Even in such a case, a trigonometric function indicative of a carrier signal of the receiving signal remains and hence an additional detection processing is required after the processing by the digital adder 3. 
     The case where ω s  and τ n  are known and approximate value ω m  of ω s  and the time difference τ n  -τ l  between the receiving signal of each element and the standard receiving signal are known has been described, but signal processings for cases where ω s  and the time difference τ n  -τ l  between the receiving signal of each element and the standard receiving signal are known and where approximate value ω m  of ω s  and τ n  are known can be analogized easily from the present embodiment. 
     Third Embodiment 
     FIG. 10 is a diagram showing a configuration of an ultrasound signal processor according to a third embodiment of the present invention. The present embodiment is a further modification of the first embodiment shown in FIG. 1. Namely, the multiplication of equation (3) by h n  (t) is decomposed as below ##EQU8## so as to be considered as two multiplying operations which permit a configuration as shown in FIG. 10. The decomposition of h n  (t) into the two multiplying operations is allowed only when the h n  (t) is a complex variable function. In FIG. 10, reference numerals 16 and 17 designate digital mixers for multiplication which substitute for that carried out by the digital mixer 15 in FIG. 1. Denoted by 20 and 21 are digital reference signal generators used during digital mixing at the digital mixers 16 and 17. A signal waveform p(t) used for initial digital mixing by the digital mixer 16 is common to the respective elements and is 
     
         p(t)=exp(-jω.sub.s tt)                               (28). 
    
     In the digital mixer 17, multiplication by a digital reference signal (which is different for each element) 
     
         q.sub.n (t)=exp(jφ.sub.n)                              (29) 
    
     generated from the digital reference signal generator 21 is effected to compensate mutual phase difference. In this configuration, by providing arrangements each composed of only the digital mixer 17 and ensuing components in parallel or performing a multiplexing processing, signals from a plurality of positions in an object to be tested can be received simultaneously. 
     FIG. 11 is a diagram showing a configuration for processing of a single channel signal in the third embodiment of the present invention. In FIG. 11, digital multipliers 26 corresponding to the digital mixers 16 and 17 in FIG. 10 use reference signals, 90° out of phase from each other, to perform multiplication. Digital mixer 17 multiplies complex output of digital adder 4 by complex digital reference signal exp(jφ n ), and digital mixer 17 is composed of four elemental digital multipliers and two digital adders, for its figure being simplified. 22 denotes digital adders for cumulation and 10 designates memories for temporary storage of results of addition at the digital adders 22 and which correspond to the digital adder 4 for cumulation addition in FIG. 10. The time relation between control signals is illustrated in FIG. 12. In the present embodiment, an analog to digital conversion (A/D conversion) command ADC and a command for ending cumulation and delivering results (cumulation/output) RSC are made to be synchronous with the transmitting signal to suppress noises. In FIG. 10, by changing, with time, control data generated by the digital reference signal generator 21 and the control circuit 9 for digital delay, the focal position can be shifted continuously. 
     FIG. 13 is a diagram showing another configuration for processing a single channel signal in the third embodiment of the present invention. In the present embodiment, digital shading networks 24 are interposed between the digital adders 22 for cumulation and the temporary memories 10 so that individual data pieces may be shaded differently during addition. Through this, the time relation among control signals (an analog to digital conversion (A/D conversion) command ADC, a command for ending cumulation and delivering results (cumulation/output) RSC and a digital shading generation command W) is set up as shown in FIG. 14 to ensure that digital data pieces individually shaded by the digital shading network 24 are added and delivered. 
     Fourth Embodiment 
     FIG. 15 is a diagram showing a configuration of an ultrasound signal processor according to a fourth embodiment of the present invention. The present embodiment is a further modification of the second embodiment shown in FIG. 8 and essentially, in the present embodiment, the configuration of the third embodiment shown in FIG. 10 is added with the analog mixer 14, analog reference signal generator 18 and analog low pass filter 11 shown in FIG. 8. 
     FIG. 16 is a diagram showing a configuration for processing of a single channel signal in the fourth embodiment of the present invention. In FIG. 16, an analog multiplier 25 corresponds to the analog mixer 14 in FIG. 15, an analog low pass filter 13 corresponds to the analog low pass filter 11 in FIG. 15, and digital multipliers 26 correspond to the digital mixers 16 and 17 in FIG. 15 and perform multiplication by using reference signals which are 90° out of phase from each other. 1 denotes digital adders for complex multiplication. 22 designates digital adders for cumulation and 10 denotes memories for temporary storage of addition results of the digital adders 22, the adders 22 and memories 10 corresponding to the digital adder 4 for cumulation addition of FIG. 15. Like the third embodiment, the time relation between control signals (ADS and RSC) is set up as shown in FIG. 12 and the ADC and RSC are made to be synchronous with the transmitting signal to suppress noises. Also, as in the case of the third embodiment, by changing, with time, control data pieces generated by the digital reference signal generator 21 and the control circuit 9 for digital delay, the focal position can be shifted continuously. 
     FIG. 17 is a diagram showing another configuration for processing of a single channel signal in the fourth embodiment of the present invention. In the present embodiment, like the configuration shown in FIG. 13, digital shading networks 24 are interposed between the digital adders 22 for cumulation and the temporary memories 10 so that individual data pieces may be shaded differently during addition. As in the case of FIG. 13, the time relation among control signals is set up as shown in FIG. 14 to ensure that digital data pieces individually shaded by the digital shading networks 24 are added and delivered. 
     Fifth Embodiment 
     Arrangements adapted to perform a processing of the digital mixer 17 and the ensuing processings shown in FIG. 13 are provided in parallel as will be described below. 
     FIG. 18 is a diagram showing a configuration of an ultrasound signal processor according to a fifth embodiment of the present invention. In FIG. 18, reference numerals used in FIG. 10 designate like components and blocks 121 to 123 having each digital mixers 17, digital delay circuits 7 and digital adders 3 are connected in parallel. Denoted by a 1  to a 3  are outputs from the block 121, by b 1  and b 2  are outputs from the block 122 and by c 1  and c 2  are outputs from the block 123, the outputs indicating signal values corresponding to an ultrasound beam formed by each block. By providing the three delay/addition arrangements in parallel after the digital mixers 4 for cumulation, receiving beams in three different directions can be formed on time division basis. 
     Sixth Embodiment 
     FIG. 19 is a diagram showing a configuration of an ultrasound signal processor according to a sixth embodiment of the present invention. Essentially, in the present embodiment, the analog mixer 14, analog reference signal generator 18 and analog low pass filter 11 shown in FIG. 8 are added to the configuration of the fifth embodiment shown in FIG. 18. 
     Seventh Embodiment 
     A configuration for storing all signals after the over-sampling processing to effect focus adjustment will now be described. 
     FIG. 20 is a diagram showing a configuration of an ultrasound signal processor according to a seventh embodiment of the present invention. In FIG. 20, digital signal memories 12 are interposed between digital adders 4 for cumulation and digital mixers 17. The memory is adapted to efficiently store data necessary for performing focus adjustment based on adaptive image reconstruction. A signal after the over-sampling processing preserves all information pieces within a band of a receiving signal which are caused by beat-down to be preserved within a low frequency band, and therefore fore the number of storing data pieces representative of the signal is compressed. By performing phase correction of the signal from the digital mixer 17 and time shift by the digital delay circuit 7 carried out in a complimentary manner to the phase correction, a beam forming method complying with conditions of an object to be imaged can be realized. Through this, delay time τ n  applied to one receiving element after another can be changed in expectation of the fact that, for example, the speed of sound sightly changes from one portion to another within an object to be tested. 
     Eighth Embodiment 
     FIG. 21 is a diagram showing a configuration of an ultrasound signal processor according to an eighth embodiment of the present invention. Essentially, in the present embodiment, the analog mixer 14, analog reference signal generator 18 and analog low pass filter 11 are added to the configuration of the seventh embodiment shown in FIG. 20. 
     In the second, fourth, sixth and eighth embodiments described previously, the configuration of the analog to digital converter for handling an ultrasound signal having a higher center frequency than that in the first, third, fifth and seventh embodiments can be simplified. 
     In the respective embodiments described as above, the frequency of a receiving signal after the analog beat-down is made to be coincident with that of a digital reference signal but the present invention is in no way limited thereto and the frequency of the digital reference signal may be changed with time. 
     The configuration of the adder 4 for cumulation is not limited to that described previously and various configurations thereof may be conceivable provided that they have the integrating effect due to addition. For example, an arrangement as shown in FIG. 22 may be employed wherein shading necessary for individual data pieces can be realized at a high degree of freedom. In FIG. 22, reference numerals 310 to 31k and 340 to 34m designate adders, 320 to 32k, 330 to 33m and 370 to 37r designate unit-delay circuits, 350 to 35k and 360 to 36 (m +1) designate multipliers and 380 to 38(r+1) designate gates. Coefficients of the respective multipliers may be fixed or may be read out of a memory, not shown, in compliance with purposes. Denoted by k, m and r are integers, not negative, which are determined by intended configuration and scale. With this configuration, by utilizing a feed-back unit 22A or a feed-forward unit 22B, an integrating circuit having a desired frequency characteristic can be set up. Further, the output frequency and timing offset can be controlled desirably by means of an output timing control unit 22C. The scale or the presence or absence of 22A, 22B and 22C is selected as necessary. Obviously, in addition to the illustrated configuration, many configurations having the same function as that of FIG. 22 may be available. 
     In the respective embodiments set forth so far, the arrangement of the digital delay circuit 7 and digital mixer 17 may be changed as necessary. In the foregoing embodiments, the absolute amplitude of the reference signal envelope in the analog mixer 14 and digital mixers 15, 16 and 17 is set to 1 (one) but this is not limitative and the amplitude of the reference signal envelope may be changed for each element to shade receiving signals. In the signal processor of the present invention, the cumulation processing after the beat-down of a receiving signal is realized and the over-sampling processing acts effectively to simplify the configuration of the analog to digital converter, and the present processor can therefore be applied to various apparatus in addition to the ultrasound apparatus. In the foregoing embodiments, each of the digital circuits such as the digital reference signal generator, digital delay circuit, control circuit for digital delay, digital adder and digital mixer may be constructed by using a corresponding analog circuit, an A/D converter and/or D/A converter in combination. 
     Next, specific examples of construction of an apparatus for forming a multibeam (ninth to fourteenth embodiments) will be described. In a received signal processing circuit of the ultrasound signal processor of the present invention, the Nyquist sampling frequency for a received signal lowered to a baseband has a low frequency and therefore, time intervals at which data pieces for one received beam are generated are prolonged and the sampling frequency for generation of these data pieces can be decreased. When the sampling frequency is set to 1/m of a sampling frequency actually supplied to the ADC, m beam data pieces can be processed in a time sharing fashion by changing the order of data pieces processed on the time axis in one received signal processing circuit. Accordingly, a multi-direction delay unit can effect a signal processing for forming a plurality of received beams through a time sharing process in one received signal processing circuit, thereby ensuring that a received multibeam can be formed without increasing the circuit scale of the received beam forming unit. 
     The embodiments of the present invention will now be described in greater detail with reference to the accompanying drawings. 
     Ninth Embodiment 
     A construction of an essential part of an ultrasound signal processor according to a ninth embodiment of the present invention is illustrated in block form in FIG. 23. Received signals received at an array of transducers 23 are each processed by an amplifier or a variable amplifier, an analog filter or an analog filter of variable frequency band width and the like and are fed to a received signal processing unit. Here, the received signal processing unit includes analog to digital converters (ADC&#39;s) 5, first waveform conversion units (digital mixers) 16, cumulation circuits 4, and multi-direction delay units 27. For simplification of explanation, 4 channels are exemplified in FIGS. 23, 24, 29, 30, 31 and 32. 
     Each of the received signals fed to the received signal processing unit constructed as shown in FIG. 23 undergoes digital conversion by means of the ADC 5 constituting the received signal processing unit. A sampling clock Sck set in the ADC is generated from a sampling clock generator 31 and supplied in common to sampling clock input terminals of the ADC&#39;s of individual channels. Obviously, with packaging in mind, the sampling clock generator may be provided on each printed circuit board (on which, for example, received signal processing circuits for 20 channels each in the form of an LSI are carried). In this case, however, the sampling clocks for all channels have to be synchronous with each other. 
     Obviously, when the received signal processing circuits take the form of LSI&#39;s, a sampling clock may be generated from an LSI of each channel. In the received signal processing unit, a number of received signal processing circuits are arranged in parallel in order that respective received signals from the respective transducers can be processed and under this situation, the word&#34;channel&#34; means a received signal processing circuit supplied with one received signal. 
     It is known in the art that a received signal can be reconstructed when the sampling frequency for the ADC is twice or more an upper limit frequency of a frequency band width for the received signal. In the present invention, signals from the individual transducers can be sampled at a sufficiently higher frequency. A sampled received signal is then fed to the first waveform conversion unit 16 at which the sampled received signal is multiplied by a digital reference signal (center frequency ω s ) generated from a digital reference signal generator 19 and a waveform of the received signal is converted into a complex signal having a difference frequency part and a sum frequency part. 
     The digital reference signal from the digital reference signal generator 19 is also fed in common to the respective channels. A concrete example of the first waveform conversion unit 16 (digital mixer) is shown in FIG. 26. 
     In the example shown in FIG. 26, a received signal converted into m bits by means of the ADC 5 branches to two of which one is multiplied by cos(ω s  t) by means of a digital multiplier 26 and the other is multiplied by sin(ω s  t) by means of a digital multiplier 26&#39;. Here, ω s  is a center frequency of the received signal. Through the signal processing shown in FIG. 26, the received signal is converted into a complex signal having a difference frequency part (difference frequency ω s  -ω s  =0) which is a signal component of a baseband and a sum frequency part (sum frequency ω s  +ω s  =2ω s ). Output signals (imaginary part and real part signals) shown in FIG. 26 are fed to a cumulation circuit 4. Since the signal component of a baseband is lowered to a frequency which is sufficiently lower than the center frequency of the first received signal, even a sampling frequency identical to the sampling frequency for the ADC can ensure sampling which sufficiently satisfies the Nyquist sampling frequency for the baseband (over-sampling) and addition (cumulation) of received signals sampled in a time series fashion can be permitted. A specified example of the cumulation circuit is shown in FIG. 27. 
     A received complex signal of (m+4) bits is sequentially held by latches 33 and three sequential consecutive data pieces of the output signal of the circuit shown in FIG. 26 are added together in an adder 22. With the ADC supplied with the maximum amplitude, the number of bits is of course increased and (m+6) bits result. Through the addition of the received signals, quantization noise and white noise of input noise are canceled out and the signal can be nearly tripled while the noise being √3 times increased, so that the S/N can be increased by 3dB. The number of addition operations COUNT in the cumulation circuit is determined by sampling frequency f s  (=ADFQ) and frequency band width BW as follows: 
     
         COUNT≦(ADFQ/BW)                                     (8). 
    
     The envelope of the received signal can be reconstructed if a condition pursuant to equation (8) is satisfied. 
     In the structure shown in FIG. 27, three consecutively received signals are sequentially added and delivered and therefore the cumulation circuit is constructed so as to have a rectangular shading filter characteristic. In order to decrease an unwanted frequency component of the sum frequency part, various methods have been contrived including a method in which two stages of the structure shown in FIG. 27 are provided and triangular weight is applied in the addition (cumulation) of received signals or the number of addition operations in the preceding and succeeding stages is adjusted to apply rectangular weight. In any method, through the use of only the digital adders, various types of weight can be realized. Given that output data pieces of the first waveform conversion unit (digital multiplier) 16 in FIG. 23 are represented by Di (i is a number of the sampling clock signals), (D1+D2+D3+D2+D3+D4+D3+D4+D5)=(D1+2D2+3D3+2D4+D5) is obtained. Coefficients of Di are 1, 2, 3, 2 and 1 to represent triangular weight. 
     The cumulation circuit constructed as shown in FIG. 27 can provide a baseband signal of the received signal. Various delay processings are carried out using the baseband signal. Here, a signal processing is carried out in which a time difference required for ultrasound to propagate through a distance difference between a target focus position and each of the transducers is compensated in terms of time or phase by means of a multi-direction delay unit 27 to match wave fronts of echoes, received signals generated from the respective transducers are added together by means of a digital adder 3, an envelope of the received signal is determined by an envelope conversion unit 28 to provide a signal for formation of a received beam, and the direction of the received beam is changed to form received beams. The above signal processing is repeated to scan the received beam to provide a display on a display unit 30 by means of a digital scan converter (DSC) 29. 
     The multi-direction delay unit 27 is constructed as exemplified in FIG. 24. In this example, each received signal processed by the cumulation circuit 4 is temporarily stored in a temporary memory 34 in order that received signals of the same Ri are saved, under the control of a control unit for temporary memory 35, so as to be used for formation of a plurality of received beams, and the received signals Ri necessary for-formation of the received beams are delivered out of the temporary memory to form a received multibeam in a time sharing fashion. 
     Tenth Embodiment 
     A sequence of multibeam formation according to a tenth embodiment of the present invention will now be described. Illustrated in FIG. 25 is an example of a sequence in which after one transmission operation of ultrasonic wave, a plurality of ultrasound received beams are formed from a received signal received at each of the transducers forming a receiving aperture, thereby forming received beams in two different directions. In FIG. 25, timings of output signals from the respective signal processing units are illustrated by taking a fourth channel, for instance, but the same holds true for another channel. A signal of sampling clock Sck is applied to a point H (sampling clock for ADC&#39;s) in FIG. 24. The ADC starts sampling operation at a timing of rise (arrow) of the sampling clock Sck. The system is operated as a whole by a system clock synchronized with the sampling clock Sck. At the timing of arrow, a received signal is sampled by the ADC and converted by the first waveform conversion unit (digital mixer) 16 into a signal having a baseband and a sum frequency part, the converted signal being represented by D1, D2, D3, . . . (each of which is a quantized received signal obtained by quantizing the amplitude of the received signal each time that the sampling clock signal rises and in the example of FIG. 26, a signal Di converted into a baseband and a sum frequency part has an amplitude of (m+4) bits). The converted signals are processed by the cumulation circuit 4. For example, in the case of the construction of FIG. 27, an output B of the cumulation circuit 4 takes the form of (D1+D2+D3)=R1, (D2+D3+D4)=R2 . . . , indicating that received signals Di to be added over three sampling clock signals are put together and added to deliver addition results. 
     Each of the output signals R1, R2, R3, . . . ,Ri, . . . of the cumulation circuit has a sum frequency part suppressed by filtering and as a result, substantially takes the form of a baseband signal. The baseband signal is stored in the temporary memory 34. It is now considered that received beams are formed in different directions at each alternate system clock signal. For example, a received beam (a beam) is formed in an a direction at an even system clock signal and a received beam (b beam) is formed in a b direction at an odd system clock signal. It is now assumed that a received signal to be added to a first received signal of a beam on a reference channel (which is, for example, the center channel of the plurality of channels constituting the receiving aperture) is R2, a next received signal on the reference channel is a first received signal for b beam, and a received signal to be added to the first received signal for b beam is R1. Here, the order of received signals used for beam formation is inverted to R2 and R1 as compared to the arrangement of the received signals delivered out of the cumulation circuit. Accordingly, the output signals from the cumulation circuit are temporarily stored in the temporary memory 34 so that for example, the received signal of R2 may be read out of the temporary memory 34 at a fourth system clock signal and the received signal of R1 may be read at the next system clock signal to ensure that the received signals necessary for received beam formation can be taken out of the temporary memory in a necessary order. Of the received signals delivered out of the temporary memory, data R2 is applied with phase compensation data aF1 for formation of a beam in a first stage of focus by means of a digital phase compensate signal generator 21. The signal processing necessary for formation of received beams in the different directions is carried out in this manner and thereafter, pieces of data Ri are sequentially delivered out of the temporary memory and added by the digital adder 3 while maintaining the order of signals of each channel and the order of con signal compensation for delay, an envelope is determined by the envelope conversion unit 28 and finally, signals of a received multibeam obtained from the DSC 29 in a time sharing fashion are displayed simultaneously as an image display on the display unit 30. 
     As shown in FIGS. 24 and 25, as compared to the order of output signal C of the cumulation circuit 4, the order of the output signals of the temporary memory is changed to R2, R1, R4, . . . upon delivery and R2 is applied with phase compensate data aF1 for formation of a beam in a first stage of focus by means of the digital phase compensate generator 21. 
     The next R1 is applied with phase compensation data bF1 for b beam of a first stage of focus. Thereafter, a second waveform conversion unit 17 performs a phase rotation processing for making the first received signal a1 of a beam, the first received signal b1 of b beam, the second received signal a2 of a beam and so on be delivered in this order. The thus delivered received signals are sequentially written in a digital delay circuit 7 such as a memory. By reading the received signals a1, b1, a2, . . . from the digital delay circuit 7 in synchronism with the delivery of received signals from the digital delay circuit of a channel used as a reference for delay time processing, a time delay can be applied. For example, in the example of FIG. 25, a delay time of two system clocks is applied to the received signal and the delivery from the digital delay circuit is such that the first received signal a1 for formation of a beam of the reference channel (second channel) is delivered at a timing of delivery of a sixth sampling clock signal, whereby in the present channel (fourth channel) set forth so far, the first received signal a1 for formation of a beam is also delivered at the timing of delivery of the sixth sampling clock signal and added with output signal a1 of the reference channel (second channel). 
     Accordingly, it will be seen that by making delivery from the digital delay circuit delayed by two clocks, a time delay of two clocks can be realized. Here, the focus stage is used to change focus data (data read out of the digital delay circuit (memory) and data for phase rotation) with time in order to obtain excellent focus at all focal depths by dynamically changing the focal distance and a section of the same focus data is defined as&#34;stage&#34;. Thus, the multi-direction delay unit 27 processes the sampled received signals in a time sharing fashion and delivers received signals for formation of a received multibeam. The delivered data pieces for all channels constituting the receiving aperture are added by the digital adder 3 and then the same contents of the signal processing as above is repeated. The thus obtained signals representative of a received multibeam are temporarily stored in the digital scan converter (DSC) and are simultaneously displayed as the received multibeam on the display unit. 
     In an ultrasonic signal processor for performing the signal control processing and signal processing by means of a personal computer, the contents of the processing of forming a received beam and DSC processing is dealt with digitally. The sequence shown in FIG. 25 is usually subjected to timing adjustment by means of, for example, a latch because of limited circuit operation speed of LSI but for convenience of explanation of the principle, an ideal operation is illustrated. 
     When considering the period of formation of data for formation of one received beam, for example, data a1, a2 and a3 for a beam, it will be seen the period of data formation is two clocks of the Sck and is twice the sampling period for the ADC, indicating that the signal processing speed for formation of one received beam is of a low frequency. 
     Illustrated in FIG. 28 is an example of construction of the second waveform conversion unit 17. Each input complex signal is multiplied by a phase signal (cosφ n , sinφ n ) having its phase rotation amount φ n  which is 90° out of phase with respect to the input signal (real part, imaginary part) by means of digital multipliers 26 and output signals of the two multipliers are added by means of a digital adder 22 to effect phase rotation. Data indicative of the phase rotation amount at that time is inputted from the digital phase compensation signal generator 21 of FIG. 24 in association with each channel. To explain with reference to FIG. 25, one received beam is dynamically focused as described previously and on the assumption that the focal position is switched each time that four sampling clock signals 5 are delivered, the focus stages are designated by F1, F2, . . . 
     aF1 is data of a first focus stage of a beam. The phase rotation data is aF1 at a timing of delivery of a fourth sampling clock signal, is bF1 for a first focus stage of b beam at a timing of delivery of a fifth sampling clock signal, is aF1 for the first focus stage for a beam at a timing of delivery of a sixth sampling clock signal and is bF1 for the first focus stage for b beam at a timing of delivery of a seventh sampling clock signal, and the focus position is switched at a timing of delivery of an eighth sampling clock signal to provide the phase rotation data which is aF2 for a second focus stage of a beam. In this manner, focus data used for rotation is changed and controlled. 
     Eleventh Embodiment 
     An eleventh embodiment of the present invention will now be described. 
     Referring to FIG. 29, there is illustrated another example of construction of the multi-direction delay unit 27 in which the digital delay circuit 7 precedes the second waveform conversion unit 17. Illustrated in FIG. 35 is a sequence effected by the construction shown in FIG. 29 (symbolized similarly to FIG. 25) in which, after one ultrasonic transmission operation, a plurality of ultrasound received beams are formed from received signals generated from respective transducers forming the receiving aperture and received beams are formed in different directions. In FIG. 35, timings of output signals from the respective signal processing units are illustrated by taking a fourth channel, for instance, but the same holds true for another channel. As shown in FIG. 35, output signals of a cumulation circuit are delayed to select received signals for formation of a received multibeam and the selected received signals are delivered to the second waveform conversion unit. 
     Output signals R1, R2, R3, . . . , Ri, . . . of the cumulation circuit are stored in the digital delay circuit (memory) 7. When reading data from the digital delay circuit (memory) 7, a delay time from the reference channel (second channel) is compensated to form a received beam (a beam) in an a direction at an even system clock Sck and a received beam (b beam) in a b direction at an odd system clock. When a delay time of two system clocks from the reference channel (second channel) is necessary for a beam and a delay time of four system clocks from the reference channel is necessary for b beam, R2 is read with a delay time of two system clocks for a beam and R1 is read with a delay time of four system clocks for b beam as shown in FIG. 35, thus realizing a delay for each received signal. The delayed signals are multiplied by phase compensation data to perform phase compensation (phase rotation), so that results subject to highly accurate delay process are sequentially delivered. Received signals sequentially delivered out of the multi-direction delay units 27 are added together by means of the digital adder 3 while keeping unchanged the order of formation of received beams of each channel and the order of delayed received signals of each channel to be added, an envelope is determined by the envelope conversion unit 28 and finally, signals of a received multibeam generated from the DSC 29 are image-displayed simultaneously on the display unit 30. Thus, by forming a plurality of ultrasound received beams from received signals generated from the respective transducers forming the receiving aperture after one transmission operation of ultrasound, a plurality of received beams can be formed on one channel in a time sharing fashion. The above operation is repeated to scan a beam, thus obtaining an image. The timing for reading data from the digital delay circuit (memory) is controlled by a control circuit for digital delay 9. 
     Twelfth Embodiment 
     A twelfth embodiment in which received signals are shaded to decrease unwanted responses of ultrasound beams is constructed as shown in FIG. 30. Digital shading networks 24 succeeding outputs of the multi-direction delay units 27 are provided on respective channels. Shading data is supplied from a shading signal generator 36 to each channel to form an excellent received beam of less unwanted response. 
     Thirteenth Embodiment 
     A thirteenth embodiment is constructed as shown in FIG. 31. Preset focus data becomes blurred because of irregularity in distribution of sound speeds in a living body. In the present embodiment, the focal blur is compensated by determining a phase error between adjacent channels from delayed complex received signals of the respective channels by means of a delay and phase error detection unit 37 for detecting a phase difference on the basis of phase multiplication or phase correlation and feed-backing the phase error and a time error converted therefrom to the control unit for received beam former 32 so as to modify a received beam formation controlling condition. 
     Fourteenth Embodiment 
     A fourteenth embodiment is constructed as shown in FIG. 32. In the Doppler (DP) processing and the color flow mapping (CFM) processing for two-dimensional color display of blood flow, the received signal is usually lowered to a baseband and then processed. Since in the signal processing method the received signal is lowered to the baseband, the received signal is passed through a moving target indication (MTI) 40 so as to detect a blood flow by means of a CFM unit 38 and a DP unit 39. The MTI is a fixed target eliminating filter based on high-pass filtering and adapted to eliminate a low frequency component representative of an artifact of a low frequency near 0 frequency due to motion of other internal organs rather than blood flow caused by respiration and heart motion. 
     In the foregoing, the formation of a received multibeam has been described but when a single received beam is formed, the signal processing after the cumulation processing may be carried out using a 1/m system clock or directly using a system clock of the same rate as the sampling clock for the ADC. The speed of the signal processing after the cumulation processing can be changed by changing control data of the control unit for received beam former. 
     While in the foregoing embodiments the present invention has been described, for simplification of explanation, by way of sector scanning in which the received signal processing circuit (received signal channel) is connected to the transducer in one to one relation and the transmitting and receiving aperture is formed by all transducers, the present invention is in no way limited thereto. In addition to the sector scanning, the present invention can be applied to an ultrasound signal apparatus needing the function of selecting an element (transducer) for wave transmission and reception (transmitting and receiving aperture selection) by means of, for example, a linear or convex ultrasonic probe, in a similar way to that in each of the foregoing embodiments. In the present invention, so long as the number of received signal processing circuits equals the number of transducers forming the receiving aperture, the processing can be carried out in which after one transmission operation of ultrasound, a plurality of ultrasound received beams are formed from received signals generated from the respective transducers forming the receiving aperture. 
     Many different embodiments of the present invention may be constructed without departing from the spirit and scope of the invention. It should be understood that the present invention is not limited to the specific embodiments described in this specification. To the contrary, the present invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the claims.