Patent Publication Number: US-2022231123-A1

Title: Stack, electronic device, and method for manufacturing stack

Description:
TECHNICAL FIELD 
     The present disclosure relates to stacks, electronic devices, and methods for manufacturing stacks. 
     The present application claims priority to Japanese Patent Application No. 2019-125868, filed on Jul. 5, 2019, the entire contents of which are incorporated herein by reference. 
     BACKGROUND ART 
     Graphene is a material in which carbon atoms are bonded together in a plane by forming sp 2  hybrid orbitals. Due to such a bonding state of carbon atoms, graphene exhibits very high carrier (electron) mobility. If graphene can be effectively utilized as channels of electronic devices such as transistors, the performance of electronic devices can be improved. 
     A method has been proposed in which a substrate consisting of silicon carbide (SiC) is heated to remove silicon atoms and thereby convert the surface layer portion of the substrate into graphene (see, for example, NPL 1). NPL 1 discloses graphene, having a step-terrace structure, that is manufactured by performing hydrogen treatment before removing silicon atoms to produce graphene, and adjusting the heating rate. 
     CITATION LIST 
     Non Patent Literature 
     
         
         NPL 1: Jianfeng Bao et al., “Sequential control of step-bunching during graphene growth on SiC(0001)”, APPLIED PHYSICS LETTERS 109, 081602 (2016) 
       
    
     SUMMARY OF INVENTION 
     A stack according to the present disclosure includes a base portion consisting of silicon carbide and having a first surface that is a Si face and a carbon atom thin film disposed on the first surface and including a first main surface facing the first surface and a second main surface that is a main surface on an opposite side from the first main surface. The carbon atom thin film consists of carbon atoms. The carbon atom thin film includes at least one of a buffer layer that is a carbon atom layer including carbon atoms bonded to silicon atoms forming the Si face and a graphene layer. The second main surface includes a plurality of terraces parallel to the Si face of the silicon carbide forming the base portion and a plurality of steps connecting together the plurality of terraces. The terraces have a width of 5 μm or more and 500 μm or less. The steps have a height of 10 nm or more and 500 nm or less. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a schematic sectional view illustrating the structure of a stack according to a first embodiment. 
         FIG. 2  is a plan view of the stack illustrated in  FIG. 1  as viewed in the thickness direction. 
         FIG. 3  is a conceptual diagram illustrating an example of the bonding state of atoms forming the stack illustrated in  FIG. 1 . 
         FIG. 4  is a conceptual diagram illustrating the bonding state of the atoms after the conversion of a buffer layer into a graphene layer. 
         FIG. 5  is a schematic sectional view schematically illustrating, in an enlarged view, a portion of the stack including a second main surface. 
         FIG. 6  is a micrograph, captured with magnification under an AFM, of a portion of the second main surface of the stack illustrated in  FIG. 1 . 
         FIG. 7  is a graph illustrating the relationship between drain voltage and drain current with varying gate voltages for a transistor manufactured using the stack according to the first embodiment. 
         FIG. 8  is a schematic sectional view schematically illustrating, in an enlarged view, a second main surface of a stack outside the scope of the present disclosure. 
         FIG. 9  is a graph illustrating the relationship between drain voltage and drain current with varying gate voltages for a transistor manufactured using the stack illustrated in  FIG. 8 . 
         FIG. 10  is a flowchart illustrating typical steps of a method for manufacturing the stack according to the first embodiment. 
         FIG. 11  is a schematic sectional view for illustrating the method for manufacturing the stack according to the first embodiment. 
         FIG. 12  is a schematic sectional view illustrating the structure of a heating device. 
         FIG. 13  is a schematic sectional view of a field-effect transistor (FET) according to a second embodiment. 
         FIG. 14  is a flowchart illustrating typical steps of a method for manufacturing a FET including a carbon atom thin film. 
         FIG. 15  is a schematic sectional view for description of the method for manufacturing a FET including a carbon atom thin film. 
         FIG. 16  is a schematic sectional view for description of the method for manufacturing a FET including a carbon atom thin film. 
         FIG. 17  is a schematic sectional view for description of the method for manufacturing a FET including a carbon atom thin film. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Problems to be Solved by Present Disclosure 
     An electronic device manufactured using the graphene disclosed in NPL 1 has a problem in that good modulation characteristics cannot be achieved. Accordingly, one object is to provide a stack that allows the modulation characteristics of an electronic device to be improved, an electronic device including the stack, and a method for manufacturing the stack. 
     Advantageous Effects of Present Disclosure 
     The above stack allows the modulation characteristics of an electronic device to be improved. 
     Description of Embodiments of Present Disclosure 
     First, embodiments of the present disclosure will be listed and described. A stack according to the present disclosure includes a base portion consisting of silicon carbide and having a first surface that is a Si face and a carbon atom thin film disposed on the first surface and including a first main surface facing the first surface and a second main surface that is a main surface on an opposite side from the first main surface. The carbon atom thin film consists of carbon atoms. The carbon atom thin film includes at least one of a buffer layer that is a carbon atom layer including carbon atoms bonded to silicon atoms forming the Si face and a graphene layer. The second main surface includes a plurality of terraces parallel to the Si face of the silicon carbide forming the base portion and a plurality of steps connecting together the plurality of terraces. The terraces have a width of 5 μm or more and 500 μm or less. The steps have a height of 10 nm or more and 500 nm or less. 
     For example, when a carbon atom thin film is used as a channel layer of a transistor, the transistor may be manufactured by forming electrodes on a region including terraces that are included in the second main surface and that allow for stable charge transport. However, if the terraces have a small width, a large number of steps are included in the channel layer. In the carbon atom thin film, regions including steps and regions including terraces have different electrical characteristics. If a large number of steps are included in the channel layer of the transistor, it is difficult to achieve good modulation characteristics. For example, a terrace width of at least 5 μm is required to form a channel layer including no steps. 
     For the stack according to the present disclosure, the terraces have a width of 5 μm or more and 500 μm or less. Because the terraces have a width of 5 μm or more, a channel layer of a transistor can be easily formed in a region including a single terrace. In addition, because the terraces have a large width, a channel layer of a transistor can be formed with a reduced number of steps included in the channel layer. Thus, good modulation characteristics can be easily imparted to the manufactured transistor. On the other hand, if the terraces have an excessive width, the steps consequently have an excessive height, and the carbon atom thin film is likely to be broken in regions where the steps are located. Because the terraces have a width of 500 μm or less, the likelihood of the carbon atom thin film being broken can be reduced. In the present disclosure, “terrace” refers to a region where the in-plane step difference is within the range of ±1 nm. 
     In addition, the steps have a height of 10 nm or more and 500 nm or less. When the carbon atom thin film includes a buffer layer, the buffer layer is preferably converted into a graphene layer by breaking the bonds between the silicon atoms forming the Si face and the carbon atoms included in the buffer layer. In this case, the bonds between the silicon atoms and the carbon atoms may be broken, for example, by supplying hydrogen gas to the stack, specifically, between the Si face and the carbon atom thin film. In this way, the buffer layer is converted into a graphene layer. The terraces have low gas permeability; therefore, it is difficult to supply hydrogen gas between the Si face and the carbon atom thin film through the terraces. 
     For the stack according to the present disclosure, the steps have a height of 10 nm or more; therefore, hydrogen gas easily passes through regions including the steps in the direction along the terraces. Thus, hydrogen gas can be easily supplied between the Si face and the carbon atom thin film. Accordingly, hydrogen gas treatment for breaking the bonds between the silicon atoms and the carbon atoms can be efficiently performed. On the other hand, if the steps have a height of more than 500 nm, the carbon atom thin film is likely to be broken in the regions including the steps. Because the steps have a height of 500 nm or less, the likelihood of the carbon atom thin film being broken can be reduced. As described above, because the terraces of the stack according to the present disclosure has a large width, and the buffer layer can be easily converted into a graphene layer by breaking the bonds between the silicon atoms and the carbon atoms, the modulation characteristics of an electronic device can be improved. 
     In the above stack, the number of atomic layers of the graphene layer may be three or less. In this case, a stack including a graphene layer that can stably ensure high carrier mobility can be obtained. 
     An electronic device according to the present disclosure includes the above stack, a first electrode disposed on the second main surface, and a second electrode disposed away from the first electrode on the second main surface. Because the electronic device according to the present disclosure includes the above stack, the modulation characteristics can be improved. 
     A method for manufacturing a stack according to the present disclosure includes the steps of providing a silicon carbide substrate having a first substrate surface that is a Si face; placing the silicon carbide substrate in a first space enclosed by a cover member disposed in a chamber; and heating the silicon carbide substrate in the first space to remove silicon atoms from a first region including the first substrate surface, thereby converting the first region into at least one of a buffer layer that is a carbon atom layer including carbon atoms bonded to silicon atoms forming the silicon carbide substrate and a graphene layer. A first member including a material containing silicon atoms is disposed in the first space. 
     Thus, silicon atoms can be supplied from the first member to the first space enclosed by the cover member to increase the concentration of silicon atoms in the first space. When silicon atoms are removed from the first region including the first substrate surface, the surface diffusion of carbon atoms and silicon atoms in the first region can be promoted. Therefore, when the first region is converted into at least one of a buffer layer and a graphene layer, the terrace width of the first surface can be easily increased, and the step height of the first surface can be easily increased. Thus, a stack having a large terrace width and a large step height can be easily obtained. 
     In the above method for manufacturing a stack, the first member may be a silicon layer covering at least a portion of an inner wall of the cover member. In this case, silicon atoms can be easily supplied to the first space. 
     Details of Embodiments of Present Disclosure 
     Next, an embodiment of a stack of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and a description thereof is not repeated. 
     First Embodiment 
     A stack according to a first embodiment of the present disclosure will be described.  FIG. 1  is a schematic sectional view illustrating the structure of the stack according to the first embodiment.  FIG. 2  is a view of the stack illustrated in  FIG. 1  as viewed in the thickness direction. In  FIG. 1 , the thickness direction of a stack  11  is indicated by the arrow T. 
     Referring to  FIGS. 1 and 2 , the stack  11  according to the first embodiment is disc-shaped. As the diameter L of the stack  11  illustrated in  FIG. 2 , for example, 2 inches (50.8 mm) is selected. As the diameter L of the stack  11 , for example, 4 inches (101.6 mm) may also be selected. 
     The stack  11  according to the first embodiment includes a base portion  12  and a carbon atom thin film  13 . The base portion  12  is plate-shaped. The base portion  12  consists of silicon carbide (SiC). The SiC forming the base portion  12  is hexagonal SiC having, for example, a 6H structure. The SiC forming the base portion  12  may also be hexagonal SiC having a 4H structure. The base portion  12  has a first surface  12 A. The first surface  12 A is a Si face of the SiC forming the base portion  12 . In  FIG. 1 , the carbon atom thin film  13  is illustrated as being thick for ease of understanding. The thickness direction of the carbon atom thin film  13  is indicated by the arrow T. 
     The carbon atom thin film  13  consists of carbon atoms. The carbon atom thin film  13  is disposed on the first surface  12 A of the base portion  12 . The carbon atom thin film  13  includes a first main surface  13 B facing the first surface  12 A and a second main surface  13 A that is a main surface on the opposite side from the first main surface  13 B. The second main surface  13 A is an exposed surface. The carbon atom thin film  13  includes at least one of a buffer layer that is a carbon atom layer including carbon atoms bonded to silicon atoms forming the first surface  12 A, which is a Si face, and a graphene layer. 
       FIG. 3  is a conceptual diagram illustrating an example of the bonding state of atoms forming the stack  11  illustrated in  FIG. 1 . Referring to  FIG. 3 , the carbon atom thin film  13  includes a buffer layer  21 A and a graphene layer  22 A. The buffer layer  21 A is a carbon atom layer including carbon atoms  24  bonded to silicon atoms  23  forming the first surface  12 A of the base portion  12 . In this embodiment, the buffer layer  21 A is disposed between the graphene layer  22 A and the first surface  12 A in the thickness direction. The graphene layer  22 A is disposed at the second main surface  13 A. For the stack  11  illustrated in  FIG. 3 , the number of atomic layers of the graphene layer  22 A is one. 
     For the stack  11  illustrated in  FIG. 3 , the buffer layer  21 A can be converted into a graphene layer, for example, by hydrogen intercalation.  FIG. 4  is a conceptual diagram illustrating the bonding state of the atoms after the conversion of the buffer layer  21 A into a graphene layer. Referring to  FIGS. 3 and 4 , when hydrogen atoms  25  are supplied between the first surface  12 A and the buffer layer  21 A, with the stack  11  being heated to a predetermined temperature, the bonds between the silicon atoms  23  and the carbon atoms  24  included in the buffer layer  21 A are broken, and the silicon atoms  23  bond to the hydrogen atoms  25  (see  FIG. 4 ). The buffer layer  21 A, which is a carbon atom layer including carbon atoms  24  having their bonds with the silicon atoms  23  broken, becomes a graphene layer  21 B. In the state illustrated in  FIG. 4 , the number of atomic layers of the graphene layers  22 A and  21 B is two. The number of atomic layers of the graphene layers  22 A and  21 B can be determined, for example, by observing a micrograph captured with magnification under an atomic force microscope (AFM). 
     The second main surface  13 A of the carbon atom thin film  13  includes a plurality of terraces and a plurality of steps.  FIG. 5  is a schematic sectional view schematically illustrating, in an enlarged view, a portion of the stack  11  including the second main surface  13 A illustrated in  FIG. 1 .  FIG. 6  is a micrograph, captured with magnification under an AFM, of a portion of the second main surface  13 A of the stack  11  illustrated in  FIG. 1 .  FIG. 6  is a view as viewed in the thickness direction of the carbon atom thin film  13 . 
     Referring to  FIGS. 5 and 6 , the second main surface  13 A of the carbon atom thin film  13  includes a plurality of terraces, specifically, a first terrace  26 A, a second terrace  26 B, and a third terrace  26 C, and a plurality of steps, specifically, a first step  27 A and a second step  27 B. The first terrace  26 A, the second terrace  26 B, and the third terrace  26 C are each parallel to the Si face of the silicon carbide forming the base portion  12 , i.e., the first surface  12 A. The first step  27 A connects the first terrace  26 A to the second terrace  26 B. The second step  27 B connects the first terrace  26 A to the third terrace  26 C. A step-terrace structure is formed on the second main surface  13 A of the carbon atom thin film  13 . 
     The first terrace  26 A has a width W 1  of 5 μm or more and 500 μm or less. Specifically, the first terrace  26 A has a width W 1  of more than 10 μm. Similarly, the other terraces, namely, the second terrace  26 B and the third terrace  26 C, have a width of 5 μm or more and 500 μm or less. The first step  27 A has a height H 1  of 10 nm or more and 500 nm or less. Similarly, the other step, namely, the second step  27 B, has a height of 10 nm or more and 500 nm or less. 
     According to this embodiment, the first terrace  26 A has a width W 1  of 5 μm or more and 500 μm or less. Because the first terrace  26 A has a width W 1  of 5 μm or more, a channel layer of a transistor can be easily formed in a region including the single first terrace  26 A. In addition, because the first terrace  26 A has a large width W 1 , a channel layer of a transistor can be formed with a reduced number of steps included in the channel layer. Thus, good modulation characteristics can be easily imparted to the manufactured transistor. On the other hand, if the first terrace  26 A has an excessive width W 1 , the first step  27 A consequently has an excessive height H 1 , and the carbon atom thin film  13  is likely to be broken in a region where the first step  27 A is located. Because the first terrace  26 A has a width W 1  of 500 μm or less, the likelihood of the carbon atom thin film  13  being broken can be reduced. To reduce the fabrication time and facilitate fabrication, the first terrace  26 A preferably has a width W 1  of 5 μm or more and 200 μm or less. To further reduce the fabrication time and facilitate fabrication, the first terrace  26 A preferably has a width W 1  of 5 μm or more and 100 μm or less. 
     Because the first step  27 A has a height H 1  of 10 nm or more, hydrogen gas easily passes through a region including the first step  27 A in the direction along the first terrace  26 A. Thus, hydrogen gas can be easily supplied to an interface Si between the Si face and the carbon atom thin film  13 . Accordingly, hydrogen gas treatment for breaking the bonds between the silicon atoms and the carbon atoms can be efficiently performed. On the other hand, if the first step  27 A has a height H 1  of more than 500 nm, the carbon atom thin film  13  is likely to be broken in the region including the first step  27 A. Because the first step  27 A has a height H 1  of 500 nm or less, the likelihood of the carbon atom thin film  13  being broken can be reduced. To reduce the fabrication time and facilitate fabrication, the first step  27 A preferably has a height H 1  of 10 nm or more and 200 nm or less. To further reduce the fabrication time and facilitate fabrication, the first step  27 A preferably has a height H 1  of 10 nm or more and 100 nm or less. 
     As described above, because the first terrace  26 A of the stack  11  according to this embodiment has a large width W 1 , and the buffer layer  21 A can be easily converted into the graphene layer  21 B by breaking the bonds between the silicon atoms and the carbon atoms, the modulation characteristics of a transistor serving as an electronic device can be improved. 
       FIG. 7  is a graph illustrating the relationship between drain voltage and drain current with varying gate voltages for a transistor manufactured using the stack  11  according to the first embodiment. In  FIG. 7 , the vertical axis includes the drain current (A), and the horizontal axis indicates the drain voltage (V). In  FIG. 7 , a line  28 A indicates a case where the gate voltage is 10 V; a line  28 B indicates a case where the gate voltage is 5 V; a line  28 C indicates a case where the gate voltage is 0 V; a line  28 D indicates a case where the gate voltage is −5 V; and a line  28 E indicates a case where the gate voltage is −10 V. 
     Referring to  FIG. 7 , the drain current that flows depending on the magnitude of the applied drain voltage changes as the gate voltage is varied from −10 V to 10 V in steps of 5 V. That is, the modulation characteristics are improved. 
     In the above embodiment, the number of atomic layers of the graphene layers  22 A and  21 B may be three or less. In this case, a stack  11  including a graphene layer that can stably ensure high carrier mobility can be obtained. 
       FIG. 8  is a schematic sectional view schematically illustrating, in an enlarged view, a portion of a stack outside the scope of the present disclosure. Referring to  FIG. 8 , a second main surface  33 A of a carbon atom thin film  33  included in a stack  31  includes a plurality of terraces, specifically, a first terrace  34 A, a second terrace  34 B, a third terrace  34 C, and a fourth terrace  34 D, and a plurality of steps, specifically, a first step  35 A, a second step  35 B, and a third step  35 C. The first terrace  34 A, the second terrace  34 B, the third terrace  34 C, and the fourth terrace  34 D are each parallel to a Si face of silicon carbide forming a base portion  32 , i.e., a first surface  32 A. The first step  35 A connects the first terrace  34 A to the second terrace  34 B. The second step  35 B connects the second terrace  34 B to the third terrace  34 C. The third step  35 C connects the third terrace  34 C to the fourth terrace  34 D. A step-terrace structure is formed on the second main surface  33 A of the carbon atom thin film  33 . 
     The first terrace  34 A has a width W 2  of about 2 μm, which is smaller than the width W 1  of the first terrace  26 A of the stack  11  according to the first embodiment described above. The other terraces also have a similar width, that is, a width smaller than the width W 1  of the first terrace  26 A. The first step  35 A has a height H 2  smaller than the height H 1  of the first step  27 A of the stack  11  according to the first embodiment described above. The other steps also have a similar height, that is, a height smaller than the height H 1  of the first step  27 A. 
     If such a stack  31  is used to manufacture a transistor, a large number of steps are included in the channel layer because the first terrace  34 A, the second terrace  34 B, the third terrace  34 C, and the fourth terrace  34 D are narrow. Thus, a transistor manufactured using such a stack  31  has poor modulation characteristics. In addition, because there is only a small interface S 2  between the Si face and the carbon atom thin film  33 , hydrogen gas is not easily supplied between the Si face and the carbon atom thin film  33 , and the buffer layer included in the carbon atom thin film  33  is not easily converted into a graphene layer. 
       FIG. 9  is a graph illustrating the relationship between drain voltage and drain current with varying gate voltages for a transistor manufactured using the stack  31  illustrated in  FIG. 8 . In  FIG. 9 , the vertical axis and the horizontal axis are the same as those in  FIG. 7 . In  FIG. 9 , a line  29 A indicates a case where the gate voltage is 10 V; a line  29 B indicates a case where the gate voltage is 5 V; a line  29 C indicates a case where the gate voltage is 0 V; a line  29 D indicates a case where the gate voltage is −5 V; and a line  29 E indicates a case where the gate voltage is −10 V. 
     Referring to  FIG. 9 , the line  29 A, the line  29 B, the line  29 C, the line  29 D, and the line  29 E almost overlap. That is, the drain current that flows depending on the magnitude of the applied drain voltage remains almost unchanged as the gate voltage is varied from −10 V to 5 V in steps of 5 V. An electronic device including such a stack  31  does not have good modulation characteristics. 
     Next, an outline of an example method for manufacturing the stack  11  according to the first embodiment will be described with reference to  FIGS. 10 to 12 . 
       FIG. 10  is a flowchart illustrating typical steps of the method for manufacturing the stack  11  according to the first embodiment. Referring to  FIG. 10 , in the method for manufacturing the stack  11  according to the first embodiment, a raw material substrate provision step is first performed as step (S 10 ).  FIG. 11  is a schematic sectional view for illustrating the method for manufacturing the stack  11 . Referring to  FIG. 11 , in this step (S 10 ), for example, a silicon carbide substrate  51  consisting of 6H-SiC and having a diameter of 2 inches (50.8 mm) is provided. Specifically, for example, the silicon carbide substrate  51  consisting of SiC is obtained by slicing an ingot consisting of SiC. The surface of the silicon carbide substrate  51  is polished and is then subjected to a process such as cleaning to ensure that the main surface has sufficient flatness and cleanliness. The silicon carbide substrate  51  has a first substrate surface  51 A. The first substrate surface  51 A is a Si face of the SiC forming the silicon carbide substrate  51 . 
     Next, a silicon carbide substrate placement step is performed as a step (S 20 ) of placing the silicon carbide substrate in a first space enclosed by a cover member disposed in a chamber. This step (S 20 ) can be performed, for example, using a heating device illustrated in  FIG. 12 .  FIG. 12  is a schematic sectional view illustrating the structure of the heating device. Referring to  FIG. 12 , a heating device  61  includes a chamber  62 , a susceptor  63 , a cover member  64 , a gas introduction pipe  65 , and an exhaust pipe  66 . 
     The chamber  62  includes a side wall portion  62 A having a hollow cylindrical shape, a bottom wall portion  62 B closing off a first end of the side wall portion  62 A, and an upper wall portion  62 C closing off a second end of the side wall portion  62 A. The susceptor  63  is disposed on the bottom wall portion  62 B inside the chamber  62 . The susceptor  63  has a substrate holding surface  63 A for holding the silicon carbide substrate  51 . 
     The cover member  64  for covering the susceptor  63  is disposed inside the chamber  62 . For example, the cover member  64  has a hollow cylindrical shape having one of its pair of ends closed off and the other end open. The cover member  64  is disposed such that the other end of the cover member  64  is in contact with the bottom wall portion  62 B. The susceptor  63  and the silicon carbide substrate  51  on the susceptor  63  are surrounded by the cover member  64  and the bottom wall portion  62 B of the chamber  62 . The susceptor  63  and the silicon carbide substrate  51  on the susceptor  63  are disposed in a first space  63 C that is a space surrounded by the cover member  64  and the bottom wall portion  62 B of the chamber  62 . The upper wall surface  64 A of the cover member  64  faces the first substrate surface  51 A of the silicon carbide substrate  51 . 
     Here, as a technique for obtaining the stack  11  according to the first embodiment described above, for example, silicon atoms are removed from the Si face by heating, with silicon disposed in the first space  63 C surrounded by the cover member  64 . As one specific example, silicon is deposited on the upper wall surface  64 A, facing the first substrate surface  51 A, and the side wall surface  64 B, facing the susceptor  63 , of the cover member  64 . That is, a silicon layer  67  serving as a first member including a material containing silicon atoms is disposed in the first space  63 C. More specifically, the silicon layer  67  is deposited on the upper wall surface  64 A and the side wall surface  64 B by vapor deposition. This reduces the speed at which silicon atoms are removed from the first substrate surface  51 A and thus allows the steps to recede by migration while leaving some of the ends of the steps, so that the stack  11  according to the first embodiment can be easily obtained. The positions at which the steps are located before receding and the direction in which the steps recede are indicated by the dashed line and the arrow Y in  FIG. 3 . 
     The gas introduction pipe  65  and the exhaust pipe  66  are connected to the upper wall portion  62 C of the chamber  62 . The gas introduction pipe  65  and the exhaust pipe  66  are each connected at one end to a through-hole formed in the upper wall portion  62 C. The other end of the gas introduction pipe  65  is connected to a gas reservoir (not illustrated) that holds an inert gas. In the first embodiment, argon is held in the gas reservoir. The other end of the exhaust pipe  66  is connected to an exhaust device (not illustrated) such as a pump. 
     Step (S 20 ) can be performed using the heating device  61  as follows. The silicon carbide substrate  51  provided in step (S 10 ) is first placed on the substrate holding surface  63 A of the susceptor  63 . Next, the cover member  64  is placed on the bottom wall portion  62 B so as to cover the susceptor  63  and the silicon carbide substrate  51  in step (S 20 ). Thus, the susceptor  63  and the silicon carbide substrate  51  on the susceptor  63  are surrounded by the cover member  64  and the bottom wall portion  62 B of the chamber  62  and are placed in the first space  63 C. 
     Next, while a valve (not illustrated) attached to the gas introduction pipe  65  is closed, a valve (not illustrated) attached to the exhaust pipe  66  is opened. The exhaust device connected to the exhaust pipe  66  is then operated to discharge gas inside the chamber  62  from the exhaust pipe  66  along the arrow F 2 . Thus, the pressure inside the chamber  62  is reduced. Here, although the susceptor  63  and the silicon carbide substrate  51  are surrounded by the cover member  64  and the bottom wall portion  62 B of the chamber  62 , the cover member  64  and the bottom wall portion  62 B are not joined together. Therefore, as the pressure inside the chamber  62  is reduced, gas inside the first space  63 C is discharged from a slight gap between the cover member  64  and the bottom wall portion  62 B due to the pressure difference between the inside and outside of the first space  63 C. As a result, the pressure in the first space  63 C is also reduced. 
     Next, the operation of the exhaust device is stopped, and the valve attached to the gas introduction pipe  65  is opened. Thus, argon held in the gas reservoir flows through the gas introduction pipe  65  and is introduced into the chamber  62  along the arrow F 1 . Here, as the pressure in the chamber  62  increases, argon enters the first space  63 C through the slight gap between the cover member  64  and the bottom wall portion  62 B due to the pressure difference between the inside and outside of the first space  63 C. In this way, the gas inside the chamber  62  is replaced by argon. When the argon pressure inside the chamber  62  increases to normal pressure (atmospheric pressure), excess argon is discharged from the exhaust pipe  66 , thus maintaining the inside pressure at normal pressure. That is, an argon atmosphere at normal pressure is maintained inside the chamber  62 . 
     Next, a conversion step is performed as a step (S 30 ) of heating the silicon carbide substrate in the first space to remove silicon atoms from a first region including the first substrate surface, thereby converting the first region into at least one of a buffer layer that is a carbon atom layer including carbon atoms bonded to silicon atoms forming the silicon carbide substrate and a graphene layer. In this step, the silicon carbide substrate  51  is heated. For example, the silicon carbide substrate  51  is heated by heating the chamber  62 . The chamber  62  may be heated, for example, by induction heating. For example, the silicon carbide substrate  51  is heated to a temperature of 1,300° C. or higher and 1,800° C. or lower in argon at normal pressure. As specific conditions for heating treatment, for example, the silicon carbide substrate  51  may be heated at 1,800° C. for 10 minutes. Thus, referring to  FIG. 11 , silicon atoms are removed from the first substrate surface  51 A side of the silicon carbide substrate  51  consisting of SiC, thereby converting the surface layer portion including the first substrate surface  51 A into a carbon atom thin film. 
     In this way, referring to  FIG. 1 , the stack  11  including the base portion  12  consisting of SiC and the carbon atom thin film  13  disposed on the first surface  12 A of the base portion  12  is obtained. 
     Thus, silicon atoms can be supplied from the silicon layer  67  serving as the first member to the first space  63 C enclosed by the cover member  64  to increase the concentration of silicon atoms in the first space  63 C. When silicon atoms are removed from the first region including the first substrate surface  51 A, the surface diffusion of carbon atoms and silicon atoms in the first region can be promoted. Therefore, when the first region is converted into at least one of a buffer layer and a graphene layer, the terrace width of the first surface can be easily increased, and the step height of the first surface can be easily increased. Thus, a stack having a large terrace width and a large step height can be easily obtained. 
     The thus-obtained stack  11  has good adhesion between the carbon atom thin film  13  and the base portion  12  consisting of SiC. In addition, the carbon atom thin film  13  can be formed over the entire surface of the silicon carbide substrate  51 . Thus, the stack  11  is suitable for manufacture of electronic devices that require suitability for mass production, such as transistors. 
     In the above embodiment, a silicon layer serving as a first member is deposited on the upper wall surface  64 A and the side wall surface  64 B, facing the susceptor  63 , of the cover member  64 ; however, the embodiment is not limited thereto, and elemental silicon may be disposed as a first member in the first space  63 C enclosed by the cover member  64 . For example, silicon may be disposed so as to be placed on the bottom wall portion  62 B in the first space  63 C enclosed by the cover member  64 . 
     Second Embodiment 
     Next, a field-effect transistor (FET) will be described as an example of an electronic device fabricated using the stack  11  according to the first embodiment described above.  FIG. 13  is a schematic sectional view of a FET according to a second embodiment. Referring to  FIG. 13 , a FET  15  according to the second embodiment is fabricated using the stack  11  according to the first embodiment described above. The FET  15  includes the stack  11  including the base portion  12  and the carbon atom thin film  13  stacked in the same manner as in the first embodiment. The carbon atom thin film  13  includes a graphene layer. The FET  15  further includes a source electrode  16 , serving as a first electrode, a drain electrode  17  disposed away from the source electrode  16 , serving as a second electrode, a gate electrode  18  disposed away from the source electrode  16  and the drain electrode  17 , serving as a third electrode, and a gate insulating film  19 . 
     The source electrode  16  is formed in contact with the second main surface  13 A. Specifically, for example, the source electrode  16  is formed on the first terrace  26 A. The source electrode  16  consists of a conductor capable of ohmic contact with the carbon atom thin film  13 , for example, nickel (Ni)/gold (Au). The drain electrode  17  is formed in contact with the second main surface  13 A. The drain electrode  17  consists of a conductor capable of ohmic contact with the carbon atom thin film  13 , for example, Ni/Au. The drain electrode  17  is also formed on the first terrace  26 A. 
     The gate electrode  18  is formed so as to cover the portion of the second main surface  13 A of the carbon atom thin film  13  located between the source electrode  16  and the drain electrode  17 . The gate insulating film  19  covers the portion of the second main surface  13 A located between the source electrode  16  and the drain electrode  17  and extends to regions covering portions of the upper surfaces of the source electrode  16  and the drain electrode  17  (main surfaces on the opposite side from the side in contact with the carbon atom thin film  13 ). The gate insulating film  19  consists of, for example, an insulator such as silicon nitride (SiN) or aluminum oxide (Al 2 O 3 ). 
     The gate electrode  18  is disposed in contact with the gate insulating film  19 . The gate electrode  18  is disposed in a region corresponding to the portion of the second main surface  13 A located between the source electrode  16  and the drain electrode  17 . The gate electrode  18  consists of a conductor, for example, Ni/Au. 
     In this FET  15 , when the voltage applied to the gate electrode  18  is lower than a threshold voltage, that is, when the FET  15  is off, an insufficient number of electrons serving as carriers are present in the portion (channel region) of the carbon atom thin film  13  located between the source electrode  16  and the drain electrode  17 ; therefore, the channel region remains nonconducting when a voltage is applied between the source electrode  16  and the drain electrode  17 . On the other hand, when a voltage of not lower than the threshold voltage is applied to the gate electrode  18  so that the FET  15  turns on, electrons serving as carriers are generated in the channel region. As a result, the source electrode  16  and the drain electrode  17  are electrically connected together via the channel region in which electrons serving as carriers have been generated. When a voltage is applied between the source electrode  16  and the drain electrode  17  in this state, a current flows between the source electrode  16  and the drain electrode  17 . 
     Here, in the FET  15  according to the second embodiment, the source electrode  16  and the drain electrode  17  are formed on the second main surface  13 A of the stack  11  described above in the first embodiment. The FET  15 , including such a stack  11 , exhibits improved modulation characteristics. In particular, the modulation characteristics of the FET  15  are further improved because the source electrode  16  and the drain electrode  17  are disposed on the first terrace  26 A among the plurality of terraces. 
     Next, referring to  FIGS. 1 and 14 , a method for manufacturing the FET  15  according to the second embodiment will be described.  FIG. 14  is a flowchart illustrating typical steps of the method for manufacturing the FET  15  including the carbon atom thin film. Referring to  FIG. 14 , in the method for manufacturing the FET  15  according to the second embodiment, a stack provision step is first performed as step (S 110 ). In this step (S 110 ), the stack  11  according to the first embodiment described above is provided (see  FIG. 1 ). The stack  11  can be manufactured by the method of manufacture described above in the first embodiment. 
     Next, referring to  FIG. 14 , an ohmic electrode formation step is performed as step (S 120 ). In this step (S 120 ), referring to  FIGS. 1 and 15 , the source electrode  16  and the drain electrode  17  are formed in contact with the second main surface  13 A of the stack  11 . For example, the source electrode  16  and the drain electrode  17  can be formed on the second main surface  13 A of the carbon atom thin film  13  by forming a mask layer consisting of a resist having openings corresponding to the regions where the source electrode  16  and drain electrode  17  are to be formed, forming a conductive film consisting of the conductor (e.g., Ni/Au) forming the source electrode  16  and the drain electrode  17 , and then performing a lift-off process. 
     Next, referring to  FIG. 14 , an insulating film formation step is performed as step (S 130 ). In this step (S 130 ), referring to  FIGS. 15 and 16 , an insulating film  20  is formed so as to cover the portion of the second main surface  13 A of the carbon atom thin film  13  located between the source electrode  16  and the drain electrode  17 , the main surface of the source electrode  16  on the opposite side from the stack  11 , and the main surface of the drain electrode  17  on the opposite side from stack  11 . The insulating film  20  can be formed, for example, by a CVD process. The material used to form the insulating film  20  may be, for example, silicon nitride (SiN). 
     Next, referring to  FIG. 10 , a gate electrode formation step is performed as step (S 140 ). In this step (S 140 ), referring to  FIGS. 12 and 13 , the gate electrode  18  is formed in contact with the portion of the insulating film  20  covering the portion of the second main surface  13 A located between the source electrode  16  and the drain electrode  17 . For example, the gate electrode  18  can be formed by forming a mask layer consisting of a resist having an opening corresponding to the region where the gate electrode  18  is to be formed, forming a conductive film consisting of the conductor (e.g., Ni/Au) forming the gate electrode  18 , and then performing a lift-off process. 
     Next, referring to  FIG. 13 , a contact hole formation step is performed as step (S 150 ). In this step (S 150 ), referring to  FIGS. 17 and 13 , contact holes for allowing contact of the source electrode  16  and the drain electrode  17  with wiring are formed by removing portions of the insulating film  20  located on the source electrode  16  and the drain electrode  17 . Specifically, for example, a mask having openings in regions corresponding to the source electrode  16  and the drain electrode  17  is formed, and the portions of the insulating film  20  exposed from the openings are removed by etching. Thus, contact holes are formed, and the remaining insulating film  20  becomes the gate insulating film  19 . The gate insulating film  19  covers the portion of the second main surface  13 A located between the source electrode  16  and the drain electrode  17  and extends to regions covering portions of the upper surfaces of the source electrode  16  and the drain electrode  17  (main surfaces on the opposite side from the side in contact with the carbon atom thin film  13 ). 
     By the above steps, the FET  15  according to the second embodiment is finished. Thereafter, for example, wiring is formed, and the individual electronic devices are separated by dicing. 
     It should be understood that the embodiments disclosed herein are illustrative in all respects and not restrictive in any way. The scope of the present disclosure is defined by the claims, rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein. 
     REFERENCE SIGNS LIST 
     
         
         
           
               11 ,  31  stack 
               12 ,  32  base portion 
               12 A,  32 A first surface 
               13 ,  33  carbon atom thin film 
               13 A,  33 A second main surface 
               13 B first main surface 
               15  FET 
               16  source electrode 
               17  drain electrode 
               18  gate electrode 
               19  gate insulating film 
               20  insulating film 
               21 A buffer layer 
               21 B,  22 A graphene layer 
               23  silicon atom 
               24  carbon atom 
               25  hydrogen atom 
               26 A,  34 A first terrace 
               26 B,  34 B second terrace 
               26 C,  34 C third terrace 
               27 A,  35 A first step 
               27 B,  35 B second step 
               28 A,  28 B,  28 C,  28 D,  28 E,  29 A,  29 B,  29 C,  29 D,  29 E line 
               34 D fourth terrace 
               35 C third step 
               51  silicon carbide substrate 
               51 A first substrate surface 
               61  heating device 
               62  chamber 
               62 A side wall portion 
               62 B bottom wall portion 
               62 C upper wall portion 
               63  susceptor 
               63 A substrate holding surface 
               63 C first space 
               64  cover member 
               64 A upper wall surface 
               64 B side wall surface 
               65  gas introduction pipe 
               66  exhaust pipe 
               67  silicon layer (first member) 
             L diameter 
             T, Y, F 1 , F 2  arrow 
             H 1 , H 2  height 
             S 1 , S 2  interface 
             W 1 , W 2  width 
             S 10 , S 20 , S 30 , S 110 , S 120 , S 130 , S 140 , S 150  step