Patent Publication Number: US-7723802-B2

Title: Semiconductor device

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a semiconductor device such as an integrated gate bipolar transistor (IGBT) and an integrated circuit (IC) with a built-in IGBT. 
   2. Description of the Background Art 
   Generally, the equivalent circuit of a collector-shorted IGBT is structured such that the base and emitter of a PNP transistor, between which the drain and source of an N-channel MOSFET are connected, are short-circuited via a resistance (first conventional example). 
   In order to turn on the IGBT of this kind, when the collector of the IGBT (the emitter of the PNP transistor) is at a higher potential than the emitter of the IGBT (the source of the N-channel MOSFET), a predetermined positive voltage is applied to the gate of the IGBT (the gate of the N-channel MOSFET). Thereby, the N-channel MOSFET is turned on, whereby electrons are injected from the emitter of the IGBT through the N-channel MOSFET into the base of the PNP transistor, and holes are injected from the collector of the IGBT through the emitter of the PNP transistor into the base of the PNP transistor. This electron and hole injection causes conductivity modulation of the PNP transistor and reduces the turn-on voltage of the PNP transistor, thereby turning on the PNP transistor. 
   On the other hand, in order to turn off the IGBT of this kind, the application of a predetermined positive voltage to the gate of the IGBT is terminated. This stops the electron and hole injection into the PNP transistor, thereby decreasing electron and hole densities in the PNP transistor and increasing the turn-on voltage of the PNP transistor. Accordingly, the PNP transistor is turned off. 
   When the emitter of the IGBT is at a higher potential than the collector of the IGBT, the IGBT of this kind conducts current from its emitter to collector through a parasitic diode in the N-channel MOSFET and through the resistance between the base and emitter of the PNP transistor (reverse conducting capability). This reverse conducting capability is essential when the IGBT is adopted as an inductance load. 
   In the case where an IGBT with no reverse conducting capability (i.e., non-collector-shorted IGBT) is adopted as an inductance load, an external diode needs to be connected in reverse parallel between the collector and emitter of the IGBT (second conventional example). 
   Such conventional examples can be found in conventional art, for example in Japanese Patent Application Laid-open No. 9-82961 (1997). 
   The first conventional example given above has the disadvantage that a higher value of the resistance between the base and emitter of the PNP transistor results in a higher conducting resistance during reverse conduction and thus inhibits the reverse conducting capability. 
   On the other hand, a lower value of the resistance, during turn-on of the IGBT, disadvantageously causes both electrons from the emitter side of the IGBT and holes from the collector side of the IGBT to flow into the resistance without flowing into the base of the PNP transistor. This makes the electron and hole injection into the PNP transistor difficult and slows down the drop in the turn-on voltage of the PNP transistor, thereby delaying the turning on of the IGBT. 
   On the contrary, a lower value of the resistance, during turn-off of the IGBT, advantageously causes electrons and holes, which are accumulated in the base of the PNP transistor, to be emitted more quickly from the base of the PNP transistor through the resistance. This results in a rapid drop in the turn-on voltage of the PNP transistor, thereby speeding up the turning off of the IGBT. 
   The second conventional example given above has a disadvantage of higher cost because it requires an external diode whose breakdown voltage and operating current need to be equivalent to those of the IGBT and thus which is about the same size as the IGBT. 
   SUMMARY OF THE INVENTION 
   An object of the present invention is to provide a semiconductor device which can simultaneously improve the operation and the reverse conducting capability of an IGBT. 
   According to the present invention, a semiconductor device includes a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type; first and second semiconductor regions of the first conductivity type; a third semiconductor region of the second conductivity type; a first gate electrode; a first collector electrode; an emitter electrode; a fourth semiconductor region of the first conductivity type; a fifth semiconductor region of the second conductivity type; a second collector electrode; and an electrode. The semiconductor layer is formed on one main surface of the semiconductor substrate. The first semiconductor region is formed in a surface of the semiconductor layer and connected to the semiconductor substrate through a semiconductor region of the first conductivity type. The second semiconductor region is formed in the surface of the semiconductor layer apart from the first semiconductor region. The third semiconductor region is formed in a surface of the first semiconductor region so as to be surrounded by the first semiconductor region. The first gate electrode is provided on a surface portion of the first semiconductor region which is sandwiched between the third semiconductor region and the semiconductor layer, with a first gate insulating film in between. The first collector electrode is provided on the second semiconductor region. The emitter electrode is provided on and extends through the first and third semiconductor regions. The fourth semiconductor region is formed in the surface of the semiconductor layer apart from the first and second semiconductor regions. The fifth semiconductor region is formed in a surface of the fourth semiconductor region so as to be surrounded by the fourth semiconductor region. The second collector electrode is provided on the fifth semiconductor region and connected to the first collector electrode. The electrode is provided on and extends through the fourth semiconductor region and the semiconductor layer to form a conducting path from the semiconductor layer to the fourth semiconductor region. 
   The fourth semiconductor region is formed in the surface of the semiconductor layer; the fifth semiconductor region is formed in the surface of the fourth semiconductor region so as to be surrounded by the fourth semiconductor region; and the second collector electrode connected to the first collector electrode is provided on the fifth semiconductor region. Thus, a diode consisting of the fourth and fifth semiconductor regions can prevent electrons, which are injected from the emitter electrode side into the semiconductor layer during turn-on of the semiconductor device, from outflowing from the semiconductor layer into the second collector electrode. Correspondingly, more electrons and holes can be accumulated quickly in the semiconductor layer, which contributes to the conductivity modulation of the semiconductor layer and allows the quick turning on of the semiconductor device. 
   Further, since the fourth semiconductor region is formed in the surface of the semiconductor layer, and the fifth semiconductor region is formed in the surface of the fourth semiconductor region so as to be surrounded by the fourth semiconductor region, a parasitic thyristor consisting of those fourth and fifth semiconductor regions, the semiconductor layer, and the semiconductor substrate can be formed on a reverse conducting path. Thus, by utilizing a low conducting resistance during the on-state of the parasitic thyristor, the semiconductor device can achieve a reverse conducting capability with low reverse conducting resistance. 
   Furthermore, since the electrode is provided on and extends through the fourth semiconductor region and the semiconductor layer to form a conducting path from the semiconductor layer to the fourth semiconductor region, the passage of current from the semiconductor layer to the fourth semiconductor region can be ensured during reverse conduction of the semiconductor device. This stabilizes the turning on of the parasitic thyristor. 
   These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a cross-sectional view of a semiconductor device according to a first preferred embodiment; 
       FIG. 2  is an equivalent circuit diagram of the semiconductor device  1   n    FIG. 1 ; 
       FIG. 3  is a cross-sectional view of a semiconductor device according to a second preferred embodiment; 
       FIG. 4  is a cross-sectional view of a semiconductor device according to a third preferred embodiment; 
       FIG. 5  is an equivalent circuit diagram of the semiconductor device  1   n    FIG. 4 ; 
       FIG. 6  is a cross-sectional view of a semiconductor device according to a fourth preferred embodiment; 
       FIG. 7  is an equivalent circuit diagram of the semiconductor device shown in  FIG. 6 ; 
       FIG. 8  is a cross-sectional view of a semiconductor device according to a fifth preferred embodiment; 
       FIG. 9  is a cross-sectional view of a semiconductor device according to a sixth preferred embodiment; 
       FIG. 10  is a cross-sectional view of a semiconductor device according to a seventh preferred embodiment; 
       FIG. 11  is a cross-sectional view of a semiconductor device according to an eighth preferred embodiment; and 
       FIG. 12  is a cross-sectional view of a semiconductor device according to a ninth preferred embodiment. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   First Preferred Embodiment 
   A semiconductor device  1 A according to this preferred embodiment is a lateral collector-shorted IGBT. It includes, as shown in  FIG. 1 , a P −  substrate  3  (semiconductor substrate of a first conductivity type); an N −  epitaxial layer  5  (semiconductor layer of a second conductivity type) formed on one main surface of the P +  substrate  3 ; a P diffusion region  9  (first semiconductor region of the first conductivity type) formed in the surface of the N −  epitaxial layer  5  and connected to the P +  substrate  3  through a P diffusion region  7  (semiconductor region of the first conductivity type); a P diffusion region  11  (second semiconductor region of the first conductivity type) formed in the surface of the N −  epitaxial layer  5  apart from the P diffusion region  9 ; an N +  diffusion region  13  (third semiconductor region of the second conductivity type) formed in the surface of the P diffusion region  9  so as to be surrounded by the P diffusion region  9 ; a first gate electrode  17  provided on a surface portion of the P diffusion region  9  which is sandwiched between the N +  diffusion region  13  and the N −  epitaxial layer  5 , with a first gate insulating film  15  in between; a first collector electrode  19   a  provided on the P diffusion region  11 ; and an emitter electrode  21  provided on and extending through the P diffusion region  9  and the N +  diffusion region  13 . In addition to this fundamental structure, the semiconductor device  1 A further includes a P diffusion region  23  (fourth semiconductor region of the first conductivity type) formed in the surface of the N −  epitaxial layer  5  apart from the P diffusion regions  9  and  11 ; an N +  diffusion region  25  (fifth semiconductor region of the second conductivity type) formed in the surface of the P diffusion region  23  so as to be surrounded by the P diffusion region  23 ; a second collector electrode  19   b  provided on the N +  diffusion region  25  and connected to the first collector electrode  19   a ; and an electrode  27  provided on and extending through the P diffusion region  23  and the N −  epitaxial layer  5  to form a conducting path from the N −  epitaxial layer  5  to the P diffusion region  23 . In this preferred embodiment, the electrode  27  is provided on the N −  epitaxial layer  5  with an N +  diffusion region  29  formed in the surface of the N −  epitaxial layer  5  in between, so as to form an ohmic contact with the N −  epitaxial layer  5 . 
   The first gate electrode  17  is connected to a gate terminal Tg, the first and second collector electrodes  19   a  and  19   b  in common to a collector terminal Tc, and the emitter electrode  21  to an emitter terminal Te. 
   The P diffusion regions  7  and  9  are located on one end h 1  of the N −  epitaxial layer  5 , the P diffusion region  11  is located in about a central portion of the N −  epitaxial layer  5 , and the P diffusion region  23  is located on the other end h 2  of the N −  epitaxial layer  5 . The N +  diffusion region  29  is located adjacent to the side of the P diffusion region  23  on the other end h 2  side of the N −  epitaxial layer  5 . 
   The semiconductor device  1 A, as a whole, is of a circular structure, which can be obtained by rotation of the cross section of  FIG. 1  about the other end h 2  of the N −  epitaxial layer  5 . 
   The equivalent circuit of the semiconductor device  1 A is, as shown in  FIG. 2 , such that a PNP transistor Tr 1  is inserted and connected between the collector terminal Tc and the emitter terminal Te; a diode D 1  is connected in reverse parallel between the base and emitter of the PNP transistor Tr 1 ; the drain and source of an N-channel MOSFET Q 1  are connected between the base and collector of the PNP transistor Tr 1 . A diode D 2  is a parasitic diode in the N-channel MOSFET Q 1 . 
   The PNP transistor Tr 1 , when viewed in  FIG. 1 , has its emitter formed of the P diffusion region  11 , its base formed of the N −  epitaxial layer  5 , and its collector formed of the P +  substrate  3  and the P diffusion regions  7  and  9 . The diode D 1 , when viewed in  FIG. 1 , has its cathode formed of the N +  diffusion region  25  and its anode formed of the P diffusion region  23 . The N-channel MOSFET Q 1 , when viewed in  FIG. 1 , has its well formed of the P diffusion regions  7  and  9  and the P +  substrate  3 , its drain formed of the N −  epitaxial layer  5 , its source formed of the N +  diffusion region  13 , its gate insulating film formed of the first gate insulating film  15 , and its gate electrode formed of the first gate electrode  17 . The parasitic diode D 2 , when viewed in  FIG. 1 , has its anode formed of the P diffusion regions  7  and  9  and the P +  substrate  3  and its cathode formed of the N −  epitaxial layer  5 . In this preferred embodiment, the diodes D 1  and D 2  (i.e., the components  25 ,  23 ,  5 ,  3 ,  7 , and  9  in  FIG. 1 ) form an NPNP parasitic thyristor. 
   Next, the operation of the semiconductor device  1 A is described with reference to  FIGS. 1 and 2 . 
   In order to turn on this semiconductor device (IGBT)  1 A, when the collector terminal Tc is at a higher potential than the emitter terminal Te, a predetermined positive voltage is applied to the gate terminal Tg. This creates an inversion layer in a surface portion S 1  of the P diffusion region  9  which is located directly below the first gate electrode  17 , and causes electron injection from the emitter terminal Te, through the components  21 ,  13 , and S 1  into the N −  epitaxial layer  5  (this electron flow is from the emitter terminal Te through the diode D 2  into the base of the PNP transistor Tr 1  in  FIG. 2 ). Along with this electron injection, in order to ensure charge neutrality of the N −  epitaxial layer  5 , holes are injected from the collector terminal Tc through the components  19   a  and  11  into the N −  epitaxial layer  5  (this hole flow is from the collector terminal Tc through the emitter of the PNP transistor Tr 1  into the base of the PNP transistor Tr 1  in  FIG. 2 ). The electron and hole injection increases the conductivity of the N −  epitaxial layer  5  (i.e., causes conductivity modulation) and reduces the turn-on voltage of the PNP transistor Tr 1  consisting of the components  11 ,  5 ,  3 ,  7 , and  9 , thereby turning on the PNP transistor Tr 1  (i.e., the semiconductor device  1 A is turned on). By this turning on, current will flow from the collector terminal Tc through the components  19   a ,  11 , and  5 , through the component(s)  3  and/or  7  and/or  9 , and through the component  21 , in sequence, into the emitter terminal Te (this current flow is from the collector terminal Tc through the PNP transistor Tr 1  into the emitter terminal Te in  FIG. 2 ). 
   At this time, the diode D 1  consisting of the components  23  and  25  prevents the electrons, which are injected in the N −  epitaxial layer  5 , from outflowing from the N −  epitaxial layer  5  through the collector electrode  19   b  into the collector terminal Tc. Correspondingly, more electrons and holes are accumulated quickly in the N −  epitaxial layer  5 , which contributes to the conductivity modulation of the N −  epitaxial layer  5  and allows the quick turning on of the semiconductor device  1 A (with a turn-on speed equivalent to that of a non-collector-shorted IGBT). 
   On the other hand, in order to turn off the semiconductor device (IGBT)  1 A, the application of a predetermined positive voltage to the gate terminal Tg is terminated. This eliminates the inversion layer in the surface portion S 1  of the P diffusion region  9  and stops the electron injection from the emitter terminal Te through the inversion layer into the N −  epitaxial layer  5  as well as the hole injection from the collector terminal Tc into the N −  epitaxial layer  5 . This gradually reduces the conductivity modulation of the N −  epitaxial layer  5  caused by the electron and hole injection and increases the turn-on voltage of the PNP transistor Tr 1  consisting of the components  11 ,  5 ,  3 ,  7 , and  9 , thereby turning off the PNP transistor Tr 1  (i.e., the semiconductor device  1 A is turned off). By this turning off, current will stop flowing from the collector terminal Tc through the components  19   a ,  11 , and  5 , through the component(s)  3  and/or  7  and/or  9 , and through the component  21 , in sequence, into the emitter terminal Te. 
   When the emitter terminal Te is at a higher potential than the collector terminal Tc, initially a reverse current flows from the emitter terminal Te through the component  21 , through the component(s)  9  and/or  7  and/or  3 , through the components  5 ,  29 ,  27 ,  23 ,  25 , and  19   b  into the collector terminal Tc (this reverse current flow is from the emitter terminal Te through the diodes D 2  and D 1  into the collector terminal Tc in  FIG. 2 ). Thereby, the NPNP parasitic thyristor consisting of the components  25 ,  23 ,  5 ,  3 ,  7 , and  9  (the thyristor consisting of the diodes D 1  and D 2  in  FIG. 2 ) is turned on. By this turning on, the above reverse current flow ultimately becomes the flow from the emitter terminal Te through the component  21 , through the component(s)  9  and/or  7  and/or  3 , and through the components  5 ,  23 ,  25 , and  19   b  into the collector terminal Tc (this reverse current flow is from the emitter terminal Te through the diodes D 2  and D 1  into the collector terminal Tc in  FIG. 2 ). Since the components  25 ,  23 ,  5 , and  3  each have a low conducting resistance during the on-state of the parasitic thyristor, the ultimate reverse current can flow from the emitter terminal Te into the collector terminal Tc with little influence from the conducting resistance. This achieves the reverse conducting capability with low reverse conducting resistance. 
   In the semiconductor device  1 A of the above structure, the P diffusion region  23  is formed in the surface of the N −  epitaxial layer  5 ; the N +  diffusion region  25  is formed in the surface of the P diffusion region  23  so as to be surrounded by the P diffusion region  23 ; and the second collector electrode  19   b  connected to the first collector electrode  19   a  is formed on the N +  diffusion region  25 . Thus, the diode D 1  consisting of the components  23  and  25  can prevent electrons, which are injected from the emitter electrode  21  into the N −  epitaxial layer  5  during the on-state of the semiconductor device  1 A, from outflowing from the N −  epitaxial layer  5  into the second collector electrode  19   b . Correspondingly, more electrons and holes can be accumulated quickly in the N −  epitaxial layer  5 , which contributes to the conductivity modulation of the N −  epitaxial layer  5  and allows the quick turning on of the semiconductor device  1 A. 
   Further, since the P diffusion region  23  is formed in the surface of the N −  epitaxial layer  5  and the N +  diffusion region  25  is formed in the surface of the P diffusion region  23  so as to be surrounded by the P diffusion region  23 , a parasitic thyristor consisting of those components  23  and  25  and of the existing components  5 ,  3 ,  7 , and  9  can be formed on the reverse conducting path (from the emitter terminal Te through the component  21 , through the component(s)  9  and/or  7  and/or  3 , and through the components  5 ,  23 ,  25 , and  19   b  to the collector terminal Tc). Thus, by utilizing a low conducting resistance during the on-state of the parasitic thyristor, the semiconductor device  1 A can achieve the reverse conductivity capability with low reverse conducting resistance. 
   Further, since the electrode  27  is provided on and extends through the P diffusion region  23  and the N −  epitaxial layer  5  to form a conducting path from the N −  epitaxial layer  5  to the P diffusion region  23 , the passage of current from the N −  epitaxial layer  5  to the P diffusion region  23  can be ensured during reverse conduction of the semiconductor device  1 A. This stabilizes the turning on of the parasitic thyristor. Since, in this preferred embodiment, the electrode  27  is provided on the N −  epitaxial layer  5  with the N +  diffusion region  29  in between, a good electrical connection can be ensured between the electrode  27  and the N −  epitaxial layer  5 . 
   Furthermore, the semiconductor device  1 A can be constructed at low cost because the diode D 1  for reverse conduction is not an external device. 
   While in this preferred embodiment, the P diffusion region  9  is formed on the one end h 1  of the N −  epitaxial layer  5 ; the P diffusion region  11  is formed in the central portion of the N −  epitaxial layer  5 ; and the P diffusion region  25  and the N +  diffusion region  29  are formed on the other end h 2  of the N −  epitaxial layer  5 , the structure may be such that the P diffusion regions  9  and  11  are formed on the one end h 1  of the N −  epitaxial layer  5 ; and the P diffusion region  25  and the N +  diffusion region  29  are formed in the central portion of the N −  epitaxial layer  5 . This shortens the interval between the P diffusion region  9  and the N +  diffusion region  29  and accordingly reduces a conduction distance in the N −  epitaxial layer  5  during reverse conduction (from the emitter terminal Te through the component  21 , through the component(s)  9  and/or  7  and/or  3 , and through the components  5 ,  29 ,  27 ,  23 ,  25 , and  19   b  into the collector terminal Tc), thereby achieving the reverse conducting capability with lower reverse conducting resistance. 
   Second Preferred Embodiment 
   A semiconductor device  1 B according to this preferred embodiment is, as shown in  FIG. 3 , constructed such that in the aforementioned first preferred embodiment, an N diffusion region (semiconductor region of the second conductivity type)  35  having a higher carrier density than the N −  epitaxial layer  5  is further formed between the N −  epitaxial layer  5  (semiconductor layer) and the P diffusion region  23  (fourth semiconductor region) to surround the P diffusion region  23 . 
   In the semiconductor device  1 A of the aforementioned first preferred embodiment, with reference to  FIGS. 1 and 2 , the formation of the diode D 1  consisting of the components  23  and  25  for reverse conduction in the N −  epitaxial layer  5  creates a parasitic PNP transistor whose emitter, base, and collector are formed respectively of the components  11 ,  5 , and  23  (a dotted line  55  in  FIG. 2  indicates the collector of this parasitic PNP transistor). When the collector terminal Tc is at a higher potential than the emitter terminal Te, a forward bias is applied to turn on this parasitic PNP transistor. By this turning on, some holes flowing from the collector terminal Tc through the electrode  19   a  into the P diffusion region  11  will flow into the electrode  27  through the components  11 ,  5 ,  23  of the parasitic PNP transistor. Those holes will then disappear in the electrode  27  after being recombined with electrons which have flown from the emitter terminal Te through the components  21 ,  13 , S 1 ,  5 , and  29  into the electrode  27 . This hinders, in the semiconductor device  1 A, the accumulation of holes from the collector terminal Tc and electrons from the emitter terminal Te in the N −  epitaxial layer S and causes insufficient conductivity modulation of the N −  epitaxial layer  5 , thereby slowing the turning on of the transistor Tn consisting of the components  11 ,  5 , and  3 . On the other hand, in this preferred embodiment, as shown in  FIG. 3 , the presence of the N diffusion region  35  cuts off the flow of holes in the components  11 ,  5 , and  23  and prevents the disappearance of holes described above, thus allowing the quick turning on of the transistor Tn. 
   Accordingly, the semiconductor device  1 B of the above structure can, in addition to achieving the aforementioned effect of the first preferred embodiment, also improve the turn-on behavior of the transistor Tr 1  with a simple structure, since the N diffusion region  35  with a higher carrier density than the N −  epitaxial layer  5  is formed between the N −  epitaxial layer  5  and the P diffusion region  23  to surround the P diffusion region  23 . 
   Third Preferred Embodiment 
   A semiconductor device  10  according to this preferred embodiment is, as shown in  FIG. 4 , constructed such that in the aforementioned first preferred embodiment, a second gate electrode  41  is further provided on a surface portion of the N −  epitaxial layer  5  (semiconductor layer) which is sandwiched between the P diffusion regions  11  and  23  (second and fourth semiconductor regions), with a second gate insulating film  39  in between; and a second gate terminal Tg 2  is connected to the second gate electrode  41 . That is, this semiconductor device IC is such that a P-channel MOSFET Q 2  (see  FIG. 5 ) whose drain and source are formed respectively of the P diffusion regions  11  and  23  is further added to the aforementioned first preferred embodiment. 
   Here, the second gate insulating film  39  is formed to approximately a thickness of field oxide film so that the semiconductor device  1 C can withstand high voltage. 
   The equivalent circuit of the semiconductor device  1 C is, as shown in  FIG. 5 , a circuit in which the above P-channel MOSFET Q 2  is added to the equivalent circuit of the aforementioned first preferred embodiment ( FIG. 2 ) in such a way that the diode D 1  is connected in parallel between the drain and source of the p-channel MOSFET Q 2 . 
   In this semiconductor device  1 C, with reference to  FIGS. 4 and 5 , when a predetermined negative voltage is not applied to the second gate terminal Tg 2  (i.e., when the P-channel MOSFET Q 2  is off), there is no continuity between the P diffusion regions  11  and  23 . Thus, the semiconductor device  1 C in this case is substantially identical in structure to and operates in the same way as the semiconductor device  1 A of the first preferred embodiment. That is, the semiconductor device (IGBT)  1 C turns on quickly but turns off rather slowly. 
   On the other hand, when a predetermined negative voltage is applied to the second gate terminal Tg 2  (i.e., the P-channel MOSFET Q 2  is on), an inversion layer is formed in a surface portion S 2  of the N −  epitaxial layer  5  which is located directly below the second gate electrode  41  to provide continuity between the P diffusion regions  11  and  23 . Thus, the semiconductor device  1 C in this case is substantially identical in structure to and operates in the same way as the collector-shorted IGBT of conventional structure (first conventional example). That is, as previously described in the first conventional example, the semiconductor device (IGBT)  1 C turns off quickly but turns on rather slowly. 
   In order to turn on the semiconductor device  1 C (i.e., when the collector terminal Tc is at a higher potential than the emitter terminal Te and a predetermined voltage is applied to the gate terminal Tg; or when the N-channel MOSFET Q 1  is turned on), the P-channel MOSFET Q 2  is turned off by not applying a predetermined negative voltage to the second gate terminal Tg 2 . By so doing, the structure of the semiconductor device  1 C is switched to that of the semiconductor device  1 A so that the semiconductor device  1 C can be turned on just like the semiconductor device  1 A. This allows the semiconductor device  1 C to turn on quickly. 
   On the other hand, in order to turn off the semiconductor device  1 C (i.e., when the application of a predetermined positive voltage to the gate terminal Tg is terminated; or when the N-channel MOSFET Q 1  is turned off), the P-channel MOSFET Q 2  is turned on by applying a predetermined negative voltage to the second gate terminal Tg 2 . By so doing, the structure of the semiconductor device  1 C is switched to the conventional structure of the collector-shorted IGBT (first conventional example) so that the semiconductor device  1 C can be turned off just like the collector-shorted IGBT of conventional structure. This allows the semiconductor device  1 C to turn off quickly. 
   The application of a predetermined negative voltage to the second gate terminal Tg 2  and the termination of that voltage application (i.e., on-off control of the P-channel MOSFET Q 2 ), described above, may be implemented by a predetermined external circuit. Or, they may automatically be implemented simultaneously with the application of a predetermined positive voltage to the first gate terminal Tg or with the termination of that voltage application (i.e., on-off control of the N-channel MOSFET Q 1 ), by short circuiting the terminals Tg 2  and Te as shown by a dotted line  43  of  FIG. 5  to fix both the terminals Tg 2  and Te at the same potential. 
   More specifically, when both the terminals Tg 2  and Te are short circuited as shown by the dotted line  43  of  FIG. 5  to be fixed at the same potential, and with reference to  FIG. 5 , when the N-channel MOSFET Q 1  is turned off, the current flow from the collector terminal Tc to the emitter terminal Te is stopped. This increases the potential of the collector terminal Tc and accordingly the potential of the drain D of the P-channel MOSFET Q 2 . This increase in the potential of the drain D causes a relative reduction in the potential of the second gate terminal Tg 2  and brings the second gate terminal Tg 2  into the same condition as when a predetermined negative voltage is applied. Accordingly, the P-channel MOSFET Q 2  is turned on. By this turning on, the equivalent circuit of  FIG. 5  becomes substantially identical to the conventional structure of the collector-shorted IGBT (first conventional example), so the transistor Tr 1  can quickly be turned off. 
   On the other hand, when the N-channel MOSFET Q 1  is turned on, current will flow from the collector terminal Tc to the emitter terminal Te. This reduces the potential of the collector terminal Tc and accordingly reduces the potential of the drain D of the P-channel MOSFET Q 2 . This reduction in the potential of the drain D stops the reduction in the potential of the second gate terminal Tg 2  relative to the potential of the drain D and brings the second gate terminal Tg 2  into the same condition as when the application of a predetermined negative voltage is terminated. Accordingly, the P-channel MOSFET Q 2  is turned off. By this turning off, the equivalent circuit of  FIG. 5  becomes substantially identical to that of the semiconductor device  1 A of the first preferred embodiment ( FIG. 2 ), so the transistor Tr 1  can quickly be turned on. 
   In this way, when both the terminals Tg 2  and Te are short circuited to be fixed at the same potential, the control of voltage applied to the second gate terminal Tg 2  can be implemented with a simple interconnection and without the use of an external circuit. 
   In the semiconductor device  1 C of the above structure, the second gate electrode  41  is provided on the surface portion of the N −  epitaxial layer  5  which is sandwiched between the P diffusion regions  11  and  23 , with the second gate insulating film  39  in between, that is, the P-channel MOSFET Q 2  is provided whose drain and source are formed respectively of the P diffusion regions  11  and  23 . Thus, by controlling continuity and non-continuity between the P diffusion regions  11  and  23  through the on-off control of the P-channel MOSFET Q 2 , the semiconductor device  1 C can, in addition to achieving the aforementioned effect of the first preferred embodiment, also selectively switch between two structures: the one substantially identical to the conventional structure of the collector-shorted IGBT (first conventional example); and the one substantially identical to that of the semiconductor device  1 A according to the aforementioned first preferred embodiment. Therefore, in turn-on of the semiconductor device  1 C, the P-channel MOSFET Q 2  is turned off so that the semiconductor device  1 C can quickly be turned on just like the semiconductor device  1 A, while in turn-off of the semiconductor device  1 C, the P-channel MOSFET Q 2  is turned on so that the semiconductor device  1 C can quickly be turned off just like the collector-shorted IGBT of conventional structure. This achieves a lateral collector-shorted IGBT which can turn both on and off quickly. 
   Fourth Preferred Embodiment 
   A semiconductor device  1 D according to this preferred embodiment is, as shown in  FIG. 6 , constructed such that in the aforementioned first preferred embodiment, a second gate electrode  49  is further provided through surface portions of the N −  epitaxial layer  5  (semiconductor layer) and the P diffusion region  23  (fourth semiconductor region) which are sandwiched between the P diffusion region  11  (second semiconductor region) and the N +  diffusion region  25  (fifth semiconductor region), with a gate insulating film  47  in between; and the second gate terminal Tg 2  is connected to the second gate electrode  49 . 
   In other words, this semiconductor device  1 D is such that, in the aforementioned third preferred embodiment, the second gate insulating film  39  and the second gate electrode  41  extend through the surface portions of the N −  epitaxial layer  5  and the P diffusion region  23  which are sandwiched between the P diffusion region  11  and the N +  diffusion region  25 . That is, this semiconductor device  1 D is constructed by adding to the aforementioned third preferred embodiment ( FIG. 4 ), an N-channel MOSFET Q 3  whose drain D and source S are formed respectively of the components  25  and  5  and which has a common gate with the P-channel MOSFET Q 2  whose drain D, source S, and gate Tg 2  are formed respectively of the components  11 ,  23 , and  41 . 
   Here, the second gate insulating film  47  is formed to approximately a thickness of field oxide film so that the semiconductor device  1 D can withstand high voltage. 
   The equivalent circuit of the semiconductor device  1 D is, as shown in  FIG. 7 , a circuit in which the above N-channel MOSFET Q 3  is added to the equivalent circuit of the aforementioned third preferred embodiment ( FIG. 5 ) in such a way that the diode D 1  is connected in parallel between the drain and source of the N-channel MOSFET Q 3  and that the second gate terminal Tg 2  is connected to the gate of the N-channel MOSFET Q 3 . 
   In this semiconductor device  1 D, when the collector terminal Tc is at a higher potential than the emitter terminal Te, the control of voltage applied to the terminals Tg and Tg 2  is done in the same way as in the aforementioned third preferred embodiment (that is, when a predetermined positive voltage is applied to the first gate terminal Tg to turn on the N-channel MOSFET Q 1 , the P-channel MOSFET Q 2  is turned off by not applying voltage to the second gate terminal Tg 2 ; while, when the application of a predetermined positive voltage to the first gate terminal Tg is terminated, the P-channel MOSFET Q 2  is turned on by applying a predetermined negative voltage to the second gate terminal Tg 2 ). During this control, the N-channel MOSFET Q 3  is off. Thus, the semiconductor device  1 D becomes substantially identical in structure to the semiconductor device  1 C of the third preferred embodiment and turns on or off just like the semiconductor device  1 C. This allows the semiconductor device  1 D to turn both on and off quickly. 
   On the other hand, when the emitter terminal Te is at a higher potential than the collector terminal Tc (in the case of reverse conduction), a predetermined positive voltage is applied to the second gate terminal Tg 2  to turn on the N-channel MOSFET Q 3  (i.e., an inversion layer is formed in a surface portion S 3  of the P diffusion region  23  which is located directly below the second gate electrode  49  so that continuity is established by the inversion layer between the components  5  and  25 ). This, with reference to  FIG. 7 , additionally provides a second reverse conducting path from the emitter terminal Te through the diode D 2  and the N-channel MOSFET Q 3  to the collector terminal Tc in parallel with a first reverse conducting path from the emitter terminal Te through the diodes D 2  and D 1  to the collector terminal Tc. Those first and second conducting paths achieve the reverse conducting capability with lower reverse conducting resistance. 
   In  FIG. 6 , the first reverse conducting path given above is from the emitter terminal Te through the component  21 , through the component(s)  7  and/or  9  and/or  3 , and through the components  5 ,  29 ,  27 ,  23 ,  25 , and  19   b  to the collector terminal Tc, and the second reverse conducting path given above is from the emitter terminal Te through the component  21 , through the component(s)  7  and/or  9  and/or  3 , and through the components  5 , S 3 ,  25 , and  19   b  to the collector terminal Tc. 
   The application of voltage to the second gate terminal Tg 2  may be implemented by a predetermined external circuit or, as in the aforementioned third preferred embodiment, may be implemented automatically by short circuiting the terminals Tg 2  and Te as shown by a dotted line  51  of  FIG. 7  to fix both the terminals Tg 2  and Te at the same potential. 
   In the latter case, with reference to  FIG. 7 , when the collector terminal Tc is at a higher potential than the emitter terminal Te, and when the N-channel MOSFET Q 1  is turned on or off by the application of a predetermined positive voltage to the first gate terminal Tg or by the termination of that voltage application, the P-channel MOSFET Q 2  is turned on or off, and accordingly, the transistor Tr 1  is quickly turned on or off in the same way as in the aforementioned third preferred embodiment. On the other hand, when the emitter terminal Te is at a higher potential than the collector terminal Tc, the potential of the gate Tg 2  of the N-channel MOSFET Q 3  becomes higher than that of the drain D of the N-channel MOSFET Q 3 , and the second gate terminal Tg 2  is brought into substantially the same condition as when a predetermined positive voltage is applied. Accordingly, the N-channel MOSFET Q 3  is turned on. This provides the second reverse conducting path (from the emitter terminal Te through the diode D 2  and the N-channel MOSFET Q 3  to the collector terminal Tc in  FIG. 7 ) in parallel with the first reverse conducting path (from the emitter terminal Te through the diodes D 2  and D 1  to the collector terminal Tc in  FIG. 7 ). Thus, in the latter case, the control of voltage applied to the second gate terminal Tg 2  can be implemented with a simple interconnection and without the use of an external circuit. 
   In the semiconductor device  1 D of the above structure, the second gate electrode  49  is also provided on the surface portion of the P diffusion region  23  which is sandwiched between the N −  epitaxial layer  5  and the N +  diffusion region  25 , with the second gate insulating film  47  in between, that is, the N-channel MOSFET Q 3  is provided whose drain and source are formed respectively of the components  25  and  5 . Thus, by controlling continuity and non-continuity between the components  25  and  5  through the on-off control of the N-channel MOSFET Q 3 , the second reverse conducting path passing through the above N-channel MOSFET Q 3  can be formed in parallel with the first reverse conducting path passing through the diode D 1  consisting of the components  23  and  25 . Thus, when the emitter terminal Te is at a higher potential than the collector terminal Tc, the presence of those parallel first and second reverse conducting paths can achieve the reverse conducting capability with lower reverse conducting resistance. 
   Further, since the second gate electrode  49  is provided also on the surface portion of the N −  epitaxial layer  5  which is sandwiched between the P diffusion regions  11  and  23 , with the second gate insulating film  47  in between, that is, the P-channel MOSFET Q 2  is provided whose drain and source are formed respectively of the P diffusion regions  11  and  23 , the semiconductor device  1 D can achieve the same effect as the semiconductor device  1 C of the aforementioned third preferred embodiment. 
   Further, the MOSFETs Q 2  and Q 3  can be formed with a simple structure and a small space, because they are formed through the formation of the second gate electrode  49  which extends through the surface portions of the N −  epitaxial layer  5  and the P diffusion region  23  which are sandwiched between the P diffusion region  11  and the N +  diffusion region  25 , with the second gate insulating film  47  in between. 
   While this preferred embodiment forms both the MOSFETs Q 2  and Q 3 , only the MOSFET Q 3  may be formed singly. 
   Fifth Preferred Embodiment 
   A semiconductor device  1 E according to this preferred embodiment is, as shown in  FIG. 8 , constructed such that in the aforementioned first preferred embodiment, the P diffusion region  23  (fourth semiconductor region) and the N +  diffusion region  25  (fifth semiconductor region), both of which constitute the diode D 1  for reverse conduction, are formed in the underlying layer of a pad  19   c  which is formed on the N −  epitaxial layer  5  (semiconductor layer) for connection with the collector terminal Tc. 
   The pad  19   c  for connection with the collector terminal Tc is surrounded by the emitter electrode  21  and typically formed on the N −  epitaxial layer  5  without being drawn out from the collector electrode  19   a  into the outside of the emitter electrode  21 . Thus, the underlying layer of the pad  19   c  is useless as a device and is wasted. In the semiconductor device  1 E, therefore, the underlying layer of the pad  19   c  is utilized as a region for forming the components  23  and  25  of the diode D 1  for reverse conduction. This eliminates the need to increase the area of the semiconductor device  1 E for formation of the components  23  and  25  and thus prevents a reduction in the share of the IGBT in the semiconductor device  1 E. This substantially reduces the conducting resistance in the semiconductor device  1 E and improves the turn-on and turn-off behavior of the semiconductor device  1 E. 
   Accordingly, the semiconductor device  1 E of the above structure can, in addition to achieving the aforementioned effect of the first preferred embodiment, also improve its turn-on and turn-off behavior, because the components  23  and  25  constituting the diode D 1  for reverse conduction are formed in the underlying layer of the pad  19   c  which is formed on the N −  epitaxial layer  5  for connection with the collector terminal Tc. 
   Sixth Preferred Embodiment 
   A semiconductor device  1 F according to this preferred embodiment includes, as shown in  FIG. 9 , the P +  substrate  3  (semiconductor substrate of a first conductivity type); the N −  epitaxial layer  5  (semiconductor layer of a second conductivity type) formed in one main surface of the P +  substrate  3 ; the P diffusion region  9  (first semiconductor region of the first conductivity type) formed in the surface of the N −  epitaxial layer  5  and connected to the P +  substrate  3  through the P diffusion region  7  (semiconductor region of the first conductivity type); the P diffusion region  11  (second semiconductor region of the first conductivity type) formed in the surface of the N −  epitaxial layer  5  apart from the P diffusion region  9 ; the N +  diffusion region  13  (third semiconductor region of the second conductivity type) formed in the surface of the P diffusion region  9  so as to be surrounded by the P diffusion region  9 ; the first gate electrode  17  provided on the surface portion of the P diffusion region  9  which is sandwiched between the N +  diffusion region  13  and the N −  epitaxial layer  5 , with the first gate insulating film  15  in between; a collector electrode  19  connected to the P diffusion region  11 ; and the emitter electrode  21  connected to the P diffusion region  9  and the N +  diffusion region  13 . In addition to this fundamental structure, the semiconductor device  1 F further includes an N diffusion region  25  (fourth semiconductor region of the second conductivity type) which is formed in the surface of the P diffusion region  11  so as to be surrounded by the P diffusion region  11  and which is connected to the collector electrode  19 ; a P +  diffusion region (fifth semiconductor region of the first conductivity type)  23  formed in the surface of the N diffusion region  25  so as to be surrounded by the N diffusion region  25 ; and electrodes  27   a  and  27   b  connected respectively to the N −  epitaxial layer  5  (semiconductor layer) and the P +  diffusion region  23  to form a conducting path from the N −  epitaxial layer  5  to the P +  diffusion region  23 . The electrode  27   a  is provided on the N −  epitaxial layer  5  with an N +  diffusion region  29  formed in the surface of the N −  epitaxial layer  5  in between so as to form an ohmic contact with the N −  epitaxial layer  5 . The electrode  27   b  is provided on the P +  diffusion region  23  and electrically connected to the electrode  27   a . In this preferred embodiment, the components corresponding to those in the aforementioned first preferred embodiment are denoted by the same reference numerals and characters. 
   The semiconductor device  1 F is, in other words, such that in the aforementioned first preferred embodiment, the components  23  and  25  constituting the diode D 1  for reverse conduction are formed in the P diffusion region  11 . 
   The electrodes  27   a  and  27   b  of this preferred embodiment correspond respectively to a portion of the electrode  27  which is provided on the N +  diffusion region  29  and a portion of the electrode  27  which is provided on the P diffusion region  23  in the aforementioned first preferred embodiment ( FIG. 1 ). Also, a portion of the electrode  19  which is provided on the P diffusion region  11  and a portion of the electrode  19  which is provided on the N diffusion region  25  in this preferred embodiment correspond respectively to the electrodes  19   a  and  19   b  in the aforementioned first preferred embodiment. Considering these correspondences, the operation of the semiconductor device  1 F is identical to that of the semiconductor device  1 A of the aforementioned first preferred embodiment, so the description thereof is omitted. 
   In this semiconductor device  1 F, the formation of the diode consisting of the components  23  and  25  for reverse conduction in the P diffusion region  11  creates a parasitic PNP transistor whose emitter, base, and collector are formed respectively of the components  11 ,  25 , and  23 . However, since the base and emitter of this parasitic PNP transistor are short circuited via the electrode  19 , the parasitic PNP transistor is never turned on. Thus, during turn-on of the semiconductor device  1 F, there is no such a case that some holes flowing from the collector terminal Tc through the electrode  19  into the P diffusion region  11  will flow into the electrode  27   b  through the components  11 ,  25 , and  23  and then disappear in the electrode  27   b  after recombined with electrons which has flown from the emitter terminal Te through the components  21 , S 1 ,  5 ,  29 , and  27   a  into the electrode  27   b . Accordingly, the formation of the diode consisting of the components  23  and  25  for reverse conduction does not result in the disappearance of holes described above. This facilitates the accumulation of holes and electrons in the N −  epitaxial layer  5  and thus allows the quick turning on of the transistor Tr 1  consisting of the components  11 ,  5 , and  3 . 
   In the semiconductor device  1 F of the above structure, the N diffusion region  25  is formed in the surface of the P diffusion region  11  so as to be surrounded by the P diffusion region  11 ; the P +  diffusion region  23  is formed in the surface of the N diffusion region  25  so as to be surrounded by the N diffusion region  25 ; and the collector electrode  19  is provided on and extends through the components  11  and  25  so as to short circuit those components  11  and  25 . Thus, the semiconductor device  1 F can, in addition to achieving the aforementioned effect of the first preferred embodiment, have the diode consisting of the components  23  and  25  for reverse conduction without inhibiting the turning on of the transistor consisting of the components  11 ,  5 ,  3 ,  7 , and  9 . 
   Seventh Preferred Embodiment 
   A semiconductor device  1 G according to this preferred embodiment is a vertical collector-shorted IGBT. It includes, as shown in  FIG. 10 , the N −  epitaxial layer  5  (semiconductor layer of a second conductivity type); the P diffusion regions  9  (first semiconductor regions of a first conductivity type) formed in one main surface of the N −  epitaxial layer  5 ; the N +  diffusion regions  13  (second semiconductor regions of the second conductivity type) formed in the surfaces of the P diffusion regions  9  so as to be surrounded by the P diffusion region  9 ; the first gate electrode  17  provided on the surface portions of the P diffusion regions  9  which are sandwiched between the N −  epitaxial layer  5  and the N +  diffusion regions  13 , with the first gate insulating film  15  in between; a P diffusion region  11   a  (third semiconductor region of the first conductivity type) formed on the other main surface of the N −  epitaxial layer  5 ; the first collector electrode  19   a  provided on the surface of the P diffusion region  11   a ; and the emitter electrodes  21  connected to the P diffusion regions  9  and the N +  diffusion regions  13 . In addition to this fundamental structure, this semiconductor device  1 G further includes the P diffusion region  23  (fourth semiconductor region of the first conductivity type) formed in the surface of the N −  epitaxial layer  5  apart from the P diffusion regions  9 ; the N +  diffusion region  25  (fifth semiconductor region of the second conductivity type) formed in the surface of the P diffusion region  23  so as to be surrounded by the P diffusion region  23 ; the second collector electrode  19   b  provided on the N +  diffusion region  25  and applied with the same voltage as the first collector electrode  19   a ; and the electrode  27  connected to the P diffusion region  23  and the N −  epitaxial layer  5  to form a conducting path from the N −  epitaxial layer  5  to the P diffusion region  23 . The electrode  27  is provided on the N −  epitaxial layer  5  with the N +  diffusion region  29  formed in the surface of the N −  epitaxial layer  5  in between so as to form an ohmic contact with the N −  epitaxial layer  5 . In this preferred embodiment, the components corresponding to those in the aforementioned first preferred embodiment are denoted by the same reference numerals and characters. 
   The first gate electrode  17  is connected to the gate terminal Tg, the emitter electrode  21  to the emitter terminal Te, and the first and second collector electrodes  19   a  and  19   b  respectively to first and second collector terminals Tc 1  and Tc 2 . 
   This semiconductor device  1 G is, in other words, such that the aforementioned first preferred embodiment is applied to a lateral IGBT. 
   The P diffusion region  11   a  corresponds to the P diffusion region  11  in the first preferred embodiment, and the first collector electrode  19   a  corresponds to the collector electrode  19   a  in the aforementioned first preferred embodiment. The first and second collector terminals Tc 1  and Tc 2  both correspond to the collector terminal Tc in the first preferred embodiment, and they are applied with the same voltage. This semiconductor device  1 G does not include components which correspond to the P diffusion region  7  and the P +  substrate  3  in the aforementioned first preferred embodiment. Considering these correspondences, the operation of the semiconductor device  1 F is identical to that of the semiconductor device  1 A of the aforementioned first preferred embodiment, so the description thereof is omitted. 
   In the semiconductor device  1 G of the above structure, as in the aforementioned first preferred embodiment, the P diffusion region  23  is formed in the surface of the N −  epitaxial layer  5 ; the N +  diffusion region  25  is formed in the surface of the P diffusion region  23  so as to be surrounded by the P diffusion region  23 ; and the second collector electrode  19   b  applied with the same voltage as the first collector electrode  19   a  is provided on the N +  diffusion region  25 . Thus, the diode consisting of the components  23  and  25  prevents electrons, which are injected from the emitter electrode  21  in the N −  epitaxial layer  5  during turn-on of the semiconductor device  1 G, from outflowing from the N −  epitaxial layer  5  into the second collector electrode  19   b . Correspondingly, more electrons and holes are accumulated quickly in the N −  epitaxial layer  5 , which contributes to the conductivity modulation of the N −  epitaxial layer  5  and allows the quick turning on of the semiconductor device  1 G. 
   Further, since the P diffusion region  23  is formed in the surface of the N −  epitaxial layer  5 , and the N +  diffusion region  25  is formed in the surface of the P diffusion region  23  so as to be surrounded by the P diffusion region  23 , a parasitic thyristor consisting of those components  23  and  25  and of the existing components  5  and  9  can be formed on a reverse conducting path (from the emitter terminal Te through the components  21 ,  9 ,  5 ,  23 ,  25 , and  19   b  to the collector terminal Tc). Thus, by utilizing a low conducting resistance during the on-state of the parasitic thyristor, the semiconductor device  1 G can achieve the reverse conducting capability with low reverse conducting resistance. 
   Further, since the electrode  27  is provided on and extends through the P diffusion region  23  and the N −  epitaxial layer  5  to form a conducting path from the N −  epitaxial layer  5  to the P diffusion region  23 , the passage of current from the N −  epitaxial layer  5  to the P diffusion region  23  can be ensured during reverse conduction of the semiconductor device  1 G. This stabilizes the turning on of the parasitic thyristor. Since, in this preferred embodiment, the electrode  27  is provided on the N −  epitaxial layer  5  with the N +  diffusion region  29  in between, a good electrical connection can be ensured between the electrode  27  and the N −  epitaxial layer  5 . 
   In this preferred embodiment, as in the aforementioned second preferred embodiment, the N diffusion region  35  having a higher carrier density than the N −  epitaxial layer  5  may be formed between the N −  epitaxial layer  5  (semiconductor layer) and the P diffusion region  23  to surround the P diffusion region  23 . 
   Eighth Preferred Embodiment 
   A semiconductor device  1 H according to this preferred embodiment is, as shown in  FIG. 11 , constructed such that the semiconductor device  1 G according to the aforementioned seventh preferred embodiment ( FIG. 10 ) further includes a P diffusion region  11   b  (sixth semiconductor region of the first conductivity type) formed in the surface of the N −  epitaxial layer  5  (semiconductor layer) apart from the P diffusion regions  9  and  23  (first and fourth semiconductor regions); a third collector electrode  19   a _ 2  provided on the P diffusion region  11   b  and connected to the second collector electrode  19   b ; the second gate electrode  41  provided on a surface portion of the N −  epitaxial layer  5  which is sandwiched between the P diffusion regions  23  and  11   b , with the second gate insulating film  39  in between; and the second gate terminal Tg 2  connected to the second gate electrode  41 . In this preferred embodiment, the components corresponding to those in the aforementioned first preferred embodiment are denoted by the same reference numerals and characters. 
   This semiconductor device  1 H is, in other words, such that the aforementioned third preferred embodiment is applied to a lateral IGBT. 
   The P diffusion regions  11   a  and  11   b  both correspond to the P diffusion region  11  in the aforementioned third preferred embodiment; the first and second collector electrodes  19   a _ 1  ( 19   a ) and  19   a _ 2  both correspond to the collector electrode  19   a  in the third preferred embodiment; and the first and second collector terminals both correspond to the collector terminal Tc in the third preferred embodiment. This semiconductor device  1 H does not include components which correspond to the P diffusion region  7  and the P +  substrate  3  in the third preferred embodiment. Considering these correspondences, the operation of the semiconductor device  1 H is identical to that of the semiconductor device  1 D of the third preferred embodiment, so the description thereof is omitted. 
   In the semiconductor device  1 H of the above structure, as in the third preferred embodiment, the second gate electrode  41  is provided on the surface portion of the N −  epitaxial layer  5  which is sandwiched between the P diffusion regions  11   b  and  23 , with the second gate insulating film  39  in between, that is, a P-channel MOSFET is provided whose drain and source are formed respectively of the P diffusion regions  11   b  and  23 . Thus, by controlling continuity and non-continuity between the P diffusion regions  11   b  and  23  through the on-off control of that P-channel MOSFET, the semiconductor device  1 H can selectively switch between two structures: the one substantially identical to the conventional structure of the collector-shorted IGBT (first conventional example); and the one substantially identical to that of the semiconductor device  1 G according to the aforementioned seventh preferred embodiment. Therefore, in turn-on of the semiconductor device  1 H, the above P-channel MOSFET is turned off so that the semiconductor device  1 H can quickly be turned on just like the semiconductor device  1 G, while in turn-off of the semiconductor device  1 H, the above P-channel MOSFET is turned on so that the semiconductor device  1 H can quickly be turned off just like the collector-shorted IGBT of conventional structure. This achieves a vertical collector-shorted IGBT which can turn both on and off quickly. 
   Ninth Preferred Embodiment 
   A semiconductor device  1 I according to this preferred embodiment includes, as shown in  FIG. 12 , the N −  epitaxial layer  5  (semiconductor layer of a second conductivity type); the P diffusion regions  9  (first semiconductor regions of a first conductivity type) formed in one main surface of the N −  epitaxial layer  5 ; the N +  diffusion regions  13  (second semiconductor regions of the second conductivity type) formed in the surfaces of the P diffusion regions  9  so as to be surrounded by the P diffusion regions  9 ; the gate electrode  17  provided on the surface portions of the P diffusion regions  9  which are sandwiched between the N −  epitaxial layer  5  and the N +  diffusion regions  13 , with the gate insulating film  15  in between; the P diffusion region  11   a  (third semiconductor region of the first conductivity type) provided on the other main surface of the N −  epitaxial layer  5 ; the first collector electrode  19   a  provided on the surface of the P diffusion region  11   a ; and the emitter electrode  21  connected to the P diffusion regions  9  and the N +  diffusion regions  13 . In addition to this fundamental structure, the semiconductor device  1 I further includes the P diffusion region  11   b  (fourth semiconductor region of the first conductivity type) formed in the surface of the N −  epitaxial layer  5  apart from the P diffusion regions  9 ; the N diffusion region  25  (fifth semiconductor region of the second conductivity type) formed in the surface of the P diffusion region  11   b  so as to be surrounded by the P diffusion region  11   b ; the P +  diffusion region  23  (sixth semiconductor region of the first conductivity type) formed in the surface of the N diffusion region  25  so as to be surrounded by the N diffusion region  25 ; the second collector electrode  19   b  provided on and extending through the N diffusion region  25  and the P diffusion region  11   b  and applied with the same voltage as the first collector electrode  19   a ; and the electrodes  27   a  and  27   b  connected respectively to the N −  epitaxial layer  5  and the P +  diffusion region  23  to form a conducting path from the N −  epitaxial layer  5  to the P +  diffusion region  23 . 
   The electrode  27   a  is provided on the N −  epitaxial layer  5  with the N +  diffusion region  29  formed in the surface of the N −  epitaxial layer  5  in between so as to form an ohmic contact with the N −  epitaxial layer  5 . The electrode  27   b  is provided on the P +  diffusion region  23  and electrically connected to the electrode  27   a . The first gate electrode  17  is connected to the gate terminal Tg, the emitter electrode  21  to the emitter terminal Te, and the first and second collector electrodes  19   a  and  19   b  respectively to the first and second collector terminals Tc 1  and Tc 2 . 
   In this preferred embodiment, the components corresponding to those in the aforementioned first preferred embodiment are denoted by the same reference numerals and characters. 
   This semiconductor device  1 I is, in other words, such that the aforementioned sixth preferred embodiment is applied to a lateral IGBT. 
   The P diffusion regions  11   a  and  11   b  correspond to the P diffusion region  11  in the sixth preferred embodiment, and the first and second collector electrodes  19   a  and  19   b  correspond to the collector electrode  19  in the sixth preferred embodiment. The first and second collector terminals Tc 1  and Tc 2  correspond to the collector terminal Tc in the sixth preferred embodiment, and they are applied with the same voltage. This semiconductor device  1 I does not include components which correspond to the P diffusion region  7  and the P +  substrate  3  in the sixth preferred embodiment. Considering these correspondences, the operation of the semiconductor device  1 I is identical to that of the semiconductor device  1 F of the sixth preferred embodiment, so the description thereof is omitted. 
   In the semiconductor device  1 I of the above structure, as in the sixth preferred embodiment, the N diffusion region  25  is formed in the surface of the P diffusion region  11   b  so as to be surrounded by the P diffusion region  11   b ; the P +  diffusion region  23  is formed in the surface of the N diffusion region  25  so as to be surrounded by the N diffusion region  25 ; and the collector electrode  19   b  is provided on and extends through the components  11   b  and  25  so as to short circuit those components  11   b  and  25 . Thus, the semiconductor device  1 I can have the diode consisting of the components  23  and  25  for reverse conduction without inhibiting the turning on of the transistor consisting of the components  11   b ,  5 , and  9  and the transistor consisting of the components  11   a ,  5 , and  9 . 
   While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.