Patent Publication Number: US-2010123612-A1

Title: Analog-to-digital conversion circuit and device

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to an analog-to-digital conversion circuit and device (ADC), preferably for mobile telephony. 
     2. Description of the Related Art 
     In mobile telephony, in some cases, an analog-to-digital conversion of single-ended type electric signals is required, i.e., of electric signals having a single voltage reference, preferably to the ground. 
     Generally, an analog-to-digital conversion device is arranged to receive in input a single-ended type electric signal coming from a relative external source having a distinctive output impedance which is not usually known or, if it is known, of a high value. 
     In these operative conditions, the need is felt to have the use of an analog-to-digital conversion device arranged for the reading of the high impedance input electric signal without incurring the typical errors associated with the division between source impedance and input impedance. 
     In order to meet this need, the analog-to-digital conversion device should be arranged to have also a very high input impedance, ideally an infinite one; therefore, a corresponding very low switched input or sampling capacitance (typically on the order of some fractions of pF, for example, at most of 0.3 pF), and a very high input resistance (typically of the order of some MOhms) is used. 
     Currently, the above requirement relative to the switched input capacitance is not found in known analog-to-digital conversion devices. 
     In fact, an analog-to-digital conversion device of a known design, directly arranged for the 10-bit sampling of an input electric signal, has an input capacitance of some pFs (for example, 5-6 pFs) to obviate further drawbacks related to usual problems such as, for example, the linearity or the noise. The operative choice of an input or sampling capacitance of some pFs contrasts with the choice of having a very low input or sampling capacitance value (at most equal to 0.3 pF). 
     In an alternative solution to the described one, the use is suggested of a unitary voltage buffer (for example, implemented with operational amplifiers) of the input electric signal arranged upstream of the analog-to-digital conversion device. Such a solution does not give an input or sampling capacitance that is as low as that required, and it also results in unreliability in terms of accuracy for conversion of single-ended type signals. This is due to the fact that, while the single-ended type analog-to-digital conversion device are arranged to convert the input signal from a ground voltage level (0V) to a predetermined reference level, which can even be very high, in any case the analog voltage buffer does not result in the ability to achieve the ground voltage level because it has active structures that begin to switch off when the voltage level is near to 0. 
     In other words, the single-ended type analog-to-digital conversion device with an input signal unitary voltage buffer arranged upstream has a criticality in reaching the ground voltage level. 
     Again, as an alternative, typically resistive structures could be employed, but this again has performance results that are unable to meet the requirement of a high input impedance. 
     BRIEF SUMMARY 
     The present disclosure provides an analog-to-digital conversion device having an alternative and improved design and function compared to the analog-to-digital conversion devices of the above-mentioned known art, and particularly which ensures reduced conversion criticalities of a ground voltage level or another reference voltage level. 
     In accordance with the present disclosure, an analog-to-digital conversion device is provided that includes an input stage arranged to receive an input signal and to provide an output analog signal as a function of the input signal; and an analog-to-digital conversion block arranged to receive the analog output signal and to provide a respective output digital signal, wherein the input stage includes a first voltage buffer arranged to provide the analog output signal to the conversion block as a translation of the input signal of an amount equivalent to a translation voltage; and a second voltage buffer arranged to provide a first reference signal to the conversion block that is representative of a translation of a first reference voltage of an amount equivalent to the translation voltage, so that the conversion block stores the input signal as a difference between the input signal and the first reference voltage, regardless of the translation voltage. 
     In accordance with the present disclosure, a circuit is provided that includes an input stage having an input and an output, the input stage including a first transistor having a drain and a source adapted to receive first and second voltage references, respectively, and a gate adapted to receive input signals; a second transistor having a drain and a source adapted to receive the first and second voltage references, and a gate adapted to receive the first voltage reference; and a third transistor having a drain and a source adapted to receive the first and second voltage references, respectively, and a gate adapted to receive a third reference voltage, the first transistor adapted to output on its source a translated voltage input signal, the second transistor adapted to output on its source a first reference signal, and the third transistor adapted to output on its source a second reference signal. 
     In accordance with the present disclosure, a mobile device is provided that includes a circuit that includes an input stage having an input and an output, the input stage including a first transistor having a drain and a source adapted to receive first and second voltage references, respectively, and a gate adapted to receive input signals; a second transistor having a drain and a source adapted to receive the first and second voltage references, and a gate adapted to receive the first voltage reference; and a third transistor having a drain and a source adapted to receive the first and second voltage references, respectively, and a gate adapted to receive a third reference voltage, the first transistor adapted to output on its source a translated voltage input signal, the second transistor adapted to output on its source a first reference signal, and the third transistor adapted to output on its source a second reference signal. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       Further characteristics and advantages of the device according to the disclosure will be more readily appreciated from the description reported below of preferred exemplary embodiments, given by way of non-limiting, indicative example, when taken in conjunction with the annexed Figures, in which: 
         FIGS. 1 and 2  illustrate, from a circuital point of view, an analog-to-digital conversion device according to an example of the disclosure; and 
         FIG. 3  illustrates, from a circuital point of view, an analog-to-digital conversion device according to a further example of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     With reference to  FIG. 1 , an analog-to-digital conversion device  100  is now described, hereinafter also simply “conversion device,” according to an example of the disclosure. 
     The conversion device  100 , which can be also referred to with the acronym ADC (Analogical to Digital Converter), finds application preferably in the mobile telephony technology in which single-ended type signals are employed. 
     The conversion device  100  includes an input stage  200  so arranged as to receive an analog-type input signal v in  coming from a conventional signal source (not shown in the Figures) and to provide an analogical output signal v in′  which is a function of the input signal v in . 
     The conversion device  100  further includes an analog-to-digital conversion block  300 , hereinafter also simply conversion block, per se known and operatively cascade-connected to the input stage  200  to receive in input the output analog signal v in′ , and to provide in output a respective digital signal V out . 
     An example of a conversion block  300  is described in U.S. Pat. No. 6,897,801 owned by the Applicant. 
     The input stage  200  includes a first voltage buffer B 1 , preferably a first source follower device. 
     The first source follower device B 1  includes a first P-channel MOS-type transistor T 1  having a predetermined channel width/length equal to W 1 /L 1 . 
     The first transistor T 1  has the gate terminal G 1  arranged to receive the input signal v in . 
     The drain terminal D 1  of the first transistor T 1  is operatively coupled to a first reference voltage V ss , the ground potential (0V) in the example. 
     The source terminal S 1  of the first transistor T 1  is operatively coupled to a second reference voltage V cc , for example, the supply voltage, through a first direct current generator I 1 . A typical supply voltage value for these applications is, for example, 2.5 V. The body of the first transistor T 1  is electrically connected to the respective source terminal S 1 . The source terminal S 1  of the first transistor D 1  is operatively coupled to the analog-to-digital conversion block  300  in order to provide it with the input stage  200  output analog signal v in′ . 
     The first source follower device B 1  is structured or arranged so that the output analog signal v in′  is a translation of the input signal v in  by an amount equal to a translation voltage V sh : 
     
       
      
       v 
       in 
       =v 
       in′ 
       +V 
       sh  
      
     
     in which V sh =V th  (threshold voltage of the first transistor T 1 )+V ov  (overdrive voltage of the first transistor T 1 ). 
     It shall be noticed that the overdrive voltage V ov  of the first transistor T 1  is the voltage that is required to allow the first transistor T 1  to transfer the current I imposed by the first current generator I 1 . 
     It shall be noticed, anyhow, that the overdrive voltage V ov  of the first transistor T 1  is independent from the input signal v in , except for negligible effects for accuracy conversions of the order, for example, of 10 bit. 
     The input stage  200  further includes a second voltage buffer B 2 , preferably a second source follower device. 
     The second source follower device B 2  includes a second P-channel MOS-type transistor T 2  that is similar to the first transistor T 1 , i.e., having a channel width/length ratio equal to W 1 /L 1 . 
     The second transistor T 2  has the respective gate terminal G 2  operatively connected to the first reference voltage V ss . The drain terminal D 2  of the second transistor T 2  is also electronically coupled to the first reference voltage V ss . The source terminal S 2  of the second transistor T 2  is operatively coupled to the second reference voltage V cc , for example, the input voltage, through a second direct current generator  12  is similar to the first current generator I 1 . The body of the second transistor T 2  is electronically connected to the respective source terminal s 2 . 
     The source terminal S 2  of the second transistor T 2  is, in turn, operatively connected to the analog-to-digital conversion block  300  to provide it with a first reference signal V rif1 . 
     The second source follower device B 2  is structured or arranged so that the first reference signal V rif1  is representative of the translation of the first reference voltage V ss  by an amount equal to the translation voltage V sh : 
     
       
      
       V 
       rif1 
       =Vss+V 
       sh  
      
     
     It shall be noticed that the translation voltage V sh  of the second source follower device B 2  is substantially the same as the first source follower device B 1  since, as already stated above, the second transistor T 2  is substantially identical to the first transistor T 1 . 
     It is pointed out that a difference between the translation voltages, which is determined by statistic mismatches of the transistors and the currents results to be, in any case, sizeable at will during the device manufacturing step, therefore it is considerable as well as negligible. 
     The input stage  200  further includes a third voltage buffer B 3 , preferably a third source follower device. 
     The third source follower device B 3  includes a third P-channel MOS-type transistor T 3  completely similar to the first T 1  and the second T 2  transistors already described above, i.e., having a channel width/length ratio equal to W 1 /L 1 . 
     The third transistor T 3  has the respective gate terminal G 3  operatively connected to a third reference voltage V ref , preferably a fraction of the second reference voltage V cc . In the case where the first reference voltage V cc  (supply voltage) is equal to 2.5 V, the third reference voltage V ref  results to be equal, for example, to 1.25 V. 
     The source terminal S 3  of the third transistor T 3  is operatively coupled to the second reference voltage V cc , through a third direct current generator  13 , which is substantially similar to the first I 1  and the second I 2  current generators described above. The body of the third transistor T 3  is electrically connected to the respective source terminal S 3 . 
     The source terminal S 3  of the third transistor T 3  is, in turn, operatively connected to the analog-to-digital conversion block  300 , in order to provide it with a second reference signal V rif2 . 
     The third source follower device B 3  is arranged so that the second reference signal V rif2  is representative of the translation of the second reference voltage V ref  by an amount equal to the translation voltage V sh : 
     
       
      
       V 
       rif2 
       =V 
       ref 
       +V 
       sh  
      
     
     It shall be noticed that the translation voltage V sh  of the third source follower device B 3  is substantially the same as the first B 1  and the second B 2  source follower devices since, as already stated above, the third transistor T 3  is substantially identical to the first T 1  and the second T 2  transistors. 
     Referring to the conversion block  300  of the example described, it is structured or arranged to receive in input the output analog signal v in′  the first reference signal V rif1 , and the second reference signal V rif2  coming from the input stage  200 , respectively. 
     As known, the conversion block  300 , in order to generate the output digital signal V out , carries out a first storing operation of the input signal v in  relative to the first reference voltage V ss  (being a single-ended type conversion block), and a second comparison operation of the input signal v in  that is stored with the third reference voltage V ref  in order to achieve the analog-to-digital conversion of the same input signal v in  (by implementing, for example, a successive-approximation algorithm, per se known). 
     Referring to the first storing operation, the conversion block  300  performs, during the first storing operation, the difference between the output analog signal v in′  and the first reference signal V rif1 , as indicated herein below: 
         v   in′   −v   rif1   =v   in   +v   sh −( V   ss   +V   sh ) 
     whereby, cancelling out the terms relative to the translation voltage V sh , it is obtained that: 
     
       
      
       v 
       in′ 
       −v 
       rif1 
       =v 
       in 
       −V 
       ss  
      
     
     As it shall be noticed, advantageously, the stored input signal v in  is, in effect, compared to the first reference voltage V ss  (in the example, the ground voltage). 
     Furthermore, it shall be noticed that the compensation of the translation voltage V sh  allows the conversion block to recover the input signal v in  as the difference of the input signal v in  and the first reference voltage V ss  independently from the translation voltage V sh . 
     This results to be rather advantageous, since the translation voltage V sh , being a function of the threshold voltage V th  and the overdrive voltage V ov  of the transistor T 1 , is process- and temperature-dependant and, for example, it would not allow the proper identification of the level 0 of the input signal V in  by the conversion block  300 . 
     This is due to the use of the first B 1  and second B 2  voltage buffers that allow having, in input at the conversion block  300 , the input signal V in  and the first reference voltage translated by the same translation voltage V sh . 
     As regards the second comparison operation between the stored input signal v in  and the third reference voltage V ref , it is pointed out that the conversion block  300  establishes, according to a successive-approximation algorithm (per se known), whether the input signal is higher or lower compared to a comparison level that is equal to V ref /2, and then compared to a comparison level that is equal to V ref /4 or 3/4V ref , and so on. 
     From an operative point of view, the conversion block  300  is structured or arranged as to contextually obtain the third reference voltage V ref  as a difference between the second reference signal V rif2  and the first reference signal V rif1 , as indicated herein below: 
         V   rif2   −V   rif1   =V   ref   +V   sh −( V   ss   +V   sh ) 
     whereby, by cancelling out the terms relative to the translation voltage V sh , it is obtained that: 
     
       
      
       V 
       rif2 
       −V 
       rif1 
       =V 
       ref 
       −V 
       ss  
      
     
     As it shall be noticed, the third reference voltage V ref  that is employed in the second comparison operation with the stored input signal v in  is obtained as the difference between the third reference voltage V ref  and the first reference voltage V ss  (ground voltage). 
     Furthermore, it shall be noticed that the compensation of the translation voltage V sh  allows the conversion block  300  to retrieve the third reference voltage V ref  as the difference of the third reference voltage V ref  and the first reference voltage V ss , independently from the translation voltage V sh . 
     This results to be rather advantageous, since the translation voltage V sh , being a function of the threshold voltage V th  and the overdrive voltage V ov  of the transistor T 1 , is process- and temperature-dependant, and it would not allow, for example, the proper identification of the exact level of the third reference voltage V ref , thus involving the missampling of the input signal v in  by the conversion block  300 . 
     This is due to the use of the second B 2  and the third B 3  voltage buffers, which allows having, in input at the conversion block  300 , the input signal V in  and the first reference voltage translated by the same translation voltage V sh . 
     In this manner, the conversion block  300  is such as to provide in output the digital signal V out  by comparing the actual input signal V in  to the actual third reference voltage V ref . 
     It shall be noticed that according to the example of the disclosure described, the conversion block  300  is arranged to perform the first recovery operation of the input signal V in  and the second recovery operation of the reference voltage V ref  by employing the same fixed reference, i.e., the first reference voltage V ss , that is the ground voltage (0V). 
     It shall be noticed that the conversion block  300  described can be referred to as being of the pseudo-differential type. Alternatively, the analog-to-digital conversion device  100  may include a differential-type conversion block. 
     As stated above, the analog-to-digital conversion device  100  of the described example advantageously allows comparing the input signal V in  and the third reference voltage V ref  by compensating the presence of the translation voltage, and avoiding that the action of process and/or temperature variations that could condition or alter the accuracy of the reference signals and voltages that are employed by the conversion block  300  to generate the digital signal V out . 
     Referring back to the input stage  200 , it is pointed out that the use of a first voltage buffer, particularly a first source follower device, allows having the required requirements met by an analog-to-digital conversion device that is dedicated, in particular, to single-ended type signals. Such requirements, which are typical for a source follower device, are: high input impedance (ideally, infinite), low input capacitance (below 0.3 pF), transfer linearity, and high band (typically of the order of Mhzs) necessary for the transfer from input to output of the analog signal also in the presence of a considerable capacitive charge, as the analog-to-digital conversion block  300  can be. 
     Referring now to  FIG. 2 , it is pointed out that, from the point of view of the circuit layout shown in  FIG. 1 , the drain terminals of the transistors T 1 , T 2 , and T 3  are operatively connected to a common pad PD corresponding to the first reference voltage V ss  through a same first electrical connection path P 1 , since such drain terminals are not responsible, at first approximation, for the voltage produced in output by the same transistors. This is due to the fact that, in any case, the P-channel MOS-transistors work in a saturation zone, and under these conditions the voltage at each source terminal is substantially insensitive to small voltage variations at the respective drain terminal. Therefore, the drain terminals can be connected to the common pad PD without paying any particular attention to the first path P 1 , being able to afford reduced voltage drops without compromising the quality of the analog-to-digital conversion device. 
     Instead, as regards the electric connection to the first reference voltage V ss  of the gate terminal G 2 , it is pointed out that an optional variation of the first reference voltage Vss would involve an equal variation of the first reference signal V rif1 . Therefore, to obviate this drawback, the gate terminal G 2  of the second transistor T 2  is electrically connected to the common pad PD through a dedicated second electrical connection path P 2 . It shall be noticed that, since the gate G 2  does not absorb current anyhow, the second path P 2  can be manufactured with a relatively high resistance (even of hundreds of Ohm), without varying the first reference voltage Vss value, and with a reduced use of the area or reduced area usage. 
     Therefore, the particular layout shown in  FIG. 2 , with the first P 1  and the second P 2  paths mutually distinct advantageously allows manufacturing the analog-to-digital conversion device  100  with an optimal accuracy and reduced area occupancy. 
     Referring to  FIG. 3 , an analog-to-digital conversion device  100 ′ according to a further embodiment is described. 
     The analog-to-digital conversion device  100 ′ is structured or arranged for the conversion of single-ended type signals relating to a first reference voltage, for example, the supply voltage. 
     It shall be noticed that, compared to the example of  FIGS. 1 and 2 , in the example of  FIG. 3  the first reference voltage will be indicated with V cc  (supply voltage), while a second reference voltage will be indicated with V ss  (ground voltage). 
     The analog-to-digital conversion device  100 ′ includes a dual input stage  200 ′ as the above-described input stage  200 , and an analog-to-digital conversion block  300 ′ which is completely similar to that described above. 
     The input stage  200 ′ includes a first voltage buffer B 1 , preferably a first source follower device, including a first N-channel MOS-type transistor T 1 &#39; having: the respective gate terminal G 1 ′ arranged to receive the input signal v in ; the respective drain terminal D 1 ′ connected to the first reference voltage V cc ; the source terminal S 1 ′ connected to a second reference voltage Vss, in the example, the ground voltage (0V), through a first current generator I 1 ′; and a body connected to the source terminal S 1 ′. 
     The input stage  200 ′ further includes a second voltage buffer B 2 , preferably a second source follower device, including a second N-channel MOS-type transistor T 2 ′ having: the respective gate G 2 ′ and drain D 2 ′ terminals connected to the first supply voltage V cc ; the source terminal S 2 ′ connected to the second reference voltage Vss (0V) through a second current generator  12 ′; and a body connected to the source terminal S 2 ′. 
     The input stage  200 ′ further includes a third voltage buffer B 3 , preferably a third source follower device, including a third N-channel MOS-type transistor T 3 ′ having: the respective gate terminal G 3 ′ connected to the third reference voltage V ref ; the respective drain terminal D 3 ′ connected to the first reference voltage V cc ; and the source terminal S 3  connected to the second reference voltage Vss (0V) through a third current generator  13 . 
     The first voltage buffer B 1 ′ is structured or so arranged as to provide the conversion block  300 ′ with an output analog signal v in″  which is representative of the translation of the input signal v in  by an amount equal to a translation voltage V sh′ . 
     The second voltage buffer B 2 ′ is structured or arranged as to provide the conversion block  300 ′ with a first reference signal V rif′  which is representative of the translation of the first reference voltage V cc  by an amount equal to the translation voltage V sh′ . 
     The third voltage buffer B 3 ′ is structured or arranged to provide the conversion block  300 ′ with a second reference signal V rif2′  that is representative of the translation of the third reference voltage V ref  by an amount equal to the translation voltage V sh′ . 
     It is pointed out that the first T 1 ′, the second T 2 ′, and the third T 3 ′ transistors have the same channel width/length W 2 /L 2 , and therefore the translation voltage V sh′  is the same for each of the transistors. 
     Furthermore, the first I 1 ′, the second I 2 ′, and the third I 3 ′ current generators are preferably completely identical one to the other. 
     The conversion block  300 ′, in the first storing operation of the input signal v in , is structured to store the input signal v in  as the difference between the input signal v in  and the first reference voltage V cc  regardless of the translation voltage V sh′ . This avoids the criticality of the identification of input signal voltage levels nearest to the second reference voltage V cc . 
     Furthermore, the conversion block  300 ′, in the second comparison operation between the stored input signal v in  and the third reference voltage V ref , is so arranged as to obtain the third reference voltage V ref  as the difference between the second reference voltage V cc  and the third reference voltage V ref  regardless of the translation voltage V sh′ . This eliminates or reduces the possibility of having an erroneous recovery of the third reference voltage V ref  and a consequent malfunctioning of the conversion block  300 ′. 
     Furthermore, also for this further embodiment, the presence of source follower devices allows the input stage  200 ′ to meet the requirements of an analog-to-digital conversion device of single-ended signals as already indicated before, and that can be found, as already specified above, in a source follower device. 
     As it shall be noticed, the object of the disclosure is fully achieved, since the analog-to-digital conversion device according to the described embodiments allows reducing the criticalities in the identification of the input signal to be converted at the reference level equal to 0V or another reference level. 
     Furthermore, the input stage with voltage buffer adapted to translate the respective input signal by a same quantity (translation voltage v sh ) allows the conversion device to store the input signal (v in ) and to obtain the sampling comparison signal (third reference voltage V ref ) regardless of the translation voltage that results to be being a function of the threshold and overdrive voltage of the transistors employed, and therefore varying with the process and the temperature. 
     Finally, the reliability of the proposed conversion device is also improved by the requirements of high input impedance, low input capacitance, transfer linearity, and high band, which are ensured by the type of voltage buffers (source follower devices) that is employed in the input stage. 
     To the above-described embodiments of the device, those of ordinary skill in the art, in order to meet contingent needs, will be able to make modifications, adaptations, and replacements of elements with functionally equivalent other ones, without departing from the scope of the following claims. Each of the characteristics described as belonging to a possible embodiment can be implemented regardless of the other embodiments described. 
     The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
     These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.