Patent Publication Number: US-9905928-B2

Title: Electrical components and method of manufacture

Description:
RELATED APPLICATIONS 
     Applicant claims priority of U.S. patent application Ser. No. 11/479,159, filed Jun. 30, 2006 and entitled ELECTRICL COMPONENTS AND METHOD OF MANUFACTURE, which in turn claims priority of US Provisional Patent Application No. 60/695,485, filed Jun. 30, 2005 and entitled SPREAD SPECTRUM RECEIVER AND METHOD OF MANUFACTURE, the contents of which are hereby incorporated herein. 
    
    
     FIELD OF THE INVENTION 
     The present invention generally relates to the construction of embedded electronic components, and in particular, to such components as they apply to signal processing. 
     BACKGROUND OF THE INVENTION 
     Conventional digital communications utilize the intensity of a signal pulse to encode a binary bit of information, using a full or high amplitude pulse to convey the 1 bit of information and a low or no amplitude pulse to signal the 0 bit datum, or vice versa. Wireless communications operate under the constraints of finite bandwidth and multiple sources of signal interference that can cause high bit error rate levels in data streams using simple digital codes. Spread-spectrum signaling protocols have been developed to address these issues in a manner that provide meaningful data rates and higher signal integrity. These protocols utilize phase shift keying (PSK) or quadrature amplitude modulation techniques to shape the transmitted pulse into a symbol that encodes a series of consecutive data bits into a single pulse.  FIG. 1A  uses a phase map to depict how a signal with constant amplitude  101  and modulated phase shift  103  produces four different phase states  105 A,  105 B,  105 C,  105 D that are used to symbolize four different two-bit combinations of data [1,1], [0,1], [1,0], [0,0].  FIG. 1B  depicts how a signal constellation containing 16 different amplitude and phase states  107  is used to encode four (4) bits per symbol: [1,1,1,1], [1,1,1,0], [1,1,0,1], [1,0,1,1], [0,1,1,1], [1,0,0,1], [1,0,0,0], [0,1,0,1], [0,1,0,0], [0,0,1,0], [1,0,0,1], [0,0,0,1], [1,0,0,0], [0,0,0,1], [0,1,1,0], and [0,0,0,0]. 
     These symbol modulation techniques affect the shape of the pulse through the signal roll-off parameter, α, which can take on values ranging between 1≦α≦0. As shown in  FIGS. 2A, 2B, 2C , different roll-off parameters used to represent different symbols will not significantly modulate the signal carrier when the pulse  109 A,  109 B,  109 C is viewed in the time domain. Time domain signal modulation primarily affects the leading and trailing tails  111 A,  111 A′,  111 B,  111 B′,  111 C,  111 C′ of the pulse.  FIGS. 3A, 3B, 3C  depicts how the varying roll-off parameters affect the pulse in the frequency domain  113 A,  113 B,  113 C. T is used to define the symbol time length and W is the Nyquist rate, W=½T, in  FIGS. 2, 3 . This modulation format causes the pulse&#39;s power spectral density to be spread over more frequencies as the roll-off parameter is increased. Therefore, symbol detection is more efficiently performed by analyzing the symbol in the frequency domain. 
     Conventional receivers will use sensors to register the pulse&#39;s time domain signature and dedicate processor functions to perform inverse Fast Fourier Transforms (IFFF) or inverse Discrete Fast Fourier Transforms that mathematically compute pulse&#39;s power spectral density. The use of mathematical methods to de-convolve a symbol&#39;s power spectral density adds component cost to the receiver, consumes additional power from any available power budget, and occupies valuable real estate when packaged on a mobile wireless platform. 
     This is particularly so in wireless communications systems based on orthogonal frequency division multiplexing (OFDM). OFDM techniques, including, but not limited to, WiMAX systems, are multi-carrier modulation methods developed to boost data rates reliably. Boosting data rates on a single carrier by shortening symbol time lengths is often more susceptible to increased bit error rates. OFDM methods use a plurality of carriers (often referred to as “sub-carriers”) operating at a lower data rate. This allows the composite data of all sub-carriers to be communicated at a combined rate that is comparable to the data rate of a single carrier with the same channel bandwidth using the same basic modulation at a higher data rate. The principal advantages to using longer symbol duration times is a net reduction in error rate by reduced susceptibility to errors from inter-symbol interference caused by multi-path time dispersion. Furthermore, inter-symbol interference is not as problematic when frequency-selective fading is distributed only over a few of the sub-carriers and the fading depth over the majority of sub-carriers is not great enough to generate significant bit errors.  FIGS. 4A, 4B  show how a plurality of sub-carriers  115  produce a composite power spectra of the individual sub-carriers that has a rectangular shape with most of the modulated data contained in the power spectral densities of leading/trailing side bands  117 A,  117 A′. However, the greater number of sub-carriers also increases the IFFF and/or IDFFF computational processing power needed to interpret the sub-carrier symbols, which processing power is limited on a mobile platform. 
     Passive resistor, capacitor, and inductor components, collectively referred to as passive components, are used to form the filtering stages that comprise these devices. At present, most passive components are assembled on the surface of a printed circuit board and generally comprise 80% of all the components used in a fully populated circuit board and account for 50% of the real estate occupied on the circuit board&#39;s major surface. Small form factor is a general requirement for mobile wireless systems. Therefore, methods that reduce a circuit&#39;s footprint by transferring the passive components from the circuit board&#39;s surface to one or more interior layers are desirable. This practice, more commonly known as embedded passive technology, is also useful in larger scale high-speed circuits, such as servers and telecommunications switches, which require a large number of electrically terminated transmission lines. Although embedded passive technologies have been under development since the early 1980&#39;s, very few approaches have been successful in meeting optimal performance tolerances. The inability to rework (exchange) an out-of-tolerance passive component after it has been embedded into the circuit board requires tolerances of ±1% of targeted performance for these components, since the failure of a single component causes the entire board value to be lost. Additionally, it is desirable for embedded passives to maintain their targeted performance tolerances over all anticipated operating temperatures to facilitate design and ensure circuit reliability. Operating temperatures typically range from −40° C. to +125° C. Most of the prior art on embedded passive technologies relies on thin film technologies that comprise a layer of material with uniform dielectric properties. Resistive metal thin films have demonstrated the greatest ability to achieve thermally stable performance with tolerances within ±1%. 
     As shown in  FIGS. 5A, 5B , embedded resistors  119  typically comprise two metal sheets consisting of a conductive metal layer  121  and a resistive metal layer  123  that are affixed to respective dielectric layers  124 ,  125 . The respective metal layers are patterned to produce conductive leads  127  within the conductive metal layer  121  and resistor elements  129 ,  130  in resistive metal layer  123 . This results in the location of resistor elements  129 ,  130  over gaps  131 ,  132  between conductive leads  127  when the two laminated sheets are aligned and brought into contact as depicted in  FIG. 5B . The resistance of the resistor elements,  129 ,  131  is controlled by the spacing of gaps  131 ,  132  between conductive leads  127 , and the sheet resistivity and thickness of the resistive metal layer  123 . Elemental resistance is determined by the spacing of gaps  131 ,  132  as the laminated resistive metal sheet will have uniform thickness and resistivity. In general, dimensional controls of the thin film metallic resistor elements  129 ,  130  will achieve tolerances of ±5% and laser trimming is used to bring the performance tolerance to within ±1% of the targeted value. Resistive thin films comprised of nickel (Ni) or platinum (Pt) have low thermal coefficients of resistance (TCR) that provide thermal stability within a tolerance of ±1% over operating temperatures. Primary reliability issues with thin film resistor elements  129 ,  130  include interactions with metallic electrodes  127  and/or the material forming dielectric layer  125  that cause metallic plaques to form, as well as mismatches between the thermal coefficients of expansion that may cause delamination between the thin film resistor elements  129 ,  130  and encapsulating dielectric  125 . 
     Thin film techniques are also used to fabricate embedded capacitors. Demand for embedded capacitors has been driven largely by a need to suppress power noise in high-speed CMOS semiconductor circuits, wherein simultaneous flipping of switching devices draws a large surge current that is supplied by the power plane embedded in the circuit board to which the semiconductor device is attached. Power noise is generated in the circuit when inadequate charge is available from within the power plane to supply the surge current. Decoupling capacitors are used to suppress power noise in high-speed circuits.  FIGS. 6A, 6B  generally depict the use of embedded decoupling capacitors  131  to suppress power noise in a circuit comprising a circuit board  133  and a high-speed semiconductor chip  135 . The power plane  137  is constructed as a laminate sheet capacitor consisting of a dielectric layer  139  inserted between two conducting metal sheets  141 ,  142  ( FIG. 6A ). One of the conducting metal layers  142  is patterned to provide floating ground planes  143  ( FIG. 6B ) in areas where the power plane  137  maintains electrical contact with a via  145  that supplies surge currents to the semiconductor device. Embedded decoupling capacitors  131 , formed by dielectric layer  139  being located between the metal sheet  141  and the floating ground plane  143 , collect and supply surplus charge to suppress power noise that can be created when there is inadequate stored charge to supply the surge current. C-Ply material manufactured by 3M Company utilizes a dielectric layer  139  that consists of an epoxy loaded with high-κ dielectric barium titanate powders. While these structures provide high sheet capacitance (6 nF/inch 2 ), higher capacitance values are desired. Furthermore, the dielectric powders loaded into the dielectric layer  139  have grain sizes (1-2 micron) that are inadequate to provide a low thermal coefficient of capacitance (TCC) and stable temperature performance. As such, 3M C-Ply decoupling capacitors are only rated to have X7R-type behavior (performance values within ±15% of the targeted value over anticipating operating temperatures). Fujitsu, Ltd. has reported the development of an aerosol deposition technique that forms a film of high-κ barium titanate ceramic at room temperature, which can be used to embed capacitors within a circuit board using an aerosol of pre-formulated ceramic powders. Grain sizes reported to be required to form high-quality films (0.05-2 micron) are also insufficient to maintain a TCC suitable for stable thermal performance or COG-type behavior. 
       FIGS. 7A, 7B  show top and profile views of a passive inductor  150  embedded into an interconnect structure or printed circuit board  151 . Inductor  150  typically comprises a coil structure  147 , or a simple loop structure (not shown), configured on one or more dielectric sheets  152 , with a feed line  149  supplying current to the coil  147 , that is situated on a separate dielectric layer  153  located inferior (or superior) to the plane(s) upon which the coil is located. The dielectric layers  152 ,  153 ,  154  are generally comprised of the identical material used to construct the circuit. 
     U.S. Pat. No. 5,154,973 to Imagawa, et al., disclose a dielectric lens antenna that includes high-κ dielectric ceramic compositions prepared from powders with a mean particle size ranging between 1 and 50 micron that are mixed with an organic thermoplastic material. U.S. Pat. No. 5,892,489 to Kanba et al., disclose a chip antenna incorporating high-κ oxide ceramics formed from powders having a mean particle size of 10 microns. U.S. patent No. to K-D Koo, et al., disclose a chip antenna which comprises helically wound conductors formed by printing planar trace structures on dielectric sheets and assembling those sheets to form said chip antenna. U.S. Pat. No. 6,028,568 to K. Asakura, et al., disclose a chip antenna containing at least one folded antenna formed by printing conductor on a plurality of dielectric layers, wherein at least one dielectric layer is a magnetic material, and fusing said dielectric layers into a solid structure. U.S. Pat. No. 6,222,489 B1 to T. Tsuru, et al., disclose a chip antenna containing monopole or dipole antenna prepared by printing conductor traces on a plurality of dielectric layers, wherein each individual layer has uniform composition providing said individual layer with either a relative permittivity of ∈ R =1-130 or relative permeability of μ R  1-7, and said plurality of layers is fused into a single component. U.S. Pat. No. 6,650,303 B2 to H. J. Kim, et al., disclose a chip antenna comprising a plurality of dielectric sheets, wherein each sheet has uniform composition throughout the sheet, and conductor leads that are configured to form a helical antenna. U.S. Pat. No. 6,680,700 B2 and U.S. Pat. No. 6,683,576 B2 to A. Hilgers disclose a chip antenna that comprises a core ceramic substrate having uniform dielectric properties and conducting metal traces on its periphery that is surface mounted to a circuit board. U.S. Pat. No. 6,025,811 to Canora et al. disclose a directional antenna with a closely-coupled director embedded or mounted on a circuit wherein the director element is a conductive element that has a rectangular cross-sectional profile. U.S. Ser. No. 10/265,351 filed by T. T. Kodas et al. disclose inkjet techniques to form conductive electronic materials from a colloidal suspension of nanoparticles in a low viscosity solvent. U.S. Ser. No. 10/286,363 filed by Koda et al. disclose direct-write (syringe-based) methods to form inorganic resistors and capacitors from a flowable high-viscosity precursor solution consisting of combination of molecular precursors and inorganic powders. U.S. Pat. Nos. 6,036,899 and 5,882,722 disclose methods and formulations to apply metallization layers using nano-particle pastes. 
     U.S. Pat. No. 6,027,826 to de Rochemont, et al., disclose articles and methods to form oxide ceramic on metal substrates to form laminate, filament and wire metal-ceramic composite structures using metalorganic (molecular) precursor solutions and liquid aerosol spray techniques. U.S. Pat. Nos. 6,323,549 and 6,742,249 to de Rochemont, et al., disclose articles that comprise, and methods to construct, an interconnect structure that electrically contacts a semiconductor chip to a larger system using at least on discrete wire that is embedded in silica ceramic, as well as methods to embed passive components within said interconnect structure using metalorganic (molecular) precursor solutions and liquid aerosol spray techniques. U.S. Pat. Nos. 5,707,715 and 6,143,432 to de Rochemont, et al., disclose articles and methods to relieve thermally-induced mechanical stress in metal-ceramic circuit boards and metal-ceramic and ceramic-ceramic composite structures prepared from a solution of metalorganic (molecular) precursors, and further discloses the incorporation of secondary phase particles (powders) in said solution of said solution of metalorganic (molecular) precursors. The contents of each of these references are incorporated herein by reference as if laid out in their entirety. U.S. Ser. No. 11/243,422 discloses articles and methods to impart frequency selectivity and thermal stability to a miniaturized antenna element, and the construction of simplified RF front-end architectures in a single ceramic module. 
     SUMMARY 
     One embodiment of the present invention provides an electrical component, comprising a ceramic element located on or in a dielectric substrate between and in contact with a pair of electrical conductors, wherein the ceramic element includes one or more metal oxides having fluctuations in metal-oxide compositional uniformity less than or equal to 1.5 mol % throughout the ceramic element. 
     The metal oxides may substantially consist of particles having a substantially uniform grain size. The grain size is measured along a major axis of each particle, and it is less than 1.5 times and greater than 0.5 times an average grain size contained in the ceramic element. The grain size is determined by controlling heat treatment during fabrication. 
     The ceramic element an electrical characteristic determined by which specific metal oxides are included. The electrical characteristic is effected by controlling average grain size using heat treatment during fabrication. The electrical characteristic of the ceramic element exhibits a substantially constant value which varies ≦1% over an operating temperature range of 40° C. to 120° C. 
     The ceramic element may be fabricated by causing simultaneous decomposition of metalorganic precursors. The simultaneous decomposition may be achieved by using rapid thermal annealing on deposited the metalorganic precursors. The ceramic element may be fabricated by depositing carboxylate salt precursors prior to the simultaneous decomposition. The precursors may be deposited as a wax compound. Radiant energy may be applied to the deposited precursors to cause the simultaneous decomposition. 
     The metal oxides may have a rutile, pyrochlore, perovskite, body-centered cubic, rhombic dodecahedron, rhombic trapezohedron crystalline phase, or mixtures thereof, that includes amounts of one or more of copper oxide (CuO), nickel oxide (NiO), ruthenium oxide (RuO 2 ), irdium oxide (IrO 2 ), rhomdium oxide (Rh 2 O 3 ), osmium oxide (OsO 2 ), antimony oxide (Sb 2 O 3 ), titanium oxide (TiO2), zirconium oxide (ZrO), hafnium oxide (HfO), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), iron oxide (Fe 2 O 3 ), and silicon oxide (SiO 4 ). 
     The ceramic element may include a resistive metal oxide material having an intrinsic sheet resistivity greater than 25 μΩ-cm. The ceramic element may also include a conductive metal oxide and further wherein the electrical component is a resistor. The metal oxides may have a rutile, pyrochlore, or perovskite crystalline phase that includes amounts of one or more of copper oxide (CuO), nickel oxide (NiO), ruthenium oxide (RuO 2 ), irdium oxide (IrO 2 ), rhomdium oxide (Rh 2 O 3 ), osmium oxide (OsO 2 ), antimony oxide (Sb 2 O 3 ), and indium-tin oxide. The metal oxides may be from the group consisting of: bismuth oxide (Bi 2 O 3 ), lanthanum oxide (La 2 O 3 ), cerium oxide (Ce 2 O 3 ), lead oxide (PbO) and neodymium oxide (Nd 2 O 3 ). The metal oxides may include alkaline earth metal oxides drawn from the group consisting of magnesium oxide (MgO), calcium oxide (CaO), strontium oxide (SrO), barium oxide (BaO), scandium oxide (Sc 2 O 3 ), titanium oxide, (Ti 2 O 3 ), vanadium oxide (V 2 O 3 ), chromium oxide (Cr 2 O 3 ), manganese oxide (Mn 2 O 3 ), and iron oxide (Fe 2 O 3 ). The metal oxides may substantially consist of particles having a substantially uniform grain size. The ceramic element may have a resistivity or resistance value which varies ≦5% over an operating temperature range of −40° C. to 125° C. The ceramic element may have a resistivity or resistance value which varies ≦1% over an operating temperature range of −40° C. to 125° C. The ceramic element can have a resistance value anywhere between 10 ohms and 50 mega-ohms. The ceramic element can have a resistance value anywhere between 1 ohm and 500 mega-ohms. 
     The electrical component may be a capacitor with the pair of electrical conductors forming opposing electrodes and the ceramic element forming a dielectric thereof. The one or more metal oxides may substantially consist of particles having a substantially uniform grain size. 
     The capacitor can have a capacitance value anywhere between 0.01 pF to 900 μF. Each of the pair of electrical conductors may include a separate enlarged area having an opposed orientation to each other with the ceramic element located there between. The electrical conductors and the ceramic element may form a sheet capacitor having a capacitance &gt;20 nF/inch 2 . 
     The pair of electrical conductors may be in the form of circuit board traces and create a multiplicity of closely spaced, interdigitated fingers for the opposing electrodes. The ceramic element may be located in a meandering gap formed between the interdigitated fingers, and the meandering gap may maintains a substantially constant spacing and even in curved or corner areas of the meandering gap. 
     The ceramic element may have a dielectric constant value which varies ≦5% over an operating temperature range of 40° C. to 120° C. The metal oxides may substantially consist of particles having a substantially uniform grain size which averages less than 70 nanometers. The ceramic element may have a dielectric constant value which varies ≦1% over an operating temperature range of 40° C. to 120° C. The metal oxides may substantially consist of particles having a substantially uniform grain size which averages less than 50 nanometers. 
     The ceramic element may have high permittivity, and the one or more metal oxides may have perovskite crystal structures and will generally have the chemical formula M (1) M (2) O 3 , with metals from group M (1)  and M (2)  included in 1:1 molar ratios. Each group M (1) , M (2)  may include a plurality of metals with the combined molarity for each group being the same. The two metals, M (1a) , M (1b) , may be selected from group M (1)  and two other metals may selected from group M (2) , and the one or more metal oxides have the chemical formula M (1a)   (1-x) M (1b)   (x) M (2a)   (1-y)  M (2b)   (y) O 3 . The metal oxides of group M(1) may include: alkaline earth metal oxides selected from magnesium oxide (MgO), calcium oxide (CaO), strontium oxide (SrO), and barium oxide (BaO); alkali metal oxides selected from lithium oxide (Li 2 O), sodium oxide (Na 2 O), potassium oxide (K 2 O), and rubidium oxide (Rb 2 O); and heavy-metal oxides selected from the group including lanthanum oxide (La 2 O 3 ), cerium oxide (Ce 2 O 3 ), lead oxide (PbO) and neodymium oxide (Nd 2 O 3 ). The metal oxides of group M(2) may include titanium oxide (TiO2), zirconium oxide (ZrO), hafnium oxide (HfO), tantalum oxide (Ta 2 O 5 ), and niobium oxide (Nb 2 O 5 ). 
     The pair of electrical conductors may be connected by one or more additional electrical conductors, which encircle the ceramic element to form an inductor. The inductor may exhibits an inductance anywhere over the range of 0.1 pH to 500 nH. The inductor may maintains its inductance value within ±1% over an operating temperature range of 40° C. to 120° C. The metal oxides may have a body-centered cubic crystalline phase, that includes iron oxide (Fe 2 O 3 ) and amounts of one or more of: cobalt monoxide (CoO), nickel oxide (NiO), zinc oxide (ZnO), manganese oxide (MnO), copper oxide (CuO), vanadium oxide (VO), magnesium oxide (MgO) and lithium oxide (Li 2 O) The electrical component of claim  42 , wherein one metal oxide of the one or more metal oxides is silicon oxide (SiO 4 ) and the ceramic element adopts a rhombic dodecahedron or rhombic trapezohedron crystalline phase, and the other metal oxides include amounts of one or more of: aluminum oxide (Al 2 O 3 ), iron oxide (Fe 2 O 3 ), chromium oxide (Cr 2 O 3 ), vanadium oxide (V 2 O 3 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), silicon oxide (SiO 2 ), yttrium oxide (Y 2 O 3 ), cobalt oxide (Co 3 O 4 ), gadolinium oxide (Gd 2 O 3 ) neodymium oxide (Nd 2 O 3 ) and holmium oxide (Ho 2 O 3 ). 
     The additional electrical conductors may form a coil around the ceramic element. The additional electrical conductors may include a multiplicity of additional conductors, including one or more second electrical conductors formed as circuit board traces and located beneath the ceramic element. Each of the one or more second electrical conductors may be elongated and have contact pads located at opposing ends thereof, wherein the multiplicity of additional conductors includes a plurality of electrical contact posts located on the contact pads and adjacent the ceramic element. The multiplicity of additional conductors may include one or more wire bonds located over the ceramic element and connecting the electrical conductor posts. 
     The ceramic element may include a plurality of ceramic elements embedded in the dielectric substrate and operatively interconnected. The plurality of ceramic elements may include first and second ceramic elements which each form a different type of passive component. The first and second ceramic elements may form a capacitor and an inductor, respectively. The plurality of ceramic elements may form an electronic filter. 
     The electrical component may further comprise an integrated circuit mounted on the dielectric substrate and operatively connected to one of the pair of electrical conductors. The ceramic element may include a plurality of ceramic elements embedded in the dielectric substrate, and further wherein the plurality of ceramic elements form an electronic filter. The electrical component may further comprise an antenna element operatively connected to the electronic filter. 
     The dielectric substrate may be one of a plurality of layers in a multilayer circuit board. One or more of the electrical conductors may include a contact pad, and further comprise an electrical conductor post positioned on the contact pad for providing electrical connection through the dielectric substrate to an adjacent layer in the circuit board. One or more other layers in the multilayer circuit board may include embedded electrical components. The electrical component may further comprise an integrated circuit mounted on one layer of the multilayer circuit board, and operatively connected to one of the pair of electrical conductors. 
     The dielectric substrate may be formed around the ceramic element. One or more of the electrical conductors and the ceramic element may be first formed on a base substrate. The base substrate may be removed before combining the dielectric substrate with other dielectric substrates to form a multilayer circuit board. One or more additional electrical components may be formed on top of the dielectric substrate at the level of a second layer of the multilayer circuit board, wherein a second dielectric layer is formed around the one or more additional electrical components to form the multilayer circuit board. 
     In another embodiment of the present invention, a method of fabricating an electrical component, comprises the steps of forming a ceramic element between and in contact with a pair of electrical conductors on a substrate including depositing a mixture of metalorganic precursors and causing simultaneous decomposition of the metal oxide precursors to form the ceramic element including one or more metal oxides. 
     The simultaneous decomposition may be achieved by using rapid thermal annealing of deposited metalorganic precursors. The ceramic element may be fabricated by depositing carboxylate salt precursors prior to the simultaneous decomposition. The precursors may be deposited as a wax compound. Radiant energy may be applied to the deposited precursors to cause the simultaneous decomposition. The metal oxides may have a rutile, pyrochlore, or perovskite crystalline phase that includes amounts of one or more of copper oxide (CuO), nickel oxide (NiO), ruthenium oxide (RuO2), irdium oxide (IrO2), rhomdium oxide (Rh2O3), osmium oxide (OsO2), and antimony oxide (Sb2O3). The metal oxides are formed having fluctuations in metal-oxide compositional uniformity less than or equal to 1.5 mol % throughout the ceramic element. The metal oxides may substantially consist of particles having a substantially uniform grain size. The grain size is measured along a major axis of each particle, and further wherein the grain sizes are less than 1.5 times and greater than 0.5 times an average grain size contained in the ceramic element. The grain size is determined by controlling heat treatment during fabrication. 
     Yet another embodiment of the invention provides an antenna, comprising: a folded antenna element having a maximum dimension D; and a meta-material dielectric body embedding the folded antenna element a distance S from an exterior surface of the meta-material dielectric body; wherein the meta-material dielectric body comprises a dielectric host have a relative permittivity ∈ R ≦10 and one or more dielectric inclusions having relative permittivity ∈ R &lt;10; the distance S is greater than the protrusion length d of the folded antenna element&#39;s reactive near-field region, wherein the reactive near-field protrusion length d is defined as d=0.62 √(D 3 /λ), and λ is the wavelength of an electromagnetic excitation emitted or received by the folded antenna element. 
     The dielectric host may be an organic dielectric. The organic dielectric may include FR4, Rogers Duroid or PFTE Teflon dielectric. The organic dielectric host may have a loss tangent tan δ≦10 −3 . The dielectric host may be an inorganic dielectric. The inorganic dielectric host may be a silica or alumina dielectric. The inorganic dielectric host may have a loss tangent tan δ≦10 −3 . The inorganic dielectric host may have a value for relative permittivity ∈ R  that is stable over operating temperatures between −150° C. and +250° C. 
     A further embodiment of the present invention provides an antenna, comprising: a folded antenna element having a maximum dimension D; and a meta-material dielectric body embedding the folded antenna element a distance S from a dielectric inclusion contained within the meta-material dielectric body; wherein the meta-material dielectric body comprises a dielectric host have a relative permittivity ∈ R ≦10 and one or more dielectric inclusions having relative permittivity ∈ R &gt;10; the distance S is greater than the protrusion length d of the folded antenna element&#39;s reactive near-field region, wherein the reactive near-field protrusion length d is defined as d=0.62 √(D 3 /λ), and λ is the wavelength of an electromagnetic excitation emitted or received by the folded antenna element. 
     The present invention describes various embodiments that allow frequency-selective antennas to be configured as a spread-spectrum receiver and use high-k inclusions and closely coupled directors in a manner that imparts radiative gain. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       For a better understanding of the present invention, together with other and further aspects thereof, reference is made to the following description taken in conjunction with the accompanying figures of the drawing, wherein: 
         FIGS. 1A, 1B  depict quadrature phase states used to encode a bit pair and a four bit packet as symbols by methods of phase shift keying and quadrature amplitude modulation, respectively; 
         FIGS. 2A, 2B, 2C  are representative time domain pulse shapes of symbols encoded with different roll-off parameters; 
         FIGS. 3A .  3 B,  3 C are representative power spectral densities as viewed in the frequency domain of the time domain symbols presented in  FIGS. 2A, 2B, 2C ; 
         FIGS. 4A, 4B  show the power spectral density for pulses modulated over a plurality of sub-carriers as the individual PSD components and when combined to form high data-rate, low bit error rate wireless communications link; 
         FIGS. 5A, 5B  depict prior art for thin film embedded resistors; 
         FIGS. 6A, 6B  depict prior art on thin film embedded capacitors; 
         FIGS. 7A, 7B  depict prior art on thin film embedded inductors; 
         FIG. 8  depicts the influence grain-size has on dielectric response as a function of temperature in BST electroceramics; 
         FIG. 9  is a flow chart describing the processes used to formulate a precursor solution that can be used to formulate a liquid aerosol spray or a solid wax useful in printing a plurality of ceramic compositions in selective locations on a substrate surface; 
         FIGS. 10A, 10B  depict a method to apply a plurality of ceramic compositions in selective locations on a substrate surface using liquid aerosol sprays; 
         FIG. 11  depicts a method to apply a plurality of ceramic compositions in selective locations on a substrate surface by printing LCD electroceramic using solid wax precursors. 
       FIGS.  12 A 1 ,  12 A 2 ,  12 B depict an alternative method to apply a plurality of ceramic compositions in selective locations on a substrate surface by printing LCD electroceramic using solid wax precursors; 
         FIGS. 13A, 13B  depict top and side views of a ceramic resistor element; 
         FIGS. 14A, 14B  depict top and side views of ceramic resistor arrays composed of elements having different resistive values; 
         FIG. 15  depicts the microstructure of a mixed-phase resistive ceramic; 
         FIGS. 16A, 16B, 16C, 16D  depict embodiments and fabrication relating to a printed circuit board that contains electrically interconnected embedded discrete resistor components; 
         FIGS. 17A, 17B, 17C, 17D, 17E, 17F, 17G  depict embodiments and fabrication relating to discrete capacitor components having COG-type behavior; 
         FIG. 18  depicts embodiments and fabrication relating to a sheet capacitor with COG-type behavior with an electrode formed from nano-metallic pastes; 
         FIGS. 19A, 19B  depict embodiments and fabrication relating to a sheet capacitor with COG-type behavior formed with metal foil electrodes; 
         FIGS. 20A, 20B, 20C  depict embodiments and fabrication relating to embedding discrete capacitor elements in a dielectric layer; 
         FIGS. 21A, 21B  depict embodiment and fabrication relating to embedded capacitors derived from a sheet capacitor layer; 
         FIG. 22  depicts a printed circuit board that contains electrically interconnected embedded discrete and sheet capacitors; 
         FIGS. 23A, 23B, 23C, 23D, 23E, 23F, 23G  depict embodiments and fabrication relating to discrete inductor coils; 
         FIGS. 24A, 24B  depict embodiments and fabrication relating to inductor coils embedded in a dielectric layer; 
         FIG. 25  depicts embodiments and fabrication relating to a printed circuit board that contains electrically interconnected embedded discrete inductor coils; 
         FIG. 26A, 26B  depict embodiments and fabrication relating to a dielectric layer that contains embedded resistors, capacitors, and inductors; 
         FIGS. 27A, 27B  depict embodiments and fabrication relating to a printed circuit board that contains electrically interconnected embedded resistors, capacitors, and inductors; 
         FIG. 28  depicts an antenna dimension; 
         FIGS. 29A, 29B, 29C  depict a folded antenna element embedded in a meta-material dielectric that confines the antenna&#39;s reactive near field within the physical perimeter of the meta-material dielectric; 
         FIG. 30  depicts an embodiment and construction of a spread-spectrum receiver; 
         FIGS. 31A, 31B  depict the placement of reactive loads on L-section matched impedance transmission lines; 
         FIGS. 32A, 32B  show representative conduction bands and corresponding VSWR profiles of a frequency-selective antenna; and 
         FIGS. 33A, 33B  depict the system architecture a single carrier and a multiple carrier spread-spectrum receiver, respectively. 
     
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     The following terms are used herein in the sense of their stated meanings. 
     The term circuit board is hereinafter defined to mean a passive circuit comprising a single dielectric layer or a plurality of stacked dielectric layers on which conductive traces have been printed or applied that is used to route electrical or electronic signals between one or more semiconductor devices, passive components, and power sources within a larger electronic system. For the purpose of this invention, circuit board may be understood to mean a back plane, a mother board, or a daughter card. 
     The term “interconnect” is hereinafter defined to mean passive circuit comprising a single dielectric layer or a plurality of stacked dielectric layers on which conductive traces have been printed or applied that is used to route electrical or electronic signals between one or more semiconductors, passive components, power sources, and a circuit board within a larger electronic system. For the purpose of this invention, interconnect is understood to mean a smaller wiring structure that is inserted between one or more semiconductor devices and a circuit board, such that the combination of the interconnect and the one or semiconductor devices functions as a module, or a subsystem module. 
     The term “electroceramic” is hereinafter defined to mean a ceramic composition that comprises two or more metal oxide components, wherein said metal oxide components have been selected to produce a specific electrical or dielectric response or physical property, such as, dielectric constant (principally defined by the materials relative permittivity (∈ R ), relative permeability (μ R ), and loss tangent (tan δ)) or electrical resistivity, etc. 
     The term “ferroelectric” is used to define a state of spontaneous polarization generated by the collective displacement of ions within the lattice of certain ionic crystals that produces a state of internal electrical polarization without the application of an external electric field. Ferroelectric materials are characterized by a transition-temperature, known as the Curie transition-temperature, below which the ionic crystal displays paraelectric behavior. 
     The term “paraelectric” is used to define a condition in which a material does not possess internal electrical polarization in the absence of electrical fields. 
     The acronym “LCD” is hereinafter defined to refer to liquid chemical deposition. Liquid chemical deposition is hereinafter defined to mean the method whereby low-volatility metalorganic salt solutions containing metal oxide precursors to a desired ceramic composition, preferably carboxylate salt precursors, are used to deposit a desired oxide composition by means of a liquid aerosol spray on a substrate heated to temperatures between 250° C. and 500° C., preferably 325° C. and 430° C., or by means of a wax-based inkjet system on substrates held at temperatures below 350° C., preferably below 250° C. 
     The term “metalorganic precursor” is hereinafter understood to describe an organic molecule to which a specific metal atom has been attached to a carbon atom through an intermediate oxygen bond. 
     The term “organometallic precursor” is hereinafter understood to describe an organic molecule to which a desired metal atom has been attached directly to a carbon atom. 
     The term “meta-material dielectric” is hereinafter understood to describe a dielectric body that comprises a lower permittivity, non-magnetic host dielectric that contains at least one higher permittivity or high permeability (μ R ≠1) dielectric inclusion within its body, wherein the inclusion has physical dimension that is small (≦λ/4, preferably ≦λ/8) compared to the wavelength of an electromagnetic excitation propagating through or incident upon the meta-material dielectric body. 
     The term “nano-particle conductive pastes” is hereinafter understood to describe a flowable precursor that consists of fine metal particles, with particle dimensions ranging from 10 nm to 100 nm, and additional chemical additives that can be used to screen print or inkjet high quality metallization layers with low conversion temperatures in the range or 100° C. to 350° C. 
     The term “rapid thermal annealing” is hereinafter understood to describe a heating process wherein a combination of resistive heat and focused radiation are applied to material layers deposited on the surface of substrate in such a way that cause said deposited material layers to be heated to internal temperatures sufficient to initiate crystallization processes in said deposited materials for a short duration of time, but leaves said substrate largely unaffected by the rapid thermal annealing process even if said substrate is susceptible to change in material phase at internal temperatures significantly lower than those used to crystallize said deposited materials. Focused radiation normally is understood to mean an absorptive wavelength of infrared, visible, or ultraviolet light delivered using a laser, a pulsed laser, or one or more lamps. Focused radiation may also include microwave radiation. Controlled gas atmospheres may also need to be used during a rapid thermal annealing process. 
     The term “passive component” is hereinafter understood to describe an elemental resistor, capacitor, or inductor. 
     The term “standard operating temperatures” is hereinafter understood to mean temperatures in the range of −40° C. to +125° C. 
     Applicant hereby incorporates by reference herein the contents of co-pending U.S. patent application Ser. No. 11/243,422, filed Oct. 3, 2005, entitled CERAMIC ANTENNA MODULE AND METHODS OF MANUFACTURE THEREOF. 
     Methods and devices that provide a means to determine the power spectral density of transmitted symbols using passive, rather than computational methods, have value in reducing the power consumption and cost of a transceiver component used in mobile wireless systems. Furthermore, methods and devices that reduce the form factor of such simplified receivers are also desirable in mobile wireless systems. Precisely tuned passive circuitry with tuning parameters that remain stable with operational temperature, and which is not affected by the surrounding electromagnetic environment, plays an important role in providing the above benefits. Factors that make these circuits susceptible to de-tuning are related primarily to materials selection, the manufacturing methods used to process the selected materials and the design of the dielectric medium that envelopes one or more antennas contained within the module. In general, the tuning of an antenna is affected by dielectric materials that are located within the antenna&#39;s near-field radiation pattern. As discussed below, the antenna&#39;s near field pattern extends a distance, d near field , away from the antenna element that is a function of the antenna&#39;s maximum dimension and its radiation wavelength. Near-fields often extend beyond the perimeter of the handheld device, which causes the antenna&#39;s tuning to change by the dielectric loads that are applied when the device is handled or brought close to the users&#39; head. As discussed below, a specific objective of the present invention is to provide one or more antennas embedded within a dielectric medium that has been engineered to contain all or most of the antenna&#39;s reactive near-field within the device. This reduces external influences on the near-field and, in turn, stabilizes the antenna&#39;s electromagnetic tuning. Another specific objective is to provide circuits and manufacturing methods with the ability to integrate passive components and dielectric materials having a wide range of performance values on a single circuit layer, wherein said performance values have tolerances and thermal stability that is ≦±1% of the targeted value. This is achieved using liquid chemical deposition (LCD), alternatively referred to as spray-pyrolyzed metalorganic decomposition (SP-MOD) in de Rochemont et al., provides the means to achieve this need. 
     LCD uses liquid solution to mix one or more metalorganic salt precursors to one or more desired metal oxides at the molecular level. Low volatility metalorganic salts are preferred precursor compounds, specifically carboxylate salt compounds, and, in particular, carboxylate salt compounds having rank (number of carbon atoms) greater than 5. Carboxylate salt compounds with rank 5 or more are predisposed to decompose rather than evaporate at elevated temperatures. This allows a wide variety of precursor compounds to be intimately mixed at the molecular-level in solution, atomized into an aerosol spray and deposited on a substrate that is heated to temperatures elevated above the decomposition temperatures of said precursor compounds. Each species of metalorganic precursor will have a unique decomposition temperature, ranging roughly between 250° C. and 350° C. The molecular-level precursor subdivision achieved in the solution is replicated in the sprayed deposit when the substrate is heated to temperatures that initiate the simultaneous decomposition of all metalorganic species. LCD methods provide a means to achieve a very high degree of chemical uniformity in deposited materials and, more specifically, provide a means to prepare very precisely controlled materials formulations irrespective of the deposited materials&#39; chemical complexity (number of distinct metal oxide components). LCD methods have demonstrated an ability to produce chemically uniform materials with control over metal stoichiometry that has a statistical variance ≦±1.5 mol %. Fluctuations in electroceramic composition that are less than 1.5 mol % have a negligible affect on dielectric performance when the electroceramic is processed into a state of controlled and uniform microstructure. The initial physical state of dielectric materials prepared using LCD methods is that of a solid solution/or glass, which has no discernible crystalline microstructure or grain/particle-size. Microstructure is now understood to have a very strong influence on the dielectric constant and physical properties of electroceramics. A uniform microstructure is a key characteristic of properly annealed LCD ceramics. Unlike powder processed ceramics, which provide a distribution of grain/particle sizes around a certain average where 20%-30% of the grains/particles will have diameters &gt;1.5× the average grain/particle size, a properly annealed LCD 100% of the grains will have particle diameters that are ≦1.5× and ≧0.5× the average grain size, preferably 100% of the grains will have particle diameters that are ≦1.25× and ≧0.75× the average grain size. Proper annealing conditions include temperatures and redox atmospheres that are dependent upon specific ceramic compositions. 
       FIG. 8  [referenced from Vest, Ferroelectrics, 102, 53-68 (1990)] depicts the dielectric constant as a function of temperature of a barium-strontium titanate (BST) electroceramic prepared from metalorganic precursors that was heat treated to produce identical materials compositions having three different grain sizes: 0.034 micron (μm)  200 , 0.10 μm  202 , and 0.200 μm  204 , respectively. BST electroceramic is a dielectric material with high-κ properties that are useful in making small capacitors. As shown, BST electroceramic with grain sizes greater than 0.10 μm or 100 nanometer (nm)  202  exhibit very high dielectric constant values (∈ R &gt;400) and ferroelectric behavior with a peak dielectric constant at a Curie transition temperature of approximately 135° C. The Curie transition temperature represents the temperature at which the dielectric will shift from paraelectric to ferroelectric behavior. In general, a larger grain size produces a higher dielectric constant and more strongly pronounced ferroelectric behavior, which is highly unstable with temperature.  FIG. 8  also demonstrates a high relative permittivity (∈ R ≧200) with a stable dielectric constant over temperature  200  when the ceramic grain/particle size is restricted to very small dimension ˜34 nm. 
     In the case of high permittivity electroceramics, smaller grain sizes suppress the formation of critical domains that initiate cooperative interactions responsible for the paraelectric to ferroelectric phase transition. A BST electroceramic parallel plate capacitor, where total capacitance C is derived as:
 
 C =A∈ o ∈ R   /d   (1)
 
Where A is the plate area, ∈ o  is the permittivity constant for free-space (∈ o =8.854×10 −12  F/m), and ∈ R  is the relative permittivity constant of the material, will have thermally unstable performance values when the ceramic contains grains have particle dimensions that are greater than 50-70 nm. Stable electrical performance (≦±1% of targeted performance values over designated operating temperatures) cannot be achieved in electroceramic capacitors formed from powder preparations due to their inability to control ceramic microstructure with the requisite precision. Although, recent advances in nano-powder technology claim fine powder preparations ranging from 10 nm to 80 nm, powder preparations do not permit uniform control over particle diameter. Particle diameter is typically defined as the length of the particle&#39;s major axis. In general, a given powder preparation will consist of a distribution of particle sizes with an average diameter, wherein 20%-30% of the distribution by volume will include particle diameters that are &gt;1.5× larger than the distributions&#39; average. Although the relationship between grain size (particle diameter) and value of dielectric performance is not linear, however, the curves for  202  and  204  in  FIG. 8  clearly show that a simple doubling of grain size (particle diameter) of BST electroceramic can produce a dielectric response value that can be 2-3× larger than the average. Furthermore, powder processes require subsequent heat treatments to sinter or convert the ceramic that initiates larger grain growth, which heat treatments cannot be uniformly controlled to high precision with a distribution of particle sizes. Thus, even a narrow distribution of particles is not sufficient to control electroceramic performance tolerances to within ±1% of targeted values over standard operating temperatures. Certain electroceramics, particularly those compositions containing neodymium oxide (Nd 2 O 3 ), will exhibit dielectric properties that are stable with temperature, but they will, in general also have, low relative permittivity, ∈ R ≦40. Therefore, electroceramics and methods or fabrication that provide devices with high relative permittivity (∈ R ≧50), precise control over targeted values (tolerances&lt;±1%), and stable thermal performance are desirable.
 
     LCD electroceramics deposits initially form as a solid solution without any discernible grains. Subsequent heat or laser treatments can be used to supply energy to the electroceramic to nucleate specific microstructure states. The rate of grain growth within the ceramic is dependent upon the precise chemical composition at a nucleation site. LCD controls ceramic composition very precisely (≦±1.5%) throughout the deposit to assure uniform grain growth when energy in sufficient quantities is supplied to initiate nucleation. Thus a specific embodiment of the invention is its ability to fabricate capacitors using high permittivity ceramic electroceramics (∈ R ≧50), generally known to exhibit ferroelectric behavior, that are provided stable temperature performance through uniform microstructure with grain sizes &lt;70 nm, preferably &lt;50 nm. In a further embodiment of the present invention, said capacitors are embedded within a circuit board or interconnect structure. 
     Reference is now made to  FIGS. 9-12  to illustrate methods to fabricate electroceramic compositions useful to the design and construction of passive components having performance tolerances and thermal stability ≦±5%, preferably ≦±1%, that provide high performance functions for high frequency components. To achieve this goal, methods are provided to deliver a plurality of LCD precursor materials in selective locations across a single substrate layer, as well as methods to apply a single layer of high-quality electroceramic uniformly across an entire substrate surface. LCD materials fabrication starts with a solution preparation step that consists of reacting the metal precursors with a carboxylic acid solvent, preferably a carboxylic acid of rank 5 or higher, to form a carboxylic acid salt solution  206 A,  206 B, . . . ,  206 N for each metal oxide incorporated into the final deposit. A single component solution is used when the objective is to fabricate a single component (one metal oxide), a plurality of single component solutions are prepared when it is desirable to synthesize a mixed metal oxide material. Two carboxylic acid salts, 2-ethylhexanoate and neo-decanoate, are preferred for their superior liquid film forming and efficient pyrolytic decomposition properties. A preferred method to form a carboxylate salt involves driving an exchange reaction between said carboxylic acid with an initial high volatility lower rank metal precursor, such as an acetate salt, through vacuum distillation and filtering. While acetate salts represent a suitable lower rank precursor for use in the LCD process, other lower rank high volatility precursors can be used without restriction. Certain metals or semi-metals, such as titanium or silicon, have a very strong affinity to hydroxyl groups (OH − ), and an ideal chemistry for LCD processing can be permanently destroyed if these compounds are exposed to even minute amounts of oxygen or water vapor. In this instance, it is necessary to react these air/moisture-sensitive compounds in a dry, inert gas atmosphere, such as helium, argon, or dry nitrogen and to package, store, and handle the solutions under glove box conditions. In this instance, the inert gas should be introduced as purge gas into the vacuum distillation column. 
     The reacted solutions are then assayed to determine a precise molar concentration  208 A,  208 B, . . . ,  208 N. Inductively-coupled plasma atomic emission spectroscopy (ICP-AES) is the preferred assay method. The assayed solutions are then titrated and thoroughly blended to form a mixed solution  210  that contains a molar stoichiometry known to produce the desired stoichiometry after spray deposition when a multi-component electroceramic is desired. The mixed precursor solution is then filtered once more after blending the plurality of precursors. Solution stoichiometry will differ from the deposit stoichiometry and depend very strongly on specific characteristics of the deposition system. The precursor solution may have to be enriched with certain metal cation concentrations that might be prone to higher loss rates during the deposition process; however, metal cation loss rates are extremely predictable when all process parameters are tightly controlled. Solutions prepared with high rank carboxylate solutions are capable of dissolving high molar concentrations of carboxylic acid salts. Metal densities in solution are more conveniently expressed in terms of their percentage weight of equivalent oxides (wt % equiv. oxide), which allows a quick calculation to determine how much solid oxide material will be created from a given quantity of solution. For instance, 100 gms of a solution that has an 10% wt % equiv. oxide, will produce 10 gms of metal oxide material after the entire quantity of material has been deposited. In general, it is advisable to prepare solutions to have wt % equiv. oxide ranging from 0.001% to 25%, preferably 0.1% to 20%. Dilute solutions (0.001% to 1% wt % equiv. oxide, are preferred when making thin film materials (&lt;1 micron thickness) using liquid aerosol spray deposition. More concentrated solutions, 1% to 25% wt % equiv. oxide, are preferred when fabricating precursor waxes, thick films (1 micron≦deposit thickness &lt;1 mm), or bulk materials (thickness ≧1 mm). The prepared solution may then be deposited on a substrate heated to temperatures between 200° C. and 500° C., preferably 250° C. and 430° C., using a liquid aerosol spray  212  for curtain coating processes, or for blanket coating processes when it is intended to completely cover the substrate surface area. The deposition is then followed by a bake out step  213  at temperatures ranging between 300° C. and 600° C., preferably 350° C. and 450° C., to remove any residual organic material remaining in the deposit after the deposition process. Controlled gas atmospheres comprising dry air, an inert gas, such as nitrogen, helium, argon, or others, with or without partial pressure redox gases, such as oxygen, or mixtures of carbon monoxide and carbon dioxide may also be applied during the bake out process to accelerate the removal or residual organic compounds. The bake out step  213  may also comprise a rapid thermal annealing step. Most often, the deposited material remains as a solid solution with no visible crystallization after the bake out step  213 . It is usually desirable to render the deposited material into an advanced state of crystallization with a precisely controlled microstructure therefore an optional annealing step  214 , preferably a rapid thermal annealing step, is applied. Focused pulsed laser light, using a wavelength that is absorbed by the medium, is a preferred process to be used in the rapid thermal annealing step because it allows a very high degree of control over the energy/power delivered to the deposit during the optional annealing step  214 . It is advantageous to use the pulsed laser light annealing in conjunction with other thermal controls described above. 
     A low cost technique to disperse a variety of ceramic compositions useful as passive components in selective locations over a single sheet or layer is preferred. A low cost technique to disperse a variety of ceramic compositions in selective locations over a single sheet or layer at room temperature or temperatures below 250° C. is also preferred. As a solution process, LCD technology is amenable to direct-write processing, which allows multiple material compositions to be applied locally on a single layer. While inkjet deposition systems would be a likely choice for this objective, a solid-solution deposit is preferred to realize the microstructure controls that achieve the best tolerances. As noted above, the solid-solution is formed when all liquid precursors are decomposed simultaneously. A multi-component precursor solution applied to the substrate at low temperature that is subsequently ramped through all precursor decomposition temperatures would initiate the sequential decomposition of multiple precursors. Sequential decomposition favors all the individual metal oxides to segregate from the solution as nano-nucleates that remain dispersed throughout the deposited material, which is disadvantageous to microstructure control. Applying the solutions to a substrate heated to temperatures sufficient to initiate the simultaneous decomposition of all metalorganic precursors preserves the molecular-level mixing achieved in the liquid solution. The boiling solvent and decomposition products generated with the simultaneous decomposition produces a “steam” of waste products to emanate from the deposit. This is disadvantageous to inkjet deposition systems as the steaming waste products will contaminate the printing heads. As shown in  FIGS. 10A, 10B , localized deposition of multiple solutions can be achieved by applying a first liquid aerosol spray  218 A of one particular precursor solution through a perforation  224  in a first solid mask  220 A that is located above the heated substrate  222 . This allows a first ceramic composition  226 A to form on the substrate  222  in a select location. A second ceramic composition  226 B ( FIG. 10B ) can then be formed in a second location by applying a second liquid aerosol spray  218 B through a perforation in a second solid mask  220 B. The solid masks  220 A,  220 B should have recesses  228  in the vicinity of the perforations  224  that prevent the solid masks  220 A,  220 B from pulling off the deposited ceramic compositions  226 A,  226 B when they are removed from the surface of the substrate  222 . This method can be used to provide a plurality of ceramic compositions that have properties useful as resistors, capacitors, or inductors, or to provide ceramic compositions that might provide differing performance values for a set of resistor components, or a set of capacitor components or a set of inductor components at selective locations on the substrate&#39;s surface. 
     Another specific embodiment of the invention includes methods to locate a plurality of ceramic compositions at selective locations on the substrate surface at lower deposition temperatures. In this instance, the solvent is completely removed from mixed solution  210  using a solvent extraction step  215  ( FIG. 9 ) to render the precursor into a solid wax that can be applied selectively to a substrate surface using a traditional wax printing system  216 . Inter-molecular forces within the waxy solid phase are strong enough to preserve the level of molecular mixing created in solution that inhibits phase segregation into single species oxides when the waxy solid is subsequently decomposed into the desired metal oxide ceramic. The creation of a solid wax phase precursor allows a number of conventional printing techniques to be used to deposit a plurality of different ceramic compositions on a single surface.  FIG. 11  depicts one method that uses a plurality of wax sticks  230 , each of which may contain precursors to a distinct ceramic composition, that are locally heated at the printer head  232  to liquefy the end of wax sticks  230  to cause droplets  234  of the precursor wax to solidify into a solid wax deposits  236  at selective locations across the surface of substrate  238  as the print head  232  traverses the substrate. The molten wax droplets  234  emerging from the printer head  232  may also be accelerated and directed by an inkjet processing stage  239 . 
     FIGS.  12 A 1 ,  12 A 2 ,  12 B make reference to an alternative wax printing technique wherein a plurality of wax precursor compositions  240 A,  240 B,  240 C,  240 D, etc. are applied to the surface of a tape  242  to form a precursor ribbon  244  with an alternating pattern of wax precursor compositions. One or more precursor ribbons  244  can then be feed off of a spool through a printing head  246  ( FIG. 12B ) that has an array of fine heated needles  248 . Selective needles  248 A in the array of needles  248  can be brought into contact with the precursor ribbon  244  as it passes in front of a print head and cause a specific precursor wax to melt into droplets  250  that adhere to a pre-selected location on the substrate  252 , where it hardens in place as a solid precursor wax deposit  254 . 
     The simultaneous decomposition of liquid aerosols at a substrate&#39;s surface generates a free-radical chemistry that causes the depositing metal oxides to bond aggressively to metal and dielectric surfaces. The decomposition cycle of the wax-based precursor does not share the same level of aggressive free-radical bonding between the metal oxide deposit and the substrate. These deposits show a preference for bonding to oxide surfaces over clean metallic surfaces. In this instance, a thin oxide layer  256  can be applied to the surface of a metallic electrode  258 , to which wax precursors  254  will be applied to form an electroceramic. In order to better achieve performance tolerances and thermal stability ≦±5%, preferably ≦±1%, it is preferable to avoid the sequential decomposition of wax precursors that may cause agglomerations of single species oxides that disrupt fine microstructure controls. To maximize decomposition rates of the solid precursor wax deposits  254  an ultraviolet-assisted (UV-assisted) pyrolysis step  217  ( FIG. 9 ), preferably a UV-assisted rapid thermal annealing pyrolysis step using focused energy in the form of microwave, infrared, or ultraviolet radiation, is applied to accelerate the initial decomposition of printed wax precursors into a solid solution of metal oxides. The UV-assisted pyrolysis step  217  is then followed by bake out step  213 , and optional annealing step  214 . 
     Reference is now made to  FIGS. 13A-27B  to describe physical embodiments for passive components having performance tolerances and thermal stability ≦±5%, preferably ≦±1% that are embedded within a circuit board or interconnect structure. A particular embodiment of the invention utilizes the selective deposition methods discussed above to form a plurality of passive components having a wide range of resistance, capacitance, inductance and impedance values on single layer. This embodiment may comprise a single class of passive component, for instance resistors only, or may combine all classes of passive components (resistors, capacitors, and inductors) on the single layer. As shown in  FIGS. 13A, 13B , a discrete resistor element  270  consists of at least two conducting electrodes  260 A,  260 B that are affixed to a sacrificial substrate or layer  262 . The at least two conducting electrodes  260 A,  260 B are derived from a low resistivity metal, such as copper, silver, or gold, or other metal or metal alloy with superior conducting properties. The two conducting electrodes  260 A,  260 B may be photolithographically patterned from thin film material, or they may be formed by direct-write methods, such as screen-printing or inkjet printing. Sacrificial layer  262  can be a peel-apart foil that generally comprises a high quality thin film used to form the conducting electrodes, a chemical stop layer, such as a chromate monolayer, and a more mechanically rugged carrier foil or plate. Sacrificial layer  262  may also comprise a dielectric surface. The materials selection for sacrificial layer  262  is predicated on its ability to withstand all future processing steps and the ease with which it can be removed at an appropriate point in the fabrication process. Resistive electroceramic  264  is selectively deposited between the conducting electrodes  260 A,  260 B. The thickness  265  of the resistive electroceramic  264 , the width  266  of resistive electroceramic  264 , and the spacing  268  between the two conducting electrodes  260 A,  260 B, are all selected to produce a targeted performance value for the resistive element  270 , given the intrinsic resistivity (measured in Ω-cm) of the resistive electroceramic  264 . The resistance value of a resistor element can also be finely tuned by laser trimming, which carves a recess  271  into the resistive electroceramic. 
     The intrinsic resistivity of the resistive electroceramic  264  is dependent upon electroceramic chemical composition and microstructure. Elemental resistors are characterized as having intrinsic sheet resistivity greater than 25 μΩ-cm. As mentioned above, LCD resistive electroceramic will exhibit the properties of an amorphous phase solid-state solution immediately after the bake-out step  213  ( FIG. 9 ). Subsequent annealing steps  214  will nucleate grains within the deposit. The amorphous phase, which effectively has 0 nm grain size, will exhibit the greatest intrinsic resistivity. Electrical conductivity is generally greatest within a grain, and impaired as the current traverses a grain boundary. Therefore, a unit volume of a given electroceramic composition will have its highest intrinsic resistivity when it has 0 nm grain size, and will have its lowest intrinsic resistivity when that unit volume comprises a single grain. Similarly, a unit volume of resistive electroceramic comprising a large number of small grains (and grain boundaries) will have higher intrinsic resistivity than the same unit volume of identical electroceramic comprising a smaller number of grain boundaries and larger grains. It is often convenient to bundle passive components in arrays, wherein each component in the array could have identical resistance values. Alternatively, it is desirable for the passive component arrays to contain individual components that have sharply different resistance values. 
     A specific embodiment is shown in  FIGS. 14A, 14B  where each resistive electroceramic  272 A,  272 B,  272 C, . . . ,  272 N, in an array  273  of resistive elements  274 , is formed with identical volumes of identical electroceramic material to be selectively annealed using focused radiation such that each resistor element  275 A,  275 B,  275 C, . . . ,  275 N, has different microstructure (grain size) and a measurably different resistance value. An additional embodiment for resistor arrays includes an array  276  of resistor elements  277 A,  277 B,  277 C, . . . ,  277 N, consisting of resistive electroceramic  278 A, . . .  278 N having identical composition and microstructure, wherein a significant physical dimension, such as the length of the resistor element (as shown),  279 A,  279 B,  279 C, . . . ,  279 N is altered to produce different resistance values. It is understood that the alterable significant physical dimension can alternatively be the resistive element thickness  265  or its width  266  as shown in  FIGS. 13A, 13B . Yet another embodiment includes an array  280  in which selective deposition is used to produce resistors elements  282 A,  282 B,  282 C, . . . ,  282 N that have different electroceramic compositions  284 B,  284 C, . . . ,  284 N and significantly different resistance values. 
     Resistive electroceramic compositions are usually classified in terms of their crystal structure and typically contain the following metal oxides as a primary component: copper oxide (CuO), nickel oxide (NiO), ruthenium oxide (RuO 2 ), irdium oxide (IrO 2 ), rhomdium oxide (Rh 2 O 3 ), osmium oxide (OsO 2 ), and antimony oxide (Sb 2 O 3 ). This group of primary metal oxides comprises the group of preferred electroceramic compositions. These single component resistive electroceramics adopt a rutile crystal structure, with the exception of antimony oxide (Sb 2 O 3 ) and rhomdium oxide (Rh 2 O 3 ), which have a trigonal crystal structures, and copper oxide (CuO) and nickel oxide (NiO), which have a cubic close-packed crystal structure. Intrinsic resistivity of the primary metal oxides with rutile crystal structures can be altered when the rutile primary oxides are combined together and with one or more transition-metal oxides and/or heavy-metal oxides in amounts that crystallize into a pyrochlore crystal structure. Intrinsic resistivity of the primary metal oxides with rutile crystal structures can also be altered when the rutile primary oxides are combined together and with one or more alkaline earth metal oxides and heavy-metal oxides in amounts that crystallize into a perovskite crystal structure. The compositional chemistry of these crystal structures generally adopt the following formulas:
 
M (1) M (2)   2 O 7 (pyrochlore)  (2a)
 
M (3) M (2) O 3 (perovskite).  (2b)
 
Where M (1)  represents one or more trivalent transition-metal oxides and/or one or more trivalent heavy-metal oxides, M (2)  represents one or more of the primary metal oxides with rutile crystal structure cited above, and M (3)  represents one or more alkaline earth metal oxides. Preferred trivalent transition-metal oxides are from the group consisting of: scandium oxide (Sc 2 O 3 ), titanium oxide, (Ti 2 O 3 ), vanadium oxide (V 2 O 3 ), chromium oxide (Cr 2 O 3 ), manganese oxide (Mn 2 O 3 ), iron oxide (Fe 2 O 3 ). Preferred heavy-metal oxides are drawn from the group consisting of bismuth oxide (Bi 2 O 3 ), lanthanum oxide (La 2 O 3 ), cerium oxide (Ce 2 O 3 ), lead oxide (PbO) and neodymium oxide (Nd 2 O 3 ). Preferred alkaline earth metal oxides are drawn from the group consisting of magnesium oxide (MgO), calcium oxide (CaO), strontium oxide (SrO), and barium oxide (BaO). Indium-tin oxide (ITO) and antimony-tin oxide are preferred electroceramic compositions when there is a need to have an optically transparent conductor or resistive element, for instance in optical display applications.
 
     As shown in  FIG. 15 , electroceramic intrinsic resistivity can be increased if a strongly insulating oxide, such as silicon dioxide or aluminum dioxide precursor, is added in small amounts, 0.001-10 mol %, preferably 0.1-3 mol % to the solid state solution. These strongly insulating oxide phases  286  will separate out from resistive electroceramic phases  288  during the annealing step causing the combined mixed phase material  290  to have higher intrinsic resistivity. 
     As will be described below, a specific need of the invention requires electroceramic resistors having a wide range of resistance values, allowing the user to select precise resistance values from 1Ω to 500 mega-Ω, preferably resistance values selected from 10Ω to 50 mega-Ω. A further need requires these electroceramic resistor need to have thermal stability and performance tolerances ≦±5%, preferably ≦±1%, and to be integrated into at least one layer of a circuit board or interconnect that is in electrical communication with a semiconductor chip or another passive circuit element, including an antenna. The wide range of resistance values are derived by selectively depositing appropriate electroceramic compositions or appropriate electroceramic compositions blended with a small amount of strongly insulating oxides and controlling the microstructure of the electroceramic composition to have grain size ranging from 0 nm to 10 microns, preferably ranging from 0 nm to 2 microns. 
     Reference is now made to  FIGS. 16A, 16B, 16C, and 16D , to describe methods to embed a plurality of discrete resistors or resistor arrays into a circuit board or interconnect structure.  FIG. 16A  shows a top view of a substrate  296  having a discrete resistor  292  and a plurality of resistor arrays  294  selectively deposited at precise locations within a pad and trace electrode network  295  that is patterned on sacrificial substrate  296 . The pad and trace electrode network  295  is used to route signals vertically and within the plane of the discrete resistors. The resistive electroceramic in each resistor element forming the discrete resistors  292  or resistor arrays  294  is selectively annealed using laser processes to render the resistive electroceramic composition(s) into a microstructure state that meets the targeted resistance value. The individual resistors may be tested and reworked, either through additional selective annealing or laser scribing, prior to further processing. 
     Once all resistor elements are fabricated within desired tolerances, an insulating dielectric layer  298 , a metallization layer  300 , and vertical interconnects (vias)  301  that maintain electrical communications between the metallization layer  300  and the pad and trace electrode network  295  are then applied to the structure as shown in  FIG. 16C . The dielectric layer  298  may be an organic material, such as FR4, polyfluorotetraehylene (PFTE) Teflon, or Rogers Duroid materials. Alternatively, the dielectric layer  298  may be an LCD processed inorganic material, such as silica, alumina, or a silicate or aluminate dielectric using a curtain coating or blanket coating liquid aerosol spray. The metallization layer  300  may comprise ground or power planes, or may be patterned to function as a signal routing network. The metallization layer  300  may be applied using a variety of techniques, such as a metal sheet that is bonded to the dielectric layer through an adhesive agent, or through direct-write methods, such as screen printing or inkjet printing, preferably using low-temperature nano-particle pastes. It is recommended to use a low-temperature metallization technique so the formed structure is subject to maximum temperatures that will not alter the microstructure of the embedded electroceramic. The layer structure  302  comprising at least one pre-tested embedded resistor element  292  or resistor array  294  in electrical communication with a pad and trace electrode network  295  and the metallization layer  300  is then separated from the sacrificial substrate  296 . 
     The embedded resistor layer structure  302  can then be combined with one or more additional signal routing layers  304 A,  304 B into a stacked multilayer structure  305  as shown in  FIG. 16D . Signal routing layers  304 A,  304 B contain vias  306 A,  306 B within a dielectric material  307 A,  307 B that maintain electrical communication between the metallization layers  308 A,  308 B of each signal routing layer  304 A,  304 B and the embedded resistor components  292  and  294 . The metallization layers  308 A,  308 B may include, in whole or in part, signal traces or power and or ground planes. This embodiment thereby provides electrical communication between the embedded resistor  292  and resistor arrays  294  and a semiconductor device  310  through conductive means  312  in electrical contact with a surface metallization layer  308 B, or an external device (not shown) through an electrical contact  314  located on the periphery of the stacked multilayer structure  305 . 
     Reference is now made to  FIGS. 17A, 17B, 17C, 17D, 17E, 17F, and 17G  that describe methods to embed discrete capacitor components having thermal stability and performance tolerances ≦±5%, preferably ≦±1%, within a printed circuit board or an interconnect structure. As shown in  FIGS. 17A, 17B , the discrete parallel plate capacitor  316  is one embodiment for a discrete capacitor element. It consists of dielectric material  317  having relative permittivity ∈ R ≧10, preferably ∈ R ≧100, inserted between a top electrode  318  and a bottom electrode  319 . The relative permittivity (∈ R ) and thickness (d)  321  of the dielectric material  317 , and the surface area  322  of the top  318  or bottom  319  electrodes, which ever is smaller, principally determine the total capacitance of the discrete capacitor element  316 , in accordance with equation (1). The parallel plate capacitor is assembled by patterning the bottom electrode  319 , at least one trace conductor  323  and a via pad  324  in a metallization layer affixed to a sacrificial substrate  325 , using the methods discussed above. Tight dimensional controls on the dielectric thickness  321  and the electrode surface areas  322  are required to achieve high tolerance. A preferred embodiment for a discrete capacitor element is shown in  FIGS. 17C, 17D, 17E, 17F and 17G . The inter-digitated capacitor  326  incorporates two opposed electrodes  328 A,  328 B that are patterned into a single metallization layer that has been applied to a sacrificial substrate  330 . Each electrode has respective electrode fingers  332 A and  332 B that are interleaved with the fingers of the opposed electrode to produce meandering line capacitance in the gap between the two sets of fingers. High permittivity electroceramic  333  ( FIGS. 17E, 17F ) is selectively deposited on and between the electrode fingers  332 A,  332 B to fill the gap spacing  334  that exists between the opposed electrode fingers  332 A,  332 B and complete the capacitor  326 . To first order, the capacitance is determined by the gap spacing  336  between fingers  332 A and  332 B, the mean finger length  337  and the dielectric permittivity of the electroceramic  333 . Therefore, manufacturing to high tolerance is limited to maintaining tolerance controls over a two process parameters: the accuracy of the patterned electrode fingers  328 A,  328 B and the chemical/microstructure properties and thickness  338  of the high permittivity electroceramic  333 . The occurrence of strong fringing fields  339  ( FIG. 17D ) that protrude above the electrodes  328 A,  328 B is an artifact of inter-digitated capacitors that can affect tolerances. The extent to which these fields protrude is inversely proportional to the relative permittivity (∈ R ) of the high-κ electroceramic  333 . The high permittivity electroceramic  333  should have a relative permittivity ∈ R ≧50, and preferably ∈ R ≧100, with respective thicknesses  338  ( FIG. 17F ) that are ≧10 μm, and ≧6 μm, respectively, to mitigate the affect of fringing fields on tolerance. Performance tolerance controls are also improved by maintaining uniform line capacitance within the device. Therefore, it is an additional preferred embodiment to utilize curved edges  340 A,  340 B ( FIG. 17G ) at the end points where the electrode fingers  332 A,  332 B interlock to preserve uniform spacing  334  throughout the capacitor&#39;s meander path. The discrete inter-digitated capacitor  326  maintains electrical communication to via pads  342 A,  342 B through one or more electrical traces  344 A,  344 B making electrical contact with the electrode fingers  332 A,  332 B. 
     A further need of the invention includes distributed sheet capacitance or decoupling capacitors that have COG-type behavior. COG-type behavior refers to a capacitance value that changes ≦±250 ppm/° C. Therefore, a COG-type capacitor will hold its performance value within 4.1% of its target over temperatures ranging from 40° C. to 125° C. As noted above, decoupling capacitors have value in suppressing power noise. Reference is now made to  FIGS. 18, 19A, and 19B  to describe a method to fabricate a sheet capacitor  355  having sheet capacitance ≧20 nf/inch 2 , preferably having sheet capacitance ≧150 nf/inch 2 , and has performance tolerance ≦±5%, preferably ≦±1% over the temperature range from −40° C. to 125° C. High permittivity LCD electroceramic  346  is applied to a conducting sheet electrode  348  that is affixed to a sacrificial substrate  350 . More specifically a reusable metal foil, such as a nickel foil, provides malleable, yet stable mechanical substrate to the thin films assembled on its surface. The thickness  351  of the conducting sheet electrode  348  ranges between 1 μm and 2 mm, preferably 20 μm and 200 μm. High permittivity electroceramic  346  is applied to the conducting sheet electrode  348  using the LCD liquid aerosol spray process described in  FIG. 9 , and subjected to an annealing process, preferably a rapid thermal annealing process, that renders the high permittivity electroceramic  346  into a paraelectric microstructure that provides maximal relative permittivity, ∈ R ≧50, preferably ∈ R ≧150, and stable thermal performance. The high permittivity electroceramic  346  has thickness  352  in the range of 10 nm to 2 mm, preferably 500 nm to 100 μm. A top electrode layer  353  is applied using a low-temperature nano-particle paste to have thickness  354  ranging from 1 μm to 1 mm, preferably 25 μm to 50 μm. The sacrificial substrate  350  is removed to produce sheet capacitor  355  prior to inserting it into a printed circuit board or interconnect structure. 
       FIGS. 19A and 19B  depict an alternative method to fabricate a sheet capacitor  356 . High permittivity electroceramic  358 A,  358 B is applied to two separate conducting metal foils  360 A,  360 B to produce metal-ceramic laminates  362 A,  362 B. The metal-ceramic laminates  362 A,  362 B are then brought together ceramic-face  364 A to ceramic face  364 B. The combined metal-ceramic-metal structure  356  is then hot-pressed/hot-rolled at temperatures ranging from 600° C. to 900° C. for a period ranging from 2 minutes to 2 hours, preferably 5 minutes to 1 hour, to render the high permittivity electroceramic  366  into a paraelectric microstructure that provides maximal relative permittivity, ∈ R ≧50, preferably ∈ R ≧150, and stable thermal performance. Applied mechanical pressure  368  should range between 5 tons/inch 2  and 200 tons/inch 2 . A dry atmosphere that does not contain oxygen is used for oxidation-sensitive metals, such as copper. In this instance, reduction-oxidation (redox) controls can be established using partial-pressure carbon monoxide/carbon dioxide mixtures in the oxygen-free atmospheres. 
     As noted above, a thermally stable capacitance value is a specific objective.  FIG. 8  depicts how fine control over microstructure can stabilize electroceramic relative permittivity. Electroceramic composition impacts dielectric strength. High permittivity is related to high electron density of the material. Therefore, electroceramic compositions comprised of heavy-metal oxides are preferred when maximizing relative permittivity, as the heavy-metals contribute higher electron densities. A specific embodiment of the invention provides thermal stability to discrete capacitors  316 ,  326  or sheet capacitors  356  by limiting the microstructure of the above referenced high permittivity electroceramics to grain sizes ≦70 nm, preferably ≦50 nm throughout the LCD deposits. Embedded capacitors components (discrete or sheet) having thermally stable capacitance values ranging from 0.01 pF to 900 μF with tolerances of ≦±5%, preferably ≦±1%, is a specific embodiment of the invention. 
     High permittivity electroceramics preferred under this invention have perovskite crystal structures and will generally have the following chemical formula.
 
M (1) M (2) O 3   (3a)
 
Where metals from group M (1)  and M (2)  exist in 1:1 molar ratios. It is possible for a plurality of metals to be represented within each group; however, the combined molarity for each group must remain the same. For instance, if two metals, M (1a) , M (1b) , are selected from group M (1)  and two other metals are selected from group M (2) , the chemical formula (3) is modified as:
 
M (1a)   (1-x) M (1b)   (x) M (2a)   (1-y) M (2b)   (y) O 3 .  (3b)
 
Group M (1)  metal oxides preferred for use in high permittivity electroceramics include: alkaline earth metal oxides selected from the group consisting of magnesium oxide (MgO), calcium oxide (CaO), strontium oxide (SrO), and barium oxide (BaO); alkali metal oxides selected from the group including lithium oxide (Li 2 O), sodium oxide (Na 2 O), potassium oxide (K 2 O), and rubidium oxide (Rb 2 O); and heavy-metal oxides selected from the group including lanthanum oxide (La 2 O 3 ), cerium oxide (Ce 2 O 3 ), lead oxide (PbO) and neodymium oxide (Nd 2 O 3 ). Group M (2)  metal oxides preferred for use in high permittivity electroceramics include: titanium oxide (TiO2), zirconium oxide (ZrO), hafnium oxide (HfO), tantalum oxide (Ta 2 O 5 ), and niobium oxide (Nb 2 O 5 ).
 
     Reference is now made to  FIGS. 20A, 20B, and 20C  to describe methods to integrate discrete capacitors and sheet capacitors into an embedded discrete capacitor layer  369  that can subsequently be incorporated into a printed circuit board or interconnect structure. Discrete parallel plate capacitors  370  or capacitor arrays  371  and inter-digitated capacitors  372  or capacitor arrays  373  are fabricated on a sacrificial substrate  374 . Each discrete parallel plate capacitor  371 ,  372  possesses via pads  375  and upper electrodes  376  that are used to make subsequent electrical connections. Each discrete inter-digitated capacitor  372 ,  373  possesses two via pads  377  that are used to make subsequent electrical connections. As shown in  FIG. 20C , once all capacitor elements are fabricated within desired tolerances, an insulating dielectric layer  378 , a metallization layer  380 , and vertical interconnects (vias)  382  that maintain electrical communications between the metallization layer  380  and the via pads  375 ,  377  or upper electrodes  376  (where desired) are then applied to the structure. The dielectric layer  378  may be an organic material, such as FR4, polyfluorotetraehylene (PFTE) Teflon, or Rogers Duroid materials. Alternatively, the dielectric layer  378  may be an LCD processed inorganic material, such as silica, alumina, or a silicate or aluminate dielectric using a curtain coating or blanket coating liquid aerosol spray. The metallization layer  380  may comprise ground or power plane, or may patterned to function as a signal routing network. The metallization layer  380  may be applied using a variety of techniques, such as a metal sheet that is bonded to the dielectric layer through an adhesive agent, or through direct-write methods, such as screen printing or inkjet printing, preferably using low-temperature nano-particle pastes. It is recommended to use a low-temperature metallization technique so the formed structure is subject to maximum temperatures that will not alter the microstructure of the embedded electroceramic. The embedded discrete capacitor layer  369  comprising at least one pre-tested embedded discrete capacitor element  370  or  371  in electrical communication with a via pad  375 ,  377  or via  382  is then separated from the sacrificial substrate  374  for use in a printed circuit board or interconnect structure. 
     Reference is now made to  FIGS. 21A, 21B and 22  to describe methods to embed discrete and sheet capacitors with COG-type behavior into a printed circuit board or interconnect structure. As shown in  FIGS. 21A, 21B , conducting electrode material from sheet capacitor with COG-type behavior is selectively removed using a subtractive process to produce a sheet capacitor layer  384  containing one or more parallel plate capacitors  386 A,  386 B with floating ground planes  388 A,  388 B and a metallization layer  389  that contain signal traces  392 , pads  393 , or functions as a power plane  394 . The sheet capacitor layer  384  and/or an embedded discrete capacitor layer  369  ( FIG. 20C ) can then be combined with one or more additional signal routing layers  396 A,  396 B,  396 C into a stacked multilayer structure  398 . Signal routing layers  396 A,  396 B,  396 C contain vias  400 A,  400 B,  400 C and metallization  404 A,  404 B,  404 C used to conduct signals within dielectric material  402 A,  402 B,  402 C. This electrical network is used to maintain electrical communication between the embedded capacitor components  406 A,  406 B,  408 A,  408 B and  410 A,  410 B and a semiconductor device  412  through conductive means  414  in electrical contact with a surface metallization layer  404 A, or an external device (not shown) through an electrical contact  416  located on the periphery of the stacked multilayer structure  398 . 
     Reference is now made to  FIGS. 23A, 23B, 23C, 23D, 23E, 23F and 23G  to describe methods to embed at least one ceramic inductor coil within a dielectric layer that can be integrated into printed circuit board or interconnect structure. A patterned metallization layer  418  is affixed to a sacrificial substrate  419  ( FIG. 23A ). The patterning in the metallization layer  418  provides two sets of pads  420 A,  420 B,  420 C, . . . ,  420 N and  421 A,  421 B,  421 C, . . . ,  421 N that are used to construct the coil windings, at least one conductive trace  422 , and at least one via pad  424  in  FIG. 23B  to route signals within the layer that contains the inductor coil or to route signals to other layers that maintain electrical communication with the layer. A first set of conducting elements  425 A,  425 B,  425 C, . . . ,  425 N are inserted between conducting pads  420 A and  421 A,  420 B and  421 B,  420 C and  421 C, and  420 N and  421 N, respectively, to form the lower half of the coil ( FIG. 23C ). The conducting elements may be formed within the patterned metallization layer  418  or, preferably, they may comprise round wire bonds, which have higher self-inductance and lower resistivity. An electroceramic  426  ( FIG. 23D ) having relative permeability μ R ≠1 is selectively deposited between the two sets of pads ( 420 A,  420 B,  420 C, . . . ,  420 N and  421 A,  421 B,  421 C, . . . ,  421 N) and over the conducting elements  425 A,  425 B,  425 C, . . . ,  425 N ( FIG. 23D ). Vertical interconnects  427 B,  427 C, . . . ,  427 N and  428 A,  428 B,  428 C, . . . ,  428 (N−1) ( FIGS. 23E, 23F ), preferably metal studs, having height  430  equal to or 10-20% greater than the thickness of magnetic electroceramic  426  are inserted on pads  420 B,  420 C, . . . ,  420 N and  421 A,  421 B,  421 C, . . . ,  421 (N−1), respectively. The thickness of deposited magnetic electroceramic  426  should be in the range 10 μm≦t≦5,000 μm, preferably in the range 100 μm≦t≦500 μm.  FIG. 23G  shows how the ceramic inductor coil  432  is completed by stitch bonding a second set of conducting wire elements  434 A,  434 B,  434 C, . . . ,  434 (N−1), between vertical interconnects  428 A and  427 B,  428 B and  427 C,  428 C and  427 (C+1), . . . ,  428 (N−1) and  427 N, respectively. The inductance L of the ceramic inductor coil  432  is determined by:
 
 L=N   2 μ o μ R A/ l   (4)
 
Where N is the number of turns in the coil, μ o =4π×10 −7  H/m, μ R  is the relative permittivity of the electroceramic  426 , A is the cross-sectional area of a single turn in the coil, and l is the length of the coil. The resistance, dimensional uniformity, and surface roughness of the metal conductor used to fabricate the coil, and the precision placement of the all conducting elements are key tolerance parameters, which is why wire bonding methods are preferred. Stud bumping and stitch bonding equipment having a bond placement accuracy &lt;±5 μm, preferably ≦±3.5 μm, a height accuracy of &lt;±10 μm, preferably ≦±3 μm, and a minimum pitch of 60 μm, preferably 50 μm, such as that provided by the AT Premier (in AccuBump mode), K&amp;S, Willow Grove, Pa., are recommended process tools. Laser trimming the selectively deposited electroceramic  426  is recommended to maintain accurate control over dimensional tolerances.
 
     Controlling the permeability of the inductor coil electroceramic  426  to a value ≦±5%, preferably ≦±1%, is another specific embodiment of the invention. It is another specific embodiment of the invention to produce elemental ceramic inductor coils providing inductance in the range of 0.01 pH to 500 nH with performance values ≦±5%, preferably ≦±1% of the targeted value. Electroceramic permeability is primarily a function of electroceramic composition, grain size, and is usually dependent upon frequency and temperature. Preferred electroceramic compositions for use in a ceramic inductor coil include ferrites and garnets. Ferrites adopt body-centered cubic crystal structure and have the following chemical formula:
 
M 1 Fe 2 O 4   (5a)
 
Where Fe is iron oxide and M 1  represents one or more select metal oxides having a total molar concentration that is half the iron oxide molar concentration. Group M 1  metal oxides preferred for use in high permeability ferrite electroceramics include: cobalt monoxide (CoO), nickel oxide (NiO), zinc oxide (ZnO), manganese oxide (MnO), copper oxide (CuO), vanadium oxide (VO), magnesium oxide (MgO) and lithium oxide (Li 2 O). Garnets adopt either rhombic dodecahedron or trapezohedron crystal structures, or a combination of the two, and have the following chemical formula:
 
A 3 B 2 (SiO 4 ) 3   (5b)
 
Where group A metal oxides have equal molar concentration to silicon oxide and group B metal oxides have molar concentration that is ⅔ the molar concentration of silicon oxide. Group A metal oxides preferred for use in high permeability garnet electroceramics include: calcium oxide (CaO), magnesium oxide (MgO), iron oxide (FeO), and manganese oxide (MnO). Group B metal oxides preferred for use in high permeability garnet electroceramics include: aluminum oxide (Al 2 O 3 ), iron oxide (Fe 2 O 3 ), chromium oxide (Cr 2 O 3 ), vanadium oxide (V 2 O 3 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), silicon oxide (SiO 2 ), yttrium oxide (Y 2 O 3 ), cobalt oxide (Co 3 O 4 ), gadolinium oxide (Gd 2 O 3 ) neodymium oxide (Nd 2 O 3 ) and holmium oxide (Ho 2 O 3 ). Ceramic inductor coils  432  ( FIG. 23G ) having inductance values ranging from 0.01 pH to 1,000 μH and tolerances ≦±5%, preferably ≦±1%, will comprise ferrite or garnet electroceramic  426  selectively annealed to have controlled microstructure with grain size ranging from 10 nm to 25 μm, preferably from 250 nm to 5 μm.
 
     Reference is now made to  FIGS. 24A, 24B  to describe methods to integrate at least one discrete inductor coil  432  fabricated on a sacrificial substrate  419  into an embedded discrete inductor coil layer  436  that can subsequently be incorporated into a printed circuit board or interconnect structure. Each discrete inductor coil  432  possesses at least one via pad  424  that is used to make subsequent electrical connections. As shown in  FIG. 24B , once all inductor coils are fabricated within desired tolerances, an insulating dielectric layer  438 , a metallization layer  440 , and vertical interconnects (vias)  442  that maintain electrical communications between the metallization layer  440  and the at least one via pad  424  (where desired) are then applied to the structure. The dielectric layer  438  may be an organic material, such as FR4, polyfluorotetraehylene (PFTE) Teflon, or Rogers Duroid materials. Alternatively, the dielectric layer  438  may be an LCD processed inorganic material, such as silica, alumina, or a silicate or aluminate dielectric using a curtain coating or blanket coating liquid aerosol spray. The metallization layer  440  may comprise a ground or power plane, or may be patterned to function as a signal routing network. The metallization layer  440  may be applied using a variety of techniques, such as a metal sheet that is bonded to the dielectric layer through an adhesive agent, or through direct-write methods, such as screen printing or inkjet printing, preferably using low-temperature nano-particle pastes. It is recommended to use a low-temperature metallization technique so the formed structure is subject to maximum temperatures that will not alter the microstructure of the embedded electroceramic. The embedded discrete inductor layer  436  comprising at least one pre-tested embedded discrete inductor coil  432  in electrical communication with a via pad  424  or via  442  is then separated from the sacrificial substrate  419  for use in a printed circuit board or interconnect structure. 
     Reference is now made to  FIG. 25  to describe methods to embed at least one discrete inductor coil into a printed circuit board or interconnect structure. The embedded discrete inductor coil layer  436  can then be combined with one or more additional signal routing layers  444 A,  444 B, into a stacked multilayer structure  446 . Signal routing layers  444 A,  444 B contain vias  448 A,  448 B, and metallization  450 A,  450 B used to conduct signals within dielectric material  452 A,  452 B. This electrical network is used to maintain electrical communication between the at least one embedded inductor coil  432  and a semiconductor device  454  through conductive means  456  in electrical contact with a surface metallization layer  450 A, or an external device (not shown) through an electrical contact  458  located on the periphery of the stacked multilayer structure  446 . 
     Reference is now made to  FIGS. 26A, 26B and 27A, 27B  to describe methods to integrate at least one discrete inductor coil  460 , at least one discrete capacitor  462 , and at least one discrete resistor  464  fabricated on a sacrificial substrate  466  into a single embedded passive layer  468  that can subsequently be incorporated into a printed circuit board or interconnect structure. Each component  460 ,  462 ,  464  possesses at least one via pad  470 A,  470 B,  470 C that is used to make subsequent electrical connections. As shown in  FIG. 26B , once all passive components are fabricated within desired tolerances, an insulating dielectric layer  472 , a metallization layer  474 , and vertical interconnects (vias)  476  that maintain electrical communications between the metallization layer  474  and the at least one via pad  470  of the passive components  460 ,  462 ,  464  (where desired) are then applied to the structure. The dielectric layer  472  may be an organic material, such as FR4, polyfluorotetraehylene (PFTE) Teflon, or Rogers Duroid materials. Alternatively, the dielectric layer  472  may be an LCD processed inorganic material, such as silica, alumina, or a silicate or aluminate dielectric using a curtain coating or blanket coating liquid aerosol spray. The metallization layer  474  may comprise a ground or power plane, or may be patterned to function as a signal routing network. The metallization layer  474  may be applied using a variety of techniques, such as a metal sheet that is bonded to the dielectric layer through an adhesive agent, or through direct-write methods, such as screen printing or inkjet printing, preferably using low-temperature nano-particle pastes. It is recommended to use a low-temperature metallization technique so the formed structure is subject to maximum temperatures that will not alter the microstructure of the embedded electroceramic. The embedded passive component layer  468 , comprising at least one pre-tested embedded passive component  460 ,  462 ,  464  in electrical communication with via pads  470  or via  476 , is then separated from the sacrificial substrate  466  for use in a printed circuit board or interconnect structure. 
     Reference is now made to  FIG. 27A, 27B  to describe methods to embed at least one discrete inductor coil into a printed circuit board or interconnect structure. In one embodiment ( FIG. 27A ), the embedded passive component layer  468  can then be combined with one or more additional signal routing layers  476 A,  476 B, into a stacked multilayer structure  478 . Signal routing layers  476 A,  476 B contain vias  478 A,  478 B, and metallization  480 A,  480 B used to conduct signals within dielectric material  482 A,  482 B. This electrical network is used to maintain electrical communication between the at least one embedded inductor coil  460 , the at least one embedded discrete capacitor  462 , and the at least one embedded discrete resistor  464  and a semiconductor device  484  through conductive means  486  in electrical contact with a surface metallization layer  480 A, or an external device (not shown) through an electrical contact  488  located on the periphery of the stacked multilayer structure  478 . In another embodiment ( FIG. 27B ), electrical connectivity between embedded resistor, capacitor, and inductor components and a semiconductor device  484  is achieved by assembling a multilayer structure ack  489  comprising an embedded resistor layer  302 , an embedded capacitor layer  369 , and an embedded inductor coil layer  436 , with one or more signal routing layers  476 A,  476 B. The one or more signal routing layers are additionally used to establish electrical communication with external devices through an electrical contact  488  located on the periphery of the multilayer structure  489 . In the manner described in reference to  FIGS. 27A, 27B , a multilayer circuit board may be constructed a combination of various components and using the most suitable two-dimensional or three-dimensional arrangement. 
     The methods and embodiments described above provide a means to produce thermally stable filtering circuits that comprise circuit LCR elements with tolerances ≦±5%, preferably ≦±1%, that can be used to control a circuit&#39;s reactive impedance Z with a tolerance of ≦±5%, preferably ≦±1%. Wireless circuits include an antenna as a principle circuit element. The tuning (impedance) of an antenna element is affected by dielectric materials that are positioned within the antenna&#39;s reactive near-field region. Making reference to  FIG. 28 , the reactive-near field protrudes a distance d from an antenna element  490  that has a maximal dimension D  491  given by: 
                   d   =     0.62   ⁢     √       (       D   3     /   λ     )     _                 (   6   )               
Where λ is the wavelength of the electromagnetic emissions radiated by the antenna element  490 . A handset device that contains an antenna element surrounded by low permittivity dielectric materials has a reactive near-field region that protrudes beyond the handset&#39;s packaging and is therefore influenced by dielectric loads in the immediate vicinity of the handset, such as the users&#39; hands and heads, or the layout or the mobile device&#39;s packaging. These loads are likely to shift dramatically during use, which is undesirable to maintaining stable impedance in the antenna circuit element. Furthermore, making even minor changes to the design of the handset package requires a re-design of its RF front-end circuitry if the same antenna is to be re-used in the renovated handset package. Therefore, it is desirable to provide a platform-independent antenna module that has a tuning (impedance) that is not affected by changes in the dielectric loads surrounding the antenna module. A specific embodiment of the invention produces a platform-independent antenna module that produces a reactive near field that is contained within the body of the antenna module and, therefore, not affected by changes in the dielectric loads that surround it.
 
     Reference is now made to  FIGS. 29A, 29B, 29C  that describe a folded antenna element  492  contained within a meta-material dielectric body  494 . The meta-material dielectric body  494  comprises a low-permittivity host dielectric  496  with relative permittivity ∈ R ≦10, preferably ∈ R ≦5, and at least one high permittivity dielectric inclusion  498  having relative permittivity ∈ R ≧10, preferably ∈ R ≧100. By definition, the at least one dielectric inclusion  498  within a meta-material dielectric body  494  has physical dimension that is small compared to the wavelength of electromagnetic excitations propagating through meta-material dielectric body  494 . The meta-material dielectric body  494  has an effective dielectric permittivity ∈ REff  that is proportional to the relative volume fractions of the relative permittivities of the host dielectric  496 , ∈ RHost , and the at least one dielectric inclusion  498 , ∈ RIncl . A specific embodiment of the invention in  FIG. 29B  comprises a folded antenna element  492  having a maximal physical dimension D folded    500  embedded within a meta-material dielectric body  494  that has an effective permittivity ∈ REff ≧10, preferably has an effective permittivity ∈ REff ≧100. Although, the diagrams contained in  FIGS. 29A, 29B, 29C  depict a folded dipole antenna, it should be understood that the same reasoning applies to a folded monopole antenna. High permittivity and high permeability dielectric media reduce the phase velocity of electromagnetic excitations propagating through them. The reduced phase velocity, in turn, produces an effective wavelength λ Eff  given by: 
     
       
         
           
             
               
                 
                   
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                     b 
                   
                   ) 
                 
               
             
           
         
       
     
     Where c is the speed of light in a vacuum (c=2.9979×10 8  m/sec 2 ), f is the frequency of the electromagnetic excitation, and μ R  and ∈ R  are the relative permeability and relative permittivity of the dielectric medium, respectively, and λ freespace  is the wavelength of electromagnetic excitation in a vacuum. Therefore, an electromagnetic excitation propagating through a non-magnetic medium (μ R =1) will have an effective wavelength λ Eff  equal to λ freespace /4 and λ freespace /10 when the dielectric medium has relative permittivity ∈ R =16 and ∈ R =100, respectively. Therefore, the resonant length l res  of a folded dipole or a folded monopole antenna, which is generally given by l res ≈λ/2, and l res ≈λ/4, respectively, is decreased proportionally, thereby allowing the maximum physical dimension of the folded antenna element  492  to be reduced to the point that its reactive near field protrudes a distance d  502  that is contained within a distance S  503  separating the folded antenna element  492  from an exterior surface of the meta-material dielectric body  494 . In this embodiment, the reactive near field will remain unaffected by changes in dielectric loading beyond the physical dimensions  504  of the antenna module  506 . High permittivity dielectric media generally have unstable thermal properties and high loss that can adversely affect frequency tuning and signaling performance. Therefore, it is another preferred embodiment of the invention to fabricate the antenna module  506  using selectively deposited dielectric inclusions  498  having thermal stability tolerances for relative permittivity ∈ R  and relative permeability μ R  that are ≦±5%, preferably ≦±1% of targeted values. High-loss materials located within an antenna&#39;s reactive near field region will affect the antenna&#39;s signal modulation in a manner that limits phase modulation roll-off rates, which, in turn, limits the number of wireless symbols that can be transmitted by the antenna. Thus, it is desirable to engineer the folded antenna element  492  and the meta-material dielectric body  494  such that the at least one high permittivity dielectric inclusion  496  is located a distance  508  away from the folded antenna element  492  that is greater than the distance d  510  to which the reactive near field protrudes In this special embodiment the reactive near field is contained within a low loss host dielectric  512  having a loss tangent tan δ≦10 −3 , preferably an ultra-low loss dielectric host having a loss tangent tan δ≦2×10 −4 . Amorphous silica is a preferred ultra-low loss dielectric medium because it has stable dielectric properties over temperatures ranging from −150° C. to +250° C. and a loss tangent tan δ=2×10 −5 . Organic dielectric media suitable for use as an ultra-low loss dielectric host  512  include PFTE Teflon and Rogers Duroid dielectric. This special embodiment also provides a platform-independent antenna module since the reactive near field protrudes a distance d  510  that remains within the antenna module&#39;s solid state dimensions  514 . 
     The art described above instructs methods and embodiments that provide wireless circuit elements (embedded passive components and platform-independent antenna modules) that maintain precise impedance tuning in the presence of electromagnetic and thermal disturbances. These embodiments are combined into a further embodiment that establishes the passive spread-spectrum receiver. Making reference to  FIGS. 30, 31A, 31B, 32, 33A, 33B  the spread-spectrum receiver  517  comprises at least one frequency-selective antenna (FSA) element  518  in electrical communication through conductive means  519  with a printed circuit board or interconnect structure  520  that comprises one or more embedded passive components having thermal stability and performance tolerances ≦±5%, preferably ≦±1%, used to construct impedance-matched transmission lines  521  within the printed circuit board or interconnect structure  520 . The printed circuit board or interconnect structure  520  is, in-turn, in electrical communication through conductive means  522  with semiconductor devices  523 A,  523 B located on a top  574  or bottom  572  major surface of the printed circuit board or interconnect structure  520 . At least one of the semiconductor devices  523 A is a low-noise power amplifier  522 A, preferably a differential low-noise power amplifier, in electrical communication with the FSA element  518  through one or more impedance-matched transmissions  521  and a first pass band filter  526 . The use of lumped circuit elements to impedance-match two components through a transmission line is generally referred to in the art as L-section matching. In general, L-section matching with discrete components mounted on the surface of a printed circuit is only used for frequencies up to about 1 GHz, because the size of the reactive components is not very small (&lt;λ/10) compared to the operating wavelength. The use of high resistivity, high permittivity, or high permeability electroceramics to form the embedded passive component embodiments described above sharply reduces passive component size. Furthermore, embedding these components within the circuit board or interconnect structure eliminates solder joints and surface vias that contribute reactive noise to the circuit. Therefore, a printed circuit board or interconnect structure that comprises L-section matched transmission lines tuned with embedded passive components having thermal stability and performance tolerances ≦±5%, preferably ≦±1%, is an additional preferred embodiment of the invention. 
       FIGS. 31A, 31B  depict two characteristic configurations for L-section matching  528 ,  530  between a signal source impedance Z o =(R o +X o )  532  and a transmission line load Z L =(R L +X L )  534  that comprise a reactive series load jX  536  and a reactive parallel load jB  538 . L-section matching  528  ( FIG. 31A ) is used when the real part R L  of the load impedance Z L    534  is greater than the source impedance Z o    532 . In this instance, the reactive parallel load jB  538  is determined by:
 
B=[ X   L ±√( R   L   /Z   o )×√( R   L   2   +X   L   2   −Z   o   R   L )]/( R   L   2   +X   L   2 )  (8a)
 
And, the reactive series load jX  536  is determined by:
 
 X =(1/B)+( X   L   Z   o   /R   L )−( Z   o /B R   L )  (8a)
 
L-section matching  530  ( FIG. 31B ) is used when the real part R 1  of the load impedance Z L    534  is less than the source impedance Z o    532 . In this instance, the reactive parallel load jB  538  is determined by:
 
B=±√[( R   L ( Z   o   −R   L )]− X   L   (8c)
 
And, the reactive series load jX  536  is determined by:
 
 X =(1/B)+( X   L   Z   o   /R   L )−( Z   o /B R   L )  (8d)
 
It is not a requirement for all impedance tuning within the printed circuit board or interconnect structure  520  to be managed using L-section matching methods as circuit tuning can also be realized using transmission-line stubs. However, the high tolerance controls, small size, and wide range of performance values enabled by the invention provide convenient means to integrate precise bandwidth filters, such as quarter-wave transformers, binomial multi-section transformers, and Chebyshev multi-section matching transformers into the spread-spectrum receiver. These filtering devices are well known to practitioners skilled in the art of microwave circuit, reference is made to  Microwave Engineering,  3 rd    Edition , David M. Pozar, John Wiley &amp; Sons, Hoboken, N.J. © 2005 (ISBN: 0-471-44878-8) for a complete description on impedance tuning parameters for these devices.
 
     As shown in  FIG. 32A, 32B , an FSA element  518  is characterized by a conductance band  540  that is tuned to a center frequency f c    542  of interest and provides ≧−20 dB signal isolation, preferably ≧−40 dB signal isolation between an upper band frequency f U    544  and a lower band frequency f L    546  that characterize the limits for a pass band  548  of interest ( FIG. 32A ). The FSA conductance band  540  is narrower than the desired pass band  548 , so the FSA  518  is additionally tuned to have frequency-dependent impedance that provides input signal reflection coefficients  550  ( FIG. 32B ) of approximately 1 at the center frequency f c    542  and input signal reflection coefficient of approximately 2 at the upper band frequency f U    544  and lower band frequency f L    546 . Signal reflection coefficients are alternatively referred to as the voltage standing wave ratio (VSWR). 
     Reference is now made to  FIGS. 30, 33 and 34  to describe design features of the spread-spectrum receiver device as they relate to embedded passive components and filtering devices derived there from within the printed circuit board or interconnect structure  520 .  FIG. 33  depicts the architecture of a single carrier-frequency spread-spectrum device  552 , comprising an FSA element  518 , a first pass band filter  526  tuned to output signal frequencies contained within a desired pass band  548  ( FIG. 32A ) to a low-noise power amplifier (LNA) semiconductor device  523 A. The LNA semiconductor device  523 A amplifies signals in the desired pass band  548  and directs them to a second pass band filter  554 . The second pass band filter  554  functions as a comb filter, preferably using an array of quarter-wave transformers. The second pass band filter  554 , isolates discrete frequency components contained in the desired pass band  548  into separate channels  556 . Signals in the separate channels  556  are directed through impedance-matched transmission lines  521  ( FIG. 30 ) to a semiconductor device  523 B ( FIG. 30 ) that contains sensor elements  558  and an analog-to-digital conversion stage  560  that integrates signal characteristics of isolated frequency components contained within separate channels  556  over a time period equal to the pulse duration length T of the wireless symbol. A clock  562  transfers the digitally formatted integration values from the separate channels  556  to a microprocessor  564  that compares the relative integration values to a reference table  566  and outputs the wireless symbol  568  that corresponds to the measured weighting across the isolated frequency channels  556 . Electrical contacts  570 A,  570 B ( FIG. 30 ) on a major surface  572 ,  574  ( 570 A) or the periphery ( 570 B) of the printed circuit board or interconnect structure  520  are used to establish electrical communication with external devices (not shown). A wide band spread-spectrum receiver  580  may alternatively comprise a plurality of single carrier-frequency spread-spectrum stages  582 ,  582 B,  582 C, . . . ,  582 N that operate in parallel to supply a microprocessor  584  with data on frequency-weighting of multiple carrier signals, which is referenced in a look-up table  586  to produce a complex wireless symbol  588  ( FIG. 34 ). 
     Although the invention has been described with respect to various embodiments, it should be realized this invention is also capable of a wide variety of further and other embodiments within the spirit and scope of the appended claims.