Patent Publication Number: US-8120931-B2

Title: Power converter with control circuit and related control method

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to control circuits, and particularly, to a control circuit having a multi-function terminal. 
     2. Description of the Prior Art 
     Please refer to  FIG. 1 , which is a diagram of a flyback converter  10 . After filtering and current rectification, an input voltage Vin is applied to a primary-side winding Lp of a transformer TX. A power switch  101  is controlled by a pulse width modulation (PWM) control signal Vg. A sense resistor Rs senses a primary-side current Ip flowing through the power switch  101 . A control circuit  100  determines duty cycle of the control signal Vg according to a feedback signal Vcomp, which corresponds to an output terminal of the converter  10 , and the primary-side current Ip, thereby stabilizing an output voltage Vo. 
     As is well-known in the art, and shown in  FIG. 1 , the output voltage Vo on a capacitor Co is generated by rectifying the current through the secondary-side winding of the transformer Tx and a diode D. The feedback compensation signal Vcomp may be generated by using a feedback module  102  to sense the amplitude of the output voltage Vo. Feedback module  102  may include a voltage divider, an optical-coupler, or other device as illustrated in  FIG. 1 . 
     Resistors  130  and  140  form a voltage divider. Control circuit  100  utilizes the voltage divider to sense a sense voltage VBNO. Thus, level of the sense voltage VBNO is proportional to the input voltage Vin. When sense voltage VBNO is lower than a predetermined level, control circuit  100  disables switching of power switch  101 , so as to prevent converter  10  from operating at too low of an input voltage Vin, which would damage the converter  10 . 
     SUMMARY OF THE INVENTION 
     According to an embodiment of the present invention, a control circuit for use in a power converter comprises a multi-function terminal, a current comparator circuit, and an under-voltage detection circuit. The current comparator circuit compares current flowing through a power switch of the power converter with a reference value through the multi-function terminal when the power switch is on, and turns the power switch off when the current reaches the reference value. The under-voltage detection circuit determines whether an input voltage of the power converter is less than a predetermined value through the multi-function terminal when the power switch is turned off. 
     According to the embodiment of the present invention, a power converter comprises a control circuit and a voltage divider circuit. The control circuit comprises a multi-function terminal, a current comparator circuit, and an under-voltage detection circuit. The current comparator circuit compares current flowing through a power switch of the power converter with a reference value through the multi-function terminal when the power switch is on, and turns the power switch off when the current reaches the reference value. The under-voltage detection circuit determines whether an input voltage of the power converter is less than a predetermined value through the multi-function terminal when the power switch is turned off. The voltage divider circuit generates a sense voltage proportional to the input voltage through the multi-function terminal. The under-voltage detection circuit determines whether the input voltage is lower than the predetermined value according to the sense voltage. 
     According to the embodiment of the present invention, a method of performing control in a power converter comprises providing a multi-function terminal, utilizing the multi-function terminal to compare a current flowing through a power switch of the power converter with a reference value when the power switch is turned on, turning off the power switch when the current reaches the reference value, determining whether an input voltage of the power converter is lower than a predetermined value through the multi-function terminal when the power switch is turned off, and holding the power switch in an off state while the input voltage is lower than the predetermined value. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of a flyback converter according to the prior art. 
         FIG. 2  is a circuit diagram of a power converter according to an embodiment of the present invention. 
         FIG. 3  is a flowchart diagram of a method of controlling a power converter according to the embodiment. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 2  is a circuit diagram of a flyback power converter  20  according to an embodiment of the present invention. Power converter  20  comprises a control circuit  200 , a power switch  201 , and a voltage divider circuit  205 . Voltage divider circuit  205  is formed of a first resistor R 1 , a second resistor R 2 , and a sense resistor Rs. In this embodiment, resistance of first resistor R 1  is much greater than combined resistance of second resistor R 2  and sense resistor Rs. After filtering and current rectification, an input voltage Vin is applied to a primary-side winding Lp of a transformer TX. Power switch  201  is controlled by a pulse width modulation (PWM) control signal Vg generated by an oscillator  240 . Sense resistor Rs senses a primary-side current Ip flowing through power switch  201 . Control circuit  200  determines duty cycle of the control signal Vg according to a feedback signal Vcomp, which corresponds to an output terminal of the converter  20 , and the primary-side current Ip, thereby stabilizing an output voltage Vo. 
     The output voltage Vo on a capacitor Co is generated by rectifying the current through the secondary-side winding of the transformer Tx and a diode D. The feedback compensation signal Vcomp may be generated by using a feedback module  202  to sense the amplitude of the output voltage Vo. Feedback module  202  may include a voltage divider, an optical-coupler, or other device as illustrated in  FIG. 2 . 
     Control circuit  200  may be an integrated circuit comprising a multi-function terminal CS, a current comparator circuit  210 , and an under-voltage detection circuit  220 . 
     First resistor R 1  couples multi-function terminal CS to an input voltage Vin of power converter  20 . Second resistor R 2  forms a low pass filter with a capacitor C 1 , and couples sense resistor Rs to multi-function terminal CS. The low pass filter filters out high frequency noise in a first sense voltage Vs generated across sense resistor Rs. 
     When power switch  201  is on, or conducts, a primary side current Ip of power converter  20  flows through power switch  201  and sense resistor Rs. Thus, the first sense voltage Vs generated across sense resistor Rs (approximately Ip*Rs) is proportional to the primary side current Ip. 
     While power switch  201  is on, current comparator  210  compares a second sense voltage Vcs and a reference voltage Vcomp. The second sense voltage Vcs is a voltage sensed by multi-function terminal CS, and can be expressed as follows: 
     
       
         
           
             
               
                 
                   
                     V 
                     CS 
                   
                   = 
                   
                     
                       Vin 
                       × 
                       
                         ( 
                         
                           
                             
                               R 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                             + 
                             Rs 
                           
                           
                             
                               R 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                             + 
                             
                               R 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                             + 
                             Rs 
                           
                         
                         ) 
                       
                     
                     + 
                     
                       
                         V 
                         S 
                       
                       × 
                       
                         ( 
                         
                           
                             R 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                           
                             
                               R 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                             + 
                             
                               R 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     Because the resistance of R 1  is much greater than the combined resistance of R 2  and Rs, the contribution of the input voltage Vin to the equation (1) can be ignored, and the second sense voltage Vcs is approximately equal to the first sense voltage Vs. The reference voltage Vcomp corresponds to a feedback voltage of the output voltage Vo of the power converter  20 . Whenever the second sense voltage Vcs reaches the reference voltage Vcomp, current comparator  210  triggers an SR flip-flop  231 , such that a logic level of the PWM control signal Vg shifts, taking the power switch  201  out of the conducting state. In other words, when the primary side current Ip reaches or exceeds a reference value, current comparator  210  turns off power switch  201 . 
     Under-voltage detection circuit  220  comprises a comparator  222  and a sample-and-hold circuit comprising a sampling switch  224  and a voltage hold circuit  226 . In this embodiment, sampling switch  224  may be an N-type metal-oxide-semiconductor (NMOS) transistor, and voltage hold circuit  226  may be a capacitor. 
     When power switch  201  is turned off, under-voltage detection circuit  220  detects the second sense voltage Vcs on multi-function terminal CS through first resistor R 1 . At this time, the second sense voltage Vcs has a value 
             Vin   ×     (         R   ⁢           ⁢   2     +   Rs         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2     +   Rs       )           
proportional to the input voltage Vin. Thus, the second sense voltage Vcs may be used to determine whether the input voltage Vin is lower than a predetermined value.
 
     Sampling switch  224  and power switch  201  are both controlled by the PWM control signal Vg. When power switch  201  is turned off, sampling switch  224  conducts, so that an input terminal of comparator  222  may detect the second sense voltage Vcs. When the second sense voltage Vcs is greater than a reference voltage Vth 1 , comparator  222  determines that the current input voltage Vin is normal, and outputs a logic high signal. The PWM signal Vg then changes according to the output of SR flip-flop  231 . Alternatively, when the second sense voltage Vcs is lower than the reference voltage Vth 1 , comparator  222  determines that the current input voltage Vin is too low, i.e. an under-voltage condition is met, and outputs a logic low signal, so that the PWM control signal Vg outputted by a logic gate  235  is fixed at a logic low level. Thus, power switch  201  stops switching, and is fixed in an off state. 
     Whenever power switch  201  conducts, due to isolation by the sampling switch  224 , voltage hold circuit  226  will store the second sense voltage Vcs corresponding to the last time the power switch  201  came out of the off state, such that output signal of comparator  222  may remain at the logic high level, and power switch  201  may switch normally. 
     Because under-voltage detection circuit  220  is only operated when power switch  201  is turned off, operation of current comparator circuit  210  while power switch  201  is conducting is not affected. 
     If the embodiment of control circuit  200  is integrated in a chip, under-voltage detection circuit  220  and current comparator circuit  210  may both utilize the same multi-function terminal CS to detect the second sense voltage Vcs, which saves a pin compared to the control circuit  100  shown in  FIG. 1 . 
     Please refer to  FIG. 3 , which is a flowchart diagram of a method of controlling a power converter according to the above embodiment. The method of performing PWM control may be derived from the above, and comprises the following steps: 
     Step  300 : Provide a multi-function terminal; 
     Step  302 : Utilize the multi-function terminal to compare a current flowing through a power switch of the power converter with a reference value when the power switch is turned on; 
     Step  304 : Turn off the power switch when the current reaches the reference value; 
     Step  306 : Send a sense voltage generated proportional to the input voltage to the multi-function terminal; 
     Step  308 : Determine whether an input voltage of the power converter is lower than a predetermined value through the multi-function terminal when the power switch is turned off; and 
     Step  310 : Hold the power switch in an off state while the input voltage is lower than the predetermined value. 
     It can be seen from the embodiment of the present invention that use of the PWM control method of  FIG. 3  in conjunction with the control circuit  200  of  FIG. 2  reduces pin count of the power converter compared to the prior art. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.