Patent Publication Number: US-2022237336-A1

Title: Object simulation using real-world environments

Description:
BACKGROUND 
     Generating realistic training data for a neural network for object detection has many challenges. Collecting training data in the real-world can be resource intensive and time consuming, often requiring a significant amount of human intervention to label the data. Artificially generated training data may have unrealistic aspects that adversely affect the ability to train a network to perform accurate inferencing. 
     TECHNICAL FIELD 
     At least one embodiment pertains to processing resources used to generate training data to train a neural network to detect and classify objects. For example, at least one embodiment pertains to processors or computing systems used to generate realistic training data to train a neural network to detect and classify objects according to various novel techniques described herein. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an example computing environment of using a simulator to apply physics-based simulations to generate training data, in accordance with at least one embodiment; 
         FIG. 2  illustrates an example of a simulator generating scene images and labels, in accordance with at least one embodiment; 
         FIG. 3  illustrates an example of a simulator generating object images and labels, in accordance with at least one embodiment; 
         FIG. 4  illustrates an example of a user interface of a simulator, in accordance with at least one embodiment; 
         FIG. 5  illustrates an example of training a neural network with a simulator to detect and classify objects, in accordance with at least one embodiment; 
         FIG. 6  illustrates an example environment of detecting and classifying objects of a checkout counter using a neural network, in accordance with at least one embodiment; 
         FIG. 7  shows an illustrative example of a process to perform simulations to obtain training data, in accordance with at least one embodiment; 
         FIG. 8  shows an illustrative example of a process to train a neural network using training data, in accordance with at least one embodiment; 
         FIG. 9  illustrates an exemplary data center, in accordance with at least one embodiment; 
         FIG. 10  illustrates a processing system, in accordance with at least one embodiment; 
         FIG. 11  illustrates a computer system, in accordance with at least one embodiment; 
         FIG. 12  illustrates a system, in accordance with at least one embodiment; 
         FIG. 13  illustrates an exemplary integrated circuit, in accordance with at least one embodiment; 
         FIG. 14  illustrates a computing system, according to at least one embodiment; 
         FIG. 15  illustrates an APU, in accordance with at least one embodiment; 
         FIG. 16  illustrates a CPU, in accordance with at least one embodiment; 
         FIG. 17  illustrates an exemplary accelerator integration slice, in accordance with at least one embodiment; 
         FIGS. 18A and 18B  illustrate exemplary graphics processors, in accordance with at least one embodiment; 
         FIG. 19A  illustrates a graphics core, in accordance with at least one embodiment; 
         FIG. 19B  illustrates a GPGPU, in accordance with at least one embodiment; 
         FIG. 20A  illustrates a parallel processor, in accordance with at least one embodiment; 
         FIG. 20B  illustrates a processing cluster, in accordance with at least one embodiment; 
         FIG. 20C  illustrates a graphics multiprocessor, in accordance with at least one embodiment; 
         FIG. 21  illustrates a graphics processor, in accordance with at least one embodiment; 
         FIG. 22  illustrates a processor, in accordance with at least one embodiment; 
         FIG. 23  illustrates a processor, in accordance with at least one embodiment; 
         FIG. 24  illustrates a graphics processor core, in accordance with at least one embodiment; 
         FIG. 25  illustrates a PPU, in accordance with at least one embodiment; 
         FIG. 26  illustrates a GPC, in accordance with at least one embodiment; 
         FIG. 27  illustrates a streaming multiprocessor, in accordance with at least one embodiment; 
         FIG. 28  illustrates a software stack of a programming platform, in accordance with at least one embodiment; 
         FIG. 29  illustrates a CUDA implementation of a software stack of  FIG. 28 , in accordance with at least one embodiment; 
         FIG. 30  illustrates a ROCm implementation of a software stack of  FIG. 28 , in accordance with at least one embodiment; 
         FIG. 31  illustrates an OpenCL implementation of a software stack of  FIG. 28 , in accordance with at least one embodiment; 
         FIG. 32  illustrates software that is supported by a programming platform, in accordance with at least one embodiment; 
         FIG. 33  illustrates compiling code to execute on programming platforms of  FIGS. 28-31 , in accordance with at least one embodiment; 
         FIG. 34  illustrates in greater detail compiling code to execute on programming platforms of  FIGS. 28-31 , in accordance with at least one embodiment; 
         FIG. 35  illustrates translating source code prior to compiling source code, in accordance with at least one embodiment; 
         FIG. 36A  illustrates a system configured to compile and execute CUDA source code using different types of processing units, in accordance with at least one embodiment; 
         FIG. 36B  illustrates a system configured to compile and execute CUDA source code of  FIG. 36A  using a CPU and a CUDA-enabled GPU, in accordance with at least one embodiment; 
         FIG. 36C  illustrates a system configured to compile and execute CUDA source code of  FIG. 36A  using a CPU and a non-CUDA-enabled GPU, in accordance with at least one embodiment; 
         FIG. 37  illustrates an exemplary kernel translated by CUDA-to-HIP translation tool of  FIG. 36C , in accordance with at least one embodiment; 
         FIG. 38  illustrates non-CUDA-enabled GPU of  FIG. 36C  in greater detail, in accordance with at least one embodiment; 
         FIG. 39  illustrates how threads of an exemplary CUDA grid are mapped to different compute units of  FIG. 38 , in accordance with at least one embodiment; and 
         FIG. 40  illustrates how to migrate existing CUDA code to Data Parallel C++ code, in accordance with at least one embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Techniques described herein provide a way to create training data on objects using realistic simulations and then feeding the training data into a neural network to train the neural network to infer objects from images captured by one or more cameras. Specifically, techniques described herein provide ways to simulate real-world effects on an object to create different images of the object that are used as training data to train a neural network. As an example, the object is one of many physical objects that may be found in a physical location or establishment. Typically, generating these object images can be a cumbersome process because, in most instances, they are performed manually (e.g., a human using a camera to capture object images). In addition, the resulting images from the camera are only able to capture the object in particular orientations (e.g., those chosen by the human using the camera), which puts limitations on how realistic the images can be. 
     Techniques described herein use a simulator that can receive a 3D model of an object and generate a plurality of images of the object in different orientations. Physics-based simulations are applied to the object by using real-world effects (e.g., light, gravity, friction, general motion dynamics, etc.) such that the resulting images from the simulation are realistic. A simulator may randomize aspects of rendering in the simulator, such as randomizing lighting configurations, object configurations, and environmental configurations, to generate realistic images. By having realistic images as training data, a neural network can be better trained to infer objects in different environments. 
     The trained model may then be used in devices to better identify objects in the event of incorrect labeling on the objects. Although the system described herein is applied to objects found in physical locations, the system is also applicable to other fields (e.g., facial recognition in airport customs screening, item sorting in recycling facilities, part recognition in manufacturing facilities, and generally in fields that utilize a neural network to perform inferencing). 
       FIG. 1  illustrates an example computing environment  100  of using a simulator to apply physics-based simulations to generate training data, in accordance with at least one embodiment. The example computing environment  100  may include a simulator  104  that receives or otherwise obtains three-dimensional (3D) models  102 ; and generates object images and labels  106 , and scene images and labels  108  based at least in part on the 3D models  102 . 
     In an embodiment, 3D models  102  are a collection of one or more 3D models of one or more objects. In an embodiment, a 3D model refers to a representation of an object in three dimensions. A 3D model may represent a physical object using a collection of points in a 3D space. A 3D model may be a mathematical representation of a 3D object. 3D models may include solid 3D models—which define a volume of an object represented, shell/boundary 3D models—which represent a surface/boundary of an object, and/or variations thereof. A 3D model may be encoded or otherwise stored in one or more computer files (e.g., ZIP, Universal Scene Description (USD) format. In an embodiment, 3D models  102  comprise one or more compressed computer files corresponding to one or more 3D models. In an embodiment, 3D models  102  comprise one or more computer files corresponding to one or more 3D models. 
     In an embodiment, 3D models  102  comprise 3D models of various objects, including but not limited to: foods, drinks, clothing items, books, toys, electronics, humans, animals, vehicles, and the like. In an embodiment, 3D models  102  comprise 3D models of objects that may be found in a self-service shop such as a supermarket or convenient store. 3D models  102  may also comprise 3D models of human faces, human organs (e.g., for medical imaging), objects on a road, vehicles, buildings, or any suitable objects. 3D models  102  may also comprise 4D models; a 4D model may refer to a 3D model that is associated with one or more states of the 3D model that may change or iterate over time. For example, a 4D model of a clock is associated with one or more states corresponding to one or more different times, in which the 4D model continuously changes states based on elapsed time. 
     In an embodiment, a simulator  104  is a collection of one or more hardware and/or software computing resources with instructions that, when executed, generates object images and labels, and scene images and labels from 3D models of objects. A simulator  104  may be a software program executing on computer hardware, application executing on computer hardware, or the like. A simulator  104  may be executing on one or more computing devices that may comprise various rendering devices, such as graphics processing units (GPUs). A simulator  104  may generate various 3D environments with various properties that may correspond to properties of real-world environments, such as gravity physics, lighting, or other environmental effects. A 3D environment may be referred to as a scene. A simulator  104  may obtain 3D models  102 . In some examples, 3D models  102  are provided to a simulator  104  by one or more computing systems. A simulator  104  may obtain 3D models  102  from one or more databases of 3D models, or from one or more systems that may generate 3D models from images. 
     A simulator  104  may generate a 3D environment comprising one or more 3D models of 3D models  102 . A 3D environment may be generated with various properties that may simulate a real-world environment; the 3D environment may simulate a real-world environment by simulating properties such as gravity, texture, and/or object physics, as well as forces such as gravitational forces, and/or frictional forces. Gravitational forces may refer to physical forces resulting from a natural phenomenon referred to as gravity. Frictional forces may refer to forces resulting from interactions between the relative motion of solid surfaces, fluid layers, and/or material elements sliding against each other. For example, in a 3D environment simulating frictional forces, interactions between two objects of smooth surfaces are different than interactions between two objects of rough or textured surfaces. In a 3D environment without frictional forces, interactions between all objects may be similar or the same. A 3D environment generated or otherwise simulated by a simulator  104  may be referred to as a physics-based simulation. A 3D environment generated by a simulator  104  may correspond to any suitable real-world environment, such as an interior of a shop, store, showroom, gallery, factory, production line, warehouse, supermarket, building, or other environment. In an embodiment, a 3D environment generated by a simulator  104  is an environment of a point of sale or point of purchase location. A point of sale or point of purchase location may comprise various objects and devices, such as payment terminals, checkout stands, conveyor belts, scanning equipment, and/or cameras. A simulator  104  may perform a plurality of physics-based simulations. A simulator  104  may perform a physics-based simulation by constructing dynamic models of objects and computing their motions via physical simulation. Physical simulation may be based on the laws of physics, which may result in physically realistic motions within a physics-based simulation. A simulator  104  may perform a physics-based simulation by generating a mathematical model that defines a state of a system and interactions between entities of the system, wherein the interactions are defined in accordance with the laws of physics. A simulator  104  may generate a 3D environment based at least in part on a mathematical model, in which object interactions within the 3D environment are in accordance with the laws of physics. A 3D environment generated by a simulator  104  may simulate gravitational effects (e.g., objects of the 3D environment may behave as if affected by gravity), frictional effects (e.g., objects of the 3D environment may behave as if affected by friction), physical effects (e.g., objects of the 3D environment may behave according to the laws of motion), and/or variations thereof. 
     A simulator  104  may generate a 3D environment comprising one or more objects corresponding to one or more 3D models of 3D models  102  and render images of the 3D environment. A simulator  104  may render images of a 3D environment using various rendering techniques, such as ray tracing and/or path tracing, such that the rendered images may be photo-realistic. A photo-realistic image may refer to an image that reproduces a real-world environment and objects of the real-world environment under real-world lighting conditions. A photo-realistic image rendered from a 3D environment representing a real-world environment comprising one or more objects may be indistinguishable from an image depicting a real-world environment comprising the one or more objects. A simulator  104  may render images of 3D environments that may be associated with labels that indicate classifications and locations of objects of the images of the 3D environments. Labels may include coordinates corresponding to bounding boxes of objects, including two-dimensional (2D) bounding boxes and/or 3D bounding boxes, and corresponding indications of classifications of the objects of the bounding boxes. A 2D bounding box of an object of an image may indicate a location of the object, and a corresponding indication may indicate a classification of the object. A 3D bounding box of an object of an image may indicate a location, size, position, and/or orientation of the object, and a corresponding indication may indicate a classification of the object. 
     For example, a simulator  104  generates a 3D environment comprising a first object and renders an image of the 3D environment, in which the simulator  104  generates, along with the rendered image, data indicating a classification of the first object, a 2D bounding box that indicates a location and/or position of the first object, and a 3D bounding box that indicates a location, position, size, and/or orientation of the first object. A simulator  104  may generate a 3D environment comprising any number of objects, and a rendered image of the 3D environment may be associated with labels indicating any number of bounding boxes/classifications corresponding to the objects. 
     In an embodiment, a simulator  104  renders images using ray tracing. Ray tracing may refer to a rendering technique for rendering an image of a 3D environment that comprises tracing one or more paths of light in an image plane of the image and simulating effects of the one or more paths of lights and its encounters with various objects and/or entities of the 3D environment. In an embodiment, a simulator  104  renders images using path tracing. Path tracing may refer to a rendering technique to accurately simulate light transport in computer graphics by tracing multiple ray paths, which can be denoted as samples, within each pixel for an image. Path tracing may be utilized to render an image of a 3D environment, in which samples may be taken to render each pixel of the image. A number of samples per pixel utilized to render pixels of an image from a scene can vary depending on a complexity of the scene and lighting configuration, in which scenes with higher complexities may require higher numbers of samples per pixel. 
     A simulator  104  may render images from a 3D environment using one or more lighting configurations of the 3D environment. For example, a first image rendered by a simulator  104  from a 3D environment is rendered from a first lighting configuration of the 3D environment (e.g., light is projected from a horizontal direction in the 3D environment), and a second image rendered by the simulator  104  from the 3D environment is rendered from a second lighting configuration of the 3D environment (e.g., light is now projected from a vertical direction in the 3D environment). A lighting configuration of a 3D environment may refer to one or more configurations of lighting conditions, such as light intensity (e.g., brighter and/or dimmer light), light color (e.g., different light colors), light patterns (e.g., flashing lights, oscillating lights, or other patterns), light direction (e.g., light projected from one or more directions), and/or variations thereof. A simulator  104  may render images of 3D environments comprising a single 3D model, or multiple 3D models of 3D models  102 . 
     A simulator  104  may randomize various aspects of a 3D environment and render images of various states of the 3D environment. A simulator  104  may randomize aspects of a 3D environment, such as lighting configurations, object configurations, and environmental configurations, in accordance with various constraints. Environmental configurations of a 3D environment may include aspects such as a background and/or foreground of the 3D environment, a 3D environment model to utilize as the 3D environment, weather effects of the 3D environment (e.g., wind, rain), and/or variations thereof. For example, a simulator  104  randomizes a background of a 3D environment, in which the randomization is constrained to backgrounds of self-service stores. A simulator  104  may randomize a lighting configuration of a 3D environment, in which the randomization may be in accordance with various constraints (e.g., light of the lighting configuration must be from the visible spectrum). A simulator  104  may randomize intensity of light, propagation directions of light, frequency or wavelength spectrums of light, and/or variations thereof. A simulator  104  may randomize a frequency of a flicker of light to simulate a flicker of a light such as a fluorescent light. A simulator  104  may randomize lighting configurations of a 3D environment such that the lighting configurations may approximate lighting configurations and conditions of the real world. A simulator  104  may randomize lighting configurations based on one or more probability distributions of values of the lighting configurations in the real world. For example, a simulator  104  randomizes light intensity of a 3D environment based on a probability distribution of light intensity values of a real-world environment corresponding to the 3D environment. A simulator  104  may utilize one or more probability distributions of lighting configuration values, which may correspond to distributions of the lighting configuration values in the real world, to randomize values of lighting configurations of a 3D environment, including values of light color, light intensity, light frequency, and/or variations thereof. 
     A simulator  104  may generate object images and labels  106 . Object images and labels  106  may be a collection of one or more images of objects and associated labels of the objects. A simulator  104  may generate object images by viewing each 3D model of 3D models  102  from different angles, and capturing images of each 3D model from the different angles. Objects may be isolated from captured images according to their 2D bounding boxes, and one or more backgrounds may be applied to the objects to generate the object images. A simulator  104  may generate a 3D environment with a directional light, load a 3D model (e.g., a 3D model of an object from 3D models  102 ) in the 3D environment, rotate the 3D model and/or rotate the directional light, and capture images of the 3D model in different positions and/or different lighting directions. 
     A simulator  104  may generate a set of images for each 3D model of 3D models  102 , in which each set of images may be associated with labels that indicate classifications and locations of objects of images of the set of images. Labels may include coordinates corresponding to bounding boxes of objects, including 2D bounding boxes and/or 3D bounding boxes, and corresponding indications of classifications of the objects of the bounding boxes. Further information regarding object images and labels can be found in the description of  FIG. 3 . 
     A simulator  104  may generate scene images and labels  108 , which may be a collection of one or more images of 3D environments comprising one or more objects and associated labels of the objects. A simulator  104  may generate scene images by generating a 3D environment, loading one or more 3D models of objects of 3D models  102  into the 3D environment, and capturing images of the 3D environment. A 3D environment may comprise a spawning point, which may be a location or position within the 3D environment in which 3D models of objects are loaded. A 3D environment may comprise a vanishing point, which may be a location or position within the 3D environment in which 3D models of objects, when moved to the vanishing point, are removed or otherwise disappear from the 3D environment. 
     A simulator  104  may load objects into a scene in various time intervals. Each object may have various phases within a scene, such as a physics phase, a render phase, and a moving phase. In a physics phase, an object may be dropped or otherwise loaded onto a plane of a scene, and its orientation and height on a flat surface may be determined and recorded. In a rendering phase, textures of an object may be loaded onto the object, in which the object may or may not be moving in a scene. In a physics phase and a rendering phase, an object may be invisible. In a moving phase, an object may be loaded or spawned at a spawning point with its recorded orientation and height, and moved to a vanishing point, in which images may be captured of the object in various time intervals, and a name, identifier, 2D and 3D bounding boxes of the object may be stored. An object may be removed from a scene when it reaches a vanishing point. In an embodiment, a simulator  104  generates a 3D environment of a checkout counter or stand with various objects of 3D models  102  and generates images of the 3D environment with the various objects. A simulator  104  may generate a 3D environment of a checkout counter or stand with a conveyor belt and load one or more objects of 3D models  102  into the 3D environment, in which the one or more objects may be moved across the conveyor belt and the simulator  104  may capture one or more images from a viewpoint above the conveyor belt. 
     A simulator  104  may configure various aspects of objects loaded into a 3D environment. A simulator  104  may randomly vary the size, scale, and/or pose of an object. A pose of an object may refer to a position and/or orientation of the object. In some examples, a simulator  104  varies poses of an object to match physically realistic poses of the object. A physically realistic pose of an object may refer to a pose of the object that may exist in the real-world. For example, a pose of a scissor object laying on its side is physically realistic, as the scissor object can lay on its side in the real-world, and a pose of the scissor object standing upright on the tips of its blades is not physically realistic, as the scissor object may not stand upright on the tips of its blades in the real-world without other external forces. A simulator  104  may randomize a number of objects loaded into a 3D environment, in which the randomization may be based on various constraints (e.g., objects that are unlikely to be paired with each other may not be loaded into the 3D environment together), probability distributions (e.g., randomization of a number of objects loaded follows a probability distribution of a number of objects in a real world environment corresponding to the 3D environment), and/or variations thereof. A simulator  104  may randomize configurations (e.g., lighting configurations such as light intensity, light frequency, and light color, object configurations such as object number, object combinations, and object pose, and environmental configurations such as weather effects, background, and scene) of a 3D environment based on probability distributions of values of the configurations from one or more real world environments corresponding to the 3D environment. 
     A simulator  104  may vary time intervals to capture images of a 3D environment. A simulator  104  may vary angles or positions of a view of a 3D environment to capture images of the 3D environment. For example, a simulator  104  generates images of a 3D environment comprising objects, in which the images comprise views of the 3D environment at various angles and/or positions, views of the 3D environment with different lighting configurations and/or physics, and views of the 3D environment with the objects in different sizes, positions, orientations, and/or poses. 
     A simulator  104  may generate images for one or more 3D models of 3D models  102 , in which each image may be associated with labels that indicate classifications and locations of objects of the image. Labels may include coordinates corresponding to bounding boxes of objects, including 2D bounding boxes and/or 3D bounding boxes, and corresponding indications of classifications of the objects of the bounding boxes. Further information regarding scene images and labels can be found in the description of  FIG. 2 . 
     A simulator  104  may generate training data (e.g., object images and labels  106  and/or scene images and labels  108 ) to train one or more neural networks, such as a classification neural network. A classification neural network, also referred to as a classifier neural network, may refer to one or more neural networks that may be trained to detect and/or classify objects from images and/or video of the objects. A classification neural network may comprise various neural network models such as a perceptron model, a radial basis network (RBN), an auto encoder (AE), Boltzmann Machine (BM), Restricted Boltzmann Machine (RBM), deep belief network (DBN), deep convolutional network (DCN), extreme learning machine (ELM), deep residual network (DRN), support vector machines (SVM), and/or variations thereof. A simulator  104  may generate images of objects to train one or more neural networks to detect the objects from the images. For example, 3D models  102  comprise models of one or more objects (e.g., foods, drinks, household items), in which a simulator  104  generates images of the one or more objects. Continuing with the example, the simulator  104  generates object images and labels  106  that comprise images of objects of the one or more objects in different orientations, locations, positions, environments, lighting conditions, and the like, and labels of classifications and locations of the objects. Continuing with the example, the simulator  104  generates scene image and labels  108  that comprise images of multiple objects of the one or more objects in different orientations, locations, positions, environments, and/or lighting conditions, and labels of classifications and locations of the multiple objects. Further continuing with the example, a neural network is trained with images and labels of object images and labels  106  and scene images and labels  108  to detect and classify the one or more objects from images of the one or more objects. 
       FIG. 2  illustrates an example  200  of a simulator generating scene images and labels, in accordance with at least one embodiment. 3D models  202 , a simulator  204 , and scene images and labels  206  may be in accordance with those discussed in connection with  FIG. 1 . 
     3D models  202  may be a collection of one or more 3D models of one or more objects. In an embodiment, a 3D model refers to a representation of an object in three dimensions. 3D models  202  may comprise 3D models of various objects, including but not limited to: foods, drinks, clothing items, books, toys, electronics, humans, animals, vehicles, and the like. In an embodiment, 3D models  202  comprise 3D models of objects that may be found in a self-service shop such as a supermarket. 3D models  202  may comprise 3D models of objects that may exist in a retail store or other shop. 3D models  202  may comprise 3D models of human faces. Referring to  FIG. 2 , 3D models  202  may comprise a model of a cylinder object, a model of a pyramid object, a model of a rectangular prism object, and may further comprise other models not depicted in  FIG. 2 . 
     In an embodiment, a simulator  204  is a collection of one or more hardware and/or software computing resources with instructions that, when executed, generates images from 3D models of objects. A simulator  204  may be a software program, application, or the like. A simulator  204  may generate various 3D environments with various properties that may correspond to properties of real-world environments, such as properties of physics, lighting, or other environmental effects. A 3D environment may be generated with various properties such as gravity, texture, object physics, that may simulate a real-world environment; the 3D environment generated by a simulator  204  may correspond to any suitable real-world environment, such as an interior of a shop, store (e.g., retail store), showroom, gallery, factory, production line, warehouse, supermarket, building, or other environment. In an embodiment, a 3D environment generated by a simulator  204  is an environment of a point of sale or point of purchase location that comprises various objects and devices, such as payment terminals, checkout stands, and/or conveyor belts. 
     A simulator  204  may render images of a 3D environment using various rendering techniques, such as ray tracing and/or path tracing, such that the rendered images may be photo-realistic. A simulator  204  may render images of 3D environments comprising objects and generate associated labels that indicate classifications and locations of objects of the images of the 3D environments. Labels may include coordinates corresponding to bounding boxes of objects, including 2D bounding boxes and/or 3D bounding boxes, and corresponding indications of classifications of the objects of the bounding boxes. In some examples, labels indicating bounding boxes of objects of a particular image are only generated for objects of the image that are visible. A simulator  204  may utilize ray tracing in one or more processes of rendering an image of a scene comprising objects to determine which objects of the objects are visible as depicted in the image, and generate labels indicating bounding boxes for the visible objects. 
     A simulator  204  may generate scene images and labels  206 , which may be a collection of one or more images of 3D environments comprising one or more objects and associated labels of the objects. A simulator  204  may generate scene images by generating a 3D environment, loading one or more 3D models of objects of 3D models  202  into the 3D environment, and capturing images of the 3D environment. A 3D environment may comprise a spawning point, which may be a location or position within the 3D environment in which 3D models of objects are loaded. A 3D environment may comprise a vanishing point, which may be a location or position within the 3D environment in which 3D models of objects, when moved to the vanishing point, are removed or otherwise disappear from the 3D environment. 
     A simulator  204  may load objects into a scene in various time intervals. Each object may have various phases within a scene, such as a physics phase, a render phase, and a moving phase. In a physics phase, an object may be dropped or otherwise loaded onto a plane of a scene, and its orientation and height on a flat surface may be determined and recorded. In a rendering phase, textures of an object may be loaded onto the object, in which the object may or may not be moving in a scene. In a physics phase and a rendering phase, an object may be invisible. In a moving phase, an object may be loaded or spawned at a spawning point with its recorded orientation and height, and images may be captured of the object in various time intervals; and a name or other identifier, and 2D and/or 3D bounding boxes of the object may be stored. An object may be removed from a scene when it reaches a vanishing point. In an embodiment, a simulator  204  generates a 3D environment of a checkout counter or stand with various objects of 3D models  202  and generates images of the 3D environment with the various objects. A simulator  204  may generate a 3D environment of a checkout counter or stand with a conveyor belt and load one or more objects of 3D models  202  into the 3D environment, in which the one or more objects may be moved across the conveyor belt and the simulator  204  may capture one or more images from a viewpoint above the conveyor belt. 
     A simulator  204  may configure various aspects of objects loaded into a 3D environment, such as sizes or scales of objects. A simulator  204  may vary time intervals to capture images of a 3D environment. A simulator  204  may vary angles or positions of a view of a 3D environment to capture images of the 3D environment. For example, a simulator  204  performs a plurality of physics-based simulations of objects in a 3D environment, and generates images of the 3D environment, in which the images comprise views of the 3D environment at various angles and/or positions, views of the 3D environment with different lighting configurations and/or physics, and views of the 3D environment with the objects in different sizes, positions, and/or orientations. A simulator  204  may perform a plurality of physics-based simulations. A physics-based simulation may be in accordance with those discussed in connection with  FIG. 1 . A 3D environment generated by a simulator  204  may simulate gravitational effects (e.g., objects of the 3D environment may behave as if affected by gravity), frictional effects (e.g., objects of the 3D environment may behave as if affected by friction), physical effects (e.g., objects of the 3D environment may behave according to the laws of motion), and/or variations thereof. A simulator  204  may vary effects simulated in a generated 3D environment, such as using different values of gravitational force, applying different coefficients of friction, varying constraints of the laws of motion, and/or variations thereof. 
     Scene images and labels  206  may comprise images  208 A,  208 B,  208 C, and may further include images not depicted in  FIG. 2 . Images  208 A,  208 B, and  208 C may each be associated with labels that indicate classifications and/or locations (e.g., bounding boxes and corresponding indications) of objects of the images  208 A,  208 B, and  208 C. Images  208 A,  208 B, and  208 C may be images of 3D environments comprising objects of 3D models  202 . In an embodiment, images  208 A,  208 B, and  208 C are images of a 3D environment comprising objects, and depict views of the 3D environment at various angles and/or positions, views of the 3D environment with different lighting configurations and/or physics, and views of the 3D environment with the objects in different sizes, positions, and/or orientations. For example, a coordinate system is defined for a 3D environment in which views of the 3D environment comprise views of the 3D environment at various angles relative to a particular axis of the coordinate system. A simulator  204  may rotate objects of a 3D environment, and may capture images at each rotation of the objects. A simulator  204  may rotate objects of a 3D environment to capture images of the top, bottom, left, right, front, and back sides of the objects of the 3D environment. 
     In an embodiment, referring to  FIG. 2 , image  208 A depicts a view of a 3D environment with a particular lighting configuration comprising a pyramid object, a rectangular prism object, and a cylinder object. In an embodiment, referring to  FIG. 2 , image  208 B depicts another view of a 3D environment with a particular lighting configuration comprising a pyramid object, a rectangular prism object, and a cylinder object, in which the pyramid object, the rectangular prism object, and the cylinder object are of different sizes and/or orientations than a pyramid object, a rectangular prism object and a cylinder object of a 3D environment depicted in image  208 A. In an embodiment, referring to  FIG. 2 , image  208 C depicts another view of a 3D environment with a particular lighting configuration comprising a pyramid object, a rectangular prism object, and a cylinder object, in which an arrangement of objects in the 3D environment is the same as an arrangement of objects in a 3D environment depicted in image  208 B, but the particular lighting configuration of the 3D environment is different from a lighting configuration of the 3D environment depicted in image  208 B. 
     Scene images and labels  206  may be utilized to train one or more neural networks to detect and/or classify objects (e.g., from one or more images or videos). For example, 3D models  202  comprise models of one or more objects (e.g., foods, drinks, household items), in which a simulator  204  generates scene images and labels  206  comprising images of the one or more objects in different orientations, locations, positions, environments, and/or lighting conditions, and labels of classifications and locations of the objects of the images. Continuing with the example, a neural network is trained with images and labels of scene images and labels  206  to detect and classify the one or more objects from images or videos of the one or more objects. In an embodiment, a simulator  204  generates a 3D environment of a checkout counter or stand with a conveyor belt with one or more objects, varies orientations, locations, positions, environments, and/or lighting conditions of the one or more objects within the 3D environment, and generates scene images and labels  206  that comprise images of the one or more objects in different orientations, locations, positions, environments and/or lighting conditions on the conveyor belt, in which the scene images and labels  206  are utilized to train a neural network to detect and classify the one or more objects from images and/or videos of the one or more objects on a conveyor belt. 
       FIG. 3  illustrates an example  300  of a simulator generating object images and labels, in accordance with at least one embodiment. 3D models  302 , a simulator  304 , and object images and labels  306  may be in accordance with those discussed in connection with  FIG. 1  and  FIG. 2 . 
     3D models  302  may be a collection of one or more 3D models of one or more objects. In an embodiment, a 3D model refers to a representation of an object in three dimensions. 3D models  302  may comprise 3D models of various objects, including but not limited to: foods, drinks, clothing items, books, toys, electronics, humans, animals, vehicles, and the like. In an embodiment, 3D models  302  comprise 3D models of objects that may be found in shops with self-service facilities, such as a supermarket. 3D models  302  may comprise 3D models of objects that may exist in a retail store or other shop. 3D models  302  may comprise 3D models of human faces. Referring to  FIG. 3 , 3D models  302  may comprise a model of a cylinder object, a model of a pyramid object, a model of a rectangular prism object, and may further comprise other models not depicted in  FIG. 3 . 
     In an embodiment, a simulator  304  is a collection of one or more hardware and/or software computing resources with instructions that, when executed, generates images from 3D models of objects. A simulator  304  may be a software program, application, or the like. A simulator  304  may generate various 3D environments with various properties that may correspond to properties of real-world environments, such as properties of physics (such as, without limitation, gravity), lighting, or other environmental effects. A 3D environment may be generated with various properties that may simulate a real-world environment; the 3D environment may simulate a real-world environment by simulating properties such as gravity, texture, object physics, and the like. A simulator  304  may perform a plurality of physics-based simulations. A physics-based simulation may be in accordance with those discussed in connection with  FIG. 1 . A 3D environment generated by a simulator  304  may simulate gravitational effects (e.g., objects of the 3D environment may behave as if affected by gravity), frictional effects (e.g., objects of the 3D environment may behave as if affected by friction), physical effects (e.g., objects of the 3D environment may behave according to the laws of motion), and/or variations thereof. A simulator  304  may vary effects simulated in a generated 3D environment, such as using different values of gravitational force, applying different coefficients of friction, varying constraints of the laws of motion, and/or variations thereof. 
     A simulator  304  may render images of objects using various rendering techniques, such as ray tracing and/or path tracing, such that the rendered images may be photo-realistic. A simulator  304  may render images of objects and generate associated labels that indicate classifications and locations of the objects of the images. Labels may include coordinates corresponding to bounding boxes of objects, including 2D bounding boxes and/or 3D bounding boxes, and corresponding indications of classifications of the objects of the bounding boxes. 
     A simulator  304  may generate object images and labels  306 , which may be a collection of one or more images of objects and associated labels of the objects. A simulator  304  may generate object images by viewing each 3D model of 3D models  302  from different angles and capturing images of each 3D model from the different angles. Objects may be identified from captured images according to their 2D bounding boxes, and one or more backgrounds may be applied to the objects to generate the object images. The one or more backgrounds may include any suitable background, environment, location, and the like, such as various locations in a supermarket. A simulator  304  may generate a 3D environment with a directional light, load a 3D model (e.g., a 3D model of an object from 3D models  302 ) in the 3D environment, rotate the 3D model and/or rotate the directional light, and capture images of the 3D model in different positions and/or different lighting directions. 
     A simulator  304  may configure various aspects of an object to capture images of the object, such as sizes or scales of the object. A simulator  304  may vary angles or positions of a view of an object to capture images of the object. For example, a simulator  304  performs a plurality of physics-based simulations of an object, and generates images of the object, in which the images comprise views of the object at various angles and/or positions, views of the object with different lighting configurations and/or physics, and views of the object in different sizes, positions, and/or orientations. 
     Object images and labels  306  may comprise images  308 A,  308 B,  308 C, and may further include images not depicted in  FIG. 3 . Images  308 A,  308 B, and  308 C may each be associated with labels that indicate classifications and/or locations (e.g., bounding boxes and corresponding indications) of objects of the images  308 A,  308 B, and  308 C. Images  308 A,  308 B, and  308 C may be images of objects of 3D models  302 . In an embodiment, images  308 A,  308 B, and  308 C are images of an object, and depict views of the object at various angles and/or positions, views of the object with different lighting configurations and/or physics, and views of the object in different sizes, positions, and/or orientations. 
     In an embodiment, referring to  FIG. 3 , image  308 A depicts a rectangular prism object in a particular orientation and lighting configuration. In an embodiment, referring to  FIG. 3 , image  308 B depicts a rectangular prism object, such as a rectangular prism object depicted in image  308 A, in a different orientation and lighting configuration. In an embodiment, referring to  FIG. 3 , image  308 C depicts a rectangular prism object, such as a rectangular prism object depicted in image  308 B, in a different size and lighting configuration. Object images and labels  306  may comprise images of each object of 3D models  302  at various angles, positions, and/or variations thereof, with different lighting configurations, physics, and/or variations thereof, in different sizes, positions, orientations, and/or variations thereof, and the like. 
     Object images and labels  306  may be utilized to train one or more neural networks to detect and/or classify objects (e.g., from one or more images or videos). For example, 3D models  302  comprise models of one or more objects (e.g., foods, drinks, household items), in which a simulator  304  generates object images and labels  306  comprising images of the one or more objects in different orientations, locations, positions, environments, and/or lighting conditions, and labels of classifications and locations of the objects of the images. Continuing with the example, a neural network is trained with images and labels of object images and labels  306  to detect and classify the one or more objects from images or videos of the one or more objects. In an embodiment, a simulator  304  generates object images and labels  306  that comprise images of objects in different orientations, locations, positions, sizes, environments, and/or lighting conditions on a conveyor belt, in which the object images and labels  306  are utilized to train a neural network to detect and classify the objects from images and/or videos of the objects on a conveyor belt. 
       FIG. 4  illustrates an example  400  of a user interface of a simulator, in accordance with at least one embodiment. A simulator interface  402  may be a user interface (UI) of a simulator such as those described in connection with  FIGS. 1-3 . In an embodiment, a simulator is a collection of one or more hardware and/or software computing resources with instructions that, when executed, generates images from 3D models of objects. A simulator may be a software program, application, or the like, and may be executing on one or more computing devices in which one or more users may utilize a simulator interface  402  to interact with the simulator. A simulator may provide various functionalities that may be accessible via a simulator interface  402 . 
     A simulator interface  402  may be an interface of a simulator. A simulator interface  402  may comprise various UI elements that users may interact with to cause a simulator to perform one or more operations. A UI element may be referred to as a button, button element, button widget, and/or variations thereof. In an embodiment, a simulator is a software application that provides a simulator interface  402 , which is a UI that users interact with to cause the simulator to perform various operations, such as generating images from 3D models of objects. A simulator may be executing on one or more computing devices, in which a user may interact with a simulator interface  402  through one or more user input hardware of the one or more computing devices, such as a mouse, keyboard, touchscreen, and the like. 
     A simulator may provide functionalities to generate images of objects that may be accessible through an image generation  404  UI element. An image generation  404  UI element may be utilized to generate object images and labels, such as those discussed in connection with  FIG. 3 . An image generation  404  UI element may comprise at least a models location  404 A UI element, a resolution  404 B UI element, an image wait time  404 C UI element, an object wait time  404 D UI element, a spacing  404 E UI element, an output images location  404 F UI element, a models list  404 G UI element, and a run  404 H UI element. 
     A models location  404 A UI element may be utilized to specify a location of one or more 3D models. An input to a models location  404 A UI element may include a location, such as a file system location and/or network location, of one or more 3D models. One or more 3D models may be in various formats, such as compressed file formats and/or uncompressed file formats. One or more 3D models may be stored in groups or in folders, and may be associated with index numbers. In an embodiment, 3D models are identified by an index number associated with a computer folder or file location. A simulator may also provide functionalities to manipulate files corresponding to 3D models, such as un-compressing the files, compressing the files, moving the files from one or more locations to one or more other locations, and/or converting the files to other file formats. 
     A resolution  404 B UI element may be utilized to specify a resolution of images to be generated by a simulator. Inputs to a resolution  404 B UI element may include integer values of a height and a width. In some examples, inputs to a resolution  404 B UI element include one or more values of heights and widths of one or more images to be generated by a simulator. An image wait time  404 C UI element may be utilized to specify a frequency of image capturing of images to be generated or otherwise captured by a simulator. Inputs to an image wait time  404 C UI element may include values of time of which an image is to be captured. For example, if an image wait time UI element  404 C specifies a value of 0.1 seconds, a simulator captures images of an object (e.g., 3D model object) every 0.1 seconds, and the object is rotated according to a specified spacing (e.g., spacing  404 E UI element). An object wait time  404 D UI element may be utilized to specify a time for a simulator to wait before starting to rotate and capture images for an object. Inputs to an object wait time  404 D UI element may include values of time for a simulator to wait. 
     A spacing  404 E UI element may be utilized to specify increments of degrees to capture images of an object. A spacing  404 E UI element may comprise inputs for degrees for an X-axis, a Y-axis, and a Z-axis. Inputs to a spacing  404 E UI element may include values of degrees for an X-axis, a Y-axis, and a Z-axis. An object may be rotated incrementally according to a XYZ Euler angle sequence specified in a spacing  404 E UI element, and images may be captured at each increment. For example, if an X-axis spacing is set to 90 degrees, a simulator samples around an X-axis every 90 degrees; an object may be rotated 0, 90, 180, and 270 degrees and images may be captured at each rotation. For example, if X-axis, Y-axis, and Z-axis spacing are all set to 90 degrees, a simulator captures images of an object rotated at 0, 90, 180, and 270 degrees for each axis, resulting in 64 images (e.g.,  4  rotations for each axis, resulting in 4×4×4=64 images). 
     An output images location  404 F UI element may be utilized to specify an output location for images generated by a simulator. Inputs to an output images location  404 F UI element may include file system location and/or network location, where a simulator may store captured or otherwise generated images and associated labels. A models list  404 G UI element may indicate 3D models that a simulator may utilize to generate images. A models list  404 G UI element may comprise a list of 3D models, in which a simulator may process and generate images for each 3D model of the list of 3D models. A run  404 H UI element may be utilized to cause a simulator to generate images. A run  404 H UI element may be an interactive UI element in which users may utilize to cause a simulator to generate images according to parameters and constraints specified by other UI elements of image generation  404  UI element. 
     An image generation  404  UI element may further comprise other UI elements for various functionalities. An image generation  404  UI element may comprise one or more UI elements that may create folders in file locations for one or more 3D models and files associated with the one or more 3D models. An image generation  404  UI element may comprise one or more UI elements that may be used to generate images for a particular 3D model, or a particular group of 3D models (e.g., model(s) indicated by models location  404 A and/or models list  404 G). An image generation  404  UI element may comprise one or more UI elements that may be used to generate images for a particular specified sequence of 3D models (e.g., models indicated by models location  404 A and/or models list  404 G). 
     A simulator may provide functionalities to generate scene images of objects that may be accessible through a scene generation  406  UI element. A scene generation  406  UI element may be utilized to generate scene images and labels, such as those discussed in connection with  FIG. 2 . A scene generation  406  UI element may comprise at least a models location  406 A UI element, an output images location  406 B UI element, a background  406 C UI element, a models list  406 D UI element, and a run  406 E UI element. 
     A models location  406 A UI element may be in accordance with a models location  404 A UI element. A models location  406 A UI element may be utilized to specify a location of one or more 3D models. An input to a models location  406 A UI element may include a location, such as a file system location and/or network location, of one or more 3D models. An output images location  406 B UI element may be in accordance with an output images location  404 F UI element. An output images location  406 B UI element may be utilized to specify an output location for images generated by a simulator. Inputs to an output images location  406 B UI element may include file system location and/or network location where a simulator may store captured or otherwise generated images and associated labels. 
     A background  406 C UI element may be utilized to specify a background or 3D environment (e.g., a scene) for a simulator to generate. Inputs to a background  406 C UI element may be a 3D model of a 3D environment, one or more images of one or more backgrounds, and the like. A 3D environment or background may correspond to any suitable real-world environment, such as an interior of a shop, store (e.g., retail store), showroom, gallery, factory, production line, warehouse, supermarket, building, or other environment. A 3D environment may be an environment of a point of sale or point of purchase location, and may comprise various objects and devices, such as payment terminals, checkout stands, and/or conveyor belts. A simulator may load a background or 3D environment specified in a background  406 C UI element, and capture images of one or more 3D models in the background or 3D environment in various orientations, locations, positions, environments, and/or lighting conditions. 
     A models list  406 D UI element may be in accordance with a models list  404 G UI element. A models list  406 D UI element may indicate 3D models that a simulator may utilize to generate images. A models list  406 D UI element may comprise a list of 3D models, in which a simulator may process and generate images for one or more 3D models of the list of 3D models. A run  406 E UI element may be in accordance with a run  404 H UI element. A run  406 E UI element may be utilized to cause a simulator to generate images. A run  406 E UI element may be an interactive UI element in which users may utilize to cause a simulator to generate images according to parameters and constraints specified by other UI elements of a scene generation  406  UI element. 
     A scene generation  406  UI element may further comprise other UI elements for various functionalities. A scene generation  406  UI element may comprise one or more UI elements that may configure physics, environmental effects, and/or lighting of a 3D environment or scene. A scene generation  406  UI element may comprise one or more UI elements that may be used to generate images for a particular 3D model, or a particular group of 3D models (e.g., model(s) indicated by models location  406 A and/or models list  406 D). A scene generation  406  UI element may comprise one or more UI elements that may be used to generate images for a particular specified sequence of 3D models (e.g., models indicated by models location  406 A and/or models list  406 D). 
     A simulator may provide functionalities to configure 3D models of objects that may be accessible through a model configuration  408  UI element. A model configuration  408  UI element may be utilized to configure models of images generated in connection with an image generation  404  UI element and a scene generation  406  UI element. A model configuration  408  UI element may be utilized to apply additional manual information to models, such as adjusting sizes, spawn characteristics, and the like. A model configuration  408  UI element may comprise at least a models location  408 A UI element, a models list  408 B UI element, a model select  408 C UI element, a configuration output  408 D UI element, a model configuration  408 E UI element, and a save  408 F UI element. 
     A models location  408 A UI element may be in accordance with a models location  404 A UI element. A models location  408 A UI element may be utilized to specify a location of one or more 3D models. An input to a models location  408 A UI element may include a location, such as a file system location and/or network location, of one or more 3D models. A models list  408 B UI element may be in accordance with a models list  404 G UI element. A models list  408 B UI element may indicate 3D models that a simulator may utilize to generate images. A model select  408 C UI element may be utilized to select a model from a models list  408 B UI element. A model select  408 C UI element may specify a 3D model to configure. Inputs to a model select  408 C UI element may include an indication of a 3D model (e.g., a 3D model from a models list  408 B UI element). 
     A configuration output  408 D UI element may be utilized to specify a location to store one or more configurations of one or more 3D models. Inputs to a configuration output  408 D UI element may include a location such as a file system location and/or network location. A simulator may store configurations of a 3D model (e.g., size, shape, orientation, appearance) in a location specified by a configuration output  408 D UI element. A simulator may utilize stored configurations of a 3D model to determine how to load the 3D model. Configurations may be stored as a text file, with each line in the text file indicating a description of an adjustment made to a model. Configurations may be stored as any suitable data object or structure. 
     A model configuration  408 E UI element may be utilized to specify configurations of a 3D model. A simulator may utilize configurations specified in a model configuration  408 E UI element to configure a 3D model. Configurations may include size adjustments (e.g., changing a scale of a 3D model), shape adjustments (e.g., changing a shape of a 3D model), orientation adjustments (e.g., changing an orientation of a 3D model), appearance adjustments (e.g., changing colors, patterns, or other aspects of an appearance of a 3D model), and the like. A simulator may load a 3D model based on configurations indicated in connection with a model configuration  408 E UI element. 
     A save  408 F UI element may be utilized to save a configuration for a 3D model. A save  408 F UI element may be an interactive UI element in which users may utilize to cause a simulator to save a particular configuration for a 3D model such that when the 3D model is loaded for one or more object images and/or scene images, the 3D model is loaded in accordance with the particular configuration. For example, a user specifies a 3D model of a cylinder in a model select  408 C UI element and a configuration of a first size, first orientation, and first color in a model configuration  408 E UI element, in which, when the 3D model is loaded by a simulator as part of one or more object image and/or scene image generation processes, the 3D model is loaded with the first size, and in the first orientation and the first color. 
     A model configuration  408  UI element may further comprise other UI elements for various functionalities. A model configuration  408  UI element may comprise one or more UI elements that may create folders in file locations for one or more 3D models and configuration files associated with the one or more 3D models. A model configuration  408  UI element may comprise one or more UI elements that may be used to configure a particular 3D model, or a particular group of 3D models (e.g., model(s) indicated by models location  408 A and/or models list  408 B). 
     It should be noted that  FIG. 4  is intended to be an illustrative example of a simulator interface and simulator interfaces may be any suitable variation thereof. A simulator interface may comprise more or fewer UI elements and components than depicted in  FIG. 4  for any suitable simulator functionality, including but not limited to: additional configuration for image generation/scene generation, file manipulation, additional model configuration, and the like. 
       FIG. 5  illustrates an example  500  of training a neural network with a simulator to detect and classify objects, in accordance with at least one embodiment. A simulator  502  may be in accordance with those discussed in connection with  FIGS. 1-4 . A simulator  502  may generate training data  504  comprising training images  506  and labels  508 , which may be used to train an untrained neural network  510  to a trained neural network  512  that may detect and classify objects of an image  514 A as an image  514 B. 
     In an embodiment, a simulator  502  is a collection of one or more hardware and/or software computing resources with instructions that, when executed, generates object images and labels, and scene images and labels from 3D models of objects. A simulator  502  may be a software program, application, or the like, that may generate various 3D environments with various properties that may correspond to properties of real-world environments, such as gravity physics, lighting, or other environmental effects. A simulator  502  may obtain 3D models of various objects. 
     A simulator  502  may generate a 3D environment comprising one or more 3D models. A 3D environment may be generated with various properties that may simulate a real-world environment; the 3D environment may simulate a real-world environment by simulating properties such as gravity, texture, and/or object physics. A 3D environment generated by a simulator  502  may correspond to any suitable real-world environment, such as an interior of a shop, store (e.g., retail store) showroom, gallery, factory, production line, warehouse, supermarket, building, or other environment. In an embodiment, a 3D environment generated by a simulator  502  is an environment of a point of sale or point of purchase location. A point of sale or point of purchase location may comprise various objects and devices, such as payment terminals, checkout stands, and/or conveyor belts. 
     A simulator  502  may generate a 3D environment comprising one or more objects corresponding to one or more 3D models and render images of the 3D environment. A simulator  502  may render images of a 3D environment using various rendering techniques, such as ray tracing and/or path tracing, such that the rendered images may be photo-realistic. A simulator  502  may render images of 3D environments that may be associated with labels that indicate classifications and locations of objects of the images of the 3D environments. Labels may include coordinates corresponding to bounding boxes of objects, including 2D bounding boxes and/or 3D bounding boxes, and corresponding indications of classifications of the objects of the bounding boxes. A 2D bounding box of an object of an image may indicate a location of the object, and a corresponding indication may indicate a classification of the object. A 3D bounding box of an object of an image may indicate a location, size, position, and/or orientation of the object, and a corresponding indication may indicate a classification of the object. 
     A simulator  502  may obtain 3D models of various objects, including but not limited to: foods, drinks, clothing items, books, toys, electronics, humans, animals, vehicles, and the like. In an embodiment, a simulator  502  obtains 3D models of objects that may be found in a self-service shop such as a supermarket. A simulator  502  may generate a 3D environment of a conveyor belt of a checkout counter, load one or more 3D models of one or more objects into the 3D environment, and generate training images  506  comprising images of objects of the one or more objects in different orientations, locations, positions, environments, lighting conditions, and the like and labels  508  comprising labels of classifications and locations of the objects. Each training image of training images  506  may be associated with a set of labels of labels  508 , in which a particular set of labels for a particular image may indicate bounding boxes of objects of the particular image, including 2D bounding boxes and/or 3D bounding boxes, and corresponding indications of classifications of the objects of the bounding boxes. Each training image of training images  506  may comprise various combinations of one or more objects in various orientations, locations, positions, environments, lighting conditions, and the like on a conveyor belt of a checkout counter. 
     A simulator  502  may generate training data  504  comprising training images  506  and associated labels  508 , and use the training data  504  to train an untrained neural network  510 . In some examples, one or more computing systems obtain training data  504  and train an untrained neural network  510  using the training data  504 . Training data  504  may be utilized to train an untrained neural network  510  to detect and classify one or more objects from one or more images. An untrained neural network  510  may be trained by causing the untrained neural network  510  to classify objects of training images  506 , and comparing the classifications with labels  508 . Classifications of objects of training images  506  determined by an untrained neural network  510  may be compared with labels  508  through one or more loss functions, in which the one or more loss functions may be utilized to update one or more components (e.g., weights, nodes, configurations) of the untrained neural network  510  to determine a trained neural network  512 . A trained neural network  512  may be trained such that the trained neural network  512  may accurately detect and classify objects of training images  506 . A trained neural network  512  may be trained such that the trained neural network  512  may generate labels for training images  506  that match or approximately match labels  508 . In an embodiment, a trained neural network  512  is trained using training data  504  to detect and classify one or more objects from one or more images of the one or more objects. 
     A trained neural network  512  may obtain an image  514 A, which may be an image captured from one or more image capturing devices, and may depict one or more objects, such as those of training images  506 . In an embodiment, an image  514 A is captured from one or more cameras of an overhead view of a conveyor belt of a checkout counter or stand. An image  514 A may be any suitable image captured from one or more cameras of one or more objects. A trained neural network  512  may detect and classify one or more objects of an image  514 A and visualize the detected/classified one or more objects in an image  514 B. An image  514 B may be an image  514 A with locations and classifications of objects indicated. A trained neural network  514  may generate an image  514 B from an image  514 A. An image  514 B may be generated from an image  514 A based on one or more locations and classifications of objects determined by a trained neural network  512 . 
     An image  514 B may comprise indications of locations and classifications of objects of an image  514 A. For example, referring to  FIG. 5 , an image  514 A is an image of an overhead view of a conveyor belt of a checkout counter depicting a box object and a can object. Continuing with the example, a trained neural network  512  detects and classifies the box object and the can object of the image  514 A, and visualizes the detection and classification of the box object and the can object as an image  514 B. Further continuing with the example, the image  514 B is the image  514 A with a first bounding box indicating a location of the box object and a first label indicating that the first bounding box comprises a box, and a second bounding box indicating a location of the can object and a second label indicating that the second bounding box comprises a can. 
       FIG. 6  illustrates an example environment  600  of detecting and classifying objects of a checkout counter using a neural network, in accordance with at least one embodiment. A computing device  604  may comprise a neural network that may be trained with training data from a simulator, such as those described in connection with  FIGS. 1-5 . A computing device  604  may be trained to detect and classify objects captured through a camera  602 . A computing device  604  may be trained to detect and classify objects such as various retail products (e.g., foods, drinks, household items). A computing device  604  may detect and classify objects based on images of the objects, and may not need to utilize barcode information on the objects. A computing device  604  may detect and classify objects based on images of the objects in various positions, including positions in which certain products are obscuring other products, and configurations, including low light conditions, variable light conditions, and/or variations thereof. 
     A computing device  604  may comprise one or more collections of hardware and/or software computing resources that may implement a neural network. A computing device  604  may be connected to a camera  602 , which may capture video and/or images and provide the captured video and/or images to the computing device  604 . A neural network of a computing device  604  may be trained using training images and labels generated by a simulator. A simulator may obtain 3D models of objects that may be found in a self-service shop such as a supermarket. A simulator may generate a 3D environment of a conveyor belt of a checkout counter, load one or more 3D models of one or more objects into the 3D environment, and generate training images comprising images of objects of the one or more objects in different orientations, locations, positions, environments, and/or lighting conditions and labels comprising labels of classifications and locations of the objects. 
     One or more systems may utilize training data and labels generated by a simulator to train a neural network of a computing device  604  by causing the neural network to classify objects of training images, and comparing the classifications with associated labels. Classifications of objects of training images determined by a neural network of a computing device  604  may be compared with associated labels through one or more loss functions, in which the one or more loss functions may be utilized to update one or more components (e.g., weights, nodes, configurations) of the neural network to train the neural network. A neural network of a computing device  604  may be trained such that the neural network may accurately detect and classify one or more objects from image and/or video of the one or more objects. 
     A computing device  604  and a camera  602  may be located at a checkout counter or stand with a conveyor belt, and the camera  602  may be positioned to have an overhead view of the conveyor belt. Objects  606 ,  608 , and  610  may be placed on a conveyor belt. Objects  606 ,  608 , and  610  may be objects such as products found in a supermarket store. A camera  602  may capture video and/or images of objects  606 ,  608 , and  610  on a conveyor belt and provide the video and/or images of the objects  606 ,  608 , and  610  to a computing device  604 . A computing device  604  may detect and classify objects  606 ,  608 , and  610 . Referring to  FIG. 6 , object  606  may be a cake box, object  608  may be a cake box in a different orientation, and object  610  may be a soup can. Referring to  FIG. 6 , a neural network of a computing device  604  may detect object  606  and classify the object  606  as cake (e.g., through a bounding box indicating a location and classification of the object  606 ), detect object  608  and classify the object  608  as cake (e.g., through a bounding box indicating a location and classification of the object  608 ), and detect object  610  and classify the object  610  as soup (e.g., through a bounding box indicating a location and classification of the object  610 ). 
     It should be noted that, while  FIG. 6  depicts a neural network trained to detect and classify objects or products in various positions, orientations, appearances, conditions, and the like, a simulator may be used to train any suitable neural network to detect and classify any suitable objects in a suitable positions, orientations, appearances, conditions, and the like. For example, a simulator generates training images of faces in various positions, orientations, appearances, conditions, and the like to train a neural network to detect and classify the faces in various positions, orientations, appearances, conditions, and the like. For example, a simulator generates training images of vehicles in various positions, orientations, appearances, conditions, and the like to train a neural network to detect and classify the vehicles in various positions, orientations, appearances, conditions, and the like. Other variations are within the scope of the present disclosure. 
       FIG. 7  shows an illustrative example of a process  700  to perform simulations to obtain training data, in accordance with at least one embodiment. Some or all of the process  700  (or any other processes described herein, or variations and/or combinations thereof) may be performed under control of one or more computer systems configured with computer-executable instructions and may be implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) executing collectively on one or more processors, by hardware, software, or combinations thereof. Code may be stored on a computer-readable storage medium in form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. A computer-readable storage medium may be a non-transitory computer-readable medium. At least some computer-readable instructions usable to perform the process  700  may not be stored solely using transitory signals (e.g., a propagating transient electric or electromagnetic transmission). A non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within transceivers of transitory signals. In an embodiment, the process  700  is performed at least in part on a computer system such as those described elsewhere in this disclosure. 
     A system performing at least a part of the process  700  includes executable code to at least obtain  702  a model of a physical object, such as a 3D model. 3D models may include solid 3D models, which define a volume of an object represented, shell/boundary 3D models, which represent a surface/boundary of an object, and/or variations thereof. A 3D model may be encoded or otherwise stored in one or more computer files. A system may obtain a model from one or more databases of 3D models. A system may obtain a model from one or more systems that may generate 3D models from images. 
     A system performing at least a part of the process  700  includes executable code to at least use  704  the model of the physical object to perform a plurality of physics-based simulations of the physical object. A system may generate a 3D environment, also referred to as a physics-based simulation, comprising one or more models. A 3D environment may be generated with various properties that may simulate a real-world environment; the 3D environment may simulate a real-world environment by simulating properties such as gravity, texture, and/or object physics. A 3D environment generated by a system may correspond to any suitable real-world environment, such as an interior of a shop, store (e.g., retail store), showroom, gallery, factory, production line, warehouse, supermarket, building, or other environment. In an embodiment, a 3D environment generated by a system is an environment of a point of sale or point of purchase location. A point of sale or point of purchase location may comprise various objects and devices, such as payment terminals, checkout stands, and/or conveyor belts. A system may generate a 3D environment comprising one or more objects in different sizes, positions, orientations, poses, and/or variations thereof, and render images of the 3D environment. 
     A system performing at least a part of the process  700  includes executable code to at least obtain  706 , based at least in part on results of the plurality of physics-based simulations, a plurality of training data to train a neural network. A system may capture images of the plurality of physics-based simulations of the physical object and generate labels that indicate classifications and locations of the physical object of the images. Labels may include coordinates corresponding to bounding boxes of objects, including 2D bounding boxes and/or 3D bounding boxes, and corresponding indications of classifications of the objects of the bounding boxes. A plurality of training data may comprise training images and associated labels. A system may utilize the plurality of training data to train one or more neural networks, such as a classification neural network. A classification neural network, also referred to as a classifier neural network, may refer to one or more neural networks that may be trained to detect and/or classify objects from images and/or video of the objects. Further information regarding training a neural network can be found in the description of  FIG. 8 . 
       FIG. 8  shows an illustrative example of a process  800  to train a neural network using training data, in accordance with at least one embodiment. Some or all of the process  800  (or any other processes described herein, or variations and/or combinations thereof) may be performed under control of one or more computer systems configured with computer-executable instructions and may be implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) executing collectively on one or more processors, by hardware, software, or combinations thereof. Code may be stored on a computer-readable storage medium in form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. A computer-readable storage medium may be a non-transitory computer-readable medium. At least some computer-readable instructions usable to perform the process  800  may not be stored solely using transitory signals (e.g., a propagating transient electric or electromagnetic transmission). A non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within transceivers of transitory signals. In an embodiment, the process  800  is performed at least in part on a computer system such as those described elsewhere in this disclosure. 
     A system performing at least a part of the process  800  includes executable code to at least obtain  802  3D models of objects. One or more systems may obtain 3D models of one or more objects and provide the 3D models to a simulator. A system may generate various 3D environments with various properties that may correspond to properties of real-world environments, such as properties of physics, lighting, or other environmental effects. A system may generate a 3D environment comprising one or more 3D models. A 3D environment may be generated using physics-based simulation (e.g., based on various properties that may simulate a real-world environment), which was described in more detail with respect to  FIG. 1  above that may simulate a real-world environment by simulating properties such as gravity, texture, and/or object physics. 
     A system performing at least a part of the process  800  includes executable code to at least generate  804  training images and labels. A system may generate a 3D environment comprising one or more objects corresponding to one or more 3D models and render images of the 3D environment. A system may render images of a 3D environment using various rendering techniques, such as ray tracing and/or path tracing, such that the rendered images may be photo-realistic. A system may render images of 3D environments that may be associated with labels that indicate classifications and locations of objects of the images of the 3D environments. Labels may include coordinates corresponding to bounding boxes of objects, including 2D bounding boxes and/or 3D bounding boxes, and corresponding indications of classifications of the objects of the bounding boxes. A system may generate training images and labels. Training images may comprise images depicting various combinations of the objects in various orientations, locations, positions, environments, and/or lighting conditions. 
     A system performing at least a part of the process  800  includes executable code to at least input  806  training images to a neural network to determine classifications. One or more systems may cause a neural network to detect and classify objects of training images. One or more systems may cause a neural network to determine classifications of objects of training images. A system performing at least a part of the process  800  includes executable code to at least compare  808  the classifications and the labels to update the neural network. Classifications of objects of training images determined by a neural network may be compared with labels through one or more loss functions, in which the one or more loss functions may be utilized to update one or more components (e.g., weights, nodes, configurations) of the neural network to train the neural network. A trained neural network may be trained such that the trained neural network may accurately detect and classify objects of training images. 
     A system performing at least a part of the process  800  includes executable code to at least use  810  the neural network to detect and classify the objects from images of the objects. For example, a neural network is trained and utilized in connection with  FIG. 6 . A neural network may be trained to detect and classify objects from images of the objects that may be captured from one or more cameras. In some examples, a neural network is trained to detect and classify objects that may be updated (e.g., updated appearance, shape), in which the neural network may be retrained to detect and classify the updated objects. A neural network may require less resources to train to detect and classify updated objects, as the neural network may already be trained to detect and classify the previous versions of the objects. Changes to particular objects may be reflected in 3D models of objects used to generate training data for a neural network such that the neural network may be trained to detect and classify updated objects. A neural network may be utilized for fraud detection in one or more environments. A neural network may obtain an image of an object, in which the object may be associated with a code (e.g., a barcode, QR code, or other identifier) that may be on the object that may indicate information of the object (e.g., a classification or label). Codes may be associated with one or more databases (e.g., barcode or QR code databases) that a neural network may interact with or perform one or more searches in connection with to determine information, such as classifications, labels, and/or variations thereof, of the codes. A neural network may determine a classification of an object based on an image of the object, and determine whether a code on the object indicates information that matches the determined classification; if the information does not match, the neural network may determine that the code was incorrectly or fraudulently placed on the object. For example, a neural network obtains an image of an object with a barcode, and the neural network classifies the object based on the image. Continuing with the example, the neural network obtains the barcode, and performs one or more searches in connection with one or more barcode databases to determine a barcode classification of the object. Further continuing with the example, the neural network compares its classification with the barcode classification; if they do not match, the neural network may determine that the barcode was incorrectly or fraudulently placed on the object. 
     In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concepts may be practiced without one or more of these specific details. 
     Data Center 
       FIG. 9  illustrates an exemplary data center  900 , in accordance with at least one embodiment. In at least one embodiment, data center  900  includes, without limitation, a data center infrastructure layer  910 , a framework layer  920 , a software layer  930  and an application layer  940 . 
     In at least one embodiment, as shown in  FIG. 9 , data center infrastructure layer  910  may include a resource orchestrator  912 , grouped computing resources  914 , and node computing resources (“node C.R.s”)  916 ( 1 )- 916 (N), where “N” represents any whole, positive integer. In at least one embodiment, node C.R.s  916 ( 1 )- 916 (N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (“FPGAs”), data processing units (“DPUs”) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid state or disk drives), network input/output (“NW I/O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.s from among node C.R.s  916 ( 1 )- 916 (N) may be a server having one or more of above-mentioned computing resources. 
     In at least one embodiment, grouped computing resources  914  may include separate groupings of node C.R.s housed within one or more racks (not shown), or many racks housed in data centers at various geographical locations (also not shown). Separate groupings of node C.R.s within grouped computing resources  914  may include grouped compute, network, memory or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.s including CPUs or processors may grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination. 
     In at least one embodiment, resource orchestrator  912  may configure or otherwise control one or more node C.R.s  916 ( 1 )- 916 (N) and/or grouped computing resources  914 . In at least one embodiment, resource orchestrator  912  may include a software design infrastructure (“SDI”) management entity for data center  900 . In at least one embodiment, resource orchestrator  912  may include hardware, software or some combination thereof. 
     In at least one embodiment, as shown in  FIG. 9 , framework layer  920  includes, without limitation, a job scheduler  932 , a configuration manager  934 , a resource manager  936  and a distributed file system  938 . In at least one embodiment, framework layer  920  may include a framework to support software  952  of software layer  930  and/or one or more application(s)  942  of application layer  940 . In at least one embodiment, software  952  or application(s)  942  may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud and Microsoft Azure. In at least one embodiment, framework layer  920  may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may utilize distributed file system  938  for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler  932  may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center  900 . In at least one embodiment, configuration manager  934  may be capable of configuring different layers such as software layer  930  and framework layer  920 , including Spark and distributed file system  938  for supporting large-scale data processing. In at least one embodiment, resource manager  936  may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system  938  and job scheduler  932 . In at least one embodiment, clustered or grouped computing resources may include grouped computing resource  914  at data center infrastructure layer  910 . In at least one embodiment, resource manager  936  may coordinate with resource orchestrator  912  to manage these mapped or allocated computing resources. 
     In at least one embodiment, software  952  included in software layer  930  may include software used by at least portions of node C.R.s  916 ( 1 )- 916 (N), grouped computing resources  914 , and/or distributed file system  938  of framework layer  920 . One or more types of software may include, but are not limited to, Internet web page search software, e-mail virus scan software, database software, and streaming video content software. 
     In at least one embodiment, application(s)  942  included in application layer  940  may include one or more types of applications used by at least portions of node C.R.s  916 ( 1 )- 916 (N), grouped computing resources  914 , and/or distributed file system  938  of framework layer  920 . In at least one or more types of applications may include, without limitation, CUDA applications. 
     In at least one embodiment, any of configuration manager  934 , resource manager  936 , and resource orchestrator  912  may implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions may relieve a data center operator of data center  900  from making possibly bad configuration decisions and possibly avoiding underutilized and/or poor performing portions of a data center. 
     Computer-Based Systems 
     The following figures set forth, without limitation, exemplary computer-based systems that can be used to implement at least one embodiment. 
       FIG. 10  illustrates a processing system  1000 , in accordance with at least one embodiment. In at least one embodiment, processing system  1000  includes one or more processors  1002  and one or more graphics processors  1008 , and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors  1002  or processor cores  1007 . In at least one embodiment, processing system  1000  is a processing platform incorporated within a system-on-a-chip (“SoC”) integrated circuit for use in mobile, handheld, or embedded devices. 
     In at least one embodiment, processing system  1000  can include, or be incorporated within a server-based gaming platform, a game console, a media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, processing system  1000  is a mobile phone, smart phone, tablet computing device or mobile Internet device. In at least one embodiment, processing system  1000  can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In at least one embodiment, processing system  1000  is a television or set top box device having one or more processors  1002  and a graphical interface generated by one or more graphics processors  1008 . 
     In at least one embodiment, one or more processors  1002  each include one or more processor cores  1007  to process instructions which, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores  1007  is configured to process a specific instruction set  1009 . In at least one embodiment, instruction set  1009  may facilitate Complex Instruction Set Computing (“CISC”), Reduced Instruction Set Computing (“RISC”), or computing via a Very Long Instruction Word (“VLIW”). In at least one embodiment, processor cores  1007  may each process a different instruction set  1009 , which may include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core  1007  may also include other processing devices, such as a digital signal processor (“DSP”). 
     In at least one embodiment, processor  1002  includes cache memory (‘cache”)  1004 . In at least one embodiment, processor  1002  can have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor  1002 . In at least one embodiment, processor  1002  also uses an external cache (e.g., a Level 3 (“L3”) cache or Last Level Cache (“LLC”)) (not shown), which may be shared among processor cores  1007  using known cache coherency techniques. In at least one embodiment, register file  1006  is additionally included in processor  1002  which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). In at least one embodiment, register file  1006  may include general-purpose registers or other registers. 
     In at least one embodiment, one or more processor(s)  1002  are coupled with one or more interface bus(es)  1010  to transmit communication signals such as address, data, or control signals between processor  1002  and other components in processing system  1000 . In at least one embodiment interface bus  1010 , in one embodiment, can be a processor bus, such as a version of a Direct Media Interface (“DMI”) bus. In at least one embodiment, interface bus  1010  is not limited to a DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., “PCI,” PCI Express (“PCIe”)), memory buses, or other types of interface buses. In at least one embodiment processor(s)  1002  include an integrated memory controller  1016  and a platform controller hub  1030 . In at least one embodiment, memory controller  1016  facilitates communication between a memory device and other components of processing system  1000 , while platform controller hub (“PCH”)  1030  provides connections to Input/Output (“I/O”) devices via a local I/O bus. 
     In at least one embodiment, memory device  1020  can be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as processor memory. In at least one embodiment memory device  1020  can operate as system memory for processing system  1000 , to store data  1022  and instructions  1021  for use when one or more processors  1002  executes an application or process. In at least one embodiment, memory controller  1016  also couples with an optional external graphics processor  1012 , which may communicate with one or more graphics processors  1008  in processors  1002  to perform graphics and media operations. In at least one embodiment, a display device  1011  can connect to processor(s)  1002 . In at least one embodiment display device  1011  can include one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device  1011  can include a head mounted display (“HMD”) such as a stereoscopic display device for use in virtual reality (“VR”) applications or augmented reality (“AR”) applications. 
     In at least one embodiment, platform controller hub  1030  enables peripherals to connect to memory device  1020  and processor  1002  via a high-speed I/O bus. In at least one embodiment, I/O peripherals include, but are not limited to, an audio controller  1046 , a network controller  1034 , a firmware interface  1028 , a wireless transceiver  1026 , touch sensors  1025 , a data storage device  1024  (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device  1024  can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as PCI, or PCIe. In at least one embodiment, touch sensors  1025  can include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver  1026  can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (“LTE”) transceiver. In at least one embodiment, firmware interface  1028  enables communication with system firmware, and can be, for example, a unified extensible firmware interface (“UEFI”). In at least one embodiment, network controller  1034  can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples with interface bus  1010 . In at least one embodiment, audio controller  1046  is a multi-channel high definition audio controller. In at least one embodiment, processing system  1000  includes an optional legacy I/O controller  1040  for coupling legacy (e.g., Personal System 2 (“PS/2”)) devices to processing system  1000 . In at least one embodiment, platform controller hub  1030  can also connect to one or more Universal Serial Bus (“USB”) controllers  1042  connect input devices, such as keyboard and mouse  1043  combinations, a camera  1044 , or other USB input devices. 
     In at least one embodiment, an instance of memory controller  1016  and platform controller hub  1030  may be integrated into a discreet external graphics processor, such as external graphics processor  1012 . In at least one embodiment, platform controller hub  1030  and/or memory controller  1016  may be external to one or more processor(s)  1002 . For example, in at least one embodiment, processing system  1000  can include an external memory controller  1016  and platform controller hub  1030 , which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with processor(s)  1002 . 
       FIG. 11  illustrates a computer system  1100 , in accordance with at least one embodiment. In at least one embodiment, computer system  1100  may be a system with interconnected devices and components, a SoC, or some combination. In at least on embodiment, computer system  1100  is formed with a processor  1102  that may include execution units to execute an instruction. In at least one embodiment, computer system  1100  may include, without limitation, a component, such as processor  1102  to employ execution units including logic to perform algorithms for processing data. In at least one embodiment, computer system  1100  may include processors, such as PENTIUM® Processor family, Xeon™, Itanium®, XScale™ and/or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, Calif., although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and like) may also be used. In at least one embodiment, computer system  1100  may execute a version of WINDOWS&#39; operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux for example), embedded software, and/or graphical user interfaces, may also be used. 
     In at least one embodiment, computer system  1100  may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (DSP), a SoC, network computers (“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system that may perform one or more instructions. 
     In at least one embodiment, computer system  1100  may include, without limitation, processor  1102  that may include, without limitation, one or more execution units  1108  that may be configured to execute a Compute Unified Device Architecture (“CUDA”) (CUDA® is developed by NVIDIA Corporation of Santa Clara, Calif.) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in a CUDA programming language. In at least one embodiment, computer system  1100  is a single processor desktop or server system. In at least one embodiment, computer system  1100  may be a multiprocessor system. In at least one embodiment, processor  1102  may include, without limitation, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In at least one embodiment, processor  1102  may be coupled to a processor bus  1110  that may transmit data signals between processor  1102  and other components in computer system  1100 . 
     In at least one embodiment, processor  1102  may include, without limitation, a Level 1 (“L1”) internal cache memory (“cache”)  1104 . In at least one embodiment, processor  1102  may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor  1102 . In at least one embodiment, processor  1102  may also include a combination of both internal and external caches. In at least one embodiment, a register file  1106  may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and instruction pointer register. 
     In at least one embodiment, execution unit  1108 , including, without limitation, logic to perform integer and floating point operations, also resides in processor  1102 . Processor  1102  may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit  1108  may include logic to handle a packed instruction set  1109 . In at least one embodiment, by including packed instruction set  1109  in an instruction set of a general-purpose processor  1102 , along with associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in a general-purpose processor  1102 . In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using full width of a processor&#39;s data bus for performing operations on packed data, which may eliminate a need to transfer smaller units of data across a processor&#39;s data bus to perform one or more operations one data element at a time. 
     In at least one embodiment, execution unit  1108  may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system  1100  may include, without limitation, a memory  1120 . In at least one embodiment, memory  1120  may be implemented as a DRAM device, an SRAM device, flash memory device, or other memory device. Memory  1120  may store instruction(s)  1119  and/or data  1121  represented by data signals that may be executed by processor  1102 . 
     In at least one embodiment, a system logic chip may be coupled to processor bus  1110  and memory  1120 . In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”)  1116 , and processor  1102  may communicate with MCH  1116  via processor bus  1110 . In at least one embodiment, MCH  1116  may provide a high bandwidth memory path  1118  to memory  1120  for instruction and data storage and for storage of graphics commands, data and textures. In at least one embodiment, MCH  1116  may direct data signals between processor  1102 , memory  1120 , and other components in computer system  1100  and to bridge data signals between processor bus  1110 , memory  1120 , and a system I/O  1122 . In at least one embodiment, system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH  1116  may be coupled to memory  1120  through high bandwidth memory path  1118  and graphics/video card  1112  may be coupled to MCH  1116  through an Accelerated Graphics Port (“AGP”) interconnect  1114 . 
     In at least one embodiment, computer system  1100  may use system I/O  1122  that is a proprietary hub interface bus to couple MCH  1116  to I/O controller hub (“ICH”)  1130 . In at least one embodiment, ICH  1130  may provide direct connections to some I/O devices via a local I/O bus. In at least one embodiment, local I/O bus may include, without limitation, a high-speed I/O bus for connecting peripherals to memory  1120 , a chipset, and processor  1102 . Examples may include, without limitation, an audio controller  1129 , a firmware hub (“flash BIOS”)  1128 , a wireless transceiver  1126 , a data storage  1124 , a legacy I/O controller  1123  containing a user input interface  1125  and a keyboard interface, a serial expansion port  1127 , such as a USB, and a network controller  1134 . Data storage  1124  may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device. 
     In at least one embodiment,  FIG. 11  illustrates a system, which includes interconnected hardware devices or “chips.” In at least one embodiment,  FIG. 11  may illustrate an exemplary SoC. In at least one embodiment, devices illustrated in  FIG. 11  may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system  1100  are interconnected using compute express link (“CXL”) interconnects. 
       FIG. 12  illustrates a system  1200 , in accordance with at least one embodiment. In at least one embodiment, system  1200  is an electronic device that utilizes a processor  1210 . In at least one embodiment, system  1200  may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more on-premise or cloud service providers, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device. 
     In at least one embodiment, system  1200  may include, without limitation, processor  1210  communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor  1210  is coupled using a bus or interface, such as an I 2 C bus, a System Management Bus (“SMBus”), a Low Pin Count (“LPC”) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a USB (versions 1, 2, 3), or a Universal Asynchronous Receiver/Transmitter (“UART”) bus. In at least one embodiment,  FIG. 12  illustrates a system which includes interconnected hardware devices or “chips.” In at least one embodiment,  FIG. 12  may illustrate an exemplary SoC. In at least one embodiment, devices illustrated in  FIG. 12  may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of  FIG. 12  are interconnected using CXL interconnects. 
     In at least one embodiment,  FIG. 12  may include a display  1224 , a touch screen  1225 , a touch pad  1230 , a Near Field Communications unit (“NFC”)  1245 , a sensor hub  1240 , a thermal sensor  1246 , an Express Chipset (“EC”)  1235 , a Trusted Platform Module (“TPM”)  1238 , BIOS/firmware/flash memory (“BIOS, FW Flash”)  1222 , a DSP  1260 , a Solid State Disk (“SSD”) or Hard Disk Drive (“HDD”)  1220 , a wireless local area network unit (“WLAN”)  1250 , a Bluetooth unit  1252 , a Wireless Wide Area Network unit (“WWAN”)  1256 , a Global Positioning System (“GPS”)  1255 , a camera (“USB 3.0 camera”)  1254  such as a USB 3.0 camera, or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”)  1215  implemented in, for example, LPDDR3 standard. These components may each be implemented in any suitable manner. 
     In at least one embodiment, other components may be communicatively coupled to processor  1210  through components discussed above. In at least one embodiment, an accelerometer  1241 , an Ambient Light Sensor (“ALS”)  1242 , a compass  1243 , and a gyroscope  1244  may be communicatively coupled to sensor hub  1240 . In at least one embodiment, a thermal sensor  1239 , a fan  1237 , a keyboard  1236 , and a touch pad  1230  may be communicatively coupled to EC  1235 . In at least one embodiment, a speaker  1263 , a headphones  1264 , and a microphone (“mic”)  1265  may be communicatively coupled to an audio unit (“audio codec and class d amp”)  1262 , which may in turn be communicatively coupled to DSP  1260 . In at least one embodiment, audio unit  1262  may include, for example and without limitation, an audio coder/decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”)  1257  may be communicatively coupled to WWAN unit  1256 . In at least one embodiment, components such as WLAN unit  1250  and Bluetooth unit  1252 , as well as WWAN unit  1256  may be implemented in a Next Generation Form Factor (“NGFF”). 
       FIG. 13  illustrates an exemplary integrated circuit  1300 , in accordance with at least one embodiment. In at least one embodiment, exemplary integrated circuit  1300  is a SoC that may be fabricated using one or more IP cores. In at least one embodiment, integrated circuit  1300  includes one or more application processor(s)  1305  (e.g., CPUs, DPUs), at least one graphics processor  1310 , and may additionally include an image processor  1315  and/or a video processor  1320 , any of which may be a modular IP core. In at least one embodiment, integrated circuit  1300  includes peripheral or bus logic including a USB controller  1325 , a UART controller  1330 , an SPI/SDIO controller  1335 , and an I 2 S/I 2 C controller  1340 . In at least one embodiment, integrated circuit  1300  can include a display device  1345  coupled to one or more of a high-definition multimedia interface (“HDMI”) controller  1350  and a mobile industry processor interface (“MIPI”) display interface  1355 . In at least one embodiment, storage may be provided by a flash memory subsystem  1360  including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller  1365  for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine  1370 . 
       FIG. 14  illustrates a computing system  1400 , according to at least one embodiment; In at least one embodiment, computing system  1400  includes a processing subsystem  1401  having one or more processor(s)  1402  and a system memory  1404  communicating via an interconnection path that may include a memory hub  1405 . In at least one embodiment, memory hub  1405  may be a separate component within a chipset component or may be integrated within one or more processor(s)  1402 . In at least one embodiment, memory hub  1405  couples with an I/O subsystem  1411  via a communication link  1406 . In at least one embodiment, I/O subsystem  1411  includes an I/O hub  1407  that can enable computing system  1400  to receive input from one or more input device(s)  1408 . In at least one embodiment, I/O hub  1407  can enable a display controller, which may be included in one or more processor(s)  1402 , to provide outputs to one or more display device(s)  1410 A. In at least one embodiment, one or more display device(s)  1410 A coupled with I/O hub  1407  can include a local, internal, or embedded display device. 
     In at least one embodiment, processing subsystem  1401  includes one or more parallel processor(s)  1412  coupled to memory hub  1405  via a bus or other communication link  1413 . In at least one embodiment, communication link  1413  may be one of any number of standards based communication link technologies or protocols, such as, but not limited to PCIe, or may be a vendor specific communications interface or communications fabric. In at least one embodiment, one or more parallel processor(s)  1412  form a computationally focused parallel or vector processing system that can include a large number of processing cores and/or processing clusters, such as a many integrated core processor. In at least one embodiment, one or more parallel processor(s)  1412  form a graphics processing subsystem that can output pixels to one of one or more display device(s)  1410 A coupled via I/O Hub  1407 . In at least one embodiment, one or more parallel processor(s)  1412  can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s)  1410 B. 
     In at least one embodiment, a system storage unit  1414  can connect to I/O hub  1407  to provide a storage mechanism for computing system  1400 . In at least one embodiment, an I/O switch  1416  can be used to provide an interface mechanism to enable connections between I/O hub  1407  and other components, such as a network adapter  1418  and/or wireless network adapter  1419  that may be integrated into a platform, and various other devices that can be added via one or more add-in device(s)  1420 . In at least one embodiment, network adapter  1418  can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter  1419  can include one or more of a Wi-Fi, Bluetooth, NFC, or other network device that includes one or more wireless radios. 
     In at least one embodiment, computing system  1400  can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, that may also be connected to I/O hub  1407 . In at least one embodiment, communication paths interconnecting various components in  FIG. 14  may be implemented using any suitable protocols, such as PCI based protocols (e.g., PCIe), or other bus or point-to-point communication interfaces and/or protocol(s), such as NVLink high-speed interconnect, or interconnect protocols. 
     In at least one embodiment, one or more parallel processor(s)  1412  incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (“GPU”). In at least one embodiment, one or more parallel processor(s)  1412  incorporate circuitry optimized for general purpose processing. In at least embodiment, components of computing system  1400  may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processor(s)  1412 , memory hub  1405 , processor(s)  1402 , and I/O hub  1407  can be integrated into a SoC integrated circuit. In at least one embodiment, components of computing system  1400  can be integrated into a single package to form a system in package (“SIP”) configuration. In at least one embodiment, at least a portion of the components of computing system  1400  can be integrated into a multi-chip module (“MCM”), which can be interconnected with other multi-chip modules into a modular computing system. In at least one embodiment, I/O subsystem  1411  and display devices  1410 B are omitted from computing system  1400 . 
     Processing Systems 
     The following figures set forth, without limitation, exemplary processing systems that can be used to implement at least one embodiment. 
       FIG. 15  illustrates an accelerated processing unit (“APU”)  1500 , in accordance with at least one embodiment. In at least one embodiment, APU  1500  is developed by AMD Corporation of Santa Clara, Calif. In at least one embodiment, APU  1500  can be configured to execute an application program, such as a CUDA program. In at least one embodiment, APU  1500  includes, without limitation, a core complex  1510 , a graphics complex  1540 , fabric  1560 , I/O interfaces  1570 , memory controllers  1580 , a display controller  1592 , and a multimedia engine  1594 . In at least one embodiment, APU  1500  may include, without limitation, any number of core complexes  1510 , any number of graphics complexes  1550 , any number of display controllers  1592 , and any number of multimedia engines  1594  in any combination. For explanatory purposes, multiple instances of like objects are denoted herein with reference numbers identifying the object and parenthetical numbers identifying the instance where needed. 
     In at least one embodiment, core complex  1510  is a CPU, graphics complex  1540  is a GPU, and APU  1500  is a processing unit that integrates, without limitation,  1510  and  1540  onto a single chip. In at least one embodiment, some tasks may be assigned to core complex  1510  and other tasks may be assigned to graphics complex  1540 . In at least one embodiment, core complex  1510  is configured to execute main control software associated with APU  1500 , such as an operating system. In at least one embodiment, core complex  1510  is the master processor of APU  1500 , controlling and coordinating operations of other processors. In at least one embodiment, core complex  1510  issues commands that control the operation of graphics complex  1540 . In at least one embodiment, core complex  1510  can be configured to execute host executable code derived from CUDA source code, and graphics complex  1540  can be configured to execute device executable code derived from CUDA source code. 
     In at least one embodiment, core complex  1510  includes, without limitation, cores  1520 ( 1 )- 1520 ( 4 ) and an L3 cache  1530 . In at least one embodiment, core complex  1510  may include, without limitation, any number of cores  1520  and any number and type of caches in any combination. In at least one embodiment, cores  1520  are configured to execute instructions of a particular instruction set architecture (“ISA”). In at least one embodiment, each core  1520  is a CPU core. 
     In at least one embodiment, each core  1520  includes, without limitation, a fetch/decode unit  1522 , an integer execution engine  1524 , a floating point execution engine  1526 , and an L2 cache  1528 . In at least one embodiment, fetch/decode unit  1522  fetches instructions, decodes such instructions, generates micro-operations, and dispatches separate micro-instructions to integer execution engine  1524  and floating point execution engine  1526 . In at least one embodiment, fetch/decode unit  1522  can concurrently dispatch one micro-instruction to integer execution engine  1524  and another micro-instruction to floating point execution engine  1526 . In at least one embodiment, integer execution engine  1524  executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine  1526  executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit  1522  dispatches micro-instructions to a single execution engine that replaces both integer execution engine  1524  and floating point execution engine  1526 . 
     In at least one embodiment, each core  1520 ( i ), where i is an integer representing a particular instance of core  1520 , may access L2 cache  1528 ( i ) included in core  1520 ( i ). In at least one embodiment, each core  1520  included in core complex  1510 ( j ), where j is an integer representing a particular instance of core complex  1510 , is connected to other cores  1520  included in core complex  1510 ( j ) via L3 cache  1530 ( j ) included in core complex  1510 ( j ). In at least one embodiment, cores  1520  included in core complex  1510 ( j ), where j is an integer representing a particular instance of core complex  1510 , can access all of L3 cache  1530 ( j ) included in core complex  1510 ( j ). In at least one embodiment, L3 cache  1530  may include, without limitation, any number of slices. 
     In at least one embodiment, graphics complex  1540  can be configured to perform compute operations in a highly-parallel fashion. In at least one embodiment, graphics complex  1540  is configured to execute graphics pipeline operations such as draw commands, pixel operations, geometric computations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex  1540  is configured to execute operations unrelated to graphics. In at least one embodiment, graphics complex  1540  is configured to execute both operations related to graphics and operations unrelated to graphics. 
     In at least one embodiment, graphics complex  1540  includes, without limitation, any number of compute units  1550  and an L2 cache  1542 . In at least one embodiment, compute units  1550  share L2 cache  1542 . In at least one embodiment, L2 cache  1542  is partitioned. In at least one embodiment, graphics complex  1540  includes, without limitation, any number of compute units  1550  and any number (including zero) and type of caches. In at least one embodiment, graphics complex  1540  includes, without limitation, any amount of dedicated graphics hardware. 
     In at least one embodiment, each compute unit  1550  includes, without limitation, any number of SIMD units  1552  and a shared memory  1554 . In at least one embodiment, each SIMD unit  1552  implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each compute unit  1550  may execute any number of thread blocks, but each thread block executes on a single compute unit  1550 . In at least one embodiment, a thread block includes, without limitation, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit  1552  executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize together and communicate via shared memory  1554 . 
     In at least one embodiment, fabric  1560  is a system interconnect that facilitates data and control transmissions across core complex  1510 , graphics complex  1540 , I/O interfaces  1570 , memory controllers  1580 , display controller  1592 , and multimedia engine  1594 . In at least one embodiment, APU  1500  may include, without limitation, any amount and type of system interconnect in addition to or instead of fabric  1560  that facilitates data and control transmissions across any number and type of directly or indirectly linked components that may be internal or external to APU  1500 . In at least one embodiment, I/O interfaces  1570  are representative of any number and type of I/O interfaces (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I/O interfaces  1570  In at least one embodiment, peripheral devices that are coupled to I/O interfaces  1570  may include, without limitation, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, and so forth. 
     In at least one embodiment, display controller AMD92 displays images on one or more display device(s), such as a liquid crystal display (“LCD”) device. In at least one embodiment, multimedia engine  240  includes, without limitation, any amount and type of circuitry that is related to multimedia, such as a video decoder, a video encoder, an image signal processor, etc. In at least one embodiment, memory controllers  1580  facilitate data transfers between APU  1500  and a unified system memory  1590 . In at least one embodiment, core complex  1510  and graphics complex  1540  share unified system memory  1590 . 
     In at least one embodiment, APU  1500  implements a memory subsystem that includes, without limitation, any amount and type of memory controllers  1580  and memory devices (e.g., shared memory  1554 ) that may be dedicated to one component or shared among multiple components. In at least one embodiment, APU  1500  implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 caches  1628 , L3 cache  1530 , and L2 cache  1542 ) that may each be private to or shared between any number of components (e.g., cores  1520 , core complex  1510 , SIMD units  1552 , compute units  1550 , and graphics complex  1540 ). 
       FIG. 16  illustrates a CPU  1600 , in accordance with at least one embodiment. In at least one embodiment, CPU  1600  is developed by AMD Corporation of Santa Clara, Calif. In at least one embodiment, CPU  1600  can be configured to execute an application program. In at least one embodiment, CPU  1600  is configured to execute main control software, such as an operating system. In at least one embodiment, CPU  1600  issues commands that control the operation of an external GPU (not shown). In at least one embodiment, CPU  1600  can be configured to execute host executable code derived from CUDA source code, and an external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, CPU  1600  includes, without limitation, any number of core complexes  1610 , fabric  1660 , I/O interfaces  1670 , and memory controllers  1680 . 
     In at least one embodiment, core complex  1610  includes, without limitation, cores  1620 ( 1 )- 1620 ( 4 ) and an L3 cache  1630 . In at least one embodiment, core complex  1610  may include, without limitation, any number of cores  1620  and any number and type of caches in any combination. In at least one embodiment, cores  1620  are configured to execute instructions of a particular ISA. In at least one embodiment, each core  1620  is a CPU core. 
     In at least one embodiment, each core  1620  includes, without limitation, a fetch/decode unit  1622 , an integer execution engine  1624 , a floating point execution engine  1626 , and an L2 cache  1628 . In at least one embodiment, fetch/decode unit  1622  fetches instructions, decodes such instructions, generates micro-operations, and dispatches separate micro-instructions to integer execution engine  1624  and floating point execution engine  1626 . In at least one embodiment, fetch/decode unit  1622  can concurrently dispatch one micro-instruction to integer execution engine  1624  and another micro-instruction to floating point execution engine  1626 . In at least one embodiment, integer execution engine  1624  executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine  1626  executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit  1622  dispatches micro-instructions to a single execution engine that replaces both integer execution engine  1624  and floating point execution engine  1626 . 
     In at least one embodiment, each core  1620 ( i ), where i is an integer representing a particular instance of core  1620 , may access L2 cache  1628 ( i ) included in core  1620 ( i ). In at least one embodiment, each core  1620  included in core complex  1610 ( j ), where j is an integer representing a particular instance of core complex  1610 , is connected to other cores  1620  in core complex  1610 ( j ) via L3 cache  1630 ( j ) included in core complex  1610 ( j ). In at least one embodiment, cores  1620  included in core complex  1610 ( j ), where j is an integer representing a particular instance of core complex  1610 , can access all of L3 cache  1630 ( j ) included in core complex  1610 ( j ). In at least one embodiment, L3 cache  1630  may include, without limitation, any number of slices. 
     In at least one embodiment, fabric  1660  is a system interconnect that facilitates data and control transmissions across core complexes  1610 ( 1 )- 1610 (N) (where N is an integer greater than zero), I/O interfaces  1670 , and memory controllers  1680 . In at least one embodiment, CPU  1600  may include, without limitation, any amount and type of system interconnect in addition to or instead of fabric  1660  that facilitates data and control transmissions across any number and type of directly or indirectly linked components that may be internal or external to CPU  1600 . In at least one embodiment, I/O interfaces  1670  are representative of any number and type of I/O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I/O interfaces  1670  In at least one embodiment, peripheral devices that are coupled to I/O interfaces  1670  may include, without limitation, displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, and so forth. 
     In at least one embodiment, memory controllers  1680  facilitate data transfers between CPU  1600  and a system memory  1690 . In at least one embodiment, core complex  1610  and graphics complex  1640  share system memory  1690 . In at least one embodiment, CPU  1600  implements a memory subsystem that includes, without limitation, any amount and type of memory controllers  1680  and memory devices that may be dedicated to one component or shared among multiple components. In at least one embodiment, CPU  1600  implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 caches  1628  and L3 caches  1630 ) that may each be private to or shared between any number of components (e.g., cores  1620  and core complexes  1610 ). 
       FIG. 17  illustrates an exemplary accelerator integration slice  1790 , in accordance with at least one embodiment. As used herein, a “slice” comprises a specified portion of processing resources of an accelerator integration circuit. In at least one embodiment, the accelerator integration circuit provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines included in a graphics acceleration module. The graphics processing engines may each comprise a separate GPU. Alternatively, the graphics processing engines may comprise different types of graphics processing engines within a GPU such as graphics execution units, media processing engines (e.g., video encoders/decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module may be a GPU with multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip. 
     An application effective address space  1782  within system memory  1714  stores process elements  1783 . In one embodiment, process elements  1783  are stored in response to GPU invocations  1781  from applications  1780  executed on processor  1707 . A process element  1783  contains process state for corresponding application  1780 . A work descriptor (“WD”)  1784  contained in process element  1783  can be a single job requested by an application or may contain a pointer to a queue of jobs. In at least one embodiment, WD  1784  is a pointer to a job request queue in application effective address space  1782 . 
     Graphics acceleration module  1746  and/or individual graphics processing engines can be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for setting up process state and sending WD  1784  to graphics acceleration module  1746  to start a job in a virtualized environment may be included. 
     In at least one embodiment, a dedicated-process programming model is implementation-specific. In this model, a single process owns graphics acceleration module  1746  or an individual graphics processing engine. Because graphics acceleration module  1746  is owned by a single process, a hypervisor initializes an accelerator integration circuit for an owning partition and an operating system initializes accelerator integration circuit for an owning process when graphics acceleration module  1746  is assigned. 
     In operation, a WD fetch unit  1791  in accelerator integration slice  1790  fetches next WD  1784  which includes an indication of work to be done by one or more graphics processing engines of graphics acceleration module  1746 . Data from WD  1784  may be stored in registers  1745  and used by a memory management unit (“MMU”)  1739 , interrupt management circuit  1747  and/or context management circuit  1748  as illustrated. For example, one embodiment of MMU  1739  includes segment/page walk circuitry for accessing segment/page tables  1786  within OS virtual address space  1785 . Interrupt management circuit  1747  may process interrupt events (“INT”)  1792  received from graphics acceleration module  1746 . When performing graphics operations, an effective address  1793  generated by a graphics processing engine is translated to a real address by MMU  1739 . 
     In one embodiment, a same set of registers  1745  are duplicated for each graphics processing engine and/or graphics acceleration module  1746  and may be initialized by a hypervisor or operating system. Each of these duplicated registers may be included in accelerator integration slice  1790 . Exemplary registers that may be initialized by a hypervisor are shown in Table 1. 
     
       
         
           
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 Hypervisor Initialized Registers 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
            
               
                 1 
                 Slice Control Register 
               
               
                 2 
                 Real Address (RA) Scheduled Processes Area Pointer 
               
               
                 3 
                 Authority Mask Override Register 
               
               
                 4 
                 Interrupt Vector Table Entry Offset 
               
               
                 5 
                 Interrupt Vector Table Entry Limit 
               
               
                 6 
                 State Register 
               
               
                 7 
                 Logical Partition ID 
               
               
                 8 
                 Real address (RA) Hypervisor Accelerator Utilization Record Pointer 
               
               
                 9 
                 Storage Description Register 
               
               
                   
               
            
           
         
       
     
     Exemplary registers that may be initialized by an operating system are shown in Table 2. 
     
       
         
           
               
             
               
                 TABLE 2 
               
               
                   
               
               
                 Operating System Initialized Registers 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
            
               
                 1 
                 Process and Thread Identification 
               
               
                 2 
                 Effective Address (EA) Context Save/Restore Pointer 
               
               
                 3 
                 Virtual Address (VA) Accelerator Utilization Record Pointer 
               
               
                 4 
                 Virtual Address (VA) Storage Segment Table Pointer 
               
               
                 5 
                 Authority Mask 
               
               
                 6 
                 Work descriptor 
               
               
                   
               
            
           
         
       
     
     In one embodiment, each WD  1784  is specific to a particular graphics acceleration module  1746  and/or a particular graphics processing engine. It contains all information required by a graphics processing engine to do work or it can be a pointer to a memory location where an application has set up a command queue of work to be completed. 
       FIGS. 18A and 18B  illustrate exemplary graphics processors, in accordance with at least one embodiment. In at least one embodiment, any of the exemplary graphics processors may be fabricated using one or more IP cores. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processors are for use within a SoC. 
       FIG. 18A  illustrates an exemplary graphics processor  1810  of a SoC integrated circuit that may be fabricated using one or more IP cores, in accordance with at least one embodiment.  FIG. 18B  illustrates an additional exemplary graphics processor  1840  of a SoC integrated circuit that may be fabricated using one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, graphics processor  1810  of  FIG. 18A  is a low power graphics processor core. In at least one embodiment, graphics processor  1840  of  FIG. 18B  is a higher performance graphics processor core. In at least one embodiment, each of graphics processors  1810 ,  1840  can be variants of graphics processor  1310  of  FIG. 13 . 
     In at least one embodiment, graphics processor  1810  includes a vertex processor  1805  and one or more fragment processor(s)  1815 A- 1815 N (e.g.,  1815 A,  1815 B,  1815 C,  1815 D, through  1815 N- 1 , and  1815 N). In at least one embodiment, graphics processor  1810  can execute different shader programs via separate logic, such that vertex processor  1805  is optimized to execute operations for vertex shader programs, while one or more fragment processor(s)  1815 A- 1815 N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor  1805  performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s)  1815 A- 1815 N use primitive and vertex data generated by vertex processor  1805  to produce a framebuffer that is displayed on a display device. In at least one embodiment, fragment processor(s)  1815 A- 1815 N are optimized to execute fragment shader programs as provided for in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in a Direct 3D API. 
     In at least one embodiment, graphics processor  1810  additionally includes one or more MMU(s)  1820 A- 1820 B, cache(s)  1825 A- 1825 B, and circuit interconnect(s)  1830 A- 1830 B. In at least one embodiment, one or more MMU(s)  1820 A- 1820 B provide for virtual to physical address mapping for graphics processor  1810 , including for vertex processor  1805  and/or fragment processor(s)  1815 A- 1815 N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in one or more cache(s)  1825 A- 1825 B. In at least one embodiment, one or more MMU(s)  1820 A- 1820 B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processor(s)  1305 , image processors  1315 , and/or video processors  1320  of  FIG. 13 , such that each processor  1305 - 1320  can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnect(s)  1830 A- 1830 B enable graphics processor  1810  to interface with other IP cores within a SoC, either via an internal bus of the SoC or via a direct connection. 
     In at least one embodiment, graphics processor  1840  includes one or more MMU(s)  1820 A- 1820 B, caches  1825 A- 1825 B, and circuit interconnects  1830 A- 1830 B of graphics processor  1810  of  FIG. 18A . In at least one embodiment, graphics processor  1840  includes one or more shader core(s)  1855 A- 1855 N (e.g.,  1855 A,  1855 B,  1855 C,  1855 D,  1855 E,  1855 F, through  1855 N- 1 , and  1855 N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. In at least one embodiment, a number of shader cores can vary. In at least one embodiment, graphics processor  1840  includes an inter-core task manager  1845 , which acts as a thread dispatcher to dispatch execution threads to one or more shader cores  1855 A- 1855 N and a tiling unit  1858  to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches. 
       FIG. 19A  illustrates a graphics core  1900 , in accordance with at least one embodiment. In at least one embodiment, graphics core  1900  may be included within graphics processor  1310  of  FIG. 13 . In at least one embodiment, graphics core  1900  may be a unified shader core  1855 A- 1855 N as in  FIG. 18B . In at least one embodiment, graphics core  1900  includes a shared instruction cache  1902 , a texture unit  1918 , and a cache/shared memory  1920  that are common to execution resources within graphics core  1900 . In at least one embodiment, graphics core  1900  can include multiple slices  1901 A- 1901 N or partition for each core, and a graphics processor can include multiple instances of graphics core  1900 . Slices  1901 A- 1901 N can include support logic including a local instruction cache  1904 A- 1904 N, a thread scheduler  1906 A- 1906 N, a thread dispatcher  1908 A- 1908 N, and a set of registers  1910 A- 1910 N. In at least one embodiment, slices  1901 A- 1901 N can include a set of additional function units (“AFUs”)  1912 A- 1912 N, floating-point units (“FPUs”)  1914 A- 1914 N, integer arithmetic logic units (“ALUs”)  1916 - 1916 N, address computational units (“ACUs”)  1913 A- 1913 N, double-precision floating-point units (“DPFPUs”)  1915 A- 1915 N, and matrix processing units (“MPUs”)  1917 A- 1917 N. 
     In at least one embodiment, FPUs  1914 A- 1914 N can perform single-precision (32-bit) and half-precision (16-bit) floating point operations, while DPFPUs  1915 A- 1915 N perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs  1916 A- 1916 N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs  1917 A- 1917 N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. In at least one embodiment, MPUs  1917 - 1917 N can perform a variety of matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix to matrix multiplication (“GEMM”). In at least one embodiment, AFUs  1912 A- 1912 N can perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.). 
       FIG. 19B  illustrates a general-purpose graphics processing unit (“GPGPU”)  1930 , in accordance with at least one embodiment. In at least one embodiment, GPGPU  1930  is highly-parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU  1930  can be configured to enable highly-parallel compute operations to be performed by an array of GPUs. In at least one embodiment, GPGPU  1930  can be linked directly to other instances of GPGPU  1930  to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU  1930  includes a host interface  1932  to enable a connection with a host processor. In at least one embodiment, host interface  1932  is a PCIe interface. In at least one embodiment, host interface  1932  can be a vendor specific communications interface or communications fabric. In at least one embodiment, GPGPU  1930  receives commands from a host processor and uses a global scheduler  1934  to distribute execution threads associated with those commands to a set of compute clusters  1936 A- 1936 H. In at least one embodiment, compute clusters  1936 A- 1936 H share a cache memory  1938 . In at least one embodiment, cache memory  1938  can serve as a higher-level cache for cache memories within compute clusters  1936 A- 1936 H. 
     In at least one embodiment, GPGPU  1930  includes memory  1944 A- 1944 B coupled with compute clusters  1936 A- 1936 H via a set of memory controllers  1942 A- 1942 B. In at least one embodiment, memory  1944 A- 1944 B can include various types of memory devices including DRAM or graphics random access memory, such as synchronous graphics random access memory (“SGRAM”), including graphics double data rate (“GDDR”) memory. 
     In at least one embodiment, compute clusters  1936 A- 1936 H each include a set of graphics cores, such as graphics core  1900  of  FIG. 19A , which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for computations associated with CUDA programs. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters  1936 A- 1936 H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations. 
     In at least one embodiment, multiple instances of GPGPU  1930  can be configured to operate as a compute cluster. Compute clusters  1936 A- 1936 H may implement any technically feasible communication techniques for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU  1930  communicate over host interface  1932 . In at least one embodiment, GPGPU  1930  includes an I/O hub  1939  that couples GPGPU  1930  with a GPU link  1940  that enables a direct connection to other instances of GPGPU  1930 . In at least one embodiment, GPU link  1940  is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU  1930 . In at least one embodiment GPU link  1940  couples with a high speed interconnect to transmit and receive data to other GPGPUs  1930  or parallel processors. In at least one embodiment, multiple instances of GPGPU  1930  are located in separate data processing systems and communicate via a network device that is accessible via host interface  1932 . In at least one embodiment GPU link  1940  can be configured to enable a connection to a host processor in addition to or as an alternative to host interface  1932 . In at least one embodiment, GPGPU  1930  can be configured to execute a CUDA program. 
       FIG. 20A  illustrates a parallel processor  2000 , in accordance with at least one embodiment. In at least one embodiment, various components of parallel processor  2000  may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (“ASICs”), or FPGAs. 
     In at least one embodiment, parallel processor  2000  includes a parallel processing unit  2002 . In at least one embodiment, parallel processing unit  2002  includes an I/O unit  2004  that enables communication with other devices, including other instances of parallel processing unit  2002 . In at least one embodiment, I/O unit  2004  may be directly connected to other devices. In at least one embodiment, I/O unit  2004  connects with other devices via use of a hub or switch interface, such as memory hub  2005 . In at least one embodiment, connections between memory hub  2005  and I/O unit  2004  form a communication link. In at least one embodiment, I/O unit  2004  connects with a host interface  2006  and a memory crossbar  2016 , where host interface  2006  receives commands directed to performing processing operations and memory crossbar  2016  receives commands directed to performing memory operations. 
     In at least one embodiment, when host interface  2006  receives a command buffer via I/O unit  2004 , host interface  2006  can direct work operations to perform those commands to a front end  2008 . In at least one embodiment, front end  2008  couples with a scheduler  2010 , which is configured to distribute commands or other work items to a processing array  2012 . In at least one embodiment, scheduler  2010  ensures that processing array  2012  is properly configured and in a valid state before tasks are distributed to processing array  2012 . In at least one embodiment, scheduler  2010  is implemented via firmware logic executing on a microcontroller. In at least one embodiment, microcontroller implemented scheduler  2010  is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on processing array  2012 . In at least one embodiment, host software can prove workloads for scheduling on processing array  2012  via one of multiple graphics processing doorbells. In at least one embodiment, workloads can then be automatically distributed across processing array  2012  by scheduler  2010  logic within a microcontroller including scheduler  2010 . 
     In at least one embodiment, processing array  2012  can include up to “N” clusters (e.g., cluster  2014 A, cluster  2014 B, through cluster  2014 N). In at least one embodiment, each cluster  2014 A- 2014 N of processing array  2012  can execute a large number of concurrent threads. In at least one embodiment, scheduler  2010  can allocate work to clusters  2014 A- 2014 N of processing array  2012  using various scheduling and/or work distribution algorithms, which may vary depending on the workload arising for each type of program or computation. In at least one embodiment, scheduling can be handled dynamically by scheduler  2010 , or can be assisted in part by compiler logic during compilation of program logic configured for execution by processing array  2012 . In at least one embodiment, different clusters  2014 A- 2014 N of processing array  2012  can be allocated for processing different types of programs or for performing different types of computations. 
     In at least one embodiment, processing array  2012  can be configured to perform various types of parallel processing operations. In at least one embodiment, processing array  2012  is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing array  2012  can include logic to execute processing tasks including filtering of video and/or audio data, performing modeling operations, including physics operations, and performing data transformations. 
     In at least one embodiment, processing array  2012  is configured to perform parallel graphics processing operations. In at least one embodiment, processing array  2012  can include additional logic to support execution of such graphics processing operations, including, but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing array  2012  can be configured to execute graphics processing related shader programs such as, but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit  2002  can transfer data from system memory via I/O unit  2004  for processing. In at least one embodiment, during processing, transferred data can be stored to on-chip memory (e.g., a parallel processor memory  2022 ) during processing, then written back to system memory. 
     In at least one embodiment, when parallel processing unit  2002  is used to perform graphics processing, scheduler  2010  can be configured to divide a processing workload into approximately equal sized tasks, to better enable distribution of graphics processing operations to multiple clusters  2014 A- 2014 N of processing array  2012 . In at least one embodiment, portions of processing array  2012  can be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. In at least one embodiment, intermediate data produced by one or more of clusters  2014 A- 2014 N may be stored in buffers to allow intermediate data to be transmitted between clusters  2014 A- 2014 N for further processing. 
     In at least one embodiment, processing array  2012  can receive processing tasks to be executed via scheduler  2010 , which receives commands defining processing tasks from front end  2008 . In at least one embodiment, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and/or pixel data, as well as state parameters and commands defining how data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler  2010  may be configured to fetch indices corresponding to tasks or may receive indices from front end  2008 . In at least one embodiment, front end  2008  can be configured to ensure processing array  2012  is configured to a valid state before a workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated. 
     In at least one embodiment, each of one or more instances of parallel processing unit  2002  can couple with parallel processor memory  2022 . In at least one embodiment, parallel processor memory  2022  can be accessed via memory crossbar  2016 , which can receive memory requests from processing array  2012  as well as I/O unit  2004 . In at least one embodiment, memory crossbar  2016  can access parallel processor memory  2022  via a memory interface  2018 . In at least one embodiment, memory interface  2018  can include multiple partition units (e.g., a partition unit  2020 A, partition unit  2020 B, through partition unit  2020 N) that can each couple to a portion (e.g., memory unit) of parallel processor memory  2022 . In at least one embodiment, a number of partition units  2020 A- 2020 N is configured to be equal to a number of memory units, such that a first partition unit  2020 A has a corresponding first memory unit  2024 A, a second partition unit  2020 B has a corresponding memory unit  2024 B, and an Nth partition unit  2020 N has a corresponding Nth memory unit  2024 N. In at least one embodiment, a number of partition units  2020 A- 2020 N may not be equal to a number of memory devices. 
     In at least one embodiment, memory units  2024 A- 2024 N can include various types of memory devices, including DRAM or graphics random access memory, such as SGRAM, including GDDR memory. In at least one embodiment, memory units  2024 A- 2024 N may also include 3D stacked memory, including but not limited to high bandwidth memory (“HBM”). In at least one embodiment, render targets, such as frame buffers or texture maps may be stored across memory units  2024 A- 2024 N, allowing partition units  2020 A- 2020 N to write portions of each render target in parallel to efficiently use available bandwidth of parallel processor memory  2022 . In at least one embodiment, a local instance of parallel processor memory  2022  may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory. 
     In at least one embodiment, any one of clusters  2014 A- 2014 N of processing array  2012  can process data that will be written to any of memory units  2024 A- 2024 N within parallel processor memory  2022 . In at least one embodiment, memory crossbar  2016  can be configured to transfer an output of each cluster  2014 A- 2014 N to any partition unit  2020 A- 2020 N or to another cluster  2014 A- 2014 N, which can perform additional processing operations on an output. In at least one embodiment, each cluster  2014 A- 2014 N can communicate with memory interface  2018  through memory crossbar  2016  to read from or write to various external memory devices. In at least one embodiment, memory crossbar  2016  has a connection to memory interface  2018  to communicate with I/O unit  2004 , as well as a connection to a local instance of parallel processor memory  2022 , enabling processing units within different clusters  2014 A- 2014 N to communicate with system memory or other memory that is not local to parallel processing unit  2002 . In at least one embodiment, memory crossbar  2016  can use virtual channels to separate traffic streams between clusters  2014 A- 2014 N and partition units  2020 A- 2020 N. 
     In at least one embodiment, multiple instances of parallel processing unit  2002  can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit  2002  can be configured to inter-operate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and/or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit  2002  can include higher precision floating point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit  2002  or parallel processor  2000  can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and/or embedded systems. 
       FIG. 20B  illustrates a processing cluster  2094 , in accordance with at least one embodiment. In at least one embodiment, processing cluster  2094  is included within a parallel processing unit. In at least one embodiment, processing cluster  2094  is one of processing clusters  2014 A- 2014 N of  FIG. 20 . In at least one embodiment, processing cluster  2094  can be configured to execute many threads in parallel, where the term “thread” refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single instruction, multiple data (“SIMD”) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction, multiple thread (“SIMT”) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster  2094 . 
     In at least one embodiment, operation of processing cluster  2094  can be controlled via a pipeline manager  2032  that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager  2032  receives instructions from scheduler  2010  of  FIG. 20  and manages execution of those instructions via a graphics multiprocessor  2034  and/or a texture unit  2036 . In at least one embodiment, graphics multiprocessor  2034  is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures may be included within processing cluster  2094 . In at least one embodiment, one or more instances of graphics multiprocessor  2034  can be included within processing cluster  2094 . In at least one embodiment, graphics multiprocessor  2034  can process data and a data crossbar  2040  can be used to distribute processed data to one of multiple possible destinations, including other shader units. In at least one embodiment, pipeline manager  2032  can facilitate distribution of processed data by specifying destinations for processed data to be distributed via data crossbar  2040 . 
     In at least one embodiment, each graphics multiprocessor  2034  within processing cluster  2094  can include an identical set of functional execution logic (e.g., arithmetic logic units, load/store units (“LSUs”), etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. In at least one embodiment, same functional-unit hardware can be leveraged to perform different operations and any combination of functional units may be present. 
     In at least one embodiment, instructions transmitted to processing cluster  2094  constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor  2034 . In at least one embodiment, a thread group may include fewer threads than a number of processing engines within graphics multiprocessor  2034 . In at least one embodiment, when a thread group includes fewer threads than a number of processing engines, one or more of the processing engines may be idle during cycles in which that thread group is being processed. In at least one embodiment, a thread group may also include more threads than a number of processing engines within graphics multiprocessor  2034 . In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor  2034 , processing can be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor  2034 . 
     In at least one embodiment, graphics multiprocessor  2034  includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor  2034  can forego an internal cache and use a cache memory (e.g., L1 cache  2048 ) within processing cluster  2094 . In at least one embodiment, each graphics multiprocessor  2034  also has access to Level 2 (“L2”) caches within partition units (e.g., partition units  2020 A- 2020 N of  FIG. 20A ) that are shared among all processing clusters  2094  and may be used to transfer data between threads. In at least one embodiment, graphics multiprocessor  2034  may also access off-chip global memory, which can include one or more of local parallel processor memory and/or system memory. In at least one embodiment, any memory external to parallel processing unit  2002  may be used as global memory. In at least one embodiment, processing cluster  2094  includes multiple instances of graphics multiprocessor  2034  that can share common instructions and data, which may be stored in L1 cache  2048 . 
     In at least one embodiment, each processing cluster  2094  may include an MMU  2045  that is configured to map virtual addresses into physical addresses. In at least one embodiment, one or more instances of MMU  2045  may reside within memory interface  2018  of  FIG. 20 . In at least one embodiment, MMU  2045  includes a set of page table entries (“PTEs”) used to map a virtual address to a physical address of a tile and optionally a cache line index. In at least one embodiment, MMU  2045  may include address translation lookaside buffers (“TLBs”) or caches that may reside within graphics multiprocessor  2034  or L1 cache  2048  or processing cluster  2094 . In at least one embodiment, a physical address is processed to distribute surface data access locality to allow efficient request interleaving among partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or miss. 
     In at least one embodiment, processing cluster  2094  may be configured such that each graphics multiprocessor  2034  is coupled to a texture unit  2036  for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor  2034  and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor  2034  outputs a processed task to data crossbar  2040  to provide the processed task to another processing cluster  2094  for further processing or to store the processed task in an L2 cache, a local parallel processor memory, or a system memory via memory crossbar  2016 . In at least one embodiment, a pre-raster operations unit (“preROP”)  2042  is configured to receive data from graphics multiprocessor  2034 , direct data to ROP units, which may be located with partition units as described herein (e.g., partition units  2020 A- 2020 N of  FIG. 20 ). In at least one embodiment, PreROP  2042  can perform optimizations for color blending, organize pixel color data, and perform address translations. 
       FIG. 20C  illustrates a graphics multiprocessor  2096 , in accordance with at least one embodiment. In at least one embodiment, graphics multiprocessor  2096  is graphics multiprocessor  2034  of  FIG. 20B . In at least one embodiment, graphics multiprocessor  2096  couples with pipeline manager  2032  of processing cluster  2094 . In at least one embodiment, graphics multiprocessor  2096  has an execution pipeline including but not limited to an instruction cache  2052 , an instruction unit  2054 , an address mapping unit  2056 , a register file  2058 , one or more GPGPU cores  2062 , and one or more LSUs  2066 . GPGPU cores  2062  and LSUs  2066  are coupled with cache memory  2072  and shared memory  2070  via a memory and cache interconnect  2068 . 
     In at least one embodiment, instruction cache  2052  receives a stream of instructions to execute from pipeline manager  2032 . In at least one embodiment, instructions are cached in instruction cache  2052  and dispatched for execution by instruction unit  2054 . In at least one embodiment, instruction unit  2054  can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group assigned to a different execution unit within GPGPU core  2062 . In at least one embodiment, an instruction can access any of a local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit  2056  can be used to translate addresses in a unified address space into a distinct memory address that can be accessed by LSUs  2066 . 
     In at least one embodiment, register file  2058  provides a set of registers for functional units of graphics multiprocessor  2096 . In at least one embodiment, register file  2058  provides temporary storage for operands connected to data paths of functional units (e.g., GPGPU cores  2062 , LSUs  2066 ) of graphics multiprocessor  2096 . In at least one embodiment, register file  2058  is divided between each of functional units such that each functional unit is allocated a dedicated portion of register file  2058 . In at least one embodiment, register file  2058  is divided between different thread groups being executed by graphics multiprocessor  2096 . 
     In at least one embodiment, GPGPU cores  2062  can each include FPUs and/or integer ALUs that are used to execute instructions of graphics multiprocessor  2096 . GPGPU cores  2062  can be similar in architecture or can differ in architecture. In at least one embodiment, a first portion of GPGPU cores  2062  include a single precision FPU and an integer ALU while a second portion of GPGPU cores  2062  include a double precision FPU. In at least one embodiment, FPUs can implement IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics multiprocessor  2096  can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. In at least one embodiment one or more of GPGPU cores  2062  can also include fixed or special function logic. 
     In at least one embodiment, GPGPU cores  2062  include SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment GPGPU cores  2062  can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores  2062  can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (“SPMD”) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for an SIMT execution model can executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform the same or similar operations can be executed in parallel via a single SIMD8 logic unit. 
     In at least one embodiment, memory and cache interconnect  2068  is an interconnect network that connects each functional unit of graphics multiprocessor  2096  to register file  2058  and to shared memory  2070 . In at least one embodiment, memory and cache interconnect  2068  is a crossbar interconnect that allows LSU  2066  to implement load and store operations between shared memory  2070  and register file  2058 . In at least one embodiment, register file  2058  can operate at a same frequency as GPGPU cores  2062 , thus data transfer between GPGPU cores  2062  and register file  2058  is very low latency. In at least one embodiment, shared memory  2070  can be used to enable communication between threads that execute on functional units within graphics multiprocessor  2096 . In at least one embodiment, cache memory  2072  can be used as a data cache for example, to cache texture data communicated between functional units and texture unit  2036 . In at least one embodiment, shared memory  2070  can also be used as a program managed cached. In at least one embodiment, threads executing on GPGPU cores  2062  can programmatically store data within shared memory in addition to automatically cached data that is stored within cache memory  2072 . 
     In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to host/processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, a GPU may be communicatively coupled to host processor/cores over a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In at least one embodiment, a GPU may be integrated on the same package or chip as cores and communicatively coupled to cores over a processor bus/interconnect that is internal to a package or a chip. In at least one embodiment, regardless of the manner in which a GPU is connected, processor cores may allocate work to the GPU in the form of sequences of commands/instructions contained in a WD. In at least one embodiment, the GPU then uses dedicated circuitry/logic for efficiently processing these commands/instructions. 
       FIG. 21  illustrates a graphics processor  2100 , in accordance with at least one embodiment. In at least one embodiment, graphics processor  2100  includes a ring interconnect  2102 , a pipeline front-end  2104 , a media engine  2137 , and graphics cores  2180 A- 2180 N. In at least one embodiment, ring interconnect  2102  couples graphics processor  2100  to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor  2100  is one of many processors integrated within a multi-core processing system. 
     In at least one embodiment, graphics processor  2100  receives batches of commands via ring interconnect  2102 . In at least one embodiment, incoming commands are interpreted by a command streamer  2103  in pipeline front-end  2104 . In at least one embodiment, graphics processor  2100  includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s)  2180 A- 2180 N. In at least one embodiment, for 3D geometry processing commands, command streamer  2103  supplies commands to geometry pipeline  2136 . In at least one embodiment, for at least some media processing commands, command streamer  2103  supplies commands to a video front end  2134 , which couples with a media engine  2137 . In at least one embodiment, media engine  2137  includes a Video Quality Engine (“VQE”)  2130  for video and image post-processing and a multi-format encode/decode (“MFX”) engine  2133  to provide hardware-accelerated media data encode and decode. In at least one embodiment, geometry pipeline  2136  and media engine  2137  each generate execution threads for thread execution resources provided by at least one graphics core  2180 A. 
     In at least one embodiment, graphics processor  2100  includes scalable thread execution resources featuring modular graphics cores  2180 A- 2180 N (sometimes referred to as core slices), each having multiple sub-cores  2150 A- 550 N,  2160 A- 2160 N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor  2100  can have any number of graphics cores  2180 A through  2180 N. In at least one embodiment, graphics processor  2100  includes a graphics core  2180 A having at least a first sub-core  2150 A and a second sub-core  2160 A. In at least one embodiment, graphics processor  2100  is a low power processor with a single sub-core (e.g., sub-core  2150 A). In at least one embodiment, graphics processor  2100  includes multiple graphics cores  2180 A- 2180 N, each including a set of first sub-cores  2150 A- 2150 N and a set of second sub-cores  2160 A- 2160 N. In at least one embodiment, each sub-core in first sub-cores  2150 A- 2150 N includes at least a first set of execution units (“EUs”)  2152 A- 2152 N and media/texture samplers  2154 A- 2154 N. In at least one embodiment, each sub-core in second sub-cores  2160 A- 2160 N includes at least a second set of execution units  2162 A- 2162 N and samplers  2164 A- 2164 N. In at least one embodiment, each sub-core  2150 A- 2150 N,  2160 A- 2160 N shares a set of shared resources  2170 A- 2170 N. In at least one embodiment, shared resources  2170  include shared cache memory and pixel operation logic. 
       FIG. 22  illustrates a processor  2200 , in accordance with at least one embodiment. In at least one embodiment, processor  2200  may include, without limitation, logic circuits to perform instructions. In at least one embodiment, processor  2200  may perform instructions, including x86 instructions, ARM instructions, specialized instructions for ASICs, etc. In at least one embodiment, processor  2210  may include registers to store packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, Calif. In at least one embodiment, MMX registers, available in both integer and floating point forms, may operate with packed data elements that accompany SIMD and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers relating to SSE2, SSE3, SSE4, AVX, or beyond (referred to generically as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processors  2210  may perform instructions to accelerate CUDA programs. 
     In at least one embodiment, processor  2200  includes an in-order front end (“front end”)  2201  to fetch instructions to be executed and prepare instructions to be used later in processor pipeline. In at least one embodiment, front end  2201  may include several units. In at least one embodiment, an instruction prefetcher  2226  fetches instructions from memory and feeds instructions to an instruction decoder  2228  which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder  2228  decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called “micro ops” or “uops”) for execution. In at least one embodiment, instruction decoder  2228  parses instruction into an opcode and corresponding data and control fields that may be used by micro-architecture to perform operations. In at least one embodiment, a trace cache  2230  may assemble decoded uops into program ordered sequences or traces in a uop queue  2234  for execution. In at least one embodiment, when trace cache  2230  encounters a complex instruction, a microcode ROM  2232  provides uops needed to complete an operation. 
     In at least one embodiment, some instructions may be converted into a single micro-op, whereas others need several micro-ops to complete full operation. In at least one embodiment, if more than four micro-ops are needed to complete an instruction, instruction decoder  2228  may access microcode ROM  2232  to perform instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing at instruction decoder  2228 . In at least one embodiment, an instruction may be stored within microcode ROM  2232  should a number of micro-ops be needed to accomplish operation. In at least one embodiment, trace cache  2230  refers to an entry point programmable logic array (“PLA”) to determine a correct micro-instruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM  2232 . In at least one embodiment, after microcode ROM  2232  finishes sequencing micro-ops for an instruction, front end  2201  of machine may resume fetching micro-ops from trace cache  2230 . 
     In at least one embodiment, out-of-order execution engine (“out of order engine”)  2203  may prepare instructions for execution. In at least one embodiment, out-of-order execution logic has a number of buffers to smooth out and re-order the flow of instructions to optimize performance as they go down a pipeline and get scheduled for execution. Out-of-order execution engine  2203  includes, without limitation, an allocator/register renamer  2240 , a memory uop queue  2242 , an integer/floating point uop queue  2244 , a memory scheduler  2246 , a fast scheduler  2202 , a slow/general floating point scheduler (“slow/general FP scheduler”)  2204 , and a simple floating point scheduler (“simple FP scheduler”)  2206 . In at least one embodiment, fast schedule  2202 , slow/general floating point scheduler  2204 , and simple floating point scheduler  2206  are also collectively referred to herein as “uop schedulers  2202 ,  2204 ,  2206 .” Allocator/register renamer  2240  allocates machine buffers and resources that each uop needs in order to execute. In at least one embodiment, allocator/register renamer  2240  renames logic registers onto entries in a register file. In at least one embodiment, allocator/register renamer  2240  also allocates an entry for each uop in one of two uop queues, memory uop queue  2242  for memory operations and integer/floating point uop queue  2244  for non-memory operations, in front of memory scheduler  2246  and uop schedulers  2202 ,  2204 ,  2206 . In at least one embodiment, uop schedulers  2202 ,  2204 ,  2206 , determine when a uop is ready to execute based on readiness of their dependent input register operand sources and availability of execution resources uops need to complete their operation. In at least one embodiment, fast scheduler  2202  of at least one embodiment may schedule on each half of main clock cycle while slow/general floating point scheduler  2204  and simple floating point scheduler  2206  may schedule once per main processor clock cycle. In at least one embodiment, uop schedulers  2202 ,  2204 ,  2206  arbitrate for dispatch ports to schedule uops for execution. 
     In at least one embodiment, execution block  2211  includes, without limitation, an integer register file/bypass network  2208 , a floating point register file/bypass network (“FP register file/bypass network”)  2210 , address generation units (“AGUs”)  2212  and  2214 , fast ALUs  2216  and  2218 , a slow ALU  2220 , a floating point ALU (“FP”)  2222 , and a floating point move unit (“FP move”)  2224 . In at least one embodiment, integer register file/bypass network  2208  and floating point register file/bypass network  2210  are also referred to herein as “register files  2208 ,  2210 .” In at least one embodiment, AGUSs  2212  and  2214 , fast ALUs  2216  and  2218 , slow ALU  2220 , floating point ALU  2222 , and floating point move unit  2224  are also referred to herein as “execution units  2212 ,  2214 ,  2216 ,  2218 ,  2220 ,  2222 , and  2224 .” In at least one embodiment, an execution block may include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units, in any combination. 
     In at least one embodiment, register files  2208 ,  2210  may be arranged between uop schedulers  2202 ,  2204 ,  2206 , and execution units  2212 ,  2214 ,  2216 ,  2218 ,  2220 ,  2222 , and  2224 . In at least one embodiment, integer register file/bypass network  2208  performs integer operations. In at least one embodiment, floating point register file/bypass network  2210  performs floating point operations. In at least one embodiment, each of register files  2208 ,  2210  may include, without limitation, a bypass network that may bypass or forward just completed results that have not yet been written into register file to new dependent uops. In at least one embodiment, register files  2208 ,  2210  may communicate data with each other. In at least one embodiment, integer register file/bypass network  2208  may include, without limitation, two separate register files, one register file for low-order thirty-two bits of data and a second register file for high order thirty-two bits of data. In at least one embodiment, floating point register file/bypass network  2210  may include, without limitation, 128-bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width. 
     In at least one embodiment, execution units  2212 ,  2214 ,  2216 ,  2218 ,  2220 ,  2222 ,  2224  may execute instructions. In at least one embodiment, register files  2208 ,  2210  store integer and floating point data operand values that micro-instructions need to execute. In at least one embodiment, processor  2200  may include, without limitation, any number and combination of execution units  2212 ,  2214 ,  2216 ,  2218 ,  2220 ,  2222 ,  2224 . In at least one embodiment, floating point ALU  2222  and floating point move unit  2224  may execute floating point, MMX, SIMD, AVX and SSE, or other operations. In at least one embodiment, floating point ALU  2222  may include, without limitation, a 64-bit by 64-bit floating point divider to execute divide, square root, and remainder micro ops. In at least one embodiment, instructions involving a floating point value may be handled with floating point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs  2216 ,  2218 . In at least one embodiment, fast ALUS  2216 ,  2218  may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU  2220  as slow ALU  2220  may include, without limitation, integer execution hardware for long-latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load/store operations may be executed by AGUs  2212 ,  2214 . In at least one embodiment, fast ALU  2216 , fast ALU  2218 , and slow ALU  2220  may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU  2216 , fast ALU  2218 , and slow ALU  2220  may be implemented to support a variety of data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating point ALU  2222  and floating point move unit  2224  may be implemented to support a range of operands having bits of various widths. In at least one embodiment, floating point ALU  2222  and floating point move unit  2224  may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions. 
     In at least one embodiment, uop schedulers  2202 ,  2204 ,  2206  dispatch dependent operations before parent load has finished executing. In at least one embodiment, as uops may be speculatively scheduled and executed in processor  2200 , processor  2200  may also include logic to handle memory misses. In at least one embodiment, if a data load misses in a data cache, there may be dependent operations in flight in pipeline that have left a scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations might need to be replayed and independent ones may be allowed to complete. In at least one embodiment, schedulers and replay mechanisms of at least one embodiment of a processor may also be designed to catch instruction sequences for text string comparison operations. 
     In at least one embodiment, the term “registers” may refer to on-board processor storage locations that may be used as part of instructions to identify operands. In at least one embodiment, registers may be those that may be usable from outside of a processor (from a programmer&#39;s perspective). In at least one embodiment, registers might not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform functions described herein. In at least one embodiment, registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. A register file of at least one embodiment also contains eight multimedia SIMD registers for packed data. 
       FIG. 23  illustrates a processor  2300 , in accordance with at least one embodiment. In at least one embodiment, processor  2300  includes, without limitation, one or more processor cores (“cores”)  2302 A- 2302 N, an integrated memory controller  2314 , and an integrated graphics processor  2308 . In at least one embodiment, processor  2300  can include additional cores up to and including additional processor core  2302 N represented by dashed lined boxes. In at least one embodiment, each of processor cores  2302 A- 2302 N includes one or more internal cache units  2304 A- 2304 N. In at least one embodiment, each processor core also has access to one or more shared cached units  2306 . 
     In at least one embodiment, internal cache units  2304 A- 2304 N and shared cache units  2306  represent a cache memory hierarchy within processor  2300 . In at least one embodiment, cache memory units  2304 A- 2304 N may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as an L2, L3, Level 4 (“L4”), or other levels of cache, where a highest level of cache before external memory is classified as an LLC. In at least one embodiment, cache coherency logic maintains coherency between various cache units  2306  and  2304 A- 2304 N. 
     In at least one embodiment, processor  2300  may also include a set of one or more bus controller units  2316  and a system agent core  2310 . In at least one embodiment, one or more bus controller units  2316  manage a set of peripheral buses, such as one or more PCI or PCI express buses. In at least one embodiment, system agent core  2310  provides management functionality for various processor components. In at least one embodiment, system agent core  2310  includes one or more integrated memory controllers  2314  to manage access to various external memory devices (not shown). 
     In at least one embodiment, one or more of processor cores  2302 A- 2302 N include support for simultaneous multi-threading. In at least one embodiment, system agent core  2310  includes components for coordinating and operating processor cores  2302 A- 2302 N during multi-threaded processing. In at least one embodiment, system agent core  2310  may additionally include a power control unit (“PCU”), which includes logic and components to regulate one or more power states of processor cores  2302 A- 2302 N and graphics processor  2308 . 
     In at least one embodiment, processor  2300  additionally includes graphics processor  2308  to execute graphics processing operations. In at least one embodiment, graphics processor  2308  couples with shared cache units  2306 , and system agent core  2310 , including one or more integrated memory controllers  2314 . In at least one embodiment, system agent core  2310  also includes a display controller  2311  to drive graphics processor output to one or more coupled displays. In at least one embodiment, display controller  2311  may also be a separate module coupled with graphics processor  2308  via at least one interconnect, or may be integrated within graphics processor  2308 . 
     In at least one embodiment, a ring based interconnect unit  2312  is used to couple internal components of processor  2300 . In at least one embodiment, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques. In at least one embodiment, graphics processor  2308  couples with ring interconnect  2312  via an I/O link  2313 . 
     In at least one embodiment, I/O link  2313  represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module  2318 , such as an eDRAM module. In at least one embodiment, each of processor cores  2302 A- 2302 N and graphics processor  2308  use embedded memory modules  2318  as a shared LLC. 
     In at least one embodiment, processor cores  2302 A- 2302 N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores  2302 A- 2302 N are heterogeneous in terms of ISA, where one or more of processor cores  2302 A- 2302 N execute a common instruction set, while one or more other cores of processor cores  2302 A- 23 - 02 N executes a subset of a common instruction set or a different instruction set. In at least one embodiment, processor cores  2302 A- 2302 N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more cores having a lower power consumption. In at least one embodiment, processor  2300  can be implemented on one or more chips or as a SoC integrated circuit. 
       FIG. 24  illustrates a graphics processor core  2400 , in accordance with at least one embodiment described. In at least one embodiment, graphics processor core  2400  is included within a graphics core array. In at least one embodiment, graphics processor core  2400 , sometimes referred to as a core slice, can be one or multiple graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core  2400  is exemplary of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core  2400  can include a fixed function block  2430  coupled with multiple sub-cores  2401 A- 2401 F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed function logic. 
     In at least one embodiment, fixed function block  2430  includes a geometry/fixed function pipeline  2436  that can be shared by all sub-cores in graphics processor  2400 , for example, in lower performance and/or lower power graphics processor implementations. In at least one embodiment, geometry/fixed function pipeline  2436  includes a 3D fixed function pipeline, a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager, which manages unified return buffers. 
     In at least one embodiment, fixed function block  2430  also includes a graphics SoC interface  2437 , a graphics microcontroller  2438 , and a media pipeline  2439 . Graphics SoC interface  2437  provides an interface between graphics core  2400  and other processor cores within a SoC integrated circuit. In at least one embodiment, graphics microcontroller  2438  is a programmable sub-processor that is configurable to manage various functions of graphics processor  2400 , including thread dispatch, scheduling, and pre-emption. In at least one embodiment, media pipeline  2439  includes logic to facilitate decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline  2439  implements media operations via requests to compute or sampling logic within sub-cores  2401 - 2401 F. 
     In at least one embodiment, SoC interface  2437  enables graphics core  2400  to communicate with general-purpose application processor cores (e.g., CPUs) and/or other components within a SoC, including memory hierarchy elements such as a shared LLC memory, system RAM, and/or embedded on-chip or on-package DRAM. In at least one embodiment, SoC interface  2437  can also enable communication with fixed function devices within a SoC, such as camera imaging pipelines, and enables use of and/or implements global memory atomics that may be shared between graphics core  2400  and CPUs within a SoC. In at least one embodiment, SoC interface  2437  can also implement power management controls for graphics core  2400  and enable an interface between a clock domain of graphic core  2400  and other clock domains within a SoC. In at least one embodiment, SoC interface  2437  enables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. In at least one embodiment, commands and instructions can be dispatched to media pipeline  2439 , when media operations are to be performed, or a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline  2436 , geometry and fixed function pipeline  2414 ) when graphics processing operations are to be performed. 
     In at least one embodiment, graphics microcontroller  2438  can be configured to perform various scheduling and management tasks for graphics core  2400 . In at least one embodiment, graphics microcontroller  2438  can perform graphics and/or compute workload scheduling on various graphics parallel engines within execution unit (EU) arrays  2402 A- 2402 F,  2404 A- 2404 F within sub-cores  2401 A- 2401 F. In at least one embodiment, host software executing on a CPU core of a SoC including graphics core  2400  can submit workloads one of multiple graphic processor doorbells, which invokes a scheduling operation on an appropriate graphics engine. In at least one embodiment, scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. In at least one embodiment, graphics microcontroller  2438  can also facilitate low-power or idle states for graphics core  2400 , providing graphics core  2400  with an ability to save and restore registers within graphics core  2400  across low-power state transitions independently from an operating system and/or graphics driver software on a system. 
     In at least one embodiment, graphics core  2400  may have greater than or fewer than illustrated sub-cores  2401 A- 2401 F, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core  2400  can also include shared function logic  2410 , shared and/or cache memory  2412 , a geometry/fixed function pipeline  2414 , as well as additional fixed function logic  2416  to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic  2410  can include logic units (e.g., sampler, math, and/or inter-thread communication logic) that can be shared by each N sub-cores within graphics core  2400 . Shared and/or cache memory  2412  can be an LLC for N sub-cores  2401 A- 2401 F within graphics core  2400  and can also serve as shared memory that is accessible by multiple sub-cores. In at least one embodiment, geometry/fixed function pipeline  2414  can be included instead of geometry/fixed function pipeline  2436  within fixed function block  2430  and can include same or similar logic units. 
     In at least one embodiment, graphics core  2400  includes additional fixed function logic  2416  that can include various fixed function acceleration logic for use by graphics core  2400 . In at least one embodiment, additional fixed function logic  2416  includes an additional geometry pipeline for use in position only shading. In position-only shading, at least two geometry pipelines exist, whereas in a full geometry pipeline within geometry/fixed function pipeline  2416 ,  2436 , and a cull pipeline, which is an additional geometry pipeline which may be included within additional fixed function logic  2416 . In at least one embodiment, cull pipeline is a trimmed down version of a full geometry pipeline. In at least one embodiment, a full pipeline and a cull pipeline can execute different instances of an application, each instance having a separate context. In at least one embodiment, position only shading can hide long cull runs of discarded triangles, enabling shading to be completed earlier in some instances. For example, in at least one embodiment, cull pipeline logic within additional fixed function logic  2416  can execute position shaders in parallel with a main application and generally generates critical results faster than a full pipeline, as a cull pipeline fetches and shades position attribute of vertices, without performing rasterization and rendering of pixels to a frame buffer. In at least one embodiment, a cull pipeline can use generated critical results to compute visibility information for all triangles without regard to whether those triangles are culled. In at least one embodiment, a full pipeline (which in this instance may be referred to as a replay pipeline) can consume visibility information to skip culled triangles to shade only visible triangles that are finally passed to a rasterization phase. 
     In at least one embodiment, additional fixed function logic  2416  can also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for accelerating CUDA programs. 
     In at least one embodiment, each graphics sub-core  2401 A- 2401 F includes a set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. In at least one embodiment, graphics sub-cores  2401 A- 2401 F include multiple EU arrays  2402 A- 2402 F,  2404 A- 2404 F, thread dispatch and inter-thread communication (“TD/IC”) logic  2403 A- 2403 F, a 3D (e.g., texture) sampler  2405 A- 2405 F, a media sampler  2406 A- 2406 F, a shader processor  2407 A- 2407 F, and shared local memory (“SLM”)  2408 A- 2408 F. EU arrays  2402 A- 2402 F,  2404 A- 2404 F each include multiple execution units, which are GPGPUs capable of performing floating-point and integer/fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. In at least one embodiment, TD/IC logic  2403 A- 2403 F performs local thread dispatch and thread control operations for execution units within a sub-core and facilitate communication between threads executing on execution units of a sub-core. In at least one embodiment, 3D sampler  2405 A- 2405 F can read texture or other 3D graphics related data into memory. In at least one embodiment, 3D sampler can read texture data differently based on a configured sample state and texture format associated with a given texture. In at least one embodiment, media sampler  2406 A- 2406 F can perform similar read operations based on a type and format associated with media data. In at least one embodiment, each graphics sub-core  2401 A- 2401 F can alternately include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each of sub-cores  2401 A- 2401 F can make use of shared local memory  2408 A- 2408 F within each sub-core, to enable threads executing within a thread group to execute using a common pool of on-chip memory. 
       FIG. 25  illustrates a parallel processing unit (“PPU”)  2500 , in accordance with at least one embodiment. In at least one embodiment, PPU  2500  is configured with machine-readable code that, if executed by PPU  2500 , causes PPU  2500  to perform some or all of processes and techniques described herein. In at least one embodiment, PPU  2500  is a multi-threaded processor that is implemented on one or more integrated circuit devices and that utilizes multithreading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) on multiple threads in parallel. In at least one embodiment, a thread refers to a thread of execution and is an instantiation of a set of instructions configured to be executed by PPU  2500 . In at least one embodiment, PPU  2500  is a GPU configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data in order to generate two-dimensional (“2D”) image data for display on a display device such as an LCD device. In at least one embodiment, PPU  2500  is utilized to perform computations such as linear algebra operations and machine-learning operations.  FIG. 25  illustrates an example parallel processor for illustrative purposes only and should be construed as a non-limiting example of a processor architecture that may be implemented in at least one embodiment. 
     In at least one embodiment, one or more PPUs  2500  are configured to accelerate High Performance Computing (“HPC”), data center, and machine learning applications. In at least one embodiment, one or more PPUs  2500  are configured to accelerate CUDA programs. In at least one embodiment, PPU  2500  includes, without limitation, an I/O unit  2506 , a front-end unit  2510 , a scheduler unit  2512 , a work distribution unit  2514 , a hub  2516 , a crossbar (“Xbar”)  2520 , one or more general processing clusters (“GPCs”)  2518 , and one or more partition units (“memory partition units”)  2522 . In at least one embodiment, PPU  2500  is connected to a host processor or other PPUs  2500  via one or more high-speed GPU interconnects (“GPU interconnects”)  2508 . In at least one embodiment, PPU  2500  is connected to a host processor or other peripheral devices via a system bus or interconnect  2502 . In at least one embodiment, PPU  2500  is connected to a local memory comprising one or more memory devices (“memory”)  2504 . In at least one embodiment, memory devices  2504  include, without limitation, one or more dynamic random access memory (DRAM) devices. In at least one embodiment, one or more DRAM devices are configured and/or configurable as high-bandwidth memory (“HBM”) subsystems, with multiple DRAM dies stacked within each device. 
     In at least one embodiment, high-speed GPU interconnect  2508  may refer to a wire-based multi-lane communications link that is used by systems to scale and include one or more PPUs  2500  combined with one or more CPUs, supports cache coherence between PPUs  2500  and CPUs, and CPU mastering. In at least one embodiment, data and/or commands are transmitted by high-speed GPU interconnect  2508  through hub  2516  to/from other units of PPU  2500  such as one or more copy engines, video encoders, video decoders, power management units, and other components which may not be explicitly illustrated in  FIG. 25 . 
     In at least one embodiment, I/O unit  2506  is configured to transmit and receive communications (e.g., commands, data) from a host processor (not illustrated in  FIG. 25 ) over system bus  2502 . In at least one embodiment, I/O unit  2506  communicates with host processor directly via system bus  2502  or through one or more intermediate devices such as a memory bridge. In at least one embodiment, I/O unit  2506  may communicate with one or more other processors, such as one or more of PPUs  2500  via system bus  2502 . In at least one embodiment, I/O unit  2506  implements a PCIe interface for communications over a PCIe bus. In at least one embodiment, I/O unit  2506  implements interfaces for communicating with external devices. 
     In at least one embodiment, I/O unit  2506  decodes packets received via system bus  2502 . In at least one embodiment, at least some packets represent commands configured to cause PPU  2500  to perform various operations. In at least one embodiment, I/O unit  2506  transmits decoded commands to various other units of PPU  2500  as specified by commands. In at least one embodiment, commands are transmitted to front-end unit  2510  and/or transmitted to hub  2516  or other units of PPU  2500  such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly illustrated in  FIG. 25 ). In at least one embodiment, I/O unit  2506  is configured to route communications between and among various logical units of PPU  2500 . 
     In at least one embodiment, a program executed by host processor encodes a command stream in a buffer that provides workloads to PPU  2500  for processing. In at least one embodiment, a workload comprises instructions and data to be processed by those instructions. In at least one embodiment, buffer is a region in a memory that is accessible read/write) by both a host processor and PPU  2500 —a host interface unit may be configured to access buffer in a system memory connected to system bus  2502  via memory requests transmitted over system bus  2502  by I/O unit  2506 . In at least one embodiment, a host processor writes a command stream to a buffer and then transmits a pointer to the start of the command stream to PPU  2500  such that front-end unit  2510  receives pointers to one or more command streams and manages one or more command streams, reading commands from command streams and forwarding commands to various units of PPU  2500 . 
     In at least one embodiment, front-end unit  2510  is coupled to scheduler unit  2512  that configures various GPCs  2518  to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit  2512  is configured to track state information related to various tasks managed by scheduler unit  2512  where state information may indicate which of GPCs  2518  a task is assigned to, whether task is active or inactive, a priority level associated with task, and so forth. In at least one embodiment, scheduler unit  2512  manages execution of a plurality of tasks on one or more of GPCs  2518 . 
     In at least one embodiment, scheduler unit  2512  is coupled to work distribution unit  2514  that is configured to dispatch tasks for execution on GPCs  2518 . In at least one embodiment, work distribution unit  2514  tracks a number of scheduled tasks received from scheduler unit  2512  and work distribution unit  2514  manages a pending task pool and an active task pool for each of GPCs  2518 . In at least one embodiment, pending task pool comprises a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular GPC  2518 ; active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by GPCs  2518  such that as one of GPCs  2518  completes execution of a task, that task is evicted from active task pool for GPC  2518  and one of other tasks from pending task pool is selected and scheduled for execution on GPC  2518 . In at least one embodiment, if an active task is idle on GPC  2518 , such as while waiting for a data dependency to be resolved, then the active task is evicted from GPC  2518  and returned to a pending task pool while another task in the pending task pool is selected and scheduled for execution on GPC  2518 . 
     In at least one embodiment, work distribution unit  2514  communicates with one or more GPCs  2518  via XBar  2520 . In at least one embodiment, XBar  2520  is an interconnect network that couples many units of PPU  2500  to other units of PPU  2500  and can be configured to couple work distribution unit  2514  to a particular GPC  2518 . In at least one embodiment, one or more other units of PPU  2500  may also be connected to XBar  2520  via hub  2516 . 
     In at least one embodiment, tasks are managed by scheduler unit  2512  and dispatched to one of GPCs  2518  by work distribution unit  2514 . GPC  2518  is configured to process task and generate results. In at least one embodiment, results may be consumed by other tasks within GPC  2518 , routed to a different GPC  2518  via XBar  2520 , or stored in memory  2504 . In at least one embodiment, results can be written to memory  2504  via partition units  2522 , which implement a memory interface for reading and writing data to/from memory  2504 . In at least one embodiment, results can be transmitted to another PPU  2504  or CPU via high-speed GPU interconnect  2508 . In at least one embodiment, PPU  2500  includes, without limitation, a number U of partition units  2522  that is equal to number of separate and distinct memory devices  2504  coupled to PPU  2500 . 
     In at least one embodiment, a host processor executes a driver kernel that implements an application programming interface (“API”) that enables one or more applications executing on host processor to schedule operations for execution on PPU  2500 . In at least one embodiment, multiple compute applications are simultaneously executed by PPU  2500  and PPU  2500  provides isolation, quality of service (“QoS”), and independent address spaces for multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause a driver kernel to generate one or more tasks for execution by PPU  2500  and the driver kernel outputs tasks to one or more streams being processed by PPU  2500 . In at least one embodiment, each task comprises one or more groups of related threads, which may be referred to as a warp. In at least one embodiment, a warp comprises a plurality of related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, cooperating threads can refer to a plurality of threads including instructions to perform a task and that exchange data through shared memory. 
       FIG. 26  illustrates a GPC  2600 , in accordance with at least one embodiment. In at least one embodiment, GPC  2600  is GPC  2518  of  FIG. 25 . In at least one embodiment, each GPC  2600  includes, without limitation, a number of hardware units for processing tasks and each GPC  2600  includes, without limitation, a pipeline manager  2602 , a pre-raster operations unit (“PROP”)  2604 , a raster engine  2608 , a work distribution crossbar (“WDX”)  2616 , an MMU  2618 , one or more Data Processing Clusters (“DPCs”)  2606 , and any suitable combination of parts. 
     In at least one embodiment, operation of GPC  2600  is controlled by pipeline manager  2602 . In at least one embodiment, pipeline manager  2602  manages configuration of one or more DPCs  2606  for processing tasks allocated to GPC  2600 . In at least one embodiment, pipeline manager  2602  configures at least one of one or more DPCs  2606  to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, DPC  2606  is configured to execute a vertex shader program on a programmable streaming multiprocessor (“SM”)  2614 . In at least one embodiment, pipeline manager  2602  is configured to route packets received from a work distribution unit to appropriate logical units within GPC  2600  and, in at least one embodiment, some packets may be routed to fixed function hardware units in PROP  2604  and/or raster engine  2608  while other packets may be routed to DPCs  2606  for processing by a primitive engine  2612  or SM  2614 . In at least one embodiment, pipeline manager  2602  configures at least one of DPCs  2606  to implement a computing pipeline. In at least one embodiment, pipeline manager  2602  configures at least one of DPCs  2606  to execute at least a portion of a CUDA program. 
     In at least one embodiment, PROP unit  2604  is configured to route data generated by raster engine  2608  and DPCs  2606  to a Raster Operations (“ROP”) unit in a partition unit, such as memory partition unit  2522  described in more detail above in conjunction with  FIG. 25 . In at least one embodiment, PROP unit  2604  is configured to perform optimizations for color blending, organize pixel data, perform address translations, and more. In at least one embodiment, raster engine  2608  includes, without limitation, a number of fixed function hardware units configured to perform various raster operations and, in at least one embodiment, raster engine  2608  includes, without limitation, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile coalescing engine, and any suitable combination thereof. In at least one embodiment, a setup engine receives transformed vertices and generates plane equations associated with geometric primitive defined by vertices; plane equations are transmitted to a coarse raster engine to generate coverage information (e.g., an x, y coverage mask for a tile) for a primitive; the output of the coarse raster engine is transmitted to a culling engine where fragments associated with a primitive that fail a z-test are culled, and transmitted to a clipping engine where fragments lying outside a viewing frustum are clipped. In at least one embodiment, fragments that survive clipping and culling are passed to a fine raster engine to generate attributes for pixel fragments based on plane equations generated by a setup engine. In at least one embodiment, the output of raster engine  2608  comprises fragments to be processed by any suitable entity such as by a fragment shader implemented within DPC  2606 . 
     In at least one embodiment, each DPC  2606  included in GPC  2600  comprise, without limitation, an M-Pipe Controller (“MPC”)  2610 ; primitive engine  2612 ; one or more SMs  2614 ; and any suitable combination thereof. In at least one embodiment, MPC  2610  controls operation of DPC  2606 , routing packets received from pipeline manager  2602  to appropriate units in DPC  2606 . In at least one embodiment, packets associated with a vertex are routed to primitive engine  2612 , which is configured to fetch vertex attributes associated with vertex from memory; in contrast, packets associated with a shader program may be transmitted to SM  2614 . 
     In at least one embodiment, SM  2614  comprises, without limitation, a programmable streaming processor that is configured to process tasks represented by a number of threads. In at least one embodiment, SM  2614  is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently and implements a SIMD architecture where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on same set of instructions. In at least one embodiment, all threads in group of threads execute same instructions. In at least one embodiment, SM  2614  implements a SIMT architecture wherein each thread in a group of threads is configured to process a different set of data based on same set of instructions, but where individual threads in group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, a call stack, and an execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within a warp diverge. In another embodiment, a program counter, a call stack, and an execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. In at least one embodiment, an execution state is maintained for each individual thread and threads executing the same instructions may be converged and executed in parallel for better efficiency. At least one embodiment of SM  2614  is described in more detail in conjunction with  FIG. 27 . 
     In at least one embodiment, MMU  2618  provides an interface between GPC  2600  and a memory partition unit (e.g., partition unit  2522  of  FIG. 25 ) and MMU  2618  provides translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In at least one embodiment, MMU  2618  provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses into physical addresses in memory. 
       FIG. 27  illustrates a streaming multiprocessor (“SM”)  2700 , in accordance with at least one embodiment. In at least one embodiment, SM  2700  is SM  2614  of  FIG. 26 . In at least one embodiment, SM  2700  includes, without limitation, an instruction cache  2702 ; one or more scheduler units  2704 ; a register file  2708 ; one or more processing cores (“cores”)  2710 ; one or more special function units (“SFUs”)  2712 ; one or more LSUs  2714 ; an interconnect network  2716 ; a shared memory/L1 cache  2718 ; and any suitable combination thereof. In at least one embodiment, a work distribution unit dispatches tasks for execution on GPCs of parallel processing units (PPUs) and each task is allocated to a particular Data Processing Cluster (DPC) within a GPC and, if a task is associated with a shader program, then the task is allocated to one of SMs  2700 . In at least one embodiment, scheduler unit  2704  receives tasks from a work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM  2700 . In at least one embodiment, scheduler unit  2704  schedules thread blocks for execution as warps of parallel threads, wherein each thread block is allocated at least one warp. In at least one embodiment, each warp executes threads. In at least one embodiment, scheduler unit  2704  manages a plurality of different thread blocks, allocating warps to different thread blocks and then dispatching instructions from a plurality of different cooperative groups to various functional units (e.g., processing cores  2710 , SFUs  2712 , and LSUs  2714 ) during each clock cycle. 
     In at least one embodiment, “cooperative groups” may refer to a programming model for organizing groups of communicating threads that allows developers to express granularity at which threads are communicating, enabling expression of richer, more efficient parallel decompositions. In at least one embodiment, cooperative launch APIs support synchronization amongst thread blocks for execution of parallel algorithms. In at least one embodiment, APIs of conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., syncthreads( ) function). However, in at least one embodiment, programmers may define groups of threads at smaller than thread block granularities and synchronize within defined groups to enable greater performance, design flexibility, and software reuse in the form of collective group-wide function interfaces. In at least one embodiment, cooperative groups enable programmers to define groups of threads explicitly at sub-block and multi-block granularities, and to perform collective operations such as synchronization on threads in a cooperative group. In at least one embodiment, a sub-block granularity is as small as a single thread. In at least one embodiment, a programming model supports clean composition across software boundaries, so that libraries and utility functions can synchronize safely within their local context without having to make assumptions about convergence. In at least one embodiment, cooperative group primitives enable new patterns of cooperative parallelism, including, without limitation, producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks. 
     In at least one embodiment, a dispatch unit  2706  is configured to transmit instructions to one or more of functional units and scheduler unit  2704  includes, without limitation, two dispatch units  2706  that enable two different instructions from same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit  2704  includes a single dispatch unit  2706  or additional dispatch units  2706 . 
     In at least one embodiment, each SM  2700 , in at least one embodiment, includes, without limitation, register file  2708  that provides a set of registers for functional units of SM  2700 . In at least one embodiment, register file  2708  is divided between each of the functional units such that each functional unit is allocated a dedicated portion of register file  2708 . In at least one embodiment, register file  2708  is divided between different warps being executed by SM  2700  and register file  2708  provides temporary storage for operands connected to data paths of functional units. In at least one embodiment, each SM  2700  comprises, without limitation, a plurality of L processing cores  2710 . In at least one embodiment, SM  2700  includes, without limitation, a large number (e.g., 128 or more) of distinct processing cores  2710 . In at least one embodiment, each processing core  2710  includes, without limitation, a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes, without limitation, a floating point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, floating point arithmetic logic units implement IEEE 754-2008 standard for floating point arithmetic. In at least one embodiment, processing cores  2710  include, without limitation, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores. 
     In at least one embodiment, tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing cores  2710 . In at least one embodiment, tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices. 
     In at least one embodiment, matrix multiply inputs A and B are 16-bit floating point matrices and accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, tensor cores operate on 16-bit floating point input data with 32-bit floating point accumulation. In at least one embodiment, 16-bit floating point multiply uses 64 operations and results in a full precision product that is then accumulated using 32-bit floating point a27ition with other intermediate products for a 4×4×4 matrix multiply. Tensor cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements, in at least one embodiment. In at least one embodiment, an API, such as a CUDA-C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use tensor cores from a CUDA-C++ program. In at least one embodiment, at the CUDA level, a warp-level interface assumes 16×16 size matrices spanning all 32 threads of a warp. 
     In at least one embodiment, each SM  2700  comprises, without limitation, M SFUs  2712  that perform special functions (e.g., attribute evaluation, reciprocal square root, and like). In at least one embodiment, SFUs  2712  include, without limitation, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, SFUs  2712  include, without limitation, a texture unit configured to perform texture map filtering operations. In at least one embodiment, texture units are configured to load texture maps (e.g., a 2D array of texels) from memory and sample texture maps to produce sampled texture values for use in shader programs executed by SM  2700 . In at least one embodiment, texture maps are stored in shared memory/L1 cache  2718 . In at least one embodiment, texture units implement texture operations such as filtering operations using mip-maps (e.g., texture maps of varying levels of detail). In at least one embodiment, each SM  2700  includes, without limitation, two texture units. 
     In at least one embodiment, each SM  2700  comprises, without limitation, N LSUs  2714  that implement load and store operations between shared memory/L1 cache  2718  and register file  2708 . In at least one embodiment, each SM  2700  includes, without limitation, interconnect network  2716  that connects each of the functional units to register file  2708  and LSU  2714  to register file  2708  and shared memory/L1 cache  2718 . In at least one embodiment, interconnect network  2716  is a crossbar that can be configured to connect any of the functional units to any of the registers in register file  2708  and connect LSUs  2714  to register file  2708  and memory locations in shared memory/L1 cache  2718 . 
     In at least one embodiment, shared memory/L1 cache  2718  is an array of on-chip memory that allows for data storage and communication between SM  2700  and a primitive engine and between threads in SM  2700 . In at least one embodiment, shared memory/L1 cache  2718  comprises, without limitation, 128 KB of storage capacity and is in a path from SM  2700  to a partition unit. In at least one embodiment, shared memory/L1 cache  2718  is used to cache reads and writes. In at least one embodiment, one or more of shared memory/L1 cache  2718 , L2 cache, and memory are backing stores. 
     In at least one embodiment, combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory accesses. In at least one embodiment, capacity is used or is usable as a cache by programs that do not use shared memory, such as if shared memory is configured to use half of capacity, texture and load/store operations can use remaining capacity. In at least one embodiment, integration within shared memory/L1 cache  2718  enables shared memory/L1 cache  2718  to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, when configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. In at least one embodiment, fixed function GPUs are bypassed, creating a much simpler programming model. In at least one embodiment and in a general purpose parallel computation configuration, a work distribution unit assigns and distributes blocks of threads directly to DPCs. In at least one embodiment, threads in a block execute the same program, using a unique thread ID in a calculation to ensure each thread generates unique results, using SM  2700  to execute a program and perform calculations, shared memory/L1 cache  2718  to communicate between threads, and LSU  2714  to read and write global memory through shared memory/L1 cache  2718  and a memory partition unit. In at least one embodiment, when configured for general purpose parallel computation, SM  2700  writes commands that scheduler unit  2704  can use to launch new work on DPCs. 
     In at least one embodiment, PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), a PDA, a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and more. In at least one embodiment, PPU is embodied on a single semiconductor substrate. In at least one embodiment, PPU is included in a SoC along with one or more other devices such as additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter (“DAC”), and like. 
     In at least one embodiment, PPU may be included on a graphics card that includes one or more memory devices. In at least one embodiment, a graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In at least one embodiment, PPU may be an integrated GPU (“iGPU”) included in chipset of motherboard. 
     Software Constructions for General-Purpose Computing 
     The following figures set forth, without limitation, exemplary software constructs for implementing at least one embodiment. 
       FIG. 28  illustrates a software stack of a programming platform, in accordance with at least one embodiment. In at least one embodiment, a programming platform is a platform for leveraging hardware on a computing system to accelerate computational tasks. A programming platform may be accessible to software developers through libraries, compiler directives, and/or extensions to programming languages, in at least one embodiment. In at least one embodiment, a programming platform may be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL™ is developed by Khronos group), SYCL, or Intel One API. 
     In at least one embodiment, a software stack  2800  of a programming platform provides an execution environment for an application  2801 . In at least one embodiment, application  2801  may include any computer software capable of being launched on software stack  2800 . In at least one embodiment, application  2801  may include, but is not limited to, an artificial intelligence (“AI”)/machine learning (“ML”) application, a high performance computing (“HPC”) application, a virtual desktop infrastructure (“VDI”), or a data center workload. 
     In at least one embodiment, application  2801  and software stack  2800  run on hardware  2807 . Hardware  2807  may include one or more GPUs, CPUs, FPGAs, AI engines, and/or other types of compute devices that support a programming platform, in at least one embodiment. In at least one embodiment, such as with CUDA, software stack  2800  may be vendor specific and compatible with only devices from particular vendor(s). In at least one embodiment, such as in with OpenCL, software stack  2800  may be used with devices from different vendors. In at least one embodiment, hardware  2807  includes a host connected to one more devices that can be accessed to perform computational tasks via application programming interface (“API”) calls. A device within hardware  2807  may include, but is not limited to, a GPU, FPGA, AI engine, or other compute device (but may also include a CPU) and its memory, as opposed to a host within hardware  2807  that may include, but is not limited to, a CPU (but may also include a compute device) and its memory, in at least one embodiment. 
     In at least one embodiment, software stack  2800  of a programming platform includes, without limitation, a number of libraries  2803 , a runtime  2805 , and a device kernel driver  2806 . Each of libraries  2803  may include data and programming code that can be used by computer programs and leveraged during software development, in at least one embodiment. In at least one embodiment, libraries  2803  may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and/or message templates. In at least one embodiment, libraries  2803  include functions that are optimized for execution on one or more types of devices. In at least one embodiment, libraries  2803  may include, but are not limited to, functions for performing mathematical, deep learning, and/or other types of operations on devices. In at least one embodiment, libraries  2803  are associated with corresponding APIs  2802 , which may include one or more APIs, that expose functions implemented in libraries  2803 . 
     In at least one embodiment, application  2801  is written as source code that is compiled into executable code, as discussed in greater detail below in conjunction with  FIGS. 33-35 . Executable code of application  2801  may run, at least in part, on an execution environment provided by software stack  2800 , in at least one embodiment. In at least one embodiment, during execution of application  2801 , code may be reached that needs to run on a device, as opposed to a host. In such a case, runtime  2805  may be called to load and launch requisite code on the device, in at least one embodiment. In at least one embodiment, runtime  2805  may include any technically feasible runtime system that is able to support execution of application S01. 
     In at least one embodiment, runtime  2805  is implemented as one or more runtime libraries associated with corresponding APIs, which are shown as API(s)  2804 . One or more of such runtime libraries may include, without limitation, functions for memory management, execution control, device management, error handling, and/or synchronization, among other things, in at least one embodiment. In at least one embodiment, memory management functions may include, but are not limited to, functions to allocate, deallocate, and copy device memory, as well as transfer data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions to launch a function (sometimes referred to as a “kernel” when a function is a global function callable from a host) on a device and set attribute values in a buffer maintained by a runtime library for a given function to be executed on a device. 
     Runtime libraries and corresponding API(s)  2804  may be implemented in any technically feasible manner, in at least one embodiment. In at least one embodiment, one (or any number of) API may expose a low-level set of functions for fine-grained control of a device, while another (or any number of) API may expose a higher-level set of such functions. In at least one embodiment, a high-level runtime API may be built on top of a low-level API. In at least one embodiment, one or more of runtime APIs may be language-specific APIs that are layered on top of a language-independent runtime API. 
     In at least one embodiment, device kernel driver  2806  is configured to facilitate communication with an underlying device. In at least one embodiment, device kernel driver  2806  may provide low-level functionalities upon which APIs, such as API(s)  2804 , and/or other software relies. In at least one embodiment, device kernel driver  2806  may be configured to compile intermediate representation (“IR”) code into binary code at runtime. For CUDA, device kernel driver  2806  may compile Parallel Thread Execution (“PTX”) IR code that is not hardware specific into binary code for a specific target device at runtime (with caching of compiled binary code), which is also sometimes referred to as “finalizing” code, in at least one embodiment. Doing so may permit finalized code to run on a target device, which may not have existed when source code was originally compiled into PTX code, in at least one embodiment. Alternatively, in at least one embodiment, device source code may be compiled into binary code offline, without requiring device kernel driver  2806  to compile IR code at runtime. 
       FIG. 29  illustrates a CUDA implementation of software stack  2800  of  FIG. 28 , in accordance with at least one embodiment. In at least one embodiment, a CUDA software stack  2900 , on which an application  2901  may be launched, includes CUDA libraries  2903 , a CUDA runtime  2905 , a CUDA driver  2907 , and a device kernel driver  2908 . In at least one embodiment, CUDA software stack  2900  executes on hardware  2909 , which may include a GPU that supports CUDA and is developed by NVIDIA Corporation of Santa Clara, Calif. 
     In at least one embodiment, application  2901 , CUDA runtime  2905 , and device kernel driver  2908  may perform similar functionalities as application  2801 , runtime  2805 , and device kernel driver  2806 , respectively, which are described above in conjunction with  FIG. 28 . In at least one embodiment, CUDA driver  2907  includes a library (libcuda.so) that implements a CUDA driver API  2906 . Similar to a CUDA runtime API  2904  implemented by a CUDA runtime library (cudart), CUDA driver API  2906  may, without limitation, expose functions for memory management, execution control, device management, error handling, synchronization, and/or graphics interoperability, among other things, in at least one embodiment. In at least one embodiment, CUDA driver API  2906  differs from CUDA runtime API  2904  in that CUDA runtime API  2904  simplifies device code management by providing implicit initialization, context (analogous to a process) management, and module (analogous to dynamically loaded libraries) management. In contrast to high-level CUDA runtime API  2904 , CUDA driver API  2906  is a low-level API providing more fine-grained control of the device, particularly with respect to contexts and module loading, in at least one embodiment. In at least one embodiment, CUDA driver API  2906  may expose functions for context management that are not exposed by CUDA runtime API  2904 . In at least one embodiment, CUDA driver API  2906  is also language-independent and supports, e.g., OpenCL in addition to CUDA runtime API  2904 . Further, in at least one embodiment, development libraries, including CUDA runtime  2905 , may be considered as separate from driver components, including user-mode CUDA driver  2907  and kernel-mode device driver  2908  (also sometimes referred to as a “display” driver). 
     In at least one embodiment, CUDA libraries  2903  may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and/or signal/image/video processing libraries, which parallel computing applications such as application  2901  may utilize. In at least one embodiment, CUDA libraries  2903  may include mathematical libraries such as a cuBLAS library that is an implementation of Basic Linear Algebra Subprograms (“BLAS”) for performing linear algebra operations, a cuFFT library for computing fast Fourier transforms (“FFTs”), and a cuRAND library for generating random numbers, among others. In at least one embodiment, CUDA libraries  2903  may include deep learning libraries such as a cuDNN library of primitives for deep neural networks and a TensorRT platform for high-performance deep learning inference, among others. 
       FIG. 30  illustrates a ROCm implementation of software stack  2800  of  FIG. 28 , in accordance with at least one embodiment. In at least one embodiment, a ROCm software stack  3000 , on which an application  3001  may be launched, includes a language runtime  3003 , a system runtime  3005 , a thunk  3007 , and a ROCm kernel driver  3008 . In at least one embodiment, ROCm software stack  3000  executes on hardware  3009 , which may include a GPU that supports ROCm and is developed by AMD Corporation of Santa Clara, Calif. 
     In at least one embodiment, application  3001  may perform similar functionalities as application  2801  discussed above in conjunction with  FIG. 28 . In addition, language runtime  3003  and system runtime  3005  may perform similar functionalities as runtime  2805  discussed above in conjunction with  FIG. 28 , in at least one embodiment. In at least one embodiment, language runtime  3003  and system runtime  3005  differ in that system runtime  3005  is a language-independent runtime that implements a ROCr system runtime API  3004  and makes use of a Heterogeneous System Architecture (“HSA”) Runtime API. HSA runtime API is a thin, user-mode API that exposes interfaces to access and interact with an AMD GPU, including functions for memory management, execution control via architected dispatch of kernels, error handling, system and agent information, and runtime initialization and shutdown, among other things, in at least one embodiment. In contrast to system runtime  3005 , language runtime  3003  is an implementation of a language-specific runtime API  3002  layered on top of ROCr system runtime API  3004 , in at least one embodiment. In at least one embodiment, language runtime API may include, but is not limited to, a Heterogeneous compute Interface for Portability (“HIP”) language runtime API, a Heterogeneous Compute Compiler (“HCC”) language runtime API, or an OpenCL API, among others. HIP language in particular is an extension of C++ programming language with functionally similar versions of CUDA mechanisms, and, in at least one embodiment, a HIP language runtime API includes functions that are similar to those of CUDA runtime API  2904  discussed above in conjunction with  FIG. 29 , such as functions for memory management, execution control, device management, error handling, and synchronization, among other things. 
     In at least one embodiment, thunk (ROCt)  3007  is an interface  3006  that can be used to interact with underlying ROCm driver  3008 . In at least one embodiment, ROCm driver  3008  is a ROCk driver, which is a combination of an AMDGPU driver and a HSA kernel driver (amdkfd). In at least one embodiment, AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs similar functionalities as device kernel driver  2806  discussed above in conjunction with  FIG. 28 . In at least one embodiment, HSA kernel driver is a driver permitting different types of processors to share system resources more effectively via hardware features. 
     In at least one embodiment, various libraries (not shown) may be included in ROCm software stack  3000  above language runtime  3003  and provide functionality similarity to CUDA libraries  2903 , discussed above in conjunction with  FIG. 29 . In at least one embodiment, various libraries may include, but are not limited to, mathematical, deep learning, and/or other libraries such as a hipBLAS library that implements functions similar to those of CUDA cuBLAS, a rocFFT library for computing FFTs that is similar to CUDA cuFFT, among others. 
       FIG. 31  illustrates an OpenCL implementation of software stack  2800  of  FIG. 28 , in accordance with at least one embodiment. In at least one embodiment, an OpenCL software stack  3100 , on which an application  3101  may be launched, includes an OpenCL framework  3110 , an OpenCL runtime  3106 , and a driver  3107 . In at least one embodiment, OpenCL software stack  3100  executes on hardware  2909  that is not vendor-specific. As OpenCL is supported by devices developed by different vendors, specific OpenCL drivers may be required to interoperate with hardware from such vendors, in at least one embodiment. 
     In at least one embodiment, application  3101 , OpenCL runtime  3106 , device kernel driver  3107 , and hardware  3108  may perform similar functionalities as application  2801 , runtime  2805 , device kernel driver  2806 , and hardware  2807 , respectively, that are discussed above in conjunction with  FIG. 28 . In at least one embodiment, application  3101  further includes an OpenCL kernel  3102  with code that is to be executed on a device. 
     In at least one embodiment, OpenCL defines a “platform” that allows a host to control devices connected to the host. In at least one embodiment, an OpenCL framework provides a platform layer API and a runtime API, shown as platform API  3103  and runtime API  3105 . In at least one embodiment, runtime API  3105  uses contexts to manage execution of kernels on devices. In at least one embodiment, each identified device may be associated with a respective context, which runtime API  3105  may use to manage command queues, program objects, and kernel objects, share memory objects, among other things, for that device. In at least one embodiment, platform API  3103  exposes functions that permit device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices, among other things. In addition, OpenCL framework provides various built-in functions (not shown), including math functions, relational functions, and image processing functions, among others, in at least one embodiment. 
     In at least one embodiment, a compiler  3104  is also included in OpenCL frame-work  3110 . Source code may be compiled offline prior to executing an application or online during execution of an application, in at least one embodiment. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment may be compiled online by compiler  3104 , which is included to be representative of any number of compilers that may be used to compile source code and/or IR code, such as Standard Portable Intermediate Representation (“SPIR-V”) code, into binary code. Alternatively, in at least one embodiment, OpenCL applications may be compiled offline, prior to execution of such applications. 
       FIG. 32  illustrates software that is supported by a programming platform, in accordance with at least one embodiment. In at least one embodiment, a programming platform  3204  is configured to support various programming models  3203 , middlewares and/or libraries  3202 , and frameworks  3201  that an application  3200  may rely upon. In at least one embodiment, application  3200  may be an AI/ML application implemented using, for example, a deep learning framework such as MXNet, PyTorch, or TensorFlow, which may rely on libraries such as cuDNN, NVIDIA Collective Communications Library (“NCCL”), and/or NVIDA Developer Data Loading Library (“DALI”) CUDA libraries to provide accelerated computing on underlying hardware. 
     In at least one embodiment, programming platform  3204  may be one of a CUDA, ROCm, or OpenCL platform described above in conjunction with  FIG. 29 ,  FIG. 30 , and  FIG. 31 , respectively. In at least one embodiment, programming platform  3204  supports multiple programming models  3203 , which are abstractions of an underlying computing system permitting expressions of algorithms and data structures. Programming models  3203  may expose features of underlying hardware in order to improve performance, in at least one embodiment. In at least one embodiment, programming models  3203  may include, but are not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++ AMP”), Open Multi-Processing (“OpenMP”), Open Accelerators (“OpenACC”), and/or Vulcan Compute. 
     In at least one embodiment, libraries and/or middlewares  3202  provide implementations of abstractions of programming models  3204 . In at least one embodiment, such libraries include data and programming code that may be used by computer programs and leveraged during software development. In at least one embodiment, such middlewares include software that provides services to applications beyond those available from programming platform  3204 . In at least one embodiment, libraries and/or middlewares  3202  may include, but are not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. In addition, in at least one embodiment, libraries and/or middlewares  3202  may include NCCL and ROCm Communication Collectives Library (“RCCL”) libraries providing communication routines for GPUs, a MIOpen library for deep learning acceleration, and/or an Eigen library for linear algebra, matrix and vector operations, geometrical transformations, numerical solvers, and related algorithms. 
     In at least one embodiment, application frameworks  3201  depend on libraries and/or middlewares  3202 . In at least one embodiment, each of application frameworks  3201  is a software framework used to implement a standard structure of application software. Returning to the AI/ML example discussed above, an AI/ML application may be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning frameworks, in at least one embodiment. 
       FIG. 33  illustrates compiling code to execute on one of programming platforms of  FIGS. 28-31 , in accordance with at least one embodiment. In at least one embodiment, a compiler  3301  receives source code  3300  that includes both host code as well as device code. In at least one embodiment, complier  3301  is configured to convert source code  3300  into host executable code  3302  for execution on a host and device executable code  3303  for execution on a device. In at least one embodiment, source code  3300  may either be compiled offline prior to execution of an application, or online during execution of an application. 
     In at least one embodiment, source code  3300  may include code in any programming language supported by compiler  3301 , such as C++, C, Fortran, etc. In at least one embodiment, source code  3300  may be included in a single-source file having a mixture of host code and device code, with locations of device code being indicated therein. In at least one embodiment, a single-source file may be a .cu file that includes CUDA code or a .hip.cpp file that includes HIP code. Alternatively, in at least one embodiment, source code  3300  may include multiple source code files, rather than a single-source file, into which host code and device code are separated. 
     In at least one embodiment, compiler  3301  is configured to compile source code  3300  into host executable code  3302  for execution on a host and device executable code  3303  for execution on a device. In at least one embodiment, compiler  3301  performs operations including parsing source code  3300  into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment in which source code  3300  includes a single-source file, compiler  3301  may separate device code from host code in such a single-source file, compile device code and host code into device executable code  3303  and host executable code  3302 , respectively, and link device executable code  3303  and host executable code  3302  together in a single file, as discussed in greater detail below with respect to  FIG. 34 . 
     In at least one embodiment, host executable code  3302  and device executable code  3303  may be in any suitable format, such as binary code and/or IR code. In the case of CUDA, host executable code  3302  may include native object code and device executable code  3303  may include code in PTX intermediate representation, in at least one embodiment. In the case of ROCm, both host executable code  3302  and device executable code  3303  may include target binary code, in at least one embodiment. 
       FIG. 34  is a more detailed illustration of compiling code to execute on one of programming platforms of  FIGS. 28-31 , in accordance with at least one embodiment. In at least one embodiment, a compiler  3401  is configured to receive source code  3400 , compile source code  3400 , and output an executable file  3410 . In at least one embodiment, source code  3400  is a single-source file, such as a .cu file, a .hip.cpp file, or a file in another format, that includes both host and device code. In at least one embodiment, compiler  3401  may be, but is not limited to, an NVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in .cu files, or a HCC compiler for compiling HIP code in .hip.cpp files. 
     In at least one embodiment, compiler  3401  includes a compiler front end  3402 , a host compiler  3405 , a device compiler  3406 , and a linker  3409 . In at least one embodiment, compiler front end  3402  is configured to separate device code  3404  from host code  3403  in source code  3400 . Device code  3404  is compiled by device compiler  3406  into device executable code  3408 , which as described may include binary code or IR code, in at least one embodiment. Separately, host code  3403  is compiled by host compiler  3405  into host executable code  3407 , in at least one embodiment. For NVCC, host compiler  3405  may be, but is not limited to, a general purpose C/C++ compiler that outputs native object code, while device compiler  3406  may be, but is not limited to, a Low Level Virtual Machine (“LLVM”)-based compiler that forks a LLVM compiler infrastructure and outputs PTX code or binary code, in at least one embodiment. For HCC, both host compiler  3405  and device compiler  3406  may be, but are not limited to, LLVM-based compilers that output target binary code, in at least one embodiment. 
     Subsequent to compiling source code  3400  into host executable code  3407  and device executable code  3408 , linker  3409  links host and device executable code  3407  and  3408  together in executable file  3410 , in at least one embodiment. In at least one embodiment, native object code for a host and PTX or binary code for a device may be linked together in an Executable and Linkable Format (“ELF”) file, which is a container format used to store object code. 
       FIG. 35  illustrates translating source code prior to compiling source code, in accordance with at least one embodiment. In at least one embodiment, source code  3500  is passed through a translation tool  3501 , which translates source code  3500  into translated source code  3502 . In at least one embodiment, a compiler  3503  is used to compile translated source code  3502  into host executable code  3504  and device executable code  3505  in a process that is similar to compilation of source code  3300  by compiler  3301  into host executable code  3302  and device executable  3303 , as discussed above in conjunction with  FIG. 33 . 
     In at least one embodiment, a translation performed by translation tool  3501  is used to port source  3500  for execution in a different environment than that in which it was originally intended to run. In at least one embodiment, translation tool  3501  may include, but is not limited to, a HIP translator that is used to “hipify” CUDA code intended for a CUDA platform into HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, translation of source code  3500  may include parsing source code  3500  and converting calls to API(s) provided by one programming model (e.g., CUDA) into corresponding calls to API(s) provided by another programming model (e.g., HIP), as discussed in greater detail below in conjunction with  FIGS. 36A-37 . Returning to the example of hipifying CUDA code, calls to CUDA runtime API, CUDA driver API, and/or CUDA libraries may be converted to corresponding HIP API calls, in at least one embodiment. In at least one embodiment, automated translations performed by translation tool  3501  may sometimes be incomplete, requiring additional, manual effort to fully port source code  3500 . 
     Configuring GPUS for General-Purpose Computing 
     The following figures set forth, without limitation, exemplary architectures for compiling and executing compute source code, in accordance with at least one embodiment. 
       FIG. 36A  illustrates a system  36 A 00  configured to compile and execute CUDA source code  3610  using different types of processing units, in accordance with at least one embodiment. In at least one embodiment, system  36 A 00  includes, without limitation, CUDA source code  3610 , a CUDA compiler  3650 , host executable code  3670 ( 1 ), host executable code  3670 ( 2 ), CUDA device executable code  3684 , a CPU  3690 , a CUDA-enabled GPU  3694 , a GPU  3692 , a CUDA to HIP translation tool  3620 , HIP source code  3630 , a HIP compiler driver  3640 , an HCC  3660 , and HCC device executable code  3682 . 
     In at least one embodiment, CUDA source code  3610  is a collection of human-readable code in a CUDA programming language. In at least one embodiment, CUDA code is human-readable code in a CUDA programming language. In at least one embodiment, a CUDA programming language is an extension of the C++ programming language that includes, without limitation, mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, device code is source code that, after compilation, is executable in parallel on a device. In at least one embodiment, a device may be a processor that is optimized for parallel instruction processing, such as CUDA-enabled GPU  3690 , GPU  36192 , or another GPGPU, etc. In at least one embodiment, host code is source code that, after compilation, is executable on a host. In at least one embodiment, a host is a processor that is optimized for sequential instruction processing, such as CPU  3690 . 
     In at least one embodiment, CUDA source code  3610  includes, without limitation, any number (including zero) of global functions  3612 , any number (including zero) of device functions  3614 , any number (including zero) of host functions  3616 , and any number (including zero) of host/device functions  3618 . In at least one embodiment, global functions  3612 , device functions  3614 , host functions  3616 , and host/device functions  3618  may be mixed in CUDA source code  3610 . In at least one embodiment, each of global functions  3612  is executable on a device and callable from a host. In at least one embodiment, one or more of global functions  3612  may therefore act as entry points to a device. In at least one embodiment, each of global functions  3612  is a kernel. In at least one embodiment and in a technique known as dynamic parallelism, one or more of global functions  3612  defines a kernel that is executable on a device and callable from such a device. In at least one embodiment, a kernel is executed N (where N is any positive integer) times in parallel by N different threads on a device during execution. 
     In at least one embodiment, each of device functions  3614  is executed on a device and callable from such a device only. In at least one embodiment, each of host functions  3616  is executed on a host and callable from such a host only. In at least one embodiment, each of host/device functions  3616  defines both a host version of a function that is executable on a host and callable from such a host only and a device version of the function that is executable on a device and callable from such a device only. 
     In at least one embodiment, CUDA source code  3610  may also include, without limitation, any number of calls to any number of functions that are defined via a CUDA runtime API  3602 . In at least one embodiment, CUDA runtime API  3602  may include, without limitation, any number of functions that execute on a host to allocate and deallocate device memory, transfer data between host memory and device memory, manage systems with multiple devices, etc. In at least one embodiment, CUDA source code  3610  may also include any number of calls to any number of functions that are specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API that is designed for use by CUDA code. In at least one embodiment, CUDA APIs include, without limitation, CUDA runtime API  3602 , a CUDA driver API, APIs for any number of CUDA libraries, etc. In at least one embodiment and relative to CUDA runtime API  3602 , a CUDA driver API is a lower-level API but provides finer-grained control of a device. In at least one embodiment, examples of CUDA libraries include, without limitation, cuBLAS, cuFFT, cuRAND, cuDNN, etc. 
     In at least one embodiment, CUDA compiler  3650  compiles input CUDA code (e.g., CUDA source code  3610 ) to generate host executable code  3670 ( 1 ) and CUDA device executable code  3684 . In at least one embodiment, CUDA compiler  3650  is NVCC. In at least one embodiment, host executable code  3670 ( 1 ) is a compiled version of host code included in input source code that is executable on CPU  3690 . In at least one embodiment, CPU  3690  may be any processor that is optimized for sequential instruction processing. 
     In at least one embodiment, CUDA device executable code  3684  is a compiled version of device code included in input source code that is executable on CUDA-enabled GPU  3694 . In at least one embodiment, CUDA device executable code  3684  includes, without limitation, binary code. In at least one embodiment, CUDA device executable code  3684  includes, without limitation, IR code, such as PTX code, that is further compiled at runtime into binary code for a specific target device (e.g., CUDA-enabled GPU  3694 ) by a device driver. In at least one embodiment, CUDA-enabled GPU  3694  may be any processor that is optimized for parallel instruction processing and that supports CUDA. In at least one embodiment, CUDA-enabled GPU  3694  is developed by NVIDIA Corporation of Santa Clara, Calif. 
     In at least one embodiment, CUDA to HIP translation tool  3620  is configured to translate CUDA source code  3610  to functionally similar HIP source code  3630 . In a least one embodiment, HIP source code  3630  is a collection of human-readable code in a HIP programming language. In at least one embodiment, HIP code is human-readable code in a HIP programming language. In at least one embodiment, a HIP programming language is an extension of the C++ programming language that includes, without limitation, functionally similar versions of CUDA mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, a HIP programming language may include a subset of functionality of a CUDA programming language. In at least one embodiment, for example, a HIP programming language includes, without limitation, mechanism(s) to define global functions  3612 , but such a HIP programming language may lack support for dynamic parallelism and therefore global functions  3612  defined in HIP code may be callable from a host only. 
     In at least one embodiment, HIP source code  3630  includes, without limitation, any number (including zero) of global functions  3612 , any number (including zero) of device functions  3614 , any number (including zero) of host functions  3616 , and any number (including zero) of host/device functions  3618 . In at least one embodiment, HIP source code  3630  may also include any number of calls to any number of functions that are specified in a HIP runtime API  3632 . In at least one embodiment, HIP runtime API  3632  includes, without limitation, functionally similar versions of a subset of functions included in CUDA runtime API  3602 . In at least one embodiment, HIP source code  3630  may also include any number of calls to any number of functions that are specified in any number of other HIP APIs. In at least one embodiment, a HIP API may be any API that is designed for use by HIP code and/or ROCm. In at least one embodiment, HIP APIs include, without limitation, HIP runtime API  3632 , a HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, etc. 
     In at least one embodiment, CUDA to HIP translation tool  3620  converts each kernel call in CUDA code from a CUDA syntax to a HIP syntax and converts any number of other CUDA calls in CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in a CUDA API, and a HIP call is a call to a function specified in a HIP API. In at least one embodiment, CUDA to HIP translation tool  3620  converts any number of calls to functions specified in CUDA runtime API  3602  to any number of calls to functions specified in HIP runtime API  3632 . 
     In at least one embodiment, CUDA to HIP translation tool  3620  is a tool known as hipify-perl that executes a text-based translation process. In at least one embodiment, CUDA to HIP translation tool  3620  is a tool known as hipify-clang that, relative to hipify-perl, executes a more complex and more robust translation process that involves parsing CUDA code using clang (a compiler front-end) and then translating resulting symbols. In at least one embodiment, properly converting CUDA code to HIP code may require modifications (e.g., manual edits) in addition to those performed by CUDA to HIP translation tool  3620 . 
     In at least one embodiment, HIP compiler driver  3640  is a front end that determines a target device  3646  and then configures a compiler that is compatible with target device  3646  to compile HIP source code  3630 . In at least one embodiment, target device  3646  is a processor that is optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver  3640  may determine target device  3646  in any technically feasible fashion. 
     In at least one embodiment, if target device  3646  is compatible with CUDA (e.g., CUDA-enabled GPU  3694 ), then HIP compiler driver  3640  generates a HIP/NVCC compilation command  3642 . In at least one embodiment and as described in greater detail in conjunction with  FIG. 36B , HIP/NVCC compilation command  3642  configures CUDA compiler  3650  to compile HIP source code  3630  using, without limitation, a HIP to CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to HIP/NVCC compilation command  3642 , CUDA compiler  3650  generates host executable code  3670 ( 1 ) and CUDA device executable code  3684 . 
     In at least one embodiment, if target device  3646  is not compatible with CUDA, then HIP compiler driver  3640  generates a HIP/HCC compilation command  3644 . In at least one embodiment and as described in greater detail in conjunction with  FIG. 36C , HIP/HCC compilation command  3644  configures HCC  3660  to compile HIP source code  3630  using, without limitation, an HCC header and a HIP/HCC runtime library. In at least one embodiment and in response to HIP/HCC compilation command  3644 , HCC  3660  generates host executable code  3670 ( 2 ) and HCC device executable code  3682 . In at least one embodiment, HCC device executable code  3682  is a compiled version of device code included in HIP source code  3630  that is executable on GPU  3692 . In at least one embodiment, GPU  3692  may be any processor that is optimized for parallel instruction processing, is not compatible with CUDA, and is compatible with HCC. In at least one embodiment, GPU  3692  is developed by AMD Corporation of Santa Clara, Calif. In at least one embodiment GPU,  3692  is a non-CUDA-enabled GPU  3692 . 
     For explanatory purposes only, three different flows that may be implemented in at least one embodiment to compile CUDA source code  3610  for execution on CPU  3690  and different devices are depicted in  FIG. 36A . In at least one embodiment, a direct CUDA flow compiles CUDA source code  3610  for execution on CPU  3690  and CUDA-enabled GPU  3694  without translating CUDA source code  3610  to HIP source code  3630 . In at least one embodiment, an indirect CUDA flow translates CUDA source code  3610  to HIP source code  3630  and then compiles HIP source code  3630  for execution on CPU  3690  and CUDA-enabled GPU  3694 . In at least one embodiment, a CUDA/HCC flow translates CUDA source code  3610  to HIP source code  3630  and then compiles HIP source code  3630  for execution on CPU  3690  and GPU  3692 . 
     A direct CUDA flow that may be implemented in at least one embodiment is depicted via dashed lines and a series of bubbles annotated A1-A3. In at least one embodiment and as depicted with bubble annotated A1, CUDA compiler  3650  receives CUDA source code  3610  and a CUDA compile command  3648  that configures CUDA compiler  3650  to compile CUDA source code  3610 . In at least one embodiment, CUDA source code  3610  used in a direct CUDA flow is written in a CUDA programming language that is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment and in response to CUDA compile command  3648 , CUDA compiler  3650  generates host executable code  3670 ( 1 ) and CUDA device executable code  3684  (depicted with bubble annotated A2). In at least one embodiment and as depicted with bubble annotated A3, host executable code  3670 ( 1 ) and CUDA device executable code  3684  may be executed on, respectively, CPU  3690  and CUDA-enabled GPU  3694 . In at least one embodiment, CUDA device executable code  3684  includes, without limitation, binary code. In at least one embodiment, CUDA device executable code  3684  includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime. 
     An indirect CUDA flow that may be implemented in at least one embodiment is depicted via dotted lines and a series of bubbles annotated B1-B6. In at least one embodiment and as depicted with bubble annotated B1, CUDA to HIP translation tool  3620  receives CUDA source code  3610 . In at least one embodiment and as depicted with bubble annotated B2, CUDA to HIP translation tool  3620  translates CUDA source code  3610  to HIP source code  3630 . In at least one embodiment and as depicted with bubble annotated B3, HIP compiler driver  3640  receives HIP source code  3630  and determines that target device  3646  is CUDA-enabled. 
     In at least one embodiment and as depicted with bubble annotated B4, HIP compiler driver  3640  generates HIP/NVCC compilation command  3642  and transmits both HIP/NVCC compilation command  3642  and HIP source code  3630  to CUDA compiler  3650 . In at least one embodiment and as described in greater detail in conjunction with  FIG. 36B , HIP/NVCC compilation command  3642  configures CUDA compiler  3650  to compile HIP source code  3630  using, without limitation, a HIP to CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to HIP/NVCC compilation command  3642 , CUDA compiler  3650  generates host executable code  3670 ( 1 ) and CUDA device executable code  3684  (depicted with bubble annotated B5). In at least one embodiment and as depicted with bubble annotated B6, host executable code  3670 ( 1 ) and CUDA device executable code  3684  may be executed on, respectively, CPU  3690  and CUDA-enabled GPU  3694 . In at least one embodiment, CUDA device executable code  3684  includes, without limitation, binary code. In at least one embodiment, CUDA device executable code  3684  includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime. 
     A CUDA/HCC flow that may be implemented in at least one embodiment is depicted via solid lines and a series of bubbles annotated C1-C6. In at least one embodiment and as depicted with bubble annotated C1, CUDA to HIP translation tool  3620  receives CUDA source code  3610 . In at least one embodiment and as depicted with bubble annotated C2, CUDA to HIP translation tool  3620  translates CUDA source code  3610  to HIP source code  3630 . In at least one embodiment and as depicted with bubble annotated C3, HIP compiler driver  3640  receives HIP source code  3630  and determines that target device  3646  is not CUDA-enabled. 
     In at least one embodiment, HIP compiler driver  3640  generates HIP/HCC compilation command  3644  and transmits both HIP/HCC compilation command  3644  and HIP source code  3630  to HCC  3660  (depicted with bubble annotated C4). In at least one embodiment and as described in greater detail in conjunction with  FIG. 36C , HIP/HCC compilation command  3644  configures HCC  3660  to compile HIP source code  3630  using, without limitation, an HCC header and a HIP/HCC runtime library. In at least one embodiment and in response to HIP/HCC compilation command  3644 , HCC  3660  generates host executable code  3670 ( 2 ) and HCC device executable code  3682  (depicted with bubble annotated C5). In at least one embodiment and as depicted with bubble annotated C6, host executable code  3670 ( 2 ) and HCC device executable code  3682  may be executed on, respectively, CPU  3690  and GPU  3692 . 
     In at least one embodiment, after CUDA source code  3610  is translated to HIP source code  3630 , HIP compiler driver  3640  may subsequently be used to generate executable code for either CUDA-enabled GPU  3694  or GPU  3692  without re-executing CUDA to HIP translation tool  3620 . In at least one embodiment, CUDA to HIP translation tool  3620  translates CUDA source code  3610  to HIP source code  3630  that is then stored in memory. In at least one embodiment, HIP compiler driver  3640  then configures HCC  3660  to generate host executable code  3670 ( 2 ) and HCC device executable code  3682  based on HIP source code  3630 . In at least one embodiment, HIP compiler driver  3640  subsequently configures CUDA compiler  3650  to generate host executable code  3670 ( 1 ) and CUDA device executable code  3684  based on stored HIP source code  3630 . 
       FIG. 36B  illustrates a system  3604  configured to compile and execute CUDA source code  3610  of  FIG. 36A  using CPU  3690  and CUDA-enabled GPU  3694 , in accordance with at least one embodiment. In at least one embodiment, system  3604  includes, without limitation, CUDA source code  3610 , CUDA to HIP translation tool  3620 , HIP source code  3630 , HIP compiler driver  3640 , CUDA compiler  3650 , host executable code  3670 ( 1 ), CUDA device executable code  3684 , CPU  3690 , and CUDA-enabled GPU  3694 . 
     In at least one embodiment and as described previously herein in conjunction with  FIG. 36A , CUDA source code  3610  includes, without limitation, any number (including zero) of global functions  3612 , any number (including zero) of device functions  3614 , any number (including zero) of host functions  3616 , and any number (including zero) of host/device functions  3618 . In at least one embodiment, CUDA source code  3610  also includes, without limitation, any number of calls to any number of functions that are specified in any number of CUDA APIs. 
     In at least one embodiment, CUDA to HIP translation tool  3620  translates CUDA source code  3610  to HIP source code  3630 . In at least one embodiment, CUDA to HIP translation tool  3620  converts each kernel call in CUDA source code  3610  from a CUDA syntax to a HIP syntax and converts any number of other CUDA calls in CUDA source code  3610  to any number of other functionally similar HIP calls. 
     In at least one embodiment, HIP compiler driver  3640  determines that target device  3646  is CUDA-enabled and generates HIP/NVCC compilation command  3642 . In at least one embodiment, HIP compiler driver  3640  then configures CUDA compiler  3650  via HIP/NVCC compilation command  3642  to compile HIP source code  3630 . In at least one embodiment, HIP compiler driver  3640  provides access to a HIP to CUDA translation header  3652  as part of configuring CUDA compiler  3650 . In at least one embodiment, HIP to CUDA translation header  3652  translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs to any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, CUDA compiler  3650  uses HIP to CUDA translation header  3652  in conjunction with a CUDA runtime library  3654  corresponding to CUDA runtime API  3602  to generate host executable code  3670 ( 1 ) and CUDA device executable code  3684 . In at least one embodiment, host executable code  3670 ( 1 ) and CUDA device executable code  3684  may then be executed on, respectively, CPU  3690  and CUDA-enabled GPU  3694 . In at least one embodiment, CUDA device executable code  3684  includes, without limitation, binary code. In at least one embodiment, CUDA device executable code  3684  includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime. 
       FIG. 36C  illustrates a system  3606  configured to compile and execute CUDA source code  3610  of  FIG. 36A  using CPU  3690  and non-CUDA-enabled GPU  3692 , in accordance with at least one embodiment. In at least one embodiment, system  3606  includes, without limitation, CUDA source code  3610 , CUDA to HIP translation tool  3620 , HIP source code  3630 , HIP compiler driver  3640 , HCC  3660 , host executable code  3670 ( 2 ), HCC device executable code  3682 , CPU  3690 , and GPU  3692 . 
     In at least one embodiment and as described previously herein in conjunction with  FIG. 36A , CUDA source code  3610  includes, without limitation, any number (including zero) of global functions  3612 , any number (including zero) of device functions  3614 , any number (including zero) of host functions  3616 , and any number (including zero) of host/device functions  3618 . In at least one embodiment, CUDA source code  3610  also includes, without limitation, any number of calls to any number of functions that are specified in any number of CUDA APIs. 
     In at least one embodiment, CUDA to HIP translation tool  3620  translates CUDA source code  3610  to HIP source code  3630 . In at least one embodiment, CUDA to HIP translation tool  3620  converts each kernel call in CUDA source code  3610  from a CUDA syntax to a HIP syntax and converts any number of other CUDA calls in source code  3610  to any number of other functionally similar HIP calls. 
     In at least one embodiment, HIP compiler driver  3640  subsequently determines that target device  3646  is not CUDA-enabled and generates HIP/HCC compilation command  3644 . In at least one embodiment, HIP compiler driver  3640  then configures HCC  3660  to execute HIP/HCC compilation command  3644  to compile HIP source code  3630 . In at least one embodiment, HIP/HCC compilation command  3644  configures HCC  3660  to use, without limitation, a HIP/HCC runtime library  3658  and an HCC header  3656  to generate host executable code  3670 ( 2 ) and HCC device executable code  3682 . In at least one embodiment, HIP/HCC runtime library  3658  corresponds to HIP runtime API  3632 . In at least one embodiment, HCC header  3656  includes, without limitation, any number and type of interoperability mechanisms for HIP and HCC. In at least one embodiment, host executable code  3670 ( 2 ) and HCC device executable code  3682  may be executed on, respectively, CPU  3690  and GPU  3692 . 
       FIG. 37  illustrates an exemplary kernel translated by CUDA-to-HIP translation tool  3620  of  FIG. 36C , in accordance with at least one embodiment. In at least one embodiment, CUDA source code  3610  partitions an overall problem that a given kernel is designed to solve into relatively coarse sub-problems that can independently be solved using thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads. In at least one embodiment, each sub-problem is partitioned into relatively fine pieces that can be solved cooperatively in parallel by threads within a thread block. In at least one embodiment, threads within a thread block can cooperate by sharing data through shared memory and by synchronizing execution to coordinate memory accesses. 
     In at least one embodiment, CUDA source code  3610  organizes thread blocks associated with a given kernel into a one-dimensional, a two-dimensional, or a three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads, and a grid includes, without limitation, any number of thread blocks. 
     In at least one embodiment, a kernel is a function in device code that is defined using a “_global_” declaration specifier. In at least one embodiment, the dimension of a grid that executes a kernel for a given kernel call and associated streams are specified using a CUDA kernel launch syntax  3710 . In at least one embodiment, CUDA kernel launch syntax  3710  is specified as “KernelName&lt;&lt;&lt;GridSize, BlockSize, SharedMemorySize, Stream&gt;&gt;&gt;(KernelArguments);”. In at least one embodiment, an execution configuration syntax is a “&lt;&lt;&lt; . . . &gt;&gt;&gt;” construct that is inserted between a kernel name (“KernelName”) and a parenthesized list of kernel arguments (“KernelArguments”). In at least one embodiment, CUDA kernel launch syntax  3710  includes, without limitation, a CUDA launch function syntax instead of an execution configuration syntax. 
     In at least one embodiment, “GridSize” is of a type dim3 and specifies the dimension and size of a grid. In at least one embodiment, type dim3 is a CUDA-defined structure that includes, without limitation, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, then z defaults to one. In at least one embodiment, if y is not specified, then y defaults to one. In at least one embodiment, the number of thread blocks in a grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, “BlockSize” is of type dim3 and specifies the dimension and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread that executes a kernel is given a unique thread ID that is accessible within the kernel through a built-in variable (e.g., “threadIdx”). 
     In at least one embodiment and with respect to CUDA kernel launch syntax  3710 , “SharedMemorySize” is an optional argument that specifies a number of bytes in a shared memory that is dynamically allocated per thread block for a given kernel call in addition to statically allocated memory. In at least one embodiment and with respect to CUDA kernel launch syntax  3710 , SharedMemorySize defaults to zero. In at least one embodiment and with respect to CUDA kernel launch syntax  3710 , “Stream” is an optional argument that specifies an associated stream and defaults to zero to specify a default stream. In at least one embodiment, a stream is a sequence of commands (possibly issued by different host threads) that execute in order. In at least one embodiment, different streams may execute commands out of order with respect to one another or concurrently. 
     In at least one embodiment, CUDA source code  3610  includes, without limitation, a kernel definition for an exemplary kernel “MatAdd” and a main function. In at least one embodiment, main function is host code that executes on a host and includes, without limitation, a kernel call that causes kernel MatAdd to execute on a device. In at least one embodiment and as shown, kernel MatAdd adds two matrices A and B of size N×N, where N is a positive integer, and stores the result in a matrix C. In at least one embodiment, main function defines a threadsPerBlock variable as 16 by 16 and a numBlocks variable as N/16 by N/16. In at least one embodiment, main function then specifies kernel call “MatAdd&lt;&lt;&lt;numBlocks, threadsPerBlock&gt;&gt;&gt;(A, B, C);”. In at least one embodiment and as per CUDA kernel launch syntax  3710 , kernel MatAdd is executed using a grid of thread blocks having a dimension N/16 by N/16, where each thread block has a dimension of 16 by 16. In at least one embodiment, each thread block includes 256 threads, a grid is created with enough blocks to have one thread per matrix element, and each thread in such a grid executes kernel MatAdd to perform one pair-wise addition. 
     In at least one embodiment, while translating CUDA source code  3610  to HIP source code  3630 , CUDA to HIP translation tool  3620  translates each kernel call in CUDA source code  3610  from CUDA kernel launch syntax  3710  to a HIP kernel launch syntax  3720  and converts any number of other CUDA calls in source code  3610  to any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax  3720  is specified as “hipLaunchKernelGGL(KernelName,GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);”. In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments has the same meaning in HIP kernel launch syntax  3720  as in CUDA kernel launch syntax  3710  (described previously herein). In at least one embodiment, arguments SharedMemorySize and Stream are required in HIP kernel launch syntax  3720  and are optional in CUDA kernel launch syntax  3710 . 
     In at least one embodiment, a portion of HIP source code  3630  depicted in  FIG. 37  is identical to a portion of CUDA source code  3610  depicted in  FIG. 37  except for a kernel call that causes kernel MatAdd to execute on a device. In at least one embodiment, kernel MatAdd is defined in HIP source code  3630  with the same “_global_” declaration specifier with which kernel MatAdd is defined in CUDA source code  3610 . In at least one embodiment, a kernel call in HIP source code  3630  is “hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);”, while a corresponding kernel call in CUDA source code  3610  is “MatAdd&lt;&lt;&lt;numBlocks, threadsPerBlock&gt;&gt;&gt;(A, B, C);”. 
       FIG. 38  illustrates non-CUDA-enabled GPU  3692  of  FIG. 36C  in greater detail, in accordance with at least one embodiment. In at least one embodiment, GPU  3692  is developed by AMD corporation of Santa Clara. In at least one embodiment, GPU  3692  can be configured to perform compute operations in a highly-parallel fashion. In at least one embodiment, GPU  3692  is configured to execute graphics pipeline operations such as draw commands, pixel operations, geometric computations, and other operations associated with rendering an image to a display. In at least one embodiment, GPU  3692  is configured to execute operations unrelated to graphics. In at least one embodiment, GPU  3692  is configured to execute both operations related to graphics and operations unrelated to graphics. In at least one embodiment, GPU  3692  can be configured to execute device code included in HIP source code  3630 . 
     In at least one embodiment, GPU  3692  includes, without limitation, any number of programmable processing units  3820 , a command processor  3810 , an L2 cache  3822 , memory controllers  3870 , DMA engines  3880 ( 1 ), system memory controllers  3882 , DMA engines  3880 ( 2 ), and GPU controllers  3884 . In at least one embodiment, each programmable processing unit  3820  includes, without limitation, a workload manager  3830  and any number of compute units  3840 . In at least one embodiment, command processor  3810  reads commands from one or more command queues (not shown) and distributes commands to workload managers  3830 . In at least one embodiment, for each programmable processing unit  3820 , associated workload manager  3830  distributes work to compute units  3840  included in programmable processing unit  3820 . In at least one embodiment, each compute unit  3840  may execute any number of thread blocks, but each thread block executes on a single compute unit  3840 . In at least one embodiment, a workgroup is a thread block. 
     In at least one embodiment, each compute unit  3840  includes, without limitation, any number of SIMD units  3850  and a shared memory  3860 . In at least one embodiment, each SIMD unit  3850  implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each SIMD unit  3850  includes, without limitation, a vector ALU  3852  and a vector register file  3854 . In at least one embodiment, each SIMD unit  3850  executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize together and communicate via shared memory  3860 . 
     In at least one embodiment, programmable processing units  3820  are referred to as “shader engines.” In at least one embodiment, each programmable processing unit  3820  includes, without limitation, any amount of dedicated graphics hardware in addition to compute units  3840 . In at least one embodiment, each programmable processing unit  3820  includes, without limitation, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of render back ends, workload manager  3830 , and any number of compute units  3840 . 
     In at least one embodiment, compute units  3840  share L2 cache  3822 . In at least one embodiment, L2 cache  3822  is partitioned. In at least one embodiment, a GPU memory  3890  is accessible by all compute units  3840  in GPU  3692 . In at least one embodiment, memory controllers  3870  and system memory controllers  3882  facilitate data transfers between GPU  3692  and a host, and DMA engines  3880 ( 1 ) enable asynchronous memory transfers between GPU  3692  and such a host. In at least one embodiment, memory controllers  3870  and GPU controllers  3884  facilitate data transfers between GPU  3692  and other GPUs  3692 , and DMA engines  3880 ( 2 ) enable asynchronous memory transfers between GPU  3692  and other GPUs  3692 . 
     In at least one embodiment, GPU  3692  includes, without limitation, any amount and type of system interconnect that facilitates data and control transmissions across any number and type of directly or indirectly linked components that may be internal or external to GPU  3692 . In at least one embodiment, GPU  3692  includes, without limitation, any number and type of I/O interfaces (e.g., PCIe) that are coupled to any number and type of peripheral devices. In at least one embodiment, GPU  3692  may include, without limitation, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU  3692  implements a memory subsystem that includes, without limitation, any amount and type of memory controllers (e.g., memory controllers  3870  and system memory controllers  3882 ) and memory devices (e.g., shared memories  3860 ) that may be dedicated to one component or shared among multiple components. In at least one embodiment, GPU  3692  implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 cache  3822 ) that may each be private to or shared between any number of components (e.g., SIMD units  3850 , compute units  3840 , and programmable processing units  3820 ). 
       FIG. 39  illustrates how threads of an exemplary CUDA grid  3920  are mapped to different compute units  3840  of  FIG. 38 , in accordance with at least one embodiment. In at least one embodiment and for explanatory purposes only, grid  3920  has a GridSize of BX by BY by 1 and a BlockSize of TX by TY by 1. In at least one embodiment, grid  3920  therefore includes, without limitation, (BX*BY) thread blocks  3930  and each thread block  3930  includes, without limitation, (TX*TY) threads  3940 . Threads  3940  are depicted in  FIG. 39  as squiggly arrows. 
     In at least one embodiment, grid  3920  is mapped to programmable processing unit  3820 ( 1 ) that includes, without limitation, compute units  3840 ( 1 )- 3840 (C). In at least one embodiment and as shown, (BJ*BY) thread blocks  3930  are mapped to compute unit  3840 ( 1 ), and the remaining thread blocks  3930  are mapped to compute unit  3840 ( 2 ). In at least one embodiment, each thread block  3930  may include, without limitation, any number of warps, and each warp is mapped to a different SIMD unit  3850  of  FIG. 38 . 
     In at least one embodiment, warps in a given thread block  3930  may synchronize together and communicate through shared memory  3860  included in associated compute unit  3840 . For example and in at least one embodiment, warps in thread block  3930 (BJ,1) can synchronize together and communicate through shared memory  3860 ( 1 ). For example and in at least one embodiment, warps in thread block  3930 (BJ+1,1) can synchronize together and communicate through shared memory  3860 ( 2 ). 
       FIG. 40  illustrates how to migrate existing CUDA code to Data Parallel C++ code, in accordance with at least one embodiment. Data Parallel C++ (DPC++) may refer to an open, standards-based alternative to single-architecture proprietary languages that allows developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and also perform custom tuning for a specific accelerator. DPC++ use similar and/or identical C and C++ constructs in accordance with ISO C++ which developers may be familiar with. DPC++ incorporates standard SYCL from The Khronos Group to support data parallelism and heterogeneous programming. SYCL refers to a cross-platform abstraction layer that builds on underlying concepts, portability and efficiency of OpenCL that enables code for heterogeneous processors to be written in a “single-source” style using standard C++. SYCL may enable single source development where C++ template functions can contain both host and device code to construct complex algorithms that use OpenCL acceleration, and then re-use them throughout their source code on different types of data. 
     In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code which can be deployed across diverse hardware targets. In at least one embodiment, a DPC++ compiler is used to generate DPC++ applications that can be deployed across diverse hardware targets and a DPC++ compatibility tool can be used to migrate CUDA applications to a multiplatform program in DPC++. In at least one embodiment, a DPC++ base tool kit includes a DPC++ compiler to deploy applications across diverse hardware targets; a DPC++ library to increase productivity and performance across CPUs, GPUs, and FPGAs; a DPC++ compatibility tool to migrate CUDA applications to multi-platform applications; and any suitable combination thereof. 
     In at least one embodiment, a DPC++ programming model is utilized to simply one or more aspects relating to programming CPUs and accelerators by using modern C++ features to express parallelism with a programming language called Data Parallel C++. DPC++ programming language may be utilized to code reuse for hosts (e.g., a CPU) and accelerators (e.g., a GPU or FPGA) using a single source language, with execution and memory dependencies being clearly communicated. Mappings within DPC++ code can be used to transition an application to run on a hardware or set of hardware devices that best accelerates a workload. A host may be available to simplify development and debugging of device code, even on platforms that do not have an accelerator available. 
     In at least one embodiment, CUDA source code  4000  is provided as an input to a DPC++ compatibility tool  4002  to generate human readable DPC++  4004 . In at least one embodiment, human readable DPC++  4004  includes inline comments generated by DPC++ compatibility tool  4002  that guides a developer on how and/or where to modify DPC++ code to complete coding and tuning to desired performance  4006 , thereby generating DPC++ source code  4008 . 
     In at least one embodiment, CUDA source code  4000  is or includes a collection of human-readable source code in a CUDA programming language. In at least one embodiment, CUDA source code  4000  is human-readable source code in a CUDA programming language. In at least one embodiment, a CUDA programming language is an extension of the C++ programming language that includes, without limitation, mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, device code is source code that, after compilation, is executable on a device (e.g., GPU or FPGA) and may include or more parallelizable workflows that can be executed on one or more processor cores of a device. In at least one embodiment, a device may be a processor that is optimized for parallel instruction processing, such as CUDA-enabled GPU, GPU, or another GPGPU, etc. In at least one embodiment, host code is source code that, after compilation, is executable on a host. In least one embodiment, some or all of host code and device code can be executed in parallel across a CPU and GPU/FPGA. In at least one embodiment, a host is a processor that is optimized for sequential instruction processing, such as CPU. CUDA source code  4000  described in connection with  FIG. 40  may be in accordance with those discussed elsewhere in this document. 
     In at least one embodiment, DPC++ compatibility tool  4002  refers to an executable tool, program, application, or any other suitable type of tool that is used to facilitate migration of CUDA source code  4000  to DPC++ source code  4008 . In at least one embodiment, DPC++ compatibility tool  4002  is a command-line-based code migration tool available as part of a DPC++ tool kit that is used to port existing CUDA sources to DPC++. In at least one embodiment, DPC++ compatibility tool  4002  converts some or all source code of a CUDA application from CUDA to DPC++ and generates a resulting file that is written at least partially in DPC++, referred to as human readable DPC++  4004 . In at least one embodiment, human readable DPC++  4004  includes comments that are generated by DPC++ compatibility tool  4002  to indicate where user intervention may be necessary. In at least one embodiment, user intervention is necessary when CUDA source code  4000  calls a CUDA API that has no analogous DPC++ API; other examples where user intervention is required are discussed later in greater detail. 
     In at least one embodiment, a workflow for migrating CUDA source code  4000  (e.g., application or portion thereof) includes creating one or more compilation database files; migrating CUDA to DPC++ using a DPC++ compatibility tool  4002 ; completing migration and verifying correctness, thereby generating DPC++ source code  4008 ; and compiling DPC++ source code  4008  with a DPC++ compiler to generate a DPC++ application. In at least one embodiment, a compatibility tool provides a utility that intercepts commands used when Makefile executes and stores them in a compilation database file. In at least one embodiment, a file is stored in JSON format. In at least one embodiment, an intercept-built command converts Makefile command to a DPC compatibility command. 
     In at least one embodiment, intercept-build is a utility script that intercepts a build process to capture compilation options, macro defs, and include paths, and writes this data to a compilation database file. In at least one embodiment, a compilation database file is a JSON file. In at least one embodiment, DPC++ compatibility tool  4002  parses a compilation database and applies options when migrating input sources. In at least one embodiment, use of intercept-build is optional, but highly recommended for Make or CMake based environments. In at least one embodiment, a migration database includes commands, directories, and files: command may include necessary compilation flags; directory may include paths to header files; file may include paths to CUDA files. 
     In at least one embodiment, DPC++ compatibility tool  4002  migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ wherever possible. In at least one embodiment, DPC++ compatibility tool  4002  is available as part of a tool kit. In at least one embodiment, a DPC++ tool kit includes an intercept-build tool. In at least one embodiment, an intercept-built tool creates a compilation database that captures compilation commands to migrate CUDA files. In at least one embodiment, a compilation database generated by an intercept-built tool is used by DPC++ compatibility tool  4002  to migrate CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, DPC++ compatibility tool  4002  generates human readable DPC++  4004  which may be DPC++ code that, as generated by DPC++ compatibility tool  4002 , cannot be compiled by DPC++ compiler and requires additional plumbing for verifying portions of code that were not migrated correctly, and may involve manual intervention, such as by a developer. In at least one embodiment, DPC++ compatibility tool  4002  provides hints or tools embedded in code to help developers manually migrate additional code that could not be migrated automatically. In at least one embodiment, migration is a one-time activity for a source file, project, or application. 
     In at least one embodiment, DPC++ compatibility tool  40002  is able to successfully migrate all portions of CUDA code to DPC++ and there may simply be an optional step for manually verifying and tuning performance of DPC++ source code that was generated. In at least one embodiment, DPC++ compatibility tool  4002  directly generates DPC++ source code  4008  which is compiled by a DPC++ compiler without requiring or utilizing human intervention to modify DPC++ code generated by DPC++ compatibility tool  4002 . In at least one embodiment, DPC++ compatibility tool generates compile-able DPC++ code which can be optionally tuned by a developer for performance, readability, maintainability, other various considerations; or any combination thereof. 
     In at least one embodiment, one or more CUDA source files are migrated to DPC++ source files at least partially using DPC++ compatibility tool  4002 . In at least one embodiment, CUDA source code includes one or more header files which may include CUDA header files. In at least one embodiment, a CUDA source file includes a &lt;cuda.h&gt; header file and a &lt;stdio.h&gt; header file which can be used to print text. In at least one embodiment, a portion of a vector addition kernel CUDA source file may be written as or related to: 
     
       
         
           
               
               
             
               
                   
                   
               
             
            
               
                   
                 #include &lt;cuda.h&gt; 
               
               
                   
                 #include &lt;stdio.h&gt; 
               
               
                   
                 #define VECTOR_SIZE 256 
               
               
                   
                 [ ] global ——  void VectorAddKernel(float* A, float* B, float* C) 
               
               
                   
                 { 
               
               
                   
                  A[threadIdx.x] = threadIdx.x + 1.0f; 
               
               
                   
                  B[threadIdx.x] = threadIdx.x + 1.0f; 
               
               
                   
                  C[threadIdx.x] = A[threadIdx.x] + B[threadIdx.x]; 
               
               
                   
                 } 
               
               
                   
                 int main( ) 
               
               
                   
                 { 
               
               
                   
                  float *d_A, *d_B, *d_C; 
               
               
                   
                  cudaMalloc(&amp;d_A, VECTOR_SIZE*sizeof(float)); 
               
               
                   
                  cudaMalloc(&amp;d_B, VECTOR_SIZE*sizeof(float)); 
               
               
                   
                  cudaMalloc(&amp;d_C, VECTOR_SIZE*sizeof(float)); 
               
               
                   
                  VectorAddKernel&lt;&lt;&lt;1, VECTOR_SIZE&gt;&gt;&gt;(d_A, d_B, d_C); 
               
               
                   
                  float Result[VECTOR_SIZE] = { }; 
               
               
                   
                  cudaMemcpy(Result, d_C, VECTOR_SIZE*sizeof(float), 
               
               
                   
                 cudaMemcpyDeviceToHost); 
               
               
                   
                  cudaFree(d_A); 
               
               
                   
                  cudaFree(d_B); 
               
               
                   
                  cudaFree(d_C); 
               
               
                   
                  for (int i=0; i&lt;VECTOR_SIZE; i++ { 
               
               
                   
                   if (i % 16 == 0) { 
               
               
                   
                    printf(“\n”); 
               
               
                   
                   } 
               
               
                   
                   printf(“%f”, Result[i]); 
               
               
                   
                  } 
               
               
                   
                  return 0; 
               
               
                   
                 } 
               
               
                   
                   
               
            
           
         
       
     
     In at least one embodiment and in connection with CUDA source file presented above, DPC++ compatibility tool  4002  parses a CUDA source code and replaces header files with appropriate DPC++ and SYCL header files. In at least one embodiment, DPC++ header files includes helper declarations. In CUDA, there is a concept of a thread ID and correspondingly, in DPC++ or SYCL, for each element there is a local identifier. 
     In at least one embodiment and in connection with CUDA source file presented above, there are two vectors A and B which are initialized and a vector addition result is put into vector C as part of VectorAddKernel( ). In at least one embodiment, DPC++ compatibility tool  4002  converts CUDA thread IDs used to index work elements to SYCL standard addressing for work elements via a local ID as part of migrating CUDA code to DPC++ code. In at least one embodiment, DPC++ code generated by DPC++ compatibility tool  4002  can be optimized-for example, by reducing dimensionality of an nd_item, thereby increasing memory and/or processor utilization. 
     In at least one embodiment and in connection with CUDA source file presented above, memory allocation is migrated. In at least one embodiment, cudaMalloc( ) is migrated to a unified shared memory SYCL call malloc_device( ) to which a device and context is passed, relying on SYCL concepts such as platform, device, context, and queue. In at least one embodiment, a SYCL platform can have multiple devices (e.g., host and GPU devices); a device may have multiple queues to which jobs can be submitted; each device may have a context; and a context may have multiple devices and manage shared memory objects. 
     In at least one embodiment and in connection with CUDA source file presented above, a main( ) function invokes or calls VectorAddKernel( ) to add two vectors A and B together and store result in vector C. In at least one embodiment, CUDA code to invoke VectorAddKernel( ) is replaced by DPC++ code to submit a kernel to a command queue for execution. In at least one embodiment, a command group handler cgh passes data, synchronization, and computation that is submitted to the queue, parallel_for is called for a number of global elements and a number of work items in that work group where VectorAddKernel( ) is called. 
     In at least one embodiment and in connection with CUDA source file presented above, CUDA calls to copy device memory and then free memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISO C++ code for printing a vector of floating point variables) is migrated as is, without being modified by DPC++ compatibility tool  4002 . In at least one embodiment, DPC++ compatibility tool  4002  modify CUDA APIs for memory setup and/or host calls to execute kernel on the acceleration device. In at least one embodiment and in connection with CUDA source file presented above, a corresponding human readable DPC++  4004  (e.g., which can be compiled) is written as or related to: 
     
       
         
           
               
             
               
                   
               
             
            
               
                 #include &lt;CL/sycl.hpp&gt; 
               
               
                 #include &lt;dpct/dpct.hpp&gt; 
               
               
                 #define VECTOR_SIZE 256 
               
               
                 void VectorAddKernel(float* A, float* B, float* C, 
               
               
                      sycl::nd_item&lt;3&gt; item_ct1) 
               
               
                 { 
               
               
                  A[item_ct1.get_local_id(2)] = item_ct1.get_local_id(2) + 1.0f; 
               
               
                  B[item_ct1.get_local_id(2)] = item_ct1.get_local_id(2) + 1.0f; 
               
               
                  C[item_ct1.get_local_id(2)] = 
               
               
                    A[item_ct1.get_local_id(2)] + B[item_ct1.get_local_id(2)]; 
               
               
                 } 
               
               
                 int main( ) 
               
               
                 { 
               
               
                  float *d_A, *d_B, *d_C; 
               
               
                  d_A = (float *)sycl::malloc_device(VECTOR_SIZE * sizeof(float), 
               
               
                       dpct::get_current_device( ), 
               
               
                       dpct::get_default_context( )); 
               
               
                  d_B = (float *)sycl::malloc_device(VECTOR_SIZE * sizeof(float), 
               
               
                       dpct::get_current_device( ), 
               
               
                       dpct::get_default_context( )); 
               
               
                  d_C = (float *)sycl::malloc_device(VECTOR_SIZE * sizeof(float), 
               
               
                       dpct::get_current_device( ), 
               
               
                       dpct::get_default_context( )); 
               
               
                  dpct::get_default_queue_wait( ).submit([&amp;](sycl::handler &amp;cgh) { 
               
               
                   cgh.parallel_for( 
               
               
                    sycl::nd_range&lt;3&gt;(sycl::range&lt;3&gt;(1, 1, 1) * 
               
               
                        sycl::range&lt;3&gt;(1, 1, VECTOR_SIZE) * 
               
               
                        sycl::range&lt;3&gt;(1, 1, VECTOR_SIZE)), 
               
               
                    [=](sycl::nd_items&lt;3&gt; item_ct1) { 
               
               
                     VectorAddKernel(d_A, d_B, d_C, item_ct1); 
               
               
                    }); 
               
               
                  }); 
               
               
                  float Result[VECTOR_SIZE] = { }; 
               
               
                  dpct::get_default_queue_wait( ) 
               
               
                   .memcpy(Result, d_C, VECTOR_SIZE * sizeof(float)) 
               
               
                   .wait( ); 
               
               
                  sycl::free(d_A, dpct::get_default_context( )); 
               
               
                  sycl::free(d_B, dpct::get_default_context( )); 
               
               
                  sycl::free(d_C, dpct::get_default_context( )); 
               
               
                  for (int i=0; i&lt;VECTOR_SIZE; i++ { 
               
               
                   if (i % 16 == 0) { 
               
               
                     printf(“\n”); 
               
               
                   } 
               
               
                   printf(“%f”, Result[i]); 
               
               
                  } 
               
               
                  return 0; 
               
               
                 } 
               
               
                   
               
            
           
         
       
     
     In at least one embodiment, human readable DPC++  4004  refers to output generated by DPC++ compatibility tool  4002  and may be optimized in one manner or another. In at least one embodiment, human readable DPC++  4004  generated by DPC++ compatibility tool  4002  can be manually edited by a developer after migration to make it more maintainable, performance, or other considerations. In at least one embodiment, DPC++ code generated by DPC++ compatibility tool  40002  such as DPC++ disclosed can be optimized by removing repeat calls to get_current_device( ) and/or get_default_context( ) for each malloc_device( ) call. In at least one embodiment, DPC++ code generated above uses a 3 dimensional nd_range which can be refactored to use only a single dimension, thereby reducing memory usage. In at least one embodiment, a developer can manually edit DPC++ code generated by DPC++ compatibility tool  4002  replace uses of unified shared memory with accessors. In at least one embodiment, DPC++ compatibility tool  4002  has an option to change how it migrates CUDA code to DPC++ code. In at least one embodiment, DPC++ compatibility tool  4002  is verbose because it is using a general template to migrate CUDA code to DPC++ code that works for a large number of cases. 
     In at least one embodiment, a CUDA to DPC++ migration workflow includes steps to: prepare for migration using intercept-build script; perform migration of CUDA projects to DPC++ using DPC++ compatibility tool  4002 ; review and edit migrated source files manually for completion and correctness; and compile final DPC++ code to generate a DPC++ application. In at least one embodiment, manual review of DPC++ source code may be required in one or more scenarios including but not limited to: migrated API does not return error code (CUDA code can return an error code which can then be consumed by the application but SYCL uses exceptions to report errors, and therefore does not use error codes to surface errors); CUDA compute capability dependent logic is not supported by DPC++; statement could not be removed. In at least one embodiment, scenarios in which DPC++ code requires manual intervention may include, without limitation: error code logic replaced with (*,0) code or commented out; equivalent DPC++ API not available; CUDA compute capability-dependent logic; hardware-dependent API (clock( )); missing features unsupported API; execution time measurement logic; handling built-in vector type conflicts; migration of cuBLAS API; and more. 
     Other variations are within spirit of present disclosure. Thus, while disclosed techniques are susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in drawings and have been described above in detail. It should be understood, however, that there is no intention to limit disclosure to specific form or forms disclosed, but on contrary, intention is to cover all modifications, alternative constructions, and equivalents falling within spirit and scope of disclosure, as defined in appended claims. 
     Use of terms “a” and “an” and “the” and similar referents in context of describing disclosed embodiments (especially in context of following claims) are to be construed to cover both singular and plural, unless otherwise indicated herein or clearly contradicted by context, and not as a definition of a term. Terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (meaning “including, but not limited to,”) unless otherwise noted. term “connected,” when unmodified and referring to physical connections, is to be construed as partly or wholly contained within, attached to, or joined together, even if there is something intervening. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within range, unless otherwise indicated herein and each separate value is incorporated into specification as if it were individually recited herein. Use of term “set” (e.g., “a set of items”) or “subset” unless otherwise noted or contradicted by context, is to be construed as a nonempty collection comprising one or more members. Further, unless otherwise noted or contradicted by context, term “subset” of a corresponding set does not necessarily denote a proper subset of corresponding set, but subset and corresponding set may be equal. 
     Conjunctive language, such as phrases of form “at least one of A, B, and C,” or “at least one of A, B and C,” unless specifically stated otherwise or otherwise clearly contradicted by context, is otherwise understood with context as used in general to present that an item, term, etc., may be either A or B or C, or any nonempty subset of set of A and B and C. For instance, in illustrative example of a set having three members, conjunctive phrases “at least one of A, B, and C” and “at least one of A, B and C” refer to any of following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language is not generally intended to imply that certain embodiments require at least one of A, at least one of B and at least one of C each to be present. In addition, unless otherwise noted or contradicted by context, term “plurality” indicates a state of being plural (e.g., “a plurality of items” indicates multiple items). A number of items in a plurality is at least two, but can be more when so indicated either explicitly or by context. Further, unless stated otherwise or otherwise clear from context, phrase “based on” means “based at least in part on” and not “based solely on.” 
     Operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, a process such as those processes described herein (or variations and/or combinations thereof) is performed under control of one or more computer systems configured with executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs or one or more applications) executing collectively on one or more processors, by hardware or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium, for example, in form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transitory signals (e.g., a propagating transient electric or electromagnetic transmission) but includes non-transitory data storage circuitry (e.g., buffers, cache, and queues) within transceivers of transitory signals. In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media having stored thereon executable instructions (or other memory to store executable instructions) that, when executed (i.e., as a result of being executed) by one or more processors of a computer system, cause computer system to perform operations described herein. A set of non-transitory computer-readable storage media, in at least one embodiment, comprises multiple non-transitory computer-readable storage media and one or more of individual non-transitory storage media of multiple non-transitory computer-readable storage media lack all of code while multiple non-transitory computer-readable storage media collectively store all of code. In at least one embodiment, executable instructions are executed such that different instructions are executed by different processors—for example, a non-transitory computer-readable storage medium store instructions and a main central processing unit (“CPU”) executes some of instructions while a graphics processing unit (“GPU”) executes other instructions. In at least one embodiment, different components of a computer system have separate processors and different processors execute different subsets of instructions. 
     Accordingly, in at least one embodiment, computer systems are configured to implement one or more services that singly or collectively perform operations of processes described herein and such computer systems are configured with applicable hardware and/or software that enable performance of operations. Further, a computer system that implements at least one embodiment of present disclosure is a single device and, in another embodiment, is a distributed computer system comprising multiple devices that operate differently such that distributed computer system performs operations described herein and such that a single device does not perform all operations. 
     Use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate embodiments of disclosure and does not pose a limitation on scope of disclosure unless otherwise claimed. No language in specification should be construed as indicating any non-claimed element as essential to practice of disclosure. 
     All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein. 
     In description and claims, terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms may be not intended as synonyms for each other. Rather, in particular examples, “connected” or “coupled” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. 
     Unless specifically stated otherwise, it may be appreciated that throughout specification terms such as “processing,” “computing,” “calculating,” “determining,” or like, refer to action and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities within computing system&#39;s registers and/or memories into other data similarly represented as physical quantities within computing system&#39;s memories, registers or other such information storage, transmission or display devices. 
     In a similar manner, term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory and transform that electronic data into other electronic data that may be stored in registers and/or memory. As non-limiting examples, “processor” may be a CPU or a GPU. A “computing platform” may comprise one or more processors. As used herein, “software” processes may include, for example, software and/or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Also, each process may refer to multiple processes, for carrying out instructions in sequence or in parallel, continuously or intermittently. Terms “system” and “method” are used herein interchangeably insofar as system may embody one or more methods and methods may be considered a system. 
     In present document, references may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. Process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways such as by receiving data as a parameter of a function call or a call to an application programming interface. In some implementations, process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transferring data via a serial or parallel interface. In another implementation, process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transferring data via a computer network from providing entity to acquiring entity. References may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transferring data as an input or output parameter of a function call, a parameter of an application programming interface or interprocess communication mechanism. 
     Although discussion above sets forth example implementations of described techniques, other architectures may be used to implement described functionality, and are intended to be within scope of this disclosure. Furthermore, although specific distributions of responsibilities are defined above for purposes of discussion, various functions and responsibilities might be distributed and divided in different ways, depending on circumstances. 
     Furthermore, although subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that subject matter claimed in appended claims is not necessarily limited to specific features or acts described. Rather, specific features and acts are disclosed as exemplary forms of implementing the claims.