Patent Publication Number: US-2021193594-A1

Title: Stress relief die implementation

Description:
TECHNICAL FIELD 
     Embodiments of the present disclosure relate to semiconductor devices, and more particularly wafer level chip scale packages (WLCSPs) with improved thermal cycling behavior. 
     BACKGROUND 
     With increasing die size of wafer level chip scale packages (WLCSPs), the mechanical robustness decreases. Particularly, the temperature cycling on board (TCoB) performance decreases, especially in the package corner due to the high thermal mismatch between the die and the board. Several solutions have been proposed to mitigate the stress attributable to the mismatch in coefficient of thermal expansion (CTE) between the components. 
     One solution is to use an underfill material around the interconnects between the WLCSP and the board. However, the inclusion of a package underfill requires additional processing steps and, therefore, increases costs. An additional solution is to increase the stand-off height of the interconnects. Such solutions result in an increase in the z-height of the package, which is not desirable in many applications. Yet another solution is to increase the size of the solder resist opening. Increasing the size of the opening reduces the ability to provide narrow and compact routing and, therefore, results in an increase in the package footprint. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a cross-sectional illustration of a WLCSP that comprises a stress relief channel that passes through a thickness of the die, in accordance with an embodiment. 
         FIG. 1B  is a cross-sectional illustration of a WLCSP that comprises a stress relief channel that is formed into the active surface of the die, in accordance with an embodiment. 
         FIG. 1C  is a cross-sectional illustration of a WLCSP that comprises a stress relief channel that is formed into a backside surface of the die, in accordance with an embodiment. 
         FIG. 1D  is a cross-sectional illustration of a WLCSP that comprises a first stress relief channel and a second stress relief channel, in accordance with an embodiment. 
         FIG. 1E  is a cross-sectional illustration of a WLCSP that comprises a first stress relief channel and a second stress relief channel where the two channels are offset from each other, in accordance with an embodiment. 
         FIG. 2A  is a plan view illustration of a WLCSP that comprises a stress relief channel that extends from a first sidewall of the die to a second sidewall of the die, in accordance with an embodiment. 
         FIG. 2B  is a plan view illustration of a WLCSP that comprises a first stress relief channel and a second stress relief channel that intersects the first stress relief channel, in accordance with an embodiment. 
         FIG. 2C  is a plan view illustration of a WLCSP that comprises a first stress relief channel and second stress relief channel, where the first channel and the second channel are filled with different materials, in accordance with an embodiment. 
         FIG. 2D  is a cross-sectional illustration of the WLCSP in  FIG. 2C  where the first stress relief channel and the second stress relief channel are formed into opposite surfaces of the die and do not intersect with each other, in accordance with an embodiment. 
         FIG. 2E  is a cross-sectional illustration of a WLCSP where the first stress relief channel and the second stress relief channel intersect, in accordance with an embodiment. 
         FIG. 2F  is a plan view illustration of a WLCSP that comprises a first stress relief channel and a second stress relief channel, where the two channels are parallel to each other, in accordance with an embodiment. 
         FIG. 2G  is a plan view illustration of a WLCSP that comprises a first stress relief channel with a first stress relief material and a second stress relief channel with a second stress relief material, in accordance with an embodiment. 
         FIG. 2H  is a plan view illustration of a WLCSP that comprises a plurality of stress relief channels, in accordance with an embodiment. 
         FIG. 3  is a cross-sectional illustration of a WLCSP that comprises a component over the backside surface of the die, where the stress relief channel electrically couples the component to the active surface of the die, in accordance with an embodiment. 
         FIG. 4A  is a cross-sectional illustration of a die on a carrier, in accordance with an embodiment. 
         FIG. 4B  is a cross-sectional illustration of the die after a stress relief channel is formed into the die, in accordance with an embodiment. 
         FIG. 4C  is a cross-sectional illustration of the die after a stress relief material is disposed into the channel, in accordance with an embodiment. 
         FIG. 4D  is a cross-sectional illustration of the die after a redistribution layer (RDL) is disposed over the die, in accordance with an embodiment. 
         FIG. 4E  is a cross-sectional illustration of the die after the carrier is removed, in accordance with an embodiment. 
         FIG. 4F  is a cross-sectional illustration of the die after a protection layer is disposed over a backside surface of the die, in accordance with an embodiment. 
         FIG. 5A  is a cross-sectional illustration of a die with a stress relief channel over a carrier, in accordance with an embodiment. 
         FIG. 5B  is a cross-sectional illustration of the die after a mold layer is disposed over the die, in accordance with an embodiment. 
         FIG. 5C  is a cross-sectional illustration of the die after the die is transferred to a second carrier, in accordance with an embodiment. 
         FIG. 5D  is a cross-sectional illustration of the die after an RDL is disposed over the die, in accordance with an embodiment. 
         FIG. 5E  is a cross-sectional illustration of the die after the second carrier is removed, in accordance with an embodiment. 
         FIG. 6A  is a cross-sectional illustration of a die attached to a carrier, in accordance with an embodiment. 
         FIG. 6B  is a cross-sectional illustration of the die after an RDL is disposed over the die, in accordance with an embodiment. 
         FIG. 6C  is a cross-sectional illustration of the die after the die is transferred to a second carrier, in accordance with an embodiment. 
         FIG. 6D  is a cross-sectional illustration of the die after a stress relief channel is formed into the die, in accordance with an embodiment. 
         FIG. 6E  is a cross-sectional illustration of the die after a stress relief material is disposed into the channel, in accordance with an embodiment. 
         FIG. 6F  is a cross-sectional illustration of the die after a backside protection layer is disposed over the die and the second carrier is removed, in accordance with an embodiment. 
         FIG. 7  is a cross-sectional illustration of an electronic system with a WLCSP that comprises a stress relief material, in accordance with an embodiment. 
         FIG. 8  is a schematic of a computing device built in accordance with an embodiment. 
     
    
    
     EMBODIMENTS OF THE PRESENT DISCLOSURE 
     Described herein are wafer level chip scale packages (WLCSPs) with improved thermal cycling behavior, in accordance with various embodiments. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations. 
     Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. 
     As noted above, there is a thermal mismatch between the die of the WLCSP and the board. Typically, the coefficient of thermal expansion (CTE) of the die is between 2-3 ppm and the CTE of the board is between 12-16 ppm. This CTE mismatch between the board and the WLCSP results in poor temperature cycling on board (TCoB) performance. As the footprint of the WLCSP increases, the stresses due to the thermal mismatch are amplified. This leads to reliability issues, particularly at the package corners. Accordingly, embodiments disclosed herein include a stress relief feature in the die of the WLCSP. The stress relief feature has a CTE that is greater than the CTE of the die. Accordingly, the effective CTE of the die is increased to more closely match the CTE of the board. More closely matching the CTE between the die and the board reduces the stress induced in the interconnects and, therefore, improves reliability. 
     Referring now to  FIG. 1A , a cross-sectional illustration of an electronic system  100  is shown, in accordance with an embodiment. In an embodiment, the electronic system comprises a board  105  and a WLCSP  120 . The board  105  may be any suitable board. For example, the board  105  may be a printed circuit board or the like. In an embodiment, the board  105  is electrically coupled to the WLCSP  120  by interconnects  145 . As shown, the interconnects  145  are solder balls, however, it is to be appreciated that any interconnect architecture may be used. 
     In an embodiment, the WLCSP  120  may comprise a die  110  and a redistribution layer (RDL)  140  over the die  110 . The die  110  may comprise an active surface  111  and a backside surface  112 . The active surface  111  may comprise integrated circuitry, transistors, and the like (not shown). The active surface  111  may also comprise back end of line (BEOL) layers (not shown). The RDL  140  is disposed over the active surface  111  of the die  110 . The RDL  140  may comprise conductive routing (e.g., traces, pads, vias, etc.) that electrically couples the integrated circuitry of the active surface  111  to the interconnects  145 . In an embodiment, the die  110  may be any type of die. For example, the die  110  may be a processor die, a graphics processor die, a memory die or the like. In an embodiment, the die  110  comprises silicon and/or any other suitable semiconductor materials. 
     In an embodiment, the WLCSP  120  may further comprise a stress relief channel  131 . In an embodiment, the stress relief channel  131  may pass through a thickness of the die  110 . That is, the stress relief channel  131  may pass from the active surface  111  to the backside surface  112  of the die  110 . In the illustrated embodiment, the stress relief channel  131  includes substantially vertical sidewalls. Such an embodiment may be provided by a mechanical sawing process or the like. Additional embodiments may include a stress relief channel  131  with tapered sidewalls that are typical of a laser drilling process. 
     In an embodiment, the stress relief channel  131  is filled with a stress relief material  130 . The stress relief material  130  comprises a CTE that is greater than a CTE of the die  110 . Accordingly, the effective CTE of the WLCSP  120  is increased in order to more closely match the CTE of the board  105 . Particularly, the effective CTE in the horizontal direction is increased. That is, the increase in the effective CTE allows for the die  110  to expand more laterally as indicated by the arrows extending out from the sidewalls. In an embodiment, the stress relief material  130  may comprise a conductive material. For example, the stress relief material  130  may include copper, silver, or the like. 
     In an embodiment, the stress relief material  130  is electrically isolated from the circuitry of the active surface  111  and the RDL  140 . This is in contrast to a through substrate via (TSV) that would typically be electrically connected to the active surface  111  and/or the RDL  140 . In other embodiments, the stress relief material  130  may be electrically coupled to one or both of the active surface  111  and/or the RDL  140 . Such an embodiment is described in greater detail below with respect to  FIG. 3 . 
     In an embodiment, the increase in the effective CTE is dependent on the thickness T of the stress relief channel  131  and the material chosen for the stress relief material  130 . For example, as the thickness T increases, the effective CTE is increased. In an embodiment, the thickness T may be approximately 10 μm or greater. In a particular embodiment, the thickness T may be between approximately 30 μm and approximately 50 μm. 
     Referring now to  FIG. 1B , a cross-sectional illustration of an electronic system  100  is shown, in accordance with an additional embodiment. In an embodiment, the electronic system  100  may be substantially similar to the electronic system  100  in  FIG. 1A , with the exception that the stress relief channel  131  does not pass entirely through a thickness of the die  110  of the WLCSP  120 . In an embodiment, the stress relief channel  131  is formed into the active surface  111  of the die  110 , but does not pass through to the backside surface  112  of the die. In an embodiment, the channel  131  may have a height H. The height H may be any value less than the total thickness of the die  110 . Embodiments with a stress relief channel  131  that does not pass entirely through a thickness of the die  110  may provide improved mechanical reliability since the die  110  is not completely diced and the left side of the die  110  remains monolithically attached to the right side of the die  110 . 
     Referring now to  FIG. 1C , a cross-sectional illustration of an electronic system  100  is shown, in accordance with an embodiment. In an embodiment, the electronic system  100  may be substantially similar to the electronic system  100  in  FIG. 1B , with the exception that the stress relief channel  131  is formed into the backside surface  112  of the die  110 . Forming the stress relief channel  131  into the backside surface  112  of the die  110  is beneficial because it doesn&#39;t occupy any area on the active surface  111  of the die  110 . 
     Referring now to  FIG. 1D , a cross-sectional illustration of an electronic system  100  is shown, in accordance with an embodiment. In an embodiment, the electronic system  100  may be substantially similar to the electronic system  100  in  FIG. 1B , with the exception that a pair of stress relief channels  131 A and  131 B are formed into the die  110 . In an embodiment, the first stress relief channel  131 A is formed into the active surface  111  and the second stress relief channel  131 B is formed into the backside surface  112  of the die  110 . In an embodiment, the first stress relief channel  131 A is aligned with the second stress relief channel  131 B. In other embodiments, the first stress relief channel  131 A and the second stress relief channel  131 B may be offset from each other. In the illustrated embodiment, the first stress relief material  130 A and the second stress relief material  130 B are shown as being the same material. In other embodiments, the first stress relief material  130 A and the second stress relief material  130 B may be different materials. 
     Referring now to  FIG. 1E , a cross-sectional illustration of an electronic system  100  is shown, in accordance with an embodiment. The electronic system  100  in  FIG. 1E  may be substantially similar to the electronic system  100  in  FIG. 1D , with the exception that the pair of stress relief channels  131 A and  131 B are offset from each other. That is, the pair of stress relief channels  131 A and  131 B may not be aligned with each other in some embodiments. 
     Referring now to  FIG. 2A , a plan view illustration of a WLCSP  220  is shown, in accordance with an embodiment. In an embodiment, the WLCSP  220  may comprise a die  210  and a stress relief channel  231  filled with a stress relief material  230 . In an embodiment, the stress relief channel  231  extends across an entire width of the die  210 . Particularly, the stress relief channel  231  may extend from a first edge  216  to a second edge  217  that is opposite from the first edge  216 . 
     In  FIG. 2A , the plan view illustration depicts a backside surface  212  of the die  210 . The stress relief channel  231  may pass entirely through a thickness of the die  210  (similar to the embodiment shown in  FIG. 1A ) or the stress relief channel  231  may pass partially through the die  210  (similar to the embodiments shown in  FIG. 1C  and  FIG. 1D ). Additionally, similar layouts (in the x-y plane) may be implemented with a stress relief channel  231  that is formed into the active surface (not shown) (similar to the embodiment shown in  FIG. 1B ). 
     Referring now to  FIG. 2B , a plan view illustration of a WLCSP  220  is shown, in accordance with an additional embodiment. In an embodiment, the WLCSP  220  includes a first stress relief channel  231 A and a second stress relief channel  231 B. The first stress relief channel  231 A may extend from a first edge  216  to a second edge  217 , and the second stress relief channel  231 B may extend from a third edge  218  to a fourth edge  219 . 
     In an embodiment, the second stress relief channel  231 B may intersect the first stress relief channel  231 A. For example, the second stress relief channel  231 B may be substantially orthogonal to the first stress relief channel  231 A. Providing stress relief channels  231 A and  231 B at orthogonal angles with respect to each other provides a modified CTE in both the x-direction (i.e., between edge  218  and edge  219 ) and the y-direction (i.e., between edge  216  and edge  217 ). In an embodiment, the first stress relief channel  231 A is filled with a first stress relief material  230 A and the second stress relief channel  231 B is filled with a second stress relief material  230 B. In an embodiment, the first stress relief material  230 A is the same as the second stress relief material  230 B. In other embodiments, the first stress relief material  230 A is different than the second stress relief material  230 B, as shown in  FIG. 2C . 
     Referring now to  FIGS. 2D and 2E , cross-sectional illustrations of a WLCSP  220  are shown, in accordance with various embodiments. The cross-sectional illustrations are along lines  2 - 2 ′ of  FIG. 2C  and illustrate variations in the locations of the first stress relief channel  231 A and the second stress relief channel  231 B. In  FIGS. 2D and 2E , the first stress relief material  230 A and the second stress relief material  230 B are shown as different materials. However, in some embodiments, the first stress relief material  230 A and the second stress relief material  230 B may be the same material. 
     As shown in  FIG. 2D , the first stress relief channel  231 A is formed into the backside surface  212  of the die  210  and the second stress relief channel  231 B is formed into the active surface  211  of the die  210  over the redistribution layer  240 . That is, the first stress relief channel  231 A and the second stress relief channel  231 B may be oriented in different directions without intersecting each other in some embodiments. 
     As shown in  FIG. 2E , the first stress relief channel  231 A and the second stress relief channel  231 B are formed into the backside surface  212  of the die  210 . That is, the first stress relief channel  231 A and the second stress relief channel  231 B may intersect each other in some embodiments. In the illustrated embodiment, the depth of the first stress relief channel  231 A substantially matches a depth of the second stress relief channel  231 B. However, it is to be appreciated that the depths of the first stress relief channel  231 A and the second stress relief channel  231 B may differ from each other in some embodiments. 
     Referring now to  FIG. 2F , a plan view illustration of a WLCSP  220  is shown, in accordance with an additional embodiment. In an embodiment, the WLCSP  220  may comprise a first stress relief channel  231 A and a second stress relief channel  231 B. The first stress relief channel  231 A may be substantially parallel to the second stress relief channel  231 B. Providing a plurality of parallel stress relief channels  231 A and  231 B allows for the effective CTE to be increased without requiring a single wide stress relief channel  231  that may disrupt placement of integrated circuitry of the die  210 . As shown in  FIG. 2G , the first stress relief material  230 A may be different than the second stress relief material  230 B 
     Referring now to  FIG. 2H , a plan view illustration of a WLCSP  220  is shown, in accordance with an additional embodiment. The WLCSP  220  may comprise a plurality of stress relief channels  231 A-D. For example, stress relief channels  231 A and  231 B may extend in a first direction, and stress relief channels  231 C and  231 D may extend in a second direction that is orthogonal to the first direction. In the illustrated embodiment, all of the stress relief materials  230 A-D are the same material. In other embodiments, two or more different materials may be used for the stress relief materials  230 A-D. 
     In addition to providing a modified CTE, the stress relief materials  230 A-D may also provide electrical shielding within the die  210  when the stress relief materials  230 A-D are conductive materials. Electrical shielding may be beneficial in situations where the die  210  includes a plurality of cores or other discrete processing blocks. In such instances, the stress relief materials  230 A-D may minimize or prevent cross-talk between regions of the die  210 . 
     Referring now to  FIG. 3 , a cross-sectional illustration of an electronic system  300  is shown, in accordance with an embodiment. In an embodiment, the electronic system  300  comprises a board  305  and a WLCSP  320 . The board is electrically coupled to the WLCSP  320  by interconnects  345 . In an embodiment, the WLCSP  320  comprises a die  310  and an RDL  340  over the active surface  311  of the die  310 . The WLCSP  320  may also comprise a stress relief channel  331  that extends from the active surface  311  to the backside surface  312 . In an embodiment, an additional component  350  is disposed over a backside surface  312  of the die  310 . The additional component  350  may be electrically coupled to the active surface  311  and/or the RDL  340  by the stress relief material  330  in the stress relief channel  331 . In an embodiment, the additional component  350  may be an active or passive component. For example, the component  350  in  FIG. 3  is a capacitor that comprises a first electrode  351 , a dielectric layer  353 , and a second electrode  352 . 
     Referring now to  FIGS. 4A-4F , a series of cross-sectional illustrations depicting a process for forming a WLCSP is shown, in accordance with an embodiment. 
     Referring now to  FIG. 4A , a cross-sectional illustration of a die  410  on a carrier  481  is shown, in accordance with an embodiment. In an embodiment, the die  410  may be secured to the carrier by an adhesive or the like (not shown). A backside surface  412  of the die  410  faces the carrier  481 , and an active surface  411  of the die  410  faces away from the carrier  481 . 
     Referring now to  FIG. 4B , a cross-sectional illustration of the die  410  after a stress relief channel  431  is formed into the die  410  is shown, in accordance with an embodiment. In an embodiment, the stress relief channel  431  may be formed with a mechanical sawing process, a laser drilling process, or the like. The stress relief channel  431  may be formed into the active surface  411  and pass all the way through the die  410  to the backside surface  412 . However, in some embodiments, the stress relief channel  431  may only pass partially through the thickness of the die  410 . 
     Referring now to  FIG. 4C , a cross-sectional illustration of the die  410  after a stress relief material  430  is disposed into the stress relief channel  431  is shown, in accordance with an embodiment. In an embodiment, the stress relief material  430  is a material that has a CTE that is higher than a CTE of the die  410 . In some embodiments, the stress relief material  430  is a conductive material, such as copper. The stress relief material  430  may be deposited with any suitable process, such as plating, sputtering, or the like. Any overburden of the stress relief material  430  over the active surface  411  may be removed (e.g., with an etching process, a polishing process, or the like). 
     Referring now to  FIG. 4D , a cross-sectional illustration of the die  410  after an RDL  440  is disposed over the active surface  411  is shown, in accordance with an embodiment. In an embodiment, the RDL  440  may comprise any number of layers to provide the needed routing for the WLCSP. For example, two metal layers are shown in  FIG. 4D , but embodiments may include a single metal layer or more than one metal layer. 
     Referring now to  FIG. 4E , a cross-sectional illustration of the die  410  after the carrier  481  is removed is shown, in accordance with an embodiment. The carrier  481  may be removed with any suitable process, and any residual adhesive on the die  410  may be cleared. Accordingly, the backside surface  412  of the die  410  is exposed. In an embodiment, the RDL  440  may be attached to a second carrier  482 . 
     Referring now to  FIG. 4F , a cross-sectional illustration of the die  410  after a backside protection layer  455  is disposed over the die  410  is shown, in accordance with an embodiment. In an embodiment, the backside protection layer  455  is disposed over the exposed backside surface  412  using any suitable deposition process. The backside protection layer  455  may be a polymer or other molding compound. In an embodiment, the second carrier  482  may be removed with any suitable process, and any residual adhesive on the RDL  440  may be removed. 
     Referring now to  FIGS. 5A-5E , a series of cross-sectional illustrations depicting a process for forming a molded WLCSP is shown, in accordance with an embodiment. 
     Referring now to  FIG. 5A , a cross-sectional illustration of a die  510  on a first carrier  581  is shown, in accordance with an embodiment. The die  510  may include an active surface  511  that is facing the carrier  581  and a backside surface  512  that is facing away from the carrier  581 . A stress relief material  530  may fill a channel through the die  510 . The channel and the stress relief material  530  may be formed through the die  510  in substantially the same manner as shown in  FIGS. 4A-4C , except that the die  510  is flipped upside down compared to the die  410 . 
     Referring now to  FIG. 5B , a cross-sectional illustration of the die  510  after a mold layer  550  is disposed over the die  510  is shown, in accordance with an embodiment. The mold layer  550  may be disposed over and in contact with the sidewall surfaces of the die  510  and the backside surface  512  of the die  510 . In an embodiment, the mold layer  550  may also contact a portion of the stress relief material  530 . 
     Referring now to  FIG. 5C , a cross-sectional illustration of the die  510  after the die is transferred from the first carrier  581  to a second carrier  582  is shown, in accordance with an embodiment. In an embodiment, the die  510  is secured to the second carrier  582  so that the active surface  511  faces away from the second carrier  582 . 
     Referring now to  FIG. 5D , a cross-sectional illustration of the die  510  after an RDL  540  is disposed over the active surface  511  of the die  510  is shown, in accordance with an embodiment. In an embodiment, the RDL  540  may comprise any number of layers to provide the needed routing for the WLCSP. For example, two metal layers are shown in  FIG. 5D , but embodiments may include a single metal layer or more than one metal layer. In an embodiment, the RDL  540  may extend past the sidewalls of the die  510 . That is, the RDL  540  may contact the active surface  511  of the die  510  and a portion of the mold layer  550 . 
     Referring now to  FIG. 5E , a cross-sectional illustration of the die  510  after the second carrier  582  is removed is shown, in accordance with an embodiment. The second carrier  582  may be removed with any suitable process, and any residual adhesive may be cleared from the mold layer  550  in some embodiments. 
     In addition to providing a modified CTE, the stress relief materials  530  may also provide electrical shielding within the die  510  when the stress relief materials  530  is conductive. Electrical shielding may be beneficial in situations where the die  510  includes a plurality of cores or other discrete processing blocks. In such instances, the stress relief material  530  may minimize or prevent cross-talk between regions of the die  510 . In some embodiments, the stress relief materials  530  may also be electrically coupled to external shielding over the package. 
     Referring now to  FIGS. 6A-6F , a series of cross-sectional illustrations depicting a process for forming a WLCSP with a backside stress relief channel is shown, in accordance with an embodiment. 
     Referring now to  FIG. 6A , a cross-sectional illustration of a die  610  on a first carrier  681  is shown, in accordance with an embodiment. In an embodiment, the die  610  may be secured to the carrier by an adhesive or the like (not shown). A backside surface  612  of the die  610  faces the first carrier  681 , and an active surface  611  of the die  610  faces away from the first carrier  681 . 
     Referring now to  FIG. 6B , a cross-sectional illustration of the die  610  after an RDL  640  is disposed over the die  610  is shown, in accordance with an embodiment. In an embodiment, the RDL  640  is disposed over the active surface  611  of the die  610 . In an embodiment, the RDL  640  may comprise any number of layers to provide the needed routing for the WLCSP. For example, two metal layers are shown in  FIG. 6B , but embodiments may include a single metal layer or more than one metal layer. 
     Referring now to  FIG. 6C , a cross-sectional illustration of the die  610  after the die  610  is transferred from the first carrier  681  to a second carrier  682  is shown, in accordance with an embodiment. In an embodiment, the die  610  is secured to the second carrier  682  so that the backside surface  612  is exposed. 
     Referring now to  FIG. 6D , a cross-sectional illustration of the die  610  after a stress relief channel  631  is formed into the backside surface  612  of the die is shown, in accordance with an embodiment. In an embodiment, the stress relief channel  631  may be formed with a mechanical sawing process, a laser drilling process, or the like. In the illustrated embodiment, the stress relief channel  631  does not pass through an entire thickness of the die  610 . However, in other embodiments, the stress relief channel  631  may pass from the backside surface  612  to the active surface  611 . 
     Referring now to  FIG. 6E , a cross-sectional illustration of the die  610  after a stress relief material  630  is disposed into the stress relief channel  631  is shown, in accordance with an embodiment. In an embodiment, the stress relief material  630  is a material that has a CTE that is higher than a CTE of the die  610 . In some embodiments, the stress relief material  630  is a conductive material, such as copper. The stress relief material  630  may be deposited with any suitable process, such as plating, sputtering, or the like. Any overburden of the stress relief material  630  over the active surface  611  may be removed (e.g., with an etching process, a polishing process, or the like). 
     Referring now to  FIG. 6F , a cross-sectional illustration of the die  610  after the die  610  is removed from the second carrier  682  and a backside protection layer  655  is disposed over the backside surface  612  is shown, in accordance with an embodiment. The second carrier  682  may be removed with any suitable process, and any residual adhesive on the die  610  may be cleared. In an embodiment, the backside protection layer  655  is disposed over the exposed backside surface  612  using any suitable deposition process. The backside protection layer  655  may be a polymer or other molding compound. The backside protection layer  655  may be disposed before or after removal of the second carrier  682 . 
     Referring now to  FIG. 7 , a cross-sectional illustration of an electronic system  790  is shown, in accordance with an embodiment. In an embodiment, the electronic system  790  may comprise a board  791  and a package substrate  705  attached to the board  791  by interconnects  792 . Interconnects  792  are illustrated as solder balls, but it is to be appreciated that embodiments may include any suitable interconnect architecture. In an embodiment, a WLCSP  720  is attached to the package substrate  705  by interconnects  745 . 
     In an embodiment, the WLCSP  720  may be similar to any of the WLCSPs described in greater detail above. For example, the WLCSP  720  illustrated in  FIG. 7  is substantially similar to the WLCSP  120  described above with respect to  FIG. 1A . For example, the WLCSP  720  comprises a die  710 , an RDL  740  over the die  710 , and a stress relief material  730  that is in a stress relief channel  731  that extends through a thickness of the die  710 . In other embodiments, the stress relief channel  731  may extend partially through a thickness of the die  710 . In yet another embodiment, there may be a plurality of stress relief channels  731 , each filled with stress relief material  730 . 
       FIG. 8  illustrates a computing device  800  in accordance with one implementation of the invention. The computing device  800  houses a board  802 . The board  802  may include a number of components, including but not limited to a processor  804  and at least one communication chip  806 . The processor  804  is physically and electrically coupled to the board  802 . In some implementations the at least one communication chip  806  is also physically and electrically coupled to the board  802 . In further implementations, the communication chip  806  is part of the processor  804 . 
     These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). 
     The communication chip  806  enables wireless communications for the transfer of data to and from the computing device  800 . The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip  806  may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device  800  may include a plurality of communication chips  806 . For instance, a first communication chip  806  may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip  806  may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. 
     The processor  804  of the computing device  800  includes an integrated circuit die packaged within the processor  804 . In some implementations of the invention, the integrated circuit die of the processor  804  may be a WLCSP with a stress relief channel that is filled by a stress relief material, in accordance with embodiments described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. 
     The communication chip  806  also includes an integrated circuit die packaged within the communication chip  806 . In accordance with another implementation of the invention, the integrated circuit die of the communication chip  806  may be WLCSP with a stress relief channel that is filled by a stress relief material, in accordance with embodiments described herein. 
     The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. 
     These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. 
     Example 1: a wafer level chip scale package (WLCSP), comprising: a die, wherein the die comprises an active surface and a backside surface, and wherein the die has a first coefficient of thermal expansion (CTE); and a channel into the die, wherein the channel is filled with a stress relief material, wherein the stress relief material has a second CTE that is greater than the first CTE. 
     Example 2: the WLCSP of Example 1, wherein the channel extends from a first edge of the die to a second edge of the die. 
     Example 3: the WLCSP of Example 1 or Example 2, wherein the channel extends through an entire thickness between the active surface and the backside surface of the die. 
     Example 4: the WLCSP of Example 3, wherein the stress relief material is a conductive material. 
     Example 5: the WLCSP of Example 4, further comprising: a component over the backside surface of the die, wherein the component is electrically coupled to the active surface of the die by the stress relief material. 
     Example 6: the WLCSP of Example 5, wherein the component is a capacitor. 
     Example 7: the WLCSP of Examples 1-6, wherein the channel is disposed into the backside surface of the die. 
     Example 8: the WLCSP of Examples 1-6, wherein the channel is disposed into the active surface of the die. 
     Example 9: the WLCSP of Examples 1-7, further comprising: a plurality of channels into the die. 
     Example 10: the WLCSP of Example 9, wherein the plurality of channels comprises a first channel and a second channel. 
     Example 11: the WLCSP of Example 10, wherein the first channel is parallel to the second channel. 
     Example 12: the WLCSP of Example 10, wherein the first channel intersects the second channel. 
     Example 13: the WLCSP of Examples 10-12, wherein the first channel comprises a first stress relief material and the second channel comprises a second stress relief material that is different than the first stress relief material. 
     Example 14: the WLCSP of Examples 10-13, wherein the first channel is disposed into the active surface of the die, and wherein the second channel is disposed into the backside surface of the die. 
     Example 15: the WLCSP of Examples 1-13, further comprising: a mold layer over the backside surface and sidewalls of the die. 
     Example 16: a method of forming a wafer level chip scale package (WLCSP), comprising: providing a die with an active surface and a backside surface on a carrier, wherein the die has a first coefficient of thermal expansion (CTE); forming a channel into the die; filling the channel with a stress relief material, wherein the stress relief material has a second CTE that is larger than the first CTE; and forming a redistribution layer (RDL) over the active surface of the die. 
     Example 17: the method of Example 16, wherein the active surface faces away from the carrier. 
     Example 18: the method of Example 17, wherein the channel is formed into the active surface. 
     Example 19: the method of Example 17 or Example 18, wherein the RDL is disposed over the active surface before forming the channel. 
     Example 20: the method of Example 19, further comprising: transferring the die to a second carrier after the RDL is formed, wherein the active surface faces the second carrier, and wherein the channel is formed into the backside surface of the die. 
     Example 21: the method of Examples 16-20, wherein the active surface faces the carrier, and wherein the channel is formed into the backside surface of the die. 
     Example 22: the method of Example 21, further comprising: forming a mold layer over the die after filling the channel with the stress relief material, wherein the mold layer is over the backside surface and sidewalls of the die; and transferring the die to a second carrier before forming the RDL, wherein the active surface of the die faces away from the second carrier. 
     Example 23: an electronic system, comprising: a board; and a wafer level chip scale package (WLCSP) coupled to the board by interconnects, wherein the WLCSP comprises: a die; a redistribution layer over the die; and a stress relief channel disposed into a surface of the die. 
     Example 24: the electronic system of Example 23, wherein the stress relief channel passes through an entire thickness of the die. 
     Example 25: the electronic system of Example 23 or Example 24, further comprising: a component over a backside surface of the die, wherein the component is electrically coupled to an active surface of the die by the stress relief channel.