Patent Publication Number: US-2018049327-A1

Title: Printed wiring board

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2016-156368, filed Aug. 9, 2016, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a printed wiring board with a built-in electronic component. 
     Description of Background Art 
     Japanese Patent Laid-Open Publication No. 2007-150002 describes a substrate with a built-in IC. The entire contents of this publication are incorporated herein by reference. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, a printed wiring board includes a central resin insulating layer, an electronic component embedded in the central resin insulating layer, a first resin insulating layer formed on a first surface side of the central resin insulating layer, a second resin insulating layer formed on a second surface side of the central resin insulating layer on the opposite side with respect to the first surface side, via conductors Ruined in the central resin insulating layer such that the via conductors are formed toward the first surface side, and metal posts formed in the central resin insulating layer such that the metal posts are formed toward the second surface side. The central resin insulating layer does not contain a core material, and the via conductors include a group of via conductors connected with the metal posts respectively such that a via conductor and a respective metal post connected to the via conductor is connecting a first surface of the central resin insulating layer and a second surface of the central resin insulating layer on the opposite side. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
         FIGS. 1A and 1B  are cross-sectional views of a printed wiring board according to an embodiment of the present invention; 
         FIG. 1C  is a cross-sectional view of a printed wiring board according to a first modified example of the embodiment; 
         FIG. 1D  is a cross-sectional view of a printed wiring board according to a second modified example of the embodiment; 
         FIG. 2A-2E  are manufacturing process diagrams of the printed wiring board of the embodiment; 
         FIG. 3A-3D  are manufacturing process diagrams of the printed wiring board of the embodiment; 
         FIG. 4A-4D  are manufacturing process diagrams of the printed wiring board of the embodiment; and 
         FIG. 5A-5D  are manufacturing process diagrams of the printed wiring board of the embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings. 
     Embodiment 
       FIG. 1A  is a cross-sectional view of a printed wiring board of an embodiment. 
     A printed wiring board  10  of the embodiment includes three resin insulating layers: a central resin insulating layer  30  that has a first surface (F) on a side where an IC chip is mounted and a second surface (S) that is on an opposite side of the first surface, and accommodates an electronic component  90  such as an IC; a first resin insulating layer  50  that is formed on the first surface side of the central resin insulating layer; and a second resin insulating layer  150  that is formed on the second surface side of the central resin insulating layer. A first conductor layer ( 34 F) is formed on the first surface of the central resin insulating layer and a second conductor layer ( 34 S) is formed on the second surface of the central resin insulating layer. An uppermost conductor layer  58  is formed on the first resin insulating layer  50 . A lowermost conductor layer  158  is formed on the second resin insulating layer  150 . The printed wiring board includes four conductor layers, which are the first conductor layer ( 34 F), the second conductor layer ( 34 S), the uppermost conductor layer  58 , and the lowermost conductor layer  158 . Via conductors  36  are formed on the first surface (F) side of the central resin insulating layer  30 , and metal posts  28  are formed on the second surface (S) side of the central resin insulating layer  30 . The metal posts  28  are connected to the second conductor layer ( 34 S) on the second surface side of the central resin insulating layer  30 . The via conductors  36  include main via conductors ( 36 A) that are respectively connected to the metal posts  28  and sub via conductors ( 36 B) that are respectively connected to terminals  92  of the electronic component  90 . The second conductor layer ( 34 S) includes a second main conductor circuit ( 34 SA) that is connected to the metal posts  28  and a second sub conductor circuit ( 34 SB) on which the electronic component is mounted. The electronic component  90  is fixed to the second sub conductor circuit ( 34 SB) via an adhesive layer  98 . The first conductor layer ( 34 F) on the first surface side of the central resin insulating layer  30  and the second main conductor circuit ( 34 SA) on the second surface side of the central resin insulating layer  30  are connected to each other via the main via conductors ( 36 A) and the metal posts  28 . The first conductor layer ( 34 F) and the uppermost conductor layer  58  are connected to each other via via conductors  60  formed in the first resin insulating layer  50 . The second conductor layer ( 34 S) and the lowermost conductor layer  158  are connected to each other via via conductors  160  formed in the second resin insulating layer  150 . A solder resist layer ( 70 F) is formed on the first resin insulating layer  50  and the uppermost conductor layer  58 . Solder bumps ( 76 F) for mounting an electronic component such as an IC chip are formed in openings ( 71 F) of the solder resist layer ( 70 F). A solder resist layer ( 70 S) is formed on the second resin insulating layer  150  and the lowermost conductor layer  158 . Solder bumps ( 76 S) for connecting an external substrate such as a motherboard are formed in openings ( 71 S) of the soldier resist layer ( 70 S). 
       FIG. 1B  illustrates an application example  110  of the printed wiring board of the embodiment. 
     An IC chip  190  is mounted on the upper solder bumps ( 76 F). The application example  110  is mounted on a motherboard  194  via lower solder bumps ( 76 S). 
     A diameter (R 1 ) of each of the metal posts  28  is 50-200 μm. A bottom diameter (R 2 ) of each of the main via conductors ( 36 A) is 30-170 μm. The diameter (R 1 ) of each of the metal posts  28  is desirably at least twice as large as the bottom diameter (R 2 ) of each of the main via conductors ( 36 A). This increases connection reliability between the main via conductors and the metal posts  28 . 
     A height difference (d) between upper surfaces of the metal posts  28  and upper surfaces of the terminals  92  of the IC chip  90  is within 20 μm. Therefore, a difference between a depth (height) (TA) of each of the main via conductors ( 36 A) connected to the metal posts  28  and a depth (height) (TB) of each of the sub via conductors ( 36 B) connected to the terminals  92  of the IC chip is within  20  p.m. That is, a height difference between the main via conductors ( 36 A) and the sub via conductors ( 36 B) is small. Therefore, the main via conductors ( 36 A) and the sub via conductors ( 36 B) can be simultaneously formed with high reliability. 
     In the printed wiring board of the embodiment, the first surface (F) and the second surface (S) of the thick central resin insulating layer  30  with the built-in electronic component are connected to each other via the main via conductors ( 36 A) and the metal posts  28 . Therefore, since the depth of each of the main via conductors ( 36 A) is small, a void or the like becomes less likely to occur, and connection reliability of the main via conductors ( 36 A) is improved. 
     In the printed wiring board of the embodiment, the central resin insulating layer  30  and the first resin insulating layer  50  each do not contain a core material and are each formed from a resin containing inorganic particles. The second resin insulating layer  150  is formed by curing a prepreg obtained by impregnating a core material such as a glass cloth with an insulating resin containing inorganic particles. Only one layer, the second resin insulating layer  150 , contains a core material that causes an increase in layer thickness. Therefore, the thickness of the printed wiring board can be reduced. Here, in the printed wiring board, a conductor layer on the IC chip mounting side has a higher wiring density than a conductor layer on the external substrate side (wirings spread downward). Here, a thin layer that does not contain a core material is arranged on the first resin insulating layer on the IC chip mounting side. Therefore, high integration of the printed wiring board can be achieved. 
     Manufacturing Method of Embodiment 
     A method for manufacturing the printed wiring board of the embodiment is illustrated in  FIG. 2A-5D . 
     A resin substrate  20  on which a carrier copper foil  21  is laminated is prepared, and a support plate ( 20   z ) obtained by affixing an ultra-thin copper foil  22  on the carrier copper foil  21  is prepared ( FIG. 2A ). A plating resist  84  of a predetermined pattern is formed on the ultra-thin copper foil  22  of the support plate ( 20   z ) ( FIG. 2B ). An electrolytic copper plating film  85  that forms the second conductor layer ( 34 S) is formed in a non-forming portion of the plating resist by electrolytic copper plating ( FIG. 2C ). 
     The plating resist is peeled off. A second plating resist  80  having openings ( 80   a ) for forming the metal posts is formed ( FIG. 2D ). An electrolytic plating film  82  for forming the metal posts is formed in the openings ( 80   a ) ( FIG. 2E ). The second plating resist is peeled off, and the metal posts  28  are exposed ( FIG. 3A ). The electronic component  90  is fixed on the second sub conductor circuit ( 34 SB) via the adhesive layer  98  ( FIG. 3B ). 
     The central resin insulating layer  30  is formed on the support plate ( 20   z ) on which the metal posts  28  are formed and the electronic component is fixed ( FIG. 3C ). The central resin insulating layer  30  is formed from a resin that does not contain a core material but contains particles. Examples of the resin include an epoxy resin, a BT (bismaleimide triazine) resin, and the like. The particles include inorganic particles such as silica particles and thermosetting resin particles such as epoxy particles. Openings ( 31 A) for the via conductors reaching the metal posts  28  and openings ( 31 B) reaching the terminals  92  of the electronic component are formed in the central resin insulating layer  30  using CO2 gas laser ( FIG. 3D ). An electroless copper plating film  52  is formed on the resin insulating layer  30  and on inner walls of the openings ( 31 A,  31 B), and a plating resist  54  is formed on the electroless copper plating film  52  ( FIG. 4A ). An electrolytic copper plating film  56  is formed on the electroless copper plating film  52  exposed from the plating resist  54 . In this case, the openings ( 31 A,  31 B) are filled with the electrolytic copper plating film  56 . The main via conductors ( 36 A) connected to the metal posts  28  are formed in the openings ( 31 A), and the sub via conductors ( 36 B) connected to the terminals  92  of the electronic component  90  are formed in the openings ( 31 B) ( FIG. 4B ). As described above, the difference between the depth (height) of each of the main via conductors ( 36 A) connected to the metal posts  28  and the depth (height) (TB) of each of the sub via conductors ( 36 B) connected to the terminals  92  of the IC chip is small. Therefore, the main via conductors ( 36 A) and the sub via conductors ( 36 B) can be simultaneously formed with high reliability. 
     The plating resist is removed ( FIG. 4C ). After the carrier copper foil  21  and the ultra-thin copper foil  22  of the support plate ( 20   z ) are mechanically separated, the ultra-thin copper foil  22  is peeled off by etching, and, at the same time, the electroless copper plating film  52  exposed from the electrolytic copper plating film  56  is removed. An intermediate substrate ( 30   z ) including the central resin insulating layer  30 , the first conductor layer ( 34 F), the second conductor layer ( 34 S), the via conductors  36 , and the metal posts  28  is completed ( FIG. 4D ). The central resin insulating layer  30  has the first surface (F) on an upper side and the second surface (S) on an opposite side of the first surface. The first resin insulating layer  50  formed from a resin that does not contain a core material but contain particles is laminated on the first surface (F) side of the central resin insulating layer  30 , and the second resin insulating layer  150  formed from a resin that contains a core material (reinforcing material) and particles is laminated on the second surface (S) side of the central resin insulating layer  30  ( FIG. 5A ). The second resin insulating layer  150  is formed of a resin and a reinforcing material. Examples of the reinforcing material include a glass cloth, aramid fiber, glass fiber, and the like. A prepreg can be used for the second resin insulating layer  150 . 
     Using laser, openings  51  reaching the first conductor layer ( 34 F) are formed in the first resin insulating layer  50 , and openings  151  reaching the second conductor layer ( 34 S) are formed in the second resin insulating layer  150  ( FIG. 5B ). 
     An electroless plating film is formed on the first resin insulating layer  50  and the second resin insulating layer  150 . A plating resist is formed. An electrolytic plating film is formed in a non-forming portion of the plating resist. After the plating resist is peeled off, the electroless plating film in a non-forming portion of the electrolytic plating film is removed. The via conductors  60  and the uppermost conductor layer  58  are formed in or on the first resin insulating layer  50 . The via conductors  160  and the lowermost conductor layers  158  are formed in or on the second resin insulating layer  150  ( FIG. 5C ). 
     The upper side solder resist layer ( 70 F) having the openings ( 71 F) is formed on the first resin insulating layer  50 , and the lower side solder resist layer ( 70 S) having the openings ( 71 S) is formed on the second resin insulating layer  150 . Upper surfaces of pads ( 73 F) are respectively exposed from the openings ( 71 F) of the upper side solder resist layer ( 70 F). On the other hand, upper surfaces of portions of the lowermost conductor layer  158  that are respectively exposed from the openings ( 71 S) of the lower side solder resist layer ( 70 S) function as pads ( 73 S) for connecting to a motherboard. 
     A nickel plating layer is formed on each of the pads ( 73 F,  73 S). Further, a gold plating layer is formed on the nickel plating layer. A metal film  72  including the nickel plating layer and the gold plating layer is formed. Instead of the nickel-gold layer, it is also possible that a nickel-palladium-gold layer or an OSP film is formed. Solder balls are respectively mounted on the pads ( 73 F,  73 S), and the solder bumps ( 76 F,  76 S) are formed by reflow. The printed wiring board  10  is completed ( FIG. 1A ). 
     The electronic component  190  such as an IC chip is mounted via the solder bumps ( 76 F) of the printed wiring board  10 , and the application example  110  is completed. The application example  110  is mounted on the external substrate  194  such as a motherboard via the solder bumps ( 76 S) ( FIG. 1B ). 
     First Modified Example of Embodiment 
       FIG. 1C  is a cross-sectional view of a printed wiring board according to a first modified example of the embodiment. 
     In the first modified example of the embodiment, the second resin insulating layer  150  containing a core material is formed on the first surface (F) side of the central resin insulating layer  30 , and the first resin insulating layer  50  that does not contain a core material is formed on the second surface (S) side of the central resin insulating layer  30 . In the printed wiring board of the first modified example of the embodiment, only one resin insulating layer contains a core material. Therefore, the thickness of the printed wiring board can be reduced. 
     Second Modified Example of Embodiment 
       FIG. 1D  is a cross-sectional view of a printed wiring board according to a second modified example of the embodiment. 
     In the second modified example of the embodiment, the central resin insulating layer  30  includes two layers, a lower resin insulating layer ( 30 A) and an upper resin insulating layer ( 30 B). The lower resin insulating layer ( 30 A) and the upper resin insulating layer ( 30 B) do not contain a core material, but have different content rates of inorganic particles and have different thermal expansion coefficients. That is, the upper resin insulating layer ( 30 B) has a higher content rate (w %) of inorganic particles and a lower thermal expansion coefficient than the lower resin insulating layer ( 30 A). This relaxes a stress due to a difference in thermal expansion between the first resin insulating layer  50 , which does not contain a core material and has a high thermal expansion coefficient, and the second resin insulating layer  150 , which contains a core material and has a low thermal expansion coefficient, and reduces warpage of the printed wiring board. 
     Japanese Patent Laid-Open Publication No. 2007-150002 describes a substrate with a built-in IC, and the substrate has a structure in which the IC is embedded in a resin layer that does not contain a core material, and the resin layer is sandwiched between two front and back core layers that each contain a core material. 
     In Japanese Patent Laid-Open Publication No. 2007-150002, a thickness of the resin layer in which the IC is embedded is likely to increase. When the thickness of the resin layer increases, a depth of a via conductor penetrating the resin layer increases. Here, when the depth of the via conductor increases, a void or the like is likely to occur and connection reliability is likely to decrease. 
     A printed wiring board according to an embodiment of the present invention includes: a central resin insulating layer that has a first surface and a second surface (that is on the opposite side of the first surface) and does not contain a core material, an electronic component being embedded in the central resin insulating layer; a first resin insulating layer that is formed on the first surface side of the central resin insulating layer; a second resin insulating layer that is formed on the second surface side of the central resin insulating layer; and a via conductor that is formed in the central resin insulating layer. A metal post is formed in the central resin insulating layer. The first surface and the second surface of the central resin insulating layer are connected to each other via the via conductor and the metal post. 
     According to an embodiment of the present invention, the first surface and the second surface of the thick central resin insulating layer accommodating an electronic component are connected to each other via the via conductor and the metal post. Therefore, since the depth of the via conductor is small, a void or the like becomes less likely to occur, and connection reliability of the via conductor is improved. 
     Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.