Patent Publication Number: US-11031916-B2

Title: Circuit with wide range input common mode voltage operation

Description:
CROSS REFERENCE TO RELATED APPLICATION(S) 
     This continuation application claims priority to U.S. patent application Ser. No. 15/940,812, filed Mar. 29, 2018, which application is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     With the increasing speed of clocking circuits such as clock buffers, phase-lock loops, and clock generators, the performance of input stages within integrated circuits has become a factor in the overall performance of the integrated circuit. 
     SUMMARY 
     In one example, a circuit includes a first transistor including a first control input and first and second current terminals and a second transistor including a second control input and third and fourth current terminals, wherein the fourth current terminal is connected to the second current terminal. A third transistor includes a third control input and fifth and sixth current terminals, wherein the sixth current terminal is connected to the first current terminal and the third control input is connected to the first control input at a first input node of the circuit. A fourth transistor includes a fourth control input and seventh and eighth current terminals, wherein the eighth current terminal is connected to the third current terminal at an output node of the circuit and the fourth control input is connected to the second control input at a second input node of the circuit. A first current source transistor is connected to the second and fourth current terminals. A second current source transistor is connected to the fifth and seventh current terminals. A fifth transistor includes a fifth control input and ninth and tenth current terminals, wherein the fifth control input is connected to the first input node of the circuit. A first resistor is connected to the tenth current terminal. A second resistor is connected to the eighth current terminal at the output node and to the first resistor. 
     In another example, a circuit includes a first common mode amplifier including a first input, a second input, and a first output. The first common mode amplifier comprises a first plurality of self-biased differential amplifiers. The circuit also includes a second common mode amplifier including a third input, a fourth input, and a second output, The third input is connected to the second input and the fourth input is connected to the first input. The second common amplifier comprises a second plurality of self-biased differential amplifiers. The circuit further includes a first gain amplifier including a fifth input and a sixth input and a second gain amplifier including a seventh input and an eighth input. The first output is connected to the fifth and eight inputs and the second output is connected to the sixth and seventh inputs. 
     In yet another example, a circuit includes a first transistor comprising a first control input and first and second current terminals and a second transistor including a second control input and third and fourth current terminals, wherein the third current terminal is connected to the first current terminal. A first current source transistor is included that comprises a third control input and fifth and sixth current terminals, wherein the sixth current terminal is connected to the first and third current terminals. A first resistor is connected to the second current terminal. A second resistor is connected to the first resistor and, at an output node, to the fourth current terminal. A second current source transistor includes a fourth control input and seventh and eighth current terminals. The seventh current terminal is connected to the first and second resistors. The third and fourth control inputs are connected together and to the second terminal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a detailed description of various examples, reference will now be made to the accompanying drawings in which: 
         FIG. 1  illustrates an example of an amplifier circuit. 
         FIG. 2  illustrates another example of an amplifier circuit. 
         FIG. 3  illustrates a system that includes multiple wide input common mode amplifiers. 
         FIG. 4  shows an example of a wide input common mode amplifier. 
     
    
    
     DETAILED DESCRIPTION 
     Various circuits are disclosed that are usable as input stages for integrated circuits. The circuits comprise amplifiers. The input signals to the illustrative amplifiers comprise differential time-varying inputs that include a common mode (CM) signal component. The input signals fluctuate over time with respect to the CM signal level. The CM signal level is between the voltages supplying power to the amplifiers (e.g., ground and VDD). One of the illustrative amplifiers operates when the input common mode (ICM) voltage level is at a lower level closer to the lower power supply voltage (e.g., ground). Another illustrative amplifier operates when the ICM voltage level is at a higher level closer to the higher power supply voltage (e.g., VDD). Yet another amplifier is designed for operation across a wide range of ICM voltage levels from close to the lower supply voltage (e.g., ground) to close to the higher power supply voltage (VDD). This latter amplifier is referred to herein as a wide input common mode amplifier (WICMA). The power supply voltages are referred to herein as ground and VDD. 
       FIG. 1  illustrates an amplifier circuit that operates particularly well for ICM voltage levels that are closer to ground than the VDD. The illustrative amplifier circuit of  FIG. 1  includes transistors M 1 , M 2 , MCS 1 , MCS 2 , and resistors R 1  and R 2 . In this example, M 1 , M 2 , and MCS 2  are p-type metal oxide semiconductor field effect (PMOS) transistors and MCS 1  is an n-type metal oxide semiconductor field effect (NMOS) transistor. Each transistor has a control input (a gate in the example of NMOS or PMOS transistors) and a pair of current terminals (source and drain in the example of NMOS or PMOS transistors). The input signal to the amplifier of  FIG. 1  is represented as VIN+ and VIN−, and the output from the amplifier is represented as OUTP, which is a single-ended signal (referenced to ground) in this example. VIN+ and VIN− are complementary voltages, that is, as VIN+ increases, VIN− decreases, and vice versa. 
     The gate of M 1  is coupled to one input node  101  to thereby receive VIN+ and the gate of M 2  is coupled to another input node  102  to thereby receive VIN−. The drain of M 1  is connected to one terminal of R 1 . Similarly, the drain of M 2  is connected to one terminal of R 2 . The other terminals of R 1  and R 2  are connected together and to the drain of MCS 1 . The source of MCS 1  is connected to the ground node  109 . The gates of MCS 1  and MCS 2  are connected together and to the node  105  between the drain of M 1  and resistor R 1 . The drain of MCS 2  is connected to the sources of both M 1  and M 2 . The source of MCS 2  is connected to a VDD node  110 . The output OUTP from the amplifier is the voltage at node  107  between the drain of M 2  and resistor R 2 . 
     The combination of M 2  and R 2  forms a common source amplifier whose current is supported (generated) by MCS 2  and MCS 1 . At relatively low ICM voltages (close to ground), VIN+ and VIN− will swing complementarily between voltages that are close to ground (e.g., between 100 mV and 300 mV for an ICM voltage level of 200 mV, and thus a 100 mV swing). As VIN+ increases within that range, the voltage on node  105  decreases due to lower current flowing through R 1  from MCS 2  and M 1 . The voltage on node  105  enhances either PMOS current source MCS 2  (when node  105  voltage decreases) or NMOS MCS 1  (when node  105  voltage increases). Also the voltage on node  105  causes a change in the resistances of MCS 1  and MCS 2 . As VIN+ increases, the voltage on node  105  decreases thereby enhancing MCS 2  to deliver more current and the resistance of MCS 2  reduces while the resistance of MCS 1  increases. At the same time, the resistance of M 2  decreases due to the decrease in VIN− to the gate of M 2 . Due to the decrease in the resistance of M 2 , the OUTP voltage increases. Conversely, as VIN+ decreases and VIN− increases, M 1  is enhanced and thus voltage on node  105  increases, which in turn enhances MCS 1  to deliver more current. Further, with a higher node  105  voltage the resistance of MCS 1  decreases, the resistance of MCS 2  increases, and the resistance of M 2  increases (due to a decrease in VIN−). As a result, the OUTP voltage decreases. 
       FIG. 2  illustrates an example of another common source amplifier circuit that operates particularly well for ICM voltage levels that are closer to VDD than to ground. The illustrative amplifier circuit of  FIG. 2  includes transistors M 3 , M 4 , MCS 3 , MCS 4 , and resistors R 3  and R 4 . In this example, M 3 , M 4 , and MCS 3  are NMOS transistors and MCS 4  is a PMOS transistor. As was the case for the example of  FIG. 2 , the input signal to the amplifier of  FIG. 1  is represented as VIN+ and VIN−, and the output from the amplifier is represented as OUTP. 
     The gate of M 3  is coupled to one input node  201  to thereby receive VIN+ and the gate of M 4  is coupled to another input node  202  to thereby receive VIN−. The drain of M 3  is connected to one terminal of R 3 . Similarly, the drain of M 4  is connected to one terminal of R 4 . The other terminals of R 3  and R 4  are connected together and to the drain of MCS 4 . The source of MCS 3  is connected to the ground node  109 . The gates of MCS 3  and MCS 4  are connected together and to the node  205  between the drain of M 3  and resistor R 3 . The drain of MCS 3  is connected to the sources of both M 3  and M 4 . The source of MCS 4  is connected to VDD node  110 . The output OUTP from the amplifier of the example of  FIG. 2  is the voltage at node  207  between the drain of M 4  and resistor R 4 . 
     The example of  FIG. 2  operates similarly to the example of  FIG. 1  but at ICM voltages that are closer to VDD rather than ground. The combination of M 4  and R 4  forms an amplifier whose current is supported (generated) by MCS 4  and MCS 3 . At relatively high ICM voltages (close to VDD), VIN+ will swing between voltages that are close to VDD (e.g., between 800 mV and 1 V for an ICM voltage level of 900 mV and a 100 mV swing relative to the ICM voltage). As VIN+ increases within that range, the resistance of NMOS M 3  decreases and thus the voltage on node  205  decreases. The decreasing voltage on node  205  enhances PMOS current source transistor MCS 4  to deliver more current. At the same time the resistance of M 4  increases due to the decrease in VIN−. An increase in resistance of M 4  results in an increase in OUTP. Conversely, if MCS 3  is enhanced to deliver more current more current (due to VIN+ decreasing causing node  205  voltage to increase), the resistance of MCS 3  decreases while the resistance of MCS 4  increases. As a result, OUTP decreases. 
       FIG. 3  shows an embodiment of a circuit  300  that includes two WICMAs  310  and  315 , and to gain amplifiers (GA)  320  and  325 .  FIG. 4  provides an illustrative implementation of each WICMA  310 ,  315  and will be discussed below. Each WICMA  310  comprises a plurality (e.g., three) of self-biased differential amplifiers which share common inputs and outputs. Each WICMA operates satisfactorily across a wide range of ICM voltage levels from just above ground to just below VDD. WICMA  310  produces a single-ended output on output node  313  and WICMA  315  produces a single-ended output on output node  318 . Each WICMA has two input nodes—one designated as a positive input (+) and the other designated as a negative input (−). The input signal to the circuit  300  is represented by VIN+ and VIN−. The + input node  311  of WICMA  310  and the negative input node  317  of WICMA  315  are connected together and to the VIN− input. The negative input node  312  of WICMA  310  and the positive input node  316  of WICMA  315  are connected together and to the VIN+ input. As such, the VIN+ and VIN− inputs are connected with one polarity to WICMA  310  and with the opposite polarity to WICMA  315 . As a result, the single-ended output on output node  313  from WICMA  310  has the same polarity as VIN+ and the single-ended output on output node  318  from WICMA  315  has the same polarity as VIN−. The output nodes  313  and  318  thus comprise a differential signal, similar to that VIN+ and VIN− but with a common mode voltage shift relative to the ICM voltage level of VIN+ and VIN−. The output nodes  313  and  318  comprise common mode voltages that are approximately half of the supply voltage VDD for any variation of ICM. 
     The gain factor of the WICMAs  310  and  315  may not be as much as is desired in many applications. Accordingly, a second stage comprising gain amplifiers  320  and  325  are included in the example of  FIG. 3 . Each GA  320 ,  325  includes a positive input and a negative input as was the case for the WICMAs  310 ,  315 . The output node  313  from WICMA  310  is coupled to the positive input node  321  of GA  320  and to the negative input node  327  of GA  325 . The output node  318  from WICMA  315  is coupled to the negative input node  322  of GA  320  and to the positive input node  326  of GA  325 . The gain factors of GAs  320  and  325  may be application specific. In one example, the gain factor is 2, but can be other than 2 in other examples. The output from circuit  300  is taken as the voltage on the output nodes  323  and  328  of GA  320  and GA  325 , respectively, as shown as OUT+ and OUT−. 
     Each of the WICMAs  310  and  315  may be implemented with a circuit such as that shown in the example of  FIG. 4 . The example WICMA implementation of  FIG. 4  effectively combines three amplifiers together—one that operates with ICM voltage levels in the lower range closer to ground, one that operates with ICM voltage levels at the upper range closer to VDD, and one that operates with ICM voltages approximately half-way between ground and VDD. The three amplifiers share input voltage nodes  301  (VIN+) and  302  (VIN−) and an output voltage node  308  (OUTP). 
     The example WICMA of  FIG. 4  includes transistors M 5 , M 6 , M 7 , M 8 , M 9 , and M 10 , current source transistors MCS 5 , MCS 6 , MCS 7 , MCS 8 , MCS 9 , and MCS 10 , and resistors R 5 , R 6 , R 7 , and R 8 . Transistors M 7 , M 8 , and M 9  are PMOS transistors and transistors M 5 , M 6 , and M 10  are NMOS transistors. Current source transistors MCS 6 , MCS 8 , and MCS 10  are PMOS transistors and current source transistors MCS 5 , MCS 7 , and MCS 9  are NMOS transistors. The transistors can be implemented with different dopings in other examples, and bipolar junction transistors can be used instead of MOS transistors. 
     The drain  406  of M 7  is connected to the drain  401  of M 5  at node  420 . The gates of M 7  and M 5  are connected together at the VIN+ input voltage node  398 . On the right side of the circuit, the drain  408  of M 8  is connected to the drain  403  of M 6  at the output voltage node (OUTP)  395 . The gates of M 8  and M 6  are connected together at the VIN− input voltage node  399 . 
     The gates of current source transistors MCS 6  and MCS 5  are connected together and also to node  420  to connect to the drains  401  and  406  of M 5  and M 7 , respectively. The source of MCS 6  is connected to the positive power node  415  (VDD) and the source of MCS 5  is connected to ground node  417  (also termed a power node). The drain of MCS 5  is connected to the sources  402  and  404  of M 5  and M 6 , respectively. The drain of MCS 6  is connected to the sources  405  and  407  of M 7  and M 8 , respectively. 
     The combination of M 5 , M 6 , M 7 , M 8 , MCS 5 , and MCS 6  represents one of the three amplifiers noted above subsumed within the architecture of the WICMA  310 ,  315 . This particular amplifier operates when the ICM voltage level is in the mid-range between ground and VDD (e.g., approximately one-half of VDD). M 6  and M 8  function as an inverter between VIN− and OUTP. That is, as the VIN− voltage falls, OUTP rises, and vice versa. The inverter comprising M 8  and M 6  receives current via current source transistors MCS 6  and MCS 5 . M 5  and M 7  also form an inverter to invert VIN+ on to node  420  (as VIN+ increases, the voltage on node  420  decreases, and vice versa). 
     The input to the amplifier is defined by VIN+ and VIN−, which has a particular ICM voltage (approximately mid-range between ground and VDD and which has a voltage swing relative to the ICM voltage level). In one example, the suitable ICM voltage level for the amplifier defined above is 600 mV for a VDD of 1V and may have a voltage swing of 200 mV relative to the ICM voltage level. Thus, VIN+ ranges from 500 mV to 700 mV, while at the same time VIN− ranges in the opposite direction from 700 mV to 500 mV. If VIN+ increases towards its upper voltage level (700 mV in this example), the voltage on node  420  decreases thereby biasing PMOS transistor MCS 6  more strongly than NMOS transistor MCS 5 . While VIN+ increases, VIN− decreases. Due to the inverter formed by M 8  and M 6 , the voltage on the output node  395  (OUTP) increases because M 6  will be turned off as VIN− may be less than the switching threshold voltage of M 6 . With MCS 6  being driven more strongly due the decrease in voltage on node  420  (which drives the gate of MCS 6 ), current from MCS 2  helps to increase the OUTP voltage even faster. By contrast, if VIN+ decreases and VIN− increases, the voltage on node  420  will increase thereby turning on M 6  and MCS 5  to a stronger state thereby providing a good conducting path from OUTP to ground thereby pulling OUTP down even faster than if the inverter formed by M 7  and M 5  was not present. 
     However, the amplifier formed by M 5 , M 6 , M 7 , M 8 , MCS 5  and MCS 6  may not function correctly at ICM voltage levels closer to ground or closer to VDD. At those higher or lower voltage levels, one of M 6  or M 8  may be stuck on or off thereby preventing the satisfactory operation. For example, if the ICM voltage level is 900 mV (with VDD equal to 1V and a 200 mV swing relative to the 900 mV ICM voltage level), M 8  will permanently in the triode or even the sub-threshold region as VIN− swings between 800 mV and 1 V and thus also remains above the threshold voltage of M 8 . As such, M 8  cannot operate as an amplifier. Similarly, if the input voltage is close to ground (e.g., ICM voltage of 200 mV with a 100 mV swing), then Vin− will be too low ever to turn on M 6 . 
     Another amplifier embedded in the architecture of each WICMA  310 ,  315  includes transistors M 8  and M 9 , current source transistors MCS 10  and MCS 9 , and resistors R 5  and R 6 . The architecture of this amplifier is similar to that shown in the example of  FIG. 1  and is operative for ICM voltage levels closer to ground. The drain  410  of M 9  is connected to R 5  (at node  422 ) which also connects to the gates of MCS 10  and MCS 9 . The drain  408  of M 8  is connected to R 6 , and R 6  also connects to MCS 9 . The sources  409  and  407  of M 9  and M 8 , respectively connect to MCS 10  as shown. As such, transistor M 8  is a component both of the amplifier which is operative for ICM voltage levels in the mid-range between ground and VDD and of the amplifier which is operative for ICM voltage levels closer to ground. Resistors R 5  and R 6  are used for this latter amplifier to advantageously permit current to flow even at lower ICM voltage levels. 
     The operation of the amplifier formed by transistors M 8  and M 9 , current source transistors MCS 10  and MCS 9 , and resistors R 5  and R 6  functions similar to that described above regarding  FIG. 1 . When ICM is low (close to ground), the transistors M 8 , M 9 , MCS 9  and MCS 10  and the resistors R 5  and R 6  will operate as an amplifier because all NMOS transistors will be off (not conduct current). Also the PMOS transistors M 7 , MCS 6  and MSC 8  will not conduct current because the current path is interrupted with M 5 , MCS 5  and MCS 9  being off). R 8  can be neglected because R 8  is of a much lower resistance than M 8 . In the case in which VIN+ increases (albeit close to ground), the voltage on node  422  will decline because M 9  will provide less current to the node  410 . At the same time M 8  becomes more open meaning it is capable of delivering more current to the OUTP node  395  due to the lower gate-to-source voltage on M 8 . As the voltage on node  422  decreases, MCS 10  will be more open i.e. provide more current to the circuit. Since M 8  provides a better conducting path for current than M 9 , the current from MCS 10  will flow to OUTP rather than to node  422  thereby causing a voltage rise for OUTP. At the same time, when the node  422  node voltage decreases, the MCS 9  will be less open (because MCS 9  gate-to-source voltage is lower). Since less current is pulled from OUTP (through R 6 ) the voltage at the node OUTP will rise quickly. The voltage OUTP is not clamped to VDD due to limited gain of the amplifier formed by M 8 , M 9 , MCS 9  and MCS 10  and the resistors R 5  and R 6 . As long as VIN+ is greater than VIN−, the OUTP voltage will be high (high compared to the case when VIN+=VIN−). In the opposite case, when VIN+ declines and VIN− increases, M 9  is enhanced to form a better conducting path for current than M 8 . The node  422  voltage declines, MCS 10  provides less current to M 8  and a majority of current flows through M 9 . At the same time MCS 9  becomes more open (because its gate-to-source voltage is higher) which will pull down the OUTP voltage and the voltage OUTP is lower than in case when VIN+ equals VIN−. Also, in this case, the voltage OUTP is not clamped to ground. 
     A third amplifier embedded in the architecture of each WICMA  310 ,  315  includes transistors M 6  and M 10 , current source transistors MCS 8  and MCS 7 , and resistors R 7  and R 8 . The architecture of this amplifier is similar to that shown in the example of  FIG. 2  and is operative for ICM voltage levels closer to VDD. The drain  411  of M 10  is connected to R 7  (at node  421 ) and to the gates of MCS 7  and MCS 8 . The drain  403  of M 6  is connected to R 8 , and R 8  also connects to MCS 8 . The sources  412  and  404  of M 10  and M 6 , respectively, connect to MCS 7  as shown. As such, transistor M 6  is a component both of the amplifier which is operative for ICM voltage levels in the mid-range between ground and VDD and of the amplifier which is operative for ICM voltage levels closer to ground. Resistors R 7  and R 8  are used for this latter amplifier to advantageously permit current to flow even at lower ICM voltage levels. 
     The operation of the amplifier formed by transistors M 6  and M 10 , current source transistors MCS 8  and MCS 7 , and resistors R 7  and R 8  functions similar to that described above regarding  FIG. 2 . When ICM is high i.e. close to VDD the transistors M 6 , M 10 , MCS 7  and MCS 8  and the resistors R 7  and R 8  will operate as amplifier because all PMOS transistors will be off and thus not conduct current. Also the NMOS transistors M 5 , MCS 5  and MSC 9  will not conduct current because the current path is interrupted due to M 7 , MCS 6  and MCS 10  being off. In this case R 6  can be neglected because the resistance of R 6  is high compared to the resistance of M 6 . When the differential voltage VIN+ increases and thus VIN− decreases, M 10  becomes a better conductive path for current than M 6  because the M 10  gate-to-source voltage raises while M 6  gate-to-source decreases. At the same time the node  421  voltage decreases and MCS 8  is more open and delivers more current. Since M 10  is a better path for current, and thus less current will flow through R 8 . The voltage drop across R 8  will be lower and the voltage OUTP increases. At the same time MCS 7  is more closed and delivers less current which prevents the discharging of OUTP through R 6  (i.e., the voltage at OUTP will raise faster due to small discharging current). In the opposite case when VIN+ decreases and VIN− increases, M 6  is a better conducting path for current than M 10 . The node  421  voltage increases and MCS 8  is less open i.e. delivers less current while MCS 7  deliver more current. As a result, the node OUTP will discharge faster (much less current is injected into this node than is pulled from the node) and the voltage OUTP will decreases faster. 
     The pairs of current source transistors—MCS 5 /MCS 6 , MCS 7 /MCS 8 , and MCS 9 /MCS 10 —operate as described above based on the change in voltages of their corresponding nodes  420 ,  421 , and  422 . 
     The above discussion is meant to be illustrative various examples. Numerous variations and modifications are possible.