Patent Publication Number: US-2007097016-A1

Title: Triple Screen Video Arcade Circuit

Description:
Triple Screen Arcade Video Circuit combines an off-the-shelf low cost video controller IC with a FPGA (field programmable gate Array) circuit to create a three screen video output circuit. This overall circuit has the features of low production cost (only a modest size FPGA is needed), low development cost (no new custom IC needs be designed), has all three video screen outputs vertically phase locked and has a single video hardware memory map. The three screen phase locking reduces eye fatigue for the viewer and improves frame to frame timing of animation of large multi-screen images, below a few nanoseconds of error. The single hardware memory map allows for off-the-shelf video games and any animating application software to make use of the all three screens of this video display circuit, as no modification to software is needed to accommodate multiple video fame memories. 
    
    
     DRAWINGS LIST  
       FIG. 1  Low Cost  3  Screen Arcade with Single Memory Map, shows typical  3  display orientation and representation as one triple wide image area in video memory.  
       FIG. 2 . Circuitry Layout with Functional Description of  3  Display System, how video memory is scanned by the two video engines in the video controller and how the second double-wide image is digitally processed into two normal size video flows.  
       FIG. 3 . Faster video data updates (writes and reads) can be done from the computer bus into video memory with this variant of the design, that allows for ½ normal scan speed of the scan engine for the double wide video flow. 
    
    
     BACKGROUND OF THE INVENTION  
      The present invention relates to the use of video controller chips to make more useful display systems with more screens, than had been intended as the feature sets of the video controller chips. Also that the larger number of displays may be vertically and horizontally phase locked. Also that the multiple displays have a single video memory map as perceived by common game software applications, flight simulator software applications and business applications, particularly those that are benefited from multiple windows.  
      This invention lowers the cost of such products, for cost to the users and cost of development. This invention also adds features not commonly found in uses of the same video controller integrated circuit chips.  
     Description of the Prior Art  
      Prior art typically used multiple video controller chips to create multiple displays. The prior are does not use a double wide second video flow, then split into two normal size flows to increase the number of display screen outputs. The prior art has taken multiple video controllers and copied them onto a single piece of silicon, but they are in function and practice, multiple video controllers. As such the computers using the video designs of that nature do not see the video memory as continuous. Thus 3 or more screen games and other applications must be made custom for those video designs. This reduces product usefulness to the users, and increases costs to the users. Prior art does not use dual scan engine video controllers as a low cost starting point to achieve three screen video systems.  
     Description of the Preferred Embodiments  
      Invention embodies, expand the intended use of Laptop PC video controller chip  100  and  200 , that was intended for use in dual screen laptop personal computers, to achieve an additional video output stream to a third screen  101  and  102 . Invention embodies a video controller IC and additional digital circuits to split a double-wide image  101  into two smaller images  103  and  104 .  
      The invention uses a single dual output (dual scan engine) video controller  200 , that has one scan engine assigned to be the master scan engine that scans 2048 by 768 pixels,  204  and second scan engine assigned to be the slave  201 . The master scan engine scans a 8×3 ratio image and outputs its data via a 24 bit parallel bus and that data stream is divided into to data streams by the line buffer in the FPGA  206 . Invention embodies circuits that use the same clock rate, thus able to use video clock subtractor (clock subtraction circuit)  202  of U.S. Pat. No. 6,626,695. The slave scan engine, uniquely scanning half the number of pixels as the master scan engine, has its clocks interrupted by the video clock subtractor  202  to achieve vertical and horizontal phase locking of the final display data flows. Invention embodies the multiplexing of the I2C ports  203  on the video controller to provide low cost control of the added digital circuits by the software video driver. Invention embodies the multiplexing of the I2C ports to provide I2C ports for each of the users display screens. Invention embodies the continuous video memory map to provide easy use of software applications that display imagery on all three screens.  
      Easing of the video memory bandwidth requirement of the video controller IC is done by scanning video memory in the video controller IC at ½ normal scan speed  300 . This improves the memory bandwidth remaining for the users video data from his/her computer to be painted into video memory faster. This is done by the added frame memory to the FPGA, so that a whole 30 Hhz frame of 2048 by 762 image can be held for faster scanning by the final output  300 .  
      The recovery of full speed frames to the final video flow is done by the FPGA managing two video memory IC&#39;s acting as double buffer frame memories  300 . The line buffer  301  in conjunction with the memories converts the 30 Hz output  302  of the master scan engine in the video controller IC to 60 Hz in the final data flow to the user&#39;s display monitors. Timing control of the external frame buffer memories  300  is accomplished by using the synchronous feature of SDRAM for the final read scanning, while using 1024 count jumps in memory addressing when writing every other pixel into the memory controlled by the FPGA.