Patent Publication Number: US-2022239220-A1

Title: Charge pump circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of U.S. provisional patent application Ser. No. 63/142,498, filed on Jan. 28, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference and made a part of this specification. 
    
    
     BACKGROUND 
     Technical Field 
     The disclosure relates a circuit; particularly, the disclosure relates to a charge pump circuit. 
     Description of Related Art 
     A display device generally comprises a display panel and a driving circuit. Since the limitation of the material of the display panel, some part of the driving circuit is often disposed on a driving integrated circuit instead of on the display panel. For example, a sweep signal generator is disposed on driving integrated circuit to provide a sweep signal for the pixels on the display panels. 
     However, in order to provide the sweep signal from the driving integrated circuit to the display panel, low impedance transmission is required. Also, for the optimization of area overhead, the sweep signal is used to provide to all the pixels. Therefore, the low resistance and low parasitic capacitance of the transmission line and the condition of sweep signal bring some limitations to the display device. 
     Further, a charge pump circuit is commonly used in voltage regulator. Since the output of the charge pump circuit is not linear, the charge pump circuit is not suitable for a signal generator. 
     SUMMARY 
     The disclosure is direct to a charge pump circuit, so as to implement an in-pixel sweep signal generator. 
     In the disclosure, the charge pump circuit includes a first transistor, a first capacitor, a second transistor, and a second capacitor. The first transistor has a first end and a second end. The first capacitor has a first end and a second end. The second end of the first capacitor is electrically connected to the second end of the first transistor. The second transistor has a first end and a second end. The first end of the second transistor is electrically connected to the second of the first transistor. The second capacitor has a first end and a second end. The first end of the second capacitor is electrically connected to the second end of the second transistor. 
     Based on the above, according to the charge pump circuit of the disclosure, by applying a plurality of input signals to the charge pump circuit, a plurality of output signals are obtain. Since the structure of the charge pump circuit is simple, it is able to be disposed on the substrate and thereby an in-pixel sweep signal generator may be implemented. 
     To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. 
         FIG. 1  is a schematic diagram of a charge pump circuit according to a first embodiment of the disclosure. 
         FIG. 2  is a schematic signal timing chart of the charge pump circuit according to the first embodiment of the disclosure. 
         FIG. 3  is a schematic diagram of a charge pump circuit according to a second embodiment of the disclosure. 
         FIG. 4  is a schematic signal timing chart of the charge pump circuit according to the second embodiment of the disclosure. 
         FIG. 5  is a schematic diagram of a charge pump circuit according to a modification of the second embodiment of the disclosure. 
         FIG. 6  is a schematic diagram of a charge pump circuit according to a third embodiment of the disclosure. 
         FIG. 7  is a schematic diagram of a charge pump circuit according to a modification of the third embodiment of the disclosure. 
         FIG. 8  is a schematic diagram of a charge pump circuit according to a fourth embodiment of the disclosure. 
         FIG. 9  is a schematic signal timing chart of the charge pump circuit according to the fourth embodiment of the disclosure. 
         FIG. 10  is a schematic diagram of a charge pump circuit according to a modification of the fourth embodiment of the disclosure. 
         FIG. 11A  is a schematic block diagram of a pixel circuit for AM-LED display panel according to one embodiment of the disclosure. 
         FIG. 11B  is a schematic signal timing chart of a pixel circuit for AM-LED display panel according to one embodiment of the disclosure. 
         FIG. 12A  is a schematic block diagram of a pixel circuit for photon counting detector according to one embodiment of the disclosure. 
         FIG. 12B  is a schematic input signal of the comparators of a pixel circuit for photon counting detector according to one embodiment of the disclosure. 
         FIG. 12C  is schematic output signals of the comparators of a pixel circuit for photon counting detector according to one embodiment of the disclosure. 
         FIG. 12D  is schematic output signals of the counters of a pixel circuit for photon counting detector according to one embodiment of the disclosure. 
         FIG. 13  is a schematic diagram of an arbitrary waveform generator according to one embodiment of the disclosure. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Reference will now be made in detail to the exemplary embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numbers are used in the drawings and the description to refer to the same or like components. 
     Certain terms are used throughout the specification and appended claims of the disclosure to refer to specific components. Those skilled in the art should understand that electronic device manufacturers may refer to the same components by different names. This article does not intend to distinguish those components with the same function but different names. In the following description and rights request, the words such as “comprise” and “include” are open-ended terms, and should be explained as “including but not limited to . . . ”. 
     The term “coupling (or connection)” used throughout the whole specification of the present application (including the appended claims) may refer to any direct or indirect connection means. For example, if the text describes that a first device is coupled (or connected) to a second device, it should be interpreted that the first device may be directly connected to the second device, or the first device may be indirectly connected through other devices or certain connection means to be connected to the second device. The terms “first”, “second”, and similar terms mentioned throughout the whole specification of the present application (including the appended claims) are merely used to name discrete elements or to differentiate among different embodiments or ranges. Therefore, the terms should not be regarded as limiting an upper limit or a lower limit of the quantity of the elements and should not be used to limit the arrangement sequence of elements. In addition, wherever possible, elements/components/steps using the same reference numerals in the drawings and the embodiments represent the same or similar parts. Reference may be mutually made to related descriptions of elements/components/steps using the same reference numerals or using the same terms in different embodiments. 
     The light emitting device of the disclosure may, for example, be adapted to a liquid crystal, a light emitting diode, a quantum dot (QD), a fluorescence, a phosphor, other suitable materials, or the combination of the aforementioned materials, but the disclosure is not limited thereto. The light emitting diode may include, for example, organic light emitting diode (OLED), sub-millimeter light emitting diode (Mini LED), micro light emitting diode (Micro LED), or quantum dot light emitting diode (QLED or QDLED) or other suitable materials. The materials may be arranged and combined arbitrarily, but the disclosure is not limited to thereto. The light emitting device of the disclosure may include peripheral systems such as driving system, control system, light source system, shelf system, and the like to support the light emitting device. 
     It should be noted that in the following embodiments, the technical features of several different embodiments may be replaced, recombined, and mixed without departing from the spirit of the disclosure to complete other embodiments. As long as the features of each embodiment do not violate the spirit of the disclosure or conflict with each other, they may be mixed and used together arbitrarily. 
       FIG. 1  is a schematic diagram of a charge pump circuit according to a first embodiment of the disclosure. Referring to  FIG. 1 , a charge pump circuit  100  may include a pump up circuit  110  and a reset circuit  120 . The pump up circuit  110  may include a first transistor T 1 , a second transistor T 2 , a first capacitor C 1 , and a second capacitor C 2 . Specifically, the first transistor T 1  may have a first end and a second end. In one embodiment, the first end of the first transistor T 1  may be the source terminal and the second end of the first transistor T 1  may be the drain terminal, but this disclosure is not limited thereto. In another embodiment, the first end of the first transistor T 1  may be the drain terminal and the second of the first transistor T 1  may be the source terminal. In the embodiment, the first capacitor C 1  may have a first end and a second end. The second end of the first capacitor C 1  may be electrically connected to the second end of the first transistor T 1  at a first node N 1 . The second transistor T 2  may have a first end and a second end. In the embodiment, the first end of the second transistor T 2  may be electrically connected to the second end of the first transistor T 1  at the first node N 1 . The second capacitor C 2  may have a first end and a second end. The first end of the second capacitor C 2  may be electrically connected to the second end of the second transistor T 2 . 
     Further, the reset circuit  120  may include a reset transistor Tr. The reset transistor may have a first end and a second end. The first end of the reset transistor Tr may be electrically connected to the first end of the second capacitor C 2 . The second end of the reset transistor Tr may receive a reset voltage. The reset transistor Tr may further have a control end. The control end of the reset transistor Tr may receive a reset signal RES. 
     In the embodiment, the reset circuit  120  may be disposed in the charge pump circuit  100 . The reset circuit  120  and the pump up circuit  110  may be integrated in an electronic device (for example, in a pixel of a display device). In the embodiment, the electronic device may include a light emitting device or a display device, but the disclosure is not limited thereto. In one embodiment, the display device may include an active matrix light emitting diode (AM-LED) display panel, but the disclosure is not limited thereto. 
     In addition, in one embodiment, the reset circuit  120  may be disposed outside the charge pump circuit  100 . In the embodiment the reset circuit  120  may be disposed on a driving integrated circuit of the pixel of the display device to provide the reset signal RES to the pump up circuit  110 . That is, the charge pump circuit  100  may not include the reset circuit  120 , but the disclosure is not limited thereto. 
       FIG. 2  is a schematic signal timing chart of the charge pump circuit according to the first embodiment of the disclosure. Referring to  FIG. 1  and  FIG. 2 , the first end of the first capacitor C 1  may receive an input signal Vi, and the first end of the second capacitor C 2  may provide an output signal Vo. In the embodiment, the first end of the transistor T 1  receives a first voltage V 1 , and a control end of the second transistor T 2  receives a second voltage V 2 . The first voltage V 1  may be lower than the second voltage V 2 , but this disclosure is not limited thereto. The second end of the second capacitor C 2  receives the reset voltage Vrst. The first transistor T 1  may have a first threshold voltage Vth 1 , and the second transistor T 2  may have a second threshold voltage Vth 2 . The first end of the first transistor T 1  is electrically connected to a control end of the first transistor. That is, the first transistor T 1  may act as a diode. In the embodiment, the first transistor T 1  may be an N-type transistor and the second transistor T 2  may be a P-type transistor, but this disclosure is not limited thereto. In one embodiment, the first transistor T 1  may be a P-type transistor and the second transistor T 2  may be an N-type transistor. 
     In the embodiment, for the convenience of understanding, for example, the first voltage V 1  may be 7 volts. The second voltage V 2  may be 9 volts. An absolute value of the first threshold voltage Vth 1  and the second threshold voltage Vth 2  may be 1 volt, but this disclosure is not limited thereto. At time t_ 1 , the reset signal RES may be switched from a low voltage level to a high voltage level. After the high voltage level is applied to the control end of the reset transistor Tr, the reset transistor Tr is turned on and the first end of the second capacitor C 2  is reset to the reset voltage Vrst. That is, the output signal Vo is reset to the reset voltage Vrst. Before time t_ 2 , the reset signal RES may be switched from the high voltage level to the low voltage level. Further, the voltage of the first node N 1  may be obtained by subtracting the first threshold voltage Vth 1  from the first voltage V 1 , thus the voltage of the first node N 1  may be represented as V 1 −|Vth 1 |. 
     At time t_ 2 , the input signal Vi may be switched from the low voltage level to the high voltage level, and the voltage difference between the low voltage level and the high voltage level may be an input voltage Vin. In the embodiment, the input voltage Vin is assumed to be 5 volts, but this disclosure is not limited thereto. Since a voltage difference between the first end and the second end of the first capacitor C 1  may maintain a constant value, the voltage of the first node N 1  may be change from V 1 −|Vth 1 | to V 1 −|Vth 1 |+Vin. However, since the first node N 1  is electrically connected to the first end of the second transistor T 2 , the voltage value of the first node N 1  may be confined by the second transistor T 2 . That is, at time t_ 2 , the voltage value of the first node N 1  may be V 2 +|Vth 2 | (the solid line of N 1  in  FIG. 2 ) instead of V 1 −|Vth 1 |+Vin (the dashed line of N 1  in  FIG. 2 ) and the second transistor T 2  may be turned on. Therefore, an extra charge Q may be discharged from the first capacitor C 1  based on the voltage difference and may be calculated by the following equation (1). 
         Q=C 1×{( V 1−| Vth 1|)+ V in−( V 2+| Vth 2|)}  (1)
 
     In the embodiment, the extra charge Q may be transferred by a second transistor current I_T 2  from the first capacitor C 1  to the second capacitor C 2 , and thereby may charge the second capacitor C 2 . That is, the value of the output signal Vo may be increased by a value of a step voltage Vstep and the value of the step voltage Vstep may be calculated by the following equation (2). 
     
       
         
           
             
               
                 
                   Vstep 
                   = 
                   
                     
                       
                         C 
                         ⁢ 
                         1 
                       
                       
                         C 
                         ⁢ 
                         2 
                       
                     
                     × 
                     
                       { 
                       
                         
                           ( 
                           
                             
                               V 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
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                                 Vth 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
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                           ) 
                         
                         + 
                         Vin 
                         - 
                         
                           ( 
                           
                             V2 
                             + 
                             
                                
                               
                                 Vth 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
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                       } 
                     
                   
                 
               
               
                 
                   ( 
                   2 
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     In the embodiment, a ratio of the first capacitor C 1  and the second capacitor C 2  may be 1/100. That is, the value of the step voltage Vstep may be 10 millivolts. Therefore, the value of the output signal Vo may be increased from the reset voltage Vrst to Vrst+Vstep. 
     At time t_ 3 , the input signal Vi may be switched from the high voltage level to the low voltage level, and the voltage difference between the low voltage level and the high voltage level may be also the input voltage Vin. Since a voltage difference between the first end and the second end of the first capacitor C 1  may maintain a constant value, the voltage of the first node N 1  may be change from V 2 +|Vth 2 | to V 2 +|Vth 2 |−Vin. However, since the first node N 1  is electrically connected to the second end of the first transistor T 1 , the voltage value of the first node N 1  may be confined by the first transistor T 1 . That is, at time t_ 3 , the voltage value of the first node N 1  may be V 1 −|Vth 1 | (the solid line of N 1  in  FIG. 2 ) instead of V 2 +|Vth 2 |−Vin (the dashed line of N 1  in  FIG. 2 ) and the first transistor T 1  may be turned on. Therefore, an insufficient charge Q′ may be charged into the first capacitor C 1  by a first transistor current I_T 1  based on the voltage difference, and may be calculated by the following equation (3). 
         Q′=C 1×{( V 2+| Vth 2|)− V in−( V 1+| Vth 1|)}=− Q   (3)
 
     At time t_ 4 , the input signal Vi may be switched from the low voltage level to the high voltage level and the voltage difference between the low voltage level and the high voltage level may be an input voltage Vin. Referring to time t_ 2 , the extra charge Q may be discharged from the first capacitor C 1 . Further, the extra charge Q may be transferred by the second transistor current I_T 2  from the first capacitor C 1  to the second capacitor C 2  and thereby may charge the second capacitor C 2 . That is, the value of the output signal Vo may be increased by the value of the step voltage Vstep. Therefore, the value of the output signal Vo may be increased from Vrst+Vstep to Vrst+(2×Vstep). 
     At time t_ 5 , the input signal Vi may be switched from the high voltage level to the low voltage level, and the voltage difference between the low voltage level and the high voltage level may be also the input voltage Vin. Referring to time t_ 3 , the insufficient charge Q′ may be charged into the first capacitor C 1  by the first transistor current I_T 1 . 
     At time t_ 6 , the input signal Vi may be switched from the low voltage level to the high voltage level, and the voltage difference between the low voltage level and the high voltage level may be an input voltage Vin. Referring to times t_ 2  and t_ 4 , the extra charge Q may be discharged from the first capacitor C 1 . Further, the extra charge Q may be transferred by the second transistor current I_T 2  from the first capacitor C 1  to the second capacitor C 2 , and thereby may charge the second capacitor C 2 . That is, the value of the output signal Vo may be increased by the value of the step voltage Vstep. Therefore, the value of the output signal Vo may be increased from Vrst+(2×Vstep) to Vrst+(3×Vstep). 
     At time t_ 7 , the input signal Vi may be switched from the high voltage level to the low voltage level, and the voltage difference between the low voltage level and the high voltage level may be also the input voltage Vin. Referring to times t_ 3  and t_ 5 , the insufficient charge Q′ may be charged into the first capacitor C 1  by the first transistor current I_T 1 . 
     It should be noted that, the output signal Vo may be increased by the value of the step voltage Vstep at times t_ 2 , t_ 4 , and t_ 6 , respectively. That is, by repeating switching the input signal Vi between the high voltage level and the low voltage level, the value of the output signal Vo may be increased to a plurality of different values. Further, the plurality of different values may be proportional to the number of repetitions of switching the input signal Vi. That is, a variety of waveforms may be able to be output by the charge pump circuit  100  and the output is substantially linear. Therefore, the charge pump circuit  100  may be used as a signal generator. In one embodiment, the charge pump circuit  100  may be used as a sweep signal generator for a pixel of a display device to implement an in-pixel sweep signal generator. Further, since the structure of the charge pump circuit  100  is simple, the charge pump circuit  100  may be disposed on the substrate and thereby an in-pixel sweep signal generator may be implemented. In one embodiment, the substrate may comprise glass or polyimide or other suitable materials, but this disclosure is not limited thereto. 
     In the embodiment, the second transistor T 2  is a P-type transistor, but this disclosure is not limited thereto. In the embodiment, the second transistor T 2  may provide a charging current (the second transistor current I_T 2 ) of the second capacitor C 2  and thereby the charge pump circuit  100  may be a pump up circuit. In another embodiment, the second transistor T 2  may be an N-type transistor, and thereby may provide a discharging current of the second capacitor C 2 . Therefore, the charge pump circuit  100  may become a pump down circuit. 
       FIG. 3  is a schematic diagram of a charge pump circuit according to a second embodiment of the disclosure. Referring to  FIG. 1  and  FIG. 3 , a charge pump circuit  300  may have a similar structure as the charge pump circuit  100 . The charge pump circuit  300  may include a first transistor T 31 , a second transistor T 32 , a first capacitor C 31 , and a second capacitor C 32 . These elements may be referred to the charge pump circuit  100  and the details are not redundantly described seriatim herein. 
     In the embodiment, the charge pump circuit  300  may further include a third transistor T 33 , a fourth transistor T 34 , a fifth transistor T 35 , a sixth transistor T 36 , and a third capacitor C 33 . In the embodiment, the third transistor T 33  may have a first end and a second end. The third transistor T 33  may be electrically connected between the second end of the second transistor T 32  and the first end of the second capacitor C 32 . The third capacitor C 33  may have a first end and a second end. The first end of the third capacitor C 33  may be electrically connected to a control end of the second transistor T 32 . The fourth transistor T 34  may have a first end and a second end. The fourth transistor T 34  may be electrically connected between the second end of the second transistor T 32  and the first end of the third capacitor C 33 . The fifth transistor T 35  may have a first end and a second end. The fifth transistor T 35  may be electrically connected between the second end of the fourth transistor T 34  and the second end of the third capacitor C 33 . The sixth transistor T 36  may have a first end and a second end. The sixth transistor T 36  may be electrically connected between the second end of the third transistor T 33  and the second end of the second capacitor C 32 . In the embodiment, the second end of the first capacitor C 31  may be indicated as a first node N 31 , the first end of the third capacitor C 33  may be indicated as a second node N 32 , and a first end of the second capacitor C 32  may be indicated as a third node N 33 . In the embodiment, the first transistor T 31  may have a first threshold voltage Vth 31 , the second transistor T 32  may have a second threshold voltage Vth 32 , but this disclosure is not limited thereto. 
     In the embodiment, the first end of the first transistor T 31  receives a first reference voltage VH. A second end of the second capacitor C 32  receives a second reference voltage VL. A second end of the third capacitor C 33  receives a reset voltage Vrst 3 . In the embodiment, a control end of the fifth transistor T 35  may receive a reset signal RES 3 . A control end of the sixth transistor T 36  may receive an initialization signal INIT 3 . In the embodiment, a control end of the third transistor T 33  and a control end of the fourth transistor T 34  receive a compensation signal COMP 3 . In the embodiment, a first end of the first capacitor C 31  may receive an input signal Vi 3 . A first end of the second capacitor C 32  may provide an output signal Vo 3 . 
       FIG. 4  is a schematic signal timing chart of the charge pump circuit according to the second embodiment of the disclosure. Referring to  FIG. 3  and  FIG. 4 , the circled numbers in the figures may indicate different steps of the operation of the charge pump circuit  300 , respectively. The arrows with the circled numbers in the figures may indicate the currents during a certain steps of the operation of the charge pump circuit  300 , respectively. An arrow toward the first capacitor C 31  may indicate charging the first capacitor C 31 , and an arrow away from the first capacitor C 31  may indicate discharging the first capacitor C 31 . 
     During the period from time t_ 31  to time t_ 32  (step  1 ), the reset signal RES 3  may be switched from a low voltage level to a high voltage level, and the compensation signal COMP 3  and initialization signal INIT 3  may be remained at a low voltage level. After the high voltage level is applied to the control end of the fifth transistor T 35 , the fifth transistor T 35  is turned on. Therefore, the first end of the third capacitor C 33  is reset to the reset voltage Vrst 3  by a fifth transistor current I_T 35 . That is, the second node N 32  is reset to the reset voltage Vrst 3 . Since the reset voltage Vrst 3  is at a low voltage level, the second transistor T 32  may be turned on. Further, the first transistor T 31  is turned on due to the high voltage level of the first reference voltage VH, and the third transistor T 33  is turned on due to the low voltage level of the compensation signal COMP 3 . Therefore, the first node N 31  and the third node N 33  are both reset to VH−|Vth 31 | by the second capacitor current I_C 32 . Before time t_ 32 , the reset signal RES may be switched from the high voltage level to the low voltage level. 
     During the period from time t_ 32  to time t_ 33  (step  2 ), the compensation signal COMP 3  may be switched from a low voltage level to a high voltage level. After the high voltage level is applied to the control end of the third transistor T 33  and fourth transistor T 34 , the third transistor T 33  is switched from on to off and the fourth transistor T 34  is switched from off to on. The second node N 32  is then compensated to VH−|Vth 31 |−|Vth 32 |, by the fourth transistor current I_T 34 . Before time t_ 33 , the compensation signal COMP 3  may be switched from the high voltage level to the low voltage level. 
     During the period from time t_ 33  to time t_ 34  (step  3 ), the initialization signal INIT 3  may be switched from a low voltage level to a high voltage level. After the high voltage level is applied to the control end of the sixth transistor T 36 , the sixth transistor T 36  is switched from off to on. The node N 33  is reset to a second reference voltage VL by a sixth transistor current I_T 36 . Before time t_ 34 , the initialization signal INIT 3  may be switched from the high voltage level to the low voltage level. 
     During the period from time t_t 34  to time t_t 35  (step  4 ), the input signal Vi 3  may be switched from a low voltage level to a high voltage level, and the voltage difference between the low voltage level and the high voltage level may be an input voltage Vin. Since a voltage difference between the first end and the second end of the first capacitor C 1  may maintain a constant value, the voltage of the first node N 31  may be change from VH−|Vth 31 | to VH−|Vth 31 |+Vin. However, since the first node N 31  is electrically connected to the first end of the second transistor T 32 , the voltage value of the first node N 31  may be confined by the second transistor T 32 . That is, at time t_ 34 , the voltage value of the first node N 31  may be remained at VH−|Vth 31 | (the solid line of N 31  in  FIG. 4 ) instead of VH−|Vth 31 |+Vin (the dashed line of N 31  in  FIG. 4 ). The second transistor T 32  and the third transistor T 33  may be turned on. Therefore, an extra charge Q may be discharged from the first capacitor C 31  based on the voltage difference and may be calculated by the following equation (4). 
         Q=C 31×{( VH−|Vth 31|+ V in)−( VH−|Vth 31|)}= C 31× V in  (4)
 
     In the embodiment, the extra charge Q may be transferred by a second transistor current I_T 32  and a third transistor current I_T 33  from the first capacitor C 31  to the second capacitor C 32  and thereby may charge the second capacitor C 32 . That is, the value of the output signal Vo 3  may be increased by a value of a step voltage Vstep 3  and the value of the step voltage Vstep 3  may be calculated by the following equation (5). 
     
       
         
           
             
               
                 
                   
                     Vstep 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                   
                   = 
                   
                     
                       
                         C 
                         ⁢ 
                         3 
                         ⁢ 
                         1 
                       
                       
                         C 
                         ⁢ 
                         3 
                         ⁢ 
                         2 
                       
                     
                     × 
                     Vin 
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     Therefore, the value of the output signal Vo 3  may be increased from the second reference voltage VL to VL+Vstep 3 . 
     During the period from time t_ 35  to time t_ 36  (step  5 ), the input signal Vi 3  may be switched from the high voltage level to the low voltage level, and the voltage difference between the low voltage level and the high voltage level may be also the input voltage Vin. Since a voltage difference between the first end and the second end of the first capacitor C 1  may maintain a constant value, the voltage of the first node N 31  may be change from VH−|Vth 31 | to VH−|Vth 31 |−Vin. However, since the first node N 31  is electrically connected to the second end of the first transistor T 31 , the voltage value of the first node N 31  may be confined by the first transistor T 31 . That is, at time t_ 34 , the voltage value of the first node N 31  may be remained at VH−|Vth 31 |(the solid line of N 31  in  FIG. 4 ) instead of VH−|Vth 31 |−Vin (the dashed line of N 31  in  FIG. 4 ) and the first transistor T 31  may be turned on. Therefore, an insufficient charge Q′ may be charged into the first capacitor C 31  by the first transistor current I_T 31  based on the voltage difference and may be calculated by the following equation (6). 
         Q′=C 31×{( VH−|Vth 31|− V in)−( VH−|Vth 31|)}= C 31×(− V in)=− Q   (6)
 
     During the period from time t_ 36  to time t_ 37 , the charging operation may repeat again as the step  4 . The extra charge Q may be discharged from the first capacitor C 31 . Further, the extra charge Q may be transferred by the second transistor current I_T 32  and the third transistor current I_T 33  from the first capacitor C 31  to the second capacitor C 32  and thereby may charge the second capacitor C 32 . Therefore, the value of the output signal Vo 3  may be increased from VL+Vstep 3  to VL+(2×Vstep 3 ). During the period from time t_ 37  to time t_ 38 , the charging operation may repeat again as the step  5 . The insufficient charge Q′ may be charged into the first capacitor C 31  by the first transistor current I_T 31 . 
     During the period from time t_ 38  to time t_ 39 , the charging operation may repeat again as the step  4 . The extra charge Q may be discharged from the first capacitor C 31 . Further, the extra charge Q may be transferred by the second transistor current I_T 32  and the third transistor current I_T 33  from the first capacitor C 31  to the second capacitor C 32  and thereby may charge the second capacitor C 32 . Therefore, the value of the output signal Vo 3  may be increased from VL+(2×Vstep 3 ) to VL+(3×Vstep 3 ). After time t_ 39 , the charging operation may repeat again as the step  5 . The insufficient charge Q′ may be charged into the first capacitor C 31  by the first transistor current I_T 31 . 
     It should be noted that, the value of the output signal Vo 3  may be increased by the value of the step voltage Vstep 3  at times t_ 34 , t_ 36 , and t_ 38 , respectively. That is, by repeating the step  4  and the step  5 , the value of the output signal Vo 3  may be increased to a plurality of different values. Further, the plurality of different values are proportional to the number of repeating the step  4  and the step  5 . That is, a variety of waveforms may be able to be output by the charge pump circuit  300 , and the output is substantially linear. Therefore, the charge pump circuit  300  may be used as a signal generator. In one embodiment, the charge pump circuit  300  may be used as a sweep signal generator for a pixel of a display device to implement an in-pixel sweep signal generator. Further, since the structure of the charge pump circuit  300  is simple, the charge pump circuit  300  may be disposed on the substrate, and thereby an in-pixel sweep signal generator may be implemented. 
     In the embodiment, the second transistor T 32  is a P-type transistor, but this disclosure is not limited thereto. In the embodiment, the second transistor T 32  may provide a charging current (the second transistor current I_T 32 ) of the second capacitor C 32  and thereby the charge pump circuit  300  may be a pump up circuit. In another embodiment, the second transistor T 32  may be an N-type transistor, and thereby may provide a discharging current of the second capacitor C 32 . Therefore, the charge pump circuit  300  may become a pump down circuit. 
       FIG. 5  is a schematic diagram of a charge pump circuit according to a modification of the second embodiment of the disclosure. Referring to  FIG. 5 , the main difference between  FIG. 3  and  FIG. 5  is that, the second transistor T 32  of the charge pump circuit  300  is a P-type transistor and the second transistor T 52  of the charge pump  500  is an N-type transistor. In the embodiment, the charge pump circuit  500  may include a first transistor T 51 , a second transistor T 52 , a first capacitor C 51 , and a second capacitor C 52 . These elements may be referred to the charge pump circuit  100  and the details are not redundantly described seriatim herein. 
     In the embodiment, the charge pump circuit  500  may further include a third transistor T 53 , a fourth transistor T 54 , a fifth transistor T 55 , a sixth transistor T 56 , and a third capacitor C 53 . In the embodiment, the third transistor T 53  may have a first end and a second end. The third transistor T 53  may be electrically connected between the second end of the second transistor T 52  and the first end of the second capacitor C 52 . The third capacitor C 53  may have a first end and a second end. The first end of the third capacitor C 53  may be electrically connected to a control end of the second transistor T 52 . The fourth transistor T 54  may have a first end and a second end. The fourth transistor T 54  may be electrically connected between the second end of the second transistor T 52  and the first end of the third capacitor C 53 . The fifth transistor T 55  may have a first end and a second end. The fifth transistor T 55  may be electrically connected between the second end of the fourth transistor T 54  and the second end of the third capacitor C 53 . The sixth transistor T 56  may have a first end and a second end. The sixth transistor T 56  may be electrically connected between the second end of the third transistor T 53  and the second end of the second capacitor C 52 . 
     In the embodiment, the second end of the first capacitor C 51  may be indicated as a first node N 51 , the first end of the third capacitor C 53  may be indicated as a second node N 52 , and a first end of the second capacitor C 52  may be indicated as a third node N 53 . In the embodiment, the first transistor T 51  may have a first threshold voltage Vth 51 , the second transistor T 52  may have a second threshold voltage Vth 52 , but this disclosure is not limited thereto. In the embodiment, the first end of the first transistor T 51  receives a second reference voltage VL. A second end of the second capacitor C 52  receives a first reference voltage VH. A second end of the third capacitor C 53  receives a reset voltage Vrst 5 . 
     In the embodiment, a control end of the fifth transistor T 55  may receive a reset signal RES 5 . A control end of the sixth transistor T 56  may receive an initialization signal INIT 5 . In the embodiment, a control end of the third transistor T 53  and a control end of the fourth transistor T 54  may receive a compensation signal COMP 5 . In the embodiment, a first end of the first capacitor C 51  may receive an input signal Vi 5 . A first end of the second capacitor C 52  may provide an output signal Vo 5 . 
     In the embodiment, the circled numbers in the figures may indicate different steps of the operation of the charge pump circuit  500 , respectively. The arrows with the circled numbers in the figures may indicate the currents during a certain steps of the operation of the charge pump circuit  500 , respectively. An arrow toward the first capacitor C 51  may indicate charging the first capacitor C 51 , and an arrow away from the first capacitor C 51  may indicate discharging the first capacitor C 51 . 
     In the embodiment, the step  1  to the step  3  may refer to the step  1  to step  3  of the second embodiment, while the details are not redundantly described seriatim herein. It should be noted that the reset signal RES 5 , the compensation signal COMP 5 , and the initialization signal INIT 5  may be switched from a high voltage level to a low voltage level during the step  1 , step  2  and step  3 , respectively. Therefore, during the step  1 , the first node N 51  and the third node N 53  may be reset to VL+|Vth 51 |, and the second node N 52  may be reset to the reset voltage Vrst 5 . During the step  2 , the second node N 52  may be compensated to VL+|Vth 51 |+|Vth 52 |. During the step  3 , the third node N 53  may be initialized to the first reference voltage VH. 
     During the period of step  4 , the input signal Vi 5  may be switched from a high voltage level to a low voltage level, and the voltage difference between the low voltage level and the high voltage level may be an input voltage Vin. Since a voltage difference between the first end and the second end of the first capacitor C 51  may maintain a constant value, the voltage of the first node N 51  may be change from VL+|Vth 51 | to VL+|Vth 51 |−Vin. However, since the first node N 51  is electrically connected to the first end of the second transistor T 52 , the voltage value of the first node N 51  may be confined by the second transistor T 52 . That is, during the step  4 , the voltage value of the first node N 51  may be remained at VL+|Vth 51 | instead of VL+|Vth 51 |−Vin. The second transistor T 52  and the third transistor T 53  may be turned on. Therefore, an insufficient charge Q′ may be charged into the first capacitor C 51  based on the voltage difference. The value of the insufficient charge Q′ may be equal to C 51 ×(−Vin). 
     In the embodiment, the insufficient charge Q′ may be transferred by a second transistor current I_T 52  and a third transistor current I_T 53  from the second capacitor C 52  to the first capacitor C 51  and thereby may discharge the second capacitor C 52 . That is, the value of the output signal Vo 5  may be decreased by a value of a step voltage Vstep 5  and the value of the step voltage Vstep 5  may be equal to (C 51 /C 52 )×Vin. Therefore, the value of the output signal Vo 5  may be decreased from the first reference voltage VH to VH−Vstep 5 . 
     During the period of step  5 , the input signal Vi 5  may be switched from the low voltage level to the high voltage level, and the voltage difference between the low voltage level and the high voltage level may be also the input voltage Vin. Since a voltage difference between the first end and the second end of the first capacitor C 51  may maintain a constant value, the voltage of the first node N 51  may be change from VL+|Vth 51 | to VL+|Vth 51 |+Vin. However, since the first node N 51  is electrically connected to the second end of the first transistor T 51 , the voltage value of the first node N 51  may be confined by the first transistor T 51 . That is, during the period of step  5 , the voltage value of the first node N 51  may be remained at VL+|Vth 51 | instead of VL+|Vth 51 |+Vin and the first transistor T 51  may be turned on. Therefore, an extra charge Q may be discharged from the first capacitor C 51  by the first transistor current I_T 51  based on the voltage difference and may be equal to (−Q′). 
     It should be noted that, the value of the output signal Vo 5  may be decreased by the value of the step voltage Vstep 5  during the step  4 . That is, by repeating the step  4  and the step  5 , the value of the output signal Vo 5  may be decreased to a plurality of different values. Further, the plurality of different values are proportional to the number of repeating the step  4  and the step  5 . That is, a variety of waveforms may be able to be output by the charge pump circuit  500  and the output is linear. Therefore, the charge pump circuit  500  may be used as a signal generator. In one embodiment, the charge pump circuit  500  may be used as a sweep signal generator for a pixel of a display device to implement an in-pixel sweep signal generator. Further, since the structure of the charge pump circuit  500  is simple, the charge pump circuit  500  may be disposed on the substrate and thereby an in-pixel sweep signal generator may be implemented. 
       FIG. 6  is a schematic diagram of a charge pump circuit according to a third embodiment of the disclosure. Referring to  FIG. 1  and  FIG. 6 , a charge pump circuit  600  may have a similar structure as the charge pump circuit  100 . The charge pump circuit  600  may include a first transistor T 61 , a second transistor T 62 , a first capacitor C 61 , and a second capacitor C 62 . These elements may be referred to the charge pump circuit  100  and the details are not redundantly described seriatim herein. 
     In the embodiment, the charge pump circuit  600  may further include a third transistor T 63 , a fourth transistor T 64 , a fifth transistor T 65 , a sixth transistor T 66 , and a third capacitor C 63 . In the embodiment, the third transistor T 63  may have a first end and a second end. The fourth transistor T 64  may have a first end and a second end. The second end of the fourth transistor T 64  may be electrically connected to the first end of the third transistor T 63 . The fifth transistor T 65  may have a first end and a second end. The first end of the fifth transistor T 65  may be electrically connected to the first end of the fourth transistor T 64 . The sixth transistor T 66  may have a first end and a second end. The first end of the sixth transistor T 65  may be electrically to the first end of the second capacitor C 62 . The second end of the sixth transistor T 66  may be electrically to the second end of the second capacitor C 62 . The third capacitor C 63  may have a first end and a second end. The first end of the third capacitor C 63  may be electrically connected to the first end of the fifth transistor C 65 . The second end of the third capacitor C 63  may be electrically connected to the second end of the fifth transistor C 65 . 
     In the embodiment, the second end of the first capacitor C 61  may be indicated as a first node N 61 , the first end of the third capacitor C 63  may be indicated as a second node N 62 , and a first end of the second capacitor C 62  may be indicated as a third node N 63 . In the embodiment, the first transistor T 61  may have a first threshold voltage Vth 61 , the second transistor T 62  may have a second threshold voltage Vth 62 , the third transistor T 63  may have a third threshold voltage Vth 63 , and the fourth transistor T 64  may have a fourth threshold voltage Vth 64 . In the embodiment, the first threshold voltage Vth 61  may be equal to the third threshold voltage Vth 63 , and the second threshold voltage Vth 62  may be equal to the fourth threshold voltage Vth 64 , but this disclosure is not limited thereto. In the embodiment, the first end of the first transistor T 61  and the second end of the third transistor T 63  receive a first reference voltage VH. A second end of the second capacitor C 62  receives a second reference voltage VL. A second end of the third capacitor C 63  receives a reset voltage Vrst 6 . 
     In the embodiment, a control end of the fifth transistor T 65  may receive a reset signal RES 6 . A control end of the sixth transistor T 66  may receive an initialization signal INIT 6 . In the embodiment, the second end of the third transistor T 63  may be electrically connected to a control end of the third transistor T 63 . The first end of the fourth transistor T 64  may be electrically connected to a control end of the fourth transistor T 64 . In the embodiment, a first end of the first capacitor C 61  may receive an input signal Vi 6 . A first end of the second capacitor C 62  may provide an output signal Vo 6 . 
     In the embodiment, the circled numbers in the figures may indicate different steps of the operation of the charge pump circuit  600 , respectively. The arrows with the circled numbers in the figures may indicate the currents during a certain steps of the operation of the charge pump circuit  600 , respectively. An arrow toward the first capacitor C 61  may indicate charging the first capacitor C 61 , and an arrow away from the first capacitor C 61  may indicate discharging the first capacitor C 61 . In the embodiment, the step  1  and the step  3  may refer to the step  1  and step  3  of the second embodiment, while the details are not redundantly described seriatim herein. It should be noted that there is no need of step  2  in the embodiment due to the designated condition of the threshold voltages of the first transistor T 61  to the fourth transistor T 64 . That is, the third transistor T 63  and the fourth transistor T 64  are designated to provide a fourth transistor current I_T 64  for compensation. In addition, the reset signal RES 6 , and the initialization signal INIT 6  may be switched from a low voltage level to a high voltage level during the periods of step  1  and step  3 , respectively. Therefore, during the period of step  1 , the first node N 61  and the third node N 63  may be reset to VH−|Vth 61 | by a second capacitor current I_C 62 , and the second node N 62  may be reset to the reset voltage Vrst 6  by a fifth transistor current I_T 65 . During the period of step  3 , the third node N 63  may be initialized to the second reference voltage VL by a sixth transistor current I_T 66 , and the second node N 62  may be initialized to VH−|Vth 61 |−|Vth 62 |. 
     During the period of step  4 , the input signal Vi 6  may be switched from a low voltage level to a high voltage level, and the voltage difference between the low voltage level and the high voltage level may be an input voltage Vin. Since a voltage difference between the first end and the second end of the first capacitor C 61  may maintain a constant value, the voltage of the first node N 61  may be change from VH−|Vth 61 | to V 1 −|Vth 61 |+Vin. However, since the first node N 61  is electrically connected to the first end of the second transistor T 62 , the voltage value of the first node N 61  may be confined by the second transistor T 62 . That is, during the period of step  4 , the voltage value of the first node N 61  may be remained at VH−|Vth 61 | instead of VH−|Vth 61 |+Vin. The second transistor T 62  may be turned on. Therefore, an extra charge Q may be discharged from the first capacitor C 61  based on the voltage difference and may be equal to C 61 ×Vin. 
     In the embodiment, the extra charge Q may be transferred by a second transistor current I_T 62  from the first capacitor C 61  to the second capacitor C 62  and thereby may charge the second capacitor C 62 . That is, the value of the output signal Vo 6  may be increased by a value of a step voltage Vstep 6  and the value of the step voltage Vstep 6  may be equal to (C 61 /C 62 )×Vin. Therefore, the value of the output signal Vo 6  may be increased from the second reference voltage VL to VL+Vstep 6 . 
     During the period of step  5 , the input signal Vi 6  may be switched from the high voltage level to the low voltage level and the voltage difference between the low voltage level and the high voltage level may be also the input voltage Vin. Since a voltage difference between the first end and the second end of the first capacitor C 61  may maintain a constant value, the voltage of the first node N 61  may be change from VH−|Vth 61 | to VH−|Vth 61 |−Vin. However, since the first node N 61  is electrically connected to the second end of the first transistor T 61 , the voltage value of the first node N 61  may be confined by the first transistor T 61 . That is, during the period of step  5 , the voltage value of the first node N 61  may be remained at VH−|Vth 61 | instead of VH−|Vth 61 |−Vin and the first transistor T 61  may be turned on. Therefore, an insufficient charge Q′ may be charged into the first capacitor C 61  by the first transistor current I_T 61  based on the voltage difference and may be equal to (−Q). 
     It should be noted that, the value of the output signal Vo 6  may be increased by the value of the step voltage Vstep 6  during the step  4 . That is, by repeating the step  4  and the step  5 , the value of the output signal Vo 4  may be increased to a plurality of different values. Further, the plurality of different values are proportional to the number of repeating the step  4  and the step  5 . That is, a variety of waveforms may be able to be output by the charge pump circuit  600  and the output is linear. Therefore, the charge pump circuit  600  may be used as a signal generator. In one embodiment, the charge pump circuit  600  may be used as a sweep signal generator for a pixel of a display device to implement an in-pixel sweep signal generator. Further, since the structure of the charge pump circuit  600  is simple, the charge pump circuit  600  may be disposed on the substrate and thereby an in-pixel sweep signal generator may be implemented. 
     In the embodiment, the second transistor T 62  is a P-type transistor, but this disclosure is not limited thereto. In the embodiment, the second transistor T 62  may provide a charging current (the second transistor current I_T 62 ) of the second capacitor C 62  and thereby the charge pump circuit  600  may be a pump up circuit. In another embodiment, the second transistor T 62  may be an N-type transistor, and thereby may provide a discharging current of the second capacitor C 62 . Therefore, the charge pump circuit  600  may become a pump down circuit. 
       FIG. 7  is a schematic diagram of a charge pump circuit according to a modification of the third embodiment of the disclosure. Referring to  FIG. 7 , the main difference between  FIG. 6  and  FIG. 7  is that, the second transistor T 62  of the charge pump circuit  600  is a P-type transistor and the second transistor T 72  of the charge pump  700  is an N-type transistor. In the embodiment, the charge pump circuit  700  may include a first transistor T 71 , a second transistor T 72 , a first capacitor C 71 , and a second capacitor C 72 . These elements may be referred to the charge pump circuit  100  and the details are not redundantly described seriatim herein. 
     In the embodiment, the charge pump circuit  700  may further include a third transistor T 73 , a fourth transistor T 74 , a fifth transistor T 75 , a sixth transistor T 76 , and a third capacitor C 73 . In the embodiment, the third transistor T 73  may have a first end and a second end. The first end of the third transistor T 73  may be electrically connected to the second end of the fourth transistor T 74 . The third capacitor C 73  may have a first end and a second end. The first end of the third capacitor C 73  may be electrically connected to a control end of the second transistor T 72 . The fourth transistor T 74  may have a first end and a second end. The fourth transistor T 74  may be electrically connected between the control end of the second transistor T 72  and the first end of the third transistor T 73 . The fifth transistor T 75  may have a first end and a second end. The fifth transistor T 75  may be electrically connected between the first end of the fourth transistor T 74  and the second end of the third capacitor C 73 . The sixth transistor T 76  may have a first end and a second end. The sixth transistor T 76  may be electrically connected between the first end of the second capacitor C 72  and the second end of the second capacitor C 72 . 
     In the embodiment, the second end of the first capacitor C 71  may be indicated as a first node N 71 , the first end of the third capacitor C 73  may be indicated as a second node N 72 , and a first end of the second capacitor C 72  may be indicated as a third node N 73 . In the embodiment, the first transistor T 71  may have a first threshold voltage Vth 71 , the second transistor T 72  may have a second threshold voltage Vth 72 , the third transistor T 73  may have a third threshold voltage Vth 73 , and the fourth transistor T 74  may have a fourth threshold voltage Vth 74 . In the embodiment, the first threshold voltage Vth 71  may be equal to the third threshold voltage Vth 73 , and the second threshold voltage Vth 72  may be equal to the fourth threshold voltage Vth 74 , but this disclosure is not limited thereto. 
     In the embodiment, the first end of the first transistor T 71 , the control end of the third transistor T 73  and the second end of the third transistor T 73  receive a second reference voltage VL. A second end of the second capacitor C 72  receives a first reference voltage VH. A second end of the third capacitor C 73  receives a reset voltage Vrst 7 . In the embodiment, a control end of the fifth transistor T 75  may receive a reset signal RES 7 . A control end of the sixth transistor T 76  may receive an initialization signal INIT 7 . In the embodiment, a first end of the first capacitor C 71  may receive an input signal Vi 7 . A first end of the second capacitor C 72  may provide an output signal Vo 7 . 
     In the embodiment, the arrows with the circled numbers in the figures may indicate the currents during a certain steps of the operation of the charge pump circuit  700 , respectively. An arrow toward the first capacitor C 71  may indicate charging the first capacitor C 71 , and an arrow away from the first capacitor C 71  may indicate discharging the first capacitor C 71 . In the embodiment, the step  1  and the step  3  may refer to the periods of step  1  and step  3  of the second embodiment, while the details are not redundantly described seriatim herein. It should be noted that there is no need of step  2  in the embodiment due to the designated condition of the threshold voltages of the first transistor T 71  to the fourth transistor T 74 . That is, the third transistor T 73  and the fourth transistor T 74  are designated to provide a fourth transistor current I_T 74  for compensation. In addition, the reset signal RES 7 , and the initialization signal INIT 7  may be switched from a high voltage level to a low voltage level during the periods of step  1  and step  3 , respectively. Therefore, during the period of step  1 , the first node N 71  and the third node N 73  may be reset to VL+|Vth 71 | by a second capacitor current I_C 72 , and the second node N 72  may be reset to the reset voltage Vrst 7  by a fifth transistor current I_T 75 . During the period of step  3 , the second node N 72  may be initialized to VL+|Vth 1 |+|Vth 2 |. 
     During the period of step  4 , the input signal Vi 7  may be switched from a high voltage level to a low voltage level and the voltage difference between the low voltage level and the high voltage level may be an input voltage Vin. Since a voltage difference between the first end and the second end of the first capacitor C 71  may maintain a constant value, the voltage of the first node N 71  may be change from VL+|Vth 71 | to VL+|Vth 71 |−Vin. However, since the first node N 71  is electrically connected to the first end of the second transistor T 72 , the voltage value of the first node N 71  may be confined by the second transistor T 72 . That is, during the step  4 , the voltage value of the first node N 71  may be remained at VL+|Vth 71 | instead of VL+|Vth 71 |−Vin. The second transistor T 72  may be turned on. Therefore, an insufficient charge Q′ may be charged into the first capacitor C 71  based on the voltage difference. The value of the insufficient charge Q′ may be equal to C 71 ×(−Vin). 
     In the embodiment, the insufficient charge Q′ may be transferred by a second transistor current I_T 72  from the second capacitor C 72  to the first capacitor C 71  and thereby may discharge the second capacitor C 72 . That is, the value of the output signal Vo 7  may be decreased by a value of a step voltage Vstep 7  and the value of the step voltage Vstep 7  may be equal to (C 71 /C 72 )×Vin. Therefore, the value of the output signal Vo 7  may be decreased from the first reference voltage VH to VH−Vstep 7 . 
     During the period of step  5 , the input signal Vi 7  may be switched from the low voltage level to the high voltage level, and the voltage difference between the low voltage level and the high voltage level may be also the input voltage Vin. Since a voltage difference between the first end and the second end of the first capacitor C 71  may maintain a constant value, the voltage of the first node N 71  may be change from VL+|Vth 71 | to VL+|Vth 71 |+Vin. However, since the first node N 71  is electrically connected to the second end of the first transistor T 71 , the voltage value of the first node N 71  may be confined by the first transistor T 71 . That is, during the step  5 , the voltage value of the first node N 71  may be remained at VL+|Vth 71 | instead of VL+|Vth 71 |+Vin and the first transistor T 71  may be turned on. Therefore, an extra charge Q may be discharged from the first capacitor C 71  by the first transistor current I_T 71  based on the voltage difference and may be equal to (−Q′). 
     It should be noted that, the value of the output signal Vo 7  may be decreased by the value of the step voltage Vstep 7  during the period of step  4 . That is, by repeating the step  4  and the step  5 , the value of the output signal Vo 7  may be decreased to a plurality of different values. Further, the plurality of different values are proportional to the number of repeating the step  4  and the step  5 . That is, a variety of waveforms may be able to be output by the charge pump circuit  700  and the output is linear. Therefore, the charge pump circuit  700  may be used as a signal generator. In one embodiment, the charge pump circuit  700  may be used as a sweep signal generator for a pixel of a display device to implement an in-pixel sweep signal generator. Further, since the structure of the charge pump circuit  700  is simple, the charge pump circuit  700  may be disposed on the substrate and thereby an in-pixel sweep signal generator may be implemented. 
       FIG. 8  is a schematic diagram of a charge pump circuit according to a fourth embodiment of the disclosure. Referring to  FIG. 1  and  FIG. 8 , a charge pump circuit  800  may have a similar structure as the charge pump circuit  100 . The charge pump circuit  800  may include a first transistor T 81 , a second transistor T 82 , a first capacitor C 81 , and a second capacitor C 82 . These elements may be referred to the charge pump circuit  100  and the details are not redundantly described seriatim herein. 
     In the embodiment, the charge pump circuit  800  may further include a third transistor T 83 , a fourth transistor T 84 , a fifth transistor T 85 , a sixth transistor T 86 , a seventh transistor T 87 , an eighth transistor T 88 , a ninth transistor T 89  and a third capacitor C 83 . In the embodiment, the third transistor T 83  may have a first end and a second end. The third transistor T 83  may be electrically connected between the second end of the second transistor T 82  and the first end of the second capacitor C 82 . The third capacitor C 83  may have a first end and a second end. The first end of the third capacitor C 83  may be electrically connected to a control end of the second transistor T 82 . The fourth transistor T 84  may have a first end and a second end. The fourth transistor T 84  may be electrically connected between the second end of the second transistor T 82  and the first end of the third capacitor C 83 . The fifth transistor T 85  may have a first end and a second end. The fifth transistor T 85  may be electrically connected between the second end of the fourth transistor T 84  and the second end of the third capacitor C 83 . The sixth transistor T 86  may have a first end and a second end. The first end of the sixth transistor T 86  may be electrically connected to the first end of the second capacitor C 82 . The seventh transistor T 87  may have a first end and a second end. The second end of the seventh transistor T 87  may be electrically connected to the second end of the sixth transistor T 86 . The eighth transistor T 88  may have a first end and a second end. The first end of the eighth transistor T 88  may be electrically connected to the second end of the seventh transistor T 87 . The ninth transistor T 89  may have a first end and a second end. The first end of the ninth transistor T 89  may be electrically connected to the second end of the eighth transistor T 88 . 
     In the embodiment, the second end of the first capacitor C 81  may be indicated as a first node N 81 , the first end of the third capacitor C 83  may be indicated as a second node N 82 , and a first end of the second capacitor C 82  may be indicated as a third node N 83 . In the embodiment, the first transistor T 81  may have a first threshold voltage Vth 81 , the second transistor T 82  may have a second threshold voltage Vth 82 , and the eighth transistor T 88  may have an third threshold voltage Vth 83 . In the embodiment, the first end of the first transistor T 81  and the first end of the seventh transistor T 87  receive a first reference voltage VH. A second end of the second capacitor C 82  and the second end of the ninth transistor T 89  receive a second reference voltage VL. A second end of the third capacitor C 83  receives a reset voltage Vrst 8 . 
     In the embodiment, a control end of the fifth transistor T 85  may receive a reset signal RES 8 . In the embodiment, a control end of the third transistor T 83  and a control end of the fourth transistor T 84  may receive a first compensation signal COMP 81 . A control end of the sixth transistor T 86 , a control end of the seventh transistor T 87 , and a control end of the ninth transistor T 89  may receive a second compensation signal COMP 82 . In the embodiment, a first end of the first capacitor C 81  may receive an input signal Vi 8 . The second end of the eighth transistor T 88  may provide an output signal Vo 8 . 
       FIG. 9  is a schematic signal timing chart of the charge pump circuit according to the fourth embodiment of the disclosure. Referring to  FIG. 8  and  FIG. 9 , the circled numbers in the figures may indicate different steps of the operation of the charge pump circuit  800 , respectively. The arrows with the circled numbers in the figures may indicate the currents during a certain steps of the operation of the charge pump circuit  800 , respectively. An arrow toward the first capacitor C 81  may indicate charging the first capacitor C 81 , and an arrow away from the first capacitor C 81  may indicate discharging the first capacitor C 81 . In the embodiment, the step  1  and the step  2  may refer to the step  1  and step  2  of the second embodiment, while the details are not redundantly described seriatim herein. In the embodiment, the reset signal RES 8 , the first compensation signal COMP 81 , the second compensation signal COMP 82  may be switched from a low voltage level to a high voltage level during the periods of step  1 , step  2 , and step  3 , respectively. Therefore, during the period of step  1 , the first node N 81  and the third node N 83  may be reset to VH−|Vth 81 | by a second capacitor current I_C 82 , the second node N 82  may be reset to the reset voltage Vrst 8  by a fifth transistor current I_T 85 , and the output signal Vo 8  may be reset to VH−|Vth 81 |−|Vth 83 | by an eighth transistor step one current I_T 88 _ 1 . During the period of step  2 , the second node N 82  may be compensated to VH−|Vth 81 |−|Vth 82 | by a fourth transistor current I_T 84 . During the period of step  3 , the third node N 83  may be compensated to VL+|Vth 83 | by a sixth transistor current I_T 86 , and the output signal Vo 8  may be compensated to the second reference voltage VL by an eighth transistor step three current I_T 88 _ 3  and a ninth transistor current I_T 89 . 
     During the step  4 , the input signal Vi 8  may be switched from a low voltage level to a high voltage level, and the voltage difference between the low voltage level and the high voltage level may be an input voltage Vin. Since a voltage difference between the first end and the second end of the first capacitor C 81  may maintain a constant value, the voltage of the first node N 81  may be change from VH−|Vth 81 | to VH−|Vth 81 |+Vin. However, since the first node N 81  is electrically connected to the first end of the second transistor T 82 , the voltage value of the first node N 81  may be confined by the second transistor T 82 . That is, during the period of step  4 , the voltage value of the first node N 81  may be remained at VH−|Vth 81 | (the solid line of N 81  in  FIG. 9 ) instead of VH−|Vth 81 |+Vin (the dashed line of N 81  in  FIG. 9 ). The second transistor T 82  and the third transistor T 83  may be turned on. Therefore, an extra charge Q may be discharged from the first capacitor C 81  based on the voltage difference and may be equal to C 81 ×Vin. 
     In the embodiment, the extra charge Q may be transferred by a second transistor current I_T 82  and a third transistor current I_T 83  from the first capacitor C 81  to the second capacitor C 82  and thereby may charge the second capacitor C 82 . In addition, the voltage value of the output signal Vo 8  may be obtained by subtracting the third threshold voltage Vth 83  from the voltage value of the third node N 83 . That is, the value of the output signal Vo 8  may be increased by a value of a step voltage Vstep 8  and the value of the step voltage Vstep 8  may be equal to (C 81 /C 82 )×Vin. Therefore, the value of the output signal Vo 8  may be increased from the second reference voltage VL to VL+Vstep 8  by an eighth transistor step four current I_T 88 _ 4 . 
     During the period of step  5 , the input signal Vi 8  may be switched from the high voltage level to the low voltage level and the voltage difference between the low voltage level and the high voltage level may be also the input voltage Vin. Since a voltage difference between the first end and the second end of the first capacitor C 81  may maintain a constant value, the voltage of the first node N 81  may be change from VH−|Vth 81 | to VH−|Vth 81 |−Vin. However, since the first node N 81  is electrically connected to the second end of the first transistor T 81 , the voltage value of the first node N 81  may be confined by the first transistor T 81 . That is, during the period of step  5 , the voltage value of the first node N 81  may be remained at VH−|Vth 81 | instead of VH−|Vth 81 |−Vin and the first transistor T 81  may be turned on. Therefore, an insufficient charge Q′ may be charged into the first capacitor C 81  by the first transistor current I_T 81  based on the voltage difference and may be equal to (−Q). 
     It should be noted that, the value of the output signal Vo 8  may be increased by the value of the step voltage Vstep 8  during the step  4 . That is, by repeating the step  4  and the step  5 , the value of the output signal Vo 8  may be increased to a plurality of different values. Further, the plurality of different values are proportional to the number of repeating the step  4  and the step  5 . That is, a variety of waveforms may be able to be output by the charge pump circuit  800  and the output is linear. Therefore, the charge pump circuit  800  may be used as a signal generator. In one embodiment, the charge pump circuit  800  may be used as a sweep signal generator for a pixel of a display device to implement an in-pixel sweep signal generator. Further, since the structure of the charge pump circuit  800  is simple, the charge pump circuit  800  may be disposed on the substrate and thereby an in-pixel sweep signal generator may be implemented. 
     In the embodiment, the second transistor T 82  is a P-type transistor, but this disclosure is not limited thereto. In the embodiment, the second transistor T 82  may provide a charging current (the second transistor current I_T 82 ) of the second capacitor C 82  and thereby the charge pump circuit  800  may be a pump up circuit. In another embodiment, the second transistor T 82  may be an N-type transistor, and thereby may provide a discharging current of the second capacitor C 82 . Therefore, the charge pump circuit  800  may become a pump down circuit. 
     In the embodiment, a difference between  FIG. 3  and  FIG. 8  is that, the output signal Vo 3  may be provided through the first end of the second capacitor C 32 , but the output signal Vo 8  may be provide through the second end of the eighth transistor T 88 . That is, the output signal Vo 8  may depend on the eighth transistor T 88  instead of a capacitor. 
       FIG. 10  is a schematic diagram of a charge pump circuit according to a modification of the fourth embodiment of the disclosure. Referring to  FIG. 8 , the main difference between  FIG. 8  and  FIG. 10  is that, the second transistor T 82  of the charge pump circuit  800  is a P-type transistor and the second transistor T 102  of the charge pump  1000  is an N-type transistor. In the embodiment, the charge pump circuit  1000  may include a first transistor T 101 , a second transistor T 102 , a first capacitor C 101 , and a second capacitor C 102 . These elements may be referred to the charge pump circuit  100  and the details are not redundantly described seriatim herein. 
     In the embodiment, the charge pump circuit  1000  may further include a third transistor T 103 , a fourth transistor T 104 , a fifth transistor T 105 , a sixth transistor T 106 , a seventh transistor T 107 , an eighth transistor T 108 , a ninth transistor T 109  and a third capacitor C 103 . In the embodiment, the third transistor T 103  may have a first end and a second end. The third transistor T 103  may be electrically connected between the second end of the second transistor T 102  and the first end of the second capacitor C 102 . The third capacitor C 103  may have a first end and a second end. The first end of the third capacitor C 103  may be electrically connected to a control end of the second transistor T 102 . The fourth transistor T 104  may have a first end and a second end. The fourth transistor T 104  may be electrically connected between the control end of the second transistor T 102  and the first end of the third transistor T 103 . The fifth transistor T 105  may have a first end and a second end. The fifth transistor T 105  may be electrically connected between the second end of the fourth transistor T 104  and the second end of the third capacitor C 103 . The sixth transistor T 106  may have a first end and a second end. The first end of the sixth transistor T 106  may be electrically connected to the first end of the second capacitor C 102 . The seventh transistor T 107  may have a first end and a second end. The second end of the seventh transistor T 107  may be electrically connected to the second end of the sixth transistor T 106 . The eighth transistor T 108  may have a first end and a second end. The first end of the eighth transistor T 108  may be electrically connected to the second end of the seventh transistor T 107 . The ninth transistor T 109  may have a first end and a second end. The first end of the ninth transistor T 109  may be electrically connected to the second end of the eighth transistor T 108 . 
     In the embodiment, the second end of the first capacitor C 101  may be indicated as a first node N 101 , the first end of the third capacitor C 103  may be indicated as a second node N 102 , and a first end of the second capacitor C 102  may be indicated as a third node N 103 . In the embodiment, the first transistor T 101  may have a first threshold voltage Vth 101 , the second transistor T 102  may have a second threshold voltage Vth 102 , and the eighth transistor T 108  may have an third threshold voltage Vth 103 . In the embodiment, the first end of the first transistor T 101  and the first end of the seventh transistor T 107  receive a second reference voltage VL. A second end of the second capacitor C 102  and the second end of the ninth transistor T 109  receive a first reference voltage VH. A second end of the third capacitor C 103  receives a reset voltage Vrst 10 . 
     In the embodiment, a control end of the fifth transistor T 105  may receive a reset signal RES 10 . In the embodiment, a control end of the third transistor T 103  and a control end of the fourth transistor T 104  may receive a first compensation signal COMP 101 . A control end of the sixth transistor T 106 , a control end of the seventh transistor T 107 , and a control end of the ninth transistor T 109  may receive a second compensation signal COMP 102 . In the embodiment, a first end of the first capacitor C 101  may receive an input signal Vi 10 . A first end of the eighth transistor T 108  may provide an output signal Vo 10 . 
     In the embodiment, the circled numbers in the figures may indicate different steps of the operation of the charge pump circuit  1000 , respectively. The arrows with the circled numbers in the figures may indicate the currents during a certain steps of the operation of the charge pump circuit  1000 , respectively. An arrow toward the first capacitor C 101  may indicate charging the first capacitor C 101 , and an arrow away from the first capacitor C 101  may indicate discharging the first capacitor C 101 . 
     In the embodiment, the step  1  and the step  2  may refer to the step  1  and step  2  of the second embodiment, while the details are not redundantly described seriatim herein. In the embodiment, the reset signal RES 10 , the first compensation signal COMP 101 , the second compensation signal COMP 102  may be switched from a high voltage level to a low voltage level during the periods of step  1 , step  2 , and step  3 , respectively. Therefore, during the period of step  1 , the first node N 101  and the third node N 103  may be reset to VL+|Vth 101 | by a second capacitor current I_C 102 , the second node N 102  may be reset to the reset voltage Vrst 10  by a fifth transistor current I_T 105 , and the output signal Vo 10  may be reset to VL+|Vth 01 |+|Vth 103 | by an eighth transistor step one current I_ 108 _ 1 . During the period of step  2 , the second node N 102  may be compensated to VL+|Vth 101 |+|Vth 102 | by a fourth transistor current I_T 104 . During the period of step  3 , the third node N 103  may be compensated to VH−|Vth 103 | by a sixth transistor current I_T 106 , and the output signal may be compensated to the first reference voltage VH by an eighth transistor step three current I_T 108 _ 3  and a ninth transistor current I_T 109 . 
     During the period of step  4 , the input signal Vi 10  may be switched from a high voltage level to a low voltage level and the voltage difference between the low voltage level and the high voltage level may be an input voltage Vin. Since a voltage difference between the first end and the second end of the first capacitor C 101  may maintain a constant value, the voltage of the first node N 101  may be change from VL+|Vth 101 | to V 1 +|Vth 101 |−Vin. However, since the first node N 101  is electrically connected to the first end of the second transistor T 102 , the voltage value of the first node N 101  may be confined by the second transistor T 102 . That is, during the period of step  4 , the voltage value of the first node N 101  may be remained at VL+|Vth 101 |instead of VL+|Vth 101 |−Vin. The second transistor T 102  and the third transistor T 103  may be turned on. Therefore, an insufficient charge Q may be charged into the first capacitor C 101  based on the voltage difference and may be equal to C 101 ×(−Vin). 
     In the embodiment, the insufficient charge Q may be transferred by a second transistor current I_T 102  and a third transistor current I_T 103  to the first capacitor C 101  from the second capacitor C 102  and thereby may discharge the second capacitor C 102 . In addition, the voltage value of the output signal Vo 10  may be obtained by adding the third threshold voltage Vth 103  to the voltage value of the third node N 103 . That is, the value of the output signal Vo 10  may be decreased by a value of a step voltage Vstep 10  and the value of the step voltage Vstep 10  may be equal to (C 101 /C 102 )×Vin. Therefore, the value of the output signal Vo 10  may be decreased from the second reference voltage VL to VL−Vstep 10 . 
     During the period of step  5 , the input signal Vi 10  may be switched from the low voltage level to the high voltage level and the voltage difference between the low voltage level and the high voltage level may be also the input voltage Vin. Since a voltage difference between the first end and the second end of the first capacitor C 101  may maintain a constant value, the voltage of the first node N 101  may be change from VL+|Vth 101 | to VL+|Vth 101 |+Vin. However, since the first node N 101  is electrically connected to the second end of the first transistor T 101 , the voltage value of the first node N 101  may be confined by the first transistor T 101 . That is, during the period of step  5 , the voltage value of the first node N 101  may be remained at VL+|Vth 101 | instead of VL+|Vth 101 |+Vin and the first transistor T 101  may be turned on. Therefore, an extra charge Q′ may be discharged from the first capacitor C 101  by the first transistor current I_T 101  based on the voltage difference and may be equal to (−Q). 
     It should be noted that, the value of the output signal Vo 10  may be decreased by the value of the step voltage Vstep 10  during the period of step  4 . That is, by repeating the step  4  and the step  5 , the value of the output signal Vo 10  may be decreased to a plurality of different values. Further, the plurality of different values are proportional to the number of repeating the step  4  and the step  5 . That is, a variety of waveforms may be able to be output by the charge pump circuit  1000  and the output is linear. Therefore, the charge pump circuit  1000  may be used as a signal generator. In one embodiment, the charge pump circuit  1000  may be used as a sweep signal generator for a pixel of a display device to implement an in-pixel sweep signal generator. Further, since the structure of the charge pump circuit  1000  is simple, the charge pump circuit  1000  may be disposed on the substrate and thereby an in-pixel sweep signal generator may be implemented. 
       FIG. 11A  is a schematic block diagram of a pixel circuit for AM-LED display panel according to one embodiment of the disclosure. Referring to  FIG. 11A , a pixel circuit  1100  may include a charge pump circuit  1103 , a comparator  1104 , a current generator  1105 , a light emitting diode  1106 , a capacitor  1102 , and a scan transistor  1101 . In the embodiment, the current generator  1105  may receive a first reference voltage VDD. The capacitor  1102  may have a first end and a second end. The scan transistor  1101  may have a first end and a second end. The first end of the capacitor  1102  may be electrically connected to the second end of the scan transistor  1101 . The second end of the capacitor  1102  may receive a second reference voltage VSS. The first end of the scan transistor  1101  may be electrically connected to a data line Data(m) of a plurality of data lines. A control end of the scan transistor  1101  may be electrically connected to a scan line Scan(n) of a plurality of scan lines. The comparator  1104  may have a positive end and a negative end. The second end of the scan transistor  1101  may be electrically connected to the positive end of the comparator  1104  to provide a pulse width modulation data D_PWM. The charge pump circuit  1103  may be electrically connected to the negative end of the comparator  1104  to provide a sweep signal SW. An output end of the comparator  1104  may be electrically connected to the current generator  1105  to provide an emission control signal E_C. The light emitting diode  1106  may receive the second reference voltage VSS and be electrically connected to the current generator  1105 . 
       FIG. 11B  is a schematic signal timing chart of a pixel circuit for AM-LED display panel according to one embodiment of the disclosure. Referring to  FIG. 11A  and  FIG. 11B , the comparator  1104  may be configured to output the emission control signal E_C according to the pulse width modulation data D_PWM and the sweep signal SW. In the embodiment, before an emission period  1110 , the comparator  1104  may be configured to output a low voltage level while there is not input of the sweep signal SW. During the emission period  1110 , the comparator  1104  may be configured to output a high voltage level while the value of the pulse width modulation data D_PWM is greater than the value the sweep signal SW. After the emission period  1110 , the comparator  1104  may be configured to output the low voltage level while the value of the pulse width modulation data D_PWM is smaller than the value the sweep signal SW. In the embodiment, the sweep signal SW may be a linear signal increasing with time, and the linear signal may be with a specific slope. In the embodiment, the charge pump circuit  1103  may be implemented by one of the charge pump circuits  100 ,  300 ,  500 ,  600 ,  700 ,  800 ,  1000  of the above embodiments of  FIG. 1 ,  FIG. 3 ,  FIG. 5  to  FIG. 8 , and  FIG. 10 . Therefore, the specific slope may be determined by a step voltage of the charge pump circuit  1103 . Since the structure of the charge pump circuit  1103  is simple, the charge pump circuit  1103  may be disposed on the substrate of the AM-LED display panel and thereby an in-pixel sweep signal generator may be implemented. 
       FIG. 12A  is a schematic block diagram of a pixel circuit for photon counting detector according to one embodiment of the disclosure. Referring to  FIG. 12A , a pixel circuit for photon counting detector may include a photo detector  1201 , a pulse shaper  1202 , a first comparator  1203 , a second comparator  1204 , a first counter  1205 , a second counter  1206 , a first scan transistor  1207 , and a second transistor  1208 . In the embodiment, the photo detector  1201  may be configured to detect a light L and generate a photo detector current I_PD according to the light L. In the embodiment, the light L may be an X-ray for computed tomography, but the disclosure is not limited thereto. 
     In the embodiment, the pulse shaper  1202  may be configured to generate an input signal  1210  according to the photo detector current I_PD. The first comparator  1203  may have a positive end and a negative end. The second comparator  1204  may have a positive end and a negative end. The positive end of the first comparator  1203  and the positive end of the second comparator  1204  may receive the input signal  1210 . The negative end of the first comparator  1203  may receive a first reference signal Ref 1 . The negative end of the second comparator  1204  may receive a second reference signal Ref 2 . The first comparator  1203  may be configured to output a first comparison signal  1220  according to the input signal and the first reference signal Ref 1 . The second comparator  1204  may be configured to output a second comparison signal  1230  according to the input signal and the second reference signal Ref 2 . 
     In the embodiment, the first counter  1205  may be configured to output a first count signal  1240  according to the first comparison signal. The second counter  1206  may be configured to output a second count signal  1250  according to the second comparison signal. The first scan transistor  1207  may have a first end and a second end. The second scan transistor  1208  may have a first end and a second end. A control end of the first scan transistor  1207  may be electrically connected to a first scan line Scan 1 ( n ) of a plurality of scan lines. A control end of the second scan transistor  1208  may be electrically connected to a second scan line Scan 2 ( n ) of a plurality of scan lines. The second end of the first scan transistor  1207  and the second end of the second scan transistor  1208  may be electrically connected to a sense line Sense(m) of a plurality of sense lines. 
       FIG. 12B  is a schematic input signal of the comparators of a pixel circuit for photon counting detector according to one embodiment of the disclosure.  FIG. 12C  is schematic output signals of the comparators of a pixel circuit for photon counting detector according to one embodiment of the disclosure.  FIG. 12D  is schematic output signals of the counters of a pixel circuit for photon counting detector according to one embodiment of the disclosure. Referring to  FIG. 12A  to  FIG. 12D , the pulse shaper  1202  may be configured to generate an input signal  1210  according to the photo detector current I_PD. The input signal  1210  may be compared with the first reference signal Ref 1  by the first comparator  1203  to obtain a first comparison signal  1220 . The input signal  1210  may be compared with the second reference signal Ref 2  by the second comparator  1204  to obtain a second comparison signal  1230 . 
     In the embodiment, the first comparator  1203  and the second  1204  may output a high voltage level while the input signal  1210  is greater than the value of the first reference signal Ref 1  or the second reference signal Ref 2 , respectively. The first comparator  1203  and the second  1204  may output a low voltage level while the input signal  1210  is less than the value of the first reference signal Ref 1  or the second reference signal Ref 2 , respectively. 
     In the embodiment, there is only one value of the peaks of the input signal  1210  is greater than the value of the first reference signal Ref 1 . Therefore, the first comparison signal  1220  may include one square wave. In the embodiment, there are three values of the peaks of the input signal  1210  are greater than the value of the second reference signal Ref 2 . Therefore, the second comparison signal  1230  may include three square waves. That is, the number of the square waves of the first comparison signal  1220  and the number of the square waves of the second comparison signal  1230  are determined according to the input signal  1210 , the first reference signal Ref 1 , and the second reference signal Ref 2 , respectively. 
     In the embodiment, the first counter  1205  and the second counter  1206  may be implemented by one of the charge pump circuits  100 ,  300 ,  500 ,  600 ,  700 ,  800 , and  1000  of the above embodiments of  FIG. 1 ,  FIG. 3 ,  FIG. 5  to  FIG. 8 , and  FIG. 10 , respectively. The first counter  1205  may be configured to output a first count signal  1240  according to the number of the square waves of the first comparison signal  1220 . The second counter  1206  may be configured to output a second count signal  1250  according to the number of the square waves of the second comparison signal  1230 . Therefore, the pixel circuit  1200  may detect the number of the photos of the light L and an in-pixel photo counting detector may be implemented. 
       FIG. 13  is a schematic diagram of an arbitrary waveform generator according to one embodiment of the disclosure. Referring to  FIG. 13 , an arbitrary waveform generator  1300  may include a first up transistor T_U 1 , a second up transistor T_U 2 , a first down transistor T_D 1 , a second down transistor T_D 2 , a reset transistor T 13   r , a first up capacitor C 1 U, a first down capacitor C 1 D, and a second capacitor C 132 . In the embodiment, the first up transistor T_U 1  may have a first end and a second end. The second up transistor T_U 2  may have a first end and a second end. The first down transistor T_D 1  may have a first end and a second end. The second down transistor T_D 2  may have a first end and a second end. The reset transistor T 13   r  may have a first end and a second end. The first up capacitor C 1 U may have a first end and a second end. The first down capacitor C 1 D may have a first end and a second end. The second capacitor C 132  may have a first end and a second end. 
     In the embodiment, the first end of the first up capacitor C 1 U may receive an input up signal Viu. The second end of the first up capacitor C 1 U may be electrically connected to the second end of first up transistor T_U 1 . The first end and a control end of the first up transistor T_U 1  may receive a first reference voltage VH. The first end of the second up transistor T_U 2  may be electrically connected to the second end of the first up transistor T_U 1 . A control end of the second up transistor T_U 2  may receive the first reference voltage VH. The second end of the second up transistor T_U 2  may be electrically connected to the first end of the second capacitor C 132 . 
     In the embodiment, the first end of the first down capacitor C 1 D may receive an input down signal Vid. The second end of the first down capacitor C 1 D may be electrically connected to the first end of first down transistor T_D 1 . The second end and a control end of the first down transistor T_D 1  may receive a second reference voltage VL. The first end of the second down transistor T_D 2  may be electrically connected to the first end of the first down transistor T_D 1 . A control end of the second down transistor T_D 2  may receive the second reference voltage VL. The second end of the second down transistor T_D 2  may be electrically connected to the first end of the second capacitor C 132 . The first end of the second capacitor C 132  may provide an output signal Vo 13 . In the embodiment, the first end of the reset transistor T 13   r  may receive a reset voltage Vrst 13 . The control end of the reset transistor T 13   r  may receive a reset signal RES 13 . The second end of the reset transistor T 13   r  may provide the output signal Vol 3 . 
     Referring to  FIG. 1  and  FIG. 13 , the first up transistor T_U 1 , the second up transistor T_U 2 , the reset transistor T 13   r , the first up capacitor C 1 U, and the second capacitor C 132  may form a pump up circuit as the charge pump circuit  100  of  FIG. 1 . The first down transistor T_D 1 , the second down transistor T_D 2 , the reset transistor T 13   r , the first down capacitor C 1 D, and the second capacitor C 132  may form a pump down circuit. That is, the output signal Vol 3  may include a plurality of pump up signals and a plurality of pump down signals according to the input up signal Viu and the input down signal Vid. By changing the combination of the input up signal Viu and the input down signal Vid, a variety of the output signals Vol 3  may be obtained. Therefore, the arbitrary waveform generator  1300  may output arbitrary waveforms. 
     In summary, according to the charge pump circuit of the disclosure, by the above circuit designs of the charge pump circuit, the charge pump may output a plurality of waveforms according to the input signal and the output of the charge pump is linear. Further, since the structure of the charge pump circuit is simple, the charge pump circuit may be disposed on the substrate of the AM-LED display panel, and thereby an in-pixel sweep signal generator may be implemented. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.