Patent Publication Number: US-2022230976-A1

Title: Memory devices and methods of forming the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of U.S. provisional application Ser. No. 63/137,757, filed on Jan. 15, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using lithography and etching techniques to form circuit components and elements thereon. 
     The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1A  through  FIG. 4C  illustrate varying views of manufacturing a memory device in accordance with some embodiments. 
         FIG. 5A  through  FIG. 5C  illustrate varying views of a memory device in accordance with some embodiments. 
         FIG. 6A  through  FIG. 10B  illustrate varying views of manufacturing a memory device in accordance with some embodiments. 
         FIG. 11A  and  FIG. 11B  illustrate varying views of a memory device in accordance with some embodiments. 
         FIG. 12  illustrates a method of forming a memory device in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 180 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Various embodiments provide a memory device such as a 3D memory device. In some embodiments, the 3D memory device is a ferroelectric field effect transistor (FeFET) memory circuit including a plurality of vertically stacked memory cells. In some embodiments, each memory cell is regarded as a FeFET that includes a word line region acting as a gate electrode, a bit line region acting as a first source/drain electrode, a source line region acting as a second source/drain electrode, a ferroelectric material acting as a gate dielectric, and an oxide semiconductor (OS) acting as a channel region. In some embodiments, each memory cell is regarded as a thin film transistor (TFT). 
       FIG. 1A  through  FIG. 4C  illustrate varying views of manufacturing a memory device in accordance with some embodiments.  FIG. 1B  is illustrated along a reference cross-section I-I′ illustrated in  FIG. 1A ,  FIG. 1C  is illustrated along a reference cross-section II-II′ illustrated in  FIG. 1A , and  FIG. 1D  is illustrated along a reference cross-section III-III′ illustrated in  FIG. 1A .  FIG. 2B through 4B  is illustrated along a reference cross-section I-I′ illustrated in  FIG. 2A through 4A , and  FIG. 2C through 4C  is illustrated along a reference cross-section I-I′ illustrated in  FIG. 2A through 4A . 
     Referring to  FIG. 1A  through  FIG. 1D , a memory  100  is formed over a carrier C 1 . In some embodiments, a de-bonding layer DB 1  is formed on a top surface of the carrier C 1 , and the memory  100  is formed on the de-bonding layer DB 1 . For example, the carrier C 1  is a glass substrate and the de-bonding layer DB 1  is a light-to-heat conversion (LTHC) release layer formed on the glass substrate. However, the disclosure is not limited thereto, and other suitable materials may be adapted for the carrier C 1  and the de-bonding layer DB 1 . In alternative embodiments, a buffer layer (not shown) is coated on the de-bonding layer DB 1 , where the de-bonding layer DB 1  is sandwiched between the buffer layer and the carrier C 1 , and a top surface of the buffer layer further provides a high degree of coplanarity. The buffer layer may be a dielectric material layer or a polymer layer which is made of polyimide, BCB, PBO, or any other suitable polymer-based dielectric material. 
     In some embodiments, the memory  100  (also referred to as a memory array) includes a plurality of memory cells  102 , which may be arranged in a grid of rows and columns. The memory cells  102  may be further stacked vertically to provide a three dimensional memory, thereby increasing device density. 
     In some embodiments, the memory  100  is a 3D stackable memory. The memory  100  may be a flash memory, such as a NAND flash memory, a NOR flash memory, or the like. A process temperature of the memory  100  is higher than 400° C., for example. In an embodiment, a process temperature of the memory  100  is about 550° C. In some embodiments, a gate of each memory cell  102  is electrically coupled to a respective word line (e.g., conductive line  112 ), a first source/drain structure of each memory cell  102  is electrically coupled to a respective conductive line  126 A (e.g., bit line), and a second source/drain structure of each memory cell  102  is electrically coupled to a respective conductive line  126 B (e.g., source line). The memory cells  102  in a same horizontal row of the memory  100  may share a common word line while the memory cells  102  in a same vertical column of the memory  100  may share a common source line and a common bit line. 
     In some embodiments, the memory  100  includes a memory cell region  106 A and staircase regions  106 B,  106 C at opposite sides of the memory cell region  106 A. The memory cells  102  are disposed over an etching stop layer  101  in the memory cell region  106 A. The memory  100  may include a plurality of staircase structures ST in the memory cell region  106 A and the staircase regions  106 B,  106 C, and a dielectric material  104  is disposed between the staircase structures ST. In some embodiments, the staircase structure ST includes a plurality of vertically stacked conductive lines  112  (e.g., word lines) with dielectric layers  114  disposed between adjacent ones of the conductive lines  112 . The conductive lines  112  and the dielectric layers  114  are stacked along a direction D from a first side to a second side. The first side is a bottom side and the second side is an upper side, and vice versa. The conductive lines  112  extend in a direction parallel to a major surface of the carrier C 1 . The conductive lines  112  may have a staircase configuration such that lower conductive lines  112  are longer than and extend laterally past endpoints of upper conductive lines  112 . For example, in  FIG. 1B , multiple, stacked layers of conductive lines  112  are illustrated with topmost conductive lines  112  being the shortest and bottommost conductive lines  112  being the longest. Respective lengths of the conductive lines  112  may increase in a direction towards the underlying etching stop layer  101 . In this manner, a portion of each of the conductive lines  112  may be accessible from above the memory  100 , and conductive contacts may be made to exposed portions of the conductive lines  112 , respectively. Although the staircase structure ST is illustrated as contacting the etching stop layer  101 , any number of intermediate layers may be disposed between the etching stop layer  101  and the staircase structure ST. In alternative embodiments, the etching stop layer  101  is omitted. 
     The conductive line  112  may each include two barrier layers (not shown) and a metal layer between the barrier layers. Specifically, a barrier layer is disposed between the metal layer and the adjacent dielectric layer  114 . The barrier layers may prevent the metal layer from diffusion to the adjacent dielectric layers  114 . The barrier layers may also provide the function of increasing the adhesion between the metal layer and the adjacent dielectric layers  114 , and may be referred to as glue layers in some examples. In some embodiments, both barrier layers and glue layers with different materials are provided as needed. The barrier layers are formed of a first conductive material, such as a metal nitride, such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, or the like. The metal layer may be formed of a second conductive material, such as a metal, such as tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, or the like. The barrier layers and metal layer may each be formed by an acceptable deposition process such as CVD, PVD, ALD, PECVD, or the like. 
     The memory  100  further includes conductive pillars  116 A (e.g., electrically connected to bit lines) and conductive pillars  116 B (e.g., electrically connected to source lines) arranged alternately. The conductive pillars  116 A and  116 B may each extend in a direction perpendicular to the conductive lines  112 . A dielectric material  115  is disposed between and isolates adjacent ones of the conductive pillars  116 A and the conductive pillars  116 B, and a dielectric material  117  is disposed between and isolates adjacent pairs of the conductive pillars  116 A and  116 B. A material of the conductive pillars  116 A,  116 B may include copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, which may be formed by a deposition process (e.g., CVD, ALD, PVD, PECVD, or the like) and a planarization (e.g., a CMP, etch back, or the like). In some embodiments, the conductive pillars  116 A correspond to and are electrically connected to the bit lines in the memory device, and the conductive pillars  116 B correspond to correspond to and are electrically connected to the source lines in the memory  100 . In alternative embodiments, the conductive pillars  116 A correspond to and are electrically connected to the source lines in the memory device, and the conductive pillars  116 B correspond to correspond to and are electrically connected to the bit lines in the memory  100 . 
     The staircase configuration of the conductive lines  112  are disposed in the staircase regions  106 B,  106 C, and the conductive pillars  116 A and  116 B are disposed in the memory cell region  106 A. Pairs of the conductive pillars  116 A and  116 B along with an intersecting conductive line  112  define boundaries of each memory cell  102 , and the dielectric material  117  is disposed between and isolates adjacent pairs of the conductive pillars  116 A and  116 B. In some embodiments, the conductive pillars  116 B are electrically coupled to ground. Although  FIG. 1B  illustrates a particular placement of the conductive pillars  116 A relative the conductive pillars  116 B, it should be appreciated that the placement of the conductive pillars  116 A and  116 B may be exchanged in other embodiments. In some embodiments, the memory device is formed by a “staircase first process” in which the staircase structure is formed before the memory cells are formed. However, the disclosure is not limited thereto. In alternative embodiments, the memory device may be formed by a “staircase last process” in which the staircase structure is formed after the memory cells are formed. 
     In some embodiments, a plurality of conductive contacts  118  are formed to electrically connected to the conductive lines  112  respectively. The conductive contacts  118  may be formed in a dielectric material  120  over the dielectric material  104 . Top surfaces of the conductive contacts  118  may be substantially coplanar with top surfaces of the conductive pillars  116 A and  116 B, the dielectric layers  114  and the dielectric materials  104 ,  115  and  117 . Then, a plurality of conductive contacts  122 A,  122 B and  122 C are formed on and electrically connected to the conductive pillars  116 A, the conductive pillars  116 B, and the conductive contacts  118 , respectively. The conductive contacts  122 A,  122 B and  122 C may be formed in a dielectric material  124  over the dielectric material  120 . The conductive material of the conductive contacts  122 A,  122 B and  122 C may include copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. 
     Then, a plurality of conductive lines  126 A,  126 B are formed to electrically connect to the conductive contacts  122 A and  122 B, so as to electrically connect to the conductive pillars  116 A and  116 B. In some embodiments, the conductive lines  126 A,  126 B are crossing over the plurality of the conductive lines  112  and the dielectric layers  114 . Conductive contacts  128  are formed to electrically connect to the conductive contacts  122 C, so as to electrically connect to the conductive lines  112 . The conductive lines  126 A and the conductive lines  126 B may each extend in a direction perpendicular to the conductive lines  112 . The conductive lines  126 A are electrically connected to the conductive pillars  116 A through the conductive contacts  122 A, and the conductive lines  126 B are electrically connected to the conductive pillars  116 B through the conductive contacts  122 B. Although the conductive lines  126 A and the conductive lines  126 B are arranged as shown in  FIG. 1A , the conductive lines  126 A and the conductive lines  126 B may have any suitable arrangement. The conductive contacts  128  are electrically connected to the conductive lines  112  through the conductive contacts  118  and  122 C. The conductive lines  126 A,  126 B and the conductive contacts  128  may be formed simultaneously. The conductive lines  126 A,  126 B and the conductive contacts  128  are formed in a dielectric material  130  over the dielectric material  124 , for example. In alternative embodiments, the conductive line  126 A and the corresponding conductive contact  122 A are integrally formed, the conductive line  126 B and the corresponding conductive contact  122 B are integrally formed and/or the conductive contacts  128  and the conductive contacts  122 C are integrally formed. For example, the conductive lines  126 A,  126 B and the conductive contacts  122 A and  122 B are formed by using a dual damascene process, and the conductive contacts  128  and the conductive contacts  122 C are formed by in a same process. In such embodiments, the conductive contact  128  is also referred to as a pad portion, and the conductive contact  122 C is also referred to as a via portion. In some embodiments, a width of the conductive contacts  128  is may be larger than a width of the conductive contacts  122 C. The conductive contact  128  may be also referred to as a bonding pad, the dielectric material  130  aside the conductive contact  128  may be also referred to as a bonding layer, and the conductive contact  128  and the dielectric material  130  may be also collectively referred to as a bonding structure. The conductive contact  122 C may be also referred to as a bonding via. A material of the conductive lines  126 A,  126 B and the conductive contacts  128  includes copper, silver, gold, tungsten, aluminum, combinations thereof, or the like, for example. The dielectric materials  104 ,  115 ,  117 ,  120 ,  124  and  130  may include an oxide (e.g., silicon oxide or the like), a nitride (e.g., silicon nitride or the like), phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), a combination thereof or the like. 
     In some embodiments, the memory  100  includes a channel layer  108 . The channel layer  108  may provide channel regions for the memory cells  102 . For example, when an appropriate voltage (e.g., higher than a respective threshold voltage (V th ) of a corresponding memory cell  102 ) is applied through a corresponding conductive line  112 , a region of the channel layer  108  that intersects the conductive line  112  allows current to flow between the conductive pillars  116 A and the conductive pillars  116 B. The channel layer  108  includes materials suitable for providing channel regions for the memory cells  102 . For example, the channel layer  108  includes oxide semiconductor (OS) such as zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO, IGZO), indium zinc oxide (InZnO), indium tin oxide (ITO), combinations thereof, or the like. In some embodiments, the channel layer  108  includes polycrystalline silicon (poly-Si), amorphous silicon (a-Si), or the like. The channel layer  108  may be deposited by CVD, PVD, ALD, PECVD, or the like. 
     In some embodiments, a memory material layer  110  is disposed between the channel layer  108  and each of the conductive lines  112  and the dielectric layer  114 , and the memory material layer  110  serve as a gate dielectric for each memory cell  102 . In some embodiments, the memory material layer  110  includes a ferroelectric material, such as a hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. 
     The memory material layer  110  may be polarized in one of two different directions, and the polarization direction may be changed by applying an appropriate voltage differential across the memory material layer  110  and generating an appropriate electric field. The polarization may be relatively localized (e.g., generally contained within each boundaries of the memory cells  102 ), and a continuous region of the memory material layer  110  may extend across a plurality of memory cells  102 . Depending on a polarization direction of a particular region of the memory material layer  110 , a threshold voltage of a corresponding memory cell  102  varies, and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the memory material layer  110  has a first electrical polarization direction, the corresponding memory cell  102  may have a relatively low threshold voltage, and when the region of the memory material layer  110  has a second electrical polarization direction, the corresponding memory cell  102  may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as the threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less error prone) to read the digital value stored in the corresponding memory cell  102 . 
     To perform a write operation on a memory cell  102  in such embodiments, a write voltage is applied across a portion of the memory material layer  110  corresponding to the memory cell  102 . In some embodiments, the write voltage is applied, for example, by applying appropriate voltages to a corresponding conductive line  112  (e.g., the word line) and the corresponding conductive pillars  116 A/ 116 B (e.g., the bit line/source line). By applying the write voltage across the portion of the memory material layer  110 , a polarization direction of the region of the memory material layer  110  may be changed. As a result, the corresponding threshold voltage of the corresponding memory cell  102  may also be switched from a low threshold voltage to a high threshold voltage or vice versa, and a digital value may be stored in the memory cell  102 . Because the conductive lines  112  intersect the conductive pillars  116 A and  116 B, individual memory cells  102  may be selected for the write operation. 
     To perform a read operation on the memory cell  102  in such embodiments, a read voltage (a voltage between the low and high threshold voltages) is applied to the corresponding conductive line  112  (e.g., the word line). Depending on the polarization direction of the corresponding region of the memory material layer  110 , the memory cell  102  may or may not be turned on. As a result, the conductive pillar  116 A may or may not be discharged through the conductive pillar  116 B (e.g., a source line that is coupled to ground), and the digital value stored in the memory cell  102  can be determined. Because the conductive lines  112  intersect the conductive pillars  116 A and  116 B, individual memory cells  102  may be selected for the read operation. 
     In some embodiments, the staircase shape of the conductive lines  112  provides a surface on each of the conductive lines  112  for the conductive contact  122 C to land on. The conductive line  112  has opposite sides  112   a  and  112   b , and the conductive contact  122 C for the conductive line  112  are disposed on one of the sides  112   a  and  112   b . In an embodiment in which the memory  100  is a single-sided driving structure, the conductive contact  122 C for the conductive line  112  is disposed at one of the sides  112   a  and  112   b . In an embodiment in which the memory  100  is a double-sided driving structure, the conductive contacts  122 C for the conductive line  112  are disposed at both sides  112   a  and  112   b . In some embodiments, as shown in  FIG. 1A , the conductive contacts  122 C for the staircase structure ST are disposed at the same side  112   a  of the conductive lines  112 . In some embodiments, the opposite sides  112   a  and  112   b  are also referred to as opposite sides of the memory cell region  106 A or opposite sides of the staircase structure ST. In some embodiments, the staircase structure ST includes a staircase ST 1  in the staircase region  106 B and a staircase ST 2  in the staircase region  106 C. In an embodiment in which the memory  100  is a single-sided driving structure, one of the staircases ST 1  and ST 2  is used, and the other of the staircases ST 1  and ST 2  is non-used. Thus, the used staircase may be also referred to as a used staircase, and the non-used staircase may be also referred to as a non-used staircase. For example, as shown in  FIG. 1A , the conductive contacts  122 C are all disposed on the to the staircases ST 1 , the staircases ST 1  are used staircases, and the staircases ST 2  are non-used staircases. 
     Referring to  FIG. 2A ,  FIG. 2B  and  FIG. 2C , a circuit structure  200  is formed over a carrier C 2 . In some embodiments, the circuit structure  200  is also referred to as a periphery circuit. A process temperature of the circuit structure  200  is lower than 400° C., for example. In some embodiments, the circuit structure  200  includes a plurality of drivers  210 A,  210 B and  210 C. The drivers  210 A,  210 B and  210 C may be formed on and in a substrate  202 . The substrate  202  may be a semiconductor substrate, such as a wafer, a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. Generally, the SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate  202  may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. 
     The drivers  210 A,  210 B and  210 C may include transistors. For example, the drivers  210 A,  210 B and  210 C respectively include a gate structure  212  and a source/drain structure  214  on opposite sides of the gate structure  212 . The gate structure  212  may include a gate dielectric layer  212   a  over a top surface of the substrate  202 , a gate electrode  212   b  over the gate dielectric layer  212   a  and a gate spacer  212   c  formed along a sidewall of the gate dielectric layer  212   a  and the gate electrode  212   b . The source/drain structure  214  is a doping region in the substrate  202  or an epitaxial structure formed in a recess of the substrate  202 . The gate spacer  212   c  may separate the source/drain structure  214  from the gate electrode  212   b  by appropriate lateral distances. In some embodiments, the transistors of the drivers  210 A,  210 B and  210 C are referred as planar-type transistors, and skin portions of the substrate  202  respectively covered by the gate structure  212  and extending between the source/drain structures  214  is functioned as a conductive channel of the transistor. In some embodiments, an isolation structure  204  such as shallow trench isolation (STI) is formed between the transistors of the drivers  210 A,  210 B and  210 C. A well (not shown) may be formed between the isolation structures  204 , and the source/drain structure  214  is formed in the well. In alternative embodiments, the transistors of the drivers  210 A,  210 B and  210 C are respectively formed as a fin-type transistor or a gate-all-around (GAA) transistor. In such embodiments, three-dimensional structure(s) (e.g., fin structure(s), nanosheet(s) or the like) intersected with and covered by a gate structure are functioned as conductive channel(s) of the transistor. Although  FIG. 2A ,  FIG. 2B  and  FIG. 2C  discuss transistors formed on and in the substrate  202 , other active devices (e.g., diodes or the like) and/or passive devices (e.g., capacitors, resistors, or the like) may also be formed as part of the circuit structure  200 . In some embodiments, in addition to the memory circuit, the circuit structure  200  further includes logic circuits, sense amplifiers, controllers, input/output circuits, image sensor circuits, the like, or combinations thereof. 
     The drivers  210 A,  210 B and  210 C are disposed corresponding to the conductive lines  126 A,  126 B and  112 , respectively. A number of the drivers  210 A,  210 B and  210 C may be respectively the same as the conductive lines  126 A,  126 B and  112 . The substrate  202  may include a region  204 A corresponding to the memory cell region  106 A and a region  204 B corresponding to one of the staircase region  106 B and  106 C. In an example in which the memory device is a single-sided driving structure, the second region  204 B corresponds to one of the staircase regions  106 B and  106 C. For example, as shown in  FIG. 2A , the second region  204 B corresponds to the staircase region  106 B. In some embodiments, the drivers  210 A and  210 B are disposed in the region  204 A, and the drivers  210 C are disposed in the region  204 B. A shown in  FIG. 2A , at least two of the drivers  210 A and  210 B are disposed adjacent to each other. For example, the drivers  210 A are disposed immediately adjacent to each other, the drivers  210 B are disposed immediately adjacent to each other, and the driver  210 A and the driver  210 B are disposed immediately adjacent to each other. However, the disclosure is not limited thereto. The drivers  210 A and  210 B may have any suitable arrangement. The drivers  210 C may be arranged in a grid of rows and columns. A number of the rows of the drivers  210 C is the same as a number of the staircase structures ST, and a number of the columns of the drivers  210 C is the same as a number of the conductive lines  112  of one staircase structure ST. The drivers  210 A and  210 B may be alternately arranged. In some embodiments, a spacing between adjacent transistors of the drivers  210 C and between adjacent transistors of drivers  210 A and  210 B ranges from 10 nm to 1000 nm. Furthermore, although not shown, the drivers  210 A,  210 B and  210 C may further include other active device(s) and/or passive device(s). 
     A dielectric material  216  may surrounds and isolates the gate dielectric layers  212   a  and the gate electrodes  212   b . In some embodiments, a plurality of conductive contacts  218 A,  218 B and  218 C are formed on and electrically connected to the drivers  210 A,  210 B and  210 C, respectively. For example, the conductive contacts  218 A,  218 B and  218 C are formed to electrically connected to the source/drain structures  214  of the drivers  210 A,  210 B and  210 C. The conductive contacts  218 A,  218 B and  218 C may be also referred to as source/drain contacts. In some embodiments, the conductive contacts  218 A,  218 B and  218 C are formed in the dielectric material  216 . In some embodiments, the conductive contacts  218 A,  218 B and  218 C respectively include a pad portion  220   a  and a via portion  220   b  between the pad portion  220   a  and the driver  210 A,  210 B or  210 C. The pad portion  220   a  may have a width lager than the via portion  220   b . In some embodiments, the pad portion  220   a  is also referred to as a bonding pad, the via portion  220   b  is also referred to as a bonding via, the dielectric material  216  is also referred to as a bonding layer, and the pad portion  220   a , the via portion  220   b  and the dielectric material  216  may be also collectively referred to as a bonding structure. 
     Referring to  FIG. 3A ,  FIG. 3B  and  FIG. 3C , the memory  100  and the circuit structure  200  are bonded. In some embodiments, the memory  100  is de-bonded and is separated from the carrier C 1 . In some embodiments, the de-bonding process includes projecting a light such as a laser light or an UV light on the de-bonding layer DB 1  (e.g., the LTHC release layer) so that the carrier C 1  can be easily removed along with the de-bonding layer DB 1 . During the de-bonding step, a tape (not shown) may be used to secure the structure before de-bonding the carrier C 1  and the de-bonding layer DB 1 . After de-bonding, the memory  100  is bonded onto the circuit structure  200  through a wafer to wafer bonding process, for example. In some embodiments, the conductive lines  126 A are bonded to the conductive contacts  218 A of the drivers  210 A, the conductive lines  126 B are bonded to the conductive contacts  218 B of the drivers  210 B, and the conductive contacts  128  of the conductive lines  112  are bonded to the conductive contacts  218 C of the drivers  210 C. Accordingly, the conductive lines  126 A are electrically connected to the drivers  210 A, the conductive lines  126 B are electrically connected to the drivers  210 B, and the conductive lines  112  are electrically connected to the drivers  210 C, respectively. The dielectric material  130  may be bonded to the dielectric material  216 . In some embodiments, as shown in  FIG. 3A , the conductive lines  126 A connecting to the adjacent drivers  210 A may be physically separated by at least one conductive line  126 A,  126 B therebetween. For example, the conductive lines  126 A,  126 B connecting to the adjacent drivers  210 A,  210 B are physically separated by two conductive lines  126 A,  126 B therebetween. However, the disclosure is not limited thereto. The drivers  210 A and the drivers  210 B may have any suitable arrangement. For example, the conductive lines  126 A,  126 B connecting to the adjacent drivers  210 A,  210 B are immediately adjacent to each other or physically separated by one or more conductive lines  126 A,  126 B therebetween. In some embodiments, a reflow process may be performed. During the bonding process, a process temperature may be lower than 400° C. 
     Referring to  FIG. 4A ,  FIG. 4B  and  FIG. 4C , the formed structure of  FIG. 3A ,  FIG. 3B  and  FIG. 3C  is de-bonded from the carrier C 2 , to form a memory device  10 . In some embodiments, the de-bonding process includes projecting a light such as a laser light or an UV light on the de-bonding layer DB 2  (e.g., the LTHC release layer) so that the carrier C 2  can be easily removed along with the de-bonding layer DB 2 . During the de-bonding step, a tape (not shown) may be used to secure the structure before de-bonding the carrier C 2  and the de-bonding layer DB 2 . In some embodiments, a thinning process such as a grinding process is performed on the substrate  202  after de-bonding from the carrier C 2 , so as to reduce a total thickness of the formed structure. 
     In some embodiments, the memory  100  is bonded onto the circuit structure  200  over the carrier C 2 , and then the resulting structure is de-bonded from the carrier C 2 . However, the disclosure is not limited thereto. In alternative embodiments, as shown in  FIG. 5A ,  FIG. 5B  and  FIG. 5C , the circuit structure  200  is bonded onto the memory  100  over the carrier C 1 . Then, the resulting structure is de-bonded from the carrier C 1 , to form the memory device  10  as shown in  FIG. 4A ,  FIG. 4B  and  FIG. 4C . In some embodiments, a thinning process such as a grinding process is performed on the substrate  202  after bonding the circuit structure  200  to the memory  100 , so as to reduce a total thickness of the formed structure. 
     In some embodiments, the memory  100  and the circuit structure  200  are formed separately and then combined by bonding. In other words, the memory  100  and the circuit structure  200  may be formed under different process condition such as process temperature, and one would not have an impact on the other. For example, the memory  100  without the periphery circuit is fabricated under a relative high temperature such as 550° C. which may have impact on the circuit structure  200 , however, the impact is prevented since the memory  100  and the circuit structure  200  are formed separately. Accordingly, the memory and the circuit structure may be formed under the desired condition thereof, and the performance of the formed memory device is improved. 
     In some embodiments, the circuit structure  200  is formed at one side of the memory  100 . For example, the drivers  210 A,  210 B and  210 C are all disposed below or above the memory  100 . However, the disclosure is not limited thereto. In alternative embodiments, the drivers  210 A,  210 B and  210 C are formed at different sides of the memory  100 . 
       FIG. 6A  through  FIG. 10B  illustrate varying views of manufacturing a memory device in accordance with some embodiments.  FIG. 6B  and  FIG. 6C  are illustrated along reference cross-sections I-I′ and II-II′ illustrated in  FIG. 6A .  FIG. 8B  through  FIG. 10B  are illustrated along reference cross-sections III-III′ illustrated in  FIG. 8A  through  FIG. 10A . The manufacturing method is similar to the patterning method of  FIG. 1A  to  FIG. 4A  and  FIG. 1B  to  FIG. 4B , and the main difference is described as below. 
     Referring to  FIG. 6A ,  FIG. 6B  and  FIG. 6C , a memory  100  is formed over a carrier C 1 . The structure, the material and the forming process of the memory  100  are similar to those of the memory  100  as described with reference to  FIG. 1A ,  FIG. 1B ,  FIG. 1C  and  FIG. 1D , and the main difference lies in the conductive lines  126 A and the conductive lines  126 B are formed at opposite sides (i.e., upper side and bottom side) of the staircase structures ST. For example, as shown in  FIG. 6A  and  FIG. 6B , the conductive lines  126 A are disposed over the staircase structures ST, and the conductive lines  126 B are disposed below the staircase structures ST. In some embodiments, as shown in  FIG. 6C , the conductive pillars  116 B are extended into the etching stop layer  101 , to electrically connect to the conductive lines  126 B. Accordingly, the conductive contacts  122 B,  122 B′ in dielectric materials  134 ,  136  are disposed between the conductive lines  126 B and the conductive pillars  116 B to electrically connect the conductive lines  126 B and the conductive pillars  116 B. The conductive lines  126 B electrically connect the conductive pillars  116 B in the same row, for example. In some embodiments, the conductive contacts  122 B′ are disposed between the conductive pillars  116 B and the conductive contacts  122 B. In alternative embodiments, one of the conductive contact  122 B and the corresponding conductive contact  122 B′ is omitted, or the conductive contact  122 B and the corresponding conductive contact  122 B′ are formed integrally. However, the disclosure is not limited thereto. The conductive lines  126 B below the staircase structures ST may have other configurations. In some embodiments, the conductive lines  126 A are bit lines, and the conductive lines  126 B are source lines. In alternative embodiments, the conductive lines  126 A are source lines, and the conductive lines  126 B are bit lines. 
     The memory  100  may be formed by the following steps. First, the conductive lines  126 B in a dielectric material  132  are formed over the de-bonding layer DB 1 , and the conductive contacts  122 B and the conductive contacts  122 B′ are formed over the conductive lines  126 B. For example, the conductive contacts  122 B are formed in a dielectric material  134  and the conductive contacts  122 B′ are formed in a dielectric material  136 . Then, the etching stop layer  101  is formed over the dielectric material  136 . After that, the conductive lines  112 , the conductive pillars  116 A and the conductive pillars  116 B may be formed over the etching stop layer  101 . In some embodiments, the conductive pillars  116 B are formed to extend into the etching stop layer  101  while the conductive pillars  116 A are formed to stop on the top surface of the etching stop layer  101 . Then, the conductive contacts  122 A and the conductive contacts  122 C may be formed in the dielectric material  124  to electrically connect to the conductive pillars  126 A and the conductive contacts  118 , respectively. After that, the conductive lines  126 A and the conductive contacts  128  may be formed to electrically connect to the conductive contacts  122 A and the conductive contacts  122 C, respectively. 
     Referring to  FIG. 7A  and  FIG. 7B , a circuit structure  200 A is formed over a carrier C 2 , and a circuit structure  200 B is formed over a carrier C 2 ′. The circuit structure  200 A may include a plurality of drivers  210 A and a plurality drivers  210 C. The circuit structure  200 A may include a plurality of drivers  210 B. The structure, the material and the forming process of the drivers  210 A,  210 B and  210 C are similar to those of the drivers  210 A,  210 B and  210 C as described with reference to  FIG. 2B  and  FIG. 3B , and the main difference lies in the drivers  210 B are formed over the carrier C 2 ′ different from the carrier C 2  over which the drivers  210 A and  210 C are formed. In other words, the fabricating process of the drivers  210 A and  210 C and the fabricating process of the drivers  210 B are separately performed. 
     Referring to  FIG. 8A  and  FIG. 8B , the memory  100  of  FIG. 6A  is bonded to one of the circuit structure  200 A and the circuit structure  200 B. In some embodiments, the memory  100  is de-bonded and separated from the carrier C 1 , and then the memory  100  is bonded to the circuit structure  200 A over the carrier C 2 . The memory  100  is bonded onto the circuit structure  200 A through a wafer to wafer bonding process, for example. In some embodiments, the conductive lines  126 A are bonded to the conductive contacts  218 A of the drivers  210 A, and the conductive contacts  128  of the conductive lines  112  are bonded to the conductive contacts  218 C of the drivers  210 C, and the dielectric material  130  is bonded to the dielectric material  216 . Accordingly, the conductive lines  126 A are electrically connected to the drivers  210 A, and the conductive lines  112  are electrically connected to the drivers  210 C, respectively. In some embodiments, a reflow process may be performed. During the bonding process, a process temperature may be lower than 400° C. In some embodiments, a thinning process such as a grinding process is performed on the substrate  202  after de-bonding from the carrier C 2 , so as to reduce a total thickness of the formed structure. 
     Referring to  FIG. 9A  and  FIG. 9B , the circuit structure  200 B is bonded to the resulting structure of  FIG. 8A  and  FIG. 8B . In some embodiments, the circuit structure  200 B is de-bonded and separated from the carrier C 2 ′, and then the circuit structure  200 B is bonded to the memory  100  over the carrier C 2 . The circuit structure  200 B is bonded onto the memory  100  through a wafer to wafer bonding process, for example. In some embodiments, the conductive contacts  218 B of the drivers  210 B are bonded to the conductive lines  126 B, and a dielectric material  216  aside the conductive contacts  218 B is bonded to the dielectric material  132  aside the conductive lines  126 B. Accordingly, the conductive lines  126 B are electrically connected to the drivers  210 B, respectively. In some embodiments, a reflow process may be performed. During the bonding process, a process temperature may be lower than 400° C. In some embodiments, a thinning process such as a grinding process is performed on the substrate  202  after de-bonding from the carrier C 2 ′, so as to reduce a total thickness of the formed structure. In some embodiments, the circuit structure  200 B is bonded to the memory  100  after bonding the circuit structure  200 A onto the memory  100 . In alternative embodiments, the circuit structure  200 B is bonded to the memory  100  before bonding the circuit structure  200 A onto the memory  100 . 
     Referring to  FIG. 10A  and  FIG. 10B , the formed structure of  FIG. 9A  and  FIG. 9B  is de-bonded from the carrier C 1 , to form a memory device  10 . In some embodiments, the de-bonding process includes projecting a light such as a laser light or an UV light on the de-bonding layer DB 1  (e.g., the LTHC release layer) so that the carrier C 1  can be easily removed along with the de-bonding layer DB 1 . During the de-bonding step, a tape (not shown) may be used to secure the structure before de-bonding the carrier C 1  and the de-bonding layer DB 1 . 
     In some embodiments, all drivers connecting to the same type of the conductive lines are formed over the same carrier. For example, the drivers  210 A connecting to the conductive lines  126 A are all formed over the carrier C 2 , the drivers  210 B connecting to the conductive lines  126 B are all formed over the carrier C 2 , and the drivers  210 C connecting to the conductive lines  112  are all formed over the carrier C 2 ′. However, the disclosure is not limited thereto. In alternative embodiments (not shown), drivers connecting to different type of the conductive lines are formed over the same carrier. That is, two of the driver  210 A, driver  210 B and the driver  210 C may be formed over the same carrier. 
     Although the embodiments of  FIG. 1A  through  FIG. 10B  illustrate a particular pattern for the conductive pillars  116 A and  116 B, other configurations are also possible. For example, in these embodiments, the conductive pillars  116 A and  116 B have a staggered pattern. However, in other embodiments (not shown), the conductive pillars  116 A and  116 B in a same row of the array are all aligned with each other. 
     In above embodiments, the memory device is a single-sided driving structure, and the second region  204 B corresponds to one of the staircase regions  106 B and  106 C. In some embodiments, as shown in  FIG. 11A  and  FIG. 11B , the memory device  10  is a double-sided driving structure, the second regions  204 B at opposite sides of the first region  204 A correspond to the staircase region  106 B and the staircase region  106 C respectively. In such embodiments, the conductive contacts  118  are formed at both sides  112   a  and  112   b  of the conductive line  112 , and the drivers  210 C are disposed in both the second regions  204 B to electrically connect the conductive contacts  118  respectively. In some embodiments, a number of the drivers  210 C is doubled. 
       FIG. 12  illustrates a method of forming a memory device in accordance with some embodiments. Although the method is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included. 
     At act S 300 , a three dimensional memory is formed over a first carrier, the three dimensional memory including a plurality of first conductive lines.  FIGS. 1A, 1B, 1C, 1D, 6A and 6B , illustrate varying views corresponding to some embodiments of act S 300 . 
     At act S 302 , a first circuit structure is formed over a second carrier, the first circuit structure including a plurality of first drivers and a plurality of first bonding pads electrically connected to the plurality of first drivers respectively.  FIGS. 2A, 2B, 2C, 7A and 7B  illustrate varying views corresponding to some embodiments of act S 302 . 
     At act S 304 , the three dimensional memory and the first circuit structure are electrically connected by bonding the first conductive lines and the first bonding pads.  FIGS. 3A, 3B, 3C, 5A, 5B, 5C, 8A, 8B, 9A and 9B  illustrate varying views corresponding to some embodiments of act S 304 . 
     In some embodiments, the memory and the circuit structure are formed separately and then combined by bonding. Thus, the memory and the circuit structure may be formed under a desired condition thereof such as a desired process temperature, and one would not have an impact on the other. Accordingly, the performance of the formed memory device is improved. 
     In accordance with some embodiments of the present disclosure, a memory device includes a staircase structure, a plurality of first conductive contacts, a plurality of first drivers and a plurality of second conductive contacts. The staircase structure includes a plurality of first conductive lines and a plurality of first dielectric layers stacked alternately. The first conductive contacts are electrically connected to the plurality of first conductive lines respectively. The second conductive contacts are electrically connected to the plurality of first drivers respectively. The plurality of first conductive contacts and the plurality of second conductive contacts are bonded and disposed between the plurality of first conductive lines and the plurality of first drivers. 
     In accordance with alternative embodiments of the present disclosure, a memory device includes a staircase structure, a plurality of first drivers, a plurality of second conductive lines and a plurality of second drivers. The staircase structure has a first side and a second side opposite to the first side and includes a plurality of first conductive lines and a plurality of first dielectric layers stacked alternately along a direction from the first side to the second side. The first drivers are disposed at the first side of the staircase structure and electrically connected to the plurality of first conductive lines respectively. The second conductive lines are disposed at the second side and cross over the plurality of first conductive lines and the plurality of dielectric layers. The second drivers are disposed at the second side of the staircase structure and electrically connected to the second conductive lines respectively. 
     In accordance with yet alternative embodiments of the present disclosure, a method of forming a memory device includes following steps. A three dimensional memory is formed over a first carrier and the three dimensional memory includes a plurality of first conductive lines. A first circuit structure is formed over a second carrier, and the first circuit structure includes a plurality of first drivers and a plurality of first bonding pads electrically connected to the plurality of first drivers respectively. The three dimensional memory and the first circuit structure are electrically connected by bonding the plurality of first conductive lines and the plurality of the first bonding pads. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.