Patent Publication Number: US-8526228-B2

Title: 8-transistor SRAM cell design with outer pass-gate diodes

Description:
RELATED APPLICATION 
     This application is related to U.S. patent application Ser. No. 13/345,619 entitled “8-TRANSISTOR SRAM CELL DESIGN WITH SCHOTTKY DIODES”, filed even date herewith, and U.S. patent application Ser. No. 13/345,629 entitled “8-TRANSISTOR SRAM CELL DESIGN WITH INNER PASS-GATE JUNCTION DIODES”, filed even date herewith, the disclosures of which are incorporated by reference herein. 
     BACKGROUND 
     The present invention relates to 8-transistor SRAM cell designs and, more particularly, relates to an 8-transistor SRAM cell design having outer pass-gate diodes to enable column select functionality. 
     A static random access memory (SRAM) is a significant memory device due to its high speed, low power consumption and simple operation. Unlike a dynamic random access memory (DRAM) cell, the SRAM does not need to regularly refresh the stored data as SRAM uses bistable latching circuitry to store each bit. 
     As variability concerns mount in future complementary metal oxide semiconductor (CMOS) technologies, SRAM cell stability, which depends on delicately balanced transistor characteristics, becomes a significant concern. 
     In traditional 6-transistor SRAM, cells must be both stable during a read event and writeable during a write event. Ignoring redundancy, such functionality must be preserved for each cell under worst-case variation. For cell stability during a read, it is desirable to strengthen the storage inverters and weaken the pass-gates. The opposite is desired for cell writeability: a weak storage inverter and strong pass-gates. This delicate balance of transistor strength ratios can be severely impacted by device variations, which dramatically degrade stability and write margins, especially in scaled technologies. 
     In a 6-transistor SRAM cell, variability tolerance is compromised by the conflicting needs of cell read stability and writeability. Because the same pass-gate devices are used to both read and write the cell, it is inevitable that the two conditions cannot be simultaneously optimized. 
     In an 8-transistor SRAM cell, two transistors are added to create a disturb-free read mechanism. Since read and write are controlled by separate devices within the cell, the two are entirely decoupled—a level that 6-transistor SRAM cells can never reach. This widens the cell optimization space to achieve sufficient stability and writeability margins. 
     While the 8-transistor cell solves read stability issues, a similar problem arises during a write operation if column select functionality (also known as half-select, partial write, or masked write) is desired. In such a scenario, the write word line is activated, but it is desired that only some of the bits tied to this write word line are written. This is a common technique used in 6-transistor SRAM arrays to facilitate bit interleaving and array floorplanning and is achieved by appropriately biasing the bit lines in each column. Those bits that are not to be written experience a bias comparable to a read disturb. In 8-transistor SRAM, operating the memory in such a fashion would unintentionally write other bits in other columns due to the strong pass-gates employed. In existing 8-transistor SRAM designs, column select functionality is thus prohibited. 
     BRIEF SUMMARY 
     The various advantages and purposes of the exemplary embodiments as described above and hereafter are achieved by providing, according to a first aspect of the exemplary embodiments, an 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line, each of the pass-gate transistors having an outer diode between the pass-gate and the write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line; wherein the 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state while the first and second read transistors affect the signal asserted during the read operation on the read bit line coupled to the cell. 
     According to a second aspect of the exemplary embodiments, there is provided a memory device which includes a plurality of 8-transistor SRAM cells arranged in columns and rows. Each 8-transistor SRAM cell includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line, each of the pass-gate transistors having an outer diode between the pass-gate and the write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state while the first and second read transistors affect the signal asserted during the read operation on the read bit line coupled to the cell. 
     According to a third aspect of the exemplary embodiments, there is provided an integrated circuit which includes a memory device. The memory device includes: a plurality of 8-transistor SRAM cells arranged in columns and rows, with each 8-transistor SRAM cell including: two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source/drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state while the first and second read transistors affect the signal asserted during the read operation on the read bit line coupled to the cell. 
    
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
       The features of the exemplary embodiments believed to be novel and the elements characteristic of the exemplary embodiments are set forth with particularity in the appended claims. The Figures are for illustration purposes only and are not drawn to scale. The exemplary embodiments, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which: 
         FIG. 1  is a circuit schematic of an 8-transistor SRAM cell. 
         FIG. 2  is a circuit schematic of an exemplary embodiment of an 8-transistor SRAM cell. 
         FIG. 3  is a top view of a layout of an 8-transistor SRAM cell. 
         FIG. 4  is a cross-sectional view of  FIG. 3  in the direction of arrows A-A showing an exemplary embodiment. 
         FIG. 5  is a cross-sectional view of  FIG. 3  in the direction of arrows A-A showing another exemplary embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     The present exemplary embodiments are directed to an 8-transistor SRAM cell in which column select writing functionality is enabled without creating cell disturbs during column select writing. In the exemplary embodiments, the pass-gates in the 8-transistor SRAM cell are altered to permit higher performance in the pull-down (write mode) configuration and lower performance in the pull-up mode, thus retaining the write margin advantage of the 8-transistor SRAM cell. By keeping the pull-up mode for the pass-gate weak, column select writing mode is permitted without disturbing adjacent bits. 
     Referring to the Figures in more detail, and particularly referring to  FIG. 1 , there is illustrated a block diagram of an 8-transistor SRAM  100  which includes cross-coupled inverters  102  for storing a bit and pass-gates  104  for writing a bit. Bits are read through read transistors  106 . As noted previously, the two read transistors  106  are added to create a disturb-free read mechanism. Since read and write are controlled by separate devices within the 8-transistor SRAM cell, the two functions of read and write are entirely decoupled. 
     However, as also noted previously, column select functionality is prohibited in the 8-transistor SRAM cell. The reason for this is that the 8-transistor SRAM cell is optimized for writing so that any bit on a write word line may write to all cells on the write word line, whether intended or not. 
       FIG. 2  is a block diagram of an 8-transistor SRAM cell (or just cell) in accordance with an exemplary embodiment. With reference to  FIG. 2 , the cell  200  may include a plurality of transistors. A first group  204  of the plurality of transistors may be employed for storing data in the cell  200 . A second group  206  of the plurality of transistors may be employed for affecting a signal coupled to the second group  206  of the plurality of transistors. The second group  206  may be mutually exclusive from the first group  204 . 
     More specifically, the first group  204  may include a first transistor  208  (such as an N-type field effect transistor (NFET)) coupled (such as via a gate terminal) to a first word line (such as a write word line (WWL))  210  such that the first word line  210  may serve to activate the first transistor  208 . The first transistor  208  may be coupled (such as via a source/drain terminal) to the input of a first logic device  214 , such as an inverter and the output of a second logic device  216 , such as an inverter. The other source/drain terminal of transistor  208  may be coupled to a first bit line  212  (such as a write bit line (WBL)) through a diode  240 . The diode  240 , which is oriented to block current flow into the cell from the first bit line  212 , may be a separate device or, more preferably, integrated into the existing SRAM cell structure to minimize cell size. 
     Although, the first and second logic devices  214 ,  216  are shown as inverters, it should be understood that each such inverter may include a pair of coupled transistors (such as an NFET coupled with a P-type field effect transistor (PFET)). The first group  204  may include a second transistor  218 , such as an NFET, coupled (such as via a gate terminal) to the first word line  210  such that the first word line  210  may serve to activate the second transistor  218 . 
     The second transistor  218  may be coupled (such as via a source/drain terminal) to the output of the first logic device  214  and the input of the second logic device  216 . The other source/drain terminal of transistor  218  may be coupled to a second bit line  220  (such as a write bit line complement (WBLb)) through a diode  242 . The diode  242 , which is oriented to block current flow into the cell from the second bit line  220 , may be a separate device or, more preferably, integrated into the existing SRAM cell structure to avoid any area penalty. A voltage of a first node  222  at the input of the first logic device  214  and the output of the second logic device  216  may serve as a value (e.g., of a bit) stored in the cell  200 . Alternatively, a voltage at another node included in the first group  204  may serve as the value stored in the cell  200 . For example, the voltage of a second node  224  at the output of the first logic device  214  and the input of the second logic device  216  may serve as the value stored in the cell  200 . Although the first and second transistors  208 ,  218  are coupled to the same word line  210 , in some embodiments, the first and second transistors  208 ,  218  may be coupled to different word lines. In this manner, in some embodiments, the first group  204  may include six transistors and two integrated diodes. 
     The second group  206  may include a seventh transistor  226  (e.g., an NFET) of the cell  200  coupled (e.g., via a gate terminal) to a read word line (RWL)  228  such that the second word line  228  may serve to activate the seventh transistor  226 . The seventh transistor  226  may be coupled (e.g., via a drain or source terminal) to a third bit line  230  (RBL). During a read operation, the second group  206  may cause the value of a signal on the third bit line  230  to track the value stored by the cell  200  (e.g., the value of the first node  222  of the first group  204 ). Therefore, the third bit line  230  may serve as an output of the cell  200 . 
     Further, the second group  206  may include an eighth transistor  232  (e.g., NFET) of the cell  200  coupled to the seventh transistor  226  (e.g., a source or drain terminal of the seventh transistor  226 ) via a drain or source terminal. The eighth transistor  232  may be coupled (e.g., via a source or drain terminal) to a low voltage, such as ground. Additionally, the eighth transistor  232  may be coupled (e.g., via a gate terminal) to the second node  224  such that the voltage of the second node  224 , which is related to the voltage of the first node  222  that serves as the value stored in the cell  200 , may serve to activate the eighth transistor  232 . In this manner, the second group  206  may include two transistors. Although the cell  200  includes NFET transistors and logic devices, such as inverters (each of which may include an NFET coupled to a PFET), different types of transistors and/or logic devices may be employed. 
     The cell  200  may comprise one or more portions of a memory  234 . More specifically, although only one cell is shown, the memory  234  may include a plurality of cells  200  arranged into rows and/or columns. The memory  234  may form part of an integrated circuit. 
     It would be desirable to perform the column select function in an 8-transistor SRAM cell, but as noted above, it is typically prohibited because of write disturbs. It is the presence of diode  240  adjacent to pass-gate  208  and diode  242  adjacent to pass-gate  218  that allows the enablement of column select in the cell  200 . In the exemplary embodiments, the pass-gates  208  and  218  in series combination with the diodes  240  and  242  permit higher performance in the pull-down mode (writing a logical ‘0’ from the bit line into the cell) configuration and lower performance in the pull-up mode (when a logical ‘1’ on the bit line pulls up/disturbs the cell). Such asymmetric behavior retains the write margin advantage of the 8-transistor SRAM cell while providing for a way to disable writing of a cell by appropriately setting the BL voltages (i.e. column select). When a WWL  210  is activated, those bits to be written should have their WBL  212  and WBLb  220  lines set to the true and complement versions of the new data. Those bits tied to this WWL  210  that should not be written should have both WBL  212  and WBLb  220  held high—with the configured diodes blocking any charge transfer that would otherwise disturb the cell. 
       FIG. 3  presents a top-down view of an exemplary embodiment of an 8-transistor SRAM cell layout  300 , which contains active regions, well isolation regions, gate structures, and contact structures. Additional mask levels are implied and should be well understood by those skilled in the art. The exemplary cell  300  may be fabricated in a conventional semiconductor substrate. 
     As shown in  FIG. 3 , pass-gate transistor  302  and pull-down transistor  304  are formed within a connected active region  306  with no isolation between them, and pull-down transistor  308  and pass-gate transistor  310  are formed within a connected active region  312 . Pull-up transistors  314  and  316  are formed within active regions  318  and  320 , respectively. Further, read transistors  322  and  324  are formed within a connected active region  326 . The active regions  306 ,  312 ,  318 ,  320  and  326  may be formed within a semiconductor substrate and are separated from one another by dielectric isolation regions. Gate structures  328  and  330  are arranged above active region  306  to form gates of pass-gate transistor  302  and pull-down transistor  304 , respectively. Above active region  312 , gate structures  332  and  334  are arranged to form gates of pull-down transistor  308  and pass-gate transistor  310 , respectively. In a similar manner, gate structure  332  forms gates of pull-up transistor  314  and one of the read transistors  322 , gate structure  330  additionally forms the gate of pull-up transistor  316  and gate structure  336  forms the gate of the second read transistor  324 . Also shown in  FIG. 3  are contact  338  for coupling with a write word line, contact  340  for also coupling with the write word line, contact  342  for coupling with a write bit line, contact  344  for coupling with the write bit line complement, contact  346  for coupling with the read word line and contact  348  for coupling with the read bit line. 
       FIG. 4  is a cross-section of  FIG. 3  in the direction of arrows A-A′. For purposes of illustration and not limitation, semiconductor structure  400  is a semiconductor on insulator (SOI) structure and includes a semiconductor substrate  402 , an insulating layer  404  and top semiconductor on insulator (SOI) layer  406 . The insulating layer  404  may be an oxide and may be referred to as a buried oxide layer. Further shown are pass-gate transistor  310 , gate structure  334  for pass-gate transistor  310 , pull-down transistor  308  and gate structure  332  for pull-down transistor  308 . Pass-gate transistor  310  and pull-down transistor  308  are connected by active area  312  within SOI layer. 
     Pass-gate transistor  310  may have a source/drains  408  and  410  while pull-down transistor  308  may have source/drains  412  and  414 . Source/drain  410  may be connected to source/drain  412  in a shared diffusion as shown in  FIG. 4 . Connected to the various sources/drains  408 ,  410 ,  412 ,  414  may be silicide contacts  416  and metal contacts  418 . 
     As noted previously, pass-gate transistors ( 208  and  218  in  FIGS. 2 ;  302  and  310  in  FIG. 3 ) may further be connected in series with an outer diode ( 240  and  242  in  FIG. 2 ). As further noted previously, the outer diode may be a separate device with separate isolation and active regions, but may preferably be integrated into the existing SRAM cell structure to minimize cell area.  FIG. 4  illustrates a preferred exemplary embodiment where the diode  420  is formed as part of the source/drain  408  for pass-gate transistor  310 . The diode  420  may be formed by epitaxial growth of a p-type layer  422  (for example, boron or boron fluoride (BF 2 )) followed by epitaxial growth of an n-type layer  424  (for example, phosphorus or arsenic). The combination of p-type layer  422  and n-type layer  424  form a pn junction diode  420 . In order to make good electrical contact between the pass-gate source/drain region  408  and the p-type terminal  422  of diode  420 , it is important to ensure that the pn junction between these two regions be heavily doped on both sides (i.e. p+ and n+ doping) to enable a tunneling junction contact. Such junction engineering can be achieved through known silicon epitaxy techniques. While  FIG. 4  focuses on the formation of diode  420  on the source/drain terminal of pass-gate transistor  310 , it should be noted that an analogous structure can be used to form a corresponding diode on pass-gate transistor  302 , which is connected to the complementary WBL. 
     An alternative embodiment is illustrated in  FIG. 5 , in which the pn junction diode  520  may be formed without any additional process steps over that needed for many standard CMOS process flows. In many advanced technologies, n-type and p-type silicon epitaxial steps are often already used to improve the parasitic source/drain resistance of NFETs and PFETs, respectively. In such technologies, the source/drain region  508  may be exposed to both epitaxial process steps through simple adjustment of block-level masks. The p-type epitaxial layer  522  may be formed when the semiconductor wafer undergoes epitaxial growth for PFETs and the n-type epitaxial layer  524  may be formed when the semiconductor wafer undergoes epitaxial growth for NFETs. This n-type epitaxial step would likely result in raised source/drain structures  526  on the n-type source drain regions. 
     It will be apparent to those skilled in the art having regard to this disclosure that other modifications of the exemplary embodiments beyond those embodiments specifically described here may be made without departing from the spirit of the invention. Accordingly, such modifications are considered within the scope of the invention as limited solely by the appended claims.