Patent Publication Number: US-9846541-B2

Title: Memory system for controlling perforamce by adjusting amount of parallel operations

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from U.S. Provisional Application No. 62/090,766, filed on Dec. 11, 2014; the entire contents of which are incorporated herein by reference. 
    
    
     FIELD 
     Embodiments described herein relate generally to memory systems. 
     BACKGROUND 
     In some cases, drives with different performances are mounted in storage server systems of the same model, each of which includes a host and a drive that is a memory system. However, when the drives with different performances are mounted, in some cases, the storage server systems of the same model have different system performances. Therefore, it is preferable to easily change the performance of the drive. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating an example of the structure of a memory system according to a first embodiment; 
         FIG. 2  is a diagram illustrating an example of the structure of a performance control interface and a configuration table module according to the first embodiment; 
         FIG. 3  is a diagram illustrating an example of the structure of a NAND memory according to the first embodiment; 
         FIG. 4  is a diagram illustrating an example of the structure of resource usage information according to the first embodiment; 
         FIG. 5  is a diagram illustrating an example of the structure of a preset value table according to the first embodiment; 
         FIG. 6  is a diagram illustrating an example of the structure of a memory system according to a second embodiment; 
         FIG. 7  is a diagram illustrating an example of the structure of a performance control interface and a configuration table module according to the second embodiment; 
         FIG. 8  is a diagram illustrating the relationship between the temperature and performance of the memory system according to the second embodiment; 
         FIG. 9  is a diagram illustrating an example of the structure of a memory system according to a third embodiment; 
         FIG. 10  is a diagram illustrating an example of the structure of a performance control interface and a configuration table module according to the third embodiment; 
         FIG. 11  is a flowchart illustrating the procedure of the operation of the memory system according to the third embodiment; and 
         FIG. 12  is a diagram illustrating an example of the mounting of the memory system. 
     
    
    
     DETAILED DESCRIPTION 
     According to an embodiment, a memory system is provided. The memory system includes a non-volatile memory and a controller configured to control the non-volatile memory. The controller includes an interface and a control unit. The interface receives a first instruction to change the performance of the memory system as a performance control instruction from a host. In addition, the control unit controls the memory system on the basis of the performance control instruction such that the number of parallel operations of parallel operating units which are operated in parallel in the memory system is changed. 
     Hereinafter, memory systems according to embodiments will be described in detail with reference to the accompanying drawings. The invention is not limited by the embodiments. In each of the following embodiments, a case in which a memory system is a solid state drive (SSD) will be described. The memory system may be a drive, such as a hard disk drive (HDD), other than the SSD. 
     First Embodiment 
       FIG. 1  is a diagram illustrating an example of the structure of a memory system according to a first embodiment. A storage server system according to the first embodiment includes a host  60 A and a memory system  10 A. The memory system  10 A is connected to an external device such as the host (host computer)  60 A. The memory system  10 A according to this embodiment controls resources (for example, a CPU and a memory) which can be operated in parallel on the basis of an instruction from the host  60 A. The memory system  10 A adjusts (throttles) the performances (for example, the number of parallel operations) of the resources which can be operated in parallel and operates at the performance corresponding to the instruction from the host  60 A. 
     The memory system  10 A includes a NAND memory  11  and a controller  12 A. The NAND memory  11  is a storage medium that can store information in a non-volatile manner. The NAND memory  11  is a NAND flash memory which is an example of a recordable non-volatile memory. 
     The controller  12 A controls the NAND memory  11 . For example, the controller  12 A writes data to the NAND memory  11  or reads data from the NAND memory  11  in response to a command from the host  60 A. The controller  12 A includes a performance control interface (IF)  20 A, a resource control unit  41 , and a configuration table module  42 A. In addition, the controller  12 A includes a CPU  51  and a memory  52 . 
     The resources (parallel operating resources  50 ) which can be operated in parallel according to this embodiment are, for example, components forming the memory system  10 A and programs forming software. The parallel operating resources  50  include, for example, the following (1) to (4): 
     (1) A component or a program that performs information processing between the memory system  10 A and the host  60 A; 
     (2) A component or a program that performs information processing between the controller  12 A and the NAND memory  11 ; 
     (3) A component or a program that performs information processing in the controller  12 A; and 
     (4) A component or a program that performs information processing in the NAND memory  11 . 
     Specifically, the parallel operating resources  50  are, for example, the CPU  51 , the memory  52 , and the NAND memory  11 . In this embodiment, a case in which the parallel operating resources  50  are, for example, the CPU  51 , the memory  52 , and the NAND memory  11  will be described. The CPU  51  may perform the operation of the resource control unit  41 . In addition, the configuration table module  42 A may be provided in the memory  52 . 
     In this embodiment, the performances of the resources are, for example, a data read/write speed, the amount of data which is read or written, and an access patterns such as sequential and random. Specifically, the performances of the resources are, for example, the number of parallel operations, data storage capacity, an information processing speed, and the amount of information processed. In addition, examples of the information processing include arithmetic processing, a data writing process, a data reading process, and a communication process. 
     Although not illustrated in  FIG. 1 , the CPU  51  is connected to the performance control interface  20 A, the resource control unit  41 , the configuration table module  42 A, and the memory  52 . Therefore, the performance control interface  20 A is connected to the configuration table module  42 A through the CPU  51 . In addition, the performance control interface  20 A is connected to the host  60 A. The resource control unit  41  is connected to the parallel operating resources  50  and the configuration table module  42 A. 
     The performance control interface  20 A receives an instruction related to performance control (hereinafter, referred to as a performance control instruction) transmitted from the host  60 A. Specifically, the performance control interface  20 A receives, as the performance control instruction, a combination of information indicating the use resources used for operations (information for identifying use resources) (hereinafter, referred to as an available resource ID) and the number of resources for each use resource (the number of parallel operations). In the performance control instruction, for example, the type of use resource (available resource ID) and the number of parallel operations to be changed are designated. Hereinafter, in some cases, a combination of the available resource ID and the number of parallel operations is referred to as resource limit information. 
     In addition, the performance control interface  20 A receives, for example, information (a preset value which will be described below) indicating the combination of the available resource ID and the number of parallel operations or a performance index. When receiving the performance control instruction, the performance control interface  20 A transmits the performance control instruction to the CPU  51 . 
     The configuration table module  42 A stores various information tables (corresponding information). In each of the information tables, a control method corresponding to the performance control instruction is set. Each of the information tables is set for each memory system  10 A. The configuration table module  42 A stores, for example, resource usage information  45 X or a performance index table  45 C, which will be described below. The resource usage information  45 X is an information table storing the resource limit information of the resources which are actually used. The memory system  10 A operates on the basis of the set resource usage information  45 X. In the performance index table  45 C, the performance index and the available resource ID are associated with each other. 
     When receiving the performance control instruction, the CPU  51  refers to the information table corresponding to the performance control instruction among the information tables stored in the configuration table module  42 A. For example, when receiving the performance index as the performance control instruction, the CPU  51  refers to the information table (performance index table  45 C) corresponding to the performance index. The CPU  51  determines the use resource on the basis of the performance index table  45 C and the performance index. The CPU  51  stores the available resource ID of the determined use resource in the resource usage information  45 X. As such, when receiving the performance control instruction, the CPU  51  updates the resource usage information  45 X. 
     The resource control unit  41  controls the parallel operating resources  50  on the basis of the resource usage information  45 X. The resource control unit  41  changes, for example, the number of parallel operations of the parallel operating resources  50 . For example, when the NAND memory  11  is designated in the resource usage information  45 X, the resource control unit  41  limits the operation of the NAND memory  11 . 
     The memory  52  is, for example, a volatile memory. The memory  52  functions as a write buffer that stores data transmitted from the host  60 A in temporary until the data is written to the NAND memory  11 . In addition, the memory  52  functions as a storage area for storing and updating management information related to the memory system  10 A and a work area for temporarily storing the data read from the NAND memory  11 . 
     Next, the structure of the performance control interface  20 A and the configuration table module  42 A will be described.  FIG. 2  is a diagram illustrating the structure of the performance control interface and the configuration table module according to the first embodiment. The CPU  51  is connected to the performance control interface  20 A and the configuration table module  42 A. 
     The performance control interface  20 A includes a resource usage interface  25   x , a preset value setting interface  25   b , a performance index setting interface  25   c , an endurance management setting interface  25   d , and a power consumption setting interface  25   e.    
     The configuration table module  42 A stores the resource usage information  45 X, a preset value table  45 B, the performance index table  45 C, an endurance management table  45 D, and a power consumption table  45 E. 
     The resource usage information  45 X is changed during the operation of the memory system  10 A in response to a request from the host  60 A. The preset value table  45 B, the performance index table  45 C, the endurance management table  45 D, and the power consumption table  45 E may be set in advance, for example, upon shipment of the memory system  10 A, or they may be changed in response to an instruction from the host  60 A. 
     The resource usage interface  25   x  receives the resource limit information (the maximum value of the performance required for the memory system  10 A) transmitted from the host  60 A and transmits the resource limit information to the CPU  51 . The available resource ID in the resource limit information is information for identifying the resource of which parallel operations (simultaneously executed operations) is limited by an instruction from the host  60 A. The number of parallel operations in the resource limit information indicates the number of the resources allowed to work in parallel indicated by the available resource ID is operated in parallel. Therefore, when the available resource ID and the number of parallel operations (the number of use resources) are designated, the type and the number of resources of which parallel operation is limited are designated. The CPU  51  registers the resource limit information in the resource usage information  45 X. 
     The resource usage information  45 X stores information related to the resource of which parallel operation is limited. Specifically, the resource usage information  45 X stores the resource limit information (the combination of the available resource ID and the number of parallel operations) of the resource of which parallel operation is limited. When the parallel operation of a plurality of resources is limited, a plurality of sets of resource limit information is stored in the resource usage information  45 X. 
     The preset value setting interface  25   b  receives the preset value transmitted from the host  60 A and transmits the preset value to the CPU  51 . The preset value indicates a combination of the use resource (available resource ID) and the number of parallel operations under typical conditions. In this embodiment, when the preset value is designated, the use resource and the number of parallel operations are designated. 
     In the preset value table  45 B, the preset value and the resource limit information of the resource of which parallel operation is limited are associated with each other. For example, a preset value “001”, a channel, the number of channels, a bank, and the number of banks are associated with each other. In this case, when the preset value “001” is designated by the host  60 A, the operation of the channels and the banks is limited to the number of channels and the number of banks corresponding to the preset value “001”. 
     The performance index setting interface  25   c  receives the performance index transmitted from the host  60 A and transmits the performance index to the CPU  51 . The performance index is information for designating the performance of the memory system  10 A. In other words, the performance index is the performance of the memory system  10 A requested by the host  60 A. 
     Examples of the performance index include input/output per second (LOPS), megabyte per second (MB/s), read/write, and random/sequential. The LOPS is the number of reading or writing operations for the NAND memory  11  per second. In addition, MB/s is the communication speed between the host  60 A and the NAND memory  11 . 
     In the performance index table  45 C, the performance index (the type of performance and a target range) and the resource limit information of the resource of which parallel operation is limited are associated with each other. Specifically, in the performance index table  45 C, the type of performance index, the target range of the performance index, and the resource limit information are associated with each other. For example, in the performance index table  45 C, MB/s which is the type of performance index, 2000 MB/s to 2400 MB/s which is the range of the performance index, a channel, and the number of channels are associated with each other. In this embodiment, since the target range of the performance index is designated, for example, a performance error is allowed in a predetermined range. 
     The endurance management setting interface  25   d  receives endurance information transmitted from the host  60 A and transmits the endurance information to the CPU  51 . The endurance information is information (minimum endurance) about the endurance of the memory system  10 A or the NAND memory  11  requested by the host  60 A. In the endurance information, for example, a period, such as one year, three years, or five years, is designated. 
     While the memory system  10 A is being used, the reliability of each block of the NAND memory  11  deteriorates. Therefore, in the NAND memory  11 , the number of blocks (defective blocks or bad blocks) which are not available as the storage areas or the number of areas (bad areas) from which data is not read due to a large number of errors increases. For example, when the number of bad blocks or the error rate during a reading operation is greater than a predetermined value, it is determined that the endurance of the memory system  10 A has ended. 
     The endurance of the memory system  10 A may be determined on the basis of information other than the number of bad blocks. For example, the endurance of the memory system  10 A may be determined on the basis of the number of writing operations, the number of erasing operations, the number of write errors, the number of erasing errors, and the command response time of the NAND memory  11 . 
     The host  60 A may transmit, for example, the number of bad blocks, the number of bad clusters, the number of writing operations, the number of erasing operations, the number of write errors, the number of erasing errors, and the command response time of the NAND memory  11  as the endurance information to the memory system  10 A. 
     In the memory system  10 A, when the host  60 A writes data to the NAND memory  11 , the operation mode may be changed, depending on, for example, the number of bad blocks. As the operation mode of the memory system  10 A, there are the following two modes as well as the normal mode:
         A read only (RO) mode: the memory system  10 A does not receive a writing operation from the host  60 A, performs the writing operations initiated the drive by itself (for example, management information, statistical information, refresh, compaction, and wear leveling). The memory system  10 A changes to the RO mode, for example, when the number of bad blocks or the error rate during a reading operation is equal to or greater than a predetermined value; and   A write protected (WP) mode: the memory system  10 A prohibits all processes involving the writing of data to the NAND memory  11 . In the WP mode, same as in RO mode, the NAND memory  11 A returns an error message in response to all write requests from the host  60 A such that data is not written. Further in the WP mode, the memory system  10 A stops the writing operations initiated the drive by itself. Therefore, when the endurance of the memory system  10 A is close to 0%, the NAND memory  11 A can secure the data written from the host  60 A as much as possible. The memory system  10 A changes to the WP mode, for example, when the number of bad blocks or the error rate during a reading operation is not less than a predetermined value.       

     The host  60 A may transmit transition conditions to the above-mentioned operation mode to the memory system  10 A, instead of the endurance information. For example, the host  60 A may transmit a first threshold value of the number of bad blocks or the error rate during a reading operation as transition conditions to the RO mode to the memory system  10 A. In addition, the host  60 A may transmit a second threshold value of the number of bad blocks or the error rate during a reading operation as WP mode to the memory system  10 A. 
     In the endurance management table  45 D, the endurance information and the resource limit information of the resource of which parallel operation is limited are associated with each other. The memory system  10 A operates such that a normal operation (for example, a reading operation or a writing operation) can be performed during the minimum endurance defined by the endurance information. 
     The host  60 A monitors the amount of data written to the NAND memory  11  in the memory system  10 A. Then, the host  60 A limits the amount of data written to the NAND memory  11  on the basis of the amount of data written to the NAND memory  11 . For example, the host  60 A may predict the endurance of the memory system  10 A on the basis of, for example, the history of the amount of data written to the NAND memory  11 . In this case, the host  60 A voluntarily limits the amount of data written to the NAND memory  11  on the basis of the predicted endurance. 
     The power consumption setting interface  25   e  receives power consumption information from the host  60 A and transmits the power consumption information to the CPU  51 . The power consumption information is information about the maximum power consumption of the memory system  10 A allowed by the host  60 A. As the power consumption, for example, 9 W (watt) or 10 W is designated. In the power consumption table  45 E, the power consumption information and the resource limit information of the resource of which parallel operation is limited are associated with each other. 
     In the memory system  10 A, for example, power consumption varies depending on workload (for example, the amount of information processed) or an environment (for example, temperature). In this embodiment, the host  60 A designates the maximum allowable power consumption of the memory system  10 A. The power consumption information may be the amount of power consumption. 
     When receiving the resource limit information, the CPU  51  registers the resource limit information in the resource usage information  45 X. In addition, when receiving the preset value, the CPU  51  selects the resource limit information corresponding to the preset value from the preset value table  45 B and registers the selected resource limit information in the resource usage information  45 X. 
     When receiving the performance index, the CPU  51  selects the resource limit information corresponding to the performance index from the performance index table  45 C and registers the selected resource limit information in the resource usage information  45 X. In the memory system  10 A, there is a correlation between the performance and the amount of heat generated. Therefore, in the performance index table  45 C, the amount of heat generated and the resource limit information are associated with each other. In the memory system  10 A, the resource limit information corresponding to the performance index is selected and the performance and the amount of heat generated are controlled. 
     The performance index setting interface  25   c  may receive a performance control instruction indicating the amount of heat generated. In this case, information indicating the correspondence between the amount of heat generated and the resource limit information is stored in the performance index table  45 C. When receiving the performance control instruction indicating the amount of heat generated, the CPU  51  selects the resource limit information corresponding to the amount of heat generated from the performance index table  45 C and registers the selected resource limit information in the resource usage information  45 X. 
     When receiving the endurance information, the CPU  51  selects the resource limit information corresponding to the endurance information from the endurance management table  45 D and registers the selected resource limit information in the resource usage information  45 X. When receiving the power consumption information, the CPU  51  selects the resource limit information corresponding to the power consumption information from the power consumption table  45 E and registers the selected resource limit information in the resource usage information  45 X. 
     The resource control unit  41  controls the parallel operating resource  50  on the basis of the resource limit information registered in the resource usage information  45 X. The resource control unit  41  simultaneously drives a first use resource and a second use resource. The resource control unit  41  operates, for example, the first use resource with the first number in parallel and operates the second use resource with the second number in parallel. 
     Each information table stored in the configuration table module  42 A is set for each memory system  10 A. The resource usage information  45 X is updated using, for example, each information table stored in the configuration table module  42 A. Therefore, the resource control unit  41  controls the parallel operating resources  50  on the basis of the information corresponding to the host memory system  10 A and the performance control instruction. 
     In some cases, a plurality of limits (a performance index, an endurance, and power consumption) are transmitted to the resource usage interface  25   x . In this case, the CPU  51  selects the resource limit information corresponding to the most strict limitation among the resource limit information items corresponding to each limit and registers the selected resource limit information in the resource usage information  45 X. 
     Next, the structure of the NAND memory  11  which can be operated in parallel will be described.  FIG. 3  is a diagram illustrating an example of the structure of the NAND memory according to the first embodiment. The NAND memory  11  according to this embodiment is connected in parallel to the controller  12 A through eight channels (8ch: ch0 to ch7). According to this structure, in the memory system  10 A, eight channel parallel operation elements  11   a  to  11   h  can be operated in parallel. The number of channels in the NAND memory  11  is not limited to 8, but any number of channels. 
     Each of the parallel operation elements  11   a  to  11   h  includes a plurality of banks (in this case, four banks Bank0 to Bank3) which can be interleaved. Each bank includes a plurality of memory chips (in this case, two memory chips Chip0 and Chip1). Each memory chip is divided into, for example, two districts Plane0 and Plane1 each having a plurality of physical blocks. 
     Plane0 and Plane1 include independent peripheral circuits (for example, a row decoder, a column decoder, a page buffer, and a data cache). In this structure, when the memory system  10 A uses a plurality of planes in multi-plane mode, the memory system  10 A can erase, write, or read the multiple planes simultaneously. Each memory chip may be divided into four planes or it may not be divided at all. 
     As such, in the NAND memory  11 , a parallel operation can be performed by a plurality of channels, a parallel operation can be performed by a plurality of banks, and a parallel operation can be performed by a plurality of planes in multi-plane mode. When the number of channels is 8, the number of banks is 4, and the number of planes is 2, a maximum of 64 physical blocks can be operated in parallel. 
     Next, the use resources and the number of parallel operations set in the resource usage information  45 X will be described.  FIG. 4  is a diagram illustrating an example of the structure of the resource usage information according to the first embodiment. In the resource usage information  45 X, the available resource ID and the number of parallel operations are associated with each other.  FIG. 4  illustrates a case in which an available resource name is stored in the resource usage information  45 X. However, the available resource name may be omitted. 
     In the resource usage information  45 X, for example, an available resource ID “001” and the number of parallel operations N 1  are associated with each other. Therefore, the resource control unit  41  operates N 1  CPUs  51  corresponding to the available resource ID “001” among the CPUs  51  in parallel. 
     The use resources registered in the resource usage information  45 X are, for example, a CPU, a NAND memory, a channel, a bank, a plane (not illustrated), a volatile memory, and a process. 
     The CPUs registered in the resource usage information  45 X are, for example, the CPUs  51 . The number of parallel operations N 1  of the CPUs is the number of CPUs which perform information processing using, for example, a lookup table (LUT). The LUT stores the correspondence relationship between a logical address and a physical address. The number of CPUs registered in the resource usage information  45 X is, for example, 1 to 6. 
     The NAND memory registered in the resource usage information  45 X is the NAND memory  11 . The number of parallel operations N 2  of the NAND memory is, for example, the number of chips which are operated in parallel among the chips forming the NAND memory  11 . 
     The channels registered in the resource usage information  45 X are the channels of the NAND memory  11 . The number of parallel operations N 3  of the channels is the number of channels which are operated in parallel among the channels. The number of channels registered in the resource usage information  45 X is, for example, 1 to 8. 
     The banks registered in the resource usage information  45 X are the banks of the NAND memory  11 . The number of parallel operations N 4  of the banks is the number of banks which are operated in parallel among the banks. The number of banks registered in the resource usage information  45 X is, for example, 1 to 4. 
     The volatile memory registered in the resource usage information  45 X is, for example, the memory  52 . The number of parallel operations N 5  of the volatile memories is the number of memories which are operated in parallel among the memories  52 . The processes registered in the resource usage information  45 X are, for example, processes related to reading or writing. The number of parallel operations N 6  of the processes is the number of processes (tasks) which are operated in parallel. 
     The use resources (the use resources which operate with the maximum number of parallel operations) which have no limit in the number of parallel operations may not be registered in the resource usage information  45 X. In other words, only the use resources which have a limit in the number of parallel operations may be registered in the resource usage information  45 X. 
     Next, the use resources which are set to the preset value and the number of use resources will be described.  FIG. 5  is a diagram illustrating an example of the structure of the preset value table. In the preset value table  45 B, the preset value and use limit information (the use resources and the number of parallel operations) are associated with each other. 
     For example, a preset value P 1 , four CPUs  51  which are operated in parallel, and two NAND memories  11  which are operated in parallel are associated with each other. Therefore, when the preset value P 1  is designated by the host  60 A, four CPUs  51  and two NAND memories  11  are operated in parallel in the memory system  10 A. 
     The preset value table  45 B is preset on the basis of, for example, the parallel operation of the memory system  10 A and characteristics during a parallel operation. One or more use limit information items which give priority at least one of the endurance, performance, temperature, and power consumption of the memory system  10 A are registered in the preset value table  45 B. For example, use limit information which gives priority to random write and use limit information which gives priority to sequential write are set. 
     In the memory system  10 A, when an operation starts, a performance control instruction is transmitted from the host  60 A to the performance control interface  20 A. The performance control instruction is, for example, the resource limit information, the preset value, the performance index, the endurance information, or the power consumption information. 
     The performance control interface  20 A transmits the received performance control instruction to the CPU  51 . Then, the CPU  51  updates the resource usage information  45 X on the basis of the performance control instruction and the information table stored in the configuration table module  42 A. Then, the resource control unit  41  controls the parallel operating resources  50  on the basis of the resource usage information  45 X. 
     Then, in the memory system  10 A, an operation corresponding to the performance control instruction transmitted from the host  60 A is performed. In other words, in the memory system  10 A, the performance, the amount of heat generated, endurance, power consumption, and temperature suitable for an operation environment are dynamically controlled. For example, the performance can be adjusted depending on the purpose of use of the storage server system to adjust the operation endurance of the memory system  10 A. 
     In the memory system  10 A, when a setting target value is the temperature or the communication speed, it is difficult to perform control in some cases. Therefore, the memory system  10 A may give levels to the resources which can be operated in parallel and may perform a control process corresponding to the level. 
     For example, the parallel operation of the banks has four levels 1 to 4 (banks). In addition, the parallel operation of the channels has five levels 1, 2, 4, 8, and 16. The parallel operation of the CPUs  51  has six levels 1 to 6. The number of combinations of the parallel operations is the product of the levels. A level value suitable for an operation environment can be set empirically or by learning from the operation of the storage server system. For example, the result of each combination (level value) and the performance index are associated with each other. Therefore, when the performance index is designated, an operation is performed with the level value corresponding to the performance index. 
     In this embodiment, the performance control interface  20 A includes a plurality of interfaces. However, the performance control interface  20 A may include at least one interface. In addition, the configuration table module  42 A may include tables corresponding to the interfaces in the performance control interface  20 A. 
     In this embodiment, the memory system  10 A controls the number of parallel operations of the resources. However, the memory system  10 A may control, for example, the frequency of access to the resources or the waiting time. The waiting time for the resource is the intentionally inserted delay-slot before starting a predetermined process such as information processing or input-output processing, is performed in the memory system  10 A. The delay-slot is controlled to change the performance of the memory system  10 A. In addition, the host  60 A may transmit an instruction to limit the resources which are operated in parallel in stages to the performance control interface  20 A. In this case, the resource control unit  41  limits the resources which are operated in parallel in stages. 
     The host  60 A may predict the necessary performance required for the memory system  10 A, on the basis of the flow rate of data (the amount of data transmitted and received) per unit time or an event (for example, an outside temperature variation or a specific command). The host  60 A predicts the performance required for the memory system  10 A on the basis of, for example, at least one of the flow rate of data per unit time and an event. Then, the host  60 A transmits a performance control instruction based on the predicted required performance to the memory system  10 A. In other words, the host  60 A predicts the required performance of the memory system  10 A and transmits a performance control instruction corresponding to the prediction result to the memory system  10 A. 
     In this embodiment, the memory system  10 A performs an operation on the basis of the performance control instruction from the host  60 A. However, when a predetermined condition is established, the memory system  10 A may voluntarily perform the operation. 
     The host  60 A may transmit resource limit information for limiting the storage capacity of the NAND memory  11  to the memory system  10 A. For example, the host  60 A may transmit, to the memory system  10 A, resource limit information for limiting the storage capacity of the NAND memory  11  from 1 terabytes to 500 gigabytes. The host  60 A can reduce the storage capacity of the NAND memory  11  to change a drive write per day (DWPD) which is one of the performance indexes. The DWPD is the ratio of the allowable amount of data written per day to the user capacity of the memory system  10 A provided to the host  60 A. In addition, the host  60 A may transmit the DWPD as the performance index to the performance index setting interface  25   c.    
     The host  60 A may transmit resource limit information for adjusting an error correction level to the memory system  10 A. In addition, an error correction circuit and the error correction level may be registered as the use resources in the resource usage information  45 X. 
     As such, the memory system  10 A according to the first embodiment includes the NAND memory  11 , which is a non-volatile memory, and the controller  12 A which controls the NAND memory  11 . The controller  12 A includes the performance control interface  20 A which receives the performance control instruction from the host  60 A. In addition, the controller  12 A includes the resource control unit  41  which controls the memory system  10 A on the basis of the performance control instruction. In the memory system  10 A, the resource control unit  41  performs an operation corresponding to the performance control instruction transmitted from the host  60 A. 
     Therefore, according to the first embodiment, the memory system  10 A performs an operation corresponding to the performance control instruction transmitted from the host  60 A. Therefore, it is possible to easily change the performance of the memory system  10 A. 
     A control process corresponding to the temperature or power consumption is performed for the parallel operating resources  50 . Therefore, it is possible to easily adjust an appropriate balance between the performance and the amount of heat generated so as to respond to a change in environment during the operation of the memory system  10 A. In addition, it is possible to easily select whether to give priority to the endurance or the performance, on the basis of the purpose of use of the storage server system. 
     Second Embodiment 
     Next, a second embodiment will be described with reference to  FIGS. 6 to 8 . In a storage server system according to the second embodiment, a host transmits a performance control instruction on the basis of the internal temperature of a memory system. Then, the memory system performs an operation corresponding to the performance control instruction (required temperature information) related to the temperature from the host. 
       FIG. 6  is a diagram illustrating an example of the structure of the memory system according to the second embodiment. Among the components illustrated in  FIG. 6 , components having the same functions as those in the memory system  10 A according to the first embodiment illustrated in  FIG. 1  are denoted by the same reference numerals and the description thereof will not be repeated. 
     The storage server system according to the second embodiment includes a host  60 B and a memory system  10 B. The memory system  10 B according to this embodiment controls the resources which can be operated in parallel, on the basis of required temperature information (performance control instruction) from the host  60 B. 
     The memory system  10 B includes a NAND memory  11  and a controller  12 B. The controller  12 B includes a performance control interface  20 B, a resource control unit  41 , and a configuration table module  42 B. In addition, the controller  12 B includes a CPU  51  and a memory  52 . 
     Although not illustrated in  FIG. 6 , the CPU  51  is connected to the performance control interface  20 B, the resource control unit  41 , the configuration table module  42 B, and the memory  52 . Therefore, the performance control interface  20 B is connected to the configuration table module  42 B through the CPU  51 . In addition, the performance control interface  20 B is connected to the host  60 B. The resource control unit  41  is connected to parallel operating resources  50  and the configuration table module  42 B. 
     The performance control interface  20 B receives a performance control instruction transmitted from the host  60 B. Specifically, when receiving the performance control instruction, the performance control interface  20 B transmits the performance control instruction to the CPU  51 . 
     The configuration table module  42 B stores various information tables. The configuration table module  42 B stores resource usage information  45 X and a temperature table  46  which will be described below. 
     The controller  12 B according to this embodiment includes a temperature measurement unit  30 . The temperature measurement unit  30  measures the internal temperature of the controller  12 B or the internal temperature of the NAND memory  11 . The temperature measurement unit  30  is connected to the host  60 B and transmits the measurement result of the temperature to the host  60 B. The temperature measurement unit  30  may be provided outside the controller  12 B or outside the memory system  10 B. The host  60 B according to this embodiment transmits a performance control instruction corresponding to the measurement result of the temperature to the performance control interface  20 B. 
     Next, the structure of the performance control interface  20 B and the configuration table module  42 B will be described.  FIG. 7  is a diagram illustrating the structure of the performance control interface and the configuration table module according to the second embodiment. The performance control interface  20 B includes a resource usage interface  25   x  and a temperature setting interface  26 . The configuration table module  42 B stores the resource usage information  45 X and the temperature table  46 . The temperature table  46  may be preset, for example, upon shipment of the memory system  10 B or it may be changed by an instruction from the host  60 B. 
     The temperature setting interface  26  receives the required temperature information transmitted from the host  60 B and transmits the required temperature information to the CPU  51 . The required temperature information is information for designating the maximum (upper limit) temperature of the memory system  10 B. In the temperature table  46 , the upper limit of the temperature required for the memory system  10 B and the resource limit information of the resources of which parallel operation is limited are associated with each other. Therefore, the memory system  10 B controls the parallel operations of the resources corresponding to the resource limit information in the temperature table  46  and operates at the temperature corresponding to the resource limit information. 
     In the memory system  10 B, when an operation starts, the temperature measurement unit  30  measures the temperature of the controller  12 B (NAND memory  11 ). Then, the temperature measurement unit  30  transmits the measurement result of the temperature to the host  60 B. Then, the host  60 B transmits a performance control instruction (required temperature information) corresponding to the measurement result of the temperature to the performance control interface  20 B. The host  60 B derives the required temperature information which is transmitted from the host  60 B to the performance control interface  20 B on the basis of, for example, the measurement result of the temperature. In addition, the required temperature information which is transmitted from the host  60 B to the performance control interface  20 B may be generated on the basis of an instruction from the user. 
     The performance control interface  20 B transmits the received required temperature information to the CPU  51 . Then, the CPU  51  updates the resource usage information  45 X on the basis of the required temperature information and the temperature table  46 . Then, the resource control unit  41  controls the parallel operating resources  50  on the basis of the resource usage information  45 X. 
     In this way, in the memory system  10 B, an operation corresponding to the performance control instruction transmitted from the host  60 B is performed. In other words, in the memory system  10 B, for example, the temperature or the amount of heat generated which is suitable for an operation environment is dynamically controlled. 
       FIG. 8  is a diagram illustrating the relationship between the temperature and the performance in the memory system according to the second embodiment.  FIG. 8  illustrates temperature/performance characteristics  80  of the memory system  10 B. In the graph illustrated in  FIG. 8 , the horizontal axis indicates the temperature of the memory system  10 B and the vertical axis indicates the performance (parallelism) of the memory system  10 B. 
     In the memory system  10 B, when an operation is continuously performed in a normal state X 1 , the temperature increases to T 1 . In addition, when the operation is continuously performed, the temperature increases to T 2 . The performance of the memory system  10 B is adjusted to an adjusted state X 2 , for example, at the time when the temperature increases to T 2  (st 1 ). Specifically, the performance of the memory system  10 B is degraded from the normal state X 1  to the adjusted state X 2 . 
     Then, in the memory system  10 B, when the operation is continuously performed in the adjusted state X 2 , the temperature increases to T 3  in some cases. In this case, the memory system  10 B changes to a shutdown state X 3  (st 2 ). Then, in the memory system  10 B, when the temperature is reduced to T 4  less than T 2  (T 1 &lt;T 4 &lt;T 2 ), the memory system  10 B is adjusted to the adjusted state X 2  (st 3 ). The magnitude relationship among T 1  to T 4  is not limited to the example illustrated in  FIG. 8 . For example, T 4  may be greater than T 2  or T 4  may be equal to T 2 . In addition, T 2  may be equal to T 3  or T 1  may be equal to T 4 . 
     In the memory system  10 B, when the operation is continuously performed in the adjusted state X 2 , the temperature is reduced to T 1  in some cases. In this case, the memory system  10 B changes to the operation in the normal state X 1  (st 4 ). In the memory system  10 B, the process from (st 1 ) to (st 4 ) is performed according to a change in temperature. 
     The host  60 B transmits a performance control instruction which can achieve the temperature/performance characteristics  80  to the memory system  10 B. For example, the host  60 B transmits parameters (for example, T 1  to T 4  and X 1  to X 3 ) for defining the curves (hysteresis) of st 1  to st 4  to the memory system  10 B. The parameters for defining the curves of st 1  to st 4  may be registered in the memory system  10 B in advance. In this case, the memory system  10 B performs an operation corresponding to the temperature/performance characteristics  80 , without receiving the performance control instruction from the host  60 B. 
     The installation environment of the storage server system varies depending on an installation place, such as weather, a region, and air-conditioning equipment. Therefore, the amount of heat which can be dissipated from the memory system  10 B varies depending on the memory system  10 B. Therefore, there is a demand for controlling the amount of heat generated from the same storage server system according to an environment. In this embodiment, since the memory system  10 B includes the temperature setting interface  26 , it is possible to easily maintain the appropriate operation environment of the storage server system. 
     In this embodiment, the temperature measurement unit  30  transmits the measurement result of the temperature to the host  60 B. However, the measurement result of the temperature may be transmitted to the host  60 B through the performance control interface  20 B. In addition, the performance control interface  20 B may not include the resource usage interface  25   x.    
     The host  60 B may predict a temperature change on the basis of the measurement result of the temperature. In this case, the host  60 B transmits a performance control instruction corresponding to the prediction result of the temperature change to the performance control interface  20 B. 
     The memory system  10 B may perform feedback control on the basis of the measurement result of the temperature such that the preset temperature or performance is obtained. In this case, the host  60 B transmits a feedback parameter as the performance control instruction to the memory system  10 B. 
     As such, the memory system  10 B according to the second embodiment includes the temperature measurement unit  30 . In the memory system  10 B, the temperature measurement unit  30  transmits the measurement result of the temperature to the host  60 B and the performance control interface  20 B receives the performance control instruction (required temperature information) corresponding to the measurement result of the temperature from the host  60 B. Then, in the memory system  10 B, the resource control unit  41  performs an operation corresponding to the required temperature information from the host  60 B. 
     Therefore, according to the second embodiment, the memory system  10 B performs an operation with the resources corresponding to the required temperature information from the host  60 B. Therefore, it is possible to easily change the temperature of the memory system  10 B or the amount of heat generated from the memory system  10 B. 
     Third Embodiment 
     Next, a third embodiment will be described with reference to  FIGS. 9 to 11 . In a storage server system according to the third embodiment, a memory system calculates its power consumption (predicted power consumption which will be described below) on the basis of the required performance (for example, bandwidth or throughput) from the host. Then, the host transmits a performance control instruction related to power consumption to the memory system on the basis of the calculated predicted power consumption. The memory system performs an operation corresponding to the performance control instruction from the host. 
       FIG. 9  is a diagram illustrating an example of the structure of the memory system according to the third embodiment. Among the components illustrated in  FIG. 9 , components having the same functions as those in the memory systems  10 A and  10 B are denoted by the same reference numerals and the description thereof will not be repeated. 
     The storage server system according to the third embodiment includes a host  60 C and a memory system  10 C. The host  60 C according to this embodiment transmits the required performances, such as the type of reading/writing operations, IOPS (the number of reading/writing operations per second), or MB/s (communication speed), to the memory system  10 C. For example, the host  60 C transmits the predetermined value of MB/s to the memory system  10 C when sequential access is performed and transmits the predetermined value of the IOPS and a command size (TL: a transfer length; for example, 4 KB or 128 KB) to the memory system  10 C when random access is performed. 
     When receiving predicted power consumption (watt) corresponding to the required performance from the memory system  10 C, the host  60 C transmits a performance control instruction (maximum allowable power consumption) corresponding to the received predicted power consumption to the memory system  10 C. 
     The memory system  10 C according to this embodiment controls the resources which can be operated in parallel on the basis of the performance control instruction from the host  60 C. The memory system  10 C includes a NAND memory  11  and a controller  12 C. 
     The controller  12 C includes a performance control interface  20 C, a resource control unit  41 , a configuration table module  42 C, and a power consumption calculation unit  31 . In addition, the controller  12 C includes a CPU  51  and a memory  52 . 
     Although not illustrated in  FIG. 9 , the CPU  51  is connected to the power consumption calculation unit  31 , the performance control interface  20 C, the resource control unit  41 , the configuration table module  42 C, and the memory  52 . Therefore, the performance control interface  20 C is connected to the configuration table module  42 C through the CPU  51 . In addition, the performance control interface  20 C is connected to the host  60 C and the power consumption calculation unit  31 . The resource control unit  41  is connected to parallel operating resources  50  and the configuration table module  42 C. 
     The performance control interface  20 C receives the required performance transmitted from the host  60 C. Specifically, the performance control interface  20 C transmits the required performance, such as throughput, received from the host  60 C to the power consumption calculation unit  31 . 
     The performance control interface  20 C receives the performance control instruction transmitted from the host  60 C. Specifically, when receiving power consumption (maximum allowable power consumption which will be described below) which is the performance control instruction, the performance control interface  20 C transmits the maximum allowable power consumption to the CPU  51 . The configuration table module  42 C stores resource usage information  45 X and a power consumption table  47  which will be described below. 
     The controller  12 C includes the power consumption calculation unit  31 . The power consumption calculation unit  31  calculates predicted power consumption corresponding to the required performance from the host  60 C. The power consumption calculation unit  31  calculates the predicted power consumption corresponding to the required performance, using, for example, an information table (not illustrated) in which the required performance and power consumption are associated with each other. The information table used by the power consumption calculation unit  31  is an information table which is set for each memory system  10 C. Therefore, the power consumption calculation unit  31  calculates the predicted power consumption of the memory system  10 C. The information table used by the power consumption calculation unit  31  is set for each memory system  10 C, for example, when the memory system  10 C is manufactured. 
     The power consumption calculation unit  31  transmits the predicted power consumption corresponding to the required performance to the host  60 C through the performance control interface  20 C. The power consumption calculation unit  31  may transmit the predicted power consumption corresponding to the required performance to the host  60 C, without passing through the performance control interface  20 C. 
     Next, the structure of the performance control interface  20 C and the configuration table module  42 C will be described.  FIG. 10  is a diagram illustrating the structure of the performance control interface and the configuration table module according to the third embodiment. The performance control interface  20 C includes a resource usage interface  25   x  and a power consumption setting interface  27 . The configuration table module  42 C stores the resource usage information  45 X and the power consumption table  47 . The power consumption table  47  may be preset, for example, upon shipment of the memory system  10 C or it may be changed by an instruction from the host  60 C. 
     The power consumption setting interface  27  transmits the required performance transmitted from the host  60 C to the power consumption calculation unit  31 . In addition, the power consumption setting interface  27  transmits a performance control instruction for the maximum allowable power consumption transmitted from the host  60 C to the CPU  51 . 
     The required performance transmitted from the host  60 C is information for designating the performance of the memory system  10 C. The performance control instruction transmitted from the host  60 C is information for designating the maximum allowable power consumption of the memory system  10 C. 
     In the power consumption table  47 , the maximum allowable power consumption required for the memory system  10 C is associated with the resource limit information of the resources of which parallel operation is limited. Therefore, the memory system  10 C controls the parallel operation of the resources corresponding to the resource limit information stored in the power consumption table  47  and operates with the maximum allowable power consumption corresponding to the resource limit information. 
     Next, the procedure of the operation of the memory system  10 C will be described.  FIG. 11  is a flowchart illustrating the procedure of the operation of the memory system according to the third embodiment. In the storage server system including the memory system  10 C, when an operation starts, the host  60 C transmits the required performance to the controller  12 C (Step S 10 ). The power consumption setting interface  27  receives the required performance from the host  60 C and transmits the required performance to the power consumption calculation unit  31 . 
     Then, the power consumption calculation unit  31  of the controller  12 C calculates predicted power consumption corresponding to the required performance (Step S 20 ). Then, the controller  12 C notifies the calculated predicted power consumption to the host  60 C through the power consumption setting interface  27  (Step S 30 ). 
     Then, the host  60 C designates the maximum allowable power consumption allowed to the memory system  10 C on the basis of the predicted power consumption from the controller  12 C and transmits the maximum allowable power consumption to the performance control interface  20 C of the controller  12 C. In other words, the host  60 C designates the maximum allowable power consumption of the controller  12 C (Step S 40 ). The host  60 C designates the maximum allowable power consumption which is transmitted from the host  60 C to the performance control interface  20 C on the basis of, for example, the predicted power consumption from the controller  12 C. The maximum allowable power consumption which is transmitted from the host  60 C to the performance control interface  20 C may be generated on the basis of an instruction from the user. 
     The performance control interface  20 C transmits the received maximum allowable power consumption to the CPU  51 . Then, the CPU  51  updates the resource usage information  45 X on the basis of the maximum allowable power consumption and the power consumption table  47 . Then, the resource control unit  41  controls the parallel operating resources  50  on the basis of the resource usage information  45 X (Step S 50 ). 
     In this way, in the memory system  10 C, an operation corresponding to the performance control instruction from the host  60 C is performed. In other words, in the memory system  10 C, power consumption suitable for an operation environment is dynamically controlled. 
     The host  60 C may designate the maximum allowable power consumption, without receiving the maximum allowable power consumption calculated by the controller  12 C. In this case, the host  60 C may transmit the designated maximum allowable power consumption to the CPU  51 , without passing through the performance control interface  20 C. In addition, the performance control interface  20 C may not include the resource usage interface  25   x.    
     As such, the memory system  10 C according to the third embodiment includes the power consumption calculation unit  31 . The host  60 C transmits the required performance to the memory system  10 C. In the memory system  10 C, the power consumption calculation unit  31  calculates predicted power consumption corresponding to the required performance and transmits the predicted power consumption to the host  60 C. When the performance control interface  20 C receives the performance control instruction (power consumption instruction) designating the maximum allowable power consumption from the host  60 C, the resource control unit  41  performs an operation corresponding to the maximum allowable power consumption instruction from the host  60 C. 
     Therefore, according to the third embodiment, the memory system  10 C performs an operation with the resources corresponding to the maximum allowable power consumption designated by the host  60 C. Therefore, it is possible to easily change the power consumption of the memory system  10 C. 
     Fourth Embodiment 
       FIG. 12  is a diagram illustrating an example of the mounting of a memory system. Here, a case in which the memory system  10 A is mounted will be described. The memory systems  10 B and  10 C have the same mounting structure as the memory system  10 A. 
     The memory system  10 A is mounted in, for example, a server system  100 . The server system  100  has a structure in which a disk array  200  and a rack-mount server  300  are connected to each other by a communication interface  400 . The communication interface  400  can have any standard. The rack-mount server  300  includes one or more hosts  60 A mounted on a server rack. The disk array  200  includes one or more memory system  10 A and one or more hard disk units  4  which are mounted on a server rack. The disk array  200  includes a power supply  3  and the power supply  3  supplies power to each unit mounted on the disk array  200  through a backplane (not illustrated). In the disk array  200 , for example, one or more memory systems  10 A are used as caches of one or more hard disk units  4 . In the disk array  200 , a storage controller unit (not shown) may be mounted which is forming a RAID over one or more hard disk units  4 . 
     In recent years, there has been a demand for a technique which matches the performances of the drivers of the server systems in order to mount the drivers with difference performances in the server systems of the same model. In addition, there has been a demand for a technique which suppresses the performance of a new-generation high-performance drive and mounts the new-generation high-performance drive in a previous-generation server system. This is because there is a demand for a technique which reduces costs, ensures components, and improves maintainability, without changing the performance of the server system. In addition, since there is a tradeoff relation between the performance and endurance of an SSD, there is a demand for adjusting the performance and endurance according to the purpose of use of the server system. 
     There is a method which defines a temporal delay in a data path when a drive is manufactured and statically adjusts the performance of the drive. In this method, whenever the performance is adjusted, it is necessary to remanufacture the drive or to update the firmware of the drive. Therefore, it takes a lot of time and effort to set the optimal performance value. 
     In addition, there is a method in which a drive detects a change in a predetermined environment (for example, a high temperature environment) and voluntarily limits the resources to be accessed. In this method, since the limit of the resources is determined for each drive, it is difficult to achieve the same performance between a plurality of drives. 
     The memory systems  10 A to  10 C according to the first to third embodiments can change the performances with ease in response to the requests from the hosts  60 A to  60 C, respectively. Therefore, even when the server system  100  is formed by different types of memory systems, it is possible to unify the performances of the memory systems and to obtain the server system  100  with the same performance. 
     For example, when a first server system  100  is formed using the memory system  10 A and a second server system  100  is formed using the memory system  10 B, the performance of the memory system  10 A is adjusted to be the same as the performance of the memory system  10 B. Therefore, the first server system  100  and the second server system  100  have the same performance. As such, different generations of drives with different performances or drivers with different performances which are provided from different vendors can be mounted in the same server system. 
     As such, according to the fourth embodiment, the memory systems  10 A to  10 C perform operations at the performances designated by the hosts  60 A to  60 C, respectively. Therefore, even when the drivers with different performances are provided in the server system  100 , it is possible to equalize the performances between the server systems  100 . 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.