Patent Publication Number: US-2023163197-A1

Title: Semiconductor Device and Method of Manufacture

Description:
PRIORITY 
     This application is a continuation-in-part of U.S. Pat. Application No. 17/854,599, filed on Jun. 30, 2022, entitled “Semiconductor Device and Method of Manufacture,” which is a continuation of U.S. Pat. Application No. 17/072,719, filed on Oct. 16, 2020, entitled “Semiconductor Device and Method of Manufacture,” now U.S. Pat. No. 11,437,492, issued on Sep. 6, 2022, which claims the benefit of U.S. Provisional Application No. 63/027,618, filed on May 20, 2020, which applications are hereby incorporated herein by reference. 
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. 
     The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    illustrates an example of a nanostructure field-effect transistor (nano-FET) in a three-dimensional view, in accordance with some embodiments. 
         FIGS.  2 ,  3 ,  4 ,  5 ,  6 A,  6 B,  7 A,  7 B,  8 A,  8 B,  9 A,  9 B,  10 A,  10 B,  11 A,  11 B,  11 C,  11 D,  11 E,  11 F,  11 G,  11 H,  11 I, 12 A,  12 B,  12 C,  12 D,  13 A,  13 B,  13 C,  13 D,  14 A,  14 B,  14 C,  15 A,  15 B,  16 A,  16 B,  17 A,  17 B,  18 A,  18 B,  19 A,  19 B,  19 C,  20 A,  20 B,  20 C,  21 A,  21 B, and  21 C  are cross-sectional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments. 
         FIGS.  22 A,  22 B,  23 A, and  23 B  illustrate embodiments using an enhanced first spacer layer and second spacer layer, in accordance with some embodiments. 
         FIG.  24    illustrates an example of a fin field-effect transistor (finFET) in a three-dimensional view, in accordance with some embodiments. 
         FIGS.  25 ,  26 ,  27 ,  28 ,  29 ,  30 ,  31 A,  31 B,  32 A,  32 B,  33 A,  33 B,  33 C,  33 D,  34 A,  34 B,  35 A,  35 B,  36 A,  36 B,  37 A,  37 B,  37 C,  38 A,  38 B,  39 A, and  39 B  illustrate embodiments utilizing enhanced spacers, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Embodiments are described below in a particular context, a die comprising nano-FETs made using a 5 nm processing node. Various embodiments may be applied, however, to dies comprising other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, or the like) in lieu of or in combination with the nano-FETs and any suitable process node, such as the 3 nm process node. 
       FIG.  1    illustrates an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs, or the like) in a three-dimensional view, in accordance with some embodiments. The nano-FETs comprise nanostructures  55  (e.g., nanosheets, nanowire, or the like) over fins  66  on a substrate  50  (e.g., a semiconductor substrate), wherein the nanostructures  55  act as channel regions for the nano-FETs. The nanostructure  55  may include p-type nanostructures, n-type nanostructures, or a combination thereof. STI regions  68  are disposed between adjacent fins  66 , which may protrude above and from between neighboring STI regions  68 . Although the STI regions  68  are described/illustrated as being separate from the substrate  50 , as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although a bottom portion of the fins  66  are illustrated as being single, continuous materials with the substrate  50 , the bottom portion of the fins  66  and/or the substrate  50  may comprise a single material or a plurality of materials. In this context, the fins  66  refer to the portion extending between the neighboring STI regions  68 . 
     Gate dielectric layers  100  are over top surfaces of the fins  66  and along top surfaces, sidewalls, and bottom surfaces of the nanostructures  55 . Gate electrodes  102  are over the gate dielectric layers  100 . Epitaxial source/drain regions  92  are disposed on the fins  66  on opposing sides of the gate dielectric layers  100  and the gate electrodes  102 . 
       FIG.  1    further illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of a gate electrode  98  and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source/drain regions  92  of a nano-FET. Cross-section B-B′ is perpendicular to cross-section A-A′ and is parallel to a longitudinal axis of a fin  66  of the nano-FET and in a direction of, for example, a current flow between the epitaxial source/drain regions  92  of the nano-FET. Cross-section C-C′ is parallel to cross-section A-A′ and extends through epitaxial source/drain regions of the nano-FETs. Subsequent figures refer to these reference cross-sections for clarity. 
     Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs or in fin field-effect transistors (FinFETs). 
       FIG.  2    through  21 C are cross-sectional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.  FIGS.  2  through  5 ,  6 A,  11 A,  13 A,  14 A,  15 A,  16 A,  17 A,  18 A,  19 A, and  20 A  illustrate reference cross-section A-A′ illustrated in  FIG.  1   .  FIGS.  6 B,  7 B,  8 B,  9 B,  10 B,  11 B,  11 C,  13 B,  14 B,  15 B,  16 B,  17 B,  18 B,  19 B, and  20 B  illustrate reference cross-section B-B′ illustrated in  FIG.  1   .  FIGS.  7 A,  8 A,  9 A,  10 A,  11 A,  13 C,  19 C, and  20 C  illustrate reference cross-section C-C′ illustrated in  FIG.  1   . 
     In  FIG.  2   , a substrate  50  is provided. The substrate  50  may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate  50  may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate  50  may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. 
     The substrate  50  has an n-type region  50 N and a p-type region  50 P. The n-type region  50 N can be for forming n-type devices, such as NMOS transistors, e.g., n-type nano-FETs, and the p-type region  50 P can be for forming p-type devices, such as PMOS transistors, e.g., p-type nano-FETs. The n-type region  50 N may be physically separated from the p-type region  50 P (as illustrated by divider  20 ), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region  50 N and the p-type region  50 P. Although one n-type region  50 N and one p-type region  50 P are illustrated, any number of n-type regions  50 N and p-type regions  50 P may be provided. 
     Further in  FIG.  2   , a multi-layer stack  64  is formed over the substrate  50 . The multi-layer stack  64  includes alternating layers of first semiconductor layers  51 A-C (collectively referred to as first semiconductor layers  51 ) and second semiconductor layers  53 A-C (collectively referred to as second semiconductor layers  53 ). For purposes of illustration and as discussed in greater detail below, the second semiconductor layers  53  will be removed and the first semiconductor layers  51  will be patterned to form channel regions of nano-FETs in the p-type region  50 P. Also, the first semiconductor layers  51  will be removed and the second semiconductor layers  53  will be patterned to form channel regions of nano-FETs in the n-type regions  50 N. Nevertheless, in some embodiments the first semiconductor layers  51  may be removed and the second semiconductor layers  53  may be patterned to form channel regions of nano-FETs in the n-type region  50 N, and the second semiconductor layers  53  may be removed and the first semiconductor layers  51  may be patterned to form channel regions of nano-FETs in the p-type regions  50 P. In still other embodiments, the first semiconductor layers  51  may be removed and the second semiconductor layers  53  may be patterned to form channel regions of nano-FETS in both the n-type region  50 N and the p-type region  50 P. In other embodiments, the second semiconductor layers  53  may be removed and the first semiconductor layers  51  may be patterned to form channel regions of nano-FETs in both the n-type region  50 N and the p-type region  50 P. 
     The multi-layer stack  64  is illustrated as including three layers of each of the first semiconductor layers  51  and the second semiconductor layers  53  for illustrative purposes. In some embodiments, the multi-layer stack  64  may include any number of the first semiconductor layers  51  and the second semiconductor layers  53 . Each of the layers of the multi-layer stack  64  may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In various embodiments, the first semiconductor layers  51  may be formed of a first semiconductor material suitable for p-type nano-FETs, such as silicon germanium or the like, and the second semiconductor layers  53  may be formed of a second semiconductor material suitable for n-type nano-FETs, such as silicon, silicon carbon, or the like. The multi-layer stack  64  is illustrated as having a bottommost semiconductor layer suitable for p-type nano-FETs for illustrative purposes. In some embodiments, multi-layer stack  64  may be formed such that the bottommost layer is a semiconductor layer suitable for n-type nano-FETs. 
     The first semiconductor materials and the second semiconductor materials may be materials having a high-etch selectivity to one another. As such, the first semiconductor layers  51  of the first semiconductor material may be removed without significantly removing the second semiconductor layers  53  of the second semiconductor material in the n-type region  50 N, thereby allowing the second semiconductor layers  53  to be patterned to form channel regions of n-type NSFETS. Similarly, the second semiconductor layers  53  of the second semiconductor material may be removed without significantly removing the first semiconductor layers  51  of the first semiconductor material in the p-type region  50 P, thereby allowing the first semiconductor layers  51  to be patterned to form channel regions of p-type NSFETS. 
     Referring now to  FIG.  3   , fins  66  are formed in the substrate  50  and nanostructures  55  are formed in the multi-layer stack  64 , in accordance with some embodiments. In some embodiments, the nanostructures  55  and the fins  66  may be formed in the multi-layer stack  64  and the substrate  50 , respectively, by etching trenches in the multi-layer stack  64  and the substrate  50 . The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Forming the nanostructures  55  by etching the multi-layer stack  64  may further define first nanostructures  52 A-C (collectively referred to as the first nanostructures  52 ) from the first semiconductor layers  51  and define second nanostructures  54 A-C (collectively referred to as the second nanostructures  54 ) from the second semiconductor layers  53 . The first nanostructures  52  and the second nanostructures  54  may further be collectively referred to as nanostructures  55 . 
     The fins  66  and the nanostructures  55  may be patterned by any suitable method. For example, the fins  66  and the nanostructures  55  may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins  66 . 
       FIG.  3    illustrates the fins  66  in the n-type region  50 N and the p-type region  50 P as having substantially equal widths for illustrative purposes. In some embodiments, widths of the fins  66  in the n-type region  50 N may be greater or thinner than the fins  66  in the p-type region  50 P. Further, while each of the fins  66  and the nanostructures  55  are illustrated as having a consistent width throughout, in other embodiments, the fins  66  and/or the nanostructures  55  may have tapered sidewalls such that a width of each of the fins  66  and/or the nanostructures  55  continuously increases in a direction towards the substrate  50 . In such embodiments, each of the nanostructures  55  may have a different width and be trapezoidal in shape. 
     In  FIG.  4   , shallow trench isolation (STI) regions  68  are formed adjacent the fins  66 . The STI regions  68  may be formed by depositing an insulation material over the substrate  50 , the fins  66 , and nanostructures  55 , and between adjacent fins  66 . The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material is silicon oxide formed by an FCVD process. An annealing process may be performed once the insulation material is formed. In an embodiment, the insulation material is formed such that excess insulation material covers the nanostructures  55 . Although the insulation material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not separately illustrated) may first be formed along a surface of the substrate  50 , the fins  66 , and the nanostructures  55 . Thereafter, a fill material, such as those discussed above may be formed over the liner. 
     A removal process is then applied to the insulation material to remove excess insulation material over the nanostructures  55 . In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the nanostructures  55  such that top surfaces of the nanostructures  55  and the insulation material are level after the planarization process is complete. 
     The insulation material is then recessed to form the STI regions  68 . The insulation material is recessed such that upper portions of fins  66  in the regions  50 N and the region  50 P protrude from between neighboring STI regions  68 . Further, the top surfaces of the STI regions  68  may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions  68  may be formed flat, convex, and/or concave by an appropriate etch. The STI regions  68  may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the fins  66  and the nanostructures  55 ). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used. 
     The process described above with respect to  FIGS.  2  through  4    is just one example of how the fins  66  and the nanostructures  55  may be formed. In some embodiments, the fins  66  and/or the nanostructures  55  may be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate  50 , and trenches can be etched through the dielectric layer to expose the underlying substrate  50 . Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins  66  and/or the nanostructures  55 . The epitaxial structures may comprise the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials. In some embodiments where epitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and/or subsequent implantations, although in situ and implantation doping may be used together. 
     Additionally, the first semiconductor layers  51  (and resulting first nanostructures  52 ) and the second semiconductor layers  53  (and resulting second nanostructures  54 ) are illustrated and discussed herein as comprising the same materials in the p-type region  50 P and the n-type region  50 N for illustrative purposes only. As such, in some embodiments one or both of the first semiconductor layers  51  and the second semiconductor layers  53  may be different materials or formed in a different order in the p-type region  50 P and the n-type region  50 N. 
     Further in  FIG.  4   , appropriate wells (not separately illustrated) may be formed in the fins  66 , the nanostructures  55 , and/or the STI regions  68 . In embodiments with different well types, different implantation steps for the n-type region  50 N and the p-type region  50 P may be achieved using a photoresist or other masks (not separately illustrated). For example, a photoresist may be formed over the fins  66  and the STI regions  68  in the n-type region  50 N and the p-type region  50 P. The photoresist is patterned to expose the p-type region  50 P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region  50 P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region  50 N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration in a range from about  10   13  atoms/cm 3  to about  10   14  atoms/cm 3 . After the implant, the photoresist is removed, such as by an acceptable ashing process. 
     Following or prior to the implantation(s) of the p-type region  50 P, a photoresist or other masks (not separately illustrated) is formed over the fins  66 , the nanostructures  55 , and the STI regions  68  in the p-type region  50 P and the n-type region  50 N. The photoresist is patterned to expose the n-type region  50 N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region  50 N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region  50 P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration in a range from about 10 13  atoms/cm 3  to about 10 14  atoms/cm 3 . After the implant, the photoresist may be removed, such as by an acceptable ashing process. 
     After the implantation(s) of the n-type region  50 N and the p-type region  50 P, an annealing may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together. 
     In  FIG.  5   , a dummy dielectric layer  70  is formed on the fins  66  and/or the nanostructures  55 . The dummy dielectric layer  70  may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer  72  is formed over the dummy dielectric layer  70 , and a mask layer  74  is formed over the dummy gate layer  72 . The dummy gate layer  72  may be deposited over the dummy dielectric layer  70  and then planarized, such as by a CMP. The mask layer  74  may be deposited over the dummy gate layer  72 . The dummy gate layer  72  may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer  72  may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer  72  may be made of other materials that have a high etching selectivity from the etching of isolation regions. The mask layer  74  may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer  72  and a single mask layer  74  are formed across the n-type region  50 N and the p-type region  50 P. It is noted that the dummy dielectric layer  70  is shown covering only the fins  66  and the nanostructures  55  for illustrative purposes only. In some embodiments, the dummy dielectric layer  70  may be deposited such that the dummy dielectric layer  70  covers the STI regions  68 , such that the dummy dielectric layer  70  extends between the dummy gate layer  72  and the STI regions  68 . 
       FIGS.  6 A through  18 B  illustrate various additional steps in the manufacturing of embodiment devices.  FIGS.  6 A,  7 A,  8 A,  9 A,  10 A,  11 A,  12 A,  12 C,  13 A,  13 C,  14 A,  15 A, and  18 A  illustrate features in either the regions  50 N or the regions  50 P. In  FIGS.  6 A and  6 B , the mask layer  74  (see  FIG.  5   ) may be patterned using acceptable photolithography and etching techniques to form masks  78 . The pattern of the masks  78  then may be transferred to the dummy gate layer  72  and to the dummy dielectric layer  70  to form dummy gates  76  and dummy gate dielectrics  71 , respectively. The dummy gates  76  cover respective channel regions of the fins  66 . The pattern of the masks  78  may be used to physically separate each of the dummy gates  76  from adjacent dummy gates  76 . The dummy gates  76  may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective fins  66 . 
     In  FIGS.  7 A and  7 B , a first spacer layer  80  and a second spacer layer  82  are formed over the structures illustrated in  FIGS.  6 A and  6 B , respectively. The first spacer layer  80  and the second spacer layer  82  will be subsequently patterned to act as spacers for forming self-aligned source/drain regions. In  FIGS.  7 A and  7 B , the first spacer layer  80  is formed on top surfaces of the STI regions  68 ; top surfaces and sidewalls of the fins  66 , the nanostructures  55 , and the masks  78 ; and sidewalls of the dummy gates  76  and the dummy gate dielectric  71 . The second spacer layer  82  is deposited over the first spacer layer  80 . The first spacer layer  80  may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, using techniques such as thermal oxidation or deposited by CVD, ALD, or the like. The second spacer layer  82  may be formed of a material having a different etch rate than the material of the first spacer layer  80 , such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like. 
     After the first spacer layer  80  is formed and prior to forming the second spacer layer  82 , implants for lightly doped source/drain (LDD) regions (not separately illustrated) may be performed. In embodiments with different device types, similar to the implants discussed above in  FIG.  4   , a mask, such as a photoresist, may be formed over the n-type region  50 N, while exposing the p-type region  50 P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins  66  and nanostructures  55  in the p-type region  50 P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region  50 P while exposing the n-type region  50 N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins  66  and nanostructures  55  in the n-type region  50 N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities in a range from about 1×10 15  atoms/cm 3  to about 1×10 19  atoms/cm 3 . An annealing may be used to repair implant damage and to activate the implanted impurities. 
     In  FIGS.  8 A and  8 B , the first spacer layer  80  and the second spacer layer  82  are etched to form first spacers  81  and second spacers  83 . As will be discussed in greater detail below, the first spacers  81  and the second spacers  83  act to self-aligned subsequently formed source drain regions, as well as to protect sidewalls of the fins  66  and/or nanostructure  55  during subsequent processing. The first spacer layer  80  and the second spacer layer  82  may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. In some embodiments, the material of the second spacer layer  82  has a different etch rate than the material of the first spacer layer  80 , such that the first spacer layer  80  may act as an etch stop layer when patterning the second spacer layer  82  and such that the second spacer layer  82  may act as a mask when patterning the first spacer layer  80 . For example, the second spacer layer  82  may be etched using an anisotropic etch process wherein the first spacer layer  80  acts as an etch stop layer, wherein remaining portions of the second spacer layer  82  form second spacers  83  as illustrated in  FIG.  8 A . Thereafter, the second spacers  83  acts as a mask while etching exposed portions of the first spacer layer  80 , thereby forming first spacers  81  as illustrated in  FIG.  8 A . 
     As illustrated in  FIG.  8 A , the first spacers  81  and the second spacers  83  are disposed on sidewalls of the fins  66  and/or nanostructures  55 . As illustrated in  FIG.  8 B , in some embodiments, the second spacer layer  82  may be removed from over the first spacer layer  80  adjacent the masks  78 , the dummy gates  76 , and the dummy gate dielectrics  71 , and the first spacers  81  are disposed on sidewalls of the masks  78 , the dummy gates  76 , and the dummy gate dielectrics  60 . In other embodiments, a portion of the second spacer layer  82  may remain over the first spacer layer  80  adjacent the masks  78 , the dummy gates  76 , and the dummy gate dielectrics  71 . 
     It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the first spacers  81  may be patterned prior to depositing the second spacer layer  82 ), additional spacers may be formed and removed, and/or the like. Furthermore, the n-type and p-type devices may be formed using different structures and steps. 
     In  FIGS.  9 A and  9 B , first recesses  86  are formed in the fins  66 , the nanostructures  55 , and the substrate  50 , in accordance with some embodiments. Epitaxial source/drain regions will be subsequently formed in the first recesses  86 . The first recesses  86  may extend through the first nanostructures  52  and the second nanostructures  54 , and into the substrate  50 . As illustrated in  FIG.  9 A , top surfaces of the STI regions  58  may be level with bottom surfaces of the first recesses  86 . In various embodiments, the fins  66  may be etched such that bottom surfaces of the first recesses  86  are disposed below the top surfaces of the STI regions  68 ; or the like. The first recesses  86  may be formed by etching the fins  66 , the nanostructures  55 , and the substrate  50  using anisotropic etching processes, such as RIE, NBE, or the like. The first spacers  81 , the second spacers  83 , and the masks  78  mask portions of the fins  66 , the nanostructures  55 , and the substrate  50  during the etching processes used to form the first recesses  86 . A single etch process or multiple etch processes may be used to etch each layer of the nanostructures  55  and/or the fins  66 . Timed etch processes may be used to stop the etching of the first recesses  86  after the first recesses  86  reach a desired depth. 
     In  FIGS.  10 A and  10 B , portions of sidewalls of the layers of the multi-layer stack  64  formed of the first semiconductor materials (e.g., the first nanostructures  52 ) exposed by the first recesses  86  are etched to form sidewall recesses  88  in the n-type region  50 N, and portions of sidewalls of the layers of the multi-layer stack  56  formed of the second semiconductor materials (e.g., the second nanostructures  54 ) exposed by the first recesses  86  are etched to form sidewall recesses  88  in the p-type region  50 P. Although sidewalls of the first nanostructures  52  and the second nanostructures  54  in sidewall recesses  88  are illustrated as being straight in  FIG.  10 B , the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching or the like. The p-type region  50 P may be protected using a mask (not shown) while etchants selective to the first semiconductor materials are used to etch the first nanostructures  52  such that the second nanostructures  54  and the substrate  50  remain relatively unetched as compared to the first nanostructures  52  in the n-type region  50 N. Similarly, the n-type region  50 N may be protected using a mask (not shown) while etchants selective to the second semiconductor materials are used to etch the second nanostructures  54  such that the first nanostructures  52  and the substrate  50  remain relatively unetched as compared to the second nanostructures  54  in the p-type region  50 P. In an embodiment in which the first nanostructures  52  include, e.g., SiGe, and the second nanostructures  54  include, e.g., Si or SiC, a dry etch process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH), or the like may be used to etch sidewalls of the first nanostructures  52  in the n-type region  50 N, and a dry etch process with hydrogen fluoride, another fluorine-based etchant, or the like may be used to etch sidewalls of the second nanostructures  54  in the p-type region  50 P. 
     In  FIGS.  11 A- 11 C , first inner spacers  90  are formed in the sidewall recess  88 . The first inner spacers  90  may be formed by depositing an inner spacer layer  264  (not separately illustrated in  FIGS.  11 A- 11 C  but illustrated as an intermediate in  FIG.  11 I  below) over the structures illustrated in  FIGS.  10 A and  10 B . The first inner spacers  90  act as isolation features between subsequently formed source/drain regions and a gate structure. As will be discussed in greater detail below, source/drain regions will be formed in the first recesses  86 , while the first nanostructures  52  in the n-type region  50 N and the second nanostructures  54  in the p-type region  50 P will be replaced with corresponding gate structures. 
       FIGS.  11 D- 11 E  illustrate a deposition system  200  that may be utilized to form the material for the inner spacer layer  264 . In an embodiment the deposition system  200  comprises a deposition chamber  203  to receive precursor materials from a first precursor delivery system  205  and a second precursor delivery system  206  and form the material for the inner spacer layer  264 . In an embodiment the first precursor delivery system  205  and the second precursor delivery system  206  may work in conjunction with one another to supply the various different precursor materials to a deposition chamber  203 . However, the first precursor delivery system  205  and the second precursor delivery system  206  may have physical components that are similar with each other. 
     For example, the first precursor delivery system  205  and the second precursor delivery system  206  may each include a gas supply  207  and a flow controller  209  (labeled in  FIG.  11 D  with regards to the first precursor delivery system  205  but not labeled for clarity with respect to the second precursor delivery system  206 ). In an embodiment in which the first precursor is stored in a gaseous state, the gas supply  207  may supply the first precursor to the deposition chamber  203 . The gas supply  207  may be a vessel, such as a gas storage tank, that is located either locally to the deposition chamber  203  or else may be located remotely from the deposition chamber  203 . In another embodiment, the gas supply  207  may be a facility that independently prepares and delivers the first precursor to the flow controller  209 . Any suitable source for the first precursor may be utilized as the gas supply  207 , and all such sources are fully intended to be included within the scope of the embodiments. 
     The gas supply  207  may supply the desired precursor to the flow controller  209 . The flow controller  209  may be utilized to control the flow of the precursor to the precursor gas controller  213  and, eventually, to the deposition chamber  203 , thereby also helping to control the pressure within the deposition chamber  203 . The flow controller  209  may be, e.g., a proportional valve, a modulating valve, a needle valve, a pressure regulator, a mass flow controller, combinations of these, or the like. However, any suitable method for controlling and regulating the flow of the gas may be utilized, and all such components and methods are fully intended to be included within the scope of the embodiments. 
     However, as one of ordinary skill in the art will recognize, while the first precursor delivery system  205  and the second precursor delivery system  206  have been described herein as having identical components, this is merely an illustrative example and is not intended to limit the embodiments in any fashion. Any type of suitable precursor delivery system, with any type and number of individual components identical to or different from any of the other precursor delivery systems within the deposition system  200 , may be utilized. All such precursor systems are fully intended to be included within the scope of the embodiments. 
     Additionally, in an embodiment in which the first precursor is stored in a solid or liquid state, the gas supply  207  may store a carrier gas and the carrier gas may be introduced into a precursor canister (not separately illustrated), which stores the first precursor in the solid or liquid state. The carrier gas is then used to push and carry the first precursor as it either evaporates or sublimates into a gaseous section of the precursor canister before being sent to the precursor gas controller  213 . Any suitable method and combination of units may be utilized to provide the first precursor, and all such combination of units are fully intended to be included within the scope of the embodiments. 
     The first precursor delivery system  205  and the second precursor delivery system  206  may supply their individual precursor materials into a precursor gas controller  213 . The precursor gas controller  213  connects and isolates the first precursor delivery system  205  and the second precursor delivery system  206  from the deposition chamber  203  in order to deliver the desired precursor materials to the deposition chamber  203 . The precursor gas controller  213  may include such devices as valves, flow meters, sensors, and the like to control the delivery rates of each of the precursors, and may be controlled by instructions received from the control unit  215  (described further below with respect to  FIG.  11 E ). 
     The precursor gas controller  213 , upon receiving instructions from the control unit  215 , may open and close valves so as to connect one or more of the first precursor delivery system  205  and the second precursor delivery system  206  to the deposition chamber  203  and direct a desired precursor material through a manifold  216 , into the deposition chamber  203 , and to a showerhead  217 . The showerhead  217  may be utilized to disperse the chosen precursor material(s) into the deposition chamber  203  and may be designed to evenly disperse the precursor material in order to minimize undesired process conditions that may arise from uneven dispersal. In an embodiment the showerhead  217  may have a circular design with openings dispersed evenly around the showerhead  217  to allow for the dispersal of the desired precursor material into the deposition chamber  203 . 
     However, as one of ordinary skill in the art will recognize, the introduction of precursor materials to the deposition chamber  203  through a single showerhead  217  or through a single point of introduction as described above is intended to be illustrative only and is not intended to be limiting to the embodiments. Any number of separate and independent showerheads  217  or other openings to introduce precursor materials into the deposition chamber  203  may be utilized. All such combinations of showerheads and other points of introduction are fully intended to be included within the scope of the embodiments. 
     The deposition chamber  203  may receive the desired precursor materials and expose the precursor materials to the structure, and the deposition chamber  203  may be any desired shape that may be suitable for dispersing the precursor materials. In the embodiment illustrated in  FIG.  11 D , the deposition chamber  203  has a cylindrical sidewall and a bottom. However, the deposition chamber  203  is not limited to a cylindrical shape, and any other suitable shape, such as a hollow square tube, an octagonal shape, or the like, may be utilized. Furthermore, the deposition chamber  203  may be surrounded by a housing  219  made of material that is inert to the various process materials. As such, while the housing  219  may be any suitable material that can withstand the chemistries and pressures involved in the deposition process, in an embodiment the housing  219  may be steel, stainless steel, nickel, aluminum, alloys of these, combinations of these, and like. 
     Within the deposition chamber  203  the substrate  50  may be placed on a mounting platform  221  in order to position and control the substrate  50  during the deposition processes. The mounting platform  221  may include heating mechanisms in order to heat the substrate  50  during the deposition processes. Furthermore, while a single mounting platform  221  is illustrated in  FIG.  11 D , any number of mounting platforms  221  may additionally be included within the deposition chamber  203 . 
     Additionally, the deposition chamber  203  and the mounting platform  221  may be part of a cluster tool system (not shown). The cluster tool system may be used in conjunction with an automated handling system in order to position and place the substrate  50  into the deposition chamber  203  prior to the deposition processes, position and hold the substrate  50  during the deposition processes, and remove the substrate  50  from the deposition chamber  203  after the deposition processes. 
     The deposition chamber  203  may also have an exhaust outlet  225  for exhaust gases to exit the deposition chamber  203 . A vacuum pump  231  may be connected to the exhaust outlet  225  of the deposition chamber  203  in order to help evacuate the exhaust gases. The vacuum pump  231 , under control of the control unit  215 , may also be utilized to reduce and control the pressure within the deposition chamber  203  to a desired pressure and may also be utilized to evacuate precursor materials from the deposition chamber  203  in preparation for the introduction of the next precursor material. 
       FIG.  11 E  illustrates an embodiment of the control unit  215  that may be utilized to control the precursor gas controller  213  and the vacuum pump  231  (as illustrated in  FIG.  11 D ). The control unit  215  may be any form of computer processor that can be used in an industrial setting for controlling process machines. In an embodiment the control unit  215  may comprise a processing unit  201 , such as a desktop computer, a workstation, a laptop computer, or a dedicated unit customized for a particular application. The control unit  215  may be equipped with a display  243  and one or more input/output components  245 , such as instruction outputs, sensor inputs, a mouse, a keyboard, printer, combinations of these, or the like. The processing unit  201  may include a central processing unit (CPU)  246 , memory  248 , a mass storage device  250 , a video adapter  254 , and an I/O interface  256  connected to a bus  258 . 
     The bus  258  may be one or more of any type of several bus architectures including a memory bus or memory controller, a peripheral bus, or video bus. The CPU  246  may comprise any type of electronic data processor, and the memory  248  may comprise any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM). The mass storage device  250  may comprise any type of storage device configured to store data, programs, and other information and to make the data, programs, and other information accessible via the bus  258 . The mass storage device  250  may comprise, for example, one or more of a hard disk drive, a magnetic disk drive, or an optical disk drive. 
     The video adapter  254  and the I/O interface  256  provide interfaces to couple external input and output devices to the processing unit  201 . As illustrated in  FIG.  11 E , examples of input and output devices include the display  243  coupled to the video adapter  254  and the I/O component  245 , such as a mouse, keyboard, printer, and the like, coupled to the I/O interface  256 . Other devices may be coupled to the processing unit  201 , and additional or fewer interface cards may be utilized. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. The processing unit  201  also may include a network interface  260  that may be a wired link to a local area network (LAN) or a wide area network (WAN)  262  and/or a wireless link. 
     It should be noted that the control unit  215  may include other components. For example, the control unit  215  may include power supplies, cables, a motherboard, removable storage media, cases, and the like. These other components, although not shown in  FIG.  11 E , are considered part of the control unit  215 . 
     The deposition system  200  may be utilized to deposit the inner spacer layer  264 . In an embodiment the inner spacer layer  264  may be a dielectric material such as SiCN, silicon nitride, or SiCON, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. Additionally, the material of the inner spacer layer  264  may be a hybrid film comprising one or more of the dielectric materials. The dielectric material may be deposited using atomic layer deposition (ALD), although any other suitable deposition process, such as chemical vapor deposition, may also be used. 
     In an embodiment in which the desired dielectric material is SiCN formed through atomic layer deposition, the formation of the inner spacer layer  264  may be initiated by putting a first precursor material into the first precursor delivery system  205 . For example, in an embodiment in which the desired dielectric material is desired to be a material such as silicon carbon nitride, the first precursor may be a material such as ammonia (NH 3 ), N 2 H 2 , or N 2 . However, any suitable first precursor may be utilized. 
     Additionally, a second precursor material may be placed into the second precursor delivery system  206 . In an embodiment the second precursor material is a material that can work in conjunction with the product of the first precursor material to form a monolayer of the desired material. In an embodiment in which the inner spacer layer  264  is desired to be silicon carbon nitride and the first precursor material is ammonia, the second precursor material may be a material such as trichloro[(trichlorosilyl)methyl]silane, dichlorosilane (DCS) or hexachlorodisilane (HCD). However, any suitable material may be utilized. 
     Once the first precursor material and the second precursor material have been placed into the first precursor delivery system  205  and the second precursor delivery system  206 , respectively, the formation of the inner spacer layer  264  may be initiated by the control unit  215  sending an instruction to the precursor gas controller  213  to connect the first precursor delivery system  205  to the deposition chamber  203 . Once connected, the first precursor delivery system  205  can deliver the first precursor material to the showerhead  217  through the precursor gas controller  213  and the manifold  216 . The showerhead  217  can then disperse the first precursor material into the deposition chamber  203 , wherein the first precursor material can be adsorbed and react with each with the exposed surfaces. 
     In the embodiment to form a layer of silicon carbon nitride, the first precursor material may be flowed into the deposition chamber  203  at a flow rate of between about 0.2 sccm and about 5 slm, with a carrier gas flow rate of between about 0.2 sccm and about 1 slm. Additionally, the deposition chamber  203  may be held at a pressure of between about 0.5 torr and about 10 torr, and a temperature of between about 500° C. and about 650° C. The process of an ALD cycle may continue for a time period of between about 3 s and about 60 s. However, as one of ordinary skill in the art will recognize, these process conditions are only intended to be illustrative, as any suitable process conditions may be utilized while remaining within the scope of the embodiments. 
       FIG.  11 F  illustrates that, in the embodiment in which a layer of silicon carbon nitride is desired to be formed using ammonia, under these process conditions the ammonia will react with the exposed surfaces in order to provide a surface wherein nitrogen is chemically bonded to the underlying surface while the opposite surface is terminated with hydrogen atoms which are exposed to the ambient atmosphere within the deposition chamber  203 . Additionally, the reaction of the ammonia with the underlying structures will be self-limiting, providing a single layer of molecules once this step is completed. 
     After the self-limiting reaction has finished, the deposition chamber  203  may be purged of the first precursor material. For example, the control unit  215  may instruct the precursor gas controller  213  to disconnect the first precursor delivery system  205  (containing the first precursor material to be purged from the deposition chamber  203 ) and to connect a purge gas delivery system  214  to deliver a purge gas to the deposition chamber  203 . In an embodiment the purge gas delivery system  214  may be a gaseous tank or other facility that provides a purge gas such as nitrogen, argon, xenon, or other gas to the deposition chamber  203 , for a purge flow of between about 2 slm and about 20 slm, such as about 10 slm for a time period of between about 0.01 s and about 30 s, such as about 1 second. Additionally, the control unit  215  may also initiate the vacuum pump  231  in order to apply a pressure differential to the deposition chamber  203  to aid in the removal of the first precursor material. The purge gas, along with the vacuum pump  231 , may purge the first precursor material from the deposition chamber  203 . 
     After the purge of the first precursor material has been completed, the introduction of the second precursor material (e.g., trichloro[(trichlorosilyl)methyl]silane) to the deposition chamber  203  may be initiated by the control unit  215  sending an instruction to the precursor gas controller  213  to disconnect the purge gas delivery system  214  and to connect the second precursor delivery system  206  (containing the second precursor material) to the deposition chamber  203 . Once connected, the second precursor delivery system  206  can deliver the second precursor material to the showerhead  217 . The showerhead  217  can then disperse the second precursor material into the deposition chamber  203 . 
     In the embodiment discussed above to form a layer of silicon carbon nitride with trichloro[(trichlorosilyl)methyl]silane and ammonia, the trichloro[(trichlorosilyl)methyl]silane may be introduced into the deposition chamber  203  at a flow rate of between about 0.2 sccm and about 5 slm, for about 20 seconds. Additionally, the deposition chamber  203  may be held at a pressure of between about 0.5 torr and about 5 torr, and at a temperature of between about 500° C. and about 650° C. However, as one of ordinary skill in the art will recognize, these process conditions are only intended to be illustrative, as any suitable process conditions may be utilized while remaining within the scope of the embodiments. 
       FIG.  11 G  illustrates that, in the embodiment in which a layer of silicon carbon nitride is desired to be formed using ammonia, under these process conditions the trichloro[(trichlorosilyl)methyl]silane will react with the exposed surfaces in order to provide a surface wherein silicon is chemically bonded to the underlying surface while the opposite surface is terminated with chlorine atoms which are exposed to the ambient atmosphere within the deposition chamber  203 . Additionally, the reaction of the trichloro[(trichlorosilyl)methyl]silane with the underlying structures will be self-limiting, providing a single layer of molecules once this step is completed. 
       FIG.  11 H  illustrates that, after the monolayer of the desired material, e.g., silicon carbon nitride, has been formed, the deposition chamber  203  may be purged (leaving behind the monolayer of the desired material on the substrate  50 ) using, e.g., a purge gas from the purge gas delivery system  214  for about one second. After the deposition chamber  203  has been purged, a first cycle for the formation of the desired material has been completed, and a second cycle similar to the first cycle may be started. For example, the repeated cycle may introduce the first precursor material, purge with the purge gas, pulse with the second precursor, and purge with the purge gas. 
     As can be seen, each cycle of the first precursor material and the second precursor material can deposit another layer of SiCN. Additionally, each cycle additionally resets the exposed surface so that the exposed surface is prepared to receive the next cycle of the first precursor material or the second precursor material. These cycles may be repeated between about 30 times and about 100 times to form the inner spacer layer  264  to a thickness of between about 20 and about 60 Å. 
     Optionally, once the material of the inner spacer layer  264  has been formed, or at any suitable time between the cycles, a cleaning gas may be introduced over the material of the inner spacer layer  264 . In an embodiment the cleaning gas may be a dry gas such as hydrogen fluoride (HF). The cleaning process may be performed at a temperature of about 100° C. However, any suitable cleaning gas and process conditions may be utilized. 
       FIG.  11 I  illustrates a close-up view of the inner spacer layer  264  as it extends into the sidewall recesses  88  between adjacent layers of the second nanostructures  54 C and makes contact with the first nanostructures  52 C which have been recessed (see, e.g.,  FIGS.  10 A- 10 B ). As can be seen, the deposition process will grow from each of the exposed surfaces of the second nanostructures  54 C and the first nanostructures  52 C to mostly fill the sidewall recesses  88 . However, the deposition process may also not fill the sidewall recesses  88  completely, leaving a void or seam  266  within the material of the inner spacer layer  264 , which seam  266  can extend into the sidewall recesses  88 . If left alone, etchants from subsequent etching processes (described further below) will enter the seam  266  and cause undesirable etching, which can lead to defects and a reduction in yield. 
     To help ameliorate these effects,  FIG.  12 A  illustrates a furnace  300  that may be utilized to perform a first annealing process after the inner spacer layer  264  has been deposited. The furnace  300  may comprise an external body  301  that encloses a central cavity  303 . The external body  301  may be shaped as a cylinder with a closed upper end and an open lower end to allow for the introduction and removal of plurality of the substrates  50  (e.g., as part of a semiconductor wafer) into and out of the furnace  300 . The external body  301  of the furnace may be formed from a heat-resistant material such as quartz, silicon-carbide, mullite, combinations of these, or the like in order to retain and redirect thermal energy towards the central cavity  303 . 
     Within the external body  301  a series of heaters  305  controlled by a controller  307  are located. The series of heaters  305  may be utilized to control the temperature within the central cavity  303  and to heat the substrates  50  as they reside within the central cavity  303 . In an embodiment the heaters  305  may be resistive heaters, although any suitable type of heater, such as radiative heaters using steam, radiative heaters using a burning hydrocarbon, or any other suitable element for transferring heat, may be utilized. 
     The controller may be, e.g., a computer with a processor, memory, and input/output ports utilized to run a control program to control the heat within the furnace  300 . Additionally, the controller  307  may have one or more temperature sensors  309  in order to provide heating information to the controller  307 . The temperature sensors  309  may be, e.g., a thermocouple installed within the central cavity  303  to monitor the temperature of the central cavity  303  and adjust the series of heaters  305  accordingly to obtain and maintain the desired annealing temperature. However, any suitable type of sensor may be utilized to measure the temperature of the central cavity  303  and transmit that measurement to the controller  307 . 
     An inner tube  311  may be placed within the external body  301  and encircling the central cavity  303 . The inner tube  311  may a material such as, e.g., quartz, silicon carbide, or mullite. The inner tube  311  may be cylindrical in shape and spaced apart from the external body  301  in order to provide a passage between the inner tube and the external body  301  for process gases to flow. 
     Inlets  313  and exits  315  may extend through the external body  301  to provide entrance and exit points for ambient gases to pass into and out of the central cavity  303 . The inlets  313  may extend into a bottom region of the central cavity  303  in order to provide fresh ambient gases into the central cavity  303 . The exits  315  may only extend through the external body  301 , such that the exits  315  open into the spacing between the external body  301  and the inner tube  311 . By placing the inlets  313  and the exits  315  at these locations, the desired ambient gases may be introduced at the bottom of the central cavity  303 , flow upwards through the central cavity  303  within the inner tube  311 , flow over the ends of the inner tube  311 , down through the spacing between the inner tube  311  and the external body  301 , and out through the exits  315 . Optionally, a vacuum pump (not individually illustrated in  FIG.  12 A ) may be attached to the exits  315  in order to facilitate the removal of the ambient gases from the central cavity  303 . 
     To seal the central cavity  303  from the ambient atmosphere, a base plate  317  may be attached to the external body  301  along the bottom of the external body  301 . The base plate  317  may be made from a similar material as the external body  301  (e.g., quartz, silicon carbide, mullite, combinations of these, or the like) and covers the opening at the bottom of the external body  301 . A seal ring  319  may be utilized to hermetically seal the central cavity  303  between the external body  301  and the base plate  317 . 
     Attached to the base plate  317  may be a wafer boat connection platform  321 . The wafer boat connection platform  321  allows for the placement and connection of a wafer boat  400  to the base plate  317 . Once attached to the base plate  317 , the wafer boat  400  may be placed into the central cavity  303  and be ready for processing. 
       FIG.  12 A  additionally illustrates a wafer boat  400  that may be utilized to insert and remove semiconductor wafers such as the substrate  50  from the furnace  300 . The wafer boat  400  may comprise a top plate  401 , a bottom plate  403 , and a plurality of support posts  405  extending between the top plate  401  and the bottom plate  403 . The top plate  401 , the bottom plate  403 , and the support posts  405  may all be made from a heat resistant material such as quartz, silicon carbide, mullite, combinations of these, or the like, and the support posts  405  may be attached to the top plate  401  and the bottom plate  403  through a suitable heat resistant method, such as bolting, welding, heat-resistant adhesives, force fits, combinations of these, or the like. 
     A series of notches may be formed at regular intervals along the support posts  405  to allow the support posts  405  to support the substrates  50 . Each notch in one of the support posts  405  may be aligned with notches at a similar height in the other support posts  405 , thereby providing four support points at each height to support the substrates  50  and other wafers. The notches may be spaced apart from each other enough to allow the heat from the furnace to evenly heat the semiconductor wafers without significant interference from adjacent wafers within the wafer boat  400 , such as about 6.3 mm apart. 
     In an embodiment the wafer boat  400  may have four support posts  405 , with each support post  405  comprising 143 notches. However, the precise number of support posts  405 , the placement of the support posts  405 , and the number of notches within the support posts may be varied beyond the embodiments described herein. All such variations are fully intended to be included within the scope of the embodiments. 
     The substrate  50  (along with other substrates  50  which may be desired to be processed simultaneously) may be placed into the wafer boat  400  after the substrate  50  has been placed onto a support ring  501  and aligned. This placement may be performed automatically, and the alignment of the substrate  50  may be maintained by the frictional forces between the substrate  50  and the support ring  501 . 
       FIG.  12 A  also illustrates that, once all of the substrates  50  have been placed into the wafer boat  400 , the wafer boat  400  (along with the substrates  50 ) may be placed onto the wafer boat connection platform  321  on the base plate  317  while the base plate  317  is separated from the external body  301  of the furnace  300 . Optionally, the wafer boat  400  may be physically attached to the wafer boat connection platform  321  using, e.g., clamps or other suitable connection devices. 
     After the wafer boat  400  has been placed on the wafer boat connection platform  321  of the base plate  317 , the base plate  317  may be mated with the external body  301  such that the wafer boat  400  and the substrates  50  are located within the central cavity  303  of the furnace  300 . Once the central cavity  303  is hermetically sealed between the external body  301  and the base plate  317 , the controller  307  may engage the heaters  305  to begin heating the central cavity  303  while desired ambient gases may be funneled into the central cavity  303  through the inlets  313 , over the wafer boat  400  and the substrate  50 , and out through the exits  315 . 
     In an embodiment the desired ambient gases (without plasma) may be chosen in order to help a portion of the inner spacer layer  264  (e.g., SiCN) both convert to an oxide (e.g., SiOCN) and well as expand in order to help reduce or close any seams  266  that may have formed during the deposition process. As such, in an embodiment the ambient gases may include an oxidizer, a regenerator, and a catalyst. For example, in some embodiments the oxidizer may be an oxygen containing gas such as water (H 2 O), oxygen, or ozone. However, any suitable oxidizer may be utilized. 
     In order to introduce the oxidizer, a carrier gas such as argon, helium, N2, combinations of these, or the like, may be bubbled through a liquid of the oxidizer. A portion of the liquid will vaporize and then be carried by the carrier gas to one or more of the inlets  313  (e.g., one 1.0 mm injector for each ambient). In an embodiment the oxidizer may have a flow rate into the furnace  300  of between about 0.5 slm and about 5 slm while the carrier gas has a flow rate into the furnace of about 0.5 slm and about 3 slm. However, any suitable methods of introducing the oxidizer and any suitable flow rates may be utilized. 
     The regenerator may be used to help prevent an overall reduction of material caused by undesired etching of the material of the inner spacer layer  264 . For example, in some embodiments in which the annealing process also works to etch and remove some of the material from the inner spacer layer  264 , the regenerator may be used to replace the removed material and regenerate the inner spacer layer  264 . As such, in some embodiments the regenerator may be the second precursor (e.g., trichloro[(trichlorosilyl)methyl]silane), DCS, HCD, combinations of these, or the like. However, any suitable regenerator may be utilized. 
     In order to introduce the regenerator, a carrier gas such as argon, helium, N2, combinations of these, or the like, may also be bubbled through a liquid of the regenerator. A portion of the liquid will vaporize and then be carried by the carrier gas to one or more of the inlets  313 . In an embodiment the regenerator may have a flow rate into the furnace  300  of between about 0.5 slm and about 5 slm while the carrier gas has a flow rate into the furnace of about 0.5 slm and about 3 slm. However, any suitable methods of introducing the regenerator and any suitable flow rates may be utilized. 
     The catalyst may be supplied in order to help with the chemical reactions that are desired to occur within the furnace  300 . As such, while the precise catalyst chosen is dependent at least in part on the material of the inner spacer layer  264 , the oxidizer, and the regenerator, in some embodiments the catalyst may be a chemical such as pyridine or the like. However, any suitable catalyst may be utilized. 
     In order to introduce the catalyst, a carrier gas such as argon, helium, nitrogen, water, oxygen, combinations of these, or the like, may be bubbled through a liquid of the catalyst. A portion of the liquid will vaporize and then be carried by the carrier gas to one or more of the inlets  313 . In an embodiment the catalyst may have a flow rate into the furnace  300  of between about 0.5 slm and about 5 slm while the carrier gas has a flow rate into the furnace of about 0.5 slm and about 3 slm. However, any suitable methods of introducing the catalyst and any suitable flow rates may be utilized. 
     Additionally, while the use of a bubbler has been described above with respect to the vaporizing of the oxidizer, the regenerator, and the catalyst, this is merely intended to be illustrative and is not intended to limit the present embodiments. Rather, any suitable vaporizer may be used to vaporize and transport the oxidizer, the regenerator, and the catalyst from storage to be used within the furnace  300 . All such vaporizers are fully intended to be included within the scope of the embodiments. 
       FIG.  12 A  additionally illustrates one suitable process whereby the heat within the central cavity  303  is transferred to the substrates  50  in a first annealing process, thereby annealing the substrates  50  and the material of the inner spacer layer  264  located on the substrates  50 . In an embodiment the first annealing process may be performed at a temperature of between about 400° C. and about 600° C., such as about 450° C.; a pressure of between about 500 torr and 800 torr; and for a time of between about 1 hour and about 6 hours, such as about 4 hours. However, any suitable parameters may be utilized. 
       FIG.  12 B  illustrates a conversion of the material of the inner spacer layer  264  to include oxygen from the oxidizer during the annealing process. In particular, as the annealing process introduces the oxidizer to the material of the inner spacer layer  264 , the oxidizer will react with the material of the inner spacer layer  264  and will introduce oxygen into the material of the inner spacer layer  264 . As such, in an embodiment in which the material of the inner spacer layer  264  is SiCN, a portion of the inner spacer layer  264  may be converted to an oxide such as SiOCN. However, any suitable materials may be used. 
       FIG.  12 C  illustrates a chart which illustrate the atomic percentage of carbon (represented in  FIG.  12 C  by the line labeled  1201 ), nitrogen (represented in  FIG.  12 C  by the line labeled  1203 ), oxygen (represented in  FIG.  12 C  by the line labeled  1205 ), and silicon (represented in  FIG.  12 C  by the line labeled  1207 ). As can be seen, by introducing the oxygen into the material of the inner spacer layer  264 , the introduction will cause both diffusion as well as reaction, the material of the inner spacer layer  264  will form two distinct regions within the material of the inner spacer layer  264 . In a particular embodiment, the material of the inner spacer layer  264  will have an oxide rich region  1210  along a surface of the material (that portion that converted to the oxide), which then has an oxygen gradient until the material of the inner spacer layer  264  will also have an oxide less region  1212  in its bulk (that portion to which the oxygen did not reach during the annealing process). 
     In an embodiment the oxide rich region  1210  may have an oxygen percentage of between about 10% and about 50%, such as about 30%. Additionally, the oxide rich region  1210  may have a nitrogen percentage of between about 5% and about 50%, such as about 5%. In a particular embodiment the oxide rich region  1210  may have an atomic percentage of silicon of about 31%, an atomic percentage of carbon of about 4%, an atomic percentage of oxygen of about 41%, and an atomic percentage of nitrogen of about 23%. As such, the oxide rich region  1210  may extend from the expanded surface of the inner spacer layer  264  between about 15 Å and about 27 Å (for 39% of the overall thickness), while the oxide-less region has a thickness of between about  30 A and about 42 Å (or the remaining 61% of the overall thickness). Additionally, the annealing process can deplete the nitrogen within the oxide rich region  1210  from about 57% (as deposited) to be between about 23 % to about 30%, such as about 28%, and slightly reduce the carbon concentration from about 5% (as deposited) to about 4%. However, any suitable concentrations and thicknesses may be utilized. 
       FIG.  12 D  illustrates that, by adding additional material (e.g., oxygen) to the material of the inner spacer layer  264 , those portions of the inner spacer layer  264  which receive the additional material (e.g., the oxide rich region  1210 ) will expand. In some embodiments the material of the inner spacer layer  264  may expand by about 32% while achieving a k-value of about 5. 
     With such an expansion, the seam  266  that was previously present within the material of the inner spacer layer  264  immediately after deposition (see, e.g.,  FIG.  11 I ) can be reduced or else completely eliminated. Such closure of the seams  266  in order to present an almost planar outwardly facing surface helps prevent unwanted complications that may arise in subsequent etching processes. 
     For example, returning now to  FIGS.  11 A- 11 C , once the inner spacer layer  264  has been deposited and treated, the inner spacer layer  264  may then be anisotropically etched to form the first inner spacers  90 . In an embodiment the etching process may be a CERTAS® etch, which introduces hydrogen fluoride (HF) and ammonia (NH 3 ) as etchants to the exposed material of the converted inner spacer material (e.g., the oxide rich region  1210 ). The HF and NH 3  may react with each other and with the oxide present in the material of the converted inner spacer material to produce (NH 4 ) 2 SiF 6  on a surface of the material of the converted inner spacer material. 
     Additionally, as the (NH 4 ) 2 SiF 6  is formed on the exposed surface of the converted inner spacer material, the (NH 4 ) 2 SiF 6  will itself act as a diffusion barrier layer that will prevent the further diffusion of HF and NH 3  into the material of the converted inner spacer material. As such, the CERTAS® etch is effectively self-limiting, as the formation of (NH 4 ) 2 SiF 6  will prevent further formation of (NH 4 ) 2 SiF 6  at a deeper depth within the material of the converted inner spacer material. The precise depth to which the (NH 4 ) 2 SiF 6  will form may be adjusted based on process conditions. 
     For example, in an embodiment the CERTAS® process conditions may be set so as to react between about 15 Å and about 150 Å, such as about 50 Å of the material of the converted inner spacer material from an oxide to (NH 4 ) 2 SiF 6 . This desired depth may be obtained by controlling the temperature, pressure, and flow rates of the etchants within the CERTAS® process. For example, the etching process may be performed at a temperature of between about 20° C. and about 60° C., such as about 30° C., while the pressure may be held between about 10 mTorr and about 100 mTorr, such as about 20 mTorr. Additionally, the flow rate of HF may be between about  10  sccm and about 100 sccm, such as about 20 sccm, and the flow rate of NH 3  may be between about 10 sccm and about 100 sccm, such as about 20 sccm. Other diluents, such as argon, xenon, helium, or other nonreactive gases, may additionally be utilized. 
     Once the reaction has effectively self-terminated (e.g., at a distance of 50 Å from the surface of the material of the converted inner spacer material), the material of the converted inner spacer material (along with the substrate  50 ) may be heated using an annealing process in order to remove the (NH 4 ) 2 SiF 6 , thereby reducing the thickness of the material of the converted inner spacer material by the thickness of the (NH 4 ) 2 SiF 6  and also exposing a remaining portion of the material of the converted inner spacer material for further processing. The heat may cause the (NH 4 ) 2 SiF 6  to thermally decompose to N 2 , H 2 O, SiF 4 , and NH 3 , all of which may be vapor and may be removed from the surface of the material of the converted inner spacer material by the annealing process. In an embodiment of the annealing process the material of the converted inner spacer material may be heated to a temperature of between about 80° C. to about 200° C., such as about 100° C. for between about 60 seconds to about 180 seconds to remove the (NH 4 ) 2 SiF 6  from the surface. 
     After the (NH 4 ) 2 SiF 6  has been removed, the material of the converted inner spacer material is again exposed and may be further processed. In an embodiment a second etching process, such as a second CERTAS® etch similar to the first CERTAS® etch described above, may be performed to controllably reduce the thickness of the material of the converted inner spacer material even further, such as reducing the material of the converted inner spacer material by another 50 Å to have a thickness of between about 15 Å and about 150 Å, such as about 120 Å. However, as one of ordinary skill in the art will recognize, the precise type of etching process, the number of iterations of the CERTAS® process, the process parameters for the etching process, and the precise thickness of the material of the converted inner spacer material as described above is intended to be illustrative only, as any number of iterations and any desired thickness of the material of the converted inner spacer material may be utilized. 
     The CERTAS® process may be utilized to reduce the thickness of the converted inner spacer material until the material of the converted inner spacer material is flush with sidewalls of the second nanostructures  54  in the n-type region  50 N and flush with the sidewalls of the first nanostructures  52  in the p-type region  50 P. For example, in embodiments in which the first inner spacers  90  are formed adjacent to silicon, the first inner spacers  90  may have a thickness of between about 4.1 nm and about 4.4 nm. In another embodiment in which the first inner spacers  90  are formed adjacent to silicon germanium, the first inner spacers  90  may have a thickness between about 9.4 nm and about 11.2 nm. 
     Additionally, while a very particular process is described above (the CERTAS® etch process) this description is intended to be illustrative and is not intended to be limiting. Rather, any suitable etching process may be utilized to thin the material of the converted inner spacer material. For example, in another embodiment, a reactive ion etching process followed by one or more cleaning process (e.g., an SC-1 or SC-2 cleaning process) may be utilized. All such etching processes are fully intended to be included within the scope of the embodiments. 
     However, although outer sidewalls of the first inner spacers  90  are illustrated as being flush with sidewalls of the second nanostructures  54  in the n-type region  50 N and flush with the sidewalls of the first nanostructures  52  in the p-type region  50 P, the outer sidewalls of the first inner spacers  90  may be recessed from sidewalls of the second nanostructures  54  and/or the first nanostructures  52 , respectively. 
     Moreover, although the outer sidewalls of the first inner spacers  90  are illustrated as being straight in  FIG.  11 B , the outer sidewalls of the first inner spacers  90  may be concave or dished. As an example,  FIG.  11 C  illustrates an embodiment in which outer sidewalls of the first inner spacers  90  are concave. Also illustrated are embodiments in which outer sidewalls of the first inner spacers  90  are concave. 
     In a particular embodiment in which the first inner spacers  90  are dished, the use of the annealing process and the reduction or removal of the seam  266 , undesired dishing may be reduced or avoided completely. For example, in some embodiments in which a CERTAS® etch is utilized, the dishing may be no bigger than about 3.2 nm, for a seam FR% reduction to about 0/44. In other embodiments in which another etch followed by an SC-1/SC-2 clean is utilized, the dishing may be no bigger than 4.3 nm, for a seam fail rate percent (FR%) reduction to about 0/44. As such, the dishing may be minimized. 
     In  FIGS.  13 A- 13 C , epitaxial source/drain regions  92  are formed in the first recesses  86 . In some embodiments, the epitaxial source/drain regions  92  may exert stress on the second nanostructures  54  in the n-type region  50 N and on the first nanostructures  52  in the p-type region  50 P, thereby improving performance. As illustrated in  FIG.  13 B , the epitaxial source/drain regions  92  are formed in the first recesses  86  such that each dummy gate  76  is disposed between respective neighboring pairs of the epitaxial source/drain regions  92 . In some embodiments, the first spacers  81  are used to separate the epitaxial source/drain regions  92  from the dummy gate layer  72  and the first inner spacers  90  are used to separate the epitaxial source/drain regions  92  from the nanostructures  55  by an appropriate lateral distance so that the epitaxial source/drain regions  92  do not short out with subsequently formed gates of the resulting nano-FETs. 
     The epitaxial source/drain regions  92  in the n-type region  50 N, e.g., the NMOS region, may be formed by masking the p-type region  50 P, e.g., the PMOS region. Then, the epitaxial source/drain regions  92  are epitaxially grown in the first recesses  86  in the n-type region  50 N. The epitaxial source/drain regions  92  may include any acceptable material appropriate for n-type nano-FETs. For example, if the second nanostructures  54  are silicon, the epitaxial source/drain regions  92  may include materials exerting a tensile strain on the second nanostructures  54 , such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions  92  may have surfaces raised from respective upper surfaces of the nanostructures  55  and may have facets. 
     The epitaxial source/drain regions  92  in the p-type region  50 P, e.g., the PMOS region, may be formed by masking the n-type region  50 N, e.g., the NMOS region. Then, the epitaxial source/drain regions  92  are epitaxially grown in the first recesses  86  in the p-type region  50 P. The epitaxial source/drain regions  92  may include any acceptable material appropriate for p-type nano-FETs. For example, if the first nanostructures  52  are silicon germanium, the epitaxial source/drain regions  92  may comprise materials exerting a compressive strain on the first nanostructures  52 , such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions  92  may also have surfaces raised from respective surfaces of the multi-layer stack  56  and may have facets. 
     Additionally, while specific processes are described above as ways to form the epitaxial source/drain regions  92  in the n-type region  50 N and in the p-type region  50 P, these descriptions are intended to be illustrative and are not intended to be limiting. Rather, any suitable process may be utilized to form the epitaxial source/drain regions  92  in the n-type region  50 N and in the p-type region  50 P. For example, the epitaxial source/drain regions  92  in both the n-type region  50 N and in the p-type region  50 P may be formed with a single material such as silicon and may be formed simultaneously (or separately) with each other. All suitable materials and processes may be utilized, and all such materials and processes are fully intended to be included within the scope of the embodiments. 
     The epitaxial source/drain regions  92 , the first nanostructures  52 , the second nanostructures  54 , and/or the substrate  50  may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an annealing. The source/drain regions may have an impurity concentration of between about 1×10 19  atoms/cm 3  and about 1×10 21  atoms/cm 3 . The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions  92  may be in situ doped during growth. 
     As a result of the epitaxy processes used to form the epitaxial source/drain regions  92  in the n-type region  50 N and the p-type region  50 P, upper surfaces of the epitaxial source/drain regions  92  have facets which expand laterally outward beyond sidewalls of the nanostructures  55 . In some embodiments, these facets cause adjacent epitaxial source/drain regions  92  of a same NSFET to merge as illustrated by  FIG.  13 A . In other embodiments, adjacent epitaxial source/drain regions  92  remain separated after the epitaxy process is completed as illustrated by  FIG.  13 C . In the embodiments illustrated in  FIGS.  13 A and  13 C , the first spacers  81  may be formed to a top surface of the STI regions  68  thereby blocking the epitaxial growth. In some other embodiments, the first spacers  81  may cover portions of the sidewalls of the nanostructures  55  further blocking the epitaxial growth. In some other embodiments, the spacer etch used to form the first spacers  81  may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region  58 . 
     The epitaxial source/drain regions  92  may comprise one or more semiconductor material layers. For example, the epitaxial source/drain regions  92  may comprise a first semiconductor material layer  92 A, a second semiconductor material layer  92 B, and a third semiconductor material layer  92 C. Any number of semiconductor material layers may be used for the epitaxial source/drain regions  92 . Each of the first semiconductor material layer  92 A, the second semiconductor material layer  92 B, and the third semiconductor material layer  92 C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer  92 A may have a dopant concentration less than the second semiconductor material layer  92 B and greater than the third semiconductor material layer  92 C. In embodiments in which the epitaxial source/drain regions  92  comprise three semiconductor material layers, the first semiconductor material layer  92 A may be deposited, the second semiconductor material layer  92 B may be deposited over the first semiconductor material layer  92 A, and the third semiconductor material layer  92 C may be deposited over the second semiconductor material layer  92 B. 
       FIG.  13 D  illustrates an embodiment in which sidewalls of the first nanostructures  52  in the n-type region  50 N and sidewalls of the second nanostructures  54  in the p-type region  50 P are concave, outer sidewalls of the first inner spacers  90  are concave, and the first inner spacers  90  are recessed from sidewalls of the second nanostructures  54  and the first nanostructures  52 , respectively. As illustrated in  FIG.  13 D , the epitaxial source/drain regions  92  may be formed in contact with the first inner spacers  90  and may extend past sidewalls of the second nanostructures  54  in the n-type region  50 N and past sidewalls of the first nanostructures  52  in the p-type region  50 P. 
     In  FIGS.  14 A- 14 C , a first interlayer dielectric (ILD)  96  is deposited over the structure illustrated in  FIGS.  6 A,  13 B, and  13 A  (the processes of  FIGS.  7 A- 13 D  do not alter the cross-section illustrated in  FIG.  6 A ), respectively. The first ILD  96  may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)  94  is disposed between the first ILD  96  and the epitaxial source/drain regions  92 , the masks  74 , and the first spacers  81 . The CESL  94  may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying first ILD  96 . 
     In  FIGS.  15 A- 15 C , a planarization process, such as a CMP, may be performed to level the top surface of the first ILD  96  with the top surfaces of the dummy gates  76  or the masks  78 . The planarization process may also remove the masks  78  on the dummy gates  76 , and portions of the first spacers  81  along sidewalls of the masks  78 . After the planarization process, top surfaces of the dummy gates  76 , the first spacers  81 , and the first ILD  96  are level within process variations. Accordingly, the top surfaces of the dummy gate layer  72  are exposed through the first ILD  96 . In some embodiments, the masks  78  may remain, in which case the planarization process levels the top surface of the first ILD  96  with top surface of the masks  78  and the first spacers  81 . 
     In  FIGS.  16 A and  16 B , the dummy gate layer  72 , and the masks  74  if present, are removed in one or more etching steps, so that second recesses  98  are formed. Portions of the dummy gate dielectrics  60  in the second recesses  98  are also be removed. In some embodiments, the dummy gate layer  72  and the dummy gate dielectrics  60  are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gate layer  72  at a faster rate than the first ILD  96  or the first spacers  81 . Each second recess  98  exposes and/or overlies portions of nanostructures  55 , which act as channel regions in subsequently completed nano-FETs. Portions of the nanostructures  55  which act as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions  92 . During the removal, the dummy gate dielectrics  60  may be used as etch stop layers when the dummy gate layer  72  are etched. The dummy gate dielectrics  60  may then be removed after the removal of the dummy gate layer  72 . 
     In  FIGS.  17 A and  17 B , the first nanostructures  52  in the n-type region  50 N and the second nanostructures  54  in the p-type region  50 P are removed extending the second recesses  98 . The first nanostructures  52  may be removed by forming a mask (not shown) over the p-type region  50 P and performing an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the first nanostructures  52 , while the second nanostructures  54 , the substrate  50 , the STI regions  58  remain relatively unetched as compared to the first nanostructures  52 . In embodiments in which the first nanostructures  52  include, e.g., SiGe, and the second nanostructures 54A-54C include, e.g., Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH), or the like may be used to remove the first nanostructures  52  in the n-type region  50 N. 
     The second nanostructures  54  in the p-type region  50 P may be removed by forming a mask (not shown) over the n-type region  50 N and performing an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the second nanostructures  54 , while the first nanostructures  52 , the substrate  50 , the STI regions  58  remain relatively unetched as compared to the second nanostructures  54 . In embodiments in which the second nanostructures  54  include, e.g., SiGe, and the first nanostructures  52  include, e.g., Si or SiC, hydrogen fluoride, another fluorine-based etchant, or the like may be used to remove the second nanostructures  54  in the p-type region  50 P. 
     In  FIGS.  18 A and  18 B , gate dielectric layers  100  and gate electrodes  102  are formed for replacement gates. The gate dielectric layers  100  are deposited conformally in the second recesses  98 . In the n-type region  50 N, the gate dielectric layers  100  may be formed on top surfaces and sidewalls of the substrate  50  and on top surfaces, sidewalls, and bottom surfaces of the second nanostructures  54 , and in the p-type region  50 P, the gate dielectric layers  100  may be formed on top surfaces and sidewalls of the substrate  50  and on top surfaces, sidewalls, and bottom surfaces of the first nanostructures  52 . The gate dielectric layers  100  may also be deposited on top surfaces of the first ILD  96 , the CESL  94 , the first spacers  81 , and the STI regions  58 . 
     In accordance with some embodiments, the gate dielectric layers  100  comprise one or more dielectric layers, such as an oxide, a metal oxide, the like, or combinations thereof. For example, in some embodiments, the gate dielectrics may comprise a silicon oxide layer and a metal oxide layer over the silicon oxide layer. In some embodiments, the gate dielectric layers  100  include a high-k dielectric material, and in these embodiments, the gate dielectric layers  100  may have a k value greater than about 7.0, and may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layers  100  may be the same or different in the n-type region  50 N and the p-type region  50 P. The formation methods of the gate dielectric layers  100  may include molecular-beam deposition (MBD), ALD, PECVD, and the like. 
     The gate electrodes  102  are deposited over the gate dielectric layers  100 , respectively, and fill the remaining portions of the second recesses  98 . The gate electrodes  102  may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although single layer gate electrodes  102  are illustrated in  FIGS.  18 A and  18 B , the gate electrodes  102  may comprise any number of liner layers, any number of work function tuning layers, and a fill material. Any combination of the layers which make up the gate electrodes  102  may be deposited in the n-type region  50 N between adjacent ones of the second nanostructures  54  and between the second nanostructure  54 A and the substrate  50 , and may be deposited in the p-type region  50 P between adjacent ones of the first nanostructures  52 . 
     The formation of the gate dielectric layers  100  in the n-type region  50 N and the p-type region  50 P may occur simultaneously such that the gate dielectric layers  100  in each region are formed from the same materials, and the formation of the gate electrodes  102  may occur simultaneously such that the gate electrodes  102  in each region are formed from the same materials. In some embodiments, the gate dielectric layers  100  in each region may be formed by distinct processes, such that the gate dielectric layers  100  may be different materials and/or have a different number of layers, and/or the gate electrodes  102  in each region may be formed by distinct processes, such that the gate electrodes  102  may be different materials and/or have a different number of layers. Various masking steps may be used to mask and expose appropriate regions when using distinct processes. 
     After the filling of the second recesses  98 , a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers  100  and the material of the gate electrodes  102 , which excess portions are over the top surface of the first ILD  96 . The remaining portions of material of the gate electrodes  102  and the gate dielectric layers  100  thus form replacement gate structures of the resulting nano-FETs. The gate electrodes  102  and the gate dielectric layers  100  may be collectively referred to as “gate structures.” 
     In  FIGS.  19 A- 19 C , the gate structure (including the gate dielectric layers  100  and the corresponding overlying gate electrodes  102 ) is recessed, so that a recess is formed directly over the gate structure and between opposing portions of first spacers  81 . A gate mask  104  comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD  96 . Subsequently formed gate contacts (such as the gate contacts  114 , discussed below with respect to  FIGS.  21 A and  21 B ) penetrate through the gate mask  104  to contact the top surface of the recessed gate electrodes  102 . 
     As further illustrated by  FIGS.  20 A- 20 C , a second ILD  106  is deposited over the first ILD  96  and over the gate mask  104 . In some embodiments, the second ILD  106  is a flowable film formed by FCVD. In some embodiments, the second ILD  106  is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like. 
     In  FIGS.  20 A- 20 C , the second ILD  106 , the first ILD  96 , the CESL  94 , and the gate masks  104  are etched to form third recesses  108  exposing surfaces of the epitaxial source/drain regions  92  and/or the gate structure. The third recesses  108  may be formed by etching using an anisotropic etching process, such as RIE, NBE, or the like. In some embodiments, the third recesses  108  may be etched through the second ILD  106  and the first ILD  96  using a first etching process; may be etched through the gate masks  104  using a second etching process; and may then be etched through the CESL  94  using a third etching process. A mask, such as a photoresist, may be formed and patterned over the second ILD  106  to mask portions of the second ILD  106  from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, the third recesses  108  extend into the epitaxial source/drain regions  92  and/or the gate structure, and a bottom of the third recesses  108  may be level with (e.g., at a same level, or having a same distance from the substrate), or lower than (e.g., closer to the substrate) the epitaxial source/drain regions  92  and/or the gate structure. Although  FIG.  20 B  illustrate the third recesses  108  as exposing the epitaxial source/drain regions  92  and the gate structure in a same cross section, in various embodiments, the epitaxial source/drain regions  92  and the gate structure may be exposed in different cross-sections, thereby reducing the risk of shorting subsequently formed contacts. After the third recesses  108  are formed, silicide regions  110  are formed over the epitaxial source/drain regions  92 . In some embodiments, the silicide regions  110  are formed by first depositing a metal (not shown) capable of reacting with the semiconductor materials of the underlying epitaxial source/drain regions  92  (e.g., silicon, silicon germanium, germanium) to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys, over the exposed portions of the epitaxial source/drain regions  92 , then performing a thermal anneal process to form the silicide regions  110 . The un-reacted portions of the deposited metal are then removed, e.g., by an etching process. Although silicide regions  110  are referred to as silicide regions, silicide regions  110  may also be germanide regions, or silicon germanide regions (e.g., regions comprising silicide and germanide). In an embodiment, the silicide region  110  comprises TiSi, and has a thickness in a range between about 2 nm and about 10 nm. 
     Next, in  FIGS.  21 A-C , contacts  112  and  114  (may also be referred to as contact plugs) are formed in the third recesses  108 . The contacts  112  and  114  may each comprise one or more layers, such as barrier layers, diffusion layers, and fill materials. For example, in some embodiments, the contacts  112  and  114  each include a barrier layer and a conductive material, and is electrically coupled to the underlying conductive feature (e.g., gate electrodes  102  and/or silicide region  110  in the illustrated embodiment). The gate contacts  114  are electrically coupled to the gate electrode  102  and may be referred to as gate contacts, and the contacts  112  are electrically coupled to the silicide regions  110  and may be referred to as source/drain contacts. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD  106 . 
     Embodiments may achieve advantages. For example, in embodiments in which the inner spacer material is formed and then converted using the annealing process in order to expand the material and seal any seams or voids in the material, subsequent etching processes more evenly etch the materials, leading to fewer defects during the etching processes. Such reduction in defects helps to improve yields and further allow for the reduction in size of the devices. 
       FIGS.  22 A- 22 B  illustrate an additional embodiment in which the first spacer layer  80  and the second spacer layer  82  are formed to provide an additional 2% (RO) boost to the device. In this embodiment the first spacer layer  80  is formed of a layer of material that has a heightened etch resistance to etchants used to remove the dummy gate dielectric  71 , the dummy gates  76 , and the masks  78 . In a particular embodiment the first spacer layer  80  may be formed of a material such as silicon carbon oxynitride (SiCON), SiOC, or SiON. However, any suitable material may be utilized. 
     The first spacer layer  80  in this embodiment may be deposited using a cyclical deposition that has both a deposition step and a treatment step that are repeated one or more times. Looking first at the deposition step, the deposition step may use a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), combinations of these, or the like, to deposit a first portion of the first spacer layer  80 . In an embodiment the first portion of the first spacer layer  80  may be deposited using CVD to a thickness of between about 1 Å and about 10 Å. However, any suitable thickness may be utilized. 
     Once the first portion of the first spacer layer  80  has been deposited, the first portion of the first spacer layer  80  is treated to densify the already deposited material. In a particular embodiment the treatment step may be a treatment such as a plasma radical treatment using a plasma precursor such as hydrogen (H 2 ), argon (Ar), N 2 /H 2 , combinations of these, or the like, for a time period of between about 10 s and about 120 s. However, any suitable treatment may be utilized. 
     By utilizing the treatment step to modify the properties of the first portion of the first spacer layer  80 , the material of the first portion of the first spacer layer  80  may be densified. For example, in the embodiment utilizing SiOCN, the treatment step may be used to modify the density of the first portion by increasing the number of Si—C bonds within the material, such that the first portion of the first spacer layer  80  has a higher etching resistance than the material as the material was deposited. 
     Once the treatment step has been performed to modify the properties of the first portion of the first spacer layer  80 , a first cycle of the deposition process has been completed. To continue the overall deposition process, the deposition step and the treatment step are repeated one or more times, such as by depositing portions of the material of the first spacer layer  80  and then treating the material prior to a subsequent deposition step. The cycles may be repeated as many times as desired to obtain a desired initial thickness. In a particular embodiment the overall deposition process may be used to form the first spacer layer  80  to an initial thickness of between about  20  Å and about 30 Å, such as about 25 Å. However, any suitable thickness may be utilized. 
     In an embodiment the above described process can be used to obtain the desired properties for the first spacer layer  80 . For example, in an embodiment in which the first spacer layer  80  is SiCON, the SiCON of the first spacer layer  80  may be formed to have a silicon percentage of between about 32.4%-atomic and about 33%-atomic and a carbon percentage of between about 12.5%-atomic and about 16%-atomic. Further, the SiCON of the first spacer layer  80  may be formed to have an oxygen percentage of between about 47%-atomic about 49.9%-atomic, and a nitrogen percentage of between about 4%-atomic and about 4.7%-atomic. 
     By forming the first spacer layer  80  within these ranges, the enhanced etching resistance can be achieved while still maintaining a larger K-value. In particular, if the concentrations are outside of these ranges, the K-value may be too small. Otherwise, the material of the first spacer layer  80  may not have the desired etch resistance. 
     In a particular embodiment in which the material of the first spacer layer  80  is SiCON, the SiCON of the first spacer layer  80  may have a first composition which comprises a silicon percentage of about 32.4%-atomic, a carbon percentage of about 13.5%-atomic, an oxygen percentage of about 49.9%-atomic and a nitrogen percentage of about 4.2%-atomic. By forming the first spacer layer  80  with this composition, the first spacer layer  80  may be formed to have a higher K-value, such as 4.7 and a higher density, such as a density of about 2.4 g/cm 3 . Finally, the first spacer layer  80  may be formed with greater than 90% coverage using a thickness of only 12.5 Å. 
     In another particular embodiment the SiCON of the first spacer layer  80  may have a second composition which comprises a silicon percentage of about 33%-atomic, a carbon percentage of about 12.5%-atomic, an oxygen percentage of about 49.8%-atomic and a nitrogen percentage of about 4.7%-atomic. By forming the first spacer layer  80  with this composition, the first spacer layer  80  may be formed to have a higher K-value, such as between about 4.7 and about 4.9 and a higher density, such as a density of about 2.5 g/cm 3 . Finally, the first spacer layer  80  may be formed with greater than 90% coverage using a thickness of only 10 Å. 
     In still yet another particular embodiment the SiCON of the first spacer layer  80  may have a third composition which comprises a silicon percentage of about 33%, a carbon percentage of about 16%, an oxygen percentage of about 47% and a nitrogen percentage of about 4%. By forming the first spacer layer  80  as described, the first spacer layer  80  may be formed in such a way as to increase the K value and density. For example, the first spacer layer  80  may be formed with a K-value of about 4.6 and a density of about 2.33 g/cm 3 . 
     After the first spacer layer  80  has been deposited, the process may be continued as described above with respect to  FIGS.  7 A- 7 B , such as by performing implantation processes to form LDD regions. For example, one or more implantation processes may be performed, and cleaning processes may be performed subsequent to the implantation processes and prior to depositing, e.g., the second spacer layer  83  as described below. However, any suitable process steps may be utilized. 
     In embodiments that utilize a cleaning process, however, the cleaning process may also include etchants that may affect the thickness of the first spacer layer  80  at this point in the process. For example, in an embodiment in which the cleaning process utilizes an etchant such as HF, the cleaning process may partially remove the material of the first spacer layer  80  by a thickness of between about 6 Å and about 7 Å. In a particular embodiment in which the first spacer layer  80  was deposited to a thickness of about 30 Å, the cleaning process may reduce the thickness of the first spacer layer  80  to be about 24 Å, while in an embodiment in which the first spacer layer  80  was deposited to a thickness of about 25 Å, the cleaning process may reduce the thickness of the first spacer layer  80  to be about 18 Å, and in an embodiment in which the thickness of the first spacer layer  80  was deposited to a thickness of about 20 Å, the cleaning process may reduce the thickness of the first spacer layer  80  to be about 13 Å. However, any suitable reduction in thickness may be utilized. 
     Once the first spacer layer  80  has been deposited, the LDD regions have been formed, and the cleaning process has been performed, the second spacer layer  82  may be formed in order to provide additional etching protection and isolation. In an embodiment the second spacer layer  82  may be formed of materials such as silicon oxycarbide (SiOC), SiO 2 , SiOCN, combinations of these, or the like. However, any suitable material may be utilized. 
     The second spacer layer  82  may be deposited using another cyclical deposition that has both a deposition step and a treatment step that a repeated one or more times. Looking first at the deposition step, the deposition step may use a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD) combinations of these, or the like, to deposit a first portion of the second spacer layer  82 . In an embodiment the first portion of the second spacer layer  82  may be deposited using CVD to a thickness of between about 10 Å and about 70 Å. However, any suitable thickness may be utilized. 
     Once the first portion of the second spacer layer  82  has been deposited, the first portion of the second spacer layer  82  is treated to densify the already deposited material. In a particular embodiment the treatment step may be a treatment such as a plasma radical treatment using a plasma precursor such as hydrogen (H 2 ), oxygen (O 2 ), nitrogen (N 2 ), combinations of these, or the like. However, any suitable treatment may be utilized. 
     By utilizing the treatment step to modify the properties of the first portion of the second spacer layer  82 , the material of the first portion of the second spacer layer  82  may be densified. For example, in the embodiment utilizing SiOC, the treatment step may be used to modify the density of the first portion of the second spacer layer  82  by increasing the number of Si—C bonds within the material, such that the first portion of the second spacer layer  82  has a higher etching resistance than the material as the material was deposited. 
     Once the treatment step has been performed to modify the properties of the first portion of the second spacer layer  82 , a first cycle of the deposition process for the second spacer layer  82  has been completed. To continue the overall deposition process, the deposition step and the treatment step are repeated one or more times, such as by depositing portions of the material and then treating the material prior to a subsequent deposition step. The cycles may be repeated as many times as desired to obtain a desired initial thickness for the second spacer layer  82 . 
     In a particular embodiment the overall deposition process may be used to form the second spacer layer  82  to an initial thickness that is at least large enough to help prevent further breakthrough if there is a breakthrough of the first spacer layer  80  in subsequent processes (e.g., etching processes discussed further below). In particular embodiments the second spacer layer  82  may be formed to an initial thickness of between about 29 Å and about 45 Å, such as about 40 Å. Thicknesses greater than this range can take up too much space, while thicknesses below this range may not work to prevent breakthroughs if a breakthrough occurs in the first spacer layer  80 . However, any suitable thickness may be utilized. 
     In a particular embodiment in which the second spacer layer  82  is SiOC, the second spacer layer  82  may have a silicon percentage of between about 20% and about 40%, such as about 30%, a carbon percentage of between about 1% and about 10%, such as about 6%, and an oxygen percentage of between about 50% and about 70%, such as about 64%. By forming the second spacer layer  82  as described, the second spacer layer  82  may be formed in such a way as to increase the K value and density. For example, the second spacer layer  82  may be formed with a K-value of about 3.8 and a density of about 2.23 g/cm 3 . 
     By forming the second spacer layer  82  within these ranges, the enhanced etching resistance can be achieved while still maintaining a larger K-value. In particular, if the concentrations are outside of these ranges, the K-value may be too small. Otherwise, the material of the second spacer layer  82  may not have the desired etch resistance. 
     In a particular embodiment the different compositions of the first spacer layer  80  (described above) may be manufactured with the second spacer layer  82 . In particular embodiments the second spacer layer  82  may be formed with any of the first composition, the second composition, and the third composition. In another embodiment the first spacer layer  80  may be formed with different portions having different compositions (such as having both the first composition and the second composition) and the second spacer layer  82  may be formed over both the first composition and the second composition. Any suitable combination of materials and compositions may be utilized, and all such combinations are fully intended to be included within the scope of the embodiments. 
       FIGS.  23 A- 23 B  illustrate that, once the first spacer layer  80  and the second spacer layer  82  have been formed (wherein these layers are represented in  FIGS.  23 A- 23 B  by the renumbered spacer layer  81 ), the process may continue as described above. For example, the first spacer layer  80  and the second spacer layer  82  may be reshaped and the epitaxial source/drain regions  92  may be formed. 
     In an embodiment, however, these processes may additionally modify the thickness of the second spacer layer  82 . For example, during the etching processes utilized to help form the epitaxial source/drain regions  92 , the etching processes may additionally remove material from the exposed surfaces of the second spacer layer  82 . As such, the thickness of the second spacer layer  82  may be reduced by a thickness of between about 6 Å and about 12 Å. For example, in an embodiment in which the second spacer layer  82  is initially deposited to 45 Å, the etching processes may reduce the thickness of the second spacer layer  82  to about 11 Å or 12 Å, while in an embodiment in which the second spacer layer  82  is initially deposited to 40 Å, the etching processes may reduce the thickness of the second spacer layer  82  to about 29 Å, and in an embodiment in which the second spacer layer  82  is initially deposited to 29 Å, the etching processes may reduce the thickness of the second spacer layer  82  to about 23 Å. However, any suitable reduction thickness may be utilized. 
     Once the epitaxial source/drain regions  92  have been formed, the process may continue. For example, the CESL  94  may be formed and the first ILD  96  may be deposited and planarized. However, any suitable processes may be utilized. 
     Additionally, while not specifically illustrated in subsequent figures (as the figures would be identical to  FIGS.  15 A- 21 C ), the process may be continued as described. For example, once the first ILD  96  has been deposited and planarized, the dummy gate dielectric  71 , the dummy gates  76 , and the masks  78  may be removed, thereby re-exposing the inner surfaces of the first spacer layer  80  (within the illustrated spacer  81  in the Figures). In an embodiment the dummy gate dielectric  71 , the dummy gates  76 , and the masks  78  may be removed using one or more etching processes with etchants such as a combination of oxygen plasma followed by dilute hydrogen fluoride. Any suitable etchant or combination of etchants may be utilized. 
     However, by forming the first spacer layer  80  as described above with the heightened etching resistance, the surfaces of the first spacer layer  80  that are exposed by the removal of the dummy gate dielectric  71 , the dummy gates  76 , and the masks  78  are more resistant to undesired etching from the etchants used to remove the dummy gate dielectric  71 , the dummy gates  76 , and the masks  78 . As such, while there may be some residual etching that occurs, there is less material from the first spacer layer  80  that is removed. 
     In a particular example in which the first spacer layer  80  is SiOCN formed as described above (e.g., with the cyclical deposition and treatment process) and the etchants are oxygen plasma followed by dilute hydrogen fluoride, the thickness of the first spacer layer  80  may be reduced an amount of about 8 Å. For example, if the first spacer layer  80  has a thickness of about  24  Å prior to the etching, the first spacer layer  80  may be reduced to a thickness of about  16  Å. 
     However, because the material of the first spacer layer  80  has an increased etching resistance and the thickness is reduced by no more than 8 Å in some embodiments, there is a reduced or eliminated chance of the etching removing all of the first spacer layer  80  to expose the adjacent second spacer layer  82 . Additionally, if there is a breakthrough of the first spacer layer  80 , the second spacer layer  82  may be formed thick enough to prevent a further breakthrough to other conductive regions. As such, the increased etching resistance helps prevent any breakthroughs that may occur during the etching process. 
     Once the dummy gate dielectric  71 , the dummy gates  76 , and the masks  78  have been removed, the process may be continued to replace the dummy gate dielectric  71  and the dummy gates  76  with the gate electrodes  102 . In an embodiment the gate electrodes  102  may be formed as described above with respect to  FIGS.  18 A- 18 B . However, any suitable process may be utilized. 
     However, by using a more etch resistant material for the first spacer layer  80 , which subsequently provides better resistance to the subsequent etch processes, there is less of an opportunity for the material of the gate electrodes  102  to be defective. In particular, by working to maintain the structural integrity of the first spacer layer  80 , the gate electrodes  102  have less opportunity to extrude through the first spacer layer  80  and into undesired regions where the conductive material of the gate electrodes  102  is not desired and may cause other problems. 
     Finally, once the gate electrodes  102  have been formed without metal extruding into undesired places, the process may be continued and the contacts  112  and the gate contacts  114  may be formed as described above with respect to  FIGS.  19 A- 21 C . However, any suitable processes and components may be utilized, and all such manufacturing processes and components are fully intended to be included within the scope of the embodiments. 
       FIG.  24    through  39 B illustrate another embodiment of using the first spacer layer  280  and the second spacer layer  282  with an enhanced resistance to the etching processes. In this embodiment, however, the first spacer layer  280  and the second spacer layer  282  are utilized within a fin field effect transistor (FinFET) embodiment. However, any other suitable embodiment, such as being used in a planar transistor, may also be utilized. 
     Looking first at  FIG.  24   ,  FIG.  24    illustrates an example of a FinFET in a three-dimensional view, in accordance with some embodiments. The FinFET comprises a fin  252  on a substrate  253  (e.g., a semiconductor substrate). Isolation regions  256  are disposed in the substrate  253 , and the fin  252  protrudes above and from between neighboring isolation regions  256 . Although the isolation regions  256  are described/illustrated as being separate from the substrate  253 , as used herein the term “substrate” may be used to refer to just the semiconductor substrate or a semiconductor substrate inclusive of isolation regions. Additionally, although the fin  252  is illustrated as a single, continuous material as the substrate  253 , the fin  252  and/or the substrate  253  may comprise a single material or a plurality of materials. In this context, the fin  252  refers to the portion extending between the neighboring isolation regions  256 . 
     A gate dielectric layer  292  is along sidewalls and over a top surface of the fin  252 , and a gate electrode  294  is over the gate dielectric layer  292 . Source/drain regions  283  are disposed in opposite sides of the fin  252  with respect to the gate dielectric layer  292  and gate electrode  294 . Source/drain region(s)  283  may refer to a source or a drain, individually or collectively dependent upon the context.  FIG.  24    further illustrates reference cross-sections that are used in later figures. Cross-section A-A is along a longitudinal axis of the gate electrode  294  and in a direction, for example, perpendicular to the direction of current flow between the source/drain regions  283  of the FinFET. Cross-section B-B is perpendicular to cross-section A-A and is along a longitudinal axis of the fin  252  and in a direction of, for example, a current flow between the source/drain regions  283  of the FinFET. Cross-section C-C is parallel to cross-section A-A and extends through a source/drain region of the FinFET. Subsequent figures refer to these reference cross-sections for clarity. 
     Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs, nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs), or the like. 
       FIG.  25    through  39 B are cross-sectional views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments.  FIGS.  25  through  30    illustrate reference cross-section A-A illustrated in  FIG.  1   , except for multiple fins/FinFETs.  FIGS.  31 A,  32 A,  33 A,  34 A,  35 A,  36 A,  37 A,  38 A, and  39 A  are illustrated along reference cross-section A-A illustrated in  FIG.  24   , and  FIGS.  31 B,  32 B,  33 B,  34 B,  35 B,  36 B,  37 B,  37 C,  38 B, and  39 B  are illustrated along a similar cross-section B-B illustrated in  FIG.  24   , except for multiple fins/FinFETs.  FIGS.  33 C and  33 D  are illustrated along reference cross-section C-C illustrated in  FIG.  24   , except for multiple fins/FinFETs. 
     In  FIG.  25   , a substrate  253  is provided. The substrate  253  may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate  253  may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate  253  may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. 
     The substrate  253  has an n-type region  150 N and a p-type region  150 P. The n-type region  150 N can be for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs. The p-type region  150 P can be for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. The n-type region  150 N may be physically separated from the p-type region  150 P (as illustrated by divider  251 ), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region  150 N and the p-type region  150 P. 
     In  FIG.  26   , fins  252  are formed in the substrate  253 . The fins  252  are semiconductor strips. In some embodiments, the fins  252  may be formed in the substrate  253  by etching trenches in the substrate  253 . The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etch may be anisotropic. 
     The fins  252  may be patterned by any suitable method. For example, the fins  252  may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins  252 . In some embodiments, the mask (or other layer) may remain on the fins  252 . 
     In  FIG.  27   , an insulation material  255  is formed over the substrate  253  and between neighboring fins  252 . The insulation material  255  may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material  255  is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material  255  is formed such that excess insulation material  255  covers the fins  252 . Although the insulation material  255  is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not shown) may first be formed along a surface of the substrate  253  and the fins  252 . Thereafter, a fill material, such as those discussed above may be formed over the liner. 
     In  FIG.  28   , a removal process is applied to the insulation material  255  to remove excess insulation material  255  over the fins  252 . In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the fins  252  such that top surfaces of the fins  252  and the insulation material  255  are level after the planarization process is complete. In embodiments in which a mask remains on the fins  252 , the planarization process may expose the mask or remove the mask such that top surfaces of the mask or the fins  252 , respectively, and the insulation material  255  are level after the planarization process is complete. 
     In  FIG.  29   , the insulation material  255  is recessed to form Shallow Trench Isolation (STI) regions  257 . The insulation material  255  is recessed such that upper portions of fins  252  in the n-type region  150 N and in the p-type region  150 P protrude from between neighboring STI regions  257 . Further, the top surfaces of the STI regions  257  may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions  257  may be formed flat, convex, and/or concave by an appropriate etch. The STI regions  257  may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material  255  (e.g., etches the material of the insulation material  255  at a faster rate than the material of the fins  252 ). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used. 
     The process described with respect to  FIGS.  25  through  29    is just one example of how the fins  252  may be formed. In some embodiments, the fins  252  may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate  253 , and trenches can be etched through the dielectric layer to expose the underlying substrate  253 . Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins  252 . For example, the fins  252  can be recessed, and a material different from the fins  252  may be epitaxially grown over the recessed fins  252 . In such embodiments, the fins  252  comprise the recessed material as well as the epitaxially grown material disposed over the recessed material. In an even further embodiment, a dielectric layer can be formed over a top surface of the substrate  253 , and trenches can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the trenches using a material different from the substrate  253 , and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins  252 . In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together. 
     Still further, it may be advantageous to epitaxially grow a material in n-type region  150 N (e.g., an NMOS region) different from the material in p-type region  150 P (e.g., a PMOS region). In various embodiments, upper portions of the fins  252  may be formed from silicon-germanium (Si x Ge 1-x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like. 
     Further in  FIG.  29   , appropriate wells (not shown) may be formed in the fins  252  and/or the substrate  253 . In some embodiments, a P well may be formed in the n-type region  150 N, and an N well may be formed in the p-type region  150 P. In some embodiments, a P well or an N well are formed in both the n-type region  150 N and the p-type region  150 P. 
     In the embodiments with different well types, the different implant steps for the n-type region  150 N and the p-type region  150 P may be achieved using a photoresist and/or other masks (not shown). For example, a photoresist may be formed over the fins  252  and the STI regions  257  in the n-type region  150 N. The photoresist is patterned to expose the p-type region  150 P of the substrate  253 . The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region  150 P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region  150 N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration of equal to or less than 10 18  cm -3 , such as between about 10 16  cm -3  and about 10 18  cm -3 . After the implant, the photoresist is removed, such as by an acceptable ashing process. 
     Following the implanting of the p-type region  150 P, a photoresist is formed over the fins  252  and the STI regions  257  in the p-type region  150 P. The photoresist is patterned to expose the n-type region  150 N of the substrate  253 . The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region  150 N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region  150 P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration of equal to or less than 10 18  cm -3 , such as between about 10 16  cm -3  and about 10 18  cm -3 . After the implant, the photoresist may be removed, such as by an acceptable ashing process. 
     After the implants of the n-type region  150 N and the p-type region  150 P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together. 
     In  FIG.  30   , a dummy dielectric layer  261  is formed on the fins  252 . The dummy dielectric layer  261  may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer  263  is formed over the dummy dielectric layer  261 , and a mask layer  265  is formed over the dummy gate layer  263 . The dummy gate layer  263  may be deposited over the dummy dielectric layer  261  and then planarized, such as by a CMP. The mask layer  265  may be deposited over the dummy gate layer  263 . The dummy gate layer  263  may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer  263  may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer  263  may be made of other materials that have a high etching selectivity from the etching of isolation regions, e.g., the STI regions  257  and/or the dummy dielectric layer  261 . The mask layer  265  may include one or more layers of, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer  263  and a single mask layer  265  are formed across the n-type region  150 N and the p-type region  150 P. It is noted that the dummy dielectric layer  261  is shown covering only the fins  252  for illustrative purposes only. In some embodiments, the dummy dielectric layer  261  may be deposited such that the dummy dielectric layer  261  covers the STI regions  257 , extending over the STI regions and between the dummy gate layer  263  and the STI regions  257 . 
       FIGS.  31 A through  39 B  illustrate various additional steps in the manufacturing of embodiment devices.  FIGS.  31 A through  39 B  illustrate features in either of the n-type region  150 N and the p-type region  150 P. For example, the structures illustrated in  FIGS.  31 A through  39 B  may be applicable to both the n-type region  150 N and the p-type region  150 P. Differences (if any) in the structures of the n-type region  150 N and the p-type region  150 P are described in the text accompanying each figure. 
     In  FIGS.  31 A and  31 B , the mask layer  265  may be patterned using acceptable photolithography and etching techniques to form masks  274 . The pattern of the masks  274  then may be transferred to the dummy gate layer  263 . In some embodiments (not illustrated), the pattern of the masks  274  may also be transferred to the dummy dielectric layer  261  by an acceptable etching technique to form dummy gates  272 . The dummy gates  272  cover respective channel regions  259  of the fins  252 . The pattern of the masks  274  may be used to physically separate each of the dummy gates  272  from adjacent dummy gates. The dummy gates  272  may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective epitaxial fins  252 . 
     Further in  FIGS.  31 A and  31 B , gate seal spacers  281  can be formed on exposed surfaces of the dummy gates  272 , the masks  274 , and/or the fins  252 . In an embodiment the gate seal spacers  281  may be formed using similar materials and similar process as the first spacer layer  80 , described above with respect to  FIGS.  22 A- 22 B . For example, a cyclical deposition process using both a deposition step and a treatment step to form a material such as SiOCN with an enhanced etch resistance may be used to form the gate seal spacers  281 . However, any suitable method may be utilized. 
     After the formation of the gate seal spacers  281 , implants for lightly doped source/drain (LDD) regions (not explicitly illustrated) may be performed. In the embodiments with different device types, similar to the implants discussed above, a mask, such as a photoresist, may be formed over the n-type region  150 N, while exposing the p-type region  150 P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins  252  in the p-type region  150 P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region  150 P while exposing the n-type region  150 N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins  252  in the n-type region  150 N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities of from about 10 15  cm -3  to about 10 19  cm -3 . An anneal may be used to repair implant damage and to activate the implanted impurities. 
     In  FIGS.  9 A and  9 B , gate spacers  282  are formed on the gate seal spacers  281  along sidewalls of the dummy gates  272  and the masks  274 . In an embodiment the gate seal spacers  281  may be formed using similar materials and similar processes as the second spacer layer  82  as described above with respect to  FIGS.  22 A- 22 B . For example, the gate spacers  282  may be formed with a material such as SiOC that is deposited using a cyclical deposition process with both a deposition and treatment process to form a enhanced material for the gate spacers  282 . However, any suitable material and deposition process may be utilized. 
     It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the gate seal spacers  281  may not be etched prior to forming the gate spacers  282 , yielding “L-shaped” gate seal spacers, spacers may be formed and removed, and/or the like. Furthermore, the n-type and p-type devices may be formed using different structures and steps. For example, LDD regions for n-type devices may be formed prior to forming the gate seal spacers  281  while the LDD regions for p-type devices may be formed after forming the gate seal spacers  281 . 
     In  FIGS.  33 A and  33 B  epitaxial source/drain regions  283  are formed in the fins  252 . The epitaxial source/drain regions  283  are formed in the fins  252  such that each dummy gate  272  is disposed between respective neighboring pairs of the epitaxial source/drain regions  283 . In some embodiments the epitaxial source/drain regions  283  may extend into, and may also penetrate through, the fins  252 . In some embodiments, the gate seal spacers  281  and the gate spacers  282  are used to separate the epitaxial source/drain regions  283  from the dummy gates  272  by an appropriate lateral distance so that the epitaxial source/drain regions  283  do not short out subsequently formed gates of the resulting FinFETs. A material of the epitaxial source/drain regions  283  may be selected to exert stress in the respective channel regions  259 , thereby improving performance. 
     The epitaxial source/drain regions  283  in the n-type region  150 N may be formed by masking the p-type region  150 P and etching source/drain regions of the fins  252  in the n-type region  150 N to form recesses in the fins  252 . Then, the epitaxial source/drain regions  283  in the n-type region  150 N are epitaxially grown in the recesses. The epitaxial source/drain regions  283  may include any acceptable material, such as appropriate for n-type FinFETs. For example, if the fin  252  is silicon, the epitaxial source/drain regions  283  in the n-type region  150 N may include materials exerting a tensile strain in the channel region  258 , such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions  283  in the n-type region  150 N may have surfaces raised from respective surfaces of the fins  252  and may have facets. 
     The epitaxial source/drain regions  283  in the p-type region  150 P may be formed by masking the n-type region  150 N and etching source/drain regions of the fins  252  in the p-type region  150 P to form recesses in the fins  252 . Then, the epitaxial source/drain regions  283  in the p-type region  150 P are epitaxially grown in the recesses. The epitaxial source/drain regions  283  may include any acceptable material, such as appropriate for p-type FinFETs. For example, if the fin  252  is silicon, the epitaxial source/drain regions  283  in the p-type region  150 P may comprise materials exerting a compressive strain in the channel region  258 , such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions  283  in the p-type region  150 P may have surfaces raised from respective surfaces of the fins  252  and may have facets. 
     The epitaxial source/drain regions  283  and/or the fins  252  may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 10 19  cm -3  and about  10   21  cm -3 . The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions  283  may be in situ doped during growth. 
     As a result of the epitaxy processes used to form the epitaxial source/drain regions  283  in the n-type region  150 N and the p-type region  150 P, upper surfaces of the epitaxial source/drain regions have facets which expand laterally outward beyond sidewalls of the fins  252 . In some embodiments, these facets cause adjacent source/drain regions  283  of a same FinFET to merge as illustrated by  FIG.  33 C . In other embodiments, adjacent source/drain regions  283  remain separated after the epitaxy process is completed as illustrated by  FIG.  33 D . In the embodiments illustrated in  FIGS.  33 C and  33 D , gate spacers  282  are formed covering a portion of the sidewalls of the fins  252  that extend above the STI regions  257  thereby blocking the epitaxial growth. In some other embodiments, the spacer etch used to form the gate spacers  282  may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI regions  257 . 
     In  FIGS.  34 A and  34 B , a first interlayer dielectric (ILD)  288  is deposited over the structure illustrated in  FIGS.  33 A and  33 B . The first ILD  288  may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)  287  is disposed between the first ILD  288  and the epitaxial source/drain regions  283 , the masks  274 , and the gate spacers  282 . The CESL  287  may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a lower etch rate than the material of the overlying first ILD  288 . 
     In  FIGS.  35 A and  35 B , a planarization process, such as a CMP, may be performed to level the top surface of the first ILD  288  with the top surfaces of the dummy gates  272  or the masks  274 . The planarization process may also remove the masks  274  on the dummy gates  272 , and portions of the gate seal spacers  281  and the gate spacers  282  along sidewalls of the masks  274 . After the planarization process, top surfaces of the dummy gates  272 , the gate seal spacers  281 , the gate spacers  282 , and the first ILD  288  are level. Accordingly, the top surfaces of the dummy gates  272  are exposed through the first ILD  288 . In some embodiments, the masks  274  may remain, in which case the planarization process levels the top surface of the first ILD  288  with the top surfaces of the top surface of the masks  274 . 
     In  FIGS.  36 A and  36 B , the dummy gates  272 , and the masks  274  if present, are removed in an etching step(s), so that recesses  290  are formed. Portions of the dummy dielectric layer  261  in the recesses  290  may also be removed. In some embodiments, only the dummy gates  272  are removed and the dummy dielectric layer  261  remains and is exposed by the recesses  290 . In some embodiments, the dummy dielectric layer  261  is removed from recesses  290  in a first region of a die (e.g., a core logic region) and remains in recesses  290  in a second region of the die (e.g., an input/output region). In some embodiments, the dummy gates  272  are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates  272  with little or no etching of the first ILD  288  or the gate spacers  282 . Each recess  290  exposes and/or overlies a channel region  258  of a respective fin  252 . Each channel region  258  is disposed between neighboring pairs of the epitaxial source/drain regions  283 . During the removal, the dummy dielectric layer  261  may be used as an etch stop layer when the dummy gates  272  are etched. The dummy dielectric layer  261  may then be optionally removed after the removal of the dummy gates  272 . 
     However, by forming the gate seal spacers  281  and the gate spacers  282  as described above, such as by using the cyclical deposition and treatment process, the gate seal spacers  281  and the gate spacers  282  may be formed to be more etch resistant to the etching processes that are utilized to remove the dummy gates  272 . As such, the gate seal spacers  281 , which may be partially etched by the etching processes, are resistant enough to prevent any undesired breakthroughs through the gate seal spacers  281  and avoid exposure of the material of the gate spacers  272 . 
     In  FIGS.  37 A and  37 B , gate dielectric layers  292  and gate electrodes  294  are formed for replacement gates.  FIG.  37 C  illustrates a detailed view of region  289  of  FIG.  37 B . Gate dielectric layers  292  one or more layers deposited in the recesses  290 , such as on the top surfaces and the sidewalls of the fins  252  and on sidewalls of the gate seal spacers 281/gate spacers  282 . The gate dielectric layers  292  may also be formed on the top surface of the first ILD  288 . In some embodiments, the gate dielectric layers  292  comprise one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. For example, in some embodiments, the gate dielectric layers  292  include an interfacial layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layers  292  may include a dielectric layer having a k value greater than about 7.0. The formation methods of the gate dielectric layers  292  may include Molecular-Beam Deposition (MBD), ALD, PECVD, and the like. In embodiments where portions of the dummy gate dielectric  260  remains in the recesses  290 , the gate dielectric layers  292  include a material of the dummy gate dielectric  260  (e.g., SiO 2 ). 
     The gate electrodes  294  are deposited over the gate dielectric layers  292 , respectively, and fill the remaining portions of the recesses  290 . The gate electrodes  294  may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although a single layer gate electrode  294  is illustrated in  FIG.  37 B , the gate electrode  294  may comprise any number of liner layers  294 A, any number of work function tuning layers  294 B, and a fill material  294 C as illustrated by  FIG.  37 C . After the filling of the recesses  290 , a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers  292  and the material of the gate electrodes  294 , which excess portions are over the top surface of the first ILD  288 . The remaining portions of material of the gate electrodes  294  and the gate dielectric layers  292  thus form replacement gates of the resulting FinFETs. The gate electrodes  294  and the gate dielectric layers  292  may be collectively referred to as a “gate stack.” The gate and the gate stacks may extend along sidewalls of a channel region  258  of the fins  252 . 
     The formation of the gate dielectric layers  292  in the n-type region  150 N and the p-type region  150 P may occur simultaneously such that the gate dielectric layers  292  in each region are formed from the same materials, and the formation of the gate electrodes  294  may occur simultaneously such that the gate electrodes  294  in each region are formed from the same materials. In some embodiments, the gate dielectric layers  292  in each region may be formed by distinct processes, such that the gate dielectric layers  292  may be different materials, and/or the gate electrodes  294  in each region may be formed by distinct processes, such that the gate electrodes  294  may be different materials. Various masking steps may be used to mask and expose appropriate regions when using distinct processes. 
     However, by using a more etch resistant material for the gate seal spacers  281  which subsequently provides better resistance to the subsequent etch processes, there is less of an opportunity for the material of the gate electrodes  294  to be defective. In particular, by working to maintain the structural integrity of the first spacer layer  80 , the gate electrodes  294  have less opportunity to extrude through the gate seal spacers  281  and into undesired regions where the conductive material of the gate electrodes  294  is not desired and may cause other problems. 
     In  FIGS.  38 A and  38 B , a gate mask  296  is formed over the gate stack (including a gate dielectric layer  292  and a corresponding gate electrode  294 ), and the gate mask  296  may be disposed between opposing portions of the gate spacers  282 . In some embodiments, forming the gate mask  296  includes recessing the gate stack so that a recess is formed directly over the gate stack and between opposing portions of gate spacers  282 . A gate mask  296  comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD  288 . The gate mask  296  is optional and may be omitted in some embodiments. In such embodiments, the gate stack may remain level with top surfaces of the first ILD  288 . 
     As also illustrated in  FIGS.  38 A and  38 B , a second ILD  308  is deposited over the first ILD  288 . In some embodiments, the second ILD  308  is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD  308  is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD and PECVD. The subsequently formed gate contacts  310  penetrate through the second ILD  308  and the gate mask  296  (if present) to contact the top surface of the recessed gate electrode  294 . 
     In  FIGS.  39 A and  39 B , gate contacts  310  and source/drain contacts  312  are formed through the second ILD  308  and the first ILD  288  in accordance with some embodiments. Openings for the source/drain contacts  312  are formed through the first and second ILDs  288  and  308 , and openings for the gate contact  310  are formed through the second ILD  308  and the gate mask  296  (if present). The openings may be formed using acceptable photolithography and etching techniques. A liner (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the ILD  308 . The remaining liner and conductive material form the source/drain contacts  312  and gate contacts  310  in the openings. An anneal process may be performed to form a silicide at the interface between the epitaxial source/drain regions  283  and the source/drain contacts  312 . The source/drain contacts  312  are physically and electrically coupled to the epitaxial source/drain regions  283 , and the gate contacts  310  are physically and electrically coupled to the gate electrodes  294 . The source/drain contacts  312  and gate contacts  310  may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the source/drain contacts  312  and gate contacts  310  may be formed in different cross-sections, which may avoid shorting of the contacts. 
     By forming the gate seal spacers  281  and the gate spacers  282  as described above, the number of defects caused by metal extrusion during formation of the gate electrodes  294  may be reduced. In particular, by using the cyclical deposition methods with both deposition and treatment processes, the gate seal spacers  281  and the gate spacers  282  can be made more etch resistant during subsequent processes. Such etch resistance prevents undesired breakthroughs during the subsequent etching processes, and helps prevent undesired extrusion of subsequently deposited materials such as the material of the gate electrodes  294 . Such a reduction or elimination of defects helps to create a more efficient manufacturing process with a higher yield. 
     In an embodiment, a method of manufacturing a semiconductor device includes: providing a semiconductor structure comprising alternately stacked first semiconductor layers and second semiconductor layers; recessing the first semiconductor layers horizontally; forming a first inner spacer on the recessed surfaces of the first semiconductor layers and sidewalls of the second semiconductor layers; and performing an annealing process to the first inner spacer to form a second inner spacer, the second inner spacer having a larger oxygen content than the first inner spacer. In an embodiment an oxygen content of the second inner spacer ranges from 10% to 50%, and a nitride content of the second inner spacer ranges from 5% to 50%. In an embodiment an oxygen content of the second inner spacer ranges from 30% to 50%. In an embodiment a nitride content of the second inner spacer ranges from 20% to 50%. In an embodiment the performing the annealing process closes a seam within the first inner spacer. In an embodiment the forming the first inner spacer is performed at least in part with an atomic layer deposition process. In an embodiment the atomic layer deposition process utilizes ammonia as a first precursor and uses trichloro[(trichlorosilyl)methyl]silane as a second precursor. 
     In another embodiment, a method of manufacturing a semiconductor device includes: depositing a stack of layers, wherein the stack of layers comprises alternating layers of a first semiconductor material and a second semiconductor material; patterning a fin from the stack of layers; etching the first semiconductor material within the fin to form a first recess; filling at least a portion of the first recess with a first dielectric material, the first dielectric material comprising a seam after the filling at least the portion of the first recess; and closing the seam within the first recess by changing at least a portion of the first dielectric material to a second dielectric material. In an embodiment the closing the seam further comprising annealing the first dielectric material. In an embodiment the first dielectric material comprises silicon carbon nitride. In an embodiment the closing the seam adds oxygen to the first dielectric material. In an embodiment after the closing the seam the second dielectric material comprises an oxygen concentration between about 10% and about 50%. In an embodiment after the closing the seam the second dielectric material comprises a nitrogen concentration between about 5% and about 50%. In an embodiment the method further includes etching the second dielectric material to form inner spacers. 
     In yet another embodiment, a semiconductor device includes: a first nanostructure surrounded by a gate dielectric; a second nanostructure over the first nanostructure, wherein the second nanostructure is surrounded by the gate dielectric; and an inner spacer located between the first nanostructure and the second nanostructure, the inner spacer having a dished surface, the dished surface having a depth of less than about 4.3 nm. In an embodiment the depth is about 3.2 nm. In an embodiment the inner spacer is free from seams between the first nanostructure and the second nanostructure. In an embodiment the inner spacer comprises SiOCN. In an embodiment an oxygen content of the inner spacer ranges from 10% to 50%. In an embodiment an oxygen content of the inner spacer ranges from 30% to 50%. 
     In yet another embodiment, a method of manufacturing a semiconductor device includes: depositing a gate structure over a semiconductor substrate; depositing a first spacer layer adjacent to the gate structure, the first spacer layer comprising SiOCN; depositing a second spacer layer in physical contact with the first spacer layer, the second spacer layer comprising SiOC; and exposing a surface of the first spacer layer opposite the second spacer layer. In an embodiment the depositing the first spacer layer deposits the first spacer layer to a thickness of between about 20 Å and about 30 Å and the depositing the second spacer layer deposits the second spacer layer to a thickness of between about 29 Å and about 45 Å. In an embodiment the depositing the first spacer layer includes: depositing a first portion of the first spacer layer; treating the first portion of the first spacer layer; after the treating the first portion depositing a second portion of the first spacer layer in physical contact with the first portion of the first spacer layer; and treating the second portion of the first spacer layer. In an embodiment the treating the first portion of the first spacer layer comprises a plasma hydrogen treatment. In an embodiment the first spacer layer has a silicon concentration of about 32.4%-at., a carbon concentration of about 13.5 %-at., an oxygen concentration of about 49.9 %-at., and a nitrogen concentration of about 4.2 %-at. In an embodiment the first spacer layer has a K-value of about 4.7 and a density of about 2.4 g/cm 3 . In an embodiment the first spacer layer has a silicon concentration of about 33%-at., a carbon concentration of about 12.5 %-at., an oxygen concentration of about 49.8 %-at., and a nitrogen concentration of about 4.7 %-at. 
     In yet another embodiment, a method of manufacturing a semiconductor device includes: depositing SiOCN to a thickness of between about 20 Å and about 30 Å in physical contact with a gate structure, wherein the depositing the SiOCN is performed at least in part with a first cyclical deposition and treatment process; and depositing SiOC to a thickness of between about 29 Å and about 45 Å in physical contact with the SiOCN, wherein the depositing the SiOC is performed at least in part with a second cyclical deposition and treatment process. In an embodiment the method further includes replacing the gate structure with a gate all around gate electrode. In an embodiment the method further includes replacing the gate structure with a finFET gate electrode. In an embodiment the SiOCN has a silicon concentration of about 33%-at., a carbon concentration of about 16%-at., an oxygen concentration of about 47%-at., and a nitrogen concentration of about 4%-at., and wherein the SiOC has a silicon concentration of about 30%-at., a carbon concentration of about 6%-at., and an oxygen concentration of about 64%-at. In an embodiment the SiOC has a k-value of about 3.8. In an embodiment the SiOC has a density of about 2.23 g/cm 3 . In an embodiment the treatment process comprises a plasma treatment. 
     In yet another embodiment, a semiconductor device includes: a gate electrode; a first spacer layer in physical contact with the gate electrode, the first spacer layer comprising SiOCN, the SiOCN having a density of at least 2.4 g/cm 3  and a k-value of at least 4.7; and a second spacer layer in physical contact with the first spacer layer, the second spacer layer comprising SiOC, the SiOC having a density of at least 2.5 g/cm 3  and a k-value of between about 4.7 and about 4.9. In an embodiment the first spacer layer has a silicon percentage of about 32.4%-at., a carbon percentage of about 13.5%-at., an oxygen percentage of about 49.9%-at., and a nitrogen percentage of about 4.2%-at. In an embodiment the second spacer layer has a silicon percentage of about 30%-at., a carbon percentage of about 6%-at., and an oxygen percentage of about 64%-at. In an embodiment the first spacer layer has a thickness of about 25 Å and the second spacer layer has a thickness of about 40 Å. In an embodiment the first spacer layer has a thickness of about 20 Å and the second spacer layer has a thickness of about 45 Å. In an embodiment the first spacer layer has a thickness of about 30 Å and the second spacer layer has a thickness of about 29 Å. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.