Patent Publication Number: US-8976588-B2

Title: NVSRAM cells with voltage flash charger

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to U.S. Patent Application No. 61/721,467, filed on Nov. 1, 2012, commonly assigned, and hereby incorporated by references in their entireties herein for all purposes. 
     This application is related to U.S. Pat. No. 7,164,608, U.S. patent application Ser. Nos. 14/037,356, 14/053,549, 14/058,227, 14/059,618, and 14/064,220, commonly assigned, which are incorporated by reference herein for all purposes. 
     Additionally, this application is related to U.S. Pat. No. 7,760,540. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     The present invention relates to a 12T NVSRAM cell with a flash Charger comprising one LV 6T SRAM cell, one 4T Flash cell and one shared paired Flash Charger transistors (2T) that can be made of a conventional 2-poly Flash transistor or a 1-poly Select transistor by shorting poly2 and poly1 of the flash cell. Additionally, the invention also provides a pair of mirrored 10T NVSRAM cells with a shared 2T flash Charger transistors. These shared 2T Flash Charger transistors are formed by using the available room of layout spacing between two source nodes of two 10T NVSRAM cells laid in same column without taking extra silicon area. Thus, this preferred pseudo-10T NVSRAM cell makes the 12T NVSRAM cell with a flash Charger size effectively equivalent to a 10T cell. 
     Additionally, during NVSRAM&#39;s Recall operation, the flash part of this pseudo-10T NVSRAM cell is configured into a paired Voltage Followers with their respective drain voltages preferably supplied by the coupling-generated charges rather than by the current supply from the VDD pin. As a result, the number of transistors used in each Flash string can be reduced from 3T to 2T without a bottom HV Select transistor that has a big overhead of a long channel length. Thus, the pseudo-10T NVSRAM cell can gain another 15% or more in cell size saving. 
     BACKGROUND OF INVENTION 
     Today, a trend of high-density NMOS NVSRAM memory more than 8 Mb is required. Therefore, besides the fixed six transistors (6T) of each SRAM cell, the number of transistors of each NMOS Flash cell should be minimized as much as possible. 
     Traditionally, a 12T NVSRAM cell comprises one 6T LV SRAM cell and one 6T HV Flash cell including paired 3T Flash strings. Each SRAM cell has paired storage nodes of Q and QB connected to two inputs of the paired Flash strings. Each 3T Flash string further includes one HV Select transistor located on top and another one on bottom, with one 2-poly HV flash transistor sandwiched in the middle of above two HV Select transistors. 
     Each paired drain nodes of the paired Flash strings are preferably connected to each paired nodes of Q and QB of each 6T LV SRAM cell directly. Conversely, the paired source nodes of each paired Flash strings are connected to a common VDD power supply to provide the different current flows to charge each paired nodes of Q and QB at two different voltage levels for each SRAM cell&#39;s subsequent amplification through two different programmed Vts of each paired Flash transistors during the Recall operation. 
     Although several NVSRAM approaches were disclosed before, the conventional 12T NVSRAM cell using low-current FN-channel program and FN SBPI method is prevailing in the market place. The flash type can be either made of 1-poly charge-trapping SONOS or MONOS type from Cypress or 2-poly floating-gate NMOS or PMOS type from Aplus Flash Technology, Inc., or a trigate flash technology from Simtek. By 2012, the highest density of a 12T NMOS NVSRAM memory in production is 16 Mb. 
     One big drawback of this 12T NMOS NVSRAM memory is its large 12T cell size that comprises one 6T LV SRAM cell and one 6T HV Flash cell. And each 6T Flash cell further comprises one pair of 3T FStrings and each FString further comprises one top HV Select transistor, one bottom HV Select transistor, and one flash transistor sandwiched by two Select transistors in the middle. 
     Due to three transistors of each Flash string have to be made of all HV devices to sustain a HV of 5-7V generated by a SBPI (Self-Boosting Program-Inhibit) scheme during the FN-Channel Program operation of NVSRAM cell, the channel length of these two HV Select transistors are made relatively bigger than the ones of a LV SRAM&#39;s two PMOS and our NMOS transistors. As a result, it is desirable to achieve any saving of each HV Select transistor in each Flash string so as to drastically reduce the NVSRAM cell size for cost reduction. 
     SUMMARY OF THE INVENTION 
     Embodiments of the present invention provide two preferred embodiments of a 12T NVSRAM cell with a Flash Charger and a pseudo-10T NVSRAM cell with one shared Charger that can be made of Flash transistor that take virtually no extra silicon area. The 12T or pseudo-10T NVSRAM cells can be made of a 2-poly floating-gate type or a 1-poly charge-trapping SONOS or MONOS flash type, regardless of PMOS type or NMOS type. 
     Other than cell size reduction, the Store operation of above the preferred NVSRAM cells use a DRAM-like charge-sharing scheme with Flash cell configured into a voltage follower associated with a charger and 2-step SRAM amplification technique to amplify threshold level difference ΔVt stored in the paired Flash transistors. The ΔVt can be detected as low as 1V when the Charger&#39;s coupled charges sufficient enough by ramping Charger&#39;s gate as high as VPP or by increasing the channel length for Flash-type Charger. 
     In an embodiment of the present invention, a 12T NVSRAM cell with a Flash Charger is provided including one LV 6T SRAM cell and one HV 6T Flash cell. Each 6T Flash cell further comprises of one paired 2T Flash string and one paired Flash-based Charger. Each 2T Flash string comprises one Flash transistor serially connected to one Select transistor on top which further connects to one of paired data nodes Q and QB of the corresponding LV 6T SRAM cell. 
     The Flash transistor and flash-based Charger transistor are preferably made of the same flash type but with a flexibility of different or same channel length. The same flash type means they can be made of either a 2-poly floating-gate type or a 1-poly charge-trapping SONOS and MONOS types, PMOS type or NMOS type. 
     In another embodiment, the present invention discloses a Pseudo-10T NMOS NVSRAM cell that is configured to coupled with an adjacent Pseudo-10T NVSRAM cell symmetrically sharing one paired 2T NMOS flash-based Charger by one LV 6T SRAM cell plus one paired top Select transistor and one paired 2T NMOS Flash cell without taking the extra MOM. 
     The transistors in the NMOS Flash cell and NMOS Flash Charger are preferably made of the same flash type but with a flexibility of different channel length. The same flash type means they can be made of either a 2-poly floating-gate type or a 1-poly charge-trapping SONOS and MONOS types. They can also be replaced by a 2-poly floating-gate type. 
     In yet another embodiment, the present invention discloses a Pseudo-10T NMOS NVSRAM cell that comprises one LV 6T SRAM cell, one paired 2T NMOS 2-poly Flash cell and one paired 2T Flash-based Charger cell with drain and source shorted together and is shared by two adjacent pseudo-10T NMOS NVSRAM cell without taking the extra room. 
     Note, the way to short the drains nodes and source nodes is not to use metal with a active contact that will create too much parasitic capacitance with an impact of reducing flash cell threshold level difference ΔVt between the paired Flash transistors. The preferred way is to make the N-active connection between two separate source nodes and drain nodes of the paired NMOS Flash Charger transistor like forming a NMOS capacitor with the active layer enclosure full poly gate of the Flash Charger. 
     The shorted drains and sources nodes of one pair of Flash Charger transistors would increase sharing of the coupling-generated charges from both Flash Charger transistor channels when a common gate voltage PumpWL of the pair of Flash Charger transistors is ramped up to a desired voltage, which is above VDD but lower than VPP. As a result, the final data node voltage difference ΔV Q-QB  is almost doubled over the above version with Source and Drain nodes totally separated for a superior Recall operation. 
     In still another embodiment, the present invention provides either a 12T NVSRAM cell with a Flash Charger or a Pseudo-10T NVSRAM cell that is configured to use a low-current FN-channel Erase scheme to decrease both flash transistor threshold levels Vts with a same initial low level by applying a negative high-voltage (HV) VNN to the paired Flash transistor gate (FWL) with the paired Flash transistor bulk held at VSS. 
     In yet still another embodiment, the present invention provides a 12TNVSRAM cell with a Flash Charger or Pseudo-10T NVSRAM cells with a shared Flash Charger that is configured to use a low-current FN-channel Program scheme to increase the paired flash transistor Vts with a desired ΔVt≧1.0V. This Program operation is preferably using a positive HV VPP to the paired Flash transistor gate along with a VSS and VDD-Vt (floating) initially in both flash&#39;s channels. The VSS and VDD-Vt are supplied directly from data nodes Q and QB of a 6T SRAM cell in the 12T or the Pseudo-10T NVSRAM cell through a top Select transistor with a Vt drop. During the FN-channel program operation, the floating-channel of VDD-Vt would be coupled to be above 5V when a Flash gate FWL is coupled to the VPP. This is commonly referred as the SBPI (Self-Boosting-Program-Inhibit) method. The flash channel held at the SBPI voltage would be prevented from programming, while the flash channel held at VSS level would be programmed with its Vt increased from initial erased Vt value (&lt;−2V) to a final Vt value (&gt;2V). 
     In a specific embodiment, the present invention provides a method for using another set of Program and Erase scheme for this 12T NVSRAM cell with a Flash Charger or a Pseudo-10T NVSRAM cells with a shared Flash Charger. The method includes using VPP FN-channel Erase operation to preferably increase both Flash transistor Vts to a same initial value above VDD along with using a VNN FN-edge scheme with a full passage of the VDD and VSS inputs from a paired Q and QB nodes by setting top Select transistor gate signals SG 1  and SG 2  higher than VDD+Vt to achieve the desired Vt difference ΔVt≧1.0V for the paired Flash transistor in the 12T NVSRAM cell with a Flash Charger and pseudo-10T NVSRAM cells. 
     In another specific embodiment, the present invention provides a method for performing a “Recall” operation of the preferred 12T NVSRAM cell with a Flash Charger or a Pseudo-10T NVSRAM cells with a shared Flash Charger that uses a DRAM-like charge-sensing scheme. The method includes converting the ΔVt stored in a paired Flash transistor through a voltage follower to a voltage difference ΔV Q-QB  at Q and QB nodes thought the aid of Flash-based Charger. Lastly, the small ΔV Q-QB  is fully amplified to VDD and VSS by two steps. The first step is to ramp up a SRAM&#39;s VDDP power line for a first amplification and the second step is to ramp down a SRAM&#39;s VSSP source line subsequently to complete the whole SRAM amplification operation. The role of Flash Charger is to ensure that the ΔV Q-QB  is more than 15% of the ΔVt=1V to compensate the mismatches of the devices along the paths of the parasitic nodes of Q and QB. 
     In yet another specific embodiment, the present invention discloses a method of a Store operation including two steps. The first step uses a FN-channel VNN Erase scheme to decrease the paired Flash transistor Vts to a same initial low Vt. The second step uses another FN-channel Program scheme to increase both Flash cell Vts with a desired ΔVt≧1V with a support of SBPI method. Another option of VNN FN-edge and VPP FN-channel can also be used for the Store operation. 
     In still another specific embodiment, the present invention discloses one paired Flash transistor configured into a voltage follower along with the Flash Charger by making the voltage level difference between two data nodes of Q and QB ΔV Q-QB &gt;30% of Vt level difference between the paired Flash transistor ΔVt 12  if the Flash Charger generates enough HV charges by ramping up the Flash Charger&#39;s gates to a HV level below VPP during a Recall operation. 
     In an alternative embodiment, the present invention provides that channel length of each Flash transistor can be flexibly increased to generate more coupling HV charges to Q and QB nodes for ensuring the success of the voltage follower operation. 
     In another alternative embodiment, the present invention provides that gate voltage of each Flash transistor can be flexibly increased to the highest level of VPP to generate more coupling charges below Mch 1  and Mch 2  with a shorter channel length for area reduction. 
     In yet another alternative embodiment, the present invention provides that gate voltage of Flash word line, FWL, can be flexibly increased from a negative value to a highest level of maximum Vt level, preferred to be positive, of the Flash transistors to help generate coupling charges for a DRAM-like charge-sensing scheme. In other words, more charges differences at paired Q and QB nodes can be achieved by taking the ramp gate of FWL on the flash transistors with a ΔVt. 
     In still another alternative embodiment, the present invention discloses a preferred amplification method for both the 12T NVSRAM cell with a Flash Charger and the Pseudo-10T NVSRAM cells with a shared Flash Charger by presetting the Q and QB to be VSS initially with a grounded flash gate FWL and ramping up the FWL but limited below a highest level of the paired Flash transistors Vt before ramping up the gate of above VDD but below VPP. 
     In this manner, the timing RC-affect leakage level from Pump node to Q and QB can be minimized to achieve higher voltage level difference ΔV Q-QB  at SRAM cell&#39;s Q and QB nodes for a superior Recall operation when a SRAM VDDP line is ramped up first and followed by ramping down SRAM&#39;s VSSP line to complete the whole amplification DRAM-like charge-sensing scheme. 
     In other embodiments, the present invention provides a method for setting initial SRAM power lines of VDDP and VSSP reversed for cancelling the mismatches of paired NMOS devices in each 6T SRAM cell without consuming any DC standby current. The reversed initial set up means VDDP=VSS but VSSP=VDD. Note, the Nwell regions (NW) of SRAM&#39;s two Inverters are commonly kept at VDD. 
     In yet other embodiments, the present invention discloses that channel length of the paired Flash transistor has to be made long enough to prevent the channel punch-through due to Drain-to-Source voltage V DS  drop being more than 5V during the floating-gate charge coupling operation. 
     In a specific embodiment, the present invention provides a 12T NVSRAM memory cell circuit with a pair of flash-based transistors as a voltage charger. The 12T NVSRAM memory cell includes a SRAM cell comprising two inverters cross-coupled to a first pass transistor and a second pass transistor commonly gated by a first word line and respectively coupled drains to a first bit line and a second bit line and sources to a first data node and a second data node. The first data node and the second data node respectively are outputted from the two invertors. Each inverter includes a PMOS device connected to a first power line and a NMOS device connected to a second power line. The first power line and the second power line are operated between a VDD power supply and ground and are separated from a common Nwell node. The 12T NVSRAM memory cell also includes a Flash cell comprising a first cell string and a second cell string sharing a common P-sub. The first/second cell string includes a first/second Select transistor, a first/second Flash transistor, and a first/second Charger transistor connected in series. The first Select transistor and the second Select transistor are gated commonly by a select-gate control line and respectively associated with a first drain terminal coupled to the first data node and a second drain terminal coupled to the second data node. The first and the second Flash transistors are gated commonly by a second word line. The first Charger transistor and the second Charger transistor are gated commonly by a pump word line and respectively associated with a first source terminal and a second source terminal. The first source terminal and the second source terminal are left floating. 
     In an embodiment, the first Charger transistor and the second Charger transistor are configured to ramp the second word line up to the VDD level followed by ramping the pump word line to a high voltage above the VDD level to generate coupling charges to respectively pass a voltage level difference through a first voltage-follower made by the first Flash transistor and the first Select transistor to the first data node and through a second voltage-follower made by the second Flash transistor and the second Select transistor to the second data node. The two cross-coupled inverters are operated to amplify the voltage level difference to a scale of VSS=0V at one of the first data node and the second data node and the VDD level at another one of the first data node and the second data node. 
     In another specific embodiment, the present invention also provides a paired pseudo-10T NVSRAM memory cell circuit with a shared flash charger. The paired pseudo-10T NVSRAM memory cell includes a first pseudo-10T NVSRAM cell having a first flash source terminal and second flash source terminal and a second pseudo-10T NVSRAM cell having a third flash source terminal and fourth flash source terminal. Additionally, the paired pseudo-10T NVSRAM memory cell includes a first Charger transistor and a second Charger transistor commonly gated by a pump word line. The first Charger transistor has a first charger drain node connected to the first flash source terminal and a first charger source node connected to the third flash source terminal. The second Charger transistor has a second charger drain node connected to the second flash source terminal and a second charger source node connected to the fourth flash source terminal. The first pseudo-10T NVSRAM cell and the second pseudo-10T NVSRAM cell are configured to be substantially same in a NVSRAM cell structure sharing a first common power line and separately a second common power line respectively operated between a VDD power supply and ground. The NVSRAM cell structure includes a SRAM cell comprising two inverters cross-coupled to a first pass transistor and a second pass transistor commonly gated by a first word line and respectively coupled drains to a first bit line and a second bit line and sources to a first data node and a second data node. The first data node and the second data node respectively are outputted from the two invertors. Each inverter includes a PMOS device connected to the first power line and a NMOS device connected to the second power line. The first power line and the second power line are separated from a common Nwell node. 
     The NVSRAM cell structure further includes a Flash cell comprising a first cell string and a second cell string sharing a common P-sub. The first/second cell string includes a first/second Select transistor, a first/second Flash transistor, and a first/second Charger transistor connected in series. The first Select transistor and the second Select transistor are gated commonly by a select-gate control line and respectively associated with a first drain terminal coupled to the first data node and a second drain terminal coupled to the second data node. The first and the second Flash transistors are gated commonly by a second word line. The first Charger transistor and the second Charger transistor are gated commonly by a pump word line and respectively associated with a first source terminal and a second source terminal. The first source terminal and the second source terminal are left floating. 
     In an embodiment, the first/second source node of the first pseudo-10T NVSRAM cell is the first/second flash source terminal and the first/second source node of the second pseudo-10T NVSRAM cell is the third/fourth flash source terminal. 
     In another embodiment, the first Charger transistor and the second Charger transistor are configured to generate coupling charges by ramping the second word line to the VDD level followed by ramping the pump word line to a level above the VDD level and to use a charge-sensing scheme and voltage-follower operation for performing a Recall operation to write a Flash logic state represented by threshold levels of the first Flash transistor and the second Flash transistor in either the first pseudo-10T NVSRAM cell or the second pseudo-10T NVSRAM cell to corresponding SRAM logic state stored by voltage levels of the first data node and the second data node in corresponding the first pseudo-10T NVSRAM cell or the second pseudo-10T NVSRAM cell. 
     During NVSRAM&#39;s Recall operation, the flash part of this pseudo-10T NVSRAM cell is configured into a paired voltage followers with their respective drain voltages preferably supplied by the coupling-generated charges rather than by the current supply from the VDD pin. As a result, the number of transistors used in each Flash string can be reduced from 3T to 2T without a bottom HV Select transistor that has a big overhead of a long channel length. Thus, the pseudo-10T NVSRAM cell can gain another 15% or more in cell size saving. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a circuit diagram of a 2-poly NMOS 12T NVSRAM cell with a Flash-based Charger according to an embodiment of the present invention. 
         FIG. 1B  a first preferred embodiment of a 1-poly SONOS or MONOS 12T NVSRAM cell with a Flash-based Charger according to another embodiment of the present invention. 
         FIG. 1C  is a circuit diagram of a 2-poly PMOS 12T NVSRAM cell with a Flash-based Charger according to yet another embodiment of the present invention. 
         FIG. 2A  is a circuit diagram of a paired 2-poly NMOS Pseudo-10T NVSRAM cell with a shared Flash-based Charger according to an alternative embodiment of the present invention. 
         FIG. 2B  is a circuit diagram of a paired 1-poly SONOS or MONOS Pseudo-10T NVSRAM cell with a shared Flash-based Charger according to another alternative embodiment of the present invention. 
         FIG. 2C  is a circuit diagram of a paired 2-poly PMOS Pseudo-10T NVSRAM cell with a shared Flash-based Charger according to yet another alternative embodiment of the present invention. 
         FIG. 3  is a chart showing a NMOS Flash transistor&#39;s Vt distribution vs time for both the 12T NVSRAM cell with a Flash Charger and Pseudo-10T NVSRAM cell&#39;s FN-channel Program operation that uses a VPP to increase Flash transistor Vts and a FN-channel Erase operation that uses a VNN to decrease Flash transistor Vts in accordance of the present invention. 
         FIG. 4  is a chart showing a NMOS Flash transistor&#39;s Vt distribution vs. time of the 12T NVSRAM cell with a Flash Charger and Pseudo-10T NVSRAM&#39;s FN-edge Program operation to decrease both Vt of MC 1  and MC 2  flash cells with a desired ΔVt≧1V in accordance with the present invention. 
         FIG. 5A  is a simulation circuit of a paired of pseudo-10T 2-poly NMOS NVSRAM&#39;s with the drains and sources nodes of a paired Flash-charger shorted together in accordance with the present invention. 
         FIG. 5B  is simulation result based on the paired pseudo-10T 2-poly NMOS NVSRAM cell with a shared flash-based charger of  FIG. 5A  in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention relates to a preferred 12T NVSRAM cell with a Flash Charger or a pseudo-10T NVSRAM cell comprising one LV 6T SRAM cell, one 4T Flash cell and one shared paired Flash Charger transistors (2T) that can be made of a conventional 2-poly Flash transistor or a 1-poly Select transistor by shorting poly2 and poly1 of the flash cell. These shared 2T Flash Charger transistors are formed on available room of layout spacing between two source nodes of two 10T NVSRAM cells laid in same column without taking extra silicon area. Thus, this preferred pseudo-10T NVSRAM cell makes a cell size of the 12T NVSRAM cell with a Flash Charger effectively equivalent to a 10T cell. 
       FIG. 1A  shows a preferred embodiment of a 2-poly NMOS 12T NVSRAM cell with a Flash-based Charger of the present invention. Each 12T NVSRAM cell with a Flash Charger  100  includes one 6T LV SRAM cell  101  and one 6T NMOS 2-poly Flash cell  103 . Each 6T LV SRAM cell  101  is like conventional one having two inverters I 1  and I 2  respectively outputting two data nodes of Q and QB coupled to two LV NMOS devices M 1  and M 2  with their gates coupled to common word line SWL and drain nodes respectively to bit lines BL and BLB. The two Inverters have coupled the PMOS devices and NMOS devices therein respectively to two common power lines VDDP and VSSP, separated from their common Nwell region coupled to NW node. Each 6T NMOS 2-poly Flash cell  103  comprises two fully symmetrical 3T NMOS 2-poly Flash strings  104  and  105 . Each String, e.g., FString1  104  further includes one 2-poly NMOS Flash transistor MC 1  in the middle, one top Select transistor of ST 1  and one additional Charge transistor Mch 1  in the bottom with its source node FSL 1  left floating. Another 3T Flash string, FString2  105  includes one 2-poly NMOS Flash transistor MC 2  in the middle, one top NMOS Select transistor of ST 2 , and one more NMOS Charge transistor Mch 2  in the bottom with its source node FSL 2  left floating. The top Select transistor ST 1  or ST 2  can be made of 2-poly NMOS flash device or 1-poly Flash design with the shortage of poly2 layer and poly1 layer. The Charge transistors Mch 1  and Mch 2  are made by the same type transistors as the paired Flash transistors MC 1  and MC 2 . Both Select transistor ST 1  and ST 2  are commonly gated by a control signal SG. Both Flash transistors MC 1  and MC 2  are commonly gated to a flash word line FWL. Both NMOS Charge transistors Mch 1  and Mch 2  are commonly gated to a power line PumpWL for providing control of coupled charges to the two FStrings  104  and  105 . 
       FIG. 1B  shows another preferred embodiment of a 1-poly SONOS or MONOS 12T NVSRAM cell with a Flash-based Charger of the present invention. Each 12T NVSRAM cell  110  includes one 6T LV SRAM cell  111  and one 6T 1-poly Flash cell  113 . Each 6T LV SRAM cell  111  is like conventional one having two inverters I 1  and I 2  respectively outputting two data nodes of Q and QB coupled to two LV NMOS devices M 1  and M 2  with their gates coupled to common word line SWL and drain nodes respectively to bit lines BL and BLB. The two Inverters have coupled the PMOS devices and NMOS devices therein respectively to two common power lines VDDP and VSSP, separated from their common Nwell region coupled to NW node. Each 6T 1-poly Flash cell  113  comprises two fully symmetrical 3T 1-poly Flash strings  114  and  115 . Each String, e.g., FString1  114  further includes one 1-poly charge-trapping type Flash transistor MC 1  in the middle, one top Select transistor of ST 1  and one additional transistor Mch 1  in the bottom with its source node FSL 1  left floating. Another 3T Flash string, FString2  115  includes one 1-poly Flash transistor MC 2  in the middle, one top Select transistor of ST 2 , and one more 1-poly transistor Mch 2  in the bottom with its source node FSL 2  left floating. Both Select transistor ST 1  and ST 2  are commonly gated by a control signal SG. Both 1-poly transistors Mch 1  and Mch 2  are commonly gated to a power line PumpWL for providing control of coupled charges to the two FStrings  114  and  115 . 
       FIG. 1C  shows yet another preferred embodiment of a 2-poly PMOS 12T NVSRAM cell with a Flash-based Charger of the present invention. Each 12T NVSRAM cell  120  includes one 6T LV SRAM cell  121  and one 6T PMOS 2-poly Flash cell  123 . Each 6T LV SRAM cell  121  is like conventional one having two inverters I 1  and I 2  respectively outputting two data nodes of Q and QB coupled to two LV NMOS devices M 1  and M 2  with their gates coupled to common word line SWL and drain nodes respectively to bit lines BL and BLB. The two Inverters have coupled the PMOS devices and NMOS devices therein respectively to two common power lines VDDP and VSSP, separated from their common Nwell region coupled to NW node. Each 6T PMOS 2-poly Flash cell  123  comprises two fully symmetrical 3T PMOS 2-poly Flash strings  124  and  125 . Each String, e.g., FString1  104  further includes one 2-poly PMOS Flash transistor MC 1  in the middle, one top Select transistor of ST 1  and one additional transistor Mch 1  in the bottom with its source node FSL 1  left floating. Another 3T Flash string, FString2  125  includes one 2-poly PMOS Flash transistor MC 2  in the middle, one top PMOS Select transistor of ST 2 , and one more PMOS transistor Mch 2  in the bottom with its source node FSL 2  left floating. The top Select transistor ST 1  or ST 2  can be made of 2-poly NMOS flash device or 1-poly Flash design with the shortage of poly2 layer and poly1 layer. Both Select transistor ST 1  and ST 2  are commonly gated by a control signal SG. Both PMOS transistors Mch 1  and Mch 2  are commonly gated to a power line PumpWL for providing control of coupled charges to the two FStrings  104  and  105 . 
     The reason for configuring the middle paired Flash transistors between the top Select transistor and the Flash Charger into a preferred paired Voltage-Follower is to allow the stored ΔVt in the paired Flash transistors can be easily detected and then fully passed to the paired input nodes, Q and QB, of an Amplifier, which is the 4T latch part of a 6T SRAM cell. 
     The regular operation of a so-called Voltage-Follower needs to meet the following equation of Vg−Vt≦Vd, where Vg is the gate voltage of Flash pairs. Vt is Flash transistor&#39;s channel threshold level. There are two Vt values of a paired Flash transistors with preferred ΔVt&gt;1V. Vd is a common drain voltage which is supplied by the boosted charges generated by ramping up Flash Charger gate to a desired voltage between a low voltage VDD and a high voltage VPP to generate coupled charges below the Flash Charger transistor&#39;s channel. If the coupled charges are not sufficient to make Vd&gt;Vg−Vt, then the outputs of the paired Voltage-Followers would not be equal to the ΔVt of the paired Flash transistors. The outputs of ΔVt of the paired Voltage-Followers are coupled to paired nodes, Q and QB, of each SRAM cell with ΔV Q-QB . The best case of Recall operation is under the condition of ΔV Q-QB =ΔVt. In other words, the ΔVt in the paired Flash transistors is 100% reflected by ΔV Q-QB  at each SRAM&#39;s paired storage nodes of Q and QB. Most of time, the ΔV Q-QB &lt;ΔVt and should be improved by using either a higher VPP ramping voltage or a larger channel length. 
     If ST 1  and ST 2  are 2-poly flash transistors, then their Vts are preferably set to be the same with a positive value of around 0.7V for a desired 1.2V VDD operation. This can be done by using a negative HV VNN FN-channel Erase scheme to first decrease the Vt level and using a positive HV VPP FN-channel Program scheme to set to be around 0.7V with Q=QB=VSS. 
     If ST 1  and ST 2  are poly1-gate flash transistors, then poly1-gate Vt is set from flash process control. The poly1-gate is achieved by shorting poly2 and poly1Together. This is the simplest way and most desired by the present invention. Since the (program or erase) operation speed of Flash String is not important, thus the shortage of poly1 and poly2 can be done per 32 or 64 NVSRAM cells in X-direction of a whole NVSRAM memory chip to save the area. 
     Due to this paired fully symmetrical cell structure and layout, the parasitic capacitance on both Q and QB nodes and the connections to Flash drain nodes of MC 1  and MC 2  are substantially tracking to set up a good foundation for this preferred 12T NVSRAM cell with a Flash Charger using a DRAM-like charge-sensing scheme for a Recall operation. Now, the operations of the 12T NVSRAM cell with a Flash Charger of  FIG. 1A  are described first below. Other versions in  FIGS. 1B and 1C  are substantially similar. Additional descriptions for the operations of pseudo-10T NVSRAM cells based on  FIGS. 2A-2C  are almost the same as the 12T NVSRAM cell with a Flash Charger of  FIGS. 1A-1C  with some minor changes in biased conditions for Recall and Store operations and will be given in later sections of the specification. 
     The detailed steps for operating this 12T NVSRAM cell with a Flash-based Charger and array in different operations will be explained below. 
     1) 6T SRAM operation: In each SRAM operation, each corresponding Flash cell is preferably isolated from each corresponding SRAM cell. The isolation of the biased conditions is preferably set as shown below:
         A) SWL=VDD for the selected SRAM cells in a single SRAM word line WL, but SWL=VSS for the non-selected SRAM cells in other N−1 WLs.   B) VDDP=VDD and VSSP=VSS.   C) SG=VSS to disconnect the drain node of ST 1  from Q node and drain node of ST 2  from QB node.   D) FWL=X, which means FWL voltage becomes don&#39;t-care and can be set either VDD or VSS.   E) PumpWL=X, which means PumpWL voltage becomes don&#39;t-care and can be set either at VDD or VSS.       

     2) Flash operation: This operation includes two sub-operations such as FN-channel Erase operation to decrease both paired flash transistor Vts to a same initial preferred value Vt≦VSS=0V and the FN-edge Program operation to increase the paired flash transistor Vts with a desired ΔVt≦1V. The biased conditions for performing this operation are explained below. 
     A) Erase operation: Using a preferred negative high voltage VNN FN-channel scheme to decrease the paired Flash transistor Vts to a same initial value of Vt≦0V. 
     
       
         
           
               
               
               
               
               
               
               
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 2-step Erase 
                 VDDP 
                 SWL 
                 BL 
                 BLB 
                 Q 
                 QB 
                 VSSP 
                 SG 
                 FWL 
                 PumpWL 
               
               
                   
               
             
            
               
                 first step: 
                 VDD 
                 X 
                 X 
                 X 
                 X 
                 X 
                 VSS 
                 VSS 
                 VSS 
                 VSS 
               
               
                 Isolation 
               
               
                 second step: 
                 VDD 
                 X 
                 X 
                 X 
                 X 
                 X 
                 VSS 
                 VSS 
                 VNN 
                 VSS 
               
               
                 Erase 
               
               
                   
               
            
           
         
       
     
     In first Isolation step, the SG=VSS and the SRAM cell is set to be a normal power setup condition such as VDDP=VDD and VSSP=VSS and other signals are Don&#39;t-care (“X” state means either VSS or VDD works) as shown in TABLE 1 above. 
     In second Erase step, the FWL is ramped down from VSS to a negative high voltage VNN˜−18V. The VNN −HV operation is defined to remove the plurality of electrons from floating-gate of 2-poly Flash cell or Nitride layer of 1-poly Flash cell type. As a result, both Flash transistor Vts would be decreased to a same desired negative value Vt&lt;0V after a predetermined erase time ≈5 ms. In other words, Vt(MC 1 )=Vt(MC 2 )≦0V, regardless of their old Vt values retained after last program. In a preferred embodiment, Vt(MC 1 )=Vt(MC 2 )&lt;−2V. 
     B) Program operation: Using a preferred high positive VPP FN-channel scheme for increasing one Flash transistor Vt and using SBPI method for inhibiting the other Flash transistor Vt with a desired ΔVt≧1.0V. The bias conditions are shown in TABLE 2 below. 
     
       
         
           
               
               
               
               
               
               
               
               
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                 2-step 
                   
                   
                 MC1 
                 MC2 
                   
                   
                   
                   
                   
                 Pump 
               
               
                 Program 
                 VDDP 
                 SWL 
                 Vt 
                 Vt 
                 Q 
                 QB 
                 VSSP 
                 SG 
                 FWL 
                 WL 
               
               
                   
               
             
            
               
                 First step 
                 VDD 
                 VSS 
                  ≦−2 V 
                 ≦−2 V 
                 VDD 
                 VSS 
                 VSS 
                 VDD 
                 VSS 
                 VSS 
               
               
                 Preset 
               
               
                 Second 
                 VDD 
                 VSS 
                 ≧1.0 V 
                   ≦0 V 
                 VDD 
                 VSS 
                 VSS 
                 VDD 
                 VPP 
                 VSS 
               
               
                 step 
               
               
                 Program 
               
               
                   
               
            
           
         
       
     
     In first Preset step, the Select gate signal SG is set to VDD to pass VSS and VDD-Vt respectively to the drains of MC 1  and MC 2  with Flash gate FWL set to VSS and flash Charger gate PumpWL to VSS. In an exemplary Case 1: For an initial SRAM logic state “0”, the Q and QB nodes are respectively at the VDD level and VSS. With Q=VDD and QB=VSS initially, then MC 1  drain voltage level is at VDD-Vt(ST 1 ) and MC 2  drain voltage level is at VSS (under conditions of ST 1  and ST 2  commonly gated by SG=VDD and Vt(ST 1 )=0.7V). SRAM power lines VDDP and VSSP are set in normal bias condition of VDDP=VDD, VSSP=VSS. Both threshold levels of Flash transistors MC 1  and MC 2  are assigned to a negative value ≦−2V. 
     In the second Program step, the Flash gate FWL is ramped up from VSS to a positive HV of VPP, ranging from +15V to +18V for a 2-poly flash cell, or +10V for a 1-poly NONOS flash cell. The channel of the flash transistor MC 1  with an initial floating voltage of VDD−VT=1.1V would be boosted to above 5V by coupling effect from high gate voltage VPP. After VPP FN-channel Program operation within a desired 10 ms program time, the MC 2  Flash cell with drain node held at VSS state would get programmed, but MC 1  with drain node held at initial VDD-Vt state would get Program-Inhibited. As a result, the final desired Vt 1 (MC 1 ) remains smaller than 0V (i.e., remains at −2V) but Vt 2 (MC 2 ) increases to greater than 1V. Therefore, the Flash logic state stored in the paired Flash transistors MC 1  and MC 2  would be defined as “1”. 
     3) Store operation: This operation is similarly defined as above Program operation to write each SRAM cell logic state into the paired Flash transistors MC 1  and MC 2 . Thus the details should be the same above and will not be repeated here for brevity. There are three kinds of Store operations as explained below.
         A) Auto-Store operation: This operation is performed upon the VDD power loss. Every SRAM cell logic data has to be written into its corresponding NVM Flash cell of paired Flash transistors MC 1  and MC 2  automatically in each 12T NVSRAM cell with a Flash Charger.   B) Software-Store operation: This operation is performed upon the call of Software-Store command controlled initiated by the off-chip MCU. Usually, it involves a sequence of defined steps.   C) Hardware-Store operation: This operation is performed upon the call of hardware-Store command controlled by one pin and initiated by the off-chip MCU. Usually, it also involves a sequence of defined steps.       

       FIG. 2A  shows a circuit diagram of a paired 2-poly NMOS Pseudo-10T NVSRAM cell with a shared flash-based charger according to an alternative embodiment of the present invention. Each Pseudo-10T NVSRAM cell comprises one 6T LV SRAM cell and one 2T 2-poly NMOS Flash cell as shown in  FIG. 1A  with one shared NMOS Flash Charger placed right between two mirrored 6T SRAM cells adjacent physically on top and bottom. The room to insert this shared 2T is by taking the active spacing in two source nodes between two pseudo-10T NSVRAM cells. Thus, no extra room is needed for adding the paired transistors for the 2-poly Flash Charger. As a result, each pseudo-10T NVSRAM cell with a shared 2-poly paired transistor has I 2  transistors but in a same layout size of a 10T NVSRAM cell. 
     As shown, the top pseudo-10T NVSRAM cell includes one LV 6T SRAM cell  210  and one 4T Flash cell, which is at upper part of the circuit box  220 . Each SRAM cell  210  includes two Inverters I 1  and I 2  with a paired storage nodes of Q 1  and Q 1 B and Pass-WL transistors of M 1  and M 2  with the gate tied to SWL 1 . Corresponding power lines include VDDP 1  and VSSP 1  for top pseudo-10T NVSRAM cell. Each flash cell comprises one paired top 2-poly (1-poly is preferred) NMOS Select transistors, ST 1  and ST 2  in box  221  with a common gate tied to SG 1  and one paired 2-poly NMOS Flash transistors, MC 1  and MC 2 , in box  222  with a common gate tied to FWL 1 . 
     Conversely, the bottom mirrored pseudo-10T NVSRAM cell comprises of another one LV 6T SRAM cell  230  and one 4T Flash cell at lower part of circuit box  220 . The SRAM cell  230  includes two Inverters 13 and 14 with a paired storage nodes of Q 2  and Q 2 B and Pass-WL transistors of M 3  and M 4  with a common gate tied to SWL 2 . Corresponding power lines include VDDP 2  and VSSP 2  for the bottom pseudo-10T NVSRAM cell. The 4T Flash cell mentioned above comprises one paired top 2-poly (1-poly is preferred) NMOS Select transistor, ST 3  and ST 4 , in box  225  with a common gate tied to SG 2  and one paired 2-poly NMOS Flash transistor, MC 3  and MC 4 , in box  224  with a common gate tied to FWL 2 . 
     In addition, both top and bottom pseudo-10T NVSRAM cells share one circuit including one paired Flash-based transistor, Mch 1  and Mch 2 , in box  223  with a common gate tied to PumpWL. In real chip layout, the shared Flash Charger (paired Mch 1  and Mch 2 ) is laid in between the spacing of source nodes of top pair of MC 1  and MC 2  and source nodes of the bottom pair of MC 3  and MC 4 . The layout room of the shared Flash Charger circuit does not really take one extra row in the NVSRAM memory as compared to the counterpart of a 12T NVSRAM cell shown in  FIG. 1A  of the present invention. 
     Besides, both drain and source nodes of Mch 1  and Mch 2  are separated in layout in  FIG. 2A . When Flash Charger&#39;s gate signal, PumpWL, is ramped to VPP 1 , Mch 1  and Mch 2  would generate individual coupled charges below their respective channels so that no sharing between these generated coupled charges between Mch 1  and Mch 2 . The charges generated from Mch 1  would flow to either Q 1  and Q 2  based on the following Vt conditions of MC 1  and MC 2 . 
       FIG. 2B  is a circuit diagram of a paired 1-poly SONOS or MONOS Pseudo-10T NVSRAM cell with a shared flash-based charger according to another alternative embodiment of the present invention. The only change is the Flash transistor type, 1-poly SONOS or MONOS charge trapping type transistor is used to replace 2-poly NMOS floating-gate type transistor. 
       FIG. 2C  is a circuit diagram of a paired 2-poly PMOS Pseudo-10T NVSRAM cell with a shared flash-based charger according to yet another alternative embodiment of the present invention. The only change is the Flash transistor type, 2-poly PMOS floating-gate type transistor is used to replace 2-poly NMOS floating-gate type transistor. 
     4) Recall operation: A first description is given below based on the paired pseudo-10T NMOS NVSRAM cells with a shared Flash Charger described above, with references to the simulation circuit of  FIG. 5A  based on  FIG. 2A  and associated results of simulation waveforms of  FIG. 5B . 
     In particular, in an example (Case A), a Flash Charger transistor Mch 1  is configured to generate HV charges that goes only to Q 1  of the top SRAM cell of the top pseudo-10T NVSRAM cell when a top pseudo-10T NVSRAM Flash transistor Vt(MC 1 )&lt;FWL 1  and in corresponding bottom pseudo-10T NVSRAM another Flash transistor Vt(MC 3 )&gt;FWL 2 . Here in the example, FWL 2 =FWL 1 . The charges flow would be blocked by MC 3  but passed by MC 1 . 
     In another example Case B), Mch 1 &#39;s generated HV charges go only to Q 2  of the bottom SRAM cell of the bottom pseudo-10T NVSRAM cell when the Vt(MC 1 )&gt;FWL 1  and the other Vt(MC 3 )&lt;FWL 2 . The charges flow would be blocked by MC 1  but passed by MC 3 . 
     Further in yet another example (Case C), Mch 1  generated HV charges will not go to both Q 1  and Q 2  on top and bottom pseudo-10T NVSRAM cells when Vt(MC 1 )&lt;FWL 1  and Vt(MC 3 )&lt;FWL 2 . The charges flow would be blocked by both MC 1  and MC 3 . 
     Similarly, the above explanation is valid to Mch 2  generated charges distribution between Q 1 B and Q 2 B. In still another example (Case D), Mch 2  generated HV charges go to Q 1 B only when Vt(MC 2 )&lt;FWL 1  but Vt(MC 4 )&gt;FWL 2 . The charges flow would be blocked by MC 4  but passed by MC 2 . 
     In one more example (Case E), Mch 2  generated HV charges go to Q 2 B only when Vt(MC 2 )&gt;FWL 1  but Vt(MC 4 )&lt;FWL 2 . The charges flow would be blocked by MC 2  but passed by MC 4 . 
     In a final example (Case F), Mch 1  generated HV charges will not go to both Q 1 B and Q 2 B, when Vt(MC 2 )&lt;FWL 1  and Vt(MC 3 )&lt;FWL 2 . The charges flow would be blocked by both MC 1  and MC 3 . In the present invention, the FWL 1 =FWL 2 =FWL=VDD, and ST 1 =ST 2 =ST=VDD. 
     Now, the Recall operation of the pseudo-10T 2-poly NMOS NVSRAM cell will be explained below with reference to  FIG. 5A  (to be shown below) that shows a paired pseudo-10T NVSRAM cell with a shared Flash Charger in the middle but the drain and source nodes of Flash Charger devices, Mch 1  and Mch 2 , are laid separated in layout. The SG 1  and SG 2  are tied together. Similarly, the FWL 1  and FWL 2  are also tied together. The VDDP and VSSP of top and bottom pseudo-10T NVSRAM cells are also tied together in reality. 
     With above set up conditions, both top and bottom pseudo-10T NVSRAM cells can be programmed and erased simultaneously. In addition, the Store and Recall operations of both NVSRAM cells can be done on the same time too. In addition, once SG 1 =SG 2 =VSS, then both pseudo-10T NVSRAM cell&#39;s SRAM cells can be read and write independently as a normal two SRAM cells in two different WLs. 
     In Recall operation, as opposite to the conventional 12T NVSRAM cell using the SRAM-like current charging scheme to charged up with a different voltages of ΔV Q-QB  at nodes, Q and QB, due to the ΔVt stored in paired Flash transistors, MC 1  and MC 2 , with initial Q=QB=VSS and Vt(MC 1 )&lt;0&lt;Vt(MC 2 ), this pseudo-10T NVSRAM cell in accordance with the present invention uses a DRAM-like charge-sensing scheme and a circuit to make ΔV Q-QB &gt;0.2V. In a preferred embodiment, the flash transistor with lower initial Vt is a negative value about −2V and the other Flash transistor with higher initial Vt is preferred to be a positive value above the VDD level. The Recall operation for a pair of pseudo-10T NVSRAM cells with a shared flash Charger is preferably divided into six steps as shown in the TABLE 3 below. 
     
       
         
           
               
               
               
               
               
               
               
             
               
                 TABLE 3 
               
               
                   
               
               
                 Recall 
                 First step 
                 Second step 
                 Third step 
                 Fourth step 
                 Fifth step 
                 Sixth step 
               
               
                   
               
             
            
               
                 Q1 
                 VSS 
                 VSS 
                 V1 
                 V3/VDD 
                 VSS/VDD 
                 VSS/VDD 
               
               
                 Q1B 
                 VSS 
                 VSS 
                 V2 
                 VDD/V3 
                 VDD/VSS 
                 VDD/VSS 
               
               
                 Q2 
                 VSS 
                 VSS 
                 V1 
                 V3/VDD 
                 VSS/VDD 
                 VSS/VDD 
               
               
                 Q2B 
                 VSS 
                 VSS 
                 V2 
                 VDD/V3 
                 VDD/VSS 
                 VDD/VSS 
               
               
                 BL 
                 VSS 
                 X 
                 X 
                 X 
                 X 
                 Low/High 
               
               
                 BLB 
                 VSS 
                 X 
                 X 
                 X 
                 X 
                 High/Low 
               
               
                 SWL1 &amp; 
                 VDD 
                 VSS 
                 VSS 
                 VSS 
                 VSS 
                 VDD 
               
               
                 SWL2 
                 pulse 
               
               
                 VDDP 
                 VSS 
                 VSS 
                 VSS 
                 Ramps to 
                 Stays at 
                 VDD 
               
               
                   
                   
                   
                   
                 VDD 
                 VDD 
               
               
                 PumpWL 
                 VSS 
                 VSS 
                 Ramps to 
                 Stays at 
                 Stays at 
                 VSS 
               
               
                   
                   
                   
                 VPP1 
                 VPP1 
                 VPP1 
               
               
                 VSSP 
                 VSS 
                 Ramps to 
                 VDD 
                 VDD 
                 Ramps to 
                 VSS 
               
               
                   
                   
                 VDD 
                   
                   
                 VSS 
               
               
                 SG 
                 VPP2 
                 VPP2 
                 VPP2 
                 VPP2 
                 VPP2 
                 VSS 
               
               
                 FWL1 &amp; 
                 VSS 
                 Ramps to 
                 Stays at 
                 Stays at 
                 Stays at 
                 VSS 
               
               
                 FWL2 
                   
                 VDD 
                 VDD 
                 VDD 
                 VDD 
               
               
                 Function 
                 SRAM 
                 Setup the 
                 Detecting 
                 1st SRAM 
                 2nd SRAM 
                 Back to 
               
               
                   
                 initial set 
                 paired 
                 ΔVt stored 
                 Amplification 
                 Amplification 
                 SRAM 
               
               
                   
                 Q = QB = 
                 Flash 
                 In MC1 &amp; 
                 by ramping 
                 by ramping 
                 operation 
               
               
                   
                 VSS By 
                 Voltage 
                 MC2 by 
                 VDDP 
                 VSSP 
               
               
                   
                 pulsing 
                 Follower 
                 ramping 
                 to VDD 
                 to VSS 
               
               
                   
                 SWL &amp; 
                 By setting 
                 Flash 
               
               
                   
                 connect 
                 FWL = 
                 Charger&#39;s 
               
               
                   
                 SRAM &amp; 
                 VDD≦ 
                 gate of 
               
               
                   
                 Flash 
                 Vtmax 
                 PumpWL 
               
               
                   
               
               
                 0 V &lt; V1, V2 &lt; V3 &lt; VDD, VDD &lt; VPP1 &lt; VPP, VPP2 = VDD + Vt(Select transistor) 
               
            
           
         
       
     
     The above VPP 1  voltage is defined as VDD&lt;VPP 1 &lt;VPP. But VPP 2 =VDD+Vt to fully pass the coupling-generated HV charges from the Flash Charger to Q and QB nodes. 
     The exact voltage of VPP 1  is preferred to be as high as possible to near VPP so that the Flash Charger can generate sufficient coupling HV charges below the channels of Mch 1  and Mch 2  to maintain a normal Voltage Follower operation. That means the coupled channel voltage in Mch 1  and Mch 2  are preferably equal or higher than the gate voltage of the common flash word line FWL. 
     In an alternative embodiment, the flash word line FWL 1  and FWL 2  (both are tied together) can be ramped to VSS (if both Vts of two Flash transistors are positive) or to −2V (if one Vt is positive, and one Vt is negative but not lower than −2V) to turn off both Flash transistors after the start of the First SRAM amplification and the second SRAM amplification for achieving better full digital VDD/VSS level with improved isolation between the top SRAM cell amplification and the bottom SRAM cell amplification. 
     The Recall operations of the 12T 2-poly NMOS NVSRAM cell with a Flash Charger shown in  FIG. 1A  is substantially like those operated through either the top or bottom pseudo-10T NVSRAM cell described above. In one or more embodiments, the Recall operations of the 12T 1-poly NMOS NVSRAM cell with a Flash Charger shown in  FIGS. 1B  and 12T PMOS 2-poly NVSRAM cell with a Flash Charger shown in  FIG. 1C  would be similar to the operations as explained above. In particularly, the Recall operations of the pseudo-10T 1-poly NMOS NVSRAM cell shown in  FIG. 2B  and pseudo-10T PMOS 2-poly NVSRAM cell shown in  FIG. 2C  would be similar to the operations for  FIG. 2A  as explained above. 
     In a specific embodiment,  FIG. 1B  shows another 12T NVSRAM cell with a Flash Charger but with 1-poly transistor Flash cell. All operations would be same as those for operating the 12T NVSRAM cell with a Flash Charger with 2-poly transistor type in  FIG. 1A  but with some differences in VPP and VNN voltages. In the NVSRAM memory using cells shown in  FIG. 1A , +/−18V is used for VPP and VNN. But in the NVSRAM memory using cells shown in  FIG. 1B , +/−10V is used for VPP and VNN due to reducing the number of layers. The FN-channel-erase and Fn-edge program operation for  FIG. 1B  has less tunneling electric field, thus slower erase and program speed. But in principle, the ΔVt generated by ramping the paired Flash Charger transistors, Mch 1  and Mch 2 , and ramping FWL to VDD to transfer the voltage level difference ΔV Q-QB  at Q and QB nodes of each SRAM cell can be achieved by using the same technique and steps. Thus the detailed description is skipped here for brevity. 
     In another specific embodiment, in  FIG. 1C  a 10T PMOS 2-poly NVSRAM cell uses 2-poly PMOS Flash transistor and 2-poly PMOS Flash Charger transistor, all operations and steps are the same except the voltage polarity of the FWL voltage has to be ramped from VDD to VSS because the opposite operating condition of the PMOS NVSRAM cell to NMOS NVSRAM cell. The PumpWL voltage is ramped up by using VPP, rather VNN to generate the positive charges in MC 3  and MC 4  channels. 
     Referring to  FIG. 2A  again, only one Flash Charger is required for two adjacent pseudo-10T NVSRAM cells in column direction of memory chip silicon layout. In addition, this Flash Charger includes one paired same 2-poly NMOS flash transistors of Mch 1  and Mch 2  that can be made right on the source-spacing of two pseudo-10T NVSRAM cells. As a result, the effective cell size becomes like a 10T NMOS 2-poly NVSRAM cell and is referred as a Pseudo-10T NVSRAM cell. Thus this Pseudo-10T 2-poly NVSRAM cell size can be further reduced from a regular pseudo-10T 2-poly NVSRAM cell size in  FIG. 1A  by around 15%. 
     As shown in the  FIG. 2A , the pseudo-10T NVSRAM cells with a shared flash Charger has no more floating source nodes. The major difference between  FIG. 1A  and  FIG. 2A  is the Pumped HV charges generated by the shared Flash Charger (Mch 1  and Mch 2 ) would be shared by one top Pseudo-10T NVSRAM cell and one bottom Pseudo-10T NVSRAM cell. As a result, the generated charged may not enough to sustain the voltage follower circuit for two NVSRAM cells in mirror. But this can be compensated by increasing the 2-fold charges by doubling the channel lengths of the Flash Charger transistors Mch 1  and Mch 2  to keep the same performance in the Recall operation as in  FIG. 1A  for the 12T NVSRAM cell with a larger cell size. 
     Other operations such as FN-channel Erase and FN-channel Program for the top Pseudo-10T NVSRAM cell and the bottom Pseudo-10T NVSRAM cell with a shared Flash Charger should be the same as the description in  FIG. 1A  for a 12T NVSRAM cell with a Flash Charger. 
     For example, the Erase operation can be performed simultaneously on MC 1  and MC 2  of the top Pseudo-10T NVSRAM cell and the MC 3  and MC 4  of the bottom Pseudo-10T NVSRAM cell by applying the same VPP voltage to FWL 1  in top Pseudo-10T NVSRAM cell and FWL 2  to the bottom Pseudo-10T NVSRAM cell on the same time with preset biased conditions of Q 1 =Q 1 B=Q 2 =Q 2 B=VSS and SWL 1 =SWL 2 =VSS to isolate top SRAM cell from top Flash cell and bottom SRAM cell from the bottom Flash cell. In today&#39;s NVSRAM cell, FWL 1  and FWL 2  can be shorted together into one with just one decoder in whole 16 Mb NVSRAM memory chip with all NVSRAM cells formed in M rows and N columns. The PumpWL is at a don&#39;t-care state which can be either at VDD or VSS. 
     Similarly, to program both MC 1  and MC 2  of the top Pseudo-10T NVSRAM cell and the MC 3  and MC 4  of the bottom Pseudo-10T NVSRAM cell, a same VNN voltage can be applied to FWL 1  and FWL 2  on the same time with the respective VDD and VSS inputs from top paired nodes of Q 1  and Q 1 B and the bottom paired nodes of Q 2  and Q 2 B set by respective top SRAM cell  210  and bottom SRAM cell  230 . Any Flash transistor&#39;s drain node connected to VDD voltage would get faster FN-edge program than the other Flash transistor&#39;s drain node connected to VSS. After a pre-determined program time, both paired MC 1  and MC 2  in  221  and MC 3  and MC 4  in  223  would get programmed to a desired ΔVt≧1V. 
     During a FN-edge program, the voltage of PumpWL line can be set to be VSS to isolate top and bottom NVSRAM cells. 
     When return back to normal SRAM operation, the FWL 1  and FWL 2  should be grounded if the Vts of all MC 1 , MC 2 , MC 3 , and MC 4  are positive values. If not, then FWL 1  and FWL can be coupled to a negative value of −2V if the lowest Vt in MC 1 , MC 2 , MC 3  and MC 4  is not lower than −2V. 
     In the 2-step SRAM amplification stage (see TABLE 3), the VDDP and VSSP can be tied together in this Pseudo-10T NVSRAM cells with a shared flash Charger, thus the first ramping up of VDDP and second ramping down of VSSP can be performed as a 10T NVSRAM cell. Thus the detailed operation description of the Pseudo-10T NVSRAM cells with a shared flash Charger is also skipped here for brevity for those skilled in this art without undue the scope of the claims herein. 
       FIG. 3  shows the graph of a FN-channel erase and FN-channel program operation vs flash gate and channel and time. The FN-channel program scheme in  FIG. 3  is used as an FN-channel Erase scheme for the present 12T and Pseudo-10T NVSRAM cell to increase MC 1  and MC 2  Vt in the beginning. With 1V difference in gate but same channel voltage, after 1 ms, the ΔVt can be 1V difference. Secondly, with 1 ms, the Flash transistor&#39;s Vt can be increased above positive 2V with gate voltage of 18V. This is used by this invention to set the paired Flash Vt to be a positive vale above VDD of 1.8V operation. 
     Conversely,  FIG. 4  shows the graph of a low-current FN-edge program to decrease the Vt of flash transistors of MC 1  and MC 2  for the present 12T NVSRAM cell with a flash Charger and Pseudo-10T NVSRAM cells with a shared flash Charger. 
     With 1V difference in the flash drain edges of MC 1  and MC 2  and a same gate voltage of −14V and same floating source. After 100 μs program time, the Vt difference between MC 1  and MC 2  ΔVt=0.8V is achieved. But after longer program time of 1-5 ms, the ΔVt is increased and kept constant with a ΔVt≈1.5V, which is larger than 1.0V as produced by using VPP FN-channel scheme with same program time. In summary, the FN-edge scheme has a stronger tunneling electric field than FN-channel scheme. Thus, with direct Q and QB voltage coupled to the paired Flash cells without using SBPI method, the FN-edge scheme can generate 1.5-fold ΔVt over the FN-channel scheme. 
     The other operations of another preferred embodiments of  FIG. 2B  1-poly Pseudo-10T NVSRAM cell and  FIG. 2C  2-poly PMOS Pseudo-10T NVSRAM cell are also skipped here without losing the spirit of the present invention. 
     Besides, due to a very low VDD and VSS inputs from SRAM&#39;s Q and QB nodes to the paired Flash cell, the channel length of MC 1  and MC 2  can be made with a minimum pitch to save the flash size, thus the cell size reduction for both the 12T NVSRAM cell with a Flash Charger and the pseudo-10T NVSRAM cell of the present invention. 
     One disadvantage of the SBPI scheme is that the channel of top and bottom Select transistors has to be big than 70 nm to prevent the Vds&gt;5V punch-through from occurring during the SBPI operation. Thus the overhead of Select transistor is big. 
     The FN-edge scheme can be used to allow the Program operation works without a SBPI method under a low VDD of 1V operation, provided an erase operation is done using FN-channel scheme to increase both Flash transistor Vts to a same higher initial value. 
     In summary, there are two preferred combination sets of biased conditions of Erase and Program operations for the present 12T NVSRAM cell with a flash Charger and Pseudo-10T NVSRAM cells with a shared flash Charger. These two sets of operation schemes are shown in the TABLE 4 below. 
     
       
         
           
               
               
               
             
               
                 TABLE 4 
               
               
                   
               
               
                 Operations 
                 1 st  Set 
                 2 nd  Set 
               
               
                   
               
             
            
               
                 Erase 
                 a) Use FN-channel to increase 
                 a) Use FN-channel to decrease 
               
               
                   
                 the Vt of MC1 and MC2 
                 the Vt of MC1 and MC2 
               
               
                   
                 simultaneously 
                 simultaneously 
               
               
                   
                 b) FWL = VPP = 18 V, 
                 b) FWL = VNN = −18 V, 
               
               
                   
                 MC1 Channel = MC2 
                 MC1 Channel = MC2 
               
               
                   
                 channel = VSS 
                 channel = VSS 
               
               
                 Program 
                 a) Use FN-edge to decrease 
                 a) Use FN-channel to increase 
               
               
                   
                 the Vt of MC1 and MC2 
                 the Vt of MC1 and MC2 
               
               
                   
                 simultaneously to achieve 
                 simultaneously to achieve 
               
               
                   
                 ΔVt &gt; 1 V 
                 ΔVt &gt; 1 V 
               
               
                   
                 b) FWL = VNN = −14 V 
                 b) FWL = VPP = +18 V 
               
               
                   
                 to −18 V 
               
               
                   
                 MC1 drain edge = VDD/VSS 
                 MC1 channel = VDD/VSS 
               
               
                   
                 and MC2 drain edge = 
                 and MC2 channel = 
               
               
                   
                 VSS/VDD 
                 VSS/VDD 
               
               
                   
               
            
           
         
       
     
       FIG. 5A  shows a simulation circuit containing one paired pseudo-10T NVSRAM cell with a shared flash Charger laid in the middle coupled to a control line PWL. The circuit embodiment should refer to the corresponding one shown in  FIG. 2A . Four source nodes of the Flash transistors are tied to a common VBST node for simplification of the simulation, which should not unduly limit the scope of the claims herein. 
       FIG. 5B  shows Recall simulation waveforms of a 12T NVSRAM cell with a flash Charger of  FIG. 1A  or pseudo-10T NVSRAM cells with a shared flash Charger of  FIG. 2A . The waveforms versus time are divided in several steps. The different times shows the desired steps of the Recall operation as explained in previous Table 3. Some numerical assumptions are made with MC 1 &#39;s Vt=2.2V but MC 2 &#39;s Vt=0.5V and ΔVt=1.7V=2.2V-0.5V with FWL ramped to 1.2V VDD and PWL (PumpWL) ramped to 6V. The simulation proves the DRAM-like charging scheme works at 1.2V VDD operation with a Flash Charger using 6V ramping gate signal to generate the required HV charges for the paired Flash Voltage Follower. 
     In the beginning 0 μs, the SG is ramped to 3V, which is larger than VDD+Vt=1.2V+0.7V=1.9V to allow the full connection between Flash cell and SRAM cell. At around 100 us, a SWL 1  and SWL 2  pulse is to set Q and QB to VSS for both top and bottom SRAM cells by grounding BL and BLB initially. 
     At 200 μs, the VSSP line of SRAM cell is ramped to 1.2V but VDDP is grounded reversely. 
     At around 208 μs, the FWL is ramped to VDD=1.2V to configure the Flash pair into the Voltage Follower pair, MC 1  and MC 2  pair and MC 3  and MC 4  pair of respective NVSRAM cells. 
     At time line 210 μs, the PumpWL (PWL) is ramped to 6V to generate the coupled HV charges below Mch 1  and Mch 2 . These HV charges are shared by top and bottom NVSRAM cells and then sent to respective Q 1 , Q 1 B, Q 2  and Q 2 B. 
     Since MC 2 =MC 4 =2.2V is higher than larger than MC 1 =MC 3 =0.5V, thus the final Voltages at Q 1 B=Q 2 B is larger than Q 1 =Q 2 . The ΔV Q-QB ≈0.4V at time line 220 μs. 
     The VDDP is ramped from VSS to VDD from at around 215 μs after PumpWL ramping. The Q 1 B=Q 2 B=VDD for the first SRAM amplification. At 250 μs, the VSSP is ramped down to VSS from VDD. As a result, the Q 1 =Q 2 =VSS after the second SRAM amplification. The small ΔVt of 1.7V is successfully detected and is fully amplified to a VDD and VSS. 
     Although the above has been illustrated according to specific embodiments, there can be other modifications, alternatives, and variations. It is understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.