Patent Publication Number: US-10312210-B2

Title: Semiconductor package

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This Application is a Continuation of U.S. application Ser. No. 14/535,643, filed Nov. 7, 2014,entitled “SEMICONDUCTOR PACKAGE,” which is hereby incorporated herein by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a semiconductor package, and in particular relates to a base design for a high-density semiconductor package. 
     Description of the Related Art 
     For a semiconductor chip package design, an increased number of input/output (I/O) connections for multi-functional chips is required. The impact of this will be pressure on printed circuit board (PCB) fabricators to minimize linewidth and space or to develop direct chip attach (DCA) semiconductors. However, the increased number of input/output connections of a multi-functional chip package may induce thermal electrical problems, for such as, problems with heat dissipation, cross talk, signal propagation delay, electromagnetic interference in RF circuits, etc. The thermal electrical problems may affect the reliability and quality of products. 
     Thus, a novel semiconductor package is desirable. 
     BRIEF SUMMARY OF THE INVENTION 
     A semiconductor package is provided. An exemplary embodiment of a semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via passes through the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via. 
     Another exemplary embodiment of a semiconductor package includes a base having a device-attach surface. A conductive via passes through the base. A semiconductor die is mounted on the base. The semiconductor die is in contact with the conductive structure by a conductive structure. 
     Yet another exemplary embodiment of a semiconductor package includes a conductive via passes through a base. The conductive via has a first terminal surface and a second terminal surface opposite to the first terminal surface. A semiconductor die is in contact with a first terminal surface of the conductive via by a conductive structure. A solder-ball is in contact with a second terminal surface of the conductive via. The second terminal surface is opposite to the first terminal surface. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is a cross-sectional view of a semiconductor package in accordance with some embodiments of the disclosure. 
         FIG. 2  is a plan view of a semiconductor die of a semiconductor package, showing the relationship between the conductive structures of the semiconductor die and the conductive vias of the base of the semiconductor package, in accordance with some embodiments of the disclosure. 
         FIGS. 3A and 3B  are cross sections showing one exemplary embodiment of a method for fabricating a base for a semiconductor package of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is determined by reference to the appended claims. 
     The present invention will be described with respect to particular embodiment s and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention. 
       FIG. 1  is a cross-sectional view of a semiconductor package  500  in accordance with some embodiments of the disclosure. In some embodiments, the semiconductor package  500  can be a flip chip package using conductive structures, for example, copper pillar bumps, connecting a semiconductor device to a base. As illustrated in  FIG. 1 , the semiconductor package  500  includes a base  200 , a semiconductor die  300  and conductive structures  222 ,  224 ,  226  and  228  in accordance with some embodiments of the disclosure. 
     In some embodiments as shown in  FIG. 1 , the base  200  includes a device-attach surface  201  and a solder-ball attach surface  203  opposite to the device-attach surface  201 . In some embodiments, the base  200 , for example a printed circuit board (PCB), may be a substrate which formed of polypropylene (PP). In some embodiments, a plurality of conductive vias  202 ,  204 ,  206  and  208  is disposed passing through the base  200 . As shown in  FIG. 1 , the conductive via  202  includes a first terminal surface  202   a  and a second terminal surface  202   b  opposite to the first terminal surface  202   a  in accordance with some embodiments of the disclosure. 
     In some embodiments, the first terminal surface  202   a  of the conductive via  202  may be aligned to the device-attach surface  201  of the base  200 . In some embodiments, the second terminal surface  202   b  of the conductive via  202  is not coplanar with the device-attach surface  201  of the base  200 . Similarly, the first terminal surfaces  204   a ,  206   a  and  208   a  of the conductive vias  204 ,  206  and  208  are designed to be aligned to the device-attach surface  201  of the base  200 , respectively. Second terminal surfaces  204   b ,  206   b  and  208   b  of the conductive vias  204 ,  206  and  208  are not coplanar with the device-attach surface  201  of the base  200 . In some other embodiments, additional metal films may be plated on the first terminal surface  202   a ,  204   a ,  206   a  and  208   a  of the conductive via  202 ,  204 ,  206  and  208 , respectively. The additional metal films may serve as extruding portions of the conductive via  202 ,  204 ,  206  and  208 . Therefore, the first terminal surface  202   a ,  204   a ,  206   a  and  208   a  of the conductive via  202 ,  204 ,  206  and  208  may extrude from the device-attach surface  201  of the base  200 . 
       FIGS. 3A and 3B  are cross sections showing one exemplary embodiment of a method for fabricating the base  200  (including base  200 - 1  and  200 - 2 ) for the semiconductor package  500  of the invention.  FIGS. 3A and 3B  also illustrate how the first terminal surface of the conductive via can be aligned to the device-attach surface of the base. In some embodiments, the method for fabricating bases for the semiconductor package  500  is also called a double-sided base fabricating process. Elements of the embodiments that are the same or similar as those previously described with reference to  FIGS. 1-2 , are not repeated hereinafter for brevity. As shown in  FIG. 3A , a carrier  400  with conductive seed layers  402   a  and  402   b  on the top surface  401  and the bottom surface  403  is provided. In some embodiments, the carrier  400  may comprise FR4 glass epoxy or stainless steel. Also, the conductive seed layers  402   a  and  402   b  are used as seed layers for subsequently formed conductive vias of bases. In some embodiments, the conductive seed layers  402   a  and  402   b  may comprise copper. 
     Next, as shown in  FIG. 3A , a laminating process is performed to respectively dispose a base material layer  406   a  and a base material layer  406   b  on the top surface  401  and the bottom surface  403  of the carrier  400 , wherein the base material layer  406   a  and a base material layer  406   b  respectively cover the first conductive traces  404   a  and  404   b . In some embodiments, the laminating process of the base material layer  406   a  and the base material layer  406   b  is simultaneously performed on the top surface  401  and the bottom surface  403  of the carrier  400 . In some embodiments, the base material layer  406   a  and the base material layer  406   b  may include polypropylene (PP). In some embodiments, the base material layer  406   a  includes a device-attach surface  201 - 1  and a solder-ball attach surface  203 - 1 . Similarly, the base material layer  406   b  includes a device-attach surface  201 - 2  and a solder-ball attach surface  203 - 2 . As shown in  FIG. 3A , the device-attach surfaces  201 - 1  and  201 - 2  are in contact with the conductive seed layers  402   a  and  402   b , respectively. The solder-ball attach surfaces  203 - 1  and  203 - 2  are respectively opposite to the device-attach surfaces  201 - 1  and  201 - 2 . In some embodiments, the solder-ball attach surfaces  203 - 1  and  203 - 2  are away from the conductive seed layers  402   a  and  402   b , respectively. 
     Next, please refer to  FIG. 3A  again, wherein a drilling process is performed to form openings (not shown) through the base material layer  406   a  and the base material layer  406   b  to define the positions of subsequently formed conductive vias  202 - 1 ,  202 - 2 ,  204 - 1 ,  204 - 2   206 - 1 ,  206 - 2 ,  208 - 1  and  208 - 2 . In some embodiments, the drilling process may comprise a laser drilling process, an etching drilling process or mechanical drilling process. Next, a plating process and an anisotropic etching process is performed to fill a conductive material into the openings to form the conductive vias  202 - 1 ,  204 - 1 ,  206 - 1 ,  208 - 1  through the base material layer  406   a , and to form the conductive vias  202 - 2 ,  204 - 2 ,  206 - 2  and  208 - 2  through the base material layer  406   b . In some embodiments, the drilling process, the plating process and the anisotropic etching process are simultaneously performed on the base material layer  406   a  and the base material layer  406   b . In some embodiments, the plating process may comprise an electrical plating process. 
     As shown in  FIG. 3A , the conductive vias  202 - 1 ,  204 - 1 ,  206 - 1 ,  208 - 1  respectively have first terminal surfaces  202   a - 1 ,  204   a - 1 ,  206   a - 1  and  208   a - 1  and second terminal surfaces  202   b - 1 ,  204   b - 1 ,  206   b - 1  and  208   b - 1 . The second terminal surfaces  202   b - 1 ,  204   b - 1 ,  206   b - 1  and  208   b - 1  are respectively opposite to the first terminal surfaces  202   a - 1 ,  204   a - 1 ,  206   a - 1  and  208   a - 1 . Similarly, the conductive vias  202 - 2 ,  204 - 2 ,  206 - 2 ,  208 - 2  respectively have first terminal surfaces  202   a - 2 ,  204   a - 2 ,  206   a - 2  and  208   a - 2 , and second terminal surfaces  202   b - 2 ,  204   b - 2 ,  206   b - 2  and  208   b - 2 . The second terminal surfaces  202   b - 2 ,  204   b - 2 ,  206   b - 2  and  208   b - 2  are respectively opposite to the first terminal surfaces  202   a - 2 ,  204   a - 2 ,  206   a - 2  and  208   a - 2 . 
     As shown in  FIG. 3A , the device-attach surface  201 - 1  of the base material layer  406   a  and the device-attach surface  201 - 2  of the base material layer  406  are in contact with the conductive seed layers  402   a  and  402   b , respectively. Therefore, the first terminal surfaces  202   a - 1 ,  204   a - 1 ,  206   a - 1  and  208   a - 1  of the conductive vias  202 - 1 ,  204 - 1 ,  206 - 1 ,  208 - 1  are aligned to the device-attach surface  201 - 1  of the base material layer  406   a  after performing the plating process and anisotropic etching process. The second terminal surfaces  202   b - 1 ,  204   b - 1 ,  206   b - 1  and  208   b - 1  are not required to be coplanar with the solder-ball attach surface  203 - 1  of the base material layer  406   a . Similarly, the first terminal surfaces  202   a - 2 ,  204   a - 2 ,  206   a - 2  and  208   a - 2  of the conductive vias  202 - 2 ,  204 - 2 ,  206 - 2 ,  208 - 2  are aligned to the device-attach surface  201 - 2  of the base material layer  406   b . The second terminal surfaces  202   b - 2 ,  204   b - 2 ,  206   b - 2  and  208   b - 2  are not required to be coplanar with the solder-ball attach surface  203 - 2  of the base material layer  406   a.    
     Next, as shown in  FIG. 3B , the base material layer  406   a  and the base material layer  406   b  are respectively separated from the top surface  401  and the bottom surface  403  of the carrier  400  to form bases  200 - 1  and  200 - 2 , which are separated from each other. Next, as shown in  FIG. 3B , again, the conductive seed layers  402   a  and  402   b  are removed from the bases  200 - 1  and  200 - 2 , respectively. 
     Please return to  FIG. 1 , because the first terminal surfaces  202   a ,  204   a ,  206   a  and  208   a  of the conductive vias  202 ,  204 ,  206 ,  208  are designed to be aligned to the device-attach surface  201  of the base  200 . The first terminal surfaces  202   a ,  204   a ,  206   a  and  208   a  of the conductive vias  202 ,  204 ,  206 ,  208  can be provided the conductive structures  222 ,  224 ,  226  and  228 , for example, copper pillar bumps, directly disposed thereon. In some embodiments, the second terminal surfaces  202   b ,  204   b ,  206   b  and  208   b  of the conductive vias  202 ,  204 ,  206  and  208  are provided solder balls  212 ,  214 ,  216  and  218  disposed thereon, respectively. 
     As shown in  FIG. 1 , the semiconductor die  300  is mounted on the die attach surface  201  of the base  200  by the conductive structures  222 ,  224 ,  226  and  228  in accordance with some embodiments of the disclosure. In some embodiments, an active surface of the semiconductor die  300  faces the base  200  by a bonding process. Circuits of the semiconductor die  300  are disposed on the active surface. In some embodiments, pads  302 ,  304 ,  306 ,  308  are disposed on the top of the circuitry of the semiconductor die  300 . In some embodiments, the pads  302 ,  304 ,  306 ,  308  belong to the uppermost metal layer of the interconnection structure (not shown) of the semiconductor die  300 . In some embodiments, the pads  302 ,  304 ,  306 ,  308  are arranged in the central area of the first semiconductor die  310  to be used to transmit ground or power signals of the semiconductor die  300 . Also, for the clear illustration of the relationship between the conductive structures  222 ,  224 ,  226  and  228  used for power or ground pads  302 ,  304 ,  306 ,  308  of the semiconductor die  300  and the conductive vias  202 ,  204 ,  206 ,  208  of the base  200 , the conductive structures used for signal pads of the semiconductor dies are not shown in the figures ( FIGS. 1 and 2 ). 
     As shown in  FIG. 1 , a first passivation layer  310  is conformably formed covering the pads  302 ,  304 ,  306 ,  308  of the semiconductor die  300 , in accordance with some embodiments of the disclosure. In some embodiments, the first passivation layer  310  is formed by deposition and patterning processes. In some embodiments, the first passivation layer  310  may be formed of materials including oxide, nitride, or oxynitride. In some embodiments, the first passivation layer  310  has openings on the pads  302 ,  304 ,  306 ,  308  of the semiconductor die  300 , so that a portion of the pads  302 ,  304 ,  306 ,  308  are respectively exposed from the openings. 
     In some embodiments, a second passivation layer  312  with openings therethrough is formed on the first passivation layer  310 , as shown in  FIG. 1 . In some embodiments, the second passivation layer  312  is formed by a coating patterning and curing process. In some embodiments, the second passivation layer  312  may comprise polyimide for providing reliable insulation when the semiconductor die  300  is subjected to various types of environmental stresses. A portion of each of the pads  302 ,  304 ,  306 ,  308  of the semiconductor die  300  is respectively exposed from the openings of the second passivation layer  312 . 
     In some embodiments, the semiconductor package  500  uses the conductive structures  222 ,  224 ,  226  and  228  respectively connecting the power and ground pads of the semiconductor die  300  to the base  200  as shown in  FIG. 1  (the conductive structures used for the signal pad of the semiconductor die are not shown in  FIG. 1 ). In some embodiments, each of the conductive structures may be a copper pillar bump structure composed of a metal stack comprising a UBM (under bump metallurgy) layer, a conductive pillar, a conductive buffer layer, and a solder cap. In some embodiments, the conductive structures  222 ,  224 ,  226  and  228  are bump on trace (BOT) structures and rectangular in a plan view as shown in  FIG. 2 . In some other embodiments, the conductive structures  222 ,  224 ,  226  and  228  can be designed to have other 180-degree rotationally symmetrical shapes, for example, an oval-shape or an octagonal shape. 
     As shown in  FIG. 1 , under bump metallurgy (UBM) layer patterns  314 ,  316 ,  318  and  320  of the conductive structure  222 ,  224 ,  226  and  228  are formed on the second passivation layer  312 , which is disposed on the semiconductor die  300 , in accordance with some embodiments of the disclosure. In some embodiments, the UBM layer patterns  314 ,  316 ,  318  and  320  are formed by a deposition method such as a sputtering or plating method and a subsequent anisotropic etching process. The anisotropic etching process is performed after forming conductive pillars. In some embodiments, the UBM layer patterns  314 ,  316 ,  318  and  320  line sidewalk and bottom surfaces of the openings of the second passivation layer  312 . Also, the UBM layer patterns  314 ,  316 ,  318  and  320  extend over the top surface of the second passivation layer  312 . In one embodiment, the UBM layer patterns  314 ,  316 ,  318  and  320  are composed of a Ti layer and a Cu layer on the Ti layer. 
     As shown in  FIG. 1 , conductive pillars  222   a ,  224   a ,  226   a  and  228   a  are respectively formed on the UBM layer patterns  314 ,  316 ,  318  and  320 , in accordance with some embodiments of the disclosure. The conductive pillars  222   a ,  224   a ,  226   a  and  228   a  are separated from each other. In some embodiments, the conductive pillars  222   a ,  224   a ,  226   a  and  228   a  respectively fill the openings of the second passivation layer  312  disposed on the semiconductor die  300 . It should be noted that the conductive pillar and the UBM layer patterns within the same opening may form an integral plug of the resulting conductive structure. Formation positions of the conductive pillars  222   a ,  224   a ,  226   a  and  228   a  are defined by a dry film photoresist or liquid photoresist patterns (not shown). In some embodiments, the conductive pillars  222   a ,  224   a ,  226   a  and  228   a  are used as solder joints for subsequent conductive structures, which are used to transmit ground or power signals of the semiconductor die  300 , disposed thereon. Therefore, the conductive pillars  222   a ,  224   a ,  226   a  and  228   a  may help to increase the mechanical strength of the bump structure. In some embodiments, the conductive pillars  222   a ,  224   a ,  226   a  and  228   a  may be formed of copper, so that deformation may be prevented during a subsequent solder re-flow process. 
     As shown in  FIG. 1 , conductive buffer layers  222   b ,  224   b ,  226   b  and  228   b  are respectively formed on the corresponding conductive pillars  222   a ,  224   a ,  226   a  and  228   a , in accordance with some embodiments of the disclosure. In some embodiments, the conductive buffer layers  222   b ,  224   b ,  226   b  and  228   b  are formed by an electroplating method. In some embodiments, the conductive buffer layers  222   b ,  224   b ,  226   b  and  228   b  are optional elements serving as a seed layer, an adhesion layer and a barrier layer for subsequent conductive bumps formed thereon. In some embodiments, the conductive buffer layers  222   b ,  224   b ,  226   b  and  228   b  may comprise Ni. In some embodiments, the number of conductive buffer layers corresponds to the number of conductive pillars designed on the semiconductor die  300 . 
     As shown in  FIG. 1 , solder caps  222   c ,  224   c ,  226   c  and  228   c  are respectively formed on the corresponding conductive buffer layers  222   b ,  224   b ,  226   b  and  228   b , in accordance with some embodiments of the disclosure. In some embodiments, the solder caps  222   c    224   c ,  226   c  and  228   c  are formed by electroplating a solder material with a patterned photoresist layer or by a screen printing process and a subsequent solder re-flow process. As shown in  FIG. 1 , the UBM layer pattern  314 , the conductive pillar  222   a , the conductive buffer layers  222   b  (optional element), and solder cap  222   c  collectively form the conductive structure  222 . The UBM layer pattern  316 , the conductive pillar  224   a , the conductive buffer layers  224   b  (optional element), and solder cap  224   c  collectively form the conductive structure  224 . The UBM layer pattern  318 , the conductive pillar  226   a , the conductive buffer layers  226   b  (optional element), and solder cap  226   c  collectively form the conductive structure  226 . The UBM layer pattern  320 , the conductive pillar  228   a , the conductive buffer layers  228   b  (optional element), and solder cap  228   c  collectively form the conductive structure  228 . 
     In some embodiments, a solder resistance layer  230  is disposed on the base  200 , away from an overlap region between the semiconductor die  300  and the base  200  as shown in  FIG. 1 . In some embodiments, the solder resistance layer  230  is formed by electroplating with a patterned photoresist layer or by a screen printing process. 
     In some embodiments, an underfill material or the underfill  232  can be introduced into the gap between the semiconductor die  300  and the base  200  as shown  FIG. 1 . The underfill  212  covers the conductive structures  224 - 228  and is adjacent to the solder resistance layer  230 . In some embodiments, the underfill  232  may comprise a capillary underfill (CUF), molded underfill (MUF) or a combination thereof. 
     As shown in  FIG. 1 , a molding compound  234  is formed covering the semiconductor die  300 , the solder resistance layer  230 , the underfill  232  and the device-attach surface  201  of the base  200  close to the semiconductor die  300 . In some embodiments, the molding material  234  may be formed of molding materials such as resin. 
       FIG. 2  is a plan view of the semiconductor die  300  of the semiconductor package  500 , in accordance with some embodiments of the disclosure. Also,  FIG. 2  shows the relationship between the conductive structures and the conductive vias of the base of the semiconductor package, in accordance with some embodiments of the disclosure.  FIG. 1  is also a cross-sectional view taken along line A-A′ of  FIG. 2 . It should be noted that for the clear illustration of the relationship between the conductive structures used for power or ground pads of the semiconductor die and the conductive vias of the base of the semiconductor package, the conductive structures and the conductive vias corresponding to the signal pads of the semiconductor die are not shown in  FIG. 2 . Also, the solder resistance layer, the underfill and the molding compound of the semiconductor package  500  are not shown in  FIG. 2 . 
     As shown in  FIGS. 1 and 2 , the first terminal surfaces  202   a ,  204   a ,  206   a  and  208   a  of the conductive vias  202 ,  204 ,  206 ,  208  are designed to be aligned to the device-attach surface  201  of the base  200  according to the fabrication process, in accordance with some embodiments of the disclosure. The first terminal surfaces  202   a ,  204   a ,  206   a  and  208   a  of the conductive vias  202 ,  204 ,  206 ,  208  can be provided the conductive structures  222 ,  224 ,  226  and  228 , for example, copper pillar bumps, directly disposed thereon. Therefore, the first terminal surfaces  202   a ,  204   a ,  206   a  and  208   a  of the conductive vias  202 ,  204 ,  206 ,  208  also serve as interfaces between the conductive structures  222 ,  224 ,  226  and  228  and the conductive vias  202 ,  204 ,  206 ,  208 , respectively. In some embodiments, the second terminal surfaces  202   b ,  204   b ,  206   b  and  208   b  of the conductive vias  202 ,  204 ,  206  and  208  are provided solder balls  212 ,  214 ,  216  and  218  directly disposed thereon, respectively. Therefore, the second terminal surfaces  202   b ,  204   b ,  206   b  and  208   b  of the conductive vias  202   a ,  204   a ,  206   a  and  208   a  may also serve as interfaces between the conductive vias  202 ,  204 ,  206 ,  208  and the solder bails  212 ,  214 ,  216  and  218 . 
     In some embodiments, the conductive vias of the base  200  are defined as extending only along a direction substantially vertical to the device-attach surface  201  and the solder-ball attach surface  203  of the base  200  as shown in  FIGS. 1 and 2 . The terminal surfaces of the conductive vias, which are close to the device-attach surface  201  of the base  200 , do not have any redistribution routing function. That is to say, the conductive via plugs of the base  200  do not have any segments extending substantially along the device-attach surface  201  of the base  200 . In some embodiments, no conductive pad is disposed on the base, covering the terminal surface of the conductive via, which is close to the device-attach surface  201  of the base  200 . That is to say, there is no conductive pad disposed between the conductive structure and the conductive via passing through the base  200 . In some embodiments, the first terminal surfaces  202   a ,  204   a ,  206   a  and  208   a  respectively fully overlap with the second terminal surfaces  202   b ,  204   b ,  206   b  and  208   b  of the conductive vias  202 ,  204 ,  206  and  208  in a cross-sectional view as shown in  FIG. 1  and in a plan view as shown in  FIG. 2 . Similarly, first terminal surfaces of the conductive vias  232   a - 232   c ,  234   a - 234   c ,  236   a - 236   c  and  238   a - 238   c , which are provided conductive structures  242   a - 242   c ,  244   a - 244   c ,  246   a - 246   c  and  248   a - 248   c  directly disposed thereon, are designed to fully overlap with second terminal surfaces of the conductive vias  232   a - 232   c ,  254   a - 234   c ,  236   a - 236   c  and  238   a - 238   c , which are provided the solder balls  252   a - 252   c ,  254   a - 254   c ,  256   a - 256   c  and  258   a - 258   c  disposed thereon, respectively, in accordance with some embodiments of the disclosure as shown in  FIG. 2 . 
     In some embodiments, the conductive structures of the semiconductor package  500  can be designed to fully or partially overlap with the corresponding conductive vias of the base  200  in a cross-sectional view as shown in  FIG. 1  and in a plan view as shown in  FIG. 2 . The arrangement of the conductive structures is not limited by the positions of the corresponding conductive vias of the base. For example, the conductive structures are not required to be disposed spaced apart from the corresponding conductive vias of the base. Therefore, the input/output (I/O) connection counts of the semiconductor die  300  and the conductive via counts of the base  200  can be improved, a high-density semiconductor package is achieved. For example, the conductive structures  222 ,  226 ,  242   a ,  242   b ,  242   c ,  244   b  are designed to fully overlap with the corresponding conductive vias  202 ,  206 ,  232   a ,  232   b ,  232   c ,  234   b  of the base  200  as shown in  FIGS. 1 and 2 . For example, the conductive structures  224 ,  228 ,  244   a ,  244   c ,  246   a - 246   c ,  248   a - 248   c  are designed to partially overlap with the corresponding conductive vias  204 ,  208 ,  234   a ,  234   c ,  236   a - 236   c ,  238   a - 238   c  of the base  200  as shown in  FIGS. 1 and 2 . 
     In some embodiments, the conductive vias of the base  200  are designed to fully overlap with the corresponding solder balls on the base  200  in a cross-sectional view as shown in  FIG. 1  and in a plan view as shown in  FIG. 2 . Therefore, the conductive structures of the semiconductor package  500  can be designed to fully overlap or partially overlap the corresponding solder balls, in accordance with some embodiments of the disclosure as shown in  FIGS. 1 and 2 . For example, the conductive structures  222 ,  226 ,  242   a ,  242   b ,  242   c ,  244   b  are designed to fully overlap with the corresponding solder balls  212 ,  216 ,  252   a ,  252   b ,  252   c ,  254   b  on the base  200  as shown in  FIGS. 1 and 2 . For example, the conductive structures  224 ,  228 ,  244   a ,  244   c ,  246   a - 246   c ,  248   a - 248   c  are designed to partially overlap with the corresponding conductive vias  214 ,  218 ,  254   a ,  254   c ,  256   a - 256   c ,  258   a - 258   c  on the base  200  as shown in  FIGS. 1 and 2 . 
     Embodiments provide a semiconductor package. The semiconductor die of the semiconductor package connects to the base using conductive structures, which is in contact with the corresponding conductive vias passing through the base. The conductive structures are designed to connect to power or ground pads of the semiconductor die. According to the design of the base, the interface between the conductive structure and the corresponding conductive via is aligned to the device-attach surface of the base. The conductive structure can be designed to be in contact with the corresponding conductive via without any conductive pad or redistribution pattern. The arrangement of the conductive structures is not limited by the positions of the corresponding conductive vias of the base. The input/output (I/O) connection counts of the semiconductor die and the conductive via counts of the base can be improved, and a high-density semiconductor package is achieved. Also, the semiconductor package may have improved the voltage drop across the network in the package. Also, the heat generated from the semiconductor die can be quickly dissipated to the outside due to the shortened path (The conductive structure can be design to be in contact with the corresponding conductive via without any conductive pad or redistribution pattern). The thermal performance of the semiconductor package can be improved. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.