Patent Publication Number: US-2023154879-A1

Title: Semiconductor device, a package substrate, and a semiconductor package

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority to Korean Patent Application No. 10-2021-0157869, filed on Nov. 16, 2021, which is herein incorporated by reference in its entirety. 
     BACKGROUND 
     1. Technical Field 
     The present disclosure provides semiconductor devices having bump pillars and methods of manufacturing the semiconductor devices, package substrates having land pillars, and semiconductor packages having the semiconductor devices and the package substrates. 
     2. Related Art 
     A distance between input and output (I/O) pads of a semiconductor device and a distance between bump lands of a package substrate are gradually decreasing. Accordingly, a gap between solder bumps bonding and connecting the semiconductor device and the package substrate is getting smaller and a problem such as a bridge between the solder bumps occurs. 
     SUMMARY 
     A semiconductor device according to an embodiment of the present disclosure may include a substrate, input and output (I/O) pads disposed at an upper portion of the semiconductor substrate, and first bump pillars disposed over the I/O pads. The first bump pillars are selectively arranged over some of the I/O pads in a first horizontal direction. 
     A semiconductor package according to an embodiment of the present disclosure may include a semiconductor device stacked over a package substrate. The semiconductor device may include a semiconductor substrate, input and output (I/O) pads disposed adjacent to one surface of the semiconductor substrate, and first bump pillars disposed over the I/O pads. The first bump pillars may be selectively arranged over some of the I/O pads in a first horizontal direction. The package substrate may include a base layer, and bump lands disposed at an upper portion of the base layer. Each of the bump lands may be vertically aligned with each of the I/O pads. 
     A semiconductor package according to an embodiment of the present disclosure may include a semiconductor device stacked over a package substrate. The semiconductor device may include a semiconductor substrate, input and output (I/O) pads disposed adjacent to one surface of the semiconductor substrate, and first bump pillars disposed over the input/out pads. The first bump pillars may be arranged to skip one by one over the I/O in a first horizontal direction. The package substrate may include a base layer, bump lands disposed at an upper portion of the base layer, and first land pillars disposed over the bump lands. The first land pillars may be arranged to skip one by one over the bump lands in the first horizontal direction. Each of the first bump pillars and each of the first land pillars may be exclusively arranged not to be vertically aligned with each other. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1 A  is a longitudinal cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure, and  FIGS.  1 B and  1 C  are perspective views of the semiconductor device. 
         FIG.  2 A  is a longitudinal cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure, and  FIGS.  2 B and  2 C  are perspective views of the semiconductor device. 
         FIGS.  3 A and  3 B  are longitudinal cross-sectional views schematically illustrating package substrates according to embodiments of the present disclosure. 
         FIGS.  4 A,  4 B,  4 C, and  4 D  are longitudinal cross-sectional views schematically illustrating semiconductor packages according to embodiments of the present disclosure. 
         FIGS.  5 A,  5 B,  5 C, and  5 D  are longitudinal cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, and  FIGS.  5 E,  5 F,  5 G,  5 H,  5 I,  5 J, and  5 K  are cross-sectional views illustrating methods manufacturing semiconductor packages according to embodiments of the present disclosure using the semiconductor device. 
         FIG.  6 A  is a longitudinal cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, and  FIGS.  6 B,  6 C,  6 D,  6 E, and  6 F  are cross-sectional views illustrating a method of manufacturing semiconductor packages according to embodiments of the present disclosure using the semiconductor device. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present disclosure will be described below in more detail with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
     It will be understood that, although the terms “first” and/or “second” may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element, from another element. For instance, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. Similarly, the second element could also be termed the first element. 
     Other expressions that explain the relationship between elements, such as “between”, “directly between”, “adjacent to” or “directly adjacent to” should be construed in the same way. 
     The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer with no intervening layers but also to a case where intervening layers are formed between the first and second layers. It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. 
     Embodiments of the present disclosure provide semiconductor devices having bump pillars selectively disposed thereon and methods of manufacturing the semiconductor devices. 
     Embodiments of the present disclosure provide semiconductor devices having first bump pillars and second bump pillars having different heights, and methods of manufacturing the semiconductor device. 
     Embodiments of the present disclosure provide package substrates having land pillars selectively disposed thereon. 
     Embodiments of the present disclosure provide package substrates having first land pillar and second land pillars having different heights. 
     Embodiments of the present disclosure provide semiconductor packages in which the semiconductor devices and the package substrates are bonded. 
       FIG.  1 A  is a longitudinal cross-sectional view showing a semiconductor device  100 A according to an embodiment of the present disclosure, and  FIGS.  1 B and  1 C  are perspective views of the semiconductor device  100 A. Referring to  FIGS.  1 A to  1 C , a semiconductor device  100 A according to an embodiment of the present disclosure may include a semiconductor substrate  110  having input and output (I/O) pads  120 , a passivation layer  130 , barrier layers  140 , and a first bump pillars  151 . 
     The semiconductor substrate  110  may include a silicon wafer, and internal circuits and a plurality of insulating layers formed on a surface of the silicon wafer. The internal circuits may include a plurality of transistors, a plurality of metal vias, multi-layered metal interconnections, and the I/O pads  120 . 
     The I/O pads  120  may be disposed in an upper portion of the semiconductor substrate  110  adjacent to a top surface of the semiconductor substrate  110 . Top surfaces of the I/O pads  120  may be exposed. The I/O pads  120  may include a metal such as aluminum (Al). 
     The passivation layer  130  may be formed on the top surfaces of the semiconductor substrate  110  to partially expose the top surfaces of the I/O pads  120 . The passivation layer  130  may include an insulating material. For example, the passivation layer  130  may include a polymeric organic material such as polyimide isoindro quindzoline (PIQ), or an inorganic material such as silicon nitride (SiN) or silicon oxide (SiO 2 ). 
     The barrier layers  140  may be formed on the I/O pads  120 . Ends of the barrier layers  140  may extend onto the passivation layer  130 . The barrier layers  140  may include a metal layer. The barrier layers  140  may include a lower layer including a barrier metal layer such as a titanium (Ti) layer and an upper layer including a seed metal layer such as a copper (Cu) layer. For example, the barrier layers  140  may include a titanium/copper (Ti/Cu) layer. 
     The first bump pillars  151  may be selectively formed on some of the I/O pads  120  or some of the barrier layers  140 . For example, the first bump pillars  151  may be arranged to skip every other one of the I/O pads  120  or the barrier layers  140 . The first bump pillars  151  may include a metal such as copper. In an embodiment, the first bump pillars  151  may be alternately disposed on the I/O pads  120  or the barrier layers  140  by serially skipping every other I/O pad  120  or the barrier layer  140  as, for example, shown in  FIG.  1 A  or  FIG.  1 B . 
     Referring to  FIG.  1 B , the I/O pads  120  may be arranged on one or more rows in a first horizontal direction D 1 . For example, as shown in  FIG.  1 B , the I/O pads  120  may include the I/O pads  120  arranged side-by-side on two rows in the first horizontal direction D 1 . The first bump pillars  151  may be selectively disposed on some of the I/O pads  120  in the first horizontal direction D 1 . For example, the first bump pillars  151  may be arranged to skip every other one of the I/O pads  120  in the first horizontal direction D 1 . The passivation layer  130  and the barrier layers  140  shown in  FIG.  1 A  are omitted to make it easier to understand the arrangements of the I/O pads  120  and the first bump pillars  151 . 
     Referring to  FIG.  1 C , the I/O pads  120  may be arranged on a plurality of rows and columns in the first horizontal direction D 1  and a second horizontal direction D 2 . For example, the I/O pads  120  may be arranged in a matrix form. The first bump pillars  151  may be selectively disposed on some of the I/O pads  120  in the first horizontal direction D 1  and the second horizontal direction D 2 . For example, the first bump pillars  151  may be arranged to skip every other one of the I/O pads  120  in the first horizontal direction D 1  and the second horizontal direction D 2 . The first horizontal direction D 1  and the second horizontal direction D 2  may be perpendicular to each other. In an embodiment, the first bump pillars  151  may be alternately disposed on the I/O pads  120  or the barrier layers  140  by serially skipping every other I/O pad  120  or the barrier layer  140  for at least one of the first direction D 1  and the second direction D 2  as, for example, shown in  FIG.  1 C . 
     As shown in  FIGS.  1 B and  1 C , the first bump pillars  151  may be arranged to be aligned on virtual parallel diagonal lines in the diagonal direction D 3 . 
       FIG.  2 A  is a longitudinal cross-sectional view illustrating a semiconductor device  100 B according to an embodiment of the present disclosure, and  FIGS.  2 B and  2 C  are perspective views of the semiconductor device  100 B. Referring to  FIGS.  2 A to  2 C , a semiconductor device  100 B according to an embodiment of the present disclosure may include a semiconductor substrate  110  having I/O pads  120 , a passivation layer  130 , barrier layers  140 , first bump pillars  151 , and second bump pillars  152 . The first bump pillars  151  may have a first height h 1 , and the second bump pillars  152  may have a second height h 2 . The first height h 1  and the second height h 2  may be different from each other. For example, the first height h 1  may be greater than the second height h 2 . (h 1 &gt;h 2 ) The first bump pillars  151  and the second bump pillars  152  may be alternately arranged in the first horizontal direction D 1 . 
     Referring to  FIG.  2 B , the I/O pads  120  may be arranged on one or more rows in the first horizontal direction D 1 . For example, as shown in  FIG.  2 B , the I/O pads  120  may be arranged side-by-side on two rows in the first horizontal direction D 1 . The first bump pillars  151  and the second bump pillars  152  may be alternately arranged on the I/O pads  120  in the first horizontal direction D 1 . The passivation layer  130  and the barrier layers  140  are omitted to make it easier to understand the arrangements of the I/O pads  120 , the first bump pillars  151 , and the second bump pillars  152 . 
     Referring to  FIG.  2 C , the I/O pads  120  may be arranged on a plurality of rows and columns in the first horizontal direction D 1  and the second horizontal direction D 2 . For example, the I/O pads  120  may be arranged in a matrix form. The first bump pillars  151  and the second bump pillars  152  may be alternately arranged in the first horizontal direction D 1  and the second horizontal direction D 2 . 
     As shown in  FIGS.  2 B and  2 C , the first bump pillars  151  and the second bump pillars  152  may be arranged to be aligned on virtual parallel diagonal lines in the diagonal direction D 3 , respectively. 
       FIGS.  3 A and  3 B  are longitudinal cross-sectional views schematically illustrating package substrates  200 A and  200 B according to embodiments of the present disclosure. Referring to  FIG.  3 A , a package substrate  200 A according to an embodiment of the present disclosure may include a base layer  210  having bump lands  220 , a solder resist layer  230 , and first land pillars  251 . 
     The base layer  210  may include a printed circuit board (PCB). For example, the base layer  210  may include prepreg layers and metal layers alternatively stacked. The bump lands  220  may be disposed at an upper portion of the base layer  210  adjacent to a top surface of the base layer  210 . Top surfaces of the bump lands  220  may be exposed. The bump lands  220  may include a metal such as copper (Cu). 
     The solder resist layer  230  may be formed on the base layer  210  to partially expose the top surfaces of the bump lands  220 . 
     The first land pillars  251  may be selectively formed on some of the bump lands  220 . The first land pillars  251  may be alternately disposed to skip every other one of the bump lands  220 . The first land pillars  251  may include a metal such as copper (Cu). In an embodiment, the first land pillars  251  may be alternately disposed on the bump lands  220  by serially skipping every other bump land  220  as for example shown in  FIG.  3 B . 
     Referring to  FIG.  3 B , a package substrate  200 B according to an embodiment of the present disclosure may include a base layer  210  having bump lands  220 , a solder resist layer  230 , first land pillars  251 , and second land pillars  252 . The first land pillars  251  may have a third height h 3 , and the second land pillars  252  may have a fourth height h 4 . The third height h 3  and the fourth height h 4  may be different from each other. For example, the third height h 3  may be greater than the fourth height h 4 . (h 3 &gt;h 4 ) The first land pillars  251  and the second land pillars  252  may be alternately arranged in a horizontal direction. 
     A height difference between the first height h 1  of the first bump pillars  151  and the second height h 2  of the second bump pillars  152  in  FIGS.  2 A to  2 C  may be substantially same as a difference between the third height h 3  of the first land pillars  251  and the fourth height h 4  of the second land pillars  252  in  FIG.  3 B  (h 1 −h 2 ≈h 3 −h 4 ). In some embodiments, the heights may be referred to as vertical heights. 
       FIGS.  4 A to  4 D  are longitudinal cross-sectional views schematically illustrating semiconductor packages  300 A- 300 D according to embodiments of the present disclosure. Referring to  FIGS.  4 A to  4 D , semiconductor packages  300 A- 300 D according to embodiments of the present disclosure may include semiconductor devices  100 A and  100 B stacked on package substrates  200 A and  200 B, respectively. The package substrates  200 A and  200 B and the semiconductor devices  100 A and  100 B may be bonded and connected with each other using solder bumps SB. 
     Referring to  FIG.  4 A , with further reference to  FIGS.  1 A and  3 A , the barrier layers  140  on which the first bump pillars  151  do not disposed of the semiconductor device  100 A and the first land pillars  251  of the package substrate  200 A may be electrically and physically connected with each other using the solder bumps SB, and the first bump pillars  151  of the semiconductor device  100 A and the bump lands  220  on which the first land pillars  251  do not disposed of the package substrate  200 A may be electrically and physically connected with each other using the solder bumps SB. The first bump pillars  151  of the semiconductor device  100 A and the first land pillars  251  of the package substrate  200 A may be alternately arranged with each other. Accordingly, the first bump pillars  151  of the semiconductor device  100 A and the first land pillars  251  of the package substrate  200 A may not be aligned and connected with each other. 
     Referring to  FIG.  4 B , with further reference to  FIGS.  1 A and  3 B , the barrier layers  140  on which the first bump pillars  151  do not disposed of the semiconductor device  100 A and the first land pillars  251  of the package substrate  200 B may be electrically connected or physically connected with each other using the solder bumps SB, and the first bump pillars  151  of the semiconductor device  100 A and the second land pillars  252  of the package substrate  200 B may be electrically and physically connected with each other using the solder bumps SB. 
     Referring to  FIG.  4 C , with further reference to  FIGS.  2 A and  3 A , the first bump pillars  151  of the semiconductor device  100 B and the bump lands  220  on which the first land pillars  251  do not disposed of the package substrate  200 A may be electrically and physically connected with each other using the solder bumps SB, and the second bump pillars  152  of the semiconductor device  100 B and the first land pillars  251  of the package substrate  200 A may be electrically and physically connected with each other using the solder bumps SB. 
     Referring to  FIG.  4 D , with further reference to  FIGS.  2 A and  3 B , the first bump pillars  151  of the semiconductor device  100 B and the second land pillars  252  of the package substrate  200 B may be electrically and physically connected with each other using the solder bumps SB, and the second bump pillars  152  of the semiconductor device  100 B and the first land pillars  251  of the package substrate  200 B may be electrically and physically connected with each other using the solder bumps SB. 
     As shown in  FIGS.  4 A to  4 D , each of the I/O pads  120  and each of the bump lands  220  may be vertically aligned with each other. For example, the I/O pad  120 , the barrier layer  140 , the first bump pillar  151  or the second bump pillar  152 , the solder bump SB, the first land pillar  251  or the second land pillars  252 , and the bump lands  220 , corresponding each other may be vertically aligned. Each of the first bump pillars  151  and each of the first land pillars  251  may be exclusively arranged not to be vertically aligned each other. Each of the second bump pillars  152  and each of the second land pillars  252  may also be exclusively arranged not to be vertically aligned. Each of the first bump pillars  151  and each of the second land pillars  252  may be vertically aligned. Each of the second bump pillars  152  and each of the first land pillars  251  may be vertically aligned. 
       FIGS.  5 A to  5 D  are longitudinal cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, and  FIG.  5 E to  5 K  are cross-sectional views illustrating methods manufacturing semiconductor packages according to embodiments of the present disclosure using the semiconductor device. Referring to  FIG.  5 A , a method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a passivation layer  130  on a semiconductor substrate  110  having I/O pads  120 . The semiconductor substrate  110  may include a silicon wafer. The semiconductor substrate  110  may include internal circuits and a plurality of insulating layers. The internal circuits may include a plurality of transistors, a plurality of metal vias, multi-layered metal interconnections, and the I/O pads  120 . The I/O pads  120  may include a metal such as aluminum (Al). Forming the passivation layer  130  may include performing a coating process or a deposition process, and a photolithography process to form the passivation layer  130  on the semiconductor substrate  110  such that the I/O pads  120  are partially exposed. That is, the surfaces of the I/O pads  120  may be partially exposed without being covered with the passivation layer  130 . The passivation layer  130  may include a polyimide-based insulating material. For example, the passivation layer  130  may include polyimide isoindro quindzoline (PIQ). In an embodiment, the passivation layer  130  may include an inorganic material such as silicon nitride (SiN) or silicon oxide (SiO 2 ). 
     Referring to  FIG.  5 B , the method may further include performing a deposition process such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form a barrier layer  140 . The barrier layer  140  may be conformally formed on a surface of the passivation layer  130  and an exposed surface of the I/O pads  120 . The barrier layer  140  may include a seed layer. The barrier layer  140  may include a lower layer including titanium and an upper layer including copper. For example, the barrier layer  140  may include a Ti/Cu stack layer. 
     Referring to  FIG.  5 C , the method may further include forming a first mask pattern M 1 . The first mask pattern M 1  may include first openings O 1  vertically aligned with some of the I/O pads  120 . The first openings O 1  may selectively expose some of the I/O pads  120 . For example, the first openings O 1  may alternately expose the I/O pads  120  to skip every other one. The barrier layer  140  vertically aligned with some of the I/O pads  120  may be exposed through the first openings O 1 . The first mask pattern M 1  may include a polymeric organic material such as a photoresist. In an embodiment, the first openings O 1  may alternately expose the I/O pads  120  by serially skipping every other I/O pad  120  to expose through the opening O 1  as shown, for example, in  FIG.  5 C . 
     Referring to  FIG.  5 D , the method may further include forming first bump pillars  151  in the first openings O 1 . The first bump pillars  151  may be formed by performing a first plating process. The first bump pillars  151  may include a metal such as copper (Cu). Thereafter, the semiconductor device  100 A illustrated in  FIG.  1 A  may be manufactured by removing the first mask pattern M 1 . 
     Referring to  FIG.  5 E , the method may further include forming a second mask pattern M 2 . The second mask pattern M 2  may be further formed on the first mask pattern M 1 . Otherwise, the second mask pattern M 2  may be formed after the first mask pattern M 1  is removed. The second mask pattern M 2  may be formed to be thicker than the first mask pattern M 1 . The second mask pattern M 2  may include second openings O 2  vertically aligned with the first bump pillars  151 , and the I/O pads  120  being not aligned with the first openings O 1 . The second openings O 2  may expose surfaces of the first bump pillars  151  and surfaces of the barrier layer  140 . 
     Referring to  FIG.  5 F , the method may further include forming a solder material SM in the second openings O 2 . The solder material SM may be directly formed on exposed surfaces of the barrier layer  140  and the first bump pillars  151 . The solder material SM may include tin (Sn). 
     Referring to  FIG.  5 G , the method may further include removing the second mask pattern M 2 . The second mask pattern M 2  may be removed by performing a strip process using chemicals including sulfuric acid or hydrogen peroxide or an ashing process using oxygen plasma. The barrier layer  140  that is not vertically aligned with the I/O pads  120  may be exposed by removing the second mask pattern M 2 . 
     Referring to  FIG.  5 H , the method may further include performing an etching process or a cleaning process to remove the exposed barrier layers  140 . The barrier layers  140  under the first bump pillars  151  and the solder material SM may remain between the I/O pads  120  and the first bump pillars  151  and between the I/O pads  120  and the solder material SM. 
     Referring to  FIG.  5 I , the method may further include performing a reflow process to transform the solder material SM into hemispherical shaped solder bumps SB. The reflow process may include heating the solder material SM to a suitable temperature between about from 120° C. to 250° C. 
     Referring to  FIG.  5 J , the method may further include heating and pressing the semiconductor device  100 A on the package substrate  200 A shown in  FIG.  3 A . The semiconductor package  300 A shown in  FIG.  4 A  may be manufactured. 
     Referring to  FIG.  5 K , the method may include heating and pressing the semiconductor device  100 A on the package substrate  200 B shown in  FIG.  3 B . The semiconductor package  300 B shown in  FIG.  4 B  may be manufactured. 
       FIG.  6 A  is a longitudinal cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, and  FIG.  6 B to  6 F  are cross-sectional views illustrating a method of manufacturing semiconductor packages according to embodiments of the present disclosure using the semiconductor device. Referring to  FIG.  6 A , a method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include performing the processes described with reference to  FIG.  5 A to  5 E , and performing a second plating process to form first bump pillars  151  and second bump pillars  152  in the second openings O 2 . The first bump pillars  151  may be vertically thicker than the second bump pillars  152 . The first bump pillars  151  may have a first height h 1 , and the second bump pillars  152  may have a second height h 2 . The first height h 1  may be greater than the second height h 2 . 
     Referring to  FIG.  6 B , the method may further include forming a third mask pattern M 3 . The third mask pattern M 3  may be further formed on the second mask pattern M 2 . Otherwise, the third mask pattern M 3  may be formed after the second mask pattern M 2  is removed. The third mask pattern M 3  may have third openings O 3  exposing surfaces of the first bump pillars  151  and the second bump pillars  152 . 
     Referring to  FIG.  6 C , the method may further include forming a solder material SM in the third openings O 3 . The solder material SM may be directly formed on surfaces of the first bump pillars  151  and the second bump pillars  152  exposed in the third openings O 3 . 
     Referring to  FIG.  6 D , the method may further include performing the processes described with reference to  FIG.  5 G to  5 I  to remove the third mask pattern M 3 , performing an etching process or a cleaning process to remove the exposed barrier layers  140 , and performing a reflow process to transform the solder material SM into hemispherical shaped solder bumps SM. 
     Referring to  FIG.  6 E , the method may further include heating and pressing the semiconductor device  100 B on the package substrate  200 A shown in  FIG.  3 A . The semiconductor package  300 C shown in  FIG.  4 C  may be manufactured. 
     Referring to  FIG.  6 F , the method may include heating and pressing the semiconductor device  100 B on the package substrate  200 B shown in  FIG.  3 B . The semiconductor package  300 D shown in  FIG.  4 D  may be manufactured. 
     According to various embodiments of the present disclosure, the distance between solder bumps can be increased, and the spacing and pitch of I/O pads of the semiconductor device, the spacing and pitch of bump pillars of the package substrate, and the spacing and pitch of bump lands of the package substrate can be reduced. In some embodiments, the spacing and pitch of the land pillars of the substrate may be reduced. Accordingly, in some embodiments, high integration and miniaturization of the semiconductor device, the package substrate, and the semiconductor package can be improved. 
     Although the present disclosure has been specifically described according to the above-described preferred embodiments, it should be noted that the above-described embodiments are for the purpose of explanation and not for the limitation thereof. In addition, it will be appreciated by person having ordinary skill in the art that various embodiments are possible within the scope of the present disclosure.