Patent Publication Number: US-4318086-A

Title: (b+a)-Bit-A/D convertor with b-bit auxiliary A/D convertor

Description:
BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     The invention relates to an analog-to-digital converter (A/D converter) for converting an analog signal into a digital signal consisting of a sequence of code words each comprising a plurality of bits. 
     (2) Description of the Prior Art 
     A/D converters are used in widely divergent technical fields. Embodiments of A/D converters are described in reference 1, (see paragraph D). In general, they convert a time-continuous signal into a time and amplitude-discrete signal. For this conversion an analog signal is sampled with a certain sampling frequency. Each of the samples thus obtained is encoded within a certain period of time, the so-called conversion time. Encoding of a signal sample means that a code word or number is generated comprising a number of symbols or bits. In order that the required number of bits does not exceed a predetermined number, the sample is first quantized, that is to say that the value of this sample is made equal to an integral number of times a pre-determined elementary voltage or current. This elementary voltage or current is denoted quantization step size. The code word now indicates how many times the quantization step size is included in the quantized sample. The number of bits of each of these code words is determined by the distance between the highest positive and the lowest negative value of the analog signal to be coded, and by the desired quantization step size. In its turn this quantization step size determines the quantizing noise introduced by the quantizing process. As known, this quantizing noise is directly proportional to the quantization step size and will have to be below a predetermined threshold. The height of this threshold is determined when the type of signal to be coded is known. For example, when coding speech signals, a greater amount of quantizing noise will be tolerated than when coding music signals which must be of Hi-Fi quality after decoding. 
     In practice, the quantizing noise is not used as an absolute quantity but it is considered relatively with respect to the signal, more particularly the ratio between the signal and the quantizing noise is considered in practice and this ratio is expressed in decibels (dB). Hereinafter this ratio will be denoted by SNR and, as known, is approximately equal to 
     
         SNR=(6n-2)dB                                               (1) 
    
     for a sinusoidal signal. Herein n represents the number of bits of each of the code words. 
     It follows from (1) that when a higher value of SNR is desired the number of bits n of each of the code words must be increased. As more quantizing noise can be allowed for coding a speech signal than for coding a music signal, twelve-bit code words are usually taken in practice for coding a speech signal but for the coding of a music signal at least 14-bit code words are required. 
     The more bits a code word must have, the greater the accuracy and stability must be of the components with which the A/D converter is implemented and, consequently, the higher its price. This price is a barrier for the use of these A/D converters in, for example, audio equipment such as, for example, magnetophons for the consumer market. 
     Hereinafter a code word comprising, for example, d bits will be denoted &#34;d-bit code word&#34;. Similarly, an A/D converter arranged for converting an analog signal into d-bit code words will be denoted &#34;d-bit A/D converter&#34;. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide an A/D converter which can be realised in an economically justified manner. 
     According to the invention, the A/D converter for converting an analog signal whose frequency spectrum is located in a certain signal frequency band into a sequence of (b+a)-bit code words comprises: 
     a. an input for receiving said analog signal; 
     b. integrating and amplitude-limiting means for producing an auxiliary signal which is an amplitude-limited version of the integrated signal applied to these means; 
     c. means for coupling the input of the integrating and amplitude-limiting means to said analog signal input; 
     d. an auxiliary analog-to-digital converter to which said auxiliary signal is applied and which is arranged for converting this auxiliary signal into a sequence of code words each comprising b bits; sampling pulses occurring with a sampling frequency greater than the Nyquist sampling frequency of the analog signal being applied to this auxiliary analog-to-digital converter; 
     e. a cascade arrangement of a digital difference network and of digital amplitude-restoring means, connected to the output of the auxiliary analog-to-digital converter; 
     f. a digital filter coupled to the output of the cascade arrangement and arranged for suppressing the components located outside the signal frequency band and for producing said (b+a)-bit code words. 
     By means of the analog-to-digital converter, according to the invention, a (b+a)-bit A/D conversion is realized, use being made for this purpose of a b-bit auxiliary A/D converter which is, in general, cheaper and simpler. In order to obtain yet a signal-to quantizing noise ratio associated with a(b+a)-bit A/D converter the analog input signal is preprocessed before it is applied to the A/D converter. Thereafter the output signal of the auxiliary A/D converter is subjected to a post-processing operation. This post-processing operation shifts the quantizing noise signal introduced by the A/D converter to such a frequency band that it can be suppressed by the digital filter. The pre-processing operation has for its purpose to enable the above-mentioned suppression of the noise signal without affecting the desired signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows schematically the construction of an A/D converter; 
     FIG. 2 shows schematically the power spectrum of an analog signal; 
     FIG. 3 shows one period of the power spectrum of a time-discrete and amplitude-continuous signal; 
     FIG. 4 shows one period of the power spectrum of a time and amplitude-discrete signal and the noise signal power spectrum introduced by the fact that the amplitude is discrete; 
     FIG. 5 shows one period of the output signal of the A/D converter of FIG. 1 if the analog signal shown in FIG. 2 is applied to it and the sampling frequency f s  is equal to 2Nf x , where N=2; 
     FIG. 6 shows the symbol of a decimator; 
     FIG. 7 shows one period of the power spectrum of the output signal of the decimator shown in FIG. 6 if a signal having the power spectrum shown in FIG. 5 is applied to it; 
     FIG. 8 shows schematically the general structure of the analog-to-digital converter according to the invention; 
     FIG. 9 shows the variation of the function sin 2  (2fT/2) occurring in expression (25); 
     FIG. 10 shows the relation, defined in expression (32) between the number of additional bits a and the increase factor N of the sampling frequency; 
     FIG. 11 shows schematically a modification of the analog-to-digital converter shown in FIG. 8; 
     FIG. 12 shows, by means of a graph, the variation of a periodical amplitude-limiting function which is non-linear in each period; 
     FIG. 13 shows by means of a graph the variation of a periodical amplitude-limiting function which is linear in each period; 
     FIG. 14 shows a simplification of the A/D converter shown in FIG. 11; 
     FIG. 15 shows in greater detail an embodiment of the cascade arrangement formed by the integrating network and the amplitude-limiting device with linear periodical limiting function; 
     FIG. 16 shows a triangular limiting function for use in the A/D converter shown in FIG. 8; 
     FIG. 17 shows the preferred embodiment of the A/D converter; 
     FIG. 18 shows in detail an embodiment of the pre-processing device for use in an A/D converter shown in FIG. 17; 
     FIG. 19 shows a nested version of the A/D converter shown in FIG. 17. 
     REFERENCES 
     1. Special Issue on Analog/Digital Conversion; IEEE Transactions on Circuits and Systems, Vol. CAS-25, No. 7, July 1978. 
     2. Digital Signal Processing; A. V. Oppenheim, R. W. Schafer; Prentice-Hall 1975; pages 413-418. 
     3. Dutch patent Application 7703633. 
     4. Optimum FIR Digital Filter Implementations for Decimation, Interpolation, and Narrow Band Filtering; L. R. Rabiner, R. E. Crochiere; IEEE Transactions on Acoustics, Speech and Signal Processing, Vol. ASSP-23, October 1975, pages 444-456. 
     5. Further Considerations in the Design of Decimators and Interpolators; R. E. Crochiere, L. R. Rabiner; IEEE Transactions on Acoustics, Speech, and Signal Processing Vol. ASSP-24, August 1976, pages 296-311. 
     6. Computation Rate and Storage Estimation in Multirate Digital Filtering with Half-Band Filters; M. G. Bellanger; IEEE Transactions on Acoustics, Speech and Signal Processing, Vol. ASSP-25, August 1977, pages 344-346. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     (1) Introduction 
     (1.1) The power spectrum of the digital signal 
     In the preceding it was stated that to enable the conversion of an analog signal into a digital signal, this analog signal must first be sampled; that the signal samples thus obtained must be quantized and, finally, the quantized signal samples must be expressed in a number (preferably represented in base-2-code). As shown schematically in FIG. 1, an A/D converter generally comprises for this purpose a sampling device 1, a quantizing device 2 and a coding device 3. Sample pulses occurring with a pre-determined frequency f s , the so-called sampling frequency, are applied to the sampling device 1. These sampling pulses are produced by clock pulse generator 4. The coding device 3 now supplies the above-mentioned digital numbers and these numbers all comprise the same number of bits. Assuming that the A/D converter shown in FIG. 1 is a b-bit A/D converter, each of the numbers produced by the coding device 3 comprises b bits having the values c 0 , c 1 , c 2 , c 3  . . . c b-1 , respectively, c i  being equal to 0 or 1. 
     It is now assumed that the input signal of this A/D converter may vary between the quantities -V max  and +V max , then the above digital number represents a voltage or current having the value: ##EQU1## The quantity 2 -b+1  V max  is called the quantizing step size and will be denoted by q, so that it holds that ##EQU2## 
     The influence of each of the processes &#34;sampling&#34; and &#34;quantizing&#34; on the power spectrum of the original analog signal will be described in this introduction. The starting point is a real analog signal which is applied to the b-bit A/D converter shown schematically in FIG. 1. This analog signal will be denoted by x a  (t), it being assumed that its frequency spectrum will only differ from zero at the frequency interval 0≦f≦f x . The power spectrum of this signal x a  (t) will be denoted by P x .sbsb.a (f) and is schematically shown in FIG. 2. 
     If now this signal x a  (t) is applied to the sampling device 1, which takes samples from x a  (t) at a sampling frequency f s  =2f x , a set of samples which will be denoted by x(n) and for which it holds that: ##EQU3## is produced at the output of the sampling device. The power spectrum of this time-discrete signal will be denoted by P x  (f). FIG. 3 shows a period of this power spectrum. 
     Thereafter, the signal samples x(n) are applied to the quantizing device 2 which performs a non-linear quantizing operation Q[.] on these signal samples x a  (nT), which results in quantized signal samples which will be denoted by x(n) and for which it holds that: 
     
         x(n)=Q[x.sub.a (nT)]=x(n)V.sub.max                         (5) 
    
     In (5) x(n) represents a b-bit number. In response to the quantized signal samples x(n) which are applied to the coding device, the coding device produces the above-mentioned b-bit numbers x(n). 
     If the amplitude of x a  (t) is limited, the quantizing operation can also be written in a different manner, it being possible to express each quantized signal sample x(n) as follows: 
     
         x(n)=x.sub.a (nT)+e(n)                                     (6) 
    
     In this expression e(n) represents the quantizing error it holding for the error that: 
     
         -q/2&lt;e(n)&lt;+q/2                                             (7) 
    
     These quantizing errors e(n) may be considered as samples of a noise signal having a power density spectrum distributed uniformly over the frequency interval 0≦f≦2f x . Consequently, this noise signal may be considered as &#34;white noise&#34; (see reference 2). If now the total noise power of this noise signal is denoted by P e  and its power spectrum by P e  (f), then it holds that: 
     
         P.sub.e =q.sup.2 /12                                       (8) 
    
     
         P.sub.e (f)=q.sup.2 T/12                                   (9) 
    
     FIG. 4 shows schematically the power spectrum of x(n). More particularly, FIG. 4 shows that this power spectrum is formed by the sum of the power spectrum of x(n) and the power spectrum of e(n). If now the total power of x(n) is represented by P x , then the signal-to-noise ratio for the signal x(n) is equal to: 
     
         P.sub.x /P.sub.e =12P.sub.x /q.sup.2                       (10) 
    
     From (10) it follows that the signal-to-noise ratio can only be increased by choosing a lower value of q. The value of V max  remaining equal, a smaller value of q requires a larger number of bits for the numbers x(n). Assuming that the quantizing step size is reduced to a value q 1  =q/2 a  then the A/D converter will have to produce (b+a)-bit numbers x(n). The digital output signal of this (b+a)-bit A/D converter will now have a signal-to-noise ratio which is equal to: 
     
         12P.sub.x 2.sup.2a /q.sup.2                                (11) 
    
     which is 2 2a  times as high as the signal-to-noise ratio expressed in (10). 
     (1.2) The sampling frequency and the signal-to-noise ratio 
     Paragraph (1.1) indicates that the samples e(n) will be considered as the samples of a noise signal having a noise power which is uniformly distributed over the frequency interval 0≦f≦f s . For the b-bit A/D converter described in paragraph E(1.1) it was assumed that f s  =2f x , so that a noise signal having a noise power equal to q 2  /24 is present in both the frequency interval 0≦f≦f x  and the frequency interval f x  ≦f≦2f x . 
     By choosing, in this b-bit A/D converter the sampling frequency f s  higher than 2f x , for example N-times higher so that f s  =2Nf x , the noise power is distributed over a frequency interval which is N times greater. As the total noise power remains equal to q 2  /12, a noise power equal to q 2  /(24N) is now present in both the frequency interval 0≦f≦f x  and the interval (2N-1)f x  ≦f≦2Nf x . FIG. 5 shows schematically the power spectrum of the digital output signal of this A/D converter for N=2. 
     The frequency components located in the frequency interval f x  ≦f≦(2N-1)f x  can now be suppressed by means of a digital low-pass filter. Thereafter, the sampling frequency can be reduced by a factor of N, so that the components of the digital signal are produced again with the sampling frequency 2f x . 
     Reducing the sampling frequency by a factor of N can be achieved by means of an arrangement which passes only each Nth number produced by the digital low-pass filter and suppresses all other numbers. Such an arrangement is described in reference 3, where it is called SRR-element. The cascade arrangement of said digital low-pass filter and the SSR-element is sometimes called decimator and will be indicated by means of the symbol shown in FIG. 6. In this symbol, N represents the reduction factor. Embodiments of such a decimator are described in, for example, the references 4, 5 and 6. 
     If now a signal y(n) is applied to the decimator with the power spectrum shown in FIG. 5, this decimator produces an output signal y(n) having a power spectrum P y  (f) whose shape is schematically shown in FIG. 7. 
     The total noise power in the frequency interval 0≦f≦2f x  is now equal to P e ,y where: 
     
         P.sub.e,y =q.sup.2 /(12N)                                  (12) 
    
     and the signal-to-noise ratio of the signal y(n) is equal to: 
     
         P.sub.x /P.sub.e,y =P.sub.x /(q.sup.2 /12N)=12NP.sub.x /q.sup.2 (13) 
    
     Now this expression can be made equal to expression (11) namely by choosing N equal to 2 2a , so that it holds, for example, for a=4 that N=256. To achieve a considerable improvement in the signal-to-noise ratio a very high sampling frequency will generally be required. 
     The reason that the increase in the sampling frequency actually results in only little improvement in the signal-to-noise ratio is that it only distributes the noise power over a larger frequency interval. An improved distribution of the noise power would result in a further improvement of the signal-to-noise ratio but then this distribution must be such that there is less noise power in those frequency intervals which are occupied by the desired signal and more in the other frequency intervals. This means for the signal whose power spectrum is shown in FIG. 5 that there must be less noise power in the frequency intervals 0≦f≦f x  and 3f x  ≦f≦4f x  and more noise power in the frequency interval f x  ≦f≦3f x . In that case the noise signal can no longer be considered as white noise and consecutive noise signal samples e(n) will be correlated. 
     A noise power having the properties meant above is obtained by means of a delta modulator and also by means of a differential pulse code modulator. Such A/D converters have a feedback loop which ensures that the consecutive noise signal samples are highly correlated, causing the major portion of the noise power to become located at frequencies around f s  /2. The drawback of a feedback circuit is, inter alia, the fact that an accurate D/A converter is required in the loop (see, for example, reference 1, pages 448-460). 
     (2). The arrangement according to the invention, general structure 
     This paragraph gives a description of the general structure, shown in FIG. 8, of an arrangement for converting an analog signal x a  (t) into a digital signal x(n) which seems to have been generated by a (b+a)-bit A/D converter, while this arrangement utilises to that end a b-bit A/D converter which is not included in a feedback loop. 
     The arrangement shown in FIG. 8 comprises a b-bit A/D converter 5 of a conventional construction. Sampling pulses are supplied to this A/D converter with a sampling frequency f s  =2Nf x . This A/D converter comprises an analog signal input 6 and a digital signal output 7. If now, as shown in the Figure, an analog signal z a  (t) is applied to this b-bit A/D converter via the input 6, then there is produced at the output thereof a digital signal formed by the b-bit numbers z(n) occurring with a frequency 2Nf x . 
     The input 6 of this A/D converter 5 is connected to the output of a pre-processing arrangement 8, to which the analog signal x a  (t), whose power spectrum is shown in FIG. 2, is applied. The output 7 of the A/D converter 5 is connected to the input of a post-processing arrangement 9, which has its output connected to the input of a decimator 10 having a reduction factor of N. The output of this decimator is coupled to the output 11 of the arrangement. The desired (b+a)-bit numbers x(n) are now produced at this output 11 with a sampling frequency 2f x . 
     The pre-processing arrangement 8 comprises an integrating network 12 and an amplitude-limiting arrangement 13 having a predetermined fixed limiting function f{.}. The integrating network 12 produces in response to the signal x a  (t) applied thereto a signal y a  (t) for which it holds that: ##EQU4## In (14) K denotes any arbitrary constant. The signal y a  (t) is applied to the limiting arrangement 13, which produces the output signal z a  (t) for which it holds that: 
     
         z.sub.a (t)=f{y.sub.a (t)}                                 (15) 
    
     This signal z a  (t) is now applied to the b-bit A/D converter 5 which produces the numbers z(n). In accordance with (5) and (6) it now holds that: 
     
         z(n)V.sub.max =z.sub.a (nT)+e(n); T=1/(2Nf.sub.x)          (16) 
    
     The post-processing arrangement 9 comprises an amplitude-restoring arrangement 14 and a difference network 15. The restoring arrangement 14 produces, in response to the numbers z(n) applied thereto, the numbers z(n) for which it holds that: ##EQU5## In (17) g{.} denotes the restoration function. For an accurate amplitude restoration g{.} must be the inverse function of the function f{.}. This means that in general it must hold for a variable α that: ##EQU6## From (15) and (17) it now follows that: ##EQU7## This digital signal z(n) is now applied to the difference network 15 which is assumed to be of the first order. This difference network 15 produces the output signal z(n) for which it holds that: ##EQU8## so that ##EQU9## with (14) it follows herefrom that: ##EQU10## Since K is any random constant it can be chosen equal to 1/T, so that the first term in (22) becomes approximately equal to x a  (nT-T/2) and (22) thus changes into: ##EQU11## 
     Each of the numbers z(n) comprise, which also applies to the numbers z(n), b bits and are applied to the decimator 10 producing the numbers z(n). As customary, the numbers z(n) are multiplied in this decimator 10 by filter coefficients which also comprise a predetermined number of bits, for example a 1  =a+a 0  bits. The numbers x(n) produced by this decimator now contain b+a 1  =b+a+a 0  bits of which only b+a bits are relevant. Only these b+a bits of each of the numbers x(n) are applied to the output 11 of the arrangement. Discarding the a 0  least-significant bits of the numbers x(n) is achieved by, for example, rounding the numbers x(n) and this process is symbolically shown in FIG. 8 by the discarding arrangement 16 to which the (b+a+a 0 )-bit numbers x(n) are applied and which produce the (b+a)-bit numbers x(n). 
     That a shift of a noise power to frequencies located outside the signal band is indeed realized by means of the arrangement shown in FIG. 8 can be explained as follows. 
     If the noise signal in z(n) is represented by s(n), then it holds in accordance with (22) that: ##EQU12## If the power spectrum of r(n) is represented by P r  (f) and that of s(n) by P s  (f) then it can be derived that: ##EQU13## FIG. 9 shows the variation of the function sin 2  (2πfT/2). If P r  (f) is finite for all values of f, then it appears from FIG. 9 that the noise originally present in the signal band is suppressed. 
     If it is now assumed that the filter in the decimator performs a function corresponding with that of an ideal low-pass filter having a cut-off frequency 1/(2NT) and if the total power of the noise signal located in the signal band is represented by P e  &#39; then it holds that: ##EQU14## If it is now assumed for simplicity that the function g{.} is a linear function, then it holds that ##EQU15## wherein K is a constant. The total noise power of e(n) is expressed in (8) and the noise spectrum of e(n) is shown in (9). From this it follows that: ##EQU16## 
     By means of (28) (26) passes into: ##EQU17## 
     Now it should hold that the noise power defined in (29) is equal to the noise power produced by an A/D converter wherein a quantizing step size q.2 -a  is used, the sampling frequency being equal to 2f x , and which produces (b+a)-bit numbers. If last-mentioned noise power is represented by P e , then it holds therefore that: ##EQU18## 
     and for P e  &#39; defined in (29) it should hold that: ##EQU19## For a desired value of a the associated value of N follows from (29), (30) and (31); it namely holds that: ##EQU20## This function defined in (32) is shown for k=1 in FIG. 10. From this FIG. 10 it appears that, if, for example, a=4 than then N is to be chosen to be 9.2. 
     (3) The amplitude-limiting and restoration functions 
     In the preceeding only one special requirement was imposed on the amplitude-limiting function. This function is namely assumed to be invertable because otherwise no amplitude-restoration function can be found. That, however, not every invertable function can be utilized as an amplitude-limiting function may be apparent from the following example. Assume: 
     
         z.sub.a (t)=arc tan y.sub.a (t)                            (33) 
    
     For an accurate restoration of the amplitude it must now hold that: 
     
         z(n)V.sub.max =tan {z.sub.a (nT)+e(n)}                     (34) 
    
     It follows from (33) and (34) that if e(n)=0 it indeed holds, as intended, that: 
     
         z(n)V.sub.max =tan {arctan y.sub.a (nT)}=y.sub.a (nT). 
    
     As, however, e(n) is in general unequal to zero, this relation is seriously disturbed. 
     A very advantageous amplitude-limiting function is obtained by periodically repeating a function defined in a given interval and being a monotonously varying and invertable function in this interval, it being necessary that this interval and, consequently, also said period is suitably chosen. In what follows hereinafter this period will be indicated by R and it will be assumed that it satisfies the relation: 
     
         R=k&#39;V.sub.max                                              (35) 
    
     Herein k&#39; denotes a number which can be represented by means of a finite number of bits. A possible amplitude-limiting function is now given by: 
     
         z.sub.a (t)=F{π[y.sub.a (t)-kR]}                        (36) 
    
     so that 
     
         z.sub.a (nT)=F{ρ[y.sub.a (nT)-k.sub.n R]}              (37) 
    
     In (36) and (37) ρ represents a random number, while it must again hold that: 
     
         -V.sub.max ≦z.sub.a (t)≦+V.sub.max           (38) 
    
     This relation (38) fixes the value of R. 
     As the numbers occurring at the output of the restoration arrangement 14 must satisfy (20) it can be derived that it must hold for the amplitude-restoration function that: ##EQU21## By now assuming that: ##EQU22## (39) passes into: 
     
         z(n)=z&#39;(n)+k.sub.n k&#39; 
    
     In its generality it follows from (21) that: 
     
         z(n)=z&#39;(n)-z&#39;(n-1)+(k.sub.n -k.sub.n-1)k&#39;                  (40) 
    
     As the amplitude of the input signal x a  (t) is limited, also the amplitude of each number z(n) is limited in accordance with (23). This means that although k n  and k n-1  are each unlimited, the difference k n  -k n-1  represents a finite number. 
     Because further z(n)V max  can never exceed V max , it holds, if the period R is chosen larger than or equal to V max  that then: ##EQU23## 
     As shown in (41), k n  -k n-1  can assume one out of three possible values. This is connected with the fact that y a  (nT) can be both greater and smaller than y a  [(n-1)T]. Should, however, x a  (t) always be positive, then y a  (t) would increase monotonously. In that case k n  -k n-1  can only be 0 or +1. If it is assumed that: 
     
         0&lt;x.sub.a (t)&lt;2V.sub.max                                   (42) 
    
     and that 
     
         R≧2V.sub.max                                        (43) 
    
     it then holds that: ##EQU24## 
     In addition, the foregoing means that z(n) can be fully determined from the difference z&#39;(n)-z&#39;(n-1). If, namely ##EQU25## 
     (4) Special embodiments 
     FIG. 11 shows schematically a modification of the arrangement shown in FIG. 8, wherein the amplitude-limiting function defined by the expression (36) is now more particularly given by: 
     
         z.sub.a (t)=arc tan {y.sub.a (t)-kR}                       (47) 
    
     and wherein the amplitude-restoration function defined by the expression (39) is now given by: 
     
         z(n)=tan {z(n)}+k.sub.n k&#39;                                 (48) 
    
     It should be noted that the constant ρ present in the expressions (36) and (39) is now chosen equal to unity. For the period R a value must now be chosen such that (38) it satisfied so that it must hold that: 
     
         -tan V.sub.max ≦y.sub.a (t)-kR≦+tan V.sub.max (49) 
    
     This is satisfied by: 
     
         R=2 tan V.sub.max                                          (50) 
    
     The relation, defined in expression (47) between z a  (t) and y a  (t) is shown graphically in FIG. 12. More particularly, FIG. 12 shows the relation between z a  (t)/V max  and y a  (t) and the period R satisfies the expression (50). 
     It follows now from (40) and (48) that: 
     
         z(n)=tan z(n)-tan z(n-1)+(k.sub.n -k.sub.n-1)k&#39;            (51) 
    
     As tan V max  exceeds V max  the expression (41) holds for k n  -k n-1 . 
     The arrangement shown in FIG. 11 is implemented to a very high degree in the same manner as the arrangement shown in FIG. 8. In this FIG. 11 elements corresponding to elements shown in FIG. 8 are given the same reference numerals as in FIG. 8. 
     As shown in FIG. 11, the amplitude-limiting arrangement 13 is now formed by a cascade arrangement of two auxiliary amplitude-limiters 17 and 18. The auxiliary limiter 17 produces a residual signal y a  (t) as well as the number k n  -k n-1 . For the relation between the input signal y a  (t) and the output signal y a  (t) of this auxiliary-limitor 17 it holds that: 
     
         y.sub.a (t)=y.sub.a (t)-kR=y.sub.a (t)-2k tan V.sub.max    (52) 
    
     This signal y a  (t) is applied to the auxiliary limiter 18 which produces the signal z a  (t) for which it holds that: 
     
         z.sub.a (t)=arctan y.sub.a (t)                             (53) 
    
     The number k n  -k n-1  produced by the auxiliary limiter 17 is applied to a constant factor multiplier 19 to which also the number k&#39; is applied and which thus produces the number (k n  -k n-1 )k&#39;. 
     For calculating the numbers z(n) defined in expression (51), the amplitude-restoration arrangement indicated by the reference 14 in FIG. 8 is now formed by a cascade arrangement of an auxiliary amplitude restorer 20 and an adder 21. The difference network 15 is now arranged between the output of the auxiliary restorer 20 and the input of the adder 21. The numbers z(n) produced by the auxiliary-A/D converter 5 are now applied to the auxiliary restorer 20, which in response thereto produces the numbers z&#39;(n) for which it holds that: 
     
         z&#39;(n)=tan z(n)                                             (54) 
    
     These numbers z&#39;(n) are applied to the difference network 15, which in response thereto produces numbers which are equal to the difference z&#39;(n)-z&#39;(n-1), the latter numbers being applied to the adder 21 to which also the number (k n  -k n-1 )k&#39; is applied. The numbers z(n), defined in (51) and which are further processed in the same manner as in the arrangement shown in FIG. 8 are now produced at the output of this adder 21. 
     The limiting arrangement 13 in the embodiment shown in FIG. 11 is thus formed by means of two auxiliary limiters 17 and 18 and the restoration arrangement is thus formed by means of a cascade arrangement of an auxiliary restorer 20 and an adder 21. The auxiliary limiter 17 can indeed be implemented (see paragraph E(5)) in a simple and economic manner, but the implementation of the auxiliary limiter 18 and the auxiliary restorer 20 is not always simple and economically feasible. The auxiliary restorer 20 and the auxiliary limiter 18 can, however, be formed by a direct through-connection, namely if the limiting function defined by the expression (36) is given by: 
     
         z.sub.a (t)=ρ[y.sub.a (t)-kR]                          (55) 
    
     For ρ=1 R can be taken equal to 2V max , so that: 
     
         z.sub.a (t)=y.sub.a (t)=y.sub.a (t)-2kV.sub.max            (56) 
    
     The relation, given in (56), between z a  (t) and y a  (t) is shown graphically in FIG. 13. Since expression (56) has the same form as expression (52), FIG. 13 is more generally a graphical representation of the relation between y a  (t)/(R/2) and y a  (t)/(R/2). 
     A restoration function which must be formed as follows: 
     
         z(n)=z(n)+k.sub.n k&#39;                                       (57) 
    
     is associated in accordance with (39) with the limiting function as defined in (56), so that (see FIG. 8): ##EQU26## 
     FIG. 14 shows an embodiment based on the limiting function defined in (56) and the restoration function defined in (57). For this embodiment it is further assumed that the signal applied to the integrating network 12 is always positive, so that the expressions (44), (45) and (46), shown in paragraph E(3) are still valid. This arrangement, shown in FIG. 14, differs from the arrangement shown in FIG. 11 in the following respects: 
     1. Now the pre-processing arrangement 8 produces no numbers k n  -k n-1  and the auxiliary limiter 18 is formed by a direct through-connection; 
     2. The post-processing arrangement 9 now comprises a polarity detector 40 which has its input connected to the output of the difference network 15 and its output to an input of the adder 21 through a gate circuit 41. The number k&#39; is also applied to this gate circuit. Each time z&#39;(n)-z&#39;(n-1) is positive, the gate circuit 41 produces the number zero, so that z(n)=z&#39;(n)-z&#39;(n-1). However, each time z&#39;(n)-z&#39;(n-1) is negative, the gate circuit 41 produces the number k&#39;, so that z(n)=z&#39;(n)-z&#39;(n-1)+k&#39;. The auxiliary restorer 20 is now also formed by a direct through-connection. 
     3. To ensure that for any random input signal x a  (t) for which it holds that -V max  &lt;x a  (t)&lt;+V max , the signal applied to the integrating network 12 is always positive, the pre-processing arrangement 8 comprises an adding device 42 to which the signal x a  (t) is applied as well as a constant signal of the value V max . So a signal x a  &#39;(t) which is always positive and for which it holds that: 
     
         X.sub.a &#39;(t)=x.sub.a (t)+V.sub.max 
    
     occurs as the output of the adding device 42. 
     (5) The auxiliary limiter 17 
     The circuit shown schematically in FIG. 15 can be used for generating the signal y a  (t) and the number k n  -k n-1 . In this circuit the functions of the integrating network 12 and that of the auxiliary limiter 17 are combined. This circuit further comprises a controled current source circuit 22 to which the input signal x a  (t) is applied as the control signal. This current source circuit produces a current I o  whose magnitude is equal to the absolute value of x a  (t) and whose direction is determined by the polarity of x a  (t). The current I o  produced when x a  (t) is positive will be denoted the charging current whereas the current I o  produced when x a  (t) is negative will be denoted the discharging current. This current I o  is applied to a capacitor C arranged between a point 23 of the circuit and ground. Via an emitter follower 24 the voltage across the capacitor C is now applied to the output 25 of this circuit at which the residual signal y a  (t) thus occurs. 
     To obtain the sawtooth shaped characteristic shown in FIG. 13, the point 23 is connected, through a switch 26 which is only symbolically shown, to a voltage of +1/2R and, through a switch 27 which is also shown symbolically only to a voltage of -1/2R. In addition, this point 23 is connected to an input of a comparator 28 and to an input of a comparator 29. The voltage -1/2R is applied to a second input of comparator 28 and the voltage +1/2R is applied to a second input of comparator 29. As long as the voltage across the capacitor C is smaller than &#34;1/2R, comparator 29 produces a logic &#34;0&#34;. If, however, the voltage across the capacitor C becomes greater than +1/2R, comparator 29 produces a logic &#34;1&#34;. The logic signals produced by the comparator 29 control the switch 27 thus that at the occurrence of a logic &#34;0&#34; this switch is in the open condition (position shown in the drawing), this switch being closed at the occurrence of a logic &#34;1&#34;. When switch 27 closes the point 23 is connected to a voltage -1/2R causing the capacitor C to discharge to this voltage -1/2R. As long as the voltage across the capacitor C is greater than -1/2R, comparator 28 produces a logic &#34;0&#34;. If, however, the voltage across the capacitor C becomes smaller than -1/2R comparator 28 produces a logic &#34;1&#34;. The logic signals produced by comparator 28 control switch 26 thus that at the occurrence of a logic &#34;0&#34; this switch is in the opened condition (position shown in the drawing), the switch being closed at the occurrence of a logic &#34;1&#34;. When switch 26 closes, the point 23 is connected to a voltage +1/2R causing the capacitor C to be charged to this voltage +1/2R. 
     In addition, the output of comparator 29 is connected to the adding input 31 of an up/down-counter 30. Each time this comparator 29 supplies a logic &#34;1&#34; the counting position of this counter 30 is increased by one unit. The output of comparator 28 is further connected to the subtracting input 32 of counter 30. Each time comparator 28 supplies a logic &#34;1&#34; the counting position of counter 30 is decreased by one unit. In addition, this counter 30 comprises an output 33 and a resetting input 34. This resetting input 34 is supplied with the sampling pulses which are also applied to the auxiliary A/D converter 5, so that at the instants nT at which the A/D converter takes a sample of z a  (t) this counter 30 is reset to the zero position. Just prior to this resetting action of this counter 30 the counting position is applied to the multiplier 19 shown in FIG. 11. All this is shown schematically in FIG. 15 by means of the switch 35, which is connected to the output 33 of the counter 30 and which is also controled by the sampling pulses. The desired number k n  -k n-1  is obtained in this manner at the output of this switch 35. 
     (6) The preferred embodiment 
     In the arrangements shown in the FIGS. 11 and 14 the limiting device 17 can be implemented in the manner shown in FIG. 15. However, this circuit shown in FIG. 15 has the drawback that the capacitor C must be discharged and charged, respectively, in a very short period of time each time the voltage +1/2R or the voltage -1/2R has been reached. It is often simpler to realize a continuous limiting function instead of the discontinuous limiting function shown in FIG. 13. An example of a continuous limiting function is shown graphically in FIG. 16. As this Figure shows, the period of this continuous limiting function is now equal to 4V max  and a value of y a  (t) is no longer unambiguously determined at a certain value of y a  (t) within a certain period. This ambiguity can be solved in the manner shown in FIG. 17. 
     The preferred embodiment of the arrangement according to the invention, shown in FIG. 17, corresponds largely to the arrangement shown in FIG. 14 but differs therefrom in the following respects. 
     1. A limiting function, whose variation is shown in FIG. 16 by means of a graph is now associated with the limiting device 17. 
     2. The output of this limiting device 17 is now also connected to the input of a differentiating network 43. The output of the network 43 is connected to the input of a quantizing device 44. The quantizing device 44 is controled by the sampling pulses occurring with the frequency f s  =2Nf x  and it produces at each sampling instant either the number +1, or the number -1, depending on the fact whether the slope of the output signal of the limiting device is positive or negative at this sampling instant. The numbers thus produced are applied to a multiplier 46 through a delay device 45. The time delay of the delay device 45 is equal to the time the auxiliary A/D converter 5 requires for converting a sample z a  (nT) of z a  (t) into a number z(n). 
     3. The above-mentioned multiplier 46 is arranged between the output of the resistor 20 and the difference network 15. 
     As the absolute value of the slope of the limiting function, shown graphically in FIG. 16, is equal to unity, the limiting device 18 and the restoring device 20 can each again be constituted by a through-connection. 
     FIG. 18 shows in greater detail an embodiment of a pre-processing arrangement as preferably used in the arrangement shown in FIG. 17 and by means of which the limiting function which is shown in the graph of FIG. 16 is realized. This pre-processing arrangement comprises a controled first current source circuit in the form of a npn-transistor 47 whose base, which functions as the control input, is coupled to the input to which the signal x a  (t) is applied, of the pre-processing arrangement through a coupling capacitor 48. This base is also connected to ground potential through a resistor 49 and a Zener diode 50. The junction of the Zener diode 50 and the resistor 49 is connected to the positive terminal of a d.c. supply source through a series arrangement of resistors 51 and 52. The emitter of transistor 47 is also connected to ground potential, through a transistor 53. This first current source circuit produces an output current I o  which is applied to a differential amplifier 54 as the supply current. 
     The differential amplifier 54 is formed by two npn-transistors 55 and 56 whose emitters are interconnected and connected to the collector of transistor 47. The base of transistor 56 is further connected to the common junction of the two resistors 51 and 52. The output signal of a Schmitt trigger circuit 57 is applied to the base of transistor 56. The collector of transistor 55 is connected to the input of a current-controlled second current source circuit 58 which has its output connected to the collector of transistor 56. This second current source circuit 58 is implemented as a so-called current mirror circuit and is formed more particularly in known manner, which manner is shown in the Figures, by two pnp- transistors 59 and 60 and a transistor 61, which is connected as a diode. The collector and the base of the transistors 60 and 59, respectively, are interconnected and connected to the collector of the transistor 55. The emitters of transistors 60 and 61 are connected to the positive terminal of the d.c. power supply. The output of this current mirror circuit 58 is formed by the collector of transistor 59, this collector being connected to the collector of transistor 56. 
     The pre-processing arrangement shown in FIG. 18 also comprises an integration capacitor C connected between a point 62 and ground potential. This point 62 is also connected to the collector of transistor 56 as well as to the input of the Schmitt trigger circuit 57 and to the input of an emitter-follower 63. The residual signal y a  (t) is produced at the output of this emitter-follower. The Schmitt trigger circuit has been set so that it produces a voltage which renders transistor 56 conductive if the voltage across the capacitor C becomes higher than +V max . If, however, the voltage across the capacitor C becomes lower than -V max  then the Schmitt trigger circuit produces an output voltage which cuts off transistor 56. When transistor 56 is cutoff, transistor 55 conducts so that a current I 1 , which is applied as the charging current to the capacitor C, flows through the collector circuit of transistor 55 and, consequently, also in the collector circuit of transistor 59. When transistor 56 conducts, transistor 55 is cutoff. Now no current will flow in the collector circuits of the transistors 55 and 59. A current I 2  which is applied as the discharging current to the capacitor C, now flows in the collector circuit of transistor 56. The value of each of the currents I 1  and I 2  is determined by the value of I o . In its turn, this current I o  is proportional to the voltage at the base of transistor 47 and this voltage is equal to the input voltage x a  (t) increased by a voltage V 50  across the Zener diode 50. When resistors 49, 51 and 52 are suitably dimensioned this voltage V 50  can be made equal to V max , so that the base voltage of transistor 47 is equal to x a  &#39;(t)=x a  (t)+V max . 
     The pre-processing arrangement shown in FIG. 18 does not only produce the residual signal y z  (t) but also a signal which corresponds to the signal occurring at the output of the quantizing device 44 shown in FIG. 17. Namely, in the arrangement shown in FIG. 18 said signal occurs at the output of the Schmitt trigger circuit 57. This output is now connected to the input of the delay network 45 through an emitter-follower 64 and a sampling device 65. This sampling device 65 is again controlled by the sampling pulses. 
     (7) Final remarks 
     1. As mentioned earlier in this description a great number of other limiting functions are also applicable, besides the limiting function extensively described hereinbefore. As it was shown hereinbefore it is advantageous to demand that these limiting functions are periodical and that they are invertable within each period. In addition to the functions already described hereinbefore the function ##EQU27## is a particularly interesting example of a limiting function. Assuming this function to represent the limiting function of the limiting device 13 in the pre-processing arrangement shown in FIG. 14 then it holds for the output signal z a  (t) of this pre-processing arrangement more particularly that: ##EQU28## when π/(2T)=ω 0 , (60) being the mathematical representation of a frequency-modulated signal having carrier frequency ω 0  /2π and the sweep ω 0  /2π. This means that the pre-processing arrangement can be in the form of a FM-modulator. 
     2. As stated in expression (23) z(n) is proportional to x a  (nT-T/2). By using a sample- and hold-circuit in the pre-processing arrangement 8 it can be ensured that z(n) becomes proportional to x a  (nT). In the arrangements shown in the FIGS. 8 and 11 the said sample-and hold circuit can be connected to the input of the integrating network 12 so that x a  (t) is applied to this integrating network 12 through this circuit so that it then holds that: 
     
         z(n)V.sub.max =x.sub.a (nT)+r(n)-r(n-1) 
    
     In the arrangements shown in the FIGS. 14 and 17 the said sample and hold circuit can be included between the input of the arrangement and the input of the adding device 42, but also between the output of the adding device 42 and the input of the integrating network 12. 
     3. The value of N required to obtain (b+a)-bit code words by means of the arrangement according to the invention, provided with a b-bit auxiliary A/D converter, can be derived from FIG. 10. For example, for a =4 it holds that N must be taken equal to 9.2. This means that if x(n) must be a sixteen-bit code word that then a 12-bit auxiliary A/D converter must be used which, however, can still be relatively expensive. It is, however, possible to obtain the 16-bit code words at the same value of N by using an auxiliary A/D converter producing code words which comprise less than 12 bits. This can be achieved by means of any one of the arrangements described hereinbefore, namely by &#34;nesting&#34; such an arrangement in known manner. Nesting, for example, the arrangement shown in FIG. 17 furnishes the arrangement shown in FIG. 19. In this arrangement of FIG. 19 the analog signal x a  (t) is applied to the auxiliary A/D converter 5 through a cascade arrangement of M pre-processing arrangements 8(1), 8(2) . . . 8(M). The code words z 3  (n) produced by this auxiliary A/D converter 5 are applied through a cascade arrangement of M-post-processing arrangements 9(1), 9(2), . . . 9(M) to the decimating filter 10. In the arrangement shown in FIG. 19, M is equal to three. Each of the three pre-processing arrangements 8(1), 8(2) and 8(3) is implemented as the pre-processing arrangements shown in FIG. 17 and it is assumed that they are each provided, in accordance with final remark 2, with a sample and hold circuit. Also each of the three post-processing arrangements 9(1), 9(2) and 9(3) is implemented in the same manner as the post-processing arrangements shown in FIG. 17.