Patent Publication Number: US-7714663-B2

Title: Cascode low noise amplifier with a source coupled active inductor

Description:
FIELD OF THE INVENTION 
   The present invention is related generally to a low noise amplifier (LNA) and, more particularly, to a cascode low noise amplifier employing active inductor. 
   BACKGROUND OF THE INVENTION 
   In recent years, applications of wireless communications become popular quickly. For example, cell phones, wireless networks, and satellite phones have been widely used by people in their lives. Therefore, the needs of communications significantly increase, and the competition in international markets is intense. To provide a technology standard for the manufacturers to design their products, the Institute of Electrical and Electronics Engineers (IEEE) issues the IEEE 802.11 specification in 1997, which defines the physical layer (PHY layer) and media access control layer (MAC layer), and also defines the radio frequency (RF) band of 2.4 GHz, in which the data transfer rate is up to 2 Mbps. Then, the 802.11a specification focuses on industry, science and medicine (ISM) band of 5 GHz (5.15-5.35 GHz, 5.725-5.8252 GHz), in which the data transfer rate reaches 20-54 Mbps, and the 802.11b specification continues the existed 2.4 GHz physical layer. 
   In the development of the main chip in communication devices, there are several important factors, such as to reduce size and cost, to limit power consumption, and to improve chip performance. In the past, the transmission frequency is restricted by the low electron drift mobility of silicon elements, so the RF front-end circuits are usually implemented by GaAs transistors. In resent years, however, many new processes are developed so that the size of complementary metal-oxide-semiconductor (CMOS) elements is dramatically reduced, and the operating frequency of CMOS circuits is thereby increased. Now, CMOS processes have had the advantages of low power, high integration, and low cost, and so take an important role in the competition between integrated circuit (IC) design houses. 
     FIG. 1  is a block diagram of a RF receiver system  100 , in which the RF signal received by an antenna  102  is amplified by a low noise amplifier  104 , and mixed with an oscillating signal from a local oscillator  110  by two quadrature mixers  106  and  108 , so as to be demodulated to be two signals with a desired band. The demodulated signals are further amplified by two amplifiers  112  and  114 , filtered by two filters  116  and  118 , and converted into two analog signals by two analog-to-digital converters (ADCs)  120  and  122  respectively. In this system  100 , the low noise amplifier  104  is the dominant stage regarding the noise performance of the whole system  100 . In consideration of noise figure and linearity, the low noise amplifier  104  is the most critical element of the RF receiver system  100 . 
   Low noise amplifiers have two types, common gate configuration and cascode configuration.  FIG. 2  shows a conventional cascode low noise amplifier  200 , which comprises a pair of cascode transistors  202  and  204 . The output transistor  202  has a drain D coupled with a load inductor L 1 , and a gate coupled with a bias voltage Vb. The input transistor  204  has a gate coupled with an input inductor L 2 , and a source S coupled with a degeneration inductor L 3 . The input signal of the cascode low noise amplifier  200  is Vin, and the output signal Vout is derived from the drain D of the transistor  202 . For integrating all the elements of the low noise amplifier  200  into a single chip, on-chip spiral inductor is employed for the inductors L 1 , L 2  and L 3 . However, the on-chip spiral inductor requires greater chip area, and its quality factor Q is restricted, so being unrealistic in applications. Further, the process of manufacturing the on-chip spiral inductor is complicated, requires higher cost, and is difficult to control the inductance of the on-chip spiral inductor. There also have been proposed to use micro electro-mechanical system (MEMS) process and other materials to improve the on-chip spiral inductor, but the effect on reducing the chip area is not significant, and the cost still cannot be reduced because the number of photomasks is increased and the elements become fragile. For cost saving, it is necessary for circuit design which requires less chip area. 
   An active inductor is a circuit composed of active elements for behaving as an inductor. For example, U.S. Pat. No. 6,784,749 to Cove et al uses an active inductor in the output of a limiting amplifier to improve the bandwidth and to reduce the size of the circuit. One advantage of an active inductor is that its size can be smaller than a passive inductor, so it can be used to replace an on-chip spiral inductor to reduce the circuit size. Another advantage of an active inductor is that it is adjustable, so the programmability can be expected, for example, if an active inductor is used in a low noise amplifier, the center frequency of the amplifier may be able to be programmed. However, there are still some disadvantages when using active inductor, and the worst case is that it brings greater noise, so it can be only used in low-frequency circuits, but not appropriate to high-frequency circuits. U.S. Pat. No. 6,028,496 to Ko et al. discloses a RF active inductor having high Q value, which is implemented by Si or GaAs field effect transistor (FET), and U.S. Pat. No. 7,068,130 to Redoute et al. further improves this RF active inductor to be without any independent DC voltage source to provide bias voltage. 
   The RF communication system market continues growing, which makes people have great interest in implementing RF elements by CMOS technology. To apply a CMOS active inductor to a RF circuit is a conception with high potential for development. A RF circuit using active inductor can reduce the chip size, and has both advantages of low cost and good circuit adaptation; for example, it can control the gain by using a current source, and improve the chip performance by adapting to the operating temperature. More importantly, a RF circuit using active inductor can control the inductance to obtain expected performance, and even can obtain high Q value easily. In Carreto-Castro et al., “RF Low-Noise Amplifiers in BiCMOS Technologies”, IEEE Trans. on Circuits and Systems, pp. 974-977, vol. 46, Issue: 7, Jul. 1999, BiCMOS is proposed to implement a RF low noise amplifier using active inductor, and is expected to reduce the noise figure (NF). However, the effect is not significant according to their experiment data. This amplifier can be only used at 1 GHz, and its NF can only reach 3.4 dB. Furthermore, the cost of BiCMOS process is very high, it is doubtful that using BiCMOS active inductor could save cost, and the performance could be good enough. In Zhuo et al., “Programmable Low Noise Amplifier with Active-Inductor Load”, Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, vol. 4, pp. 365-368, 1998, a common gate CMOS low noise amplifier is proposed, which uses an active inductor to replace the original on-chip spiral inductor load, and so has a good adjustable range for 1 GHz center frequency. However, replacing the load inductor which is coupled to the output of the low noise amplifier by an active inductor causes greater noise, so it also can be only used in low frequency circuits. 
   SUMMARY OF THE INVENTION 
   One object of the present invention is to provide a cascode low noise amplifier employing active inductor. 
   Another object of the present invention is to reduce the chip size of a low noise amplifier. 
   Yet another object of the present invention is to decrease the NF of a RF low noise amplifier. 
   Still another object of the present invention is to increase the high frequency gain of a low noise amplifier with active inductors. 
   According to the present invention, a low noise amplifier comprises a pair of cascode transistors, among which is an input transistor having a source coupled with an active inductor. The low noise amplifier can be equivalent to three current sources coupled in series, and the active inductor introduces a transconductance such that the NF is reduced and the gain is increased. Since the active inductor replaces the on-chip spiral inductor, the size of the low noise amplifier is reduced. The active inductor can further provide input impedance matching for the low noise amplifier. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a block diagram of a conventional RF receiver system; 
       FIG. 2  is a conventional cascode low noise amplifier; 
       FIG. 3  is a cascode low noise amplifier according to the present invention; 
       FIG. 4  is a typical cascode active inductor; 
       FIG. 5  is a typical regulated cascode active inductor; 
       FIG. 6  is a combination of the circuits of  FIGS. 3 and 5 ; 
       FIG. 7  is a top view of a physical chip including the cascode low noise amplifier shown in  FIG. 3 ; 
       FIG. 8  is a small-signal model of a MOS transistor; 
       FIG. 9  is an equivalent circuit of the low noise amplifier shown in  FIG. 2  when taking the noise into consideration; 
       FIG. 10  is an equivalent circuit of the low noise amplifier shown in  FIG. 2  when calculating the transimpedance thereof; 
       FIG. 11  is an equivalent circuit of the low noise amplifier shown in  FIG. 2  when regarding the pair of cascode transistors as two current sources; 
       FIG. 12  is a small-signal equivalent circuit of an active inductor; 
       FIG. 13  is an equivalent circuit of the low noise amplifier shown in  FIG. 3  when regarding the pair of cascode transistors and the active inductor as three current sources coupled in series; and 
       FIG. 14  shows the case that the active inductor provides input impedance matching for the low noise amplifier of  FIG. 3 . 
   

   DETAIL DESCRIPTION OF THE INVENTION 
     FIG. 3  provides a cascode low noise amplifier  300  according to the present invention, which comprises a pair of cascode transistors  302  and  304 , and a load inductor L 1  coupled to the drain D of the output transistor  302 . The drain D of the output transistor  302  is also the output of the low noise amplifier  300  to provide the output signal Vout, and the gate of the output transistor  302  is coupled with a bias voltage Vb 1 . The input transistor  304  has a gate coupled with an input signal Vin through an input inductor L 2 , and a source S coupled with an active inductor  306 . The input impedance seen from the input Vin is Zin 1 . Preferably, all the elements  302 ,  304  and  306  are integrated into a same chip. Either one of the inductors L 1  and L 2  may be an external wire-wound inductor, an on-chip spiral inductor, or an active inductor. If the load inductor L 1  is an on-chip spiral inductor or an active inductor, it can be also integrated with the elements  302 ,  304  and  306  into the same chip, and it is the same for the input inductor L 2 . In this embodiment, the signal path is from the input Vin to the output Vout through the input inductor L 2 , the input transistor  304 , and the output transistor  302 . The active inductor  306  is not on this signal path, so it introduces less noise. If the load inductor L 1  is an active inductor, it may introduce more noise because it is coupled to the output Vout. In other embodiments, resistor, transistor or other electronic element may replace the load inductor L 1  to serve as the load element. 
     FIGS. 4 and 5  show a typical cascode active inductor  400  and a typical regulated cascode active inductor  500 , respectively. Either one of them can be regarded as an inductor L when seen from the node Vh. The cascode active inductor  400  of  FIG. 4  comprises a pair of cascode transistors  402  and  404 , the drain of the transistor  402  is coupled to the gate of a transistor  406  and a current source  408 , the gate of the transistor  402  is coupled with a bias voltage Vba, and the gate of the transistor  404 , the source of the transistor  406 , and a current source  410  are all coupled to the node Vh. The regulated cascode active inductor  500  of  FIG. 5  includes the circuit of  FIG. 4 , and the bias voltage to the gate of the transistor  402  is provided by the serially coupled transistor  502  and current source  504 . As described in Thanachayanont and Payne, “VHF CMOS integrated active inductor”, Electronics Letters, vol. 32, pp. 999-1000, May 1996, the active inductors  400  and  500  may reduce the output conductance at the node V 1 , thereby reducing the inductor loss in the circuits. 
     FIG. 6  shows a cascode low noise amplifier  600 , which is the circuit of  FIG. 3  having the regulated cascode active inductor  500  of  FIG. 5  as the active inductor  306 , and the current mirror composed of two transistors  602  and  604  as the current source  410  of  FIG. 5 . In this current mirror, the drain and gate of the bias transistor  602  are both coupled with a bias voltage Vb 2 , and the drain of the mirror transistor  604  is the output of the active inductor  306  coupled to the source S of the transistor  304 . In the active inductor  306 , the transistor  406  and the power inputs of the current sources  408  and  504  are all coupled with a bias voltage Vb 3 . Either one of the current sources  408  and  504  may employ current mirror configuration. The use of current mirror for implementing current source is well known. Because the active inductor  306  is coupled to the source of the transistor  304 , but not on the signal path, less noise will be introduced. In this embodiment, only one transistor  604  is used to serially couple to the cascode transistors  302  and  304 , so the supply voltage VDD can be small but enough to support the biases of the transistors  302 ,  304 , and  604  at normal working point, and it is therefore suitable for low voltage applications, such as cell phone, personal digital assistant (PDA), notebook computer and other handheld or portable devices with battery power supply. In other embodiments for higher voltage applications, an active inductor configured by other different circuits can be coupled between the source S of the transistor  304  and ground GND. The active inductor  306  is constructed with active elements, so can be produced by standard semiconductor process, for example CMOS process. In a preferred embodiment, the transistors  302  and  304  and the active inductor  306  are all constructed with MOS elements, so they can be integrated into a same chip by standard CMOS process. Another advantage of producing the transistors  302  and  304  and the active inductor  306  by standard CMOS process is that they can be integrated into the same chip having the other parts of the device, thereby decreasing the number of chips in the device and lowering the cost. Another advantage of the active inductor  306  is that it is adjustable, so the low noise amplifier  600  is also adjustable. In a preferred embodiment, the inductance of the active inductor  306  is about 0.5-5 nH, and the operating frequency of the low noise amplifier  600  is 5.7 GHz. If higher frequency is desired for the active inductor  306  to operate, more advanced process may be used. 
   In an embodiment as shown in  FIG. 7 , both of the inductors L 1  and L 2  are on-chip spiral inductors and are integrated into the same chip having the transistors  302  and  304  and the active inductor  306 .  FIG. 7  also shows that the active inductor  306  constructed by active elements occupies less chip area than the on-chip spiral inductors L 1  and L 2 , thereby reducing the whole size of the low noise amplifier  600 . Another advantage of using the active inductor  306  is that the manufacture of the elements of the active inductor  306  is simpler and easier, and requires lower cost therefore. 
   The principle of the low noise amplifier circuit  300  shown in  FIG. 3  is described as below.  FIG. 8  is a small-signal model of a MOS transistor, in which capacitor Cgs represents the gate-to-source parasitic capacitance, capacitor Cgd represents the gate-to-drain parasitic capacitance, gm represents the transconductance of the MOS transistor, Vgs represents the gate-to-source voltage, resistor ro represents the channel resistance, and Zin 2  represents the input impedance seen from the source S. At first, the NF of a cascode low noise amplifier is explained. As shown in  FIG. 9 , two currents Id 1  represent the noise currents of the transistors  202  and  204  in the low noise amplifier  200  of  FIG. 2 , and Zs represents the input impedance. Because there is no Miller effect on the transistor  202 , the small-signal voltage gain of the low noise amplifier  200  is 
                       Av   =       ⁢     Vout   /   Vin                   =       ⁢         1     s   ⁡     (       Cgs   ⁢           ⁢   2     +     Cm   ⁢           ⁢   2       )           Zs   +     1     s   ⁡     (       Cgs   ⁢           ⁢   2     +     Cm   ⁢           ⁢   2       )             ·     [         (       -   gm     ⁢           ⁢   2     )     ·   Zin     ⁢           ⁢   2     ]     ·     [     gm   ⁢           ⁢     1   ·     (     sL   ⁢           ⁢   1     )         ]         ,                 [     Eq   ⁢     -     ⁢   1     ]               
where gm 1  is the transconductance of the transistor  202 , gm 2  is the transconductance of the transistor  204 , Cm 2  is the Miller effect on the gate of the transistor  204 , and Cgs 2  is the gate-to-source parasitic capacitance of the transistor  204 . With reference to  FIG. 10 , the transimpedance of the noise current Id 2  is defined as
   Rm 2= V out/ Id 2=( gm 1 ·sL 1)/( gm 1 +sCgs 1),  [Eq-2] 
where Cgs 1  is the gate-to-source parasitic capacitance of the transistor  202 . Therefore, the noise current Id 2  can be converted into a Thevenin equivalent voltage  Vn 2    in a stack manner. The transimpedance of the noise current Id 1  can be defined as
   Rm 1 =V out/ Id 1=(− sCgs 1 ·sL 1)/( sCgs 1 +gm 1).  [Eq-3] 
With reference to Gonzalez, “Microwave transistor amplifiers: analysis and design”, Prentice Hall, Lee, “The Design of CMOS Radio-Frequency Integrated Circuits”, Cambridge University Press, 1998, and Sodini et al., “The effect of high fields on MOS device and circuit performance”, IEEE Transactions on Electron. Devices, Vol. ED-31, No. 10, OCT, 1984, from the equations Eq-1, Eq-2 and Eq-3, the equivalent NF at the output Vout of the cascode low noise amplifier  200  is approximately
 
                     NF   =     1   +       [           V   2     ⁢   ng   ⁢           ⁢   2     _     +       (             I   2     ⁢   d   ⁢           ⁢   2     _         g   2     ⁢   m   ⁢           ⁢   2       +             I   2     ⁢   d   ⁢           ⁢   1     _     ×     ω   2     ⁢     C   2     ⁢   gs   ⁢           ⁢   2         g   2     ⁢   m   ⁢           ⁢   2   ×     g   2     ⁢   m   ⁢           ⁢   1         )     ·         ω   2     ⁡     (       Cgs   ⁢           ⁢   2     +     Cm   ⁢           ⁢   2       )       2     ·            Zs   +     1     j   ⁢       ω   _     ⁡     (       Cgs   ⁢           ⁢   2     +     Cm   ⁢           ⁢   2       )                  2         ]     /         V   2     ⁢           ⁢   ns   ⁢           ⁢   2     _           ,     ⁢                   [     Eq   ⁢     -     ⁢   4     ]               
where ω is the angular frequency, and Vng 2  and Vns  2  are two Thevenin equivalent voltages at the gate and the source of the transistor  204 , respectively. The equation Eq-4 shows that the NF is decreased with the increasing of gm 1  and gm 2 , or the decreasing of the impedance Zs. According to Sodini et al., “The effect of high fields on MOS device and circuit performance”, IEEE Transactions on Electron. Devices, Vol. ED-31, No. 10, OCT, 1984, the saturation current of a short channel MOS transistor is
   Idd≈W·Cox ·( Vgs−Vth )· Vsat,   [Eq-5] 
where W is the channel width of the transistor, Cox is the capacitance of the gate oxide, Vth is the threshold voltage of the transistor, and Vsat is the gate-source saturation voltage. The transimpedance of the short channel MOS transistor is
   gm≡∂Idd/∂Vgs=K·W·Cox·Vsat,   [Eq-6] 
where K is a constant between 0 and 1. The equation Eq-6 shows that increasing the channel width W 2  of the transistor  204  can increase the transconductance gm 2  of the conventional low noise amplifier  200 . Although the increase of the channel width W 2  also increases the capacitance Cgs 2 , according to the equation Eq-4, the contribution of the increased Cgs 2  to the noise is compensated by the increased gm 2  in the denominator. However, the increased channel width W 2  of the transistor  204  will result in greater current Idd, and thereby consume more power. As shown in  FIG. 11 , according to the small-signal model of MOS transistor shown in  FIG. 8 , the conventional low noise amplifier  200  of  FIG. 2  can be regarded as two current sources  206  and  208  coupled in series. If the current flowing therethrough is Idd, the transconductance of the transistor  202  is
   gm 1 =∂Idd/∂Vgs 1,  [Eq-7] 
where Vgs 1  is the gate-to-source voltage of the transistor  202 , and the transconductance of the transistor  204  is
   gm 2 =∂Idd/∂Vgs 2,  [Eq-8] 
where Vgs 2  is the gate-to-source voltage of the transistor  204 .  FIG. 12  shows a small-signal equivalent circuit of an active inductor, which comprises a current source  308 , an equivalent variable inductor Leq, an equivalent series resistor Req, a parasitic parallel resistor Rp, and a parasitic parallel capacitor Cp. According to the small-signal models of  FIGS. 8 and 12 , the low noise amplifier  300  of  FIG. 3  can be regard as three current sources  310 ,  312 , and  314  coupled in series, as shown in  FIG. 13 . If the current flowing therethrough is Idd, the transconductance of the transistor  302  is
   g′m 1 =∂Idd/∂V′gs 1,  [Eq-9] 
where V″gs 1  is the gate-to-source voltage of the transistor  302 , and the transconductance of the transistor  304  is
   g′m 2 =∂Idd/∂V′gs 2,  [Eq-10] 
where V′gs 2  is the gate-to-source voltage of the transistor  304 . Because the circuit of  FIG. 13  has one transconductance gm 3  more than the circuit of  FIG. 11 , for the same current Idd, the gate-to-source voltages V′gs 1  and V′gs 2  of the transistors  302  and  304  must be smaller than the gate-to-source voltages Vgs 1  and Vgs 2  of the transistors  202  and  204 , respectively, and therefore the transconductances g′m 1  and g′m 2  of the transistor  302  and  304  are greater than the transconductances gm 1  and gm 2  of the transistor  202  and  204 , respectively. From the equation Eq-4, when the transconductances of the pair of cascode transistors of the cascode low noise amplifier increase, the NF decreases, so the low noise amplifier  300  has smaller NF. Moreover, because the transconductances g′m 1  and g′m 2  of the transistors  302  and  304  are greater, the low noise amplifier  300  has greater gain.
 
   As shown in  FIG. 14 , in addition to adaptive inductor function, the active inductor  306  also provides input impedance matching function. For achieving good matching, the active inductor  306  can be so designed to be adjustable. With reference to  FIG. 9 , when the channel width W 1  of the transistor  204  increases, the gate-to-source parasitic capacitance Cgs 2  also increases, so it must increase inductively to compensate the increased Cgs 2 . The conventional design will increase the input impedance Zs when it is desired to increase the channel width W 2  of the transistor  204 . The equation Eq-4 shows that the impedance Zs will contribute to the noise to the low noise amplifier  200 , and therefore the greater impedance Zs will result in greater noise. With reference to  FIG. 14 , to provide the same input inductively, it can be achieved by decreasing the impedance Zs and increasing the inductively of the active inductor  306 . Therefore, it saves more chip area. 
   While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.