Patent Publication Number: US-8994019-B2

Title: Semiconductor device

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. 
     In this specification, a semiconductor device generally means a device which can function by utilizing semiconductor characteristics, and an electrooptic device, a semiconductor circuit, and electronic device are all semiconductor devices. 
     2. Description of the Related Art 
     Attention has been focused on a technique for forming a transistor using a semiconductor thin film (also referred to as a thin film transistor (TFT)) formed over a substrate having an insulating surface. The transistor is applied to a wide range of electronic devices such as an integrated circuit (IC) or an image display device (display device). A silicon-based semiconductor material is widely known as a material for a semiconductor thin film applicable to a transistor. As another material, an oxide semiconductor has been attracting attention. 
     For example, a transistor whose active layer includes an amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) is disclosed (see Patent Document 1). 
     REFERENCE 
     Patent Document 
     
         
         [Patent Document] Japanese Published Patent Application No. 2006-165528 
       
    
     SUMMARY OF THE INVENTION 
     An object of an embodiment of the present invention is to provide a structure of a semiconductor device which achieves quick response and high-speed drive by improving on-state characteristics (e.g., on-state current and field-effect mobility) of a transistor, and to provide a method for manufacturing the structure, in order to achieve a semiconductor device with higher performance. 
     Another object of an embodiment of the present invention is to provide a highly reliable semiconductor device whose threshold voltage is unlikely to shift even after long-term usage. 
     It is an object of an embodiment of the present invention to achieve at least one of the above-described objects. 
     According to an embodiment of the present invention, in a transistor in which a semiconductor layer, a source and drain electrode layers, a gate insulating film, and a gate electrode are sequentially stacked, the semiconductor layer is a non-single-crystal oxide semiconductor layer containing at least indium, a Group 3 element, zinc, and oxygen. 
     The non-single-crystal oxide semiconductor layer may be a mixed layer including a crystalline region and an amorphous region. As a crystal included in the crystalline region, a c-axis aligned crystal can be used. 
     The Group 3 element functions as a stabilizer (stabilization agent). A favorable example of the Group 3 element is yttrium (Y). 
     As the stabilizer, a Group 4 element may be used in addition to the Group 3 element. As the Group 4 element, zirconium (Zr) or titanium (Ti) can be used favorably. For example, as the stabilizer, yttrium and zirconium, yttrium and titanium, cerium (Ce) and titanium, or cerium and zirconium can be used in combination. 
     As the stabilizer, a Group 13 element may be used in addition to the Group 3 element. A favorable example of the Group 13 element is gallium (Ga). For example, as the stabilizer, yttrium and gallium, or cerium and gallium can be used in combination. 
     The oxide semiconductor layer can be formed by a sputtering method using an oxide target having a composition ratio of indium: stabilizer: zinc of 1:1:1 (atomic ratio), 3:1:2 (atomic ratio), or 2:1:3 (atomic ratio), or an oxide target whose composition is in the neighborhood of that of the above-described oxide target. 
     In the case of using a Group 3 element and a Group 4 element as the stabilizer, the oxide semiconductor layer can be formed by a sputtering method using an oxide target having a composition ratio of the Group 3 element to the Group 4 element of 1:1 (atomic ratio), 2:1 (atomic ratio), or 1:2 (atomic ratio). 
     Alternatively, in the case of using a Group 3 element and a Group 13 element as the stabilizer, the oxide semiconductor layer can be formed by a sputtering method using an oxide target having a composition ratio of the Group 3 element to the Group 13 element of 1:1 (atomic ratio), 2:1 (atomic ratio), or 1:2 (atomic ratio). 
     Note that the composition ratio of the oxide semiconductor layer reflects the composition ratio of the oxide target but is not necessarily the same as the composition ratio of the oxide target. For example, even in the case where the composition ratio of the oxide target can be expressed by natural numbers in the above-described manner, the composition ratio of the oxide semiconductor layer formed using the oxide target may be expressed by non-natural numbers. 
     An embodiment of the invention disclosed in this specification is a semiconductor device including a non-single-crystal oxide semiconductor layer containing at least indium, yttrium, and zinc, a gate insulating film, a source electrode layer, a drain electrode layer, and a gate electrode layer, in which yttrium functions as a stabilization agent. 
     Another embodiment of the invention disclosed in this specification is a semiconductor device including a non-single-crystal oxide semiconductor layer containing at least indium, yttrium, zirconium, and zinc, a gate insulating film, a source electrode layer, a drain electrode layer, and a gate electrode layer, in which yttrium and zirconium function as stabilization agents. 
     Another embodiment of the invention disclosed in this specification is a semiconductor device including a non-single-crystal oxide semiconductor layer containing at least indium, yttrium, gallium, and zinc, a gate insulating film, a source electrode layer, a drain electrode layer, and a gate electrode layer, in which yttrium and gallium function as stabilization agents. 
     In the oxide semiconductor layer, a region that does not overlap with the gate electrode layer may contain a dopant. 
     In addition, in the oxide semiconductor layer, a region which overlaps with neither the source electrode layer nor the drain electrode layer may have a higher oxygen concentration than a region overlapping with the source electrode layer or the drain electrode layer. 
     Furthermore, a dopant may be introduced into the oxide semiconductor layer with the use of the gate electrode layer as a mask so that low-resistance regions containing a dopant and having a lower resistance than a channel formation region are formed in a self-aligned manner with the channel formation region interposed therebetween. The dopant is an impurity by which electrical conductivity of the oxide semiconductor layer is changed. As the method for introducing the dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used. 
     With the oxide semiconductor layer including the low-resistance regions between which the channel formation region is provided in the channel length direction, on-state characteristics (e.g., on-state current and field-effect mobility) of the transistor are increased, which enables high-speed operation and quick response. 
     In addition, heat treatment (dehydration or dehydrogenation treatment) for releasing hydrogen or moisture may be performed on the oxide semiconductor layer. In the case of using a crystalline oxide semiconductor layer as the oxide semiconductor layer, heat treatment for crystallization may be performed. 
     The dehydration or dehydrogenation treatment may be accompanied with elimination of oxygen which is a main constituent material of an oxide semiconductor, that is, a reduction of oxygen in the oxide semiconductor. An oxygen vacancy exists in a portion from which oxygen is eliminated in the oxide semiconductor film, and causes a donor level which leads to a change in electrical characteristics of a transistor. 
     Thus, it is preferable to supply oxygen to the oxide semiconductor layer after the oxide semiconductor layer is subjected to the dehydration or dehydrogenation treatment. By supply of oxygen to the oxide semiconductor layer, oxygen vacancies in the film can be reduced. 
     For example, an oxide insulating film including much (excessive) oxygen, which serves as a supply source of oxygen, may be provided in contact with the oxide semiconductor layer, whereby oxygen can be supplied from the oxide insulating film to the oxide semiconductor layer. Heat treatment may be performed in the above structure in the state where the oxide semiconductor layer having been subjected to the heat treatment for dehydration or dehydrogenation treatment is at least partly in contact with the oxide insulating film, in order to supply oxygen to the oxide semiconductor layer. 
     Further or alternatively, oxygen (which includes at least one of an oxygen radical, an oxygen atom, and an oxygen ion) may be added to the oxide semiconductor layer having been subjected to the dehydration or dehydrogenation treatment, in order to supply oxygen to the oxide semiconductor layer. Oxygen can be introduced by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like. 
     Further, it is preferable that the oxide semiconductor layer provided in the transistor be a film whose oxygen content is higher than that in the stoichiometric composition ratio of the oxide semiconductor in a crystalline state. In the film including excessive oxygen, the oxygen content is higher than that in the stoichiometric composition ratio of the oxide semiconductor. Alternatively, the oxygen content is higher than that of the oxide semiconductor in a single crystal state. In some cases, oxygen may exist between lattices of the oxide semiconductor. 
     By removing hydrogen or moisture from the oxide semiconductor to purify the oxide semiconductor so as to contain impurities as few as possible, and supplying oxygen to reduce oxygen vacancies therein, the oxide semiconductor can become an i-type (intrinsic) oxide semiconductor or a substantially i-type (intrinsic) oxide semiconductor. This enables the Fermi level (E f ) of the oxide semiconductor to be at the same level as the intrinsic Fermi level (E i ) thereof. Thus, by using the oxide semiconductor layer for a transistor, variation in the threshold voltage V th  of the transistor and a shift of the threshold voltage ΔV th  due to oxygen vacancies can be reduced. 
     An embodiment of the present invention relates to a semiconductor device including a transistor or a semiconductor device including a circuit including a transistor. For example, an embodiment of the present invention relates to a semiconductor device including a transistor whose channel formation region is formed of an oxide semiconductor or a semiconductor device including a circuit including such a transistor. For example, an embodiment of the present invention relates to an electronic device which includes, as a component, an LSI; a CPU; a power device mounted in a power circuit; a semiconductor integrated circuit including a memory, a thyristor, a converter, an image sensor, or the like; an electro-optical device typified by a liquid crystal display panel; or a light-emitting display device including a light-emitting element. 
     It is possible to provide a structure of a semiconductor device which achieves quick response and high-speed drive by improving on-state characteristics (e.g., on-state current and field-effect mobility) of a transistor, and to provide a method for manufacturing the structure, in order to achieve a semiconductor device with higher performance. 
     A highly reliable semiconductor device whose threshold voltage is unlikely to shift even after long-term usage can be provided. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the accompanying drawings: 
         FIGS. 1A to 1E  illustrate an embodiment of a semiconductor device and a method for manufacturing the semiconductor device; 
         FIGS. 2A to 2C  illustrate an embodiment of a semiconductor device; 
         FIGS. 3A to 3D  illustrate an embodiment of a semiconductor device; 
         FIGS. 4A to 4C  illustrate an embodiment of a semiconductor device; 
         FIG. 5A  is a cross-sectional view of an embodiment of a semiconductor device, 
         FIG. 5B  is a plan view thereof, and  FIG. 5C  is a circuit diagram thereof; 
         FIG. 6A  is a circuit diagram of an embodiment of a semiconductor device and  FIG. 6B  is a perspective view thereof; 
         FIG. 7A  is a plan view of an embodiment of a semiconductor device and  FIGS. 7B and 7C  are cross-sectional views thereof; 
         FIGS. 8A and 8B  are circuit diagrams of an embodiment of a semiconductor device; 
         FIG. 9  is a block diagram of an embodiment of a semiconductor device; 
         FIG. 10  is a block diagram of an embodiment of a semiconductor device; and 
         FIG. 11  is a block diagram of an embodiment of a semiconductor device. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, embodiments of the invention disclosed in this specification will be described with reference to the accompanying drawings. Note that the invention disclosed in this specification is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and the scope of the invention. Therefore, the invention disclosed in this specification is not construed as being limited to the description of the following embodiments. Note that the ordinal numbers such as “first” and “second” in this specification are used for convenience and do not denote the order of steps and the stacking order of layers. In addition, the ordinal numbers in this specification do not denote particular names which specify the present invention. 
     [Embodiment 1] 
     In this embodiment, one embodiment of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to  FIGS. 1A to 1E  and  FIGS. 2A to 2C . In this embodiment, a transistor including an oxide semiconductor film is described as an example of the semiconductor device. 
     The transistor may have a single-gate structure in which one channel formation region is formed, a double-gate structure in which two channel formation regions are formed, or a triple-gate structure in which three channel formation regions are formed. Alternatively, the transistor may have a dual-gate structure including two gate electrode layers positioned over and under a channel formation region with a gate insulating film provided therebetween. 
     A transistor  440   a  illustrated in  FIGS. 1A to 1E  is an example of a planar type transistor having a top-gate structure. 
     The transistor  440   a  includes, over a substrate  400  having an insulating surface over which an oxide insulating layer  436  is provided, an oxide semiconductor layer  403  including a channel formation region  409  and low-resistance regions  404   a  and  404   b , a source electrode layer  405   a , a drain electrode layer  405   b , a gate insulating film  402 , and a gate electrode layer  401 . An insulating film  407  is formed over the transistor  440   a.    
     In  FIGS. 1A to 1E , the source electrode layer  405   a  and the drain electrode layer  405   b  are not overlapped with the gate electrode layer  401 , over the oxide semiconductor layer  403 ; however, the source electrode layer  405   a  and the drain electrode layer  405   b  may be partly overlapped with the gate electrode layer  401  like a transistor  440   b  illustrated in  FIG. 2A . 
     The oxide semiconductor layer  403  is a non-single-crystal oxide semiconductor layer containing at least indium, a Group 3 element, zinc, and oxygen. 
     The Group 3 element functions as a stabilizer (stabilization agent). A favorable example of the Group 3 element is yttrium (Y). 
     As the stabilizer, a Group 4 element may be used in addition to the Group 3 element. As the Group 4 element, zirconium (Zr) or titanium (Ti) may be used as appropriate. For example, as the stabilizer, yttrium and zirconium, yttrium and titanium, cerium (Ce) and titanium, or cerium and zirconium can be used in combination. 
     As the stabilizer, a Group 13 element may be used in addition to the Group 3 element. As the Group 13 element, gallium (Ga) can be used favorably. For example, as the stabilizer, yttrium and gallium, or cerium and gallium can be used in combination. 
     The oxide semiconductor layer  403  can be formed by a sputtering method using an oxide target having a composition ratio of indium: stabilizer: zinc of 1:1:1 (atomic ratio), 3:1:2 (atomic ratio), or 2:1:3 (atomic ratio), or an oxide target whose composition is in the neighborhood of that of the above-described oxide target. 
     In the case of using a Group 3 element and a Group 4 element as the stabilizer, the oxide semiconductor layer  403  can be formed by a sputtering method using an oxide target having a composition ratio of the Group 3 element to the Group 4 element of 1:1 (atomic ratio), 2:1 (atomic ratio), or 1:2 (atomic ratio). 
     Alternatively, in the case of using a Group 3 element and a Group 13 element, the oxide semiconductor layer  403  can be formed by a sputtering method using an oxide target having a composition ratio of the Group 3 element to the Group 13 element of 1:1 (atomic ratio), 2:1 (atomic ratio), or 1:2 (atomic ratio). 
     Note that the composition ratio of the oxide semiconductor layer reflects the composition ratio of the oxide target but is not necessarily the same as the composition ratio of the oxide target. For example, in the case where the composition ratio of the oxide target can be expressed by natural numbers in the above-described manner, the composition ratio of the oxide semiconductor layer formed using the oxide target may be expressed by non-natural numbers. 
     The non-single-crystal oxide semiconductor layer  403  may be a mixed layer including a crystalline region and an amorphous region. As a crystal included in the crystalline region, a c-axis-aligned crystal can be used. 
     In an oxide semiconductor having crystallinity, defects in the bulk can be further reduced and when a surface flatness is improved, higher mobility can be obtained. In order to improve the surface flatness, the oxide semiconductor is preferably formed over a flat surface. Specifically, the oxide semiconductor may be formed over a surface with an average surface roughness (R a ) of less than or equal to 1 nm, preferably less than or equal to 0.3 nm, further preferably less than or equal to 0.1 nm. 
     Note that the average surface roughness (R a ) is obtained by expanding, into three dimensions, arithmetic mean surface roughness that is defined by JIS B 0601: 2001 (ISO4287:1997) so as to be able to apply it to a curved surface. R a  can be expressed as an “average value of the absolute values of deviations from a reference surface to a designated surface” and is defined by the following formula. 
     
       
         
           
             
               
                 
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     Here, the specific surface is a surface which is a target of roughness measurement, and is a quadrilateral region which is specified by four points represented by the coordinates (x 1 , y 1 , f(x 1 , y 1 )), (x 1 , y 2 , f(x 1 , y 2 )), (x 2 , y 1 , f(x 2 , y 1 )), and (x 2 , y 2 , f(x 2 , y 2 )). S 0  represents the area of a rectangle which is obtained by projecting the specific surface on the xy plane, and Z 0  represents the height of the reference surface (the average height of the specific surface). Ra can be measured using an atomic force microscope (AFM). 
     As the oxide semiconductor layer  403 , an oxide semiconductor layer including a crystal and having crystallinity (crystalline oxide semiconductor layer) can be used. The crystals in the crystalline oxide semiconductor layer may have crystal axes oriented in random directions or in a certain direction. 
     An oxide semiconductor layer including a crystal having a c-axis which is substantially perpendicular to a surface of the oxide semiconductor layer can be preferably used as the crystalline oxide semiconductor layer. 
     The oxide semiconductor layer including a crystal having a c-axis substantially perpendicular to a surface has neither single crystal structure nor amorphous structure and is an oxide semiconductor layer including a c-axis aligned crystal (also referred to as CAAC), i.e., a CAAC-OS layer. 
     CAAC-OS is an oxide semiconductor containing a crystal with c-axis alignment which has a triangular or hexagonal atomic arrangement when seen from the direction of the a-b plane, the surface, or the interface and in which metal atoms are arranged in a layered manner, or metal atoms and oxygen atoms are arranged in a layered manner along the c-axis, and the direction of the a-axis or the b-axis is varied in the a-b plane (or the surface or the interface), that is, which rotates around the c-axis. A CAAC-OS film (layer) is a thin film that includes a crystalline region crystallized along the c-axis or a crystalline portion crystallized along the c-axis and in which alignment along the a-b plane does not necessarily appear. 
     The CAAC-OS is, in a broad sense, non-single-crystal including a phase which has a triangular, hexagonal, regular triangular, or regular hexagonal atomic arrangement when seen from the direction perpendicular to the a-b plane and in which metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis direction. 
     A CAAC-OS film is not a single crystal, but this does not mean that the CAAC-OS film is composed of only an amorphous component. The CAAC-OS film is a thin film including a c-axis-aligned crystalline region and an amorphous region. Although the CAAC-OS film includes a crystalline portion, a boundary between one crystalline portion and another crystalline portion is not clear in some cases. 
     Nitrogen may be substituted for part of oxygen included in the CAAC-OS. The c-axes of individual crystalline portions included in the CAAC-OS film may be aligned in one direction (e.g., the direction perpendicular to a surface of a substrate over which the CAAC-OS is formed, a surface of the CAAC-OS or the CAAC-OS film, or an interface of the CAAC-OS film). Alternatively, normals of the a-b planes of individual crystalline portions included in the CAAC-OS film may be aligned in one direction (e.g., the direction perpendicular to a surface of a substrate over which the CAAC-OS film is formed, a surface of the CAAC-OS or the CAAC-OS film, an interface of the CAAC-OS film, or the like). 
     The crystalline oxide semiconductor layer enables a change of electric characteristics of the transistor due to irradiation with visible light or ultraviolet light to be further suppressed, leading to a highly reliable semiconductor device. 
     There are three methods for obtaining a crystalline oxide semiconductor layer having c-axis alignment. The first is a method in which an oxide semiconductor layer is deposited at a temperature higher than or equal to 200° C. and lower than or equal to 500° C. so that the c-axis is substantially perpendicular to the top surface. The second is a method in which an oxide semiconductor layer is deposited thin, and is subjected to heat treatment at a temperature(s) higher than or equal to 200° C. and lower than or equal to 700° C., so that the c-axis is substantially perpendicular to the top surface. The third is a method in which a first-layer oxide semiconductor layer is deposited thin, and is subjected to heat treatment at a temperature(s) higher than or equal to 200° C. and lower than or equal to 700° C., and a second-layer oxide semiconductor layer is deposited thereover, so that the c-axis is substantially perpendicular to the top surface. 
     The oxide semiconductor layer  403  has a thickness greater than or equal to 1 nm and less than or equal to 30 nm (preferably greater than or equal to 5 nm and less than or equal to 10 nm) and can be formed by a sputtering method, a molecular beam epitaxy (MBE) method, a CVD method, a pulse laser deposition method, an atomic layer deposition (ALD) method, or the like as appropriate. The oxide semiconductor layer  403  may be formed with a sputtering apparatus which performs deposition in the state where top surfaces of a plurality of substrates are substantially perpendicular to a top surface of a sputtering target. 
     For example, the CAAC-OS film is formed by a sputtering method with a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, a crystal region included in the sputtering target may be separated from the target along an a-b plane; in other words, a sputtered particle having a plane parallel to an a-b plane (flat-plate-like sputtered particle or pellet-like sputtered particle) may flake off from the sputtering target. In that case, the flat-plate-like sputtered particle reaches a substrate while maintaining their crystal state, whereby the CAAC-OS film can be formed. 
     For the deposition of the CAAC-OS film, the following conditions are preferably used. 
     By reducing the amount of impurities entering the CAAC-OS film during the deposition, the crystal state can be prevented from being broken by the impurities. For example, the concentration of impurities (e.g., hydrogen, water, carbon dioxide, or nitrogen) which exist in the deposition chamber may be reduced. Furthermore, the concentration of impurities in a deposition gas may be reduced. Specifically, a deposition gas whose dew point is −80° C. or lower, preferably −100° C. or lower is used. 
     By increasing the substrate heating temperature during the deposition, migration of a sputtered particle is likely to occur after the sputtered particle reaches a substrate surface. Specifically, the substrate heating temperature during the deposition is higher than or equal to 100° C. and lower than or equal to b 740° C., preferably higher than or equal to 200° C. and lower than or equal to 500° C. By increasing the substrate heating temperature during the deposition, when the flat-plate-like sputtered particle reaches the substrate, migration occurs on the substrate surface, so that a flat plane of the flat-plate-like sputtered particle is attached to the substrate. 
     Furthermore, it is preferable that the proportion of oxygen in the deposition gas be increased and the power be optimized in order to reduce plasma damage at the deposition. The proportion of oxygen in the deposition gas is 30 vol % or higher, preferably 100 vol %. 
     The sputtering target, which is a polycrystalline metal oxide target, is made by mixing each metal oxide powder in a predetermined molar ratio, applying pressure, and performing heat treatment at a temperature higher than or equal to 1000° C. and lower than or equal to 1500° C. The kinds of powder and the molar ratio for mixing powder may be determined as appropriate depending on the desired sputtering target. 
       FIGS. 1A to 1E  illustrate an example of a method for manufacturing the transistor  440   a.    
     First, the oxide insulating layer  436  is formed over the substrate  400  having an insulating surface. 
     There is no particular limitation on a substrate that can be used as the substrate  400  having an insulating surface as long as it has heat resistance enough to withstand heat treatment performed later. For example, a glass substrate of barium borosilicate glass, aluminoborosilicate glass, or the like, a ceramic substrate, a quartz substrate, or a sapphire substrate can be used. A single crystal semiconductor substrate or a polycrystalline semiconductor substrate of silicon, silicon carbide, or the like; a compound semiconductor substrate of silicon germanium or the like; an SOI substrate; or the like can be used as the substrate  400 , or the substrate provided with a semiconductor element can be used as the substrate  400 . 
     A flexible substrate may be used as the substrate  400  to manufacture a semiconductor device. To manufacture a flexible semiconductor device, the transistor  440   a  including the oxide semiconductor layer  403  may be directly formed over a flexible substrate; or alternatively, the transistor  440   a  including the oxide semiconductor layer  403  may be formed over a substrate, and then may be separated and transferred to a flexible substrate. Note that in order to separate the transistor  440   a  from the manufacturing substrate and transfer it to the flexible substrate, a separation layer may be provided between the manufacturing substrate and the transistor  440   a  including the oxide semiconductor film. 
     The oxide insulating layer  436  can be formed by a plasma CVD method, a sputtering method, or the like using any of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide, or a mixed material thereof. 
     The oxide insulating layer  436  may be either a single layer or a stacked layer. 
     A silicon oxide film is formed by a sputtering method as the oxide insulating layer  436  in this embodiment. 
     Further, a nitride insulating film may be provided between the oxide insulating layer  436  and the substrate  400 . The nitride insulating film can be formed using any of silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or a mixed material of any of these, by a plasma CVD method, a sputtering method, or the like. 
     Next, the oxide semiconductor layer  403  is formed over the oxide insulating layer  436 . 
     The oxide insulating layer  436 , which is in contact with the oxide semiconductor layer  403 , preferably contains oxygen which exceeds at least the stoichiometric composition ratio in the film (the bulk). For example, in the case where a silicon oxide film is used as the oxide insulating layer  436 , the composition formula is SiO 2+α  (α&gt;0). By using such a film as the oxide insulating layer  436 , oxygen can be supplied to the oxide semiconductor layer  403 , leading to favorable characteristics. By the supply of oxygen to the oxide semiconductor layer  403 , oxygen vacancies in the film can be reduced. 
     For example, when the oxide insulating layer  436  containing much (excessive) oxygen, which serves as an oxygen supply source, is provided so as to be in contact with the oxide semiconductor layer  403 , oxygen can be supplied from the oxide insulating layer  436  to the oxide semiconductor layer  403 . Heat treatment may be performed in the state where the oxide semiconductor layer  403  and the oxide insulating layer  436  are in contact with each other at least partly to supply oxygen to the oxide semiconductor layer  403 . 
     In order that hydrogen or water will be not contained in the oxide semiconductor layer  403  as much as possible in the formation step of the oxide semiconductor layer  403 , it is preferable to heat the substrate provided with the oxide insulating layer  436  in a preheating chamber in a sputtering apparatus as a pretreatment for formation of the oxide semiconductor layer  403  so that impurities such as hydrogen and moisture adsorbed to the substrate and/or the oxide insulating layer  436  are eliminated and evacuated. As an exhaustion unit provided in the preheating chamber, a cryopump is preferable. 
     Therefore, planarizing treatment may be performed on the region of the oxide insulating layer  436  which is in contact with the oxide semiconductor layer  403 . The planarization treatment may be, but not particularly limited to, polishing treatment (such as chemical mechanical polishing (CMP)), dry etching treatment, or plasma treatment. 
     As plasma treatment, reverse sputtering in which an argon gas is introduced and plasma is generated can be performed. The reverse sputtering is a method in which voltage is applied to a substrate side with use of an RF power source in an argon atmosphere and plasma is generated in the vicinity of the substrate so that a substrate surface is modified. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like may be used. The reverse sputtering can remove particle substances (also referred to as particles or dust) attached to the top surface of the oxide insulating layer  436 . 
     As the planarization treatment, polishing treatment, dry etching treatment, or plasma treatment may be performed plural times, or these treatments may be performed in combination. In the case where the treatments are combined, the order of steps is not particularly limited and may be set as appropriate depending on the roughness of the surface of the oxide insulating layer  436 . 
     The oxide semiconductor layer  403  is preferably deposited under a condition such that much oxygen is contained (for example, by a sputtering method in an atmosphere where the proportion of oxygen is 100%) so as to be a film containing much oxygen (preferably containing excessive oxygen as compared to the stoichiometric composition ratio of the oxide semiconductor in a crystalline state). 
     Note that in this embodiment, a target used for forming the oxide semiconductor layer  403  by a sputtering method is, for example, an oxide target having a composition ratio of indium: stabilizer (yttrium and zirconium): zinc of 1:1:1 (atomic ratio) where the composition ratio of yttrium: zirconium is 1:1 (atomic ratio); thus, an oxide semiconductor film containing indium, yttrium, zirconium, and zinc is formed. 
     The composition ratio of the oxide semiconductor film formed by a sputtering method is not equivalent to or the same as that of the target in some cases, and for example a film in which the percentage of zinc is lower than that of indium may be formed. In other words, an oxide semiconductor film having a composition ratio of indium: stabilizer (yttrium and zirconium): zinc that is equal to or in the neighborhood of the composition ratio of the target is formed. Even in such a case, increasing the percentage of oxygen (making the oxygen excessive state) in the oxide semiconductor film can suppress generation of defects due to oxygen vacancies, thereby forming an intrinsic or substantially intrinsic oxide semiconductor film. 
     The relative density (the fill rate) of the metal oxide target is 90% to 100% inclusive, preferably 95% to 99.9% inclusive. By using the metal oxide target with high relative density, a dense oxide semiconductor film can be formed. 
     It is preferable to use a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed as a sputtering gas used when the oxide semiconductor layer  403  is formed. 
     The substrate is held in a film formation chamber kept under reduced pressure. Then, a sputtering gas from which hydrogen and moisture are removed is introduced while residual moisture in the film formation chamber is removed, and the oxide semiconductor layer  403  is formed over the substrate  400  using the above target. In order to remove moisture remaining in the deposition chamber, an entrapment vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump is preferably used. As an exhaustion unit, a turbo molecular pump to which a cold trap is added may be used. In the deposition chamber which is evacuated with an entrapment vacuum pump such as a cryopump, a hydrogen atom, a compound containing a hydrogen atom such as water (H 2 O) (further preferably, also a compound containing a carbon atom), and the like are removed, whereby the impurity concentration in the oxide semiconductor layer  403  formed in the deposition chamber can be reduced. 
     The oxide insulating layer  436  and the oxide semiconductor layer  403  are preferably formed in succession without exposure to the air. Through successive formation of the oxide insulating layer  436  and the oxide semiconductor layer  403  without exposure to the air, impurities such as hydrogen and moisture can be prevented from being adsorbed onto a surface of the oxide insulating layer  436 . 
     The oxide semiconductor layer  403  can be formed by processing an oxide semiconductor film into an island shape by a photolithography process. 
     Further, a resist mask for forming the island-shaped oxide semiconductor layer  403  may be formed by an inkjet method. Formation of the resist mask by an inkjet method needs no photomask; thus, manufacturing cost can be reduced. 
     Note that the etching of the oxide semiconductor film may be dry etching, wet etching, or both dry etching and wet etching. As an etchant used for wet etching of the oxide semiconductor film, for example, a mixed solution of phosphoric acid, acetic acid, and nitric acid, or the like can be used. 
     Further, heat treatment may be performed on the oxide semiconductor layer  403  in order to remove excess hydrogen (including water and a hydroxyl group) (to perform dehydration or dehydrogenation treatment). The temperature of the heat treatment is higher than or equal to 300° C. and lower than or equal to 700° C., or lower than the strain point of the substrate. The heat treatment can be performed under reduced pressure, a nitrogen atmosphere, or the like. For example, the substrate is put in an electric furnace which is a kind of heat treatment apparatus, and the oxide semiconductor layer  403  is subjected to the heat treatment at 450° C. for an hour in a nitrogen atmosphere. 
     Further, a heat treatment apparatus used is not limited to an electric furnace, and a device for heating a process object by heat conduction or heat radiation from a heating element such as a resistance heating element may be alternatively used. For example, an RTA (rapid thermal anneal) apparatus such as a GRTA (gas rapid thermal anneal) apparatus or an LRTA (lamp rapid thermal anneal) apparatus can be used. An LRTA apparatus is an apparatus for heating a process object by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. A GRTA apparatus is an apparatus for heat treatment using a high-temperature gas. As the high-temperature gas, an inert gas which does not react with a process object by heat treatment, such as nitrogen or a rare gas such as argon, is used. 
     For example, as the heat treatment, GRTA may be performed as follows. The substrate is put in an inert gas heated at high temperature of 650° C. to 700° C., is heated for several minutes, and is taken out of the inert gas. 
     Note that in heat treatment, it is preferable that moisture, hydrogen, and the like be not contained in nitrogen or a rare gas such as helium, neon, or argon. The purity of nitrogen or the rare gas such as helium, neon, or argon which is introduced into the heat treatment apparatus is set to preferably 6N (99.9999%) or higher, further preferably 7N (99.99999%) or higher (that is, the impurity concentration is preferably 1 ppm or lower, further preferably 0.1 ppm or lower). 
     In addition, after the oxide semiconductor layer  403  is heated by the heat treatment, a high-purity oxygen gas, a high-purity dinitrogen monoxide gas, or ultra dry air (the moisture amount is less than or equal to 20 ppm (−55° C. by conversion into a dew point), preferably less than or equal to 1 ppm, further preferably less than or equal to 10 ppb, in the measurement with the use of a dew point meter of a cavity ring down laser spectroscopy (CRDS) system) may be introduced into the same furnace. It is preferable that water, hydrogen, or the like be not contained in the oxygen gas or the dinitrogen monoxide gas. The purity of the oxygen gas or the dinitrogen monoxide gas which is introduced into the heat treatment apparatus is preferably 6N or more, further preferably 7N or more (i.e., the impurity concentration in the oxygen gas or the dinitrogen monoxide gas is preferably 1 ppm or lower, further preferably 0.1 ppm or lower). The oxygen gas or the dinitrogen monoxide gas acts to supply oxygen that is a main component of the oxide semiconductor and that is reduced by the step for removing an impurity for the dehydration or dehydrogenation, so that the oxide semiconductor layer  403  can be a highly-purified, i-type (intrinsic) oxide semiconductor film. 
     Note that the heat treatment for dehydration or dehydrogenation can be performed in the process of manufacturing the transistor  440   a  anytime after formation of the oxide semiconductor film which is to be processed into the oxide semiconductor layer  403  and before formation of the insulating film  407 . For example, the heat treatment may be performed after formation of the oxide semiconductor film or after formation of the island-shaped oxide semiconductor layer  403 . 
     Further, the heat treatment for dehydration or dehydrogenation may be performed more than once or may be combined with another heat treatment. 
     When the heat treatment for dehydration or dehydrogenation is performed in the state where the oxide insulating layer  436  is covered with the oxide semiconductor film which has not been processed into the island-shaped oxide semiconductor layer  403 , oxygen contained in the oxide insulating layer  436  can be prevented from being released by the heat treatment, which is preferable. 
     Further or alternatively, oxygen (which includes at least one of an oxygen radical, an oxygen atom, and an oxygen ion) may be introduced into the oxide semiconductor layer that has been subjected to the dehydration or dehydrogenation treatment in order to supply oxygen to the oxide semiconductor layer. 
     Introduction (supply) of oxygen to the dehydrated or dehydrogenated oxide semiconductor layer  403  enables the oxide semiconductor layer  403  to be highly purified and to be i-type (intrinsic). Variation in electrical characteristics of a transistor having the highly-purified and i-type (intrinsic) oxide semiconductor layer  403  is suppressed, and the transistor is electrically stable. 
     As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like may be used. 
     In the step of introducing oxygen into the oxide semiconductor layer  403 , oxygen may be directly introduced into the oxide semiconductor layer  403  or introduced into the oxide semiconductor layer  403  through another film such as the gate insulating film  402  or the insulating film  407 . An ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like may be employed for the introduction of oxygen through another film, whereas plasma treatment or the like can be employed for the introduction of oxygen directly into the exposed oxide semiconductor layer  403 . 
     The addition of oxygen into the oxide semiconductor layer  403  can be performed anytime after dehydration or dehydrogenation treatment is performed thereon. Further, oxygen may be introduced a plurality of times into the dehydrated or dehydrogenated oxide semiconductor layer  403 . 
     Next, a conductive film to be a source electrode layer and a drain electrode layer (including a wiring formed in the same layer as the source electrode layer and the drain electrode layer) is formed over the oxide semiconductor layer  403 . The conductive film is formed using a material that can withstand heat treatment in a later step. As a conductive film used for the source electrode layer and the drain electrode layer, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W and a metal nitride film containing any of the above elements as its main component (a titanium nitride film, a molybdenum nitride film, and a tungsten nitride film) can be used. A film of a high melting point metal such as Ti, Mo, W, or the like or a metal nitride film of any of these elements (a titanium nitride film, a molybdenum nitride film, and a tungsten nitride film) may be stacked on one of or both of a lower side and an upper side of a metal film of Al, Cu, or the like. Alternatively, the conductive film used for the source electrode layer and the drain electrode layer may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide, tin oxide, zinc oxide, indium oxide-tin oxide, indium oxide-zinc oxide, or any of these metal oxide materials in which silicon oxide is contained can be used. 
     Through a photolithography process, a resist mask is formed over the conductive film, and selective etching is performed thereon, so that the source electrode layer  405   a  and the drain electrode layer  405   b  are formed, and then, the resist mask is removed. 
     Next, the gate insulating film  402  covering the oxide semiconductor layer  403 , the source electrode layer  405   a , and the drain electrode layer  405   b  is formed (see  FIG. 1A ). 
     To improve the coverage with the gate insulating film  402 , the above-described planarizing treatment may be performed also on the top surface of the oxide semiconductor layer  403  and top surfaces of the source electrode layer  405   a  and the drain electrode layer  405   b . It is preferable that the flatness of the top surface of the oxide semiconductor layer  403  and the top surfaces of the source electrode layer  405   a  and the drain electrode layer  405   b  be good particularly when the thickness of the gate insulating film  402  is small. 
     The gate insulating film  402  can be formed to have a thickness greater than or equal to 1 nm and less than or equal to 20 nm by a sputtering method, an MBE method, a CVD method, a pulse laser deposition method, an ALD method, or the like as appropriate. Alternatively, the gate insulating film  402  may be formed with a sputtering apparatus in which film formation is performed with surfaces of a plurality of substrates set substantially perpendicular to a surface of a sputtering target. 
     The gate insulating film  402  can be formed using a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film. It is preferable that the gate insulating film  402  include oxygen in a portion which is in contact with the oxide semiconductor layer  403 . In particular, the gate insulating film  402  preferably contains a large amount of oxygen which exceeds at least the stoichiometric ratio in (a bulk of) the film. For example, in the case where a silicon oxide film is used as the gate insulating film  402 , the composition formula thereof is SiO 2+α  (α&gt;0). In this embodiment, a silicon oxide film of SiO 2+α  (α&gt;0) is used as the gate insulating film  402 . By using the silicon oxide film as the gate insulating film  402 , oxygen can be supplied to the oxide semiconductor layer  403 , leading to good characteristics. Further, the gate insulating film  402  is preferably formed in consideration of the size of a transistor to be formed and the step coverage with the gate insulating film  402 . 
     When the gate insulating film  402  is formed using a high-k material such as  20  hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y (x&gt; 0, y&gt;0)), hafnium silicate (HfSi x O y (x&gt; 0, y&gt;0)) to which nitrogen is added, hafnium aluminate (HfAl x O y  (x&gt;0,y&gt;0)), or lanthanum oxide, gate leakage current can be reduced. Further, the gate insulating film  402  may have either a single-layer structure or a stacked-layer structure. 
     Then, the gate electrode layer  401  is formed over the gate insulating film  402  by a plasma CVD method, a sputtering method, or the like (see  FIG. 1B ). The gate electrode layer  401  can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium or an alloy material which contains any of these materials as its main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as a nickel silicide film may be used as the gate electrode layer  401 . The gate electrode layer  401  may have a single-layer structure or a stacked-layer structure. 
     The gate electrode layer  401  can also be formed using a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added. It is also possible that the gate electrode layer  401  has a stacked structure of the above conductive material and the above metal material. 
     As one layer of the gate electrode layer  401  which is in contact with the gate insulating film  402 , a metal oxide containing nitrogen, specifically, an In—Ga—Zn—O film containing nitrogen, an In—Sn—O film containing nitrogen, an In—Ga—O film containing nitrogen, an In—Zn—O film containing nitrogen, a Sn—O film containing nitrogen, an In—O film containing nitrogen, or a metal nitride (e.g., InN or SnN) film can be used. These films each have a work function higher than or equal to 5 eV, preferably higher than or equal to 5.5 eV; thus, when these are used as the gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be positive. Accordingly, a so-called normally-off switching element can be provided. 
     Next, a dopant  421  is introduced into the oxide semiconductor layer  403  with the use of the gate electrode layer  401 , the source electrode layer  405   a , and the drain electrode layer  405   b  as masks, whereby the low-resistance regions  404   a  and  404   b  are formed. 
     Depending on the thickness of the source electrode layer  405   a  and the drain electrode layer  405   b  and the condition of introduction of the dopant  421 , the dopant  421  may be introduced into the oxide semiconductor layer  403  in the regions under the source electrode layer  405   a  and the drain electrode layer  405   b  in some cases, or the dopant  421  may be introduced into the oxide semiconductor layer  403  in the regions under the source electrode layer  405   a  and the drain electrode layer  405   b  such that the dopant concentration in each of the regions is higher than that of the other low-resistance regions in the oxide semiconductor layer  403 . 
     In a transistor  440   c  in  FIG. 2B , a tungsten film with small thickness, for example 10 nm, is formed as the source electrode layer  405   a  and the drain electrode layer  405   b . Owing to the above-described small thickness of each of the source electrode layer  405   a  and the drain electrode layer  405   b , when a dopant is introduced into the oxide semiconductor layer  403  to form low-resistance regions, the dopant can also be introduced into the oxide semiconductor layer  403  which is below the source electrode layer  405   a  and the drain electrode layer  405   b , through the source electrode layer  405   a  and the drain electrode layer  405   b . As a result, in the transistor  440   c , the low-resistance regions  404   a  and  404   b  are formed in the oxide semiconductor layer  403  which is below the source electrode layer  405   a  and the drain electrode layer  405   b.    
     The dopant  421  is an impurity by which the electrical conductivity of the oxide semiconductor layer  403  is changed. One or more selected from the following can be used as the dopant  421 : Group 15 elements (typical examples thereof are phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), nitrogen (N), argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn). 
     The dopant  421  can be introduced into the oxide semiconductor layer  403  through other films (e.g., the insulating film  407 , the source electrode layer  405   a , and the drain electrode layer  405   b ) by an implantation method. As the method for introducing the dopant  421 , an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used. In the case where the above method is used, it is preferable to use a single ion of the dopant  421 , a fluoride ion, or a chloride ion. 
     The introduction of the dopant  421  may be controlled by setting the addition conditions such as the acceleration voltage and the dosage, or the thickness of the films through which the dopant passes as appropriate. In this embodiment, boron is used as the dopant  421 , whose ion is introduced by an ion implantation method. The dosage of the dopant  421  is preferably set to be greater than or equal to 1×10 13  ions/cm 2  and less than or equal to 5×10 16  ions/cm 2 . 
     The concentration of the dopant  421  in the low-resistance regions is preferably greater than or equal to 5×10 18 /cm 3  and less than or equal to 1×10 22 /cm 3 . 
     The dopant  421  may be introduced while the substrate  400  is heated. 
     The introduction of the dopant  421  into the oxide semiconductor layer  403  may be performed a plurality of times, and a plurality of kinds of dopants may be used. 
     Further, heat treatment may be performed thereon after the introduction of the dopant  421 . The heat treatment is preferably performed at a temperature(s) higher than or equal to 300° C. and lower than or equal to 700° C. (further preferably higher than or equal to 300° C. and lower than or equal to 450° C.) for one hour under an oxygen atmosphere. The heat treatment may be performed under a nitrogen atmosphere, reduced pressure, or the air (ultra-dry air). 
     In the case where the oxide semiconductor layer  403  is a crystalline oxide semiconductor film, part of the oxide semiconductor layer  403  may become amorphous by  20  the introduction of the dopant  421 . In that case, the crystallinity of the oxide semiconductor layer  403  can be recovered by performing a heat treatment thereon after the introduction of the dopant  421 . 
     Thus, the oxide semiconductor layer  403  in which the low-resistance regions  404   a  and  404   b  are formed with the channel formation region  409  sandwiched therebetween is formed. 
     Through the above-described process, the transistor  440   a  of this embodiment can be manufactured (see  FIG. 1C ). With the non-single-crystal oxide semiconductor layer  403  containing at least indium, a Group 3 element, zinc, and oxygen, high on-state characteristics (high field-effect mobility), low off-state current, and high reliability of the transistor  440   a  can be achieved. 
     Next, the insulating film  407  is formed over the oxide semiconductor layer  403 , the source electrode layer  405   a , the drain electrode layer  405   b , the gate insulating film  402 , and the gate electrode layer  401  (see  FIG. 1D ). 
     The insulating film  407  can be formed by a plasma-enhanced CVD method, a sputtering method, an evaporation method, or the like. As the insulating film  407 , an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, or a gallium oxide film can be typically used. 
     Alternatively, as the insulating film  407 , an aluminum oxide film, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film, or a metal nitride film (e.g., an aluminum nitride film) can be used. 
     The insulating film  407  can be either a single-layer film or a stacked-layer film. The insulating film  407  can be a stack of a silicon oxide film and an aluminum oxide film, for example. 
     The insulating film  407  is preferably formed by a method such as a sputtering method, in which an impurity such as water or hydrogen does not enter the insulating film  407 . In addition, it is preferable that the insulating film  407  include an excessive amount of oxygen on the side closer to the oxide semiconductor layer  403  because the film including an excessive amount of oxygen serves as a supply source of oxygen for the oxide semiconductor layer  403 . 
     In this embodiment, a silicon oxide film with a thickness of 100 nm is formed as the insulating film  407  by a sputtering method. The silicon oxide film can be formed by a sputtering method under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas and oxygen. 
     In order to remove residual moisture from the deposition chamber of the insulating film  407  in a manner similar to that of the deposition of the oxide semiconductor film, an entrapment vacuum pump (such as a cryopump) is preferably used. When the insulating film  407  is deposited in the deposition chamber evacuated using a cryopump, the impurity concentration of the insulating film  407  can be reduced. As an evacuation unit for removing moisture remaining in the deposition chamber of the insulating film  407 , a turbo molecular pump provided with a cold trap may be used. 
     It is preferable that a high-purity gas in which an impurity such as hydrogen, water, a hydroxyl group, or hydride is reduced be used as the sputtering gas for the formation of the insulating film  407 . 
     The aluminum oxide film which can be used as the insulating film  407  provided over the oxide semiconductor layer  403  has a high shielding (blocking) effect of preventing penetration of both oxygen and an impurity such as hydrogen or moisture. 
     Therefore, in and after the manufacturing process, the aluminum oxide film functions as a protective film for preventing entry of an impurity such as hydrogen or moisture, which causes a change, into the oxide semiconductor layer  403  and release of oxygen, which is a main constituent material of the oxide semiconductor, from the oxide semiconductor layer  403 . 
     Further, a planarization insulating film may be formed thereover in order to reduce surface roughness due to the transistor. As the planarization insulating film, an organic material such as polyimide, an acrylic resin, or a benzocyclobutene-based resin can be used. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material) or the like. Note that the planarization insulating film may be formed by stacking a plurality of insulating films formed from these materials. 
     Further, respective openings reaching the source electrode layer  405   a  and the drain electrode layer  405   b  are formed in the gate insulating film  402  and the insulating film  407 , and a wiring layer  465   a  and a wiring layer  465   b  electrically connected to the source electrode layer  405   a  and the drain electrode layer  405   b , respectively, are formed in the openings (see  FIG. 1E ). With the use of these wiring layers  465   a  and  465   b , the transistor is connected to another transistor, which can lead to formation of a variety of circuits. 
     Alternatively, as a transistor  440 d in  FIG. 2C , the wiring layers  465   a  and  465   b  may be formed directly on the oxide semiconductor layer  403  without providing the source electrode layer  405   a  and the drain electrode layer  405   b.    
     The wiring layers  465   a  and  465   b  can be formed using a material and a method which are similar to those of the gate electrode layer  401 , the source electrode layer  405   a , and the drain electrode layer  405   b . For example, as the wiring layers  465   a  and  465   b , a stack of a tantalum nitride film and a copper film or a stack of a tantalum nitride film and a tungsten film can be used. 
     In the oxide semiconductor layer  403  which is highly purified and whose oxygen vacancies are reduced, impurities such as hydrogen and water are sufficiently removed; the hydrogen concentration in the oxide semiconductor layer  403  is less than or equal to 5×10 19 /cm 3 , preferably less than or equal to 5×10 18 /cm 3 . The hydrogen concentration in the oxide semiconductor layer  403  is measured by secondary ion mass spectrometry (SIMS). 
     The current value in the off state (off-state current value) of the transistor  440   a  which uses the highly purified oxide semiconductor layer  403  containing an excessive amount of oxygen that reduces an oxygen vacancy according to this embodiment is less than or equal to 100 zA per micrometer of channel width at room temperature (1 zA (zeptoampere)=1×10 −21  A), preferably less than or equal to 50 zA/mm. 
     In the above-described manner, it is possible to provide a structure of a semiconductor device which achieves quick response and high-speed drive by improving on-state characteristics (e.g., on-state current and field-effect mobility) of a transistor, and to provide a method for manufacturing the structure, in order to achieve a semiconductor device with higher performance. 
     A highly reliable semiconductor device whose threshold voltage is unlikely to shift even after long-term usage can be provided. 
     [Embodiment 2] 
     In this embodiment, another embodiment of a semiconductor device will be described with reference to  FIGS. 3A to 3D . The same portions as those in the above embodiment or the portions having functions similar to those in the above embodiment can be formed in manners similar to those of the above embodiment. The same steps as those in the above embodiment and steps similar to those in the above embodiment can be conducted in manners similar to those of the above embodiment. Therefore, the descriptions thereof are not repeated in this embodiment. In addition, detailed description of the same portions is omitted. A transistor  420  illustrated in  FIGS. 3A to 3C  in this embodiment is an example of a transistor having a top-gate structure.  FIG. 3A  is a plan view of the transistor  420 ,  FIG. 3B  is a cross-sectional view taken along line X-Y in  FIG. 3A , and  FIG. 3C  is a cross-sectional view taken along line V-W in  FIG. 3A . 
     The transistor  420  is provided over a substrate  400  having an insulating surface and includes a source electrode layer  405   a  and a drain electrode layer  405   b  embedded in an oxide insulating layer  436 , an oxide semiconductor layer  403  in contact with part of the source electrode layer  405   a  and part of the drain electrode layer  405   b , a gate insulating film  402  covering the oxide semiconductor layer  403 , and a gate electrode layer  401  provided over the gate insulating film  402  so as to overlap with the oxide semiconductor layer  403 . An insulating film  407  is formed over the transistor  420 . A wiring layer  465   a  and a wiring layer  465   b  which are electrically connected to the source electrode layer  405   a  and the drain electrode layer  405   b , respectively, are provided over the insulating film  407 . 
     The transistor  420  includes the source electrode layer  405   a  and the drain electrode layer  405   b  which are embedded in the oxide insulating layer  436 . For example, such source electrode layer  405   a  and drain electrode layer  405   b  embedded in the oxide insulating layer  436  can be formed in the following manner: after the oxide insulating layer  436  is formed over the source electrode layer  405   a  and the drain electrode layer  405   b , CMP treatment is performed to expose upper surfaces of the source electrode layer  405   a  and the drain electrode layer  405   b . Other than or in addition to the CMP treatment, etching treatment or the like can be employed. For higher crystallinity of the oxide semiconductor layer  403  provided over the oxide insulating layer  436 , a surface of the oxide insulating layer  436  is preferably as flat as possible. 
     In  FIGS. 3A to 3C , the source electrode layer  405   a  and the drain electrode layer  405   b  of the transistor  420  are electrically connected to the wiring layer  465   a  and the wiring layer  465   b , respectively, with the oxide semiconductor layer  403  interposed therebetween. Alternatively, as illustrated in  FIG. 3D , the drain electrode layer  405   b  (or the source electrode layer  405   a ) may be in direct contact with the wiring layer  465   b  (or the wiring layer  465   a ) in a region where the oxide semiconductor layer  403  is not provided. 
     In the transistor  420 , the oxide semiconductor layer  403  includes a channel formation region  409  and a pair of low-resistance regions  404   a  and  404   b  that are formed in a self-aligned manner by introducing a dopant with the use of the gate electrode layer  401  as a mask. However, the oxide semiconductor layer  403  of this embodiment is not limited to the one described above and may be an oxide semiconductor layer not containing a dopant. 
     The oxide semiconductor layer  403  in the transistor  420  is a non-single-crystal oxide semiconductor layer containing at least indium, a Group 3 element, zinc, and oxygen. The oxide semiconductor layer  403  is a non-single-crystal layer and may be a mixed layer including a crystalline region and an amorphous region. As a crystal, a CAAC is preferable. 
     The Group 3 element functions as a stabilizer (stabilization agent). A favorable example of the Group 3 element is yttrium (Y). 
     As the stabilizer, a Group 4 element may be used in addition to the Group 3 element. As the Group 4 element, zirconium (Zr) or titanium (Ti) can be used favorably. For example, as the stabilizer, yttrium and zirconium, yttrium and titanium, cerium (Ce) and titanium, or cerium and zirconium can be used in combination. 
     As the stabilizer, a Group 13 element may be used in addition to the Group 3 element. As the Group 13 element, gallium (Ga) can be used favorably. For example, as the stabilizer, yttrium and gallium, or cerium and gallium can be used in combination. 
     The oxide semiconductor layer  403  can be formed by a sputtering method using an oxide target having a composition ratio of indium: stabilizer: zinc of 1:1:1 (atomic ratio), 3:1:2 (atomic ratio), or 2:1:3 (atomic ratio), or an oxide target whose composition is in the neighborhood of that of the above-described oxide target. 
     In the case of using a Group 3 element and a Group 4 element as the stabilizer, the oxide semiconductor layer  403  can be formed by a sputtering method using an oxide target having a composition ratio of the Group 3 element to the Group 4 element of 1:1 (atomic ratio), 2:1 (atomic ratio), or 1:2 (atomic ratio). 
     Alternatively, in the case of using a Group 3 element and a Group 13 element as the stabilizer, the oxide semiconductor layer  403  can be formed by a sputtering method using an oxide target having a composition ratio of the Group 3 element to the Group 13 element of 1:1 (atomic ratio), 2:1 (atomic ratio), or 1:2 (atomic ratio). 
     Note that the composition ratio of the oxide semiconductor layer reflects the composition ratio of the oxide target but is not necessarily the same as the composition ratio of the oxide target. For example, even in the case where the composition ratio of the oxide target can be expressed by natural numbers in the above-described manner, the composition ratio of the oxide semiconductor layer formed using the oxide target may be expressed by non-natural numbers. 
     In this embodiment, the oxide semiconductor layer  403  is formed by a sputtering method using an oxide target having a composition ratio of indium: stabilizer (yttrium and zirconium): zinc of 1:1:1 (atomic ratio) where the composition ratio of yttrium: zirconium is 1:1 (atomic ratio). 
     The transistor  420  including the non-single-crystal oxide semiconductor layer containing at least indium, the Group 3 element, zinc, and oxygen has high on-state characteristics (e.g., on-state current and field-effect mobility); thus, quick response and high-speed drive of a semiconductor device are achieved. 
     A highly reliable semiconductor device whose threshold voltage is unlikely to shift even after long-term usage can be provided. 
     This embodiment can be implemented in combination with any of the other embodiments as appropriate. 
     [Embodiment 3] 
     In this embodiment, another embodiment of a semiconductor device will be described with reference to  FIGS. 4A to 4C . The same portions as those in the above embodiment or the portions having functions similar to those in the above embodiment can be formed in manners similar to those of the above embodiment. The same steps as those in the above embodiment and steps similar to those in the above embodiment can be conducted in manners similar to those of the above embodiment. Therefore, the descriptions thereof are not repeated in this embodiment. In addition, detailed description of the same portions is omitted. 
     A transistor  480 , a transistor  410 , and a transistor  430  illustrated in  FIGS. 4A to 4C  in this embodiment are examples of a transistor having a bottom-gate structure.  FIGS. 4A to 4C  are cross-sectional views of the transistor  480 , the transistor  410 , and the transistor  430  in a channel length direction. 
     One mode of the semiconductor device is the transistor  480  illustrated in  FIG. 4A . The transistor  480  is an inverted staggered transistor, which is one of bottom-gate transistors. 
     The transistor  480  includes a gate electrode layer  401 , a gate insulating film  402 , a non-single-crystal oxide semiconductor layer  403  containing at least indium, a Group 3 element, zinc, and oxygen, a source electrode layer  405   a , and a drain electrode layer  405   b , which are sequentially provided over a substrate  400  having an insulating surface. An insulating film  407  is formed over the transistor  480 . 
     Another mode of the semiconductor device is the transistor  410  illustrated in  FIG. 4B . The transistor  410  has one type of a bottom-gate structure called a channel protective type (also called a channel stop type) and is also referred to as an inverted staggered transistor. 
     The transistor  410  includes a gate electrode layer  401 , a gate insulating film  402 , a non-single-crystal oxide semiconductor layer  403  containing at least indium, a Group 3 element, zinc, and oxygen, an insulating film  427 , a source electrode layer  405   a , and a drain electrode layer  405   b , which are sequentially provided over a substrate  400  having an insulating surface. An insulating film  408  is formed over the transistor  410 . 
     The insulating film  427  is provided over a region overlapping with the gate electrode layer  401  of the oxide semiconductor layer  403 , and functions as a channel protective film. 
     The insulating film  427  may be formed using a material and a method similar to those of the insulating film  407 ; as a typical example, a single layer or a stacked layer using one or more of inorganic insulating films such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a hafnium oxide film, a gallium oxide film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, and an aluminum nitride oxide film can be used. 
     When the insulating film  427  in contact with the oxide semiconductor layer  403  (or a film in contact with the oxide semiconductor layer  403  in the case where the insulating film  427  has a stacked-layer structure) contains much oxygen, the insulating film  427  (or the film in contact with the oxide semiconductor layer  403 ) can favorably function as a supply source which supplies oxygen to the oxide semiconductor layer  403 . 
     The insulating film  408  can be formed using a material and a method similar to those of the insulating film  407 . 
     Another mode of the semiconductor device is the bottom-gate transistor  430  illustrated in  FIG. 4C . 
     The transistor  430  includes a gate electrode layer  401 , a gate insulating film  402 , a source electrode layer  405   a , a drain electrode layer  405   b , and a non-single-crystal oxide semiconductor layer  403  containing at least indium, a Group 3 element, zinc, and oxygen, which are sequentially provided over a substrate  400  having an insulating surface. An insulating film  407  is formed over the transistor  430 . 
     The transistor  430  has a structure in which the oxide semiconductor layer  403  is provided over the source electrode layer  405   a  and the drain electrode layer  405   b . 
     The oxide semiconductor layer  403  is a non-single-crystal layer and may be a mixed layer including a crystalline region and an amorphous region. The mixed layer including a crystalline region and an amorphous region is preferably a CAAC-OS film. 
     The Group 3 element functions as a stabilizer (stabilization agent). A favorable example of the Group 3 element is yttrium (Y). 
     As the stabilizer, a Group 4 element may be used in addition to the Group 3 element. As the Group 4 element, zirconium (Zr) or titanium (Ti) can be used favorably. For example, as the stabilizer, yttrium and zirconium, yttrium and titanium, cerium (Ce) and titanium, or cerium and zirconium can be used in combination. 
     As the stabilizer, a Group 13 element may be used in addition to the Group 3 element. A favorable example of the Group 13 element is gallium (Ga). For example, as the stabilizer, yttrium and gallium, or cerium and gallium can be used in combination. 
     The oxide semiconductor layer  403  can be formed by a sputtering method using an oxide target having a composition ratio of indium: stabilizer: zinc of 1:1:1 (atomic ratio), 3:1:2 (atomic ratio), or 2:1:3 (atomic ratio), or an oxide target whose composition is in the neighborhood of that of the above-described oxide target. 
     In the case of using a Group 3 element and a Group 4 element as the stabilizer, the oxide semiconductor layer  403  can be formed by a sputtering method using an oxide target having a composition ratio of the Group 3 element to the Group 4 element of 1:1 (atomic ratio), 2:1 (atomic ratio), or 1:2 (atomic ratio). 
     Alternatively, in the case of using a Group 3 element and a Group 13 element as the stabilizer, the oxide semiconductor layer  403  can be formed by a sputtering method using an oxide target having a composition ratio of the Group 3 element to the Group 13 element of 1:1 (atomic ratio), 2:1 (atomic ratio), or 1:2 (atomic ratio). 
     Note that the composition ratio of the oxide semiconductor layer reflects the composition ratio of the oxide target but is not necessarily the same as the composition ratio of the oxide target. For example, even in the case where the composition ratio of the oxide target can be expressed by natural numbers in the above-described manner, the composition ratio of the oxide semiconductor layer formed using the oxide target may be expressed by non-natural numbers. 
     In this embodiment, the oxide semiconductor layer  403  is formed by a sputtering method using an oxide target having a composition ratio of indium: stabilizer (yttrium and zirconium): zinc of 1:1:1 (atomic ratio) where the composition ratio of yttrium: zirconium is 1:1 (atomic ratio). 
     The transistors  480 ,  410 , and  430  including the non-single-crystal oxide semiconductor layer containing at least indium, the Group 3 element, zinc, and oxygen have high on-state characteristics (e.g., on-state current and field-effect mobility); thus, quick response and high-speed drive of a semiconductor device are achieved. 
     A highly reliable semiconductor device whose threshold voltage is unlikely to shift even after long-term usage can be provided. 
     This embodiment can be implemented in combination with any of the other embodiments as appropriate. 
     [Embodiment 4] 
     In this embodiment, an example of a semiconductor device which includes the transistor described in any of Embodiments 1 to 3, which can hold stored data even when not powered, and which does not have a limitation on the number of write cycles, will be described with reference to drawings. Note that a transistor  162  included in the semiconductor device in this embodiment is the transistor described in any of Embodiments 1 to 3. Any of the structures of the transistors described in Embodiments 1 to 3 can be employed for the transistor  162 . 
     Since the off-state current of the transistor  162  is small, stored data can be held for a long time owing to such a transistor. In other words, power consumption can be sufficiently reduced because a semiconductor storage device in which refresh operation is unnecessary or the frequency of refresh operation is extremely low can be provided. 
       FIGS. 5A and 5B  illustrate an example of a structure of a semiconductor device.  FIG. 5A  is a cross-sectional view of the semiconductor device,  FIG. 5B  is a plan view of the semiconductor device, and  FIG. 5C  is a circuit diagram of the semiconductor device. Here,  FIG. 5A  corresponds to a cross section along line C 1 -C 2  and line D 1 -D 2  in  FIG. 5B . 
     The semiconductor device illustrated in  FIGS. 5A and 5B  includes a transistor  160  including a first semiconductor material in a lower portion, and the transistor  162  including a second semiconductor material in an upper portion. The transistor  162  can have the same structure as that described in any of Embodiments 1 to 3. 
     Here, the first semiconductor material and the second semiconductor material are preferably materials having different band gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (e.g., silicon) and the second semiconductor material may be an oxide semiconductor. A transistor including a material other than an oxide semiconductor can operate at high speed easily. On the other hand, a transistor including an oxide semiconductor enables holding of charge for a long time owing to its characteristics. 
     Although all the transistors are n-channel transistors here, p-channel transistors can be used. The technical nature of this embodiment of the disclosed invention is to use an oxide semiconductor in the transistor  162  so that data can be held. Therefore, it is not necessary to limit a specific structure of the semiconductor device, such as a material of the semiconductor device or a structure of the semiconductor device, to the structure described here. 
     The transistor  160  in  FIG. 5A  includes a channel formation region  116  provided over a substrate  185  including a semiconductor material (e.g., silicon), impurity regions  120  with the channel formation region  116  provided therebetween, metal compound regions  124  in contact with the impurity regions  120 , a gate insulating layer  108  provided over the channel formation region  116 , and a gate electrode  110  provided over the gate insulating layer  108 . Note that a transistor whose source electrode and drain electrode are not illustrated in a drawing may be referred to as a transistor for the sake of convenience. Further, in such a case, in description of a connection of a transistor, a source region and a source electrode are collectively referred to as a “source electrode”, and a drain region and a drain electrode are collectively referred to as a “drain electrode”. That is, in this specification, the term “source electrode” may include a source region. 
     An element isolation insulating layer  106  is provided over the substrate  185  to surround the transistor  160 . Insulating layers  128  and  130  are provided to cover the  30  transistor  160 . Note that in order to realize high integration, it is preferable that, as in  FIG. 5A , the transistor  160  does not have a sidewall insulating layer. On the other hand, when the characteristics of the transistor  160  have priority, the sidewall insulating layer may be formed on a side surface of the gate electrode  110  and the impurity regions  120  may include a region having a different impurity concentration. 
     The transistor  162  shown in  FIG. 5A  includes an oxide semiconductor in the channel formation region. Here, an oxide semiconductor layer  144  included in the transistor  162  is preferably highly purified. By using a highly purified oxide semiconductor, the transistor  162  can have extremely favorable off-state current characteristics. 
     An insulating layer  150  having a single-layer structure or a stacked-layer structure is provided over the transistor  162 . In addition, a conductive layer  148   b  is provided in a region overlapping with an electrode layer  142   a  of the transistor  162  with the insulating layer  150  provided therebetween, and the electrode layer  142   a , the insulating layer  150 , and the conductive layer  148   b  form a capacitor  164 . That is, the electrode layer  142   a  of the transistor  162  functions as one electrode of the capacitor  164 , and the conductive layer  148   b  functions as the other electrode of the capacitor  164 . Note that the capacitor  164  may be omitted if a capacitor is not needed. Alternatively, the capacitor  164  may be separately provided above the transistor  162 . 
     An insulating layer  152  is provided over the transistor  162  and the capacitor  164 . Further, a wiring  156  for connecting the transistor  162  to another transistor is provided over the insulating layer  152 . Although not illustrated in  FIG. 5A , the wiring  156  is electrically connected to an electrode layer  142   b  through an electrode formed in an opening provided in the insulating layer  150 , the insulating layer  152 , the gate insulating film  146 , and the like. Here, the electrode is preferably provided so as to partly overlap with at least the oxide semiconductor layer  144  of the transistor  162 . 
     In  FIGS. 5A and 5B , the transistor  160  is provided so as to overlap with at least part of the transistor  162 . The source region or the drain region of the transistor  160  is preferably provided so as to overlap with part of the oxide semiconductor layer  144 . Further, the transistor  162  and the capacitor  164  are provided so as to overlap with at least part of the transistor  160 . For example, the conductive layer  148   b  of the capacitor  164  is provided so as to overlap with at least part of the gate electrode  110  of the transistor  160 . With such a planar layout, the area occupied by the semiconductor device can be reduced; thus, higher integration can be achieved. 
     Note that the electrical connection between the electrode layer  142   b  and the wiring  156  may be established by direct contact of the electrode layer  142   b  and the wiring  156  with each other or through an electrode provided in an insulating layer lying therebetween. Alternatively, the electrical connection may be established through a plurality of electrodes. 
     Next, an example of a circuit configuration corresponding to  FIGS. 5A and 5B  is illustrated in  FIG. 5C . 
     In  FIG. 5C , a first wiring (1st Line) is electrically connected to a source electrode of the transistor  160 . A second wiring (2nd Line) is electrically connected to a drain electrode of the transistor  160 . A third wiring (3rd Line) and one of source or drain electrodes of the transistor  162  are electrically connected to each other, and a fourth wiring (4th Line) and a gate electrode of the transistor  162  are electrically connected to each other. A gate electrode of the transistor  160  and one of the source electrode and the drain electrode of the transistor  162  are electrically connected to one electrode of the capacitor  164 . A fifth line (5th Line) and the other electrode of the capacitor  164  are electrically connected to each other. 
     The semiconductor device in  FIG. 5C  utilizes a characteristic in which the potential of the gate electrode of the transistor  160  can be held, and thus enables data writing, holding, and reading as follows. 
     Writing and holding of data are described. First, the potential of the fourth line is set to a potential at which the transistor  162  is turned on, so that the transistor  162  is turned on. Accordingly, the potential of the third line is supplied to the gate electrode of the transistor  160  and the capacitor  164 . That is, predetermined charge is given to the gate electrode of the transistor  160  (writing). Here, one of two kinds of charges providing different potentials (hereinafter referred to as Low level charge and High level charge) is given. After that, the potential of the fourth line is set to a potential at which the transistor  162  is turned off, so that the transistor  162  is turned off. Thus, the charge given to the gate electrode of the transistor  160  is held (storing). 
     Since the off-state current of the transistor  162  is extremely low, the charge of the gate electrode of the transistor  160  is held for a long time. 
     Next, reading of data is described. By supplying an appropriate potential (reading potential) to the fifth line while a predetermined potential (constant potential) is supplied to the first line, the potential of the second line varies depending on the amount of charge held in the gate electrode of the transistor  160 . This is because in general, when the transistor  160  is an n-channel transistor, an apparent threshold voltage V th     —     H  in the case where a high-level charge is given to the gate electrode of the transistor  160  is lower than an apparent threshold voltage V th     —     L  in the case where a low-level charge is given to the gate electrode of the transistor  160 . Here, an apparent threshold voltage refers to the potential of the fifth line, which is needed to turn on the transistor  160 . Thus, the potential of the fifth wiring is set to a potential V 0  which is between V th H  and V th L , whereby charge given to the gate electrode of the transistor  160  can be determined. For example, in the case where a high-level charge is given in writing, when the potential of the fifth wiring is set to V 0  (&gt;V th     —     H ), the transistor  160  is turned on. In the case where a low level charge is given in writing, even when the potential of the fifth wiring is set to V 0  (&lt;V th     —     L ), the transistor  160  remains in an off state. Therefore, the stored data can be read by the potential of the second line. 
     Note that in the case where memory cells are arrayed to be used, only data of desired memory cells needs to be read. In the case where such reading is not performed, a potential at which the transistor  160  is turned off, that is, a potential smaller than V th     —     H  may be given to the fifth wiring regardless of the state of the gate electrode of the transistor  160 . Alternatively, a potential which allows the transistor  160  to be turned on regardless of a state of the gate electrode, that is, a potential higher than V th     —     L  may be applied to the fifth lines. 
     When a transistor having a channel formation region formed using an oxide semiconductor and having extremely small off-state current is applied to the semiconductor device in this embodiment, the semiconductor device can store data for an extremely long period. In other words, power consumption can be adequately reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. Moreover, stored data can be held for a long period even when power is not supplied (note that a potential is preferably fixed). 
     Further, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike a conventional nonvolatile memory, it is not necessary to inject and extract electrons into and from a floating gate, and thus a problem such as deterioration of a gate insulating layer does not occur at all. In other words, the semiconductor device according to one embodiment of the present invention does not have a limit on the number of times of writing which is a problem in a conventional nonvolatile memory, and reliability thereof is drastically improved. Furthermore, data is written or held by turning on or off the transistor, whereby high-speed operation can be easily realized. 
     Further, when the transistor  162  is a transistor including a non-single-crystal oxide semiconductor layer containing at least indium, a Group 3 element, zinc, and oxygen, high performance of the semiconductor device can be achieved. Further, the semiconductor device in this embodiment includes a transistor whose threshold voltage is unlikely to shift even after long-term usage; thus, the semiconductor device can have high reliability. 
     The methods and structures described in this embodiment can be combined as appropriate with any of the methods and structures described in the other embodiments. 
     [Embodiment 5] 
     In this embodiment, a semiconductor device which includes the transistor described in any of Embodiments 1 to 3, which can hold stored data even when not powered, which does not have a limitation on the number of write cycles, and which has a structure different from the structure described in Embodiment 4 is described with reference to  FIGS. 6A and 6B  and  FIGS. 7A to 7C . Note that the transistor  162  included in the semiconductor device in this embodiment is the transistor described in any of Embodiments 1 to 3. Any of the structures of the transistors described in Embodiments 1 to 3 can be employed for the transistor  162 . 
       FIG. 6A  illustrates an example of a circuit configuration of a semiconductor device, and  FIG. 6B  is a conceptual diagram illustrating an example of a semiconductor device. First, the semiconductor device illustrated in  FIG. 6A  is described, and then, the semiconductor device illustrated in  FIG. 6B  is described. 
     In the semiconductor device illustrated in  FIG. 6A , a bit line BL is electrically connected to the source electrode or the drain electrode of the transistor  162 , a word line WL is electrically connected to the gate electrode of the transistor  162 , and the source electrode or the drain electrode of the transistor  162  is electrically connected to a first terminal of a capacitor  254 . 
     The transistor  162  including an oxide semiconductor has extremely low off-state current. For that reason, a potential of the first terminal of the capacitor  254  (or a charge accumulated in the capacitor  254 ) can be held for an extremely long period by turning off the transistor  162 . 
     Next, writing and holding of data in the semiconductor device (a memory cell  250 ) illustrated in  FIG. 6A  are described. 
     First, the potential of the word line WL is set to a potential at which the transistor  162  is turned on, so that the transistor  162  is turned on. Accordingly, the potential of the bit line BL is supplied to the first terminal of the capacitor  254  (writing). After that, the potential of the word line WL is set to a potential at which the transistor  162  is turned off, so that the transistor  162  is turned off. Thus, the charge at the first terminal of the capacitor  254  is held (holding). 
     Because the off-state current of the transistor  162  is extremely small, the potential of the first terminal of the capacitor  254  (or the charge accumulated in the capacitor) can be held for a long time. 
     Next, reading of data is described. When the transistor  162  is turned on, the bit line BL which is in a floating state and the capacitor  254  are electrically connected to each other, and the charge is redistributed between the bit line BL and the capacitor  254 . As a result, the potential of the bit line BL is changed. The amount of change in potential of the bit line BL varies depending on the potential of the first terminal of the capacitor  254  (or the charge accumulated in the capacitor  254 ). 
     For example, the potential of the bit line BL after charge redistribution is (C B ×V B0 +C×V)/(C B +C), where V is the potential of the first terminal of the capacitor  254 , C is the capacitance of the capacitor  254 , C B  is the capacitance of the bit line BL (hereinafter also referred to as bit line capacitance), and V W ) is the potential of the bit line BL before the charge redistribution. Therefore, it can be found that assuming that the memory cell  250  is in either of two states in which the potentials of the first terminal of the capacitor  254  are V 1  and V 0  (V 1 &gt;V 0 ), the potential of the bit line BL in the case of holding the potential V 1  (=(C B ×V B0 +C×V 1 )/(C B +C)) is higher than the potential of the bit line BL in the case of holding the potential V 0  (=(C B ×V B0 +C×V 0 )/(C B +C)). 
     Then, by comparing the potential of the bit line BL with a predetermined potential, data can be read. 
     As described above, the semiconductor device illustrated in  FIG. 6A  can hold charge that is accumulated in the capacitor  254  for a long time because the off-state current of the transistor  162  is extremely low. In other words, power consumption can be adequately reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. Moreover, stored data can be stored for a long time even when power is not supplied. 
     Next, the semiconductor device illustrated in  FIG. 6B  is described. 
     The semiconductor device illustrated in  FIG. 6B  includes a memory cell array  251  (memory cell arrays  251   a  and  251   b ) including a plurality of memory cells  250  illustrated in  FIG. 6A  as memory circuits in the upper portion, and a peripheral circuit  253  in the lower portion which is necessary for operating the memory cell array  251  (the memory cell arrays  251   a  and  251   b ). Note that the peripheral circuit  253  is electrically connected to the memory cell array  251 . 
     In the structure illustrated in  FIG. 6B , the peripheral circuit  253  can be provided under the memory cell array  251  (the memory cell arrays  251   a  and  251   b ). Thus, the size of the semiconductor device can be decreased. 
     It is preferable that a semiconductor material of the transistor provided in the peripheral circuit  253  be different from that of the transistor  162 . For example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor is preferably used. Alternatively, an organic semiconductor material or the like may be used. A transistor including such a semiconductor material can operate at sufficiently high speed. Therefore, a variety of circuits (e.g., a logic circuit or a driver circuit) which needs to operate at high speed can be favorably realized by the transistor. 
     Note that  FIG. 6B  illustrates, as an example, the semiconductor device in which two memory cell arrays (the memory cell array  251   a  and the memory cell array  251   b ) are stacked; however, the number of stacked memory cell arrays is not limited thereto. Three or more memory cell arrays may be stacked. 
     Next, a specific structure of the memory cell  250  illustrated in  FIG. 6A  is described with reference to FIGS.  7 A to  7 C. 
       FIGS. 7A to 7C  illustrate a structure example of the memory cell  250 .  FIG. 7A  is a plan view of the memory cell  250 .  FIG. 7B  is a cross-sectional view taken along line A-B in  FIG. 7A . 
     The transistor  162  in  FIGS. 7A and 7B  can have the same structure as the transistor in any of Embodiments 1 to 3. 
     As illustrated in  FIG. 7B , the transistor  162  is formed over an electrode  502  and an electrode  504 . The electrode  502  serves as a bit line BL in  FIG. 6A  and is in contact with the low-resistance region of the transistor  162 . The electrode  504  serves as one electrode of the capacitor  254  in  FIG. 6A  and is in contact with the low-resistance region of the transistor  162 . Over the transistor  162 , the electrode  506  provided in a region overlapping with the electrode  504  serves as the other electrode of the capacitor  254 . 
     As illustrated in  FIG. 7A , the other electrode  506  of the capacitor  254  is electrically connected to a capacitor line  508 . A gate electrode  148   a  over the oxide semiconductor layer  144  with the gate insulating film  146  provided therebetween is electrically connected to a word line  509 . 
       FIG. 7C  is a cross-sectional view in a connection portion between the memory cell array  251  and the peripheral circuit. The peripheral circuit can include, for example, an n-channel transistor  510  and a p-channel transistor  512 . The n-channel transistor  510  and the p-channel transistor  512  are preferably formed using a semiconductor material other than an oxide semiconductor (e.g., silicon). With such a material, the transistor included in the peripheral circuit can operate at high speed. 
     When the planar layout in  FIG. 7A  is employed, the area occupied by the semiconductor device can be reduced; thus, the degree of integration can be increased. 
     As described above, the plurality of memory cells formed in multiple layers in the upper portion each include a transistor including an oxide semiconductor. Since the off-state current of the transistor including a non-single-crystal oxide semiconductor containing at least indium, a Group 3 element, zinc, and oxygen is low, stored data can be held for a long time owing to the transistor. In other words, the frequency of refresh operation can be significantly lowered, which leads to a sufficient reduction in power consumption. Further, as illustrated in  FIG. 7B , the capacitor  254  is formed by stacking the electrode  504 , the oxide semiconductor layer  144 , the gate insulating film  146 , and the electrode  506 . 
     A semiconductor device having a novel feature can be obtained by being provided with both a peripheral circuit including the transistor including a material other than an oxide semiconductor and a memory circuit including the transistor including an oxide semiconductor. In addition, with a structure where the peripheral circuit and the memory circuit are stacked, the degree of integration of the semiconductor device can be increased. 
     This embodiment can be implemented in combination with any of the other structures described in the other embodiments as appropriate. 
     [Embodiment 6] 
     In this embodiment, examples of application of the semiconductor device described in any of the above embodiments to portable devices such as cellular phones, smartphones, or electronic books will be described with reference to  FIGS. 8A and 8B ,  FIG. 9 ,  FIG. 10 , and  FIG. 11 . 
     In portable devices such as a mobile phone, a smart phone, and an e-book reader, an SRAM or a DRAM is used so as to store image data temporarily. This is because response speed of a flash memory is low and thus a flash memory is not suitable for image processing. On the other hand, an SRAM or a DRAM has the following characteristics when used for temporary storage of image data. 
     In an ordinary SRAM, as illustrated in  FIG. 8A , one memory cell includes six transistors, that is, transistors  801  to  806 , which are driven with an X decoder  807  and a Y decoder  808 . The transistors  803  and  805  and the transistors  804  and  806  each serve as an inverter, and high-speed driving can be performed therewith. However, an SRAM has a disadvantage of large cell area because one memory cell includes six transistors. Provided that the minimum feature size of a design rule is F, the area of a memory cell in an SRAM is generally 100 F 2  to 150 F 2 . Therefore, a price per bit of an SRAM is the most expensive among a variety of memory devices. 
     In a DRAM, as illustrated in  FIG. 8B , a memory cell includes a transistor  811  and a storage capacitor  812 , which are driven with an X decoder  813  and a Y decoder  814 . One cell includes one transistor and one capacitor and thus the area of a memory cell is small. The area of a memory cell of a DRAM is generally less than or equal to 10 F 2 . Note that in the case of a DRAM, a refresh operation is always necessary and power is consumed even when a rewriting operation is not performed. 
     However, the area of the memory cell of the semiconductor device described in the above embodiments is about 10 F 2  and frequent refreshing is not needed. Therefore, the area of the memory cell is reduced, and the power consumption can be reduced. 
     Next,  FIG. 9  is a block diagram of a portable device. The portable device illustrated in  FIG. 9  includes an RF circuit  901 , an analog baseband circuit  902 , a digital baseband circuit  903 , a battery  904 , a power supply circuit  905 , an application processor  906 , a flash memory  910 , a display controller  911 , a memory circuit  912 , a display  913 , a touch sensor  919 , an audio circuit  917 , a keyboard  918 , and the like. The display  913  includes a display portion  914 , a source driver  915 , and a gate driver  916 . The display  913  includes a display portion  914 , a source driver  915 , and a gate driver  916 . The application processor  906  includes a CPU  907 , a DSP  908 , and an interface  909  (IF  909 ). In general, the memory circuit  912  includes an SRAM or a DRAM; by employing the semiconductor device described in any of the above embodiments for the memory circuit  912 , writing and reading of data can be performed at high speed, data can be held for a long time, and power consumption can be sufficiently reduced. 
       FIG. 10  illustrates an example of using the semiconductor device described in any of the above embodiments in a memory circuit  950  for a display. The memory circuit  950  illustrated in  FIG. 10  includes a memory  952 , a memory  953 , a switch  954 , a switch  955 , and a memory controller  951 . Further, in the memory circuit  950 , image data input from a signal line (input image data), a display controller  956  which reads and controls data held in the memories  952  and  953 , and a display  957  which displays data by a signal from the display controller  956  are connected. 
     First, image data (input image data A) is formed by an application processor (not shown). The input image data A is held in the memory  952  through the switch  954 . The image data (stored image data A) held in the memory  952  is transmitted to the display  957  through the switch  955  and the display controller  956  and is displayed on the display  957 . 
     In the case where the input image data A is not changed, the stored image data A is read from the display controller  956  through the memory  952  and the switch  955  at a frequency of 30 Hz to 60 Hz normally. 
     Next, for example, when data displayed on the screen is rewritten by a user (that is, in the case where the input image data A is changed), new image data (input image data B) is formed by the application processor. The input image data B is held in the memory  953  through the switch  954 . The stored image data A is read periodically from the memory  952  through the switch  955  even during that time. After the completion of storing the new image data (the stored image data B) in the memory  953 , from the next frame for the display  957 , the stored image data B starts to be read, transmitted to the display  957   20  through the switch  955  and the display controller  956 , and displayed on the display  957 . This reading operation is continued until another new image data is held in the memory  952 . 
     By alternately writing and reading image data to and from the memory  952  and the memory  953  as described above, images are displayed on the display  957 . Note that the memory  952  and the memory  953  are not limited to separate memories, and a single memory may be divided and used. By employing the semiconductor device described in any of the above embodiments for the memory  952  and the memory  953 , data can be written and read at high speed and held for a long time, and power consumption can be sufficiently reduced. 
       FIG. 11  is a block diagram of an electronic book. The electronic book in  FIG. 11  includes a battery  1001 , a power supply circuit  1002 , a microprocessor  1003 , a flash memory  1004 , an audio circuit  1005 , a keyboard  1006 , a memory circuit  1007 , a touch panel  1008 , a display  1009 , and a display controller  1010 . 
     Here, the semiconductor device described in any of the above embodiments can be used for the memory circuit  1007  in  FIG. 11 . The memory circuit  1007  has a function of temporarily storing the contents of a book. For example, users use a highlight function in some cases. When the user reads an e-book, the user will put a mark on a specific part in some cases. Such a marking function is called a highlighting function, by which characters are changed in color or type, underlined, or bold-faced, for example, so that a specific part is made to look distinct from the other part. In the function, information about the part specified by the user is stored and retained. In the case where the information is stored for a long time, the information may be copied to the flash memory  1004 . Even in such a case, by employing the semiconductor device described in any of the above embodiments, writing and reading of data can be performed at high speed, data can be held for a long time, and power consumption can be sufficiently reduced. 
     As described above, the semiconductor device in any of the above embodiments is mounted on each of the portable devices described in this embodiment. Therefore, it is possible to obtain a portable device which is capable of reading data at high speed, holding data for a long time, and reducing power consumption. 
     The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the other structures, methods, and the like described in the other embodiments. 
     This application is based on Japanese Patent Application serial No. 2011-172157 filed with Japan Patent Office on Aug. 5, 2011, the entire contents of which are hereby incorporated by reference.