Patent Publication Number: US-11664570-B2

Title: Flux-tunable qubit architecture for multiplexing qubit control lines

Description:
BACKGROUND 
     Technical Field 
     The present disclosure generally relates to superconducting devices, and more particularly, to qubit control. 
     Description of the Related Art 
     Superconducting quantum computing is an implementation of a quantum computer in superconducting electronic circuits. Quantum computation studies the application of quantum phenomena for information processing and communication. Various models of quantum computation exist, and the most popular models include the concepts of qubits and quantum gates. A qubit is a generalization of a bit that has two possible states, but can be in a quantum superposition of both states. A quantum gate is a generalization of a logic gate, however the quantum gate describes the transformation that one or more qubits will experience after the gate is applied on them, given their initial state. Various quantum phenomena, such as superposition and entanglement, do not have analogs in the world of classical computing and therefore may involve special structures, techniques, and materials. 
     SUMMARY 
     According to various embodiments, a method and system are provided for multiplexing control lines of a qubit array. A qubit control signal is applied to a single driveline. The qubit control signal on the single driveline is split between a first resonator and a second resonator, wherein the first driveline is operative to control a first qubit, a second tunable qubit, a third qubit, and a fourth tunable qubit. The first qubit is coupled to the second tunable qubit by the first resonator. The third qubit is coupled to the fourth tunable qubit by the second resonator. A variation in amplitude of the qubit control signal is compensated for by adjusting a frequency of the second tunable qubit and/or a frequency of the fourth tunable qubit. A disorder may be, without limitation, a variation in the first qubit&#39;s frequency and/or a variation in a pulse amplitude. 
     In one embodiment, the control line is configured to drive a resonator induced phase (RIP) gate, the first resonator is a RIP resonator, and the second resonator is a RIP resonator. 
     In one embodiment, a calibration of the RIP gate between the first qubit and the second qubit is provided by maximizing a fidelity of the gate while varying a RIP frequency. 
     In one embodiment, the second and fourth tunable qubits are flux-tunable Ancilla qubits operative to modify a frequency difference between the corresponding RIP resonator by changing a quantum state dependent frequency shift χ on the corresponding RIP resonator of the first and second RIP resonators. The frequency of the RIP resonator may depend on the quantum states, the Ancilla and the Data qubit. If both qubits are in a ground state then the frequency of the RIP resonator will not shift. If one, or both qubits are in the excited state, the RIP resonator frequency will shift by χ. 
     The magnitude of the χ shift depends on the frequency different between the Ancilla qubit and the RIP resonator. 
     In one embodiment, a magnitude of the frequency shift χ of the first qubit and second tunable qubit depends on a frequency difference between the second tunable qubit and the first qubit. 
     In one embodiment, a second variation in amplitude of the qubit control signal is compensated for by adjusting a frequency of the fourth tunable qubit. 
     In one embodiment, the qubit control signal is a radio frequency (RF) pulse having a fixed drive amplitude and a fixed frequency. 
     In one embodiment, the splitting is performed by a resistive power splitter, a reactive power splitter, or a multi-port coupler. 
     In one embodiment, the splitting is performed by a Wilkinson resistive power splitter, a Wye power splitter, or a Delta power splitter. 
     In one embodiment, error correction is performed for a surface code architecture by cyclically performing at least one of X-parity and Z-parity. 
     In one embodiment, the first resonator is detuned from the second resonator. A drive frequency of the qubit control signal is moved to a frequency where a gate rate for the first qubit and the second tunable qubit is same as a gate rate for the third qubit and the tunable fourth qubit. 
     According to one embodiment, a quantum structure includes a first qubit, a second tunable qubit coupled to the first qubit via a first resonator, a third qubit, a fourth tunable qubit coupled to the third qubit via a second resonator, and a fixed driveline coupled to the first resonator and the second resonator. The second tunable qubit is configured to be adjusted to compensate for a variation in amplitude of a qubit control signal of the fixed driveline. 
     In one embodiment, the control line carries signals to a resonator to drive a resonator induced phase (RIP) gate. The first resonator is a RIP resonator. The second resonator is a RIP resonator. 
     In one embodiment, the second and fourth tunable qubits are flux-tunable Ancilla qubits configured to modify a quantum state dependent frequency shift χ of its corresponding RIP resonator. 
     In one embodiment, a modification of χ of at least one of the first or third resonators is operative to mitigate a disorder in a pulse amplitude of the qubit control signal. 
     In one embodiment, an adjustment of a frequency of the fourth tunable qubit is operative to compensate for a second variation in amplitude of the qubit control signal. 
     In one embodiment, the qubit control signal is a radio frequency (RF) pulse having a fixed drive amplitude and a fixed frequency. 
     In one embodiment, the splitting is performed by a resistive power splitter, a reactive power splitter, or a multi-port coupler. 
     In one embodiment, there is an RF splitter configured to split a qubit control signal on the fixed single driveline. 
     According to one embodiment, a quantum structure includes a first qubit, a second tunable qubit coupled to the first qubit via a first resonator, a third qubit, a fourth tunable qubit coupled to the third qubit via a second resonator, and a shared driveline coupled to the first resonator and the second resonator. The first resonator is detuned from the second resonator. A drive frequency of a qubit control signal is at a frequency where a gate rate for the first qubit and the second tunable qubit is same as a gate rate for the third qubit and the tunable fourth qubit. The detuning of the first resonator from the second resonator can be performed by way of fabricating the resonators with different dimensions. 
     These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The drawings are of illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be practiced with additional components or steps and/or without all the components or steps that are illustrated. When the same numeral appears in different drawings, it refers to the same or like components or steps. 
         FIG.  1 A  illustrates an example architecture of a quantum computing system, consistent with an illustrative embodiment. 
         FIG.  1 B  provides an example graphical representation of a number of wires used in a quantum system with respect to a logical qubit size, consistent with and illustrative embodiment. 
         FIG.  2    illustrates basic elements of a flux-tunable qubit architecture, consistent with illustrative embodiments. 
         FIG.  3    provides an expansion of the basic elements of  FIG.  2   , consistent with an illustrative embodiment. 
         FIG.  4 A  illustrates a change in θ ZZ  as a function of the change in χ and a change in ε 0 , respectively. 
         FIG.  4 B  illustrates a change in χ as a function of the change in detuning Δ. 
         FIG.  5    provides a conceptual diagram explaining how a qubit is tuned, consistent with an illustrative embodiment. 
         FIGS.  6 A and  6 B  provide diagrams related to using RIP frequency as a knob to multiplex access to multiple qubits, consistent with an illustrative embodiment. 
         FIG.  7    illustrates a gate rate vs. drive frequency of the example of  FIG.  6 A , consistent with an illustrative embodiment. 
         FIG.  8    provides an overview of an example architecture having 17 qubits, where eight are tunable qubits and nine are fixed, consistent with an illustrative embodiment. 
         FIG.  9    illustrates a multiplexed RIP bus driving a first entangling gate, consistent with an illustrative embodiment. 
         FIG.  10    illustrates a multiplexed RIP bus driving a second entangling gate, consistent with an illustrative embodiment. 
         FIG.  11    illustrates a multiplexed RIP bus driving a third entangling gate, consistent with an illustrative embodiment. 
         FIG.  12    illustrates a multiplexed RIP bus driving a fourth entangling gate, consistent with an illustrative embodiment. 
         FIGS.  13 A to  13 D  provide different ways of performing power splitting a qubit control signal, consistent with illustrative embodiments. 
         FIG.  14    presents an illustrative process related to reading out signals from a quantum processor, consistent with an illustrative embodiment. 
         FIG.  15    provides a functional block diagram illustration of a computer hardware platform that can be used to implement a particularly configured computing device that can host a qubit control engine, consistent with an illustrative embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Overview 
     In the following detailed description, numerous specific details are set forth by way of examples to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and/or circuitry have been described at a relatively high-level, without detail, to avoid unnecessarily obscuring aspects of the present teachings. 
     In discussing the present technology, it may be helpful to describe various salient terms. As used herein a qubit represents a quantum bit and a quantum gate is an operation performed on a qubit, such as controlling the super-positioning between two qubits. 
     As used herein, a resonator-induced phase (RIP) gate is a multi-qubit entangling gate. It allows a high degree of flexibility in qubit frequencies, making it appropriate for quantum operations in large-scale architectures. An advantage of the RIP gate is its ability to couple qubits even if they are substantially detuned from each other. Accordingly, a RIP gate can overcome challenges due to constraints on the frequency arrangements of the qubits that may hinder scalability towards larger quantum architectures. The RIP gate is a CZ gate that uses the strong coupling between qubits and a resonator in a quantum system. It can be realized by applying a detuned pulsed microwave drive to a shared bus cavity. 
     As used herein, the term C-phase relates to a controlled phase gate, where a Z rotation of one qubit is defined by the state of another qubit. A ZZ refers to a state dependent qubit interaction that can be used to form a C-phase gate. 
     As used herein, the term flux-tunable relates to a device whose frequency depends on magnetic flux. 
     As used herein, an ancilla qubit relates to a quantum bit that can be used in error correcting protocols to store entangled quantum states. Ancilla can be used in a parity circuit to extract the parity of an entangled state. A parity circuit relates to a quantum circuit used for determining the parity of an entangled state of data qubits. 
     As used herein, a transmon is type of superconducting qubit, in which the charging energy Ec is much smaller than the Josephson energy Ej. 
     As used herein, a driveline relates to a qubit control line that carries signals to the qubit. The term multiplexing includes the meaning of a single control line capable of carrying signals for multiple qubits. 
     Although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     Example embodiments are described herein with reference to schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope. 
     It is to be understood that other embodiments may be used and structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments. 
     As used herein, certain terms are used indicating what may be considered an idealized behavior, such as “lossless,” “superconductor,” “superconducting,” “absolute zero,” which are intended to cover functionality that may not be exactly ideal but is within acceptable margins for a given application. For example, a certain level of loss or tolerance may be acceptable such that the resulting materials and structures may still be referred to by these “idealized” terms. 
     The present disclosure generally relates to superconducting devices, and more particularly, efficient interaction with a lattice array comprising a plurality of qubits. The electromagnetic energy associated with a qubit can be stored in so-called Josephson junctions and in the capacitive and inductive elements that are used to form the qubit. In one example, to read out the qubit state, a microwave signal is applied to the microwave readout cavity that couples to the qubit at the cavity frequency. The transmitted (or reflected) microwave signal goes through multiple thermal isolation stages and low-noise amplifiers that are used to block or reduce the noise and improve the signal-to-noise ratio. Alternatively, or in addition, a microwave signal (e.g., pulse) can be used to entangle one or more qubits. Much of the process is performed in a cold environment (e.g., in a cryogenic chamber), while the microwave signal of a qubit is ultimately measured at room temperature. The amplitude and/or phase of the returned/output microwave signal carries information about the qubit state, such as whether the qubit has dephased to the ground or excited state. The microwave signal carrying the quantum information about the qubit state is usually weak (e.g., on the order of a few microwave photons). To measure this weak signal with room temperature electronics (i.e., outside the refrigerated environment), low-noise quantum-limited amplifiers (QLAs), such as Josephson amplifiers and travelling-wave parametric amplifiers (TWPAs), may be used as preamplifiers (i.e., first amplification stage) at the output of the quantum system to boost the quantum signal, while adding the minimum amount of noise as dictated by quantum mechanics, in order to improve the signal to noise ratio of the output chain. In addition to Josephson amplifiers, certain Josephson microwave components that use Josephson amplifiers or Josephson mixers such as Josephson circulators, Josephson isolators, and Josephson mixers can be used in scalable quantum processors. 
     A qubit system may include one or more readout resonators coupled to the qubit. A readout resonator may be a transmission line that includes a capacitive connection to ground on one side and is either shorted to the ground on the other side, such as for a quarter wavelength resonator, or may have a capacitive connection to ground, such as for a half wavelength resonator, which results in oscillations within the transmission line, with the resonant frequency of the oscillations being close to the frequency of the qubit. For example, the readout resonator affects a pulse coming from the control/measurement instruments at the readout resonator frequency. The pulse acts as a measurement that decoheres the qubit and makes it collapse into a state of “one” or “zero,” thereby imparting a phase shift on that measurement pulse. 
     Between qubits there may be a coupling resonator, sometimes referred to herein as a coupler resonator or RIP bus, which allows coupling different qubits together in order to realize quantum logic gates. The coupling resonator is typically structurally similar to the readout resonator. However, more complex designs are possible. When a qubit is implemented as a transmon, each side of the coupling resonator is coupled (e.g., capacitively or inductively) to a corresponding qubit by being in adequate proximity to (e.g., the capacitor of) the qubit. Since each side of the coupling resonator has coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator (e.g., RIP bus). In this way, there is mutual interdependence in the state between coupled qubits, thereby allowing a coupling resonator to use the state of one qubit to control the state of another qubit. Entanglement occurs when the interaction between two qubits is such that the states of the two cannot be specified independently, but can only be specified for the whole system. In this way, the states of two qubits are linked together such that a measurement of one of the qubits, causes the state of the other qubit to collapse. 
     The ability to include more qubits is salient to being able to realize the potential of quantum computers. Generally, performance increases as temperature is lowered, for example by reducing the residual thermally-excited state qubit population and decreasing the thermal broadening of the qubit transition frequencies. Accordingly, the lower the temperature, the better for a quantum processor. 
     It has been determined that to increase the computational power and reliability of a quantum computer, improvements are needed along two main dimensions. First, is the qubit count itself. The more qubits in a quantum processor, the more states can in principle be manipulated and stored. Second is low error rates, which is relevant to manipulate qubit states accurately and perform sequential operations that provide consistent results and not merely unreliable data. Thus, to improve fault tolerance of a quantum computer, a large number of physical qubits should be used to store a logical quantum bit. In this way, the local information is delocalized such that the quantum computer is less susceptible to local errors and the performance of measurements in the qubits&#39; eigenbasis, similar to parity checks of classical computers, thereby advancing to a more fault tolerant quantum bit. 
     In one aspect, the teachings herein are based on Applicants&#39; insight that directly applying conventional integrated circuit techniques for interacting with computing elements to superconducting quantum circuits may not be effective because of the unique challenges presented by quantum circuits that are not presented in classical computing architectures. Accordingly, embodiments of the present disclosure are further based on recognition that issues unique to quantum circuits have been taken into consideration when evaluating applicability of conventional integrated circuit techniques to building superconducting quantum circuits, and, in particular, to electing methods and architectures used for interacting efficiently with qubits. 
     Example Architecture 
       FIG.  1 A  illustrates an example architecture  100  of a quantum computing system, consistent with an illustrative embodiment. The architecture  100  includes a quantum processor  112  comprising a plurality of qubits  114 . The quantum processor  112  is located in a refrigeration unit  110 , which may be a dilution refrigerator. A dilution refrigerator is a cryogenic device that provides continuous cooling to temperatures typically in and around 10 mK. Most of the physical volume of the architecture  100  is due to the large size of the refrigeration unit  110 . To reach the near-absolute zero temperatures at which the system operates, the refrigeration unit  110  may use liquid helium as a coolant. 
     There is a measurement and control unit  130  that is outside of the refrigeration unit  110 . The measurement and control unit  130  is able to communicate with the quantum processor through an opening  116 , sometimes referred to as a bulkhead of the dilution refrigerator  110 , that also forms a hermetic seal separating the ambient atmospheric pressure from the vacuum pressure of the cryostat under operation. A practical challenge in known refrigeration devices that house qubits  114  is that the number of qubits that can be accommodated in the refrigeration unit is limited due the number of wires between the measurement and control unit  130  and the qubits  114  measured/controlled thereby. 
     As the number of qubits  114  increases, for example to hundreds, thousands, or more, the opening  116  may not be large enough to accommodate all the lines  120  supporting the quantum processor  112  in the dilution refrigerator  110 . Stated differently, access to the vacuum environment of the dilution refrigerator  110  is limited to the number of connectors that can fit through the bulkhead opening  116 . Known architectures, where a bus is driven to produce two qubit gates, typically involve a factor of two more control lines than the cross-resonance gate discussed herein, thereby making higher scaling impractical. 
     Accordingly, in one aspect, what is provided herein is an architecture that substantially reduces the number of lines between a measurement and control unit  130  and a quantum processor  112  that is housed in a refrigerated environment. Multiple qubits  114  of the quantum processor  112  can be accessed by way of multiplexing drivelines, which reduces the number of qubit control lines to perform an error correction protocol. The concepts discussed herein provide an architecture and method that minimizes the number of drivelines used to control a quantum processor  112 . In one aspect, two qubits are coupled together by a resonator. Driving the resonator with an RF pulse drives a two qubit C-phase gate. One of those two qubits is flux tunable, which facilitates adjustment of the qubit frequency and aligns the frequency with a radio frequency (RF) pulse that drives the two-qubit gate. 
     As mentioned above, the teachings herein facilitate a substantial reduction in the number of wires that are used between a refrigerated environment  110  and measurement and control equipment  130 . In this regard  FIG.  1 B  provides an example graphical representation of the number of wires used in a quantum system with respect to a logical qubit size, consistent with and illustrative embodiment. A disadvantage of an architecture where the bus involves a drive tone (e.g., such as RIP) is that there is an extra driveline used for each bus, represented by the dashed line in  FIG.  1 B . For example, the number of bus lines for a distance d surface code is provided by the equation below:
 
 N   bus lines =4 d   2 −4 d   (Eq. 1)
 
     Accordingly, for a 1000 qubit system d˜23, the total number of lines is &gt;3000 for traditional systems. In contrast, by using an ancilla based on the teachings herein, although an additional line is provided for tunability, there are only 4 total RIP lines, represented by the dashed-dot line in  FIG.  1 B . 
     In one embodiment, the calculations for a number of RIP lines is based on the size of logical qubit d. The following expressions provide some relationships for different parameters: 
     The number of physical qubits is:
 
 N   Physical Q =2 d   2 −1  (Eq. 2)
 
     The number of ancilla qubits is:
 
 N   Ancilla Q   =d   2 −1  (Eq. 3)
 
     The number of data qubits is:
 
 N   Data Q   =d   2   (Eq. 4)
 
     The number of bus connections is:
 
 N   Bus =4 d   2 −4 d   (Eq. 5)
 
     There are substantially more bus connections and each bus involves its own RIP drive line. In this example architecture, the total number of bus connections is reduced to 4. However, the number of ancilla drive lines is increased by a factor of 2. Each ancilla qubit involves a single qubit RF drive line, and it involves a drive line for flux tuning. There are significantly more bus connections that than there are Ancilla qubits. 
     The number of after multiplexing drive lines is:
 
 N   Drive Lines   =N   Data Q +2 N   Ancilla Q +4=3 d   2 +2  (Eq. 6)
 
     Thus, even after doubling the number of ancilla lines, we still have fewer drive lines than a case where there is one drive-line per bus. By virtue of using the teachings herein, there is one driveline per qubit, represented by the solid line in  FIG.  1 B , thereby substantially reducing the number of lines to the refrigerated environment. 
     In one aspect, the concepts discussed herein are scalable in that the architecture allows the splitting of the RF tone, sometimes referred to herein as the flux pulse or the qubit control signal, and driving multiple resonators with the same RF tone. The variation in the RF tone can be mitigated by adjusting the flux tunable qubit frequency. These concepts are discussed in more detail below. 
     Example Basic Elements 
     Reference now is made to  FIG.  2   , which illustrates basic elements of a flux-tunable qubit architecture, consistent with illustrative embodiments. In particular,  FIG.  2    illustrates a fixed frequency qubit  202  as well as a tunable ancilla qubit  204 , sometimes referred to herein simply as a tunable qubit.  FIG.  2    also illustrates a basic flux-tunable qubit element  206  comprising a fixed frequency qubit Q d    211  and a tunable ancilla Q tune    213 , which are coupled together by a RIP bus  214  having a first frequency f 1 . The first qubit Q d  and the second tunable qubit Q tune  can be entangled by a pulse  220 . For example, a fixed frequency RIP (e.g., radio frequency (RF)) pulse  220  can drive a two-qubit gate by way of the fixed frequency qubit Q d  ( 211 ) and the tunable qubit Q tune  ( 213 ) via the RIP bus  214  having a first frequency f 1 . In this way, first qubit Q d    211  and the second tunable qubit Q tune    213  can be entangled. The theory for a RIP device can be better understood in view of the following expression, which assumes that assumes χ for each qubit is the same: 
     
       
         
           
             
               
                 
                   
                     
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     Where:
         Δ=ω d −ω r ;   {dot over (θ)} is the ZZ rotation rate (i.e., the frequency offset of a qubit that is dependent on the state of the other qubit); and   {tilde over (ε)} 0  is a fixed drive amplitude.       

     Applicants have determined that two of these basic elements  206  can be combined to provide a multiplexed basic flux-tunable qubit element  208 . The tunable qubit Q tune  (e.g.,  221  and/or  219 ) is a tunable ancilla. Variations in the RIP pulse frequency and/or the frequency of the fixed frequency qubit Q d  (e.g.,  209 ) can be compensated for with the tunable qubit Q tune  (e.g.,  221 ). Stated differently, the tunable qubit Q tune  can be adjusted to calibrate the gate to the fixed RIP pulse  222 . 
     In the proposed architecture of the multiplexed basic flux tunable element  208 , the flux tunable qubit Q tune  (e.g.,  221  and/or  219 ) can be used to vary χ of equation 1 above by applying a flux pulse  222  on the ancilla qubit Q tune    221  and/or  219 . This tunes the ancilla qubit Q tune  (e.g.,  221 ) to get a certain desired frequency difference between the two qubits. This sequence modifies ↔ of equation 1 above, and allows for the calibration of a fixed drive amplitude {tilde over (ε)} 0 . Accordingly, any variations in the signal propagating on the fixed driveline  230  (i.e., going to the first RIP resonator  216  and the second RIP resonator  218 ) can be adjusted by the corresponding tunable qubit Q tune    221  and/or Q tune    219 . In this way, the amount of entanglement between a qubit (e.g.,  209 ) and its corresponding tunable qubit (e.g.,  221 ) can be controlled. 
     The multiplexed basic flux tunable element  208  is less susceptible to various types of disorders because of the flux-tunability of Q tune . Example disorders mitigated by the multiplexed basic flux tunable element  208  include a disorder in the amplitude of the RIP drives {tilde over (ε)} 0 . Further, fabrication process that may lead to a disorder in the data qubit frequency ω d , as well as the RIP resonator frequency ω r , are mitigated by the teachings herein. 
     Example Expansion of Basic Elements 
     Reference now is made to  FIG.  3   , which provides an expansion of the basic elements of  FIG.  2   , consistent with an illustrative embodiment. A basic flux-tunable qubit element  206  and a multiplexed basic flux-tunable qubit element  308  are repeated in  FIG.  3    as a reference to structures that are expanded thereon to provide multiplex capability. More particularly,  FIG.  3    illustrates an example element for a single parity check  306  comprising a plurality of fixed qubits  322  to  328  coupled to a common tunable qubit  310 . In structure  306 , each fixed frequency qubit (e.g.,  322  to  328 ) is coupled to the tunable qubit  310  via a RIP bus (sometimes referred to herein as a coupling resonator) having a different frequency (e.g., f 1  to f 4 ). For example, qubit Q d    322  is coupled to a RIP bus having a first frequency f 1 , qubit Q d    324  is coupled to a RIP bus having a second frequency f 2 , qubit Q d    326  is coupled to a RIP bus having a third frequency f 3 ; and qubit Q d    328  is coupled to a RIP bus having a fourth frequency f 4 . In one embodiment, the difference between the frequencies of the RIP busses f 1  to f 4  is 100 Mhz or more. 
     The tunable qubit  310  can be sequentially adjusted to perform a gate with qubit Q d .  322 , then re-tuned to perform a gate with qubit Q d .  324 , then re-tuned to perform a gate with the qubit Q d .  328 , and so on. While four fixed frequency qubit devices have been shown by way of example in the basic element  306 , it will be understood that any number of fixed frequency qubits can be coupled to a tunable qubit Q tune , each having a RIP bus of a different frequency. The basic element for a single parity check  306  can be expanded for multiple parity checks while maintaining a fixed number of RIP buses. In this regard,  FIG.  3    illustrates an expansion of multiplexed elements for multiple parity checks  310 , where additional fixed frequency qubits Q d    330  and Q d    332  are included in the array via shared Q tune    352 . Fixed frequency qubits Q d    324  and Q d    328  are both shared (e.g., accessible) by both tunable qubits Q tune    310  and Q tune    352 . Accordingly, multiple qubits having a same qubit frequency can be accessed concurrently. For example, the qubits coupled to RIP busses having a first frequency f 1  could all be accessed at a same time, as they share the same RF line, thereby substantially reducing a number of wires used in the refrigerated environment. For simplicity and to avoid clutter, a lattice of six fixed qubits Q d  and two tunable qubits Q tune  have been shown in structure  310 . It will be understood that any size lattice is supported by the teachings herein. 
     Example Graphs 
     As discussed above, the teachings herein can mitigate various disorders. To that end,  FIGS.  4 A and  4 B  illustrate how a 1% change in the RIP pulse amplitude can be compensated for by a 40% change in chi. If the control lines going to each RIP resonator had slightly different transmission properties, then each resonator would experience a different amplitude electric field. More specifically,  FIG.  4 A  illustrates a change in θ ZZ  as a function of the change in χ and a change in ε 0 , respectively. The frequency of the RIP resonator depends on the quantum states the ancilla and the data qubit. If both qubits are in a ground state, then the frequency of the RIP resonator will not shift. If one, or both qubits are in the excited state, the RIP resonator frequency will shift by χ. The magnitude of the χ shift depends on the frequency different between the ancilla qubit and the RIP resonator. 
       FIG.  4 B  illustrates a change in   as a function of the change in detuning Δ. For example, the detuning is changed by 30%. For example, the flux tunable qubit is being detuned from the frequency of the RIP resonator. The change is in reference to the detuning (i.e., a change in frequency). Accordingly,  FIGS.  4 A and  4 B  provide a working range. 
       FIG.  5    provides a conceptual diagram explaining how a qubit is tuned, consistent with an illustrative embodiment. More particularly, graph  500  illustrates a normalized tunable qubit frequency. There is a RIP pulse  504  that is applied during a tuning phase of a tunable qubit  502  that compensates for the disorders discussed herein, including disorders from qubit frequencies, resonator, amplitude of the pulse when split, etc. The RIP pulse is applied to perform a two-qubit gate (e.g., entangling the fixed frequency qubit with a tunable qubit (e.g., ancilla). Regarding waveform  502 , it illustrates the change in frequency of the qubit over time. While the qubit is tuned to the higher frequency, there is a window that we can apply the RIP pulse shown in  504  to generate entanglement. The change in frequency of the qubit displayed in waveform  502  may be achieved in practice by applying a flux to the tunable qubit. Accordingly, the dashed lines between  502  and  500  illustrate that these changes in frequency are connected to changes in flux. 
     Additional Embodiment 
       FIGS.  6 A and  6 B  provide diagrams related to using RIP frequency as a knob to multiplex access to multiple qubits, consistent with an illustrative embodiment. Two different RIP resonant buses (i.e., R 1  and R 2 ) in  FIG.  6 A  that connect qubits Q 1  to Q 4 , respectively, are driven using a shared driveline  602 .  FIG.  6 B  illustrates that the RIP resonators R 1  and R 2  are deliberately detuned from each other. In this way, we can drive in between the two resonators  610 . Stated differently, a two-qubit gate can be applied between Q 1 -Q 2  concurrently with Q 3 -Q 4 . In this way, an RF pulse can be applied to both RIP resonators concurrently that are between the frequencies of the two resonators, thereby expediting phase accumulation. 
     This concept may be better understood in view of  FIG.  7   , which illustrates a gate rate vs. drive frequency of the example of  FIG.  6 A , consistent with an illustrative embodiment. Curve  702  represents qubits Q 1  and Q 2  of  FIG.  6 A , whereas curve  704  represents qubits Q 3  and Q 4  of  FIG.  6 A . For example, curve  702  represents the gate rate, or rate of entanglement generation, between qubits Q 1  and Q 2 , and curve  704  represents the gate rate between qubits Q 3  and Q 4  as a function of the frequency of the RIP drive applied concurrently to R 1  and R 2 . Since the gate rate falls off with the detuning, we can move the drive frequency and find a place where the gate rate for Q 1 , Q 2  is the same as Q 3 , Q 4 , represented by point  706  at approximately 7.11 GHz in  FIG.  7   . 
     As illustrated, the ZZ rate as function of drive frequency is plotted  704  for R 1  at 6 GHz and R 2  at 6.2 GHz. Near 6.11 GHz, gate speeds on R 1  and R 2  are equal. Accordingly, the two gates can be driven in parallel. It should be noted that in scenarios where we want to only do a gate on Q 1  and Q 2  (but not Q 3  and Q 4 ) we can split the gate into two parts and use an echo sequence to remove the ZZ accumulation on Q 3  and Q 4 . As mentioned previously, ZZ represents a state dependent qubit interaction that can be used to form a C phasegate . It should be noted that, as used herein, the terms ZZ rate, gate rate, or rate of entanglement generation are all interchangeable. The 2-qubit operation we are trying to achieve happens over a period of time. The inverse of the time to complete the operation is the ‘rate’ of the operation. 
     Example Embodiments 
       FIG.  8    provides an overview of an example architecture having 17 qubits, where eight are tunable qubits (represented by qubits annotated with Qa) and nine are fixed qubits (represented by qubits annotated with Q d ), consistent with an illustrative embodiment. In one embodiment, the architecture of  FIG.  8    can be used in the context of a surface code type device where X and Z parity checks  802  and  804  are performed. For example, the X-parity check  802  checks the phase, whereas the Z-parity check  804  checks the state (e.g., up or down). 
       FIG.  8    illustrates an architecture supporting four separate RIP busses f 1  to f 4 . All RIP busses having a same frequency can be driven concurrently during an error correction cycle. To that end,  FIGS.  9  to  12    illustrate different RIP busses being activated at different stages (e.g., time periods) during a parity check. More particularly,  FIGS.  9  to  12    illustrate a multiplexed RIP bus driving a first, second, third, and fourth entangling gate, respectively, consistent with an illustrative embodiment. For example, referring to  FIG.  9   , when a RIP pulse  904  of a first frequency f 1  is generated on fixed drive-line  906 , all RIP buses having a same frequency f 1  can be driven concurrently during an error correcting cycle. Similarly, in  FIG.  10   , when a RIP pulse  1004  of a second frequency f 2  is generated on a separate fixed drive-line  1006 , all RIP buses having a same frequency f 2  can be driven concurrently during an error correcting cycle. The operation of the multiplexed RIP bus of  FIGS.  11  and  12   , driving a third entangling gate and a fourth entangling gate, respectively, is substantially similar to that of  FIGS.  9  and  10   , and therefore not repeated here for brevity. In one embodiment, the operation depicted in  FIGS.  9  to  12    can be run repeatedly in a cycle in the context of performing X and Z parity checks. 
     Example Power Splitters 
     As discussed above, functions relating to multiplexing RIP drive signals involve splitting of a qubit control signal into two or more paths. To that end,  FIGS.  13 A to  13 D  provide different ways of performing power splitting that can be used to split a qubit control signal. More specifically,  FIG.  13 A  illustrates a 2-way Wilkinson power splitter;  FIG.  13 B  illustrates a 3-way Wilkinson power splitter; and  FIG.  13 C  illustrates an N-way Wilkinson power splitter. In some embodiments, the power is not split immediately in a first stage but split in progressive stages, as illustrated in  FIG.  13 D . 
     Example Process 
     With the foregoing overview of the example architectures, it may be helpful now to consider a high-level discussion of an example process. To that end,  FIG.  14    presents an illustrative process related to reading out signals from a quantum processor. Processes  1400  is illustrated as a collection of blocks, in a logical flowchart, which represents a sequence of operations that can be implemented in hardware, software, or a combination thereof. In the context of software, the blocks represent computer-executable instructions that, when executed by one or more processors, perform the recited operations. Generally, computer-executable instructions may include routines, programs, objects, components, data structures, and the like that perform functions or implement abstract data types. In each process, the order in which the operations are described is not intended to be construed as a limitation, and any number of the described blocks can be combined in any order and/or performed in parallel to implement the process. For discussion purposes, the process is described with reference to the architecture of the multiplexed basic element  208  of  FIG.  2   . 
     At block  1402 , a qubit control signal  222  is applied to a single driveline  223 . 
     At block  1404 , the qubit control signal on the single driveline is split between a first resonator  216  and a second resonator  218 , wherein the single driveline  223  is operative to control a first qubit  209 , a second tunable qubit  211 , a third qubit  217 , and a fourth tunable qubit  219 . 
     At block  1406 , the first qubit  209  is coupled to the second tunable qubit  211  by the first resonator  216 . 
     At block  1408 , the third qubit  217  is coupled to the fourth tunable qubit  219  by the second resonator  218 ; and 
     At block  1410 , a variation in amplitude of the qubit control signal is compensated by adjusting a frequency of the second tunable qubit  211 . 
     In one embodiment, at block  1412 , further compensation is provided for a variation in amplitude of the qubit control signal by adjusting a frequency of the fourth tunable qubit  219 . 
     In some embodiments, the flow of process  1400  may be repeated cyclically. 
     Example Computer Platform 
     As discussed above, functions relating to interacting with qubits by way of measurement and control signals may include a measurement and control unit, as shown in  FIG.  1 A .  FIG.  15    provides a functional block diagram illustration of a computer hardware platform  1500  that can be used to implement a particularly configured computing device that can host a qubit control engine  1540 . In particular,  FIG.  15    illustrates a network or host computer platform  1500 , as may be used to implement an appropriately configured computing device, such as the measurement and control block  130  of  FIG.  1   . 
     The computer platform  1500  may include a central processing unit (CPU)  1504 , a hard disk drive (HDD)  1506 , random access memory (RAM) and/or read only memory (ROM)  1508 , a keyboard  1510 , a mouse  1512 , a display  1514 , and a communication interface  1516 , which are connected to a system bus  1502 . 
     In one embodiment, the HDD  1506 , has capabilities that include storing a program that can execute various processes, such as the qubit control engine  1540 , in a manner described herein. The qubit control engine  1540  may have various modules configured to perform different functions. For example, there may be a control module  1542  that is operative to send control signals to the qubit. There may be a measurement module  1544  operative to perform functions to receive feedback from the qubits discussed herein. There may be a multiplex module  1548  that is configured to provide the multiplex control signals discussed herein. 
     In one embodiment, a program, such as Apache™, can be stored for operating the system as a Web server. In one embodiment, the HDD  1506  can store an executing application that includes one or more library software modules, such as those for the Java™ Runtime Environment program for realizing a JVM (Java™ virtual machine). 
     CONCLUSION 
     The descriptions of the various embodiments of the present teachings have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. 
     While the foregoing has described what are considered to be the best state and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all applications, modifications and variations that fall within the true scope of the present teachings. 
     The components, steps, features, objects, benefits and advantages that have been discussed herein are merely illustrative. None of them, nor the discussions relating to them, are intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, magnitudes, sizes, and other specifications that are set forth in this specification, including in the claims that follow, are approximate, not exact. They are intended to have a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they pertain. 
     Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional, and/or different components, steps, features, objects, benefits and advantages. These also include embodiments in which the components and/or steps are arranged and/or ordered differently. 
     Aspects of the present disclosure are described herein with reference to a flowchart illustration and/or block diagram of a method, apparatus (systems), and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions. 
     These computer readable program instructions may be provided to a processor of an appropriately configured computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks. 
     The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks. 
     The call-flow, flowchart, and block diagrams in the figures herein illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions. 
     While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term “exemplary” is merely meant as an example, rather than the best or optimal. Except as stated immediately above, nothing that has been stated or illustrated is intended or should be interpreted to cause a dedication of any component, step, feature, object, benefit, advantage, or equivalent to the public, regardless of whether it is or is not recited in the claims. 
     It will be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein. Relational terms such as first and second and the like may be used solely to distinguish one entity or action from another without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “a” or “an” does not, without further constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element. 
     The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.