Patent Publication Number: US-4322694-A

Title: Crystal oscillator implemented with CMOS technology

Description:
This is a divisional of application Ser. No. 868,432, filed Jan. 10, 1978, now abandoned, which is a divisional of application Ser. No. 760,522, filed Jan. 19, 1977 and now U.S. Pat. No. 4,091,338. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to CMOS amplifiers useful for crystal oscillators. 
     In the past, a CMOS analog amplifier as illustrated in FIG. 1 was employed as an amplifier in crystal oscillators for a variety of electronic apparatuses for example solid state wristwatches to fulfill low power consumption requirements. The amplifier includes a basic inverter consisting of a P-channel MOS transistor P and an N-channel MOS transistor N, and a resistor R f  of a high resistance value connected between an input terminal V in  and an output terminal V out  of the complementary MOS inverter for biasing purposes. Advantageously, the circuit exhibits high gain, low power dissipation performance characteristics while retaining simple circuit construction. 
     Nevertheless, one difficulty is experienced in reducing the output impedance in the vicinity of the operating center of the CMOS inverter. If the output impedance is forced into a low impedance state, there is a requirement that the mutual conductance of the P-channel and N-channel MOS transistors be increased while the threshold level voltage V th  thereof be decreased. Those requirements result in an increase in dissipation of current. In addition, because the output impedance is constructed by active elements such as MOS transistors, the output impedance is greatly varied in accordance with input and output potential levels, power supply voltages, temperatures, etc. 
     FIG. 2 depicts interrelation among an input voltage V in , an output voltage V out , output impedance R out , current I c  flowing through P- and N- MOS transistors when supplied with a voltage (V DD  -V SS ), which occur within the CMOS analog amplifier of FIG. 1. 
     The graph (I) in FIG. 2 shows a V in  -V out  characteristic of a conventional CMOS transistor, indicating that V in  is biased at the substantially same as V out  via the bias resistor R f  and thus the CMOS operating center V coc  is given. The graph (II) shows the dependency of the output impedance R out  upon variations in the output voltage V out , indicating that R out  tends to take a maximum at the operating center V coc  and reduce when the power supply potential approximates either V DD  or V SS . Analysis of the graph (II) also reveals the fact that a reduction in the power supply voltage (V DD  -V SS ) and a temperature rise permit the output impedance R out  to be increased as suggested by the curves (1) and (2). 
     The graph (III) shows variations in the current I c  flowing through the CMOS when supplied with (V DD  -V SS ), as a function of the input potential V in . While the current I c  has a peak at the operating center, the same is correspondingly reduced in accordance with a degree of deviation from the operating center V coc . 
     FIG. 3 shows an example wherein the above discussed type of the amplifier is applied to timekeeping crystal oscillators having a frequency of about 32.768 KHz. A quartz resonator is denoted as X and phase shifting or frequency adjustment capacitors are denoted as C 1  and C 2 . When the crystal impedance value (hereinafter referred to as the CI of the quartz resonator X is relatively small (typically, in the order of several tens KΩ), the crystal oscillator of FIG. 3 is satisfactory for practical use of timekeeping devices. The critical conditions for practical use of timekeeping devices are that changes in oscillation frequency due to power supply voltage change Δf/f.V be below 1.0 sec/day.V, dissipation of current under a voltage supply of 1.6 V be below 5 μA, the lowest oscillation initiating voltage be below 1.4 V and the oscillation initiating period be within 8 seconds. 
     However, if CI of the quartz resonator X is increased beyond 100 KΩ, the circuit of FIG. 1 can fulfill these requirements no longer. In the event that CI is several hundred KΩ, oscillation will be very difficult. It is believed that this is caused by the above disadvantages mentioned with respect to the CMOS analog amplifier of FIG. 1. 
     In a characteristic diagram of FIG. 2, the difficulty in reducing the output impedance Romax in the vicinity of the operating center V coc  causes the period of time required for initiating oscillation to be considerably longer because it is difficult to excite the quartz resonator in order to initiate oscillation. In addition, the difficulty in reducing the average of the output impedance R out  implies an increase in the oscillation initiating voltage is required. 
     The greater the variations in the output impedance R out  of the amplifier as a function of power voltage variations, the greater the regulation of the oscillation frequency. Although silver batteries recommended for use in solid state wristwatches can provide a comparatively stable discharge voltage when loaded with a light-load, their temperature dependencies vary from battery to battery to thereby adversely effect the performances of the oscillator. 
     When the CI of the quartz resonator is increased in this way, the attenuation factor of a feed-back system including a phase shifter is correspondingly increased. As a consequence, the difficulty in initiating oscillation is still not avoided since the maximum and average of the output impedance R out  of the amplifier remain unchanged at their high values. 
     Accordingly, it is a primary object of the present invention to provide an improved amplifier suited for effectively exciting quartz resonators of relatively high CI, which has the advantage of comparatively high gain, comparatively low output impedance, minimized variations in output impedance, and minimized power dissipation. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     Other objects and novel features of the present invention are set forth in the appended claims and the present invention as to its organization and its mode of operation will best be understood from a consideration of the following detailed description of the preferred embodiments taken in connection with the accompanying drawings, wherein: 
     FIG. 1 is a circuit diagram of a prior art CMOS analog amplifier; 
     FIG. 2 is a graph showing the operating characteristics of the analog amplifier of FIG. 1; 
     FIG. 3 is a circuit diagram of an example of applications of the analog amplifier of FIG. 1; P FIG. 4 is a circuit diagram of one preferred form of an analog amplifier constructed in accordance with the present invention; 
     FIGS. 5(a), 5(b), 5(c) and 5(d) are circuit diagrams of examples of the essential implementations of the circuit of FIG. 4; 
     FIG. 6 is a graph showing operating characteristics of the example shown in FIG. 5(a); 
     FIG. 7 is a circuit diagram of another preferred form of the present invention; 
     FIG. 8 is a graph showing operating characteristics of the circuit of FIG. 7 for illustration of operation; 
     FIG. 9 is a circuit diagram of an example of application of the present invention; 
     FIG. 10 is a graph showing operating characteristics of the embodiment of FIG. 7; 
     FIG. 11 is a circuit diagram of still another preferred form of the present invention; 
     FIG. 12 is a circuit diagram of another preferred form of the present invention; 
     FIG. 13 is a circuit diagram of a resistor load MOS amplifier; 
     FIG. 14 is a graph showing operating characteristics of the amplifier of FIG. 13; 
     FIG. 15 is a circuit diagram of one preferred form of the present invention utilizing the resistor-loaded MOS amplifier; 
     FIG. 16 is a circuit diagram of another preferred form of the present invention utilizing the resistor-loaded MOS amplifier; 
     FIG. 17 is a graph of characteristic curves for the purpose of illustration of operation of the embodiments of FIGS. 15 and 16; 
     FIG. 18 is a circuit diagram of a multi-stage amplifier utilizing the portion of the circuit of FIG. 16; 
     FIG. 19 is a circuit diagram of an oscillator utilizing the multi-stage amplifier of FIG. 18; 
     FIG. 20 is a graph showing frequency characteristic of the amplifier of FIG. 9; 
     FIG. 21 is a circuit diagram of one preferred form of the present invention effective to improve the frequency characteristic of FIG. 20; 
     FIG. 22 is a circuit diagram of an oscillator incorporating the embodiment of FIG. 21 thereinto; and 
     FIGS. 23 and 24 are graphic representations of operating characteristics of the circuit of FIG. 22. 
    
    
     DETAILED DESCRIPTION OF INVENTION 
     Attention is initially called to FIG. 4 of the drawings which illustrates a basic construction of an amplifier embodying the present invention. A CMOS analog amplifier having high gain and low power consumption properties as briefly described above is provided at its output with an impedance converter IC which has a considerably higher input impedance and a considerably lower output impedance, for the purposes of reducing the output impedance of the CMOS analog amplifier. The resulting circuit arrangement assures low output impedance and low power consumption while keeping the high gain properties of the CMOS scheme. 
     The impedance converter IC may take a variety of forms some of which are shown in FIGS. 5(a) through 5(d). 
     In case where the basic circuit construction is in the form of CMOS as described above, a MOSFET follower as suggested in FIG. 5(a) is most beneficial because of its simplicity of integrated circuit manufacture. However, when taking only the function of the impedance converter into account, a junction type FET of FIG. 5(b), or bipolar transistors of FIGS. 5(c) and 5(d) may be equally applicable. In any case, since the output impedance of the CMOS analog amplifier is considerably high, it is recommended that the input impedance of the impedance converter IC be as high as possible. To this end, for the emitter follower of FIG. 5(c) β should be as high as possible. In case of FIG. 5(d), a Darlington Connection may be used. Moreover, super-β transistors may be employed. Other elements may be employed as far as they do not interfere with the performances of the impedance converter. In the case of FET&#39;s, P-channel or N-channel enhancement mode or depletion mode FET&#39;s are optionally selectable. In the case of bipolar transistors, either PNP type or NPN type transistors may be useful. 
     In the examples of FIGS. 5(a) through 5(d) there is provided a resistor R as a passive element at their output portions. This causes variations in the output impedance due to variations in power supply voltage and temperature to be greatly reduced as compared with the circuit of FIG. 1 wherein the output impedance is established by only passive elements. 
     The output impedance itself may be optionally determined by the resistor R and the gm of the transistors. However, in determining and more particularly reducing the output impedance, care must be taken not to increase current consumption. 
     FIG. 6 illustrates correlation among input voltage V in  &#39;, output voltage V out , output impedance R out , current I f  flowing through the MOSFET and the resistor R when supplied with power voltage V DD  -V SS , etc. 
     The graph (I) shows V in  &#39; versus V out  characteristic of a MOSFET follower. The presence of the threshold voltage V th  inherent to the MOSFET develops no output V out  while the input V in  &#39; changes from V ss  to V th . The gain should not be more than 1 from the viewpoint of the operating principle of the follower amplifier. In other words, the maximum of the output V out  never reaches V DD  in contrast with the CMOS scheme. 
     The graph (II) indicates the development of the output impedance R out  of the MOSFET follower as a function of variations in the output potential V out . Since the MOSFET is in the pinch off state before the input V in  &#39; changes from V ss  to V th , the output impedance R out  is the very output resistor R. As the input V in  &#39; exceeds the voltage V th  and advances toward the voltage V DD , the internal resistance of the MOSFET is correspondingly reduced, thereby accomplishing a reduction of the output impedance R out . 
     Within the graph (II), the curve (1) represents the output impedance R out  when power supply voltage is between V DD  -V SS  and at room temperature, whereas the curve (2) represents the same when the power supply voltage is between V DD  -V SS  and at a higher than room temperature. It will be clear from the curves that the output impedance in the case (2) is higher than in the case (1). 
     The graph (III) depicts the current I F  flowing across the power terminals V DD  and V SS  of the MOSFET follower when supplied with V DD  -V SS , as a function of the input potential V in  &#39;. Since the MOSFET is in the pinch off state, it permits little or no current I F  till the input V in  &#39; reaches the voltage V th . However, when the input V in  &#39; is increased beyond the voltage V th  to approach the voltage V DD , the ON resistance of the MOSFET is decreased and the current I F  is increased. 
     An amplifier arrangement which employs as a buffer means for the CMOS analog amplifier, the MOSFET follower having the above discussed properties, is illustrated in FIG. 7. An N-channel MOSFET forming the follower circuit is denoted as N&#39;. While the output terminal of the CMOS analog amplifier is commonly connected to the input terminal of the next succeeding stage MOS follower, both are respectively denoted as V out , V in  &#39; for the sake of explanation only. A total of the consumption current I c  of the CMOS analog amplifier and the consumption current I F  of the MOS follower is denoted as I T  as shown in FIG. 8. 
     FIG. 8 illustrates some of the operating characteristics of the CMOS analog amplifier. The graph (I) depicts relationship between the input potential V in  and the output potential V out  &#39;; the graph (II) depicts relationship between the input potential V in  &#39; and the output potential V out  within the MOS follower; the graph (III) depicts relationship between the output potential V out  and the output impedance R out  ; and the graph (IV) depicts relationship between the input potential V in  and the consumption current I c  and I F  and the total consumption current I T . These graphs are provided for comparison between the basic CMOS amplifier of FIG. 2 and the MOSFET follower of FIG. 7. 
     It is obvious from relationship between the curve (I) in the graph (III) and the curve (3) in the graph (IV) and relationship between the curve (2) in the graph (III) and the curve (4) in the graph (IV) that intention to reduce the output impedance R out  leads to an increase in the consumption current I c . 
     Analysis of the curve (5) in the graph (III) reveals that the output impedance R out  always stands below the resistance value of the output resistor R for all of the possible output potentials by employment of the MOS follower driver. While the output voltage is biased with the operating center V FOC  of the MOS follower output, the peak of the output impedance R out  does not stand in the vicinity of the operating center V FOC  in contrast with the basic CMOS amplifier. 
     Accordingly, the circuit of FIG. 7 is effective since the output impedance R out  at the operating center should be low. 
     As stated earlier, in case of the basic CMOS amplifier of FIG. 1, the only way to reduce the output impedance is to increase gm of the P- and N-MOS transistors or to decrease V th . This results in an increase in consumption current. However, since pursuant to the circuit of FIG. 7 the output of the CMOS analog amplifier is utilized only to drive a gate capacitor of the next succeeding state MOS follower, the output impedance of the CMOS amplifier may be sufficiently high as not to disturb the frequency characteristic of the amplifier. For example, the characteristics as suggested by the curve (2) of the graph (III) and the curve (4) of the graph (IV) may be employed. In other words, it is not difficult to reduce the voltage gain even if P- and N-MOS transistors within the CMOS scheme assume smaller gm. This enables the consumption current I c  in the CMOS amplifier region to be largely reduced. 
     Moreover, since the circuit of FIG. 7 is such that the output impedance R out  is established by the MOS follower including one passive element (that is, the resistor R; the only factor causing variations in its resistance is temperature) but excluding one active element (that is, the MOS transistor), the output impedance R out  of the MOS follower circuit is scarcely varied due to variations in the input and output potentials, the power supply voltage, temperature, etc. 
     The following describes the consumption current I F  in the MOS follower circuit. The curve (6) in the graph (IV) of FIG. 8 illustrates changes in the consumption current I F  in the MOS follower circuit as a function of changes in the input potential V in . No current I F  flows till the input potential V in  &#39; is increased from V SS  to V th . As V in  &#39; approaches V DD  through V th , I F  is increased. When V DD  is exceeded, I F  takes a maximum. 
     Voltage V s , an input voltage V in  of the CMOS amplifier, is sufficient to permit the output voltage V out  &#39; of the CMOS amplifier to continue saturating at the voltage V DD . Voltage V thin , also an input voltage V in  of the CMOS amplifier is sufficient to permit the input potential V in  &#39; of the MOS follower to reach the voltage V th . 
     No current I F  will flow during a period of time where the input voltage V in  is between the voltage V DD  and the voltage V thin . 
     The current I F  is increased as the voltage changes from the voltage V thin  to the voltage V s . But, I F  becomes constant during transition from V s  to V ss . When variations in the consumption current I c , responsive to variations in the input voltage V in  are described by the curve (4) in the graph (IV) of FIG. 8, the total consumption current I T  will be I F  +I c  as viewed from the curve (7). 
     In the circuit of FIG. 7 it is possible to utilize the output V out  &#39; since it has relatively good linearity and a relatively good amplitude characteristic. The output V out  &#39; is, therefore, useful when driving a light-load. 
     Accordingly, when the amplifier embodying the present invention is combined with quartz resonators of higher CI in crystal oscillators for solid state timekeeping devices, the amplifier gives excellent oscillation characteristics. More particularly, it is possible to reduce the oscillation initiating duration, the oscillation initiating voltage and the oscillating frequency deviation and power consumption. In addition, signals of large amplitude are obtainable through the utilization of the output terminal V out  &#39; to assure a simplicity in a pulse re-shaping circuit of the next succeeding stage. FIG. 9 is an example wherein excitation of the crystal oscillator, having requirement for lowered output impedance, is through the output V out  of the MOS follower and signal stretching is through the output V out  &#39; of the CMOS amplifier. The output is re-shaped easily by introduction into a CMOS re-shaping circuit I n . 
     An example of practical conditions is as follows: the MOS transistor N&#39; within the MOS follower amplifier is an N-channel one wherein β÷400 μυ/V and Vth=0.7 V at 1 μA; the resistor R is 470 KΩ; the quartz resonator X has a nominal oscillation frequency of 32.768 KHz; CI is 265 KΩ; capacitors C 1  and C 2  are respectively 19 pF and 81 pF. When V DD  -V SS  =1.6V and room temperature 25° C., I F  =1.35 μA, I c  =1.95 μA, I F  =3.20 μA, the oscillation initiating duration =6 sec., the minimum oscillation initiating voltage and oscillation frequency deviation against power voltage variations is 0.8 sec/day V. These results are completely satisfactory to timekeeping crystal oscillators. 
     For comparison purposes, if the quartz oscillator is excited by the CMOS amplifier without using the MOS follower, the following unfavorable results are given: the consumption current is 5.8 μA; the oscillation initiating duration is over 40 sec.; the oscillation initiating voltage is 1.6 V; the frequency deviation is 2.5 sec/day V. Input-output waveform characteristics of the MOS follower stage when biased via the R f  are illustrated in FIG. 10, wherein the curve (A) represents relationship between the follower input voltage V in  &#39; and the follower output voltage V out  in case where the threshold voltage V th  of the MOS transistor N&#39; of FIG. 7 is not ignored as compared with the power supply voltage V DD  -V SS . The curve (B) shows the case where the threshold voltage V th  is extremely low as compared with the power voltage V DD  -V SS  or zero. For the MOS follower having the characteristics shown by the curve (A), the operating center of the output V out  is V FOC  &#39; when the input of the MOS follower is biased with the voltage ##EQU1## via R f  within the CMOS amplifier. When the input V in  &#39; takes the signal waveform (1), the output V out  will take the somewhat disturbed waveform (2). For the MOS follower having the characteristic shown by the curve (B), the waveform of the output V out  contains little distortion. As a matter of fact, the MOS follower as shown by the curve (B) intends to increase the consumption current. Meanwhile, when a large amplitude signal is not necessary but waveform distortion must be small, the CMOS amplifier and the MOS follower can be AC coupled through a capacitor C as suggested in FIG. 11. By a couple of resistors R 1  and R 2 , the source follower input V in  &#39; is biased with ##EQU2## to attain the waveform (5) containing little distortion. In this instance V out  has the operating center V FOC  &#34;. 
     As shown in FIG. 12, current limiting effects are expected if a substrate potential is declined to V ss  and voltage drop is developed between a substrate and a source due to the resistor R. 
     The consumption current is therefore reduced even though the resistor R is not high. 
     Another approach to reduce and stabilize the output impedance without a considerable large reduction in the consumption current is suggested in FIG. 13 showing employment of a resistor-load MOS amplifier. 
     FIG. 14 illustrates the output potential V out , the output impedance R out , the current I L  flowing through N-channel MOS transistor N and the resistor R, etc., as a function of the input potential V in . 
     The graph (I) in FIG. 14 represents the V in  -V out  characteristics of the resistor-load amplifier. Due to the presence of the threshold voltage V th  inherent to the MOS transistors, the output potential V out  remains unchanged at V DD  till the input potential V in  changes from V ss  to V th . However, during voltage transition from V th  to V IS  the output potential V out  is greatly varied from V DD  to V OS . As well, during transition from V IS  to V DD  the output potential V out  is held at the saturated value V OS . 
     The graph (II) shows the development of the output impedance R out  as a function of variations in the output potential V out . When the input potential V in  changes from V ss  to V in , the MOS transistor is held at the pinch off state and therefore the output impedance V out  is constituted by only the output resistor R. As the input potential V in  is increased via V th  to V IS , the on resistance of the MOS transistor is correspondingly reduced with an accompanying gradual reduction in the output impedance R out . The output potential V out  is held at the saturated state V OS  till the input potential V in  is varied from V IS  to V DD . Thus, the output impedance R out  becomes unchanged. The curve (1) in the graph (II) shows the output impedance R out  under the power supply voltage V DD  -V SS  and at room temperature, whereas the curve (2) shows the same under the conditions where the power supply voltage is lower than V DD  -V SS  and the circumambient temperature is higher than room temperature. 
     The graph (III) shows the current I L  flowing across the power supply terminals V DD  and V SS  of the resistor-load MOS amplifier when supplied with V DD  -V SS , as a function of the input potential V in . Since the MOS transistor is at the pinch off state when the input potential V in  is varied from V SS  to V th , no current I L  flows. But, as the input potential V in  is increased via V th  to V IS , the ON resistance of the MOS transistor is reduced to thereby increase the current I L . If V IS  is exceeded, the current I L  is saturated at I LS . 
     As noted earlier, the amplifier of FIG. 13 supplies current through the load resistor R when its active elements are conductive. The output impedance R out  is formed by the constant resistor R and the internal impedance of the MOS transistor N. The number of the MOS transistors as the active elements is reduced from two to one such that variations in the output impedance R out  due to the input and output voltage levels, the power supply voltage and the temperature are further minimized. 
     FIG. 15 is one preferred form of the present invention which is predicated upon a combination of the complementarily coupled transistor amplifier and the above discussed resistor-load transistor amplifier. In the prior art amplifier, while the output impedance is relatively high and its variations due to the input and output levels and the power supply voltage are relatively large, the voltage gain is high and the input impedance is high. In accordance with the amplifier described with respect to FIGS. 13 and 14, the input impedance is high but the output impedance is relatively low and its variations due to the input and output levels and the power supply voltage also is relatively low. 
     The embodiment of FIG. 15 comprises a CMOS amplifier 1 including a P-channel MOS transistor P, an N-channel MOS amplifier N and a bias resistor R f  provided between its input and output, and a resistor-load MOS amplifier 2 of which the load resistor R is is connected to the drain of the N-channel MOS transistor N. The output node of the CMOS amplifier 1 is connected to the input node of the resistor-load MOS amplifier 2. With such an arrangement, the input node of the resistor-load MOS amplifier 2 is biased. 
     In case where DC amplification is not needed and variations in the bias level at the input node of the resistor-load amplifier should be minimized, DC level is cut via a capacitor C and a resistor R f  &#39; establishes self biasing as suggested in FIG. 16. 
     FIG. 17 illustrates various characteristics for the purpose of explanation of operation of the circuits shown in FIGS. 15 and 16. In FIG. 17, the graph (I) represents relationship between the input potential V in  &#39; and the output potential V out  &#39; within the CMOS amplifier 1; the graph (II) represents the relationship between the input potential V in  and the output potential V out  within the resistor-load MOS amplifier 2; the graph (III) represents the relationship between the output potential V out  and the output impedance R out  ; and the graph (IV) represents the relationship between the input potential V in  in the CMOS amplifier 1 and the consumption current I c  in the CMOS amplifier 1, the counterpart I I  in the resistor-load amplifier 2 and the sum thereof I T  (=I c  +I I ). It is obvious from relationship between the curve (1) in the graph (III) and the curve (3) in the graph (IV) and relationship between the curve (2) in the graph (III) and the curve (4) in the graph (IV) that the consumption circuits I c  and I c  &#39; are unavoidably increased if the output impedance R out  is sought to be reduced. 
     It will be noted that the operating center of the resistor-load MOS amplifier 1 is somewhat shifted depending upon whether the DC coupling of FIG. 15 or the AC coupling of FIG. 16 is employed. Such fact is depicted on the graphs (II) and (III) in FIG. 17. A shows the operating center in case of the DC coupling while B shows the same in case of the AC coupling. 
     As illustrated in the graph (I) in FIG. 17, the output potential V out  and the output impedance R out  are constant until the input potential V in  &#39; is varied from V DD  to V thin . Under these circumstances the consumption current I I  of the resistor-load MOS amplifier 2 is zero and hence the total consumption current I T  is only the consumption current I c  of the CMOS amplifier. 
     Therefore, as viewed from the graphs (II) and (III), the output potential V out  is approximately equal to V OS  and the output impedance R out  is gradually decreased to the resistance R S  during the period where the input V in  &#39; is advanced from V thin  toward V ISN . Simultaneously, the consumption current I I  and in other words I T  are increased. 
     During a period where V in  &#39; is varied from V ISIN  to V SS  the resistor-load MOS amplifier 2 is saturated so that the output potential V out  and the output impedance R out  are substantially settled at V OS  and R S . The consumption current I I  becomes constant and the consumption current I C  is gradually reduced, thereby reducing the total of the consumption current I T . 
     As suggested in FIG. 18, the CMOS amplifier 1 may be provided in a multi-stage fashion. In case where the number of the amplifier stages is an even number, inversion is developed between the input V in  and the output V out . In the given example, the respective ones of the CMOS amplifiers are AC coupled via a series of capacitors C, C&#39;, . . . C (n-1). 
     In FIG. 19, a two-stage CMOS amplifier 1 is provided and the output V out  of the resistor-load MOS amplifier 2 is employed to excite the quartz resonator X. 
     Attention must be paid to the frequency characteristics of the respective amplifiers. In FIG. 20, (a) represents the frequency characteristic of the CMOS amplifier and (b) represents the counterpart of the resistor-load amplifier, wherein the input signal is 10 mVp-p, the voltage supply is 3.0 V and the output floating capacitance is 8 pF. 
     In the case of the CMOS amplifier, the voltage gain is about 130 at a low frequency range but only 1.8 in the vicinity of the oscillating frequency of the quartz resonator X (i.e., 32.768 KHz). In contrast to this, for the resistor-load amplifier the voltage gain is about 40 l at a low frequency range and about 3.6 in the vicinity of the oscillating frequency 32.768 KHz. The resistor-load amplifier, therefore, manifests the better frequency characteristics although the current consumption is equal. Furthermore, since the gain within the DC and low frequency region is lower for the resistor-load amplifier, a multi-stage arrangement of the resistor-load amplifier is possible in principle. 
     FIG. 21 is an example of a two-stage direct coupling resistor-load amplifier. Detailed analysis of the bias characteristics of the resistor-load amplifier of FIG. 21 is as follows. 
     Biasing is basically accomplished by the resistor R f  provided between the drain and the gate of the first stage MOS transistor M 1 . Therefore, when the input and output potentials of the transistor M 1  are respectively V in1  and V out1 . 
     
         V.sub.out1 =V.sub.in1                                      (1) 
    
     If the threshold voltage of the first stage MOS transistor M 1  is V th1 , V th1  &gt;0. 
     
         V.sub.out1 &gt;V.sub.in1 -V.sub.th1                           (2) 
    
     This shows the fact that the MOS transistor M 1  is in the saturated state. Therefore, current i DS  flowing through the MOS transistor is as follows. ##EQU3## If current flowing through the load resistor R 1  is i L , ##EQU4## Because the next succeeding state is a MOS gate load, no DC current flows. 
     
         i.sub.DS =i.sub.L                                          (5) 
    
     The equations (3) and (4) are substituted into the equation (5). 
     
         V.sub.out =V.sub.DD -k.sub.1 R.sub.1 (V.sub.in1 -V.sub.th1).sup.2 (6) 
    
     The equation (1) is substituted into the above. ##EQU5## That is, ##EQU6## In this manner, the first stage amplifier is biased via the bias resistor R f  and provides the output potential which is determined by V th1  of the MOS transistor M 1 , K 1 , the load resistor R 1  and the power supply voltage V DD  without regard to R f . 
     The input-output relationship of the second-stage resistor-load MOS amplifier is as follow wherein K 2  is the constant of the MOS transistor M 2 , V th2  is the threshold voltage of M 2  and R 2  is the load resistor. 
     
         K.sub.1 R.sub.1 =K.sub.2 R.sub.2                           (9) 
    
     If the following is established, 
     
         V.sub.th1 =V.sub.th2                                       (10) 
    
     From the equation (8), 
     
         V.sub.out2 =V.sub.in2 =V.sub.out1 =V.sub.in1               (11) 
    
     It thus can be considered from temperature-dependent variations in K 1 , K 2 , V th1 , V th2 , that the resistors R 1  and R 2  are not varied when implemented with integrated circuit technology. The equation (11) therefore seems almost practical for use. The amplifier of FIG. 21 eliminates the need for capacitor coupling and exhibits the substantially stable performance characteristics. 
     FIG. 22 shows an application of the amplifier of FIG. 21 to an oscillator containing a quartz resonator of higher CI. A quartz enabling stage CD, an impedance converter, consists of a load resistor R 3  and a MOS transistor M 3  and serves to excite a quartz circuit CC. Biasing is accomplished by R f  &#39;. A preamplifier PA as suggested by FIG. 21 is coupled via a capacitor C 03  with the quartz enabling stage CD. 
     FIG. 23 illustrates deviation in sec/day and the period of time required for initiating oscillation t osc  as a function of the power supply voltage V ss  and external capacitors C 1  and C 2 . The greater the deviation the greater the capacitors C 1  and C 2 . The most favorable results are obtained at 0-0.5 S/D. V out . When the external capacitors are not coupled, the period t osc  is reduced to a minimum (shorter than 1.0 sec.). FIG. 24 depicts the total consumption current I T  (μA), the deviation (sec/day) and the oscillation period t osc  (sec.) when the power supply voltage V DD  -V SS  is 1.55 V and the external capacitors C 1  and C 2  are altered. 
     While only certain embodiments of the present invention have been described, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as claimed.