Patent Publication Number: US-2013241501-A1

Title: Charging System

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a charging system, and more particularly, to a charging system capable of controlling at least one of a unit gain buffer and at least one independent voltage source to sequentially charge a capacitor according to a range which a target voltage is located, to flexibly reduce power consumption or improve charging speed. 
     2. Description of the Prior Art 
     In general, when performing LCD driving, a unit gain buffer is utilized to charge a capacitor of each pixel to a target voltage according to a gray scale of each pixel in each image, to display each image. 
     For example, please refer to  FIG. 1 , which is a schematic diagram of a conventional unit gain buffer  10  charging a capacitor  12 . As shown in  FIG. 1 , the unit gain buffer  10  is driven by a driving voltage V P , and includes a positive input terminal for receiving a target voltage V T , and a negative input terminal coupled to an output terminal of the unit gain buffer to form a negative feedback loop, to maintain the output terminal voltage at the target voltage V T . Therefore, the capacitor  12  can be charged to the target voltage V T . In such a condition, total power consumption caused by charging the capacitor  12  can be denoted as: P=I*V=(V T *C*F)*V P , wherein C is capacitance of the capacitor  12 , and F is switching frequency of display image, i.e. the capacitor  12  is charged to the target voltage V T  in a period of 1/F. 
     However, the conventional method of charging the capacitor  12  with only the unit gain buffer  10  lacks flexibility in power consumption and charging speed, which may cause power consumption too high or charging speed too low. Thus, there is a need for improvement of the prior art. 
     SUMMARY OF THE INVENTION 
     It is therefore an objective of the present invention to provide a charging system capable of controlling at least one of a unit gain buffer and at least one independent voltage source to sequentially charge a capacitor according to a range which a target voltage is located, to flexibly reduce power consumption or improve charging speed. 
     The present invention discloses a charging system, for charging a capacitor. The charging system comprises a unit gain buffer, driven by a driving voltage, and including a positive input terminal for receiving a target voltage, and a negative input terminal coupled to an output terminal of the unit gain buffer; at least one independent voltage source, for providing at least one voltage; a first switch, coupled between the output terminal of the unit gain buffer and the capacitor; at least one second switch, coupled between the at least one independent voltage source and the capacitor; and a switch control waveform generator, coupled to the first switch and the at least one second switch, for controlling at least one of the first switch and the at least one second switch to be sequentially turned on in one cycle according to a control signal, to sequentially charge the capacitor with at least one of the unit gain buffer and the at least one independent voltage source. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a conventional unit gain buffer charging a capacitor. 
         FIG. 2A  is a schematic diagram of a charging system according to an embodiment of the present invention. 
         FIG. 2B  is a schematic diagram of a voltage to digital code conversion information. 
         FIG. 2C  is a schematic diagram of dividing a driving voltage into three ranges. 
         FIG. 2D  is a schematic diagram of three waveform signals. 
         FIG. 2E  to  FIG. 2G  are schematic diagrams of three switches to be turned on in one cycle under different conditions. 
         FIG. 3A  is a schematic diagram of another charging system according to an embodiment of the present invention. 
         FIG. 3B  is a schematic diagram of dividing a driving voltage into four ranges. 
         FIG. 3C  is a schematic diagram of four waveform signals. 
         FIG. 3D  to  FIG. 3G  are schematic diagrams of four switches to be turned on in one cycle under different conditions. 
         FIG. 4  and  FIG. 5  are schematic diagrams of other two charging systems according to an embodiment of the present invention. 
         FIG. 6A  and  FIG. 7A  are schematic diagrams of further two charging systems according to an embodiment of the present invention. 
         FIG. 6B  and  FIG. 7B  are schematic diagrams of voltage range determination circuits shown in  FIG. 6A  and  FIG. 7A , respectively. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIG. 2A , which is a schematic diagram of a charging system  20  according to an embodiment of the present invention. As shown in  FIG. 2A , the charging system  20  is utilized for charging the capacitor  12 , and includes a unit gain buffer  200 , independent voltage sources VS A  and VS B , switches S T , S A , and S B , and a switch control waveform generator  202 . The unit gain buffer  200  is similar to the unit gain buffer  10 , and is driven by a driving voltage V P . The unit gain buffer  200  includes a positive input terminal for receiving a target voltage V T , and a negative input terminal coupled to an output terminal of the unit gain buffer  200  to form a negative feedback loop, to maintain the output voltage at the target voltage V T , wherein the target voltage V T  is usually set to be less than the driving voltage V P , such that the unit gain buffer  200  can maintain the output voltage at the target voltage V T . The independent voltage sources VS A  and VS B  provide voltages V A  and V B , respectively. The switch S T  is coupled between the output terminal of the unit gain buffer  200  and the capacitor  12 , and the switches S A  and S B  are coupled between the independent voltage sources VS A  and VS B , and the capacitor  12 . The switch control waveform generator  202  is couple to control terminals of the switches S T , S A , and S B , and controls at least one of the switches S T , S A , and S B  to be sequentially turned on in one cycle according to a control signal Con, which includes control codes D 0  and D 1 , to sequentially charge the capacitor  12  with at least one of the unit gain buffer  200  and the independent voltage sources VS A  and VS B . As a result, the switch control waveform generator  202  can flexibly switch a charging source of the capacitor  12  according to the control signal Con, to reduce power consumption or improve charging speed. 
     In detail, the switch control waveform generator  202  can control the independent voltage source VS A  to charge the capacitor  12  to the corresponding voltage V A  first, i.e. turn on the switch S A , and then control the unit gain buffer  200  to charge the capacitor  12  to the target voltage V T . In such a condition, if the voltage V A  is less than the target voltage V T  and less than the driving voltage V P , total power consumption caused by charging the capacitor  12  is P=I*V=(V A *C*F)*V A +((V T −V A )*C*F)*V P , which is less than total power consumption caused by the conventional charging method only utilizing the unit gain buffer  10 : P=I*V=(V T *C*F)*V P , i.e. the capacitor  12  is first charged to the voltage V A  which is less than the driving voltage V P , and thus power consumption can be reduced. On the other hand, if the voltage V A  is greater than the target voltage V T  and less than the driving voltage V P , the capacitor  12  can be charged to the target voltage V A  first, wherein the target voltage V A  is greater than the target voltage V T , and then the unit gain buffer  200  adjusts the voltage across the capacitor  12  to the target voltage V T . In this case, although power consumption is less reduced than the previous method (because the voltage V A  is greater than the target voltage V T ), charging speed can be improved for the capacitor  12  to rapidly achieve the target voltage V T . As a result, the charging system  20  can flexibly switch the charging source of the capacitor  12  according to different requirements, to reduce power consumption or improve charging speed. 
     Noticeably, if the voltage V B  is greater than the voltage V A , the switch control waveform generator  202  can also control the independent voltage source VS A  to charge the capacitor  12  to the corresponding voltage V A , then control the independent voltage source VS B  to charge the capacitor  12  to the corresponding voltage V B , and then control the unit gain buffer  200  to charge the capacitor  12  to the target voltage V T  in the cycle. In such a condition, since the capacitor  12  is charged with the smaller voltage V A  first and then with the greater voltage V B , more power is saved than the case that the capacitor  12  is only charged with the greater voltage V B . As a result, the charging system  20  can charge the capacitor  12  with different voltages sequentially from small to large, to further reduce power consumption. 
     For example, please refer to  FIG. 2A  together with  FIG. 2B  to  FIG. 2G .  FIG. 2B  is a schematic diagram of a voltage to digital code conversion information VDI;  FIG. 2C  is a schematic diagram of dividing the driving voltage V P  into ranges R A , R B , and R C ;  FIG. 2D  is a schematic diagram of waveform signals W T , W A , and W B ;  FIG. 2E  to  FIG. 2G  are schematic diagrams of switches S T , S A , and S B  to be turned on in the cycle under different conditions. As shown in  FIG. 2A , a display data generator  22  outputs a digital code DV T  of a target voltage V T , e.g. 8 bits, a gamma generator  24  divides a gamma curve to correspond different digital codes to different voltages to generate the voltage to digital code conversion information VDI, e.g. the 8-bit digital codes are corresponding to 256 voltages as shown in  FIG. 2B , a digital to analog converter  26  generates the target voltage V T  in an analog form according to the digital code DV T  of the target voltage V T  and the voltage to digital code conversion information VDI. 
     In this embodiment, the charging system  20  further includes a voltage range determination circuit  204 . The voltage range determination circuit  204  divides the driving voltage V P  to the ranges R A , R B , and R C  according to the voltages V A  and V B , and determines the target voltage V T  located in one of the ranges R A , R B , and R C , to generate the control signal Con, wherein the range R A  has a lower limit of voltage  0  and an upper limit of the voltage V A , the range R B  has a lower limit of the voltage V A  and an upper limit of the voltage V B , and the range R C  has a lower limit of the voltage V B  and an upper limit of the voltage V P . In the case that the voltage range determination circuit  204  is a digital circuit, the voltage range determination circuit  204  receives the digital codes DV T , DV A , and DV B  of the target voltage V T , and the voltages V A  and V B , to determine the target voltage V T  located in one of the ranges R A , R B , and R C , and generate the control signal Con, which includes the control codes D 0  and D 1 . For example, when the target voltage V T  is located in the range R A , the control signal Con is D 1 D 0 =00, when the target voltage V T  is located in the range R B , the control signal Con is D 1 D 0 =01, and when the target voltage V T  is located in the range R C , the control signal Con is D 1 D 0 =10. In such a situation, the switch control waveform generator  202  performs logic operation to the waveform signals W T , W A , and W B  shown in  FIG. 2D , to switch a charging source of the capacitor  12  when the control signal Con indicates different control codes D 1  and D 0 , i.e. different ranges, so as to reduce power consumption or improve charging speed. 
     In detail, when the target voltage V T  is located in one of the ranges R A , R B , and R C , the control signal Con indicates the switch control waveform generator  202  to control one of the independent voltage sources VS A  and VS B  to charge the capacitor  12  to a corresponding voltage first, i.e. the voltage V A  or V B , and then control the unit gain buffer  200  to charge the capacitor  12  to the target voltage V T  in the cycle. In such a condition, as shown in upper half part of  FIG. 2F , middle part of  FIG. 2G , and lower half part of  FIG. 2G , the corresponding voltage to which the capacitor  12  is charged first can be less than or equal to a lower limit of the range, such that the capacitor  12  can be charged with a voltage less than the driving voltage V P  first, and thus power consumption can be effectively reduced. Besides, as shown in lower half part of  FIG. 2E  and lower half part of  FIG. 2F , i.e. the part of the switch S B  and the corresponding voltage V B , the corresponding voltage to which the capacitor  12  is charged first can be an upper limit of the range, such that the capacitor  12  can be charged to a voltage greater than the target voltage V T  first, and then the unit gain buffer  200  adjusts the voltage across the capacitor  12  to the target voltage V T . In this case, although power consumption is reduced less than the previous method (because the voltage V A  is greater than the target voltage V T ), charging speed can be improved for the capacitor  12  to rapidly achieve the target voltage V T . 
     Moreover, as shown in lower half part of  FIG. 2F  and upper half part of  FIG. 2G , in the cycle, the control signal Con can also indicate the switch control waveform generator  202  to control another one of the independent voltage sources VS A  and VS B , e.g. the independent voltage source VS A , to charge the capacitor  12  to another corresponding voltage, e.g. the voltage V A , then control the independent voltage source, e.g. the independent voltage source VS B , to charge the capacitor  12  to the corresponding voltage, e.g. the voltage V B , and then control the unit gain buffer  200  to charge the capacitor  12  to the target voltage V T , wherein the corresponding voltage is greater than the another corresponding voltage. In such a condition, since the capacitor  12  is charged with the smaller voltage first and then with the greater voltage, more power is saved than the case that the capacitor  12  is charged only with the greater voltage. In other words, the charging system  20  can charge the capacitor  12  with different voltages sequentially from small to large, to further reduce power consumption. Finally, as shown in upper half part of  FIG. 2E , in the case that the target voltage V T  is located in the range R A , if the capacitor  12  is not desired to be charged greater than the target voltage V T , the capacitor  12  can only be charged with the unit gain buffer  12 , too. In this case, power consumption is not reduced. 
     Noticeably, the spirit of the present invention is to flexibly switch the charging source of the capacitor  12  according to different requirements, to reduce power consumption or improve charging speed. Those skilled in the art can make modifications and alterations accordingly. For example, in the above embodiment, the voltages V A  and V B  provided by the independent voltage sources VS A  and VS B  are both less than the driving voltage V P ; in other embodiments, the voltage provided by the independent voltage source can also be greater than the driving voltage V P , to charge the capacitor  12  to the voltage greater than the target voltage V T  and the driving voltage V P  first, and then the unit gain buffer  200  adjusts the voltage across the capacitor  12  to the target voltage V T . In this case, although power consumption is larger than charging the capacitor  12  only with the unit gain buffer  10  in the prior art (because the voltage is greater than the driving voltage V P ), charging speed can further be improved for the capacitor  12  to rapidly achieve the target voltage V T . Besides, the above switches S T , S A , and S B  are illustrated as MOSFET, which are not limited to NMOS, PMOS, or CMOS, and can be other types of switch; the independent voltage sources VS A , VS B  can be linear regulator or switch regulator, which is not limited herein. 
     Besides, number of independent voltage sources and corresponding components is not limited to which shown in the above embodiment, and can be other numbers, i.e. the present invention is not limited to determine the target voltage V T  located in one of the three ranges according to two independent voltage sources, wherein number of ranges can be any one. For example, please refer to FIG.  3 A to  FIG. 3G .  FIG. 3A  is a schematic diagram of an another charging system  30  according to an embodiment of the present invention;  FIG. 3B  is a schematic diagram of dividing the driving voltage V P  to ranges R A , R B , R C , and R D ;  FIG. 3C  is a schematic diagram of waveform signals W T , W A , W B , and W C ;  FIG. 3D  to  FIG. 3G  are schematic diagrams of switches S T , S A , S B , and S C  to be turned on in the cycle under different conditions. As shown in  FIG. 3A , the charging system  30  is similar to the charging system  20 , and thus components and signals with similar functions are denoted by the same symbols. The main difference between the charging system  30  and the charging system  20  is that the charging system  30  further includes an independent voltage source VS C  for providing a voltage V C  less than the driving voltage V P , and a switch S C  coupled between the independent voltage source VS C  and the capacitor  12 , such that the voltage range determination circuit  204  further determines if the target voltage V T  is located in a range R D  according to a digital code DV S  of the voltage V C  to generate the corresponding control signal Con, i.e. control codes D 1 D 0 =11, such that the switch control waveform generator  202  performs logic operation to the waveform signals W T , W A , W B  and W C  shown in  FIG. 3C , to switch a charging source of the capacitor  12  when the control signal Con indicates different control codes D 1  and D 0 , i.e. different ranges, so as to reduce power consumption or improve charging speed. 
     In such a situation, when the target voltage V T  is located in one of the ranges R A , R B , R C , and R D , in the cycle, the control signal Con also indicates the switch control waveform generator  202  to control one of the independent voltage sources VS A , VS B , and VS C  to charge the capacitor  12  to a corresponding voltage, i.e. the voltage V A , V B , or V C , and then control the unit gain buffer  200  to charge the capacitor  12  to the target voltage V T . In such a condition, as shown in upper half part of  FIG. 3E , second part of  FIG. 3F , third part of  FIG. 3F , first part of  FIG. 3G , fourth part of  FIG. 3G , and sixth part of  FIG. 3G , the corresponding voltage to which the capacitor  12  is charged first can be less than or equal to a lower limit of the range, such that the capacitor  12  can be charged with a voltage less than the driving voltage V P  first, and thus power consumption can be effectively reduced. Besides, as shown in lower half part of  FIG. 3D , lower half part of  FIG. 3E , i.e. the part of the switch S B  and the corresponding voltage V B , and fourth to seventh parts of  FIG. 3F , i.e. the part of the switch S C  and the corresponding voltage V C , the corresponding voltage to which the capacitor  12  is charged first can be an upper limit of the range, such that the capacitor  12  can be charged to a voltage greater than the target voltage V T  first, and then the unit gain buffer  200  adjusts the voltage across the capacitor  12  to the target voltage V T . In this case, although power consumption is reduced less than the previous method (because the corresponding voltage is greater than the target voltage V T ), charging speed can be improved for the capacitor  12  to rapidly achieve the target voltage V T . 
     Moreover, as shown in lower half part of  FIG. 3E , first, fourth, fifth, and seventh parts of  FIG. 3F , and second, third, fifth, and seventh parts of  FIG. 3G , in the cycle, the control signal Con can also indicate the switch control waveform generator  202  to control another one of the independent voltage sources VS A , VS B , and VS C , e.g. the independent voltage source VS A  or VS B , to charge the capacitor  12  to another corresponding voltage, e.g. the voltage V A  or V B , then control the independent voltage source, e.g. the independent voltage source VS B  or VS C , to charge the capacitor  12  to the corresponding voltage, e.g. the voltage V B  or V C , and then control the unit gain buffer  200  to charge the capacitor  12  to the target voltage V T , wherein the corresponding voltage is greater than the another corresponding voltage. In such a condition, since the capacitor  12  is charged with the smaller voltage first and then with the greater voltage, more power is saved than the case that the capacitor  12  is only charged with the greater voltage. In other words, the charging system  20  can charge the capacitor  12  with different voltages sequentially from small to large, to further reduce power consumption. Finally, as shown in upper half part of  FIG. 3D , in the case that the target voltage V T  is located in the range R A , if the capacitor  12  is not desired to be charged greater than the target voltage V T , the capacitor  12  can only be charged with the unit gain buffer  12 , too. In this case, power consumption is not reduced. Other detailed operation methods about the charging system  30  can be referred to the above description about the charging system  20 . 
     In addition, in the above embodiments shown in the  FIG. 2A  and  FIG. 3A , the voltage range determination circuit  204  is a digital circuit and determines in which range the target voltage V T  located to generate the control codes D 0  and D 1  as the control signal Con, but the method for generating the control signal Con is not limited to this. For example, please refer to  FIG. 4  and  FIG. 5 , which are schematic diagrams of the charging systems  40  and  50 , respectively, according to an embodiment of the present invention. The charging systems  40  and  50  are similar to the charging systems  20  and  30 , respectively, and thus components and signals with similar functions are denoted by the same symbols. The main difference between the charging systems  40  and  50  and the charging systems  20  and  30  is that the charging systems  40  and  50  do not include the voltage range determination circuit  204 , and directly utilize at least one of the digital codes among the digital code DV T  of the target voltage V T  as the control signal Con. For example, if the digital code DV T  of the target voltage V T  has 8 bits, e.g. B 7  to B 0 , since several most significant bits of the digital code DV T  can approximately divide the driving voltage V P  to at least one range, the charging system  40  can divide the driving voltage V P  to three ranges according to the digital codes B 7 B 6 , and then utilize the digital codes B 7 B 6  as the control signal Con to control the switch control waveform generator  202 , wherein the function of the digital codes B 7 B 6  is similar to the control codes D 0 , and D 1 , and the charging system  50  can divide the driving voltage V P  to four ranges according to the digital codes B 7 B 6 B 5 , and then utilize the digital codes B 7 B 6 B 5  as the control signal Con to control the switch control waveform generator  202 , wherein the function of the digital codes B 7 B 6 B 5  is similar to the control codes D 0 , and D 1 . Other detailed operation methods about the charging systems  40  and  50  can be referred to the above description about the charging systems  20  and  30 . 
     Moreover, in the above embodiments shown in the  FIG. 2A  and  FIG. 3A , the voltage range determination circuit  204  is a digital circuit and determines in which range the target voltage V T  located to generate the control codes D 0  and D 1  as the control signal Con, but the voltage range determination circuit can also be realized as an analog circuit. For example, please refer to  FIG. 6A  and  FIG. 7A , which are schematic diagrams of the charging systems  60  and  70 , respectively, according to an embodiment of the present invention. The charging systems  60  and  70  are similar to the charging systems  20  and  30 , respectively, and thus components and signals with similar functions are denoted by the same symbols. The main difference between the charging system  60  and the charging system  20  is that the voltage range determination circuit  604  included in the charging system  60  is an analog circuit. The voltage range determination circuit  604  receives the target voltage V T  and the voltages V A  and V B , to determine the target voltage V T  located in one of the ranges R A , R B , and R C , and generate the control signal Con, which includes comparison results A 1  and A 0 . The main difference between the charging system  70  and the charging system  30  is that the voltage range determination circuit  704  included in the charging system  70  is an analog circuit. The voltage range determination circuit  704  receives the target voltage V T  and the voltages V A , V B , and V C , to determine the target voltage V T  located in one of the ranges R A , R B , R C , and R D , and generate the control signal Con, which includes comparison results A 2 , A 1 , and A 0 . 
     In detail, please refer to  FIG. 6B  and  FIG. 7B , which are schematic diagrams of the voltage range determination circuits  604  and  704 , respectively. As shown in  FIG. 6A , the voltage range determination circuit  604  includes comparators C A  and C B  utilized for comparing the target voltage V T  with the voltages V A  and V B , respectively, to determine the target voltage V T  located in one of the ranges R A , R B , and R C , and generate the comparison results A 1  and A 0  as the control signal Con, wherein the function of the comparison results A 1  and A 0  is similar to the control codes D 0  and D 1 . On the other hand, the voltage range determination circuit  704  includes comparators C A , C B , and C C  utilized for comparing the target voltage V T  with the voltages V A , V B , and V C , respectively, to determine the target voltage V T  located in one of the ranges R A , R B , R C , and R D , and generate the comparison results A 2 , A 1 , and A 0  as the control signal Con, wherein the function of the comparison results A 2 , A 1 , and A 0  is similar to the control codes D 0  and D 1 . Other detailed operation methods about the charging systems  60  and  70  can be referred to the above description about the charging systems  20  and  30 . 
     In the prior art, the method of charging the capacitor  12  with only the unit gain buffer  10  lacks flexibility in power consumption and charging speed, which may cause power consumption too high or charging speed too low. In comparison, the present invention can flexibly switch the charging source of the capacitor  12  according to different requirements, to reduce power consumption or improve charging speed. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.