Patent Publication Number: US-2003235019-A1

Title: Electrostatic discharge protection scheme for flip-chip packaged integrated circuits

Description:
BACKGROUND OF THE INVENTION  
       [0001] 1. Field of the Invention  
       [0002] The present invention relates to an electrostatic discharge (ESD) protection scheme. In particular, the present invention relates to an ESD protection scheme employing a trace on a package substrate to connect an ESD clamp circuit and a protected circuit.  
       [0003] 2. Description of the Related Art  
       [0004] ESD protection is an important reliability issue in integrated circuit (IC) industry. Concerning on-chip ESD protection design, VDD-to-VSS ESD clamp circuits are widely used to protect core or input/output (I/O) circuits from damage by ESD stress, as shown in FIG. 1. VDD or VSS pads ( 18   a  and  18   b ) are suggested to couple to VDD-to-VSS ESD clamp circuits ( 40  or  44 ) in a chip die  20  to protect the core or I/O circuits ( 38  or  42 ) from damage in every combination of ESD stress in the ESD test.  
       [0005]FIG. 2 shows an exemplary placement for I/O circuits, VDD-to-VSS ESD clamp circuits, and core circuits in a traditional packaged IC chip die. A chip die  20  of a traditional packaged IC has I/O circuits  38  at the periphery and core circuits  42  at the central area. Due to the considerable resistance of the power rails in a chip die, every VDD-to-VSS ESD clamp circuit  40  can only protect a limited number of nearby I/O circuits  38  or pads. Therefore, additional VDD-to-VSS ESD clamp circuits  40  must sometimes be inserted between I/O circuits  38  as shown in FIG. 2.  
       [0006] As pin counts of the ICs and speeds of I/O circuits increase, flip chip package technique becomes more popular. Unlike traditional packaged ICs, bonding wires are not used to connect the pads on the chip die with the package. The flip chip package technique uses solder bumps to connect the pads on the chip die with the package. With the flip chip technique, pads can be placed directly on I/O or core circuits and can contribute very low parasitic inductance after connecting the pads and the package. Taking advantage of flip chip package technique, many VDD or VSS pads can be placed directly on I/O or core circuits for better signal integrity and power distribution. In such a configuration, if every VDD-to-VSS ESD clamp circuit still protects a limited number of nearby pads, placing VDD-to-VSS ESD clamp circuit in the central area will become common and, as a result, will consume a very large silicon area and increase the difficulty for auto-place-and-route (APR). If not, the core circuit becomes even more susceptible to ESD stress.  
       SUMMARY OF THE INVENTION  
       [0007] An object of the present invention is to eliminate limitations due to considerable resistance of the power rails in an IC chip die.  
       [0008] Another object of the present invention is to increase flexibility for the design of ESD protection in the flip chip IC.  
       [0009] The ESD protection scheme of the present invention includes a conductive trace in a package substrate and a chip die. The chip die includes a protected circuit and a power ESD clamp circuit. The protected circuit is powered by a first high power rail and a first low power rail. The power ESD clamp circuit is coupled between a second high power rail and a second low power rail. All power rails are fabricated on the chip die. The first high power rail is separated from the second high power rail on the IC chip die. Nevertheless, during an ESD event, the first high power rail is coupled to the second high power rail through the first conductive trace in the package substrate.  
       [0010] The first low power rail is coupled to the second low power rail through another conductive trace in the package substrate, or, alternatively, is connected to the second low power rail without a route outside the IC chip die.  
       [0011] In comparison with the routes provided only by the conductive strips, typically having a thickness less than 1 um, the conductive traces on the package substrate typically have a thickness of several tens um to hundreds um. Therefore, each conductive trace in the package substrate can provide a much less-resistant route to bridge the power rails in the chip die than that provided only by the conductive strips in the chip die. Each power ESD clamp circuit, as a result, can protect much more I/O circuits or pads. As a result, the number of ESD clamp circuits can be reduced to save silicon area and cost.  
       [0012] Furthermore, employing the bridge of the conductive traces in the package substrate, ESD clamp circuits have much more flexibility to be placed in the chip die. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0013] The present invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein:  
     [0014]FIG. 1 shows a conventional ESD protection scheme utilizing metal strips on a chip die to connect VDD-to-VSS ESD protection circuits with I/O or core circuits;  
     [0015]FIG. 2 shows an exemplary placement for I/O circuits, VDD-to-VSS ESD clamp circuits, and core circuits in a traditional packaged IC chip die;  
     [0016]FIG. 3 shows an ESD protection scheme of the present invention for core or I/O circuits;  
     [0017]FIG. 4 shows the ESD protection scheme of the present invention for a chip die that has separated power rail pairs corresponding to I/O and core circuits, respectively;  
     [0018]FIG. 5 shows two ESD protection schemes for the ESD stress across different power rail pairs;  
     [0019]FIG. 6 shows the combination of the ESD protection schemes in FIGS. 4 and 5;  
     [0020]FIG. 7 shows an alternative ESD protection scheme design for the ESD stress across different power rail pairs;  
     [0021]FIG. 8 shows an ESD protection system according to the present invention; and  
     [0022]FIGS. 9 and 10 are two top views of the pad arrangement for two chip dies. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
     [0023]FIG. 3 shows an ESD protection scheme for core or I/O circuits. In a chip die  20 , there are VDD-to-VSS ESD clamp circuits  22  and core and I/O circuits  24 . VDD-to-VSS ESD clamp circuits  22  are coupled between two power rails, VDD_ESD and VSS_ESD, while the core or I/O circuits  24  are coupled between two power rails, VDD_IC and VSS_IC. Each power rail is connected to a power pad  28  formed with a solder bump  26 . Before the chip die  20  is packaged, VDD_IC is separated from VDD_ESD, and VSS_IC is separated from VSS_ESD. Taking a flip chip device as an example, the chip die is mounted face down on a package substrate, such as a printed circuit board, and then attached to the package substrate by welding or soldering. VDD_trace  30  in the package substrate provides a route to bridge VDD_IC and VDD_ESD through the solder bumps  26 , and, furthermore, connects them to a VDD pin of the package. Similarly, VSS trace  32  in the package substrate provides a route to bridge VSS_IC and VSS_ESD through the solder bumps  26 , and, furthermore, connects them to a VSS pin of the package. Normally, on-chip metal lines, including power rails, have a line thickness of tens um, at most, depending on the manufacture specification. Designer can widen the line-width, but not the line-thickness. Traces in a package substrate have a line thickness from tens um to hundred um. Thus, at the same width, traces usually have much less parasitic resistance than the power rails.  
     [0024] In normal operation, electrical power comes from the VDD and VSS pins, and goes through VDD and VSS traces, VDD_IC and VSS_IC, to power the core and I/O circuits  24 , while VDD-to-VSS ESD clamp circuits  22  are kept in off state. During an ESD event, such as positive ESD voltage on a VDD pin and a VSS pin is grounded, the ESD voltage or stress is first spread over the VDD trace  30  due to its lower resistance in comparison with that of the rails on the chip die  20 . Before the core or I/O circuits  24  is damaged by the ESD stress, VDD-to-VSS ESD clamp circuits  22  are designed to be turned on by the high ESD stress, and provide a low-impedance path from VDD to VSS to discharge the ESD current and protect the chip die  20  from ESD damage.  
     [0025] In the ESD protection scheme of FIG. 3, VDD-to-VSS ESD clamp circuits  22  are not required to be close to the core or I/O circuits  24 , as in the prior art. This flexibility allows the VDD-to-VSS clamp circuits to be placed at previously difficult-to-use locations so the overall silicon area of the chip die is not increased.  
     [0026] The benefit of the ESD protection scheme in FIG. 3 further includes the lower number of VDD-to-VSS ESD claim circuits  22  required to protect the core or I/O circuits  24 , compared to those needed in the prior art. The number of the VDD-to-VSS ESD clamp circuits depends on the response speed of each VDD-to-VSS clamp circuit in every combination of ESD stress. If there is a combination in which all the VDD-to-VSS ESD clamp circuits respond too low to protect the core or I/O circuits, usually due to the considerable resistance of the power rails, an additional VDD-to-VSS ESD clamp circuit must be specially inserted and placed into the chip die. In the prior art, more I/O or core circuits imply more VDD-to-VSS ESD clamp circuits. Applying the present invention, no matter what combination of ESD stress is, it will quickly be spread over VDD trace  30  or VSS trace  32  because of the lower resistance of the traces in the package substrate to turn on the connected VDD-to-VSS ESD clamp circuits. Thus, every combination of ESD stress is almost the same in view of ESD response speed. Once the number of VDD-to-VSS clamp circuits is enough in consideration of ESD protection, it is still enough even if the number of the core or I/O circuits is increased.  
     [0027] The pair of power rails for core circuits can always be separated from the pair of power rails for I/O circuits, as shown in FIG. 4, to prevent power bouncing or noise migration. FIG. 4 shows the ESD protection scheme of the present invention for a chip die that has separate power rail pairs corresponding to I/O and core circuits, respectively. The power rail pair, VDD_I/O and VSS_I/O, is specially provided for I/O circuits  38 . The power rails pair, VDD_core and VSS_core, is specially provided for core circuits  42 . VDD-to-VSS ESD clamp circuits  40  protect the I/O circuits  38  via solder bumps  26 , VDD_trace_I/O  39  and VSS_trace_I/O  41 . VDD-to-VSS ESD clamp circuits  44  protect the core circuits  42  via solder bumps  26 , VDD_trace_core  43  and VSS_trace_core  45 . The power bouncing induced by the high current driving in the I/O circuits  38  will not affect the core circuits  42  since the power rail pairs are separated.  
     [0028] ESD protection must be provided in case of the ESD stress across different power rail pairs. FIG. 5 shows two ESD protection schemes for the ESD stress across different power rail pairs. VDD-to-VSS ESD clamp circuits  46  protect the ESD stress across the VDD pin for core circuits and the VSS pin for I/O circuits, and are coupled between VDD_trace_core  43  and VSS_trace_I/O  41 . VDD-to-VSS ESD clamp circuits  48  protect the ESD stress across the VDD pin for I/O circuits and the VSS pin for core circuits, and are coupled between VDD_trace_I/O  39  and VSS_trace_core  45 .  
     [0029]FIG. 6 shows the combination of the ESD protection schemes in FIGS. 4 and 5. Through the package substrate, the power rail pair of VDD_trace_core  43  and VSS_trance_core  45  is connected to the VDD and VSS pins (not shown) to substantially transmit power to the core circuits  42 . The power rail pair of VDD_trace_I/O  39  and VSS_trance_I/O  41  is connected to the VDD and VSS pins to substantially transmit power to the I/O circuits  38 .  
     [0030] An alternative ESD protection scheme design for the ESD stress across different power rail pairs is shown in FIG. 7. To protect circuits powered by different power pins from ESD damage, ESD_pass cell(s) ( 60 ˜) can be inserted between traces for different power pins to construct a discharge route during an ESD event. One way to construct an ESD_pass cell is to connect two diodes in parallel but reverse direction. Thus, the anode and the cathode of one diode are respectively coupled to the cathode and the anode of another diode. Each diode can be composed of several diodes connected in series in order to have a higher threshold voltage. The threshold voltages of the two diodes depend on how much noise margin or voltage difference is acceptable between the two connected traces at normal operation condition. In FIG. 7, ESD_pass cells  60   a ,  60   b ,  60   c  and  60   d  are individually coupled between power traces. In normal operation, the voltage difference across the VDD_trace_core_ 1   43   a  and VDD_trace_I/O  39 , for example, is not high enough to turn on the ESD_pass cell  60   a . In an ESD event with positive voltage on VDD_trace_I/O  39  and ground voltage on VSS_trace_core_ 1   45   a , there are at least two discharge routes in FIG. 7. One route starts from VDD_trace_I/O  39 , passes through ESD_pass cell  60   a , VDD_trace_core_ 1   43   a , and VDD-to-VSS ESD clamp circuits  42   a , and ends at VSS_trace_core_ 1   45   a . The other route starts from VDD_trace_I/O  39 , passes through VDD-to-VSS ESD clamp circuits  40 , VSS_trace_I/O  41 , and ESD_pass cell  60   b , and ends at VSS_trace_core_ 1   45   a . Between them, the route with the lowest turn-on voltage will be automatically selected to discharge the ESD stress.  
     [0031]FIG. 8 shows an ESD protection system according to the present invention. In advanced IC chip, it is common to power different circuit groups with different power rail pairs connected to different power pins on the package. To meet the requirement of ESD protection for each combination of power pins, the ESD protection system in FIG. 8 is proposed. Core circuits  42   a  are powered by two power rails, VDD_core_ 1  and VSS_core_ 1 . ESD_pass cell  60   e  is coupled to VDD_core_ 1  through a trace  64   a  in the package, and furthermore, coupled to a global ESD high bus  80 , another trace in the package. ESD_pass cell  60   h  is coupled to VSS_core_ 1  through a trace  66   a  in the package, and furthermore, coupled to a global ESD low bus  82 , another trace in the package. VDD-to-VSS ESD clamp circuits  62  are coupled between global ESD high and low buses ( 80  and  82 ). The similar connections are applied to core circuit  42   b  and I/O circuits  38 . In normal operation, VDD-to-VSS ESD clamp circuits  62  and all ESD_pass cells function as open circuits. During ESD stress, they may be triggered on to act as short circuits to discharge the ESD stress. For example, if the ESD positive voltage pulses on trace  64   a  while trace  66   b  is grounded, the discharge current will sequentially go through trace  64   a , ESD_pass cell  60   e , global ESD high bus  80 , VDD-to-VSS ESD clamp circuits  62 , global ESD low bus  82 , ESD_pass cell  60   k  and trace  66   b.    
     [0032] By applying the traces in package to connect VDD-to-VSS ESD clamp circuits with I/O or core circuits, designers have more flexibility to place pads on a chip die. FIGS. 9 and 10 are two top views of the pad arrangement for two chip dies. I/O circuits  38  are placed at all sides of the square chip die  20 . What must be noticed is that, except an inevitable I/O pad, every I/O circuit has only one power pad, either VDD or VSS. The I/O circuit with a VSS/VDD pad is placed between two I/O circuits, each having a VDD/VSS pad. Of course, every I/O circuit must be powered through at least two power rails, for example, VDD and VSS. Every power rail in an I/O circuit is connected to a power trace via a power pad on the I/O circuit or on an adjacent I/O circuit. VDD-to-VSS ESD clamp circuit has two power pads thereon, which provide bridges to connect with the I/O or core circuits via the traces in the package substrate. In FIG. 9, all VDD-to-VSS ESD clamp circuits  66  are placed at the four corner regions. In FIG. 10, in addition to a VDD-to-VSS ESD clamp circuit  66  in a corner region, two VDD-to-VSS ESD clamp circuits  68  are located in the central region of a chip die  20 . Several I/O circuits  38  are also placed in the central region to divide the core circuits into two groups, core circuits  1  and core circuits  2 . All the core circuits have power pads thereon to connect their power rails with the power rails of the VDD-to-VSS ESD clamp circuits via the traces on the package substrate.  
     [0033] In comparison with the prior art, which uses metal strips in a chip die to connect VDD-to-VSS clamp circuits with I/O or core circuits, the ESD protection scheme of the present invention utilizes traces in the package substrate to bridge them. Due to less resistance, the VDD-to-VSS ESD clamp circuit can protect more I/O or core circuits, can be placed in any region to result a smaller die size, and to save cost.  
     [0034] Finally, while the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.