Patent Publication Number: US-7223678-B2

Title: Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor

Description:
This application is a divisional of U.S. application Ser. No. 10/879,378, filed Jun. 29, 2004, now issued as U.S. Pat. No. 7,057,223 on Jun. 6, 2006, which is a continuation of U.S. application Ser. No. 09/551,027, filed Apr. 17, 2000, now issued as U.S. Pat. No. 6,764,901 on Jul. 20, 2004, which is a divisional of U.S. application Ser. No. 08/939,742, filed Oct. 6, 1997, now issued as U.S. Pat. No. 6,066,869 on May 23, 2000. These applications are incorporated herein by reference. 

   TECHNICAL FIELD OF THE INVENTION 
   The present invention relates generally to the field of memory devices and, in particular, to a circuit and method for a folded bit line memory cell with a vertical transistor and a trench capacitor. 
   BACKGROUND OF THE INVENTION 
   Electronic systems typically store data during operation in a memory device. In recent years, the dynamic random access memory (DRAM) has become a popular data storage device for such systems. Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., “1” or “0”) in a large number of cells. The data is stored in a cell as a charge on a capacitor located within the cell. Typically, a high logic level is approximately equal to the power supply voltage and a low logic level is approximately equal to ground. 
   The cells of a conventional DRAM are arranged in an array so that individual cells can be addressed and accessed. The array can be thought of as rows and columns of cells. Each row includes a word line that interconnects cells on the row with a common control signal. Similarly, each column includes a bit line that is coupled to at most one cell in each row. Thus, the word and bit lines can be controlled so as to individually access each cell of the array. 
   A memory array is typically implemented as an integrated circuit on a semiconductor substrate in one of a number of conventional layouts. One such layout is referred to as an “folded digit line” architecture. In this architecture, sense amplifier circuits are provided at the edge of the array. The bit lines are paired in complementary pairs. Each complementary pair in the array feeds into a sense amplifier circuit. The sense amplifier circuit detects and amplifies differences in voltage on the complementary pair of bit lines as described in more detail below. 
   To read data out of a cell, the capacitor of a cell is accessed by selecting the word line associated with the cell. A complementary bit line that is paired with the bit line for the selected cell is equilibrated with the voltage on the bit line for the selected cell. The equilibration voltage is typically midway between the high and low logic levels. Thus, conventionally, the bit lines are equilibrated to one-half of the power supply voltage, V CC /2. When the word line is activated for the selected cell, the capacitor of the selected cell discharges the stored voltage onto the bit line, thus changing the voltage on the bit line. 
   The sense amplifier detects and amplifies the difference in voltage on the pair of bit lines. The sense amplifier typically includes two main components: an n-sense amplifier and a p-sense amplifier. The n-sense amplifier includes a cross-coupled pair of n-channel transistors that drive the low bit line to ground. The p-sense amplifier includes a cross-coupled pair of p-channel transistors and is used to drive the high bit line to the power supply voltage. 
   An input/output device for the array, typically an n-channel transistor, passes the voltage on the bit line for the selected cell to an input/output line for communication to, for example, a processor of a computer or other electronic system associated with the DRAM. In a write operation, data is passed from the input/output lines to the bit lines by the input/output device of the array for storage on the capacitor in the selected cell. 
   Each of the components of a memory device are conventionally formed as part of an integrated circuit on a “chip” or wafer of semiconductor material. One of the limiting factors in increasing the capacity of a memory device is the amount of surface area of chip used to form each memory cell. In the industry terminology, the surface area required for a memory cell is characterized in terms of the minimum feature size, “F,” that is obtainable by the lithography technology used to form the memory cell. Conventionally, the memory cell is laid out with a transistor that includes first and second source/drain regions separated by a body or gate region that are disposed horizontally along a surface of the chip. When isolation between adjacent transistors is considered, the surface area required for such a transistor is generally 8F 2  or 6F 2 . 
   Some researchers have proposed using a vertical transistor in the memory cell in order to reduce the surface area of the chip required for the cell. Each of these proposed memory cells, although smaller in size from conventional cells, fails to provide adequate operational characteristics when compared to more conventional structures. For example, U.S. Pat. No. 4,673,962 (the &#39;962 Patent) issued to Texas Instruments on Jun. 16, 1997. The &#39;962 Patent discloses the use of a thin poly-silicon field effect transistor (FET) in a memory cell. The poly-silicon FET is formed along a sidewall of a trench which runs vertically into a substrate. At a minimum, the poly-silicon FET includes a junction between poly-silicon channel  58  and the bit line  20  as shown in  FIG. 3  of the &#39;962 Patent. Unfortunately, this junction is prone to charge leakage and thus the poly-silicon FET may have inadequate operational qualities to control the charge on the storage capacitor. Other known disadvantages of such thin film poly-silicon devices may also hamper the operation of the proposed cell. 
   Other researchers have proposed use of a “surrounding gate transistor” in which a gate or word line completely surrounds a vertical transistor. See, e.g.,  Impact of a Vertical Φ - shape transistor  ( VΦT )  Cell for  1  Gbit DRAM and Beyond , IEEE Trans. On Elec. Devices, Vol 42, No.12, December, 1995, pp. 2117–2123. Unfortunately, these devices suffer from problems with access speed due to high gate capacitance caused by the increased surface area of the gate which slows down the rise time of the word lines. Other vertical transistor cells include a contact between the pass transistor and a poly-silicon plate in the trench. Such vertical transistor cells are difficult to implement due to the contact and should produce a low yield. 
   For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for realizable memory cell that uses less surface area than conventional memory cells. 
   SUMMARY OF THE INVENTION 
   The above mentioned problems with memory cells and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A memory cell is described which includes a vertical transistor and trench capacitor. 
   In particular, an illustrative embodiment of the present invention includes a memory cell for a memory array with a folded bit line configuration. The memory cell includes an access transistor that is formed in a pillar of single crystal semiconductor material. The access transistor has first and second sources/drain regions and a body region that are vertically aligned. The access transistor also includes a gate that is coupled to a wordline disposed adjacent to the body region of the access transistor. A passing wordline is separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell. A trench capacitor is also included. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide. In another embodiment, the second plate of the trench capacitor surrounds the second source/drain region. In another embodiment, an ohmic contact is included to couple the second plate to a layer of semiconductor material. 
   In another embodiment, a memory device is provided. The memory device includes an array of memory cells. Each memory cell includes a vertical access transistor that is formed of a single crystalline semiconductor pillar that extends outwardly from a substrate. The semiconductor pillar includes a body and first and second source/drain regions. A gate is disposed adjacent to a side of the pillar adjacent to the body region. The memory cell also includes a trench capacitor wherein a first plate of the trench capacitor is integral with the first source/drain region and a second plate of the trench capacitor is disposed adjacent to the first plate. The memory device also includes a number of bit lines that are each selectively coupled to a number of the memory cells at the second source/drain region of the access transistor. This forms columns of memory cells in a folded bit line configuration. Finally, the memory device also includes a number of wordlines. The wordlines are disposed substantially orthogonal to the bit lines in trenches between rows of the memory cells. Each trench includes two wordlines. Each wordline is coupled to gates of alternate access transistors on opposite sides of the trench. In another embodiment, the pillars extend outward from a semiconductor portion of the substrate. In another embodiment, a surface area of the memory cell is four F 2 , wherein F is a minimum feature size. In another embodiment, a second plate of the trench capacitor surrounds the second source/drain region of the access transistor. In another embodiment, the second plate of the trench capacitor is maintained at approximately ground potential. In another embodiment, the pillar has a sub-micron width so as to allow substantially fall depletion of the body region. 
   In another embodiment, a memory array is provided. The memory array includes a number of memory cells forming an array with a number of rows and columns. Each memory cell includes an access transistor with body and first and second source/drain regions formed vertically, outwardly from a substrate. A gate is disposed adjacent to a side of the transistor. The memory array includes a number of first isolation trenches that separate adjacent rows of memory cells. First and second wordlines are disposed in each of the first isolation trenches. The first and second wordlines are coupled to alternate gates on opposite sides of the trench. The memory array also includes a number of second isolation trenches, each substantially orthogonal to the first isolation trenches and intraposed between the adjacent memory cell. 
   In another embodiment, a method of fabricating a memory array is provided. A number of access transistors were formed wherein each access transistor is formed in a pillar of semiconductor material that extends outwardly from a substrate. The access transistor includes a first source/drain region, a body region and second source/drain region that are formed vertically. The method also includes forming a trench capacitor wherein a first plate of the trench capacitor is integral with the first source/drain region of the access transistor. Further, the method includes forming a number of wordlines in a number of trenches that separates adjacent rows of access transistors. Each trench includes two wordlines with the gate of each wordline interconnecting alternate access transistors on opposite sides of the trench. Finally, the method includes a number of bit lines that interconnect second source/drain regions of selected access transistors. 
   In another embodiment, a method of fabricating a memory is provided. The method begins with forming a first conductivity type first source/drain region layer on a substrate. A second conductivity type body region layer is formed on the first source/drain region layer. A first conductivity type second source/drain region layer is formed on the body region layer. Additionally, a plurality of substantially parallel column isolation trenches are formed extending through the second source/drain region layer, the body region layer and the first source/drain region layer. This provides column bars between the column isolation trenches. Further, a plurality of substantially parallel row isolation trenches are formed orthogonal to the column isolation trenches and extending to substantially the same depth as the column isolation trenches. This produces an array of vertical access transistors for the memory array. The row and column isolation trenches are filled with a conductive material to a level that does not exceed the lower level of the body region so as to provide a common plate for capacitors of the memory cells of the memory array. Two conductive wordlines are formed in each row isolation trench to selectively interconnect alternate access transistors on opposite sides of the row isolation trench. Finally, bit lines are formed to selectively interconnect the second source/drain regions of the access transistors on each column. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block/schematic diagram of an illustrative embodiment of the present invention that includes a memory device that is coupled to an electronic system; 
       FIG. 2  is a plan view of an illustrative embodiment of a layout for a memory array according to the teachings of the present invention; 
       FIG. 3  is a perspective view of the illustrative embodiment of  FIG. 2 ; 
       FIG. 4  is a schematic diagram of a memory cell of the embodiment of  FIGS. 2 and 3 ; and 
       FIGS. 5A through 5M  are perspective and elevational views of an embodiment of an integrated circuit that illustrate processing steps for fabricating the integrated circuit according to the teachings of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention maybe practiced. The embodiments are intended to describe aspects of the invention in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and logical, mechanical and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense. 
   In the following description, the terms wafer and substrate are interchangeably used to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art. 
   The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizonal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. 
     FIG. 1  is a block/schematic diagram that illustrates generally one embodiment of a memory device  100  incorporating an array of memory cells constructed according to the teachings of the present invention. Memory device  100  is coupled to electronic system  101 . Electronic system  101  may comprise, for example, a microprocessor, a memory controller, a chip set or other appropriate electronic system. Memory device  100  illustrates, by way of example but not by way of limitation, a dynamic random access memory (DRAM), in a folded bit line configuration. Memory device  100  includes array  110  with N word lines and M complementary bit line pairs. Array  110  further includes memory cells  112 -ij, where i refers to the word line of the cell and j refers to the bit line of the cell. It is noted that an asterisk (*) is used to indicate a cell that is associated with a complementary bit line. 
   In the exemplary embodiment of  FIG. 1 , each of memory cells  112 -ij has a substantially identical structure, and accordingly, only one memory cell is described herein. These memory cells  112 -ij include a vertical transistor where one plate of a capacitor is integral with the transistor. 
   The vertical transistors are laid out in a substantially checker-board pattern of rows and columns on a substrate. Memory cell  112 - 11  includes vertical transistor  130 - 11 . A source/drain region of transistor  130 - 11  is formed in a deep trench and extends to a sufficient depth to form a storage node of storage capacitor  132 - 11 . The other terminal of storage capacitor  132 - 11  is part of a mesh or grid of poly-silicon that surrounds the source/drain region of transistor  130 - 11  and is coupled to ground potential. 
   The N word lines, WL- 1  through WL-N, are formed in trenches that separate adjacent rows of vertical transistors  130 -ij. Each trench houses two word lines, with each word line in a trench acting as a gate for alternate transistors on one side of the trench. 
   Bit lines BL- 1  through BL-M are used to write to and read data from memory cells  112 -ij in response to addressing circuitry. For example, address buffer  114  is coupled to control bit line decoder  118 , which also includes sense amplifiers and input/output circuitry that is coupled to bit lines BL- 1  through BL-M and complement bit lines BL- 1 * through BL-M* of array  110 . Address buffer  114  also is coupled to control word line decoder  116 . Word line decoder  116  and bit line decoder  118  selectably access memory cells  112 -ij in response to address signals that are provided on address lines  120  from electronic system  101  during write and read operations. 
   In operation, memory  100  receives an address of a particular memory cell at address buffer  114 . For example, electronic system  101  may provide address buffer  114  with the address for cell  112 - 11  of array  110 . Address buffer  114  identifies word line WL- 1  for memory cell  112 - 11  to word line decoder  116 . Word line decoder  116  selectively activates word line WL- 1  to activate access transistor  130 - 1 j of each memory cell  112 - 1 j that is connected to word line WL- 1 . Bit line decoder  118  selects bit line BL- 1  for memory cell  112 - 11 . For a write operation, data received by input/output circuitry is coupled to bit lines BL- 1  through access transistor  130 - 11  to charge or discharge storage capacitor  132 - 11  of memory cell  112 - 11  to represent binary data. For a read operation, bit line BL- 1  of array  110  is equilibrated with bit line BL- 1 *. Data stored in memory cell  112 - 11 , as represented by the charge on its storage capacitor  132 - 11 , is coupled to bit line BL- 1  of array  110 . The difference in charge in bit line BL- 1  and bit line BL- 1 * is amplified, and a corresponding voltage level is provided to the input/output circuits. 
     FIGS. 2 through 4  illustrate an embodiment of a memory cell with a vertical transistor and trench capacitor for use, for example, in memory device  100  of  FIG. 1 . Specifically,  FIG. 2  is a plan view of a layout of a number of memory cells indicated generally at  202 A through  202 D in array  200 .  FIG. 2  depicts only four memory cells. It is understood, however, that array  200  may include a larger number of memory cells even though only four are depicted here. 
   Each memory cell is constructed in a similar manner. Thus, only memory cell  202 C is described herein in detail. Memory cell  202 C includes pillar  204  of single crystal semiconductor material, e.g., silicon, that is divided into second source/drain region  206 , body region  208 , and first source/drain region  210  to form access transistor  211 . Pillar  204  extends vertically outward from substrate  201  of, for example, p− silicon. Second source/drain region  206  and first source/drain region  210  each comprise, for example, n+ silicon and body region  208  comprises p− silicon. 
   Word line  212  passes body region  208  of access transistor  211  in isolation trench  214 . Word line  212  is separated from body region  208  of access transistor  211  by gate oxide  216  such that the portion of word line  212  adjacent to body region  208  operates as a gate for access transistor  211 . Word line  212  may comprise, for example, n+ poly-silicon material that is deposited in isolation trench  214  using an edge-defined technique such that word line  212  is less than a minimum feature size, F, for the lithographic technique used to fabricate array  200 . Passing word line  213  is also formed in trench  214 . Cell  202 C is coupled with cell  202 B by bit line  218 . 
   Memory cell  202 C also includes storage capacitor  219  for storing data in the cell. A first plate of capacitor  219  for memory cell  202 C is integral with first source/drain region  210  of access transistor  211 . Thus, memory cell  202 C may be more easily realizable when compared to conventional vertical transistors since there is no need for a contact between first source/drain region  210  and capacitor  219 . Second plate  220  of capacitor  219  is common to all of the capacitors of array  200 . Second plate  220  comprises a mesh or grid of n+ poly-silicon formed in deep trenches that surrounds at least a portion of first source/drain region  210  of each pillar  204 A through  204 D. Second plate  220  is grounded by contact with substrate  201  underneath the trenches. Second plate  220  is separated first source/drain region  210  by gate oxide  222 . 
   With this construction for memory cell  202 C, access transistor  211  is like a silicon on insulator device. Three sides of the transistor are insulated by thick oxide in the shallow trench. If the doping in pillar  204  is low and the width of the post is sub-micron, then body region  208  can act as a “fully-depleted” silicon on insulator transistor with no body or substrate to contact. This is desirable to avoid floating body effects in silicon on insulated transistors and is achievable due to the use of sub-micron dimensions in access transistor  211 . 
     FIG. 4  is a schematic diagram that illustrates an effective circuit diagram for the embodiment of  FIGS. 2 and 3 . It is noted that storage capacitor  219  formed by first source/drain region  210  and second plate  220  is depicted as four separate capacitors. This represents that the first plate  220  surrounds second source/drain region  210  which increases the charge storage capacitance and stored charge for the memory cell. It is also noted that second plate  220  is maintained at a constant potential, e.g., ground potential. 
   As shown in  FIG. 2 , the memory cells of array  200  are four-square feature (4F 2 ) memory cells. Using cell  202 D as an example, the surface area of cell  202 D is calculated based on linear dimensions in the bit line and word line directions. In the bit line direction, the distance from one edge of cell  202 D to a common edge of adjacent cell  202 A is approximately 2 minimum feature sizes (2F). In the word line direction, the dimension is taken from the midpoint of isolation trenches on either side of memory cell  202 D. Again, this is approximately two minimum feature sizes (2F). Thus, the size of the cell is 4F 2 . This size is much smaller than the current cells with stacked capacitors or trenched capacitors. 
     FIGS. 5A through 5M  illustrate one embodiment of a process for fabricating an array of memory cells, indicated generally at  299 , according to the teachings of the present invention. In this example, dimensions are given that are appropriate to a 0.2 micrometer lithographic image size. For other image sizes, the vertical dimensions can be scaled accordingly. 
   As shown in  FIG. 5A , the method begins with substrate  300 . Substrate  300  comprises, for example, a P-type silicon wafer, layer of P− silicon material, or other appropriate substrate material. As shown in  FIG. 5A , substrate  300  is a single unbonded substrate. Layer  302  is formed, for example, by epitaxial growth outwardly from layer  300 . Layer  302  comprises single crystalline N+ silicon that is approximately 3.5 micrometers thick. Layer  304  is formed outwardly from layer  302  by epitaxial growth of single crystalline P− silicon of approximately 0.5 microns. Layer  306  is formed by ion implantation of donor dopant into layer  304  such that layer  306  comprises single crystalline N+ silicon with a depth of approximately 0.1 microns. 
   A thin layer of silicon dioxide (SiO 2 ), referred to as pad oxide  308 , is deposited or grown on layer  306 . Pad oxide  308  has a thickness of approximately 10 nanometers. A layer of silicon nitride (Si 3 N 4 ), referred to as pad nitride  310 , is deposited on pad oxide  308 . Pad nitride  310  has a thickness of approximately 200 nanometers. 
   Photo resist layer  312  is deposited outwardly from layer  310 . Photo resist layer  312  is patterned with a mask to define openings  314  in layer  312  to be used in selective etching. As shown in  FIG. 5B , column isolation trenches  316  are etched through openings  314  in photo resist layer  312  in a direction parallel to which the bit lines will be formed. Column isolation trenches  316  extend down through nitride layer  310 , oxide layer  308 , N+ layer  306 , P− layer  304 , N+ layer  302 , and into substrate  300 . 
   A thin thermal protective oxide layer  318  is grown on exposed surfaces of substrate  300  and layers  302 ,  304 , and  306 . Layer  318  is used to protect substrate  300  and layers  302 ,  304  and  306  during subsequent process step. 
   A layer of intrinsic poly-silicon  320  is deposited by chemical vapor deposition (CVD) to fill column isolation trenches  316 . Layer  320  is etched by reactive ion etching (RIE) such that layer  320  is recessed below a top of layer  302 . Layer  322  of silicon nitride (Si 3 N 4 ) is deposited by, for example, chemical vapor deposition to fill trenches  316 . Layer  322  is planarized back to a level of layer  310  using, for example, chemical mechanical polishing (CMP) or other suitable planarization technique to produce the structure shown in  FIG. 5C . 
   As shown in  FIG. 5D , layer  324  of photo resist material is deposited outwardly from nitride layers  322  and  310 . Layer  324  is exposed through a mask to define openings  326  in layer  324 . Openings  326  are orthogonal to trenches  316  that were filled by intrinsic poly-silicon layer  320  and nitride layer  322 . Next, nitride layers  310  and  322  are etched to a depth sufficient to expose a working surface  328  of layer  306 . It is noted that at this point layer  320  of intrinsic poly-silicon is still covered by a portion of nitride layer  322 . 
   As shown in  FIG. 5E , the portion of layers  306 ,  304 , and  302  that are exposed in openings  326  are selectively etched down to a distance approximately equal to column isolation trenches  316 . A thin thermal protective oxide is grown on the exposed silicon of layers  302 ,  304  and  306  as well as an exposed upper surface of layer  300 . This oxide layer is labeled  330  in  FIG. 5E . 
   As shown in  FIG. 5F , the remaining nitride layer  322  exposed in openings  326  is directionally etched to expose layer of intrinsic poly-silicon  320 . It is noted that nitride layer  322  and nitride layer  310  remain intact under the photo resist layer  324 . Layer of intrinsic poly-silicon  320  is next isotropically etched using a silicon etchant which does not attack oxide or nitride layers. Next, an isotropic oxide etch is performed to remove all exposed thin oxide. The photo resist layer  324  is removed. At this point, the method has produced the structure shown in  FIG. 5G . This structure includes a nitride bridge formed from nitride layers  310  and  322  that extends orthogonal to column isolation trenches  316  and covers the remaining portions of layers  302 ,  304 , and  306 . The structure also includes row isolation trenches  332  that are orthogonal to column isolation trenches  316 . The structure of  FIG. 5G  also includes pillars  334 A through  334 D of single crystal silicon material. Pillars  334 A through  334 D form the basis for individual memory cells for the memory array formed by the process. 
   An optional metal contact  336  may be formed by, for example, deposition of a collimated refractory metal deposition, e.g., titanium, tungsten, or a similar refractory metal. This provides an ohmic metal contact for a capacitor plate on a surface  335  of substrate  300 . 
   Dielectric layer  338  is deposited or grown on sidewalls of layer  302  of pillars  334 A through  334 D. Layer  338  acts as the dielectric for the storage capacitors of array  299  of memory cells. If contact  336  was previously deposited on a surface of substrate  300 , dielectric layer  338  should be directionally etched to clear dielectric material from the bottom of row isolation trench  332 . 
   Next, a common plate for all of the memory cells of array  299  is formed by a chemical vapor deposition of N+ poly-silicon or other appropriate refractory conductor in column isolation trenches  316  and row isolation trenches  332 . In this manner, conductor mesh or grid  340  is formed so as to surround each of pillars  334 A through  334 D. Mesh  340  is planarized and etched back to a level approximately at the bottom of the nitride bridge formed by nitride layers  322  and  310  as shown in  FIG. 5H . An additional etch is performed to remove any remaining exposed capacitor dielectric of layer  338  from the sides of semiconductor pillars  334 A through  334 D. 
   Referring to  FIG. 51 , layer  350  of silicon nitride (Si 3 N 4 ) is formed by, for example, chemical vapor deposition to a thickness of approximately 20 nanometers. Layer  350  is directionally etched to leave silicon nitride on sidewalls  352  of pillars  344 B and  344 C as shown in  FIG. 5I . It is noted that silicon nitride is also deposited on the sidewalls of pillars  334 A and  334 B. Layer  354  of thermal silicon dioxide (SiO 2 ) is grown or deposited to a depth of approximately 100 nanometers on exposed surfaces  356  of mesh  340 . Layer  350  is then removed. 
   Referring to  FIG. 5J , layer  358  of intrinsic poly-silicon is deposited, for example, by chemical vapor deposition with a thickness of approximately 50 nanometers. Layer  358  is directionally etched to the leave intrinsic poly-silicon on sidewalls  352  of pillars  334 B and  334 C as shown in  FIG. 5J . It is noted that layer  358  is also formed on pillars  334 A and  334 D. 
   As shown in  FIGS. 5J and 5K , layer  360  of photo resist material is deposited and masked to expose alternate sidewalls  352  of pillars  334 A through  334 D. Exposed portions of layer  358  in openings  362  through photo resist layer  360  are selectively etched to expose sidewalls  352  of pillars  334 A through  334 D. Photo resist layer  360  is removed and gate oxide layer  364  is grown on exposed sidewalls  352  of pillars  334 A through  334 D. Additionally, gate oxide layer  364  is also deposited on remaining intrinsic poly-silicon layers  358 . 
   Referring to  FIG. 5L , word line conductors  366  are deposited by, for example, chemical vapor deposition of n+ poly-silicon or other refractory metal to a thickness of approximately 50 nanometers. Conductors  366  are directionally and selectively etched to leave on sidewalls  352  of pillars  334 A through  334 D and on exposed surfaces of intrinsic poly-silicon layer  358 . 
   Next, a brief oxide etch is used to expose the top surface of intrinsic poly-silicon layer  358 . Layer  358  is then selectively etched to remove the remaining intrinsic poly-silicon using an etchant such as KOH and alcohol, ethylene and pyrocatechol or gallic acid (as described in U.S. Pat. No. 5,106,987 issued to W. D. Pricer). Next, an oxide layer is deposited by, for example, chemical vapor deposition to fill the space vacated by layer  358  and to fill in between word line conductors  366 . Additionally conventional process steps are used to add bit lines  368  so as to produce the structure shown in  FIG. 5M  including memory cells  369 A through  369 D. 
   CONCLUSION 
   Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. For example, the semiconductor materials and dimensions specified in this application are given by way of example and not by way of limitation. Other appropriate material can be substituted without departing from the spirit and scope of the invention.