Patent Publication Number: US-2023163033-A1

Title: Display panel

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This is a continuation application of and claims the priority benefit of U.S. application Ser. No. 17/315,371, filed on May 10, 2021, which claims the priority benefit of China application serial no. 202010499270.7, filed on Jun. 4, 2020. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
    
    
     BACKGROUND 
     Technical Field 
     The disclosure relates to a panel, and more particularly to a panel provided with a peripheral region. 
     Description of Related Art 
     For a small-sized display device, since the size and pixel pitch of the display panel are relatively small, the lower peripheral region of the display panel lacks a sufficient circuit placement space in the horizontal direction to dispose a light on test (LOT) circuit. That is to say, a small-sized display device has to dispose the LOT circuit by increasing the size of the display panel, so the small-sized display device fails to achieve the effect of a narrow bezel. In view of this, the following proposes several solutions in the embodiments. 
     SUMMARY 
     The disclosure proposes a display provided with a peripheral region, which can effectively reduce the circuit placement space of peripheral region. 
     According to an embodiment of the disclosure, the panel of the disclosure includes a plurality of signal lines and a plurality of transistors. The plurality of transistors are disposed in the peripheral region. Each of the plurality of transistors comprises a gate, a source and a drain. At least one of the plurality of signal lines is electrically connected to the source or the drain of one of the plurality of transistors. The foresaid signal line includes a turning portion. The turning portion is disposed in the peripheral region. 
     Based on the above, the panel of the disclosure may dispose the turning portion of the signal line in the peripheral region, so as to effectively save the circuit placement space of the peripheral region of the panel. 
     To make the aforementioned features and advantages of the disclosure more comprehensible, embodiments accompanied with drawings are described in detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. 
         FIG.  1    is a schematic view of a testing circuit according to the first embodiment of the disclosure. 
         FIG.  2    is a schematic view of a testing circuit according to the second embodiment of the disclosure. 
         FIG.  3    is a schematic view of a process layout of a circuit according to the first embodiment of the disclosure. 
         FIG.  4    is a cross-sectional structure view of a transistor according to an embodiment of the disclosure. 
         FIG.  5    is a schematic view of a testing circuit according to the third embodiment of the disclosure. 
         FIG.  6    is a schematic view of a testing circuit according to the fourth embodiment of the disclosure. 
         FIG.  7    is a schematic view of a process layout of a circuit according to the third embodiment of the disclosure. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Throughout the specification and appended claims of the disclosure, certain words are used to refer to specific elements. Persons skilled in the art should understand that electronic device manufacturers may refer to the same elements by different names. The text does not intend to distinguish the elements with the same function but different names. In the following specification and claims, the words “comprise” and “include” are open-ended words and thus should be interpreted as the meaning of “comprising but not limited to . . . .” 
     Directional terms mentioned in the text, such as “upper,” “lower,” “front,” “back,” “left,” “right,” etc., merely refer to directions with reference to the accompanying drawings. Therefore, the directional terms used are used to illustrate, but not to limit the disclosure. In the drawings, each drawing shows the general features of the methods, structures, and/or materials used in specific embodiments. However, the drawings should not be interpreted as defining or limiting the scope or nature covered by the embodiments. For example, for the sake of clarity, the relative size, thickness, and position of each film layer, region, and/or structure may be shrunk or enlarged. 
     In some embodiments of the disclosure, terms related to engagement and connection, such as “connect”, “interconnect”, etc., unless specifically defined, may mean that two structures are in direct contact, or that two structures are not in direct contact and another structure is provided between the two structures. The terms related to engagement and connection may also include the case where two structures are movable or two structures are fixed. In addition, the term “electrical connection” includes any direct and indirect electrical connection means. 
     The ordinal numbers used in the specification and claims, such as “first”, “second”, and the like, are used to modify elements, but neither imply nor represent that the/the plurality of element(s) has/have any previous ordinal numbers, and represent neither the order of an element and another element nor the order of the manufacturing method. The ordinal numbers are merely used to clearly distinguish an element with a certain name from another element with the same name. It is possible that the same term is not used in the claims and the specification, accordingly, the first element in the specification may be the second element in the claims. It should be understood that the following embodiments may replace, reorganize, and mix the technical features of several different embodiments to complete other embodiments without departing from the spirit of the disclosure. 
     In each embodiment of the disclosure, a display panel may, for example, include a liquid crystal, a light emitting diode, a quantum dot (QD), fluorescence, phosphor, other suitable materials, or a combination of the foregoing, but is not limited thereto. The light emitting diode may, for example, include an organic light emitting diode (OLED), a mini LED, a micro LED, a quantum dot LED (QLED or QDLED), fluorescence, phosphor, or other suitable materials, and the materials may be arbitrarily arranged and combined, but is not limited thereto. In each embodiment of the disclosure, the display panel may be, for example, disposed in a virtual reality (VR) device or other small-sized display devices. 
       FIG.  1    is a schematic view of a testing circuit according to the first embodiment of the disclosure. Referring to  FIG.  1   , a circuit  100  includes a testing circuit and a plurality of signal lines D 1  to D 6 . The circuit  100  is a partial circuit of a peripheral region (surrounding area) on a substrate of the display panel. In the present embodiment, the testing circuit includes a plurality of transistors  110 _ 1  to  110 _ 6  electrically connected to the signal lines D 1  to D 6 , and includes a plurality of testing signal lines V 1  to V 6  and a control line SB. In the present embodiment, the transistors  110 _ 1  to  110 _ 6  are disposed in two groups, which may be divided into an odd group (the transistors  110 _ 1 ,  110 _ 3 , and  110 _ 5 ) and an even group (the transistors  110 _ 2 ,  110 _ 4 , and  110 _ 6 ). The two groups of transistors are respectively arranged in a first direction P 1  (horizontal direction), and the two groups of transistors are disposed in two rows in a second direction P 2  (vertical direction). The first direction P 1 , the second direction P 2 , and a third direction P 3  are perpendicular to each other. The two groups of transistors are separately disposed on both sides of a wire region of the testing signal lines V 1  to V 6  and the control line SB. 
     It is worth noting that the number of transistors and the number of signal lines of the testing circuit of the disclosure are merely examples, and are not limited to  FIG.  1   . The number of transistors and the number of signal lines of the testing circuit of a real product are far greater than the numbers as shown in  FIG.  1   , and may be determined according to a panel specification, a panel resolution, or a special testing requirement. In the present embodiment, the plurality of transistors of the disclosure are disposed in at least two groups, and the number of transistors of each group of the at least two groups is less than a total number of the signal lines. In addition, extending toward the second direction P 2  from the signal lines D 1  to D 6 , a display panel  10  may further include a pixel array. The signal lines D 1  to D 6  may be, for example, coupled to a plurality of data lines from the first column to the sixth column of the pixel array, and the testing circuit may, for example, further include another plurality of transistors along the first direction P 1 . The configuration of the another plurality of transistors may be the same as the configuration of the transistors  110 _ 1  to  110 _ 6 , and the another plurality of transistors are, for example, electrically connected to the data lines from the seventh column to the twelfth column of the pixel array. 
     In the present embodiment, the transistors  110 _ 1  to  110 _ 6  respectively include gates  111 _ 1  to  111 _ 6 , drains  112 _ 1  to  112 _ 6 , and sources  113 _ 1  to  113 _ 6 . The gates  111 _ 1  to  111 _ 6  of the transistors  110 _ 1  to  110 _ 6  are electrically connected to the control line SB to receive a control signal. The drains  112 _ 1  to  112 _ 6  of the transistors  110 _ 1  to  110 _ 6  are respectively electrically connected to the testing signal lines V 1  to V 6  to respectively receive testing signals. The sources  113 _ 1  to  113 _ 6  of the transistors  110 _ 1  to  110 _ 6  are respectively electrically connected to the signal lines D 1  to D 6  to respectively provide driving signals to corresponding columns of pixel units in the corresponding pixel array through the signal lines D 1  to D 6 , so as to, for example, perform a light on test (LOT). 
     More specifically, in the present embodiment, the control line SB and the testing signal lines V 1  to V 6  are sequentially arranged along the second direction P 2 . The transistors  110 _ 1 ,  110 _ 3 , and  110 _ 5  in the odd group are configured on a side adjacent to the control line SB. The transistors  110 _ 2 ,  110 _ 4 , and  110 _ 6  in the even group are configured on a side adjacent to the testing signal line V 6 , and are closer to the pixel array than the transistors  110 _ 1 ,  110 _ 3 , and  110 _ 5  in the odd group. The drains  112 _ 1 ,  112 _ 3 , and  112 _ 5  of the transistors  110 _ 1 ,  110 _ 3 , and  110 _ 5  in the odd group are sequentially electrically connected to the odd-numbered testing signal lines V 1 , V 3 , and V 5 , and the sources  113 _ 1 ,  113 _ 3 , and  113 _ 5  are sequentially electrically connected to the odd-numbered signal lines D 1 , D 3 , and D 5 . The drains  112 _ 2 ,  112 _ 4 , and  112 _ 6  of the transistors  110 _ 2 ,  110 _ 4 , and  110 _ 6  in the even group are sequentially electrically connected to the even-numbered testing signal lines V 2 , V 4 , and V 6 , and the sources  113 _ 2 ,  113 _ 4 , and  113 _ 6  are sequentially electrically connected to the even-numbered signal lines D 2 , D 4 , and D 6 . Therefore, since the testing circuit of the present embodiment divides the transistors  110 _ 1  to  110 _ 6  into the odd group (the transistors  110 _ 1 ,  110 _ 3 , and  110 _ 5 ) and the even group (the transistors  110 _ 2 ,  110 _ 4 , and  110 _ 6 ) to separately dispose the transistors in different rows, the testing circuit of the present embodiment can effectively save the circuit placement space in the first direction P 1 . 
     However, the configuration order of the control line SB and the testing signal lines V 1  to V 6  of the disclosure is not limited to  FIG.  1   . In an embodiment, the transistors  110 _ 2 ,  110 _ 4 , and  110 _ 6  in the even group are closer to the pixel array than the transistors  110 _ 1 ,  110 _ 3 , and  110 _ 5  in the odd group. However, the configuration order of the control line SB and the testing signal lines V 1  to V 6  may be sequentially arranged along a direction opposite to the second direction P 2 . 
       FIG.  2    is a schematic view of a testing circuit according to the second embodiment of the disclosure. Referring to  FIG.  2   , a circuit  200  includes a testing circuit and a plurality of signal lines D 1  to D 6 . The testing circuit of the present embodiment includes a plurality of transistors  210 _ 1  to  210 _ 6 , a plurality of testing signal lines V 1  to V 6 , and a control line SB. The plurality of transistors  210 _ 1  to  210 _ 6  are electrically connected to the signal lines D 1  to D 6 . In the present embodiment, the transistors  210 _ 1  to  210 _ 6  are disposed in two groups, which may be divided into an odd group (the transistors  210 _ 1 ,  210 _ 3 , and  210 _ 5 ) and an even group (the transistors  210 _ 2 ,  210 _ 4 , and  210 _ 6 ). The two groups of transistors are respectively arranged in a first direction P 1  (horizontal direction), and the two groups of transistors are disposed in two rows in a second direction P 2  (vertical direction). The two groups of transistors are separately disposed on both sides of a wire region of the testing signal lines V 1  to V 6  and the control line SB. 
     In the present embodiment, the transistors  210 _ 1  to  210 _ 6  respectively include gates  211 _ 1  to  211 _ 6 , drains  212 _ 1  to  212 _ 6 , and sources  213 _ 1  to  213 _ 6 . The gates  211 _ 1  to  211 _ 6  of the transistors  210 _ 1  to  210 _ 6  are electrically connected to the control line SB to receive a control signal. The drains  212 _ 1  to  212 _ 6  of the transistors  210 _ 1  to  210 _ 6  are respectively electrically connected to the testing signal lines V 1  to V 6  to respectively receive testing signals. The sources  213 _ 1  to  213 _ 6  of the transistors  210 _ 1  to  210 _ 6  are respectively electrically connected to the signal lines D 1  to D 6  to respectively provide driving signals to the corresponding columns of pixel units in the corresponding pixel array through the signal lines D 1  to D 6 , so as to, for example, perform a LOT. Moreover, the electrical connection relationship of the transistors  210 _ 1  to  210 _ 6  with the testing signal lines V 1  to V 6 , the control line SB, and the signal lines D 1  to D 6  is the same as the electrical connection relationship of the transistors  110 _ 1  to  110 _ 6  of  FIG.  1   . 
     Different from  FIG.  1   , in the present embodiment, the control line SB and the testing signal lines V 1  to V 6  are sequentially arranged along the direction opposite to the second direction P 2 . The transistors  210 _ 1 ,  210 _ 3 , and  210 _ 5  in the odd group are configured on a side adjacent to the testing signal line V 1 . The transistors  210 _ 2 ,  210 _ 4 , and  210 _ 6  in the even group are configured on a side adjacent to the control line SB, and are farther away from the pixel array than the transistors  210 _ 1 ,  210 _ 3 , and  210 _ 5  in the odd group. Therefore, since the testing circuit of the present embodiment divides the transistors  210 _ 1  to  210 _ 6  into the odd group (the transistors  210 _ 1 ,  210 _ 3 , and  210 _ 5 ) and the even group (the transistors  210 _ 2 ,  210 _ 4 , and  210 _ 6 ) to separately dispose the transistors in different rows, the testing circuit of the present embodiment can effectively save the circuit placement space in the first direction P 1 . 
     However, the configuration order of the control line SB and the testing signal lines V 1  to V 6  of the disclosure is not limited to  FIG.  2   . In an embodiment, the transistors  210 _ 2 ,  210 _ 4 , and  210 _ 6  in the even group are also farther away from the pixel array than the transistors  210 _ 1 ,  210 _ 3 , and  210 _ 5  in the odd group. However, the configuration order of the testing signal lines V 1  to V 6  and the control line SB may be sequentially arranged along the second direction P 2 . 
     In addition, in a testing embodiment, when a circuit analysis is performed on a certain testing circuit, if testing signal lines of the testing circuit are located in the middle or between two rows of transistors of the testing circuit, and signal lines electrically connected to the upper and lower rows of transistors are respectively jump cut at intervals, for example, every two adjacent transistors are respectively electrically connected to two discontinuously arranged signal lines, the testing circuit may be regarded as implementing the structural design of the testing circuit of  FIG.  1    or  FIG.  2    of the disclosure. 
       FIG.  3    is a schematic view of a process layout of a circuit according to the first embodiment of the disclosure. The process layout of the circuit  100  of  FIG.  1    may be as shown in  FIG.  3   . Referring to  FIG.  3   , in the present embodiment, a circuit  300  includes a testing circuit and a plurality of signal lines D 1  to D 6 . The testing circuit of the present embodiment includes a plurality of transistors  310 _ 1  to  310 _ 6  electrically connected to the signal lines D 1  to D 6 , and includes a plurality of testing signal lines V 1  to V 6  and a control line SB. In the present embodiment, gates  311 _ 1  to  311 _ 6  of the transistors  310 _ 1  to  310 _ 6  and drains  312 _ 1  to  312 _ 6  and sources  313 _ 1  to  313 _ 6  of the transistors  310 _ 1  to  310 _ 6  are formed on metal layers of different heights, and the drains  312 _ 1  to  312 _ 6  and the sources  313 _ 1  to  313 _ 6  of the transistors  310 _ 1  to  310 _ 6  are formed on metal layers of the same height. In the present embodiment, the control line SB and the testing signal lines V 1  to V 6  are sequentially arranged along the second direction P 2 . The transistors  310 _ 1 ,  310 _ 3 , and  310 _ 5  in the odd group are configured on a side adjacent to the control line. The transistors  310 _ 2 ,  310 _ 4 , and  310 _ 6  in the even group are configured on a side adjacent to the testing signal line V 6 , and are closer to the pixel array than the transistors  310 _ 1 ,  310 _ 3 , and  310 _ 5  in the odd group. 
     In the present embodiment, graphics with the same pattern in  FIG.  3    may be regarded as being located on a same metal layer of a display panel  30 . Specifically, in the present embodiment, the gates  311 _ 1  to  311 _ 6  of the transistors  310 _ 1  to  310 _ 6  are extended below a metal wire of the control line SB through wires of a same metal layer, and are electrically connected to the control line SB through vias h 1 , h 8 , and h 15 . In the present embodiment, the drains  312 _ 1  to  312 _ 5  of the transistors  310 _ 1  to  310 _ 5  are extended to respective corresponding vias h 2 , h 5 , h 9 , h 12 , and h 16  through wires of a same metal layer, then extended below metal wires of the respective corresponding testing signal lines V 1  to V 5  through wires electrically connected to the vias h 2 , h 5 , h 9 , h 12 , and h 16  and located on a metal layer below the testing signal lines V 1  to V 6  and the control line SB, and finally electrically connected to the respective corresponding testing signal lines V 1  to V 5  through respective corresponding vias h 3 , h 6 , h 10 , h 13 , and h 17 . In addition, since the drain  312 _ 6  of the transistor  310 _ 6  is not required to cross other signal lines, the drain  312 _ 6  of the transistor  310 _ 6  may be directly extended and electrically connected to the testing signal line V 6  through the wires of the same metal layer. In the present embodiment, the sources  313 _ 1  to  313 _ 6  of the transistors  310 _ 1  to  310 _ 6  are extended to respective corresponding vias h 4 , h 7 , h 11 , h 14 , h 18 , and h 19  through wires of a same metal layer, and then electrically connected to the respective corresponding signal lines D 1  to D 6  through the vias h 4 , h 7 , h 11 , h 14 , h 18 , and h 19 . In addition, the signal lines D 1  to D 6  are extended, toward the second direction P 2 , to corresponding columns of pixel units in the pixel array of the display panel  30  through wires of a metal layer located above the testing signal lines V 1  to V 6  and the control line SB. Therefore, the process layout of the testing circuit of the present embodiment can effectively save the circuit placement space of the testing circuit in the first direction P 1 . 
     In addition, it is worth noting that since the wire distances extended from the gates  311 _ 1  to  311 _ 6  and the drains  312 _ 1  to  312 _ 5  of the transistors  310 _ 1  to  310 _ 5  of the transistors  310 _ 1  to  310 _ 5  to the respective vias are relatively close, to avoid short circuit between the wires extended from the gates  311 _ 1  to  311 _ 6  and the drains  312 _ 1  to  312 _ 5  of the transistors  310 _ 1  to  310 _ 5  to the respective vias, all the wires extended from the drains  312 _ 1  to  312 _ 5  of the transistors  310 _ 1  to  310 _ 5  to the respective corresponding vias h 3 , h 6 , h 10 , h 13 , and h 17  are extended for a distance toward a direction (opposite to the first direction P 1 ) away from the gates  311 _ 1  to  311 _ 6 , and then extended to the respective corresponding vias h 3 , h 6 , h 10 , h 13 , and h 17 . 
       FIG.  4    is a cross-sectional structure view of a transistor according to an embodiment of the disclosure. The cross-sectional structure of the present embodiment may be, for example, a cross-sectional structure of a plane (viewed toward the second direction P 2 ) formed by the transistor  310 _ 2  of  FIG.  3    along the first direction P 1  and the third direction P 3  of a reference line RV, but the disclosure is not limited thereto. All of the transistors  310 _ 1  to  310 _ 6  have the cross-sectional structure of a transistor  400  of the present embodiment. Taking the cross-section of the transistor  310 _ 2  as an example, referring to  FIG.  4   , the transistor  400  is formed on a substrate in the peripheral region of the display panel. On the display panel, a substrate  401 , a buffer layer  402 , an active layer  4031 , a gate insulating layer  403 , a metal interlayer dielectric layer  404 , an insulating layer  405 , a planarization layer  406 , and an insulating layer  407  are sequentially formed in the third direction P 3 . In the present embodiment, a lightly doped region R 1  and heavily doped regions R 2  and R 2 ′ are formed and included in the active layer  4301 , and the lightly doped region R 1  is located between the heavily doped regions R 2  and R 2 ′. In the present embodiment, a metal layer  410  of the gate of the transistor  400  is formed on the gate insulating layer  403 . A metal layer  420  of the drain and the source of the transistor  400  is formed on the metal interlayer dielectric layer  404  and is electrically connected to the heavily doped regions R 2  and R 2 ′ by penetrating the gate insulating layer  403  and the metal interlayer dielectric layer  404 . In addition, a metal layer  430  passing through the signal line above the drain of the transistor  400  may be formed on the insulating layer  405 . That is, the metal layer  430  passing through the signal line above the drain of the transistor  400 , the metal layer  410  of the gate of the transistor  400 , and the metal layer  420  of the drain and the source of the transistor  400  are respectively formed on metal layers of different heights. 
       FIG.  5    is a schematic view of a testing circuit according to the third embodiment of the disclosure. Referring to  FIG.  5   , a circuit  500  includes a testing circuit and a plurality of signal lines D 1  to D 6 . The testing circuit of the present embodiment includes a plurality of transistors  510 _ 1  to  510 _ 6  electrically connected to the signal lines D 1  to D 6 , and includes a plurality of testing signal lines V 1  to V 6  and control lines SB 1  and SB 2 . In the present embodiment, the transistors  510 _ 1  to  510 _ 6  are disposed in two groups, which may be divided into an odd group (the transistors  510 _ 1 ,  510 _ 3 , and  510 _ 5 ) and an even group (the transistors  510 _ 2 ,  510 _ 4 , and  510 _ 6 ). The two groups of transistors are respectively arranged in a first direction P 1  (horizontal direction), and the two groups of transistors are disposed in two rows in a second direction P 2  (vertical direction). The two groups of transistors are separately disposed on both sides of a wire region of the testing signal lines V 1  to V 6 . In addition, the control lines SB 1  and SB 2  are located outside the two rows of the transistors  510 _ 1  to  510 _ 6 . 
     In the present embodiment, the transistors  510 _ 1  to  510 _ 6  respectively include gates  511 _ 1  to  511 _ 6 , drains  512 _ 1  to  512 _ 6 , and sources  513 _ 1  to  513 _ 6 . The gates  511 _ 1 ,  511 _ 3 , and  511 _ 5  of the transistors  510 _ 1 ,  510 _ 3 , and  510 _ 5  in the odd group are electrically connected to the control line SB 1  to receive a control signal. The gates  511 _ 2 ,  511 _ 4 , and  511 _ 6  of the transistors  510 _ 2 ,  510 _ 4 , and  510 _ 6  in the even group are electrically connected to the control line SB 2  to receive another control signal. The drains  512 _ 1  to  512 _ 6  of the transistors  510 _ 1  to  510 _ 6  are respectively electrically connected to the testing signal lines V 1  to V 6  to respectively receive testing signals. The sources  513 _ 1  to  513 _ 6  of the transistors  510 _ 1  to  510 _ 6  are respectively electrically connected to the signal lines D 1  to D 6  to respectively provide driving signals to corresponding columns of pixel units in the corresponding pixel array through the signal lines D 1  to D 6 , so as to, for example, perform a LOT. 
     More specifically, in the present embodiment, the control line SB 1 , the testing signal lines V 1  to V 6 , and the control line SB 2  are sequentially arranged along the second direction P 2 . The transistors  510 _ 1 ,  510 _ 3 , and  510 _ 5  in the odd group are configured between the testing signal line V 1  and the control line SB 1 . The transistors  510 _ 2 ,  510 _ 4 , and  510 _ 6  in the even group are configured between the testing signal line V 6  and the control line SB 2 , and are closer to the pixel array than the transistors  510 _ 1 ,  510 _ 3 , and  510 _ 5  in the odd group. The drains  512 _ 1 ,  512 _ 3 , and  512 _ 5  of the transistors  510 _ 1 ,  510 _ 3 , and  510 _ 5  in the odd group are sequentially electrically connected to the odd-numbered testing signal lines V 1 , V 3 , and V 5 , and the sources  513 _ 1 ,  513 _ 3 , and  513 _ 5  are sequentially electrically connected to the odd-numbered signal lines D 1 , D 3 , and D 5 . The drains  512 _ 2 ,  512 _ 4 , and  512 _ 6  of the transistors  510 _ 2 ,  510 _ 4 , and  510 _ 6  in the even group are sequentially electrically connected to the even-numbered testing signal lines V 2 , V 4 , and V 6 , and the sources  513 _ 2 ,  513 _ 4 , and  513 _ 6  are sequentially electrically connected to the even-numbered signal lines D 2 , D 4 , and D 6 . Therefore, since the testing circuit of the present embodiment divides the transistors  510 _ 1  to  510 _ 6  into the odd group (the transistors  510 _ 1 ,  510 _ 3 , and  510 _ 5 ) and the even group (the transistors  510 _ 2 ,  510 _ 4 , and  510 _ 6 ) to separately dispose the transistors in different rows, the testing circuit of the present embodiment can effectively save the circuit placement space in the first direction P 1 . 
     However, the configuration order of the testing signal lines V 1  to V 6  of the disclosure is not limited to  FIG.  5   . In an embodiment, the transistors  510 _ 2 ,  510 _ 4 , and  510 _ 6  in the even group are also closer to the pixel array than the transistors  510 _ 1 ,  510 _ 3 , and  510 _ 5  in the odd group. However, the configuration order of the testing signal lines V 1  to V 6  may be sequentially arranged along a direction opposite to the second direction P 2 . 
       FIG.  6    is a schematic view of a testing circuit according to the fourth embodiment of the disclosure. Referring to  FIG.  6   , a circuit  600  includes a testing circuit and a plurality of signal lines D 1  to D 6 . The testing circuit of the present embodiment includes a plurality of transistors  610 _ 1  to  610 _ 6  electrically connected to the signal lines D 1  to D 6 , and includes a plurality of testing signal lines V 1  to V 6  and control lines SB 1  and SB 2 . In the present embodiment, the transistors  610 _ 1  to  610 _ 6  are disposed in two groups, which may be divided into an odd group (the transistors  610 _ 1 ,  610 _ 3 , and  610 _ 5 ) and an even group (the transistors  610 _ 2 ,  610 _ 4 , and  610 _ 6 ). The two groups of transistors are respectively arranged in a first direction P 1  (horizontal direction), and the two groups of transistors are disposed in two rows in a second direction P 2  (vertical direction). The two groups of transistors are separately disposed on both sides of a wire region of the testing signal lines V 1  to V 6 . In addition, the control lines SB 1  and SB 2  are located outside the two rows of the transistors  610 _ 1  to  610 _ 6 . 
     In the present embodiment, the transistors  610 _ 1  to  610 _ 6  respectively include gates  611 _ 1  to  611 _ 6 , drains  612 _ 1  to  612 _ 6 , and sources  613 _ 1  to  613 _ 6 . The gates  611 _ 1 ,  611 _ 3 , and  611 _ 5  of the transistors  610 _ 1 ,  610 _ 3 , and  610 _ 5  in the odd group are electrically connected to the control line SB 1  to receive a control signal. The gates  611 _ 2 ,  611 _ 4 , and  611 _ 6  of the transistors  610 _ 2 ,  610 _ 4 , and  610 _ 6  in the even group are electrically connected to the control line SB 2  to receive another control signal. The drains  612 _ 1  to  612 _ 6  of the transistors  610 _ 1  to  610 _ 6  are respectively electrically connected to the testing signal lines V 1  to V 6  to respectively receive testing signals. The sources  613 _ 1  to  613 _ 6  of the transistors  610 _ 1  to  610 _ 6  are respectively electrically connected to the signal lines D 1  to D 6  to respectively provide driving signals to corresponding columns of pixel units in the corresponding pixel array through the signal lines D 1  to D 6 , so as to, for example, perform a LOT. 
     Different from  FIG.  5   , in the present embodiment, the wire position of the control lines SB 1  and SB 2  is opposite to  FIG.  5   , and the testing signal lines V 1  to V 6  are sequentially arranged along a direction opposite to the second direction P 2 . The transistors  610 _ 2 ,  610 _ 4 , and  610 _ 6  in the even group are farther away from the pixel array than the transistors  610 _ 1 ,  610 _ 3 , and  610 _ 5  in the odd group. Therefore, since the testing circuit of the present embodiment divides the transistors  610 _ 1  to  610 _ 6  into the odd group (the transistors  610 _ 1 ,  610 _ 3 , and  610 _ 5 ) and the even group (the transistors  610 _ 2 ,  610 _ 4 , and  610 _ 6 ) to separately dispose the transistors in different rows, the testing circuit  600  of the present embodiment can effectively save the circuit placement space in the first direction P 1 . 
     However, the configuration order of the testing signal lines V 1  to V 6  of the disclosure is not limited to  FIG.  6   . In an embodiment, the transistors  610 _ 2 ,  610 _ 4 , and  610 _ 6  in the even group are also farther away from the pixel array than the transistors  610 _ 1 ,  610 _ 3 , and  610 _ 5  in the odd group. However, the configuration order of the testing signal lines V 1  to V 6  may be sequentially arranged along the second direction P 2 . 
     In addition, in a testing embodiment, when a circuit analysis is performed on a certain testing circuit, if testing signal lines of the testing circuit are located in the middle or between two rows of transistors of the testing circuit, and signal lines electrically connected to the upper and lower rows of transistors are respectively jump cut at intervals, for example, every two adjacent transistors are respectively electrically connected to two discontinuously arranged signal lines, the testing circuit may be regarded as implementing the structural design of the testing circuit of  FIG.  5    or  FIG.  6    of the disclosure. Alternatively, in another testing embodiment, when a circuit analysis is performed on a certain testing circuit, if the testing circuit may have two control lines located outside the two rows of transistors, the testing circuit may also be regarded as implementing the structural design of the testing circuit  500  or  600  of  FIG.  5    or  FIG.  6    of the disclosure. 
       FIG.  7    is a schematic view of a process layout of a circuit according to the third embodiment of the disclosure. The process layout of the circuit  500  of  FIG.  5    may be as shown in  FIG.  7   . Referring to  FIG.  7   , in the present embodiment, a circuit  700  includes a testing circuit and a plurality of signal lines D 1  to D 6 . The testing circuit of the present embodiment includes a plurality of transistors  710 _ 1  to  710 _ 6  electrically connected to the signal lines D 1  to D 6 , and includes a plurality of testing signal lines V 1  to V 6  and control lines SB 1  and SB 2 . In the present embodiment, gates  711 _ 1  to  711 _ 6  of the transistors  710 _ 1  to  710 _ 6  and drains  712 _ 1  to  712 _ 6  and sources  713 _ 1  to  713 _ 6  of the transistors  710 _ 1  to  710 _ 6  are formed on metal layers of different heights, and the drains  712 _ 1  to  712 _ 6  and the sources  713 _ 1  to  713 _ 6  of the transistors  710 _ 1  to  710 _ 6  are formed on metal layers of the same height. In the present embodiment, the testing signal lines V 1  to V 6  are sequentially arranged along the second direction P 2 . The transistors  710 _ 1 ,  710 _ 3 , and  710 _ 5  in the odd group are configured on a side adjacent to the testing signal line V 1 . The transistors  710 _ 2 ,  710 _ 4 , and  710 _ 6  in the even group are configured on a side adjacent to the testing signal line V 6 , and are closer to the pixel array than the transistors  710 _ 1 ,  710 _ 3 , and  710 _ 5  in the odd group. The control line SB 1  is located on a side of the transistors  710 _ 1 ,  710 _ 3 , and  710 _ 5  in the odd group away from the testing signal line V 1 , and the control line SB 2  is located on a side of the transistors  710 _ 2 ,  710 _ 4 , and  710 _ 6  in the even group away from the testing signal line V 6 . 
     In the present embodiment, the graphics with the same pattern in  FIG.  7    may be regarded as being located on a same metal layer of a display panel  70 . Specifically, in the present embodiment, the gates  711 _ 1  to  711 _ 6  of the transistors  710 _ 1  to  710 _ 6  are extended below metal wires of the respective corresponding control lines SB 1  and SB 2  through wires of a same metal layer, and are electrically connected to the respective corresponding control lines SB 1  and SB 2  through vias g 1 , g 4 , g 8 , g 12 , g 16 , and g 20 . In the present embodiment, the drains  712 _ 2  to  712 _ 5  of the transistors  710 _ 1  to  710 _ 5  are extended to respective corresponding vias g 5 , g 9 , g 13 , and g 17  through wires of a same metal layer, then extended below metal wires of the respective corresponding testing signal lines V 2  to V 5  through wires electrically connected to the vias g 5 , g 9 , g 13 , and g 17  and located on a metal layer below the testing signal lines V 1  to V 6  and the control lines SB 1  and SB 2 , and finally electrically connected to the respective corresponding testing signal lines V 2  to V 5  through respective corresponding vias g 6 , g 10 , g 14 , and g 18 . In addition, since the drains  712 _ 1  and  712 _ 6  of the transistors  710 _ 1  and  710 _ 6  are not required to cross other signal lines, the drains  712 _ 1  and  712 _ 6  of the transistors  710 _ 1  and  710 _ 6  may be directly extended and electrically connected to the testing signal lines V 1  and V 6  respectively through the wires of the same metal layer. In the present embodiment, the sources  713 _ 1  to  713 _ 6  of the transistors  710 _ 1  to  710 _ 6  are extended to respective corresponding vias g 3 , g 7 , g 11 , g 15 , g 19 , and g 21  through wires of a same metal layer, and then electrically connected to the respective corresponding signal lines D 1  to D 6  through the vias g 3 , g 7 , g 11 , g 15 , g 19 , and g 21 . In addition, the signal lines D 1  to D 6  are extended, toward the second direction P 2 , to corresponding columns of pixel units in the pixel array of the display panel  70  through wires of a metal layer located above the testing signal lines V 1  to V 6  and the control lines SB 1  and SB 2 . Therefore, the process layout of the testing circuit of the present embodiment can effectively save the circuit placement space of the testing circuit in the first direction P 1 , and effectively avoid short circuit between the wires of the gates  711 _ 1  to  711 _ 6  and the drains  712 _ 1  to  712 _ 6  of the transistors  710 _ 1  to  710 _ 6 . 
     In summary of the above, the testing circuit of the display panel of the disclosure may divide the plurality of transistors into two rows to dispose the transistors on both sides of the testing signal lines, so as to effectively reduce the circuit placement space in the horizontal direction and help achieve the effect of a narrow bezel. Moreover, the testing circuit of the display panel of the disclosure may further respectively electrically connect the two rows of transistors to the two control lines, and the two control lines are disposed on the outer side of the two rows of transistors, so as to effectively avoid short circuit between the wires of the gate and the drain of each of the transistors. 
     Finally, it should be noted that the above embodiments are merely used to illustrate the technical solutions of the disclosure and are not intended to limit them, and the features of the embodiments may be arbitrarily mixed and matched as long as they do not violate the spirit of the disclosure or conflict with each other. Although the disclosure has been described in detail with reference to the above embodiments, persons of ordinary skill in the art should understand that they may still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents, and that such modifications or replacements do not cause the corresponding technical solutions to substantially deviate from the scope of the technical solutions of the embodiments of the disclosure.