Patent Publication Number: US-7904665-B2

Title: Multiprocessor system and its operational method

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a distributed shared memory type multiprocessor system configured using multiple cells. In particular, the present invention relates to a coherency technology in distributed shared memory type multiprocessor systems having multiple cells. 
     2. Description of the Related Art 
     In the field of computer systems, “a multiprocessor system” consisting of multiple processors is known. Among the multiprocessor systems, those which are constituted of multiple cells (or multiple nodes) wherein multiple cells are connected by buses and switches are well known. Each of the multiple cells independently contains a processor and main memory, and a “shared memory” is configured logically with all main memories (For example, referred to the Japanese Patent Laid Open Nos. 2000-67024, 2000-259596, 1994-110844, 1999-219343, and 2003-216597). Memories are distributed and shared by multiple processors so that the multiple processors may be also called a “distributed shared memory type (DSM) multiprocessor system” or “distributed shared memory type architecture”. 
       FIG. 1  is a block diagram showing a configuration of a distributed shared memory type multiprocessor system  1 . The multiprocessor system  1  shown in  FIG. 1  is composed of multiple cells C 1  to Cn (n is an integer showing the number of cells) and a cross over switch  9  mutually connecting these multiple cells C 1  to Cn. Each cell Cj (j is an integer that is greater than 1, but less than n) has at least one CPU (microprocessor)  2 - j - 1  to  2 - j - m  (m is an integer showing the CPU number within each cell) and main memory (local memory)  5 - j . Each of the CPUs  2  loads at least one cache memory (stored-in-cache)  7 . A shared memory is composed of all of the main memories  5 - 1  to  5 - n  that have been distributed and the shared memory can be referred by all CPUs  2 . 
     In this distributed shared memory type multiprocessor system  1 , while using cache  7 , each CPU  2  accesses the data stored in the main memory  5 - 1  to  5 - n , and also performs updating. When using a write back method for data updating, the updated data remains in the cache  7  so that there is a possibility that the latest data may not be present in the main memory  5 - j . At this point, if multiple CPUs  2  try to reference/update the identical memory area, correct results cannot be obtained due to incoherency of the data. Thus, in the multiprocessor system, it is important to assure consistency of the data (referred to as “cache coherency”) in order for each CPU  2  to enable accessing the latest data. One should consider the fact that it is important to maintain coherency among multiple cells C 1  to Cn as well as maintaining coherency among cache  7  within each cell Cj. 
     As a coherency protocol, a “Directory-based Cache Coherency Protocol” and “Snooping Cache Coherency Protocol” are known. 
     According to the directory-based cache coherency protocol, a table (directory) is installed to manage the status of caching regarding the data stored in the main memory. When a certain CPU accesses data where the CPU is present, the information regarding the caching status stored in the directory is initially investigated. If the desired latest data are determined to be present in only a certain cache instead of in the main memory, the CPU accesses its data for that cache. 
     According to the snooping cache coherency protocol, when a certain CPU accesses data of a certain access address, all caches examine whether they own copies of the data of that access address. Each cache changes their own status (cache status) to enable acquisition of the latest data, if necessary. For example, according to MESI protocol, the following four cache statuses are provided: “I: invalid”, “S: shared (the latest data are present in the main memory and in multiple caches), “E: Exclusive (the latest data are present in the main memory and its own cache)”, and “M: modified (the latest data are present only in its own cache”. 
     In each of the cells C 1  to Cn shown in  FIG. 1 , in order to implement the aforementioned cache coherency, cache coherency circuits  3 - 1  to  3 - n  and directories  4 - 1  to  4 - n  are installed. A directory  4 - j  is a memory area implemented by DRAM and the like, and it stores information for managing the caching status regarding the data stored in the main memory  5 - j  of its own cell Cj. More specifically, the directory  4 - j  stores a table showing the cell caching the latest data regarding the data stored in the main memory  5 - j  of its own cell Cj. The cell caching the latest data can be its own cell or an other cell. The cache coherency circuit  3  is configured such that the coherency among the cells C 1  to Cn is assured by referring to the directory  4 . The cache coherency in each cell can be implemented, for example, by the snooping cache coherency protocol. 
     A cell loading the CPU  2  which is an issuing source for issuing a read request for certain data are hereinafter referred to as “a request cell CR”. A cell loading the main memory  5  wherein the data to be accessed is stored is hereinafter referred to as “a home cell CH”. Also, a cell having a cache  7  caching the latest version (latest data) of the data to be accessed is hereinafter referred to as “an owner cell CO”. The inventors of the present application focused at the fact that in the multiprocessor system  1  using the directory  4 , a status occurs with a different request cell CR, home cell CH and owner cell CO. 
     Operational examples of the conventional multiprocessor system in such a state will be explained with reference to  FIG. 2 . Initially, the CPU  2  of the request cell CR issues a read request to the home cell CH having the main memory  5  storing the data to be accessed (Step S 1 ). The home cell CH searches (retrieves) its own directory  4  in response to the read request. From the information stored in the directory  4 , the home cell CH detects the fact that the latest version of the target data is stored in the cache  7  of the owner cell CO. Then, the home cell CH issues a snoop request to the owner cell CO (Step S 2 ). 
     In response to the snoop request, the owner cell CO reads out the latest data from the cache  7 . In order to rewrite the latest data in the main memory  5  of the home cell CH, the owner cell CO issues a write back to the home cell CH (Step S 3 ). The write back issued by the owner cell CO in response to the snoop request is hereinafter referred to as “reply write back”. Simultaneously with this reply write back, the owner cell CO directly transmits the latest data read as a reply data to the request cell CR (Step S 3 ′). As a result, the latency from the issuing of the read request to the reception of the reply data can be implemented by 3HOP (Steps S 1 , S 2 , S 3 ′) (The latency between the cells is considered as 1 HOP). 
     The CPU  2  of the request cell CR issuing the read request stores the reply data received in its own cache  7 . Subsequently, in the case when the reply data of the cache  7  is replaced, there is a possibility of the generation of a write back from the request cell CR to the home cell CH (Step S 3 ″). The write back issued when the CPU  2  replaces the cache  7  is hereinafter referred to as a “request write back”. Since the aforementioned reply write back (Step S 3 ) and the request write back (Step S 3 ″) are performed by a different path, the order is not always determined unconditionally. If Step S 3  is carried out “later” than Step S 3 ″, the latest data updated by the request cell CR in the main memory  5  of the home cell CH is overwritten by the old data from the owner cell CO. That is, if Step S 3  is different from Step S 3 ″, there is a problem that the coherency is not always assured. 
     In order to solve this problem, an operational example will be explained with reference to  FIG. 3 . Initially, the request cell CR issues a read request to the home cell CH (Step S 1 ). Next, the home cell CH issues a snoop request to the owner cell CO (Step S 2 ). In response to the snoop request, the owner cell CO reads the latest data from the cache  7  and issues a reply write back to the home cell CH (Step S 3 ). Here, the owner cell CO does not directly transmit the latest data to the request cell CR. Next, the home cell CH updates its own main memory by the latest data in response to the reply write back. Later, the home cell CH transmits the latest data as a reply data to the request cell CR (Step S 4 ). 
     By this processing, the occurrence of the relationship between the Step S 3  and Step S 3 ″ as shown in  FIG. 2  is prevented so that it is possible to assure coherency between cells. However, in the case of the processing shown in  FIG. 3 , the latency from issuing of the read request to the reception of the reply data becomes 4 HOP (Steps S 1 , S 2 , S 3 , S 4 ). This implies a reduction in the processing speed. Basically, multiple processors are used in the multiprocessor system in order to improve processing speed so that the aforementioned reduction in processing speed is a serious problem. 
     SUMMARY OF THE INVENTION 
     Thus, an object of the present invention is to enable both assuring coherency and improving processing speed. That is, the purpose of the present invention is to provide technology enabling suppression of latency regarding read requests within 3HOP or less. 
     The means for solving problems will be explained below using the numbers and encodes used in the preferred embodiments of the present invention. These numbers and encodes are added with parentheses in order to clarify the relationships of the descriptions of “What is claimed is” and “Detailed Description of the Preferred Embodiments”. However, these numbers and encodes should not be used for the interpretation of the technical scope of the invention as described in the “What is claimed is” 
     A multiprocessor system ( 1 ) of an embodiment of the present invention includes multiple cells (C 1  to Cn) and a network ( 9 ) which connects among the multiple cells (C 1  to Cn). Each cell (Cj) includes a processor ( 2 ), a directory ( 4 ), a cache memory ( 7 ), and a main memory ( 5 ). Multiple cells (C 1  to Cn) include request cells (CR), home cells (CH), and owner cells (CO). The latest version of the target data stored in the main memory ( 5 ) of the home cell (CH) is stored in the cache memory ( 7 ) of the owner cell (CO). 
     The request cell (CR) issues a read request for the target data to the home cell (CH). The home cell (CH) issues a snoop request to the owner cell (CO) in response to the read request. The owner cell (CO) directly transmits the latest data to the request cell (CR) in response to the snoop request. As a result, the latency from issuing the read request to the reception of reply data can be implemented by 3HOP. 
     Also, the owner cell (CO) transmits the reply write back to the home cell (CH) in response to the snoop request. The request cell (CR) issues a request write back for the same address as the aforementioned target data in the home cell (CH). The request write back includes the directory updating information in order to enable coherency between the status of the cache ( 7 ) included in the request cell (CR) and the status of the directory ( 4 ) in the home cell (CH). The home cell (CH), if the reply write back from the owner cell (CO) is received after the request write back from the request cell (CR), aborts the reply write back, and also updates the status of the directory ( 4 ) based on the directory update information. 
     This configuration prevents the data updated by the request write back from the request cell (CR) from being overwritten by the old data by the reply write back from the owner cell (CO). Thus, despite the fact that the pathways are different between the request write back and the reply write back, assurance of coherency is enabled. In other words, even though the owner cell (CO) transmits the reply data directly to the request cell (CR), coherency among the cells can be maintained. 
     According to the multiprocessor system of the present invention, even though the request cell CR, the home cell CH and the owner cell CO are different, it is possible to make the latency from the issuing of the read request to the reception of the reply data to be 3HOP. In addition, assurance of coherency among cells is enabled. That is, both assurance of coherency and shortening of the latency (improvement in processing speed) can be implemented. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing a configuration of the distributed shared memory type multiprocessor system. 
         FIG. 2  is a conceptual view showing operations of the conventional multiprocessor system. 
         FIG. 3  is a conceptual view showing operations of the conventional multiprocessor system. 
         FIG. 4  is a conceptual view showing operations of the multiprocessor system of the present invention. 
         FIG. 5  is a table showing an example of the information stored in the directory concerned in the embodiment of the present invention. 
         FIG. 6  is a block diagram showing a configuration of the cache coherency circuit concerned in the present embodiment. 
         FIG. 7  is a block diagram showing a configuration of the main pipe unit concerned in the present embodiment. 
         FIG. 8  is a table showing an example of the snoop management table concerned in the present embodiment. 
         FIG. 9  is a table showing an abstract of the method of updating the directory concerned in the present embodiment. 
         FIG. 10  is a diagram showing an example of the operational flow of the multiprocessor system concerned in the present embodiment. 
         FIG. 11  shows cache statuses, a snoop management table and a table showing transition of the information stored in the directory. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The multiprocessor system concerned in the embodiment of the present invention is explained with reference to the attached drawings. 
     1. Concept 
     The operations of the multiprocessor system concerned in the present embodiment are explained with reference to  FIG. 4 . In  FIG. 4 , the request cell CR loads a CPU where a read request is a source issuing a read request. The home cell CH has a main memory wherein data to be accessed is stored. The owner cell CO has a cache caching the latest version of the data to be accessed (latest data). Here, the case when the request cell CR, the home cell CH and the owner cell CO are different is considered. 
     Initially, CPU of the request cell CR issues a read request to the home cell CH having access target data (Step S 1 ). The home cell CH searches (retrieves) its own directory in response to the read request. From the information stored in the directory, the home cell CH detects that the latest version of the target data are stored in the cache of the owner cell CO. Thus, the home cell CH issues a snoop request to the owner cell CO (Step S 2 ). 
     The owner cell CO reads out the latest data from the cache in response to the snoop request. Then, the owner cell CO issues a reply write back for the home cell CH in order to rewrite the latest data in the main memory of the home cell CH (Step S 3 ). At the same time as this reply write back, the owner cell CO directly transmits the latest data which has been read as a reply data to the request cell CR (Step S 3 ′). As a result, the latency from the issuing of the read request to the reception of the reply data can be implemented by 3HOP (Steps S 1 , S 2 , S 3 ′). 
     The CPU of the request cell CR that issued the read request stores the reply data received in its own cache. Subsequently, in the case when the data in the cache is replaced, the request cell CR issues a request write back to the home cell CH (Step S 3 ″). Since the aforementioned reply write back (Step S 3 ) and the request write back (Step S 3 ″) are performed through different paths, the order is not always determined unconditionally. 
     The cells according to an embodiment of the present invention have a function of registering the read request received in a specified table. Also, the cells according to an embodiment of the present invention have a function of making the detection flag effective when detecting the request write back for the same target address as that of the registered read request. Moreover, the cells according to an embodiment of the present invention have a function of “discarding” the received reply write back by referring to the aforementioned detection flag when receiving the reply write back (Step S 3 ) later than the request write back (Step S 3 ″). In other words, the cells according to an embodiment of the present invention have a function of discarding the reply write back when detecting the request write back (Step S 3 ″) during the period from the time when issuing the snoop request (Step S 2 ) to the reply write back (Step S 3 ). 
     By so doing, it prevents the data updated by the request write back from the request cell CR from being overwritten by the old data by the reply write back from the owner cell CO in the home cell CH. Thus, even though Step S 3  is different from Step S 3 ″, it is possible to assure coherency. In other words, even though the owner cell CO directly transmits the reply data to the request cell CR (Step S 3 ′), coherency among the cells can be maintained. In contrast, while assuring the coherency, the latency from the time when issuing the read request to the time receiving the reply data can be implemented by 3HOP. That is, both assurance of coherency and shortening of the latency (improvements in processing speed) can be implemented. 
     2. Configuration 
     2-1. Overall Configuration 
     Specific configuration examples to implement the processing concerned in the present embodiment will be explained below. The multiprocessor system concerned in the present embodiment is a distributed shared memory type multiprocessor system and the overall configuration is the same configuration shown in  FIG. 1 . That is, the distributed shared memory type multiprocessor system  1  concerned in the present embodiment includes multiple cells (nodes) C 1  to Cn (n is an integer showing the number of cells), and a crossbar switch  9  connecting among the multiple cells C 1  to Cn. The multiple cells C 1  to Cn can be connected to each other by a network such as shared buses and data links and the like. 
     The multiple cells C 1  to Cn have the same function. Each cell Cj (j is an integer of 1 or greater and n or less) includes at least one CPU (microprocessor)  2 - j - 1  to  2 - j - m  (m is an integer showing the number of CPUs in each cell), and a main memory (local memory)  5 - j . Each of the CPUs  2  carries at least one cache memory (store-in-cache)  7 . A shared memory is composed of all of the main memories  5 - 1  to  5 - n  that are installed distributedly and the shared memory is referenced by all CPUs  2 . 
     If a single cell has several caches  7 , local cache coherency in the cell is implemented, for example by the “snooping cache coherency protocol”. In this case, the cache  7  loaded in each CPU  2  manages the cache status for example based on the MESI protocol. According to the MESI protocol, the following four cache statuses: “M (modified)”, “E (exclusive)”, “S (shared)”, and “I (invalid)” or “U (uncached)” are provided: 
     M (Modified): The data in the cache is present only within the cache, and I is not identical to the data within the main memory. Namely, the latest data are present only in its cache. 
     E (Exclusive): The data in the cache is present only within the cache among multiple caches, and is identical to the data within the main memory. Namely the latest data are present in its cache and main memory. 
     S (Shared): The data in the cache is present in its cache and in the cache of other CPU, and is identical to the data in the main memory. Namely the latest data are present in multiple caches and in the main memory. 
     I (Invalid), U (Uncached): The data in the cache is invalid. Namely, the latest data are present in the main memory, but not in its cache. 
     The cache protocols that are applied to the present invention are not limited to the aforementioned MESI protocols. As long as cache status M (Modified) can be provided, any of the cache protocols can be applied. 
     Also, not only the cache coherency within the cells must be maintained, but also it is important to maintain cache coherency among multiple cells C 1  to Cn shown in  FIG. 1 . According to the present embodiment, cache coherency among multiple cells C 1  to Cn is controlled based on “the directly-based cache coherency protocol”. For this reason, in each of cells C 1  to Cn cache coherency circuit  3 - 1  to  3 - n  and a directory  4 - 1  to  4 - n  are installed. 
     The directory  4 - j  is a memory area implemented by DRAM and the like. In the directory  4 - j , information for managing the status of caching regarding the data stored in the main memory  5 - j  of its own cell Cj is stored. More specifically, in the directory  4 - j , the status of all data stored in the main memory  5 - j  of its own cell Cj, and a table showing the cell caching the latest version of the data (namely owner cell CO) are stored. The owner cell CO caching the latest data can be its own cell or can be other cells. 
     An example of the information stored in the directory  4 - j  is shown in  FIG. 5 . As shown in  FIG. 5 , the status (P, S, U) and the owner cell information are assigned to each data address of the main memory  5 - j . For example, the status regarding the data address A 0  is “P (private)”. The status “P” indicates a possibility that the latest data are registered in the cache  7  of the only cell. All of “M”, “E”, “S” and “I” are allowed as cache status of the cache. As owner cell information, the cell number of the owner cell is registered. 
     Also, the status regarding data address A 1  is “S”. The status “S (shared)” indicates a possibility that the latest data are registered in the cache  7  of multiple cells. As a cache status of the cache  7 , “S” or “I” is allowed. In this case, as owner cell information, bit maps corresponding to the cells C 1  to Cn are registered. As an example, a case when the number of cells is three (n=3) and the latest data are stored in the cache  7  of the cell C 1  and C 2  is considered. In this case, bits corresponding to the cell C 1  and the cell C 2  among the bit maps of three bits are set to be “1” and the bit corresponding to the cell C 3  is set to be “0”: (cell C 3 , cell C 2 , cell C 1 )=(0, 1, 1). The owner information is managed by this bit map. 
     Also, the status regarding the data address A 2  is “U (uncached)”. Also, the status “U” indicates that the data in the main memory  5 - j  is the latest data. In this case, none is particularly registered as owner cell information (N/A: not available). The statuses P, S U shown above can be described as cache statuses regarding the main memory  5 - j.    
     By referring to the directory  4 - j , the cache coherency circuit  3 - j  concerned in the present embodiment performs coherency control among the cells C 1  to Cn. Namely, cache coherency circuit  3 - j  assures cache coherency using the directory  4 - j  based on the directory-based cache coherency protocol. As will be explained below, the present invention is characterized in this cache coherency circuit  3 - j.    
     2-2. Cache Coherency Circuit 
       FIG. 6  is a block diagram showing a configuration of the cache coherency circuit  3 - j  of the cell Cj concerned in the present embodiment. In the cell Cj, the cache coherency circuit  3 - j  is connected to plural numbers of CPU  2 -J- 1  to  2 - j - m , directory  4 - j , and main memory  5 - j . Also, the cache coherency circuit  3 - j  is connected such that communication to other cells is enabled via the crossbar switch  9 . As shown in  FIG. 6 , the cache coherency circuit  3 - j  has a CPU request control unit  10 , a crossbar request control unit  20 , a main pip0e unit  30 , a directory access control unit  40 , a main memory access control unit  50 , and a reply data control unit  60 . These units are configured such that they can correspond with each other with data and requests. 
     As requests, “read request”, “snoop request”, “reply write back” and “request write back” are available. 
     The read requests include read target addresses and the read request issuing sources. In the present example, the read target address is an address in the main memory  5  in the home cell CH and the issuing source is CPU  2  of the request cell CR. Namely, the read requests include at least information regarding the request cell CR and home cell CH. 
     In the snoop request, information of the read request is copied and the read target addresses and read request issuing source are included. 
     In the reply write back, information of the snoop request is copied and the read target addresses and read request issuing source are included. Moreover, write back data are included in the reply write back. The read target addressees are write back target addresses in which the write back data are rewritten. 
     The request write back includes write back data, write back target addresses, request write back issuing source, and directory updating information. In the present example, the write back target address is the address in the main memory  5  in the home cell CH, and the issuing source is CPU  2  of the request cell CR. The directory updating information is the information for coherency between the cache status of the cache  7  included in the request cell CR and the status of the directory  4  of the home cell CH. The directory updating information indicates how the status of the directory  4  of the home cell CH can be updated. 
     A CPU request control unit  10  has a function of processing the request from the CPU  2 . More specifically, the CPU request control unit  10  receives the read request issued by the CPU  2  and transfers the read request to the main pipe unit  30  of its own cell or to the home cell CH in response to the read target addresses included in the read requests. Also, the CPU request control unit  10  receives the write back issued by the CPU  2 , and transfers the write back to the main pipe unit  30  of its own cell or to the home cell CH in response to the write back target addresses included in the write back. 
     Moreover, the CPU request control unit  10  has a function of processing snoop requests for the CPU  2 . More specifically, the CPU request control unit  10  transfers the snoop requests received from the crossbar switch or directory access control unit  40  to the CPU  2 . Then, the CPU request control unit  10  directly transmits the reply data obtained from the cache  7  of the CPU  2  by the snoop processing to the request cell CR. As a result, the latency from the time when issuing read request to the time when receiving reply data can be shortened. 
     The crossbar request control unit  20  has a function of processing requests received from the crossbar switch  9 . More specifically, the crossbar request control unit  20  transfers the read request received from the crossbar switch  9 , reply write back and request write back to the main pipe unit  30 . 
     The main pipe unit  30  has a function of arbitrating the requests received from the CPU request control unit  10  and the crossbar requests control  20 , and also a function of controlling requests for the directory access control unit  40  and main memory access control unit  50 . The detailed function of the main pipe unit  30  will be explained more precisely later in Section 2-3. 
     The directory access control unit  40  controls access to the directory  4 . Specifically, the directory access control unit  40  performs retrieving (searching the directory  4  in response to the requests received from the main pipe unit  30  (read request, request write back, reply write back). According to the status of the directory  4  read out, the directory access control unit  40  issues a snoop request to the owner cell CO or CPU request control unit  10  of its own cell. 
     Also, the directory access control unit  40  updates the directory  4  in response to the request received from the main pipe unit  30 . A method of updating the directory  4  depends upon the status of the directory  4  that has been read out and is regulated based on the specified rules (See  FIG. 9 ). However, in the case of reply write back, updating of the directory  4  may be performed by a different method from the specified rules. In such a case, the directory access control unit  40  receives an “update request” from the main pipe unit  30 . Then, the directory access control unit  40  updates the directory  4  as instructed by the update request. 
     The main memory access control unit  50  controls the access to the main memory  5 . Specifically, the main memory access control unit  50  reads out the target data from the main memory  5  in response to the read request received from the main pipe unit  30 . Then, the main memory access control unit  50  transmits the read data (read-out data) as reply data to the request cell CR or the reply data control unit  60  of its own cell. Also, the main memory access control unit  50  writes the write back data in the main memory  5  in response to the reply write back or request write back received from the main pipe unit  30 . 
     The reply data control unit  60  has a function of transferring the reply data received from the main memory access control unit  50  or from the crossbar switch  9  to CPU  2 . 
     2-3. Main Pipe Unit 
       FIG. 7  is a block diagram showing a configuration of the main pipe unit  30  concerned in the present embodiment. As shown in  FIG. 7 , the main pipe unit  30  includes a snoop management table  31 , a write back detection circuit  32 , a cancel determination circuit  33 , a discard determination circuit  34 , and an arbitration control circuit  35 . 
     The arbitration control circuit  35  performs arbitration between the request from the CPU request control unit  10  and the request from the crossbar request control unit  20 . The request after acquiring arbitration is transferred to the snoop management table  31 , write back detection circuit  32 , cancel determination circuit  33 , and discard determination circuit  34 . 
     The snoop management table  31  is a table where information is stored and multiple entries are stored. Each of the entries includes a valid bit  311 , address information  312 , cell information  313 , and write back detection information  314 .  FIG. 8  shows an example of the snoop management table  31  in a certain cell. The valid (V) bit  311  shows whether the entry is a valid entry (“1”) or an empty entry (“0”). 
     As the address information  312 , read target addresses showing read request (e.g., A 0 , A 1 ) are stored. As the cell information (request cell information)  313 , the numbers of cells at the issuing source that issued the read request (e.g.: C 1 , C 3 ) are stored. As mentioned above, the cells according to an embodiment according to an embodiment of the present invention have a function of storing the read request received. As will be described later, multiple read target addresses (A 0 , A 1 ) corresponding to multiple entries are controlled differently. Namely, the number of “certain read target addresses” included in the address information  312  is either 0 or 1. If the read request for a certain read target address has been registered, the read request to the same read target address is in a read request registration stand-by state. 
     The write back detection information  314  contains a detection flag and directory update information. The detection flag and the directory update information correspond to the registered address information  312  and cell information  313 . The detection flag is a flag that indicates whether or not there is a write back from the request cell CR, namely whether or not the request write back is detected. When the detection flag is valid (“1”), a request write back for the read target address (A 0 ) is detected. In contrast, the directory update information is an information showing in which status the directory  4  is updated and is setup at the same time when the detection flag is set to be “1”. As will be described later, this directory update information is used when generating an update request. 
     Returning to  FIG. 7 , the write back detection circuit  32  includes an address information comparator  321 , a cell information comparator  322 , and AND  323 . This write back detection circuit  32  receives the request transferred from the arbitration control circuit  35 . Then, the write back detection circuit  32  detects “request write back” for each of the read target addresses shown by address information  312  by referring to the aforementioned snoop management table  31 . 
     Specifically, the address information comparator  321  compares the write back target addresses indicated by the write back (reply write back or request write back) with the read target addresses shown by the address information  312  in the aforementioned snoop management table  31 . Then, the address information comparator  321  outputs bit map data (number of bits total number of entries) showing agreement (“1”)/disagreement (“0”) with respect to all entries. In this case, if the V bit  311  is invalid, entries are determined to be automatically disagreement (“0”). In this bit map data, all bits are expressed by “0” or only one of the bits is “1”. Those entries corresponding to “1” among the bit map data are referred to as “agreement entries”. 
     In contrast, the cell information comparator  322  compares the number of the issuing source indicated by the request write back with the number of request cell CR indicated by the cell information  313  in the aforementioned snoop management table  31  when receiving the request write back. Then, the cell information comparator  322  outputs bit map data showing agreement (“1”)/disagreement (“0”) with respect to all entries. If the V bit  311  is invalid, entries are determined to be automatically disagreement (“0”). 
     AND  323  outputs a logical product between the bit map data from the address information comparator  321  and the bit map data from the cell information comparator  322 . In the bit map data output, all bits are expressed as “0” or only one bit is “1”. Then the write back detection circuit  32  modifies the write back detection information  314  of the entries corresponding to “1” (agreement entries) among the bit map data. Specifically, the write back detection circuit  32  modifies the detection flag from invalid (“0”) to valid (“1”), and also set up the directory modification information to the directory update information shown by the request write back. Namely, the directory update information is stored in the snoop management table  31  corresponding to the verified detection flag. 
     The fact that the output of AND  323  contains “1” means that “a request cell CR issues a read request to a certain address, and furthermore, the same request cell CR issues request write back to the same address”. Namely, the write back detection circuit  32  is a circuit for detecting the request write back related to the read request that has been registered in the snoop management table  31 . If the write back detection circuit  32  detects such a request write back, it sets up the detection flag of the agreement entries at “1”. Therefore, the cells according to an embodiment according to an embodiment of the present invention have a function of validating the detection flag when detecting a request write back for the same target addresses as those of the registered read request. The information regarding the read request that has been stored in advance in the snoop management table  31  (address information  312 , cell information  313 ) is considered as information for detecting the request write back which may be received later. 
     Also, the write back detection circuit  32  when receiving the reply write back, outputs address agreement entries output from the address information comparator  321  (bit map data) to the cancel determination circuit  33  and discard determination circuit  34 . Also, the write back detection circuit  32  when receiving reply write back, invalidates V bit  311  regarding the address agreement entries (“0”). Namely, the write back detection circuit  32  initializes the entries related to the reply write back in response to the reply write back. 
     Next, a cancel determination circuit  33  will be explained. As mentioned above, if a read request for a certain read target address has already been registered in the snoop management table  31 , the read request for the same read target address is set in a registration stand-by state. For this reason, a cancel determination circuit  33  is installed. The cancel determination circuit  33  receives a read request from the arbitration control circuit  35 , and also receives outputs from the address information comparator  321  of the aforementioned write back detection circuit  32 . If address agreement entries are output from the address information comparator  321 , that is, if a read request to the same address as the read target address which has been registered in the snoop management table  31  is detected, the cancel determination circuit  33  requests reissuing of the read request for the CPU request control unit  10  and the crossbar request control unit  20 . Then, the same operation is repeated until there is a free entry in the snoop management table  31 . As a result, the read request is in a registration stand-by state. 
     The discard determination circuit  34  receives requests transferred from the arbitration control circuit  35  (read request, request write back, reply write back). If the request received is a read request, the discard determination circuit  34  outputs the read request to the directory access control unit  40  and the main memory access control unit  50 . Also, if the request is a request write back, the discard determination circuit  34  outputs the request write back to the directory access control unit  40  and the main memory access control unit  50 . 
     Also, if the request received is a reply write back, the discard determination circuit  34  receives outputs from the address information comparator  321  (bit map data) and references the write back detection information  314  of the address agreement entries shown by the bit map data. If the detection flag of the write back detection information  314  as referenced is “0”, the discard determination circuit  34  outputs reply write back directory access control unit  40  and the main memory access control unit  50 . In contrast, if the detection flag is “1”, it means that the reply write back is entered after the request write back. In this case, the discard determination circuit  34  discards the reply write back received. Therefore, the reply write back is not output to the main memory access control unit  50 . However, the discard determination circuit  34  issues an “update request” for updating the status of the directory  4  in the directory access control unit  40 . The contents of instruction of the update request are determined by the “directory update information” in the write back detection information  314  as referenced. 
     As explained above, the main pipe unit  30  concerned in the present embodiment has (1) a function of registering a read request from the request cell CR, (2) a function of storing the detection results when detecting the request write back for the same target addresses as those for a read request as registered, (3) and a function of controlling requests for the directory access control unit  40  and the main memory access control unit  50 . Specifically, when receiving a reply write back after a request write back, it includes a function of discarding the rely write back and updating the directory  4 . The aforementioned function (1) is provided by snoop management table  31 . The aforementioned function (2) is provided by write back detection circuit and snoop management table  31 . The aforementioned function (3) is provided by discard determination circuit  34  and smooth management table  31 . As a result, the operations shown in  FIG. 4  are implemented 
       FIG. 9  briefly shows the status of retrieving the directory  4  for various requests and the status after updating. The summary shown in  FIG. 9  is referred in the following explanation of the operational examples. 
     3. System Operational Examples 
     Operational examples of a multiprocessor system  1  concerned in the present embodiment will be explained with reference to the previously mentioned  FIG. 6 ,  FIG. 7 ,  FIG. 9  and the following drawings. In this operational example, the request cell CR, home cell CH and owner cell CO are assumed to be different from each other. For example, the request cell CR is represented by the cell C 1 , the home cell CH is represented by the cell C 2 , and the owner cell CO is represented by the cell C 3 . Namely, the target address to be read out by the CPU  2  of the request cell C 1  (e.g., CPU  2 - 1 - 1 ) is an address in the main memory  5 - 2  loaded on the home cell C 2 , and the latest data corresponding to the address is stored in the cache  7  in the CPU  2  (e.g., CPU  2 - 3 - 1 ) loaded in the owner cell C 3 . 
       FIG. 10  is a conceptual diagram showing a processing flow in the present operational example.  FIG. 11  shows the cache status of CPU  2 - 1 - 1  in the request cell C 1 , snoop management table  31  and the contents of the directory  4 - 2  in the cache coherency circuit  3 - 2  in the home cell C 2 , and changes in the cache status of the CPU  2 - 3 - 1  of the owner cell C 3 . In the initial state, the cache status of the CPU  2 - 1 - 1  in the request cell C 1  is “I (invalid)” and the cache status of the CPU  2 - 3 - 1  in the owner cell C 3  is “M (Modified)”. Also, in the directory  4 - 2  of the home cell C 2 , the status for the read target address A 0  is expressed as “P” and the owner cell information is expressed as “cell C 3 ”. 
     Step S 11 : Request Cell C 1 : Issuing Read Request 
     Initially, CPU  2 - 1 - 1  in the request cell C 1  issues a “read request” to the address A 0  in the main memory  5 - 2  in the home cell C 2 . This read request contains a read target address A 0  and the issuing source (CPU  2 - 1 - 1 ). When the CPU  2 - 1 - 1  issues a read request, a snoop processing is executed respectively in CPU  2 - 1 - 1  to CPU 2 - 1 - m  in the request cell C 1 . Specifically, it is investigated whether respective cache  7  of CPU  2 - 1 - 1  to CPU  2 - 1 - m  stores data at the read target address A 0 . 
     If there are no cache hits, the read request is transmitted to the cache coherency circuit  3 - 1  in the request cell C 1 . The CPU request control unit  10  in the cache coherency circuit  3 - 1  receives a read request from the CPU  2 - 1 - 1 . The CPU request control unit  10  determines the home cell C 2  as an access target based on the read target address A 0  included in the read request. The home cell C 2  is unconditionally determined by the read target address A 0 . Then, the CPU request control unit  10  transmits a read request to the home cell C 2  via the crossbar switch  9 . 
     Step S 12 : Home Cell C 2 : Updating Snoop Management Table  31   
     The crossbar request control unit  20  of the cache coherency circuit  3 - 2  in the home cell C 2  receives the read request via the crossbar switch  9  from the request cell C 2 . Then, the crossbar request control unit  20  transfers the read request received to the main pipe unit  30 . The arbitration control circuit  35  of the main pipe unit  30  performs arbitration with the read request from its read request and the CPU request control unit  10 . 
     When the read request acquires arbitration from the crossbar request control unit  20 , the read request is transferred to the snoop management table  31 , write back detection circuit  32 , cancel determination circuit  33 , and discard determination circuit. Then, the main pipe unit  30  registers its read request in the free entry of the snoop management table  31 . In this case, as shown in  FIG. 11 , with respect to the entries registered for the read request, V-bit  311  is modified from “0” to “1” and the read target address A 0  is registered as address information  312  and the number of the request cell C 1  is registered as cell information  313 , and the detection flag of the write back detection information  314  is set to “0”. 
     If a read request for the same address A 0  is present in the valid entry of the snoop management table  31  (V bit  311  “1” entry), the address information comparator  321  (See  FIG. 7 ) detects the address agreement entry. Once the address agreement entry is detected, the cancel determination circuit  33  requests the crossbar request control unit  20  to reissue the read request. As a result, the read request is set in a registration stand-by state. Therefore, the phenomenon that plural numbers of read requests for the same address are stored in the snoop management table  31  can be prevented. 
     Subsequently, the main pipe unit  30  (discard determination circuit  34 ) transmits read requests to the directory access control unit  40  and the main memory access control unit  50 . 
     Step S 13 : Home Cell C 2 : Directory Access 
     The directory access control unit  40  in the home cell C 2  initially indexes directory  4 - 2  in response to the read requests received. As shown in  FIG. 11 , in the directory  4 - 2 , the status for the read target address A 0  is “P” and the owner cell information is “cell C 3 ”. In this case, the directory access control unit  40  issues a “snoop request” to the owner cell C 3  via crossbar switch  9 . The read request information is copied in the snoop request which includes read target address A 0  and the read request issuing source (CPU  2 - 1 - 1  of the request cell C 1 ). 
     Also, the directory access control unit  40  updates the directory  4 - 2  in response to the read request. With reference to  FIG. 9 , if the status is “P” during the time of retrieval for the read request, the status is not updated (NC: No changes). Moreover, the directory access control unit  40  outputs the status information “P” and the owner cell information “C 3 ” to the main memory access control unit  50 . 
     Step S 14 : Home Cell C 2 : Memory Access 
     On the other hand, the main memory access control unit  50  in the home cell C 2  read the data out from the read target address A 0  in the main memory  5 - 2  in response to the read request received. Then the main memory access control unit  50  imparts the status information “P” and the owner cell information “C 3 ” that are received from the directory access control unit  40 , to the data that has been read, in order to generate reply data DR. The memory access control unit  50  transmits the reply data DR via the crossbar switch  9  to the request cell C 1 . 
     Step S 15 : Request Cell C 1 : Reception of the Reply Data DR 
     The reply data control unit  60  of the request cell C 1  receives the reply data DR from the crossbar switch  9 . The reply data DR indicates that the status is “P” and the owner cell is cell C 3 . In this case, the reply data control unit  60  waits for the reply data from the owner cell C 3 . 
     Step S 16 : Owner Cell C 3 : Issuing the Snoop Processing and the Reply Write Back 
     The CPU request control unit  10  of the owner cell C 3  receives the snoop request issued by the home cell C 2 . Then, the CPU request control unit  10  issues the snoop request in the CPU  2 - 3 - 1  to  2 - 3 - m  of its own cell C 3 . Each cache  7  of CPU  2 - 3 - 1  to  2 - 3 - m  executes the snoop processing. As a result, the CPU  2 - 3 - 1  showing the cache status of “M” issues the “reply write back” to the CPU request control unit  10 . The snoop request information is copied in the reply write back, and the read target address A 0  and the read request issuing source (request cell C 1 ) are included. Moreover, the reply write back includes the data read-out from the cache  7  (write back data). The read target address A 0  is also a write back target address A 0  from which the write back data is rewritten. Also in response to the reply write back issued, the cache status of the cache  7  of the CPU  2 - 3 - 1  is modified from “M” to “I”. 
     The CPU request control unit  10  of the owner cell C 3  when receiving the reply write back from the CPU  2 - 3 - 1  transmits the reply write back via the crossbar switch  9  to the home cell C 2  (Step S 16 - 1 ). The home cell C 2  is determined unconditionally by the write back target address A 0 . 
     Moreover, the CPU request control unit  10  of the owner cell C 3  directly transmits the data read-out from the cache  7  (reply data DR′) to the request cell C 1  (Step S 16 - 2 ). The destination of the transmission (request cell C 1 ) can determine based on the issuing source information of the snoop request or the read request included in the reply write back. 
     Step S 17 : Request Cell C 1 : Reception of the Reply Data DR′ 
     The reply data control unit  60  of the request cell C 1  directly receives the reply data DR′ through the crossbar switch  9  from the owner cell C 3 . In this case, the reply data control unit  60  discards the reply data DR received from the aforementioned Step S 15 . Then, the reply data control unit  60  transmits the reply data DR′ received from the owner cell C 3  to the CPU  2 - 1 - 1  that is the issuing source of the read request. The CPU  2 - 1 - 1  when receiving the reply data DR′, registers the reply data DR′ in its own cache  7 . In this case, the cache status of the cache  7  of the CPU  2 - 1 - 1  is modified from “I” to “E”. As mentioned above, the process from issuing the read request to the reception of the reply data DR′ is implemented by 3HOP. 
     Step S 18 : Request Cell C 1 : Issuing the Request Write Back 
     After Step S 17 , the CPU  2 - 1 - 1  rewrites the data stored in the cache  7  with new data. That is, the data stored in the cache  7  is updated. In this case, the status of the cache  7  is temporarily modified from “E” to “M”. Moreover, the CPU  2 - 1 - 1  issues a “request write back” to the CPU request control unit  10  in response to the data updating in the cache  7 . In response to the issuing of the request write back, the cache status of the cache  7  of the CPU  2 - 1 - 1  is modified from “M” to “I”. This request write back includes the latest data stored in the cache  7  (write back data), write back target address A 0 , issuing source information (CPU  2 - 1 - 1  of the request cell C 1 ), and directory update information. If the cache status is modified to “I”, the directory update information is set to “U update”. 
     For reference, the case is considered when another CPU  2 - 1 - 2  issues a read request for its data after the status of the cache  7  of the CPU  2 - 1 - 1  is modified from “E” to “M”. In this case, the data stored in the cache  7  of the CPU  2 - 1 - 1  shifts to the cache  7  of the CPU  2 - 1 - 2  due to the snoop processing. While the cache status of the CPU  2 - 1 - 1  is modified from “M” to “I”, the cache status of the CPU  2 - 1 - 2  is modified from “I” to “E”. In this case, since the cache status in the cell C 1  contains “E”, the directory update information of the request write back issued by the CPU  2 - 1 - 1  can be set to “NC update”. 
     The CPU request control unit  10  of the cache coherency circuit  3 - 1 , when receiving the request write back (U update) determines the home cell C 2  to become the access destination based on the write back target address A 0  and then, the CPU request control unit  10  transmits the request write back to the home cell C 2  via the crossbar switch  9 . 
     Step S 19 : Home Cell C 2 : Detecting the Request Write Back 
     The crossbar request control unit  20  of the cache coherency circuit  3 - 2  in the home cell C 2  receives the request write back from the request cell C 1  and then, the crossbar request control unit  20  transfers the request write back received to the main pipe unit  30 . The arbitration control circuit  35  of the main pipe unit  30  performs arbitration between the request write back and the request from the CPU request control unit  10 . 
     Once the request write back from the crossbar request control unit  20  acquires arbitration, the request write back is transferred to the write back detection circuit  32  and the discard determination circuit  34 . In the write back detection circuit  32 , the address information comparator  321  detects that the address information  312  of the snoop management table  31  shown in  FIG. 11  (“A 0 ”) agrees with the write back target address A 0  shown by the request write back. Also, the cell information comparator  322  detects that the cell information  313  of the snoop management table  31  shown in  FIG. 11  (“C 1 ”) agrees with the issuing source information shown by the request write back (“C 1 ”). And then, the agreement entry is detected by calculation of AND  323 . In this case, the write back detection circuit  32  updates the write back detection information  314  of the agreement entry in the snoop management table  31 . Specifically, the detection flag of the agreement entry is set to be “1”. Also, according to the directory update information included in the request write back (U update), the directory update information of the agreement entry is set to be “U”. 
     As explained above, in the home cell C 2 , it is stored that the request write back for the address A 0  is detected. Also, the snoop management table  31  is updated. Consequently, the main pipe unit  30  (discard determination circuit  34 ) transmits the request write back to the directory access control unit  40  and the main memory access control unit  50 . 
     Step S 20 : Home Cell C 2 : Directory Access, Memory Access 
     The main memory access control unit  50  of the home cell C 2 , in response to the request write back received, rewrites the write back data in the write back target address A 0  in the main memory  5 - 2 . 
     Also, the directory access control unit  40 , in response to the request back received, indexes and updates the directory  4 - 2 . As shown in  FIG. 11 , in the directory  4 - 2 , the owner cell information is “cell C 3 ”. Namely, as a result of indexing in the directory  4 - 2 , the issuing source information shown by the request write back (Request cell C 1 ) is found to be different from the owner cell information in the directory  4 - 2  (Owner cell C 3 ). In this case, with reference to  FIG. 9 , the directory access control unit  40  does not update status of the directory  4 - 2  and the owner cell information (NC: No change). 
     Step S 21 : Home Cell C 2 : Discard the Reply Write Back 
     The home cell C 2  receives a “reply write back” by the aforementioned Step S 16 - 1  after the “request write back” by Step S 19 . The crossbar request control unit  20  of the cache coherency circuit  3 - 2  in the home cell C 2  receives the reply write back from the owner cell C 3  and then, the crossbar request control unit  20  transfers the reply write back received to the main pipe unit  30 . The arbitration control circuit  35  of the main pipe unit  30  performs arbitration between the reply write back and the request from the CPU request control unit  10 . 
     Once the request write back from the crossbar request control unit  20  acquires arbitration, the reply write back is transferred to the write back detection circuit  32  and the discard determination circuit  34 . In the write back detection circuit  32 , the address information comparator  321  performs a comparison between the write back target address A 0  shown by the reply write back and the address information  312  of the snoop management table  31  and then, the write back detection circuit  32  informs the address agreement entry that agrees with the write back target address A 0 , to the discard determination circuit  34 . 
     The discard determination circuit  34 , when receiving the reply write back, reads out the write back detection information  314  of the address agreement entry in the snoop management table  31 . As shown in  FIG. 11 , the detection flag of the address agreement entry is set to be “1”. This means that the request write back has already been performed. As a result, the discard determination circuit  34  recognizes that the request write back has been performed prior to the reply write back. In this case, the discard determination circuit  34  discards the reply write back (Discard) and does not output the reply write back to the main memory access control unit  50 . As a result, this prevents that the data updated by the request write back from the request cell CR from being overwritten by the old data by the reply write back from the owner cell C 0 . 
     Step S 22 : Home Cell C 2 : Updating the Directory 
     Also, the discard determination circuit  34  when referring to the write back detection information  314 , detects that the directory update information of the address agreement entry is set to be “U” (See  FIG. 11 ). In this case, the discard determination circuit  34  issues an “update request (U update)” to the directory access control unit  40 . The directory access control unit  40  updates the directory  4 - 2  in response to the update request received. According to the regulations shown in  FIG. 9 , in the case of reply write back, “NC” is given, but in the present case, the “update request (U update)” is prioritized. Thus, the directory access control unit  40  modifies the status of the directory  4 - 2  from “P” to “U” in response to the update request to delete the owner cell information. As shown in  FIG. 11 , it is found that there is no incoherency among the cache status of the cell C 1  (“I”), the status of the directory  4 - 2  of the cell C 2  (“U”), and the cache status of the cell C 3  (“I”). That is, coherency is maintained among the cells. 
     When the reply write back is received, the write back detection circuit  32  initializes the address agreement entry in the snoop management table  31  based on the outputs from the address information comparator  321 . Specifically, the write back detection circuit  32  returns the V bit  311  regarding the address agreement entry to “0”. This ends a series of processing. 
     Also, the processing in the case when the home cell C 2  receives the reply write back before the request write back is as follows. Since the detection flag of the write back detection information  314  is still “0”, the discard determination circuit  34  outputs the reply write back to the directory access control unit  40  and the main memory access control unit  50 . As a result, the write back is executed as usual and the write back data is rewritten in the address A 0 . According to the rules shown in  FIG. 9 , the status of the directory  4 - 2  is maintained to be “P” and the owner cell information is modified from “Cell C 3 ” to “Cell C 1  (Request cell)”. The cell C 1 , is designated by the “issuing source information of the request cell” included in the reply write back. Also, this entry is initialized by the reply write back. Thus, even though the request write back is received later, the detection flag of the write back detection information  314  will not be validated. Only the request write back is executed directly. 
     4. Summary 
     As mentioned above, according to the present invention, assurance of coherency and shortening of latency can be implemented even in such a state that the request cell CR, home cell CH and owner cell CO are different. 
     When an access occurs from the request cell CR to the cache  7  of the owner cell CO, the owner cell CO returns the latest data to the request cell CR at the same time as the write back to the main memory  5 . As a result, it is possible to implement latency from the state of issuing the read request to the state of receiving the reply data by 3HOP. 
     Also, if a snoop management table  31 , a write back detection circuit  32 , and a discard determination circuit  34  are installed in the cache coherency circuit  3 - j  loaded in the cell Cj, the following functions are provided to each cell Cj: (1) a function of registering the read request from the request cell CR, (2) a function of validating the detection flag when a request write back is detected for the same address as that of the target address of the read request as registered, (3) a function of discarding the reply write back received by referring to the aforementioned detection flag when the reply write back is received after the request write back, and (4) a function of updating the directory along with discarding the reply write back. These functions prevent that the updated data by the request write back from the request cell CR is overwritten by the old data by the reply write back from the owner cell CO. Thus, despite the differences in the pathways between the request write back and the reply write back, it is possible to assure coherency. In other words, even though the owner cell CO directly transmits the reply data DR′ to the request cell CR, coherency among the cells can be maintained. 
     As explained above, according to the present invention, while assuring coherency, it is possible to implement the latency from the process of issuing the read request to the process of receiving reply data by 3 HOP. That is, both assurance of coherency and shortening of the latency (improvement in processing speed) can be implemented. This invention demonstrated a further greater effect in large-scale multiprocessor systems wherein the distance between the request cell CR and the home cell CH (number of HOPs) and the distance between the home cell CH and the owner cell CO become greater.