Patent Publication Number: US-7710206-B2

Title: Design structure for improved current controlled oscillation device and method having wide frequency range

Description:
This non-provisional U.S. Patent Application is a continuation-in-part of U.S. patent application Ser. No. 11/278,196, which was filed Mar. 31, 2006, now U.S. Pat. No. 7,355,486, and is assigned to the present assignee. 

   BACKGROUND 
   The present invention relates generally to current controlled oscillation (ICO) devices, and, more particularly, to a design structure for an improved ICO device having wide frequency range and integrated proportional frequency control capable of operation at low supply voltages. 
   Controlled oscillators are used in a variety of integrated circuits for applications such as, for example, signal generation and detection, as well as in phase locked loop (PLL) circuits. In a controlled oscillator, the frequency of an output signal is responsive to a control signal provided thereto. There are various types of controlled oscillators, with one of the more common types being a current controlled oscillator (ICO). A typical ICO includes a controlled current source coupled to a ring oscillator, which in turn features a chain of inverter stages (typically an odd number). The output of one inverter in the stage is coupled to the input of a succeeding inverter, and so on, with the output of the last inverter fed back to the input of the first inverter in the stage. Typical inverters are formed from CMOS transistors, although other types of devices may also be used. 
   The frequency of the output signal of an ICO is inversely proportional to the delay/switching time of the inverters that form the oscillator. In turn, the switching time of an inverter corresponds to the time needed to charge and discharge the input capacitance of a successive inverter to a level respectively above or below the switching threshold of the successive inverter. The charge and discharge period is determined by the magnitude of current that is used to charge the input capacitance. It is this charging current that is provided and controlled by the controlled current source. 
   One disadvantage associated with conventional current controlled oscillators is that the gain of the oscillator is not controllable at a given operating frequency. This is particularly the case for an oscillator that is used over a wide range of operating frequencies, as the gain of a conventional ICO (i.e., the relationship of output frequency versus bias current) is constrained by the desired frequency range. It would therefore be desirable to be able to configure a wide range oscillator for applications such as phase locked loops, for example, that also keeps the gain at a low level so that the overall loop bandwidth can be optimized. 
   SUMMARY 
   The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a design structure embodied in a machine readable medium used in a design process, the design structure including a current controlled, phase locked loop device including a phase detector configured to compare a reference frequency to an output frequency of a current controlled oscillator (ICO), a charge pump coupled to the phase detector and a low pass filter coupled to the charge pump. A voltage to current (V to I) converter is coupled to the low pass filter, providing an output current for integral control of the ICO. A control circuit is coupled to the ICO, and receives increment and decrement outputs of the phase detector, wherein the control circuit is configured to provide proportional control of the ICO through an amount of bias current applied thereto. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures: 
       FIG. 1  is a schematic block diagram of a phase locked loop employing a conventionally configured current controlled oscillator; 
       FIG. 2  is a schematic block diagram of a phase locked loop employing a current controlled oscillator configured in accordance with an embodiment of the invention; 
       FIG. 3  is a more detailed block diagram of the control circuit and current controlled oscillator of  FIG. 2 ; 
       FIG. 4  is a schematic diagram illustrating an exemplary delay stage used in the current controlled oscillator of  FIGS. 2 and 3 ; 
       FIG. 5  is a detailed schematic diagram of the control circuit of  FIGS. 2 and 3 ; 
       FIG. 6  is a graph illustrating bias current versus frequency curves for the current controlled oscillator, as a function of the adjustable gain of the delay stages, in accordance with a further embodiment of the invention; and 
       FIG. 7  is a flow diagram of an exemplary design process used in semiconductor design, manufacturing, and/or test. 
   

   DETAILED DESCRIPTION 
   Disclosed herein is a novel design structure embodied in a machine readable medium used in a design process, which provides current controlled oscillator that reduces jitter in a PLL by providing the capability of changing the gain of the ICO curves, depending upon the frequency of operation. By reducing the gain of the ICO, the PLL loop bandwidth can be shaped to reduce the overall jitter of the system. In addition, a novel control circuit provides both proportional and integral control for the ICO, which allows for the ICO to operate at low supply voltages. 
   Referring initially to  FIG. 1 , there is shown a schematic diagram of a phased locked loop  100  utilizing a conventional current controlled oscillator. As is shown, the PLL  100  includes a phase detector  102 , charge pump  104 , low pass filter  106  (with at least one resistor element and one or more capacitor elements), voltage to current converter  108 , and a current controlled oscillator  110  and output buffer  112  placed in a negative feedback configuration. There may also be a divide-by-N counter  114  included in the feedback path in order to obtain fractional multiples of the reference frequency F ref  out of the PLL  100 . 
   The ICO  110  generates a periodic output signal F out  that is compared to the reference frequency F ref . If the output signal F out , for example, begins to fall behind the reference frequency, then the phase detector  102  causes the charge pump  104  (through output signal “INC”) to change the control voltage (converted to control current) to speed up the ICO  110 . Conversely, if the output signal begins to creep ahead of the reference signal, than the phase detector  102  causes the charge pump  104  (through output signal “DEC”) to change the control current to slow down the ICO  110 . The low pass filter  106  provides both proportional and integral control of the ICO  110 , and smoothes out any abrupt control inputs from the charge pump  104 . 
   As indicated previously, ICOs (such as those built on microprocessor chips), being formed from a ring of active delay stages, suffer from more jitter than other types of oscillators as a result of the fixed gain thereof over a given range of operating frequencies and the consequent inability to shape the loop bandwidth. 
   Therefore, in accordance with an embodiment of the invention,  FIG. 2  illustrates a schematic block diagram of a phase locked loop  200  employing a novel current controlled oscillator  210  and associated control circuit  216 , featuring a wide frequency range, integrated and proportional control, and wherein the gain may be adjustably decreased at a given operating frequency in order to provide improved noise performance at low operating voltages. For ease of description, similar components of a phased locked loop are designated with the same reference numerals as shown in  FIG. 1 . 
   It will first be noted that the control circuit  216  provides proportional frequency control for the ICO  216  by receiving the INC and DEC outputs from the phase detector  102 . The INC and DEC pulses are compared within the control circuit  216 , and determine the amount of bias current provided to the ICO  210 , which in turn determines the frequency of operation thereof. As such, the low-pass filter  206  need only provide a capacitive element for integral frequency control, the voltage of which is again converted to a current through V to I converter  108 . As described in further detail hereinafter, the output of the V to I converter  108  is used by the control circuit  216  and thus the ICO  210 . 
   A bias generator  218  provides a pair of reference current signals for use by the control circuit  216  in determining control voltages applied to the ICO delay elements, that in turn control the bias current of the ICO  210  and hence the frequency thereof. In addition, a gain control block  220  provides a control signal applied directly to delay elements of the ICO  210  so as to adjustably control the amount of gain of the elements and thereby select the gain of the ICO  210 . The operation of the gain control feature is also described in further detail hereinafter. 
   Referring now to  FIG. 3 , a more detailed block diagram of the dashed portion of  FIG. 2  is illustrated. In particular, the ICO  210  includes (in an exemplary embodiment) a two-stage, latch-based configuration. Because both delay stages  302   a ,  302   b  utilize differential inputs and outputs (i.e., the logical true and complement signals of the latch), an odd number of stages is not needed. In addition to the power rail inputs (V DD , V SS ) each latch delay stage  302   a ,  302   b  is provided with the gain control signal VCNTL generated by the gain control block  220  of  FIG. 2 . As also shown in  FIG. 3 , a reset circuit  304  is provided in order to initially establish complementary input voltages to the input terminals VIN_P, VIN_N, of the second delay stage  302   b  and facilitate the oscillating output of the ICO  210 . 
   The inputs and outputs of the control circuit  216  are also labeled in  FIG. 3 . The inputs include the INC signal and DEC signal from the phase detector  102  of  FIG. 2 , as well as the two reference signals IPUMP_REF 1 , IPUMP_REF 2 , generated by the bias generator  218 . The output current from the V to I converter  108  is input into the control circuit  216 , the node voltage of which (NBIAS) represents one of the two bias voltages for the delay stages  302   a ,  302   b , that in turn control the bias current thereof. The other bias voltage (PBIAS) is an output of the control circuit  216 , which is described in additional detail later. 
     FIG. 4  is a schematic diagram illustrating an exemplary delay stage  302  used in the current controlled oscillator  210  of  FIGS. 2 and 3 . As is shown, the stage  302  includes biasing transistors P 1  and N 1 , the conductivity of which determines the amount of current through the cell and hence the frequency. A higher cell current leads to a higher frequency because the cell delay is reduced. The fully differential cell can thus be used to build ring oscillators of varying lengths. The gate of P 1  is coupled to PBIAS, the voltage of which is determined by control circuit  216 , while the gate of N 1  is controlled by the voltage at NBIAS, coupled to the output of the V to I converter  108  as stated above. The latch portion of the delay stage  302  includes NFETs N 2  and N 3 , along with PFETs P 2  and P 3 . In the embodiment depicted, the input signals to the stage  302  (VIN_P, VIN_N) are shown coupled to NFETS N 2  and N 3 , respectively, while the PFETs P 2  and P 3  are cross-coupled. However, the input signals could alternatively be coupled to P 2  and P 3  with N 2  and N 3  being cross-coupled. 
   As will further be noted from  FIG. 4 , PFETs P 2  and P 3  are cross-coupled through a pair of NFETs N 4  and N 5 . This provides the adjustable gain control of the ICO through a suitable voltage on VCNTL. The higher the biasing voltage of VCNTL, the more conductive the cross coupling paths and thus the greater the gain. In a conventionally configured delay latch, the cross coupling is a direct short circuit, and thus the gain of the cell is maximized and not adjustable. Accordingly, where it is desired to reduce the gain of the ICO, the value of VCNTL can be lowered so as to increase the resistance of the cross coupling paths. 
   Referring now to  FIG. 5 , the control circuit  216  is schematically illustrated in further detail. When the output frequency of the ICO is equal to the reference frequency, no changes in the output frequency are needed. In other words, the output values INC and DEC of the phase detector are zero. As to the increment portion of the control circuit, it will be seen that so long as INC is zero, PFET P 8  will maintain the gate of PFET P 9  at the supply rail, thus keeping P 9  off. Therefore, the only current flowing through diode configured NFET N 11  is from the V_I current input (generated by V_I converter  108 ). The voltage at this node also represents the output NBIAS voltage used to control the N 1  gate of the delay stages of  FIG. 4 . Conversely, the diode connected PFET P 10 , in series with NFET N 10  determines the output PBIAS voltage used to control the P 1  gate of the delay stages of  FIG. 4 . 
   Thus, it will be seen that the V_I current input provides the integral portion of the control of the ICO. In the event that the phase detector  102  ( FIG. 1 ) determines that the output frequency falls behind the reference frequency, then the value of INC changes to high, thereby disabling PFET P 8 . As a result, the gate of PFET P 9  and diode connected PFET P 7  are decoupled from the supply rail. This allows current to flow through the current mirror P 7  and N 9 , as determined by IPUMP_REF 1  and N 6 , and consequently through P 9 . The result is to (proportionally) add to the amount of current provided by V_I, which in turn increases the value of NBIAS and decreases the value of PBIAS, thereby providing more bias current to the delay cells and increases the oscillation frequency thereof. Once the output frequency catches up to the reference frequency, INC will return to low and cause P 8  to deactivate P 9  and remove the extra current flowing through N 11 . This returns the ICO back to the integral control thereof, as determined by the value of V_I. 
   On the other hand, if the output frequency begins to exceed the reference frequency, then the value of DEC changes to high, thereby disabling PFET P 6  and decoupling PFET P 4  and diode connected PFET P 5  from the supply rail. Once current begins to flow through P 4  and diode connected NFET N 8  (as determined by IPUMP_REF 2 ), N 7  will become conductive. Because N 7  is connected in parallel with respect to N 11  it will therefore (when rendered conductive) decrease the amount of current through N 11  as supplied by V_I. This results in decreasing the voltage at output NBIAS and increasing the voltage at output PBIAS, thereby decreasing the bias current applied to the delay cells and reducing the output frequency thereof. Once the output frequency again matches the reference frequency, DEC will return to zero, thus causing the gates of P 4  and P 5  to be pulled back up to V DD , shutting off current through N 7  and increasing the value of current through N 11  to the amount determined by integral current control signal V_I. In the exemplary embodiment depicted, the frequency range of the ICO  210  with a supply voltage of about 0.8 V is about 70 MHz to about 1033 MHz, representing a factor of more than 10. 
   One key advantage of this method of proportional control is that the amount of current added to or subtracted from the V_I current is easy to change, simply by changing the bias voltage at nodes IPUMP_REF 1  and IPUMP_REF 2 . Changing the current added or subtracted is equivalent to changing the value of the “R” in the RC low pass filter of  FIG. 1 . The loop bandwidth and the damping are affected by the equivalent resistance, and thus this provides an easy way to control both the loop bandwidth and damping. 
     FIG. 6  is a plot of the output frequency versus the bias current at two different values of the control voltage VCNTL (which again represents the output of the gain control block  220  of  FIG. 2 ). As can be seen, the effect of the VCNTL is to flatten the curves such that the gain is reduced. By way of example, at an operating frequency of 300 MHz, the gain is about 4.93 MHz/μA with VCNTL=1.0 V, but only 3.21 MHz/μA with VCNTL=1.5V. Also shown in  FIG. 6  is the output frequency vs. bias current curve for a conventional delay cell with no gain control capability. That is, the NFETs N 4  and N 5  in  FIG. 4  are simply replaced with short circuits. As will thus be appreciated, the use of the series NFETs along with a variable VCNTL voltage affords a means of changing the slope (i.e., the gain) of the characteristics at any desired frequency. The gain of an oscillator impacts the phase noise characteristics through the bandwidth of the control loop. Thus, by reducing the bandwidth of the loop, the output noise may also be reduced. 
     FIG. 7  is a block diagram illustrating an example of a design flow  700 . Design flow  700  may vary depending on the type of IC being designed. For example, a design flow  700  for building an application specific IC (ASIC) will differ from a design flow  700  for designing a standard component. Design structure  710  is preferably an input to a design process  720  and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Design structure  710  comprises circuit embodiments  200 ,  210 ,  302 ,  216  in the form of schematics or HDL, a hardware-description language, (e.g., Verilog, VHDL, C, etc.). Design structure  710  may be contained on one or more machine readable medium(s). For example, design structure  710  may be a graphical representation of circuit embodiments  200 ,  210 ,  302 ,  216  illustrated in  FIGS. 2-5 . Design process  720  synthesizes (or translates) circuit embodiments  200 ,  210 ,  302 ,  216  into a netlist  730 , where netlist  730  is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc., and describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of a machine readable medium. This may be an iterative process in which netlist  730  is resynthesized one or more times depending on design specifications and parameters for the circuit. 
   Design process  720  includes using a variety of inputs; for example, inputs from library elements  735  which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications  740 , characterization data  750 , verification data  760 , design rules  770 , and test data files  580 , which may include test patterns and other testing information. Design process  720  further includes, for example, standard circuit design processes such as timing analysis, verification tools, design rule checkers, place and route tools, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process  720  without deviating from the scope and spirit of the invention. The design structure of the invention embodiments is not limited to any specific design flow. 
   Design process  720  preferably translates embodiments of the invention as shown in  FIGS. 2-5 , along with any additional integrated circuit design or data (if applicable), into a second design structure  790 . Second design structure  790  resides on a storage medium in a data format used for the exchange of layout data of integrated circuits (e.g. information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures). Second design structure  790  may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce embodiments of the invention as shown in  FIGS. 2-5 . Second design structure  790  may then proceed to a stage  795  where, for example, second design structure  790 : proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc. 
   While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.