Patent Publication Number: US-2022223377-A1

Title: Voltage waveform generator for plasma processing apparatuses

Description:
TECHNICAL FIELD 
     The present disclosure is related to a voltage waveform generator for a plasma processing apparatus, and to a related method of generating a voltage waveform for use in plasma processing, in particular a voltage waveform for producing a voltage bias on a substrate to be plasma processed. 
     INTRODUCTION 
     In plasma assisted etching and plasma assisted layer deposition radio frequency (RF) generators are used to generate a bias voltage for controlling the ion energy. To improve process control, accurate control of the bias voltage and the resulting ion energy distribution (IED) is of importance. Generating this bias voltage is done with limited efficiency (wideband) linear amplifiers or with limited flexibility (narrowband) switch-mode amplifiers or dedicated pulse generating amplifiers. Most amplifiers are only indirectly controlling the output voltage waveform (e.g. controlling output power or relying on calibration), resulting in limited performance (the generated waveform is less close to the desired output voltage waveform), resulting in a less desired ion energy distribution and limited reproducibility (wafer to wafer variation and system to system variation). 
     U.S. Pat. No. 9,208,992 describes a plasma processing apparatus comprising a switch mode power supply for forming a periodic voltage function at an exposed surface of the substrate to be processed. The periodic voltage function effectuates a desired ion energy intensity distribution to perform etching of the substrate or plasma deposition on the substrate. 
     The above switch mode power supply can generate a waveform of particular shape with a DC current to compensate for the ion current (see FIG. 14 of U.S. Pat. No. 9,208,992). To do so, the switch mode power supply comprises two switch components that are coupled in a half-bridge and are controlled based on drive signals generated by a controller as shown in FIG. 3; of U.S. Pat. No. 9,208,992. With such a waveform, the reactor capacitance and stray inductance experience commutation resulting in losses. The relation between system parameters and the commutation (or switching) losses P can be expressed as: 
       P REACTOR COMMUTATION ∝C REACTOR ·V COMMUTATION ·f COMMUTATION  
 
     Typical ranges for the parameters are:
         C REACTOR : 500 pF to 10 nF,   V COMMUTATION : 10 V to 2 kV,   f COMMUTATION : 20 kHz to 1 MHz.       

     Depending on the process conditions and reactor design, this can result in losses over 500 W. 
     In current plasma processes, there is a tendency towards higher commutation voltage levels, larger reactors sizes, with higher capacitance C REACTOR  Using the prior art waveform generator would thus entail even higher losses, which is unacceptable. 
     In addition, a plasma reactor has an inherent reactor capacitance and the interconnection between reactor and bias voltage generator a stray inductance, which form a LC circuit having an inherent resonance characteristic. Due to the resonance in the system, slow switching speeds (limited dV/dt on the switch node) or a damping resistance (or snubber) are mandatory to prevent excitation of the resonance which would cause undesired ringing of the substrate voltage. This ringing would result in an undesired voltage on the substrate, which has a negative influence on the desired IED. Such slow switching speed results in long discharge time periods effectively reducing the process/discharge ratio, which in turn results in a longer time to process the substrate. A too long discharge time can additionally have a negative influence on the sheath formation or preservation of the sheath. However, a damping resistance (or snubber) would cause additional undesired losses. 
     SUMMARY 
     It is an aim of the present disclosure to overcome the above drawbacks. It is an aim of the present disclosure to provide a voltage waveform generator for use in plasma processing and related method of generating a voltage waveform, which allows for obtaining higher efficiency. It is an aim to provide such generator and method allowing for increasing process throughput with no or limited efficiency loss. 
     It is an aim of the present disclosure to provide plasma processing apparatuses and related methods that allow for an improved process control. In particular, it is an aim to provide such apparatuses and methods that enable to approach the ideal or desired voltage waveform more precisely and/or which allow for faster convergence to such ideal waveform. 
     According to a first aspect of the present disclosure, there is provided a method of generating a voltage waveform for use in plasma processing. The voltage waveform is advantageously a periodic bias voltage that is applied to an exposed surface of a substrate undergoing plasma processing, such as plasma assisted etching, plasma assisted layer deposition, or Reactive Ion Etching (REI). 
     According to a second aspect of the present disclosure, there is provided a voltage waveform generator for a plasma processing apparatus. The voltage waveform generator is advantageously configured to generate a periodic bias voltage to be applied to a substrate that is subjected to plasma processing. The voltage waveform generator is advantageously configured to implement the method according to the first aspect. 
     According to a third aspect of the present disclosure, there is provided a plasma processing apparatus, comprising the voltage waveform generator of the second aspect. 
     The voltage waveform generator according to the present disclosure comprises a power stage topology allowing generation of a periodic bias voltage, e.g. for use in a plasma processing apparatus. The power stage topology comprises different voltage levels which can consecutively be coupled to the output for obtaining the periodic bias voltage. The number of voltage levels is such that resonant commutation during a change of voltage levels of the waveform can be obtained, resulting in fast and lossless commutation. Furthermore, advantageously, through appropriate control of the timing of the switches that apply the different voltage levels, and through appropriate selection of the voltage levels, it can be obtained that at the end of the commutation (discharge) period, the desired substrate voltage level is reached, which is advantageously substantially equal to the generator output voltage, and the current though the stray inductance of the interconnection between the generator and the substrate is approximately 0 A. As a result, there is no ringing in the system, obviating the need to implement damping or slow commutation. The lossless commutation allows for generating the bias voltage in a highly efficient manner. The fast commutation reduces the disturbance of the sheath during the discharge period. This results in better process control. The fast commutation makes it possible to further narrow down the IED. A narrow IED is critical for process control. 
     According to another aspect, a method of controlling or operating a plasma processing apparatus is described herein. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure will now be described in more detail with reference to the appended drawings, wherein same reference numerals illustrate same features and wherein: 
         FIG. 1  represents an example of a voltage waveform generator used as bias generator for an ICP (Inductively Coupled Plasma) reactor according to aspects of the present disclosure; 
         FIG. 2  represents a simplified reactor plasma model and the voltage waveform generator according to the present disclosure coupled to it; 
         FIG. 3  represents (periodic) voltage waveforms (not drawn to scale) that can be applied to the nodes indicated in  FIG. 2 ; 
         FIG. 4  represents a voltage waveform generator according to a first embodiment of the present disclosure; 
         FIG. 5  represents the voltage waveform generator of  FIG. 4 , with a simplified model of the load coupled to the power stage of the voltage waveform generator; 
         FIG. 6  represents a possible switch implementation of the voltage waveform generator of  FIG. 4 , with N-channel MOSFETs; 
         FIG. 7  represents the voltage waveform generator of  FIG. 4 , in which the DC current source has been implemented with a DC voltage source and coupled inductor, and optionally a transient voltage suppressor (TVS); 
         FIG. 8  represents a graph showing the relation between the power stage voltage levels and the switch control signals for the voltage waveform generator of  FIG. 4 ; 
         FIG. 9  represents schematically a closed loop control implementation of the voltage waveform generator of  FIG. 4 ; 
         FIG. 10  represents the voltage waveform generator of  FIG. 4  with added commutation inductances; 
         FIG. 11  represents a graph showing voltage and current levels during a commutation according to aspects of the present disclosure with switch slew-rate; 
         FIG. 12  represents a graph showing voltage and current levels during a non-optimal commutation with switch slew-rate; 
         FIG. 13  represents a voltage waveform generator as in  FIG. 4  including an overvoltage protection circuit; 
         FIG. 14  represents a first implementation example of the overvoltage protection circuit of  FIG. 13 ; 
         FIG. 15  represents a second implementation example of the overvoltage protection circuit of  FIG. 13 ; 
         FIG. 16  represents a voltage waveform generator according to a second embodiment of the present disclosure, with a continuous current source; 
         FIG. 17  represents a possible switch implementation of the voltage waveform generator of  FIG. 16 , with N-channel MOSFETs. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows one of the typical usages of a bias voltage waveform generator (BVG)  10  in an Inductively Coupled Plasma (ICP) apparatus  100 , where the BVG  10  is controlling the substrate  101  (typically a wafer) voltage by controlling the substrate stage voltage. In a plasma reactor  102 , a plasma  103  is generated by introduction of a plasma forming gas  104  in a dielectric tube  108  surrounded by an induction coil  107 . The arrangement forms a plasma torch which directs the plasma  103  towards a platform  105  (substrate stage) on which the substrate  101  is positioned. Optionally, a precursor  109  can be introduced in the plasma reactor  102 . A RF voltage is applied to the induction coil  107  through a RF power supply  120 , and a matching network  121  as known in the art. The RF power supply  120 , as well as the BVG  10  can be controlled through a system host controller  130 . Plasma processes suitable for the present disclosure are so called low or reduced pressure plasma, i.e. operating at a pressure significantly below atmospheric pressure, e.g. between 1 mTorr and 10 Torr. To this end, the plasma reactor  102  is advantageously airtight and the desired pressure in plasma reactor  102  is obtained through a vacuum pump  106 . 
     The BVG  10  can also be used in other configurations like a Capacitively Coupled Plasma (CCP) reactor, or with a direct inter connection (not via the system host) of control signals between a source power generator (RF power supply) and BVG. A different source can be used to generate the plasma (e.g. Capacitively Coupled Plasma, Electron Cyclotron Resonance, Magnetron, DC voltage, etc.). 
       FIG. 2  represents a (highly) simplified electrical model of a plasma reactor, showing the load posed by the reactor and the plasma on the BVG  10  so as to explain the operation of the BVG  10 . BVG  10  comprises a power stage  11  which is coupled to the output terminal  12  of the BVG  10  through an optional physical capacitor C 1  to prevent DC current from the voltage induced on the surface of the substrate  101 , or from the voltage of an electronic chuck from flowing through the power stage  11 . The power stage  11  is configured to generate a bias voltage which is applied at output terminal  12 . The DC component of this bias voltage is self-biasing due to C 1 , e.g. the voltage is set due to the difference in ion and electron mobility in the sheath. The plasma reactor can be modeled as shown in  FIG. 2 , although more or less complex models can be used as well. L 1  is a lumped inductance representing the inductance caused by the BVG output power interconnection and return path. C 2  is a lumped capacitance representing the capacitance from the substrate stage  105  and substrate stage power interconnection to earth. This capacitance is usually dominated by the capacitance from the substrate table to the dark shield, i.e. a metal shield adjacent the platform  105  preventing the plasma to propagate beyond the platform, e.g. into pump  106 . C 3  is the combined capacitance of the dielectric substrate and/or substage stage of dielectric material (e.g. due to the electrostatic chuck holder on/in the substrate stage). R P  Represents the sheath impedance, caused by the limited ion mobility in the sheath, during the process period. D P  Represents the high electron mobility in the sheath, during the discharge period. V PL  is the plasma potential at the sheath above the substrate. 
     A DC (bias) voltage over the sheath ideally results in a narrow IED, with the level of the DC voltage controlling the level of the (average) ion energy. There is a charge build up on dielectric substrates and/or substage stages of dielectric material (e.g. electrostatic chuck holders) caused by the positively charged ions that are collected on the surface. This charge build up on the substrate and/or substrate stage needs to be compensated for to keep the voltage potential over the sheath (and therefore the ion energy) constant. The charge build up and therefore the potential over the substrate and/or substrate stage needs to be limited to prevent damage of the substrate and/or substrate stage. This compensation can be achieved by a periodic discharge of the substrate and/or substrate stage during a discharge period T D  between consecutive process periods T P  as shown in  FIG. 3 .  FIG. 3  shows an ideal periodic voltage waveform V P  to be generated by the BVG, so as to obtain an ideal voltage waveform V S  on the exposed surface of the substrate. The nodes V P , V T , V S  in which the waveforms are evaluated are shown in  FIG. 2 , where V P  represents the voltage output by the power stage  11 , V T  the voltage at the substrate stage (table)  105 , and V S  the substrate voltage, i.e. the voltage on the exposed surface of the substrate  101 . Typical values for the discharge period T D  can be on the order of 500 ns. Typical values for the processing period T P  can be on the order of 10 μs. 
     According to the present disclosure, the drawbacks of the prior art relating to excessive commutation losses and uncontrolled resonance ringing are remedied by implementing a particular commutation in the power stage  11  of the BVG  10 , referred to as resonant commutation. Referring to  FIG. 4 , to make resonant commutation possible, the power stage  11  comprises a first DC power supply, implemented as a voltage source  21  configured to output a DC voltage of a first magnitude V 1 . DC voltage source  21  is connected to an output node  14  of the power stage  11  through a first switch SW 1 . The power stage  11  further comprises a second DC power supply, implemented as a current source  51  configured to output a DC current of a second magnitude I 2 , and a ground terminal  13  providing earth potential. In the present embodiment, DC current source  51  is connected to output node  14  through a second switch SW 2 . The ground terminal  13  is connected to an intermediate node  15  between the current source  51  and the second switch SW 2  through a bypass switch SW 5 . 
     Closing both switches SW 2  and SW 5  connects ground terminal  13  to the output node  14 . The output node is connected to the output terminal  12  of the BVG  10 , which in turn can be coupled to the substrate stage  105 . DC blocking capacitor C 1  can optionally be coupled between the output node  14  and the output terminal  12 . 
     In addition, power stage  11  comprises a third DC power supply, and a fourth DC power supply, both being implemented as voltage sources  31 ,  41  respectively and configured to output DC voltages of a third magnitude V 3  and a fourth magnitude V 4 , respectively. DC voltage source  31  and  41  are connected to the output node  14  through respective third and fourth switches SW 3 , SW 4 . The interconnection lines between voltage sources  31  and  41  and output node  14  can advantageously comprise diodes D 3  and D 4  respectively to allow current in one direction only. All the voltage sources  21 - 41  are parallel connected to output node  14 . 
     A simplified model of the load as seen by the output node  14  is shown in  FIG. 5 .  FIG. 6  shows a possible implementation of switches SW 1  through SW 5  using N-channel MOSFETs. 
     Referring to  FIG. 7 , the DC current source  51  can alternatively be implemented using a DC voltage source  52  in series with an inductor  53  typically having a large inductance, e.g. 0.5 mH or more. A transient voltage suppressor  54  is advantageously placed over SW 5  to provide a continuous current path for inductor  53 , and to limit the voltage over SW 5 . Other alternative implementations use a power amplifier generating a variable DC current, e.g. for compensation of dielectric constant change due to voltage biasing. Likewise, alternative implementations of voltage sources  21 ,  31  and  41  are possible, e.g. based on a current source with capacitor connected between current source output and ground. It is alternatively possible to connect the low voltage side of voltage source  41  (connected to ground in  FIG. 7 ) to the low voltage side of voltage source  52 . This allows to use only voltage sources providing positive voltages. 
     According to the present disclosure, the additional DC voltage sources  31  and  41  allow for reducing or eliminating commutation losses and resonance ringing during or after commutation when obtaining a desired bias voltage waveform. Referring to  FIG. 8 , the switches SW 1  through SW 5  can be operated using control signals following the sequence shown. To obtain the desired periodic voltage waveform V S  at the substrate  101 , the BVG  10  will need to output a voltage waveform V P  at the output node  14 , depending on the modeled load (see e.g.  FIG. 2 ). V P  can comprise a positive voltage peak to obtain a substrate discharge, followed by a voltage drop and ramp down during a processing time of the substrate. 
     Advantageously, the waveform V P  can include at least three distinct voltage levels: a first positive voltage of magnitude V 1 , which is advantageously supplied by voltage source  21 , a second negative voltage of magnitude V 5 , obtained by ramping down the voltage when connecting current source  51  to the load, and ground potential V 0 . The voltage waveform generator  10  according to the present disclosure advantageously allows for obtaining such waveform by using the additional voltage sources  31  and  41  to provide for intermediate voltage levels V 3  and V 4  in the waveform V P  for effecting the voltage rise towards V 1  on the one hand, and the voltage drop to ground potential V 0 , or even to V 5 , on the other. These additional (intermediate) voltage levels, allow for avoiding undesired voltage oscillation following a commutation event by using an appropriate switching timing between the different voltage levels. 
     By way of example, and still referring to  FIG. 8 , starting at time T 0 , a substrate discharge period T D  is started in which the substrate voltage V S  is brought to a positive value. To this end, switch SW 4  is closed at T 0 , while the other switches SW 1 , SW 2  and SW 3  remain open, except for the bypass switch SW 5  which may be closed as well to provide for a current path for current I 2 . Closing SW 4  causes V P  to rise to the magnitude V 4  of voltage source  41 . Next, at T 1 , SW 1  is closed causing V P  to rise to level V 1 . SW 4  is advantageously opened somewhat after T 1 , since V 4  is lower than V 1  and due to the presence of diode D 4 . The magnitude V 1  is advantageously selected to make the substrate voltage V S  positive. 
     To start a new processing period T P  following the substrate discharge period T D , V S  is made negative again. To do so, switch SW 1  and advantageously also SW 4  are opened, e.g. at time T 2 , and somewhat later, at T 3 , switch SW 3  is closed causing the voltage V P  to fall to the magnitude V 3  of voltage source  31 , until switch SW 2  is closed at time T 4  connecting the output node to ground potential (causing a (further) drop of V P ) since switch SW 5  remains closed until a later time T 5 . This marks the beginning of the processing period T P . The magnitudes V 3 , V 4  and V 1  are advantageously maintained constant during closure of the respective switches, and the magnitude may be continuously constant throughout operation. 
     At T 5 , SW 5  is opened while SW 2  is kept closed. This causes the output node  14  to be connected to the current source  51  and current I 2  will effect a voltage ramp down of V P  advantageously allowing to maintain the substrate voltage V S  at a constant level, by compensating for the charge build up on the substrate and/or substrate stage. Just prior to starting a new discharge period, bypass switch SW 5  is closed at time T 7 , advantageously somewhat after opening switch SW 2  at time T 6 . 
     Switch SW 3  can be opened at some time past T 4  and possibly even past T 5  due to diode D 3 . Note that there is advantageously no dead time required between SW 4  and SW 1  (due to diode D 4 ) and between SW 3  and SW 2  (due to diode D 3 ). The dead time T 3 −T 2  is required to prevent short circuiting of V 1  and V 3 . 
     The power stage  11  as described herein allows to be operated (by generating appropriate switching control signals for switches SW 1 -SW 5 ) in such a way to minimize the oscillations on the output and to prevent parasitic resonance in the system. To this end, the power stage is advantageously operated such that the current through L 1  is brought to 0 A at the end of a commutation period. In the waveform of  FIG. 8 , there are basically two commutation periods. A first commutation is during a voltage rise phase, in particular starting at T 0 , i.e. the closure of SW 4 , and ending at T 1 , i.e. the closure of SW 1 . A second commutation is during a voltage drop phase. This commutation period starts at T 3 , i.e. the closure of SW 3  and ends at T 4 , i.e. the closure of SW 2 . 
     To ensure that the current through L 1  can be brought to 0 A at end of a commutation period, in particular at T 4 , and advantageously also at T 1 , the instants T 1  and T 4  in which the switches SW 1  respectively SW 2  are closed (or equivalently the switching intervals T 1 −T 0  and T 4 −T 3 ), are advantageously appropriately selected. If the switch (SW 1  or SW 2 ) closes too late, an oscillation between L 1  and the voltage V P  on the output node  14  is induced due to a capacitance on the output node  14  and the fact that the voltage on this capacitance is not equal to the voltage on C 4 . If the switch (SW 1  or SW 2 ) closes too early the current through L 1  is not 0 A and this will cause a ringing between L 1  and C 4 . The criticality of selecting the appropriate switching time is shown in  FIGS. 11 and 12 . In  FIGS. 11 and 12 , T 0  and T 1  represent the instants at which control signals are applied to switches SW 4  and SW 1  to close the respective switch. In practice, the switches will have a finite switching speed which is shown in  FIGS. 11 and 12  by a finite dV/dt on the voltage V P  at the output node  14 . As a result, the switch SW 4  will start closing at T 0  and the closed state will be achieved at instant T SW4 . Similarly, switch SW 1  starts closing at T 1  and the closed state will be achieved at instant T SW1 . 
     As can be seen from  FIG. 11 , the closed state of switch SW 1  is achieved at an instant T SW1  at which the current I L1  through L 1  has fallen to zero, and oscillation of the voltage at the substrate stage V T  or at the substrate V S  is prevented. This is not the case in  FIG. 12 , where the closed state of SW 1  (T SW1 ) is achieved at an instant in which I L1  is not zero at T SW1 . 
     In addition to the above, oscillation is advantageously prevented by appropriate selection of the voltage level applied during a commutation period (V 3  respectively V 4 ). The voltage level advantageously falls between the voltage level at commutation start (instants T 0  and T 3  respectively) and the voltage level at commutation end (instants T 1  and T 4  respectively). It can be shown that an optimal voltage level of V 3  and V 4  equals (V END COMMUTATION +V START COMMUTATION )/2. In other words, an optimal magnitude of V 3  is the average of V P  at T 0  and T 1 . An optimal magnitude of V 4  is the average of V P  at T 3  and T 4 . 
     When the load of the BVG  10  as seen at output node  14  can be modeled as a series LC circuit with reactor inductance L 1  and total capacitance C 4  as shown in  FIG. 5 , the optimal commutation time T COMMUTATION  equaling T 1 −T 0  and T 4 −T 3  respectively can be set as T COMMUTATION =π√{square root over (L 1 C 4 )} where C 4  represents the equivalent capacitance as seen from output node  14 , e.g. the total of C 1 , C 2  and C 3  in the model of  FIG. 2 . More generally, it can be stated that the optimal commutation time T COMMUTATION  assuming ideal conditions corresponds to half the period corresponding to the fundamental natural frequency f 0  (resonant frequency) of the load, or T COMMUTATION =0.5/f 0 . 
     In the above it is assumed that all components, e.g. switches, diodes, and the lumped model of the plasma reactor are ideal and lossless. Since this will not correspond to a real situation, the commutation parameters can be further adapted to take non-ideal situations into account. One may start operation based on the values for the commutation parameters (commutation time, commutation voltage) as determined above. During operation, one or more of these commutation parameters are advantageously adapted by implementing an appropriate process control, e.g. through a closed loop control algorithm, e.g. based on current feedback. Referring to  FIG. 9 , the BVG  10  comprises a controller  16  configured to control operation of the power stage  11 . In particular, controller  16  is configured to output switch control signals  161  to control operation of switches SW 1  through SW 5 . Controller  16  can be configured to output voltage setpoints  162  to set the magnitude of one or more of DC voltage sources  21 ,  31 ,  41  and possibly  52 . Controller  16  can further be configured to output a current setpoint  163  to set the level of DC current I 2  output by current source  51 . Alternatively, one or more of the DC voltage sources  21 ,  31 ,  41  and  52 , and/or current source  51  can have a voltage or current output of fixed magnitude. 
     Controller  16  advantageously comprises a feedback control loop, advantageously a current feedback control loop  164 . Current control loop  164  comprises a current sensor  165  configured to measure the current output by the power stage  11 . Current sensor  165  can be arranged at output node  14 . Controller  16  can comprise a first input  167  coupled to current control loop  164 , which is configured to feed the value of the output current measured by current sensor  165  to the controller  16 . Through a second input  166 , controller  16  can be configured to receive setpoints for one or more of the switch control signals  161 , the voltage setpoints  162  and the current setpoint  163 . These setpoints can be received from a system host controller or user interface, which may be configured to determine the setpoints based on a model of the load of the BVG  10 , e.g. as determined in the previous paragraphs. Controller  16  may be configured to adjust the setpoints, in particular switch control signals  161  and/or voltage setpoints  162 , based on the input  167  fed back from the current sensor  165 . 
     Referring to  FIG. 10 , to improve control of the commutation period and make the commutation less sensitive to the closing moment of SW 1  or SW 2  in case of reactors with a high self-resonance frequency (e.g. low C 4  and/or low L 1 ), commutation inductors L 3  and L 4  can be added in series with commutation switches SW 3  and SW 4 . Alternatively, or in addition, an inductor can be added series with the output blocking capacitor C 1  (not shown). 
     The diagram of  FIG. 10  additionally comprises an overvoltage protection circuit, implemented through diode DFW and a bidirectional transient voltage suppressor TVS FW  allowing to protect an overvoltage between SW 4  and L 4 . 
     Referring to  FIG. 13 , an overvoltage protection circuit  17  can be provided at the output of the power stage  11  or BVG  10  and configured to protect the power stage  11  by clamping the output voltage. Possible implementations of the overvoltage protection circuit are shown in  FIGS. 14 and 15 . The overvoltage protection circuit can comprise a diode D 1  between output node  14  and the voltage source  21 . Between output node  14  and earth potential, a diode D 2  and unidirectional transient voltage suppressor TVS 1  are coupled in opposite current direction. When a current through the clamping diodes and/or TVS is detected by current measurement sensors  171 ,  172  or  173 , the power stage  11  can be turned off to reduce losses. 
     Referring to  FIGS. 16 and 17 , in an alternative embodiment of power stage  110  for the BVG  10 , current source  51  is coupled between the output node  14  and the output terminal  12 , advantageously between output node  14  and output blocking capacitor C 1 . This allows to have a continuous compensation current I 2 , although the voltage across current source  51  will be higher than for power stage  11 . In power stage  110 , the bypass switch SW 5  can be omitted, even though switch SW 2  should have bidirectional voltage blocking and current conduction capability.