Patent Publication Number: US-7898588-B2

Title: Dual conversion gain gate and capacitor and HDR combination

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 11/178,324, filed on Jul. 12, 2005 now U.S. Pat. No. 7,728,896, the subject matter of which is incorporated in its entirety by reference herein. 
    
    
     The invention relates generally to semiconductor imaging devices and in particular to a CMOS active pixel sensor (“APS”) imager having an array of pixel cells and circuitry for the cells. 
     BACKGROUND OF THE INVENTION 
     There is a current interest in CMOS active pixel sensor imagers for use as low cost imaging devices.  FIG. 1  shows a signal processing system  100  that includes a CMOS active pixel sensor (“APS”) pixel array  230  and a controller  232  that provides timing and control signals to enable the read out of signals stored in the pixels in a manner commonly known to those skilled in the art. Exemplary arrays have dimensions of M×N pixels, with the size of the array  230  depending on a particular application. The imager pixels are readout a row at a time using a column parallel readout architecture. The controller  232  selects a particular row of pixels in the array  230  by controlling the operation of row addressing circuit  234  and row drivers  240 . Signals stored in the selected row of pixels are provided on column lines to a readout circuit  242 . The pixel signals read from each of the columns are then readout sequentially using a column addressing circuit  244 . 
       FIG. 2  shows the pixel array  230  of the system  100  of  FIG. 1  in greater detail.  FIG. 2  illustrates a six transistor (6T) CMOS pixel cell  10  in the pixel array  230 . The 6T CMOS pixel cell  10  generally comprises a photo-conversion device  23  for generating and collecting charge generated by light incident on the pixel cell  10 , and a transfer transistor  27  for transferring charge from the photo-conversion device  23  to a sensing node, typically a floating diffusion region  5 . The floating diffusion region  5  is electrically connected to the gate of an output source follower transistor  19 . The pixel cell  10  also includes a reset transistor  16  for resetting the floating diffusion region  5  to a predetermined voltage (shown as the array pixel supply voltage Vaa_pix); and a row select transistor  18  for outputting a signal from the source follower transistor  19  to an output column line in response to a row select signal. Although not required, in this exemplary pixel cell  10 , a capacitor  20  may also be included to increase the charge storage capacity of floating diffusion region  5 . One plate of the capacitor  20  is coupled to Vaa_pix and the other plate of the capacitor  20  is coupled to the floating diffusion region  5  through a dual conversion gain (“DCG”) transistor  21 . Although also not required, in this exemplary pixel  10 , a high dynamic range (“HDR”) transistor  25  is included. One source/drain of HDR transistor  25  is coupled to Vaa_pix and the other source/drain of the HDR transistor  25  is coupled to the photo-conversion device  23 . 
     In the CMOS pixel cell  10  depicted in  FIG. 2 , electrons are generated by light incident on the photo-conversion device  23 . These charges are transferred to the floating diffusion region  5  by the transfer transistor  27  when the transfer transistor  27  is activated. The source follower transistor  19  produces an output signal based on the transferred charges. The output signal is proportional to the number of electrons extracted from the photo-conversion device  23 . When DCG transistor  21  is enabled, capacitor  20  is coupled to the floating diffusion region  5  and increases the storage capability and charges the conversion gain of floating diffusion region  5 . When HDR transistor  25  is enabled, Vaa_pix is coupled to the photo-conversion device  23  and drives some charges away from the photo conversion device  23  which increases the dynamic range of pixel cell  10 . 
     It is desirable to increase the fill factor and charge storage capacity of the pixels  10  in the array  230 . However, the inclusion of a capacitor  20  and DCG transistor  21  and the control lines to control them requires space in the pixel  10  and/or in the array  230 . Additionally, the HDR transistor  25  (to increase the dynamic range) requires space in the pixel  10  and/or in the array  230 . There is a tradeoff of space: the greater space consumed by capacitors and the transistors, the less space available for the photo-conversion device  23 . As such, including capacitors and transistors and the control lines to control them in the array  230  affects the fill factor of the array  230 . Therefore, it is desirable to include controllable capacitors and transistors to increase charge storage capacity and dynamic range without significantly effecting the fill factor of the array  230 . 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention provides a method and apparatus for more efficient capacitor placement and metal routing in pixels employing dual conversion gain (DCG) and high dynamic range (HDR) transistors. 
     In one aspect of the invention, one activation circuit is shared by a DCG transistor and an HDR transistor. 
     In another aspect of the invention, the shared activation circuit includes a common gate for DCG and HDR transistors. 
     In another aspect of the invention, the common gate also provides one plate of a capacitor employed in a dual conversion gain circuit. 
     In another aspect of the invention, a plurality of pixels forming a pixel circuit has respective HDR transistors activated by a shared activation circuit which share a readout circuit. 
     In another aspect of the invention, a shared activation circuit is provided for a plurality of HDR transistors in one pixel circuit formed by a pair of pixels and a DCG circuit for a different pixel circuit formed by another pair of pixels. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features and advantages of the invention will be more readily understood from the following detailed description of the invention which is provided in connection with the accompanying drawings, in which: 
         FIG. 1  is a block diagram of a conventional APS system; 
         FIG. 2  is a schematic diagram of a portion of a pixel array of  FIG. 1 ; 
         FIG. 3  is a schematic diagram of a portion of a pixel array in accordance with an exemplary embodiment of the invention; 
         FIG. 4  is a schematic diagram of a portion of a sample and hold circuit in accordance with an exemplary embodiment of the invention; 
         FIG. 5  is a timing diagram depicting a partial operation of the pixel array of  FIG. 3  and the sample and hold circuit of  FIG. 4  in accordance with an exemplary embodiment of the invention; 
         FIG. 6  is an additional timing diagram depicting a partial operation of the pixel array of  FIG. 3  and the sample and hold circuit of  FIG. 4  in accordance with an exemplary embodiment of the invention; 
         FIG. 7  is a timing diagram depicting a partial operation of the pixel array of  FIG. 3  and the sample and hold circuit of  FIG. 4  in accordance with another exemplary embodiment of the invention; 
         FIG. 8  is a plan view of a portion of the device of  FIG. 3 ; and 
         FIG. 9  is a block diagram showing a processor system incorporating at least one imaging device constructed in accordance with an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific exemplary embodiments of the invention. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to make and use the invention, and it is to be understood that structural, logical, or other changes may be made to the specific embodiments disclosed without departing from the spirit and scope of the present invention. 
       FIG. 3  shows an exemplary embodiment of the invention in the form of an imaging device  600  that combines the control signal lines for high dynamic range and dual conversion gain transistors to reduce the space required in the device  600 . Imaging device  600  includes pixels  300   a  through  300   l  in accordance with the illustrated embodiment of the invention. Pixels  300   a  and  300   g ,  300   b  and  300   h ,  300   c  and  300   i ,  300   d  and  300   j ,  300   e  and  300   k , and  300   f  and  300   l  are part of respective identical pixel circuits  610   a ,  610   b ,  610   c ,  610   d ,  610   e ,  610   f , which are part of pixel array  601 . Taking pixel circuit  610   b  as representative, pixels  300   b  and  300   h  respectively include a photo-conversion device  623   b    633   b , and a transfer transistor  627   b ,  637   b . Pixel circuit  610   b  also includes floating diffusion region  605   b  and reset transistor  616   b , and readout circuitry, i.e., source follower transistor  619   b  and row select transistor  618   b , which are shared by pixels  300   b  and  300   h . Pixel circuit  610   b  also includes a DCG/HDR circuit that includes a transistor  641   b  and a capacitor  640   b , and HDR transistors  625   b ,  635   b . The DCG/HDR circuit is connected to pixel circuit  610   b  and  610   d . Pixel circuits  610   a ,  610   c ,  610   d ,  610   e ,  610   f  are similarly constructed as pixel circuit  610   b.    
     The DCG/HDR circuitry of pixel circuit  610   b  is operated by a control line  609   b  for the HDR transistors  625   b  and  635   b , but the capacitor is actually connected through DCG transistor  641   b  to the floating diffusion region  605   d  of a pixel circuit  610   d  to the left and below pixel circuit  610   b . Likewise, the DCG/HDR circuitry of pixel circuit  610   c  is shared with circuit  610   e , and so on throughout a pixel array. As seen in  FIG. 3  with respect to pixel circuit  610   b  as representational of the other pixel circuits  601   a ,  610   c ,  610   d ,  610   e , and  610   f , DCG/HDR circuitry is shared with a diagonally located pixel circuit, one pixel circuit row below and one pixel circuit column over, i.e., pixel circuits  610   b  and  610   d . The floating diffusion region  605   d  of pixel circuit  610   d  is switchingly coupled to capacitor  640   b  in pixel circuit  610   b  by DCG transistor  641   b . The same sharing of DCG/HDR circuit applies to pixel circuits  601   a ,  610   c ,  610   d ,  610   e , and  610   f , although not all neighboring pixel circuits are shown in  FIG. 3 . Therefore, a DCG/HDR control signal carried on line  609   b  not only controls HDR transistors  625   b ,  635   b  of pixel circuit  610   b , which switchingly couples photo-conversion devices  623   b ,  633   b  to Vaa_pix, but also controls DCG transistor  641   b , which switchingly couples capacitor  640   b  of pixel circuit  610   b  to the floating diffusion region  605   d  of pixel circuit  610   d . The capacitor  640   b  of pixel circuit  610   b  stores a charge with the floating diffusion region  605   d  of pixel circuit  610   d  through switch  641   b  of pixel circuit  610   b , line  611   b , and line  612   d . As such, the control signal carried on line  609   b  controls two different circuits: the HDR transistors  625   b ,  635   b  in pixel circuit  610   b  and the DCG transistor  641   b , which couples capacitor  640   b  to the floating diffusion region  605   d  of pixel circuit  610   d . Thus, the DCG signal for a pixel circuit row is the same signal used for the HDR signal of the previous pixel circuit row. Although the invention is described with reference to sharing control signals between diagonally located pixel circuits—i.e., one pixel circuit row and one pixel circuit column apart, the invention is not so limited. 
     It is conventionally known during the manufacture of imaging devices such as imaging device  600  to include dummy pixels and dummy pixel circuits around the periphery of the pixel array  601 . Although not shown, pixel circuits on the edge of a pixel array  601  are coupled to dummy pixel circuits to maintain the consistency of the diagonally-shared charges and control signals. For example, if pixel circuit  610   b  is located on the top edge of the pixel array  601 , then pixel circuit  610   b  shares a capacitor connected to line  612   b  in a dummy pixel circuit one column over to the right and one pixel circuit row above pixel circuit  610   b.    
     With the pixels circuits (e.g.,  610   b ,  610   d ) sharing circuitry and control signals, the amount of circuitry required and space needed in and around the pixel array  601  to operate the pixel array  601  is reduced. As such, the pixel array  601  of imaging device  600  includes HDR and DCG circuits and can take advantage of the benefits that accompany the inclusion of the HDR and DCG circuits without significantly affecting the fill factor of the pixel array  601 . 
     Pixel circuits in a pixel circuit common column share a readout column line  701 , e.g.  701   a ,  701   b , and are coupled to a shared sample and hold circuit  700  ( FIG. 4 ). In an exemplary embodiment, signals are read from the pixel array  601  ( FIG. 3 ) pixel row by pixel row starting with the top pixel row and proceeding incrementally to the bottom pixel row. For example, pixels  300   a ,  300   b , and  300   c  would be readout at substantially the same time. Then pixels  300   g ,  300   h , and  300   i  would be readout at substantially the same time. Then pixels  300   d ,  300   e , and  300   f  would be readout at substantially the same time. The row by row readout of the pixel array continues until the last row of the array. 
     Three signals are readout from each pixel: Vrst—the reset signal, Vsig—the charge signal, and Vdcg—the second charge or dual conversion gain signal. Operation of the pixel array is described in greater detail below. Depending on the type of shutter used, a read ahead integration may be employed, as discussed more fully below. 
       FIG. 4  is a schematic diagram of a portion of a sample and hold circuit  700  in accordance with an exemplary embodiment of the invention. Although only one sample and hold circuit  700  is depicted, sample and hold circuit  700  is representative of a sample and hold circuit  700  for each column of pixel circuits in the pixel array. As indicated above, in an exemplary embodiment three signals are read out from each pixel, e.g., Vrst 1 , Vsig 1 , Vdcg 1 . 
     In an exemplary embodiment as seen in  FIG. 4 , each of the three signals received from the associated pixel circuit are separately stored in the sample and hold circuit  700 . Sample and hold circuit  700  has a subcircuit  730  for storing signals from the pixel. Subcircuit  730  has three capacitors  714 ,  716 ,  718  for storing signals Vrst 1 , Vsig 1 , Vdcg 1 . Capacitors  714 ,  716 ,  718  are selectively coupled to the column line  701   a  through switches  706 ,  708 ,  710 , respectively, which are controlled by control signals SHR 1 , SHS 1  and SDCG 1 . Capacitors  714 ,  716 ,  718  are selectively coupled to downstream circuitry through switches  722 ,  724 ,  726 , respectively. 
     The stored Vrst, Vsig, Vdcg signals can be read out and if preferred, combined, in many different ways. For example, in an exemplary embodiment, an external circuit (not shown) controls switches of the sample and hold circuit  700  depending on the value of the value Vsig. For example, a threshold value is established (usually during manufacture), where the threshold is indicative of an abundance of signal value that has occurred during pixel readout, thus a dual conversion gain transformation may be applied. During readout, the Vsig is compared to the threshold value. If Vsig&gt;threshold then the pixel output signal is Vrst-Vdcg. Otherwise, the output signal is Vrst-Vsig. Thus, for example, if the stored signals of subcircuit  730  are to be combined in a differential amplifier (not shown) coupled to the sample and hold circuit  700  and Vsig 1  is greater than the threshold, then switches  724  and  726  are closed and capacitors  716  and  718  are coupled with the differential amplifier. If Vsig 1  is not greater than the threshold, then switches  722  and  726  are closed and capacitors  714  and  718  are coupled with the differential amplifier. 
       FIG. 5  is a timing diagram depicting a partial operation of the pixel array  601  of  FIG. 3  and the sample and hold circuit  700  of  FIG. 4  in accordance with an exemplary embodiment of the invention. For simplicity, the readout of one pixel is depicted and is representational of the other pixels being readout. In the timing diagram of  FIG. 5 , the signals are active “high,” i.e., high logic state. A “Row” is a row of pixels e.g.,  300   a ,  300   b ,  300   c  ( FIG. 3 ). The first row of pixels is Row  0 , e.g., pixels  300   a ,  300   b ,  300   c  ( FIG. 3 ); the second row of pixels is Row  1 , e.g.,  300   g ,  300   h ,  300   i  ( FIG. 3 ). Row  5  is not depicted in  FIG. 3 , but is described as part of the timing diagram of  FIG. 5 . 
     In  FIG. 5 , Addr is the pixel circuit row address of the pixel row being readout and ras is the read address signal. ROW  0 , ROW  1 , and ROW  5  are representational of the row select gate signals for pixel rows  0 ,  1 , and  5 , respectively. In implementation, a global row select signal is provided to the row decode circuitry, which AND&#39;s the row select signal with the Addr signal to provide the row select gate signal to the appropriate row. For example, if Addr is “000”, then the row decode provides a row select gate signal to row  0 . Tx 0 , 0 , Tx 1 , 0 , Tx 2 , 0 , Tx 3 , 0  and Tx 5 , 0  are the representational transfer gate signals for row  0 , first pixel, i.e., pixel  300   a , row  1 , first pixel, i.e., pixel  300   g , row  2 , first pixel, i.e., pixel  300   d , row  3 , first pixel, i.e., pixel  300   j ; rows, first pixel, (not shown). In implementation, global transfer gate signals are provided to the column decode circuitry, which decodes the global transfer gate signal and the current desired pixel column to provide the transfer gate signal to the appropriate column. For example, during pixel column read of the pixel array the column decode circuitry will generate a Tx signal, e.g., Txj, 0  that will enable corresponding transfer gate in a j th  row and first column. For example, during a first row, column read a Tx 0 , 0  is enabled for pixel  300   a . During a second pixel column read of the pixel array the column decode circuitry will provide an enable signal on the next Tx signal, e.g., Tx_, 1  that will enable corresponding transfer gate. For example, during a first row, second column read a Tx 0 , 1  is enabled for pixel  300   b . Reset 0 , Reset 1 , and Reset 5  are the representational reset gate signals for rows  0 ,  1 , and  5 , respectively. In implementation, a global reset signal is provided to the row decode circuitry, which AND&#39;s the reset signal with the Addr signal to provide the reset signal to the appropriate row. In this case, each pixel will receive two row signals. For example, pixel circuit  610   a  receives a row  0 , and a row  1  signal, which collectively control row select transistor  618   a . DCGHDR 0 , DCGHDR 1 , and DCGHDR 2  are the representational DCG/HDR gate control signals for rows  0 ,  1 , and  2 . A DCGHDR of row  0  appears to apply to a gate in a different pixel circuit. For example, the DCGHDR signal for pixel  300   d  (and  300   j ) is DCGHDR 2  (as it is in the third pixel row). However, the DCGHDR 2  signal is applied to and controls a gate  641   b  in pixel circuit  610 . In implementation, a global DCGHDR signal is provided to the row decode circuitry, which AND&#39;s the DCGHDR signal with the Addr signal to provide the DCGHDR signal to the appropriate DCGHDR gate. 
     In  FIG. 5 , SHR 1 , SHS 1 , and SDCG 1  are the signals that enable the switches  706 ,  708 ,  710  to couple capacitors  714 ,  716 ,  718  to the column line  701   a , respectively. 
     In  FIG. 5 , time period t 0  indicates the initial setup time period during which the pixel circuit row address of the pixels cells to be readout is provided. In this example during t 0 , an Addr of 000 is provided which corresponds to the first pixel row of the first pixel circuit row (i.e., row  0 ). Although the example describes the readout from one pixel, e.g., pixel  300   a , of one pixel circuit, e.g., pixel circuit  610   a  ( FIG. 3 ), this example is representational of all of pixels in a pixel row of a pixel circuit row being readout at substantially the same time as is conventionally known. 
     During time period t 1 , pixel circuit  610   a  is reset and the reset charge is stored as follows. Control signals Row 0 , Reset 0 , DCGHDR 0  and SHR 1  are enabled (i.e., asserted high) ( FIG. 5 ). The Row 0  signal closes switch  618   a  and couples pixel circuit  610   a  to a column line ( FIG. 3 ). The Reset 0  signal closes switch  616   a  and couples Vaa_pix to the pixel circuit  610   a  ( FIG. 3 ). The DCGHDR 0  signal closes switch  641   x  (a switch in a pixel circuit  610   x  not illustrated in  FIG. 3  that is similar to switch  641   a , where pixel circuit  610   x  is one pixel circuit row above and one column to the right of pixel circuit  610   a ) and couples photo-conversion device  623   a  to the floating diffusion region  605   a  and the capacitor  640   x  (a capacitor in pixel circuit  610   x  not illustrated in  FIG. 3  that is similar to capacitor  640   a ) through line  612   a  to a pixel circuit one row above and one row to the right of pixel circuit  610   a . The SHR 1  signal closes switch  706  and couples capacitor  714  to pixel circuit  610   a  through column line  701   a . Thus at the end of time period t 1 , pixel circuit  610   a  is reset and the reset voltage of the pixel circuit  610   a  is stored in the sample and hold circuit  700 . Control signals Reset 0 , DCGHDR 0 , and SHR 1  are disabled (i.e., driven low) by the end of time. When DCGHDR 0  is pulsed, the photo-conversion devices of previous pixel circuit row (not shown) are reset at the same time. As such, the integration time of the pixel array requires calculating the integration time to reflect two pixel circuit rows being accessed. Although discussed in terms of enabling and disabling a control signal, this series of actions may also be referred to as pulsing—asserting/deasserting—a control signal as is commonly known. 
     During time period t 2 , the integration charge (i.e., photosignal) of the pixel circuit  610   a  is readout and stored as follows. Control signals Tx 0 , 0  and SHS 1  are enabled (i.e., driven high). The Tx 0 , 0  signal closes switch  627   a  and couples photo-conversion device  623   a  to the floating diffusion region  605   a . The SHS 1  signal closes switch  708  and couples capacitor  716  to pixel circuit  610   a  through column line  701   a . The charge stored on floating diffusion region  605   a  is read out and stored on the capacitor  716 . Thus at the end of t 2 , the signal voltage Vsig 1  of the pixel circuit  610   a  is stored in the sample and hold circuit  700 . Control signals Tx 0 , 0  and SHS 1  are disabled (i.e., driven low) by the end of time period t 2  ( FIG. 5 ). 
     During time period t 3 , any additional integration charge of the pixel circuit  610   a  is readout and stored as follows. Control signals Tx 0 , 0  SDCG 1 , and DCGHDR 0  are enabled (i.e., driven high). The Tx 0 , 0  signal closes switch  627   a  and switch  641   x  (a switch in a pixel circuit  610   x  not illustrated in  FIG. 3  that is similar to switch  641   a , where pixel circuit  610   x  is one pixel circuit row above and one column to the right of pixel circuit  610   a ) and couples photo-conversion device  623   a  to the floating diffusion region  605   a  and the capacitor  640   x  (a capacitor in pixel circuit  610   x  not illustrated in  FIG. 3  that is similar to capacitor  640   a ) through line  612   a  to a pixel circuit one row above and one row to the right of pixel circuit  610   a . The SDCG 1  signal closes switch  710  and couples capacitor  718  to pixel circuit  610   a  through column line  701   a . The charge stored on floating diffusion region  605   a  and capacitor  640   x  is read out and stored on the capacitor  718 . Thus at the end of t 3 , any additional signal voltage of the pixel circuit  610   a  is stored in the sample and hold circuit  700 . Control signals Row  0 , Tx 0 , 0 , SDCG 1 , and DCGHDR 0  are disabled (i.e., driven low) by the end of time period t 3  ( FIG. 5 ). Thus pixel circuit  610   a  has been reset, integrated, readout and stored at the end of time period t 3 . 
     During time period t 4  the integration process is commenced for a row five pixel rows ahead of Row 0 . As is commonly known, when a mechanical shutter is not used, a pixel circuit row of pixels is initiated for integration in advance of the readout. In the exemplary embodiment, a row is initiated five rows ahead of the current row being readout. As such; since Row 0  has been readout, Row 5  is then prepared for integration. Time period t 4  indicates the initial setup time period during which the pixel circuit row address of the pixels cells to be initiated is provided. In this example during time period t 4 , an Addr of 005 is provided. Although the example describes the initiation of one pixel cell this is representational of all of pixels in a pixel row of a pixel circuit row being initiated at substantially the same time as is conventionally known. 
     In time period t 5 , control signals Reset 5  and Tx 5 , 0  are enabled (i.e., driven high) ( FIG. 5 ). Pixel  300   y  (not illustrated in  FIG. 3 ) is a pixel similar to pixel  300   a  and five pixel rows below pixel circuit  300   a . The Reset 5  signal closes switch  616   y  (a switch in pixel  300   y  not illustrated in  FIG. 3  that is similar to switch  616   a ) and couples Vaa_pix to the pixel circuit  610   y . The Tx 5 , 0  signal closes switch  635   y  (a switch in pixel circuit  300   y  not illustrated in  FIG. 3  that is similar to switch  635   a ) and couples photo-conversion device  633   y  (photo-conversion device in pixel circuit  300   y  not illustrated in  FIG. 3  that is similar to photo-conversion device  633   a ) to Vaa_pix. Thus at the end of time period t 5 , pixel  300   y  is reset and ready for integration. Control signals Reset 5  and Tx 5 , 0  are disabled (i.e., driven low) ( FIG. 5 ). After which, the pixel circuit  300   y  integrates. 
     As is conventionally known, a readout from a pixel array actually comprises a series of successive readouts. During initial readouts from the pixel array different adjustments and calculations may occur. For example, during the initial readouts exposure settings are adjusted. After a first readout of the pixel array, the values read from the array are computed and exposure is adjusted. A pixel array is readout a second time and the values read from the array are computed and exposure is again adjusted. The final, usable readout from the pixel array may occur after several initial readouts. As such, the pixel is readout in a rolling manner, i.e., that if pixel array has 100 rows and the pixel array is successively readout from row  0  to  99 , then on subsequent readouts of the pixel array, row  0  is readout after row  99 . Thus, in the present example when row  95  is being readout, row  0  (five rows ahead) is initiated for readout. While the invention describes a five row ahead initiation, the invention is not so limited. 
       FIG. 6  is a timing diagram depicting a partial operation of the integration of pixel array of  FIG. 3  in accordance with an exemplary embodiment of the invention. For simplicity, time periods t 0 , t 1 , t 2 , t 3 , t 4  are referred to, but are not the same as the time periods t 0 , t 1 , t 2 , t 3 , t 4  of  FIG. 5 . In the timing diagram of  FIG. 6 , the signals are active or enabled “high,” i.e., high logic state. 
     GBL_HDR is the global control signal for the HDRDCG signal. This is combined (e.g., “ANDed”) with the local address of a pixel row to provide the HDRDCG of the row. SHUTTER is the control signal for a mechanical shutter to control exposure of the pixel array. Frame Valid is the control signal that an imager typically produces to indicate to the image system that a valid image is being readout. 
     As depicted in  FIG. 6 , the system alternates between integrating charge, e.g., time periods t 2 , t 4 , and reading out signals, e.g., time periods t 1 , t 3 . During an integration time period, e.g., time period t 2 , a SHUTTER signal is enabled thereby temporary opening the mechanical shutter (not shown) of the pixel array. A GBL_HDR is enabled whereby the DCG_HDR transistors in the pixel array are enabled, i.e., closed. For example, the GBL_HDR enabled would close transistors  625 ,  635   a  in pixel circuit  610   a , where pixel circuit  610   a  is representational of all of the pixel circuits, e.g.,  610   a ,  610   b ,  610   c ,  610   d ,  610   e , and  610   f . The GBL_HDR varies over the integration time period t 2 , starting at a high level, where the pixels are reset and the level falls off, i.e., decreases, over time as the pixels integrate. At the end of time period t 2 , the GBL_HDR and the SHUTTER signals are disabled. 
       FIG. 7  is a timing diagram depicting a partial operation of the pixel array  601  of  FIG. 3  and the sample and hold circuit  700  of  FIG. 4  in accordance with another exemplary embodiment of the invention. The timing diagram of  FIG. 7  is applicable to systems that use a mechanical shutter and thus, there is no need to start a row integration several rows before the pixel circuit row is readout. As such, the timing diagram of  FIG. 7  is similar to the timing diagram of  FIG. 5 , but not does include initiation time periods t 4  and t 5  ( FIG. 5 ). 
       FIG. 8  shows a plan view of a circuit layout of a portion of the pixel array  601  of  FIG. 3 .  FIG. 8  shows a row select transistor  618 , source follower transistor  619 , DCG transistor  641 , HDR gate  625 , transfer transistor  627 , capacitor  640 , reset transistor  616 , floating diffusion region  605 , and photo-conversion region  623 . 
       FIG. 9  shows a system  1100 , a typical processor system modified to include an imager device  600  (as constructed in  FIG. 3 ). The system  1100  is exemplary of a system having digital circuits that could include image sensor devices. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision, vehicle navigation, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, and other image acquisition or processing system. 
     System  1100 , for example a camera system, generally comprises a central processing unit (CPU)  1110 , such as a microprocessor, that communicates with an input/output (I/O) device  1150  over a bus  1170 . Imaging device  600  also communicates with the CPU  1110  over the bus  1170 . The system  1100  also includes random access memory (RAM)  1160 , and can include removable memory  1130 , such as flash memory, which also communicate with the CPU  1110  over the bus  1170 . The imaging device  600  may be combined with a processor, such as a CPU, digital signal processor, or microprocessor, with or without memory storage on a single integrated circuit or on a different chip than the processor. 
     It should be appreciated that other embodiments of the invention include a method of manufacturing the circuit  1100 . For example, in one exemplary embodiment, a method of manufacturing an CMOS readout circuit includes the steps of providing, over a portion of a substrate corresponding to a single integrated circuit, at least a pixel array with shared control lines ( FIG. 3 ) as described above using known semiconductor fabrication techniques. 
     While the invention has been described and illustrated with reference to specific exemplary embodiments, it should be understood that many modifications and substitutions can be made without departing from the spirit and scope of the invention. For example, although the invention is described with reference to sharing DCG/HDR control signals between diagonally located pixel circuits, the invention is not so limited. Thus, a single control signal can be used to control what was previously controlled by a plurality of separate signals. Accordingly, the invention is not to be considered as limited by the foregoing description but is only limited by the scope of the claims.