Patent Publication Number: US-2022231039-A1

Title: Semiconductor devices including stack structure having gate region and insulating region

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application is a continuation of U.S. patent application Ser. No. 16/856,560, filed Apr. 23, 2020, which application claims benefit of priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0086900 filed on Jul. 18, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     Example embodiments of the present inventive concepts relate to semiconductor devices, and more particularly, to semiconductor devices including a stack structure having a gate region and an insulating region. 
     A semiconductor device including gate electrodes stacked in a direction perpendicular to a surface of a semiconductor substrate has been developed. To improve integration density of a semiconductor device, the number of the stacked gate electrodes has been increased. As the number of the gate electrodes stacked in the direction perpendicular to the surface of the semiconductor substrate has been increased, difficulty in a process of electrically connecting the gate electrodes to a peripheral circuit has increased, and unexpected defects have occurred. 
     SUMMARY 
     An example embodiment of the present inventive concepts provides semiconductor devices which may have improved integration density. 
     According to an example embodiment of the present inventive concepts, a semiconductor device includes a lower structure including a lower substrate, an upper substrate on the lower substrate, a peripheral circuit region between the lower substrate and the upper substrate and including peripheral wirings, and a gap-fill insulating layer penetrating the upper substrate; a stack structure in a memory cell array region on the lower structure and extending into a connection region on the lower structure, wherein the stack structure has a staircase structure in the connection region, the stack structure includes a gate region and a first insulating region, the gate region is in the memory cell array region and extends into the connection region, and the first insulating region is in the connection region; a capping insulating layer on the stack structure; and a memory cell vertical structure in the gate region in the memory cell array region, the stack structure includes a plurality of first layers and a plurality of second layers alternately stacked on the lower structure, the plurality of second layers include a plurality of gate layers in the gate region, a plurality of mold layers in the first insulating region, a plurality of gate pads extending from the plurality of gate layers, and a plurality of mold pads extending from at least one of the mold layers, each of the plurality of gate layers includes a conductive material, each of the plurality of mold layers includes an insulating material, the plurality of mold layers include one or a plurality of lower mold layers, a plurality of intermediate mold layers on the one or the plurality of lower mold layers, and one or a plurality of floating mold layers on the plurality of intermediate mold layers, the plurality of mold pads include a plurality of intermediate mold pads extending from at least one of the plurality of intermediate mold layers, the plurality of intermediate mold pads include a staircase structure descending in a first direction, the first direction extends to the connection region from the memory cell array region, the plurality of intermediate mold pads include a plurality of first intermediate mold pads, and a second intermediate mold pad between a pair of the plurality of first intermediate mold pads, each of the plurality of first intermediate mold pads has a first length in the first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, at least one of the plurality of intermediate mold pads has a mold pad portion and an insulating protrusion portion on the mold pad, at least one of the plurality of first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and at least a central region of the second intermediate mold pad does not include the insulating protrusion portion. 
     According to an example embodiment of the present inventive concepts, a semiconductor device includes a lower structure; a stack structure in a memory cell array region on the lower structure and extending into a connection region on the lower structure, where the stack structure includes a gate region including a plurality of gate pads and an insulating region including a plurality of mold pads; and a memory cell vertical structure penetrating the gate region in the memory cell array region, the plurality of mold pads includes a plurality of intermediate mold pads, the plurality of intermediate mold pads include a plurality of first intermediate mold pads, and a second intermediate mold pad between a pair of the plurality of first intermediate mold pads, each of the plurality of first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, at least one intermediate mold pad of the plurality of intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, at least one first intermediate mold pad of the plurality of first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and at least a central region of the second intermediate mold pad does not include the insulating protrusion portion. 
     According to an example embodiment of the present inventive concepts, a semiconductor device includes a lower structure including a lower substrate, an upper substrate on the lower substrate, a peripheral circuit region between the lower substrate and the upper substrate and including peripheral wirings, and a gap-fill insulating layer penetrating the upper substrate; a stack structure in a memory cell array region on the lower structure and extending into a connection region on the lower structure, where the stack structure includes a gate region and an insulating region, the gate region is in the memory cell array region and extends into the connection region, and the first insulating region is in the connection region; a memory cell vertical structure penetrating the gate region in the memory cell array region; and a capping insulating layer on the stack structure, the stack structure includes a plurality of first layers and a plurality of second layers alternately stacked on the lower structure, the plurality of first layers comprise interlayer insulating layers, the plurality of second layers include a plurality of gate layers in the gate region, a plurality of mold layers in the insulating region, a plurality of gate pads extending from the gate layers, and a plurality of mold pads extending from at least some of the mold layers, the plurality of mold pads include a plurality of intermediate mold pads, the plurality of intermediate mold pads include a plurality of first intermediate mold pads and a second intermediate mold pad between a pair of the plurality of first intermediate mold pads, each of the plurality of first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, the first direction extends to the connection region from the memory cell array region, and at least one of the plurality of first intermediate mold pads has a first thickness, and a central region of the second intermediate mold pad includes an insulating material layer having a second thickness less than the first thickness, or the central region of the second intermediate mold pad comprises the capping insulating layer. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The above and other aspects, features, and advantages of the present inventive concepts will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a plan diagram illustrating a semiconductor device according to an example embodiment of the present inventive concepts; 
         FIG. 2  is an enlarged plan diagram illustrating portion “A” illustrated in  FIG. 1 ; 
         FIGS. 3 to 12  are cross-sectional diagrams illustrating an example of a semiconductor device according to an example embodiment of the present inventive concepts; 
         FIGS. 13A and 13B  are enlarged cross-sectional diagrams illustrating a modified example of a semiconductor device according to an example embodiment of the present inventive concepts; 
         FIGS. 14 and 15  are enlarged cross-sectional diagrams illustrating another modified example of a semiconductor device according to an example embodiment of the present inventive concepts; 
         FIG. 16  is an enlarged cross-sectional diagram illustrating another modified example of a semiconductor device according to an example embodiment of the present inventive concepts; 
         FIG. 17  is an enlarged cross-sectional diagram illustrating another modified example of a semiconductor device according to an example embodiment of the present inventive concepts; 
         FIG. 18  is an enlarged cross-sectional diagram illustrating another modified example of a semiconductor device according to an example embodiment of the present inventive concepts; 
         FIG. 19  is an enlarged cross-sectional diagram illustrating another modified example of a semiconductor device according to an example embodiment of the present inventive concepts; 
         FIGS. 20A to 20C  are cross-sectional diagrams illustrating modified examples of a semiconductor device according to an example embodiment of the present inventive concepts; 
         FIG. 21  is a flowchart illustrating an example of a method of manufacturing a semiconductor device according to an example embodiment of the present inventive concepts; and 
         FIGS. 22A to 23B  are cross-sectional diagrams illustrating an example of a method of manufacturing a semiconductor device according to an example embodiment of the present inventive concepts. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, embodiments of the present inventive concepts will be described with reference to the accompanying drawings. 
     An example of a semiconductor device according to an example embodiment of the present inventive concepts will be described with reference to  FIGS. 1 to 12 . In the description below, each element will be described with reference to  FIGS. 1 to 12 , and an example of each element will be described with reference to portions of  FIGS. 1 to 12 . With regard to  FIGS. 1 to 12 ,  FIG. 1  is a plan diagram illustrating a semiconductor device according to an example embodiment of the present inventive concepts,  FIG. 2  is an enlarged plan diagram illustrating portion “A” illustrated in  FIG. 1 ,  FIG. 3  is a cross-sectional diagram taken along line I-I′ in  FIG. 2 ,  FIG. 4  is an enlarged plan diagram illustrating portion “B” illustrated in  FIG. 3 ,  FIG. 5  is a cross-sectional diagram taken along line II-II′ in  FIG. 2 ,  FIG. 6  is an enlarged plan diagram illustrating portion “C” illustrated in  FIG. 5 ,  FIG. 7  is a cross-sectional diagram taken along line in  FIG. 2 ,  FIG. 8  is an enlarged plan diagram illustrating portion “D” illustrated in  FIG. 7 ,  FIG. 9  is a cross-sectional diagram taken along line IV-IV′ in  FIG. 2 ,  FIG. 10  is an enlarged plan diagram illustrating portion “E” illustrated in  FIG. 9 ,  FIG. 11  is a cross-sectional diagram taken along line V-V′ in  FIG. 2 , and  FIG. 12  is an enlarged diagram illustrating portions “F 1 ” and “F 2 ” illustrated in  FIG. 11 . 
     Referring to  FIGS. 1 to 12 , a semiconductor device  1  in the example embodiment may include a lower structure  3 , a memory cell array region MA on the lower structure  3 , and a connection region EA. The memory cell array region MA and the connection region EA may be adjacent to each other. 
     The lower structure  3  may include a lower substrate  5 , an upper substrate  12  on the lower substrate  5 , and a peripheral circuit region  7  between the lower substrate  5  and the upper substrate  12 . 
     The lower structure  3  may further include a gap-fill insulating layer  13  penetrating the upper substrate  12 , and an intermediate insulating layer  14  on, and in some embodiments, surrounding, the upper substrate  12 . The peripheral circuit region  7  may include peripheral wirings  8  and a lower insulating layer  9  on, and in some embodiments covering, the peripheral wirings  8 . 
     The semiconductor device  1  in the example embodiment may include a stack structure ST on the lower structure  3 . 
     The stack structure ST may be disposed in the memory cell array region MA, and may extend into the connection region EA. 
     The stack structure ST may include a gate region GA including a conductive material, and an insulating region IA which does not include a conductive material. 
     The gate region GA may be disposed in the memory cell array region MA, and may be partially disposed in the connection region EA. The insulating region IA may be disposed in the connection region EA, and may be adjacent to the gate region GA. 
     The stack structure ST may include first layers  20  and second layers  23  alternately stacked on the lower structure  3 . 
     The first layers  20  may be disposed in the gate region GA and the insulating region IA. The first layers  20  may be configured as interlayer insulating layers. 
     The second layers  23  may include gate layers  29 G,  31 G,  33 G, and  35 G disposed in the gate region GA, and mold layers  29 M,  31 M, and  35 M disposed in the insulating region IA. 
     In an example embodiment, the mold layers  29 M,  31 M, and  35 M may be formed of an insulating material having etching selectivity different from an etching selectivity of the first layers  20 . For example, the first layers  20  may be formed of silicon oxide, and the mold layers  29 M,  31 M, and  35 M may be formed of silicon nitride. 
     In an example embodiment, each of the gate layers  29 G,  31 G,  33 G, and  35 G may include a conductive material. For example, each of the gate layers  29 G,  31 G,  33 G, and  35 G may be configured as gate electrodes. 
     The gate layers  29 G,  31 G,  33 G, and  35 G may include one or a plurality of lower gate layers  29 G, a plurality of intermediate gate layers  31 G on the one or the plurality of lower gate layers  29 G, and a plurality of upper gate layers  33 G on the plurality of intermediate gate layers  31 G. 
     The mold layers  29 M,  31 M, and  35 M may include one or a plurality of lower mold layers  29 M, a plurality of intermediate mold layers  31 M on the one or the plurality of lower mold layers  29 M, and a plurality of upper mold layers  35 M on the plurality of intermediate mold layers  31 M. 
     The lower and intermediate gate layers  29 G and  31 G and the lower and intermediate mold layers  29 M and  31 M disposed on the same level in a boundary region between the gate region GA and the insulating region IA may be on opposite sides of each other and may be in contact with each other. 
     The gate layers  29 G,  31 G,  33 G, and  35 G may further include floating gate layers  35 G, and the mold layers  29 M,  31 M, and  35 M may further include floating mold layers  35 M. 
     The floating gate layers  35 G may be disposed on the plurality of intermediate mold layers  31 M in the connection region EA, and may be spaced apart from the plurality of upper gate layers  33 G. The floating mold layers  35 M may be disposed on the plurality of intermediate mold layers  31 M in the connection region EA, and may be spaced apart from the plurality of upper gate layers  33 G. 
     The gate layers  29 G,  31 G,  33 G, and  35 G may include a plurality of gate pads arranged in staircase form, and the mold layers  29 M,  31 M, and  35 M may include a plurality of mold pads arranged in staircase form. As used herein, a “staircase form” or “staircase structure” refers to a plurality of layers in which an outermost edge of a first layer extends laterally beyond an outermost edge of a second layer that is immediately above the first layer. 
     The one or the plurality of lower gate layers  29 G may include one or a plurality of lower gate pads  29 GP, the plurality of intermediate gate layers  31 G may include intermediate gate pads  31 GP, the plurality of upper gate layers  33 G may include upper gate pads  33 GP, and the floating gate layers  35 G may include floating gate pads  35 GP. 
     The one or the plurality of lower mold layers  29 M may include one or a plurality of lower mold pads  29 MP, the plurality of intermediate mold layers  31 M may include intermediate mold pads  31 MP, and the floating mold layers  35 M may include floating mold pads  35 MP. 
     The semiconductor device  1  in the example embodiment of the present inventive concepts may further include a memory cell vertical structure  46  in the memory cell array region MA. The memory cell vertical structure  46  may penetrate the gate region GA of the stack structure ST. 
     The semiconductor device  1  in the example embodiment may further include a plurality of separation structures  69   a,    69   b,  and  69   c.    
     The plurality of separation structures  69   a,    69   b,  and  69   c  may include a plurality of first separation structures  69   a  crossing the memory cell array region MA and the connection region EA, a plurality of second separation structures  69   b  crossing the memory cell array region MA and extending into a partial region of the connection region EA, and a plurality of third separation structures  69   c  disposed in the connection region EA. 
     The plurality of second separation structures  69   b  may be disposed between the plurality of first separation structures  69   a.  The plurality of third separation structures  69   c  may be disposed between the plurality of first separation structures  69   a.    
     The stack structure ST may be divided into a plurality of regions by the plurality of first separation structures  69   a.  As illustrated in  FIG. 2 , in the connection region EA, the stack structure ST may include a first stack region ST 1 , a second stack region ST 2  on a first side of the first stack region ST 1 , and a third stack region ST 3  on a second side of the first stack region ST 1 , opposite the first side. Accordingly, in the connection region EA, the first stack region ST 1  may be disposed between the second stack region ST 2  and the third stack region ST 3 . The first stack region ST 1 , the second stack region ST 2 , and the third stack region ST 3  may be separated from one another by ones of the plurality of first separation structures  69   a.    
     The plurality of third separation structures  69   c  may be disposed in the first stack region ST 1 , and may not be disposed in the second stack region ST 2  and the third stack region ST 3 . 
     In the first stack region ST 1 , the plurality of third separation structures  69   c  and the plurality of second separation structures  69   b  may have end portions opposing each other. 
     In the stack structure ST, the gate region GA may be disposed across the memory cell array region MA and the first stack region ST 1 , and may be disposed in a portion of the second stack region ST 2  and a portion of the third stack region ST 3 . 
     In the stack structure ST, the insulating region IA may include a first insulating region IA 1  disposed in a portion of the second stack region ST 2  and a second insulating region IA 2  disposed in a portion of the third stack region ST 3 . 
     In the connection region EA, the upper gate layers  33 G may include upper gate pads  33 GP descending to a first height (e.g., in the Z direction in  FIG. 3 ) in a first direction X. In other words, respective ones of the upper gate pads  33 GP are lower in the Z direction as the respective upper gate pads  33 GP extend in the first direction X. The first direction X may be directed to the connection region EA from the memory cell array region MA. 
     In the connection region EA, the intermediate gate layers  31 G and the intermediate mold layers  31 M may respectively include intermediate pads  31 GP and  31 MP descending to a second height (e.g., in the Z direction in  FIGS. 3 and 5 ) higher than the first height in the first direction X. In other words, a distance between respective adjacent ones of the intermediate pads  31 GP and  31 MP is greater in the Z direction than a distance between respective adjacent ones of upper gate pads  33 GP. 
     The intermediate pads  31 GP and  31 MP may include the intermediate gate pads  31 GP of the intermediate gate layers  31 G and the intermediate mold pads  31 MP of the intermediate mold layers  31 M. In the second stack region ST 2  and the third stack region ST 3 , respective ones of the intermediate pads  31 GP and  31 MP may be disposed at a constant level in a second direction Y. In the first stack region ST 1 , respective ones of the intermediate pads  31 GP and  31 MP may be lowered to the first height in a direction from the second stack region ST 2  to the third stack region ST 3 . 
     In the connection region EA, the lower gate layers  29 G and the lower mold layers  29 M may include lower pads  29 GP and  29 MP lowered to a first height in the first direction X from a staircase having a certain height in the second stack region ST 2  and lowered to the first height in a direction towards the third stack region ST 3  from the second stack region 
     ST 2  in the first stack region ST 1 . The lower pads  29 GP and  29 MP may include lower gate pads  29 GP of the lower gate layers  29 G and lower mold pads  29 MP of the lower mold layers  29 M. 
     The first direction X may be directed to the connection region EA from the memory cell array region MA, and the second direction Y may be perpendicular to the first direction X. 
     In the connection region EA, the floating gate layers  35 G and the floating mold layers  35 M may include floating pads  35 GP and  35 MP lowered to a second height in a direction towards the upper gate pads  33 GP from a staircase having a certain height in the second stack region ST 2  and lowered to the second height in a direction towards the third stack region ST 3  from the second stack region ST 2  in the first stack region ST 1 . 
     The floating pads  35 GP and  35 MP may include floating gate pads  35 GP of the floating gate layers  35 G and floating mold pads  35 MP of the floating mold layers  35 M. 
     In example embodiments, the first height may refer to a distance between upper surfaces of the second layers  23  adjacent to each other in a vertical direction Z. 
     In example embodiments, the second height may be greater than the first height. For example, the second height may refer to a distance between an upper surface of a lowermost second layer of four second layers  23  arranged in the vertical direction Z and an upper surface of an uppermost second layer. 
     A first capping insulating layer  40  and a second capping insulating layer  43  may be disposed on the stack structure ST. The first capping insulating layer  40  may be on, and in some embodiments cover, an uppermost second layer of the second layers  23 , and the second capping insulating layer  43  may have an upper surface coplanar with an upper surface of the first capping insulating layer  40  and may be on, and in some embodiments cover, a remaining portion of the stack structure ST. 
     A first upper insulating layer  66  and a second upper insulating layer  72  stacked in order may be disposed on the first capping insulating layer  40  and the second capping insulating layer  43 . The first to third separation structures  69   a,    69   b,  and  69   c  may penetrate the stack structure ST, may extend upwardly, and may penetrate the first and second capping insulating layers  40  and  43  and the first upper insulating layer  66 . 
     Bit line contact plugs  78  penetrating the first upper insulating layer  66  and the second upper insulating layer  72  and electrically connected to the memory cell vertical structure  46  may be disposed. 
     In the connection region EA, gate contact structures  75  penetrating the first upper insulating layer  66  and the second upper insulating layer  72 , extending downwardly, and electrically connected to the lower, intermediate, and upper gate pads  29 GP,  31 GP, and  33 GP may be disposed. 
     Peripheral contact structures  81  in contact with peripheral pad portions  8 P of the peripheral wirings  8 , extending upwardly, and penetrating the gap-fill insulating layer  13  and the insulating region IA of the stack structure ST may be disposed. 
     Gate connection wirings  85  may be disposed on the gate contact structures  75  and the peripheral contact structures  81 . 
     In an example embodiment, in the connection region EA, dummy contact plugs  75   d  penetrating the first upper insulating layer  66  and the second upper insulating layer  72 , extending downwardly, and electrically connected to the floating gate pads  35 GP may be disposed. The dummy contact plugs  75   d  may be electrically insulated from the gate connection wirings  85 . Bit lines  84  may be disposed on the bit line contact plugs  78 . 
     In the description below, the intermediate mold pads  31 MP of the intermediate mold layers  31 M will be described in greater detail with reference to  FIGS. 3 and 4 . 
     Referring to  FIGS. 3 and 4 , the intermediate mold pads  31 MP of the intermediate mold layers  31 M may include first intermediate mold pads  31 MPa and a second intermediate mold pad  31 MPb disposed between the first intermediate mold pads  31 MPa. The second intermediate mold pad  31 MPb may be disposed between some of the plurality of first intermediate mold pads  31 MPa and some of the plurality of first intermediate mold pads  31 MPa. 
     The first intermediate mold pads  31 MPa may respectively have the same or similar structure, and the second intermediate mold pad  31 MPb may have a structure different from the structure of each of the first intermediate mold pads  31 MPa. 
     In an example embodiment, each of the first intermediate mold pads  31 MPa may have a first length in the first direction X, and the second intermediate mold pad  31 MPb may have a second length in the first direction X, greater than the first length. 
     In an example embodiment, each of the first intermediate mold pads  31 MPa and the second intermediate mold pad  31 MPb may include a mold pad portion  24   a  and an insulating protrusion portion  24   b  on the mold pad portion  24   a.    
     The insulating protrusion portion  24   b  may be formed of a material having etching selectivity different from etching selectivity of the mold pad portion  24   a.  For example, the mold pad portion  24   a  may be formed of a first insulating material based on (e.g., including) silicon nitride, and the insulating protrusion portion  24   b  may be formed of a second insulating material based on (e.g., including) silicon nitride having an etching speed higher than an etching speed of the first insulating material, though the present inventive concepts are not limited thereto. For example, the mold pad portion  24   a  may be formed of a first silicon nitride, and the insulating protrusion portion  24   b  may be formed of a second silicon nitride configured to be more porous than the first silicon nitride. The second silicon nitride may have an etching speed higher than an etching speed of the first silicon nitride with respect to an etchant including phosphate. 
     In an example embodiment, the second intermediate mold pad  31 MPb may include a first portion  31 Mb 1  and a second portion  31 Mb 2  spaced apart from each other in the first direction X. The first portion  31 Mb 1  and the second portion  31 Mb 2  may be spaced apart from the memory cell array region MA in order. For example, the first portion  31 Mb 1  may be between the second portion  31 Mb 2  and the memory cell array region MA in the first direction X. 
     Each of the first portion  31 Mb 1  and the second portion  31 Mb 2  may include the mold pad portion  24   a  and the insulating protrusion portion  24   b  described above. A length of the first portion  31 Mb 1  in the first direction X may be greater than a length of the second portion  31 Mb 2  in the first direction X. 
     The length of the first portion  31 Mb 1  in the first direction X may be substantially the same as a length of each of the first intermediate mold pads  31 MPa in the first direction X. A length of the second portion  31 Mb 2  in the first direction X may be less than a length of each of the first intermediate mold pads  31 MPa in the first direction X. 
     In an example embodiment, one or a plurality of the second intermediate mold pads  31 MPb may be disposed. When the plurality of second intermediate mold pads  31 MPb are disposed, each of the plurality of second intermediate mold pads  31 MPb may be disposed between one of the plurality of first intermediate mold pads  31 MPa and another of the plurality of first intermediate mold pads  31 MPa. When the plurality of second intermediate mold pads  31 MPb are disposed, each of the plurality of second intermediate mold pads  31 MPb may have the first portion  31 Mb 1  and the second portion  31 Mb 2 . 
     The plurality of second intermediate mold pads  31 MPb may be disposed in each of the first insulating region IA 1  and the second insulating region IA 2 . In  FIG. 2 , portion “CTa” overlapping the first insulating region IA 1  and the second insulating region IA 2  may refer to a central region of the second intermediate mold pad  31 MPb disposed between the first portion  31 Mb 1  and the second portion  31 Mb 2  of each of the plurality of second intermediate mold pads  31 MPb. At least the central region of the second intermediate mold pad  31 MPb may not include the insulating protrusion portion  24   b.    
     The central region of the second intermediate mold pad  31 MPb may include, and in some embodiments be filled with, the second capping insulating layer  43 . The second capping insulating layer  43  may include an insulating material different from an insulating material of the intermediate mold layers  31 M. For example, when the second capping insulating layer  43  is formed of a single material such as silicon oxide, or the like, a region between the first portion  31 Mb 1  and the second portion  31 Mb 2  of the second intermediate mold pad  31 MPb may be filled with the silicon oxide of the second capping insulating layer  43 . Differently from the above-described example embodiment, when the second capping insulating layer  43  is formed of at least two materials of a barrier insulating layer and a capping insulating layer, a region between the first portion  31 Mb 1  and the second portion  31 Mb 2  of the second intermediate mold pad  31 MPb may be filled with the barrier insulating layer of the second capping insulating layer  43 . The barrier insulating layer of the second capping insulating layer  43  may be formed of a material different from silicon nitride, such as aluminum oxide, or the like, for example, and the capping insulating layer of the second capping insulating layer  43  may be formed of silicon oxide. 
     Referring back to  FIG. 3 , the lower mold pads  29 MP of the lower mold layers  29 M may include first lower mold pads  29 MPa and a second lower mold pad  29 MPb. The second lower mold pad  29 MPb may be disposed between the first lower mold pads  29 MPa and the first intermediate mold pads  31 MPa. 
     A length of the second lower mold pad  29 MPb in the first direction X may be greater than a length of each of the first lower mold pads  29 MPa in the first direction X. The second lower mold pad  29 MPb may have a structure the same as or similar to a structure of the second intermediate mold pad  31 MPb and may be formed of a material the same as or similar to a material of the second intermediate mold pad  31 MPb. 
     In  FIG. 2 , portion “CTb” overlapping the first insulating region IA 1  and the second insulating region IA 2  may refer to a central region of each of the second lower mold pads  29 MPb. 
     In the description below, the intermediate gate pads  31 GP of the intermediate gate layers  31 G, arranged in the first direction X, will be described in greater detail with reference to  FIGS. 5 and 6 . 
     Referring to  FIGS. 5 and 6 , the intermediate gate layers  31 G may include the intermediate gate pads  31 GP each having an increased thickness. 
     The intermediate gate pads  31 GP may include first intermediate gate pads  31 GPa, and a second intermediate gate pad  31 GPb disposed between adjacent ones of the first intermediate gate pads  31 GPa. For example, the second intermediate gate pad  31 GPb may be disposed between one of the plurality of first intermediate gate pads  31 GPa and another of the plurality of first intermediate gate pads  31 GPa. 
     The second intermediate gate pad  31 GPb may have a structure different from a structure of each of the first intermediate gate pads  31 GPa. 
     In an example embodiment, each of the first intermediate gate pads  31 GPa may have a first length in the first direction X, and the second intermediate gate pad  31 GPb may have a second length in the first direction X, greater than the first length. 
     In an example embodiment, the second intermediate gate pad  31 GPb may include a first portion  31 GPb 1  and a second portion  31 GPb 2  spaced apart from each other in the first direction X. A length of the first portion  31 GPb 1  in the first direction X may be greater than a length of the second portion  31 GPb 2  in the first direction X. 
     A length of the first portion  31 GPb 1  in the first direction X may be substantially the same as a length of each of the first intermediate gate pads  31 GPa in the first direction X. A length of the second portion  31 GPb 2  in the first direction X may be less than a length of each of the first intermediate gate pads  31 GPa in the first direction X. 
     In an example embodiment, one or a plurality of the second intermediate gate pads  31 GPb may be disposed. When the plurality of second intermediate gate pads  31 GPb are disposed, each of the plurality of second intermediate gate pads  31 GPb may be disposed between one of the plurality of first intermediate gate pads  31 GPa and another one of the plurality of first intermediate gate pads  31 GPa. 
     Similarly to the second intermediate mold pad  31 MPb, a central region of the second intermediate mold pad  31 MPb may include and, in some embodiments be filled with, the second capping insulating layer  43 . For example, a central region between the first portion  31 GPb 1  and the second portion  31 GPb 2  of the second intermediate gate pad  31 GPb may include, and in some embodiments be filled with, the second capping insulating layer  43 . In  FIG. 2 , portion “CTa” overlapping the gate region GA may refer to a central region of each of the second intermediate gate pads  31 GPb. 
     The lower gate pads  29 GP of the lower gate layers  29 G may include first lower gate pads  29 GPa and a second lower gate pad  29 GPb. The second lower gate pad  29 GPb may be disposed between the first lower gate pads  29 GPa and the first intermediate gate pads  31 GPa. 
     A length of the second lower gate pad  29 GPb in the first direction X may be greater than a length of each of the first lower gate pads  29 GPa in the first direction X. The second lower gate pad  29 GPb may have a structure substantially the same as the structure of the second intermediate gate pad  31 GPb and may be formed of a material the same as or similar to a material of the second intermediate gate pad  31 GPb. In  FIG. 2 , portion “CTb” overlapping the gate region GA may refer to a central region of each of the second lower gate pads  29 GPb. 
     In the description below, the insulating region IA and the gate region GA will be described in greater detail with reference to  FIGS. 7, 8, 9, and 10 .  FIGS. 7 and 8  may illustrate a cross-sectional surface of a region between the first portion  31 Mb 1  and the second portion  31 Mb 2  of the second intermediate mold pad  31 MPb spaced apart from each other in the first direction X, illustrated in  FIG. 4 .  FIGS. 9 and 10  may illustrate a cross-sectional structure of a central region of one of the first intermediate mold pads  31 MPa in the second direction Y. 
     Referring to  FIGS. 7 and 8 , in the cross-sectional structure of a region between the first portion  31 Mb 1  (in  FIG. 4 ) and the second portion  31 Mb 2  (in  FIG. 4 ) in the second direction, an uppermost second layer of the second layers  23 , the second intermediate mold layer  31 M and the second intermediate gate layer  31 G, may not include a portion having an increased thickness. 
     In the cross-sectional structure of a region between the first portion  31 Mb 1  (in  FIG. 4 ) and the second portion  31 Mb 2  (in  FIG. 4 ) in the second direction, a width of the insulating region IA in the second direction Y may be determined by a width of the second intermediate mold layer  31 M in the second direction Y. 
     Referring to  FIGS. 9 and 10 , in the second stack region ST 2  (in  FIG. 2 ), the intermediate pads  31 GP and  31 MP may be disposed at a constant level. In the first stack region ST 1  (in  FIG. 2 ), the intermediate gate pads  31 GP of the intermediate pads  31 GP and  31 MP may be lowered to the first height in a direction towards the third stack region ST 3  (in  FIG. 2 ) from the second stack region ST 2 . In the third stack region ST 3  (in  FIG. 2 ), the intermediate pads  31 GP and  31 MP may be disposed at a constant level. 
     As described in the example embodiment with reference to  FIGS. 3 and 4 , each of the first intermediate mold pads  31 MPa may include the mold pad portion  24   a  and the insulating protrusion portion  24   b  on the mold pad portion  24   a.  A length of the insulating protrusion portion  24   b  in the second direction Y may be less than a length of the mold pad portion  24   a  in the second direction Y. 
     Each of first intermediate gate pads  31 GPa of the intermediate gate pads  31 GP adjacent to the first intermediate mold pads  31 MPa may include a gate extension portion  31 GPe extending from an upper region of a portion having an increased thickness to an upper surface of the mold pad portion  24   a  and adjacent to a side surface of the insulating protrusion portion  24   b.  The gate extension portion  31 GPe may be in contact with an upper surface of the mold pad portion  24   a  and may be in contact with a side surface of the insulating protrusion portion  24   b.  Accordingly, each of the first intermediate gate pads  31 GPa of the intermediate gate pads  31 GP adjacent to the first intermediate mold pads  31 MPa may include the gate extension portion  31 GPe overlapping an upper surface of the mold pad portion  24   a  of the adjacent first intermediate mold pad  31 MPa. A width of the insulating region IA in the second direction Y may be determined by a length of the insulating protrusion portion  24   b  in the second direction Y. A length of the insulating protrusion portion  24   b  in the second direction Y may be less than a length of each of the intermediate mold layers  31 M in the second direction Y. A length of the mold pad portion  24   a  in the second direction Y may be the same as a length of each of the intermediate mold layers  31 M in the second direction Y. 
     The insulating region IA may have a first length L 1  in the second direction Y in the cross-sectional structure of a region between the first portion  31 MPb 1  (in  FIG. 4 ) and the second portion  31 MPb 2  (in  FIG. 4 ) in the second direction Y as in the example embodiment illustrated in  FIGS. 7 and 8 . The insulating region IA may also have a second length L 2  in the second direction Y in a cross-sectional structure of the central region of one of the first intermediate mold pads  31 MPa in the second direction Y as in the example embodiment illustrated in  FIGS. 9 and 10 . The first length L 1  may be greater than the second length L 2 . 
     In the description below, the gate layers  29 G,  31 G,  33 G, and  35 G, the memory cell vertical structure  46 , and the separation structures  69   a,    69   b,  and  69   c  will be described in greater detail with reference to  FIGS. 11 and 12 . 
     Referring to  FIGS. 11 and 12 , each of the gate layers  29 G,  31 G,  33 G, and  35 G may include a first gate layer  27   a  and a second gate layer  27   b.  The first gate layer  27   a  may cover a lower surface and an upper surface of the second gate layer  27   b  and may extend to a region between the second gate layer  27   b  and the memory cell vertical structure  46 . 
     In an example embodiment, the first gate layer  27   a  may include a first conductive material (e.g., tungsten (W), or the like), and the second gate layer  27   b  may include a second conductive material (e.g., titanium nitride (TiN), tungsten nitride (WN), or the like) different from the first conductive material. 
     In another example embodiment, the first gate layer  27   a  may include a dielectric material, and the second gate layer  27   b  may include a conductive material (e.g., TiN, W, or the like). A dielectric material of the first gate layer  27   a  may include a high-k dielectric such as aluminum oxide (AlO). 
     The memory cell vertical structure  46  may include a dielectric structure  48 , a channel layer  57 , a core layer  60 , and a pad layer  63 . The channel layer  57  may be disposed on a side surface of the core layer  60 , the pad layer  63  may be disposed on the core layer  60 , and the dielectric structure  48  may be disposed on an external side surface of the channel layer  57 . 
     The dielectric structure  48  may include a first dielectric layer  50 , a second dielectric layer  54 , and a data storage layer  52  disposed between the first dielectric layer  50  and the second dielectric layer  54 . The second dielectric layer  54  may be disposed between the channel layer  57  and the data storage layer  52 . 
     The bit line contact plugs  78  may be in contact with the pad layer  63 . 
     In an example embodiment, the intermediate gate layers  31 G may include word lines. Regions of the data storage layer  52  opposing the intermediate gate layers  31 G which may be configured as word lines may be configured as data storage regions which may store data in a flash memory device. 
     In an example embodiment, at least the one lower gate layer  29 G or at least one of the plurality of lower gate layers  29 G may be configured as a lower selection gate electrode, and at least one of the plurality of upper gate layers  33 G may be configured as an upper selection gate electrode. 
     In another example embodiment, when a plurality of the lower gate layers  29 G are provided, one of the plurality of lower gate layers  29 G may be configured as a lower selection gate electrode, and the other may be configured as a lower erasing gate electrode used in an erasing operation of a flash memory device. One of the plurality of upper gate layers  33 G may be configured as an upper selection gate electrode, and the other may be configured as an upper erasing gate electrode used in an erasing operation of a flash memory device. 
     In an example embodiment, each of the first to third separation structures  69   a,    69   b,  and  69   c  may include a separation spacer  70   a  and a separation core pattern  70   b.  The separation core pattern  70   b  may be formed of an insulating material, and the separation core pattern  70   b  may be formed of a conductive material. 
     In another example embodiment, each of the first to third separation structures  69   a,    69   b,  and  69   c  may be formed of an insulating material, silicon oxide, for example. 
     In the description below, a modified example of the second intermediate mold pad  31 MPb (in  FIG. 4 ) illustrated in  FIG. 4  will be described with reference to  FIG. 13A .  FIG. 13A  is an enlarged diagram illustrating a modified example of the second intermediate mold pad  31 MPb (in  FIG. 4 ) illustrated in  FIG. 4 . 
     In the modified example, referring to  FIG. 13A , a second intermediate mold pad  31 MPb′ may include a mold pad portion  24   a′,  and a first insulating protrusion portion  24   b   1  and a second insulating protrusion portion  24   b   2  disposed on the mold pad portion  24   a′  and spaced apart from each other. The first insulating protrusion portion  24   b   1  and the second insulating protrusion portion  24   b   2  may be spaced apart from a memory cell array region MA in order. A length of the first insulating protrusion portion  24   b   1  in the first direction X may be greater than a length of the second insulating protrusion portion  24   b   2  in the first direction X. 
     In the description below, a modified example of the second intermediate gate pad  31 GPb (in  FIG. 6 ) illustrated in  FIG. 6  will be described with reference to  FIG. 13B .  FIG. 13B  is an enlarged diagram illustrating a modified example of the second intermediate gate pad  31 GPb (in  FIG. 6 ) illustrated in  FIG. 6 . 
     In the modified example, referring to  FIG. 13B , a second intermediate gate pad  31 GPb′ may include a first portion  31 GPb 1 ′ and a second portion  31 GPb 2 ′ arranged in order in the first direction X and each having an increased thickness, and a third portion  31 GPb 3 ′ connecting the first portion  31 GPb 1 ′ to the second portion  31 GPb 2 ′. A thickness (e.g., in a vertical Z direction) of the third portion  31 GPb 3 ′ may be less than a thickness of each of the first portion  31 GPb 1 ′ and the second portion  31 GPb 2 ′. The third portion  31 GPb 3 ′ may be a central region of the second intermediate gate pad  31 GPb′. The central region  31 GPb 3 ′ of the second intermediate gate pad  31 GPb′ may include a conductive material layer. The first portion  31 GPb 1 ′, the second portion  31 GPb 2 ′, and the central region  31 GPb 3 ′ may include the conductive material layer. 
     In the description below, a modified example of the second intermediate mold pad  31 MPb (in  FIG. 4 ) illustrated in  FIG. 4  will be described with reference to  FIG. 14 .  FIG. 14  is an enlarged diagram illustrating a modified example of the second intermediate mold pad  31 MPb (in  FIG. 4 ) illustrated in  FIG. 4 . 
     In the example embodiment, referring to  FIG. 14 , a second intermediate mold pad  31 Mb″ may include a mold pad portion  24   a″  and a first insulating protrusion portion  24   b   1 ′ and a second insulating protrusion portion  24   b   2 ′ disposed on the mold pad portion  24   a″  and spaced apart from each other. A length of each of the first insulating protrusion portion  24   b   1 ′ and the second insulating protrusion portion  24   b   2 ′ in the first direction X may be less than a length of each of first intermediate mold pads  31 MPa in the first direction X. 
     In the description below, a modified example of the second intermediate gate pad  31 GPb (in  FIG. 6 ) illustrated in  FIG. 6  will be described.  FIG. 15  is an enlarged diagram illustrating a modified example of the second intermediate gate pad  31 GPb (in  FIG. 6 ) illustrated in  FIG. 6 . 
     In the modified example, referring to  FIG. 15 , a second intermediate gate pad  31 GPb″ may have a thickness substantially the same as a thickness of each of first intermediate gate pads  31 GPa, and may have a length in the first direction X greater than a length of each of the first intermediate gate pads  31 GPa in the first direction X. 
     In the description below, a modified example of the second intermediate mold pad  31 MPb (in  FIG. 4 ) will be described with reference to  FIG. 16 .  FIG. 16  is an enlarged diagram illustrating another modified example of the second intermediate mold pad  31 MPb illustrated in  FIG. 4 . 
     In the modified example, referring to  FIG. 16 , a second intermediate mold pad  31 MPbb may include a first portion  31 MPb 1 ′ and a second portion  31 MPb 2 ′ spaced apart from each other in the first direction X. Each of the first portion  31 MPb 1 ′ and the second portion  31 MPb 2 ′ may include the mold pad portion  24   a  ( FIG. 4 ) and the insulating protrusion portion  24   b  ( FIG. 4 ) described in the aforementioned example embodiment. 
     A length of each of the first portion  31 MPb 1 ′ and the second portion  31 MPb 2 ′ in the first direction X may be less than a length of each of the first intermediate mold pads  31 MPa in the first direction X. 
     In the description below, modified examples of the first intermediate mold pads  31 MPa (in  FIG. 4 ) and the second intermediate mold pad  31 MPb (in  FIG. 4 ) will be described with reference to  FIGS. 17 and 18 .  FIGS. 17 and 18  are enlarged diagrams illustrating modified examples of the first intermediate mold pads  31 MPa (in  FIG. 4 ) and the second intermediate mold pad  31 MPb (in  FIG. 4 ). 
     In the modified examples, referring to  FIG. 17 , a second intermediate mold pad  31 MPbb′ may not have an increased thickness. Each of partial first intermediate mold pads  31 MPa 1  of first intermediate mold pads  31 MPaa adjacent to the second intermediate mold pad  31 MPbb′ may not have an increased thickness, and each of the other first intermediate mold pads  31 MPa 2  may have an increased thickness. For example, the first intermediate mold pads  31 MPa 2  of the first intermediate mold pads  31 MPaa, each of which has an increased thickness, may include the mold pad portion  24   a  and the insulating protrusion portion  24   b  described in the aforementioned example embodiment, and the first intermediate mold pads  31 MPa 1  of the first intermediate mold pads  31 MPaa, each of which does not have an increased thickness, may only include the mold pad portion  24   a  and may not include the insulating protrusion portion  24   b.    
     In the modified examples, referring to  FIG. 18 , a second intermediate mold pad  31 MPbb″ may not have an increased thickness, each of partial first intermediate mold pads  31 MPa 1 ′ of the first intermediate mold pads  31 MPaa′ adjacent to the second intermediate mold pad  31 MPbb″ may not have an increased thickness, and each of the other first intermediate mold pads  31 MPa 2 ′ may have an increased thickness. 
     The first intermediate mold pads  31 MPa 1 ′, each of which does not have an increased thickness, may be referred to as first thin intermediate mold pads, and the first intermediate mold pads  31 MPa 2 ′, each of which has an increased thickness, may be referred to as first thick intermediate mold pads. 
     A difference in height between the first thin intermediate mold pad  31 MPa 1 ′ of the first intermediate mold pads  31 MPaa′ disposed at a level higher than a level of the second intermediate mold pad  31 MPbb″, adjacent to the second intermediate mold pad  31 MPbb″, and the second intermediate mold pad  31 MPbb″ may be less than a difference in height between the first thin intermediate mold pad  31 MPa 1 ′ and the first thick intermediate mold pad  31 MPa 2 ′. 
     A difference in height between the first thin intermediate mold pad  31 MPa 1 ′ of the first intermediate mold pads  31 MPaa′ disposed at a level lower than a level of the second intermediate mold pad  31 MPbb″, adjacent to the second intermediate mold pad  31 MPbb″, and the second intermediate mold pad  31 MPbb″ may be greater than a difference in height between the first thin intermediate mold pad  31 MPa 1 ′ and the first thick intermediate mold pad  31 MPa 2 ′. 
     In some aforementioned example embodiments, each of some of the plurality of intermediate mold pads  31 MP may include the mold pad portion  24   a  and the insulating protrusion portion  24   b  on the mold pad portion  24   a,  each of at least some of a plurality of first intermediate mold pads  31 MPa may include the mold pad portion  24   a  and the insulating protrusion portion  24   b.    
     In some aforementioned example embodiments, at least a central region of the second intermediate mold pad  31 MPb may not include the insulating protrusion portion  24   b.  or example, as illustrated in  FIG. 4 , the central region of the second intermediate mold pad  31 MPb may include, and in some embodiments be filled with, the second capping insulating layer  43 . 
     In some example embodiments, a first intermediate mold pad of the plurality of first intermediate mold pads  31 MIPa, including the mold pad portion  24   a  and the insulating protrusion portion  24   b,  may have a first thickness, and in some example embodiments, a central region of the second intermediate mold pad may have a second thickness less than the first thickness. For example, as illustrated in  FIG. 13A , the central region of the second intermediate mold pad  31 MPb′ (in  FIG. 13A ) may include an insulating material layer having the second thickness less than the first thickness. The insulating material layer of the central region of the second intermediate mold pad  31 MPb′ (in  FIG. 13A ) may be a portion of the mold pad portion  24   a.    
     In example embodiments, by providing the stack structure ST including the gate region GA and the insulating region IA, integration density of the semiconductor device may improve. 
     In the description below, a modified example of a semiconductor device la will be described with reference to  FIGS. 19 to 20C . With regard to  FIGS. 19 to 20C ,  FIG. 19  is a plan diagram illustrating a modified example of a semiconductor device.  FIG. 20A  is a cross-sectional diagram illustrating a region taken along line VI-VI′ in  FIG. 19 .  FIG. 20B  is a cross-sectional diagram illustrating a region taken along line VII-VII′ in  FIG. 19 .  FIG. 20C  is a cross-sectional diagram illustrating regions taken along lines VIII-VIII′ and IX-IX′. 
     Referring to  FIGS. 19 to 20C , a lower structure  3  substantially the same as in the aforementioned example embodiment may be disposed. The lower structure  3  may include a lower substrate  5 , an upper substrate  12  on the lower substrate  5 , a peripheral circuit region  7  between the lower substrate  5  and the upper substrate  12 , a gap-fill insulating layer  13  penetrating the lower substrate  5 , and an intermediate insulating layer  14  on, and in some embodiments surrounding, a side surface of the lower substrate  5 . 
     A stack structure ST′ may be disposed on the lower structure  3 . The stack structure ST′ may be disposed in a memory cell array region MA and a connection region EA on the lower structure  3 . The stack structure ST′ may include a gate region GA′ and an insulating region IA′ which does not include a conductive material. 
     The gate region GA′ may be disposed in the memory cell array region MA and may be disposed in a portion of the connection region EA. 
     The stack structure ST′ may include first layers  120  and second layers  123  alternately stacked on the lower structure  3 . The first layers  120  may be disposed in the gate region GA′ and the insulating region IA′. The first layers  120  may be configured as interlayer insulating layers. 
     A first capping insulating layer  140  and a second capping insulating layer  143  may be disposed on the stack structure ST′. The first capping insulating layer  140  may be on, and in some embodiments cover, an uppermost second layer of the second layers  123 . The second capping insulating layer  143  may have an upper surface coplanar with an upper surface of the first capping insulating layer  140 , and may be on, and in some embodiments cover, a remaining portion of the stack structure ST′. 
     A plurality of separation structures  169   a,    169   b,  and  169   c  penetrating the stack structure ST′ may be disposed on the lower structure  3 . The plurality of separation structures  169   a,    169   b,  and  169   c  may include first separation structures  169   a  crossing the memory cell array region MA and the connection region EA, a second separation structure  169   b  crossing the memory cell array region MA and extending into a portion of the connection region EA, and a third separation structure  169   c  disposed in a portion of the connection region EA. 
     Each of the first separation structures  169   a  may include a pair of first portions  169   a   1  crossing the memory cell array region MA and extending into a portion of the connection region EA, and a second portion  169   a   2  connected to the pair of first portions  169   a   1  and extending in the first direction X in the connection region EA. 
     The third separation structure  169   c  may be disposed between the second portions  169   a   2  of the first separation structures  169   a.  The second separation structures  169   b  may be disposed between the first portions  169   a   1  of the first separation structures  169   a.    
     A distance between a side surface of the third separation structure  169   c  and a side surface of the second portion  169   a   2  of each of the first separation structures  169   a  adjacent to the third separation structure  169   c  may be greater than a distance between side surfaces of the second separation structure  169   b  adjacent to each other. A distance between a side surface of the third separation structure  169   c  and a side surface of the second portion  169   a   2  of each of the first separation structures  169   a  adjacent to the third separation structure  169   c  may be greater than a distance between a side surface of the second separation structure  169   b  and a side surface of the first portion  169   a   1  of the first separation structure  169   a,  adjacent to each other. 
     The second layers  123  may include gate layers  129 G,  131 G,  133 G, and  135 G disposed in the gate region GA′ and mold layers  129 M,  131 M, and  135 M disposed in the insulating region IA′. Accordingly, respective ones of the lower and intermediate gate layers  129 G and  131 G and respective ones of the lower and intermediate mold layers  129 M and  131 M disposed at the same level in a boundary region between the gate region GA′ and the insulating region IA′ may oppose each other (e.g., respective ends of the lower and intermediate mold layers  129 M and  131 M may face respective ends of the lower and intermediate gate layers  129 G and  131 G). 
     In an example embodiment, the mold layers  129 M,  131 M, and  135 M may be formed of a material the same as a material of the mold layers  29 M,  31 M, and  35 M illustrated in  FIGS. 1 to 12 . 
     In an example embodiment, each of the gate layers  129 G,  131 G,  133 G, and  135 G may include a conductive material. For example, each of the gate layers  129 G,  131 G,  133 G, and  135 G may be configured as a gate electrode. 
     The gate layers  129 G,  131 G,  133 G, and  135 G may include one or a plurality of lower gate layers  129 G, a plurality of intermediate gate layers  131 G on the one or the plurality of lower gate layers  129 G, a plurality of upper gate layers  133 G on the plurality of intermediate gate layers  131 G, and a floating gate layer  135 G on the plurality of intermediate gate layers  131 G. 
     The mold layers  129 M,  131 M, and  135 M may include one or a plurality of lower mold layers  129 M, a plurality of intermediate mold layers  131 M on the one or the plurality of lower mold layers  129 M, and a floating mold layer  135 M on the plurality of intermediate mold layers  131 M. 
     The gate layers  129 G,  131 G,  133 G, and  135 G may include a plurality of gate pads arranged in staircase structure, and the mold layers  129 M,  131 M, and  135 M may include a plurality of mold pads arranged in staircase structure. For example, the one or the plurality of lower gate layers  129 G may include one or a plurality of lower gate pads  129 GP, the plurality of intermediate gate layers  131 G may include intermediate gate pads  131 GP, and the plurality of upper gate layers  133 G may include upper gate pads  133 GP. The one or the plurality of lower mold layers  129 M may include one or a plurality of lower mold pads  129 MP, and the intermediate mold layers  131 M may include intermediate mold pads  131 MP. 
     At least one of the lower, intermediate, and upper gate pads  129 GP,  131 GP, and  133 GP may have a thickness greater than a thickness of each of the gate layers  129 G,  131 G, and  133 G. A thickness of each of the gate layers  129 G,  131 G, and  133 G may refer to a thickness of a region of each of the gate layers  129 G,  131 G, and  133 G in which the lower, intermediate, and upper gate pads  129 GP,  131 GP, and  133 GP are not disposed. 
     At least one of the lower and intermediate mold pads  129 MP and  131 MP may have a thickness greater than a thickness of each of the gate layers  129 G,  131 G, and  133 G. 
     In some embodiments, at least one of the lower and intermediate mold pads  129 MP and  131 MIP may have a thickness greater than a thickness of each of the mold layers  129 M and  133 M. A thickness of each of the mold layers  129 M and  133 M may refer to a thickness of a region of each of the mold layers  129 M and  133 M in which the lower and intermediate mold pads  129 MP and  133 MP are not disposed. 
     The intermediate gate pads  131 GP may include first intermediate gate pads  131 GPa formed of a material the same as a material of the first intermediate gate pads  31 GPa (in  FIG. 6 ) illustrated in  FIG. 6  and having a structure the same as a structure of each of the first intermediate gate pads  31 GPa, and may include a second intermediate gate pad  131 GPb formed of a material the same as a material of the second intermediate gate pad  31 GPb (in  FIG. 6 ) illustrated in  FIG. 6  and having a structure the same as a structure of the second intermediate gate pad  31 GPb. The second intermediate gate pad  131 GPb may include a first portion  131 GPb 1  and a second portion  131 GPb 2  spaced apart from each other as in the example embodiment illustrated in  FIG. 6 , and a central region of the second intermediate gate pad  131 GPb between the first portion  131 GPb 1  and the second portion  131 GPb 2  may be filled with the second capping insulating layer  143 . 
     The lower gate pads  129 GP may include first lower gate pads  129 GPa formed of a material the same as a material of the first lower gate pads  29 GPa (in  FIG. 5 ) illustrated in  FIG. 5  and having a structure the same as a structure of each of the first lower gate pads  29 GPa, and may include a second lower gate pad  129 GPb formed of a material the same as a material of the second lower gate pad  29 GPb (in  FIG. 5 ) illustrated in  FIG. 5  and having a structure the same as a structure of the second lower gate pad  29 GPb. The second lower gate pad  129 GPb may include a first portion  129 GPb 1  and a second portion  129 GPb 2  spaced apart from each other as in the example embodiment illustrated in  FIG. 5 , and a central region of the second lower gate pad  129 GPb between the first portion  129 GPb 1  and the second portion  129 GPb 2  may be filled with the second capping insulating layer  143 . 
     The intermediate mold pads  131 MP may include first intermediate mold pads  131 MPa formed of a material the same as a material of the first intermediate mold pads  31 MPa (in  FIG. 4 ) illustrated in  FIG. 4  and having a structure the same as a structure of each of the first intermediate mold pads  31 MPa, and may include a second intermediate mold pad  131 MPb formed of a material the same as a material of the second intermediate mold pad  31 MPb (in  FIG. 4 ) illustrated in  FIG. 4  and having a structure the same as a structure of the second intermediate mold pad  31 MPb. For example, each of the first intermediate mold pads  131 MPa may include a mold pad portion  124   a  and an insulating protrusion portion  124   b  on the mold pad portion  124   a.  The second intermediate mold pad  131 MPb may include a first portion  131 MPb 1  and a second portion  131 MPb 2  spaced apart from each other as in the example embodiment illustrated in  FIG. 4 . A central region of the second intermediate mold pad  131 MPb may not include the insulating protrusion portion  124   b.  For example, the central region of the second intermediate mold pad  131 MPb between the first portion  131 MPb 1  and the second portion  131 MPb 2  may be filled with the second capping insulating layer  143 . 
     The lower mold pads  129 MP may include a first lower mold pads  129 MPa and a second lower mold pad  129 MPb. The second lower mold pad  129 MPb may be adjacent to the intermediate mold pads  131 MP, and may include a first portion  129 MPb 1  and a second portion  129 MPb 2  spaced apart from each other. A central region of the second lower mold pad  129 MPb may not include the insulating protrusion portion  124   b.  For example, the central region of the second lower mold pad  129 MPb between the first portion  129 MPb 1  and the second portion  129 MPb 2  may be filled with the second capping insulating layer  143 . 
     In  FIG. 19 , a reference numeral “CT” may refer to a central region of the second intermediate mold pad  131 MPb, a central region of the second intermediate gate pad  131 GPb, a central region of the second lower mold pad  129 MPb, and a central region of the second lower gate pad  129 GPb. 
     A first upper insulating layer  166  and a second upper insulating layer  172  stacked in order on the first capping insulating layer  140  and the second capping insulating layer  143  may be disposed. The first to third separation structures  169   a,    169   b,  and  169   c  may penetrate the stack structure ST′, may extend upwardly, and may penetrate the first and second capping insulating layers  140  and  143  and the first upper insulating layer  166 . 
     Bit line contact plugs  178  penetrating the first upper insulating layer  166  and the second upper insulating layer  172  and electrically connected to the memory cell vertical structure  146  may be disposed. 
     In the connection region EA, gate contact structures  175  penetrating the first upper insulating layer  166  and a second upper insulating layer  172 , extending downwardly, and electrically connected to the lower, intermediate, and upper gate pads  129 GP,  131 GP, and  133 GP may be disposed. 
     Peripheral contact structures  181  in contact with peripheral pad portions  8 P of the peripheral wirings  8 , extending upwardly, and penetrating the gap-fill insulating layer  113  and the insulating region IA′ of the stack structure ST′ may be disposed. 
     Gate connection wirings  185  may be disposed on the gate contact structures  175  and the peripheral contact structures  181 . 
     Bit lines  184  may be disposed on the bit line contact plugs  178 . 
     In the description below, an example of a method of manufacturing a semiconductor device will be described with reference to  FIGS. 21, and 22A to 23B .  FIG. 21  is a flowchart illustrating a method of manufacturing a semiconductor device according to an example embodiment of the present inventive concepts.  FIGS. 22A to 23B  are cross-sectional diagrams illustrating an example of a method of manufacturing a semiconductor device according to an example embodiment of the present inventive concepts.  FIGS. 22A and 23A  are cross-sectional diagrams illustrating a region taken along line VII-VII′ in  FIG. 19 , and  FIGS. 22B and 23B  are cross-sectional diagrams illustrating regions taken along lines VIII-VIII′ and IX-IX′ in  FIG. 19 . 
     Referring to  FIGS. 19, 21, 22A, and 22B , a mold structure  119  including insulating layers  120  and mold layers  121  may be formed on a lower structure  3  (S 10 ). The insulating layers  120  may be formed of silicon oxide, and the mold layers  121  may be formed of silicon nitride. The insulating layers  120  and the mold layers  121  may be alternately stacked. 
     The lower structure  3  may include a lower substrate  5 , an upper substrate  12  on the lower substrate  5 , a peripheral circuit region  7  between the lower substrate  5  and the upper substrate  12 , a gap-fill insulating layer  13  penetrating the lower substrate  5 , an intermediate insulating layer  14  an, and in some embodiments surrounding, a side surface of the lower substrate  5 . 
     The mold structure  119  may be formed in a memory cell array region MA and a connection region EA on the lower structure  3 . 
     In the connection region EA, a staircase structure exposing the mold layers  121  may be formed (S 20 ). For example, a staircase structure may be formed by patterning the insulating layers  120  and the mold layers  121 , and the mold layers  121  may be exposed by the staircase structure. Forms of the staircase structure may not be limited to the example illustrated in the diagrams, and may be varied. For example, the staircase structure may be configured as the staircase structure of the stack structure ST illustrated in  FIGS. 1 to 12 . 
     In the connection region EA, pad regions  121 P each having an increased thickness may be formed by forming additional mold layers  124   b  on the exposed mold layers  121  (S 30 ). 
     By performing a photolithography process and an etching process, portions of the pad regions  121 P may be etched (S 40 ). 
     In an example embodiment, each of the etched partial pad regions may have a length in the first direction X, greater than a length of each of the other pad regions in the first direction X. The etched partial pad regions may be divided into a first portion  121 P 1  and a second portion  121 P 2 . 
     In an example embodiment, the etching the portions of the pad regions  121 P may include removing the additional mold layer and the mold layer of the etched pad region. 
     In another example embodiment, the etching the portions of the pad regions  121 P may include removing only the additional mold layer and leaving the mold layer of the etched pad region. 
     Capping insulating layers  140  and  143  on, and in some embodiments covering, the mold structure  119  may be formed. The capping insulating layers  140  and  143  may include a first capping insulating layer  140  formed before forming the staircase structure, and a second capping insulating layer  143  formed after forming the staircase structure. A memory cell vertical structure  146  penetrating the first capping insulating layer  140  and the mold structure  119  may be formed. The memory cell vertical structure  146  may have a structure the same as a structure of the memory cell vertical structure  46  (in  FIG. 12 ) illustrated in  FIG. 12 . 
     Referring to  FIGS. 20A to 20C  along with  FIGS. 19, 21, 23A and 23B , an insulating layer  166  may be formed (S 50 ). For example, a first upper insulating layer  166  may be formed on the first and second capping insulating layers  140  and  143 . Separation trenches  165  penetrating the first upper insulating layer  166 , the first and second capping insulating layers  140  and  143 , and the mold structure  119  (in  FIG. 22A ) in order may be formed. 
     Portions of the mold layers  121  and portions of the additional mold layers  124   b  may be replaced with the gate layers  129 G,  131 G,  133 G, and  135 G (in  FIGS. 20A to 20C ) (S 60 ). 
     The replacing portions of the mold layers  121  and portions of the additional mold layers  124   b  with the gate layers  129 G,  131 G,  133 G, and  135 G (in  FIGS. 20A to 20C ) may include forming empty spaces  167  by partially etching the mold layers  121  and the additional mold layers  124   b,  exposed by the separation trenches  165 , and forming the gate layers  129 G,  131 G,  133 G, and  135 G (in  FIGS. 20A to 20C ) in the empty spaces  167 . 
     The remaining mold layers  121  (in  FIGS. 23A and 23B ) and the remaining first upper insulating layer  166  may be included in the mold layers  129 M,  131 M, and  135 M described in the aforementioned example embodiment with reference to  FIGS. 20A and 20B . 
     Referring to  FIGS. 19 and 20A to 20C , separation structures  169   a,    169   b,  and  169   c  (in  FIG. 20C ) filling the separation trenches  165  (in  FIG. 23B ) may be formed. A second upper insulating layer  172  may be formed on the first upper insulating layer  166 . 
     Bit line contact plugs  178  penetrating the first and second upper insulating layers  166  and  172  and electrically connected to the memory cell vertical structure  146  may be formed. 
     Gate contact structures  175  penetrating the first and second upper insulating layers  166  and  172 , extending downwardly, and electrically connected to the gate pads  129 GP,  131 GP, and  133 GP of the gate layers  129 G,  131 G,  133 G, and  135 G (in  FIGS. 20A to 20C ) may be formed. 
     The peripheral contact structures  181  penetrating the insulating region IA′ (in  FIG. 19 ) including the mold layers  129 M,  131 M, and  135 M and electrically connected to peripheral pad portions  8 P of peripheral wirings  8  of the peripheral circuit region  7  of the lower structure  3  may be formed. 
     A bit line  184  may be formed on the bit line contact plug  178 . 
     Gate connection wirings  185  may be formed on the gate contact structures  175  and the peripheral contact structures  181 . 
     According to the aforementioned example embodiments, by providing the stack structure including the gate region and the insulating region on the lower structure including the peripheral circuit region, integration density of the semiconductor may improve. 
     While the example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concepts as defined by the appended claims.