Patent Publication Number: US-2013241638-A1

Title: Signal amplifier circuit for usb port

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application related in a co-pending U.S. patent application entitled “SIGNAL AMPLIFIER CIRCUIT FOR USB PORT,” Attorney Docket Number US43306, simultaneously filed with the present application. 
    
    
     BACKGROUND 
     1. Technical Field 
     The present disclosure relates to a signal amplifier circuit for USB ports. 
     2. Description of Related Art 
     Universal serial bus (USB) technology is broadly applied as a solution to serial communications. The USB 3.0 specification was published on 12 Nov. 2008. The USB 3.0 specification&#39;s main goals were to increase the data transfer rate (up to 5 Gbit/s), to decrease power consumption, to increase power output, and to be backwards-compatible with USB 2.0. USB 3.0 includes a new, higher speed bus called super speed connected in parallel with the USB 2.0 bus. The signals usually tend to attenuate in USB 3.0 during transmission for a long distance on printed circuit boards. Therefore, the quality of the signals is affected. 
     Therefore there is a need for improvement in the art. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
         FIG. 1  is a block diagram of an embodiment of a signal amplifier circuit for USB port. 
         FIG. 2  is a circuit diagram of the signal amplifier circuit of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.” 
       FIG. 1  illustrates a block diagram of a signal amplifier circuit for USB ports in accordance with one embodiment. The signal amplifier circuit includes a USB controller  100 , an amplifier circuit  200 , a signal regulator circuit  300 , and a USB port  400 . The amplifier circuit  200  amplifies differential signals transmitted between the USB controller  100  and the USB port  300 . The signal regulator circuit  300  regulates amplitude and jitter of differential signals amplified by the amplifier circuit  200 . In one embodiment, the USB port  300  is a USB 3.0 port. 
       FIG. 2  illustrates a circuit diagram of the signal amplifier circuit in accordance with one embodiment. The USB controller  100  includes a super speed transmitter differential pair SSTX+, SSTX−, a super speed receiver differential pair SSRX+, SSRX−, and two first differential signal receiving and transmitting terminals D+, D−. The amplifier circuit  200  includes two first input terminals RX 1 +, RX 1 −, two second input terminals RX 2 +, RX 2 −, two first output terminals TX 1 +, TX 1 −, two second output terminals TX 2 +, TX 2 −, a de-emphasis regulating terminal DE, an equalization regulating terminal EQ, an amplitude regulating terminal OS, an enable terminal EN, and an operation terminal CM. 
     The signal regulator circuit  300  includes a first signal regulating unit, a second signal regulating unit, and a third signal regulating unit. The first signal regulating unit includes switches K 1 , K 2  and resistor R 1 . The de-emphasis regulating terminal DE is electrically connected to a DC voltage via the switch K 1  and the resistor R 1  connected in series. The de-emphasis regulating terminal DE is grounded via the switch K 2 . The second signal regulating unit includes switches K 3 , K 4  and resistor R 2 . The equalization regulating terminal EQ is electrically connected to the DC voltage via the switch K 3  and the resistor R 2  connected in series. The equalization regulating terminal EQ is grounded via the switch K 4 . The third signal regulating unit includes switches K 5 , K 6  and resistor R 3 . The amplitude regulating terminal OS is electrically connected to the DC voltage via the switch K 5  and the resistor R 3  connected in series. The amplitude regulating terminal OS is grounded via the switch K 6 . The enable terminal EN is electrically connected to the DC voltage via a resistor R 4 . The operation terminal CM is grounded. In one embodiment, the DC voltage is +3.3V. 
     The USB port  400  includes two first differential signal receiving terminals  401 ,  402 , two first differential signal transmitting terminals  403 ,  404 , and two second differential signal receiving and transmitting terminals  405 ,  406 . The super speed transmitter differential pair SSTX+, SSTX− is electrically connected to the first input terminals RX 1 −, RX 1 +. The super speed receiver differential pair SSRX+, SSRX− is electrically connected to the second output terminals TX 2 −, TX 2 +. The first output terminals TX 1 −, TX 1 + are electrically connected to the first differential signal receiving terminals  401 ,  402 . The second input terminals RX 2 −, RX 2 + are electrically connected to the first differential signal transmitting terminals  403 ,  404 . The first differential signal receiving and transmitting terminals D+, D− are electrically connected to the second differential signal receiving and transmitting terminals  405 ,  406 . 
     The amplifier circuit  200  includes a first amplifier U 1  and a second amplifier U 2 . The first amplifier U 1  is electrically connected to the first input terminals RX 1 −, RX 1 + and the first output terminals TX 1 −, TX 1 +. The second amplifier U 2  is electrically connected to the second input terminals RX 2 −, RX 2 + and the second output terminals TX 2 −, TX 2 +. In one embodiment, the first differential signal receiving and transmitting terminals D+, D− and the second differential signal receiving and transmitting terminals  405 ,  406  support the USB 2.0 specification. The super speed transmitter differential pair SSTX+, SSTX− and the super speed receiver differential pair SSRX+, SSRX− support the USB 3.0 specification. 
     In application, the data of USB 3.0 specification stored in the USB controller  100  is transmitted to the first amplifier U 1  from the super speed transmitter differential pair SSTX+, SSTX− to the first input terminals RX 1 −, RX 1 +. The data of USB 3.0 is amplified by the first amplifier U 1  and is then transmitted to the USB port  400  from the first output terminals TX 1 −, TX 1 + to the first differential signal receiving terminals  401 ,  402 . The data of USB 3.0 specification from the USB port  400  is transmitted to the second amplifier U 2  via the second input terminals RX 2 −, RX 2 +. The data of USB 3.0 is amplified by the second amplifier U 2  and is then transmitted to the USB controller  100  from the second output terminals TX 2 −, TX 2 + to the super speed receiver differential pair SSRX+, SSRX−. The data of USB 2.0 specification stored in the USB controller  100  is transmitted to the USB port  400  from the first differential signal receiving and transmitting terminals D+, D− to the second differential signal receiving and transmitting terminals  405 ,  406 . The data of USB 2.0 specification from the USB port  400  is transmitted to the USB controller  100  via the second differential signal receiving and transmitting terminals  405 ,  406  to the first differential signal receiving and transmitting terminals D+, D−. 
     In one embodiment, when the switches K 1 , K 3 , and K 5  are closed, the amplifier circuit  200  receives a high voltage level regulating signal via the de-emphasis regulating terminal DE, the equalization regulating terminal EQ, and the amplitude regulating terminal OS. When the switches K 2 , K 4 , and K 6  are closed, the amplifier circuit  200  receives a low voltage level regulating signal via the de-emphasis regulating terminal DE, the equalization regulating terminal EQ, and the amplitude regulating terminal OS. The amplifier circuit  200  regulates the amplified differential signals according to the high voltage level and low voltage level regulating signals. 
     Even though numerous characteristics and advantages of the present disclosure have been set forth in the foregoing description, together with details of the structure and function of the disclosure, the disclosure is illustrative only, and changes may be made in detail, especially in the matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.