Patent Publication Number: US-2011068397-A1

Title: Power devices and associated methods of manufacturing

Description:
TECHNICAL FIELD 
     The current technology is related generally to power devices and associated methods of manufacturing. In particular, the current technology is related generally to vertical metal-oxide field effect transistors (MOSFET) and associated methods of manufacturing. 
     BACKGROUND 
     Vertical MOSFET generally have superior power switching performance when compared to conventional bipolar devices. However, the on-state resistance of power MOSFET increases sharply as breakdown voltage increases. As a result, vertical MOSFET may be unusable in high voltage applications. 
     One solution for achieving lower on-state resistance while maintaining reasonable breakdown voltage is by utilizing “super junctions.”  FIG. 1  schematically illustrates a conventional n-type vertical MOSFET  10  with super junctions. As shown in  FIG. 1 , the MOSFET  10  includes a drain electrode  12  coupled to an n-type drain  13  at a first end  10   a,  a source electrode  14  coupled to an n-type source  20 , and a gate  16  spaced apart from the drain  12  at a second end  10   b,  and a drift region  18  between the first and second ends  10   a  and  10   b.  The MOSFET  10  also includes a p-type well  21  proximate to the source  14  and the gate  16 , forming the body region of the field effect transistor. 
     The drift region  18  includes a p-type pillar  22  juxtaposed with an n-type pillar  24 , forming a “super junction.” The p-type pillar  22  and the n-type pillar  24  are doped with select ion concentrations such that these two pillars at least approximately deplete each other laterally. As a result, the MOSFET  10  may have a high breakdown voltage between the source  14  and the drain  12 . In operation, the n-type pillar  24  forms a conduction channel between the drain  12  and the source  14 . Compared with conventional power MOSFET, the n-type pillar  24  may be doped with higher concentrations and thus may have a low on-state resistance. 
       FIGS. 2A-2C  are partially schematic cross-sectional views of a semiconductor substrate  11  undergoing a process for forming the vertical MOSFET  10  of  FIG. 1  in accordance with the prior art. As shown in  FIG. 2A , the process includes depositing an n-type epitaxial layer  26  and implanting a p-type dopant  28  (e.g., boron) on a surface  27  of the n-type epitaxial layer  26 . As shown in  FIG. 2B , the n-type epitaxial layer  26  deposition and p-type dopant  28  implantation operations are repeated to form a drift region  18  until a desired thickness is achieved. As shown in  FIG. 2C , the implanted p-type dopant  28  is thermally diffused to merge into the p-type pillar  22 . 
     Thermally diffusing and merging the p-type dopant  28  in the multiple n-type epitaxial layers  26 , however, requires a long processing duration because the p-type dopant  28  is implanted superficially on the surface  27  of the n-type epitaxial layers  26 . As a result, the p-type dopant  28  diffuses not only vertically but also laterally to a significant degree. As a result, the foregoing technique cannot form pillars with small lateral dimensions (e.g., less than 12 microns) except by using a large number (e.g., 20) of epitaxial layer depositions. Accordingly, certain improvements are needed for efficiently and cost effectively forming small dimension pillars in vertical MOSFET. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a partially schematic cross-sectional view of a vertical MOSFET in accordance with the prior art. 
         FIGS. 2A-2C  are partially schematic cross-sectional views of a semiconductor substrate undergoing a process for forming the vertical MOSFET of  FIG. 1  in accordance with the prior art. 
         FIGS. 3A-3G  are partially schematic cross-sectional views of a semiconductor substrate undergoing a process for forming a vertical MOSFET in accordance with embodiments of the technology. 
         FIG. 4A  illustrates an example of simulation results of the process in  FIGS. 3A-3D . 
         FIG. 4B  illustrates an example of simulation results of the process in  FIG. 3E . 
         FIG. 4C  is a plot of dopant concentration versus depth of the example of simulation results in  FIG. 4B . 
         FIGS. 5A-5G  are partially schematic cross-sectional views of a semiconductor substrate undergoing a process for forming a vertical MOSFET in accordance with additional embodiments of the technology. 
     
    
    
     DETAILED DESCRIPTION 
     Several embodiments of the present technology are described below with reference to vertical MOSFET useful for power switching and associated methods of manufacturing. Many details of certain embodiments are described below with reference to semiconductor substrates. The term “semiconductor substrate” is used throughout to include a variety of articles of manufacture, including, for example, individual integrated circuit dies, sensor dies, switch dies, and/or dies having other semiconductor features. The term “photoresist” generally refers to a material that can be chemically modified when exposed to electromagnetic radiation. The term encompasses both positive photoresist, configured to be soluble when activated by the electromagnetic radiation, and negative photoresist, configured to be insoluble when activated by light. Many specific details of certain embodiments are set forth in  FIGS. 3A-5G  and in the following text to provide a thorough understanding of these embodiments. Several other embodiments can have configurations, components, and/or process operations different than those described in this disclosure. One of ordinary skill in the relevant art, therefore, will appreciate that additional embodiments may be practiced without several of the details of the embodiments shown in  FIGS. 3A-5G . 
       FIGS. 3A-3G  are partially schematic cross-sectional views of a semiconductor substrate  100  undergoing a process for forming a vertical MOSFET in accordance with embodiments of the technology. In the following discussion, the semiconductor substrate  100  includes an n-type substrate material for illustration purposes. One of ordinary skill in the art will understand that embodiments of the process may also include a p-type substrate material or an intrinsic (i.e., non-doped) substrate material in lieu of the n-type substrate material. 
     Referring to  FIG. 3A , in the illustrated embodiment, the semiconductor substrate  100  includes a first n-type substrate material  102  and an optional second n-type substrate material  104 . The first n-type substrate material has a first dopant concentration, and the optional second n-type substrate material  104  has a second dopant concentration lower than the first dopant concentration. In certain embodiments, the optional second n-type substrate material  104  may be deposited as an n-type epitaxial layer on the first n-type substrate material  102 . In other embodiments, the first and second n-type substrate materials  102  and  104  may be formed via diffusion, implantation, and/or other suitable techniques. In further embodiments, the optional second n-type substrate material  104  may be omitted. 
     As shown in  FIG. 3A , the process includes depositing an n-type epitaxial layer  106  onto the optional second substrate material  104  via chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), liquid phase epitaxy, and/or other suitable deposition techniques. The term “epitaxial layer” as used hereinafter generally refers to a monocrystalline film or layer on a monocrystalline substrate material. For example, the epitaxial layer  106  may include a monocrystalline silicon layer or other suitable semiconductor material doped with phosphorus (P), arsenic (As), antimony (Sb), and/or other suitable n-type dopant. In one embodiment, the epitaxial layer  106  has a dopant concentration that is generally the same as the optional second substrate material  104 . In other embodiments, the epitaxial layer  106  may have other desired dopant concentrations. The epitaxial layer  106  may have a thickness of about 3 microns to about 5 microns and/or other desired thickness values. 
     After depositing the epitaxial layer  106 , the process includes masking the epitaxial layer  106  with a masking material. In certain embodiments, masking the epitaxial layer  106  includes depositing a photoresist  108  (or other suitable masking materials) onto the epitaxial layer  106  via spin coating and/or other suitable techniques, as shown in  FIG. 3B . In one embodiment, the photoresist  108  has a thickness T that is at least five microns. In other embodiments, the photoresist  108  may have other desired thicknesses based on, for example, characteristics of an implanted dopant, implantation conditions, and/or other suitable criteria. 
     The photoresist  108  may then be patterned to form openings  110  in the photoresist  108 . The term “patterning” as used hereinafter generally refers to printing a desired pattern on a photoresist and subsequently removing certain portions of the photoresist to form the desired pattern in the photoresist using photolithography and/or other suitable techniques. Even though two openings  110  are shown in  FIG. 3B , in certain embodiments, the photoresist  108  may include any desired number of openings  110  based at least on a desired number of pillars (or continuous dopant columns). 
     As shown in  FIG. 3C , the process further includes implanting a plurality of vertically stacked dopant regions  114  into the epitaxial layer  106  via the openings  110 . In the illustrated embodiment, four discrete dopant regions  114  are vertically stacked one on top of another and occupy the entire thickness H of the epitaxial layer  106 . In other embodiments, any desired number of dopant regions  114  may be implanted in the epitaxial layer  106 . In further embodiments, the implanted dopant regions  114  may be spaced apart from one another by a distance (e.g., 0.1 micron). In yet further embodiments, the implanted dopant regions  114  may occupy only a portion of the thickness H of the epitaxial layer  106 . The individual dopant regions  114  can have a thickness of about 0.5 microns to about 1.5 microns and/or other desired thickness values. 
     In the illustrated embodiment, the individual dopant regions  114  may include the same dopant and generally the same dopant concentration and distribution profile. In other embodiments, the individual dopant regions  114  may include different dopants, dopant concentrations, and/or distribution profiles. For example, the dopant regions  114  may have graduated dopant concentrations and/or profiles from a first side to a second side of the epitaxial layer  106 . In another example, different dopants may be used for at least some of the dopant regions  114 . 
     In several embodiments, ion implantation techniques may be used for implanting the dopant regions  114 . In such embodiments, the epitaxial layer  106  is bombarded with select dopant ions (as indicated by arrows  112 ). Suitable dopant ions may include boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Ti), and/or other suitable dopants. The depth, dopant concentration, and/or distribution profile of the individual dopant regions  114  may be controlled by altering or adjusting at least one of (1) an implantation energy, (2) an ion concentration, and (3) an implantation duration. For example, to implant a dopant region  114  with a low dopant concentration in a condensed profile deep into the epitaxial layer  106 , a high implantation energy (e.g., greater than about 1,000 keV) with a low ion concentration and short implantation duration may be used. To implant a dopant region  114  with a high dopant concentration in a proliferated profile shallow into the epitaxial layer  106 , low implantation energy (e.g., less than about 200 keV) with a high ion concentration and long implantation duration may be used. In other embodiments, implanting the dopant regions  114  may be via diffusion and/or other suitable techniques. 
     In certain embodiments, the thickness of the epitaxial layer  106  may be chosen based on the highest available ion implantation energy that can introduce an implanted dopant region  114  at a depth that allows the lowermost implanted region  114  in the epitaxial layer  106  to merge with the uppermost implanted region  114  of the same epitaxial layer  106 . In other embodiments, the thickness of the epitaxial layer  106  may be chosen based on other suitable criteria. 
     In certain embodiments, an optional hardmask (e.g., silicon dioxide and/or other suitable masking materials, not shown) may be deposited on the epitaxial layer  106  before the photoresist  108  is deposited and patterned. Subsequently, the hardmask is etched through the openings in the photoresist before the ion implantation operation. The optional hardmask may provide improved masking of high-energy ion implantations with a thin layer, which may minimize the thickness of the photoresist  108  and may thus improve the manufacturability of the foregoing process. 
     As shown in  FIG. 3D , the process includes removing the photoresist  108  and repeating the operation stages illustrated in  FIGS. 3A-3C  until a desired number of epitaxial layers  106  are formed. In the illustrated embodiment, five epitaxial layers  106  are shown for illustration purposes. In other embodiments, any desired number of epitaxial layers  106  may be formed on the first n-type substrate material  102  or the optional second n-type substrate material  104 . 
     As shown in  FIG. 3E , after a desired number of epitaxial layers  106  are formed, the process includes merging the dopant regions  114  in the individual epitaxial layers  106  to form a p-type pillar  116 . In one embodiment, merging the dopant regions  114  includes thermally diffusing the dopant regions  114  at a temperature (e.g., 1,100° C.) for a short period of time (e.g., 120 minutes). In other embodiments, merging the dopant regions  114  may include radiating the epitaxial layers  106  and/or via other suitable techniques. 
     Several embodiments of the foregoing process can produce doped pillars with a reduced lateral dimension compared to the conventional technique discussed above with reference to  FIGS. 2A-2C . Unlike the conventional technique, several embodiments of the foregoing process include forming a plurality of closely spaced or directly contacting dopant regions  114  vertically stacked in the individual epitaxial layers  106 . As a result, short diffusion durations may be sufficient to merge the dopant regions  114 , thus reducing lateral diffusion of the dopant in the epitaxial layers  106  in contrast to the conventional technique. 
     Several embodiments of the foregoing process can allow improved control of vertical and/or lateral doping concentrations and/or distribution profiles. For example, for each of the epitaxial layers  106 , different dopant concentrations (e.g., increasing or decreasing with respect to the thickness H) and/or distribution profiles (e.g., a lateral and/or vertical dimension of the dopant regions  114 ) may be used for at least some of the dopant regions  114 . As a result, the pillars  116  may have a select concentration and/or distribution profile after merging. 
     Even though the process is illustrated above as having the same openings  110  for patterning the individual epitaxial layers  106 , in certain embodiments, other openings that are different in at least one of a location, a shape, a width, and a depth may be used for at least some of the epitaxial layers  106  to form pillars  116  with a conical shape as shown in  FIGS. 3F  or  3 G. In other embodiments, other patterns of openings may be used for at least some of the epitaxial layers  106  to form pillars  116  with a stepped shape, a zigzag shape, a parabolic shape, and/or other suitable shapes. 
     In further embodiments, the process may include additional operations prior to removing the photoresist  108 . For example, an etching operation may be performed through the openings  110  to form a shallow recess (not shown) in the epitaxial layer  106 . The shallow recess may be used for alignment of subsequent photo masks and/or other purposes. In yet further embodiments, the process can also include forming a source, a gate, a drain, and/or other suitable components to form a vertical MOSFET generally similar in structure to the MOSFET  10  in  FIG. 1 . 
     Simulations were performed based on a process generally similar to that discussed with reference to  FIGS. 3A-3E . In these simulations, ten epitaxial layers were formed. Each of the epitaxial layers has a thickness of 4 microns and an n-type dopant concentration of 2.5×10 15  atoms per centimeter cubed. Four boron doped regions were formed via a 4 micron wide photoresist opening in each of the epitaxial layers. The implantation energy and ion densities used are listed below: 
                                                 Implantation energy   Ion density               keV   atoms/cm 2                                                      First region   200   5 × 10 11             Second region   1,000   5 × 10 11             Third region   1,700   5 × 10 11             Fourth region   2,500   5 × 10 11                      
After forming the four boron doped regions, thermal diffusion was performed at 1,100° C. for 120 minutes. The formed super junctions appeared to be generally uniform with an 8 micron pitch (i.e., a 4 micron boron pillar next to a 4 micron n-type pillar). After diffusion, the vertical extent of each implanted region is about 1 micron.
 
       FIG. 4A  illustrates an example of simulation results of the process in  FIGS. 3A-3D .  FIG. 4B  illustrates simulation results of the process in  FIG. 3E , and  FIG. 4C  is a plot of dopant concentration versus depth of the simulation results in  FIG. 4B . In these simulations, boron is implanted at four different implantation energies into each of the ten n-type epitaxial layers  106 , though other types of dopant and/or epitaxial layer may also be used. As shown in  FIG. 4A , a plurality of dopant regions  114  are vertically stacked with a distance separating one another along a depth of the stacked epitaxial layers  106 . As shown in  FIG. 4B , after merging, the dopant regions  114  are diffused together to form a pillar or column  116  of boron dopant. The lateral extent of the column  116  is substantially the same as the lateral extent of the individual dopant regions  114 , allowing the widths of the column  116  to be much narrower compared to prior art super junction devices. 
     As shown in  FIG. 4C , the dopant concentration along the depth of the epitaxial layer  106  appears to be generally uniform. The individual implantation operations introduces a dopant region that has the highest doping concentration near a center of its vertical extent and decreasing doping concentrations toward two ends from the center. Because there is little lateral diffusion of the implanted dopant regions  114 , the doping concentration is substantially constant across the width of the individual implanted dopant regions  114 . 
       FIGS. 5A-5G  are partially schematic cross-sectional views of a substrate  100  undergoing a process for forming a vertical MOSFET in accordance with additional embodiments of the technology. In the following discussion, several embodiments of the process may include components and/or structures that are generally similar to those discussed above with reference to  FIGS. 3A-3G . As such, similar identification numbers refer to similar components and/or structures. 
     As shown in  FIG. 5A , the process includes depositing an intrinsic (i.e., substantially non-doped) epitaxial layer  206  onto the optional second substrate material  104  via CVD, PECVD, ALD, and/or other suitable deposition techniques. After depositing the epitaxial layer  206 , the process includes depositing a first photoresist  208  onto the epitaxial layer  206  via spin coating and/or other suitable techniques, as shown in  FIG. 5B . The first photoresist  208  may then be patterned to form first openings  210 . Even though two first openings  210  are shown in  FIG. 5B , in other embodiments, the first photoresist  208  may include any desired number of first openings  210  based at least in part on a desired number of first pillars with a first dopant type. 
     As shown in  FIG. 5C , the process includes implanting a plurality of vertically stacked first dopant regions  214  into the epitaxial layer  206  via the openings  210  with ions of the first dopant type (as indicated by the arrows  212 ). The first dopant type may be n-type or p-type. As shown in  FIG. 5D , the process also includes removing the first photoresist  208  from the epitaxial layer  206  and depositing a second photoresist  218  onto the epitaxial layer  206 . The second photoresist  218  may then be patterned to form a second opening  220 . In the illustrated embodiment, the second opening  220  generally corresponds to a space between two adjacent columns of vertically stacked first dopant regions  214 . In other embodiments, the second opening  220  may also correspond to a space that at least partially overlaps with at least one of the adjacent columns of vertically stacked first dopant regions  214 . 
     As shown in  FIG. 5E , the process includes implanting a plurality of vertically stacked second dopant regions  224  into the epitaxial layer  206  via the opening  220  with ions of a second dopant type (as indicated by arrows  222 ). The second dopant type is different than the first dopant type and may also be n-type or p-type depending on characteristics of the first dopant type. In the illustrated embodiment, the second dopant regions  224  are laterally spaced apart and between two adjacent columns of the first dopant regions  214 . In other embodiments, the second dopant regions  224  may be laterally juxtaposed and in direct contact or may at least partially overlap with the two adjacent columns of the first dopant regions  214 . 
     As shown in  FIG. 5F , the process includes removing the second photoresist  218  and repeating the operations illustrated in  FIGS. 5A-5E  until a desired number of epitaxial layers  206  are formed. In the illustrated embodiment, five epitaxial layers  206  are shown for illustration purposes. In other embodiments, any desired number of epitaxial layers  206  may be formed. 
     As shown in  FIG. 5G , after the desired number of epitaxial layers  206  are formed, the process includes merging the first dopant regions  214  and merging the second dopant regions  224  in the individual epitaxial layers  206  to form at least one first dopant-type (e.g., p-type) pillar  216  and at least one second dopant-type (e.g., n-type) pillar  226 , respectively. In one embodiment, merging the first and second dopant regions  214  and  224  includes thermally diffusing the first and second dopant regions  214  and  224  at a temperature (e.g., 1,100° C.). In other embodiments, merging the first and second dopant regions  214  and  224  may include radiating the epitaxial layers  206  and/or other suitable techniques. 
     Several embodiments of the process discussed above with reference to  FIGS. 5A-5G  may have improved charge balance and control when compared to conventional techniques. In the conventional technique discussed above with reference to  FIGS. 2A-2C , a p-type dopant is implanted in n-type epitaxial layers, in which the concentration and/or distribution profile of the n-type dopant may not be easily controlled. In contrast, several embodiments of the foregoing process implant particular types of dopant at a desired concentration and/or distribution profile and thus may have improved charge balance and control. 
     From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration. However, various modifications may be made without deviating from the disclosure. Many of the elements of one embodiment may be combined with other embodiments in addition to or in lieu of the elements of the other embodiments. Accordingly, the disclosure is not limited except as by the appended claims.