Patent Publication Number: US-6339319-B1

Title: Cascoded current mirror circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to current mirror circuits and more particularly to transistor current mirror circuits used in analog integrated circuit devices. 
     2. Description of Related Art 
     Transistor current sources used in analog integrated circuits are generally well known. Typically, such circuits have been utilized as biasing elements and as load devices for amplifier stages. The use of current sources in biasing can result in superior insensitivity of current performance to power-supply variations and to temperature. Furthermore, current sources are frequently more economical than resistors in terms of the die area required to provide bias current of a certain value, particularly when the value of the bias current required is relatively small. When used as a load element in transistor amplifiers, the high incremental resistance of the current source results in high voltage gain at low power supply voltages. 
     One type of known current source comprises a current mirror and is commonly used in both junction and field effect semiconductor technology. In its simplest form, a current mirror circuit consists of a resistor and two transistors whose currents are constantly proportional to one another. In order to provide a more accurate current source which is less susceptible to variations in output current and changes in supply voltages, cascoded current mirrors were developed. However, as is well known, cascoded current mirrors require more headroom, i.e., more voltage compliance for achieving a desired operating range, than simple current mirrors. Accordingly, well known beta helper circuitry was then added to reduce base current errors; however this type of circuitry increases the headroom requirement even more. 
     SUMMARY 
     Accordingly, it is an object of the present invention to provide an improvement in circuitry used in connection with analog integrated circuit architecture. 
     It is another object of the present invention to provide an improvement in analog integrated circuit current sources. 
     It is yet another object of the invention to provide an improvement in the type of transistor current sources known as current mirrors. 
     And it is yet still another object of the invention to provide an improvement in cascoded current mirror circuits. 
     These and other objects are achieved by the addition of an emitter follower to a current mirror and, more particularly to a cascoded current mirror that uses beta helpers to reduce the mirror error due to base currents for restoring a Vbe of voltage compliance to the cascoded current mirror, and thus allows the use of a cascoded current mirror in applications where it could not otherwise be used due to voltage compliance problems. 
     In its broadest aspect, the invention is directed to a current mirror circuit, comprising: at least two semiconductor devices, and preferably two pairs of cascoded semiconductor devices, such as transistors, having first and second current conducting electrodes and a control electrode, connected together in a current mirror circuit configuration, wherein the control electrodes thereof are commonly connected together, the first current conducting electrodes being directly connected to a first supply voltage terminal and the second current conducting electrodes being connected to a second supply voltage terminal through respective electrical impedance elements for providing a reference or input current through one of said semiconductor devices and an output current through the other of said semiconductor devices and wherein the reference current and the output current mirror each other and have a constant ratio; a third and a fourth semiconductor device, each having first and second current conducting electrodes and a control electrode, connected between said at least two semiconductor devices to improve the voltage compliance thereof, wherein the control electrode of the third semiconductor device is connected to the second current conducting electrode of said one semiconductor device, wherein one of said first and second current conducting electrodes of the third semiconductor device is directly connected to the first supply voltage terminal, and the other of said first and second current conducting electrodes of said third semiconductor device is connected to the second supply voltage terminal through a load impedance and directly to the control electrode of the fourth semiconductor device, and wherein one of said first and second current conducting electrodes of the fourth semiconductor device is directly connected to the second supply voltage terminal and the other of said first and second current conducting electrodes of the fourth semiconductor device is connected to the first supply voltage terminal through a load impedance and directly to the control electrodes of said at least two semiconductor devices. 
     Further scope of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood, however, that the detailed description and specific examples, while indicating the preferred embodiments of the invention, are presented for purposes of illustration only, since various changes, alterations and modifications coming within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more fully understood when considered in conjunction with the accompanying drawings which are provided by way of illustration only, and thus are not limitative of the present invention, and wherein: 
     FIGS. 1A and 1B are electrical schematic diagrams illustrative of conventional complementary type simple current mirror circuits; 
     FIGS. 2A and 2B are electrical schematic diagrams illustrative of conventional complementary type cascoded current mirror circuits; 
     FIGS. 3A and 3B are electrical schematic diagrams of conventional complementary type simple current mirror circuits including beta helper circuitry; 
     FIGS. 4A and 4B are electrical schematic diagrams illustrative of conventional complementary type cascoded current mirror circuits also including beta helper circuitry; 
     FIGS. 5A and 5B are electrical schematic diagrams illustrative of complementary type simple current mirror circuits with beta helper circuitry and an emitter follower in accordance with one embodiment of the subject invention; and 
     FIGS. 6A and 6B are electrical schematic diagrams illustrative of complementary type cascoded current mirror circuits with both beta helper circuitry and circuitry in accordance with the preferred embodiment of the subject invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the drawings wherein like reference numerals refer to like parts throughout, FIGS. 1A and 1B respectively depict npn and pnp semiconductor embodiments of a simple current mirror circuit which is generally well known to those skilled in the art of integrated circuit and semiconductor technology. Reference numeral  10 , for example, denotes a first npn transistor Q 1  connected between voltage supply source rails V cc  and V ee  via a collector load impedance  12  which causes a reference current or input current I 1  to follow and thus is considered an I 1  current source. The base and collector of transistor Q 1  is diode connected, forcing the collector-base voltage to zero. The base of Q 1  is connected to the base of a second npn transistor Q 2 , denoted by reference numeral  14 , whose collector is connected to V cc  via a load resistor  16 , providing an output current I 0  therethrough. Further as shown, the emitter electrodes of both Q 1  and Q 2  are connected to the V ee  rail. Ground potential may also be substituted for V ee  when desirable. 
     FIG. 1B is a complementary pnp transistor embodiment of FIG.  1 A and simply involves a required reversal of polarity connections which is conventional. 
     In a current mirror circuit which is implemented, for example, on a die of an integrated current structure, the output current I 0  is proportional to the input current I 1  being dependent upon the ratio of the respective emitter areas A 1  and A 2  of transistors Q 1  and Q 2  on the die, such that:            I   O       I   1       =       A   2       A   1                       
     Thus for the case of identical devices Q 1  and Q 2 , the output current I 0  and reference/input current  1   1  are equal. Actually, the devices need not be identical; the emitter areas of Q 1  and Q 2  can be made different, which will cause the current values I 0  and I 1  for the two transistors to be different. The two currents, however will have a constant ratio. This ratio can be either less than or greater than unity, and thus any desired output current I 0  can be derived from a fixed reference current, I 1 . 
     Referring now to FIGS. 2A and 2B, shown thereat are npn and pnp embodiments of a cascoded current mirror and which are also well known to those skilled in the art. As shown in FIG. 2A, a third npn transistor Q 3  shown by reference numeral  18  is series connected to transistor Q 1 . Transistor Q 3  is also diode connected. A fourth npn transistor Q 4  shown by reference numeral  20  is also series connected to transistor Q 2 . 
     With respect to the complementary circuit configuration of FIG. 2B, a third pnp transistor Q 3  shown by reference numeral  19  is connected in series to Q 1 . In a like manner, a fourth pnp transistor Q 4  shown by reference numeral  21  is series connected to transistor Q 2  consisting of pnp transistor  15 . 
     The cascoded current mirror configurations provide a circuit which is not only more accurate, but is less susceptible to variation in output current I 0  with respect to changes in V cc . Such circuitry, however, involves twice as many transistors and thus involves a loss of V be  of voltage compliance due to the additions of transistors Q 3  and Q 4 . 
     In an effort to reduce base current errors in current mirror circuitry utilizing diode connected transistors Q 1  and Q 3  such as shown, for example, in FIGS. 1A,  1 B and  2 A,  2 B, the prior art has resorted to the inclusion of a beta helper circuit shown, for example, in FIGS. 3A and 3B including a transistor Q 5  coupled between the collector and base junction of transistor Q 1 . In FIG. 3A, this takes the form of an npn transistor  22  connected across the collector-base junction of npn transistor  10 , while in FIG. 3B, it comprises the inclusion of a pnp transistor  23 , having its base-emitter junction connected across the base-collector junction of pnp transistor  11 . 
     Further, the emitter of beta helper transistor Q 5  of FIG. 3A is commonly connected to the base electrodes of transistors Q 1  and Q 2  at circuit node  24 , with circuit node  24  being connected to the V ee  rail via emitter load resistor  26 . In the complementary circuit of FIG. 3B, the emitter resistor  26  of transistor Q 5  is now returned to the supply rail V cc    
     Beta helper circuitry provides more accuracy by reducing the base current errors inherent in the simple and cascoded current mirror configurations. However, it results in the addition of still another transistor element. The V be  voltage drop across transistor Q 5  limits the voltage swing of I 1  and the voltage at I 1  current source  12  cannot be any higher than V cc −2V be  for the circuits to operate correctly for FIG.  3 B. 
     The same conditions apply with respect to the npn and pnp cascoded current mirror circuits with beta helper circuitry such as shown in FIGS. 4A and 4B. In the circuitry shown in FIGS. 4A and 4B, there is provided a second beta helper circuit which includes transistor Q 6  which in the npn configuration, comprises the transistor  28 , while in the pnp configuration, comprises the transistor  29 . As with the beta helper transistor Q 5  shown in FIG. 4A, the emitter of Q 6  is, commonly connected to the base electrodes of transistors Q 3  and Q 4  at circuit node  32  as well as being returned to the voltage supply rail V ee  via resistor  30 . However, in the pnp implementation of FIG. 4B, emitter resistor  30  is now returned to the V cc  rail. Beta helpers in the cascoded embodiment limit the voltage swing across the I 0  load element  16 . 
     This now leads to a consideration of the embodiments of the subject invention which involves the addition of an emitter follower to the beta helper circuitry of FIGS. 3A,  3 B and  4 A,  4 B and which operates to restore a V be  of voltage compliance to the circuitry. A simple current mirror configuration of such a circuit is shown in FIGS. 5A and 5B and comprise npn and pnp implementations of the same circuit. 
     Considering now FIG. 5A, an emitter follower circuit including transistor Q 7 , consisting of a pnp transistor  34 , the emitter of which is coupled to the base of the beta helper transistor Q 5  shown consisting of the transistor  22 . An emitter resistor  36  for transistor Q 7  is connected to the V cc  rail at circuit node  38 . The collector of the transistor Q 7  is connected directly to the V ee  rail. The base of the pnp transistor Q 7  is connected to the collector of transistor Q 1  and the current source  12 . 
     It is to be noted that the transistors Q 1 , Q 2 , and Q 5  are comprised of npn transistors  10 ,  14  and  22 , whereas the emitter follower transistor Q 7  comprises a transistor  34  of opposite semiconductivity i.e. a pnp transistor. The transistor Q 7 , in effect, acts as a level shifter to provide a compensating V be  to circuit node  38  so as to improve the voltage swing of I 1  at circuit node  40 . 
     In the complementary circuit configuration of FIG. 5B, transistors Q 1 , Q 2  and Q 5  are comprised of the pnp transistors  11 ,  15 , and  23 , respectively. Now, however, the emitter follower transistor Q 7  comprises a npn transistor  35 , with the emitter electrode now being returned to the V ee  rail by means of emitter resistor  36 . 
     The concept of adding an emitter follower circuit for restoring a 1V be  of voltage compliance for enhancing the head room requirement, was conceived primarily for use in connection with a cascoded current mirror circuit that uses beta helpers. Accordingly, the complementary npn and pnp embodiments shown in FIGS. 6A and 6B disclose the preferred embodiments of the invention. 
     With respect to the npn embodiment shown in FIG. 6A, it is similar to the cascoded current mirror with beta helper circuit configuration shown in FIG. 4A; however, it now additionally includes an emitter follower transistor Q 7  consisting of a pnp transistor  34  located in front of beta helper transistor Q 6 . In this regard, the base of Q 7  is connected to circuit node  37 , which is common to the series interconnection of the emitter of Q 1  and the collector of Q 3 . Furthermore, the emitter of emitter follower transistor Q 7  is directly connected in a voltage follower circuit relationship to the base of Q 6  and is returned from circuit node  38  to the V cc  rail via resistor  36 . The collector of the emitter follower transistor Q 7  is connected directly to the V ee  rail which is noted heretofore as also capable of being at zero or ground potential. 
     This circuit configuration results in a 1V be  (base to emitter) voltage drop at circuit node  32  which is caused by the base-emitter junction of transistor Q 3 . The beta helper transistor Q 6 , however, results in a 2V be  voltage drop at circuit node  38  which is common to the emitter of Q 7  and the base of Q 6 . The presence of the transistor Q 7  now acts as a level shifter, restoring a 1V be  of voltage compliance to circuit node  37 , whereas in the configuration of FIG. 4A, the voltage at circuit node  24  would be V ee +3V be  resulting in I 0  not being able to be lower than this or else transistor Q 2  saturates. With the inclusion of the transistor Q 7  as shown in FIG. 6A, I 0  can pull down to V ee +2V be , thus reducing the head room requirement by 1V be . 
     Turning attention now to the pnp embodiment as shown in FIG. 6B, the same circuit relationship exists; however, the emitter follower transistor Q 7  now comprises an npn transistor  35  whose base is connected to circuit node  41  between the collector of Q 1  and the emitter of Q 3 . The collector of the emitter follower transistor Q 7  is now connected to the V cc  rail. The emitter is directly connected to base of Q 6 . Emitter load resistor  36  is connected to the V ee  rail at circuit node  38 . Further as shown in FIG. 6B, the pnp beta helper transistor Q 6  has its collector connected directly to the V ee  rail, while the emitter is connected to circuit node  40 , which is common to the base electrodes of transistors Q 1  and Q 2 , and further returned to the V cc  supply rail via resistor  30 . 
     Thus what has been shown and described is a cascoded current mirror circuit which includes an emitter follower to restore a V be  of voltage compliance to a circuit that also uses beta helpers which operate to reduce the mirror error due to base currents. Such a configuration, in particular, allows the use of a cascoded current mirror circuit, in applications where it could not normally be used due to voltage compliance problems. 
     Having thus shown and described what is at present considered to be the preferred embodiments of the invention, it should be noted that the same has been made by way of illustration and not limitations. Accordingly, all modifications, alterations and changes coming within the spirit and scope of the invention as set forth in the appended claims, are herein meant to be included.