Patent Publication Number: US-8984213-B2

Title: Electronic system and memory managing method thereof

Description:
This application claims the benefit of Taiwan application Serial No. 100142612, filed Nov. 21, 2011, the subject matter of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates in general to a flash memory, and more particularly, to a method for managing a multi-level cell (MLC) flash memory. 
     2. Description of the Related Art 
     Different from a single-level cell (SLC) flash memory, an MLC flash memory is capable of storing at least two information bits in each storage unit. The term “multi-level” as used here means that each storage unit has more than two voltage values. Although the MLC flash memory is compromised by drawbacks of having shorter lifespan, higher power consumption, and a slower access speed, the MLC is still prevalent in various kinds of storage device because it has a greater capacity per unit cost than that of the SLC flash memory. 
     The MLC flash memory generally includes several blocks, each of which includes multiple sets of paired pages. Taking a page containing 32 pages as an example, the block possibly contains 16 most significant bit (MSB) pages and 16 least significant bit (LSB) pages. Each MSB page pairs with one LSB page to form a set of storage unit. One of the most critical drawbacks of the MLC flash memory is that, when an unexpected power-off or reset takes place while data are being written into a MSB page, not only data in the MSB page currently being written but also data originally stored in the paired LSB page corresponding to the MSB page are damaged, and vice versa. 
     Certain solutions for preventing or remedying the above error are available. In one conventional solution, an upper file system restores a file that is not completely written according to a system log. In another conventional solution, a writable region is limited within a single-type page (e.g., only the MSB page or the LSB page) between the paired pages—such approach suffers from a shortcoming of significantly reduced available capacity of a memory. In yet another conventional solution, data originally stored in a paired page B of a page A is duplicated to a backup region when writing data into the page A. Thus, when an error occurs in the write process, the system simply restores the data back to the page B from the backup region. 
     SUMMARY OF THE INVENTION 
     The invention is directed to a method for managing a multi-level unit (MLC) flash memory. In a write procedure, data are first stored in a predetermined type of pages in a cache block to prevent mutual damaging of paired pages. When a write-back condition is met, a set of target data is officially written to a target block. In the occurrence of an unusual situation during the process of writing the set of target data into the target block, the data in the cache block may be utilized to assist in restoring the target block. 
     According to one embodiment the present disclosure, a method for managing an MLC flash memory including a plurality of blocks is provided. Each block includes a plurality of sets of a first page and a second page configured in pair. In response to a request for writing a set of target data into a target block, at least one cache block is selected from the plurality of blocks. The set of target data is then written into the first pages of the at least one cache block. When a write-back condition is met, the set of target data is written from the cache block to the target block. 
     According to another embodiment of the disclosure, an electronic system is provided. The electronic system includes an MLC flash memory and a controller. The MCL includes a plurality of blocks, each block of which includes a plurality of sets of a first page and a second page configured in pair. In response to a request for writing a set of target data into a target block, the controller selects at least one cache block from the plurality of blocks, and the writes the set of target data into the first pages of the at least one cache block. When a write-back condition is met, the controller writes the set of target data from the cache block to the target block. 
     According to yet another embodiment of the disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores a code readable and executable by a processor. The code is for managing an MLC flash memory. The MLC memory includes a plurality of blocks, each of which includes plurality of sets of a first page and a second page configured in pair. In response to a request for writing a set of target data into a target block, a first code selects at least one cache block from the plurality of blocks. A second code writes the set of target data into the first pages of the at least cache block. When a write-back condition is met, a third code writes the set of target data from the first pages of the at least one cache to the target block. 
     The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a flowchart of a method for managing a memory according to an embodiment of the disclosure. 
         FIG. 2  is a schematic diagram showing content of a cache block according to one embodiment of the disclosure. 
         FIG. 3  is a schematic diagram depicting relations among pages of a target block and cache blocks according to one embodiment of the disclosure. 
         FIGS. 4 and 5  are flowcharts of a method for managing a memory according to an embodiment of the disclosure. 
         FIG. 6  is a block diagram of an electronic device according to one embodiment of the disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A method for managing a flash memory, e.g., a multi-level cell (MLC) flash memory, is provided according to one embodiment of the disclosure.  FIG. 1  shows a flowchart of the method. In practice, the MLC flash memory may be directly built-in an electronic system, or may be in a form of a memory card or a portable disk connecting to an electronic system via versatile converting devices. For example, the electronic system may be a digital video camera, a mobile communication device, a portable computer, a desktop computer, or an external storage device capable of communicating with the MLC flash memory. 
     In this embodiment, the MLC flash memory includes a plurality of blocks, each of which includes a plurality of sets of a first page and a second page configured in pair. For example, the first page may be a most significant bit (MSB) page, and the second page is correspondingly a least significant bit (LSB) page. Alternatively, the first page may be an LSB page and the second page may correspondingly be an MSB page. In a triple-level cell (TLC) flash memory, the first page and the second page may be any two pages among three pages of a same set. In the following descriptions, an example of the first page being an LSB page and the second page being an MSB page is given. 
     Referring to  FIG. 1 , in Step S 11 , a request for writing target data into a target block is received. In response to the request, Step S 12  is performed to select at least one cache block from the blocks of the MLC flash memory. For example, the MLC flash memory may be designed to reserve a predetermine number (e.g., 20) of blocks serving as cache blocks. If the request received in Step S 11  is for writing target data into a target block A of the MLC flash memory, Step S 12  is performed to select two unused cache blocks B 1  and B 2  from the 20 cache blocks, corresponding to the target block A. 
     In Step S 13 , the target data intended for the target block A are first written into the cache blocks B 1  and B 2  instead of being directly written into the target block A.  FIG. 2  is a schematic diagram of the cache blocks B 1  and B 2 . In this embodiment, the target data are stored in the LSB pages in the cache blocks B 1  and B 2 . In other words, the MSB pages in the cache blocks B 1  and B 2  are not utilized. Taking a situation that the target block A and the cache blocks B 1  and B 2  respectively including 16 LSB pages and 16 MSB pages as an example, the target data is only stored in the 16 LSB pages in the cache block B 1  and the 16 LSB pages in the cache block B 2 . 
     Assume that the size of the target data intended for the target block A in the embodiment in  FIG. 2  occupy 14 pages. It should be noted that, the target data are sequentially written into the LSB pages of the cache blocks B 1  and B 2 , with a column with sequence number indicating a write sequence. In this embodiment, the first page of the target data is stored into a page bearing a page number 0 in the cache block B 1 , the second page of the target data is stored into a page bearing a page number 0 in the cache block B 2 , and the third page of the target data is stored in a page bearing a page number 1 in the cache block B 1 . In  FIG. 2 , the first 13 pages of the target data are stored, and the 14 th  page is being stored into a page bearing a page number 10 in the cache block B 2 . 
     As shown in  FIG. 2 , the target data are distributed in the LSB pages in the cache blocks B 1  and B 2 . Since the MSB pages in the cache blocks B 1  and B 2  are not used, a storage approach of the cache blocks B 1  and B 2  are substantially the same as that of the SLC flash memory, and is thus free from mutual damaging of the paired pages. 
     In Step S 14 , it is determined whether a write-back condition is met. In one embodiment, the write-back condition is met when a normal shut-down occurs. A normal shut-down refers to a situation that the electronic system implementing the MLC flash memory enters a shut-down state according to a normal procedure. When a determination result in Step S 14  is negative, Step S 16  is performed to end the current write procedure. Conversely, when the determination result in Step S 14  is affirmative, Step S 15  is performed to write the target data from the LSB pages in the cache blocks B 1  and B 2  back to the target block A. In practice, when the normal shut-down is in progress, the data stored in the above 20 blocks can be respectively written back to the corresponding target block. 
       FIG. 3  shows a schematic diagram depicting relations among the pages in the target block A and those in the cache blocks B 1  and B 2 . In this embodiment, when the determination result in Step S 14  is affirmative, the target data stored in the 14 pages LSB pages in the cache blocks B 1  and B 2  are respectively written back to the pages numbered 0 to 13 in the target block according to the sequence number. It should be noted that, the writable region in the target block A for storing the target data is not limited to a specific type of pages. That is to say, both the LSB pages and the MSB pages in the target block A may be utilized for storing data. Further, when writing the data back to the target block A, backup data for restoring original data is still present in the cache blocks B 1  and B 2 , and so mutual damaging of the paired pages is eliminated. 
     In another embodiment, the write-back condition is met when a capacity of a cache block saturates. For example, assuming the size of the target data intended for the target block A occupies a total of 32 pages, i.e., the target data occupies all the LSB pages in the cache blocks B 1  and B 2 . After having written the target data into the cache blocks B 1  and B 2 , it is determined that the capacity of the cache blocks B 1  and B 2  has reached saturation. When the capacity of the cache blocks B 1  and B 2  has reached saturation, the write-back condition is met and Step S 15  is performed to write the target data stored in the LSB pages in the cache blocks B 1  and B 2  back to the pages numbered 0 to 31 in the target block A. 
     In practice, before reaching capacity saturation of the cache blocks B 1  and B 2 , the target data intended for the target block A are temporarily stored in the cache blocks B 1  and B 2 . Each cache block currently being used is marked to indicate to which block in the MLC flash memory that the cache block corresponds. After writing the data target back to the target block A, the cache blocks B 1  and B 2  are cleared to again become cache blocks that are not in use. 
     In another embodiment, the write-back condition includes an insufficient number of cache blocks. For example, assume the foregoing 20 cache blocks are all marked as in use. When a request for writing data into the MLC flash memory arises, data in one or more cache blocks in the 20 cache blocks are written back to the corresponding block, so as to vacate cache blocks for storing new data. 
       FIG. 4  shows a flowchart of a managing method according to another embodiment of the disclosure. In the method according to this embodiment, the method further includes Step S 12 A. In Step S 12 A, it is determined whether at least one cache block in the flash memory is assigned to be corresponding to the target block before Step S 12 . When a determination result in Step S 12 A is negative, at least one cache block is selected from unused blocks for the target block in Step S 12 B. Conversely, when the determination result in Step S 12 A is affirmative, the target data are directly written into the at least one cache block corresponding to the target block in Step S 13 . For example, if cache blocks B 1  and B 2  among the foregoing 20 cache blocks are already assigned to be corresponding to target block A, the cache blocks B 1  and B 2  can be directly used instead of additionally assigning another cache block to the target block. 
       FIG. 5  shows a flowchart of a managing method according to yet another embodiment of the disclosure. This process is implemented jointly with the method described in  FIG. 4  or  FIG. 1 . As previously described, the data in the cache blocks are supposedly written back to respective blocks when an electronic device enters a shut-down state under normal operation. Thus, after an electronic device operating jointly with the flash memory is reactivated, Step S 21  is performed to determine whether a cache block stored with data is present in the flash memory. When a determination result in Step S 21  is affirmative, an abnormal shut-down may have occurred, and Step S 22  is performed. In Step S 22 , the data in the cache block is written back to the block corresponding to the cache block to restore the data that is possibly not correctly written thereto earlier. 
     According to another embodiment of the disclosure, an electronic device is provided. Referring to  FIG. 6 , the electronic device includes a flash memory  62 , e.g., an MLC flash memory, and a controller  64 . The flash memory  62  includes a plurality of blocks, each of which includes a plurality of sets of a first page and a second page configured in pair. In response to a request for writing target data into a target block A, the controller  64  selects at least one cache block (B 1  and B 2 ) from the blocks, and writes the target data into the first pages (e.g., LSB pages) in the at least one cache block (B 1  and B 2 ). When a write-back condition is established, the controller  64  writes the target data from the first pages in the at least one cache block (B 1  and B 2 ) back to the target block A. 
     Operation details of the controller  64  can be referred to in the description of the foregoing managing methods and shall be omitted herein. In one embodiment, the controller  64  further includes a determining module for performing Step S 12 A and a selecting module for performing Step S 12 . In one embodiment, the controller  64  further includes another determining module for performing Step S 21  and a restoring module for performing Step S 22 . 
     According to yet another embodiment of the disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores a code that is readable and executable by a processor. For example, the code is installed in memory management firmware of an electronic device. The code is for managing a flash memory. When the code is loaded and executed by the processor, the processes in  FIG. 1 ,  4 , or  5  may be achieved. 
     Therefore, the disclosure provides a novel method for managing a flash memory. During a write procedure, data are stored in a predetermined type of pages in a cache block to prevent mutual damaging of the paired pages. The target data is only officially written into a target block when a write-back condition is established. In the event of an abnormal situation during the process of writing the target data into the target block, the data in the cache block may be utilized to assist in restoring the target block. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.