Patent Publication Number: US-2016232103-A1

Title: Block storage apertures to persistent memory

Description:
BACKGROUND 
     In a conventional computer system, a block storage device including non-volatile memory can be communicably coupled to a block storage device controller, which, in turn, can be communicably coupled to a processor by a system bus. Such a system bus is typically implemented as a Peripheral Component Interconnect express (PCIe) bus, allowing the processor to access block data storable within the block storage device by issuing one or more input/output (I/O) commands to the block storage device controller over the PCIe bus. Having received an I/O command from the processor over the PCIe bus, the block storage device controller can perform I/O processing including one or more direct memory access (DMA) operations to access the block data storable in the block storage device, and ultimately send a signal to the processor over the PCIe bus to signal completion of the I/O processing. However, such I/O processing performed by the block storage device controller in conjunction with the PCIe bus can cause latency in the processing of block write/read operations in such a conventional computer system. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated in and constitute part of this specification, illustrate one or more embodiments described herein, and, together with the Detailed Description, explain these embodiments. In the drawings: 
         FIG. 1  is a block diagram illustrating an exemplary apparatus for accessing, in a computer system, at least one non-volatile memory (NVM) device, which, in conjunction with an NVM device controller, can he collectively viewed by the computer system as a block storage device, in accordance with the present application; 
         FIG. 2  is a block diagram illustrating the NVM device controller included in the apparatus of  FIG. 1 ; 
         FIG. 3  is a block diagram illustrating an exemplary block window, a plurality of exemplary control registers, an exemplary address translation component, and an exemplary media management translation table included in the NVM device controller of  FIG. 2 ; 
         FIG. 4  is a flow diagram illustrating an exemplary method of operating the NVM device controller of  FIG. 1 ; 
         FIG. 5  is a block diagram of an exemplary computer system in which the NVM device controller of  FIG. 2  may be employed; 
         FIG. 6 a    is a block diagram illustrating an exemplary alternative embodiment of the NVM device controller of  FIG. 2 , including an exemplary mailbox for use by a host processor in issuing and monitoring one or more commands, such as memory load/store commands, sent by the host processor to the NVM device controller over a memory bus; 
         FIG. 6 b    is a diagram illustrating an exemplary op-code format associated with a respective command, an exemplary write protect bit associated with the op-code format, and an exemplary input payload format for use b a host processor in issuing the respective command to an NVM device controller us in the mailbox of  FIG. 6   a;    
         FIG. 6 c    is a diagram illustrating an exemplary status code format associated with respective command, and an exemplary output payload format for use by a host processor in monitoring completion of the respective command using the mailbox of  FIG. 6   a;  and 
         FIGS. 7 a -7 b    depict a flow diagram illustrating an exemplary method of issuing a command to an NVM device controller over a memory bus, and monitoring a status of completion of the command by a host processor using the mailbox of  FIG. 6   a.    
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Apparatus and methods are disclosed for accessing at least one non-volatile memory (NVM) device computer system that includes it least one host processor and at least one memory bus. In the disclosed apparatus and methods, the NVM device is communicably coupleable to the memory bus through an NVM device controller, thereby allowing the host processor to access persistent data storable within the NVM device by issuing one or more memory load/store commands to the NVM device controller over the memory bus. The computer system in conjunction with the host processor can implement a block storage driver, and the NVM device in conjunction with the NVM device controller can be collectively viewed by the computer system as a block storage device. Because the NVM device controller includes at least one block window (such a block window is also referred to herein as an “aperture”) that defines at least one address range for accessing one or more blocks of the persistent data storable within the NVM device, the computer system can as exploit, with reduced la envy full capacity of the NVM device without being unduly constrained by physical addressing limits imposed by the host processor, or by limits imposed by an operating system (OS) executed by the host processor. 
       FIG. 1  depicts an illustrative embodiment of an exemplary apparatus  100  for accessing at least one NVM device in a computer system, in accordance with the present application. As shown in  FIG. 1 , the apparatus  100  includes a host processor  101 , and one or more NVM device controllers  102 . 1 - 102 . n  (also referred to herein as “NVM controllers”) communicably coupled to the host, processor  101  by one or more memory buses  103 . 1 - 103 . n,  respectively As further shown in  FIG. 1 , one or more NVM devices can be communicably coupled to each of the NVM controllers  102 . 1 - 102 . n.  For example, one or more NVM devices  104 . 1 - 104 . m  can be communicably coupled to the NVM controller  102 . 1 , which, in turn, is communicably coupled to the host processor  101  via the memory bus  103 . 1 . Likewise, one or more NVM devices  106 . 1 - 106 . p  can be communicably coupled to the NVM controller  102 . n,  which, in turn, is communicably coupled to the host processor  101  via the memory bus  103 . n.    
     In the exemplary apparatus  100  of  FIG. 1 , the host processor  101  can he implemented using one or more processors, one or more multi-core processors, and/or any other suitable processor or processors. Further, each of the NVM devices  104 . 1 - 104 . m,    106 . 1 - 106 . p  can include non-volatile memory (NVM) such as NAND or NOR flash memory that uses a single bit per memory cell, multi-level cell (MLC) memory, for example, NAND flash memory with two bits per cell, polymer memory, phase-change memory (PCM), nanowire-based charge-trapping memory, ferroelectric transistor random access memory (FeTRAM), 3-dimensional cross-point memory, non-volatile memory that uses memory resistor (memristor) technology, or any other suitable non-volatile memory, NVM device, or persistent data storage medium. 
       FIG. 2  depicts an exemplary NVM controller  202  that can be employed in the apparatus  100  of  FIG. 1 . As shown in  FIG. 2 , the NVM controller  202  includes at least one block window (aperture)  208 , a plurality of control registers  212 , an address translation component  214 , a media management translation table  216 , an optional encryption component  218 , and an optional decryption component  220 . As further shown in  FIG. 2 , an NVM device  204  is communicably coupled to the NVM controller  202 , which, in turn, is communicably coupleable to the host processor  101  (see  FIG. 1 ) via a memory bus  203 . 
     In the exemplary NVM controller  202  of  FIG. 2 , the aperture  208  defines an address range for accessing one or more blocks of persistent data storable within the NVM device  204 . The plurality of control registers  212  can include a plurality of command registers  0 -q, a plurality of status registers  0 -q, and a plurality of memory-mapped base address registers  0 -q containing a. plurality logical base addresses, respectively. Each of the plurality of memory-mapped base address registers  0 ,  1 , . . . q corresponds to a predetermined portion of the address range defined by the aperture  208 . Further, the plurality of status registers  0 -q are associated with the plurality of command registers  0 -q, respectively, and the status register/command register pairs  0 , 0 ,  1 , 1 , . . . q,q are, in turn, associated with the plurality of memory-mapped base address registers  0 -q, respectively. 
     The address translation component  214  is operative to translate one or more logical addresses within the address range defined by the aperture  208  to actual physical addresses within a valid address range for a block write to (or a block read front) the NVM device  204 , based at least on information provided by the host processor  101 . The NVM controller  202  can employ the media management translation table  216  for performing wear leveling operations and/or enforcing endurance limits for the NVM device  204  (e.g., an NVM device including flash memory). The NVM controller  202  can further employ the encryption component  218  for encrypting block data to be written to the NVM device  204 , as well as the decryption component  220  for decrypting block data to be read from the NVM device  204 . 
     In an exemplary mode of operation, the host processor  101  (see  FIG. 1 ) can access persistent data storable within the NVM device  204  (see  FIG. 2 ) by issuing one or more memory load/store commands to the NVM controller  202  (see  FIG. 2 ) over the memory bus  20 $ (see  FIG. 2 ). In this exemplary mode of operation, the host processor  101  can configure the NVM controller  202  for performing a block write (BW) to the NVM device  204  by translating a specified BW address within its address space to a logical SW address within the address range defined by the aperture  208  (see  FIG. 2 ). The logical BW address can be expressed in terms of a logical BW base address and a logical SW offset address. The host processor  101  can select an available aperture within the NVM controller  202  such as the aperture  208 ) by addressing the respective aperture  208  directly over the memory bus  203 . 
     Having configured the NVM controller  202  for performing the desired block write operation to the NVM device  204 , the host processor  101  can issue a memory store command over the memory bus  203  to the NVM controller  202 . The memory store command provides at least the logical SW base address and the logical SW offset address, which defines a relative offset from the logical SW base address. The host processor  101  writes the memory store command to a selected one of the plurality of command registers  0 -q, based at least on the logical BW base/offset address provided via the memory store command. In response to the memory store command issued. by the host processor  101 , the NVM controller  202  selects the memory-mapped base address register  0 ,  1 , . . . q associated with the status register/command register pair  0 , 0 ,  1 , 1 , . . . q,q that includes the selected command register  0 ,  1 , . . . q. Further, the NVM controller  202  receives block data to be written to the NVM device  204  at the relative offset from the logical SW base address within the address range of the aperture  208 . 
     The address translation component  214  (see  FIG. 2 ) within the NVM controller  202  receives the logical base address contained in the selected base address register  0 , 1 , . . . , q, receives the block data received at the relative offset from the logical  8 W base address within the address range of the aperture  208 , and translates the logical base address and the logical BW offset address to an actual physical address of a block (the block  204   a ) within the NVM device  204 . The NVM controller  202  can check the translated address to determine, whether it conforms to a valid address range for a block write to the NVM device  204 . In the event the translated address does not conform to a valid address range for a block write to the NVM device  204 , the NVM controller  202  can set an error flag in the status register  0 ,  1 , . . . , q associated with the selected command register  0 ,  1 , . . . , q. In the event the translated address conforms to a valid address range for a block write to the NVM device  204 , the NVM controller  202  is successfully configured for performing the desired block, write operation to the NVM device  204 . 
     The NVM controller  202  can employ the media management translation table  216  to perform wear-leveling operations, and to enforce endurance limits for the NVM device  204 , as desired and/or required. The NVM controller  202  can further employ the encryption component  218  to encrypt the block data to be written to the block  204   a  of the NVM device  204 , as desired and/or required. The NVM controller  202  can then write the block data to the actual physical address of the block  204   a.  At the completion of the block write to the NVM device  204 , the host processor  101  can read, over the memory bus  203 , the status register  0 ,  1 , . . . , q associated with the selected command register  0 ,  1 , . . . , q to check the error status of the block write Operation. 
     In this exemplars mode of operation, the host processor  101  (see  FIG. 1 ) can further configure the NVM controller  202  (see  FIG. 2 ) for performing a block read (BR) from Me NVM device  204  (see  FIG. 2 ) by translating a specified BR address within its address space to a logical BR address within the address range defined by the aperture  208 . The logical BR address can be expressed in terms of a logical BR base address and a logical BR offset address. As described herein with reference to the block write operation, the host processor  101  can select an available aperture within the NVM controller  202  (such as the aperture  208 ) by addressing the respective aperture  208  directly over the memory bus  203 . 
     Having configured the NVM controller  202  for performing the desired block read operation from the NVM device  204 , the host processor  101  can issue a memory load command over the memory bus  203  to the NVM controller  202 . The memory load command provides at least the logical BR base address and the logical BR offset address, which defines a relative offset from the logical BR base address. The host processor  101  writes the memory load command to a selected one of the plurality of command registers  0 -q, based at least on the logical BR base/offset address provided via the memory load command. In response to the memory load command issued by the host processor  101 , the NVM controller  202  selects the memory-mapped base address register  0 ,  1 , . . . , q associated with the status register/command register pair  0 , 0 ,  1 , 1 , . . . , q,q that includes the selected command register  0 ,  1 , . . . , q. 
     The address translation component  214  receives the logical base address from the selected base address register  0 ,  1 , . . . , q, receives the logical BR offset address provided via the memory load command, and translates the logical base address and logical BR offset address to an actual physical address of a block (e.g., the block  204   a ) within the NVM device  204 . The NVM controller  202  can check the translated address to determine whether it conforms to a valid address range for a block read from the NVM device  204 . In the event the translated address does not conform to is valid address range for a block read from the NVM device  204 , the NVM controller  202  can set an error flag in the status register  0 ,  1 , . . . , q associated with the selected command register  0 ,  1 , . . . , q. In the event the translated address conforms to a valid address range for a block read from the NVM device  204 , the NVM controller  202  is successfully configured for performing the desired block read operation from the NVM device  204 . 
     The NVM controller  202  can employ the decryption component  220  to decrypt the block data to be read from the block  204   a  of the NVM device  204 , as desired and/or required. 
     The NVM controller  202  can then read the block data from the actual physical address of the block  204   a.  At the completion of the block read from the NVM device  204 , the host processor  101  can read, over the memory bus  203 , the status register  0 ,  1 , . . . , q associated with the selected command register  0 ,  1 , . . . , q to check the error status of the block read operation. 
     By allowing the host processor  101  to access persistent data storable within the 
     NVM device  204  by issuing one or more memory load/store commands to the NVM controller  202  over the memory bus  203 , in which the NVM controller  202  includes the aperture  208  that defines an address range for accessing one or more blocks of the persistent data storable within the NVM device  204 , a computer system can advantageously exploit, with reduced latency, the full capacity of the NVM device  204  without being unduly constrained by physical addressing limits of the host processor  101 , or by limits imposed by the OS executed by the host processor  101 . 
     The operation of an NVM controller for translating one or more logical addresses within an address range defined by an aperture to actual physical addresses of one or more blocks within an NVM device will he further understood with reference to the following illustrative example and  FIG. 3 . As shown in  FIG. 3 , an NVM controller  302  can include a Monk window (aperture)  308 , a plurality of control registers  312  including a plurality of command registers  0 - 31 , a plurality of status registers  0 - 31 , and a plurality of memory-Mapped base address registers  0 - 31  containing a plurality logical base addresses, respectively, an address translation component  314 , and a media management translation table  316 . Each of the plurality of memory-mapped base address registers  0 ,  1 , . . . ,  31  corresponds to a predetermined portion of the address range defined by the aperture  308 . Further, the plurality of status registers  0 - 31  are associated with the plurality of command registers  0 - 31 , respectively, and the status register/command register pairs  0 , 0 ,  1 , 1 , . . . ,  31 , 31  are, in turn, associated with the plurality of memory-mapped base address registers  0 - 31 , respectively. 
     In this illustrative example, the aperture  308  is configured to support a block size of 256 kilobytes (KB). It is noted, however, that the aperture  308  may alternatively be configured to support a block size of 16 KB, 64 KB, 128 KB, 512 KB, 1 megabyte (MB), 2 MB, 4 MB, or any other suitable block size. Each sub-block within the block size of 256 KB is defined herein as 1/32 of the block size of 256 KB (i.e., 8 KB), or any other suitable sub-block size. Each of the plurality of memory-mapped base address registers  0 - 31  is therefore configured to correspond to 8 KB of the address range 0-256 KB) defined by the aperture  308 . Specifically, the base address register  0  is configured to contain a 0 th  logical base address covering 0-8 KB of the address range defined b the aperture  308 , the base address register  1  is configured to contain a logical base address covering 8-16 KB of the address range defined by the aperture  308 , the base address register  2  is configured to contain a 2 nd  logical base address covering 16-24 KB of the address range defined by the aperture  308 , and so on up to the base address register  31 , which is configured to contain a logical base address covering 248-256 KB of the address range defined by the aperture  308 . 
     With reference to this illustrative example, a memory load/store command issued by the host processor  101  (see  FIG. 1 ) to the NVM controller  302  (see  FIG. 3 ) over a memory bus  303  (see  FIG. 3 ) can provide a logical base address and a logical offset address for use in writing block data to or reading block data from, a block within the NVM device  204  (see  FIG. 2 ). Such a logical base address can be represented by the logical base address “X”, and therefore the address range defined by the aperture  308  can be expressed as ranging from the logical base address X to the logical address X+256 KB (see  FIG. 3 ). Further, an exemplary relative offset from the logical base address X can be expressed as “8 KB” (plus a cache line offset, if any), or an other suitable relative offset. Such a cache line can correspond to 64 bytes (B), or any other suitable number of bytes. 
     For example, the host processor  101  can configure the N \TM controller  302  for performing a block write. (BW) to the NVM device  204  by issuing an exemplary command that conforms to the following format:
         Store 0x0000 1200 0008 1000 to 0x8804 1000,
 
in which “0x0000 1200 0008 1000” corresponds to the block address that is to he accessed through the, aperture  308 , “0x8804 0000” corresponds to the base address of the command registers  0 - 31 , and “0x1000” is the offset corresponding to the command register  1 , which is associated with the base address register  1 . The host processor  101  can hen access the block address by issuing one or more memory load/store commands, specifying one or more accesses to the following:
   0x0000 0000 4800 2000,
 
in which “0x0000 0000 4800 0000” corresponds to the logical base address “X” of the aperture  308 , and “0x2000” corresponds to the 1 st  logical base a(dress contained in the base address register  1 . As noted above, in this illustrative example, the 1 st  logical base address, namely, 0x2000, covers 8-16 KB of the address range define by the aperture  308 .
       

     Accordingly, the memory load/store command issued by the host processor  101  to the NVM controller  302  over the memory bus  303  can provide a logical base/offset address that can be represented by the term “X+8 KB” (plus a cache line offset, if any), which conforms to the address range, “X” to “X+256 KB”, defined by the aperture  308 . The host processor  101  can write the memory load/store command to a selected one of the plurality or command registers  0 - 31 , e.g., the command register  1 , based at least on the logical base offset address, X+8 KB (plus a cache line offset if any), provided via the memory load/store command. 
     The address translation component  314  receives the 1 st  logical base address from the selected base address register  1 , receives an indication of the cache line offset, if any, from the aperture  308 , and translates the 1 st  logical base address and the cache line offset, if any, to the actual physical address of the block within the NVM device  204 . The NVM controller  302  can then write the block data to, or read the block data from, the actual physical address of the respective block. 
     An exemplary method of operating an NVM controller for writing block data to, or reading block data from, one or more blocks within NVM device is described below with reference to  FIG. 4 . As depicted in block  402 , a memory load/store command is received at the NVM controller over a memory bus, in which the memory load/store command includes a logical address conforming to at least a portion of an address range defined by a block window (aperture) included in the NVM controller. As depicted in block  404 , a representation of the logical address is translated to an actual physical address of the block within the NVM device. As depicted in block  406 , a determination is made as to whether the translated address conforms to a valid address range for accessing the block within the NVM device. In the event the translated address conforms to a valid address range for accessing the block within the NVM device, the block data is written to, or read from, the actual physical address of the block within the e NVM device, as depicted in block  408 . Otherwise, a status error flag is set, as depicted in block  410 , and the exemplary method of operating the NVM controller ends. 
       FIG. 5  depicts an exemplary computer system  500  that can be configured to implement apparatus and methods of the claimed invention. As shown in  FIG. 5 , the computer system.  500  can include at least one host processor  502  communicably coupled to at least one memory  504  by a system bus  514 , and communicably coupled to an NVM device controller  520  by a memory bus  515 . The computer system  500  can further include a keyboard  516  and a display  518  communicably coupled to the system bus  514 , and at least one NVM device  512  communicably coupled to the NVM device controller  520 . The NVM device controller  520  includes at least one processor  520   a  operative to execute at least one program out of at least one non-transitory storage medium, such as a memory  520   b  or any other suitable storage medium, to access persistent data storable in one or more blocks within the NVM device  512 . The host processor  502  is operative to execute instructions stored on at least one non-transitory storage medium, such as the memory  504  or any other suitable storage medium, for performing various processes within the computer system  500 , including one or more processes for controlling operations of the NVM device controller  520  The memory  504  can include one or more Memory components such as a volatile memory  510 , which may be implemented as dynamic random access memory (DRAM) or any other suitable volatile memory. The memory  504  can also be configured to store an operating system (OS)  506  executable by the host processor  502 , as well as one or more applications  508  that may be run by the OS  506 . In response to a request generated by one of the applications  508 , the host processor  502  can execute the OS  506  to perform desired data write/read operations on the volatile memory  510 , and/or desired block write/read operations on the NVM device  512  via the NVM device controller  520 . 
     It is noted that  FIG. 5  illustrates an exemplary embodiment of the computer system  500 , and that other embodiments of the computer system  500  may include more apparatus components, or fewer apparatus components, than the apparatus components illustrated in  FIG. 5 . Further, the apparatus components may be arranged differently than as illustrated in  FIG. 5 . For example, in some embodiments, the NVM device  512  may be located at a remote site accessible to the computer system  500  via the Internet or any other suitable network. In addition, functions performed by various apparatus components contained in other embodiments of the computer system  500  may be distributed among the respective components differently than as described herein. 
     Having described the above exemplary embodiments of the disclosed apparatus and methods, other alternative embodiments or variations may be made. For example, it was described herein that an NVM device controller can include at least one block window (aperture) that defines at least one address range for accessing persistent data storable in one or more blocks within an NVM device. In an alternative embodiment, such an aperture can be implemented as a block window for reading block data from the NVM device, a block window for writing block data to the NVM device, and/or a write combining buffer for writing data to the NVM device with atomic write support. 
     It was also described herein that an NVM device controller can be configured to perform a block write operation to an NVM device by translating a logical block write address within an address range defined by an aperture to an actual physical address of a block within the NVM device. In an alternative embodiment, such a block write operation can be performed to copy data from volatile in such as dynamic random access memory (DRAM) to the NVM device over a memory bus with reduced latency. 
     It was further described herein that a host processor could access persistent data storable within an NVM device by issuing one or more memory load/store commands to an NVM device controller over a memory bus. As depicted in  FIG. 6   a,  in one embodiment, such an NVM device controller  620  can include a processor  609 , as well as at least one payload data storage  608  (also referred to herein as a/the “payload mailbox”), at least one command register  510 . 1 , and at least one status register  610 . 2 , which collectively can be employed to provide a cacheable, bidirectional, memory-mapped access path between the host processor  101  (see  FIG. 1 ) and the NVM device controller  620  over a memory bus  603 . For example, the NVM device controller  620  can be incorporated in a DIMM, a double data rate (DDR) DIMM, and/or a non-volatile (NV) DIMM. In this embodiment, the host processor  101  can issue commands and access payload data and status information (e.g., the status of command execution) over the memory bus  603  via a command interface, which is implemented in the NVM device controller  620  by the command register  610 . 1  (also referred to herein as the “mailbox command register”), the status register  610 . 2  (also referred to herein as the “mailbox status register”), and at least one address range  607  (also referred to herein as the “mailbox address range”) defined by the payload mailbox  608 . The host processor  101  can issue such commands, as well as access such payload data and status information, via such a command interface using cacheable memory load/store commands issued in-band over the bidirectional access path implemented by the memory bus  603 , which is configured to support slave operations performed by the NVM device controller  620 . 
       FIG. 6 b    depicts an exemplary op-code format  660  associated with a respective memory load/store command, an exemplary write protect bit  662  associated with the respective memory load/store command, and an exemplary input payload format  664  for use by the host processor  101  (see  FIG. 1 ) in issuing the respective memory load/store command, using the mailbox command register  610 . 1  and the mailbox address range  607  of  FIG. 6   a.  As shown in  FIG. 6   b,  the op-code format  660  can include a command code  660 . 1  (e.g., memory load command, memory store command), a payload type  660 . 2  (e.g., small payload, large payload), and an interrupt type  660 . 3  (e.g., low priority, high priority). 
       FIG. 6 c    depicts an exemplary status code format  670  associated with a respective memory load/store command, and an exemplary output payload format  672  for use by the host processor  101  (see  FIG. 1 ) in monitoring completion of the execution of the respective memory load/store command, using the mailbox status register  610 . 2  and the mailbox address range  607  of  FIG. 6   a.  As shown in  FIG. 6   c,  the status code format  670  can include a status code  670 . 1  (e.g., command failure status code, command success results, error status), a command progress status  670 . 2  (e.g., command has started, command has completed, command is aborted), and a command success/failure status  670 . 3  (e.g., command was successful, command has failed, error flag). 
     An exemplary method of issuing a memory load/store command and monitoring completion of the memory load/store command, by a host processor using a mailbox, is described below with reference to  FIGS. 7 a   - 7   b,  as well as  FIGS. 6 a   - 6   c.  In one embodiment, this exemplary method may be initiated by a system management interrupt (SMI), and may therefore be implemented in a system management mode (SMM) as an OS independent mechanism. 
     As depicted in block  702  (see  FIG. 7 a   ), a determination is made, by the host processor  101 , as to whether the memory load/store command to be issued by the host processor  101  requires data (e.g., block data) to be sent to the NVM device controller  620 . In the event the memory load/store command requires data to he sent to the NVM controller  620 , such data is sent, by the host processor  101  over the memory bus  603  using the input payload format  664 , to at least a portion of the mailbox address range  607  defined by the payload mailbox  608 , as depicted in block  704 . As depicted in block  706  the memory load/store command is issued, by the host processor  101  over the memory bus  603  using the op-code format  660 , to the NVM device controller  620 , by writing the memory load/store command to the mailbox command register  610 . 1 . As further depicted in block  706 , the write protect bit  662  is set, by the host processor  101 , to conform to a predetermined logic level (e.g., the write protect bit  662  may be set to a logical high level). As depicted in block  708 , in response to the write protect hit  662  being set to a logical high level by the host processor  101 , an SMI is generated by the NVM device controller  620  and subsequently handled by the SMM of the processor  609 . For example, the SMM may be embodied as one or more basic input/output system (BIOS) services of the processor  609 . It is noted that, once the write protect bit  662  is set by the host processor  101 , the NVM device controller  620  write-protects one or more registers for the input payload from being further written to by the host processor  101 . 
     While the NVM device controller  620  executes the memory load/store command, the input payload is copied by the NVM device controller  620  to its internal memory, the mailbox status register  610 . 2  is updated by the NVM device controller  620  using the status code format  670  to indicate that the input payload is being processed (e.g., the command progress status  670 . 2  indicates that the command has started), and the write protect bit  662  is cleared by the NVM device controller  620 , as depicted in block  710 . It is noted that, once the write protect bit  662  is cleared by the NVM device controller  620 . the input payload register(s) are no longer write-protected from being written to by the host processor  101 , thereby allowing the host processor  101  to issue another command, over the memory bus  603  to the NNW device controller  620  using the op-code format  660 , before the execution of the current command has completed. 
     As depicted in block  712 , the status of the execution of the memory load/store command is monitored by the host processor  101  by reading the mailbox status register  610 . 2 , using the status code format  670 . In the event the mailbox status register  610 . 2  has been updated by the NVM device controller  620  to indicate that the execution of the memory load/store command has completed (e.g., the command progress status  670 . 2  indicates that the command has completed), a determination is made, by the host processor  101  using the output payload format  672 , as to whether the memory load/store command requires data (e.g., block data) to be accessed from the NVM device  204  via the NVM device controller  620 , as depicted in block  714 . In the event the memory load/store command requires data to be accessed by the host processor  101  via the NVM device controller  620 , such data is accessed, by the host processor  101  over the memory bus  603  using the output payload format  672 , from at least a portion of the mailbox address range  607  defined by the payload mailbox  608 , as depicted in block  716 . As depicted in block  718 , a determination is made, by the host processor  101 , as to whether the execution of the memory load/store command has completed successfully (e.g., the command progress status  670 . 2  indicates that the command was successful). In the event the memory load/store command has completed successfully, the data accessed using the output payload format  672  is processed by the host processor  101 , as depicted in block  720 . As depicted in block  722 , upon completion of the processing of the data by the host processor  101 , the processor  609  within the NVM device controller  620  exits the SMM. 
     Although illustrative examples of various embodiments of the disclosed subject matter are described, herein, one of ordinary skill in the relevant art will appreciate that other manners of implementing the disclosed subject matter may alternatively be used. In the preceding description, various aspects of the disclosed subject matter have been described. For purposes of explanation, specific systems, apparatus, methods, and configurations were set forth in order to provide a thorough understanding of the disclosed subject matter. However, it will be apparent to one skilled in the relevant art having the benefit of this disclosure that the subject matter may he practiced without the specific details described herein. In other instances, well-known features, components, and/or modules were omitted, simplified, or combined in order not to obscure the disclosed subject matter. 
     It is noted that the term “operative to”, as employed herein, means that a corresponding device, system, apparatus, etc., is able to operate, or is adapted to operate, for its desired functionality when the device, system, or apparatus is in its powered-on state. Moreover, various embodiments of the disclosed subject matter may be implemented in hardware, firmware, software, or some combination thereof, and may be described by reference to, or in conjunction with, program code such as instructions, functions, procedures, data structures, logic, application programs, design representations, and/or formats for simulation, emulation, and/or fabrication of a design, which when accessed by a machine results in the machine performing tasks, defining abstract data types or low-level hardware contexts, or producing a result. 
     It is further noted that the techniques illustrated in the drawing figures can be implemented using code and/or data. stored and/or executed on one or more computing de ices, such as general-purpose computers or computing devices. Such computers or computing devices store and communicate code and/or data (internally and/or with other computing devices over a network) using machine-readable media such as machine readable storage media (e.g., magnetic disks, optical disks, random access memory (RAM), read only memory (ROM), flash memory devices, phase-change memory) and machine readable communication media (e.g., electrical, optical, acoustical, or other form of propagated signals such as carrier waves, infrared signals, digital signals, etc.). 
     No element, operation, or instruction employed herein should be construed as critical or essential to the application unless explicitly described as such. Also, as employed herein, the article “a” is intended to include one or more items. Where only one item is intended, the term “one” or similar language is employed. Further, the phrase “based on” is intended to mean “based, at least in part, on” unless explicitly stated otherwise. 
     It is intended that the invention not be limited to the particular embodiments disclosed herein, but that the invention will include any and all particular embodiments and equivalents falling within the scope of the following appended claims.