Patent Publication Number: US-2023154830-A1

Title: Semiconductor device and method of forming the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation-in-part (CIP) application of and claims the priority benefit of U.S. application Ser. No. 17/687,688, filed Mar. 7, 2022, entitled “Package Structure and Method of Forming the Same,” which is a continuation application of U.S. application Ser. No. 16/547,590, filed on Aug. 22, 2019, entitled “Package Structure and Method of Forming the Same,” now U.S. Pat. No. 11,270,927, issued Mar. 8, 2022. This application further claims priority to U.S. Provisional Application No. 63/370,716, filed Aug. 8, 2022, entitled “Package with Adhesion Promoter (AP) and Method of Fabricating the Same.” The entirety of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
    
    
     BACKGROUND 
     The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from continuous reductions in minimum feature size, which allows more of the smaller components to be integrated into a given area. These smaller electronic components also demand smaller packages that utilize less area than previous packages. Some smaller types of packages for semiconductor components include quad flat packages (QFPs), pin grid array (PGA) packages, ball grid array (BGA) packages, flip chips (FC), three-dimensional integrated circuits (3DICs), wafer level packages (WLPs), and package on package (PoP) devices and so on. 
     Currently, integrated fan-out packages are becoming increasingly popular for their compactness. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1 A  to  FIG.  1 M  are schematic cross-sectional view illustrating a method of forming a package structure according to some embodiments of the disclosure. 
         FIG.  2 A  to  FIG.  2 C  are enlarged cross-sectional views illustrating a portion of the package structure according to some embodiments of the disclosure. 
         FIG.  3 A  to  FIG.  3 C  are enlarged cross-sectional views illustrating a portion of the package structure according to some embodiments of the disclosure. 
         FIG.  4    is a flowchart illustrating a method of forming an adhesion promoter layer on a TIV according to some embodiments of the disclosure. 
         FIG.  5 A  to  FIG.  5 I  are schematic cross-sectional view illustrating a method of forming a package structure according to some embodiments of the disclosure. 
         FIG.  6 A  to  FIG.  6 C  are enlarged cross-sectional views illustrating a portion of the package structure according to some embodiments of the disclosure. 
         FIG.  7 A  to  FIG.  7 C  are enlarged cross-sectional views illustrating a portion of the package structure according to some embodiments of the disclosure. 
         FIG.  8    is an enlarged cross-sectional view illustrating a portion of the package structure according to some embodiments of the disclosure. 
         FIG.  9 A  and  FIG.  9 B  are enlarged cross-sectional views illustrating a portion of the package structure according to some embodiments of the disclosure. 
         FIG.  10 A  to  FIG.  10 C  are enlarged cross-sectional views illustrating a portion of the package structure according to some embodiments of the disclosure. 
         FIG.  11    is a flowchart illustrating a method of forming an adhesion promoter layer on a conductive pattern according to some embodiments of the disclosure. 
         FIG.  12    illustrates a manufacturing method of a semiconductor device in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. 
       FIG.  1 A  to  FIG.  1 M  are schematic cross-sectional views illustrating a method of forming a package structure and a PoP device according to some embodiments of the disclosure.  FIG.  2 A  to  FIG.  2 C  are enlarged cross-sectional views illustrating a polymer layer, a TIV, an adhesion promoter layer and an encapsulant of a package structure. 
     Referring to  FIG.  1 A , a carrier  10  is provided. The carrier  10  may be a glass carrier, a ceramic carrier, or the like. A de-bonding layer  11  is formed on the carrier  10  by, for example, a spin coating method. In some embodiments, the de-bonding layer  11  may be formed of an adhesive such as an Ultra-Violet (UV) glue, a Light-to-Heat Conversion (LTHC) glue, or the like, or other types of adhesives. The de-bonding layer  11  is decomposable under the heat of light to thereby release the carrier  10  from the overlying structures that will be formed in subsequent steps. 
     A polymer layer  12  is formed on the de-bonding layer  11 . The polymer layer  12  includes, for example, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), Ajinomoto Buildup Film (ABF), or the like or combinations thereof. The polymer layer  12  is formed by a suitable fabrication technique such as spin-coating, lamination, deposition, or the like. 
     Still referring to  FIG.  1 A , a plurality of through integrated fan-out vias (TIVs)  15  are formed on the polymer layer  12 . In some embodiments, the TIV  15  includes a seed layer  13  and a conductive post  14  on the seed layer  13 . The seed layer  13  is a metal seed layer such as a copper seed layer. For example, the seed layer  13  may include titanium, copper, the like, or a combination thereof. In some embodiments, the seed layer includes a first seed layer  13   a  and a second seed layer  13   b  over the first seed layer  13   a  ( FIG.  2 A ). The first seed layer  13   a  and the second seed layer  13   b  may include different materials. For example, the first seed layer is a titanium layer, and the second seed layer is a copper layer. In some embodiments, the conductive post  14  include a material the same as the second seed layer  13   b  and different from the first seed layer  13   a . The conductive post  14  includes a suitable metal, such as copper. However, the disclosure is not limited thereto. The sidewalls of the conductive posts  14  may be substantially aligned with the sidewalls of the seed layer  13 . The sidewalls of the TIVs  15  may be substantially straight, inclined, arced or the like. 
     The TIVs  15  may be formed by the following processes: a seed material layer is formed on the polymer layer  12  by a physical vapor deposition (PVD) process such as sputtering. A patterned mask layer is then formed on the seed material layer, the patterned mask layer has a plurality of openings exposing a portion of the seed material layer at the intended locations for the subsequently formed TIVs  15 . Thereafter, the conductive posts  14  are formed on the seed material layer within the openings by a plating process, such as electroplating. Thereafter, the patterned mask layer is stripped by an ashing process, for example. The seed material layer not covered by the conductive posts  14  is removed by an etching process using the conductive posts  14  as the etching mask. As such, the seed layers  13  underlying the conductive posts  14  are remained, the seed layer  13  and the conductive post  14  constitute the TIV  15 . 
     Referring to  FIG.  1 B , in some embodiments, adhesion promoter material layers  18  are formed on the TIVs  15  to cover the top surfaces and sidewalls of the TIVs  15 . The adhesion promoter material layer  18  may include a metal chelate compound, such as copper chelate. The metal chelate compound included in the adhesion promoter material layer  18  is corresponding to the metal included in the TIV  15 . That is, the adhesion promoter material layer  18  and the TIV  15  include a same metal element. In some embodiments, the adhesion promoter material layer  18  may be formed by conducting a chelation reaction between a chelating agent and the TIV  15 . 
     Referring to  FIG.  1 B  and  FIG.  4   , for example, the adhesion promoter material layers  18  may be formed by the following processes: after the TIVs  15  are formed, in step S 10 , a pre-cleaning process is performed on the TIVs  15  to clean the surfaces of the TIVs  15 . The detergent used in the pre-cleaning process may include an acid such as citric acid (CX-100), hydrochloric acid, sulfuric acid, acetic acid, or the like or combinations thereof. The pre-cleaning process may be performed at room temperature for 5 seconds to 10 minutes, such as 1 minute, for example, but the disclosure is not limited thereto. The pre-cleaning process may remove undesired substance on the surface of the TIVs  15 , such as impurities or metal oxide. In some embodiments, after the TIV  15  is formed, the metal included in the TIV  15  may be oxidized when exposed to moisture or air for a period of time, and metal oxide such as copper oxide may be formed on the surface of the TIV  15 . In the embodiments in which the surface of the TIV  15  is oxidized, the metal oxide on the surface of the TIV  15  is removed by the pre-cleaning process. 
     Thereafter, in step S 20 , a first cleaning process is further performed to clean the surfaces of the TIVs  15 . In some embodiments, the first cleaning process may remove the remnant generated from the pre-cleaning process, such as the reaction product of the detergent and the metal oxide, the remained detergent, impurities, or combinations thereof. The first cleaning process may be a deionized water rinsing process, and may be performed for 5 seconds to 10 minutes, such as 1 minute, for example. However, the disclosure is not limited thereto. 
     After the first cleaning process is performed, in step S 30 , a drying process is performed to dry the surfaces of the TIVs  15 . In some embodiments, the structure shown in  FIG.  1 B  is placed in a drying apparatus, and the drying process is performed by introducing an inert gas such as dry nitrogen gas into the drying apparatus, so as to dry the surfaces of the TIVs  15  and also prevent the TIVs  15  from being oxidized again. In some embodiments, the drying process is performed at room temperature for 5 seconds to 10 minutes, such as 1 minute, for example. 
     Afterwards, in step S 40 , a treatment process is performed on the TIVs  15  by applying a treatment agent on the TIVs  15  (step S 41 ) and conducting a reaction (such as a chelating reaction) between the TIVs  15  and the treatment agent (step S 42 ). The method of applying the treatment agent may include dipping, spraying, spin coating, the like, or combinations thereof. The treatment process may be performed at a temperature ranging from room temperature to 80° C. or at 40° C. In some embodiments, the treatment process is performed in an alkaline environment, a weak acid environment or a neutral pH environment, but the disclosure is not limited thereto. For example, the pH of the treatment agent may be in a range of 5 to 12 or 8 to 12. The treatment agent includes a chelating agent, and the concentration of the chelating agent may range from 0.01 wt % to 100 wt %. In some embodiments, the chelating agent includes chelating ligands capable of forming coordination bond with the metal (such as copper) of the TIVs  15 . For example, the ligand atom of the chelating ligand may include N, O, S, or combinations thereof. 
     In some embodiments, the chelating agent may be represented by the following general formulas (I): 
     
       
         
         
             
             
         
       
     
     In the formula (I), A may include a monocyclic ring such as a mono-heterocyclic ring, a bicyclic ring, a tricyclic ring, a tetracyclic ring, or the like, and each ring may be a five-membered ring or a six-membered ring. In some embodiments, A includes conjugated double bonds. In some embodiments, A includes one or more heterocyclic rings such as aromatic heterocyclic rings. The heterocyclic ring may be mono-heterocyclic ring or fused heterocyclic ring. The heterocyclic ring includes heteroatoms such as N, S, O or combinations thereof. However, the disclosure is not limited thereto. 
     In some embodiments, the general formula (I) may include the following formulas (II)-(XII), for example. 
     
       
         
         
             
             
         
       
       
         
         
             
             
         
       
     
     In the above formulas, the functional groups X, Y, Z may be the same as or different from each other. X may be —CH, —CR′, —NH, —NR′, —S, —O, respectively. Y and Z may be —CH 3 , —CR′, —NH 2 , —RNH 2 , —NHR′, —RNHR′, —SH, —RSH, —SR′, —RSR′, —OH, —ROH, —OR′, —R—OR′, respectively. In each formula, Y and Z may be the same as or different from each other. R may be a carbon chain, and the carbon chain may be a linear side chain 
     
       
         
         
             
             
         
       
     
     or a branch side chain such as 
     
       
         
         
             
             
         
       
     
     Still referring to  FIG.  1 B , during the treatment process, a chelating reaction is conducted between the metal of TIVs  15  and the chelating agent, and a metal chelate compound (that is, the adhesion promoter material layer  18 ) is formed on the surfaces of the TIVs  15 . During the chelating reaction, metal atoms or metal cations on the surface of or diffused from the TIVs  15  chelates with the chelating agent, and coordinate bonds are formed between the metal atoms or cations and the chelating ligands of the chelating agent. In some embodiments in which the TIV  15  includes copper, the metal cations may be Cu +  or Cu 2+ . In some embodiments, the coordination bonds may be formed between the respective metal atom or cation and the same or different types of chelating ligands of the chelating agent. 
     Referring to  FIG.  1 B , in some embodiments, the chelating agent has a specific affinity for the metal included in TIV  15 , and only reacts with the TIV  15  without reacting with the polymer layer  12 . Therefore, the adhesion promoter material layer  18  is selectively formed on the surfaces of the TIVs  15  by the treatment process. 
     In some embodiments, the duration of the treatment process may range from 5 seconds to 10 minutes, for example. However, the disclosure is not limited thereto. The duration of the treatment process may be adjusted depending on the required thickness of the adhesion promoter material layer  18  according to product design. In some embodiments, the thickness of the adhesion promoter material layer  18  increases as the duration of the treatment process increases. The thickness increase rate of the adhesion promoter material layer  18  may be reduced over time. It is because as the thickness of the adhesion promoter material layer  18  increases, the time required for metal cations to diffuse outside the metal chelate to react with the chelating agent increases. 
     In some embodiments, as illustrated in step S 50  of  FIG.  4   , a second cleaning process is then performed to clean the surfaces of the adhesion promoter material layers  18 . The second cleaning process may be a deionized water rinsing process, and may be performed for 5 seconds to 10 minutes, such as 1 minute. Thereafter, in step S 60 , a drying process may be performed to dry the surface of the adhesion promoter material layer  18 . The drying process may be performed using dry air. In some embodiments, the drying process is performed at room temperature for 5 seconds to 10 minutes, such as 1 minute, for example. As such, the formation of the adhesion promoter material layer  18  is thus completed. 
     Referring to  FIG.  1 B  and  FIG.  2 A , in some embodiments, the sidewalls and top surfaces of the conductive post  14  are covered, such as completely covered by the adhesion promoter material layer  18 . The sidewalls of the seed layer  13  may be partially covered or completely covered by the adhesion promoter material layer  18 . In some embodiments in which the seed layer  13  includes first and second seed layers  13   a  and  13   b , and the conductive post  14  and the second seed layer  13   b  includes the same metal such as copper, and the first seed layer  13   a  include a metal (such as titanium) different from the second seed layer  13   b , the chelating agent may react with the copper included in the conductive post  14  and the second seed layer  13   b  without reacting with titanium included in the first seed layer  13   a . In some embodiments, the metal chelate produced by the chelating reaction is formed on and cover the sidewalls of the conductive post  14  and the second seed layer  13   b  and may further extend to (partially or completely) cover the sidewalls of the first seed layer  13   a . In other words, the adhesion promoter material layer  18  is in physical contact with the first seed layer  13   a , the second seed layer  13   b  and the conductive post  14  of the TIV  15 . Chemical bonds such as coordination bonds are formed between the second seed layer  13   b  and the adhesion promoter material layer  18 , and between the conductive post  14  and the adhesion promoter material layer  18 , while no chemical bond is formed between the first seed layer  13   a  and the adhesion promoter material layer  18 . 
     Referring to  FIG.  1 C , a die  25  is mounted on the polymer layer  12  by pick and place processes. In some embodiments, the die  25  is attached to the polymer layer  12  through an adhesive layer  19  such as a die attach film (DAF), silver paste, or the like. In some embodiments, the die  25  is one of a plurality of dies cut apart from a wafer, for example. The die  25  may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip or a memory (such as DRAM) chip. The number of the die  25  shown in  FIG.  1 C  is merely for illustration, and the disclosure is not limited thereto. In some embodiments, two or more dies  25  may be disposed side by side on the polymer layer  12  over the carrier  10 , and the two or more dies  25  may be the same types of dies or the different types of dies. 
     Still referring to  FIG.  1 C , the die  25  is disposed on the polymer layer  12  and laterally between the TIVs  15 , that is, the TIVs  15  are laterally aside or around the die  25 . In some embodiments, the die  25  includes a substrate  20 , a plurality of pads  21 , a passivation layer  22 , a plurality of connectors  23  and a passivation layer  24 . In some embodiments, the substrate  20  is made of silicon or other semiconductor materials. Alternatively or additionally, the substrate  20  includes other elementary semiconductor materials such as germanium, gallium arsenic, or other suitable semiconductor materials. In some embodiments, the substrate  20  may further include other features such as various doped regions, a buried layer, and/or an epitaxy layer. Moreover, in some embodiments, the substrate  20  is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Furthermore, the substrate  20  may be a semiconductor on insulator such as silicon on insulator (SOI) or silicon on sapphire. 
     In some embodiments, a plurality of devices are formed in or on the substrate  20 . The devices may be active devices, passive devices, or combinations thereof. In some embodiments, the devices are integrated circuit devices. The devices are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or the like, or combinations thereof. 
     In some embodiments, an interconnection structure and a dielectric structure are formed over the devices on the substrate  20 . The interconnection structure is formed in the dielectric structure and connected to different devices to form a functional circuit. In some embodiments, the dielectric structure includes an inter-layer dielectric layer (ILD) and one or more inter-metal dielectric layers (IMD). In some embodiments, the interconnection structure includes multiple layers of metal lines and plugs (not shown). The metal lines and plugs include conductive materials, such as metal, metal alloy or a combination thereof. For example, the conductive material may include tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or combinations thereof. The plugs include contact plugs and via plugs. The contact plugs are located in the ILD to be connected to the metal lines and the devices. The via plugs are located in the IMD to be connected to the metal lines in different layers. 
     The pads  21  may be or electrically connected to a top conductive feature of the interconnection structure, and further electrically connected to the devices formed on the substrate  20  through the interconnection structure. The material of the pads  21  may include metal or metal alloy, such as aluminum, copper, nickel, or alloys thereof. 
     The passivation layer  22  is formed over the substrate  20  and covers a portion of the pads  21 . Another portion of the pads  21  is exposed by the passivation layer  22  and serves as an external connection of the die  25 . The connectors  23  are formed on and electrically connected to the pads  21  not covered by the passivation layer  22 . The connector  23  includes solder bumps, gold bumps, copper bumps, copper posts, copper pillars, or the like. The passivation layer  24  is formed over the passivation layer  22  and laterally aside the connectors  23  to cover the sidewalls of the connectors  23 . The passivation layers  22  and  24  respectively include an insulating material such as silicon oxide, silicon nitride, polymer, or a combination thereof. The polymer may include polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), the like, or combinations thereof. The materials of the passivation layer  22  and the passivation layer  24  may be the same or different. In some embodiments, the top surface of the passivation layer  24  and the top surfaces of the connectors  23  are substantially coplanar with each other. 
     Referring to  FIG.  1 D , an encapsulant material layer  28  is then formed over the carrier  10  to encapsulate the die  25 , the TIVs  15  and the adhesion promoter material layer  18 . Specifically, the encapsulant material layer  28  is formed on the polymer layer  12 , encapsulating sidewalls and top surfaces of the die  30 , sidewalls and top surfaces of the adhesion promoter material layer  18 . The adhesion promoter material layer  18  is sandwiched between the TIVs  15  and the encapsulant material layer  28 . In some embodiments, the adhesion promoter material layer  18  includes a functional group (such as the functional group X, Y, Z in the above formulas) which may react with the encapsulant material layer  28 , and chemical bonds may be formed between the adhesion promoter material layer  18  and the encapsulant material layer  28 . 
     In some embodiments, the encapsulant material layer  28  includes a molding compound, a molding underfill, a resin such as epoxy, a combination thereof, or the like. In some other embodiments, the encapsulant material layer  28  includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like, which may be easily patterned by exposure and development processes or laser drilling process. In alternative embodiments, the encapsulant material layer  28  includes nitride such as silicon nitride, oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like. 
     In some embodiments, the encapsulant material layer  28  includes a composite material including a base material (such as polymer) and a plurality of fillers distributed in the base material. The filler may be a single element, a compound such as nitride, oxide, or a combination thereof. The fillers may include silicon oxide, aluminum oxide, boron nitride, alumina, silica, or the like, for example. In some embodiments, the fillers may be spherical fillers, but the disclosure is not limited thereto. The cross-section shape of the filler may be circle, oval, or any other shape. In some embodiments, the encapsulant material layer  28  is formed by a suitable fabrication technique such as molding, spin-coating, lamination, deposition, or similar processes. 
     Referring to  FIG.  1 E , in some embodiments, a planarization process is performed to remove a portion of the encapsulant material layer  28  over the top surfaces of the die  25  and the TIVs  15  and portions of the adhesion promoter material layers  18  on the top surfaces of the TIVs  15 , such that the top surfaces of the connectors  23  of the die  25  and the top surfaces of the TIVs  15  are exposed. The planarization process includes a grinding or polishing process such as a chemical mechanical polishing (CMP) process. 
     Still referring to  FIG.  1 E , after the planarization process is performed, a plurality of adhesion promoter layers  18   a  and an encapsulant  28   a  are formed. The adhesion promoter layers  18   a  are located on the polymer layer  12  and laterally aside the TIVs  15 , surrounding the sidewalls of the TIVs  15 . The encapsulant  28   a  is located on the polymer layer  12  and laterally aside the die  25 , the adhesion promoter layer  18   a  and the TIVs  15 , encapsulating sidewalls of the die  25 , sidewalls of the adhesion promoter layer  18   a  and sidewalls of the TIVs  15 . The adhesion promoter layer  18   a  is sandwiched between and in physical contact with the TIV  15  and the encapsulant  28   a . In other word, the encapsulant  28   a  is not in direct physical contact with the TIV  15 , and separated from the TIV  15  by the adhesion promoter layer  18   a  therebetween. In some embodiments, the top surface of the die  25 , the top surfaces of the TIVs  15 , the top surface of the adhesion promoter layer  18   a  and the top surface of the encapsulant  28   a  are substantially coplanar with each other. 
     Referring to  FIG.  1 F , a redistribution layer (RDL) structure  32  is formed on the die  25 , the TIVs  15 , and the encapsulant  28   a . The RDL structure  32  is electrically connected to the die  25  and the TIVs  15 . In some embodiments, the RDL structure  32  is referred to as a front-side RDL structure of the die  30 . Through the specification, wherein the “front-side” refers to a side close to the connectors of the die. 
     In some embodiments, the RDL structure  32  includes a plurality of polymer layers PM 1 , PM 2  and PM 3  and a plurality of redistribution layers RDL 1  and RDL 2  stacked alternately. The number of the polymer layers or the redistribution layers shown in  FIG.  1 F  is merely for illustration, and the disclosure is not limited thereto. 
     The redistribution layer RDL 1  penetrates through the polymer layer PM 1  and is electrically connected to the connectors  23  of the die  25  and the TIVs  15 . The redistribution layer RDL 2  penetrates through the polymer layer PM 2  and is electrically connected to the redistribution layer RDL 1 . The polymer layer PM 3  is located on and covers the polymer layer PM 2  and the redistribution layer RLD 2 . 
     In some embodiments, each of the polymer layers PM 1 , PM 2 , and PM 3  includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. In some embodiments, each of the redistribution layers RDL 1  and RDL 2  includes conductive materials. The conductive materials includes metal such as copper, aluminum, nickel, titanium, alloys thereof, a combination thereof or the like, and is formed by a physical vapor deposition (PVD) process such as sputtering, a plating process such as electroplating, or a combination thereof. In some embodiments, the redistribution layers RDL 1  and RDL 2  include a seed layer SL and a conductive layer CL formed thereon, respectively. The seed layer SL may be a metal seed layer such as a copper seed layer. In some embodiments, the seed layer includes a first seed layer such as a titanium layer and a second seed layer such as a copper layer over the first seed layer. The metal layer may be copper or other suitable metals. 
     In some embodiments, the redistribution layers RDL 1  and RDL 2  respectively includes a plurality of vias V and a plurality of traces T connected to each other. The vias V are embedded in and penetrate through the polymer layers PM 1  and PM 2 , to connect the traces T of the redistribution layers RDL 1  and RDL 2 , and the traces T are located on the polymer layers PM 1  and PM 2 , and are extending on the top surface of the polymer layers PM 1  and PM 2 , respectively. 
     Still referring to  FIG.  1 F , in some embodiments, the polymer layer PM 3  is patterned to form a plurality of openings  34 . The openings  34  expose a portion of the top surface of the redistribution layer RDL 2 . In some embodiments, conductive terminals may be formed on the redistribution layer RDL 2  exposed by the openings  34 , but the disclosure is not limited thereto. In alternative embodiments, a plurality of TIVs may be formed on the redistribution layer RDL 2 , and one or more dies may further be stacked on the RDL structure  32 . 
     Referring to  FIG.  1 G , in some embodiments, a plurality of the TIVs  37  are formed on the redistribution layer RDL 2  exposed by the openings  34  of the polymer layer PM 3 . The TIV  37  includes a seed layer  35  and a conductive post  36  on the seed layer  35 . The materials and forming method of the TIV  37  are similar to, and may be the same as or different from those of the TIV  15 . In some embodiments, the seed layer  35  is a metal seed layer such as a copper seed layer. For example, the seed layer  35  may include titanium, copper, the like, or a combination thereof. In some embodiments, the seed layer  35  includes a first seed layer  35   a  such as a titanium layer and a second seed layer  35   b  such as a copper layer over the first seed layer  35   a  ( FIG.  2 B ). The conductive post  36  includes a suitable metal, such as copper. The seed layer  35  covers the surface of the opening  34  and a portion of the top surface of the polymer layer PM 3 . The conductive post  36  covers the surface of the seed layer  35 , filling the opening  34  and protruding from the top surface of the polymer layer PM 3 . It is noted that, the number of the TIVs  37  shown in  FIG.  1 G  is merely for illustration, and the disclosure is not limited thereto. 
     Referring to  FIG.  1 H , an adhesion promoter material layer  38  is then formed to cover the sidewalls and top surfaces of the TIVs  37 . In some embodiments, the adhesion promoter material layer  38  includes a metal chelate, such as copper chelate. The forming method of the adhesion promoter material layer  38  is similar to, and may be substantially the same as or different form that of the adhesion promoter material layer  18 , which is not described again here. 
     The adhesion promoter material layer  38  covers the sidewalls and the top surface of the conductive post  36 , and the sidewalls of the seed layer  35  on the top surface of the polymer layer PM 3 . 
     Referring to  FIG.  1 I , a die  45  is mounted on the polymer layer PM 3  of the RDL structure  32  by pick and place processes. In some embodiments, the die  45  is attached to the polymer layer PM 3  through an adhesive layer  39  such as a die attach film (DAF), silver paste, or the like. The die  45  may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip or a memory chips. The number of the die  45  shown in  FIG.  1 I  is merely for illustration, and the disclosure is not limited thereto. In some embodiments, two or more dies  45  may be mounted on the polymer layer PM 3  of the RDL structure  32 , and the two or more dies  45  may be the same types of dies or the different types of dies. The die  45  and the die  25  may be the same types of dies or different types of dies. The structure of the die  45  is similar to, and may be the same as or different from the structure of the die  25 . 
     In some embodiments, the die  45  includes a substrate  40 , a plurality of pads  41 , a passivation layer  42 , a plurality of connectors  43  and a passivation layer  44 . The materials, forming method, and structural features of the substrate  40 , the pads  41 , the passivation layer  42 , the connectors  43  and the passivation layer  44  of the die  45  are substantially the same as those of the die  25 , which are not described again here. 
     Still referring to  FIG.  1 I , an encapsulant material layer  48  is then formed on the RDL structure  32  to encapsulant sidewalls and top surfaces of the die  45 , the TIVs  37  and the adhesion promoter material layer  38 . The material and forming method of the encapsulant material layer  48  are similar to, and may be the same as or different from those of the encapsulant material layer  28  ( FIG.  1 D ). 
     Referring to  FIG.  1 J , in some embodiments, a planarization process is then performed to expose the top surfaces of the connectors  43  of the die  45  and top surfaces of the TIVs  37 . The planarization process may include a grinding or polishing process such as a CMP process. In some embodiments, a portion of the encapsulant material layer  48  over the top surfaces of the die  45  and the TIVs  37  and portions of the adhesion promoter material layer  38  on the top surfaces of the TIVs  37  are removed by the planarization process, and an encapsulant  48   a  and an adhesion promoter layer  38   a  are remained. In some embodiments, after the planarization process is performed, the top surface of the die  45 , the top surfaces of the TIVs  37 , the top surfaces of the adhesion promoter layers  38   a  and the top surface of the encapsulant  48   a  are substantially coplanar with each other. 
     Referring to  FIG.  1 K , a RDL structure  52  is then formed on the die  45 , the TIVs  37  and the encapsulant  48   a . The RDL structure  52  is electrically connected to the die  45  and the TIVs  37 . In some embodiments, the RDL structure  52  includes a plurality of polymer layers PM 10 , PM 20 , PM 30  and PM 40 , and a plurality of redistribution layers RDL 10 , RDL 20 , RDL 30  and RDL 40  stacked alternately. The number of the polymer layers or the redistribution layers shown in  FIG.  1 K  is merely for illustration, and the disclosure is not limited thereto. The materials and forming method of the polymer layers and redistribution layers of the RDL structure  52  are similar to, and may be the same as or different from those of the RDL structure  32 . 
     The redistribution layer RDL 10  penetrates through the polymer layer PM 10  and is electrically connected to the connectors  43  of the die  45  and the TIVs  37 . The redistribution layer RDL 20  penetrates through the polymer layer PM 20  and is electrically connected to the redistribution layer RDL 10 . The redistribution layer RDL 30  penetrates through the polymer layer PM 30  and is electrically connected to the redistribution layer RDL 20 . The redistribution layer RDL 40  penetrates through the polymer layer PM 40  and is electrically connected to the redistribution layer RDL 30 . 
     In some embodiments, similar to the redistribution layers RDL 1  and RDL 2 , the redistribution layers RDL 10 , RDL 20 , RDL 30 , and RDL 40  include a seed layer SL and a conductive layer CL formed thereon, respectively. In some embodiments, the redistribution layers RDL 10 , RDL 20 , RDL 30  respectively includes a plurality of vias V and a plurality of traces T connected to each other. The vias V are embedded in and penetrate through the polymer layers PM 10 , PM 20 , PM 30 , to connect the traces T of the redistribution layers RDL 10 , RDL 20 , RDL 30 , the traces T are located on the polymer layers PM 10 , PM 20 , PM 30 , and are extending on the top surface of the polymer layers PM 10 , PM 20 , PM 30 , respectively. 
     In some embodiments, the redistribution layer RDL 40  is the topmost redistribution layer of the RDL structure  52 , and is referred to as under-ball metallurgy (UBM) layer for ball mounting. 
     Still referring to  FIG.  1 K , a plurality of connectors  56  are formed over and electrically connected to the redistribution layer RDL 40  of the RDL structure  52 . In some embodiments, the connectors  56  are referred as conductive terminals. In some embodiments, the connectors  56  may be ball grid array (BGA) connectors, solder balls, controlled collapse chip connection (C4) bumps, or a combination thereof. In some embodiments, the material of the connector  56  includes copper, aluminum, lead-free alloys (e.g., gold, tin, silver, aluminum, or copper alloys) or lead alloys (e.g., lead-tin alloys). The connector  56  may be formed by a suitable process such as evaporation, plating, ball dropping, screen printing and reflow process, a ball mounting process or a C4 process. In some embodiments, metal posts or metal pillars (not shown) may further be formed between the redistribution layer RDL 40  and the connectors  56 , but the disclosure is not limited thereto. The connectors  56  are electrically connected to the connectors  43  of the die  45  and the TIVs  37  through the RDL structure  52 , and further electrically connected to the connectors  23  of the die  25  and the TIVs  15  through the RDL structure  32 . 
     Referring to  FIG.  1 K  and  FIG.  1 L , in some embodiments, the de-bonding layer  11  is decomposed under the heat of light, and the carrier  10  is then released from the overlying structure, and a package structure  100   a  is thus formed. In some embodiments, the package structure  100   a  may further be coupled to other package structures to form a package on package (PoP) device. 
     Referring to  FIG.  1 L  and  FIG.  1 M , portions of the polymer layer  12  may be removed by a laser drilling process to form openings OP in the polymer layer  12 . The openings OP expose portions of the bottom surfaces of TIVs  15 . Thereafter, the package structure  100   a  is electrically connected to a package structure  200  to form a PoP device  300  through a plurality of connectors  54 . The connectors  54  fill in the openings OP and are electrically connected to the TIVs  15 . The package structure  100   a  and the package structure  200  may include the same types of devices or the different types of devices. The package structure  200  may include active devices, passive devices, or combinations thereof. In some embodiments, the package structure  200  is a memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), or other type of memory. In some embodiments, an underfill layer UF may further be formed to fill the space between the package structure  100   a  and the package structure  200  and surround the connectors  54 . 
     Referring to  FIG.  1 L , in some embodiments, the package structure  100   a  includes the polymer layer  12 , the die  25 , the TIVs  15 , the adhesion promoter layers  18   a , the encapsulant  28   a , the RDL structure  32 , the die  45 , the TIVs  37 , the adhesion promoter layers  38   a , the encapsulant  48   a , the RDL structure  52  and the connectors  56 . The die  25  and the die  45  are electrically connected to each other through the RDL structure  32 , the TIVs  37  and the RDL structure  52 . In some embodiments, the polymer layer  12  is disposed on back side of the die  25 , the RDL structure  32  is disposed on front side of the die  25  and on back side of the die  45 , and the RDL structure  52  is disposed on the front side of the die  45 . 
     The TIVs  15  are laterally aside the die  25 , and the encapsulant  28   a  are laterally aside the die  25  and the TIVs  15 , encapsulating sidewalls of the die  25  and sidewalls of the TIVs  15 . In some embodiments, the adhesion promoter layers  18   a  are sandwiched between and in physical contact with the TIVs  15  and the encapsulant  28   a . In other words, the sidewalls of the TIVs  15  are covered by the adhesion promoter layers  18   a , and separated from the encapsulant  28   a  by the adhesion promoter layer  18   a  therebetween. The sidewalls of the adhesion promoter layers  18   a  are laterally encapsulated by the encapsulant  28   a.    
     Referring to  FIG.  1 L  and  FIG.  2 A , in some embodiments, the TIV  15  includes the seed layer  13  and the conductive post  14 . The seed layer  13  includes a first seed layer  13   a  such as a titanium layer, and a second seed layer  13   b  such as a copper layer. In some embodiments, the adhesion promoter layer  18   a  includes a first portion P 1  and a second portion P 2  on the first portion P 1 . For example, the first portion P 1  is laterally on sidewalls of the first seed layer  13   a  of the TIV  15 , the second portion P 2  is laterally on sidewalls of the second seed layer  13   b  and the conductive post  14  of the TIV  15 . In some embodiments, the second portion P 2  is conformal with the second seed layer  13   b  and the conductive post  14  of the TIV  15 , while the first portion P 1  is not conformal with the first seed layer  13   a  of the TIV  15 . The shapes of the first portion P 1  and the second portion P 2  shown in  FIG.  2 A  is merely for illustration, and the disclosure is not limited thereto. 
     In some embodiments, the thickness T 1  of the first portion P 1  and the thickness T 2  of the second portion P 2  are different. Herein, the thickness T 1  and the thickness T 2  refer to the thicknesses of the first portion P 1  and the second portion P 2  along a horizontal direction parallel with a top or bottom surface of the die  25 , respectively. In some embodiments, the thickness T 2  of the second portion P 2  may be uniform, while the thickness T 1  of the first portion P 1  may be decreased gradually from a bottom of the second portion P 2  toward the top surface of the polymer layer  12 . In other words, the first portion P 1  is tapered away from the second portion P 2 , and tapered toward the top surface of the polymer layer  12 . The thickness (i.e. average thickness) T 1  of the first portion P 1  is less than the thickness T 2  of the second portion P 2 . 
     In some embodiments, the first portion P 1  has an arced surface, which may also be referred as the bottom surface BS of the adhesion promoter layer  18   a . In some embodiments, the bottom surface of the TIV  15  and the bottom surface of the encapsulant  28   a  are substantially coplanar with each other and in contact with the polymer layer  12 . The bottom surface of the TIV  15  is not in contact with the adhesion promoter layer  18   a . The bottom surface BS of the adhesion promoter layer  18   a  is higher than the bottom surfaces of the TIV  15  and the encapsulant  28   a , and is covered by and in physical contact with the encapsulant  28   a . In other words, a portion of the encapsulant  28   a  is vertically sandwiched between the adhesion promoter layer  18   a  and the polymer layer  12 . The orthographic projection of the adhesion promoter layer  18   a  on the top surface of the polymer layer  12  is overlapped with the orthographic projection of the portion of the encapsulant  28   a  on the top surface of the polymer layer  12 . It is noted that, the shape of the first portion P 1  is merely for illustration, and the disclosure is not limited thereto. 
     In the illustrated embodiments, the adhesion promoter layer  18   a  extends to the bottom of the first seed layer  13   a  and may completely cover the sidewalls of the first seed layer  13   a , but the disclosure is not limited thereto. In alternative embodiments, the first portion P 1  of the adhesion promoter layer  18   a  may cover a portion of sidewalls of the first seed layer  13   a , and another portion of sidewalls of the first seed layer  13   a  may be covered by and in physical contact with the encapsulant  28   a , as shown in  FIG.  2 C . 
       FIG.  2 B  illustrates an enlarged cross-sectional view of the TIV  37 . In some embodiments, the TIV  37  includes a first seed layer  35   a , a second seed layer  35   b  and a conductive post  36 . The adhesion promoter layer  38   a  is laterally sandwiched between the TIV  37  and the encapsulant  48   a . In some embodiments, the adhesion promoter layer  38   a  includes a first portion P 10  on sidewalls of the first seed layer  35   a  and a second portion P 20  on sidewalls of the second seed layer  35   b  and the conductive post  36 . Except that a portion of the TIV  37  is embedded in the polymer layer PM 3 , the other structural features of the TIV  37  and the adhesion promoter layer  38   a  are substantially the same as those of the TIV  15  and the adhesion promoter layer  18   a , which are not described again here. 
     In the embodiments of the disclosure, the adhesion promoter layer is formed between the TIV and the encapsulant, which may help to improve the adhesion between the TIV and the encapsulant. On the other hand, the adhesion promoter layer may help to avoid or reduce the TIV contacting air or moisture, and therefore the oxidation of the TIV may be avoided or reduced. In some embodiments, the TIVs  15  and  37  of the package structure  100   a  are not oxidized with the protection of the adhesion promoter layer  18   a / 38   a , but the disclosure is not limited thereto. In alternative embodiments, portions of the TIVs  15  and  37  may still be oxidized. The details are described below taken the TIV  15  as an example. 
       FIG.  3 A  to  FIG.  3 C  illustrate examples of the oxidation of the TIV  15 . 
     Referring to  FIG.  3 A  to  FIG.  3 C , in some embodiments, the metal included in the TIV  15  or metal cations diffused from the TIV  15  may be oxidized, and an oxide layer  50  may be formed aside the TIV  15 . The oxide layer  50  includes a metal oxide such as copper oxide. In some embodiments, as shown in  FIG.  3 A , the oxide layer  50  is formed on the sidewalls of the TIV  15  and located between the TIV  15  and the adhesion promoter layer  18   a . In some embodiments, migration of the oxide layer  50  may be occurred over time. That is, the location of the oxide layer  50  may be changed over time. For example, the oxide layer  50  may migrate away from the sidewalls of the TIV  15  and may be distributed within the adhesion promoter layer  18   a , as shown in  FIG.  3 B . In some embodiments, the oxide layer  50  may further migrate out of the adhesion promoter layer  18   a  and is located between the adhesion promoter layer  18   a  and the encapsulant  28   a , as shown in  FIG.  3 C . Although the oxide layer  50  is illustrated as a continuous layer, the disclosure is not limited thereto. In alternative embodiments, the oxide layer  50  may be a discontinuous layer. The oxide layer  50  may have a uniform thickness or includes a plurality of oxide portions with different thicknesses. 
       FIG.  5 A  to  FIG.  5 I  are schematic cross-sectional views illustrating a method of forming a package structure and a PoP device according to some embodiments of the disclosure.  FIG.  6 A  to  FIG.  6 C  are enlarged cross-sectional views illustrating polymer layers, a conductive pattern and an adhesion promoter layer. 
     Referring to  FIG.  5 A , a carrier  10  is provided. The carrier  10  may be a glass carrier, a ceramic carrier, or the like. A de-bonding layer  11  is formed on the carrier  10  by, for example, a spin coating method. In some embodiments, the de-bonding layer  11  may be formed of an adhesive such as an Ultra-Violet (UV) glue, a Light-to-Heat Conversion (LTHC) glue, or the like, or other types of adhesives. The de-bonding layer  11  is decomposable under the heat of light to thereby release the carrier  10  from the overlying structures that will be formed in subsequent steps. 
     Referring to  FIG.  5 A  to  FIG.  5 C , a redistribution layer (RDL) structure  32  is formed on the de-bonding layer  11 . In some embodiments, the RDL structure  32  is referred to as a back-side RDL structure. Throughout the specification, wherein the “back-side” refers to a side close to the package structure  200  (shown in  FIG.  5 I ). 
     In some embodiments, the RDL structure  32  includes a plurality of polymer layers PM 1 , PM 2  and PM 3  and a plurality of redistribution layers RDL 1  and RDL 2 . The number of the polymer layers or the redistribution layers shown in  FIG.  5 C  is merely for illustration, and the disclosure is not limited thereto. 
     As shown in  FIG.  5 A , first, a polymer layer PM 1  is formed on the de-bonding layer  11 . In some embodiments, the polymer layer PM 1  includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. 
     Then, a plurality of conductive patterns CP 1  of the redistribution layer RDL 1  are formed on the polymer layer PM 1 . In some embodiments, the conductive pattern CP 1  includes a seed layer  13  and a conductive layer  14  on the seed layer  13 . The seed layer  13  is a metal seed layer such as a copper seed layer. For example, the seed layer  13  may include titanium, copper, the like, or a combination thereof. In some embodiments, the seed layer includes a first seed layer  13   a  and a second seed layer  13   b  over the first seed layer  13   a  ( FIG.  6 A ). The first seed layer  13   a  and the second seed layer  13   b  may include different materials. For example, the first seed layer  13   a  is a titanium layer, and the second seed layer  13   b  is a copper layer. In some embodiments, the conductive layer  14  include a material the same as the second seed layer  13   b  and different from the first seed layer  13   a . The conductive layer  14  includes a suitable metal, such as copper. However, the disclosure is not limited thereto. The sidewalls of the conductive layers  14  may be substantially aligned with the sidewalls of the seed layer  13 . The sidewalls of the conductive patterns CP 1  may be substantially straight, inclined, arced or the like. 
     The conductive patterns CP 1  may be formed by the following processes: a seed material layer is formed on the polymer layer PM 1  by a physical vapor deposition (PVD) process such as sputtering. A patterned mask layer is then formed on the seed material layer, the patterned mask layer has a plurality of openings exposing a portion of the seed material layer at the intended locations for the subsequently formed conductive patterns CP 1 . Thereafter, the conductive layers  14  are formed on the seed material layer within the openings by a plating process, such as electroplating. Thereafter, the patterned mask layer is stripped by an ashing process, for example. The seed material layer not covered by the conductive layers  14  is removed by an etching process using the conductive layers  14  as the etching mask. As such, the seed layers  13  underlying the conductive layers  14  are remained, the seed layer  13  and the conductive layer  14  constitute the conductive pattern CP 1 . 
     Referring to  FIG.  5 B , in some embodiments, adhesion promoter material layers  18  are formed on the conductive patterns CP 1  to cover the top surfaces and sidewalls of the conductive patterns CP 1 . The adhesion promoter material layer  18  may include a metal chelate compound, such as copper chelate. The metal chelate compound included in the adhesion promoter material layer  18  is corresponding to the metal included in the conductive pattern CP 1 . That is, the adhesion promoter material layer  18  and the conductive pattern CP 1  include a same metal element. In some embodiments, the adhesion promoter material layer  18  may be formed by conducting a chelation reaction between a chelating agent and the conductive pattern CP 1 . 
     Referring to  FIG.  5 B  and  FIG.  11   , for example, the adhesion promoter material layers  18  may be formed by the following processes: after the conductive patterns CP 1  are formed, in step S 10 ′, a pre-cleaning process is performed on the conductive patterns CP 1  to clean the surfaces of the conductive patterns CP 1 . The detergent used in the pre-cleaning process may include an acid such as citric acid (CX-100), hydrochloric acid, sulfuric acid, acetic acid, or the like or combinations thereof. The pre-cleaning process may be performed at room temperature for 5 seconds to 10 minutes, such as 1 minute, for example, but the disclosure is not limited thereto. The pre-cleaning process may remove undesired substances on the surfaces of the conductive patterns CP 1 , such as impurities or metal oxide. In some embodiments, after the conductive pattern CP 1  is formed, the metal included in the conductive pattern CP 1  may be oxidized when exposed to moisture or air for a period of time, and metal oxide such as copper oxide may be formed on the surface of the conductive pattern CP 1 . In the embodiments in which the surface of the conductive pattern CP 1  is oxidized, the metal oxide on the surface of the conductive pattern CP 1  is removed by the pre-cleaning process. 
     Thereafter, in step S 20 ′, a first cleaning process is further performed to clean the surfaces of the conductive patterns CP 1 . In some embodiments, the first cleaning process may remove the remnant generated from the pre-cleaning process, such as the reaction product of the detergent and the metal oxide, the remained detergent, impurities, or combinations thereof. The first cleaning process may be a deionized water rinsing process, and may be performed for 5 seconds to 10 minutes, such as 1 minute, for example. However, the disclosure is not limited thereto. 
     After the first cleaning process is performed, in step S 30 ′, a drying process is performed to dry the surfaces of the conductive patterns CP 1 . In some embodiments, the structure shown in  FIG.  5 B  is placed in a drying apparatus, and the drying process is performed by introducing an inert gas such as dry nitrogen gas into the drying apparatus, so as to dry the surfaces of the conductive patterns CP 1  and also prevent the conductive patterns CP 1  from being oxidized again. In some embodiments, the drying process is performed at room temperature for 5 seconds to 10 minutes, such as 1 minute, for example. 
     Afterwards, in step S 40 ′, a treatment process is performed on the conductive patterns CP 1  by applying a treatment agent on the conductive patterns CP 1  (step S 41 ′) and conducting a reaction (such as a chelating reaction) between the conductive patterns CP 1  and the treatment agent (step S 42 ′). The method of applying the treatment agent may include dipping, spraying, spin coating, the like, or combinations thereof. The treatment process may be performed at a temperature ranging from room temperature to 80° C. or at 40° C. In some embodiments, the treatment process is performed in an alkaline environment, a weak acid environment or a neutral pH environment, but the disclosure is not limited thereto. For example, the pH of the treatment agent may be in a range of 5 to 12 or 8 to 12. The treatment agent includes a chelating agent, and the concentration of the chelating agent may range from 0.01 wt % to 100 wt %. In some embodiments, the chelating agent includes chelating ligands capable of forming coordination bond with the metal (such as copper) of the conductive patterns CP 1 . For example, the ligand atom of the chelating ligand may include N, O, S, or combinations thereof. In some embodiments, the chelating agent may be represented by the general formulas (I) described above. 
     Still referring to  FIG.  5 B , during the treatment process, a chelating reaction is conducted between the metal of conductive patterns CP 1  and the chelating agent, and a metal chelate compound (that is, the adhesion promoter material layer  18 ) is formed on the surfaces of the conductive patterns CP 1 . During the chelating reaction, metal atoms or metal cations on the surface of or diffused from the conductive patterns CP 1  chelates with the chelating agent, and coordinate bonds are formed between the metal atoms or cations and the chelating ligands of the chelating agent. In some embodiments in which the conductive pattern CP 1  includes copper, the metal cations may be Cu +  or Cu 2+ . In some embodiments, the coordination bonds may be formed between the respective metal atom or cation and the same or different types of chelating ligands of the chelating agent. 
     Referring to  FIG.  5 B , in some embodiments, the chelating agent has a specific affinity for the metal included in conductive pattern CP 1 , and only reacts with the conductive pattern CP 1  without reacting with the polymer layer PM 1 . Therefore, the adhesion promoter material layer  18  is selectively formed on the surfaces of the conductive patterns CP 1  by the treatment process. 
     In some embodiments, the duration of the treatment process may range from 5 seconds to 10 minutes, for example. However, the disclosure is not limited thereto. The duration of the treatment process may be adjusted depending on the required thickness of the adhesion promoter material layer  18  according to product design. In some embodiments, the thickness of the adhesion promoter material layer  18  increases as the duration of the treatment process increases. The thickness increase rate of the adhesion promoter material layer  18  may be reduced over time. It is because as the thickness of the adhesion promoter material layer  18  increases, the time required for metal cations to diffuse outside the metal chelate to react with the chelating agent increases. 
     In some embodiments, as illustrated in step S 50 ′ of  FIG.  11   , a second cleaning process is then performed to clean the surfaces of the adhesion promoter material layers  18 . The second cleaning process may be a deionized water rinsing process, and may be performed for 5 seconds to 10 minutes, such as 1 minute. Thereafter, in step S 60 ′, a drying process may be performed to dry the surface of the adhesion promoter material layer  18 . The drying process may be performed using dry air. In some embodiments, the drying process is performed at room temperature for 5 seconds to 10 minutes, such as 1 minute, for example. As such, the formation of the adhesion promoter material layer  18  is thus completed. 
     Referring to  FIG.  5 B  and  FIG.  6 A , in some embodiments, the sidewalls and the top surface of the conductive layer  14  are covered, such as completely covered by the adhesion promoter material layer  18 . The sidewalls of the seed layer  13  may be partially covered or completely covered by the adhesion promoter material layer  18 . In some embodiments in which the seed layer  13  includes the first and second seed layers  13   a  and  13   b , and the conductive layer  14  and the second seed layer  13   b  includes the same metal such as copper, and the first seed layer  13   a  include a metal (such as titanium) different from the second seed layer  13   b , the chelating agent may react with the copper included in the conductive layer  14  and the second seed layer  13   b  without reacting with titanium included in the first seed layer  13   a . In some embodiments, the metal chelate produced by the chelating reaction is formed on and cover the sidewalls of the conductive layer  14  and the second seed layer  13   b  and may further extend to (partially or completely) cover the sidewalls of the first seed layer  13   a . In other words, the adhesion promoter material layer  18  is in physical contact with the first seed layer  13   a , the second seed layer  13   b  and the conductive layer  14  of the conductive pattern CP 1 . Chemical bonds such as coordination bonds are formed between the second seed layer  13   b  and the adhesion promoter material layer  18 , and between the conductive layer  14  and the adhesion promoter material layer  18 , while no chemical bond is formed between the first seed layer  13   a  and the adhesion promoter material layer  18 . 
     Referring to  FIG.  5 C , a polymer layer PM 2  is formed between the conductive patterns CP 1  of the redistribution layer RDL 1 . In some embodiments, the polymer layer PM 2  includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. 
     Then, a redistribution layer RDL 2  may be formed over the redistribution layer RDL 1 , to electrically connect to the redistribution layer RDL 1 . In some embodiments, the redistribution layer RDL 2  includes a plurality of conductive patterns CP 2  formed in the polymer layer PM 2  and a plurality of vias V formed between the conductive patterns CP 1  and the conductive patterns CP 2 , to electrically connect the redistribution layer RDL 1  and the redistribution layer RDL 2 . In some embodiments, the via V is formed integrally with the conductive pattern CP 2  thereover. For example, the via V and the conductive pattern CP 2  are formed by a dual damascene process. In some embodiments, a width of the via V decreases as the via V becomes closer to the conductive pattern CP 1 . 
     In some embodiments, as shown in  FIG.  5 C  and  FIG.  6 A , the conductive pattern CP 2  and the via V respectively includes a seed layer  13  and a conductive layer  14  on the seed layer  13 . In some embodiments in which the conductive pattern CP 2  and the via V are integrally formed, the seed layer  13  of the conductive pattern CP 2  is continuous with the seed layer  13  of the via V, and the conductive layer  14  of the conductive pattern CP 2  is continuous with the conductive layer  14  of the via V. However, the disclosure is not limited thereto. In alternative embodiments, the via V and the conductive pattern CP 2  are formed respectively. In such embodiments, the seed layer  13  of the conductive pattern CP 2  is continuously disposed between the conductive layer  14  of the conductive pattern CP 2  and the conductive layer  14  of the via V. 
     The sidewalls of the conductive layer  14  may be substantially aligned with the sidewalls of the seed layer  13 . The sidewalls of the conductive patterns CP 1  may be substantially straight, inclined, arced or the like. The seed layer  13  is a metal seed layer such as a copper seed layer. For example, the seed layer  13  may include titanium, copper, the like, or a combination thereof. In some embodiments, the seed layer  13  includes a first seed layer  13   a  and a second seed layer  13   b  over the first seed layer  13   a . The first seed layer  13   a  and the second seed layer  13   b  may include different materials. For example, the first seed layer is a titanium layer, and the second seed layer is a copper layer. In some embodiments, the conductive layer  14  include a material the same as the second seed layer  13   b  and different from the first seed layer  13   a . The conductive layer  14  includes a suitable metal, such as copper. 
     In some embodiments, after forming the redistribution layer RDL 2 , a polymer layer PM 3  is formed over the polymer layer PM 2  to cover the redistribution layer RDL 2 . The redistribution layer RDL 1  penetrates into the polymer layer PM 2 , and the redistribution layer RDL 2  penetrates through a portion of the polymer layer PM 2  to electrically connect to the redistribution layer RDL 1 . In some embodiments, the conductive patterns CP 1 , CP 2  are, for example, traces. The conductive patterns CP 1  are embedded in the polymer layer PM 2 , and are located on and extending on the top surface of the polymer layer PM 1 , respectively. The conductive patterns CP 2  are embedded in the polymer layer PM 3 , and are located on and extending on the top surface of the polymer layer PM 2 , respectively. The vias V penetrate through the polymer layer PM 2  between the conductive patterns CP 1  and the conductive patterns CP 2 . The polymer layer PM 3  is located on and covers the polymer layer PM 2  and the redistribution layer RLD 2 . 
     Still referring to  FIG.  5 C , in some embodiments, the polymer layer PM 3  is patterned to form a plurality of openings  34 . The openings  34  expose a portion of the top surface of the redistribution layer RDL 2 . In some embodiments, conductive terminals may be formed on the redistribution layer RDL 2  exposed by the openings  34 . 
     Referring to  FIG.  5 D , a plurality of through integrated fan-out vias (TIVs)  37  are formed on the redistribution layer RDL 2  exposed by the openings  34  of the polymer layer PM 3 . In some embodiments, the TIV  37  includes a seed layer  35  and a conductive post  36  on the seed layer  35 . The seed layer  35  is a metal seed layer such as a copper seed layer. For example, the seed layer  35  may include titanium, copper, the like, or a combination thereof. In some embodiments, the seed layer  35  includes a first seed layer  35   a  and a second seed layer  35   b  over the first seed layer  35   a  ( FIG.  7 A ). The first seed layer  35   a  and the second seed layer  35   b  may include different materials. For example, the first seed layer is a titanium layer, and the second seed layer is a copper layer. In some embodiments, the conductive post  36  include a material the same as the second seed layer  35   b  and different from the first seed layer  35   a . The conductive post  36  includes a suitable metal, such as copper. However, the disclosure is not limited thereto. The sidewalls of the conductive posts  36  may be substantially aligned with the sidewalls of the seed layer  35 . The sidewalls of the TIVs  37  may be substantially straight, inclined, arced or the like. The TIVs  37  may be also referred to as through vias (TV). 
     The TIVs  37  may be formed by the following processes: a seed material layer is formed on exposed surfaces of the polymer layer PM 3  by a physical vapor deposition (PVD) process such as sputtering. A patterned mask layer is then formed on the seed material layer, the patterned mask layer has a plurality of openings exposing a portion of the seed material layer at the intended locations for the subsequently formed TIVs  37 . Thereafter, the conductive posts  36  are formed on the seed material layer within the openings by a plating process, such as electroplating. Thereafter, the patterned mask layer is stripped by an ashing process, for example. The seed material layer not covered by the conductive posts  36  is removed by an etching process using the conductive posts  36  as the etching mask. As such, the seed layers  35  underlying the conductive posts  36  remain, and the seed layer  35  and the conductive post  36  constitute the TIV  37 . It is noted that, the number and the location of the TIVs  37  shown in  FIG.  5 D  is merely for illustration, and the disclosure is not limited thereto. In alternative embodiments (not shown), the TIV  37  may be disposed directly above the conductive pattern CP 1 . 
     Still referring to  FIG.  5 D , an adhesion promoter material layer  38  is then formed to cover the sidewalls and top surfaces of the TIVs  37 . In some embodiments, the adhesion promoter material layer  38  includes a metal chelate, such as copper chelate. The forming method of the adhesion promoter material layer  38  is similar to, and may be substantially the same as or different form that of the adhesion promoter material layer  18 , which is not described again here. The adhesion promoter material layer  38  covers the sidewalls and the top surface of the conductive post  36 , and the sidewalls of the seed layer  35  on the top surface of the polymer layer PM 3 . 
     Referring to  FIG.  5 E , a die  45  is mounted on the polymer layer PM 3  by pick and place processes. In some embodiments, the die  45  is attached to the polymer layer PM 3  through an adhesive layer  39  such as a die attach film (DAF), silver paste, or the like. In some embodiments, the die  45  is one of a plurality of dies cut apart from a wafer, for example. The die  45  may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip or a memory (such as DRAM) chip. The number of the die  45  shown in  FIG.  5 D  is merely for illustration, and the disclosure is not limited thereto. In some embodiments, two or more dies  45  may be disposed side by side on the polymer layer PM 3  over the carrier  10 , and the two or more dies  45  may be the same types of dies or the different types of dies. 
     Still referring to  FIG.  5 E , the die  45  is disposed on the polymer layer PM 3  and laterally between the TIVs  37 , that is, the TIVs  37  are laterally aside or around the die  45 . In some embodiments, the die  45  includes a substrate  40 , a plurality of pads  41 , a passivation layer  42 , a plurality of connectors  43  and a passivation layer  44 . In some embodiments, the substrate  40  is made of silicon or other semiconductor materials. Alternatively or additionally, the substrate  40  includes other elementary semiconductor materials such as germanium, gallium arsenic, or other suitable semiconductor materials. In some embodiments, the substrate  40  may further include other features such as various doped regions, a buried layer, and/or an epitaxy layer. Moreover, in some embodiments, the substrate  40  is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Furthermore, the substrate  40  may be a semiconductor on insulator such as silicon on insulator (SOI) or silicon on sapphire. 
     In some embodiments, a plurality of devices are formed in or on the substrate  40 . The devices may be active devices, passive devices, or combinations thereof. In some embodiments, the devices are integrated circuit devices. The devices are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or the like, or combinations thereof. 
     In some embodiments, an interconnection structure and a dielectric structure are formed over the devices on the substrate  40 . The interconnection structure is formed in the dielectric structure and connected to different devices to form a functional circuit. In some embodiments, the dielectric structure includes an inter-layer dielectric layer (ILD) and one or more inter-metal dielectric layers (IMD). In some embodiments, the interconnection structure includes multiple layers of metal lines and plugs (not shown). The metal lines and plugs include conductive materials, such as metal, metal alloy or a combination thereof. For example, the conductive material may include tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or combinations thereof. The plugs include contact plugs and via plugs. The contact plugs are located in the ILD to be connected to the metal lines and the devices. The via plugs are located in the IMD to be connected to the metal lines in different layers. 
     The pads  41  may be or electrically connected to a top conductive feature of the interconnection structure, and further electrically connected to the devices formed on the substrate  40  through the interconnection structure. The material of the pads  41  may include metal or metal alloy, such as aluminum, copper, nickel, or alloys thereof. 
     The passivation layer  42  is formed over the substrate  40  and covers a portion of the pads  41 . Another portion of the pads  41  is exposed by the passivation layer  42  and serves as an external connection of the die  45 . The connectors  43  are formed on and electrically connected to the pads  41  not covered by the passivation layer  42 . The connector  43  includes solder bumps, gold bumps, copper bumps, copper posts, copper pillars, or the like. The passivation layer  44  is formed over the passivation layer  42  and laterally aside the connectors  43  to cover the sidewalls of the connectors  43 . The passivation layers  42  and  44  respectively include an insulating material such as silicon oxide, silicon nitride, polymer, or a combination thereof. The polymer may include polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), the like, or combinations thereof. The materials of the passivation layer  42  and the passivation layer  44  may be the same or different. In some embodiments, the top surface of the passivation layer  44  and the top surfaces of the connectors  43  are substantially coplanar with each other. 
     Still referring to  FIG.  5 E , an encapsulant material layer  48  is then formed over the carrier  10  to encapsulate the die  45 , the TIVs  37  and the adhesion promoter material layer  38 . Specifically, the encapsulant material layer  48  is formed on the polymer layer PM 3 , encapsulating the sidewalls and top surfaces of the die  45 , the sidewalls and top surfaces of the adhesion promoter material layer  38 . The adhesion promoter material layer  38  is sandwiched between the TIVs  37  and the encapsulant material layer  48 . In some embodiments, the adhesion promoter material layer  38  includes a functional group (such as the functional group X, Y, Z in the above formulas) which may react with the encapsulant material layer  48 , and chemical bonds may be formed between the adhesion promoter material layer  38  and the encapsulant material layer  48 . 
     In some embodiments, the encapsulant material layer  48  includes a molding compound, a molding underfill, a resin such as epoxy, a combination thereof, or the like. In some other embodiments, the encapsulant material layer  48  includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like, which may be easily patterned by exposure and development processes or laser drilling process. In alternative embodiments, the encapsulant material layer  48  includes nitride such as silicon nitride, oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like. 
     In some embodiments, the encapsulant material layer  48  includes a composite material including a base material (such as polymer) and a plurality of fillers distributed in the base material. The filler may be a single element, a compound such as nitride, oxide, or a combination thereof. The fillers may include silicon oxide, aluminum oxide, boron nitride, alumina, silica, or the like, for example. In some embodiments, the fillers may be spherical fillers, but the disclosure is not limited thereto. The cross-section shape of the filler may be circle, oval, or any other shape. In some embodiments, the encapsulant material layer  48  is formed by a suitable fabrication technique such as molding, spin-coating, lamination, deposition, or similar processes. 
     Referring to  FIG.  5 F , in some embodiments, a planarization process is performed to remove a portion of the encapsulant material layer  48  over the top surfaces of the die  45  and the TIVs  37  and portions of the adhesion promoter material layers  38  on the top surfaces of the TIVs  37 , such that the top surfaces of the connectors  43  of the die  45  and the top surfaces of the TIVs  37  are exposed. The planarization process includes a grinding or polishing process such as a chemical mechanical polishing (CMP) process. 
     After the planarization process is performed, a plurality of adhesion promoter layers  38   a  and an encapsulant  48   a  are formed. The adhesion promoter layers  38   a  are located on the polymer layer PM 3  and laterally aside the TIVs  37 , and surrounding the sidewalls of the TIVs  37 . The encapsulant  48   a  is located on the polymer layer PM 3  and laterally aside the die  45 , the adhesion promoter layer  38   a  and the TIVs  37 , and encapsulating the sidewalls of the die  45 , the adhesion promoter layer  38   a  and the TIVs  37 . The adhesion promoter layer  38   a  is sandwiched between and in physical contact with the TIV  37  and the encapsulant  48   a . In other word, the encapsulant  48   a  is not in direct physical contact with the TIV  37 , and separated from the TIV  37  by the adhesion promoter layer  38   a  therebetween. In some embodiments, as shown in  FIG.  5 F  and  FIG.  7 A , portions of the TIVs  37  are removed by the planarization process, and thus the top surfaces of the TIVs  37  are lower than the top surfaces of the adhesion promoter layers  38   a  and the encapsulant  48   a . However, the disclosure is not limited thereto. In alternative embodiments, the top surface of the die  45 , the top surfaces of the TIVs  37 , the top surface of the adhesion promoter layer  38   a  and the top surface of the encapsulant  48   a  are substantially coplanar with each other. 
     Referring to  FIG.  5 G , a redistribution layer (RDL) structure  52  is formed on the die  45 , the TIVs  37 , and the encapsulant  48   a . The RDL structure  52  is electrically connected to the die  45  and the TIVs  37 . In some embodiments, the RDL structure  52  includes a plurality of polymer layers PM 30 , PM 20 , PM 20  and PM 30 , and a plurality of redistribution layers RDL 10 , RDL 20 , RDL 30  and RDL 40  stacked alternately. The number of the polymer layers or the redistribution layers shown in  FIG.  5 K  is merely for illustration, and the disclosure is not limited thereto. The materials and forming method of the polymer layers and redistribution layers of the RDL structure  52  are similar to, and may be the same as or different from those of the RDL structure  32 . 
     The redistribution layer RDL 10  penetrates through the polymer layer PM 30  and is electrically connected to the connectors  43  of the die  45  and the TIVs  37 . The redistribution layer RDL 20  penetrates through the polymer layer PM 20  and is electrically connected to the redistribution layer RDL 10 . The redistribution layer RDL 30  penetrates through the polymer layer PM 20  and is electrically connected to the redistribution layer RDL 20 . The redistribution layer RDL 40  penetrates through the polymer layer PM 30  and is electrically connected to the redistribution layer RDL 30 . 
     In some embodiments, similar to the redistribution layers RDL 1  and RDL 2 , the redistribution layers RDL 10 , RDL 20 , RDL 30 , and RDL 40  include a seed layer SL and a conductive layer CL formed thereon, respectively. In some embodiments, the redistribution layers RDL 10 , RDL 20 , RDL 30  respectively includes a plurality of vias V and a plurality of traces T connected to each other. The vias V are embedded in and penetrate through the polymer layers PM 30 , PM 20 , PM 20 , to connect the traces T of the redistribution layers RDL 10 , RDL 20 , RDL 30 , the traces T are located on the polymer layers PM 30 , PM 20 , PM 20 , and are extending on the top surface of the polymer layers PM 30 , PM 20 , PM 20 , respectively. In some embodiments, the redistribution layer RDL 40  is the topmost redistribution layer of the RDL structure  52 , and is referred to as under-ball metallurgy (UBM) layer for ball mounting. 
     Still referring to  FIG.  5 G , a plurality of connectors  56  are formed over and electrically connected to the redistribution layer RDL 40  of the RDL structure  52 . In some embodiments, the connectors  56  are referred as conductive terminals. In some embodiments, the connectors  56  may be ball grid array (BGA) connectors, solder balls, controlled collapse chip connection (C4) bumps, or a combination thereof. In some embodiments, the material of the connector  56  includes copper, aluminum, lead-free alloys (e.g., gold, tin, silver, aluminum, or copper alloys) or lead alloys (e.g., lead-tin alloys). The connector  56  may be formed by a suitable process such as evaporation, plating, ball dropping, screen printing and reflow process, a ball mounting process or a C4 process. In some embodiments, metal posts or metal pillars (not shown) may further be formed between the redistribution layer RDL 40  and the connectors  56 , but the disclosure is not limited thereto. The connectors  56  are electrically connected to the connectors  43  of the die  45  and the TIVs  37  through the RDL structure  52 , and further electrically connected to the RDL structure  32  through the TIVs  37 . 
     Referring to  FIG.  5 G  and  FIG.  5 H , in some embodiments, the de-bonding layer  11  is decomposed under the heat of light, and the carrier  10  is then released from the overlying structure, and a package structure  100   b  is thus formed. In some embodiments, the package structure  100   b  may further be coupled to other package structures to form a package on package (PoP) device. 
     Referring to  FIG.  5 H  and  FIG.  5 I , portions of the polymer layer PM 1  may be removed by a laser drilling process to form openings OP in the polymer layer PM 1 . In some embodiments, a dielectric layer  58  is formed over the polymer layer PM 1 , and the openings OP are formed in the polymer layer PM 1  and the dielectric layer  58 . The dielectric layer  58  includes a substrate dielectric layer such as Ajinomoto Build-up Film (ABF) or the like. The openings OP expose portions of the bottom surfaces of conductive patterns CP 1 . Thereafter, the package structure  100   b  is electrically connected to a package structure  200  to form a PoP device  300  through a plurality of connectors  60 . The connectors  60  fill in the openings OP and are electrically connected to the connective patterns CP 1 . For example, the connector  60  penetrates the polymer layer PM 1  and the dielectric layer  58 , to contact the connective pattern CP 1 . The package structure  100   b  and the package structure  200  may include the same types of devices or the different types of devices. The package structure  200  may include at least one die having a structure similar to the die  45 . The package structure  200  may include active devices, passive devices, or combinations thereof. In some embodiments, the package structure  200  is a memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), or other type of memory. In some embodiments, an underfill layer  62  may further be formed to fill the space between the package structure  100   b  and the package structure  200  and surround the connectors  60 . 
     Referring to  FIG.  5 I , in some embodiments, the package structure  100   b  includes the RDL structure  32  including the conductive patterns CP 1 , the adhesion promoter layers  18   a  aside the conductive patterns CP 1 , the die  45 , the TIVs  37 , the adhesion promoter layers  38   a  aside the TIVs  37 , RDL structure  52  and the connectors  56 . The RDL structure  32  and the RDL structure  52  are electrically connected to each other through the TIVs  37 . In some embodiments, the RDL structure  32  is disposed on back side of the die  45 , and the RDL structure  52  is disposed on front side of the die  45 . 
     In some embodiments, the connective patterns CP 1  are immediately adjacent to the package structure  200 , and the polymer layer PM 2  surrounds the connective patterns CP 1 . In some embodiments, the adhesion promoter layers  18   a  are sandwiched between and in physical contact with the connective patterns CP 1  and the polymer layer PM 2 . In other words, the top surface and the sidewalls of the connective patterns CP 1  are covered by the adhesion promoter layers  18   a , and separated from the polymer layer PM 2  by the adhesion promoter layer  18   a  therebetween. 
     Referring to  FIG.  5 I  and  FIG.  6 A , in some embodiments, the conductive pattern CP 1  includes the seed layer  13  and the conductive layer  14 . The seed layer  13  includes a first seed layer  13   a  such as a titanium layer, and a second seed layer  13   b  such as a copper layer. In some embodiments, the adhesion promoter layer  18   a  is laterally on sidewalls of the conductive layer  14 , the first seed layer  13   a  and the second seed layer  13   b  of the conductive pattern CP 1 . For example, the adhesion promoter layer  18   a  continuously covers the sidewalls of the conductive layer  14 , the first seed layer  13   a  and the second seed layer  13   b  of the conductive pattern CP 1 . In some embodiments, the bottom surface of the adhesion promoter layer  18   a  is entirely in direct contact with the polymer layer PM 1 . 
     Referring to  FIG.  6 B , in alternative embodiments, the adhesion promoter layer  18   a  includes a first portion P 1  and a second portion P 2  on the first portion P 1 . For example, the first portion P 1  is laterally on the sidewall of the first seed layer  13   a  of the conductive pattern CP 1 , and the second portion P 2  is laterally on the sidewalls of the second seed layer  13   b  and the conductive layer  14  of the conductive pattern CP 1 . In some embodiments, the second portion P 2  is a conformal layer on the second seed layer  13   b  and the conductive layer  14  of the conductive pattern CP 1 , while the first portion P 1  is not a conformal layer on the first seed layer  13   a  of the conductive pattern CP 1 . The shapes of the first portion P 1  and the second portion P 2  shown in  FIG.  6 B  is merely for illustration, and the disclosure is not limited thereto. 
     In some embodiments, the thickness T 1  of the first portion P 1  and the thickness T 2  of the second portion P 2  are different. Herein, the thickness T 1  and the thickness T 2  refer to the thicknesses of the first portion P 1  and the second portion P 2  along a horizontal direction parallel with a top or bottom surface of the die  45 , respectively. In some embodiments, the thickness T 2  of the second portion P 2  may be uniform, while the thickness T 1  of the first portion P 1  may decrease gradually from a bottom of the second portion P 2  toward the top surface of the polymer layer PM 1 . In other words, the first portion P 1  is tapered away from the second portion P 2 , and tapered toward the top surface of the polymer layer PM 1 . The thickness (e.g., average thickness) T 1  of the first portion P 1  is less than the thickness T 2  of the second portion P 2 . 
     In some embodiments, the first portion P 1  has an arced surface, which may also be referred as the bottom surface BS of the adhesion promoter layer  18   a . In some embodiments, the bottom surface of the conductive pattern CP 1  and the bottom surface of the polymer layer PM 2  are substantially coplanar with each other and in contact with the polymer layer PM 1 . The bottom surface of the conductive pattern CP 1  is not in contact with the adhesion promoter layer  18   a , for example. At least a portion of the bottom surface BS of the adhesion promoter layer  18   a  is higher than the bottom surfaces of the conductive pattern CP 1  and the polymer layer PM 2 , and is covered by and in physical contact with the polymer layer PM 2 . In other words, a portion of the polymer layer PM 2  is directly under a portion of the bottom surface BS of the adhesion promoter layer  18   a  and is vertically sandwiched between the adhesion promoter layer  18   a  and the polymer layer PM 1 . The orthographic projection of the adhesion promoter layer  18   a  on the top surface of the polymer layer PM 1  is overlapped with the orthographic projection of the portion of the polymer layer PM 2  on the top surface of the polymer layer PM 1 . It is noted that, the shape of the first portion P 1  is merely for illustration, and the disclosure is not limited thereto. 
     In the illustrated embodiments, the adhesion promoter layer  18   a  extends to the bottom of the first seed layer  13   a  and may completely cover the sidewalls of the first seed layer  13   a , but the disclosure is not limited thereto. In alternative embodiments, the first portion P 1  of the adhesion promoter layer  18   a  may cover a portion of sidewalls of the first seed layer  13   a , and another portion of sidewalls of the first seed layer  13   a  may be covered by and in physical contact with the encapsulant  28   a , as shown in  FIG.  6 C . 
     In some embodiments, the TIVs  37  are laterally aside the die  45 , and the encapsulant  48   a  are laterally aside the die  45  and the TIVs  37 , and encapsulating sidewalls of the die  45  and sidewalls of the TIVs  37 . In some embodiments, the adhesion promoter layers  38   a  are sandwiched between and in physical contact with the TIVs  37  and the encapsulant  48   a . In other words, the sidewalls of the TIVs  37  are covered by the adhesion promoter layers  38   a , and separated from the encapsulant  48   a  by the adhesion promoter layer  38   a  therebetween. The sidewalls of the adhesion promoter layers  38   a  are laterally encapsulated by the encapsulant  48   a.    
     Referring to  FIG.  5 I  and  FIG.  7 A , in some embodiments, the TIV  37  includes the seed layer  35  and the conductive post  36 . The seed layer  35  includes a first seed layer  35   a  such as a titanium layer, and a second seed layer  35   b  such as a copper layer. A portion of the TIV  37  is embedded in the polymer layer PM 3 . For example, portions of the first seed layer  35   a  and the second seed layer  35   b  are embedded in the polymer layer PM 3 . In some embodiments, the top surface of the TIV  37  is lower than the top surfaces of the encapsulant  48   a  and the adhesion promoter layer  38   a . The top surfaces of the encapsulant  48   a  and the adhesion promoter layer  38   a  are substantially coplanar, for example. In some embodiments, the adhesion promoter layer  38   a  continuously covers the sidewalls of the conductive post  36 , the first seed layer  35   a  and the second seed layer  35   b  of the TIV  37 . In some embodiments, the bottom surface of the adhesion promoter layer  38   a  is entirely in direct contact with the polymer layer PM 3 . 
     Referring to  FIG.  5 L  and  FIG.  7 B , in some embodiments, the adhesion promoter layer  38   a  includes a first portion P 10  and a second portion P 20  on the first portion P 10 . For example, the first portion P 10  is laterally on sidewalls of the first seed layer  35   a  of the TIV  37 , the second portion P 20  is laterally on sidewalls of the second seed layer  35   b  and the conductive post  36  of the TIV  37 . In some embodiments, the second portion P 20  is a conformal layer on the second seed layer  35   b  and the conductive post  36  of the TIV  37 , while the first portion P 10  is not a conformal layer on the first seed layer  35   a  of the TIV  37 . The shapes of the first portion P 10  and the second portion P 20  shown in  FIG.  7 B  is merely for illustration, and the disclosure is not limited thereto. 
     In some embodiments, a thickness T 3  of the first portion P 10  and a thickness T 4  of the second portion P 20  are different. Herein, the thickness T 3  and the thickness T 4  refer to the thicknesses of the first portion P 10  and the second portion P 20  along a horizontal direction parallel with a top or bottom surface of the die  45 , respectively. In some embodiments, the thickness T 4  of the second portion P 20  may be uniform, while the thickness T 3  of the first portion P 10  may decrease gradually from a bottom of the second portion P 20  toward the top surface of the polymer layer PM 3 . In other words, the first portion P 10  is tapered away from the second portion P 20 , and tapered toward the top surface of the polymer layer PM 3 . The thickness (e.g., average thickness) T 3  of the first portion P 10  is less than the thickness T 4  of the second portion P 20 . 
     In some embodiments, the first portion P 10  has an arced surface, which may also be referred as the bottom surface BS&#39; of the adhesion promoter layer  38   a . In some embodiments, the bottom surface of the TIV  37  and the bottom surface of the encapsulant  48   a  are substantially coplanar with each other and in contact with the polymer layer PM 3 . The bottom surface of the TIV  37  is not in contact with the adhesion promoter layer  38   a . At least a portion of the bottom surface BS&#39; of the adhesion promoter layer  38   a  is higher than the bottom surfaces of the TIV  37  and the encapsulant  48   a , and is covered by and in physical contact with the encapsulant  48   a . In other words, a portion of the encapsulant  48   a  is vertically sandwiched between the adhesion promoter layer  38   a  and the polymer layer PM 3 . The orthographic projection of the adhesion promoter layer  38   a  on the top surface of the polymer layer PM 3  is overlapped with the orthographic projection of the portion of the encapsulant  48   a  on the top surface of the polymer layer PM 3 . It is noted that, the shape of the first portion P 10  is merely for illustration, and the disclosure is not limited thereto. 
     In the illustrated embodiments, the adhesion promoter layer  38   a  extends to the bottom of the first seed layer  35   a  and may completely cover the sidewalls of the first seed layer  35   a , but the disclosure is not limited thereto. In alternative embodiments, the first portion P 10  of the adhesion promoter layer  38   a  may cover a portion of sidewalls of the first seed layer  35   a , and another portion of sidewalls of the first seed layer  35   a  may be covered by and in physical contact with the encapsulant  48   a , as shown in  FIG.  7 C . 
     In some embodiments, the sidewalls of TIVs  37  are illustrated as substantially straight. However, the disclosure is not limited thereto. In alternative embodiments, the TIVs  37  have curved sidewalls and/or inclined sidewalls. For example, as shown in  FIG.  8   , the TIV  37  is disposed in an opening  49  of the encapsulant  48   a . In some embodiments, the TIV  37 , the adhesion promoter layer  38   a  and the opening  49  have curved sidewalls. The opening  49  has curved sidewalls  49   s   1 ,  49   s   2  (also referred to as inner sidewalls  49   s   1 ,  49   s   2  of the encapsulant  48   a ), and the adhesion promoter layer  38   a  is a conformal layer between the sidewalls  49   s   1 ,  49   s   2  of the encapsulant  48   a  and the TIV  37 . In such embodiments, a distance d between the inner sidewalls  49   s   1 ,  49   s   2  decreases and then increases as the inner sidewalls  49   s   1 ,  49   s   2  become closer to the RDL structure  32 . Similarly, the width w of the TIV  37  also decreases and then increases as the TIV  37  extends from an upper surface towards the RDL structure  32 . 
     In some embodiments, the adhesion promoter layers  18   a ,  38   a  are illustrated as a single layer. However, the adhesion promoter layers  18   a ,  38   a  may have a multi-layered structure. For example, as shown in  FIG.  9 A , the adhesion promoter layer  18   a  includes a first adhesion promoter layer  19   a  and a second adhesion promoter layer  19   b  conformally disposed on the first adhesion promoter layer  19   a . The materials of the first adhesion promoter layer  19   a  and the second adhesion promoter layer  19   b  are different, and the first adhesion promoter layer  19   a  and the second adhesion promoter layer  19   b  may respectively include a metal chelate compound as described above. The second adhesion promoter layer  19   b  includes the material having a specific affinity to the first adhesion promoter layer  19   a  and/or the polymer layer PM 2 . For example, compared to the first adhesion promoter layer  19   a , the second adhesion promoter layer  19   b  has more affinity to the polymer layer PM 2 . In some embodiments, the bottom surfaces of the first adhesion promoter layer  19   a  and the second adhesion promoter layer  19   b  are, for example, partially higher than the bottom surfaces of the conductive pattern CP 1  and the polymer layer PM 2 , and are covered by and in physical contact with the polymer layer PM 2 . However, the disclosure is not limited thereto. The bottom surfaces of the first adhesion promoter layer  19   a  and the second adhesion promoter layer  19   b  may be entirely in contact with the polymer layer PM 1  as shown in  FIG.  6 A  or entirely higher than the bottom surfaces of the conductive pattern CP 1  as shown in  FIG.  6 C . Similarly, the adhesion promoter layer  38   a  on the TIV  37  may have multi-layered structure. 
     In some embodiments, the adhesion promoter layers  18   a ,  38   a  are illustrated as a continuous layer. However, the disclosure is not limited thereto. In alternative embodiments, one or both of the adhesion promoter layers  18   a ,  38   a  are non-continuous layer. For example, as shown in  FIG.  9 B , the adhesion promoter layer  18   a  includes a plurality adhesion promoter patterns  19   p  on the top surface and/or sidewalls of the conductive pattern CP 1 . The adhesion promoter patterns  19   p  may respectively include a metal chelate compound as described above. In some embodiments, the adhesion promoter patterns  19   p  are formed simultaneously and have the same material. Compared to the adhesion promoter layer  18   a  formed after performing the pre-cleaning process as shown in  FIG.  5 B , island shaped-adhesion promoter patterns  19   p  may be formed by omitting or performing the pre-cleaning process less than described above. The adhesion promoter patterns  19   p  may have substantially the same or different size (e.g., height and/or width), and have similar or different shapes. The adhesion promoter patterns  19   p  may be respectively shaped as a partial sphere, merged spheres or any suitable shape. The adhesion promoter patterns  19   p  are physically separated from each other and thus portions of the conductive pattern CP 1  are exposed by the adhesion promoter patterns  19   p . The adhesion promoter patterns  19   p  may be randomly or regularly dispersed on the exposed surface of the conductive pattern CP 1 . That is, the distances between the adhesion promoter patterns  19   p  may be constant or different. In some embodiments, the conductive pattern CP 1  includes the seed layer  13  and the conductive layer  14 , and the adhesion promoter patterns  19   p  may be disposed on the seed layer  13  and/or the conductive layer  14 . For example, as shown in  FIG.  9 B , the adhesion promoter patterns  19   p  are illustrated as being on the sidewalls and top surface of the conductive layer  14  of the conductive pattern CP 1 . However, the disclosure is not limited. The adhesion promoter patterns  19   p  may be disposed on and in physical contact with at least one of the first seed layer  13   a , the second seed layer  13   b  and the conductive layer  14  of the conductive pattern CP 1 . 
     In some embodiments, the adhesion promoter patterns  19   p  provide a larger contact area to the polymer layer PM 2 , which may help to improve the adhesion between the conductive pattern CP 1  and the polymer layer PM 2 . Similarly, the adhesion promoter layer  38   a  on the TIV  37  may be non-continuous layer and includes a plurality of adhesion promoter patterns. Accordingly, the adhesion promoter patterns help to improve the adhesion between the TIV  37  and the encapsulant  48   a.    
     In the embodiments of the disclosure, the adhesion promoter layer is formed between the conductive pattern and the polymer layer, which may help to improve the adhesion between the conductive pattern and the polymer layer. For example, the laser drilling process used for the formation of the openings OP in the polymer layer PM 1  may cause the delamination or crack between the conductive pattern CP 1  and the polymer layer PM 2 , and the issue is prevented or reduced by the adhesion promoter layer  18   a  between the conductive pattern CP 1  and the polymer layer PM 2 . On the other hand, the adhesion promoter layer may help to avoid or reduce the conductive pattern contacting air or moisture, and therefore the oxidation of the conductive pattern may be avoided or reduced. Accordingly, the formation of dendrites due to copper oxidation may be prevented. In some embodiments, the connective patterns CP 1  of the package structure  100   b  are not oxidized with the protection of the adhesion promoter layer  18   a , but the disclosure is not limited thereto. 
     Similarly, in the embodiments of the disclosure, the adhesion promoter layer  38   a  is between the TIV and the encapsulant, which may help to improve the adhesion between the TIV and the encapsulant. In addition, as shown in  FIG.  5 I , the TIV  37  is physically separated from the conductive pattern CP 1  by a portion WP of the polymer layer PM 2  directly below the TIV  37 . In some embodiments, the TIV  37  is physically connected to the conductive pattern CP 2 , and the conductive pattern CP 2  is separated from the conductive pattern CP 1  by the portion WP of the polymer layer PM 2  therebetween in the region below the TIV  37 . The orthographic projection of the portion WP on the top surface of the polymer layer PM 1  is entirely overlapped with the orthographic projection of the TIV  37  on the top surface of the polymer layer PM 1 , for example. In some embodiments, there is no conductive pattern in the portion WP of the polymer layer PM 2 . That is, there is no conductive pattern in the region below the TIV  37  and the corresponding portions of the conductive pattern CP 2  below the TIV  37  to physically connect the conductive pattern CP 2  and the underlying conductive pattern CP 1 . The portion WP of the polymer layer PM 2  is referred to as a weak point since it may cause the TIV  37  thereover to delaminate from the encapsulant  48   a . However, in some embodiments, the adhesion between the TIV  37  and the encapsulant  48   a  is enhanced, and thus the delamination due to the weak point is prevented or reduced. On the other hand, the adhesion promoter layer  38   a  may help to avoid or reduce the TIVs  37  contacting air or moisture, and therefore the oxidation of the TIVs  37  may be avoided or reduced. In some embodiments, the TIVs  37  of the package structure  100   b  are not oxidized with the protection of the adhesion promoter layer  38   a , but the disclosure is not limited thereto. In alternative embodiments, portions of the connective patterns CP 1  and TIVs  37  may be oxidized. The details are described below taken the TIV  37  as an example. 
       FIG.  10 A  to  FIG.  10 C  illustrate examples of the oxidation of the TIV  37 . 
     Referring to  FIG.  10 A  to  FIG.  10 C , in some embodiments, the metal included in the TIV  37  or metal cations diffused from the TIV  37  may be oxidized, and an oxide layer  50  may be formed aside the TIV  37 . The oxide layer  50  includes a metal oxide such as copper oxide. In some embodiments, as shown in  FIG.  10 A , the oxide layer  50  is formed on the sidewalls of the TIV  37  and located between the TIV  37  and the adhesion promoter layer  38   a . In some embodiments, migration of the oxide layer  50  may occur over time. That is, the location of the oxide layer  50  may change over time. For example, the oxide layer  50  may migrate away from the sidewalls of the TIV  37  and may be distributed within the adhesion promoter layer  38   a , as shown in  FIG.  10 B . In some embodiments, the oxide layer  50  may migrate out of the adhesion promoter layer  38   a  to between the adhesion promoter layer  38   a  and the encapsulant  48   a , as shown in  FIG.  10 C . Although the oxide layer  50  is illustrated as a continuous layer, the disclosure is not limited thereto. In alternative embodiments, the oxide layer  50  may be a discontinuous layer. The oxide layer  50  may have a uniform thickness or includes a plurality of oxide portions with different thicknesses. 
     Although only the conductive pattern CP 1  and the TIV  37  aside the encapsulant  48   a  are illustrated as having the adhesion promoter layer  18   a ,  38   a  thereon, respectively, the disclosure is not limited thereto. The adhesion promoter layer may be formed on surfaces of any traces, vias of the RDL structure or interconnection structure or through vias at any location if required, to improve the adhesion to adjacent layers. 
       FIG.  12    illustrates a manufacturing method of a semiconductor device in accordance with some embodiments. Although the method is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included. 
     At act S 100 , a first conductive pattern is formed on a first polymer layer.  FIG.  5 A ,  FIG.  6 A  to  FIG.  6 C ,  FIG.  9 A  and  FIG.  9 B  illustrate views corresponding to some embodiments of act S 100 . 
     At act S 102 , a first adhesion promoter layer is formed on the first conductive pattern, wherein the first adhesion promoter layer is in direct contact with the first conductive pattern.  FIG.  5 B ,  FIG.  6 A  to  FIG.  6 C ,  FIG.  9 A  and  FIG.  9 B  illustrate views corresponding to some embodiments of act S 102 . 
     At act S 104 , a second polymer layer is formed on the first polymer layer, wherein the second polymer layer is in direct contact with the first adhesion promoter layer.  FIG.  5 C ,  FIG.  6 A  to  FIG.  6 C ,  FIG.  9 A  and  FIG.  9 B  illustrate views corresponding to some embodiments of act S 104 . 
     At act S 106 , a first die is placed over a first side of the first polymer layer.  FIG.  5 E  illustrates a view corresponding to some embodiments of act S 106 . 
     At act S 108 , a second die is placed at a second side of the first polymer layer, the second side of the first polymer layer being opposite the first side of the first polymer layer, wherein the second die is electrically connected to the first die through the first conductive pattern.  FIG.  5 I  illustrates a view corresponding to some embodiments of act S 108 . 
     In the embodiments of the disclosure, the adhesion promoter layer is respectively formed between the conductive layer and the polymer layer and between the TIV and the encapsulant, and chemical bonds are respectively formed between the conductive layer and the adhesion promoter layer and between the TIV and the adhesion promoter layer. Thus, the adhesion between the conductive layer and the polymer layer and between the TIV and the encapsulant is improved, and the delamination or crack between the conductive layer and the polymer layer and between the TIV and the encapsulant is avoided or reduced. Accordingly, the dent issue due to the delamination or crack is also prevented or reduced. Further, the oxidation of the conductive layer and the TIV may be avoided or reduced. Therefore, product yield and the reliability of the package structure are improved. 
     In the embodiments of the disclosure, the adhesion promoter layer is formed between the TIV and the encapsulant, and chemical bonds are formed between the TIV and the adhesion promoter layer, so as to improve the adhesion between the TIV and the encapsulant and avoid or reduce the delamination or crack between the TIV and the encapsulant. Further, the oxidation of the TIV may be avoided or reduced. Therefore, product yield and the reliability of the package structure are improved. 
     In accordance with some embodiments of the disclosure, a package structure includes a die, a TIV, an encapsulant, an adhesion promoter layer, a RDL structure and a conductive terminal. The TIV is laterally aside the die. The encapsulant laterally encapsulates the die and the TIV. The adhesion promoter layer is sandwiched between the TIV and the encapsulant. The RDL structure is electrically connected to the die and the TIV. The conductive terminal is electrically connected to the die through the RDL structure. 
     In accordance with alternative embodiments, a package structure includes a die, a TIV, an adhesion promoter layer, an encapsulant, a first RDL structure, a second RDL structure and a conductive terminal. The TIV is laterally aside the die. The adhesion promoter layer laterally surrounds the TIV. The encapsulant laterally encapsulates the die, the adhesion promoter layer and the TIV. The first RDL structure is located on a back side of the die. The second RDL structure is located on a front side of the die. The conductive terminal is electrically connected to the die through the second RDL structure. 
     In accordance with some embodiments of the disclosure, a method of forming a package structure includes the following processes. A TIV is formed laterally aside a die. An adhesion promoter layer is formed on sidewalls of the TIV. An encapsulant is formed to laterally encapsulate the die, the adhesion promoter layer and the TIV. A RDL structure is formed on the die and the encapsulant. A conductive terminal is formed to electrically connect to the die RDL structure. 
     In accordance with some embodiments of the disclosure, a semiconductor device includes a first die, a second die, a first redistribution layer (RDL) structure and a connector. The RDL structure is disposed between the first die and the second die and is electrically connected to the first die and the second die and includes a first polymer layer, a second polymer layer, a first conductive pattern and an adhesion promoter layer. The adhesion promoter layer is between and in direct contact with the second polymer layer and the first conductive pattern. The connector is disposed in the first polymer layer and in direct contact with the second die and the first conductive pattern. 
     In accordance with some embodiments of the disclosure, a semiconductor device includes a first redistribution layer (RDL) structure, a first die, a through via and an encapsulant. The first RDL structure includes a first polymer layer, a first conductive pattern and an adhesion promoter layer. The first die is over the first RDL structure. The through via is over the first RDL structure, and the through via is adjacent the first die, wherein the through via is physically separated from the first conductive pattern by a portion of the first polymer layer between the through via and the first conductive pattern. The encapsulant is over the first RDL structure and is between the first die and the through via. The adhesion promoter layer extends between a sidewall of the through via and the encapsulant. 
     In accordance with some embodiments of the disclosure, a method of forming a semiconductor device is as follows. A first conductive pattern is formed on a first polymer layer. A first adhesion promoter layer is formed on the first conductive pattern, wherein the first adhesion promoter layer is in direct contact with the first conductive pattern. A second polymer layer is formed on the first polymer layer, wherein the second polymer layer is in direct contact with the first adhesion promoter layer. A first die is placed over a first side of the first polymer layer. A second die is placed at a second side of the first polymer layer, the second side of the first polymer layer being opposite the first side of the first polymer layer, wherein the second die is electrically connected to the first die through the first conductive pattern. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.