Patent Publication Number: US-9835685-B2

Title: Test circuit and method for controlling test circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2014-244322, filed on Dec. 2, 2014, the entire contents of which are incorporated herein by reference. 
     FIELD 
     The embodiments discussed herein are related to a test circuit and a method for controlling a test circuit. 
     BACKGROUND 
     In a system in package (SiP), a plurality of semiconductor chips are embedded in a single package. 
     Related technology is disclosed in Japanese Laid-open Patent Publication No. 2004-317352, Japanese Laid-open Patent Publication No. 2011-81887, Japanese Laid-open Patent Publication No. 2013-105996, Japanese Laid-open Patent Publication No. 2003-309183, Japanese Laid-open Patent Publication No. 2002-185309, or Japanese Laid-open Patent Publication No. 62-169355. 
     SUMMARY 
     According to an aspect of the embodiments, test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device from outside the semiconductor device; signal paths provided between at least one semiconductor chip included in the semiconductor chips and another semiconductor chip included in the semiconductor chips, data which is supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the at least one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating an expected value via one or more signal paths included in the signal paths, a select signal indicating the one or more signal paths which transmit the data indicating the expected value; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device from among the signal paths. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  illustrates an example of a test circuit; 
         FIG. 2  illustrates another example of a test circuit; 
         FIG. 3  illustrates an example of a select signal generating unit and a path selecting unit; 
         FIG. 4  illustrates an example of a first switching unit; 
         FIG. 5  illustrates an example of a second switching unit; 
         FIG. 6  illustrates an example of a majority determination selecting unit; 
         FIG. 7  illustrates an example of a control method of a test circuit; 
         FIG. 8  illustrates another example of a test circuit; 
         FIG. 9  illustrates an example of a first switching unit; 
         FIG. 10  illustrates another example of a test circuit; and 
         FIG. 11  illustrates an example of a select signal generating unit. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Input/output terminals of a plurality of semiconductor chips are coupled to each other by bumps such as micro-bumps. In a semiconductor device in which a plurality of semiconductor chips are stacked, a failure may be caused in a signal path including an I/O terminal, a micro-bump or the like by manufacturing defects or the like of the micro-bump. For example, a failure in which a signal path including an I/O terminal, a micro-bump or the like is open, a failure in which wires adjacent to each other are short-circuited, or the like is caused. Accordingly, after two semiconductor chips are coupled to each other via a bump, a coupling between the semiconductor chips is tested. 
     A decrease of a yield (non-defective rate of a semiconductor chip) due to a bonding failure of micro-bumps increases the cost of an SiP. Therefore, for example, in a semiconductor device in which a plurality of semiconductor chips are stacked, a failure is avoided by bypassing a failure portion. 
     In order to detect a failure portion of a signal path between semiconductor chips, for example, a scan flip flop (a flip flop circuit designed for a scan test) which is provided in correspondence with each terminal of a test target is used. For example, in a test circuit formed in a semiconductor device, test data is set to a scan flip flop of one of the semiconductor chips coupled to each other via a scan chain or the like. 
     A test circuit transmits test data from a scan flip flop of one of semiconductor chips coupled to each other to a scan flip flop of the other of the semiconductor chips. The test data is retained in the scan flip flop of the other semiconductor chip. The test circuit acquires the test data retained in the scan flip flop of the other of the semiconductor chip via the scan chain or the like, and detects a failure portion of a signal path between semiconductor chips based on the acquired data. 
     A data retaining circuit in which an affection of malfunction of a flip flop circuit is reduced is provided by redundancy of the flip-flop circuit. For example, the data retaining circuit retains input data in three flip flops circuits, and outputs data according to a logic value which corresponds to a majority of output data of three flip flop circuits. In a semiconductor integrated circuit which is fabricated by using silicon on insulator (SOI) technology, a test circuit having a redundant configuration is provided. 
     A failure may be caused on a signal path for testing which is used when data is set in a scan flip flop circuit, a signal path for testing which is used when the data retained in the scan flip flop is acquired, or the like, among signal paths between chips coupled to each other. In this case, it may be difficult to perform a test for detecting a failure portion of a signal path between semiconductor chips. For example, if a failure occurs in a signal path for test, among signal paths between chips coupled to each other, the failure may not be avoided by bypassing a failure portion. Thus, yield of a semiconductor device may decrease, and a manufacturing cost of the semiconductor device may increase. 
     Arrows of dashed lines illustrated in the figures indicate a signal flow of data or the like. 
       FIG. 1  illustrates an example of a test circuit. A test circuit  10  tests a semiconductor device SEM 1  that includes a plurality of semiconductor chips  100  and  200 . The semiconductor device SEM 1  may be a system in package (SiP) in which the plurality of semiconductor chips  100  and  200  are embedded in a single package. Input/output (I/O) terminals of the plurality of semiconductor chips  100  and  200  are coupled to each other by a bump such as a micro-bump. 
     The test circuit  10  includes terminals TI 1 , TI 10 , TI 11 , TI 20 , TI 21 , TO 1 , TO 10 , and TO 20 , a select signal generating unit  20 , a path selecting unit  30 , and a test unit  40 . 
     The test input terminal TI 1  is a test input terminal to which data for testing the semiconductor device SEM 1  is input from the outside of the semiconductor device SEM 1 . The test output terminal TO 1  is an output terminal from which data corresponding to test results of the respective semiconductor chips  100  and  200  is output to the outside of the semiconductor device SEM 1 . The test input terminal TI 1  and the test output terminal TO 1  correspond to external terminals of the semiconductor device SEM 1 . For example, the test input terminal TI 1  and the test output terminal TO 1  are disposed on a surface of the semiconductor chip  100 , for example, a surface on which a logic circuit that performs a function of the semiconductor chip  100  is formed. The terminals TI 10 , TI 11  and TO 10  are disposed on a back surface of the semiconductor chip  100 . Data that is supplied to the test input terminal TI 1  is transmitted to the terminals TI 10  and TI 11  via a through-electrode or the like that passes through a substrate of the semiconductor chip  100 . Data that is input to the terminal TO 10  is transmitted to the test output terminal TO 1  via the through-electrode or the like that passes through the substrate of the semiconductor chip  100 . The terminals TI 20 , TI 21 , and TO 20  are disposed on a surface of the semiconductor chip  200 , and are respectively coupled to the terminals TI 10 , TI 11  and TO 10  via the bumps or the like. 
     For example, a signal path PT 1  between the terminals TI 10  and TI 20  and a signal path PT 2  between the terminals TI 11  and TI 21  are signal paths for test through which the data supplied to the test input terminal TI 1  is transmitted. A signal path PT 3  between the terminals TO 10  and TO 20  is a signal path for test through which the data supplied to the test output terminal TO 1  is transmitted. Hereinafter, the signal paths for test PT 1 , PT 2 , and PT 3  may be referred to as test paths. The test circuit  10  includes a plurality of test paths PT 1  and PT 2  through which the data supplied to the test input terminal TI 1  is redundantly transmitted. 
     The select signal generating unit  20  is provided in the semiconductor chip  200  that is at least one of the plurality of semiconductor chips  100  and  200 , and is coupled to another semiconductor chip  100  via the plurality of signal paths PT 1  and PT 2 . For example, the select signal generating unit  20  receives data D 10  with a logic value equal to a certain expected value from the test input terminal TI 1  via another semiconductor chip  100  and the plurality of signal paths PT 1  and PT 2 , and outputs select signals SELCTL to the path selecting unit  30 . 
     For example, a test device that tests the semiconductor device SEM 1  supplies the data D 10  with a logic value equal to the expected value to the test input terminal TI 1 . The data D 10  with a logic value equal to the expected value is transmitted to the select signal generating unit  20  from the test input terminals TI 1  via the plurality of signal paths PT 1  and PT 2 . The select signal generating unit  20  compares each of the data D 10  which is received via the plurality of signal paths PT 1  and PT 2  with the expected value, and generates the select signal SELCTL, based on the comparison results. 
     For example, if a failure, for example, an open circuit, a short circuit, or the like of the micro-bump is caused in the signal path PT 2 , among the plurality of signal paths PT 1  and PT 2 , the data D 10  transmitted to the select signal generating unit  20  via the signal path PT 2  does not coincide with the expected value. The data D 10  transmitted to the select signal generating unit  20  via the signal path PT 1  coincides with the expected value. In this case, the select signal generating unit  20  generates the select signals SELCTL indicating the signal path PT 1 . Upon receiving the data D 10  indicating the expected value via one of the plurality of signal paths PT 1  and PT 2 , the select signal generating unit  20  generates the select signals SELCTL indicating the signal paths PT through which the data D 10  indicating the expected value is transmitted. 
     The path selecting unit  30  is disposed in the semiconductor chip  200  including the select signal generating unit  20 , and is coupled to the plurality of signal paths PT 1  and PT 2 . The path selecting unit  30  selects the signal paths PT which are used when the semiconductor device SEM 1  is tested, among the plurality of signal paths PT 1  and PT 2 , based on the select signal SELCTL. For example, if a failure occurs in the signal path PT 2 , among the plurality of signal paths PT 1  and PT 2 , the path selecting unit  30  receives the select signal SELCTL indicating the signal path PT 1  from the select signal generating unit  20 . 
     In this case, the path selecting unit  30  selects the signal path PT 1  indicating the select signal SELCTL, among the plurality of signal paths PT 1  and PT 2 , as the signal paths PT between the test unit  40  of the semiconductor chip  200  and another semiconductor chip  100 . The path selecting unit  30  transmits the data received from the test input terminals TI 1  via the signal path PT 1  to the test unit  40  of the semiconductor chip  200 . 
     The test unit  40  is provided in each of the plurality of semiconductor chips  100  and  200 , and tests the semiconductor device SEM 1 . For example, the test unit  40  of the semiconductor chip  200  tests the semiconductor chip  200 , using the data transmitted from the path selecting unit  30 . The test unit  40  of the semiconductor chip  200  transmits the data according to the test results to the test output terminal TO 1  via the terminals TO 20  and TO 10 . For example, the test unit  40  of the semiconductor chip  100  tests the semiconductor chip  100 , using the data supplied to the test input terminal TI 1 . The test unit  40  of the semiconductor chip  100  transmits the data according to the test results to the test output terminal TO 1 . 
     In the test circuit  10 , if one of the test paths PT 1  and PT 2  through which the data supplied to the test input terminal TI 1  is transmitted fails, a test for detecting a failure portion of a signal path between the semiconductor chips  100  and  200  is performed. Therefore, the failure may be avoided by bypassing the failure portion. A decrease of yield due to a bonding failure between the semiconductor chips  100  and  200  may be suppressed, and a manufacturing cost of the semiconductor device SEM 1  may be reduced. 
     For example, a test device that tests the semiconductor device SEM 1  supplies the data D 10  with a logic value equal to the expected value to the test input terminal TI 1 . After the path selecting unit  30  selects the signal paths PT that are used at the time of testing the semiconductor device SEM 1 , the test device supplies the data that tests the semiconductor device SEM 1  to the test input terminal TI 1 . The test circuit  10  performs a test for detecting a failure portion of a signal path between the semiconductor chips  100  and  200 , using the data supplied to the test input terminal TI 1 . 
     For example, in a configuration of the test circuit  10 , the test paths PT (PT 1 , PT 2 ) through which the data supplied to the test input terminal TI 1  is transmitted may be configured by three or more redundant signal paths. For example, the test path PT 3  may be redundant. In this case, the select signal generating unit  20  and the path selecting unit  30  which receive data through the redundant test path PT 3 , for example, the two test paths are provided in the semiconductor chip  100 . For example, the test circuit  10  may be embedded in the semiconductor device SEM 1  in which three semiconductor chips are stacked. In this case, the select signal generating unit  20  and the path selecting unit  30  may be provided in at least two of the three semiconductor chips. The test circuit  10  may be embedded in the semiconductor device SEM 1  in which four or more semiconductor chips are stacked. 
     In  FIG. 1 , the test circuit  10  includes the path selecting unit  30  that receives the data supplied to the test input terminal TI 1  via the plurality of signal paths PT 1  and PT 2 . The path selecting unit  30  selects the signal paths PT that are used at the time of testing the semiconductor device SEM 1 , among the plurality of signal paths PT 1  and PT 2 , based on the select signals SELCTL received from the select signal generating unit  20 . Upon receiving the data D 10  indicating the expected value via one of the plurality of signal paths PT 1  and PT 2 , the select signal generating unit  20  generates the select signals SELCTL indicating the signal paths PT through which the data D 10  indicating the expected value is transmitted. 
     If one of the signal paths PT 1  and PT 2  through which the data supplied to the test input terminal TI 1  is transmitted fails, a test for detecting a failure portion of the signal path between the plurality of semiconductor chips  100  and  200  is performed. Therefore, the failure may be avoided by bypassing the failure portion. Yield of the semiconductor device SEM 1  may increase. 
     For example, when the semiconductor device SEM 1  is tested, if the test circuit  10  which verifies operations of the semiconductor chips CHIP does not perform a normal operation, it may be determined that a logic circuit does not operate, even if the logic circuit which realizes the functions of the semiconductor chips CHIP is normal. Since abnormality of a bonding portion which bonds the plurality of semiconductor chips CHIP is avoided, yield of the semiconductor device SEM 1  may increase. 
       FIG. 2  illustrates another example of a test circuit. In  FIG. 2 , the same or similar symbols or reference numerals will be attached to substantially the same elements as or similar elements to the elements illustrated in  FIG. 1 , and detailed description thereof will be omitted or reduced. A test circuit TESC tests a semiconductor device SEM 2  which includes a plurality of semiconductor chips CHIP (CHIP 1 , CHIP 2 , CHIP 3 ). The semiconductor device SEM 2  may be an SiP in which the plurality of semiconductor chips CHIP are embedded in a single package. I/O terminals of the plurality of semiconductor chips CHIP are coupled to each other by bumps such as micro-bumps. For example, terminals which are disposed on a back surface of the semiconductor chip CHIP 1  are bonded to terminals, which are disposed on a surface of the semiconductor chip CHIP 2 , by bumps. Terminals which are disposed on a back surface of the semiconductor chip CHIP 2  are bonded to terminals, which are disposed on a surface of the semiconductor chip CHIP 3 , by bumps. 
     The surfaces of the respective semiconductor chips CHIP are surfaces on which logic circuits for realizing the function of the respective semiconductor chips CHIP are formed. The terminals disposed on the back surfaces of the respective semiconductor chips CHIP are coupled to the circuits or the like in the respective semiconductor chips CHIP via through-electrodes which pass through substrates of the respective semiconductor chips CHIP. 
     The semiconductor device SEM 2  may accept a test method standardized by a joint test action group (JTAG) as, for example, IEEE1149.1. Hereinafter, IEEE1149.1 may be referred to as the JTAG. For example, terminals for interface signals TCK (test clock), TMS (test mode select), TRST (test reset), TDI (test data in), and TDO (test data out) which are referred to as TAP (test access port), are provided in the semiconductor device SEM 2 . 
     The test circuit TESC includes select signal generating units SGEN, path selecting units SEL, buffers BF, first switching units SWA, second switching units SWB, a switch control unit SWCTL, majority determination selecting units MAJ, and test units TAP corresponding to the JTAG. The test circuit TESC includes the terminals TDI, TDO, TCK, TMS, and TRST which are provided in the respective semiconductor chips CHIP. 
     A terminal TDI 1  is a test input terminal which receives data TDI for testing the semiconductor device SEM 2 , for example, data scanned in the respective semiconductor chips CHIP from the outside of the semiconductor device SEM 2 . A terminal TDO 1  is a test output terminal which outputs data TDO corresponding to the test results of the semiconductor chips CHIP, for example, data scanned out from the respective semiconductor chips CHIP to the outside of the semiconductor device SEM 2 . Hereinafter, the data TDI and TDO is referred to as signals TDI and TDO. 
     A terminal TCK 1  is a test clock terminal which receives, for example, the clock signal TCK for testing (hereinafter, may be referred to as test clock TCK) from the outside of the semiconductor device SEM 2 . 
     A terminal TMS 1  is a test mode select terminal which receives a signal TMS for selecting a test mode (hereinafter, may be referred to as a test mode select TMS) from the outside of the semiconductor device SEM 2 . A terminal TRST 1  is a test reset terminal which receives a signal TRST for resetting a state of the test unit TAP (hereinafter, may be referred to as a test reset TRST) from the outside of the semiconductor device SEM 2 . 
     For example, the test input terminal TDI 1 , the test output terminal TDO 1 , the test clock terminal TCK 1 , the test mode select terminal TMS 1 , and the test reset terminal TRST 1  correspond to the external terminals of the semiconductor device SEM 2 . For example, the test input terminal TDI 1 , the test output terminal TDO 1 , the test clock terminal TCK 1 , the test mode select terminal TMS 1 , and the test reset terminal TRST 1  are disposed on a surface of the semiconductor chip CHIP 1 . 
     Terminals TDI 10 , TDI 11 , TDO 10 , TDO 11 , TCK 10 , TMS 10 , TMS 11 , TMS 12 , TRST 10 , TRST 11 , and TRST 12  are disposed on a back surface of the semiconductor chip CHIP 1 . Terminals TDI 20 , TDI 21 , TDO 20 , TDO 21 , TCK 20 , TMS 20 , TMS 21 , TMS 22 , TRST 20 , TRST 21 , and TRST 22  are disposed on a surface of the semiconductor chip CHIP 2 . 
     The terminals TDI 20 , TDI 21 , TDO 20 , and TDO 21  are respectively coupled to the terminals TDI 10 , TDI 11 , TDO 10 , and TDO 11  via bumps or the like. In addition, the terminals TCK 20 , TMS 20 , TMS 21 , TMS 22 , TRST 20 , TRST 21 , and TRST 22  are coupled to the terminals TCK 10 , TMS 10 , TMS 11 , TMS 12 , TRST 10 , TRST 11 , and TRST 12  via bumps or the like. 
     Terminals TDI 22 , TDI 23 , TDO 22 , TDO 23 , TCK 21 , TMS 23 , TMS 24 , TMS 25 , TRST 23 , TRST 24 , and TRST 25  are disposed on a back surface of the semiconductor chip CHIP 2 . Terminals TDI 30 , TDI 31 , TDO 30 , TDO 31 , TCK 30 , TMS 30 , TMS 31 , TMS 32 , TRST 30 , TRST 31 , and TRST 32  are disposed on a surface of the semiconductor chip CHIP 3 . 
     The terminals TDI 30 , TDI 31 , TDO 30 , and TDO 31  are respectively coupled to the terminals TDI 20 , TDI 21 , TDO 20 , and TDO 21  via bumps or the like. In addition, the terminals TCK 30 , TMS 30 , TMS 31 , TMS 32 , TRST 30 , TRST 31 , and TRST 32  are coupled to the terminals TCK 20 , TMS 20 , TMS 21 , TMS 22 , TRST 20 , TRST 21 , and TRST 22  via bumps or the like. 
     Signal paths PT 10  to PT 20  between the semiconductor chips CHIP 1  and CHIP 2 , and signal paths PT 21  to PT 31  between the semiconductor chips CHIP 2  and CHIP 3  are signal paths for testing through which signals for testing, for example, interface signals such as the data TDI are transmitted. Hereinafter, the signal paths for testing PT 10  to PT 31  may be referred to as test paths. 
     For example, the signal path PT 10  between the terminals TDI 10  and TDI 20  and the signal path PT 11  between the terminals TDI 11  and TDI 21  are test paths between the semiconductor chips CHIP 1  and CHIP 2 , through which the data TDI supplied to the test input terminal TDI 1  is transmitted. The signal path PT 21  between the terminals TDI 22  and TDI 30  and the signal path PT 22  between the terminals TDI 23  and TDI 31  are test paths between the semiconductor chips CHIP 2  and CHIP 3 , through which the data TDI supplied to the test input terminal TDI 1  is transmitted. The test circuit TESC includes a plurality of test paths PT 10 , PT 11 , PT 21 , and PT 22  through which the data TDI supplied to the test input terminal TDI 1  is redundantly transmitted. 
     The semiconductor chip CHIP 1  is a part of the test circuit TESC, and includes a switch control unit SWCTL, first switching units SWA 1  to SWA 4 , a select signal generating unit SGEN 2 , a path selecting unit SEL 2 , a second switching unit SWB, the test unit TAP, and buffers BF 1  to BF 9 . 
     A switch control signal (hereinafter, may be referred to as a control signal) which is output from the switch control unit SWCTL to the first switching unit SWA 1  is determined by a state of the TAP controller in the test unit TAP. In  FIG. 2 , for the sake of easy viewing, signal lines between the switch control unit SWCTL and the first switching units SWA 2  to SWA 4 , the second switching unit SWB, the test unit TAP, or the like may be omitted. 
     The first switching units SWA (SWA 1  to SWA 4 ) are set to one of an internal transmission state and a passing-through state, based on a control signal which is received from the switch control unit SWCTL. In the internal transmission state, data which is received by the first switching units SWA, for example, the data TDI of the first switching unit SWA 1  is transmitted to the test units TAP of the semiconductor chips CHIP thereof. In the passing-through state, the data which is received by the first switching units SWA, for example, the data TDI in the first switching unit SWA 1  is transmitted to another semiconductor chip CHIP. 
     An input terminal of the first switching unit SWA 1 , for example, a terminal IN 10  illustrated in  FIG. 4  is coupled to the test input terminal TDI 1 . One of two output terminals of the first switching unit SWA 1 , for example, one of terminals OUT 10  and OUT 11  illustrated in  FIG. 4  is coupled to the terminals TDI 10  and TDI 11  via the buffers BF 1  and BF 2 , and the other of the two output terminals of the first switching unit SWA 1  is coupled to the test unit TAP. 
     For example, if the control signal which is received from the switch control unit SWCTL indicates the internal transmission state, the first switching unit SWA 1  transmits the data TDI transmitted from the test input terminal TDI 1  to the test unit TAP of the semiconductor chip CHIP 1 . If the control signal which is received from the switch control unit SWCTL indicates the passing-through state, the first switching unit SWA 1  transmits the data TDI transmitted from the test input terminal TDI 1  to the semiconductor chips CHIP 2  via the signal paths PT 10  and PT 11 . Accordingly, the data TDI supplied to the test input terminal TDI 1  is transmitted to a select signal generating unit SGEN 1  and a path selecting unit SEL 1  of the semiconductor chip CHIP 2  via the plurality of signal paths PT 10  and PT 11 . 
     An input terminal of the first switching unit SWA 2  is coupled to the test clock terminal TCK 1 . One of two output terminals of the first switching unit SWA 2  is coupled to the terminal TCK 10  via the buffer BF 3 , and the other of the two output terminals of the first switching unit SWA 2  is coupled to the test unit TAP. 
     An input terminal of the first switching unit SWA 3  is coupled to the test reset terminal TRST 1 . One of two output terminals of the first switching unit SWA 3  is coupled to the terminals TRST 10 , TRST 11 , and TRST 12  via the buffers BF 4 , BF 5 , and BF 6 , respectively, and the other of the two output terminals of the first switching unit SWA 3  is coupled to the test unit TAP. 
     An input terminal of the first switching unit SWA 4  is coupled to the test mode select terminal TMS 1 . One of two output terminals of the first switching unit SWA 4  is coupled to the terminals TMS 10 , TMS 11 , and TMS 12  via the buffers BF 7 , BF 8 , and BF 9 , respectively, and the other of the two output terminals of the first switching unit SWA 4  is coupled to the test unit TAP. 
     For example, if the first switching units SWA of the semiconductor chip CHIP 1  are set to the internal transmission state, the test unit TAP of the semiconductor chip CHIP 1  receives the signals TDI, TCK, TMS, and TRST from the terminals TDI 1 , TCK 1 , TMS 1 , and TRST 1 , respectively. If the first switching units SWA of the semiconductor chip CHIP 1  are set to the passing-through state, the signals TDI, TCK, TMS, and TRST supplied to the terminals TDI 1 , TCK 1 , TMS 1 , and TRST 1 , respectively, are transmitted to the semiconductor chip CHIP 2 . Even if the first switching units SWA 2  to SWA 4  are set to the passing-through state, the signals TCK, TMS, and TRST may be transmitted to the test unit TAP of the semiconductor chips CHIP thereof. 
     The test unit TAP performs a test corresponding to the JTAG. The test unit TAP includes a TAP controller, a command register, a data register, and the like. The TAP controller in the test unit TAP is a state machine of a synchronization type which is controlled by the signals TCK, TMS, and TRST. For example, the TAP controller generates control signals of the command register, the data register, or the like, for example, a drive clock, based on the signals TCK, TMS, and TRST. 
     A state of the control signal which is output from the switch control unit SWCTL is controlled by a state transition (mode) of the TAP controller. One state of the control signal may be allocated to a plurality of modes of the TAP controller. 
     For example, the command register in the test unit TAP is used for selecting the data register which performs a scan operation. For example, the command register receives the data TDI indicating a command code or the like, and a control signal from the TAP controller. The command code is set in the command register. For example, the data TDI indicating the command code or the like is supplied to the test input terminal TDI 1  from a test device which tests the semiconductor device SEM 2 . 
     The data register in the test unit TAP is a boundary scan register, a bypass register, or the like. For example, the data register receives a control signal from the TAP controller, and the data TDI supplied to the test input terminal TDI 1 , and retains the received data TDI. The data register transmits the retained data TDI to the test output terminal TDO 1  as the data TDO. The test unit TAP transmits the data TDO corresponding to the test results of the semiconductor device SEM 2  to the test output terminal TDO 1 . 
     Two input terminals of the select signal generating unit SGEN 2  are coupled to the terminals TDO 10  and TDO 11 . For example, the select signal generating unit SGEN 2  of the semiconductor chip CHIP 1  is coupled to the terminals TDO 20  and TDO 21  of the semiconductor chip CHIP 2  via the signal paths PT 19  and PT 20 , respectively. 
     For example, the select signal generating unit SGEN 2  receives the data TDO with a logic value equal to a certain expected value from the test unit TAP of another semiconductor chip CHIP 2  via the plurality of signal paths PT 19  and PT 20 , and outputs the select signals SELCTL to the path selecting unit SEL 2 . 
     For example, if a failure occurs in the signal path PT 20 , among the plurality of signal paths PT 19  and PT 20 , the select signal generating unit SGEN 2  receives the data TDO with a logic value equal to the expected value via the signal path PT 19 . In this case, the select signal generating unit SGEN 2  generates the select signals SELCTL indicating the signal path PT 19 , and outputs the generated select signals SELCTL to a control terminal of the path selecting unit SEL 2 . 
     If the select signal generating unit SGEN 2  receives the data TDO indicating the expected value via one of the plurality of signal paths PT 19  and PT 20 , the select signal generating unit SGEN 2  generates the select signals SELCTL indicating the signal paths PT that transmits the data TDO indicating the expected value. 
     When the test paths PT are selected, the data TDO which is transmitted from the semiconductor chip CHIP 2  to the semiconductor chip CHIP 1  is data TDI transmitted to the test unit TAP of the semiconductor chip CHIP 2  from the test input terminal TDI 1  via the semiconductor chip CHIP 1  or the like. Therefore, for example, the select signal generating unit SGEN 2  receives the data TDO with a logic value equal to the certain expected value from the test input terminal TDI 1  via another the semiconductor chip CHIP 2  and the plurality of signal paths PT 19  and PT 20 . 
     The two input terminals of the path selecting unit SEL 2  are coupled to the terminals TDO 10  and TDO 11 . For example, the path selecting unit SEL 2  is coupled to the terminals TDO 20  and TDO 21  of the semiconductor chip CHIP 2  via the signal paths PT 19  and PT 20 , respectively. 
     The path selecting unit SEL 2  selects the signal paths PT which are used at the time of testing the semiconductor device SEM 2 , among the plurality of signal paths PT 19  and PT 20 , based on the select signal SELCTL. For example, if a failure occurs in the signal path PT 20 , among the plurality of signal paths PT 19  and PT 20 , the path selecting unit SEL 2  receives the select signals SELCTL indicating the signal path PT 19  from the select signal generating unit SGEN 2 . 
     In this case, the path selecting unit SEL 2  selects the signal path PT 19  indicated by the select signal SELCTL, among the plurality of signal paths PT 19  and PT 20  as a signal path between the semiconductor chips CHIP 1  and CHIP 2 . For example, the path selecting unit SEL 2  transmits the data TDO received from the test unit TAP of another semiconductor chip CHIP 2  via the signal path PT 19  to the second switching unit SWB. 
     The second switching unit SWB is set to one of the internal transmission state and the passing-through state, based on the control signal received from the switch control unit SWCTL. In the internal transmission state, the second switching unit SWB transmits the data received from the test units TAP of the semiconductor chips CHIP thereof to the test output terminal TDO 1 . In addition, in the passing-through state, the second switching unit SWB transmits the data received from the test unit TAP of another semiconductor chip CHIP to the test output terminal TDO 1 . 
     For example, one of two input terminals of the second switching unit SWB, for example, one of terminals IN 20  and IN 21  illustrated in  FIG. 5  is coupled to the path selecting unit SEL 2 , and the other of the two input terminals the second switching unit SWB is coupled to the test unit TAP. An output terminal of the second switching unit SWB, for example, a terminal OUT 20  illustrated in  FIG. 5  is coupled to the test output terminal TDO 1 . 
     For example, if a control signal received from the switch control unit SWCTL indicates an internal transmission state, the second switching unit SWB transmits the data TDO transmitted from the test unit TAP to the test output terminal TDO 1 . If the control signal received from the switch control unit SWCTL indicates a passing-through state, the second switching unit SWB transmits the data TDO transmitted from the path selecting unit SEL 2  to the test output terminal TDO 1 . The data TDO transmitted via the signal paths PT selected by the path selecting unit SEL 2 , among the plurality of signal paths PT 19  and PT 20 , is transmitted to the test output terminal TDO 1 . 
     The semiconductor chip CHIP 2  is a part of the test circuit TESC, and includes a switch control unit SWCTL, first switching units SWA 1  to SWA 4 , a select signal generating unit SGEN 2 , a path selecting unit SEL 2 , a second switching unit SWB, a test unit TAP, and buffers BF 1  to BF 11 . The semiconductor chip CHIP 2  is a part of the test circuit TESC, and includes a select signal generating unit SGEN 1 , a path selecting unit SEL 1 , and majority determination selecting units MAJ 1  and MAJ 2 . 
     The select signal generating unit SGEN 1  may be substantially the same as or similar to the select signal generating unit SGEN 2 . The select signal generating unit SGEN 1  receives the data TDI with a logic value equal to the certain expected value from the test input terminal TDI 1  via another semiconductor chip CHIP 1  and the plurality of signal paths PT 10  and PT 11 , and outputs the select signals SELCTL to the path selecting unit SEL 1 . 
     For example, if a failure occurs in the signal path PT 10 , among the plurality of signal paths PT 10  and PT 11 , the select signal generating unit SGEN 1  receives the data TDI with a logic value equal to the expected value via the signal path PT 11 . In this case, the select signal generating unit SGEN 1  generates the select signals SELCTL indicating the signal path PT 11 , and outputs the generated select signals SELCTL to a control terminal of the path selecting unit SEL 1 . In this way, if the select signal generating unit SGEN 1  receives the data TDI indicating the expected value via one of the plurality of signal paths PT 10  and PT 11 , the select signal generating unit SGEN 1  generates the select signals SELCTL indicating the signal paths PT through which the data TDI indicating the expected value is transmitted. 
     The path selecting unit SEL 1  may be substantially the same as or similar to the path selecting unit SEL 2 . For example, the path selecting unit SEL 1  selects the signal paths PT which are used at the time of testing the semiconductor device SEM 2 , among the plurality of signal paths PT 10  and PT 11 , based on the select signal SELCTL. 
     Two input terminals of the path selecting unit SEL 1  are coupled to the terminals TDI 20  and TDI 21 . For example, the path selecting unit SEL 1  of the semiconductor chip CHIP 2  is coupled to the terminals TDI 10  and TDI 11  of the semiconductor chip CHIP 1  via the signal paths PT 10  and PT 11 , respectively. An output terminal of the path selecting unit SEL 1  is coupled to the first switching unit SWA 1 . 
     For example, if a failure occurs in the signal path PT 10 , among the plurality of signal paths PT 10  and PT 11 , the path selecting unit SEL 1  receives the select signals SELCTL indicating the signal path PT 11  from the select signal generating unit SGEN 1 . In this case, the path selecting unit SEL 1  selects the signal path PT 11  indicated by the select signals SELCTL among the plurality of signal paths PT 10  and PT 11  as a signal path PT between the semiconductor chips CHIP 1  and CHIP 2 . For example, the path selecting unit SEL 1  transmits the data TDI received from the test input terminal TDI 1  via the signal path PT 11  to the first switching unit SWA 1 . 
     The switch control unit SWCTL may be substantially the same as or similar to the switch control unit SWCTL of the semiconductor chip CHIP 1 . The first switching units SWA (SWA 1  to SWA 4 ) may be substantially the same as or similar to the first switching units SWA of the semiconductor chip CHIP 1 . 
     An input terminal of the first switching unit SWA 1  is coupled to an output terminal of the path selecting unit SEL 1 . One of two output terminals of the first switching unit SWA 1  is coupled to the terminals TDI 22  and TDI 23  via the buffers BF 1  and BF 2 , and the other of the two output terminals of the first switching unit SWA 1  is coupled to the test unit TAP. 
     For example, the first switching unit SWA 1  which is set to the internal transmission state transmits the data TDI transmitted from the path selecting unit SEL 1  to the test unit TAP of the semiconductor chip CHIP 2 . The first switching unit SWA 1  which is set to the passing-through state transmits the data TDI transmitted from the path selecting unit SEL 1  to the select signal generating unit SGEN 1  and the path selecting unit SEL 1  of the semiconductor chip CHIP 3  via the signal paths PT 21  and PT 22 , respectively. 
     An input terminal of the first switching unit SWA 2  is coupled to the terminal TCK 20 . One of two output terminals of the first switching unit SWA 2  is coupled to the terminal TCK 21  via the buffer BF 3 , and the other of the two output terminals of the first switching unit SWA 2  is coupled to the test unit TAP. 
     An input terminal of the first switching unit SWA 3  is coupled to the output terminal of the majority determination selecting unit MAJ 1 . One of two output terminals of the first switching unit SWA 3  is coupled to the terminals TRST 23 , TRST 24 , and TRST 25  via the buffers BF 4 , BF 5 , and BF 6 , respectively, and the other of the two output terminals of the first switching unit SWA 3  is coupled to the test unit TAP. 
     An input terminal of the first switching unit SWA 4  is coupled to the output terminal of the majority determination selecting unit MAJ 2 . One of two output terminals of the first switching unit SWA 4  is coupled to the terminals TMS 23 , TMS 24 , and TMS 25  via the buffers BF 7 , BF 8 , and BF 9 , respectively, and the other of the two output terminals of the first switching unit SWA 4  is coupled to the test unit TAP. 
     The majority determination selecting units MAJ (MAJ 1 , MAJ 2 ) output the data with a logic value equal to a logic value having the majority of the logic values of, for example, three of data received by three input terminals. For example, three input terminals of the majority determination selecting unit MAJ 1  are respectively coupled to the terminals TRST 20 , TRST 21 , and TRST 22 , and an output terminal of the majority determination selecting unit MAJ 1  is coupled to the input terminal of the first switching unit SWA 3 . 
     For example, if the signal path PT 13  among the plurality of signal paths PT 13 , PT 14 , and PT 15  fails, logic values of the data transmitted from the signal paths PT 14  and PT 15  have the majority of logic values of the data transmitted from the signal paths PT 13 , PT 14 , and PT 15 . In this case, the majority determination selecting unit MAJ 1  transmits a signal TRST with a logic value equal to that of the data transmitted from the signal paths PT 14  and PT 15  to the first switching unit SWA 3 . Thus, even if one of the signal paths PT 13 , PT 14 , and PT 15  fails, the semiconductor device SEM 2  transmits the signal TRST from the semiconductor chip CHIP 1  to the semiconductor chip CHIP 2 . 
     Three input terminals of the majority determination selecting unit MAJ 2  are respectively coupled to the terminals TMS 20 , TMS 21 , and TMS 22 , and an output terminal of the majority determination selecting unit MAJ 2  is coupled to the input terminal of the first switching unit SWA 4 . For example, if the signal path PT 16  among the plurality of signal paths PT 16 , PT 17 , and PT 18  fails, the majority determination selecting unit MAJ 2  outputs a signal TMS with a logic value equal to that of the data transmitted from the signal paths PT 17  and PT 18  to the first switching unit SWA 4 . Thus, even if one of the signal paths PT 16 , PT 17 , and PT 18  fails, in the semiconductor device SEM 2 , the signal TMS is transmitted from the semiconductor chip CHIP 1  to the semiconductor chip CHIP 2 . 
     The select signal generating unit SGEN 2 , the path selecting unit SEL 2 , the second switching unit SWB and the test unit TAP may be substantially the same as or similar to the select signal generating unit SGEN 2 , the path selecting unit SEL 2 , the second switching unit SWB and the test unit TAP, respectively, in the semiconductor chip CHIP 1 . 
     Two input terminals of the select signal generating unit SGEN 2  are coupled to terminals TDO 22  and TDO 23 . For example, the select signal generating unit SGEN 2  of the semiconductor chip CHIP 2  is coupled to terminals TDO 30  and TDO 31  of the semiconductor chip CHIP 3  via signal paths PT 30  and PT 31 , respectively. An output terminal of the select signal generating unit SGEN 2  is coupled to a control terminal of the path selecting unit SEL 2 . 
     Two input terminals of the path selecting unit SEL 2  are coupled to the terminals TDO 22  and TDO 23 . For example, the path selecting unit SEL 2  is coupled to the terminals TDO 30  and TDO 31  of the semiconductor chip CHIP 3  via the signal paths PT 30  and PT 31 , respectively. An output terminal of the path selecting unit SEL 2  is coupled to input terminals of the second switching unit SWB. 
     One of the two input terminals of the second switching unit SWB is coupled to the path selecting unit SEL 2 , and the other of the two input terminals of the second switching unit SWB is coupled to the test unit TAP. An output terminal of the second switching unit SWB is coupled to the terminals TDO 20  and TDO 21  via the buffers BF 10  and BF 11 , respectively. 
     If the first switching units SWA of each of the semiconductor chips CHIP 1  and CHIP 2  are respectively set to the passing-through state and the internal transmission state, the data TDI supplied to the test input terminal TDI 1  is transmitted to the test unit TAP of the semiconductor chip CHIP 2 . The signals TCK, TMS, and TRST supplied to the terminals TCK 1 , TMS 1 , and TRST 1  are transmitted to the test unit TAP of the semiconductor chip CHIP 2 . 
     If the first switching units SWA of both the semiconductor chip CHIP 1  and CHIP 2  are set to the passing-through state, the signals TDI, TCK, TMS, and TRST supplied to the terminals TDI 1 , TCK 1 , TMS 1 , and TRST 1  are transmitted to the semiconductor chip CHIP 3 . 
     If the second switching units SWB of each of the semiconductor chips CHIP 1  and CHIP 2  are set to the passing-through state and the internal transmission state, the data TDO transmitted from the test the test unit TAP of the semiconductor chip CHIP 2  is transmitted to the test output terminal TDO 1 . If the second switching units SWB of both the semiconductor chips CHIP 1  and CHIP 2  are set to the passing-through state, the data TDO transmitted from the test unit TAP of the semiconductor chip CHIP 3  is transmitted to the test output terminal TDO 1 . 
     The semiconductor chip CHIP 3  is a part of the test circuit TESC, and includes a select signal generating unit SGEN 1 , a path selecting unit SEL 1 , majority determination selecting units MAJ 1  and MAJ 2 , a test unit TAP, and buffers BF 10  and BF 11 . The select signal generating unit SGEN 1 , the path selecting unit SEL 1 , and the majority determination selecting units MAJ 1  and MAJ 2  may be substantially the same as or similar to the select signal generating unit SGEN 1 , the path selecting unit SEL 1 , and the majority determination selecting units MAJ 1  and MAJ 2  of the semiconductor chip CHIP 2 , respectively. The test unit TAP may be substantially the same as or similar to the test unit TAP of the semiconductor chip CHIP 2 . 
     Two input terminals of the select signal generating unit SGEN 1  are coupled to terminals TDI 30  and TDI 31 . For example, the select signal generating unit SGEN 1  of the semiconductor chip CHIP 3  is coupled to the terminals TDI 22  and TDI 23  of the semiconductor chip CHIP 2  via signal paths PT 21  and PT 22 , respectively. An output terminal of the select signal generating unit SGEN 1  is coupled to a control terminal of the path selecting unit SEL 1 . 
     Two input terminals of the path selecting unit SEL 1  are coupled to the terminals TDI 30  and TDI 31 . For example, the path selecting unit SEL 1  of the semiconductor chip CHIP 3  is coupled to the terminals TDI 22  and TDI 23  of the semiconductor chip CHIP 2  via the signal paths PT 21  and PT 22 , respectively. An output terminal of the path selecting unit SEL 1  is coupled to the test unit TAP. 
     Three input terminals of the majority determination selecting unit MAJ 1  are respectively coupled to the terminals TRST 30 , TRST 31 , and TRST 32 , and an output terminal of the majority determination selecting unit MAJ 1  is coupled to the test unit TAP. Three input terminals of the majority determination selecting unit MAJ 2  are respectively coupled to the terminals TMS 30 , TMS 31 , and TMS 32 , and an output terminal of the majority determination selecting unit MAJ 2  is coupled to the test unit TAP. 
     The test unit TAP outputs the data TDO to the terminals TDO 30  and TDO 31  via the buffers BF 10  and BF 11 , respectively. If the second switching units SWB of both the semiconductor chips CHIP 1  and CHIP 2  are set to the passing-through state, the data TDO output from the test unit TAP of the semiconductor chip CHIP 3  is transmitted to the test output terminal TDO 1 . 
     If the first switching units SWA of both the semiconductor chips CHIP 1  and CHIP 2  are set to the passing-through state, the data TDI supplied to the test input terminal TDI 1  is transmitted to the test unit TAP of the semiconductor chip CHIP 3 . The signals TCK, TMS, and TRST supplied to the terminals TCK 1 , TMS 1 , and TRST 1  are transmitted to the test unit TAP of the semiconductor chip CHIP 3 . 
     In the test circuit TESC, for example, the switch control unit SWCTL may be provided inside the test unit TAP, for example, inside a TAP controller in the test unit TAP. The first switching unit SWA 4  or the like may be omitted. 
     For example, the test paths PT (PT 10 , PT 11 ) through which the data supplied to the test input terminal TI 1  is transmitted may be redundant by three or more signal paths. For example, the test circuit TESC may be embedded in the semiconductor device SEM 2  in which two semiconductor chips CHIP are stacked, for example, the semiconductor device SEM 2  in which the semiconductor chip CHIP 2  is omitted. The test circuit TESC may be embedded in the semiconductor device SEM 2  in which four or more semiconductor chips CHIP are stacked. 
       FIG. 3  illustrates an example of a select signal generating unit and a path selecting unit. The select signal generating unit and the path selecting unit which are illustrated in  FIG. 3  may be the select signal generating unit SGEN and the path selecting units SEL illustrated in  FIG. 2 . A clock CLK that is supplied to a terminal CLK illustrated in  FIG. 3  may be the clock signal TCK supplied to the test clock terminal TCK 1  illustrated in  FIG. 2 , or a clock generated based on the clock signal TCK. 
     Terminals IN 1  and IN 2  are coupled to the terminals TDI 20  and TDI 21  in the select signal generating unit SGEN 1  and the path selecting unit SEL 1  of the semiconductor chip CHIP 2 . The terminals IN 1  and IN 2  are coupled to the terminals TDI 30  and TDI 31  in the select signal generating unit SGEN 1  and the path selecting unit SEL 1  of the semiconductor chip CHIP 3 . 
     The terminals IN 1  and IN 2  are coupled to the terminals TDO 22  and TDO 23  in the select signal generating unit SGEN 2  and the path selecting unit SEL 2  of the semiconductor chip CHIP 2 . The terminals IN 1  and IN 2  are coupled to the terminals TDO 10  and TDO 11  in the select signal generating unit SGEN 2  and the path selecting unit SEL 2  of the semiconductor chip CHIP 1 . 
     A terminal OUT 1  is coupled to the first switching unit SWA 1  or the like in the path selecting unit SEL 1  of the semiconductor chip CHIP 2 . The terminal OUT 1  is coupled to the test unit TAP in the path selecting unit SEL 1  of the semiconductor chip CHIP 3 . The terminal OUT 1  is coupled to the second switching units SWB in the path selecting unit SEL 2  of the semiconductor chips CHIP 1  and CHIP 2 . 
     The select signal generating unit SGEN 1  includes shift registers SFTR 1  and SFTR 2  with n bits (n is an integer equal to or larger than 2), logical product circuits AND 1  and AND 2 , logical sum circuits OR 1 , OR 2 , and OR 3 , and flip flop circuits FFC 1  and FFC 2 . 
     The shift registers SFTR (SFTR 1 , SFTR 2 ) may be an example of data storage units which respectively store data (data transmitted to the terminals IN 1 , IN 2 ) received via a plurality of signal paths PT. For example, the shift registers SFTR operate in synchronization with the clock CLK supplied to the terminal CLK, and sequentially store the data transmitted to the terminals IN (IN 1 , IN 2 ). 
     The shift registers SFTR respectively include n flip flop circuits FF (FF 1 , FF 2 , FF 3 , FF 4 , . . . , FFn) which operate in synchronization with the clock CLK supplied to the terminal CLK. 
     For example, an input terminal of the first flip flop circuit FF 1  of the shift register SFTR 1  is coupled to the terminal IN 1 . An input terminal of the first flip flop circuit FF 1  of the shift register SFTR 2  is coupled to the terminal IN 2 . An input terminal of each of the flip flop circuits FF 2 , FF 3 , FF 4 , . . . , and FFn is coupled to output terminals of the flip flop circuits FF of the previous stage. 
     Output terminals of the flip flop circuits FF of the odd stages of the shift register SFTR 1  are coupled to an input terminal of the logical product circuit AND 1 , and output terminals of the flip flop circuits FF of the even stages are coupled to an input terminal of the logical product circuit AND 1  via inverters INV. 
     For a certain input vector that is set, a logical inversion (inverter) is inserted such that an output of the logical product circuit AND 1  increases by one. For example, the input vector may be set to “010101 . . . ”, or “101010 . . . ”. 
     The inverters INV output signals which are obtained by inverting signals received in the input terminals thereof. In  FIG. 3 , the output terminals of the flip flop circuits FF 2 , FF 4 , and FFn of the shift register SFTR 1  are respectively coupled to input terminals of inverters INV 1 , INV 2 , and INV 3 . If the flip flop circuit FFn of the final stage is the flip flop circuits FF of the odd stages, the output terminal of the flip flop circuit FFn is coupled to the input terminal of the logical product circuit AND 1 . 
     Output terminals of the flip flop circuits FF of the odd stages of the shift register SFTR 2  are coupled to an input terminal of the logical product circuit AND 2 , and output terminals of the flip flop circuits FF of the even stages are coupled to an input terminal of the logical product circuit AND 2  via inverters INV. In  FIG. 3 , the output terminals of the flip flop circuits FF 2 , FF 4 , and FFn of the shift register SFTR 2  are respectively coupled to input terminals of inverters INV 4 , INV 5 , and INV 6 . If the flip flop circuit FFn of the final stage is the flip flop circuits FF of the odd stages, the output terminal of the flip flop circuit FFn is coupled to the input terminal of the logical product circuit AND 2 . 
     The logical product circuits AND (AND 1 , AND 2 ) may be an example of a first control unit that asserts control signals CNT (CNT 1 , CNT 2 ) corresponding to the signal paths PT through which data indicating an expected value is transmitted. For example, the logical product circuit AND 1  calculates a logical product of the data received in the n input terminals, and outputs the calculation results to the input terminal of the logical sum circuit OR 1 . In addition, the logical product circuit AND 2  calculates a logical product of the data received in the n input terminals, and outputs the calculation results to the input terminal of the logical sum circuit OR 2 . 
     In  FIG. 3 , the data indicating the expected value is data with n bits in which logic values of odd-numbered bits (outputs of the flip flop circuits FF of the odd stages) are “1” and logic values of even-numbered bits (outputs of the flip flop circuits FF of the even stages) are “0”. 
     For example, if outputs of the flip flop circuits FF of the odd stages and the even stages of the shift register SFTR 1  respectively have a logic value “1” and a logic value “0”, the logical product circuit AND 1  outputs the control signal CNT 1  with a logic value “1” to the logical sum circuit OR 1 . In the same manner, if outputs of the flip flop circuits FF of the odd stages and the even stages of the shift register SFTR 2  respectively have a logic value “1” and a logic value “0”, the logical product circuit AND 2  outputs the control signal CNT 2  with a logic value “1” to the logical sum circuit OR 2 . 
     The logical sum circuits OR 1  and OR 2  calculate a logical sum of the data received in the two input terminals, and outputs the calculation results. For example, the two input terminals of the logical sum circuit OR 1  are respectively coupled to the output terminal of the logical product circuit AND 1  and the output terminal of the flip flop circuit FFC 1 , and the output terminal of the logical sum circuit OR 1  is coupled to the input terminals of the flip flop circuit FFC 1 . For example, the two input terminals of the logical sum circuit OR 2  are respectively coupled to the output terminal of the logical product circuit AND 2  and the output terminal of the flip flop circuit FFC 2 , and the output terminal of the logical sum circuit OR 2  is coupled to the input terminal of the flip flop circuit FFC 2 . 
     If data with a logic value of “1” is stored in the flip flop circuit FFC 1 , the logical sum circuit OR 1  receives the data with a logic value of “1” from the flip flop circuit FFC 1 . Therefore, if the data with a logic value of “1” is stored in the flip flop circuit FFC 1 , the logical sum circuit OR 1  outputs the data with a logic value of “1” to the flip flop circuit FFC 1  regardless of a logic value of the control signal CNT 1 . 
     In the same manner, if data with a logic value of “1” is stored in the flip flop circuit FFC 2 , the logical sum circuit OR 2  receives the data with a logic value of “1” from the flip flop circuit FFC 2 . Therefore, if the data with a logic value of “1” is stored in the flip flop circuit FFC 2 , the logical sum circuit OR 2  outputs the data with a logic value of “1” to the flip flop circuit FFC 2  regardless of a logic value of the control signal CNT 2 . 
     The flip flop circuit FFC (FFC 1 , FFC 2 ) may be an example of a select signal storage unit which stores logic values of each of a plurality of control signals CNT (CNT 1 , CNT 2 ), and outputs the select signals SELCTL (SELCTL 1 , SELCTL 2 ) based on the stored logic values. For example, the flip flop circuit FFC operates in synchronization with the clock CLK, and stores the data which is received in the input terminal. If terminal INH receives a signal with a logic value of “1”, the flip flop circuit FFC prohibits input of the clock signal CLK. For example, during a time period in which a terminal INH receives a signal with a logic value of “1”, the logic values of the data stored in the flip flop circuits FFC are not updated, even if the logic values of the data transmitted to the input terminals of the flip flop circuits FFC are changed. 
     The output terminal of the flip flop circuit FFC 1  is coupled to the input terminals of the logical sum circuits OR 1  and OR 3  and the input terminal of the logical product circuit AND 3 . For example, the select signal SELCTL 1  indicating a logic value of the data stored in the flip flop circuit FFC 1  is transmitted to the logical sum circuits OR 1  and OR 3  and the logical product circuit AND 3 . The output terminal of the flip flop circuit FFC 2  is coupled to the input terminals of the logical sum circuits OR 2  and OR 3  and the input terminal of the logical product circuit AND 4 . For example, the select signal SELCTL 2  indicating the logic value of the data which is stored in the flip flop circuit FFC 2  is transmitted to the logical sum circuit OR 2  and OR 3  and the logical product circuit AND 4 . 
     If logic values of the asserted control signals CNT are stored in a select signal storage unit, for example, the flip flop circuits FFC, the logical sum circuit OR 3  may be an example of a second control unit which suppresses an update of the logic values stored in the select signal storage unit. For example, the logical sum circuit OR 3  calculates a logical sum of the select signals SELCTL 1  and SELCTL 2  received in the two input terminals, and outputs the calculation results to the terminals INH of the flip flop circuits FFC 1  and FFC 2 . For example, if the data with a logic value of “1” is stored in one of the flip flop circuits FFC 1  and FFC 2 , the logical sum circuit OR 3  suppresses the update of the logic values of the data stored in the respective flip flop circuits FFC 1  and FFC 2 . 
     For example, if a failure occurs in the signal paths PT coupled to the terminal IN 1  of the terminals IN 1  and IN 2 , the control signal CNT 1  is maintained as a negated state, and the control signal CNT 2  is asserted. In this case, data with a logic value of “0” and data with a logic value of “1” are respectively stored in the flip flop circuits FFC 1  and FFC 2 . The logical sum circuit OR 3  receives the select signal SELCTL 1  with a logic value of “0” from the flip flop circuit FFC 1 , and receives the select signal SELCTL 2  with a logic value of “1” from the flip flop circuit FFC 2 . Therefore, the logical sum circuit OR 3  outputs a signal with a logic value of “1” to the terminal INH of the flip flop circuits FFC 1  and FFC 2 . 
     While the logical sum circuit OR 3  outputs the signal with a logic value of “1” to the terminal INH of the flip flop circuits FFC 1  and FFC 2 , the flip flop circuit FFC 1  stops an update of the logic value of “0” of the stored data. In the same manner, while the logical sum circuit OR 3  outputs the signal with a logic value of “1” to the terminal INH of the flip flop circuits FFC 1  and FFC 2 , the flip flop circuit FFC 2  stops an update of the logic value of “1” of the stored data. 
     Therefore, the select signals SELCTL 1  and SELCTL 2  are maintained as a logic value “0” and a logic value “1”. For example, during a time period after the select signals SELCTL indicating the signal paths PT through which the data indicating the expected value is transmitted are generated, the select signal generating unit SGEN may avoid the logic values of the select signals SELCTL 1  and SELCTL 2  from changing depending upon a change of the data transmitted to the terminals IN 1  and IN 2 . The select signal generating unit SGEN stably supplies the select signals SELCTL indicating the signal paths PT through which the data indicating the expected value is transmitted to the path selecting unit SEL. 
     The path selecting unit SEL includes logical product circuits AND 3  and AND 4 , and logical sum circuit OR 4 . The logical product circuits AND 3  and AND 4  calculate a logical product of data received in two input terminals, and output the calculation results. 
     The two input terminals of the logical product circuit AND 3  are respectively coupled to the input terminal IN 1  and the output terminals of the flip flop circuit FFC 1 . For example, the logical product circuit AND 3  calculates a logical product of the select signal SELCTL 1  received from the flip flop circuit FFC 1  of the select signal generating unit SGEN and data received from the terminal IN 1 , and outputs the calculation results to the logical sum circuit OR 4 . 
     The two input terminals of the logical product circuit AND 4  are respectively coupled to the input terminal IN 2  and the output terminals of the flip flop circuit FFC 2 . For example, the logical product circuit AND 4  calculates a logical product of the select signal SELCTL 2  received from the flip flop circuit FFC 2  of the select signal generating unit SGEN and data received from the terminal IN 2 , and outputs the calculation results to the logical sum circuit OR 4 . 
     The logical sum circuit OR 4  calculates a logical sum of the data received in the two input terminals, for example, a logical sum of the output signals of the logical product circuits AND 3  and AND 4 , and outputs the calculation results to the terminal OUT 1 . 
     For example, if a failure occurs in the signal paths PT coupled to the terminal IN 1  of the terminals IN 1  and IN 2 , the logical product circuit AND 3  receives the select signal SELCTL 1  of a logic value of “0” from the flip flop circuit FFC 1  of the select signal generating unit SGEN. The logical product circuit AND 3  outputs the data with a logical value of “0” to the logical sum circuit OR 4 , regardless of the logic value of the data transmitted to the terminal IN 1 . 
     If a failure occurs in the signal paths PT coupled to the terminal IN 1  of the terminals IN 1  and IN 2 , the logical product circuit AND 4  receives the select signal SELCTL 2  of a logic value of “1” from the flip flop circuit FFC 2  of the select signal generating unit SGEN. The logical product circuit AND 4  outputs the data with a logic value equal to the data transmitted to the terminal IN 2  to the logical sum circuit OR 4 . 
     Therefore, if a failure occurs in the signal paths PT coupled to the terminal IN 1  of the terminals IN 1  and IN 2 , the logical sum circuit OR 4  outputs the data with a logic value equal to the data transmitted to the terminal IN 2  to the terminal OUT 1 . 
     For example, the select signal generating unit SGEN may include a negative logical sum circuit instead of the logical product circuits AND 1  and AND 2 . In this case, the data indicating the expected value is data with n bits in which odd-numbered bits, for example, the logic values of the outputs of the flip flop circuits FF of the odd stages are “0” and even-numbered bits, for example, the logic values of the outputs of the flip flop circuits FF of the even stages are “1”. 
       FIG. 4  illustrates an example of a first switching unit. The first switching unit illustrated in  FIG. 4  may be the first switching unit SWA illustrated in  FIG. 2 . Each of the first switching units SWA (SWA 1  to SWA 4 ) includes a logical product circuits AND 10  and AND 11 , an inverter INV 10 . The logical product circuits AND 10  and AND 11  calculate a logical product of data received in two input terminals thereof, and output the calculation results. The inverter INV 10  outputs a signal which is obtained by inverting a signal received in an input terminal thereof. 
     The input terminal of the inverter INV 10  is coupled to a terminal SWSEL 1 , and an output terminal of the inverter INV 10  is coupled to one of the two input terminals of the logical product circuit AND 10 . The other of the two input terminals of the logical product circuit AND 10  is coupled to a terminal IN 10 , and the output terminal of the logical product circuit AND 10  is coupled to a terminal OUT 10 . Two input terminals of the logical product circuit AND 11  are respectively coupled to the terminals IN 10  and SWSEL 1 , and output terminal of the logical product circuit AND 11  is coupled to a terminal OUT 11 . 
     For example, the terminal SWSEL 1  receives a control signal from the switch control unit SWCTL. If the control signal received in the terminal SWSEL 1  has a logic value of “0”, a signal received in the terminal IN 10  is output from the terminal OUT 10 . If the control signal received in the terminal SWSEL 1  has a logic value of “1”, a signal received in the terminal IN 10  is output from the terminal OUT 11 . 
     For example, in the semiconductor chip CHIP 2 , the terminal IN 10  of the first switching unit SWA 1  is coupled to an output terminal of the path selecting unit SEL 1 . The terminal OUT 10  is coupled to a test input terminal (terminal receiving the data TDI) of the test unit TAP, and the terminal OUT 11  is coupled to the buffers BF 1  and BF 2 . 
       FIG. 5  illustrates an example of a second switching unit. The second switching unit illustrated in  FIG. 5  may be the second switching unit SWB illustrated in  FIG. 2 . The second switching unit SWB includes the logical product circuits AND 20  and AND 21 , a logical sum circuit OR 20 , and an inverter INV 20 . The logical product circuits AND 20  and AND 21  calculate a logical product of data received in two input terminals thereof, and output the calculation results. The logical sum circuit OR 20  calculates a logical sum of data received in two input terminals thereof, and output the calculation results. The inverter INV 20  outputs a signal which is obtained by inverting a signal received in an input terminal thereof. 
     The input terminal of the inverter INV 20  is coupled to the terminal SWSEL 1 , and an output terminal of the inverter INV 20  is coupled to one of two input terminals of the logical product circuit AND 20 . The other of the two input terminals of the logical product circuit AND 20  is coupled to the terminal IN 20 . Two input terminals of the logical product circuit AND 21  are respectively coupled to the terminals IN 21  and SWSEL 1 . Two input terminals of the logical sum circuit OR 20  are respectively coupled to the output terminals of the logical product circuits AND 20  and AND 21 , and an output terminal of the logical sum circuit OR 20  is coupled to a terminal OUT 20 . 
     For example, the terminal SWSEL 1  receives a control signal from the switch control unit SWCTL. If the control signal received in the terminal SWSEL 1  has a logic value of “0”, a signal received in the terminal IN 20  is output from the terminal OUT 20 . If the control signal received in the terminal SWSEL 1  has a logic value of “1”, a signal received in the terminal IN 21  is output from the terminal OUT 20 . 
     For example, in the semiconductor chip CHIP 2 , the terminals IN 20  and IN 21  of the second switching unit SWB are respectively coupled to a test output terminal of the test unit TAP such as a terminal from which the data TDO is output, and the output terminal of the path selecting unit SEL 2 . The terminal OUT 20  of the second switching unit SWB is coupled to the buffers BF 10  and BF 11 . 
       FIG. 6  illustrates an example of a majority determination selecting unit. The majority determination selecting unit illustrated in  FIG. 6  may be the majority determination selecting units MAJ illustrated in  FIG. 2 . The majority determination selecting unit MAJ (MAJ 1 , MAJ 2 ) includes logical product circuits AND 30 , and 31 , and AND 32 , and a logical sum circuit OR 30 . The logical product circuits AND 30 , and 31 , and AND 32  calculate a logical product of data received in two input terminals thereof, and output the calculation results. The logical sum circuit OR 30  calculates a logical sum of data received in three input terminals thereof, and outputs the calculation results. 
     The two input terminals of the logical product circuit AND 30  are respectively coupled to terminals IN 30  and IN 31 . The two input terminals of the logical product circuit AND 31  are respectively coupled to the terminals IN 30  and IN 32 . The two input terminals of the logical product circuit AND 32  are respectively coupled to the terminals IN 31  and IN 32 . The three input terminals of the logical sum circuit OR 30  are respectively coupled to the output terminals of the logical product circuits AND 30 , AND 31  and AND 32 , and the output terminal of the logical sum circuit OR 30  is coupled to a terminal OUT 30 . 
     For example, if signals received in the terminals IN 30  and IN 31  have a logic value equal to each other, signals with a logic value equal to that of the signal received in the terminals IN 30  and IN 31  are output from the terminal OUT 30 . For example, if signals received in the terminals IN 30  and IN 32  have a logic value equal to each other, signals with a logic value equal to that of the signals received in the terminals IN 30  and IN 32  are output from the terminal OUT 30 . For example, if signals received in the terminals IN 31  and IN 32  have a logic value equal to each other, signals with a logic value equal to that of the signals received in the terminals IN 31  and IN 32  are output from the terminal OUT 30 . 
     For example, in the semiconductor chip CHIP 2 , the terminals IN 30 , IN 31 , and IN 32  of the majority determination selecting unit MAJ 1  are respectively coupled to the terminals TRST 20 , TRST 21 , and TRST 22 . The terminal OUT 30  of the majority determination selecting unit MAJ 1  is coupled to the input terminal of the first switching unit SWA 3 , for example, the terminal IN 10  illustrated in  FIG. 4 . 
       FIG. 7  illustrates an example of a control method of a test circuit. In  FIG. 7 , a control method of the test circuit TESC illustrated in  FIG. 2  is illustrated. In  FIG. 7 , a control method of the test circuit TESC at the time of setting the test paths PT between the semiconductor chips CHIP 1  and CHIP 2  is illustrated. Operations S 100  to S 130 , S 200 , S 220 , S 240 , S 260 , S 280 , S 310 , and S 400  illustrates an operation of the test circuit TESC included in the semiconductor chip CHIP 1 . Operations S 210 , S 230 , S 250 , S 270 , S 290 , and S 300  illustrates an operation of the test circuit TESC included in the semiconductor chip CHIP 2 . The operations S 130  to S 270  illustrated in  FIG. 7  illustrates a flow in which setting is performed from the semiconductor chips CHIP on a lower side to the semiconductor chips CHIP on an upper side, for example, an upper chip transmission sequence. The operations S 260  to S 400  correspond to a test of an actual circuit, for example, a test of the semiconductor device SEM 2 . For example, the operations illustrated in  FIG. 7  may be controlled by a test device which tests the semiconductor device SEM 2 . In  FIG. 7 , an initial state of the first switching units SWA and an initial state of the second switching units SWB may be an internal transmission state. 
     In operation S 100 , the semiconductor chip CHIP 1  receives the signal TRST which resets a state of the test unit TAP, at the test reset terminal TRST 1 . For example, the test device asserts the signal TRST which is supplied to the test reset terminal TRST 1 . Therefore, the asserted signal TRST is transmitted to the test unit TAP of the semiconductor chip CHIP 1 , and the state of the test unit TAP of the semiconductor chip CHIP 1  is reset. 
     In operation S 110 , the semiconductor chip CHIP 1  receives the test clock TCK which is supplied from the test device, at the test clock terminal TCK 1 . Therefore, the test clock TCK is transmitted to the test unit TAP of the semiconductor chip CHIP 1 . 
     In operation S 120 , the semiconductor chip CHIP 1  receives the signal TRST which releases the reset, at the test reset terminal TRST 1 . For example, the test device negates the signal TRST which is supplied to the test reset terminal TRST 1 . Therefore, the negated signal TRST is transmitted to the test unit TAP of the semiconductor chip CHIP 1 , and processing of resetting the state of the test unit TAP of the semiconductor chip CHIP 1  terminates. 
     In operation S 130 , the semiconductor chip CHIP 1  receives the test mode select signal TMS which is supplied from the test device, at the test mode select terminal TMS 1 . Therefore, the test mode select signal TMS is transmitted to the test unit TAP of the semiconductor chip CHIP 1 , and the state of the test unit TAP is determined. 
     For example, the test device sets the state of the test unit TAP of the semiconductor chip CHIP 1  to a state for setting the test paths PT between the semiconductor chips CHIP 1  and CHIP 2 , using the test mode select signal TMS. The test device controls the switch control unit SWCTL by controlling a state of the TAP controller in the test unit TAP, and sets the first switching units SWA and the second switching units SWB of the semiconductor chip CHIP 1  to a passing-through state. 
     The signals TDI, TCK, TMS, and TRST which are supplied from the test device to the terminals TDI 1 , TCK 1 , TMS 1 , and TRST 1  are transmitted to the semiconductor chip CHIP 2 . The data TDO which is transmitted from the semiconductor chip CHIP 2  is transmitted to the test output terminal TDO 1 . 
     In operation S 200 , the semiconductor chip CHIP 1  receives the signal TRST which resets the state of the test unit TAP, at the test reset terminal TRST 1 , and transmits the received signal TRST to the semiconductor chip CHIP 2  using the three signal paths PT 13 , PT 14 , and PT 15 . Therefore, the semiconductor chip CHIP 2  receives the signal TRST which resets the state of the test unit TAP, in operation S 210 . For example, the test device asserts the signal TRST which is supplied to the test reset terminal TRST 1 . Therefore, the asserted signal TRST is transmitted to the test unit TAP of the semiconductor chip CHIP 2  via the semiconductor chip CHIP 1 . 
     In operation S 210 , the semiconductor chip CHIP 2  receives the signal TRST which resets the state of the test unit TAP, at the terminals TRST 20 , TRST 21 , and TRST 22 . Therefore, the majority determination selecting unit MAJ 1  of the semiconductor chip CHIP 2  receives the signal TRST which is transmitted via each of the three signal paths PT 13 , PT 14 , and PT 15 . The majority determination selecting unit MAJ 1  determines logic values of the data which is transmitted to the first switching unit SWA 3 , among the logic values of the signals TRST which are transmitted via each of the three signal paths PT 13 , PT 14 , and PT 15 , based on a majority determination logic. Therefore, the signal TRST which resets the state of the test unit TAP, for example, the asserted signal TRST is transmitted to the test unit TAP of the semiconductor chip CHIP 2 , and the state of the test unit TAP of the semiconductor chip CHIP 2  is reset. 
     In operation S 220 , the semiconductor chip CHIP 1  transmits the test clock TCK which is supplied to the test clock terminal TCK 1  to the semiconductor chip CHIP 2 . Therefore, the semiconductor chip CHIP 2  receives the test clock TCK in operation S 230 . 
     In operation S 230 , the semiconductor chip CHIP 2  receives the test clock TCK which is transmitted from the semiconductor chip CHIP 1 , at the terminal TCK 20 . Therefore, the test clock TCK is transmitted to the test unit TAP of the semiconductor chip CHIP 2 . 
     In operation S 240 , the semiconductor chip CHIP 1  receives the signal TRST which releases the reset, at the test reset terminal TRST 1 , and transmits the received signal TRST to the semiconductor chip CHIP 2  using the three signal paths PT 13 , PT 14 , and PT 15 . Therefore, the semiconductor chip CHIP 2  receives the signal TRST which releases the reset, in operation S 250 . For example, the test device negates the signal TRST which is supplied to the test reset terminal TRST 1 . The negated signal TRST is transmitted to the test unit TAP of the semiconductor chip CHIP 2  via the semiconductor chip CHIP 1 . 
     In operation S 250 , the semiconductor chip CHIP 2  receives the signal TRST which releases the reset, at the terminals TRST 20 , TRST 21 , and TRST 22 . Therefore, the majority determination selecting unit MAJ 1  of the semiconductor chip CHIP 2  receives the signal TRST which is transmitted via each of the three signal paths PT 13 , PT 14 , and PT 15 . The majority determination selecting unit MAJ 1  determines logic values of the data which is transmitted to the first switching unit SWA 3 , among the logic values of the signals TRST which are transmitted via each of the three signal paths PT 13 , PT 14 , and PT 15 , based on a majority determination logic. The signal TRST which released the reset, for example, the negated signal TRST is transmitted to the test unit TAP of the semiconductor chip CHIP 2 , and processing of resetting the state of the test unit TAP of the semiconductor chip CHIP 2  terminates. 
     In operation S 260 , the semiconductor chip CHIP 1  receives the test mode select signal TMS which is supplied from the test device, at the test mode select terminal TMS 1 . The semiconductor chip CHIP 1  transmits the test mode select signal TMS which is received from the test device to the semiconductor chip CHIP 2  using the three signal paths PT 16 , PT 17 , and PT 18 . Therefore, the semiconductor chip CHIP 2  receives the test mode select signal TMS in operations S 270 . 
     In operation S 270 , the semiconductor chip CHIP 2  receives the test mode select signal TMS, at the terminals TMS 20 , TMS 21 , and TMS 22 . Therefore, the majority determination selecting unit MAJ 2  of the semiconductor chip CHIP 2  receives the signal TMS which is transmitted via each of the three signal paths PT 16 , PT 17 , and PT 18 . The majority determination selecting unit MAJ 2  determines logic values of the data which is transmitted to the first switching unit SWA 4 , among the logic values of the signals TMS which are transmitted via each of the three signal paths PT 16 , PT 17 , and PT 18 , based on a majority determination logic. Therefore, the test mode select signal TMS is transmitted to the test unit TAP of the semiconductor chip CHIP 2 , and the state of the test unit TAP is determined. 
     For example, the test device sets the state of the test unit TAP of the semiconductor chip CHIP 2  to a state for setting the test paths PT between the semiconductor chips CHIP 1  and CHIP 2 , using the test mode select signal TMS. The operation states of the first switching units SWA and the second switching units SWB of the semiconductor chip CHIP 2  are maintained in an internal transmission state. 
     Therefore, the data TDI which is supplied to the test input terminal TDI 1  from the test device is transmitted to a test unit of the semiconductor chip CHIP 2 . The data TDI which is transmitted to the test unit TAP of the semiconductor chip CHIP 2  is transmitted to the test output terminal TDO 1  as the data TDO. 
     In operation S 280 , the semiconductor chip CHIP 1  receives the data TDI with a logic value equal to the expected value, at the test input terminal TDI 1 , and transmits the received data TDI to the semiconductor chip CHIP 2  using the two signal paths PT 10  and PT 11 . For example, the test device alternately transmits the data with a logic value of “0” and the data with a logic value of “1” to the test input terminal TDI 1 . Therefore, if one of the signal paths PT 10  and PT 11  is normal in operation S 290 , the semiconductor chip CHIP 2  receives the data TDI with a logic value equal to the expected value. 
     In operation S 290 , the semiconductor chip CHIP 2  receives the data TDI, at the terminals TDI 20  and TDI 21 . Therefore, the select signal generating unit SGEN 1  of the semiconductor chip CHIP 2  receives the data TDI which is transmitted via each of the two signal paths PT 10  and PT 11 . If the data TDI which is transmitted via each of the two signal paths PT 10  and PT 11  indicates the expected value, the select signal generating unit SGEN 1  generates the select signals SELCTL indicating the signal paths PT through which the data TDI indicating the expected value is transmitted. For example, the select signal generating unit SGEN 1  asserts the select signals SELCTL corresponding to the signal paths PT through which the data TDI indicating the expected value is transmitted, among the select signals SELCTL 1  and SELCTL 2 . 
     The path selecting unit SEL 1  of the semiconductor chip CHIP 2  selects the signal paths PT which are used at the time of testing the semiconductor device SEM 2 , among the signal paths PT 10  and PT 11 , based on the select signals SELCTL received from the select signal generating unit SGEN 1 . For example, the path selecting unit SEL 1  selects the signal paths PT corresponding to the asserted select signal SELCTL. Therefore, the test paths PT between the semiconductor chips CHIP 1  and CHIP 2  at the time of transmitting the data TDI are set. 
     Since the test paths PT at the time of transmitting the data TDI are set, the data TDI transmitted from the semiconductor chip CHIP 1 , and the data TDI indicating the expected value are transmitted to the test unit TAP of the semiconductor chip CHIP 2 . 
     In operation S 300 , the semiconductor chip CHIP 2  transmits the data TDI transmitted to the test unit TAP of the semiconductor chip CHIP 2 , for example, the data TDI indicating the expected value, to the semiconductor chip CHIP 1  using the two signal paths PT 19  and PT 20  as the data TDO. Therefore, if one of the signal paths PT 19  and PT 20  is normal, the semiconductor chip CHIP 1  receives the data TDO with a logic value equal to the expected value, in operation S 310 . 
     In operation S 310 , the semiconductor chip CHIP 1  receives the data TDO, at the terminals TDO 10  and TDO 11 . Therefore, the select signal generating unit SGEN 2  of the semiconductor chip CHIP 1  receives the data TDO transmitted via each of the two signal paths PT 19  and PT 20 . If the data TDO received via one of the two signal paths PT 19  and PT 20  indicates the expected value, the select signal generating unit SGEN 2  generates the select signals SELCTL indicating the signal paths PT through which the data TDO indicating the expected value is transmitted. For example, the select signal generating unit SGEN 2  asserts the select signals SELCTL corresponding to the signal paths PT through which the data TDO indicating the expected value is transmitted, among the select signals SELCTL 1  and SELCTL 2 . 
     The path selecting unit SEL 2  of the semiconductor chip CHIP 1  selects the signal paths PT which are used at the time of testing the semiconductor device SEM 2 , among the signal paths PT 19  and PT 20 , based on the select signals SELCTL received from the select signal generating unit SGEN 2 . For example, the path selecting unit SEL 2  selects the signal paths PT corresponding to the asserted select signal SELCTL. Therefore, the test paths PT between the semiconductor chips CHIP 1  and CHIP 2  at the time of transmitting the data TDO are set. Since the test paths PT at the time of transmitting the data TDO are set, the data TDO transmitted from the semiconductor chip CHIP 2  is transmitted to the test output terminal TDO 1 . 
     In operation S 400 , the semiconductor chip CHIP 1  outputs the data TDO received from the semiconductor chip CHIP 2  to the test device via the test output terminal TDO 1 . 
     The test paths PT between the semiconductor chips CHIP 1  and CHIP 2  are set. Setting of the test paths PT between the semiconductor chips CHIP 2  and CHIP 3  may be performed after, for example, operation S 400 . For example, the test device controls the switch control unit SWCTL by controlling the state of the TAP controller in the test unit TAP, and sets the first switching unit SWA 1  and the second switching unit SWB of the semiconductor chip CHIP 2  to a passing-through state. 
     The test device makes the semiconductor chip CHIP 1  perform substantially the same operations as or similar operations to the operations S 200 , S 220 , S 240 , S 260 , and S 280 , and makes the semiconductor chip CHIP 3  perform substantially the same operations as or similar operations to the operations S 210 , S 230 , S 250 , S 270 , and S 290 . The test device makes the semiconductor chip CHIP 3  perform substantially the same operation as or similar operations to operation S 300 , and makes the semiconductor chip CHIP 1  perform substantially the same operations as or similar operations to operations S 310  and S 400 . The test paths PT between the semiconductor chip CHIP 2  and CHIP 3  are set. 
     After the test paths PT between the plurality of semiconductor chips CHIP are set, the data TDI for testing the semiconductor device SEM 2  is supplied to the test input terminal TDI 1 . 
     For example, if a test using the test unit of the semiconductor chip CHIP 1  is performed, the test device does not transmit the data TDI or the like to the test unit of the semiconductor chips CHIP 2  and CHIP 3 , and thus a malfunction of the test units TAP of the semiconductor chips CHIP 2  and CHIP 3  may be reduced. A collision between the data TDO which is output from the test unit TAP of the semiconductor chip CHIP 1  and the data TDO which is transmitted from another semiconductor chip CHIP may be reduced. 
     If a test using the test unit TAP of the semiconductor chip CHIP 2  is performed, for example, the test device sets the first switching units SWA and the second switching units SWB of the semiconductor chip CHIP 1  to a passing-through state. The test device sets the first switching units SWA and the second switching units SWB of the semiconductor chip CHIP 2  to an internal transmission state. Since the data TDI or the like is not transmitted to the test units TAP of the semiconductor chips CHIP 1  and CHIP 3 , a malfunction of the test units TAP of the semiconductor chips CHIP 1  and CHIP 3  may be reduced. A collision between the data TDO which is output from the test unit TAP of the semiconductor chip CHIP 2  and the data TDO which is transmitted from another semiconductor chip CHIP may be reduced. 
     If a test using the test unit TAP of the semiconductor chip CHIP 3  is performed, for example, the test device sets the first switching units SWA and the second switching units SWB of the semiconductor chips CHIP 1  and CHIP 2  to a passing-through state. Since the data TDI or the like is not transmitted to the test units TAP of the semiconductor chips CHIP 1  and CHIP 2 , a malfunction of the test units TAP of the semiconductor chips CHIP 1  and CHIP 2  may be reduced. A collision between the data TDO which is output from the test unit TAP of the semiconductor chip CHIP 3  and the data TDO which is transmitted from another semiconductor chip CHIP may be reduced. 
     For example, after the test paths PT of the data TDI between the semiconductor chips CHIP 1  and CHIP 2  are set, and before the test path of the data TDO is set, the test paths PT of the data TDI between the semiconductor chips CHIP 2  and CHIP 3  may be set. After the test paths PT between the semiconductor chips CHIP 1  and CHIP 2  are set, and before the test path between the semiconductor chips CHIP 2  and CHIP 3  is set, the test using the test unit TAP of the semiconductor chip CHIP 2  may be performed. The signal TRST may be transmitted from the TAP controller or the like in the test units TAP of the semiconductor chips CHIP on a lower side to the semiconductor chips CHIP on an upper side. 
     In  FIG. 2  to  FIG. 7 , substantially the same effects as or similar effects to those in  FIG. 1  may be obtained. For example, if data TDI indicating the expected value is received via any one of the plurality of signal paths, the select signal generating unit SGEN generates the select signals SELCTL indicating the signal paths PT through which the data TDI indicating the expected value is transmitted. The path selecting unit SEL selects the signal path PT which is used at the time of testing the semiconductor device SEM 2  form among the signal paths PT, based on the select signals SELCTL received from the select signal generating unit SGEN. 
     Even if the signal paths PT which becomes redundant and through which the data supplied to the test input terminal TDI 1  is transmitted, for example, one of the signal paths PT which is configured by one set of two pieces fails, a test for detecting a failure portion of the signal path between the semiconductor chips CHIP is performed. Therefore, the failure may be avoided by bypassing the failure portion. Yield of the semiconductor device SEM 2  may increase. 
     The test circuit TESC includes the first switching units SWA which switch a transmission destination of the data TDI or the like, and the second switching unit SWB which switches a transmission source of the data TDO. Therefore, the test circuit TESC supplies the data TDI or the like to the test units TAP of the semiconductor chips CHIP which are targets to be tested, among the test units TAP of the plurality of semiconductor chips CHIP. For example, in the test circuit TESC, transmission of the data or the like to the test units TAP other than the semiconductor chips CHIP which are targets to be tested, among the test units TAP of the plurality of semiconductor chips CHIP, may be reduced. 
     The select signal generating unit SGEN includes the logical sum circuit OR 3  which suppresses the update of the logic value stored in the flip flop circuits FFC if the logic value of the asserted control signals CNT are stored in the flip flop circuits FFC. For example, during a time period after the select signals SELCTL indicating the signal paths PT through which the data TDI indicating the expected value is transmitted are generated, it is possible to reduce the change of the select signals SELCTL depending on a change of the data TDI transmitted to the signal path PT. The select signals SELCTL indicating the signal paths PT through which data indicating the expected value is transmitted are stably supplied to the path selecting unit SEL. 
       FIG. 8  illustrates another example of a test circuit. In  FIG. 8 , the same or similar symbols or reference numerals may be attached to substantially the same elements as or similar elements to the elements illustrated in  FIG. 1  to  FIG. 7 , and detailed description thereof may be omitted or reduced. A test circuit TESC 2  tests a semiconductor device SEM 3  which includes a plurality of semiconductor chips CHIP (CHIP 1 , CHIP 2 , CHIP 3 ). The semiconductor device SEM 3  may be substantially the same as or similar to the semiconductor device SEM 2  illustrated in  FIG. 2 , except that the semiconductor device SEM 3  includes the test circuit TESC 2  instead of the test circuit TESC illustrated in  FIG. 2 . A control method of the test circuit TESC 2  may be substantially the same as or similar to the control method of the test circuit TESC. 
     The test circuit TESC 2  includes a switch control unit SWCTL 2  and a first switching unit SWC, instead of the switch control unit SWCTL and the first switching units SWA which are illustrated in  FIG. 2 . The other configuration of the test circuit TESC 2  may be substantially the same as or similar to the test circuit TESC illustrated in  FIG. 2 . 
     For example, the test circuit TESC 2  includes the select signal generating units SGEN, the path selecting units SEL, the buffers BF, the first switching units SWC, the second switching units SWB, the switch control units SWCTL 2 , the majority determination selecting units MAJ, and the test units TAP corresponding to the JTAG. 
     For example, the switch control unit SWCTL 2  sets operation states of the first switching units SWC 1  to SWC 4  and the second switching unit SWB, according to a state of a TAP controller in the test unit TAP. In  FIG. 8 , for the sake of easy viewing, signal lines among the switch control unit SWCTL 2 , the first switching units SWC 2  to SWC 4 , the second switching unit SWB, the test units TAP and the like may be omitted. 
     For example, the switch control unit SWCTL 2 , according to the semiconductor chips CHIP which are targets to be tested, generates a control signal which controls an operation state of the first switching units SWC 1  to SWC 4 , and a control signal which controls an operation state of the second switching unit SWB. 
     The first switching units SWC (SWC 1  to SWC 4 ) are set to one of an internal transmission state, a passing-through state, and a both-direction state, based on the control signal which is received from the switch control unit SWCTL 2 . In the internal transmission state, the data received by the first switching unit SWC, for example, the data TDI of the first switching unit SWC 1  is transmitted to the test units TAP of the semiconductor chips CHIP thereof. In the passing-through state, the data received by the first switching unit SWC, for example, the data TDI of the first switching unit SWC 1  is transmitted to another semiconductor chip CHIP. In the both-direction state, the data received by the first switching unit SWC, for example, the data TDI of the first switching unit SWC 1  is transmitted to the test units TAP of the semiconductor chips CHIP thereof and another semiconductor chip CHIP 1 . 
     A coupling relationship between an input terminal and two output terminals of each of the first switching units SWC may be substantially the same as or similar to the first switching units SWA illustrated in  FIG. 2 . If the first switching units SWC of the semiconductor chip CHIP 1  are set to the internal transmission state, the test unit TAP of the semiconductor chip CHIP 1  receives the signals TDI, TCK, TMS, and TRST from the terminals TDI 1 , TCK 1 , TMS 1 , and TRST 1 , respectively. If the first switching units SWC of the semiconductor chip CHIP 1  are set to the passing-through state, the signals TDI, TCK, TMS, and TRST supplied to the terminals TDI 1 , TCK 1 , TMS 1 , and TRST 1  are transmitted to the semiconductor chip CHIP 2 . 
     If the first switching units SWC of the semiconductor chip CHIP 1  are set to the both-direction state, the test unit TAP of the semiconductor chip CHIP 1  receives the signals TDI, TCK, TMS, and TRST from the terminals TDI 1 , TCK 1 , TMS 1 , and TRST 1 , respectively. If the first switching units SWC of the semiconductor chip CHIP 1  are set to the both-direction state, the signals TDI, TCK, TMS, and TRST supplied to the terminals TDI 1 , TCK 1 , TMS 1 , and TRST 1  are transmitted to the semiconductor chip CHIP 2 . 
     For example, the switch control unit SWCTL 2  may be provided to the inside of the test unit TAP, for example, the inside of a TAP controller of the test unit TAP. The first switching unit SWC 4  or the like may be omitted. 
     For example, the test paths PT (PT 10 , PT 11 , or the like) through which the data supplied to the test input terminal TI 1  is transmitted may be redundant by three or more signal paths. For example, the test circuit TESC 2  may be embedded in the semiconductor device SEM 3  in which two semiconductor chips CHIP are stacked, for example, the semiconductor device SEM 3  in which the semiconductor chip CHIP 2  is omitted. The test circuit TESC 2  may be embedded in the semiconductor device SEM 3  in which four or more semiconductor chips CHIP are stacked. 
       FIG. 9  illustrates an example of a first switching unit. The first switching unit illustrated in  FIG. 9  may be the first switching unit SWC illustrated in  FIG. 8 . The first switching units SWC (SWC 1  to SWC 4 ) respectively include a logical product circuit AND 10  and AND 11 . The logical product circuit AND 10  calculates a logical product of data transmitted to two terminals IN 10  and SWSEL 10 , and outputs the calculation results to a terminal OUT 10 . The logical product circuit AND 11  calculates a logical product of data transmitted to two terminals IN 10  and SWSEL 11 , and outputs the calculation results to a terminal OUT 11 . 
     For example, the terminals SWSEL 10  and SWSEL 11  receive control signals from the switch control unit SWCTL 2 . If the control signals received at the terminals SWSEL 10  and SWSEL 11  are respectively a logic value “1” and a logic value “0”, for example, in the internal transmission state, a signal received at the terminal IN 10  is output from the terminal OUT 10 , and the terminal OUT 11  is maintained as a logic value “0”. If the control signals received in the terminals SWSEL 10  and SWSEL 11  are respectively a logic value “0” and a logic value “1”, for example, in the passing-through state, a signal received at the terminal IN 10  is output from the terminal OUT 11 , and the terminal OUT 10  is maintained as a logic value “0”. 
     If the control signals received at the terminals SWSEL 10  and SWSEL 11  are a logic value “1”, for example, in the both-direction state, a signal received in the terminal IN 10  is output from both the terminal OUT 10  and OUT 11 . For example, in the semiconductor chip CHIP 2 , the terminal IN 10  of the first switching unit SWC 1  is coupled to the output terminal of the path selecting unit SEL 1 . The terminal OUT 10  is coupled to a test input terminal (terminal which receives the data TDI) of the test unit TAP, and the terminal OUT 11  is coupled to buffers BF 1  and BF 2 . 
     Substantially the same effects as in  FIG. 2  to  FIG. 7  may be obtained also in  FIG. 8  and  FIG. 9 . For example, even if the signal paths PT which become redundant and through which the data supplied to the test input terminal TDI 1  is transmitted, for example, one of the signal paths PT which is configured by one set of two pieces fails, a test for detecting a failure portion of the signal path between the semiconductor chips CHIP is performed. Therefore, the failure may be avoided by bypassing the failure portion. Yield of the semiconductor device SEM 3  may increase. 
     The test circuit TESC 2  includes the first switching units SWC which switch a transmission destination of the data TDI or the like. For example, if the same data is set in a data register or the like in the test unit TAP of the plurality of semiconductor chips CHIP, the test circuit TESC 2  supplies the data TDI or the like to the test units TAP of the plurality of semiconductor chips CHIP through a broadcast. As a result, time for setting data to the data register or the like in the test unit TAP may be reduced, and test time of the semiconductor device SEM 3  may be reduced. 
       FIG. 10  illustrates another example of a test circuit. In  FIG. 10 , the same or similar symbols or reference numerals will be attached to substantially the same elements as or similar elements to the elements illustrated in  FIG. 1  to  FIG. 9 , and detailed description thereof may be omitted or reduced. A test circuit TESC 3  tests a semiconductor device SEM 4  which includes a plurality of semiconductor chips CHIP (CHIP 1 , CHIP 2 , CHIP 3 ). The semiconductor device SEM 4  may be substantially the same as or similar to the semiconductor device SEM 2  illustrated in  FIG. 2 , except that the semiconductor device SEM 4  includes the test circuit TESC 3  instead of the test circuit TESC illustrated in  FIG. 2 . A control method of the test circuit TESC 3  may be substantially the same as or similar to the control method of the test circuit TESC. 
     The test circuit TESC 3  includes select signal generating units SGENa (SGENa 1 , SGENa 2 ), instead of the select signal generating unit SGEN (SGEN 1 , SGEN 2 ) illustrated in  FIG. 2 . The other configuration of the test circuit TESC 3  may be substantially the same as or similar to the test circuit TESC illustrated in  FIG. 2 . 
     For example, the test circuit TESC 3  includes the select signal generating units SGENa, the path selecting units SEL, the buffers BF, the first switching units SWA, the second switching units SWB, the switch control units SWCTL, the majority determination selecting units MAJ, and the test units TAP corresponding to the JTAG. 
     If a plurality of signal paths PT through which the data TDI indicating the expected value is transmitted exist, the select signal generating units SGENa generate the select signals SELCTL indicating one of the plurality of signal paths PT through which the data TDI indicating the expected value is transmitted. 
     For example, the switch control unit SWCTL may be provided inside the test unit TAP, for example, inside a TAP controller in the test unit TAP. The first switching unit SWA 4  or the like may be omitted. 
     For example, the test circuit TESC 3  may include the switch control unit SWCTL 2  and the first switching units SWC which are illustrated in  FIG. 8 , instead of the switch control unit SWCTL and the first switching units SWA. 
     The test paths PT (PT 10 , PT 11 , or the like) through which the data supplied to the test input terminal TI 1  is transmitted may be redundant by three or more signal paths. For example, the test circuit TESC 3  may be embedded in the semiconductor device SEM 4  in which two semiconductor chips CHIP are stacked, for example, the semiconductor device SEM 4  in which the semiconductor chip CHIP 2  is omitted. The test circuit TESC 3  may be embedded in the semiconductor device SEM 4  in which four or more semiconductor chips CHIP are stacked. 
       FIG. 11  illustrates an example of a select signal generating unit. The select signal generating unit illustrated in  FIG. 11  may be the select signal generating unit SGENa illustrated in  FIG. 10 . A coupling destination or the like of terminals CLK, IN 1 , and IN 2  illustrated in  FIG. 11  may be substantially the same as or similar to the select signal generating unit SGEN illustrated in  FIG. 3 . In the select signal generating units SGENa, a negative logical product circuit NAND 1  and a logical product circuit AND 5  are added to the select signal generating unit SGEN illustrated in  FIG. 3 . The other configuration of the select signal generating units SGENa may be substantially the same as or similar to the select signal generating unit SGEN illustrated in  FIG. 3 . 
     The select signal generating units SGENa respectively include shift registers with n bits SFTR 1  and SFTR 2 , the logical product circuits AND 1 , AND 2 , and AND 5 , the negative logical product circuit NAND 1 , the logical sum circuits OR 1 , OR 2 , and OR 3 , and the flip flop circuits FFC 1  and FFC 2 . Here, n is an integer equal to or higher than 2. In the select signal generating units SGENa, the select signal SELCTL 2   a  is transmitted to the path selecting unit SEL, instead of the select signal SELCTL 2 . 
     The negative logical product circuit NAND 1  receives the select signals SELCTL 1  and SELCTL 2  from the flip flop circuits FFC 1  and FFC 2  at two input terminals thereof, respectively. The negative logical product circuit NAND 1  calculates a negative logical product of the select signals SELCTL 1  and SELCTL 2  received in the two input terminals thereof, and outputs the calculation results to the logical product circuit AND 5 . 
     The logical product circuit AND 5  respectively receives an output signal of the negative logical product circuit NAND 1  and the select signal SELCTL 2 , at the two input terminals thereof, respectively. The logical product circuit AND 5  calculates a logical product of the data received in the two input terminals, and transmits the calculation results to the path selecting unit SEL as the select signal SELCTL 2   a.    
     For example, if both the select signals SELCTL 1  and SELCTL 2  have a logic value of “0”, the select signals SELCTL 1  and SELCTL 2   a  with a logic value of “0” are transmitted to the path selecting unit SEL. For example, if the select signals SELCTL 1  and SELCTL 2  are respectively a logic value of “0” and a logic value of “1”, the select signal SELCTL 1  with a logic value of “0” and the select signal SELCTL 2   a  with a logic value of “1” are transmitted to the path selecting unit SEL. In addition, for example, if the select signals SELCTL 1  and SELCTL 2  are respectively a logic value of “1” and a logic value of “0”, the select signal SELCTL 1  with a logic value of “1” and the select signal SELCTL 2   a  with a logic value of “0” are transmitted to the path selecting unit SEL. 
     If both the select signals SELCTL 1  and SELCTL 2  have a logic value of “1”, the select signal SELCTL 1  with a logic value of “1” and the select signal SELCTL 2   a  with a logic value of “0” are transmitted to the path selecting unit SEL. 
     Even if a plurality of signal paths PT through which the data TDI indicating the expected value is transmitted exist, the select signal generating units SGENa respectively transmit the select signals SELCTL indicating one of the plurality of signal paths PT through which the data TDI indicating the expected value is transmitted, to the path selecting unit SEL. For example, in the path selecting unit SEL illustrated in  FIG. 3 , if both the select signals SELCTL 1  and SELCTL 2  have a logic value of “1”, waveforms of the data which is output from the path selecting unit SEL may be degraded due to a difference or the like of delay time of the data which is transmitted to the terminals IN 1  and IN 2 . 
     In the select signal generating units SGENa, both the select signals SELCTL 1  and SELCTL 2   a  may not become a logic value of “1”. Therefore, degradation of the waveform of the data which is output from the path selecting unit SEL may be reduced. 
     Substantially the same effects as in  FIG. 2  to  FIG. 7  may be obtained also in  FIG. 10  and  FIG. 11 . For example, even if the signal paths PT which become redundant and through which the data supplied to the test input terminal TDI 1  is transmitted, for example, one of the signal paths PT which is configured by one set of two pieces fails, a test for detecting a failure portion of the signal path between the semiconductor chips CHIP is performed. Therefore, the failure may be avoided by bypassing the failure portion. Yield of the semiconductor device SEM 4  may increase. 
     If a plurality of signal paths PT through which the data TDI indicating the expected value is transmitted exist, the select signal generating units SGENa respectively generate the select signals SELCTL indicating one of the plurality of signal paths PT through which the data TDI indicating the expected value is transmitted. For example, both the select signals SELCTL 1  and SELCTL 2   a  which are transmitted to the path selecting unit SEL may not become a logic value of “1”. Therefore, degradation of the waveforms of the data which is output from the path selecting unit SEL may be reduced. 
     All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.