Patent Publication Number: US-2023143132-A1

Title: Volatile memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C. 119 from Korean Patent Application No. 10-2021-0153223 filed on Nov. 9, 2021 and Korean Patent Application No. 10-2022-0007654 filed on Jan. 19, 2022, the collective subject matter of which is hereby incorporated by reference in its entirety. 
     BACKGROUND 
     Technical Field 
     The present disclosure relates to volatile memory devices, and more particularly, to volatile memory devices having an open bit line structure. 
     Description of the Related Art 
     Semiconductor memory devices may be generally categorized as volatile memory devices and non-volatile memory devices. Volatile memory devices (e.g., dynamic random access memory (RAM) (DRAM)) store data by charging/discharging of a constituent cell capacitor. Volatile memory devices provide relatively fast data access speeds, and are commonly used as components in computer memory systems. However, volatile memory devices lose stored data in the absence of applied power. In contrast, non-volatile memory devices are able to retain stored data in the absence of applied power. Non-volatile memory devices also provide very large data storage capacity. Accordingly, non-volatile memory devices are primarily used to implement large-capacity (or bulk) memory systems able to store program data, application data, and/or user data. 
     Volatile memory devices may be further categorized as having either an open bit line structure or a folded bit line structure. A sense amplifier of the volatile memory device having the corresponding structure may have corresponding bit line pairs. However, volatile memory devices having an open bit line structure may include an unnecessary mat due to particular characteristics of the open bit line structure. 
     SUMMARY 
     Aspects of the present disclosure provide volatile memory devices having a reduced area. 
     Aspects of the present disclosure also provide volatile memory devices capable of being more densely integrated. 
     Aspects of the present disclosure are not limited to those mentioned above, and additional objects of the present disclosure will be appreciated by those skilled in the art upon consideration of the following detailed description and accompanying drawings. 
     According to an aspect of the present disclosure, a volatile memory device may include; a row decoder extending in a first direction, a column decoder extending in a second direction, a cell region between the row decoder and the column decoder and including a first sense amplifier and a first bit line connected to the first sense amplifier, and a first peripheral circuit region spaced apart from the cell region in the first direction and including includes a first complementary bit line connected to the first sense amplifier, wherein the first sense amplifier is configured to perform a read/write operation in relation to a first memory cell connected to the first bit line using the first complementary bit line. 
     According to an aspect of the present disclosure, a volatile memory device may include; a row decoder extending in a first direction, a column decoder extending in a second direction, and a memory cell array between the row decoder and the column decoder. The memory cell array may include; a substrate, a first sense amplifier on the substrate, a first bit line connected to the first sense amplifier, and a first complementary bit line connected to the first sense amplifier, wherein a first height from the substrate to the first sense amplifier is greater than a third height from the substrate to the first complementary bit line, and a second height from the substrate to the first bit line is greater than the third height. 
     According to an aspect of the present disclosure, a volatile memory device may include; a row decoder extending in a first direction, a column decoder extending in a second direction, a memory cell array between the row decoder and the column decoder, and a dummy mat disposed separated from the memory cell array in the first direction. The memory cell array may include; a center region including a first sense amplifier, a first mat including a first bit line connected to the first sense amplifier, and a second mat including a first complementary bit line connected to the first sense amplifier, and a first edge region separated from the center region in the first direction and including a second sense amplifier and a second bit line connected to the second sense amplifier, wherein the dummy mat includes a second complementary bit line separated from the first edge region in the first direction and connected to the second sense amplifier without being disposed in the memory cell array. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Advantages, benefits, and features, as well as the making and use of embodiments consistent with the present disclosure will become more apparent upon consideration of the following detail description together with the accompanying drawings, in which: 
         FIG.  1    is a block diagram illustrating a memory system according to some embodiments; 
         FIG.  2    is a block diagram further illustrating a memory device of  FIG.  1   ; 
         FIG.  3    is a plan view illustrating a memory device according to some embodiments; 
         FIG.  4    is an enlarged view further illustrating a second memory bank of  FIG.  3   ; 
         FIG.  5    is an enlarged view further illustrating the first region REG1 of  FIG.  4   ; 
         FIG.  6    is a circuit diagram illustrating a sense amplifier and a plurality of memory cells of  FIG.  4   ; 
         FIG.  7    is a cross-sectional view further illustrating the first region REG1 of  FIG.  5   ; 
         FIGS.  8  and  9    are diagrams illustrating a bit line and a complementary bit line according to some embodiments; 
         FIG.  10    is a cross-sectional view further illustrating the first region REG1 according to some embodiments; 
         FIG.  11    is a cross-sectional view further illustrating the first region REG1 according to some embodiments; 
         FIG.  12    is an enlarged view further illustrating the second region REG2 of  FIG.  4   ; 
         FIGS.  13  and  14    are plan views further illustrating the first region REG1 according to some embodiments; 
         FIG.  15    is a cross-sectional view further illustrating the first region REG1 of  FIGS.  13  and  14   ; 
         FIG.  16    is a block diagram illustrating a memory system according to some embodiments; 
         FIG.  17    is a cross-sectional diagram illustrating a semiconductor package according to some embodiments; 
         FIG.  18    is a perspective diagram illustrating one implementation example for a semiconductor package according to some embodiments; and 
         FIG.  19    is a cross-sectional diagram illustrating a semiconductor package according to some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, the certain embodiments according to the present disclosure will be described with reference to the accompanying drawings. 
     Figure  (FIG. )  1    is a block diagram illustrating a memory system according to some embodiments. 
     Referring to  FIG.  1   , the memory system may generally include a host device  20  and a memory storage device  1 , wherein the memory storage device  1  may include a memory device  100  and a memory controller  10 . 
     The memory controller  10  may control the overall operation of the memory device  100 . In this regard, the memory controller  10  may control data communication (e.g., transmission and/or receipt of data) between the external host device  20  and the memory device  100 . That is, the memory controller  10  may control the memory device  100  in performing various operations (e.g., a write (or program) operation, a read operation, an erases operation, etc.) responsive to one or more request(s) received from the host device  20  (e.g., a write (or program) request, a read request, or an erase request). 
     Within the memory storage device  1 , the memory controller  10  and the memory device  100  may communication through a memory interface MEM I/F. In similar vein, the memory controller  10  may communicate with the external host device  20  through a host interface (not shown). Accordingly, the memory controller  10  may communicate a variety of external signals between the memory device  100  and the host device  20 , and may further communicate a variety of internal signals (e.g., command/control signals CMD, address signals ADDR, clock signals CLK, and data signals DQ) to control operation of the memory device  100 . 
     In some embodiments, the memory device  100  may include a DRAM, a Double Data Rate 4 DRAM (DDR4), a Synchronous DRAM (SDRAM), a Low Power DDR4 (LPDDR4) SRAM, a LPDDR5 SDRAM, etc. Alternately or additionally, the memory device  100  may include a non-volatile memory device. Hereafter, certain embodiments will be described under an assumption that the memory device  100  includes a volatile memory device. 
     Thus, the memory controller  10  may communicate a clock signal CLK, a command CMD, an address ADDR signal, etc. to the memory device  100 . Further, the memory controller  10  may provide data DQ to the memory device  100  and/or receive data DQ from the memory device  100 . 
     In some embodiments, the memory device  100  may include a memory cell array  200  for storing the data DQ, a control logic circuit  110  and a data input/output (I/O) buffer  195 . 
       FIG.  2    is a block diagram further illustrating in one example the memory device  100  of  FIG.  1   . 
     Referring to  FIG.  2   , the memory device  100  may include a control logic circuit  110 , an address register  120 , a bank control logic circuit  130 , a row address multiplexer  140 , a refresh counter  145 , a column address latch  150 , a row decoder  160 , a column decoder  170 , a memory cell array  200 , a sense amplifier  300 , an I/O gating circuit  190 , an ECC engine  191 , and a data I/O buffer  195 . 
     The memory cell array  200  may be generally disposed between the row decoder  160  and the column decoder, and may include a plurality of bank memory arrays. The row decoder  160  may be connected to the plurality of bank memory arrays. The column decoder  170  may be connected to the plurality of bank memory arrays. The sense amplifier  300  may be connected to the plurality of bank memory arrays, respectively. The memory cell array  200  may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells formed at intersection points of the word lines and the bit lines. 
     The address register  120  may be supplied with an address ADDR from the memory controller  10 . The address ADDR may include a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR. The address register  120  may provide the bank address BANK_ADDR to the bank control logic circuit  130 . The address register  120  may provide the row address ROW_ADDR to the row address multiplexer  140 . The address register  120  may provide the column address COL_ADDR to the column address latch  150 . 
     The bank control logic circuit  130  may generate a bank control signal in response to the bank address BANK_ADDR. The bank row decoder  160  may be activated in response to the bank control signal. The column decoder  170  may be activated in response to the bank control signal corresponding to the bank address BANK_ADDR. 
     The row address multiplexer  140  may receive the row address ROW_ADDR from the address register  120 , and may receive a refresh row address REF_ADDR from the refresh counter  145 . The row address multiplexer  140  may select one of the row address ROW_ADDR or the refresh row address REF_ADDR and output the selected one to a row address RA. The row address RA may be transferred to the row decoder  160 . 
     The refresh counter  145  may sequentially output the refresh row addresses REF_ADDR under the control of the control logic circuit  110 . 
     The row decoder  160  activated by the bank control logic circuit  130  may decode the row address RA output from the row address multiplexer  140  to activate the word line corresponding to the row address RA. For example, the row decoder  160  may apply a word line driving voltage to the word line corresponding to the row address RA. 
     The column address latch  150  may receive the column address COL_ADDR from the address register  120 , and may temporarily store the received column address COL_ADDR. The column address latch  150  may gradually increase the column address COL_ADDR received in a burst mode. The column address latch  150  may provide the temporarily stored column address COL_ADDR or the gradually increased column address COL_ADDR to the column decoder  170 . 
     The column decoder  170  activated by the bank control logic circuit  130  may activate the sense amplifier  300  corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the corresponding I/O gating circuit  190 . 
     The I/O gating circuit  190  may include a circuit for gating I/O data, an input data mask logic, read data latches for storing data output from the memory cell array  200 , and write drivers for writing data in the memory cell array  200 . 
     A codeword CW read from the bank memory array of the memory cell array  200  may be sensed by the sense amplifier  300  corresponding to the bank memory array. The codeword CW may also be stored in the read data latch. The codeword CW stored in the read data latch may be ECC-decoded by the ECC engine  191 , and the data DQ for which ECC decoding is performed may be provided to the memory controller  10  through the data I/O buffer  195 . 
     The data I/O buffer  195  may provide the data DQ to the ECC engine  191  based on the clock signal CLK in the write operation. The data I/O buffer  195  may provide the data DQ provided from the ECC engine  191  to the memory controller  10  based on the clock signal CLK in the read operation. 
     The memory cell array  200  may be connected to the sense amplifier  300 , and the row decoder  160  and the column decoder  170  may be connected to the memory cell array  200  and the sense amplifier  300 . Here, the plurality of bit lines included in the memory cell array  200  may be connected to the sense amplifier  300  in an open bit line structure. This will be described in more detail. 
       FIG.  3    is a plan (or top-down) view illustrating a memory device according to some embodiments. 
     Referring to  FIG.  3   , the memory device  100  may include a plurality of bank memory arrays BMA 1  to BMA 16 , a row decoder  160 , a column decoder  170 , a first peripheral circuit region PERI 1 , and a second peripheral circuit region PERI 2 . 
     In some embodiments, the memory device  100  may be disposed in a horizontal plane defined by a first horizontal direction (first direction X) and a second horizontal direction (second direction Y) intersecting the first direction X. In some embodiments, the memory device  100  may have a substantially rectangular shape. 
     As one example, the memory device  100  may include sixteen ( 16 ) bank memory arrays BMA 1  to BMA 16 . The  16  bank memory arrays BMA 1  to BMA 16  may process data of 1Gb, but the embodiments of the present disclosure are not limited thereto. The memory device  100  may include a different number of bank memory arrays BMA 1  to BMA 16  in addition to the  16  bank memory arrays. The bank memory arrays BMA 1  to BMA 16  may be arranged regularly. For example, the first, third, fifth, seventh, ninth, eleventh, thirteenth and fifteenth bank memory arrays BMA 1 , BMA 3 , BMA 5 , BMA 7 , BMA 9 , BMA 11 , BMA 13  and BMA 15  may be sequentially arranged along an opposite direction of the second direction Y, and the second, fourth, sixth, eighth, tenth, twelfth, fourteenth and sixteenth bank memory arrays BMA 2 , BMA 4 , BMA 6 , BMA 8 , BMA 10 , BMA 12 , BMA 14  and BMA16 may be sequentially arranged along the opposite direction of the second direction Y. In addition, the second, fourth, sixth, eighth, tenth, twelfth, fourteenth and sixteenth bank memory arrays BMA 2 , BMA 4 , BMA 6 , BMA 8 , BMA 10 , BMA 12 , BMA 14  and BMA 16  may be spaced apart from the first, third, fifth, seventh, ninth, eleventh, thirteenth and fifteenth bank memory arrays BMA 1 , BMA 3 , BMA 5 , BMA 7 , BMA 9 , BMA 11 , BMA 13  and BMA 15  in the first direction X. 
     The row decoder  160  may extend in the first direction X, and may be disposed among the plurality of bank memory arrays BMA 1  to BMA 16 . For example, the row decoder  160  may be disposed between the first bank memory array BMA 1  and the third bank memory array BMA 3 . The column decoder  170  may extend in the second direction Y, and may be disposed on one side of the plurality of bank memory arrays BMA 1  to BMA 16 . For example, the column decoder  170  may be disposed in the first direction X from the first bank memory array BMA 1 . Also, the row decoder  160  may cross the column decoder  170 . In addition, the plurality of bank memory arrays BMA 1  to BMA 16  may be surrounded by the row decoder  160  and the column decoder  170 . The plurality of bank memory arrays BMA 1  to BMA 16  may be defined by the row decoder  160  and the column decoder  170 . 
     The first and second peripheral circuit regions PERI 1  and PERI 2  may be disposed in a portion of the memory device  100  except for the plurality of bank memory arrays BMA1 to BMA16, the row decoder  160  and the column decoder  170 . The first and second peripheral circuit regions PERI 1  and PERI 2  may include the control logic circuit  110 , the address register  120 , the bank control logic circuit  130 , the row address multiplexer  140 , the refresh counter  145 , the column address latch  150 , the I/O gating circuit  190 , the ECC engine  191  and the data I/O buffer  195  of  FIG.  2   . 
     The first peripheral circuit region PERI 1  may be disposed among the plurality of bank memory arrays BMA 1  to BMA 16 . The second peripheral circuit region PERI 2  may be disposed outside the plurality of bank memory arrays BMA 1  to BMA 16 . For example, the second peripheral circuit region PERI 2  may be disposed in a direction opposite to the first direction X from the first, third, fifth, seventh, ninth, eleventh, thirteenth and fifteenth bank memory arrays BMA 1 , BMA 3 , BMA 5 , BMA 7 , BMA 9 , BMA 11 , BMA 13  and BMA 15 , and may be disposed in the first direction X from the second, fourth, sixth, eighth, tenth, twelfth, fourteenth and sixteenth bank memory arrays BMA 2 , BMA 4 , BMA 6 , BMA 8 , BMA 10 , BMA 12 , BMA 14  and BMA 16 . 
     One of the bank memory arrays BMA 1  to BMA 16  may include a portion of the memory cell array  200  and the sense amplifier  300 , but the embodiments of the present disclosure are not limited thereto. One of the bank memory arrays BMA 1  to BMA 16  may include a first edge region EDG 1  and a second edge region EDG 2 . For example, the second bank memory array BNK 2  may include a first edge region EDG 1  in a direction opposite to the first direction X and a second edge region EDG 2  in the first direction X. 
     The memory bank may be defined by one of the bank memory arrays BMA 1  to BMA 16 , one row decoder  160  and one column decoder  170 . For example, the second memory bank BNK 2  may be defined by the second bank memory array BNK 2 , the row decoder  160 , and the column decoder  170 . In this case, the memory bank may correspond to a storage unit indicating one bank address. 
       FIG.  4    is an enlarged view further illustrating, in part, the second memory bank BNK 2  of  FIG.  3   . 
     Referring to  FIG.  4   , the second memory bank BNK 2  may include a row decoder  160 , a column decoder  170 , and a second bank memory array BMA 2  substantially surrounded by the row decoder  160  and the column decoder  170 . The second bank memory array BMA 2  may be referred to as a second cell region CELL 2 . The second bank memory array BMA 2  may include a plurality of sense amplifiers, a plurality of mats, and a plurality of decoders. The plurality of sense amplifiers, the plurality of mats, and the plurality of decoders may be disposed in a region defined by the row decoder  160  and the column decoder  170 . 
     The plurality of mats may include first to (n)th sub-memory arrays SMA 11  to SMA 1   n , first to (n)th sub-memory arrays SMA 21  to SMA 2   n , and first to (n)th sub-memory arrays SMA m   1  to SMAmn. The first to (n)th sub-memory arrays SMA 11  to SMA 1   n , the first to (n)th sub-memory arrays SMA 21  to SMA 2   n , and the first to (n)th sub-memory arrays SMA m   1  to SMAmn may be arranged along the first direction X. For example, the first to (n)th sub-memory arrays SMA 21  to SMA 2   n  may be disposed in the first direction X from the first to (n)th sub-memory arrays SMA 11  to SMA 1   n , and the first to (n)th sub-memory arrays SMA m   1  to SMAmn may be disposed in the first direction X from the first to (n)th sub-memory arrays SMA 21  to SMA 2   n . 
     The first to (n)th sub-memory arrays SMA 11  to SMA 1   n  may be arranged along the second direction Y. For example, the second sub-memory array SMA 12  may be disposed in the second direction Y from the first sub-memory array SMA 11 , and the (n)th sub-memory array SMA 1   n  may be disposed in the second direction Y from the (n-1)th sub-memory array SMA 1 ( n - 1 ). In this case, the first to (n)th sub-memory arrays SMA 11  to SMA 1   n  may be disposed in the first edge region EDG 1 . 
     The first to (n)th sub-memory arrays SMA 21  to SMA 2   n  may be arranged along the second direction Y. For example, the second sub-memory array SMA 22  may be disposed in the second direction Y from the first sub-memory array SMA 21 , and the (n)th sub-memory array SMA 2   n  may be disposed in the second direction Y from the (n-1)th sub-memory array SMA 2 ( n - 1 ). In this case, the first to (n)th sub-memory arrays SMA 21  to SMA 2   n  may be disposed in a center region CNT. The center region CNT may correspond to a region between the first edge region EDG 1  and the second edge region EDG 2 . For example, the center region CNT may correspond to a portion except for the first edge region EDG 1  and the second edge region EDG 2  in the second bank memory array BMA 2 . 
     The first to (n)th sub-memory arrays SMA m   1  to SMAmn may be arranged along the second direction Y. For example, the second sub-memory array SMA m   2  may be disposed in the second direction Y from the first sub-memory array SMA m   1 , and the (n)th sub-memory array SMAmn may be disposed in the second direction Y from the (n-1)th sub-memory array SMAm(n-1). In this case, the first to (n)th sub-memory arrays SMA m   1  to SMAmn may be disposed in the second edge region EDG 2 . 
     The plurality of sense amplifiers may include first to (n)th sub-sense amplifiers SA 11  to SA 1   n , first to (n)th sub-sense amplifiers SA 21  to SA 2   n , first to (n)th sub-sense amplifiers SA m   1  to SAmn, and first to (n)th sub-sense amplifiers SA(m+1)1 to SA(m+1)n. The plurality of sense amplifiers may be disposed among the plurality of mats. 
     The sense amplifier may read or write (hereafter, “read/write”) data by using a bit line and a complementary bit line, which are included in the mat. The sense amplifier and the decoder may be driven by the row decoder  160  and the column decoder  170 . 
     The first to (n)th sub-sense amplifiers SA 11  to SA 1   n  may be disposed between the column decoder  170  and the first to (n)th sub-memory arrays SMA 11  to SMA 1   n . In this case, each of the first to (n)th sub-sense amplifiers SA 11  to SA 1   n  may be connected to each of the first to (n)th sub-memory arrays SMA 11  to SMA 1   n . The first to (n)th sub-sense amplifiers SA 11  to SA 1   n  may be disposed in the first edge region EDG 1 . 
     The first to (n)th sub-sense amplifiers SA 21  to SA 2   n  may be disposed between the first to (n)th sub-memory arrays SMA 11  to SMA 1   n  and the first to (n)th sub-memory arrays SMA 21  to SMA 2   n . The first to (n)th sub-sense amplifiers SA 21  to SA 2   n  may be connected to the first to (n)th sub-memory arrays SMA 11  to SMA 1   n  and the first to (n)th sub-memory arrays SMA 21  to SMA 2   n . The first to (n)th sub-sense amplifiers SA m   1  to SAmn may be disposed in a direction opposite to the first direction X from the first to (n)th sub-memory arrays SMA m   1  to SMAmn. The first to (n)th sub-sense amplifiers SA m   1  to SAmn may be connected to the first to (n)th sub-memory arrays SMA m   1  to SMAmn. The first to (n)th sub-sense amplifiers SA 21  to SA 2   n  and the first to (n)th sub-sense amplifiers SAm1 to SAmn may be disposed in the center region CNT. 
     The first to (n)th sub-sense amplifiers SA(m+1)1 to SA(m+1)n may be disposed between the second peripheral circuit region PERI 2  and the first to (n)th sub-memory arrays SMA m   1  to SMAmn. In this case, each of the first to (n)th sub-sense amplifiers SA(m+1)1 to SA(m+1)n may be connected to each of the first to (n)th sub-memory arrays SMA m   1  to SMAmn. The first to (n)th sub-sense amplifiers SA(m+1)1 to SA(m+1)n may be disposed in the second edge region EDG 2 . 
     The plurality of decoders may include first to (n)th decoders SWD11 to SWD1n, first to (n)th decoders SWD 21  to SWD 2   n , and first to (n)th decoders SWD m   1  to SWDmn. The first to (n)th decoders SWD 11  to SWD 1   n  may be connected to the first to (n)th sub-memory arrays SMA 11  to SMA 1   n , the first to (n)th decoders SWD 21  to SWD 2   n  may be connected to the first to (n)th sub-memory arrays SMA 21  to SMA 2   n , and the first to (n)th decoders SWD m   1  to SWDmn may be connected to the first to (n)th sub-memory arrays SMA m   1  to SMAmn. The plurality of decoders may drive each sub-memory array. 
     The first peripheral circuit region PERI 1  may include a first dummy mat DM 1 . The first dummy mat DM 1  may be disposed in a direction opposite to the first direction X from the second bank memory array BMA 2 , and may be disposed in a direction opposite to the first direction X from the column decoder  170 . In some embodiments, the first dummy mat DM 1  may be disposed to overlap the column decoder  170 , but the embodiments are not limited thereto. 
     The first dummy mat DM 1  may include first to (n)th dummy memory arrays DMA 11  to DMA 1   n . The first to (n)th dummy memory arrays DMA 11  to DMA 1   n  may be arranged in the second direction Y. The first to (n)th dummy memory arrays DMA 11  to DMA 1   n  may be connected to the first to (n)th sub-sense amplifiers SA 11  to SA 1   n , respectively. In this case, the first to (n)th dummy memory arrays DMA 11  to DMA 1   n  may be disposed in the first peripheral circuit region PERI 1 , and the first to (n)th sub-sense amplifiers SA 11  to SA1n may be disposed in the second cell region CELL 2 . 
     The second peripheral circuit region PERI 2  may include a second dummy mat DM 2 . The second dummy mat DM 2  may be arranged in the first direction X from the second bank memory array BMA2. 
     The second dummy mat DM 2  may include first to nth dummy memory arrays DMA 21  to DMA 2 N. The first to (n)th dummy memory arrays DMA 21  to DMA 2   n  may be arranged in the second direction Y. The first to (n)th dummy memory arrays DMA 21  to DMA 2   n  may be connected to the first to (n)th sub-sense amplifiers SA(m+1)1 to SA(m+1)n, respectively. In this case, the first to (n)th dummy memory arrays DMA 21  to DMA 2   n  may be disposed in the second peripheral circuit region PERI 2 , and the first to (n)th sub-sense amplifiers SA(m+1)1 to SA(m+1)n may be disposed in the second cell region CELL 2 . 
       FIG.  5    is an enlarged view further illustrating a first region REG 1  indicated in  FIG.  4   , and  FIG.  6    is a circuit diagram further illustrating in one example a sense amplifier SA 11  connected to memory cells MC 1  and MC 1 ′. 
     Referring to  FIG.  5   , the second memory bank BNK 2  corresponding to a first region REG 1  may include a first sub-memory array SMA 11 , a second sub-memory array SMA 12 , a first sub-memory array SMA 21 , a second sub-memory array SMA 22 , a first sub-sense amplifier SA 11 , a second sub-sense amplifier SA 12 , a first sub-sense amplifier SA 21 , a second sub-sense amplifier SA 22 , a first sub-sense amplifier SA 31 , and a second sub-sense amplifier SA 32 . In addition, the first peripheral circuit region PERI 1  may include a first dummy memory array DMA 11  and a second dummy memory array DMA 12 . 
     The first sub-memory array SMA 11  may include a first bit line BL 11  and a first bit line BL 21 . The first bit line BL 11  and the first bit line BL 21  may extend in the first direction X. The first bit line BL 11  may be connected to the first sub-sense amplifier SA 11 , and the first bit line BL 21  may be connected to the first sub-sense amplifier SA 21 . The first word line WL 1  may extend in the second direction Y, and may be connected to both of the first bit line BL 11  and the first bit line BL 21  of the first sub-memory array SMA 11 . In addition, the first word line WL 1  may be connected to the first decoder SWD 11 . 
     The second sub-memory array SMA 12  may include a second bit line BL 12  and a second bit line BL 22 . The second bit line BL 12  and the second bit line BL 22  may extend in the first direction X. The second bit line BL 12  may be connected to the second sub-sense amplifier SA 12 , and the second bit line BL 22  may be connected to the second sub-sense amplifier SA 22 . The first word line WL 1  may be connected to the second bit line BL 12  and the second bit line BL 22 . 
     The first sub-memory array SMA 21  may include a first complementary bit line BLB 21  and a first complementary bit line BLB 31 . The first complementary bit line BLB 21  and the first complementary bit line BLB 31  may extend in the first direction X. The first complementary bit line BLB 21  may be connected to the first sub-sense amplifier SA 21 , and the first complementary bit line BLB 31  may be connected to the first sub-sense amplifier SA 31 . The second word line WL 2  may extend in the second direction Y, and may be connected to both the first complementary bit line BLB 21  and the first complementary bit line BLB 31  of the first sub-memory array SMA 21 . Further, the second word line WL 2  may be connected to the first decoder SWD21. 
     The second sub-memory array SMA 22  may include a second complementary bit line BLB 22  and a second complementary bit line BLB 32 . The second complementary bit line BLB 22  and the second complementary bit line BLB 32  may extend in the first direction X. The second complementary bit line BLB 22  may be connected to the second sub-sense amplifier SA 22 , and the second complementary bit line BLB 32  may be connected to the second sub-sense amplifier SA 32 . The second word line WL 2  may be connected to the second complementary bit line BLB 22  and the second complementary bit line BLB 32 . 
     The first dummy memory array DMA 11  may include a first complementary bit line BLB 11 . The first complementary bit line BLB 11  may extend in the first direction X. The first complementary bit line BLB 11  may be connected to the first sub-sense amplifier SA 11 . That is, the first sub-sense amplifier SA 11  may be connected to both the first bit line BL 11  of the first sub-memory array SMA 11  and the first complementary bit line BLB 11  of the first dummy memory array DMA 11 . The first sub-sense amplifier SA 11  may perform a read/write operation for the memory cell connected to the first bit line BL 11  by using the first complementary bit line BLB 11 . 
     The second dummy memory array DMA 12  may include a second complementary bit line BLB 12 . The second complementary bit line BLB 12  may extend in the first direction X. The second complementary bit line BLB 12  may be connected to the second sub-sense amplifier SA 12 . That is, the second sub-sense amplifier SA 12  may be connected to both the second bit line BL 12  of the second sub-memory array SMA 12  and the second complementary bit line BLB 12  of the second dummy memory array DMA 12 . The second sub-sense amplifier SA 12  may perform a read/write operation for the memory cell connected to the second bit line BL 12  by using the second complementary bit line BLB 12 . 
     In some embodiments, the first bit line BL 11  and the second bit line BL 12  may be disposed in the second cell region CELL 2 , and the first complementary bit line BLB 11  and the second complementary bit line BLB 12  may be disposed in the first peripheral circuit region PERI 1 . That is, the first complementary bit line BLB 11  and the second complementary bit line BLB 12  may not be disposed in the second cell region CELL 2 . The first complementary bit line BLB 11  and the second complementary bit line BLB 12  may be embedded in the first peripheral circuit region PERI 1  rather than the second cell region CELL 2 . As the first and second dummy memory arrays DMA 11  and DMA 12  including the first complementary bit line BLB 11  and the second complementary bit line BLB 12  are not disposed in the second cell region CELL 2 , an area of the second cell region CELL 2  of the memory device  100  may be reduced. That is, a memory device  100  having an increased cell density may be provided. 
     Referring to  FIG.  6    (e.g., in the context of  FIG.  4   , the first sub-sense amplifier SA 11  may be connected to the first bit line BL 11  and the first complementary bit line BLB 11 . 
     The first memory cell MC 1  may be connected to both the first bit line BL 11  and the first word line WL 1 , and may be disposed at an intersection point between the first bit line BL 11  and the first word line WL 1 . The first memory cell MC 1  may include a first transistor TR 1  and a first capacitor C 1 . The first memory cell MC 1  may perform a read/write operation by charging or discharging the first capacitor C 1  by the first sub-sense amplifier SA 11 . A first memory cell MC 1 ′ may be connected to the first complementary bit line BLB 11  and a first word line WL 1 ′, and may be disposed at an intersection point between the first complementary bit line BLB 11  and the first word line WL 1 ′. The first memory cell MC 1 ′ may include a first transistor TR 1 ′ and a first capacitor C 1 ′. The first memory cell MC 1 ′ may correspond to a memory cell referred to in the case that the first sub-sense amplifier SA 11  performs a read/write operation for the first memory cell MC 1 . That is, the first memory cell MC 1 ′ may correspond to a complementary relation with the first memory cell MC 1 . In addition, the first complementary bit line BLB 11  may correspond to a complementary relation with the first bit line BL 11 . 
     In some embodiments, the first bit line BL 11  may be included in the first sub-memory array SMA 11 , whereas the first complementary bit line BL 11  may be included in the first dummy memory array DMA 11 . The first sub-sense amplifier SA 11  may perform a read/write operation of data by using the first complementary bit line BLB 11  and the first bit line BL 11 , which are disposed in their respective regions different from each other. 
       FIG.  7    is a cross-sectional view further illustrating the first region REG 1  indicated in  FIG.  5   . 
     Referring to  FIG.  7   , the memory device  100  may include a first substrate SUB 1 , a second substrate SUB 2 , a third substrate SUB 3 , a first sub-sense amplifier SA 11 , first and second metal lines ML 1  and ML 2 , first and second metal contacts MCN 1  and MCN 2 , a first bit line BL 11 , and a first complementary bit line BLB 11 . In this case, the first sub-sense amplifier SA 11  and the first bit line BL 11  may be disposed in the second cell region CELL 2 , and the first complementary bit line BLB 11  may be disposed in the first peripheral circuit region PERI 1 . The second substrate SUB 2  may be disposed on the first substrate SUB 3 , and the third substrate SUB 3  may be disposed on the second substrate SUB 3 . 
     The first bit line BL 11  may be connected to the first sub-sense amplifier SA 11  through the second metal line ML 2  and the second metal contact MCN 2 , and the first complementary bit line BLB 11  may be connected to the first sub-sense amplifier SA 11  through the first metal line ML 1  and the first metal contact MCN 1 . 
     In this case, the first complementary bit line BLB 11  may be disposed on the second substrate SUB 2 . The first sub-sense amplifier SA 11  and the first bit line BL 11  may be disposed on the third substrate SUB 3 . A height from a lower surface of the first substrate SUB 1  to the first bit line BL 11  may be a first height H 1 , a height from the lower surface of the first substrate SUB 1  to the first sub-sense amplifier SA 11  may be a second height H 2 , and a height from the lower surface of the first substrate SUB 1  to the first complementary bit line BLB 11  may be a third height H 3 . In this case, the third height H 3  may be lower than the first height H 1  and the second height H 2 . That is, the first complementary bit line BLB 11  may be embedded in the first peripheral circuit region PERI 1 , and may be formed in a region deeper than the first bit line BL 11  and the first sub-sense amplifier SA 11 . Therefore, the memory device  100  including a cell region having a reduced area may be provided. 
       FIGS.  8  and  9    are respective conceptual diagrams illustrating a bit line and a complementary bit line according to some embodiments. 
     Referring to  FIG.  8   , the first bit line BL 11  may have a first length  a   1  in the first direction X, and the first complementary bit line BL 11  may have a second length  a   2  in the first direction X. 
     A capacitance C of the first bit line BL 11  or the first complementary bit line BLB 11  may be determined using Equation 1 that follows: 
     
       
         
           
             C 
             = 
             ∈ 
             ⋅ 
             
               a 
               t 
             
           
         
       
     
     Here, the capacitance of the bit line is inversely proportional to a thickness of the bit line, and is proportional to a length of the bit line. 
     The second length  a   2  may be greater than the first length  a   1 . In this way, the second length  a   2  of the first complementary bit line BLB 11  is greater than the first length  a   1  of the first bit line BL 11 , so that the capacitance of the first complementary bit line BLB 11  and the capacitance of the first bit line BL 11  may be adjusted to be substantially equal to each other. 
     Referring to  FIG.  9   , the first bit line BL 11  may have a first thickness  t   1 , and the first complementary bit line BLB 11  may have a second thickness  t   2 . The first thickness  t   1  may be greater than the second thickness  t   2 . In this way, the second thickness  t   2  of the first complementary bit line BLB 11  may be smaller than the first thickness  t   1  of the first bit line BL 11 , so that the capacitance of the first complementary bit line BLB 11  and the capacitance of the first bit line BL 11  may be substantially equal to each other. 
     As described above, the capacitance of the first complementary bit line BLB 11  may be adjusted, and the memory device  100  having more improved performance may be provided. 
       FIG.  10    is a cross-sectional view further illustrating in one example the first edge region EDG 1  of  FIGS.  3  and  4    according to some embodiments. 
     Referring to  FIG.  10   , the memory device  100  may include a first logic circuit LC 1 . In this case, the first logic circuit LC 1  may be disposed in the first peripheral circuit region PERI 1 . The first logic circuit LC 1  may correspond to the control logic circuit  110 , the address register  120 , the bank control logic circuit  130 , the row address multiplexer  140 , the refresh counter  145 , the column address latch  150 , the row decoder  160 , the column decoder  170 , the I/O gating circuit  190 , the ECC engine  191 , and the data I/O buffer  195  of  FIG.  2   . 
     The first complementary bit line BLB 11  may be disposed on the first substrate SUB 1 . The height from the lower surface of the first substrate SUB 1  to the first complementary bit line BLB 11  may correspond to a third height H 3 ′. The first complementary bit line BLB 11  may be connected to the first sub-sense amplifier SA 11  through the first metal line ML 1  and the first metal contact MCN 1 . 
     The first logic circuit LC 1  may be spaced apart from the lower surface of the first substrate SUB 1  as much as a fourth height H 4 . In this case, the fourth height H 4  may be greater than the third height H 3 ′. That is, both the first complementary bit line BLB 11  and the first logic circuit LC 1  may be disposed in the first peripheral circuit region PERI 1 . Also, the first complementary bit line BLB 11  may be disposed below the first logic circuit LC 1 . As the first complementary bit line BLB 11  is buried in the first peripheral circuit region PERI 1  rather than the second cell region CELL 2 , the memory device  100  in which a cell area is reduced may be provided. 
       FIG.  11    is a cross-sectional view further illustrating in another example the first region EDG 1  of  FIGS.  3  and  4    according to some embodiments. 
     Referring to  FIG.  11   , the first complementary bit line BLB 11  may be disposed in the second substrate SUB 2 . The first complementary bit line BLB 11  may extend in the second direction Y. That is, the first complementary bit line BLB 11  may extend in a direction other than the first direction X, but the embodiments of the present disclosure are not limited thereto. The first complementary bit line BLB 11  may extend in a direction other than the first direction X and the second direction Y. 
       FIG.  12    is an enlarged view further illustrating a second region REG 2  indicated in  FIG.  4   . 
     Referring to  FIG.  12   , the second cell region CELL 2  corresponding to the second region REG 2  may include a first sub-sense amplifier SA m   1 , a first sub-sense amplifier SA(m+1)1, a second sub-sense amplifier SA m   2 , a second sub-sense amplifier SA(m+1)2, a first sub-memory array SMA m   1 , and a second sub-memory array SMA m   2 . The second peripheral circuit region PERI 2  corresponding to the second region REG 2  may include a first dummy memory array DMA 21  and a second dummy memory array DMA 22 . 
     The first sub-memory array SMA m   1  may include a first bit line BL m   1  and a first bit line BL( m + 1 ) 1 . The first bit line BLm1 may be connected to the first sub-sense amplifier SA m   1 , and the first bit line BL( m + 1 ) 1  may be connected to the first sub-sense amplifier SA(m+1)1. The second sub-memory array SMA m   2  may include a second bit line BL m   2  and a second bit line BL( m + 1 ) 2 . The second bit line BL m   2  may be connected to the second sub-sense amplifier SA m   2 , and the second bit line BL( m + 1 ) 2  may be connected to the second sub-sense amplifier SA(m+1)2. An m(th) word line WLm may be connected to the first sub-memory array SMA m   1  and the second sub-memory array SMA m   2 . 
     The first dummy memory array DMA 21  may be disposed to be spaced apart from the first sub-sense amplifier SA(m+1)1 in the first direction X. The first dummy memory array DMA 21  may include a first complementary bit line BLB( m + 1 ) 1 . The first dummy memory array DMA 21  may be disposed in the second peripheral circuit region PERI 2  not the second cell region CELL 2 . The first sub-sense amplifier SA(m+1)1 may perform a read/write operation for the memory cell connected to the first bit line BL( m + 1 ) 1  by using the first complementary bit line BLB( m + 1 ) 1 . 
     The second dummy memory array DMA 22  may be disposed to be spaced apart from the second sub-sense amplifier SA(m+1)2 in the first direction X. The second dummy memory array DMA 22  may include a second complementary bit line BLB( m + 1 ) 2 . The second dummy memory array DMA 22  may be disposed in the second peripheral circuit region PERI 2  not the second cell region CELL 2 . The second sub-sense amplifier SA(m+1)2 may perform a read/write operation for the memory cell connected to the second bit line BL( m + 1 ) 2  by using the second complementary bit line BLB( m + 1 ) 2 . 
     As the first complementary bit line BLB( m + 1 ) 1  and the second complementary bit line BLB( m + 1 ) 2  are disposed in the second peripheral circuit region PERI 2 , an area of the second cell region CELL 2  may be reduced, and the memory device  100  having an increased cell density may be provided. 
     Hereinafter, the memory device  100  according to some embodiments will be described in some additional detail with reference to  FIGS.  13 ,  14  and  15   . 
       FIGS.  13  and  14    are respective plan views illustrating the first region REG 1  according to some embodiments, and  FIG.  15    is a cross-sectional view further illustrating the first region REG 1  of  FIGS.  13  and  14   . 
     Referring to  FIGS.  13  and  14   , the second memory bank BNK 2  corresponding to the first region REG 1  may include a first sub-sense amplifier SA 11 , a second sub-sense amplifier SA 12 , a first sub-memory array SMA 11 , a second sub-memory array SMA 12 , a first dummy memory array DMA 11 , and a second dummy memory array DMA 12 . 
     The first sub-memory array SMA 11  and the first dummy memory array DMA 11  may be connected to the first sub-sense amplifier SA 11 . The first sub-memory array SMA 11  may include a first bit line BL 11 , and the first dummy memory array DMA 11  may include a first complementary bit line BLB 11 . The first word line WL 1  may be connected to the first bit line BL 11 , but may not be connected to the first complementary bit line BLB 11 . The first complementary bit line BLB 11  may be disposed below the first bit line BL 11 . The first sub-memory array SMA 11  may overlap the first dummy memory array DMA 11 , but the embodiments of the present disclosure are not limited thereto. 
     The second sub-memory array SMA 12  and the second dummy memory array DMA 12  may be connected to the second sub-sense amplifier SA 12 . The second sub-memory array SMA 12  may include a second bit line BL 12 , and the second dummy memory array DMA 12  may include a second complementary bit line BLB 12 . The first word line WL 1  may be connected to the second bit line BL 12 , but may not be connected to the second complementary bit line BLB 12 . The second complementary bit line BLB 12  may be disposed below the second bit line BL 12 . The second sub-memory array SMA 12  may overlap the second dummy memory array DMA 12 , but the embodiments of the present disclosure are not limited thereto. 
     The first and second dummy memory arrays DMA 11  and DMA 12  may be disposed in the second cell region CELL 2  or the second bank memory array BMA 2 , not the first peripheral circuit region PERI 1 . The first and second complementary bit lines BLB 11  and BLB 12  included in the first and second dummy memory arrays DMA 11  and DMA 12  may be disposed below the first and second bit lines BL 11  and BL 12 , whereby the memory device  100  having an increased cell density may be provided. 
     In this case, the length of each of the first and second complementary bit lines BLB 11  and BLB 12  may be greater than that of each of the first and second bit lines BL 11  and BL 12 , and the thickness of each of the first and second complementary bit lines BLB 11  and BLB 12  may be less than that of each of the first and second bit lines BL 11  and BL 12 . 
     Referring to  FIG.  15   , the memory device  100  may include a substrate SUB 0 , a first substrate SUB 1 , a second substrate SUB 2 , a third substrate SUB 3 , a first sub-sense amplifier SA 11 , first and second metal lines ML 1  and ML 2 , first and second metal contacts MCN 1  and MCN 2 , a first bit line BL 11 , a first complementary bit line BLB 11 , a first word line WL 1 , and the like. The first sub-sense amplifier SA 11 , the first and second metal lines ML 1  and ML 2 , the first and second metal contacts MCN 1  and MCN 2 , the first bit line BL 11 , the first complementary bit line BLB 11 , and the first word line WL 1  may be disposed in the second cell region CELL 2 , and may not be disposed in the first peripheral circuit region CELL 1  and the second peripheral circuit region CELL 2 . 
     The first sub-sense amplifier SA 11  may be disposed on the third substrate SUB 3 . A height from a lower surface of the substrate SUBO to the first sub-sense amplifier SA 11  may be a fifth height H 5 . The first bit line BL 11  may be disposed on the third substrate SUB 3 . A height from the lower surface of the substrate SUBO to the first bit line BL 11  may be a sixth height H 6 . The first word line WL 1  may be disposed in the first substrate SUB 1 . A height from the substrate SUBO to the first word line WL 1  may be a seventh height H 7 . The first complementary bit line BLB 11  may be disposed on the substrate SUBO. A height from the lower surface of the substrate SUBO to the first complementary bit line BLB 11  may be an eighth height H 8 . 
     The eighth height H 8  may be less than the fifth to seventh heights H 5  to H 7 . That is, the first complementary bit line BLB 11  may be formed in a region deeper than the first sub-sense amplifier SA 11 , the first bit line BL 11 , and the first word line WL 1 . The first complementary bit line BLB 11  is not formed in the first peripheral circuit region PERI 1  but formed in the second cell region CELL 2 , whereby the memory device  100  having an increased cell density may be provided. 
       FIG.  16    is a block diagram illustrating a memory system according to some embodiments. 
     Referring to  FIG.  16   , the host device  20  may include a memory controller  10 . That is, in the memory system of  FIG.  1   , the memory controller  10  was disposed external to the host device  20 , whereas the memory controller  10  of  FIG.  16    may be internal to the host device  20 . The host device  20  may control the memory device  100  through the memory controller  10 . In this case, the host device  20  may perform communication with the memory device  100  using one or more conventionally-understood and commercially-available technical standards, like those related to protocols associated with double data rate (DDR), low power double data rate (LPDDR), graphics data rate (GDDR), Wide I/O, High Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), and/or Compute eXpress Link (CXL). 
       FIG.  17    is a cross-sectional diagram illustrating a semiconductor package according to some embodiments. 
     Referring to  FIG.  17   , a semiconductor package  1000  may include a stacked memory device  1100 , a system-on-chip  1200 , an interposer  1300 , and a package substrate  1400 . The stacked memory device  1100  may include a buffer die  1110  and core dies  1120  to  1150 . 
     Each of the core dies  1120  to  1150  may include a memory cell array. The core dies  1120  to  1150  may include the memory device  100  described with reference to  FIGS.  1  to  16   . The buffer die  1110  may include a physical layer  1111  and a direct access region (DAB)  1112 . The physical layer  1111  may be electrically connected to a physical layer  1210  of the system-on-chip  1200  through the interposer  1300 . The stacked memory device  1100  may receive signals from the system-on-chip  1200  through the physical layer  1111 , or may transmit the signals to the system-on-chip  1200 . 
     The direct access region  1112  may provide an access path that may test the stacked memory device  1100  without passing through the system-on-chip  1200 . The direct access region  1112  may include a conductive means (e.g., port or pin) that may directly perform communication with an external test device. A test signal and data received through the direct access region  1112  may be transmitted to the core dies  1120  to  1150  through TSVs. Data read from the core dies  1120  to  1150  to test the core dies  1120  to  1150  may be transmitted to the test device through the TSVs and the direct access region  1112 . Therefore, a direct access test for the core dies  1120  to  1150  may be performed. 
     The buffer die  1110  and the core dies  1120  to  1150  may be electrically connected to one another through TSVs  1101  and bumps  1102 . The buffer die  1110  may receive signals provided to each channel through the bumps  1102  allocated for each channel from the system-on-chip  1200 . For example, the bumps  1102  may be micro-bumps. 
     The system-on-chip  1200  may execute applications supported by the semiconductor package  1000  by using the stacked memory device  1100 . For example, the system-on-chip  1200  may include at least one processor of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a neural processing unit (NPU), a tensor processing unit (TPU), a vision processing unit (VPU), an image signal processor (ISP), or a digital signal processor (DSP) to execute specialized computations. 
     The system-on-chip  1200  may include the physical layer  1210  and a memory controller  1220 . The physical layer  1210  may include I/O circuits for transmitting and receiving signals to and from the physical layer  1111  of the stacked memory device  1100 . The system-on-chip  1200  may provide various signals to the physical layer  1111  through the physical layer  1210 . The signals provided to the physical layer  1111  may be transferred to the core dies  1120  to  1150  through the TSVs  1101  and interface circuits of the physical layer  1111 . 
     The memory controller  1220  may control the overall operation of the stacked memory device  1100 . The memory controller  1220  may transmit signals for controlling the stacked memory device  1100  to the stacked memory device  1100  through the physical layer  1210 . The memory controller  1220  may correspond to the memory controller  10  of  FIG.  1   . 
     The interposer  1300  may connect the stacked memory device  1100  with the system-on-chip  1200 . The interposer  1300  may connect the physical layer  1111  of the stacked memory device  1100  with the physical layer  1210  of the system-on-chip  1200 , and may provide physical paths formed using conductive materials. Therefore, the stacked memory device  1100  and the system-on-chip  1200  may be stacked on the interposer  1300  to transmit and receive signals to and from each other. 
     Bumps  1103  may be attached to an upper portion of the package substrate  1400 , and solder balls  1104  may be attached to a lower portion of the package substrate  1400 . For example, the bumps  1103  may be flip-chip bumps. The interposer  1300  may be stacked on the package substrate  1400  through the bumps  1103 . The semiconductor package  1000  may transmit and receive signals to and from other external packages or semiconductor devices through the solder balls  1104 . For example, the package substrate  1400  may be a printed circuit board (PCB). 
       FIG.  18    is a perspective diagram illustrating in one example a semiconductor package according to some embodiments. 
     Referring to  FIG.  18   , the semiconductor package  2000  may include a plurality of stacked memory devices  2100  and a system-on-chip  2200 . The stacked memory devices  2100  and the system-on-chip  2200  may be stacked on the interposer  2300 , and the interposer  2300  may be stacked on a package substrate  2400 . The semiconductor package  2000  may transmit and receive signals to and from other external packages or semiconductor devices through solder balls  2001  attached to a lower portion of the package substrate  2400 . 
     Each of the stacked memory devices  2100  may be implemented based on the HBM standard, but the present disclosure is not limited thereto. Each of the stacked memory devices  2100  may be implemented based on the GDDR, HMC, or Wide I/O standard. Each of the stacked memory devices  2100  may correspond to the stacked memory device  1100  of  FIG.  18   . 
     The system-on-chip  2200  may include at least one processor such as a CPU, an AP, a GPU and an NPU, and a plurality of memory controllers for controlling the plurality of stacked memory devices  2100 . The system-on-chip  2200  may transmit and receive signals to and from a corresponding stacked memory device through the memory controller. The system-on-chip  2200  may correspond to the system-on-chip  1200  of  FIG.  17   . 
       FIG.  19    is a cross-sectional diagram illustrating a semiconductor package according to some embodiments. 
     Referring to  FIG.  19   , the semiconductor package  3000  may include a stacked memory device  3100 , a host die  3200 , and a package substrate  3300 . The stacked memory device  3100  may include a buffer die  3110  and core dies  3120  to  3150 . The buffer die  3110  may include a physical layer  3111  for performing communication with the host die  3200 , and each of the core dies  3120  to  3150  may include a memory cell array. 
     The host die  3200  may include a physical layer  3210  for performing communication with the stacked memory device  3100 , and a memory controller  3220  for controlling the overall operation of the stacked memory device  3100 . The host die  3200  may also include a processor for controlling the overall operation of the semiconductor package  3000  and executing an application supported by the semiconductor package  3000 . For example, the host die  3200  may include at least one processor such as a CPU, an AP, a GPU and an NPU. 
     The stacked memory device  3100  may be disposed on the host die  3200  based on TSVs  3001  and vertically stacked on the host die  3200 . Therefore, the buffer die  3110 , the core dies  3120  to  3150  and the host die  3200  may be electrically connected to one another through the TSVs  3001  and bumps  3002  without an interposer. For example, the bumps  3002  may be micro-bumps. 
     Bumps  3003  may be attached to an upper portion of the package substrate  3300 , and solder balls  3004  may be attached to a lower portion of the package substrate  3300 . For example, the bumps  3003  may be flip-chip bumps. The host die  3200  may be stacked on the package substrate  3300  through the bumps  3003 . The semiconductor package  3000  may transmit and receive signals to and from other external packages or semiconductor devices through the solder balls  3004 . 
     Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that the present disclosure can be implemented in various forms without being limited to the above-described embodiments and can be embodied in other specific forms without departing from the technical spirit and essential characteristics. Thus, the above embodiments are to be considered in all respects as illustrative and not restrictive.