Patent Publication Number: US-8983020-B2

Title: Shift register circuit and driving method thereof

Description:
TECHNICAL FIELD 
     The present disclosure relates to a display technical field, and more particularly to a shift register circuit and a driving method thereof. 
     BACKGROUND 
     To reduce the need of a large number of driver integrated chip (IC) and thereby meeting the compact design requirement, some liquid crystal display (LCD) manufacturers use the gate driver on array (GOA) technology to manufacture the shift register in the LCD manufacture process. 
     With the increasing of display resolution, the distance between each two pixels in an LCD is getting smaller and smaller and consequently the interaction between the pixels is getting more and more serious. One of the interaction issues is: the pixels being charged (or, updated) may result in a pixel charge coupling effect on those pixels already have been charged (or, updated), and thereby leading to an abnormal display image, such as low brightness uniformity. 
     In today&#39;s pixel array structure of LCD panel, the half source driving (HSD) structure is able to reduce the cost of source drivers by doubling the number of scan line but cutting half the number of data line. However, if the HSD structure is employed on the gate drive circuit board (regardless the GOA structure or the IC packaging structure), the aforementioned pixel voltage coupling effect still occurs and the abnormal display image issue may get worst. 
     SUMMARY 
     An embodiment of the disclosure is to provide a shift register circuit, which includes a first shift register string and a second shift register string. The first shift register string is configured to receive a first start signal and output a first-stage control signal. The second shift register string, electrically connected to the first shift register string, is configured to receive the first-stage control signal and a second start signal and output the first pulse of a first-stage scan signal according to the first-stage control signal and the second start signal and consequently output the second pulse of the first-stage scan signal according to the second start signal; wherein the first and second pulses are configured to have different pulse widths. 
     Another embodiment of the disclosure is to provide a driving method of a shift register circuit. The shift register circuit includes a first shift register string and a second shift register string. The driving method includes: providing a first start signal to the first shift register string and thereby configuring the first shift register string to output a first-stage control signal; and providing the first-stage control signal and a second start signal to the second shift register string and thereby configuring the second shift register string to output the first pulse of a first-stage scan signal according to the first-stage control signal and the second start signal and consequently output the second pulse of the first-stage scan signal according to the second start signal, wherein the first and second pulses are configured to have different pulse widths. 
     Still another embodiment of the disclosure is to provide a shift register circuit, which includes a shift register string. The shift register string includes a first pull-down unit and a second pull-down unit. The shift register string is configured to receive a control signal and a start signal and output the first pulse of a first-stage scan signal according to the control signal and the start signal and consequently output the second pulse of the first-stage scan signal according to the start signal, wherein the first and second pulses are configured to have different pulse widths. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
         FIG. 1  is a schematic view of a shift register circuit in accordance with an embodiment of the present disclosure; 
         FIG. 2  is a schematic waveform view of the signals associated with the shift register circuit shown in  FIG. 1 ; 
         FIGS. 3A ,  3 B are schematic in-detailed circuit views of the first stage of first shift register and the first stage of second shift register shown in  FIG. 1  in accordance with a first embodiment of the present disclosure, respectively; 
         FIGS. 4A ,  4 B are schematic in-detailed circuit views of the first stage of first shift register and the first stage of second shift register shown in  FIG. 1  in accordance with a second embodiment of the present disclosure, respectively; 
         FIGS. 5A ,  5 B are schematic in-detailed circuit views of the first stage of first shift register and the first stage of second shift register shown in  FIG. 1  in accordance with a third embodiment of the present disclosure, respectively; 
         FIG. 6  is a schematic flowchart illustrating a driving method of a shift register circuit in accordance with an embodiment of the present disclosure; 
         FIG. 7  is a schematic view illustrating a signal connection between a first shift register (except the first stage of first shift register) in the first shift register string and a respective second shift register (except the first stage of second shift register) in the second shift register string; and 
         FIG. 8  is a schematic view of a display apparatus employing the shift register circuit of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The present disclosure will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this disclosure are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. 
       FIG. 1  is a schematic view of a shift register circuit in accordance with an embodiment of the present disclosure. As shown, the shift register circuit  100  in this embodiment includes a first shift register string  10  and a second shift register string  20 . 
     The first shift register string  10  includes a plurality of stages of first shift register, such as the first stage of first shift register  11 , the second stage of first shift register  13 , and so on. The first stage of first shift register  11  is configured to receive a start signal SP 2 , a clock signal CK 2 , a complementary clock signal XCK 2 , a second-stage control signal K( 2 ) and accordingly output a first-stage control signal K( 1 ) to the second stage of first shift register  13 . The second stage of first shift register  13  is configured to the receive first-stage control signal K( 1 ), the clock signal CK 2 , the complementary clock signal XCK 2 , a third-stage control signal K( 3 ) and accordingly output a second-stage control signal K( 2 ). In addition, it is understood that the rest first shift registers in the first shift register string  10  each have the signal connection similar to that of the first stage of first shift register  11  and the second stage of first shift register  13 . 
     The second shift register string  20  includes a plurality of stages of second shift register, such as the first stage of second shift register  21 , the second stage of second shift register  23 , and so on. The first stage of second shift register  21  is configured to receive a start signal SP 1 , a clock signal CK 1 , a complementary clock signal XCK 1 , the first-stage control signal K( 1 ) from the first stage of first shift register  11 , a second-stage scan signal G( 2 ) and accordingly output a first-stage scan signal G( 1 ). The second stage of second shift register  23  is configured to the receive first-stage scan signal G( 1 ), the clock signal CK 1 , the complementary clock signal XCK 1 , the second-stage control signal K( 2 ) from the second stage of first shift register  13 , a third-stage scan signal G( 3 ) and accordingly output the second-stage scan signals G( 2 ). In addition, it is understood that the rest second shift registers in the second shift register string  20  each have the signal connection similar to that of the first stage of second shift register  21  and the second stage of second shift register  23 . 
       FIG. 2  is a schematic waveform view of the signals associated with the shift register circuit  100  shown in  FIG. 1 ; wherein each two adjacent dotted lines presents the same time length. Please refer to  FIGS. 1 ,  2  both. The start signal SP 2  is configured to provide one pulse to the first stage of first shift register  11  in one frame period; and accordingly the first stage of first shift register  11  is configured to, in response to the receiving of the pulse of the start signal SP 2 , output the first-stage control signal K( 1 ) to both of the first stage of second shift register  21  and the second stage of first shift register  13  according to the clock signal CK 2 , the complementary clock signal XCK 2  and the second-stage control signal K( 2 ). 
     In addition, the start signal SP 1  is configured to provide two pulses to the first stage of second shift register  21  in one frame period; and accordingly the first stage of second shift register  21  is configured to, in response to the receiving of the two pulses of the start signal SP 1 , output the first-stage scan signal G( 1 ) according to the clock signal CK 1 , the complementary clock signal XCK 1 , the first-stage control signal K( 1 ) and the second-stage scan signals G( 2 ). 
     Specifically, the first stage of second shift register  21  is configured to output the first pulse of the first-stage scan signal G( 1 ) according to the first-stage control signal K( 1 ) and the start signal SP 1  and then output the second pulse of the first-stage scan signal G( 1 ) according to the start signal SP 1 . The first and second pulses of the first-stage scan signal G( 1 ) are configured to have different pulse widths; in this embodiment, the first pulse is configured to have a pulse width half to that of the second pulse. Specifically, in this embodiment, the generation of the first pulse of the first-stage scan signal G( 1 ) according to the first-stage control signal K( 1 ) is realized by configuring the first-stage control signal K( 1 ) to turn on both of the first pull-down unit  25  (shown in  FIG. 3B ) and the second pull-down unit  27  (shown in  FIG. 3B ). Therefore, by using the first pulse of the first-stage scan signal G( 1 ) to perform the pre-charging operation on the electrically-connected pixels in advance, these electrically-connected pixels can have a narrowed down potential difference while being charged by the second pulse of the first-stage scan signal G( 1 ). Thus, the voltage coupling effect on the potential of the pixels already have been charged is reduced; and consequently the unusual displaying issue can be avoided in this embodiment. 
     For example, in one frame period, because the pixels electrically connected to the second-stage scan signal G( 2 ) are performed the pre-charging operation by the first pulse thereof in advance, these electrically-connected pixels can have a narrowed down potential variation while being updated by the second pulse of the second-stage scan signal G( 2 ). Thus, the voltage coupling effect, resulted via the stray capacitors and on the pixels electrically connected to the first-stage scan signal G( 1 ) and have been updated in this frame period, is reduced and consequently the abnormal display image (such as low brightness uniformity) occurring in the prior art can be avoided. 
     Please refer back to  FIG. 2 , again. As shown, in one frame period the start signal SP 2  is configured to have the pulse thereof lagging behind the first pulse of the start signal SP 1 . Specifically, in this embodiment the start signals SP 1  and SP 2  are configured to have the same pulse width, and the start signal SP 2  is configured to have the pulse thereof lagging behind the first pulse of the start signal SP 1  by, for example, a half pulse width. In addition, the first-stage scan signal G( 1 ) is configured to have the first pulse thereof leading ahead of the first pulse of the second-stage scan signal G( 2 ); the second-stage scan signal G( 2 ) is configured to have the first pulse thereof leading ahead of the first pulse of the third-stage scan signal G( 3 ); the first-stage scan signal G( 1 ) is configured to have the second pulse thereof leading ahead of the second pulse of the second-stage scan signal G( 2 ); the second-stage scan signal G( 2 ) is configured to have the second pulse thereof leading ahead of the second pulse of the third-stage scan signal G( 3 ). 
       FIGS. 3A ,  3 B are schematic in-detailed circuit views of the first stage of first shift register  11  and the first stage of second shift register  21  shown in  FIG. 1  in accordance with a first embodiment of the present disclosure, respectively. As shown in  FIG. 3A , the first stage of first shift register  11  includes an input unit  11   a  and an output unit  11   b , both are electrically connected to a connection node bt 1 . The input unit  11   a  is configured to receive the start signal SP 2  and the second-stage control signal K( 2 ) which is outputted from the second stage of first shift register  13 . The output unit  11   b  is configured to receive the clock signal CK 2 , the complementary clock signal XCK 2  and output the first-stage control signal K( 1 ) according to the voltage level at the connection node bt 1 . 
     The input unit  11   a  includes transistors T 1  and T 2 . Specifically, the transistor T 1  has a first end, a control end and a second end. The transistor T 1  is configured to have the first end thereof electrically connected to the control end thereof; the control end thereof for receiving the start signal SP 2 ; and the second end thereof electrically connected to the connection node bt 1 . The transistor T 2  has a first end, a control end and a second end. The transistor T 2  is configured to have the first end thereof electrically connected to the second end of the transistor T 1 ; the control end thereof for receiving the second-stage control signal K( 2 ); and the second end thereof for receiving a voltage source VSS. 
     The output unit  11   b  includes a capacitor C 1  and transistors T 3 ˜T 7 . Specifically, the capacitor C 1  has a first end and a second end. The capacitor C 1  is configured to have the first end thereof for receiving the clock signal CK 2 . The transistor T 3  has a first end, a control end and a second end. The transistor T 3  is configured to have the first end thereof electrically connected to the second end of the capacitor C 1 ; the control end thereof electrically connected to the connection node bt 1 ; and the second end thereof for receiving the voltage source VSS. The transistor T 4  has a first end, a control end and a second end. The transistor T 4  is configured to have the first end thereof for receiving the clock signal CK 2 ; the control end thereof electrically connected to the connection node bt 1 ; and the second end thereof for outputting the first-stage control signal K( 1 ). 
     As shown in  FIG. 3A , the transistor T 5  has a first end, a control end and a second end. The transistor T 5  is configured to have the first end thereof electrically connected to the control end of the transistor T 4 ; the control end thereof electrically connected to the first end of the transistor T 3 ; and the second end thereof electrically connected to the second end of the transistor T 4 . The transistor T 6  has a first end, a control end and a second end. The transistor T 6  is configured to have the first end thereof electrically connected to the second end of the transistor T 5 ; the control end thereof electrically connected to the control end of the transistor T 5 ; and the second end thereof for receiving the voltage source VSS. The transistor T 7  has a first end, a control end and a second end. The transistor T 7  is configured to have the first end thereof electrically connected to the first end of the transistor T 6 ; the control end thereof for receiving the complementary clock signal XCK 2 ; and the second end thereof for receiving the voltage source VSS. 
     As shown in  FIG. 3B , the first stage of second shift register  21  includes an input unit  21   a  and an output unit  21   b , both are electrically connected to a connection node bt 2 . The input unit  21   a  is configured to receive the start signal SP 1  and the second-stage scan signal G( 2 ) which is outputted from the second stage of second shift register  23 . The output unit  21   b  is configured to receive the clock signal CK 1  and the complementary clock signal XCK 1  and output the first-stage scan signal G( 1 ) according to the voltage level at the connection node bt 2 . 
     The input unit  21   a  includes transistors T 8  and T 9 . Specifically, the transistor T 8  has a first end, a control end and a second end. The transistor T 8  is configured to have the first end thereof electrically connected to the control end thereof; the control end thereof for receiving the start signal SP 1 ; and the second end thereof electrically connected to the connection node bt 2 . The transistor T 9  has a first end, a control end and a second end. The transistor T 9  is configured to have the first end thereof electrically connected to the second end of the transistor T 8 ; the control end thereof for receiving the second-stage scan signal G( 2 ); and the second end thereof for receiving the voltage source VSS. 
     As shown in  FIG. 3B , the output unit  21   b  includes a capacitor C 2  and transistors T 10 ˜T 14 . Specifically, the capacitor C 2  has a first end and a second end. The capacitor C 2  is configured to have the first end thereof for receiving the clock signal CK 1 . The transistor T 10  has a first end, a control end and a second end. The transistor T 10  is configured to have the first end thereof electrically connected to the second end of the capacitor C 2 ; the control end thereof electrically connected to the connection node bt 2 ; and the second end thereof for receiving the voltage source VSS. The transistor T 11  (also referred as an output transistor) has a first end, a control end and a second end. The transistor T 11  is configured to have the first end thereof for receiving the clock signal CK 1 ; the control end thereof electrically connected to the connection node bt 2 ; and the second end thereof for outputting the first-stage scan signal G( 1 ). 
     As shown in  FIG. 3B , the transistor T 12  has a first end, a control end and a second end. The transistor T 12  is configured to have the first end thereof electrically connected to the control end of the transistor T 11 ; the control end thereof electrically connected to the first end of the transistor T 10 ; and the second end thereof electrically connected to the second end of the transistor T 11 . The transistor T 13  has a first end, a control end and a second end. The transistor T 13  is configured to have the first end thereof electrically connected to the second end of the transistor T 12 ; the control end thereof electrically connected to the control end of the transistor T 12 ; and the second end thereof for receiving the voltage source VSS. The transistor T 14  has a first end, a control end and a second end. The transistor T 14  is configured to have the first end thereof electrically connected to the first end of the transistor T 13 ; the control end thereof for receiving the complementary clock signal XCK 1 ; and the second end thereof for receiving the voltage source VSS. 
     In addition, as shown in  FIG. 3B , the first pull-down unit  25  is electrically connected to the output unit  21   b  and configured to receive the first-stage control signal K( 1 ). Specifically, the first pull-down unit  25  includes a pull-down transistor PD 1 . The pull-down transistor PD 1  has a first end, a control end and a second end. The pull-down transistor PD 1  is configured to have the first end thereof electrically connected to the second end of the transistor T 11 ; the control terminal thereof for receiving the first-stage control signal K( 1 ); and the second end thereof for receiving the voltage source VSS. 
     The second pull-down unit  27  is electrically connected to the connection node bt 2  and configured to receive the first-stage control signal K( 1 ). Specifically, the second pull-down unit  27  includes a pull-down transistor PD 2 . The pull-down transistor PD 2  has a first end, a control end and a second end. The pull-down transistor PD 2  is configured to have the first end thereof electrically connected to the connection node bt 2 ; the control terminal thereof for receiving the first-stage control signal K( 1 ); and the second end thereof for receiving the voltage source VSS. In addition, the transistors T 1 ˜T 14  and the pull-down transistors PD 1 , PD 2  each can be implemented by either a field effect transistor or a bipolar transistors, and preferably are implemented by a P-type or N-type thin film transistor in this embodiment. 
     One of the generation mean of the first pulse of the scan signal will be described in detail with reference of  FIG. 3A ,  3 B. As shown, the first stage of first shift register  11  shown in  FIG. 3A  and the first stage of second shift register  21  shown in  FIG. 3B  have the similar circuit structure; and the main difference between the two is that the first-stage of second shift register  21  further includes the pull-down transistors PD 1 , PD 2  for the implementation of the first pull-down unit  25  and the second pull-down unit  27 , respectively. Please refer to  FIGS. 2 ,  3 A and  3 B. In one frame period, the first stage of second shift register  21  and the first-stage of first shift register  11  are configured to generate the first pulse of the first-stage scan signal G( 1 ) and the pulse of the first-stage control signal K( 1 ) in response to the receiving of the first pulse of the start signal SP 1  and the pulse of the start signal SP 2 , respectively. 
     Specifically, the first pull-down unit  25  and the second pull-down unit  27  are turned on in response to the receiving of the pulse of the first-stage control signal K( 1 ) and thereby configuring the transistor T 11  to have the control and second ends thereof electrically connected to the voltage source VSS when the first pulse of the first-stage scan signal G( 1 ) is having a pulse width half to that of the second pulse. In other words, the first pulse of the first-stage scan signal G( 1 ) is converted from a logic-high level into a logic-low level at the rising edge of the pulse of the first-stage control signal K( 1 ). Therefore, the first-stage scan signal G( 1 ) is shaped to have the first pulse having a pulse width half to that of the second pulse thereof. It is understood that the first pulse of each one of the scan signals can be generated based on the same manner; and no unnecessary detail is given here. 
       FIGS. 4A ,  4 B are schematic in-detailed circuit views of the first stage of first shift register  11  and the first stage of second shift register  21  shown in  FIG. 1  in accordance with a second embodiment of the present disclosure, respectively; wherein the circuit structures shown in  FIGS. 4A ,  4 B are adapted to used to a bi-directional shift register. As shown, the main difference between the first stage of first shift register  11  and the first stage of second shift register  21  in the second embodiment and that in the first embodiment is: the input units  11   a ,  21   a  in the second embodiment respectively shown in  FIGS. 4A ,  4 B are further configured to be supplied with an input signal Bi and a complementary input signal Xbi; wherein it is to be noted that the input signals Bi, Xbi are not required to be complementary to each other in another embodiment. Because the first stage of first shift register  11  and the first stage of second shift register  21  in the second embodiment respectively shown in  FIGS. 4A ,  4 B each have a circuit structure similar to that in the first embodiment respectively shown in  FIGS. 3A ,  3 B, no unnecessary detail is given here. 
     As shown in  FIG. 4A , the transistor T 1  is configured to have the first end thereof for receiving the input signal Bi; the control end thereof for receiving the start signal SP 2 ; and the second end thereof electrically connected to the connection node bt 1 . The transistor T 2  is configured to have the first end thereof electrically connected to the second end of the transistor T 1 ; the control end thereof for receiving the second-stage control signal K( 2 ); and the second end thereof for receiving the complementary input signal XBi. 
     As shown in  FIG. 4B , the transistor T 8  is configured to have the first end thereof for receiving the input signal Bi; the control end thereof for receiving the start signal SP 1 ; and the second end thereof electrically connected to the connection node bt 2 . The transistor T 9  is configured to have the first end thereof electrically connected to the second end of the transistor T 8 ; the control end thereof for receiving the second-stage scan signal G( 2 ); and the second end thereof for receiving the complementary input signal XBi. 
       FIGS. 5A ,  5 B are schematic in-detailed circuit views of the first stage of first shift register  11  and the first stage of second shift register  21  shown in  FIG. 1  in accordance with a third embodiment of the present disclosure, respectively. As shown, the main difference between the first stage of first shift register  11  and the first stage of second shift register  21  in the third embodiment and that in the first embodiment is: the capacitor C 1  for the voltage regulation in the output unit  11   b  in the first embodiment is replaced by the diode-connected transistors T 15 , T 16  in the third embodiment; and the capacitor C 2  for the voltage regulation in the output unit  21   b  in the first embodiment is replaced by the diode-connected transistors T 17 , T 18  in the third embodiment. Because the first stage of first shift register  11  and the first stage of second shift register  21  in the third embodiment respectively shown in  FIGS. 5A ,  5 B each have a circuit structure similar to that in the first embodiment respectively shown in  FIGS. 3A ,  3 B, no unnecessary detail is given here. 
     As shown in  FIG. 5A , the transistor T 15  is configured to have the first end thereof for receiving the clock signal CK 2 ; and the control and second ends thereof electrically connected to the first end of the transistor T 3 . The transistor T 16  is configured to have the first end thereof for receiving the clock signal CK 2 ; the control end thereof electrically connected to the first end thereof; and the second end thereof electrically connected to the first end of the transistor T 3 . 
     As shown in  FIG. 5B , the transistor T 17  is configured to have the first end thereof for receiving the clock signal CK 1 ; and the control and second ends thereof electrically connected to the first end of the transistor T 10 . The transistor T 18  is configured to have the first end thereof for receiving the clock signal CK 1 ; the control end thereof electrically connected to the first end thereof; and the second end thereof electrically connected to the first end of the transistor T 10 . 
     According to the circuit structures shown in  FIGS. 3A ,  3 B,  4 A,  4 B,  5 A and  5 B, to those ordinarily skilled in the art it is understood that the first stage of first shift register  11  shown in  FIGS. 3A ,  4 A and  5 A has a circuit structure corresponding to that of the first stage of second shift register  21  shown in  FIGS. 3B ,  4 B and  5 B, respectively. In addition, and the main difference between each two of the first stage of first shift registers as well as each two of the first stage of second shift registers is the associated input and output signals, as exemplarily illustrated in  FIG. 7 . 
       FIG. 6  is a schematic flowchart illustrating a driving method of the shift register circuit  100  shown in  FIG. 1  in accordance with an embodiment of the present disclosure. Please refer the  FIGS. 1 and 6  both. In step S 601 , the first shift register string  10  is supplied with the start signal SP 2  and thereby being configured to output the first-stage control signal K( 1 ). 
     Next, in step S 603 , the second shift register string  20  is supplied with the first-stage control signal K( 1 ) and the start signal SP 1  and thereby being configured to output the first pulse of the first-stage scan signal G( 1 ) accordingly; then, the second shift register string  20  outputs the second pulse of the first-stage scan signal G( 1 ) according to the start signal SP 1 . Specifically, the first and second pulses are configured to have a pulse width different to each other; and specifically, the first pulse is configured to have a width half to that of the second pulse. 
     According to the aforementioned description, to those ordinarily skilled in the art it is understood that the first shift registers (except the first stage of first shift register  11 ) each in the first shift register string  10  and the second shift registers (except the first-stage second shift register  21 ) each in the second shift register string  20  can be summarized to have a signal connection as illustrated in  FIG. 7 . 
       FIG. 7  is a schematic view illustrating a signal connection between a first shift register (except the first stage of first shift register  11 ) in the first shift register string  10  and a respective second shift register (except the first stage of second shift register  21 ) in the second shift register string  20 ; wherein the signal connection herein is exemplified by between the n th  stage of first shift register in the first shift register string  10  and the respective n th  stage of second shift register in the second shift register string  20 . As shown, the n th  stage of first shift register in the first shift register string  10  is configured to receive the clock signal CK 2 , the complementary clock signal XCK 2 , the control signal K(n+1) outputted from the (n+1) th  stage of first shift register, the control signal K(n−1) outputted from the (n−1) th  stage of first shift register and accordingly output the n th -stage control signal K(n). The n th  stage of second shift register in the second shift register string  20  is configured to receive the clock signal CK 1 , the complementary clock signal XCK 1 , the control signal K(n) outputted from the n th  stage of first shift register, the scan signal G(n+1) outputted from the (n+1) th  stage of second shift register, the scan signal G(n−1) outputted from the (n−1) th  stage of second shift register and accordingly output the n th -stage scan signal G(n). In addition, to those ordinarily skilled in the art it is understood that the first shift register string  10  and the second shift register string  20  may further include at least one redundant shift register electrically connected to the last stage of first and second shift registers therein, respectively, for providing a feedback signal. 
       FIG. 8  is a schematic view of a display apparatus employing the shift register circuit of the present disclosure. As shown, the display apparatus  800  includes a shift register circuit  82 , a data driving circuit  84  and a display panel  86 . The display panel  86  includes a plurality of pixels  88 , a plurality of data lines  90  and a plurality of scan lines  92 . The data driving circuit  84  is electrically connected to the data lines  90 ; and the shift register circuit  82  is electrically connected to the scan lines  92 . The shift register circuit  82  includes the first shift register string  10  and the second shift register string  20 . The first shift register string  10  includes a plurality of stages of first shift register; wherein the first shift register string  10  herein is exemplified by including six stages of first shift register (i.e., the first stage of first shift register  11 , the second stage of first shift register  13 , . . . , the fifth stage of first shift register  19  and the sixth stage of first shift register  1 D). The second shift register string  20  includes a plurality of stages of second shift register; wherein the second shift register string  20  herein is exemplified by including six stages of second shift register (i.e., the first stage of second shift register  21 , the second stage of second shift register  23 , . . . , the fifth stage of second shift register  29  and the sixth stage of second shift register  2 D). The first shift register  1 D and the second shift register  2 D both are a redundant shift register; and accordingly it is understood that only the first five stages of second shift registers  21 ˜ 29  in the second shift register string  20  are configured to output the scan signals G( 1 )˜G( 5 ), respectively. It is to be noted that the first shift register  1 D and the second shift register  2 D may have no dummy in another embodiment. 
     As shown in  FIG. 8 , the scan signals G( 1 )˜G( 5 ) each are configured to provide two pulses from the shift register circuit  82  in one frame period; wherein the first pulse in each one frame period is used for the pre-charging operation. Take the scan signals G( 1 ) and G( 2 ) in  FIG. 8  as an example and please also reference with  FIG. 2 . After the scan signal G( 1 ) writing voltages to the pixels  88  electrically connected thereto by the second pulse thereof in the first frame period, consequently the scan signal G( 2 ) writes voltages to the pixels  88  electrically connected thereto by the second pulse thereof in the same first frame period. Because the pixels  88  electrically connected to the scan signal G( 1 ) already have been updated in the first frame period while the pixels  88  electrically connected to the scan signal G( 2 ) are being updated by the second pulse of the scan signal G( 2 ), the pixel update performed by the scan signal G( 2 ) may result in a voltage coupling effect on the pixels  88  electrically coupled to the scan signal G( 1 ); in other words, due to the pixels  88  electrically coupled to the scan signal G( 1 ) are already done with the write operation in the first frame period, the voltage coupling resulted from the write operation of the scan signal G( 2 ) on the electrically-coupled pixels  88  may lead to a declining picture quality on the display panel  86 . However, in this present embodiment, due to the scan signal G( 2 ) is configured to perform the pre-charging operation on the pixels  88  electrically coupled thereto by the first pulse thereof in the same first frame period, these electrically-coupled pixels  88  can have less voltage variation while being updated by the second pulse of the scan signal G( 2 ); thus, the voltage coupling effect resulted from the second pulse in the first frame period is reduced consequently. 
     In summary, through configuring the scan signal to have a first pulse and a second pulse in one frame period and using the first period to perform the pre-charging operation on the electrically-connected pixels before these electrically-connected pixels are being updated by the second pulse, these electrically-connected pixels can have a narrowed down potential difference so as to avoid the voltage coupling effect on the pixels already have been charged; thus, the abnormal display image (such as low brightness uniformity along a vertical line) occurring in the prior art is avoided, consequently. Specifically, because having a narrowed down voltage variation, these pixels have been performed by the pre-charging operation can have lower voltage coupling effect on other pixels while being updated; and accordingly the display images can have a brightness with higher uniformity. 
     While the disclosure has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the disclosure needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.