Patent Publication Number: US-11664330-B2

Title: Semiconductor package

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of and claims priority to U.S. patent application Ser. No. 16/109,766 filed on Aug. 23, 2018, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0182025, filed on Dec. 28, 2017 in the Korean Intellectual Property Office, the disclosure of each of which is hereby incorporated by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     Example embodiments of the present disclosure relate to a semiconductor package including a plurality of semiconductor chips. 
     DISCUSSION OF RELATED ART 
     High performance, high speed, and small sizes of electric components have been increasingly demanded with continuing developments of the electronics industry. Responding to this trend, a semiconductor package has been manufactured in such a way that a plurality of semiconductor chips are mounted on a single interposer or package substrate. A warpage in a semiconductor package may be caused by a difference in coefficients of thermal expansion between elements constituting the semiconductor package. A magnitude of the warpage may be increased in a semiconductor package including a plurality of semiconductor chips. 
     SUMMARY 
     According to example embodiments of the inventive concepts, a semiconductor package may include a first substrate having a first surface and a second surface opposite to the first surface, the first substrate including a plurality of first pads on the first surface thereof and a plurality of second pads on the second surface thereof; a first semiconductor chip on the first surface of the first substrate, the first semiconductor chip connected to a first group of first pads of the plurality of first pads; a second semiconductor chip on the first surface of the first substrate, the second semiconductor chip connected to a second group of first pads of the plurality of first pads; a stiffener on the first semiconductor chip and the second semiconductor chip, the stiffener covering a space between the first semiconductor chip and the second semiconductor chip; and an encapsulant on the first surface of the first substrate, the encapsulant covering at least a sidewall of each of the first and second semiconductor chips and the stiffener. 
     According to example embodiments of the inventive concepts, a semiconductor package may include an first substrate having opposite first and second surfaces, wherein the first substrate includes a plurality of first pads on the first surface thereof and a plurality of second pads on the second surface thereof, a first semiconductor chip on the first surface of the first substrate, wherein the first semiconductor chip is connected to first portions of the plurality of first pads and includes a stepped portion that is lower than an upper surface thereof, a second semiconductor chip on the first surface of the first substrate, wherein the second semiconductor chip is connected to second portions of the plurality of first pads and has an upper surface that is substantially flush with a surface of the stepped portion of the first semiconductor chip, a stiffener on the stepped portion of the first semiconductor chip and the second semiconductor chip, wherein the stiffener covers a space between the first semiconductor chip and the second semiconductor chip and has a plate shape, and an encapsulant on the first surface of the first substrate, wherein the encapsulant covers a sidewall of the first semiconductor chip, a sidewall of the second semiconductor chip, and a sidewall of the stiffener. 
     According to example embodiments of the inventive concepts, a semiconductor package may include a package substrate, wherein the package substrate includes an insulating member having opposite first and second surfaces, a plurality of first pads on the first surface of the insulating member, a plurality of second pads on the second surface of the insulating member, and a redistribution layer in the insulating member and connected to the plurality of first pads and the plurality of second pads, a first semiconductor chip on the package substrate, wherein the first semiconductor chip is connected to the plurality of first pads, a second semiconductor chip on the package substrate, wherein the second semiconductor chip is connected to the plurality of second pads, a stiffener on the first semiconductor chip and the second semiconductor chip, wherein the stiffener covers a space between the first and second semiconductor chips, and an encapsulant on the package substrate, wherein the encapsulant covers at least a sidewall of the first semiconductor chip, at least a sidewall of the second semiconductor chip, and a sidewall of the stiffener. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a cross-sectional view of a semiconductor package according to example embodiments. 
         FIG.  2    is a plan view of the semiconductor package of  FIG.  1   . 
         FIGS.  3 A and  3 B  are schematic diagrams representing a warpage phenomenon before and after improvement, to illustrate an effect caused by a stiffener according to example embodiments. 
         FIG.  4    is a cross-sectional view of a semiconductor package according to example embodiments. 
         FIG.  5    is a plan view of the semiconductor package of  FIG.  4   . 
         FIG.  6    is a schematic diagram representing a warpage phenomenon to illustrate an effect caused by a stiffener according to example embodiments. 
         FIG.  7    is a cross-sectional view of a module including the semiconductor package of  FIG.  4     
         FIG.  8    is a cross-sectional view of a semiconductor package according to example embodiments. 
         FIG.  9    is a plan view of the semiconductor package of  FIG.  8   . 
         FIG.  10    is a cross-sectional view of a module including the semiconductor package of  FIG.  8   . 
         FIGS.  11 ,  12 , and  13    are cross-sectional views of a semiconductor package according to example embodiments. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. However, the inventive concepts may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein. 
       FIG.  1    is a cross-sectional view of a semiconductor package according to example embodiments.  FIG.  2    is a plan view of the semiconductor package of  FIG.  1   .  FIG.  1    is a cross-sectional view taken along line I-I′ of  FIG.  2   . 
     Referring to  FIGS.  1  and  2   , a semiconductor package  100  includes an interposer  110  having a first surface  110 A and an opposing second surface  110 B, first semiconductor chip  120  on the first surface  110 A of the interposer  110  and second semiconductor chip  130  on the first surface  110 A of the interposer  110 , and an encapsulant  160  on the first surface  110 A of the interposer  110 . The semiconductor package  100  further includes a stiffener  150  on the first and second semiconductor chips  120  and  130 . 
     The interposer  110  includes a substrate  111 , a wiring circuit  114  in the substrate  111 , a plurality of first pads  112  on the first surface  110 A thereof, and a plurality of second pads  113  on the second surface  110 B thereof. The plurality of first pads  112  and the plurality of second pads  113  may be connected to the wiring circuit  114 . Even though, in  FIG.  1   , the wiring circuit  114  is shown in a dotted line in a portion of the substrate  111 , the inventive concepts are not limited thereto. The wiring circuit  114  may be connected to respective ones of the plurality of first and second pads  112  and  113 . 
     The substrate  111  may be a silicon substrate. In some embodiments, the substrate  111  may be a printed circuit board. For example, the substrate  111  may include a thermosetting resin, e.g., an epoxy resin, a thermoplastic resin, e.g., a polyimide, or a photosensitive insulating material. 
     In some embodiments, the substrate  111  may include a prepreg, an ajinomoto build-up film (ABF), FR-4, or a bismaleimide triazine (BT) resin. 
     Outer terminals  115  are disposed on the plurality of second pads  113  on the second surface  110 B of the interposer  110 . The outer terminals  115  may include tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), bismuth (Bi), and/or an alloy thereof. 
     The first semiconductor chip  120  may have an active surface facing the first surface  110 A of the interposer  110  and an inactive surface opposite to the active surface. The first semiconductor chip  120  includes first connection electrodes (or connection pads)  120 P disposed on the active surface thereof. Connection terminals  116  respectively are disposed between the first connection electrodes  120 P and the first pads  112  of the interposer  110 . The first semiconductor chip  120  may be flip-chip bonded on the first surface  110 A of the interposer  110  by the connection terminals  116 . The first semiconductor chip  120  may include a logic chip, e.g., a controller or a microprocessor. 
     The various pads of a device described herein may be conductive terminals connected to internal wiring of the device, and may transmit signals and/or supply voltages between an internal wiring and/or internal circuit of the device and an external source. For example, chip pads of a semiconductor chip may electrically connect to and transmit supply voltages and/or signals between an integrated circuit of the semiconductor chip and a device to which the semiconductor chip is connected. The various pads may be provided on or near an external surface of the device and may generally have a planar surface area (often larger than a corresponding surface area of the internal wiring to which they are connected) to promote connection to a further terminal, such as a bump or solder ball, and/or an external wiring. 
     Although the second semiconductor chip  130  is shown as a single chip in the drawings, the inventive concepts are not limited thereto. The second semiconductor chip  130  may include a plurality of semiconductor chips (refer to  FIGS.  8  and  9   ). The second semiconductor chip  130  may include a memory chip, such as a high-band memory (HBM). In some embodiments, the second semiconductor chip  130  may include a DRAM, an SRAM, a flash memory, a PRAM, an ReRAM, a FeRAM, or an MRAM. 
     The second semiconductor chip  130  may have an active surface having the second connection electrodes  130 P thereon, and an inactive surface opposite to the active surface. The second semiconductor chip  130  may be flip-chip bonded to the interposer  110  such that the second connection electrodes  130 P are connected to the first pads  112  of the interposer  110  by the connection terminals  116 . According to example embodiments, a first group of the first pads  112  among the plurality of first pads  112  are connected to chip pad of the first semiconductor chip  120  and second group of the first pads  112  among the plurality of first pads  112  are connected to chip pad of the second semiconductor chip  130 . According to example embodiments, the first group of the first pads  112  among the plurality of first pads  112  are not connected to the chip pad of the second semiconductor chip  130  and the second group of the first pads  112  among the plurality of first pads  112  are not connected to the chip pad of the first semiconductor chip  120 . 
     The second semiconductor chip  130  may be laterally spaced apart from the first semiconductor chip  120 . According to this exemplary embodiment, an upper surface  120 T of the first semiconductor chip  120  is positioned at the same level in a direction perpendicular to the first surface  110 A of the interposer  110  as an upper surface  130 T of the second semiconductor chip  130  and a lowermost surface of the first semiconductor chip  120  is positioned at the same level in a direction perpendicular to the first surface  110 A of the interposer  110  as a lowermost surface of the second semiconductor chip  130 . However, the disclosure is not limited thereto. For example, in alternative embodiments, an upper surface  120 T of the first semiconductor chip  120  may be positioned at a level higher than a level of the upper surface  130 T of the second semiconductor chip  130  in a direction perpendicular to the first surface  110 A of the interposer  110  (see, e.g.,  FIG.  12   ). A space S between the first semiconductor chip  120  and the second semiconductor chip  130  may be a region in which a warpage of the semiconductor package  100  is generated due to a difference in coefficients of thermal expansion (CTEs) between other elements of the semiconductor package  100 , e.g., the encapsulant  160  and the interposer  110 . For example, when the encapsulant  160  includes an organic material having a relatively high CTE, such as an epoxy molding compound, and the substrate  111  of the interposer  110  includes silicon, the warpage may be increased by a difference in CTEs therebetween. According to example embodiments, the encapsulant  160  may be single layered and may comprise homogeneous molding compound. 
     The stiffener  150  is disposed on the first semiconductor chip  120  and the second semiconductor chip  130  and connects the first and second semiconductor chips  120  and  130 . The stiffener  150  covers the space S between the first and second semiconductor chips  120  and  130  that may act as a bending region. The stiffener  150  may be attached to the upper surfaces  120 T and  130 T of the first semiconductor chip  120  and the second semiconductor chip  130  using the adhesive layer  161 . The adhesive layer  161  may include a non-conductive film (NCF), an anisotropic conductive film (ACF), an ultraviolet (UV) sensitive film, an instant adhesive, a thermoset adhesive, a laser curable adhesive, an ultrasonic curable adhesive, and a non-conductive paste (NCP). 
     The encapsulant  160  may cover the first and second semiconductor chips  120  and  130 , e.g., sidewalls and portions of upper surfaces of the first and second semiconductor chips  120  and  130 . The encapsulant  160  may cover a sidewall of the stiffener  150 . The encapsulant  160  may have a flat upper surface  100 T that is substantially flush with an upper surface  150 T of the stiffener  150 . The flat upper surface  100 T of the encapsulant  160  may be formed by polishing the encapsulant  160  to expose the stiffener  150 . 
     The stiffener  150  may have a plate shape. The stiffener  150  may have a thickness t in a direction perpendicular to the first surface  110 A of the interposer  110  sufficient enough to prevent or inhibit the warpage from occurring. However, a thickness T of the semiconductor package  100  in a direction perpendicular to the first surface  110 A of the interposer  110  may be limited not to exceed a certain thickness. The thickness t of the stiffener  150  may be less than 20% of the thickness T of the semiconductor package  100 . For example, the thickness t of the stiffener  150  may be less than 500 μm. According to example embodiments, a thickness t 1  of the first semiconductor chip  120  may be the same as the thickness t 2  of the second semiconductor chip  130  in a direction perpendicular to the first surface  110 A of the interposer  110 , but the disclosure is not limited thereto. In alternative embodiments, the first and second semiconductor devices  120  and  130  may have varying thickness in the direction perpendicular to the first surface  110 A of the interposer  110 . According to example embodiments, the thickness t of the stiffener  150  may be less than the thickness t 1  of the first semiconductor chip  120  and the thickness t of the stiffener  150  may be less than the thickness t 2  of the second semiconductor chip  130 . 
     The stiffener  150  may include a material having a rigidity (e.g., Young&#39;s modulus) greater than the encapsulant  160 . 
     According to example embodiments, the stiffener  150  may be rectangular-shaped and the side surfaces of the rectangular-shaped stiffener  150  parallel to the side surfaces of the semiconductor package  100  or the side surfaces of the first and second semiconductor chips  120  and  130  may have corresponding lengths smaller than the length of the upper surface  150 T or the length of the lower surface  150 L of the stiffener  150  in a direction parallel to the first surface  110 A of the interposer  110 . According to example embodiments, the upper surface  150 T of the stiffener  150  may have the same length in a direction parallel to the first surface  110 A of the interposer  110  as the lower surface  150 L of the stiffener in the direction parallel to the first surface  110 A of the interposer  110 . According to example embodiments, the thickness t of the stiffener  150  may be smaller than a thickness of the adhesive layer  161  in the direction perpendicular to the first surface  110 A of the interposer  110 . According to example embodiments, the lower surface  150 L of the stiffener  150  faces the inactive surfaces of the first and second semiconductor chips  120  and  130  (e.g., upper surfaces  120 T and  130 T of the first and second semiconductor chips  120  and  130 , respectively) and the upper surface  150 T of the stiffener  150  faces away from the inactive surfaces of the first and second semiconductor chips  120  and  130 . 
     In some embodiments, the stiffener  150  may include the same material composition as the substrate  111  of the interposer  110 . The material composition of the stiffener  150  allows sufficient control of the stresses caused by the CTE mismatches of the various materials in the semiconductor package  100 ; thereby, providing the semiconductor package  100  with less bowing and so improved co-planarity (in compliance with industry specifications) with the surface (e.g., PCB board) to which it is ultimately bound. Furthermore, the material composition of the stiffener  150  allows a lighter package to be realized, which is beneficial for applications where weight is a factor. In this exemplary embodiment, a mismatch of CTEs between an upper part and a lower part of the semiconductor package  100  may be prevented or minimized, thus reducing or preventing the warpage. According to example embodiments, the stiffener  150  may not include a logic circuit and/or may not include a transistor. The stiffener  150  and the substrate  111  of the interposer  110  may include, e.g., silicon. According to an exemplary embodiment, the stiffener may be formed entirely of crystalline semiconductor material, but the disclosure is not limited thereto. According to example embodiments, the stiffener  150  may extend from a portion of the upper surface  120 T of the first semiconductor chip  120  onto an adjacent portion of the upper surface  130 T of the second semiconductor chip  130  and may be provided at an edge region of the semiconductor package  100 . Thus, warpage in the edge region of the semiconductor package  100  (e.g., edge region of the interposer  110 ) may be reduced. According to example embodiments, the stiffener  150  may include a redistribution line therein as a wiring structure to connect the first and second semiconductor chips  120  and  130 . 
     Referring to  FIG.  2   , an area (or size) of the first semiconductor chip  120  may have larger than an area (or size) of the second semiconductor chip  130 . The stiffener  150  has a first width W 1  in a first direction (i.e., vertical direction) and a second width W 2  in a second direction (i.e., horizontal direction) perpendicular to the first direction. The stiffener  150  may be disposed on the upper surfaces  120 T and  130 T of adjacent portions of the first and second semiconductor chips  120  and  130 . According to example embodiments, less than 50% (e.g., in a range between 20%-40%) of the surface area of the upper surface  120 T of the first semiconductor chip  120  may be covered by the stiffener  150  and more than 50% (e.g., in a range between 60%-100%) of the surface area of the upper surface  130 T of the second semiconductor chip  130  may be covered by the stiffener  150 . However, the disclosure is not limited thereto. For example, in alternative embodiments, the entire surface area of the upper surface  120 T of the first semiconductor chip  120  and the entire surface area of the upper surface  130 T of the second semiconductor chip  130  may be covered by the stiffener  150  (see, e.g.,  FIG.  12   ). 
       FIGS.  3 A and  3 B  are schematic diagrams representing a warpage phenomenon before and after improvement, to illustrate an effect caused by a stiffener according to example embodiments. 
     Referring to  3 A, when stiffener is not disposed on the upper surfaces  120 T and  130 T of adjacent portions of the first and second semiconductor chips  120  and  130 , it is shown that a space C 1  between the first and second semiconductor chips  120  and  130  is highly wrapped. However, when the stiffener is provided to cover a considerable portion (e.g., more than 75%) of the space C 1 , the warpage may be highly reduced in the same space C 1 . 
     Meanwhile, since the area (or size) of the second semiconductor chip  130  is less than the area (or size) of the first semiconductor chip  120 , a contact area between the interposer  110  and the encapsulant  160  may be greater around the second semiconductor chip  130  than around the first semiconductor chip  120 . Thus, a considerable amount of the warpage may be caused in an edge region C 2  of the interposer  110  around the second semiconductor chip  130  as well as in the space C 1  between the first and second semiconductor chips  120  and  130   
     The warpage in the edge region C 2  of the interposer  110  may be controlled by an occupying area of the stiffener  150 . 
       FIG.  4    is a cross-sectional view of a semiconductor package according to example embodiments.  FIG.  5    is a plan view of the semiconductor package of  FIG.  4   .  FIG.  4    illustrates a cross-sectional view taken along line II-II′ of  FIG.  5   .  FIG.  6    is a schematic diagram representing a warpage phenomenon to illustrate an effect caused by a stiffener according to example embodiments. 
     Referring to  FIGS.  4  and  5   , a semiconductor package  100 A is similar to or the same as the semiconductor package  100  described with reference to  FIGS.  1  and  2   , except for a structure of the stiffener  150 ′. 
     Referring to  FIG.  5   , since an area (or size) of the second semiconductor chip  130  may be less than an area (or size) of the first semiconductor chip  120 , a contact area of the interposer  110  and the encapsulant  160  is larger around the second semiconductor chip  130  than around the first semiconductor chip  120 . Thus, an edge region (refer to, e.g., C 2  of  FIG.  6   ) of the interposer  110  around the second semiconductor chip  130  may be warped. 
     According to one exemplary embodiment, the stiffener  150 ′ may extend onto an upper surface of a peripheral portion of the second semiconductor chip  130  adjacent to the edge region of the interposer  110 . For example, a first width W 1 ′ in a first direction (i.e., vertical direction) and a second width W 2 ′ of the stiffener  150 ′ in a second direction (i.e., horizontal direction) perpendicular to the first direction may be increased greater than the first width W 1  and the second width W 2  of the stiffener  150  of the above example embodiment shown in  FIGS.  1  and  2    to further cover the peripheral portion of the second semiconductor chip  130  adjacent to the edge region of the interposer  110 . 
     As a result, as shown in  FIG.  6   , the warpage may be relieved in the edge region C 2  of the interposer  110 . In some embodiments, to improve the warpage in the edge C 2  of the interposer  110 , the stiffener  150 ′ may cover almost the entire upper surface  130 T of the second semiconductor chip  130 . In other embodiments, a stiffener  150  (see  FIG.  12   ) may extend onto the upper surface  120 T of a peripheral portion of the first semiconductor chip  120  that is further away from the second semiconductor chip  130 . 
       FIG.  7    is a cross-sectional view of a module including the semiconductor package of  FIG.  4     
     Referring to  FIG.  7   , a semiconductor package module  200 A includes the semiconductor package  100 A shown in  FIG.  4    and a package substrate  210  which the semiconductor package  100 A is mounted. The semiconductor package module  200 A may be a complete semiconductor package (i.e., a semiconductor package in its final form after completing manufacturing processes of the semiconductor package). The semiconductor package  100 A may be a component of the semiconductor package module  200 A. 
     The package substrate  210  includes upper pads  212 , lower pads  213 , and a redistribution layer connecting the upper pads  212  and the lower pads  213 . The upper pads  212  may be connected to the second pads  113  of the interposer  110  by the outer terminals  115 . The redistribution layer includes at least one wiring circuit formed of a via and a conductive pattern, like a redistribution layer  314  of a package substrate  310  (see  FIG.  13   ). 
     The upper pads  212  may be formed corresponding to the sizes and the arrangements of the second pads  113  of the interposer  110 . The lower pads  213  may be formed to enlarge sizes and spaces of the lower pads  213 , based on input/output (I/O) terminals of a circuit, such as a circuit of a motherboard. Such a circuit may be embodied by the redistribution layer of the package substrate  210 . Outer connection terminals  215 , e.g., solder bumps, to be connected to an outer circuit are disposed on the lower pads  213 , respectively. The outer connection terminals  215  may include may include tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), bismuth (Bi), and/or an alloy thereof. 
     The semiconductor package module  200 A includes a heat spreader  170  on an upper surface of the semiconductor package  100 A, e.g., an upper surface of the stiffener  150 ′. The heat spreader  170  may have a cap structure and extend onto a sidewall of the semiconductor package  100 . The heat spreader  170  may be attached to the semiconductor package  100  using an adhesive member  180 . The heat may be transmitted from the first and second semiconductor chips  120  and  130  to the heat spreader  170  through the stiffener  150 ′. 
     The heat spreader  170  may include a highly thermally conductive material, e.g., metal or ceramic. In some embodiments, the heat spreader  170  may include a thermal interface material (TIM). The adhesive member  180  may include an NCF, an ACF, a UV sensitive film, an instant adhesive, a thermoset adhesive, a laser curable adhesive, an ultrasonic curable adhesive, and an NCP. 
       FIG.  8    is a cross-sectional view of a semiconductor package according to example embodiments.  FIG.  9    is a plan view of the semiconductor package of  FIG.  8   .  FIG.  8    illustrates a cross-sectional view taken along line of  FIG.  9   . 
     Referring to  FIGS.  8  and  9   , a semiconductor package  100 B is similar to or the same as the semiconductor package  100  described with reference to  FIGS.  1  and  2   , except that step portions G are formed in the first semiconductor chip  120 ′, a plurality of the second semiconductor chips  130 A,  130 B,  130 C, and  130 D are provided, two stiffeners  150 A and  150 B are provided, a thickness Ta of the first semiconductor chip  120 ′ and a thickness Tb of the second semiconductor chips  130 A,  130 B,  130 C, and  130 D are different from each other (Ta≠Tb). 
     The semiconductor package  100 B includes the first semiconductor chip  120 ′, such as an application specific integrated circuit (ASIC) and the four second semiconductor chips  130 A to  130 D, such HBMs, around the first semiconductor chip  120 ′. Referring to  FIG.  9   , each two of the four second semiconductor chips  130 A to  130 D are arranged at each of two opposite sides of the first semiconductor chip  120 ′. 
     The thickness Ta of the first semiconductor chip  120 ′ may be different from the thickness Tb of the second semiconductor chips  130 A to  130 D. Referring to  FIG.  8   , the thickness Ta of the first semiconductor chip  120 ′ may be greater than the thickness Tb of the second semiconductor chips  130 A to  130 D. The first semiconductor chip  120 ′ include stepped portions G, which are lower than an upper surface thereof, in a region adjacent to the second semiconductor chips  130 A to  130 D, such that upper surfaces of the stiffeners  150 A and  150 B on the step portions G may be flush with an upper surface of the first semiconductor chip  120 ′. A surface (e.g., a recessed surface) of the first semiconductor chip  120 ′ provided by the step portions G thereof may be substantially flush with upper surfaces of the second semiconductor chips  130 A to  130 D. 
     Referring to  FIG.  9   , the stepped portions G of the first semiconductor chip  120 ′ are formed in opposite peripheral portions thereof, respectively. Each of the stepped portions G may correspond to each two of the second semiconductor chips  130 A to  130 D. 
     The stiffeners  150 A and  150 B may include a first stiffener  150 A and a second stiffener  150 B. The first and second stiffeners  150 A and  150 B may be disposed on the stepped portions G and on the upper surfaces of the second semiconductor chips  130 A to  130 D and cover spaces S 1  and S 2  between the first semiconductor chip  120 ′ and the second semiconductor chips  130 A to  130 D. According to exemplary embodiments, a length of the first stiffener  150 A in a direction parallel to an upper surface of the interposer  110  covering the stepped portion G of the first semiconductor chip  120 ′ adjacent to the second semiconductor chips  130 A and  130 D may be smaller than a length of the first stiffener  150 A in a direction parallel to an upper surface of the interposer  110  covering the upper surfaces of the second semiconductor chips  130 A and  130 D. According to exemplary embodiments, a length of the second stiffener  150 B in a direction parallel to an upper surface of the interposer  110  covering the stepped portion G of the first semiconductor chip  120 ′ adjacent to the second semiconductor chips  130 B and  130 C may be smaller than a length of the first stiffener  150 A in a direction parallel to an upper surface of the interposer  110  covering the upper surfaces of the second semiconductor chips  130 B and  130 C. 
     The stepped portions G in the first semiconductor chip  120 ′ may prevent a thickness of the semiconductor package  100 B from increasing by a thickness t of the first and second stiffeners  150 A and  150 B. In some embodiments, the stepper portions G may be formed to have a depth d in a direction perpendicular to an upper surface of the interposer  110  greater than the thickness t of the first and second stiffeners  150 A and  150 B in the direction perpendicular to an upper surface of the interposer  110 , thus providing the first and second stiffeners  150 A and  150 B in the semiconductor package  100 B without an increase of the thickness of the semiconductor package  100 B. 
       FIG.  10    is a cross-sectional view of a module including the semiconductor package of  FIG.  8   . 
     Referring to  FIG.  10   , a semiconductor package module  200 B is similar to or the same as the semiconductor package module  200 A described with reference to  FIG.  7    except that the semiconductor package  100 B shown in  FIG.  8    is provided therein. 
     The semiconductor package module  200 B includes the package substrate  210  and the semiconductor package  100 B shown in  FIG.  8   . The package substrate  210  includes the upper pads  212 , the lower pads  213 , and the redistribution layer connecting the upper pads  212  and the lower pads  213 . The upper pads  212  may be connected to the second pads  113  of the interposer  110  by the outer terminals  115 . 
     The semiconductor package module  200 B includes the heat spreader  170  on an upper surface and a sidewall of the semiconductor package  100 B. Since upper surfaces of the first and second stiffeners  150 A and  150 B and an upper surface of the first semiconductor chip  120 ′ are substantially flush with one another, the heat generated from the first semiconductor chip  120 ′ and the second semiconductor chips  130 A to  130 D may be transmitted to the heat spreader  170  adjacent thereto through the upper surface of the first semiconductor chip  120 ′ and the first and second stiffeners  150 A and  150 B. 
       FIG.  11    is a cross-sectional view of a semiconductor package according to example embodiments. 
     Referring to  FIG.  11   , a semiconductor package  100 C is similar to or the same as the semiconductor package  100  described with reference to  FIGS.  1  and  2   , except that a first semiconductor chip  120 ″ and the second semiconductor chip  130  have different thickness, the first semiconductor chip  120 ″ includes the stepped portion G therein, and a stiffener  150 C includes a redistribution layer  155 . 
     The thickness of the first semiconductor chip  120 ″ in a direction perpendicular to an upper surface of the interposer  110  may be greater than the thickness of the second semiconductor chip  130  in the direction perpendicular to the upper surface of the interposer  110 . The stepped portion G, which is lower than an upper surface of the first semiconductor chip  120 ″, may be formed in a portion of the first semiconductor chip  120 ″ contiguous to the second semiconductor chip  130 . A surface provided by the stepped portion G (e.g., a recessed surface) of the first semiconductor chip  120 ″, may be substantially flush with the upper surface  130 T of the second semiconductor chip  130 . Thus, the stiffener  150 C on the step portion G of the first semiconductor chip  120 ″ and on the second semiconductor chip  130  may be positioned at a flat level. 
     The stiffener  150 C may be a redistribution structure including the redistribution layer (RDL)  155 , but not be a dummy chip. The stiffener  150 C may have a plurality of connection pads  150 P on a lower surface (or a mounting surface) thereof that are connected to the redistribution layer  155 . The redistribution layer  155  may be formed of vias and conductive patterns. The redistribution layer  155  may be formed of one or more layers. 
     The first semiconductor chip  120 ″ includes first lower electrodes  120 P 1  on a lower surface thereof and first upper electrodes  120 P 2  on a portion of the upper surface (e.g., the recessed surface) thereof. The first lower electrodes  120 P 1  may be connected to the first pads  112  of the interposer  110  by first connection terminals  116 . The first upper electrodes  120 P 2  may be provided on the stepped portion G to be connected to the connection pads  150 P of the stiffener  150 C by second connection terminals  156 . The first upper electrodes  120 P 2  may be below the stiffener  150 C. 
     The stiffener  150 C may be fixed to the first and second semiconductor chips  120 ″ and  130  with the second connection terminals  156  without using an adhesive. According to example embodiments, an underfill resin may be provided between the stiffener  150 C and the first and second semiconductor chips  120 ″ and  130 . In some embodiments, the encapsulant  160  may cover sidewalls and at least a portion of a lower surface of the first semiconductor chip  120 ″, sidewalls and at least a portion of a lower surface and at least a portion of an upper surface of the second semiconductor chip  130 , and sidewalls and at least a portion of a lower surface of the stiffener  150 C. 
     The second semiconductor chip  130  includes second lower electrodes  130 P 1  on a lower surface thereof and second upper electrodes  130 P 2  on an upper surface thereof. The second lower electrodes  130 P 1  may be connected to the first pads  112  of the interposer  110  by the first connection terminals  116 . The second upper electrodes  130 P 2  may be connected to the connection pads  150 P of the stiffener  150 C by the second connection terminals  156 . 
     Since the redistribution layer  155  of the stiffener  150 C acts to connect at least some electrodes of the first and second semiconductor chips  120 ″ and  130 , the wiring circuit  114  of the interposer  110  may be simplified. In some embodiments, the wiring circuit  114  of the interposer  110  may be simplified, thus reducing the number of layers of the wiring circuit  114 . Thus, a thickness of the semiconductor package  100 C may be reduced. 
       FIG.  12    is a cross-sectional view of a semiconductor package according to example embodiments. 
     Referring to  FIG.  12   , a semiconductor package  100 D is similar to or the same as the semiconductor package  100  described with reference to  FIGS.  1  and  2   , except that thicknesses Ta and Tb of the first and second semiconductor chips  120  and  130  are different (Ta Tb), and a thickness of a stiffener  150 D is different depending on portions thereof. 
     The thickness Ta of the first semiconductor chip  120  in a direction perpendicular to an upper surface of the interposer  110  may be greater than the thickness Tb of the second semiconductor chip  130  in the direction perpendicular to the upper surface of the interposer  110 . In this exemplary embodiment, a structure of the stiffener  150 D may be modified without forming a stepped portion in the first semiconductor chip  120 , unlike the aforementioned example embodiments of  FIGS.  8  and  11   . 
     The stiffener  150 D has a flat upper surface and includes a first portion  150 Da having a first thickness ta in a direction perpendicular to an upper surface of the interposer  110  and a second portion  150 Db having a second thickness tb in the direction perpendicular to the upper surface of the interposer  110  greater than the first thickness ta. The thinner first portion  150 Da of the stiffener  150  may be disposed on the upper surface  120 T of the first semiconductor chip  120 . The thicker second portion  150 Db of the stiffener  150  may be disposed on the upper surface  130 T of the second semiconductor chip  130 . A difference (tb−ta) between the thicknesses ta and tb of the stiffener  150  may be set to correspond to (e.g., to be substantially equal to or less than) a difference (Ta−Tb) between the thicknesses Ta and Tb of the first and second semiconductor chips  120  and  130 . 
     The stiffener  150 D may have a substantially flat upper surface flush with an upper surface of the encapsulant  160 . The stiffener  150 D may cover substantially the entire upper surface  120 T of the first semiconductor chip  120  and the entire upper surface  130 T of the second semiconductor chip  130 , in cross-sectional view. The stiffener  150 D may cover the space between the first and second semiconductor chips  120  and  130  and extend onto the upper surfaces  120 T and  130 T of the peripheral portions of the first and second semiconductor chips  120  and  130 , adjacent to the edge region of the interposer  110 . 
       FIG.  13    is a cross-sectional view of a semiconductor package according to example embodiments. 
     Referring to  FIG.  13   , a semiconductor package  100 E is similar to or the same as the semiconductor package  100  described with reference to  FIGS.  1  and  2   , except that the thicknesses of the first and second semiconductor chips  120  and  130  are different, a stepped portion G is formed in the first semiconductor chip  120 , and a package substrate  310  is provided instead of the interposer. 
     In the case in which the thicknesses of the first and second semiconductor chips  120  and  130  are different, the stepped portion G is formed in the first semiconductor chip  120  so that the stiffener  150  is disposed thereon, similar to the stiffener  150  shown in  FIG.  8   . 
     According to example embodiments, the first and second semiconductor chips  120  and  130  are connected to the package substrate  310  without the interposer. The first and second semiconductor chips  120  and  130  are mounted on the package substrate  310 . 
     The package substrate  310  includes an insulating member  311  having opposite first and second surfaces  310 A and  310 B, a plurality of first pads  312  and a plurality of second pads  313  that are on the first surface  310 A and the second surface  310 B, respectively, of the insulating member  311 , a redistribution layer  314  in the insulating member  311  to connect the first and second pads  312  and  313 . The insulating member  311  may be a printed circuit board (PCB). For example, the insulating member  311  may include a thermosetting resin, e.g., an epoxy resin, a thermoplastic resin, e.g., a polyimide, or a photosensitive insulating material. 
     In some embodiments, the insulating member  311  may include a prepreg, an ajinomoto build-up film (ABF), FR-4, or a bismaleimide triazine (BT) resin. The redistribution layer  314  and the first and second pads  312  and  313  may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and/or an alloy thereof, but are not limited thereto. Outer terminals  315  may be disposed on the second pads  313 , respectively. The outer terminals  315  may include tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), bismuth (Bi), and/or an alloy thereof. 
     While the present inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.