Patent Publication Number: US-11036659-B2

Title: Memory system for receiving communication information from external device via virtual channels and control method of memory system

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-052380, filed Mar. 20, 2019, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a memory system and a control method of the memory system. 
     BACKGROUND 
     A solid state drive (SSD) includes a nonvolatile memory (NVM) and has an interface complying with predetermined specification. The SSD and an information processing device transmit and receive, for example, commands, user data, completions, and the like in accordance with the predetermined specification. For example, the SSD writes user data received from the information processing device to the NVM, and transmits user data read from the NVM to the information processing device, in accordance with the predetermined specification. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating a configuration example of an information processing system for an embodiment. 
         FIG. 2  is a look-up table illustrating an example of priority relation information of the embodiment. 
         FIG. 3  is a sequence chart illustrating an example of an initialization process in determining the number of virtual channels used between the information processing system and the memory system of the embodiment. 
         FIG. 4  is a sequence chart illustrating an example of NVM read command execution in the embodiment. 
         FIG. 5  is a sequence chart illustrating an example of NVM write command execution in the embodiment. 
         FIG. 6  is a sequence chart illustrating an example of NVM read command execution in the memory system of the embodiment. 
         FIG. 7  is a sequence chart illustrating an example of NVM write command execution in the memory system of the embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     An embodiment will be described hereinafter with reference to the accompanying drawings. In the following description, those relevant items having substantially the same function and configuration will be denoted by the same reference number, and the description will be repeated only when necessary. Further, the following embodiment illustrates a device and a method which give concrete forms to technical ideas, and the technical ideas of the embodiment are not intended to limit materials, shapes, structures, arrangements, etc., of components to those descried below. The technical ideas of the embodiment can be modified in various manners in the scope of patent claims. 
     In general, according to one embodiment, a memory system includes an NVM and a controller. The controller communicates with an external device via virtual channels, and controls the NVM. The virtual channels include a first virtual channel and a second virtual channel. The virtual channels comply with Peripheral Component Interconnect Express Base Specification (hereinafter referred to as PCIe). The controller manages a set of priority relation information in which the first virtual channel is associated with a first priority and the second virtual channel is associated with a second priority. In this context, the second priority has a lower priority than the first priority. The controller receives, from the external device, first communication information corresponding to the first priority or second communication information corresponding to the second priority. In a case where the first communication information is received, the controller requests third communication information associated with the first communication information to the external device via the first virtual channel, based on the priority relation information. In a case where the second communication information is received, the controller requests fourth communication information associated with the second communication information to the external device via the second virtual channel, based on the priority relation information. 
     In the embodiment, the memory system complies with first specification communicates with an external information processing device. The memory system may be incorporated in the information processing device. 
     In addition, the memory system complies with second specification which is different from the first specification to execute a command issued by the information processing device. 
     In the following description, for example, the first specification is PCIe and the second specification is NVM Express Base Specification (hereinafter referred to as NVMe). However, the first specification and the second specification can be changed as appropriate. 
     In the following description, for example, communication information is communicated and processed in compliant with PCIe and NVMe. The communication information is a generic term of, for example, command notification, command request, command, descriptor of data-transfer request, descriptor of data-transfer, data transmitted or received between the controller and the external device per execution of the command, completion, or the like. 
       FIG. 1  is a block diagram illustrating a configuration example of an information processing system  1 A for the embodiment. 
     The information processing system  1 A includes an information processing device  1  and a memory system  2 . 
     The information processing device  1  may be called, for example, a host. The information processing device  1  may be, for example, a personal computer, a server, a client device, a cellular telephone, a mobile information terminal, an imaging device, a sensor device, or the like. 
     In the embodiment, the memory system  2  is explained by an example of an SSD, but the same configuration and functions can be applied to any nonvolatile storage devices such as a hard disk drive (HDD), a memory card, a hybrid memory system including an HDD and an SSD, an optical disk device, and the like. 
     First, a configuration of the information processing device  1  will be described. 
     The information processing device  1  includes a memory  3 , a Chipset  4 B, and a processor  4 . The configuration and operation of the information processing device  1  described in the embodiment are mere examples and are not limited to these. 
     The memory  3  stores software SW, a physical region pointer (PRP)  5 , user data  3 W to be written to the memory system  2 , and user data  3 R read from the memory system  2 . A PRP is defined under, for example, NVMe and is indicative of, for example, descriptor of data-transfer. 
     The Chipset  4 B executes communication between the information processing device  1  and the memory system  2  in accordance with an instruction of the processor  4 . 
     The processor  4  functions as a communication control unit  4 A by executing the software SW stored in the memory  3 . The software SW may be, for example, an operating system, an application program, a driver or the like. The processor  4  may be formed by an electronic circuit. 
     The communication control unit  4 A transmits instructions to the Chipset  4 B and controls the communication between the information processing device  1  and the memory system  2  by using the Chipset  4 B. To simplify the following description, the description of the Chipset  4 B will be omitted. 
     In a communication initialization phase between the information processing device  1  and the memory system  2 , the former will probe the capabilities of the latter (hereinafter simply called virtual channel capability registers information), and receive the virtual channel capability registers information from the latter. 
     The communication control unit  4 A determines the number of virtual channels that can be used in the communication between the information processing device  1  and the memory system  2 , based on the received virtual channel capability registers information in the PCIe controller  11 . The virtual channels and the virtual channel capability registers are defined under, for example, PCIe. 
     In the embodiment, it is assumed that the number of usable virtual channels is five and that virtual channels VC 0  to VC 4  can be used for the communication between the information processing device  1  and the memory system  2 . In another embodiment, the number of virtual channels may be two or more. More specifically, the number of virtual channels may be two or more and smaller than or equal to the number of the maximum virtual channels defined in PCIe. 
     The communication control unit  4 A transmits a command notification to the memory system  2 . The command notification is defined under, for example, NVMe. 
     The communication control unit  4 A receives a command request corresponding to the command notification from the memory system  2 , via a virtual channel determined by the memory system  2 . 
     The communication control unit  4 A transmits a command corresponding to the command request to the memory system  2 , via the same virtual channel determined by the memory system  2 . 
     The communication control unit  4 A receives a PRP request from the memory system  2 , via the virtual channel determined by the memory system  2 . 
     The communication control unit  4 A reads the PRP  5  corresponding to the PRP request from the memory  3  and transmits the PRP  5  to the memory system  2 , via the virtual channel determined by the memory system  2 . 
     If the command transmitted to the memory system  2  is a read command, the communication control unit  4 A will receive the corresponding user data  3 R from the memory system  2  via the virtual channel determined by the memory system  2 . The communication control unit  4 A stores the user data  3 R at a location indicated by PRP  5  in the memory  3 . After receiving the user data  3 R, the communication control unit  4 A receives a completion from the memory system  2 , via the virtual channel determined by the memory system  2 . 
     If the command transmitted to the memory system  2  is a write command, the communication control unit  4 A receives user data request from the memory system  2 , via the virtual channel determined by the memory system  2 . The communication control unit  4 A reads the user data  3 W corresponding to the user data request from the memory  3  and transmits the user data  3 W to the memory system  2 , via the virtual channel determined by the memory system  2 . After transmitting the user data  3 W, the communication control unit  4 A receives a completion from the memory system  2 , via the virtual channel determined by the memory system  2 . 
     The communication control unit  4 A may be implemented in another block of the information processing device  1 , instead of the processor  4 . The processor  4  and the Chipset  4 B may be combined. For example, the processor  4  and the Chipset  4 B may be formed as one chip or one package. The processor  4 , the Chipset  4 B, and the memory  3  may be formed as one chip or one package. 
     Next, a configuration of the memory system  2  will be described. The configuration and operation of the memory system  2  described in the embodiment are mere examples and are not limited to these. 
     The memory system  2  includes a controller  7 , a memory  8 , and a nonvolatile memory  10 . For the memory  8 , for example, a dynamic random access memory (DRAM) may be used. 
     In the embodiment, the controller  7  may be formed by an electronic circuit such as system-on-a-chip (SoC). Some functions of the controller  7  may be realized by dedicated hardware or may be realized by executing software such as firmware by the processor. The controller  7  and the memory  8  may be combined. For example, the controller  7  and the memory  8  may be formed as one chip or one package. The controller  7 , the memory  8 , and the nonvolatile memory  10  may be formed as one chip or one package. 
     The controller  7  may be connected with the information processing device  1  via physical communication lines  1 B. The controller  7  includes a front end block  7 F, a back end block  7 B, and a read/write controller  9 . The controller  7  receives a command from the information processing device  1  and controls the nonvolatile memory  10  in accordance with the command. For example, when the controller  7  receives a read command from the information processing device  1 , the controller executes a read operation on the nonvolatile memory  10 . When the controller  7  receives a write command from the information processing device  1 , the controller  7  executes a write operation on the nonvolatile memory  10 . 
     The front end block  7 F includes the PCIe controller  11  that operates per PCIe, and the NVMe controller  12  that operates per NVMe. 
     The PCIe controller  11  has buffer memories  110  to  114 , which correspond to virtual channels VC 0  to VC 4  respectively, to store communication information exchanged between the information processing device  1  and the memory system  2 . Temporary storage devices of other type such as queues may be used instead of the buffer memories  110  to  114 . 
     That is, the PCIe controller  11  stores the communication information, which is received from the information processing device  1  via the virtual channels VC 0  to VC 4 , in the buffer memories  110  to  114 , respectively. Similarly, the PCIe controller  11  stores the communication information, which is received from queue circuits  130  to  134 , in the buffer memories  110  to  114 , respectively. 
     The PCIe controller  11  transmits communication information stored in the buffer memories  110  to  114  to the information processing device  1 , via the virtual channels VC 0  to VC 4 , respectively. 
     The PCIe controller  11  shares information about usable virtual channels VC 0  to VC 4  to the NVMe controller  12 . The NVMe controller  12  creates priority relation information  6  by associating the usable virtual channels VC 0  to VC 4  with NVMe priority information, and stores the priority relation information  6  in the memory  8 . In a different implement, a different block in the memory system  2  may create and store the priority relation information  6  in the memory  8 . 
     In an operation phase, the PCIe controller  11  receives a command notification from the information processing device  1 . The PCIe controller  11  transmits the received command notification to the NVMe controller  12 . The NVMe controller  12  reads the priority relation information  6  from the memory  8 , and determines which virtual channel to be used for transmitting the command request, based on the submission queue (SQ) priority of the received command notification. The PCIe controller  11  stores the command request in the buffer memory corresponding to the determined virtual channel, and then transmits the command request to the information processing device  1  via the determined virtual channel. 
     The NVMe controller  12  includes an arbitration unit  13  and direct memory access (DMA) circuits  140  to  144 . The arbitration unit  13  implements Weighted Round Robin with Urgent Priority Class Arbitration (WRRUPCA) defined in NVMe. The NVMe controller  12  processes selected communication information stored in the queue circuits  130  to  134  by WRRUPCA algorithm. Note that each of the queue circuits  130  to  134  is assumed to contain, for example, a class of SQ. 
     The subsequent NVM command processing in the NVMe controller  12  includes four steps: “command fetch and interpretation”, “PRP fetch and interpretation”, “data transfer”, and “completion transmission”. 
     In the embodiment, an algorithm such as WRRUPCA described above is assumed to be used for arbitration. However, other arbitration algorithms that assign different priorities to SQ may be used instead of WRRUPCA. 
     The queue circuits  130  to  134  are mapped to the virtual channels VC 0  to VC 4 , respectively. The queue circuits  130  to  134  may adopt a first-in first-out method. 
     The NVMe controller  12  executes the subsequent NVM command processing based on the selected communication information by the arbitration unit  13 . 
     The DMA circuits  140  to  144  are mapped to the virtual channels VC 0  to VC 4 , respectively. 
     The back end block  7 B includes a processor  15 . The processor  15  includes a memory  16 . The memory  16  is divided into areas  160  to  164 , which are mapped to the virtual channels VC 0  to VC 4 , respectively. The memory  16  may also be implemented outside of the processor  15 . In such a case, the processor  15  will write to and read from the external memory  16 . 
     The processor  15  transfers data stored in each of the areas  160  to  164  to the nonvolatile memory  10  via the read/write controller  9 . Similarly, the processor  15  transfers data stored in the nonvolatile memory  10  to each of the areas  160  to  164 , via the read/write controller  9 . In both cases, the processor  15  may use a different algorithm to select which area in Memory  16  should be serviced. 
     The nonvolatile memory  10  is, for example, a NAND flash memory but may be other nonvolatile semiconductor memories such as magnetoresistive random access memory (MRAM), phase change random access memory (PRAM), resistive random access memory (ReRAM), or ferroelectric random access memory (FeRAM). For example, the nonvolatile memory  10  may be a magnetic memory, a semiconductor memory of a three-dimensional structure, or the like. 
     The nonvolatile memory  10  is logically divided into areas  100  to  104 , which are mapped to the virtual channels VC 0  to VC 4 , respectively. 
     In moving data from the queue circuits  130  to  134  to the nonvolatile memory  10 , each of the DMA circuits  140  to  144  transfers selected data from the corresponding queue circuits  130  to  134 , to the respective areas  160  to  164  in the memory  16 , based on the arbitration algorithm in the arbitration unit  13 . The processor  15  transmits the user data read from the areas  160  to  164  of the memory  16  to the read/write controller  9 . The read/write controller  9  then writes the corresponding data to the areas  100  to  104  of the nonvolatile memory  10 , respectively. 
     In moving data from the nonvolatile memory  10  to the buffer memories  110  to  114  of the PCIe controller  11 , the read/write controller  9  reads data from the areas  100  to  104  of the nonvolatile memory  10 , and transmits the data to the processor  15 . The processor  15  then stores the received user data to the areas  160  to  164  of the memory  16 , respectively. The DMA circuits  140  to  144  transfer the user data from the areas  160  to  164  in the memory  16  to the buffer memories  110  to  114  of the PCIe controller  11 , respectively. 
       FIG. 2  is a look-up table illustrating an example of the priority relation information  6 . 
     The priority relation information  6  includes NVMe priority information  61  and PCIe priority information  62 . In  FIG. 2 , the priority relation information  6  maps the virtual channels VC 0  to VC 4  of PCIe to priorities defined in NVMe. 
     The NVMe priority information  61  includes priorities used for WRRUPCA, for example, of which are Low priority, Medium priority, High priority, Urgent priority and Admin. The priority order in this case is, for example, Low priority&lt;Medium priority&lt;High priority&lt;Urgent priority&lt;Admin. 
     The PCIe priority information  62  complies with the priorities of the respective virtual channels VC 0  to VC 4  defined in PCIe. In  FIG. 2 , the priority order is, for example, VC 0  priority&lt;VC 1  priority&lt;VC 2  priority&lt;VC 3  priority&lt;VC 4  priority. 
     The priority relation information  6  maps Low priority to VC 0 , Medium priority to VC 1 , High priority to VC 2 , Urgent priority to VC 3 , and Admin to VC 4 . 
     In the controller  7 , communication information having a higher priority is transmitted, received and processed more preferentially than communication information having a lower priority. QoS (Quality of Service) for communication information with a higher NVMe priority can thus be improved. 
     The priority relation information  6  of  FIG. 2  is a mere example and can be changed as appropriate. For example, multiple virtual channels may be mapped to one item in the NVMe priority information  61 . Similarly, multiple items of the NVMe priority information  61  may be mapped to one virtual channel. 
     The PCIe controller  11  preferentially schedules and processes communication information based on the PCIe priority information  62 . 
     The NVMe controller  12  preferentially schedules and processes communication information based on the NVMe priority information  61 . 
       FIG. 3  is a sequence chart illustrating an example of the initialization process in determining the number of virtual channels used between the information processing system  1 A and the memory system  2  of the embodiment. 
     Specifically, the information processing device  1  transmits a request for virtual channel capability registers information to the memory system  2  in step S 301 . The virtual channel capability registers information includes, for example, the number of supported virtual channels in the memory system  2 . 
     In step S 302 , the PCIe controller  11  of the memory system  2  transmits the virtual channel capability registers information to the information processing device  1 . 
     In step S 303 , the information processing device  1  determines the number (five in the embodiment) of virtual channels that can be used between the information processing device  1  and the memory system  2 , based on the virtual channel capability registers information received from the memory system  2 . 
       FIG. 4  is a sequence chart illustrating an example of NVM read command execution in the embodiment. 
     In step S 401 , the communication control unit  4 A of the information processing device  1  transmits a NVM command notification, to the memory system  2 , via one of the virtual channels VC 0  to VC 4 . 
     In step S 402 , the NVMe controller  12  determines which priority is associated with a command, based on how the NVM command notification being sent to the controller. The NVMe controller  12  acts on the command notification priority, and determines which virtual channel to be used for a command request, based on the priority relation information  6 . The NVMe controller  12  then shares the determined virtual channel information with the PCIe controller  11 . 
     In this example, the virtual channel VC 0  is determined as the virtual channel to be used. The same operation applies when the virtual channels VC 1  to VC 4  are determined to be used by the memory system  2 . 
     In step S 403 , the PCIe controller  11  transmits a command request corresponding to the command notification to the information processing device  1 , via the virtual channel VC 0  determined in step S 402 . 
     Upon receiving the command request from the memory system  2 , the communication control unit  4 A transmits the command corresponding to the command request to the former in step  404 , via the same virtual channel of the command request, per PCIe protocol. 
     In step S 405 , the PCIe controller  11  stores the received command in the buffer memory  110  corresponding to the virtual channel VC 0 . The PCIe controller  11  then transfers the command stored in the buffer memory  110  to the queue circuit  130 , of which corresponds to the virtual channel VC 0 . The description from steps S 403  to S 405  corresponds to, for example, command fetch of the NVMe controller  12 . 
     In step S 406 , the NVMe controller  12  processes the command stored in the queue circuit  130 , of which is selected per the arbitration algorithm in the arbitration unit  13 . 
     In step S 407 , the NVMe controller  12  transmits the PRP request to the information processing device  1 , through the PCIe controller  11 . The used virtual channel for this transmission is VC 0 , which was determined in step S 402 . 
     Upon receiving the PRP request from the memory system  2 , the communication control unit  4 A transmits the corresponding PRP  5  to the former in step S 408 , via the same virtual channel of the PRP request, per PCIe protocol. 
     In step S 409 , the PCIe controller  11  stores the received PRP  5  in the buffer memory  110  corresponding to the virtual channel VC 0 . The PCIe controller  11  then transfers the PRP  5  to the queue circuit  130 . The description from steps S 407  to S 409  corresponds to, for example, PRP fetch of the NVMe controller  12 . 
     The NVMe controller  12  stores the PRP  5  stored in the buffer memory  110  into the queue circuit  130  corresponding to the virtual channel VC 0  determined in step S 402 . 
     In step S 410 , the NVMe controller  12  interprets the PRP stored in the queue circuit  130 , of which is selected per the arbitration algorithm in the arbitration unit  13 . 
     In step S 411 , the controller  7  reads the requested user data  3 R from the nonvolatile memory  10 , and stores the user data  3 R in the buffer memory  110 . 
     In step S 412 , the PCIe controller  11  transmits the user data  3 R stored in the buffer memory  110  to the information processing device  1 , via the virtual channel VC 0  determined in step S 402 . 
     In step S 413 , the NVMe controller  12  stores completion in the buffer memory  110 . The PCIe controller  11  transmits the completion to the information processing device  1 , via the virtual channel VC 0  determined in step S 402 . Step S 413  corresponds to, for example, the completion transmission of the NVMe controller  12 . 
       FIG. 5  is a sequence chart illustrating an example of NVM write command execution in the embodiment. 
     The descriptions for step S 501  to step  510  will be omitted since the concept is basically same as those in S 401  to step S 410  of  FIG. 4 . 
     In step S 511 , the PCIe controller  11  transmits a write data request to the information processing device  1 , via the virtual channel VC 0  determined in step S 502 . 
     Upon receiving the write data request, the communication control unit  4 A reads the corresponding user data  3 W from the memory  3 , and transmits the user data  3 W to the memory system  2  in step S 512 . 
     In step S 513 , the PCIe controller  11  stores the received user data  3 W in the buffer memory  110 , and then transfers it to the queue circuit  130 . 
     In step S 514 , the NVMe controller  12  transfers the user data  3 W stored in the queue circuit  130  to the nonvolatile memory  10  via the back end block  7 B and the read/write controller  9 . The user data  3 W of the queue circuit  130  is selected based on the arbitration algorithm of the arbitration unit  13 . 
     In step S 515 , the NVMe controller  12  stores completion in the buffer memory  110 . The PCIe controller  11  transmits the completion to the information processing device  1 , via the virtual channel VC 0  determined in step S 502 . 
       FIG. 6  is a sequence chart illustrating an example of NVM Read command execution in the memory system  2  of the embodiment.  FIG. 6  corresponds to step S 411  of  FIG. 4 . In  FIG. 6 , the read/write controller  9  and the nonvolatile memory  10  are illustrated as one block  9 - 10  to simplify the description. The description of  FIG. 6  focuses on the items that are associated with the virtual channel VC 0 . The corresponding descriptions for the virtual channels VC 1  to VC 4  are omitted, as the concept is the same. 
     In step S 601 , the NVMe controller  12  passes the relevant information to the back end block  7 B, and instructs the back end block  7 B to execute a read command. 
     In step S 602 , the back end block  7 B instructs the read/write controller  9  to execute the read command, per the NVMe controller  12  instruction. 
     In step S 603 , the read/write controller  9  reads the user data  3 R from the area  100  of the nonvolatile memory  10 , which is associated with the determined virtual channel VC 0 . 
     In step S 604 , the read/write controller  9  transmits the user data  3 R to the back end block  7 B. 
     In step S 605 , the back end block  7 B stores the user data  3 R in the area  160 , which is associated with the determined virtual channel VC 0 . 
     In step S 606 , the DMA circuit  140  of the NVMe controller  12  reads out the user data  3 R stored in the area  160 . 
     In step S 607 , the DMA circuit  140  stores the user data  3 R in the buffer memory  110 , of which is associated with the determined virtual channel VC 0 . 
       FIG. 7  is a sequence chart illustrating an example of NVM write command execution in the memory system  2  of the embodiment.  FIG. 7  corresponds to step S 514  of  FIG. 5 . In  FIG. 7 , the read/write controller  9  and the nonvolatile memory  10  are illustrated as one block  9 - 10  to simplify the description. The description of  FIG. 7  focuses on the items that are associated with the virtual channel VC 0 . The corresponding descriptions for the virtual channels VC 1  to VC 4  are omitted, as the concept is the same. 
     In step S 701 , the NVMe controller  12  instructs the back end block  7 B to execute an NVM write command. The DMA circuit  140  transfers the user data  3 W from the queue circuit  130  to the area  160 . Both the queue circuit  130  and the area  160  are associated with virtual channel VC 0 . 
     In step S 702 , the back end block  7 B transfers the user data  3 W to the read/write controller  9 . 
     In step S 703 , the read/write controller  9  writes the user data  3 W to the area  100  of the nonvolatile memory  10 , which is associated with the virtual channel VC 0 . 
     In step S 704 , the read/write controller  9  transmits a write completion notification to the back end block  7 B. 
     In step S 705 , the back end block  7 B transmits the write completion notification to the NVMe controller  12 . 
     The benefits of using the information processing system  1 A according to the above-described embodiment are described next. 
     In the present embodiment, the memory system  2  manages the priority relation information  6  in which the NVMe priority information  61  is associated with the PCIe priority information  62 . In the embodiment, communication information that is set to have a higher priority in NVMe is transmitted and received using a virtual channel having a higher priority, and vice-versa, between the information processing device  1  and the memory system  2 . 
     Thus, the controller  7  according to the embodiment can execute a communication transaction with different priority, while complying with PCIe (for example, determination of a virtual channel to be used) and NVMe. 
     In the embodiment, communication information with different priorities in NVMe can be transmitted and received via different virtual channels VC 0  to VC 4 . Furthermore, NVM command processing is executed in association with the virtual channels VC 0  to VC 4 , from a begin stage where the memory system  2  receives a command notification from the information processing device  1 , to an end stage where the memory system  2  transmits a completion to the information processing device  1 . QoS of the whole transaction between the information processing device  1  and the memory system  2  can thus be improved. 
     In the embodiment, the processor  15  of the back end block  7 B separately uses the areas  160  to  164  of the memory  16  in accordance with the priorities of the virtual channels VC 0  to VC 4 . The areas  100  to  104  of the nonvolatile memory  10  are also managed based on the same priorities scheme. So, read and write operations to the nonvolatile memory  10  can be executed with different priorities, to further improve the QoS. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.