Patent Publication Number: US-7713822-B2

Title: Method of forming high density trench FET with integrated Schottky diode

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
   This application is a continuation of U.S. application Ser. No. 11/388,790, filed Mar. 24, 2006, which disclosure is incorporated herein by reference in its entirety for all purposes. 

   BACKGROUND OF THE INVENTION 
   The present invention relates in general to semiconductor power device technology, and in particular to structures and methods for forming a monolithically integrated trench gate field effect transistor (FET) and Schottky diode. 
   In today&#39;s electronic devices it is common to find the use of multiple power supply ranges. For example, in some applications, central processing units are designed to operate with a different supply voltage at a particular time depending on the computing load. Consequently, dc/dc converters have proliferated in electronics to satisfy the wide ranging power supply needs of the circuitry. Common dc/dc converters utilize high efficiency switches typically implemented by power MOSFETs. The power switch is controlled to deliver regulated quanta of energy to the load using, for example, a pulse width modulated (PWM) methodology. 
     FIG. 1  shows a circuit schematic for a conventional dc/dc converter. A PWM controller  100  drives the gate terminals of a pair of power MOSFETs Q 1  and Q 2  to regulate the delivery of charge to the load. MOSFET switch Q 2  is used in the circuit as a synchronous rectifier. In order to avoid shoot-through current, both switches must be off simultaneously before one of them is turned on. During this “dead time,” the internal diode of each MOSFET switch, commonly referred to as body diode, can conduct current. Unfortunately the body diode has relatively high forward voltage and energy is wasted. To improve the conversion efficiency of the circuit, a Schottky diode  102  is often externally added in parallel with the MOSFET (Q 2 ) body diode. Because a Schottky diode has lower forward voltage than the body diode, Schottky diode  102  effectively replaces the MOSFET body diode. The lower forward voltage of the Schottky diode results in improved power consumption. 
   For many years, the Schottky diode was implemented external to the MOSFET switch package. More recently, some manufacturers have introduced products in which discrete Schottky diodes are co-packaged with discrete power MOSFET devices. There have also been monolithic implementations of power MOSFETs with Schottky diode. An example of a conventional monolithically integrated trench MOSFET and Schottky diode is shown in  FIG. 2 . A Schottky diode  210  is formed between two trenches  200 - 3  and  200 - 4  surrounded by trench MOSFET cells on either side. N-type substrate  202  forms the cathode terminal of Schottky diode  210  as well as the drain terminal of the trench MOSFET. Conductive layer  218  provides the diode anode terminal and also serves as the source interconnect layer for MOSFET cells. The gate electrode in trenches  200 - 1 ,  200 - 2 ,  200 - 3 ,  200 - 4  and  200 - 5  are connected together in a third dimension and are therefore similarly driven. The trench MOSFET cells further include body regions  208  with source region  212  and heavy body regions  214  therein. 
   The Schottky diodes in  FIG. 2  are interspersed between trench MOSFET cells. As a result, the Schottky diodes consume a significant portion of the active area, resulting in lower current ratings or a large die size. There is therefore a need for a monolithically and densely integrated Schottky diode and trench gate FET with superior performance characteristics. 
   BRIEF SUMMARY OF THE INVENTION 
   In accordance with another embodiment of the invention, a method of forming a monolithically integrated trench FET and Schottky diode includes the following steps. Two trenches are formed extending through an upper silicon layer and terminating within a lower silicon layer. The upper and lower silicon layers have a first conductivity type. First and second silicon regions of a second conductivity type are formed in the upper silicon layer between the pair of trenches. A third silicon region of the first conductivity type is formed extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer. A silicon etch is performed to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions forming source regions. An interconnect layer is formed filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer. The interconnect layer electrically contacts the second silicon region so as to form a Schottky contact therebetween. 
   In one embodiment, the lower silicon layer has a higher doping concentration that the upper silicon layer. 
   In another embodiment, the electrical contact between the interconnect layer and the portion of the upper silicon layer is made at a depth below the source regions. 
   In another embodiment, each of the first and second regions has a substantially uniform doping concentration. 
   In another embodiment, a heavy body region of the second conductivity type is formed between the pair of trenches. The heavy body region extends into the two body regions and into the portion of the upper silicon layer. 
   In yet another embodiment, the two body regions, the source regions, and the heavy body region are self-aligned to the pair of trenches. 
   A further understanding of the nature and the advantages of the invention disclosed herein may be realized by reference to the remaining portions of the specification and the attached drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a circuit schematic for a conventional dc/dc converter using power MOSFETs with a Schottky diode; 
       FIG. 2  shows a cross-sectional view of a conventional monolithically integrated trench MOSFET and Schottky diode; 
       FIG. 3  is an exemplary simplified isometric view of a portion of an array of stripe-shaped cells each having a trench MOSFET and a Schottky diode integrated therein, in accordance with an embodiment of the invention; 
       FIG. 4  shows a cross-section view along heavy body regions  326  in  FIG. 3 ; 
       FIG. 5  is a simplified cross section view showing an alternate implementation of the heavy body region to that shown in  FIGS. 3 and 4 , in accordance with an embodiment of the invention; 
       FIGS. 6A-6F  are simplified cross section views illustrating an exemplary process sequence for forming the monolithically integrated trench MOSFET and Schottky diode shown in  FIG. 3 , according to an embodiment of the present invention; and 
       FIGS. 7A-7C  show simulated avalanche current flow lines for three different dimple depths in a monolithically integrated trench MOSFET and Schottky diode structure. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   In accordance with embodiments of the invention, a Schottky diode is optimally integrated with a trench MOSFET in a single cell repeated many times in an array of such cells. Minimal to no active area is sacrificed in integrating the Schottky diode, yet the total Schottky diode area is large enough to handle 100% of the diode forward conduction. The MOSFET body diode thus never turns on, eliminating reverse recovery losses. Further, because of Schottky diode&#39;s lower forward voltage drop compared to that of the MOSFET body diode, power losses are reduced. 
   Moreover, the Schottky diode is integrated with the MOSFET such that the Schottky contact is formed below the MOSFET source regions. This advantageously diverts the avalanche current away from the source regions toward the Schottky regions, preventing the parasitic bipolar transistor from turning on. The device ruggedness is thus improved. This feature of the invention also eliminates, for the most part, the need for heavy body regions typically required in each MOSFET cell of prior art structures to prevent the parasitic bipolar transistor from turning on. Instead, islands of heavy body regions are incorporated intermittently and far apart from one another merely to ensure good source metal to body region contact. In essence, the heavy body regions required in prior art trench MOSFETs are, for the most part, replaced with Schottky diode. Accordingly, no additional silicon area is allocated to the Schottky diode. 
     FIG. 3  is an exemplary simplified isometric view of a portion of an array of stripe-shaped cells each having a trench MOSFET and a Schottky diode integrated therein, in accordance with an embodiment of the invention. A highly doped N-type (N+) region  302  overlies an N-type silicon substrate (not shown) which has an even higher doping concentration (N++) than N+ region  302 . A plurality of trenches  304  extend to a predetermined depth within N+ region  302 . A shield electrode  305  and an overlying gate electrode  308  are embedded in each trench  304 . In one embodiment, shield electrodes  305  and gate electrodes  308  comprise polysilicon. An inter-electrode dielectric  310  insulates the gate and shield electrodes from one another. Shield dielectric layer  312  lines lower sidewalls and bottom of each trench  304 , and insulates shield electrodes  305  from surrounding N+ region  302 . A gate dielectric  316 , which is thinner than shield dielectric  312 , lines the upper sidewalls of trenches  304 . A dielectric cap  314  extends over each gate electrode  308 . In one embodiment, shield electrodes  305  are electrically connected to source regions along a third dimension, and thus are biased to the same potential as the source regions during operation. In other embodiments, shield electrodes  305  are electrically tied to gate electrodes  308  along a third dimension, or are allowed to float. 
   Two P-type body regions  318  separated by a lightly doped N-type (N−) region  320  are located between every two adjacent trenches  304 . Each body region  318  extends along one trench sidewall. In the various embodiments shown in the figures and described herein, body regions  318  and N− region  320  have substantially the same depth, however body regions  318  may be slightly shallower or deeper than N− region  320  and vice versa without any significant impact on the device operation. A highly doped N-type source region  322  is located directly above each body region  318 . Source regions  322  vertically overlap gate electrode  308 , and possess a rounded outer profile due to the presence of dimples  324  forming contact openings. Each dimple  324  extends below corresponding source regions  322  between every two adjacent trenches. As shown, source regions  322  and body regions  318  together form the rounded sidewalls of dimples  324 , and N− regions  320  extend along the bottom of dimples  324 . In one embodiment, N+ region  302  is an N+ epitaxial layer, and N− regions  320  are portions of an N− epitaxial layer in which body regions  318  and source regions  322  are formed. When MOSFET  300  is turned on, a vertical channel is formed in each body region  318  between each source region  322  and the highly doped region  302  along trench sidewalls. 
   A Schottky barrier metal  330 , which is peeled back in  FIG. 3  to expose the underlying regions, fills dimples  324  and extends over dielectric caps  314 . Schottky barrier metal  330  electrically contacts N− regions  320  along the bottom of dimples  324 , thus forming a Schottky contact. Schottky barrier metal  330  also serves as the top-side source interconnect, electrically contacting source regions  322  and heavy body regions  326 . 
   During reverse bias, the depletion regions formed at each body/N− junction advantageously merge in N− region  320  thus fully depleting N− region  320  beneath the Schottky contact. This eliminates the Schottky leakage current which in turn allows the use of barrier metals with lower work functions. An even lower forward voltage is thus obtained for the Schottky diode. 
   Islands of heavy body regions  326  are formed intermittently along the cell stripes, as shown. Heavy body regions  326  extend through N− regions  320 . This is more clearly shown in  FIG. 4  which is a cross-section view through heavy body regions  326  of the structure in  FIG. 3 . The cross section view in  FIG. 4  is, for the most part, similar to the cross section view along the face of the isometric view in  FIG. 3  except that in  FIG. 4  the two source regions between every two adjacent trenches are replaced with one contiguous heavy body region  326  extending through N− regions  320 . Heavy body regions  326  provide ohmic contact between source metal  330  and body regions  318 . Because heavy body regions  326  extend through N− regions  320 , no Schottky diode is formed in these regions. No MOSFET current flows in these regions either, because of the absence of source regions. 
     FIG. 5  is a simplified cross section view showing an alternate implementation of the heavy body region to that in  FIGS. 3 and 4 , in accordance with another embodiment of the invention. In  FIG. 5 , heavy body regions  526  extend only along a bottom portion of each dimple  524  such that source regions  522  are kept intact. Thus, MOSFET current does flow in these regions, but heavy body regions  526  prevent Schottky barrier metal  530  from contacting N− regions  310  and thus no Schottky diode is formed in these regions. 
   Referring back to  FIG. 3 , the intermittent placing of heavy body regions  326  differs from conventional implementations where heavy body regions extend along the entire length of the cell stripes between two adjacent source regions as in the prior art  FIG. 2  structure. Continuous heavy body regions are not needed in the  FIG. 3  structure because of the manner in which the Schottky diode is integrated with the trench MOSFET. As can be seen in  FIG. 3 , by extending dimples  324  well below source regions  322 , the Schottky contacts are similarly formed well below source regions  322 . As described more fully in connection with  FIGS. 7A-7C  further below, with the Schottky contacts positioned well below source regions  322 , the avalanche current is diverted away from source regions  322  toward the Schottky regions, thus preventing the parasitic bipolar transistor from turning on. This eliminates the need for continuous heavy body regions along the cell stripes typically required in prior art structures. Instead, islands of heavy body regions  326  are incorporated intermittently and far apart from one other along the cell stripes to ensure good source metal  330  to body region  318  contact. With the continuous heavy body regions replaced, for the most part, with Schottky regions, no additional silicon area needs to be allocated to the Schottky diode. Thus no silicon area is sacrificed in integrating the Schottky diode. 
   In some embodiments, the placement frequency of heavy body regions  326  along the stripes is dictated by the device switching requirements. For faster switching devices, heavy body regions are placed more frequently along the stripes. For these devices, additional silicon area may need to be allocated to Schottky diode (e.g., by increasing the cell pitch). For slower switching devices, fewer heavy body regions are required along the stripes. For these devices, placing a heavy body region at each end of a stripe may suffice, thus maximizing the Schottky diode area. 
     FIGS. 6A-6F  are simplified cross section views illustrating an exemplary process sequence for forming the integrated MOSFET-Schottky structure in  FIG. 3 , according to an embodiment of the present invention. In  FIG. 6A , two epitaxial layers  602  and  620  overlying a silicon substrate (not shown) are formed using conventional techniques. Epitaxial layer  620  which is a lightly doped N-type layer (N−) extends over epitaxial layer  620  which is a highly doped N-type layer (N+). A hard mask (e.g., comprising oxide) is formed, patterned and etched to form hard mask islands  601  over N− epi  620 . Surface areas of the N− epi  620  are thus exposed through openings  606  defined by hard mask islands  601 . In one embodiment, openings  606 , which define the trench width, are about 0.3 μm each, and the width of each hard mask island  601  is in the range of 0.4-0.8 μm. These dimensions define the cell pitch within which the MOSFET and Schottky diode are formed. Factors impacting these dimensions include the capabilities of the photolithographic equipment and the design and performance goals. 
   In  FIG. 6B , trenches  603  terminating within N− epi  620  are formed by etching silicon through openings  606  using conventional silicon etch techniques. In one embodiment, trenches  603  have a depth of about 1 μm. A conventional selective epitaxial growth (SEG) process is then used to grow highly doped P-type (P+) silicon regions  618 A within each trench  603 . In one embodiment, P+ silicon region  618 A has a doping concentration of about 5×10 17  cm −3 . In another embodiment, prior to forming P+ regions  618 , a thin layer of high-quality silicon lining the sidewalls and bottom of trenches  608  is formed. The thin silicon layer serves as an undamaged silicon surface suitable for growth of the P+ silicon. 
   In  FIG. 6C , a diffusion process is performed to diffuse the p-type dopants into P+ region  618 A into N− epi  620 . Out-diffused P+ regions  618 B extending laterally under hard mask islands  601  and downward into N− epi  620  are thus formed. Multiple thermal cycles may be carried out to achieve the desired out-diffusion. The dotted lines in  FIG. 6C  show the outline of trenches  603 . This diffusion process, as well as other thermal cycles in the process, causes N+ epi  602  to diffuse upward. These upward diffusions of N+epi  602  need to be accounted for in selecting the thickness of N− epi  620 . 
   In  FIG. 6D , using hard mask islands  601 , a deep trench etch process is performed to form trenches  604  extending through P+ regions  618 B and N− epi  620 , terminating in N+epi  602 . In one embodiment, trenches  604  have a depth of about 2 μm. The trench etch process cuts through and removes a central portion of each P+ silicon region  618 B, leaving vertically outer P+ strips  618 C extending along trench sidewalls. 
   In another embodiment of the invention, P+ strips  618 C are formed using a two-pass angled implant instead of the SEG technique depicted by  FIGS. 6B-6D , as described next. In  FIG. 6B , after forming trenches  603  through mask openings  606 , P-type dopants such as boron are implanted into opposing trench sidewalls using conventional two-pass angled implant techniques. Hard mask islands  604  serve as blocking structures during the implantation process to prevent the implant ions from entering the mesa regions and to confine the location of the implanted ions to the desired regions in N− epi  620 . To arrive at the structure shown in  FIG. 6D , after the two pass angled implant, a second trench etch is carried out to extend the depth of trenches  603  into N+epi  602 . In an alternate variation, only one trench etch (rather than two) is performed as follows. In  FIG. 6B , using hard mask islands  601 , a trench etch is carried out to form trenches extending into N+ epi  602  to about the same depth as trenches  604  in  FIG. 6D . A two-pass angled implant is then carried out to implant P-type dopants into opposing trench sidewalls. The implant angle and the thickness of hard mask islands  601  are adjusted to define upper trench sidewall regions that are to receive the implant ions. 
   In  FIG. 6E , a shielded gate structure is formed in trenches  604  using known techniques. A shield dielectric  612  lining lower sidewalls and bottom of trenches  604  is formed. Shield electrodes  605  are then formed filling a lower portion of trenches  604 . An inter-electrode dielectric layer  610  is then formed over shield electrode  605 . A gate dielectric  616  lining upper trench sidewalls is then formed. In one embodiment, gate dielectric  616  is formed in an earlier stage of the process. Recessed gate electrodes  608  are formed filling an upper portion of trenches  604 . Dielectric cap regions  614  extend over gate electrodes  608  and fill the remainder of trenches  604 . 
   Next, N-type dopants are implanted into all exposed silicon regions followed by a drive in process, thereby forming N+ regions  622 A. No mask is used in the active region in forming N+ regions  622 A. As shown in  FIG. 6E , the various thermal cycles associated with forming the shielded gate structure and the N+ regions  622 A cause P-type regions  618 C to out-diffuse thereby forming wider and taller body regions  618 D. As indicated earlier, these thermal cycles also cause N+epi  602  to diffuse upward as depicted in  FIG. 6E . It is important to ensure that upon completion of the manufacturing process, the two body regions between every two adjacent trenches remain spaced apart and do not merge, otherwise the Schottky diode is eliminated. Another goal in designing the process is to ensure that N− epi  620  and body region  618 D after completion of the process have substantially the same depth, although slightly different depths would not be fatal to the operation of the device. These goals can be achieved by adjusting a number of the process steps and parameters including the thermal cycles, the depth of the first trench recess ( FIG. 6B ), and doping concentration of various regions including the body regions, the N− epi region and the N+epi region. 
   In  FIG. 6F , without using a mask in the active region, a dimple etch process is performed to etch through N+ regions  622 A such that outer portions  622 B of N+ regions  622 A are preserved. The preserved outer portions  622 A form the source region. A dimple  624  is thus formed between every two adjacent trench. Dimples  624  form contact openings extending below source regions  622 B and into N− regions  620 . “Dimple etch” as used in this disclosure refers to silicon etch techniques which result in formation of silicon regions with sloped, rounded outer profiles as do source regions  622 B in  FIG. 6F . In one embodiment, the dimples extend to a depth within the bottom half of body regions  618 D. As indicated before, a deeper dimple results in formation of a Schottky contact below the source regions. This helps divert reverse avalanche current away from the source, thus preventing the parasitic bipolar transistor from turning on. While the above dimple etch does not require a mask in the active region, in an alternate embodiment a mask is used to define a central portion of N+ regions  622 A that is etched through to the desired depth. Outer portions of N+ regions  622 A extending under such a mask are thus preserved. These outer regions form the source regions. 
   Using a masking layer, P-type dopants are implanted into the dimple region intermittently along each stripe. Islands of heavy body regions (not shown) are thus formed between every two adjacent trench. If the heavy body implementation of  FIG. 4  is desired, a high enough dosage of P-type dopants need to be used during the heavy body implant in order to counter-dope those portions of the source regions where the heavy body regions are to be formed. If the heavy body implementation of  FIG. 5  is desired, a lower dosage of P-type dopants needs to be used during the implant so that the source regions are not counter-doped and thus remain intact. 
   In  FIG. 6F , conventional techniques can be used to form a Schottky barrier metal  630  over the structure. Schottky barrier metal  630  fills dimples  624 , and where metal  630  comes in electrical contact with N− regions  620 , a Schottky diode is formed. Metal layer  630  also contacts source regions  622 B and the heavy body regions. 
   In the process sequence depicted by  FIGS. 6A-6F , neither of the two masks used requires critical alignment. As a result, the integrated MOSFET-Schottky structure has many vertical and horizontal self-aligned features. In addition, the above-described process embodiments enable reduction of the channel length. Conventional processes utilize an implant and drive technique to form the body regions. This technique results in a tapered doping profile in the channel region requiring a longer channel length. In contrast, the above-described alternate techniques of selective epitaxial growth and two-pass angled implant for forming the body regions provide a uniform doping profile in the channel region, thus allowing a shorter channel length to be used. The on-resistance of the device is thus improved. 
   Moreover, use of a double epi structure provides design flexibility enabling optimization of the breakdown voltage and the on resistance while maintaining tight control over the MOSFET threshold voltage (Vth). Tight control over Vth is achieved by forming body regions  618  in N− epi  618  which compared to N+epi  602  exhibits a far more consistent and predictable doping concentration. Forming body regions in a background region with a predictable doping concentration allows tighter control over the threshold voltage. On the other hand, shielded electrodes  605  extending into N+epi  602  allows use of a higher doping concentration in N+epi  602  for the same breakdown voltage. A lower on-resistance is thus obtained for the same breakdown voltage and without adversely impacting control over the MOSFET threshold voltage. 
     FIGS. 7A-7C  show simulated avalanche current flow lines for three different dimple depths in an integrated trench MOSFET-Schottky diode structure. In the  FIG. 7A  structure, dimple  729 A extends to a depth just below source region  722 . In the  FIG. 7B  structure, dimple  729 B extends deeper to about one half the height of body region  718 . In the  FIG. 7C  structure, dimple  729 C extends even deeper to just above the bottom of body region  718 . In  FIGS. 7A-7C , a gap appears in the top metal  730 . This gap was included only for simulation purposes, and in practice, no such gap would be present in the top metal as is evident from the other figures in this disclosure. 
   As can be seen in  FIG. 7A , avalanche current flow lines  732 A are in close proximity to source region  722 . However, as the dimple depth is increased in  FIG. 7B  and yet deeper in  FIG. 7C , avalanche current flow lines  732 B and  732 C are shifted further away from source region  722  toward the Schottky region. The diversion of avalanche current away from the source region helps prevent the parasitic bipolar transistor from turning on, and thus improves the ruggedness of the device. In essence, the Schottky region acts like a heavy body region in collecting the avalanche current, thus eliminating the need for heavy body region for this purpose. Heavy body regions would still be required to obtain a good contact to the body region, but the frequency and size of the heavy body regions can be significantly reduced compared to conventional MOSFET structures. This frees up a large silicon area which is allocated to the Schottky diode. Thus, for the exemplary simulated structures in  FIGS. 7A-7C , dimples which extend to a depth within the bottom half of body region  718  provide optimum results. 
   While the invention has been described using shielded gate trench MOSFET embodiments, implementation of the invention in other shielded gate MOSFET structures and trench gate MOSFETs with thick bottom dielectric as well as other types of power devices would be obvious to one skilled in this art in view of this disclosure. For example, the above-described techniques for integrating Schottky diode with MOSFET can be similarly implemented in the various power devices disclosed in the above-referenced U.S. patent application Ser. No. 11/026,276, filed Dec. 29, 2004, in particular in the trench gate, shielded gate, and charge balance devices shown, for example, in  FIGS. 1 ,  2 A,  3 A,  3 B,  4 A,  4 C,  5 C,  9 B,  9 C,  10 - 12 , and  24 . 
   Although a number of specific embodiments are shown and described above, embodiments of the invention are not limited thereto. For example, while some embodiments of the invention are described using the open cell structure, implementing the invention using closed cell structures with various geometric shapes such as polygonal, circular, and rectangular, would be obvious to on skilled in this are in view of this disclosure. Further, while the embodiments of the invention are described using n-channel devices, the conductivity type of the silicon regions in these embodiments can be reversed to obtain p-channel devices. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claim, along with their full scope of equivalents.