Patent Publication Number: US-10763249-B2

Title: Image display device

Description:
BACKGROUND 
     1. Field 
     The present disclosure relates to an image display device. 
     2. Description of the Related Art 
     A display device which is provided with a plurality of micro light emission elements constituting a pixel on a drive circuit substrate has been proposed. As such a display device, for example, a small-sized display device for displaying a color image is disclosed in Japanese Unexamined Patent Application Publication No. 2002-141492. In the display device, a drive circuit is formed on a silicon substrate and a minute ultraviolet light emitting diode (LED) array is disposed on the drive circuit. In the display device, a wavelength conversion layer which converts ultraviolet ray into red, green, and blue visible lights is provided on an ultraviolet light emitting diode. 
     Such a display device has characteristics of small size, high luminance, and high durability. Therefore, it is expected to serve as a display device for a display apparatus such as a glasses-type device or head up display (HUD). 
     In addition, in such a display device, since materials constituting the drive circuit substrate and the micro light emission element are different, a process of bonding both the drive circuit substrate and the micro light emission element is desired. (See Japanese Unexamined Patent Application Publication No. 2002-141492 and United States Patent Application Publication No. 2011/0035925). 
     In a process of bonding a micro LED onto a large-scale integrated circuit (LSI) in which the drive circuit is formed to manufacture a minute projection display apparatus, it is desirable to bond a micro LED group which is a light emission element unit onto a wafer on which a drive circuit LSI is formed, and to electrically connect electrodes of the individual micro LEDs to electrodes of the drive circuit in one-to-one manner. The size of one micro LED is about 50 μm to several μm and the number of the micro LEDs is tens of thousands to millions. Accordingly, the size of one electrode is about 1 μm to 10 μm, which is very small. In addition, in the silicon substrate constituting a general drive circuit, a GaN layer which constitutes the micro LED and a sapphire substrate which is a growth substrate have different thermal expansion coefficients, when a temperature rises in the bonding process, design positions of the electrodes on the drive circuit LSI and the electrodes of the micro LED are deviated depending on difference in the thermal expansion coefficient and this leads to a situation that the small electrodes do not overlap with each other. Even if the electrodes are connected to each other by disposing patterns so as to overlap each other in a heated state, when the temperature returns to room temperature, the large thermal stress occurs to break the connection. 
     In order to avoid such a problem, a method of connecting electrodes without temperature rise has been proposed in United States Patent Application Publication No. 2011/0035925, but a special cylindrical electrode structure for connection has to be provided, and it is not easy to apply the method to a minute electrode. In addition, the large stress has to be applied for the connection, and when the display device has high resolution and the number of electrodes for connecting increases, it is desirable to apply a very large pressure. For this reason, it is not easy to apply the method disclosed in United States Patent Application. Publication. No. 2011/0035925 to the display device with high resolution. 
     It is desirable to provide a method of appropriately bonding electrodes, while suppressing the rise in temperature in bonding in which the number of bonding electrodes is large and the size of the electrode is small. 
     SUMMARY 
     (1) According to an embodiment of the present disclosure, there is provided an image display device comprising a plurality of micro light emission elements that are connected onto a drive circuit substrate incorporating a drive circuit of the micro light emission element, in which the micro light emission element has a light emitting surface on an opposite side to a bonding surface with the drive circuit, at least one of a surface on a connecting surface of the micro light emission element and a surface on a connecting surface side of the drive circuit substrate has a protrusion portion and a recess portion, an electrode of the micro light emission element and an electrode on a side of the drive circuit substrate are connected to each other via a metal nanoparticle, and a space formed between the surface on the connecting surface side of the micro light emission element and the surface on the connecting surface side of the drive circuit substrate is filled with a photo-curing resin. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a sectional view of a pixel portion of an image display device according to a first embodiment of the present disclosure; 
         FIGS. 2A and 2B  are top views of a micro light emission element according to the first embodiment of the present disclosure; 
         FIGS. 3A to 3E  are views showing a manufacturing step of the micro light emission element according to the first embodiment of the present disclosure; 
         FIGS. 4A to 4G  are views showing a manufacturing step of the image display device according to the first embodiment of the present disclosure; 
         FIG. 5A  is a top view of the image display device according to the first embodiment of the present disclosure and  FIGS. 5B and 5C  are sectional views of an outer peripheral portion of the image display device according to the first embodiment of the present disclosure; 
         FIGS. 6AA to 6AD  are top views of the micro light emission element according to a modification example of the first embodiment of the present disclosure; 
         FIGS. 6BA to 6BC  are top views of the micro light emission element according to the modification example of the first embodiment of the present disclosure; 
         FIGS. 7A to 7C  are sectional views of an image display device according to a second embodiment of the present disclosure; 
         FIGS. 8A to 8E  are views showing a manufacturing step of a micro light emission element according to the second embodiment of the present disclosure; 
         FIGS. 9A to 9H  are views showing a manufacturing step of the image display device according to the second embodiment of the present disclosure; 
         FIGS. 10A and 10B  are sectional views of an image display device according to a third embodiment of the present disclosure; 
         FIGS. 11A to 11D  are views showing a manufacturing step of a micro light emission element according to the third embodiment of the present disclosure; 
         FIGS. 12A to 12H  are views showing a manufacturing step of the image display device according to the third embodiment of the present disclosure; and 
         FIGS. 13A to 13E  are views showing a manufacturing step of a micro light emission element according to a fourth embodiment of the present disclosure. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     First Embodiment 1 
     One embodiment of the present disclosure will be described below. 
     Outline of Structure of Image Display Device 
     Hereinafter, embodiments of the present disclosure will be described with reference to the drawings ( FIG. 1 , and the like) by exemplifying an image display device  200  on which a plurality of micro light emission elements  100  are mounted as a light source. The image display device  200  has the plurality micro light emission elements  100  in a pixel region  1  ( FIG. 5A ). In addition, the image display device  200  includes a drive circuit substrate  50  for supplying a current to the micro light emission element  100  and emitting light. Light emitted from the micro light emission element  100  is emitted to an opposite side to the drive circuit substrate  50 . In the following, a case in which a single crystal silicon is adopted as a material of the drive circuit substrate  50  is described, but a glass substrate or a plastic substrate forming a polycrystal silicon TFT or an IGZO-TFT may be also adopted as the material of the drive circuit substrate  50 . 
     A wavelength conversion layer, a light diffusion layer, a color filter, a microlens, and the like may be disposed on a light emission side of the micro light emission element  100 , but the present disclosure is not directly related thereto, such that it is not described in the drawings. 
     The drive circuit substrate  50  is constituted by a micro light element drive circuit, a row selection circuit, a column signal output circuit, an image processing circuit, an input/output circuit, and the like. The micro light element drive circuit controls the current supplied to each micro light emission element  100 . In addition, the row selection circuit selects each row of the micro light emission element  100  arranged in a two-dimensional matrix form. In addition, the column signal output circuit outputs a light emission signal to each column of the micro light emission element  100 . In addition, the image processing circuit calculates a light emission signal based on an input signal. 
     A P-drive electrode  51  (second drive electrode) and an N-drive electrode  52  (first drive electrode) in order to connect to the micro light emission element  100  are disposed on a surface of a bonding surface side of the drive circuit substrate  50 . 
     In general, the drive circuit substrate  50  is a silicon substrate (semiconductor substrate) on which a large-scale integrated circuit (LSI) is formed, and since it can be manufactured by a known technique, functions and configurations of the techniques are not described in detail. 
     A section along a substrate surface of the micro light emission element  100  can have various planar shapes such as rectangular, polygonal, circular, and elliptical. The maximum length in a direction along a substrate surface is assumed to be 60 μm or less. 
     In addition, the image display device  200  is assumed that 3,000 or more micro light emission elements  100  are integrated into a pixel region  1 . 
     The micro light emission element  100  includes a compound semiconductor  14  as a light emission portion, and generally, an N-side layer  11  (first conductive layer), a light emission layer  12 , and a P-side layer  13  (second conductive layer) are each laminated in this order. 
     The compound semiconductor  14 , for example, a micro LED element which emits light in a wavelength band from ultraviolet ray to the green light, is a nitride semiconductor (AlInGaN-based). The compound semiconductor  14  is an AlInGaP-based in a case of emitting light in a wavelength band from yellowish green color to red color. Furthermore, the compound semiconductor  14  is an AlGaAs-based or a GaAs-based in a wavelength band from red color to infrared color. 
     Hereinbelow, a configuration, in which the N-side layer  11  is disposed on the light emission side, regarding the compound semiconductor  14  constituting the micro light emission element  100  will be entirely described. However, the compound semiconductor  14  can have a configuration in which the P-side layer  13  is disposed on the light emission side. 
     Although each of the N-side layer  11 , the light emission layer  12 , and the P-side layer  13  is generally optimized to include a plurality of layers rather than a single layer, but it is not directly related to the present disclosure, the detailed structure of each layer is not described. In general, the light emission layer is interposed between an N-type layer and a P-type layer, but there is also a case in which the N-type layer and the P-type layer include a non-doped layer or, in some cases, a layer having a dopant with opposite conductivity, and thus, the N-type layer and the P-type layer are described as an N-side layer and a P-side layer in the following. 
     Details of Image Display Device  200   
     As shown in.  FIG. 1 , the image display device  200  has a configuration in which the micro light emission element  100  which emits light is bonded at the bonding surface (indicated by thick broken line) on the drive circuit substrate  50 . The micro light emission element  100  has the light emission layer  12  isolated by an isolation trench  15 . In the pixel region  1 , a P-electrode  19 P (second electrode) connected to the P-side layer  13  is disposed in the region in which the light emission layer  12  remains. In addition, in the pixel region  1 , an N-electrode  19 N (first electrode) connected to the N-side layer  11  is disposed in the region (isolation region) of the isolation trench  15 . 
     Since the P-electrode  19 P and the N-electrode  19 N are simultaneously formed by the same step as described later, although shapes, sizes, and thicknesses are different from each other, but as a material, the P-electrode  19 P and the N-electrode  19 N are constituted by wiring materials having the same structure. Generally, the wiring material has a laminated structure formed of a plurality of layers such as a barrier metal layer, a main conductive layer, and a cap layer, but the P-electrode  19 P and the N-electrode  19 N have the same laminated structure. That is, the image display device  200  is constituted by a single wiring layer on the micro light emission element  100   b  side. 
     In the configuration of the present embodiment, since the P-electrode  19 P and the N-electrode  19 N are constituted by a metal material ohmic-connected to the N-side layer  11 , the ohmic connection to the P-side layer  13  is performed via a P-electrode layer  10 . In a case where the compound semiconductor  14  is a nitride semiconductor, the P-electrode layer  10  is a good conductor, for example, an indium-tin-oxide (ITO), which is a transparent electrode, palladium (Pd), or the like. 
     The isolation trench  15  of the micro light emission element  100  is buried with a protection layer  17  and a surface (second surface) on the bonding surface side of the protection layer  17  is flat. The P-electrode  19 P and the N-electrode  19 N are formed on the bonding surface side, and the surfaces are configured in a flat surface having almost the same height as that of the surface of the protection layer  17 . 
     In addition, the surface of the P-drive electrode  51  and the surface of N-drive electrode  52  on the drive circuit substrate  50  side are configured to be higher than a surface of an insulating layer  55 . That is, the P-drive electrode  51  and the N-drive electrode  52  are protrusion portions on the surface of the drive circuit substrate  50  and portions of the insulating layer  55  not covered by the electrodes are recess portions. The P-electrode  19 P and the N-electrode  19 N are respectively connected to the P-drive electrode  51  and the N-drive electrode  52  on the drive circuit substrate  50  side. 
     Nanometer-sized metal nanoparticles  30  are arranged at a boundary surface between the P-electrode  19 P and the P-drive electrode  51  and a boundary surface between the N-electrode  19 N and the N-drive electrode  52 . A space portion between the drive circuit substrate  50  and the micro light emission element  100  is filled with a photo-curing resin  31 . Since the P-electrode  19 P and the P-drive electrode  51 , or the N-electrode  19 N and the N-drive electrode  52  are in contact with each other via a number of metal nanoparticles  30  and the drive circuit substrate  50  and the micro light emission element  100  are firmly in close contact with each other due to a shrinkage of the photo-curing resin  31 , excellent electrical connection can be realized. A material of the metal nanoparticles  30  is palladium (Pd), gold (Au), platinum (Pt), nickel (Ni), aluminum (Al), or the like. The photo-curing resin  31  is a resin which causes a polymerization reaction to be cured by irradiation of ultraviolet rays or near-ultraviolet rays, may be an acrylate radical polymerization type resin such as an epoxy-based resin, a urethane-based resin, an acrylic based-resin, and a silicone-based resin, and may be a cationic polymerization type resin such as an epoxy-based resin. 
     As such, the P-electrode  19 P and the P-drive electrode  51 , or the N-electrode  19 N and the N-drive electrode  52  are electrically connected to each other by the metal nanoparticles  30 , such that surface layers of the P-electrode  19 P and the N-electrode  19 N and surface layers of the P-drive electrode  51  and the N-drive electrode  52  may be different materials. 
     Outline of Micro Light Emission Element  100   
     As viewed from the bonding surface side, in general, the micro light emission elements  100  are arranged in a two-dimensional array. As shown in  FIG. 2B , the P-electrode  19 P is disposed in the center portion of the micro light emission element  100  and the N-electrode  19 N is disposed at an isolation region of a boundary. The isolation trench  15  is present at a lower portion of the N-electrode  19 N as shown in  FIG. 2A .  FIG. 1  shows an I-I cross section in  FIG. 2B . In addition,  FIG. 2A  show a surface after forming the isolation trench  15  (state of  FIG. 3B ). Furthermore,  FIG. 2B  shows a surface after forming the P-electrode  19 P and the N-electrode  19 N (state of  FIG. 3E ). However, the protection layer  17  is omitted. 
     Manufacturing Method of Micro Light Emission Element  100   
     Next, a manufacturing step of the micro light emission element  100  is described with reference to  FIGS. 3A to 3E . As shown in  FIG. 3A , the compound semiconductor  14  formed of the N-side layer  11 , the light emission layer  12 , and the P-side layer  13  is sequentially laminated on a growth substrate  9 , and the P-electrode layer  10  is deposited on the compound semiconductor. The growth substrate  9  is, for example, a sapphire substrate. The growth substrate  9  is desirably a substrate transparent to ultraviolet ray or near-ultraviolet ray. 
     Next, as shown in  FIG. 3B , portions of the P-electrode layer  10 , the P-side layer  13 , the light emission layer  12 , and the N-side layer  11  are etched to form the isolation trench  15 . At this time, the portion including the light emission layer  12  is referred to as a mesa  16 . 
     As shown in.  FIG. 2A , the isolation trenches  15  are arranged in vertical and horizontal directions at equal intervals and the mesa  16  has a truncated square pyramid shape. However, the shape of the mesa  16  is not limited to the truncated square pyramid shape and may be a truncated cone shape or other polygonal truncated cone shapes. 
     It is desirable that a side wall of the mesa  16  is inclined at 45 degrees±10 degrees with respect to the surface formed by the light emission layer  12 . Among light emitted from the light emission layer  12 , a proportion of the light traveling in a direction parallel with the light emission layer  12  is largest. Therefore, light emitting efficiency of the micro light emission element  100  can be improved by reflecting the light to a direction of a light emission surface. 
     Light emitted to a horizontal direction repeats the reflection, is absorbed by vertical sidewalls and therefore does not exit to the outside freer the light emission surface in a case where the side wall of the mesa  16  is perpendicular. If the inclination of the side wall of the mesa  16  is greatly deviated from 45 degrees, an incident angle becomes too large when the light is incident on the light emission surface, which causes total reflection on the light emission surface and thus the light does not exit to the outside. 
     Next, as shown in  FIG. 3C , the protection layer  17  is deposited to flatten by chemical-mechanical-polishing (CMP) the surface. The protection layer  17  is an insulating layer, and is, for example, SiO 2 , SiN, or SiON, or a laminated film formed thereof. In a formation of the protection layer  17 , various film formation techniques such as a chemical vapor deposition (CVD) method, a sputtering method, and a coating method can be used. 
     Next, as shown in.  FIG. 3D , a P-groove  18 P is formed on the mesa  16  and an N-groove  18 N is formed on the isolation trench  15 . The P-groove  18 P has a hole shape and reaches the P-electrode layer  10 . The N-groove  18 N is a channel shape running in both the vertical and horizontal directions and reaches the N-side layer  11  of a bottom portion of the isolation trench  15 . 
     Furthermore, as shown in  FIG. 3E , the P-groove  18 P and the N-groove  18 N are buried with the metal film by a damascene method to form the P-electrode  19 P and the N-electrode  19 N. The metal film is a combination of a barrier film such as tantalum (Ta), tungsten (W), and titanium nitride (TiN) with copper. The metal film may also be a combination of gold or nickel, an aluminum alloy, or the like with the corresponding barrier film. In the damascene method, a metal thin film is deposited and CMP polishing is performed on a base structure having a groove, so that the metal thin film can remain in the groove and the surface is flattened. 
     Here, the damascene method is one of the metal wiring formation method of LSI, and is a thin film formation technique using a plating technique and a CMP method in combination. The damascene technique of burying a fine metal wiring layer in the insulating layer is referred to as a damascene method. Copper wiring is usually produced by using the damascene method. A groove is formed with a wiring shape in an interlayer insulating layer and metal such as copper is buried. There is two wiring methods, one is called a “single damascene wiring method”, which is a method of forming a wiring groove after forming a contact plug of metal in a connection hole. The other method is called a “dual damascene wiring method”, which is a method of burying the metal at once after forming the connection hole and the wiring groove. The damascene method is used in combination with a CMP technique of flattening a multilayer wiring layer. The step of  FIGS. 3A to 3E  is a single damascene wiring method. 
     By doing so, the P-electrode  19 P is disposed on the mesa  16 , the N-electrode  19 N is disposed on an isolation trench  15 , the P-electrode  19 P and the N-electrode  19 N are disposed together on the surface the same plane) which is to be the bonding surface, such that the surfaces thereof are configured to be made of the same materials and are leveled with the surface of the protection layer  17 . 
     In the configuration of the embodiment, the wiring layer is formed of one layer, and can be formed by the two-stage photolithography process of forming the isolation trench  15  and the mesa  16  and forming the P-groove  18 P and the N-groove  18 N. Therefore, the micro light emission element  100  can be manufactured in a very simple manufacturing step, such that the capital investment can be reduced and manufacturing costs can be greatly reduced. Manufacturing Method of Image Display Device  200   
     Next, a manufacturing step of the image display device  200  will be described with reference to  FIG. 4 . As shown in  FIG. 4A , the micro light emission element  100  is formed through the steps of  FIGS. 3A to 3E . Next, as shown in  FIG. 4B , the metal nanoparticles  30  are arranged on the substrate of the micro light emission element  100 . The metal nanoparticles  30  are, for example, palladium. 
     The nanoparticles of the palladium can be formed utilizing self-organization of a block copolymer. (see Japanese Patent No. 5875124). One of the methods of utilizing the self-organization of the block copolymer is a method of (i) spin-coating polystyrene-block-poly(2-vinylpyridine) which is a kind of the block copolymer on the micro light emission element  100 , (ii) immersing the spin-coated film to an aqueous solution of sodium tetrachloropalladate (Na2PdCl4) and selectively precipitating the palladium ion into a 2-vinylpyridine core in polystyrene-block-poly(2-vinylpyridine), and (iii) removing polystyrene-block-poly(2-vinylpyridine) by a plasma treatment. In this method, the palladium nanoparticles having sizes of several tens of nanometers can be precipitated at an interval of about 100 nm to 300 nm. 
     The thickness of the block copolymer for forming such metal nanoparticles  30  are very thin, such that it is not easy t uniformly form the nanoparticles on the surface with large protrusions and recesses. Accordingly, an electrode surface on which the metal nanoparticles  30  are formed is desirable to be flat. In the present embodiment, this condition is satisfied by forming the surface of the micro light emission element  100  to be flat. 
     In addition, the drive circuit substrate  50  is manufactured as shown in  FIG. 4C . The drive circuit substrate  50  is formed on a single crystal silicon substrate (wafer) by the ordinary complementary metal oxide semiconductor (CMOS) process. The surface of the P-drive electrode  51  and the surface of the N-drive electrode  52  on the drive circuit substrate  50  side is configured to be higher than the surface of the insulating layer  55 . The wiring material constituting the P-drive electrode  51  and the N-drive electrode  52  is, for example, copper wiring or an aluminum alloy. The aluminum is processed by a dry etching technique in a case of the aluminum alloy, such that it is easy to form the structure in  FIG. 4C . The copper wiring is formed by a damascene method in a case of the copper wiring, such that it requires an additional step of etching the insulating layer around copper wiring because the surface is flattened. That is, as shown in  FIG. 4C , a protrusion portion of the surface on the bonding surface side of the drive circuit substrate  50  is an electrode constituting the P-drive electrode  51  or the N-drive electrode  52 , and a recess portion is an exposed portion of the insulating layer  55  which is disposed between the electrodes. 
     Here, it is desirable that the drive circuit substrate  50  is in a wafer state and it is desirable that the micro light emission elements  100  and their growth substrate  9  in  FIG. 4A  is a group divided from a wafer for example, where each group corresponds to an image display device  200 . The divided group of the micro light emission element  100  is referred to as a light emission element unit  101 . 
     Next, the light emission element unit  101  is disposed on the silicon surface on which the drive circuit substrate  50  is formed as shown in  FIG. 4D . At this stage, a space  33  is disposed between the surface on the bonding surface side of the drive circuit substrate  50  and the surface on the bonding surface side of the light emission element unit  101 . Next, as shown in  FIG. 4E , the space  33  is filled with the photo-curing resin  31  by injecting the photo-curing resin  31  into the space  33 . By performing the connection for every light emission element units, the time necessary the photo-curing resin  31  to be spread all over the space can be shortened and the bonding time is also shortened. It is also possible to bond the wafers together by taking more time. 
     In order to widely spread the photo-curing resin  31  between the drive circuit substrate  50  and the light emission element unit  101 , a space is desirable between both of them. It is not easy to spread the photo-curing resin  31  over the space defined by a height of the metal nanoparticles  30  in a short time. Since the connecting surface of the light emission element unit  101  side to which the metal nanoparticles  30  are bonded is flat, it is desirable to form protrusion portions or recess portions on the drive circuit substrate  50  side in order to form the sufficient space  33 . This is the reason why the P-drive electrode  51  and the N-drive electrode  52  have a projecting shape. 
     Next, as shown in  FIG. 4F , light is radiated from the growth substrate  9  side to cure the resin, such that the photo-curing resin  31  is cured. In a case where the growth substrate  9  does not transmit light as a silicon substrate, since photo curing is not able to be performed unless the growth substrate  9  is peeled off, it is desirable that the growth substrate  9  transmits light for photo-curing. By performing the photo curing, the drive circuit substrate  50  and the micro light emission element  100  are firmly connected to each other, and thus it is easy to perform a subsequent peeling step of the growth substrate ( FIG. 4G ). The peeling of the growth substrate  9  can be realized by the laser lift-off method or the like. By performing heating after peeling the growth substrate  9 , the polymerization of the photo-curing resin  31  is further promoted so as to make electrical connection firmer. At this time, since the growth substrate  9  is peeled off, the thermal stress caused due to the difference in coefficient of thermal expansion is greatly released. 
     Even when the P-electrode  19 P and the N-electrode  19 N of the micro light emission element  100  are press-bonded to the P-drive electrode  51  and the N-drive electrode  52  of the drive circuit substrate  50  through the metal nanoparticles  30 , respectively, the connection resistance is not able to be substantially reduced. However, the connection resistance can be reduced without raising a temperature because of large shrinkage stress, which is appeared by irradiating the photo-curing resin  31  with curing light. Accordingly, the connection for the drive circuit substrate  50  and the micro light emission element  100  which are greatly different in thermal coefficients of expansion can be performed without concerning the position deviation of the electrodes. 
     Effect 
     Next, a plan view of the image display device  200  is shown in  FIG. 5A . In the image display device  200 , a portion which emits light and actually displays an image is the pixel region  1 . The description so far is mostly for the pixel region  1 . 
     In addition to the pixel region  1 , a dummy region  2  which does not emit light, a plurality of external connection regions  3 , a scribing portion  4  which separates the image display devices  200  individually from each other, or the like are present in the image display device  200 . In the dummy region  2 , the row selection circuit, the column signal output circuit, the image processing circuit, and the input/output circuit other than the micro light element drive circuit are disposed on the drive circuit substrate  50 . 
     The light emission element unit  101  is bonded to cover the pixel region  1 . The micro light emission element  100  as shown in  FIG. 1  is disposed in the light emission element unit  101  on the pixel region  1 , but it is desirable to dispose a substrate-side dummy electrode  53  outside the pixel region  1  on the drive circuit substrate  50  and a dummy element  110  as a part of the light emission element unit  101  on the substrate-side dummy electrode  53 . It is preferable that the dummy element  110  and the micro light emission element  100  are manufactured at same time on the growth substrate  9 . Thus they have the same layered structure as shown in  FIG. 4G  and  FIG. 5B  and are formed of an identical material. These structures are for reducing leakage of the photo-curing resin  31  to the outside of the light emission element unit  101 . For example, when the large amount of the photo-curing resin  31  leaks to the direction of (B) or (C) in a case where the photo-curing resin  31  is injected to a portion between the drive circuit substrate  50  and the light emission element unit  101  from the direction of (A) in  FIG. 5A , the leaked resin covers the external connection region  3  and it is hard to remove the leaked resin. On the other hand, as in a direction of (D), some leakage to a portion where the external connection region  3  does not present does not matter. In addition, when the space between the drive circuit substrate  50  and the light emission element unit  101  is reduced, it takes more time for the photo-curing resin  31  to spread all over the space and the process time becomes longer, which are not desirable. Therefore, in an outer peripheral portion of the pixel region  1 , it is desirable to adjust the size of the space depending on the directions. That is, in the dummy region  2 , a space at a side adjacent to the external connection region  3  is provided to be small, and a space at a side far from the external connection region  3  is provided to be large. 
     In this configuration, the bonding surface of the light emission element unit  101  is flat, such that the size of the space is adjusted depending on the length of the substrate-side dummy electrode  53  on the drive circuit substrate  50  side. The substrate-side dummy electrode  53  may be increased in a case of making the space smaller as shown in  FIG. 5B  and the substrate-side dummy electrode  53  may be shortened in a case of making the space longer as shown in  FIG. 5C . Here, the space is a portion which is filled with the photo-curing resin  31 . As such, the leakage of the photo-curing resin  31  can be controlled to facilitate the electric connection in the external connection region  3  by disposing the substrate-side dummy electrode  53  for adjusting the size of the space and the dummy element  110  corresponding to the substrate-side dummy electrode  53  in the outer peripheral portion of the pixel region  1 . That is, in this configuration, leakage of the photo-curing resin  31  from the pixel region  1  adjacent to the external connection region  3  can be smaller than leakage of the photo-curing resin  31  from the pixel region  1  far from the external connection region  3 . 
     The dummy element  110  in an outer periphery of the light emission element unit  101  can be used as a temporal region when bonding the light emission element unit  101  onto the drive circuit substrate  50 . It is not desirable to keep a state in which the light emission element unit  101  is pressed against the drive circuit substrate  50  while uniformly spreading the photo-curing resin  31  because the bonding throughput is decreased. For example, by performing light irradiation after injecting the photo-curing resin  31  from (B) side and (C) side and infiltrating the photo-curing resin  31  under the dummy element  110 , the light emission element unit  101  is fixed to the drive circuit substrate  50  in the portion of the dummy element  110 . The time desired for the photo-curing resin  31  to over the dummy element  110  is shorter than the time of infiltrating the whole light emission element unit, such that the bonding throughput can be improved. The photo-curing resin  31  is injected from (A) side after bonding a plurality of light emission element units  101  and is spread all over the light emission element unit  101 , and then the light irradiation is performed. These steps can be performed concurrently to the plurality of light emission element units  101 , high productivity can be realized even if it takes some time. Such a case, the space that is formed by the substrate-side dummy electrode  53  may be larger on (B) side and (C) side than the pixel region  1 . When the photo-curing resin  31  is injected from (B) side and (C) side, since it is desirable to infiltrate a small amount of the photo-curing resin  31  into the dummy element  110  in a short time, it is desirable that the space is large. When the photo-curing resin  31  is injected from (A) side, the photo-curing resin  31  does not leak from (B) side and (C) side, because (B) side and (C) side have already been blocked by previously injected and cured photo-curing resin  31 . On the other hand, in order to uniformize the infiltration of the photo-curing resin  31  on (D) side, for example, the space that is formed by the substrate-side dummy electrode  53  is reduced at the center portion of (D) side where infiltration speed is high, and the space can be gradually widen toward ends adjacent to (B) side and (C) side. That is, the dummy region  2  has a side in which a small space is provided at the center portion and a large space is provided at the periphery portion. 
     As such, it is desirable that the dummy element  110  is disposed at the outer periphery of the pixel region  1  in order to temporarily fix the light emission element unit  101 , reduce the leakage of the photo-curing resin  31 , uniformize the infiltration of the photo-curing resin  31 , or the like. Furthermore, it is desirable to dispose the substrate-side dummy electrode  53  for controlling the space between the light emission element unit  101  and the drive circuit substrate  50  in the outer periphery of the pixel region  1 . To temporarily fix the light emission element unit  101 , it is preferable that the dummy elements on two sides facing to each other like (B) and (C) have larger space than the light emission element  100  in the pixel region. It is also preferable at least one of the sides is adjacent to the external connection region  3 . 
     Modification Example of First Embodiment 
     In a first embodiment, the micro light emission element  100  is one type and is a monochromatic display device. However, as shown in.  FIG. 6AA , a pixel  5  is formed of a blue sub-pixel  6 , a red sub-pixel  7 , and a green sub-pixel  8 , so that a full color display device can be formed. Each sub-pixel has an individual micro light emission element. Each sub-pixel may be composed of a micro light emission element which emits blue light, red light, and green light, and the micro light emission element which emits the blue light may be combined with the wavelength conversion layer to emit the red light or the green light. 
     In  FIG. 6AA , a periphery of each sub-pixel is surrounded by the isolation trench  15 , the N-electrodes  19 N are disposed all of on the isolation trench  15 . However, as shown in  FIG. 6AB , it is possible to dispose the N-electrode  19 N so as to surround the pixel  5  while surrounding the periphery of each sub-pixel by the isolation trench  15 . In such a case, it is not desirable to dispose the N-electrode  19 N between the sub-pixels in the pixel  5 , such that the isolation trench  15  between the sub-pixels can be narrowed. As a result, by widening a width of the mesa  16  of the sub-pixel, an area of the light emission layer  12  is widened, a density of current flowing in the light emission layer  12  is lowered, and thus the light emitting efficiency can be improved. 
     Furthermore, as shown in  FIG. 6AC , the N-electrode  19 N can be disposed in only one side of the boundary of the pixel  5  or, as shown in  FIG. 6AD , the N-electrode  19 N can be disposed at four corners of the pixel  5  in a dot shape. Both of  FIGS. 6AC and 6AD  have the same effect as  FIG. 6AB , and the effect for improving light emitting efficiency becomes larger as an amount of the N-electrode  19 N disposed is reduced. As such, the N-electrode  19 N is disposed on the isolation trench  15  and it is not desirable to dispose the N-electrode  19 N on the entire region of the isolation trench  15 . Since it is desirable that the wiring resistance is uniform between the pixels  5  in order to make the variation in light output uniform between the pixels  5 , it is desirable that the N-electrode  19 N is at least provided for each pixel  5 . Accordingly, as shown in  FIG. 6AD , it is most desirable to dispose the N-electrode  19 N at four corners of the pixel  5 . A shape of the sub-pixel is not limited to a shape shown in  FIG. 6AA , for example, a shape shown in  FIG. 6BA  may be used. 
     In the above examples, one P-electrode  19 P is disposed for micro light emission element  100 , but is not necessarily limited to one. For example, as shown in  FIG. 6BB , two of a P-electrode  1   19 P 1  and a P-electrode  2   19 P 2  may be disposed. By providing the P-electrode  1   19 P 1  and the P-electrode  2   19 P 2 , in a case where a conduction defect occurs on one of them, a redundant function of replacing the one to the other one can be realized. Here, the redundant function means that a spare device is disposed as a backup in a system, the backup device replaces a failure device which appears in the system, and the function of the entire system can be maintained. 
     In addition, as shown in  FIG. 6BC , the micro light emission element  100  can be substantially divided in two by also dividing the P-electrode layer into a P-electrode layer  1   10 - 1  and a P-electrode layer  2   10 - 2 . In a case where the P-electrode  1   19 P 1  side is defective, the redundant function can be realized not only for the conduction defect of the electrode but also for the micro light emission element  100  by using the P-electrode  2   19 P 2 . 
     In order to realize the redundant function, it is required to cause each micro light emission element  100  on the drive circuit substrate  50  side to have a function of storing whether or not the defect occurs and selecting the normal P-electrode at the time of operation. Although it increases costs, cost reduction effect due to yield improvement by redundancy becomes larger in general, and thus such a redundant function is effective. 
     In this case, the pattern of the P-electrode layer  10  and the pattern of the mesa  16  are different from each other, so that the photolithography process may increase by one step. However, it can be determined which way to choose, to have only two P-electrodes or to split both P-electrode layer and P-electrode, by considering trade-off between the increase in cost due to process increase and the cost reduction due to the yield improvement by the redundant function. As such, the P-electrode is disposed on the mesa.  16  having the light emission layer  12 , but is not necessarily limited to one, and a plurality the P-electrodes may be disposed. 
     To dispose the electrode in the micro light emission element  100  in a small and dense manner is desirable from various aspects, such as not only the minimization of the pixel but also a formation of the sub-pixel for colorization and an addition of redundant function for yield improvement, as described above. It is becoming more and more difficult to form a bump on each electrode in response to such the miniaturization in size of the electrode. As in the present disclosure, in the structure for disposing the self-organized metal nanoparticles, a number of projecting portions can be provided on the respective electrodes without concerning a short circuit between the electrodes. 
     Second Embodiment 
     Another embodiment of the present disclosure will be described below. 
     As shown in  FIG. 7A , an image display device  200   a  of the present disclosure is different from the image display device  200  of the first embodiment in that, the bonding surface on a drive circuit substrate  50   a  side is flat, the bonding surface side of the micro light emission element  100   a  is not flat, the micro light emission elements  100   a  are separated individually, the micro light emission element  100   a  has the P-electrode  19 P on the bonding surface side, and the common N-electrode  40  is provided on the light emission surface side. 
     Outline of Image Display Device  200   a    
     As shown in.  FIG. 7A , the image display device  200   a  has a configuration in which the micro light emission element  100   a  which emits light is bonded to the drive circuit substrate  50   a.  at the bonding surface (indicated by thick broken line). The micro light emission element  100   a  has the light emission layer  12  isolated by the isolation trench  15  and, the micro light emission elements  100   a  are separated individually by the separation trench  20 . In the pixel region  1 , the P-electrode  19 P (second electrode) connected to the P-side layer  13  is disposed in the region in which the light emission layer  12  remains. In addition, as shown in  FIG. 7B , the common N-electrode  40  connected to the N-side layer  11  is connected to the N-electrode  19 N (first electrode) outside the pixel region  1 . 
     A surface of the P-drive electrode  51  on a drive circuit substrate  50   a  side is configured to be almost flush with a surface of the insulating layer  55 . The P-electrode  19 P is connected to the P-drive electrode  51  on the drive circuit substrate  50   a  side. 
     Nanometer-sized metal nanoparticles  30  are arranged at the boundary surface between the P-electrode  19 P and the P-drive electrode  51 . A portion between the drive circuit substrate  50   a  and the micro light emission element  100   a  is filled with the photo-curing resin  31 . Since the P-electrode  19 P and the P-drive electrode  51 , or the N-electrode  19 N and the N-drive electrode  52  are in contact with each other via a number of metal nanoparticles  30  and the drive circuit substrate  50   a  and the micro light emission element  100   a  are firmly in close contact with each other due to the shrinkage of the photo-curing resin  31 , excellent electrical connection can be realized. 
     In this configuration, the bonding surface of the drive circuit substrate  50   a  is flat, such that the size of the space  33  is determined by the P-electrode  19 P, an exposed portion of the protection layer  17  disposed in a part of the isolation trench  15 , and the separation trench  20 . That is, the P-electrode  19 P is a protrusion portion and both the exposed portion of the protection layer  17  and the separation trench  20  are the recess portion of the surface on the bonding surface side of the micro light emission element  100   a.  The recess potion overlaps the isolation trench  15 . Specially, the size of the space  33  is adjusted depending on the length of the P-electrode  19 P on a light emission element unit  101   a  side and the width of the separation trench  20 . As shown in  FIG. 7C , in a case where the space  33  is reduced, the P-electrode  19 P in a dummy element  110   a  may be elongated so as to reduce the disposition of a separation trench  20 . On the contrary, the separation trench  20  may be disposed densely so as to shorten the P-electrode  19 P in a case where the space  33  becomes large. That is, the length of the part of the isolation trench  15  may be longer. As in the first embodiment, the dummy element  110   a  can be used for temporarily fixing the light emission element unit  101   a  by disposing the dummy element  110   a  on an outer periphery portion of the pixel region  1 . In addition, as in the first embodiment, the leakage of the photo-curing resin  31  can be reduced or the infiltration of the photo-curing resin  31  can be uniformized by controlling a width of the space  33  of the dummy element  110   a.    
     Manufacturing Method of Micro Light Emission Element  100   a    
     Next, a manufacturing step of the micro light emission element  100   a  will be described with reference to  FIGS. 8A to 8E . The figure shows the pixel region  1  on the left side and a portion of the dummy element  110   a  including the N-electrode on the right side. As can been seen in  FIG. 8A to 8E , the dummy element  110   a  and the micro light emission element  100   a  are manufactured at same time on the growth substrate  9 . Thus they have the same layered structure and are formed of an identical material. The manufacturing step of the micro light emission element  100   a  is made through the same step in  FIGS. 3A to 3C , and thus will be omitted. Accordingly, the protection layer  17  is deposited on the mesa  16  as shown in  FIG. 8A , and then, the P-groove  18 P is formed on the mesa  16  as shown in  FIG. 8E . The P-groove  18 P has a hole shape and reaches the P-electrode layer  10 . The N-groove  18 N is formed on the bottom portion of the isolation trench  15  and reaches the N-side layer  11  in a dummy element region. As shown in  FIG. 8C , the P-groove  18 P and the N-groove  18 N are buried with the metal film and the P-electrode  19 P and the N-electrode  19 N are formed, by the damascene method. 
     Next, as shown in  FIG. 8D , an upper portion of the P-electrode  19 P and the N-electrode  19 N is exposed by etching the surface of the protection layer  17 . This etching may be dry etching or wet etching. Furthermore, as shown in  FIG. 8E , the protection layer  17  and the compound semiconductor  14  are etched to form the separation trench  20 . The separation trench  20  desirably separates the micro light emission element  100   a  individually. Since light leakage between the micro light emission elements  100   a  is reduced by separating the micro light emission element  100   a,  contrast of a display image can be improved and color mixture can be reduced. 
     As in the micro light emission element  100   a,  the light emission element which has only one electrode on the bonding surface needs additional process steps to form the other electrode on the light emission surface after bonding to the drive circuit substrate  50   a  However, the micro light emission element  100   a  is beneficial in that the pixel can be formed to such a fine pixel size that there is no space for disposing the P-electrode and the N-electrode in parallel on the bonding surface. 
     As shown in.  FIG. 8E , it is desirable that the separation trench  20  reaches the growth substrate  9 , however, the compound semiconductor  14  may remain. As a film thickness of remained compound semiconductor  14  becomes thinner, the light leakage is reduced and thus, from the viewpoint of reduction of the light leakage, it is desirable that the film thickness of remained compound semiconductor  14  is as thin as possible. However, remaining the thin compound semiconductor  14  is beneficial in that the resistance of the common N-electrode  40  and the diffusion of exit light cap be reduced since the light emission surface of the micro light emission element  100   a  can be uniform and flat. 
     Manufacturing Method of Image Display Device  200   a    
     Next, a manufacturing step of the image display device  200   a  will be described with reference to  FIGS. 9A to 9H . As shown in  FIG. 9A , the micro light emission element  100   a  is formed through the steps in  FIGS. 8A to 8E . Next, the drive circuit substrate  50   a  is manufactured as shown in  FIG. 9B . The drive circuit substrate  50   a  is formed on a single crystal silicon substrate (wafer) by the ordinary complementary metal-oxide semiconductor (CMOS) process. The surface of the P-drive electrode  51  and the surface of the N-drive electrode  52  on the drive circuit substrate  50   a  side is configured to be flush with the surface of the insulating layer  55 . The wiring material forming the P-drive electrode  51  and the N-drive electrode  52  is, for example, copper wiring. In a case of the copper wiring, the copper wiring is formed by the damascene method, such that the surface is flat and the structure in  FIG. 9B  can be easily manufactured. 
     Next, as shown in  FIG. 9C , the nanoparticles of palladium are arranged on the surface of the drive circuit substrate  50   a  by the method as in the first embodiment. In the first embodiment, the metal nanoparticles  30  are arranged on the bonding surface of the micro light emission element  100  as shown in  FIG. 4B , but in the present embodiment, the metal nanoparticles  30  are arranged on the bonding surface of the drive circuit substrate  50   a.    
     Here, it is desirable that the drive circuit substrate  50   a  is in a wafer state and it is desirable that the micro light emission elements  100   a  and their growth substrate  9  in  FIG. 9A  is a group divided from a wafer for example, where each group corresponds to an image display device  200   a.  The divided group of the micro light emission element  100   a  is referred to as a light emission element unit  101   a.    
     Next, the light emission element unit  101   a  is disposed on the silicon surface on which the drive circuit substrate  50   a  is formed as shown in  FIG. 3D , and the photo-curing resin  31  is injected to the boundary surface as shown in  FIG. 9E . By performing connection in unit of the light emission element, the time in which the photo-curing resin  31  is spread all over the space can be shortened and therefore the bonding time is also reduced. It is also possible to bond the wafers together by taking more time. 
     Next, as shown in  FIG. 9F , light for curing resin is radiated from the growth substrate  9  side to cure the resin, such that the photo-curing resin  31  is cured. In a case where the growth substrate  9  does not transmit light like a silicon substrate, since photo curing is not able to be performed unless the growth substrate  9  is peeled off, it is desirable that the growth substrate  9  can transmit light to cure the photo-curing resin  31 . By performing the photo curing, the drive circuit substrate  50   a  and the micro light emission element  100   a  are firmly connected to each other, and thus it is easy to perform a subsequent peeling step of the growth substrate ( FIG. 9G ). The peeling of the growth substrate  9  can be realized by the laser lift-off method or the like. By performing heating after peeling the growth substrate  9 , the polymerization of the photo-curing resin  31  is further promoted so as to make electrical connection firmer. At this time, since the growth substrate  9  is peeled off, the thermal stress caused by the difference in coefficient of thermal expansion is greatly released. 
     Next, as shown in  FIG. 9H , the common N-electrode  40  is formed on the light emission surface side of the micro light emission element  100   a.  The common N-electrode  40  is indium-tin-oxide (ITO) thin film which is a transparent conductive film. 
     In this configuration, the effect same as the first embodiment can be obtained. 
     Third Embodiment 
     Still another embodiment of the present disclosure will be described below. 
     As shown in.  FIG. 10A , in an image display device  200   b  of the present embodiment, both the bonding surface on a drive circuit substrate  50   b  side and the bonding surface on a micro light emission element  100   b  side are not flat and the micro light emission elements  100   b  are separated individually, which are different from the image display device  200  of the first embodiment. 
     Outline of Image Display Device  200   b    
     As shown in  FIG. 10A , the image display device  200   b  has a configuration in which the micro light emission element  100   b  which emits light is bonded to the bonding surface (indicated by thick broken line) on the drive circuit substrate  50   b.  The micro light emission element  100   b  has the light emission layer  12  isolated by an isolation trench  15  and, the micro light emission elements  100   b  are separated individually by the separation trench  20 . 
     Since the P-electrode  19 P and the N-electrode  19 N are simultaneously formed by the same step as described later, although shapes, sizes, and depths are different from each other, as a material, the P-electrode  19 P and the N-electrode  19 N are constituted by the wiring materials having the same structure. Generally, the wiring material has a laminated structure formed of a plurality of layers such as a barrier metal layer, a main conductive layer, and a cap layer, but the P-electrode  19 P and the N-electrode  19 N have the same laminated structure. That is, the image display device  200   b  is constituted by a single wiring layer on the micro light emission element  100   b  side. 
     In the configuration of the present embodiment, since the P-electrode  19 P and the N-electrode  19 N is formed of a metal material ohmic-connected to the N-side layer  11 , the ohmic connection to the P-side layer  13  is performed via the P-electrode layer  10 . In a case where the compound semiconductor  14  is a nitride semiconductor, the P-electrode layer  10  is a good conductor, for example, an indium-tin-oxide (ITO) which is a transparent electrode, palladium (Pd), or the like. 
     The isolation trench  15  of the micro light emission element  100   b  is covered by a protection layer  17   b,  but is not buried. The P-electrode  19 P and the N-electrode  19 N are formed on the bonding surface side and the P-electrode  19 P (second electrode) connected to the P-side layer  13  and the N-electrode  19 N connected to the N-side layer  11  are disposed in the region in which the light emission layer  12  of the micro light emission element  100   b  remains. 
     The surface of the P-drive electrode  51  and the surface of the N-drive electrode  52  on the drive circuit substrate  50   b  side are configured to be higher than the surface of the insulating layer  55 . The P-electrode  19 P and the N-electrode  19 N are respectively connected to the P-drive electrode  51  and the N-drive electrode  52  on the drive circuit substrate  50   b  side. 
     Nanometer-sized metal nanoparticles  30  are arranged at the boundary surface of both electrodes. A portion between the drive circuit substrate  50   b  and the micro light emission element  100   b  is filled with the photo-curing resin  31 . Since the P-electrode  19 P and the P-drive electrode  51 , or the N-electrode  19 N and the N-drive electrode  52  are in contact with each other via a number of metal nanoparticles  30  and the drive circuit substrate  50   b  and the micro light emission element  100   b  are firmly in close contact with each other due to the shrinkage of the photo-curing resin  31 , excellent electrical connection can be realized. 
     As such, the P-electrode  19 P and the P-drive electrode  51 , or the N-electrode  19 N and the N-drive electrode  52  are electrically connected by the metal nanoparticles  30 , such that surface layers of the P-electrode  19 P and the N-electrode  19 N and surface layers of the P-drive electrode  51  and the N-drive electrode  52  may have different materials. 
     In this configuration, since the electrode of the bonding surface of the drive circuit substrate  50   b  is formed to be higher than the insulating layer  55 , the substrate-side dummy electrode  53  is disposed outside the pixel region.  1  and thus the size of the space can be controlled. That is, a protrusion portion of the surface on the bonding surface side of the drive circuit substrate  50   b  is an electrode of the P-drive electrode  51 , the N-drive electrode  52 , the dummy electrode  53 , or the like, and the recess portion is the exposed portion of the insulating layer  55 . In addition, the size of the space can be adjusted depending on the length of the P-electrode  19 P at the light emission element unit  101   b  side and the width of the separation trench  20 . That is, the protrusion portion of the surface on the bonding surface side of the light emission element unit  101   b  side is an electrode of the P-electrode  19 P or the N-electrode  19 N, and the recess portion is the isolation trench  15  including the separation trench  20 . As shown in  FIG. 10B , in a case where the space is reduced, the P-electrode  19 P in a dummy element  110   b  may be elongated so as to reduce the disposition of the separation trench  20 . In parallel, the long substrate-side dummy electrode  53  may be disposed. On the contrary, the separation trench  20  may be disposed densely so as to shorten the P-electrode  19 P in a case where the space becomes large. The short substrate-side dummy electrode  53  may be disposed. As in the first embodiment, the dummy element  110   b  can be used for temporarily fixing the light emission element unit  101   b  by disposing the dummy element  110   b  on an outer periphery portion of the pixel region  1 . In addition, as in the first embodiment, the leakage of the photo-curing resin  31  can be reduced or the infiltration of the photo-curing resin  31  can be uniformized by controlling a width of the space of the dummy element  110   b.    
     Manufacturing Method of Micro Light Emission Element  100   b    
     Next, a manufacturing step of the micro light emission element  100   b  will be described with reference to  FIGS. 11A to 11D . The manufacturing step of the micro light emission element  100   b  is made through the same steps in  FIG. 3A  and  FIG. 3B , and thus will be omitted. As shown in  FIG. 11A , the protection layer  17   b  is deposited, but it is not desirable that the isolation trench  15  is completely buried unlike the first embodiment, and thus a thin film is sufficient. Next, as shown in  FIG. 11B , a P-contact hole  21 P is formed on the mesa  16  and an N-contact hole  21 N is formed on the bottom portion of the isolation trench  15 . The P-contact hole  21 P has a hole shape and reaches the P-electrode layer  10 , and the N-contact hole  21 N also has a hole shape and reaches the N-side layer  11 . As shown in  FIG. 11C , the P-electrode  19   b P and an N-electrode  19   b N are formed by the lift-off method. As an electrode material, for example, gold (Au) is used as a main conductive layer, and nickel (Ni) and platinum (Pt) serving as an adhesive layer or a barrier layer are disposed at lower portion thereof. 
     Next, as shown in  FIG. 11D , the separation trench  20  is formed by etching the protection layer  17   b  of the isolation trench  15  and the compound semiconductor  14 . It is desirable that the separation trench  20  separates the micro light emission element  100   b  individually. The role of the separation trench  20  is the same as in the second embodiment. 
     The manufacturing step is similar to a manufacturing step of the LED in the related art and is simple and is effective in a case where the micro light emission element  100   b  is relatively large. Manufacturing Method of Image Display Device  200   b    
     Next, a manufacturing step of the image display device  200   b  will be described with reference to  FIGS. 12A to 12H . The drive circuit substrate  50   b  is manufactured as shown in  FIG. 12A . The drive circuit substrate  50   b  is formed on a single crystal silicon substrate (wafer) by the ordinary complementary metal-oxide semiconductor (CMOS) process. The surface of the P-drive electrode  51  and the surface of the N-drive electrode  52  on the drive circuit substrate  50   b  side are configured to be higher than the surface of the insulating layer  55 . The wiring material forming the P-drive electrode  51  and the N-drive electrode  52  is, for example, aluminum alloy wiring. 
     Since it is not easy to form the metal nanoparticles as it is on the surface of the substrate with such protrusion portions and recess portions, it is desirable to flatten the surface first, form the metal nanoparticle, and then remove the remaining portion other than the electrode portion. 
     First, as shown in  FIG. 12B , the flattening layer  32  is formed between the P-drive electrode  51  and the N-drive electrode  52  first. Next, as shown in  FIG. 12C , the nanoparticles of palladium are arranged by the method as in the first embodiment. After that, as shown in  FIG. 12C , the flattening layer  32  is removed. The flattening layer  32  is, for example, a resin layer, and can be coated, flattened by etch-back, and dissolved and removed by the solvent. 
     Here, it is desirable that the drive circuit substrate  50   b  is in a wafer state and it is desirable that the micro light emission elements  100   b  and their growth substrate  9  in  FIG. 12E  is a group divided from a wafer for example, where each group corresponds to an image display device  200   b.  The divided group of the micro light emission element  100   b  is referred to as a light emission element unit  101   b.    
     Next, as shown in.  FIG. 12E , the light emission element unit  101   b  is disposed on the silicon surface on which the drive circuit substrate  50   b  and, as shown in  FIG. 12F , the photo-curing resin.  31  is injected. 
     Next, as shown in  FIG. 12G , light is radiated from the growth substrate  9  side to cure the resin, such that the photo-curing resin  31  is cured. In a case where the growth substrate  9  does not transmit light as a silicon substrate, since photo curing is not able to be performed unless the growth substrate  9  is peeled off, it is desirable that the growth substrate  9  can transmit the curing light. By performing the photo curing, the drive circuit substrate  50   b  and the micro light emission element  100   b  are firmly connected to each other, and thus it is easy to perform a subsequent peeling step of the growth substrate ( FIG. 12H ). The peeling of the growth substrate  9  can be realized by the laser lift-off method or the like. By performing heating after peeling the growth substrate  9 , the polymerization of the photo-curing resin  31  is further promoted so as to make electrical connection firmer. At this time, since the growth substrate  9  is peeled off, the thermal stress caused by the difference in coefficient of thermal expansion is greatly released. 
     In this configuration, the same effect as the first embodiment can be obtained. 
     Fourth Embodiment 
     Still another embodiment of the present disclosure will be described below. 
     As shown in  FIG. 13E , the present embodiment is different from the micro light emission element  100  of the first embodiment in that a micro light emission element  100   c  is vertical cavity surface emitting laser (VOSEL) type micro laser element. As compared with the micro LED element, the spectrum of an emission wavelength is narrowed and display with high directivity is possible. 
     Manufacturing Method of Micro Light Emission Element  100   c    
     An example of a manufacturing method of the micro light emission element  100   c  will be described with reference to  FIGS. 13A to 13E .  FIGS. 13A to 13E  are sectional views each showing a manufacturing step of the micro light emission element  100   c.    
     As shown in  FIG. 13A , a first reflection layer  42 , an N-side layer  11   c,  the light emission layer  12 , and the P-side layer  13  are deposited on the growth substrate  9  in this order to form a compound semiconductor  14   c.  The first reflection layer  42  is a distributed Bragg reflector (DBR) which reflects light of an oscillated wavelength and may be a part of the N-side layer  11   c.  The first reflection layer  42  can be formed by stacking a plurality of pairs of an AlxGa(1−x)N layer and a GaN layer in a case where the blue light is emitted using the nitride semiconductor. For example, the first reflection layer  42  includes 20 layers of GaN/AlGaN pair in which a thickness of GaN layer is 46 nm, a thickness of the AlxGa(1−x)N layer is 47 nm, and a total thickness of GaN/AlGaN pair is 93 nm, and a total thickness of the first reflection layer  42  is about 1.8 μm. 
     A transparent electrode layer  44  and a second reflection layer  45  are further deposited on the compound semiconductor  14   c.  The transparent electrode layer  44  is an electrode layer such as indium-tin-oxide (ITO), and a thickness thereof is about 50 nm to 600 nm. The second reflection layer  45  is DBR formed of a dielectric multilayer film. For example, the second reflection layer  45  includes 10 layers of a pair of a TiO 2  thin film (thickness of 36 nm) and a SiO 2  thin film (thickness of 77 nm), and an entire thickness thereof is about 1.1 μm. A reflectance of the second reflection layer to the blue light is higher than a reflectance of the first reflection layer  42 . 
     As shown in  FIG. 13B , after the second reflection layer  45  is laminated, the isolation trench  15  is formed by a photolithography technique and a dry etching technique. The isolation trench  15  is formed by etching a portion of the second reflection layer  45 , a transparent electrode  44 , the P-side layer  13 , the light emission layer  12 , and a part of the N-side layer  11   c.  It is not desirable that a side surface of the isolation trench  15  is greatly inclined unlike the first embodiment. This is because a laser element does not emit light in a horizontal direction, it is not necessary to have reflection surface of the horizontally emitted light. Next, as shown in  FIG. 13C , the isolation trench  15  is buried with the protection layer  17  and the surface is flattened. In addition, as shown in  FIG. 13D , the N-groove  18 N and the P-groove  18 P are formed. The N-groove  18 N reaches the N-side layer  11   c  of the bottom portion of the isolation trench  15  by etching the protection layer  17 . The P-groove  18 P reaches the transparent electrode  44  by etching the protection layer  17  and the second reflection layer  45 . Next, as shown in  FIG. 13E , a P-electrode  19   c P and the N-electrode  19 N are formed. Here, the P-electrode  19   c P is formed above the light emission layer  12 , but it is desirable that the P-electrode  19   c P is not disposed on the center in the region where the light emission layer  12  is present, and is disposed on the outer peripheral portion. This is because the P-electrode  19   c P penetrates the second reflection layer  45 , resulting in inhibition of the light emission by the laser element. 
     By doing so, the P-electrode  19   c P is disposed above the light emission layer  12  and the N-electrode  19 N is disposed on the isolation trench  15 , the P-electrode  19   c P and the N-electrode  19 N are disposed together on the surface which is to be the bonding surface, the surfaces thereof are configured to be made of the same materials and are leveled with the surface of the protection layer  17 . The image display device which is the same as the first embodiment can be configured by bonding the micro light emission element  100   c  to the drive circuit substrate (the same as the drive circuit substrate  50  in the first embodiment). The same effect as the first embodiment can be realized. Furthermore, the present embodiment can achieve an additional effect in that a width of the spectrum of the emission wavelength is narrowed and thus directivity becomes high with respect to the first embodiment. 
     The present disclosure is not limited to the embodiments described above, and various modifications are possible within the scope of claims. The embodiments obtained by combining the technical means disclosed in different embodiments are included in the technical scope of the present disclosure. Further, by combining the technical means disclosed in each embodiment, new technical features can be formed. 
     The present disclosure contains subject matter related to that disclosed in Japanese Priority Patent Application No. 62-678533 filed in the Japan Patent Office on May 31, 2018, the entire contents of which are hereby incorporated by reference. 
     It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.