Patent Publication Number: US-6657420-B1

Title: Accurate ultra-low current generator

Description:
FIELD OF THE INVENTION 
     The present invention is related to and apparatus and method for generating low currents. More particularly, the present invention is related to current generators that accurately generate low currents using switched capacitor techniques. 
     BACKGROUND OF THE INVENTION 
     An accurate current can be generated with an operational amplifier that is arranged in a feedback loop. The operational amplifier (op-amp) is arranged to force a known reference voltage across a known resistor value. The resistor and op-amp are arranged to convert the reference voltage to current. An example current generator circuit ( 400 ) that uses an operational amplifier is illustrated in FIG.  4 . 
     As shown in FIG. 4, current generator circuit ( 400 ) includes an N-type field effect transistor (FET MSF), three resistors (R 41 -R 43 ), and an operational amplifier (AMP 40 ). FET MSF includes a gate that is connected to a control node, a drain that is connected to an output node (OUT), and a source that is connected to a feedback node. Resistor R 41  is connected between the feedback node and ground. Resistors R 42  and R 43  are series connected between a voltage reference terminal (VREF) and ground. Amplifier AMP 40  includes a non-inverting input that is connected to a common node between resistors R 42  and R 43 , an inverting input that is connected to the feedback node, and an output that is coupled to the control node. 
     In operation, a reference voltage (VREF) is applied to the current generator circuit ( 400 ). Resistors R 42  and R 43  operate as a resistor divider that provides a second reference voltage (VR 2 ) in response to the reference voltage (VREF). FET MSF receives a control voltage (VCTL) from the output of amplifier AMP 40  and produces an output current (IOUT). The output current (IOUT) flows through resistor R 41 , which produces a feedback voltage (VFB). Amplifier AMP 40  provides the control voltage (VCTL) in response to a comparison between the second reference voltage (VR 2 ) and the feedback voltage (VFB). Amplifier AMP 40  provides control of FET MSF such that output current IOUT is determined by the second reference voltage (VR 2 ) divided by the resistance of R 41 . 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a method and apparatus for accurately generating low currents using switched capacitor techniques. The current generator includes a reference voltage generator that provides a reference signal to a switched capacitor integrator. In one example, the reference circuit includes a switched capacitor divider. The switched capacitor integrator circuit produces a voltage ramp in response to the reference signal and other timing signals. The rate of the voltage ramp is proportional to the ratio of capacitors in the switched capacitor integrator and a clock frequency that is associated with the timing signals. A feedback circuit impresses the voltage ramp across an output capacitor circuit that has a very low capacitance value. The capacitor is arranged to differentiate the voltage ramp to produce an accurate low current. The switched capacitor design is suitable for integration in a monolithic integrated circuit. The integrator and the feedback stage are periodically reset. 
    
    
     A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detailed description of illustrative embodiments of the invention, and to the appended claims. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram of an exemplary current generator; 
     FIG. 2 is a detailed schematic diagram of an exemplary current generator; 
     FIG. 3 is a partial schematic diagram of an exemplary current generator, which is in accordance with the invention. 
     FIG. 4 is a schematic diagram of a conventional current generator. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meaning of “a,” “an,” and “the” includes plural reference, the meaning of “in” includes “in” and “on.” The term “connected” means a direct electrical connection between the items connected, without any intermediate devices. The term “coupled” means either a direct electrical connection between the items connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, or data signal. 
     The present invention is directed at accurately producing a very low current using switched capacitor techniques. A voltage ramp signal is produced in response to a reference signal using a switched capacitor integrator. A voltage-to-current converter circuit receives the voltage ramp signal. An output capacitor in the voltage-to-current converter is arranged to produce a controlled current in response to the voltage ramp signal. The value of the output capacitor and the rate of the voltage ramp signal are chosen such that a very small capacitor may be utilized with a relatively slow voltage ramp. In one example, the capacitor and voltage ramp are arranged to provide an accurate output current on the order of 10 pA. The small capacitors and switched capacitor design are suitable for use in an integrated circuit. 
     FIG. 1 is a schematic block diagram of an exemplary current generator ( 100 ). Current generator  100  includes a reference circuit ( 102 ), a switched capacitor integrator circuit ( 104 ), and a voltage-to-current converter circuit ( 106 ). Reference circuit  102  has an output that is coupled to an input of switched capacitor integrator circuit  104 . Switched capacitor integrator circuit  104  has another input that is arranged to receive a first control signal (CTL 1 ), and an output that is coupled to an input of voltage-to-current converter circuit  106 . Voltage-to-current converter circuit  106  has another input that is arranged to receive a second control signal (CTL 2 ), and an output that is arranged to provide an output signal (IOUT). 
     In operation, reference circuit  102  produces a reference signal (VX). Switched capacitor integrator circuit  104  produces a ramp signal (VRAMP) in response to the reference signal (VX) and the first control signal (CTL 1 ). Voltage-to-current converter  106  produces the output signal (IOUT) in response to the ramp signal (VRAMP) and the second control signal (CTL 1 ). The output current signal (IOUT) is related to the rate of the ramp signal (VRAMP). 
     Reference circuit  102  may be any voltage reference that is suitable for switched capacitor integrator circuit  104 . In one example, reference circuit  102  includes a band-gap type of reference circuit that provides a voltage on the order of 1.25V. In another example, the reference circuit  102  includes a switched capacitor circuit that operates as a voltage-divider. In still another example, the reference circuit includes a buffer that is arranged to isolate reference circuit  102  from the switched capacitor integrator circuit  104 . 
     The first and second control signals (CTL 1 , CTL 2 ) correspond to one or more control signals that are necessary to control switch timing of switched capacitor integrator  104  and voltage-to-current converter  106 . In one example, the first control signal includes a reset control line, and at least two clock signals. The reset control line may be utilized to reset the integrator, while the clock signals may be used to control the switch timing in the integrator. The clock signals may be related to one another such as inverses of one another. The clock signals may also be non-overlapping clock signals. The clock signals may correspond to different phases that are derived from a single clock signal. Second control signal CTL 2  may similarly include clock signals and reset control for voltage-to-current converter  106 . 
     Ramp signal VRAMP corresponds to a voltage signal that increases gradually over time. In one example, the voltage of VRAMP increases at a rate of 1 volt per second (a slow ramp). 
     Voltage-to-current converter circuit  106  produces output signal IOUT in response to ramp signal VRAMP and second control signal CTL 2 . Signal IOUT has a current that is proportional to the rate at which the voltage of VRAMP increases over time as will be discussed in further detail with reference to FIG.  2 . 
     FIG. 2 is a schematic diagram of an exemplary current generator circuit ( 200 ) that is in accordance with the present invention. Similar to current generator circuit  100  shown in FIG. 1, current generator circuit  200  includes a reference circuit ( 102 ), a switched capacitor integrator circuit ( 104 ), and a voltage-to-current converter circuit ( 106 ). Current generator circuit  200  also includes a switch control logic circuit ( 202 ). 
     Switch control logic circuit  202  has an output that is coupled to node N 208  and another output coupled to node N 209 . The output at node N 208  corresponds to a first clock signal (Ø 1 ), while the output at node N 209  corresponds to a second clock signal (Ø 2 ). 
     Reference circuit  102  includes a voltage source (VREF), two switches (SW 1 -SW 2 ), and two capacitors (C 1 , C 2 ). Voltage source VREF is coupled to node N 210 . Capacitor C 1  is coupled between node N 201  and node N 202 . Capacitor C 2  is coupled between node N 200  and node N 202 . Node N 200  is connected to ground. Switch SW 1  is coupled between node N 210  and N 201 . Switch SW 2  is coupled between node N 201  and N 200 . Switch SW 1  is arranged to selectively couple node N 210  to node N 201  in response to the first clock signal (Ø 1 ). Switch SW 2  is arranged to selectively couple node N 201  to node N 200  in response to the second clock signal (Ø 2 ). 
     Switched capacitor integrator circuit  104  includes three switches (SW 3 -SW 5 ), two capacitors (C 3 -C 4 ), and an amplifier circuit (AMP 1 ). Switch SW 3  is coupled between node N 202  and node N 200 . Switch SW 4  is coupled between node N 203  and node N 200 . Switch SW 5  is coupled between node N 203  and node N 204 . Capacitor C 3  is coupled between node N 202  and node N 203 . Capacitor C 4  is coupled between node N 204  and node N 205 . Amplifier AMP 1  has an inverting input that is coupled to node N 204 , a non-inverting input that is coupled to node N 200 , and an output that is coupled to node N 205 . Switch SW 3  is arranged to selectively couple node N 202  to node N 200  in response to the second clock signal (Ø 2 ). Switch SW 4  is arranged to selectively couple node N 203  to node N 200  in response to the first clock signal (Ø 1 ). Switch SW 5  is arranged to selectively couple node N 203  to node N 204  in response to the second clock signal (Ø 2 ). 
     Voltage-to-current converter circuit  106  includes a transistor (M 1 ), an amplifier circuit (AMP 2 ), and a capacitor (C 0 ). Amplifier AMP 2  has a non-inverting input that is coupled to node N 205 , an inverting input that is coupled to node N 207 , and an output that is coupled to node N 211 . Transistor M 1  has a gate that is coupled to node N 211 , a source that is coupled to node N 207 , and a drain that is coupled to node N 206 . Capacitor C 0  is coupled between node N 207  and node N 200 . 
     During operation, switch control logic  202  produces clock signals Ø 1  and Ø 02 . In one example, the first clock signal (Ø 1 ) corresponds to an inverse of the second clock signal (Ø 2 ). In another example, the first clock signal (Ø 1 ) and the second clock signal (Ø 2 ) correspond to a set of non-overlapping clock signals. For proper operation of the switched capacitor circuit employed in current generator circuit  200 , switch SW 1  and SW 4  cannot be active at the same time that switches SW 2 , SW 3  and SW 5  are active, and vice-versa. 
     The operation of current generator circuit  200  has two phases of operation corresponding to the clock signals. During phase Ø 2 , switches SW 2 , SW 3 , and SW 5  are closed and the remaining switches are open. The operating phases for current generator circuit  200  are discussed as follows below. 
     Phase Ø 1  Operation 
     During phase Ø 1 , switches SW 1  and SW 4  are closed, and switches SW 2 , SW 3 , and SW 5  are open. 
     The voltage source (VREF) is coupled to capacitor C 1 . Capacitors C 1 , C 2  and C 3  are arranged as a capacitive voltage divider such that a voltage (VX) is produced at node N 202  in response to the voltage source (VREF). The reference voltage (VX) is determined by the voltage source and the capacitor values such that:              VX   =     VREF   ·     [     C1     (     C1   +   C2   +   C3     )       ]               (   I   )                         
     At the end of phase Ø 1 , capacitor C 3  is fully charged to VX. Thus, capacitor C 3  stores a charge (Q 3 ) corresponding to: 
     
       
           Q   3 = VX·C   3   (II) 
       
     
     Substituting equation (I) into equation (II) yields:              Q3   =     VREF   ·     [       C1   ·   C3       (     C1   +   C2   +   C3     )       ]               (   III   )                         
     Since switch SW 5  is open, amplifier AMP 1  and capacitor C 4  maintain a relatively constant output voltage (VRAMP) at node N 205  during phase Ø 1 . 
     Phase Ø 2  Operation 
     During phase Ø 2 , switches SW 1  and SW 4  are open, and switches SW 2 , SW 3 , and SW 5  are closed. 
     The voltage source (VREF) is decoupled from capacitor C 1 , and capacitors C 1  and C 2  are fully discharged to ground through switches SW 2  and SW 3 . The charge that was previously stored on capacitor C 3  (i.e., C 3 ·VX) is transferred to capacitor C 4  such that AMP 1 , and capacitors C 3  and C 4  operate as an integrator. A current flows through capacitor C 3  when the capacitor is coupled to ground through switch SW 3 . The current flow (I) through C 3  is determined by the change in charge in capacitor C 3 :              I   =       Δ                 Q3       Δ                 t               (   IV   )                         
     Substituting equation (II) into equation (IV) yields:              I   =       (     VX     Δ                 t       )     ·   C3             (   V   )                         
     All of the current (I) that is flowing through capacitor C 3  must also flow through capacitor C 4 . The current in capacitor C 4  is determined by the change in the voltage (VC 4 ) on capacitor C 4  as:              I   =     C4   ·     (       Δ                 VC4       Δ                 t       )               (   VI   )                         
     Solving for the change in voltage on capacitor C 4  yields:                Δ                 VC4     =         (     1   C4     )     ·   Δ                   t             (   VII   )                         
     Substituting equation (V) into equation (VII) yields:                Δ                 VC4     =     VX   ·     (     C3   C4     )               (   VIII   )                         
     The output voltage (VRAMP) from amplifier AMP 1  will correspond to an initial ramp voltage (VRAMP i ) at the end of each phase Ø 1  clock cycle. During the phase Ø 2  clock cycle, the ramp voltage will increase by an amount corresponding to equation (VIII). The ramp signal (VRAMP) may thus be determined by the following equation: 
     
       
           VRAMP=VRAMP   i   +ΔVC   4   (IX) 
       
     
     Combining equation (IX) and (VIII) yields:              VRAMP   =       VRAMP   i     +     VX   ·     (     C3   C4     )                 (   X   )                         
     Finally, combining equation (X) and (I) yields:              VRAMP   =       VRAMP   i     +     VREF   ·     (     C3   C4     )     ·     [     C1     (     C1   +   C2   +   C3     )       ]                 (   XI   )                         
     Amplifier circuit AMP 2  receives the ramp signal (VRAMP) from node N 205  and provides a control signal to node N 211 . Transistor M 1  is configured as a follower circuit such that the voltage at node N 207  will follow the ramp signal (VRAMP). Capacitor C 0  will conduct a current (IOUT) as the ramp signal increases such that:              IOUT   =     CO   ·     (       Δ                 VRAMP       Δ                 t       )               (   XII   )                         
     The time period associated with the voltage ramp is determined by the frequency (f) of switching in the switched capacitor circuits. Since f=1/Δt, the output current is determined as:              IOUT   =     CO   ·     (     C3   C4     )     ·     [     C1     (     C1   +   C2   +   C3     )       ]     ·   f   ·   VREF             (   XIII   )                         
     A variety of control parameters may be adjusted to change the output current. First, the ratio of C 1  and (C 1 +C 2 +C 3 ) may be adjusted to scale the source voltage (VREF) and produce an appropriate reference voltage (VX) for integration. Second, the reference voltage (VX) is scaled by the ratio of capacitors C 3  and C 4  to adjust the step size of the ramp signal (VRAMP). Thus, the rate of the ramp signal can be changed by either the frequency (f) or the ratio C 3 /C 4 . Lastly, the overall output current is scaled by the value of capacitor C 0 . 
     In one example, 
     
       
           C   1 = C   3 ,  C   2 =10 ·C   1 ,  C   4 =100 ·C   1 , and 
       
     
     
       
           VRAMP=VREF·f/ 1200 
       
     
     In this example, VRAMP increases by VREF/1200 in each clock cycle. 
     In another example, 
     
       
           VREF =1.2V, 
       
     
     
       
           f =100 KHz, 
       
     
     
       
           C   0 =200 fF,  C   1 = C   3 ,  C   2 =10 ·C   1 ,  C   4 =100 ·C   3 , and 
       
     
     
       
           IOUT =10 pA. 
       
     
     As illustrated in the above discussion and examples, very small accurate currents can be achieved with the present invention. The capacitors in current generator  200  are related to one another as ratios. By arranging the ratios carefully, the output current (IOUT) is controlled. A variety of trimming techniques may be employed to change the designated output current as may be desired. The capacitor ratios may be dynamically selectable. For example, the ratio of C 3  and C 4  may be used to control the step size of the ramp, which in turn will control the output current to increase. A set of switches may be arranged to select one or more capacitors in parallel and/or series combination as capacitor C 3  and/or C 4 . Thus, any desired ratio for C 3 /C 4  may be achieved by activating the appropriate switches. The selection may be designated by a memory such as a register. Other capacitors may also be dynamically selected to adjust the overall output current. Alternatively, the clock frequency can be changed to control the ramp signal. 
     FIG. 3 is a schematic diagram illustrating a partial view of a current generator circuit ( 300 ) that is accordance with the present invention. The partial view shown in FIG. 3 operates substantially similar to that illustrated in FIG.  2 . Current generator  300  includes switched capacitor integrator circuit  104 , voltage-to-current converter circuit  106 , and reset logic circuit X 310 . Switched capacitor integrator circuit  104  includes switch SW 301 , capacitor C 4 , and amplifier AMP 1 . Voltage-to-current generator circuit  106  includes amplifier AMP 2 , transistors M 1  and M 301 , a current source (Isink), switches SW 302 -SW 303 , and capacitor C 0 . 
     Switch SW 301  is coupled between node N 300  and node N 301 , and has a control termninal that is coupled to node N 307 . Node N 300  is connected to ground. Capacitor C 4  is coupled between node N 301  and node N 302 . Amplifier AMP 1  has a non-inverting input that is coupled to node N 300 , an inverting input that is coupled to node N 301 , and an output that is coupled to node N 302 . Switch SW 302  is coupled between nodes N 300  and N 302 , and has a control terminal that is coupled to node N 307 . Amplifier AMP 2  has an inverting input that is coupled to node N 303 , a non-inverting input that is coupled to node N 302 , and an output that is coupled to node N 304 . Transistor M 301  has a gate that is coupled to node N 304 , a source that is coupled to node N 303 , and a drain that is coupled to node N 313 . Current source Isink is coupled between nodes N 300  and N 303 . Transistor M 1  has a gate that is coupled to node N 304 , a source that is coupled to node N 303 , and a drain that is coupled to node N 313 . Capacitor C 0  is coupled between nodes N 300  and N 306 . Switch SW 303  is coupled between node N 300  and node N 306 , and has a control terminal that is coupled to node N 307 . 
     Reset logic circuit X 310  includes comparator CMP 1 , NOR gate X 302 , latch X 306 , and inverter X 305 . Latch X 306  includes NOR gates X 303  and X 304 . Comparator CMP 1  has an inverting input that is coupled to node N 303 , a non-inverting input that is coupled to node N 308 , and an output that is coupled to node N 314 . NOR gate X 302  has an input that is coupled to node N 314 , another input that is coupled to node N 309 , and an output that is coupled to node N 310 . NOR gate X 303  has an input that is coupled to node N 310 , another input that is coupled to node N 312 , and an output that is coupled to node N 311 . NOR gate X 304  has an input that is coupled to node N 309 , another input that is coupled to node N 311 , and an output that is coupled to node N 312 . Inverter X 305  is coupled between nodes N 311  and N 307 . 
     In operation, switched capacitor integrator circuit  104  and voltage-to-current circuit  106  each function substantially the same as in current generator  200 , with the addition of switches SW 301 , SW 302 , and SW 303 . Switch SW 301 , switch SW 302 , and switch SW 303  are arranged to operate as reset switches. Switches SW 301 -SW 303  are closed when a reset signal (RST) is active. The logical level of signal RST is determined by reset logic circuit X 310 . Switches SW 301 -SW 303  are reset periodically in response to signal RST such that the integration capacitor (C 4 ) and the output capacitor are completely discharged to ground. 
     Amplifier AMP 2  is arranged to simultaneously drive transistors M 301  and M 1 . Transistor M 1  is a source follower that is used in conjunction with amplifier AMP 2  to impress ramp signal VRAMP on capacitor C 0 . Transistor M 301  and current source Isink are arranged to provide negative feedback to amplifier AMP 2 . Transistor M 301  also allows amplifier AMP 2  to have improved stability since the feedback voltage at node N 303  is not affected by transient events in capacitor C 0 . 
     Reset logic circuit X 310  determines when ramp signal VRAMP should be reset. Comparator X 301  compares source voltage VREF to the voltage at node N 303 . The voltage at node N 303  follows ramp voltage VRAMP. The reset signal (RST) is forced to be a low logic signal when the ramp signal (VRAMP) is below VREF. Comparator CMP 1  provides a low logic signal to NOR gate X 302  when the ramp voltage exceeds VREF (or alternatively another predetermined level), enabling the latch. Signal Ø 1  is also coupled to NOR gate X 302 . NOR gate X 302  will only produce an output with a high logical level when the phase Ø 1  is not active and the voltage at node N 303  exceeds VREF. The output of NOR gate X 302  acts as a set signal for the latch (X 306 ), while signal Ø 1  acts as an enable signal. When the output of NOR gate X 302  is a high logic level, the logical level of RST will be high until the next rising edge of signal Ø 1  (i.e., a reset logic pulse). 
     The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.