Patent Publication Number: US-4367421-A

Title: Biasing methods and circuits for series connected transistor switches

Description:
The field of the present invention relates generally to switching circuits, and more specifically to a method and circuit wherein a plurality of relatively low voltage transistors are connected to switch an operating voltage having a substantially higher level than the voltage rating of each one of the individual switching transistors. 
     In one embodiment of the present invention, a plurality of N (where N is an integer greater than one) switching transistors are protected from excessive inverse voltage across paths having main current paths connected in series between opposite terminals of a voltage source by (1) dividing the voltage between the terminals into a plurality of (N-1), each bias voltage having a predetermined level; (2) applying the (N-1) bias voltages to the common connections between the main current paths of the N switching transistors, respectively, for maintaining the voltage across each main current path at a level no greater than the path inverse voltage rating, when said N switching transistors are non-conductive or turned off; and (3) limiting the level of voltage across the main current paths of the N switching transistors to the inverse voltage ratings, respectively, regardless of the conduction states of the N transistors. 
    
    
     In the drawing, wherein like items are identified by the same reference numerals, wherein: 
     FIG. 1 is a schematic diagram of my prior invention wherein a metallic oxide semiconductor field effect (MOSFET) transistor supplies base current to a bipolar transistor and has a main current path in a negative feedback path between the collector and base electrodes of the bipolar transistor to improve the transient response and capability and turn-off time of the bipolar transistor; and 
     FIGS. 2 through 8 are circuit schematic diagrams of different embodiments of my present invention, respectively. 
    
    
     In FIG. 1, an NPN bipolar transistor 1 includes a collector electrode connected to one terminal of a load 3 and a drain (D) electrode of a field effect transistor 5. The other terminal of the load 3 is connected to a power terminal 7 for receiving an operating voltage +E. Also, the field effect transistor (hereinafter referred to as an FET) 5 includes a source (S) electrode connected to the base electrode of the bipolar transistor 1, and a gate (G) electrode connected to an input terminal 9 for receiving a control signal. A low value resistor 11 is connected between the base and emitter electrodes of the bipolar transistor 1, to ensure rapid turn off of transistor 1 from a conductive state in response to zero bias at the bipolar base electrode. The emitter of transistor 1 is connected to terminal 13 for receiving a source of reference potential, in this example, ground. The switching circuit is operated by applying a positive going control signal, typically +15 volts to input terminal 9 for turning on transistor 5, causing the impedance of the main current path of transistor 5 between the source and drain thereof, to be substantially reduced, permitting current to flow from terminal 7, through resistor 3 and the main current path of transistor 5, into the base electrode of transistor 1, causing transistor 1 to turn on rapidly. Some of the current flowing through transistor 5 also flows through resistor 11 to ground. Once turned on, transistor 1 is substantially prevented from going into a saturated conduction state because of the negative feedback path provided by the main current path of transistor 5 between the collector and base electrodes of transistor 1. Also, this negative feedback path improves the transient capability of transistor 1, by increasing the magnitude of the base current thereto whenever a transient increase in the magnitude of current flowing into the collector electrode of transistor 1 causes the voltage across the collector and emitter electrodes (V CE ) to increase. In this manner, transistor 1 is substantially operated near the edge of saturation but not in saturation, assuming that the impedance of the load 3 is such that transistor 1 could be operated in a saturated state where it not for negative feedback provided. The operation of this switching circuit is described in greater detail in my copending application, Ser. No. 41,008, filed on May 21, 1979, for VMOS/BIPOLAR POWER SWITCH. 
     In FIG. 1, transistor 5 is shown as a MOSFET transistor. One advantage of using a MOSFET transistor is that such transistors have high input impedance, which provides a very high gain for the circuit of FIG. 1. However, in relatively high power switching applications, where the level of +E is necessarily a relatively high voltage, transistor 5 must be a power MOSFET transistor, such as a VMOS or DMOS, for example, which has the disadvantage of presently being expensive, and typically has a relatively high &#34;on resistance&#34; with present technology, causing undesirable power dissipation when conducting. 
     As shown in FIG. 2, the present inventor discovered that he could improve upon his switching circuit of FIG. 1, by connecting the main source drain current paths of two field effect transistors 15,17, respectively, in series, and connecting them as shown for providing the function of transistor 5 of FIG. 1, and at the same time providing appropriate biasing as described infra, for permitting these transistors 15,17 to have typically half the inverse voltage rating of transistor 5 of FIG. 1. For example, when the switching circuit of FIG. 1 is turned off, by removing the control signal from input terminal 9, typically by reducing the magnitude of the control signal to ground, in this example, +E volts is applied across the main current path (between the drain and source electrodes thereof) of transistor 5. Accordingly, transistor 5 must have a voltage rating of at least +E volts. In the first embodiment of the invention, as illustrated in FIG. 2, a resistive voltage divider including resistors 19 and 21 provides a bias voltage V A  at the common connection of the main current paths of transistors 15 and 17. When transistors 15 and 17 are turned off, the voltage ratings of transistors 15 and 17 need only be equal to V A  and (E-V A ), respectively. In the preferred embodiment, resistors 19 and 21 are of equal value, and have substantially higher resistance than load 3, so the value of V A  is about equal to 1/2E. In this latter example, the voltage ratings of transistors 15 and 17 are identical and equal to at least 1/2E volts, reducing the need for different transistor types. Resistor 23 to prevents the voltage between the gate G and source S electrodes of transistor 17 from floating with respect to the reference potential at terminal 13. Capacitor 25, as shown in phantom, represents the capacitance due to parasitic and lead capacitance at point A; however, in certain applications capacitor 25 is provided externally, as described infra. Blocking diode 27 prevents current flow from the output point of the voltage divider 19,21 to input terminal 9. 
     Operation of the circuit of FIG. 2 is now described. A positive going control signal is applied to input terminal 9, causing transistor 15 to turn on, substantially reducing the impedance of the main current path of transistor 15, thereby permitting base current to flow into the base electrode of bipolar transistor 1. In response to the flow of base current, transistor 1 turns on so there is a substantial reduction of the impedance of its main current path, causing a substantial drop in the voltage at point B. This drop in voltage at point B is rapid enough to prevent excessive inverse voltage from being applied across transistor 17 after turn-on of transistor 15. As the level of the voltage at point B drops, the voltage V A  at point A drops correspondingly, causing diode 27 to become forward biased when the voltage V A  drops to at least one diode drop below the level of the control voltage at input terminal 9. Typically, assuming that the level of the control voltage is +15 volts, diode 27 becomes forward biased when the voltage V A  drops to about 14.4 volts, and when the voltage V A  drops an additional 5 or 6 volts, that is, to about 8 volts, the voltage across the gate and source electrodes of transistor 17 is about +8 volts with respect to the gate, causing transistor 17 to turn on, completing the turn-on cycle for the circuit of FIG. 2. The timing of the turn-on of the circuit of FIG. 2 is partly dependent upon the value of the capacitor 25. When this circuit is turned off, capacitor 25 charges to a voltage level of thereacross of V A  volts, via the charge current conduction path provided by load 3 and resistor 19. When transistor 15 initially turns on, capacitor 25 discharges through the discharge current path provided by the on-resistance of transistor 15 in series with the parallel combination of resistor 11 and the input impedance of transistor 1. Accordingly, the rate of discharge of capacitor 25 is determined by a time constant equal to the product of the value of capacitor 25 times the value of the resistance provided by the on-resistance of transistor 15 in series with the parallel combination of resistor 11 and the input impedance of transistor 1. Since the value of capacitor 25 is typically very small, the capacitor discharges very quickly. In certain applications, it may be desirable to include additional capacitance by providing a discrete capacitor for capacitor 25 the capacitance of the discrete capacitor is additive to the parasitic capacitances to obtain a desired turn-on time for the circuit of FIG. 2. When the control signal applied to terminal 9 is removed or its level is reduced, for example, to ground transistor 15 responds by turning off so there is a substantial increasing of the impedance of its main current path, interrupting the flow of base current to transistor 1, causing the latter to turn off and the voltage at point B to approach +E volts, and the bias voltage V A  to correspondingly increase to its predetermined value for the off condition of the circuit of FIG. 2. As transistor 1 so turns off, diode 27 again becomes backbiased, and capacitor 25 charges to follow the rise in voltage of V A  ; the charging time constant being equal to the product of the value of capacitor 25 times the sum of the resistive values of resistor 19 and load impedance 3. Also, turn off of transistor 15 interrupts the flow of current through transistor 17, which is substantially turned off at the same time as transistor 15. Because transistors 15 and 17 have a much faster turn-off time than transistor 1 and capacitor 25 has a very small value, the voltage at point A very quickly rises in correspondence with the increase in voltage at point B as transistor 1 turns off, ensuring that the inverse voltage ratings of transistors 15 and 17 are not exceeded. 
     As described above, in FIG. 2, transistors 15 and 17 provide the function of transistor 5 of FIG. 1. The circuit of FIG. 2 has an advantage over that of FIG. 1 because it employs lower inverse voltage rated transistors 15,17 having an on-resistance substantially lower than that of transistor 5, assuming similar conditions of operating voltage and load impedance. Also, the lower inverse voltage rated transistors 15, 17, tend to be less expensive than the higher voltage transistor 5 required in the circuit of FIG. 1. Alternatively, assuming that transistors 5, 15, and 17 are identical types, the circuit of FIG. 2 can be used to switch as operating voltage +E having a value twice the level of the operating voltage in the circuit of FIG. 1. In other words, the circuit of FIG. 2 is capable of switching higher voltages than the circuit of FIG. 1, assuming that the control transistor is identical in type to the control transistors 15 and 17. Transistors 15 and 17 are not necessarily MOSFET transistors, but can be bipolar transistors so long as the bipolar transistors have substantially faster switching times than output transistor 1. However, the use of bipolar transistors for the control transistors 15,17 in place of power MOSFETS would substantially reduce the input impedance of this switching circuit, and correspondingly the power gain of the circuit. 
     In FIG. 3, a second embodiment of the invention, the first embodiment of the invention of FIG. 2 is expanded to include plural N control or switching transistors Q 1  through Q N  to provide the function of transistor 5 of FIG. 1. As shown, resistive voltage dividers R 1 , R 1  &#39; through R.sub.(N-1), R&#39;.sub.(N-1) provide bias voltages V 1  through V.sub.(N-1) at the common connections between the control transistors Q 1  through Q N , respectively. The blocking diodes 27 and resistors 23 provide the same functions as described for the like components of FIG. 2. Capacitors C 1  through C.sub.(N-1) represent parasitic capacitance as previously described for the circuit of FIG. 2. Capacitor C.sub.(N-1) may, in some applications, be a discrete predetermined capacitance externally connected to the circuit to provide a desired switching time characteristic for the circuit of FIG. 3. Load 3 is connected between output terminals 7 and 29, and the reference voltage terminal 13 is receives a reference voltage E 2 , in this example, ground. However, if E.sub. 2 is not at ground potential, the maximum voltage applied across the serial string of the control transistors Q 1  through Q N  is equal to the value (E 1  -E 2 ) when the circuit of FIG. 3 is inoperative, that is, when all of the transistors of the circuit are turned off. The voltage E 3  at output terminal 29 is substantially equal to +E 1  when the output transistor 1 and control transistors Q 1  through Q N  are turned off, and has a level equal to the voltage drop across the collector and emitter electrodes of output transistor 1 when this transistor is turned on, assuming that terminal 13 is connected to ground. Accordingly, assuming that E 2  is at ground potential, the minimum voltage rating for control transistor Q 1  is (E 1  -V 1 ), for transistor Q 2  is (V 1  -V 2 ), and proceeding down the chain for transistor Q N  is V.sub.(N-1). In most applications, it is economically expedient for transistors Q 1  through Q N  to have equal voltage ratings, whereby the voltage rating is as shown in Equation 1 below: 
     
         Voltage Rating=(E.sub.1 /N)) volts for each Q.sub.N        (1) 
    
     Again assuming equal voltage ratings for transistors Q 1  through Q N , the bias voltages V 1  through V.sub.(N-1) are determined from Equation 2, as follows: 
     
         V.sub.K =E.sub.1 1-(K/N) volts,                            (2) 
    
     where N is at least 2, and K represents the position of the bias voltage point in the serial chain, e.g., K=1 for V 1  ; K=2 for V 2  ; -K=(N-1) for V.sub.(N-1). 
     In operation of the circuit of FIG. 3, when a control signal is applied to input terminal 9, transistor Q N  turns on, permitting base current to flow in transistor 1, causing the latter to turn on so there is an impedance drop between its collector and emitter electrodes, causing the voltage +E 3  at terminal 29 to rapidly decrease, thereby preventing excessive inverse voltage from being applied across transistors Q 1  through Q.sub.(N-1) after the turn-on of Q N . Also, there is a substantial reduction in the voltage V.sub.(N-1) upon turn-on of transistor Q N , permitting transistor Q.sub.(N-1) to turn on when the voltage at its gate exceeds V.sub.(N-1) by a predetermined value typically +8 volts. Proceeding up the chain of transistors to Q 1 , these transistors turn on sequentially in a similar manner, for completing the turn-on of the switching circuit. 
     Another embodiment of the invention (FIG. 4) includes NPN bipolar transistors Q 1  &#39; through Q N  &#39;  which functions and are connected similarly to the MOSFET transistors Q 1  through Q N  of FIG. 3. has a Resistor 23 is connected between the base and emitter electrodes of the Q&#39; N  bipolar transistor of FIG. 4, for ensuring fast turn-off of this transistor. The circuit of FIG. 4 operates substantially in the same manner as the circuit of FIG. 3, except that the circuit of FIG. 4 has a much lower power gain and input impedance than the circuit of FIG. 3. 
     The present inventor has recognized that in certain applications it is desirable to eliminate the NPN bipolar output transistor 1 of FIG. 3, in a manner permitting field only effect transistors Q 1  through Q N  to switch power to and from the load 3. As shown in FIG. 5, the resistive voltage divider networks of FIG. 3 are replaced by Zener diode unidirectional controlled voltage breakdown devices Z 1  through Z N . Zener diodes Z 1  through Z N  form a voltage divider network between output terminal 29 and reference voltage terminal 13 for providing the bias voltages V 1  &#39; through V&#39; N-1 ), when the switching transistors Q 1  through Q N  are turned off or non-conductive. Also, the breakdown voltage ratings of the Zener diodes are chosen to be no greater than the inverse voltage rating of the main current path of the particular switching transistor they are connected across. Zener diodes 31 are polarized so the anodes and cathodes thereof are respectively connected to the drains and gates of transistors Q 1  -Q N  to conduct current in the same direction as the main current paths of the transistors they are connected across whenever the diode breakdown voltage is exceeded. Also, an individual Zener diode 31 is connected between the gate and source electrodes of each one of the transistors Q 1  through Q N , for protecting these field effect transistors from excessively high levels of input voltage or gate voltage. 
     In operation of the circuit of FIG. 5, a control signal is applied to input terminal 9, first causing transistor Q N  to turn on, substantially reducing the level of voltage at point C, causing the voltage differential between the gate and source electrodes of field effect transistor Q.sub.(N-1) to increase and turn on this transistor. As turn on proceeds in this manner up the chain of serially connected field effect transistors to transistor Q 1 , the voltage differentials between the gate and source electrodes similarly increases, until all of these transistors are turned on to permit current to flow through the load 3. This progression occurs very rapidly because of the relatively high switching speeds of the field effect transistors Q 1  through Q N . If at any time during this turn-on cycle the inverse voltage rating of any particular one of these field effect transistors is exceeded, the associated Zener diode Z 1  through Z.sub.(N-1) breaks down to limit the voltage across the main current path of the particular field effect transistor to a safe value until such time that the overvoltage condition is removed. In this manner, the Zener diodes Z 1  through Z N , provide via the reverse bias impedance and voltage breakdown level characteristics thereof, both voltage limiting of the level of voltage across the main current paths of the field effect transistors Q 1  through Q N , and appropriate levels of bias voltages V&#39; 1  and through V&#39;.sub.(N-1) for ensuring that the inverse voltage ratings of the field effect transistors are not exceeded when these transistors are all turned off. 
     The characteristics of the modified circuit of FIG. 5 are improved by employing the circuit of FIG. 6, to include the NPN bipolar transistor 1, having its base emitter path shunted by resistor 11, which is connected in series with the circuitry between terminals 7 and 13, FIG. 5, in turn connected in shunt with the base and collector of transistor 1. More particularly, the alternative embodiment of the invention of FIG. 6 provides greater power gain and a reduced level of on-resistance in comparison to the circuit of FIG. 5, for reasons previously explained for other embodiments of the invention. 
     FIG. 7 is an alternative embodiment of the invention in comparison to the circuit of FIG. 5. In FIG. 7, bipolar transistors Q 1  through Q N  are used instead of field effect transistors, respectively, as in FIG. 5. In FIG. 7, input resistors 23 are connected across the base and emitter electrodes of each one of the bipolar transistors. The circuit of FIG. 7 in comparison to the circuit of FIG. 5 has a substantially reduced input impedance, but offers the advantage of a substantially lower on-resistance because of the use of bipolar transistors, and higher power handling capability in view of present technology. 
     The another embodiment of the invention illustrated in FIG. 8 is a bipolar dual to the FET circuit illustrated in FIG. 6, wherein the circuit of FIG. 7 replaces the circuit of FIG. 5. In comparison to the circuit of FIG. 7, the circuit of FIG. 8 offers increased input impedance and power gain via the addition of bipolar transistor 1.