Patent Publication Number: US-11387755-B1

Title: Control system connected to an arresting gear system having an outer control loop and a plurality of inner current control loops

Description:
RELATED APPLICATION 
     This application is a Continuation of U.S. Ser. No. 16/505,511 filed Jul. 8, 2019, which is a Continuation-in-Part of U.S. Ser. No. 14/825,712 filed Aug. 13, 2015, now U.S. Pat. No. 10,348,229, which claims the benefit of U.S. Ser. No. 62/043,996 filed Aug. 29, 2014. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of Invention 
     The present invention relates generally to the field of current controllers. More specifically, the present invention is related to a control system connected to an arresting gear system having an outer control loop and a plurality of inner current control loops. 
     Discussion of Related Art 
     The paper to P. C. Kraus titled “Method of Multiple Reference Frames Applied to the Analysis of Symmetrical Induction Machinery” discusses the mathematics and physical implementation of using multiple reference frames for control of motors. 
     The paper to P. Xiao titled “Multiple Reference Frame-based Control of Three-Phase PWM Boost Rectifiers under Unbalanced and Distorted Input Conditions” discusses implementation of multiple reference frames for control. However, Xiao&#39;s implementation is based on straightforward application of the fundamental ideas in the above-referenced paper to Kraus. 
     The U.S. Patent to Sepe, Jr. (U.S. Pat. No. 7,969,103), also assigned to Electro Standards Laboratories, discloses the use of delay state feedback to enhance performance over a wide speed range for electric motors. 
     Embodiments of the present invention are an improvement over prior art systems and methods. 
     SUMMARY OF THE INVENTION 
     In one embodiment, the present invention provides a control system connected to an advanced arresting gear system, the control system comprising: (a) an outer control loop receiving: (i) a port side shaft position, θ p , and (ii) a starboard side shaft position θ s  and, based on received position information, generating a first torque control command τ mp  and a second torque control command τ ms ; (b) a first inner control loop associated with a port-side motor current controller receiving a first pair of dq-axis current commands i qp * and i dp *, the first pair of dq-axis current commands computed based on the first torque control command τ mp , the first inner control loop outputting a first voltage command ν abc   p  for controlling a port side motor that controls a port side of an arrestment cable; (c) a second inner control loop associated with a starboard-side motor current controller receiving a second pair of dq-axis current commands i qs * and i ds *, the second pair of dq-axis current commands computed based on the second torque control command τ ms , the second inner control loop outputting a second voltage command ν abc   s  for controlling a starboard side motor that controls the starboard side of the arrestment cable, wherein each of the port-side motor current controller and the starboard-side motor current controller utilizes a plurality of internally generated feed forward voltages to either: (1) apply a priori knowledge about one or more voltage profiles used by the port-side motor current controller and/or the starboard-side motor current controller, or (2) inject one or more voltage profiles for use by the port-side motor current controller and/or the starboard-side motor current controller to help cancel one or more disturbances or help improve a response time associated with the port-side motor current controller and/or the starboard-side motor current controller, wherein each of the port-side motor current controller and the starboard-side motor current controller comprises: a positive sequence controller, the positive sequence controller comprising a PI filter with a dq input and a summer connected to an output of the PI filter; at least one negative sequence controller, the negative sequence controller connected to the dq input and the summer comprising a rotation transformer connected to an integrator block in series with an inverse rotational transformation block, one or more delay state feedback to counter control loop delays, said delay state feedback providing high bandwidth, low current overshoot, small current rise time and good current stability margins, wherein the one or more delay state feedback to counter loop delays is not enabled when the loop delays are below a predetermined threshold or when high bandwidth performance is not needed, and where undesirable interactions between the positive sequence controller and negative sequence controller is minimized by sharing error signals. 
     In another embodiment, the present invention provides a control system connected to an advanced arresting gear system, the control system comprising: (a) an outer control loop receiving: (i) a port side shaft position, θ p , and (ii) a starboard side shaft position θ s  and, based on received position information, generating a first torque control command τ mp  and a second torque control command τ ms ; (b) a first inner control loop associated with a port-side motor current controller receiving a first pair of dq-axis current commands i qp * and i dp *, the first pair of dq-axis current commands computed based on the first torque control command τ mp , the first inner control loop outputting a first voltage command ν abc   p  for controlling a port side motor that controls a port side of an arrestment cable; (c) a second inner control loop associated with a starboard-side motor current controller receiving a second pair of dq-axis current commands i qs * and i ds *, the second pair of dq-axis current commands computed based on the second torque control command τ ms , the second inner control loop outputting a second voltage command ν abc   s  for controlling a starboard side motor that controls the starboard side of the arrestment cable, and wherein each of the port-side motor current controller and the starboard-side motor controller comprises: a positive sequence controller, the positive sequence controller comprising a PI filter with a dq input and a summer connected to an output of the PI filter; at least one negative sequence controller, the negative sequence controller connected to the dq input and the summer comprising a rotation transformer connected to an integrator block in series with an inverse rotational transformation block; one or more delay state feedback to counter control loop delays, said delay state feedback providing high bandwidth, low current overshoot, small current rise time and good current stability margins; and one or more cross coupled gains between a d-axis and a q-axis, the cross coupled gains a linear, including proportional to, or a nonlinear function of one or more of the following: a speed of the port side motor, a speed of the starboard side motor, a frequency of the port side motor, and a frequency of the starboard side motor, wherein the one or more delay state feedback to counter loop delays is not enabled when the loop delays are below a predetermined threshold or when high bandwidth performance is not needed, and wherein undesirable interactions between the positive sequence controller and negative sequence controller is minimized by sharing error signals. 
     In yet another embodiment, the present invention provides a method as implemented in a control system connected to an advanced arresting gear system, the method comprising: (a) receiving in an outer control loop: (i) a port side shaft position, θ p , and (ii) a starboard side shaft position θ s ; (b) generating a first torque control command τ mp  and a second torque control command τ ms  based on received position information; (c) receiving, in a first inner control loop associated with a port-side motor current controller, a first pair of dq-axis current commands i qp * and i dp *, the first pair of dq-axis current commands computed based on the first torque control command τ mp , the first inner control loop outputting a first voltage command ν abc   p  for controlling a port side motor that controls a port side of an arrestment cable; (d) receiving, in a second inner control loop associated with a starboard-side motor current controller, a second pair of dq-axis current commands i qs * and i ds *, the second pair of dq-axis current commands computed based on the second torque control command τ ms , the second inner control loop outputting a second voltage command ν abc   s  for controlling a starboard side motor that controls the starboard side of the arrestment cable, wherein each of the port-side motor current controller and the starboard-side motor controller comprises: a positive sequence controller, the positive sequence controller comprising a PI filter with a dq input and a summer connected to an output of the PI filter; at least one negative sequence controller, the negative sequence controller connected to the dq input and the summer comprising a rotation transformer connected to an integrator block in series with an inverse rotational transformation block, one or more delay state feedback to counter control loop delays, said delay state feedback providing high bandwidth, low current overshoot, small current rise time and good current stability margins, where undesirable interactions between the positive sequence controller and negative sequence controller is minimized by sharing error signals, wherein each of the port-side motor current controller and the starboard-side motor current controller utilizes a plurality of internally generated feed forward voltages to either: (1) apply a priori knowledge about one or more voltage profiles used by the port-side motor current controller and/or the starboard-side motor current controller, or (2) inject one or more voltage profiles for use by the port-side motor current controller and/or the starboard-side motor current controller to help cancel one or more disturbances or help improve a response time associated with the port-side motor current controller and/or the starboard-side motor current controller, and wherein the one or more delay state feedback to counter loop delays is not enabled when the loop delays are below a predetermined threshold or when high bandwidth performance is not needed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure, in accordance with one or more various examples, is described in detail with reference to the following figures. The drawings are provided for purposes of illustration only and merely depict examples of the disclosure. These drawings are provided to facilitate the reader&#39;s understanding of the disclosure and should not be considered limiting of the breadth, scope, or applicability of the disclosure. It should be noted that for clarity and ease of illustration these drawings are not necessarily made to scale. 
         FIG. 1A  depicts a standard control approach, without negative sequence rejection. 
         FIG. 1B  depicts one embodiment of the present invention&#39;s negative sequence rejection by operating on an existing error signal. 
         FIG. 2  shows an alternate and extended form of the same NS/PI controller shown in  FIG. 1B . 
         FIG. 3  shows cross coupled gains that are added to a controller. 
         FIG. 4  shows a block diagram for the NS/PI vector current control system with both speed dependent cross coupling feedback and delay state feedback. 
         FIG. 5  depicts a block diagram of an advanced arresting gear (AAG) system, defining inputs outputs and various subsystems. 
         FIG. 6  depicts a block diagram of high-level control systems connected with the AAG plant system. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     While this invention is illustrated and described in a preferred embodiment, the invention may be produced in many different configurations. There is depicted in the drawings, and will herein be described in detail, a preferred embodiment of the invention, with the understanding that the present disclosure is to be considered as an exemplification of the principles of the invention and the associated functional specifications for its construction and is not intended to limit the invention to the embodiment illustrated. Those skilled in the art will envision many other possible variations within the scope of the present invention. 
     Note that in this description, references to “one embodiment” or “an embodiment” mean that the feature being referred to is included in at least one embodiment of the invention. Further, separate references to “one embodiment” in this description do not necessarily refer to the same embodiment; however, neither are such embodiments mutually exclusive, unless so stated and except as will be readily apparent to those of ordinary skill in the art. Thus, the present invention can include any variety of combinations and/or integrations of the embodiments described herein. 
     This present invention describes a design for the negative sequence proportional integral (NS/PI) current control system for linear and rotary electric motors, and by extension to electric power systems, with the discussion here applied to induction motors. The controllers developed here have advanced features, to be described, which provide many advantages over the typical proportion-integral (PI) controllers and over other controllers with negative sequence harmonic suppression. Particularly, the inclusion of a novel negative sequence suppressor based on the transformed positive sequence current i dq  error signals to cancel harmonics induced by line imbalance is a key advantage. The use of the shared i dq  error signal in this approach allows the positive and negative sequence controllers to operate with minimal interference with each other so that additional filtering to isolate the positive and negative sequence components is not required and thus does not limit controller bandwidth. In addition to providing both positive sequence control and negative sequence suppression control, the controller developed here has extended bandwidth via additional feedback paths and feedback states that are not found in other controllers with negative sequence harmonic injection, and is able to operate over a very broad mechanical speed range, and also works well at relatively high electrical frequencies. 
     The inclusion of negative sequence control generally alters the frequency response characteristics of a current controller at high frequency and causes reduced gain and phase margins when operating the motor at high speed. In order to allow for greater design flexibility to combat this issue, the NS/PI control modifies the usual industrial approaches and allows cross coupling gains between the d-axis and q-axis current controllers. A design analysis over the full required speed range of the motor indicates that more robust performance is provided with cross coupled gains that are proportional to motor speed, and the existence of any control loop delays, which are normally detrimental to control stability, is dealt with by the innovative inclusion of delay state feedback to provide high bandwidth, low overshoot, small rise time and good stability margins. The net result is a controller with eight or more (two more needed for every loop delay in a given system) unique gains, used symmetrically on each of the two axes, with half of those gains (the cross coupled ones) changing linearly with motor speed. 
     This controller is more complex to implement than a standard uncoupled PI controller. Fortunately, the use of cross coupled gains (even speed dependent gains) is straightforward to implement digitally in software. The resulting code simply allows more terms than a typical PI controller for calculating the d-axis and q-axis voltage commands. This means a few more multiply and addition operations are required. One complication with establishing the controller design is calculating the required gains. With eight or more unique numbers to determine, manual tuning is not practical, being unduly tedious or even impossible in practice. Hence, a pole placement method can be used to directly calculate the required gains, and pole locations are selected based on design criteria. The method of calculating gains via this methodology is not shown here, but standard textbooks on modern control theory describe this known method. 
     This design is applied for controlling induction motors with imbalanced phases caused by cabling connections, or other reasons, in industrial environments and shipboard use, especially when the induction motors must provide very fast and accurate control with high bandwidth and good stability margins. However, the installation of such a system requires long power cables which can create line imbalance, resulting in high torque ripple from negative sequence harmonics. Suppression of the torque ripple is problematic with standard control methods because any controller that targets the harmonics requires high frequency operations and this tends to destabilize standard current control topologies, unless the dynamic performance of the control system is reduced to prevent instability. Hence, this disclosed design provides a way to overcome all of these issues and provide a higher bandwidth, and better overall control, even with the added negative sequence suppression feature included. 
     The method described here, to suppress the negative sequence harmonic caused by imbalance, can be extended to suppress any other positive or negative sequence harmonic, either individually, or collectively. For example, if inverter harmonics introduce undesirable harmonics, then those particular harmonics can be removed by the same basic method. 
     Controller Design 
     The controller design is applied in the well-known dqo-axes rotor reference frame. When motor coils share a common neutral point connection, the 0-axis reference frame is not needed in the control design. Here the design is performed in the dq-axes reference frame but is applicable to the dq0-axes reference frame without loss of generality. 
       FIG. 1A  depicts a standard control approach, without negative sequence rejection. The input 3-phase measured currents i abc  are transformed to the stationary 2-phase frame currents i αβ  via the T αβ  transform block  102 . The stationary frame currents are then transformed to the rotating frame i dq  currents via the rotation transform R γ    104 . The error signal vector e dq  is generated by taking the difference between the measured currents and the commanded currents. The error vector signal is fed through the PI filter  106  to generate a rotating frame voltage command ν dq , and then the reverse transforms (generated by R γ   −1  transform block  108  and T αβ   −1  transform block  110 ) are used to generate stationary frame voltage commands. 
       FIG. 1B  depicts one embodiment of the present invention&#39;s negative sequence rejection by operating on an existing error signal. The modification is to transform the error signal using a rotation transform at −2 (which is the harmonic factor) times the transform angle. Using the rotation transform R γ    112  but with angle −2γ as input as shown within the dotted box in  FIG. 1 , effectively creates a reference frame that is synchronized with the negative sequence harmonic. The integrator block (G/S)  114  is then applied to the transformed error signal and the result is transformed back into the dq synchronous frame via inverse rotational transformation block R γ   −1    116 , and that signal is added back to the PI filter output to form the ν dq  voltage command. 
     Other implementations of negative sequence harmonic suppression controllers develop a separate error signal for the negative sequence portion of the control system. An innovation here (as shown in  FIG. 1B ) is that the standard error signal e dq  used by the standard positive sequence controller is transformed into the negative sequence reference frame and is also used there. Because both the positive and negative sequence controllers share the same error signal e dq , undesirable interaction between them is minimized and special filters to separate the negative sequence current components from the positive sequence current components are not needed. This allows for increased controller bandwidth because additional filtering can introduce delays. The sharing of the error signal can be done for any harmonic factor β. Without loss of generality, the example discussed here has β=−2 for the negative sequence harmonic caused by phase imbalance, but any factor can be used. It is also possible to dynamically change β if desired. Transform blocks are showing the matrix operator transforms that operate on the signal vectors. Most of the required math is evident from the diagram. The PI Filter is a gain term added to an amplified integration term and the G/s block is an amplified integration block. Operator transforms are as follows. 
     
       
         
           
             
               
                 
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       FIG. 1A  shows the standard PI filter approach typically used for motor control, on the top block diagram. The bottom block diagram,  FIG. 1B , shows the modification (with dotted lines) that is added to provide the negative sequence control function. Note the innovation shown in the diagram is that the second controller operates on the existing error signal e dq  which is different from other approaches. This has the advantage of simple implementation and automatic prevention of conflict between the two controllers since both controllers try to zero out the error signal. The approach is scalable such that multiple NS Controller Subsystems can be paralleled, with e dq  used as input for each one, separate harmonic factors β m , for each of the m subsystems, and with the sum of the outputs from each NS Controller Subsystems added to the output of the PI Filter to compute ν dq  in order to target and simultaneously suppress more than one harmonic. 
     In one embodiment, the present invention discloses a current controller comprising: a positive sequence controller; and a negative sequence controller, where error signals operated on by said positive sequence controller are transformed into a negative sequence reference frame and input to said negative sequence controller. 
     In another embodiment, the present invention provides a method as implemented in a current controller for higher bandwidth operation based on minimized interference between positive and negative components of a current controller, said method performed without additional filtering on measured currents to isolate positive and negative current components, said method comprising: identifying error signals operated on by a positive sequence controller; transforming identified error signals into a negative sequence reference frame associated with a negative sequence controller; inputting transformed error signals to a negative sequence controller, and where undesirable interactions between said positive sequence controller and negative sequence controller is minimized by sharing error signals. 
     The simpler above approach is good for situations where the required control bandwidth is not too stringent, and there is not too much loop delay in the feedback path.  FIG. 2  shows an alternate and extended form of the same NS/PI controller shown in  FIG. 1B . This form is preferred for control design and is better for showing additional features that can be incorporated into the structure.  FIG. 2  shows a more detailed view of  FIG. 1B . Here more detail is provided and a feed forward voltage command is added to provide better transient response, as is often done in these systems. The input 3-phase measured currents i abc  are transformed to the stationary 2-phase frame currents i αβ  via the T αβ  transform block. The stationary frame currents are then transformed to the rotating frame i dq  currents via the rotation transform block R γ , which uses the flux angle γ. The error signal vector e dq  is generated by taking the difference between the measured currents and the commanded currents. This figure makes the PI filter function explicit. The error signal is split into 3 paths. In the first path, the error signal vector e dq  is multiplied by the proportional gain G p . In the second path, the error signal e dq  is integrated by the T s /(z−1) block and then multiplied by the integral gains G i . In the third path, the error signal is further transformed into the negative sequence frame. The function is to transform the error signal using a rotation transform at −2 times the transform angle γ. In between the to-and-from rotational transforms R γ  and R γ   −1  that are fed with the −2γ angle, an integrator block T s /(z−1) is inserted. After transformation back to the positive dq-frame, the z dq  signal is multiplied by the G h  gain. The three paths are added together, as shown, and then a feedforward signal (as typically used in standard practice) is added to form the dq-frame commanded voltage ν dq . This commanded voltage is transformed to a stationary frame 2-phase voltage ν αβ , using the R γ   −1  transform block with input angle γ. Then, this signal vector is transformed by the T αβ   −1  block to form the commanded ν abc * three-phase voltages. 
     In more demanding applications where higher bandwidth is desired and the loop delays are not too large, cross coupled gains can be added to the controller as shown in  FIG. 3 . In general the cross coupled gains could be constant numbers, or can be made functions of motor speed or electrical frequency. The functional form of the speed/frequency dependence can be determined by analysis to place the poles and keep them in the same general spot as speed changes. However, this is complicated and a simplification is to make the cross coupled gains proportional to motor speed, as shown in  FIG. 3 .  FIG. 3  shows an extended block diagram from that in  FIG. 2 . Here more feedback is provided to create cross coupled gains that allow full pole placement designs to be realized, provided that delays are small. The input 3-phase measured currents i abc  are transformed to the stationary 2-phase frame currents i αβ  via the T αβ  transform block. The stationary frame currents are then transformed to the rotating frame i dq  currents via the rotation transform R γ , which uses the rotor flux angle γ. The error signal vector e dq  is generated by taking the difference between the measured currents and the commanded currents. The error signal is split into three paths. In the first path, the error signal vector e dq  formed and split into separate e d  and e q  components. In the second path, the error signal e dq  is integrated by the Ts/(z−1) block to create the x dq  vector which is then split into separate x d  and x q  components. In the third path, the error signal is further transformed into the negative sequence frame. The function is to transform the error signal using a rotation transform at −2 times the transform angle γ. In between the to-and-from rotational transforms R γ  and R γ   −1  that are fed with the −2γ angle, an integrator block Ts/(z−1) is inserted. After transformation back to the positive dq-frame, the z dq  signal is split into separate z d  and z q  components. The three paths are multiplied by various gain factors and then added together, as shown. The gain multiplications include all of the same G p , G i  and G h  gain multiplications; however, also included are the cross coupled gains which are also scaled by the motor speed to provide adaptive gains. The cross coupled gain signals feeding into the sum junction for V dpi  are −ω m G pc e q , −ω m G ic x q , −ω m G hc z q . The cross coupled gain signals feeding into the sum junction for V qpi  are ω m G pc e d , ω m G ic x d , ω m G hc z d . Then feedforward signals (as typically used in standard practice) V dff  and V qff  are added to the V dpi  and V qpi  voltage channels, respectively, to form the dq-frame commanded voltage ν dq . This commanded voltage is transformed to a stationary frame 2-phase voltage van, using the R γ   −1  transform block fed with angle γ. Then, this signal vector is transformed by the T αβ   −1  block to form the commanded ν abc * three-phase voltages. 
     This disclosure identifies the cross coupled gains (constant or speed dependent) as useful for a solution depending on the required system specification. When the cross coupled gains are made proportional to speed, it is often possible to maintain system stability and good performance without having highly complicated functions. 
     In another embodiment, the present invention provides a current controller comprising: a positive sequence controller, at least one negative sequence controller, and one or more delay state feedbacks to counter control loop delays, said delay state feedbacks providing high bandwidth, low current overshoot, small current rise time and good current stability margins. 
     In another embodiment, the present invention provides a method as implemented in a current controller to address a negative sequence control altering a frequency response characteristics of said current controller at high frequency causing reduced gain and phase margins when operating a motor at high speed, said current controller comprising a positive sequence controller and at least one negative sequence controller, said method comprising: identifying control loop delays in said current controller; and providing one or more delay state feedback to counter control loop delays, said delay state feedback providing high bandwidth, low current overshoot, small current rise time and good current stability margins. 
     In another embodiment, the present invention provides a current controller comprising: a positive sequence controller, at least one negative sequence controller, and one or more cross coupled gains between a d-axis and a q-axis, said cross coupled gains proportional to speed of a motor associated with said current controller. In an extended embodiment, the gains can be a general scaled function of speed in order for the design to work over an entire operating speed of said motor. 
     In another embodiment, the present invention provides a method as implemented in a current controller associated with a motor, said current controller comprising a positive sequence controller and at least one negative sequence controller, said method comprising: identifying a speed of said motor; and providing one or more cross coupled gains between a d-axis and a q-axis, said cross coupled gains proportional to said identified speed of said motor. In an extended embodiment, the gains can be a general scaled function of speed in order for the design to work over an entire operating speed of said motor. 
     In another embodiment, the present invention provides a current controller comprising: a positive sequence controller, at least one negative sequence controller, one or more delay state feedback to counter control loop delays, said delay state feedback providing high bandwidth, low current overshoot, small current rise time and good current stability margins; and one or more cross coupled gains between a d-axis and a q-axis, said cross coupled gains proportional to speed of a motor associated with said current controller. In an extended embodiment, the gains can be a general scaled function of speed in order for the design to work over an entire operating speed of said motor. 
     In another embodiment, the present invention provides a method as implemented in a current controller associated with a motor, said current controller comprising a positive sequence controller and at least one negative sequence controller, said method comprising: identifying a speed of said motor; providing one or more delay state feedback to counter control loop delays, said delay state feedback providing high bandwidth, low current overshoot, small current rise time and good current stability margins; and providing one or more cross coupled gains between a d-axis and a q-axis, said cross coupled gains proportional to said identified speed of said motor. In an extended embodiment, the gains can be a general scaled function of speed in order for the design to work over an entire operating speed of said motor. 
     The block diagram for the NS/PI vector current control system in its most advanced form, with both speed dependent cross coupling feedback and delay state feedback, is shown in  FIG. 4 .  FIG. 4  shows an extended block diagram from that in  FIG. 3 . Here more feedback is provided to create delay state gains that allow full pole placement designs to be realized, when delays can&#39;t be neglected. The input 3-phase measured currents i abc  are transformed to the stationary 2-phase frame currents i αβ  via the T αβ  transform block. The stationary frame currents are then transformed to the rotating frame i dq  currents via the rotation transform R γ , which uses the flux angle γ. The error signal vector e dq  is generated by taking the difference between the measured currents and the commanded currents. The error signal is split into three paths. In the first path, the error signal vector e dq  formed and split into separate e d  and e q  components. In the second path, the error signal e dq  is integrated by the Ts/(z−1) block to create the x dq  vector which is then split into separate x d  and x q  components. In the third path, the error signal is further transformed into the negative sequence frame. The function is to transform the error signal using a rotation transform at −2 times the transform angle γ. In between the to-and-from rotational transforms R γ  and R γ   −1  that are fed with the −2γ angle, an integrator block Ts/(z−1) is inserted. After transformation back to the positive dq-frame, the z dq  signal is split into separate z d  and z q  components. The three paths are multiplied by various gain factors and then added together, as shown. The gain multiplications include all of the same G p , G i  and G h  gain multiplications; and also included are the cross coupled gains which are also scaled by the motor speed to provide adaptive gains. Additionally, the delay states are implemented in the block diagram and then delay state gains, and cross coupled gains (also scaled by motor speed) are added. The cross coupled gain signals feeding into the sum junction for V dpi  are −ω m G pc e q , −ω m G ic x q , −ω m G hc z q , ω m G DVc1 V qpi1 , and ω m G DFc2 V qpi2 , where V qpi1  and V qpi2  are the first and second delay states of V qpi . The cross coupled gain signals feeding into the sum junction for V qpi  are ω m G pc e d , ω m G ic x d , ω m G hc z d , −ω m G DFc1 V dpi1 , and −ω m G DFc2 V dpi2 , where V dpi1  and V dpi2  are the first and second delay states of V dpi . Then feedforward signals (as typically used in standard practice) V dff  and V qff  are added to the V dpi  and V qpi  voltage channels, respectively, to form the dq-frame commanded voltage ν dq . This commanded voltage is transformed to a stationary frame 2-phase voltage ν αβ , using the R γ   −1  transform block fed with angle γ. Then, this signal vector is transformed by the T αβ   −1  block to form the commanded ν abc * three-phase voltages. 
     For illustration purposes, the presentation assumes two loop delay states. However, the method is general to any arbitrary number of delay states. Also, the harmonic factor β=−2 is shown for illustration, but any other integer value or values for β could be chosen. If it is desirable to simultaneously suppress multiple harmonics, then multiple values of β can be used in a block parallel implementation of the controller to achieve suppression for each harmonic. The blocks are shown for the control gains. These are indicating that the cross coupled gains are multiplied by the motor speed Wm. The transform blocks are showing the matrix operator transforms that operate on the signal vectors, and the z-dependent blocks are showing digital delays (1/z) and digital integration blocks (T s /(z−1)). 
     The following formulas provide the algorithm explicitly, and these formulas are general enough to implement any of the controller forms discussed above. In the simpler cases, the respective gains that are not needed are simply set to zero. 
     
       
         
           
             
               
                 i 
                 αβ 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 T 
                 αβ 
               
               · 
               
                 
                   i 
                   abc 
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
             
           
         
       
       
         
           
             
               
                 i 
                 d 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   cos 
                   ⁡ 
                   
                     ( 
                     γ 
                     ) 
                   
                 
                 · 
                 
                   
                     i 
                     a 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               + 
               
                 
                   sin 
                   ⁡ 
                   
                     ( 
                     γ 
                     ) 
                   
                 
                 · 
                 
                   
                     i 
                     β 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 i 
                 q 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   cos 
                   ⁡ 
                   
                     ( 
                     γ 
                     ) 
                   
                 
                 · 
                 
                   
                     i 
                     β 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               - 
               
                 
                   sin 
                   ⁡ 
                   
                     ( 
                     γ 
                     ) 
                   
                 
                 · 
                 
                   
                     i 
                     α 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 e 
                 d 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   i 
                   d 
                   * 
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
               - 
               
                 
                   i 
                   d 
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
             
           
         
       
       
         
           
             
               
                 e 
                 q 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   i 
                   q 
                   * 
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
               - 
               
                 
                   i 
                   q 
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
             
           
         
       
       
         
           
             
               
                 x 
                 d 
               
               ⁡ 
               
                 [ 
                 
                   n 
                   + 
                   1 
                 
                 ] 
               
             
             = 
             
               
                 
                   x 
                   d 
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
               + 
               
                 
                   T 
                   s 
                 
                 · 
                 
                   
                     e 
                     d 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 x 
                 q 
               
               ⁡ 
               
                 [ 
                 
                   n 
                   + 
                   1 
                 
                 ] 
               
             
             = 
             
               
                 
                   x 
                   q 
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
               + 
               
                 
                   T 
                   s 
                 
                 · 
                 
                   
                     e 
                     q 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 e 
                 
                   d 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   cos 
                   ⁡ 
                   
                     ( 
                     
                       
                         - 
                         2 
                       
                       ⁢ 
                       γ 
                     
                     ) 
                   
                 
                 · 
                 
                   
                     e 
                     d 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               + 
               
                 
                   sin 
                   ⁡ 
                   
                     ( 
                     
                       
                         - 
                         2 
                       
                       ⁢ 
                       γ 
                     
                     ) 
                   
                 
                 · 
                 
                   
                     e 
                     q 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 e 
                 
                   q 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   cos 
                   ⁡ 
                   
                     ( 
                     
                       
                         - 
                         2 
                       
                       ⁢ 
                       γ 
                     
                     ) 
                   
                 
                 · 
                 
                   
                     e 
                     q 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               - 
               
                 
                   sin 
                   ⁡ 
                   
                     ( 
                     
                       
                         - 
                         2 
                       
                       ⁢ 
                       γ 
                     
                     ) 
                   
                 
                 · 
                 
                   
                     e 
                     d 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 z 
                 
                   d 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                 
               
               ⁡ 
               
                 [ 
                 
                   n 
                   + 
                   1 
                 
                 ] 
               
             
             = 
             
               
                 
                   z 
                   
                     d 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
               + 
               
                 
                   T 
                   s 
                 
                 · 
                 
                   
                     e 
                     
                       d 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 z 
                 d 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   cos 
                   ⁡ 
                   
                     ( 
                     
                       
                         - 
                         2 
                       
                       ⁢ 
                       γ 
                     
                     ) 
                   
                 
                 · 
                 
                   
                     z 
                     
                       d 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               - 
               
                 
                   sin 
                   ⁡ 
                   
                     ( 
                     
                       
                         - 
                         2 
                       
                       ⁢ 
                       γ 
                     
                     ) 
                   
                 
                 · 
                 
                   
                     z 
                     
                       q 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 z 
                 q 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   cos 
                   ⁡ 
                   
                     ( 
                     
                       
                         - 
                         2 
                       
                       ⁢ 
                       γ 
                     
                     ) 
                   
                 
                 · 
                 
                   
                     z 
                     
                       q 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               + 
               
                 
                   sin 
                   ⁡ 
                   
                     ( 
                     
                       
                         - 
                         2 
                       
                       ⁢ 
                       γ 
                     
                     ) 
                   
                 
                 · 
                 
                   
                     z 
                     
                       d 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 v 
                 dpi 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   G 
                   p 
                 
                 · 
                 
                   
                     e 
                     d 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               - 
               
                 
                   
                     ω 
                     m 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
                 · 
                 
                   G 
                   pc 
                 
                 · 
                 
                   
                     e 
                     q 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               + 
               
                 
                   G 
                   i 
                 
                 · 
                 
                   
                     x 
                     d 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               - 
               
                 
                   
                     ω 
                     m 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
                 · 
                 
                   G 
                   ic 
                 
                 · 
                 
                   
                     x 
                     q 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               + 
               
                 
                   G 
                   h 
                 
                 · 
                 
                   
                     z 
                     d 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               - 
               
                 
                   
                     ω 
                     m 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
                 · 
                 
                   G 
                   hc 
                 
                 · 
                 
                   
                     z 
                     q 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               - 
               
                 
                   G 
                   
                     DF 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
                 · 
                 
                   
                     v 
                     dpi 
                   
                   ⁡ 
                   
                     [ 
                     
                       n 
                       - 
                       1 
                     
                     ] 
                   
                 
               
               + 
               
                 
                   
                     ω 
                     m 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
                 · 
                 
                   G 
                   
                     DFc 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
                 · 
                 
                   
                     v 
                     dpi 
                   
                   ⁡ 
                   
                     [ 
                     
                       n 
                       - 
                       1 
                     
                     ] 
                   
                 
               
               - 
               
                 
                   G 
                   
                     DF 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                 
                 · 
                 
                   
                     v 
                     qpi 
                   
                   ⁡ 
                   
                     [ 
                     
                       n 
                       - 
                       2 
                     
                     ] 
                   
                 
               
               + 
               
                 
                   
                     ω 
                     m 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
                 · 
                 
                   G 
                   
                     DFc 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                 
                 · 
                 
                   
                     v 
                     qpi 
                   
                   ⁡ 
                   
                     [ 
                     
                       n 
                       - 
                       2 
                     
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 v 
                 qpi 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   G 
                   p 
                 
                 · 
                 
                   
                     e 
                     q 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               + 
               
                 
                   
                     ω 
                     m 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
                 · 
                 
                   G 
                   pc 
                 
                 · 
                 
                   
                     e 
                     d 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               + 
               
                 
                   G 
                   i 
                 
                 · 
                 
                   
                     x 
                     q 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               + 
               
                 
                   
                     ω 
                     m 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
                 · 
                 
                   G 
                   ic 
                 
                 · 
                 
                   
                     x 
                     d 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               + 
               
                 
                   G 
                   h 
                 
                 · 
                 
                   
                     z 
                     q 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               + 
               
                 
                   
                     ω 
                     m 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
                 · 
                 
                   G 
                   hc 
                 
                 · 
                 
                   
                     z 
                     d 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               - 
               
                 
                   G 
                   
                     DF 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
                 · 
                 
                   
                     v 
                     qpi 
                   
                   ⁡ 
                   
                     [ 
                     
                       n 
                       - 
                       1 
                     
                     ] 
                   
                 
               
               - 
               
                 
                   
                     ω 
                     m 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
                 · 
                 
                   G 
                   
                     DFc 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
                 · 
                 
                   
                     v 
                     dpi 
                   
                   ⁡ 
                   
                     [ 
                     
                       n 
                       - 
                       1 
                     
                     ] 
                   
                 
               
               - 
               
                 
                   G 
                   
                     DF 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                 
                 · 
                 
                   
                     v 
                     qpi 
                   
                   ⁡ 
                   
                     [ 
                     
                       n 
                       - 
                       2 
                     
                     ] 
                   
                 
               
               - 
               
                 
                   
                     ω 
                     m 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
                 · 
                 
                   G 
                   
                     DF 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     c 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                 
                 · 
                 
                   
                     v 
                     dpi 
                   
                   ⁡ 
                   
                     [ 
                     
                       n 
                       - 
                       2 
                     
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 v 
                 dff 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   R 
                   S 
                 
                 · 
                 
                   i 
                   d 
                   * 
                 
               
               - 
               
                 
                   
                     ω 
                     e 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
                 · 
                 
                   ( 
                   
                     
                       L 
                       S 
                     
                     - 
                     
                       
                         L 
                         m 
                         2 
                       
                       
                         L 
                         r 
                       
                     
                   
                   ) 
                 
                 · 
                 
                   
                     i 
                     q 
                     * 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 v 
                 qff 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   R 
                   S 
                 
                 · 
                 
                   
                     i 
                     q 
                     * 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               + 
               
                 
                   
                     ω 
                     e 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
                 · 
                 
                   L 
                   S 
                 
                 · 
                 
                   
                     i 
                     d 
                     * 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 v 
                 d 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   v 
                   dpi 
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
               + 
               
                 
                   v 
                   dff 
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
             
           
         
       
       
         
           
             
               
                 v 
                 q 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   v 
                   qpi 
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
               + 
               
                 
                   v 
                   qff 
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
             
           
         
       
       
         
           
             
               v 
               ⁢ 
               
                   
               
               ⁢ 
               
                 α 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
             
             = 
             
               
                 
                   cos 
                   ⁡ 
                   
                     ( 
                     γ 
                     ) 
                   
                 
                 · 
                 
                   
                     v 
                     d 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               - 
               
                 
                   sin 
                   ⁡ 
                   
                     ( 
                     γ 
                     ) 
                   
                 
                 · 
                 
                   
                     v 
                     q 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 v 
                 β 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 
                   cos 
                   ⁡ 
                   
                     ( 
                     γ 
                     ) 
                   
                 
                 · 
                 
                   
                     v 
                     q 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
               + 
               
                 
                   sin 
                   ⁡ 
                   
                     ( 
                     γ 
                     ) 
                   
                 
                 · 
                 
                   
                     v 
                     d 
                   
                   ⁡ 
                   
                     [ 
                     n 
                     ] 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 i 
                 abc 
               
               ⁡ 
               
                 [ 
                 n 
                 ] 
               
             
             = 
             
               
                 T 
                 αβ 
                 
                   - 
                   1 
                 
               
               · 
               
                 
                   v 
                   αβ 
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
             
           
         
       
     
     Often, negative sequence harmonics are small when the motor speed is small. Hence, optionally, the NS portion of the controller can be turned off below a particular motor speed threshold. This is accomplished by forcing the z-integrators to zero and resetting the x-integrators, whenever speed is below the speed threshold. Off conditions for the z-integrators are always zero and the values of z-integrators must be transferred to the x d  and x q  integrators according to the following formulas. Optionally, a hysteresis-based threshold (dual value) could be used for on the speed threshold, but the simple (single-valued) threshold is inherently noise resistant in this case, hence it may not provide any noticeable difference in performance. 
     
       
         
           
             
               
                 x 
                 d 
               
               ⁡ 
               
                 [ 
                 
                   n 
                   + 
                   1 
                 
                 ] 
               
             
             = 
             
               
                 
                   x 
                   d 
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
               + 
               
                 
                   1 
                   
                     G 
                     i 
                   
                 
                 · 
                 
                   ( 
                   
                     
                       
                         G 
                         h 
                       
                       · 
                       
                         z 
                         d 
                       
                     
                     - 
                     
                       
                         ω 
                         m 
                       
                       · 
                       
                         G 
                         hc 
                       
                       · 
                       
                         z 
                         q 
                       
                     
                   
                   ) 
                 
               
             
           
         
       
       
         
           
             
               
                 x 
                 q 
               
               ⁡ 
               
                 [ 
                 
                   n 
                   + 
                   1 
                 
                 ] 
               
             
             = 
             
               
                 
                   x 
                   q 
                 
                 ⁡ 
                 
                   [ 
                   n 
                   ] 
                 
               
               + 
               
                 
                   1 
                   
                     G 
                     i 
                   
                 
                 · 
                 
                   ( 
                   
                     
                       
                         G 
                         h 
                       
                       · 
                       
                         z 
                         q 
                       
                     
                     + 
                     
                       
                         ω 
                         m 
                       
                       · 
                       
                         G 
                         hc 
                       
                       · 
                       
                         z 
                         d 
                       
                     
                   
                   ) 
                 
               
             
           
         
       
     
     The NS/PI controller outlined above was implemented on a digital control system and applied to a one horsepower, three phase induction motor with a 22% inductance imbalance added to one phase leg to demonstrate its effectiveness, although its use in not restricted to a particular power or size level. Successful suppression of the undesirable harmonic was realized while still maintaining high bandwidth operation. 
     
       
         
           
               
             
               
                   
               
               
                 Symbol Definitions 
               
               
                 The following definitions and conventions are used in this document. 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                 T s   
                 digital sample time 
                   
               
               
                 N pp   
                 number of pole pairs 
                   
               
               
                 L m   
                 mutual inductance 
                   
               
               
                 L lr   
                 rotor leakage inductance 
                   
               
               
                 L ls   
                 stator leakage inductance 
                   
               
               
                 R r   
                 rotor resistance 
                   
               
               
                 R s   
                 stator resistance 
                   
               
               
                 L r   
                 rotor inductance 
                 L r  = L m  + L lr   
               
               
                 L s   
                 stator inductance 
                 L s  = L m  + L ls   
               
               
                 G p   
                 proportional gain [V/A] 
                 G p   
               
               
                 G pc   
                 proportional cross gain [V/A] 
                 G pc   
               
               
                 G i   
                 first integral gain [V/As] 
                 G i   
               
               
                 G ic   
                 first integral cross gain [V/As] 
                 G ic   
               
               
                 G h   
                 second integral gain [V/As] 
                 G h   
               
               
                 G hc   
                 second integral cross gain [V/As] 
                 G hc   
               
               
                 G DF1   
                 delay gain for delay 1 
                 G DF   
               
               
                 G DF2   
                 delay gain for delay 2 
                 G DF   
               
               
                 G DFc1   
                 delay cross gain for delay 1 
                 G DFc   
               
               
                 G DFc2   
                 delay cross gain for delay 2 
                 G DFc   
               
               
                 i d *, i q * 
                 commanded dq-frame currents 
                 [A] 
               
               
                 i d , i q   
                 measured rotating dq-frame currents 
                 [A] 
               
               
                 i a , i b , i c   
                 measured abc-frame currents 
                 [A] 
               
               
                 i α , i β   
                 measured stationary dq-frame currents 
                 [A] 
               
               
                 e d , e q   
                 dq-frame current errors (positive frame) 
                 [A] 
               
               
                 e d2 , e q2   
                 dq-frame current errors (negative frame) 
                 [A] 
               
               
                 v d , v q   
                 commanded dq-frame voltages 
                 [V] 
               
               
                 v dff , v qff   
                 feed-forward portion of dq-frame voltages 
                 [V] 
               
               
                 v dpi , v qpi   
                 feedback portion of dq-frame voltages 
                 [V] 
               
               
                 v α , v β   
                 commanded stationary dq-fmme voltages 
                 [V] 
               
               
                 v a , v b , v c   
                 commanded abc-frame voltages 
                 [V] 
               
               
                 x d , x q   
                 PI dq-frame integral states 
                 [As] 
               
               
                 z d2 , z q2   
                 NS dq-frame integral states (negative frame) 
                 [As] 
               
               
                 z d , z q   
                 NS dq-frame integral states (positive frame) 
                 [As] 
               
               
                 ω m   
                 estimated mechanical rotor speed 
                 [rad/s] 
               
               
                 γ 
                 estimated electrical synchronous angle 
                 [rad] 
               
               
                 ω e   
                 estimated electrical synchronous frequency 
                 [rad/s] 
               
               
                 VPI 
                 PI dq-frame PI filter output voltages 
                 [V] 
               
               
                 VHS 
                 NS controller subsystem output voltage 
                 [V] 
               
               
                 β 
                 harmonic factor 
                 [no units] 
               
               
                 n 
                 discrete time 
                 [no units] 
               
               
                   
               
            
           
         
       
     
       FIG. 5  shows a block diagram of a typical modern-day electric motor-based Advanced Arresting Gear (AAG) system. This AAG system can be viewed as the “plant” in the context of a control feedback system, with relevant inputs and outputs identified, as needed for operation of controllers and feedback systems. There can be variations on this system, but the key relevant feature is the use of motors that require high bandwidth and fast transient response, over relatively short time periods of an arrestment (about 2-10 seconds). 
     In  FIG. 5 , the “Tailhook and Aircraft” represent the aircraft that engages an arrestment cable on the deck of a carrier, with the tail-hook (attached to the aircraft) grabbing the cable on landing. The AAG system has two nominally identical port and starboard (stbd) systems that pull and control the arrestment cable to bring the aircraft to a halt by the time the aircraft reaches the end of the deck without steering it outside of the prescribed runway path, and without violating force and performance specifications for the arresting system and the aircraft. The cable is routed through sheaves, then to shock absorbers and then to cable drums attached to two independent (port and stbd) shafts which are controlled with water twisters, brakes and motors. The block diagram shows that each (port or stbd) shaft is composed of several pieces. The main cable drum stores (with many turns or wraps) the cable as it is pulled in. There is a friction brake that can apply torque resistance directly to the drum. There can also be a water twister, connected with a shaft-coupler, which can provide a “speed-squared” torque resistance to the shaft system. And, there is a rotary motor, connected with a shaft-coupler, which can provide either torque resistance, or torque driving to the shaft system. Each brake requires its own local controller that converts incoming torque commands into the appropriate brake pressure to achieve that. Each shaft has at least one optical encoder to measure the position changes on the shaft. 
     As seen in  FIG. 5 , this system has four primary sets of inputs and four primary sets of outputs. The inputs are two torque commands; τ bp  for the port side brake and τ bs  for the stbd side brake, and two sets (three signals each) of abc-frame motor voltage commands, ν abc   p  and ν abc   s . The voltage commands are generated by the current controller and typically applied to the coils of the motor through power electronics, such as a pulse width modulated inverter. The outputs are two position measurements; θ p  for the port side shaft position and θ s  for the stbd side shaft position, and two sets (three signals each) of abc-frame motor current measurements, i abc   p  and i abc   s . The port currents measurements and port shaft position measurement are taken as inputs to the port current controller in order to complete the closed loop feedback for the port dq vector current controller. The starboard currents and position measurements are used by the starboard dq vector current controller in the same way. 
     With the basic “plant” system identified,  FIG. 6  shows a typical interconnection scheme between the various embodiments of the current controller in  FIGS. 1A-B  to  FIG. 4  and the basic plant in  FIG. 5 . The following discussion will detail the port-side interconnections, but it also applies to the corresponding starboard side interconnections. Referring to  FIG. 1B , the controller input currents i abc  are the measured currents i p   abc  shown as being output from the Port Side AAG Plant in  FIG. 6 , corresponding to the port motor output currents in  FIG. 5 . Referring to  FIG. 1B , the commanded direct and quadrature frame vector of currents i dq * are the currents i* dp  and i* qp  shown in  FIG. 6  emanating from the Command Conversion subsystem based on the commanded torque τ mp  being generated by the Outer Control Loop in order to apply force on the port side cable to arrest the aircraft in a prescribed manner. Referring to  FIG. 1B , the estimated electrical synchronous angle γ typically aligned with the rotor flux of the motor is calculated based on the type of motor being used and the availability of measurements. For a synchronous motor such as an AC permanent magnet motor or servo motor, γ is calculated by scaling the measured shaft position θ p  output from the Port Side AAG Plant in  FIG. 6  by the number of motor pole pairs, which is a parameter of the physical construction of the motor. For an induction motor as in this embodiment, γ is calculated by estimating the motor&#39;s slip angle via a scaled integration of id* and i q * and adding that to a scaled θ p . In other implementations without mechanical shaft feedback, it is possible to estimate γ based on measurement of motor electrical quantities, but this method is often sensitive to measurement errors and disturbances and not discussed further. The various methods of calculating γ as are known in the literature and include the methods above, can be applied as appropriate to achieve the best performance without changing the essence of this work. Referring to  FIG. 1B , the output of the current controller v abc * is connected to the inputs v p   abc  entering the Port Side AAG Plant in  FIG. 6 , which is the input to the Port Motor in  FIG. 5 . 
     All of the inputs and outputs of the motor controller embodiment shown in  FIG. 1B  have now been interconnected with the AAG plant. Moving to the current controller embodiments in  FIGS. 2-4 , notice that the controllers&#39; complexity changes but that their external inputs and outputs are the same as the current controller in  FIG. 1B . Their interconnections with the AAG plant are the same as the controller described in  FIG. 1B . The controllers in  FIGS. 2-4  do have additional internal feed forward voltages V dff  and v qff  but these are internally generated and do not affect the system interconnections. These feedforward voltages are often used to apply the nominal voltage profile needed to generate the desired currents and is a controller component that can be found in the literature. 
       FIG. 6  shows that the general architectural approach for the AAG control system is to use two “inner-loop” current controllers to control the torques of both motors, with two individual commands τ mp  and τ ms , and then use an outer control loop to provide the torque commands. This allows the inner loop motor controllers to be optimized for high bandwidth and fast transient response, independently of the concerns of arresting the aircraft, and the outer control loop can be optimized for the lower bandwidth requirement to stop the aircraft in a precise way. It can be seen that the output loop measures the shaft positions, and then provides a pair of torque commands. In its simplest form, accelerating torque commands can be used to reduce the impact effects of the aircraft engaging the arresting cable and then decelerating torque can be used to remove energy from the aircraft, and to ultimately bring it to a stop in a prescribed manner. Classic proportional and integral controller techniques can be applied for base performance and for highest performance, advanced optimal control methods such as Linear Quadratic Gaussian control with Loop Transfer Recovery (LQG/LTR) methods can be applied. Without loss of generality, any one of a number of known outer loop control methods can be applied and interconnected with the high performance current controllers described here for the AAG system. In addition to the motor torque commands, the outer loop also provides brake torque commands τ bp  and τ bs  to the AAG Plant. These are brake torques that are used if there is a motor failure or if there is a desired torque that exceeds the motor&#39;s capability. In cases such as this, the Outer Control Loop divides the desired torque commands between the motor and the brake as appropriate. It should be noted that the brake is not used unless necessary. 
     The individual torque commands are converted into appropriate dq-axis current commands (i qp * , i qs * , i dp * and i ds *), as required for the inputs to the inner loop motor controllers. The method of converting torque command to current commands depends upon the type of motor used. For permanent magnet synchronous motors, the direct axis current is often initially commanded to zero and the q-axis current is then a scaled version of the torque command, with constants that are known from the motor construction. For induction motors or synchronous motors without permanent magnets, the direct axis current is used to establish the rated rotor flux that gives the highest torque per amp and then the quadrature axis current is proportional to the desired torque. For many motor types, if the motor speed is high enough, then id is used to weaken the rotor flux and iq is used to control the torque level within the motor&#39;s capability. Using any of these known methods of converting torque commands to motor current commands, the motor controllers then provide measurement of the motor currents and, via feedback gains, determine the commanded motor voltage profiles necessary to regulate the motor currents to the desired values. The need for the AAG system to have high bandwidth, fast transient response, and wide operating range, along with the ability to minimize harmonic imbalances lead to the use of the electric motor controller with negative sequence harmonic suppression (NSHS) which was the subject of related U.S. Ser. No. 14/825,712. 
     In one embodiment, each of the port-side motor current controller and the starboard-side motor controller comprises: a positive sequence controller, the positive sequence controller comprising a PI filter with a dq input and a summer connected to an output of the PI filter; at least one negative sequence controller, the negative sequence controller connected to the dq input and the summer comprising a rotation transformer connected to an integrator block in series with an inverse rotational transformation block, one or more delay state feedback to counter control loop delays, said delay state feedback providing high bandwidth, low current overshoot, small current rise time and good current stability margins. 
     In another embodiment, each of the port-side motor current controller and the starboard-side motor controller comprises: a positive sequence controller, the positive sequence controller comprising a PI filter with a dq input and a summer connected to an output of the PI filter; at least one negative sequence controller, the negative sequence controller connected to the dq input and the summer comprising a rotation transformer connected to an integrator block in series with an inverse rotational transformation block; one or more delay state feedback to counter control loop delays, said delay state feedback providing high bandwidth, low current overshoot, small current rise time and good current stability margins; and one or more cross coupled gains between a d-axis and a q-axis, said cross coupled gains proportional to speed of a motor associated with said current controller, said motor is any of the following: a linear and rotary electric motor or an induction motor. 
     In yet another embodiment, each of the port-side motor current controller and the starboard-side motor current controller comprises: a positive sequence controller; and at least one negative sequence controller, where one or more error signals operated on by the positive sequence controller are transformed into at least one sequence reference frame and input to the at least one negative sequence controller with at least one targeted harmonic set by a harmonic factor value. 
     In another embodiment, each of the port-side motor current controller and the starboard-side motor current controller comprises: a positive sequence controller; at least one negative sequence controller; a rotational transformer, and where the rotational transformer transforms one or more error signals operated on by the positive sequence controller into at least one sequence reference frame for input to the at least one negative sequence controller with at least one targeted harmonic set by a harmonic factor value. 
     In yet another embodiment, each of the port-side motor current controller and the starboard-side motor current controller comprises: a positive sequence controller; at least one negative sequence controller; a rotational transformer, and wherein one or more error signals computed by taking a difference between measured and commanded currents are shared between the positive sequence controller and the at least one negative sequence controller, and wherein the rotational transformer transforms the one or more error signals operated on by the positive sequence controller into at least one sequence reference frame for input to the at least one negative sequence controller with at least one targeted harmonic set by a harmonic factor value. 
     In yet another embodiment, each of the port-side motor current controller and the starboard-side motor current controller comprises: a positive sequence controller; at least one negative sequence controller; a rotational transformer; and one or more cross coupled gains between a d-axis and a q-axis, the cross coupled gains proportional to speed of the motor; wherein one or more error signals computed by taking a difference between measured and commanded currents are shared between the positive sequence controller and the at least one negative sequence controller, and wherein the rotational transformer transforms the one or more error signals operated on by the positive sequence controller into at least one sequence reference frame for input to the at least one negative sequence controller with at least one targeted harmonic set by a harmonic factor value. 
     In yet another embodiment, each of the port-side motor current controller and the starboard-side motor current controller implements a method for higher bandwidth operation based on minimized interference between positive and negative components of a current controller, the method performed without additional filtering on measured currents to isolate positive and negative current components, the method comprising: identifying one or more error signals operated on by a positive sequence controller; transforming the one or more error signals into at least one negative sequence reference frame associated with at least one negative sequence controller; inputting transformed error signals to the negative sequence controller, and where undesirable interactions between the positive sequence controller and negative sequence controller is minimized by sharing error signals. 
     In yet another embodiment, each of the port-side motor current controller and the starboard-side motor current controller implements a method for higher bandwidth operation based on minimized interference between positive and negative components of a current controller, the method performed without additional filtering on measured currents to isolate positive and negative current components, the method comprising: identifying one or more error signals operated on by a positive sequence controller; transforming the one or more error signals into at least one negative sequence reference frame associated with at least one negative sequence controller and input to the at least one negative sequence controller with at least one targeted harmonic set by a harmonic factor value; inputting transformed error signals to the negative sequence controller, and where undesirable interactions between the positive sequence controller and negative sequence controller is minimized by sharing error signals. 
     In yet another embodiment, each of the port-side motor current controller and the starboard-side motor current controller implements a method for higher bandwidth operation based on minimized interference between positive and negative components of a current controller, the method performed without additional filtering on measured currents to isolate positive and negative current components, the method comprising: identifying one or more error signals operated on by a positive sequence controller; picking a harmonic factor value to suppress a positive or negative sequence harmonic caused by phase imbalance; transforming the one or more error signals into at least one negative sequence reference frame associated with at least one negative sequence controller and input to the at least one negative sequence controller with at least one targeted harmonic set by the harmonic factor value picked to suppress the positive or negative sequence harmonic caused by phase imbalance; inputting transformed error signals to the negative sequence controller, and where undesirable interactions between the positive sequence controller and negative sequence controller is minimized by sharing error signals. 
     The various embodiments described above are provided by way of illustration only and should not be construed to limit the scope of the disclosure. Those skilled in the art will readily recognize various modifications and changes that may be made to the principles described herein without following the example embodiments and applications illustrated and described herein, and without departing from the spirit and scope of the disclosure. 
     While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination. 
     CONCLUSION 
     A system and method has been shown in the above embodiments for the effective implementation of a control system connected to an arresting gear system having an outer control loop and a plurality of inner current control loops. While various preferred embodiments have been shown and described, it will be understood that there is no intent to limit the invention by such disclosure, but rather, it is intended to cover all modifications falling within the spirit and scope of the invention, as defined in the appended claims.