Patent Publication Number: US-9887322-B2

Title: Light-emitting device

Description:
REFERENCE TO RELATED APPLICATION 
     This application is a divisional application of U.S. patent application Ser. No. 14/953,876 entitled “LIGHT-EMITTING DEVICE”, filed on Nov. 30, 2015, which is a divisional application of U.S. patent application Ser. No. 13/421,898 entitled “LIGHT-EMITTING DEVICE”, filed on Mar. 16, 2012, the contents of which is incorporated herein by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     The application relates to a light-emitting device, and more particularly, to a light-emitting device with a plurality of buried electrodes. 
     DESCRIPTION OF BACKGROUND ART 
     The light-emitting diode (LED) is a solid state semiconductor device, which has been broadly used as a light-emitting device. The light-emitting device structure comprises a p-type semiconductor layer, an n-type semiconductor layer, and an active layer. The active layer is formed between the p-type semiconductor layer and the n-type semiconductor layer. The structure of the light-emitting device generally comprises III-V group compound semiconductor such as gallium phosphide, gallium arsenide, or gallium nitride. The light-emitting principle of the LED is the transformation of electrical energy to optical energy by applying electrical current to the p-n junction to generate electrons and holes. Then, the LED emits light when the electrons and the holes combine. 
       FIG. 1A  illustrates a conventional light-emitting device  1   a . The light-emitting device  1   a  comprises a substrate  15   a ; a semiconductor stack  10   a  comprising a first type semiconductor layer  13   a , a second type semiconductor layer  11   a  and an active layer  12   a  formed between the first type semiconductor layer  13   a  and the second type semiconductor layer  11   a ; a first electrode  18   a  electrically connected to the first type semiconductor layer  13   a ; and a second electrode  19   a  electrically connected to the second type semiconductor layer  11   a . The material of the first electrode  18   a  and the second electrode  19   a  comprises metal or metal alloy. As illustrated in  FIG. 1A , the first electrode  18   a  is formed on a top surface  17   a  of the light-emitting device  1   a . The electrical current from the first electrode  18   a  is not dispersed uniformly in the first type semiconductor layer  13   a  of the light-emitting device  1   a.    
       FIG. 1B  illustrates another example of a conventional light-emitting device  1   b . The light-emitting device  1   b  comprises a substrate  15   b ; a semiconductor stack  10   b  comprising a first type semiconductor layer  13   b , a second type semiconductor layer  11   b  and an active layer  12   b  formed between the first type semiconductor layer  13   b  and the second type semiconductor layer  11   b ; a first electrode  18   b  electrically connected to the first type semiconductor layer  13   b ; a second electrode  19   b  electrically connected to the second type semiconductor layer  11   b ; and a conductive layer  16   b  formed between the first type semiconductor layer  13   b  and the first electrode  18   b . The material of the first electrode  18   b  and the second electrode  19   b  comprises metal or metal alloy. 
     As illustrated in  FIG. 1B , the conductive layer  16   b  is formed on the first type semiconductor layer  13   b  and the first electrode  18   b  is formed on a top surface  17   b  of the conductive layer  16   b . The material of the conductive layer  16   b  comprises thin metal or metal alloy. The conductive layer  16   b  is used to improve the electrical current spreading. However, the transmittance of the conductive layer  16   b  is low, and the light emitting efficiency of the light-emitting device  1   b  is affected. 
     SUMMARY OF THE DISCLOSURE 
     A light-emitting device of an embodiment of the present disclosure comprises a substrate; a semiconductor stack comprising a first type semiconductor layer, a second type semiconductor layer and an active layer formed between the first type semiconductor layer and the second type semiconductor layer, wherein the first type semiconductor layer comprises a non-planar roughened surface; a bonding layer formed between the substrate and the semiconductor stack; and multiple recesses each comprising a bottom surface lower than the non-planar roughened surface; and multiple buried electrodes physically buried in the first type semiconductor layer, wherein the multiple buried electrodes are formed in the multiple recesses respectively, and one of the multiple buried electrodes comprises an upper surface; wherein an upper surface of the buried electrode and the non-planar roughened surface of the first type semiconductor layer are substantially on the same plane. 
     A light-emitting device of an embodiment of the present disclosure comprises a substrate; a semiconductor stack comprising a first type semiconductor layer, a second type semiconductor layer and an active layer formed between the first type semiconductor layer and the second type semiconductor layer wherein the first type semiconductor layer comprises a top surface; a bonding layer formed between the substrate and the semiconductor stack; multiple recesses recessed from the top surface toward the active layer; and multiple buried electrodes in the multiple recesses respectively, wherein one of the multiple buried electrodes comprises an upper surface, and the upper surface of the buried electrode and the top surface of the first type semiconductor layer are substantially on the same plane. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  illustrates a cross-sectional diagram of a conventional light-emitting device; 
         FIG. 1B  illustrates a cross-sectional diagram of a conventional light-emitting device; 
         FIG. 2  illustrates a cross-sectional diagram of a light-emitting device according to the first embodiment of the present disclosure; 
         FIGS. 3A to 3D  illustrate a process flow for manufacturing the light-emitting device according to an embodiment of the present disclosure; 
         FIGS. 4A to 4C  illustrate cross-sectional diagrams of a plurality of buried electrodes in a light-emitting device according to the first embodiment of the present disclosure; 
         FIGS. 5A to 5I  illustrate cross-sectional diagrams of a plurality of buried electrodes in a light-emitting device according to the first embodiment of the present disclosure; 
         FIG. 6  illustrates a cross-sectional diagram of a light-emitting device according to the second embodiment of the present disclosure; 
         FIGS. 7A to 7B  illustrate cross-sectional diagrams of a plurality of buried electrodes in a light-emitting device according to the second embodiment of the present disclosure; 
         FIG. 8  illustrates a cross-sectional diagram of a light-emitting device according to the third embodiment of the present disclosure; and 
         FIGS. 9A to 9B  illustrate cross-sectional diagrams of a plurality of buried electrodes in a light-emitting device according to the third embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The embodiment of the disclosure is illustrated in detail, and is plotted in the drawings. The same or the similar part is illustrated in the drawings and the specification with the same number. 
       FIG. 2  illustrates a cross-sectional diagram of a light-emitting device  2  according to the first embodiment of the present disclosure. The light-emitting device  2  comprises a substrate  27 ; a semiconductor stack  20  comprising a first type semiconductor layer  23 , a second type semiconductor layer  21  and an active layer  22  formed between the first type semiconductor layer  23  and the second type semiconductor layer  21 ; a bonding layer  25  formed between the substrate  27  and the semiconductor stack  20 ; a first electrode  28  electrically connected to the first type semiconductor layer  23 ; a second electrode  29  electrically connected to the second type semiconductor layer  21 ; and a plurality of buried electrodes  24  physically buried in the first type semiconductor layer  23  and electrically connected to the first electrode  28 . 
     The material of the semiconductor stack  20  comprises III-V group based semiconductor material such as InGaN, AlGaAs, or AlGaInP. The semiconductor stack  20  is epitaxially grown on a growth substrate (not shown). The method of forming each layer of the semiconductor stack  20  is not particularly limited. Besides a metal organic chemical vapor deposition method (MOCVD method), each layer of the semiconductor stack  20  may be formed by a known method such as a molecular beam epitaxy method (MBE method), a hydride vapor phase epitaxy method (HVPE method), a sputtering method, an ion-plating method and an electron showering method. 
     The plurality of buried electrodes  24  buried in the first type semiconductor layer  23  increases the contact area between the buried electrode  24  and the first type semiconductor layer  23 . Each of the plurality of the buried electrode  24  electrically connected to each other with an extension electrode (not shown). With the buried electrode  24 , the contact area between the buried electrode  24  and the first type semiconductor layer  23  is increased and an electrical current is injected into the first type semiconductor layer  23  uniformly. 
     A trench  200  is formed in the semiconductor stack  20  by etching process. A sidewall  200   a  of the trench  200  is insulated from the semiconductor stack  20  with dielectric materials such as SiO 2  and Si 3 N 4 . A conductive channel is formed by filling conductive material in the trench  200 , wherein the conductive material can be metal or metal alloy, or a transparent conductive material like ITO or ZnO. The materials of the plurality of buried electrodes  24  and the first electrode  28  comprise conductive materials such as metal or metal alloy, and transparent conductive materials such as ITO or ZnO. The materials of the plurality of buried electrodes  24 , the first electrode  28  and the trench  200  are the same or different from each other. The plurality of buried electrodes  24  and the first electrode  28  are electrically connected via the conductive channel. The first electrode  28  and the second electrode  29  are formed on the same side of the semiconductor stack  20  opposite to a top surface  23   a  of the first type semiconductor layer  23 . The first electrode  28  and the second electrode  29  are isolated from each other by an isolation layer  200   b . The material of the isolation layer  200   b  comprises dielectric material such as SiO 2  and Si 3 N 4 . 
     As shown in  FIG. 2 , the substrate  27  is a transparent substrate. A light emitted from the active layer  22  can be emitted out through the transparent substrate  27 . The material of the substrate  27  can be sapphire, glass, GaP, ZnSe and SiC. The substrate  27  is attached to the first type semiconductor layer  23  by the bonding layer  25 . The material of the bonding layer  25  can be transparent material such as epoxy, polyimide (PI), perfluorocyclobutane (PFCB), benzocyclobutene (BCB), spin-on glass (SOG) and silicone. 
     When the light-emitting device  2  is operated under a high electrical current, the thickness of the buried electrode  24  is preferred to be thick with a range of about 2˜6 μm to reduce the sheet resistance of the light-emitting device  2  and increase the device reliability. As shown in  FIG. 2 , when the light emitted from the active layer  22  passes through the bonding layer  25 , part of the light is absorbed by the bonding layer  25 . In order to reduce the thickness H 2   a  of the bonding layer  25 , improve the light emission efficiency of the light-emitting device  2  and maintain the thickness of the buried electrode  24  in a range of about 2˜6 μm, the plurality of buried electrodes  24  is buried in the first type semiconductor layer  23 . The first type semiconductor layer  23  comprises the top surface  23   a  and a plurality of recesses  24   a . Each of the plurality of recesses  24   a  comprises a bottom surface  24   b  lower than the top surface  23   a  of the first type semiconductor layer  23 . The conductive materials such as metal or metal alloy, or the transparent conductive materials such as ITO or ZnO are formed in the plurality of recesses  24   a  to form the plurality of buried electrodes  24 . The conductive materials or the transparent conductive materials can be formed in the plurality of recesses  24   a  by electron beam evaporation, physical vapor deposition or sputter deposition. 
       FIGS. 3A-3D  illustrate a process flow for manufacturing a light-emitting device  3  according to an embodiment of the present disclosure. As shown in  FIGS. 3A-3D , a photoresist layer  31  formed on a top surface  35  of a semiconductor stack  30  is used to define the pattern of a plurality of buried electrodes  34  of the light-emitting device  3  by a conventional lithography process. As shown in  FIG. 3B , a plurality of recesses  37  is formed by etching the semiconductor stack  30  through an area  32  not protected by the photoresist layer  31 . A depth D 2  of each of the plurality of recesses  37  is controlled by dry etching process parameters such as etch time, etchant gas flow rate and etchant gas type. A wet etch process is optionally performed to clean the surface containments of the plurality of recesses  37 , and flatten a sidewall surface  37   s  and a bottom surface  37   b  of each of the plurality of recesses  37 . As shown in  FIG. 3C , a conductive material  33  is formed in the plurality of recesses  37  and on a top surface  36  of the photoresist layer  31 . The adhesion between the semiconductor stack  30  and the conductive material  33  is improved because of the flat sidewall surface  37   s  and bottom surface  37   b  of each of the plurality of recesses  37 . As shown in  FIG. 3D , the photoresist layer  31  is lifted off by the conventional etch method and the plurality of buried electrodes  34  is buried in the semiconductor stack  30 . The thickness T 3  of each of the plurality of buried electrodes  34  is controlled by thin-film deposition process such as deposition rate and deposition time. After the pattern definition process and the deposition process as shown in  FIGS. 3A-3D  are finished, the plurality of buried electrodes  34  comprising an upper surface  341  is formed in the plurality of recesses  37  correspondingly. 
     As shown in  FIG. 2 , the plurality of buried electrodes  24  is buried in the first type semiconductor layer  23  by the method illustrated in  FIGS. 3A-3D . Each of the plurality of buried electrodes  24  comprises an embedded portion  242  formed under the top surface  23   a  of the first type semiconductor layer  23  and an exposed portion  241  formed above the top surface  23   a  of the first type semiconductor layer  23 . The embedded portion  242  is physically buried in the first type semiconductor layer  23  and electrically connected to the first type semiconductor layer  23 . The thickness H 2  of the exposed portion of each of the plurality of buried electrodes  24  is reduced compared with that of the electrode not buried in the first type semiconductor layer. Because the thickness H 2  of the exposed portion of each of the plurality of buried electrodes  24  is reduced, the thickness H 2   a  of the bonding layer  25  used to attach the substrate  27  to the semiconductor stack  20  is also reduced. 
     The thickness H 2   a  of the bonding layer  25  is related with the thickness H 2  of the exposed portion  241  of each of the plurality of buried electrodes  24 . As the thickness H 2  of the exposed portion  241  is increased, the thickness H 2   a  of the bonding layer  25  is preferred to be increased to provide adhesion between the substrate  27  and the semiconductor stack  20 .  FIGS. 4A-4C  illustrate different examples of the plurality of buried electrodes  24  in the light-emitting device  2  according to the first embodiment of the present disclosure. 
       FIG. 4A  illustrates an example of a cross-sectional diagram of the plurality of buried electrodes  24  in the light-emitting device  2  according to the first embodiment of the present disclosure. As shown in  FIG. 4A , an upper surface  443  of each of the plurality of buried electrodes  24  is higher than the top surface  23   a  of the first type semiconductor layer  23 . Each of the plurality of buried electrodes  24  comprises the embedded portion  242  formed under the top surface  23   a  of the first type semiconductor layer  23  and the exposed portion  241  formed above the top surface  23   a  of the first type semiconductor layer  23 . The size of the embedded portion  242  is smaller than that of the exposed portion  241 . 
       FIG. 4B  illustrates another example of a cross-sectional diagram of the plurality of buried electrodes  24  in the light-emitting device  2  according to the first embodiment of the present disclosure. The size of the embedded portion  242  is equal to that of the exposed portion  241 . 
       FIG. 4C  illustrates another example of a cross-sectional diagram of the plurality of buried electrodes  24  in the light-emitting device  2  according to the first embodiment of the present disclosure. The size of the embedded portion  242  is larger than that of the exposed portion  241 . 
     As shown in  FIG. 2 , in order to increase the light emission efficiency of the light-emitting device  2 , the top surface  23   a  of the first type semiconductor layer  23  can be a non-planar surface such as the one of the cross-sectional diagrams illustrated in  FIGS. 5A-5I . 
       FIG. 5A  illustrates an example of a cross-sectional diagram of the plurality of buried electrodes  24  in the light-emitting device  2  according to the first embodiment of the present disclosure. The top surface  23   a  of the first type semiconductor layer  23  is a non-planar surface. In the present embodiment, the non-planar surface is a roughened surface  23   a ′, and an average roughness of the roughened surface  23   a ′ is greater than 0.05 μm. The light emission efficiency of the light-emitting device  2  illustrated in  FIG. 2  is increased by the roughened surface  23   a ′. As shown in  FIG. 5A , the upper surface  443  of each of the plurality of buried electrodes  24  is higher than the roughened surface  23   a ′ of the first type semiconductor layer  23 . Each of the plurality of buried electrodes  24  comprises the embedded portion  242  formed under the top surface  23   a  of the first type semiconductor layer  23  and the exposed portion  241  formed above the top surface  23   a  of the first type semiconductor layer  23 . The embedded portion  242  is physically buried in the first type semiconductor layer  23  and electrically connected to the first type semiconductor layer  23 . The size of the embedded portion  242  is smaller than that of the exposed portion  241 . 
       FIG. 5B  illustrates another example of a cross-sectional diagram of the plurality of buried electrodes  24  in the light-emitting device  2  according to the first embodiment of the present disclosure. The top surface  23   a  of the first type semiconductor layer  23  is the non-planar surface. In the present embodiment, the non-planar surface is the roughened surface  23   a ′, and the average roughness of the roughened surface  23   a ′ is greater than 0.05 μm. The light emission efficiency of the light-emitting device  2  is increased by the roughened surface  23   a ′. As shown in  FIG. 5B , the upper surface  443  of each of the plurality of buried electrodes  24  is higher than the roughened surface  23   a ′ of the first type semiconductor layer  23 . Each of the plurality of buried electrodes  24  comprises the embedded portion  242  formed under the top surface  23   a  of the first type semiconductor layer  23  and the exposed portion  241  formed above the top surface  23   a  of the first type semiconductor layer  23 . The embedded portion  242  is physically buried in the first type semiconductor layer  23  and electrically connected to the first type semiconductor layer  23 . The size of the embedded portion  242  is equal to that of the exposed portion  241 . 
       FIG. 5C  illustrates another example of a cross-sectional diagram of the plurality of buried electrodes  24  in the light-emitting device  2  according to the first embodiment of the present disclosure. The top surface  23   a  of the first type semiconductor layer  23  is the non-planar surface. In the embodiment, the non-planar surface is the roughened surface  23   a ′, and the average roughness of the roughened surface  23   a ′ is greater than 0.05 μm. The light emission efficiency of the light-emitting device  2  is increased by the roughened surface  23   a ′. As shown in  FIG. 5C , the upper surface  443  of each of the plurality of buried electrodes  24  is higher than the roughened surface  23   a ′ of the first type semiconductor layer  23 . Each of the plurality of buried electrodes  24  comprises the embedded portion  242  formed under the top surface  23   a  of the first type semiconductor layer  23  and the exposed portion  241  formed above the top surface  23   a  of the first type semiconductor layer  23 . The embedded portion  242  is physically buried in the first type semiconductor layer  23  and electrically connected to the first type semiconductor layer  23 . The size of the embedded portion  242  is larger than that of the exposed portion  241 . 
     When the top surface  23   a  of the first type semiconductor layer  23  is the roughened surface  23   a ′ and the upper surface  443  of each of the plurality of buried electrodes  24  is higher than the roughened surface  23   a ′ of the first type semiconductor layer  23  as illustrated in  FIGS. 5A-5C , the thickness H 2   a  of the bonding layer  25  is determined according to the thickness H 2  of the exposed portion  241 . 
       FIG. 5D  illustrates another example of a cross-sectional diagram of the plurality of buried electrodes  24  in the light-emitting device  2  according to the first embodiment of the present disclosure. The top surface  23   a  of the first type semiconductor layer  23  is the non-planar surface. In the present embodiment, the non-planar surface is the roughened surface  23   a ′, and the average roughness of the roughened surface  23   a ′ is greater than 0.05 μm. The light emission efficiency of the light-emitting device  2  is increased by the roughened surface  23   a ′. As shown in  FIG. 5D , the upper surface  443  of each of the plurality of buried electrodes  24  and the roughened surface  23   a ′ of the first type semiconductor layer  23  are substantially on the same plane. Each of the plurality of buried electrodes  24  comprises the embedded portion  242  formed under the top surface  23   a  of the first type semiconductor layer  23  and the exposed portion  241  formed above the top surface  23   a  of the first type semiconductor layer  23 . The embedded portion  242  is physically buried in the first type semiconductor layer  23  and electrically connected to the first type semiconductor layer  23 . The size of the embedded portion  242  is smaller than that of the exposed portion  241 . 
       FIG. 5E  illustrates another example of a cross-sectional diagram of the plurality of buried electrodes  24  in the light-emitting device  2  according to the first embodiment of the present disclosure. The top surface  23   a  of the first type semiconductor layer  23  is the non-planar surface. In the present disclosure, the non-planar surface is the roughened surface  23   a ′, and the average roughness of the roughened surface  23   a ′ is greater than 0.05 μm. The light emission efficiency of the light-emitting device  2  is increased by the roughened surface  23   a ′. As shown in  FIG. 5E , the upper surface  443  of each of the plurality of buried electrodes  24  and the roughened surface  23   a ′ of the first type semiconductor layer  23  are substantially on the same plane. Each of the plurality of buried electrodes  24  comprises the embedded portion  242  formed under the top surface  23   a  of the first type semiconductor layer  23  and the exposed portion  241  formed above the top surface  23   a  of the first type semiconductor layer  23 . The embedded portion  242  is physically buried in the first type semiconductor layer  23  and electrically connected to the first type semiconductor layer  23 . The size of the embedded portion  242  is larger than that of the exposed portion  241 . 
       FIG. 5F  illustrates another example of a cross-sectional diagram of the plurality of buried electrodes  24  in the light-emitting device  2  according to the first embodiment of the present disclosure. The top surface  23   a  of the first type semiconductor layer  23  is the non-planar surface. In the present embodiment, the non-planar surface is the roughened surface  23   a ′, and the average roughness of the roughened surface  23   a ′ is greater than 0.05 μm. The light emission efficiency of the light-emitting device  2  is increased by the roughened surface  23   a ′. As shown in  FIG. 5F , the upper surface  443  of each of the plurality of buried electrodes  24  and the roughened surface  23   a ′ of the first type semiconductor layer  23  are substantially on the same plane. Each of the plurality of buried electrodes  24  comprises the embedded portion  242  formed under the top surface  23   a  of the first type semiconductor layer  23  and the exposed portion  241  formed above the top surface  23   a  of the first type semiconductor layer  23 . The embedded portion  242  is physically buried in the first type semiconductor layer  23  and electrically connected to the first type semiconductor layer  23 . The size of the embedded portion  242  is equal to that of the exposed portion  241 . 
     When the top surface  23   a  of the first type semiconductor layer  23  is the roughened surface  23   a ′, and the upper surface  443  of each of the plurality of buried electrodes  24  and the roughened surface  23   a ′ of the first type semiconductor layer  23  are substantially on the same plane as illustrated in  FIGS. 5D-5F , the thickness H 2   a  of the bonding layer  25  is preferred at least larger than 0.05 μm. 
       FIG. 5G  illustrates another example of a cross-sectional diagram of the plurality of buried electrodes  24  in the light-emitting device  2  according to the first embodiment of the present disclosure. The top surface  23   a  of the first type semiconductor layer  23  is the non-planar surface. In the present embodiment, the non-planar surface is the roughened surface  23   a ′, and the average roughness of the roughened surface  23   a ′ is greater than 0.05 μm. The light emission efficiency of the light-emitting device  2  is increased by the roughened surface  23   a ′. As shown in  FIG. 5G , the upper surface  443  of each of the plurality of buried electrodes  24  is lower than the roughened surface  23   a ′ of the first type semiconductor layer  23 . Each of the plurality of buried electrodes  24  comprises the embedded portion  242  formed under the top surface  23   a  of the first type semiconductor layer  23  and the exposed portion  241  formed above the top surface  23   a  of the first type semiconductor layer  23 . The embedded portion  242  is physically buried in the first type semiconductor layer  23  and electrically connected to the first type semiconductor layer  23 . The size of the embedded portion  242  is smaller than that of the exposed portion  241 . 
       FIG. 5H  illustrates another example of a cross-sectional diagram of the plurality of buried electrodes  24  in the light-emitting device  2  according to the first embodiment of the present disclosure. The top surface  23   a  of the first type semiconductor layer  23  is the non-planar surface. In the present embodiment, the non-planar surface is the roughened surface  23   a ′, and the average roughness of the roughened surface  23   a ′ is greater than 0.05 μm. The light emission efficiency of the light-emitting device  2  is increased by the roughened surface  23   a ′. As shown in  FIG. 5H , the upper surface  443  of each of the plurality of buried electrodes  24  is lower than the roughened surface  23   a ′ of the first type semiconductor layer  23 . Each of the plurality of buried electrodes  24  comprises the embedded portion  242  formed under the top surface  23   a  of the first type semiconductor layer  23  and the exposed portion  241  formed above the top surface  23   a  of the first type semiconductor layer  23 . The embedded portion  242  is physically buried in the first type semiconductor layer  23  and electrically connected to the first type semiconductor layer  23 . The size of the embedded portion  242  is equal to that of the exposed portion  241 . 
       FIG. 5I  illustrates another example of a cross-sectional diagram of the plurality of buried electrodes  24  in the light-emitting device  2  according to the first embodiment of the present disclosure. The top surface  23   a  of the first type semiconductor layer  23  is the non-planar surface. In the present embodiment, the non-planar surface is the roughened surface  23   a ′, and the average roughness of the roughened surface  23   a ′ is greater than 0.05 μm. The light emission efficiency of the light-emitting device  2  is increased by the roughened surface  23   a ′. As shown in FIG. SI, the upper surface  443  of each of the plurality of buried electrodes  24  is lower than the roughened surface  23   a ′ of the first type semiconductor layer  23 . Each of the plurality of buried electrodes  24  comprises the embedded portion  242  formed under the top surface  23   a  of the first type semiconductor layer  23  and the exposed portion  241  formed above the top surface  23   a  of the first type semiconductor layer  23 . The embedded portion  242  is physically buried in the first type semiconductor layer  23  and electrically connected to the first type semiconductor layer  23 . The size of the embedded portion  242  is larger than that of the exposed portion  241 . 
     When the top surface  23   a  of the first type semiconductor layer  23  is the roughened surface  23   a ′ and the upper surface  443  of each of the plurality of buried electrodes  24  is lower than the roughened surface  23   a ′ of the first type semiconductor layer  23  as illustrated in  FIGS. 5G-5I , the thickness H 2   a  of the bonding layer  25  is preferred at least larger than 0.05 μm. 
       FIG. 6  illustrates a cross-sectional diagram of a light-emitting device  6  according to the second embodiment of the present disclosure. The light-emitting device  6  comprises a substrate  67 ; a semiconductor stack  60  comprising a first type semiconductor layer  63 , a second type semiconductor layer  61 , and an active layer  62  formed between the first type semiconductor layer  63  and the second type semiconductor layer  61 ; a bonding layer  65  formed between the substrate  67  and the semiconductor stack  60 ; a first electrode  68  electrically connected to the first type semiconductor layer  63 ; a second electrode  69  electrically connected to the second type semiconductor layer  61 ; and a plurality of buried electrodes  64  physically buried in the first type semiconductor layer  63  and electrically connected to the first electrode  68 . 
     The material of the semiconductor stack  60  comprises III-V group based semiconductor material such as InGaN, AlGaAs, or AlGaInP. The semiconductor stack  60  is epitaxially grown on a growth substrate (not shown). The method of forming each layer of the semiconductor stack  60  is not particularly limited. Besides a metal organic chemical vapor deposition method (MOCVD method), each layer of the semiconductor stack  60  may be formed by a known method such as a molecular beam epitaxy method (MBE method), a hydride vapor phase epitaxy method (HVPE method), a sputtering method, an ion-plating method and an electron showering method. 
     The plurality of buried electrodes  64  buried in the first type semiconductor layer  63  increases the contact area between the buried electrode  64  and the first type semiconductor layer  63 . Each of the plurality of the buried electrode  64  electrically connected to each other with an extension electrode (not shown). With the buried electrode  64 , the contact area between the buried electrode  64  and the first type semiconductor layer  63  is increased and an electrical current is injected into the first type semiconductor layer  63  uniformly. 
     A trench  600  is formed in the semiconductor stack  60  by etching process. A sidewall  600   a  of the trench  600  is insulated from the semiconductor stack  60  with dielectric materials such as SiO 2  or Si 3 N 4 . A conductive channel is formed by filling conductive material in the trench  600 , wherein the conductive material can be metal or metal alloy, or a transparent conductive material like ITO or ZnO. The materials of the plurality of buried electrodes  64  and the first electrode  68  comprise conductive materials such as metal or metal alloy, and transparent conductive materials such as ITO or ZnO. The materials of the plurality of buried electrodes  64 , the first electrode  68  and the trench  600  are the same or different from each other. The plurality of buried electrodes  64  and the first electrode  68  are electrically connected via the conductive channel. In the present embodiment, the first electrode  68  and the second electrode  69  are formed on the same side of the semiconductor stack  60  opposite to a top surface  63   a  of the first type semiconductor  63 . The first electrode  68  and the second electrode  69  are isolated from each other by an isolation layer  600   b . The material of the isolation layer  600   b  comprises dielectric material such as SiO 2  or Si 3 N 4 . 
     As shown in  FIG. 6 , the substrate  67  is a transparent substrate. A light emitted from the active layer  62  can be emitted out through the transparent substrate  67 . The material of the substrate  67  can be sapphire, glass, GaP, ZnSe, and SiC. The substrate  67  is attached to the first type semiconductor layer  63  by the bonding layer  65 . The material of the bonding layer  65  can be transparent material such as epoxy, polyimide (PI), perfluorocyclobutane (PFCB), benzocyclobutene (BCB), spin-on glass (SOG) and silicone. 
     When the light-emitting device  6  is operated under a high electrical current, the thickness of the buried electrode  64  is preferred to be thick with a range of about 2˜6 μm to reduce the sheet resistance of the light-emitting device  6  and increase the device reliability. As shown in  FIG. 6 , when the light emitted from the active layer  62  passes through the bonding layer  65 , part of the light is absorbed by the bonding layer  65 . In order to reduce the thickness H 6   a  of the bonding layer  65 , improve the light emission efficiency of the light-emitting device  6 , and maintain the thickness of the buried electrode  64  in a range of about 2˜6 μm, the plurality of buried electrodes  64  is buried in the first type semiconductor layer  63 . The first type semiconductor layer  63  comprises the top surface  63   a  and a plurality of recesses  64   a . Each of the plurality of recesses  64   a  comprises a bottom surface  64   b  lower than the top surface  63   a  of the first type semiconductor layer  63 . The conductive materials such as metal or metal alloy, or the transparent conductive materials such as ITO or ZnO are formed in the plurality of recesses  64   a  to form the plurality of buried electrodes  64 . The conductive materials or the transparent conductive materials can be formed in the plurality of recesses  64   a  by electron beam evaporation, physical vapor deposition or sputter deposition. The upper surface  64   c  of each of the plurality of the buried electrodes  64  and the top surface  63   a  of the first type semiconductor layer  63  are substantially on the same plane. 
       FIG. 7A  illustrates an example of a cross-sectional diagram of the plurality of buried electrodes  64  in the light-emitting device  6  according to the second embodiment of the present disclosure. As shown in  FIG. 7A , the first type semiconductor layer  63  comprises the top surface  63   a  and the plurality of recesses  64   a . Each of the plurality of recesses  64   a  comprises the bottom surface  64   b  lower than the top surface  63   a  of the first type semiconductor layer  63 . The conductive materials such as metal or metal alloy, and the transparent conductive materials such as ITO or ZnO are formed in the plurality of recesses  64   a  to form the plurality of buried electrodes  64 . The upper surface  64   c  of each of the plurality of buried electrodes  64  and the top surface  63   a  of the first type semiconductor layer  63  are substantially on the same plane. 
     As shown in  FIG. 6 , in order to increase the light emission efficiency of the light-emitting device  6 , the top surface  63   a  of the first type semiconductor layer  63  can be a non-planar surface as illustrated in  FIG. 7B .  FIG. 7B  illustrates a cross-sectional diagram of the plurality of buried electrodes  64  in the light-emitting device  6  according to the second embodiment of the present disclosure. As shown in  FIG. 7B , the first type semiconductor layer  63  comprises the top surface  63   a  and the plurality of recesses  64   a . The top surface  63   a  is a non-planar surface. The non-planar surface is a roughened surface  63   a ′ and an average roughness of the roughened surface is greater than 0.05 μm. The light emission efficiency of the light-emitting device  6  is increased by the roughened surface  63   a ′. Each of the plurality of recesses  64   a  comprises the bottom surface  64   b  lower than the top surface  63   a  of the first type semiconductor layer  63 . The conductive materials such as metal or metal alloy, and the transparent conductive materials such as ITO or ZnO are formed in the plurality of recesses  64   a  to form the plurality of buried electrodes  64 . The upper surface  64   c  of each of the plurality of the buried electrodes  64  is lower than the roughened surface  63   a ′ of the first type semiconductor layer  63 . 
     As shown in  FIG. 6 , the plurality of buried electrodes  64  is totally buried in the first type semiconductor layer  63 . The top surface  63   a  of the first type semiconductor layer  63  and the upper surface  64   c  of each of the plurality of the buried electrode  64  are substantially on the same plane. In the second embodiment illustrated in  FIG. 6 , the plurality of buried electrodes  64  is totally buried in the first type semiconductor layer  63  and there is no exposed portion of each of the plurality of buried electrodes  64 . Thus, the thickness H 6   a  of the bonding layer  65  used to attach the substrate  67  to the semiconductor stack  60  is reduced. 
       FIG. 8  illustrates a cross-sectional diagram of a light-emitting device  8  according to the third embodiment of the present disclosure. The light-emitting device  8  comprises a substrate  87 ; a semiconductor stack  80  comprising a first type semiconductor layer  83 , a second type semiconductor layer  81 , and an active layer  82  formed between the first type semiconductor layer  83  and the second type semiconductor layer  81 ; a bonding layer  85  formed between the substrate  87  and the semiconductor stack  80 ; a first electrode  88  electrically connected to the first type semiconductor layer  83 ; a second electrode  89  electrically connected to the second type semiconductor layer  81 ; and a plurality of buried electrodes  84  physically buried in the first type semiconductor layer  83  and electrically connected to the first electrode  88 . 
     The material of the semiconductor stack  80  comprises III-V group based semiconductor material such as InGaN, AlGaAs, or AlGaInP. The semiconductor stack  80  is epitaxially grown on a growth substrate (not shown). The method of forming each layer of the semiconductor stack  80  is not particularly limited. Besides a metal organic chemical vapor deposition method (MOCVD method), each layer of the semiconductor stack  80  may be formed by a known method such as a molecular beam epitaxy method (MBE method), a hydride vapor phase epitaxy method (HVPE method), a sputtering method, an ion-plating method and an electron showering method. 
     The plurality of buried electrodes  84  buried in the first type semiconductor layer  83  increases the contact area between the buried electrode  84  and the first type semiconductor layer  83 . Each of the plurality of the buried electrode  84  electrically connected to each other with an extension electrode (not shown). With the buried electrode  84 , the contact area between the buried electrode  84  and the first type semiconductor layer  83  is increased and an electrical current is injected into the first type semiconductor layer  83  uniformly. 
     A trench  800  is formed in the semiconductor stack  80  by etching process. A sidewall  800   a  of the trench  800  is insulated from the semiconductor stack  80  with dielectric materials such as SiO 2  or Si 3 N 4 . A conductive channel is formed by filling conductive material in the trench  800 , wherein the conductive material can be metal or metal alloy, or a transparent conductive material like ITO or ZnO. The materials of the plurality of buried electrodes  84  and the first electrode  88  comprise conductive materials such as metal or metal alloy, and transparent conductive materials such as ITO or ZnO. The materials of the plurality of buried electrodes  84 , the first electrode  88  and the trench  800  are the same or different from each other. The plurality of buried electrodes  84  and the first electrode  88  are electrically connected via the conductive channel. The first electrode  88  and the second electrode  89  are formed on the same side of the semiconductor stack  80  opposite to a top surface  83   a  of the first type semiconductor  83 . The first electrode  88  and the second electrode  89  are isolated from each other by an isolation layer  800   b . The material of the isolation layer  800   b  comprises dielectric material such as SiO 2  or Si 3 N 4 . 
     As shown in  FIG. 8 , the substrate  87  is a transparent substrate. A light emitted from the active layer  82  can be emitted out through the transparent substrate  87 . The material of the substrate  87  can be sapphire, glass, GaP, ZnSe, and SiC. The substrate  87  is attached to the first type semiconductor layer  83  by the bonding layer  85 . The material of the bonding layer  85  can be transparent material such as epoxy, polyimide (PI), perfluorocyclobutane (PFCB), benzocyclobutene (BCB), spin-on glass (SOG) and silicone. 
     When the light-emitting device  8  is operated under a high electrical current, the thickness of the buried electrode  84  is preferred to be thick with a range of about 2˜6 μm to reduce the sheet resistance of the light-emitting device  8  and increase the device reliability. As shown in  FIG. 8 , when the light emitted from the active layer  82  passes through the bonding layer  85 , part of the light is absorbed by the bonding layer  85 . In order to reduce the thickness H 8   a  of the bonding layer  85 , improve the light emission efficiency of the light-emitting device  8 , and maintain the thickness of the buried electrode  84  in a range of about 2˜6 μm, the plurality of buried electrodes  84  is buried in the first type semiconductor layer  83 . The first type semiconductor layer  83  comprises the top surface  83   a  and a plurality of recesses  84   a . Each of the plurality of recesses  84   a  comprises a bottom surface  84   b  lower than the top surface  83   a  of the first type semiconductor layer  83 . The conductive materials such as metal or metal alloy, or the transparent conductive materials such as ITO or ZnO are formed in the plurality of recesses  84   a  to form the plurality of buried electrodes  84 . The conductive materials or the transparent conductive materials can be formed in the plurality of recesses  84   a  by electron beam evaporation, physical vapor deposition or sputter deposition. The upper surface  84   c  of the buried electrode  84  is lower than the top surface  83   a  of the first type semiconductor layer  83 . 
     The plurality of buried electrodes  84  is buried in the first type semiconductor layer  83 .  FIG. 9A  illustrates a cross-sectional diagram of the plurality of buried electrodes  84  in the light-emitting device  8  according to the third embodiment of the present disclosure. As shown in  FIG. 9A , the first type semiconductor layer  83  comprises the top surface  83   a  and the plurality of recesses  84   a . Each of the plurality of recesses  84   a  comprises the bottom surface  84   b  lower than the top surface  83   a  of the first type semiconductor layer  83 . The conductive materials such as metal or metal alloy, and the transparent conductive materials such as ITO or ZnO are formed in the plurality of recesses  84   a  to form the plurality of buried electrodes  84 . The upper surface  84   c  of the buried electrode  84  is lower than the top surface  83   a  of the first type semiconductor layer  83 . 
     As shown in  FIG. 8 , in order to increase the light emission efficiency of the light-emitting device  8 , the top surface  83   a  of the first type semiconductor layer  83  can be a non-planar surface as illustrated in  FIG. 9B .  FIG. 9B  illustrates a cross-sectional diagram of the plurality of buried electrodes  84  in the light-emitting device  8  according to the third embodiment of the present disclosure. As shown in  FIG. 9B , the first type semiconductor layer  83  comprises the top surface  83   a  and the plurality of recesses  84   a . The top surface  83   a  is a non-planar surface. The non-planar surface is a roughened surface  83   a ′ and an average roughness of the roughened surface  83   a ′ is greater than 0.05 μm. The light emission efficiency of the light-emitting device  8  is increased by the roughened surface  83   a ′. Each of the plurality of recesses  84   a  comprises the bottom surface  84   b  lower than the top surface  83   a  of the first type semiconductor layer  83 . The conductive materials such as metal or metal alloy, and the transparent conductive materials such as ITO or ZnO are formed in the plurality of recesses  84   a  to form the plurality of buried electrodes  84 . The upper surface  84   c  of each of the plurality of the buried electrode  84  is lower than the roughened surface  83   a ′ of the first type semiconductor layer  83 . 
     As shown in  FIG. 8 , the plurality of buried electrodes  84  is totally buried in the first type semiconductor layer  83 . The upper surface  84   c  of the buried electrode  84  is lower than the top surface  83   a  of the first type semiconductor layer  83 . In the third embodiment illustrated in  FIG. 8 , the plurality of buried electrodes  84  is totally buried in the first type semiconductor layer  83  and there is no exposed portion of each of the plurality of buried electrodes  84 . Thus, the thickness H 8   a  of the bonding layer  85  used to attach the substrate  87  to the semiconductor stack  80  is reduced. 
     The principle and the efficiency of the present disclosure illustrated by the embodiments above are not the limitation of the disclosure. Any person having ordinary skill in the art can modify or change the aforementioned embodiments. Therefore, the protection range of the rights in the disclosure will be listed as the following claims.