Patent Publication Number: US-2015084895-A1

Title: Load driving method, load driving circuit, and application devices thereof

Description:
TECHNICAL FIELD 
     The present invention relates to the driving technologies, and in particular, to a load driving method, a load driving circuit, and application devices thereof. 
     BACKGROUND 
     At present, network communication technologies and multimedia technologies have created a colorful virtual world of rich visual and audile experience, which bring great joy to people while transmitting information. With high-speed development of the network towards bandwidth, transmission and rendering of haptic information has become a next target in the virtual reality technology, and is drawing attention of the science and technology field, industry field, and commerce field in the world. The haptic rendering technology, as a next generation virtual reality technology, has become a hotspot which is being researched and developed worldwide. The haptic rendering technology refers to: by controlling a physical effect prompt of a haptic display, generating a corresponding touch feeling when a finger touches the display, thereby implementing human-machine interaction with respect to haptic information. 
     As touch screens gradually replace mechanical keys in handheld consumer devices, due to lack of haptic responses, consumers are imposing requirements on timely responses. Adding the haptic response in the consumer devices may improve user experience. In addition, a haptic function may be designed and provided on the user interface, which is a new mainstream user interface for smartphones and other handheld consumer devices. 
     In an electronic haptic response system, a motor driving circuit is an essential component. A corresponding motor driving circuit needs to be designed according to the working voltage of the motor. When a single-terminal input motor driving circuit is employed, due to defects of an amplifier component in a voltage differential generation circuit for generating a driving voltage in the motor driving circuit, the generated driving voltage may be subjected to linear distortion. As a result, the driving voltage generated by the voltage differential generation circuit fails to be regulated to a desired voltage by regulating a duty cycle of an input signal. To be specific, a voltage applied on the motor fails to be effectively regulated to the working voltage of the motor. 
     SUMMARY 
     To solve the technical problem in the prior art, embodiments of the present invention provide a load driving method, a load driving circuit, and application devices thereof. 
     The technical solutions of the present invention are implemented as follows: 
     An embodiment of the present invention provides a load driving circuit, comprising a voltage differential generation circuit and a common mode voltage generation circuit; wherein: 
     the voltage differential generation circuit is configured to generate a driving voltage for driving a load; and 
     the common mode voltage generation circuit is configured to: when the voltage differential generation circuit generates the driving voltage for driving the load, regulate voltages output by a first output terminal and a second output terminal of the voltage differential generation circuit by the same voltage value. 
     An embodiment of the present invention provides a load driving method. The load driving method comprises: 
     when a voltage differential generation circuit generates a driving voltage for driving a load, regulating voltages output by a first output terminal and a second output terminal of the voltage differential generation circuit by the same voltage value. 
     An embodiment of the present invention provides a touch apparatus, comprising a touch screen and a load driving circuit, wherein the load driving circuit comprises a voltage differential generation circuit and a common mode voltage generation circuit; wherein: 
     the voltage differential generation circuit is configured to generate a driving voltage for driving a load; and 
     the common mode voltage generation circuit is configured to: when the voltage differential generation circuit generates the driving voltage for driving the load, regulate voltages at a first output terminal and a second output terminal of the voltage differential generation circuit by the same voltage value. 
     An embodiment of the present invention provides an electronic device, comprising: a main board, a housing, and a touch apparatus, the touch apparatus comprising a touch screen and a load driving circuit, wherein the load driving circuit comprises a voltage differential generation circuit and a common mode voltage generation circuit; wherein: 
     the voltage differential generation circuit is configured to generate a driving voltage for driving a load; and 
     the common mode voltage generation circuit is configured to: when the voltage differential generation circuit generates the driving voltage for driving the load, regulate voltages at a first output terminal and a second output terminal of the voltage differential generation circuit by the same voltage value. 
     According to the load driving method, the load driving circuit, and application devices thereof provided in the embodiments of the present invention, when the voltage differential generation circuit generates a driving voltage for driving a load, the common mode voltage generation circuit regulates voltages output by a first output terminal and a second output terminal of the voltage differential generation circuit by the same voltage value, such that a central value of a voltage output by the first output terminal and a voltage output by the second output terminal of the voltage differential generation circuit is effectively regulated. In this way, when a duty cycle of an input signal is within a range of 0 to 100%, the driving voltage generated by the voltage differential generation circuit is in a linear relation with the duty cycle of the input signal, thereby ensuring fidelity of an output signal. 
     In addition, the implementation solutions according to the embodiments of the present invention are simple, convenient, and easy to implement. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a schematic structural diagram of output stages of two amplifiers in a voltage differential generation circuit; 
         FIG. 2A  is a schematic structural diagram of a simulation result obtained by simulation using a conventional load driving circuit; 
         FIG. 2B  is a schematic structural diagram of a product test result after an integrated circuit is fabricated using the conventional load driving circuit; 
         FIG. 3  is a schematic structural diagram of a load driving circuit according to an embodiment of the present invention; 
         FIG. 4A  is a schematic structural diagram of a load driving circuit according to Embodiment 1 of the present invention; 
         FIG. 4B  is a schematic structural diagram of another load driving circuit according to Embodiment 1 of the present invention; 
         FIG. 5  is a schematic structural diagram of a load driving circuit according to Embodiment 2 of the present invention; 
         FIG. 6  is a schematic view of a simulation result obtained by simulation using a load driving circuit according to an embodiment of the present invention; and 
         FIG. 7  is a schematic view of a product test result after an integrated circuit is fabricated using a load driving circuit according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     At present, in the single-terminal input motor driving circuit designed according to the working voltage of the motor specified on the motor before delivery from factory, since two amplifier components in the voltage differential generation circuit for generating the driving voltage in the motor driving circuit are subjected to defects, that is, a metal-oxide-semiconductor field-effect transistor (MOSFET) as an output stage of the amplifier is in a deep linear region, the generated driving voltage may be subjected to linear distortion. As a result, when the driving voltage generated by the voltage differential generation circuit is regulated by regulating the duty cycle of the input signal, the driving voltage generated by the voltage differential generation circuit fails to be regulated to a desired voltage. To be specific, the voltage applied on the motor fails to be effectively regulated to the working voltage of the motor. For example,  FIG. 1  illustrates output states of two amplifiers in a voltage differential generation circuit. Assume that the working voltage of the motor is V reg , when the desired driving voltage is V reg , one output terminal of the voltage differential generation circuit needs to output a voltage V reg , and the other output terminal of the voltage differential generation circuit needs to output a voltage 0. However, since the MOSFET as an output stage of the amplifier is in a deep linear region, the voltage output by the other output terminal of the voltage differential generation circuit is not 0, but is a value greater than 0, such that the driving voltage generated by the voltage differential generation circuit is not V reg , but is a voltage less than V reg . In this way, when the duty cycle of the input signal is with a range of 0 to 100%, as illustrated in  FIG. 2A  and  FIG. 2B , the driving voltage generated by the voltage differential generation circuit is not completely in a linear relation with the duty cycle of the input signal. 
     The single-terminal input herein refers to that an input voltage in the voltage differential generation circuit is only connected relatively from an input terminal. 
     Based on this, in the embodiments of the present invention, when the voltage differential generation circuit generates a driving voltage for driving a load, the common mode voltage generation circuit regulates voltages output by a first output terminal and a second output terminal of the voltage differential generation circuit by the same voltage value, such that a central value of a voltage output by the first output terminal and a voltage output by the second output terminal of the voltage differential generation circuit is regulated. In this way, when a duty cycle of an input signal is within a range of 0 to 100%, the driving voltage generated by the voltage differential generation circuit is in a linear relation with the duty cycle of the input signal, thereby ensuring fidelity of an output signal. 
     The present invention is described hereinafter in detail with reference to the attached drawings and specific embodiments. 
     An embodiment of the present invention provides a load driving circuit. As illustrated in  FIG. 3 , the load driving circuit comprises a voltage differential generation circuit  31  and a common mode voltage generation circuit  32 ; wherein: 
     When the voltage differential generation circuit  32  generates a driving voltage for driving a load, the common mode voltage generation circuit  31  regulates voltages output by a first output terminal and a second output terminal of the voltage differential generation circuit  32  by the same voltage value, such that a central value of a voltage output by the first output terminal and a voltage output by the second output terminal of the voltage differential generation circuit  32  is regulated by a first voltage. In this way, when a duty cycle of an input signal is within a range of 0 to 100%, the driving voltage generated by the voltage differential generation circuit  32  is in a linear relation with the duty cycle of the input signal, thereby ensuring fidelity of an output signal. The first voltage may be set according to the actual requirements, for example, 50 mV, 100 mV, 150 mV, 200 mV, or the like. Herein, assume that the voltage output by the first output terminal is V out1  and the voltage output by the second output terminal is V out2 , then the central value is specifically calculates as: 
     
       
         
           
             
               
                 
                   V 
                   
                     out 
                      
                     
                         
                     
                      
                     1 
                   
                 
                 + 
                 
                   V 
                   
                     out 
                      
                     
                         
                     
                      
                     2 
                   
                 
               
               2 
             
             . 
           
         
       
     
     Regulating a central value of a voltage output by the first output terminal and a voltage output by the second output terminal of the voltage differential generation circuit  32  by a first voltage refers to: using a central value of the voltage output by the first output terminal and the voltage output by the second output terminal when the load driving circuit does not comprise the common mode voltage generation circuit  31  as a reference, up-regulating or down-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  by the first voltage, that is, using the voltage output by the first output terminal and the voltage output by the second output terminal when the load driving circuit does not comprise the common mode voltage generation circuit  31  as a reference, up-regulating or down-regulating the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  by the same voltage. 
     In this embodiment, the load driving circuit is a single-terminal input driving circuit. The single-terminal input driving circuit herein refers to that: an input voltage in the voltage differential generation circuit  32  is only connected relatively from an input terminal; simply speaking, the voltage differential generation circuit  32  has only one input voltage. 
     The load may be a motor, wherein the motor may be a haptic motor, for example, an eccentric rotating mass (ERM) motor, or the like. 
     Embodiment 1 
     In this embodiment, as illustrated in  FIG. 4A , the common mode voltage generation circuit  31  may comprise: a first resistor R 1 , a second resistor R 2 , and a third resistor R 3 ; and the voltage differential generation circuit  32  may comprise: a fourth p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) MP 4 , a fourth n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) MN 4 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , a first operational amplifier A 1 , a second operational amplifier A 2 , and a capacitor C ap . 
     The connection relations among various components of the load driving circuit as illustrated in  FIG. 4A  are as follows: 
     In the common mode voltage generation circuit  31 , one terminal of the first resistor R 1  is connected to a first input voltage, the other terminal of the first resistor R 1  is connected to one terminal of the second resistor R 2 , one terminal of the third resistor R 3  and a positive pole of the first operational amplifier A 1  in the voltage differential generation circuit  32 , the other terminal of the second resistor R 2  is connected to a positive pole of the second operational amplifier A 2  in the voltage differential generation circuit  32 , the other terminal of the third resistor R 3  is grounded, a resistance ratio of the first resistor R 1  to the second resistor R 2  to the third resistor R 3  is R 1 :R 2 :R 3 =2:1:2. 
     In the voltage differential generation circuit  32 , a gate of the fourth PMOSFET MP 4  is connected to an input signal and a gate of the fourth NMOSFET MN 4 , a source of the fourth PMOSFET MP 4  is connected to the first input voltage, a drain of the fourth PMOSFET MP 4  is connected to one terminal of the fourth resistor R 4  and a drain of the fourth NMOSFET MN 4 , a source of the fourth NMOSFET MN 4  is grounded, the other terminal of the fourth resistor R 4  is connected to one terminal of the fifth resistor R 5 , one terminal of the capacitor C ap  and a negative pole of the first operational amplifier A 1 , the other terminal of the fifth resistor R 5  is connected to the other terminal of the capacitor C ap , an output terminal of the first operational amplifier A 1  and one terminal of the sixth resistor R 6 , the other terminal of the sixth resistor R 6  is connected to a negative pole of the second operational amplifier A 2  and one terminal of the seventh resistor R 7 , the other terminal of the seventh resistor R 7  is connected to an output terminal of the second operational amplifier A 2 , the output terminal of the first operational amplifier A 1  and the output terminal of the second operational amplifier A 2  are respectively connected to two terminals of the load, a resistance ratio of the fifth resistor R 5  to the fourth resistor R 4  is 1:1, and a resistance of the sixth resistor R 6  is equal to that of the seventh resistor R 7 . 
     The input signal herein may be a pulse signal, for example, a pulse width modulation (PWM) signal. The value of the first input voltage may be determined according to related working parameters of the load. For example, assume that the load is a motor, the value of the first input voltage may be determined according to the working voltage of the motor. For example, if the working voltage of the motor is 3 V, the first input voltage is 3 V. Herein, the working voltage of the motor may be determined according to the working voltage set for the motor before delivery from factory. For example, if the working voltage set for the motor before delivery from factory is 3 V, it is determined that the working voltage of the motor is 3 V. After the value of the first input voltage is determined, the first input voltage may be provided by a power supply capable of generating a constant alternate current voltage, for example, a voltage regulator or the like, for use by corresponding components in the load driving circuit, such that the load driving circuit generates a corresponding driving voltage. The regulator may be specifically a low dropout (LDO) regulator or the like. The first operational amplifier and the second operational amplifier may be both class-AB amplifiers. In this way, when the amplifier works, a great current may be output such that requirements of the circuit are accommodated. 
     For ease of description, in the description of the working principles of the load driving circuit as illustrated in  FIG. 4A , the output terminal of the first operational amplifier A 1  is referred to as a first output terminal of the voltage differential generation circuit  32 , and the output terminal of the second operational amplifier A 2  is referred to as a second output terminal of the voltage differential generation circuit  32 ; the voltage connected to the positive pole of the first operational amplifier A 1  is referred to as V cmi , and the voltage connected to the positive pole of the second operational amplifier A 2  is referred to as V cmo , the first input voltage is referred to as V reg , the voltage output by the first output terminal is referred to as V out1 , and the voltage output by the second output terminal is referred to as V out2 . 
     The working principles of the load driving circuit as illustrated in the  FIG. 4A  are as follows: 
     When the load driving circuit works, a current I bp  is applied to the second resistor R 2 , and a flow direction of the current I bp  is from the second resistor R 2  to the third resistor R 3 . Assume that the resistance of the first resistor R 1  is 2R, then the resistance of the second resistor R 2  is R, and the resistance of the third resistor R 3  is 2R. In this case, a reference voltage of the first operational amplifier A 1 , that is, the voltage connected to the positive pole of the first operational amplifier A 1  is 
     
       
         
           
             
               
                 V 
                 cmi 
               
               = 
               
                 
                   
                     V 
                     reg 
                   
                   2 
                 
                 + 
                 
                   
                     I 
                     bp 
                   
                   × 
                   R 
                 
               
             
             , 
           
         
       
     
     and correspondingly, a reference voltage of the second operational amplifier A 2 , that is, the voltage connected to the positive pole of the second operational amplifier A 2  is 
     
       
         
           
             
               V 
               cmo 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 2 
               
               + 
               
                 
                   I 
                   bp 
                 
                 × 
                 2 
                  
                 
                   R 
                   . 
                 
               
             
           
         
       
     
     Under such circumstances, when the input signal is a low-level signal, the fourth PMOSFET MP 4  is conducted and the fourth NMOSFET MN 4  is turned off, such that the voltage of the input signal is V reg . Since the reference voltage of the first operational amplifier A 1  is 
     
       
         
           
             
               V 
               cmi 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 2 
               
               + 
               
                 
                   I 
                   bp 
                 
                 × 
                 R 
               
             
           
         
       
     
     and the reference voltage of the second operational amplifier A 2  is 
     
       
         
           
             
               
                 V 
                 cmo 
               
               = 
               
                 
                   
                     V 
                     reg 
                   
                   2 
                 
                 + 
                 
                   
                     I 
                     bp 
                   
                   × 
                   2 
                    
                   R 
                 
               
             
             , 
           
         
       
     
     the voltage output by the first output terminal of the voltage differential generation circuit  32  is V out1 =V reg +2R×I bp  and correspondingly the voltage output by the second output terminal of the voltage differential generation circuit  32  is V out2 =2R×I bp , such that the driving voltage generated by the voltage differential generation circuit  32  is V driver =V out2 −V out1 =−V reg . Analogously, when the input signal is a high-level signal, the fourth PMOSFET MP 4  is turned off and the fourth NMOSFET MN 4  is conducted, such that the voltage of the input signal is 0. Since the reference voltage of the first operational amplifier A 1  is 
     
       
         
           
             
               V 
               cmi 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 2 
               
               + 
               
                 
                   I 
                   bp 
                 
                 × 
                 R 
               
             
           
         
       
     
     and the reference voltage of the second operational amplifier A 2  is 
     
       
         
           
             
               
                 V 
                 cmo 
               
               = 
               
                 
                   
                     V 
                     reg 
                   
                   2 
                 
                 + 
                 
                   
                     I 
                     bp 
                   
                   × 
                   2 
                    
                   
                       
                   
                    
                   R 
                 
               
             
             , 
           
         
       
     
     the voltage output by the first output terminal of the voltage differential generation circuit  32  is V out1 =R×2I bp  and correspondingly the voltage output by the second output terminal of the voltage differential generation circuit  32  is V out2 =V reg +R×2I bp , such that the driving voltage generated by the voltage differential generation circuit  32  is V driver =V out2 −V out1 =V reg . 
     In conclusion, the reference voltages of the first operational amplifier A 1  and the second operational amplifier A 2  are regulated such that a central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is up-regulated, that is, up-regulated from 
     
       
         
           
             
               
                 
                   V 
                   reg 
                 
                 2 
               
                
               
                   
               
                
               to 
                
               
                   
               
                
               
                 
                   V 
                   reg 
                 
                 2 
               
             
             + 
             
               
                 I 
                 bp 
               
               × 
               2 
                
               
                   
               
                
               
                 R 
                 . 
               
             
           
         
       
     
     To be specific, the central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is up-regulated by I bp ×2R , that is, the first voltage is I bp ×2R. 
     When the input signal is a low-level signal, the duty cycle of the input signal is 0; and when the input signal is a high-level signal, the duty cycle of the input signal is 100%. The current I bp  applied on the second resistor R 2  may be generated by an additional circuit. 
     The principles of down-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal in the voltage differential generation circuit  32  are the same as those of up-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal in the voltage differential generation circuit  32 . 
     Based on  FIG. 4A , when the voltage differential generation circuit is subjected to an N-fold gain, that is, a resistance ratio of the fifth resistor R 5  and the fourth resistor R 4  is N:1, in another load driving circuit according to this embodiment, as illustrated in  FIG. 4B , the common mode voltage generation circuit  31  may comprise: an eleventh resistor R 11 , a twelfth resistor R 12 , a thirteenth resistor R 13 , and a fourteenth resistor R 14 ; and the voltage differential generation circuit  32  may comprise: a fourth PMOSFET MP 4 , a fourth NMOSFET MN 4 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , a first operational amplifier A 1 , a second operational amplifier A 2 , and a capacitor C ap . 
     The connection relations among various components of the load driving circuit as illustrated in  FIG. 4B  are as follows: 
     In the common mode voltage generation circuit  31 , one terminal of the eleventh resistor R 11  is connected to the first input voltage and the other terminal of the eleventh resistor R 11  is connected to one terminal of the thirteenth resistor R 13  and a positive pole of the first operational amplifier A 1  in the voltage differential generation circuit  32 , one terminal of the twelfth resistor R 12  is connected to the first input voltage and the other terminal of the twelfth resistor R 12  is connected to one terminal of the fourteenth resistor R 14  and a positive pole of the second operational amplifier A 2  in the voltage differential generation circuit  32 , the other terminal of the thirteenth resistor R 13  and the other terminal of the fourteenth resistor R 14  are both grounded, a resistance ratio of the eleventh resistor R 11  to the thirteenth resistor R 13  is N:1, and a resistance ratio of the twelfth resistor R 12  to the fourteenth resistor R 14  is 1:1. 
     In the voltage differential generation circuit  32 , a gate of the fourth PMOSFET MP 4  is connected to an input signal and a gate of the fourth NMOSFET MN 4 , a source of the fourth PMOSFET MP 4  is connected to a fourth input voltage, a drain of the fourth PMOSFET MP 4  is connected to one terminal of the fourth resistor R 4  and a drain of the fourth NMOSFET MN 4 , a source of the fourth NMOSFET MN 4  is grounded, the other terminal of the fourth resistor R 4  is connected to one terminal of the fifth resistor R 5 , one terminal of the capacitor C ap  and a negative pole of the first operational amplifier A 1 , the other terminal of the fifth resistor R 5  is connected to the other terminal of the capacitor C ap , an output terminal of the first operational amplifier A 1  and one terminal of the sixth resistor R 6 , the other terminal of the sixth resistor R 6  is connected to a negative pole of the second operational amplifier A 2  and one terminal of the seventh resistor R 7 , the other terminal of the seventh resistor R 7  is connected to an output terminal of the second operational amplifier A 2 , the output terminal of the first operational amplifier A 1  and the output terminal of the second operational amplifier A 2  are respectively connected to two terminals of the load, a resistance ratio of the fifth resistor R 5  to the fourth resistor R 4  is 1:1, and a resistance of the sixth resistor R 6  is equal to that of the seventh resistor R 7 . The fourth input voltage is 1/N of the first input voltage. 
     The working principles of the load driving circuit as illustrated in  FIG. 4B  are analogous to those of the load driving circuit as illustrated in  FIG. 4A . However, it should be noted that when the load driving circuit works, a current I 1  needs to be applied to the eleventh resistor R 11 , and a direction of the current I 1  is from the positive pole of the first operational amplifier A 1  to the eleventh resistor R 11 ; and a current I 2  needs to be applied to the twelfth resistor R 12 , and a direction of the current I 2  is from the positive pole of the second operational amplifier A 2  to the twelfth resistor R 12 . Assume that the resistance of the thirteenth resistor R 13  is R 13  and the resistance of the fourteenth resistor R 14  is R 14 , then 
     
       
         
           
             
               
                 I 
                 1 
               
               × 
               
                 R 
                 13 
               
             
             = 
             
               
                 
                   
                     I 
                     2 
                   
                   × 
                   
                     R 
                     14 
                   
                 
                 
                   2 
                    
                   
                       
                   
                    
                   N 
                 
               
               . 
             
           
         
       
     
     As seen from the above description, in the load driving circuit as illustrated in  FIG. 4B , the common mode voltage generation circuit  31  regulates the reference voltage of the first operational amplifier in the voltage differential generation circuit  32  from a second voltage to a third voltage, and regulates the reference voltage of the second operational amplifier in the voltage differential generation circuit  32  from the second voltage to a fourth voltage, wherein the third voltage satisfies equation 
     
       
         
           
             
               V 
               3 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 + 
                 
                   V 
                   1 
                 
               
               
                 N 
                 + 
                 1 
               
             
           
         
       
     
     and the fourth voltage satisfies equation 
     
       
         
           
             
               V 
               4 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 2 
               
               + 
               
                 
                   V 
                   1 
                 
                 . 
               
             
           
         
       
     
     In this way, the central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  are regulated by the first voltage. In the equations, V 3  denotes the third voltage, V reg  denotes a first input voltage, V 1  denotes a voltage, i.e., the first voltage, by which voltages output by the first output terminal and the second output terminal of the voltage differential generation circuit  32  are regulated; the first voltage or the second voltage is half of the first input voltage of the voltage differential generation circuit  32 ; and the first input voltage is a maximum value of the driving voltage that needs to be generated. In this embodiment, the third voltage corresponds to V cmi  in the load driving circuit as illustrated in  FIG. 4A , the fourth voltage corresponds to V cmo  in the load driving circuit as illustrated in  FIG. 4A , V 1  corresponds to I bp ×2R in the load driving circuit as illustrated in  FIG. 4A . 
     Herein, a central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is regulated, such that when a duty cycle of an input signal is within a range of 0 to 100%, the first operational amplifier and the second operational amplifier in the voltage differential generation circuit  32  both work in a linear region, thereby ensuring fidelity of an output signal. 
     Embodiment 2 
     In this embodiment, as illustrated in  FIG. 5 , the common mode voltage generation circuit  31  may comprise: an eighth resistor R 8 , a ninth resistor R 9 , a tenth resistor R 10 , a first PMOSFET MP 1 , a second PMOSFET MP 2 , a third PMOSFET MP 3 , a first NMOSFET MN 1 , a second NMOSFET MN 2 , a third NMOSFET MN 3 , a third operational amplifier A 3 , a fourth operational amplifier A 4 , a first buffer BUF 1 , and a second buffer BUF 2 ; and the voltage differential generation circuit  32  may comprise: a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , a first operational amplifier A 1 , a second operational amplifier A 2 , and a capacitor C ap . 
     The connection relations among various components of the load driving circuit as illustrated in  FIG. 5  are as follows: 
     In the common mode voltage generation circuit  31 , a gate of the first PMOSFET MP 1  is connected to an input signal, a source of the first PMOSFET MP 1  is connected to an output terminal of the first buffer BUF 1 , a drain of the first PMOSFET MP 1  is connected to a drain of the first NMOSFET MN 1  and one terminal of the fourth resistor R 4  in the voltage differential generation circuit  32 , an input terminal of the first buffer BUF 1  is connected to a drain of the second PMOSFET MP 2  and one terminal of the eighth resistor R 8 , a gate of the second PMOSFET MP 2  is connected to a gate of the third PMOSFET MP 3 , a drain of the third PMOSFET MP 3  and a drain of the third NMOSFET MN 3 , a source of the second PMOSFET MP 2  is connected to a source of the third PMOSFET MP 3  and a power supply, a gate of the first NMOSFET MN 1  is connected to an input signal, a source of the first NMOSFET MN 1  is connected to an output terminal of the second buffer BUF 2 , an input terminal of the second buffer BUF 2  is connected to a drain of the second NMOSFET MN 2  and one terminal of the ninth resistor R 9 , a gate of the second NMOSFET MN 2  is connected to an output terminal of a third operational amplifier A 3 , a source of the second NMOSFET MN 2  is connected to one terminal of the tenth resistor R 10  and grounded, a positive pole of the third operational amplifier A 3  is connected to the other terminal of the eighth resistor R 8  and the other terminal of the ninth resistor R 9 , a negative pole of the third operational amplifier A 3  is connected to a second input voltage, the other terminal of the tenth resistor R 10  is connected to a source of the third NMOSFET MN 3  and a negative pole of a fourth operational amplifier A 4 , a positive pole of the fourth operational amplifier A 4  is connected to a third input voltage, an output terminal of the fourth operational amplifier A 4  is connected to a gate of the third NMOSFET MN 3 , and a resistance of the eighth resistance R 8  is equal to that of the ninth resistor R 9 . 
     In the voltage differential generation circuit  32 , the other terminal of the fourth resistor R 4  is connected to one terminal of the fifth resistor R 5 , one terminal of the capacitor C ap  is connected to a negative pole of the first operational amplifier A 1 , the other terminal of the fifth resistor R 5  is connected to the other terminal of the capacitor C ap , an output terminal of the first operational amplifier A 1  and one terminal of the sixth resistor R 6 , the other terminal of the sixth resistor R 6  is connected to a negative pole of the second operational amplifier A 2  and one terminal of the seventh resistor R 7 , the other terminal of the seventh resistor R 7  is connected to an output terminal of the second operational amplifier A 2 , a positive pole of the first operational amplifier A 1  and a positive pole of the second operational amplifier A 2  are both connected to a second input voltage, an output terminal of the first operational amplifier A 1  and an output terminal of the second operational amplifier A 2  are respectively connected to two terminals of the load, and a resistance of the sixth resistor R 6  is equal to that of the seventh resistor R 7 . 
     The input signal herein may be a pulse signal, for example, a PWM signal. The value of the second input voltage is half of the voltage provided by the power supply. To be specific, a resistor may be serially connected between the power supply and the negative pole of the third operational amplifier A 3  and a resistor may be serially connected between the power supply and the positive pole of the first operational amplifier A 1  and the positive pole of the second operational amplifier A 2 , such that the value of the second input voltage is half of the voltage provided by the power supply. The power supply is directed to supply power for the load driving circuit. The value of the third input voltage is half of a reference voltage generated by a reference voltage generation circuit. To be specific, a resistor may be serially connected between the reference voltage generation circuit and the positive pole of the fourth operational amplifier A 4 , such that the value of the third input voltage is half of a reference voltage generated by a reference voltage generation circuit. The reference voltage generation circuit is directed to providing a bias voltage for the load driving circuit, such that various components in the entire load driving circuit are in a working state anytime. The first operational amplifier and the second operational amplifier are both class-AB amplifiers. In this way, when the amplifier works, a great current may be output such that requirements of the circuit are accommodated. 
     For ease of description, in the description of the working principles of the load driving circuit as illustrated in  FIG. 5 , the output terminal of the first operational amplifier Al is referred to as a first output terminal of the voltage differential generation circuit  32 , the output terminal of the second operational amplifier A 2  is referred to as a second output terminal of the voltage differential generation circuit  32 , the voltage output by the first output terminal is referred to as V out1 , the voltage output by the second output terminal is referred to as V out2 , a current flowing through the eighth resistor R 8  and the ninth resistor R 9  and flowing along a direction from the eighth resistor R 8  to the ninth resistor R 9  is referred to as I 1 , a current flowing through the tenth resistor R 10  and flowing along a direction from the drain of the third PMOSFET MP 3  to the tenth resistor R 10  is referred to as I 2 , the voltage provided by the power supply is referred to as V DD , the reference voltage generated by the reference voltage generation circuit is referred to as V bg , and the working voltage of the load is referred to as V reg . Herein, the value of the working voltage of the load may be determined according to related working parameters of the load. For example, assume that the load is a motor, the value of the first input voltage may be determined according to the working voltage of the motor. For example, if the working voltage of the motor is 3 V, the first input voltage is 3 V. After the value of the first input voltage is determined, the first input voltage may be provided by a power supply capable of generating a constant alternate current voltage, for example, a voltage regulator or the like, for use by corresponding components in the load driving circuit, such that the load driving circuit generates a corresponding driving voltage. The regulator may be specifically an LDO regulator or the like. 
     The working principles of the load driving circuit as illustrated in the  FIG. 5  are as follows: 
     When the load driving circuit works, when the input signal is a low-level signal, the first PMOSFET MP 1  is conducted and the first NMOSFET MN 1  is turned off, such that the voltage of the input signal is 
     
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 + 
                 
                   V 
                   reg 
                 
               
               2 
             
             . 
           
         
       
     
     In this case, since the reference voltages of the first operational amplifier A 1  and the second operational amplifier A 2 , i.e., the voltages connected to the positive poles of the first and second operational amplifiers, are both 
     
       
         
           
             
               
                 V 
                 DD 
               
               2 
             
             , 
           
         
       
     
     the voltage output by the first output terminal of the voltage differential generation circuit  32  is 
     
       
         
           
             
               V 
               
                 out 
                  
                 
                     
                 
                  
                 1 
               
             
             = 
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
           
         
       
     
     and the voltage output by the second output terminal of the voltage differential generation circuit  32  is 
     
       
         
           
             
               
                 V 
                 
                   out 
                    
                   
                       
                   
                    
                   2 
                 
               
               = 
               
                 
                   
                     V 
                     DD 
                   
                   - 
                   
                     V 
                     reg 
                   
                 
                 2 
               
             
             , 
           
         
       
     
     such that the driving voltage generated by the voltage differential generation circuit  32  is V driver =V out2   −V   out1 =−V reg . Analogously, when the input signal is a high-level signal, the first NMOSFET MN 1  is conducted and the first PMOSFET MP 1  is turned off, such that the voltage of the input signal is 
     
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
             . 
           
         
       
     
     In this case, since the reference voltages of the first operational amplifier A 1  and the second operational amplifier A 2  are both 
     
       
         
           
             
               
                 V 
                 DD 
               
               2 
             
             , 
           
         
       
     
     the voltage output by the first output terminal of the voltage differential generation circuit  32  is 
     
       
         
           
             
               V 
               
                 out 
                  
                 
                     
                 
                  
                 1 
               
             
             = 
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
           
         
       
     
     and the voltage output by the second output terminal of the voltage differential generation circuit  32  is 
     
       
         
           
             
               
                 V 
                 
                   out 
                    
                   
                       
                   
                    
                   2 
                 
               
               = 
               
                 
                   
                     V 
                     DD 
                   
                   + 
                   
                     V 
                     reg 
                   
                 
                 2 
               
             
             , 
           
         
       
     
     such that the driving voltage generated by the voltage differential generation circuit  32  is V driver =V out2 −V out1 =V reg . 
     In conclusion, a voltage range of the input signal is regulated from a range of 0 to V reg  to a range of 
     
       
         
           
             
               
                 
                   
                     V 
                     DD 
                   
                   - 
                   
                     V 
                     reg 
                   
                 
                 2 
               
                
               
                   
               
                
               to 
                
               
                   
               
                
               
                 
                   
                     V 
                     DD 
                   
                   + 
                   
                     V 
                     reg 
                   
                 
                 2 
               
             
             , 
           
         
       
     
     such that a central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is up-regulated, that is, up-regulated from 
     
       
         
           
             
               V 
               reg 
             
             2 
           
         
       
     
     to 
     
       
         
           
             
               
                 V 
                 DD 
               
               2 
             
             . 
           
         
       
     
     To be specific, the central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is up-regulated by 
     
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
             , 
           
         
       
     
     that is, the first voltage is 
     
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
             . 
           
         
       
     
     When the input signal is a low-level signal, the duty cycle of the input signal is 0; and when the input signal is a high-level signal, the duty cycle of the input signal is 100%. 
     In the load driving circuit as illustrated in  FIG. 5 , assume that the resistances of the eight resistor R 8  and the ninth resistor R 9  are both R 1  and the resistance of the tenth resistor R 10  is R 2 , then the following equation may be given: 
     
       
         
           
             
               
                 
                   
                     I 
                     1 
                   
                   = 
                   
                     
                       V 
                       ref 
                     
                     
                       2 
                       × 
                       
                         R 
                         1 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
             
               
                 
                   
                     I 
                     2 
                   
                   = 
                   
                     
                       V 
                       bg 
                     
                     
                       R 
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     Therefore,  
     
       
         
           
             
               
                 
                   
                     V 
                     reg 
                   
                   = 
                   
                     2 
                     × 
                     
                       
                         R 
                         1 
                       
                       
                         R 
                         2 
                       
                     
                     × 
                     
                       V 
                       bg 
                     
                     × 
                     
                       
                         I 
                         1 
                       
                       
                         I 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     Since V bg  is a fixed value, in practice, when V reg  is determined, a ratio of R 1  to R 2  may be obtained according to equation (3), and thus specific values of R 1  and R 2  may be determined. 
     The principles of down-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal in the voltage differential generation circuit  32  are the same as those of up-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal in the voltage differential generation circuit  32 . 
     As seen from the above description, in the load driving circuit as illustrated in  FIG. 5 , upon determining a range of the driving voltage to be generated, the common mode voltage generation circuit  31  regulates a voltage range of an input signal based on the range of the driving voltage by a fifth voltage, and regulates reference voltages of a first operational amplifier and a second operational amplifier a sixth voltage to a seventh voltage, wherein: the fifth voltage, the sixth voltage, the seventh voltage satisfy equation V 5 =V 7 −V 6 , where V 5  denotes the fifth voltage, V 6  denotes the sixth voltage, V 7  denotes the seventh voltage, the sixth voltage is half of a maximum value of the driving voltage that needs to be generated, and the fifth voltage is equal to the first voltage. Herein, V 5  corresponds to 
     
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
             , 
           
         
       
     
     V 6  corresponds to 
     
       
         
           
             
               
                 V 
                 reg 
               
               2 
             
             , 
           
         
       
     
     and V 7  corresponds to 
     
       
         
           
             
               
                 V 
                 DD 
               
               2 
             
             . 
           
         
       
     
     Herein, a central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is regulated, such that when a duty cycle of an input signal is within a range of 0 to 100%, the first operational amplifier and the second operational amplifier in the voltage differential generation circuit  32  both work in a linear region, thereby ensuring fidelity of an output signal. 
     Based on the above load driving circuit, an embodiment of the present invention provides a load driving method. The load driving method comprises: when the voltage differential generation circuit generates a driving voltage for driving a load, up-regulating voltages output by a first output terminal and a second output terminal of the voltage differential generation circuit by the same voltage value, such that a central value of a voltage output by the first output terminal and a voltage output by the second output terminal of the voltage differential generation circuit is regulated by a first voltage. In this way, when a duty cycle of an input signal is within a range of 0 to 100%, the driving voltage generated by the voltage differential generation circuit is in a linear relation with the duty cycle of the input signal, thereby ensuring fidelity of an output signal. The first voltage may be set according to the actual requirements, for example, 50 mV, 100 mV, 150 mV, 200 mV, or the like. Herein, assume that the voltage output by the first output terminal is V out1  and the voltage output by the second output terminal is V out2 , then the central value is specifically calculates as: 
     
       
         
           
             
               
                 
                   V 
                   
                     out 
                      
                     
                         
                     
                      
                     1 
                   
                 
                 + 
                 
                   V 
                   
                     out 
                      
                     
                         
                     
                      
                     2 
                   
                 
               
               2 
             
             . 
           
         
       
     
     Regulating a central value of a voltage output by the first output terminal and a voltage output by the second output terminal of the voltage differential generation circuit by a first voltage refers to: using a central value of the voltage output by the first output terminal and the voltage output by the second output terminal when the load driving circuit does not comprise the common mode voltage generation circuit as a reference, up-regulating or down-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit by the first voltage, that is, using the voltage output by the first output terminal and the voltage output by the second output terminal when the load driving circuit does not comprise the common mode voltage generation circuit as a reference, up-regulating or down-regulating the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit by the same voltage. 
     To be specific, in an embodiment, the reference voltage of the first operational amplifier in the voltage differential generation circuit  32  is regulated from a second voltage to a third voltage, and the reference voltage of the second operational amplifier in the voltage differential generation circuit  32  is regulated from the second voltage to a fourth voltage, wherein the third voltage satisfies equation 
     
       
         
           
             
               V 
               3 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 + 
                 
                   V 
                   1 
                 
               
               
                 N 
                 + 
                 1 
               
             
           
         
       
     
     and the fourth voltage satisfies equation 
     
       
         
           
             
               V 
               4 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 2 
               
               + 
               
                 
                   V 
                   1 
                 
                 . 
               
             
           
         
       
     
     In this way, the central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  are regulated by the first voltage. In the equations, V 3  denotes the third voltage, V reg  denotes a first input voltage, V 1  denotes a voltage, i.e., the first voltage, by which voltages output by the first output terminal and the second output terminal of the voltage differential generation circuit  32  are regulated; the first voltage or the second voltage is half of the first input voltage of the voltage differential generation circuit; and the first input voltage is a maximum value of the driving voltage that needs to be generated. 
     Specifically, in another embodiment, upon determining a range of the driving voltage to be generated, a voltage range of an input signal is regulated based on the range of the driving voltage by a fifth voltage, and reference voltages of a first operational amplifier and a second operational amplifier are regulated from a sixth voltage to a seventh voltage, wherein: the fifth voltage, the sixth voltage, the seventh voltage satisfy equation V 5 =V 7 −V 6 , where V 5  denotes the sixth voltage, V 6  denotes the sixth voltage, V 7  denotes the seventh voltage, the sixth voltage is half of a maximum value of the driving voltage that needs to be generated, and the fifth voltage is equal to the first voltage. 
     In this embodiment, the load driving circuit is a single-terminal input driving circuit. The single-terminal input driving circuit herein refers to that: an input voltage in the voltage differential generation circuit is only connected relatively from an input terminal; simply speaking, the voltage differential generation circuit has only one input voltage. 
     The load may be a motor, wherein the motor may be specifically a haptic motor, for example, an ERM motor, or the like. 
     Based on the above load driving circuit, an embodiment of the present invention provides a touch apparatus, wherein the touch apparatus comprises a touch screen and a load driving circuit. When an operator touches the touch screen, a touch signal is generated and the touch signal generates a touch feedback via the load driving circuit, for example, a touch vibration feedback. 
     As illustrated in  FIG. 3 , the load driving circuit comprises a common mode voltage generation circuit  31  and a voltage differential generation circuit  32 . 
     Regulating a central value of a voltage output by the first output terminal and a voltage output by the second output terminal of the voltage differential generation circuit  32  by a first voltage refers to: using a central value of the voltage output by the first output terminal and the voltage output by the second output terminal when the load driving circuit does not comprise the common mode voltage generation circuit  31  as a reference, up-regulating or down-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  by the first voltage, that is, using the voltage output by the first output terminal and the voltage output by the second output terminal when the load driving circuit does not comprise the common mode voltage generation circuit  31  as a reference, up-regulating or down-regulating the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  by the same voltage. 
     In this embodiment, the load driving circuit is a single-terminal input driving circuit. The single-terminal input driving circuit herein refers to that: an input voltage in the voltage differential generation circuit  32  is only connected relatively from an input terminal; simply speaking, the voltage differential generation circuit  32  has only one input voltage. 
     The load may be a motor, wherein the motor may be specifically a haptic motor, for example, an ERM motor, or the like. 
     Embodiment 1 
     In this embodiment, as illustrated in  FIG. 4A , the common mode voltage generation circuit  31  may comprise: a first resistor R 1 , a second resistor R 2 , and a third resistor R 3 ; and the voltage differential generation circuit  32  may comprise: a fourth PMOSFET MP 4 , a fourth NMOSFET MN 4 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , a first operational amplifier A 1 , a second operational amplifier A 2 , and a capacitor C ap . 
     The connection relations among various components of the load driving circuit as illustrated in  FIG. 4A  are as follows: 
     In the common mode voltage generation circuit  31 , one terminal of the first resistor R 1  is connected to a first input voltage, the other terminal of the first resistor R 1  is connected to one terminal of the second resistor R 2 , one terminal of the third resistor R 3  and a positive pole of the first operational amplifier A 1  in the voltage differential generation circuit  32 , the other terminal of the second resistor R 2  is connected to a positive pole of the second operational amplifier A 2  in the voltage differential generation circuit  32 , the other terminal of the third resistor R 3  is grounded, a resistance ratio of the first resistor R 1  to the second resistor R 2  to the third resistor R 3  is R 1 :R 2 :R 3 =2:1:2. 
     In the voltage differential generation circuit  32 , a gate of the fourth PMOSFET MP 4  is connected to an input signal and a gate of the fourth NMOSFET MN 4 , a source of the fourth PMOSFET MP 4  is connected to the first input voltage, a drain of the fourth PMOSFET MP 4  is connected to one terminal of the fourth resistor R 4  and a drain of the fourth NMOSFET MN 4 , a source of the fourth NMOSFET MN 4  is grounded, the other terminal of the fourth resistor R 4  is connected to one terminal of the fifth resistor R 5 , one terminal of the capacitor C ap  and a negative pole of the first operational amplifier A 1 , the other terminal of the fifth resistor R 5  is connected to the other terminal of the capacitor C ap , an output terminal of the first operational amplifier A 1  and one terminal of the sixth resistor R 6 , the other terminal of the sixth resistor R 6  is connected to a negative pole of the second operational amplifier A 2  and one terminal of the seventh resistor R 7 , the other terminal of the seventh resistor R 7  is connected to an output terminal of the second operational amplifier A 2 , the output terminal of the first operational amplifier A 1  and the output terminal of the second operational amplifier A 2  are respectively connected to two terminals of the load, a resistance ratio of the fifth resistor R 5  to the fourth resistor is 1:1, and a resistance of the sixth resistor R 6  is equal to that of the seventh resistor R 7 . 
     The input signal herein may be a pulse signal, for example, a PWM signal. The value of the first input voltage may be determined according to related working parameters of the load. For example, assume that the load is a motor, the value of the first input voltage may be determined according to the working voltage of the motor. For example, if the working voltage of the motor is 3 V, the first input voltage is 3 V. Herein, the working voltage of the motor may be determined according to the working voltage set for the motor before delivery from factory. For example, if the working voltage set for the motor before delivery from factory is 3 V, it is determined that the working voltage of the motor is 3 V. After the value of the first input voltage is determined, the first input voltage may be provided by a power supply capable of generating a constant alternate current voltage, for example, a voltage regulator or the like, for use by corresponding components in the load driving circuit, such that the load driving circuit generates a corresponding driving voltage. The regulator may be specifically an LDO regulator or the like. The first operational amplifier and the second operational amplifier may be both class-AB amplifiers. In this way, when the amplifier works, a great current may be output such that requirements of the circuit are accommodated. 
     For ease of description, in the description of the working principles of the load driving circuit as illustrated in  FIG. 4A , the output terminal of the first operational amplifier A 1  is referred to as a first output terminal of the voltage differential generation circuit  32 , and the output terminal of the second operational amplifier A 2  is referred to as a second output terminal of the voltage differential generation circuit  32 ; the voltage connected to the positive pole of the first operational amplifier A 1  is referred to as V cmi , and the voltage connected to the positive pole of the second operational amplifier A 2  is referred to as K cmo , the first input voltage is referred to as V reg , the voltage output by the first output terminal is referred to as V out1 , and the voltage output by the second output terminal is referred to as V out2 . 
     The working principles of the load driving circuit as illustrated in the  FIG. 4A  are as follows: 
     When the load driving circuit works, a current I bp  is applied to the second resistor R 2 , and a flow direction of the current I bp  is from the second resistor R 2  to the third resistor R 3 . Assume that the resistance of the first resistor R 1  is 2R, then the resistance of the second resistor R 2  is R, and the resistance of the third resistor R 3  is 2R. In this case, a reference voltage of the first operational amplifier A 1 , that is, the voltage connected to the positive pole of the first operational amplifier A 1  is 
     
       
         
           
             
               
                 V 
                 cmi 
               
               = 
               
                 
                   
                     V 
                     reg 
                   
                   2 
                 
                 + 
                 
                   
                     I 
                     bp 
                   
                   × 
                   R 
                 
               
             
             , 
           
         
       
     
     and correspondingly, a reference voltage of the second operational amplifier A 2 , that is, the voltage connected to the positive pole of the second operational amplifier A 2  is 
     
       
         
           
             
               V 
               cmo 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 2 
               
               + 
               
                 
                   I 
                   bp 
                 
                 × 
                 2 
                  
                 
                   R 
                   . 
                 
               
             
           
         
       
     
     Under such circumstances, when the input signal is a low-level signal, the fourth PMOSFET MP 4  is conducted and the fourth NMOSFET MN 4  is turned off, such that the voltage of the input signal is V reg . Since the reference voltage of the first operational amplifier A 1  is 
     
       
         
           
             
               V 
               cmi 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 2 
               
               + 
               
                 
                   I 
                   bp 
                 
                 × 
                 R 
               
             
           
         
       
     
     and the reference voltage of the second operational amplifier A 2  is 
     
       
         
           
             
               
                 V 
                 cmo 
               
               = 
               
                 
                   
                     V 
                     reg 
                   
                   2 
                 
                 + 
                 
                   
                     I 
                     bp 
                   
                   × 
                   2 
                    
                   R 
                 
               
             
             , 
           
         
       
     
     the voltage output by the first output terminal of the voltage differential generation circuit  32  is V out1 =V reg +2R×I bp  and correspondingly the voltage output by the second output terminal of the voltage differential generation circuit  32  is V out2 =2R×I bp , such that the driving voltage generated by the voltage differential generation circuit  32  is V driver =V out2 −V out1 =−V reg . Analogously, when the input signal is a high-level signal, the fourth PMOSFET MP 4  is turned off and the fourth NMOSFET MN 4  is conducted, such that the voltage of the input signal is 0. Since the reference voltage of the first operational amplifier A 1  is 
     
       
         
           
             
               V 
               cmi 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 2 
               
               + 
               
                 
                   I 
                   bp 
                 
                 × 
                 R 
               
             
           
         
       
     
     and the reference voltage of the second operational amplifier A 2  is 
     
       
         
           
             
               
                 V 
                 cmo 
               
               = 
               
                 
                   
                     V 
                     reg 
                   
                   2 
                 
                 + 
                 
                   
                     I 
                     bp 
                   
                   × 
                   2 
                    
                   R 
                 
               
             
             , 
           
         
       
     
     the voltage output by the first output terminal of the voltage differential generation circuit  32  is V out1 =R×2I bp  and correspondingly the voltage output by the second output terminal of the voltage differential generation circuit  32  is V out2 =V reg +R×2I bp , such that the driving voltage generated by the voltage differential generation circuit  32  is V driver =V out2 −V out1 =V reg . 
     In conclusion, the reference voltages of the first operational amplifier A 1  and the second operational amplifier A 2  are regulated such that a central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is up-regulated, that is, up-regulated from 
     
       
         
           
             
               
                 
                   V 
                   reg 
                 
                 2 
               
                
               
                   
               
                
               to 
                
               
                   
               
                
               
                 
                   V 
                   reg 
                 
                 2 
               
             
             + 
             
               
                 I 
                 bp 
               
               × 
               2 
                
               
                 R 
                 . 
               
             
           
         
       
     
     To be specific, the central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is up-regulated by I bp ×2R, that is, the first voltage is I bp ×2R. 
     When the input signal is a low-level signal, the duty cycle of the input signal is 0; and when the input signal is a high-level signal, the duty cycle of the input signal is 100%. The current I bp  applied on the second resistor R 2  may be generated by an additional circuit. 
     The principles of down-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal in the voltage differential generation circuit  32  are the same as those of up-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal in the voltage differential generation circuit  32 . 
     Based on  FIG. 4A , when the voltage differential generation circuit is subjected to an N-fold gain, that is, a resistance ratio of the fifth resistor R 5  and the fourth resistor R 4  is N:1, in another load driving circuit according to this embodiment, as illustrated in  FIG. 4B , the common mode voltage generation circuit  31  may comprise: an eleventh resistor R 11 , a twelfth resistor R 12 , a thirteenth resistor R 13 , and a fourteenth resistor R 14 ; and the voltage differential generation circuit  32  may comprise: a fourth PMOSFET MP 4 , a fourth NMOSFET MN 4 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , a first operational amplifier A 1 , a second operational amplifier A 2 , and a capacitor C ap . 
     The connection relations among various components of the load driving circuit as illustrated in  FIG. 4B  are as follows: 
     In the common mode voltage generation circuit  31 , one terminal of the eleventh resistor R 11  is connected to the first input voltage and the other terminal of the eleventh resistor R 11  is connected to one terminal of the thirteenth resistor R 13  and a positive pole of the first operational amplifier A 1  in the voltage differential generation circuit  32 , one terminal of the twelfth resistor R 12  is connected to the first input voltage and the other terminal of the twelfth resistor R 12  is connected to one terminal of the fourteenth resistor R 14  and a positive pole of the second operational amplifier A 2  in the voltage differential generation circuit  32 , the other terminal of the thirteenth resistor R 13  and the other terminal of the fourteenth resistor R 14  are both grounded, a resistance ratio of the eleventh resistor R 11  to the thirteenth resistor R 13  is N:1, and a resistance ratio of the twelfth resistor R 13  to the fourteenth resistor R 14  is 1:1. 
     In the voltage differential generation circuit  32 , a gate of the fourth PMOSFET MP 4  is connected to an input signal and a gate of the fourth NMOSFET MN 4 , a source of the fourth PMOSFET MP 4  is connected to a fourth input voltage, a drain of the fourth PMOSFET MP 4  is connected to one terminal of the fourth resistor R 4  and a drain of the fourth NMOSFET MN 4 , a source of the fourth NMOSFET MN 4  is grounded, the other terminal of the fourth resistor R 4  is connected to one terminal of the fifth resistor R 5 , one terminal of the capacitor C ap  and a negative pole of the first operational amplifier A 1 , the other terminal of the fifth resistor R 5  is connected to the other terminal of the capacitor C ap , an output terminal of the first operational amplifier A 1  and one terminal of the sixth resistor R 6 , the other terminal of the sixth resistor R 6  is connected to a negative pole of the second operational amplifier A 2  and one terminal of the seventh resistor R 7 , the other terminal of the seventh resistor R 7  is connected to an output terminal of the second operational amplifier A 2 , the output terminal of the first operational amplifier A 1  and the output terminal of the second operational amplifier A 2  are respectively connected to two terminals of the load, a resistance ratio of the fifth resistor R 5  to the fourth resistor R 4  is 1:1, a resistance of the sixth resistor R 6  is equal to that of the seventh resistor R 7 , and the fourth input voltage is 1/N of the first input voltage. 
     The working principles of the load driving circuit as illustrated in  FIG. 4B  are analogous to those of the load driving circuit as illustrated in  FIG. 4A . However, it should be noted that when the load driving circuit works, a current I 1  needs to be applied to the eleventh resistor R 11 , and a direction of the current I 1  is from the positive pole of the first operational amplifier A 1  to the eleventh resistor R 11 ; and a current I 2  needs to be applied to the twelfth resistor R 12 , and a direction of the current I 2  is from the positive pole of the second operational amplifier A 2  to the twelfth resistor R 12 . Assume that the resistance of the thirteenth resistor R 13  is R 13  and the resistance of the fourteenth resistor R 14  is R 14 , then 
     
       
         
           
             
               
                 I 
                 1 
               
               × 
               
                 R 
                 13 
               
             
             = 
             
               
                 
                   
                     I 
                     2 
                   
                   × 
                   
                     R 
                     14 
                   
                 
                 
                   2 
                    
                   N 
                 
               
               . 
             
           
         
       
     
     As seen from the above description, in the load driving circuit as illustrated in  FIG. 4B , the common mode voltage generation circuit  31  regulates the reference voltage of the first operational amplifier in the voltage differential generation circuit  32  from a second voltage to a third voltage, and regulates the reference voltage of the second operational amplifier in the voltage differential generation circuit  32  from the second voltage to a fourth voltage, wherein the third voltage satisfies equation 
     
       
         
           
             
               V 
               3 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 + 
                 
                   V 
                   1 
                 
               
               
                 N 
                 + 
                 1 
               
             
           
         
       
     
     and the fourth voltage satisfies equation 
     
       
         
           
             
               V 
               4 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 2 
               
               + 
               
                 
                   V 
                   1 
                 
                 . 
               
             
           
         
       
     
     In this way, the central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  are regulated by the first voltage. In the equations, V 3  denotes the third voltage, V reg  denotes a first input voltage, V 1  denotes a voltage, i.e., the first voltage, by which voltages output by the first output terminal and the second output terminal of the voltage differential generation circuit  32  are regulated; the first voltage or the second voltage is half of the first input voltage of the voltage differential generation circuit; and the first input voltage is a maximum value of the driving voltage that needs to be generated. In this embodiment, the third voltage corresponds to V cmi  in the load driving circuit as illustrated in  FIG. 4A , the fourth voltage corresponds to V cmo  in the load driving circuit as illustrated in  FIG. 4A , V 1  corresponds to I bp ×2R in the load driving circuit as illustrated in  FIG. 4A . 
     Herein, a central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is regulated, such that when a duty cycle of an input signal is within a range of 0 to 100%, the first operational amplifier and the second operational amplifier in the voltage differential generation circuit  32  both work in a linear region, thereby ensuring fidelity of an output signal. 
     Embodiment 2 
     In this embodiment, as illustrated in  FIG. 5 , the common mode voltage generation circuit  31  may comprise: an eighth resistor R 8 , a ninth resistor R 9 , a tenth resistor R 10 , a first PMOSFET MP 1 , a second PMOSFET MP 2 , a third PMOSFET MP 3 , a first NMOSFET MN 1 , a second NMOSFET MN 2 , a third NMOSFET MN 3 , a third operational amplifier A 3 , a fourth operational amplifier A 4 , a first buffer BUF 1 , and a second buffer BUF 2 ; and the voltage differential generation circuit  32  may comprise: a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , a first operational amplifier A 1 , a second operational amplifier A 2 , and a capacitor C ap . 
     The connection relations among various components of the load driving circuit as illustrated in  FIG. 5  are as follows: 
     In the common mode voltage generation circuit  31 , a gate of the first PMOSFET MP 1  is connected to an input signal, a source of the first PMOSFET MP 1  is connected to an output terminal of the first buffer BUF 1 , a drain of the first PMOSFET MP 1  is connected to a drain of the first NMOSFET MN 1  and one terminal of the fourth resistor R 4  in the voltage differential generation circuit  32 , an input terminal of the first buffer BUF 1  is connected to a drain of the second PMOSFET MP 2  and one terminal of the eighth resistor R 8 , a gate of the second PMOSFET MP 2  is connected to a gate of the third PMOSFET MP 3 , a drain of the third PMOSFET MP 3  and a drain of the third NMOSFET MN 3 , a source of the second PMOSFET MP 2  is connected to a source of the third PMOSFET MP 3  and a power supply, a gate of the first NMOSFET MN 1  is connected to an input signal, a source of the first NMOSFET MN 1  is connected to an output terminal of the second buffer BUF 2 , an input terminal of the second buffer BUF 2  is connected to a drain of the second NMOSFET MN 2  and one terminal of the ninth resistor R 9 , a gate of the second NMOSFET MN 2  is connected to an output terminal of a third operational amplifier A 3 , a source of the second NMOSFET MN 2  is connected to one terminal of the tenth resistor R 10  and grounded, a positive pole of the third operational amplifier A 3  is connected to the other terminal of the eighth resistor R 8  and the other terminal of the ninth resistor R 9 , a negative pole of the third operational amplifier A 3  is connected to a second input voltage, the other terminal of the tenth resistor R 10  is connected to a source of the third NMOSFET MN 3  and a negative pole of a fourth operational amplifier A 4 , a positive pole of the fourth operational amplifier A 4  is connected to a third input voltage, an output terminal of the fourth operational amplifier A 4  is connected to a gate of the third NMOSFET MN 3 , and a resistance of the eighth resistance R 8  is equal to that of the ninth resistor R 9 . 
     In the voltage differential generation circuit  32 , the other terminal of the fourth resistor R 4  is connected to one terminal of the fifth resistor R 5 , one terminal of the capacitor C ap  is connected to a negative pole of the first operational amplifier A 1 , the other terminal of the fifth resistor R 5  is connected to the other terminal of the capacitor C ap , an output terminal of the first operational amplifier A 1  and one terminal of the sixth resistor R 6 , the other terminal of the sixth resistor R 6  is connected to a negative pole of the second operational amplifier A 2  and one terminal of the seventh resistor R 7 , the other terminal of the seventh resistor R 7  is connected to an output terminal of the second operational amplifier A 2 , a positive pole of the first operational amplifier A 1  and a positive pole of the second operational amplifier A 2  are both connected to a second input voltage, an output terminal of the first operational amplifier A 1  and an output terminal of the second operational amplifier A 2  are respectively connected to two terminals of the load, and a resistance of the sixth resistor R 6  is equal to that of the seventh resistor R 7 . 
     The input signal herein may be a pulse signal, for example, a PWM signal. The value of the second input voltage is half of the voltage provided by the power supply. To be specific, a resistor may be serially connected between the power supply and the negative pole of the third operational amplifier A 3  and a resistor may be serially connected between the power supply and the positive pole of the first operational amplifier A 1  and the positive pole of the second operational amplifier A 2 , such that the value of the second input voltage is half of the voltage provided by the power supply. The power supply is directed to supply power for the load driving circuit. The value of the third input voltage is half of a reference voltage generated by a reference voltage generation circuit. To be specific, a resistor may be serially connected between the reference voltage generation circuit and the positive pole of the fourth operational amplifier A 4 , such that the value of the third input voltage is half of a reference voltage generated by a reference voltage generation circuit. The reference voltage generation circuit is directed to providing a bias voltage for the load driving circuit, such that various components in the entire load driving circuit are in a working state anytime. The first operational amplifier and the second operational amplifier are both class-AB amplifiers. In this way, when the amplifier works, a great current may be output such that requirements of the circuit are accommodated. 
     For ease of description, in the description of the working principles of the load driving circuit as illustrated in  FIG. 5 , the output terminal of the first operational amplifier A 1  is referred to as a first output terminal of the voltage differential generation circuit  32 , the output terminal of the second operational amplifier A 2  is referred to as a second output terminal of the voltage differential generation circuit  32 , the voltage output by the first output terminal is referred to as V out1 , the voltage output by the second output terminal is referred to as V out2 , a current flowing through the eighth resistor R 8  and the ninth resistor R 9  and flowing along a direction from the eighth resistor R 8  to the ninth resistor R 9  is referred to as I 1 , a current flowing through the tenth resistor R 10  and flowing along a direction from the drain of the third PMOSFET MP 3  to the tenth resistor R 10  is referred to as I 2 , the voltage provided by the power supply is referred to as V DD , the reference voltage generated by the reference voltage generation circuit is referred to as V bg , and the working voltage of the load is referred to as V reg . Herein, the value of the working voltage of the load may be determined according to related working parameters of the load. For example, assume that the load is a motor, the value of the first input voltage may be determined according to the working voltage of the motor. For example, if the working voltage of the motor is 3 V, the first input voltage is 3 V. After the value of the first input voltage is determined, the first input voltage may be provided by a power supply capable of generating a constant alternate current voltage, for example, a voltage regulator or the like, for use by corresponding components in the load driving circuit, such that the load driving circuit generates a corresponding driving voltage. The regulator may be specifically an LDO regulator or the like. 
     The working principles of the load driving circuit as illustrated in the  FIG. 5  are as follows: 
     When the load driving circuit works, when the input signal is a low-level signal, the first PMOSFET MP 1  is conducted and the first NMOSFET MN 1  is turned off, such that the voltage of the input signal is 
     
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 + 
                 
                   V 
                   reg 
                 
               
               2 
             
             . 
           
         
       
     
     In this case, since the reference voltages of the first operational amplifier A 1  and the second operational amplifier A 2 , i.e., the voltages connected to the positive poles of the first and second operational amplifiers, are both 
     
       
         
           
             
               
                 V 
                 DD 
               
               2 
             
             , 
           
         
       
     
     the voltage output by the first output terminal of the voltage differential generation circuit  32  is 
     
       
         
           
             
               V 
               
                 out 
                  
                 
                     
                 
                  
                 1 
               
             
             = 
             
               
                 
                   V 
                   DD 
                 
                 + 
                 
                   V 
                   reg 
                 
               
               2 
             
           
         
       
     
     and the voltage output by the second output terminal of the voltage differential generation circuit  32  is 
     
       
         
           
             
               
                 V 
                 
                   out 
                    
                   
                       
                   
                    
                   2 
                 
               
               = 
               
                 
                   
                     V 
                     DD 
                   
                   - 
                   
                     V 
                     reg 
                   
                 
                 2 
               
             
             , 
           
         
       
     
     such that the driving voltage generated by the voltage differential generation circuit  32  is V driver =V out2 −V out1 =−V reg . Analogously, when the input signal is a high-level signal, the first NMOSFET MN 1  is conducted and the first PMOSFET MP 1  is turned off, such that the voltage of the input signal is 
     
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 + 
                 
                   V 
                   reg 
                 
               
               2 
             
             . 
           
         
       
     
     In this case, since the reference voltages of the first operational amplifier A 1  and the second operational amplifier A 2  are both 
     
       
         
           
             
               
                 V 
                 DD 
               
               2 
             
             , 
           
         
       
     
     the voltage output by the first output terminal of the voltage differential generation circuit  32  is 
     
       
         
           
             
               V 
               
                 out 
                  
                 
                     
                 
                  
                 1 
               
             
             = 
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
           
         
       
     
     and the voltage output by the second output terminal of the voltage differential generation circuit  32  is 
     
       
         
           
             
               
                 V 
                 
                   out 
                    
                   
                       
                   
                    
                   2 
                 
               
               = 
               
                 
                   
                     V 
                     DD 
                   
                   + 
                   
                     V 
                     reg 
                   
                 
                 2 
               
             
             , 
           
         
       
     
     such that the driving voltage generated by the voltage differential generation circuit  32  is V driver =V out2 −V out1 =−V reg . 
     In conclusion, a voltage range of the input signal is regulated from a range of 0 to V reg  to a range of 
     
       
         
           
             
               
                 
                   
                     V 
                     DD 
                   
                   - 
                   
                     V 
                     reg 
                   
                 
                 2 
               
                
               
                   
               
                
               to 
                
               
                   
               
                
               
                 
                   
                     V 
                     DD 
                   
                   + 
                   
                     V 
                     reg 
                   
                 
                 2 
               
             
             , 
           
         
       
     
     such that a central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is up-regulated, that is, up-regulated from 
     
       
         
           
             
               V 
               reg 
             
             2 
           
         
       
     
     to 
     
       
         
           
             
               
                 V 
                 DD 
               
               2 
             
             . 
           
         
       
     
     To be specific, the central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is up-regulated by 
     
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
             , 
           
         
       
     
     that is, the first voltage is 
     
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
             . 
           
         
       
     
     When the input signal is a low-level signal, the duty cycle of the input signal is 0; and when the input signal is a high-level signal, the duty cycle of the input signal is 100%. 
     In the load driving circuit as illustrated in  FIG. 5 , assume that the resistances of the eight resistor R 8  and the ninth resistor R 9  are both R 1  and the resistance of the tenth resistor R 10  is R 2 , then the following equation may be given: 
     
       
         
           
             
               
                 
                   
                     I 
                     1 
                   
                   = 
                   
                     
                       V 
                       reg 
                     
                     
                       2 
                       × 
                       
                         R 
                         1 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
             
               
                 
                   
                     I 
                     2 
                   
                   = 
                   
                     
                       V 
                       bg 
                     
                     
                       R 
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     Therefore, 
     
       
         
           
             
               
                 
                   
                     V 
                     reg 
                   
                   = 
                   
                     2 
                     × 
                     
                       
                         R 
                         1 
                       
                       
                         R 
                         2 
                       
                     
                     × 
                     
                       V 
                       bg 
                     
                     × 
                     
                       
                         I 
                         1 
                       
                       
                         I 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     Since V bg  is a fixed value, in practice, when V reg  is determined, a ratio of R 1  to R 2  may be obtained according to equation (3), and thus specific values of R 1  and R 2  may be determined. 
     The principles of down-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal in the voltage differential generation circuit  32  are the same as those of up-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal in the voltage differential generation circuit  32 . 
     As seen from the above description, in the load driving circuit as illustrated in  FIG. 5 , upon determining a range of the driving voltage to be generated, the common mode voltage generation circuit  31  regulates a voltage range of an input signal based on the range of the driving voltage by a fifth voltage, and regulates reference voltages of a first operational amplifier and a second operational amplifier from a sixth voltage to a seventh voltage, wherein: the fifth voltage, the sixth voltage, the seventh voltage satisfy equation V 5 =V 7 −V 6 , where V 5  denotes the fifth voltage, V 6  denotes the sixth voltage, V 1  denotes the seventh voltage, the sixth voltage is half of a maximum value of the driving voltage that needs to be generated, and the fifth voltage is equal to the first voltage. Herein, V 5  corresponds to 
     
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
             , 
           
         
       
     
     V 6  corresponds to 
     
       
         
           
             
               
                 V 
                 reg 
               
               2 
             
             , 
           
         
       
     
     and V 7  corresponds to 
     
       
         
           
             
               
                 V 
                 DD 
               
               2 
             
             . 
           
         
       
     
     Herein, a central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is regulated, such that when a duty cycle of an input signal is within a range of 0 to 100%, the first operational amplifier and the second operational amplifier in the voltage differential generation circuit  32  both work in a linear region, thereby ensuring fidelity of an output signal. 
     Based on the above touch apparatus, an embodiment of the present invention provides an electronic device, wherein the electronic device comprises: a main board, a housing, and a touch apparatus. The touch apparatus comprises a touch screen and a load driving circuit. Under control of a controller on the main board, when an operator touches the touch screen, a touch signal is generated and the touch signal generates a touch feedback via the load driving circuit, for example, a touch vibration feedback. The controller may be a central processing unit (CPU). 
     As illustrated in  FIG. 3 , the load driving circuit comprises a common mode voltage generation circuit  31  and a voltage differential generation circuit  32 . 
     When the voltage differential generation circuit  32  generates a driving voltage for driving a load, the common mode voltage generation circuit  31  regulates voltages output by a first output terminal and a second output terminal of the voltage differential generation circuit  32  by the same voltage value, such that a central value of a voltage output by the first output terminal and a voltage output by the second output terminal of the voltage differential generation circuit  32  is regulated by a first voltage. In this way, when a duty cycle of an input signal is within a range of 0 to 100%, the driving voltage generated by the voltage differential generation circuit  32  is in a linear relation with the duty cycle of the input signal, thereby ensuring fidelity of an output signal. The first voltage may be set according to the actual requirements, for example, 50 mV, 100 mV, 150 mV, 200 mV, or the like. Herein, assume that the voltage output by the first output terminal is V out1  and the voltage output by the second output terminal is V out2 , then the central value is specifically calculates as: 
     
       
         
           
             
               
                 
                   V 
                   
                     out 
                      
                     
                         
                     
                      
                     1 
                   
                 
                 + 
                 
                   V 
                   
                     out 
                      
                     
                         
                     
                      
                     2 
                   
                 
               
               2 
             
             . 
           
         
       
     
     Regulating a central value of a voltage output by the first output terminal and a voltage output by the second output terminal of the voltage differential generation circuit  32  by a first voltage refers to: using a central value of the voltage output by the first output terminal and the voltage output by the second output terminal when the load driving circuit does not comprise the common mode voltage generation circuit  31  as a reference, up-regulating or down-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  by the first voltage, that is, using the voltage output by the first output terminal and the voltage output by the second output terminal when the load driving circuit does not comprise the common mode voltage generation circuit  31  as a reference, up-regulating or down-regulating the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  by the same voltage. 
     In this embodiment, the load driving circuit is a single-terminal input driving circuit. The single-terminal input driving circuit herein refers to that: an input voltage in the voltage differential generation circuit  32  is only connected relatively from an input terminal; simply speaking, the voltage differential generation circuit  32  has only one input voltage. 
     The load may be a motor, wherein the motor may be specifically a haptic motor, for example, an ERM motor, or the like. 
     Embodiment 1 
     In this embodiment, as illustrated in  FIG. 4A , the common mode voltage generation circuit  31  may comprise: a first resistor R 1 , a second resistor R 2 , and a third resistor R 3 ; and the voltage differential generation circuit  32  may comprise: a fourth PMOSFET MP 4 , a fourth NMOSFET MN 4 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , a first operational amplifier A 1 , a second operational amplifier A 2 , and a capacitor C ap . 
     The connection relations among various components of the load driving circuit as illustrated in  FIG. 4A  are as follows: 
     In the common mode voltage generation circuit  31 , one terminal of the first resistor R 1  is connected to a first input voltage, the other terminal of the first resistor R 1  is connected to one terminal of the second resistor R 2 , one terminal of the third resistor R 3  and a positive pole of the first operational amplifier A 1  in the voltage differential generation circuit  32 , the other terminal of the second resistor R 2  is connected to a positive pole of the second operational amplifier A 2  in the voltage differential generation circuit  32 , the other terminal of the third resistor R 3  is grounded, a resistance ratio of the first resistor R 1  to the second resistor R 2  to the third resistor R 3  is R 1 :R 2 :R 3 =2:1:2. 
     In the voltage differential generation circuit  32 , a gate of the fourth PMOSFET MP 4  is connected to an input signal and a gate of the fourth NMOSFET MN 4 , a source of the fourth PMOSFET MP 4  is connected to the first input voltage, a drain of the fourth PMOSFET MP 4  is connected to one terminal of the fourth resistor R 4  and a drain of the fourth NMOSFET MN 4 , a source of the fourth NMOSFET MN 4  is grounded, the other terminal of the fourth resistor R 4  is connected to one terminal of the fifth resistor R 5 , one terminal of the capacitor C ap  and a negative pole of the first operational amplifier A 1 , the other terminal of the fifth resistor R 5  is connected to the other terminal of the capacitor C ap , an output terminal of the first operational amplifier A 1  and one terminal of the sixth resistor R 6 , the other terminal of the sixth resistor R 6  is connected to a negative pole of the second operational amplifier A 2  and one terminal of the seventh resistor R 7 , the other terminal of the seventh resistor R 7  is connected to an output terminal of the second operational amplifier A 2 , the output terminal of the first operational amplifier A 1  and the output terminal of the second operational amplifier A 2  are respectively connected to two terminals of the load, a resistance ratio of the fifth resistor R 5  to the fourth resistor is 1:1, and a resistance of the sixth resistor R 6  is equal to that of the seventh resistor R 7 . 
     The input signal herein may be a pulse signal, for example, a PWM signal. The value of the first input voltage may be determined according to related working parameters of the load. For example, assume that the load is a motor, the value of the first input voltage may be determined according to the working voltage of the motor. For example, if the working voltage of the motor is 3 V, the first input voltage is 3 V. Herein, the working voltage of the motor may be determined according to the working voltage set for the motor before delivery from factory. For example, if the working voltage set for the motor before delivery from factory is 3 V, it is determined that the working voltage of the motor is 3 V. After the value of the first input voltage is determined, the first input voltage may be provided by a power supply capable of generating a constant alternate current voltage, for example, a voltage regulator or the like, for use by corresponding components in the load driving circuit, such that the load driving circuit generates a corresponding driving voltage. The regulator may be specifically an LDO regulator or the like. The first operational amplifier and the second operational amplifier may be both class-AB amplifiers. In this way, when the amplifier works, a great current may be output such that requirements of the circuit are accommodated. 
     For ease of description, in the description of the working principles of the load driving circuit as illustrated in  FIG. 4A , the output terminal of the first operational amplifier A 1  is referred to as a first output terminal of the voltage differential generation circuit  32 , and the output terminal of the second operational amplifier A 2  is referred to as a second output terminal of the voltage differential generation circuit  32 ; the voltage connected to the positive pole of the first operational amplifier A 1  is referred to as V cmi , and the voltage connected to the positive pole of the second operational amplifier A 2  is referred to as V cmo , the first input voltage is referred to as V reg , the voltage output by the first output terminal is referred to as V out1 , and the voltage output by the second output terminal is referred to as V out2 . 
     The working principles of the load driving circuit as illustrated in the  FIG. 4A  are as follows: 
     When the load driving circuit works, a current I bp  is applied to the second resistor R 2 , and a flow direction of the current I bp  is from the second resistor R 2  to the third resistor R 3 . Assume that the resistance of the first resistor R 1  is 2R, then the resistance of the second resistor R 2  is R, and the resistance of the third resistor R 3  is 2R. In this case, a reference voltage of the first operational amplifier A 1 , that is, the voltage connected to the positive pole of the first operational amplifier A 1  is 
     
       
         
           
             
               
                 V 
                 cmi 
               
               = 
               
                 
                   
                     V 
                     reg 
                   
                   2 
                 
                 + 
                 
                   
                     I 
                     bp 
                   
                   × 
                   R 
                 
               
             
             , 
           
         
       
     
     and correspondingly, a reference voltage of the second operational amplifier A 2 , that is, the voltage connected to the positive pole of the second operational amplifier A 2  is 
     
       
         
           
             
               V 
               cmo 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 2 
               
               + 
               
                 
                   I 
                   bp 
                 
                 × 
                 2 
                  
                 
                     
                 
                  
                 
                   R 
                   . 
                 
               
             
           
         
       
     
     Under such circumstances, when the input signal is a low-level signal, the fourth PMOSFET MP 4  is conducted and the fourth NMOSFET MN 4  is turned off, such that the voltage of the input signal is V reg . Since the reference voltage of the first operational amplifier A 1  is 
     
       
         
           
             
               V 
               cmi 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 2 
               
               + 
               
                 
                   I 
                   bp 
                 
                 × 
                 R 
               
             
           
         
       
     
     and the reference voltage of the second operational amplifier A 2  is 
     
       
         
           
             
               
                 V 
                 cmo 
               
               = 
               
                 
                   
                     V 
                     reg 
                   
                   2 
                 
                 + 
                 
                   
                     I 
                     bp 
                   
                   × 
                   2 
                    
                   
                       
                   
                    
                   R 
                 
               
             
             , 
           
         
       
     
     the voltage output by the first output terminal of the voltage differential generation circuit  32  is V out1 =V reg +2R×I bp  and correspondingly the voltage output by the second output terminal of the voltage differential generation circuit  32  is V out2 =2R×I bp , such that the driving voltage generated by the voltage differential generation circuit  32  is V driver =V out2 −V out1 =−V reg . Analogously, when the input signal is a high-level signal, the fourth PMOSFET MP 4  is turned off and the fourth NMOSFET MN 4  is conducted, such that the voltage of the input signal is 0. Since the reference voltage of the first operational amplifier A 1  is 
     
       
         
           
             
               V 
               cmi 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 2 
               
               + 
               
                 
                   I 
                   bp 
                 
                 × 
                 R 
               
             
           
         
       
     
     and the reference voltage of the second operational amplifier A 2  is 
     
       
         
           
             
               
                 V 
                 cmo 
               
               = 
               
                 
                   
                     V 
                     reg 
                   
                   2 
                 
                 + 
                 
                   
                     I 
                     bp 
                   
                   × 
                   2 
                    
                   R 
                 
               
             
             , 
           
         
       
     
     the
 
voltage output by the first output terminal of the voltage differential generation circuit  32  is V out1 →R×2I bp  and correspondingly the voltage output by the second output terminal of the voltage differential generation circuit  32  is V out2 =V reg +R×2I bp , such that the driving voltage generated by the voltage differential generation circuit  32  is V driver =V out2 −V out1 =−V reg .
 
     In conclusion, the reference voltages of the first operational amplifier A 1  and the second operational amplifier A 2  are regulated such that a central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is up-regulated, that is, up-regulated from 
     
       
         
           
             
               
                 
                   V 
                   reg 
                 
                 2 
               
                
               
                   
               
                
               to 
                
               
                   
               
                
               
                 
                   V 
                   reg 
                 
                 2 
               
             
             + 
             
               
                 I 
                 bp 
               
               × 
               2 
                
               
                 R 
                 . 
               
             
           
         
       
     
     To be specific, the central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is up-regulated by I bp ×2R, that is, the first voltage is I bp ×2R. 
     When the input signal is a low-level signal, the duty cycle of the input signal is 0; and when the input signal is a high-level signal, the duty cycle of the input signal is 100%. The current I bp  applied on the second resistor R 2  may be generated by an additional circuit. 
     The principles of down-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal in the voltage differential generation circuit  32  are the same as those of up-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal in the voltage differential generation circuit  32 . 
     Based on  FIG. 4A , when the voltage differential generation circuit is subjected to an N-fold gain, that is, a resistance ratio of the fifth resistor R 5  and the fourth resistor R 4  is N:1, in another load driving circuit according to this embodiment, as illustrated in  FIG. 4B , the common mode voltage generation circuit  31  may comprise: an eleventh resistor R 11 , a twelfth resistor R 12 , a thirteenth resistor R 13 , and a fourteenth resistor R 14 ; and the voltage differential generation circuit  32  may comprise: a fourth PMOSFET MP 4 , a fourth NMOSFET MN 4 , a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , a first operational amplifier A 1 , a second operational amplifier A 2 , and a capacitor C ap . 
     The connection relations among various components of the load driving circuit as illustrated in  FIG. 4B  are as follows: 
     In the common mode voltage generation circuit  31 , one terminal of the eleventh resistor R 11  is connected to the first input voltage and the other terminal of the eleventh resistor R 11  is connected to one terminal of the thirteenth resistor R 13  and a positive pole of the first operational amplifier A 1  in the voltage differential generation circuit  32 , one terminal of the twelfth resistor R 12  is connected to the first input voltage and the other terminal of the twelfth resistor R 12  is connected to one terminal of the fourteenth resistor R 14  and a positive pole of the second operational amplifier A 2  in the voltage differential generation circuit  32 , the other terminal of the thirteenth resistor R 13  and the other terminal of the fourteenth resistor R 14  are both grounded, a resistance ratio of the eleventh resistor R 11  to the thirteenth resistor R 13  is N:1, and a resistance ratio of the twelfth resistor R 12  to the fourteenth resistor R 14  is 1:1; and 
     In the voltage differential generation circuit  32 , a gate of the fourth PMOSFET MP 4  is connected to an input signal and a gate of the fourth NMOSFET MN 4 , a source of the fourth PMOSFET MP 4  is connected to a fourth input voltage, a drain of the fourth PMOSFET MP 4  is connected to one terminal of the fourth resistor R 4  and a drain of the fourth NMOSFET MN 4 , a source of the fourth NMOSFET MN 4  is grounded, the other terminal of the fourth resistor R 4  is connected to one terminal of the fifth resistor R 5 , one terminal of the capacitor C ap  and a negative pole of the first operational amplifier A 1 , the other terminal of the fifth resistor R 5  is connected to the other terminal of the capacitor C ap , an output terminal of the first operational amplifier A 1  and one terminal of the sixth resistor R 6 , the other terminal of the sixth resistor R 6  is connected to a negative pole of the second operational amplifier A 2  and one terminal of the seventh resistor R 7 , the other terminal of the seventh resistor R 7  is connected to an output terminal of the second operational amplifier A 2 , the output terminal of the first operational amplifier A 1  and the output terminal of the second operational amplifier A 2  are respectively connected to two terminals of the load, a resistance ratio of the fifth resistor R 5  to the fourth resistor R 4  is 1:1, and a resistance of the sixth resistor R 6  is equal to that of the seventh resistor R 7 . The fourth input voltage is 1/N of the first input voltage. 
     The working principles of the load driving circuit as illustrated in  FIG. 4B  are analogous to those of the load driving circuit as illustrated in  FIG. 4A . However, it should be noted that when the load driving circuit works, a current I 1  needs to be applied to the eleventh resistor R 11 , and a direction of the current I 1 I 2  is from the positive pole of the first operational amplifier A 1  to the eleventh resistor R 11 ; and a current I 2  needs to be applied to the twelfth resistor R 12 , and a direction of the current I 2  is from the positive pole of the second operational amplifier A 2  to the twelfth resistor R 12 . Assume that the resistance of the thirteenth resistor R 13  is R 13  and the resistance of the fourteenth resistor R 14  is R 14 , then 
     
       
         
           
             
               
                 I 
                 1 
               
               × 
               
                 R 
                 13 
               
             
             = 
             
               
                 
                   
                     I 
                     2 
                   
                   × 
                   
                     R 
                     14 
                   
                 
                 
                   2 
                    
                   N 
                 
               
               . 
             
           
         
       
     
     As seen from the above description, in the load driving circuit as illustrated in  FIG. 4B , the common mode voltage generation circuit  31  regulates the reference voltage of the first operational amplifier in the voltage differential generation circuit  32  from a second voltage to a third voltage, and regulates the reference voltage of the second operational amplifier in the voltage differential generation circuit  32  from the second voltage to a fourth voltage, wherein the third voltage satisfies equation 
     
       
         
           
             
               V 
               3 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 + 
                 
                   V 
                   1 
                 
               
               
                 N 
                 + 
                 1 
               
             
           
         
       
     
     and the fourth voltage satisfies equation 
     
       
         
           
             
               V 
               4 
             
             = 
             
               
                 
                   V 
                   reg 
                 
                 2 
               
               + 
               
                 
                   V 
                   1 
                 
                 . 
               
             
           
         
       
     
     In this way, the central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  are regulated by the first voltage. In the equations, V 3  denotes the third voltage, V reg  denotes a first input voltage, V 1  denotes a voltage, i.e., the first voltage, by which voltages output by the first output terminal and the second output terminal of the voltage differential generation circuit  32  are regulated; the first voltage or the second voltage is half of the first input voltage of the voltage differential generation circuit; and the first input voltage is a maximum value of the driving voltage that needs to be generated. In this embodiment, the third voltage corresponds to V cmi  in the load driving circuit as illustrated in  FIG. 4A , the fourth voltage corresponds to V cmo  in the load driving circuit as illustrated in  FIG. 4A , V 1  corresponds to I bp ×2R in the load driving circuit as illustrated in  FIG. 4A . 
     Herein, a central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is regulated, such that when a duty cycle of an input signal is within a range of 0 to 100%, the first operational amplifier and the second operational amplifier in the voltage differential generation circuit  32  both work in a linear region, thereby ensuring fidelity of an output signal. 
     Embodiment 2 
     In this embodiment, as illustrated in  FIG. 5 , the common mode voltage generation circuit  31  may comprise: an eighth resistor R 8 , a ninth resistor R 9 , a tenth resistor R 10 , a first PMOSFET MP 1 , a second PMOSFET MP 2 , a third PMOSFET MP 3 , a first NMOSFET MN 1 , a second NMOSFET MN 2 , a third NMOSFET MN 3 , a third operational amplifier A 3 , a fourth operational amplifier A 4 , a first buffer BUF 1 , and a second buffer BUF 2 ; and the voltage differential generation circuit  32  may comprise: a fourth resistor R 4 , a fifth resistor R 5 , a sixth resistor R 6 , a seventh resistor R 7 , a first operational amplifier A 1 , a second operational amplifier A 2 , and a capacitor C ap . 
     The connection relations among various components of the load driving circuit as illustrated in  FIG. 5  are as follows: 
     In the common mode voltage generation circuit  31 , a gate of the first PMOSFET MP 1  is connected to an input signal, a source of the first PMOSFET MP 1  is connected to an output terminal of the first buffer BUF 1 , a drain of the first PMOSFET MP 1  is connected to a drain of the first NMOSFET MN 1  and one terminal of the fourth resistor R 4  in the voltage differential generation circuit  32 , an input terminal of the first buffer BUF 1  is connected to a drain of the second PMOSFET MP 2  and one terminal of the eighth resistor R 8 , a gate of the second PMOSFET MP 2  is connected to a gate of the third PMOSFET MP 3 , a drain of the third PMOSFET MP 3  and a drain of the third NMOSFET MN 3 , a source of the second PMOSFET MP 2  is connected to a source of the third PMOSFET MP 3  and a power supply, a gate of the first NMOSFET MN 1  is connected to an input signal, a source of the first NMOSFET MN 1  is connected to an input terminal of the second buffer BUF 2 , an output terminal of the second buffer BUF 2  is connected to a drain of the second NMOSFET MN 2  and one terminal of the ninth resistor R 9 , a gate of the second NMOSFET MN 2  is connected to an output terminal of a third operational amplifier A 3 , a source of the second NMOSFET MN 2  is connected to one terminal of the tenth resistor R 10  and grounded, a positive pole of the third operational amplifier A 3  is connected to the other terminal of the eighth resistor R 8  and the other terminal of the ninth resistor R 9 , a negative pole of the third operational amplifier A 3  is connected to a second input voltage, the other terminal of the tenth resistor R 10  is connected to a source of the third NMOSFET MN 3  and a negative pole of a fourth operational amplifier A 4 , a positive pole of the fourth operational amplifier A 4  is connected to a third input voltage, an output terminal of the fourth operational amplifier A 4  is connected to a gate of the third NMOSFET MN 3 , and a resistance of the eighth resistance R 8  is equal to that of the ninth resistor R 9 . 
     In the voltage differential generation circuit  32 , the other terminal of the fourth resistor R 4  is connected to one terminal of the fifth resistor R 5 , one terminal of the capacitor C ap  is connected to a negative pole of the first operational amplifier A 1 , the other terminal of the fifth resistor R 5  is connected to the other terminal of the capacitor C ap , an output terminal of the first operational amplifier A 1  and one terminal of the sixth resistor R 6 , the other terminal of the sixth resistor R 6  is connected to a negative pole of the second operational amplifier A 2  and one terminal of the seventh resistor R 7 , the other terminal of the seventh resistor R 7  is connected to an output terminal of the second operational amplifier A 2 , a positive pole of the first operational amplifier A 1  and a positive pole of the second operational amplifier A 2  are both connected to a second input voltage, an output terminal of the first operational amplifier A 1  and an output terminal of the second operational amplifier A 2  are respectively connected to two terminals of the load, and a resistance of the sixth resistor R 6  is equal to that of the seventh resistor R 7 . 
     The input signal herein may be a pulse signal, for example, a PWM signal. The value of the second input voltage is half of the voltage provided by the power supply. To be specific, a resistor may be serially connected between the power supply and the negative pole of the third operational amplifier A 3  and a resistor may be serially connected between the power supply and the positive pole of the first operational amplifier A 1  and the positive pole of the second operational amplifier A 2 , such that the value of the second input voltage is half of the voltage provided by the power supply. The power supply is directed to supply power for the load driving circuit. The value of the third input voltage is half of a reference voltage generated by a reference voltage generation circuit. To be specific, a resistor may be serially connected between the reference voltage generation circuit and the positive pole of the fourth operational amplifier A 4 , such that the value of the third input voltage is half of a reference voltage generated by a reference voltage generation circuit. The reference voltage generation circuit is directed to providing a bias voltage for the load driving circuit, such that various components in the entire load driving circuit are in a working state anytime. The first operational amplifier and the second operational amplifier are both class-AB amplifiers. In this way, when the amplifier works, a great current may be output such that requirements of the circuit are accommodated. 
     For ease of description, in the description of the working principles of the load driving circuit as illustrated in  FIG. 5 , the output terminal of the first operational amplifier Al is referred to as a first output terminal of the voltage differential generation circuit  32 , the output terminal of the second operational amplifier A 2  is referred to as a second output terminal of the voltage differential generation circuit  32 , the voltage output by the first output terminal is referred to as V out1 , the voltage output by the second output terminal is referred to as V out2 , a current flowing through the eighth resistor R 8  and the ninth resistor R 9  and flowing along a direction from the eighth resistor R 8  to the ninth resistor R 9  is referred to as I 1 , a current flowing through the tenth resistor R 10  and flowing along a direction from the drain of the third PMOSFET MP 3  to the tenth resistor R 10  is referred to as I 2 , the voltage provided by the power supply is referred to as V DD , the reference voltage generated by the reference voltage generation circuit is referred to as V bg , and the working voltage of the load is referred to as V reg . Herein, the value of the working voltage of the load may be determined according to related working parameters of the load. For example, assume that the load is a motor, the value of the first input voltage may be determined according to the working voltage of the motor. For example, if the working voltage of the motor is 3 V, the first input voltage is 3 V. After the value of the first input voltage is determined, the first input voltage may be provided by a power supply capable of generating a constant alternate current voltage, for example, a voltage regulator or the like, for use by corresponding components in the load driving circuit, such that the load driving circuit generates a corresponding driving voltage. The regulator may be specifically an LDO regulator or the like. 
     The working principles of the load driving circuit as illustrated in the  FIG. 5  are as follows: 
     When the load driving circuit works, when the input signal is a low-level signal, the first PMOSFET MP 1  is conducted and the first NMOSFET MN 1  is turned off, such that the voltage of the input signal is V DD +V reg /2. In this case, since the reference voltages of the first operational amplifier A 1  and the second operational amplifier A 2 , i.e., the voltages connected to the positive poles of the first and second operational amplifiers, are both V DD /2, the voltage output by the first output terminal of the voltage differential generation circuit  32  is 
     
       
         
           
             
               V 
               
                 out 
                  
                 
                     
                 
                  
                 1 
               
             
             = 
             
               
                 
                   V 
                   DD 
                 
                 + 
                 
                   V 
                   reg 
                 
               
               2 
             
           
         
       
     
     and the voltage output by the second output terminal of the voltage differential generation circuit  32  is 
     
       
         
           
             
               
                 V 
                 
                   out 
                    
                   
                       
                   
                    
                   2 
                 
               
               = 
               
                 
                   
                     V 
                     DD 
                   
                   - 
                   
                     V 
                     reg 
                   
                 
                 2 
               
             
             , 
           
         
       
     
     such that the driving voltage generated by the voltage differential generation circuit  32  is V driver =V out2 −V out1 =−V reg . Analogously, when the input signal is a high-level signal, the first NMOSFET MN 1  is conducted and the first PMOSFET MP 1  is turned off, such that the voltage of the input signal is 
     
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
             . 
           
         
       
     
     In this case, since the reference voltages of the first operational amplifier A 1  and the second operational amplifier A 2  are both 
     
       
         
           
             
               V 
               
                 out 
                  
                 
                     
                 
                  
                 1 
               
             
             = 
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
           
         
       
     
     the voltage output by the first output terminal of the voltage differential generation circuit  32  is 
     
       
         
           
             
               
                 V 
                 DD 
               
               2 
             
             , 
           
         
       
     
     and the voltage output by the second output terminal of the voltage differential generation circuit  32  is 
     
       
         
           
             
               
                 V 
                 
                   out 
                    
                   
                       
                   
                    
                   2 
                 
               
               = 
               
                 
                   
                     V 
                     
                       DD 
                        
                       
                           
                       
                     
                   
                   + 
                   
                     V 
                     reg 
                   
                 
                 2 
               
             
             , 
           
         
       
     
     such that the driving voltage generated by the voltage differential generation circuit  32  is V driver =V out2 −V out1 =−V reg . 
     In conclusion, a voltage range of the input signal is regulated from a range of 0 to V reg  to a range of 
     
       
         
           
             
               
                 
                   
                     V 
                     DD 
                   
                   - 
                   
                     V 
                     reg 
                   
                 
                 2 
               
                
               
                   
               
                
               to 
                
               
                   
               
                
               
                 
                   
                     V 
                     DD 
                   
                   - 
                   
                     V 
                     reg 
                   
                 
                 2 
               
             
             , 
           
         
       
     
     such that a central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is up-regulated, that is, up-regulated from 
     
       
         
           
             
               V 
               reg 
             
             2 
           
         
       
     
     to 
     
       
         
           
             
               
                 V 
                 DD 
               
               2 
             
             . 
           
         
       
     
     To be specific, the central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is up-regulated by 
     
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
             , 
           
         
       
     
     that is, the first voltage is 
     
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
             . 
           
         
       
     
     When the input signal is a low-level signal, the duty cycle of the input signal is 0; and when the input signal is a high-level signal, the duty cycle of the input signal is 100%. 
     In the load driving circuit as illustrated in  FIG. 5 , assume that the resistances of the eight resistor R 8  and the ninth resistor R 9  are both R 1  and the resistance of the tenth resistor R 10  is R 2 , then the following equation may be given: 
     
       
         
           
             
               
                 
                   
                     I 
                     1 
                   
                   = 
                   
                     
                       V 
                       reg 
                     
                     
                       2 
                       × 
                       
                         R 
                         1 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
             
               
                 
                   
                     I 
                     2 
                   
                   = 
                   
                     
                       V 
                       bg 
                     
                     
                       R 
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     Therefore, 
     
       
         
           
             
               
                 
                   
                     V 
                     reg 
                   
                   = 
                   
                     2 
                     × 
                     
                       
                         R 
                         1 
                       
                       
                         R 
                         2 
                       
                     
                     × 
                     
                       V 
                       bg 
                     
                     × 
                     
                       
                         I 
                         1 
                       
                       
                         I 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     Since V bg  is a fixed value, in practice, when V reg  is determined, a ratio of R 1  to R 2  may be obtained according to equation (3), and thus specific values of R 1  and R 2  may be determined. 
     The principles of down-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal in the voltage differential generation circuit  32  are the same as those of up-regulating the central value of the voltage output by the first output terminal and the voltage output by the second output terminal in the voltage differential generation circuit  32 . 
     As seen from the above description, in the load driving circuit as illustrated in  FIG. 5 , upon determining a range of the driving voltage to be generated, the common mode voltage generation circuit  31  regulates voltage range of an input signal is regulated based on the range of the driving voltage by a fifth voltage, and regulates reference voltages of a first operational amplifier and a second operational amplifier from a sixth voltage to a seventh voltage, wherein: the fifth voltage, the sixth voltage, the seventh voltage satisfy equation V 5 =V 7 −V 6 , where V 5  denotes the fifth voltage, V 6  denotes the sixth voltage, V 7  denotes the seventh voltage, the sixth voltage is half of a maximum value of the driving voltage that needs to be generated, and the fifth voltage is equal to the first voltage. Herein, V 5  corresponds to 
     
       
         
           
             
               
                 
                   V 
                   DD 
                 
                 - 
                 
                   V 
                   reg 
                 
               
               2 
             
             , 
           
         
       
     
     V 6  corresponds to 
     
       
         
           
             
               
                 V 
                 reg 
               
               2 
             
             , 
           
         
       
     
     and V 7  , corresponds to 
     
       
         
           
             
               
                 V 
                 DD 
               
               2 
             
             . 
           
         
       
     
     Herein, a central value of the voltage output by the first output terminal and the voltage output by the second output terminal of the voltage differential generation circuit  32  is regulated, such that when a duty cycle of an input signal is within a range of 0 to 100%, the first operational amplifier and the second operational amplifier in the voltage differential generation circuit  32  both work in a linear region, thereby ensuring fidelity of an output signal. 
     The electronic device herein may be a mobile phone, an iPad, a laptop, or the like. 
       FIG. 6  is a schematic view of a simulation result obtained with the technical solution according to Embodiment 1 of the present invention. The simulation conditions are as follows: The resistance of the load is 15 ohms, the working voltage of the load is 3 V, a range of the driving voltage that needs to be generated is 0 to 3 V. The simulation result indicates that: With the technical solution according to the embodiment of the present invention, when the duty cycle of the input signal is within a range of 0 to 100%, the generated driving voltage is completely in a linear relation with the duty cycle of the input signal. 
     In the mean time, for better illustration of the technical solutions according to the embodiment of the present invention, the generated driving voltage is completely in a linear relation with the duty cycle of the input signal, an integrated circuit (IC) is fabricated with the technical solution according to Embodiment 1 of the present invention, and the generated driving voltage is tested, wherein the test temperature is 25° C.; the test conditions are as follows: the resistance of the load is 15 ohms and the working voltage of the load is 3 V, the range of the driving voltage that needs to be generated is 0 to 3 V. Then, the test result is as illustrated in  FIG. 7 . 
     As seen from  FIG. 7 , the duty cycle of the input signal is in a linear relation with the generated driving voltage. This further indicates that, with the technical solutions according to the embodiments of the present invention, when the duty cycle of the input signal is within a range of 0 to 100%, the generated driving voltage is in a linear relation with the duty cycle of the input signal, thereby ensuring fidelity of an output signal. 
     The above embodiments are merely preferred embodiments of the present invention, but are not intended to limit the protection scope of the present invention.