Patent Publication Number: US-7589554-B2

Title: I/O interface circuit of intergrated circuit

Description:
This Application is a Continuation Application of U.S. patent application Ser. No. 10/968,114 which was filed on Oct. 20, 2004 now U.S. Pat. No. 7,832,152, and is incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a bidirectional input and output (I/O) interface circuit used for inputting and outputting data to and from an integrated circuit and, particularly, to an I/O interface circuit of an integrated circuit in which a terminator in input mode and a driver in output mode are improved. 
     2. Description of Related Art 
     In a high-speed logic circuit where a signal rises and falls quickly, it is necessary to treat a signal line as a transmission line of a distributed constant circuit, in which signal reflection matters. The signal reflection occurs at a connection point between a transmission line and a circuit with different impedance from the characteristic impedance of the transmission line. If the characteristic impedance of the transmission line is Z 0 , the load impedance of the same is ZL, a reflection coefficient ρ 1  at a receiving end is expressed as: ρ 1 =(ZL−Z 0 )/(ZL+Z 0 ). If the output impedance of a signal source is ZS, a reflection coefficient ρ 2  at a transmitting end is expressed as: ρ 2 =(ZS−Z 0 )/(ZS+Z 0 ). Thus, the signal reflection is doesn&#39;t occur when the transmission line is terminated with ZL=Z 0  or ZS=Z 0 . Hence, an I/O portion of an integrated circuit has a terminator for matching impedance of another circuit with the impedance of the transmission circuit. 
     I/O circuits of integrated circuits thus generally include an output circuit (output buffer), an input circuit (input buffer), and a termination circuit. However, since the output circuit and the termination circuit occupy a relatively large area, separate placement of the two circuits causes increase in a chip area. 
     Japanese Unexamined Patent Application Publication No. 2003-133943, for example, proposes an I/O circuit of a large-scale integrated circuit (LSI) which uses a part of an output circuit also as a termination circuit to reduce the occupation area.  FIG. 11  is a circuit diagram which shows this I/O interface circuit in a way to clarify the relation to the present invention. 
     The I/O interface circuit  110  of  FIG. 11  is connected to an I/O terminal  100  connected to a transmission line outside of the LSI. The I/O interface circuit  110  includes a driver  1  as an output circuit (output buffer) and an input circuit (input buffer)  5 . In the driver  1 , a plurality of pairs of P-channel (Pch) transistors  2  and N-channel (Nch) transistors  3  are connected in series between a supply voltage VDD and a ground voltage GND. The connection points between the Pch transistors  2  and Nch transistors  3  are all connected to the I/O terminal  100 . A controller  4  supplies a control signal to each of the gates of the Pch transistors  2  and Nch transistors  3 , thereby turning on or off the transistor. 
     In the case of using the I/O interface circuit  110  in input mode, an input enable signal IEN inputted to the input circuit  5  is set High, and an output enable signal OEN inputted to the controller  4  is set Low. During the input mode, data is inputted to the I/O terminal  100  (Y 0 ), transmitted through the input circuit  5 , and then supplied inside the LSI as a signal Y 1 . Meanwhile, since the output enable signal OEN is Low, the controller  4  outputs a signal to turn on both of the Pch transistor  2  and the Nch transistor  3  of the driver  1 , thus forming a terminator (Thevenin terminator) R 1 . 
     On the other hand, in the case of using the I/O interface circuit  110  in output mode, the input enable signal IEN is set Low, and the output enable signal OEN is set High. During the output mode, a signal A is inputted to the controller  4 , transmitted through the driver  1 , and outputted from the I/O terminal  100 . When the output enable signal OEN is High and the output signal A is High, the controller  4  outputs a signal to turn on the Pch transistor  2  and turn off the Nch transistor  3  of the driver  1 . This turns on all the Pch transistors  2  in the driver  1 , thereby outputting the supply voltage VDD through the I/O terminal  100 . When the output enable signal OEN is High and the output signal A is Low, the controller  4  outputs a signal to turn off the Pch transistors  2  and turn on the Nch transistor  3  of the driver  1 . This turns on all the Nch transistors  3  in the driver  1 , thereby outputting the ground voltage GND through the I/O terminal  100 . In this way, a signal of High (VDD) or Low (GND) is outputted through the I/O terminal  100  in accordance with High or Low of the output signal A. 
     As described above, the transistors of the driver  1  serve as the terminator (Thevenin terminator) in the input mode and as the driver transistor in the output mode. The output circuit is thus used also as the termination circuit, which reduces the chip occupation area. 
     It has now been discovered that the I/O interface circuit  110  cannot maintain constant termination resistance since the termination resistance varies depending on variation in process conditions and temperature changes. 
     Further, the I/O interface circuit  110  cannot maintain constant output impedance neither since the output impedance also varies depending on variation in process conditions and temperature changes. 
     It has now been also discovered that the I/O interface circuit  110  cannot match the impedance with the impedance of the transmission line in at least either input or output mode since load impedance in the input mode and output impedance in the output mode are different. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, there is provided an input/output interface circuit of an integrated circuit which includes a plurality of transistor pairs, an input/output terminal which is connected to a connection point of each transistor pair of the plurality of transistor pairs, and a controller which controls switching of each transistor of the plurality of transistor pairs so as to constitute an output buffer in output mode and a termination circuit in input mode. The controller controls output impedance of the output buffer and load impedance of the termination circuit in such a way that they have a predetermined value. 
     The present invention allows providing constant termination resistance (load impedance) in input mode without depending on variation in process conditions and temperature changes. It also allows providing constant output impedance in output mode without depending on variation in process conditions and temperature changes. 
     Further, the present invention allows equalizing the load impedance in input mode and the output impedance in output mode so as to match the impedance with the impedance of a transmission line both in the input and output modes, which can offer higher-speed signal transmission. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a block diagram illustrating an I/O interface circuit according to an embodiment of the present invention; 
         FIG. 2  is a block diagram illustrating a transistor structure in input mode in the I/O interface circuit; 
         FIG. 3  is a block diagram illustrating a transistor structure in output mode in the I/O interface circuit; 
         FIG. 4  is a circuit diagram of a drive controller; 
         FIG. 5  is a circuit diagram of a driver; 
         FIG. 6  is a block diagram illustrating an impedance controller; 
         FIG. 7  is a conversion table of a binary code and a thermometer code; 
         FIG. 8  is a circuit diagram illustrating a driver under temperature changes in input mode; 
         FIG. 9  is a circuit diagram illustrating a driver when an output signal A is Low in output mode; 
         FIG. 10  is a circuit diagram illustrating a driver when an output signal A is High in output mode; and 
         FIG. 11  is a block diagram illustrating a conventional I/O interface circuit. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed. 
     An embodiment of the present invention is explained hereinafter with reference to the drawings.  FIG. 1  is a block diagram showing an I/O interface circuit according to a first embodiment of the invention.  FIGS. 2 and 3  are diagrams to explain a circuit configuration in input mode and output mode, respectively.  FIG. 4  is a circuit diagram showing a drive controller.  FIG. 5  is a circuit diagram showing a driver.  FIGS. 6 and 7  are a block diagram and a chart, respectively, showing an impedance controller.  FIGS. 8 ,  9 , and  10  are circuit diagrams showing the circuit operation according to this embodiment. 
     An I/O interface circuit  10  of  FIG. 1  is connected to an I/O terminal  14  connected to a transmission line outside a LSI. The I/O interface circuit  10  includes a driver  13  as an output circuit (output buffer) and an input circuit (input buffer)  12 . In the driver  13 , a plurality of pairs of Pch transistors  21  and Nch transistors  22  are connected in series between a supply voltage VDD and a ground voltage GND. The Pch transistor  21  serves as a first transistor, and the Nch transistor  22  as a second transistor. The supply voltage VDD serves as a first power source, and the ground voltage GND as a second power source. The connection points between the Pch transistors  21  and the Nch transistors  22  are all connected to the I/O terminal  14 . A drive controller  11  supplies a control signal to each of the gates of the Pch transistors  21  and Nch transistors  22 , thereby turning on or off the transistor. An impedance controller  19  is connected to the drive controller  11 . The impedance controller  19  outputs an impedance control signal to control the impedance of the driver  13  according to resistance of reference resistors  17  and  18 . The impedance controller  19  and the drive controller  11  constitute a controller of the driver  13 . 
     As shown in  FIG. 5 , the driver  13  is constituted by a plurality of pairs of the Pch transistors  21  and the Nch transistors  22 . Two pairs of the Pch and Nch transistors  21  and  22  make a set of four. Two Pch transistors  21  and two Nch transistors  22  in one set each have the same on-resistance value. The driver  13  includes a primary driver  13   a  and a secondary driver  13   b.    
     The primary driver  13   a  is constituted by two transistor pairs as a first set. The two transistor pairs are composed of a transistor pair of Pch and Nch transistors MP 0  and MN 0 , and a transistor pair of Pch and Nch transistors MP 1  and MN 1 . 
     The primary driver  13   a  is constituted by two or an even number of transistor pairs as a second or later set. The two or an even number of transistor pairs are composed of a transistor pair of Pch and Nch transistors MP 2  and MN 2 , a transistor pair of Pch and Nch transistors MP 3  and MN 3 , a transistor pair of Pch and Nch transistors MP 4  and MN 4 , a transistor pair of Pch and Nch transistors MP 5  and MN 5  and so on, to a transistor pair of Pch and Nch transistors MP (x−1) and MN (x−1), and a transistor pair of Pch and Nch transistors MPx and MNx. 
     In the primary driver  13   a , the Pch transistors MP 0  and MP 1  have the same channel width W, WP 0 , and the same on-resistance, and the Nch transistors MN 0  and MN 1  have the same channel width W, WN 0 , and the same on-resistance. Similarly, in the secondary driver  13   b , the Pch transistors MP 2  and MP 3  have the same channel width W, WP 1 , and the same on-resistance, and the Nch transistors MN 2  and MN 3  have the same channel width W, WN 1 , and the same on-resistance. In this way, in a set of two transistor pairs, two Pch transistors have the same channel width W and the same on-resistance value, and two Nch transistors have the same channel width W and the same on-resistance value. 
     The drive controller  1  receives an output signal A from inside the LSI. The output signal A is then supplied to the driver  13  and outputted to the I/O terminal  14 . On the other hand, the I/O terminal  14  receives an input signal from outside the LSI. The input signal is then supplied inside the LSI through the input circuit  12  as an input signal Y 1 . The drive controller  11  is controlled by an output enable signal OEN. The input circuit  12  is controlled by an input enable signal IEN. 
     A reference resistor  17  is connected to a supply voltage VDD and a reference resistor  18  is connected to a ground voltage GND, outside the LSI. The reference resistors  17  and  18  have the same resistance, R 2 . The reference resistors  17  and  18  are connected to the impedance controller  19  inside the LSI via terminals  15  and  16 , respectively. The resistance R 2  of the reference resistors  17  and  18  corresponds to impedance of the transmission line. For example, the resistance R 2  is proportionally twice the size of the impedance of the transmission line. Thus, the resistance R 2  corresponds to resistance R 1  of a Thevenin terminator, which is described later. The impedance controller  19  outputs control signals CP 0  to CPx and CN 0  to CNx to the drive controller  11 . The drive controller  11  outputs control signals PP 0 , PP 1 , PN 0 , PN 1 , SP 0  to SPx, and SN 0  to SNx, to the gate of each transistor of the driver  13 . 
     As shown in  FIG. 4 , the drive controller  11  includes inverters  31 ,  34 ,  35 ,  37   a ,  37   b , and NANDs  32 ,  33 ,  36   a  to  36   d , and NORs  38   a  to  38   d . The output signal A from inside the LSI is inverted by the inverter  31  and inputted to one input of the NAND  32 . The output enable signal OEN is inputted to the other input of the NAND  32 . The output from the NAND  32  is inverted by the inverter  35  and then outputted the primary driver  13   a  as signals PP 0  and PN 1 . The output signal A and the output enable signal OEN are also inputted to the NAND  33 . The output from the NAND  33  is outputted to the primary driver  13   a  as signals PP 1  and PN 0 . 
     The control signal CP 0  from the impedance controller  19  is inputted to the NANDs  36   a  and  36   b . The output from the NAND  32  is also inputted to the NAND  36   a , and the output from the inverter  34  is also inputted to the NAND  36   b . Similarly, the control signal CP 1  is inputted to the NANDs  36   c  and  36   d . The output from the NAND  32  is also inputted to the NAND  36   c , and the output from the inverter  34  is also inputted to the NAND  36   d . In this way, the control signals SP 0  to SPx to the Pch transistors of the secondary driver  13   b  of the driver  13  are generated from the control signals CP 0  to CPx from the impedance controller  19 . 
     The control signal CN 0  from the impedance controller  19  is inverted by the inverter  37   a  and inputted to the NORs  38   a  and  38   b . The output from the NAND  32  is also inputted to the NOR  38   a , and the output from the inverter  34  is also inputted to the NOR  38   b . Similarly, the control signal CN 1  is inverted by the inverter  37   b  and inputted to the NORs  38   c  and  38   d . The output from the NAND  32  is also inputted to the NOR  38   c , and the output from the inverter  34  is also inputted to the NOR  38   d . In this way, the control signals SN 0  to SNx to the Nch transistors of the secondary driver  13   b  of the driver  13  are generated from the control signals CN 0  to CNx from the impedance controller  19 . 
     As shown in  FIG. 5 , the drive signals PP 0  and PN 0  are inputted to the gates of the Pch transistor MP 0  and the Nch transistor MN 0 , respectively, of the primary driver  13   a . The drive signals PP 1  and PN 1  are inputted to the gates of the Pch transistor MP 1  and the Nch transistor MN 1 , respectively, of the primary driver  13   a . The drive signals SP 0  and SN 0  are inputted to the gates of the Pch transistor MP 2  and the Nch transistor MN 2 , respectively, of the secondary driver  13   b . The drive signals SP 1  and SN 1  are inputted to the gates of the Pch transistor MP 3  and the Nch transistor MN 3 , respectively, of the secondary driver  13   b . Further, the drive signals SP 2  and SN 2  are inputted to the gates of the Pch transistor MP 4  and the Nch transistor MN 4 , respectively, of the secondary driver  13   b . The drive signals SP 3  and SN 3  are inputted to the gates of the Pch transistor MP 5  and the Nch transistor MN 5 , respectively, of the secondary driver  13   b . In this way, the drive signals of SP 4  and SN 4  to SPx and SNx are inputted to the gates of the other Pch and Nch transistors of the secondary driver  13   b.    
     The impedance controller  19  outputs control signals CP 0  to CPx, and CN 0  to CNx to control the number of transistors  21 ,  22  of the driver  13  to be turned on, to the drive controller  11 . The impedance controller  19  outputs the control signals in correspondence with, or, for example, in proportional to, the resistance R 2  of the reference resistors  17  and  18 . Thus, when the output impedance and Thevenin termination resistance determined by the on-resistance of the MOS transistors  21  and  22  are deviated from a predetermined value determined by the resistance R 2  due to variation in process conditions or change in the LSI temperature, the impedance controller  19  controls the number of driving transistors of the secondary driver  13   b  in such a way that the output impedance and Thevenin termination resistance match be the predetermined value. 
       FIG. 6  shows an example of the impedance controller  19 . The impedance controller  19  includes a circuit  40  for controlling on and off of the Pch transistors  21  of the driver  13 . The impedance controller  19  also includes a circuit (not shown) for controlling on and off of the Nch transistors  22  of the driver  13 . Thus, the impedance controller  19  includes a detector having a first detector element with the same characteristics as the Pch transistor  21 , and a detector having a second detector element (not shown) with the same characteristics as the Nch transistor  22 . The impedance controller  19  of this embodiment has a Pch detector transistor  7  as the first detector element, and a Nch detector transistor (not shown) as the second detector element. 
     The circuit  40  in the impedance controller  19  shown in  FIG. 6  has an impedance adjuster  41 . In one case, the circuit  40  receives a reference voltage REFV from the reference resistor  17  connected to the VDD via a terminal  48 . In this case, the terminal  48  is an equivalent of the terminal  15  of  FIG. 1 . The reference voltage REFV is then inputted to one input (positive input) terminal of a comparator  43 . The impedance adjuster  41  and a resistor  42  are connected in series between a supply voltage VDD and a voltage VSS. The connection point  41   a  of the impedance adjuster  41  and the resistor  42  is connected to a negative input terminal of the comparator  43 . The voltage VSS is a voltage between the VDD and the GND. The Pch detector transistor  7  detects a change in the process conditions of the impedance adjuster  41  and the temperature of the LSI. The Pch detector transistor  7  therefore has the same transistor characteristics as the Pch transistor  21  of the driver  13  to serve as a detector element of the Pch transistor  21 . Thus, a change in the impedance of the Pch detector transistor  7  is detected as a change in the impedance of the Pch transistor  21  of the driver  13 . 
     An output from the comparator  43  is inputted to an up/down counter  44 . The up/down counter  44  counts up and down according to the signal from the comparator  43  in synchronization with a clock signal CLK supplied through a terminal  49 . 
     The comparator  43  compares a comparative voltage on the connection point  41   a  with the reference voltage REFV, and outputs an up signal (High) if the reference voltage REFV is higher than the comparative voltage, and outputs a down signal (Low) if it is lower than the comparative voltage. On each clock cycle, the up/down counter  44  counts up (increments) one binary value when the signal from the comparator  43  is High, and counts down (decrements) one binary value when it is Low. Further, the up/down counter  44  outputs a count value (binary code or binary value) composed of B 0 , B 1 , and B 2  to a code converter  45  and an averager  46  on each clock cycle. 
     The code converter  45  converts the binary code composed of B 0 , B 1 , and B 2  from the up/down counter  44  to a thermometer code composed of T 0 , T 1 , T 2 , T 3 , and so on to Tx, as shown in the conversion table of  FIG. 7 , and outputs it to the impedance adjuster  41 . If the signal from the comparator  43  is High, the impedance adjuster  41  reduces its impedance to increase the comparative voltage on the connection point  41   a.    
     On the other hand, the binary codes from the up/down counter  44  are sequentially inputted to the averager  46 . The averager  46  retains the binary codes, adds four sets of the binary codes, for example, and divides the sum by four. The averager  46  then outputs the averaged binary code. The binary code which is inputted to the averager  46  each time is composed of three bits of count value: B 0 , B 1 , and B 2 , and the averaged binary code outputted from the averager  46  is composed of three bits of codes: FOUT 0 , FOUT 1 , and FOUT 2 . 
     The averaged binary codes, FOUT 0 , FOUT 1 , and FOUT 2 , are then inputted to a code converter  47 . The code converter  47  converts the codes into the thermometer codes of six bits: T 0 , T 1 , T 2 , T 3 , and so on to Tx, based on the conversion table of  FIG. 7 , and outputs them as CP 0 , CP 1 , CP 2 , CP 3 , and so on to CPx. 
     In the other case, the circuit  40  of the impedance controller  19  receives a reference voltage REFV from the reference resistor  18  connected to the GND via a terminal  48 . In this case, the terminal  48  is an equivalent of the terminal  16  of  FIG. 1 . The code converter  47  outputs the thermometer codes of CN 0 , CN 1 , CNN, CN 3 , and soon to CNx. The Nch detector transistor, which detects a change in the process conditions of the impedance adjuster  41  and the temperature of the LSI, has the same transistor characteristics as the Nch transistor  22  of the driver  13 . Thus, a change in the on-resistance of the Nch detector transistor  22  corresponds to a change in the impedance of the Nch transistor  22 . 
     The thermometer codes CP 0 , CP 1 , CP 2 , CP 3 , and so on to CPx, and the thermometer codes CN 0 , CN 1 , CN 2 , CN 3 , and so on to CNx are inputted to the drive controller  11  as impedance controller control signals. 
     The operation of the I/O interface circuit  10  having the above structure is explained hereinafter. In the case of using the I/O interface circuit  10  in the input mode, the input enable signal IEN is set High, and the output enable signal OEN is set Low. The drive controller  11  of  FIG. 4  thereby outputs a signal where PP 0  and PN 1  are Low and PP 1  and PN 0  are High to the primary driver  13   a . Thus, in the primary driver  13   a  of the driver  13  shown in  FIG. 5 , a pair of the Pch transistor MP 0  and the Nch transistor MN 0  are turned on and a pair of the Pch transistor MP 1  and the Nch transistor MN 1  are turned off. Hence, if the signal from the impedance controller  19  turns off all the transistors of the secondary driver  13   b , in the drive circuit  13 , the Pch transistor  21  (MP 0 ) and the Nch transistor  22  (MN 0 ) are connected in series between the power supply voltage VDD and the ground voltage GND, forming Thevenin terminator, as shown  FIG. 2 . The connection point of the Pch transistor  21  and the Nch transistor  22  constituting the Thevenin terminator is connected to the I/O terminal  14 . If the on-resistance of the Pch and Nch transistors  21  and  22  is R 1 , their combined resistance R 1 / 2  is set equal to the impedance of the transmission line. The load impedance in the input mode thereby matches the impedance of the transmission line. The signal inputted through the I/O terminal  14  is thereby supplied inside the LSI through the input circuit  12  as an input signal Y 1 . 
     On the other hand, in the case of using the I/O interface circuit  10  in the output mode, the output enable signal OEN is set High, and the input enable signal IEN is set Low. This turns on either the Pch transistors MP 0  and MP 1 , or the Nch transistors MN 0  and MN 1  of the primary drivers  13   a  of  FIGS. 4 and 5 . If the output signal A is High, the Pch transistors MP 0  and MP 1  having the same on-resistance are turned on, and the Nch transistors MN 0  and MN 1  are turned off. If, on the contrary, the output signal A is Low, the Nch transistors MN 0  and MN 1  having the same on-resistance are turned on, and the Pch transistors MP 0  and MP 1  are turned off. Thus, in the output mode, input of the output signal A of High level causes the Pch transistors MP 0  and MP 1  to be both turned on to constitute a drive transistor, while input of the output signal A of Low level causes the Nch transistors MN 0  and MN 1  to be both turned on to constitute a drive transistor. The driver  13  with output impedance R 3  is thereby configured as shown  FIG. 3 . Since the Pch transistors MP 0  and MP 1  have the same channel width W of WP 0  and the same on-resistance, if the Pch transistors MP 0  and MP 1  are turned on, the output impedance of R 3 =K/(WP 0 +WP 0 )=K/2WP 0 =(½)(K/WP 0 )=(½)R 1 , where K is a constant, is generated between the supply voltage VDD and the voltage of the I/O terminal  14 . Thus, the output impedance R 3  is: R 3 =(½)R 1 =(½)R 2 . 
     Since the Thevenin termination is formed in the input mode, the I/O interface circuit  10  is equivalent with a circuit in which half resistance ((½)R 1 ) is terminated with a half voltage. Hence, the load impedance in the input mode and the output impedance R 3  in the output mode are the same. It is thereby possible to equalize the load impedance in the input mode and the output impedance R 3  in the output mode, and match the load and output impedance with the impedance of the transmission line. 
     In the output mode, high level of the output signal A from the LSI is outputted from the I/O terminal  14  through the Pch transistors MP 0  and MP 1  connected to the supply voltage VDD. On the other hand, Low level of the output signal A is outputted from the I/O terminal  14  through the Nch transistors MN 0  and MN 1  connected to the ground voltage GND. 
     A change in the temperature of the LSI or variation in the condition of manufacture (process variation) causes output impedance and Thevenin resistance determined by the on-resistance R 1  of the Pch transistors MP 0  and MP 1  and the on-resistance R 1  of the Nch transistors MN 0  and MN 1  to be deviated from a predetermined value determined by the resistance R 2  of the reference resistors  17  and  18 . When the output impedance and Thevenin resistance of the primary driver  13   a  in the driver  13  are deviated from the predetermined value, the impedance of the impedance adjuster  41  (Pch transistor or Nch transistor) in the impedance controller  19  is also deviated from the predetermined value. The code converter  47  therefore outputs control signals CP 0 , CP 1 , CP 2 , and so on to CPx, and CN 1 , CN 2 , CN 3 , and so on to CNx based on the comparison result of the comparator  43  in the impedance controller  19 . 
     In the input mode, if the resistance of the Pch transistor corresponding to MP 0  increases to reduce the comparative voltage on the connection point  41   a , causing the up/down counter  44  to increment a certain number, which is determined as one binary value by the averager  46 , the code converter  47  outputs a control signal of CP= . . . 001, in which CP 0  is 1 and other codes of CP 1 , CP 2 , to CPx are 0, as shown in  FIG. 7 . On the other hand, if the resistance of the Nch transistor corresponding to MN 0  increases to reduce the comparative voltage on the connection point  41   a , causing the up/down counter  44  to increment a certain number, which is determined as two binary values by the averager  46 , the code converter  47  outputs a control signal of CN= . . . 011, in which CN 0  and CN 1  are 1 and other codes of CP 2 , to CPx are 0. 
     This turns on the Pch transistor MP 2 , Nch transistors MN 2  and MN 4  of the secondary driver  13   b  in addition to the Pch transistor MP 0  and Nch transistor MN 0  of the primary driver  13   a , as shown in  FIG. 8 . The resistance of the Pch transistors  21  in the VDD side (MP 0 , MP 2 ), and the Nch transistors  22  in the GND side (MN 0 , MN 2 , MN 4 ) thereby matches the reference resistance R 2 . In this way, the transistors of the secondary driver  13   b  are turned on to control the resistance of the Pch transistors  21  and the resistance of the Nch transistors  22  based on the reference resistance R 2 . This allows the resistance of the Thevenin terminator to be a constant predetermined value in spite of changes in the LSI temperature or variation in the process conditions. It is thereby possible to form the terminator independent of temperature changes and variation in process conditions in the input mode. 
     On the other hand, in the output mode, if the output signal is Low, the impedance controller  19  outputs the control signals of CP= . . . 001, and CN= . . . 011. This turns on the Nch transistors MN 2 , MN 3 , MN 4 , and MN 5  of the secondary driver  13   b  in addition to the Nch transistors MN 0  and MN 1  of the primary driver  13   a , as shown in  FIG. 9 . The other transistors remain off. 
     On the contrary, if the output signal is High in the output mode, the impedance controller  19  outputs the control signals of CP= . . . 001, and CN= . . . 011. This turns on the Pch transistors MP 2  and MP 3  of the secondary driver  13   b  in addition to the Pch transistors MP 0  and MP 1  of the primary driver  13   a , as shown in  FIG. 10 . The other transistors remain off. 
     In this way, in the output mode, the output impedance of the Nch transistors MN 0 , MN 1 , MN 2 , MN 3 , MN 4 , and MN 5  when the output signal is Low, and the output impedance of the Pch transistors MP 0 , MP 1  MP 2  and MP 3  when the output signal is High are controlled based on the reference resistance R 2 . This allows the output impedance R 3  to be a constant predetermined value in spite of changes in the LSI temperature and variation in the process conditions. It is thereby possible to form the output impedance independent of temperature changes and variation in process conditions in the output mode. 
     The impedance controller  19  of the present invention is not limited to the one described in the above embodiment. For example, when the on-resistance of the transistors of the driver  13  varies, it is possible to directly input the count value of the up/down counter  44  to the code converter  47  and use the thermometer code CP 0  to CPx and CN 0  to CNx as a control signal to turn on or off the transistors of the driver  13 . However, it is preferred to employ the averager  46  to average the count value of the up/down counter  44  with a plurality of input count values, input the averaged value to the code converter  47 , and use the thermometer code CP 0  to CPx and CN 0  to CNx as a control signal to turn on or off the transistors of the driver  13  as described above since this allows more stable control. If the comparative voltage on the connection point  41   a  varies to be close to the reference voltage due to temperature changes and so on, the comparison result of the comparator  43  becomes indeterminate between up-counting or down-counting the up/down counter  44 . This is the same when the comparative voltage exceeds or falls below the upper and lower limit of an offset voltage of the comparator  43  from the reference voltage due to noise. The offset voltage of the comparator is a voltage to cause an error in determining if the comparative voltage is higher or lower than the reference voltage. The up/down counter  44  thereby varies among a count value corresponding to the reference voltage, a count value of one step higher, and a count value of one step lower. By averaging the count value, it is possible to prevent the variation in the comparative voltage from affecting impedance matching data. 
     It is apparent that the present invention is not limited to the above embodiment, that may be modified and changed without departing from the scope and spirit of the invention.