Patent Publication Number: US-2022215870-A1

Title: Ferroelectric random access memory device and method for operating read and write thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C. 119(a) to Korean Patent Application No. 10-2021-0001355, filed on Jan. 6, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
     BACKGROUND 
     1. Technical Field 
     The present disclosure relates to a ferroelectric random access memory device and a method for operating read/write thereof, more particularly to a ferroelectric random access memory device that operates read and write with low power and a method for operating read/write thereof. 
     2. Description of the Related Art 
     Non-Volatile Memory (NVM) has the advantage of not only not consuming standby power as data can be maintained even when the power is cut off in standby mode, but also having a higher degree of integration than volatile memory, which is advantageous for high-capacity implementation. 
       FIG. 1  shows a structure of a ferroelectric random access memory element, and  FIG. 2  shows a hysteresis characteristic of a ferroelectric random access memory element. 
     Among non-volatile memories, a ferroelectric random access memory (hereinafter FeRAM) is a memory device that uses a ferroelectric as a memory element. Conventionally, ferroelectrics were mainly applied to capacitor elements, but now, as shown in  FIG. 1 , ferroelectric transistor (Ferroelectric FET: hereinafter FeFET) elements having a structure in which a ferroelectric layer is added between a gate and an oxide layer in a MOSFET structure are receiving much attention. When a ferroelectric random access memory is configured with an FeFET element as shown in  FIG. 1 , it has advantages of excellent performance, such as excellent compatibility with CMOS circuits, high ON/OFF ratio (10 6 ) and fast write speed (10 ns) and low write power consumption compared to other conventional non-volatile memories such as STT-MRAM, PRAM and ReRAM. 
     As shown in  FIG. 2 , in the FeFET element, the threshold voltage (V TH ) varies depending on the gate-source voltage (V GS ) or the gate-drain voltage (V GD ) according to the hysteresis characteristic of the ferroelectric. Accordingly, one bit of data can be stored using a variable threshold voltage (V TH ). In general, among the variable threshold voltages (V TH ), the first threshold voltage (V TH1 ) of a relatively low voltage level is designated to store logic 1, and the second threshold voltage (V TH2 ) of the relatively high voltage level is designated to store logic 0. 
     As shown in  FIG. 1 , the FeFET element has a three-terminal structure of source-gate-drain, and the read/write paths are different, so there are advantages in that the chances of read/write failures are very low and the structure of the write circuit is simple. 
     Meanwhile, for conventional ferroelectric random access memories, 1 FeFET structure in which each cell consists of one FeFET, 1T+1FeFET structure of one transistor and one FeFET, 2T+1FeFET structure of two transistors and one FeFET, and the like are being used. 
     In the 1 FeFET structure, since each cell is composed of one FeFET, the cell size is small and the degree of integration is high, but there is a problem that write disturbance may occur. In addition, in the 1T+1FeFET structure, although write disturbance does not occur, there is a problem that a threshold voltage drop may occur, and in the 2T+1FeFET structure, there is a problem that not only a threshold voltage drop may occur, but also the degree of integration is lowered due to a large cell area. 
     In particular, in all of the 1 FeFET, 1T+1FeFET, and 2T+1FeFET structures, the conventional read/write method has a disadvantage in that power consumption is large during a read/write operation, and there is an inconvenience of using a negative voltage during the write operation. 
     SUMMARY 
     An object of the present disclosure is to provide a ferroelectric random access memory device capable of reducing power consumption during a read/write operation and a method for operating read/write thereof. 
     Another object of the present disclosure is to provide a ferroelectric random access memory device capable of performing a read/write operation with fewer types of voltage level and a method for operating read/write thereof. 
     A ferroelectric random access memory device according to an embodiment of the present disclosure, conceived to achieve the objectives above, comprises a memory cell array including a plurality of memory cells each having one ferroelectric transistor (hereinafter, FeFET) connected between a corresponding read line of a plurality of read lines and a corresponding source line of a plurality of source lines and one transistor connected between a corresponding bit line of a plurality of bit lines and a gate of the FeFET and having a gate connected to a corresponding word line of a plurality of word lines; and a read/write control unit, when address information for a memory cell to be written is applied together with a write command and data to be stored, in a first step selecting a word line and a read line corresponding to a row address of the address information from among a plurality of word lines and a plurality of read lines and applying a write voltage having a pre-designated positive voltage level, and in a second step applying a ground voltage to the selected read line, and applying the write voltage to a bit line corresponding to a memory cell to which data of 1 is to be written according to a column address of the address information among a plurality of bit lines. 
     In the FeFET, the pattern of the hysteresis curve may be shifted in the positive voltage direction so that a first threshold voltage of a relatively low voltage level for storing data of 1 and a second threshold voltage of a relatively high voltage level for storing data of 0 have positive voltage levels. 
     The read/write control unit, in the first step, may apply a ground voltage to unselected word lines and read lines and the plurality of bit lines, and may float the plurality of source lines. 
     The read/write control unit, in the second step, may apply a ground voltage to a bit line corresponding to a memory cell to be maintained as data of 0, and may float the plurality of source lines. 
     When a read command and address information for a memory cell storing data to be read are applied, the read/write control unit may select a word line corresponding to a row address of the address information from among a plurality of word lines and a plurality of read lines and apply a pre-designated data voltage, select a read line corresponding to a row address and apply a pre-designated drain read voltage, and apply a pre-designated gate read voltage to the plurality of bit lines. 
     The read/write control unit may apply a ground voltage to unselected word lines and unselected read lines, and may float the plurality of source lines. 
     The ferroelectric random access memory device may further comprise a sense amplifier unit comprising a plurality of sense amplifiers connected to each of the plurality of source lines to determine data stored in the memory cells by amplifying a voltage applied from the memory cells through the source lines. 
     The read/write control unit may comprise: a row decoder receiving and decoding a row address, selecting a read line and a word line corresponding to a row address among the plurality of read lines and the plurality of word lines, applying a write voltage to the selected read line and word line in response to a write command, and applying a drain read voltage and the data voltage to the selected read line and word line, respectively, in response to the read command; a column decoder receiving and decoding a column address and outputting; and a data input/output unit, when a write command is applied, receiving the decoded column address and data to be stored, applying the write voltage to a bit line corresponding to a memory cell in which data of 1 of the received data is to be stored, and when a read command is applied, applying a gate read voltage to the plurality of bit lines to obtain data determined by the plurality of sense amplifiers. 
     The write voltage may have a pre-designated voltage level higher than the second threshold voltage, the gate read voltage and the data voltage may have a voltage level between the first threshold voltage and the second threshold voltage, and the drain read voltage may have a voltage level between the gate read voltage and the write voltage. 
     A read/write method of a ferroelectric random access memory device according to another embodiment of the present disclosure, conceived to achieve the objectives above, including a plurality of memory cells each having one ferroelectric transistor (hereinafter, FeFET) connected between a corresponding read line of a plurality of read lines and a corresponding source line of a plurality of source lines and one transistor connected between a corresponding bit line of a plurality of bit lines and a gate of the FeFET and having a gate connected to a corresponding word line of a plurality of word lines, comprises: a first step of, when address information for a memory cell to be written is applied together with a write command and data to be stored, selecting a word line and a read line corresponding to a row address of the address information from among a plurality of word lines and a plurality of read lines and applying a write voltage having a pre-designated positive voltage level, thereby writing data of 0 to all memory cells in a corresponding row; and a second step of applying a ground voltage to the selected read line, and applying the write voltage to a bit line corresponding to a memory cell to which data of 1 is to be written according to a column address of the address information among a plurality of bit lines. 
     Accordingly, the ferroelectric random access memory device and a method for operating read/write thereof according to an embodiment of the present disclosure, can perform a read/write operation with fewer types of voltage level as well as not using a negative voltage, and can reduce power consumption during a read/write operation. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a structure of a ferroelectric random access memory element. 
         FIG. 2  shows a hysteresis characteristic of a ferroelectric random access memory element. 
         FIGS. 3A and 3B  are a diagram for explaining a read/write operation of a ferroelectric random access memory device having a 1 FeFET structure. 
         FIGS. 4A and 4B  are a diagram for explaining a read/write operation of a ferroelectric random access memory device having a 1T+1FeFET structure. 
         FIGS. 5A and 5B  are a diagram for explaining a read/write operation of a ferroelectric random access memory device having a 2T+1FeFET structure. 
         FIG. 6  shows a hysteresis characteristic of a ferroelectric random access memory element according to an embodiment of the present disclosure. 
         FIG. 7  is a diagram for explaining a write operation of a ferroelectric random access memory device according to an embodiment of the present disclosure. 
         FIG. 8  shows a write timing diagram of the ferroelectric random access memory of  FIG. 7 . 
         FIG. 9  is a diagram for explaining a read operation of a ferroelectric random access memory device according to an embodiment of the present disclosure. 
         FIG. 10  shows a read timing diagram of the ferroelectric random access memory of  FIG. 7 . 
         FIG. 11  shows a schematic structure of a ferroelectric random access memory device according to an embodiment of the present disclosure. 
         FIG. 12  shows a write method of a ferroelectric random access memory device according to an embodiment of the present disclosure. 
         FIG. 13  shows a read method of a ferroelectric random access memory device according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In order to fully understand the present disclosure, operational advantages of the present disclosure, and objects achieved by implementing the present disclosure, reference should be made to the accompanying drawings illustrating preferred embodiments of the present disclosure and to the contents described in the accompanying drawings. 
     Hereinafter, the present disclosure will be described in detail by describing preferred embodiments of the present disclosure with reference to accompanying drawings. However, the present disclosure can be implemented in various different forms and is not limited to the embodiments described herein. For a clearer understanding of the present disclosure, parts that are not of great relevance to the present disclosure have been omitted from the drawings, and like reference numerals in the drawings are used to represent like elements throughout the specification. 
     Throughout the specification, reference to a part “including” or “comprising” an element does not preclude the existence of one or more other elements and can mean other elements are further included, unless there is specific mention to the contrary. Also, terms such as “unit”, “device”, “module”, “block”, and the like described in the specification refer to units for processing at least one function or operation, which may be implemented by hardware, software, or a combination of hardware and software. 
       FIGS. 3A and 3B  are a diagram for explaining a read/write operation of a ferroelectric random access memory device having a 1 FeFET structure. 
       FIGS. 3A and 3B  show four memory cells by way of example, each consisting of one FeFET (F 11 , F 12 , F 21 , F 22 ), in which two word lines (WL 1 , WL 2 ), two bit lines (BL 1 , BL 2 ) and a plurality of source lines (SL 1 , SL 2 ) intersect in a memory cell array including a plurality of memory cells defined by a plurality of word lines (WL), a plurality of bit lines (BL) and a plurality of source lines (SL).  FIG. 3A  shows a write operation, and  FIG. 3B  shows a read operation. 
     Referring to  FIG. 3A , in the ferroelectric random access memory device having a 1 FeFET structure, a write operation may be performed in two steps: writing data of 0 and writing data of 1. Here, a process of writing data of 1 and 0 to two memory cells corresponding to the second word line (WL 2 ) among the two word lines (WL 1 , WL 2 ) among the four memory cells will be described as an example. That is, it represents a process in which the second row is selected and data is written. 
     In the ferroelectric random access memory device of the 1 FeFET structure, in order to first write data of 0 to the 22nd FeFET (F 22 ), a pre-designated negative write voltage (−V W ) is applied to the selected second word line (WL 2 ), and a voltage (−V W /2) of ½ level of the negative write voltage (−V W ) is applied to the remaining unselected word lines (WL 1 ). 
     Meanwhile, the second bit line (BL 2 ) corresponding to the 22nd FeFET (F 22 ) to which data of 0 is to be written is maintained at a pre-designated ground voltage, while a voltage (−V W /2) of ½ level of the negative write voltage (−V W ) is applied to the remaining bit line (BL 1 ), like the unselected word line (WL 1 ). At this time, all of the source lines (SL 1 , SL 2 ) are maintained at a ground voltage. 
     Accordingly, since a negative write voltage (−V W ) is applied to the gate of the 22nd FeFET (F 22 ) through the second word line (WL 2 ), and a ground voltage is maintained for the second bit line (BL 2 ) and the second source line (SL 2 ), a voltage difference equal to the negative write voltage (−V W ) is applied between the gate-source and gate-drain, and thus a negative write voltage (−V W ) is applied to the ferroelectric disposed between the gate and the oxide layer, so that the threshold voltage (V TH ) of the 22nd FeFET (F 22 ) is increased to the second threshold voltage (V TH2 ). 
     Thereafter, in the step of writing data of 1 to the 21st FeFET (F 21 ), a positive write voltage (V W ) is applied to the second word line (WL 2 ), and a voltage (V W /2) of ½ level of the positive write voltage (V W ) is applied to the remaining unselected word line (WL 1 ). In addition, a ground voltage is applied to the first bit line (BL 1 ) and the first source line (SL 1 ) corresponding to the 21st FeFET (F 21 ) to which data of 1 is to be written, while a voltage (V W /2) of ½ level of a positive write voltage (V W ) is applied to the remaining bit line (BL 2 ) and source line (SL 2 ). 
     That is, unlike the 22nd FeFET (F 22 ) in which data of 0 is written, a positive write voltage (V W ) is applied to the gate of the 21st FeFET (F 21 ), so that the threshold voltage (V TH ) of the 21st FeFET (F 21 ) is lowered to the first threshold voltage (V TH1 ). 
     As a result, the 21st FeFET (F 21 ) has a relatively low first threshold voltage (V TH1 ), and the 22nd FeFET (F 22 ) has a relatively high second threshold voltage (V TH2 ) to store data 1 and 0. 
     Referring to  FIG. 3B , in the read process, a ferroelectric random access memory device of the same 1 FeFET structure applies a pre-designated gate read voltage (V G_READ ) to the second word line (WL 2 ) corresponding to the selected row, applies a pre-designated drain read voltage (V D_READ ) to all the bit lines (BL 1 , BL 2 ), and measures the current (I ON ) flowing through the source lines (SL 1 , SL 2 ) to determine the data stored in the FeFET (F 21 , F 22 ) on the selected second word line (WL 2 ). At this time, since the 21st FeFET (F 21 ) has a first threshold voltage (V TH1 ) that is a negative voltage level, while the 22nd FeFET (F 22 ) has a second threshold voltage (V TH2 ) that is a positive voltage level, a current (I ON ) flows through the 21st FeFET (F 21 ), whereas no current flows through the 22nd FeFET (F 22 ). Accordingly, data stored in the 21st FeFET (F 21 ) and the 22nd FeFET (F 22 ) can be easily determined. 
     As described above, in the ferroelectric random access memory device of the 1 FeFET structure shown in  FIGS. 3A and 3B , since a memory cell is composed of only one FeFET, there is an advantage in that the degree of integration can be greatly improved. 
     However, looking again at the case of writing data of 0 to the 22nd FeFET (F 22 ) on the left in  FIG. 3A , since a voltage (−V W /2) of ½ level of the negative write voltage (−V W ) is applied to the first word line (WL 1 ) to the 12th FeFET (F 12 ) and a ground voltage is applied to the second bit line (BL 2 ) and the second source line (SL 2 ), a voltage difference is generated between the gate-source and gate-drain of the 12th FeFET (F 12 ) by a voltage (−V W /2) of ½ level of the negative write voltage (−V W ). 
     In addition, since a negative write voltage (−V W ) is applied to the second word line (WL 2 ) to the 21st FeFET (F 21 ) and a voltage (−V W /2) of ½ level of the negative write voltage (−V W ) is applied to the first bit line (BL 1 ), a voltage difference is also generated between the gate-drain of the 21st FeFET (F 21 ) by a voltage (−V W /2) of ½ level of the negative write voltage (−V W ). 
     In addition, looking at the case of writing data of 1 to the 21st FeFET (F 21 ) on the right in  FIG. 3A , since a voltage (V W /2) of ½ level of the positive write voltage (V W ) is applied to the first word line (WL 1 ) to the 11th FeFET (F 11 ) and a ground voltage is applied to the first bit line (BL 1 ) and the first source line (SL 1 ), a voltage difference is generated between the gate-source and gate-drain of the 11th FeFET (F 11 ) by a voltage (V W /2) of ½ level of the positive write voltage (V W ). 
     In addition, since a positive write voltage (V W ) is applied to the second word line (WL 2 ) to the 22nd FeFET (F 22 ) and a voltage (V W /2) of ½ level of the positive write voltage (V W ) is applied to the second bit line (BL 2 ) and the second source line (SL 2 ), a voltage difference is also generated between the gate-source and gate-drain of the 22nd FeFET (F 22 ) by a voltage (V W /2) of ½ level of the positive write voltage (V W ). 
     That is, write disturbance occurs in which the heat generated from each of the cells in which the write operations are performed makes the electrical state of other adjacent cells unstable. In particular, as shown on the right side in  FIG. 3A , there is a problem in that the threshold voltage (V TH ) of the 22nd FeFET (F 22 ) that has been raised to the second threshold voltage (V TH2 ) may be lowered again. 
     Moreover, during the two-step operation, at least one voltage level swing is required for all bit lines (BL 1 , BL 2 ), two voltage level swings are required for the word lines (WL 1 , WL 2 ), and in the second step, one voltage level swing is also required for the selected source line (SL 2 ), and thus there is a disadvantage that the power consumption is large. 
       FIGS. 4A and 4B  are a diagram for explaining a read/write operation of a ferroelectric random access memory device having a 1T+1FeFET structure. Also  FIG. 4A  shows a write operation, and  FIG. 4B  shows a read operation. 
     In addition,  FIGS. 4A and 4B  also show only four memory cells by way of example, each memory cell being defined by a plurality of word lines (WL), a plurality of read lines (RL), a plurality of bit lines (BL) and a plurality of source lines (SL), and consisting of one transistor (T 11 , T 12 , T 21 , T 22 ) and one FeFET (F 11 , F 12 , F 21 , F 22 ). 
     Referring to  FIGS. 4A and 4B , in the ferroelectric random access memory device of the 1T+1FeFET structure, a drain and a source of the FeFET (F 11 , F 12 , F 21 , F 22 ) of each memory cell are respectively connected to the corresponding read lines (RL 1 , RL 2 ) and source lines (SL 1 , SL 2 ). In addition, transistors (T 11 , T 12 , T 21 , T 22 ) are connected between the corresponding bit lines (BL 1 , BL 2 ) and the gate of the corresponding FeFET (F 11 , F 12 , F 21 , F 22 ), and the gates are connected to the corresponding word lines (WL 1 , WL 2 ). 
     As shown in  FIG. 4A , the write operation of the ferroelectric random access memory device of a 1T+1FeFET structure may be performed in one step. For example, in a process of writing data of 1 and 0 to the two memory cells corresponding to the second word line (WL 2 ) as in  FIGS. 3A and 3B , a pre-designated positive write voltage (V W ) is applied to the selected second word line (WL 2 ), and a negative write voltage (−V W ) is applied to the remaining unselected word line (WL 1 ). Accordingly, two transistors (T 21 , T 22 ) whose gates are connected to the second word line (WL 2 ) to which the positive write voltage (V W ) is applied are turned on, thereby connecting the corresponding bit lines (BL 1 , BL 2 ) and gates of the corresponding FeFETs (F 21 , F 22 ). On the other hand, two transistors (T 11 , T 12 ) whose gates are connected to the first word line (WL 1 ) to which the negative write voltage (−V W ) is applied maintain an off state. 
     In addition, a positive write voltage (V W ) is applied to the first bit line (BL 1 ) corresponding to the 21st FeFET (F 21 ) to which data of 1 is to be written, and a negative write voltage (−V W ) is applied to the second bit line (BL 2 ) corresponding to the 22nd FeFET (F 22 ) to which data of 0 is to be written. Accordingly, a positive write voltage (V W ) is applied to the gate of the 21st FeFET (F 21 ), while a negative write voltage (−V W ) is applied to the gate of the 22nd FeFET (F 22 ). At this time, the source lines (SL 1 , SL 2 ) and the read lines (RL 1 , RL 2 ) are maintained at the ground voltage. 
     Accordingly, the gate-source and gate-drain voltages of the 21st FeFET (F 21 ) are expressed as a positive write voltage (V W ), and the gate-source and gate-drain voltages of the 22nd FeFET (F 22 ) are expressed as a negative write voltage (−V W ). Accordingly, the threshold voltage (V TH ) of the 21st FeFET (F 21 ) is lowered to the first threshold voltage (V TH1 ), while the threshold voltage (V TH ) of the 22nd FeFET (F 22 ) is increased to the second threshold voltage (V TH2 ). 
     Referring to  FIG. 4B , in the read process, a pre-designated drain read voltage (V D_READ ) is applied to the second read line (RL 2 ) corresponding to the selected row, and a ground voltage is applied to the remaining read line (RL 1 ) and all bit lines (BL 1 , BL 2 ), word lines (WL 1 , WL 2 ) and source lines (SL 1 , SL 2 ). 
     When the drain read voltage (V D_READ ) is applied to the second read line (RL 2 ), since a current (I ON ) flows through the 21st FeFET (F 21 ) having the first threshold voltage (V TH1 ) that is a negative threshold voltage (V TH ), whereas the 22nd FeFET (F 22 ) has a positive second threshold voltage (V TH2 ), a current (I ON ) flows through the 21st FeFET (F 21 ), whereas no current flows through the 22nd FeFET (F 22 ). Accordingly, by measuring the current (I ON ), data stored in each of the 21st FeFET (F 21 ) and the 22nd FeFET (F 22 ) can be determined. 
     Although the ferroelectric random access memory device of a 1T+1FeFET structure shown in  FIGS. 4A and 4B  have a lower degree of integration compared to the ferroelectric random access memory device of 1FeFET structure of  FIGS. 3A and 3B  due to the addition of one transistor to each memory cell, it has an advantage that write disturbance does not occur during write operation. However, in the ferroelectric random access memory device of the 1T+1FeFET structure, due to the threshold voltage of the added transistor, a threshold voltage drop (V TH  drop) occurs in which the voltage level actually applied to the gate of the 21st FeFET (F 21 ) is lowered than the positive write voltage (V W ). Moreover, since during the write operation, one voltage level swing is required for all the bit lines (BL 1 , BL 2 ) and the word lines (WL 1 , WL 2 ), and during the read operation, the read line (RL 2 ) and the source line (SL 1 ) are driven to generate static current flow, there is still a problem of large power consumption. 
     Here, the reason that the ferroelectric random access memory device does not sense a voltage and measures a current to determine data is because a sneak current may occur. 
     As shown in  FIG. 4B , when applying a pre-designated drain read voltage (V D_READ ) to the selected second read line (RL 2 ) and applying a ground voltage to the remaining read line (RL 1 ), all the bit lines (BL 1 , BL 2 ), the word lines (WL 1 , WL 2 ) and the source lines (SL 1 , SL 2 ), if, for example, the 11th FeFET (F 11 ) connected to the same source line (SL 1 ) as the 21st FeFET (F 21 ) in which data of 1 is stored has a first threshold voltage (V TH1 ) that is a negative threshold voltage (V TH ), that is, if data of 1 is stored in the 11th FeFET (F 11 ) of the unselected row, a sneak current occurs in which the current flowing to the source line (SL 1 ) through the 21st FeFET (F 21 ) also flows to the unselected read line (RL 1 ) through the 11th FeFET (F 11 ). Due to this sneak current, the voltage level of the source line (SL 1 ) is changed. Therefore, the data cannot be determined by sensing the voltage. 
       FIGS. 5A and 5B  are a diagram for explaining a read/write operation of a ferroelectric random access memory device having a 2T+1FeFET structure. 
     In  FIGS. 5A and 5B , each memory cell further comprises, in addition to one transistor (T 1   11 , T 1   12 , T 1   21 , T 1   22 ) and one FeFET (F 11 , F 12 , F 21 , F 22 ), one transistor (T 2   11 , T 2   12 , T 2   21 , T 2   22 ) connected between the drain of the FeFET (F 11 , F 12 , F 21 , F 22 ) and the read line (RL 1 , RL 2 ), and gates of the added transistors (T 2   11 , T 2   12 , T 2   21 , T 2   22 ) are connected to corresponding data lines (DL 1 , DL 2 ). 
     Referring to  FIG. 5A , in the write operation of the ferroelectric random access memory device of a 2T+1FeFET structure, similarly to the ferroelectric random access memory device of a 1T+1FeFET structure, a pre-designated positive write voltage (V W ) is applied to the selected second word line (WL 2 ), and a negative write voltage (−V W ) is applied to the remaining unselected word line (WL 1 ). In addition, a positive write voltage (V W ) is applied to the first bit line (BL 1 ) corresponding to the 21st FeFET (F 21 ) to which data of 1 is to be written, and a negative write voltage (−V W ) is applied to the second bit line (BL 2 ) corresponding to the 22nd FeFET (F 22 ) to which data of 0 is to be written. At this time, the source lines (SL 1 , SL 2 ), the read lines (RL 1 , RL 2 ) and the data lines (DL 1 , DL 2 ) are maintained at the ground voltage. 
     Meanwhile, referring to  FIG. 5B , in the read operation, it is the same as the ferroelectric random access memory device of a 1T+1FeFET structure of  FIGS. 4A and 4B  in that a pre-designated drain read voltage (V D_READ ) is applied to the second read line (RL 2 ) corresponding to the selected row, and a ground voltage is applied to the remaining read line (RL 1 ) and source lines (SL 1 , SL 2 ). Accordingly, one voltage level swing is still required for all the bit lines (BL 1 , BL 2 ) and the word lines (WL 1 , WL 2 ), resulting in high power consumption. 
     However, during the read operation of the ferroelectric random access memory device of a 2T+1FeFET structure, a pre-designated gate read voltage (V G_READ ) is applied to the bit lines (BL 1 , BL 2 ), and a pre-designated data voltage (V DD ) is applied to the data lines (DL 1 , DL 2 ). Accordingly, the ferroelectric random access memory device of a 2T+1FeFET structure has additional transistors (T 2   11 , T 2   12 , T 2   21 , T 2   22 ) on the path through which the read current (I ON ) flows, so that it reduces the amount of static current during read operation compared to a ferroelectric random access memory device of a 1T+1FeFET structure, however a static current still flows, thus the current consumption is not small, and since each memory cell is provided with two transistors, there is a limitation in that the degree of integration is lowered. 
     In particular, due to the need to use a negative level voltage as well as a positive level voltage, there is a problem in that the configuration of the power supply is very complicated. 
       FIG. 6  shows a hysteresis characteristic of a ferroelectric random access memory element according to an embodiment of the present disclosure. 
     The pattern of the hysteresis curve of the FeFET element shown in  FIG. 1  may be variously modified through structural change or composition change, including the gate electrode structure change or the addition of a metal layer inside ferroelectric layer, in the FeFET element. Accordingly, in this embodiment, as shown in  FIG. 6 , the pattern of the hysteresis curve of the FeFET element is shifted in the positive voltage direction, and in particular, the pattern of the hysteresis curve of the FeFET element is shifted such that the first threshold voltage (V TH1 ) of a low voltage level becomes a positive voltage level. Accordingly, both the first threshold voltage (V TH1 ) and the second threshold voltage (V TH2 ) may have positive voltage levels (here, for example, 0.68V and 1.58V). 
     As shown in  FIG. 6 , a technique for shifting a pattern of a hysteresis curve of an FeFET element in a positive voltage direction is a known technique, and thus detailed description thereof will be omitted. 
       FIG. 7  is a diagram for explaining a write operation of a ferroelectric random access memory device according to an embodiment of the present disclosure, and  FIG. 8  shows a write timing diagram of the ferroelectric random access memory of  FIG. 7 . 
     Referring to  FIG. 7 , the structure of the ferroelectric random access memory device according to the present disclosure is basically the same as that of the 1T+1FeFET ferroelectric random access memory device shown in  FIGS. 4A and 4B . That is, it includes a memory cell array including a plurality of memory cells defined by a plurality of word lines (WL), a plurality of read lines (RL), a plurality of bit lines (BL) and a plurality of source lines (SL), each memory cell consisting of one transistor (T 11 , T 12 , T 21 , T 22 ) and one FeFET (F 11 , F 12 , F 21 , F 22 ). However, in this embodiment, the FeFETs (F 11 , F 12 , F 21 , F 22 ) are implemented as FeFET elements in which the pattern of the hysteresis curve is shifted in the positive voltage direction as shown in  FIG. 6 . 
     In each memory cell, both ends of the FeFET (F 11 , F 12 , F 21 , F 22 ) are connected between the corresponding read lines (RL 1 , RL 2 ) and the source lines (SL 1 , SL 2 ) among the plurality of read lines (RL) and the plurality of source lines (SL). In addition, the transistor (T 11 , T 12 , T 21 , T 22 ) is connected between the corresponding bit lines (BL 1 , BL 2 ) among the plurality of bit lines (BL) and the gate of the corresponding FeFET (F 11 , F 12 , F 21 , F 22 ), and the gate is connected to the corresponding word line (WL 1 , WL 2 ) among the plurality of word lines (WL). 
     That is, each transistor (T 11 , T 12 , T 21 , T 22 ) is turned on/off according to a voltage level applied to the corresponding word line (WL 1 , WL 2 ) connected to the gate to electrically connect or block the corresponding bit line (BL 1 , BL 2 ) and the gate of the FeFET (F 11 , F 12 , F 21 , F 22 ). 
     In  FIG. 7 , it is shown as an example that the plurality of word lines (WL) and the plurality of read lines (RL) are arranged to run in parallel in a first direction, and that the plurality of bit lines (BL) and the plurality of source lines (SL) are arranged to run in parallel in a second direction perpendicular to the first direction, however, the running direction of each line may be different depending on the design of the memory cell array. 
     When the write operation of the ferroelectric random access memory device of  FIG. 7  is described with reference to the timing diagram of  FIG. 8 , the write operation of the ferroelectric random access memory device according to the present embodiment also consists of two steps. 
     Here again, the description will be made on the assumption that data is written to the memory cell arranged in the second row as an example, and it is assumed that, in the second row, data of 1 is written to the memory cell of the first column and data of 0 is written to the memory cell of the second column. 
     First, in the first step, a pre-designated positive write voltage (V W ) (for example, 4V) is applied only to the second word line (WL 2 ) and the second read line (RL 2 ) corresponding to the row selected to write data (here, the second row), the plurality of source lines (SL) are floated, and all other lines are maintained at a ground voltage with a voltage level lower than the positive write voltage (V W ). That is, the same positive write voltage (V W ) is applied only to two lines of the selected second word line (WL 2 ) and the second read line (RL 2 ). 
     As the positive write voltage (V W ) is applied to the second word line (WL 2 ), the two transistors (T 21 , T 22 ) whose gates are connected to the second word line (WL 2 ) are turned on, thereby connecting the corresponding bit lines (BL 1 , BL 2 ) and the gates of the corresponding FeFETs (F 21 , F 22 ). 
     Since all the bit lines (BL 1 , BL 2 ) maintain the ground voltage, the positive write voltage (V W ) is also applied to the second read line (RL 2 ), and the source lines (SL) are in a floating state, a reverse voltage difference by the positive write voltage (V W ) is generated between the gate-drain of each of the 21st and 22nd FeFETs (F 21 , F 22 ). Accordingly, the threshold voltage (V TH ) of the 21st and 22nd FeFETs (F 21 , F 22 ) is increased to the second threshold voltage (V TH2 ) of a relatively high voltage level (for example, 1.58V) among the first and second threshold voltages (V TH1 , V TH2 ) according to the hysteresis characteristic of the FeFET. That is, data of 0 is written to all memory cells of the selected row. 
     In  FIGS. 4A, 4B, 5A and 5B , the word line (WL) and the read line (RL) are used separately for a write operation and a read operation, respectively, however in the present disclosure, a positive write voltage (V W ) is applied to the read line (RL 2 ) corresponding to the memory cell selected in the first step during a write operation. However, since all the bit lines (BL 1 , BL 2 ) connected to the gates of the 21st and 22nd FeFETs (F 21 , F 22 ) maintain the ground voltage, and thus the FeFETs (F 21 , F 22 ) maintain the off state, even when the positive write voltage (V W ) is applied to the read line (RL 2 ), the read line (RL 2 ) is only charged with the positive write voltage (V W ), a current path with the corresponding source line (SL 1 , SL 2 ) is not formed, and thus the power consumption is very negligible. In addition, since the second word line (WL 2 ) is connected to the gates of the 21st and 22nd FeFETs (F 21 , F 22 ), the power consumption is likewise very low. 
     Thereafter, in the second step, the positive write voltage (V W ) is still applied to the second word line (WL 2 ), and a ground voltage is applied to the second read line (RL 2 ). In addition, a positive write voltage (V W ) is applied to the first bit line (BL 1 ) corresponding to the memory cell to which data of 1 is to be written. At this time, the unselected word line (WL 1 ), read line (RL 1 ) and bit line (BL 2 ) maintain a ground voltage, and the source lines (SL) maintain a floating state. That is, a voltage swing occurs only in the second read line (RL 2 ) and the first bit line (BL 1 ). 
     Accordingly, a positive write voltage (V W ) is applied to the gate of the 21st FeFET (F 21 ), a ground voltage is applied to the drain, and thus a voltage difference is generated between the gate-drain of the 21st FeFET (F 21 ) by the positive write voltage (V W ), so that the threshold voltage (VIE) of the 21st FeFET (F 21 ) is lowered to the first threshold voltage (V TH1 ) of a relatively low voltage level (for example, 0.68V). That is, data 1 is written to the corresponding memory cell. At this time, since a ground voltage is applied to the gate of the 21st FeFET (F 21 ) through the second bit line (BL 2 ), a gate-drain voltage difference does not occur, thereby maintaining the second threshold voltage (V TH2 ). 
     That is, the ferroelectric random access memory device according to the present embodiment is configured to, when writing data to a memory cell arranged in a selected row, swing only the voltage level applied to one word line (WL 2 ) and one read line (RL 2 ) corresponding to the corresponding row and the bit line (BL 1 ) corresponding to the memory cell to which data of 1 is to be written, so that the power consumption can be greatly reduced. Moreover, since only the same positive write voltage (V W ) is applied to all of the lines in which the voltage level is swung, only one voltage needs to be generated as the voltage level required for the write operation. Therefore, it is possible to greatly simplify the configuration of the power supply of the ferroelectric random access memory device. 
       FIG. 9  is a diagram for explaining a read operation of a ferroelectric random access memory device according to an embodiment of the present disclosure, and  FIG. 10  shows a read timing diagram of the ferroelectric random access memory of  FIG. 7 . 
       FIG. 9  also shows a 1T+1FeFET ferroelectric random access memory device as in  FIG. 7  as a ferroelectric random access memory device according to the present embodiment. However, in the present embodiment, the ferroelectric random access memory device is configured to detect the voltage rather than the current, unlike FIGS.  3 A to  5 B, during the read operation to determine the data, and thus further includes a plurality of sense amplifiers (SA) respectively connected to a plurality of source lines (SL). 
     When the read operation of the ferroelectric random access memory device of  FIG. 9  is described with reference to  FIG. 10 , a pre-designated data voltage (V DD ) is applied to the word line (WL 2 ) corresponding to the selected memory cell, and a pre-designated drain read voltage (V D_READ ) is applied to the read line (RL 2 ), so that the word line (WL 2 ) and the read line (RL 2 ) are pre-charged with the data voltage (V DD ) and drain read voltage (V D_READ ) levels, respectively. 
     In addition, the unselected word line (WL 1 ) and read line (RL 1 ) are maintained at the ground voltage, a pre-designated gate read voltage (V G_READ ) is applied to all the bit lines (BL 1 , BL 2 ), and all source lines (SL) maintain a floating state. 
     That is, in the present embodiment, the word line (WL 2 ) corresponding to the selected memory cell is used by applying the data voltage (V DD ) not only during the write operation but also during the read operation. 
     Here, the gate read voltage (V G_READ ) may have a voltage level (for example, 1V) between the first threshold voltage (V TH1 ) and the second threshold voltage (V TH2 ). In addition, the data voltage (V DD ) may be set to the same level as the gate read voltage (V G_READ ), and the drain read voltage (V D_READ ) may have a voltage level (for example, 1.5V) between the gate read voltage (V G_READ ) and the positive write voltage (V W ). 
     The data voltage (V DD ) is applied to the word line (WL 2 ), and thus the two transistors (T 21 , T 22 ) are turned on, so that the gate read voltage (V G_READ ) applied to the bit lines (BL 1 , BL 2 ) is applied to the gates of the 21st and 22nd FeFETs (F 21 , F 22 ). At this time, the 21st FeFET (F 21 ) having a low first threshold voltage (Van) is turned on in response to the gate read voltage (V G_READ ) applied through the first bit line (BL 1 ) and the 21st transistor (T 21 ), however, the 22nd FeFET (F 22 ) is maintained in a turned-off state since it has a relatively high second threshold voltage (V TH2 ). In addition, the read line (RL 2 ) pre-charged with the drain read voltage (V D_READ ) is connected to the drains of the 21st and 22nd FeFETs (F 21 , F 22 ), and source lines (SL 1 , SL 2 ) in a floating state are connected to the sources, respectively. 
     Accordingly, the drain read voltage (V D_READ ) applied to the drain of the 21st FeFET (F 21 ) through the second read line (RL 2 ) is applied to the corresponding sense amplifier (SA) through the first source line (SL 1 ). However, in the 22nd FeFET (F 22 ), due to the second threshold voltage (V TH2 ), the drain read voltage (V D_READ ) applied through the second read line (RL 2 ) is blocked so that the second source line (SL 2 ) maintains a floating state. That is, the drain read voltage (V D_READ ) is not applied to the sense amplifier (SA). 
     Accordingly, each sense amplifier may detect the voltage level applied through the corresponding source line (SL 1 , SL 2 ) to determine the data stored in the corresponding memory cell. 
     The sense amplifier (SA) is generally implemented as an OP amplifier or the like, so that no current flows from the input terminal side. Therefore, even when the drain read voltage (V D_READ ) is applied from the second read line (RL 2 ) to the first source line (SL 1 ), the current (I ON ) flows only temporarily while the first source line (SL 1 ) is charged, and then the current (I ON ) does not flow thereafter. Accordingly, data can be read with minimal power consumption. 
     As a result, the ferroelectric random access memory device according to the present embodiment uses both a read line and a word line in both read and write operations, and detects data based on voltage, so that not only can it significantly reduce power consumption, but also it can read and write data with a small number of voltage levels without generating a negative voltage. 
       FIG. 11  shows a schematic structure of a ferroelectric random access memory device according to an embodiment of the present disclosure. 
     Referring to  FIG. 11 , the ferroelectric random access memory device of the present embodiment may include a memory cell array  110 , a sense amplifier unit  120 , a row decoder  130 , a column decoder  140 , a data input/output unit  150  and a power supply unit  160 . 
     In the memory cell array  110 , a plurality of word lines (WL), a plurality of read lines (RL), a plurality of bit lines (BL) and a plurality of source lines (SL) are arranged in a pre-designated direction, respectively, and a plurality of memory cells defined by the plurality of word lines (WL), the plurality of read lines (RL), the plurality of bit lines (BL) and the plurality of source lines (SL) are provided. In addition, as shown in  FIGS. 7 and 9 , each of the plurality of memory cells (MC) is composed of one transistor (T) and one FeFET (F), and can store different data according to the threshold voltage level of the FeFET. 
     The sense amplifier unit  120  has a plurality of sense amplifiers respectively connected to the plurality of source lines (SL) of the memory cell array  110 , and detects and amplifies a voltage applied through the source lines during a read operation, and transmits it to the data input/output unit  150 . That is, it determines the data stored in the selected memory cell and stores it in the data input/output unit  150 . 
     The row decoder  130  receives a row address and a read or write command among address information applied to designate a memory cell to be read or written. The row decoder  130  decodes the row address to select the word line (WL) and the read line (RL) corresponding to the row address from among the plurality of word lines (WL) and the plurality of read lines (RL), and applies a pre-designated voltage to each of the selected word line (WL) and read line (RL) depending on whether it is a read command or a write command, thereby activating it. 
     When a write command is applied, the row decoder  130 , in the first step, applies a pre-designated positive write voltage (V W ) to both the selected word line (WL) and read line (RL), and then, in the second step, applies the positive write voltage (V W ) to the selected word line (WL) as it is, while applying a ground voltage to the read line (RL). 
     On the other hand, when a read command is applied, the row decoder  130  applies a pre-designated data voltage (V DD ) to the selected word line (WL), and applies a pre-designated drain read voltage (V D_READ ) to the selected read line (RL), thereby activating it. 
     The column decoder  140  receives a column address from among the address information, decodes the column address, and transmits it to the data input/output unit  150 . 
     The data input/output unit  150  receives a read or write command, and receives the decoded column address from the column decoder  140 . If the applied command is a write command, the data input/output unit  150  first applies a ground voltage to all the bit lines (BL) in the first step, and floats all source lines (SL), so that the threshold voltages of FeFETs (F) of all memory cells (MC) connected to the word line (WL) and the read line (RL) selected by the row decoder  130  become the second threshold voltage (V TH2 ) of a high voltage level, so that data of 0 is written. 
     In the second step, it applies a positive write voltage (V W ) to a bit line (BL) corresponding to a memory cell to which data of 1 is to be written according to data applied corresponding to each column address, so that the threshold voltage of the FeFET (F) of the memory cell (MC) connected to the corresponding bit line (BL) becomes the first threshold voltage (V TH1 ) of a low voltage level, so that data of 1 is written. 
     On the other hand, if the applied command is a read command, the data input/output unit  150  applies a gate read voltage (V G_READ ) to all bit lines (BL), and receives the data amplified and determined by the plurality of sense amplifiers of the sense amplifier unit  120  and outputs it to the outside. 
     Here, for example, the configuration of the row decoder  130 , the column decoder  140  and the data input/output unit  150  may be integrated into the read/write control unit. 
     The power supply unit  160  generates a positive write voltage (V W ), a data voltage (V DD ), a drain read voltage (V D_READ ) and a gate read voltage (V G_READ ), and applies the positive write voltage (V W ) to the row decoder  130 , and outputs a data voltage (V DD ), a drain read voltage (V D_READ ) and a gate read voltage (V G_READ ) to the data input/output unit  150 . 
       FIG. 12  shows a write method of a ferroelectric random access memory device according to an embodiment of the present disclosure. 
     Referring to  FIGS. 7, 8 and 11 , with regard to the write method of a ferroelectric random access memory device according to the present embodiment, first, in the first step (S 10 ), by decoding row address information among the applied address information, a word line (WL) and a read line (RL) corresponding to the row address are selected from among a plurality of word lines (WL) and a plurality of read lines (RL) (S 11 ). That is, memory cells (MC) are selected in units of rows, among the plurality of memory cells (MC) of the memory cell array  100 . Then, in response to a write command, a pre-designated positive write voltage (VW) is applied to both the selected word line (WL) and read line (RL) (S 12 ). At this time, a ground voltage is maintained to the bit line (BL) and the remaining unselected word line (WL) and the read line (RL), and source lines are floated, so that the threshold voltages of FeFETs (F) of all memory cells (MC) connected to the selected word line (WL) and read line (RL) become the second threshold voltage (V TH2 ) of a high voltage level, so that data of 0 is written (S 13 ). 
     Thereafter, in the second step (S 20 ), the column address among the applied address information is decoded, and data to be stored in each of the memory cells (MC) of the row is received and obtained (S 21 ). Then, the bit line (BL) corresponding to the memory cell (MC) to which data of 1 is to be written is selected according to the applied data (S 22 ). When the bit line (BL) is selected, a positive write voltage (V W ) is applied to the selected bit line (BL), so that the threshold voltage of the FeFET (F) of the corresponding memory cell (MC) becomes the first threshold voltage (V TH1 ) of a low voltage level, so that data of 1 is written (S 23 ). 
       FIG. 13  shows a read method of a ferroelectric random access memory device according to an embodiment of the present disclosure. 
     Referring to  FIGS. 9 to 11 , with regard to the write method of a ferroelectric random access memory device according to the present embodiment, by decoding row address information among the applied address information, a word line (WL) and a read line (RL) corresponding to the row address are selected from among a plurality of word lines (WL) and a plurality of read lines (RL) (S 31 ). Then, in response to a read command, a pre-designated data voltage (V DD ) is applied to the selected word line (WL), and a pre-designated drain read voltage (V D_READ ) is applied to the selected read line (RL) (S 32 ). 
     In addition, a gate read voltage (V G_READ ) is applied to all bit lines (BL), and all source lines (SL) are floated (S 33 ). 
     Thereafter, data is determined by sensing and amplifying the voltage applied to the source line (SL) according to the threshold voltage of the FeFET (F) of each memory cell (MC) (S 34 ). Then, the determined data is output (S 35 ). 
     A method according to the present disclosure can be implemented as a computer program stored in a medium for execution on a computer. Here, the computer-readable medium can be an arbitrary medium available for access by a computer, where examples can include all types of computer storage media. Examples of a computer storage medium can include volatile and non-volatile, detachable and non-detachable media implemented based on an arbitrary method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data, and can include ROM (read-only memory), RAM (random access memory), CD-ROM&#39;s, DVD-ROM&#39;s, magnetic tapes, floppy disks, optical data storage devices, etc. 
     While the present disclosure is described with reference to embodiments illustrated in the drawings, these are provided as examples only, and the person having ordinary skill in the art would understand that many variations and other equivalent embodiments can be derived from the embodiments described herein. 
     Therefore, the true technical scope of the present disclosure is to be defined by the technical spirit set forth in the appended scope of claims.