Patent Publication Number: US-10790398-B2

Title: Chalcogen back surface field layer

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. application Ser. No. 15/281,789 filed on Sep. 30, 2016, now U.S. Pat. No. 10,014,423, the disclosure of which is incorporated by reference herein. 
    
    
     STATEMENT OF GOVERNMENT RIGHTS 
     This invention was made with Government support under Contract number DE-EE0006334 awarded by Department of Energy. The Government has certain rights in this invention. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to kesterite (e.g., CZT(S,Se)) photovoltaic devices and more particularly, to kesterite photovoltaic devices having a chalcogen (e.g., selenium (Se), sulfur (S) and/or tellurium (Te)) back surface field layer. 
     BACKGROUND OF THE INVENTION 
     Copper zinc tin sulfo-selenide (CZT(S,Se)) is a non-toxic, earth abundant kesterite material that is used as the light absorbing material for thin film photovoltaic devices. CZT(S,Se) has many advantages relative to other thin film photovoltaic devices but overall the efficiency is a little more than half that of copper indium gallium selenide (CIGSe), cadmium telluride (CdTe), and bulk silicon (Si) photovoltaic devices. The primary reason for this low efficiency is the abundance of bulk defects that arise during fabrication of the CZT(S,Se) material. 
     To circumvent this efficiency deficit, device simulations have shown that if the absorber thickness is reduced to 1 micrometer (μm) or below, and a high work function back contact is utilized, then electrostatic field effects can result in higher open circuit voltages (Voc) and hence a higher efficiency CZT(S,Se) device. However, a high degree of electron-hole recombination at the back contact works to lower Voc. 
     Therefore, improved CZT(S,Se) device configurations and techniques for the fabrication thereof that solve these efficiency and electron-hole recombination challenges would be desirable. 
     SUMMARY OF THE INVENTION 
     The present invention provides kesterite photovoltaic devices having a chalcogen (e.g., selenium (Se), sulfur (S) and/or tellurium (Te)) back surface field layer. In one aspect of the invention, a method of forming a photovoltaic device is provided. The method includes: forming a complete photovoltaic device having a substrate, an electrically conductive layer on the substrate, an absorber layer (e.g., a kesterite absorber layer having copper, zinc, tin, and at least one of sulfur and selenium) on the electrically conductive layer, a buffer layer on the absorber layer, and a transparent front contact on the buffer layer; removing the substrate and the electrically conductive layer from the complete photovoltaic device to expose a backside surface of the absorber layer; forming a passivating layer (e.g., a selenium, sulfur, and/or tellurium layer) on the backside surface of the absorber layer; and forming a high work function back contact on the passivating layer. 
     In another aspect of the invention, a photovoltaic device is provided. The photovoltaic device includes: a high work function back contact; a passivating layer on the high work function back contact, wherein the passivating layer includes a material selected from: pure selenium, pure sulfur, and pure tellurium; an absorber layer (e.g., a kesterite absorber layer having copper, zinc, tin, and at least one of sulfur and selenium) on the passivating layer; a buffer layer on the absorber layer; and a transparent front contact on the buffer layer. 
     A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating an exemplary methodology for forming a CZT(S,Se)-based PV device having a Se, S and/or Te backside passivating layer according to an embodiment of the present invention; 
         FIG. 2  is a cross-sectional diagram illustrating a substrate having a layer(s) of an electrically conductive material formed thereon according to an embodiment of the present invention; 
         FIG. 3  is a cross-sectional diagram illustrating a CZT(S,Se) absorber layer having been formed on the conductive layer according to an embodiment of the present invention; 
         FIG. 4  is a cross-sectional diagram illustrating a buffer layer having been formed on the CZT(S,Se) absorber layer according to an embodiment of the present invention; 
         FIG. 5  is a cross-sectional diagram illustrating a transparent front contact having been formed on the buffer layer according to an embodiment of the present invention; 
         FIG. 6  is a cross-sectional diagram illustrating a metal grid having been formed on the transparent front contact according to an embodiment of the present invention; 
         FIG. 7  is a cross-sectional diagram illustrating the CZT(S,Se) absorber layer, the buffer layer, the transparent front contact, and the metal grid having been separated from the conductive layer and substrate according to an embodiment of the present invention; 
         FIG. 8  is a cross-sectional diagram illustrating a passivating layer having been formed on the backside surface of the CZT(S,Se) absorber layer according to an embodiment of the present invention; 
         FIG. 9  is a cross-sectional diagram illustrating a high work function back contact having been formed on the passivating layer according to an embodiment of the present invention; 
         FIG. 10  is a cross-sectional diagram illustrating the completed CZT(S,Se)-based photovoltaic device according to an embodiment of the present invention; and 
         FIG. 11  is a diagram illustrating performance of exemplary devices prepared according to the present techniques according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     As provided above, for CZT(S,Se) absorber-based devices if the absorber thickness is reduced (e.g., to less than or equal to about 1 micrometer (μm)) and a high work function back contact is used, then electrostatic field effects can result in higher open circuit voltages (Voc) and hence a higher efficiency CZT(S,Se) device. A notable challenge to this approach, however, is that a high degree of electron-hole recombination at the back contact occurs which actually lowers the Voc. 
     Advantageously, a solution to this electron-hole recombination problem is provided herein where a passivating layer is implemented to reduce the electron-hole recombination. Specifically, according to the present techniques, an intermediate film of a chalcogen such as selenium (Se), sulfur (S) and/or tellurium (Te) is added to the back surface of the device which has been found to result in higher device efficiencies. The term “chalcogen” generally refers to the elements in group 16 of the periodic table. As will be described in detail below, the present techniques involve a unique process by which the substrate and conductive layer are removed (e.g., exfoliated) from a completed device, and replaced with the passivating layer followed by a high work function back contact. 
     The present techniques are now described by way of reference to methodology  100  of  FIG. 1 , along with reference to  FIGS. 2-10 . In step  102 , a complete CZT(S,Se)-based photovoltaic device is fabricated. By “CZT(S,Se)-based” it is meant that CZT(S,Se) serves as the absorber material of the photovoltaic device. As its name implies, a CZT(S,Se) material contains common, readily available elements namely copper (Cu), zinc (Zn), tin (Sn), and at least one of sulfur (S) and selenium (Se). For a general discussion on kesterites and use of kesterite in solar cells, see, for example, Mitzi et al., “Prospects and performance limitations for Cu—Zn—Sn—S—Se photovoltaic technology,” Phil Trans R Soc A 371 (July 2013), the contents of which are incorporated by reference as if fully set forth herein. 
     By first forming a completed device (and then subsequently replacing the substrate and conductive layer with a passivating layer and high work function back contact—see below) allows for all processes necessary for device fabrication to be carried out before the passivating layer is put in place. For instance, as will be described in detail below, an anneal (preferably in a chalcogen environment) is performed post-deposition of the CZT(S,Se) absorber. By placing the passivating layer at the end of the process, the passivating layer does not experience these anneal conditions, and thus does not undergo intermixing with the CZT(S,Se) absorber. As a result, the passivating layer can remain distinct from the CZT(S,Se) absorber. For instance, according to an exemplary embodiment, the passivating layer is a layer of pure elemental selenium (Se), sulfur (S) and/or tellurium (Te). It is notable that the CZT(S,Se) absorber and/or any layers formed by interaction with the CZT(S,Se) absorber would not contain pure elemental selenium (Se), sulfur (S) and/or tellurium (Te). 
     According to an exemplary embodiment, the CZT(S,Se)-based photovoltaic device is fabricated in step  102  as follows. The fabrication process begins with a suitable device substrate  202  coated with a layer  204  (or optionally multiple layers represented generically by layer  204 ) of an electrically conductive material. See  FIG. 2 . 
     Suitable substrates include, but are not limited to, glass, ceramic, metal foil, or plastic substrates. Suitable materials for forming conductive layer  204  include, but are not limited to, molybdenum (Mo), molybdenum trioxide (MoO 3 ), gold (Au), nickel (Ni), tantalum (Ta), tungsten (W), aluminum (Al), platinum (Pt), titanium nitride (TiN), silicon nitride (SiN), and combinations including at least one of the foregoing materials (for example as an alloy of one or more of these metals or as a stack of multiple layers such as MoO 3 +Au). According to an exemplary embodiment, the conductive layer  204  is coated on substrate  202  to a thickness of greater than about 0.1 micrometers (μm), e.g., from about 0.1 μm to about 2.5 μm, and ranges therebetween. In general, the various layers of the device will be deposited sequentially using a combination of vacuum-based and/or solution-based approaches. By way of example only, the electrically conductive material  204  can be deposited onto the substrate  202  using evaporation or sputtering. 
     Next, a CZT(S,Se) absorber layer  302  is formed on the conductive layer  204 . See  FIG. 3 . As highlighted above, the CZT(S,Se) absorber layer  302  contains Cu, Zn, Sn, and at least one of S and Se. According to an exemplary embodiment, the CZT(S,Se) absorber layer  302  is formed having a total thickness of from about 0.5 micrometers (μm) to about 2 μm, and ranges therebetween. 
     The CZT(S,Se) absorber layer  302  can be formed using vacuum-based, solution-based, or other suitable approaches to form a stack of layers. See for example U.S. Patent Application Publication Number 2012/0061790 by Ahmed et al., entitled “Structure and Method of Fabricating a CZTS Photovoltaic Device by Electrodeposition,” the contents of which are incorporated by reference as if fully set forth herein. The sequence of the layers in the stack can be configured to achieve optimal band grading and/or adhesion to the substrate. See, for example, Dullweber et al., “Back surface band gap gradings in Cu(In,Ga)Se 2  solar cells,” Thin Solid Films, vol. 387, 11-13 (May 2001), the contents of which are incorporated by reference as if fully set forth herein. 
     Suitable solution-based kesterite fabrication techniques are described, for example, in U.S. Patent Application Publication Number 2013/0037111 by Mitzi et al., entitled “Process for Preparation of Elemental Chalcogen Solutions and Method of Employing Said Solutions in Preparation of Kesterite Films,” the contents of which are incorporated by reference as if fully set forth herein. Suitable particle-based precursor approaches for CZT(S,Se) formation are described, for example, in U.S. Patent Application Publication Number 2013/0037110 by Mitzi et al., entitled “Particle-Based Precursor Formation Method and Photovoltaic Device Thereof,” the contents of which are incorporated by reference as if fully set forth herein. 
     Since the as-deposited materials have poor grain structure and a lot of defects, following deposition of the CZT(S,Se) materials a post anneal in a chalcogen environment is preferably performed. An anneal in a chalcogen environment improves the grain structure and defect landscape in the CZT(S,Se) material. According to an exemplary embodiment, the anneal is performed at a temperature of from about 400 degrees Celsius (° C.) to about 800° C., and ranges therebetween. 
     A buffer layer  402  is then formed on the CZT(S,Se) absorber layer  302 . See  FIG. 4 . The buffer layer  402  forms a p-n junction with the CZT(S,Se) absorber layer  302 . According to an exemplary embodiment, the buffer layer  402  is formed having a thickness of from about 100 angstroms (Å) to about 1,000 Å, and ranges therebetween. 
     Suitable buffer layer materials include, but are not limited to, cadmium sulfide (CdS), a cadmium-zinc-sulfur material of the formula Cd 1-x Zn,S (wherein 0&lt;x≤1), indium sulfide (In 2 S 3 ), zinc oxide, zinc oxysulfide (e.g., a Zn(O,S) or Zn(O,S,OH) material), and/or aluminum oxide (Al 2 O 3 ). According to an exemplary embodiment, the buffer layer  402  is deposited on the CZT(S,Se) absorber layer  302  using standard chemical bath deposition. 
     A transparent front contact  502  is then formed on the buffer layer  402 . See  FIG. 5 . Suitable transparent front contact materials include, but are not limited to, transparent conductive oxides (TCOs) such as indium-tin-oxide (ITO) and/or aluminum (Al)-doped zinc oxide (ZnO) (AZO)). According to an exemplary embodiment, the transparent front contact  502  is formed on the buffer layer  402  by sputtering. 
     Optionally, a metal grid  602  can be formed on the transparent front contact  502 . See  FIG. 6 . Suitable materials for forming the metal grid  602  include, but are not limited to, Ni and/or Al. According to an exemplary embodiment, the metal grid  602  is formed on the transparent front contact  502  using evaporation or sputtering. Forming a complete photovoltaic device at the beginning of the process enables steps to be undertaken to produce a high quality device. For instance, building the device on a Mo-coated glass substrate can be beneficial in terms of coefficient of thermal expansion (CTE) matching between the device and the substrate, as well as it permits the formation of beneficial secondary compounds such as MoS 2  and/or MoSe 2 , etc. 
     Referring back to methodology  100 , in step  104  the photovoltaic device including the CZT(S,Se) absorber layer is separated from the underlying substrate and conductive layer. This will expose the backside surface of the CZT(S,Se) absorber layer, which is a side of the CZT(S,Se) absorber layer opposite the buffer layer. According to an exemplary embodiment, step  104  is carried out using an exfoliation process. Exfoliation involves attaching the front of the device to a quartz plate via epoxy adhesive and mechanically removing it from the substrate. The weakest point of the stack is the absorber layer/conductive layer interface where the exfoliation takes place. 
     Step  104  is illustrated schematically in  FIG. 7 . As shown in  FIG. 7 , a quartz plate  702  is attached (e.g., epoxied) to the front of the stack (i.e., on the transparent front contact  502  over the metal grid  602 ) and the CZT(S,Se) absorber layer  302  (and with it the buffer layer  402 , the transparent front contact  502 , and the metal grid  602 ) is separated from the conductive layer  204 /substrate  202 ). The backside surface of the CZT(S,Se) absorber layer  302  (i.e., a side of the CZT(S,Se) absorber layer  302  opposite the buffer layer  402 ) is now exposed. The conductive layer  204 /substrate  202  can be discarded or used in the production of additional devices. The quartz plate  702  can remain in place or, as shown in the figures, be removed following exfoliation. 
     Referring back to methodology  100 , in step  106  a passivating layer is next deposited onto the (now-exposed) backside surface of the CZT(S,Se) absorber layer. According to an exemplary embodiment, the passivating layer includes Se, S, and/or Te and is formed on the backside surface of the CZT(S,Se) absorber layer to a thickness of from about 1 nanometer (nm) to about 100 nm, and ranges therebetween. As highlighted above, the passivating layer serves to passivate or suppress electron-hole recombination at the high workfunction back contact (to be formed as per step  108 —described below) which enhances device efficiency. By way of example only, the passivating layer can be deposited onto the backside surface of the CZT(S,Se) absorber layer using evaporation or sputtering. 
     As described above, by placing the passivating layer at the end of the process, the passivating layer does not experience the high temperature annealing conditions associated with the absorber fabrication, and thus the passivating layer does not intermix with the CZT(S,Se) absorber. As a result, the passivating layer remains as a separate layer from the CZT(S,Se) absorber having a distinct composition, e.g., according to an exemplary embodiment the passivating layer is a layer of pure elemental Se, S and/or Te. 
     Step  106  is illustrated schematically in  FIG. 8 . As shown in  FIG. 8 , the conductive layer  204 /substrate  202  have been taken away (e.g., and discarded or re-used). The remaining device structure is also shown flipped such that the backside surface of the CZT(S,Se) absorber layer is now on top. This flipping is done for ease of manufacture such that the additional device layers (i.e., passivating layer, high workfunction back contact, etc.) can be formed sequentially, one on top of the other. As shown in  FIG. 8 , a passivating layer  802  (including, e.g., Se, S, and/or Te) has been formed on the backside surface of the CZT(S,Se) absorber layer  302 . 
     Referring back to methodology  100 , in step  108  a high work function (e.g., above 4.5 electron volts (eV)) back contact is formed on the passivating layer. Suitable materials for the high work function back contact include, but are not limited to, Mo, MoO 3 , Au, Ni, Ta, W, Al, Pt, TiN, SiN, and combinations thereof. For instance, according to an exemplary embodiment, the high work function back contact is formed from MoO 3 +Au. 
     Step  108  is illustrated schematically in  FIG. 9 . As shown in  FIG. 9 , a high work function back contact  902  is formed on the passivating layer  802 . The high work function back contact  902  is separated from the CZT(S,Se) absorber layer  302  by the passivating layer  802 . The passivating layer  802  serves to passivate or suppress electron-hole interface recombination at the high work function back contact  902  which enhances device efficiency as is illustrated in the examples provided below. Electron-hole recombination at the interface between the high work function back contact  902  and the CZT(S,Se) absorber layer  302  is suppressed by inclusion of the higher band gap surface field material (i.e., the passivating layer  802 ) at that interface. 
     The completed CZT(S,Se)-based photovoltaic device is shown in  FIG. 10 . The depiction provided in  FIG. 10  has the device turned right-side up, with the high work function back contact  902  at the bottom. As shown in  FIG. 10 , the high work function back contact  902  is separated from the CZT(S,Se) absorber layer  302  by the passivating layer  802 . Specifically, the CZT(S,Se)-based photovoltaic device as shown in  FIG. 10  includes high work function back contact  902 , passivating layer  802  on the high work function back contact  902 , CZT(S,Se) absorber layer  302  on the passivating layer  802 , buffer layer  402  on the CZT(S,Se) absorber layer  302 , transparent front contact  502  on the buffer layer  402 , and metal grid  602  on the transparent front contact  502 . 
     The present techniques are now described in further detail by way of reference to the following non-limiting device examples shown in  FIG. 11 . The data in  FIG. 11  shows the results from a control pre-exfoliated CZT(S,Se) device (open boxes) for a 1.1 μm thick CZT(S,Se) absorber layer. 
     Before the addition of a 10 nm Se (passivating) layer the highest device efficiencies were less than 9 percent (%). Incorporation of a pure Se passivating layer, lead to up to a 36 millivolt (mV) increase in open circuit voltage (Voc), up to an 11% increase in fill factor (FF), up to 6 milliamps per square centimeter (mA/cm 2 ) in short circuit current, and an absolute 3.7% increase in efficiency. The results in  FIG. 11  are shown for 15 different devices. Notably device #8 had an efficiency of 12.2%, a 68.5% FF, a Voc of 467 mV, and a short circuit current of 38 mA/cm 2 . See  FIG. 11 . 
     Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope of the invention.