Patent Publication Number: US-5893149-A

Title: Flushing of cache memory in a computer system

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     This invention relates to caches in computer systems. In particular, this invention relates to a mechanism for maintaining data coherency when replacing data in the caches of these computer systems. 
     Incorporation by Reference 
     This patent application is related to the following copending, commonly assigned patent applications, the disclosures of which are incorporated herein by reference in their entirety: 
     Description of the Related Art 
     In a multi-level cache computer system having at least a lower-level cache and a higher-level cache, since the cache sizes are not infinitely large, eventually it becomes necessary to replace duplicated data in the computer system&#39;s cache memory in order to make room for caching new data. Generally, the smaller lower-level cache can replace data in its cache lines by generating write-backs, while replacement of the cached data pages in the larger higher-level cache is done under software control. 
     In one simplistic scheme, when a page in the higher-level cache memory needs to be replaced from a requesting subsystem of the computer system, the following sequence of steps are performed. For every cache line associated with the page, regardless of the status of the cache line, a &#34;replace request&#34; message is propagated, all the way to the data&#39;s home location. The home location references a home directory to determine the status of the cache line. If the requesting subsystem has &#34;dirty&#34; data, a request for the data is made from the home location to the requesting subsystem. The requesting subsystem then provides the data to the home location. Upon receipt of the data, the home location marks the appropriate entry of the home directory &#34;Invalid&#34; and a &#34;replace --  completed&#34; message is sent back to the requesting subsystem. 
     Unfortunately, the above-described simplistic scheme generates an excessive amount of network traffic because an unnecessary number of network messages are exchanged between the requesting subsystem and the home location. 
     Thus there is a need for an efficient mechanism for replacing data in the cache memory of a computer system which maintains data coherency while reducing network traffic within the computer system. 
     SUMMARY OF THE INVENTION 
     The present invention provides an efficient streamlined cache coherent protocol for replacing data in a multiprocessor distributed-memory computer system. In one implementation, the computer system includes a plurality of subsystems, each subsystem includes at least one processor and an associated cache and directory. The subsystems are coupled to a global interconnect via global interfaces. 
     In one embodiment, when data is replaced from a requesting subsystem, an asynchronous flush operation is initiated. In this implementation, the flush operation includes a pair of decoupled local flush instruction and corresponding global flush instruction. By decoupling the local flush instructions from the global flush instructions, once the requesting processor in the requesting subsystem is done issuing the local flush instruction, the requesting processor does not have to wait for a corresponding response from home location associated with the data being replaced. Instead, the requesting processor is freed up quickly since there is no need to wait for an acknowledgment from the home location (home subsystem) over the global interconnect. 
     In this embodiment, the home subsystem responds with an appropriate ACK message. The requesting subsystem reissues a read-to-own (RTO) transaction on its local interconnect thereby retrieving and invalidating any copy(s) of the data in the requesting subsystem. A Completion message is sent to the home subsystem together with the dirty data. 
     Subsequently, a confirmation of the completion of the flush operation can be implemented using a &#34;synchronization&#34; mechanism provided by the computer system. Once such confirmation verifies that all previously valid cache lines associated with a page have been successfully replaced with respect to their home location, then the replaced cache lines can now be marked &#34;invalid&#34; at the home subsystem. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     The objects, features and advantages of the system of the present invention will be apparent from the following description in which: 
     FIG. 1A is a block diagram showing a networked computering system 100 with a hybrid cache-only memory architecture/non-uniform memory architecture (COMA/NUMA). 
     FIG. 1B is an exemplary memory map for a networked computering system of FIG. 1A. 
     FIGS. 2A and 2B are flowcharts illustrating one embodiment of the invention. 
     FIG. 3 is a protocol table depicting the operation of the embodiment illustrated by FIG. 2. 
     FIG. 4 is a block diagram depicting one embodiment of the global interface of Figure IA. 
     FIG. 5 is a block diagram of one embodiment of one portion of the global interface of FIG. 4. 
     FIG. 6 is a table depicting synchronous operations employed by one embodiment of the computer system of FIG. 1A. 
     FIG. 7 is an exemplary code sequence using one of the synchronization operations shown in FIG. 6. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the following description, numerous details provide a thorough understanding of the invention. These details include functional blocks and an exemplary cache architecture to aid implementation of a cost-effective scheme for maintaining data coherency within a computer system. In addition, while the present invention is described with reference to a specific data coherent scheme for a distributed cache of a multiprocessor computer system, the invention is applicable to a wide range of caches and network architectures. In other instances, well-known circuits and structures are not described in detail so as not to obscure the invention unnecessarily. 
     The above-identified pending applications disclose a hybrid cache-only memory architecture/non-uniform memory architecture (COMA/NUMA) having a shared global memory address space and a coherent caching system for a networked computing system. FIG. 1A is a block diagram showing one such hybrid COMA/NUMA computer system 100 which provides a suitable exemplary hardware environment for the present invention. 
     System 100 includes a plurality of subsystems 110, 120, . . . 180, coupled to each other via a global interconnect 190. Each subsystem is assigned a unique network node address. Each subsystem includes one or more processors, a corresponding number of memory management units (MMUs) and hybrid second level caches (L2$s), a COMA cache memory assigned with portion of a global memory address space, an optional third-level cache (L3$), a global interface and a local interconnect. For example, subsystem 110 includes processors 111a, 111b . . . 111i, MMUs 112a, 112b, . . . 112i, L2$s 113a, 113b, . . . 113i, COMA cache memory 114, L3$ 118, global interface 115 and local interconnect 119. In order to support a directory-based cache coherency scheme, subsystems 110, 120, . . . 180 also include directories 116, 126, . . . 186 coupled to global interfaces 115, 125, . . . 185, respectively. 
     Data originating from, i.e., whose &#34;home&#34; location is, anyone of COMA cache memories 114, 124, . . . 184 may be duplicated in cache memory of system 100. For example, in COMA mode, system 100&#39;s cache memory includes both COMA cache memories 114, 124, . . . 184 and L2$s 113a . . . 113i, 123a . . . 123i, and 183a . . . 183i, and data whose &#34;home&#34; is in cache memory 114 of subsystem 110 may be duplicated in one or more of cache memories 124, . . . 184 and may also be duplicated in one or more of L2$s 113a . . . 113i, 123a . . . 123i, and 183a . . . 183i. Alternatively, in NUMA mode, system 100&#39;s cache memory includes L2$s 113a . . . 113i, 123a . . . 123i, and 183a . . . 183i, and data whose &#34;home&#34; is in cache memory 114 of subsystem 110 may be duplicated in one or more of L2$s 113a . . . 113i, 123a . . . 123i, and 183a . . . 183i. 
     In one embodiment of the present invention, as illustrated by the hybrid COMA/NUMA computer system 100 of FIG. 1A and the memory map of FIG. 1B, the &#34;home&#34; location of a page of data is in COMA cache memory 124 of subsystem 120, i.e., subsystem 120 is the home subsystem. The content of the home page can also exist in the cache memory space of one or more of requesting subsystems, for example, in the memory space of requesting subsystem 110. Hence, in COMA mode, memory space is allocated in COMA cache memory 114 in page increments, also known as shadow pages, and optionally in hybrid L2$s 113a, 113b, . . . 113i in cache line increments. Alternatively, in NUMA mode, memory space can be allocated in hybrid L2$ 113a, 113b, . . . 113i in cache line increments. Note that the allocation of memory units in system 100, pages and cache lines, are only exemplary and other memory units and sub-units are possible. See pending patent applications &#34;A Hybrid NUMA Coma Caching System And Methods For Selecting Between The Caching Modes&#34; by Hagersten et al., filed Dec. 22, 1995, Ser. No. 08/577,283. (Reference Number P1003) and &#34;A Hybrid NUMA Coma Caching System And Methods For Selecting Between The Caching Modes&#34; by Wood et al., filed Dec. 22, 1995, Ser. No. 08/575,787. (Reference Number P1004) which describe in detail the hybrid COMA/NUMA architecture and methods for selecting between the COMA/NUMA modes, respectively. 
     Home directory 126 is responsible for maintaining the states of existing copies of the home page throughout system 100. In addition, MTAGs associated with the home memory and any shadow page in subsystems 110, 180 track the status of the local copies in each requesting subsystem using one of the following four exemplary states. 
     An invalid (&#34;I&#34;) state indicates that a particular subsystem does not have a (cached) copy of a data line of interest. 
     A shared (&#34;S&#34;) state indicates that the subsystem, and possibly other nodes, have a shared (cached) copy of the data line of interest. 
     An owned (&#34;O&#34;) state indicates that the subsystem, and possibly other nodes, have a (cached) copy of the data line of interest. The subsystem with the O copy is required to perform a write-back upon replacement. 
     A modified (&#34;M&#34;) state indicates that the subsystem has the only (cached) copy of the data line of interest, i.e., the subsystem is the sole owner of the data line and there are no S copies in the other nodes. 
     FIGS. 2A and 2B are flowcharts and FIG. 3 is a protocol table, illustrating how global data coherency between a shadow page in cache memory 114 and its corresponding home page in cache memory 124 is maintained, when requesting subsystem 110 needs to free the memory space currently occupied by the shadow page. Note that while the following example describes a flush operation on cache lines associated with a page cached in a higher-level cache, e.g., cache memory 114, the invention is applicable to other computer systems with non-COMA/NUMA architectures, such as a computer system with a COMA-only or any other type higher-level cache. 
     The following column definitions provide a guide to using the protocol table of FIG. 3. 
     Bus Trans specifies the transaction generated on the local interconnect. A Writestream to alternate LPA space have extra mnemonics added: prefetch shared (WS --  PS), prefetch modified (WS --  PM), fast write (WS --  FW) and flush (WS --  FLU). 
     Req. Node MTAG tells the MTAG state of the requested cache line, e.g. M (MODIFIED), O (OWNED), S (SHARED) or I (INVALID). Accesses to remote memory in NUMA mode have no valid MTAG and are denoted N (NUMA) in this column. 
     Request specifies what transactions are sent from the requester to the home agent. 
     State in Dir describes the D-state, which is the state in which the requesting node is (according to the home) when the home starts servicing the request, and the D-state, which is the requesting node&#39;s new state in the home. The symbol &#34;-&#34; indicates that no state change is necessary and the symbol &#34;*&#34; corresponds to all possible states. If the requester&#39;s state is not known, due to a limited directory representation, the D-state is here assumed to be I. State MODIFIED (M) is when the node is the owner and no sharers exists. 
     Demand specifies what demand transactions are sent from the home to the slaves. We distinguish between transactions to an owner and to a sharer. H --  INV transactions are not sent to the requesting node, but all other transactions are sent if the home node is also a slave. Each demand carries the value of the number of demands sent out by the home agent. 
     Reply specifies what reply transactions are received by the requester to the home. We distinguish between transactions from an owner, a sharer and from the home. Each reply carries the value of the number of demands sent out by the home agent. 
     FT Reissue specifies what local interconnect transactions to send after all replies have been received. The extensions to the transactions are explained in Table 11-1. This column also defines the new MTAG state, which is sent with the transaction. The symbol &#34;-&#34; indicates that no state change is performed. Note that this is the only way of changing the MTAG state. This is why sometimes &#34;dummy&#34; RS --  N/new --  state are used to change the MTAG state. Note also that reissued transactions use the &#34;normal&#34; GA or LPA space even if the original transaction was to an alternative space. e.g., WS --  PM. 
     Compl. describes the completion phase. It always involves a packet sent from the request agent back to the home agent. The completion may carry data. 
     Referring to both the table of FIG. 3 and the flowchart of FIG. 2A, one of several well-known algorithms can be used to select a suitable page for replacement (step 210). For example, the selection criteria may be a shadow page that has been least-recently used (LRU) or least frequently used. Note that home pages of subsystem 110 are normally preserved, i.e., they are treated preferentially with respect to shadow pages, since home pages are typically poor candidates for replacement. 
     Upon selection of a suitable shadow page for replacement, the selected page is demapped locally. In other words, local access to the selected page by processors 111a, 111b, . . . 111i is frozen while the selected shadow page is in the process of being &#34;flushed&#34; (step 220). Flushing restores coherency between shadow pages and home pages within system 100 whenever a shadow page is discarded. 
     In this implementation, since the higher-level cache, e.g., cache 114, maintains MTAGs (memory tags) reflecting the status of the shadow cache lines locally, e.g., in directory 116, these local MTAG entries associated with each shadow cache line of the selected shadow page can be scanned by processor 111a. If the status of one or more of the shadow cache lines is valid, e.g., having an &#34;O&#34; (owned) or an &#34;M&#34; (modified) state, these shadow cache line(s) are identified for flushing (step 230). (See row #1 of FIG. 3). Alternatively, the entire selected page, i.e., every cache line associated with the selected page, can be flushed without consulting the local MTAGs, regardless of the respective MTAG state. 
     FIG. 2B details step 240 for flushing the selected shadow page from cache memory 114 of requesting subsystem 110. The asynchronous flush operation of each valid shadow cache line is carried out in a two distinct asynchronous phases. For each valid cache line in the selected shadow page, a local flush instruction (WS --  FLU) which includes the address identifying the shadow cache line is sent to local global interface 115 of requesting subsystem 110 (step 241). In response to each local flush instruction, global interface 115 spawns a global flush instruction (R --  FLU) to home subsystem 120 (step 242). 
     FIG. 1B shows an exemplary scheme for encoding flush instructions which use different ranges of addresses so that the flush instructions can be easily distinguished from other instructions by local interconnect 119. See co-pending application &#34;A Multiprocessing System Configured to Perform Synchronization Operations&#34; by Hagersten et al., filed concurrently herewith. (Reference Number P1551) for the exemplary encoding scheme. 
     In accordance with the invention, by decoupling the local flush instructions from the global flush instructions, once processor 111a is done issuing a local flush instruction, processor 111a does not have to wait for a corresponding response from home subsystem 120. Instead, processor 111a is freed up quickly since there is no need to wait for an acknowledgment from home subsystem 120 over global interconnect 190. 
     Referring again to FIG. 2B, upon receipt of the global flush instruction from requesting subsystem 110, home subsystem 120 sends an appropriate &#34;acknowledgment&#34; message back to requesting subsystem (step 243). As discussed above and detailed in FIG. 3, the type of acknowledgment message depends on the status of the shadow cache line as recorded in home directory 126. 
     As shown in row #1 of FIG. 3, if the status of the shadow cache line is &#34;M&#34; or &#34;O&#34;, home subsystem 120 sends a &#34;H --  ACK&#34; acknowledge message to requesting subsystem 110 indicating that the content of the corresponding cache line in the home page needs to be updated, i.e., the cache line is &#34;dirty&#34;. Since requesting subsystem 110 has &#34;dirty&#34; data, home subsystem 120 has to &#34;pull&#34; the dirty data value from the replacing (previously requesting) subsystem 110. Sending the &#34;H --  ACK&#34; causes requesting subsystem 110 to &#34;reissue&#34; a read-to-own (RTO) transaction on its local interconnect 119 (step 244). Because &#34;dirty data can reside in either cache 114, L2$ 112a, or in both caches, the RTO transaction causes the retrieval of the dirty data from the appropriate cache within subsystem 110. The issuance of the RTO transaction on local interconnect 119 also has the effect of invalidating any shared copy within subsystem 110 and also updates the respective local MTAGs to the &#34;I&#34; state. 
     As shown in row #1 of FIG. 3, having retrieved the dirty data via local interconnect 119, requesting subsystem 110 can now send the dirty data appended to a &#34;completion message&#34;, e.g., a &#34;R --  CMP --  W&#34; completion message (step 245). Home subsystem 120 is now able to update its home copy of the data and also its home directory 126 by marking the corresponding entry in home directory 126 &#34;I&#34; (invalid) (step 246). Hence, the above described flush operation permits the &#34;M&#34; and &#34;O&#34; copies of the home page to migrate back to COMA cache memory 124 of home system 120 gracefully and efficiently. 
     Referring now to row #2 of FIG. 3, if the status of the shadow cache line is &#34;S&#34; (shared), home subsystem 120 sends a &#34;H --  NACK&#34; acknowledge message to requesting subsystem 110 indicating that the shadow cache line in the shadow page can be discarded and the corresponding MTAG associated with requesting directory 116 can be marked &#34;I&#34;. Accordingly, requesting subsystem 110 reissues an RTO transaction on local interconnect 119 thereby invalidating any shared copy within subsystem 110 and also updates the respective local MTAGs of subsystem 110 to the &#34;I&#34; state. A &#34;R --  CMP&#34; completion message, without any appended data, is sent to home subsystem 120. Home subsystem 120 updates the corresponding entry in home directory 126 by marking the shadow cache line as having an &#34;I&#34; (invalid) state. 
     Conversely, as depicted in row #3 of FIG. 3, if the status of the shadow cache line in home directory 126 is &#34;I&#34;, home subsystem 120 sends a &#34;H --  NOPE&#34; message to requesting subsystem 110. Subsequently, requesting subsystem 110 discards the shadow cache line and marks its corresponding local MTAG &#34;I&#34;. A &#34;R --  CMP&#34; completion message (without data) is sent to home subsystem 120. 
     As shown in row #4 of FIG. 3, if the local MTAG of requesting subsystem 110 shows the copy of data to be &#34;I&#34;, no further action is taken by both requesting subsystem 110 and home subsystem 120. 
     As discussed above, it is also possible for data to be cached in L2$ 113a but not in cache 114, for example, if data is cached solely in NUMA mode. Hence, in addition to gracefully migrating COMA copies (using a local physical address) to home subsystem 120, system 100 must be capable of gracefully migrating NUMA copies (using a global address) back to home subsystem 120. This can be accomplished by generating the appropriate NUMA and/or COMA flush instructions using the global and local flush address space (encoding) shown in FIG. 11B. 
     Referring to rows #5-7 of FIG. 3, since the issuance of an RTO transaction on local interconnect 119 causes all copies of the data to be retrieved, the steps taken by requesting subsystem 110 is similar to the above-described steps for flushing data stored in cache 114. In this implementation, the major difference being the MTAGs only record the status of data stored in cache 114 but does not reflect the status of data stored in L2$ 113a. Hence, when data stored in L2$ 112a is replaced, with the exception of updating the local MTAG of requesting subsystem 110, both requesting subsystem 110 and home subsystem 120 take similar actions described above and depicted in row #1-3 of FIG. 3. 
     Referring to step 250 of FIG. 2A, a confirmation of the completion of the flush operation can be implemented using a &#34;synchronization&#34; mechanism. One such confirmation verifies that all previously valid cache lines associated with a page have been successfully replaced with respect to their home location and the replaced cache lines are now marked &#34;invalid&#34;. An exemplary synchronization mechanism is described in co-pending application &#34;A Multiprocessing System Configured to Perform Synchronization Operations&#34; by Hagersten et al., filed concurrently herewith, (Reference Number P1551), and a description is also provided below. 
     Turning next to FIGS. 4 and 5, a block diagram of one embodiment of global interface 115 and a detailed block diagram of request agent 400 are shown, respectively. Additionally, SMP in queue 94, SMP PIQ 96, SMP out queue 92, and transaction filter 98 are shown. Transaction filter 98 is coupled to SMP bus 20, SMP in queue 94, SMP PIQ 96, and request agent 400. SMP out queue 92, SMP in queue 94, and SMP PIQ 96 are coupled to request agent 400 as well. 
     Each transaction presented upon SMP bus 20 for which ignore signal 70 is asserted is stored by global interface 115 for later reissue. As mentioned above, ignore signal 70 may be asserted if the access rights for the affected coherency unit do not allow the transaction to complete locally. Additionally, ignore signal 70 may be asserted if a prior transaction from the same subnode 50 is pending within global interface 115. Still further, ignore signal 70 may be asserted for other reasons (such as full in queues, etc.). 
     Request agent 400 comprises multiple independent control units 310A-310N. A control unit 310A-310N may initiate coherency activity (e.g. perform a coherency request) for a particular transaction from SMP in queue 94 or SMP PIQ 96, and may determine when the coherency activity completes via receiving replies. An initiation control unit 312 selects transactions from SMP in queue 94 and SMP PIQ 96 for service by a control unit 310A-310N. Any selection criteria may be employed as long as neither SMP in queue 94 nor SMP PIQ 96 are unconditionally prioritized higher than the other and as long as at least one control unit 310A-310N is not allocated to performing I/O operations. 
     In addition to selecting transactions for service by control units 310, initiation control unit 312 informs a second control unit 314 that a synchronization operation has been selected for initiation. A sync signal upon a sync line 316 coupled between initiation control unit 312 and control unit 314 is asserted when a synchronization operation is selected from either SMP in queue 94 or SMP PIQ 96. Control unit 314 manages a synchronization vector control register 318, and reissues the synchronization operation to SMP out queue 92 upon completion of the synchronization operation. 
     Upon receipt of an asserted sync signal upon sync line 316, control unit 314 causes control register 318 to record which control units 310 are currently performing coherency activities (i.e. those control units 310 which are not idle). In one embodiment, control register 318 includes multiple bits. Each bit corresponds to one of control units 310. If the bit is set, the corresponding control unit 310A-310N is performing coherency activity which was initiated prior to control unit 314 initiating a synchronization operation. If the bit is clear, the corresponding control unit 310A-310N is either idle or performing coherency activity which was initiated subsequent to control unit 314 initiating a synchronization operation. Each control unit 310 provides an idle line (e.g. idle line 322A from control unit 310A) to control register 318. When the idle signal upon an idle line 322 is asserted, the bit corresponding to the idle control unit 310 within control register 318 is cleared. 
     Control unit 314 monitors the state of control register 318. When each of the bits have been reset, each of control units 310 have been idle at least once. Therefore, coherency activity which was outstanding upon initiation of the synchronization operation has completed. Particularly, the transactions corresponding to the coherency activity have been globally performed. Therefore, the synchronization operation is complete. Control unit 314 reissues the synchronization operation to SMP out queue 92, and subsequently the reissue transaction completes within the SMP node. More particularly, the synchronization transaction is cleared from the initiating processor. The initiating processor may therefore determine when the synchronization operation has completed (by inserting a processor level synchronization subsequent to the synchronization operation, for example). Exemplary code sequences employing the synchronization operation are shown below. 
     In one embodiment, the synchronization operation is placed into SMP in queue 94 upon performance of the synchronization operation upon SMP bus 20 (similar to other transactions). Additionally, ignore signal 70 is asserted for the synchronization operation upon SMP bus 20. 
     It is noted that request agent 400 is configured to accept only one synchronization operation at a time in the present embodiment. Furthermore, two types of synchronization operations are defined: a coherent synchronization and I/O synchronization. Coherent synchronizations synchronize transactions placed in SMP in queue 94. Alternatively, I/O synchronizations synchronize I/O transactions (i.e. transactions placed in SMP PIQ 96). 
     Additionally, control units 310 may further employ a freeze state for use when errors are detected. If an error is detected for a transaction being serviced by a control unit 310, the control unit transitions to a freeze state and remains therein until released by a software update to a control register. In this manner, information regarding the transaction for which the error is detected (stored by the state machine) may be accessed to aid in determining the error. For purposes of allowing synchronization operations to complete, entering the freeze state is equivalent to entering the idle state. 
     Turning next to FIG. 6, a table 330 is shown listing exemplary asynchronous operations according to one embodiment of computer system 100. A column 332 lists the asynchronous transaction. A column 334 lists the encoding of the transaction upon SMP bus 20. Finally, a column 336 lists the synchronization operation which is used to synchronize the particular asynchronous operations. 
     The fast write stream asynchronous operation is employed to enhance the performance characteristics of writes to remote nodes. When a fast write stream operation is performed, system interface 115 allows the initiating processor to transfer the data thereto prior to performing coherency activities which may be required to obtain write permission to the affected coherency unit. In this manner, the processor resources consumed by the fast write stream operation may be freed more rapidly than otherwise achievable. As shown in column 334, the fast write stream operation is coded as a write stream having the five most significant bits of the address coded as shown. The &#34;nn&#34; identifies the home node of the address. The coherent synchronization operation (&#34;WS --  SC&#34;) is used to synchronize the fast write stream operation. 
     A second asynchronous operation employed in the exemplary embodiment is the flush operation. When a flush operation is detected by system interface 115, the affected coherency unit (if stored in the SMP node) is flushed. In other words, the coherency unit is stored back to the home node and the MTAG for the coherency unit is set to invalid. In the exemplary embodiment, the flush operation is coded as a write stream operation having the five most significant bits of the address coded as shown in column 334. The flush command uses a write stream encoding, although the data corresponding to the write stream is discarded. Similar to the fast write stream, system interface 115 allows the data to be transferred prior to global performance of the flush operation. The flush operation is synchronized using WS --  SC. 
     The synchronization operations in the exemplary embodiment are coded as write stream operations as well, although any encoding which conveys the synchronization command upon SMP bus 20 may be used. In particular for the exemplary embodiment, the WS --  SC operation is coded as a write stream operation for which the seven most significant address bits are coded as 0111100 (in binary). The WS --  SP operation is coded as a write stream operation for which the seven most significant address bits are coded as 0111101 (in binary). An alternative embodiment may employ a specially coded I/O read operation to perform synchronization. When the I/O read operation is detected, previously received transactions are completed prior to returning data for the I/O read operation. 
     Turning now to FIG. 7, an exemplary code sequence 340 is shown depicting use of synchronization operations. The example includes instructions from the SPARC microprocessor architecture. The order of operations in the program (the &#34;program order&#34;) is indicated by arrow 342. In the example, several fast write stream operations are performed (the &#34;WS --  FW&#34; operations shown in FIG. 7). Upon completion of a series of fast write stream operations, the code sequence includes a WS --  SC operation to synchronize the completion of the operations. Additionally, a MEMBAR instruction is included to guarantee completion of the WS --  SC operation prior to initiation of any memory operations subsequent to the MEMBAR instruction. 
     Generally, the WS --  SC operation is an example of a system level synchronization operation. The WS --  SC operation causes a synchronization to occur in the system interface 115 of the SMP node 12A-12D within which the WS --  SC operation is executed. In this manner, the node is synchronized. However, synchronizing the processor itself is performed using a processor level synchronization operation. The processor level synchronization operation does not synchronize the node, but does synchronize the processor 111a within which it is executed. By pairing a system level synchronization in the manner of FIG. 7, a complete synchronization of each level of the computer system may be achieved. 
     Various optimizations of the above described cache coherent mechanism are possible. For example, when flushing a shadow page, instead of flushing valid cache lines individually, the entire page may be flushed. Performance tradeoffs are also possible. For example, instead of flushing cache lines with a &#34;M&#34; or &#34;O&#34; state when a page is replaced, the entire page, i.e., every cache line may be flushed, simplifying the procedure at the expense of the network traffic. 
     Other modifications and additions are possible without departing from the spirit of the invention. For example, instead of blocking all read and write requests whenever a request is outstanding, read-to-share requests are blocked only if there is a read-to-own or a write-back request outstanding. In addition, each subsystem may be equipped with additional circuitry to perform &#34;local data forwarding&#34; so that processors within a subsystem can provide data to each other without accessing the host directory of another subsystem. Hence, the scope of the invention should be determined by the following claims.