Patent Publication Number: US-11043458-B2

Title: Method of manufacturing an electronic device comprising a conductive pad on a protruding-through electrode

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE 
     The present application is a CONTINUATION of U.S. patent application Ser. No. 15/953,024, filed Apr. 13, 2018, and titled “ELECTRONIC DEVICE COMPRISING A CONDUCTIVE PAD ON A PROTRUDING-THROUGH ELECTRODE,” expected to issue as U.S. Pat. No. 10,410,967; which is a CONTINUATION of U.S. patent application Ser. No. 15/250,397, filed Aug. 29, 2016, and titled “CONDUCTIVE PAD ON PROTRUDING THROUGH ELECTRODE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING,” now U.S. Pat. No. 9,947,623; which is a CONTINUATION of U.S. patent application Ser. No. 14/615,127, filed Feb. 5, 2015, and titled “CONDUCTIVE PAD ON PROTRUDING THROUGH ELECTRODE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING,” now U.S. Pat. No. 9,431,323; which is a CONTINUATION of U.S. patent application Ser. No. 14/017,797, filed Sep. 4, 2013, and titled “CONDUCTIVE PAD ON PROTRUDING THROUGH ELECTRODE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING,” now U.S. Pat. No. 8,981,572; which is a CONTINUATION of U.S. patent application Ser. No. 13/306,685, filed Nov. 29, 2011, and titled “CONDUCTIVE PAD ON PROTRUDING THROUGH ELECTRODE SEMICONDUCTOR DEVICE,” now U.S. Pat. No. 8,552,548. 
     The above-identified applications are hereby incorporated herein by reference in their entirety. 
    
    
     TECHNICAL FIELD 
     The present application relates to a semiconductor device and a method of manufacturing the semiconductor device. 
     BACKGROUND 
     In the information Technology (IT) industry, requirements for semiconductor devices have changed into small size and convenience in response to consumers&#39; demands, and thus semiconductor devices are being changed to be miniaturized and modularized. Such changes are contributive to developing techniques for manufacturing the devices and require innovative process techniques. 
     A representative example of the semiconductor devices is a System In Package (SIP) that satisfies the aforementioned changed requirements. Here, the SIP is manufactured by putting semiconductor dies having their respective functions into a single device or stacking devices to produce a module. 
     Of late, as a method of stacking identical or different semiconductor dies, which is the core technology of the SIP, a Through-Silicon-Vias (TSV) process of connecting semiconductor dies by forming through holes in silicon has been in development, rather than an existing wire connection method. Here, laser drilling, wet etching, dry etching and the like are known as a technique for forming through holes for the TSV process. However, the TSV process is relatively complex. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A and 1B  illustrate cross-sectional views of a semiconductor device according to various embodiments; 
         FIG. 2  illustrates a cross-sectional view of a semiconductor device according to another embodiment; 
         FIG. 3  illustrates a cross-sectional view of a semiconductor device according to another embodiment; 
         FIGS. 4A, 4R, 4C, 4D, and 4E  illustrate sequential cross-sectional views of a method of manufacturing a semiconductor device according to another embodiment; 
         FIG. 5  illustrates a cross-sectional view of a semiconductor device according to another embodiment; 
         FIG. 6  illustrates a cross-sectional view of a semiconductor device according to another embodiment; 
         FIG. 7  illustrates a cross-sectional view of a semiconductor device according to another embodiment; 
         FIGS. 8A, 8B, 8C, 8D, and 8F  illustrate sequential cross-sectional views of a method of manufacturing a semiconductor device according to another embodiment; 
         FIG. 9  illustrates a cross-sectional view of a semiconductor device according to another embodiment; 
         FIG. 10  illustrates a cross-sectional view of a semiconductor device according to another embodiment; 
         FIGS. 11A, 11B, 11C ,  11 D 1 ,  11 D 2 ,  11 E 1 , and  11 E 2  are sequential cross-sectional views of a method of manufacturing a semiconductor device according to another embodiment; and 
         FIG. 12  illustrates a cross-sectional view to show a state in which a semiconductor device is bonded to a carrier wafer with a temporary bonding adhesive for a plating process of a method of manufacturing a semiconductor device. 
     
    
    
     In the following description, the same or similar elements are labeled with the same or similar reference numbers. 
     DETAILED DESCRIPTION 
     Referring to  FIGS. 1A and 1B , cross-sectional views of a semiconductor device according to various embodiments are illustrated. 
     As shown in  FIG. 1A , a semiconductor device  101  includes a semiconductor die  110 , a through electrode  120 , a dielectric layer  130 , a conductive pad  140 , and a conductive bump  150 . 
     The semiconductor die  110  includes a substantially planar first surface  111 , a substantially planar second surface  112  opposing the first surface  111 . Also, the semiconductor die  110  further includes a through hole  113  penetrating the first surface  111  and the second surface  112 . Also, the semiconductor die  110  further includes an insulating layer  114  on the inner wall of the through hole  113 . 
     Furthermore, the semiconductor die  110  includes an active region  115  disposed on the second surface  112 , a bond pad  116  formed on the active region  115 , and another insulating layer  117  covering the circumference of the bond pad  116  and the active region  115 . The first surface  111  is sometimes called the inactive surface of the semiconductor die  110  whereas the second surface  112  is sometimes called the active surface of the semiconductor die  110 . 
     The insulating layer  114  serves to prevent the through electrode  120  from being electrically shorted to the semiconductor die  110 , and the outer insulating layer  117  provides appropriate protection for the active region  115  from external foreign substances. Those insulating layers  114  and  117  may be formed of any one selected from the group consisting of silicon oxide, silicon nitride, polymer and equivalents thereof. However, in other embodiments, the kinds of insulating layers  114  and  117  are not limited. 
     The through electrode  120  is provided inside the through hole  113 , that is, inside the insulating layer  114 . The through electrode  120  is substantially formed in the through hole  113 , and extends and protrudes upwardly to a predetermined length through and above the first surface  111 . Here, the through electrode  120  extending through and protruding above the first surface  111  includes a top surface  121  and both side surfaces  122 , and the top surface  121  is substantially planar. The exposed side surfaces  122  are sometimes called an exposed sidewall  122  of the through electrode  120 , i.e., the portion of the sidewall of the through electrode  120  exposed from the dielectric layer  130 . 
     The through electrode  120  may be formed of any one of copper, tungsten, aluminum, gold, silver, and equivalents thereof in general, but the materials of the through electrode  120  is not limited thereto. Furthermore, the through electrode  120  may further include a barrier or seed layer (not shown) disposed on the inner wall of the insulating layer  114 . 
     The dielectric layer  130  disposed on the first surface  111  of the semiconductor die  110  and has a predetermined thickness. Also, the dielectric layer  130  may have an opening  131  in a region corresponding to the through electrode  120 . This opening  131  may have an inclined sectional shape. That is, the opening  131  may have a relatively small lower region and a relatively wide upper region. 
     Of course, the through electrode  120  penetrates the opening  131 , and extends and protrudes upwardly to a predetermined length. In general, the length (or thickness) of the through electrode  120  extending and protruding upwardly from the first surface  111  of the semiconductor die  110  may be smaller than, equal to, or greater than the maximum thickness of the dielectric layer  130 . In other words, the maximum thickness of the dielectric layer  130  may be greater than, equal to, or smaller than the length (or thickness) of the through electrode  120  extending and protruding upwardly from the first surface  111  of the semiconductor die  110 . 
     Also, since the opening  131  is formed in part of the dielectric layer  130 , the first surface  111  of the semiconductor die  110  is not exposed through the opening  131 . That is, the opening  131  does not fully penetrate the dielectric layer  130  but is formed in part of the dielectric layer  130 . 
     Here, the dielectric layer  130  may be formed of at least one selected from the group consisting of Poly Benz Oxazole(PBO), PolyImide(PI), Benzo Cyclo Butene(BCB), BismalemideTriazine(BT), phenolic resin, epoxy, Silicone, Si3N4, SiO2, and equivalents thereof, but the material of the dielectric layer  130  is not limited thereto. Also, even though a single dielectric layer  130  is illustrated in the drawing, multiple dielectric layers  130  may be used. 
     The conductive pad  140  includes a first electroless plating layer  141 , a second electroless plating layer  142 , and a third electroless plating layer  143 . The first electroless plating layer  141  roughly surrounds the through electrode  120  inside the opening  131 . That is, the first electroless plating layer  141  surrounds the top surface  121  and both side surfaces  122  of the through electrode  120  exposed within the opening  131 . The second electroless plating layer  142  surrounds the first electroless plating layer  141 . Also, the third electroless plating layer  143  surrounds the second electroless plating layer  142 . Also, the lower ends of the first, second and third electroless plating layers  141 ,  142  and  143  may or may not contact the surface of the opening  131 . 
     The first electroless plating layer  141  may be formed of nickel or equivalents thereof in general, but the material of the first electroless plating layer  141  is not limited thereto. The second electroless plating layer  142  may be palladium or equivalents thereof, but the material of the second electroless plating layer  142  is not limited thereto. Furthermore, the third electroless plating layer  143  may be formed of gold or equivalents thereof, but the material of the third electroless plating layer  143  is not limited thereto. 
     Here, the third electroless plating layer  143  suppresses the oxidation of the through electrode  120 . Also, the first electroless plating layer  141  and the second electroless plating layer  142  suppress interaction between the through electrode  120  and the third electroless plating layer  143 . The second electroless plating layer  142  may not be formed in some cases. 
     In general, such a conductive pad  140  protrudes upwardly with a predetermined thickness or is exposed through the surface of the dielectric layer  130 . Thus, the conductive pad  140  serves to facilitate the stacking of a plurality of semiconductor devices  101 . 
     The conductive bump  150  is formed on the bond pad  116 , and extends downwardly from the second surface  112 . Here, the through electrode  1201 , the active region  115 , and the bond pad  116  may be electrically connected. 
     The conductive bump  150  has a diameter greater than the diameter of the through electrode  120 , thus allowing the conductive bump  150  to be stably mounted on an external device. Furthermore, the conductive bump  150  may come into contact with the insulating layer  117  by having a relatively great diameter. That is, the insulating layer  117  may be interposed between the bond pad  116  and the conductive bump  150 . 
     The conductive bump  150  may be formed of the same material as the through electrode  120 . Additionally, the conductive bump  150  may be formed of a material such as solder (SnPb, SnAg) or the like. Furthermore, in one embodiment, a solder cap  151  is formed on the conductive bump  150 , however, the solder cap  151  is not an essential element. Of course, in a case where there is a solder cap  151 , the semiconductor device  101  can be more easily mounted on an external device. 
     In such a manner, the semiconductor device  101  according to an embodiment has the conductive pad  140  formed by an electroless plating method, and thus seed metal is not required, and there is no need for a high-temperature sputtering process for the formation of seed metal. 
     As shown in  FIG. 1B , a semiconductor device  102  according to an embodiment includes another insulating layer  118  on the surface of the insulating layer  117 . Substantially, the insulating layer  118  also covers a predetermined region of the bond pad  116 . Furthermore, a predetermined region of the conductive bump  150  also contacts the insulating layer  118 . Thus, the insulating layers  117  and  118  may be interposed between the bond pad  116  and the conductive bump  150 . 
     The insulating layer  118  may be substantially formed of any one selected from the group consisting of Poly Benz Oxazole(PBO), PolyImide(PI), Benzo Cyclo Butene (BCB), BismaleimideTriazine(BT), phenolic resin, epoxy, Silicone, Si3N4, SiO2, and equivalents thereof, but the material of the insulating layer  118  is not limited thereto. 
     Accordingly, in the semiconductor device  102  according to this embodiment, the insulating layer  118  can efficiently absorb stress acting on the conductive bump  150 . Thus, cracking between the bond pad  116  and the conductive bump  150  is efficiently prevented. 
     Meanwhile, even though the insulating layer  118  is not described in the following embodiments, those of skill in the art will understand that the insulating layer  118  is applied to each embodiment in other examples. 
     Referring to  FIG. 2 , a cross-sectional view of a semiconductor device  201  according to another embodiment is illustrated. As shown in  FIG. 2 , the semiconductor device  201  according to another embodiment is similar to the semiconductor device  101  shown in  FIG. 1A , and thus only the significant differences will be described. 
     As shown in  FIG. 2 , a dielectric layer  230  does not having an opening, and instead, may have a slightly protruding projection  231 . That is, the through electrode  120  extends and protrudes upwardly to a predetermined length through the slight projection  231  rather than an opening. Accordingly, the thickness (or length) of the through electrode  120  substantially extending from the first surface  111  of the semiconductor die  110  may be slightly greater than the thickness of the dielectric layer  230 . 
     Furthermore, a conductive pad  240  is formed by an electroless plating method on the through electrode  120  extending and protruding upwardly to a predetermined length through the projection  231  of the dielectric layer  230 . That is, the conductive pad  240  includes a first electroless plating layer surrounding the top surface  121  and both side surfaces  122  of the through electrode  120  and disposed on the surface of the dielectric layer  230 , a second electroless plating layer covering the first electroless plating layer, and a third electroless plating layer covering the second electroless plating layer. 
     Here, the top surface of the conductive pad  240  has a substantially planar shape. The conductive pad  240  may or may not come into contact with the projection  231  of the dielectric layer  230 . Here, the first, second and third electroless plating layers are similar to the layers  141 ,  142 ,  143  as discussed above in reference to semiconductor device  101 , and thus a detailed description thereof is omitted. 
     Meanwhile, the semiconductor device  201  is manufactured by exposing the through electrode  120  by applying a blanket process to the dielectric layer  230 , and then applying a plating process to the top surface  121  and both side surfaces  122  of the exposed through electrode  120 . Here, the blanket process renders the dielectric layer  230  the thickest in a region (the projection  231 ) corresponding to the through electrode  120 , and gradually thinner as it is distanced from the through electrode  120 . 
     Thus, there is no need to form an opening in the dielectric layer  230  of the semiconductor device  201 , and this simplifies a manufacturing process. Here, the blanket process means wet or dry etching performed upon the entire top surface of the dielectric layer  230 . 
     Referring to  FIG. 3 , a cross-sectional view of a semiconductor device  301  according to another embodiment is illustrated. As shown in  FIG. 3 , the semiconductor device  301  according to another embodiment is similar to the semiconductor device  201  illustrated in  FIG. 2 , and thus only the significant differences will now be described. 
     As shown in  FIG. 3 , a dielectric layer  330  does not have an opening or a protrusion. That is, the top surface  332  of the dielectric layer  330  may be in the same plane as the top surface  121  of the through electrode  120 . Furthermore, a conductive pad  340  is formed on only the top surface  121  of the through electrode  120 . That is, the conductive pad  340  is not formed on the sidewall of the through electrode  120 , and thus the conductive pad  340  has a substantially planar shape. Here, the top surface  121  of the through electrode  120  has a substantially planar shape. 
     The semiconductor device  301  is manufactured by exposing the through electrode  120  through a chemical mechanical polishing (CMP) to the dielectric layer  330 , and applying a plating process to the top surface  121  of the exposed through electrode  120 . Here, by the CMP process, the top surface  121  of the through electrode  120  and the top surface  332  of the dielectric layer  330  are all in the same plane. 
     Referring to  FIGS. 4A through 4E , a method of manufacturing the semiconductor device  101  of  FIG. 1A  according to another embodiment is illustrated. The manufacturing method of the semiconductor device  101  according to another embodiment includes forming a through electrode, etching a semiconductor die, forming a dielectric layer, forming an opening, and forming a conductive pad. 
     As shown in  FIG. 4A , in the forming a through electrode, a through hole  113  is formed in a semiconductor die  110  having a first surface  111 A and a second surface  112  opposing the first surface  111 A, and an insulating layer  114  is formed on the inner wall of the through hole  113 . Thereafter, a through electrode  120  is formed inside the insulating layer  114 . 
     Here, the through hole  113  is formed by any one of laser drilling, wet etching, dry etching, or equivalent methods thereof, but the method for forming the through hole  113  is not limited thereto. However, the laser drilling, unlike wet etching or dry etching, does not require a mask manufacturing process, a photo-process or the like, and allows the length and width of the through hole  113  to be set relatively easily. 
     Furthermore, the insulating layer  114  may be formed of silicon oxide (SiOx) or silicon nitride (SiNx) by using a chemical vapor deposition (CVD) method or may be formed of a polymer by using a spin coating method or a sublimation method. However, the method for forming the insulating layer  114  is not limited to the described ones. 
     Furthermore, the through electrode  120  may be formed of any one selected from the group consisting of copper, tungsten, aluminum, gold, silver or equivalents thereof, but the material of the through electrode  120  is not limited thereto. 
     Substantially, before the through electrode  120  is formed, a barrier and/or seed layer (not shown) may be formed on the inner wall of the through hole  113  (i.e., the inner wall of the insulating layer  114 ). Furthermore, the through electrode  120  may be formed of an electroplating process or an electroless plating process. 
     Furthermore, a conductive bump  150  is formed on the bond pad  116 . Here, the conductive bump  150  has a greater diameter than that the through electrode  120 . In some cases, a solder cap  151  may be formed on the conductive bump  150 . 
     Also, the top surface  121  of the through electrode  120  may be formed to be in the same plane as the first surface  111 A of the semiconductor die  110 . Substantially, the first surface  111 A of the semiconductor die  110  may be formed through back-grinding such that the top surface  121  of the through electrode  120  is exposed externally through the first surface  111 A of the semiconductor die  110 . 
     Due to the back-grinding, the top surface  121  of the through electrode  120  is substantially planar. Furthermore, a region removed by the back-grinding is an inactive region other than an active region  115 , and the removal thereof does not have any influence on the operation of the semiconductor die  110 . Reference numeral  117  in the drawing indicates another insulating layer covering the active region  115  and the circumference of the bond pad  116 . 
     As shown in  FIG. 4B , in the etching of the semiconductor die, the first surface  111 A ( FIG. 4A ) of the semiconductor die  110  is removed to a predetermined depth by dry etching or wet etching to form the first surface  111  ( FIG. 4B ). Here, an etchant used in the dry etching or the wet etching affects only the semiconductor die  110  and the insulating layer  114 , and has no influence on the through electrode  120 . Accordingly, this etching provides a portion of the through electrode  120  extending and protruding upwardly to a predetermined length through the semiconductor die  110  and the insulating layer  114 . 
     As shown in  FIG. 4G , in the forming a dielectric layer, the first surface  111  of the semiconductor die  110  is coated with a dielectric layer  130  with a sufficient thickness to cover the through electrode  120 . The dielectric layer  130  is formed by, for example, a spin coating method, but the coating method of the dielectric layer  130  is not limited. Furthermore, the dielectric layer  130  may be formed of one selected from the group consisting of Poly Benz Oxazole(PBO), PolyImide(PI), Benzo Cyclo Butene(BCB), BismaleimideTriazine(BT), phenolic resin, epoxy, Silicone, and equivalents thereof, but the material of the dielectric layer  130  is not limited thereto. 
     As the dielectric layer  130  is formed in the above manner, the thickness of the dielectric layer  130  becomes greater than the length (or thickness) of the through electrode  120  extending and protruding from the first surface  111  of the semiconductor die  110 . 
     As shown in  FIG. 4D , in the forming an opening, the dielectric layer  130  is removed partially corresponding to the through electrode  120 , thus forming an opening  131  with a predetermined depth and width. For example, a mask is formed on a portion of the dielectric layer  130  not corresponding to the through electrode  120 , and is not formed on the other portion of the dielectric layer  130  which does corresponding to the through electrode  120 . 
     In this state, by partially removing the dielectric layer  130  using wet etching or dry etching, the opening  131  with a predetermined depth and width is formed. Here, the opening  131  has an inclined shape. That is, the opening  131  has a narrower lower region and is widened toward its upper region. Of course, the through electrode  120 , i.e., the exposed top surface  121  and both side surfaces  122 , is exposed to the outside through the opening  131 . 
     As shown in  FIG. 4E , in the forming a conductive pad, a conductive pad  140  is formed on the through electrode  120 , extending and protruding through the opening  131 , by an electroless plating method. The conductive pad  140  includes a first electroless plating layer  141 , a second electroplating layer  142 , and a third electroplating layer  143  as described above. 
     The first electroless plating layer  141  is formed to surround the through electrode  120 . Furthermore, the second electroless plating layer  142  roughly covers the first electroless plating layer  141 . Also, the third electroless plating layer  143  roughly covers the second electroless plating layer  142 . 
     Furthermore, the first electroless plating layer  141  may be formed of nickel or equivalents thereof. Also, the second electroless plating layer  142  may be formed of palladium or equivalents thereof. Furthermore, the third electroless plating layer  143  may be formed of gold or equivalents thereof. Here, the second electroless plating layer  142  may not be formed in some cases. 
     Since the conductive pad  140  is formed by an electroless plating method as described above, there is no need for seed metal, as well as a high-temperature sputtering process for the formation of seed metal. 
     In another embodiment, referring back to  FIGS. 2 and 4C  together, after the dielectric layer  130  ( FIG. 4C ) is formed, the entirety of the top surface of the dielectric layer  130  is dry- or wet-etched by using the blanket process to form the dielectric layer  230  ( FIG. 2 ), thus causing the through electrode  120  to protrude, and subsequently the conductive pad  240  is formed on the through electrode  120 . In such a manner, the semiconductor device  201  shown in  FIG. 2  is obtained through wet or dry etching. 
     In yet another embodiment, referring back to  FIGS. 3 and 4C  together, after the dielectric layer  130  ( FIG. 4C ) is formed, the entirety of the top surface of the dielectric layer  130  is subjected to grinding by using a CMP process to form the dielectric layer  330  ( FIG. 3 ), thus exposing the through electrode  120 , and subsequently, the conductive pad  340  is formed on the through electrode  120 . In such a manner, the semiconductor device  301  shown in  FIG. 3  is obtained. 
     Referring to  FIG. 5 , a cross-sectional view of a semiconductor device  401  according to another embodiment is illustrated. As shown in  FIG. 5 , the semiconductor device  401  according to another embodiment is similar to the semiconductor device  101  shown in  FIG. 1A , and thus only the significant differences will now be described. 
     An insulating layer  414  surrounding the through electrode  120  may extend not only between the first surface  111  and the second surface  112  of the semiconductor die  110  as in  FIG. 1A  but also to an opening  431  in a dielectric layer  430 . That is, the insulating layer  414  extends upwardly to a predetermined length through the first surface  111  of the semiconductor die  110 , and thus is interposed between the dielectric layer  430  and the through electrode  120 . In the above manner, the dielectric layer  430  contacts the insulating layer  414 , rather than the through electrode  120 . 
     Furthermore, a conductive pad  440  may be disposed on the through electrode  120  outside the insulating layer  414 . That is, the conductive pad  440  is formed on the top surface  121  and both side surfaces  122  of the through electrode  120  protruding through the insulating layer  414 , and the thickness of the conductive pad  440  may be almost similar to the thickness of the insulating layer  414 , but the thickness of the conductive pad  440  is not limited thereto. Here, the top surface  121  of the through electrode  120  is not planar but substantially curved. 
     In such a manner, according to this embodiment, the through electrode  120  does not come into direct contact with the dielectric layer  430 . That is, the insulating layer  414  is further interposed between the through electrode  120  and the dielectric layer  430 . Accordingly, insulating properties for the through electrode  120  are more enhanced. 
     Referring to  FIG. 6 , a cross-sectional view of a semiconductor device  501  according to another embodiment is illustrated. As shown in  FIG. 6 , the semiconductor device  501  according to this embodiment is similar to the semiconductor device  201  shown in  FIG. 2 , and thus only the significant differences will now be described. 
     An insulating layer  514  fully covers both side portions, i.e., the entire sidewall, of the through electrode  120 . That is, the insulating layer  514  is formed not only between the first surface  111  and the second surface  112  of the semiconductor die  110  but also between the through electrode  120  and a dielectric layer  530 . In other words, the entirety of the outer cylindrical sidewall other than the top surface  121  of the through electrode  120  is covered with the insulating layer  514 . Accordingly, the through electrode  120  and the dielectric layer  530  do not come into direct contact with each other. Also, the dielectric layer  530  formed around the insulating layer  514  may further include a projection  531  in a region corresponding to the through electrode  120 . 
     Also, a conductive pad  540  is formed on only the top surface  121  of the through electrode  120  exposed through the insulating layer  514 . Of course, as described above, the conductive pad  540  includes a first electroless plating layer, a second electroless plating layer, and a third electroless plating layer similar to the layers  141 ,  142 ,  143  described above. Here, the top surface  121  of the through electrode  120  is not planar but substantially curved. 
     The semiconductor device  501  is manufactured by applying a blanket process to the dielectric layer  530  to thus expose the through electrode  120 , and applying a plating process to the top surface  121  of the exposed through electrode  120 . Here, due to the blanket process, the dielectric layer  530  is the thickest in a region (the protrusion  531 ) corresponding to the through electrode  120 , and becomes thinner as it is distanced from the through electrode  120 . 
     Referring to  FIG. 7 , a cross-sectional view of a semiconductor device  601  according to another embodiment is illustrated. As shown in  FIG. 7 , the semiconductor device  601  according to another embodiment is similar to the semiconductor device  201  shown in  FIG. 2 , and thus only the significant differences will now be described. 
     An insulating layer  614  fully covers the entire sidewall of the through electrode  120 . Also, the respective top surfaces of the through electrode  120 , the insulating layer  614  and a dielectric layer  630  are in the same plane. Thus, the through electrode  120  and the dielectric  630  do not come into directly contact with each other. Also, a conductive pad  640  is formed on only the top surface  121  of the through electrode  120  exposed through the insulating layer  614 . 
     The semiconductor device  601  is manufactured by applying a CMP process to the dielectric layer  630  to thus expose the through electrode  120 , and applying a plating process to the top surface  121  of the exposed through electrode  120 . Here, due to the CMP process, the respective top surfaces  121  of the through electrode  120 , the insulating layer  614  and the dielectric layer  630  are in the same plane. That is, the top surface  121  of the through electrode  120  has a substantially planar shape. Of course, due to the aforementioned process, the dielectric layer  630  does not have any opening or protrusion. 
     Referring to  FIGS. 8A through 8E , a method of manufacturing the semiconductor device  401  of  FIG. 5  according to one embodiment is illustrated. The method of manufacturing the semiconductor device  401  according to another embodiment includes forming a through electrode, etching a semiconductor die, forming a dielectric layer, forming an opening, and forming a conductive pad. 
     As shown in  FIG. 8A , in the forming a through electrode, a through hole  113  is formed in a semiconductor die  110  having a first surface  111 A and a second surface  112  opposing the first surface  111 A, an insulating layer  414  is formed on the inner wall of the through hole  113 , and a through electrode  120  is then formed inside the insulating layer  414 . In this case, the insulating layer  414  surrounds the top surface  121  and the entire sidewall of the through electrode  120 . 
     As shown in  FIG. 8B , in the etching a semiconductor die, the first surface  111 A of the semiconductor die  110  ( FIG. 8A ) is removed to a predetermined depth by wet etching or dry etching to form a first surface  111  ( FIG. 8B ). Here, an etchant used for the dry etching or the wet etching affects only the semiconductor die  110  and does not affect the insulating layer  414 . By the etching process, the upper regions of the through electrode  120  and the insulating layer  414  extend and protrude upwardly to a predetermined length through the first surface  111  of the semiconductor die  110 . 
     As shown in  FIG. 8C , in the forming a dielectric layer, the first surface  111  of the semiconductor die  110  is coated with a dielectric layer  430  having a sufficient thickness to cover the insulating layer  414  formed on the surface of the through electrode  120 . 
     As shown in  FIG. 8D , in the forming an opening, a portion of the dielectric layer  430  corresponding to the through electrode  120  is removed to thus form an opening  431  having a predetermined depth and width. At this time, the insulating layer  414  formed on the through electrode  120  is also removed. That is, the insulating layer  414  formed in a region corresponding to the through electrode  120  exposed through the opening  431  is also removed. Accordingly, the through electrode  120  without the insulating layer  414  is exposed to the outside through the opening  431 . However, even in this state, the dielectric layer  430  is in contact with the in layer  414  without contacting the through electrode  120 . 
     As shown in  FIG. 8E , in the forming a conductive pad, a conductive pad  440  is formed on the through electrode  120  extending and protruding through the opening  431  by an electroless plating method. For example, a first electroless plating layer, a second electroless plating layer, and a third electroless plating layer as described above are sequentially formed to thus form the conductive pad  440 . Of course, due to the aforementioned process, the conductive pad  440  can come into contact with the insulating layer  414  and/or the dielectric layer  430 . 
     In another embodiment, referring back to  FIGS. 6 and 8C  together, after the dielectric layer  430  ( FIG. 8C ) is formed, the entirety of the top surface of the dielectric layer  430  and a portion of the insulating layer  414  are wet- or dry-etched by using a blanket process to form the dielectric layer  530  ( FIG. 6 ) to thus cause the through electrode  120  to protrude, and subsequently, the conductive pad  540  is formed on the through electrode  120 . In such a manner, the semiconductor device  501  shown in  FIG. 6  is obtained. 
     In another embodiment, referring back to  FIGS. 7 and 8C  together, after the dielectric layer  430  ( FIG. 8C ) is formed, the entirety of the top surface of the dielectric layer  430  and a portion of the insulating layer  414  are subjected to grinding by using a CMP process to form the dielectric layer  630  ( FIG. 7 ) to thus expose the through electrode  120 , and subsequently, the conductive pad  640  is formed on the through electrode  120 . In such a manner, the semiconductor device  601  shown in  FIG. 7  is obtained. 
     Referring to  FIG. 9 , a cross-sectional view of a semiconductor device  701  according to another embodiment is illustrated. As shown in  FIG. 9 , the semiconductor device  701  according to another embodiment is similar to the semiconductor device  101  shown in  FIG. 1A , and only the significant differences will now be described. 
     As shown in  FIG. 9 , a conductive pad  740  is formed on the through electrode  120  protruding and extending through an opening  731  of a dielectric layer  730 , and the conductive pad  740  contacts an insulating layer  714  surrounding the through electrode  120 . Accordingly, substantially, the dielectric layer  730  does not come into contact with the through electrode  120 , and contacts only the insulating layer  714  and the conductive pad  740 . Here, the top surface  121  of the through electrode  120  is roughly curved shape, which is not planar. 
     Referring to  FIG. 10 , a cross-sectional view of a semiconductor device  801  according to another embodiment is illustrated. As shown in  FIG. 10 , the semiconductor device  801  according to another embodiment is similar to the semiconductor device  201  shown in  FIG. 2 , and thus only the significant differences will now be described. 
     As shown in  FIG. 10 , the top surface  121  of the through electrode  120  is exposed through a dielectric layer  830 . That is, the top surface  121  of the through electrode  120  is exposed through a protrusion  831  of the dielectric layer  830 . Also, a conductive pad  840  is formed on the top surface  121  of the exposed through electrode  120 . Accordingly, the conductive pad  840  slightly protrudes through the dielectric layer  830 . Here, the top surface  121  of the through electrode  120  is not planar and has a substantially curved shape. 
     Referring to  FIGS. 11A, 11B, 11C ,  11 D 1 , and  11 E 1 , a method of manufacturing the semiconductor device  701  of  FIG. 9  according to another embodiment is illustrated. The manufacturing method of the semiconductor device  701  according to another embodiment includes forming a through electrode, etching a semiconductor die, forming a dielectric layer, forming an opening, and forming a conductive pad. 
     As shown in  FIG. 11A , in the forming a through electrode, a through hole  113  is formed in a semiconductor die  110  having a first surface  111 A and a second surface  112  opposing the first surface  111 A, an insulating layer  714  is formed on the inner wall of the through hole  113 , and a through electrode  120  is then formed inside the insulating layer  714 . At this time, the insulating layer  714  surrounds the top surface  121  and the entire sidewall of the through electrode  120 . 
     As shown in  FIG. 11B , in the etching a semiconductor die, the first surface  111 A of the semiconductor die  110  ( FIG. 11A ) is removed to a predetermined depth through wet etching or dry etching to form the first surface  111  as illustrated in  FIG. 11B . An etchant used in the dry etching or the wet etching affects only the semiconductor die  110  and the insulating layer  714 , and does not affect the through electrode  120 . Accordingly, due to this etching process, the upper region of the through electrode  120  extends and protrudes upwardly to a predetermined length through the first surface  111  of the semiconductor die  110 . 
     As shown in  FIG. 11C , in the forming a dielectric layer, the first surface  111  of the semiconductor die  110  is coated with a dielectric layer  730  having a sufficient thickness to cover the through electrode  120 . 
     As shown in FIG.  11 D 1 , in the forming an opening, a portion of the dielectric layer  730  corresponding to the through electrode  120  is removed to thus form an opening  731  extending entirely thorough the dielectric layer  730  to expose the insulating layer  714 . At this time, the through electrode  120  is exposed as well. 
     As shown in FIG.  11 E 1 , in the forming a conductive pad, a conductive pad  740  is formed on the through electrode  120  extending and protruding through the opening  731  by using an electroless plating method. The conductive pad  740  extends entirely through the dielectric layer  730  to contact the insulating layer  714 . Accordingly, substantially, the dielectric layer  730  does not come into contact with the through electrode  120 , and contacts only the insulating layer  714  and the conductive pad  740 . 
     FIGS.  11 D 2 ,  11 E 2  are cross-sectional views of the semiconductor device of  FIG. 11C  at later stages during fabrication in accordance with an alternative embodiment. As shown in FIG.  11 D 2 , in the forming an opening, a portion of the dielectric layer  730  corresponding to the through electrode  120  is removed to thus form an opening  731 . The opening  731  extends only partially, but not entirely, through the dielectric layer  730  such that, a portion of the dielectric layer  730  remains above the insulating layer  714 . At this time, the through electrode  120  is exposed as well. 
     As shown in FIG.  11 E 2 , in the forming a conductive pad, a conductive pad  740  is formed on the through electrode  120  extending and protruding through the opening  731  by using an electroless plating method. The conductive pad  740  extends partially, but not entirely, through the dielectric layer  730  to be space apart from the insulating layer  714 . Accordingly, substantially, a portion of the dielectric layer  730  does come into contact with the through electrode  120  between the insulating layer  714  and the conductive pad  740 . 
     In accordance with yet another embodiment, referring back to  FIGS. 10 and 11C , after the dielectric layer  730  ( FIG. 11C ) is formed, the entirety of the top surface of the dielectric layer  730  is wet or dry-etched by using a blanket process to form the dielectric layer  830  ( FIG. 10 ) to thus allow the through electrode  120  to protrude, and subsequently, the conductive pad  840  is formed on the through electrode  120 . In this manner, the semiconductor device  801  shown in  FIG. 10  is obtained. 
     In accordance with another embodiment, referring back to  FIGS. 3 and 11C  together, after the dielectric layer  730  ( FIG. 11C ) is formed, the entirety of the top surface of the dielectric layer  730  is subjected to grinding to form the dielectric layer  330  as illustrated in  FIG. 3  to thus expose the through electrode  120 , and subsequently, the conductive pad  340  is formed on the through electrode  120 . In this manner, the semiconductor device  301  shown in  FIG. 3  is obtained. 
     Referring to  FIG. 12 , a state in which the semiconductor device  101  of  FIG. 1A  is bonded to a carrier wafer  912  by a temporary bonding adhesive  911  for a plating process of a manufacturing method of the semiconductor device  101  according to an embodiment is illustrated. 
     As shown in  FIG. 12 , in the manufacturing process of the semiconductor device  101 , the semiconductor device  101  is bonded to a carrier wafer  912  by a temporary bonding adhesive  911 . That is, the conductive bump  150 , the solder cap  151 , the insulating layer  117  of the semiconductor device  101  are bonded to the carrier wafer  912  by the temporary bonding adhesive  911 . 
     Here, since the temporary bonding adhesive  911  has a low level of viscosity at a high-temperature process in general, the semiconductor device  101  is easily separated from the carrier wafer  912  in a high-temperature process. Furthermore, a gas generated from the temporary bonding adhesive  911  may cause cracking in the semiconductor device  101 . That is, the temporary bonding adhesive  911  is not suitable for a high-temperature process such as existing sputtering. 
     However, according to embodiments, a low temperature process such as plating is used rather than a high-temperature process such as sputtering, and thus the semiconductor device  101  is not easily separated from the carrier wafer  912  during a plating process. Also, the use of the low-temperature process does not cause gas generation from the temporary bonding adhesive  911 , and prevents cracking in the semiconductor device  101 . 
     Although specific embodiments were described herein, the scope of the invention is not limited to those specific embodiments. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of the invention is at least as broad as given by the following claims.