Patent Publication Number: US-2005135174-A1

Title: Power-up signal generator for semiconductor memory devices

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
      This is a divisional of application Ser. No. 10/255,999, filed on Sep. 26, 2002, now U.S. Pat. No. ______, which is incorporated herein by reference. 
    
    
     BACKGROUND  
      The present invention relates to power-up signal generators for semiconductor memory devices and, more particularly, to a power-up signal generator for generating a power-up signal that is disabled during a deep power down entry and enabled by an internal power supply voltage during a deep power down exit.  
      A deep power down entry designates a state in which all internal power supply voltages used inside a dynamic random access memory (DRAM) device are turned off to reduce a standby current drain when the DRAM device is not used for a period time. A power-up signal is a signal indicating that a DRAM device is able to operate normally. When the power-up signal is enabled at a high level, the DRAM device operates normally.  
       FIGS. 1 and 2  are circuit diagrams of power-up signal generators known in the prior art. The power-up signal generator includes a voltage divider  11  for dividing an external power supply voltage Vext, a pull-up unit  12  for pulling-up a divided voltage A, a driving unit  16  for receiving the divided voltage A to generate a power-up detection signal DET for determining the time that a power-up signal PWRUP is enabled, and a driving unit  15  for receiving the power-up detection signal DET to generate the power-up signal PWRUP. The driving unit  16  includes a pull-up unit  14  for pulling-up the power-up detection signal DET and a pull-down unit  13  for pulling-down the power-up detection signal DET.  
      The voltage divider  11  includes resistors R 1  and R 2  connected in series between the external power supply voltage Vext and a ground voltage Vss. The pull-up unit  12  includes a NMOS transistor N 1  that is connected between the external power supply voltage Vext and a node SN 1  and the divided voltage A is applied to its gate. The pull-down unit  13  includes an NMOS transistor N 2  connected between an output node SN 2  and the ground voltage Vss. The divided voltage A is applied to a gate of the NMOS transistor N 2 . The pull-up unit  14  includes a resistor R 3  connected between the external power supply voltage Vext and the output node SN 2 . The driving unit  15  includes an inverter IV 1  connected between the external power supply voltage Vext and the ground voltage Vss. The inverter IV 1  inverts the power-up detection signal DET to output the power-up signal PWRUP.  
      The construction of the power-up signal generator of  FIG. 2  is the same as that of the power-up signal generator of  FIG. 1 , except that a PMOS transistor P 1  is used in the pull-up unit  14  instead of the resistor R 3 . Accordingly, a detailed description of  FIG. 2  is omitted.  
      In the prior power-up signal generator, the power-up signal PWRUP is disabled at a low level until an internal power supply voltage, which is generated from the external power supply voltage Vext, reaches a stable level. The power-up signal PWRUP is enabled at a high level when the current flowing through the resistor R 3  ( FIG. 3 ) or the PMOS transistor P 1  ( FIG. 2 ) is larger than the current flowing through the NMOS transistor N 2 .  
      The power-up signal PWRUP is always enabled in a deep power down entry, as well as in a deep power down exit. The power-up signal PWRUP is always enabled because some semiconductor elements such as a clock buffer, or a mode register set, etc., should be in an operation state during the deep power down exit.  
      However, if the power-up signal PWRUP is enabled at a high level in a deep power down entry, the DRAM device operates in the state in which the internal power supply voltage is not generated. Accordingly, the semiconductor elements that operate by the internal power supply voltage will malfunction because the internal power supply voltage Vint is not provided thereto.  
     SUMMARY  
      It is an object of the present invention to prevent a malfunction in the deep power down entry by using a deep power down power-up signal which is always enabled for semiconductor elements which maintain at a stand by mode in the deep power down entry and using a power up signal which is disabled in the deep power down entry and enabled in a deep power down exit for semiconductor elements which operates after an internal power supply voltage is generated.  
      The disclosed apparatus may include a power-up detector for generating a power-up detection signal by means of an external power supply voltage; deep power down power-up signal generator for generating a deep power down power-up signal in response to the power-up detection signal, a power-up signal generator for generating a power-up signal in response to the power-up detection signal and power-up controller for determining whether or not enable the power-up signal in a deep power down entry.  
      In another aspect, the disclosed apparatus may include a power-up detector for generating a power-up detection signal by means of an external power supply voltage, a deep power down power-up signal generator for receiving the power-up detection signal to generate a deep power down power-up signal and a power-up controller for receiving the power-up detection signal and a deep power down mode signal to generate a power-up control signal. The disclosed apparatus may also include a power-up signal generator for generating a power-up signal that is enabled or disabled in response to the power-up control signal.  
      In another aspect, the disclosed apparatus may include a deep power down power-up signal generator for generating a deep power down power-up detection signal by means of an external power supply voltage, power-up signal generator for generating a power-up signal by the means of an internal power supply voltage and power-up controller for determining whether or not enable the power-up signal in a deep power down entry. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       FIGS. 1 and 2  are circuit diagrams of power-up signal generators according to the prior art;  
       FIGS. 3 and 4  are circuit diagrams of a first type of power-up signal generators;  
       FIGS. 5 and 6  are circuit diagrams of a second type of power-up signal generators;  
       FIGS. 7A  to  7 C are detailed circuit diagrams of power-up controllers of  FIGS. 5 and 6 ;  
       FIGS. 8 and 9  are circuit diagrams of a third type of power-up signal generators; and  
       FIG. 10  is a timing diagram of the power-up signal generator. 
    
    
     DETAILED DESCRIPTION  
      Turning now to  FIGS. 3 and 4 , the first type of power-up signal generators include a power-up detector  110 , a deep power down power-up signal generator  120 , a power-up signal generator  130  and a power-up controller  140 .  
      The power-up detector  110  includes a voltage divider  111  for dividing an external power supply voltage Vext, a pull-up unit  112  for pulling-up a divided voltage A and a driving unit  115  for receiving the divided voltage A to generate a power-up detection signal DET for determining an enable time of a deep power down power-up signal DPD-PWRUP and a power-up signal PWRUP. The driving unit  115  includes a pull-up unit  114  for pulling-up the power-up detection signal DET and a pull-down unit  113  for pulling-down the power-up detection signal DET.  
      The voltage divider  111  includes resistors R 11  and R 12  connected in series between the external power supply voltage Vext and a ground voltage Vss. The pull-up unit  112  includes an NMOS transistor N 11  connected between the external power supply voltage Vext and a node SN 11  and has the divided voltage A applied to its gate. The pull-down unit  113  includes a NMOS transistor N 12  connected between an output node SN 12  and the ground voltage Vss. The divided voltage A is applied to the gate of N 12 . The pull-up unit  114  includes a resistor R 13  connected between the external power supply voltage Vext and the output node SN 12 .  
      The power-up detector  110  outputs the power-up detection signal DET according to a current ratio of the resistor R 13  and the NMOS transistor N 12 . The power-up detection signal DET determines the time that the deep power down power-up signal DPD-PWRUP and the power-up signal PWRUP are enabled. That is, when the current flowing through the resistor R 13  (or the PMOS transistor P 12  of  FIG. 4 ) is larger than the current flowing through the NMOS transistor N 12 , the power-up detector  110  outputs the power-up detection signal DET of a low level to enable the deep power down power-up signal DPD-PWRUP and the power-up signal PWRUP at a high level.  
      The inverter IV 11  inverts the power-up detection signal DET. The deep power down power-up signal generator  120  includes inverters IV 12  and IV 13  connected between the external power supply voltage Vext and the ground voltage Vss. The inverters IV 12  and IV 13  invert an output signal of an inverter IV 11  to generate the deep power down power-up signal DPD-PWRUP.  
      The deep power down power-up signal generator  120  generates the deep power down power-up signal DPD-PWRUP, which is always enabled in the deep power down entry as well as the deep power down exit.  
      The power-up signal generator  130  includes inverters IV 14  and IV 15  connected between the internal power supply voltage Vint and the ground voltage Vss. The inverters IV 14  and IV 15  invert the output signal of the inverter IV 11  to generate the power-up signal PWRUP. The power-up signal generator  130  generates the power-up signal PWRUP, which is disabled at a low level in deep power down entry and enabled at a high level by the internal power supply voltage Vint in the deep power down exit.  
      The power-up controller  140  includes a PMOS transistor P 11  with its source connected to the external power supply voltage Vext. A deep power down mode signal DPD is applied to its gate. In the deep power down entry, the deep power down mode signal DPD is at a high level and, therefore, the power-up controller  140  is not enabled and does not provide the external power supply voltage Vext to the power-up signal generator  130 . In the deep power down exit, the deep power down mode signal DPD is at a low level and, therefore, the power-up controller  140  is enabled to provide the internal power supply voltage Vint from the external power supply voltage Vext. The internal power supply voltage Vint is, in turn, supplied to the power-up signal generator  130 .  
      The construction of the power-up signal generator of  FIG. 4  is substantially the same as that of the power-up signal generator in  FIG. 3  except that a PMOS transistor P 12  is used in the power-up detector  110  rather than the resistor R 13  of  FIG. 3 . Accordingly, a detailed description of  FIG. 4  is omitted.  
      Hereinafter, operation of the power-up signal generator of  FIGS. 3 and 4  is described in brief. First, the deep power down power-up signal DPD-PWRUP is used for a clock enable buffer, or a mode register set, etc., which should be in a standby state in the deep power down entry. The power-up signal PWRUP is used for an initialization of other semiconductor elements in a DRAM device by means of the internal power supply voltage.  
      When the current flowing through the resistor R 13  ( FIG. 3 ) or the PMOS transistor P 12  ( FIG. 4 ) is larger than the current flowing through the NMOS transistor N 12 , the power-up detection signal DET transitions to a low level. When the power-up detection signal DET transitions to a low state, the deep power down power-up signal DPD-PWRUP and a power-up signal PWRUP become enabled at high levels.  
      At this time, the deep power down power-up signal DPD-PWRUP is always enabled at a high level in the deep power down entry and the deep power down exit. On the other hand, the power-up signal PWRUP is disabled at a low level in the deep power down entry and is enabled at a high state by the internal power supply voltage Vint from the PMOS transistor P 11  in the deep power down exit.  
      In more detail, the deep power down mode signal DPD is at a high level in the deep power down power-up entry and, therefore, the PMOS transistor P 11  turns off. Because the external power supply voltage Vext is not provided to the inverters IV 14  and IV 15 , the power-up signal PWRUP is disabled at a low level. In the deep power down power-up exit, the deep power down mode signal DPD is at a low level and therefore the PMOS transistor P 11  turns on and the internal power supply voltage Vint is supplied from the external power supply voltage Vext. Because the internal power supply voltage is provided to the power-up signal generator  130 , the power-up signal PWRUP is enabled at a high level by the internal power supply voltage Vint.  
      According to the apparatuses shown in  FIGS. 3 and 4 , the deep power down power-up signal DPD-PWRUP is enabled at a high level in the deep power down entry and the deep power down exit. Apparatuses shown in  FIGS. 3 and 4  disable the power-up signal PWRUP at a low level in the deep power down entry and enable the power-up signal PWRUP at a high level in the deep power down exit. Therefore, the malfunction of the semiconductor chip device can be prevented in the deep power down entry.  
       FIG. 5  and  FIG. 6  are circuit diagrams of a second type of power-up signal generators. The power-up signal generators include a power-up detector  210 , a deep power down power-up signal generator  220 , a power-up controller  230 , and a power-up signal generator  240 .  
      The power-up detector  210  includes a voltage divider  211  for dividing an external power supply voltage Vext, a pull-up unit  212  for pulling-up a divided voltage A, and a driving unit  215  for receiving the divided voltage A to generate a power-up detection signal DET for determining an enable time of a deep power down power-up signal DPD-PWRUP and a power-up signal PWRUP. The driving unit  215  includes a pull-down unit  213  for pulling-down the power-up detection signal DET and a pull-up unit  214  for pulling-up the power-up detection signal DET.  
      The voltage divider  211  includes resistors R 21  and R 22  connected in series between the external power supply voltage Vext and a ground voltage Vss. The pull-up unit  212  includes a NMOS transistor N 21  with its source and its drain connected to the external power supply voltage Vext and a node SN 21 , respectively. The divided voltage A is applied to the gate of the NMOS transmitter N 21 . The pull-down unit  213  includes a NMOS transistor N 22  with its drain and its source are connected to an output node SN 22  and the ground voltage Vss respectively. The divided voltage A is applied to the gate of the NMOS transistor N 22 . The pull-up unit  214  includes a resistor R 23  connected between the external power supply voltage Vext and the output node SN 22 .  
      The power-up detector  210  outputs the power-up detection signal DET according to a current ratio of the resistor R 23  and the NMOS transistor N 22  and determines when the deep power down power-up signal DPD-PWRUP and the power-up signal PWRUP are enabled by the power-up detection signal DET. That is, when the current flowing through the resistor R 23  ( FIG. 5 ) or the PMOS transistor P 21  ( FIG. 6 ) is larger than the current flowing through the NMOS transistor N 22 , the power-up detector  210  outputs the power-up detection signal DET of a low level to enable the deep power down power-up signal DPD-PWRUP and the power-up signal PWRUP at high levels.  
      The deep power down power-up signal generator  220  includes inverters IV 21 , IV 22  and IV 23  connected between the external power supply voltage Vext and the ground voltage Vss. The inverters IV 21 -IV 23  invert the power-up detection signal DET to generate the deep power down power-up signal DPD-PWRUP.  
      The deep power down power-up signal generator  220  generates the deep power down power-up signal DPD-PWRUP, which is always enabled in the deep power down entry and the deep power down exit.  
      The power-up controller  230  receives the power-up detection signal DET and the deep power down mode signal DPD and generates a power-up control signal PWRUPZ for controlling whether to enable the power-up signal PWRUP.  
      The power-up controller  230  may have the construction as shown in any of  FIG. 7A  through  FIG. 7C .  
      The power-up controller  230 , as shown in  FIG. 7A  includes an inverter IV 27  connected between the external power supply voltage Vext and the ground voltage Vss. The inverter IV 27  inverts the power-up detection signal DET. An inverter IV 28  is also connected between the external power supply voltage Vext and the ground voltage Vss and inverts the deep power down mode signal DPD. A NAND gate ND 1  is connected between the external power supply voltage Vext and the ground voltage Vss and carries out NAND logic on the output signals of the inverters IV 27  and IV 28  to generate the power-up control signal PWRUPZ.  
      The power-up controller  230 , as shown in  FIG. 7B , includes a NOR gate NR 1 , connected between the external power supply voltage Vext and the ground voltage Vss, which carries out NOR logic on the power-up detection signal DET and the deep power down mode signal DPD. An inverter IV 29 , which is connected between the external power supply voltage Vext and the ground voltage Vss, inverts an output signal of the NOR gate NR 1  to generate the power-up control signal PWRUPZ.  
      The power-up controller  230 , as shown in  FIG. 7C , includes an inverter IV 30  that is connected between the external power supply voltage Vext and the ground voltage Vss and inverts the deep power down mode signal DPD. A PMOS transistor P 22  has its source and its drain connected to the external power supply voltage Vext and an output stage, respectively. An output signal of the inverter IV 30  is applied to the gate of the PMOS transistor P 22 . A transfer gate T 1  receives the power-up detection signal DET to generate the power-up control signal PWRUPZ under the control of the deep power down mode signal DPD and the output signal of the inverter IV 30 .  
      Returning to  FIG. 6 , the power-up signal generator  240  includes inverters IV 24 , IV 25  and IV 26 , each of which is connected between the external power supply voltage Vext and the ground voltage Vss. The inverters IV 24 -IV 26  invert the power-up control signal PWRUPZ to generate the power-up signal PWRUP. The power-up signal generator  240  generates the power-up signal PWRUP, which is disabled at a low level in the deep power down entry and is enabled at a high level in the deep power down exit.  
      The construction of the power-up signal generator of  FIG. 6  is the substantially same as that of the power-up signal generator of  FIG. 5 , except that a PMOS transistor P 21  is used in the power-up detector  210  instead of the resistor R 23 . Accordingly, a detailed description of  FIG. 6  is omitted.  
      Hereinafter, an operation of the second type of power-up signal generators is described in brief.  
      The deep power down power-up signal DPD-PWRUP is always enabled at a high level in the deep power down entry and the deep power down exit. On the other hand, the power-up signal PWRUP is disabled at a low level in the deep power down entry and is enabled at a high state in the deep power down exit.  
      In more detail, the deep power down mode signal DPD is at a high level in the deep power down entry and therefore the power-up control signal PWRUPZ transitions to a high level and the power-up signal PWRUP becomes disabled at a low level. In the deep power down exit, the deep power down mode signal DPD is at a low level and the power-up control signal PWRUPZ transitions to a low level and the power-up signal PWRUP becomes enabled at a high level.  
      The second type of power-up signal generators enable the deep power down power-up signal DPD-PWRUP at a high level in the deep power down entry and the deep power down exit. According to the power-up control signal PWRUPZ, the power-up signal PWRUP is disabled at a low level in the deep power down entry power-up signal PWRUP is enabled at a high level in the deep power down exit. Therefore, the malfunction of the semiconductor chip device can be prevented in the deep power down entry.  
      Next, power-up signal generators of a third type are described in more detail with reference to the accompanying  FIGS. 8 and 9 .  
       FIGS. 8 and 9  are circuit diagrams of the power-up signal generators of the third type. The power-up signal generators include a deep power down power-up signal generator  310 , a power-up signal generator  320 , and a power-up controller  330 .  
      The deep power down power-up signal generator  310  includes a voltage divider  311  for dividing an external power supply voltage Vext, a pull-up unit  312  for pulling-up a divided voltage A, and a driving unit  315  for receiving the divided voltage A to generate a power-up detection signal DET and a driving unit  316  for receiving the power-up detection signal DET to generate a deep power down power-up signal DPD-PWRUP. The driving unit  315  includes a pull-up unit  314  for pulling-up the power-up detection signal DET and a pull-down unit  313  for pulling-down the power-up detection signal DET.  
      The voltage divider  311  includes resistors R 31  and R 32  connected in series between the external power supply voltage Vext and a ground voltage Vss. The pull-up unit  312  includes a NMOS transistor N 31  with its source and its drain connected to the external power supply voltage Vext and a node SN 31 , respectively. The divided voltage A is applied to the gate of the NMOS transistor N 31 . The pull-down unit  313  includes a NMOS transistor N 32  with its drain and its source connected to an output node SN 32  and the ground voltage Vss, respectively. The divided voltage A is applied to the gate of the NMOS transistor N 32 . The pull-up unit  314  includes a resistor R 33  connected between the external power supply voltage Vext and the output node SN 32 . The driving unit  316  includes inverters IV 31 , IV 32  and IV 33  connected between the external power supply voltage Vext and the ground voltage. The inverters IV 31 -IV 33  invert the power-up detection signal DET to generate the deep power down power-up signal DPD-PWRUP.  
      The deep power down power-up signal generator  310  generates the deep power down power-up signal DPD-PWRUP, which is always enabled in the deep power down entry and the deep power down exit.  
      The power-up signal generator  320  includes a voltage divider  331  for dividing an internal power supply voltage Vint, a pull-up unit  332  for pulling-up a divided voltage A, a driving unit  335  for receiving the divided voltage A to generate a power-up detection signal DET, and a driving unit  336  for receiving the power-up detection signal DET to generate a power-up signal PWRUP. The driving unit  335  includes a pull-up unit  334  for pulling-up the power-up detection signal DET and a pull-down unit  333  for pulling-down the power-up detection signal DET.  
      The voltage divider  331  includes resistors R 34  and R 35  connected in series between the internal voltage Vint and the ground voltage Vss. The pull-up unit  332  includes a NMOS transistor N 33  connected between the internal power supply voltage Vint and a node SN 33 . The divided voltage A is applied to the gate of NMOS transistor N 33 . The pull-down unit  333  includes a NMOS transistor N 34  with its drain and its source connected to an output node SN 34  and the ground voltage Vss respectively. The divided voltage A is applied to the gate of the NMOS transistor N 34 . The pull-up unit  334  includes a resistor R 36  connected between the internal power supply voltage Vint and the output node SN 34 . The driving unit  336  includes inverters IV 34 , IV 35  and IV 36  connected between the internal power supply voltage Vint and the ground voltage Vss. The inverters IV 34 -IV 36  invert the power-up detection signal DET to generate the power-up signal PWRUP.  
      The power-up signal generator  320  generates the power-up signal PWRUP, which is disabled at a low level in the deep power down entry and enabled at a high level in the deep power down exit.  
      The power-up controller  330  includes a PMOS transistor P 31  with its source connected to the external power supply voltage. The deep power down mode signal DPD is applied to the gate of the PMOS transistor P 31 .  
      In the deep power down entry, the deep power down mode signal DPD is at a high level, and the power-up controller  330  having the above construction turns off the PMOS transistor P 31  and, therefore, does not provide the external power supply voltage Vext. In the deep power down exit, the deep power down mode signal DPD is at a low level, which enables the PMOS transistor P 31  and generates the internal power supply voltage Vint from the external power supply voltage Vext and provides the internal power supply voltage Vint to the power-up signal generator  320 .  
      The construction of the power-up signal generator of  FIG. 9  is substantially the same as that of the power-up signal generator of  FIG. 8  except that PMOS transistors P 32  and P 33  are used in the deep power down power-up signal generator  310  and the power-up signal generator  320  instead of the resistors R 33  and R 36 . Accordingly, a detailed description of  FIG. 9  is omitted.  
      Hereinafter, operation of the third type of power-up signal generators is described in brief.  
      The deep power down power-up signal DPD-PWRUP is always enabled at a high level in the deep power down entry and the deep power down exit. On the other hand, the power-up signal PWRUP is disabled at a low level in the deep power down entry and is enabled at a high level in the deep power down exit.  
      In more detail, the deep power down mode signal DPD is at a high level in the deep power down entry and, therefore, the PMOS transistor P 31  turns off. The external power supply voltage Vext is not provided and the power-up signal PWRUP becomes disabled at a low level. In the deep power down exit, the deep power down mode signal DPD is at a low level and the PMOS transistor P 31  turns on. The internal power supply voltage Vint, which is made from the external power supply voltage Vext, is provided to the power-up signal generator  320  and the power-up signal PWRUP is enabled at a high level by the internal power supply voltage Vint.  
      The third type of power-up signal generators enable the deep power down power-up signal DPD-PWRUP at a high level in the deep power down entry as well as the deep power down exit. The third type of power-up signal generators disables the power-up signal PWRUP at a low level in the deep power down entry and enables the power-up signal PWRUP at a high level in the deep power down exit. Therefore, the malfunction of the semiconductor chip device can be prevented in the deep power down entry.  
       FIG. 10  is an operation waveform of the deep power down power-up signal DPD-PWRUP and the power-up signal PWRUP according to the deep power down mode signal DPD. Referring to  FIG. 10 , the deep power down power-up signal DPD-PWRUP is continuously enabled at a high level. The power-up signal PWRUP is disabled at a low level in the deep power down entry and, therefore, the internal power supply voltage is not provided.  
      The disclosed apparatus uses a deep power down power-up signal that is always enabled for semiconductor elements that maintain at a standby mode in the deep power down entry. The disclosed apparatus also uses a power-up signal that is disabled in the deep power down entry and enabled in a deep power down exit for semiconductor elements that operate after an internal power supply voltage is generated, thereby preventing malfunction of the semiconductor elements during the deep power down entry.  
      The disclosed apparatus generates the deep power down power-up signal that is always enabled at a high level in the deep power down entry and the deep power down exit. The power-up signal is disabled at a low level in the deep power down entry and is enabled at a high level in the deep power down exit to drive a DRAM device. Accordingly, a malfunction of a semiconductor chip device in the deep power down entry is prevented. Therefore, the chip has stable operation, thereby improving the reliability of the chip.  
      Although certain apparatus constructed in accordance with the teachings of the invention have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all embodiments of the teachings of the invention fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.