Patent Publication Number: US-8120037-B2

Title: System for displaying images

Description:
This Application claims priority of Taiwan Patent Application No. 097105863, filed on Feb. 20, 2008, the entirety of which is incorporated by reference herein. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a light emitting display technology, and in particular to a self-emitting display device for a system for displaying images capable of suppressing threshold voltage shift while preventing reduction of aperture ratio and a method for fabricating the same. 
     2. Description of the Related Art 
     Recently, with the development and wide application of electronic products such as mobile phones, PDAs, and notebook computers, there has been increasing demand for flat panel displays (FPDs) which consume less electric power and occupy less space. Organic electroluminescent/light-emitting devices (OELDs/OLEDs) are self-emitting and highly luminous, with a wider viewing angle, a faster response speed, and a simple fabrication process, making them an industry display of choice. 
     The current trend in FPD technology is for development of an organic electroluminescent display with higher luminescent efficiency and longer operating lifespan. Accordingly, an active matrix (AM) organic electroluminescent device with thin film transistors has been developed. 
     An AMOLED typically employs polysilicon (poly-Si) or amorphous silicon (α-Si) as an active layer for a thin film transistor (TFT). However, electrons for such an active layer, may be trapped in the gate dielectric layer during device operation, resulting in threshold voltage (V th ) shift. The luminance of OLEDs depends on injection current (I d ). Thus, increased threshold voltage may result in reduced injection current, which negatively impacts the OLED. 
     BRIEF SUMMARY OF THE INVENTION 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. A system for displaying images is provided. An embodiment of a system for displaying images comprises a self-emitting display device comprising an array substrate comprising a pixel region. A light-emitting diode is disposed on the array substrate of the pixel region. First and second driving thin film transistors are electrically connected to a light-emitting diode. The first driving thin film transistor comprises a first gate and an active layer stacked on the array substrate of the pixel region and the second driving thin film transistor comprises the active layer and a second gate thereon. The first gate is coupled to a first voltage and the second gate is coupled to a second voltage different from the first voltage during the same frame. 
     Another embodiment of a system for displaying images comprises a self-emitting display device comprising an array substrate comprising a pixel region. A light-emitting diode is disposed on the array substrate of the pixel region. First and second driving thin film transistors are electrically connected to a light-emitting diode. The first driving thin film transistor comprises a first gate and an active layer stacked on the array substrate of the pixel region and the second driving thin film transistor comprises the active layer and a second gate thereon. A first storage capacitor comprises a first electrode and a second electrode stacked on the array substrate of the pixel region, in which the first electrode is electrically connected to the first gate. A second storage capacitor comprises the second electrode and a third electrode thereon, in which the third electrode is electrically connected to the second gate. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIGS. 1A to 1G  are cross sections of an embodiment of a method for fabricating a system for displaying images incorporating a self-emitting display device. 
         FIG. 2  shows an equivalent circuit shown in  FIG. 1G . 
         FIGS. 3A to 3B  and  3 B- 1  are cross sections of the operation of driving thin film transistors in the self-emitting display device shown in  FIG. 1G . 
         FIG. 4  schematically shows another embodiment of a system for displaying images. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
     Systems for displaying images and fabrication methods for the same are provided. Referring to  FIGS. 1G and 2 , in which  FIG. 1G  illustrates an exemplary embodiment of such a system, and  FIG. 2  shows a relationship of the electrical connection (or an equivalent circuit) of a structure shown in  FIG. 1G . Specifically, the system incorporates a self-emitting display device  300 , such as an organic light-emitting device, comprising a lower substrate (hereinafter referring to as array substrate)  100  and an upper substrate (not shown) opposite thereto. The array substrate  100  and the upper substrate may comprise a transparent material, such as glass, quartz or the like. The array substrate  100  typically comprises a plurality of pixel regions defined by a plurality of scan lines and a plurality of data lines. Here, in order to simplify the diagram, only a pixel region P is depicted. 
     Moreover, a light-emitting diode D (not shown), first and second driving thin film transistors DT 1  and DT 2 , and first and second storage capacitors C 1  and C 2  are disposed on the pixel region P of the array substrate  100 . The first driving thin film transistor DT 1  may be N or P-type. In the embodiment, an example of an N-type thin film transistor (NTFT) is described. The first driving thin film transistor DT 1  comprises a gate  104   a , an insulating layer (serving as a gate dielectric layer)  106 , an active layer  108  having source/drain regions  108   a  and lightly doped drain (LDD) regions  108   c , and a source/drain  120  electrically connected to the source/drain regions  108   a . The gate  104   a  and the active layer  108  are successively disposed on the pixel region P of the array substrate  100 . The second driving thin film transistor DT 2  may be N or P-type. In the embodiment, an example of an NTFT is described. The second driving thin film transistor DT 2  comprises a gate  114   a , an insulating layer (serving as a gate dielectric layer)  112 , the active layer  108 , and the source/drain  120 . The gate  114   a  is disposed on the active layer  108  and substantially aligns the gate  104   a . In the embodiment, a common active layer  108  and a common source/drain  120  are common to first and second driving thin film transistors DT 1  and DT 2   
     The first storage capacitor C 1  comprises two electrodes  104   b  and  108   b  and an insulating layer (serving as a capacitor dielectric)  106  therebetween. The electrodes  104   b  and  108   b  are successively disposed on the pixel region P of the array substrate  100 . The second capacitor C 2  comprises two electrodes  108   b  and  114   b  and an insulating layer (serving as a capacitor dielectric)  112  therebetween. The electrode  114   b  is disposed on the electrode  108   b  and substantially aligns the electrode  104   b . In the embodiment, a electrode  108   b  is common to the first and second storage capacitor C 1  and C 2 . Moreover, the electrode  108   b  is extended from the active layer  108 . That is, a material layer, such as a polysilicon (poly-Si) or amorphous silicon (α-Si) layer, is defined to form the active layer  108  and the electrode  108   b.    
     Referring to  FIG. 2 , the input terminals of first and second driving thin film transistors DT 1  and DT 2  are electrically connected to the electrode (i.e. the electrode  108   b ) of the first and second storage capacitors C 1  and C 2  and coupled to a voltage source V dd . Moreover, the output terminals of first and second driving thin film transistors DT 1  and DT 2  are electrically connected to the light-emitting diode D, which is coupled to a voltage source V ss  lower than the voltage source V dd . The control terminal (i.e. the gate  104   a ) of the first driving thin film transistor DT 1  is electrically connected to another electrode (i.e. the electrode  104   b ) of the first storage capacitor C 1  and the control terminal (i.e. the gate  114   a ) of the second driving thin film transistor DT 2  is electrically connected to another electrode (i.e. the electrode  114   b ) of the second storage capacitor C 2 . 
     In the embodiment, when the self-emitting display device  300  is being operated, the gate  104   a  of the first driving thin film transistor DT 1  is coupled to a voltage V 1  and the gate  114   a  of the second driving thin film transistor DT 2  is coupled to a voltage V 2  during the same frame, in which the voltages V 1  and V 2  have the same level and opposing polarities. 
     Referring to  FIGS. 3A to 3B  and  3 B- 1 , which are cross sections of the operation of driving thin film transistors DT 1  and DT 2  in the self-emitting display device  300  shown in  FIG. 1G . As shown in  FIG. 3A , the gate  104   a  of the first driving thin film transistor DT 1  is coupled to a voltage V 1  having a negative polarity and the gate  114   a  of the second driving thin film transistor DT 2  is coupled to a voltage V 2  having a positive polarity during one frame. Accordingly, the direction of the electric field E is downward, as indicated by the arrow, and the light-emitting diode D is driven by the second driving thin film transistor DT 2 . As a result, the electrons e in the active layer  108  are trapped in the gate dielectric layer  112  of the second driving thin film transistor DT 2 , such that the threshold voltage of the second driving thin film transistor DT 2  may be shifted during the next driving period. Accordingly, as shown in  FIG. 3B , during the next frame, the polarity of the voltage V 1  is transformed to positive and the polarity of the voltage V 2  is transformed to negative, such that the direction of the electric field E is upward, as indicated by the arrow, and the light-emitting diode D is driven by the first driving thin film transistor DT 1 . As a result, the electrons e trapped in the gate dielectric layer  112  flow back to the active layer  108 , preventing the threshold voltage of the second driving thin film transistor DT 2  from shifting during the next driving period. 
     As shown in  FIG. 3B-1 , the electrons e in the active layer  108  are trapped in the gate dielectric layer  106  of the first driving thin film transistor DT 1 , such that the threshold voltage of the first driving thin film transistor DT 1  may be shifted during the next driving, during the next frame. However, the polarity of the voltage V 1  can be transformed to negative and the polarity of the voltage V 2  can be transformed to positive during the next frame, such that the direction of the electric field E is downward (i.e. the light-emitting diode D is driven by the second driving thin film transistor DT 2 ). As a result, the electrons e trapped in the gate dielectric layer  106  flow back to the active layer  108 , preventing the threshold voltage of the first driving thin film transistor DT 1  from shifting during the next driving period. In another embodiment, the voltages V 1  and V 2  have the same polarity and different levels and can use the similar method to prevent threshold voltage shift. 
     Referring to  FIGS. 1A to 1G , which illustrate an embodiment of a method for fabricating a system for displaying images incorporating a self-emitting display device. As shown in  FIG. 1A , an array substrate  100  comprising a pixel region P is provided. The substrate  100  may comprise glass or quartz. A buffer layer  102  and a conductive layer  104  are successively formed on the array substrate  100 . The buffer layer  102  may be a single layer, such as a silicon oxide or nitride layer. The buffer layer  102  may also be multiple layers comprising a silicon oxide and a silicon nitride. The conductive layer  104  may comprise metal, such as Al, Ag, Mo, AlNd, or a combination thereof. The conductive layer  104  can be formed by a conventional deposition process, such as sputtering. 
     As shown in  FIG. 1B , the conductive layer  104  is patterned by a conventional lithography and etching process, to form a gate  104   a  for a driving thin film transistor and an electrode  104   b  for a storage capacitor in the pixel region P. Thereafter, an insulating layer  106  and a semiconductor layer  107  are successively formed on the buffer layer  102  and cover the gate  104   a  and the electrode  104   b.  The portion of the insulating layer  106  covering the gate  104   a  serves as a gate dielectric layer and the portion of the insulating layer  106  covering the electrode  104   b  serves as a capacitor dielectric layer. The insulating layer  106  may be a single layer, such as a silicon oxide or nitride layer. The insulating layer  106  may also be multiple layers comprising a silicon oxide and a silicon nitride. The semiconductor layer  107  may comprise a polysilicon (poly-Si) or amorphous silicon (α-Si) layer. 
     As shown in  FIG. 1B and 1C , a photoresist patterned layer  110  is formed on the semiconductor layer  107  above the gate  104   a . Ion implantation  111  is performed on the semiconductor layer  107  using the photoresist patterned layer  110  as an implant mask, to form the active layer  108  with source/drain regions  108   a  on the insulating layer  106  above the gate  104   a  and form an electrode  108   b  on the insulating layer  106  above the electrode  104   b , in which a first storage capacitor C 1  is composed of the electrodes  104   b  and  108   b  and the insulating layer  106 . 
     As shown in  FIG. 1D , after removing the photoresist patterned layer  110 , an insulating layer  112  and a conductive layer  114  are successively formed on the active layer  108  and the electrode  108   b , which is extended from the active layer  108 . The insulating layer  112  may be a single layer, such as a silicon oxide or nitride layer. The insulating layer  112  may also be multiple layers comprising a silicon oxide and a silicon nitride. The conductive layer  114  may comprise metal, such as Al, Ag, Mo, AlNd, or a combination thereof. The conductive layer  114  can be formed by a conventional deposition process, such as sputtering. The portion of the insulating layer  112  covering the active layer  108  serves as a gate dielectric and the portion of the insulating layer  112  covering the electrode  108   b  serves as a capacitor dielectric. 
     As shown in  FIG. 1E , the conductive layer  114  is patterned by a conventional lithography and etching process, to form a gate  114   a  on the insulating layer  112  above the active layer  108  and an electrode  114   b  on the insulating layer  112  above the electrode  108   b , in which the gate  114   a  substantially aligns the gate  104   a  and the electrode  114   b  substantially aligns the electrode  104   b . A second storage capacitor C 2  is composed of the electrodes  108   b  and  114   b  and the insulating layer  112 . Light ion implantation  115  is performed on the active layer  108  using the gate  114   a  as an implant mask, to form lightly doped drain (LDD) regions  108   c  therein and adjacent to the source/drain region  108   a.    
     As shown in  FIG. 1F , an interlayer dielectric (ILD) layer  116  and a planarization or protective layer  118  are successively formed on the insulating layer  112  and cover the gate  114   a  and the electrode  114   b . Thereafter, the planarization layer  118 , the ILD layer  116 , and the insulating layer  112  are successively etched to form via holes  119  therein to expose the source/drain regions  108   a.    
     As shown in  FIG. 1G , a conductive layer  120  fills the via holes  119  to electrically connect to the source/drain regions  108   a . The conductive layer  120  may comprise metal, such as Al, Ag, Mo, AlNd, or a combination thereof, and serve as source/drain for a thin film transistor. In the embodiment, a first driving thin film transistor DT 1  is composed of the gate  104   a , the insulating layer  106 , the active layer  108 , and the source/drain  120 , and a second driving thin film transistor DT 2  is composed of the gate  114   a , the insulating layer  112 , the active layer  108 , and the source/drain  120 . 
     According to the embodiment, the light-emitting diode D is alternately driven by the first and second driving thin film transistors DT 1  and DT 2 . Moreover, the electrons e are back to the active layer  108  by the driving thin film transistor that does not drive the light-emitting diode D. Accordingly, threshold voltage shift can be prevented. Moreover, since the second driving thin film transistor DT 2  and the second storage capacitor C 2  respectively stack on the first driving thin film transistor DT 1  and the first storage capacitor C 1 , the aperture ratio of the pixel region P is not reduced while increasing the number of the driving thin film transistor and the storage capacitor. 
       FIG. 4  schematically shows another embodiment of a system for displaying images which, in this case, is implemented as a self-emitting display device or an electronic device such as a laptop computer, a mobile phone, a digital camera, a personal digital assistant (PDA), a desktop computer, a television, a car display or a portable DVD player. In some embodiments, the described self-emitting display device can be incorporated into a display panel, such as a self-emitting display panel. As shown in  FIG. 4 , a display panel  400  may comprise a self-emitting display device  300  shown in  FIG. 1G . In some embodiments, the display panel  400  can be incorporated into an electronic device. As shown in  FIG. 4 , an electronic device  600  comprises the display panel  400  having the self-emitting display device  300  and a controller  500  that is coupled to the self-emitting display device  300 . The controller  500  is operative to provide input signals (e.g. image signals) to the self-emitting display device  300  to generate images. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.