Patent Publication Number: US-8111216-B2

Title: Display system and pixel driving circuit thereof

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation-In-Part of pending U.S. patent application Ser. No. 11/801,162, filed May 8, 2007 and entitled “system for displaying image and driving display element method”. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a display system and, in particular, to a display system with a pixel driving circuit compensating threshold voltage and power loss. 
     2. Description of the Related Art 
     Organic light emitting diode (OLED) displays that use organic compounds as a lighting material for illumination are flat displays. The advantages of the OLED displays are a smaller size, lighter weight, wider viewing angle, higher contrast ratio and faster speed. 
     Active matrix organic light emitting diode (AMOLED) displays are currently emerging as the next generation flat panel displays. Compared with active matrix liquid crystal displays (AMLCD), the AMOLED display has many advantages, such as higher contrast ratio, wider viewing angle, and thinner module without backlight, lower power consumption, and lower cost. Unlike the AMLCD display, which is driven by a voltage source, an AMOLED display requires a current source to drive a display device EL (electroluminescent). The brightness of display device EL is proportional to the current conducted thereby. Variations in current level have a great impact on brightness uniformity of an AMOLED display. Thus, the quality of a pixel driving circuit is critical to the quality of an AMOLED display. 
       FIG. 1  shows a conventional 2T1C (2 transistors and 1 capacitor) pixel driving circuit  10  in an AMOLED display. Pixel driving circuit  10  comprises transistors Mx and My. When signal SCAN turns on transistor Mx, data signal shown as V data  in the  FIG. 1  is loaded into a gate of p-type transistor My and stored in capacitor Cst. Thus, there is a constant current driving display device EL to emit light. Typically, in an AMOLED display, a current source is implemented by a P-type TFT (My in  FIG. 1 ) gated by data signal V data  and having source and drain connected to V dd  and the anode of display device EL, respectively, as shown in  FIG. 1 . The brightness of display device EL with respect to V data  therefore has the following relation.
 
Brightness∝current∝(V dd −V data −V th ) 2  
 
     Where V th  is a threshold voltage of transistor My and V dd  is a power supply voltage. However, since there is typically a variation in V th  for a LTPS type TFT due to a low temperature polysilicon (LTPS) process, it is supposed that a non-uniformity problem in brightness exists in an AMOLED display if V th  is not properly compensated. Moreover, a voltage drop in the power line also causes the brightness non-uniformity problem. To overcome such problems, implementation of a pixel driving circuit with threshold voltage V th  and power supply voltage V dd  compensation to improve display uniformity is required. 
     BRIEF SUMMARY OF THE INVENTION 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     An embodiment of a display image system with a pixel driving circuit is provided. The pixel driving circuit comprises a storage capacitor, a transistor, a transfer circuit, a driving element and a switch circuit. The storage capacitor comprises a first node and a second node. The transistor comprises a gate coupled to a discharge signal and is coupled between the first node and the second node, wherein the transistor is turned on by the discharge signal to discharge the storage capacitor during a first period. The transfer circuit is coupled to the first node of the storage capacitor. The transfer circuit transmits a data signal or a reference signal to the first node of the storage capacitor. The driving element comprises a first terminal coupled to a first fixed potential, a second terminal coupled to the second node of the storage capacitor, and a third terminal outputting a driving current. The switch circuit is coupled between the driving element and a display element, directs the driving element to operate as a diode during a second period and allows the driving current to be output to the display element during a third period. 
     Another embodiment of a display image system with a pixel driving circuit is provided. The pixel driving circuit comprises a storage capacitor, a transistor, a transfer circuit, a driving element and a switch circuit. The storage capacitor comprises a first node and a second node. The transistor comprises a gate receiving a discharge signal and is coupled between the first node and the second node, wherein the transistor is turned on by the discharge signal to discharge the storage capacitor during a first discharge period and a second discharge period. The transfer circuit is coupled to the first node of the storage capacitor. The transfer circuit transmits a data signal or a reference signal to the first node of the storage capacitor. The driving element comprises a first terminal coupled to a first fixed potential, a second terminal coupled to the second node of the storage capacitor and a third terminal outputting a driving current. The switch circuit is coupled to the driving element, a first display element and a second display element, directs the driving element to operate as a diode during a first data load period and a second data load period and allows the driving current respectively to be output to the first display element and the second display element during a first emission period and a second emission period. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  shows a conventional 2T1C (2 transistors and 1 capacitor) pixel driving circuit in an AMOLED display; 
         FIG. 2  shows a pixel driving circuit according to an embodiment of the invention; 
         FIG. 3  is a timing diagram of a lighting signal, a discharge signal, a scan line signal, and horizontal clock signals of a pixel driving circuit shown in  FIG. 2 ; 
         FIG. 4  shows an AMOLED display loading data into red R, green G and blue B signal lines respectively by using horizontal clock signals CKHL 1 , CKH 2  and CKH 3 ; 
         FIG. 5  shows a pixel driving circuit according to another embodiment of the invention; 
         FIG. 6  is a timing diagram of signals of lighting signal, discharge signal, scan line signal, inverse scan line signal, and horizontal clock signals of a pixel driving circuit shown in  FIG. 5 ; 
         FIG. 7  schematically shows another embodiment of a system for displaying images according to the invention; 
         FIG. 8  shows a pixel driving circuit according to another embodiment of the invention; 
         FIG. 9  is a timing diagram of a frame signal, a discharge signal, a scan line signal and lighting signals according to the embodiment of the invention shown in  FIG. 8 ; and 
         FIG. 10  schematically shows another embodiment of a system for displaying images according to the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 2  shows a pixel driving circuit  200  according to an embodiment of the invention. Pixel driving circuit  200  compensates a threshold voltage and a power loss, such that the voltage of power supply PVdd is not limited by scan signal Scan. Pixel driving circuit  200  comprises storage capacitor Cst, transfer circuit  210 , driving transistor (driving element) M 5 , transistor M 6  and switch circuit  220 . 
     Transfer circuit  210  is coupled to first node A of storage capacitor Cst and transmits data signal Vdata or reference signal Vref to first node A of storage capacitor Cst. Reference signal Vref may be a fixed voltage signal. Driving transistor M 5  may be a PTFT (positive-channel thin film transistor) transistor. A source terminal of transistor M 5  is coupled to first voltage PVdd. A gate terminal of transistor M 5  is coupled to second node B of storage capacitor Cst. More specifically, first voltage is power supply PVdd. Switch circuit  220  is coupled to a drain terminal of transistor M 5 . Switch circuit  220  directs transistor M 5  to operate as a diode, such that transistor M 5  becomes a diode-connected transistor once fourth transistor M 4  is turned on. Display device EL is coupled to switch circuit  220 . Preferably, display device EL is an electroluminescent device. Additionally, a cathode of display device EL is coupled to a second voltage. More specifically, the second voltage is voltage VSS or ground voltage. 
     Transfer circuit  210  comprises first transistor M 1  and second transistor M 2 , as shown in  FIG. 2 , wherein first transistor M 1  and second transistor M 2  are an NTFT (negative-channel thin film transistor) transistor and a PTFT transistor, respectively. A drain terminal of first transistor M 1  receives data signal Vdata. A gate terminal and a source terminal of first transistor M 1  are connected to first scan line Scan and first node A of storage capacitor Cst, respectively. A source terminal of second transistor M 2  receives reference signal Vref. A gate terminal and a drain terminal of second transistor M 2  are connected to scan line Scan and first node A of storage capacitor Cst, respectively. Preferably, transistors M 1  and M 2  are polysilicon thin film transistors, providing higher current driving capability. 
     When scan line signal Scan is pulled high, transfer circuit  210  transmits data signal Vdata to first node A of storage capacitor Cst. When scan line signal Scan is pulled low, transfer circuit  210  transmits reference signal Vref to first node A of storage capacitor Cst. 
     Switch circuit  220  comprises third transistor M 3  and fourth transistor M 4 . As shown in  FIG. 2 , third transistor M 3  is a PMOS transistor and fourth transistor M 4  is a NMOS transistor. A drain terminal of third transistor M 3  is connected to an anode of display device EL, while a gate terminal and a source terminal of third transistor M 3  are connected to lighting signal Emi and driving transistor M 5 , respectively. Fourth transistor M 4  comprises a source terminal coupled to driving transistor M 5  and third transistor M 3 . A drain terminal of fourth transistor M 4  is coupled to second node B of storage capacitor Cst, a source terminal of transistor M 6  and a gate terminal of driving transistor M 5 . A gate terminal of fourth transistor M 4  is connected to scan line Scan. Preferably, transistors M 3  and M 4  are polysilicon thin film transistors, providing higher current driving capability. 
     When scan line signal Scan is pulled high, fourth transistor M 4  of switch circuit  220  directs driving transistor M 5  to operate as a diode, becoming a diode-connected transistor once fourth transistor M 4  is turned on. 
     A drain terminal of transistor M 6  is coupled to first node A of storage capacitor Cst. A gate terminal of transistor M 6  is coupled to discharge signal Discharge. A source terminal of transistor M 6  is coupled to second node B of storage capacitor Cst, the drain terminal of transistor M 4  and the gate terminal of driving transistor M 5 . 
       FIG. 3  is a timing diagram of lighting signal Emi, discharge signal Discharge, scan line signal Scan, and horizontal clock signals CKH 1 , CKH 2  and CKH 3  of a pixel driving circuit  200  shown in  FIG. 2 . From a previous emission mode of the pixel driving circuit, when discharge signal Discharge is pulled high and lighting signal Emi is kept high, pixel driving circuit  200  of  FIG. 2  is in discharge mode S 1 . In discharge mode S 1 , transistor M 6  is turned on, and a high-level reference signal Vref is input to first node A and second node B of storage capacitor Cst. The charge stored in storage capacitor Cst is thus discharged in the discharge mode. The discharge of storage capacitor Cst ensures normal operation in subsequent steps. 
     Following the discharge of storage capacitor Cst, scan line signal Scan is pulled high, then pixel driving circuit  200  enters data load mode S 2 . When scan signal Scan is pulled high, first transistor M 1  and fourth transistor M 4  are turned on while second transistor M 2  and transistor M 6  are turned off. Since first transistor M 1  and fourth transistor M 4  are turned on, the voltage of first node A of storage capacitor Cst equals the voltage of data signal Vdata, where V th  is the threshold voltage of driving transistor M 5 . The voltage of second node B of storage capacitor Cst equal to Pvdd−Vth. Thus, the stored voltage across storage capacitor is Vdata−(PVdd−Vth). 
     When scan signal Scan is pulled low, data load mode S 2  ends. When lighting signal Emi is pulled low, pixel-driving circuit  200  enters emission mode S 3 . Since scan line signal Scan is low, second transistor M 2  is turned on and the voltage of first node A of storage capacitor Cst is reference voltage Vref. Since the stored voltage across storage capacitor cannot be changed immediately, the voltage of second node B of storage capacitor Cst becomes Vref−[Vdata+(PVdd−Vth)]. Current through the display device is proportional to (Vsg−Vth) 2  and also proportional to (Vdata−Vref) 2 . Thus, the current through display device EL is independent of threshold voltage V th  of driving transistor M 5  as well as power supply PVdd. The operation repeats continuously to control pixel emissions. 
       FIG. 4  shows an AMOLED display loading data into red R, green G and blue B signal lines respectively by using horizontal clock signals CKH 1 , CKH 2  and CKH 3 . When scan line signal Scan at row 1 , row 2  . . . or rown is high, in data load mode S 2 , horizontal clock signals CKH 1 , CKH 2  and CKH 3  respectively turn on switches SW 1 , SW 2  and SW 3  sequentially and data is loaded in red R, green G and blue B signal lines sequentially. 
       FIG. 5  shows pixel driving circuit  500  according to another embodiment of the invention. Pixel driving circuit  500  compensates a threshold voltage and a power supply, such that voltage of power supply PVdd is not limited by scan signal Scan. Pixel driving circuit  500  is similar to pixel driving circuit  200 , except that transistors M 7  and M 8  of  FIG. 5  are NTFT transistors while second transistor M 2  and third transistor M 3  of  FIG. 2  are PTFT transistors. A gate terminal of transistor M 7  of  FIG. 5  is coupled to inverse scan line signal ScanX. The phase of inverse scan line signal ScanX is opposite to that of scan line signal Scan. 
       FIG. 6  is a timing diagram of signals of lighting signal Emi, discharge signal Discharge, scan line signal Scan, inverse scan line signal ScanX, and horizontal clock signals CKH 1 , CKH 2  and CKH 3  of a pixel driving circuit  500  shown in  FIG. 5 . From a previous emission mode of the pixel driving circuit, when discharge signal Discharge is pulled low and lighting signal Emi is kept low, pixel driving circuit  500  of  FIG. 5  is operated in discharge mode S 1 . In discharge mode S 1 , transistor M 6  is turned on, and a high-level reference signal Vref is input to first node A and second node B of storage capacitor Cst. The charge stored in storage capacitor Cst is thus discharged in the discharge mode. The discharge of storage capacitor Cst ensures normal operation in subsequent steps. 
       FIG. 7  schematically shows another embodiment of a system for displaying images which, in this case, is implemented as display panel  400  or electronic device  600 . As shown in  FIG. 7 , display panel  400  comprises a pixel driving circuit  200  of  FIG. 2 . Display panel  400  can form a portion of a variety of electronic devices (in this case, electronic device  600 ). Generally, electronic device  600  can comprise display panel  400  and power supply  770 . Further, power supply  770  is operatively coupled to display panel  400  and provides power to display panel  400 . Electronic device  600  can be a mobile phone, digital camera, PDA (personal data assistant), notebook computer, desktop computer, television, or portable DVD player, for example. 
     The operation of  FIG. 5  is similar to that of  FIG. 2 . Thus, the electrical current through display device EL of  FIG. 5  is proportional to (Vsg−Vth) 2  and is also proportional to (Vdata−Vref) 2 , and the current through display device EL of  FIG. 5  is independent of threshold voltage V th  of driving transistor M 5  as well as power supply PVdd. The operation repeats continuously to control pixel emissions. 
     Pixel driving circuits  200  and  500  ( FIGS. 2 and 5 ) of the embodiments of the present invention are independent of threshold voltage V th  of driving transistor M 5  as well as power supply PVdd. Power supply PVdd and scan line signal Scan are independent of each other. Thus, the voltage range of scan line signal Scan is not limited by the voltage range of power supplies PVdd, and vice versa. 
     Since a display panel comprises more and more pixels and need to provide more and more colors, design engineers often increase different color emitting light units to increase pixels and colors. A conventional emitting light unit (pixel driving circuit  10 ) comprises a display device EL and a corresponding driving circuit. Since the driving circuit cannot emit light, reducing the size of the driving circuit is required for higher aperture ratio. The challenge for design engineers is thus, to put less driving circuits and more display devices in a fixed sized display panel. 
       FIG. 8  shows a pixel driving circuit  800  according to an embodiment of the invention. Pixel driving circuit  800  is a 5T1C+2C design circuit. In addition, pixel-driving circuit  800  compensates a threshold voltage and a power loss, such that the voltage of power supply PVdd is not limited by scan signal Scan. Pixel driving circuit  800  comprises storage capacitor Cst, transfer circuit  810 , driving transistor (driving element) M 5 , transistor M 6 , switch circuit  820  and display devices EL 1  and EL 2 . Display devices EL 1  and EL 2  can be emitting light units and share driving circuit  850  to provide more lighting area in pixel driving circuit  800 . Display devices EL 1  and EL 2  respectively use driving circuit  850  in sub-frame periods SF 1  and SF 2 . 
     Transfer circuit  810  is coupled to first node A of storage capacitor Cst and transmits data signal Vdata or reference signal Vref to first node A of storage capacitor Cst. Reference signal Vref is a fixed voltage signal. Driving transistor M 5  is PTFT transistor. The source terminal of driving transistor M 5  is coupled to power supply PVDD that is DC voltage. The gate terminal of driving transistor M 5  is coupled to second node B of storage capacitor Cst. Switch circuit  820  is coupled to the drain terminal of driving transistor M 5  and makes driving transistor M 5  diode-connected. Display devices EL 1  and EL 2  are respectively coupled to transistors M 3  and M 7 . In addition, the cathodes of display devices EL 1  and EL 2  are coupled to the second voltage. The second voltage can be ground or a fixed voltage VSS. 
     Transfer circuit  810  comprises first transistor M 1  and second transistor M 2 , as shown in  FIG. 8 , wherein first transistor M 1  and second transistor M 2  are an NTFT transistor and a PTFT transistor, respectively. The drain and gate of first transistor M 1  respectively receives data signal Vdata and scan signal Scan. The source terminal of first transistor M 1  is connected to first node A of storage capacitor Cst. The source and gate terminals of second transistor M 2  respectively receive reference signal Vref and scan signal Scan. The drain terminal of second transistor M 2  is connected to first node A of storage capacitor Cst. Preferably, transistors M 1  and M 2  are polysilicon thin film transistors, providing higher current driving capability. 
     When scan line signal Scan is pulled high, transfer circuit  810  transmits data signal Vdata to first node A of storage capacitor Cst. When scan line signal Scan is pulled low, transfer circuit  810  transmits reference signal Vref to first node A of storage capacitor Cst. 
     Switch circuit  820  comprises transistors M 3 , M 4  and M 7 . Transistors M 3  and M 7  are PTFT transistors and transistor M 4  is an NMOS transistor. The drain terminals of transistors M 3  and M 7  are respectively connected to anodes of display devices EL 1  and EL 2 , the gate terminals of transistors M 3  and M 7  respectively receive lighting signal Emit_ 1  and Emit_ 2  and the source terminals of transistors M 3  and M 7  are coupled to driving transistor M 5 . Transistor M 4  comprises a source terminal coupled to driving transistor M 5  and transistors M 3  and M 7  and a drain terminal coupled to second node B of storage capacitor Cst, the source terminal of transistor M 6  and the gate terminal of driving transistor M 5 . The gate of transistor M 4  receives scan line signal Scan. Preferably, transistors M 3  and M 7  are polysilicon thin film transistors, providing higher current driving capability. When scan line signal Scan is pulled high, transistor M 4  of switch circuit  820  directs driving transistor M 5  to operate as a diode, becoming a diode-connected transistor once transistor M 4  is turned on. 
     The drain terminal of transistor M 6  is coupled to first node A of storage capacitor Cst. The gate terminal of transistor M 6  receives discharge signal Discharge. The source terminal of transistor M 6  is coupled to second node B of storage capacitor Cst, the drain terminal of transistor M 4  and the gate terminal of driving transistor M 5 . 
       FIG. 9  is a timing diagram of frame signal FRAME, discharge signal Discharge, scan line signal Scan and lighting signals Emit_ 1  and Emit_ 2  according to the embodiment of the invention shown in  FIG. 8 . Pixel driving circuit  800  decides sub-frame period SF 1  or sub-frame period SF 2  according to frame signal FRAME. A frame period comprises sub-frame period SF 1  and sub-frame period SF 2 . During sub-frame period SF 1 , when discharge signal Discharge is pulled high and lighting signal Emit_ 1  is maintained at high voltage level, pixel driving circuit  800  is operated at discharge mode S 1 . During discharging period S 1 , transistor M 6  is turned on and scan signal Scan is at low voltage level. Thus, reference signal Vref is stored at first node A and second node B of storage capacitor Cst to discharge storage capacitor Cst. The discharge of storage capacitor Cst ensures normal operation in subsequent steps. 
     Following the discharge of storage capacitor Cst, scan line signal Scan is pulled high, then pixel driving circuit  800  enters data load mode S 2 . When scan line signal Scan is pulled high, transistor M 1  and transistor M 4  are turned on while transistor M 2  and transistor M 6  are turned off. Since transistor M 1  and transistor M 4  are turned on, the voltage of first node A of storage capacitor Cst equals the voltage of data signal Vdata, where V th  is the threshold voltage of driving transistor M 5 . The voltage of second node B of storage capacitor Cst equal to Pvdd−Vth. Thus, the stored voltage across storage capacitor is Vdata−(PVdd−Vth). 
     When scan line signal Scan is pulled low, data load mode S 2  ends. When lighting signal Emi_ 1  is pulled low, pixel-driving circuit  800  enters emission mode S 3 . Since scan line signal Scan is at low voltage level, second transistor M 2  is turned on and the voltage of first node A of storage capacitor Cst is reference voltage Vref. Since the voltage across storage capacitor cannot be changed immediately, the voltage of second node B of storage capacitor Cst becomes Vref−[Vdata+(PVdd−Vth)]. Currents through the display devices EL 1  and EL 2  are proportional to (Vsg−Vth) 2  and also proportional to (Vdata−Vref) 2 . Thus, during sub-frame period SF 1 , the current through display device EL 1  is independent of threshold voltage V th  of driving transistor M 5  as well as power supply PVdd. 
     During sub-frame period SF 2 , lighting signal Emit_ 1  is maintained at high voltage level. During sub-frame period SF 2 , discharge signal Discharge, scan line signal Scan and lighting signal Emit_ 2  repeat the emitting light sequence of sub-frame period SF 1 . When discharge signal Discharge is pulled high and lighting signal Emit_ 2  is maintained at high voltage level, pixel-driving circuit  800  is operated at discharge mode S 4  and storage capacitor Cst discharges charges. When scan line signal Scan is pulled high, pixel-driving circuit  800  enters data load mode S 5 . When scan line signal Scan is pulled low, data load mode S 2  ends. When lighting signal Emi_ 2  is pulled low, pixel-driving circuit  800  enters emission mode S 6 . Other operations at sub-frame period SF 2  are the same as those at sub-frame period SF 1 . Thus, during sub-frame period SF 2 , the current through display device EL 2  is independent of threshold voltage V th  of driving transistor M 5  as well as power supply PVdd. As shown in  FIG. 9 , discharge mode S 1 , data load mode S 2 , emission mode S 3 , discharge mode S 4 , data load mode S 5  and emission mode S 5  occur in order. 
     Pixel driving circuit  800  is independent of threshold voltage V th  of driving transistor M 5  as well as power supply PVdd. And power supply PVDD is independent of the voltage level of scan line signal Scan. Thus, the voltage range of scan line signals Scan is not limited to the voltage range of power supply PVdd. Display devices EL 1  and EL 2  share driving circuit  850  to increase the lighting areas of display devices EL 1  and EL 2  of pixel driving circuit  800 . 
       FIG. 10  schematically shows another embodiment of a system for displaying images according to the invention that, in this case, is implemented as display panel  400  or electronic device  600 . As shown in  FIG. 10 , display panel  400  comprises a pixel driving circuit  800  of  FIG. 8 . Display panel  400  can form a portion of a variety of electronic devices (in this case, electronic device  600 ). Generally, electronic device  600  can comprise display panel  400  and power supply  770 . Further, power supply  770  is operatively coupled to display panel  400  and provides power to display panel  400 . Electronic device  600  can be a mobile phone, digital camera, PDA (personal data assistant), notebook computer, desktop computer, television, or portable DVD player, for example. 
     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited to thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.