Patent Publication Number: US-3878513-A

Title: Data processing method and apparatus using occupancy indications to reserve storage space for a stack

Description:
United States Patent Werner 1 1 DATA PROCESSING METHOD AND APPARATUS USING OCCUPANCY INDICATIONS TO RESERVE STORAGE SPACE FOR A STACK [75] Inventor: John R. Werner, Glendora. Calif.  
 [73] Assignee: Burroughs Corporation, Detroit,  
 Mich.  
 [22] Filed: Feb. 8, 1972 [2]] App]. No.: 224,435  
 [52] US. Cl. 340/1725 [51] Int. Cl. G06f 7/00; G06f 13/00 [58] Field of Search 340/1725; 444/1 [56] References Cited UNITED STATES PATENTS 3,416,138 12/1968 Brass 340/1725 3,573,750 4/1971 lshidatc 340/1725 3,588,839 6/1971 Beledy et a1. 340/1725 3,594,732 7/1971 Mendelson et a1. 340/1725 3,629,587 12/1971 Faber 1 1 340/1715 3,670,307 6/1972 Arnold et al H 340/1725 3,670.309 6/1972 Amdahl et a1. 340/1725 3,675,217 7/1972 Dauber et al. 340/1725 OTHER PUBLICATIONS Scarrott, G. (1., Information Processing, Vol. 1, 1965,  
 pp 137-141. (L-7140-l245) Primary Examiner-l-larvey E. Springborn Assistant Examiner-Michael Sachs Attorney, Agent, or Firm-Christie, Parker &amp; Hale tl-&#34;lfl t ttttl 1 Apr. 15, 1975 tions in one-to-one correspondence with a group of memory locations so as to define corresponding pairs of locations. Each pair is reserved for storing a different stack word and has four occupancy conditions. Before the actual accumulation of the stack word for which the pair is reserved. the pair is in a first condition wherein both locations of the pair are unoccupied. After actual accumulation. the pair is either in a second condition wherein only the extension is occupied, or in a third condition wherein only the memory location is occupied, or in a fourth condition wherein both locations are occupied. Preferably each extension location has occupied and copy indicating storage cells having four states each indicating one of the four possible conditions. Stack words forming the record of execution of a first program block are initially accumulated in the extension locations. When a second program block nested within the first program block is entered the record of execution of the first block is transferred to the presently corresponding memory 10- cations and then the associating register means is set to associate the extension registers with a different group of memory locations so that the extension locations are available to store stack words for the second block. The stack includes a linked list of control words containing stack depth information indicating the number of stack words accumulated in executing each block. Upon a transfer of control from the second block back to the first block the stack depth information is used to set the associating register means so that the required number of extension locations are again reserved for storing the previously accumulated record of execution of the first block. Instead of indiscriminately transferring the record of execution of the first block back to such reserved extension locations, the occupancy and copy indicating storage cells for each such reserved extension location are set to indicate that only the respective memory location is occupied. Thus upon a further transfer of control to another block, the occupancy and copy indicating storage cells provide information used to eliminate unnecessary transfers of words to memory locations already storing the proper words.  
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 00 47-4 7 than 7- DATA PROCESSING METHOD AND APPARATUS USING OCCUPANCY INDICATIONS TO RESERVE STORAGE SPACE FOR A STACK CROSS-REFERENCE TO A RELATED APPLICATION A related patent applicaation entitled DATA PRO- CESSOR HAVING AN ADDRESSABLE LOCAL MEMORY LINKED TO A MEMORY STACK AS AN EXTENSION THEREOF, by Erwin A. Hauck and assigned to the assignee of this invention. bearing Ser. No. 224,420, filed Feb. 8, l972 has issued as US. Pat. No. 3,725,876. This related patent is directed to a data processing system wherein the storage of information items is allocated between a main stack storing memory and a local stack extension memory such that parameters and variables local to a currently executing program block are captured in the stack extension memory where they can be selectively read out quickly and repeatedly. The related patent discloses means operative upon entry from an old program block into a new program block for allocating the stack extension memory to the storage of a stack for the new block and for transferring a stack for the old program block from the stack extension memory to the main stack storing memory.  
  The present invention is directed to an improved method and apparatus for an addressable stack extension memory wherein the allocation of storing information items is controlled by an occupancy indication and the invention provides for updating the occupancy indication upon exit from one program block into another program block.  
 BACKGROUND OF THE INVENTION l. Field of the Invention This invention relates to data processing system methods and apparatus and, particularly to stack organized data processing.  
 2. Description of the Prior Art A machine language program for a data processing system comprises executable program operators for causing a data processor to process input data in a series of steps. During the execution of a program, infor mation items in the nature of intermediate results are produced. Such information items are temporarily stored in a memory until they are needed in a subsequent step. In many data processing applications, these information items are needed in an order reversed from the order in which they were produced. Thus the information items are written into the memory and then read from the memory on a last-in, first out (LIFO) basis. The task of storing such information items involves certain sub-tasks. For example, memory space must be allocated for storing such information items and then de-allocated after they are no longer needed. Also, the information items must be stored in such a way that the data processor will know where to find them when they are needed.  
  Prior art data processors have included apparatus, commonly called a stack mechanism, for facilitating this task. A stack mechanism accumulates the information items in a memory in the form ofa linear list called a memory stack. As information items which must be saved for later use are produced, the stack mechanism writes such information items into the memory by what are called push-down operations. When an information item is needed, the stack mechanism reads it from the memory by what is called a pop-up operation. Each push-down operation causes an information item to be added to the memory stack or, equivalently, to increase the total of accumulated information items. Each popup operation causes an information item to be removed from the memory stack or, equivalently, to decrease the total of accumulated information items. Thus the memory stack expands as a result of push-down operations and contracts as a result of popup operations.  
  A memory stack has a top of memory stack information item. This is the information item which was added to the memory stack by the last or, equivalently, the most recent push-down operation and which has not yet been removed from the memory stack by a pop&#39;up operation. A stack mechanism includes means for keeping track of where the top of stack information resides. Typically, a stack mechanism includes an address register for this purpose. This address register stores a pointer which points to a memory location which contains the information item at the top of the memory stack. The noun pointer and the verb points&#34; are useful items, which will be used in this application. The term pointer subsumes the terms absolute address, relative address, and indirect address. Thus a pointer is a coded signal identifying a desired location. A pointer is said to point to a desired location. These terms are useful because they express a concept in a way which subordinates unimportant detail. Consider for example a situation in which the top of memory stack information item is a double precision word and occupies two successive memory locations. In this situation, it would be imprecise to say that the abovementioned address register stores the address of the location storing the top of stack information item.  
  A stack can be built up from different kinds of information items. The stack can consist entirely of operands. entirely of control words, or a mixture of operands and control words. When the stack consists entirely ofoperands, the stack is called an operand stack. An operand stack is built up on a pure LIFO basis. That is, the operands in the stack can be brought out of the memory only in an order reversed from the order in which they were brought in. In other words, there is no random access addressing means by which the programmer can order operands to be brought out of the operand stack in a different order. Since the memory stack operands cannot be addressed by the programmer they are said to be invisible to the programmer. The memory means which stores an operand stack typically comprises first and second high speed registers within a data processor and a part of a main memory. A stack mechanism that is used in connection with an operand stack typically comprises means for linking these two high speed registers to the memory stack so that they form the top two available locations of the stack storage means and a part ofthe control unit of the processor which produces control signals for causing operands in the stack to be poppedup and pusheddown. This linkage is accomplished by providing an occupancy-indicating flip-flop for each of the two high speed registers and a stack pointer register. The stack pointer register stores an indication of the main mem ory location storing the top of memory stack operand. Each occupany flip-flop stores an indication of whether or not there is a valid operand in its associated register.  
 An operand stack is particularly suited to facilitate 1e computation of equations that are expressed in Pol- .h notationv Such equations are parenthesis free and onsist of a string of operands and operators. A conention is established whereby each arithmetic opera- )t operates on two immediately preceding operands. &#39;onsider. for example, the Polish notation string a b c -.r. The two operands preceding the plus sign are b and and therefore the plus sign indicates that b and c are i be combined to form a single new operand (b 0). low the two operands preceding the multiply sign beome (b c) and u. Therefore the multiply sign indiates that the two operands a and (b c) are to be comined to form a single new operand (u).\&#39;(h+(&#39;). Each .me a pair of operands are operated upon or combined a form a new single operand they are said to be &#34;diested.&#34;  
  A program for the exemplary Polish notation string iven above and the response thereto of a prior art proessor is as follows. A program operator orders the proessor to fetch the operand u from an indicated loca ion of the memory and to place a at the top of the tack. The stack mechanism responds to adjust the tack down. In adjusting the stack down the stack nechanism checks the first occupancy-indicating fliplop. If it is indicated that a valid operand is stored herein the contents of the second register is pushed lown into the memory stack and then replaced by the :ontents of the first register. After the stack has been idjusted down the first register is unoccupied and is herefore available to store the operand u. Then the op- :rand a is fetched from memory and stored into the &#39;irst register. Simultaneously. the first occupancy fliplop is set to indicate that the first register contains a alid operand. A second and third program operator .hen orders the processor to place the operands b and respectively at the top of the stack, and the processor &#39;esponds as described above.  
  At this point the operand u is now the top of memory ,tack operand; the operand b is stored in the second &#39;egister; and the operand c is the top of stack operand ind is stored in the first register. Next a program opera- :or orders an add operation. The processor responds to :ouple the contents of the first and second registers to :he arithmetic unit which sums the b and r operands to Jroduce the single operand (b +0] and stores this sum Jack into the second register. Simultaneously the first )ccupancy flip flop is reset to indicate that the first reglster does not contain a valid operand. This is done because the two operands b and c previously occupying the first and second registers have been combined into a single operand now occupying only the second register and the first register is unoccupied. Next. a program operator orders a multiply operation. The stack mechanism responds to adjust the stack up. In adjusting the stack up the stack mechanism checks the first occupancy-indicating flip-flop and finds that no valid operand is stored in the first register. Therefore, the contents of the second register (b c) are transferred to the first register and the operand at the top of memory stack (operand u) is retrieved from memory and stored into the second register. The processor then couples the contents of the first and second registers to the arithmetic unit which produces the product (a).r(b+c) and stores this product back into the second register. A digital processor which operates in accordance with the foregoing is described in US. Pat. No. 3,200,379.  
  The above-described example illustrates one of two related problems that arise in stacking words. Both of these problems stem from the fact that a significant amount of time is required for main memory accesses and this time is quite large compared to the time re quired for a register to register transfer. Two factors affect this relative access time. Firstly. main memory is generally constructed from magnetic core elements which are inherently slower than the circuit elements within the processor. Secondly, main memory is generally shared by a plurality of requesting units such as other data processors, input/output controllers, and the like. Such sharing of main memory leads to queuing of requests. In contrast, an intraprocessor transfer is independent of other units in the system. Since the transfer of information back and forth between main memory and the processor takes a relatively large amount of time, the system throughput is adversely affected by repeated main memory accesses. The adverse effect of the first problem is measured in terms of what is called stack adjustment overhead. Note that in the abovedescribed example the processor read out the operand a from main memory, did nothing of significance with it. stored it back into main memory. and subsequently read it out again for use in connection with the multiply operation. Thus three main memory accesses were involved before the operand a was actually combined with the operand (b c). Such repeated main memory accesses are time consuming and serously affect the computing power of the machine.  
  The related problem of repeated main memory accesses does not directly involve pop-up, push-down operations ofa LIFO memory. This problem arises in con nection with obtaining information from indicated locations of the main memory for placement in the stack. To understand this problem consider first an oversimplified example of the computation of a. In Polish notation a is expressed aaaxx. A program for this Polish notation string could make three consecutive main memory accesses to fetch the same variable for placing the variable at the top of the stack three consecutive times. Then two multiply operators would cause the three operands to be combined to form a. This related problem is manifested whenever the same operand must be brought to the top of the stack several different times during the execution of a program string. This related problem becomes especially aggravated when the location of the desired operand is indicated by an indirect address. An indirect address is an address that specifies a location whose contents is either an address or another indirect address. The contents of the specified location are used to obtain the actual operand. Thus a chain of main memory accesses may be necessary to obtain a single desired operand for placement in the stack.  
  In an attempt to minimize the number of main memory accesses and thereby increase processing speeds, prior art data processors have included high speed local memories. Such local memories have less storage capacity than the main memory because in general the cost and access time of a memory increases in proportion to its storage capacityv In systems which include a main memory and a data processor having a local memory. some means must be provided for allocating be tween the two memories the storage of information items. The allocation means must decide what information should be stored in the local memory and what information should be stored in the main memory; it must decide when to store information in the local memory and when to store information in the main memory; and it must decide when to replace information in the local memory with information from the main memory.  
  Consider an approach taken in the prior art to alleviate the stack adjustment overhead problem discussed above by employing a local memory in the data processor. The approach is disclosed in U.S. Pat. No. 3,40l,376 by G. H. Barnes et al entitled CENTRAL PROCESSOR and assigned to the assignee of this invention. The Barnes et al patent discloses a data processor which includes the usual pair of high speed registers and additionally includes l2 other high speed registers that operate as an operand stack extension. In this machine the stack is adjusted down by pushing the operands out of the pair of high speed registers down into the stack extension instead of writing them into the main memory immediately. Also the stack is adjusted up by popping up operands from the stack extension instead of reading them out from the top of the stack in main memory. The last operand pushed down into the stack extension is always the first word popped up into the pair of high speed registers. As is typical with an operand stack, the operands stored in this stack extension are invisible to the programmer. Although this stack extension is a pure LlFO memory with respect to operand transfers between it and the pair of high speed registers, it operates on a first-in first-out (FIFO) basis with respect to transfers of operands that pass through the stack extension to the main memory. This is because the operands at the bottom of the stack extension are pushed out of the bottom ofthe stack extension into the operand stack in the main memory when it becomes necessary to make space available in the stack extension for storage of more operands. Thus as a series of operands are pushed down into the stack extension the first operand moves down through the stack extension and after the stack extension is full the first operand is the first ofthe series to be pushed down into the stack in main memory.  
  The means for linking this stack extension to the main memory stack comprises a top pointer, a bottom pointer, a detector for detecting predetermined differences between the top and bottom pointers, and a main memory stack location pointer. The top pointer identifies the register storing the top word in the stack extension. The bottom pointer identifies the register storing the bottom word in the stack extension. In use, all of the registers including and between the two identified registers store operands and are said to be occupied. Therefore, the differences between the top and bottom pointers provide an indication of the extent to which the stack extension memory, as a whole, is occupied. When the difference detector senses that the stack extension memory is full it actuates circuitry which transfers the bottom four words of the stack extension over to the main memory stack in accordance with address information provided by the main memory stack location pointer. Also, when the difference detector senses that the stack extension is nearly empty it actuates circuitry which transfers to the bottom of the stack extension four words from the main memory stack. Thus the stack extension always contains the top words in the stack.  
  A second type of stack consisting entirely of control words has been used to link different parts ofa program together. Frequently in the execution of a program it becomes necessary for a first procedure to initiate the execution of (call) a second procedure. When such a call occurs it is necessary to remember the point in the first procedure where the processor should return at the completion of the second procedure. Furthermore, a called procedure can itself call a different procedure and therefore it is necessary to remember a plurality of return points. Thus a stack for storing a plurality of re turn points can be called a subroutine control stack.  
  A third type of stack consisting of a mixture of operands and control words is disclosed in US. Pat. No. 3.l53,225 by .l. N. Merner et al. entitled DATA PRO- CESSOR WITH lMPROVED SUBROUTINE CON- TROL and assigned to the assignee of this invention. The data processor of this patent includes means for inserting control words into the stack as well as operands so as to mark off areas of the stack that are related to particular subroutines. The insertion of these control words into the stack serves several functions. One function is to provide subroutine linkage information by creating a linked list denoting the stack history. The stack history list is a record of the actual sequential order in which the program entered different levels. Another function is to provide base addresses for relative addressing within the stack. During subroutine execution a program operator can call on or obtain a parameter that is stored within the stack even though the parameter cannot be popped up immediately because it was not the last item pushed down into the stack. Thus this type of stack is not a pure LIFO stack, and the words within the stack are considered to be visible&#34; to the programmer.  
  An advantage arises from the provision of means for addressing within a stack and rendering the words therein visible. That is that once an information item has been placed in the stack it can be brought to the top of the stack again without using indirect addressing techniques and the attendant multiplicity ofmain memory accesses.  
  US Pat. No. 3,461,435 by R. S. Barton et al, entitled STACK MECHANISM HAVlNG MULTIPLE DlS PLAY REGISTERS and assigned to the assignee of this invention, also discloses a stack mechanism that stores in a single stack both operands and subroutine control information. The data processor disclosed in this patent discloses improved apparatus for addressing within a stack. The processor has a plurality of display registers each of which stores an address of a control word which marks the stack. Each stored address is a base address for base relative addressing within the stack. All of the base addresses for the current procedural addressing environment are made visible by the display registers.  
  US. Pat. No. 3,548,384 entitled PROCEDURE ENTRY FOR A DATA PROCESSOR EMPLOYING A STACK and assigned to the assignee of this invention, is directed to the method and means by which the above-mentioned display registers are updated. This patent describes in detail how the information con tained within the control words in the stack can be used in the execution of programs expressed in ALGOL-like languages.  
  A program written in ALGOL is arranged in blocks. A block comprises one or more statements that order certain actions; declarations of identifiers; and the tatements BEGIN and END. which mark the boundries of the block.  
  One purpose of a block is to introduce a new level of omentclature by means of the declarations of identilers. A new level of nomenclature is introduced by esting one block within another block. Such nested locks are related to each other as local and global docks. Under the ALGOL rules an identifier can have he same meaning within a local block as it has within ts global block. On the other hand, the same identifier I215 completely different meanings within the nested docks when the identifier is redeclared within the local dock. This is a powerful feature of the ALGOL lan- ,uage because it permits a programmer to use convelient, suggestive identifiers within the block he is writ ng without fear that he may be inadvertently affecting ome other block.  
  Before a program written in ALGOL is executed, it s translated into machine code by another program :alled a compiler. The machine code comprises a pluality of program operators or instructions. The pro ;ram code produced by the compiler is used to control he processing of data. It is advantageous to make the irogram code independent ofthe data in the sense that he program code is not modified during the time it :ontrols the processing of data. Since the program code s not modified while controlling the processing of one .et of data it can be used again for controlling the pro- :essing of a different set of data in the same manner. This feature is called re-entrant coding and is a powerul tool in a multiprocessing machine.  
  The prior art computing machine described in US. at. No. 3548384 has features which facilitate the ex- :cution of programs having a block structure. Its in- :truction preparatory includes program operators hav ng functions which closely resemble the functions of ;he BEGIN and END statements of ALGOL. It includes 1 stack mechanism for building a stack representing the &#39;ecord of execution of a block. Each block storage area )f a stack has a Mark Stack Control Word (MSCW) which is located at its beginning or base and which ;erves to identify the particular block storage area. A Return Control Word (RCW) is located in the next lo- :ation above each MSCW. The RCW contains information that is used upon completion of execution of the program block. For procedural blocks, the successive locations of the stack upwardly from the RCW :ontain parameters that have been passed to the procedure. In addition, references to variables and procedures that have been declared local to the block are stored above the RCW. Parameters are located in the stack by a lexicographical level value (1!) plus an increment value (5). The lexicographical level selects one of the display registers and the absolute address in the display register is added to the increment value to give the main memory address of the desired parameters.  
  In the related patent application entitled DATA PROCESSOR HAVING AN ADDRESSABLE LOCAL MEMORY LINKED TO A MEMORY STACK AS AN EXTENSION THEREOF, cross-referenced above, there is disclosed an improved stack organization that stores parameters in a high speed addressable memory which is linked to a main stack storing memory to form a stack extension memory. An object of this improved stack organization is to allocate the storage of information items between the main memory and the stack extension memory such that those information items that are currently needed for processing are stored in the stack extension memory. Two features of this stack extension memory contrast with prior art stack extensions. One. information items are not pushed down out of the bottom of this stack extension into the main memory stack but instead are captured during the exe cution of a program block. Two, the stack extension memory is addressable and captured information items are made visible. That is, a program operator can order a captured information item to be read from a selected location and be brought to the top of the stack.  
  Consider now how these two features attain the above-mentioned object. A program having a block structure contains program operators indicating the boundaries of each block. A block can be nested as a local block within a global block. Execution of such a program can proceed in stages wherein the program enters the global block; then enters the local block before completing the execution of the global block; then exits or returns from the local block to the global block; and then completes the execution of the global block. Thus the block which the processor is currently executing changes from the global block to the local block and then changes back to the global block. Each block has its own local variables which will be referred to during its execution. A block which is a procedural block will in addition have parameters passed to it from a calling block and these parameters will be referred to during the execution of the procedural block. Upon entry into a block. information items such as parameters and local variables are written into the stack extension memory. Since these information items will be needed during execution of the entered block, it is advantageous to store them in the higher speed extension memory. During the execution of the entered block a stack is built up in the stack extension memory but the parameters and variables are not pushed down out of the bottom of the stack extension memory as in the prior art, and instead are captured while the block is being executed. Since the stack extension memory is addressable, the parameters and variables can be referred to as needed and can be brought to the top of the stack in any desired order. As each new block is entered, the stack extension memory is flushed out so that it will be available for storing a stack for the new block. This flushing is in the nature of an overlay wherein accumulated information items are transferred to the main stack storing memory. Thus it can be seen that information items are not permanently captured in the stack extension memory. Instead the stack extension memory captures them only during the stage in which they are most frequently needed for processing and the stack extension memory is updated each time a new block is entered. Although main memory accesses are still required for bringing information items into the stack extension memory and for flushing out the stack extension, a substantial number of main memory ac cesses are saved in stack adjustment operations and in bringing parameters and local variables to the top of the stack.  
  The present invention provides a further improve ment in allocating the storage of information items between a stack extension memory and a main stack storing memory. It is an object of this invention to reduce further the number of main memory accesses in executing a program and in particular to eliminate some of the main memory accesses which are involved in obtaining information items from the main stack storing memory for writing into the stack extension memory.  
 SUMMARY OF THE INVENTION The present invention is directed to an improved method and apparatus for allocating the storage of information items between a main stack storing memory and a stack extension memory.  
  A data processing system embodying the present invention includes memory means comprising an addressable main memory and an addressable stack extension memory; a plurality of occupancy indicating means, each associated with a different address of the stack extension memory and each indicating whether its associated address stores an information item of a stack; and means for accumulating in the memory means information items which must be saved for later use and for retrieving an accumulated information item when needed either from the stack extension memory or from the main memory in accordance with an indi cation provided by the occupancy indicating means. The invention provides a stack mechanism for writing information items into the stack extension memory and for reading them out on a last-in, first-out basis whereby a stack of information items is accumulated. The invention also provides a means for reading out some other information item within the stack in addition to the last information item added to the stack.  
  A feature of the present invention resides in the storing within the stack extension memory of information items which can be referred to in a program block building the stack and the setting of the occupancy indicating means to indicate that such information items can be read out of the stack extension memory and that a time consuming main memory access is unnecessary.  
  Another feature of the present invention resides in the selective manner in which information items are written into the stack extension memory. As in the system of the above-mentioned related application the contents ofthe stack extension memory are updated on each entry into a new program block by writing into the stack extension memory the parameters and local variables for the new program block. In contrast, however, the present invention provides for the elimination of main memory accesses involved in updating the contents of the stack extension memory upon leaving (exit from) a program block. For example, upon an exit from a local block back to a previously entered global block, the stack which has already been accumulated for the global block is not automatically written into the stack extension memory. Instead, the present invention provides for temporarily reserving space in the stack ex tension memory for the global stack. Each address of the stack extension memory so reserved has its occupancy indicating means reset to indicate that it does not actually store a valid information item. In the event that such information is needed in the first stages of executing the global block a main memory access can be made to obtain it. On the other hand, in the event that such information item is not so needed at least one and possibly two main memory accesses are eliminated depending upon whether the program next exits the global block or next enters another local block.  
  A preferred embodiment of the present invention includes a plurality of copy indicating means. each associated with a different stack extension memory address and each indicating whether an information item stored in the associated address is a copy of an information item stored in the main memory stack. In this preferred embodiment, the flushing of the stack extension upon entry into a program block involves inspection of the copy indicating means and the elimination of main memory write accesses for those information items which are copies.  
  A feature of the preferred embodiment resides in reserving space in the stack extension memory for a stack, selectively reading an information item from a stack in the main memory, writing the information unit into the stack extension memory and setting the copy indicating means.  
  Another feature of this invention resides in the novel manner in which a stack history list is used to allocate locations of the stack extension memory. The stack his tory list is made up from a linked list of control words which make the beginning of stack areas storing stacks for the different program blocks. The mark words contain a difference value pointing to a preceding mark word and indicating the depth of the preceding stack. As each block is exited. this difference value is ob tained and supplied to address modifying means which in turn produces a pointer to a new top location of the stack extension memory. All of the locations below the new top location are reserved.  
  A method in accordance with the present invention comprises the steps of accumulating as a stack in the stack extension memory a plurality of words during the execution of a block of push-down and pop-up operations and simultaneously updating a pointer to the top of stack word; marking the locations ofthe stack extension memory to indicate such locations are occupied; detecting an entry into a different block. and responsive thereto, flushing the stack extension; accumulating, updating and marking as above for the different block; detecting an exit back to the original block. and responsive thereto. marking the locations of the stack extension memory and setting the pointer to point to the location of the stack extension which had stored the top of stack word for the original block when the program entered the different block.  
 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall block diagram of a data processing system having a stack extension memory and embodying the present invention;  
  FIG. 2 is a block diagram of block 2 of FIG. 1 and shows the details of the stack extension memory and its associated circuitry;  
  FIG. 3 is a sketch showing the format of various types of words stored in a stack;  
  FIG. 4 comprises FIGS. 4A, 4B, and 4C which are sketches representing a snapshot of a condition of a stack before marking the stack and entering a new block; after entering a new block; and after exiting from the new block, respectively;  
  FIG. 5 is a flow diagram of the STK ADJ (1,1) operation of the present invention;  
  FIG. 6 is a flow diagram of the STK ADJ (0,0) opera tion of the present invention;  
  FIG. 7 is a flow diagram of the Mark Stack (MKS) operation of the present invention;  
  FIG. 8 is a flow diagram showing the manner in which the stack extension is flushed during execution of the ENTER operator;  
  FIG. 9 is a flow diagram of an operation called an :IIC transfer and shows the manner in which words in stack are transferred internally within the stack ex- :nsion memory;  
  FIG. I is a flow diagram of the operations involved I executing the EXIT and RETURN operators;  
  FIG. II is a flow diagram showing the manner in &#39;hich a parameter captured in a stack extension regis- :r is called to the top of the stack; and  
  FIG. 12 is a flow diagram showing the manner in &#39;hich the ADD operation is executed.  
 DESCRIPTION OF THE PREFERRED EMBODIMENT General Description Before considering the details of the construction nd operation of the preferred embodiment of the data rocessing system, consider first the general functions fits major components in connection with the block iagrams of FIGS. I and 2, and the format of the differnt types of words shown in FIG. 3.  
  A memory shown at 20 has a plurality of memory loations 22 and stores programs comprising executable trings of program operators; input data to be proessed; output data; and in addition, stores some of the itermediate results of processing in the form of a tack.  
  A stack organized data processor shown generally hroughout the rest of FIG. 1 processes data under conrol of the program strings. To that end, the processor ncludes a register for storing program operators during heir execution (P register 28), an arithmetic and logial unit (ALIS), and a conventional timing and control lnit (controller 40) which forms control signals to conrol the sequencing of micro-operations involved in excuting program operators.  
  The ALIS performs various arithmetic and logical iperaions such as adding, subtracting, and the like in manner well known in the computer art. A tutorial reatment of the construction and operation of a comiuter arithmetic and logical unit is given in a textbook ntitled Digital Computer Design Fundamentals. by K. Chu, published by the McGraw Hill Book Company, nc. in I962. The pertinent pages of this textbook are iages 363-368 and pages 430444.  
  A plurality of buses couple the data processor to nemory 20. Bus b6 carries address signals which idenify selected locations within memory 20; bus b carries nformation to be written into selected locations during vrite operations and carries information read out of seected locations during read operations; and bus ACR :arries control signals to initiate memory accesses and ndicate whether a read or a write cycle should be exe- :uted.  
  Display register memory 55 comprises a plurality of lisplay registers DO-DN (not individually shown) idenical in structure and function to the display registers lescribed in above-mentioned U.S. Pat. No. 3,548,384. Thus, display register 1 (D[l]) stores the base address if an array stored in memory 20. This array is called a egment dictionary and comprises a plurality of segnent descriptors. The format of a segment descriptor s shown in FIG. 3. A segment descriptor points to a lo- :ation in memory wherein the beginning of a code ,egment for a program block is stored.  
  Consider briefly the manner in which program code s read out of memory 20. The program code is partitioned into program segments. Each program segment has a base address and comprises a plurality of program operators which are addressable relative to its base address. The program operators have variable field length and are frequently packed together within a single location of memory 20. The segmentation of the program code is tied into the block structure of higher level languages. Thus an execution of the program changes from one block to another, there is a transfer of control from one program segment to another.  
  The display register D[1] a program dictionary register (PDR), a program base register (PBR), a program index register (PIR), and a program syllable register (PSR) (see 45 and combine to form a means for pointing to the program operator to be executed. The program pointing means employs the techniques of indirect addressing and relative addressing. To that end, an address adder 26 is provided for forming absolute addresses of memory 20 from a base address and an index.  
  As a preliminary matter, indirect addressing is used to locate the base address of a program segment. To that end, a segment descriptor is read out of memory 20 from an address calculated by address adder 26. The segment descriptor includes a field pointing to the base address ofa program segment which field is loaded into PBR. The address stored in PBR is updated each time control is transferred from one segment to another. During execution of a segment, sequential locations of main memory 20 are addressed relative to PBR. To that end, address adder 26 adds the contents of PBR and PIR to form an absolute address. After this absolute address has been calculated, controller 40 produces a fetch control signal (F) which is applied to gate 29 and a word is transferred from memory 20 throughgate 29 to P register 28. Since the word in P register 28 may contain more than one program operator, the PSR register 45 provides a means for identifying the program operator for execution.  
  The processor includes a stack extension memory within block 2 which is shown in more detail in FIG. 2. The stack extension memory comprises a plurality of stack extension registers SER30-0 through SER30-31 (not all shown). A bus b4 carries words being written into and read from the stack extension memory. A plurality of gates 93-0 through 93-31 selectively gate words carried by the b4 bus into respective stack extension registers. A plurality of gates 91-0 through 9l-3I selectively gate words out of respective stack extension registers to the b4 bus. A selection matrix (SM94) has a plurality of output lives (R0 through R31) coupled by lines not shown to gates 9I-0 through 9l-3I respectively. During an operation in which a word is read out of the stack extension memory, SM94 applies a control signal on one of its output lines to enable a selected one of gates 91-0 through 91-31 to apply a word from a stack extension register to the b4 bus. A selection matrix (SM95) has a plurality of output lines (W0 through W3I coupled by lines not shown to gates 930 through 93-31 respectively. During an operation in which a word is written into the stack extension memory, SM95 applies a control signal on one of its output lines to enable a selected one of gates 93-0 through 93-31 to load a word carried by the b4 bus into a stack extension register.  
  The stack extension memory includes two registers for storing addresses to select stack extension registers during read and write operations. SESA77 stores an address pointing to a stack extension register as a source of a word for application to the b4 bus. SEDASO stores an address pointing to a stack extension register as a destination for a word carried by the b4 bus. A third register TOSE74 also stores an address pointing to a stack extension register. The basic function ofTOSE74 is to point to the stack extension register storing the top of stack extension word. TOSE74 is a conventional up/- down counter composed of flip-flops. TOSE74 has a count up input (+1) and a count down input (l) and is responsive to control pulses applied to its inputs to increment and decrement the address it stores. TO- SE74 also has a set input (S) and is responsive to a con trol pulse applied thereto to set each of its internal flipflops to a &#39;1 state. When so set, TOSE74 stores the binary equivalent of decimal 31 and thereby points to SER30-3l.  
  An important feature of the stack extension memory is that it is programmatically addressable. That is. the program operator repertory includes operators containing addresses pointing to registers within the stack extension memory. For example, a value call operator which is described in more detail in connection with FIG. 11 contains an address couple field comprising an I! part and a 5 part. Controller 40 is operative to cause the transfer of the address couple field of such program operators to a C register 61. As will be explained in more detail hereafter. controller 40 is further operative to transfer the 6 part to SESA77 over a b30 bus connecting C register 61 to block 2. A 8 value stored in SE- SA77 is gated via gate 96 to SM94 to select one of the stack extension registers for readout. The 8 values 0 through 31 select registers SER30-0 through SER30-3l respectively.  
  The stack extension memory stores some of the intermediate results of processing in the form of a stack which is linked to the stack in memory 20 as an extension thereof. As will be explained in more detail hereafter, words are written into and read out ofthe stack extension memory in several distinguishable types of operations. In stack adjusting operations. words are pushed down and popped up on a last-in. first-out basisv In another type of operation words are written into and read from the stack extension memory on the basis of a selection made by a program operator. In still another type of operation words are flushed out ofthe stack extension memory and written into memory 20.  
  A register 10 and B register 12 provide temporary storage of words such as operands and control words of various types. Bus bl and bus b2 carry operands from A register 10 to B register 12 respectively to input cir cuits of ALIS and a bus b3 carries the output ofALlS back to A register 10.  
  As an example of the operation of ALIS, the execu tion of an ADD operator is described hereafter in connection with FIG. 11. During the ADD operation a first operand stored in A register 10 is added to a second operand stored in B register 12; the sum of the two operands then replaces the first operand and the second operand is disregarded. Thus the first and second operands are said to be combined or digested.  
  A register [0, B register 12, the stack extension memory within block 2, and a plurality of locations 22in the memory taken together form a stack storage means. The stack storage means provides for the storage of the record of execution ofa program in the form of a stack similar to the stack described above in connection with the discussion of US. Pat. No. 3.548.384. Thus the stack storage means stores the intermediate results accumulated during the execution of a plurality of pro gram blocks and stores the linking control words such as the MSCW and the RCW.  
  F register 52 stores an address of memory 20 and the address stored therein is continually updated so that it points to a memory location 22 for storing the MSCW for the program block having control of the processor.  
  During the execution of program code for an entered block. the data processor accumulates words in the stack storage means. The F register 52 is set to point to the memory location reserved for storing the MSCW for the program block having control of the processor. The stack extension location SER30-0 is associated with the memory location pointed to by the F register 52 to form a corresponding pair of locations reserved for storing the MSCW for the program block having control. Furthermore the stack extension locations SER30-l through SER30-3l are associated in one-to one correspondence with a group of 31 sequentially addressable memory locations above the memory location pointed to by F register 52 so as to define a plurality of corresponding pairs of locations. Each pair is reserved for storing a different stack word and has four occupancy conditions. Before the actual accumulation of the stack word for which the pair is reserved. the pair is in a first condition wherein both the extension location and the corresponding memory location are unoccupied. After actual accumulation. the pair is either in a second condition wherein only the extension is occupied, or in a third condition wherein only the memory location is occupied. or in a fourth condition wherein both locations are occupied. The data processor has means (described below) settable to indicate the occupancy condition for each corresponding pair.  
  A stack stored in the stack storage means has a top of stack word and has. during most stages of operation. a top of memory stack word. The top of stack word is the word which was most recently added to the stack and which has not yet been digested. The top of memory stack word is the word which was most recently pushed-down out of B register 12 and which has not yet been popped-up back into B register 12. During various stages of program execution the place where the top of stack word is located changes. The top of stack word can reside in A register 10, B register 12, the stack extension memory or memory 20.  
  The data processor includes means for indicating where the top of stack word resides. A register 10 includes a flip-flop identified as AROFll which indicates whether or not the top of stack word resides in A register 10. AROFll has an ARO output signal which is a l when the top of stack word resides in A register 10 and is a 0 otherwise. B register 12 includes a corre sponding flip-flop identified as BRO13 having a BRO output. When the top of stack word resides in B register 12, the BRO signal will be a l and the ARO signal will be a 0&#39;. A condition wherein both the ARO and BRO signals are O indicates that neither A register 10 nor B register 12 stores the top of stack word and that the top of stack word is stored either in the stack extension memory or memory 20.  
  An S register 24 (FIG. 1) and the top of stack extension pointer register TOSE74 and a stack extension overflow flip-flop SEOV82 (FIG. 2) combine to indiate where the top of memory stack word resides. It iould be noted that the top of memory stack word is ie top of stack word when A register and B register 2 are empty. S register 24 is a conventional up/down aunter storing an address of memory 20. S register 24 as a count up input (+1 I and a count down input (I) ad is responsive to control pulses applied to its inputs ither to increment or to decrement the address it ores. As will be described in more detail hereafter .mtrol pulses are applied to the inputs of S register 24 J update the address stored therein as the stack exands and contracts. During operations wherein a word popped-up from memory 20, the word is read out of ne ofthe memory locations 22 pointed to by S register 4 and then the address stored in S register 24 is decre- Iented. During operations wherein a word is pushedown into memory 20, the address stored in S register 4 is incremented and then the word is written into one fthe memory locations 22 pointed to by S register 24. EOVSZ has a set input and a reset input for receiving ontrol pulses which change its state. An SEOV signal roduced by SEOVBZ indicates whether or not the .ack has over-flowed out of the stack extension memry into the memory 20.  
  Before continuing with the description of the means )r indicating where the top of the memory stack word asides recall that each extension register is associated &#39;ith a different memory location 22 to form correnonding pairs. A particular one of the memory loca ons 22 can be reserved for storing the top of memory :ack word but the top of memory stack word will not ctually be stored therein. In this situation, the top of iemory stack word is actually stored in the stack ex- :nsion register corresponding to the particular memry location 22. Furthermore, a series of memory locaons 22 can be reserved for storing without actually Loring any stack words. This feature of the present inention arises because 5 register 24 is counted up each me a word is pushed down out of B register 12 even tough the word is pushed down into the stack extenlOll memory and not into memory 20. Consequently, iemory space in memory is reserved for possible iture storage of stack words residing in the stack ex znsion memory.  
  On the other hand, memory space in the stack extenion memory can be reserved for possible future storge of stack words residing in memory 20. This is an nportant feature ofthe present invention and leads to ie elimination of many time consuming accesses to 1emory20. As will be explained in more detail in conection with the sketches shown in FIG. 4 and the flow iagram shown in FIG. 10, memory space is reserved 1 the stack extension memory during the execution of re EXIT and RETURN operators. The RETURN oprator is inserted at the end of program blocks in the ature of procedures which return a value to another rogram block. The EXIT operator is inserted at the rid of a program string for other types of blocks.  
  Both the EXIT operator and the RETURN operator rder the data processor to start executing a different rogram block. By virtue of the nesting of program locks and the recursive use of procedures, execution f the EXIT and RETURN operators frequently cause &#39;ansfer of control to a program block which has parally been executed. Under these circumstances the itermediate results accumulated during the earlier artial execution of the block reside in memory 20. The  
 present invention includes means for reserving space in the stack extension memory for possible future storage of the last named intermediate results. In this connection. consider again FIG. 2.  
  Associated with the stack extension memory is an occupancy indicating means preferably comprising a plurality of flip-flops, OF-0 through OF 3l, (not all shown) each of which is associated with a different register (SER) of the stack extension memory. Each ofthe flip flops OF-0 through OF-31 assumes a I state to provide an indication that its associated register is occupied in that it stores a stack word, and assumes a 0 state to provide an indication that its associated register is empty or unoccupied in that it does not store such a stack word. The indications provided by the occupancy indicating means are coupled to controller 40 (shown in FIG. 1). The state of the occupancy indicating means is controlled by a plurality of gating networks -0 through 90-31. Each of the gating networks 90 is responsive to control signals formed by controller 40 to appropriately set and reset the occupancy indicating flip-flops.  
  While the invention is not limited thereto, preferably as indicated by FIG. 2, each of the registers SER30-0 through SER30-3l also has an associated flip-flop CF-0 through CF-3l. Each flip-flop CF-0 to CF-3I assumes a I state when the respective corresponding memory location 22 is occupied in that it stores a stack word and assumes a *0 state when the respective corre sponding memory location is unoccupied. The copy indicating means are useful in eliminating accesses to memory 20 during execution of an ENTER operator which indicates that a new program block is being entered.  
  Thus in the preferred embodiment, each extension register includes occupancy and copy indicating stor age cells having four states each indicating one of four possible occupancy conditions of a corresponding pair.  
  Consider again the means for indicating where the top of stack resides. When the top of stack word resides in A register 10, AROFll so indicates by producing a l as its ARO output signal (i.e., ARO I). When it resides in B register 12, AROFIl and BROFI3 so indicate by producing a 0 and a l as their ARO and BRO output signals (i.e. ARO O; BRO I). When it resides in the stack extension memory AROFll and BROF13 indicate that A register 10 and B register 12 are empty by producing O signals at their ARO and BRO outputs (i.e. ARO 0; BRO 0); SEOVSZ indicates that no overflow condition exists by producing a 0&#39; as its SEOV output signal (i.e., SEOV =0); TOSE74 points to the stack extension register storing the top of stack word; and the occupancy indicating flip-flop associated therewith produces a l as an output signal. The latter condition is symbolized as 0[TOSE] I. If the occupancy flip-flop is a 0 the stack extension memory does not contain the top of stack word OITOSE] O. The symbol C[TOSE] 1 indicates that the copy indicating flip-flop associated with the register storing the top of stack word is producing a l as an output signal. The fact that the top of stack word resides in memory 20 is indicated in any of the following three ways. First: ARO =0, BRO =0, SEOV IV In this first case. an overflow condition exists and S register 24 points to the location within memory 20 which actually stores the top of stack word. This condition is symbolized as {MISI} =top of stack word. Second: ARO O,  
 BRO 0, SEOV 0, lTOSE1= 0. and C[TOSE] I. In this second case. an overflow condition does not exist; however. a register within the stack extension memory has been reserved for storing but does not actually store the top of stack word. In this case the top of stack word is actually stored in memory at the located pointed to by S register 24. Third: ARO 0. BRO =0, SEOV=0, O[TOSE]= l, and C[TOSE] =1. In this third case the top of stack word actually resides in both memory 20 and the stack extension memory. Thus the top of stack word stored in the stack extension memory is said to be a copy of the top of stack word stored in memory 20.  
  The fact that a particular stack extension register is reserved for storing but does not actually store a stack word is indicated in the following manner. One. TO- SE74 points to the particular stack extension register or to any other stack extension register having a higher address. Two. the occupancy indicating flip-flop associated with the particular stack extension register prod acts a O as an output signal. It should be noted that stack extension registers having a higher address than the address stored in TOSE74 are merely reserved for future storage of words not yet accumulated. Consequently, the states of their occupancy and copy indicating flip-flops are not material.  
  A feature of the present invention resides in reserving a plurality of stack extension registers upon exiting from one block to another. As will be explained in more detail in connection with FIG. 10, all of the occupancy indicating flip-flops OF-0 through OF-3l are simultaneously reset upon such an exit. To that end. as shown in FIG. 2, there is provided a CLEAR input line which carries a signal formed by controller 40 for simultaneously resetting all of the occupancy indicating flip-flops. Also during such an exit, as explained hereafter, TOSE74 is set to point to a calculated address of the stack extension memory. By virtue of the setting of TOSE74 and the clearing of the occupancy indicating flip-flops memory space is reserved in the stack extension memory for possible future storage of stack words relating to the block exited to.  
  In concluding the general description of the preferred embodiment. reference is made again to FIGS. 1 and 2 for a description of the function of S Save register and FS register 71 respectively. S Save register 25 is a conventional counter register storing an address of memory 20 and having a count-up input, receiving control signals from controller 40 to increment the address stored therein by l. S Save register 25 comes into play in the event of an overflow of stack words out of a stack extension memory into memory 20. In such event controller 40 causes gate 69 to transfer the address stored in S register 24 into S Save register 25. The address so transferred is the address of the location of memory 20 used for storing the first word to overflow out of the stack extension memory. FS register 71 serves to save for later use an address of the stack ex tension memory. The address saved therein is the address wherein an IMSCW is stored during MKS operation.  
 GENERAL DESCRIPTION OF OPERATION The general operation of the data processing system is best understood after first considering the types of words stored in a stack. In general, these words are variables. reference words, and control words of vari ous types. FIG. 3 is a sketch which illustrates the word structure of the reference words and the control words used herein. Shown in FIG. 3 are an incomplete mark stack control word (IMSCW), a mark stack control word (MSCW), a program control word (PCW). a segment descriptor (SD). an indirect reference word (IRW). and a word from a program code segment containing a plurality of program operator syllables. Table I gives an explanation of the various symbols used to identify the fields within the words shown in FIG. 3.  
 TABLE I Symbol Description of Symhol Tag Identifies type of word.  
 DISP An increment value which when added to the absolute address contained in the BOSR register gives the address of an MSC&#39;W. This value is used to link the MSCWs together to form an address environment list.  
 DE A difference value indicating a stack depth; that is. the number of locations storing stack words accumulated during execution of a block. The address of the word in which this field is found minus this field gi\es the address of an MSCW. This value is used to link the MSCWs together to provide the stack history list.  
 &#34;.6 This is an address couple. The I! part is the Iexicographical level of a particular item and points to a particular displa register. The 8 part is an increment \alue or relative address. 8 can he added to the content of the display register pointed to b) II to produce a main memory address. 5 can also be used as a direct address of an item within the addressable stack extension.  
 SDI A segment descriptor index. This is a relative address pointing to a segment descriptor.  
 E An environment indicator. This is a one bit field indicating whether the word of which it is a part is an IMSCW or an MSCW.  
 ADDRESS A value contained in a segment descriptor which points to the beginning ol&#39;a program segment.  
 PIRPSR Values used for setting the FIR and PSR registers so that they point to the first program operator to be executed when control is transferred to a different program segment.  
 N A value identifying whether the processor should go into its normal or control state.  
 LL A value used for setting the LL register so that it indicates the lexicographical level of the program segment to which control is transferred.  
  FIG. 4 comprises FIGS. 4A, 4B. and 4C and. among other things. illustrates how the stack extension mem ory is linked to a stack in memory 20.  
  Briefly, FIG. 4 shows an example of the manner in which stack words are distributed between memory 20 and the stack extension memory at three different stages of a particular program. In this example. a program segment for a block referred to as block A has been partially executed. The program segment for block A has caused an entry into a program segment for a block referred to as block B. The program seg-