Patent Publication Number: US-6668305-B1

Title: Method and apparatus for the staggered startup of hard disk drives

Description:
COPYRIGHT NOTICE 
     Contained herein is material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction of the patent disclosure by any person as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all rights to the copyright whatsoever. 
     FIELD OF THE INVENTION 
     The present invention relates to computer systems; more particularly, the present invention relates to powering hard disk drives. 
     BACKGROUND 
     A hard disk drive (HDD) is a permanent storage device within a computer system that is used for data and the programs used to create the data. A HDD typically includes individual platters covered on both sides with a magnetic material. An HDD operates by writing small magnetic charges onto the surface of the disk platter. The platters spin at thousands of Revolution per Minute (RPM). Generally, a HDD requires in excess of two amperes (2 A) at 12 Vdc (or a 24 W power input) during the time the disk platter goes from zero RPM to its maximum RPM. The time required for a HDD to reach its maximum speed may take up to three seconds. 
     Ordinarily, the power supply for the computer system can easily manage the power requirements for starting a single HDD. However, in system applications where multiple HDDs are used, the power supply is typically designed to accommodate the startup of all HDDs at once. For example in a system employing four HDDs, it is necessary for the system power supply to be capable of managing in excess of 96 W (e.g., 24 W×4) of power at 12 Vdc. A power supply that is capable of handling such high power requirements is not cost effective for installation within a computer system. Therefore, a method to reduce the power needed to startup HDDs in a computer system is desired. 
     SUMMARY 
     According to one embodiment, a method and apparatus is disclosed for powering up hard disk drives. According to one embodiment, the method includes staggering the startup of hard disk drives (HDDs) in a computer system including a plurality of HDDs. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention. The drawings, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only. 
     FIG. 1 is a block diagram of one embodiment of a computer system; 
     FIG. 2 is a block diagram of one embodiment of interface drivers coupled to hard disk drives; and 
     FIG. 3 is a flow diagram of one embodiment for the staggered startup of hard disk drives. 
    
    
     DETAILED DESCRIPTION 
     A method and apparatus for starting hard disk drives is described. In the following detailed description of the present invention numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention. 
     Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. 
     FIG. 1 is a block diagram of one embodiment of a computer system  100 . According to one embodiment, computer system  100  comprises a server. Computer system  100  includes a central processing unit (processor)  105  coupled to processor bus  110 . In one embodiment, processor  105  is a processor in the Pentium® family of processors including the Pentium® II family and mobile Pentium® and Pentium® II processors available from Intel Corporation of Santa Clara, Calif. Alternatively, other processors may be used. Processor  105  may include a first level (L1) cache memory (not shown in FIG.  1 ). 
     In one embodiment, processor  105  is also coupled to cache memory  107 , which is a second level (L2) cache memory, via dedicated cache bus  102 . The L1 and L2 cache memories can also be integrated into a single device. Alternatively, cache memory  107  may be coupled to processor  105  by a shared bus. One of ordinary skill in the art will appreciate that cache memory  107  is optional and is not required for computer system  100 . 
     Chip set  120  is also coupled to processor bus  110 . Chip set  120  may include a memory controller for controlling a main memory  113 . Further, chip set  120  may be coupled to a video device  125  that handles video data requests to access main memory  113 . In one embodiment, video device  125  includes a video monitor such as a cathode ray tube (CRT) or liquid crystal display (LCD) and necessary support circuitry. 
     Main memory  113  is coupled to processor bus  110  through chip set  120 . Main memory  113  and cache memory  107  store sequences of instructions that are executed by processor  105 . The sequences of instructions executed by processor  105  may be retrieved from main memory  113 , cache memory  107 , or any other storage device. Additional devices may also be coupled to processor bus  110 , such as multiple processors and/or multiple main memory devices. Computer system  100  is described in terms of a single processor; however, multiple processors can be coupled to processor bus  110 . 
     Processor bus  110  is coupled to system bus  130  by chip set  120 . In one embodiment, system bus  130  is a Peripheral Component Interconnect (PCI) bus adhering to a Specification Revision 2.1 bus developed by the PCI Special Interest Group of Portland, Oreg.; however, other bus standards may also be used. Multiple devices, such as audio device  127 , may be coupled to system bus  130 . In addition, hard disk drive (HDD) interface devices (e.g., HDD interface  154  and HDD interface  156 ) may be coupled to system bus  130 . One of ordinary skill in the art will recognize that other quantities of HDD interfaces (e.g., 3, 4, 5, etc.) may be included within computer system  100 . 
     According to one embodiment, HDD interfaces  154  and  156  provide an interface between signals received in a format transmitted by system bus  130  to the HDD format of computer system  100 . In a further embodiment, HDD interfaces  154  and  156  have Integrated Drive Electronics (IDE) interfaces that convert received signals from a PCI configuration to an IDE format. FIG. 2 is a block diagram of one embodiment of HDD interfaces coupled to HDDs  251 - 254  via switches  221 - 224 . In particular, HDD interface  154  is coupled to switches  221  and  222 , which are in turn coupled to HDDs  251  and  252 , respectively. Similarly, HDD interface  156  is coupled to switches  223  and  224 , which are in turn coupled to HDDs  253  and  254 , respectively. 
     Switches  221 - 224  provide electrical power from a power supply (not shown) within computer system to each respective HDD drive. According to one embodiment, the switches provide “hot swap” capability that enables the HDD drives to be inserted into (and removed from) computer system  100  without computer system  100  having to be reset. HDDs  251 - 254  provide permanent storage area within computer system  100  that is used for data and the programs used to create the data. Each HDD includes individual platters covered on both sides with a magnetic material. HDDs  251 - 254  operate by writing small magnetic charges onto the surface of the disk platter. According to one embodiment, the platters within each HDD spin at thousands of Revolution per Minute (RPM). 
     According to one embodiment, HDDs  251 - 254  are IDE drives. IDE drives include controller electronics that are built into the HDD. According to one embodiment, each of HDDs  251 - 254  require in excess of two amperes (2 A) at 12 Vdc (or a 24 W power input) during the time the disk platter goes from zero RPM to its maximum RPM. Typically, the requisite time for the platters within each HDD to reach its maximum speed is three seconds. Upon computer system  100  startup, each of the HDDs  251 - 254  are also powered up. However, if HDDs  251 - 254  are started up simultaneously, the computer system  100  power supply must typically be capable of supplying in excess of 96 W (e.g., 24 W×4) of power at 12 Vdc. As described above, a power supply that is capable of handling such high power requirements is not cost effective for installation within computer system  100 . 
     According to one embodiment, the powering up of HDD drives  251 - 254  are staggered (or alternated) upon the startup of computer system  100 . In order to provide the staggered startup of HDDS  251 - 254 , programmable logic  260  is coupled to chipset  120  and HDD drives  251 - 254 . In one embodiment, programmable logic  260  receives signals from HDD interface  154  and HDD interface  156  via chipset  120  upon system startup. Upon receiving the signals from chipset  120 , programmable logic  260  transmits a RESET signal to each of the HDDs  251 - 254 . In particular, programmable logic  260  transmits RESET 1 -RESET 4  signals to HDDs  251 - 254 , respectively. In one embodiment, programmable logic  260  is a field programmable gate array (FPGA). However, one of ordinary skill in the art will appreciate that other programmable devices (e.g., a ROM, PAL, etc.) may be used to implement programmable logic  260 . 
     According to one embodiment, the RESET signal remains at a low logic level when power is initially applied to HDDs  251 - 254 . However, prior to the booting sequence of HDDs  251 - 254 , programmable logic  260  receives the signals from chipset  120 . Subsequently, the RESET signals are de-asserted (e.g., transition to a high logic level) one at a time. Once the last RESET signal has been de-activated, the booting sequence will begin. One of ordinary skill in the art will appreciate that the operation of the RESET signals could be reversed. For example, in other embodiments, the RESET signals may begin at a high logic level and later transition to a low logic level. 
     FIG. 3 is a flow diagram of one embodiment for the staggered startup of HDDs  251 - 254  at an HDD interface. At process block  310 , electrical power is received from the computer system  100  power supply (not shown) at HDDs  251 - 254 . As described above, a platter within an HDD will not immediately begin the spinning cycle upon being powered up. The spinning cycle will not begin as long as the RESET signal received from programmable logic  260  is asserted. At process block  320 , it is determined whether an HDD is detected at an HDD interface. If an HDD is detected, a signal is transmitted to programmable logic  260  at process block  330 . After the signal is transmitted to programmable logic  260 , control is returned to process block  320  where it is determined whether another HDD is detected. If so, control is returned to process block  330  where another signal is transmitted to programmable logic  260 . 
     The progression through process blocks  320  and  330  continues until all of the HDDs connected to the HDD interface has been detected. Note that in other embodiments, the HDD interface may detect all of the connected HDDs before transmitting a signal to programmable logic  260 . In such an embodiment, an encoded signal is transmitted to programmable logic  260  indicating which devices are connected. Note that the process blocks described (e.g., process blocks  310 - 330 ) above are implemented at each of the HDD interfaces  154  and  156 . 
     If it is determined that another HDD has not been detected at the HDD interface, programmable logic  260  de-asserts a RESET signal to the first indicated HDD, process block  340 . At process block  350 , the platter within the HDD begins spinning. At process block  360 , it is determined whether there is another HDD in which a RESET signal is to be de-asserted. If another RESET signal is to be de-asserted, control is returned to process block  340  where programmable logic  260  de-asserts a RESET signal to the next indicated HDD. Subsequently, control is returned to process block  350  where the platter within the next HDD begins spinning. According to one embodiment, the delay between activation of each HDD is four seconds. However, one of ordinary skill in the art will recognize that other delays may be implemented. The progression through process blocks  320  and  3340 - 360  continues until all of the RESET signals for detected devices have been de-asserted. 
     Staggering each HDD in computer system  100  helps to reduce the total power needed during the startup spinning cycle for all HDDs in computer system  100 . Reducing the power makes it possible for computer system  100  to use a more cost effective power supply. Moreover, less power consumed by HDD startup results in other components within computer system being able to share the same power outlet. 
     Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims which in themselves recite only those features regarded as the invention. 
     Thus, a method to reduce the power needed to startup HDDs in a computer system has been described.