Patent Publication Number: US-9853839-B2

Title: System, method and software program for tuneable equalizer adaptation using sample interpolation

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     In a conventional digital receiver system which samples data at a given BAUD rate (once per symbol transmission interval), there is no intermediate-time information available to adapt an analog continuous-time equalizer (“CTE”) and/or feed-forward equalizer (“FFE”) according to an optimal zero-force edge (“ZFE”) convergence (or lock) criterion. 
     Various embodiments of the present invention solve the problem of generating intermediate-time information useable to drive ZFE adaptation. Further, various embodiments of the present invention increase flexibility by enabling user-specified over-peaking and/or under-peaking (i.e. configurable equalizer tuning) with respect to the ZFE convergence (or lock) criterion. 
     Description of Related Art 
     T. Toifl et. al. (“Low Complexity Adaptive Equalization for High-Speed Chip-to-Chip Communication Paths by Zero-Forcing of Jitter Components”, IEEE Trans. Commun. vol. 54, no. 9, September 2006 pp. 1554-57) describes the basic concept of zero-forcing of jitter components by adapting a feed-forward equalizer. 
     This concept has also been applied to adapt both a receiver peaking amplifier (which realizes a similar function as an FFE postcursor) and FFE precursor(s)/postcursor(s) in analog input/output (“I/O”) core designs. In these analog designs, a dedicated “edge path” sampler is available which samples the “jitter component” or edge intersymbol interference (“ISI”). This edge ISI sample is missing in a digital I/O core (which samples only at the data sample point). 
     SUMMARY 
     As mentioned above, an edge ISI sample is missing in a digital I/O core. Various embodiments of the present invention overcome this problem by generating intermediate-time information useable to drive adaptation (e.g., continuous-time equalizer adaptation and/or feed-forward equalizer adaptation) in the context of a baud-rate sampled digital receiver. 
     In one embodiment, a system is provided, comprising: an analog continuous-time equalizer, the analog continuous-time equalizer being configured to obtain data in the form of an analog signal; an analog-to-digital converter in operative communication with the analog continuous-time equalizer, the analog-to-digital converter being configured to receive an output from the analog continuous-time equalizer; a feed-forward equalizer in operative communication with the analog-to-digital converter, the feed-forward equalizer being configured to receive an output from the analog-to-digital converter; a first buffer in operative communication with the feed-forward equalizer, the first buffer being configured to capture an output of the feed-forward equalizer; an interpolator in operative communication with the first buffer, the interpolator being configured to receive an output from the first buffer; a second buffer, the second buffer being configured to capture one of: (a) the output of the feed-forward equalizer via operative communication with the feed-forward equalizer; and (b) data based upon the output of the feed-forward equalizer; a zero-force edge calculator in operative communication with the interpolator, the second buffer and the analog continuous-time equalizer, the zero-force edge calculator being configured to receive an output from the interpolator and an output from the second buffer, the zero-force edge calculator being further configured to feed back continuous-time equalizer adaptation data to the analog continuous-time equalizer; wherein the continuous-time equalizer adaptation data fed back by the zero-force edge calculator to the analog continuous-time equalizer is based at least in part upon the output from the interpolator and the second buffer. 
     In another embodiment, a method is provided, comprising: receiving data in the form of an analog signal; applying the received data to an analog continuous-time equalizer process; applying an output of the analog continuous-time equalizer process to an analog-to-digital converter process; applying an output of the analog-to-digital converter process to a feed-forward equalizer process; capturing an output of the feed-forward equalizer process in a first buffer process; applying an output of the first buffer process to an interpolation process; capturing in a second buffer process one of: (a) an output of the feed-forward process; and (b) an output of another process based upon the output of the feed-forward process; applying an output of the interpolation process to a zero-force edge process; applying an output of the second buffer process to the zero-force edge process; and feeding back at least part of an output of the zero-force edge process to the analog continuous-time equalizer process. 
     In another embodiment, a computer-readable storage device is provided having stored thereon computer-readable instructions that, when executed by a computer, implement: receiving data in the form of an analog signal; applying the received data to an analog continuous-time equalizer process; applying an output of the analog continuous-time equalizer process to an analog-to-digital converter process; applying an output of the analog-to-digital converter process to a feed-forward equalizer process; capturing an output of the feed-forward equalizer process in a first buffer process; applying an output of the first buffer process to an interpolation process; capturing in a second buffer process one of: (a) an output of the feed-forward process; and (b) an output of another process based upon the output of the feed-forward process; applying an output of the interpolation process to a zero-force edge process; applying an output of the second buffer process to the zero-force edge process; and feeding back at least part of an output of the zero-force edge process to the analog continuous-time equalizer process. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The drawings are provided for illustrative purpose only and do not necessarily represent practical examples of the present invention to scale. 
         FIG. 1  shows a block diagram of a digital receiver system providing an example implementation according to an embodiment of the present invention. 
         FIG. 2A  shows a graph of an example fractional delay interpolator frequency response according to an embodiment of the present invention and  FIG. 2B  shows a corresponding example sixth order fractional delay interpolation polynomials used for the graph of  FIG. 2A . 
         FIGS. 3A and 3B  show a block diagram of a method according to an embodiment of the present invention. 
         FIG. 4  shows a block diagram of a digital receiver system providing an example implementation according to an embodiment of the present invention. 
         FIG. 5  shows a block diagram of a digital receiver system providing an example implementation according to an embodiment of the present invention. 
         FIG. 6  shows a graph with simulation results (illustrating the peaking amplifier setting found for both known-edge data (reference) and inventive interpolated-edge data). 
         FIG. 7  shows an example of a fractional delay interpolator polynomial lookup table according to an embodiment of the present invention. 
         FIG. 8  shows a block diagram of a digital receiver system providing an example implementation according to an embodiment of the present invention. 
         FIGS. 9A and 9B  show a block diagram of a method according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     One embodiment of the present invention relates to a system for tuneable equalizer adaptation using sample interpolation. Another embodiment of the present invention relates to a method for tuneable equalizer adaptation using sample interpolation. Another embodiment of the present invention relates to a software program for tuneable equalizer adaptation using sample interpolation. 
     Various embodiments of the present invention are based upon the observation that the zero-forcing of jitter components is equivalent to decorrelating ISI that arises from a data bit and appears at an edge crossover position at, for example, 1.5 unit intervals (“UI”) delayed (from the data bit). 
     In various embodiments, the intermediate sample position data at the 1.5 unit interval delay is estimated using interpolation polynomials applied to the sampled data (i.e., the received data after analog-to-digital conversion). The sampled data is measured at discrete unit intervals with a time period “T” corresponding to an ADC sample rate of FS=1.0/T samples/sec. 
     There are certain advantages to decorrelating 1.5 UI distant ISI computed by the interpolation polynomials. ISI added to the signal by the interpolation polynomials is reduced as the time delay of the ISI gets larger and larger—since the interpolation polynomial coefficients rapidly decay in magnitude beyond +−1 unit samples from the polynomial central delay. As a specific example to further illustrate this point, a first order linear interpolation polynomial has coefficients {0.5, 0.5} which achieve a central delay of 0.5 UI, and polynomial tap weights removed +−1 unit samples from this central delay are 0. In another specific example illustrating an improved accuracy interpolation polynomial over the first order interpolator, a 6 th  order interpolation polynomial targeting a design bandwidth of FS/3 at an interpolation delay of ½ UI is used. This design bandwidth (as opposed to a lower design bandwidth such as FS/4 or FS/8) reduces unwanted ISI contributed by the interpolation polynomials at the 1.5 UI distant delay while still being sufficiently lower than the Nyquist sample frequency of FS/2 to enable the design of an accurate 6 th  order interpolation polynomial. At smaller interpolation delays than 0.5 UI, it is possible to target greater than FS/3 design bandwidth while using a 6 th  order interpolation polynomial. In particular, the polynomials with very small interpolation delay from the digitized samples such as 1/32 UI may have an interpolation bandwidth approaching the Nyquist sample rate of FS/2 (as illustrated in  FIG. 2A , discussed in more detail below). 
     In one example, an array of interpolation polynomials is applied to vary the interpolation delay as a function of estimated edge delay from the digitized samples. In another example, tuneable peaking is achieved by offsetting the estimated edge delay (enabling a user to achieve more, less, or equivalent peaking compared to the zero-force edge convergence (or lock) criterion). 
     Referring now to  FIG. 1 , a block diagram of a digital receiver system providing an example implementation according to one embodiment of the present invention is shown. In this embodiment, baud-rate interpolation to support ZFE adaptation is provided (via creation of estimated edge samples that are used to drive ZFE adaptation of the CTE and FFE postcursor). Such baud-rate interpolation is sufficiently accurate when used in conjunction with ZFE since ZFE reacts to ISI at a 1.5 UI distant delay from source data as discussed above. As a result, a delay interpolator can be implemented with sufficient accuracy when driven off BAUD-rate sampled data (i.e., data that undergoes analog-to-digital conversion at the BAUD rate). 
     Still referring to  FIG. 1 , digital receiver  100  (which may be implemented, for example, as a dedicated integrated circuit (“IC”) chip, as a field-programmable gate array (“FPGA”), or as an application-specific integrated circuit (“ASIC”)) is provided. Digital receiver  100  includes receiver component (“RX”)  102 , which receives analog data and outputs the received analog data to CTE  104  (operating as a peaking amplifier). The CTE  104  then provides an output to analog-to-digital converter (“ADC”)  106 . The ADC in turn outputs digital data that drives FFE  108 . FFE  108  provides sequential output samples (e.g., 8-bit samples) that are periodically captured in snapshot buffer  110 . The samples in the snapshot buffer  110  are provided to interpolator  112 , which performs interpolation of the samples using optimal fractional delay interpolation polynomials. In one example, the fractional delay interpolation polynomials are designed for a flat frequency response from normalized frequency 0 to a minimum of FS/3 ( FIGS. 2A and 2B , described in more detail below, provide specific examples of such fractional delay interpolation polynomials). The interpolated samples (representing estimated “edge” information) are created in the interpolator  112  via application of the samples from the snapshot buffer  110  to the fractional delay interpolation polynomials. 
     Once each interpolated edge sample is computed, each interpolated edge sample is provided to ZFE  114 . Also provided to ZFE  114  are data values from snapshot buffer  116 , which receives at an input thereto the same sequential output samples from FFE  108  that are provided to snapshot buffer  110 . 
     Still referring to  FIG. 1 , it is noted that each interpolated edge sample (from interpolator  112 ) provided to ZFE  114  is decorrelated with 1.5 unit interval distant data (from snapshot buffer  116 ) according to a conventional ZFE convergence (or lock) criterion. Further, in one example, the adaptation accomplishes a joint equalization of the CTE and FFE by a two stage process as follows: (1) first adapting the CTE peaking setting until the CTE peaking setting converges to the ZFE convergence (or lock) criterion (i.e., edge ISI decorrelated from data bit 1.5 unit interval distant); and (2) next, the FFE postcursor is adapted to the ZFE convergence (or lock) criterion. Since the FFE normally has much finer resolution than the peaking amplifier, the second stage of ZFE lock on the FFE postcursor can be viewed as a fine tune equalization while the CTE can be viewed as a coarse tune equalization. 
     Referring now to  FIG. 2A , a graph  201  of an example fractional delay interpolator frequency response according to an embodiment of the present invention is shown (as seen, the x-axis of graph  201  is “Normalized Frequency” and the y-axis of graph  201  is “|H| (dB)”. Further,  FIG. 2B  shows a set  203  of corresponding example sixth order fractional delay interpolation polynomials used for the graph of  FIG. 2A . As seen in  FIG. 2B , the fractional delay interpolation polynomials of this example are 6th order, or 7 tap polynomials. In one specific example, 17 sets of fractional delay interpolation polynomials are used to form a range of fractional delays varying from 0 to 0.5 unit interval in steps of 1.0/32 unit interval. 
     The delay used on a given channel is in turn derived from an estimated edge location relative to the sampled data. The estimated edge location may be found by using a simple conventional closed-loop early/late phase detector apparatus of the type known in the art. In this approach, the polynomial interpolation delay is varied until a conventional early/late phase detector outputs an equal number of early/late determinations on average when provided the interpolated edge and detected data information. In an embodiment which uses a decision-feedback equalizer, the edge location may be estimated using an open-loop technique based on a first decision-feedback equalization tap value, which may be independently derived using a conventional technique. As an illustrative example, a first decision-feedback equalization tap may have a normalized value of 0, indicating an interpolation delay of 0.5 is needed to estimate the edge crossover, or a normalized value of 1.0, indicating an interpolation delay of 0 is needed to estimate edge crossover, or a normalized value between 0 and 1.0, indicating an interpolation delay between 0 to 0.5 is needed to estimate the edge crossover. A linear relationship of a first decision-feedback tap value “h1” to the edge delay can then be used to estimate the edge delay and subsequently select the appropriate interpolation polynomial corresponding to the estimated delay, specifically:
 
Estimated edge delay= h 1* k  
 
where constant “k” is chosen by the user to optimize the accuracy of the estimated edge delay.
 
     Referring now to  FIGS. 3A and 3B , a block diagram of a method according to an embodiment of the present invention is shown. As seen in these  FIGS. 3A and 3B , the method comprises: at block  301 —receiving data in the form of an analog signal; at block  303 —applying the received data to an analog continuous-time equalizer process; at block  305 —applying an output of the analog continuous-time equalizer process to an analog-to-digital converter process; at block  307 —applying an output of the analog-to-digital converter process to a feed-forward equalizer process; at block  309 —periodically capturing an output of the feed-forward equalizer process in a first buffer process; at block  311 —applying an output of the first buffer process to an interpolation process; at block  315 —periodically capturing an output of the feed-forward equalizer process in a second buffer process; at block  317 —applying an output of the interpolation process to a zero-force edge process; at block  319 —applying an output of the second buffer process to the zero-force edge process; at block  321 —feeding back an output of the zero-force edge process to the continuous-time equalizer process and the feed-forward equalizer process; at block  323 —changing at least one continuous-time equalizer characteristic of the continuous-time equalizer process based upon the output of the zero-force edge process that is fed back to the continuous-time equalizer process; and at block  325 —changing at least one feed-forward equalizer characteristic of the feed-forward equalizer process based upon the output of the zero-force edge process that is fed back to the feed-forward equalizer process. In one specific example, each of: the first buffer process of block  309  and the interpolation process of block  311  are carried out concurrently with the second buffer process of block  315  (wherein the ZFE process of blocks  317  and  319  operates on corresponding edge samples and data samples). 
     Referring now to  FIG. 4 , a block diagram of a digital receiver system providing an example implementation according to an embodiment of the present invention is shown. As seen in this  FIG. 4 , integrated circuit (“IC”)  401  receives input analog data (such as the type of analog data received by RX  102  of  FIG. 1 ) and provides output data. In one specific example, integrated circuit  401  may be configured to operate by implementing elements of the type described in connection with  FIG. 1 . In another specific example, integrated circuit  401  may include firmware  401 A. In another specific example, integrated circuit  401  may receive user input. (e.g., via keyboard, mouse, and/or any other appropriate user interface (e.g., graphical user interface associated with a display)). Such user input may permit the user to vary the interpolator delay offset (thus enabling the user to achieve more or less peaking than the standard ZFE algorithm would provide, as discussed in more detail below). 
     Referring now to  FIG. 5 , a block diagram of a digital receiver system providing an example implementation according to an embodiment of the present invention is shown. As seen in this  FIG. 5 , computer  501  receives input analog data (such as the type of analog data received by RX  102  of  FIG. 1 ) and provides output data. In one specific example, computer  501  may be configured to operate by implementing elements of the type described in connection with  FIG. 1 . In another specific example, computer  501  may include processor (e.g., CPU)  501 A and memory  501 B (which operatively communicate). Memory  501 B may be a computer-readable medium including computer-readable instructions (or processor-readable instructions) that, when executed by processor  501 A implement the required functionality. In another specific example, memory  501 B may be a hardware device (such as a solid-state memory or an optical memory device or a magnetic memory device). In another specific example, computer  501  may receive user input (e.g., via keyboard, mouse, and/or any other appropriate user interface (e.g., graphical user interface associated with a display)). Again, user input may permit the user to vary the interpolator delay offset (thus enabling the user to achieve more or less peaking than the standard ZFE algorithm would provide, as discussed in more detail below). Further, the computer  501  may provide output to (and/or receive back input from) one or more of a display and/or a printer. 
     Referring now to  FIG. 6 , a graph  601  of Zero-Force Equalizer CTE Lock vs Channel Loss showing simulation results (illustrating the peaking amplifier setting found for both known-edge data (reference) and inventive interpolated-edge data) is provided. As seen, the x-axis of Graph  601  is Channel Loss and the y-axis of graph  601  is ZFE Lock Step (1 . . . 12). The trace labeled as “A” is the Reference (ideal edge), the trace labeled as “B” is Interpolation (no delay offset) and the trace labeled as “C” is Interpolation (delay offset 2/32 unit interval). In this example, use of the interpolated values resulted in approximately 2 dB less applied peaking compared to the known-edge solution. This bias may be addressed by offsetting the estimated edge location interpolator delay by 2/32 unit interval. This results in similar peaking (within +−1 peaking amplifier step, or approximately +−1 dB accuracy in this example) found for both known-edge and interpolated-edge techniques. 
     As described herein, a dynamic peaking control (“DPC”) using a zero-force edge mechanism which attempts to minimize ISI at the EDGE location is provided. The zero-force edge algorithm uses both DATA and EDGE samples. However, the sampling system only captures DATA samples. The EDGE samples are computed using an interpolation function which is modeled, in one specific example, as a 6 th  order polynomial: 
               EDGE   ⁡     [   n   ]       =       ∑     i   =   0     6     ⁢       INT   ⁡     [   i   ]       ·     S   ⁡     [     i   +   n   -   4     ]                 
where n is valid (in this example) from 3 to 12 with a 16 sample size (0:15) snapshot capture. The coefficient values for the interpolation (in this example) are shown as INT[i] in the fractional interpolator polynomial lookup table  701  of  FIG. 7 , where various delays are created.
 
     Referring now to  FIG. 8 , a block diagram of a digital receiver system providing an example implementation according to one embodiment of the present invention is shown. This embodiment is similar to the embodiment of  FIG. 1 , with the addition of decision-feedback equalizer (“DFE”)  818 . This embodiment of  FIG. 8  otherwise operates in a similar manner to the embodiment of  FIG. 1 . More particularly, this embodiment of  FIG. 8  utilizes digital receiver  800  (which may be implemented, for example, as a dedicated IC chip, as a FPGA, or as an ASIC). Digital receiver  800  includes receiver component (“RX”)  802 , which receives analog data and outputs the received analog data to CTE  804  (operating as a peaking amplifier). The CTE  804  then provides an output to ADC  806 . The ADC in turn outputs digital data that drives FFE  808 . FFE  808  provides sequential output samples (e.g., 8-bit samples) that are periodically captured in snapshot buffer  810 . The samples in the snapshot buffer  810  are provided to interpolator  812 , which performs interpolation of the samples using optimal fractional delay interpolation polynomials. 
     Once each interpolated edge sample is computed, each interpolated edge sample is provided to ZFE  814 . Also provided to ZFE  814  are data values from snapshot buffer  816  (snapshot buffer  816  is fed data values from DFE  818 , which receives at an input thereto the same sequential output samples from FFE  808  that are provided to snapshot buffer  810 ). 
     Referring now to  FIGS. 9A and 9B , a block diagram of a method according to an embodiment of the present invention is shown. As seen in these  FIGS. 9A and 9B , the method comprises: at block  901 —receiving data in the form of an analog signal; at block  903 —applying the received data to an analog continuous-time equalizer process; at block  905 —applying an output of the analog continuous-time equalizer process to an analog-to-digital converter process; at block  907 —applying an output of the analog-to-digital converter process to a feed-forward equalizer process; at block  909 —periodically capturing an output of the feed-forward equalizer process in a first buffer process; at block  911 —applying an output of the first buffer process to an interpolation process; at block  913 —applying the output of the feed-forward equalizer process to a decision-feedback equalizer process; at block  915 —periodically capturing an output of the decision-feedback equalizer process in a second buffer process; at block  917 —applying an output of the interpolation process to a zero-force edge process; at block  919 —applying an output of the second buffer process to the zero-force edge process; at block  921 —feeding back an output of the zero-force edge process to the continuous-time equalizer process and the feed-forward equalizer process; at block  923 —changing at least one continuous-time equalizer characteristic of the continuous-time equalizer process based upon the output of the zero-force edge process that is fed back to the continuous-time equalizer process; and at block  925 —changing at least one feed-forward equalizer characteristic of the feed-forward equalizer process based upon the output of the zero-force edge process that is fed back to the feed-forward equalizer process. In one specific example, each of: the first buffer process of block  909  and the interpolation process of block  911  are carried out concurrently with the DFE process of block  913  and the second buffer process of block  915  (wherein the ZFE process of blocks  917  and  919  operates on corresponding edge samples and data samples. 
     In one specific example, FFE output samples are followed by a DFE of arbitrary length. In another specific example, FFE output samples are followed by a maximum-likelihood sequence estimator (“MLSE”), which may be used to replace a DFE function in some receiver embodiments. 
     Further, various embodiments of the present invention add a new dimension of flexibility, beyond the conventional ZFE adaptation algorithm (which is typically only capable of finding a peaking setting which decorrelates edge ISI), by varying the interpolator delay offset (thus enabling a user to achieve more or less peaking than the standard ZFE algorithm would provide). The extra flexibility of such embodiments of the present invention may provide enhanced performance under certain channel conditions (e.g., where either more or less peaking than conventional ZFE would normally provide gives better system performance). 
     As described herein, baud-rate interpolation is shown capable of driving ZFE adaptation to within ˜+−1 db of peaking accuracy using 6th order polynomial interpolators, on channels ranging from 10 dB loss to 35 dB loss, over 0 to 0.5 unit interval interpolation delay. In one example, lower loss channels most likely will not occur since the receiver frontend (in this example) will be intentionally bandwidth limited on low loss channels to support baud-rate clock and data recovery (“CDR”) operation, which typically requires bandwidth limit in the channel to function correctly. 
     In another example, the interpolation polynomials could be useable to drive a dynamic-data centering (“DDC”) algorithm with an early/late scan-out of approximately +−0.125 unit interval from each sample point. In such an algorithm, a time offset data sample is estimated using the interpolation polynomials instead of an edge sample. A control method can then compare the early/late interpolated data samples with the sampled data to make a determination of proper sample timing and adjust sample timing appropriately earlier or later to achieve a desired centered sample point using conventional methods known in the art. 
     As described herein, various embodiments may be implemented in software, firmware, hardware or any combination thereof. In one specific example, the firmware may be associated with a hardware device that can be programmed to change the configuration of the device (e.g., an FPGA, or an ASIC). 
     In another example, the physical implementations and methods described herein may be applied to embedded and/or real-time applications. 
     As described herein, various embodiments may be used in the context of analog, mixed signal design and communications technologies. 
     As described herein, various embodiments may utilize at least some level of anti-aliasing filter (lowpass filtering) prior to the ADC. Typically the application channel, receiver electronics, and CTE provide automatically lowpass filtering of sufficient value. In one specific example, an embodiment of the present invention provides a digital receiver that adds a “bandwidth limit” function in the receiver front-end to provide sufficient lowpass filtering so that a baud-rate CDR can work reliably. This “bandwidth limit” function also increases the accuracy of the polynomial interpolation, such that in a practical application of a digital receiver there will always be sufficient anti-aliasing in front of the ADC so the interpolation polynomials can generate sufficiently accurate results to drive the peaking amplifier and FFE adaptation (in one specific example, “infinite bandwidth” data could not be utilized). 
     As described herein, a method is provided for receiving data in the form of an analog signal; performing an analog continuous-time equalizer process on the received data; performing an analog-to-digital converter process on an output of the analog continuous-time equalizer process; performing a feed-forward equalizer process on an output of the analog-to-digital converter process; periodically capturing, in a first buffer process, an output of the feed-forward equalizer process; performing an interpolation process on an output of the first buffer process; performing a decision-feedback equalizer process on the output of the feed-forward equalizer process; periodically capturing in a second buffer process an output of the decision-feedback equalizer process; performing a zero-force edge process on: (a) an output of the interpolation process and (b) an output of the second buffer process; and feeding back an output of the zero-force edge process to: (a) the analog continuous-time equalizer process and (b) the feed-forward equalizer process. 
     Various mechanisms may be employed to determine which interpolation delay polynomial to use to compute the interpolated edge. In one example, a conventional technique called an “early/late” phase detector can be used to correlate the interpolated edge with decoded data to find the appropriate interpolation polynomial. Of course, any other appropriate technique may be used to determine which interpolation delay polynomial to use to compute the interpolated edge, such as the open loop estimation method based on a first decision-feedback tap value, etc. 
     In one embodiment, the FFE is limited to a single postcursor. In another embodiment, a feed-forward equalizer with two or more postcursors (“FFE2+”) may be provided where a control method first adapts the peaking amplifier (or CTE), and then adapts the feed-forward equalizer by changing a first tap of the feed-forward equalizer (with the FFE adaptation limited to a single postcursor). This example then shuts off the interpolator-based peaking amplifier/FFE first tap adaptation while the method adaptively equalizes one or more remaining FFE taps (i.e., one or more taps subsequent to the first tap). 
     In another embodiment, adaptation may be provided to one or more FFE precursor taps (in one specific example, interaction with a common baud-rate clock recovery technique may prohibit adaptation of the first precursor, but a second precursor could be adapted). 
     In another embodiment a device (e.g., an IC, an FPGA, or an ASIC) may be configured to carry out any process or processes disclosed herein. 
     In another embodiment, a system is provided, comprising: an analog continuous-time equalizer, the analog continuous-time equalizer being configured to obtain data in the form of an analog signal; an analog-to-digital converter in operative communication with the analog continuous-time equalizer, the analog-to-digital converter being configured to receive an output from the analog continuous-time equalizer; a feed-forward equalizer in operative communication with the analog-to-digital converter, the feed-forward equalizer being configured to receive an output from the analog-to-digital converter; a first buffer in operative communication with the feed-forward equalizer, the first buffer being configured to capture an output of the feed-forward equalizer; an interpolator in operative communication with the first buffer, the interpolator being configured to receive an output from the first buffer; a second buffer, the second buffer being configured to capture one of: (a) the output of the feed-forward equalizer via operative communication with the feed-forward equalizer; and (b) data based upon the output of the feed-forward equalizer; a zero-force edge calculator in operative communication with the interpolator, the second buffer and the analog continuous-time equalizer, the zero-force edge calculator being configured to receive an output from the interpolator and an output from the second buffer, the zero-force edge calculator being further configured to feed back continuous-time equalizer adaptation data to the analog continuous-time equalizer; wherein the continuous-time equalizer adaptation data fed back by the zero-force edge calculator to the analog continuous-time equalizer is based at least in part upon the output from the interpolator and the second buffer. 
     In one example, the system further comprises a decision-feedback equalizer, the decision-feedback equalizer being in operative communication with the feed-forward equalizer and the second buffer, the decision-feedback equalizer being configured to receive the output of the feed-forward equalizer and provide to the second buffer the data based upon the output of the feed-forward equalizer. 
     In another example, the system comprises an integrated circuit, and each of the analog continuous-time equalizer, the analog-to-digital converter, the feed-forward equalizer, the first buffer, the interpolator, the decision-feedback equalizer, the second buffer, and the zero-force edge calculator comprises hardware of the integrated circuit. 
     In another example, the integrated circuit comprises one of an FPGA and an ASIC. 
     In another example, the system further comprises: a processor comprising hardware; and a memory storing computer-readable instructions that, when executed by the processor, implement each of the analog continuous-time equalizer, the analog-to-digital converter, the feed-forward equalizer, the first buffer, the interpolator, the decision-feedback equalizer, the second buffer, and the zero-force edge calculator comprises hardware of the integrated circuit. 
     In another example, the system further comprises a receiver component, the receiver component being configured to receive data from outside of the system and to provide the received data to the analog continuous-time equalizer. 
     In another example, the system comprises an integrated circuit, and the receiver comprises hardware of the integrated circuit. 
     In another example, the analog continuous-time equalizer is further configured to perform a peaking amplifier process. 
     In another example, the output of the feed-forward equalizer is data in the form of sequential output samples. 
     In another example, the interpolator is further configured to use a plurality of optimal fractional delay interpolation polynomials. 
     In another example, at least one continuous-time equalizer characteristic of the analog continuous-time equalizer is changed based upon the continuous-time equalizer adaptation data that is fed back to the analog continuous-time equalizer. 
     In another example: the zero-force edge calculator is in operative communication with the feed-forward equalizer and the zero-force edge calculator is further configured to feed back feed-forward equalizer adaptation data to the feed-forward equalizer; the feed-forward equalizer adaptation data fed back by the zero-force edge calculator to the feed-forward equalizer is based at least in part upon the output from the interpolator and the second buffer; and at least one feed-forward equalizer characteristic of the feed-forward equalizer is changed based upon the feed-forward equalizer adaptation data that is fed back to the feed-forward equalizer. 
     In another embodiment, a method is provided, comprising: receiving data in the form of an analog signal; applying the received data to an analog continuous-time equalizer process; applying an output of the analog continuous-time equalizer process to an analog-to-digital converter process; applying an output of the analog-to-digital converter process to a feed-forward equalizer process; capturing an output of the feed-forward equalizer process in a first buffer process; applying an output of the first buffer process to an interpolation process; capturing in a second buffer process one of: (a) an output of the feed-forward process; and (b) an output of another process based upon the output of the feed-forward process; applying an output of the interpolation process to a zero-force edge process; applying an output of the second buffer process to the zero-force edge process; and feeding back at least part of an output of the zero-force edge process to the analog continuous-time equalizer process. 
     In one example, the method further comprises a decision-feedback equalizer process, the decision-feedback equalizer process being the other process such that the decision-feedback equalizer process receives the output of the feed-forward equalizer process and provides an output to the second buffer process based upon the output of the feed-forward process. 
     In another example, the method further comprises: feeding back at least part of the output of the zero-force edge process to the feed-forward equalizer process; changing at least one continuous-time equalizer characteristic of the analog continuous-time equalizer process based upon the output of the zero-force edge process that is fed back to the analog continuous-time equalizer process; and changing at least one feed-forward equalizer characteristic of the feed-forward equalizer process based upon the output of the zero-force edge process that is fed back to the feed-forward equalizer process. 
     In another example, the method further comprises: feeding back at least part of the output of the zero-force edge process to the feed-forward equalizer process; first changing at least one continuous-time equalizer characteristic of the analog continuous-time equalizer process based upon the output of the zero-force edge process that is fed back to the analog continuous-time equalizer process; then changing a value associated with a first tap of the feed-forward equalizer process; and then changing one or more values associated with one or more respective one or more subsequent taps of the feed-forward equalizer process without further changing the at least one continuous-time equalizer characteristic and without further changing the value associated with the first tap of the feed-forward equalizer process, wherein the changing of the one or more values associated with the one or more respective one or more subsequent taps of the feed-forward equalizer process is not responsive to the output of the zero-force edge process. 
     In another embodiment, a computer-readable storage device is provided having stored thereon computer-readable instructions that, when executed by a computer, implement: receiving data in the form of an analog signal; applying the received data to an analog continuous-time equalizer process; applying an output of the analog continuous-time equalizer process to an analog-to-digital converter process; applying an output of the analog-to-digital converter process to a feed-forward equalizer process; capturing an output of the feed-forward equalizer process in a first buffer process; applying an output of the first buffer process to an interpolation process; capturing in a second buffer process one of: (a) an output of the feed-forward process; and (b) an output of another process based upon the output of the feed-forward process; applying an output of the interpolation process to a zero-force edge process; applying an output of the second buffer process to the zero-force edge process; and feeding back at least part of an output of the zero-force edge process to the analog continuous-time equalizer process. 
     In one example, the computer-readable instructions, when executed by the computer, further implement a decision-feedback equalizer process, the decision-feedback equalizer process being the other process such that the decision-feedback equalizer process receives the output of the feed-forward equalizer process and provides an output to the second buffer process based upon the output of the feed-forward process. 
     In another example, the computer-readable instructions, when executed by the computer, further implement: feeding back at least part of the output of the zero-force edge process to the feed-forward equalizer process; changing at least one continuous-time equalizer characteristic of the analog continuous-time equalizer process based upon the output of the zero-force edge process that is fed back to the analog continuous-time equalizer process; and changing at least one feed-forward equalizer characteristic of the feed-forward equalizer process based upon the output of the zero-force edge process that is fed back to the feed-forward equalizer process. 
     In another example, the computer-readable instructions, when executed by the computer, further implement: feeding back at least part of the output of the zero-force edge process to the feed-forward equalizer process; first changing at least one continuous-time equalizer characteristic of the analog continuous-time equalizer process based upon the output of the zero-force edge process that is fed back to the analog continuous-time equalizer process; then changing a value associated with a first tap of the feed-forward equalizer process; and then changing one or more values associated with one or more respective one or more subsequent taps of the feed-forward equalizer process without further changing the at least one continuous-time equalizer characteristic and without further changing the value associated with the first tap of the feed-forward equalizer process, wherein the changing of the one or more values associated with the one or more respective one or more subsequent taps of the feed-forward equalizer process is not responsive to the output of the zero-force edge process. 
     In another example, any steps described herein may be carried out in any desired appropriate order. 
     While the present invention has been shown and described with respect to various embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims. In addition, all of the examples disclosed herein are intended to be illustrative, and not restrictive.