Patent Publication Number: US-7710092-B2

Title: Self tracking ADC for digital power supply control systems

Description:
RELATED APPLICATION DATA 
     This application is a continuation-in-part of application Ser. No. 11/349,853, filed Feb. 7, 2006 now U.S. Pat. No. 7,315,157, for ADC TRANSFER FUNCTION PROVIDING IMPROVED DYNAMIC REGULATION IN A SWITCHED MODE POWER SUPPLY, which was a continuation of application Ser. No. 10/779,475, filed Feb. 12, 2004, now issued as U.S. Pat. No. 7,023,190 on Apr. 4, 2006, which was in turn a continuation-in-part of application Ser. No. 10/361,667, filed Feb. 10, 2003 now U.S. Pat. No. 6,933,709, for DIGITAL CONTROL SYSTEM AND METHOD FOR SWITCHED MODE POWER SUPPLY. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to power supply circuits, and more particularly to digital control systems and methods for switched mode power supply circuits. 
     2. Description of Related Art 
     Switched mode power supplies are known in the art to convert an available direct current (DC) or alternating current (AC) level voltage to another DC level voltage. A buck converter is one particular type of switched mode power supply that provides a regulated DC output voltage to a load by selectively storing energy in an output inductor coupled to the load by switching the flow of current into the output inductor. It includes two power switches that are typically provided by MOSFET transistors. A filter capacitor coupled in parallel with the load reduces ripple of the output current. A pulse width modulation (PWM) control circuit is used to control the gating of the power switches in an alternating manner to control the flow of current in the output inductor. The PWM control circuit uses signals communicated via a feedback loop reflecting the output voltage and/or current level to adjust the duty cycle applied to the power switches in response to changing load conditions. 
     Conventional PWM control circuits are constructed using analog circuit components, such as operational amplifiers, comparators and passive components like resistors and capacitors for loop compensation, and some digital circuit components like logic gates and flip-flops. But, it is desirable to use entirely digital circuitry instead of the analog circuit components since digital circuitry takes up less physical space, draws less power, and allows the implementation of programmability features or adaptive control techniques. A conventional digital control circuit includes an analog-to-digital converter (ADC) that converts an error signal representing the difference between a signal to be controlled (e.g., output voltage (V o )) and a reference into a digital signal having n bits. The digital control circuit uses the digital error signal to control a digital pulse width modulator, which provides control signals to the power switches having a duty cycle such that the output value of the power supply tracks the reference. In order to keep the complexity of the PWM control circuit low, it is desirable to hold the number of bits of the digital signal to a small number. At the same time, however, the number of bits of the digital signal needs to be sufficiently high to provide resolution good enough to secure precise control of the output value. Moreover, the ADC needs to be very fast to respond to changing load conditions. Current microprocessors exhibit supply current slew rates of up to 20 A/μs, and future microprocessors are expected to reach slew rates greater than 350 A/μs, thereby demanding extremely fast response by the power supply. 
     Single stage (i.e., flash) ADC topologies are utilized in power supply control circuit applications since they have very low latency (i.e., overall delay between input and output for a particular sample). If a standard flash ADC device is used to quantize the full range of regulator output voltage with desired resolution (e.g., 5 mV), the device will necessarily require a large number of comparators that will dissipate an undesirable amount of power. Under normal operation, the output voltage V o  of the regulator remains within a small window, which means that the ADC need not have a high resolution over the entire range. Accordingly, a “windowed” ADC topology permits high resolution over a relatively small voltage range tracked by a reference voltage (V ref ). Since the quantization window tracks the reference voltage V ref , the signal produced by the ADC will be the voltage error signal. Thus, the windowed ADC provides the dual functions of the ADC and error amplifier, resulting in a further reduction of components and associated power dissipation. 
     Notwithstanding these advantages, a drawback with the windowed ADC topology is that the device can go into saturation due to transient load conditions that cause the window ranges to be exceeded. By way of example, a 4-bit windowed ADC has a least significant bit (LSB) resolution of roughly 5 mV. This means that an output voltage error of as low as ±40 mV pushes the ADC into saturation. The ADC would then continue to reflect the same error signal (i.e., maximum) even though the actual error could grow even larger, referred to as a “windup” condition of the digital control system. The reaction of the feedback loop in this windup condition can be difficult to predict, since without accurate information about the error size the digital control system no longer functions as a linear system. This behavior can be particularly harmful, since it can damage the load due to overcurrent and/or overvoltage, and can also damage the power supply itself. 
     Another disadvantage of the ADC is that it digitizes only the loop error. There is therefore no digital representation of the absolute output voltage (V o ). In order to monitor the power supply and the feedback loop it is very often necessary to add other supervisory circuits to provide functions such as under-voltage protection, Power-Good-Low monitor, Power-Good-High monitor, and over-voltage protection. Since the voltage thresholds monitored by those supervisory circuits are usually not within the range of the ADC circuit, additional analog comparators together with analog voltage thresholds would be necessary. This is not economical and is very often not very accurate. 
     It would therefore be advantageous to have an ADC circuit that provides a digital representation of a parameter that needs to be regulated (e.g., the absolute output voltage of a power supply), so that any additional monitoring and supervisory circuits could be implemented as full digital circuits. Furthermore, it would be advantageous to provide an ADC circuit having high resolution around the steady state operating point of the power supply, but that can also settle quickly to a new operating point. 
     SUMMARY OF THE INVENTION 
     The present invention provides a self-tracking analog-to-digital converter (ADC) for use in applications such as in a switched mode power supply. The self-tracking ADC overcomes the disadvantages of the prior art by providing a digital representation of a parameter under regulation (e.g., the absolute output voltage of a power supply), thereby enabling any additional monitoring and supervisory circuits to be implemented as full digital circuits. 
     In an embodiment of the invention, a self-tracking analog-to-digital converter includes a digital-to-analog converter (DAC) adapted to provide a variable reference voltage, a windowed flash analog-to-digital converter (ADC) adapted to provide an error signal e k  corresponding to a difference between an input voltage V i  and the variable reference voltage, and digital circuitry adapted to generate suitable control signals for the DAC based on the error signal e k . More particularly, the digital circuitry includes a first digital circuit adapted to provide a first function value f(e k ) in response to the error signal e k , the first function value f(e k ) representing an amount of correction to be applied to the variable reference voltage. A second digital circuit is adapted to provide a counter that combines the first function value f(e k ) with a previous counter state N k  to provide a next counter state N k+1 , the next counter state N k+1  being applied as an input to the digital-to-analog converter. A third digital circuit is adapted to scale the previous counter state N k  by a factor M and combine the scaled counter state M·N k  with the error signal e k  to provide a digital output value D k  representing the input voltage V i . 
     In another embodiment of the invention, a switched mode power supply comprises at least one power switch adapted to convey power between input and output terminals of the power supply, and a digital controller adapted to control operation of the at least one power switch responsive to an output measurement of the power supply. The digital controller includes the self-tracking analog-to-digital converter, a digital filter providing a digital control output based on a difference between a digital output of the self-tracking analog-to-digital converter and a reference value, and a digital pulse width modulator providing a control signal to the at least one power switch. The self-tracking analog to digital converter comprises a digital-to-analog converter (DAC) adapted to provide a variable reference voltage, a windowed flash analog-to-digital converter (ADC) adapted to provide an error signal e k  corresponding to a difference between the output measurement and the variable reference voltage, a first digital circuit adapted to generate a first function value f(e k ) in response to the error signal e k , the first function value f(e k ) representing an amount of correction to be applied to the variable reference voltage, a second digital circuit adapted to provide a counter that combines the first function value f(e k ) with a previous counter state N k  to provide a next counter state N k+1 , the next counter state N k+1  being applied as an input to the DAC, and a third digital circuit adapted to scale the previous counter state N k  by a factor M and combine the scaled counter state M·N k  with the error signal e k  to provide a digital output value D k  representing the output measurement. 
     A more complete understanding of the self-tracking ADC for use in a switched mode power supply will be afforded to those skilled in the art, as well as a realization of additional advantages and objects thereof, by a consideration of the following detailed description of the preferred embodiment. Reference will be made to the appended sheets of drawings, which will first be described briefly. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts a switched mode power supply having a digital control circuit; 
         FIG. 2  depicts a windowed flash ADC that provides high and low saturation signals; 
         FIG. 3  depicts a digital controller having an infinite impulse response filter and error controller; 
         FIG. 4  is a graph depicting a linear ADC transfer function; 
         FIG. 5  is a graph depicting a linear ADC transfer function with an increased step size at the window boundaries in accordance with an embodiment of the invention; 
         FIG. 6  is a graph depicting a non-linear ADC transfer function with increased step size and increased gain at the window boundaries in accordance with another embodiment of the invention; 
         FIG. 7  is a block diagram of a self-tracking ADC in accordance with an embodiment of the invention; 
         FIG. 8  graphically illustrates a range of exemplary comparator thresholds for the self-tracking ADC of  FIG. 7 ; 
         FIG. 9  is a block diagram of a self-tracking ADC in accordance with another embodiment of the invention; 
         FIG. 10  graphically illustrates a range of exemplary comparator thresholds for the self-tracking ADC of  FIG. 9 ; 
         FIG. 11  graphically illustrates a range of exemplary comparator thresholds for an alternative embodiment of the self-tracking ADC that avoids limit cycle oscillations; and 
         FIG. 12  depicts a switched mode power supply having a digital control circuit that includes a self-tracking ADC. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention provides a method for digitally controlling a switched mode power supply. More specifically, the invention provides an ADC circuit that produces a digital representation of a parameter that needs to be regulated (e.g., the absolute output voltage of a power supply), so that any additional monitoring and supervisory circuits could be implemented as full digital circuits. In the detailed description that follows, like element numerals are used to describe like elements illustrated in one or more figures. 
       FIG. 1  depicts an exemplary switched mode power supply  10  having a digital control circuit in accordance with an embodiment of the present invention. The power supply  10  comprises a buck converter topology to convert an input DC voltage V in  to an output DC voltage V o  applied to a resistive load  20  (R load ). The power supply  10  includes a pair of power switches  12 ,  14  provided by MOSFET devices. The drain terminal of the high side power switch  12  is coupled to the input voltage V in , the source terminal of the low side power switch  14  is connected to ground, and the source terminal of the power switches  12  is coupled to the drain terminal of the power switch  14  to define a phase node. An output inductor  16  is coupled in series between the phase node and the terminal providing the output voltage V o , and a capacitor  18  is coupled in parallel with the resistive load R load . Respective drivers  22 ,  24  alternatingly drive the gate terminals of the power switches  12 ,  14 . In turn, the drivers  22 ,  24  are controlled by digital control circuit  30  (described below). The opening and closing of the power switches  12 ,  14  provides an intermediate voltage having a generally rectangular waveform at the phase node, and the filter formed by the output inductor  16  and capacitor  18  converts the rectangular waveform into a substantially DC output voltage V o . 
     The digital control circuit  30  receives a feedback signal from the output portion of the power supply  10 . As shown in  FIG. 1 , the feedback signal corresponds to the output voltage V o , though it should be appreciated that the feedback signal could alternatively (or additionally) correspond to the output current drawn by the resistive load R load  or any other signal representing a parameter to be controlled by the digital control circuit  30 . The feedback path may further include a voltage divider (not shown) to reduce the detected output voltage V o  to a representative voltage level. The digital control circuit  30  provides a pulse width modulated waveform having a duty cycle controlled to regulate the output voltage V o  (or output current) at a desired level. Even though the exemplary power supply  10  is illustrated as having a buck converter topology, it should be understood that the use of feedback loop control of the power supply  10  using the digital control circuit  30  is equally applicable to other known power supply topologies, such as boost and buck-boost converters in both isolated and non-isolated configurations, and to different control strategies known as voltage mode, current mode, charge mode and/or average current mode controllers. 
     More particularly, the digital control circuit  30  includes analog-to-digital converter (ADC)  32 , digital controller (G(z))  34 , and digital pulse width modulator (DPWM)  36 . The ADC  32  further comprises a windowed flash ADC that receives as inputs the feedback signal (i.e., output voltage V o ) and a voltage reference (Ref) and produces a digital voltage error signal (VEd k ) representing the difference between the inputs (Ref−V o ). In the embodiment of  FIG. 1 , the digital controller  34  has a transfer function G(z) that transforms the voltage error signal VEd k  to a digital output provided to the DPWM  36 , which converts the signal into a waveform having a proportional pulse width (PWM k ). As discussed above, the pulse-modulated waveform PWM k  produced by the DPWM  36  is coupled to the gate terminals of the power switches  12 ,  14  through the respective drivers  22 ,  24 . 
       FIG. 2  depicts an exemplary windowed flash ADC  40  for use in the digital control circuit  30 . The ADC  40  receives as inputs the voltage reference Ref and the output voltage V o . The voltage reference is applied to the center of a resistor ladder that includes resistors  42 A,  42 B,  42 C,  42 D connected in series between the reference voltage terminal and a current source connected to a positive supply voltage (V DD ), and resistors  44 A,  44 B,  44 C,  44 D connected in series between the reference voltage terminal and a current source connected to ground. The resistors each have corresponding resistance values to define together with the current sources a plurality of voltage increments ranging above and below the voltage reference Ref. The magnitude of the resistance values and/or current sources can be selected to define the LSB resolution of the ADC  40 . An array of comparators is connected to the resistor ladder, including a plurality of positive side comparators  46 A,  46 B,  46 C,  46 D and a plurality of negative side comparators  48 A,  48 B,  48 C,  48 D. The positive side comparators  46 A,  46 B,  46 C,  46 D each have a non-inverting input terminal connected to the output voltage V o , and an inverting input terminal connected to respective ones of the resistors  42 A,  42 B,  42 C,  42 D. Likewise, the negative side comparators  48 A,  48 B,  48 C each have a non-inverting input terminal connected to the output voltage V o , and an inverting input terminal connected to respective ones of the resistors  44 A,  44 B,  44 C,  44 D. Negative side comparator  48 D has a non-inverting input terminal connected to ground and the inverting input terminal connected to the output voltage V o . It should be appreciated that a greater number of resistors and comparators may be included to increase the number of voltage increments and hence the range of the ADC  40 , and that a limited number of resistors and comparators is shown in  FIG. 2  for exemplary purposes only. 
     The ADC  40  further includes a logic device  52  coupled to output terminals of comparators  46 A,  46 B,  46 C and  48 A,  48 B,  48 C. The logic device  52  receives the comparator outputs and provides a multi-bit (e.g., 4-bit) parallel output representing the digital voltage error VEd k . By way of example, an output voltage V o  that exceeds the reference voltage Ref by one and a half voltage increments would cause the outputs of comparators  46 B,  46 A,  48 A,  48 B, and  48 C to go high, while the outputs of comparators  46 C,  46 D and  48 D remain low. The logic device  52  would interpret this as logic level  9  (or binary  1001 ) and produce an associated voltage error signal VEd k . It should be understood that the voltage reference Ref is variable so as to shift the window of the ADC  40 . If the output voltage V o  exceeds the highest voltage increment of the resistor ladder, the output terminal of comparator  46 D provides a HIGH saturation signal. Similarly, if the output voltage V o  is lower than the lowest voltage increment of the resistor ladder, the output terminal of comparator  48 D provides a LOW saturation signal. 
     In a conventional windowed flash ADC, the resistors  44 A,  44 B,  44 C,  44 D have equal values so as to define a plurality of n voltage references equally spaced above and below the reference voltage Ref. The n comparators  46 A,  46 B,  46 C and  48 A,  48 B,  48 C compare the actual output voltage V O  against the n voltage references and generate a corresponding “thermometer” code, such that comparators  0  to X have an output of one and comparators X+1 to n have an output of zero, with X depending on the voltage amplitude of the V O  signal. 
     It should be appreciated that the range that the windowed flash ADC  40  is able to convert into a digital signal is limited by the step size between each reference voltage and the number of comparators. In order to keep the circuit complexity to a reasonable level, an exemplary implementation may include sixteen comparators. The step size of the circuit should be kept low enough (e.g., 5 mV) by selecting appropriate values of the resistors to provide enough resolution in the feedback loop. The step size directly relates to the output voltage static regulation and also the noise added to the output voltage due to the quantization of the error signal. With sixteen comparators and a 5 mV step size, the overall window is only ±40 mV. In the event of a sudden and large current change on the output of the power supply  10  (e.g., due to load current changes), the dynamic voltage excursion can easily exceed 40 mV. In that case, the ADC  40  saturates and the voltage error signal VEd k  is no longer linear, i.e., it is not proportional to the actual error. As discussed above, the output terminal of comparator  46 D provides a HIGH saturation signal to reflect this saturation condition. 
       FIG. 4  illustrates a graph depicting a linear ADC transfer function in accordance with a conventional windowed flash ADC. The horizontal dimension of the graph reflects the analog error signals input to the logic device  52  and the vertical dimension reflects the digital output from the logic device. As shown, there is a linear relationship between the input analog error signal and the digital output of the ADC within the conversion window due to selection of resistors having uniform values that provide equal voltage increments and the mapping of the digital output values to the input error signal in uniform increments. As a result, the practical window size of the ADC is fairly limited, which has certain disadvantages. Namely, it makes the feedback system non-linear during large and sudden load changes, which tends to make it difficult to guarantee stability in such conditions. In addition, when the correction to the output due to saturation changes so much that it falls immediately into the opposite saturation, the circuit can become unstable and produce a limit cycle oscillation between the ADC window boundaries. 
       FIG. 5  illustrates a graph depicting an ADC transfer function in which the step size is changed in accordance with an embodiment of the invention. As in  FIG. 4 , the horizontal dimension of the graph reflects the analog error signals input to the logic device  52  and the vertical dimension reflects the digital output of the logic device. The step size is increased in the region adjacent to the boundary of the ADC window by using different resistor values in the boundary regions. In addition, the logic device  52  is changed such that the “temperature” code out of the comparators is mapped into a digital number matching the increased step size at the boundary of the window. This keeps the overall transfer function of the ADC linear. While the window is enlarged overall, the gain is substantially unaffected. The decreased resolution at the ADC boundary regions is acceptable since the steady state voltage of the ADC will always be around zero error (assuming a controller transfer function with a pole at zero). At zero error, the resolution is the same as with the previous embodiment and therefore stability and output voltage precision is unaffected. The larger step size of the ADC only affects the circuit during large dynamic changes, i.e., step increases or decreases in load current). Since this is a dynamic process, the precision of the regulation is not important, but by providing a gain number proportional to the actual error the overall stability of the circuit is improved. 
     The embodiment of  FIG. 5  illustrates the use of two different step sizes, i.e., a first step size in the center of the ADC window and a second, larger step size in the peripheral region of the window. It should be appreciated that there may alternatively be a plurality of intermediary gradations of step size ranging from the first step size in the center of the ADC window to the second step size at the periphery. Each of these gradations of step size would nevertheless be mapped into digital numbers matching the corresponding step size to keep the overall transfer function of the ADC linear. 
     While the ADC transfer function of  FIG. 5  increases the ADC window size to improve stability robustness and provides a linear relationship between ADC input and output over a larger window size, it does not provide faster settling time during transient regulation conditions. In the embodiment of  FIG. 6 , the transfer function is further modified to increase the step size at the window boundary as in the preceding embodiment, and also the transfer function is made non-linear toward the window boundary so that the error reported to the controller  36  is larger than the actual value. In the center of the window, the step size and mapping to the digital number is as in the preceding embodiments. But, at the peripheral region of the window, the magnitude of the digital output is increased out of proportion with the step increases of the analog input. The non-linear mapping in the peripheral region of the window helps to speed up the feedback loop for large dynamic errors without altering the small signal stability in steady state conditions. As in the preceding embodiment, the horizontal dimension of the graph reflects the analog error input to the logic circuit  52  and the vertical dimension reflects the digital output of the logic circuit. It should be appreciated that there may be a plurality of gradations of step size and mapping to the digital numbers at the periphery of the ADC window. 
     Returning now to  FIG. 3 , a digital controller having a digital filter and ADC  62  is depicted. The digital filter further comprises an infinite impulse response (IIR) filter that produces an output PWM′ k  from previous voltage error inputs VEd k  and previous outputs PWM′ k . As discussed above, ADC  40  provides the voltage error inputs VEd k . The digital filter outputs PWM′ k  are provided to the digital pulse width modulator (DPWM)  36 , which provides the pulse width modulated control signal (PWM k ) to the power supply power switches. 
     The IIR filter is illustrated in block diagram form and includes a first plurality of delay registers  72 ,  74 , . . . ,  76  (each labeled z −1 ), a first plurality of mathematical operators (multipliers) with coefficients  71 ,  73 , . . . ,  77  (labeled C 0 , C 1 , . . . , Cn), a second plurality of mathematical operators (adders)  92 ,  94 ,  96 , a second plurality of delay registers  82 ,  84 , . . . ,  86  (each labeled z −1 ), and a third plurality of mathematical operators (multipliers) with coefficients  83 ,  87  (labeled B 1 , . . . , Bn). Each of the first delay registers  72 ,  74 ,  76  holds a previous sample of the voltage error VEd k , which is then weighted by a respective one of the coefficients  71 ,  73 ,  77 . Likewise, each of the second delay registers  82 ,  84 ,  86  holds a previous sample of the output PWM′ k , which is then weighted by a respective one of the coefficients  83 ,  87 . The adders  92 ,  94 , and  96  combine the weighted input and output samples. It should be appreciated that a greater number of delay registers and coefficients may be included in the IIR filter, and that a limited number is shown in  FIG. 3  for exemplary purposes only. The digital filter structure shown in  FIG. 3  is an exemplary implementation of the following transfer function G(z): 
     
       
         
           
             
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     The error controller  62  receives a plurality of input signals reflecting error conditions of the ADC  40  and the digital filter. Specifically, the error controller  62  receives the HIGH and LOW saturation signals from the ADC  40  reflecting that the output voltage V o  is above and below the voltage window of the ADC, respectively. Each of the mathematical operators (adders)  92 ,  94 ,  96  provides an overflow signal to the error controller  62  reflecting an overflow condition (i.e., carry bit) of the mathematical operators. The digital filter further includes a range limiter  81  that clips the output PWM′ k  if upper or lower range limits are reached. In that situation, the range limiter  81  provides the error controller  62  with a corresponding limit signal. 
     The error controller  62  uses these input signals to alter the operation of the digital filter in order to improve the responsiveness of the digital filter to changing load conditions. The error controller  62  is coupled to each of the first plurality of delay registers  72 ,  74 ,  76  and second plurality of delay registers  82 ,  84 ,  86  to enable the resetting and/or presetting of the value stored therein. As used herein, “resetting” refers to the setting of the value to an initial value (e.g., zero), whereas “presetting” refers to the setting of the value to another predetermined number. Particularly, the error controller  62  can replace the previous samples of the voltage error VEd k  and output PWM′ k  with predetermined values that change the behavior of the power supply. The digital controller further includes multiplexer  64  that enables selection between the PWM′ k  output signal and a predetermined output signal provided by the error controller  62 . A select signal provided by the error controller  62  determines which signal passes through the multiplexer  64 . When the ADC  40  goes into HIGH or LOW saturation, the error controller  62  sets the PWM′ k  signal to a specific predetermined value (or sequence of values that are dependent in part on the previous samples) by controlling the multiplexer  64 . In order to recover smoothly from such a condition, the error controller can also alter the delayed input and output samples by reloading the first plurality of delay registers  72 ,  74 ,  76 , and second plurality of delay registers  82 ,  84 ,  86 . This will assure a controlled behavior of the feedback loop as the ADC  40  recovers from saturation. 
     By way of example, if the ADC  40  experiences a positive saturation, i.e., the LOW signal changing from a low state to a high state, the PWM′ k  sample can be reset to zero to help to reduce the error. By resetting the PWM′ k  sample to zero, the pulse width delivered to the high side power switch  12  of the power supply  10  goes to zero, effectively shutting off power to the resistive load  20  (see  FIG. 1 ). In order to recover from this situation smoothly, the samples PWM′ k−1 , PWM′ k−2 , . . . , PWM′ k−n  can also be reset to zero or preset to another value in order to allow a smooth recovery. Likewise, if the ADC  40  experiences a negative saturation, i.e., the HIGH signal changing from a low state to a high state, the PWM′ k  sample can be preset to a maximum value to increase the pulse width delivered to the high side power switch  12  to reduce the error. Also, when an internal numeric overflow of the digital filter occurs, the error controller  62  can take actions to prevent uncontrolled command of the power switches of the power supply, such as altering the input and output samples of the digital filters. 
     In a further embodiment of the invention, the ADC is configured to provide a digital representation of the absolute output voltage (V o ). This digital representation of the output voltage V o  can then be further utilized by other power supply supervisory circuits to provide functions such as under-voltage protection, Power-Good-Low monitor, Power-Good-High monitor, and over-voltage protection. Hence, the entire control circuitry for the power supply can be implemented using digital circuitry, thereby eliminating the need for analog circuit components such as comparators. 
       FIG. 7  illustrates an exemplary embodiment of a self-tracking ADC having an analog section  110  and a digital section  120 . The analog section  110  includes a windowed flash ADC  112  and a digital-to-analog converter (DAC)  114 . A subtractor  115  produces a voltage representing a difference between an input voltage (V i ) and a variable reference voltage generated by the DAC  114 . The windowed flash ADC  112  digitizes the voltage difference and provides an error signal e k  to the digital section  120 , which corrects the DAC variable reference voltage so that it tracks the input voltage V i . It should be appreciated that the input voltage V i  to the self-tracking ADC may actually be the output voltage V o  of the power supply, as described above in the preceding embodiments. Alternatively, the input voltage V i  may be any other voltage for which regulation is desired. 
     The digital section  120  further includes a clamp  122 , an integrator  124 , an adder  125 , and a function circuit  128  that combine to generate the new digital reference N k  that will be converted back into an analog voltage by DAC  114 . The error signal e k  is further used to generate together with the reference value N k  the absolute representation of the input voltage V i . The coarse input voltage V i  representation is provided by N k , and a fine difference value between the coarse DAC reference N k  and the real input voltage is provided by the value e k . 
     More particularly, the output e k  of the flash windowed ADC  112  is applied to the function circuit  128 . The function circuit  128  generates a value f(e k ) that represents the correction to be applied to the variable reference voltage so that it tracks more closely the input voltage. The value f(e k ) may be calculated as follows:
 
 f ( e   k )=ROUND( e   k   /M )
 
The value f(e k ) is applied to a counter formed by integrator  124 , clamp  122 , and adder  125 . The adder  125  combines the value f(e k ) to the previous counter state N k  and gets clamped by the clamp  122 . The clamp  122  provides an output corresponding to the next counter state N k+1 . The clamp  122  serves to limit the count value and prevent the counter from rolling over. The next state N k+1  of the counter is applied to the DAC  114  and gets sampled on the next clock cycle by the integrator  124 .
 
     The counter state N k  is used together with the ADC error signal e k  to determine the digital representation of the absolute input voltage V i . The counter state N k  is scaled with the resolution difference M by multiplier  126  and the result is added to the ADC error e k  by adder  127 . Finally, another clamp circuit  130  may be coupled to the output of adder  127  to avoid negative digital values or excessive high values. The output value D k  represents the digital representation of the absolute input voltage V i . 
     It should be appreciated that the resolution of DAC  114  as compared to the mid-band resolution of the windowed flash ADC  112  is lower by a constant factor M. For example, ADC  112  could have a mid-band least significant bit (LSB) resolution of 5 mV. Hence, with a factor M=5 the LSB resolution of DAC  114  would thus be 25 mV. Accordingly, the DAC  114  will therefore generate a relatively coarse reference voltage close to the input voltage, and the ADC  112  will generate an error e k  compared to this coarse reference voltage. The windowed flash ADC  112  has also a much higher resolution in the middle of its window; in contrast, the resolution decreases towards the edge of the window. This has an advantage that the window size for a given number of comparators is larger. A drawback is that the accuracy at the edge of the window decreases, but this is generally not a concern in most power supply applications. Also, it is advantageous to have a larger ADC window, since this will be help to correct the DAC reference voltage with larger step sizes so that the reference voltage can track faster signals. 
     Continuing the previous example, the DAC  114  could have a total of 8 bits (e.g., defining a range from 0 to 6.375V), the windowed flash ADC  112  could have a total of eighteen comparators with a mid-band resolution of 5 mV, and M could be equal to 5. The resolution of the combined circuit is therefore log 2 (5·2 8 )=10.3 bit. It is advantageous (but not necessary) that the outer band resolution of the ADC  112  is equal to or a multiple of the DAC resolution, in this example therefore 25 mV, 50 mV, . . . , etc. 
       FIG. 8  illustrates an example of the comparator thresholds, the corresponding error values e k  from the ADC  112 , the function values f(e k ), the next counter state N k+1  and the digital output D k  for an assumed input voltage around 1.2V and a DAC reference value N k =50 (with other parameters as noted previously). In this example, the ADC  112  also will be able to track input signals changing with a rate of 7·25 mV per clock cycle. 
     In the embodiment of  FIG. 7 , it can be seen that the values e k  to be added to M·N k  to produce the output D k  can be relatively large, but only a few values out of the complete range will actually be used because of the coarse resolution of the window ADC  112  on its boundaries. This may represent a waste of resources for certain applications. Also, the ADC  112  may not produce directly the value e k , but more likely would produce a bit pattern corresponding to the comparator outputs. 
     In a second embodiment, the output D k  is generated in a different manner to simplify the implementation. Particularly,  FIG. 9  illustrates a modified digital section  140  that includes a clamp  142 , an integrator  144 , and an adder  145  arranged as in  FIG. 7  to provide a counter. Instead of the function circuit, the embodiment of  FIG. 9  includes a look up table (LUT)  146  that provides a first function value f(e k ) to the adder  145 . As in the preceding embodiment, the resulting digital reference N k+1  will be converted back into an analog voltage by DAC  114 . The LUT  146  also provides a second function value g(e k ) used to produce the digital representation of the absolute input voltage V i . The new counter state N k+1  is scaled with the resolution difference M by multiplier  148  and the result is added to the second function value g(e k ) by adder  147 . Another clamp circuit  150  may be coupled to the output of adder  17  to avoid negative digital values or excessive high values. The output value D k  represents the digital representation of the absolute input voltage V i . 
     More particularly, the output value D k  is determined in accordance with the following expressions:
 
 D   k   =M·N   k   +e   k  
 
 N   k+1   =N   k   +f ( e   k )
 
The output value D k  also relates to one of the following expressions:
 
 D   k   =M ·( N   k+1   −f ( e   k ))+ e   k  
 
 D   k   =M·N   k+1   +e   k   −M·f ( e   k )
 
By defining g(e k )=e k −M·f(e k ) and using the definition of f(e k ) stated above yields:
 
 g ( e   k )= e   k   −M ·ROUND( e   k   /M )
 
It will be appreciated that the function g(e k ) can only take the values given by the following inequality:
 
− M/ 2 &lt;g ( e   k )&lt; M/ 2
 
In the example above, g(e k ) would therefore only be either −2, −1, 0, 1 or 2, which is much simpler to handle. Hence, a look up table may be used instead of arithmetic circuitry to generate the function g(e k ).  FIG. 10  shows the corresponding values for the different functions for an input voltage V i  around 1.2V and N k =50 as an example.
 
     In steady state conditions (i.e., input voltage V i  is essentially a constant DC voltage), it would be advantageous to have the DAC reference value also being constant. By way of example, a steady state input voltage V i  may be converted to e k =+3 with N k . In the next cycle, the DAC  114  will be incremented by one and the result should theoretically be e k =−2 with N k +1=N k , and remain there since the error is small enough to not provoke a reference voltage change (i.e., f(e k )=0). But, because of small errors in the comparator thresholds of the flash windowed ADC  112  and the LSB size of the DAC  114 , the conversion result could be e k =−3 with N k+1 =N k −1. This result could again lower the output of the DAC  114  by 1 LSB. Due to the same uncertainty in the next cycle, the DAC  114  could again be incremented by 1. These successive limit cycle oscillations are particularly undesirable in regulation applications. 
     To avoid such limit cycle oscillations, the switchpoints causing the DAC  114  to increment and decrement in mid-band should not be symmetric. This will introduce a small hysteresis and will eliminate the limit cycle oscillation. No change in thresholds are necessary to accomplish this. For example, a different encoding of the g(e k ) and f(e k ) values as shown in  FIG. 11  will have the same effect. Note that changes to the preceding  FIG. 10  are marked in grey in  FIG. 11 . The hysteresis is graphically shown in  FIG. 11  as an asymmetry between the +1 and −1 values of f(e k ). 
     Lastly,  FIG. 12  illustrates an exemplary switched mode power supply (as in  FIG. 1 ) including a digital control circuit having the self-tracking ADC as discussed above with respect to  FIGS. 7-11 . As in  FIG. 1 , the digital control circuit includes a digital controller  34  and a digital pulse width modulator (DPWM)  36 . In this embodiment, the digital control circuit further includes a self-tracking ADC comprising DAC  114 , adder  115  and flash windowed ADC  112  substantially as described above in  FIGS. 7 and 9 . The adder  115  is further coupled to the junction of a voltage divider formed by resistors  164 ,  162  connected in series across the output terminals of the switched mode power supply. It should be appreciated that the voltage at the junction of the voltage divider is a scaled representation of the output voltage V o  of the switched mode power supply, and corresponds to the input voltage V i  described above with respect to  FIGS. 7-11 . 
     The DAC  114  and ADC  112  are further coupled to a tracker circuit  120  corresponding to the digital section  120  of  FIG. 7 . Alternatively, it should be appreciated that the tracker circuit  120  could be provided by the digital section  140  of  FIG. 9 . The tracker circuit  120  provides an output value corresponding to a digital representation of the scaled representation of the absolute output voltage V o  of the switched mode power supply. This digital representation of the output voltage V o  is subtracted from a reference voltage by subtractor  160 , which provides a difference value (or voltage error) to the digital controller  34 . It should be appreciated that the digital representation of the output voltage V o  may also be used by other control circuitry used to monitor and regulate the performance of the switched mode power supply. 
     Having thus described a preferred embodiment of a self-tracking ADC for use in a switched mode power supply, it should be apparent to those skilled in the art that certain advantages of the system have been achieved. It should also be appreciated that various modifications, adaptations, and alternative embodiments thereof may be made within the scope and spirit of the present invention. The invention is further defined by the following claims.