Patent Publication Number: US-2021184454-A1

Title: Bandwidth-boosted bidirectional serial bus buffer circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claim priority to U.S. Provisional Application No. 62/947,553, filed Dec. 13, 2019, entitled “Bandwidth-Boosted Bidirectional I2C Buffer Architecture,” which is hereby incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     Serial buses, such as the inter-integrated circuit (I 2 C) bus, are widely used to connect systems of devices. For example, the I 2 C bus is used to provide communication between a master device and one or more slave devices. In such applications; the capacitance added to the serial bus by the slave devices may be large enough to significantly degrade signal transition times and cause violation of serial bus timing specifications. 
     SUMMARY 
     A serial bus buffer circuit that includes a switchable low impedance path to reduce transients (glitches) on the bus signals is disclosed herein. In one example, a serial bus buffer circuit includes a master input-output terminal, a slave input-output terminal, a first switch, a second switch, a resistor, and a switch control circuit. The first switch includes a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the master input-output terminal. The resistor includes a first terminal and a second terminal. The first terminal of the resistor is coupled to the second terminal of the first switch. The second switch includes a first terminal, a second terminal, and a control terminal. The first terminal of the second switch is coupled to the second terminal of the resistor. The second terminal of the second switch is coupled to the slave input-output terminal. The switch control circuit is coupled to the master input-output terminal, the slave input-output terminal, the control terminal of the first switch, and the control terminal of the second switch. 
     In another example, a serial bus buffer circuit includes a master input-output terminal, a slave input-output terminal, a switched resistor circuit, and a switch control circuit. The switched resistor circuit is configured to provide a low impedance connection between the master input-output terminal and the slave input-output terminal. The switch control circuit is coupled to the switched resistor circuit, and is configured to enable the low impedance connection based on voltage at the master input-output terminal and voltage at the slave input-output terminal. 
     In a further example, a method includes monitoring a first voltage at a master input-output terminal of a serial bus buffer circuit, and monitoring a second voltage at a slave input-output terminal of the serial bus buffer circuit. The first voltage and the second voltage are compared to a low logic level threshold. The low impedance connection between the master input-output terminal and the slave input-output terminal is enabled responsive to the first voltage or the second voltage being below the low logic threshold. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a detailed description of various examples, reference will now be made to the accompanying drawings in which: 
         FIG. 1  shows a block diagram for an example serial bus system that includes a serial bus buffer circuit; 
         FIG. 2  shows a block diagram for an example serial bus buffer circuit that includes transient reduction circuitry; 
         FIG. 3  shows a glitch produced at a handoff in a serial bus buffer circuit that lacks transient reduction circuitry; and 
         FIG. 4  shows a glitch produced at a handoff in a serial bus buffer circuit that includes transient reduction circuitry; and 
         FIG. 5  shows a flow diagram for an example method for reducing transients in a serial bus buffer circuit. 
     
    
    
     DETAILED DESCRIPTION 
     Serial bus buffer circuits are used to reduce capacitive loading and improve signal integrity in serial bus systems (e.g., I 2 C bus systems). Serial bus buffers that lack very high bandwidth, produce glitches during handoff transitions (such as acknowledge, clock-stretching, etc.). Some serial bus buffer circuit implementations provide good glitch rejection, but poor isolation between serial bus devices. Other serial bus circuit implementations provide good isolation between serial bus devices, but are too slow to provide good glitch rejection. 
     The serial bus buffer circuits of the present disclosure include a compensation circuit that dynamically switches a low impedance compensation path between the master and slave terminals of the serial bus buffer circuit when handoff conditions are detected. The low impedance compensation path increases the bandwidth of the serial bus buffer circuit to reduce the amplitude and duration of handoff glitches. The serial bus buffer circuits also provide good master-slave isolation when the low-impedance compensation path is disabled. 
       FIG. 1  shows a block diagram for an example serial bus system  100  that includes a serial bus buffer circuit. The serial bus system  100  includes a master device  102 , a serial bus buffer circuit  104 , and a slave device  106 . In some implementations of the serial bus system  100 , the master device  102  is an I2C master, the slave device  106  is an I2C slave, and the serial bus buffer circuit  104  is an I2C serial bus buffer circuit. The master device  102  is coupled to a master input-output terminal  104 A of the serial bus buffer circuit  104 , and the slave device  106  is coupled to a slave input-output terminal  104 B of the serial bus buffer circuit  104 . The serial bus buffer circuit  104  provides isolation and increased drive between the master device  102  and the slave device  106 . The serial bus buffer circuit  104  includes a low impedance compensation path between the master input-output terminal  104 A and the slave input-output terminal  104 B. The serial bus buffer circuit  104  detects potential handoffs and enables the low impedance compensation path when a potential handoff is detected to reduce glitch amplitude and duration. When handoff conditions are not present, the serial bus buffer circuit  104  disables the low impedance compensation path to provide increased isolation between the master input-output terminal  104 A and the slave input-output terminal  104 B. 
       FIG. 2  shows a block diagram for an example serial bus buffer circuit  200  that includes transient reduction circuitry. The serial bus buffer circuit  200  is an implementation of the serial bus buffer circuit  104 . The serial bus buffer circuit  200  includes a switched resistor circuit switched resistor circuit  202 , a drive circuit  204 , a drive circuit  206 , a switch control circuit  208 , a resistor  210 , a switch  212 , a resistor  214 , and a switch  216 . The switched resistor circuit  202  is an implementation of the low impedance compensation path of the serial bus buffer circuit  104 . The switched resistor circuit  202  includes a resistor  218 , a switch  220 , and a switch  222 . The switch  220  and the switch  222  are closed to connect the resistor  218  to the master input-output terminal  104 A and the slave input-output terminal  104 B and enable a low impedance connection between the master input-output terminal  104 A and the slave input-output terminal  104 B. The switch  220  and the switch  222  are opened to isolate the master input-output terminal  104 A from the slave input-output terminal  104 B. 
     A terminal  220 A of the switch  220  is coupled to the master input-output terminal  104 A. A terminal  220 B of the switch  220  is coupled to the terminal  218 A of the resistor  218 . A terminal  218 B of the resistor  218  is coupled to the terminal  222 B of the switch  222 . A terminal  222 A of the switch  222  is coupled to the slave input-output terminal  104 B. 
     The switch control circuit  208  monitors the voltages on the master input-output terminal  104 A and the slave input-output terminal  104 B and controls the switched resistor circuit  202  based on the voltages. The switch control circuit  208  includes a terminal  208 A coupled to the master input-output terminal  104 A and a terminal  208 B coupled to the slave input-output terminal  104 B. The switch control circuit  208  also includes a terminal  208 D coupled to a control terminal  220 C of the switch  220 , and a terminal  208 E coupled to a control terminal  222 C of the switch  222 . The switch control circuit  208  includes analog circuitry, such as analog comparators, that compares the voltages on the master input-output terminal  104 A and the slave input-output terminal  104 B to a logic low voltage of the serial bus buffer circuit  200  (e.g., 30% of the power supply voltage at a power supply terminal  232 ). If the switch control circuit  208  detects a logic low voltage at the master input-output terminal  104 A or the slave input-output terminal  104 B, the switch control circuit  208  closes the switch  220  and the switch  222  to enable the low impedance connection between the master input-output terminal  104 A and the slave input-output terminal  104 B. 
     The switch control circuit  208  also includes analog circuitry, such as analog comparators that compares the voltages on the master input-output terminal  104 A and the slave input-output terminal  104 B to a predetermined voltage (e.g., 700 millivolts (mv)), and includes slew rate detection circuitry that measures the slew rate of the voltages at the master input-output terminal  104 A and slave input-output terminal  104 B. If the voltage at the master input-output terminal  104 A and the voltage at the slave input-output terminal  104 B exceed the predetermined voltage, and the slew rate of the voltage at the master input-output terminal  104 A and of the voltage at the slave input-output terminal  104 B exceed a predetermined slew rate (e.g., 1.2 volts per microsecond), then the switch control circuit  208  opens the switch  220  and the switch  222  to disable the low impedance connection between the master input-output terminal  104 A and the slave input-output terminal  104 B. 
     The switch control circuit  208  also includes digital circuitry, such as state machine circuitry, that controls (opens and closes as described above) the switch  220  and the switch  222  based on the outputs of the analog circuitry and the current state of the switches  220  and  222 . 
     The drive circuit  204  includes an amplifier  224  and a transistor  226 . The transistor  226  is an N-channel metal oxide semiconductor field effect transistor (MOSFET) in some implementations of the drive circuit  204 . A non-inverting input terminal  224 A of the amplifier  224  is coupled to the master input-output terminal  104 A, and an inverting input terminal  224 B of the amplifier  224  is coupled to the slave input-output terminal  104 B. An output terminal  224 C of the amplifier  224  is coupled to the gate terminal  226 G of the transistor  226 . A source terminal  226 S of the transistor  226  is coupled to a ground terminal  234 . A drain terminal  226 D of the transistor  226  is coupled to the master input-output terminal  104 A. The amplifier  224  turns on the transistor  226  to pull down the master input-output terminal  104 A when the voltage at the master input-output terminal  104 A is greater than the voltage at the slave input-output terminal  104 B. 
     The drive circuit  206  includes an amplifier  228  and a transistor  230 . The transistor  230  is an N-channel MOSFET in some implementations of the drive circuit  206 . A non-inverting input terminal  228 A of the amplifier  228  is coupled to the slave input-output terminal  104 B, and an inverting input terminal  228 B of the amplifier  228  is coupled to the master input-output terminal  104 A. An output terminal  228 C of the amplifier  228  is coupled to the gate terminal  230 G of the transistor  230 . A source terminal  230 S of the transistor  230  is coupled to the ground terminal  234 . A drain terminal  230 D of the transistor  230  is coupled to the slave input-output terminal  1046 . The amplifier  228  turns on the transistor  230  to pull down the slave input-output terminal  104 B when the voltage at the slave input-output terminal  104 B is higher than the voltage at the master input-output terminal  104 A. 
     The switch  212  couples the resistor  210  to the master input-output terminal  104 A to pull up the master input-output terminal  104 A under control of the switch control circuit  208 . The resistor  210  includes a terminal  210 A coupled to the power supply terminal  232  and a terminal  210 B coupled to a terminal  212 A of the switch  212 . A terminal  212 B of the switch  212  is coupled to the master input-output terminal  104 A, and a control terminal  212 C of the switch  212  is coupled to a terminal  208 C of the switch control circuit  208 . The switch control circuit  208  closes the switch  212  based on the voltage at the master input-output terminal  104 A exceeding a threshold (e.g., 30% of the voltage at the power supply terminal  232 ) to decrease the rise time of the voltage of the master input-output terminal  104 A. 
     The switch  216  couples the resistor  214  to the slave input-output terminal  104 B to pull up the master input-output terminal  104 A under control of the switch control circuit  208 . The resistor  214  includes a terminal  214 A coupled to the power supply terminal  232  and a terminal  214 B coupled to a terminal  216 A of the switch  216 . A terminal  216 B of the switch  216  is coupled to the slave input-output terminal  104 B, and a control terminal  216 C of the switch  216  is coupled to a terminal  208 F of the switch control circuit  208 . The switch control circuit  208  closes the switch  216  based on the voltage at the slave input-output terminal  104 B exceeding a threshold (e.g., 30% of the voltage at the power supply terminal  232 ) to decrease the rise time of the voltage of the slave input-output terminal  104 B. 
       FIG. 3  shows a glitch produced at a handoff in a serial bus buffer circuit that lacks transient reduction circuitry. The glitch  300  has maximum amplitude of about 965 my and is greater than about 300 my in amplitude for about 350 nanoseconds (ns). 
       FIG. 4  shows a glitch produced at a handoff by an implementation of the serial bus buffer circuit  104 . The glitch  400  has maximum amplitude of less than 830 my and is greater than about 300 my in amplitude for less than about 140 nanoseconds (ns). Thus, the serial bus buffer circuit  104  substantially reduces the amplitude and duration of transient glitches on the serial bus relative to a serial bus buffer circuit that lacks transient reduction circuitry. 
       FIG. 5  shows a flow diagram for an example method  500  for reducing transients in a serial bus buffer circuit. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some implementations may perform only some of the actions shown. Operations of the method  500  are performed by an implementation of the serial bus buffer circuit  200 . 
     In block  502 , the switch control circuit  208  monitors the voltage at the master input-output terminal  104 A and the voltage at the slave input-output terminal  104 B. 
     In block  504 , the switch control circuit  208  compares the voltage at the master input-output terminal  104 A to a low logic level threshold (e.g., 30% of the voltage at the power supply terminal  232 ), and compares the voltage at the slave input-output terminal  104 B to the low logic level threshold. 
     In block  506 , if the voltage at the master input-output terminal  104 A is less than the low logic level threshold, or the voltage at the slave input-output terminal  104 B is less than the low logic level threshold, then the method continues in block  508 . If the voltage at the master input-output terminal  104 A is not less than the low logic level threshold, and the voltage at the slave input-output terminal  104 B is not less than the low logic level threshold, then the method continues in block  502 . 
     In block  508 , the switch control circuit  208  enables a low impedance path between the master input-output terminal  104 A and the slave input-output terminal  104 B. Enabling the low impedance path includes closing the switch  220  and the switch  222 . Handoff transients are reduced while the low impedance path is enabled. 
     In block  510 , the switch control circuit  208  monitors the voltage at the master input-output terminal  104 A and the voltage at the slave input-output terminal  104 B, and monitors the slew rate of the voltage at the master input-output terminal  104 A and the slew rate of the voltage at the slave input-output terminal  104 B. 
     In block  512 , the switch control circuit  208  compares the voltage at the master input-output terminal  104 A to a predetermined threshold (a disable threshold, e.g., 700 mv), compares the voltage at the slave input-output terminal  104 B to the predetermined threshold, compares the slew rate of voltage at the master input-output terminal  104 A to a threshold slew rate (e.g., 1.2 v/us), and compares the slew rate of voltage at the slave input-output terminal  104 B to the threshold slew rate. 
     In block  514 , if the voltage at the master input-output terminal  104 A is greater than the predetermined threshold, the slew rate of the voltage at the master input-output terminal  104 A is greater than the threshold slew rate, the voltage at the slave input-output terminal  104 B is greater than the predetermined threshold, and the slew rate of the voltage at the slave input-output terminal  104 B is greater than the threshold slew rate, then the method  500  continues in block  516 . If the voltage at the master input-output terminal  104 A is not greater than the predetermined threshold, the slew rate of the voltage at the master input-output terminal  104 A is not greater than the threshold slew rate, the voltage at the slave input-output terminal  104 B is not greater than the predetermined threshold, or the slew rate of the voltage at the slave input-output terminal  104 B is not greater than the threshold slew rate, then the method  500  continues in block  510 . 
     In block  516 , the switch control circuit  208  disables the low impedance path between the master input-output terminal  104 A and the slave input-output terminal  104 B. Disabling the low impedance path includes opening the switch  220  and the switch  222 . 
     The term “couple” is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with the description of the present disclosure. For example, if device A generates a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A. 
     Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.