Patent Publication Number: US-11658696-B2

Title: Network transceiver with VGA channel specific equalization

Description:
BACKGROUND 
     Modern computing infrastructure includes a variety of network connected devices such as servers, routers, switches in data centers and end-user computer devices, tablets, and smartphones that connect to these data centers via local area and wide area networks. These connected devices involve high speed transmission of large amounts of data in near real time. The demand for speed and efficiency has increased dramatically within recent years, and data transmission rates have seen a steady climb. Ethernet has been the standard method of connecting these computers and devices on a network that requires high speed transmission. Pulse Amplitude Modulation (PAM) technique has been used for high speed transmission. Pulse Amplitude Modulation-4 (PAM-4), which is a four-level modulation scheme, has been adopted for achieving a higher data rate in some Ethernet networks. 
     SUMMARY 
     According to one aspect of the present disclosure, a network transceiver device is provided, including at least two variable gain amplifiers (VGAs) configured to amplify received signals, and at least two sets of analog digital converters (ADCs), each set including a plurality of ADCs coupled to a respective output of a corresponding one of the plurality of VGAs, the sets of ADCs being arranged in at least a first VGA-specific channel and at least a second VGA-specific channel. The network transceiver device may further include a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive a respective output of a corresponding one of the plurality of ADCs in either the first VGA-specific channel or the second VGA-specific channel, each FFE being configured to adaptively equalize the output of received from the corresponding one of the ADCs utilizing a plurality of equalization coefficients, the equalization coefficients including a first equalization coefficient subset with coefficient values that are common all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for the first VGA-specific channel and a second set of coefficient values for the second VGA-specific channel, the first and second set of coefficient values being computed independently of each other. 
     This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to implementations that solve any or all disadvantages noted in any part of this disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    shows a schematic view of a computing system that includes a plurality of network transceiver devices configured to transmit data between computing devices over a transmission medium, according to one example of the present disclosure. 
         FIG.  2    shows a schematic view of an example network transceiver device of the system of  FIG.  1   , which includes a transmitter and receiver. 
         FIG.  3    schematically shows an example receiver of the network transceiver device of the system of  FIG.  1   , in which a plurality of ADCs and a plurality of FFEs are arranged in one or more VGA-specific channels. 
         FIG.  4 A  schematically shows FFE coefficients for the VGA-specific channels of the receiver of  FIG.  3   . 
         FIG.  4 B  schematically shows ADC buses and FFE coefficients for the VGA-specific channels of the receiver of  FIG.  3   . 
         FIG.  5    schematically shows an example CDR circuit of the network transceiver device of  FIG.  2   . 
         FIG.  6    is a graph of an example impulse response signal utilized by the phase detector of the CDR circuit of  FIG.  5   , showing a main cursor, two precursors, and two post cursors. 
         FIG.  7    schematically shows an example of clock pulses that are generated by the CDR circuit of  FIG.  2    and used in timing of the VGAs of the network transceiver device. 
         FIG.  8    schematically shows an example of the clock pulses generated by the CDR circuit of  FIG.  2   , which are used for the timing of ADCs in the network transceiver device. 
         FIG.  9    schematically shows a fanout architecture in which four sets of interleaved ADCs are arranged in two VGA-specific channels. 
         FIG.  10    shows a flowchart of a signal processing method according to one example of the present disclosure. 
         FIG.  11    shows additional steps of the method of  FIG.  10   . 
     
    
    
     DETAILED DESCRIPTION 
     As discussed above, the connected computers and devices in modern computing infrastructure often utilize high speed transmission of large amounts of data in near real time. Computer network speeds have evolved significantly over time, rising from 10 Mbps for connecting local computers to more than 40 Gbps for connecting servers, switches, and routers in data centers. Challenges exist to achieving even higher data rates for such network transmissions. For example, at the physical link level of the Open Systems Interconnect (OSI) model, communications hardware such as a transmission medium (e.g., copper or fiber cables, wireless, etc.) and connectors such as network transceivers operate to transfer data symbols between endpoint devices. It is difficult for conventional network transceivers to operate at such high data transmission rates. Some modern network transceivers include variable gain amplifiers (VGAs) coupled to analog digital converters (ADCs). Physical limitations on the conversion rates of the ADCs in such network transceivers limit the maximum achievable data transfer rate for each ADC. 
     To address these issues, a network transceiver device and signal processing method for use therewith are disclosed herein.  FIG.  1    shows a system  10  including a network transceiver device  12  according to one aspect of the present disclosure that transmits and receives communications over a transmission medium  14  with one or more computing devices  16 . In the depicted configuration, a first computing device  16 A communicates via a first network transceiver device  12 A via the transmission medium  14  and second network transceiver device  12 B to transmit and receive data to and from second computing device  16 B. Computing devices  16  may be any of a variety of types of computing devices, such as laptop, desktop, server, or network appliance such as an application delivery controller, load balancer, switch, etc. Computing devices  16  may also be mobile computing devices such as a handheld tablet or smartphone device. The transmission medium may be a conductive wire such as a copper cable, an optical transmission device such as an optical fiber. One form factor in which the network transceiver device may be provided is a network interface card such as a Peripheral Component Interconnect (PCI) ethernet adapter network interface card. The network transceiver device  12  may be configured to operate as a four-level pulse-amplitude modulated (PAM-4) transceiver. 
     Turning now to  FIG.  2   , the network transceiver device  12  may include a transmitter  18  configured to transmit, and a receiver  20  configured to receive, communications sent over the transmission medium  14 . Each of the transmitter  18  and receiver  20  are connected to terminals that connect to the transmission medium  14  to send and receive signals over the transmission medium  14 . Two of these terminals are labeled TXP and TXN, and are differential serial output signals, while the other two are labeled RXP and RXN, and are differential serial input signals. The TXP, TXN, RXP and RXN signals interface to the transmission medium  14 . Conversely, each of the transmitter  18  and receiver  20  also have respective interfaces, namely the TX interface  24  and the RX interface  52 , which are configured to interface with the computing devices  16 . Typically, these interfaces operate over interconnects or circuitry on a network interface card. Thus, the computer devices  16  may be integrated in a same housing H with the network transceiver device  12 . 
     The transmitter  18  transmits signals over the transmission medium  14 , and the signals are received by a T-Coil  26  at the receiver  20 . The T-Coil  26  includes inductors used for impedance matching and reduction of input return-loss. A diode for electrostatic discharge (ESD) protection is also included with the T-Coil  26 . After the T-Coil  26 , the signals go through a continuous time linear equalizer (CTLE)  28 , which is a linear filter applied at a receiver that attenuates low-frequency signal components and amplifies high-frequency signal components and compensate high-frequency losses introduced by the transmission medium  14 . The CTLE  28  is implemented on the input side of the receiver  20  to perform linear equalization in the analog domain before analog-to-digital conversion, which is described below. In the depicted configuration, one CTLE  28  is provided, which has the benefit of minimizing power consumption for the analog equalization, since CTLE consumes significant power at high transmission rates. However, in other configurations it will be appreciated that more than one CTLE can be installed in the receiver  20 . 
     The network transceiver device  12  further may include at least two variable gain amplifiers (VGAs)  30  configured to amplify received signals. The VGAs  30  are configured to receive equalized output from the CTLE  28 . Each VGA  30  is an electronic amplifier that varies its gain depending on a control voltage. The VGAs  30  can be used to amplify low amplitude signals and attenuate high amplitude signals, as desired. The VGAs  30  may be placed before ADCs  32  to adjust gain of the equalized signals to lie within a dynamic range of each of the ADCs  32  before the gain-adjusted equalized signals are supplied to the ADCs  32 . To achieve a high transmission rate, such as 112 Gbps, a fanout architecture is utilized. Thus, in one example embodiment, two VGAs  30  are provided, and the two VGAs  30  fan out to 64 interleaved ADCs  32 , although other numbers and ratios of VGAs and ADCs may be provided. In one example, four sets of ADCs are included, with 16 ADCs included in each of the four sets. The interconnection of the VGAs  30  to the ADCs  32  will be described below. Each ADC  32  includes a track and hold circuit  34 . Each track and hold circuit  34  tracks input signals to each ADC  32  and holds a fixed amplitude while conversion by each ADC  32  is in process. Each track and hold circuit  34  holds the incoming analog signals from the VGAs  30  and each ADC  32  generates digital signals from the analog signals based on a sampling clock generated by a clock data recovery (CDR) circuit  36 , which is described below. The CDR circuit  36  includes a phase detector  40  and phase interpolator  38 . The CDR circuit  36  receives digital data from the ADCs  32 , extracts clock data from the received signal, and generates a sample clock signal, which is transmitted to the ADCs  32 . The details of the function of the CDR circuit  36  are described below. 
     The network transceiver device  12  further may include digital equalizers  42  such as feed-forward equalizers (FFEs)  44  and decision feedback equalizers (DFEs)  46 . The FFE  44  utilizes a digital finite impulse response filter (FIR) to compensate for pre-cursor and post-cursor inter-symbol interference (ISI). The DFE  46  is a nonlinear equalizer that uses previous detector decision to eliminate an inter-symbol interference (ISI) on pulses that are currently being demodulated. The FFEs  44  and DFEs  46  are configured to adaptively equalize outputs received from the ADCs  32 . Further, in some configurations, the network transceiver device  12  may further include a maximum likelihood sequence estimation (MLSE) equalizer  48 . The MLSE equalizer  48  utilizes a Viterbi algorithm to detect the presence of inter-symbol interference (ISI) and noise. The MLSE equalizer is coupled on output side of the plurality of the DFEs, and is configured to correct DFE burst errors in each of the plurality of DFEs, upon detection of the occurrence such burst errors. 
     The digital equalizers  42  receive digital data from the ADCs  32 , receive coefficient values from a least mean square adaptation module  50 , serially perform equalization in the digital domain on the output of the ADCs based on the coefficients, and output the equalized digital data to an RX interface  52 . The equalized digital data is represented as PAM (HAT) after output by the DFE  46 , and PAM when output in final form after the MLSE equalizer  48  (when included) to the RX interface. It will be appreciated that the values of PAM (HAT) and PAM are returned to the least means square adaptation value for use in a subsequent time step. The equalized digital data PAM is transmitted via the RX interface  52  to the computing device  16 B. The equalized digital data PAM represents one of the four PAM signal states 0, 1, 2, or 3. Additional details of the function of each digital equalizer are described below. 
     Turning to  FIG.  3   , the network transceiver device  12  further includes at least two sets  60  of analog digital converters (ADCs)  32 , including a first ADC set  60 A and a second ADC set  60 B. Each set  60  includes a plurality of ADCs  32  coupled to a respective output of a corresponding one of the plurality of VGAs  30 . The sets  60  of ADCs  32  are arranged in at least one first VGA-specific channel  66  and at least one second VGA-specific channel  68 . It will be appreciated that the first VGA-specific channel  66  may be referred to as an even channel since it contains even numbered ADCs and the second VGA-specific channel  68  may be referred to as an odd channel since it contains odd numbered ADCs, the even and odd numbered ADCs being interleaved in a sampling sequence as discussed below. In the depicted embodiment, sixteen even channels  66  in the first ADC set  60 A and sixteen odd channels  68  are provided in the second ADC set  60 B of the ADCs  32 , although other configurations are possible. The VGAs  30  provide signals to the track and hold circuits  34 , which output at an appropriate timing signals to each of the ADCs  32 , which in turn convert the analog signals into digital signals. Each ADC  32  is operated based on a different phase of the sampling clock generated from the CDR circuit  36  as described below. 
     It will be appreciated that, by installing multiple VGAs and multiple ADCs in a network transceiver device, parallelism can be achieved that enables a higher overall data transmission rate and overcomes the individual conversion rate limitation of each ADC. For example, even if a single ADC is limited to 875 MHz, a throughout of 112 Gbps (or 56 Gbps symbol transfer rate) can be realized by using a fanout to 64 ADCs from 2 VGAs. However, adopting such a fanout architecture that utilizes a plurality VGAs can create other challenges, such as VGA gain mismatch and bandwidth mismatch. 
     As illustrated, the network transceiver device  12  further includes the plurality of FFEs  44 , each of which is coupled to receive a respective output of a corresponding one of the plurality of ADCs  32  in either an even channel or an odd channel. Each FFE  44  is configured to adaptively equalize the output received from the corresponding one of the ADCs  32 . The receiver  20  employs the plurality of FFEs  44  to equalize digital signals received from the plurality of ADCs  32 . Each FFE  44  utilizes a digital finite impulse response filter (FIR) to compensate for pre-cursor and post-cursor inter-symbol interference (ISI). Each FFE  44  generates delayed versions of the input signal that are added back to the signal with proper weights known as equalization coefficients. To address the gain and bandwidth mismatch challenges described above, the network transceiver device  12  utilizes an FFE architecture that computes some FFE equalization coefficients independently for each VGA channel, and commonly for other FFE equalization coefficients, as further described below in relation to  FIG.  4 A . Thus, each FFE utilizes one or more VGA-specific channel equalization coefficients during equalization. It will be appreciated that the first set of coefficient values and second set of coefficient values typically differ in value from each other when computed in this manner. 
     Turning now to  FIG.  4 A , each FFE  44  may be configured to adaptively equalize the output received from the corresponding one of the ADCs  32  utilizing a plurality of equalization coefficients  100 . The equalization coefficients  100  include a first equalization coefficient subset  102  with coefficient values that are common to all FFEs  44 , and a second equalization coefficient subset that is channel specific and that has a first set  104  of coefficient values for the odd channel and a second set  106  of coefficient values for the even channel. The first and second set of coefficient values are computed independently of each other as described below. 
     In the depicted configuration as described in  FIG.  3   , two VGAs  30 , a plurality of ADCs  32  coupled to each VGA  30 , and a plurality of FFEs  44  respectively coupled to each ADC, are employed. Each FFE  44  may be implemented with multiple tap filters and multiple tap coefficients, with the FFE taps including a main cursor, as well as pre-cursor and post-cursor taps. In the depicted configuration, the FFEs  44  are implemented with twenty taps and twenty coefficients, with the taps including five pre-cursors and fourteen post-cursors. Other tap variations are possible. In an architecture that employs only one VGA, it will be appreciated that the same coefficient values would be applied for all channels. However, the use of a plurality of VGAs  30  in network transceiver device  12  causes VGA gain mismatch and bandwidth mismatch to be introduced, as discussed above. To address these mismatch challenges when two VGAs are used as illustrated, two sets of coefficients, one for the odd channels and one for the even channels, are created as described in relation to  FIG.  4 A . The values of the coefficients between these two sets are the same except for the coefficients of the pre-cursor, main cursor, and post-cursor. In the depicted configuration, the values of the five coefficients of the pre-cursor, main cursor and post-cursor are different. The coefficient values  104 ,  106  of the pre-cursor, main cursor, and post-cursor for the odd and even channels are computed independently of each other. Additional coefficients can be changed in the pre-cursors and post-cursors of the odd and even channels to improve the correction of the VGA gain and bandwidth mismatches. Further, in implementations in which more than two VGAs are provided, it will be appreciated that more than two channels will be created, and in such implementations a set of coefficients will be generated for each channel corresponding to each VGA. Thus, if four VGAs are provided, four coefficient sets would be generated corresponding to four different ADC subsets. In such embodiments, these additional VGA-specific channels may be referred to as a third, fourth, etc. VGA-specific channels. 
     The sets of coefficients can be generated using the following techniques. The first and second sets of coefficient values can be computed to minimize a squared error associated with an ADC sample of analog input signal. For example, the squared error may be computed based on the following: 
               e   k   2     =       [       EQTARG   [     d   k     ]     -     (         ∑     m   =   0     nffe             hffe   m     ⁢     ADC     k   -   m           -       ∑     i   =   1     m             hdfe   j     ⁢     d     k   -   1             )       ]     2           
In the above equation:
         hffe m  is an FFE coefficient;   hdfe i  is a DFE coefficient;   ADC k  is a k th  ADC sample (i.e., a current sample from a current time step);   ADC k-m  is an ADC sample corresponding to (k-m)th input signal sample;   EQTARG[d k ] is an equalization target for the FFE equalization corresponding to one of the four PAM levels;   d k  is an output of the DFE data slicer at time interval k;   d k-i  is an output of the DFE data slicer at time interval k-i;   m is an index of FFE coefficients; and   n is a number of DFE taps.       

     In the depicted configuration as described in  FIG.  4 B , a first ADC bus  150  from a current timestep n, and second ADC bus  152  from a prior time step n−1 are stored and made accessible to the FFEs  44 . Each ADC bus  150 ,  152  contains an array of ADC values from the respective time step. While arrays of 32 values are shown, other sized buses may be utilized. In  FIG.  4 B  adco 0  refers to the output of the ADC zero at timestep n, and adco p  refers to the output of ADC zero at the “previous” timestep n−1, and so forth. In this example, the FFEs  44  are implemented with twenty taps and twenty coefficients, organized into two sets of coefficients, one for the odd channels and one for the even channels. The values of the coefficients between these two sets are the same except for the coefficients of the pre-cursor, main cursor, and post-cursor in this example. In the depicted configuration, the values of the three coefficients of the pre-cursor, main cursor and post-cursor are different, and are labeled with “o” for odd channel coefficients and “e” for even channel coefficients. In  FIG.  4 B , hffe 13   o , hffe 14   o , and hffe 15   o  are the coefficients of the pre-cursor, main cursor, and post-cursor for the odd channels, while hffe 13   e , hffe 14   e , and hffe 15   e  in  FIG.  4 B  are the coefficients of the pre-cursor, main cursor, and post-cursor for the even channels. The values of hffe 13   o , hffe 14   o , and hffe 15   o  are computed independently from those of hffe 13   e , hffe 14   e , and hffe 15   e . 
     FFE equalized outputs FFEQ may be generated by multiplying ADC samples with FFE coefficients. For example, equalized output FFEQ 27   p  corresponding to adco 27   p  which corresponds to an odd channel may be computed by a first matrix multiplication  154  in  FIG.  4 B , which it will be appreciated multiplies the upper array by the lower array within the brackets of  154 . Equalized output FFEQ 28   p  corresponding to adco 28   p  which corresponds to an even channel may be computed by a second matrix multiplication  156  in  FIG.  4 B , which it will be appreciated multiplies the upper array by the lower array within the brackets of  156 . In  FIG.  4 B , hffe 14   o  and hffe 14   e  correspond to FFE coefficients for the main cursor in the odd and even VGA-specific channels, respectively. The DFE  46  compensates for a first tap post-cursor (assuming that one DFE tap at first post-cursor is used) and generates the equalized output. For example, the equalized output corresponding to adco 27   p  may be computed as follows.
 
 EQ   27   p   =FFEQ   27   p   −hdfe*d   26   p  
 
Similarly, the equalized output for adco 28   p  may be computed as follows.
 
 EQ   28   p   =FFEQ   28   p   −hdfe*d   27   p  
 
In these equations, hdfe is a DFE coefficient and “d” represents a DFE slicer decision for the equalized output, i.e., positive or negative 1. The error for each equalized output may be computed. For example, the error corresponding to adco 27   p  may be computed as follows.
 
 Err   27   p   =EQTARG   27   p −( FFEQ   27   p   −hdfe*d   26   p )
 
The error corresponding to adco 28   p  may be computed as follows.
 
 Err   28   p   =EQTARG   28   p −( FFEQ   28   p   −hdfe*d   27   p )
 
Similarly, a set of thirty-two errors for thirty-two ADCs  32  are generated as follows.
 
[ Err   27   p   ,Err   28   p   ,Err   29   p   ,Err   30   p   ,Err   31   p   ,Err   0   ,Err   1   . . . ,Err   26 ]
 
Based on this error set, the following three sets of errors (err, err o , and err e ) are generated.
 
 err=Err   27   p   +Err   28   p   +Err   29   p   +Err   30   p   +Err   31   p   +Err   0   + . . . +Err   26  
 
 err   o   =Err   27   p   +Err   29   p   +Err   31   p   +Err   1   + . . . +Err   25  
 
 err   e   =Err   28   p   +Err   30   p   +Err   0   +Err   2   + . . . +Err   26  
 
It will be appreciated that “err” is used by the least mean square adaptation module  50  to compute and adapt all FFE coefficients except hffe 13 , hffe 14 , and hffe 15 . Similarly, “err o ” is used to compute and adapt hffe 13   o , hffe 14   o , and hffe 15   o  for an odd channel, and “err e ” is used to compute and adapt hffe 13   e , hffe 14   e , and hffe 15   e  for an even channel. While in this example three coefficients are independently computed for even and odd channels, it will be appreciated that another number of such coefficients may be independently computed. And, while odd and even channel examples are used, these should be understood to be VGA-specific channels, as more than two VGA-specific channels may be used in some configurations.
 
     As discussed above briefly in relation to  FIG.  2   , the network transceiver device  12  further includes the CDR circuit  36  coupled on an input side and output side of the plurality of the ADCs  32 . As shown in detail in  FIG.  5   , the CDR circuit  36  includes a phase detector  40  configured to detect a phase of a signal received from each of the ADCs  32 . The phase detector  40  of the CDR circuit  36  is configured to determine a timing of an impulse response in the received signal from the ADC  32  utilizing at least two precursor coefficients, a main coefficient, and at least two post cursor coefficients. The phase detector  40  compares the phase between input data and a recovered sampling clock data and generates up and down signals based on the phase difference between the input data and the clock data and provides information to a phase interpolator  38  to adjust the sampling clock&#39;s phase. The phase interpolator  38  is configured to generate a recovery clock signal by controlling a phase of a reference clock signal based on the phase information provided by the phase detector  40 . The phase interpolator  38  outputs signals to a CML-to-CMOS converter  124  which converts a limited swing signal to a full swing CMOS signal, suitable for use with standard CMOS logic. Multiple sample clock signals are generated utilizing a pulse divider  126  and pulse generator  128  and supplied to the ADCs  32 . In the depicted embodiment, the CDR circuit  36  generates sixty-four clock pulses for the 64 ADCs  32 . 
       FIG.  7    illustrates an example of clock pulses generated and output to drive the timing of the VGAs, in the case of two VGAs being provided, labeled VGA 0  and VGA 1  in the figure. As shown, the clock pulses ping pong, that is, alternate back and forth between VGA 0  and VGA 1 .  FIG.  8    illustrates an example of the clock pulses for a first set of 16 ADCs in the 64 ADCs. The remaining ADCs utilize similar clock pulses for their timing. For scale reference, unit intervals of 8UI, 4UI and 2UI and 64UI are labeled.  FIG.  9    illustrates four set of 16 ADCs  32  arranged downstream of the two VGAs. It will be appreciated that since the VGAs are driven on a ping pong timing according to the clock signals of  FIG.  7   , and because the ADCs are driven according to the clock in  FIG.  8   , that each of the 64 ADCs are driven in successive order, with the even channel and odd channel ADCs alternating the drive order. While ADC 0  is illustrated at the top in the first set of ADCs associated with VGA 0  (corresponding to the even channel), it will be appreciated that ADC 1 , ADC 2 , and ADC 3  (hidden in the figure) are respectively provided in different ADC sets associated with VGA 0  and VGA 1  (corresponding to the odd channel). Retimers  140  are provided downstream of each bank of 8 ADCs in each of the even and odd channels in a 16 ADC set, to re-time the output of the ADCs based on the CDR circuit  36  output. Retimer  142  is provided to synchronize and re-time the signals coming from each of the four sets of ADCs, also based on the CDR circuit  36  output. 
     Returning to  FIG.  5   , the phase detector  40  may operate according to a predetermined timing recovery scheme. One possible timing scheme is a Mueller-Muller timing recovery scheme. The Mueller-Muller timing recovery scheme takes into account one pre-cursor and one post-cursor, as detailed below. Alternatively, for greater accuracy, the phase detector may be a Multiple Pre/Post Cursor Phase detector that takes into account at least two precursor coefficients, a main coefficient, and at least two post cursor coefficients, as detailed below.  FIG.  6    illustrates the main cursor, two precursors, and two post cursors in an example impulse response signal.
 
Δτ k   =A   k-1 ( x   k   −x   k-2 )(Post= A   k-1   x   k   ,Pre=A   k-1   x   k-2 )  Mueller-Muller Phase Detector:
 
Timing Update: Δτ k   =f ( h   −2   ,h   −1   ,h   0   ,h   1   h   2 )  Multiple Pre/Post Cursor Phase Detector:
 
     Returning to  FIG.  5   , the CDR circuit  36  may further include a skew correction module  130 , which is configured to correct skew among the samples from the ADCs. It will be appreciated that the multiple sample clock signals may be generated in either a differential timing mode or a common timing mode. In the differential timing mode, differences in the timing among each ADC in a particular VGA-specific channel (even or odd) within a particular set of ADCs are corrected, wherein in the common timing mode, differences between the different sets of ADCs are corrected. Typically, the corrections according to the differential timing mode are implemented at the retimers  140  and corrections for the common timing mode are implemented at the retimer  142 . Each of these modes takes both pre-cursor and post-cursor timing errors into consideration in order to correct sample skew. Details for the common mode timing update and differential mode timing update follow.
 
Δτ k =Σ i=1   NADC Δτ err   Common Mode Timing Update
 
Timing Update: [Δτ k   1 ,Δτ k   2 , . . . ,Δτ k   NS ]=[Σ i=1,5 . . .    NADC Δτ err ,Σ i=2,6, . . .    NADC Δτ err , . . . ,Σ i=4,8, . . .    NADC Δτ err ]  Differential Mode Timing Update:
 
       FIG.  10    shows a flowchart of an example signal processing method  200  that may be performed at the receiver  20  of the network transceiver device  20  in  FIG.  2   . Alternatively, the method  200  may be performed on other suitable hardware. At step  202 , the method  200  may include amplifying received signals at at least two variable gain amplifiers (VGAs). At step  204 , the method  200  may further include receiving amplified signals from the VGAs at at least two sets of analog digital converters (ADCs), and performing analog digital conversion at each ADC according to a timing signal received from the CDR circuit, as discussed below. Each set includes a plurality of ADCs coupled to a respective output of a corresponding one of the plurality of VGAs. The sets of ADCs may be arranged in at least one first VGA-specific channel, such as the even channel discussed above, and at least one second VGA-specific channel, such as the odd channel discussed above. At step  206 , the method  200  may further include receiving signals from the plurality of ADCs at a plurality of feed-forward equalizers (FFEs) in either the first VGA-specific channel or the second VGA-specific channel. At step  208 , the method  200  may further include receiving signals from the plurality of the FFEs at a plurality of decision feedback equalizers (DFEs). At  210 , the method may include equalizing the output of the ADCs using the FFE, DFE and/or MLSE equalization discussed above, to generate an equalized digital signal, which may contain PAM-4 encoded data. To achieve this equalization at  210 , at step  212 , the method  200  may further include equalizing adaptively an output received from the corresponding one of the ADCs at each FFE, utilizing a plurality of equalization coefficients. The equalization coefficients may include a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for the first VGA-specific channel and a second set of coefficient values for the second VGA-specific channel. The first and second set of coefficient values are computed independently of each other. At step  214 , the method  200  may further include equalizing a respective output of a corresponding one of the plurality of FFEs in either a VGA-specific channel, for example an even channel or an odd channel, at each DFE. Though not shown in detail in  FIG.  10   , the method may also include performing MLSE equalization, as discussed above. Following equalization, at step  216 , the method  200  may further include recovering clock data and generating a timing signal based thereon, which is fed to control timing of the ADCs. Example substeps that may be performed to accomplish step  216  are discussed below in relation to  FIG.  11   . Finally, at step  218 , the method  200  may further include outputting data, e.g., a PAM-4 symbol or data contained within a PAM-4 symbol, based on the equalized digital signal. 
       FIG.  11    shows a flowchart of an example substeps of step  216  of the signal processing method  220  of  FIG.  10   , which may be performed at the clock data recovery (CDR) circuit  36  of the network transceiver device  20  in  FIG.  2   , or using other suitable hardware. At step  222 , the method may include receiving a sample signal from the output of each ADC at a clock data recovery (CDR) circuit. At step  224 , the method may further include generating, via the CDR circuit, a channel timing signal and an ADC timing signal, the channel timing signal alternating between a first VGA-specific channel and a second VGA-specific channel, e.g., between even and odd channels corresponding to the at least two VGAs, as shown in  FIG.  7   . The ADC signal may include pulses that increment through each of the plurality of ADCs in the at least two ADC sets, as shown in  FIG.  8   . At step  226 , the method may further include driving the plurality of ADCs in each ADC set using the channel timing signal and the ADC timing signal, which results in the interleaved ADC sequence discussed above. 
     The above systems and methods may be implemented to achieve increased throughput in a network transceiver device, while addressing gain mismatch and bandwidth mismatch that can occur from using an ADC fanout architecture including multiple parallel VGA channels. In particular, such an approach is believed to be applicable to achieve data transmission rates of 112 Gbps and higher using PAM-4 encoding, although it may also be applied to lower transmission rates if desired. 
     The computing devices  16  described above may be any suitable computing device, including a processor, volatile memory, and non-volatile memory, and instructions as software or firmware for example, stored in such memory, and executable via the processor to achieve the functions described herein, and may take the form of desktops, laptops, servers, routers, switches, network appliances, tablet computers, smartphones, etc. The network transceiver devices  12  described above may be integrated within the housings of the computing devices and connected via an interconnect to a I/O board, motherboard, daughterboard etc., of such devices. In some particular configurations, the network transceiver device may be an ethernet card, network transceiver module, network adaptor, or similar device. 
     The following paragraphs discuss several aspects of the present disclosure. According to one aspect of the present disclosure, a network transceiver device is provided. The network transceiver device may include at least two variable gain amplifiers (VGAs) configured to amplify received signals. The network transceiver device may further include at least two sets of analog digital converters (ADCs), each set including a plurality of ADCs coupled to a respective output of a corresponding one of the plurality of VGAs, the sets of ADCs being arranged in at least a first VGA-specific channel and at least a second VGA-specific channel. The network transceiver device may further include a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive a respective output of a corresponding one of the plurality of ADCs in either the first VGA-specific channel or the second VGA-specific channel, each FFE being configured to adaptively equalize the output received from the corresponding one of the ADCs utilizing a plurality of equalization coefficients, the equalization coefficients including a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for the first VGA-specific channel and a second set of coefficient values for the second VGA-specific channel, the first and second set of coefficient values being computed independently of each other. 
     According to this aspect, the network transceiver device may further include a Continuous Time Linear Equalizer (CTLE) coupled on input side of the plurality of the VGAs. 
     According to this aspect, the network transceiver device may further include a plurality of decision feedback equalizers (DFEs), each DFE being coupled to receive a respective output of a corresponding one of the plurality of FFEs in either the first VGA-specific channel or the second VGA-specific channel. 
     According to this aspect, the network transceiver device may further include a clock data recovery (CDR) circuit coupled on an input side and an output side of the plurality of the ADCs. The CDR circuit is configured to receive ADC sample signal from the output of each ADC and in response thereto, to generate a channel timing signal and an ADC timing signal, the channel timing signal alternating between the first VGA-specific channel and the second VGA-specific channel, and the ADC signal including pulses that increment through each of the plurality of ADCs in the at least two ADC sets. 
     According to this aspect, the CDR circuit may include a phase detector configured to detect a phase of a signal received from each of the ADCs, wherein the phase detector of the CDR circuit is configured to determine a timing of an impulse response in the received signal from the ADC utilizing at least two precursor coefficients, a main coefficient, and at least two post cursor coefficients. 
     According to this aspect, the network transceiver device may further include a maximum likelihood sequence estimation (MLSE) equalizer coupled on output side of the plurality of the DFEs, the MLSE equalizer being configured to correct DFE burst errors in each of the plurality of DFEs. 
     According to this aspect, the network transceiver device may be configured to operate as a four-level pulse-amplitude modulated (PAM-4) transceiver. 
     According to this aspect, the first set of coefficient values and second set of coefficient values may differ in value from each other. 
     According to this aspect, the first set of coefficient values and second set of coefficient values may be computed to minimize a squared error associated with an ADC sample of analog input signal. 
     According to this aspect, the squared error may be computed based on a formula of 
               e   k   2     =       [       EQTARG   [     d   k     ]     -     (         ∑     m   =   0     nffe         hffe   m     ⁢   A   ⁢   D   ⁢     C     k   -   m           -       ∑     i   =   1     m         hdfe   i     ⁢     d     k   -   i             )       ]     2           
and
         hffe m  is an FFE coefficient;   hdfe i  is a DFE coefficient;   ADC k  is a k th  ADC sample;   ADC k-m  is an ADC sample corresponding to (k-m)th input signal sample;   EQTARG[d k ] is an equalization target for the FFE equalization;   d k  is an output of the DFE data slicer at time interval k;   d k-i  is an output of the DFE data slicer at time interval k-i;   m is an index of FFE coefficients; and   n is a number of DFE taps.       

     According to this aspect, the at least two sets of analog ADCs, may include four sets of ADCs, with 16 ADCs included in each of the four sets. 
     According to another aspect of the present disclosure, a signal processing method is provided. The signal processing method may include amplifying received signals at at least two variable gain amplifiers (VGAs). The signal processing method may further include receiving amplified signals from the VGAs at at least two sets of analog digital converters (ADCs), each set including a plurality of ADCs coupled to a respective output of a corresponding one of the plurality of VGAs, the sets of ADCs being arranged in at least one first VGA-specific channel and at least one second VGA-specific channel. The signal processing method may further include receiving signals from the plurality of ADCs at a plurality of feed-forward equalizers (FFEs) in either the first VGA-specific channel or the second VGA-specific channel. The signal processing method may further include equalizing adaptively an output received from the corresponding one of the ADCs at each FFE, utilizing a plurality of equalization coefficients, the equalization coefficients including a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for the first VGA-specific channel and a second set of coefficient values for the second VGA-specific channel, the first and second set of coefficient values being computed independently of each other. 
     According to this aspect, the signal processing method may further include receiving signals from the plurality of the FFEs at a plurality of decision feedback equalizers (DFEs). The signal processing method may further include equalizing a respective output of a corresponding one of the plurality of FFEs in either the first VGA-specific channel or the second VGA-specific channel at each DFE. 
     According to this aspect, the signal processing method may further include receiving a sample signal from the output of each ADC at a clock data recovery (CDR) circuit. The signal processing method may further include generating, via the CDR circuit, a channel timing signal and an ADC timing signal, the channel timing signal alternating between the first VGA-specific channel and the second VGA-specific channel, and the ADC signal including pulses that increment through each of the plurality of ADCs in the at least two ADC sets. The signal processing method may further include driving the plurality of ADCs in each ADC set using the channel timing signal and the ADC timing signal. 
     According to this aspect, the CDR circuit may include a phase detector configured to detect a phase of a signal received from each of the ADCs. The phase detector of the CDR circuit may be configured to determine a timing of an impulse response in the received sample signal from the ADC utilizing at least two precursor coefficients, a main coefficient, and at least two post cursor coefficients. 
     According to this aspect, the signal processing method may be performed in a four-level pulse-amplitude modulated (PAM-4) transceiver. 
     According to this aspect, the first set of coefficient values and second set of coefficient values may differ in value from each other. 
     According to this aspect, the first and second set of coefficient values may be computed to minimize a squared error an ADC sample of analog input signal. 
     According to this aspect, the squared error may be computed based on a formula of 
               e   k   2     =       [       EQTARG   [     d   k     ]     -     (         ∑     m   =   0     nffe         hffe   m     ⁢   A   ⁢   D   ⁢     C     k   -   m           -       ∑     i   =   1     m         hdfe   i     ⁢     d     k   -   i             )       ]     2           
and
         hffe m  is an FFE coefficient;   hdfe i  is a DFE coefficient;   ADC k  is a k th  ADC sample;   ADC k-m  is an ADC sample corresponding to (k-m)th input signal sample;   EQTARG[d k ] is an equalization target for the FFE equalization;   d k  is an output of the DFE data slicer at time interval k;   d k-i  is an output of the DFE data slicer at time interval k-i;   m is an index of FFE coefficients; and   n is a number of DFE taps.       

     According to another aspect of the present disclosure, a network transceiver device is provided. The network transceiver device may include at least two variable gain amplifiers (VGAs) configured to amplify received signals. The network transceiver device may further include at least two sets of analog digital converters (ADCs), each set including a plurality of ADCs coupled to a respective output of a corresponding one of the plurality of VGAs, the sets of ADCs being arranged in at least a first VGA-specific channel and at least a second VGA-specific channel. The network transceiver device may further include a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive a respective output of a corresponding one of the plurality of ADCs in either the first VGA-specific channel or the second VGA-specific channel, each FFE being configured to adaptively equalize the output received from the corresponding one of the ADCs utilizing one or more VGA-specific channel equalization coefficients. 
     According to another aspect of the present disclosure, a network transceiver device is provided. The network transceiver device may include at least two variable gain amplifiers (VGAs) configured to amplify received signals. The network transceiver device may further include at least two sets of analog digital converters (ADCs), each set including a plurality of ADCs coupled to a respective output of a corresponding one of the plurality of VGAs, the sets of ADCs being arranged in at least a first VGA-specific channel and a second VGA-specific channel. The network transceiver device may further include a clock data recovery (CDR) circuit coupled to each of the plurality of ADCs, wherein the CDR circuit is configured to receive an ADC sample signal from each of the plurality of ADCs, and in response is configured to generate a channel timing signal and an ADC timing signal, the channel timing signal alternating between the first VGA-specific channel and the second VGA specific channel, and the ADC timing signal including pulses that increment through each of the plurality of ADCs in the at least two sets of ADCs. 
     According to this aspect, each CDR circuit may include a phase detector configured to detect a phase of a signal received from each of the ADCs. 
     According to this aspect, the network transceiver device may further include the phase detector of each CDR circuit is configured to determine a timing of an impulse response in the received signal from the ADC utilizing at least two precursor coefficients, a main coefficient, and at least two post cursor coefficients. 
     According to this aspect, the network transceiver device may further include a skew correction module configured to correct skew among samples from the ADCs taking into consideration both pre-cursor and post-cursor timing errors in order to correct sample skew. 
     According to this aspect, the skew correction module may operate in either a differential timing mode or a common timing mode. 
     According to this aspect, in the differential timing mode, differences in the timing among each ADC in a particular VGA-specific channel within each of the at least two sets of ADCs may be corrected. 
     According to this aspect, in the common timing mode, differences between the at least two sets of ADCs may be corrected. 
     According to this aspect, the network transceiver device may further include a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive a respective output of a corresponding one of the plurality of ADCs in either the first VGA-specific channel or the second VGA-specific channel, each FFE being configured to adaptively equalize the output received from the corresponding one of the ADCs utilizing a plurality of equalization coefficients, the equalization coefficients including a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for the first VGA-specific channel and a second set of coefficient values for the second VGA-specific channel, the first and second set of coefficient values being computed independently of each other. 
     According to this aspect, the first set of coefficient values and second set of coefficient values may differ in value from each other. 
     According to this aspect, the first and second set of coefficient values may be computed to minimize a squared error associated with an ADC sample of analog input signal. 
     According to this aspect, the network transceiver device may be configured to operate as a four-level pulse-amplitude modulated (PAM-4) transceiver. 
     According to another aspect of the present disclosure, a signal processing method is provided. The signal processing method may include amplifying received signals at at least two variable gain amplifiers (VGAs). The signal processing method may further include receiving amplified signals from the VGAs at at least two sets of analog digital converters (ADCs), each set including a plurality of ADCs coupled to a respective output of a corresponding one of the plurality of VGAs, the sets of ADCs being arranged in at least one first VGA-specific channel and at least one second VGA-specific channel. The signal processing method may further include receiving an ADC sample signal from each of the plurality of ADCs at a clock data recovery (CDR) circuit coupled to each of the plurality of ADCs, and in response generating a channel timing signal and an ADC timing signal, the channel timing signal alternating between the first VGA-specific channel and the second VGA specific channel, and the ADC timing signal including pulses that increment through each of the plurality of ADCs in the at least two sets of ADCs. 
     According to this aspect, each CDR circuit may include a phase detector configured to detect a phase of a signal received from each of the plurality of ADCs. 
     According to this aspect, the signal processing method may further include determining a timing of an impulse response in the received signal from the ADC utilizing at least two precursor coefficients, a main coefficient, and at least two post cursor coefficients, using the phase detector of each CDR circuit. 
     According to this aspect, the signal processing method may further include correcting skew among samples from the ADCs taking into consideration both pre-cursor and post-cursor timing errors in order to correct sample skew, using a skew correction module. 
     According to this aspect, the skew correction module may operate in either a differential timing mode or a common timing mode. 
     According to this aspect, in the differential timing mode, differences in the timing among each ADC in a particular VGA-specific channel within each of the at least two sets of ADCs may be corrected. 
     According to this aspect, in the common timing mode, differences between the at least two sets of ADCs may be corrected. 
     According to this aspect, the signal processing method may further include equalizing the output of the plurality of ADCs, to generate an equalized digital signal. 
     According to this aspect, the signal processing method may further include outputting data including a PAM-4 symbol or data contained within a PAM-4 symbol, based on the equalized digital signal. 
     It will be understood that the configurations and/or approaches described herein are exemplary in nature, and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, various acts illustrated and/or described may be performed in the sequence illustrated and/or described, in other sequences, in parallel, or omitted. Likewise, the order of the above-described processes may be changed. 
     The subject matter of the present disclosure includes all novel and non-obvious combinations and sub-combinations of the various processes, systems and configurations, and other features, functions, acts, and/or properties disclosed herein, as well as any and all equivalents thereof.