Patent Publication Number: US-2015076523-A1

Title: Semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a division of and claims the benefit of priority under 35 U.S.C. §120 from U.S. Ser. No. 13/782,318 filed Mar. 1, 2013, and claims the benefit of priority under 35 U.S.C. §119 from Japanese Patent Application No. 2012-170280 filed Jul. 31, 2012; the entire contents of each of which are incorporated herein by reference. 
    
    
     FIELD 
     Embodiments described herein relate generally to a semiconductor device. 
     BACKGROUND 
     Silicon carbide (SiC) has excellent physical properties exhibiting 3 times the band gap, approximately 10 times the breakdown field strength, and approximately 3 times the thermal conductivity compared to silicon (Si). Utilizing these properties of SiC allows a semiconductor device having excellent low-loss and high temperature operation to be realized. 
     A semiconductor device in which such SiC is used may also be considered for a configuration that has embedded transistors of different conductivity types (for example, a complementary metal oxide semiconductor (CMOS)). 
     Improvement in different switching characteristics is important in a semiconductor device that uses SiC. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A and 1B  are schematic views illustrating examples of configurations of a semiconductor device according to a first embodiment; 
         FIG. 2  is a diagram illustrating a relationship between gate voltage and carrier mobility; 
         FIGS. 3A and 3B  are diagrams illustrating a CMOS inverter; 
         FIGS. 4A to 4C  schematically illustrate an example of a method for manufacturing the semiconductor device; 
         FIGS. 5A and 5B  are schematic views illustrating examples of configurations of a semiconductor device according to a second embodiment;  FIGS. 6A and 6B  are schematic views illustrating examples of configurations of a semiconductor device according to a third embodiment; 
         FIGS. 7A to 7C  schematically illustrate an example of a method for manufacturing the semiconductor device; 
         FIG. 8  is a schematic view illustrating an example of a configuration of a semiconductor device according to a fourth embodiment; and 
         FIGS. 9A and 9B  are schematic cross-sectional views illustrating examples of a configuration of a semiconductor device according to the fourth embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes a first region of a first conductivity type, a second region of the first conductivity type and a third region of a second conductivity type. The first region is disposed along a first crystal face of a silicon carbide region. The silicon carbide region has the first crystal face and a second crystal face having a different plane orientation from the plane orientation of the first crystal face. The second region is disposed along the first crystal face. The third region is provided between the first region and the second region. The third region is disposed along the first crystal face. The second transistor includes a fourth region of the second conductivity type, a fifth region of the second conductivity type and a sixth region of the first conductivity type. The fourth region is disposed along the second crystal face of the silicon carbide region. The fifth region is disposed along the second crystal face. The sixth region is provided between the fourth region and the fifth region. The sixth region is disposed along the second crystal face. 
     Various embodiments will be described hereinafter with reference to the accompanying drawings. 
     Note that the drawings are schematic or simplified illustrations and that relationships between thicknesses and widths of parts and proportions in size between parts may differ from actual parts. Also, even where identical parts are depicted, mutual dimensions and proportions may be illustrated differently depending on the drawing. 
     Note that in the drawings and specification of this application, the same numerals are applied to constituents that have already appeared in the drawings and have been described, and repetitious detailed descriptions of such constituents are omitted. 
     Further, in the following description, the + and − symbols attached to the notations of n and p indicating the n-type and p-type conductive types show relative high and low impurity concentrations in the conductivity types respectively. 
     Further, in the following description, planes offset in a range of 8 degrees to the crystal face are included in the plane orientation illustrating the crystal face. 
     First Embodiment 
       FIGS. 1A and 1B  are schematic views illustrating examples of configurations of a semiconductor device according to a first embodiment. 
       FIG. 1A  illustrates a schematic perspective view of a semiconductor device  110 , and  FIG. 1B  schematically illustrates a layout of a transistor region. Note that the broken line shown in  FIG. 1A  shows a state prior to removing (etching or the like) a surface  101   a  of an SiC wafer  101 . 
     As illustrated in  FIG. 1A , the semiconductor device  110  according to the first embodiment is provided with a first field effect transistor (first transistor) Tr 1  provided on a silicon carbide region  100  and a second field effect transistor (second transistor) Tr 2  provided on the silicon carbide region  100 . 
     The silicon carbide region  100  has a first crystal face  100   a  and a second crystal face  100   b.  The silicon carbide region  100  includes for example, an SiC wafer (substrate)  101  and a crystal layer  102  provided on the SiC wafer  101 . 
     The polytype of the silicon carbide region  100  is 4H. In other words, the silicon carbide region  100  is a 4H-SiC. In the embodiment, a surface (first face)  101   a  of the SiC wafer  101  is a (000-1) face (C face). The first crystal face  100   a  is one of the crystal face of the 4H-SiC crystal faces which are the silicon carbide region  100  The first crystal face  100   a  is the surface  101 A of, for example, the SiC wafer  101 . In other words, the first crystal face  100   a  is, for example, the (000-1) face of the 4H-SiC. Note that the first crystal face  100   a  may be a surface of a layer of crystal that has grown on the surface  101   a  of the SiC wafer  101 . 
     The second crystal face  100   b  has a different plane orientation from the plane orientation of the first crystal face  100   a.  The second crystal face  100   b  in the embodiment is a face that is orthogonal to the first crystal face  100   a.  The second crystal face  100   b  is, for example, a (11-20) face (a face). In the embodiment, the second crystal face  100   b  is a side face (second base)  102   s  of, for example, the crystal layer  102 . Note that the second crystal face  100   b  may be a face equivalent to the (11-20) face (a face). 
     As illustrated in  FIG. 1B , a first field effect transistor Tr 1  has an n-type (first conductivity type in the embodiment) source region (first region)  11 , an n-type drain region (second region)  12 , a p-type (second conductivity type in the embodiment) channel region (third region)  13  provided between the source region  11  and the drain region  12 . Here, the source region  11 , the drain region  12 , and the channel region  13  are disposed along the first crystal face  100   a.    
     A first gate insulating film (first insulating film)  31  is provided on top of the channel region  13 , and a first gate electrode (first electrode) G 1  is provided on top of the first gate insulating film  31 . The first field effect transistor Tr 1 , when ON state, forms an n-type channel in the channel region  13 . In other words, the first field effect transistor Tr 1  is an n-channel metal oxide semiconductor field effect transistor (MOSFET). Note that in the first field effect transistor Tr 1 , the channel is formed along the first crystal face  100   a . The first field effect transistor Tr 1  may be formed in plurality on the first crystal face  100   a.    
     A second field effect transistor Tr 2  has a p-type source region (fourth region)  21 , a p-type (second conductivity type) drain region (fifth region)  22 , and an n-type channel region (sixth region)  23  provided between the source region  21  and the drain region  22 . The source region  21 , the drain region  22 , and the channel region  23  are disposed along the second crystal face  100   b.    
     A second gate insulating film (second insulating film)  32  is provided on top of the channel region  23  and a second gate electrode (second electrode) G 2  is provided on top of the second gate insulating film  32 . The second field effect transistor Tr 2 , when ON state, forms a p-type channel in the channel region  23 . In other words, the second field effect transistor Tr 2  is a p-type MOSFET. Note that in the second field effect transistor Tr 2 , the channel is formed along the second crystal face  100   b.  The second field effect transistor Tr 2  may be formed in plurality on the second crystal face  100   b.    
     In this manner, with the semiconductor device  110 , transistors having conductivity types appropriate to the respective crystal face is provided for different crystal faces (first crystal face  100   a  and second crystal face  100   b ) of the silicon carbide region  100  In the semiconductor device  110 , an n-channel MOSFET (first field effect transistor Tr 1 ) in which a channel is formed along the first crystal face  100   a  is provided and a p-channel MOSFET (second field effect transistor Tr 2 ) in which a channel is formed along the second crystal face  100   b  is provided. Disposing transistors having a conductivity type appropriate to the respective crystal face allows a sufficient level of performance to be achieved by the transistors having respective conductivity types in the semiconductor device  110  in which SiC is used. 
     A description will be given here of a relationship between a crystal face and the characteristics of a transistor according to conductivity type. 
       FIG. 2  is a diagram illustrating a relationship between gate voltage Vg (V) and carrier mobility μFE (cm2/Vs). 
       FIG. 2  illustrates the gate voltage dependence of carrier mobility for each of an n-channel MOSFET (hereinafter referred to as “n-FET (Si)”) formed along the (0001) face (Si face), an n-channel MOSFET (hereinafter referred to as “n-FET (C)”) formed along the (000-1) face (C face), a p-channel MOSFET (hereinafter referred to as “p-FET (Si)”) formed along the (0001) face (Si face), and a p-channel MOSFET (hereinafter referred to as “p-FET (C)”) formed along the (000-1) face (C face) respectively on a 4H-SiC substrate. 
     First, a description will be given of the mobility of the n-channel MOSFET (hereinafter referred to as “n-FET”). As shown in  FIG. 2 , it can be understood that the mobility of the n-FET (C) is higher than the mobility of the n-FET (Si). 
     Next, a description will be given of the mobility of the p-channel MOSFET (hereinafter referred to as “p-FET”). As shown in  FIG. 2 , the n-FET (C) remains OFF state irrespective of the gate voltage without switching. Therefore, the mobility of the n-FET (C) is zero. 
     Meanwhile, although the p-FET (Si) switches, the mobility thereof is smaller than the mobility of the n-FET (Si) formed along the same (0001) face (Si face). 
     The result from this leads to the assumptions (1) and (2) given below for forming a device using transistors having different conductivity types on a 4H-SiC substrate. Note that the example given here is that of forming a CMOS device. 
     (1) . . . Not suited to forming a CMOS device along the (000-1) face (C face). This is because the p-FET (C) formed along the (000-1) face (C face) does not operate normally. Therefore, in order to form a CMOS on an SiC substrate where the (000-1) (C face) face is the surface requires a technique for disposing the p-FET onto a crystal face other than the (000-1) face (C face). 
     For example, there is a report that the p-FET operates on the (11-20) face that is orthogonal to the (000-1) face (C face) (see for example, M. Noborio et al., IEEE trans. Electron Devices, vol. 56, no. 9, pp. 1953-1958, Sep. 2009). Accordingly, providing a p-FET along on the (11-20) face is one solution. 
     (2) . . . While a CMOS device created along the (0001) face (Si face) will operate, disposing one of an n-FET (Si) or a p-FET (Si) on another crystal face provides at least one advantage of either high performance or high integration. 
     For example, there is a report in which the carrier mobility of an n-FET, when formed on the (11-20) face, is higher than when formed on the (0001) face (Si face) (see for example, M. Noborio et al., IEEE trans. Electron Devices, vol. 56, no. 9, pp. 1953-1958, Sep. 2009). Accordingly, providing an n-FET on the (11-20) face and providing a p-FET on the (0001) face (Si face) improve the operating speed of the CMOS. 
     Also, a similar effect is provided by providing an n-FET on the (000-1) face (C face) and providing a p-FET on the (0001) face (Si face). 
     In the semiconductor device  110  according to the embodiment, transistor characteristics of respective conductivity types can be sufficiently demonstrated by using the relationship between the crystal face of the SiC and the characteristics of an n-FET and a p-FET as described above. In other words, in the semiconductor device  110 , the n-FET, which is the first field effect transistor Tr 1 , is provided along (000-1) face which is the first crystal face  100   a,  and the p-FET, which is the second field effect transistor Tr 2 , is provided along (11-20) face which is the second crystal face  100   b.  By this, the characteristics of the semiconductor device  110  are improved when providing transistors having different conductivity types when using SiC. 
     In addition, the integration level of a CMOS circuit is improved when providing the p-FET on the (11-20) face. The p-FET has lower carrier mobility then the n-FET. Therefore, the channel width of the p-FET is preferred to be wider than the channel width of the n-FET. As with the semiconductor device  110  according to the embodiment, providing the p-FET on the (11-20) face that is orthogonal to the surface  101   a  of the SiC wafer  101  makes the direction of the channel width of the p-FET to be orthogonal to the surface  101   a . Accordingly, the occupied area of an entire CMOS is reduced compared to the case when the direction of the channel width of the p-FET is in the direction along the surface  101   a.    
       FIGS. 3A and 3B  are diagrams illustrating a CMOS inverter. 
       FIG. 3A  shows a circuit diagram of the CMOS inverter, and  FIG. 3B  shows the input/output characteristics of the CMOS inverter. 
       FIG. 3B  shows the input/output characteristics of a CMOS inverter  190  according to a reference example in which the n-FET and p-FET of the CMOS inverter for the circuit shown in  FIG. 3A  are provided along the (0001) face (Si face), and it shows the input/output characteristics of a CMOS inverter  111  in which the n-FET is provided along (000-1) face (C face) and the p-FET is provided along (0001) face (Si face). 
     As illustrated in  FIG. 3B , it can be understood that the CMOS inverter  111  in which the n-FET and p-FET are provided on mutually different crystal faces has favorable inverter characteristics compared to the CMOS inverter  190  in which the n-FET and p-FET are provided on the same crystal face. 
     Next, a method for manufacturing the semiconductor device  110  will be described. 
       FIGS. 4A to 4C  schematically illustrate an example of a method for manufacturing the semiconductor device. 
     Note that the broken lines shown in  FIGS. 4A to 4C  show a state prior to removing (etching or the like) a surface  101   a  of an SiC wafer  101 . 
     First, an SiC wafer  101  is prepared as illustrated in  FIG. 4A . The SiC crystal polymorph of the SiC wafer  101  is 4H. The surface  101   a  of the SiC wafer  101  is the (000-1) face. 
     Next, p-type impurities are implanted into a portion of the surface  101   a  of the SiC wafer  101  by photolithography and ion implantation processes. By this, a p-type region  101 P is formed on the SiC wafer  101 . 
     Next, as illustrated in  FIG. 4B , the crystal layer  102  is formed using, for example, epitaxial growth, by introducing n-type impurities onto the surface  101   a  of the SiC wafer  101 . Subsequently, a photolithography process is followed by an etching process to remove a portion of the crystal layer  102  to thereby expose the surface  101 Pa of the p-type region  101 P. The surface  101 Pa is the first crystal face  100   a.    
     Furthermore, removing a portion of the crystal layer  102  forms the side face  102   s  of the crystal layer  102 . The side face  102   s  is the second crystal face  100   b.  The angle created by the side face  102   s  of the crystal layer  102  and the surface  101 Pa of the p-type region  101 P is not less than 72 degrees and not more than 98 degrees and is preferably close to 90 degrees. In addition, the side face  102   s  of the crystal layer  102  is preferably a face equivalent to the (11-20) face. 
     Next, as illustrated in  FIG. 4C , n-type impurities are introduced onto a portion of the surface  101 Pa of the p-type region  101 P by photolithography and ion implantation processes. By this, the n-type source region  11  and the n-type drain region  12  are formed. The area between the source region  11  and the drain region  12  is where the p-type channel region  13  resides where n-type impurities have not been introduced. 
     In addition, p-type impurities are introduced onto a portion of the side face  102   s  of the crystal layer  102  by photolithography and ion implantation processes. The p-type impurities are introduced, for example, by oblique ion implantation onto the side face  102   s . By this, the p-type source region  21  and the p-type drain region  22  are formed. The area between the source region  21  and the drain region  22  is where the n-type channel region  23  resides where p-type impurities have not been introduced. 
     After the n-type and p-type impurities have been introduced, a high temperature annealing process is performed to activate the impurities. Subsequent processes for gate insulating film deposition, gate electrode deposition, and electrode etching are performed to form the first field effect transistor Tr 1  which is an n-FET on the surface  101 Pa of the p-type region  101 P, and to form the second field effect transistor Tr 2  which is a p-FET on the side face  102   s  of the crystal layer  102 . The semiconductor device  110  is completed after this manner. 
     Note that the semiconductor device  110  becomes a CMOS device with the continuity of the drain region  12  of the first field effect transistor Tr 1  with the drain region  22  of the second field effect transistor Tr 2 . Further, a power device and a CMOS device may be embedded on the same SiC wafer  101  by, for example, creating a power MOSFET in a region other than in the region of the SiC wafer  101  where the CMOS device is created. The CMOS device may be used as a drive circuit and the like to control the embedded power device, or it may be used as an integrated circuit that functions on the SiC wafer  101  by configuring an arithmetic logic circuit or a high-speed memory circuit or the like. 
     Second Embodiment 
       FIGS. 5A and 5B  are schematic views illustrating examples of configurations of a semiconductor device according to a second embodiment. 
       FIG. 5A  illustrates a schematic perspective view of a semiconductor device  120 , and  FIG. 5B  schematically illustrates a layout of a transistor region. Note that the broken line shown in  FIG. 5A  shows a state prior to removing (etching or the like) the surface  101   a  of the SiC wafer  101 . 
     As illustrated in  FIG. 5A , the semiconductor device  120  according to the second embodiment differs in the orientation of the crystal face of the surface  101   a  of the SiC wafer  101  compared to the semiconductor device  110  according to the first embodiment. 
     In other words, in the semiconductor device  120 , the first crystal face  100   a  of the silicon carbide region  100  which is a 4H-SiC is the (0001) face. When the surface  101   a  of the SiC wafer  101  is the first crystal face  100   a,  the crystal face of the surface of the SiC wafer  101  is the (0001) face. Note that the first crystal face  100   a  may be a surface of a layer of crystal that has grown on the surface  101   a  of the SiC wafer  101 . 
     The crystal face of the second crystal face  100   b  of the silicon carbide region  100  in the semiconductor device  120  is the (11-20) face similar to the semiconductor device  110  according to the first embodiment. The second crystal face  100   b  may be a face equivalent to the (11-20) face. 
     As illustrated in  FIG. 5B , the first field effect transistor Tr 1  has an n-type (first conductivity type in the embodiment) source region (first region)  11 , an n-type drain region (second region)  12 , a p-type (second conductivity type in the embodiment) channel region (third region)  13  provided between the source region  11  and the drain region  12 . Here, the source region  11 , the drain region  12 , and the channel region  13  are disposed along the first crystal face  100   a.    
     A first gate insulating film (first insulating film)  31  is provided on top of the channel region  13 , and a first gate electrode (first electrode) G 1  is provided on top of the first gate insulating film  31 . The first field effect transistor Tr 1 , when ON state, forms an n-type channel in the channel region  13 . In other words, the first field effect transistor Tr 1  is an n-FET. In the first field effect transistor Tr 1 , the channel is formed along the first crystal face  100   a.    
     A second field effect transistor Tr 2  has a p-type source region (fourth region)  21 , a p-type drain region (fifth region)  22 , and the n-type channel region (sixth region)  23  provided between the source region  21  and the drain region  22 . The source region  21 , the drain region  22 , and the channel region  23  are disposed along the second crystal face  100   b    
     A second gate insulating film (second insulating film)  32  is provided on top of the channel region  23  and a second gate electrode (second electrode) G 2  is provided on top of the second gate insulating film  32 . The second field effect transistor Tr 2 , when ON state, forms a p-type channel in the channel region  23 . In other words, the second field effect transistor Tr 2  is a p-FET. In the first field effect transistor Tr 2 , the channel is formed along the second crystal face  100   b.    
     In this manner, in the semiconductor device  120 , the n-FET (the first field effect transistor Tr 1 ) is provided along the (0001) face which is the first crystal face  100   a,  and the p-FET (the second field effect transistor Tr 2 ) is provided along (11-20) face which is the second crystal face  100   b.  Disposing transistors having a conductivity type appropriate to the respective crystal face allows a sufficient level of performance to be achieved by the transistors having respective conductivity types in the semiconductor device  120  in which SiC is used. 
     The method for manufacturing the semiconductor device  120  is similar to the method for manufacturing the semiconductor device  110  according to the first embodiment. The method for manufacturing the semiconductor device  120  is similar to the method for manufacturing the semiconductor device  110  other than the use of the SiC wafer  101  in which the crystal face is the (0001) face. 
     In the semiconductor device  120 , a similar circuit configuration to that of the semiconductor device  110  according to the first embodiment may be adopted. In other words, it becomes a CMOS device with the continuity of the drain region  12  of the first field effect transistor Tr 1  with the drain region  15  of the second field effect transistor Tr 2 . Further, a power device and a CMOS device may be embedded on the same SiC wafer  101  by, for example, creating a power MOSFET in a region other than in the region of the SIC wafer  101  where the CMOS device is created. The CMOS device may be used as a drive circuit and the like to control the embedded power device, or it may be used as an integrated circuit that functions on the SiC wafer  101  by configuring arithmetic logic circuit or a high-speed memory circuit or the like. 
     In this manner, in the semiconductor device  120 , an n-channel MOSFET (first field effect transistor Tr 1 ) in which a channel is formed along the first crystal face  100   a  is provided and a p-channel MOSFET (second field effect transistor Tr 2 ) in which a channel is formed along the second crystal face  100   b  is provided. Disposing transistors having a conductivity type appropriate to the respective crystal face allows a sufficient level of performance to be achieved by the transistors having respective conductivity types in the semiconductor device  120  in which SiC is used. 
     In the semiconductor device  120  according to the embodiment, in addition to a similar effect to that of the semiconductor device  110  according to the first embodiment, a beneficial effect is achieved in that mass production of a stable semiconductor device is possible because epitaxial growth on the Si face can be more stably performed than on the C face. 
     Third Embodiment 
       FIGS. 6A and 6B  are schematic views illustrating examples of configurations of a semiconductor device according to a third embodiment. 
       FIG. 6A  illustrates a schematic perspective view of a semiconductor device  130 , and  FIG. 6B  schematically illustrates a layout of a transistor region. Note that the broken line shown in  FIG. 6A  shows a state prior to removing (etching or the like) the surface  101   a  of the SiC wafer  101 . 
     As illustrated in  FIG. 6A , the semiconductor device  130  according to the second embodiment differs in the orientation of the crystal face of the surface  101   a  of the SiC wafer  101  compared to the semiconductor device  110  according to the first embodiment and the semiconductor device  120  according to the second embodiment. 
     In other words, in the semiconductor device  130 , the first crystal face  100   a  of the silicon carbide region  100  which is a 4H-SiC is the (0001) face. When the surface  101   a  of the SiC wafer  101  is the first crystal face  100   a,  the crystal face of the surface of the SiC wafer  101  is the (0001) face. Note that the first crystal face  100   a  may be a surface of a layer of crystal that has grown on the surface  101   a  of the SiC wafer  101 . 
     The crystal face of the second crystal face  100   b  of the silicon carbide region  100  in the semiconductor device  130  is the (11-20) face similar to the semiconductor device  110  according to the first embodiment. Note that the second crystal face  100   a  may be a surface (side face) of a layer of crystal that has grown on the surface  101   a  of the SiC wafer  101   a.    
     As illustrated in  FIG. 6B , the first field effect transistor Tr 1  has a p-type (first conductivity type in the embodiment) source region (first region)  11 , a p-type drain region (second region)  12 , and an n-type (second conductivity type in the embodiment) channel region (third region)  13  provided between the source region  11  and the drain region  12 . Here, the source region  11 , the drain region  12 , and the channel region  13  are disposed along the first crystal face  100   a.    
     A first gate insulating film (first insulating film)  31  is provided on top of the channel region  13 , and a first gate electrode (first electrode) G 1  is provided on top of the first gate insulating film  31 . The first field effect transistor Tr 1 , when ON state, forms a p-type channel in the channel region  13 . In other words, the first field effect transistor Tr 1  is a p-FET. In the first field effect transistor Tr 1 , the channel is formed along the first crystal face  100   a.    
     The second field effect transistor Tr 2  has an n-type source region (fourth region)  21 , an n-type drain region (fifth region)  22 , and a p-type channel region (sixth region)  23  provided between the source region  21  and the drain region  22 . The source region  21 , the drain region  22 , and the channel region  23  are disposed along the second crystal face  100   b    
     A second gate insulating film (second insulating film)  32  is provided on top of the channel region  23  and a second gate electrode (second electrode) G 2  is provided on top of the second gate insulating film  32 . The second field effect transistor Tr 2 , when ON state, forms an n-type channel in the channel region  23 . In other words, the second field effect transistor Tr 2  is an n-FET. In the first field effect transistor Tr 2 , the channel is formed along the second crystal face  100   b.    
     In this manner, the semiconductor device  130  is provided with a p-FET (the first field effect transistor Tr 1 ) where a channel is formed along the (0001) face which is the first crystal face  100   a,  and is provided with an n-FET (the second field effect transistor Tr 2 ) where a channel is formed along the (11-20) face which is the second crystal face  100   b.  Disposing transistors having a conductivity type appropriate to the respective crystal face allows a sufficient level of performance to be achieved by the transistors having respective conductivity types in the semiconductor device  130  in which SiC is used. 
     In the semiconductor device  130  according to the embodiment, in addition to a similar effect to that of the semiconductor device  110  according to the first embodiment, a beneficial effect is achieved in that mass production of a stable semiconductor device is possible because epitaxial growth on the Si face can be more stably performed on the C face. 
     Next, a method for manufacturing the semiconductor device  130  will be described. 
       FIGS. 7A to 7C  schematically illustrate an example of a method for manufacturing the semiconductor device. 
     Note that the broken line shown in  FIGS. 7A to 7C  shows a state prior to removing (etching or the like) the surface  101   a  of the SiC wafer  101 . First, an SiC wafer  101  is prepared as illustrated in  FIG. 7A . The SiC crystal polymorph of the SiC wafer  101  is 4H. The surface  101   a  of the SiC wafer  101  is the (0001) face. 
     Next, p-type impurities are implanted into a portion of the surface  101   a  of the SiC wafer  101  by photolithography and ion implantation processes. By this, a p-type region  101 P is formed on the SiC wafer  101 . 
     Next, as illustrated in  FIG. 7B , a p-type crystal layer  102 P is formed using, for example, epitaxial growth, by introducing p-type impurities onto the surface  101   a  of the SiC wafer  101 . Subsequently, a photolithography process is followed by an etching process to remove a portion of the p-type crystal layer  102 P. The thickness of the p-type crystal layer  102 P that is removed by the etching process is preferred to be thinner than the overall thickness of the p-type crystal layer  102 P. 
     A side face  102 Ps of the p-type crystal layer  102 P that is exposed by the etching process is the second crystal face  100   b . Further, a surface  102 Pa of the p-type crystal layer  102 P that is exposed by the etching process is the first crystal face  100   a.  The angle created by the side face  102 Ps of the p-type crystal layer  102 P and the surface  102 Pa of the p-type region  102 P is not less than  72  degrees and not more than 98 degrees and is preferably close to 90°. In addition, the side face  102 Ps of the p-type crystal layer  102 P is preferably a face equivalent to the (11-20) face. 
     Next, n-type impurities are introduced onto the surface  102 Pa of the p-type crystal layer  102 P adjacent to the side face  102 Ps by photolithography and ion implantation processes. By this, an n-type region  102 N is formed. 
     Next, as illustrated in  FIG. 7C , p-type impurities are introduced onto a portion of the surface of the n-type region  102 N by photolithography and ion implantation processes. By this, the p-type source region  11  and the p-type drain region  12  are formed. The area between the source region  11  and the drain region  12  is where the n-type channel region  13  resides where p-type impurities have not been introduced. 
     In addition, n-type impurities are introduced onto a portion of the side face  102 Ps of the p-type crystal layer  102 P by photolithography and ion implantation processes. The n-type impurities are introduced, for example, by oblique ion implantation onto the side face  102 Ps. By this, an n-type source region  14  and an n-type drain region  15  are formed. The area between the source region  14  and the drain region  15  is where the p-type channel region  16  resides where n-type impurities have not been introduced. 
     After the n-type and p-type impurities have been introduced, a high temperature annealing process is begun to activate the impurities. Subsequent process for gate insulating film deposition, gate electrode deposition, and electrode etching are performed to form the first field effect transistor Tr 1  which is a p-FET on the surface of the n-type region  102 N, and to form the second field effect transistor Tr 2  which is an n-FET on the side face  102 Ps of the p-type crystal layer  102 P. The semiconductor device  130  is completed after this manner. 
     In the semiconductor device  130 , a similar circuit configuration to that of the semiconductor device  110  according to the first embodiment or to that of the semiconductor device  120  according to the second embodiment may be adopted. In other words, it becomes a CMOS device with the continuity of the drain region  12  of the first field effect transistor Tr 1  with the drain region  15  of the second field effect transistor Tr 2 . Further, a power device and a CMOS device may be embedded on the same SiC wafer  101  by, for example, creating a power MOSFET in a region other than in the region of the SiC wafer  101  where the CMOS device is created. The CMOS device may be used as a drive circuit and the like to control the embedded power device, or it may be used as an integrated circuit that functions on the SiC wafer  101  by configuring arithmetic logic circuit or a high-speed memory circuit or the like. 
     Fourth Embodiment 
       FIG. 8  is a schematic view illustrating an example of a configuration of a semiconductor device according to a fourth embodiment. 
       FIGS. 9A and 9B  are schematic cross-sectional views illustrating examples of a configuration of a semiconductor device according to the fourth embodiment. 
       FIG. 9A  illustrates a cross-sectional view of the AA plane illustrated in  FIG. 8 , and  FIG. 9B  illustrates a cross-sectional view of the BB plane illustrated in  FIG. 8 . 
     As illustrated in  FIG. 8 , the semiconductor device  140  according to the fourth embodiment differs in that the first crystal face  100   a  and the second crystal face  100   b  are mutually parallel compared to the semiconductor device  110  according to the first embodiment. 
     In the semiconductor device  140 , the first crystal face  100   a  of the silicon carbide region  100  which is a 4H-SiC is the (000-1) face, and the second crystal face  100   b  is the (0001) face. Note that the first crystal face  100   a  may be a face equivalent to the (000-1). Note that the second crystal face  100   b  may be a face equivalent to (0001). 
     The silicon carbide region  100  includes a crystal layer  102  provided on, for example, an SiC wafer (substrate)  101  and an SiC wafer  101 . The surface (first face)  101   a  of the SiC wafer  101  is either the (11-20) face or the (1-100) face. The crystal layer  102  has a plurality of side faces  102   s  that are orthogonal to the surface  101   a  of the SiC wafer  101 . One of the plurality of side faces  102   s  is the first crystal face  100   a,  and another one is the second crystal face  100   b.    
     As illustrated in  FIGS. 8 and 9B , the first field effect transistor Tr 1  has an n-type (first conductivity type in the embodiment) source region (first region)  11 , an n-type drain region (second region)  12 , a p-type (second conductivity type in the embodiment) channel region (third region)  13  provided between the source region  11  and the drain region  12 . Here, the source region  11 , the drain region  12 , and the channel region  13  are disposed along the first crystal face  100   a.    
     A first gate insulating film (first insulating film)  31  is provided on top of the channel region  13 , and a first gate electrode (first electrode) G 1  is provided on top of the first gate insulating film  31 . The first field effect transistor Tr 1 , when ON state, forms an n-type channel in the channel region  13 . In other words, the first field effect transistor Tr 1  is an n-FET. In the first field effect transistor Tr 1 , the channel is formed along the first crystal face  100   a.    
     The second field effect transistor Tr 2  has a p-type source region (fourth region)  21 , a p-type (second conductivity type) drain region (fifth region)  22 , and an n-type channel region (sixth region)  23  provided between the source region  21  and the drain region  22 . The source region  21 , the drain region  22 , and the channel region  23  are disposed along the second crystal face  100   b    
     A second gate insulating film (second insulating film)  32  is provided on top of the channel region  23 , and a second gate electrode (second electrode) G 2  is provided on top of the second gate insulating film  32 . The second field effect transistor Tr 2 , when ON state, forms a p-type channel in the channel region  23 . In other words, the second field effect transistor Tr 2  is a p-FET. In the first field effect transistor Tr 2 , the channel is formed along the second crystal face  100   b.    
     In this manner, in the semiconductor device  140 , the n-FET (the first field effect transistor Tr 1 ) is provided along the (000-1) face which is the first crystal face  100   a,  and the p-FET (the second field effect transistor Tr 2 ) is provided along (0001) face which is the second crystal face  100   b.  Disposing transistors having a conductivity type appropriate to the respective crystal face allows a sufficient level of performance to be achieved by the transistors having respective conductivity types in the semiconductor device  140  in which SiC is used. 
     As illustrated in  FIG. 9A , in the semiconductor device  140 , the length (thickness) t 2  of the n-type channel region  23  in a direction parallel to the surface  101   a  is greater than the length (thickness) t 1  of the p-type channel region  13  in a direction parallel to the surface  101   a.  As described above, the p-FET has a carrier mobility that is lower than that of the n-FET. Accordingly, because the length t 2  of the channel region  23  is greater than the length t 1  of the channel region  13  the difference in carrier mobilities between the p-FET and the n-FET can be adjusted. 
     Further, the first gate electrode G 1  is integrally provided with a second gate electrode G 2 . In other words, the gate electrode G is formed so as to cover the side face  102   s  and the top face  102   a  of the crystal layer  102 . Of the gate electrodes G, that opposing the first channel region  13  having the first gate insulating film  31  therebetween is the first gate electrode G 1 , and that opposing the second channel region  23  having the second gate insulating film  32  therebetween is the second gate electrode G 2 . 
     In the semiconductor device  140  according to the embodiment, transistor characteristics of respective conductivity types can be sufficiently demonstrated by using the relationship between the crystal face of the SiC and the characteristics of an n-FET and a p-FET as described above. By this, the characteristics of the semiconductor device  110  are improved when providing transistors having different conductivity types when using SiC. 
     Further, in the semiconductor device  140 , the directions of the respective channel widths of the n-FET and the p-FET are directions that are orthogonal to the surface  101   a  of the SiC wafer  101 . Accordingly, the occupied area of the device is reduced compared to when provided along the surface  101   a  of the SiC wafer  101  in the directions of the respective channel widths of the n-FET and the p-FET. 
     Next, a method for manufacturing the semiconductor device  140  will be described. 
     First, an SiC wafer  101  is prepared as illustrated in  FIG. 8 . The SiC crystal polymorph of the SiC wafer  101  is 4H. The surface  101   a  of the SiC wafer  101  is either the (11-20) face or the (1-100) face. N-type impurities are introduced to the SiC wafer  101 . 
     Next, a portion of the surface  101   a  of the SiC wafer  101  is removed by photolithography and ion implantation processes to form an SiC projection portion  102   t.  The projection portion  102   t  is equivalent to the crystal layer  102 . The projection portion  102   t  is provided in the shape of a fin that extends along the surface  101   a . Note that in place of forming the projection portion  102   t,  the crystal layer  102  may be formed using, for example, epitaxial growth, by introducing an n-type impurities onto the surface  101   a  of the SiC wafer  101 . One of the plurality of side faces of the projection portion  102   t  is the first crystal face  100   a,  and another two are the second crystal faces  100   b.    
     Next, after photolithography has completed, n-type impurities are introduced onto a portion of the first crystal face  100   a  by ion implantation having an oblique incidence angle. By this, the n-type source region  11  and the n-type drain region  12  are formed. The area between the source region  11  and the drain region  12  is where the p-type channel region  13  resides where n-type impurities have not been introduced. 
     Next, n-type impurities are introduced onto a portion of the first crystal face  100   a  by ion implantation having an oblique incidence angle. By this, the p-type source region  21  and the p-type drain region  22  are formed. The area between the source region  21  and the drain region  22  is where the n-type channel region  23  resides where p-type impurities have not been introduced. 
     After the n-type and p-type impurities have been introduced, a high temperature annealing process is performed to activate the impurities. 
     Next, after depositing an SiN layer thicker than the height of the fin shaped projection portion  102   t  on the entire surface of the SiC wafer  101  using, for example, a chemical vapor deposition (CVD) method, the SiN layer is polished by a chemical mechanical polishing (CMP) process to expose the top portion of the fin shaped projection portion  102   t.    
     Next, an SiO 2  film is formed on the top portion of the projection portion  102   t  exposed by a thermal oxidation process. Subsequently, the SiN layer is selectively removed chemically. By this, an insulating film  26  of SiO 2  is provided on the top portion of the projection portion  102   t.  The insulating film  26  functions to provide element isolation between the first field effect transistor Tr 1  and the second field effect transistor Tr 2 . 
     Subsequent processes for gate insulating film deposition, gate electrode deposition, and electrode etching are performed to form the gate electrodes G. By this, the first field effect transistor Tr 1 , which is an n-FET, is provided on the first crystal face  100   a  which is one side face  102   s  of the projection portion  102   t,  and the second field effect transistor Tr 2 , which is a p-FET, is provided on the second crystal face  100   b  which is another side face  102   s  of the projection portion  102   t.  The semiconductor device  140  is completed after this manner. 
     The semiconductor device  140  becomes a CMOS device with the continuity of the drain region  12  of the first field effect transistor Tr 1  with the drain region  15  of the second field effect transistor Tr 2 . Further, a power device and a CMOS device may be embedded on the same SiC wafer  101  by, for example, creating a power MOSFET in a region other than in the region of the SiC wafer  101  where the CMOS device is created. The CMOS device may be used as a drive circuit and the like to control the embedded power device, or it may be used as an integrated circuit that functions on the SiC wafer  101  by configuring an arithmetic logic circuit or a high-speed memory circuit or the like. 
     As described above, the semiconductor device according to the embodiment can improve the switching characteristics of a semiconductor device in which SiC is used. 
     Note also that although embodiments and variations have been described above, the invention is not limited to these. For example, configurations of the above described embodiments or variations which have been added to, removed from, or changed in design in a way that could be easily arrived at by a person skilled in the art, and any appropriate combination of the characteristics of the embodiments is to be construed as being within the scope of the invention. 
     In addition, although a MOSFET was used as an example of the transistor in the embodiment, it also can be applied to a bipolar transistor. Further, in addition to transistors, it can also be applied to diodes. Furthermore, although transistors having appropriate conductivity types for the first crystal face  100   a  and the second crystal face  100   b,  respectively, are provided in the semiconductor devices  110 ,  120 ,  130 , and  140 , transistors having appropriate conductivity types for three or more different crystal faces may also be provided. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.