Patent Publication Number: US-11646317-B2

Title: Integrated circuit device, method, and system

Description:
PRIORITY CLAIM 
     The present application claims the priority of U.S. Provisional Application No. 62/982,488, filed Feb. 27, 2020, which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     An integrated circuit (IC) typically includes a number of semiconductor devices represented in an IC layout diagram. An IC layout diagram is hierarchical and includes modules which carry out higher-level functions in accordance with the semiconductor device&#39;s design specifications. The modules are often built from a combination of cells, each of which represents one or more semiconductor structures configured to perform a specific function. Cells having pre-designed layout diagrams, sometimes known as standard cells, are stored in standard cell libraries (hereinafter “libraries” or “cell libraries” for simplicity) and accessible by various tools, such as electronic design automation (EDA) tools, to generate, optimize and verify designs for ICs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1 A  is a schematic view of an IC layout diagram, in accordance with some embodiments. 
         FIG.  1 B  is a schematic, enlarged view of a portion of an IC layout diagram, in accordance with some embodiments. 
         FIG.  1 C  is a schematic cross-sectional view combined with a schematic circuit diagram of an IC device, in accordance with some embodiments. 
         FIG.  2    is a schematic view of an IC layout diagram, in accordance with some embodiments. 
         FIG.  3 A  is a schematic view of an IC layout diagram, in accordance with some embodiments. 
         FIG.  3 B  is a schematic view of an IC layout diagram, in accordance with some embodiments. 
         FIG.  4 A  is a schematic view of an IC layout diagram, in accordance with some embodiments. 
         FIG.  4 B  is a schematic cross-sectional view combined with a schematic circuit diagram of an IC device, in accordance with some embodiments. 
         FIG.  5    is a flow chart of a method of generating an IC layout diagram, in accordance with some embodiments. 
         FIG.  6    is a perspective view of an example transistor having a fin feature, in accordance with some embodiments. 
         FIG.  7    is a block diagram of an EDA system, in accordance with some embodiments. 
         FIG.  8    is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     A well tap cell, referred to herein as “TAP cell,” is a standard cell which defines a region in a doped well where the doped well is coupled to a bias voltage, such as a power supply voltage. TAP cells are included in an IC layout diagram to improve latch-up immunity of ICs manufactured in accordance with the IC layout diagram. 
     With the current tendency of scaling down semiconductor devices, placement of TAP cells in an IC layout diagram for manufacturing ICs raises one or more considerations including, but not limited to, process bottleneck due to reduced lithography critical dimension (CD), and mixed channel effects. To address one or more of such considerations, in an IC layout diagram in accordance with some embodiments, first TAP cells of a first semiconductor type (e.g., N-type or P-type) are placed in rows and columns, and second TAP cells of a different, second semiconductor type (e.g., P-type or N-type) are placed in elongated configurations or band shapes across multiple columns of the first TAP cells. As a result, in at least one embodiment, it is possible to achieve one or more effects, including, but not limited to, relaxing of process constraints, increasing of latch-up immunity, reducing of areas occupied or blocked by TAP cells, and increasing of areas where standard cells other than TAP cells are placeable. 
       FIG.  1 A  is a schematic view of an IC layout diagram  100  of an IC device, in accordance with some embodiments. The IC layout diagram  100  comprises a plurality of first TAP cells  110 - 117  of a first semiconductor type, and a plurality of second TAP cells  120 ,  121  of a second semiconductor type different from the first semiconductor type. The first TAP cells  110 - 117  are arranged in at least two columns  118 ,  119 . For example, the first TAP cells  110 ,  112 ,  114 ,  116  are arranged in the column  118 , and the first TAP cells  111 ,  113 ,  115 ,  117  are arranged in the column  119 . The columns  118 ,  119  are adjacent each other in a first direction, e.g., X direction, and extend in a second direction, e.g., Y direction, transverse to the first direction. At least one of the second TAP cells  120 ,  121  extends in the X direction between the columns  118 ,  119  over a length L greater than a length L′ of each of the first TAP cells  110 - 117  in the X direction. The at least one of the second TAP cells  120 ,  121  overlaps, in the Y direction along the page, at least one first TAP cell in at least one of the columns  118 ,  119 . 
     In the example configuration in  FIG.  1 A , the second TAP cell  120  is elongated in the X direction, and has a length L in the X direction greater than its height in the Y direction. The second TAP cell  120  overlaps, in the Y direction, the first TAP cells  110 - 117 . For example, the second TAP cell  120  extends continuously in the X direction from a first end  122  to a second end  123  thereof. The first end  122  of the second TAP cell  120  overlaps, in the Y direction, the first TAP cells  110 ,  112 ,  114 ,  116  in the column  118 . The second end  123  of the second TAP cell  120  overlaps, in the Y direction, the first TAP cells  111 ,  113 ,  115 ,  117  in the column  119 . A middle portion  124  of the second TAP cell  120  is between the first end  122  and the second end  123 , and overlaps none of the first TAP cells  110 - 117  in the Y direction. The second TAP cell  121  has an elongated configuration similar to that described above with respect to the second TAP cell  120 . The second TAP cells  120 ,  121  are adjacent each other in the Y direction, and there is no other TAP cell of the second semiconductor type between the second TAP cells  120 ,  121 . The second TAP cells  120 ,  121  sandwich therebetween multiple rows and columns of the first TAP cells, namely, the two columns  118 ,  119 , and four rows formed respectively by the first TAP cells  110  and  111 , the first TAP cells  112  and  113 , the first TAP cells  114  and  115 , and the first TAP cells  116  and  117 . 
     The configuration described above with respect to  FIG.  1 A  is an example, and other configurations are within the scopes of various embodiments. For example, some embodiments include different numbers of first TAP cells in each of the columns  118 ,  119  and/or different numbers of columns of first TAP cells sandwiched between each pair of adjacent second TAP cells  120 ,  121 . In at least one embodiment, at least one of the second TAP cells  120 ,  121  has a configuration different from that described above with respect to  FIG.  1 A . For example, at least one of the first end  122  or second end  123  of the second TAP cell  120  does not overlap the corresponding column  118  or  119  in the Y direction. For another example, the second TAP cells  120 ,  121  have different lengths in the X direction. In a further example, at least one of the second TAP cells  120 ,  121  is not a single second TAP cell extending continuously in the X direction as described with respect to  FIG.  1 A , but instead comprises a series of discrete second TAP cells as described herein with respect to  FIG.  3 B . 
     The IC layout diagram  100  further comprises a plurality of first well regions  130 ,  132 ,  134 ,  136  of the first semiconductor type, and a plurality of second well regions  131 ,  133 ,  135 , 137 ,  139  of the second semiconductor type. The first well regions  130 ,  132 ,  134 ,  136  and the second well regions  131 ,  133 ,  135 , 137 ,  139  extend in the X direction, and are arranged alternatingly in the Y direction. Each of the first TAP cells  110 - 117  is in a corresponding one of the first well regions  130 ,  132 ,  134 ,  136 , and each of the second TAP cells  120 ,  121  is in a corresponding one of the second well regions  131 ,  133 ,  135 , 137 ,  139 . For example, the first TAP cells  110  and  111  are in the first TAP cell  130 , the first TAP cells  112  and  113  are in the first TAP cell  132 , the first TAP cells  114  and  115  are in the first TAP cell  134 , and the first TAP cells  116  and  117  are in the first TAP cell  136 , whereas the second TAP cell  120  is in the second well region  131 , and the second TAP cell  121  is in the second well region  139 . 
     In the example configuration in  FIG.  1 A , the first semiconductor type is N-type and the second semiconductor type is P-type. In other words, the first well regions  130 ,  132 ,  134 ,  136  are N-type well regions (hereinafter “N wells”), the second well regions  131 ,  133 ,  135 , 137 ,  139  are P-type well regions (hereinafter “P wells”), the first TAP cells  110 - 117  are N-type TAP cells (hereinafter “NTAP cells”), and the second TAP cells  120 ,  121  are P-type TAP cells (hereinafter “PTAP cells”). An N well is a region that includes N-type dopants, whereas a P well is a region that includes P-type dopants. In the drawings, N wells are labelled as “NW,” P wells are labelled as “PW,” N-type dopants are labelled as “N+” and P-type dopants are labelled as “P+.” 
     An NTAP cell is a region in an N well, but with a higher concentration of N-type dopants than the N well itself. For example, the NTAP cell  110  has a higher concentration of N-type dopants than the N well  130  in which the NTAP cell  110  is formed. A PTAP cell is a region in a P well, but with a higher concentration of P-type dopants than the P well itself. For example, the PTAP cell  120  has a higher concentration of P-type dopants than the P well  131  in which the PTAP cell  120  is formed. 
     In an N well, P-type active regions with P-type dopants are arranged in areas not occupied or blocked by NTAP cells to form one or more circuit elements. In a P well, N-type active regions with N-type dopants are arranged in areas not occupied or blocked by PTAP cells to form one or more circuit elements. Examples of circuit elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, P-channel and/or N-channel field effect transistors (PFETs/NFETs), etc.), FinFETs, planar MOS transistors with raised source/drains, or the like. For example, in the N wells  130 ,  132 ,  134 ,  136 , P-type active regions (not shown in  FIG.  1 A , but described herein with respect to  FIG.  1 C ) are arranged in the areas not occupied or blocked by the NTAP cells  110 - 117  to define P-channel metal-oxide semiconductor (PMOS) regions for forming PMOS transistors. In the P wells  133 ,  135 ,  137 , N-type active regions (not shown in  FIG.  1 A , but described herein with respect to  FIG.  1 C ) are arranged in the areas not occupied or blocked by the PTAP cells  120 ,  121  to define N-channel metal-oxide semiconductor (NMOS) regions for forming NMOS transistors. A cell having a pre-designed layout diagram is read from a cell library and placed in the IC layout diagram  100  such that NMOS transistors of the cell are arranged in an NMOS region, whereas PMOS transistors of the cell are arranged in a PMOS region. NTAP cells, PTAP cells, N-type active regions and P-type active regions are sometimes commonly referred to as oxide-definition (OD) regions, and are schematically illustrated in  FIG.  1 B  with the label “OD.” 
     The IC layout diagram  100  further comprises gate regions (not shown in  FIG.  1 A , but described herein with respect to  FIG.  1 B ) which include a conductive material, such as, polysilicon, and are schematically illustrated in  FIG.  1 B  with the label “Poly.” Other conductive materials for the gate regions, such as metals, are within the scopes of various embodiments. The gate regions extend, or are elongated, in the Y direction across the OD regions. The Y direction is also referred to herein as the Poly direction. In some embodiments, each OD region has one or more fin features arranged therein. Such fin features extend, or are elongated, in the X direction, and spaced from each other in the Y direction. The X direction is also referred to herein as the Fin direction. An example of a fin feature is described with respect to  FIG.  6   . 
     In at least one embodiment, a number of fin features in each of the first TAP cells  110 - 117  and a number of fin features in each of the second TAP cells  120 ,  121  satisfy the following relationship:
 
 F 2/ F 1≥( DY/DX )*( L/A )  (1)
 
     where 
     F 1  is the number of fin features in each of the first TAP cells  110 - 117 , 
     F 2  is the number of fin features in each of second TAP cells  120 ,  121  which are elongated in the X direction, 
     DX is a half of a first distance  2 *DX in the X direction between facing sides of the first TAP cells in the adjacent columns  118 ,  119 , 
     DY is a half of a second distance  2 *DY in the Y direction between facing sides of the second TAP cells  120 ,  121 , 
     L is the length of the second TAP cell  120  or  121  in the X direction, and 
     A is a cell height in the Y direction, and is a sum of a height A 1  of a first well region (e.g.,  132 ) and a height A 2  of an adjacent second well region (e.g.,  135 ). 
     In the example configuration in  FIG.  1 A , F 1  is the number F NTAP  of fin features in each NTAP cell, and F 2  is the number F PTAP  of fin features in each PTAP cell, and the relationship (1) becomes
 
 F   PTAP   /F   NTAP ≥( DY/DX )*( L/A )  (1′)
 
     By configuring the NTAP cells and PTAP cells to have different configurations and to satisfy the relationship (1) or (1′), it is possible in some embodiments to match or improve a latch-up (LUP) immunity index compared to another approach. Specifically, the LUP immunity index of an IC device corresponding to the IC layout diagram  100  is determined by the following relationship
 
 V=J body* L *( A/ 2)*(2 DY/A )*( Rc/F   PTAP )  (2)
 
     where 
     V is the LUP immunity index represented by a voltage drop caused by a leakage current Jbody in the IC device, and 
     Rc is a unit resistance. 
     The lower the voltage drop V, the better LUP immunity of the IC device. 
     In another approach where the NTAP cells and PTAP cells are configured similarly to each other, and similarly to the NTAP cells  110 - 117 , the LUP immunity index V′ of an IC device in accordance with the another approach is determined by the following relationship
 
 V′=J body*2 DX *( A/ 2)*( Rc/F   NTAP )  (3)
 
     To match or improve the LUP immunity index compared to the another approach, the following relationship is to be satisfied:
 
 V≤V′   (4)
 
     Based on the relationships (2), (3) and (4), the relationships (1′) and (1) are obtained. 
     In some embodiments, the IC layout diagram  100  satisfies at least one of the following: DY is from 0.5 μm to 1000 μm, DX is from 0.05 μm to 100 μm, L is from 0.1 μm to 5000 μm, or A is from 0.025 μm to 0.300 μm. The range of 0.025 μm to 0.300 μm of the cell height A corresponds to one or more considerations and/or constraints in an example semiconductor manufacturing process. At the range of 0.025 μm to 0.300 μm of the cell height A, if DX is below the range of 0.05 μm to 100 μm and/or if DY is below the range of 0.5 μm to 1000 μm, there is an excessive increase in the chip area of TAP cells with an associated decrease in the remaining chip area for other functional cells of the IC layout diagram  100 . At the range of 0.025 μm to 0.300 μm of the cell height A, if DX is above the range of 0.05 μm to 100 μm and/or if DY is above the range of 0.5 μm to 1000 μm, there is an elevated risk of latch-up. The range of 0.1 μm to 5000 μm for the length L of the elongated TAP cells (e.g.,  120  or  121 ) is derived from the respective range(s) for A, DX and/or DY based on the relationship (1) or (1′). 
       FIG.  1 B  is a schematic, enlarged view of a portion  140  of the IC layout diagram  100 , in accordance with some embodiments, for describing an example to determine the number of fin features in a TAP cell. The portion  140  includes a well region  141 , an OD region  142 , and a plurality of gate regions  143 ,  144 . The well region  141  extends in the X direction, and surrounds or encloses therein the OD region  142 . The OD region  142  includes one or more fin features (not shown) which extend in the X direction. The OD region  142  has a length Lop in the X direction, and a height W in the Y direction. The gate regions  143 ,  144  extend in the Y direction across the OD region  142 , and are arranged at a pitch CPP in the X direction. 
     The number F of fin features in the OD region  142  is determined by
 
 F =( L   OD   /CPP )* W*Fn   (5)
 
     where Fn is a number of fin features per unit height in the Y direction. In at least one embodiment, CPP and W are the same for all TAP cells. 
     In an example, the portion  140  corresponds to a region containing a first TAP cell, e.g.,  110  in  FIG.  1 A . Specifically, the well region  141  corresponds to the first well region  130 , the OD region  142  corresponds to the first TAP cell  110 , L OD  corresponds to the length L′ of the first TAP cell  110 , W corresponds to the height of the first TAP cell  110  in the Y direction, and F corresponds to F 1  or F NTAP  which is the number of fin features in the first TAP cell  110 . Accordingly, the number of fin features in each first TAP cell is determinable from the relationship (5). 
     In another example, the portion  140  corresponds to a region containing a second TAP cell, e.g.,  120  in  FIG.  1 A . Specifically, the well region  141  corresponds to the second well region  131 , the OD region  142  corresponds to the second TAP cell  120 , L OD  corresponds to the length L of the second TAP cell  120 , W corresponds to the height of the second TAP cell  120  in the Y direction, and F corresponds to F 2  or F PTAP  which is the number of fin features in the second TAP cell  120 . Accordingly, the number of fin features in each second TAP cell is also determinable from the relationship (5). 
       FIG.  1 C  is a schematic cross-sectional view of an IC device  150 , in accordance with some embodiments. The IC device  150  corresponds to a portion of the IC layout diagram  100  which is indicated by arrow Y→Y 1  in  FIG.  1 A . The cross-sectional view in  FIG.  1 C  is also combined with a schematic circuit diagram of the IC device  150 . 
     The IC device  150  comprises a substrate  151  on which the TAP cells, well regions, active regions, gate regions, fin features described with respect to  FIGS.  1 A and  1 B  are formed. For example, the IC device  150  comprises, on the substrate  151 , the N well  134 , P well  137 , N well  136 , and P well  139 . P-type active regions  152 ,  153 , and the NTAP cell  115  are formed in the N well  134 . A gate region  154  is formed over the P-type active regions  152 ,  153 , and defines together with the P-type active regions  152 ,  153  a PMOS. N-type active regions  155 ,  156  are formed in the P well  137 . A gate region  157  is formed over the N-type active regions  155 ,  156 , and defines together with the N-type active regions  155 ,  156  an NMOS. The PTAP cell  121  is formed in the P well  139 . The IC device  150  further comprises a plurality of isolation regions  158  between adjacent P well and N well. The P-type active region  152  of the PMOS is coupled to a first power supply voltage, e.g., VDD. The N-type active region  156  of the NMOS is coupled to a second power supply voltage, e.g., VSS, which is in at least one embodiment, the ground. The substrate  151  is a P-type substrate. 
     The schematic circuit diagram of the IC device  150  in  FIG.  1 C  shows parasitic transistors Q 1  and Q 2 . The parasitic transistor Q 1  is a PNP transistor formed by the P-type active region  152 , the N well  134 , and the P-type substrate  151 . The parasitic transistor Q 2  is an NPN transistor formed by the N well  134 , the P well  137 , and the N-type active region  156 . In the absence of the NTAP cell  115  and/or the PTAP cell  121 , there is a concern that a leakage current in one or more of the P-type substrate  151 , P wells and N wells of the IC device  150  is sufficient to cause both of the parasitic transistors Q 1  and Q 2  to turn ON, and create a current path from VDD, through the turned ON parasitic transistors Q 1  and Q 2 , to VSS. Such a current path between VDD and VSS is a latch-up situation that adversely affects performance of the IC device  150 . 
     The provision of the NTAP cell  115  which is coupled to VDD and the PTAP cell  121  which is coupled to VSS reduces the likelihood of latch-up situations and improves LUP immunity of the IC device  150 . In the schematic circuit diagram of the IC device  150  in  FIG.  1 A , a resistor R NW  represents a TAP cell resistance between the NTAP cells, representative by the NTAP cell  115 , and the base of the parasitic transistor Q 1 , whereas a resistor R Psub  represents a TAP cell resistance between the PTAP cells, representative by the PTAP cell  121 , and the base of the parasitic transistor Q 2 . The lower the resistances of the resistors R NW  and R Psub , the lower the likelihood of the parasitic transistors Q 1  and Q 2  being turned ON, respectively, the better the LUP immunity of the IC device  150 . The resistance of the resistor R NW  depends on a configuration and/or arrangement of NTAP cells. The resistance of the resistor R Psub  depends on a configuration and/or arrangement of PTAP cells. For example, referring to  FIG.  1 A , the resistance of the resistor R Psub  increases when the distance  2 *DY between the adjacent elongated second TAP cells  120 ,  121  increase; however, the resistance of the resistor R Psub  decreases when the length L or the number of fin features of the elongated second TAP cells  120 ,  121  increases. By configuring and/or arranging the NTAP cells and/or PTAP cells as described herein, it is possible in at least one embodiment to improve LUP immunity of the IC device  150 . 
     As described herein, some other approaches for TAP cell placement suffer from some potential problems. For example, in a first approach, TAP cells are placed in a half-cell height arrangement across boundaries between P wells and N wells. Such a half-cell height arrangement faces manufacturing difficulties, especially at CD below 100 nm. In contrast, as described with respect to  FIGS.  1 A- 1 B , the TAP cells in some embodiments are completely enclosed within respective well regions, therefore avoiding manufacturing difficulties associated with the half-cell height arrangement. For another example, in the described first approach and in a different, second approach, there are concerns with respect to mixed channel effects due to implant discontinuity between closely arranged NTAP cells and PTAP cells. Such concerns of mixed channel effects are obviated by one or more embodiments described herein. In some embodiments, it is possible to achieve one or more effects, including, but not limited to, relaxing process constraints especially at advanced manufacturing process nodes, improving latch-up immunity, reducing of areas occupied or blocked by TAP cells, and increasing of areas where standard cells other than TAP cells are placeable. In some still further embodiments, with no process constraints at advanced manufacturing process nodes, it is possible to improve latch-up immunity and/or reduce areas occupied or blocked by TAP cells. In an example, the areas occupied or blocked by TAP cells is reduced, in at least one embodiment, to about 85% of that observed in other approaches, without sacrificing LUP immunity. 
       FIG.  2    is a schematic view of an IC layout diagram  200 , in accordance with some embodiments. The IC layout diagram  200  comprises a plurality of portions  201 ,  201 , . . .  20   n  which are arranged at regular intervals in the X direction and Y direction. TAP cells are placed in each of the portions  201 ,  201 , . . .  20   n  in similar manner. For example, in each of the portions  201 ,  201 , . . .  20   n , TAP cells are placed as described with respect to  FIG.  1 A  in at least one embodiment. Other TAP cell placements as described with respect to  FIGS.  3 A,  3 B, and  4 A , are within the scopes of various embodiments. As a result, TAP cells are placed at regular intervals and in a repeating pattern over the IC layout diagram  200 , to ensure intended LUP immunity over the IC layout diagram  200 . In some embodiments, one or more advantages or effects described with respect to  FIG.  1 A  are achievable in the IC layout diagram  200 . 
       FIG.  3 A  is a schematic view of an IC layout diagram  300 A, in accordance with some embodiments. In at least one embodiment, the IC layout diagram  300 A corresponds to any of the portions  201 ,  201 , . . .  20   n  in  FIG.  2   . Similarly to the IC layout diagram  100 , the IC layout diagram  300 A comprises a plurality of first TAP cells representatively indicated at  310 , and a plurality of second TAP cells  320 ,  321 . The first TAP cells  310  correspond to the first TAP cells  110 - 117  of the IC layout diagram  100 , but are arranged in more than two columns, e.g., four columns  318 ,  319 ,  328 ,  329 . The second TAP cells  320 ,  321  correspond to the second TAP cells  120 ,  121 , and extend in the X direction across the four columns  318 ,  319 ,  328 ,  329  of the first TAP cells  310 . In some embodiments, configurations, modifications, advantages or effects described with respect to  FIG.  1 A  are achievable in the IC layout diagram  300 A. 
       FIG.  3 B  is a schematic view of an IC layout diagram  300 B, in accordance with some embodiments. In at least one embodiment, the IC layout diagram  300 B corresponds to any of the portions  201 ,  201 , . . .  20   n  in  FIG.  2   . Similarly to the IC layout diagram  300 A, the IC layout diagram  300 B comprises a plurality of first TAP cells  310 , which are arranged in four columns  318 ,  319 ,  328 ,  329 . However, instead of each of the continuous second TAP cells  320 ,  321  in the IC layout diagram  300 A, the IC layout diagram  300 B includes a series  330 ,  331  of discrete second TAP cells representatively indicated at  332 ,  333 ,  334 ,  335 . The second TAP cells  332 ,  333 ,  334 ,  335  are arranged in a line along the X direction, at an interval d. The length L of each of the series  330 ,  331  for determining the number of fin features in the series is a total of length m of each second TAP cells  332 ,  333 ,  334 ,  335  in the series. In each of the series, e.g., series  331 , a first end TAP cell  332  at a first end of the series  331  overlaps, in the Y direction, the first TAP cells in one of the columns, e.g., column  318 . A second end TAP cell  335  at a second end of the series  331  overlaps, in the Y direction, first TAP cells in another column  329 . The series  331  further comprises at least one middle TAP cell  334  between the first and second ends of the series  331 , and overlapping no first TAP cell among the first TAP cells in the columns  318 ,  319 ,  328 ,  329 . In some embodiments, configurations, modifications, advantages or effects described with respect to  FIG.  1 A  are achievable in the IC layout diagram  300 B. 
       FIG.  4 A  is a schematic view of an IC layout diagram  400 , in accordance with some embodiments. The IC layout diagram  400  in  FIG.  4 A  is similar to the IC layout diagram  100  in  FIG.  1 A , with the exception that P-type regions, wells or TAP cells in the IC layout diagram  400  correspond to N-type regions, wells or TAP cells in the IC layout diagram  100 , and vice versa. An element in  FIG.  4 A  is denoted by the same reference numeral as a corresponding element in  FIG.  1 A , but with the prime symbol added to  FIG.  4 A . For example, a well region  130 ′ in  FIG.  4 A  corresponds to the well region  130  in  FIG.  1 A . In at least one embodiment, an IC device corresponding to the IC layout diagram  400  is formed on an N-type substrate, as described with respect to  FIG.  4 B . 
       FIG.  4 B  is a schematic cross-sectional view of an IC device  150 ′, in accordance with some embodiments. The IC device  150 ′ corresponds to a portion of the IC layout diagram  400  which is indicated by arrow in  FIG.  4 A . The cross-sectional view in  FIG.  4 B  is also combined with a schematic circuit diagram of the IC device  150 ′. The IC device  150 ′ in  FIG.  4 B  is similar to the IC device  150  in  FIG.  1 C , with the exception that P-type substrate, regions, wells, TAP cells, in the IC device  150 ′ correspond to N-type substrate, regions, wells, TAP cells in the IC device  150 , and vice versa. An element in  FIG.  4 B  is denoted by the same reference numeral as a corresponding element in  FIG.  1 C , but with the prime symbol added to  FIG.  4 B . For example, a substrate  151 ′ in  FIG.  4 B  corresponds to the substrate  151  in  FIG.  1 C . Further, NMOS, PMOS, Q 1 ′(NPN), Q 2 ′(PNP), R PW  and R Nsub  in  FIG.  4 B  correspond to PMOS, NMOS, Q 1 (PNP), Q 2 (NPN), R NW  and R Psub  in  FIG.  1 C , respectively. 
     In some embodiments, configurations, operations, modifications, advantages or effects described with respect to the IC layout diagram  100  in  FIG.  1 A  and/or the IC device  150  in  FIG.  1 C  are achievable in the IC layout diagram  400  in  FIG.  4 A  and/or the IC device  150 ′ in  FIG.  4 B . Some embodiments include IC layout diagrams similar to the IC layout diagram  300 A or  300 B, but with similar changes from P-type substrate, wells, regions or TAP cells to N-type substrate, wells, regions or TAP cells, respectively, and vice versa. 
       FIG.  5    is a flow chart of a method  500  for TAP cell placement in an IC layout diagram, in accordance with some embodiments. In at least one embodiment, the method  500  is performed in whole or in part by a processor as described herein, to generate an IC layout diagram corresponding to at least one of the IC layout diagrams  100 ,  200 ,  300 A,  300 B and  400 . 
     At operation  505 , a plurality of first TAP cells is placed in an IC layout diagram such that the first TAP cells are arranged in two adjacent columns. For example, as described with respect to  FIG.  1 A , a plurality of first TAP cells  110 - 117  is placed in the IC layout diagram  100  such that the first TAP cells  110 - 117  are arranged in two adjacent columns  118 ,  119 . The two adjacent columns  118 ,  119  are adjacent each other in a first direction, e.g., the X direction, and extend in a second direction, e.g., the Y direction, transverse to the first direction. The first TAP cells  110 - 117  are of a first semiconductor type, e.g., N-type as in  FIG.  1 A , or P-type as in  FIG.  4 A . 
     At operation  515 , two second TAP cells of a second semiconductor type different from the first semiconductor type are placed in the IC layout diagram. Each of the two second TAP cells extends continuously between the two adjacent columns of the first TAP cells over a second length greater than a first length of each of the first TAP cells. For example, as described with respect to  FIG.  1 A , two second TAP cells  120 ,  121  are placed in the IC layout diagram  100 . Each of the two second TAP cells  120 ,  121  extends continuously between the two adjacent columns  118 ,  119  of the first TAP cells  110 - 117  over a length L greater than a length L′ of each of the first TAP cells  110 - 117 . The two adjacent columns  118 ,  119  of the first TAP cells  110 - 117  are located between the two second TAP cells  120 ,  121  in the Y direction. The second TAP cells  120 ,  121  are of a second semiconductor type, e.g., P-type as in  FIG.  1 A , or N-type as in  FIG.  4 A . 
     In at least one embodiment, operations  505  and  515  occur concurrently, e.g., in a place and route operation of an IC manufacturing flow. In one or more embodiments, the first TAP cells and/or the second TAP cells are standard cells stored in and read from one or more cell libraries. In some embodiments, operations  505  and  515  are performed to place TAP cells at regular intervals and in a repeating pattern over the IC layout diagram, as described with respect to  FIG.  2   . 
     The described methods include example operations, but they are not necessarily required to be performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiments of the disclosure. Embodiments that combine different features and/or different embodiments are within the scope of the disclosure and will be apparent to those of ordinary skill in the art after reviewing this disclosure. 
       FIG.  6    is a perspective view of an example circuit element  600  having a fin feature, in accordance with some embodiments. In the example configuration in  FIG.  6   , circuit element  600  is a fin field-effect transistor (FINFET). FINFET  600  comprises a substrate  602 , at least one fin feature (or fin)  604  extending in a Z direction from substrate  602 , a gate dielectric  606  along surfaces of fin  604 , and a gate electrode  608  over gate dielectric  606 . A source region  610  and a drain region  612  are disposed over substrate  602  on opposite sides of fin  604 . Fin  604 , source region  610  and drain region  612  belong to an active region (or OD region) which corresponds, in one or more embodiments, to any active region described with respect to  FIGS.  1 A- 4 B . In at least one embodiment, gate electrode  608  corresponds to any gate region described with respect to  FIGS.  1 A- 4 B . The described configuration of a fin feature in an active region is an example. Other configurations are within the scopes of various embodiments. 
     In some embodiments, some or all of the methods discussed above are performed by an IC layout diagram generation system. In some embodiments, an IC layout diagram generation system is usable as part of a design house of an IC manufacturing system discussed below. 
       FIG.  7    is a block diagram of EDA system  700  in accordance with some embodiments. 
     In some embodiments, EDA system  700  includes an automated placement and routing (APR) system. Methods described herein of designing layout diagrams and representing wire routing arrangements, in accordance with one or more embodiments, are implementable, for example, using EDA system  700 , in accordance with some embodiments. 
     In some embodiments, EDA system  700  is a general purpose computing device including a hardware processor  702  and a non-transitory, computer-readable storage medium  704 . Storage medium  704 , amongst other things, is encoded with, i.e., stores, computer program code  706 , i.e., a set of executable instructions. Execution of instructions  706  by hardware processor  702  represents (at least in part) an EDA tool which implements a portion or all of, e.g., the methods described herein in accordance with one or more embodiments (hereinafter, the noted processes and/or methods). 
     Processor  702  is electrically coupled to computer-readable storage medium  704  via a bus  708 . Processor  702  is also electrically coupled to an I/O interface  710  by bus  708 . A network interface  712  is also electrically connected to processor  702  via bus  708 . Network interface  712  is connected to a network  714 , so that processor  702  and computer-readable storage medium  704  are capable of connecting to external elements via network  714 . Processor  702  is configured to execute computer program code  706  encoded in computer-readable storage medium  704  in order to cause EDA system  700  to perform a portion or all of the noted processes and/or methods. In one or more embodiments, processor  702  is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. 
     In one or more embodiments, computer-readable storage medium  704  is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium  704  includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium  704  includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD). 
     In one or more embodiments, storage medium  704  stores computer program code  706  configured to cause EDA system  700  (where such execution represents (at least in part) the EDA tool) to perform a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium  704  also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium  704  stores a library  707  of standard cells, including HPC cells as disclosed herein. 
     EDA system  700  includes I/O interface  710 . I/O interface  710  is coupled to external circuitry. In one or more embodiments, I/O interface  710  includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor  702 . 
     EDA system  700  also includes network interface  712  coupled to processor  702 . Network interface  712  allows EDA system  700  to communicate with network  714 , to which one or more other computer systems are connected. Network interface  712  includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more EDA systems  700 . 
     EDA system  700  is configured to receive information through I/O interface  710 . The information received through I/O interface  710  includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor  702 . The information is transferred to processor  702  via bus  708 . EDA system  700  is configured to receive information related to a UI through I/O interface  710 . The information is stored in computer-readable medium  704  as user interface (UI)  742 . 
     In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EDA system  700 . In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. 
     In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like. 
       FIG.  8    is a block diagram of an integrated circuit (IC) manufacturing system  800 , and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using manufacturing system  800 . 
     In  FIG.  8   , IC manufacturing system  800  includes entities, such as a design house  820 , a mask house  830 , and an IC manufacturer/fabricator (“fab”)  850 , that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device  860 . The entities in system  800  are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house  820 , mask house  830 , and IC fab  850  is owned by a single larger company. In some embodiments, two or more of design house  820 , mask house  830 , and IC fab  850  coexist in a common facility and use common resources. 
     Design house (or design team)  820  generates an IC design layout diagram  822 . IC design layout diagram  822  includes various geometrical patterns designed for IC device  860 . The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device  860  to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram  822  includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house  820  implements a proper design procedure to form IC design layout diagram  822 . The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram  822  is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram  822  is expressed in a GDSII file format or DFII file format. 
     Mask house  830  includes data preparation  832  and mask fabrication  844 . Mask house  830  uses IC design layout diagram  822  to manufacture one or more masks  845  to be used for fabricating the various layers of IC device  860  according to IC design layout diagram  822 . Mask house  830  performs mask data preparation  832 , where IC design layout diagram  822  is translated into a representative data file (“RDF”). Mask data preparation  832  provides the RDF to mask fabrication  844 . Mask fabrication  844  includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)  845  or a semiconductor wafer  853 . The design layout diagram  822  is manipulated by mask data preparation  832  to comply with particular characteristics of the mask writer and/or requirements of IC fab  850 . In  FIG.  8   , mask data preparation  832  and mask fabrication  844  are illustrated as separate elements. In some embodiments, mask data preparation  832  and mask fabrication  844  can be collectively referred to as mask data preparation. 
     In some embodiments, mask data preparation  832  includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram  822 . In some embodiments, mask data preparation  832  includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem. 
     In some embodiments, mask data preparation  832  includes a mask rule checker (MRC) that checks the IC design layout diagram  822  that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram  822  to compensate for limitations during mask fabrication  844 , which may undo part of the modifications performed by OPC in order to meet mask creation rules. 
     In some embodiments, mask data preparation  832  includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab  850  to fabricate IC device  860 . LPC simulates this processing based on IC design layout diagram  822  to create a simulated manufactured device, such as IC device  860 . The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram  822 . 
     It should be understood that the above description of mask data preparation  832  has been simplified for the purposes of clarity. In some embodiments, data preparation  832  includes additional features such as a logic operation (LOP) to modify the IC design layout diagram  822  according to manufacturing rules. Additionally, the processes applied to IC design layout diagram  822  during data preparation  832  may be executed in a variety of different orders. 
     After mask data preparation  832  and during mask fabrication  844 , a mask  845  or a group of masks  845  are fabricated based on the modified IC design layout diagram  822 . In some embodiments, mask fabrication  844  includes performing one or more lithographic exposures based on IC design layout diagram  822 . In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)  845  based on the modified IC design layout diagram  822 . Mask  845  can be formed in various technologies. In some embodiments, mask  845  is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask  845  includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask  845  is formed using a phase shift technology. In a phase shift mask (PSM) version of mask  845 , various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication  844  is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer  853 , in an etching process to form various etching regions in semiconductor wafer  853 , and/or in other suitable processes. 
     IC fab  850  includes wafer fabrication  852 . IC fab  850  is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab  850  is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business. 
     IC fab  850  uses mask(s)  845  fabricated by mask house  830  to fabricate IC device  860 . Thus, IC fab  850  at least indirectly uses IC design layout diagram  822  to fabricate IC device  860 . In some embodiments, semiconductor wafer  853  is fabricated by IC fab  850  using mask(s)  845  to form IC device  860 . In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram  822 . Semiconductor wafer  853  includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer  853  further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). 
     Details regarding an integrated circuit (IC) manufacturing system (e.g., system  800  of  FIG.  8   ), and an IC manufacturing flow associated therewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 20150278429, published Oct. 1, 2015, U.S. Pre-Grant Publication No. 20140040838, published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entireties of each of which are hereby incorporated by reference. 
     In some embodiments, an integrated circuit (IC) device comprises a plurality of first TAP cells of a first semiconductor type, and a plurality of second TAP cells of a second semiconductor type different from the first semiconductor type. The plurality of first TAP cells is arranged in at least two columns, the at least two columns adjacent each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first TAP cells has a first length in the first direction. The plurality of second TAP cells comprises at least one second TAP cell extending in the first direction between the at least two columns over a second length greater than the first length of each of the plurality of first TAP cells in the first direction. 
     In some embodiments, a method comprises placing, in an integrated circuit (IC) layout diagram, a plurality of first TAP cells of a first semiconductor type in two adjacent columns. The method further comprises placing, in the IC layout diagram, two second TAP cells of a second semiconductor type different from the first semiconductor type. The two adjacent columns are adjacent each other in a first direction, extend in a second direction transverse to the first direction, and are located between the two second TAP cells in the second direction. Each of the plurality of first TAP cells has a first length in the first direction. Each of the two second TAP cells extends continuously in the first direction between the two adjacent columns over a second length greater than the first length of each of the plurality of first TAP cells in the first direction. At least one of the placing the plurality of first TAP cells or the placing the two second TAP cells is executed by a processor. 
     In some embodiments, a system comprises a processor configured to perform TAP cell placement in an integrated circuit (IC) layout diagram by placing a plurality of first TAP cells of a first semiconductor type in rows and columns, and placing a plurality of second TAP cells of a second semiconductor type different from the first semiconductor type. The rows extend in a first direction, and the columns extend in a second direction transverse to the first direction. Each of the plurality of second TAP cells is elongated in the first direction and overlaps, in the second direction, multiple first TAP cells among the plurality of first TAP cells. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.