Patent Publication Number: US-6665853-B2

Title: Netlist consistency checking

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates to a method and computer system for checking a netlist for consistency with input/output connectivity lists. 
     2. Related Art 
     A customer may provide input/output connectivity lists for a Controlled Collapse Chip Connection (C4) chip and for a ball grid array (BGA) circuit card, for use in developing an input netlist file to a design software package. Unfortunately, the input netlist file for the design software package may have formatting constraints that result in errors when the data in the aforementioned input/output connectivity lists are utilized for developing said input file. Said errors constitute a quality assurance concern. Thus there is a need to effectively mitigate said errors. 
     SUMMARY OF THE INVENTION 
     In first embodiments, the present invention provides a method for checking a netlist L, comprising: 
     providing an I/O connectivity list I 1  for a first electrical package P 1 , wherein I 1  includes I/O locations on a surface S 1  of the first electrical package P 1 ; 
     providing an I/O connectivity list I 2  for a second electrical package P 2 , wherein I 2  includes I/O locations on a surface S 2  of the second electrical package P 2 ; 
     providing the netlist L that describes electrical nets between I/O locations on S 1  and I/O locations on S 2 , wherein I denotes I 1  and I 2  collectively, wherein a relationship exists between L and I, wherein the relationship is selected from the group consisting of a mutually consistent relationship and a mutually inconsistent relationship, and wherein a first necessary condition for the relationship to be a mutually consistent relationship is that the I/O locations in L and the I/O locations in I are mutually consistent; and 
     determining whether the relationship is the mutually consistent relationship. 
     In second embodiments, the present invention provides a computer system for checking a netlist L, comprising an algorithm adapted to: 
     access an I/O connectivity list I 1  for a first electrical package P 1 , wherein I 1  includes I/O locations on a surface S 1  of the first electrical package P 1 ; 
     access an I/O connectivity list I 2  for a second electrical package P 2 , wherein I 2  includes I/O locations on a surface S 2  of the second electrical package P 2 ; 
     access the netlist L that describes electrical nets between I/O locations on S 1  and I/O locations on S 2 , wherein I denotes I 1  and I 2  collectively, wherein a relationship exists between L and I, wherein the relationship is selected from the group consisting of a mutually consistent relationship and a mutually inconsistent relationship, and wherein a first necessary condition for the relationship to be a mutually consistent relationship is that the I/O locations in L and the I/O locations in I are mutually consistent; and 
     determine whether the relationship is the mutually consistent relationship. 
     The present invention effectively mitigates errors in an input netlist file to a design software package, wherein said errors relate to a utilization of C4 and BGA input/output connectivity lists. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 depicts a front cross-sectional view of an electronic structure comprising a chip electrically coupled to a chip carrier by Controlled Collapse Chip Connection (C4) solder connections at a C4 surface of the chip, in accordance with embodiments of the present invention. 
     FIG. 2 depicts a planar view of the C4 surface of the chip in FIG. 1, in accordance with embodiments of the present invention. 
     FIG. 3 depicts a planar view of a ball grid array (BGA) surface of the chip carrier in FIG. 1, in accordance with embodiments of the present invention. 
     FIG. 4 depicts a front cross-sectional view of a general electronic structure, as abstracted from FIGS. 1-3, in accordance with embodiments of the present invention. 
     FIG. 5 is a flow chart showing a method of checking a netlist, in accordance with embodiments of the present invention. 
     FIG. 6A depicts an input/output (I/O) connectivity list I 1  of I/O locations and associated energy types on a surface S 1  of first electrical package P 1 , in accordance with embodiments of the present invention. 
     FIG. 6B depicts a list of cartesian coordinate values for each I/O location of the surface S 1  of first electrical package P 1  of FIG. 6A, in accordance with embodiments of the present invention. 
     FIG. 7A depicts an I/O connectivity list I 2  of I/O locations and associated energy types on a surface S 2  of second electrical package P 2 , in accordance with embodiments of the present invention. 
     FIG. 7B depicts a list of cartesian coordinate values for each I/O location of the surface S 2  of second electrical package P 2  of FIG. 7A, in accordance with embodiments of the present invention. 
     FIG. 8 depicts a netlist L of nets between I/O locations on the surface S 1  of FIG.  6 A and I/O locations on the surface S 2  of FIG. 7A, in accordance with embodiments of the present invention. 
     FIG. 9 depicts output resulting from mutual consistency comparisons between the I/O connectivity lists I 1  and I 2  of FIGS. 6A &amp; 7A and the netlist L of FIG. 8, in accordance with embodiments of the present invention. 
     FIG. 10 depicts a revised netlist L 1  of nets between I/O locations on the surface S 1  of FIG.  6 A and I/O locations on the surface S 2  of FIG. 7A where the revised netlist is a modification of the netlist L of FIG. 8, in accordance with embodiments of the present invention. 
     FIG. 11 depicts output resulting from mutual consistency comparisons between the I/O connectivity lists I 1  and I 2  of FIGS. 7A &amp; 7B and the revised netlist L 1  of FIG. 10, in accordance with embodiments of the present invention. 
     FIG. 12 depicts a computer system for checking a netlist, in accordance with embodiments of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 depicts a front cross-sectional view of an electronic structure  10  comprising an integrated circuit chip  12  electrically coupled to a chip carrier  15  by Controlled Collapse Chip Connection (C4) solder connections at a surface  28  of the chip  12 , in accordance with embodiments of the present invention. The C4 solder connections comprise C4 solder balls  21 - 23  at input/output (I/O) locations  13 - 15 , respectively on the surface  28 . The I/O locations  13 - 15  on the surface  28  are electrically coupled to ball grid array (BGA) solder balls  37 - 38  at I/O locations  17 - 19  on a surface  29  of the chip carrier  16 , by use of electrical nets  31 - 33 , respectively. The electrical net  31  comprises the C4 solder ball  21  and a net portion  24  interior to the chip carrier  16 . The electrical net  32  comprises the C4 solder ball  22  and a net portion  25  interior to the chip carrier  16 . The electrical net  33  comprises the C4 solder ball  23  and a net portion  26  interior to the chip carrier  16 . 
     FIG. 2 depicts a planar view of the surface  28  of the chip  12  in FIG. 1, in accordance with embodiments of the present invention. FIG. 2 shows the I/O locations  13 - 15  shown also in FIG. 1, as well as I/O location  43 - 45  and I/O location  53 - 55 . 
     FIG. 3 depicts a planar view of the surface  29  of the chip carrier  16  in FIG. 1, in accordance with embodiments of the present invention. FIG. 3 shows the I/O locations  17 - 19  shown also in FIG. 1, as well as I/O location  47 - 49  and I/O location  57 - 59 . 
     FIG. 4 depicts a front cross-sectional view of a general electronic structure, as abstracted from FIGS. 1-3, in accordance with embodiments of the present invention. The general electrical structure comprises a first electrical package P 1  and a second electrical package P 2 , wherein the first electrical package P 1  is electrically coupled to the second electrical package P 2  by electrical nets N 1 , N 2 , N 3 , . . . The electrical nets N 1 , N 2 , N 3 , . . . respectively provide electrical coupling between the I/O locations α 1 , α 2 , α 3 , . . . on the surface S 1  and the I/O locations β 1 , β 2 , β 3 , . . . on the surface S 2 . 
     Referring to FIGS.  1 - 4 : the first electrical package P 1  is embodied in the chip  12 , the surface S 1  is embodied in the surface  28  of the chip  12 , the I/O locations α 1 , α 2 , α 3 , . . . on the surface S 1  are embodied in I/O locations  13 - 15  and  43 - 45  and  53 - 55 , the second electrical package P 2  is embodied in the chip carrier  16 , the surface S 2  is embodied in the surface  29  of the chip carrier  16 , the I/O locations β 1 , β 2 , β 3 , . . . on the surface S 2  are embodied in I/O locations  17 - 19  and  47 - 49  and  57 - 59 , and the electrical nets N 1 , N 2 , N 3 , . . . are embodied in the electrical nets  31 - 33 . 
     The general electrical structure of FIG. 4 may be arrived at by the following design process. An I/O connectivity list I 1  for the first electrical package P 1  is provided, wherein I 1  includes the I/O locations α 1 , α 2 , α 3 , . . . on the surface S 1  of the first electrical package P 1 . An I/O connectivity list I 2  for the second electrical package P 2  is also provided, wherein I 2  includes I/O locations β 1 , β 2 , β 3 , . . . on the surface S 2  of the second electrical package P 2 . A designer may use the I/O connectivity lists I 1  and I 2  to develop the netlist L that describes the electrical nets N 1 , N 2 , N 3 , . . . between the I/O locations α 1 , α 2 , α 3 , . . . on S 1  and the I/O locations β 1 , β 2 , β 3 , . . . on S 2 . The netlist L may be cast in a form of an input file to a design software package such as, inter alia, the CADENCE® software package of the Allegro Company. The input file may contain, however, errors due to such factors as reformatting errors or design errors made by the designer. Said errors may include mutual inconsistencies between the I/O locations in L and the I/O locations in I, wherein I denotes I 1  and I 2  collectively. Thus a relationship exists between L and I, wherein the relationship is either a mutually consistent relationship or a mutually inconsistent relationship (i.e., not a mutually consistent relationship). A necessary condition for the relationship between L and I to be a mutually consistent relationship is that the I/O locations in L and the I/O locations in I are mutually consistent. By definition herein, the I/O locations in L and the I/O locations in I are mutually consistent if each I/O location in I is accounted for in L (i.e., present in L) and each I/O location in L is accounted for in I (i.e., present in I). 
     FIG. 5 is a flow chart showing a method of checking the netlist L, in accordance with embodiments of the present invention. In step  61 , the I/O connectivity list I 1  is provided, and in step  62 , the I/O connectivity list I 2  is provided. Steps  61  and  62  may be performed in parallel (as shown) or in sequence. The I/O connectivity lists I 1  and I 2  may each be in any data format such as, inter alia, a file, a table, a database, a spreadsheet, etc. In step  63 , the netlist L is provided. The netlist L may be in any data format such as, inter alia, a file, a table, a database, a spreadsheet, etc. In an embodiment, the netlist L may conform to the input form requirements of a design software package such as, inter alia, the CADENCE® software package. A possible scenario is, inter alia, that the netlist designer first creates the netlist (“first netlist”), such as from knowledge of I 1  and I 2 ; then the designer creates a design (e.g., by using the design software package); then the designer again creates the netlist (“second netlist”). The second netlist may differ from the first netlist for any reason such as from errors that occur between generation of the first netlist and the second netlist. The netlist L in step  63  could be, inter alia, the first netlist or the second netlist. As stated supra, a relationship exists between L and I such that the I/O locations in L and the I/O locations in I are either mutually consistent or mutually inconsistent, and accordingly the relationship between L and I is either a mutually consistent relationship or a mutually inconsistent relationship. Step  64  determines whether the relationship between L and I is a mutually consistent relationship. Step  65  generates output relating to whether L and I have been determined in step  64  to be mutually consistent. Step  66  is a decision block which makes a decision based on whether L and I have been determined in step  64  to be mutually consistent. If step  64  has determined that the relationship between L and I is mutually consistent, then step  66  makes the decision to next execute step  67  which ends the method. If step  64  has instead determined that said relationship between L and I is mutually inconsistent (i.e., not mutually consistent), then step  66  makes the decision to next execute step  68 . Step  68  modifies L in an effort to make the relationship between L and I become a mutually consistent relationship. Step  68  may be implmented in software or manually. After step  68  is executed, step  64  is reentered and steps  64 - 66  and  67 / 68  are again executed in a next iteration. Steps  64 - 66  and  67 / 68  may be reexecuted in as many iterations as is needed to ultimately arrive at the mutually consistent relationship between L and I. The method of FIG. 5 may be implemented in an algorithm within a computer system, such as the computer system  90  described infra in conjunction with FIG.  12 . The method of FIG. 5 may be comprise any modification (e.g., a modification in logic) that would be apparent to a person of ordinary skill in the art. 
     In addition to including I/O locations on the surface S 1  of the first electrical structure P 1 , the I/O connectivity list I 1  may also specify an energy type E 1  at each of said I/O locations on S 1 , respectively. For example, an energy type E 1  may exist at each of I/O locations α 1 , α 2 , α 3 , . . . on the surface S 1  in FIG. 4, and the energy type E 1  may differ from one another at the various I/O locations α 1 , α 2 , α 3 , . . . Similarly, in addition to including I/O locations on the surface S 2 , the I/O connectivity list I 2  may specify an energy type E 2  at each of said I/O locations on S 2 . For example, an energy type E 2  may exist at each of I/O locations β 1 , β 2 , β 3 , . . . on the surface S 2  in FIG. 4, and the energy type E 2  may differ from one another at the various I/O locations β 1 , β 2 , β 3 , . . . . 
     In an embodiment, the energy types E 1  at each of said I/O locations on the surface S 1  is a “ground”, a “voltage”, a “null type”, or a “signal type”; and the energy types E 2  at each of said I/O locations on the surface S 2  is a “ground”, a “voltage”, a “null type”, or a “signal type”. A “ground” is a zero voltage level. A “voltage” is a constant voltage level, where the numerical value of the constant voltage level is indicated in the specification of E 1 . Note that a “ground” is logically unnecessary and may either exist for convenience or not exist, since a “ground” is a special case of a “voltage” at a zero voltage level and is therefore within the scope of a “voltage”. A “null type” denotes an absence of a ground, voltage, and signal type. An electrical contact such as a solder ball does not exist at a null spatial point. A “signal type” denotes an electrical signal (voltage or current) having a time-dependent profile such as, inter alia, a succession of pulses, wherein successive pulses are separated by a zero pulse level. The signal type may be one of a generic signal, a class signal, and a specific signal. A generic signal is a signal whose time dependence is open-ended and thus unspecified. A class signal is a signal subject to stated constraints but the signal is not totally constrained. As an example, a class signal may be a periodic signal whose period lies between stated numerical limits of a minimum period and a maximum period. As another example, a class signal may be a phase lock looping type signal. A specific signal is a signal whose time dependence is totally specified. 
     In an embodiment, the signal type of the energy type E 1  is a specific signal, and the signal type of the energy types E 2  is a generic signal, a class signal, or a specific signal. Such an embodiment may be relevant for the electrical structure  10  of FIGS. 1-3 such that the first electrical structure P 1  comprises a chip (e.g., the chip  12 ) and the second electrical structure P 2  comprises a chip carrier (e.g., the chip carrier  16 ). 
     A necessary condition for the relationship between L and I to be mutually consistent may be that the energy types in L and the energy types in I are mutually consistent. By definition herein, the energy types in L and the energy types in I are mutually consistent if each energy type in I is accounted for in L (i.e., present in L at the I/O location specified in I) and each energy type in L is accounted for in I (i.e., present in I at the I/O location specified in L). The preceding necessary condition relating to mutual consistency of energy types in L and I is in addition to the other necessary condition stated supra relating to the mutual consistency of the I/O locations in L and I. 
     FIGS. 6-11 next present an example illustrating the I/O connectivity lists, netlists, and output from mutual consistency comparisons, in accordance with embodiments of the present invention. 
     FIG. 6A depicts an I/O connectivity list I 1  of I/O locations and associated energy types on a surface S 1  of first electrical package P 1 , in accordance with embodiments of the present invention. Each line of FIG. 6A is identified by a sequence number (i.e., “Seq#”), which represents an I/O location and an energy type associated with said I/O location. Each I/O location is identified by a symbolic character string. For example, sequence number  5  represents the I/O location “FA” having an associated energy type VD 1 . The energy types in FIG. 6A comprise a ground (GND), voltage (VDn, n=an integer), a null type (NULL), a generic signal (SIG), a class signal (PLLm, m=1,2,3, . . . ), and a specific signal (SIGk, k=an integer). The integer “n’ in VDn identifies a voltage level. The PLLm signal class stands for a phase lock looping signal class of type m (.e., each value of m identifies a different phase lock looping signal class). 
     FIG. 6B depicts a list of cartesian coordinate values (X 1 , Y 1 ) for each I/O location of the surface S 1  of a first electrical package P 1  of FIG. 6A, in accordance with embodiments of the present invention. The magnitude of (X 1 , Y 1 ) depends on where the origin of coordinates (0,0) is located and on the units (e.g., microns, mm, mils, etc.) used to express linear dimensions. The use of cartesian coordinates is merely illustrative and any other expression of I/O location (e.g., polar coordinates) could alternatively be used. 
     FIG. 7A depicts an I/O connectivity list I 2  of I/O locations and associated energy types on a surface S 2  of a second electrical package P 2 , in accordance with embodiments of the present invention. Each line of FIG. 7A is identified by a sequence number (i.e., “Seq#”), which represents an I/O location and an energy type associated with said I/O location. Each I/O location is identified by a symbolic character string, using the same nomenclature that was described supra in conjunction with FIG.  6 A. Generally, the character strings identifying I/O locations on the surface S 2  may differ from, and are independent of, the character strings identifying I/O locations on the surface S 1 . The I/O locations in FIGS. 6A and 7A are sequenced similarly in that corresponding I/O locations (with respect to nets that connect said corresponding points) are sequenced in the same order in FIGS. 6A and 7A. Generally, however, the I/O locations in FIGS. 6A and 7A may be independently sequenced in any order. 
     FIG. 7B depicts a list of cartesian coordinate values (X 2 , Y 2 ) for each I/O location of the surface S 2  of first electrical package P 2  of FIG. 7A, in accordance with embodiments of the present invention. The magnitude of (X 2 , Y 2 ) depends on where the origin of coordinates (0,0) is located and on the units (e.g., microns, mm, mils, etc.) used to express linear dimensions. The use of cartesian coordinates is merely illustrative and any other expression of I/O location (e.g., polar coordinates) could alternatively be used. Although FIGS. 6B and 7B express coordinate values in the same system of units, the coordinate values in may be expressed in different units. Additionally, the origin of coordinates differ for FIGS. 6B and 7B by the displacement vector (100, 200). 
     FIG. 8 depicts a netlist L of nets between I/O locations on the surface S 1  of FIG.  6 A and I/O locations on the surface S 2  of FIG. 7A, in accordance with embodiments of the present invention. Each line of FIG. 8 is identified by a sequence number (i.e., “Seq#”), which represents a net that electrically couples I/O locations on the surface S 1  and with I/O locations on the surface S 2 . The I/O locations in FIG. 8 are intended to be the same as the I/O locations in FIGS. 6A and 7A, except that the I/O locations in FIG. 8 may differ in format from the I/O locations in FIGS. 6A and 7A. For example, the I/O locations for S 1  in FIG. 8 are prefixed by “U1.” relative to the I/O locations for S 1  in FIG.  6 A. As another example, the I/O locations for S 2  in FIG. 8 are prefixed by “J1.” relative to the I/O locations for S 2  in FIG.  7 A. As an example of how to interpret the nets of FIG. 8, sequence number  9  identifies a net having the specific signal SIG 21  between the I/O location DM on the surface S 1  and the I/O location D 13  on the surface S 2 . 
     In accordance with steps  64  and  65  of the method of FIG. 5, described supra, FIG. 9 depicts output (step  65 ) resulting from mutual consistency comparisons (step  64 ) between the I/O connectivity lists I 1  and I 2  of FIGS. 6A &amp; 7A and the netlist L of FIG.  8 . The mutual consistency comparisons of step  64  take into account formatting difference between the I/O connectivity lists I 1  and I 2  of FIGS. 6A &amp; 7A and the netlist L of FIG.  8 . For example, the mutual consistency comparisons of step  64  comprise stripping away the aforementioned “U1.” and “J1.” prefixes in FIG.  8 . As another example, the mutual consistency comparisons of step  64  may comprise parsing portions of FIGS. 6A &amp; 7A and/or FIG.  8 . 
     In accordance with embodiments of the present invention, FIG. 9 identifies mutual inconsistencies in terms of I/O connectivity list parameters of FIGS. 6A and 7A which are unmatched in the netlist of FIG. 8, and also in terms of the netlist parameters of FIG. 8 which are unmatched in the I/O connectivity lists of FIGS. 6A and 7A. The mismatches denoted in FIG. 9 result from errors in the nets of sequence numbers  3 ,  6 ,  17 , and  18  in FIG.  8 . In the net of sequence number  3 , the I/O location of surface S 1  should be U 1 .DW and not U 1 .DV. In the net of sequence number  6 , the energy type should be VD 2  and not VD 3 . In the net of sequence number  17 , the energy type should be GND and not VD 4 . In the net of sequence number  18 , the energy type should be SIG 27  and not SIG 28 , the I/O location of surface S 1  should be U 1 .BH and not U 1 .BB, and the I/O location of surface S 2  should be J 1 .B 08  and not J 1 .B 02 . While FIG. 9 identifies mutual inconsistencies, the output step  65  may also include an identification of mutual consistencies in terms of I/O connectivity list parameters of FIGS. 6A and 7A which are matched in the netlist of FIG. 8, and also in terms of the netlist parameters of FIG. 8 which are matched in the I/O connectivity lists of FIGS. 6A and 7A. 
     FIG. 10 depicts a revised netlist L 1  of nets between I/O locations on the surface S 1  of FIG.  6 A and I/O locations on the surface S 2  of FIG. 7A wherein the revised netlist is a modification of the netlist L of FIG. 8, in accordance with embodiments of the present invention. FIG. 10 results from an attempt to correct the errors in the netlist of FIG. 8, wherein said errors were identified in FIG.  9 . Such an attempt to correct said errors is in accordance with step  68  of the method of FIG. 5, described supra. 
     FIG. 11 depicts output (step  65 ) resulting from mutual consistency comparisons (step  64 ) between the I/O connectivity lists I 1  and I 2  of FIGS. 6A &amp; 7A and the netlist L 1  of FIG.  10 . FIG. 11 reveals that the netlist L 1  of FIG.  10  and the I/O connectivity list I of FIGS. 6A and 7A (i.e., I denotes the I/O connectivity lists I 1  and I 2  of FIGS. 6A and 7A respectively) are mutually consistent. 
     FIG. 12 illustrates a computer system  90  for checking a netlist L, in accordance with embodiments of the present invention. The computer system  90  comprises a processor  91 , an input device  92  coupled to the processor  91 , an output device  93  coupled to the processor  91 , and memory devices  94  and  95  each coupled to the processor  91 . The input device  92  may be, inter alia, a keyboard, a mouse, any other pointing device, etc. The output device  93  may be, inter alia, a printer, a plotter, a computer screen, a magnetic tape, a removable hard disk, a floppy disk, etc. The memory devices  94  and  95  may be, inter alia, a hard disk, a dynamic random access memory (DRAM), a read-only memory (ROM), etc. The memory device  95  includes a computer code  97 . The computer code  97  includes an algorithm for checking the netlist L, wherein said algorithm is in accordance with the method described supra in conjunction with FIG.  5 . The processor  91  executes the computer code  97 . The memory device  94  includes input data  96 . The input data  96  includes input required by the computer code  97 . The output device  93  displays output from the computer code  97 . In particular, the output device  93  includes the output medium and displays, inter alia, the output of FIGS. 9 and 11. 
     While FIG. 12 shows the computer system  90  as a particular configuration of hardware and software, any configuration of hardware and software, as would be known to a person of ordinary skill in the art, may be utilized for the purposes stated supra in conjunction with the particular computer system  90  of FIG.  12 . For example, the memory devices  94  and  95  may be portions of a single memory device rather than separate memory devices. 
     While embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.