Patent Publication Number: US-2013235623-A1

Title: Two-switch flyback power converters

Description:
REFERENCE TO RELATED APPLICATION 
     This application is based on Provisional Application Ser. No. 61/609,572, filed 12 Mar. 2012, currently pending. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention relates to a power converter, and more particularly, the present invention relates to a two-switch Flyback power converter. 
     2. Description of Related Art 
       FIG. 1  shows a traditional Flyback topology of power converters. A transformer T 1  includes a primary-winding N P  and a secondary-winding N S . A first terminal of the primary-winding N P  is coupled to receive a DC input voltage V IN . The secondary-winding N S  generates an output voltage V O  via a rectifier D O  and a capacitor C O . A drain terminal of a power switch M is coupled to a second terminal of the primary-winding N P . A sense resistor R S  is coupled between a source terminal of the power switch M and a ground. A switching current I P  flows through the primary-winding N P  and the power switch M when the power switch M is turned on. The sense resistor R S  is used to generate a current-sense signal V C  in response to the switching current I P . In order to regulate the output voltage V O , a control circuit  20  generates a drive signal V G  to control the power switch M for switching the transformer T 1  in response to the current-sense signal V C  and a feedback signal V FB . 
     A bulk capacitor C huge  providing the DC input voltage V IN  is located between a power source V AC  and a bridge rectifier  10 . The bulk capacitor C huge  connected from an output terminal of the bridge rectifier  10  to the ground is for stabilizing the DC input voltage V IN  at the output terminal of the bridge rectifier  10  connected to the Flyback topology. 
     In recent years, the size and cost problem of the bulk capacitor in switching power converters has drawn much attention. In addition, the quality of the bulk capacitor influences the usage life of the power converters. Therefore, it has become a major concern to lower or eliminate the capacitance of the bulk capacitor. 
     BRIEF SUMMARY OF THE INVENTION 
     The object of the present invention is to provide a two-switch Flyback power converter. The two-switch Flyback power converters with less capacitance of the bulk capacitor or bulk capacitor-less can reduce the voltage ripples at the output voltage for cost saving. 
     A two-switch Flyback power converter according to the present invention comprises a transformer, a first switch, a second switch, and a control circuit. The transformer includes a primary-winding and a secondary-winding. The primary-winding is coupled to a power source of the two-switch Flyback power converter and has a first winding and a second winding. The first switch is coupled to switch the first winding. The second switch is coupled to switch the first winding and the second winding. The control circuit generates a first-drive signal and a second-drive signal to control the first switch and the second switch for switching the transformer and regulating an output of the two-switch Flyback power converter. The first switch and the second switch can deliver more power in a valley of the rectified power source by switching different winding to improve ripples of an output voltage of the two-switch Flyback power converter. 
    
    
     
       BRIEF DESCRIPTION OF ACCOMPANIED DRAWINGS 
       The accompanying drawings are included to provide further understanding of the invention, and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
         FIG. 1  shows a traditional topology of power converters. 
         FIG. 2  shows a circuit diagram of an embodiment of two-switch Flyback power converters according to the present invention. 
         FIG. 3  shows a circuit diagram of an embodiment of a control circuit according to the present invention. 
         FIG. 4  shows the waveforms of the power source, the high-voltage signal, the first-drive signal and the second-drive signal according to the present invention. 
         FIG. 5  shows a circuit diagram of another embodiment of the two-switch Flyback power converters according to the present invention. 
         FIG. 6  shows the waveforms of the power source, the high-voltage signal, the first-drive signal and the second-drive signal according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       FIG. 2  is a circuit diagram of an embodiment of two-switch Flyback power converters according to the present invention. A rectifier can be a full-wave rectifier having a first diode D 1  and a second diode D 2  according to one embodiment of the present invention, anodes of the first diode D 1  and the second diode D 2  are connected to the power source V AC . respectively. Cathodes of the first diode D 1  and the second diode D 2  are together connected to a high-voltage terminal HV of a control circuit  30  through a first-series resistor R 1  and a second-series resistor R 2 . A high-voltage signal V HV  is generated at the high-voltage terminal HV through the full-wave rectification of the first diode D 1  and the second diode D 2 . Thus, the rectifier is coupled to the power source V AC  for rectifying the power source V AC  to generate the high-voltage signal V HV . The bridge rectifier  10  including a plurality of diodes rectifies the power source V AC  to generate the input voltage V IN . A bulk capacitor C tiny  with less capacitance coupled from the output terminal of the bridge rectifier  10  to the ground is for stabilizing the input voltage V IN  at the output terminal of the bridge rectifier  10 . 
     The two-switch Flyback power converter comprises a transformer T 2  including a primary-winding and a secondary-winding Ns. The secondary-winding Ns generates the output voltage V O  via the rectifier D O  and the capacitor C O . The rectifier D O  is coupled between a terminal of the secondary-winding Ns and an output terminal of the two-switch Flyback power converter. The capacitor C O  is coupled to the output terminal of the two-switch Flyback power converter. 
     The primary-winding includes a first winding N P1  and a second winding N P2 . The first winding N P1  is coupled to the second winding N P2  in series. A first terminal of the first winding N P1  is coupled to the input voltage V IN . Therefore, the primary-winding is coupled to the power source V AC  through the bridge rectifier  10 . A drain terminal of a first switch M 1  is coupled to a second terminal of the first winding N P1  and a first terminal of the second winding N P2 . A first-switching current I P1  flowing through the first winding N P1  is generated at the drain terminal of the first switch M 1 . An output terminal VG 1  of the control circuit  30  generates a first-drive signal V G1  supplied to a gate terminal of the first switch M 1 . The first-drive signal V G1  controls the first switch M 1  to switch the first winding N P1  of the transformer T 2  for regulating the output voltage V O  of the two-switch Flyback power converter. 
     A sense circuit includes a first-sense resistor R S1  and a second-sense resistor R S2 . The first-sense resistor R S1  is coupled between a source terminal of the first switch M 1  and the ground. A drain terminal of a second switch M 2  is coupled to a second terminal of the second winding N P2 . A second-switching current I P2  flowing through the second winding N P2  is generated at the drain terminal of the second switch M 2 . An output terminal VG 2  of the control circuit  30  generates a second-drive signal V G2  supplied to a gate terminal of the second switch M 2 . The second-drive signal V G2  controls the second switch M 2  to switch the first winding N P1  and the second winding N P2  of the transformer T 2  for regulating the output voltage V O  of the two-switch Flyback power converter. The first switch M 1  and the second switch M 2  are power switches according to one embodiment of the present invention. The second-sense resistor R S2  is coupled between a source terminal of the second switch M 2  and the first-sense resistor R S1 . A current-sense signal V CS  is generated at the second-sense resistor R S , and the source terminal of the second switch M 2  coupled to a current-sense terminal CS of the control circuit  30  in response to the second-switching current I P2 . 
     The control circuit  30  generates the first-drive signal V G1  and the second-drive signal V G2  to regulate the output of the two-switch Flyback power converter in response to the high-voltage signal V HV , the current-sense signal V CS , and a feedback signal V FB . The feedback signal V FB  is obtained at a feedback terminal FB of the control circuit  30  by detecting the output voltage V O . The feedback signal V FB  is correlated to the output voltage V O . 
       FIG. 3  shows a circuit diagram of an embodiment of the control circuit according to the present invention. The control circuit  30  comprises a detection circuit  310 , a PWM circuit  360 , and a switch circuit  370 . The detection circuit  310  includes a high-voltage switch J 1 , a first transistor S a second transistor S 2 , a third transistor S 3  and a hysteresis comparator  312 . The detection circuit  310  is coupled to the series resistors R 1  and R 2  for detecting the high-voltage signal V HV  to generate a sample signal V SP . Therefore, the detection circuit  310  detects the power source V AC  (as shown in  FIG. 2 ) for generating the sample signal V SP  through detecting the high-voltage signal V HV . The high-voltage switch J 1  formed by a Junction Field Effect Transistor (JFET) has a drain terminal coupled to the series resistors R 1  and R 2  for receiving the high-voltage signal V HV . The drain terminal of the high-voltage switch J 1  is further coupled to the power source V AC  through the series resistors R 1  and R 2 , the diodes D 1  and D 2 . 
     The first transistor S 1  has a drain terminal coupled to a source terminal of the high-voltage switch a gate terminal coupled to a gate terminal of the high-voltage switch J 1 . The sample signal V SP  is generated at the source terminal of the high-voltage switch J 1  and the drain terminal of the first transistor S 1 . The sample signal V SP  is correlated to the high-voltage signal V HV . A trigger signal V GJ1  is generated at the gate terminals of the high-voltage switch J 1  and the first transistor S 1 . The second transistor S 2  has a drain terminal coupled to the gate terminals of the high-voltage switch J 1  and the first transistor S 1 , a source terminal coupled to the source terminal of the high-voltage switch J 1  and the drain terminal of the first transistor S 1  for receiving the sample signal V SP . The third transistor S 3  has a drain terminal coupled to the drain terminal of the second transistor S 2  and the gate terminals of the high-voltage switch J 1  and the first transistor S 1  for receiving the trigger signal V GJ1 , a source terminal that is coupled to the ground, a gate terminal coupled to a gate terminal of the second transistor S 2 . 
     A positive input terminal of the hysteresis comparator  312  is coupled to a source terminal of the first transistor S 1  for receiving a supply voltage V DD . The hysteresis comparator  312  has a negative input terminal to receive a threshold signal V TH . An output terminal of the hysteresis comparator  312  generates a switching signal V SW  that is coupled to the gate terminals of the second transistor S 2  and the third transistor S 3 . By comparing the supply voltage V DD  with the threshold signal V TH , the switching signal V SW  is generated and controls an on/off status of the second transistor S 2  and the third transistor S 3 . The hysteresis comparator  312  is only one embodiment of the present invention, and the prevent invention isn&#39;t limited to the hysteresis comparator  312 . 
     In this manner, the switching signal V SW  is at a high-level once the supply voltage V DD  is larger than an upper-limit of the threshold signal V TH . On the contrary, the switching signal V SW  is at a low-level once the supply voltage V DD  is smaller than a lower-limit of the threshold signal V TH . The lower-limit of the threshold signal V TH  is also called an under voltage lockout (UVLO). Because of the hysteresis characteristic of the hysteresis comparator  312 , the difference between the upper-limit and the lower-limit always keeps a fixed voltage range. 
     When the power source V AC  is switched on, the drain terminal of the high-voltage switch J 1  receiving the high-voltage signal V HV  is turned on immediately. The switching signal V SW  is at the low-level since the supply voltage V DD  hasn&#39;t been created yet. At this time, the third transistor S 3  is turned off and the second transistor S 2  is turned on. The sample signal V SP  is about a threshold voltage of the second transistor S 2  and generated at the source terminal of the high-voltage switch J 1  and the drain terminal of the first transistor S 1 . Because the second transistor S 2  is turned on, the trigger signal V GJ1  is the same as the sample signal V SP  and generated at the gate terminals of the high-voltage switch J 1  and the first transistor S 1 . 
     In the meantime, the first transistor S 1  is turned on and the supply voltage V DD  is charged by the high-voltage signal V HV . The first transistor S 1  serves as a charge transistor for charging the supply voltage V DD . When the supply voltage V DD  reaches to the upper-limit of the threshold signal V TH , the switching signal V SW  is at the high-level. At this time, the third transistor S 3  is turned on and the second transistor S 2  is turned off. Because the trigger signal V GJ1  is pulled down to the ground, the first transistor S 1  is turned off and the gate terminal of the high-voltage switch J 1  is at a low-level. During a short period, the source-to-gate voltage of the high-voltage switch J 1  will be higher than a threshold and the high-voltage switch J 1  is turned off. 
     The switch circuit  370  includes a fourth transistor S 4 , a pull-down resistor R 3 , a voltage comparator  320 , a flip-flop  330 , a first AND gate  340  and a second AND gate  350 . The fourth transistor S 4  has a drain terminal coupled to the detection circuit  310  for receiving the sample signal V SP , and a source terminal coupled to one terminal of the pull-down resistor R 3  for generating an input signal V INAC . The other terminal of the pull-down resistor R 3  is coupled to the ground. A gate terminal of the fourth transistor S 4  is coupled to receive a clock signal V CLK . The fourth transistor S 4  is turned on once the clock signal V C1  is at a high-level. Because of the voltage drop in the pull-down resistor R 3 , the source-to-gate voltage of the high-voltage switch J 1  will be lower than the threshold and the high-voltage switch J 1  is turned on. On the other hand, the high-voltage switch J 1  is turned off once the clock signal V CLK  is at a low-level. 
     The voltage comparator  320  has a positive input terminal receiving a reference signal V REF , and a negative input terminal coupled to the source terminal of the fourth transistor S 4  for receiving the input signal V INAC . The input signal V INAC  is proportional to the high-voltage signal V HV  and correlated to the sample signal V SP  once the high-voltage switch J 1  and the fourth transistor S 4  are turned on. A clock input terminal CK of the flip-flop  330  coupled to the gate terminal of the fourth transistor S 4  receives the clock signal V CLK . An input terminal D of the flip-flop  330  coupled to an output terminal of the voltage comparator  320  receives a first signal V 1 . The first signal V 1  is generated by comparing the input signal V INAC  with the reference signal V REF . As mentioned above, the voltage comparator  320  is utilized for generating the first signal V 1  in response to the sample signal V SP  and the reference signal V REF . 
     The PWM circuit  360  includes an oscillator (OSC)  362 , a PWM comparator  363 , an inverter  364 , a flip-flop  365  and an AND gate  366 . The oscillator  362  generates a pulse signal PLS. A positive input terminal of the PWM comparator  363  receives the feedback signal V FB . The current-sense signal V CS  is supplied to a negative input terminal of the PWM comparator  363 . The feedback signal V FB  is correlated to the output voltage V O  (as shown in  FIG. 2 ), and the current-sense signal V CS  is correlated to the second-switching current I P2  (as shown in  FIG. 2 ). The flip-flop  365  has an input terminal D receiving a supply voltage V CC , a clock-input terminal CK receiving the pulse signal PLS, a reset-input terminal R receiving a reset signal V RESET . The reset signal V RESET  is generated when the current-sense signal V CS  is larger than the feedback signal V FB . A first input terminal of the AND gate  366  coupled to the oscillator  362  receives the pulse signal PLS through the inverter  364 . A second input terminal of the AND gate  366  is coupled to an output terminal Q of the flip-flop  365 . A PWM signal V PWM  is generated at an output terminal of the AND gate  366 . 
     A first input terminal of the first AND gate  340  is coupled to an output terminal Q of the flip-flop  330 . The PWM signal V PWM  is supplied to a second input terminal of the first AND gate  340  and a first input terminal of the second AND gate  350 . A second input terminal of the second AND gate  350  is coupled to an output terminal QN of the flip-flop  330 . The first-drive signal V G1  and the second-drive signal V G2  are generated at the output terminals of the first AND gate  340  and the second AND gate  350 , respectively. 
       FIG. 4  shows the waveforms of the power source V AC , the high-voltage signal V HV , the first-drive signal V G1  and the second-drive signal V G2  according to the present invention. The period of the power source V AC  is about 20 ms if the input supply frequency of the power source V AC  is 50 Hz. The high-voltage signal V HV  is generated through the full-wave rectification of the first diode D 1  and the second diode D 2  (as shown in  FIG. 2 ). As shown in  FIG. 3  the clock signal V CLK  is used to control the fourth transistor S 4  for sampling the high-voltage signal V HV . 
     When the high-voltage signal V HV  is higher than the reference signal V REF , the first-drive signal V G1  will be disabled and the second-drive signal V G2  will be enabled. Therefore, the first switch M 1  will be turned off and the second switch M 2  will start high-frequency switching. Once the high-voltage signal V HV  is lower than the reference signal V REF , the second-drive signal V G2  will be disabled and the first-drive signal V G1  will be enabled. Therefore, the second switch M 2  is turned off and the first switch M 1  will start high-frequency switching. According to above, the first switch M 1  will start switching and the second switch M 2  will be turned off when the power source V AC  is lower than a threshold such as the reference signal V REF . The second switch M 2  will start switching and the first switch M 1  will be turned off when the power source V AC  is higher than the threshold. In other words, the control circuit  30  is utilized to detect whether the power source V AC  drops off to the valley of the power source V AC  that is rectified, such as the valley of the high-voltage signal V HV  or the input voltage V IN . The control circuit  30  drives the first switch M 1  in a first operating mode when the power source V AC  is lower than the threshold, and the control circuit  30  drives the second switch M 2  in a second operating mode when the power source V AC  is higher than the threshold. 
     Referring to  FIG. 2 , when the first switch M 1  is switching, the turn ratio of the primary-winding to the secondary-winding Ns (the winding turns of the first winding N P1  to the winding turns of the secondary-winding Ns) is a low level, the first-switching current I P1  is a high level, and a lower resistance of the sense circuit (the first-sense resistor R S1 ) is determined. When the second switch M 2  is switching, the turn ratio of the primary-winding to the secondary-winding Ns (the winding turns of the first winding N P1  and the second winding N P2  to the winding turns of the secondary-winding Ns) is a high level, the second-switching current I P2  is a low level, and a higher resistance of the sense circuit (the first-sense resistor R S1  and the second-sense resistor R S2 ) is determined. Therefore, the switches M 1  and M 2  can deliver more power in the valley of the rectified power source, such as the valley of the high-voltage signal V HV  or the input voltage V IN , by switching different winding or adjusting a turn ratio of the primary-winding to improve the ripples of the output voltage V O . 
     If the power converters using Flyback topology don&#39;t have the bulk capacitor, the large ripples will be generated at the output voltage V O  when the power source V AC  drops to the valley of the rectified power source. During the valley of the rectified power source, the power source V AC  stays a lower voltage and lasts a short period. According to the present invention, the two-switch Flyback power converters with less capacitance of the bulk capacitor C tiny  (as shown in  FIG. 2 ) or bulk capacitor-less (as shown in  FIG. 5 ) can reduce the voltage ripples at the output voltage V O  by adding another switch M 2  such as MOSFET. Since the cost of MOSFET is much cheaper than the bulk capacitor, the two-switch Flyback power converters can save total BOM cost. 
       FIG. 6  shows the waveforms of the power source V AC , the high-voltage signal V HV , the first-drive signal V G1  and the second-drive signal V G2  according to the two-switch Flyback power converter without bulk capacitor shown the  FIG. 5 . When the high-voltage signal V HV  is higher than the reference signal V REF , the first-drive signal V G1  will be disabled and the second-drive signal V G2  will be enabled. Therefore, the first switch M 1  (as shown in  FIG. 5 ) will be turned off and the second switch M 2  (as shown in  FIG. 5 ) will start high-frequency switching. Once the high-voltage signal V HV  is lower than the reference signal V REF , the second-drive signal V G2  will be disabled and the first-drive signal V G1  will be enabled. Therefore, the second switch M 2  is turned off and the first switch M 1  will start high-frequency switching. The two-switch Flyback power converter can reduce the voltage ripples at the output voltage V O  by switching different winding or adjusting a turn ratio of the primary-winding even if the two-switch Flyback power converter has a smaller bulk capacitor or lacks the bulk capacitor C tiny . 
     Although the present invention and the advantages thereof have been described in detail, it should be understood that various changes, substitutions, and alternations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims. That is, the discussion included in this invention is intended to serve as a basic description. It should be understood that the specific discussion may not explicitly describe all embodiments possible; many alternatives are implicit. The generic nature of the invention may not fully explained and may not explicitly show that how each feature or element can actually be representative of a broader function or of a great variety of alternative or equivalent elements. Again, these are implicitly included in this disclosure. Neither the description nor the terminology is intended to limit the scope of the claims.