Patent Publication Number: US-9843258-B2

Title: Buck power stage with multiple MOSFET types

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. provisional application No. 62/119,630 filed Feb. 23, 2015, titled “HIGH VOLTAGE CMOS CASCODE BUCK POWER STAGE WITH MULTIPLE MOSFET TYPES,” which is incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present application generally relates to semiconductor buck power converters, and more particularly to buck power converters having an output stage having more than two switches. 
     BACKGROUND OF THE INVENTION 
     Typical buck regulator power converters, such as that illustrated in  FIG. 1 , utilize two switches  10  and  20  (e.g. MOSFETs) to connect the converter&#39;s switch node (Vx) to either Vin or to ground. The switch node can present a pulse-width modulated square wave with its high-level at the voltage of Vin and it&#39;s low-level at the ground voltage of the input of a second order output filter  30 . The output filter time-averages the switch node square wave to present a filtered output voltage that is proportional to the amount of time per cycle the switch node is connected to Vin. 
     Each switch in this typical configuration must be able to block the full input voltage (the difference between the voltage at Vin and ground) while off and while turning on. Therefore, each switch must have a minimum breakdown voltage equal to the input voltage plus a margin. In practice, it is typical to have the minimum breakdown voltage equal to two times the input voltage in discrete circuits where parasitic reactance in the interconnect causes destructive voltage spiking. This may be less severe in fully integrated regulators. 
     MOSFET switch performance characteristics are dramatically impacted by their breakdown voltage. Two critical performance metrics in a MOSFET are its RDSon and gate charge (Qg). In general, MOSFET RDSon per unit area is proportional to the square of its breakdown voltage. In addition, Qg is proportional to the area of gate and the thickness of the oxide underneath the gate. Higher voltage MOSFETs typically feature a thicker gate oxide which increases the Qg. This is compounded by the aforementioned fact that the gate area of a higher voltage MOSFET must be exponentially larger to achieve the same RDSon as a lower voltage version, thus exponentially increasing Qg as well. 
     Since losses in a MOSFET are proportional to both RD Son and Qg, reducing the blocking requirements on the MOSFETs in a voltage regulator is highly advantageous. 
     BRIEF SUMMARY OF THE INVENTION 
     One inventive aspect is a buck voltage converter. The buck voltage generator includes a controller configured to generate one or more pulse width modulation (PWM) signals, and a plurality of serially connected switches configured to receive the PWM signals and to generate an output voltage signal at an output terminal based on the received PWM signals. The output voltage signal has an average voltage corresponding with a duty cycle of the PWM signals, a first switch of the plurality of serially connected switches has a first breakdown voltage and a second switch of the plurality of serially connected switches has a second breakdown voltage, and the first breakdown voltage is less than the second breakdown voltage. 
     Another inventive aspect is a buck voltage converter. The buck voltage generator includes a plurality of serially connected switches configured to generate an output voltage signal at an output terminal, where the output voltage signal has an average voltage corresponding with a duty cycle of one or more PWM signals. A first switch of the plurality of serially connected switches has a first breakdown voltage and a second switch of the plurality of serially connected switches has a second breakdown voltage, and the first breakdown voltage is less than the second breakdown voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic illustration of a conventional buck power converter. 
         FIG. 2  is a schematic illustration of a buck power converter according to an embodiment. 
         FIG. 3  is a schematic illustration of the buck converter of  FIG. 2  generating a high output voltage. 
         FIG. 4  is a waveform diagram illustrating a buck converter output transition from low to high. 
         FIG. 5  is a schematic illustration of the buck converter of  FIG. 2  generating a low output voltage. 
         FIG. 6  is a waveform diagram illustrating a buck converter output transition from high to low. 
         FIG. 7  is a schematic illustration of a portion of a buck converter connected to bias voltage generators. 
         FIG. 8  is a schematic illustration of a bias voltage generator which may be used as a bias generator of the buck converter of  FIG. 7 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Particular embodiments of the invention are illustrated herein in conjunction with the drawings. 
     Various details are set forth herein as they relate to certain embodiments. However, the invention can also be implemented in ways which are different from those described herein. Modifications can be made to the discussed embodiments by those skilled in the art without departing from the invention. Therefore, the invention is not limited to particular embodiments disclosed herein. 
       FIG. 2  is a schematic illustration of a buck power converter according to an embodiment. 
     In order to avoid the aforementioned performance limitation of using power MOSFETs with breakdown voltages that exceed Vin, cascode output stages (“FET stacking”) may be used. For example, as shown in  FIG. 2 , a series connection of MOSFETs can be used so that the resulting breakdown voltage of the series connected switches is equal to the sum of the breakdown voltages of the individual switches. Thus, one can utilize relatively low-voltage switches in a high-voltage application. 
       FIG. 2  illustrates buck converter  100 , which includes pulse width modulation (PWM) controller  110 , switch stack  120 , output filter  130 , and voltage feedback generator  140 . Buck converter  100  is configured to generate a substantially DC voltage at output terminal Vout based on a received reference voltage at input terminal Cin and a received feedback voltage representing the output voltage Vout of the regulator. 
     In some embodiments, the PWM controller  110  and the switch stack  120  are integrated on a single integrated circuit semiconductor substrate, for example, comprising a semiconductor, such as single-crystalline silicon. In some embodiments, the PWM controller  110 , the switch stack  120 , and the filter  130  are integrated on a single integrated circuit semiconductor substrate, for example, comprising a semiconductor, such as single-crystalline silicon. In some embodiments, the PWM controller  110 , the switch stack  120 , the filter  130 , and the voltage feedback generator  140  are integrated on a single integrated circuit semiconductor substrate, for example, comprising a semiconductor, such as single-crystalline silicon. 
     In some embodiments, the PWM controller  110  and the switch stack  120  are integrated on a single package substrate, for example, on a package substrate within an integrated circuit package having a semiconductor die attached thereto. In some embodiments, the PWM controller  110 , the switch stack  120 , and the filter  130  are integrated on a single package substrate, for example, on a package substrate within an integrated circuit package having a semiconductor die attached thereto. In some embodiments, the PWM controller  110 , the switch stack  120 , the filter  130 , and the voltage feedback generator  140  are integrated on a single package substrate, for example, on a package substrate within an integrated circuit package having a semiconductor die attached thereto. 
     PWM controller  110  is configured to receive a control signal at Cin and generate PWM signals for switch stack  120  at nodes  111  and  116 . In some embodiments, the PWM signals switch at a frequency greater than or equal to 1 MHz. In some embodiments, PWM controller  110  is replaced by another controller, such as a constant on-time controller, a hysteretic controller, or a resonant controller. Other controllers may be alternatively used. 
     Switch stack  120  is configured to receive the PWM signals at nodes  111  and  116 , and to alternately and repeatedly drive output filter  130  with an output voltage signal at node Vx substantially equal to the voltage at input terminal Vin and ground. For example, during a first time period, switch stack  120  drives output filter  130  with an output signal voltage substantially equal to the voltage at Vin, and during a next, second time period, switch stack  120  drives output filter  130  with a output signal voltage substantially equal to the ground voltage. Switch stack  120  repeatedly alternates between driving the output filter  130  with the output signal voltage substantially equal to the voltage at input terminal Vin and substantially equal to ground, such that the proportion of time during which switch stack  120  drives the output filter with the output signal voltage substantially equal to the voltage at input terminal Vin is substantially equal to the ratio of the desired output voltage to the voltage at input terminal Vin. Accordingly, the output voltage signal may have an average voltage corresponding with a duty cycle or an inverse of the duty cycle of the PWM signals at nodes  111  and  116 . 
     Output filter  130  receives the PWM voltage from switch stack  120 , and generates a substantially DC voltage at output terminal Vout. In this embodiment, the output filter  130  comprises an inductor  132  and a capacitor  134 . In alternative embodiments, alternative filter architectures are used. 
     In this embodiment, a voltage divided version of the DC voltage at output terminal Vout is fed back to PWM controller  110 . In some embodiments, PWM controller  110  is configured to adjust the PWM signals at nodes  111  and  116  so as to generate a desired DC voltage at output terminal Vout. In some embodiments, the desired reverence DC voltage may be received at input Cin. In some embodiments, a digital signal representing the desired DC voltage may be received at input Cin. In some embodiments, input Cin is configured to additionally or alternatively receive other control information, such as frequency information. In some embodiments, alternate feedback schemes are used. For example, in some embodiments, the DC voltage at output terminal Vout is fed back to PWM controller  110 , and no resistor divider network is used. 
     Switch stack  120  includes multiple types of MOSFETs. Switch stack  120  includes fast and power efficient switches having structures consistent with MOSFETs located in internal portions of an integrated circuit, and are referred to as core transistors. In addition, switch stack  120  includes high voltage tolerance switches having structures consistent with MOSFETs located in peripheral portions of the integrated circuit, and are called I/O transistors. 
     Core transistors typically have thinner gate oxide than the I/O transistors. For example, in some manufacturing processes, the gate oxide thickness of a core transistor may be about 1.2 nm, and the gate oxide thickness of the I/O transistors may be about 4.1 nm. Core transistors and I/O transistors may have other gate oxide thicknesses as well. In some embodiments, the gate oxide thickness of I/O transistors may be about 1.5, about 2, about 2.5, about 3, about 3.5, about 4, or more times the gate oxide thickness of core transistors. 
     In addition, core transistors typically have shorter minimum gate lengths and correspondingly low RD Son as compared with the I/O transistors. For example, in some manufacturing processes, the minimum gate length for core transistors may be about 28 nm, and the minimum gate length for I/O transistors may be about 150 nm. 
     Furthermore, core transistors typically have lower gate to source, gate to drain, and drain to source breakdown voltages than I/O transistors. 
     Other differences between core transistors and I/O transistors may exist, as understood by one of skill in the art. 
     In the embodiment of  FIG. 2 , switch stack  120  includes P-type MOSFETs  121 ,  122 , and  123 , and includes N-type MOSFETs  126 ,  127 , and  128 . 
     In some embodiments, MOSFETs  121 ,  122 ,  126 , and  127  are core transistors, and MOSFETs  123  and  128  are I/O transistors. However, all combinations of core and I/O transistors are contemplated. For example, in some embodiments, MOSFETs  122 ,  123 ,  127 , and  128  are I/O transistors, and MOSFETs  121  and  126  are core transistors. In alternative embodiments, MOSFETs  121 ,  122 ,  123 ,  126 ,  127 , and  128 , are all either core transistors or I/O transistors. 
     In alternative embodiments, the MOSFETs  121 ,  122 , and  123  and  126 ,  127 , and  128  are serially connected in a different order. For example, MOSFET  121  may be connected to MOSFET  126  with no other transistors intervening, where the gate of MOSFET  121  is connected with node  111  and the gate of MOSFET  126  is connected with node  116 . In such embodiments, the bias voltages for MOSFETs  122 ,  123 ,  126 , and  127  are correspondingly modified as compared with those generated in the embodiments discussed below. 
     In embodiments where MOSFETs  121  and  126  are core transistors, MOSFETs  121  and  126  switch very fast and have low RDSon. 
     In embodiments where MOSFETs  123  and  128  are I/O transistors, MOSFETs  123  and  128  increase the breakdown voltage of switch stack  120 , and do not need to be actively switched on and off each cycle. Because they are not switched, the impact of their high gate charge is reduced. 
     In embodiments where MOSFETs  122  and  127  are either core transistors or I/O transistors, MOSFETs  122  and  127  increase the breakdown voltage of switch stack  120 , and may not be actively switched on and off each cycle. When not switched, the impact of their gate charge, whether relatively high or low, is reduced. 
     In the embodiment of  FIG. 2 , MOSFETs  122 ,  123 ,  127 , and  128  receive bias voltages at their gates respectively connected to one of the bias voltage inputs V 1 , V 2 , and V 3 , and are not switched. In some embodiments, a fourth bias voltage input is used, and each of MOSFETs  122 ,  123 ,  127 , and  128  receive a different bias voltage. In some embodiments, only two bias voltage inputs are used, bias voltage inputs V 1  and V 3 . In such embodiments, the gate of MOSFET  123  may be connected to bias voltage input V 1 , and the gate of MOSFET  128  may be connected to bias voltage input V 3 . 
     In alternative embodiments, MOSFETs  122 ,  123 ,  127 , and  128  may be switched between their bias voltages and either the voltage at input terminal Vin or ground. 
       FIG. 3  is a schematic illustration of buck converter  100  while the output of switch stack  120  is substantially equal to the voltage at Vin. Example voltages are indicated at the various nodes of switch stack  120 . In other embodiments, different voltages occur. 
     As shown in this example, the voltage at input terminal Vin is equal to 3 V, and the bias voltages at bias voltage inputs V 1 , V 2 , and V 3  are respectively 1 V, 1.5 V, and 2 V. In addition, the PWM signals applied to MOSFETs  121  and  126  are respectively 2 V and 0 V. 
     In response to their gate voltages, MOSFET  126  is substantially nonconductive, and MOSFETs  121 ,  122 , and  123  are conductive. Consequently, the voltage at the output of switch stack  120  is 3 V. In this state, the N-type MOSFETs  126 ,  127 , and  128  are at risk of experiencing damaging over voltages. However, because of their bias voltages, they do not. As shown, MOSFET  126  experiences 0.8 V, MOSFET  127  experiences 0.5 V, and MOSFET  128  experiences 1.7 V. 
       FIG. 4  is a waveform diagram illustrating a transition from 0 V to 3 V at the output Vx of switch stack  120  response to PWM signals applied to the gates of MOSFETs  121  and  126 . 
     As shown, the PWM signal Vg 121  applied to node  111  connected to the gate of 
     MOSFET  121  transitions from 3 V to 2 V. Likewise, substantially simultaneously, the PWM signal Vg 126  applied to node  116  connected to the gate of MOSFET  126  transitions from 1 V to 0 V. In response to the gate of MOSFET  121  transitioning from 3V to 2 V, MOSFET  121  turns on. Likewise, in response to the gate of MOSFET  126  transitioning from 1V to 0 V, MOSFET  126  turns off. Although not illustrated in  FIG. 4 , the PWM signals Vg 121  and Vg 126 , respectively applied to nodes  111  and  116 , are aligned in time so that MOSFET  126  turns off before MOSFET  121  turns on. 
     In response to MOSFET  121  turning on and MOSFET  126  turning off, the following transitions occur: the voltage at the drain of MOSFET  121  Vd 121  transitions from 2.2 V to 3 V, the voltage at the drain of MOSFET  122  Vd 122  transitions from 1.7 V to 3 V, the voltage at the drain of MOSFET  126  Vd 126  transitions from 0 V to 0.8 V, the voltage at the drain of MOSFET  127  Vd 127  transitions from 0 V to 1.3 V and the voltage at the output terminal Vx of switch stack  120  transitions from 0 V to 3 V. 
     During the output transitions from 0 V to 3 V, MOSFETs  126 ,  127 , and  128  may temporarily experience voltages higher than those indicated in  FIG. 4 . However, at least because of parasitic capacitances between each of the source nodes of transistors  127  and  128  and the nodes of switch stack  120  transitioning to 3 V, and because of sub-threshold conduction of transistors  127  and  128 , the duration and magnitude of the voltages higher than those indicated in  FIG. 3  experience by MOSFETs  126 ,  127 , and  128  are less than that which would be required to damage MOSFETs  126 ,  127 , and  128 . In some embodiments, switch stack  120  is physically formed with capacitive structures which increase the capacitance between each of the source nodes of transistors  127  and  128  and the nodes of switch stack  120  transitioning to 3 V. 
       FIG. 5  is a schematic illustration of buck converter  100  while the output of switch stack  120  is substantially equal to ground. Example voltages are indicated at the various nodes of switch stack  120 . In other embodiments, different voltages occur. 
     As shown in this example, the voltage at input terminal Vin is equal to 3 V, and the bias voltages at bias voltage inputs V 1 , V 2 , and V 3  are respectively 1 V, 1.5 V, and 2 V. In addition, the PWM signals applied to MOSFETs  121  and  126  are respectively 3 V and 1 V. 
     In response to their gate voltages, MOSFET  121  is substantially nonconductive, and MOSFETs  126 ,  127 , and  128  are conductive. Consequently, the voltage at the output of switch stack  120  is 0 V. In this state, the P-type MOSFETs  121 ,  122 , and  123  are at risk of experiencing damaging over voltages. However, because of their bias voltages, they do not. As shown, MOSFET  121  experiences 0.8 V, MOSFET  122  experiences 0.5 V, and MOSFET  123  experiences 1.7 V. 
       FIG. 6  is a waveform diagram illustrating a transition from 3 V to 0 V at the output Vx of switch stack  120  response to PWM signals applied to the gates of MOSFETs  121  and  126 . 
     As shown, the PWM signal Vg 121  applied to node  111  connected to the gate of MOSFET  121  transitions from 2 V to 3 V. Likewise, substantially simultaneously, the PWM signal Vg 126  applied to node  116  connected to the gate of MOSFET  126  transitions from 0 V to 1 V. In response to the gate of MOSFET  121  transitioning from 2 V to 3 V, MOSFET  121  turns off. Likewise, in response to the gate of MOSFET  126  transitioning from 0 V to 1 V, MOSFET  126  turns on. Although not illustrated in  FIG. 6 , the PWM signals Vg 121  and Vg 126 , respectively applied to nodes  111  and  116 , are aligned in time so that MOSFET  126  turns on after MOSFET  121  turns off. 
     In response to MOSFET  121  turning on and MOSFET  126  turning off, the following transitions occur: the voltage at the drain of MOSFET  121  Vd 121  transitions from 3 V to 2.2 V, the voltage at the drain of MOSFET  122  Vd 122  transitions from 3 V to 1.7 V, the voltage at the drain of MOSFET  126  Vd 126  transitions from 0.8 V to 0 V, the voltage at the drain of MOSFET  127  Vd 127  transitions from 1.3 V to 0 V and the voltage at the output terminal Vx of switch stack  120  transitions from 3 V to 0 V. 
     During output transitions from 3 V to 0 V, MOSFETs  126 ,  127 , and  128  may temporarily experience voltages higher than those indicated in  FIG. 6 . However, at least because of parasitic capacitances between each of the source nodes of transistors  127  and  128  and the nodes of switch stack  120  transitioning to 0 V, and because of sub-threshold conduction of transistors  127  and  128 , the duration and magnitude of the voltages higher than those indicated in  FIG. 6  experience by MOSFETs  126 ,  127 , and  128  are less than that which would be required to damage MOSFETs  126 ,  127 , and  128 . In some embodiments, switch stack  120  is physically formed with capacitive structures which increase the capacitance between each of the source nodes of transistors  127  and  128  and the nodes of switch stack  120  transitioning to 0 V. 
     As shown in  FIGS. 4 and 6 , PWM controller  110  switches the gate of MOSFET  121  between 2 V and 3 V. Furthermore, as shown in  FIGS. 3 and 5 , 3 V is the voltage at Vin, and 2 V is the voltage at the bias voltage input V 3 . 
     Similarly, as shown in  FIGS. 4 and 6 , PWM controller  110  switches the gate of MOSFET  126  between 0 V and 1 V, and, as shown in  FIGS. 3 and 5 , 1 V is the voltage at the bias voltage input V 1  and 0 V is the ground voltage. 
       FIG. 7  is a schematic illustration of a portion  200  of a buck converter connected to bias voltage generators  230 ,  240 , and  250 . Portion  200  includes inverter  212 , inverter  214 , and switch stack  220 . In some embodiments, inverters  212  and  214  may be part of a PWM controller circuit, such as PWM controller  110  of  FIG. 2 . 
     As shown, the power and ground connections for inverter  212  are respectively connected to the input terminal Vin and bias voltage input V 3 . As a result, in response to a PWM signal driving inverter  212 , inverter  212  causes the gate voltage of transistor  121  to be either the voltage at input terminal Vin or the voltage at bias voltage input V 3 . 
     In addition, the power and ground connections for inverter  214  are respectively connected to bias voltage input V 1  and ground. As a result, in response to a PWM signal driving inverter  214 , inverter  214  causes the gate voltage of transistor  126  to be either the voltage at the voltage at bias voltage input V 1  or ground. 
     Bias voltage generators  230 ,  240 , and  250  are configured to respectively generate the bias voltages at V 1 , V 2 , and V 3 . Bias voltage generators  230 ,  240 , and  250  may have bias voltage generation architectures as known to those of ordinary skill in the art configured to generate fixed bias voltages. 
       FIG. 8  is a schematic illustration of a bias voltage generator  300  which may be used, for example as bias generator  250  to generate the bias voltage at V 3  in  FIG. 7 . 
     Bias voltage generator  300  includes resistor  310 , current source  315 , amplifier  320 , transistor  330 , and pull up device  340 . 
     Resistor  310  and current source  315  collectively generate a reference voltage substantially equal to the bias voltage to be applied to V 3 . The reference voltage is referenced to Vin, and is a fixed voltage drop VR from the voltage at Vin. The magnitude of the fixed voltage drop VR is determined by the IR drop in resistor  310 . In some embodiments, the fixed voltage drop VR is substantially equal to the voltage at V 1 , such that the reference voltage is substantially equal to the voltage at input terminal Vin minus the voltage at V 1 . 
     The reference voltage is applied to amplifier  320 , which in cooperation with transistor  330  and pull up device  340  generates the bias voltage applied to V 3 . 
     In some embodiments, transistor  330  is a P-type transistor, for example, in a source-follower configuration. In some embodiments, transistor  330  is an N-type transistor, for example, in a common-source configuration. In some embodiments, alternative configurations may be used. 
     Pull up device  340  may comprise one or more of a resistor, a diode-connected transistor, a current source, and a capacitor. 
     As shown, transistor  330  is connected to V 1 , which has a voltage generated by bias voltage generator  230 , as shown in  FIG. 7 . Therefore, the charge flowing through inverter  212  of  FIG. 7  from input terminal Vin to V 3  also flows through transistor  330  to V 1 . Consequently, because the charge is conducted to V 1 , it can be reused by another circuit powered by the voltage at V 1 , such as inverter  214 . 
     Though the present invention is disclosed by way of specific embodiments as described above, those embodiments are not intended to limit the present invention. Based on the methods and the technical aspects disclosed above, variations and changes may be made to the presented embodiments by those skilled in the art without departing from the spirit and the scope of the present invention.