Patent Publication Number: US-9837513-B2

Title: Semiconductor device and manufacturing method thereof

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The technical field of the present invention relates to a semiconductor device and a manufacturing method thereof. Note that in this specification, a semiconductor device refers to a semiconductor element itself or a device including a semiconductor element. As an example of such a semiconductor element, for example, a transistor (a thin film transistor and the like) can be given. In addition, a semiconductor device also refers to a display device such as a liquid crystal display device. 
     2. Description of the Related Art 
     In recent years, metal oxides having semiconductor characteristics (hereinafter, referred to as oxide semiconductors) have attracted attention. Oxide semiconductors may be applied to transistors (see Patent Documents 1 and 2), for example. 
     There are many types of transistors. For example, transistors may be classified as a bottom gate-type structure and a top gate-type structure according to the positional relationship among a substrate, a gate, and a channel formation region. A transistor structure having a gate placed between a channel formation region and a substrate is called a bottom gate-type structure. A transistor structure having a channel formation region placed between a gate and a substrate is called a top gate-type structure. 
     In addition, transistors may be classified as a bottom contact type and a top contact type according to connection portions of a source and a drain with a semiconductor layer in which a channel is formed. A transistor with a structure where the connection portions of a source and a drain with a semiconductor layer in which a channel is formed is placed on a substrate side is called a bottom contact type. A transistor with a structure where the connection portions of a source and a drain with a semiconductor layer in which a channel is formed is placed on a side opposite to a substrate (that is, a counter substrate side in a liquid crystal display device) is called a top contact type. 
     Types of transistors can be classified as a BGBC (bottom gate bottom contact) structure, a BGTC (bottom gate top contact) structure, a TGTC (top gate top contact) structure, and a TGBC (top gate bottom contact) structure. 
     REFERENCE 
     Patent Documents 
     [Patent Document 1] Japanese Published Patent Application No. 2007-123861 
     [Patent Document 2] Japanese Published Patent Application No. 2007-096055 
     SUMMARY OF THE INVENTION 
     An object of one embodiment of the present invention is to provide a transistor having a sufficiently large on-state current and a sufficiently small off-state current. Such a transistor having a sufficiently large on-state current and a sufficiently small off-state current has good switching characteristics. 
     Meanwhile, a transistor when applied to many types of products preferably has high reliability. 
     One of methods for examining reliability of transistors is a bias-temperature stress test (hereinafter, referred to as a Gate Bias Temperature (GBT) test). The GBT test is one kind of accelerated test and a change in characteristics, caused by long-term usage, of transistors can be evaluated in a short time. In particular, the amount of shift in threshold voltage of the transistor between before and after a GBT test is an important indicator for examining reliability. The smaller the shift in the threshold voltage between before and after a GBT test is, the higher the reliability of the transistor is. 
     In particular, the temperature of a substrate over which a transistor is formed is set at a fixed temperature. A source and a drain of the transistor are set at the same potential, and a gate is supplied with a potential different from those of the source and the drain for a certain period. The temperature of the substrate may be determined depending on the purpose of the test. Further, the potential applied to the gate is higher than the potential of the source and the drain (the potential of the source and the drain is the same) in a “+GBT test” while the potential applied to the gate is lower than the potential of the source and the drain (the potential of the source and the drain is the same) in a “−GBT test.” 
     Strength of the GBT test may be determined based on the temperature of a substrate and electric field intensity and time period of application of the electric field to a gate insulating layer. The electric field intensity in the gate insulating layer is determined as the value of a potential difference between a gate, and a source and a drain divided by the value of the thickness of the gate insulating layer. For example, when an electric field intensity of the gate insulating layer having a thickness of 100 nm is 2 MV/cm, the potential difference is 20 V. 
     Furthermore, the shift in the threshold voltage of a transistor having an oxide semiconductor in a channel formation region is also confirmed by a GBT test. 
     Therefore, one embodiment of the present invention is to provide a semiconductor device having high reliability and threshold voltage which is difficult to shift despite long term usage. 
     Further, another embodiment of the present invention is to provide a semiconductor device having high reliability and good switching characteristics. 
     Furthermore, a gate, a source and a drain of a transistor are preferably formed over the same layer as a gate wiring and a source wiring. The gate wiring and the source wiring are preferably formed of a material having high conductivity. 
     The semiconductor device having good switching characteristics, which is one embodiment of the present invention, can be obtained by forming a semiconductor layer serving as a channel formation region to have a sufficient thickness to the thickness of the gate insulating layer. 
     Further, the semiconductor device having high reliability, which is one embodiment of the present invention, can be obtained by improving coverage of each layer to be provided. 
     Specific structures of one preferred embodiment of the present invention will be described below. 
     One embodiment of the present invention is an etching method including at least first and second etching processes. Here, a “film to be etched” preferably has a three-layer structure including a first film, a second film, and a third film from the lower side. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. 
     The above-described etching method that is one embodiment of the present invention can be applied to a manufacturing process of a semiconductor device. In particular, when the “film to be etched” is a conductive film, the etching method that is one embodiment of the present invention, described above is preferably used. Especially, the “layer provided below and in contact with the first film” is preferably a semiconductor layer. In other words, a transistor is preferably a top contact type. 
     In other words, one embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of forming a first wiring layer; forming an insulating layer to cover the first wiring layer; forming a semiconductor layer over the insulating layer; stacking a first conductive film, a second conductive film, and a third conductive film in this order over the semiconductor layer; forming a resist mask over the third conductive film; and performing etching including at least two steps on the first to third conductive films using the resist mask to form separated second wiring layers having a three-layer structure. The two-step etching includes a first etching process, which is performed until at least the first conductive film is exposed, and a second etching process, which is performed under the condition that the etching rate for the first conductive film is higher than that in the first etching process and the etching rate for the semiconductor layer is lower than that in the first etching process. After the second etching process, the resist mask is removed using a resist stripper. 
     Another embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of forming a semiconductor layer; stacking a first conductive film, a second conductive film, and a third conductive film in this order over the semiconductor layer; forming a resist mask over the third conductive film; performing etching including at least two steps on the first to third conductive films using the resist mask to form separated first wiring layers having a three-layer structure; forming an insulating layer to cover the first wiring layer and the semiconductor layer; and forming a second wiring layer to overlap with the semiconductor layer over the insulating layer. The two-step etching includes a first etching process, which is performed until at least the first conductive film is exposed, and a second etching process, which is performed under the condition that the etching rate for the first conductive film is higher than that in the first etching process and the etching rate for the semiconductor layer is lower than that in the first etching process. After the second etching process, the resist mask is removed using a resist stripper. 
     Note that the present invention is not limited thereto and a transistor may be a bottom contact type. In other words, in the BGBC or TGBC structure, the above-described etching method may be used for the formation of the source and the drain having a three-layer structure. In the BGBC structure, the “layer provided below and in contact with the first film” is a gate insulating layer. In the TGBC structure, the “layer provided below and in contact with the first film” is an insulating film or a substrate to be a base. 
     However, the present invention is not limited thereto, and the above-described etching method that is one embodiment of the present invention can be used when a conductive film to be a gate is etched. 
     In one embodiment of the present invention having any one of the above-described structures, the first etching process is performed using a gas containing more chlorine than fluorine as its main component and the second etching process is performed using a gas containing more fluorine than chlorine as its main component. 
     More specifically, a mixture gas of a BCl 3  gas and a Cl 2  gas are given as a gas containing more chlorine than fluorine as its main component. As a gas containing more fluorine than chlorine, a SF 6  gas is given. 
     In one embodiment of the present invention having any one of the above-described structures, it is preferable that the first conductive film be thicker than the third conductive film. This is because the layer provided below and in contact with the first conductive film is not easily exposed in the first etching process when the first conductive film is formed to be thick, and wiring resistance is reduced when the first conductive film is formed to be thick although the third conductive film is preferably thin because of being etched by the first etching. 
     In one embodiment of the present invention having any one of the above-described structures, when the second conductive film is formed to be thick, a conductive material for forming the second conductive film preferably has higher conductivity than a conductive material for forming the first conductive film and the third conductive film. This is because wiring resistance is reduced when the second conductive film is formed to be thick. 
     In one embodiment of the present invention having any one of the above-described structures, the first conductive film and the third conductive film may be titanium films and the second conductive film may be aluminum film, for example. 
     In one embodiment of the present invention having any one of the above-described structures, the semiconductor layer may be an oxide semiconductor layer, for example. 
     In one embodiment of the present invention having any one of the above-described structures, the oxide semiconductor layer may be formed of a material of IGZO, for example. 
     According to one embodiment of the present invention, the “layer provided below and in contact with the first film” can be prevented from being thinned. Thus, in the case where the “layer provided below and in contact with the first film” is a semiconductor layer, reduction in the thickness of the semiconductor layer can be prevented. Thus, the on-state current of the semiconductor layer can become sufficiently large and the off-state current of the semiconductor layer can become sufficiently small. Further, variation in the thickness of the semiconductor layer within a substrate surface, which occurs due to etching, can be prevented and variation in characteristics can be prevented. 
     According to one embodiment of the present invention, a semiconductor device having characteristics which hardly shift in a GBT test can be obtained. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A to 1C  illustrate a method for manufacturing a semiconductor device of Embodiment 1. 
         FIGS. 2A to 2D  illustrate a method for manufacturing a semiconductor device of Embodiment 1. 
         FIGS. 3A to 3C  illustrate a method for manufacturing a semiconductor device of Embodiment 1. 
         FIGS. 4A to 4C  illustrate a method for manufacturing a semiconductor device of Embodiment 2. 
         FIGS. 5A to 5D  illustrate a method for manufacturing a semiconductor device of Embodiment 2. 
         FIGS. 6A to 6F  are electronic devices of Embodiment 3. 
         FIGS. 7A and 7B  are STEM images described in Example 1. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description and it is easily understood by those skilled in the art that the mode and details can be variously changed without departing from the scope and spirit of the present invention. Accordingly, the invention should not be construed as being limited to the description of the embodiments below. In describing structures of the present invention with reference to the drawings, the same reference numerals are used in common for the same portions in different drawings. The same hatching pattern is applied to similar parts, and the similar parts are not especially denoted by reference numerals in some cases. In addition, for convenience, an insulating layer is, in some cases, not illustrated in plan views. 
     Furthermore, hereinafter, ordinal numbers, such as “first” and “second,” are used merely for convenience, and the present invention is not limited to the numbers. 
     Embodiment 1 
     In this embodiment, a semiconductor device that is one embodiment of the present invention and a manufacturing method thereof are described. A transistor is given as an example of a semiconductor device. 
     A method for manufacturing a transistor of this embodiment, which is described with reference to  FIGS. 1A to 1C ,  FIGS. 2A to 2D , and  FIGS. 3A to 3C  includes the steps of forming a first wiring layer  102 ; forming a first insulating layer  104  to cover the first wiring layer  102 ; forming a semiconductor layer  106  over the first insulating layer  104 ; stacking a first conductive film  107 A, a second conductive film  107 B, and a third conductive film  107 C in this order over the semiconductor layer  106  to form a multilayer conductive film  107 ; and performing etching including at least two steps on the multilayer conductive film  107  to form separated second wiring layers  108  having a three-layer structure. The two-step etching includes a first etching process, which is performed until at least the first conductive film  107 A is exposed, and a second etching process, which is performed under the condition that the etching rate for the first conductive film  107 A is higher than that in the first etching process and the etching rate for the semiconductor layer  106  is lower than that in the first etching process. 
     First, the first wiring layer  102  is formed over a substrate  100  at the selected areas, the first insulating layer  104  is formed to cover the first wiring layer  102 , and the semiconductor layer  106  is formed over the first insulating layer  104  at the selected areas ( FIG. 1A ). 
     A substrate having an insulative surface may be used as the substrate  100 . For example, a glass substrate, a quartz substrate, a semiconductor substrate having an insulating layer formed on its surface, or a stainless steel substrate having an insulating layer formed on its surface may be used as the substrate  100 . 
     The first wiring layer  102  constitutes at least a gate of a transistor. The first wiring layer  102  may be formed of a conductive material. The first conductive layer  102  may be formed in such a manner that a conductive film is formed and is processed by photolithography. 
     The first insulating layer  104  constitutes at least a gate insulating layer of the transistor. The first insulating layer  104  may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. When the semiconductor layer  106  is an oxide semiconductor layer, the first insulating layer  104  is preferably formed by a sputtering method so that moisture and hydrogen are removed as much as possible from the first insulating layer  104  which is in contact with the semiconductor layer  106 . The first insulating layer  104  may be a single layer or a stack of a plurality of layers. 
     The first insulating layer  104  may be formed using gallium oxide, aluminum oxide, or other oxygen-excess oxides. 
     Note that “silicon oxynitride” contains more oxygen than nitrogen. 
     Further, “silicon nitride oxide” contains more nitrogen than oxygen. 
     Here, the semiconductor layer  106  is formed of oxide semiconductor. The semiconductor layer  106  may be formed in such a manner that a semiconductor film is formed and is processed by photolithography. For forming the semiconductor layer  106 , an oxide semiconductor, which made to be an intrinsic (I-type) or a substantially intrinsic (I-type) by removing impurities to highly purify the oxide semiconductor so that impurities which are carrier donors besides main components do not exist in the oxide semiconductor as much as possible, is used. 
     The highly purified oxide semiconductor layer contains extremely few carriers (close to zero), and the carrier concentration thereof is lower than 1×10 14 /cm 3 , preferably lower than 1×10 12 /cm 3 , more preferably lower than 1×10 11 /cm 3 . 
     The off-state current can be small in a transistor because the number of carriers in the oxide semiconductor layer for forming the semiconductor layer  106  is extremely small. It is preferable that off-state current be as low as possible. 
     It is important that the state of the interface (interface state, interface charge, and the like) between the first insulating layer  104  and the semiconductor layer  106  be adjusted to be appropriate because such a highly purified oxide semiconductor is very sensitive to the interface state and interface charge. Thus, it is preferable that the first insulating layer  104  which is in contact with the highly purified oxide semiconductor have high quality. Here, the “first insulating layer  104  has high quality” means that there are few defects on the surface or inside the first insulating layer  104  and few defect levels and interface states to trap charge, and it is difficult to generate a fixed charge. 
     The first insulating layer  104  is preferably formed by, for example, a high-density plasma CVD method using a microwave (e.g., a frequency of 2.45 GHz) because the first insulating layer  104  can be a dense layer having high withstand voltage. This is because a close contact between the purified oxide semiconductor layer and a high-quality gate insulating layer reduces interface states and produces desirable interface characteristics 
     Needless to say, another film formation method such as a sputtering method or a plasma CVD method can be employed as long as it enables formation of a high-quality insulating layer as the first insulating layer  104 . 
     As an oxide semiconductor to be the semiconductor layer  106 , the oxide semiconductor includes at least one element selected from In, Ga, Sn, Zn, Al, Mg, Hf, or lanthanoid like the following metal oxide can be used: a four-component metal oxide such as an In—Sn—Ga—Zn-based oxide semiconductor; a three-component metal oxide such as an In—Ga—Zn-based oxide semiconductor (also referred to as IGZO), an In—Sn—Zn-based oxide semiconductor, an In—Al—Zn-based oxide semiconductor, a Sn—Ga—Zn-based oxide semiconductor, an Al—Ga—Zn-based oxide semiconductor, or a Sn—Al—Zn-based oxide semiconductor, an In—Hf—Zn-based oxide semiconductor, an In—La—Zn-based oxide semiconductor, an In—Ce—Zn-based oxide semiconductor, an In—Pr—Zn-based oxide semiconductor, an In—Nd—Zn-based oxide semiconductor, an In—Pm—Zn-based oxide semiconductor, an In—Sm—Zn-based oxide semiconductor, an In—Eu—Zn-based oxide semiconductor, an In—Gd—Zn-based oxide semiconductor, an In—Tb—Zn-based oxide semiconductor, an In—Dy—Zn-based oxide semiconductor, an In—Ho—Zn-based oxide semiconductor, an In—Er—Zn-based oxide semiconductor, an In—Tm—Zn-based oxide semiconductor, an In—Yb—Zn-based oxide semiconductor, an In—Lu—Zn-based oxide semiconductor; a two-component metal oxide such as an In—Zn-based oxide semiconductor, a Sn—Zn-based oxide semiconductor, an Al—Zn-based oxide semiconductor, a Zn—Mg-based oxide semiconductor, a Sn—Mg-based oxide semiconductor, or an In—Mg-based oxide semiconductor; an one-component metal oxide such as an indium oxide, a tin oxide, or a zinc oxide; or the like. The above oxide semiconductor may contain SiO 2 . Here, for example, an In—Ga—Zn-based oxide semiconductor means an oxide semiconductor containing In, Ga, or Zn, and there is no particular limitation on the composition ratio thereof. Further, In—Ga—Zn-based oxide semiconductor may contain an element other than In, Ga, or Zn. 
     An oxide semiconductor to be the semiconductor layer  106  may be represented by the chemical formula, InMO 3 (ZnO) m  (m&gt;0). Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, M can be Ga, Ga and Al, Ga and Mn, or Ga and Co. The above oxide semiconductor may contain SiO 2 . 
     A target containing In 2 O 3 , Ga 2 O 3 , and ZnO at a composition ratio of 1:1:1 [molar ratio] may be used for forming the oxide semiconductor film to be the semiconductor layer  106  by a sputtering method. Without limitation on the material and the composition of the target, for example, a target containing In 2 O 3 , Ga 2 O 3 , and ZnO at a composition ratio of 1:1:2 [molar ratio] may be used. Here, for example, an In—Ga—Zn-based oxide semiconductor film means an oxide film containing indium (In), gallium (Ga), and zinc (Zn), and there is no particular limitation on the composition ratio. 
     The oxide semiconductor film for forming the semiconductor layer  106  is formed by a sputtering method with use of an In—Ga—Zn-based oxide semiconductor target. Further, the semiconductor layer  106  can be formed by a sputtering method under a rare gas (e.g., Ar) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas and an oxygen gas. 
     Further, the filling rate of the target is 90% to 100% inclusive, preferably 95% to 99.9% inclusive. With the use of the target having a high filling rate, the oxide semiconductor film to be formed can be a dense film. 
     Next, first heat treatment is performed on the semiconductor layer  106 . The oxide semiconductor layer can be dehydrated or dehydrogenated by the first heat treatment. The temperature of the first heat treatment is higher than or equal to 400° C. and lower than or equal to 750° C., preferably higher than or equal to 400° C. and lower than the strain point of the substrate. In this embodiment, heat treatment may be performed in a nitrogen gas atmosphere at 450° C. for one hour as the first heat treatment. Note that there is no particular limitation on timing of the first heat treatment as long as it is after formation of the oxide semiconductor layer. Further, the atmosphere for performing the first heat treatment may be not only a nitrogen gas atmosphere, but also a mixed gas atmosphere containing an oxygen gas and a nitrogen gas, an oxygen gas atmosphere, and an atmosphere from which moisture is sufficiently removed (dry air). After the first heat treatment, the oxide semiconductor layer is preferably processed without exposure to the air so that water or hydrogen can be prevented from reentering the oxide semiconductor layer 
     Dehydration or dehydrogenation may be performed on the first insulating layer  104  in advance by performing preheating before the semiconductor layer  106  is formed. 
     It is preferable that remaining moisture and hydrogen in a film-formation chamber be sufficiently removed before the semiconductor film to be the semiconductor layer  106  is formed. That is, before formation of the semiconductor film to be the semiconductor layer  106 , evacuation is preferably performed with an entrapment vacuum pump (e.g., a cryopump, an ion pump, or a titanium sublimation pump). 
     Next, the multilayer conductive film  107  is formed to cover the first insulating layer  104  and the semiconductor layer  106  ( FIG. 1B ). 
     The multilayer conductive film  107  includes the first conductive film  107 A, the second conductive film  107 B, and the third conductive film  107 C in this order from the substrate  100  side. The first conductive film  107 A, the second conductive film  107 B, and the third conductive film  107 C may be each formed of a conductive material. As a conductive material for forming the first conductive film  107 A and the second conductive film  107 C, Ti, W, Mo or Ta, or a nitride thereof can be given, for example. As a conductive material for forming the second conductive film  107 B, Al is given, for example. 
     Next, a resist mask  109  is formed over the multilayer conductive film  107  at the selected areas ( FIG. 1C ). The resist mask  109  may be formed by photolithography. 
     Next, etching is performed on the multilayer conductive film  107  using the resist mask  109 , whereby the second wiring layer  108  is formed. The second wiring layer  108  constitute at least source and drain of a transistor. The etching process for forming the second wiring layer  108  includes two-step etching. Here, the first and the second etching processes for forming the second wiring layer  108  are described with reference to  FIGS. 2A to 2D , paying attention to a region in  FIG. 1C  surrounded by a dotted frame. 
     First, using the resist mask  109  ( FIG. 2A ), the multilayer conductive film  107  is etched until at least the first conductive film  107 A is exposed (the first etching process). Here, the first conductive film  107 A is etched, whereby a first conductive film  107 D is formed. The first conductive film  107 D exists over the entire surface of the first insulating layer  104  and the semiconductor layer  106 , and there is no particular limitation on the etching depth of the first conductive film  107 A as long as the insulating layer  104  and the semiconductor layer  106  are not exposed ( FIG. 2B ). Note that a portion of the second conductive film  107 B, which does not overlap with the resist mask  109 , is etched, whereby a second conductive film  107 E is formed. Further, a portion of the third conductive film  107 C, which does not overlap with the resist mask  109 , is etched, whereby a third conductive film  107 F is formed. 
     Note that the first etching process may be performed in a gas atmosphere containing a large amount of chlorine as its main component (a larger amount of chlorine than fluorine). Here, as an example of the gas containing a large amount of chlorine, a CCl 4  gas, a SiCl 4  gas, a BCl 3  gas, or a Cl 2  gas can be given. Specifically, a mixed gas of a BCl 3  gas and a Cl 2  gas is preferably used. 
     Then, the first conductive film  107 D is etched until the first insulating layer  104  and the semiconductor layer  106  are exposed, whereby a first layer  108 A of the second wiring layer is formed (the second etching process). Here, the third conductive film  107 F is etched because of recession of the resist mask, whereby a third layer  108 C of the second wiring layer is formed. Note that in the second etching process, it is only necessary that at least the first insulating layer  104  and the semiconductor layer  106  are exposed and the exposed semiconductor layer  106  is not removed by the etching ( FIG. 2C ). 
     Note that the second etching process may be performed in a gas atmosphere containing a large amount of fluorine as its main component (a larger amount of fluorine than chlorine). Here, as an example of the gas containing a large amount of fluorine, a CF 4  gas, a SF 6  gas, a NF 3  gas, a CBrF 3  gas, CF 3 SO 3 H gas, or C 3 F 8  can be given. Specifically, a SF 6  gas is preferably used. 
     As described above, it is known that the gas containing a large amount of fluorine as its main component (specifically, a SF 6  gas) has a high etching rate for a resist mask and reduce the size of the resist mask (the resist mask is made to recede). Thus, the resist mask  109  is reduced in size by the second etching, whereby a resist mask  109 C is formed. Further, by the reduction in size of the resist mask  109 , a portion of the third conductive film  107 F, which does not overlap with the resist mask  109 C, is also etched. However, in the case where the second conductive film  107 E is formed of a material containing Al as its main component, for example, the second conductive film  107 E is not etched. 
     However, the present invention is not limited thereto, and a portion of the second conductive film  107 E, which does not overlap with the resist mask  109 C may be etched. 
     Lastly, the resist mask  109 C is removed ( FIG. 2D ). In the case where the second conductive film  107 E is formed of a material containing Al as its main component, a product containing aluminum is attached to a side wall of the second conductive film  107 E due to the second etching. When the resist mask  109 C is removed by a resist stripper in this state, the side wall of the second conductive film  107 E is slightly etched and a second layer  108 B of the second wiring layer is formed. Here, as the resist stripper, a chemical solution which corrodes aluminum may be used. “Nagase resist strip N-300” (manufactured by Nagase ChemteX Co., Ltd.) may be used, for example. Note that “Nagase resist strip N-300” (manufactured by Nagase ChemteX Co., Ltd.) includes 2-aminoethanol and glycol ether at 30 wt % and 70 wt %, respectively. 
     As described above, the multilayer conductive film  107  is etched to form the second wiring layers  108 , so that the separated second wiring layers  108  can be formed while the thickness of the semiconductor layer  106  in a portion to be a channel formation region is kept. By forming the second wiring layer  108  using such an etching method, variation in thickness of the semiconductor layer  106  in the portion to be a channel formation region within the substrate surface can be small even when the substrate  100  has a large area. 
     Further, in the second wiring layer  108  formed as described above, the side walls of the first layer  108 A, the second layer  108 B, and the third layer  108 C of the second wiring layer do not exist in the same plane. The second wiring layer  108  has a side wall with a three-stepped shape. 
     As explained above, the transistor according to this embodiment is achieved ( FIG. 3A ). 
     Note that the transistor shown in  FIG. 3A  is provided over the substrate  100  and includes the first wiring layer  102 , the first insulating layer  104  formed to cover the first wiring layer  102 , the semiconductor layer  106  formed over the first insulating layer  104 , and the second wiring layer  108  formed to overlap the semiconductor layer  106 . There is little difference between the thickness (referred to as “first thickness”) of a portion of the semiconductor layer  106 , which does not overlap with the second wiring layer  108  and the thickness (referred to as, “the second thickness”) of a portion of the semiconductor layer  106 , which overlaps with the second wiring layer  108 . 
     Further, in the transistor shown in  FIG. 3A , the on-state current of the transistor can be sufficiently large and the off-state current of the transistor can be sufficiently small because the thickness of the semiconductor layer  106  can be kept thick. Further, it is possible to achieve transistors in which variation in characteristics is small because there is little variation in thickness of semiconductor layers within the substrate surface due to etching even when the transistor  100  has a large area 
     The thickness of the semiconductor layer  106  may depend on the relationship with the thickness of the first insulating layer  104 . When the thickness of the first insulating layer  104  is 100 nm, the thickness of the semiconductor layer  106  may be approximately greater than or equal to 15 nm. The reliability of the transistor may be improved when the thickness of the semiconductor layer  106  is greater than or equal to 25 nm. The thickness of the semiconductor layer  106  is preferably 30 nm to 40 nm. 
     Meanwhile, a second insulating layer  110  is formed further in the transistor shown in  FIG. 3A  ( FIG. 3B ). 
     The second insulating layer  110  may be formed of silicon oxide, silicon nitride, silicon oxynitride or the like, and is preferably formed by a sputtering method. It is because water or hydrogen can be prevented from reentering the semiconductor layer  106 . Specifically, a portion of the second insulating layer  110 , which is in contact with the semiconductor layer  106 , is preferably formed of silicon oxide. Otherwise, when the second insulating layer  110  has a structure having a plurality of stacked layers, at least a layer, which is in contact with the semiconductor layer  106 , may be formed of silicon oxide, and an organic resin layer or the like may be formed over the silicon oxide layer. 
     Next, second heat treatment (preferably at greater than or equal to 200° C. and less than or equal to 400° C., for example, greater than or equal 250° C. and less than or equal to 350° C.) is performed in an inert gas atmosphere, or an oxygen gas atmosphere. For example, the second heat treatment is performed in a nitrogen gas atmosphere at 250° C. for one hour. In the second heat treatment, heat is applied while part of the oxide semiconductor layer (a channel formation region) is in contact with the second insulating layer  110 . Further, the second heat treatment may be performed after forming the second insulating layer  110 . However, the timing is not limited thereto. 
     Further, the third wiring layer  112  is formed over the second insulating layer  110  at the selected area to overlap with the channel formation region of the semiconductor layer  106  ( FIG. 3C ). Because the third wiring layer  112  functions as a back gate, it may be formed of conductive material. The third wiring layer  112  may be an electrically independent wiring, electrically connected to the first wiring layer  102 , or floating. The third wiring layer  112  can be formed using a material and a method which are similar to those of the first wiring layer  102   
     When the third wiring layer  112  is an electrically independent wiring, it may function as a back gate which does not depend on the potential of the first wiring layer  102 . In this case, it is possible to control the threshold voltage by the back gate. 
     When the third wiring layer  112  is electrically connected to the first wiring layer  102 , the potential of the third wiring layer  112  can be equal to the potential of the first wiring layer  102  or the potential in accordance with the potential of the first wiring layer  102 . When the third wiring layer  112  is set to the potential in accordance with the potential of the first wiring layer  102 , a resistor may be provided between a gate formed using the first wiring layer  102  and a back gate formed using the third wiring layer  112 . At this time, the current per unit area when the transistor is on can be increased. 
     When the third wiring layer  112  is floating, the third wiring layer  112  cannot function as a back gate, but it is possible to function as an additional protection layer for the semiconductor layer  106 . 
     Further, a transistor having the semiconductor layer  106 , which is a highly purified oxide semiconductor layer, can decrease the current in an off state (off-state current) to a level under 10 zA/μm (less than 10 zA per 1 μm of the channel width), under 100 zA/μm at 85° C. That is, the off-state current can be lowered to be around the measurement limit or below the measurement limit. 
     Embodiment 2 
     The present invention is not limited to the mode described in Embodiment 1. For example, a transistor may have a TGTC structure as a semiconductor device of one embodiment of the present invention. 
     A method for manufacturing a transistor according to one embodiment of the present invention, described with reference to  FIGS. 4A to 4C , and  FIGS. 5A to 5D  includes the steps of forming a semiconductor layer  206 ; stacking a first conductive film  207 A, a second conductive film  207 B, and a third conductive film  207 C in this order over the semiconductor layer  206  to form a multilayer conductive film  207 ; performing etching including at least two steps on the multilayer conductive film  207  to form the separated first wiring layers  208  having a three-layer structure; forming an insulating layer  210  to cover the first wiring layer  208  and the semiconductor layer  206 ; and forming a second wiring layer  212  over the semiconductor layer  210  to overlap with the semiconductor layer  206 . The two-step etching includes the first etching process, which is performed until at least the first conductive film  207 A is exposed, and the second etching process, which is performed under the condition that the etching rate for the first conductive film  207 A is higher than that in the first etching process and the etching rate for the semiconductor layer  206  is lower than that in the first etching process. 
     First, a base insulating layer  204  is preferably formed over the substrate  200 , and the semiconductor layer  206  is formed over the substrate  200  or the base insulating layer  204  at the selected area ( FIG. 4A ). 
     The substrate  200  may be the same as the substrate  100  of Embodiment 1. 
     The base insulating layer  204  can be formed of the same material and by the same method as the first insulating layer  104  of Embodiment 1. 
     The semiconductor layer  206  can be formed of the same material and by the same method as the semiconductor layer  106  of Embodiment 1. 
     Next, the multilayer conductive film  207  is formed over the base insulating layer  204  and the semiconductor layer  206 , and a resist mask  209  is formed over the multilayer conductive film  207  at the selected area ( FIG. 4A ). 
     The multilayer conductive film  207  can be formed of the same material and by the same method as the multilayer conductive film  107  of Embodiment 1. 
     The resist mask  209  can be formed by photolithography as the resist mask  109  of Embodiment 1. 
     Next, etching is performed on the multilayer conductive film  207  using the resist mask  209 , whereby the first wiring layer  208  is formed. The first wiring layer  208  constitutes at least source and drain of a transistor. The etching process for forming the first wiring layer  208  includes two-step etching. Here, the first and the second etching processes for forming the first wiring layer  208  are described with reference to  FIGS. 5A to 5D , paying attention to a region in  FIG. 4A  surrounded by a dotted frame. 
     First, using the resist mask  209  ( FIG. 5A ), the multilayer conductive film  207  is etched until at least the first conductive film  207 A is exposed (the first etching process). Here, the first conductive film  207 A is etched, whereby a first conductive film  207 D is formed. The first conductive film  207 D exists over the entire surface of the base insulating layer  204  and the semiconductor layer  206 , and there is no particular limitation on the etching depth of the first conductive film  207 A as long as the base insulating layer  204  and the semiconductor layer  206  are not exposed ( FIG. 5B ). Note that a portion of the second conductive film  207 B, which does not overlaps with the resist mask  209 , is etched, whereby a second conductive film  207 E is formed. Further, a portion of the third conductive film  207 C, which does not overlap with the resist mask  209 , is etched, whereby a third conductive film  207 F is formed. 
     Note that the first etching process may be performed in a gas atmosphere containing a large amount of chlorine as its main component (a larger amount of chlorine than fluorine). Here, as an example of the gas containing a large amount of chlorine, a CCl 4  gas, a SiCl 4  gas, a BCl 3  gas, or a Cl 2  gas can be given. Specifically, a mixed gas of a BCl 3  gas and a Cl 2  gas is preferably used. 
     Next, the first conductive film  207 D is etched until the base insulating layer  204  and the semiconductor layer  206  are exposed, whereby a first layer  208 A of the first wiring layer is formed (the second etching process). Here, the third conductive film  207 F is etched because of the recession of the resist mask, whereby a third layer  208 C of the first wiring layer is formed. Note that in the second etching process, it is only necessary that at least the base insulating layer  204  and the semiconductor layer  206  are exposed and the exposed semiconductor layer  206  is not removed by the etching ( FIG. 5C ). 
     Note that the second etching process may be performed in a gas atmosphere containing a large amount of fluorine as its main component (a larger amount of fluorine than chlorine). Here, as an example of the gas containing a large amount of fluorine, a CF 4  gas, a SF 6  gas, a NF 3  gas, a CBrF 3  gas, CF 3 SO 3 H gas, or C 3 F 8  can be given. Specifically, a SF 6  gas is preferably used. 
     As described above, it is known that the gas containing a large amount of fluorine as its main component (specifically, a SF 6  gas) has a high etching rate for a resist mask and reduce the size of the resist mask (the resist mask is made to recede). Thus, the resist mask  209  is reduced in size by the second etching, whereby a resist mask  209 C is formed. Further, by the reduction in size of the resist mask  209 , a portion of the third conductive film  207 F, which does not overlap with the resist mask  209 C, is also etched. However, in the case where the second conductive film  207 E is formed of a material containing Al as its main component, for example, the second conductive film  207 E is not etched. 
     However, the present invention is not limited thereto, and a portion of the second conductive film  207 E, which does not overlap with the resist mask  209 C, may be etched. 
     Lastly, the resist mask  209 C is removed ( FIG. 5D ). In the case where the second conductive film  207 E is formed of a material containing Al as its main component, a product containing aluminum is attached to a side wall of the second conductive film  207 E due to the second etching. When the resist mask  209 C is removed by a resist stripper in this state, the side wall of the second conductive film  207 E is slightly etched and a second layer  208 B of the first wiring layer is formed. Here, as the resist stripper, a chemical solution which corrodes aluminum may be used. “Nagase resist strip N-300” (manufactured by Nagase ChemteX Co., Ltd.) may be used, for example. 
     As described above, the multilayer conductive film  207  is etched to form the first wiring layers  208 , so that the separated first wiring layers  208  can be formed while the thickness of the semiconductor layer  206  in a portion to be a channel formation region is kept. By forming the first wiring layer  208  using such an etching method, variation in thickness of the semiconductor layer  206  in the portion to be a channel formation region within the substrate surface can be small even when the substrate  200  has a large area. 
     Further, in the second wiring layer  208  formed as described above, the side walls of the first layer  208 A, the second layer  208 B, and the third layer  208 C of the first wiring layer do not exist in the same plane. The first wiring layer  208  has a side wall with a three-stepped shape ( FIG. 4B ). 
     Then, the insulating layer  210  is formed over the first wiring layer  208 , the semiconductor layer  206 , and the base insulating layer  204  ( FIG. 4C ). The insulating layer  210  constitutes at least a gate insulating layer of the transistor. 
     The insulating layer  210  can be formed of the same material and by the same method as the first insulating layer  104  of Embodiment 1. Thus, the first insulating layer  210  may be formed using gallium oxide, aluminum oxide, or other oxygen-excess oxides. 
     Next, the second wiring layer  212  is formed over the insulating layer  210  at the selected area to overlap with at least the semiconductor layer  206  ( FIG. 4C ). The second wiring layer  212  constitutes at least a gate of the transistor. Accordingly, the transistor according to this embodiment is manufactured ( FIG. 4C ). 
     Further, the transistor shown in  FIG. 4C  includes the semiconductor layer  206 , the separated first wiring layers  208 , over the semiconductor layer  206 , the insulating layer  210  formed to cover the first wiring layer  208 , and the second wiring layer  212  provided over the insulating layer  210 . There is little difference between the thickness (hereinafter, “first thickness”) of a portion of the semiconductor layer  206 , which does not overlap with the first wiring layer  208  and the thickness (hereinafter, “the second thickness”) of a portion of the semiconductor layer  206 , which overlaps with the first wiring layer  208 . 
     Further, in the transistor shown in  FIG. 4C , the on-state current of the transistor can be sufficiently large and the off-state current of the transistor can be sufficiently small because the thickness of the semiconductor layer  206  can be kept thick. Further, it is possible to achieve transistors in which variation in characteristics is small because there is little variation in thickness of semiconductor layers within the substrate surface due to etching even when the transistor  200  has a large area 
     The thickness of the semiconductor layer  206  may depend on the relationship with the thickness of the insulating layer  210 . When the thickness of the insulating layer  210  is 100 nm, the thickness of the semiconductor layer  206  may be approximately greater than or equal to 15 nm. The reliability of the transistor is improved when the thickness of the semiconductor layer  206  is greater than or equal to 25 nm. The thickness of the semiconductor layer  206  is preferably greater than or equal to 25 nm and less than or equal to 50 nm. 
     As explained in this embodiment, a transistor having a TGTC structure may be manufactured by adjusting the thickness of the semiconductor layer. 
     Further, although not illustrated, a back gate may be provided between the base insulating layer  204  and the substrate  200  to overlap with the semiconductor layer  206 . Disposing the back gate in this manner may provide the same effect as forming the third wiring layer  112  in Embodiment 1. 
     Note that the oxide semiconductor layer is highly purified also in this embodiment. A transistor having the semiconductor layer  206 , which is a highly purified oxide semiconductor layer, can decrease the current in an off state (off-state current) to a level under 10 zA/μm (less than 10 zA per 1 μm of the channel width), under 100 zA/μm at 85° C. That is, the off current can be lowered to be around the measurement limit or below the measurement limit. 
     However, the present invention is not limited to the modes described in Embodiments 1 and 2, and can be changed as appropriate within the range without depart from the spirit of the present invention. For example, the transistor may have a BGBC structure or a TGBC structure. 
     Embodiment 3 
     Next, electronic devices according to an embodiment of the present invention will be described. In the electronic devices of this embodiment, at least one of transistors described in Embodiments 1 and 2 is mounted. Examples of the electronic devices of the present invention include a computer, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable information terminal (including a portable game machine, an audio reproducing device, and the like), a digital camera, a digital video camera, electronic paper, and a television device (also referred to as a television or a television receiver). For example, the transistor described in either Embodiment 1 or 2 may be used as a pixel transistor constituting a pixel portion of such an electronic device. 
       FIG. 6A  illustrates a laptop personal computer, which includes a housing  301 , a housing  302 , a display portion  303 , a keyboard  304 , and the like. The transistor described in either Embodiment 1 or 2 is provided in the housings  301  and  302 . By mounting the transistor described in Embodiment 1 or 2 on the laptop personal computer illustrated in  FIG. 6A , display unevenness of the display portion can be reduced and reliability can be improved. 
       FIG. 6B  illustrates a portable information terminal (PDA), which includes a display portion  313 , an external interface  315 , an operation button  314 , and the like in a main body  311 . Further, a stylus  312  for operating the portable information terminal or the like is provided. The transistor described in either Embodiment 1 or 2 is provided in the main body  311 . By mounting the transistor described in Embodiment 1 or 2 on the PDA illustrated in  FIG. 6B , display unevenness of the display portion can be reduced and reliability can be improved. 
       FIG. 6C  illustrates an e-book reader  320  mounted with electronic paper, which includes two housings of a housing  321  and a housing  323 . The housing  321  and the housing  323  include a display portion  325  and a display portion  327 , respectively. The housing  321  is combined with the housing  323  by a hinge  337 , so that the e-book reader  320  can be opened and closed using the hinge  337  as an axis. The housing  321  is provided with a power switch  331 , operation keys  333 , a speaker  335 , and the like. At least one of the housing  321  and the housing  323  is provided with the transistor described in either Embodiment 1 or 2. By mounting the transistor described in Embodiment 1 or 2 on the e-book reader illustrated in  FIG. 6C , display unevenness of the display portion can be reduced and reliability can be improved. 
       FIG. 6D  illustrates a mobile phone which includes two housings of a housing  340  and a housing  341 . Moreover, the housings  340  and  341  which are shown unfolded in  FIG. 6D  can overlap with each other by sliding. Thus, the mobile phone can be in a suitable size for portable use. The housing  341  includes a display panel  342 , a speaker  343 , a microphone  344 , a pointing device  346 , a camera lens  347 , an external connection terminal  348 , and the like. The housing  340  is provided with a solar cell  349  for charging the mobile phone, an external memory slot  350 , and the like. In addition, an antenna is incorporated in the housing  341 . At least one of the housing  340  and the housing  341  is provided with the transistor described in either Embodiment 1 or Embodiment 2. By mounting the transistor described in Embodiment 1 or 2 on the mobile phone illustrated in  FIG. 6D , display unevenness of the display portion can be reduced and reliability can be improved. 
       FIG. 6E  illustrates a digital camera which includes a main body  361 , a display portion  367 , an eyepiece  363 , an operation switch  364 , a display portion  365 , a battery  366 , and the like. The transistor described in either Embodiment 1 or 2 is provided in the main body  361 . By mounting the transistor described in Embodiment 1 or 2 on the digital camera illustrated in  FIG. 6E , display unevenness of the display portion can be reduced and reliability can be improved. 
       FIG. 6F  is a television set  370  which includes a housing  371 , a display portion  373 , a stand  375 , and the like. The television set  370  can be operated by an operation switch included in the housing  371  or by a remote controller  380 . In the housing  371  or the remote controller  380 , the transistor described in either Embodiment 1 or 2 is mounted. By mounting the transistor described in Embodiment 1 or 2 on the television set illustrated in  FIG. 6F , display unevenness of the display portion can be reduced and reliability can be improved. 
     Example 1 
     In this example, the transistor of Embodiment 1, that is, the transistor shown in  FIG. 3A  is actually fabricated, and STEM images of a cross section of the transistor are illustrated in  FIGS. 7A and 7B . 
     A glass substrate was used as the substrate  100 . Note that, a base insulating layer was formed using silicon oxynitride between the substrate  100  and the first wiring layer  102 . 
     The first wiring layer  102  was formed of tungsten and had a thickness of 150 nm. 
     The first insulating layer  104  was formed of a silicon oxynitride and had a thickness of 100 nm. 
     The semiconductor layer  106  was formed of an In—Ga—Zn—O-based oxide semiconductor and had a thickness of 50 nm. 
     The first layer  108 A of the second wiring layer was formed of Ti and had a thickness of 100 nm. The second layer  108 B of the second wiring layer was formed of Al and had a thickness of 200 nm. The third layer  108 C of the second wiring layer was formed of Ti and had a thickness of 50 nm. 
     The second insulating layer  110  was formed of a silicon oxide and had a thickness of 300 nm. 
     Here, two kinds of samples were prepared for comparison. 
     As for a first sample, etching for processing the multilayer conductive film  107  to form the second wiring layers  108  is performed using only a mixture gas of a BCl 3  gas and a Cl 2  gas. 
     As for a second sample, two-step etching for processing the multilayer conductive film  107  to form the second wiring layer  108  was performed. The first etching process was performed using a mixture gas of a BCl 3  gas and a Cl 2  gas, and the second etching process was performed using only a SF 6  gas. 
       FIG. 7A  is a cross-sectional STEM image of the side surface of the second wiring layer  108  in the first sample.  FIG. 7B  is a cross-sectional STEM image of the side surface of the second wiring layer  108  in the second sample. 
     As seen from  FIGS. 7A and 7B , the semiconductor layer  106  of the first sample is etched; however, the semiconductor layer  106  of the second sample is hardly etched. In other words, by the two-step etching that is one embodiment of the present invention, the layer provided below and in contact with the film to be etched was able to prevent from being etched while being etched deeply in a conventional method. 
     This application is based on Japanese Patent Application serial no. 2010-161374 filed with Japan Patent Office on Jul. 16, 2010, the entire contents of which are hereby incorporated by reference.