Patent Publication Number: US-10784191-B2

Title: Interface structures and methods for forming same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to U.S. Provisional Patent Application No. 62/480,022, filed on Mar. 31, 2017, the entire contents of which are incorporated by reference herein in their entirety and for all purposes. This application is related to U.S. patent application Ser. No. 15/709,309, Sep. 19, 2017, the entire contents of which are incorporated by reference herein in their entirety and for all purposes. 
    
    
     BACKGROUND 
     Field 
     The field relates to stacked and electrically interconnected structures and methods for forming the same. In particular, the field relates to elements (such as semiconductor dies) that are connected with an interface structure that defines a filter. 
     Description of the Related Art 
     Passive electronic components can be important at the system board level (e.g., motherboard level), at the package level, and/or at the device chip level. In various systems, passive components can be used to filter electrical signals so as to pass signals across one or more bands of frequencies and/or to attenuate (or block) signals across one or more bands of other frequencies. In some electronic devices, discrete passive components such as resistors, capacitors, and/or inductors may be mounted to the system board and/or to the package substrate in order to filter the electrical signals. However, the use of such discrete passive components may occupy valuable space in the package or the larger electronic device or system. 
     Accordingly, there remains a continuing need for improved incorporation of electrical components such as passive components into electronic systems or packages 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a schematic side view of a device that includes a stacked and electrically interconnected structure, according to various embodiments. 
         FIG. 1B  is a schematic diagram of an electronic system incorporating one or more devices with stacked and electrically interconnected structures, according to various embodiments. 
         FIG. 2A  is a schematic perspective view of an interface structure comprising a filter device, according to various embodiments. 
         FIG. 2B  is a schematic circuit diagram of the filter device of  FIG. 2A . 
         FIG. 2C  is a schematic perspective view of a first conductive interface feature of the interface structure shown in  FIG. 2A . 
         FIG. 2D  is a schematic perspective view of an intermediate non-conductive feature with a conductive interconnect that is incorporated into the interface structure of  FIG. 2A . 
         FIG. 2E  is a schematic perspective view of a second conductive interface feature of the interface structure shown in  FIG. 2A . 
         FIG. 2F  is a schematic side cross-sectional view of a portion of the interface structure of  FIG. 2A . 
         FIG. 2G  is a graph of gain versus frequency for a conventional band-reject filter. 
         FIG. 2H  is a graph of gain versus frequency for the filter shown and described in  FIGS. 2A-2F . 
         FIG. 3A  is a schematic perspective view of an interface structure comprising a filter device that can be modeled by an inductor in series with a capacitor, according to various embodiments. 
         FIG. 3B  is a schematic circuit diagram of the filter device of  FIG. 3A . 
         FIG. 3C  is a schematic perspective view of a first conductive interface feature of the interface structure shown in  FIG. 3A . 
         FIG. 3D  is a schematic perspective view of an intermediate non-conductive feature with a conductive interconnect that is incorporated into the interface structure of  FIG. 3A . 
         FIG. 3E  is a schematic perspective view of a second conductive interface feature of the interface structure shown in  FIG. 3A . 
         FIG. 3F  is a schematic side cross-sectional view of a portion of the interface structure of  FIG. 3A . 
         FIG. 3G  is a graph of gain versus frequency for the filter shown and described in  FIGS. 3A-3F . 
         FIG. 3H  is a schematic side sectional view of a filter, according to yet another embodiment. 
         FIG. 4A  is a schematic top plan view of a first conductive interface feature, according to various embodiments. 
         FIG. 4B  is a schematic top plan view of a second conductive interface feature, according to various embodiments. 
         FIG. 5A  is a schematic top plan view of a first conductive interface feature, according to another embodiment. 
         FIG. 5B  is a schematic top plan view of a second conductive interface feature, according to another embodiment. 
         FIG. 6A  is a top plan view of the conductive feature of  FIG. 2A , which can be incorporated into various types of filters and devices. 
         FIG. 6B  is a schematic circuit diagram of a radio frequency (RF) power amplifier output low pass filter that can be used in conjunction with various embodiments disclosed herein. 
         FIG. 6C  is a schematic circuit diagram of an RF down conversion device that can be used in conjunction with various embodiments disclosed herein. 
         FIG. 6D  is a schematic circuit diagram of an RF up conversion device that can be used in conjunction with various embodiments disclosed herein. 
         FIG. 6E  is a top plan view of a conductive feature in which the contact comprises a continuous, single contact. 
         FIG. 6F  is a top plan view of a conductive feature in which the contact comprises a plurality of polygonal contacts. 
         FIG. 6G  is a top plan view of a conductive feature in which the contact comprises a plurality of rounded contacts. 
         FIG. 7A  is a schematic top view of first and second conductive features that can be used in conjunction with the band-reject filter of  FIGS. 2A-2F . 
         FIG. 7B  is a schematic top view of the first and second conductive features that can be patterned to define a band pass filter, similar to the band pass filter described in  FIGS. 3A-3G . 
     
    
    
     DETAILED DESCRIPTION 
     Various embodiments disclosed herein relate to interface structures between two bonded elements (e.g., two bonded semiconductor elements) that can serve as passive filters to selectively attenuate (e.g., block or reduce) and/or pass electrical signals at various bands of frequencies. For example, one or more electronic components, particularly passive components, can be incorporated on an element, such as a semiconductor element, by way of direct bonding without an intervening adhesive. In some embodiments, two semiconductor elements can be patterned with conductive and non-conductive features such that, when the two semiconductor elements are bonded together (e.g., by way of direct bonds), the corresponding patterns mate to define one or a plurality of passive components between the bonded semiconductor elements. Beneficially, therefore, the embodiments disclosed herein can integrate electronic components, and particularly passive components (such as resistors, capacitors, inductors, or combinations thereof), into the bonded interface structure between the two semiconductor elements. While examples are provided for bonding semiconductor elements, the skilled artisan will appreciate that the principles and advantages taught herein are applicable to the bonding of other electronic circuit or device elements that may or may not include semiconductor materials. The integration of passive components into the interface region can advantageously enable smaller devices and/or packages, since the passive components need not be separately provided on the device die or on the package substrate. Rather, the passive components can be integrated with the mechanical and/or electrical connections formed along the bonded interface. Furthermore, the incorporation of a filter into the interface between bonded elements can improve the coupling of analog electronic devices to digital electronic devices. For example providing the passive devices (e.g., passive filters) electrically close to the circuits can significantly improve electrical performance. Moreover, as explained herein, conventional passive components (e.g., surface mount components) occupy a large portion of package or board space. Incorporating these passive components into the bonding layer (e.g., the interface structure) can reduce costs and the lateral footprint of the package or device, particularly as compared with larger passive surface mount components such as inductors. 
     In some embodiments, as explained herein, each of the two elements to be bonded can be defined with corresponding patterns, and the passive components can be defined along the bonded interface of the two elements. In some embodiments, the passive components can be defined in layers formed on one of the elements, and the one element can be bonded to the other element in any suitable manner, e.g., by direct bonding, or with an adhesive. In other embodiments, the passive components can be defined partially by layers formed on one element and partially in layers formed on another element, which layers can be bonded (e.g., direct bonded or bonded with an adhesive) to one another. 
       FIG. 1A  is a schematic side view of a device  1  that includes a stacked and electrically interconnected structure  7  (also referred to herein as stacked structures) according to various embodiments. The stacked structure  7  can comprise a first element  2  mounted to a second element  3 . As explained herein, in some embodiments, the first element  2  can be directly bonded to the second element  3  without an intervening adhesive. In other embodiments, however, an adhesive (e.g., an epoxy, solder, etc.) can be used to mount the first element  2  to the second element  3 . The first element  2  can comprise any suitable type of element, such as a semiconductor element (e.g., an integrated device die or chip, an interposer, etc.), an optical element, etc. For example, in some embodiments, the first element  2  can comprise an integrated device die, such as a memory die, a processor die, a microelectromechanical systems (MEMS) die, a sensor die, etc. Similarly, the second element  3  can comprise any suitable type of element, such as a semiconductor element (e.g., an integrated device die or chip, an interposer, etc.), an optical element, etc. For example, in some embodiments, the second element  3  can comprise an integrated device die, such as a memory die, a processor die, a microelectromechanical systems (MEMS) die, a sensor die, etc. In other embodiments, the second element  3  can comprise an interposer or a package substrate (e.g., a laminate or printed circuit board substrate, a ceramic substrate, etc.). 
     As shown in  FIG. 1A , the device  1  can comprise one or a plurality of interface structures  10  that mechanically and electrically connect the first and second elements  2 ,  3 . The interface structure  10  can provide a mechanical and electrical connection between the elements  2 ,  3 . As explained herein, the interface structure  10  can be patterned or formed to define various types of passive electronic components, such as inductors and capacitors, which can be arranged to filter electrical signals. The interface structure  10  can comprise one or a plurality of conductive features  12  and one or a plurality of non-conductive features  14 . In some embodiments, the conductive and non-conductive features  12 ,  14  may be patterned entirely on one of the elements  2 ,  3 , and, when the elements  2 ,  3  are bonded, the interface structure  10  can comprise the features  12 ,  14 . In the illustrated embodiment, however, the first element  2  can comprise first conductive features  12 A and first non-conductive features  14 A. The second element  3  can comprise second conductive features  12 B and second non-conductive features  14 B. When the first and second elements  2 ,  3  are bonded, the first and second conductive features  12 A,  12 B can be bonded to define the conductive feature  12 , and the first and second non-conductive features  14 A,  14 B can be bonded to define the non-conductive feature  14 . 
     The interface structures  10  disclosed and illustrated herein can include filters or other passive electronic devices along the bonding interface between the elements  2 ,  3 . It should be appreciated that other types of connections, besides the illustrated filters  15 , may also be provided between the elements  2 ,  3  (e.g., along the bonding interface). For example, in the embodiments disclosed herein, direct metal connections between corresponding bond pads of the elements  2 ,  3  may also be provided, e.g., to transfer signals between the dies. In the disclosed embodiments, therefore, through-signal connections, power supply connections, ground connections, or other electrical connections may be provided across the bonding interface between the elements  2 ,  3 . 
     In the embodiments disclosed herein, the interface structures  10  can be formed or defined during wafer-level fabrication processes. For example, in some embodiments, the interface structures  10  (e.g., the conductive and/or nonconductive features  12 ,  14  disclosed herein) can be fabricated as layer(s) with semiconductor processing techniques (e.g., deposition, lithography, etc.), before dicing of the wafer into elements or chips. In some embodiments, the interface structures  10  (e.g., the conductive and/or nonconductive features  12 ,  14 ) can be fabricated as part of the elements  2 ,  3  (e.g. as part of a semiconductor chip or die), and/or as part of a redistribution layer (RDL) of the elements  2 ,  3 . In some embodiments, the interface structures  10  can be provided along respective bonding surfaces of the elements  2 ,  3 . In other embodiments, the interface structures  10  can be provided between bond pads of the elements  2 ,  3  and the outer surface (e.g., a bonding surface) of the elements  2 ,  3 . 
     In the illustrated embodiment, the first and second elements  2 ,  3  can be directly bonded to one another without an intervening adhesive, to define a direct bond interface  13 . In such embodiments, the interface structure  10  can comprise conductive and non-conductive features  12 ,  14  patterned to define a passive device such as a filter. To accomplish the direct bonding, in some embodiments, respective bonding surfaces  8 ,  9  of the first and second elements  2 ,  3  (e.g., bonding surfaces of the conductive features  12 A,  12 B, and of the non-conductive features  14 A,  14 B) can be prepared for bonding. The bonding surfaces  8 ,  9  of the conductive and non-conductive features  12 ,  14  of the interface structure  10  can be polished to a very high degree of smoothness (e.g., less than 20 nm surface roughness, or more particularly, less than 5 nm surface roughness). In some embodiments, the surfaces to be bonded may be terminated with a suitable species and activated prior to bonding. For example, in some embodiments, the non-conductive surfaces  14 A,  14 B to be bonded may be very lightly etched for activation and exposed to a nitrogen-containing solution and terminated with a nitrogen-containing species. As one example, the surfaces to be bonded (e.g., non-conductive field regions  14 A,  14 B) may be exposed to an ammonia dip after a very slight etch, and/or a nitrogen-containing plasma (with or without a separate etch). 
     In some embodiments, the conductive features  12 A,  12 B of the first and second elements  2 ,  3  can be flush with the exterior surfaces (e.g., the non-conductive features  14 A,  14 B) of the respective elements  2 ,  3 . In other embodiments, the conductive features  12 A,  12 B may extend above the exterior surfaces (e.g., the non-conductive features  14 A,  14 B) of the respective elements  2 ,  3 . In still other embodiments, the conductive features  12 A,  12 B can be recessed relative to the exterior surfaces (e.g., non-conductive features  14 A,  14 B) of the respective elements  2 ,  3 . 
     Once the respective bonding surfaces  2 ,  3  are prepared, the non-conductive features  14 A of the first element  2  can be brought into contact with corresponding non-conductive features  14 B of the second element  3 . The interaction of the activated surfaces can cause the non-conductive features  14 A of the first element  2  to directly bond with the corresponding non-conductive features  14 B of the second element  3  without an intervening adhesive, without application of external pressure, without application of voltage, and at room temperature. In various embodiments, the bonding forces of the non-conductive features  14 A,  14 B can include covalent bonds that are greater than Van der Waals bonds and exert significant forces between the conductive features  12 A,  12 B. Regardless of whether the conductive features  12 A,  12 B are flush with the nonconductive features  14 A,  14 B, recessed or protrude, direct bonding of the nonconductive features  14 A,  14 B can facilitate direct metal-to-metal bonding between the conductive features  12 A,  12 B. In various embodiments, the elements  2 ,  3  may be heated after bonding to strengthen the bonds between the nonconductive features  14 A,  14 B, between the conductive features  12 A,  12 B, and/or between opposing conductive and non-conductive regions, to cause the elements  2 ,  3  to bond to one another, to form a direct electrical and mechanical connection. 
     Additional details of the direct bonding processes used in conjunction with each of the disclosed embodiments may be found throughout U.S. Pat. Nos. 7,126,212; 8,153,505; 7,622,324; 7,602,070; 8,163,373; 8,389,378; and 8,735,219, and throughout U.S. Patent Publication Nos. US 2017/0062366; US 2017/0200711; and US 2017/0338214, the contents of each of which are hereby incorporated by reference herein in their entirety and for all purposes. In other embodiments, however, the elements  2 ,  3  can be directly electrically connected using a conductive adhesive. For example, in such other embodiments, the conductive features of the interface structure  10  can be connected together using a conductive epoxy, solder, or any other suitable conductive adhesive. 
       FIG. 1B  is a schematic diagram of an electronic system  80  incorporating one or more devices  1  with stacked and electrically interconnected structures  7 , according to various embodiments. The system  80  can comprise any suitable type of electronic device, such as a mobile electronic device (e.g., a smartphone, a tablet computing device, a laptop computer, etc.), a desktop computer, an automobile or components thereof, a stereo system, a medical device, a camera, or any other suitable type of system. In some embodiments, the electronic system  80  can comprise a microprocessor, a graphics processor, an electronic recording device, or digital memory. The system  80  can include one or more device packages  82  which are mechanically and electrically connected to the system  80 , e.g., by way of one or more motherboards. Each package  82  can comprise one or more devices  1 . The system  80  shown in  FIG. 1B  can comprise any of the stacked structures  7  shown and described herein. 
     In some devices, it can be challenging to integrated filters into the packaging structure. For example, in some devices, the filter may be surface mounted to the package substrate and/or to the system motherboard. In such arrangements, the filter may occupy valuable space on the package substrate or board, which may increase the overall lateral area or footprint of the device. Furthermore, analog devices formed in Group III-IV semiconductor materials may not utilize a high number of layers. In some Group III-IV analog devices, for example, only one to three layers may be used. Embodiments disclosed herein may utilize stacked and electrically connected structures  7  that can be directly bonded to one another without an intervening adhesive, which can beneficially increase the overall layer count for Group III-IV semiconductor devices. Further, in the disclosed embodiments, package and/or board space may be conserved by providing the filter devices in the interface structure  10  between the elements  2 ,  3 . 
       FIG. 2A  is a schematic perspective view of an interface structure  10  comprising a filter device  15 , according to various embodiments.  FIG. 2B  is a schematic circuit diagram of the filter device  15  of  FIG. 2A .  FIG. 2C  is a schematic perspective view of a first conductive interface feature  12 A of the interface structure  10  shown in  FIG. 2A .  FIG. 2D  is a schematic perspective view of an intermediate non-conductive feature  14  with a conductive interconnect  16  that is incorporated into the interface structure  10  of  FIG. 2A .  FIG. 2E  is a schematic perspective view of a second conductive interface feature  12 B of the interface structure  10  shown in  FIG. 2A .  FIG. 2F  is a schematic side cross-sectional view of a portion of the interface structure  10  of  FIG. 2A . 
     As shown, the interface structure  10  of  FIG. 2A  can comprise the first conductive feature  12 A, the second conductive feature  12 B, and the non-conductive feature  14  disposed between the first and second conductive features  12 A,  12 B. As shown in the equivalent circuit diagram of  FIG. 2B , the interface structure  10  can serve as a filter  15 , which can be modeled as an inductor L in parallel with a capacitor C. As explained below in connection with  FIG. 2H , the filter  15  of  FIGS. 2A-2F  can serve as a band-reject filter that attenuates (e.g., reduces or blocks the amplitude of) an electrical signal at a desired frequency or range of frequencies. 
     As illustrated in  FIGS. 2A and 2C-2E , the interface structure can comprise a plurality of segments  17 A,  17 B,  17 C, which traverse a plurality of turns about a vertical axis z of the structure  10 . As shown the vertical axis z can be approximately perpendicular to the direct bond interface  13  and/or to the major lateral dimension of the elements  2 ,  3 . The segments  17 A- 17 C can turn about the z axis in a particular direction, e.g., clockwise or counterclockwise. As shown, the first segment  17 A can extend along the x-direction, the second segment  17 B can extend from the first segment  17 A along they-direction, and the third segment  17 C can extend from the second segment  17 B along the −x-direction. Further, as shown in  FIGS. 2C and 2E , an insulating gap  4  can electrically separate the segments  17 A- 17 C laterally so as to direct current around the z-axis. As shown, for example, the gap  4  can comprise a first insulating gap region  4 A lying in a region between the first, second, and third segments  17 A- 17 C. A second insulating gap region  4 B can extend along the −x direction from the first gap region  4 A and can electrically separate the first and third segments  17 A,  17 C. The insulating gap can comprise any suitable insulating material, e.g., silicon oxide. Providing the insulating gap regions  4 A,  4 B between the segments  17 A- 17 C in the manner shown in  FIGS. 2A and 2C-2E  can beneficially enable electrical current to flow along the turns of the conductive features  12 A,  12 B, which can create an inductance L for the filter  15 . 
     Thus, as shown in the model of  FIG. 2B , the filter  15  can comprise an inductive current pathway P L  and a capacitive current pathway P C  (see  FIG. 2F ) in parallel with the inductive current pathway P L . As explained above, and as shown in  FIGS. 2A-2C , the turning of the segments  17 A- 17 C in the first conductive feature  12 A can generate an inductive pathway P L  along the segments  17 A- 17 C of the first feature  12 A. For example, as shown in  FIGS. 2A and 2C , current can be introduced into the interface structure  10  by way of an input terminal  6 A and can exit the interface structure  10  by way of an output terminal  6 B. The inductive pathway P L  can pass along the first segment  17 A, the second segment  17 B, and the third segment  17 C. Directing the current along the turns of the first conductive feature  12 A can generate at least a portion of the inductance L for the filter  15 . 
     As shown in  FIG. 2D  and in the cross-section of  FIG. 2F , the non-conductive feature  14  can be disposed or sandwiched between the first and second conductive features  12 A,  12 B. In the illustrated embodiment, the first conductive feature  12 A can be applied or formed on the first element  2 , and the second conductive feature  12 B can be applied or formed on the second element  3 . Furthermore, the non-conductive feature  14  shown in  FIG. 2D  can comprise a first non-conductive feature  14 A applied or formed on the first element  2  (e.g., on the first conductive feature  12 A). The non-conductive feature  14  can further comprise a second non-conductive feature  14 B applied or formed on the second element  3  (e.g., on the second conductive feature  12 B). When the first and second elements  2 ,  3  are bonded to form the direct bond interface  13 , the first and second non-conductive features  14 A,  14 B can cooperate to define the non-conductive feature  14 . 
     As shown in  FIGS. 2D and 2F , a conductive interconnect  16  can be provided through the non-conductive interface feature  14  from the first conductive feature  12 A to the second conductive feature  12 B. The conductive interconnect  16  can serve as a direct electrical connection, or short, between the conductive features  12 A,  12 B. The inductive pathway P L  can accordingly extend from the first conductive feature  12 A, through the interconnect  16 , to the second conductive feature  12 B. As shown in  FIG. 2F , the second conductive feature  12 B can extend underneath the insulating gap region  4 B (for example, as shown in  FIG. 2F , the right portion of conductive feature  12 B can extend underneath the gap region  4 B and extend leftward laterally beyond the interconnect  16 ). A third insulating gap region  4 C can be provided in the second conductive feature  12 B. As illustrated in  FIG. 2F , the conductive interconnect  16  can comprise a third conductive feature  12 C provided adjacent the first non-conductive feature  14 A and over the first conductive feature  12 A. The conductive interconnect  16  can further comprise a fourth conductive feature  12 D provided adjacent the second non-conductive feature  14 B and over the second conductive feature  12 B. As with the non-conductive features  14 A,  14 B, the third and fourth conductive features  12 C,  12 D can be directly bonded to one another without an intervening adhesive to form a part of the direct bond interface  13 . 
     Thus, in the illustrated embodiment, the first and third conductive features  12 A,  12 C, and the first non-conductive feature  14 A can be provided on the first element  2 , and the second and further conductive features  12 B,  12 D, and the second non-conductive feature  14 B can be provided on the second element  3 . In other embodiments, however, more or fewer layers may be provided on each element  2 ,  3 . For example, in some embodiments, the entire filter  15  may be provided on only one of the elements  2 ,  3 . In other embodiments, some of the conductive and/or non-conductive features may be provided on one element, and other of the conductive and/or non-conductive features may be provided on the other element. 
     Turning to  FIG. 2E , the inductive pathway P L  can pass vertically from the first conductive feature  12 A, through the interconnect  16 , and into the second conductive feature  12 B. In  FIG. 2F , for example, the inductive pathway P L  can extend laterally to the portion of the conductive feature  12 B shown on the right hand side of  FIG. 2F . As with the first conductive feature  12 A, the second conductive feature  12 B can comprise a plurality of turns, in which the segments  17 A- 17 C define the turns around the z-axis. The inductive pathway P L  can traverse along the segments  17 A- 17 C and around the insulating gap region  4 A. In some embodiments, the inductive pathway P L  can extend counterclockwise (or clockwise) around both conductive features  12 A,  12 B. In other embodiments, the pathway P L  may extend in opposite directions (e.g., clockwise in one conductive feature and counterclockwise in the other direction). The inductive pathway P L  can exit the interface structure  10  through the output terminal  6 B and can be routed to other structures or circuits in the second element  3 . 
     Returning to  FIG. 2F , the capacitor C of the model circuit of  FIG. 2B  can be defined by the first and second conductive features  12 A,  12 B and the intervening non-conductive feature  14 . Thus, as shown in  FIG. 2F , the first conductive feature  12 A can serve as a first terminal of the capacitor C, the second conductive feature  12 B can serve as a second terminal of the capacitor C, and the non-conductive feature  14  can serve as the intervening dielectric. Accordingly, the capacitive electrical pathway P C  can extend vertically from the first conductive feature  12 A, through the non-conductive feature  14 , to the second conductive feature  12 B. As above, the conductive pathway P C  can exit the interface structure  10  through the output terminal  6 B. 
     Thus, as explained herein, the interface structure  10  disclosed herein can provide an inductive electrical pathway P L  in parallel to a capacitive electrical pathway P C . As explained above, the inductive electrical pathway P L  can extend around the turns of the segments  17 A- 17 C of the first and second conductive features  12 A,  12 B. The interconnect  16  can provide an electrical connection between the first and second conductive features  12 A,  12 B. The capacitive electrical pathway P C  can extend through the thickness of the interface structure  10 , e.g., from the first conductive feature  12 A, through the non-conductive feature  14 , to the second conductive feature  12 B. 
     In various embodiments, the conductive features  12 A- 12 D and non-conductive features  14 A- 14 B can be patterned to have the desired inductance L and capacitance C values to form the filter  15  for passing and/or attenuating signals at various bands. In various embodiments, the conductive features  12 A- 12 D and non-conductive features  14 A- 14 B can be patterned to have any suitable or desired inductance L. In various embodiments, the conductive features  12 A- 12 D and non-conductive features  14 A- 14 B can be patterned to have any suitable capacitance C. The inductance L can be tuned in various ways. For example, in some embodiments, the number of turns or segments  17 A- 17 C along the first and second conductive features  12 A,  12 B can be selected so as to achieve the desired inductance L. In some embodiments, a width w of the segments  17 A- 17 C can be selected so as to achieve the desired inductance L. For example, the width w of the segments  17 A- 17 C can be in a range of 0.1 microns to 2 microns. In some embodiments, a thickness of the conductive features  12 A,  12 B and/or the nonconductive features  14  may also be selected so as to achieve the desired inductance L. 
     Similarly, the capacitance C can be tuned in a variety of ways. For example, the capacitance C can be selected based on one or more of, e.g., a thickness t of the non-conductive feature  14 , an area A of the conductive features  12 A,  12 B (which can comprise the sum of A 1  and A 2  shown in  FIG. 2F  so as to account for the area covered by the conductive interconnect  16 ), and/or the material to be used for the metallic and/or non-metallic features  12 ,  14 . In various embodiments, for example, the thickness t of the non-conductive feature  14  can be in a range of 0.1 microns to 2 microns. The overall area A can be selected to achieve the desired capacitance C, with the overall area A=A 1 +A 2 , so as to account for the area covered by the conductive interconnect  16 . 
     The conductive features  12 A,  12 B can comprise any suitable conductive material, including metals such as copper, aluminum, gold, silver, metal alloys, other metals, etc. In some embodiments, the conductive features  12 A,  12 B can comprise surface layers, such as barrier layers (e.g., a metal nitride barrier material, such as a titanium nitride barrier material). The non-conductive features  14 A,  14 B can comprise any suitable non-conductive or dielectric material, such as silicon oxide. 
       FIG. 2G  is a graph of gain versus frequency for a conventional band-reject filter.  FIG. 2H  is a graph of gain versus frequency for the filter  15  shown and described in  FIGS. 2A-2F . The embodiment of  FIGS. 2A-2F  can beneficially serve as a band-reject filter or resonator in which signals at one or a plurality of frequencies are rejected or attenuated, and signals at other frequencies are passed or transmitted. As shown by the insertion loss plot of  FIG. 2H , electrical signals at frequencies in a reject band between about 2.2 GHz and about 2.4 GHz can be attenuated, while electrical signals at frequencies outside this reject band can be passed with little or negligible transmission losses. Beneficially, the performance of the filter  15  shown in  FIG. 2H  (e.g., the filter  15  of  FIGS. 2A-2F ) can provide a relatively narrow reject band that can accurately and selectively reject or attenuate certain frequencies. For example, it is desirable to have finite, well-defined bands for frequency rejection. Having a narrow band (or multiple narrow bands) may improve the performance of the filter. By contrast, in the conventional filter of  FIG. 2G , the insertion loss plot indicates that frequencies across a much wider band of frequencies (e.g., 2 GHz to 4 GHz) may be attenuated. For example, the shallower, sloping range of  FIG. 2G  may not perform as well as the filter of  FIG. 2H , since  FIG. 2G  includes wider bands for rejection, which makes filtering of undesirable bands and maintenance of desired bands more challenging. Thus, the embodiments disclosed herein enable for higher selectivity filters that may be provided along the bond interface between two elements. 
       FIGS. 3A-3G  illustrate other embodiments of filters  15  that can be formed in accordance with various embodiments disclosed herein.  FIG. 3A  is a schematic perspective view of an interface structure  10  comprising a filter device  15  that can be modeled by an inductor in series with a capacitor, according to various embodiments.  FIG. 3B  is a schematic circuit diagram of the filter device  15  of  FIG. 3A .  FIG. 3C  is a schematic perspective view of a first conductive interface feature  12 A of the interface structure  10  shown in  FIG. 3A .  FIG. 3D  is a schematic perspective view of an intermediate non-conductive feature  14  with a conductive interconnect  16  that is incorporated into the interface structure  10  of  FIG. 3A .  FIG. 3E  is a schematic perspective view of a second conductive interface feature  12 B of the interface structure  10  shown in  FIG. 3A .  FIG. 3F  is a schematic side cross-sectional view of a portion of the interface structure  10  of  FIG. 3A . Unless otherwise noted, components shown in  FIGS. 3A-3F  may be the same as or generally similar to like-numbered components of  FIGS. 2A-2F . 
     As with the embodiment of  FIGS. 2A-2F , the interface structure  10  of  FIG. 3A-3F  can comprise a first conductive feature  12 A, a second conductive feature  12 B, and an intervening non-conductive feature  14  disposed or sandwiched between the conductive features  12 A,  12 B, to define the filter device  15 . Unlike the embodiment of  FIGS. 2A-2F  (which can be modeled as a capacitor C in parallel with an inductor L), in the embodiment of  FIGS. 3A-3F , the filter device  15  can be modeled as a capacitor C in series with an inductor L. Further, unlike the embodiment of  FIGS. 2A-2F , the filter device  15  can serve as a bandpass filter or resonator, in which electrical signals at a band of one or more frequencies are passed, while signals with frequencies outside the band are attenuated (e.g., blocked or reduced in amplitude), as shown in  FIG. 3G . 
     As shown in  FIG. 3C , the first conductive feature  12 A can electrically communicate with the input terminal  6 A. The first conductive feature  12 A can comprise any suitable size or shape, and can serve as an electrical input pad to the filter  15 . Turning to  FIGS. 3D-3F , the non-conductive feature  14  can be provided between the first conductive feature  12 A and the second conductive feature  12 B. As with the embodiment of  FIGS. 2A-2F , the non-conductive feature  14  can comprise a first non-conductive feature  14 A provided on the first element  2  (e.g., over the first conductive feature  12 A), and a second non-conductive feature  14 B provided on the second element  3  (e.g., over the second conductive feature  12 B). Furthermore, as shown in  FIG. 3F , a third non-conductive feature  14 C can be disposed about the first conductive feature  12 A. When the elements  2 ,  3  are bonded, the first and second non-conductive features  14 A,  14 B can be directly bonded along the direct bond interface  13  to define the intervening non-conductive feature  14 . As explained above, however, in some embodiments, more or fewer layers may be provided on each element  2 ,  3 . For example, as explained above, the first conductive feature  12 A, the non-conductive feature  14 , and the second conductive feature  12 B can be provided on only one of the elements. Other combinations may be suitable. 
     As shown in  FIG. 3F , the capacitive electrical pathway P C  can extend from the first conductive feature  12 A, down through the non-conductive feature  14 , to the second conductive feature  12 B. As shown in  FIGS. 3A, 3E, and 3F , the second conductive feature  12 B can comprise a pad portion  19  and a coil portion  18  extending around the pad portion  19 . The capacitance C can be tuned by selecting one or more of an area A 1  of the first conductive feature  12 A, an area A 2  of the pad portion  19  of the second conductive feature  12 B, a thickness t of the non-conductive feature  14 , and/or the insulating material for the non-conductive material  14 . The thickness t can be in a range of 0.1 microns to 2 microns. The non-conductive feature  14  can comprise any suitable insulating material, such as silicon oxide, etc. 
     As shown in  FIGS. 3B and 3F , the inductive electrical pathway P L  can be in series with the capacitive electrical pathway P C . Returning to  FIG. 3E , the second conductive feature  12 B can be patterned to define the coil portion  18  that defines a plurality of turns about the z-axis, which can be perpendicular to the direct bond interface  13 . The coil portion  18  can generate the inductance L in series with the capacitance C. As with the first and second conductive features  12 A,  12 B of  FIGS. 2A-2F , the coil portion  18  can turn about the z-axis in a clockwise or counterclockwise direction. As compared with  FIGS. 2A-2F , however, in the embodiment of  FIGS. 3A-3F , the coil portion  18  can comprise more turns than the filter  14   FIGS. 2A-2F . For example, as shown in  FIG. 3E , the coil portion  18  can loop around the pad portion  19  at least two times, at least three times, at least four times, at least five times, or at least 6 times. The number of turns of the coil portion  18  can be selected so as to tune the overall inductance L of the filter  15 . 
     Further as shown in  FIG. 3F , a fourth non-conductive feature  14 D can be provided between segments of the coil portion  18  to electrically separate the coils as the coil portion  18  winds around the pad portion  19 . The coil portion  18  can have a pitch p defined at least in part by a width w C  of the conductive coil portion  18  and a width w N  defined at least in part by the intervening fourth non-conductive portion  14 D. The width w C  of each coil of the coil portion  18  may be smaller than the width of the segments  17 A- 17 C of the conductive portions  12 A,  12 B of  FIGS. 2A-2F . For example, in various embodiments, the width w C  of the conductive portion of each coil can be in a range of 0.1 microns to 50 microns. The width w N  of the non-conductive portion  14 D can be in a range of 0.1 microns to 50 microns. The pitch p of the coil portion can be in a range of 0.2 microns to 100 microns. Beneficially, the number of turns, the pitch p, and/or the widths w C , w N  can be selected so as to tune the inductance L of the interface structure  10 . 
     As shown in  FIG. 3E , the inductive electrical pathway P L  can extend from the pad portion  19  and along the coils of the coil portion  18  disposed about the pad portion  19 . The inductive pathway P L  can exit the interface structure at the output terminal  6 B and can be transferred to other devices and/or structures of the second element  3 . Thus, as with the embodiment of  FIGS. 2A-2F , in the embodiment of  FIGS. 3A-3F , a filter  15  can be provided within and/or integrated with the interface structure  10  between two elements  2 ,  3 . 
       FIG. 3G  is a graph of gain versus frequency for the filter  15  shown and described in  FIGS. 3A-3F . The embodiment of  FIGS. 3A-3F  can beneficially serve as a band pass filter or resonator in which signals at one or a plurality of frequencies are passed or transmitted, and signals at other frequencies are attenuated. As shown by the insertion loss plot of  FIG. 3G , in this example, electrical signals at frequencies in a pass band between about 1.4 GHz and about 1.8 GHz can be passed or transmitted, while electrical signals at frequencies outside this pass band can be attenuated (e.g., blocked or reduced in amplitude). Beneficially, the performance of the filter  15  shown in  FIG. 3G  (e.g., the filter  15  of  FIGS. 3A-3F ) can provide a relatively narrow pass band that can accurately and selectively passes certain frequencies. 
       FIG. 3H  is a schematic side sectional view of a filter  15 , according to yet another embodiment. Unless otherwise noted, the components of  FIG. 3H  may be the same as or generally similar to like numbered components of  FIGS. 3A-3F . Unlike the embodiment of  FIGS. 3A-3F  (which can be modeled as a capacitor C in series with an inductor L, or an L-C circuit), in the embodiment of  FIG. 3H , the filter  15  can be modeled as an inductor in series with a capacitor in series with another inductor, or L-C-L circuit. In the embodiment of  FIGS. 3A-3F , the first conductive portion  12 A comprises a pad embedded or surrounded by the non-conductive portion  14 C. By contrast, in the embodiment of  FIG. 3H , the first conductive portion  12 A can comprise a first pad portion  19 A and a first coil portion  18 A disposed about the first pad portion  19 A by a number of turns or coils. The coil portion  18 A can comprise metallic portions separated by the third non-conductive feature  14 C. As with the embodiment of  FIGS. 3A-3F , the second conductive portion  12 B can comprise a second pad portion  19 A and a second coil portion  18 B disposed about the second pad portion  19 B by a number of turns or coils. A fourth non-conductive feature  14 D can separate adjacent sections of the second coil portion  18 B. Thus, in  FIG. 3H , the first conductive feature  12 A can comprise a first inductive pathway extending about the first coil portion  18 A (similar to the inductive pathway disposed along the second conductive portion  12 B shown in  FIGS. 3A and 3E ). A capacitive pathway P C  can extend from the first conductive portion  12 A, through the non-conductive portion  14 , to the second conductive portion  12 B. The second conductive portion  12 B can comprise a second inductive pathway extending around the second coil portion  18 B (similar to the inductive pathway disposed along the second conductive portion  12 B shown in  FIGS. 3A and 3E ). 
     Thus, the embodiment of  FIG. 3H  can serve as an inductor-capacitor-inductor (L-C-L) series circuit. As with the embodiment of  FIGS. 3A-3F , the first conductive feature  12 A, the non-conductive feature  14 , and the second conductive feature  12 B can be tuned to achieve desired filter properties, e.g., desired inductances and a desired capacitance. 
       FIG. 4A  is a schematic top plan view of a first conductive interface feature  12 A, according to various embodiments.  FIG. 4B  is a schematic top plan view of a second conductive interface feature  12 B, according to various embodiments. Unless otherwise noted, the conductive features  12 A,  12 B of  FIGS. 4A and 4B  can be generally similar to like-numbered components of  FIGS. 2A-3H . For example, as with  FIGS. 2A-2F , the first and second conductive features  12 A,  12 B can comprise a plurality of segments  17 A- 17 G that define a plurality of turns about the z-axis, which can be perpendicular to the direct bond interface  13 . In  FIGS. 4A-4B , the segments  17 A- 17 G can have a relatively large width w, as compared with the width we of the coil portion  18 A of  FIGS. 3A-3H . The larger width w of  FIGS. 4A-4B  can be tuned so as to adjust the inductance of the interface structure  10 . In various embodiments, the width w of the segments  17 A- 17 G can be in a range of 0.1 microns to 100 microns. 
     As shown in  FIGS. 4A and 4B , the one or a plurality of contacts  33  can be provided on the first and/or second conductive features  12 A,  12 B. In various embodiments, the contacts  33  can provide input and/or output electrical signals to the respective conductive features  12 A,  12 B. In embodiments such as those shown in  FIGS. 2A-2F , the contacts  33  can extend through the intervening non-conductive material  14  to provide an electrical pathway through the non-conductive material  14 . In embodiments, such as those shown in  FIGS. 3A-3H , the contacts  33  may not extend through the nonconductive material  14 , but may instead serve as input and output terminals to series L-C (or L-C-L) circuitry. 
       FIG. 5A  is a schematic top plan view of a first conductive interface feature  12 A, according to another embodiment.  FIG. 5B  is a schematic top plan view of a second conductive interface feature  12 B, according to another embodiment. Unless otherwise noted, the conductive features  12 A,  12 B of  FIGS. 5A and 5B  can be generally similar to like-numbered components of  FIGS. 2A-4B . As with the embodiment of  FIG. 3H , for example, the first conductive feature  12 A can comprise a first pad portion  19 A and a first coil portion  18 A extending about the first pad portion  19 A. The third non-conductive feature  14 C can be provided between adjacent sections or coils of the first coil portion  18 A. Similarly, the second conductive feature  12 B can comprise a second pad portion  19 B and a second coil portion  18 B extending about the second pad portion  19 B. The fourth non-conductive feature  4 D can be provided between adjacent sections or coils of the second coil portion  18 B. Thus, the first and second conductive features  12 A,  12 B, and the third and fourth non-conductive features  14 C,  14 D can represent top plan views of the features shown in the embodiment of  FIG. 3H  (e.g., an L-C-L circuit in series) in various arrangements. In other arrangements, a conductive interconnect can connect the first and second conductive features  12 A,  12 B, in embodiments that utilize a parallel L-C arrangement. Unlike the arrangement of  FIGS. 4A-4B , the width w of the coils of the coil portions  18 A,  18 B can be smaller than the corresponding widths w of the segments  17 A- 17 G of  FIGS. 4A-4B . The arrangement of  FIGS. 5A-5B  may include more turns that the arrangement of  FIGS. 4A-4B . 
       FIG. 6A  is a top plan view of a conductive feature  12  (e.g., one of the conductive features  12 A,  12 B of  FIG. 2A , which includes the conductive interconnect  16  that connects the first and second conductive features  12 A,  12 B through the nonconductive feature  14 . As explained above, the conductive features  12 , the nonconductive feature  14 , and interconnect  16  can be utilized in the band reject filter  15  described above in connection with  FIGS. 2A-2H . In other embodiments, however, the conductive features  12 , the nonconductive feature  14 , and interconnect  16  can be employed in other types of filters, such as low pass filters. For example, in some embodiments, the nonconductive feature  14  and interconnect  16  can be used in a radio frequency (RF) power amplifier output low pass filter, such as the filter shown in  FIG. 6B . Beneficially, the relatively large contact area of the solid interconnect  16  (e.g., the relatively large contact area that the interconnect  16  provides between the first and second conductive features  12 A,  12 B) shown in  FIG. 6A  can enable the filter to handle relatively high power throughput (e.g., about 0.5 W to about 1 W). In still other embodiments, the conductive features  12  and interconnect  16  of  FIG. 6A  can be utilized in an RF transceiver mixer output low pass filter. For example, the embodiment of  FIG. 6A  can be utilized in an RF down conversion device such as that shown in  FIG. 6C . In other arrangements, the embodiment of  FIG. 6A  can be utilized in an RF up conversion device such as that shown in  FIG. 6D . Still other applications for the embodiment of  FIG. 6A  may be suitable. 
       FIGS. 6E-6G  illustrate various implementations of the conductive contact(s)  33  that can be provided on the first and/or second conductive features  12 A,  12 B. As explained above, the contact(s)  33  can serve as an electrical input and/or output to the respective conductive features  12 A,  12 B. In some embodiments, the contact(s)  33  can communicate with the interconnect  16  that extends through the non-conductive feature  14 .  FIG. 6E  is a top plan view of a conductive feature  12  (which may comprise the first and/or second conductive feature  12 A,  12 B) in which the contact  33  comprises a continuous, single contact.  FIG. 6F  is a top plan view of a conductive feature  12  (which may comprise the first and/or second conductive feature  12 A,  12 B) in which the contact  33  comprises a plurality of polygonal contacts.  FIG. 6G  is a top plan view of a conductive feature  12  (which may comprise the first and/or second conductive feature  12 A,  12 B) in which the contact  33  comprises a plurality of rounded (e.g., circular or elliptical) contacts. In some embodiments, the single continuous contact  33  of  FIG. 6E  may be desirable, e.g., for high power applications. In other embodiments, the plurality of discrete contacts  33  of  FIGS. 6F-6G  may be desirable. For example, in some arrangements, if a larger contact  33  is polished, dishing may occur. To avoid or mitigate the effects of dishing, the plurality of discrete contacts  33  may be utilized. Still other sizes and shapes of the contact(s)  33  may be suitable. 
       FIG. 7A  is a schematic top view of first and second conductive features  12 A,  12 B that can be used in conjunction with the band-reject filter  15  of  FIGS. 2A-2F .  FIG. 7B  is a schematic top view of the first and second conductive features  12 A,  12 B that can be patterned to define a band pass filter  15 , similar to the band pass filter  15  described above in  FIGS. 3A-3G .  FIGS. 7A-7B  illustrate that the first and second conductive features  12 A,  12 B can be patterned to define any suitable type of filter. For example, the pattern of the conductive features  12 A,  12 B of  FIG. 7A  can be used with a band-reject filter. Similarly, the pattern of the conductive features  12 A,  12 B of  FIG. 7B  can be used with a band-pass filter. Still other patterns for the conductive features  12 A,  12 B may be suitable for defining filters and other electronic components between the elements  2 ,  3 . 
     In one embodiment, a stacked and electrically interconnected structure is disclosed. The stacked and electrically interconnected structure can comprise a first element and a second element directly bonded to the first element along a bonding interface without an intervening adhesive. The filter circuit can be integrally formed between the first and second elements along the bonding interface. 
     In another embodiment, a stacked and electrically interconnected structure is disclosed. The stacked and electrically interconnected structure can comprise a first element and a second element mounted to the first element. The stacked and electrically interconnected structure can comprise an interface structure between the first and second elements. The interface structure can mechanically and electrically connect the first and second elements. The interface structure can comprise a filter circuit integrated within the interface structure. The filter circuit can be configured to pass electrical signals at a first range of frequencies and to attenuate electrical signals at a second range of frequencies. 
     In another embodiment, a stacked and electrically interconnected structure is disclosed. The stacked and electrically interconnected structure can comprise a first element and a second element mounted to the first element. The stacked and electrically interconnected structure can comprise an interface structure between the first and second elements. The interface structure can mechanically and electrically connect the first and second elements. The interface structure can comprise an inductive electrical pathway between the first element and the second element and a capacitive electrical pathway between the first element and the second element. 
     For purposes of summarizing the disclosed embodiments and the advantages achieved over the prior art, certain objects and advantages have been described herein. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment. Thus, for example, those skilled in the art will recognize that the disclosed implementations may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught or suggested herein without necessarily achieving other objects or advantages as may be taught or suggested herein. 
     All of these embodiments are intended to be within the scope of this disclosure. These and other embodiments will become readily apparent to those skilled in the art from the following detailed description of the embodiments having reference to the attached figures, the claims not being limited to any particular embodiment(s) disclosed. Although this certain embodiments and examples have been disclosed herein, it will be understood by those skilled in the art that the disclosed implementations extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses and obvious modifications and equivalents thereof. In addition, while several variations have been shown and described in detail, other modifications will be readily apparent to those of skill in the art based upon this disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope. It should be understood that various features and aspects of the disclosed embodiments can be combined with, or substituted for, one another in order to form varying modes of the disclosed implementations. Thus, it is intended that the scope of the subject matter herein disclosed should not be limited by the particular disclosed embodiments described above, but should be determined only by a fair reading of the claims that follow.