Patent Publication Number: US-2023144660-A1

Title: Electronic fuse structure embedded in top via

Description:
BACKGROUND 
     The present invention relates in general to semiconductor fabrication methods and resulting structures. More specifically, the present invention relates to forming eFuse structures in top via interconnects. 
     An electronic fuse (eFuse) is a microscopic fuse embedded into an integrated circuit. eFuses are often used to as a one-time programmable read-only memory (ROM) or to dynamically reprogram an integrated circuit in real-time. For example, if a sub-system in an integrated circuit has failed, the integrated circuit&#39;s behavior can be instantly changed by blowing one or more eFuses, thereby changing the integrated circuit&#39;s structure. As another example, some gaming consoles have utilized eFuses to permanently record a newer version of a ROM to prevent downgrading of the firmware. 
     SUMMARY 
     Embodiments of the present invention include fabrication methods and the corresponding structures. In some embodiments, the fabrication method comprises forming one or more dummy vias on top of one or more bottom lines on a substrate. The method further comprises selectively etching a first dummy via of the one or more dummy vias to reduce a size of the first dummy via. The method further comprises depositing a dielectric layer around the one or more dummy vias. The method further comprises removing the first dummy via to create a first eFuse vacancy. The method further comprises depositing a conductive material in the first eFuse vacancy to create an eFuse. The method further comprises forming one or more top lines. One of the top lines is formed on top of the eFuse. 
     Additional embodiments of the present disclosure include a second fabrication method. The fabrication method comprises forming one or more dummy vias on top of one or more bottom lines on a substrate. The method further comprises encapsulating the one or more dummy vias in a dielectric material. The method further comprises performing a planarization process to remove a portion of the dielectric material and expose a top surface of the one or more dummy vias. The method further comprises removing a first dummy via to create a first eFuse vacancy. The method further comprises depositing a spacer material in the first eFuse vacancy. The spacer material is deposited along sidewalls of the first eFuse vacancy but does not fill the first eFuse vacancy. The method further comprises depositing a conductive material in the first eFuse vacancy to create an eFuse. The method further comprises removing the spacer material. The method further comprises forming one or more top lines. One top line of the one or more top lines is formed on top of the eFuse. 
     Further embodiments of the present disclosure include a semiconductor device. The semiconductor device comprises a plurality of bottom lines. One or more top vias are arranged on top of the plurality of bottom lines. One or more electronic fuses (eFuses) are also arranged on top of the plurality of bottom lines. Each eFuse of the one or more eFuses is a via having a smaller critical dimension that the one or more top vias. A plurality of top lines are arranged on top of the one or more top vias and the one or more eFuses. 
     The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The drawings included in the present disclosure are incorporated into, and form part of, the specification. They illustrate embodiments of the present disclosure and, along with the description, serve to explain the principles of the disclosure. The drawings are only illustrative of typical embodiments and do not limit the disclosure. 
         FIG.  1    illustrates a flowchart of an example method for forming an eFuse in a top via, in accordance with embodiments of the present disclosure. 
         FIG.  2 A  is a schematic diagram illustrating an example semiconductor component following the performance of a portion of the example method of  FIG.  1   , in accordance with embodiments of the present disclosure. 
         FIG.  2 B  is a schematic diagram illustrating the example semiconductor structure of  FIG.  2 A  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  2 C  is a schematic diagram illustrating the example semiconductor structure of  FIG.  2 B  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  3 A  is a schematic diagram illustrating the example semiconductor structure of  FIG.  2 C  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  3 B  is a schematic diagram illustrating the example semiconductor structure of  FIG.  3 A  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  3 C  is a schematic diagram illustrating the example semiconductor structure of  FIG.  3 B  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  3 D  is a schematic diagram illustrating the example semiconductor structure of  FIG.  3 C  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  3 E  is a schematic diagram illustrating the example semiconductor structure of  FIG.  3 D  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  3 F  is a schematic diagram illustrating the example semiconductor structure of  FIG.  3 E  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  3 G  is a schematic diagram illustrating the example semiconductor structure of  FIG.  3 F  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  3 H  is a schematic diagram illustrating the example semiconductor structure of  FIG.  3 G  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  3 I  is a schematic diagram illustrating the example semiconductor structure of  FIG.  3 H  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  3 J  is a schematic diagram illustrating the example semiconductor structure of  FIG.  3 I  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  3 K  is a schematic diagram illustrating the example semiconductor structure of  FIG.  3 J  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  3 L  is a schematic diagram illustrating the example semiconductor structure of  FIG.  3 K  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  3 M  is a schematic diagram illustrating the example semiconductor structure of  FIG.  3 L  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 A  is a schematic diagram illustrating the example semiconductor structure of  FIG.  2 C  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 B  is a schematic diagram illustrating the example semiconductor structure of  FIG.  4 A  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 C  is a schematic diagram illustrating the example semiconductor structure of  FIG.  4 B  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 D  is a schematic diagram illustrating the example semiconductor structure of  FIG.  4 C  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 E  is a schematic diagram illustrating the example semiconductor structure of  FIG.  4 D  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 F  is a schematic diagram illustrating the example semiconductor structure of  FIG.  4 E  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 G  is a schematic diagram illustrating the example semiconductor structure of  FIG.  4 F  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 H  is a schematic diagram illustrating the example semiconductor structure of  FIG.  4 G  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 I  is a schematic diagram illustrating the example semiconductor structure of  FIG.  4 H  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 J  is a schematic diagram illustrating the example semiconductor structure of  FIG.  4 I  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 K  is a schematic diagram illustrating the example semiconductor structure of  FIG.  4 J  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 L  is a schematic diagram illustrating the example semiconductor structure of  FIG.  4 K  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 M  is a schematic diagram illustrating the example semiconductor structure of  FIG.  4 L  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 N  is a schematic diagram illustrating the example semiconductor structure of  FIG.  4 M  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
         FIG.  4 O  is a schematic diagram illustrating the example semiconductor structure of  FIG.  4 N  following the performance of additional fabrication operations, in accordance with embodiments of the present disclosure. 
     
    
    
     While the embodiments described herein are amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the particular embodiments described are not to be taken in a limiting sense. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. 
     DETAILED DESCRIPTION 
     Embodiments of the present invention are generally directed to semiconductor fabrication methods and resulting structures, and more particularly to eFuse structures and methods of making eFuse structures in top vias. While the present disclosure is not necessarily limited to such applications, various aspects of the disclosure may be appreciated through a discussion of various examples using this context. 
     Various embodiments of the present disclosure are described herein with reference to the related drawings, where like numbers refer to the same component. Alternative embodiments can be devised without departing from the scope of the present disclosure. It is noted that various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present disclosure is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer “A” over layer “B” include situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s). 
     The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus. 
     For purposes of the description hereinafter, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figures. The terms “overlying,” “atop,” “on top,” “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements such as an interface structure can be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements. It should be noted, the term “selective to,” such as, for example, “a first element selective to a second element,” means that a first element can be etched, and the second element can act as an etch stop. 
     As used herein, the articles “a” and “an” preceding an element or component are intended to be nonrestrictive regarding the number of instances (i.e. occurrences) of the element or component. Therefore, “a” or “an” should be read to include one or at least one, and the singular word form of the element or component also includes the plural unless the number is obviously meant to be singular. 
     As used herein, the terms “invention” or “present invention” are non-limiting terms and not intended to refer to any single aspect of the particular invention but encompass all possible aspects as described in the specification and the claims. 
     The terms “about,” “substantially,” “approximately,” “slightly less than,” and variations thereof, are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” can include a range of ±8% or 5%, or 2% of a given value. 
     For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. 
     In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. 
     Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Another deposition technology is plasma enhanced chemical vapor deposition (PECVD), which is a process which uses the energy within the plasma to induce reactions at the wafer surface that would otherwise require higher temperatures associated with conventional CVD. Energetic ion bombardment during PECVD deposition can also improve the film&#39;s electrical and mechanical properties. 
     Removal/etching is any process that removes material from the wafer. Examples include etch processes (either wet or dry), chemical-mechanical planarization (CMP), and the like. One example of a removal process is ion beam etching (IBE). In general, IBE (or milling) refers to a dry plasma etch method which utilizes a remote broad beam ion/plasma source to remove substrate material by physical inert gas and/or chemical reactive gas means. Like other dry plasma etch techniques, IBE has benefits such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching (RIE). In general, RIE uses chemically reactive plasma to remove material deposited on wafers. With RIE the plasma is generated under low pressure (vacuum) by an electromagnetic field. High-energy ions from the RIE plasma attack the wafer surface and react with it to remove material. 
     Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (“RTA”). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device. 
     Semiconductor lithography is the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photo-resist. 
     To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and gradually the conductors, insulators and selectively doped regions are built up to form the final device. 
     Turning now to an overview of technologies that are more specifically relevant to aspects of the present disclosure, fuse devices are useful in complementary metal-oxide-semiconductor (CMOS) chips for redundancy implementation in memory arrays, for trimming resistors, capacitors and other discrete components in analog circuits, for permanently holding information. A typical implementation is a laser fuse, where laser energy is used to evaporate metal links, and the resulting resistance change is sensed using a latch. This device pitch is not scalable below the wavelength of the laser beam, typically 1.06 um, resulting in excessive use of chip area. This approach limits the choice of inter-level dielectrics and metal interconnects. Another implementation is a silicide fuse, where an electrical current is used to burn out the silicide line. However, silicide is not easy to burn out thoroughly, and re-growth is an issue. 
     Embodiments of the present disclosure may overcome the above issues with current eFuse technologies. Some embodiments of the present disclosure include an eFuse structure embedded in small-dimension top via interconnects. In particular, the eFuse is fabricated at a via portion between a line above (referred to herein as the top line) and a line below (referred to herein as the bottom line) the via portion, and the eFuse therefor does not take up considerable space (small dimension compatible). The eFuse may be, for example, a smaller via than the vias that are not meant to act as eFuses. In some embodiments, the eFuse may have a different shape than the normal vias. 
     As recognized by the inventors, an eFuse is the good candidate to overcome scalability challenge especially in advanced nodes. Also, top via structures are being developed to reduce the via resistance for advanced nodes. Thus, it is very important and valuable to come up with the processes which enable to have both eFuse and top via structures together at local level (minimum pitch) for advanced node devices. 
     Furthermore, because via density is considerably lower than the density at other layers in a semiconductor device, there is considerable room to embed eFuses into the via portion of the semiconductor device. Additionally, the embedded eFuse can be integrated into top via interconnects without significant increases in the number of fabrication process steps required to fabricate the resulting semiconductor device. 
     The via resistance of the eFuses can be kept low due to the eFuse having a top via structure. The properties of the eFuse are also easily modified by changing the materials and critical dimensions (e.g., thickness, cross-sectional area, etc.) of the eFuse. For example, thinner eFuses will have a higher electrical resistance. The critical dimension, and therefore properties, of the eFuse via is easily controlled by modulating wet process time and concentration of wet chemical. In some embodiments, the eFuse will have a critical dimension of approximately 5 nm-20 nm. 
     Because the eFuse properties can be controlled by modifying the critical dimension of the eFuse, any suitable conductive material can be used. In some embodiments, the eFuses may be made using, for example, W, Cu, Al, Ta, Co, Ru, or Rh. Cu may be especially good for the eFuse portion of the via because of lower melting point of Cu. 
     Additional embodiments of the present disclosure include methods of forming the top via eFuses. Broadly speaking, the method comprises patterning lines on a substrate using, for example, RIE processes. Additionally, the lines may include a dielectric layer patterned above them. The dielectric layer may be patterned so as to create dummy vias above the bottom interconnects (lines). One or more of the dummy vias may be removed to create vacancies for the vias and eFuses. One or more eFuses and one or more vias may be formed in the vacancies (e.g., trenches). Top interconnects may then be formed above the one or more vias and the one or more eFuses. 
     In some embodiments, removing the one or more dummy vias comprises exposing at least one dummy via that is to be made into an eFuse and performing an etch process to reduce the size of the exposed dummy via. A spin-on-glass (SOG) fill process and SOG CMP process may then be performed to form a dielectric layer around the dummy vias. The dummy vias that are in a location corresponding to an actual via or an eFuse may then be selectively patterned to form vacancies in the dielectric layer. The vacancies may then be filled with a conductive material, such as Cu, to create the one or more vias and the one or more eFuses. Illustrative embodiments of the present disclosure that implement this process are shown in  FIGS.  3 A- 3 M . 
     In some other embodiments, the size of the dummy vias that are to become eFuses are not etched to reduce their size. Instead, an SOG fill process and SOG CMP process are performed to form a dielectric layer around the dummy vias. The dummy vias that are in a location corresponding to an actual via or an eFuse may then be selectively patterned to form vacancies in the dielectric layer. At this stage, the vacancies for the eFuses and the vacancies for the vias may be substantially the same size. 
     An optical planarization layer (OPL) is deposited on top of the structure such that the OPL fills in the vacancies. A hardmask is then patterned on top of the OPL above the locations of the now-filled vacancies that will include the vias. An OPL etch process is then performed to remove the OPL from the eFuse vacancies. A spacer (e.g., SiN, SiO2) is then deposited on the structure such that the spacer partially, but not fully, fills the eFuse vacancies. The spacer is then etched back such that it is removed from the substantial horizontal portion (i.e., the bottom) of the eFuse vacancies, leaving spacer material just on the sidewalls of the eFuse vacancies. 
     A second OPL etchback (or ash) process is then performed to expose the via vacancies. A metal fill is then deposited (with a liner) to fill both the eFuse and via vacancies. The metal fill may be, for example, Cu, Al, Ru, W, etc. The liner may be, for example, TiN. A CMP process is then performed to planarize the structure. The SOG, SiN, and spacer materials are then removed, leaving behind one or more via structures and one or more eFuse structures. As a result of the deposition of the spacer material into the eFuse vacancies, but not the via vacancies, prior to deposition of the metal fill, the eFuse vias are substantially smaller than the regular top vias. This allows the eFuse vias to act as fuses and be tripped through application of a current to melt the metal fill. Illustrative embodiments of the present disclosure that implement this process are shown in  FIGS.  4 A- 4 O . 
     Turning now to the figures,  FIG.  1    illustrates a flowchart of an example method  100  for forming a semiconductor device having eFuses embedded in top vias, in accordance with embodiments of the present disclosure.  FIGS.  2 A- 2 C  illustrate the semiconductor device during performance of operation  102 .  FIGS.  3 A- 3 M  illustrate the semiconductor device at various intermediate stages in the fabrication process, in accordance with a first embodiment of the present disclosure.  FIGS.  4 A- 4 O  illustrate the semiconductor device at various intermediate stages in the fabrication process, in accordance with a second embodiment of the present disclosure. 
     Referring first to  FIG.  1   , the method  100  may be performed by, for example, processing logic that comprises hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processor), firmware, or any combination thereof. For example, the method  100  may be performed by computer systems of a semiconductor fabrication plant controlling fabrication equipment. The method  100  begins at operation  102 , wherein an intermediate structure is formed. 
     The intermediate structure may comprise bottom interconnects (e.g., lines) with dummy vias arranged on top of the lines. The dummy vias may be made of a sacrificial material that will be replaced in subsequent processing steps. For example, the dummy vias may be made of a dielectric, such as SiN. The bottom lines and dummy vias can be formed using either a damascene flow process or a subtractive flow process in different combinations and orders within the context of two main integration schemes for forming interconnect structures. A damascene flow refers to the processes of forming interconnect structures by depositing an oxide layer, forming a trench into the oxide layer, and then depositing metal into the trench. Alternatively, a subtractive flow refers to processes of forming interconnect structures by depositing metal, and then etching the metal to form the interconnect structures. 
     In some embodiments, the performance of operation  102  comprises multiple sub-operations. In a first sub-operation, a material stack is formed. An example material stack for a semiconductor device  200  is shown in  FIG.  2 A . As shown in  FIG.  2 A , the material stack comprises a substrate  202 , which may be any suitable substrate (e.g., a dielectric material). A low-k etch stop layer  204  may be deposited on top of the substrate  202 . The etch stop layer  204  may be, for example, a thin layer of silicon carbon nitride (SiCN). A barrier metal  206  may be deposited on top of the low-k etch stop layer  204 . The barrier metal  206  may be a diffusion barrier material such as, for example, TaN or TiN. 
     A layer of conductive metal layer  208  may be deposited on top of the barrier metal  206 . The conductive metal layer  208  will subsequently be patterned into bottom lines. As such, any suitable line material may be used, such as, for example, Ru. The conductive metal layer  208  may be deposited using any suitable process. For example, the layer of Ru may be deposited using PVD. A sacrificial layer  210  is then deposited on top of the metal layer  208 . The sacrificial layer  210  may be used to create dummy vias and dummy eFuses, which are structures that will be replaced by the actual vias and eFuses. In some embodiments, the sacrificial layer  210  may be, for example, SiN. A hardmask  212  is then deposited on top of the sacrificial layer  210 . The hardmask  212  is deposited in locations where the top vias and eFuses will be formed. 
     In a second sub-operation of operation  102 , the sacrificial layer and the metal layers are patterned and etched to create a plurality of lines and a plurality of dummy vias on top of the lines.  FIG.  2 B  shows the semiconductor device  200  after formation of the dummy vias. As shown in  FIG.  2 B , the sacrificial layer  210  and the metal layer  208  have been selectively etched (using the hardmask  212 ) to create a plurality of trenches  214  separating a plurality of via stacks. The semiconductor device  200  may be etched using, for example, an RIE process using the barrier layer  206  as an etch stop. 
     In a third sub-operation of operation  102 , a SOG process is performed to fill in the trenches with a dielectric material and support the via stacks. A planarization process may then be performed to planarize the semiconductor device such that the top surface of the dummy vias is substantially coplanar with the dielectric fill. The performance of these suboperations may complete operation  102 . 
       FIG.  2 C  shows the semiconductor device  200  after performance of the SOG process and CMP process and, therefore, completion of operation  102 . As shown in  FIG.  2 C , a dielectric layer  216  has been deposited on the semiconductor device  200  to fill in the trenches  214  (shown in  FIG.  2 B ). The dielectric layer  216  completely surrounds the via stacks. Additionally, a CMP process has been performed to planarize the top of the semiconductor device and remove any extraneous dielectric  216  that was deposited on top of the via stacks. As a result of the CMP process, the top surface of the dummy vias  210  is substantially coplanar with the top surface of the dielectric  216 . 
     Returning to  FIG.  1   , one or more dummy vias are removed to create vacancies for via and eFuse creation at operation  104 . The vacancies may be formed in locations where vias and eFuses will be created in subsequent processing steps. The performance of operation  104  comprises multiple sub-operations. The specific sub-operations may depend on the specific embodiment being performed. The sub-operations that are performed in accordance with two embodiments of the present disclosure will be discussed below with reference to  FIGS.  3 A- 3 M  (a first embodiments) and  FIGS.  4 A- 4 O  (a second embodiment). 
     At operation  106 , one or more vias and one or more eFuses are formed in the via and eFuse vacancies creation at operation  104 . The performance of operation  106  comprises multiple sub-operations. The specific sub-operations may depend on the specific embodiment being performed. The sub-operations that are performed in accordance with two embodiments of the present disclosure will be discussed below with reference to  FIGS.  3 A- 3 M  (a first embodiments) and  FIGS.  4 A- 4 O  (a second embodiment). 
     At operation  108 , the top interconnects are formed above the one or more vias and the one or more eFuses. The performance of operation  108  comprises multiple sub-operations. The specific sub-operations may depend on the specific embodiment being performed. The sub-operations that are performed in accordance with two embodiments of the present disclosure will be discussed below with reference to  FIGS.  3 A- 3 M  (a first embodiments) and  FIGS.  4 A- 4 O  (a second embodiment). 
     Reference will now be made to  FIGS.  3 A- 3 M , in which operations  104 - 108  are performed to form a semiconductor device in accordance with a first embodiment of the present disclosure. Referring first to  FIG.  3 A , shown is the semiconductor device  300  (e.g., semiconductor device  200  of  FIG.  2 C ) after additional fabrication processing steps have been performed. In particular,  FIG.  3 A  shows the semiconductor device  300  after a second hardmask  318  has been formed and patterned on top of a portion of the semiconductor device  300 . In particular, the second hardmask  318  is formed over all of the dummy vias  210  that will be converted into regular vias in subsequent operations. 
     After forming the second hardmask  318 , the exposed portion of the dielectric layer  216  is removed, as shown in  FIG.  3 B . The exposed dielectric layer  216  may be removed using, for example, a combination of a UV treatment, such as Advanced Surface Treatment and organic film Removal (ASTR), and dilute hydrofluoric acid etching, with the barrier layer  206  acting as an etch stop. As a result of the etching, large trenches  320  may be formed where the dielectric layer  216  has been removed. 
     An additional wet etching process may then be performed to trim the exposed dummy vias  210 , as shown in  FIG.  3 C . For example, if the dummy vias  210  are made out of SiN, a dHF wet etch may be performed to thin the exposed dummy vias  210 . The etching process used, as well as the amount of time that the wet etch is allowed to react with the dummy vias  210 , may be controlled in order to control the thickness of the resulting dummy vias  210 . As shown in  FIG.  3 C , the wet etching may also change the shape of the exposed dummy vias  210  such that the thickness of the dummy vias  210  is larger at the bottom (i.e., where the dummy vias  210  touch the metal lines  208 ) than at the top. 
     As shown in  FIG.  3 D , a hardmask and dielectric etch process may be used to remove the second hardmask  318 . As a result of the removal of the second hardmask  318 , the dielectric layer  216  may be reduced as well. However, a subsequent SOG fill and SOG CMP process may then be performed to again fill the gaps  320  in the dielectric layer  216 , as shown in  FIG.  3 E . Additionally, the CMP process may be performed in order to planarize the dielectric layer  216  such that the top surface of the dielectric layer  216  is substantially coplanar with the top surface of the dummy vias  210 . 
     Via patterning may then be performed to remove one or more dummy vias  210  (selective to the dielectric layer  216 ) to create a plurality of vacancies in the dielectric layer  216 . This is shown in  FIG.  3 F . The vacancies may be created in areas where vias and eFuses will be created in subsequent processing operations. In particular, the vacancies may include one or more via vacancies  322 A and one or more eFuse vacancies  322 B in the dielectric layer  216 . The via vacancies  322 A and eFuse vacancies  322 B are collectively and individually referred to herein as vacancies  322 . 
     A metal fill  326  is then deposited into the vacancies  322 . This is shown in  FIG.  3 G . In particular, deposition of the metal fill  326  may comprise first depositing a liner  324 . The liner  324  may be, for example, an adhesive layer that allows the metal fill  326  to adhere to the semiconductor device  300 . In some embodiments, the liner  324  may be TiN, and the metal fill  326  may be, for example, Cu, Al, Ru, or W. 
     The metal fill  326  may be planarized using, for example, a CMP process. This is shown in  FIG.  3 H . In particular, the CMP process may remove the excess metal fill  326  that is not deposited in the vacancies  322 . For example, as shown in  FIG.  3 H , the metal fill  326  may be planarized to a depth that removes all metal fill  326  and the liner  324  from the top of the dielectric layer  216  and the dummy vias  210 , thereby electrically isolating the resulting top via  330  and the resulting eFuse  328 . 
     As shown in  FIG.  3 I , the dielectric layer  216  and the remaining dummy vias  210  may be removed. As previously discussed, removal of the dielectric layer  216  and the dummy vias  210  may be performed using, for example, an ASTR and dHF etch process. 
     As shown in  FIG.  3 J , the barrier metal layer  206  may be selectively etched. In particular, an etching process may be performed to remove the barrier metal layer  206  from areas between the bottom lines  208 . However, the barrier metal layer  206  may still exist underneath the bottom lines  208 . 
     As shown in  FIG.  3 K , after removing the barrier metal layer  206  from between the lines  208 , a layer of SiCN  332  is deposited on top of the bottom lines  208 , the via  330 , and the eFuse  328 . A low-k dielectric  334  can then be deposited on top of the SiCN layer  332  using, for example, flowable chemical vapor deposition (fCVD). The low-k dielectric may be, for example, fluorine-doped silicon dioxide, organosilicate glass dielectrics (e.g., carbon-doped oxides), porous silicon dioxide, or any other suitable low-k dielectric material. 
     As shown in  FIG.  3 L , the semiconductor device  300  may be planarized to expose the metal fill  326  of both the via  330  and the eFuse  328 . A cerium oxide based slurry may be used in the CMP process to remove the top of the low-k dielectric  334 . 
     As shown in  FIG.  3 M , top lines can be formed on top of both the via  330  and the eFuse  328 . The top lines may be formed using one or more known fabrication processes. The top lines may be made of a liner  336  and a metal fill  338 . The liner may be, for example, TiN, and the metal fill  338  may be made out of any suitable conductive metal. For example, the metal fill  338  may be Cu, Al, Ru, W, etc. In some embodiments, the metal fill  338  may be made of the same material as the bottom lines  208  and/or the metal fill  326  of the via  330  and eFuse  328 . However, in some embodiments, the metal fill  326 , the metal fill  338 , and the bottom lines  208  may be made of different conductive materials. 
     Reference will now be made to  FIGS.  4 A- 4 O , in which operations  104 - 108  are performed to form a semiconductor device  400  in accordance with a second embodiment of the present disclosure. Referring first to  FIG.  4 A , shown is the semiconductor device  400  (e.g., the semiconductor device  200  of  FIG.  2 C ) after additional fabrication processing steps have been performed. In particular,  FIG.  4 A  shows the semiconductor device  400  after one or more dummy vias  210  have been removed, thereby creating vacancies  418 . The vacancies  418  may be in the locations where a via and an eFuse are going to be formed. 
     As shown in  FIG.  4 B , an OPL layer  420  is deposited on top of the semiconductor device  400 . The OPL layer  420  may be deposited until it completely fills both vacancies  418 . In addition, the OPL layer  420  may be formed on top of the other dummy vias  210  and the dielectric layer  216 . This may be done to ensure that sufficient OPL has been deposited to completely fill both vacancies. 
     As shown in  FIG.  4 C , a hardmask  422  is deposited and patterned above a portion of the OPL layer  420 . In particular, the hardmask  422  is deposited over the now-filled vacancy  418  that will subsequently be formed into a regular top via. 
     As shown in  FIG.  4 D , an OPL etch process is performed to remove the portion of the OPL layer  420  that was not under the hardmask  422 . The OPL etch process may be selective to the dielectric material  216  and the metal line  208  such that only the exposed portion of the OPL layer  420  is removed. As a result of the OPL etch, an eFuse vacancy  424  is formed. 
     As shown in  FIG.  4 E , an OPL thinning process is performed. This reduces the thickness of the excess OPL layer  420  from the via vacancy. 
     As shown in  FIG.  4 F , after thinning the OPL layer  420 , a spacer layer  426  is deposited on top of the semiconductor device  400 . The spacer layer  426  may be, for example, a layer of SiN or SiO2. 
     As shown in  FIG.  4 G , a spacer etchback process is performed to remove most of the spacer layer  426 . In particular, the spacer layer  426  is removed from all of the semiconductor device  400  except that the spacer layer  426  still exists along the sidewalls of the via vacancy  424 . However, the spacer layer  426  has been removed from the bottom of the via vacancy  424 . 
     As shown in  FIG.  4 H , an OPL ash process is performed to remove the remaining part of the OPL layer  420  (shown in  FIG.  4 G ). This creates a second vacancy  428 , also referred to herein as a via vacancy  428 , in the semiconductor device  400 . 
     A metal fill  432  is then deposited into the vacancies  424 ,  428 . This is shown in  FIG.  4 I . In particular, deposition of the metal fill  432  may comprise first depositing a liner  430  into the vacancies  424 ,  428 . The liner  430  may be, for example, an adhesive layer that allows the metal fill  432  to adhere to the semiconductor device  400 . In some embodiments, the liner  430  may be TiN, and the metal fill  432  may be, for example, Cu, Al, Ru, or W. 
     The metal fill  432  may be planarized using, for example, a CMP process. This is shown in  FIG.  4 J . In particular, the CMP process may remove the excess metal fill  432  that is not deposited in the vacancies  424 ,  428 . For example, as shown in  FIG.  4 J , the metal fill  432  may be planarized to a depth that removes all metal fill  432  and the liner  430  from the top of the dielectric layer  216  and the dummy vias  210 , thereby electrically isolating the resulting top via  436  and the resulting eFuse  434 . 
     As shown in  FIG.  4 K , the dielectric layer  216  and the remaining dummy vias  210  may be removed. As previously discussed, removal of the dielectric layer  216  and the dummy vias  210  may be performed using, for example, an ASTR and dHF etch process. 
     As shown in  FIG.  4 L , the barrier metal layer  206  may be selectively etched. In particular, an etching process may be performed to remove the barrier metal layer  206  from areas between the bottom lines  208 . However, the barrier metal layer  206  may still exist underneath the bottom lines  208 . 
     As shown in  FIG.  4 M , after removing the barrier metal layer  206  from between the lines  208 , a layer of SiCN  438  is deposited on top of the bottom lines  208 , the via  436 , and the eFuse  434 . A low-k dielectric  440  can then be deposited on top of the SiCN layer  438  using, for example, flowable chemical vapor deposition (fCVD). The low-k dielectric may be, for example, fluorine-doped silicon dioxide, organosilicate glass dielectrics (e.g., carbon-doped oxides), porous silicon dioxide, or any other suitable low-k dielectric material. 
     As shown in  FIG.  4 N , the semiconductor device  400  may be planarized to expose the metal fill  432  of both the via  436  and the eFuse  434 . A cerium oxide based slurry may be used in the CMP process to remove the top of the low-k dielectric  440 . 
     As shown in  FIG.  4 O , top lines can be formed on top of both the via  436  and the eFuse  434 . The top lines may be formed using one or more known fabrication processes. The top lines may be made of a liner  442  and a metal fill  444 . The liner  442  may be, for example, TiN, and the metal fill  444  may be made out of any suitable conductive metal. For example, the metal fill  444  may be Cu, Al, Ru, W, etc. In some embodiments, the metal fill  444  may be made of the same material as the bottom lines  208  and/or the metal fill  432  of the via  436  and eFuse  434 . However, in some embodiments, the metal fill  444 , the metal fill  432 , and the bottom lines  208  may be made of different conductive materials. 
     It is to be understood that the aforementioned advantages are example advantages and should not be construed as limiting. Embodiments of the present disclosure can contain all, some, or none of the aforementioned advantages while remaining within the spirit and scope of the present disclosure. 
     Detailed embodiments of the structures of the present invention are described herein. However, it is to be understood that the embodiments described herein are merely illustrative of the structures that can be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the invention is intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features can be exaggerated to show details of particular components. Therefore, specific structural and functional details described herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present description 
     It should also be understood that material compounds will be described in terms of listed elements, e.g., SiN, SiCN, SiCO, or SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes Si x Ge (1-x)  where x is less than or equal to 1, and the like. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys. 
     It should be noted that not all masking, patterning, and lithography processes are shown because a person of ordinary skill in the art would recognize where masking and patterning processes are utilized to form the identified layers and openings, and to perform the identified selective etching processes, as described herein. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.