Patent Publication Number: US-11031962-B2

Title: Carrier aggregated signal transmission and reception

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 16/203,943, filed Nov. 29, 2018 in the U.S. Patent and Trademark Office, which claims the benefit under 35 U.S.C. § 119 of Korean Patent Application Nos. 10-2017-0166194 and 10-2018-0090411, respectively filed on Dec. 5, 2017 and Aug. 2, 2018, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference in their entireties. 
    
    
     TECHNICAL FIELD 
     The inventive concept relates generally to a radio-frequency integrated chip (RFIC) and a wireless communication device, and more particularly, to an RFIC configured to transceive signals using carrier aggregation and a wireless communication device including the RFIC. 
     DISCUSSION OF RELATED ART 
     Carrier aggregation (CA) refers to the aggregation of a plurality of carrier waves (“carriers”) on a single transmission path for the transmission of signals between wireless communication devices. A frequency range of signal energy transmitted via one modulated carrier may be referred to as a frequency channel. Using CA, a wireless device may transmit/receive a larger amount of data over a given wireless channel encompassing multiple frequency channels, by concurrently processing multiple carriers that may each carry respective data. 
     With CA, frequency channels over which data is transmitted may be variously arranged. A CA-capable transmitter, receiver, or transceiver of a wireless communication device may be comprised of multiple single-carrier receivers, transmitters or transceivers (herein called “carrier transmitters”, “carrier receivers”, or “carrier transceivers”) which are designed to support various arrangements of the frequency channels. 
     In addition, a phase-locked loop (PLL) configured to support a fixed frequency may be utilized so that a plurality of carrier transmitters and/or carrier receivers may process information signals. With many current designs, since a plurality of carrier transmitters and carrier receivers use individual PLLs, a large area for the PLLs is occupied in a chip, and power consumption of the PLLs is high. 
     SUMMARY 
     The inventive concept provides a radio-frequency integrated chip (RFIC) configured to support frequency signals for each of a plurality of carrier transmitters and a plurality of carrier receivers using a single phase-locked loop (PLL), and a wireless communication device including the RFIC. 
     According to an aspect of the inventive concept, there is provided an RFIC configured to receive a receiving signal composed of at least first and second carrier signals. The RFIC may include first and second carrier receivers and a PLL. The first carrier receiver is configured to receive a first portion of the receiving signal and generate therefrom a first digital carrier signal corresponding to the first carrier signal. The first carrier receiver includes a first analog mixer configured to translate frequencies of the first carrier signal in an analog domain and a first digital mixer configured to further translate frequencies of the first carrier signal in a digital domain and output the first digital carrier signal. The carrier receiver is configured to receive a second portion of the receiving signal and generate therefrom a second digital carrier signal corresponding to the second carrier signal. The second carrier receiver includes a second analog mixer configured to translate frequencies of the second carrier signal in an analog domain and a second digital mixer configured to further translate frequencies of the second carrier signal in the digital domain and output the second digital carrier signal. The PLL is configured to output a first frequency signal having a first frequency to each of the first and second carrier receivers. The first analog mixer translates the frequencies of the first carrier signal using a second frequency signal generated by dividing the first frequency signal, and the second analog mixer translates the frequencies of the second carrier signal using a third frequency signal generated by dividing the first frequency signal. 
     According to another aspect of the inventive concept, there is provided an RFIC configured to transmit a carrier aggregated signal. The RFIC includes first and second carrier transmitters and a phase-locked loop (PLL). The first carrier transmitter is configured to receive a first digital carrier signal and generate therefrom a first transmitting signal. The first carrier transmitter includes a first digital mixer configured to translate frequencies of the first digital carrier signal in a digital domain, and a first analog mixer configured to translate frequencies of a first analog carrier signal, derived from the first digital carrier signal, in an analog domain. The second carrier transmitter is configured to receive a second digital carrier signal and generate therefrom a second transmitting signal. The second carrier transmitter includes a second digital mixer configured to translate frequencies of the second digital carrier signal in the digital domain, and a second analog mixer configured to translate frequencies of a second analog carrier signal, derived from the second digital carrier signal, in the analog domain. The PLL is configured to output a first frequency signal having a first frequency to the first carrier transmitter and the second carrier transmitter. The first analog mixer up-converts the frequencies of the first analog carrier signal using a second frequency signal generated by dividing the first frequency signal, and the second analog mixer up-converts the frequencies of the second analog carrier signal using a third frequency signal generated by dividing the first frequency signal. 
     According to another aspect of the inventive concept, there is provided a wireless communication device configured to receive a receive signal composed of at least first and second carrier signals. The wireless communication device may include an RFIC including a first carrier receiver configured to receive a first portion of the receive signal and generate therefrom a first digital carrier signal corresponding to the first carrier signal, a second carrier receiver configured to receive a second portion of the receive signal and generate therefrom a second digital carrier signal, a PLL configured to output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver, and a modulator-demodulator (MODEM) configured to down-convert frequencies of the first and second digital carrier signals in a digital domain and then demodulate the down-converted first and second digital carrier signals. The first carrier receiver includes a first analog mixer configured to down-convert frequencies of the receive signal using a second frequency signal generated based on the first frequency signal. The second carrier receiver includes a second analog mixer configured to down-convert the frequencies of the first receive signal using a third frequency signal generated based on the first frequency signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which like reference characters indicate like elements or operations, wherein: 
         FIG. 1  is a block diagram of a wireless communication device according to an example embodiment; 
         FIG. 2  is a block diagram of a radio-frequency integrated chip (RFIC) according to an example embodiment; 
         FIG. 3  is a block diagram of an RFIC according to an example embodiment; 
         FIG. 4  is a flowchart of a method of operating a carrier receiver, according to an example embodiment; 
         FIGS. 5A, 5B and 5C  are graphs illustrating a method of operating an analog receiving circuit, according to example embodiments; 
         FIG. 6  is a block diagram of an RFIC according to an example embodiment; 
         FIG. 7  is a block diagram of an RFIC according to an example embodiment; 
         FIG. 8  is a block diagram of an RFIC according to an example embodiment; 
         FIG. 9  is a block diagram of a wireless communication device according to an example embodiment; 
         FIG. 10  is a block diagram of an RFIC according to an example embodiment; 
         FIG. 11  is a block diagram of an RFIC according to an example embodiment; 
         FIG. 12  is a block diagram of a wireless communication device according to an example embodiment; 
         FIG. 13  is a block diagram of a wireless communication device according to an example embodiment; 
         FIG. 14  is a block diagram of a wireless communication device according to an example embodiment; 
         FIG. 15  is a block diagram of a wireless communication device according to an example embodiment; 
         FIG. 16  is a block diagram of an RFIC according to an example embodiment; 
         FIG. 17  is a block diagram of an RFIC according to an example embodiment; 
         FIG. 18  is a block diagram of an RFIC according to an example embodiment; 
         FIG. 19  is a diagram of a wireless communication system including various wireless communication equipment according to an example embodiment. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     In the following description, the term “radio frequency integrated chip” (RFIC) refers to a chip (a small piece of semiconductor material) within which a plurality of circuit components are integrated, where at least some of the circuit components are operable at RF frequencies. 
     Herein, a “carrier aggregated signal” refers to a multi-carrier signal. The term “carrier receiver” refers to receiver circuitry for receiving and processing signal energy associated with at least a single carrier within a carrier aggregated receive signal. A “carrier transmitter” refers to transmitter circuitry for processing and outputting, in a transmit path, signal energy associated with at least a single carrier of a carrier aggregated transmit signal. Processing in the transmit and receive paths may include amplifying, filtering, frequency translating, and D/A or A/D conversion. 
     Herein, a “mixed” signal may refer to a signal output by a mixer, which is frequency translated relative to an input signal to the mixer. 
     Herein, for brevity, any signal, voltage or other variable may be referred to interchangeably just by its previously introduced legend. For example, a “first analog receiving signal RS_A 1 ” may be referred to as just “RS_ 1 ” or “signal RS_ 1 ”; a “first mixed receiving signal RS_M 1 ” may be referred to as just “RS_M 1 ” or “signal RS_M 1 ”; etc. Similarly, a component partly identified with a legend and having a basic function, such as a filter or a mixer, but differentiated from other similar functioning components with augmented terms such as “first”, “second”, “receiving”, “transmitting”, etc., may, for brevity, be later called just its functional name+its legend. For instance, a “first analog receiving filter  114 ” may subsequently be called “filter  114 ”; a “first digital mixer  117 ” may be later called “mixer  117 ”; etc. 
     Herein, the terms “receiving signal” and “receive signal” will be used interchangeably. “Transmitting signal” and “transmit signal” will be used interchangeably. 
       FIG. 1  is a block diagram of a wireless communication device,  1 , according to an example embodiment. Wireless communication device  1  may be any type of communication device for receiving and/or transmitting a carrier aggregated signal. Some examples of wireless communication device  1  include a base station (BS), an access point (AP), user equipment (UE) and a client device. A UE is mobile or fixed wireless communication equipment and may be referred to as terminal equipment, a mobile station (MS), a mobile terminal (MT), a user terminal (UT), a subscriber station (SS), a wireless device, or a handheld device. A BS may be a fixed station configured to communicate with UEs and/or another BS. A BS may be referred to as a Node B, an evolved-Node B (eNB), or a base transceiver system (BTS). An AP may form a communication connection with one or more client devices based on a wireless fidelity (WiFi) communication protocol. 
     The wireless communication device  1  may receive a receiving signal RS (interchangeably, a “receive signal”) from another wireless communication device of a wireless communication system using an antenna Ant. Examples of the wireless communication system include but are not limited to a long-term evolution (LTE) system, an LTE-advance (LTE-A) system, a code-division multiple access (CDMA) system, a global system for mobile communications (GSM) system, a wireless local area network (WLAN) system, a WiFi system, a Bluetooth system, a Bluetooth low-energy (BLE) system, a ZigBee system, a near-field communication (NFC) system, a magnetic secure transmission system, a radio-frequency (RF) system, and a body area network (BAN) system. 
     A plurality of wireless communication devices included in the wireless communication system may be connected to each other using a wireless communication network. Wireless communication networks may share available network resources and support the communication of a plurality of users. For example, in the wireless communication networks, information may be transmitted using various modulation and spectrum allocation methods, such as code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), orthogonal frequency division multiple access (OFDMA), and single-carrier frequency division multiple access (SC-FDMA). 
     Herein, a “carrier signal” is a modulated carrier, which is a band-limited signal containing spectral energy over a band encompassing the carrier frequency. Carrier aggregation is a technique by which a plurality of carrier signals are merged within a wireless communication signal to thereby form a “carrier aggregated signal”. Each carrier signal may occupy a respective bandwidth within a wider frequency range of the carrier aggregated signal. Since each carrier signal carries information, the use of carrier aggregation may allow for an increase in the data transmission rate and/or other performance benefits as compared to a single carrier system. 
     As shown in  FIG. 1 , the wireless communication device  1  includes an RFIC  10  and a MODEM  20 , where RFIC  10  may include a plurality of carrier receivers (e.g.,  110 ,  120 , and  130 ) and a phase-locked loop (PLL)  200 . While only receiver circuitry is shown in  FIG. 1 , RFIC  10  may further include transmitter circuitry for generating a carrier aggregated transmit signal, described later. In other embodiments, device  1  may use conventional transmitter circuitry, or is just a receiving device and omits transmitter circuitry. On receive, RFIC  10  receives the carrier aggregated receive signal RS, which includes n carrier signals CS 1  to CSn, where n is two or more and may be dependent on the particular application or protocol. The PLL  200  may output a “first frequency” signal FS 1  to each of the carrier receivers  110 ,  120 , and  130 , where the first frequency signal FS 1  is a signal with a sinusoidal, square wave or other shaped waveform oscillating at a first, fixed frequency. The PLL  200  may be a feedback circuit configured to maintain a frequency of an output signal constant. The PLL  200  may fix an adjustment point so as to avoid phase jitter and output a stable first frequency signal FS 1  to each of the carrier receivers  110 ,  120 , and  130 . 
     Each of the carrier receivers  110 ,  120 , and  130  may receive a portion of the receive signal RS from the antenna Ant through a signal divider  5  which divides the receive signal RS from the antenna into a plurality of signal portions, each being an attenuated version of the receive signal RS. (Hereafter, for convenience of description, each of these portions of the receive signal RS received by a respective carrier receiver may be referred to as just the receive signal RS.) Each of the carrier receivers  110 ,  120  and  130  may frequency translate (e.g. down-convert) the receive signal RS. In other embodiments, a plurality of antennas are provided and the signal divider  5  is omitted, where each antenna receives the receive signal RS and provides the same to a respective carrier receiver  110 ,  120  or  130 . Each of the carrier receivers  110 ,  120  and  130  may frequency translate the receive signal RS by a different respective frequency offset (amount). Following frequency translation, carrier signals CS 1  to CSn from the receive signal RS may be sampled by using one or more clock signals generated based on the first frequency signal FS 1 . Each clock signal may be a sinusoidal, square wave or other shaped waveform. 
     In an example, the first carrier receiver  110  may sample a first carrier signal CS 1  within the receiving signal RS and generate a first digital carrier signal CS 1 - d  containing baseband information of the first carrier signal CS 1 . To this end, the first carrier receiver  110  may use a second, fixed frequency signal, generated based on the first frequency signal FS 1 , to frequency translate the receiving signal RS by a first offset prior to sampling and digitally mixing the same. In other words, the second frequency signal may serve as a local oscillator (LO) signal for the frequency translation in the analog domain. The carrier signal CS 1  may also be sampled using the second frequency signal as a clock signal for sampling. 
     The second carrier receiver  120  may sample a second carrier signal CS 2  from the receiving signal RS and generate a second digital carrier signal CS 2 - d  containing baseband information of the second carrier signal CS 2 . Here, the second carrier receiver may use a third frequency signal for frequency translation by a second offset that differs from the first offset. In other words, the third frequency signal may serve as a local oscillator (LO) signal for the frequency translation. The third frequency signal is also generated based on the first frequency signal FS 1 . The carrier signal CS 2  may also be sampled using the third frequency signal as a clock signal for sampling. 
     According to the inventive concept, each of the carrier receivers  110 ,  120 , and  130  may generate different respective fixed frequency signals based on the first frequency signal FS 1  received from one PLL  200 , and also sample carrier signals CS 1  to CSn from the receiving signal RS using the generated fixed frequency signals. That is, the carrier receivers  110 ,  120 , and  130  may share one PLL  200  with each other. Thus, the number of PLLs  200  may be reduced and an area and power consumption otherwise consumed for multiple PLLs  200  may be reduced. 
       FIG. 2  is a block diagram of an RFIC  10  according to an example embodiment. The RFIC  10  may include a first carrier receiver  110 , a second carrier receiver  120 , and a PLL  200 . The first carrier receiver  110  may include a first analog receiving circuit  111 , a first ADC  115 , a first digital receiving circuit  116 , and a first frequency divider  118 . The second carrier receiver  120  may include a second analog receiving circuit  121 , a second ADC  125 , a second digital receiving circuit  126 , and a second frequency divider  128 . Operations of the second carrier receiver  120  may be the same as or similar to operations of the first carrier receiver  110  and thus redundant descriptions thereof will be omitted. 
     The PLL  200  may generate a first frequency signal FS 1  having a first frequency and output the first frequency signal FS 1  to the first frequency divider  118  and the second frequency divider  128 . The first frequency divider  118  may divide, by a first divisor, the first frequency of the first frequency signal FS 1  and thereby generate a second frequency signal FS 2  having a second, fixed frequency. The second frequency divider  128  may divide, by a second divisor, the first frequency of the first frequency signal FS 1  and thereby generate a third frequency signal FS 3  having a third, fixed frequency. In an embodiment, the first divisor differs from the second divisor, such that the second and third frequencies are different. In addition, the second frequency may correspond to a first channel corresponding to a first carrier signal CS 1 , and the third frequency may correspond to a second channel corresponding to a second carrier signal CS 2 . For instance, the second and third frequencies may be set so that the first and second carrier signals are down-converted, in the respective carrier receivers, to the same lower frequency band after respective analog mixing operations. In an example, at least one of the first and second divisors of the frequency dividers  118 ,  128  is an integer of two or more. In another example, at least one of the first and second divisors is a non-integer greater than one. 
     The first analog receiving circuit  111  may receive the receiving signal RS, process the receiving signal RS using the second frequency signal FS 2 , and thereby generate a first analog receiving signal RS_A 1 . Each of the receiving signal RS and the first analog receiving signal RS_A 1  may be an analog signal having a continuous magnitude. In addition, the processing of the receiving signal RS may include mixing, filtering, and amplifying the receiving signal RS in an analog domain as will be described below with reference to  FIG. 3 . 
     The first ADC  115  may receive a first analog receiving signal RS_A 1  and generate, by sampling and quantizing signal RS_A 1 , a first digital receiving signal RS_D 1 . In an embodiment, ADC  115  may sample signal RS_A 1  using signal FS 2  as a clock signal provided along a path  141 . In this case, signal FS 2  is used both as an LO signal for down-conversion within the first analog receiving circuit  111 , and as a clock signal for sampling. In other embodiments, ADC  115  may sample signal RS_A 1  using signal FS 1  as a clock signal, or by using another clock signal. 
     The first digital receiving circuit  116  may receive the first digital receiving signal RS_D 1 , process the first digital receiving signal RS_D 1 , and thereby generate the first digital carrier signal CS 1 - d . The first digital carrier signal CS 1 - d  may be a sequence of bits representing information carried by the carrier signal CS 1 , such as a representation of a modulation envelope by which the carrier of carrier signal CS 1  was modulated. 
     In a similar manner, the second carrier receiver  120  may process signal RS to derive the second digital carrier signal CS 2 - d . In this process, ADC  125  may sample a second analog receive signal RS_A 2  using signal FS 3  (provided via path  142 ) as a clock signal. This generates a second digital receive signal RS_D 2  which is converted by digital receiving circuit  126  to the second digital carrier signal CS 2 - d.    
     According to the inventive concept, the first carrier receiver  110  and the second carrier receiver  120  may receive the first frequency signal FS 1  from the common PLL  200  and process the first frequency signal FS 1  in the analog domain using a frequency signal obtained by dividing the first frequency of the first frequency signal FS 1  so that an area and power consumption otherwise allocated for multiple PLLs  200  may be reduced. 
       FIG. 2  illustrates an embodiment in which two carrier receivers  110  and  120  share one PLL  200 . In other embodiments, three or more carrier receivers share one PLL  200  with each other. 
       FIG. 3  is a block diagram of the RFIC  10  of  FIG. 2 , further illustrating example configurations for the analog and digital receiving circuits according to an example embodiment. Redundant descriptions with respect to  FIG. 2  will be omitted. 
     RFIC  10  of  FIG. 3  may include first and second carrier receivers  110 ,  120  and PLL  200 . The first carrier receiver  110  may include first analog receiving circuit  111 , first ADC  115 , first digital receiving circuit  116 , and first frequency divider  118 . The second carrier receiver  120  may include second analog receiving circuit  121 , second ADC  125 , second digital receiving circuit  126 , and second frequency divider  128 . 
     The first analog receiving circuit  111  may include a first receiving amplifier  112 , a first analog receiving mixer  113 , and a first analog receiving filter  114 , and the first digital receiving circuit  116  may include a first digital receiving mixer  117 . The second analog receiving circuit  121  may include a second receiving amplifier  122 , a second analog receiving mixer  123 , and a second analog receiving filter  124 , and the second digital receiving circuit  126  may include a second digital receiving mixer  127 . Operations of the second carrier receiver  120  may be the same as or similar to operations of the first carrier receiver  110  and thus redundant description will be omitted. 
     The first receiving amplifier  112  may amplify receiving signal RS and generate a first amplified receiving signal RS 1 . In an example, the first receiving amplifier  112  may be a low-noise amplifier (LNA). The first analog receiving mixer  113  may receive the first amplified receiving signal RS 1  and a second frequency signal FS 2 , translate a frequency band of the first amplified receiving signal RS 1  based on the second frequency signal FS 2 , and generate a first “mixed” receiving signal RS_M 1  (as noted above, a “mixed” signal herein refers to a signal that has been frequency translated by a mixer). (Herein, translating a frequency band of a signal refers to shifting all frequency components of the signal to thereby generate a frequency shifted signal substantially without distortion.) In an embodiment, the second frequency signal FS 2  may be a signal oscillating at a fixed second frequency, and the first analog receiving mixer  113  may down-convert the first amplified receiving signal RS 1  based on the second frequency and thereby place the first amplified receiving signal RS 1  in a predetermined channel. Signal RS_M 1  may have frequency components lower than corresponding frequency components of signal RS, by an amount equaling the frequency of signal FS 2 . (If signal RS is centered at X MHz and the frequency of FS 2  is Y MHz, signal RS_M 1  may be centered at Z=(X−Y) MHz.) 
     The first analog receiving filter  114  may filter the first mixed receiving signal RS_M 1  and generate a first analog receiving signal RS_A 1 . Although  FIG. 3  illustrates each of filters  114  and  124  as a low-pass filter (LPF), they may each alternatively be a band-pass filter (BPF) or a high-pass filter (HPF). 
     The first ADC  115  may generate first digital receiving signal RS_D 1  by sampling and quantizing the first analog receiving signal RS_A 1 . The first digital receiving mixer  117  may computationally translate a frequency band of signal RS_D 1  in a digital domain so as to generate first digital carrier signal CS 1 - d , and output the same to the MODEM (refer to  20  in  FIG. 1 ). To this end, digital mixer  117  may perform digital signal processing on the digital samples comprising signal RS_D 1 . This generates first digital carrier signal CS 1 - d  which may be composed of digital samples representing baseband signal energy of carrier signal CS 1 . These samples of baseband signal energy may then be demodulated by the MODEM, through calculations, to recover the original data carried by carrier signal CS 1 . Thus, according to the inventive concept, a frequency band of a receiving signal may be finely translated using a two-step mixing process using the first analog receiving mixer  113  and the first digital receiving mixer  117 . Thus, the frequency translation by the first analog receiving mixer  113  may be a coarse frequency translation by a coarse frequency offset, and the frequency translation by the first digital receiving mixer  117  may be fine frequency translation by a fine frequency offset smaller than the coarse frequency offset. The second carrier receiver  120  may likewise use a two-step mixing process to generate the second digital carrier signal CS 2 - d.    
       FIG. 4  is a flowchart of a method of operating a carrier receiver  110 , according to an example embodiment. 
     Referring to  FIGS. 3 and 4 , the carrier receiver  110  may amplify a receiving signal RS and generate a first amplified receiving signal RS 1  (S 110 ). The carrier receiver  110  may generate a second frequency signal FS 2  based on a first frequency signal FS 1  received from the PLL  200  (S 120 ). The carrier receiver  110  may translate a frequency band of a first amplified receiving signal RS 1  using a second frequency signal FS 2  and generate a first mixed receiving signal RS_M 1  (S 130 ). The carrier receiver  110  may filter the first mixed receiving signal RS_M 1  and generate the first analog receiving signal RS_A 1  (S 140 ). The carrier receiver  110  may sample RS_A 1  and generate a first digital receiving signal RS_D 1  (S 150 ). The carrier receiver  110  may translate a frequency band of RS_D 1  in a digital domain and generate a first digital carrier signal CS 1 - d  (S 160 ). 
       FIGS. 5A, 5B and 5C  are graphs illustrating a method of operating an analog receiving circuit, according to example embodiments. In  FIGS. 5A to 5C , the abscissa denotes a frequency freq, and the ordinate denotes power intensity PWR. 
     Referring to  FIGS. 3 and 5A , within carrier receiver  110 , the first receiving amplifier  111  may amplify the receiving signal RS and generate the first amplified receiving signal RS 1  including the first carrier signal CS 1  and a second carrier signal CS 2 . The first carrier signal CS 1  included in the first amplified receiving signal RS 1  may be disposed in a first channel CH 1 , and the second carrier signal CS 2  may be disposed in a second channel CH 2 . 
     Referring to  FIGS. 3 and 5B , the first analog receiving mixer  113  may translate the frequency band of the first amplified receiving signal RS 1  using the second frequency signal FS 2  having a second frequency f 2  and generate the first mixed receiving signal RS_M 1 . The first carrier signal CS 1  included in the first mixed receiving signal RS_M 1  may be located in a predetermined channel PC, which may be a channel that is f 2  Hz lower than the first channel CH 1 . 
     Referring to  FIGS. 3 and 5C , the first analog receiving filter  114  may filter the first mixed receiving signal RS_M 1  and generate the first analog receiving signal RS_A 1 . In an embodiment, the first analog receiving filter  114  may filter out signals outside the predetermined channel PC (eliminate signals other than those within the predetermined channel PC). In the embodiment shown in  FIG. 5C , the first analog receiving filter  114  may eliminate the second carrier signal CS 2  included in the first mixed receiving signal RS_M 1  and generate the first analog receiving signal RS_A 1  including only the first carrier receiving signal CS 1 . 
     In a similar manner, within carrier receiver  120 , the second analog receiving circuit  121  may translate the frequency band of receive signal RS by a frequency offset equal to f 3  Hz so as to place the second carrier signal CS 2  within a predetermined channel. This predetermined channel may be the same or different as the channel PC, depending on the divisor of frequency divider  128 , and signals outside the channel may be filtered out to facilitate the recovery of information carried by the second carrier signal CS 2 . 
       FIG. 6  is a block diagram of an RFIC,  10   a , according to an example embodiment. In this example, an amount of analog frequency translation within each carrier receiver may be dynamically selectable. Redundant descriptions with respect to  FIG. 3  will be omitted. 
     Referring to  FIG. 6 , the RFIC  10   a  may include a first carrier receiver  110   a , a second carrier receiver  120   a , and a PLL  200   a . The first carrier receiver  110   a  may include a first receiving amplifier  112   a , a first analog receiving mixer  113   a , a first analog receiving filter  114   a , a first ADC  115   a , a first digital receiving mixer  117   a , a first frequency divider  118 _ 1   a , a second frequency divider  118 _ 2   a , a third frequency divider  118 _ 3   a , and a first frequency switch  118 _ 4   a . The second carrier receiver  120   a  may include a second receiving amplifier  122   a , a second analog receiving mixer  123   a , a second analog receiving filter  124   a , a second ADC  125   a , a second digital receiving mixer  127   a , a fourth frequency divider  128 _ 1   a , a fifth frequency divider  128 _ 2   a , a sixth frequency divider  128 _ 3   a , and a second frequency switch  128 _ 4   a . Operations of the second carrier receiver  120   a  may be the same as or similar to operations of the first carrier receiver  110   a  and thus, redundant descriptions thereof will be omitted. 
     The first frequency divider  118 _ 1   a  may generate a second frequency signal FS 2  having a second frequency based on a received first frequency signal FS 1 . The second frequency divider  118 _ 2   a  may generate a third frequency signal FS 3  having a third frequency based on the received first frequency signal FS 1 . The third frequency divider  118 _ 3   a  may generate a fourth frequency signal FS 4  having a fourth frequency based on the received first frequency signal FS 1 . The first frequency switch  118 _ 4   a  may output one of the second frequency signal FS 2 , the third frequency signal FS 3 , and the fourth frequency signal FS 4  to the first analog receiving mixer  113   a  based on a first frequency selection signal Sig_FS 1 . In an example, the second frequency may be higher than the third frequency, and the third frequency may be higher than the fourth frequency. 
     According to an embodiment, the first carrier receiver  110   a  may selectively translate a frequency band of a first amplified receiving signal RS 1  based on the first frequency selection signal Sig_FS 1 . As a result, the first carrier receiver  110   a  may selectively sample a target carrier signal from a receiving signal RS based on the first frequency selection signal Sig_FS 1 . 
       FIG. 6  illustrates an example in which a plurality of frequency signals (e.g., FS 2 , FS 3 , and FS 4 ) output by a plurality of frequency dividers (e.g.,  118 _ 1   a ,  118 _ 2   a , and  118 _ 3   a ) included in the first carrier receiver  110   a  are different from a plurality of frequency signals (e.g., FS 5 , FS 6 , and FS 7 ) output by a plurality of frequency dividers  128 _ 1   a ,  128 _ 2   a , and  128 _ 3   a  included in the second carrier receiver  120   a . In an alternative example, the corresponding frequency signals of the frequency signals FS 2 , FS 3 , and FS 4  output by the frequency dividers  118 _ 1   a ,  118 _ 2   a , and  118 _ 3   a  and the frequency signals FS 5 , FS 6 , and FS 7  output by the frequency dividers  128 _ 1   a ,  128 _ 2   a , and  128 _ 3   a  may have the same frequency. In this case, the amount of frequency translation in each carrier receiver  110   a ,  120   a  may still differ from one another, through selection of a different respective frequency divider. 
     In alternative examples, the number of frequency dividers in each carrier receiver  110   a ,  110   b  may be more or fewer than three. In a further alternative embodiment, the switches  118 _ 4   a  and  128 _ 4   a  may be eliminated if a frequency divider in each carrier receiver is configured to selectively output one of a plurality of frequency signals based on the first frequency signal FS 1  and a control signal (not shown). 
       FIG. 7  is a block diagram of an RFIC,  10   b , according to an example embodiment. Redundant descriptions with respect to  FIG. 2  will be omitted. 
     Referring to  FIG. 7 , the RFIC  10   b  may include a first carrier receiver  110   b , a second carrier receiver  120   b , and a PLL  200   b . The first carrier receiver  110   b  may also include a first analog receiving circuit  111   b , a first ADC  115   b , a first digital receiving circuit  116   b , a first frequency divider  118   b , and a third frequency divider  119   b . The second carrier receiver  120   b  may include a second analog receiving circuit  121   b , a second ADC  125   b , a second digital receiving circuit  126   b , a second frequency divider  128   b , and a fourth frequency divider  129   b . Operations of the second carrier receiver  120   b  may be the same as or similar to operations of the first carrier receiver  110   b  and thus, redundant descriptions thereof will be omitted. 
     The third frequency divider  119   b  may receive a first frequency signal FS 1  from the PLL  200   b  and generate a fourth frequency signal FS 4  having a fourth, fixed frequency. The first ADC  115   b  may sample a first analog receiving signal RS_AL 1  using the fourth frequency signal FS 4  as a clock signal, and generate a first digital receiving signal RS_D 1 . In an embodiment, the fourth frequency signal FS 4  may have the same frequency as a fifth frequency signal FS 5  of the second carrier receiver  120   b . In another embodiment, signal FS 4  has a different frequency from that of signal FS 5 . In still another embodiment, at least one of the first ADC  115   b  and the second ADC  125   b  directly receives the first frequency signal FS 1  from the PLL  200   b  and perform an ADC operation using the first frequency signal FS 1  as a clock signal, rather than using signal FS 4  or FS 5  as the clock signal. In yet another alternative embodiment, only one, but not both, of the first and second ADCs  115   b ,  125   b  shares the PLL  200   b  with the respective analog receiving circuit  111   b  or  121   b.    
       FIG. 8  is a block diagram of an RFIC,  10   c , according to an example embodiment. In this embodiment, filtering of a frequency translated signal may be performed in the digital domain rather than in the analog domain. Redundant descriptions with respect to the RFIC of  FIG. 3  will be omitted. 
     Referring to  FIG. 8 , the RFIC  10   c  may include a first carrier receiver  110   c , a second carrier receiver  120   c , and a PLL  200   c . The first carrier receiver  110   c  may include a first analog receiving circuit  111   c , a first ADC  115   c , a first digital receiving circuit  116   c , and a first frequency divider  118   c . The second carrier receiver  120   c  may include a second analog receiving circuit  121   c , a second ADC  125   c , a second digital receiving circuit  126   c , and a second frequency divider  128   c.    
     The first analog receiving circuit  111   c  may include a first receiving amplifier  112   c  and a first analog receiving mixer  113   c . The first digital receiving circuit  116   c  may include a first digital receiving filter  114   c  and a first digital receiving mixer  117   c . The second analog receiving circuit  121   c  may include a second receiving amplifier  122   c  and a second analog receiving mixer  123   c . The second digital receiving circuit  126   c  may include a second digital receiving filter  124   c  and a second digital receiving mixer  127   c . Operations of the second carrier receiver  120   c  may be the same as or similar to operations of the first carrier receiver  110   c  and thus, redundant descriptions thereof will be omitted. 
     The first analog receiving mixer  113   c  may translate a frequency band of a first amplified receiving signal RS 1  based on a second frequency signal FS 2  and thereby generate a first mixed receiving signal RS_M 1 . The first ADC  115   c  may sample the first mixed receiving signal RS_M 1  and generate a first digital receiving signal RS_D 1 . The first digital receiving filter  114   c  may filter the first digital receiving signal RS_D 1  in the digital domain and thereby generate a third digital receiving signal RS_D 3 . The first digital receiving mixer  117   c  may translate the frequency band of the first digital receiving signal RS_D 3  in the digital domain and thereby generate a first digital carrier signal CS 1 - d.    
       FIG. 9  is a block diagram of an example transmitter portion of wireless communication device  1 , according to an embodiment. Redundant description of identical elements shown in  FIG. 1  will be omitted. As mentioned above in the discussion of  FIG. 1 , the RFIC  10  may include carrier receivers and/or carrier transmitters; the RFIC  10  of  FIG. 10  includes at least the carrier transmitters. Wireless communication device  1  may include RFIC  10  and MODEM  20 , where RFIC  10  may include a plurality n of carrier transmitters (e.g., first, second, and third carrier transmitters  310 ,  320 , and  330 ) and a PLL  200 . As noted above, a carrier transmitter refers to transmitter circuitry configured to process and transmit at least one carrier signal of a carrier aggregated signal. The PLL  200  may output a first frequency signal FS 1  to each of the first, second, and third carrier transmitters  310 ,  320 , and  330 . 
     Each of the first, second, and third carrier transmitters  310 ,  320 , and  330  may receive a plurality of digital carrier signals CS 1 - d  to CSn-d from the MODEM  20 , and process (e.g., filter, mix and upconvert, and/or amplify) the plurality of carrier signals CS 1 - d  to CSn-d using a respective fixed frequency signal generated based on a first frequency signal FS 1 . A carrier-aggregated transmitting signal TS may be generated by combining the processed signals using a combiner  7 . Each digital carrier signal CS 1 - d  to CSn-d may be a stream of digital samples of a modulated information signal. In an example, the first carrier transmitter  310  may process the first digital carrier signal CS 1 - d  using a second frequency signal generated based on the first frequency signal FS 1 , and the second carrier transmitter  320  may process the second digital carrier signal CS 2 - d  using a third frequency signal generated based on the first frequency signal FS 1 , to thereby generate first and second analog carrier signals CS 1 , CS 2 . The first carrier signal CS 1  may be merged with the second carrier signal CS 2  using the combiner  7  to generate at least part of the transmitting signal TS, which may be transmitted through an antenna Ant. 
     According to the inventive concept, the first, second, and third carrier transmitters  310 ,  320 , and  330  may generate respective target frequency signals based on the first frequency signal FS 1  received from a single PLL  200 , and process the plurality of carrier signals CS 1  to CSn (e.g., after they were converted to analog form) using the generated frequency signals. That is, the first, second, and third carrier transmitters  310 ,  320 , and  330  may share one PLL  200 . Thus, the number of PLLs  200  otherwise provided may be reduced and an area and power consumption for such PLLs  200  may be reduced. 
       FIG. 10  is a block diagram of an RFIC  10  according to an example embodiment. Redundant descriptions as with reference to  FIGS. 3 and 9  will be omitted. 
     Referring to  FIG. 10 , the RFIC  10  may include the first carrier transmitter  310 , second carrier transmitter  320 , and PLL  200 . The first carrier transmitter  310  may further include a first analog transmitting circuit  311 , a first DAC  315 , a first digital transmitting circuit  316 , a first frequency divider  318 , and a third frequency divider  319 . The second carrier transmitter  320  may include a second analog transmitting circuit  321 , a second DAC  325 , a second digital transmitting circuit  326 , a second frequency divider  328 , and a fourth frequency divider  329 . 
     The first analog transmitting circuit  311  may include a first transmitting amplifier  312 , a first analog transmitting mixer  313 , and a first analog transmitting filter  314 . The first digital transmitting circuit  316  may include a first digital transmitting mixer  317 . The second analog transmitting circuit  321  may include a second transmitting amplifier  322 , a second analog transmitting mixer  323 , and a second analog transmitting filter  324 . The second digital transmitting circuit  326  may include a second digital transmitting mixer  327 . Operations of the second carrier transmitter  320  may be the same as or similar to operations of the first carrier transmitter  310 , and thus, redundant descriptions thereof will be omitted. 
     The first digital transmitting mixer  317  may translate (e.g., up-convert) a frequency band of first carrier signal CS 1 - d  in a digital domain and thereby generate a first digital transmitting signal TS_D 1 . Also, the third frequency divider  319  may generate a fourth frequency signal FS 4  based on the first frequency signal FS 1 . The first DAC  315  may receive the fourth frequency signal FS 4  and generate a first analog transmitting signal TS_A 1  from the first digital transmitting signal TS_D 1  using the fourth frequency signal FS 4  as a clock for D/A conversion. The first analog transmitting filter  314  may filter the first analog transmitting signal TS_A 1  and generate a third analog transmitting signal TS_A 3 . The first frequency divider  318  may generate a second frequency signal FS 2  based on the first frequency signal FS 1 . The first analog transmitting mixer  313  may translate (e.g. up-convert) a frequency band of the third analog transmitting signal TS_A 3  using the second frequency signal FS 2  and thereby generate a first transmitting signal TS 1 . The first transmitting amplifier  312  may amplify the first transmitting signal TS 1  and output the amplified first transmitting signal TS 1 , which contains mainly the frequencies of a carrier signal CS 1  carrying the information of digital carrier signal CS 1 - d . In an example, the first transmitting amplifier  312  may be a power amplifier (PA). 
     As noted above, the RFIC  10  may further include the combiner (merging circuit)  7 , which may be configured to merge the first transmitting signal TS 1  with a second transmitting signal TS 2 , the latter containing mainly the frequencies of a carrier signal CS 2  in a band different from that of signal CS 1 . The merging circuit  7  may merge the first transmitting signal TS 1  received from the first carrier transmitter  310  with the second transmitting signal TS 2  received from the second carrier transmitter  320 , generate a carrier aggregated transmitting signal TS, and output the generated transmitting signal TS through an antenna to the exterior. 
       FIG. 10  illustrates an embodiment in which fixed frequency signals generated based on the first frequency signal FS 1  are output to the first and second analog transmitting mixers  313  and  323  and the first and second DACs  315  and  325  included in each of the first and second carrier transmitters  310  and  320 . However, the inventive concept is not limited thereto, and may be applied to an embodiment in which a frequency signal generated based on the first frequency signal FS 1  is output only to the first and second analog transmitting mixers  313  and  323  in a similar way to  FIG. 3 . In this case, clock signals used for the D/A conversion by DACs  315  and  325  may be obtained elsewhere. 
     In addition,  FIG. 10  illustrates an embodiment in which frequency signals FS 2  and FS 3  generated by the first and second frequency dividers  318  and  328  are respectively output to the first and second analog transmitting mixers  313  and  323 . However, the inventive concept is not limited thereto, and may be applied to an embodiment in which any one of a plurality of frequency signals generated by a plurality of frequency dividers is selectively output (at any given time) to the first and second analog transmitting mixers  313  and  323  in a similar way to the receive path embodiment of  FIG. 6 . 
     Moreover,  FIG. 10  illustrates an embodiment in which the first and second analog transmitting circuits  311  and  321  include the first and second transmitting amplifiers  312  and  322 , the first and second analog transmitting mixers  313  and  323 , and the first and second analog transmitting filters  314  and  324 , respectively. However, the inventive concept is not limited thereto, and may be applied to an embodiment in which the first and second analog transmitting circuits  311  and  321  include the first and second transmitting amplifiers  312  and  322  and the first and second analog transmitting mixers  313  and  323 , respectively, while each of the first and second digital transmitting circuits  316  and  326  include a digital transmitting filter and a digital transmitting mixer in a similar way to the receive path embodiment of  FIG. 8 . 
       FIG. 11  is a block diagram of an RFIC,  10   d , according to an example embodiment. Redundant descriptions with respect to  FIGS. 2 and 10  will be omitted. The RFIC  10   d  may include a plurality of carrier receivers (e.g.,  110   d ,  120   d , and  130   d ) and a plurality of carrier transmitters (e.g.,  310   d ,  320   d , and  330   d ), and a PLL  200   d . Also, each of the carrier receivers  110   d ,  120   d , and  130   d  may include an analog receiving circuit  111   d , an ADC  115   d , a digital receiving circuit  116   d , and a first frequency divider  118   d . Each of the carrier transmitters  310   d ,  320   d , and  330   d  may include an analog transmitting circuit  311   d , a DAC  315   d , a digital transmitting circuit  316   d , and a second frequency divider  318   d.    
     The PLL  200   d  may output a first frequency signal FS 1  to each of the carrier receivers  110   d ,  120   d , and  130   d  and the carrier transmitters  310   d ,  320   d , and  330   d . The first frequency divider  118   d  may generate a second frequency signal FS 2  based on the first frequency signal FS 1  and output the second frequency signal FS 2  to the analog receiving circuit  111   d . The second frequency divider  318   d  may generate a third frequency signal FS 3  based on the first frequency signal FS 1  and output the third frequency signal FS 3  to the analog transmitting circuit  311   d.    
       FIG. 11  illustrates an embodiment in which all the carrier receivers  110   d ,  120   d , and  130   d  and all the carrier transmitters  310   d ,  320   d , and  330   d  operate based on the first frequency signal FS 1 . In alternative embodiments, some, but not all, of the carrier receivers  110   d ,  120   d , and  130   d  and some, but not all, of the carrier transmitters  310   d ,  320   d , and  330   d  operate based on the first frequency signal FS 1 . 
       FIG. 12  is a block diagram of a wireless communication device  1   e  according to an example embodiment. The same descriptions as with reference to  FIG. 2  will be omitted. 
     Referring to  FIG. 12 , the wireless communication device  1   e  may include an RFIC  10   e  and a MODEM  20   e . The RFIC  10   e  may further include a first carrier receiver  110   e , a second carrier receiver  120   e , and a PLL  200   e , and the MODEM  20   e  may include a digital receiving circuit  21   e . The first carrier receiver  110   e  may include a first analog receiving circuit  111   e , a first ADC  115   e , a first frequency divider  118   e , and a third frequency divider  119   e . The second carrier receiver  120   e  may include a second analog receiving circuit  121   e , a second ADC  125   e , a second frequency divider  128   e , and a fourth frequency divider  129   e.    
     Unlike the embodiment shown in  FIG. 2 , the digital receiving circuit  21   e  may be located in the MODEM  20   e . The digital receiving circuit  21   e  may process (e.g., mix or filter) a first digital receive signal RS_D 1  received from the first ADC  115   e  and a second digital receive signal RS_D 2  received from the second ADC  125   e  in a digital domain and thereby generate digital carrier signals CS 1 - d  and CS 2 - d . These digital carrier signals may then be output to a modem processing circuit  27  for demodulation. Alternatively, sampling by ADCs  115   e ,  125   e  is sufficient to provide the digital receive signals RS_D 1  and RS_D 2  in a form suitable for direct demodulation, and these signals are routed directly to demodulation processing circuit  27 . Note that the digital receive signals RS_D 1  and RS_D 2  may be provided on individual signal paths to MODEM  20   f.    
       FIG. 13  is a block diagram of a wireless communication device,  1   f , according to an example embodiment. Redundant descriptions with respect to  FIG. 12  will be omitted. The wireless communication device if may include an RFIC  10   f  and a MODEM  20   f . In this example, MODEM  20   f  may include a digital receiving circuit  21   f  which may perform demodulation of digital carrier signals CS 1 - d , CS 2 - d  provided by RFIC  10   f  in a form suitable for direct demodulation. 
     The RFIC  10   f  may include a first carrier receiver  110   f , a second carrier receiver  120   f , and a PLL  200   f , and the MODEM  20   f  may include a digital receiving circuit  21   f . The first carrier receiver  110   f  may include a first analog receiving circuit  111   f , a first ADC  115   f , a first frequency divider  118   f , and a third frequency divider  119   f . The second carrier receiver  120   f  may include a second analog receiving circuit  121   f , a second ADC  125   f , a second frequency divider  128   f , and a fourth frequency divider  129   f . In addition, the first analog receiving circuit  111   f  may include a first receiving amplifier  112   f , a first analog receiving mixer  113   f , and a first analog receiving filter  114   f . The second analog receiving circuit  121   f  may include a second receiving amplifier  122   f , a second analog receiving mixer  123   f , and a second analog receiving filter  124   f.    
     In the embodiment shown in  FIG. 13 , a first carrier signal CS 1  and a second carrier signal CS 2  within carrier aggregated receive signal RS may be signals that are filtered by the first analog receiving filter  114   f  or the second analog receiving filter  124   f  After such filtering, analog filtered signals RS_A 1  and RS_A 2  may be composed mainly of carrier signals CS 1  and CS 2 , respectively. Signals RS_A 1  and RS_A 2  are A/D converted into digital carrier signals CS 1 - d , CS 2 - d  by ADCs  115   f  and  12   f , respectively. In an example, the digital receiving circuit  21   f  may directly demodulate signals CS 1 - d  and CS 2 - d , as noted above. Alternatively, the digital receiving circuit  21   f  include at least one digital mixer to digitally translate frequencies of the signals CS 1 - d  and CS 2 - d  in a digital domain prior to the demodulation that recovers the original data. (In this case, modem processing circuit  27  may be part of digital receiving circuit  21   f .) Note that the digital signals CS 1 - d  and CS 2 - d  may be provided on individual signal paths to MODEM  20   f.    
       FIG. 14  is a block diagram of a wireless communication device,  1   g , according to an example embodiment. Redundant descriptions with respect to  FIG. 13  will be omitted. 
     Referring to  FIG. 14 , the wireless communication device  1   g  may include an RFIC  10   g  and a MODEM  20   g . Also, the RFIC  10   g  may include a first carrier receiver  110   g , a second carrier receiver  120   g , and a PLL  200   g , and the MODEM  20   g  may include a digital receiving circuit  21   g . The first carrier receiver  110   g  may include a first analog receiving circuit  111   g , a first ADC  115   g , a first frequency divider  118   g , and a third frequency divider  119   g . The second carrier receiver  120   g  may include a second analog receiving circuit  121   g , a second ADC  125   g , a second frequency divider  128   g , and a fourth frequency divider  129   g . In addition, the first analog receiving circuit  111   g  may include a first receiving amplifier  112   g  and a first analog receiving mixer  113   g , and the second analog receiving circuit  121   g  may include a second receiving amplifier  122   g  and a second analog receiving mixer  123   g.    
     In device  1   g , a first digital carrier signal CS 1 - d  and a second carrier signal CS 2 - d  may be unfiltered signals. The digital receiving circuit  21   g  may include at least one digital mixer and at least one digital filter. The at least one digital filter may filter the first digital carrier signal CS 1 - d  and the second digital carrier signal CS 2 , and the at least one digital mixer may translate frequencies of the first carrier signal CS 1  and the second carrier signal CS 2  in a digital domain. 
       FIG. 15  is a block diagram of a wireless communication device  1   h  according to an example embodiment. Redundant description with respect to  FIG. 9  will be omitted. The wireless communication device  1   h  may include an RFIC  10   h  and a MODEM  20   h . Also, the RFIC  10   h  may include a first carrier transmitter  310   h , a second carrier transmitter  320   h , and a PLL  200   h , and the MODEM  20   h  may include a digital transmitting circuit  21   h . The first carrier transmitter  310   h  may include a first analog transmitting circuit  311   h , a first DAC  315   h , a first frequency divider  318   h , and a third frequency divider  319   h . The second carrier transmitter  320   h  may include a second analog transmitting circuit  321   h , a second ADC-DAC  325   h , a second frequency divider  328   h , and a fourth frequency divider  329   h.    
     Unlike the embodiment shown in  FIG. 9 , the digital transmitting circuit  21   h  of device  1   h  may be located in the MODEM  20   h . The digital transmitting circuit  21   h  may process (e.g., mix or filter) carrier signals in a digital region and output the processed first and second carrier signals CS 1 - d  and CS 2 - d.    
       FIG. 16  is a block diagram of an RFIC,  10   i , according to an example embodiment. Redundant description with respect to  FIG. 1  will be omitted. The RFIC  10   i  may include a first carrier receiver  110   i , a second carrier receiver  120   i , a third carrier receiver  130   i , a fourth carrier receiver  140   i , a first PLL  210   i , and a second PLL  220   i.    
     The first PLL  210   i  may output a first frequency signal FS 1  having a first frequency to the first carrier receiver  110   i  and the second carrier receiver  120   i . The second PLL  220   i  may output a second frequency signal FS 2  having a second frequency to the third carrier receiver  130   i  and the fourth carrier receiver  140   i.    
     The first carrier receiver  110   i  may sample a first carrier signal CS 1  from a receiving signal RS using a frequency signal generated based on the first frequency signal FS 1  to generate digital carrier signal CS 1 - d . The second carrier receiver  120   i  may sample a second carrier signal CS 2  from the receiving signal RS using the frequency signal generated based on the first frequency signal FS 1  to generate digital carrier signal CS 2 - d . The third carrier receiver  130   i  may sample a third carrier signal CS 3  from the receiving signal RS using a frequency signal generated based on the second frequency signal FS 2  to generate digital carrier signal CS 3 - d . The fourth carrier receiver  140   i  may sample a fourth carrier signal CS 4  from the receiving signal RS using the frequency signal generated based on the second frequency signal FS 2  to generate digital carrier signal CS 4 - d.    
     Although  FIG. 16  illustrates an RFIC including a plurality of carrier receivers, the inventive concept of  FIG. 16  may be also applied to a plurality of carrier transmitters. 
       FIG. 17  is a block diagram of an RFIC,  10   j , according to an example embodiment. Redundant description with respect to  FIG. 1  will be omitted. The RFIC  10   j  may include a first carrier receiver  110   j , a second carrier receiver  120   j , a third carrier receiver  130   j , a fourth carrier receiver  140   j , a PLL  210   j , and a frequency divider  230   j.    
     The PLL  210   j  may output a first frequency signal FS 1  having a first frequency to the frequency divider  230   j , the first carrier receiver  110   j , and the second carrier receiver  120   j . The frequency divider  230   j  may output a second frequency signal FS 2  having a second frequency to the third carrier receiver  130   j  and the fourth carrier receiver  140   j  based on the first frequency signal FS 1  received from the PLL  210   j.    
     The first carrier receiver  110   j  may sample a first carrier signal CS 1  from a receiving signal RS using a frequency signal generated based on the first frequency signal FS 1  to generate a digital carrier signal CS 1 - d . The second carrier receiver  120   j  may sample a second carrier signal CS 2  from the receiving signal RS using the frequency signal generated based on the first frequency signal FS 1  to generate a digital carrier signal CS 2 - d . The third carrier receiver  130   j  may sample a third carrier signal CS 3  from the receiving signal RS using a frequency signal generated based on the second frequency signal FS 2  to generate a digital carrier signal CS 3 - d . The fourth carrier receiver  140   j  may sample a fourth carrier signal CS 4  from the receiving signal RS using the frequency signal generated based on the second frequency signal FS 2  to generate a digital carrier signal CS 4 - d.    
     Although  FIG. 17  illustrates an RFIC including a plurality of carrier receivers, the inventive concept of  FIG. 17  may be also applied to a plurality of carrier transmitters. 
       FIG. 18  is a block diagram of an RFIC,  10   k , according to an example embodiment. Redundant description with respect to  FIG. 1  will be omitted. The RFIC  10   k  may include a first carrier receiver  110   k , a second carrier receiver  120   k , a first PLL  210   k , and a PLL switch  240   k . Also, the first carrier receiver  110   k  may include a second PLL PLL 2 , and the second carrier receiver  120   k  may include a third PLL PLL 3 . 
     The first PLL  210   k  may output a first frequency signal FS 1  having a first frequency to the PLL switch  240   k . The PLL switch  240   k  may output the first frequency signal FS 1  to the first carrier receiver  110   k  and the second carrier receiver  120   k  based on a first signal Sig 1 . 
     In an embodiment in which the PLL switch  240   k  outputs the first frequency signal FS 1  to the first carrier receiver  110   k  and the second carrier receiver  120   k  based on the first signal Sig 1 , the first carrier receiver  110   k  and the second carrier receiver  120   k  may sample carrier signals CS 1  and CS 2  from a receiving signal RS using a frequency signal generated based on the first frequency signal FS 1 , to generate digital carrier signals CS 1 - d  and CS 2 - d , respectively. 
     In an embodiment in which the PLL switch  240   k  outputs the first frequency signal FS 1  only to the first carrier receiver  110   k  based on the first signal Sig 1 , the first carrier receiver  110   k  may sample a first carrier signal CS 1  from a receiving signal RS using a frequency signal generated based on the first frequency signal FS 1 , and the second carrier receiver  120   k  may sample a second carrier signal CS 2  from the receiving signal RS using a frequency signal generated by the third PLL PLL 3 , to generate digital carrier signals CS 1 - d , CS 2 - d.    
     In an embodiment in which the PLL switch  240   k  does not output the first frequency signal FS 1  to the first carrier receiver  110   k  and the second carrier receiver  120   k  based on the first signal Sig 1 , the first carrier receiver  110   k  may sample a first carrier signal CS 1  from a receiving signal RS using a frequency signal generated by the second PLL PLL 2 , and the second carrier receiver  120   k  may sample a second carrier signal CS 2  from the receiving signal RS using a frequency signal generated by the third PLL PLL 3 . Although  FIG. 18  illustrates an RFIC including a plurality of carrier receivers, the inventive concept may be also applied in a similar manner to a plurality of carrier transmitters. 
       FIG. 19  is a diagram of a wireless communication system including various wireless communication equipment according to an example embodiment. In the example system, each of a home gadget  2100 , a home appliance  2120 , entertainment equipment  2140 , and an AP  2200  may include a wireless communication device for transmitting/receiving carrier aggregated signals according to an example embodiment. In some embodiments, the home gadget  2100 , the home appliance  2120 , the entertainment equipment  2140 , and the AP  2200  may together constitute an Internet of Things (IoT) network system. The items of communication equipment shown in  FIG. 19  are only examples, and it will be understood that a wireless communication device according to an example embodiment may be included in other types of communication equipment. 
     The home gadget  2100 , the home appliance  2120 , the entertainment equipment  2140 , and the AP  2200  may transmit/receive carrier aggregated signals using the wireless communication devices according to the above-described example embodiments. In an embodiment, the home gadget  2100 , the home appliance  2120 , the entertainment equipment  2140 , and the AP  2200  may include a plurality of carrier transmitters and/or a plurality of carrier receivers configured to share a PLL with each other. Thus, area and power consumption of the respective wireless communication devices included in the home gadget  2100 , the home appliance  2120 , the entertainment equipment  2140 , and the AP  2200  may be reduced. 
     Typical example embodiments of the inventive concept are disclosed in the above description and the drawings. Although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation. It will be understood by one of ordinary skill in the art that various changes in form and details may be made to the disclosed embodiments without departing from the spirit and scope of the inventive concept as defined by the following claims.