Patent Publication Number: US-2002003308-A1

Title: Semiconductor chip package and method for fabricating the same

Description:
BACKGROUND OF THE INVENTION  
       [0001] 1. Field of the Invention  
       [0002] The present invention relates to a semiconductor chip package and a method for fabricating the same, and more particularly to a chip scale package and a method for fabricating the same.  
       [0003] 2. Description of the Related Art  
       [0004] As semiconductor integrated circuit chips become more multi-functional and highly integrated, the chips include more bonding pads (or terminal pads), and thus packages for the chips have more external terminals (or leads). When a conventional plastic package that has its leads along the perimeter of the package must accommodate a large number of leads, the footprint of the package increases. However, a goal in many electronic systems is to minimize the size of the systems. Thus, to accommodate a large number of pins without increasing the footprint of package, pin pitch (or lead pitch) of the package must decrease. However, a pin pitch of less than about 0.4 mm gives rise to many technical concerns. For example, trimming of a package having a pin pitch less than 0.4 mm requires expensive trimming tools, and the leads are prone to bending during handling of the package. In addition, surface-mounting of such packages demands a costly and complicated surface-mounting process.  
       [0005] To avoid the technical problems of conventional fine-pitch packages, packages that have area array external terminals have been suggested. Among these packages are ball grid array packages and chip scale packages, which can be considered miniaturized versions of the ball grid array packages. The semiconductor industry presently uses a number of chip scale packages. A micro ball grid array package (μBGA) and a bump chip carrier (BCC) are examples of the chip scale packages. The μBGA package includes a polyimide tape on which a conductive pattern is formed and employs a totally different manufacturing process from a conventional plastic packaging. The bump chip carrier package includes a substrate having grooves formed around a central portion of a top surface of a copper alloy plate and an electroplating layer formed in the grooves. Accordingly, chip scale packages use specialized packaging materials and processes that increase package manufacturing costs.  
       [0006] Therefore, a chip scale package that uses conventional packaging materials and processes is needed for a cost-effective package with a small footprint.  
       SUMMARY OF THE INVENTION  
       [0007] According to an embodiment of the present invention, a semiconductor package includes: a substrate having a conductive lead pattern formed on a bottom surface of the substrate and holes open to a top surface of the substrate so as to expose part of the conductive lead pattern; a semiconductor chip attached to the top surface of the substrate; bonding wires electrically connecting bonding pads of the chip to the corresponding exposed conductive lead pattern; and an encapsulating body which encapsulates the semiconductor chip and the bonding wires. The conductive lead pattern is used as external terminals of the package, and additional conductive means such as solder balls can be attached to the conductive patterns to facilitate surface-mounting of the package.  
       [0008] The semiconductor package can further include a deformation preventing pattern to reduce warpage of the package. The deformation preventing pattern can be made of the same material as the conductive pattern, or can be made of an insulating material.  
       [0009] Instead of the bonding wires, conductive bumps can be formed on the bonding pads of the chip, so that the chip is flip-bonded to the exposed conductive pattern. In addition, a plated layer may be formed on the conductive lead pattern.  
       [0010] In accordance with another embodiment of the invention, a method for forming the semiconductor package described above includes: preparing the substrate; attaching a semiconductor chip to the top surface of the substrate with an adhesive; electrically connecting the bonding pads of the chip to the corresponding exposed conductive pattern; and encapsulating semiconductor chip and any bonding wires or conductive bumps. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0011] Features and advantages of the present invention will become apparent by describing in detail specific embodiments thereof with reference to the accompanying drawings, in which:  
     [0012]FIG. 1 is a partial cut-away perspective view of a semiconductor package according to an embodiment of the present invention;  
     [0013]FIG. 2 is a bottom view of the semiconductor package of FIG. 1;  
     [0014]FIG. 3 is a sectional view of the semiconductor package of FIG. 1, taken along the line I-I;  
     [0015]FIG. 4 is a sectional view of another semiconductor package according to the invention;  
     [0016]FIG. 5 a  is a bottom view of a semiconductor package having the cross-section of FIG. 4;  
     [0017]FIG. 5 b  is a bottom view of another semiconductor package having the cross-section of FIG. 4;  
     [0018]FIG. 6 is a sectional view of another semiconductor package according to the invention;  
     [0019]FIG. 7 is a bottom view of the semiconductor package of FIG. 6;  
     [0020]FIG. 8 is a sectional view of another semiconductor package according to the invention;  
     [0021] FIGS.  9  to  12  are sectional views of semiconductor packages that according to the invention use conductive bumps instead of bonding wires;  
     [0022]FIG. 13 is a flow diagram of a method for fabricating a semiconductor chip package according to an embodiment of the present invention; and  
     [0023]FIG. 14 is a flow diagram of a method for fabricating a semiconductor chip package according to another embodiment of the present invention.  
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     [0024] Referring to FIGS.  1  to  3 , which illustrate a semiconductor package according to an embodiment of the present invention, a semiconductor chip  1  is attached by an adhesive  3  on a top surface of a substrate  10 . Substrate  10  includes an insulating sheet  11  and a conductive lead pattern  13  formed under insulating sheet  11 . Insulating sheet  11  can be made of a printed circuit board material such as polyimide or FR-5 epoxy, and a silver (Ag) epoxy can be employed as adhesive  3 , which attaches chip  1  to insulating sheet  11 . Holes  12  formed through insulating sheet  11  are around the perimeter of chip  1  and expose part of conductive lead pattern  13 . Metal wires  5  electrically connect bonding pads  2  of chip  1  to the exposed parts of conductive lead pattern  13 . Finally, a mold body  7 , which is typically made of a molding compound, encapsulates chip  1  and metal wires  5 .  
     [0025] To prevent oxidation of conductive lead pattern  13  and facilitate soldering of the semiconductor package to a mother board, a plated layer  15  can be formed on conductive lead pattern  13 . Plated layer  15  can be formed of tin, solder alloys or gold. In addition, being external terminals of the semiconductor package, conductive lead pattern  13  is patterned so as to accommodate various surface-mounting technologies. In FIG. 2, conductive lead pattern  13  extends to edges of insulating sheet  11  for edge soldering.  
     [0026] The semiconductor package of FIG. 2 includes no pattern on a center portion of a bottom surface of insulating sheet  11 . When chip  1  is attached to insulating sheet  11 , the center portion can be deformed or warped due to a difference between the thermal expansion coefficients of chip  1  and insulating sheet  11 . To make the center portion resistant to the deformation, a deformation preventing pattern can be formed on the bottom surface of insulating sheet  11  as shown in FIGS. 4, 5A and  5 B. FIGS. 5A and 5B respectively show a single deformation preventing pattern  14  and a divided deformation preventing pattern  18  formed at the center portion of the bottom surface of insulating sheet  11 . Deformation preventing patterns  14  and  18  can be made of the same material as conductive lead pattern  13  or of an insulating material, and are electrically separate from conductive lead pattern  13 .  
     [0027] FIGS.  6  to  8  show semiconductor packages having conductive lead patterns  13  that do not extend to the edges of the packages. The package of FIG. 6 does not include a deformation preventing pattern, while the packages of FIGS. 7 and 8 include a deformation preventing pattern  14 .  
     [0028] Referring to FIG. 13, two methods of manufacturing the semiconductor packages of FIGS.  1  to  8  in accordance with the present invention can be explained. One method starts with step  31  by preparing a substrate that includes an insulating sheet having throughholes formed along a perimeter of one or more central areas for mounting of one or more chips. A large base substrate having multiple unit substrates, each unit substrate having a central area for a chip, can be used to improve efficiency of a packaging process. A conductive plate attaches to a bottom side of the insulating sheet.  
     [0029] Step  32  attaches one or more semiconductor chips to the insulating sheet with an adhesive. In step  33 , a conventional wirebonding connects bonding pads of each semiconductor chip to the conductive plate where exposed through the throughholes; and a transfer-molding or dispensing of step  34  encapsulates each semiconductor chip and its associated wirebonding area.  
     [0030] After step  34 , a conventional etching process patterns the conductive plate to form a conductive lead patterns which form the external terminals of each semiconductor package and if necessary, deformation preventing patterns (step  35 ). Step  36  plates the conductive lead pattern with tin, solder alloys or gold using a plating technique such as electroplating. The deformation preventing pattern can be formed in an extra step after step  36  by attaching pieces of insulating material to the bottom surface of the substrate. Finally, when a number of semiconductor packages are manufactured on a large base substrate having multiple unit substrates, step  39  separates the base substrate to form individual semiconductor packages.  
     [0031] The other method of FIG. 13 eliminates steps  35  and  36 . Instead, step  31  prepares a substrate that includes an insulating sheet and a conductive lead pattern formed on a bottom surface of the insulating sheet. Selectively etching a conductive sheet attached to the bottom surface of the insulating film can prepare such a substrate. If necessary, the conductive lead pattern is plated with tin, solder alloys or gold. In addition, a deformation preventing pattern can be formed on the bottom surface of the insulating film by the etching or attaching a piece of insulating sheet. Steps  34 ,  33 ,  34  and  39  are the same in both methods.  
     [0032] FIGS.  9  to  12  show semiconductor packages, which employ flip-chip bonding to connect semiconductor chips to external terminals of the packages, in accordance with other embodiments of the present invention.  
     [0033] Referring to FIGS.  9  to  12 , a semiconductor chip  31  having conductive bumps  33  formed on bonding pads of semiconductor chip  31  electrically connects to a substrate  20  which includes an insulating sheet  21  and a conductive lead pattern  23  formed under insulating sheet  21 . Insulating sheet  21  has holes  22  formed therethrough along a perimeter of chip  31 , and a part of conductive lead pattern  23  is exposed through throughholes  22 . Conductive bumps  33  connect to the exposed part of conductive lead pattern  23  by a flip-chip bonding. Then, an encapsulating body  40  is formed between chip  31  and substrate  20  to protect the flip-chip bonding area. Encapsulating body  40  is typically formed by dispensing a liquid encapsulant (underfill material), and thus, in order to prevent an overflow of the encapsulant, substrate  20  may include a dam  25  formed on a top surface thereof. Insulating sheet  21  can be made of a printed circuit board material such as polyimide or FR-5 epoxy, and conductive bumps  33  can be made of solder alloys.  
     [0034] To prevent oxidation of conductive lead pattern  23  and to obtain an easy soldering of the semiconductor package to a mother board, an electroplating layer  29  can be formed on conductive lead pattern  23 . Electroplating layer  29  can be formed of tin, solder alloys or gold. In addition, being external terminals of the semiconductor package, conductive lead pattern  23  is patterned so as to accommodate various surface-mounting technologies. In FIGS. 9 and 10, conductive lead pattern  23  extends to edges of insulating sheet  21  for edge soldering.  
     [0035] The semiconductor package of FIG. 9 includes no pattern on a center portion of a bottom surface of insulating sheet  21 . When chip  31  is flip-chip bonded to insulating sheet  11 , the center portion can be deformed or warped due to a difference between the thermal expansion coefficients of chip  31  and insulating sheet  21 . Thus, to make the center portion resistant to the deformation, a deformation preventing pattern  24  can be formed on the bottom surface of insulating sheet  21  as shown in FIGS. 10 and 12. Deformation preventing patterns  24  can be made of the same material as conductive lead pattern  13  or an insulating sheet material, and is electrically insulated from conductive lead pattern  13 . FIGS. 11 and 12 show semiconductor packages having their conductive lead patterns  23  not extending to the edges of the packages.  
     [0036] Referring to FIG. 14, two methods of manufacturing the semiconductor packages of FIGS.  9  to  12  in accordance with the present invention can be explained. One method starts with step  41  by preparing a substrate. The substrate includes an insulating sheet having throughholes formed to receive conductive bumps of a semiconductor chip. A conductive plate attaches to the bottom of the insulating sheet. In step  42 , a flip chip bonding bonds the conductive bumps formed on bonding pads of the semiconductor chip to the portions of the conductive plate exposed through the throughholes; and a dispensing method of step  43  encapsulates the flip-chip bonding area between the chip and the substrate.  
     [0037] After step  43 , a conventional etching process of step  44  patterns the conductive plate to form a conductive lead pattern which is used as external terminals of the semiconductor package and if necessary, a deformation preventing pattern. Step  45  plates the conductive lead pattern with tin, solder alloys or gold. The deformation preventing pattern can be formed in an optional step after step  45  by attaching a piece of an insulating sheet to the bottom surface of the substrate. Finally, when a number of semiconductor packages are manufactured on a large base substrate having multiple unit substrates, step  48  separates the base substrate into individual semiconductor packages.  
     [0038] The alternative method of FIG. 14 eliminates steps  44  and  45 . Instead, step  41  prepares a substrate that includes an insulating sheet and a conductive lead pattern formed on a bottom surface of the insulating sheet, for example, by selectively etching a conductive sheet attached to the bottom surface of the insulating film. If necessary, the conductive lead pattern is plated with tin, solder alloys or gold. In addition, a deformation preventing pattern can be formed on the bottom surface of the insulating film by the etching or attaching a piece of an insulating sheet. Steps  41 ,  32 ,  43  and  48  are the same in both methods.  
     [0039] The constituents and manufacturing methods employed in the semiconductor packages in accordance with the present invention are common in the field of semiconductor chip packaging so that none of extra cost or difficulties that arise in manufacturing of a conventional fine-pitch plastic package occur.  
     [0040] The present invention has been described above with reference to the aforementioned embodiments. It is evident, however, that many alternative modifications and variations will be apparent to those having skill in the art in light of the foregoing description. Accordingly, the present invention embraces all such alternative modifications and variations as fall within the spirit and scope of the invention defined by the appended claims.