Patent Publication Number: US-11646205-B2

Title: Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to U.S. Patent Application Ser. No. 62/927,553 filed Oct. 29, 2019 titled “METHODS OF SELECTIVELY FORMING N-TYPE DOPED MATERIAL ON A SURFACE, SYSTEMS FOR SELECTIVELY FORMING N-TYPE DOPED MATERIAL, AND STRUCTURES FORMED USING SAME,” the disclosure of which is hereby incorporated herein by reference in its entirety. 
    
    
     FIELD OF INVENTION 
     The present disclosure generally relates to methods and systems suitable for forming electronic devices. More particularly, the disclosure relates to methods and systems that can be used for selectively forming a doped semiconductor material on a surface of a substrate. 
     BACKGROUND OF THE DISCLOSURE 
     The scaling of semiconductor devices, such as, for example, complementary metal-oxide-semiconductor (CMOS) devices, has led to significant improvements in speed and density of integrated circuits. However, conventional device scaling techniques face significant challenges for future technology nodes. 
     For example, for several applications, it may be desirable to form highly-doped n-type semiconductor material that can form a source region or drain region of an n-type metal-oxide semiconductor (NMOS) portion of a CMOS device. Approaches to form such regions can include traditional deposition, pattern, and etch processes. However, as the size of devices decreases and the geometry or topology of the devices becomes more complex, it is often desirable to selectively form highly-doped n-type semiconductor material only on selected areas of a substrate. 
     Typical approaches for selectively depositing highly-doped n-type semiconductor material, such as phosphorus-doped silicon, include use of dichlorosilane and phosphine at temperatures in excess of 600° C. Although such techniques can work in some cases, the deposition temperature may be undesirably high for several applications. And, low resistivity values, desired for some applications, may not be achievable using such techniques. 
     Cyclical deposition and etch processes have also been reported to selectively form highly-doped n-type semiconductor material. However, such processes are relatively slow and expensive. 
     Accordingly, improved methods for selectively forming highly-doped n-type semiconductor material at relatively low temperature and/or using a relatively quick and/or less expensive process, improved systems for forming the highly-doped n-type semiconductor material, and structures and devices including the highly-doped n-type semiconductor material are desired. 
     SUMMARY OF THE DISCLOSURE 
     This summary is provided to introduce a selection of concepts in a simplified form. These concepts are described in further detail in the detailed description of example embodiments of the disclosure below. This summary is not necessarily intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. 
     Various embodiments of the present disclosure relate to methods for selectively forming highly-doped n-type semiconductor material on portions of a substrate, to structures and devices formed using such methods, and to apparatus for performing the methods and/or for forming the structure and/or devices. While the ways in which various embodiments of the present disclosure address drawbacks of prior methods and systems are discussed in more detail below, in general, various embodiments of the disclosure provide improved methods of selectively forming highly-doped n-type semiconductor material at relatively low temperatures and/or using relatively fast (e.g., compared to cyclical deposition and etch processes) epitaxial growth techniques. The highly-doped n-type semiconductor material can exhibit relatively low contact resistance, and can be used, for example, to form source, drain, or other regions of devices, such as CMOS devices. 
     In accordance with exemplary embodiments of the disclosure, a method for selectively forming n-type doped material on a surface of a substrate is disclosed. Exemplary methods include providing a substrate, comprising a surface comprising a first area comprising a first material and a second area comprising a second material, within a reaction chamber; depositing an n-type doped semiconductor material overlying the surface, wherein the n-type doped semiconductor material forms as doped monocrystalline material overlying the first area and as doped non-monocrystalline material overlying the second area; and depositing a semiconductor material overlying the n-type doped semiconductor material, wherein the semiconductor material forms as monocrystalline material overlying the first area and as non-monocrystalline material overlying the second area. An etch rate of the monocrystalline material overlying the first area may be much lower than an etch rate of the non-monocrystalline material overlying the second area. Thus, the monocrystalline material overlying the first area can serve as an etch barrier during a step of removing the non-monocrystalline material overlying the second area and the non-monocrystalline n-type doped semiconductor material overlying the second area. In accordance with various aspects of these embodiments, the semiconductor material includes intrinsically-doped semiconductor material or semiconductor material with an dopant (e.g., extrinsic dopant or total dopant) concentration of less than 1 at-% or less than 0.02 at-% or less than 1×10 17 . The semiconductor material can include a Group IV semiconductor, such as one or more of silicon, carbon, germanium, and tin. The n-type doped semiconductor material can include the semiconductor material and one or more n-type dopants, such as one or more Group V dopants. The one or more Group V dopants can be selected from the group consisting of phosphorus, arsenic, and antimony, in any combination. A concentration of one or more n-type dopants in the n-type doped semiconductor material can be greater than 0.3 at-%, greater than 2 at-%, greater than 3 at-%, greater than 4 at-%, greater than 5 at-%, greater than 6 at-%, greater than 7 at-% and/or less than 20 at-%, less than 15 at-%, or less than 10 at-%. A temperature within the reaction chamber (e.g., of a susceptor within the reaction chamber) during the step of depositing an n-type doped semiconductor material and/or the step of depositing a semiconductor material can be less than 700° C., less than 600° C., less than 550° C., less than 525° C., less than 500° C., less than 475° C., or between about 400° C. and about 600° C. Exemplary methods can further include a step of etching the monocrystalline material overlying the first area and the non-monocrystalline material overlying the second area. Further exemplary methods can include selectively removing the n-type doped semiconductor material in the second area. The first material can be monocrystalline. The second material can be non-monocrystalline. The first material can include semiconductor material, such as Group IV semiconductor material. The second material can include dielectric material, such as an oxide, a nitride, or an oxynitride (e.g., silicon oxide, silicon nitride, or silicon oxynitride). 
     In accordance with further exemplary embodiments of the disclosure, a structure is formed using a method as described herein. The structure can include a substrate and an n-type doped semiconductor material formed overlying a portion of the substrate. A concentration of one or more n-type dopants in the n-type doped semiconductor material can be greater than 0.3 at-%, greater than 2 at-%, greater than 3 at-%, greater than 4 at-%, greater than 5 at-%, greater than 6 at-%, greater than 7 at-%, greater than 8 at-% and/or less than 20 at-%, less than 15 at-%, or less than 10 at-%. Additionally or alternatively, a sheet resistance of the n-type doped material layer can be less than 1 mOhm·cm, less than 0.7 mOhm·cm, less than 0.5 mOhm·cm, less than 0.4 mOhm·cm, less than 0.35 mOhm·cm, less than 0.3 mOhm·cm, or less than 0.25 mOhm·cm. The n-type doped material layer can be used to form, for example, a source and/or drain region of a device, such as a field effect transistor (FET) (e.g., a FinFET) or other MOSFET devices. 
     In accordance with yet additional embodiments of the disclosure, a device or portion thereof can be formed using a method and/or a structure as described herein. 
     In accordance with yet additional examples of the disclosure, a system to perform a method as described herein and/or to form a structure, device, or portion of either is disclosed. 
     These and other embodiments will become readily apparent to those skilled in the art from the following detailed description of certain embodiments having reference to the attached figures. The invention is not being limited to any particular embodiments disclosed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       A more complete understanding of the embodiments of the present disclosure may be derived by referring to the detailed description and claims when considered in connection with the following illustrative figures. 
         FIG.  1    illustrates a method in accordance with at least one embodiment of the disclosure. 
         FIG.  2    illustrates a substrate or structure for use with methods in accordance with exemplary embodiments of the disclosure. 
         FIGS.  3 - 5    illustrate structures formed in accordance with at least one embodiment of the disclosure. 
         FIG.  6    illustrates a cross-sectional view of an NMOS device formed in accordance with at least one embodiment of the invention. 
         FIG.  7    illustrates a reactor system in accordance with additional exemplary embodiments of the disclosure. 
     
    
    
     It will be appreciated that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of illustrated embodiments of the present disclosure. 
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     Although certain embodiments and examples are disclosed below, it will be understood by those in the art that the invention extends beyond the specifically disclosed embodiments and/or uses of the invention and obvious modifications and equivalents thereof. Thus, it is intended that the scope of the invention disclosed should not be limited by the particular disclosed embodiments described below. Further, the illustrations presented herein are not necessarily meant to be actual views of any particular material, structure, or device, but rather may be idealized representations that can be used to describe embodiments of the disclosure. 
     As set forth in more detail below, various embodiments of the disclosure provide methods for selectively forming n-type doped semiconductor material overlying a portion of a surface of a substrate relative to another portion of the surface of the substrate. Exemplary methods can be used to, for example, form source and/or drain regions of semiconductor devices (e.g., MOSFETs and/or FinFETs) that exhibit relatively low contact resistance, can be formed at relatively low temperatures, and/or can be formed relatively quickly and/or inexpensively—e.g., compared to similar devices or structures using typical cyclical deposition and etch techniques. 
     In this disclosure, “gas” can include material that is a gas at normal temperature and pressure (NTP), a vaporized solid and/or a vaporized liquid, and can be constituted by a single gas or a mixture of gases, depending on the context. A gas other than the process gas, e.g., a gas introduced without passing through a gas distribution assembly, a multi-port injection system, other gas distribution device, or the like, can be used for, e.g., sealing the reaction space, and can include a seal gas, such as a rare gas. In some cases, the term “precursor” can refer to a compound that participates in the chemical reaction that produces another compound, and particularly to a compound that constitutes a film matrix or a main skeleton of a film; in this disclosure, the term “reactant” can be used interchangeably with the term precursor. The term “inert gas” can refer to a gas that does not take part in a chemical reaction and/or does not become a part of a film matrix to an appreciable extent. Exemplary inert gases include helium (He), Argon (Ar), and nitrogen (N 2 ), and any combination thereof. Inert gases can be used as dilution gases and/or carrier gases. 
     As used herein, the term “substrate” can refer to any underlying material or materials that can be used to form, or upon which, a device, a circuit, or a film can be formed. A substrate can include a bulk material, such as silicon (e.g., single-crystal silicon), other Group IV materials, such as carbon, germanium, and/or tin, or compound semiconductor material, and can include one or more layers overlying or underlying the bulk material. Further, the substrate can include various features, such as recesses, protrusions, and the like formed within or on at least a portion of a layer of the substrate. As set forth in more detail below, a surface of a substrate can include two or more areas, wherein a material in the first area differs from the material in the second area—e.g., the materials can have different compositions and/or different crystalline structure. 
     As used herein, the term “epitaxial layer” can refer to a substantially single crystalline layer upon an underlying substantially single crystalline substrate or layer. 
     As used herein, the term “monocrystalline” may refer to a material that includes a substantial single crystal, i.e., a crystalline material that displays long range ordering. It should, however, be appreciated that a “monocrystalline” material may not be a perfect single crystal but may comprise various defects, stacking faults, atomic substitutions, and the like, as long as the “monocrystalline” material exhibits long range ordering. 
     As used herein, the term “non-monocrystalline” may refer to a material that does not comprise a substantial single crystal, i.e., a material which displays either short range ordering or no ordering of the crystalline structure. Non-monocrystalline materials may comprise polycrystalline materials which may display short range ordering and amorphous materials which may display substantially no ordering of the crystalline structure. 
     As used herein, the term “chemical vapor deposition” can refer to any process wherein a substrate is exposed to one or more volatile precursors, which react and/or decompose on a substrate surface to produce a desired deposition. 
     As used herein, the term “film” and/or “layer” can refer to any continuous or non-continuous structures and material, such as material deposited by the methods disclosed herein. For example, film and/or layer can include two-dimensional materials, three-dimensional materials, nanoparticles or even partial or full molecular layers or partial or full atomic layers or clusters of atoms and/or molecules. A film or layer may comprise material or a layer with pinholes, which may be at least partially continuous. 
     As used herein, a “structure” can include a substrate as described herein. Structures can include one or more layers overlying the substrate, such as one or more layers formed according to a method as described herein. 
     Further, in this disclosure, any two numbers of a variable can constitute a workable range of the variable, and any ranges indicated may include or exclude the endpoints. Additionally, any values of variables indicated (regardless of whether they are indicated with “about” or not) may refer to precise values or approximate values and include equivalents, and may refer to average, median, representative, majority, or the like. Further, in this disclosure, the terms “include,” “including,” “constituted by” and “having” can refer independently to “typically or broadly comprising,” “comprising,” “consisting essentially of,” or “consisting of” in some embodiments. In this disclosure, any defined meanings do not necessarily exclude ordinary and customary meanings in some embodiments. 
     A selective deposition process as described herein can involve a greater amount of material remaining on a first surface relative to a second surface. For example, a selective process may result in a greater amount of the n-type doped material remaining in a first area formed over monocrystalline material relative to any n-type doped material remaining in a second area over non-monocrystalline material. In some embodiments of the disclosure, a selectivity of a process can be expressed as a ratio of material remaining on the first surface relative to the amount of material formed on the first and second surfaces combined. For example, if 10 nm of n-type doped material remains in the first area and 1 nm of n-type doped material remains in the second area, the selective deposition process will be considered to have 91% selectivity. In some embodiments, the selectivity of the methods disclosed herein may be greater than 80%, greater than 90%, greater than 95%, greater than 99.5%, greater than 98%, greater than 99%, or even about 100%. 
     Turning now to the figures,  FIG.  1    illustrates a method  100  for selectively forming n-type doped material on a surface of a substrate.  FIGS.  2 - 5    illustrate structures  200 ,  300 ,  400 , and  500  that can correspond to steps of method  100 . 
     Method  100  includes the steps of providing a substrate within a reaction chamber (step  102 ), depositing an n-type doped semiconductor material (step  104 ), and depositing a semiconductor material (step  106 ). In the illustrated example, method  100  also includes selectively removing a portion of the n-type doped semiconductor material (step  108 ). 
     Step  102  can include providing a substrate, comprising a surface comprising a first area comprising a first material and a second area comprising a second material, within a reaction chamber. With reference to  FIG.  2   , a structure/substrate  200  can include a first area  206  comprising a first material  202  and a second area  208  comprising a second material  204 . First material  202  can include a monocrystalline surface  210 ; second material  204  can include a non-monocrystalline surface  212 , such as a polycrystalline surface or an amorphous surface. First material  202  and monocrystalline surface  210  may comprise a Group IV semiconductor material, such as, for example, one or more of: silicon (Si), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), germanium (Ge), or the like. Second material  204  and non-monocrystalline surface  212  can include dielectric material, such as, for example, an oxide, an oxynitride, or a nitride, including, for example, a silicon oxide, a silicon nitride, and/or a silicon oxynitride. 
     As a non-limiting example, a reaction chamber suitable for step  102  can include a reaction chamber of a chemical vapor deposition system. However, it is also contemplated that other reaction chambers and alternative chemical vapor deposition systems may also be utilized to perform the embodiments of the present disclosure. The reaction chamber can be a stand-alone reaction chamber or part of a cluster tool. 
     Step  102  can include heating the substrate to a desired deposition temperature (e.g., for step  104 ) within the reaction chamber. In some embodiments of the disclosure, step  102  includes heating the substrate (or a susceptor holding the substrate) to a temperature of less than 700° C., less than 600° C., less than 550° C., less than 525° C., less than 500° C., or less than 475° C. For example, in some embodiments of the disclosure, heating the substrate to a deposition temperature may comprise heating the substrate to a temperature between approximately 400° C. and approximately 600° C. 
     In addition to controlling the temperature of the substrate, a pressure within the reaction chamber may also be regulated. For example, in some embodiments of the disclosure, a pressure within the reaction chamber during step  102  may be less than 200 Torr, or less than 100 Torr, or less than 50 Torr, or less than 25 Torr, or even less than 10 Torr. In some embodiments, a pressure in the reaction chamber may be between 10 Torr and 100 Torr. 
     With reference to  FIG.  1    and  FIG.  3   , during step  104 , n-type doped semiconductor material is deposited overlying the surface of the substrate to form structure  300 . The n-type doped semiconductor material can epitaxially form as doped monocrystalline material  302  overlying first area  206  and as doped non-monocrystalline material  304  overlying the second area  208 . Doped monocrystalline material  302  can include a monocrystalline surface  306 . Non-monocrystalline material  304  can include a non-monocrystalline surface  308 . The n-type doped semiconductor material can be epitaxially grown in a single step—i.e., without using a cyclical deposition and etch process. 
     During step  104 , semiconductor precursor—e.g., a Group IV semiconductor precursor and an n-type dopant (e.g., phosphorus, arsenic, and/or antimony) precursor are flowed into the reaction chamber—e.g., through one or more gas injectors, such as multi-port injectors (MPIs) including a plurality of individual port injectors for providing a gas mixture into the reaction chamber. Various combinations of the precursors can be supplied to one or more of the individual port injectors to fine tune concentration profiles as desired. Step  104  can include coflowing or alternately flowing multiple dopant sources. Further, one or more dopant precursors can be coflowed or alternately flowed with one or more Group IV precursors. 
     In some embodiments, a single Group IV precursor may be utilized during the deposition process; for example, a single Group IV precursor may be utilized when the Group IV semiconductor to be deposited comprises silicon (Si) or germanium (Ge). In some embodiments, two or more Group IV precursors may be utilized during the deposition process; for example, two or more Group IV precursors may be utilized when the Group IV semiconductor to be deposited comprises a Group IV semiconductor alloy including, but not limited to, silicon germanium, silicon germanium carbide (Si 1-x-y Ge x C y ), germanium tin (Ge 1-x Sn x ), germanium silicon tin (Ge 1-x-y Si x Sn y ), germanium silicon tin carbide (Ge 1-x-y Si x Sn y C x ), silicon tin (Si 1-x Sn x ), silicon tin carbide (Si 1-x-y Sn x C y ), or silicon carbide (Si 1-x C x ). 
     Exemplary silicon precursors include one or more hydrogenated and/or halide silicon precursors, such as those selected from the group comprising: silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), tetrasilane (Si 4 H 10 ), diiodosilane (SiI 2 H 2 ), triiodosilane (SiI 3 H), the like, or any other suitable silicon-containing precursor—e.g., such as those that can be used at low temperature, without significant reduction of the growth rate. 
     Exemplary germanium precursors include one or more of germane (GeH 4 ), digermane (Ge 2 H 6 ), trigermane (Ge 3 H 8 ), and germylsilane (GeH 6 Si). 
     Exemplary tin precursors include tin tetrachloride (SnCl 4 ) and tin deuteride (SnD 4 ). 
     Exemplary n-type dopant precursors include Group V dopant precursors comprising one or more of P, As and Sb. Exemplary n-type dopant precursors include Group V dopant precursors comprising H and one of P, As or Sb. Exemplary n-type dopant precursors include Group V dopant precursors comprising halide, such as CI, Br or I, and one of P, As or Sb. Exemplary n-type dopant precursors include Group V dopant precursors, such as, for example, phosphine (PH 3 ), phosphorus trichloride (PCl 3 ), phosphorus tribromide (PBr 3 ), phosphorus triiodide (PI 3 ), arsine (AsH 3 ), arsenic tribromide (AsBr 3 ), arsenic triiodide (AsI 3 ), antimony trichloride (SbCl 3 ), antimony pentachloride (SbCl 5 ), stibine (SbH 3 ), deuterated stibine (SbD 3 ), the like or mixtures or derivatives thereof, or any other suitable precursor containing a Group V element. In some embodiments, the n-type dopant precursor may be provided in diluted form and the diluted form may comprise approximately 1% to approximately 20% dopant precursor in a carrier gas. 
     A temperature and pressure within the reaction chamber can be the same or similar to the temperature and pressure within the reaction chamber during step  102 . 
     A thickness of n-type doped semiconductor material formed during step  104  in area  206  and/or area  208  can be between about 1 nm and about 50 nm, between about 5 nm and about 30 nm, or between about 7 nm and about 10 nm. A concentration of one or more n-type dopants in the n-type doped semiconductor material can be greater than 0.3 at-%, greater than 2 at-%, greater than 3 at-%, greater than 4 at-%, greater than 5 at-%, greater than 6 at-%, greater than 7 at-%, greater than 8 at-%, and/or less than 20 at-%, less than 15 at-%, or less than 10 at-%. 
     With reference to  FIGS.  1  and  4   , during step  106 , semiconductor material  406  is deposited overlying the n-type doped semiconductor material formed during step  104 . Semiconductor material  406  can include intrinsically-doped Group IV semiconductor material. Or, any extrinsic doping can be less than 1×10 17 . 
     As illustrated, structure  400  can include a monocrystalline material  402  overlying the first area  206  and non-monocrystalline material  404  formed overlying second area  208 . A thickness of semiconductor material  406  over area  206  and/or  208  formed during step  106  can be between about 1 nm and about 10 nm, between about 2 nm and about 8 nm, or between about 3 nm and about 6 nm. 
     Step  106  can be performed in the same reaction chamber used during step  104 . Alternatively, step  106  can be performed in another reaction chamber, such as another reaction chamber in the same cluster tool as the reaction chamber used during step  104 . A pressure and temperature within the reaction chamber can be the same or similar to the temperature and pressure described above in connection with steps  102  and  104 . 
     During step  108 , an etch is performed to remove monocrystalline material  402  overlying doped monocrystalline material  302 , non-monocrystalline material  404  overlying non-monocrystalline material  304 , and non-monocrystalline material  304  to form structure  500 , illustrated in  FIG.  5   . 
     A halide gas can be used to etch materials during step  108 . By way of examples, a gas including an etchant, such as one or more of Cl 2 , Br 2 , HCl, HBr, I 2 , HF, or the like can be used during step  108 . The gas can additionally include a diluent, such as one or more of nitrogen, argon, and/or helium. By way of one example, the gas can include a chlorine-containing gas, such as chlorine, and a diluent, such as nitrogen. 
     Step  108  can be performed in the same reaction chamber used during step  106 . Alternatively, step  108  can be performed in another reaction chamber, such as another reaction chamber in the same cluster tool as the reaction chamber used during step  106 . A pressure within the reaction chamber can be the same or similar to the pressure described above in connection with steps  102  and  104 . A temperature within the reaction chamber can be about 400° C. to about 600° C. 
     During step  108 , non-monocrystalline material  404  and non-monocrystalline material  304  can exhibit a much greater etch rate compared to monocrystalline material  402 . For example, the etch rate of non-monocrystalline material  404  can be greater than 2 or greater than 5 times an etch rate of monocrystalline material  402 . As a result, non-monocrystalline material  404  and non-monocrystalline material  304  are etched quickly, while doped monocrystalline material  302  is protected or shielded from the etch process by monocrystalline material  402 . 
       FIG.  5    illustrates structure  500  after the selective removal of non-monocrystalline material  404 , non-monocrystalline material  304 , and then monocrystalline material  402 . In accordance with at least one embodiment of the disclosure, each of non-monocrystalline material  404 , non-monocrystalline material  304 , and monocrystalline material  402  can be removed in a single etch step using the same etchant. 
     Although not separately illustrated, method  100  can additionally include a preclean step. The preclean step can include a process to remove any oxides and/or other contaminants on a surface prior to forming the n-type doped material on the surface. The preclean step may incorporate flow of chemicals and sublimation. Additionally or alternatively, the preclean step can include flow nitrogen trifluoride (NF 3 ) and ammonia (NH 3 ) with remote plasma to form activated species. The preclean step may take place at a temperature range between 500° C. and 800° C., between 550° C. and 700° C., or between 600° C. and 650° C. In other embodiments, the preclean step may take place at a temperature range between 20° C. and 500° C., between 50° C. and 300° C., or between 100° C. and 250° C. 
       FIG.  6    illustrates a device  600  in accordance with at least one embodiment of the disclosure. Device  600  includes a fin  610 , a shallow trench isolation (STI) layer  620 , a contact layer  630 , and a gate  640 . Fin  610  may include a stack of lateral nanowires including, for example, at least one of: silicon, germanium, silicon germanium, or combinations thereof. STI layer  620  can include a dielectric material, such as silicon oxide, silicon oxynitride, silicon oxycarbon, or any combination thereof, for example. Gate  640  may also comprise an oxide material, such as hafnium oxide or aluminum oxide, for example. 
     Contact layer  630  can include an n-type doped material, such as silicon phosphine (SiP), silicon arsenide (SiAs), silicon antimonide (SiSb), or the like, which can be formed according to method  100 . Contact layer  630  can be grown with a particular crystallographic orientation, such as a ( 111 ) direction in accordance with the Miller indices notation. Contact layer  630  can be used to form a source and/or drain region of device  600 . 
       FIG.  7    illustrates a system  700  in accordance with yet additional exemplary embodiments of the disclosure. System  700  can be used to perform a method as described herein and/or to form a structure, device, or portion thereof as described herein. 
     In the illustrated example, system  700  includes an optional substrate handling system  702 , one or more reaction chambers  704 , a gas injection system  706 , and optionally a wall  708  disposed between reaction chamber(s)  704  and substrate handling system  702 . System  700  can also include a first gas source  710 , a second gas source  712 , a third gas source  714 , a fourth gas source  716 , an exhaust source  726 , and a controller  728 . 
     Although illustrated with four gas sources  710 - 716 , system  700  can include any suitable number of gas sources. One or more of gas sources  710 - 716  can include, for example, a precursor gas, such as Group IV precursor(s) and/or n-type dopant precursor(s), as described above, including mixtures of such precursors and/or mixtures of one or more precursors with a carrier gas, such as nitrogen, argon, helium or the like. Additionally or alternatively, one of gas sources  710 - 716  or another gas source can include an etchant, such as a halide, such as the one or more etchants as described above. One or more gas sources  710 - 716  can also include an inert gas. Gas sources  710 - 716  can be coupled to reaction chamber  704  via lines  718 - 724 , which can each include flow controllers, valves, heaters, and the like. 
     System  700  can include any suitable number of reaction chambers  704  and substrate handling systems  702 . Further, one or more reaction chambers  704  can be or include a cross-flow, cold wall epitaxial reaction chamber. 
     Exhaust source  726  can include one or more vacuum pumps. 
     Controller  728  can be configured to perform various functions and/or steps as described herein. Controller  728  can include one or more microprocessors, memory elements, and/or switching elements to perform the various functions. Although illustrated as a single unit, controller  728  can alternatively comprise multiple devices. By way of examples, controller  728  can be used to control gas flow (e.g., by monitoring flow rates of precursors and/or other gases from sources  710 - 716  and/or controlling valves, motors, heaters, and the like). Further, when system  700  includes two or more reaction chambers, the two or more reaction chambers can be coupled to the same/shared controller. 
     During operation of reactor system  700 , substrates, such as semiconductor wafers (not illustrated), are transferred from, e.g., substrate handling system  702  to reaction chamber  704 . Once substrate(s) are transferred to reaction chamber  704 , one or more gases from gas sources  710 - 716 , such as precursors, dopants, carrier gases, etchants, and/or purge gases, are introduced into reaction chamber  704  via gas injection system  706 . Gas injection system  706  can be used to meter and control gas flow of one or more gases (e.g., from one or more gas sources  710 - 716 ) during substrate processing and to provide desired flows of such gas(es) to multiple sites within reaction chamber  704 . 
     It is to be understood that the configurations and/or approaches described herein are exemplary in nature, and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various acts illustrated may be performed in the sequence illustrated, in other sequences, or omitted in some cases. 
     The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems, and configurations, and other features, functions, acts, and/or properties disclosed herein, as well as any and all equivalents thereof.