Patent Publication Number: US-11398200-B2

Title: Display device

Description:
BACKGROUND OF THE INVENTION 
     Technical Field 
     This disclosure relates to a display device, and more particularly to a display device capable of improving a vertical crosstalk problem. 
     Related Art 
     With the advancement of technology, flat panel displays (more particularly liquid crystal display devices) have been widely used in various fields, and thus have the superior features including the thin body, the low power consumption and the radiationless property, gradually replaced the conventional Cathode Radial Tube display devices, and applied to various electronic products, such as mobile phones, portable multimedia devices, notebook computers, liquid crystal televisions, liquid crystal screens and the like. 
     A liquid crystal display device mainly utilizes an electric field to control rotations of liquid crystal molecules to make light rays penetrate through the liquid crystal molecules to display an image. A pixel includes four colors of sub-pixels arranged in, for example, WRGB, and thus has the advantage of the high transmittance. At present, the liquid crystal display device has been accepted in the market, and various manufacturers have started to develop this new technology on this basis. With the continuous increases in the Pixel Per Inch and the scan frequency of the display and in order to decrease the number of the source drive ICs, there are many products each having the pixel arrangement modified from the vertical arrangement of one gate line collocating with one data line (1G1D) into half source driving (HSD) of two gate lines collocating with one data line. The HSD technology can decrease the number of the source drive ICs as well as advantageously increase the production capacity. 
     In addition, in order to increase the aperture ratio and the view angle, the current product tends to use the 4-domain two-pixel rendering technology, wherein the combination of two sub-pixels is utilized and different voltages are used to control different orientations of liquid crystals to render one dark and one bright (two) sub-pixels. In addition, in order to make the display frame become more uniform, the prior art also utilizes the checkerboard pattern arrangement of the 4-domain sub-pixels of the dark area and the 4-domain sub-pixels of the bright area include the design method of two different polarities (positive and negative polarities) in the overall display to decrease the flicker of the display frame. However, the maximum problem of this pixel design is that the same colors of sub-pixels cannot mutually offset in one frame time due to the parasitic capacitance coupling, so that the vertical crosstalk of the display frame is induced, and the frame taste is deteriorated. 
     SUMMARY 
     In view of the deficiencies of the prior art, the inventor has obtained this disclosure after the research and development have been made. An objective of this disclosure is to provide a display device capable of improving a vertical crosstalk problem. 
     To achieve the above objective, the present disclosure discloses a display device. The display device comprises a display pane. The display panel comprises a plurality of gate line sets, a plurality of data lines, a plurality of pixels, and a drive circuit. The plurality of data lines are interleaved with the plurality of gate line sets, and the plurality of data lines comprise an n th  data line and an (n+1) th  data line, where n is an odd number. The plurality of pixels are arranged in a row direction and a column direction, wherein each of the pixels comprises a plurality of colors of sub-pixels arranged in the row direction. The plurality of sub-pixels arranged in the row direction are electrically connected to the gate line set of the corresponding row. Each of the data lines is electrically connected to the two adjacent sub-pixels of the same pixel. Each of the gate line sets sequentially has a first gate line and a second gate line. The first gate line is electrically connected to one of odd-numbered and even-numbered ones of the sub-pixels of the pixels of the same row. The second gate line is electrically connected to the other one of the odd-numbered and even-numbered ones of sub-pixels of the pixels of the same row. The drive circuit transmits a data signal to drive the plurality of pixels through the plurality of data lines. In one frame time, the data signal drives the two adjacent sub-pixels of the same pixel through the n th  data line or the (n+1) th  data line using opposite polarities, the data signal drives the same pixel through the n th  data line and the (n+1) th  data line using opposite polarities, and the data signal drives the column-direction adjacent two sub-pixels through the n th  data line and the (n+1) th  data line using opposite polarities. 
     In one embodiment, the plurality of gate line sets and the plurality of data lines are interleaved and respectively electrically connected to the plurality of pixels. 
     In one embodiment, the drive circuit comprises a scan driving unit and a data driving unit, the scan driving unit is coupled to the plurality of pixels through the plurality of gate line sets, and the data driving unit is coupled to the plurality of pixels through the plurality of data lines. 
     In one embodiment, each of the pixels is electrically connected to two of the data lines. 
     In one embodiment, a plurality of colors of the sub-pixels of each of the pixels of the same row have the same order. 
     In one embodiment, the n th  data line and the (n+1) th  data line are connected to the same pixel. 
     In one embodiment, the pixel comprises a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in order, the first sub-pixel and the second sub-pixel are electrically connected to a corresponding one of the n th  data line and the (n+1) th  data line, the third sub-pixel and the fourth sub-pixel are electrically connected to the other corresponding one of the n th  data line and the (n+1) th  data line. 
     In one embodiment, in one frame time, the two adjacent sub-pixels of the same pixel connected to the n th  data line and the (n+1) th  data line have the same polarity. 
     In one embodiment, two adjacent ones of the pixels arranged in the column direction form a pixel set, and in each of the pixel sets, two of the sub-pixels arranged in the column direction have different colors. 
     In one embodiment, each of the pixels comprises four colors of sub-pixels arranged in the row direction. 
     In one embodiment, the four colors of sub-pixels are respectively WRGB, RGBY or RGBC, where W denotes white, R denotes red, G denotes green, B denotes blue, Y denotes yellow, and C denotes cyan. 
     In one embodiment, a plurality of colors of sub-pixels of two of the pixels in adjacent two rows and arranged in the column direction have the same order. 
     In one embodiment, a plurality of colors of sub-pixels of two of the pixels in adjacent two rows and arranged in the column direction have different orders. 
     In one embodiment, in one frame time, polarity orders of the sub-pixels driven by the data signal through the n th  data line in the column direction are negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive and negative, and the orders are respectively repeated; polarity orders of the sub-pixels driven by the data signal through the (n+1) th  data line in the column direction are positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative and positive, and the orders are respectively repeated. 
     In one embodiment, the colors of the sub-pixels connected to the n th  data line are sequentially WRBWBWWRWBRWRWW, and the order is repeated; and the colors of the sub-pixels connected to the (n+1) th  data line are sequentially GBRGRGGBGRBGBGGR, and the order is repeated, where W denotes white, R denotes red, G denotes green, and B denotes blue. 
     In one embodiment, the plurality of sub-pixels of each of the pixels of the same row render the same voltage polarity order. 
     In one embodiment, adjacent two of the sub-pixels arranged in the column direction render opposite voltage polarities. 
     In one embodiment, in a next frame time, the plurality of data lines transmit the data signal in a polarity inversion mode to drive the plurality of pixels. 
     In one embodiment, in one frame time, the drive circuit makes one pixel of column-adjacent two of the pixels become a bright area, and makes the other one pixel of column-adjacent two of the pixels become a dark area, wherein the same color of bright area sub-pixels arranged in the column direction render a positive-to-negative polarity ratio of 1:1. 
     To achieve the above objective, the present disclosure further discloses a display device. The display device comprises a display panel. The display panel comprises a plurality of gate line sets, a plurality of data lines, a plurality of pixels, and a drive circuit. The plurality of data lines are interleaved with the plurality of gate line sets, wherein the plurality of data lines comprise an n th  data line and an (n+1) th  data line, where n is an odd number. The plurality of pixels are arranged in a row direction and a column direction, wherein each of the pixels comprises four colors of sub-pixels arranged in the row direction. Four colors of the sub-pixels of each of the pixels of the same row have the same order. The plurality of sub-pixels arranged in the row direction are respectively electrically connected to the gate line set of the corresponding row. Each of the data lines is electrically connected to two adjacent sub-pixels of the same pixel. Each of gate lines of the gate line sets sequentially has a first gate line and a second gate line. The first gate line is electrically connected to one of odd-numbered and even-numbered ones of the sub-pixels of the pixels of the same row. The second gate line is electrically connected to the other one of the odd-numbered and even-numbered ones of sub-pixels of the pixels of the same row. The drive circuit transmits a data signal to drive the plurality of pixels through the plurality of data lines. In one frame time, the data signal drives the two adjacent sub-pixels of the same pixel through the n th  data line or the (n+1) th  data line using opposite polarities, the data signal drives the same pixel through the n th  data line and the (n+1) th  data line using opposite polarities, the data signal drives the column-direction adjacent two sub-pixels through the n th  data line and the (n+1) th  data line using opposite polarities, the drive circuit makes one pixel of column-adjacent two of the pixels become a bright area, and makes the other one pixel of column-adjacent two of the pixels become a dark area, and the same color of bright area sub-pixels arranged in the column direction render a positive-to-negative polarity ratio of 1:1. 
     As mentioned above, this disclosure discloses a new pixel drive arrangement method, wherein under the connection architecture of the plurality of colors of sub-pixels and the half source driving technology, the same color of bright area sub-pixels arranged in the column direction (vertical direction) in one frame time may render a positive-to-negative polarity ratio of 1:1, and the positive and negative polarities mutually offset to eliminate the vertical crosstalk problem of the display panel caused by the parasitic capacitance coupling, so that the display frame becomes more uniform and the frame taste is enhanced. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of embodiments of the present application, which constitutes a part of the specification, illustrate embodiments of the present disclosure is used, together and explain the principles of the present disclosure with the description. Apparently, the drawings in the following description are only some embodiments of the present disclosure, those of ordinary skill in the art is concerned, without any creative effort, and may also obtain other drawings based on these drawings. In the following drawings: 
         FIG. 1  is a functional block diagram showing a display device of an embodiment of this disclosure; 
         FIGS. 2A and 2B  are schematic views respectively showing connections of pixels of the display panel with gate lines and data lines in an embodiment of this disclosure; 
         FIG. 3  is a schematic view showing waveforms of the data signal corresponding to the gate line in one frame time in the connection architecture of the sub-pixel with the gate line and the data line of  FIG. 2B ; and 
         FIGS. 4A to 4D  are schematic views respectively showing manufacturing processes of four color filter layers of the display device of an embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Specific structural and functional details disclosed herein are merely representative and are for purposes of describing example embodiments of the present disclosure. However, the present disclosure may be embodied in many alternate forms, and should not be interpreted as being limited to the embodiments set forth herein. 
     In the description of the present disclosure, it is to be understood that the term “center”, “lateral”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer” and other indicated orientation or positional relationships are based on the location or position relationship shown in the drawings, and are for convenience of description of the present disclosure only and to simplify the description, and not indicate or imply that refers to devices or elements must have a specific orientation, the orientation of a particular configuration and operation, therefore, cannot be construed as limiting the present disclosure. In addition, the terms “first”, “second” are used to indicate or imply relative importance or the number of technical features specified implicitly indicated the purpose of description and should not be understood. Thus, there is defined “first”, “second” features may be explicitly or implicitly include one or more of the features. In the description of the present disclosure, unless otherwise specified, the meaning of “more” is two or more. Further, the term “comprising” and any variations thereof are intended to cover non-exclusive inclusion. 
     In the description of the present disclosure, it is noted that, unless otherwise expressly specified or limited, the terms “mounted,” “connected to”, “connected” are to be broadly understood, for example, may be a fixed connection, may be a detachable connection, or integrally connected; may be a mechanical connector may be electrically connected; may be directly connected, can also be connected indirectly through intervening structures, it may be in communication the interior of the two elements. Those of ordinary skill in the art, be appreciated that the specific circumstances of the specific meanings in the present disclosure. 
     The terminology used herein is for describing particular embodiments only and is not intended to limit embodiments to an exemplary embodiment. Unless the context clearly indicates otherwise, singular forms as used herein, “a”, “an” are intended to include the plural. It should also be understood that, as used herein the term “comprising” and/or “comprising,” as used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or combinations thereof. 
     This disclosure will be further described in detail with reference to the accompanying drawings and specific embodiments below. 
       FIG. 1  is a functional block diagram showing a display device of an embodiment of this disclosure. Referring to  FIG. 1 , a display device  1  of this embodiment is a liquid crystal display device, and may include a display panel  11  and a drive circuit  12 . The display panel  11  includes a plurality of pixels arranged in a row direction and a column direction, a plurality of gate line sets (or referred to as gate lines G 1 , G 2 , . . . ) and a plurality of data lines (or referred to as source lines D 1 , D 2 , D 3 , . . . ). The plurality of gate line sets and the plurality of data lines are interleaved and respectively electrically connected to the plurality of pixels. Each pixel may include a plurality of colors of sub-pixels arranged in the row direction. 
     The drive circuit  12  is electrically connected to the display panel  11 , and may drive the plurality of pixels of the display panel  11  to display an image. The drive circuit  12  of this embodiment may include a scan driving unit  121 , a data driving unit  122  and a timing control unit  123 . The scan driving unit  121  may be coupled to the plurality of pixels through the gate lines, and the data driving unit  122  may be coupled to the plurality of pixels through the data lines. The scan driving unit  121  may respectively output scan signals to turn on the gate lines, and the data driving unit  122  may output a plurality of data signals corresponding to the data lines to drive the corresponding pixels. In addition, the timing control unit  123  may transmit a vertical sync signal and a horizontal sync signal to the scan driving unit  121 , convert the video signal received from the external port into the data signal used by the data driving unit  122  and transmit the data signal and the horizontal sync signal to the data driving unit  122 . In one frame time, when the gate lines are respectively and sequentially turned on by the scan signals, the data driving unit  122  may transmit the data signals corresponding to each row of sub-pixels to each sub-pixel through the data lines, so that the display panel  11  displays the image. 
       FIGS. 2A and 2B  are schematic views respectively showing connections of pixels of the display panel with gate lines and data lines in an embodiment of this disclosure. Please refer to  FIGS. 2A and 2B .  FIGS. 2A and 2B  show the same connection architecture. However,  FIG. 2B  also shows the bright and dark conditions of the sub-pixels of each pixel (the sub-pixels rendered in dashed lines are dark areas). In  FIGS. 2A and 2B , 16 gate lines G 1  to G 16 , 4 data lines D 1  to D 4  and 8 rows (transverse) of total 16 pixels (64 sub-pixels P) are taken as an example, but this disclosure is not restricted thereto. In different embodiment, more gate lines, data lines and pixels may be designed according to actual requirements. 
     In  FIG. 2A , the 16 gate lines G 1  to G 16  may be divided into eight gate line sets (surrounded by the dashed lines), wherein each set has two gate lines, that is, (G 1 , G 2 ), (G 3 , G 4 ) to (G 15 , G 16 ), and the 4 data lines D 1  to D 4  are respectively represented by D 1  to D 4 . The display panel  11  has a plurality of pixels arranged in the row direction (horizontal direction) and the column direction (vertical direction). Each pixel has a plurality of sub-pixels P arranged in the row direction. The plurality of sub-pixels P arranged in the row direction are respectively electrically connected to the gate line set of the corresponding row, and each of the data lines is respectively electrically connected to the two adjacent sub-pixels P of the same pixel. Specifically speaking, for example, the gate line set (G 1 , G 2 ) may simultaneously drive two pixels of the first row (each pixel includes four sub-pixels P of white (W), red (R), green (G) and blue (B). The gate line set (G 3 , G 4 ) may simultaneously drive two pixels of the second row, and the data lines D 1 , D 2 , D 3  and D 4  are respectively electrically connected to the two adjacent sub-pixels P of the same pixel. That is, each pixel is electrically connected to two data lines, respectively. Similarly, as shown in  FIG. 2A , each of the data lines is connected to the two adjacent sub-pixels P of the same pixel. Therefore, the display device  1  of this embodiment adopts the half source driving (HSD) technology. In addition to reducing of the number of the source driver ICs, it is also advantageous to the improvement of the production capacity. 
     Each pixel of this embodiment includes four colors (WRGB) of sub-pixels P arranged in the row direction, and the four colors of sub-pixels P of each pixel of the same row have the same order, but four colors of sub-pixels P of two pixels in adjacent two rows and arranged in the column direction have the same order or different orders. However, this disclosure is not restricted thereto. In addition, in adjacent two data lines connected to the same pixel: the n th  data line and the (n+1) th  data line are represented by D(n) and D(n+1) (n is an odd number), the colors of the sub-pixels P connected to the data line D(n) from top to bottom are sequentially WRBWBWWRWBRWRWWB, and the order is repeated; and the colors of the sub-pixels P connected to the data line D(n+1) from top to bottom are sequentially GBRGRGGBGRBGBGGR, and the order is repeated. 
     In addition, two adjacent pixels arranged in the column direction may form a pixel set T (surrounded by the dashed lines), wherein in each pixel set T, two sub-pixels P arranged in the column direction have different colors, but two adjacent sub-pixels P of two different pixel sets T may have the same color or different colors. Taking the pixel set in the upper left corner (labeled as T 1 ) as an example, the sub-pixels P of the pixel in the upper half portion sequentially have a WRGB stripe arrangement, and the sub-pixels P of the pixel in the lower half portion sequentially have a BWRG arrangement. The four sub-pixels P in the upper half portion are respectively electrically connected to the same set of gate lines G 1  and G 2  of the corresponding row and the two adjacent data lines D 1  and D 2  of the corresponding column, and the four sub-pixels P in the lower half portion are respectively electrically connected to the same set of gate lines G 3  and G 4  of the corresponding row and the corresponding two adjacent data lines D 1  and D 2 . The color of each pixel above takes the WRGB as an example, but it is not restricted thereto. In different embodiments, different four colors are also possible, such as RGBY, RGBC or others, and this disclosure is not restricted thereto. 
     In addition, in this embodiment, each set of gate lines may sequentially have two gate lines, referred to as a first gate line and a second gate line. The first gate line may be respectively electrically connected to one of odd-numbered and even-numbered ones of the sub-pixels P of the same row of pixels (odd and even numbers are counted from left to right), and the second gate line may be respectively electrically connected to one of odd-numbered and even-numbered ones of the sub-pixels P of the same row of pixels. In this embodiment, the gate lines of the odd-numbered rows are in charge of connecting and driving of the odd-numbered sub-pixels P of the same row, and the gate lines of the even-numbered rows are in charge of connecting and driving of the even-numbered sub-pixels P of the same row (or vice versa). Again, taking the gate lines G 1  and G 2  as an example, the gate line G 1  of this embodiment is respectively electrically connected to the 1 st , 3 rd , 5 th  and 7 th  sub-pixels P among the plurality of pixels in the same row, and the gate line G 2  is respectively electrically connected to the 2 nd , 4 th , 6 th  and 8 th  sub-pixels P among the plurality of pixels in the same row. Similarly, the gate line G 3  is respectively electrically connected to the 1 st , 3 rd , 5 th , and 7 th  sub-pixels P among the plurality of pixels in the same row, and the gate line G 4  is respectively electrically connected to the 2 nd , 4 th , 6 th  and 8 th  sub-pixels P among the plurality of pixels in the same row, and so on. 
     In addition, each pixel may include a first sub-pixel P, a second sub-pixel P, a third sub-pixel P and a fourth sub-pixel P arranged in order, the first sub-pixel P and the second sub-pixel P in each pixel are electrically connected to a corresponding one of the n th  data line and the (n+1) th  data line, the third sub-pixel P and the fourth sub-pixel P are electrically connected to the other corresponding one of the n th  data line and the (n+1) th  data line (the first to fourth ones are also counted from left to right). In this embodiment, taking the data lines D 1 (D 3 ) and D 2 (D 4 ) as an example, the data line D 1 (D 3 ) is electrically connected to the first sub-pixel P and the second sub-pixel P of each pixel in the vertical direction, and the data line D 2 (D 4 ) is electrically connected to the third sub-pixel P and the fourth sub-pixel P of each pixel in the vertical direction, and so on. 
     Referring to  FIGS. 2A and 2B  in conjunction with  FIG. 3 , wherein  FIG. 3  is a schematic view showing waveforms of the data signal corresponding to the gate line in one frame time in the connection architecture of the sub-pixel with the gate line and the data line of  FIG. 2B . In a driving method of the display device of this embodiment, under the above-mentioned connection architecture, the data signal is transmitted through the plurality of data lines by the driving circuit  12  to drive the plurality of pixels of the display panel  11 , wherein in one frame time, the data signal drives the two adjacent sub-pixels P of the same pixel through the n th  data line or the (n+1) th  data line using opposite polarities, the data signal drives the same pixel through the n th  data line and the (n+1) th  data line using opposite polarities (i.e., at the same time, if the n th  data line has the positive polarity, then the (n+1) th  data line has the negative polarity; or vice versa), and the data signal drives the two adjacent sub-pixels P in the column-direction through the n th  data line and the (n+1) th  data line using opposite polarities. 
     In this embodiment, as shown in  FIG. 2A , the data signal drives the two adjacent sub-pixels P of the same pixel through the n th  data line and the (n+1) th  data line that respectively includes two polarities (the positive polarity and the negative polarity), and in one frame time, polarity orders of the sub-pixels P driven by the data signal through the n th  data line in the column direction are negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive, and negative; and polarity orders of the sub-pixels P driven by the data signal through the (n+1) th  data line in the column direction are positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative and positive. In addition, in the same frame time, the polarity orders of the sub-pixels P driven through the n th  data line and the (n+1) th  data line in the column direction are respectively repeated. That is, the polarity orders of the sub-pixels P driven through the n th  data line in the column direction are repeatedly negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive and negative; and the polarity orders of the sub-pixels P driven through the (n+1) th  data line in the column direction repeat positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative and positive. Thus, in one frame time, polarities of the two adjacent sub-pixels P of the same pixel driven by the data signal through the n th  data line and the (n+1) th  data line are opposite; polarities of two sub-pixels P of the same pixel driven by the data signal through the n th  data line and the (n+1) th  data line are opposite; and polarities of two adjacent sub-pixels P in the column-direction driven by the data signal through the n th  data line and the (n+1) th  data line are also opposite. 
     Therefore, in one frame time, polarities of two adjacent sub-pixels P of the same pixel driven by the data signal and connected to the n th  data line are opposite; polarities of two adjacent sub-pixels P of the same pixel driven by the data signal and connected to the (n+1) th  data line are also opposite; and polarities of two adjacent sub-pixels P of the same pixel connected to the n th  data line and the (n+1) th  data line are the same. 
     In addition, in a next frame time, the driving polarity of the data signal employs the polarity inversion driving mode, so that the properties of liquid crystal molecules are not destroyed. In other words, in this embodiment, in a next frame time, polarity orders of the sub-pixel P in the column direction driven by the data signal through the n th  data line and the (n+1) th  data line are respectively: positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative and positive; and negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive and negative; and in the next frame time, polarity orders of the sub-pixels P in the column direction driven by the data signal through the n th  data line and the (n+1) th  data line are respectively repeatedly positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative and positive; and negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive, negative, negative, positive, positive and negative. 
     With the connection architecture and the driving method of the gate line, the data line and the sub-pixel P, as shown in  FIG. 2B , the drive circuit  12  can make each pixel set T have the following properties within one frame time: the voltage polarities rendered by the four colors of sub-pixels P of one of the pixels are respectively negative, positive, positive and negative (−++−); and the voltage polarities rendered by the plurality of colors of sub-pixels P of another one of the pixels are respectively positive, negative, negative and positive (+−−+); or vice versa. That is, the voltage polarities rendered by the plurality of colors of sub-pixels P of one of the pixels are respectively positive, negative, negative, positive (+−−+), and the voltage polarities rendered by the plurality of colors of sub-pixels P of another one of the pixels are respectively negative, positive, positive and negative (−++−). In addition, the plurality of sub-pixels P of each pixel of the same row render the same voltage polarity order, and two adjacent sub-pixels P arranged in the column direction render opposite voltage polarities. In a next frame time, the rendered voltage polarities of all sub-pixels P are opposite to those of the previous frame time. 
     In addition, in one frame time, the drive circuit  12  also makes one pixel of column-adjacent two of the pixels become a bright area, and makes the other one pixel of column-adjacent two of the pixels become a dark area. As shown in  FIG. 2B , in this embodiment, one pixel of column-adjacent two of the pixels becomes a bright area, and the other one pixel of column-adjacent two of the pixels becomes a dark area. Also, in each pixel set T, one pixel becomes a dark area, and another pixel becomes a bright area. That is, the display panel of this embodiment adopts four colors of sub-pixels and collocates with the two pixel rendering technology. 
     Therefore, as shown in  FIG. 3 , in the above-mentioned connection architecture, the same color of bright area sub-pixels arranged in the column direction P render a positive-to-negative polarity ratio of 1:1. For example, for the data line D 1 , the number of positive polarity and the number of negative polarity of the blue (B) sub-pixel P are equal to 1; the number of positive polarities and the number of negative polarities of the white (W) sub-pixel P are equal to 2; and the number of positive polarity and the number of negative polarity of the red (R) sub-pixel P are equal to 1. Again, for the data line D 2 , the number of positive polarity and the number of negative polarity of the blue (B) sub-pixel P are equal to 1; the number of positive polarities and the number of negative polarities of the green (G) sub-pixel P are equal to 2; and the number of positive polarity and the number of negative polarity of the red (R) sub-pixel P are equal to 1. The number of positive and negative polarities corresponding to other data lines D 3  and D 4  can refer to  FIG. 3 , and detailed descriptions thereof will be omitted. 
     As mentioned hereinabove, in the display device of this embodiment, a new pixel driving configuration is proposed. Under the connection architecture of the four colors of sub-pixel and the half source driving technology, the same color of bright area sub-pixels P arranged in the column direction (vertical direction) within one frame time render a positive-to-negative polarity ratio of 1:1, the positive and negative polarities are used to offset the vertical crosstalk problem of the display panel caused by the parasitic capacitance coupling, thereby making the display frame more uniform and enhancing the frame taste. 
     Please refer to  FIGS. 4A to 4D , wherein  FIGS. 4A to 4D  are schematic views respectively showing manufacturing processes of four color filter layers of the display device of an embodiment. 
     As shown in  FIG. 4A , the first manufacturing process of four color filter layers of the display device of this embodiment includes: forming a black matrix layer  112  with spaced portions on a substrate  111 , and forming the first color filter layer (such as R) by, for example, coating on the substrate  111  and the black matrix layer  112 ; then, as shown in  FIG. 4B , the second process includes: performing the exposure process by a mask  2 , wherein an opening  21  of the mask  2  corresponds to the installation position of the first color sub-pixel; then, as shown in  FIG. 4C , the third process includes: performing the development process to define the position of the first color (R) filter layer on the substrate  111 ; and after that, the first process, the second process and the third process are repeated to define the positions of four colors (R, G, B, W) filter layers on the substrate  111 , thereby obtaining the arrangement of the four colors of sub-pixels P. The black matrix layer  112  may be disposed around the four color filter layers. 
     In summary, this disclosure discloses a new pixel drive arrangement method, wherein under the connection architecture of the plurality of colors of sub-pixels and the half source driving technology, the same color of bright area sub-pixels arranged in the column direction (vertical direction) in one frame time may render a positive-to-negative polarity ratio of 1:1, and the positive and negative polarities mutually offset to eliminate the vertical crosstalk problem of the display panel caused by the parasitic capacitance coupling, so that the display frame becomes more uniform and the frame taste is enhanced. 
     Although the present disclosure has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments, will be apparent to persons skilled in the art. It is, therefore, contemplated that the appended claims will cover all modifications that fall within the true scope of the present disclosure.