Patent Publication Number: US-2023155482-A1

Title: Adaptive Electrical Power Distribution Panel

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation in Part of U.S. patent application Ser. No. 17/525,535, filed Nov. 12, 2021, which is a Continuation in Part of U.S. patent application Ser. No. 16/532,163, filed Aug. 5, 2019, which is a continuation of U.S. patent application Ser. No. 16/233,556, filed Dec. 27, 2018, which issued as U.S. Pat. No. 10,666,161 on May 26, 2020, which is a continuation of U.S. patent application Ser. No. 14/749,339, filed Jun. 24, 2015, which issued as U.S. Pat. No. 10,205,324 on Feb. 12, 2019, which is a continuation of U.S. patent application Ser. No. 14/062,884, filed Oct. 24, 2013, which issued as U.S. Pat. No. 9,735,703 on Aug. 15, 2017, which is a continuation of U.S. patent application Ser. No. 13/103,070, filed May 8, 2011, which issued as U.S. Pat. No. 8,937,822 on Jan. 20, 2015. This application is additionally a Continuation in Part of U.S. patent application Ser. No. 15/676,826, filed Aug. 14, 2017. The disclosures of each of these references are incorporated by reference herein in their entireties. 
    
    
     FIELD OF INVENTION 
     The present invention relates generally to electrical power distribution, and in particular to an adaptive electrical power distribution panel connected to a utility power grid, that automatically, selectively, individually, and dynamically disconnects one or more branch circuits, appliances, or devices from the power utility grid in response to monitored conditions. 
     BACKGROUND 
     Lower cost, high-power, efficient, DC-to-AC converters (also known as “inverters”) are of interest for solar energy economics. At the current state of the art as of the date of filing this CIP, DC-AC inverters have surpassed the photovoltaic panels in cost and have become the second highest cost item for a solar system, next to installation labor. For high efficiency and low heat dissipation, commutation of DC to produce AC preferably uses solid state switches that are either fully on or fully off, and do not dwell more than a microsecond or so in an intermediate state. Therefore it is more complicated to produce a sine wave that takes on all values between the negative peak and the positive peak. On the other hand, producing a square wave which switches between the positive peak and the negative peak produces a form of AC that is not suitable for all loads. 
     Various manufacturers provide prior art DC-AC converters, which fall into one of a few broad classes and operating modes. The class of “modified sine wave” converters maintains both the same rms and the same peak voltage as a sine wave, while still employing only on-off commutation. This is done by switching the voltage between the desired positive peak, zero and the negative peak, spending 50% of the repetition period at zero, therefore achieving both the same peak and the same rms values as a true sine wave, and being compatible with a greater variety of loads. 
     Still, there are loads that do not tolerate the modified sine wave; for example, appliances that present inductive loads, such as induction motors, some cellphone and laptop battery chargers, fluorescent lamps and tumble dryers, and any device with an internal power supply that uses capacitive reactance as a lossless voltage-dropping means, can malfunction on modified sine waveforms. Moreover, there is a potential problem with radio and TV interference due to the high level of harmonics of the modified square wave converter. Such a waveform is therefore not a candidate for coupling solar-generated power into the utility network or into house wiring. 
     “True sine wave” is another class of prior art DC-AC inverter. Linear amplifiers provide the absolute cleanest AC power waveforms, but their inefficiencies cause high heat dissipation in converters of several kilowatts capacity. Moreover, linear amplifiers lose efficiency rapidly when operating into non-unity power factor loads. Some sine wave inverters overcome the problems with linear amplifiers by using digitally-synthesized waveforms, which are multi-step approximations to a smooth sine wave. One example of a step-approximation sine wave inverter is the XANTREX (formerly Trace) SW4048. 
     U.S. Pat. No. 5,930,128, by the current Inventor, discloses a power waveform generator that expresses the sinusoidal waveform as a series of numerical samples in a number base comprising a plurality of digits; selecting corresponding digits from each numerical sample and generating therefrom a waveform corresponding to the sequence of each digit; and then using combining means to form a weighted combination of the digit-corresponding waveforms, wherein the weights are chosen in relation to the numerical significance of each digit. For example, using a ternary number base, the weighting means would add the digit waveforms in the ratios 1:1/3:1/9 and could for example be a transformer with these turns ratios. 
     U.S. Pat. No. 5,373,433 also describes using series connected, turns-ratio weighted transformer coupling of 3-level waveforms to produce a 27-level step approximation to a sine wave. The principle described therein is similar to that used in the aforementioned XANTREX SW4048 inverter. The combining means disclosed in the &#39;128 patent for combining digit-corresponding waveforms was, in a low-frequency case, a series connection of transformers having turns ratios in the ratios of corresponding numerical digits. In a high-frequency case, the combining means comprised a set of quarter wave lines having characteristic impedances in the ratios of corresponding digits. 
     In a device built in accordance with the &#39;128 patent, the series-connected transformer is the appropriate version for 60 Hz, as ¼ wavelength lines are impractical at 60 Hz. However, the transformers needed for the inventions of the &#39;128 and &#39;533 patents represent a significant fraction of the total cost and weight of medium-power converters, and also account for a few percent loss in total efficiency. Therefore, other solutions that avoid the disadvantages and pitfalls of the above prior art would be useful. In particular, a solution avoiding these low-frequency transformers would be a benefit. 
     Transformerless inverters are known in the prior art, particularly for utility-interactive inverters, using high-frequency switching or pulse width modulation to approximate a sinewave. However, a disadvantage that arises in these conceptual converters is the imposition of the high-frequency switching waveform on the solar array, which can capacitively couple through the glass cover upon touching it, potentially causing RF burn to personnel or damage to the solar panel, as well as causing the solar array to radiate substantial radio interference. Thus a design is required that can create a more benign voltage fluctuation on the solar array DC conductors. 
     Another categorization of converter relates to whether they are designed to power loads directly, or whether they are designed to feed and sell power back into the electricity grid. A load inverter that can power loads directly is said to operate in standalone mode, and is also called a “standalone inverter,” while a grid-tie inverter is said to operate in grid-interactive mode and is also called a “grid-interactive inverter.” 
     For safety and other reasons, the latter have to meet different specifications than the former, especially under fault conditions. In particular, a load inverter should be a constant voltage source, while a grid-tie inverter does not have a constant voltage output but must adapt to the voltage of the grid, and is a current source. Moreover, a load inverter is always used with battery storage, and should maintain efficiency at both light and heavy loads, and have low no-load power consumption, so that the battery is not discharged while the inverter is idling at night. Grid-tie inverters however do not have the same requirement for no-load power consumption, as they do not operate at night. 
     A complete alternative energy installation may thus comprise a number of functions, including load inverters, grid-tie inverters, load management for manually or automatically transferring load between the utility and alternative energy supplies, storage batteries, battery chargers, circuit breakers, surge protectors and other safety devices to protect equipment and wiring and eliminate the risk of electrical mishaps under conceivable fault conditions. Other than the inverters and the array, these additional components are known as “balance-of-system” components. 
     For high power grid-tie installations, typically 20 kw and above, 3-phase inverters are preferable in order to keep the gauge and cost of wiring down and to assist in maintaining balance between the three phases of the electricity grid. For converters over 100 Kw, 3-phase is often mandated by the utility company. Three phase inverters using pulse width modulation are known from the art of solid state Motor Drives, but they are not suitable for grid-interactive use for many reasons, and Motor Drives do not need or have ground leak detection on the DC bus, which is internal. 
     The total cost of balance-of-system components required in an installation can be significant; therefore it is an objective of this disclosure to describe novel designs of inverters, safety devices, and automatic load management devices that provide a more efficient and cost effective complete installation, and which achieve cost reductions in the electronics to complement the currently falling cost of photovoltaic panels. 
     In systems such as described in parent U.S. patent application Ser. Nos. 14/062,884 and 13/103,070, electrical loads may be fed with power selected from a first AC power source or a second AC power source in dependence on various considerations. Such considerations can include the state of the AC power source voltages, i.e., over or under voltage, frequency accuracy and the current or power taken by each load. Thus monitoring the power taken by each load, whichever source is feeding it, is a desired function. 
     Two electrical power sources may or may not be exactly synchronized in frequency, but even if synchronized, may not be exactly in the same phase. When it is desired to monitor the voltage, current or power from two such sources using a common monitoring device such as a microprocessor, a dilemma arises as to from which one of the sources the microprocessor should take its timing. For example, the zero-crossings of the AC voltage of the first source could be used to interrupt a microprocessor to start sampling and Digital-to-Analog converting analog electrical parameters such as voltage and current during a cycle. However, one purpose in providing two alternate electrical sources is so that the second source continues to support operations if the first source is experiencing an outage. Thus synchronizing to one source or the other does not provide a continuous synchronization suitable for accurate monitoring. Therefore a solution is needed for configuring a processor to monitor electrical parameters of multiple sources that continues to operate smoothly across outages of either source. 
     The Background section of this document is provided to place embodiments of the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Approaches described in the Background section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section. 
     SUMMARY 
     The following presents a simplified summary of the disclosure in order to provide a basic understanding to those of skill in the art. This summary is not an extensive overview of the disclosure and is not intended to identify key/critical elements of embodiments of the invention or to delineate the scope of the invention. The sole purpose of this summary is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later. 
     An adaptive electrical power distribution panel includes or is connected to a controller. The adaptive panel receives electrical power from at least a utility power grid, and optionally an alternative power source. The adaptive panel outputs electrical power to a plurality of branch circuits, appliances, or devices. The controller continuously or periodically monitors one or more conditions. The adaptive panel automatically, selectively, individually, and dynamically disconnects one or more branch circuits, appliances, or devices from the power utility grid. A selection of which one or more branch circuits, appliances, or devices to disconnect from the utility power grid is made algorithmically by the controller, in response to the monitored conditions. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. 
         FIG.  1    shows a top-level block diagram of a DC-AC load converter. 
         FIG.  2    shows a bidirectional DC-DC converter. 
         FIG.  3    shows a floating H-bridge for commutating a floating DC supply. 
         FIG.  4    shows the waveforms of four ternary digits over a repetition cycle. 
         FIG.  5    shows waveforms of the 120 volt H-bridge and on the DC supply. 
         FIG.  6    shows a common mode hash filter. 
         FIG.  7    shows details of the transient response of the common mode hash filter. 
         FIG.  8    shows an RFI filter used to suppress high frequencies on the output. 
         FIGS.  9 A and  9 B  show the difference between a correct and an erroneous RFI filter. 
         FIG.  10    shows more detail of a load inverter design according to the invention. 
         FIG.  11    shows the start-up circuit for limiting inrush current. 
         FIG.  12    shows the output sinusoidal waveform from an inventive converter. 
         FIG.  13    shows the output spectrum from the converter before RFI filtering. 
         FIG.  14    shows the converter output noise spectrum after RFI filtering. 
         FIG.  15    shows the principle of a single-phase grid intertie inverter. 
         FIG.  16    shows the principle of a 3-phase grid intertie inverter. 
         FIG.  17    shows a complete solar installation for grid-interactive use only. 
         FIG.  18    shows a complete solar installation using a standalone inverter. 
         FIG.  19    shows a bimodal solar electric installation. 
         FIG.  20 A  shows an equivalent circuit of a photovoltaic (solar) cell. 
         FIG.  20 B  shows the I-V characteristics of a solar panel. 
         FIG.  20 C  shows temperature dependence of solar panel characteristics. 
         FIGS.  21 A,  21 B, and  21 C  show the DC-DC converter waveforms for reducing standby current. 
         FIG.  22    shows the outline schematic of a smart load center. 
         FIG.  23    shows three phase waveforms. 
         FIG.  24    shows another arrangement of a 3-phase grid intertie inverter. 
         FIG.  25    shows a modified doublet and core flux waveforms. 
         FIG.  26 A  shows a vector diagram of a generator back-feeding the grid. 
         FIG.  26 B  shows the vector diagram for rectifier mode. 
         FIG.  27    shows a remote-controlled solar combiner and DC disconnect. 
         FIG.  28    shows a multi-mode inverter. 
         FIG.  29    shows source-selection switches connected to an inverter and directly to the grid. 
         FIG.  30    shows the connection of additional switching transistors. 
         FIG.  31    shows source-selection switches connected to an inverter and to the grid through a grid-isolation relay. 
         FIG.  32    shows the configuration of  FIG.  31    with an inverter having multiple first outputs for separate connection to appliance circuits. 
         FIG.  33    is a flow diagram of a method of independently, selectively supplying power to circuits from one of the grid and the inverter. 
         FIG.  34    shows a current sensing circuit using a Hall Effect sensor 
         FIG.  35    shows a software arrangement for forming sample differences on the fly. 
         FIG.  36    shows a voltage measurement circuit 
         FIG.  37    shows a general software structure 
     
    
    
     DETAILED DESCRIPTION 
     For simplicity and illustrative purposes, the present invention is described by referring mainly to an exemplary embodiment thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be readily apparent to one of ordinary skill in the art that the present invention may be practiced without limitation to these specific details. In this description, well known methods and structures have not been described in detail so as not to unnecessarily obscure the present invention. 
       FIG.  1    depicts a DC-to-AC conversion apparatus according to a first embodiment, comprising an input ( 100 ) for a floating DC power source, for example 120 volts DC from ten 12-volt rechargeable batteries connected in series; a pair of output terminals ( 150 ) for the AC output, one of which may be connected to the grounded conductor or neutral of the AC load; a bidirectional DC-DC converter ( 110 ) for converting the DC input to a number of floating DC output voltages, and a set of reversing switches  120   a - 120   d  controlled by opto-isolated driver circuit  200 . While one of a pair of single phase power conductors is normally a grounded neutral conductor, the inventive converter may alternatively provide a floating output relative to an arbitrary reference potential terminal. The bidirectional property of the DC-DC converter  110  implies that power may instantaneously flow in either direction at any pair of input or output terminals. If the current flows out of a positive terminal, the direction of power flow is “out,” while if current flows into a positive terminal, the direction of power flow is “in.” The DC-DC converter is of a substantially lossless, switching type, implying that all power that flows in must come out, although the converter may optionally contain energy storage capacitors such there may be an instantaneous imbalance between input and output power as the capacitors are accumulating or releasing energy. 
     In this example, it is assumed that the inverter output waveform to be generated is represented as a sequence of numerical samples, each numerical sample value being expressed with four digits in the ternary number system, e.g. (T4, T3, T2, T1), wherein each digit Ti (i=1 . . . 4) can only take on one of the three values: −1, 0 or +1. In correspondence with the place significance of the different ternary digits, a number of floating DC supplies are generated with ratios 1:1/3:1/9:1/27. Assuming a 120-volt DC input source, the floating DC supplies generated by converter  100  are therefore 40 v, 13.33 v and 4.44 volts, which are respectively ⅓ rd, 1/9th and 1/27th of the nominally 120 volt floating DC power source. The sum of the DC input and all outputs of the DC-DC converter is 120+40+13.33+4.44=177.77 volts. This is the peak voltage that could be generated at the AC output ( 150 ), and corresponds to a useful sine wave output voltage of 125.7 volts rms. If necessary, all the voltages can be scaled to produce other output voltages, for example 100v, 115, 120 v, 125 v, 220 v, etc., while still maintaining the power-of-3 ratios between the floating supply voltages. Other voltage outputs or waveforms (within the maximum available peak voltage of all DC supplies added together) may alternatively be generated by choosing the appropriate sequence of ternary digits. For example, the invention could be used to produce an output waveform for driving a vibration table for mechanical testing purposes, the waveform being either non-repetitive, or having a desired repetition frequency. 
     Other number systems than ternary could be used; for example, the binary number system could be used, or the quaternary number system could be used in which digits take on the values−3,−1, +1 or +3. However, ternary is of slightly lower component complexity per waveform step and is therefore the presently preferred choice. 
     Continuing to refer to  FIG.  1   , the floating DC input and the floating outputs from DC-DC converter ( 110 ) each feed respective polarity reversing switches  120   a ,  120   b ,  120   c  and  120   d . The outputs of the switches are directly connected in series to the AC output  150 , so that, by either inverting the selected polarity of each DC supply or not, or not selecting it, in accordance with a respective one of the ternary digits T4, T3, T2, T1, the series-connected output can be any of the 81 values (120T4+40T3+13.33T2+4.44T1) volts. For example, if all switches select the positive polarity, the output voltage will be 120+40+13.33+4.44=177.77 volts. If however the 4.44 volt switch is controlled to feed straight through, the output voltage will be 120+40+13.33=173.33 volts. If the 4.44 v switch is controlled to reverse the polarity, the output voltage will be 120+40+13.33-4.44=168.88 volts. By appropriate control of the switches therefore, any output voltage between −177.77 and +177.77 volts, in steps of 4.44 volts, can be produced. It is important to note that, when a DC source polarity is selected to oppose the output voltage and therefore the current flow, power is feeding backwards into the DC-DC converter, which must therefore be of a bi-directional design using for example synchronous rectifiers. 
     It is a significant advantage to arrange that the voltage corresponding to the most significant ternary digit, or from which the greatest power is drawn, comes directly from the DC input, and does not pass through the DC-DC converter, as the DC-DC converter then only has to convert the remaining fraction of the total power. Most of the AC output power then comes directly from the DC input source, which improves the total conversion efficiency. 
     In order to generate a 60 Hz step-approximation to a 125.7 volt rms sinewave, the switches are controlled to select sequentially among the 3 4 =81 possible voltage levels from −77.77 to +177.77 volts and back again, repetitively in the proper sequence and at the proper times. One cycle therefore comprises nominally 2×81 voltage steps, so that the number of level changes per second is approximately 2×81×60=9720. This is somewhat rapid for mechanical switching means such as relays, rotary commutators, or cam-actuated contacts, but is well within the capability of semiconductor switches which can operate 100 times faster than the required speed. 
       FIG.  3    depicts a full H-bridge of N-type power MOSFETs, which is the presently preferred configuration for switches  120   a - 120   d . Four N-type MOSFET power transistors labeled Tr(a), Tr(b) Tr(c), Tr(d) are connected between the DC input+ve terminal and the −ve terminal. By turning on transistors Tr(a) and Tr(d) while turning off transistors Tr(b) and Tr(c), the DC+ve input is connected to output pin  163  while DC−ve input is connected to output pin  164 . Conversely, by turning on transistors Tr(b) and Tr(c) while keeping transistors Tr(a) and Tr(d) off, the DC+ve input is connected to output terminal  164  while the DC−ve input is connected to output pin  163 . A pass-through state is created either by turning on transistors Tr(a) and Tr(c) while holding Tr(b) and Tr(d) off, which connects the DC+ve input to both output terminals  163  and  164 , or by turning on transistors Tr(b) and Tr(d) while holding Tr(a) and Tr(c) off, which connects the DC−ve input to both output terminals  163  and  164 . These two pass-through states both give zero voltage output between terminals  163  and  164 , but differ as to which polarity of the floating DC input is connected to the output terminals. Both pass-through states are used in the invention at different times. 
     A MOSFET is turned on or off by applying a positive or (negative or zero) voltage between its gate and its source terminals. Since the sources of the upper MOSFETs Tr(a) and Tr(c) of the H-bridge are connected to different ones of the H-bridge outputs, and the sources of the lower two MOSFETs Tr(b) and Tr(d) of the H-bridge are connected to the negative of the DC supply, three different relatively floating supplies are required for the gate drivers IC(a), IC(b), IC(c) and IC(d). IC(b) and IC(d) may use the same gate driver supply, but IC(a) and IC(c) create separate supplies using bootstrap diodes D 1  and D 2  to charge capacitors C 1  and C 2 , respectively. Further discussion of bootstrapping may be found in  FIG.  4    of Intersil Application Note AN9324.4 dated March 2003, by George E. Danz, the disclosure of which is incorporated herein by reference in its entirety. 
     Due to the reference potentials for the gate drivers being different, even within the same H-bridge, all gate drivers are preferably opto-isolated. A suitable opto-isolated gate driver is Fairchild part number FOD3180. An opto-isolator comprises a light-emitting diode illuminating a phototransistor. When current is passed through the light emitting diode at its input, the output will be enabled. Since it is important that TR(a) and TR(b) should never be turned on at the same time, as this would short the DC input, this is rendered impossible by connecting their gate driver input LEDs back-to-back. Likewise, the gate driver input LEDs for TR(c) and TR(d) are connected back-to-back. A control input  161  is conditioned by two inverting AND gates to produce opposite polarity output signals which connect through resistors R 3  and R 4  to the LEDs of gate drivers IC(c) and IC(d). A logic 0 at pin  161  will enable IC(d) to turn on TR(d) and switch TR(c) off. A logic 1 at pin  161  will enable IC(c) to turn on TR(c) and switch TR(d) off. A logic 0 at input pin  162  will produce logic 1&#39;s at both NAND gate outputs and thus no current will flow in either LED, turning both TR(c) and TR(d) off. The latter state is useful for fast shutdown upon fault events. 
     If the H-bridges of  FIG.  1    are controlled according to a fixed timing to generate step approximations to a sine wave, the output voltage will simply be proportional to the DC input voltage, e.g., 125.7 volts rms output for 120 volts DC input, or 104.75 volts rms output for 100 volts DC input, or 146.65 volts rms output for 140 volts DC input. The range 100 volts DC to 140 volts DC represents the range of voltages that could be produced by 60 lead-acid cells in series between the two extreme states of (a) substantially fully discharged and (b) fully charged and receiving a bulk or absorption charge. It may not be desirable to allow the AC output to vary so much over this range of DC input voltages. Accordingly, a method is used to maintain more constant AC output voltage in the face of varying DC input. 
     Instead of controlling the switches in a fixed timing sequence, a controller determines the time at which a sine wave output of desired amplitude passes from being nearer one voltage step to being nearer an adjacent voltage step, given the actual DC supply voltages, and may control the switches to change from the previous voltage step to the adjacent voltage step at the determined time. A simple implementation of the foregoing comprises pre-computing a sequence of switching times for each of a number of possible sub-ranges of the DC input voltage; for example, a first series of switching times for the range 100−110 volts; a second series for 110 to 120 volts; a third series for 120−130 volts, and a fourth series for 130 to 140 volts. Moreover, the series of switching times can be computed to give a nominal output voltage of 120 volts rms instead of 125.7 volts. 
     This method of determining a series of switching times to produce a constant 120 volt AC sine wave output with various DC input voltages may be extended to operate over the DC input voltage range 100 to 327 volts. At 327 volts, the 170-volt peak value of a 120 v rms AC sine wave is produced with a 4-digit ternary number of 1, −1, −1, −1, which illustrates that the highest voltage H-bridge still makes its maximum voltage contribution of 327 volts, but with the other three H-bridges backing-off this voltage by −109 volts, −36.3 and −12.1 volts respectively. Under these circumstances the highest voltage H-bridge is only contributing current for short periods at the very peaks, so the majority of power flow passes through the DC-DC converter, reducing efficiency and maximum output rating. For such a converter, the specification should indicate an efficiency and a maximum power derating factor as a function of input voltage. Input voltage ranges up to perhaps 200 volts may still be accommodated however with most of the output power coming directly from the DC input and only a fraction being supplied by the DC-DC converter, and therefore without significant loss of efficiency or power derating. Utilizing the extended input voltage capability is one way to construct a bimodal system using the same array voltage for both the grid-tie and the standalone modes, as will be described more fully herein. 
     The above example of an extreme DC input voltage of 327 V suggests another embodiment of the inverter. When the highest H-bridge voltage is 327 V, the second highest is 109 V. This suggests an inverter wherein the input voltage was the second highest floating DC source, and the bidirectional DC converter generated floating outputs of 3 times, 1/3rd and 1/9th of the input. Thus in one embodiment a converter for a nominal 96-volt battery powers the second highest voltage H-bridge directly, and the DC-DC converter generates 3×96=288 V, 96/3=32 V, and 32/3=10.67 V for the other H-bridges. Each inverter design is thus optimized for an intended range of DC input voltages. When the DC input voltage is outside the design range, a fault detector may apply a logic zero to pin  162  of  FIG.  3    and to a corresponding pin on the other half of the H-bridge and to all H-bridges, thus instantly halting operation of the converter until the input voltage once more lies consistently within the design range. 
       FIG.  12    shows the output sinusoidal waveform from the converter produced by controlling the switches in the proper sequence, when the DC input is 126 volts (a fully charged, 60-cell lead acid battery) and the desired AC output is 120 volts rms. For 60 amps AC output (7.2 kilowatts of output power), DC-to-DC converter ( 11 ) supplies only 1274 watts of the total power, the remainder coming directly from the 126 volt DC input via only H-bridge  120   a , which switches at only 60 Hz. Switching losses are therefore negligible for the bulk of the power flow. 
     The use of floating DC supplies of 120, 40, 13.33, and 4.44 volts to the inputs of the H-bridges, plus the use of opto-isolators to isolate the power MOSFET control lines, means that the outputs provided from the H-bridges are also floating, and can therefore be joined in series directly—that is, without further coupling means or weighting means, to provide an output voltage of 120×T4+40×T3+13.33×T2+4.44×T1 where (T4, T3, T2, T1) is the four ternary digit representation of the desired instantaneous output voltage from the converter. The ability to join the H-bridge outputs in series directly confers the benefit that the inventive DC-AC converter scheme requires no 60 Hz transformers, which reduces weight in particular, but the main benefits are reduced cost and size, and improved efficiency. 
     If the DC input voltage is not 120 volts, but in general is denoted by Vdc, then the formula for the instantaneous output voltage is Vdc(T4+T3/3+T2/9+T1/27). 
     For a greater number of digits than 4, for example n digits T1 . . . T(n), the formula for instantaneous output voltage is 
     T(n)+T(n−1)/3+T(n−2)/9++T1/3 (n-1)  times the DC input voltage if the direct current source voltage is the greatest of the floating DC supplies or alternatively
 
3T(n)+T(n−1)+T(n−1)/3++T1/3 (n-2)  times the DC input voltage if the direct current source voltage is the second greatest of the floating DC supplies, or even more generally
 
3 m [T(n)+T(n−1)/3+T(n−2)/9++T1/3 (n-1) ] where the power m is zero if the highest voltage is directly equal to the DC input voltage; m=1 if the DC input voltage is the second highest of the floating supply voltages; m=2 if the DC supply voltage is the third highest if the floating supply voltages, and so forth.
 
       FIG.  4    illustrates the behavior of the four ternary digits T4, T3, T2, T1 when generating a 120-volt rms AC output when Vdc=126 volts, as was used to produce the output waveform of  FIG.  12   . For this particular input and output voltage, it may be seen that the desired peak voltage of 120√2=169.7 volts is approximated with T4=T3=1 and T2=R 1 =0, giving 126(1+⅓)=168 volts. This is nearer 169.7 V than the next higher step of 172.44 V with T4=T3=T1=1 and T2=0. Thus small changes in the DC input voltage may require substantial changes in the waveform to maintain an absolutely constant 120 volt rms output; however such accuracy is not required and a finite number of precomputed waveforms may be used as previously described. 
     Some hysteresis in selecting the best waveform can be provided so as to prevent the converter nurdling, which describes the sound of periodic changes in inverter hum when inverters alternate between different waveforms. In any case, a selected waveform is used for at least an entire cycle to ensure symmetry between the positive and negative half-cycles and to ensure zero net DC bias on the output. 
       FIG.  4    also illustrates that the most significant DC supply voltage is not used (i.e., T4=0) around the zero crossings of the sine wave. Thus H-bridge  120   a  is programmed to the “pass-through” state when T4=0. In the pass-through state, either the DC input positive line or the DC input negative line is connected to both outputs of H-bridge  120   a . It is deliberately chosen that one H-bridge  120   a  output provides the neutral or grounded conductor output of the converter while the hot leg is provided by the end of the series H-bridge string, i.e., from an output of H-bridge  120   d . This results in either the DC input positive line or the negative line being connected to neutral (the grounded conductor) in the pass-through state. 
     By choosing to form the pass through state by connecting the positive DC input to neutral in the pass-through period following a positive half cycle where T4 was previously equal to 1, and choosing to form the pass-through state by connecting the negative of the DC supply to the neutral/ground after a negative half cycle when T4 was equal to −1, the waveform on each DC input terminal is a symmetrical square wave ranging from 0 to +120 V on the positive terminal alternating with 0 to −120 V on the negative terminal. Each DC input terminal may therefore be described as having a voltage of 60 volts DC mean with a 60 Hz, 60 volt peak square wave superimposed. When connected to a solar array, such a configuration is in conformance with the NEC electrical code (2008) provided a warning label is attached indicating that both terminals of the array and DC circuit are ungrounded and thus hot. An appropriate color code for wiring to the array is black for negative and red for positive, as both colors are standard colors for AC hot legs. 
     When the above-described pass-through states are used, the resulting common-mode square wave on the DC inputs will be slightly phase-shifted relative to the AC output. If the square wave shall be in phase with the AC output, then the pass-through state of H-bridge  120   a  can be created by connecting the positive DC input terminal to neutral/ground for the first half of the pass-through state after T4=1 and connecting the negative of the DC input to neutral/ground for the second half, and vice-versa for the pass-through state following T4=−1. In this way, the square wave positive-to-negative transition coincides with the zero crossings of the AC output, as shown in  FIG.  5   . 
     At time T1 on the left, the AC output is negative and the most significant ternary digit equals −1, and the DC supply+ve line is connected to neutral via MOSFET Tr(a). Accordingly the TR(a) drive waveform is at a logic 1 level, corresponding to MOSFET Tr(a) being ON. When TR(a) is ON, TR(b) must be off to avoid shorting the DC supply, which is guaranteed by connecting their opto-isolator LED&#39;s back-to-back. As the AC output rises towards zero, the most significant ternary digit goes to zero at time T2. At that point TR(c) is turned on and Tr(d) is turned off so that a pass-through state is created while leaving the DC positive line connected to neutral. The AC output goes through zero at the center of the period during which the ternary digit is zero at time T3. To synchronize the common mode AC component on the DC supply lines with the AC output, the negative of the DC input shall now be connected to neutral instead of the positive, while maintaining a pass-through state. Thus Tr(b) turns on, and Tr(a) off, while simultaneously Tr(c) turns back on and Tr(d) turns off. This results in the negative of the DC input being connected to neutral and also the H-bridge output is connected to the DC supply so that there is no net voltage supplied to the output, in conformity with the most significant digit still being zero. 
     At time T4, the most significant ternary digit becomes +1. At that point the negative of the DC input is left connected to neutral while the H-bridge output shall be connected to positive. Thus Tr(c) and Tr(d) change state. The situation now remains constant until the ternary digit next goes to zero at time T5, whereupon Tr(c) and Tr(d) change state again to create a pass-through state. At time T6 in the middle of the period during which the ternary digit is zero, Tr(a) and Tr(b) change state requiring Tr(c) and Tr(d) also to change state to maintain the pass-through state until time T7. At time T7, Tr(c) and Tr(d) change state to deliver a negative voltage to the H-bridge output when the most significant ternary digit becomes equal to −1. The just-described sequence then repeats indefinitely from time T8. 
     If an inverter is designed in which the supply voltage ( 100 ) is not the greatest of the floating supply voltages, then the common-mode waveform caused on the DC inputs will no longer be a simple square wave corresponding to the most significant ternary digit, but will have a waveform determined by the lesser significant ternary digit associated with the lesser supply voltage. Likewise, if the invention is used to produce other waveforms for other applications, then a more complex common-mode waveform related to the sequence of a particular ternary digit is induced on the DC conductors. When such a waveform is used as the probe signal for ground leak detection on the DC conductors, it may then be beneficial to detect leakage current using a correlator that correlates for that particular waveform. 
     To obtain a sine wave output voltage, controller  200  of  FIG.  1    represents the sine wave as numerical samples expressed in the ternary number system. When using a finite number of digits, it might be necessary to approximate the desired output voltage by the nearest ternary combination, and there are many ways in which an approximation could be constructed. For example, a ternary digit can be jittered between two adjacent values on successive instants of a high-frequency clock in order to approximate an intermediate value. This method is however reserved for a variation in the inverter design in which one of the ternary digits, e.g., the least significant digit T1, could be omitted, along with the associated components and the 4.44 volt floating supply, the value of T2 then being jittered between adjacent values at a high frequency so as to create a mean voltage between the 13.33 volt steps, thereby reducing component count. A low-pass LC interpolation filter is then connected at H-bridge  120   c  output to smooth the waveform. Frequent switching can be a source of additional switching losses, however switching only a low voltage supply such as 13.33 volts produces much less switching loss than jittering the 120-volt supply. 
     A second approach is to choose the nearest ternary approximation to the desired instantaneous output voltage at a sequence of successive, equi-spaced time intervals generated by a sampling clock. Yet another approach, which is the presently preferred approach, is to keep the ternary value fixed as long as it is the nearest approximation to the exact voltage, and to increment it or decrement it to the next adjacent value only at the instant that a different value becomes the nearest approximation. Storing the approximately 81 time-values of this sequence of switching instants requires much less memory than storing the ternary digits at all 32768 clock instants. 
     One method of producing the ternary digit sequence is as follows: Let controller  200  comprise a crystal reference oscillator running at 2 15 ×60=1,966,080 Hz. The oscillator clocks a 15-bit divider to produce a 15-bit address to a 32768×16-bit Read Only Memory (ROM) containing the precomputed waveforms required on the FET control lines of the H-bridges during one 60 Hz cycle. Symmetries, such as +/− symmetry, could be exploited to reduce memory size, if important. The buffered memory output bits drive the opto-isolators that drive the FET gates of each H-bridge to generate one of its three output voltage states at each instant and in the correct sequence. 
     The presently preferred approach uses a time counter for counting of the order of 32768 steps over a 60 Hz cycle, an address counter, and memory to store a count and an associated set of MOSFET drive signals. The address counter is initialized to the first address at an appropriate point in the power-up procedure and a set of MOSFET drive signals are read from the memory at that address, together with the next count. When the time counter reaches the next count, the address is incremented and the next set of MOSFET drive signals is read from memory, together with the next count value. In this way, the number of sets of signal values stored is only of the order of the number of waveform steps. Either method can be implemented in a suitable microcontroller, such as an 80C51, which contains suitable time-counters. 
     Using the above methods, it is relatively easy to construct a converter that can be selected to generate 50 Hz or 60 Hz, or even 400 Hz power by varying the oscillator frequency, the memory contents, or both, or storing waveforms over a lowest common multiple period of the desired frequency selections, or computing the ternary digit sequences in real time. 
     The ternary representation of a sine wave of peak voltage Vo volts when the DC input voltage is Vdc may be computed as follows:
         Divide up one cycle of 360 degrees into 32768 equal increments 0, θ, 2θ, 3θ . . . 32767θ, where θ=360/32768 degrees.   Compute the value A equal to Vo times the SINE of each angle. Then, for each angle:
           if A is greater than or equal to +Vdc/2, then T4=1;   if A is less than or equal to −Vdc/2, then T4=−1;   else T4=0.   
           Subtract Vdc times the just-determined value of T4 from A to obtain the remainder in A.
           If the remainder in A is greater than or equal to Vdc/6 volts, then T3=1;   if A is less than or equal to −Vdc/6 volts, then T3=−1;   else T3=0.   
           Subtract Vdc/9 times the just determined value of T2 from A to get the final remainder in A.
           If the final remainder A is greater than or equal to Vdc/54 volts, then T1=1;   if A is less than or equal to −Vdc/54 volts, then T1=−1;   else T1=0.   
           Repeat the above determination of ternary words (T4, T3, T2, T1) for each of the 32768 angular increments.       

     The above algorithm can also be executed using different voltage thresholds, corresponding to other DC input voltage levels, in order to determine a ternary digit sequence that will yield the desired AC rms output voltage for the other DC input voltages. 
     Having determined the ternary values for each clock period, the H-bridge drive signals required for that ternary value are then stored along with the clock count at which they are invoked, thus occupying a much smaller memory. With four H-bridges, the drive signals are conveniently packed into one byte, and slightly more than 81 entries result due to using both pass-through states for the most significant H-bridge around zero crossings, as shown in  FIG.  5   , which correspond to the same ternary digit of zero. In effect, two different forms of zero are used for the most significant ternary digit. In some cases it is possible that additional memory entries could be created in the event that small timing differences were needed between switching different H-bridges in order to minimize glitches. 
     The above ternary approximation algorithm can be executed for any set of graduated supply voltages, and for any desired output waveform or voltage. The peak output voltage should however be less than the sum of the floating DC supply voltages, if clipping of the waveform is to be avoided. 
     A number of ternary representation sequences can be precomputed and stored for different ratios of sine wave output voltage to DC supply voltage, in steps of a few percent for example, the selection among which then provides the means to regulate the output sine wave voltage against changes in DC supply voltage. 
     The algorithm may alternatively be executed in real time using a microprocessor or digital signal processor. For self-test purposes, the converter is equipped with an A-to-D converter that measures and checks each voltage step against limits during the start-up sequence, and may also periodically recheck each voltage step during normal operation, for example, by sampling and digitizing a voltage step level just before a step to the next voltage level in sequence is taken. Then the time at which the just-measured voltage step is the best approximation to the desired instantaneous sine wave level can be computed, and if different than the currently stored value, the stored value may be updated. By stepping to a higher voltage step a little earlier, or a lower voltage step a little later, a small increase in the output rms voltage is achieved, while stepping to a lower voltage step earlier or to a higher voltage step later, a small decrease in rms output voltage is obtained. In this way, a continuous and fine regulation of the output rms voltage may be obtained. 
     It is also possible to use a clock frequency that is different than a power of 2 times 60 Hz. There may then be more or fewer than 32768 clock cycles in one converter cycle. In a preferred implementation, an 80C51 microprocessor clock is 11.0592 MHz, giving an internal clock frequency of 11.0592/6 MHz, which is 30720 clocks in one 60 Hz cycle. Consequently the ternary digit sequence is calculated in steps of 360 degrees divided by 30720. The converter may also be provided with other stored sequences that can be selected to generate 50 Hz or 400 Hz outputs, which have repetition periods of 36864 and 4608 counts respectively, when using a crystal frequency of 11.0592 MHz. 
       FIGS.  10  and  11    give more circuit detail of the load converter.  FIG.  11    gives detail of the DC input circuit, showing the entry of the DC +ve and −ve lines through a common mode filter  200  into a start-up circuit comprising start-up relay RLY 1  ( 203 ), 100-watt lamp B 1  ( 204 ), photo-sensor ( 206 ) and main power relay RLY 2  ( 205 ). DC power flows through main power relay RLY 2  ( 205 ) when closed and through  100 A current measuring shunt ( 206 ) to 60 KHz bidirectional DC-DC inverter ( 110 ) and to 120-volt H-bridge  120   a . Bidirectional DC-DC inverter  110  generates the floating DC voltages of 40 v, 13.33 v and 4.44 volts for the other three H-bridges  120   b ,  120   c , and  120   d.    
     Each of the DC voltages produced by the bidirectional DC-DC inverter is decoupled with a substantial reservoir capacitor, which however is not essential to the operation of the inverter. There are two advantages of using reservoir capacitors: first, to reduce copper losses in the 60 KHz inverter transformer windings by smoothing out current demand, and second, to reduce low-load or no-load standby power. Both of these will be explained in further detail herein. Upon switch on, these reservoir capacitors would cause a substantial and potentially damaging in-rush current to flow for some fraction of a second; the purpose of the start-up circuit of  FIG.  11    is to reduce such in-rush current to safe values. The start-up circuit also permits the whole inverter to be powered up stage-by-stage, while checking for faults at each stage, so that start-up may be aborted if faults exist that could cause a cascade of other component failures. 
     Referring to  FIG.  11   , the DC+ and − input terminals are connected through common mode filter  200  to control circuit and auxiliary power supply unit  202  via a 250 mA fuse  201 . Upon applying a DC input to the input terminals, auxiliary PSU  202  starts operating and powers up the control circuit, which may contain a microprocessor. After performing self checks to verify that the control circuit initialized itself correctly, ensuring that all output relays and the start-up and main power relay are in the OFF position, and all H-bridge transistors are off, the control circuit closes start-up relay RLY 1  ( 203 ), the coil of which is powered from the already operating auxiliary PSU ( 202 ), to connect the DC positive line through 100-watt lamp ( 204 ) to the input of the 60 KHz bidirectional DC-DC converter ( 110 ). The DC-DC converter power transistors and synchronous rectifier transistors are commutated at this point so that DC flowing through lamp  204  will be converted to the desired output voltages, charging all reservoir capacitors at a rate determined by the limited lamp current. For the purpose of analysis, the total reservoir capacitance transformed through the 60 KHz inverter transformer ratio may be lumped into a single value, shown dotted in  FIG.  11   . The current required to charge this capacitor is sufficient to light the 100-watt lamp for a second or so, the lamp dimming as the capacitor charges towards 120 V. The lamp  204  thus limits the in-rush current to perhaps 7 amps when the filament is cold, falling to 0.8 amps when the filament is at full brightness, and then falling further as the capacitance charges up towards 120 V. The charging is faster than exponential, as the resistance of the lamp reduces from 150 ohms at full brightness to about 18 ohms as it cools. The use of a lamp instead of a series resistor has this benefit of faster charging, and also is able to dissipate 100 watts as long as necessary, whereas a 100 watt resistor would need heat-sinking and would be more expensive. 
     If any fault exists which causes the 60 KHz inverter, or any H-bridge, which is supposed to be off, to take current, then the no-load current through the lamp will not drop to zero, and will be high enough to cause the lamp to remain partially lit. After allowing 2 seconds for normal start up, such a fault condition is detected using phototransistor  206 , which is in close proximity to lamp  204 , and the control circuit aborts start up and opens start-up relay  203  upon detecting the abnormal condition. Assuming, however, that the lamp does not remain lit, after two seconds the control circuit concludes that all reservoir capacitors have been successfully charged and that no abnormal no-load current exists. The control circuit also requires to have seen the lamp light briefly after the start-up relay is closed, thus verifying the integrity of the lamp and the phototransistor. If the lamp does not light briefly after closing the start-up relay, the start-up sequence may be aborted. Automatic retries may optionally be programmed to occur up to a limit. 
     After the reservoir capacitors are charged, the main inverter H-bridges are operated off load with the AC output relays open.  FIG.  10    shows more detail of the complete single-phase load converter. Referring to  FIG.  10   , the DC input enters via common-mode filter  200  to the startup circuit just described with the aid of  FIG.  11   . The start-up circuit switches the filtered DC input through a 100-amp current shunt ( 101 - 5 ) to 60 KHz inverter  110 - 1  and 120 V H-bridge  120   a.  60 KHz inverter  110 - 1  together with synchronous rectifiers  110 - 2 ,  110 - 2 , and  110 - 4  constitute the bidirectional DC-DC converter of  FIG.  2   . Each synchronous rectifier has an output reservoir capacitor and is connected to an associated H-bridge,  120   b ,  120   c , or  120   d . The four H-bridges are driven by four corresponding sets of four opto-isolated MOSFET drivers ( 222 ). Each synchronous rectifier uses two further MOSFET drives and the 60 KHz inverter uses two MOSFET drivers, making 26 in total. The MOSFET drivers require 12−15 volt power supplies. Two MOSFET drivers can use the same 15-volt supply if they drive MOSFETs that have their sources connected. Thus, using the transistor identifications of  FIG.  3   , one 15-volt supply is required for H-bridge  120   a  TR(b) and TR(d); another is required for H-bridge  120   b  TR(b) and Tr(d) and the transistors of its associated synchronous rectifier  110 - 2 ; a third is required for H-bridge  120   c  and its associated synchronous rectifier  110 - 3 ; a fourth for H-bridge  120   d  and rectifier  110 - 4  and a fifth for 60 KHz inverter  110 - 1 . Other isolated supplies may be required for microprocessor controller and waveform generator  202 - 2  and for various overcurrent, undervoltage, and overvoltage sensors. All these supplies are produced by auxiliary power supply  202 - 1 . Auxiliary supply  202 - 1  comprises a low-power, switch-mode regulator producing high frequency AC which is distributed to the location on the printed circuit board at which an isolated supply is needed, where it is transformed to the desired voltage using a small toroidal isolating transformer followed by a diode rectifier. Distributing AC and isolating and rectifying it at destination has the benefit of reducing PCB tracking congestion. 
     The output from H-bridge  120   d  is coupled back to controller  202 - 2  where the instantaneous output voltage can be sampled and digitized by an A-to-D converter. Each ternary step can thus be tested in turn during the start-up sequence by measuring the output voltage produced. If all ternary steps look normal and lamp  204  did not light in the process, the conclusion is that all H-bridge transistors are operating normally with neither short nor open circuits, giving a very low no-load current. The H-bridges are then operated to generate the normal step approximation to a 120 volt rms sine wave. Again assuming that lamp  404  remains unlit, the inverter is now generating the desired 60 Hz output with no abnormal no-load current. The main power relay ( 205 ) is then closed, which shorts out the lamp and start-up relay to allow high currents to flow when the AC load is connected. Note that relay  205  closes only when there is zero volts across its contacts and zero current through it. This permits it to be a very much lower cost relay than one with sufficiently robust contacts to make or break full load many times. 60 Hz generation is then temporarily suspended by controlling the four ternary H-bridges to the open circuit condition so that the AC output relays may also be closed with no voltage across them and no current though their contacts. 60 HZ generation is then resumed to deliver AC power to the load, and if no current overload is detected, the inverter has successfully executed a safe start-up. Both the main power relay and the AC output relays derive their coil power from the 13.33 volt output of the 60 KHz inverter, so that any failure of the DC-DC converter forces those relays to the open condition. Moreover, the auxiliary PSU is diode-protected such that it will neither power-on nor be damaged by connecting the DC input with reverse polarity. The start-up relay cannot therefore be operated if the DC input is of the reverse polarity, thus protecting polarized electrolytic capacitors and the H-bridge switches from accidental damage. 
     Power down of the inverter can be initiated by a user OFF switch or by detection of any of the following fault conditions, which are not necessarily exhaustive:
         Over- or undervoltage at the DC input;   Overcurrent from the DC supply;   Excessive AC current;   Overtemperature on the heat sink;   Lamp  204  becoming lit; or   Abnormal AC output voltage waveform.
 
The above fault conditions may be arranged to cause substantially instantaneous cessation of inverter operation.
       

     A normal Power down occurs in approximately the reverse order to power-up. First, commutation of the ternary H-bridges ceases and they are switched to the open circuit condition. The AC output relays  131  are then opened, which occurs with zero volts across the contacts and zero current through them. The main power relay ( 205 ) is then opened, which occurs with no current flowing through it and zero volts across its contacts. Finally, the start-up relay  203  is de-energized, which connects the reservoir capacitance through the lamp to ground, discharging it. The 60 KHz inverter continues to operate while the reservoir capacitors are discharging, but is deactivated after a few seconds. The control circuit can check whether lamp  204  lit momentarily during the capacitor discharge sequence, as it should. The inverter is then ready to begin a power-up cycle once any fault condition is cleared. Automatic restart attempts can be programmed to occur up to a specified number of retries, if desired. 
       FIG.  12    shows the ternary approximation of the sine wave output from the inventive load converter. A feature of this invention is that all the voltage steps are of approximately the same size, but have a varying dwell time according to how fast the sine wave is changing. This gives a well-spread approximation error spectrum with no dominant harmonics.  FIG.  13    shows the amplitude of each harmonic of 60 Hz up to 16384×60 Hz, which is in the middle of the medium waveband. 
     The Medium Wave frequency band begins at about half way from center, where the spectral energy in any 9 KHz AM radio channel is seen to be 78 dB below the main 60 Hz component. For a 5 kW (+67 dBm) converter, this is a level of −11 dBm in the 9 KHz bandwidth of an AM radio. This is still a high level of radio noise, and interference with radio and TV reception from Medium Wave all the way up to VHF TV frequencies has been observed when using prior art converters. Such interference is called “inverter hash” and has been known since the days or rotary converters, or dynamotors, where it was due to commutator/brush noise. Thus, despite the good sine-approximation evident in  FIG.  12   , the sheer power of the converter requires that additional hash suppression be used when operating close to sensitive radio receivers. Suppression of radio interference shall be at least sufficient to meet FCC part  15  specifications, but greater suppression is often desirable. 
       FIG.  10    shows more detail of a complete load converter, including RFI filters at both the DC input ( 200 ) and the converter output ( 131 ). The RFI filters are required, as the output will be distributed around the house wiring in a residential application. A suitable 2 rd -order LC filter is shown in  FIG.  8   .  FIG.  14    shows the reduction in medium-wave interference to 98 dB below the inverter output when using the filter. This additional 20 dB of suppression of inverter hash substantially eliminates interference at medium wave and above with radio and TV in the same location. 
     As discussed further herein in relation to common mode filtering on the DC side, RFI filters preferably include damping resistors as well as capacitors and inductors, to ensure that no high-Q resonances occur at any frequency when connected to arbitrary house wiring and appliances. This is the purpose of C 2  and R 1  in  FIG.  8   . These components are chosen also to minimize ringing and overshoot on no load. 
       FIG.  9    emphasizes the difference between a safe RFI filtering circuit ( 9 B) and an unsafe RFI filtering circuit ( 9 A). Unfortunately, the unsafe circuit of  FIG.  9 A  is in widespread use on the input power connectors of Personal Computers, VCRs, and the like, and electronic technicians quite commonly experience shock from laboratory benches due to the use of such filters in laboratory test equipment when the ground is temporarily lost, as can happen accidentally or deliberately in a dynamic R&amp;D environment for various reasons. It can also result in inadvertent damage to expensive equipment upon accidental or deliberate disconnection of the equipment ground. 
     With the prior art circuit of  FIG.  9 A , should the ground connection to the equipment fail, the line voltage will be divided in two by the potential divider formed by the filter capacitors, and the chassis or case of the equipment will become live to the touch, at about 60 volts 60 Hz AC (in the US) or 120 volts 50 Hz (in Europe). The current is limited when the filter capacitors are small, e.g., 0.01 uF, but can still be felt as an electric shock, and is very unpleasant if the equipment is a medical device attached to a catheter, for example. Moreover, when several pieces of equipment are used together, as in a rack or a lab bench, the net current can reach more dangerous levels. For an entire household, the typical ground current that can be measured flowing down the grounding rod is often as high as 50 mA, arising from all installed appliances such as TV sets, computers, VCR&#39;s, washing machines, etc. 
       FIG.  9 B  shows the safer form of RFI filter. In  FIG.  9 B , the filtering capacitors decouple the hot line to the neutral line, not the equipment ground as in  FIG.  9 A . The neutral line is then decoupled to the equipment ground with another capacitor. In this way, should the ground become disconnected, the chassis or case of the equipment is only connected via a capacitor to the neutral line, not the hot line, thereby avoiding a safety hazard. It would require both the ground and the neutral wire to fail while the hot line remained intact, in order to cause the case or chassis of the equipment to become live when using the RFI filtering circuit of  FIG.  9 B , which is therefore a safer arrangement. 
     For the reasons given above, the output RFI filter comprises a series inductor in the 120-volt AC hot leg output, and capacitors C 1  and C 2  connect to neutral, not equipment ground. Furthermore, the neutral output is decoupled to equipment ground through the neutral output isolating relay contacts. In this way, when the output relays are open, there is no path to ground for the inverter, battery or array circuits, not even through the 1 uF neutral-ground decoupling capacitor, thus ensuring complete isolation of the DC circuits when the inverter is not operating. 
       FIG.  6    shows the common mode hash filter used on the DC input. This also returns the decoupling capacitors to neutral rather than equipment ground for the reasons discussed above. A common-mode filter is used due to the square wave exported to the DC input lines being in phase on both terminals. The purpose of this filter is to slow the rise and fall times of the edges of the 60 Hz square wave in order to avoid exporting radio interference to DC equipment such as the solar array and battery. The DC lines from the array may be protected against induced static during thunderstorms by means of gas discharge surge arrestors, and it is desired to avoid peak voltages due to filter overshoot under normal operation that could cause premature ignition of the surge arrestors.  FIG.  7    shows the transient response of the common mode hash filter of  FIG.  6   , after optimization of component values for minimum overshoot. 
       FIG.  2    shows a bidirectional DC-DC converter for providing various floating DC output voltages such as Vdc/3, Vdc/9, and Vdc/27 using a DC source of Vdc volts. 
     The DC-DC converter uses a high switching frequency such as 60 KHz, enabling the transformer to be much smaller than would be required for 60 Hz operation. The transformer in  FIG.  2    has four windings, which have turns ratios N 1 :N 2 :N 3 :N 4  in proportion to the voltage ratios V 1 :V 2 :V 3 :V 4 . For the purposes of explanation, each winding has been shown as a center tapped winding with the center taps connected to the positive terminal of the DC inputs or outputs and the ends of the windings connected to the drains of N-type MOSFET pairs. Power MOSFETs generally comprise a drain-to source body diode which is shown as part of the transistor. 
     One of the transistor pairs, for example TR1a and TR1b, is commutated at 60 KHz and a voltage V 1  is applied to that input. The other transistor pairs are commutated in synchronism and form synchronous rectifiers. For example, TR2a is switched on when the transformer winding end to which its drain is connected goes negative, thereby transferring the negative voltage to the −ve terminal of the V 2  output. Likewise TR2b is switched on when its drain goes negative, and the drain of TR2a goes positive, TR2a is switched off when its drain is positive and thus does not pass current. Thus a DC voltage V 2  is produced at the V 2  output which is N 2 /N 1  times V 1 , where N 2  and N 1  are the numbers of turns on the respective transformer windings. It can be seen that the input circuit for V 1  is indistinguishable from any output circuit. Thus any one of the transistor pairs can function either as an inverter commutating a DC input or as a synchronous rectifier producing a DC output. Thus power flow can be from any port to any other port depending on whether the port is sinking current or sourcing current. This is important to the operation of the inventive load converter as power flows in the reverse direction whenever a ternary digit has the opposite sign to the instantaneous output voltage, or if the AC output current is not in phase with the AC output voltage due to the non-unity load power factor of a reactive load. 
     In a presently preferred implementation of the converter, the commutator used to connect the 120 volt supply to the transformer is a full H-bridge, eliminating the primary center-tap and simplifying the transformer. The 40 volt, 13.33 volt, and 4.44 volt windings are however center tapped and connected to synchronous rectifier MOSFET pairs as shown in  FIG.  2   . Using a transformer center tap is simpler than using a full H-bridge synchronous rectifier, as each synchronous rectifier can share a gate driver supply with the H-bridge it powers, since their sources are common. Moreover, the transformer can be divided into two or three transformers with their non-center-tapped primaries paralleled, in order to obtain convenient sizes and avoid wiring concentration. In a presently preferred implementation, a first transformer has a 120 volt primary and a center tapped 40-0-40 secondary, while a second transformer has a 120 volt primary and center tapped 4.44-0-4.44 and 13.33-0-13.33 volt secondaries. Providing the 40 V supply from a first transformer and the lower voltages from a second transformer results in identically-sized, small transformers. 
     In designing a DC-to-DC converter, a trade off must be made between switch losses, copper loss in the windings, and hysteresis loss in the core. Using a higher frequency gives fewer turns of thicker wire, but core and switch losses increase. In the 60 KHz region, skin-effect is significant for smaller wire than 23 AWG, so Litz wire comprising many strands of 23 AWG is used to reduce copper loss. 
     Core loss persists even when the output power is zero, which can be a significant contributor to standby (no-load) current. In the inventive load converter, standby current due to core and switching losses in the DC-DC converter is reduced by use of a novel waveform. Firstly, the 40, 13.33, and 4.44 volt outputs of the DC-DC converter are provided with large reservoir capacitors. This has the first benefit that current in the transformer windings is proportional to the mean DC current of each output, rather than the peak current, thereby reducing copper losses in the windings. A second benefit is that the reservoir capacitors can supply the low currents required for light loads for at least one or more cycles of the 60 KHz switching frequency, enabling switching cycles to be periodically omitted. For example, if the load current is only 1/10th the peak output capability, then every alternate DC-DC converter switching cycle can be omitted and all the transistors of  FIG.  2    are held in the off state during the omitted cycle. In this way, core and switching losses are halved at 1/10 maximum power output. At even lower power outputs, for example 1/100 th the maximum, it may be chosen to omit 9 out of 10 DC-DC converter switching cycles, which reduces the core and switching losses even further. Upon detecting an increase in load current or reduction of any voltage, the number of omitted switching cycles may be instantaneously reduced in anticipation of the need to supply greater current to the reservoir capacitors. 
       FIG.  21    exemplifies the novel DC-DC converter waveforms.  FIG.  21 ( a )  shows the DC-DC converter switching waveforms when operating continuously with no omitted cycles.  FIG.  21 ( b )  shows the switching waveforms when alternate switching cycles are omitted, and  FIG.  21 ( c )  shows omitting three out of every four switching cycles. This method of reducing switching losses at light load is different than merely reducing the switching frequency. If the switching frequency were reduced instead, the volt-time integral into the transformer on every half cycle would increase, increasing the peak flux density and potentially causing core saturation. However, keeping the positive and negative half cycles the same length in microseconds while omitting cycles does not increase the flux density. 
     An alternative waveform for reducing switching frequency would be to space the on periods of TR 1   b  TR4b midway between the on periods of TR 1   a  TR 4   a . However this has some consequences for transformer and controller design and is not the preferred method. The presently preferred method of omitting complete cycles has the advantages that the transformer flux is reset to zero after each non-omitted, complete cycle, and that all transistors can use the same control waveforms. 
     An isolated positive pulse or half cycle followed by a negative pulse or half cycle may be referred to as a “doublet.” The inventive power-saving waveform for light loads may therefore be described as driving the DC-DC converter with doublets, the spacing between successive doublets being increased as the current demand reduces. 
     Power transformers exhibit an “in-rush current” phenomenon, which occurs when power is suddenly supplied to the transformer at a voltage zero crossing. The flux in the core rises to a maximum during the first half cycle, and then falls to zero during the reverse-polarity half cycle. However, that implies a DC bias to the flux, which therefore swings between zero and twice the normal peak. This DC bias decays due to winding resistance after several cycles, but meantime may cause core saturation and greatly magnified in-rush current. To prevent this, it is advantageous to modify the waveform of the doublet by including the last quarter-cycle of the previous (omitted) cycle and the first quarter cycle of the following (omitted) cycle, thus preventing the flux density in the core from exceeding its normal steady-state value. The modified doublet and the attendant core-flux waveform are shown in  FIG.  25   . It is known from the art of solid state relays to employ peak switching of AC voltages into inductive loads precisely for avoidance of in-rush current, as just described. 
     Since high-frequency transformers must operate at much less than saturation flux density in order to reduce core loss, typically at around 100 to 200 milliTeslas, it may not be necessary to use the more complex modified doublet waveform of  FIG.  25    when omitting cycles. The choice between the waveforms of  FIGS.  21  and  25    should be made in dependence of the DC-DC transformer design and the properties of the magnetic material used for its core. 
     A 7.2 kilowatt single-phase standalone inverter has been designed according to the above principles using a single 4-layer printed circuit board (PCB) of size 12″×14″ for all higher-power and high-current components and one smaller 4-layer PCB for microprocessor and control functions. The power board uses a “maximum-copper” layout, in which heavy-current conductors are of the widest possible dimensions, formed through removing copper in narrow strips to isolate different circuit nodes, thereby leaving the maximum amount of copper, rather than the conventional PCB layout technique of defining narrow tracks of copper where conductors are required and etching away everything else. Power transistors requiring heat-sinking are contained within a 14″×5″ section in the middle of the board and have their leads soldered to the board on the component side, so that no leads or solder bumps protrude to the other side, which may then be bolted flat to a metal heatsink forming part of the case of the inverter. The inverter, as with other equipment designs described herein, may be designed to be mounted flush with the wall covering (e.g., SHEETROCK™) in the 14″ gap between two studs at the standard 16″ spacing in US residential wood frame construction. The outer gridded surface of the heatsink is inside the wall, and louvered vents may be placed above and below the inverter to provide convective airflow as necessary, with the gap between studs acting as a chimney to enhance convection. A thermistor on the heatsink protects the inverter from overtemperature in the event of use at maximum power for prolonged periods with restricted airflow. 
     While the above-described load converter provides some proportion of a household or business electricity needs and provides a desirable battery back-up facility, the timing of the demand is not necessarily correlated with solar irradiation, which is the purpose of storing energy in a battery for future use. Currently, lead acid batteries are the only economic storage solution, but this may change if electric vehicle battery research and their large production volume succeed in reducing the cost of other battery types. In general, storage batteries, and lead acid batteries in particular, survive only a finite number of charge-discharge cycles before replacement becomes necessary. To prolong life, it is desirable to avoid 100% depth of discharge on a regular basis, and to allow normally only 20% depth of discharge, except during the emergency situation of a utility outage. Using 10, 12-volt, 100 ampere-hour, deep-cycle batteries, the energy storage available during a utility outage would thus be 12 kilowatt-hours, which will run essential household appliances for a considerable period. Only 20% or 2.4 kilowatt hours should be used regularly however. Thus it is only possible to defer 2.4 KwHrs of consumption of solar energy to a later period of the day without using a much bigger battery. Some of this supply-demand timing mismatch can be resolved by using smart devices to start loads, such as a dishwasher, according to a timer, or even according to solar illumination. Another possibility is to divert solar energy in excess of battery charging needs to HVAC or other diversionary load. However, there is a limit to how much solar array energy can be absorbed by a household immediately due to the very varying demand and supply curves. To improve the supply-demand match, solar energy can be diverted to the utility grid where the demand curve is averaged over millions of users. This is the purpose of a grid inter-tie inverter. 
     Before describing the inventive grid-tie inverter in more detail, a solar combiner is described that assists smart energy management in a complete installation. The circuit of solar combiner  700  is shown in  FIG.  27   . A number of DC inputs  700 - 1  to  700 - n  may be connected to the terminals of individual solar panels or different strings of solar panels. The inputs are isolated and have separate−ve and +ve terminals for wiring to the solar array. Each pair of input wires is connected to the input of a respective per-string circuit  710 - 1  to  710 - n . Each per-string circuit comprises fuses  701   a ,  701   b  on both the positive line and the negative line to protect wiring from fault conditions. Each DC input line then proceeds through snubber circuit ( 702 ,  703 ,  704 ) and blocking diode  705  to DPDT relay  706 . Blocking diodes  705  prevent reverse current flow to any string or panel exhibiting lower voltage than the other strings, for example when a panel is shadowed. When properly selected, blocking diodes have a voltage drop of around 0.6 volts, so there is a compromise between the diode loss and the current loss due to shadowing without diodes. For array voltages below about 36 volts, it may be more efficient to omit the blocking diodes and tolerate shadowing loss, while it is more efficient to employ them for higher array voltages. An advantage of blocking diodes is that they also prevent blowing a fuse if a string is accidentally short-circuited. Blocking diodes may also be desirable for lower array voltages if a substantial fraction of the total number of strings can be simultaneously shadowed. 
     Snubber circuit comprising capacitor  702 , diode  703 , and resistor  704  operates in conjunction with blocking diode  704  to protect the contacts of relays  706 ,  707  from high in-rush current and arcing on making or breaking. Consider for example that the load on output  1  comprises a large capacitor, e.g., the reservoir capacitor on an inverter. When relay  706  is closed to route current to output  1 , the load may instantaneously appear like a short circuit, pulling the voltage of the positive line down to the potential of the negative line. This negative going transient passes through capacitor  702  and reverse biases diode  703 , so that the only current that flows is the array short circuit current, which is inherently limited, plus the current flowing through resistor  704  to discharge capacitor  702 . The load voltage then rises smoothly with relay  706  contacts closed and capacitor  702  charges through resistor  704  to the same voltage. When relay  706  contacts open to disconnect the string from the load, the string voltage attempts to rise, and the positive going transient passes through capacitor  702  to forward bias diode  703 , which therefore caps the voltage rise at about 0.7 volts. Thus the relay contacts are only required to break load current with 0.7 volts across them. In another situation, the load may already be charged or powered by other strings when relay  706  closes. If capacitor  702  is not already charged, blocking diode  706  will prevent a high back-in-rush current from the load, leaving capacitor  702  to be charged only by the inherently limited array current. A suitable capacitor  702  is about 220 uF with a working voltage above the highest open circuit string voltage with which the combiner is intended to operate. 
     One positive and one negative output contact from each of relays  706  are paralleled to the DC output bus connected to output  1  terminals  721 . Each relay may be controlled, via control port  1 , to connect its associated string to output  1 . Thus the combiner can be remotely controlled via control port  1  to deliver the current of 0, 1, 2, . . . , n strings to output  1 . Typically, eight relays ( 706 ) would be driven by a relay driver chip located in a controller. The controller may be part of inverter  1000 . A suitable relay driver chip is the Texas Instruments part number TPL9201. Output  1  may be connected to a battery and a load converter. The load converter can monitor the battery voltage and optionally the battery net current and, via control port  1 , direct the combiner to output more or less current to output  1  by selecting or deselecting strings in order to keep the battery at an optimum state of charge. The load converter can thereby achieve intelligent battery management, by implementing in software different charge regimes such as bulk charge, absorption charge, equalization charge, and float charge, in dependence on the history of the battery state. Alternatively, a separate charge controller can implement these functions in cooperation with the solar combiner  700 . The advantage of involving the solar combiner in charge control is that any string not required to achieve the desired instantaneous load inverter plus battery charge current can have its current diverted to a secondary output  2 . 
     When relay  706  is not selected to output its associated string current to output  1 , the current is routed to relay  707 . Relay  707  may be programmed to divert the current to a second output bus connected to output  2  terminals  722 . Output  2  is connected to a load that is of lower priority than the load on output  1 , as control port  1  must have caused a relay  706  to relinquish current in order for output  2  to receive it. The second priority load can comprise controls connected to control port  2  to select any of the strings relinquished by the first priority load, or none. When control port  2  does not select a string, its output appears on associated string test points which are isolated from all other strings and loads, which is useful for maintenance purposes. A bleed resistor  708  is connected across each test point so that, upon deselecting a string for maintenance purposes, the charge on capacitor  702  is bled down to a safe value in about 30 seconds. If neither the first nor second priority load selects any string, then all strings are isolated from each other and the loads, thereby providing a DC disconnect function. DC disconnect can be forced using switch  709  local to the combiner, which removes power from all relay coils. Second or further switches can optionally be provided at remote locations to force DC disconnect. For example, a DC disconnect can be provided at an inverter, at the main service entrance of a building, and so forth. In any case, when the inventive load inverter is connected to output  1  and control port  1 , if the inverter ceases inverting for any reason, relay power will not be supplied to control port  1 , and DC from the array will be disconnected from output  1 . Likewise, if a grid-tie inverter is connected to output  2  and control port  2 , cessation of inverting will disconnect relay power from control port  2  causing all relays  707  to disconnect DC power from output port  2 . An inventive load converter and an inventive grid tie inverter may also be coupled such that, if one ceases inverting, the other will also cease inverting. Optionally, relays  707  can be replaced with manual DPDT switches, and then the load on output  2  automatically receives the current of any string not used for output  1 , as long as the associated manual switch has enabled it. However, the disconnect function of manual switches cannot be remote-controlled from another location. 
     Since each per-string circuit  710  is identical, a small sub-board can be designed to accommodate the components, and only as many installed in a particular combiner as there are strings to be combined. Since no combiner is required for a single string, it is logical to put at least two circuits  710  on a sub-board, and then to install as many sub-boards as required to reach or exceed the desired combining capacity. Parameters for a typical combiner board are:
         Absolute Maximum string voltage: 380 volts   Maximum number of strings per combiner: 8   Maximum current per string: 8 amps   Total maximum current: 64 amps.       

       FIG.  15    illustrates an inventive single-phase grid inter tie inverter. As in the load converter configuration, the circuitry is simplified by the use of a floating solar array in which neither terminal is permanently connected to ground or the neutral line. The floating DC supply from the solar array is fed through common-mode filter  200  to H-bridge  2010 . The four MOSFET power transistors of the H-bridge are able to be turned on and off by opto-isolated controller  2020 . Tr(a) and Tr(b) connect the positive and the negative of the DC supply alternately to the AC output neutral line, which is a grounded conductor. The DC− is connected to the neutral when the AC output is required momentarily to be positive, and the DC+ is connected to neutral when the AC output is momentarily required to be negative. This switching is synchronized with the utility grid so that the two solar array terminals are alternately grounded at a 60 Hz repetition rate. Common mode filter  2000  slows the switching edges as previously described so as to avoid the export of high frequency interference. The voltage on each solar array terminal relative to ground thus comprises an average of about 85 volts DC with an 85-volt peak square wave superimposed. For the safety of electricians or other personnel who may work on the solar system, the solar array and other parts of the DC circuit shall, according to the National Electrical Code (2008) be labeled with an indication that both DC conductors are hot. An appropriate wire color coding is red for positive and black for negative, both of which signify “hot” in an AC context, while identifying positive and negative in a DC context. 
     When the DC−ve is connected to neutral, the other two H-bridge transistors TR(c) and TR(d) operate at a high switching frequency, for example 200 KHz, to connect the DC+ to the AC output with a mark-space ratio varying in proportion to the desired sinewave current waveform. The on-off switching can for example be a delta-sigma modulation representation of the desired positive half cycle. Thus TR(c) turns on for a time to cause current to increase in L 1 . Tr(c) then turns off and TR(d) turns on to catch the flyback from L 1 . TR(c) and Tr(d) operate in reverse for a negative half cycle, when the DC+ isconnected to neutral. The required switching patterns may be precomputed and stored in controller  2020  memory for one complete 60 Hz cycle, or else synthesized in real time to create the desired current or to follow the utility voltage. C 1  further smooths the current from L 1  to deliver a sine wave current to the utility. A further RFI filter  2030  may be used to reduce export of inverter hash which could otherwise cause radio interference. 
     The inverter of  FIG.  15    has in principle a high efficiency when operating at normal power levels, but does not operate efficiently at greatly reduced power levels. One reason for this is that the impedances of L 1  and C 1  must be related to the output current and thus values appropriate for the maximum current do not provide proper smoothing at much lower currents. Moreover, the high frequency switching losses, while being negligible at full power, would be relatively more significant at lower powers. Also, this type of inverter must deliver a current to the utility at whatever voltage the utility exhibits, in contrast with the previously described load converter which must deliver a constant voltage to the load, whatever current the load draws. For these reasons, a grid-tie inverter does not make a good load converter, and vice-versa, although it is possible to design an inverter, known as a bimodal inverter, which can be wired up and operated in either mode. 
     Both types of high-efficiency converter have a number of things in common however, as well as the inventive principles described by the attached claims: In the single-phase case, the instantaneous power delivered to the load or utility is proportional to the square of the voltage, and therefore follows a sin 2  (wt) curve which is a double-frequency raised cosine ranging from zero watts to twice the mean power. In the load converter case, the battery evens out this demand and allows the solar array to charge the battery at a constant current. In the case of the grid-inter-tie inverter however, without the battery, there would be no means to even out the demand, and thus the solar array would have to be sized to deliver twice the mean current with consequent under-utilization at other times in the 120 Hz cycle. To avoid this, a single phase grid inter-tie inverter requires a substantial input reservoir capacitor C 2  to even out current flow over each 120 Hz cycle, and thus to match it with the constant current available from the solar array. 
     If the grid-tie inverter delivers 60 amps rms to the utility at 120 volts, that is 7.2 Kw, the mean current from the solar array is 7.2 Kw divided by the DC input voltage of, say 175 volts; that is, 41 amps. The peak current required by the inverter is 82 amps. C 2  must therefore supply 41 amps during a positive-going 120 Hz half cycle and recharge at 41 amps on the negative-going half cycle. Neglecting the solar array output resistance, the 41 amp peak cosine current ripple must be absorbed by C 2  without producing a large ripple voltage. For 2 volts peak ripple, the value of C 2  is given by 2Π 120 C 2 =41 amps/2 volts, from which C 2  is determined to be approximately 27000 uF. The size and construction of this capacitor is determined more by its ripple current handling requirement than by its capacitance, and consists of several aluminum electrolytic capacitors in parallel. This reservoir capacitor thus operates with a current ripple equal to the full output current, and must therefore be operated very conservatively and well within its maximum ripple current capability to prevent degradation. Degraded electrolytic capacitors operating with high voltages and ripple currents can overheat and burst causing a big mess, as often happened with antique tube radios, and has happened more recently with grid-tie inverters of the prior art. As will be shown, the inventive three-phase grid-tie inverter can operate with a much smaller smoothing capacitor, as the current demand from the solar array for the three phase case consists of three, double-frequency raised cosine curves spaced 240 degrees apart, which substantially cancel each other and produce much less ripple current. 
     The grid-tie inverter is self-regulating, in that it attains a level of output current to the utility which allows the solar array voltage to rise to the required minimum of √2 times the peak utility voltage, that is about 170 volts assuming 120 volts at the utility. 
     A grid-tie inverter has to meet specific safety requirements and in particular the anti-islanding requirement specified in Underwriter Laboratories standard UL1741. Anti-islanding refers to means that must be employed to prevent the inverter from attempting to back-power a neighborhood during a utility outage, as this could endanger personnel trying to fix the fault. Anti-islanding is achieved by having the inverter controller  2020  derive its timing cues from the utility voltage, for example by waiting for a utility voltage zero-crossing to trigger the next switching cycle. If the utility is in outage, leaving one or more utility converters in a neighborhood connected to the grid, they will each wait for the next zero crossing and the frequency will therefore drift until it is clearly out of limits, at which point the inverter stops and opens the output disconnect relay  2100 . The inverter is also programmed to trip out if the voltage at its utility connection is outside of specified limits, which is also indicative of disruption of the utility connection. Controller  2020  continues to monitor the utility voltage, and if it returns to within predetermined voltage and frequency limits and remains there consistently for 30 seconds, the inverter will resume operation. Various integrated circuits have been developed to monitor the grid voltage and frequency and are available on the market to facilitate the implementation of anti-islanding; for example, the Analog Devices part number ADE7753. 
     The presence of an AC component on the array DC terminals has a number of benefits; for example, it facilitates detection of ground leakage faults on the DC side. If the inverter is connected to the utility via a regular two-pole AC GFI breaker, any leakage path on the DC side will result in a 60 Hz imbalance current between neutral and hot on the AC side, thus tripping the breaker. The anti-islanding circuits then detect failure of the utility input and shut off the inverter, opening the output relays. and the combiner relays, effecting an automatic DC disconnect. The two pole GFCI breaker uses one pole to interrupt the hot leg and the other to interrupt the neutral. The breaker pigtail is used to provide the ground connection for upstream equipment so that the sensitivity of the breaker is not affected by capacitive currents to the cable sheath or conduit, but only by an unexpected source of ground leakage. 
     Alternatively, a specific common-mode current transformer can be used on the DC feed to detect any AC current caused by a ground fault on the DC side. A presently preferred wiring method to connect the inverter to the array combiner, and to connect each photovoltaic string to the combiner, is insulated, flexible metallic sheathed conduit also known as Liquidtight (metallic). The flexible metal sheath encloses the DC connections and provides some screening of residual inverter hash. The insulating outer sheath on the Liquidtight also prevents accidental connection with any other grounding source, such as a water pipe, and discourages its unauthorized use as a ground for other appliances or circuits. The sheath of the Liquidtight is ultimately grounded via the GFCI breaker pigtail, if this method of DC ground fault leakage detection is employed. 
     Other benefits in the single phase case of the 60 Hz AC component on the DC conductors concern the specification of relays and fuses. Any disconnecting device, such as a switch, relay, or fuse, must usually be particularly designed and specified to break a DC circuit as opposed to an AC circuit. AC is easier to break, because there are two voltage zero-crossings per cycle that will extinguish any arcing rapidly. In the single-phase case, the inventive converters alternately ground the positive and negative DC conductors. Therefore the voltage on either DC conductor is zero for a whole half-cycle, and not just a zero-crossing. Thus it is permissible to use AC-rated fuses in combiner  700  to protect against shorts to ground of any array wiring. Likewise, the battery fuses may be AC rated rather than DC-rated, or either. In the three-phase case however, DC-rated fuses are required, as the DC conductors do not exhibit voltage zero-crossings or zero periods. 
     For higher power levels, for example 20-100 kw or above, utilities prefer or insist that 3-phase power be delivered equally on all three phases to reduce cable costs and to maintain load balance. In the prior art, a three-phase inverter was constructed using three, synchronized single-phase inverters, and even three separate solar arrays. With the inventive 3-phase inverter design, an integrated 3-phase inverter is provided that operates from a single solar array. It is even more economic, per kilowatt, to construct the inventive 3-phase inverter than the inventive singe-phase inverter, due in large part to the elimination of the need for the large input reservoir capacitors. 
       FIG.  16    shows the principle of a 3-phase sine wave inverter according to the invention. The DC input is applied to three half-bridges that can connect either DC+ or DC-through an LC smoothing filter to each of the three-phase outputs a, b, and c. The three phase utility connection can for example be a 120/208 connection with neutral, i.e., the utility transformer has a Y-configured secondary while most likely having a A-primary. Other three-phase utility configurations are possible. For example, a A-secondary with no neutral can be used. However, the Y-connection is presently preferred so as to allow the RFI filter capacitors to decouple RF interference to neutral rather than ground, for aforementioned safety reasons Also, some means would be needed when using a A-secondary to prevent the system floating to an arbitrary offset voltage—for example leak-resistors to ground from all three phases. The inventive 3-phase inverter can also be adapted to operate with a 120/240/208 volt system having a so called 208-volt “high leg.” In Europe, a common 3-phase voltage is 240/416, which results in an inverter adapted to European voltages supplying twice the power (e.g. 40 kW) for the same current. 
       FIG.  23    shows the inverter voltage waveforms at the output to the utility and on the input DC+ and DC− lines. The half-H-bridges operate according to the following logic: 
     (1) If Phase(a)&gt;0 v and Phase(b) and Phase(c)&lt;0 v then connect DC+ to phase(a).
 
(2) If Phase(a)&lt;0 v and Phase(b) and Phase(c)&gt;0 v then connect DC− to phase(a).
 
(3) If Phase(b)&gt;0 v and Phase(c) and Phase(a)&lt;0 v then connect DC+ to phase(b).
 
(4) If Phase(b)&lt;0 v and Phase(c) and Phase(a)&gt;0 v then connect DC− to phase(b).
 
(5) If Phase(c)&gt;0 v and Phase(a) and Phase(b)&lt;0 v then connect DC+ to phase(c).
 
(6) If Phase(c)&lt;0 v and Phase(a) and Phase(b)&gt;0 v then connect DC− to phase(c).
 
     Operating the switches according to the above logic causes a common-mode AC signal to appear in-phase on DC terminals with a frequency of three times the AC output frequency of the inverter, which is 180 Hz for an output frequency of 60 Hz. The 180 Hz common mode signal is almost a sine wave, and requires less filtering than the 60 Hz square wave of a single phase inverter. It is also possible to construct split-phase inverters according to the invention, the split phase inverter providing two AC output hot leg terminals with relative 180 degree phasing. Alternatively, a two-phase inverter can be constructed according to the invention that provides two AC output hot leg terminals having a 90-degree relative phasing. In the latter case, a Scott-T transformer of the prior art can be used to convert the two-phase output to a three-phase output, if so desired. 
     When a first switch connects a DC input line to one of the phases, the other DC line is simply the DC supply voltage away from that phase in voltage. That other DC line is then chopped at high frequency by other switches to generate, after hash-filtering, the best approximation to the desired voltage difference to the other phase. In particular, the mark space ratio of the chopping action rises to 100% ON at the peak of the phase-to-phase voltage. The phase-to-phase voltage is 120√3=208 v rms for a 120/208 three-phase service, and the peak is a further factor of √2 higher. Thus the solar array is loaded down to a DC voltage of 120√6=294 volts, assuming the AC voltage output is 120 volts rms per phase. With this voltage, the DC+ and DC− lines are seen to execute a near-sine waveform with an amplitude of 45.47 volts peak to peak and at a frequency of three times the AC output frequency. This 180 Hz waveform that is superimposed on the DC lines is not quite a sine wave, as may be determined by computing its spectrum, but is sufficiently free of high frequency harmonics that the common mode filter needed for a three-phase inverter may be simpler than in the single-phase case. Moreover, the instantaneous power delivered to the load is a flatline in the 3-phase case, and therefore the current from the DC supply is also a flatline, and not a 120 Hz waveform, as was the case with single phase. Therefore in the 3-phase case, capacitor C 2  does not have to smooth out a full-current 120 Hz ripple waveform, as it was required to do in the single phase case, and a smaller value suffices to prevent export of inverter hash to the DC circuits. The ripple is low only when connected to a three-phase utility having substantially equal voltages on each phase and substantially the correct 120-degree relative phasing. The utility is normally guaranteed to maintain these parameters within quite tight limits, as otherwise three-phase motors can be damaged; however, fault conditions can arise, such as loss of a phase, which requires monitoring. A simple method to monitor the utility phase and voltage balance is to connect equal value resistors from each phase to a common point, which should then be at zero volts AC relative to neutral. Detecting the residual voltage at this point provides a measure of utility phase and voltage balance. If the measured balance value is outside of a threshold value, a utility input fault condition is declared and the inverter powers down and the output relays are opened. Three small, fused control transformers remain connected to the utility to monitor resumption within correct limits, and also supply power to the control microprocessor and other control circuits even in the absence of solar power at the DC input. Thus in contrast to the load inverter, the grid-tie inverter requires a utility input in order to operate. Without a utility input, the grid-tie inverter cannot supply relay control signals to combiner and DC disconnect unit of  FIG.  27   , and thus the DC input is disconnected at source. 
     The AC outputs of a single-phase or 3-phase grid-tie inverter are also preferably protected against voltage spikes on the utility connection. This can be done by use of gas-discharge tube surge arrestors, for example. Such devices have instantaneous current-sinking ability of thousands of amps, and can tolerate such currents long enough to trip a 60-amp breaker, should the over-voltage transient persist. These should preferably be connected between line and neutral, but in the case of a delta-connected 3-phase service with no neutral, they can be connected between line and utility ground and/or line-to-line. 
     In summary, a 3-phase inverter according to the invention delivers three times the power output of a single-phase inverter using only about the same number of components, and uses a smaller capacitor on the DC input. A 3-phase grid-tie inverter of 21.6 Kw capacity is therefore only of the same order of complexity and cost as a 7.2 Kw single phase load inverter. 
     There are many subtleties in designing such an inverter to back-feed power to the grid.  FIG.  26    shows a vector diagram pertaining to a voltage generator which is presumed to have an inductive output impedance and a vector output voltage of V 1 , connected to a utility grid of vector voltage Vo. The vector difference between (V 1 −Vo) between the generator voltage V 1  and the utility voltage V 2 , divided by the inductive output reactance wL, determines the current flow to the grid. The current lags the voltage across the inductor L by 90 degrees; therefore in order for the current to be in phase with the grid, i.e., a horizontal vector, the difference voltage (V 1 −Vo) must lead by 90 degrees, i.e., be a vertical vector. Thus either the generator phase must be advanced from ϕ1 to ϕ2, or else the voltage must be reduced below V 1  in order to rotate (V 1 −Vo) to the vertical position, or even both the phase and the voltage must be adjusted. 
     In the case of the grid-tie inverter, the generator voltage V 1  is proportional to the array voltage and the array voltage is inversely dependent on the current taken from the array, which is proportional to the component of the current in phase with the utility, i.e., the projection of the current vector on the horizontal axis. Moreover, since wL is by necessity a very small reactance, (V 1 −Vo) is a very short vector, of the order of 1 to 2 volts, and the sensitivity of the current phase to changes in array voltage and thus V 1  is very high. It may be deduced that changes in the generator phase ϕ cause large changes in current magnitude while changes in array voltage and thus V 1  cause changes in current phase, but, to a first order, not its magnitude. Thus proper operation of the grid-tie inverter requires controlling the generator phase advance relative to the utility to adjust the current magnitude until the array is operating at a desired point, i.e., the maximum power point (MPP). One strategy is thus to advance the inverter phase (which increases the output current) if the array current is too low and thus the array voltage is too high, or conversely to retard the phase if the array voltage is too low because the current is too high. A simplified strategy is to control the phase of the inverter such that the phase of the current is in phase with the utility, i.e., to control the inverter phase such that the voltage across the inductor L has a phase that leads the utility phase by 90 degrees. If this results in too little current, such that V 1  increases, the result will be that the current will lag the utility, and the generator phase shall then be advanced, increasing the current and reducing V 1 . Conversely, if the current is too high, causing V 1  to reduce, the current phase will advance over the utility phase and thus the inverter phase will then be retarded to bring the current into phase with the utility. Maximum power point tracking is then approximately achieved at the same time as synchronizing the inverter to the grid. 
     The phase of the voltage across the inductor L 1  ( FIG.  15   ) or La, Lb, Lc ( FIG.  16   ), which are the switch-mode smoothing inductors, is simply sensed by adding a secondary winding thereto, or else by adding a secondary winding to the following RF hash filter, and feeding the secondary voltage to a zero-crossing phase detector. The secondary winding senses the derivative of current. The secondary voltage may thus first be integrated to obtain a 60 Hz current-related signal. The phase detector simply comprises logging the count in a master clock counter at which a current zero crossing occurs and determining if it was early or late. This shall be done for all three phases in a 3-phase system, and either a mean taken, or else each phase can be separately controlled from its own sensor coil. 
     The three phase inverter of  FIG.  16    is a simplified circuit, and has the characteristic that the DC input is not switched to connect directly with any AC output terminal, but rather connects it through the smoothing inductors La, Lb, or Lc to one of the output terminals. This has the result that some of the high frequency switching waveform is transferred to the DC input, which would require a more complicated DC input filter.  FIG.  24    shows a switching arrangement to avoid this and to ensure that, at the appropriate time, a DC input line that is selected to connect to an AC output terminal is directly connected to that output terminal, bypassing the associated smoothing inductor La, Lb, or Lc. 
     Referring to  FIG.  24   , in period 1 of the three-phase cycle, Phase a and Phase c are positive or zero while Phase b is negative. According to the above-described switching logic therefore, the Phase b output terminal shall be directly connected to the DC negative input line. This is done by turning on TR4b to conduct. Just prior to period 1, Tr2b was executing a switching cycle with varying duty factor, the duty factor having just reached 100% at the beginning of the period. Thus TR2b is also left conducting when Tr4b is switched on, and shares the load current with Tr4b. At the end of period 1, phase b and phase c transition to negative while phase a is positive. Accordingly, the phase-a output terminal shall be directly connected to the DC input positive line. This is done by turning on Tr3a. Just prior to period 2, Tr1a had been switching but had reached a 100% duty factor. Therefore Tr1a is left 100% ON to share the load current with Tr3a. At the actual boundary between two periods, for example at the boundary of period 2 and period 3, the switches operate according to the “Tarzan principle”—that is, do not let go of one vine until grabbing hold of the next one. Thus for an instant, Tr1a and Tr3a are connecting the DC positive input line to the phase-a output terminal while TR2c and Tr4c are connecting the DC negative line to the phase-c output terminal. In this way, the DC input is always anchored by either its negative line or its positive line to one of the three phase output terminals. 
     It can be mentioned that, to obtain proper relative phase of the switches taking into account the delay through inductors La, Lb, and Lc, the switching waveforms of Tr1a, Tr2a, Tr1b, Tr2b, Tr1c, and Tr2c may be slightly time-advanced relative to the switching waveforms of Tr3a, Tr4a, Tr3b, Tr4b, Tr3c, and Tr4c. This time advance corresponds to the phasing of the generator relative to the utility voltage discussed in relation to the vector diagram of  FIG.  26   . Thus the phase advance of the waveforms for switches Tr1a, b, c and Tr2a, b, c is adaptively controlled to make the AC output current lie in phase with the utility voltage while switches TR2a, b, c, and TR4a, b, c operate in a fixed relationship to the utility voltage. 
     It can be mentioned that the testing of high power converters to confirm efficiency and adequate heat dissipation at maximum load can consume a considerable number of kilowatt hours. It is also difficult to measure efficiencies in the 98-99% region by measuring the input DC power and output AC power with different instruments. A 1% measurement inaccuracy can lead to the erroneous conclusion that an inverter is more than 100% efficient, or that it is less efficient than it really is. A presently preferred method to test an inverter is therefore to rectify the AC output with a rectifier circuit especially designed to consume a sinusoidal current in phase with the voltage, and to feed the DC back into the inverter input. The inverter DC source need then only supply the difference between the input and output power, i.e., the amount of power wasted in inefficiency, plus the rectifier circuit inefficiency. This is both a more accurate and more cost-effective way of testing inverters. 
     The grid-tie inverter described herein may be operated in reverse to transfer energy from an AC source to a DC load. It simply requires programming the phase control circuit described above to ensure that the phase of the voltage across the series smoothing inductor is 90 degrees retarded with respect to the AC voltage. Power will then flow from the AC to the DC circuit. As illustrated in  FIG.  26   a   , for rectifier mode, the amount of phase retard should be controlled to produce the desired amount of AC load current and thus rectified DC current while the voltage V 1  is controlled by adjusting the switching waveform duty factor to make the AC current in phase with the AC voltage. The same circuit arrangement can thus be used with an alternative control regime to make a rectifier which presents a linear load of low power factor to the AC supply. This is useful for inverter testing as described above, and is also useful for high power battery chargers for electric vehicles where it is desired that they should present a linear load to the utility. 
       FIG.  18    shows the block diagram of an electrical installation employing the first load inverter implementation to provide a household with solar-generated AC power. A solar array comprising one or more strings of solar panels is installed on a south-facing roof for example, and any exposed metallic parts other than its electrical terminals shall be returned to ground via a grounding conductor to give some degree of protection against thunderstorm transients. Each string of panels connects to solar combiner  700  therefore using three conductors—the DC positive, the DC negative and the grounding conductor. The preferred wiring method between a string of solar panels and the solar combiner is to use Liquidtight flexible metallic conduit (LFMC) to carry the positive and negative lines of at least one string as well as an array grounding wire. The metallic sheath of the Liquidtight should also be bonded to the array frame (if metal), and the solar combiner case, thus effectively providing a coaxial connection. Such a coaxial connection is a superior method of preventing thunderstorm transients entering into the signal and power paths. The 2008 National Electrical Code suggested the use of a separate grounding rod for the array when the array was remote from other equipment. However it was recognized that this could be inadvisable and that requirement was removed in the 2011 version of the Code. For installing systems using devices according to this invention, all grounding shall be routed back to the common premises grounding electrode system. This may consist of more than one grounding rod or electrode, however all grounding electrodes must be connected together on the load center side of the inverter and no other ground shall be connected to the installation on the battery or array side of the ground leak detector. 
     As already described, solar combiner  700  selectively combines the currents from multiple strings of solar panels according to relay control signals presented to its control port  1 . Standalone inverter  1000  is connected to control port  1  via a 9-conductor cable, for example an 8-conductor-plus-braid Cat 5 cable, or a DB9 serial port cable, and controls the string selection in order to maintain the voltage of battery  500  within desired limits. To avoid prejudicing operation of the ground leak detection function, the braid of the Cat 5 cable or ground return of a DB9 cable must not be connected to the ground or any part of the DC circuit inside the combiner. The relay coils provide this desired isolation. One method, which requires monitoring only the battery voltage, progressively switches out strings of panels when the battery voltage approaches a target value. For example, suppose battery charging is operating in the float charge regime where the battery voltage shall be maintained at approximately 135 volts for 60 lead-acid cells in series. If the battery voltage is less than 120 volts, all strings are selected to charge it. As the voltage approaches 135, strings are switched out depending on the rate of approach, which is determined by battery-voltage monitoring circuit that can be contained within controller  202 . For example, if the voltage is 126 volts and rising at the rate of 0.2 volts per second, it can be predicted that the voltage will reach 135 volts in 45 seconds. Thus in five seconds, one string is switched out. If the battery voltage one second later is less, one more string is switched back in. If on the other hand the battery voltage continues to rise such that it will reach the target voltage in less than 45 seconds, one more string will be switched out. The foregoing description of float charging is merely intended to be exemplary of all possible methods of controlling battery charging when only monitoring battery voltage. Preferably, the battery charge controller would also be able to monitor net battery charge current. This requires a current sensor at the battery such as a very low resistance current shunt (not shown) with a pair of dedicated wires back to the DC-AC converter  1000 , where the battery charging logic and control resides. 
     The combined current from the selected strings is routed from solar combiner  700  to battery  500 , again using preferably LFMC to maintain a coaxial path. The trade size of Liquidtight shall be sufficient for the gauge of conductors needed for the total current of all strings, plus an equipment grounding conductor used together with as the Liquidtight metal sheath to transport the equipment ground. Battery  500  shall be housed in a suitably ventilated enclosure to dissipate any hydrogen out-gassing safely to the outside. The housing may include a perforated metal or foil screen which then should be bonded to the Liquidtight sheath and the equipment grounding conductor. The 2008 National Electrical Code leaves it optional whether the battery wiring includes fuses. Since a large storage battery is a source of potentially huge fault current in the event of a short in the wiring, it is highly recommended that fuses be installed as close to the battery as possible. At least two fuses are required for this purpose. For example, one fuse may be inserted in the positive connection from the combiner  700  and a second fuse is then inserted in the positive connection to the inverter  1000 . A common fuse in the battery connection must not be used, as in the event of its blowing, the array would be left directly connected to load inverter  1000 , which is an unstable arrangement. Four fuses ( 550 ) may also be used, connecting one in each of the positive and negative conductors to and from the battery, as shown in  FIG.  18   . 
     Liquidtight flexible metallic conduit  400  or other metallic conduit is used to route the wires from battery  500  through the ground leak detector comprised of items  800 ,  801 , and  802  to inverter  1000 . The conduit and its enclosed positive, negative, and ground conductors pass in their entirety through a large, high-mu ferrite toroid  800 . A suitable toroid is Magnetics Inc. part number 4916 in W material with a mu of 10000. The inner diameter of this toroid is 33 mm. This accommodates trade size ¾ ″ LFMC. This size LFMC accommodates three #4 AWG THWN-2 conductors, which are good for 95 amps continuous. The grounding conductor may be of a smaller gauge, for example #6 AWG. Toroid  800  is wound with about 100 turns of relatively fine wire, such as #20 AWG, as it does not have to pass any current. This forms a 1:100 voltage step-up transformer between the net current flowing in the conduit and its conductors, which should be zero if there is no ground leak on the battery/array side of the toroid. The 100-turn secondary has an inductance of 118 mH while the effective 1-turn primary has an inductance of 11.8 uH. A 60 Hz imbalance current in the conduit of 6 mA will cause a primary voltage of 0.0267 mV and a secondary voltage of 2.67 mV. The sensitivity may be increased by adding capacitor  802  to roughly resonate the secondary inductance of 118 mH. A 60 uF capacitor resonates the inductance and also suppresses signals at other than 60 Hz, such as medium wave radio stations, or nearby amateur radio transmissions. A load resistor of 220 ohms keeps the Q-factor of the resonant circuit below 5 and thus insensitive to small component variations. With a Q of 5, the induced voltage due to a ground leak current of 6 mA rises to 13 mV. An amplifier inside inverter  1000  amplifies this voltage and compares it to a threshold. If it exceeds a threshold corresponding to 6 mA, the inverter executes a shutdown, controlling the combiner to the DC disconnect state and opening both the inverter AC output relays and the DC input power and start-up relays. This completely isolates the array from the battery and ground, and the battery from the inverter and ground, thus preventing any further ground leakage current. Thus personnel coming into contact with either DC conductor are prevented from receiving a shock of greater than 6 mA AC. Since the DC voltage for a single phase converter is similar to the AC voltage, this also prevents a DC current flowing of this magnitude. The purpose of passing both the conduit and its enclosed conductors through the ground leak detector toroid is so that capacitively coupled current from the current-carrying conductors to the conduit, array frame, or battery box do not cause an imbalance current through the toroid which could reduce sensitivity or cause spurious tripping. However, there are instances when such current due to a gross fault should be detected, as will be described more fully herein. 
     A standalone solar installation may also be used in conjunction with utility power. A common form of low-cost installation is where the solar power is routed via a transfer switch to a “subsistence panel,” which is an electrical load center that supplies power to the most important appliances that need to be kept running in the event of utility failure. For example, the subsistence panel may feed lights, power points for TVs, radios, computers, fridge, freezer, water pump, and microwave, but may not attempt to feed heavy consuming appliances such as HVAC, tumble dryer, or electric stove. The transfer switch allows either utility or solar power to be selected to feed the subsistence panel. Other, heavier loads such as HVAC are connected to a regular load center fed only by utility power. Alternatively, a transfer panel may be used, which comprises a number of switches that select, for each appliance or circuit, whether they take their power from the utility or the solar panels. The transfer switches can be left in a position wherein the total normal load may be handled continuously by the solar array/battery combination with typically expected hours of sunlight, while preserving the ability to temporarily feed any other appliances from the solar system should an emergency need arise, or feed any load from utility in the event of a prolonged period without sun. 
     Existing transfer panels tend to be of one of two types: either they transfer all loads from one supply to the other, manually or automatically, which assumes the alternate supply is a generator powerful enough to take the whole load, or of a second type that can manually transfer each circuit independently. The per-circuit type does not seem to be readily available with automatic load transfer switching, possibly because no criteria had existed for transferring only some loads and not others. Moreover, the per-circuit type generally comprises two sets of circuit breakers, one set for the utility supply and a second set for the alternate supply. A transfer switch may be connected after the breakers, or else the breaker pairs may be mechanically interconnected such that when one of a pair is on, the other is off. Changes to the Electrical Code in 2008 however required the use of arc-fault breakers (AFCIs) on many circuits, such as bedroom circuits, and many of the remaining circuits use GFCI breakers. AFCI and GFCI circuit breakers are more expensive, so the aforementioned per-circuit transfer switch load center would now be significantly more costly, since it would require two AFCIs or GFCIs per circuit. Accordingly there is a need for a more economic form of per-circuit load transfer switching for intelligent load management. The outline of a smart transfer panel  3000  that provides intelligent load management is shown in  FIG.  22   . 
     In  FIG.  22   , in contrast to the two power busses that normally extend down the center of the panel and into which circuit breakers are connected, there are now four power busbars—two for solar power and two for utility power. Quadruple busbar  3009  is sized to handle 60 amps on each solar input lug L 1  and L 2  ( 3001 ) and 60 amps on each utility power input lug L 1  and L 2  ( 3002 ). The panel of  FIG.  22    is intended to be a sub-panel and is fed from a 60 A, two-pole breaker in the main service panel. The solar input derives from solar inverter  1000  and is already current limited. A phase-splitting auto-transformer may be used with inverter  1000  to provide the two anti-phase hot legs L 1  and L 2  ( 3001 ). The transformer need only handle about half the power output of the inverter, if load is evenly balanced between L 1  and L 2 . In a larger installation, two load inverters synchronized 180 degrees out-of-phase and two battery banks can be installed to provide 7.2 Kw on each of L 1  and L 2 . One array can be used with combiner  700  to charge both battery banks alternately, or else two isolated sub-arrays may be used, as it is not possible to power two anti-phased inverters from the same array without additional isolating devices that cause a few percent additional efficiency loss. When one array and combiner  700  is used with two inverters, each inverter may be given first priority control over half of the strings and second priority control over the other half of the strings. 
     Single Pole, Double Throw (SPDT) relays  3003  are used to select power either from one of the solar power busbars or from a utility power busbar. Each Group of 8 relays may be driven by a relay driver chip such as the aforementioned Texas Instruments part number TPL9201. The circuit breakers ( 3004 ) on one side are wired to select solar power in the unenergized state while the circuit breakers ( 3005 ) on the other side are wired to select utility power in the unenergized state. On each side, the breakers alternate between selecting L 1  and L 2 , such that a pair of adjacent slots may be used for a double pole (240-volt) circuit such as a well pump or dryer. The source of power selected by each relay  3003  is routed to its associated breaker through a toroidal core  3008  upon which a secondary is wound to provide a current sensor for each circuit. The current sensor outputs connect to one or more coherent measuring chips such as the aforementioned Analog Devices part number ADE7753 which provides a microprocessor interface for reading current, voltage, power, and power factor. The 16 current sensors may be multiplexed to a single ADE7753 using analog multiplexers and measured sequentially approximately once every one or two seconds. This is sufficiently frequent to capture most circuit on/off switching activity and give a reasonable measure of average power consumption per circuit. The relay coils may be wired to relay driver circuits such as Texas Instrument part number TPL9201. These also have microprocessor interfaces that permit a microprocessor to control the relays. A microprocessor board (not shown) has inputs for the current sensor signals, power from both solar and utility via small control transformers, interfaces with any user controls and displays, and with external computers such as a PC, and provides control signals to the relays. Software then implements the intelligence to manage the loads, examples of which are as follows. 
     The user or installer may set up the smart transfer panel upon installation either via front panel push buttons or by connecting to a PC which can provide a more user-friendly interface. Set up may include initializing a time-of-day clock, determining from which source each load normally derives its power and setting the criterion for changing the selection. For example, each circuit can be programmed to be one of: 
     1. Always solar, never utility.
 
2. Normally solar, priority 1; utility back up.
 
3. Normally solar, priority 2; utility back up.
 
4. Normally utility; priority 1 for solar back up.
 
5. Normally utility, priority 2 for solar back up.
 
6. Always utility, never solar.
 
     The above list is not intended to be exhaustive, and there may be other regimes, such as different selection depending on time of day, more than two priorities, etc. The purpose of priorities is to anticipate what the user would ultimately want to do in the case of a long utility outage and lack of sun. In the limit when energy runs out, it will be necessary to shed load in order to prioritize the most important appliances. For example, lights could have first priority during the evening and nighttime while well pump, computer and cordless telephone power outlets had first priority for solar energy in daytime. These time-of-day dependent algorithms may be built in with the help of a real time clock chip or software program so that the operation that the user would wish will be automatic if the occasion arises. 
     The smart transfer panel may also communicate with inverter  1000  to receive information on the availability of solar power, which can depend on the state of the battery, which is monitored by the load inverter. If utility power is available, i.e., there is no outage requiring emergency power from solar for loads that would normally be powered from the utility, then it is desirable that the battery would not normally be discharged to a depth of more than 20% in any day. Therefore, if the battery reaches a threshold depth of discharge that should not be exceeded except in an emergency, the inverter can inform the smart transfer panel to begin shedding load from solar and transferring load to the utility. On the other hand, if utility power fails, those loads would instantly be transferred back to solar and the battery would be permitted to be fully discharged. Before full discharge is reached however, at some intermediate point load would start to be shed according to the pre-programmed order of priorities. 
     One feature of the software can be that the smart transfer panel attempts to avoid relay switching under load, in order to maximize contact life. If transferring power from one source to another is not an instantaneous imperative, the current sensors can provide an indication of a low-load period in which to perform load transfer. In addition, the inverter  1000  may be provided with a 60 Hz synchronizing pulse from the transfer panel so that power transfer is phase-synchronous and substantially glitch-free. 
     The smart transfer panel preferably also has an interface for a PC, for example, an RS232 interface. A wireless interface using Bluetooth or WiFi is also conceivable. The PC interface circumvents the limit on the amount of program memory that it is economic or sensible to attach to a small microprocessor such as is envisaged to be included in the smart transfer panel. Coupling to an external PC allows the PC to host additional software and provide full keyboard, mouse and display user interfaces, color graphics and suchlike. It can also, via the internet, allow remote monitoring or maintenance of an installation, and has access to the entire internet as a resource. For example, weather forecasts received from the internet can help anticipate solar irradiation (insolation) and manage the energy consumption accordingly. Historical records of insolation by season or date are also available on the internet for such purposes. The PC interface can also display to the user his energy consumption on each circuit and how much derived from solar and utility respectively, as well as these usages versus time of day, day of week, month, season, or year. Thus the use of a smart transfer panel in a hybrid solar/utility power installation can provide many benefits as well as the tools to manage energy consumption for greater economy. 
     The sizing of a standalone system is more critical than the sizing of a grid-interactive system, as sufficient power must be provided for the maximum load in the season of minimum insolation, but then the excess is wasted at other times of lower load or higher insolation. A hybrid solar/utility installation with a smart transfer panel and load center as just described relaxes the need to avoid undersizing the solar source and helps to use excess power, but does not derive great benefit from oversizing. To derive benefit from much larger solar arrays, it can either be arranged to power some of the heavier house loads such as HVAC to beneficially absorb excess solar power, or else a grid-tie inverter can be added to return excess power to the grid. Firstly, a system having only grid-inter-tie will be described with the aid of  FIG.  17   . 
     The grid-tie installation shown in  FIG.  17    has been deliberately drawn to emphasize the similarity with the standalone installation of  FIG.  18   . The most noticeable difference is the absence of the battery  500  of  FIG.  17   , and the use of grid-interactive inverter  2200  (single phase version, as illustrated in  FIG.  15   ) as opposed to the standalone inverter  1000 . The array now connects directly to the grid-interactive inverter  2200 , which, since it is the only user of the array power, connects to combiner priority 1 output and priority 1 control port. The connection to the control port is used to provide a remotely-activated DC disconnect function. 
     The single-phase grid-interactive inverter impresses substantially the same common-mode signal of the same 60 Hz frequency on to the DC conductors as the standalone inverter, and thus the same ground leak detector ( 800 ,  801 ,  802 ) can be used. It is alternatively possible to use a 60 Hz AC, two-pole GFI breaker on the AC output, the two breaker “line” poles being used unconventionally for the hot and neutral while the pigtail and breaker neutral are used to convey the equipment ground to the solar system. This arrangement requires that the breaker be installed in a special sub-panel that is wired in the above way, and not in the main service panel ( 4030 ). Alternatively the breaker may be pre-wired into converter  2200 . 
     The ground leak detector comprised of items  800 ,  801 ,  802  measures the imbalance current between the DC positive line, the DC negative line and the ground line including the encircling conduit. To do this, the conduit and its entire set of contained conductors passes through the center of the toroid. Currents caused on the ground conductor or in the conduit by capacitive coupling of the AC ground-leak probe signals from the DC conductors are thereby balanced out and do not cause false tripping or adversely affect the ground-leak detection sensitivity. High sensitivity may thereby be achieved for the purposes of protecting personnel from shock. For this function, the array end of the conduit and the array frame must not be connected to any local ground, but should only be grounded via the metallic conduit and the grounding conductor contained therein back through the leak detector to the main system ground. 
     Current solar systems ignore personnel shock risks and employ ground leak detectors on the DC side purely to warn of malfunction and to protect against excessive currents. For example, in some systems, the conduit and grounding conductor contained therein may be connected by a fuse to the main system ground, which blows in the event of a short to the conduit or other grounded metal part, such as the array frame, leaving the array and conduit ungrounded. The inverter must switch off under such circumstances and both DC conductors must be disconnected to isolate the DC circuit and prevent current flow. A warning sign must be placed at appropriate locations warning that, in the event of a ground fault being indicated, conductors that are normally grounded may no longer be grounded and may be at hazardous potentials. 
     Using the inventive ground leak detection principle described herein, an improved form of protection of the DC circuit from excessive currents may be contrived. By using a second toroidal core, the DC conductors may be passed through the core without passing the conduit and grounding conductor through the core. Upon occurrence of a ground fault, the AC probe signal current in the ground conductor passing around the outside of the core will not cancel the AC probe current in the DC conductors, but will enhance the coupling to the toroid secondary, thus providing a strong, easily detectable signal in the secondary indicative of a gross ground fault that is easily distinguished from capacitive currents by its much larger magnitude. This indication may be detected in the inverter and cause it to immediately shut down, opening the input relays in the DC circuit, the output relays in the AC output circuit and removing the relay drive signals to the remote-controlled combiner and DC disconnect. Both variations of the ground leak detector are illustrated in insets A and B of  FIG.  17   . Inset A shows the conduit as well as the DC+ and − conductors passing through the toroid, while inset B show only the DC conductors passing through the toroid. The former (A) can detect very small leakage currents to ground other than the conduit or equipment ground on the array side of the detector, while the latter can detects heavier ground leaks from the DC conductors to the conduit or equipment ground. 
     When ground leak detectors as just described are used, the AC output of inverter  2200  is wired to a single-pole,  60  A breaker ( 4040 ) in the main service panel ( 4030 ) or in a conventional sub-panel which connects to the main service panel. The main service panel ( 4030 ) houses the main AC disconnect for the solar system. When the AC disconnect is operated, the anti-islanding protection required by specification UL1741 operates and shuts down inverter ( 2200 ); this in turn removes control power from control port  1  of combiner ( 700 ) causing the DC disconnect relays to open. An OFF switch on the inverter can also be used to operate the DC disconnect function, as can a switch locally at combiner  700 . 
     In the grid-tie system of  FIG.  17   , array  1500  may need to output a higher DC voltage than in the standalone system of  FIG.  18   . If the standalone system of  FIG.  18    uses a nominally 120-volt battery, float charged at say 135 volts, then the array should deliver power efficiently at 135 volts. It may also be required to deliver a voltage somewhere in the range 140 to 144 volts for bulk, absorption and equalization charging. A fuller discussion of array-to-system voltage matching is given later in connection with implementing bimodal systems. 
     The main service panel of a residential system receives its power from, in the USA, a split-phase 120/240-volt single-phase service drop or service lateral ( 4010 ). The service drop usually comprises three wires—two 120 volt rms hots 180 degrees out-of-phase with each other, and a neutral. The neutral is likely already grounded at the utility pole transformer or pad-mounted transformer, but is also bonded in the main service panel to the local grounding system provided by grounding electrode  1010 . The two hot lines from the service drop pass through the meter to the main service panel. 
     One of two possible metering regimes may be used. 
     In “net metering,” other building loads are supplied by other breaker circuits from main service panel ( 4030 ), and the meter clocks up the net difference between power imported to power the loads and power exported from grid-tie inverter ( 2200 ). 
     In “dual metering,” a separate export meter is connected between grid-tie inverter ( 2200 ) and the service drop. Thus the service drop ( 4010 ) may feed two main service panels through two meters—one for power imported and one for power exported. Power exported may be remunerated at a lower or higher rate per kilowatt hour than power imported is charged, as distinct from net metering, which provides a one-to-one offset of imported power by exported power. 
       FIG.  17    shows a single-phase system typical of a residential installation. However, using 3-phase versions of the inverter that have been explained above using  FIGS.  16 ,  23 ,  24   , and  26 , a connection to a three phase service drop can be made. Typically in the USA, the 3-phase service drop would be a 120/208 volt service, but with suitable voltage scaling, an array and inverter can be adapted to a European 240 volt, single phase service, a European 240/4163-phase service, a US 277/480-volt service, or even a US 120/240-208 volt split-phase plus 3-phase service having a 208-volt “high leg.” It is preferred to connect a grid-tie system to the lowest available service voltage in order to minimize the maximum DC voltage of the array for reasons of personnel safety. When a 120/2083-phase connection is used, the array voltages are nominally 294 volts between the positive and negative DC lines and 147 volts from each to ground. The shock potential from a 147-volt to ground DC line is much less than that of a 120-volt AC line. 
     Because the grid-tie system of  FIG.  17    is the simplest and lowest cost to provide, it is the fastest growing type of solar electric installation. However, many people are surprised and disappointed to learn that, if the utility fails, they do not have power. This is partly because of the anti-islanding requirement, but also due to the absence of the battery, which is required to stabilize the array voltage when the load is variable. Consequently it is of interest to be able to construct or upgrade either  FIG.  17    or  FIG.  18    to a “bimodal system” which provides both grid tie and battery back-up. 
     There are many ways to construct a bimodal system. A bimodal inverter cannot necessarily operate in both modes simultaneously, although the XANTREX SW4012, 4024 and 4048 can be integrated very well to provide both modes of operation and automatically switch between the two appropriately. One way to use the inventive inverters of this application to construct a bimodal system would be to install two separate systems according to  FIGS.  17  and  18   , respectively. However, it is desirable to share parts such as the array  1500 , the combiner  700 , the DC wiring, ( 400 ), the ground leak detector(s) ( 800 ,  801 ,  802 ), and so forth.  FIG.  19    shows a bimodal system sharing these common parts. Since the single-phase grid-tie inverter employs an array voltage of 170 volts and the standalone system requires 135-144 volts for battery charging, a discussion of array voltages, efficiencies, and how both requirements can be satisfied is appropriate. Of course, one solution is to operate the standalone inverter at 170 volts, as was shown above to be perfectly feasible to include during its design, but then a 168 volt battery comprising 14, 12-volt units in series would be required, instead of the ten mentioned previously to achieve 120 volts. This would have the advantage of providing 16.8 kilowatt hours of back-up capacity, but at greater cost. There is another argument however that can be used to reconcile different DC voltage requirements of the standalone and grid-tie inverters. 
     First of all, the voltage-current characteristics of solar cells will be explained with the aid of  FIGS.  20  and  20     a.    
       FIG.  20    shows that a photovoltaic cell is a current source of photocurrent  11  in parallel with an intrinsic diode D 1 . In the absence of an external load, the photocurrent flows through the diode in the forward-biased direction causing the diode to develop a potential across its terminals which is equal to the typical voltage drop of a forward biased diode of around 0.6 volts. Whatever the technology, diode I-V curves are given by Shockley&#39;s equation: 
         I ( V,T )= I sat[exp(β qV/kT )−1]  (1)
 
     where I(V,T) is the current at voltage V and temperature T;
 
Isat is the diode saturation voltage (leakage current when reverse biased);
 
q is the charge on an electron;
 
k is Boltzman&#39;s constant;
 
T is absolute temperature in degrees Kelvin, and
 
β is an ideality factor which is between 55% and 80%, i.e., 0.55 to 0.88 for silicon diodes.
 
     At 25 degrees C., kT/q is about 26 millivolts, so the equation (1) simplifies to: 
         I ( V,T )= I sat[exp(β V/ 0.026)−1]  (2).
 
     If the solar cell of  FIG.  20    is shorted, the diode voltage will be zero and will take no current, so all of the photocurrent  11  comes out. This is by definition the short circuit current Isc of the cell. When the solar cell is now open circuited, the current Isc flows into the diode which is therefore the value of I(V) given by equation (2), and which can be inverted to give V, now the open circuit voltage of the solar cell Voc, as: 
         Voc =(0.026/β)Log e ( Isc/I sat+1)  (3).
 
     Since Isc and Voc are externally measurable, the values measured at 25 degrees C. in full sun, known as Standard Test Conditions, may be substituted in equation (3) to obtain the unknown Isat for the diode as: 
         I sat= Isc /[exp(β Voc/ 0.026)−1]  (4).
 
     Now substituting for Isat in equation (2), the diode current at any other voltage V is found to be: 
         I ( V )= Isc [exp(β V/ 0.026)−1]/[[exp(β Voc/ 0.026)−1]  (5).
 
     The current output by the solar cell is the photocurrent Isc minus the diode current, that is: 
     
       
         
           
             
               
                 
                   
                     I 
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     A typical monocrystalline silicon solar panel in current production comprising 72 series connected cells has the following characteristics: 
     Maximum Power 195 watts
 
open circuit voltage Voc=45 volts
 
short circuit current Isc=5.45 amps
 
voltage at maximum power Vmp=38.3 volts
 
Current at maximum power Imp=5.09 amps.
 
     From the above, the per-cell voltages may be deduced as: 
         Voc= 45/72=0.625 and  Vmp= 0.532. 
     Substituting in equation (6), the whole I-V curve of this cell may be computed and the voltage scale multiplied by 72 to give the whole I-V curve for the panel. The power may also be plotted by computing the product of I and V. This is shown in the curves of  FIG.  20   a   . It is found that these highly efficient cells have an ideality factor of about 74% and a light-to-electricity conversion efficiency over 18%. 
     The diode voltage of a photovoltaic cell exhibits the same temperature coefficient of −2.16 mV per degree C. as other silicon diodes. Solar panels are deliberately exposed to full sun and therefore tend to rise above the Standard Test Conditions temperature of 25 degrees C. when fully illuminated in the summer. Typically, they might reach 50 degrees C., so the open circuit voltage VOC will drop by 25×2.16 mV per cell or 3.9 volts for a 72-cell panel. At the coldest winter temperatures, say −15 degrees C., the Voc of the panel may rise by 6.2 volts. These two extremes are plotted in  FIG.  20   b   . If four of these panels are strung in series, it can be seen that, at the high temperature extreme, the voltage range 132−144 volts, which is the exact range desired for battery charging, is around the peak power point, and peak power is about 175 watts. If the array is loaded to the same voltage range at the low temperature extreme, the power is in the range 180−197 watts per panel. For the single-phase grid interactive inverter requirement of 170 volts however, four series panels are not enough at the highest temperature, although they would be perfect at the low temperature extreme. If on the other hand 5 panels are strung in series, the 170 volts required for the grid-tie inverter lies at the maximum power point of about 175 watts per panel at the high temperature extreme, while the battery float charge voltage of 135 volts is sub-optimum, at about 145 watts per panel. 
     In such a bimodal system, the economic benefit is primarily obtained by the grid-tie system using net metering or dual metering. The purpose of the battery and standalone inverter is purely to provide back-up in the event of a utility outage. Therefore little energy is normally drawn from the battery system and the array is only used to keep the battery float charged, for which it is sufficient that the combiner  700  occasionally divert one panel from grid-tie to battery charge maintenance. Therefore the efficiency of battery charging from the array is unimportant, and the array voltage should be optimized for best grid-tie operation. Five of the illustrative panels would therefore be used in series per string, to provide a maximum power point at 170 volts at maximum cell temperature, and upon diverting a string for the purposes of battery float charging, the diverted string would be loaded down to the slightly less optimum voltage range of 120-140 volts. 
     The bimodal system of  FIG.  19    thus comprises a nominally 170 volt array  1500  that operates at its most efficient point when driving the grid-tie inverter. Each string of the array is selectively combined by combiner  700  either to feed the grid-tie inverter or to charge the battery. The battery is connected to the priority 1 output port of combiner  700  and standalone converter ( 1000 ) controls the string selection for battery charging via control port  1 . Strings not selected for battery charging are available to be selected by the grid-tie inverter  2200 , which would usually select all available strings. Thus there are two combined outputs from combiner  700  each comprising a DC positive and a DC negative conductor. These four, high current conductors are contained within the same conduit in order to pass together through the same DC leak detector ( 800 ,  801 ,  802 ). The DC leak detector may be provided with a second winding to feed detectors in both the grid tie inverter and the standalone inverter, as both will have such detectors built in. This provides continuous ground leak detection, should one or other inverter be taken out of service or switched off. Standalone converter  1000  provides a single hot leg of 7.2 Kw which is split into two anti-phase hot legs by autotransformer  1700 , to permit the driving of 240-volt loads as well as 120-volt loads. These two solar-derived hot legs connect to busses  3001  of Smart Load Center  3000 . DC power for grid tie inverter  2200  is split off after the ground leak detector. The AC output of grid-tie inverter  2200  connects to a 60 A single-pole breaker in the service panel, or a suitable sub-panel fed from the main service panel. The service panel (or suitable sub-panel) also houses a two-pole breaker supplying utility power to Smart Load Center  3000 . 
       FIG.  19    shows a communication and synchronization buss connecting the Smart Load center  3000 , grid-tie inverter  2200  and standalone inverter  1000 . The communications buss  1750  employs opto-isolators at the receiving ends to avoid creating ground loops, and serves the following functions: 
     First, a grid derived 60 Hz sync pulse is supplied to standalone inverter  1000 , of such phase that both grid-tie inverter  2200  and standalone inverter  1000  are connecting their respective negative DC input terminals to neutral at the same time, thereby ensuring that the phase of the common mode ground-leak probe signal is the same for both. This is not an essential requirement for operation, but considered desirable. Moreover, it is desirable to synchronize inverter  1000  with the utility grid to facilitate glitch-free changeover from utility to solar by Smart Load Center  3000 . 
     Second, the inverter  1000  can communicate the availability of solar/battery power to Smart Load Center  3000  in order to implement prioritized load-shedding in the event of a prolonged utility outage. 
     Third, the Smart Load Center  3000  can receive status flags from both inverters  1000  and  2200  and periodic reports of current delivered to the grid from inverter  2200 , so that, in addition to battery status from inverter  1000  and AC circuit current measurements from its own per-circuit current sensors, all information may be collated for communication if desired to a PC via an RS232 connection, and to receive commands from a PC for remote control of the system via more user-friendly software. It is not envisaged that high data rates would be needed on buss  1750 , and a baud rate of 60 bauds is envisaged between units  1000 ,  3000 , and  2200  to be sufficient. 
       FIG.  28    illustrates the simplified circuit of an inverter  5000  having two sets of power output terminals, each with two hot legs (1 and 2) and a neutral. Each pair of hot legs may be the anti-phase 120 volt 60 Hz legs of a U.S. split-phase installation. Alternatively, the inverter  5000  could have only one hot leg present on each output, and it could be 240 volts at 50 Hz, as is common in Europe and China. It is also possible to configure the inverter  5000  with three hot legs on each output, in conformance with a three-phase electrical system, such as a U.S. 120/208 volt, 60 Hz 3-phase system. Although the description herein will henceforth concentrate on the 120-0-120 split-phase system most common in the USA, this is not a limitation of the invention, and those of skill in the art can easily adapt the teachings herein to implement a single-phase 240 v/50 Hz European system, any 3-phase system, or other configuration. 
     The above-incorporated &#39;777 patent discloses an inverter having two independent outputs with independent overload trip on each output, and teaches that one output may be current-controlled for connecting to the grid in a grid-tied mode, while the other output is a voltage-controlled output for powering appliance circuits directly, i.e., in the absence of grid power during a grid outage. 
     In  FIG.  28   , both inverter outputs appear identical up to the point where one is fed through a current sensor  5012 , hash filter  5013 , and grid and neutral isolation relays  5014  to the utility grid (a current-controlled output), while the other is connected to voltage sensor  5011  and fed though hash filter  5015  and output disconnect relays  5016  (a voltage-controlled output). The voltage-controlled output may also be fed through a current sensor (not shown) for the purposes of a current overload trip, while the current sensor  5012  on the current-controlled grid output serves as a feedback element to controller  5010  to control the output current to be a sine wave of desired RMS value. The controller  5010  may control the current to be output to the grid and in phase with it, such that power is exported, or may control the current to be from the grid and in phase with it, such that power is imported for the purposes of charging a battery supplying the DC input. Thus, power can be imported from the grid when tariffs are low and exported to the grid when tariffs are high. The inverter  5000  (or controller in communication therewith) may also have set in internal memory an energy “ask” value and may post the ask value via the internet to an energy exchange. The inverter may also receive energy “bids” electronically over the internet and if the bid equals or exceeds the ask, the inverter  5000  may be enabled to export a number of energy units up to the bid number. The exact exchange mechanism and the economic units used for posting bids and asks are not material to this disclosure. 
     For simplicity, many I/O connections to controller  5010  for reading current sensors, sensing voltages, and controlling relays have been omitted. However, those of skill in the art will but understand that controller  5010  shall also have such I/O connections for everything it is required to sense, measure, or control to implement embodiments of the invention. 
     The inverter  5000  of  FIG.  28    accepts a floating DC input voltage having a positive terminal at a nominal potential +Vdc and a negative terminal at a nominal potential of −Vdc, the DC source voltage thus being in total 2 Vdc. The DC source may comprise a battery that is charged by photovoltaic panels when the sun is shining. The controller may control charging to implement charge control regimes that avoid overcharging and have bulk absorption and equalization modes. When the sun is not shining, the energy source for charging the battery may be the grid, as mentioned above. 
     The range +Vdc to −Vdc must be large enough to allow the switching transistors Q 3  and Q 4 , using pulse width modulation, delta-sigma modulation, or any other similar high speed on-off switching, to generate a desired output waveform ranging from the positive peak of a 120 v RMS sinewave (+169 volts) to the negative peak (−169 volts). This would be a total DC supply at a minimum of 340 volts approximately, which however is often rounded up to 360−400 volts to allow some margin. The on/off switching frequency used must be orders of magnitude higher than the desired 50 Hz or 60 Hz output frequency to permit low pass filters  5013 ,  5015  to substantially eliminate the switching frequency components while passing the 50/60 Hz power waveform with negligible loss. In the above-incorporated patents, it is disclosed that such filters must comprise damping components, and those of skill in the art are referred to the incorporated patents for a fuller description of filter damping. 
     The inverter  5000  of  FIG.  28    operating in grid-tied mode with the grid isolation relays  5014  closed comprises switching of transistors Q 9  and Q 10 , which are controlled to switch between Vdc+ and Vdc− with a varying mark-space ratio to produce a sinewave current after filtering by the Leg  1  filter channel of filter  5013 . Likewise, Q 7  and Q 8  are controlled to produce an antiphase sinewave current through the Leg  2  filter channel of filter  5013 . Both filter channels comprise at least a high-current series inductor, a shunt capacitor to neutral, and damping components, as described herein above. The gate drive signals to Q 9  and Q 10  are replicated by controller  110  to Q 3  and Q 4 , which therefore produce the same voltage through the Leg  1  channel of filter  5015 , as exists on Leg  1  of the grid. Similarly, the gate drive signals to Q 7  and Q 8  are replicated to Q 5  and Q 6 . The above-incorporated &#39;777 patent discloses that a neutral may be created by using another pair of transistors Q 1  and Q 2  switching with a 50/50 mark-space ratio to produce zero voltage, in effect splitting the total 2 Vdc supply voltage evenly between a +Vdc line and a −Vdc line. In some circumstances, the mark-space ratio of the switching of transistors Q 1  and Q 2  may be used to adjust a DC bias on any AC output to zero. 
     It is also known in the prior art to add additional components to cause switching between 0 (neutral) and +Vdc to generate positive half cycles, and between 0 and −Vdc to generate negative half cycles, thereby halving the switching voltage excursion. This reduces switching losses and eases filtering. Such an arrangement using additional MOSFETs is shown in  FIG.  30    for one exemplary output. 
     In  FIG.  30   , back-to-back MOSFETs Q 11  and Q 12  are added to allow switching either between −Vdc and 0 volts or 0 volts and +Vdc. When a positive half cycle is desired, Q 11  may be turned ON and Q 4  turned OFF for the duration of the positive half cycle, while Q 3  and Q 12  effect switching between +Vdc and 0 with the desired mark-space ratio to produce a half sinewave output. To produce the negative half sine wave, Q 3  is turned OFF and Q 12  is turned ON for the duration of the negative half cycle while Q 11  and Q 4  effect switching between 0 and −Vdc to produce the negative half cycle. The switching frequency components are suppressed by a low pass filter comprised of L 1  and C 1 , with damping components C 2 , L 2 , and R 1  to suppress ringing. The purpose of L 2  is to form a second-order high pass filter with C 2  to reduce 60 Hz components reaching damping resistor R 1 , and thus reduce power loss in the damping. One such arrangement may be used for any or all outputs except for the zero-volt neutral output. The circuit of  FIG.  30    may be replicated and also applied to the transistor pairs Q 5 /Q 6 , Q 7 /Q 8 , and Q 9 /Q 10 , with appropriate modifications to the gate control outputs of controller  5010 . 
     It may be seen in  FIG.  28    that the grid isolation relays  5014  comprise a neutral disconnect relay. It has been disclosed above and in the incorporated patents that, in transformerless inverters lacking isolation between DC input and AC output, it can be desirable to isolate the circuitry from ground in the event of ground fault detection on the DC side, such as on a solar panel. Therefore, the inverter  5000  executes a start-up sequence with the grid and neutral isolation relays open, and may determine whether there is any unexpected signal between the neutral generated by the inverter and the grid neutral, as an indication of ground fault, before proceeding. Many other self-checks at initial switch-on, as also described above, may also be performed. 
     The inverter  5000  may alternatively or additionally employ any of the multilevel techniques described in U.S. Pat. No. 10,998,755 entitled “Transformerless DC to AC converter using selectively series-connected capacitors and PWM,” 10,784,710 entitled “Transformerless DC to AC converter,” and 10,250,162 entitled “DC bias prevention in transformerless inverters,” all of which are assigned to the assignee of the present disclosure, and which are hereby incorporated by reference herein in their entireties. 
       FIG.  29    shows an inverter  5000 , broadly of the type illustrated in  FIG.  28    and described above, connected to the grid and to source-selection switches RLY 1 , RLY 2 , etc., which are controlled by a controller to select either the grid or the inverter as the source of power for each appliance circuit. For ease of explanation, in this discussion the controller is assumed to be controller  5010  of the inverter  5000  (see  FIG.  28   ), although this is not a limitation of embodiments of the present invention. Those of skill in the art will readily recognize that control circuits discussed herein may be implemented in a variety of ways, e.g., as control logic, state machines, programmable logic together with appropriate firmware, stored-program microprocessors together with appropriate software, and the like. Such controllers may be centralized or distributed, with appropriate wired or wireless control, communications, and data exchange. 
     As disclosed above and in the above-incorporated &#39;703 patent, the source-selection switches are upstream of the appliance circuit breakers CB 1 , CB 2 , etc., so that whichever power source is selected, current flows to the appliance circuit through the same breaker, which may be an Overcurrent Protection Device (OCPD), an Arc Fault Circuit Interruption device (AFCI) or a Ground Fault Circuit Interruption device (GFCI) or any combination thereof (Combi breaker). This avoids the expense of the double breaker provisioning that would have been necessary had the source-selection switches been placed after the breakers. 
     Electromechanical OCPDs have an inherent delay in responding to an overload. Even at extremely high overloads, such as 5000 amps available short circuit current, the interruption time has been measured to be of the order of 4 mS. Not all relays have the ability to withstand such an overload even for 4 mS, due to limited contact pressure. Special newly-developed relays have overcome this problem. This feature is only required when the selected power source is the grid, because when the selected power source is the inverter, the inverter has fast electronic overload current limiting to a much lower available short-circuit current value. 
     Another caution that must be observed with small source-selection switches is that, when breaking a circuit (which may be inductive) an arc is drawn across the opening contact, which may still be conducting current from the first source when the contact makes with the second source. If the sources are of different voltage, undesirable source-to-source conduction can occur. One remedy is to use source-selection switches of a type that spend a sufficient time in an intermediate state when transitioning from one source to another, in which neither source is connected to the load, to permit current interruption to the first source to complete, and arcing to subside (i.e., a “break-before-make” switch). This can be done in various ways using two relays, for example. However, embodiments of the present invention solve this problem by having the inverter  5000  and the source-selection switches jointly controlled by the controller  5010  in one or more of the various manners described herein. 
     The controller  5010  shall preferably be powered whatever source of power is active. It was described above that primary and secondary power sources should contribute to powering the controller by a diode-OR function, which may be obtained by paralleling the outputs of multiple diode rectifiers that rectify the different AC power sources. For example, split-phase grid inputs L 1  and L 2  and inverter split-phase inputs L 1  and L 2  may be half-wave peak-rectified, and the four rectifier diode outputs paralleled to produce approximately 169 volts DC. The 169 VDC so produced may then be regulated using a switched-mode power supply to obtain +12 volts DC power to power relays and the controller. Traditionally, generator transfer switch logic has been powered by the 12 volt generator start battery, so that it is functional when the grid fails and before the generator starts. In the same way, if a generator is part of the installation, the 12 volts from the generator start battery can be diode-OR′ed with the 12 volts from the above switched-mode power supply, to provide yet another power source for maintaining the controller  5010  operative when all AC sources are out. If no generator is part of the installation, the inverter battery may, through suitable power conditioning, also produce 12 volts that can be diode-OR′ed with other 12 volt sources, to maintain a source of relay power and hold the controller operative under all circumstances. An inverter  5000  would normally already contain such a relay power source, so those of skill in the art will recognize that the combination suggested herein can result in some economy of parts. 
     In  FIG.  29   , inverter  5000  represents the inverter of  FIG.  28   , except that the grid isolation relays have been extracted and relabeled  5002 , as their operation is important for the following discussion. When inverter  5000  is operating with grid isolation relays  5002  closed and delivering a controlled current to the grid, the voltages on Leg 1  and Leg 2  of output C are identical to the grid voltage due to transistors Q 3 , Q 4 , Q 5 , and Q 6  of  FIG.  28    being switched with the same gate drive signals as transistors Q 7 , Q 8 , Q 9 , and Q 10 . Therefore, if source-selection switches RLY 1  or RLY 2  are controlled to select a different source, they are selecting between two identical voltages with no potential for source-to-source conduction due to make-before-break or arcing. Switching loads from the grid to output C of inverter  5000 , however, changes the source of the energy from grid to inverter, and ultimately the power is drawn from the DC source, such as a solar-charged battery, instead of the grid. 
     The controller  5010  is therefore capable of selecting some loads to be powered from the gird, while others are powered from the solar-charged battery, achieving self-consumption of own solar power and saving money at the full grid tariff. Therefore, the controller  5010 , with knowledge of the amount of solar energy being received, or of the charge state of the battery, and of the current grid tariff, can decide to increase “self-consumption” of low cost solar energy and reduce the consumption of higher cost grid energy. 
     After maximizing self-consumption, if there is excess energy left over from maintaining the battery fully charged, the controller can decide to increase the current fed back to the grid, to utilize the excess and receive a credit from the utility. If the time-of-day-based credit presently offered by the utility for fed-back energy is particularly attractive, it is even possible to contemplate discharging the battery to feed energy to the grid, as long as timely replenishment can be expected, such as by receiving a weather report from the Internet indicating that a sunny day is expected. Such decisions can be performed automatically by controller  5010  by executing mathematical calculations to optimize the benefit for the homeowner. 
     It is possible to operate the arrangement of  FIG.  29    using DC directly from solar panels, without storage by the battery. The controller  5010  first seeks to maximize self-consumption of instantaneously received solar energy before it feeds the excess to the grid. However, without storage, when clouds obscure the sun and reduce the DC power availability, the current fed to the grid must be reduced to maintain the load current. Since the inverter  5000  is bidirectional, the current can even be controlled to be negative, i.e., taken from the grid, in order to maintain load current by supplementing solar power with grid power. In the case of no battery storage, when current is drawn from the grid to support a load greater than incoming solar power, if an appliance is switched off, the instantaneous reduction in demand must be reacted to very promptly by the controller  5010  to reduce the current drawn from the grid, so that there is no attempt to feed it back to the photovoltaic panels. This is the same mechanism as normally used to control current fed to the grid in sympathy with the fluctuation of sunlight received, and is effected by detecting a rise in the DC input voltage and increasing the current fed to the grid to counteract the rise, thus stabilizing the input voltage. In the case that specific terminals are provided to connect to one or more strings of a solar array, the DC input from the string may be controlled such that the string is operating at its maximum power point, so-called Maximum Power Point Tracking or MPPT. 
     If the grid fails, instantaneously the controller  5010  will maintain the current fed to the grid to be proportional to grid voltage, which is normally a sine wave. This will result in a change to the switching transistor drive that will cause the voltage-controlled output also to instantaneously mimic the faulty grid voltage. However, upon detecting that the grid voltage is out-of-specification, the controller  5010  may cease to switch transistors Q 7 , Q 8 , Q 9 , and Q 10  and simultaneously transfer to controlling the voltage of the voltage-controlled output. It may also cease to switch transistors Q 3 , Q 4 , Q 5 , and Q 6  momentarily too, effectively open-circuiting the voltage-controlled inverter output, and simultaneously control the source-selection switches to transfer as many loads from the grid to the voltage-controlled output as the inverter can support, based on actual measured load current prior to the grid outage, user priorities, historical data, and the like. After allowing for source-selection relay operating time (typically about 10 mS), the voltage-controlled output can be resumed. 
     If the out-of-specification grid voltage persists for longer than a 60 Hz cycle or so, then the controller  5010  may open the grid isolation relays  5002 . At that point, with the system of  FIG.  29   , loads left on the grid will be unpowered. 
     During a prolonged outage, if it becomes desirable to transfer loads to or from the inverter  5000 , it may be deemed safe to do so as long as the grid voltage, which is still being monitored by the inverter  5000  by an input bypassing the grid-isolation relays, is zero. To make doubly sure of a safe transfer, the inverter voltage-controlled output can be inhibited to the open-circuit condition momentarily once more for the 10 mS required for the source-selection relays to complete the transition. 
       FIG.  31    shows an alternative connection for the grid supply to the source-selection switches. In  FIG.  31   , the grid supply connection to the source-selection switches RLY 1  and RLY 2  comes from the inverter side of the grid-isolation relay  5002 . When the grid-isolation relay  5002  is closed, operation is as previously described for  FIG.  29   . However, if the grid fails or goes out of specification in the case of  FIG.  31   , controller  5010  may not need to transfer any loads from the grid to the voltage-controlled inverter output. Instead, the current-controlled output is inhibited until the grid-isolation relay  5002  opens, and there is no need even momentarily to interrupt the voltage-controlled output, as no selection switches will be changed. Once the grid-isolation relay  5002  is open, however, the current-controlled output may restart in voltage-controlled mode to power appliances that were previously connected to the grid. Both inverter outputs can be alike in power output capability, so that the total power available from the inverter  5000  can be double that of  FIG.  29   . Even so, if the total load on the grid prior to the outage exceeded the power capability of the now voltage-controlled grid output, controller  5010  may transfer some loads to fully utilize the power from output C before re-enabling the grid output. If the remaining load on the grid output is still too great, then the user may be alerted by an automatic message to his phone or laptop, or via a front panel display on the unit, suggesting which breaker or breaker circuit to turn off to permit the remainder to be powered. Optionally, additional controlled switches can be included to provide an OFF mode for appliance circuits that can be selected by the controller  5010  without user action. Alternatively, smart appliances or smart outlets can be controlled by the controller to OFF using wireless or power line communications, as disclosed in U.S. Pat. Nos. 9,793,953 and 9,785,213, assigned to the assignee of the present disclosure and incorporated by reference herein in their entireties. 
     Embodiments of the present invention also include the possibility to implement a hybrid of  FIGS.  29  and  31   , wherein some selection switches are connected to the grid side of the grid-isolation switch  5002 , and others are connected to the inverter side of the grid-isolation switch  5002 . It would thereby be possible to leave appliances connected to the grid side of the grid-isolation switch  5002  unpowered during a grid outage. For example, a clothes washer, dish washer, tumble dryer, water heater, and HVAC could be connected to selection switches with their grid input from the grid side of the grid-isolation switch  5002 , so that load shedding during a prolonged outage could be effected by selecting the grid as the power source, always to be overridden by the user manually selecting an inverter output for an appliance. An example of an appliance that would have its grid power taken from the inverter side of the grid-isolation switch  5002  could be a refrigerator or freezer, so that they would continue to be powered during a grid outage even if their selection switches were manually fixed in one position. Such appliances could also be designated high priority loads, and whichever configuration of selection switch they used would automatically prioritize them to receive inverter power during a grid outage, overriding manual control unless their priority designation was altered by the user. 
     In view of the above operation, it is logical to assign the highest priority circuits to be kept alive during a grid outage to the normal voltage-controlled inverter output, as during a prolonged outage and the absence of sun or generator support it may be necessary to begin to shed load as the battery discharges. In this case, the first loads could be shed by switching the second voltage-controlled grid output OFF and gradually transferring loads to the OFF output from the normal voltage-controlled output in order of lowest priority. 
     When the grid outage is over and the grid is once more deemed to be in specification and stable, as determined by the controller  5010  monitoring the grid on input A, the controller  5010  may prepare to re-close the grid-isolation relay  5002 . As a prelude to that, the grid output, if operating in voltage-controlled mode, is switched off by inhibiting the switching of transistors Q 7 , Q 8 , Q 9 , and Q 10  and re-enabling switching in the current-controlled mode after the grid-isolation relay  5002  has closed. The voltage-controlled output, which was operating in an autonomous, self-controlled mode in the absence of the grid as a pilot, is then slaved to the switching of transistors Q 7 , Q 8 , Q 9 , and Q 10  once the current-controlled mode is confirmed to be operating normally and the grid voltage and frequency remain in specification. Thus, loads powered by the normal voltage-controlled output do not suffer any power interruption upon resumption of the grid. 
     The arrangement of  FIG.  31    also allows any double-pole (240 volt) appliance circuit to be switched from grid to inverter  5000  using two, single-pole switches. When attempting this in prior art systems, or with the system of  FIG.  29   , account must be taken of the possible consequences of one of the single-pole source-selection switches failing to switch, for example if it is a relay with welded contacts. If a two-pole (240 v) appliance circuit is left with one pole connected to grid and the other to inverter  5000 , and the grid fails, the inverter voltage-controlled output would feed current through one pole of the appliance circuit to the other, violating the anti-islanding regulations. If the grid fails open-circuit, such as if the main breaker trips or is pulled, the two-pole appliance could also feed the other appliances on the grid pole of the two-pole appliance with a deficient voltage. In the system of  FIG.  31   , however, the second pole of a two-pole (240 volt) appliance left erroneously connected to the grid would be on the inverter side of the grid-isolation relay  5002 , which would rapidly disconnect it from grid upon a grid outage, and furthermore would replace the grid voltage by converting the current-controlled inverter output to a voltage-controlled output. Thus, an appliance which was intended to be powered with a phase 1 developed by switching transistors Q 3  and Q 4  of  FIG.  28    and with a phase 2 developed by Q 5  and Q 6  of  FIG.  28   , if erroneously powered by phase 2 developed by transistors Q 7  and Q 8 , would not notice any difference, since Q 7  and Q 8  are identical transistors to Q 3  and Q 4 , and are switched with identical drive waveforms. 
     It has thus been disclosed how advantageous combinations of a dual-mode inverter  5000  and source-selection switches may be jointly controlled to select appliance circuits to be powered either by grid power or solar-derived inverter power, while avoiding circumstances under which undesired current flow between grid and inverter could occur. Embodiments of the invention may be implemented by a combination of an inverter  5000  and a set of source-selection switches in a single housing, or as separate units with an appropriate communications link there-between for joint control in the manner described. Such a communications link should preferably be dedicated solely to the control functions to implement embodiments of the invention, and not shared with anything else that could interfere with operation or timing of those critical control functions. 
     In any particular state of the selection switches, the loads or appliance circuits are effectively divided in  FIGS.  29  and  31    into two groups: a first group of appliance circuits that are connected by their associated selection switches to a first inverter output, and second group of appliance circuits that are connected by their associated selection switches to receive grid power or power from a second inverter output. The principle can be extended to the case where the inverter  5000  has multiple, first outputs and the selection switches connected selected loads to either a determined one of the multiple first inverter outputs, or to the grid, or a second inverter output. In the limit, the inverter  5000  can in principle have as many first inverter outputs as there are selection switches, and each selection switch connects its appliance to one of the multiple first inverter outputs, or to the grid, or second inverter output, as shown in  FIG.  5   . 
       FIG.  32    shows the inverter  5000  now has a first output number  1  connected to the source-selection switch of appliance circuit  1 , and a first output number  2  connected to the source-selection switch of appliance circuit  2 . There can be as many outputs and selection switches as desired, but only two are shown for clarity. Since the only difference between an inverter output for phase 1 (Leg 1 ) and phase 2 (Leg 2 ) of a split phase system is how the output transistors are driven, which is trivial for the controller to set, the multiple first outputs can in principle be of uncommitted phase and a set of three may even be programmed to output 3-phase. However, if the grid is a split-phase grid, at least one of the set of three-phase could be synchronized to either leg1 or leg2 of the split-phase grid outputs by using the same switching transistor waveforms. The others could employ the same switching waveforms, but delayed by ⅓ rd and ⅔ rds of a cycle in a suitable memory or shift register. Preferably the selection switch should connect to a grid phase of the same phase as the inverter output, but if this is not possible due to the grid being split-phase and a set of outputs being 3-phase, then the precautions during switching between un-synchronized sources should be taken, namely placing the inverter output switching transistors in the non-conductive state during the switching time of a selection switch when changing sources. 
     Such an embodiment of the invention may be used to provide 3-phase outputs when the grid service is only single-phase or split-phase. The cost for the flexibility just described is that each inverter output needs a filter such as half of filter  5015  of  FIG.  28    comprising a series inductor, shunt capacitor to neutral, and damping. Although the inductor would only need to pass a lower current than for an output feeding all appliance circuits, the inductor size unfortunately does not reduce much, as it must be a proportionally higher inductance for lower current. 
       FIG.  33    depicts the steps in a method  5050  of independently, selectively supplying power to each of a plurality of appliance circuits from one of an electric utility grid and a DC-to-AC inverter  5000 . The flow diagram of  FIG.  33    depicts two parallel paths, indicating that the operations described in each path occur simultaneously. Furthermore, although depicted as sequential steps, those of skill in the art will understand that both paths of the method are continuously ongoing, as indicated by the arrows looping back from end to beginning. 
     The electric utility grid is periodically or continuously monitored to detect faults or a shutdown (block  5052 ). If a grid fault is detected (block  5054 ), the grid-isolation switch  5002  is controlled to disconnect an output of the DC-to-AC inverter  5000  from the grid (block  5056 ). 
     Meanwhile (that is, while monitoring of the grid is ongoing), each source-selection switch is controlled to route either grid power or inverter power to the associated appliance circuit ( 5058 ). The flow diagram blocks within block  5058  indicate how this occurs. Only if the grid and inverter  5000  output the same, time-synchronized voltage waveform, or if one of the grid and inverter  5000  output zero volts, then the state of a source-selection switch may be changed to route the other of grid power or inverter power to its associated appliance circuit. However, if the voltage waveforms output by the grid and inverter  5000  are not the same and time-synchronized, and neither of them outputs zero volts, the source-selection switch is prevented from changing state, and the associate appliance circuit remains connected to the prior power source. In this manner, it is ensured that loads on the appliance circuits do not experience a glitch in supply voltage upon switching between power sources, and cross-source conduction is prevented. 
     It has been shown above how a variety of useful solar energy systems may be constructed using different combinations of a small number of novel equipment designs. While other industries are competing to reduce the cost of solar panels, soon to be under $1/watt, the inventive inverters and system integration techniques described herein permit commensurate reductions of other main components and balance-of-system components in order to drive down the total installation cost of a solar system to levels where the economics of solar energy become compelling. 
     Embodiments of the present invention present numerous advantages over the prior art. They provide substantially no break in power to high priority circuits, while maximizing the economic benefits of using solar energy rather than grid energy. 
     Parent U.S. patent application Ser. No. 15/676,826 addresses the problem of synchronizing AC power from two different sources. A microprocessor is provided with a crystal oscillator which is a large integer multiple of common power line frequencies, such as 50 and 60 Hz. 60 Hz is used as the exemplary frequency in further description below. The crystal oscillator frequency is divided down internally using a timer inside the microprocessor to provide an approximate 60 Hz tick, and at least one integer multiple thereof, such as 480 Hz. The internal 60 Hz is not synchronized to any power source and so drifts slowly in phase relative to the approximately 60 Hz frequencies of the multiple power sources. The power supply for the microprocessor is obtained by half-wave rectifying and diode-ORing every phase of every electrical source so that it continues to function even if all phase bar one have failed. 
     The microprocessor uses the internally generated clocks of 60 Hz and the multiple of 60 Hz to sample, or cause to sample, the currents and voltages desired to be measured and to analog-to-digital convert them to numerical sample values. 
     A set of numerical values for each voltage and current, approximately equally spaced in time over a cycle, are Fourier analyzed to determine the fundamental component of each for each complete cycle. The fundamental component so calculated is a complex number having a real part representative of the amplitude of a cosine wave component and an imaginary part representative of a sine wave component. The ratio of the sine to the cosine amplitudes is the tangent of the phase difference between the power source and the microprocessor&#39;s internally generated 60 Hz reference tick. The phase drifts at a rate depending on the frequency difference between the microprocessor&#39;s internal clock and the electrical power source being measured, and thus the frequency difference can be determined for each source relative to the microprocessor&#39;s reference, and thus also relative to each other, by determining for example the average phase change per cycle over several cycles. 
     To obtain an average value of a measured fundamental component of current or voltage, the per-cycle measured values are corrected for phase drift using the frequency so determined and then coherently averaged. 
     The power transferred to a load via a branch circuit fed with a substantially sinusoidal voltage is calculated as the average value of the per cycle complex current samples times the conjugate of the corresponding per cycle complex voltage samples, the phase drift on the conjugate of voltage being of equal and opposite sign to the phase drift of the current and thus canceling. The average value so obtained is used as a measure of real and reactive power and so also the power factor of the load is determined. A calibration procedure is implemented in production in which a known resistive load is used to determine and calibrate out any fixed phase differences between the measurement of current and voltage caused by small timing delays or phase changes in circuits and software, the calibration values being stored in non-volatile memory for each equipment. 
     When a load or branch circuit is switched to be powered from a second source instead of a first source, while the current measurement continues to supply samples of the load current, the selection of voltage samples with which it is combined must be switched to be taken from the second source instead of the first source. Moreover, the phase drift correction used to correct complex current values before averaging current may be determined by the phase drift of the voltage of the selected power source. 
     One embodiment relates to a system for monitoring the electrical parameters of a number of electrical loads or branch circuits, at least one of which may be powered at different times by a selected one of at least two AC power sources of nominally the same frequency. The system includes a clock generator operative to generate a local reference clock of nominally the same frequency as said at least two power sources or an integral multiple thereof; current sensors operative to sense the instantaneous current flowing in said loads or branch circuits and produce corresponding voltage waveforms; voltage scaling circuits operative to scale the voltage input from each of said at least two voltage sources to produce corresponding scaled voltages; analog to digital conversion circuits operative to convert said current corresponding waveforms and said scaled voltages to numerical values representing current and voltage measurement values at multiple samples per cycle, the AtoD conversion being triggered and synchronized by said clock generator; microprocessor circuits operative to control the selection of one of said at least two power circuits to power said at least one or load or branch circuit and to process said numerical values to obtain a complex number representing the phase and amplitude of a current or voltage over one or more power frequency cycles, said microprocessor circuits combining the complex number representative of a current value in a load or branch circuit with the complex value representative of the voltage value of the source selected to power said load or branch circuit in order to obtain the average or cumulative value of an electrical parameter of the load or branch circuit, and a power supply operative to convert power input from any or all of said at least two power sources or any phase thereof to a voltage suitable for powering said clock generator, current sensors, voltage scaling circuits, Analog to Digital conversion and microprocessor circuits. 
     Another embodiment relates to a method of determining the amount of energy consumed from the electricity grid by each of a number of branch circuits or loads and separately determining for the same branch circuits or loads the energy consumed from a solar energy source. A solar or utility indicator of the instantaneous source selected for each of said loads or branch circuits is maintained. The complex voltage of each of the utility and solar sources is measured using a locally generated phase or timing reference. The complex current flowing in each of said loads or branch circuits is measured using said same locally generated phase or timing reference. For each of said loads or branch circuits, said measured complex current is multiplied by the conjugate of said measured complex voltage of the source indicated by said indicator for each load or branch circuit to obtain an instantaneous power value. Said instantaneous power values for successive time instants are accumulated in a bin designated for solar if said indicator indicates the solar power source or alternatively in a bin designated for utility if said indicator indicates the utility power source, thereby obtaining for each load branch circuit a separate value for the energy consumed from solar and utility sources respectively. 
     Yet another embodiment relates to a method of determining an accurate average value of a complex AC current. A first complex number representative of AC current over one or more power frequency cycles is determined. A second complex number representative of the AC source voltage causing said current over one of more power frequency cycles is determined. A first average value is determined as the average of the product of said first complex number with the conjugate of said second complex number. A second average value is determined as the average value of said second complex number with the conjugate of itself. Said first average value is divided by the square root of said second average value to obtain said accurate average value of said complex AC current. 
     Still another embodiment relates to a method of determining an accurate average value of complex AC currents that can be drawn from any one of a number of AC voltage sources at different times. A first complex number representative of AC current over one or more power frequency cycles is determined. second complex numbers representative of each of said AC source voltages over one of more power frequency cycles are determined. The first complex number is multiplied by the conjugate of the second complex number associated with the source from which the current is momentarily drawn and accumulating the result in a first bin associated with that source. the second complex number associated with the source from which the current is momentarily drawn is multiplied by the conjugate of itself and the result is accumulated in a second bin associated with that source. The values in each of said first bins associated with a source are divided by the square root of the value in the corresponding second bin associated with the same source to obtain an accurate average value for said complex AC current drawn from each source. 
     As discussed above,  FIG.  22    shows an automatic transfer switch panel for selecting, independently for each of a number of breaker-protected branch circuits, whether a branch circuit is powered by a first source, such as the electric utility grid, or a second source, such a DC-to-AC converter driven by a solar-charged storage battery. Such a panel provides an exemplary platform for describing the current invention; however, the invention is not limited to a system having only two sources, nor is it limited to the transfer switches for transferring between the multiple sources being collected together in a single panel. 
     In  FIG.  22   , current sensors ( 3008 ) sense the current delivered through each breaker to its load or branch circuit. The current is selected to have come from one or other of the quadruple bussbar lines ( 3001 , 3002 ) by an associated one of SPDT relays ( 3003 ). The phase of the current therefore depends on the phase of the voltage on the selected bussbar. 
     In the current invention, the AC voltage on each bussbar is measured. In an apparatus according to  FIG.  22   , the voltage on all four bussbars is preferably measured even when the voltages on pairs of the bussbars comes from a split-phase 120-0-120 volt source as used in the USA, as that can provide a useful indication of the failure of one phase. When one of the two phases of a split phase source fails, it is then desirable to avoid powering 240 volt loads from that source as they would then only receive 120 volts at best. Thus failure of one phase of one source is an indication that may used to effect automatic transfer of 240 volt loads to another source having both phases intact. A three-phase version having six bussbars can alternatively be envisaged, in which case all six voltages of the six bussbars would preferably be measured, and also used to power the electronics of the invention. 
       FIG.  36    shows a suitable voltage measurement circuit, of which there is one per phase and per source. The problem solved by this circuit is as follows: 
     The voltage to be measured on the Live wire of the phase, typically 120 volts rms, is to be potted down and level-shifted to the range typically accepted by low cost AtoD converter chips, for example to the range 0 to 5 volts. A suitable result of scaling down and level shifting would be to obtain an AC signal of 1 volt rms centered on 2.5 volts, which therefore swings between 1.1 and 3.9 volts with a nominal 120 v rms input, leaving some headroom to correctly measure an overvoltage condition. Moreover, the AtoD, microprocessor and other low power electronics are preferably operating relative to ground, which is not exactly the same as neutral, even though neutral is grounded at the service entrance. Fault conditions can cause neutral to become live and even under normal conditions the voltage drop along the neutral line can be as much as 2.5% of the voltage, that is 3 volts rms. Thus if the scaling potentiometer chain comprises a pair of resistors in the ratio 119:1 between live and neutral, the result would be 1 volt rms plus the uncertain neutral voltage. On the other hand, if the scaling potentiometer chain comprised a pair of resistors in the ratio 119:1 between live and ground, that would inject a current into the ground or case of the apparatus, for which there are strict and very small safety limits. To keep the current down to the 1 uA level, potentiometer resistance values over 100 Mohms would be needed, which are vulnerable to change with exposure to moisture. To avoid the above pitfalls, the circuit of  FIG.  36    performs the scaling in two steps. A first approximately 12:1 pot-down relative to neutral is performed by resistors R 46  and R 47 . This results in approximately 10 volts RMS at the junction of R 46 , R 47 , and R 36  relative to neutral. The voltage relative to ground is 10 volts RMS plus the neutral voltage. The 10:1 ratio of R 36  to feedback resistor R 38  then reduces this voltage by a further 10:1, obtaining 1 v rms at the Op-Amp output. To remove the uncertain neutral voltage and obtain an output referred to ground, the neutral voltage is scaled by a combination of R 48 , R 49 , R 37  and (R 39 //R 40 ) and applied to the opposite polarity input of the LMP7701 Op-amp, exactly canceling the contribution of the uncertain neutral voltage to the Op-Amp output. It may be seen that the current flowing from Live to ground has been kept to around the 1 uA level, and even this is largely canceled by the circuit attached to the opposite phase. Thus, by performing a scaling of the power line voltage to be measured in two steps, a first scaling relative neutral and a second scaling relative to ground, a voltage measurable by a grounded microprocessor circuit is obtained without injecting significant leakage current into the chassis of the apparatus. 
     To measure the current, current sensors ( 3008 ) may be toroidal magnetic cores through which the current-carrying conductor passes to form a 1-turn primary. A multi-turn secondary then produces an output voltage which is proportional to the derivative of the current. The derivative of the current is 90 degrees advanced compared with the current, and liable to be noisy due to magnification of noise at high frequencies relative to the power line frequency, and therefore requires low-pass filtering and phase correction by a process approximately equivalent to an integrator to cancel the differentiation. This filtering and phase adjustment may be carried out by hardware, digital signal processing software, or a combination. 
     Alternatively the current sensor may be a Hall Effect sensor such as the MLX92105 chip made by Melexis Microelectronic Integrated Systems. When a Hall Effect sensor is used, the current conductor is passed close to the sensor such that the magnetic field vector from the current carrying conductor penetrates the sensor in the direction of its greatest magnetic sensitivity. A Hall Effect sensor does not differentiate the current, but the small signal therefrom requires substantial amplification, adding noise, and may therefore still need filtering to reduce noise. A Hall Effect sensor is thus easier to use and simplifies manufacture by avoiding the need to thread a wire through a core, but either a Hall sensor or a coil pickup may be used. 
       FIG.  34    illustrates a segment from a suitable circuit that uses the above mentioned MLX92105 Hall Effect sensor. Three channels only are shown for simplicity. The important components that may be seen are the Melexis sensors at the bottom, an ATMEL AT-TINY microprocessor at the top having eight analog-to-digital conversion inputs, one of which is connected to the amplified output of each sensor, and the crystal X1 attached to the processor for providing a reference clock. A suitable reference clock frequency is 11.0592 MHz, which is 256×90×8×60 Hz. An internal power-of-2 prescaler may be set to divide the crystal frequency by 256 and then a programmable counter is set to count to 90 and then reset repeatedly, thus providing an 8×60 or 480 Hz internal timer interrupt, which occurs at intervals of 2.0833 milliseconds. Upon each interrupt, the AT-TINY&#39;s internal AtoD converter is triggered to convert the signal from each of eight current sensors in turn in rapid succession, which takes less than 1.5 milliseconds. The AC current signal from the Hall Effect sensors is biased to be centered on +2.5 volts DC by a following amplifier that also attenuates noise below half and above twice the line frequency, and the gain of the amplifier is chosen to keep the output voltage within the 0 to 5 volt range of the AT-TINY&#39;s AtoD converter. The resulting converted, digitized samples are of 10-bit accuracy, and include the DC bias of 2.5 volts added to the AC current signal. 
     During most of the 1.5 mS time the AtoD converters are operating, the processor is actually free to do calculation, as it is also during the rest of the 2.08333 mS. The AtoD converter, once triggered, takes between 100 uS and 200 uS to perform a conversion, and then interrupts the processor when complete. The processor may perform of the order of 1000 instructions during this conversion time. When eight samples from each current sensor have been collected over one 60 Hz period of 8×2.08333=16.66 mS, these available CPU cycles for calculation while the next eight samples on each of the eight channels are being collected are sufficient to perform a simple Fourier analysis of the previously collected 8 samples on each channel to determine a complex number per channel per cycle indicative of amplitude and phase relative to the microprocessor&#39;s reference clock of the fundamental frequency components of each current. With the assumption that the voltage is sinusoidal, only the fundamental frequency component of the current at 60 Hz is needed to compute the power. 
     Fourier analysis of 8 samples per cycle to determine the fundamental component uses the equations: 
       Cosine component=( S 1− S 5)+( S 2− S 6− S 4+ S 8)/√2  (7)
 
       Sine component=( S 3− S 7)+( S 2− S 6+ S 4− S 8)/√2  (8)
 
     Equations (7) and (8) are seen to be based on four sample differences taken four apart, namely (S1-S5), (S2-S6), (S3-S7) and (S4-S8). The equations may thus be written in terms of the differences D 1 , D 2 , D 3 , D 4  as follows: 
       Cosine component= D 1+( D 2− D 4)/√2  (9)
 
       Sine component= D 3+( D 2+ D 4)/√2  (10)
 
     An efficient software code thus computes the four differences on the fly as samples are received by subtracting them from the samples received four ago and storing the differences in the same locations, thus halving the size of the RAM buffer required. Computing the differences also eliminates the DC bias. 
       FIG.  35    shows the software structure for forming and storing the above differences on the fly. The number of samples collected per cycle is 8 per channel, or 64 for 8 channels. Each sample is 10 bits long, requiring two bytes of storage. Therefore a one-cycle buffer size would normally be 128 bytes. However, by computing and storing only the four differences required, the buffer size reduces to 64 bytes. Two such buffers are required, as one is being used for calculation while the other is being filled. One buffer is shown occupying the address range 0 to 3 F (hex) or 0000000 to 00111111 binary, and the second buffer occupies range 80 to BF (hex) or 1000000 to 10111111 binary. 
     The software uses register Y for addressing the buffers. Pointer Y is initialized to either 00000000 or 10000000 upon receiving a 60 Hz tick interrupt, depending on whether the first or second buffer is to be used. Also, the contents of the selected buffer are zeroed at the start. 
     At step  100 , the least significant 8 bits of an AtoD conversion are read into R 16 . 
     At step  101 , the current contents of buffer location Y are read into R 17 . First time round, this will be zero, but second time round it will the complement of the AtoD value from the first time round. 
     At step  102 , the previous buffer value in R 17  is subtracted from the LSB of the AtoD result in R 16 . R 17  was zero the first time round so the result is simply the LSB R 16  unchanged. This is rewritten to the buffer at step  103  and the buffer pointer Y is incremented. 
     At step  104  the MSB of the AtoD result is loaded into R 16 . At step  105 , the next byte from the buffer is loaded into R 17 . This will be zero first time round also, but is the previous sample&#39;s MSB the second time round. At step  106 , the previous buffer value in R 17  is subtracted from the AtoD MSB in R 16  with a Borrow from the LSB subtraction at step  102 , and the result put back into the buffer at step  107 . This completes dealing with a first result of AtoD conversion. The buffer pointer has moved on two bytes and now points to the previous result of the next channel. At step  108 , it is ensured that bit  6  of the pointer Y remains at zero by ANDing BF (hex)=10111111 with Y&#39;s LSB, which is R 28 , so that it will not increment outside of the buffer area to which it was initialized. This process continues for the first 4 samples received on all 8 channels, the 32, 2-byte samples then filling the 64-byte buffer. The buffer pointer Y then wraps around so that the next 32 samples are subtracted from the first 32 samples, leaving four, 2-byte differences for all eight channels in the 64-byte buffer. The differences are actually the negative of the difference used in equations (9) and (10) above, but this may be trivially accounted for by later operations. 
     The four differences per channel are then processed as described above to determine a cosine and sine component for each channel while the second buffer is being filled during the next cycle, having initializing Y to 10000000 (hex 80). Actually, Y is alternated between the two buffers by, after each round, adding hex 80 to its LSB which toggles its most significant bit, thereby switching the buffer starting address alternately between 00000000 and 10000000. 
     Calculating sample differences cancels out the above-mentioned 2.5 volt DC bias, which is the same on all samples. Moreover, 1/√2 is accurately approximated by 181/256. Thus division by 1/√2 is accomplished by multiplying by 181 with a byte shift to the right, which equates to division by a denominator of 256. Since the multiplication is always by the same number 181/256, the result can be precomputed for every possible 8-bit multiplicand and stored in the processor&#39;s EPROM as a 256-element table of 2-byte products, thus reducing multiplication to table-lookup. Negative numbers are changed to positive numbers for multiplication and then the sign of the result changed to negative. 
     Two table look-ups are needed for multiplying a 16-bit value by 181 to give a 3-byte result, of which only the most significant two bytes are needed. The first table look-up uses the LSB of the 16 bits to get a 2-byte result, and the second table look-up uses the MSB. The first result is then added to the second result with a one byte relative displacement to get the three-byte result, only the most significant two bytes of which are used to complete the calculation of equations (9) and (10) to get 16-bit results for cosine and sine components, which are then passed to a main processor. 
     The main processor is for example an ATMEGA processor, which uses the same 11.0592 MHz crystal frequency to generate and supply a 60 Hz tick to the AT-TINY processor to trigger a new measurement sequence and to trigger output of the previous calculations. The ATMEGA processor measures the voltage from the circuits of  FIG.  36    in the same way as described for the current to obtain a cosine and a sine component. The ATMEGA has a hardware multiplier that can be used to multiply by 181, which is a little faster than table lookup. Since the AT-TINY is synchronized to the same 60 Hz tick from the main processor, the phase reference is the same for voltage and current give or take some small, constant timing corrections that may be needed to be taken out by a one-time calibration. Communication between the AT-TINY and the main processor, which is an AT-MEGA1284 in a prototype system, uses the Serial Peripheral Interface, or “SPI port” for short. 
     The voltage scaling circuit of  FIG.  36    effectively measures line voltage alone. Line voltage alone, when combined with current, is more accurately representative of the power consumed from the source. The line-to-neutral voltage combined with current would be a correct estimate of the power taken by the load but an underestimate of the power consumed from the source, as it ignores the loss in the neutral wire, which has to be paid for. Also, without canceling the contribution of the neutral voltage, which is in-phase with the line voltage, the circuit of  FIG.  36    would have produced an overestimate of the power consumed from the source. Thus by accomplishing down-scaling of the line voltage in two steps, the first step being a downscaling relative to neutral and the second step being relative to ground, an accurate scaling of the line voltage is achieved without injecting significant current into the equipment ground. 
     The scaled-down voltages from all phases of all power sources are sampled, AtoD converted and translated to a cosine and a sine value per cycle, exactly as explained above for current samples. Since power source voltages are expected to be of a stable nature, unlike load current which varies widely and may be zero, determining the phase drift and therefore frequency error of a source relative to the microprocessor&#39;s crystal controlled clock is best accomplished by processing the voltage samples. The accuracy of the microprocessor crystal is expected to be better than 20 parts per million, which means it would take 50,000 cycles, or about 800 seconds at 60 Hz, to drift one cycle. However, the frequency accuracy of the sources may not be so accurate. Utility grids are required to maintain frequency within +/−0.5 Hz but typical deviations are one tenth of that, namely +/−0.05 Hz. With a worst case error of +/−0.5 Hz, the complex voltage vector measured as described above would rotate through 360 degrees in two seconds or 120 cycles, and so cannot be averaged over long periods without correcting for this rotation rate. The phase drift is thus a worst case of +/−3 degrees per cycle. This is however low enough that the above Fourier analysis period could be extended to two or more cycles in length by accumulating the differences D 1 , D 2 , D 3 , D 4  over more than one cycle if desired before calculating equations (9) and (10). 
     There are several methods to compensate for phase rotation of the measured currents and voltages. One way is to determine the rate of rotation. 
     If the complex voltage measurement yields a value (VR(i), VI(i)) for cycle number (i), where VR is the cosine component and VI is the sine component, then the phase change from cycle i to cycle i+1 is given by 
         d φ=ATAN2[ VR ( i +1) Vi ( i )− VI ( i +1) VR ( i ), VR ( i +1) VR ( i )+ VI ( i +1) VI ( i )]  (11)
 
     where ATAN2 is the dual-argument Arctangent function for the angle of the vector (x,y). The frequency error is then given by dw=dφ/dt=60 dφ radians per second when dt= 1/60 Hz or 30 dφ/Π Hz. 
     The frequency discriminator equation (11) can be computed using cycles more than one apart providing the phase change over the interval will never approach or exceed 180 degrees. Results of equation (11) can be averaged over as many cycles as desired to give an accurate frequency error estimate. The average frequency error estimate can then be used to remove the phase rotation per cycle from successive cycles of current or voltage measurements. Removal of phase drift during averaging can be accomplished through carrying the previous complex average result forward and complex-multiplying it by Exp(j dφ) where dφ is the phase drift per cycle. This aligns it in phase with the next cycle&#39;s complex value enabling it to be coherently combined to form an updated average. 
     While the invention may comprise such a means as just discussed to assess the frequency accuracy of sources to see if they are out of bounds, there is a simpler means to account for frequency error while averaging voltages and currents. 
     One equation for computing instantaneous power is 
         P=I·V*   (12)
 
     where I and V are the one-cycle complex current and voltage measurements respectively and * means complex conjugate. The complex conjugate of V rotates in the opposite direction with frequency error to the direction in which I rotates, thus keeping the vector value of P static, and thus capable of being averaged or accumulated without drift correction to obtain an accurate mean power value or cumulative energy use value. Moreover, the derotated value I can be obtained by dividing P by the magnitude of V. The magnitude of V is given by 
       | V|=√V·V*   (13).
 
     Thus an equation for derotated instantaneous current that is capable of being averaged is 
         I=I·V*/√V·V*   (14).
 
     Provided that the voltage is not fluctuating rapidly or by a large amount, equation (14) does not need to be computed every cycle. Instead, the value of |V| may be averaged or accumulated over 60 samples over one second for example, and likewise the value of P from equation (12) may be averaged or accumulated over 60 cycles, and the ratio of the 1-second averages or accumulations only need be computed by equation (14) once per second. 
     Since the invention is concerned with measuring electrical parameters of systems connected to two or more sources of power that may selected at any time to power any load, the computation of average or cumulative parameters should be truncated for any load when its power source selection is changed, and a new average computation initialized or old cumulative calculation for the selected source resumed using the voltage of the newly selected source to combine with the load current. Thus the software computations of average load current and power or cumulative energy consumption and even of instantaneous current and power are deliberately synchronized with the switching of power source from one source to another. Accurate synchronization is facilitated when it is the same processor that affects source switching as performs the power calculations. In the case of  FIG.  22   , each breaker circuit may be selected to be powered from either the utility grid or from a solar inverter by controlling selection relays ( 3003 ). An internal software variable remembers the last programmed state of relays ( 3003 ) and therefore indicates for each load whether it is powered from the utility grid or solar. This variable is made accessible to the software routines that compute equations (6) or (8) so that the appropriate voltage is selected to combine with each load current measurement and so that the result may be averaged or accumulated in the correct bin, namely a “utility grid” average or cumulative bin or a “solar” average or cumulative bin. 
     In order to properly synchronize the different functions carried out by software, a specific software structure is used in which different hardware such as relays and AtoD converters are controlled by device-specific Device Control Programs that run only when needed to perform the following two exemplary types of task: 
     (1) Alter the hardware status
 
(2) Respond to a query about hardware status or hardware generated data.
 
     The structure of a Device Control Program, or DCP for short, is typically as shown in  FIG.  37   . Requests to perform a task are communicated by creating a Device Control Block (DCB) which is entered into a queue for the specified device by a common queuing routine. Every DCB for every device has a 4-byte area comprising a 16-bit placeholder for a Link address for linking to another DCB in a chain or linked list of DCBs; a one byte placeholder for a “callerID” that indicates the process number requesting the task, and a one byte “Reply” that is used for two purposes: On input, it indicates whether the calling process desires to be suspended until completion of the requested task or not. On output at completion, it indicates to the calling process that the task has been completed. The rest of the DCB contains device-specific arguments such as relay driver control codes or, in the case of the AtoD converter DCP, may indicate a buffer address to receive the results. 
     The calling program prepares the DCB and then passes its address as an argument to a common utility program “QUEUER” along with the device number for which it is intended QUEUER looks at the queue for that device and if no other DCB is at the head of queue (i.e. the variable Head_of_Queue is zero) then it places the DCB address in the Head_of_Queue variable, marks the calling program as inactive if the Reply byte so requested, marks the DCP of the called device active, and then performs a reschedule in which the highest priority process will be awarded the CPU cycles while the state of the running process is saved for later resumption. There are many variations of rescheduling strategies, such as only scanning to determine the highest priority active process if that is not obvious, but a description of all possible real time operating system algorithms is beyond the scope of the current application as it is very dependent on the choice of processor. 
     If on the other hand QUEUER detects a DCB at the head of queue already, it places the address of the new DCB in the placeholder Link of the DCB at the end of the current, non-empty queue where it will be dealt with in turn. 
       FIG.  37    depicts a suitable real-time operating system structure. Data structure ( 100 ) illustrates the Head-Of-queue variable that is an element of an operating system array, there being one element per process, whether it is a hardware device or merely a calculating program. Each process has a process/device number, and its Head-Of-Queue variable is accessed by addressing the array using the process/device number as an index. The 16-bit Head-Of-Queue variable either contains 0000(hex) is the queue is empty of else it contains the address of the DCB at the head of the queue. It therefore points to the first DCB to be served. The link word or first two bytes of the DCB contain either 0000(hex) ii there are no other DCBs in the queue, or else it contains the address of the next DCB in line. It therefore points to the next DCB, forming as linked list with the last DCB in the queue having 0000(hex) in its link word. 
     Device-dependent code ( 200 ) shows the device control program (DCP) structure for processing DCBs. Upon power up, each DCP in turn is entered at a power-up initialization entry point and performs device-dependent initialization tasks that can be relegated to a subroutine call to keep the structure even more alike between different DCPs. The DCP is then deactivated (suspended) until it is reactivated by its Head-of-Queue variable becoming non-zero. When that happens, the code is resumed from where it left off and moves on to get the DCN indicated by the address at its Head-of-Queue variable. It then performs the task indicated by the arguments passed to it in the DCB by the calling process and then exits by calling common code ( 300 ) which is a routine called “NEXTDCB” that performs a number of standard functions common to all DCPs, namely, it returns a value to the caller in the REPLY byte indicative of completion (or otherwise, if other potential conditions can arise), sets the calling process to active it the original value of the REPLY byte had requested suspension, and then transfers the link address form the DCB just processed into the Head-of-Queue variable. The code then returns to examining whether the queue is empty or not. 
     Even when a process is not a hardware device, but just a computing routine, it can be useful to utilize the software structure of  FIG.  37    to communicate data between processes. The reason is that when a result computed by one program comprises more than one byte of piece of data that is desired to be a read by another process, there has to be a way to ensure that a partially processed result is not read. This is assured by passing the computing process a DCB that requests a result, the computing process only testing the queue and replying to the request when computing is complete, thus ensuring partially computed results are not returned. For example, the relay driver program may process requests to change relay states, of which there are 16, the states therefore occupying two bytes. The power computation program requires to know the relay states in order to combine currents with the correct voltages to determine power. Thus the power computation program may pass a DCB to the relay driver DCP requesting the state. This will be dealt with after or before any other DCBs that may be requesting relay state change, thereby guaranteeing that the correct instantaneous relay state is returned. Every process or software context that may be required to run at times unrelated to the times at which other processes run is preferably conformed to the software structure of a DCP as in  FIG.  37   . It is also desirable that every hardware device or chip that cannot be used simultaneously by two asynchronous users be driven by a DCP. An example of this is a 3-to-8 line converter chip such as a 74HC138. Such a chip may be used to convert three digital output lines from a processor into one of eight enables for devices attached to the SPI port. For example, in an exemplary apparatus according to  FIGS.  22  and  34 - 37    there may be two AT-TInies communicating with the ATMEGA main processor using the SPI port, four TPL9201 relay driver chips, a real-time clock-calendar chip and a flash memory for archiving events such as power failure and electrical parameters averaged over various time periods from 15 minutes to one year. Each of the above eight devices has an associated DCP. When the DCP needs to send data to or receive data from its device, it first needs to set the 74HC138 to generate the appropriate enable signal so that the device is the only active device on the SPI port. To avoid conflict between different DCPs all wanting to control the same 74HC138 at possibly the same time, it too may be configured as a device controlled by a DCP, and requests for its use are lodged by queuing a DCB to control it. The DCB passes a request parameter to set it to a given state and mark it as busy, until the calling DCP releases it. The 74HC138 DCP grants its use to the calling DCP via an indication in the REPLY byte. When the calling DCP is finished using the chip, it releases it by canceling the busy signal thus allowing any subsequent DCB issued by a different calling DCP to be serviced. 
     It has thus been described above how to monitor the electrical parameters of multiple loads of branch circuits such as voltage, current, power, power factor and cumulative energy consumption from each source of power when a branch circuit can be powered from one or more sources, and the sources are not necessarily synchronized in phase or frequency, and the sources can experience outages. This desirable function is achieved by use of low-cost microprocessors which are operable even when only one phase of one power source is alive, the microprocessors generating and using their own reference clock which is nominally equal to the frequency of the electrical power sources or an integer multiple thereof such that operation continues uninterrupted when either power source fails, and by use of efficiently implemented complex arithmetic to perform digital signal processing operations that remove the frequency or phase error or drift between the self-generated reference clock and the power sources to produce accurate average values of the electrical parameters. Many variations in the exemplary clock and crystal frequencies, sample rates and digital word lengths may be made by a person of average skill in the art without departing from the spirit and scope of the invention as described by the attached claims. 
     As used herein, the term “configured to” means set up, organized, adapted, or arranged to operate in a particular way; the term is synonymous with “designed to.” 
     The present invention may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.