Patent Publication Number: US-2023163038-A1

Title: Semiconductor package including heat spreader layer

Description:
CROSS-REFERENCE TO THE RELATED APPLICATION 
     This application is a continuation application of U.S. patent application Ser. No. 17/235,502, filed Apr. 20, 2021, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0127014, filed on Sep. 29, 2020, in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     1. Field 
     The inventive concept relates to a semiconductor package, and particularly, to a semiconductor package including a heat spreader layer. 
     2. Description of the Related Art 
     As highly-integrated and miniaturized semiconductor devices are needed, a size of each semiconductor device is progressively reduced. Also, semiconductor packages need to process massive data. Accordingly, semiconductor packages include a plurality of semiconductor chips molded therein. 
     As semiconductor devices are highly integrated and progressively enhanced in performance, heat to be dissipated may excessively occur in semiconductor devices. Thermal interface materials (TIM) may be disposed in semiconductor packages so as to dissipate heat, but may be difficult to be applied to mobile devices requiring small-volume semiconductor packages. 
     SUMMARY 
     The exemplary embodiments of the disclosure provide a semiconductor package which effectively dissipates heat occurring in a semiconductor device. 
     A semiconductor package in accordance with an embodiment of the disclosure may include a connection layer, a semiconductor chip disposed at a center portion of the connection layer, an adhesive layer disposed on the semiconductor chip, a heat spreader layer disposed on the adhesive layer, and a lower redistribution layer disposed on the connection layer and a bottom surface of the semiconductor chip, wherein a width of the adhesive layer may be the same as a width of the semiconductor chip, and a width of the heat spreader layer may be less than the width of the adhesive layer. 
     A semiconductor package in accordance with an embodiment of the disclosure may include a connection layer, a semiconductor chip surrounded by the connection layer, an adhesive layer disposed on the semiconductor chip, a plurality of heat spreader layers disposed on the adhesive layer, and a lower redistribution layer disposed on the connection layer and a bottom surface of the semiconductor chip, wherein a width of the adhesive layer may be the same as a width of the semiconductor chip, a width of each of the plurality of heat spreader layers may be less than a width of the adhesive layer, and the plurality of heat spreader layers may be arranged in a lattice pattern. 
     A semiconductor package in accordance with an embodiment of the disclosure may include a semiconductor chip, an adhesive layer disposed on the semiconductor chip, a thin film layer disposed on the adhesive layer, a heat spreader layer disposed on the thin film layer, an encapsulant covering the semiconductor chip, the adhesive layer, and the heat spreader layer, a lower redistribution layer disposed on a bottom surface of the semiconductor chip and a bottom surface of the encapsulant, the lower redistribution layer including an insulation layer and a wiring pattern, an upper redistribution layer disposed on the encapsulant, a conductive via connecting the lower redistribution layer to the upper redistribution layer, an external connection terminal disposed on a bottom surface of the lower redistribution layer and electrically connected to the semiconductor chip and the conductive via through the wiring pattern, and a heat dissipation via passing through the encapsulant and the upper redistribution layer and vertically overlapping the heat spreader layer, wherein a width of the adhesive layer may be the same as a width of the semiconductor chip, a width of the thin film layer may be less than a width of the adhesive layer and may be the same as a width of the heat spreader layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1 A  is a vertical cross-sectional view of a semiconductor package according to an embodiment of the disclosure. 
         FIG.  1 B  is a vertical cross-sectional view of a semiconductor package according to an embodiment of the disclosure. 
         FIG.  2    is a horizontal cross-sectional view taken along line I-I′ of the semiconductor package illustrated in  FIG.  1   . 
         FIG.  3 A  is a vertical cross-sectional view taken along line II-II′ of the semiconductor package illustrated in  FIG.  2   . 
         FIG.  3 B  is a vertical cross-sectional view taken along line of the semiconductor package illustrated in  FIG.  2   . 
         FIG.  4    is a vertical cross-sectional view of a semiconductor package according to an embodiment of the disclosure. 
         FIG.  5    is a horizontal cross-sectional view taken along line IV-IV′ of the semiconductor package illustrated in  FIG.  4   . 
         FIG.  6 A  is a vertical cross-sectional view taken along line V-V′ of the semiconductor package illustrated in  FIG.  5   . 
         FIG.  6 B  is a vertical cross-sectional view taken along line VI-VI′ of the semiconductor package illustrated in  FIG.  5   . 
         FIGS.  7 A and  7 B  are vertical cross-sectional views of a semiconductor package according to an embodiment of the disclosure. 
         FIG.  8    is a horizontal cross-sectional view taken along line VII-VII′ of the semiconductor package illustrated in  FIGS.  7 A and  7 B . 
         FIG.  9    is a vertical cross-sectional view of a semiconductor package according to an embodiment of the disclosure. 
         FIG.  10    is a horizontal cross-sectional view taken along line X-X′ of the semiconductor package illustrated in  FIG.  9   . 
         FIG.  11    is a vertical cross-sectional view of a semiconductor package according to an embodiment of the disclosure. 
         FIG.  12    is a vertical cross-sectional view of a semiconductor package according to an embodiment of the disclosure. 
     
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       FIG.  1 A  is a vertical cross-sectional view of a semiconductor package according to an embodiment of the disclosure.  FIG.  1 B  is a vertical cross-sectional view of a semiconductor package according to an embodiment of the disclosure.  FIG.  2    is a horizontal cross-sectional view taken along line I-I′ of the semiconductor package illustrated in  FIG.  1   .  FIG.  3 A  is a vertical cross-sectional view taken along line II-IF of the semiconductor package illustrated in  FIG.  2   .  FIG.  3 B  is a vertical cross-sectional view taken along line of the semiconductor package illustrated in  FIG.  2   . 
     Referring to  FIGS.  1 A to  3 B , a semiconductor package  100  according to an embodiment of the disclosure may include a connection layer  110 , a semiconductor chip  120 , an adhesive layer  130 , a thin film layer  140 , a heat spreader layer  150 , a lower redistribution layer  160 , an external connection terminal  170 , an encapsulant  180 , and an upper redistribution layer  190 . 
     The connection layer  110  may be a plate having a tetragonal rim shape in a top view. The connection layer  110  may include a cavity  112 , a core  114 , conductive pads  116 , and conductive vias  118 . The cavity  112  may be formed at a center portion of the connection layer  110 . The core  114  may include a first core  114   a  including a bottom surface contacting the lower redistribution layer  160 , and a second core  114   b  disposed on the first core  114   a . The conductive pads  116  may include a first conductive pad  116   a  buried into the first core  114   a , a second conductive pad  116   b  disposed on the first core  114   a , and a third conductive pad  116   c  disposed on the second core  114   b . For example, a bottom surface of the first conductive pad  116   a  and the bottom surface of the first core  114   a  may be coplanar and the first conductive pad  116   a  may protrude into the first core  114   a , a bottom surface of the second conductive pad  116   b  and a top surface of the first core  114   a  may be coplanar and the second conductive pad  116   b  may protrude from the top surface of the first core  114   a , and a bottom surface of the third conductive pad  116   c  and a top surface of the second core  114   b  may be coplanar and the third conductive pad  116   c  may protrude from the top surface of the second core  114   b . The conductive vias  118  may include a first conductive via  118   a  which passes through the first core  114   a  and electrically connects the first conductive pad  116   a  to the second conductive pad  116   b , and a second conductive via  118   b  which passes through the second core  114   b  and electrically connects the second conductive pad  116   b  to the third conductive pad  116   c.    
     It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact. 
     Spatially relative terms, such as “top,” “bottom,” “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe positional relationships, such as illustrated in the figures, e.g. It will be understood that the spatially relative terms encompass different orientations of the device in addition to the orientation depicted in the figures. 
     Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, compositions, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, composition, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, compositions, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes. 
     For example, the core  114  may include an insulating material. The insulating material may be a thermo curable resin such as an epoxy resin, a thermoplastic resin such as polyimide, or an insulating material (for example, prepreg, Ajinomoto build-up film (ABF), FR-4, and bismaleimide triazine (BT)) where each of the resins is impregnated into a core material such as an inorganic filler and/or a glass fiber (for example, glass cloth or glass fabric). 
     For example, the conductive pads  116  may include at least one of electrolytically deposited (ED) copper foil, rolled-annealed (RA) copper foil, stainless steel foil, aluminum foil, ultra-thin copper foils, sputtered copper, and copper alloys. For example, the conductive via  118  may include at least one of copper (Cu), nickel (Ni), stainless steel, and beryllium copper. 
     The semiconductor chip  120  may be disposed in the cavity  112 . For example, the semiconductor chip  120  may be disposed to be surrounded by the connection layer  110  such that outer side surfaces of the semiconductor chip face inner side surfaces of the connection layer  110 . The semiconductor chip  120  may be described as being disposed at a center portion of the connection layer  110 , for example, such that taking the entire connection layer outer boundary as a whole, the semiconductor chip  120  is disposed at a center portion within that boundary. A horizontal width of the semiconductor chip  120  may be less than a horizontal width of the cavity  112 . The semiconductor chip  120  may be disposed to be spaced apart from an inner surface of the connection layer  110 . A chip pad  122  may be disposed under the semiconductor chip  120 . A bottom surface of the chip pad  122  may be coplanar with a bottom surface of the semiconductor chip  120 . For example, the chip pad  122  may be embedded in the semiconductor chip  120 . The bottom surface of the chip pad  122  may be coplanar with a bottom surface of the first conductive pad  116   a . In an embodiment, the chip pad  122  may have a structure which is disposed on the bottom surface of the semiconductor chip  120  to protrude from the bottom surface of the semiconductor chip  120 . 
     The semiconductor chip  120  may include and/or may be an application processor (AP) chip such as a microprocessor or a microcontroller, a logic chip such as a central processing unit (CPU), a graphics processing unit (GPU), modem, an application-specific integrated circuit (ASIC), or a field programmable gate array (FPGA), a volatile memory such as dynamic random access memory (DRAM) or static random access memory (SRAM), and a non-volatile memory such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM). In each embodiments of the disclosure, one semiconductor chip  120  is illustrated, but this is merely an example and plural semiconductor chips may be included in a package, and the semiconductor chip  120  may include and/or may be any one or more of semiconductor chips of all types which are to be packaged, like 2.1-dimensional (2.1D) semiconductor chips, 2.5-dimensional (2.5D) semiconductor chips, and three-dimensional (3D) semiconductor chips. 
     The adhesive layer  130  may be disposed on the semiconductor chip  120 . The adhesive layer  130  may completely cover a top surface of the semiconductor chip  120 . For example, a width W 1  of the adhesive layer  130  in a first horizontal direction D 1  may be the same as a width of the semiconductor chip  120  in the first horizontal direction D 1 , and a width W 2  of the adhesive layer  130  in a second horizontal direction D 2  may be the same as a width of the semiconductor chip  120  in the second horizontal direction D2. A thickness H1 of the adhesive layer  130  may be about 2 μm to about 8 μm. The adhesive layer  130  may include a material which is relatively higher in thermal conductivity than an organic compound. For example, the adhesive layer  130  may include at least one of silicon oxide (SiO x ), epoxy, polyimide (PI), and polymex. When the adhesive layer  130  includes at least one of silicon oxide, epoxy, polyimide, and polymex, a heat dissipation effect may be higher than when the adhesive layer  130  includes an organic compound having relatively low thermal conductivity. The adhesive layer  130  may be provided between the semiconductor chip  120  and the thin film layer  140 , and thus, an adhesive force between the semiconductor chip  120  and the thin film layer  140  may be improved. 
     Terms such as “about” or “approximately” may reflect amounts, sizes, orientations, or layouts that vary only in a small relative manner, and/or in a way that does not significantly alter the operation, functionality, or structure of certain elements. Distances described as the same as other distances, half of other distances, etc., may be exactly the same or half, or may be substantially the same, half, etc., within acceptable variations caused by manufacturing, etc. For example, a range from “about 0.1 to about 1” may encompass a range such as a 0%-5% deviation around 0.1 and a 0% to 5% deviation around 1, especially if such deviation maintains the same effect as the listed range. 
     The thin film layer  140  may be disposed on the adhesive layer  130 . A width W 3  of the thin film layer  140  in the first horizontal direction D 1  may be less than the width W 1  of the adhesive layer  130  by two times a first length S 1  in the first horizontal direction D 1 . For example, the first length S 1  may be about 1 μm to about 4 μm. A width W 4  of the thin film layer  140  in the second horizontal direction D 2  may be less than the width W 2  of the adhesive layer  130  by two times a second length S 2  in the second horizontal direction D 2 . For example, the second length S 2  may be about 1 μm to about 4 μm. In an embodiment, the first length S 1  may be the same as the second length S 2 . For example, the first horizontal direction D 1  may be perpendicular to the second horizontal direction D 2 . 
     A thickness H 2  of the thin film layer  140  may be about 0.04 μm to about 0.16 μm. The thin film layer  140  may include or be formed of a material which is less in coefficient of thermal expansion (CTE) than the heat spreader layer  150 . For example, the thin film layer  140  may include or be formed of at least one of tungsten (W), titanium (Ti), tantalum (Ta), silicon oxide (SiO x ), tantalum oxide (TaO), silicon nitride (SiN), and tantalum nitride (TaN). 
     The heat spreader layer  150  may be disposed on the thin film layer  140 . A width W 5  of the heat spreader layer  150  in the first horizontal direction D 1  may be the same as a width 3  of the thin film layer  140  in the first horizontal direction D 1 , and a width W 6  of the heat spreader layer  150  in the second horizontal direction D 2  may be the same as a width W 4  of the thin film layer  140  in the second horizontal direction D 2 . A thickness H 3  of the heat spreader layer  150  may be about 2 μm to about 8 μm. In an embodiment, the thickness H 3  of the heat spreader layer  150  may be the same as the thickness H 1  of the adhesive layer  130 . The heat spreader layer  150  may include or be formed of a material which is high in thermal conductivity. For example, the heat spreader layer  150  may include or be formed of at least one of Cu, a Cu alloy, diamond (C), carbon nano tube (CNT), and boron nitride (BN). The thin film layer  140  may include or be formed of a material which is lower in CTE than the heat spreader layer  150 , and thus, may prevent the heat spreader layer  150  from thermally expanding and penetrating into the semiconductor chip  120  or the adhesive layer  130 . 
     The lower redistribution layer  160  may be disposed on a bottom surface of the connection layer  110 . The lower redistribution layer  160  may include an insulation layer  162  and a wiring pattern. The wiring pattern may include a redistribution pattern  164 , a conductive via  166 , and an under bump metallurgy (UBM)  168 . For example, the UBM  168  may be a metal pattern which the external connection terminal  170  may contact. The insulation layer  162  may include a plurality of first insulation layers  162   a , each including a top surface contacting the connecting layer  110 , and a second insulation layer  162   b  which is disposed on a bottom surface of the first insulation layer  162   a  and includes a bottom surface exposed. For example, the plurality of the first insulation layers  162   a  may be laterally arranged. For example, the plurality of the first insulation layers  162   a  may be positioned at the same vertical level. 
     The redistribution pattern  164  may include a first redistribution pattern  164   a  buried into the first insulation layer  162   b  and a second redistribution pattern  164   b  disposed on the bottom surface of the first insulation layer  162   b . Conductive vias  166  may include a first conductive via  166   a , which passes through the first insulation layer  162   a  and electrically connects the first conductive pad  116   a  to the first redistribution pattern  164   a , and a second conductive via  166   b  which passes through the second insulation layer  162   b  and electrically connects the first redistribution pattern  164   a  to the second redistribution pattern  164   b . The UBM  168  may be disposed on a bottom surface of the second redistribution pattern  164   b . For example, the insulation layer  162  may include or be formed of ABF, epoxy, or polyimide. The insulation layer  162  may include or be formed of a photosensitive polymer. For example, the photosensitive polymer may include at least one of photosensitive polyimide, polybenzoxazole, a phenolic polymer, and a benzocyclobutene-based polymer. The redistribution pattern  164  and the UBM  168  may include or be formed of Cu, Ni, stainless steel, or a Cu alloy such as beryllium copper. 
     The external connection terminal  170  may be disposed on a bottom surface of the UBM  168 . The external connection terminal  170  may be electrically connected to the lower redistribution layer  160 . The external connection terminal  170  may be electrically connected to the semiconductor chip  120  and/or the conductive via  118  through the wiring pattern of the lower redistribution layer  160 . The external connection terminal  170  may be a solder ball or a solder bump. 
     The encapsulant  180  may be disposed on the lower redistribution layer  160 . The encapsulant  180  may be filled into a space between the connection layer  110  and the semiconductor chip  120 , the adhesive layer  130 , the thin film layer  140 , and the heat spreader layer  150 . For example, the encapsulant  180  may include or be formed of an insulating material such as ABF. 
     The upper redistribution layer  190  may be disposed on a top surface of the encapsulant  180 . A sidewall of the upper redistribution layer  190  may be disposed to be vertically aligned with a portion of an outer sidewall of the encapsulant  180 . The upper redistribution layer  190  may be electrically connected to the lower redistribution layer  160  through the conductive vias  118 . 
     The upper redistribution layer  190  may include an insulation layer  192 , a redistribution pattern  194 , and a conductive via  196 . The insulation layer  192  may include a first insulation layer  192   a  including a bottom surface contacting the encapsulant  180 , a second insulation layer  192   b  disposed on a top surface of the first insulation layer  192   a , and a third insulation layer  192   c  disposed on a top surface of the second insulation layer  192   b . The third insulation layer  192   c  may be a passivation layer. As illustrated in  FIG.  1 A , the redistribution pattern  194  may include a first redistribution pattern  194   a  buried into both/opposite portions of the second insulation layer  192   b , a second redistribution pattern  194   b  disposed at both/opposite sides of the top surface of the second insulation layer  192   b , and a third redistribution pattern  194   c  disposed at both/opposite sides of the top surface of the third insulation layer  192   c . As illustrated in  FIG.  1 B , the redistribution pattern  194  may include only the third redistribution pattern  194   c . For example, the redistribution pattern  194  may be formed of a single layer of redistribution pattern. 
     As illustrated in  FIG.  1 A , conductive vias  196  may include a first conductive via  196   a  which passes through the encapsulant  180  and the first insulation layer  192   a  and electrically connects the third conductive pad  116   c  to the first redistribution pattern  194   a , a second conductive via  196   b  which passes through the second insulation layer  192   b  and electrically connects the first redistribution pattern  194   a  to the second redistribution pattern  194   b , and a third conductive via  196   c  which passes through the third insulation layer  192   c  and electrically connects the second redistribution pattern  194   b  to the third redistribution pattern  194   c . As illustrated in  FIG.  1 B , the conductive via  196  may include only a fourth conductive via  196   d  which passes through the encapsulant  180 , the first insulation layer  192   a , and the second insulation layer  192   b  and electrically connects the third conductive pad  116   c  to the third redistribution pattern  194   c.    
     As illustrated in  FIG.  1 A , a heat dissipation pad  198  and a heat dissipation via  199  may be disposed at a center portion of the encapsulant  180  and a center portion of the upper redistribution layer  190 . The heat dissipation pad  198  and the heat dissipation via  199  may be covered by a fourth insulation layer  192   d . The heat dissipation via  199  may vertically overlap the semiconductor chip  120 , the adhesive layer  130 , the thin film layer  140 , and the heat spreader layer  150 . Heat dissipation pads  198  may include a first heat dissipation pad  198   a  disposed at a center portion of an inner sidewall of the encapsulant  180 , a second heat dissipation pad  198   b  buried into a center portion of the first insulation layer  192   a , and a third heat dissipation pad  198   c  disposed on a top surface of the third insulation layer  192   c . Heat dissipation vias  199  may include a first heat dissipation via  199   a  which passes through the encapsulant  180  and connects the first heat dissipation pad  198   a  to the second heat dissipation pad  198   b , and a second heat dissipation via  199   b  which passes through the first insulation layer  192   a , the second insulation layer  192   b  and the third insulation layer  192   c  and electrically connects the second heat dissipation pad  198   b  to the third heat dissipation pad  198   c.    
     As illustrated in  FIG.  1 B , the heat dissipation via  199  may include a third heat dissipation via  199   c  which passes through the encapsulant  180 , the first insulation layer  192   a , and the second insulation layer  192   b . When the heat dissipation via  199  includes only the third heat dissipation via  199   c , a heat dissipation layer  199   d  may be disposed on the top surface of the second insulation layer  192   b , and a plurality of third heat dissipation vias  199   c  may be thermally connected to one another by the heat dissipation layer  199   d . The heat dissipation via  199  may be formed by a CO 2  laser process. For example, the heat dissipation pad  198  and the heat dissipation via  199  may include at least one of Cu, a Cu alloy, diamond (C), CNT, and BN. Heat generated/occurring in the semiconductor chip  120  may transfer/flow to the heat spreader layer  150  through the adhesive layer  130  and the thin film layer  140  and may be dissipated to the outside through the heat dissipation pad  198  and the heat dissipation vias  199 . 
       FIG.  4    is a vertical cross-sectional view of a semiconductor package according to an embodiment of the disclosure.  FIG.  5    is a horizontal cross-sectional view taken along line IV-IV′ of the semiconductor package illustrated in  FIG.  4   .  FIG.  6 A  is a vertical cross-sectional view taken along line V-V′ of the semiconductor package illustrated in  FIG.  5   .  FIG.  6 B  is a vertical cross-sectional view taken along line VI-VI′ of the semiconductor package illustrated in  FIG.  5   . 
     Referring to  FIGS.  4  to  6 B , a semiconductor package  100  according to an embodiment of the disclosure may include a connection layer  110 , a semiconductor chip  120 , an adhesive layer  130 , a plurality of thin film layers  240 , a plurality of heat spreader layers  250 , a lower redistribution layer  160 , an external connection terminal  170 , an encapsulant  180 , and an upper redistribution layer  190 . 
     The adhesive layer  130  may be disposed on the semiconductor chip  120 . The plurality of thin film layers  240  may be disposed on the adhesive layer  130 . The plurality of thin film layers  240  may be disposed in a lattice pattern. For example, two thin film layers  240  may be disposed laterally in a first horizontal direction D 1 . Each of the plurality of thin film layers  240  may be apart from, by a first length S 1 , a corresponding corner of the adhesive layer  130  in a second horizontal direction D 2  and may be apart from, by a second length S 2 , the corresponding corner of the adhesive layer  130  in the first horizontal direction D 1 . Adjacent thin film layers  240  may be apart from each other by a third length S 3  with respect to the first horizontal direction D 1  and may be apart from each other by a fourth length S 4  with respect to the second horizontal direction D 2 . A width W 7  of each of the thin film layers  240  in the first horizontal direction D 1  and a width W 8  of each of the thin film layers  240  in the second horizontal direction D 2  may be expressed as the following Equations 1 and 2. 
     
       
         
           
             
               
                 
                   
                     W 
                     7 
                   
                   = 
                   
                     
                       
                         W 
                         1 
                       
                       2 
                     
                     - 
                     
                       S 
                       1 
                     
                     - 
                     
                       
                         S 
                         3 
                       
                       2 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                         
                     1 
                   
                   ] 
                 
               
             
             
               
                 
                   
                     W 
                     8 
                   
                   = 
                   
                     
                       
                         W 
                         2 
                       
                       2 
                     
                     - 
                     
                       S 
                       2 
                     
                     - 
                     
                       
                         S 
                         4 
                       
                       2 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                         
                     2 
                   
                   ] 
                 
               
             
           
         
       
     
     The first length S 1  may be half of the third length S 3 , and the second length S 2  may be half of the fourth length S 4 . In this case, the width W 7  of each of the thin film layers  240  in the first horizontal direction D 1  and the width W 8  of each of the thin film layers  240  in the second horizontal direction D 2  may be expressed as the following Equations 3 and 4. 
     
       
         
           
             
               
                 
                   
                     W 
                     7 
                   
                   = 
                   
                     
                       
                         W 
                         1 
                       
                       2 
                     
                     - 
                     
                       2 
                       ⁢ 
                       
                         S 
                         1 
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                         
                     3 
                   
                   ] 
                 
               
             
             
               
                 
                   
                     W 
                     8 
                   
                   = 
                   
                     
                       
                         W 
                         2 
                       
                       2 
                     
                     - 
                     
                       2 
                       ⁢ 
                       
                         S 
                         2 
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                         
                     4 
                   
                   ] 
                 
               
             
           
         
       
     
     For example, when each of the first length S 1  and the second length S 2  is about 1 μm to about 4 μm, the width W 7  of each of the thin film layers  240  in the first horizontal direction D 1  and the width W 8  of each of the thin film layers  240  in the second horizontal direction D 2  may respectively be 2 μm to 8 μm less than half of the width W 1  of the adhesive layer  130  in the first horizontal direction D 1  and half of the width W 2  of the adhesive layer  130  in the second horizontal direction D 2 . In an embodiment, when the width W 1  of the adhesive layer  130  in the first horizontal direction D 1  is the same as the width W 2  of the adhesive layer  130  in the second horizontal direction D 2  and the first length S 1 , the second length S 2 , the third length S 3 , and the fourth length S 4  are the same, the width W 7  of each of the thin film layers  240  in the first horizontal direction D 1  may be the same as the width W 8  of each of the thin film layers  240  in the second horizontal direction D 2 . 
     The plurality of heat spreader layers  250  may be respectively disposed on the plurality of thin film layers  240 . The plurality of heat spreader layers  250  may be disposed in a lattice pattern. A width W 9  of each of the heat spreader layers  250  in the first horizontal direction D 1  may be the same as the width W 7  of each of the thin film layers  240  in the first horizontal direction D 1 , and a width W 10  of each of the heat spreader layers  250  in the second horizontal direction D 2  may be the same as the width W 8  of each of the thin film layers  240  in the second horizontal direction D 2 . The widths W 7  and W 8  of each of the thin film layers  240  and the widths W 9  and W 10  of each of the heat spreader layers  250  may be set to be less than the widths W 7  and W 8  of the adhesive layer  130 , thereby decreasing an effective area of a warpage phenomenon of the semiconductor package  100  caused by a stress of the heat spreader layer  250  having a relatively large CTE in a semiconductor manufacturing process performed at a high temperature. 
       FIGS.  7 A and  7 B  are vertical cross-sectional views of a semiconductor package according to an embodiment of the disclosure.  FIG.  8    is a horizontal cross-sectional view taken along line VII-VII′ of the semiconductor package illustrated in  FIGS.  7 A and  7 B . 
     Referring to  FIGS.  7 A to  8   , a semiconductor package  300  according to an embodiment of the disclosure may include an encapsulant  310 , a connection layer  312 , a semiconductor chip  320 , an adhesive layer  330 , a thin film layer  340 , a heat spreader layer  350 , a lower redistribution layer  360 , an external connection terminal  370 , and an upper redistribution layer  380 . 
     The semiconductor chip  320 , the adhesive layer  330 , the thin film layer  340 , the heat spreader layer  350 , the lower redistribution layer  360 , and the upper redistribution layer  380  may be respectively the same as the semiconductor chip  120 , the adhesive layer  130 , the thin film layer  140 , the heat spreader layer  150 , the lower redistribution layer  160 , and the upper redistribution layer  180  illustrated in  FIGS.  1  to  3 B . A vertical cross-sectional view taken along line VIII-VIII′ of  FIG.  8    and a vertical cross-sectional view taken along line IX-IX′ of  FIG.  8    may be respectively the same as  FIGS.  3 A and  3 B . 
     The encapsulant  310  may have a structure which covers the heat spreader layer  350  and the lower redistribution layer  360 . A vertical-direction inner sidewall of the encapsulant  310  may contact a sidewall of the semiconductor chip  320  and a sidewall of the adhesive layer  350 . A horizontal inner surface of the encapsulant  310  may contact a top surface of the heat spreader layer  350 . For example, the encapsulant  312  may include or be formed of an epoxy molding compound (EMC), a thermoplastic resin such as polyimide, or a resin where a reinforcing agent such as an inorganic filler is added thereto, and for example, may include or be formed of ABF, FR-4, BT, or a resin. Also, the encapsulant  312  may include or be formed of a molding material such as an EMC or a photosensitive material such as PIE. The connection layer  312  may pass through the encapsulant  310  and may be a conductive via which electrically connects the lower redistribution layer  360  to the upper redistribution layer  380 . 
     The external connection terminal  370  may be disposed on a bottom surface of the lower redistribution layer  360 . A horizontal-direction width of a portion of the lower redistribution layer  360  on which external connection terminals  370  are disposed may be greater than a horizontal-direction width of the semiconductor chip  320  as illustrated in  FIG.  7 A  or may be less than the horizontal-direction width of the semiconductor chip  320  as illustrated in  FIG.  7 B . For example, the semiconductor chip  320  may vertically overlap all of the external connection terminals  370  attached on the lower redistribution layer  360  in some embodiments. In certain embodiments, one or more of the external connection terminals  370  attached on the lower redistribution layer  360  do not vertically overlap the semiconductor chip  320 . 
       FIG.  9    is a vertical cross-sectional view of a semiconductor package according to an embodiment of the disclosure.  FIG.  10    is a horizontal cross-sectional view taken along line X-X′ of the semiconductor package illustrated in  FIG.  9   . 
     Referring to  FIGS.  9  and  10   , a semiconductor package  300  according to an embodiment of the disclosure may include an encapsulant  310 , a connection layer  312 , a semiconductor chip  320 , an adhesive layer  330 , a plurality of thin film layers  340 , a plurality of heat spreader layers  350 , a lower redistribution layer  360 , an external connection terminal  370 , and an upper redistribution layer  380 . 
     The semiconductor chip  320 , the adhesive layer  330 , the thin film layers  340 , the heat spreader layers  350 , the lower redistribution layer  360 , and the upper redistribution layer  380  may be respectively the same as the semiconductor chip  120 , the adhesive layer  130 , the thin film layers  240 , the heat spreader layers  250 , the lower redistribution layer  160 , and the upper redistribution layer  190  illustrated in  FIGS.  4  to  6 B . A vertical cross-sectional view taken along line XI-XI′ of  FIG.  10    and a vertical cross-sectional view taken along line XII-XII′ of  FIG.  10    may be respectively the same as  FIGS.  6 A and  6 B . 
       FIG.  11    is a vertical cross-sectional view of a semiconductor package  500  according to an embodiment of the disclosure. 
     Referring to  FIG.  11   , the semiconductor package  500  may include a lower semiconductor package  510  and an upper semiconductor package  520 . Each of the lower semiconductor package  510  and the upper semiconductor package  520  may be the same as one of the semiconductor packages  100  to  300  illustrated in  FIGS.  1  to  10   . 
     The lower semiconductor package  510  and the upper semiconductor package  520  may be electrically connected to each other by an external connection terminal of the upper semiconductor package  520 . 
       FIG.  12    is a vertical cross-sectional view of a semiconductor package  600  according to an embodiment of the disclosure. 
     Referring to  FIG.  12   , the semiconductor package  600  may include a lower semiconductor package  610 , an upper semiconductor package  620 , and a wire  630 . Each of the lower semiconductor package  610  and the upper semiconductor package  620  may be the same as one of the semiconductor packages  100  to  300  illustrated in  FIGS.  1  to  10   . The upper semiconductor package  620  may be disposed on the lower semiconductor package  610 . The lower semiconductor package  610  and the upper semiconductor package  620  may be electrically connected to each other by the wire  630 . 
     According to the embodiments of the disclosure, a width of a heat spreader layer may be set to be less than that of a semiconductor package, and thus, a heat spreader layer may be prevented from being diffused to a semiconductor chip in a semiconductor manufacturing process performed at a high temperature. 
     According to the embodiments of the disclosure, only an adhesive layer and a thin film layer may be provided between the semiconductor chip and the heat spreader layer, thereby decreasing the manufacturing cost. For example, the adhesive layer and the thin film layer may replace all other layers, patterns and/or materials previously used. 
     According to the embodiments of the disclosure, the adhesive layer including silicon oxide and/or the like may be provided between the semiconductor chip and the heat spreader layer, and thus, heat occurring/generated in the semiconductor package may be more effectively dissipated than a case where an adhesive layer including an organic material is provided. 
     Hereinabove, the embodiments of the disclosure have been described with reference to the accompanying drawings, but it may be understood that those skilled in the art may implement the embodiments in another detailed form without changing the inventive concept or the essential feature. It should be understood that the embodiments described above are merely examples in all aspects and are not limited.