Patent Publication Number: US-6710418-B1

Title: Schottky rectifier with insulation-filled trenches and method of forming the same

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates in general to semiconductor technology and in particular to improved Schottky rectifier structures and methods of manufacturing the same. 
     Silicon-based power rectifiers are well known and have been used in power electronic systems for many decades. Silicon Schottky rectifiers have generally been used in applications operating at mid to low voltages due to their lower on-state voltage drop and faster switching speed. A conventional planar Schottky rectifier structure is shown in FIG. 1A. A top metal electrode forms a Schottky contact with the underlying semiconductor region  106 . The traditional method of optimizing this rectifier changes the Schottky contact metal to alter the barrier height. Although the on-state voltage drop can be reduced by decreasing the barrier height, the reverse leakage current increases exponentially leading to unstable operation at high temperatures. Attempts to improve upon this tradeoff between on-state and reverse blocking power losses has led to the development of the junction barrier controlled Schottky (JBS) structure shown in FIG.  1 B. 
     In FIG. 1B, closely-spaced p-type regions  114  are formed in n-type region  112 . A top metal electrode  113  forms a Schottky contact with the surface area of n-type region  112  between p-type regions  114 , and forms an ohmic contact with p-type regions  114 . The pn junction formed by p-type regions  114  and n-type region  112  forms a potential barrier below the Schottky contact, resulting in a lower electric field at the metal-semiconductor interface. The resulting suppression of the barrier height lowering responsible for the poor reverse leakage in these devices allowed some improvements in the power loss tradeoff. However, the Schottky contact area through which the on-state current flows is reduced due the lateral diffusion of p-type regions  114 , and the series resistance is increased by current constriction between the junctions. 
     Further performance improvements have been obtained by the incorporation of a trench MOS region under the Schottky contact to create the trench MOS-barrier Schottky (TMBS) rectifier structure shown in FIG.  1 C. The MOS structure greatly reduces the electric field under the Schottky contact while enabling the support of voltages far in excess of the parallel-plane breakdown voltage in mesa region  119 . This allows optimizing mesa region  119  to have a higher diping concentration thus reducing the rectifier&#39;s on state voltage drop A further improvement in the electric field distribution under the Schottky contact has been obtained by using a graded doping profile in the mesa region. 
     It has been observed however, that the TMBS structure suffers from high leakage due to phosphorous segregation at the oxide-silicon interface. The increased phosphorous concentration reduces the accumulation threshold on the mesa sidewalls and increases the leakage current. Further, the TMBS and JBS structures have higher capacitance due to the presence of MOS structures  118  in the TMBS structure and the presence of p-type regions  114  in the JBS structure. 
     Thus, Schottky rectifiers having a low forward voltage, high reverse breakdown voltage, and low capacitance which do not suffer from high leakage are desirable. 
     BRIEF SUMMARY OF THE INVENTION 
     In accordance with an embodiment of the present invention, a semiconductor rectifier includes an insulation-filled trench formed in a semiconductor region. Strips of resistive material extend along the trench sidewalls. The strips of resistive material have a conductivity type opposite that of the semiconductor region. A conductor extends over and in contact with the semiconductor region so that the conductor and the underlying semiconductor region form a Schottky contact. 
     In one embodiment, the semiconductor region is formed over a substrate, and the substrate and the semiconductor region have the same conductivity type. 
     In another embodiment, the strips of resistive material are discontinuous along the bottom of the insulation-filled trench. 
     In another embodiment, the strips of resistive material comprise doped silicon material. 
     In another embodiment, the conductor is in contact with the strips of resistive material. 
     In another embodiment, the strips of resistive material comprise silicon material having a doping concentration of about four to five times greater than a doping concentration of the semiconductor region. 
     In accordance with another embodiment of the present invention, a semiconductor rectifier is formed as follows. A trench is formed in a semiconductor region. Strips of resistive material are formed along the trench sidewalls. The strips of resistive material have a conductivity type opposite that of the semiconductor region. The trench is substantially filled with insulating material. A conductor is formed over and in contact with the semiconductor region so that the conductor and the underlying semiconductor region form a Schottky contact. 
     In another embodiment, the semiconductor region is formed over a substrate, and the substrate and the semiconductor region have the same conductivity type. 
     In another embodiment, the strips of resistive material are discontinuous along the bottom of the trench. 
     In another embodiment, the strips of resistive material comprise silicon material having a doping concentration of about four to five times greater than a doping concentration of the semiconductor region. 
     The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the present invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A,  1 B, and  1 C show cross-section views of three known Schottky rectifier structures; 
     FIG. 2 shows a cross-section view of a Schottky rectifier structure in accordance with an embodiment of the present invention; and 
     FIGS. 3A,  3 B, and  3 C show cross-section views at different process steps exemplifying one method for manufacturing the Schottky rectifier structure in FIG. 2 in accordance with an embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments of a semiconductor Schottky rectifier with insulation-filled trenches and method of forming the same are described in accordance with the invention. Strips of resistive elements extending along the trench sidewalls result in high breakdown voltage, enabling the doping concentration of the mesa region to be increased so that a lower forward voltage is obtained. Further, by filling the trenches with insulation rather than silicon material, a far lower device capacitance is achieved. 
     FIG. 2 shows a cross-section view of a Schottky rectifier structure  200  in accordance with an embodiment of the present invention. An epitaxial layer  204  over a substrate  202  includes a plurality of insulation-filled trenches  214  extending from a top surface of epitaxial layer  204  to a predetermined depth. Each trench  214  is lined with a strip  208  of lightly-doped silicon material along its sidewalls. Silicon strips  208  are of opposite conductivity type to epitaxial layer  204  and substrate  202 . A conductoer  210 , e.g., from metal, extending along the top surface forms the anode electrode of rectifier  200 . Conductor  210  forms a Schottky contact with the underlying epitaxial layer  204 , and also contacts silicon strips  208  at the top. Another conductor  216  extending along the bottom surface contacts substrate  202  and forms the cathode electrode of rectifier  200 . 
     Silicon strips  208  influence the vertical charge distribution in the mesa region such that the electric field spreads deeper into the mesa region resulting in a more uniform field throughout the depth of the mesa region. A higher breakdown voltage is thus achieved. Strips  208  also prevent the low accumulation threshold of the TMBS structure thus eliminating the high leakage problem of the TMBS structure. Further, trenches  214  can be made as narrow as the process technology allows, thus increasing the Schottky contact area. Moreover, because a significant portion of the space charge region is supported in the insulation-filled trenches, the capacitance of the rectifier is substantially reduced. This is because the permitivity of insulators is greater than silicon (e.g., four times greater for oxide). 
     In one embodiment wherein a breakdown voltage of 80-100V is desired, epitaxial layer  204  has a doping concentration in the range of 5×10 15  to 1×10 16  cm −3  and strips  208  have a doping concentration of about 5-10 times that of epitaxial layer  204 . The doping concentration in p strips  208  impacts the capacitance of the rectifier. Highly-doped p strips lead to higher capacitance since a higher reverse bias potential is needed to fully deplete the p strips. Thus, if capacitance reduction is a design goal, then a low doping concentration would be more desirable for p strips  208 . 
     To achieve effective vertical charge control, spacing Lp between adjacent strips  208  needs to be carefully engineered. In one embodiment, spacing Lp is determined in accordance with the following proposition: the product of the doping concentration in the mesa region and the spacing Lp be in the range of 2×10 12  to 4×10 12  cm −2 . Thus, for example, for a mesa region doping concentration of 5×10 15  cm −3 , the spacing Lp needs to be about 4 μm. 
     FIGS. 3A,  3 B, and  3 C show cross-section views at different process steps exemplifying one method for manufacturing the Schottky rectifier structure in FIG. 2 in accordance with an embodiment of the invention. In FIG. 3A, a hard mask  314  along with conventional silicon trench etch methods are used to etch epitaxial layer  304  to form trench openings  316 . Using the same mask  314 , p liners  318  are formed by implanting p-type impurities at about a 20° angle into both sidewalls and bottom of the trenches using conventional methods. In FIG. 3B, the portion of p liners  318  along the bottom of the trenches are removed using conventional silicon etch methods, thus leaving p strips  308  along the sidewalls of the trenches. In FIG. 3C, a thermally-grown oxide layer  320  is formed along the inner sidewalls and bottom of each trench. The p-type dopants in p strips  308  are then activated using conventional methods. Conventional oxide deposition steps (e.g., SOG method) are carried out to fill the trenches with oxide, followed by planarization of the oxide surface. Note that in the FIG. 2 structure the thermally grown oxide liners, similar to those in FIG. 3C, are present but not shown for simplicity. The thermally grown oxide layers are included to provide a cleaner interface between the trench insulator and the p strips. 
     While the above is a complete description of the embodiments of the present invention, it is possible to use various alternatives, modifications and equivalents. For example, the cross-sectional views are intended for depiction of the various regions in the different structures and do not necessarily limit the layout or other structural aspects of the cell array. Further, the trenches may be terminated at a shallower depth within in the epitaxial layer, or alternatively extended to terminate at the substrate. Also, the p strips along the trench sidewalls may be insulated from the top electrode so that they float. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claim, along with their full scope of equivalents.