Patent Publication Number: US-7213142-B2

Title: System and method to initialize registers with an EEPROM stored boot sequence

Description:
BACKGROUND 
   1. Technical Field 
   Embodiments of the invention relate to the field of initialization of ASICs, and more specifically to initializing registers with an EEPROM stored boot sequence. 
   2. Background Information and Description of Related Art 
   Complex Application Specific Integrated Circuits (ASICs) have a large number of configuration registers. These registers perform a variety of functions, such as device identification, feature enumeration, configuration of device operation, or communication of interrupts. Following system reset, there must be a process to initialize these registers. 
   One way to initialize these registers is to come up in a default state after power up and use software to program the ASIC. Another way is to use hardware to initialize the ASIC. However, current hardware solutions are inflexible, since the hardware stores dedicated information in fixed locations that only allow the hardware to initialize a limited number of predefined registers. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     The invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings: 
       FIG. 1  is a block diagram illustrating one generalized embodiment of a system incorporating the invention. 
       FIG. 2  is a flow diagram illustrating a method according to an embodiment of the invention. 
       FIG. 3  is a block diagram illustrating a suitable computing environment in which certain aspects of the illustrated invention may be practiced. 
   

   DETAILED DESCRIPTION 
   Embodiments of a system and method to initialize registers with an EEPROM stored boot sequence are described. In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description. 
   Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. 
   Referring to  FIG. 1 , a block diagram illustrates a system  100  according to one embodiment of the invention. Those of ordinary skill in the art will appreciate that the system  100  may include more components than those shown in  FIG. 1 . However, it is not necessary that all of these generally conventional components be shown in order to disclose an illustrative embodiment for practicing the invention. 
   System  100  includes an electrically erasable programmable read-only memory (EEPROM)  104  coupled to an application specific integrated circuit (ASIC)  102 . The ASIC  102  includes an EEPROM controller  106  and a bus controller  108 . The bus controller  108  controls the activity on bus  114 . Upon system reset, the EEPROM controller  106  reads the configuration records of the EEPROM  104 . The configuration records are processed to determine which registers are to be initialized with the specified data. The configuration records are translated to write requests. The target registers, such as  120 ,  122 , or  124 , are accessed via the bus  114  and the specified data is written to the registers. In this way, any register in the ASIC may be initialized via the configuration records of the EEPROM. In one embodiment, register accesses by a processor  110  and other masters  112  are prevented during the initialization of the registers. This may be done by a multiplexor (MUX), such as  118 , controlled by the bus controller  108 . 
   The following is an example of a configuration record format according to one embodiment of the invention. 
                                   Command   Space   Length                      Address 1   Address 0           Address 2   Address 2           Data Byte 1   Data Byte 0           Data Byte 3   Data Byte 2                    
After system reset, the configuration records are read. The command field in the configuration record indicates the next action to be taken. For example, an end command may be used to indicate that no further configuration records are to be processed. A jump command may be used to indicate that the next configuration record to be processed is at a specified address. A write command may be used to indicate that the specified data is to be written to specified target registers. The target registers are specified by the address space and address fields, and the data to be written to the target registers is specified by the data fields. The length field specifies the length of the data, such as the number of bytes, to be written to the specified register address.
 
     FIG. 2  illustrates a process of register initialization upon system reset according to one embodiment of the invention. Upon system reset, the process starts at  202 , where the address of the first configuration record is loaded. Then, at  204 , the record header is read. The record header contains information such as the command, the address space, and the length. At  206 , the address field of the record is read. At  208 , the command field is checked to determine what action to take next. For example, if the command is an end or reserved/undefined command, the process is finished and no further configuration records are processed. If the command is a jump, then a new record is read from the specified address in the address field, and the process starts again from  202 . If the command is a write, then at  210 , the data in the record is read. At  212 , the data is written to the specified address space and address via the bus. In one embodiment, data is read from the record and written to the target address until the specified length has been satisfied. In one embodiment, if the command is a sequential write, the target address may be incremented after each write to the bus. After the configuration record is finished processing, the next configuration record is read from the next sequential EEPROM address, and the process is repeated from  204 . 
   In one embodiment, other masters, such as the processor, may be blocked from accessing the registers until the configuration records are finished processed. This may be done using a MUX controlled by the bus controller. 
   In one embodiment, some configuration registers may be read-only to masters, such as the processor, but may be written to by the EEPROM controller during initialization. This may be implemented by having writes initiated by the EEPROM controller contain a different value in the write requests than writes initiated by other masters, such as the processor. For example, writes initiated by the EEPROM controller may have a “01” in the two least significant address bits, while writes from the other masters have a “00” in the two least significant address bits. In this way, write requests from the EEPROM controller and write requests from other masters may be differentiated. The EEPROM controller may then be allowed to have read/write access to the registers during initialization upon system reset, while other masters have read only access to the same registers. 
     FIG. 3  is a block diagram illustrating a suitable computing environment in which certain aspects of the invention may be practiced. A computer system  300  has components  302 – 314 , including a processor  302 , a memory  304 , an Input/Output device  306 , a data storage  312 , a network interface  310 , and a display device  314 , coupled to each other via a bus  308 . In one embodiment, memory  304  may include a dynamic random access memory device (DRAM). The components perform their conventional functions known in the art and provide means for implementing the system  100 . Collectively, these components represent a broad category of hardware systems, including but not limited to general purpose computer systems and specialized packet forwarding devices. It is to be appreciated that various components of computer system  300  may be rearranged, and that certain implementations of embodiments of the invention may not require nor include all of the above components. Furthermore, additional components may be included in system  300 , such as additional processors (e.g., a digital signal processor), storage devices, memories, and network or communication interfaces. 
   As will be appreciated by those skilled in the art, the content for implementing an embodiment of the method of the invention, for example, computer program instructions, may be provided by any machine-readable media which can store data that is accessible by system  100 , as part of or in addition to memory, including but not limited to cartridges, magnetic cassettes, flash memory cards, digital video disks, random access memories (RAMs), read-only memories (ROMs), and the like. In this regard, the system  100  is equipped to communicate with such machine-readable media in a manner well-known in the art. 
   It will be further appreciated by those skilled in the art that the content for implementing an embodiment of the method of the invention may be provided to the system  100  from any external device capable of storing the content and communicating the content to the system  100 . For example, in one embodiment of the invention, the system  100  may be connected to a network, and the content may be stored on any device in the network. 
   While the invention has been described in terms of several embodiments, those of ordinary skill in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.