Patent Publication Number: US-9885754-B2

Title: Integrated circuit with self-verification function, verification method and method for generating a BIST signature adjustment code

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to an integrated circuit, and more particularly, to an integrated circuit with a Built-In Self-Test circuit and associated verification method. 
     2. Description of the Prior Art 
     In general, a Built-In Self-Test circuit, so called BIST circuit hereinafter, is usually disposed in a chip which needs Read Only Memory (ROM), and this BIST circuit usually can use Single Input Signature Register (SISR) algorithm or Multiple Input Signature Register (MISR) algorithm. The purpose of the BIST circuit is testing product or reading and operating all the data of the ROM to generate a signature pattern when the data of ROM needs to be decided if it is correct and comparing this signature pattern with a predetermined signature pattern to decide if the data stored in ROM has error; wherein the predetermined signature pattern is the signature pattern produced by the BIST circuit when the data of ROM has no error. More specifically, because when the data of ROM has error, it has very high probability to reflect on the signature pattern of the BIST circuit. Therefore, as long as the signature pattern generated by the BIST circuit is the same with the predetermined signature pattern, it can decide the data of the ROM has no error; otherwise, when the signature pattern generated by the BIST circuit and the predetermined signature pattern are different, that means the data of ROM has error. 
     The above-mentioned predetermined signature pattern will be considered to dispose on chip or off chip according to the consideration of design of designer. In general test of factory mass production, the predetermined signature pattern is disposed off chip, but the predetermined signature pattern is stored in the chip of the electronic product for some electronic products which need to execute BIST when every time turns on (for example, the chip that BIST circuit in). For these electronic products which need to execute BIST when every time turns on, when the internal ROM needs to change the stored signature pattern or other data, it makes the signature pattern generated by the BIST circuit after reading the ROM change as well. Therefore, the predetermined signature pattern stored in the chip needs to be changed correspondingly, so it needs to spend extra costs of mask and also needs extra test for testing if the timing and function of circuit is correct after the design of mask changed. 
     SUMMARY OF THE INVENTION 
     One object of the present invention is to provide an integrated circuit and associated method, which doesn&#39;t need to change the predetermined signature pattern when the code or other data stored in the ROM need to be changed, to save the costs of mask and following costs of testing. 
     According to an embodiment of the present invention, an integrated circuit comprises a BIST circuit, a predetermined signature pattern and a ROM, wherein the predetermined signature pattern is stored in the integrated circuit previously, the ROM stores at least one information and one BIST signature adjustment code, the BIST signature adjustment code is irrelevant to any functional information stored in the ROM; wherein the BIST circuit is arranged to test the content stored in the ROM and generate a signature pattern, and compare the signature pattern with the predetermined signature pattern to decide if the information stored in the ROM has error. 
     According to another embodiment of the present invention, a verification method comprises: providing a ROM which stores at least one information and one BIST signature adjustment code, wherein the BIST signature adjustment code is irrelevant to any functional information stored in the ROM; and executing BIST to the content stored in the ROM to generate a signature pattern, and comparing the signature pattern with a predetermined signature pattern to decide if the content stored in the ROM has error. 
     According to another embodiment of the present invention, disclosing a method for generating a BIST signature adjustment code, the method is executed after a processor executed a code, wherein the BIST signature adjustment code is stored in a ROM, and the method comprising: acquiring the signature pattern corresponding to the BIST signature adjustment code according to a predetermined signature pattern and the signature pattern corresponding to the information of the ROM, wherein the signature pattern corresponding to the BIST signature adjustment code is N bits; using a BIST circuit to test N sets of digital code respectively to generate N sets of signature pattern, wherein each set of digital code comprises N bits, wherein in the Kth set of digital code, only the Kth bit is “1” and the rest of bits are all “0”, K is any number between 1 to N; multiplying N sets of signature pattern by corresponding variable respectively, then adding each other to acquire a calculation result; setting the calculation result equal to the signature pattern of the BIST signature adjustment code to obtain N equations with N variables; and solving the N variables according to the N equations with N variables, wherein the N variables are used to be the BIST signature adjustment code. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating an integrated circuit with self-verification function. 
         FIG. 2  is a diagram illustrating the signature patterns generated by two versions of chips. 
         FIG. 3  is a flowchart illustrating the verification method according to an embodiment of the present invention. 
         FIG. 4  is a flowchart illustrating a method for generating the BIST signature adjustment code according to an embodiment of the present invention. 
         FIG. 5  is a diagram illustrating the computer readable media according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should not be interpreted as a close-ended term such as “consist of”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
     Refer to  FIG. 1 , which is a diagram illustrating an integrated circuit  100  with self-verification function. As shown in  FIG. 1 , the integrated circuit  100  comprises a BIST circuit  110  and a ROM  120 , wherein the BIST circuit  110  comprises a core circuit  112 , a comparing unit  114  and a predetermined signature pattern  116 , and the ROM  120  comprises effective information  122  and a BIST signature adjustment code  124 . In this embodiment, the integrated circuit  100  can be applied in the electronic product which needs to execute BIST when every time turns on to assure that the content of the ROM  120  is correct, particularly can be applied in the electronic product which needs higher availability or correctness, for example the vehicular computer, etc. 
     In the BIST circuit  110 , the core circuit  112  can use SISR algorithm circuit or MISR algorithm circuit, which the main function is reading every bit of the ROM  120  and generating a signature pattern accordingly, wherein the signature pattern can be composed of a plurality of digital value “0” and “1”. The comparing unit  114  is arranged to compare the signature pattern generated by the core circuit  112  with a predetermined signature pattern  116  to decide if the data stored in the ROM  120  is correct then report the result to the following related circuit. More specifically, if the signature pattern generated by the core circuit  112  and the predetermined signature pattern  116  are identical, that means the data stored in the ROM  120  is correct; and if the signature pattern generated by the core circuit  112  and the predetermined signature pattern  116  are different, that means the data stored in the ROM  120  has error. In addition, in  FIG. 1 , the predetermined signature pattern  116  is stored in a storage unit of the BIST circuit  110 , but in other embodiments, the predetermined signature pattern  116  can also be stored in the storage unit of other chips. 
     In this embodiment, the BIST circuit  110  executes the above-mentioned operations to decide if the content stored in the ROM  120  is correct when every time the applied electronic product turns on (for example, when every time a laptop turns on). 
     In the ROM  120 , the effective information  122  can be any functional program instruction (program code), data, parameter or any meaningful content, etc. which stored in the ROM  120 . The BIST signature adjustment code  124  is functionally irrelevant to any content of the information  122 . More specifically, the BIST signature adjustment code  124  is just read and executed the related operations by the BIST circuit  110  to generate signature pattern instead of reading by other circuits to execute any substantial functional operation; in other words, even there is a circuit reads the BIST signature adjustment code  124 , it won&#39;t execute any functional operation just because the BIST signature adjustment code  124 . 
     The number of bits of the BIST signature adjustment code  124  is bigger than or equal to the number of bits of the signature pattern generated by the core circuit  112 . For example, if the signature pattern generated by the core circuit  112  is 24 bits, the BIST signature adjustment code  124  is 24 bits or even more. In addition, in this embodiment, the BIST signature adjustment code  124  can be stored in the consecutive address of the ROM  120 ; however, in other embodiments, at least two portions of the BIST signature adjustment code  124  are stored in discontinuous addresses of the ROM  120  respectively. 
     In this embodiment, if the ROM  120  has an unused area, that is the area different from the effective information  122  and the BIST signature adjustment code  124 , the bits of the area will be set to “0”. 
     The purpose of disposing the BIST signature adjustment code  124  in the ROM  120  of the present invention is making the signature pattern generated by the core circuit  112  the same as the signature pattern of the previous version of chip, wherein most of the content of the previous version of chip are similar with the integrated circuit  100  in  FIG. 1 . The main difference is the content stored in the ROM. Therefore, it can avoid adjusting the architecture of the BIST circuit  110  dramatically (i.e. the predetermined signature pattern  116  doesn&#39;t need to change). More specifically, refer to  FIG. 2 , assume in the previous version of chip, the ROM  220  stores the information  222 , and the signature pattern generated by the BIST circuit after reading the content of the ROM  220  is SIG d ; however, in the integrated circuit  100  in this embodiment, the signature pattern generated by the BIST circuit after reading the content of the ROM  220  is also SIG d , wherein SIG 1  in  FIG. 2  corresponds to the signature pattern of the effective information  122 , and SIG 2  corresponds to the signature pattern of the BIST signature adjustment code  124 . As shown in  FIG. 2 , because the signature pattern generated by the integrated circuit  100  and the signature pattern generated by the previous version of chip are identical, that also means the stored predetermined signature patterns are the same too. Therefore, when designing the BIST circuit  110 , the design of the previous version of chip can be used, particularly, the predetermined signature pattern  116  part doesn&#39;t need to be changed, so it can reduce the masks which need to redesign, and save the following costs of testing further. 
     Refer to  FIG. 3 , which is a flowchart illustrating the verification method according to an embodiment of the present invention, and refer to the disclosed content in  FIG. 1  and  FIG. 2 , the flow of the verification method of the present invention is described as follows: 
     Step  300 : the flow starts. 
     Step  302 : provide a ROM, which stores at least effective information and a BIST signature adjustment code, wherein the BIST signature adjustment code is irrelevant to any functional information stored in the ROM. 
     Step  304 : execute Built-In Self-Test to the content stored in the ROM to generate a signature pattern, and compare the signature pattern with a predetermined signature pattern to determine if the content stored in the ROM has error. 
     On the other hand, for deciding the content of the BIST signature adjustment code  124 , because the number of bits of the signature pattern generated by the core circuit  112  is higher therefore using traditional exhaustive attack method spends too much time, so it&#39;s not suitable for deciding the BIST signature adjustment code  124 . Therefore, the present invention provides a method that can find the BIST signature adjustment code  124  fast and correctly as following. 
     First, assume the BIST signature adjustment code  124  has N bits, wherein N is the number of bits of the signature pattern generated by the core circuit  112 , and the N bits of the BIST signature adjustment code  124  are (r n-1 , r n-2 , r n-3 , . . . , r 1 , r 0 ) respectively. In addition, refer to  FIG. 2 , because the signature pattern SIG d  corresponding to the effective information  222  and the signature pattern SIG 1  corresponding to the effective information  122  are both known, so the signature pattern SIG 2  corresponding to the BIST signature adjustment code  124  equals to (SIG d -SIG 1 ). As the above statements, assume f( ) means the function executed by the core circuit  112  for generating the signature pattern, then f(r n-1 , r n-2 , r n-3 , . . . , r 1 , r 0 )=(SIG d −SIG 1 ). 
     The above-mentioned (r n-1 , r n-2 , r n-3 , . . . , r 1 , r 0 ) can be represented as r n-1 *(1000 . . . 000)+r n-2 *(0100 . . . 000)+r n-3 *(0010 . . . 000)+ . . . +r 1 *(0000 . . . 010)+r 0 *(0000 . . . 001) further, and the algorithm used by the core circuit  112  for generating the signature pattern is linear. Therefore, f(r n-1 , r n-2 , r n-3 , . . . , r 1 , r 0 )=r n-1 *f(1000 . . . 000)+r n-2 *f(0100 . . . 000)+r n-3 *f(0010 . . . 000)+ . . . +r 1 *f(0000 . . . 010)+r 0 *f(0000 . . . 001)=(SIG d −SIG 1 ), so N equations with N variables can be acquired in this time (each bit value corresponds to an equation, and there are (r n-1 , r n-2 , r n-3 , . . . , r 1 , r 0 ) N variables in total, if f(1000 . . . 000), f(0100 . . . 000), f(0010 . . . 000), . . . , and f (0000 . . . 001) are linear independent to each other, then each value of (r n-1 , r n-2 , r n-3 , . . . , r 1 , r 0 ) can be solved via solving the simultaneous equation, which means the BIST signature adjustment code  124  is determined). 
     In addition, if f(1000 . . . 000), f(0100 . . . 000), f(0010 . . . 000), and f (0000 . . . 001) are not linear independent to each other, and can&#39;t decide each value of (r n-1 , r n-2 , r n-3 , . . . , r 1 , r 0 ), then the BIST signature adjustment code  124  can be assumed to have (N+1) bits and repeat the above-mentioned steps to acquire N equations with (N+1) variables to decide the (N+1) variables as the BIST signature adjustment code  124 ; next, if the variables still can&#39;t be decided, then assume the BIST signature adjustment code  124  has (N+2) bits continuously, and repeat the above-mentioned steps until the BIST signature adjustment code  124  is determined. 
     Refer to the above disclosed content, the flowchart for generating the BIST signature adjustment code  124  stored in the ROM  120  is described in  FIG. 4 , which comprises the following steps: 
     Step  400 : the flow starts. 
     Step  402 : acquire the signature pattern corresponding to the BIST signature adjustment code according to a predetermined signature pattern and the signature pattern corresponding to the effective information of the ROM; 
     Step  404 : use a BIST circuit to test N sets of digital code respectively to generate N sets of signature pattern respectively, wherein each set of digital code comprises N bits, wherein in the Kth set of digital code, only the Kth bit is “1” and the rest of bits are all “0”, K is any number between 1 to N; 
     Step  406 : multiply N sets of signature pattern by the corresponding variable then add each other to acquire a calculation result; 
     Step  408 : set the calculation result equal to the signature pattern of the BIST signature adjustment code to acquire N equations with N variables; and 
     Step  410 : solve the N variables according to the N equations with N variables, wherein the N variables are used to be the BIST signature adjustment code. 
     The flow shown in  FIG. 4  can be executed by a computer program of a computer readable media, more specifically, refer to  FIG. 5 , a host computer  500  comprises at least a processor  510  and a computer readable media  520 , wherein the computer readable media  520  can be a hard drive or other storage device, and the computer readable media  520  stores a computer program  522 . The host computer  500  executes the steps in  FIG. 4  when the processor  510  is executing the computer program  522 . 
     In the integrated circuit and the verification method disclosed in the present invention, it makes the signature pattern generated by the BIST circuit when reading the ROM identical with the signature pattern of the previous version of chip via a BIST signature adjustment code stored in the ROM, therefore it can avoid adjusting the predetermined signature pattern part. Moreover, the present invention further discloses a method for deciding the BIST signature adjustment code, which can decide the suitable BIST signature adjustment code fast and correctly. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.