Patent Publication Number: US-7719386-B2

Title: Phase shifter having components which suppress fluctuations in the phase shifter pass characteristics

Description:
REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of the priority of Japanese patent application No. 2006-297296, filed on Nov. 1, 2006, the disclosure of which is incorporated herein in its entirety by reference thereto. 
     FIELD OF THE INVENTION 
     The present invention relates to a phase shifter, and particularly to a filter switching-over type phase shifter for use in microwave band. 
     BACKGROUND OF THE INVENTION 
     The filter switching-over type phase shifter is usually made up by a high-pass filter (HPF) for producing the phase lead of the signal phase, a low-pass filter for producing the phase lag of the signal phase (LPF), and single pole double throw switches (SPDT switches) for switching-over between the high-pass and low-pass filter units. The amount of phase shift is created by the phase difference produced on switching-over between these two types of the filter units. 
     The configuration of this filter switching-over type phase shifter will now be described.  FIG. 9  is a circuit diagram showing a basic configuration of a filter switching-over type phase shifter of a type described in Patent Document 1. A high-pass filter (HPF)  112  is made up by two capacitors C 111  and C 112 , connected in series with a signal line, and an inductor L 111 , connected from a junction of the two capacitors C 111  and C 112  to the ground. A low-pass filter (LPF)  113  is made up by two inductors L 112  and L 113 , connected in series with a signal line, and a capacitor C 113 , connected from the junction of the two inductors L 112  and L 113  to the ground. The high-pass filter  112  and the low-pass filter  113  are connected via a single pole double throw switch (SPDTSW)  110  to an input terminal IN, while being connected via a single pole double throw switch (SPDTSW)  110  to an output terminal OUT. 
     The operation of the phase shifter, constructed as described above, will now be explained. If, when a signal from the input terminal IN to the output terminal OUT is passed through the high-pass filter  112 , a bias, not shown, operating for turning an FET (field-effect transistor) Q 101  on, is applied to the gates of FETs (field-effect transistors) Q 101  and Q 103 , the source-drain resistance is lowered to establish a practically short-circuited state, and hence the signal is allowed to pass through the high-pass filter  112 . 
     Meanwhile, a bias voltage, not shown, which turns off the FET, is applied to the gates of FETs Q 105  and Q 107 , in order to inhibit the signal flowing to the low-pass filter  113 , thereby increasing the source-drain resistance of the FETs Q 105  and Q 107 . 
     On the other hand, when the low-pass filter  113  is turned on, the signal is allowed to flow to the low-pass filter  113  by applying the bias which is the reverse of that described above to the gates of the FETs of the single pole double throw switches  110  and  111 . 
     In this manner, the single pole double throw switches  110  and  111  are changed (switched) over so that signals will flow through the high-pass filter  112  or the low-pass filter  113 . The input signal will be delayed by the inductors L 112  and L 113 , connected in series with the low-pass filter  113 , when the signal is passed through the low-pass filter  113 , while the input signal will lead (advance) by the capacitors Cl 11  and C 112 , connected in series with the high-pass filter  112 . Hence, the phase difference of the signal is produced by changing over the filter units by the single pole double throw switches  110  and  111 . It is noted that, for realizing a desired phase shift value, the values of the components in the respective filter units need to be changed to optimum values. 
     [Patent Document 1] 
     Japanese Patent Kokai Publication No. JP-P2006-19823A ( FIG. 3 ) 
     SUMMARY OF THE INVENTION 
     The following analyses are given by the present invention. The entire disclosure of Patent Documents 1 is incorporated herein by reference thereto. 
     Meanwhile, with the high frequency band, such as the GHz band, the signal leaks via the FETs that are turned off, depending on the off-capacitance of the FETs of the single pole double throw switches. As a solution, inductors are connected in parallel with the FETs. In other words, inductors L 121 , L 123 , L 122 , and L 124  are connected in parallel with the FETs Q 101 , Q 103 , Q 105 , and Q 107 , respectively. By connecting the inductors in parallel with the FETs, a parallel resonance circuit in a desired band is formed by the off-capacitance of the FETs that are turned off and the inductance of the inductors. This parallel resonance circuit puts an off-state switch in a high-impedance state, thereby improving the cut-off characteristics. As a result, the pass characteristics of the on-state switch will also improve. 
     However, according to the present invention, it has been discovered that, depending upon the conditions, the square error of the phase shift amount versus frequency deteriorates in the conventional phase shifter. In other words, the desirable pass characteristics of the high-pass filter cannot always be obtained. Therefore, the following analysis regarding the impedance characteristics of the switch that is turned off on the low-pass filter side has been performed. 
     The FETs can be approximated by resistance when they are turned on, and by capacitance when they are off.  FIG. 10  shows an equivalent circuit of the phase shifter in which the FETs on the high-pass filter side are turned on and the FETs on the low-pass filter side are turned off.  FIG. 10  includes input terminal IN and output terminal OUT and single pole double throw switches  110  and  111 .  FIG. 10  also includes a high-pass filter (HPF)  112  having two capacitors (capacitance C 2 , each) connected in series and an inductor (inductance L 2 ) connected to the junction (node) of the two capacitors is provided between a pair of on-state switches, each being comprised of a resistance R 1  equivalently representing the on-state FET, and inductor (inductance L 1 ) connected in parallel with the resistance R 1 . Further, a low-pass filter (LPF)  113  having two inductors (inductance L 3 , each) connected in series and a capacitor (capacitance C 3 ) connected to the junction (node) of the two inductors is provided between a pair of off-state switches, each being comprised of capacitors (capacitance Cl) equivalently representing the off-state FET, and inductors (the inductance L 1 ) connected in parallel with the capacitors. 
     Next, an impedance Z, looking from the input or output side to the low-pass filter side, is calculated. Since the phase shifter is configured symmetrically about the filters, C 3  may be regarded as an equivalent of two capacitors with C 3 /2 capacitance shunt-connected in parallel. Further, since it is enough that only one side of the symmetry axis may be taken into consideration, and the other side may be ignored, the impedance calculation can be simplified. The impedance Z in the equivalent circuit in  FIG. 10  can be represented by an equivalent circuit shown in  FIG. 11 .  FIG. 11  includes capacitors C 1  and C 3 /2 and inductors L 1  and L 3 . 
     Here, the impedance Z with respect to frequency ω is represented as follows. 
     
       
         
           
             Z 
             = 
             
               j 
               ( 
               
                 
                   
                     ω 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       L 
                       1 
                     
                   
                   
                     1 
                     - 
                     
                       
                         ω 
                         2 
                       
                       ⁢ 
                       
                         L 
                         1 
                       
                       ⁢ 
                       
                         C 
                         1 
                       
                     
                   
                 
                 + 
                 
                   ω 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     L 
                     3 
                   
                 
                 - 
                 
                   2 
                   
                     ω 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       C 
                       3 
                     
                   
                 
               
               ) 
             
           
         
       
       
         
           
             Therefore 
             , 
             
               
 
             
             ⁢ 
             
               
                  
                 Z 
                  
               
               = 
               
                 
                   
                     ω 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       L 
                       1 
                     
                   
                   
                     1 
                     - 
                     
                       
                         ω 
                         2 
                       
                       ⁢ 
                       
                         L 
                         1 
                       
                       ⁢ 
                       
                         C 
                         1 
                       
                     
                   
                 
                 + 
                 
                   ω 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     L 
                     3 
                   
                 
                 - 
                 
                   2 
                   
                     ω 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       C 
                       3 
                     
                   
                 
               
             
           
         
       
     
     Further, the resonance frequency ω 0  in the parallel resonance circuit in which L 1  and C 1  are connected in parallel is represented by 
     
       
         
           
             
               ω 
               0 
             
             = 
             
               
                 1 
                 
                   
                     L 
                     1 
                   
                   ⁢ 
                   
                     C 
                     1 
                   
                 
               
             
           
         
       
       
         
           and 
         
       
       
         
           
             
               C 
               1 
             
             = 
             
               1 
               
                 
                   ω 
                   0 
                   2 
                 
                 ⁢ 
                 
                   L 
                   1 
                 
               
             
           
         
       
     
     Next, C 1  is substituted into the equation |Z|, and |Z| is derived by numerical calculation. The frequency response of |Z| is shown in  FIG. 12 . Here, f 0 =10 GHz (=ω 0 /2π), L 1 =1 nH; L 3 =0.03 nH; C 3 =0.2 pF. As shown in  FIG. 12 , |Z| becomes 0 ohms (short-circuited) at a frequency of 8.46 GHz. 
     The off-state side, i.e., the low-pass filter side, should have a high impedance, however, depending on the frequency, a short circuit occurs as described. As a result, the pass characteristics (curve) of the high-pass filter side will deteriorate, and the phase shift curve will fluctuates by small peaks (positive and/or negative, i.e., recess) caused by unnecessary resonances, causing the square error of the phase shift amount versus frequency to deteriorate. 
     In order to solve the problem of the deterioration of the pass characteristics caused by the short-circuit in the resonance circuit described above, the present inventor has conceived that the decrease in impedance can be prevented by adding resistance to the inductor in series thereby decreasing the Q factor of the resonance circuit at resonance. In other words, the present inventor has come to a concept that desirable pass characteristics can be obtained by providing (adding) appropriate resistance value to the inductor, and achieved the present invention. 
     According to an aspect of the present invention, there is provided a phase shifter that selectively switches between a low-pass filter and a high-pass filter using first and second single pole double throw switches provided on input and output sides respectively and operatively linked to each other; wherein the first and second single pole double throw switches include a first switch device that connects a single pole side junction node and the low-pass filter, a first inductance circuit connected in parallel with the first switch device, a second switch device that connects the single pole side junction node and the high-pass filter and that performs an ON/OFF operation exclusively from the first switch device, and a second inductance circuit connected in parallel with the second switch device; provided that the first inductance circuit is constituted by a serially-connected circuit of an inductor and a resistor. 
     The inductance of the inductor, the resistance of the resistor and the capacitance of the first switch device in the off state in the first inductance circuit are selected so as to suppress/avoid fluctuation, deterioration in the pass characteristics of the phase shifter. 
     The meritorious effects of the present invention are summarized as follows. 
     According to the present invention, by adding resistance to an inductor in a switch device and an inductance circuit connected to a low-pass filter, occurrence of a short-circuit can be prevented in a resonance circuit formed by the inductance circuit and the capacitance of the switch device in an off state. As a result, the deterioration of the phase characteristics and amplitude characteristics in the pass characteristics can be prevented. 
    
    
     
       BRIEF DESCRIPTIONS OF THE DRAWINGS 
         FIG. 1  is a circuit diagram showing the configuration of a phase shifter relating to an example of the present invention. 
         FIG. 2  is an equivalent circuit diagram of the phase shifter relating to the example of the present invention. 
         FIGS. 3A and 3B  are equivalent circuit diagrams of the impedance looking from the input or output side to the low-pass filter side in the phase shifter relating to the example of the present invention. 
         FIG. 4  is a graph showing the frequency response of S 21  in magnitude when the high-pass filter side is turned on. 
         FIG. 5  is a graph showing the frequency response of S 21  in phase angle when the high-pass filter side is turned on. 
         FIG. 6  is a graph showing the frequency response of S 21  in magnitude when the low-pass filter side is turned on. 
         FIG. 7  is a graph showing the frequency response of S 21  in phase angle when the low-pass filter side is turned on. 
         FIG. 8  is a graph showing the frequency response of the phase difference obtained by subtracting the phase when the low-pass filter side is turned on from the phase when the high-pass filter side is turned on. 
         FIG. 9  is a circuit diagram showing the configuration of a conventional phase shifter. 
         FIG. 10  is an equivalent circuit diagram of the conventional phase shifter. 
         FIG. 11  is an equivalent circuit diagram of the impedance looking from the input or output side to the low-pass filter side. 
         FIG. 12  is a drawing showing the frequency response of an impedance |Z|. 
     
    
    
     PREFERRED MODES OF THE INVENTION 
     A phase shifter relating to an example of the present invention selectively switches between a low-pass filter (LPF  13  in  FIG. 1 ) and a high-pass filter (HPF  12  in  FIG. 1 ) using first and second single pole double throw switches ( 10   a  and  10   b  in  FIG. 1 ) provided on the input and output sides respectively and operatively linked to each other. The first and second single pole double throw switches include first switch device (Q 1   c  and Q 1   d  in  FIG. 1 ) that connects the single pole side junction nodes and the low-pass filter, first inductance circuits (L 1   c  and R 2   c , and L 1   d  and R 2   d  in  FIG. 1 ) each connected in parallel with the first switch device, second switch devices (Q 1   a  and Q 1   b  in  FIG. 1 ) that connect the single pole side junction nodes and the high-pass filter and that perform an ON/OFF operation exclusively from the first switch devices, and second inductance circuits (L 1   a  and R 2   a , and L 1   b  and R 2   b  in  FIG. 1 ) each connected in parallel with the second switch device. Each first inductance circuit is comprised of an inductor and resistor connected in series. 
     In the first inductance circuit, when the inductance of the inductor is L, the resistance of the resistor is R, and the capacitance of the first switch device in an off state is C, it is preferable that R be larger than 0 and smaller than (L/C) 1/2 . 
     The resistance may be the parasitic resistance of the inductor. Further, the inductor and the resistor may be made up of a material having an electrical resistivity higher than that of gold. Further, the inductor may be made up of a material having an electrical resistivity equal to or lower than that of gold. It is preferable that the switch devices be constituted by field-effect transistors. 
     In the phase shifter configured as described, the switch device and the inductance circuit are connected in parallel, and when the switch device is turned off, a resonance circuit is formed by the inductance circuit and the capacitance of the turned off switch device. In this case, in the inductance circuit connected in parallel with the switch device connected to the low-pass filter, formation of a short-circuit can be prevented in the resonance circuit by adding the resistor to the inductor in series. As a result, the cut-off performance of the switch device when it is turned off will improve. Therefore, the influence of the impedance on the off-state low-pass filter side on the pass characteristics of the on-state high-pass filter can be reduced, and the insertion loss versus frequency and the fluctuations in the phase shift amount can be minimized. 
     EXAMPLE 1 
       FIG. 1  is a circuit diagram showing the configuration of a phase shifter relating to an example of the present invention. In  FIG. 1 , the phase shifter comprises inductors L 1   a , L 1   b , L 1   c , L 1   d , L 2 , L 3   a , and L 3   b , capacitors C 2   a , C 2   b , and C 3 , FETs Q 1   a , Q 1   b , Q 1   c , and Q 1   d , resistors R 2   a , R 2   b , R 2   c , and R 2   d , an input terminal IN, and an output terminal OUT. The phase shifter shown in  FIG. 1  is different from the one shown in  FIG. 9  in that the resistors R 2   a , R 2   b , R 2   c , and R 2   d  are connected in series with the inductors L 1   a , L 1   b , L 1   c , and L 1   d  respectively, and they are further connected in parallel with each of the FETs, respectively. Otherwise, the configuration is identical. Therefore, the inductors connected in parallel with the switch devices will be described in detail, and the explanation of the other components will be omitted since they are identical to those in the conventional example. Here, the resistors R 2   a , R 2   b , R 2   c , and R 2   d  represent resistance elements connected in series with each of the inductors or the parasitic resistance of any one of the inductors. Note that, in the case where resistance elements are inserted, the resistors represent resistance elements including the parasitic resistance of the inductors. 
       FIG. 2  is an equivalent circuit diagram when the FETs Q 1   a  and Q 1   b  are turned on and the FETs Q 1   c  and Q 1   d  are turned off in  FIG. 1 . In other words, an equivalent circuit diagram when the high-pass filter (HPF)  12  has pass characteristics is shown. A resistor R 1  represents the on-state of the FETs and a capacitor C 1  represents the off-state of the FETs. R 2  represents the parasitic resistance of the inductors of the switch devices. Here, symbols attached to the components in  FIG. 2  represent the component values. The circuit of  FIG. 2  includes input terminal IN and output terminal OUT connected to a first single pole double throw switch device  10   a  and a second single pole double throw switch device lO b , which include inductance circuits including an inductance L 1  and a resistance R 2 . High-pass filter (HPF)  12  includes capacitors C 2  and inductor L 2 . Low-pass filter (LPF)  13  includes inductors L 3  and capacitor C 3 . 
     Here, an impedance Z looking from the input or output side to the low-pass filter side is represented by an equivalent circuit diagram shown in  FIG. 3A  and by the following equation. Capacitance C 3 /2 represents the capacitance C 3  divided by two. Note that the approximation is performed assuming that R 2  is small. 
     
       
         
           
             Z 
             = 
             
               j 
               ( 
               
                 
                   
                     ω 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       L 
                       1 
                     
                   
                   
                     1 
                     - 
                     
                       
                         ω 
                         2 
                       
                       ⁢ 
                       
                         L 
                         1 
                       
                       ⁢ 
                       
                         C 
                         1 
                       
                     
                   
                 
                 + 
                 
                   ω 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     L 
                     3 
                   
                 
                 - 
                 
                   2 
                   
                     ω 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       C 
                       3 
                     
                   
                 
               
               ) 
             
           
         
       
       
         
           
             Therefore 
             , 
             
               
 
             
             ⁢ 
             
               
                  
                 Z 
                  
               
               = 
               
                 
                   
                     ω 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       L 
                       1 
                     
                   
                   
                     1 
                     - 
                     
                       
                         ω 
                         2 
                       
                       ⁢ 
                       
                         L 
                         1 
                       
                       ⁢ 
                       
                         C 
                         1 
                       
                     
                   
                 
                 + 
                 
                   ω 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     L 
                     3 
                   
                 
                 - 
                 
                   2 
                   
                     ω 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       C 
                       3 
                     
                   
                 
               
             
           
         
       
     
     Further, an admittance Y of the parallel resonance circuit is represented by an equivalent circuit diagram shown in  FIG. 3B  and by the following equation. 
     
       
         
           
             
               
                 
                   Y 
                   = 
                   
                     
                       1 
                       
                         
                           R 
                           2 
                         
                         + 
                         
                           jω 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             L 
                             1 
                           
                         
                       
                     
                     + 
                     
                       jω 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         C 
                         1 
                       
                     
                   
                 
               
             
             
               
                 
                   = 
                   
                     
                       
                         R 
                         2 
                       
                       
                         
                           R 
                           2 
                           2 
                         
                         + 
                         
                           
                             ω 
                             2 
                           
                           ⁢ 
                           
                             L 
                             1 
                             2 
                           
                         
                       
                     
                     + 
                     
                       jω 
                       ( 
                       
                         
                           C 
                           1 
                         
                         - 
                         
                           
                             L 
                             1 
                           
                           
                             
                               R 
                               2 
                               2 
                             
                             + 
                             
                               
                                 ω 
                                 2 
                               
                               ⁢ 
                               
                                 L 
                                 1 
                                 2 
                               
                             
                           
                         
                       
                       ) 
                     
                   
                 
               
             
           
         
       
     
     Since the circuit resonates when the imaginary part of Y is 0 in this admittance Y, the resonance frequency a)o is expressed as follows. 
               ω   0     =         1       L   1     ⁢     C   1         -       R   2   2       L   1   2                 
Here, the condition that makes ω 0  (f 0 ) constant is
 
     
       
         
           
             
               C 
               1 
             
             = 
             
               
                 L 
                 1 
               
               
                 
                   R 
                   2 
                   2 
                 
                 + 
                 
                   
                     ω 
                     0 
                     2 
                   
                   ⁢ 
                   
                     L 
                     1 
                     2 
                   
                 
               
             
           
         
       
     
     Next, imagining a practical use, component values are given to the equivalent circuit shown in  FIG. 2 , and analysis regarding characteristics obtained by a simulation will be explained. Here, R 1 =4 ohms; R 2 =2 ohms, 10 ohms, or 20 ohms; C 2 =0.7 pF; C 3 =0.2 pf; L 1 =1 nH; L 2 =0.6 nH; L 3 =0.15 nH. Further, the frequency band is from 8 GHz to 12 GHz, and the resonance frequency f 0  is 10 GHz. Further, as described, the equation of C 1    
               C   1     =       L   1             L   1   2     ⁡     (     2   ⁢   π   ⁢           ⁢     f   0       )       2     +     R   2   2               
has been corrected so that f 0  is constant even if R 2  changes.
 
     S parameter S 21 , which is the pass characteristics when the parasitic resistance R 2  of the inductors of the switch devices in each of  FIGS. 5-8  is 2 ohms, 10 ohms, and 20 ohms, is derived using a simulation.  FIG. 4  is a graph titled 90 deg. bit HPF ON, showing the frequency response of S 21  in magnitude vs. frequency when the high-pass filter side is turned on.  FIG. 5  is a graph titled 90 deg. bit HPF ON, showing the frequency response of S 21  in phase angle vs. frequency when the high-pass filter side is turned on.  FIG. 6  is a graph titled 90 deg. bit LPF ON, showing the frequency response of S 21  in magnitude vs. frequency when the low-pass filter side is turned on.  FIG. 7  is a graph titled 90 deg. bit LPF ON, showing the frequency response of S 21  in phase angle vs. frequency when the low-pass filter side is turned on.  FIG. 8  is a graph titled 90 deg. bit, showing the frequency response of the phase vs. frequency difference obtained by subtracting the phase when the low-pass filter side is turned on from the phase when the high-pass filter side is turned on. 
     Referring to  FIG. 4 , when R 2 =2 ohms, the magnitude of S 21  decreases greatly around 8.4 GHz. Further, the phase response in  FIG. 5  shows an increase caused by resonance around 8.4 GHz, and the phase-difference response in  FIG. 8  also shows positive and negative peaks around 8.4 GHz. On the other hand, by raising the parasitic resistance R 2  of the inductor(s) to 10 ohms and 20 ohms, such peaks can be eliminated or reduced. Further, the mean square error of the phase shift amount in a frequency band between 8 GHz and 12 GHz is 7.15 degrees when R 2 =2 ohms, however, it is improved to be 1.30 degrees when R 2 =10 ohms and 1.27 degrees when R 2 =20 ohms. 
     These positive and negative peaks in the characteristics caused by resonance occur when, with the high-pass filter side turned on, the impedance of the parts that should be in a high impedance state is reduced in the resonance circuit, on the low-pass filter side, constituted by three elements: the off-capacitance C 1  of the FET, the inductor L 1  of the switch device, and the capacitor C 3  of the low-pass filter. Therefore, by increasing the parasitic resistance R 2  of the inductor L 1 , a high impedance can be maintained even at 8.4 GHz. As a result, the fluctuations (occurrence of peaks) in the characteristic curves caused by resonance can be suppressed. 
     On the other hand, when the low-pass filter side is turned on, the characteristics of S 21  show smooth curves as shown in  FIGS. 6 and 7 , and turning off the high-pass filter side does not cause the decrease in impedance in the resonance circuit. 
     Next, a conductive material used for the inductors will be described. For a semiconductor device in a phase shifter for use in 1 GHz or higher, it is preferred that conductive materials having a higher resistivity than that of gold such as titanium nitride, tungsten silicide, platinum, and titanium be used for the inductors because larger resistance is needed. 
     In order to satisfy the conditions of the resistance in the inductance circuit as described, from the conditions for resonance to exist 
               ω   0     =           1       L   1     ⁢     C   1         -       R   2   2       L   1   2           ≥   0                   R   2     =         ρ   ⁢           ⁢     l   S       ≤         L   1       C   1           =     R   ⁢           ⁢     max   ⁢     
     (       ρ   ⁢     :     ⁢           ⁢   resistivity     ;     1   ⁢     :     ⁢           ⁢   the   ⁢           ⁢   length   ⁢           ⁢   of   ⁢           ⁢   the   ⁢           ⁢   wiring     ;     S   ⁢     :     ⁢           ⁢   the   ⁢           ⁢   sectional   ⁢           ⁢   area   ⁢           ⁢   of   ⁢           ⁢   the   ⁢           ⁢   wiring       )               
Therefore, from the following inequality,
 
             ρ   ≤       S   l     ⁢         L   1       C   1                 
as an upper limit of the resistivity of the material used for the inductors, the following equation must be satisfied.
 
     
       
         
           
             ρ 
             = 
             
               
                 S 
                 l 
               
               ⁢ 
               
                 
                   
                     L 
                     1 
                   
                   
                     C 
                     1 
                   
                 
               
             
           
         
       
     
     Now, imagining a practical use, for instance, when L 1 =1 nH; C 1 =80 fF; S=10 um (wiring width)×1 um (wiring thickness); and 1=400 um, the upper limit of the resistivity has to be defined by ρ=2.8×10 −4 Ωcm. Therefore, as the conductive material used for the inductors in the switch devices, conductive materials having a lower resistivity than this such as titanium nitride (ρ=1.6×10 −4 Ωcm), tungsten silicide (ρ=1.9×10 −4 Ωcm), platinum (ρ=1.4×10 −5 Ωcm), and titanium (ρ=7.0×10 −5 Ωcm) are preferred. 
     Note that the resistivity of gold is ρ=3.0×10 −6 Ωcm, and R 2  in the above equation will be 1.2 ohms. This means that, when the inductors are made up of gold, the resistance of the inductors is not sufficient to reduce the deterioration of the pass characteristics. Therefore, in the case where the inductors in the switch devices are made up of a low-resistivity material such as gold rather than a high-resistivity material, the decrease in impedance caused by resonance can be prevented by connecting a resistance element to the inductor in series thereby increasing the resistance. 
     The above explanation mainly refers to the switch on the input terminal side, however, the same applies to the switch on the output terminal side since the phase shifter is configured symmetrically with respect to the filters (HPF and LPF). 
     Further, the short-circuit caused by resonance does not occur in the inductance circuit connected in parallel with the switch connected to the high-pass filter side, and there is no deterioration of the characteristics such as the one shown in  FIGS. 6 and 7 . Therefore, it is not necessary to define a lower limit of the resistance in the inductance circuit, however, from the design standpoint, it is conventional to configure the switch device on the high-pass filter side identically to the one on the low-pass filter side. 
     It should be noted that other objects, features and aspects of the present invention will become apparent in the entire disclosure and that modifications may be done without departing the gist and scope of the present invention as disclosed herein and claimed as appended herewith. 
     Also it should be noted that any combination of the disclosed and/or claimed elements, matters and/or items may fall under the modifications aforementioned.