Patent Publication Number: US-2023163208-A1

Title: Bypassed gate transistors having improved stability

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation of U.S. patent application Ser. No. 16/907,983 filed Jun. 22, 2020, which claims priority as a continuation of U.S. patent application Ser. No. 16/182,642 filed Nov. 7, 2018, which claims priority under 35 U.S.C. § 120 as a divisional of U.S. patent application Ser. No. 15/587,830, filed May 5, 2017, which in turn claims priority under 35 U.S.C. § 120 as a continuation-in-part of U.S. patent application Ser. No. 15/073,201, filed Mar. 17, 2016, the entire content of each of which is incorporated by reference herein. 
    
    
     FIELD 
     The inventive concepts described herein relate to microelectronic devices and, more particularly, to high power, high frequency transistors having unit cell-based structures. 
     BACKGROUND 
     Electrical circuits requiring high power handling capability while operating at high frequencies, such as radio frequencies (500 MHz), S-band (3 GHz) and X-band (10 GHz), have in recent years become more prevalent. Because of the increase in high power, high frequency circuits, there has been a corresponding increase in demand for transistors which are capable of reliably operating at radio and microwave frequencies while still being capable of handling higher power loads. 
     To provide increased output power, transistors with larger gate peripheries have been developed. One technique for increasing the effective gate periphery of a transistor is to provide a plurality of transistor cells that are connected in parallel. For example, a high power transistor may include a plurality of gate fingers that extend in parallel between respective elongated source and drain contacts, as illustrated in  FIG.  1   . 
     In particular,  FIG.  1    illustrates a metal layout of a conventional transistor structure  10  that includes a gate pad  12 , a source pad  22  and a drain pad  32  on a semiconductor structure  20 .  FIG.  1    is a plan view of the device (i.e., looking down at the device from above). As shown in  FIG.  1   , in the conventional transistor  10 , the gate pad  12  is connected by a gate bus  14  to a plurality of gate fingers  16  that extend in parallel in a first direction (e.g., the y-direction indicated in  FIG.  1   ). The source pad  22  is connected to a plurality of parallel source contacts  26  via a source bus  24 , and the drain pad  32  is connected to a plurality of drain contacts  36  via a drain bus  34 . Each gate finger  16  runs along the y-direction between a pair of adjacent source and drain contacts  26 ,  36 . A unit cell of the transistor  10  is illustrated at box  40 , and includes a gate finger  16  that extends between adjacent source and drain contacts  26 ,  36 . The “gate length” refers to the distance of the gate metallization in the x-direction, while the “gate width” is the distance by which the source and drain contacts  26 ,  36  overlap in the y-direction. That is, “width” of a gate finger  16  refers to the dimension of the gate finger  16  that extends in parallel to the adjacent source/drain contacts  26 ,  36  (the distance along the y-direction). The gate periphery of the device refers to the sum of the gate widths for each gate finger  16  of the device  10 . 
     In addition to adding unit cells, the gate periphery of a multi-cell transistor device may be increased by making the gate fingers wider (i.e., longer in the y-direction). As the gate fingers of a device become wider, however, the high frequency performance of the device may be adversely impacted. In addition, making the gate fingers wider typically means that the gate fingers must handle increased current densities, which can cause electromigration of the gate finger metallization. 
     SUMMARY 
     A transistor device according to some embodiments includes a source contact extending in a first direction, a gate finger extending in the first direction adjacent the source contact, and a drain contact adjacent the gate finger. The gate finger is between the drain contact and the source contact. A gate pad is electrically connected to the gate finger at a plurality of points along the gate finger. 
     The device further includes a gate jumper that extends in the first direction and that is conductively connected to the gate pad. The gate pad is conductively connected through the gate jumper to at least one of the plurality of points along the gate finger. 
     The device may further include a gate bus connected to the gate jumper and the gate finger, and a gate signal distribution bar that is spaced apart from the gate bus in the first direction and that connects the gate jumper to the gate finger. 
     A transistor device according to further embodiments includes a gate pad, a gate finger in conductive contact with the gate pad at a first location on the gate finger and extending in a first direction, and a gate jumper in conductive contact with the gate pad and extending in the first direction. The gate jumper is conductively connected to the gate finger at a second location on the gate finger that is spaced apart from the first location so that a gate signal received at the gate pad is applied to the gate finger at the first location and at the second location. 
     A transistor device according to further embodiments includes a gate bus, a gate finger in contact with the gate bus and extending in a first direction, and a gate jumper in contact with the gate bus and extending in the first direction, wherein the gate jumper is in conductive contact with the gate finger at a location along the gate finger that is spaced apart from the gate bus in the first direction. 
     A transistor device according to further embodiments includes a substrate, a gate bus on the substrate, and first and second source contact segments on the substrate and extending in a first direction. The first and second source contact segments are separated from one another in the first direction by a gap. The device further includes a gate finger on the substrate and connected to the gate bus. The gate finger extends in the first direction adjacent the source contact segments. The device further includes a drain contact on the substrate adjacent the gate finger, wherein the gate finger is between the drain contact and the source contact segments, a gate jumper connected to the gate bus, wherein the gate jumper is provided over the source contact segments and extends in the first direction, and a gate signal distribution bar on the substrate and extending from the gap between the first and second source contact segments to the gate finger. The gate signal distribution bar contacts the gate finger at a gate signal distribution point that is spaced apart from the gate bus in the first direction, and the gate signal distribution bar is conductively connected to the gate jumper. 
     A transistor according to further embodiments includes a drain contact extending along a first axis, a source contact extending along a second axis that is parallel to the first axis, a gate finger extending between the source contact and the drain contact, and a plurality of spaced-apart gate resistors that are electrically connected to the gate finger. At least a first of the gate resistors is disposed in a portion of a region between the first axis and the second axis that is between a first end and a second end of the gate finger when the transistor is viewed from above. 
     In some embodiments, the gate finger may include a plurality of discontinuous, collinear gate finger segments that are electrically connected to each other. The transistor may further include a gate jumper that is electrically connected between a gate bus and a first of the gate finger segments. The first of the gate resistors may be interposed along an electrical path between the gate jumper and a first of the gate finger segments. The transistor may also include a first gate signal distribution bar that is interposed along an electrical path between the gate jumper and the first of the gate finger segments. The first of the gate resistors may be interposed along an electrical path between the first gate signal distribution bar and the first of the gate finger segments. Each gate finger segment may be part of a respective gate split, and the transistor may further include an odd mode resistor that is positioned between two adjacent gate splits. 
     In some embodiments, the source contact includes a plurality of collinear discontinuous source contact segments, and the gate jumper extends over the source contact. A first gate signal distribution bar may extend in a gap between two adjacent source contact segments. The odd mode resistor may be interposed between the first gate signal distribution bar and a second gate signal distribution bar that is collinear with the first gate signal distribution bar. Moreover, the transistor may include a second source contact that includes a plurality of collinear discontinuous source contact segments that does not have a gate jumper extending over it, and the odd mode resistor may be between two adjacent ones of the source contact segments of this second source contact. 
     A transistor according to still further embodiments includes a source contact extending in a first direction, a gate jumper extending in the first direction and a gate finger that comprises a plurality of discontinuous gate finger segments which may be collinear with each other. The transistor further includes a plurality of spaced-apart gate resistors that are electrically connected to the gate jumper. A first of the gate finger segments is connected to the gate jumper through a first of the gate resistors. 
     In some embodiments, the source contact includes a plurality of discontinuous source contact segments, and the first of the gate resistors is in a gap between two adjacent source contact segments. The gate jumper may extend over at least some of the source contact segments. The transistor may further include a drain contact extending in the first direction adjacent the gate finger so that the gate finger extends between the source contact and the drain contact, a second gate finger that comprises a plurality of discontinuous and collinear gate finger segments that extend in the first direction so that the drain contact extends between the gate finger and the second gate finger, and a second source contact that includes a plurality of discontinuous source contact segments that extends in the first direction adjacent the second gate finger. An odd-mode resistor may be provided in a gap between two adjacent source contact segments of the second source contact. 
     A gate signal distribution bar may extend between the gate jumper and a first of the gate finger segments of the first gate finger and between the gate jumper and a first of the gate finger segments of the second gate finger. The gate signal distribution bar may be located in a gap between two adjacent source contact segments of the source contact. The odd-mode resistor may be connected between the gate signal distribution bar and a second gate signal distribution bar that connects gate finger segments of a plurality of additional gate fingers to a second gate jumper. 
     A transistor according to further embodiments includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction. Each of the gate fingers comprises at least spaced-apart and generally collinear first and second gate finger segments, where the first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region. 
     In some embodiment, the transistor further includes a plurality of source contacts that extend in the first direction, each source contact including a plurality of discontinuous source contact segments, and each source contact extending between the gate fingers of respective pairs of the gate fingers and a plurality of drain contacts that extend in the first direction, each drain contact extending between the respective pairs of the gate fingers. A gate bus may be electrically connected to the gate fingers and a gate jumper may be electrically connected to the gate bus, where the gate jumper is interposed along an electrical path between and at least some of the gate finger segments and the gate bus. 
     In some embodiments, the resistor may be an odd mode resistor that is positioned between two adjacent ones of the source contact segments of one of the source contacts. In other embodiments, the resistor may be a gate resistor that is interposed along an electrical path between the gate jumper and the first gate finger segment of a first of the gate fingers. In these embodiments, the gate resistor may be interposed along a first gate signal distribution bar that extends between the gate jumper and the first gate finger segment of a first of the gate fingers. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate certain embodiment(s) of the invention. In the drawings: 
         FIG.  1    is a plan view of a metal layout of a conventional multi-cell transistor. 
         FIG.  2    is a plan view of a metal layout of a transistor in accordance with some embodiments. 
         FIG.  3    is a partial isometric view of the transistor of  FIG.  2   . 
         FIG.  4    is a partial cross section of the transistor of  FIG.  2    taken along line A-A′ of  FIG.  2   . 
         FIG.  5    is a plan view of a larger version of the transistor of  FIG.  2   . 
         FIG.  6    is a detail plan view of a small portion of the transistor of  FIG.  5   . 
         FIG.  7    is a cross-section of a unit cell of a transistor device taken along line B-B′ of  FIG.  2   . 
         FIG.  8    is a plan view of a metal layout of a transistor in accordance with further embodiments. 
         FIG.  9 A  is a partial cross section taken along line A-A′ of  FIG.  8   . 
         FIG.  9 B  is a partial cross section taken along line B-B′ of  FIG.  8   . 
         FIG.  10    is a plan view of a larger version of the transistor of  FIG.  8   . 
         FIG.  11    is a detail plan view of a small portion of the transistor of  FIG.  10   . 
         FIG.  12    is a plan view of a metal layout of a transistor in accordance with additional embodiments. 
         FIG.  13    is a plan view of a metal layout of a transistor in accordance with yet additional embodiments. 
         FIG.  14    is a plan view of a metal layout of a transistor in accordance with still further embodiments. 
         FIG.  15    is a plan view of a metal layout of a transistor in accordance with additional embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present inventive concepts are described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concepts to those skilled in the art. Like numbers refer to like elements throughout. 
     Embodiments of the inventive concepts provide multi-cell transistor devices with large effective gate widths. By feeding the gate signal to the gate fingers at multiple locations along the width of the gate finger, the high frequency gain performance of the transistor may be improved, and electromigration concerns that are normally associated with wide gate fingers can be reduced. According to some embodiments, a larger gate width of a multi-cell transistor device can be accommodated by adding a second layer of metal over the source regions of a unit cell to act as a gate jumper. The gate jumper is connected to the gate finger at various locations along the gate finger, effectively dividing the gate finger into multiple segments. The gate jumper may be provided by a second layer of metal that extends over and above the source contact that connects the gate pad to the gate segments. In some embodiments, the gate jumper could extend over and above the drain contact or the gate finger instead of over and above the source contact. 
     By effectively dividing the gate finger into segments and distributing the gate signal to each of the gate finger segments by means of a gate jumper, the gain performance of the transistor may be improved and electromigration concerns can be alleviated. 
     Thus, embodiments of the inventive concepts provide transistor layouts that define multiple unit cells in series for each gate finger. Individually, each of the unit cells has a shorter effective gate width. However, when connected in series, the unit cells can increase the effective length of a single gate finger. The gate fingers of the series-connected unit cells are connected to a gate bus by means of a second metal bridge that runs over the source contacts of the unit cells. The metal bridge is connected between the source contacts to connecting bars that run along the surface of the substrate between the source contacts and connect to the gate finger. 
     A transistor having a layout as described herein may have higher frequency performance and higher output power while at the same time having a reduced current density, which can improve device reliability. 
     Pursuant to further embodiments of the present invention, multi-cell transistors with large effective gate widths are provided in which a plurality of series gate resistors (which are also referred to as “gate resistors” herein) are distributed throughout the device. For example, the transistors may have segmented gate fingers, and a series gate resistor may be provided for each gate finger segment or for pairs of gate finger segments. This approach breaks up long feedback loops within the gate fingers and drains of the transistor structure by making the feedback loops lossy enough to avoid high levels of instability. The distributed series gate resistors may be positioned, for example, in the gap regions that are provided between the gate finger segments of the gate fingers. 
     Thus, in some embodiments, transistors are provided that include a drain contact extending along a first axis, a source contact extending along a second axis that is parallel to the first axis, and a gate finger extending between the source contact and the drain contact. The gate finger may comprise a plurality of physically discontinuous, collinear gate finger segments that are electrically connected to each other by one or more other structures (e.g., a gate jumper). The transistor further includes a plurality of spaced-apart gate resistors that are electrically connected to the gate finger. At least one of the gate resistors is disposed in a portion of the region between the first axis and the second axis that is between a first end and a second end of the gate finger when the transistor is viewed from above. In some embodiments, a gate jumper may be electrically connected to the gate finger, and the gate jumper may be electrically connected to a gate bus. The gate jumper may be interposed along an electrical path between a first of the gate finger segments and the gate bus, and a first of the gate resistors may be interposed along an electrical path between the gate jumper and the first of the gate finger segments. 
     In other embodiments, transistors are provided that include a source contact extending in a first direction, a gate jumper extending in the first direction, and a gate finger that comprises a plurality of discontinuous gate finger segments that extend in the first direction. The transistor further includes a plurality of spaced-apart gate resistors, each of which is electrically connected to the gate jumper. A first of the gate finger segments is connected to the gate jumper through a first of the gate resistors. 
     Pursuant to still further embodiments of the present invention, multi-cell transistors with large effective gate widths are provided in which a plurality of odd mode resistors are distributed throughout the device. In an example embodiment, odd mode resistors may be provided in the gap regions that are formed between the “gate splits,” where a gate split refers to the regions where a plurality of gate finger segments extend in parallel to each other. The odd mode resistors may be distributed throughout these gap regions to further improve the stability of the transistor. The above described gate resistors may also be located in these gap regions. 
     Thus, in additional embodiments, transistors are provided that include a plurality of gate fingers that extend in a first direction and that are spaced apart from each other in a second direction that is perpendicular to the first direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other, where the first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. At least one resistor is disposed in the gap region. The at least one resistor may be an odd mode resistor and/or a series gate resistor. 
     The transistors according to embodiments of the inventive concepts may have large effective gate widths, support increased power density levels and exhibit improved frequency response as compared to conventional transistors. Additionally, the gate series resistors and odd mode resistors, if provided, may help prevent feedback loops that may generate unwanted signals at frequencies that are low enough to be close to or within the operating frequency range of the transistor. Accordingly, the transistors may also exhibit increased stability and hence may have improved production yields and/or better reliability. 
     It will be appreciated that the above-described embodiments may be combined in any fashion. For example, transistors may be provided that include both distributed gate resistors and distributed odd mode resistors. Likewise, transistors having non-segmented gate fingers may include either or both distributed gate resistors and distributed odd mode resistors. 
     Embodiments of the present invention will now be described in greater detail with reference to  FIGS.  2 - 15   . 
       FIG.  2    is a plan view of a metal layout of a transistor  100  in accordance with some embodiments. The transistor is formed on a semiconductor structure  120  that includes one or more device epitaxial layers which are described in greater detail below. The layout of  FIG.  2    is simplified for ease of understanding and includes a gate pad  112  that is connected to a gate bus  114  and a drain pad  132  that is connected to a drain bus  134 . The source pad and source bus are omitted from  FIG.  2    for clarity of illustration, but are illustrated in  FIGS.  5  and  6   . 
     A plurality of gate fingers  116  are connected to the gate bus  114  and extend in the y-direction. Likewise, a plurality of drain contacts  136  are connected to the drain bus  134  and extend in parallel with and adjacent to respective ones of the gate fingers  116 . Although only four gate fingers  116  and three drain contacts  136  are illustrated in  FIG.  2   , it will be appreciated that the transistor  100  may have many more gate fingers  116  and drain contacts  136  so that the transistor has a large number of unit cells. 
     Source contacts  162  are also provided and extend in the y-direction in parallel with adjacent ones of the gate fingers  116 . The source contacts  162  are divided in the y-direction into respective source contact segments  162   a ,  162   b  and  162   c . The source contact segments may be connected by means of source contact bars  128  ( FIG.  6   ) that extend laterally across the device structure (in the x-direction). The source contact segments  162   a ,  162   b ,  162   c  may be connected by other means. For example source contact plugs may be provided that electrically connect each source contact segment  162   a ,  162   b ,  162   c  to a common conductive layer located, for example, in a lower level of the device. 
     Adjacent ones of the source contact segments  162   a - 162   c  are separated by gaps  162   g . Although  FIG.  2    illustrates three source contact segments  162   a - 162   c  for each source contact  162 , the inventive concepts are not limited to such a configuration, and it will be appreciated that the source contact  162  may include two or more source contact segments  162   a - 162   c.    
     The gate fingers  116  may extend in parallel with the source contacts  162  for the entire length of the source contacts  162 . However, because the source contacts  162  are divided into source contact segments  162   a - 162   c , the source contact segments  162   a ,  162   b  and  162   c  define a plurality of series unit cells  40   a ,  40   b ,  40   c  for each of the gate fingers  116 . That is, each gate finger  116  acts as a gate contact for a plurality of unit cells  40   a ,  40   b ,  40   c  that are laid out in the direction (y-direction) along which the gate fingers  116  extend and that defines the width of the gate fingers  116 . Thus, the total width contributed to the gate periphery of the overall device by each gate finger  116  is equal to the distance by which the gate finger  116  overlaps the adjacent source contact segments  162   a ,  162   b  and  162   c  in the y-direction. 
     The transistor  100  further includes a plurality of gate jumpers  172  that extend along the y-direction in parallel with the gate fingers  116 . The gate jumpers  172  may be formed over the source contacts  162 , and may be insulated from the source contacts  162  by, for example, a dielectric layer and/or an air gap. The gate jumpers  172  are electrically connected to the gate bus  114 , and connect each gate finger  116  to the gate bus  114  at multiple locations along the gate finger  116 . 
     In particular, the gate jumpers  172  connect to the gate fingers  116  through gate signal distribution bars  174  that are provided at multiple locations along the width of the device and that extend laterally (in the x-direction) within the gaps  162   g  between adjacent ones of the source contact segments  162   a ,  162   b  and  162   c . The gate signal distribution bars  174  contact the gate fingers  116  at respective gate signal distribution points  176 . Thus, an electrical signal applied to the gate pad  112  (a “gate signal”) is carried to the gate bus  114 , and then to the gate jumpers  172 , which distribute the gate signal to the gate fingers  116  at multiple locations (the gate signal distribution points  176 ) along the width of the gate fingers  116 . Thus, in the embodiment of  FIG.  2   , rather than having the gate fingers  116  carry the gate signal for the entire width of the device, the gate signal is carried by the gate jumpers  172  over a large part of the width of the device and then distributed to the gate fingers  116  at various locations along the width of the device. 
     The gate jumpers  172  may have larger cross sectional areas than the gate fingers  116 , and thus may be better able to handle higher current densities than the gate fingers  116  without the problems normally associated with increased gate widths, such as electromigration and reduction of high frequency gain performance. 
       FIG.  3    is a partial isometric view of the metal layout of transistor  100 , and  FIG.  4    is a partial cross section taken along line A-A′ of  FIG.  2   . As can be seen in  FIGS.  3  and  4   , the gate jumpers  172  are formed at a metal level higher than the metal level of the source contact segments  162   a ,  162   b ,  162   c , the gate fingers  116 , the gate bus  114  and the gate signal distribution bars  174 . The gate jumpers  172  are connected to the gate bus  114  and the gate signal distribution bars  174  by vertical contact plugs  178 . 
     The gate jumpers  172 , gate bus  114 , vertical contact plugs  178  and gate signal distribution bars  174  may be formed of a conductive material, such as copper or aluminum, having a very low resistance. 
       FIG.  5    is a plan view of a larger version of transistor  100 , and  FIG.  6    is a detail plan view of a small portion  150  of the metal layout of  FIG.  5    (namely the portion within the dotted box in  FIG.  5   ). The transistor  100  includes a plurality of unit cells  40  that extend vertically (in the y-direction). Each of the unit cells  40  includes one gate finger  116  that extends over the entire width of the device, and is subdivided into series unit cells  40   a ,  40   b ,  40   c  that are arranged in the vertical direction (y-direction) as described above. In the embodiment illustrated in  FIGS.  5  and  6   , each of the unit cells  40  has an overall width of  1120  microns, with the series unit cells  40   a ,  40   b , and  40   c  having widths of  370  microns,  380  microns and  370  microns, respectively, although the inventive concepts are not limited to these particular dimensions. In this manner, the effective gate width of the device may be increased. 
     Referring to  FIG.  6   , a gate pad  112  and gate bus  114  are provided at the one end of the structure, while a drain pad  132  and drain bus  134  are provided at the other end of the structure. Source pads  122  are provided on the side of the structure and are connected to a source bus  124 . The source bus  124  is connected to a plurality of source contact bars  128  that extend in the lateral direction (x-direction) to contact the source contact segments  162   a ,  162   b ,  162   c . As noted above, the source contact segments  162   a ,  162   b ,  162   c  may be electrically connected in other ways such as through the use of source contact plugs that electrically connect each source contact segment  162   a ,  162   b ,  162   c  to a common conductive layer. 
     The detail view of the portion  150  of the device layout of the transistor  100  in  FIG.  6    also illustrates the gate fingers  116 , the gate jumpers  172 , gate signal distribution bars  174  and the gate signal distribution points  176  where the gate signal distribution bars  174  contact the gate fingers  116 . 
       FIG.  7    is a cross-section of a unit cell  40  of a transistor device  100  taken along line B-B′ of  FIG.  2   . The transistor structure  100  includes a semiconductor structure  120  including a substrate  200 , which may, for example, include 4H—SiC or 6H—SiC. A channel layer  210  is formed on the substrate  200 , and a barrier layer  220  is formed on the channel layer  210 . The channel layer  210  and the barrier layer  220  may include Group III-nitride based materials, with the material of the barrier layer  220  having a higher bandgap than the material of the channel layer  210 . For example, the channel layer  210  may comprise GaN, while the barrier layer  220  may comprise AlGaN. 
     Due to the difference in bandgap between the barrier layer  220  and the channel layer  210  and piezoelectric effects at the interface between the barrier layer  220  and the channel layer  210 , a two dimensional electron gas (2DEG) is induced in the channel layer  210  at a junction between the channel layer  210  and the barrier layer  220 . The 2DEG acts as a highly conductive layer that allows conduction between the source and drain regions of the device that are beneath a source contact segment  162   b  and a drain contact  136 , respectively. The source contact segment  162   b  and the drain contact  136  are formed on the barrier layer  220 . A gate finger  116  is formed on the barrier layer  220  between the drain contact  136  and the source contact segment  162   b . A gate jumper  172  is provided over the source contact segment  162   b , and is connected to the gate finger  116  through a vertical contact plug  178  and a gate signal distribution bar  174 . The vertical contact plug  178  and the gate signal distribution bar  174  are provided in gaps  162   g  between adjacent ones of the source contact segments  162   a - 162   c  and do not physically contact the source contact segments  162   a - 162   c . Note that the source contact segment  162   b  is not actually in the cross-section of  FIG.  7    as it is offset in the y-direction from the cut along line B-B′ (see  FIG.  2   ), but is illustrated in  FIG.  7    to facilitate the above explanation. 
     A first interlayer insulating layer  232  is formed over the drain contact  136 , the gate finger  116 , the source contact segment  162   b  and the gate signal distribution bar  174 . The interlayer insulating layer  232  may include a dielectric material, such as SiN, SiO 2 , etc. The vertical contact plug  178  penetrates the first interlayer insulating layer  232 . The gate jumper  172  is formed on the first interlayer insulating layer  232 , which insulates the gate jumper  172  from the source contact segment  162   b . A second interlayer insulating layer  234  may be formed on the first interlayer insulating layer  232  and the gate jumper  172 . The second interlayer insulating layer  234  may include a dielectric material, such as SiN, SiO 2 , etc. 
     The material of the gate finger  116  may be chosen based on the composition of the barrier layer  220 . However, in certain embodiments, conventional materials capable of making a Schottky contact to a nitride based semiconductor material may be used, such as Ni, Pt, NiSi x , Cu, Pd, Cr, W and/or WSiN. The drain contacts  136  and source contact segments  162  may include a metal, such as TiAlN, that can form an ohmic contact to GaN. 
     Series gate resistors and odd mode resistors may be included in the high power transistors according to embodiments of the present invention in order to stabilize the feedback loops within the gate fingers and drains of the device. In high power devices, the gates may have long gate widths in order to increase the gate periphery of the device, which results in long feedback loops. Because these high power transistors have large transconductance values, the feedback loops may be prone to instability. In particular, the feedback loops may generate an unwanted signal which may be in or out of the frequency band of operation of the transistor. In either case, the generation of such a signal may be problematic, and may render the transistor unusable. The instability of the feedback loops tends to increase with the length of the feedback loop. 
     Pursuant to further embodiments of the present invention, high power transistors are provided that include multiple series gate resistors and/or odd mode resistors that are distributed throughout the device and, in particular, along the long gate fingers. The distributed series gate resistors and/or odd mode resistors may be particularly advantageous in transistors that have segmented gate fingers as such devices may include gap regions between the “gate splits” that are natural locations for locating the series gate resistors and/or odd mode resistors along the width of the gate fingers. Herein, the term “gate splits” refers to the shorter arrays of gate finger segments that are produced when long gate fingers are segmented into multiple gate finger segments as discussed above with reference to  FIGS.  2 - 7   . The gap regions that are present between adjacent gate splits may be a convenient location for implementing the distributed series gate resistors and odd mode resistors, as will be discussed in greater detail below. 
     It has been found that by distributing the series gate resistors and/or odd mode resistors along the extended width of the gate fingers, the feedback loops may become sufficiently lossy such that the potential instability is overcome. Accordingly, by distributing the series gate resistors and/or odd mode resistors along the extended width of the gate fingers it may be possible to increase device yield and/or reduce the failure rate of devices in the field. Moreover, when the series gate resistors and/or odd mode resistors are distributed along and between gate finger segments of a segmented gate fingers, relatively small resistance levels may be used. For example, if a transistor has three gate splits, the resistance levels may be about one third the size of the resistance levels that would be used if the gate fingers were not segmented. Moreover, in practice it has been found that the reduction in the resistance values is even greater. For example, when three gate splits are used, the series resistors included along each gate segment may have resistance values that are one fourth to one fifth of the resistance value of a series gate resistor that is implemented at the gate pad. The use of resistors having lower resistance values reduces losses and therefore results in a transistor having a higher gain, while also exhibiting increased stability. 
       FIG.  8    is a plan (top) view of a metal layout of a transistor  300  in accordance with further embodiments that implements both the series gate resistors and the odd mode resistors in a distributed fashion, as discussed above. The transistor  300  is formed on a semiconductor structure  320  that includes one or more device epitaxial layers. The semiconductor structure  320  may be the same as the semiconductor structure  120  discussed above with reference to  FIG.  7   . As with the preceding figures, the layout of  FIG.  8    is simplified for ease of understanding and includes a pair of gate pads  312  that are connected to a respective pair of gate buses  314 , as well as a drain pad  332  that is connected to a drain bus  334 . A source pad  322  and source bus are also included in the transistor  300 , but are omitted from  FIG.  8    for clarity of illustration. The source pad  322  is shown in  FIG.  10   . 
     A plurality of gate fingers  316  are connected to each gate bus  314  and extend in the y-direction. Each gate finger  316  is divided in the y-direction into three gate finger segments  316   a ,  316   b  and  316   c . As described below, the gate finger segments  316   a ,  316   b ,  316   c  of each gate finger  316  may be electrically connected to each other via gate jumpers  372 , gate signal distribution bars  374  and vertical contact plugs  378  ( FIG.  9 A ). A plurality of drain contacts  336  are connected to the drain bus  334  and extend in parallel with and adjacent respective ones of the gate fingers  316 . The gate signal distribution bars  374  may be formed at a different vertical level in the device than the gate distribution bars  174  of transistor  100  to allow the gate signal distribution bars  374  to pass over the drain contacts  336 , as will be described below. Source contacts  362  are also provided and extend in the y-direction in parallel with adjacent ones of the gate fingers  316 . The source contacts  362  are also divided in the y-direction into respective source contact segments  362   a ,  362   b  and  362   c . The source contact segments  362   a ,  362   b ,  362   c  may be electrically connected to each other via source contact plugs  364 . Each source contact plug  364  may electrically connect a respective source contact segment  362   a ,  362   b ,  362   c  to a common conductive layer that acts as a source bus. This source bus may be located, for example, in a lower level of the device. More than one source contact plug  364  may be provided per source contact segment  362   a ,  362   b ,  362   c  in some embodiments. Two representative source contact plugs  364  are illustrated on one source contact segment  362   c  in  FIG.  8   . The source contact plugs  364  for the other source contact segments  362   a ,  362   b ,  362   c  have been omitted from  FIG.  8    (as well as from  FIGS.  9 A- 9 B and  12 - 13   ) to simplify the drawings.  FIGS.  10  and  11    illustrate how, for example, a pair of source contact plugs  364  may be provided for each source contact segment  362   a ,  362   b ,  362   c . The source contact segments  362   a ,  362   b ,  362   c  may also be electrically connected by other means such as, for example, source contact bars. In  FIG.  8   , a total of sixteen segmented gate fingers  316 , eight segmented source contacts  362  and eight drain contacts  336  are shown. It will be appreciated, however, that the transistor  300  may have many more gate fingers  316 , source contacts  362  and drain contacts  336  so that the transistor  300  has a large number of unit cells. Fewer gate fingers  316 , source contacts  362  and drain contacts  336  may be provided in other embodiments. 
     Adjacent ones of the gate finger segments  316   a - 316   c  are separated by gaps  316   g , and adjacent ones of the source contact segments  362   a - 362   c  are separated by gaps  362   g . Although  FIG.  8    illustrates three gate finger segments  316   a - 316   c  and three source contact segments  362   a - 362   c  for each respective gate finger  316  and source contact  362 , the inventive concepts are not limited to such a configuration. Thus, it will be appreciated that a gate finger  316  may include two or more gate finger segments and that a source contact  362  may include two or more source contact segments. 
     The gate fingers  316  may extend in parallel with the source contacts  362  for the entire length of the source contacts  362 . Because the gate fingers  316  and source contacts  362  are segmented, a plurality of unit cells  340   a ,  340   b ,  340   c  are defined along each gate finger  316 . That is, each gate finger segment  316   a - 316   c  acts as a gate contact for a respective unit cell  340   a ,  340   b ,  340   c  that are laid out in the direction (y-direction) along which the gate fingers  316  extend. The sum of the width of the gate finger segments  316   a - 316   c  defines the total width of each gate finger  316 . Thus, the total width contributed to the gate periphery of the overall device by each gate finger  316  is equal to the sum of the widths of the gate finger segments  316   a - 316   c  in the y-direction. 
     The transistor  300  further includes a plurality of gate jumpers  372  that extend along the y-direction in parallel with the gate fingers  316 . The gate jumpers  372  may be formed at a metal level higher than the metal level of the source contact segments  362 , the gate fingers  316  and the gate buses  314 . The gate jumpers  372  may be formed over the source contacts  362 , and may be insulated from the source contacts  362  by, for example, a dielectric layer and/or an air gap. The gate jumpers  372  need not extend over the source contact segments  362   c  that are farthest from the gate buses  314 . The gate jumpers  372  are electrically connected to the gate buses  314 . The gate jumpers  372  may electrically connect some or all of the gate finger segments  316   a - 316   c  of each gate finger  316  to one of the gate buses  314 . In the embodiment depicted in  FIG.  8   , each gate jumper  372  electrically connects gate finger segments  316   b  and  316   c  to a gate bus  314 , while gate finger segments  316   a  are connected to the gate buses  314  via more direct connections. Gate finger segments  316   a  may be connected to the gate buses  314  through the gate jumper  372  in other embodiments. In some embodiments, the gate jumpers  372  may be positioned over the drain contacts  336  or the gate fingers  316  instead of over the source contacts  362 . 
       FIG.  9 A  is a partial cross section taken along line A-A′ of  FIG.  8   .  FIG.  9 B  is a partial cross section taken along line B-B′ of  FIG.  8   . As can be seen in  FIGS.  8  and  9 A , a plurality of gate jumpers  372 , gate signal distribution bars  374  and vertical contact plugs  378  are provided. The gate jumpers  372  are connected to a gate bus  314  and the gate signal distribution bars  374  by the vertical contact plugs  378 . The gate jumpers  372 , gate signal distribution bars  374  and vertical contact plugs  378  are used to connect each gate finger segment  316   b - 316   c  to one of the gate buses  314 . The gate signal distribution bars  374  may be formed at a higher metal layer in the device than the gate fingers  316 . For example, the gate signal distribution bars  374  may be formed in the same metal layer of the device as the gate jumpers  372 , as shown in  FIG.  9 A . Vertical contact plugs  378  may connect the gate jumpers  372  to the gate buses  314 . Additional vertical contact plugs  378  (not visible in the cross-section of  FIG.  9 A , but located at the points where each gate signal distribution bar passes over a gate resistor  380  in the plan view of  FIG.  8   ) may physically and electrically connect the gate signal distribution bars  374  to the gate resistors and the gate finger segments  316   a - 316   c  connected thereto. As noted above, the gate jumpers  372  may extend over and above the source contacts  362 . As can be seen in  FIG.  8   , a gate jumper  372  is provided over every other source contact  362 , in contrast to the transistor  100  of  FIGS.  2 - 7    which included a gate jumper  172  extending over every source contact  162 . Each gate jumper  372  in the transistor  300  of  FIGS.  8 - 9 B  thus feeds four gate fingers  316  instead of two gate fingers  116  as in the case of transistor  100 . The gate signal distribution bars  374  are formed at a higher metal layer in the device than the gate distribution bars  174  of transistor  100  to allow each gate signal distribution bar  374  to pass over two drain contacts  336  to connect to the outer ones of the four gate finger segments  316   a - 316   c.    
     The gate jumpers  372 , gate buses  314 , vertical contact plugs  378  and gate signal distribution bars  374  may be formed of a conductive material, such as copper or aluminum, having a very low resistance. 
     Still referring to  FIGS.  8  and  9 A , the gate signal distribution bars  374  extend laterally (in the x-direction) in the gaps  362   g  between adjacent ones of the source contact segments  362   a ,  362   b  and  362   c . The gate signal distribution bars  374  that are coupled to the first gate finger segments  316   a  may be coupled to two of the gate finger segments  316   a . Each of the gate signal distribution bars  374  that are coupled to the second or third gate finger segments  316   b ,  316   c  may be coupled to four of the gate finger segments  316   b  or  316   c . As can be seen in  FIG.  8   , each gate signal distribution bar  374  that is coupled to the first gate finger segments  316   a  may connect to one of the gate buses  314  through a gate resistor  380 . The gate signal distribution bars  374  that connect to the gate finger segments  316   a  may be part of the same metal layer as the gate fingers  316  or part of the same metal layer as the gate jumpers  372 , since these gate signal distribution bars  374  need not cross the drain contacts  336 . Each gate signal distribution bar  374  that is coupled to either second gate finger segments  316   b  or third gate finger segments  316   c  may connect to one of the gate buses  314  through one of the gate jumpers  372 , and may connect to the gate finger segments  316   b ,  316   c  through respective vertical contact plugs  378 , as can be seen in  FIGS.  8  and  9 A . A series gate resistor  380  is provided on the electrical path between each gate finger segment  316   b ,  316   c  and its associated gate signal distribution bar  374 . 
     Referring still to  FIGS.  8  and  9 A , the distribution of an electrical signal that is applied to the gate pad  312  on the left-hand side of  FIG.  8    to the leftmost gate finger segments  316   a ,  316   b ,  316   c  in  FIG.  8    will now be discussed. When the gate signal is applied to the gate pad  312 , it is carried to the left gate bus  314 . The gate signal travels from the left gate bus  314  through a first gate signal distribution bar  374  and a first series gate resistor  380  to the first gate finger segment  316   a . The gate signal also travels from the left gate bus  314  through a first vertical contact plug  378  that connects the gate bus  314  to a gate jumper  372 , through the gate jumper  372  to a second gate signal distribution bar  374 , and through the second gate signal distribution bar  374  to a second vertical contact plug  378  that connects to the leftmost second gate finger segment  316   b  through a second series gate resistor  380 . Similarly, the gate signal travels from the left gate bus  314  through the first vertical contact plug  378  to the gate jumper  372 , through the gate jumper  372  to a third gate signal distribution bar  374 , and through the third gate signal distribution bar  374  to a third vertical contact plug  378  that connects to the leftmost third gate finger segment  316   c  through a third series gate resistor  380 . 
     Thus, as shown in  FIGS.  8  and  9 A , the gate signal does not travel the full length of any gate finger  316 , but instead travels only along the length of a gate finger segment (for example, gate finger segments  316   a ) or along the length of a gate finger segment and part of the gate jumper  372  (for example, gate finger segments  316   b ) or along the length of a gate finger segment and the full length of the gate jumper  372  (for example, gate finger segments  316   c ). The gate jumpers  372  may have larger cross sectional areas than the gate fingers  316 , and thus may be better able to handle higher current densities than the gate fingers  316  without the problems normally associated with increased gate widths, such as electromigration and reduction of high frequency gain performance. The gate signals also travel along a portion of a gate signal distribution bar  374  and vertical contact plugs  378 . However, it should be noted that  FIG.  8    is not drawn to scale and that the distance that a gate signal travels along any gate signal distribution bar  374  may be very small compared to the length of a gate finger segment in the y-direction (e.g., less than 5%), as can be seen in  FIGS.  10 - 11   . The distances travelled along the vertical contact plugs  378  are also very small. Accordingly, the distance that the gate signals travel along narrow conductive traces may be reduced. 
     As discussed above, the transistor  300  includes a plurality of series gate resistors  380  that are distributed throughout the device. In particular, a series gate resistor  380  is provided at or near one end of each gate finger segment  316   a ,  316   b ,  316   c . As shown in  FIG.  8   , the gate fingers  316  are divided into three “gate splits,” namely a first gate split  382   a  that includes the gate finger segments  316   a , a second gate split  382   b  that includes the gate finger segments  316   b , and a third gate split  382   c  that includes the gate finger segments  316   c . A first gap region  384   a  is provided between the gate buses  314  and the first gate split  382   a , a second gap region  384   b  is provided between gate splits  382   a  and  382   b , and a third gap region  384   c  is provided between gate splits  382   b  and  382   c.    
     As shown in  FIG.  8   , the series gate resistors  380  may be formed in the above-described gap regions  384   a - 384   c . The series gate resistors  380  may be formed, for example, by depositing a higher resistivity conductive material, as compared to the conductive material used to form the gate fingers  316 , drain contacts  336 , source contacts  362 , etc. The series gate resistors  380  may be provided in any appropriate vertical level of the transistor  300 . In an example embodiment, the series gate resistors  380  may be formed at the same metallization level as the source contacts  362 , the drain contacts  336  and the gate fingers  316 , as can be seen or inferred from  FIGS.  8  and  9 A . It will also be appreciated that the gate resistors  380  (or the odd mode resistors  390  discussed below) may be replaced with other lossy elements that may act as the functional equivalent to a resistor, such as, for example, a series inductor-capacitor circuit. 
     As will be discussed below with reference to  FIG.  12   , a single series gate resistor  80  may provided between each gate pad  312  and its associated gate bus  314  instead of the distributed series gate resistors  380  included in transistors according to certain embodiments of the present invention. When the series gate resistors are implemented as a single series gate resistor  80  between each gate pad  312  and its corresponding gate bus  314 , each series gate resistor  80  may need to have a relatively high resistance value in order to reduce or prevent instabilities in the device. In the transistor  300 , a plurality of series gate resistors  380  are positioned between the gate splits  382  of the device. Each of the gate resistors  380  may have a much smaller resistance value as compared to the gate resistors  80  that would be required if gate resistors  80  were only located between the gate pads  312  and the gate buses  314 . 
     A series gate resistor  380  may be provided for each gate finger segment  316   a ,  316   b ,  316   c  in some embodiments, while in other embodiments some gate finger segments may share a series gate resistor  380 . In the particular embodiment depicted in  FIG.  8   , all of the gate finger segments  316   b ,  316   c  have their own associated series gate resistor  380 , while pairs of gate finger segments  316   a  share a single series gate resistor  380 . It will also be appreciated that in other embodiments, some of the gate finger segments  316   a - 316  may not have an associated gate resistor  380 . 
     By distributing the series gate resistance in two or more locations along the gate fingers  316 , the feedback loops within the gate fingers and drains of the transistor may be made sufficiently lossy so that instability may be reduced or eliminated. This may improve device yields and/or reduce the occurrence rate of device failures in the field. Moreover, as described above and as can be seen in  FIG.  8   , the current path along any particular gate finger segment  316   a ,  316   b ,  316   c  may only traverse a single series gate resistor  380 . As the series gate resistors  380  may have relatively small resistance values, power losses are reduced and the transistor  300  may thus support higher gain levels for a given size device. 
     As can be seen in  FIG.  8   , the transistor  300  includes a drain contact  336  that extends in the y-direction along a first axis, a source contact  362  that extends in the y-direction along a second axis that is parallel to the first axis, and a gate finger  316  that extends between the source contact  362  and the drain contact  336 . The gate finger  316  comprises a plurality of discontinuous and collinear gate finger segments  316   a ,  316   b ,  316   c  that are electrically connected to each other. The transistor  300  further includes a plurality of spaced-apart gate resistors  380  that are electrically connected to the gate finger  316 . Each gate resistor  380  may be coupled between a respective one of the gate finger segments  316   a ,  316   b ,  316   c  and a respective one of the gate signal distribution bars  374 . At least one of the gate resistors  380  is disposed between the first axis and the second axis. A gate jumper  372  is interposed along an electrical path between a gate bus  314  and the gate finger  316 . The gate jumper  372  is interposed along respective electrical paths between gate finger segments  316   b  and  316   c  and the gate bus  314 , and respective gate resistors  380  are interposed along respective electrical paths between the gate jumper  372  and the gate finger segments  316   b ,  316   c.    
     As can also be seen in  FIG.  8   , the transistor  300  includes a source contact  362  that extends in the y-direction, a gate jumper  372  that extends in the y-direction, and a gate finger  316  that comprises a plurality of discontinuous and electrically-connected gate finger segments  316   a ,  316   b ,  316   c . The transistor  300  further includes a plurality of spaced-apart gate resistors  380 . Gate finger segments  316   b  and  316   c  are connected to the gate jumper  372  through respective first and second gate resistors  380 . Pairs of the gate finger segments  316   a  are connected to the gate buses  314  through respective gate resistors  380 . 
     As is further shown in  FIG.  8   , odd mode resistors  390  are also included in the transistor  300 . The odd mode resistors  390  are provided to break up the long odd mode instability feedback loops in the device. In particular, as the number of gate fingers  316  fed by a gate jumper  372  increases, instabilities may arise. For example, a transistor may be stable when a gate jumper  372  feeds four gate fingers  316 , but may start to show instability if the gate jumper  372  is used to feed eight gate fingers  316 . When instabilities arise may be a function of the gate finger width and the frequency of operation of the device. The odd mode resistors  390  may be interposed between adjacent gate signal distribution bars  374 . When the transistor  300  operates normally, the voltage on each side of each odd mode resistor  390  should be the same, and thus no current should flow between adjacent gate signal distribution bars  374 . 
     Odd mode resistors  390  may be provided in the gap regions  384  that are between adjacent gate splits  382 . As shown in  FIGS.  8  and  9 B , odd mode resistors  390  may be implemented at, for example, the same metallization level as the gate signal distribution bars  374  and source contacts  362 , and may be directly connected between two adjacent gate distribution bars  374 . Odd mode resistors  390  may also be interposed between adjacent gate buses  314 . 
     Thus, the transistor  300  may include a plurality of gate fingers  316  that extend in the y-direction and that are spaced apart from each other in the x-direction. Each of the gate fingers  316  may include a plurality of spaced-apart and generally collinear gate finger segments  316   a ,  316   b ,  316   c  that are electrically connected to each other, where the gate finger segments  316   a ,  316   b ,  316   c  are arranged in respective gate splits  382   a ,  382   b ,  382   c  that are separated by gap regions  384   b ,  384   c . Odd mode resistors  390  are disposed in the gap regions  384   b ,  384   c . In example embodiments, the odd mode resistors  390  may be interposed between adjacent gate signal distribution bars  374 . 
     It will also be appreciated that the source contact  362  need not be segmented in some embodiments. In particular, the gate resistors  380  and the odd mode resistors may both be implemented in the same metal layer as the gate signal distribution bars  374  and the gate jumpers  372 . In such an implementation, the source contacts  362  need not be segmented. Thus, it will be appreciated that in other embodiments the resistors  380 ,  390  may be implemented directly above, or above and to the side of, the source contacts  362  in other embodiments, and that each source contact  362  may be a single, continuous (i.e., non-segmented) source contact  362 . 
     While  FIG.  8    depicts a transistor  300  that includes segmented gate fingers  316  and segmented source contacts  362 , it will be appreciated that embodiments of the present invention are not limited thereto. For example, in other embodiments, the drain contacts  336  may be segmented in a similar fashion so that each drain contact includes, for example, three separate segments. When the drain contacts  336  are segmented, they may be electrically connected to each other via, for example, drain contact plugs and another metallization layer in the device. In embodiments, where the drain contacts are segmented, the source contacts  362  may or may not be segmented. Additionally, the gate fingers  316  may be segmented as shown in  FIG.  8    or may not be segmented as shown in  FIG.  2    (as well as in  FIGS.  14 - 15   ). Segmenting the drain contacts may provide additional room in the regions between the gate splits for gate resistors  380  and/or odd mode resistors  390 . As one simplt example of such an embodiment having segmented drain contacts  336 , the transistor  300  of  FIG.  8    could be modified so that reference numerals  332 ,  334  and  336  were a source pad, a source bus and source contacts, respectively, and reference numerals  362   362   a / 362   b / 362   c  and  364  were a drain contact, drain contact segments and drain contact plugs, respectively. In other words,  FIG.  8    may also be viewed as an embodiment having segmented gate fingers  316  and segmented drain contacts  362  simply by reversing the source and drain features. 
       FIG.  10    is a plan view of a larger version of the transistor  300  of  FIG.  8   .  FIG.  11    is a detail plan view of a small portion  302  of the transistor  300  of  FIG.  10   . 
     Referring to  FIGS.  10  and  11   , the transistor  300  includes a plurality of unit cells that extend vertically (in the y-direction). Each of the unit cells includes a gate finger  316  that extends over the entire width of the device, and is subdivided into series unit cells  340   a ,  340   b ,  340   c  that are arranged in the vertical direction (y-direction) as described above. In the embodiment illustrated in  FIGS.  10 - 11   , each of the unit cells  340  has an overall width of 1120 microns, with the series unit cells  340   a ,  340   b , and  340   c  having widths of  370  microns, 380 microns and 370 microns, respectively, although the inventive concepts are not limited to these particular dimensions. 
     A plurality of gate buses  314  are provided at the one end of the structure, while a drain bus  334  is provided at the other end of the structure. Source pads  322  are provided on the side of the structure and are connected to a source bus that is located, for example, on a lower metallized layer of the device (not shown). The source contact segments  362   a ,  362   b ,  362   c  are connected to the source bus via contact plugs  364 . 
     The detail view of the portion  302  of the device layout of the transistor  300  in  FIG.  11    also illustrates the gate fingers  316 , the gate jumpers  372 , the gate signal distribution bars  374 , the series gate resistors  380  and the odd mode resistors  390 . 
     The transistors according to embodiments of the inventive concepts may include a semiconductor structure that is a multiple layer structure. For example, as discussed above with reference to  FIG.  7   , the semiconductor structure  120  of transistor  100  may include a substrate  200  (e.g., 4H—SiC or 6H—SiC) that has at least a channel layer  210  and a barrier layer  220  formed thereon. The same is true with respect to the other transistors according to embodiments of the inventive concepts that are depicted herein. Thus, while it will be appreciated that the discussion of the semiconductor structure  120  in  FIG.  7    applies equally to the semiconductor structures of each of the other embodiments described herein, although the metallization and other aspects of the device will vary based on the differences between the various embodiments depicted in the figures. Thus, for example, it will be appreciated that all of the transistors described herein may include silicon carbide substrates and Group III-nitride based channel and barrier layers, and that the semiconductor structures of these transistors may operate in the manner described with reference to  FIG.  7   . 
       FIG.  12    is a plan view of a metal layout of a transistor  400  in accordance with further embodiments of the inventive concepts. The transistor  400  is similar to the transistor  300  discussed above with reference to  FIGS.  8 - 11   , except that the transistor  400  uses a series gate resistors  80  that are connected between each gate pad  312  and a respective gate bus  314  instead of the distributed series gate resistors  380  that are included in the transistor  300 . Since aside from this change the two transistors  300 ,  400  may otherwise be essentially identical, further discussion of the transistor  400  will be omitted. 
       FIG.  13    is a plan view of a metal layout of a transistor  500  in accordance with still further embodiments of the inventive concepts. The transistor  500  is also similar to the transistor  300  discussed above with reference to  FIGS.  8 - 11   , except that the transistor  500  uses a single odd mode resistor  90  between each pair of adjacent gate buses  314  and does not include the distributed odd mode resistors  390  that are provided in the gap regions  384   b ,  384   c  in transistor  300  of  FIG.  8   . Since aside from this change the two transistors  300 ,  500  may otherwise be essentially identical, further discussion of the transistor  500  will be omitted. 
     It will be appreciated that features of the above-described embodiments may be combined in any way to create a plurality of additional embodiments. For example,  FIG.  14    is a plan view of a metal layout of a transistor  100 ′ that is identical to the transistor  100  described above, except that it has been modified to include series gate resistors  180  that may be identical to the series gate resistors  380  of  FIG.  8   . As another example,  FIG.  15    is a plan view of a metal layout of a transistor  300 ′ that is similar to the transistor  300  described above, except that the gate fingers  316  are no longer segmented, and the location of the series gate resistors  380  are modified accordingly. It will be appreciated that  FIGS.  14  and  15    are provided to illustrate a few of the possible combinations of the differnet embodiments that result in additional embodiments. 
     Embodiments of the inventive concepts may be particularly well suited for use in connection with Group III-nitride based high electron mobility transistor (HEMT) devices. As used herein, the term “Group III nitride” refers to those semiconducting compounds formed between nitrogen and the elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and/or indium (In). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds all have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements. 
     Suitable structures for GaN-based HEMTs that may utilize embodiments of the present invention are described, for example, in commonly assigned U.S. Publication No. 2002/0066908A1 published Jun. 6, 2002, for “Aluminum Gallium Nitride/Gallium Nitride High Electron Mobility Transistors Having A Gate Contact On A Gallium Nitride Based Cap Segment And Methods Of Fabricating Same,” U.S. Publication No. 2002/0167023A1 for “Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier/Spacer Layer,” published Nov. 14, 2002, U.S. Publication No. 2004/0061129 for “Nitride-Based Transistors And Methods Of Fabrication Thereof Using Non-Etched Contact Recesses,” published on Apr. 1, 2004, U.S. Pat. No. 7,906,799 for “Nitride-Based Transistors With A Protective Layer And A Low-Damage Recess” issued Mar. 15, 2011, and U.S. Pat. No. 6,316,793 entitled “Nitride Based Transistors On Semi-Insulating Silicon Carbide Substrates,” issued Nov. 13, 2001, the disclosures of which are hereby incorporated herein by reference in their entirety. 
     In particular embodiments of the present invention, the substrate  200  may be a semi-insulating silicon carbide (SiC) substrate that may be, for example, 4H polytype of silicon carbide. Other silicon carbide candidate polytypes include the 3C, 6H, and 15R polytypes. 
     Optional buffer, nucleation and/or transition layers (not shown) may be provided on the substrate  200  beneath the channel layer  210 . For example, an AIN buffer layer may be included to provide an appropriate crystal structure transition between the silicon carbide substrate and the remainder of the device. Additionally, strain balancing transition layer(s) may also be provided as described, for example, in commonly assigned U.S. Publication 2003/0102482A1, published Jun. 5, 2003, and entitled “Strain Balanced Nitride Hetrojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors,” the disclosure of which is incorporated herein by reference as if set forth fully herein. Moreover, one or more capping layers, such as SiN capping layers, may be provided on the barrier layer  220 . 
     Silicon carbide has a much closer crystal lattice match to Group III nitrides than does sapphire (Al 2 O 3 ), which is a very common substrate material for Group III nitride devices. The closer lattice match of SiC may result in Group III nitride films of higher quality than those generally available on sapphire. Silicon carbide also has a very high thermal conductivity so that the total output power of Group III nitride devices on silicon carbide is, typically, not as limited by thermal dissipation of the substrate as in the case of the same devices formed on sapphire. Also, the availability of semi-insulating silicon carbide substrates may provide for device isolation and reduced parasitic capacitance. Appropriate SiC substrates are manufactured by, for example, Cree, Inc., of Durham, N.C., the assignee of the present invention. 
     Although silicon carbide may be used as a substrate material, embodiments of the present invention may utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP and the like. In some embodiments, an appropriate buffer layer also may be formed. 
     In some embodiments of the present invention, the channel layer  210  is a Group III-nitride, such as Al x Ga 1−x N where 0≤x&lt;1, provided that the energy of the conduction band edge of the channel layer  210  is less than the energy of the conduction band edge of the barrier layer  220  at the interface between the channel and barrier layers. In certain embodiments of the present invention, x=0, indicating that the channel layer  210  is GaN. The channel layer  210  may also be other Group III-nitrides such as InGaN, AlInGaN or the like. The channel layer  210  may be undoped or unintentionally doped and may be grown to a thickness of greater than about 20 Å. The channel layer  210  may also be a multi-layer structure, such as a superlattice or combinations of GaN, AlGaN or the like. 
     The channel layer  210  may have a bandgap that is less than the bandgap of the barrier layer  220 , and the channel layer  210  may also have a larger electron affinity than the barrier layer  220 . In certain embodiments of the inventive concepts, the barrier layer  220  is AlN, AlInN, AlGaN or AlInGaN with a thickness of between about 0.1 nm and about 10 nm. In particular embodiments of the inventive concepts, the barrier layer  22  is thick enough and has a high enough Al composition and doping to induce a significant carrier concentration at the interface between the channel layer  210  and the barrier layer  220 . 
     The barrier layer  220  may be a Group III-nitride and has a bandgap larger than that of the channel layer  210  and a smaller electron affinity than the channel layer  210 . Accordingly, in certain embodiments of the present invention, the barrier layer  220  may include AlGaN, AlInGaN and/or AlN or combinations of layers thereof. The barrier layer  220  may, for example, be from about 0.1 nm to about 30 nm thick. In certain embodiments of the present invention, the barrier layer  220  is undoped or doped with an n-type dopant to a concentration less than about 10 19  cm −3 . In some embodiments of the present invention, the barrier layer  220  is Al x Ga 1−x N where 0&lt;x&lt;1. In particular embodiments, the aluminum concentration is about 25%. However, in other embodiments of the present invention, the barrier layer 220 comprises AlGaN with an aluminum concentration of between about 5% and about 100%. In specific embodiments of the present invention, the aluminum concentration is greater than about 10%. 
     While embodiments of the present invention are illustrated with reference to a GaN High Electron Mobility Transistor (HEMT) structure, the present inventive concepts are not limited to such devices. Thus, embodiments of the present invention may include other transistor devices having a plurality of unit cells and a controlling electrode. Embodiments of the present invention may be suitable for use in any semiconductor device where a wider controlling electrode is desired and multiple unit cells of the device are present. Thus, for example, embodiments of the present invention may be suitable for use in various types of devices, such as, MESFETs, MMICs, SITs, LDMOS, BJTs, pHEMTs, etc., fabricated using SiC, GaN, GaAs, silicon, etc. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” “comprising,” “includes” and/or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
     Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “lateral” or “vertical” may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. 
     Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. 
     In the drawings and specification, there have been disclosed typical embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.