Patent Publication Number: US-2023136654-A1

Title: Memory system and command determination method

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-177618, filed Oct. 29, 2021, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a memory system and a command determination method. 
     BACKGROUND 
     A solid state drive (SSD) including a NAND flash memory is one known example of a memory system. In SSDs, a technique of operating a plurality of memory chips connected to identical channels in parallel in bank units is adopted. This technique may be referred to as bank interleaving or the like. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a block diagram illustrating a memory system according to an embodiment. 
         FIG.  2    is a block diagram illustrating a controller  240 - 0  and a connection relationship between the controller  240 - 0  and memory chips  110   a ,  110   b , and  110   c.    
         FIG.  3    is a flowchart of a first command determination method according to an embodiment. 
         FIG.  4    is a flowchart of a second command determination method according to an embodiment. 
         FIG.  5    is a flowchart of a third command determination method according to an embodiment. 
         FIG.  6    depicts commands stored in a command queue according to an embodiment. 
         FIG.  7    depicts temporal changes of commands stored in a command queue according to an embodiment. 
         FIG.  8    depicts temporal changes of commands input to an arbiter according to an embodiment. 
         FIG.  9    is a timing chart illustrating an order of commands executed by a first command determination method according to an embodiment. 
         FIG.  10    is a timing chart illustrating an order of commands executed by a first command determination method according to a first comparative example. 
         FIG.  11    depicts commands stored in a command queue according to an embodiment. 
         FIG.  12    is a timing chart illustrating an order of commands executed by a first command determination method according to an embodiment. 
         FIG.  13    is a timing chart illustrating an order of commands executed by a command determination method according to a second comparative example. 
         FIG.  14    depicts commands stored in a command queue according to an embodiment. 
         FIG.  15    is a timing chart illustrating an order of commands executed by a fourth command determination method according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Certain embodiments provide a memory system and a command determination method capable of improving a processing capacity. 
     In general, according to one embodiment, a memory system includes a non-volatile memory including first and second memory chips both connected to a first channel. Each of the first and second memory chips is configured to output a first signal indicating whether the respective first or second memory chip is in a busy state. The memory system further includes a first queue that stores one or more commands to be executed by the first memory chip, a second queue that stores one or more commands to be executed by the second memory chip, and a processor. The processor is configured to issue a second signal indicating whether a command stored in the first or second queue is a first-type command or a second-type command, the first-type command causing the first or second memory chip to be in the busy state for longer than the second-type command. The memory system further includes a first arbiter configured to select from the first and second queues a command to be executed next based on the first and second signals, and a first memory interface controller configured to send the selected command to the first or second memory chip via the first channel. 
     Hereinafter, certain example embodiments will be described with reference to the drawings. 
       FIG.  1    is a block diagram of a memory system  1  according to an embodiment. The memory system  1  can be connected to a host device  2 . The memory system  1  can accept an access request (e.g., a read request, a write request, or the like) from the host device  2 . The communication of signals between the memory system  1  and the host device  2  is performed in accordance with, for example, PCIe, which is one of interface standards. The host device  2  is an information processing apparatus outside the memory system  1 . The host device  2  is, for example, an information processing apparatus such as a personal computer or a server, a tester device, a manufacturing apparatus, an imaging apparatus such as a still camera or a video camera, a mobile terminal such as a tablet computer or a smartphone, a game device, or an in-vehicle terminal such as a car navigation system. 
     The memory system  1  includes a non-volatile memory  100 , a memory controller  200 , a first channel ch 0 , a second channel ch 1 , a third channel ch 2 , and a fourth channel ch 3 . Hereinafter, when it is not necessary to distinguish between the first channel ch 0 , the second channel ch 1 , the third channel ch 2 , and the fourth channel ch 3 , those channels ch 0 -ch 3  are simply referred to as the channels ch. 
     The non-volatile memory  100  stores data non-volatilely. The non-volatile memory  100  is, for example, a NAND flash memory, a magnetoresistive random access memory (MRAM), a phase change random access memory (PRAM), a resistive random access memory (ReRAM), or a ferroelectric random access memory (FeRAM). 
     The memory controller  200  controls the non-volatile memory  100 . For example, the memory controller  200  writes data instructed to be written by the host device  2  into the non-volatile memory  100 , reads the data instructed to be read by the host device  2  from the non-volatile memory  100 , and transmits the read data to the host device  2 . 
     The channels ch are each a group of wirings. Each channel ch include one or more I/O signal lines and one or more control signal lines. An I/O signal line is, for example, a signal line for communication of data, an address, and a command. A control signal line is, for example, a signal line for communication of a write enable (WE) signal, a read enable (RE) signal, a command latch enable (CLE) signal, an address latch enable (ALE) signal, and a write protect (WP) signal. A chip enable signal is a signal for enabling a memory chip  110 , and is asserted at a low level in this example. 
     Next, an internal configuration of the non-volatile memory  100  will be described. The non-volatile memory  100  includes a plurality of banks (banks # 0 , # 1 , and # 2 ). When it is not necessary to distinguish between the banks # 0 , # 1 , and # 2 , those banks are simply referred to as banks #. 
     Each bank is a collection of a plurality of memory chips. The bank # 0  includes memory chips  110   a ,  110   d ,  110   g , and  110   j . The bank # 1  includes memory chips  110   b ,  110   e ,  110   h , and  110   k . The bank # 2  includes memory chips  110   c ,  110   f ,  110   i , and  110   l . Hereinafter, when it is not necessary to distinguish between the memory chips  110   a  to  110   l , the memory chips are simply referred to as the memory chips  110  or the memory chips. 
     The memory chip  110  is an integrated circuit (IC) chip including a plurality of non-volatile elements. The memory chip  110  writes data and reads data in units called pages including, for example, a plurality of memory cells. A unique physical address is assigned to each page. 
     Next, an internal configuration of the memory controller  200  will be described. The memory controller  200  includes a random access memory (RAM)  210 , a read only memory (ROM)  220 , a host interface (I/F)  230 , and a plurality of controllers  240 - 0 ,  240 - 1 ,  240 - 2 , and  240 - 3 , and a processor  250 . The memory controller  200  is configured as, for example, a system-on-a-chip (SoC) or a plurality of chips. Hereinafter, when it is not necessary to distinguish between the controllers  240 - 0 ,  240 - 1 ,  240 - 2 , and  240 - 3 , those controllers are simply referred to as the controllers  240 . The RAM  210 , the ROM  220 , the host interface  230 , the controllers  240 , and the processor  250  are connected to each other by a bus. One or more of the RAM  210 , the ROM  220 , the host I/F  230 , the controllers  240 , and the processor  250  may be disposed outside the memory controller  200 . 
     The RAM  210  functions as a cache, a buffer, and a working area. The RAM  210  is, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), or a combination of the DRAM and the SRAM. Data received from the host device  2  is stored in the RAM  210 . Further, data read from the non-volatile memory  100  is stored in the RAM  210 . The RAM  210  may be provided outside the memory controller  200 . 
     The ROM  220  is a memory to which new information cannot be written. The ROM  220  stores, for example, firmware used by the processor  250 . The firmware is software including data and the like for a plurality of commands related to the memory chips  110 . The plurality of commands related to the memory chips  110  are, for example, a read sense command, a program command, a data-in command, and a data-out command. The firmware may be stored in the non-volatile memory  100 . 
     The host interface  230  is a circuit configured to execute communication with external devices. The host interface  230  performs communication of information (e.g., an access request, a response, and data) between the host device  2  and the memory controller  200 . 
     The controller  240  is hardware such as a control circuit for controlling the memory chips  110 . The controller  240 - 0  is connected to the memory chips  110   a ,  110   b , and  110   c  via the first channel ch 0 . The controller  240 - 1  is connected to the memory chips  110   d ,  110   e , and  110   f  via the second channel ch 1 . The controller  240 - 2  is connected to the memory chips  110   g ,  110   h , and  110   i  via the third channel ch 2 . The controller  240 - 3  is connected to the memory chips  110   j ,  110   k , and  110   l  via the fourth channel ch 3 . The controller  240 - 0  can operate a plurality of memory chips connected to the channel ch 0  in parallel (bank interleaving). The same applies to the controllers  240 - 1 ,  240 - 2 , and  240 - 3 . 
     The processor  250  is hardware for executing an instruction set recorded in software. The processor  250  is, for example, a central processing unit (CPU). The processor  250  controls the entire memory controller  200  by executing the firmware. 
     The firmware includes data necessary to generate a busy period signal indicating whether a busy period of the memory chip  110  that executes a read sense command is longer than a certain period. 
     In the same manner, the firmware includes data necessary to generate a busy period signal indicating whether a busy period of the memory chip  110  that executes a program command, a data-in command, or a data-out command is longer than a certain period. The busy period is a period of a state in which the memory chip  110  does not accept any command or instruction from the outside (e.g., the host device  2 ). 
     The processor  250  generates a busy period signal based on the data described above. The processor  250  issues the generated busy period signal. 
     A time for a read sense command or a program command transmitted to the memory chip  110  to occupy the I/O signal line is shorter than a time for a data-in command or a data-out command transmitted to the memory chip  110  to occupy the I/O signal line. 
     A busy period required for the memory chip  110  to execute a read sense command or a program command is longer than a busy period required for the memory chip  110  to execute a data-in command and a data-out command. 
       FIG.  2    is a block diagram illustrating the controller  240 - 0  and a connection relationship between the controller  240 - 0  and the memory chips  110   a  to  110   c . The configurations of the controllers  240 - 0  to  240 - 3  are the same. Further, the configurations of the memory chips  110   a  to  110   l  are the same. Therefore, description for a configuration of a controller not illustrated in  FIG.  2    and description for a connection relationship between the controller and a memory chip not illustrated in  FIG.  2    will be omitted. 
     The memory chip  110   a  of the bank # 0 , the memory chip  110   b  of the bank # 1 , and the memory chip  110   c  of the bank # 2  connected to the controller  240 - 0  share one I/O signal line. That is, a plurality of memory chips  110  connected to the same channel ch are connected to one I/O signal line. 
     The memory chip  110   a  outputs a ready/busy signal Ry/By- 0  indicating whether the memory chip  110   a  is in a busy state or a ready state in which an instruction is acceptable from the outside. The memory chip  110   b  outputs a ready/busy signal Ry/By- 1  indicating whether the memory chip  110   b  is in the busy state or the ready state. The memory chip  110   c  outputs a ready/busy signal Ry/By- 1  indicating whether the memory chip  110   c  is in the busy state or the ready state. Hereinafter, when it is not necessary to distinguish between the signals Ry/By- 0 , Ry/By- 1 , and Ry/By- 2 , those signals Ry/By- 0 , Ry/By- 1 , and Ry/By- 2  are simply referred to as Ry/By #. 
     The controller  240 - 0  includes a queue unit  241 , an arbiter  242 , and a memory interface (I/F) controller  243 . 
     The queue unit  241  includes three command queues  241 - 0 ,  241 - 1 , and  241 - 2 , corresponding to the three banks # 0 , # 1 , and # 2  (three memory chips  110   a ,  110   b , and  110   c ). The command queues  241 - 0 ,  241 - 1 , and  241 - 2  have a one-to-one correspondence with the banks # 0 , # 1 , and # 2 . Hereinafter, when it is not necessary to distinguish between the command queues  241 - 0 ,  241 - 1 , and  241 - 2 , these command queues are referred to as the command queues  241 -#. Each command queue  241 -# has a queue structure capable of storing a plurality of commands. The queue structure is, for example, a first-in first-out (FIFO) structure or a first-in, last-out (FILO) structure. A command queue  241 -# stores either or both of a command having a period of being in a busy state longer than a certain period or a command having a period of being in the busy state less than or equal to the certain period. Hereinafter, a period of being in the busy state is referred to as a busy period. A command having a busy period longer than the certain period is called a first command (first-type command). A command having a busy period equal to or less than the certain period is called a second command (second-type command). 
     The command queue  241 - 0  stores commands to be executed by the memory chip  110   a  of the bank # 0 . The commands are issued by the processor  250 . The commands are stored in the command queue  241 - 0  in the reception order. 
     The command queue  241 - 1  stores commands to be executed by the memory chip  110   b  of the bank # 1 . The commands are issued by the processor  250 . The commands are stored in the command queue  241 - 1  in the reception order. 
     The command queue  241 - 2  stores commands to be executed by the memory chip  110   c  of the bank # 2 . The commands are issued by the processor  250 . The commands are stored in the command queue  241 - 2  in the reception order. 
     The arbiter  242  is a processing circuit or a processor connected to the command queues  241 -#. The command queue  241 - 0  outputs the command stored at its head. This output command is input to the arbiter  242 . The command queue  241 - 1  outputs the command stored at its head. This output command is input to the arbiter  242 . The command queue  241 - 2  outputs the command stored at its head. This output command is input to the arbiter  242 . 
     The ready/busy signal Ry/By- 0  output from the memory chip  110   a , the ready/busy signal Ry/By- 1  output from the memory chip  110   b , and the ready/busy signal Ry/By- 2  output from the memory chip  110   c  are input to the arbiter  242 . A busy period signal Sa generated by the processor  250  is also input to the arbiter  242 . 
     Based on the ready/busy signal Ry/By- 0 , the ready/busy signal Ry/By- 1 , the ready/busy signal Ry/By- 2 , and the busy period signal Sa, the arbiter  242  determines which of the commands from the command queues  241 - 0 ,  241 - 1 , and  241 - 2  is to be executed next by the memory chip  110  according to a command determination method, which will be described below. 
     The arbiter  242  issues a signal Sb to the memory interface controller  243 . When a first command is selected according to the command determination method, the signal Sb includes information indicating the first command. The signal Sb including the information indicating a first command is referred to as a signal Sb 1 . Further, when a second command is selected according to the command determination method, the signal Sb includes information indicating the second command. The signal Sb including the information indicating a second command is referred to as a signal Sb 2 . 
     The memory interface controller  243  controls transmission and reception of data between the RAM  210  and the memory chip  110  based on the signal Sb. 
     When executing a read sense command, the memory interface controller  243  instructs the memory chip  110  to prepare for reading data. For example, when reading data from the memory chip  110   a  among the memory chips  110   a  to  110   c  of the channel ch 0 , a low-level chip enable signal is input to the memory chip  110   a , and a high-low level chip enable signal is input to the memory chips  110   b  and  110   c . The execution of the read sense command involves a waiting time. However, the execution of the read sense command does not involve occupation of the I/O signal line. 
     When executing a data-out command, the memory interface controller  243  reads the data prepared by the memory chip  110 . For example, when a low-level chip enable signal is input to the memory chip  110   a  and a high-low level chip enable signal is input to the memory chips  110   b  and  110   c , data can be read from the memory chip  110   a  by using one I/O signal line. The data-out command uses the I/O signal line. Therefore, the execution of the data-out command involves occupation of the I/O signal line. 
     When executing a data-in command, the memory interface controller  243  instructs the memory chip  110  to prepare for writing data. For example, when data is written to the memory chip  110   a  among the memory chips  110   a ,  110   b , and  110   c  of the channel ch 0 , a low-level chip enable signal is input to the memory chip  110   a , and a high-low level chip enable signal is input to the memory chips  110   b  and  110   c . The data-in command uses the I/O signal line. Therefore, the execution of the data-in command involves occupation of the I/O signal line. 
     When executing a program command, the memory interface controller  243  writes the data prepared by the memory chip  110  to the memory chip. For example, when a low-level chip enable signal is input to the memory chip  110   a  and a high-low level chip enable signal is input to the memory chips  110   b  and  110   c , data can be written into the memory chip  110   a  by using one I/O signal line. The execution of the program command involves a waiting time. However, the execution of the program command does not involve occupation of the I/O signal line. 
     Next, a first command determination method according to an embodiment performed by the arbiter  242  will be described.  FIG.  3    is a flowchart of the first command determination method according to an embodiment. The first command determination method is a method of determining a command to be executed next among commands stored in the command queue  241 -#. 
     The arbiter  242  determines whether a first command exists in the command queue  241 -# based on the busy period signal Sa (S 1 ). 
     When the first command exists in the command queue  241 -# (Yes in S 1 ), the arbiter  242  executes a second command determination method (S 2 ). The second command determination method is a method of determining whether a first command which is executable is stored in the command queue  241 -#. 
     After the execution of the second command determination method is completed, the arbiter  242  determines whether there is a first command that is to be executed with priority over a second command (S 3 ). 
     When there is a first command to be executed with priority over a second command (Yes in S 3 ), the arbiter  242  issues a signal Sb 1  to the memory interface controller  243 . Upon receiving the signal Sb 1 , the memory interface controller  243  causes the memory chip  110  to execute the first command (S 4 ). The case where a first command to be executed with priority over a second command exists is a case where a process (S 13 ) which will be described below is executed. 
     After the execution of the first command (S 4 ), the arbiter  242  ends the first command determination method (end). 
     When a first command does not exist in the command queue  241 -# (No in S 1 ), or when a first command exists in the command queue  241 -# but is not a first command to be executed with priority over a second command (No in S 3 ), the arbiter  242  determines whether a second command exists in the command queue  241 -# based on a busy period signal Sa (S 5 ). The case where a first command to be executed with priority over a second command is not present in the command queue  241 -# is a case of Yes in a process (S 14 ) which will be described below. 
     When a second command exists in the command queue  241 -# (Yes in S 5 ), the arbiter  242  executes a third command determination method (S 6 ). The third command determination method is a method of determining whether a second command which is executable is stored in the command queue  241 -#. 
     After the execution of the third command determination method is completed, the arbiter  242  determines whether a second command to be executed exists in the command queue  241 -# (S 7 ). 
     When a second command to be executed exists in the command queue  241 -# (Yes in S 7 ), the arbiter  242  issues a signal Sb 2  to the memory interface controller  243 . Upon receiving the signal Sb 2 , the memory interface controller  243  causes the memory chip  110  to execute the second command (S 8 ). The case where a second command to be executed exists is a case where a process (S 23 ) which will be described below is executed. 
     After the execution of the second command (S 8 ), the arbiter  242  ends the first command determination method (end). 
     When a second command is not in the command queue  241 -# (No in S 5 ), the arbiter  242  next determines whether a first command is present (S 1 ). 
     When a second command to be executed is not in the command queue  241 -# (No in S 7 ), the arbiter  242  next determines whether a first command is present in the command queue  241 -# (S 1 ). The case where a second command to be executed is not present is a case of Yes in a process (S 24 ) which will be described below. 
     Next, the second command determination method will be described.  FIG.  4    is a flowchart of the second command determination method according to an embodiment. 
     The arbiter  242  selects one bank # according to an order of circulation using, for example, a round robin method (S 11 ). 
     Next, the arbiter  242  determines whether a memory chip of the selected bank # is in a busy state based on the ready/busy signal Ry/By # (S 12 ). 
     When the memory chip of the selected bank # is not in the busy state (No in S 12 ), the arbiter  242  selects a first command as a command to be executed by the memory chip of the selected bank # (S 13 ). 
     When the first command is selected to be executed by the memory chip of the selected bank # (S 13 ), the arbiter  242  ends the second command determination method (end). 
     When the memory chip of the selected bank # is in the busy state (Yes in S 12 ), the arbiter  242  determines whether the busy state of the memory chip has been checked for all the banks other than the selected bank # (S 14 ). 
     When the busy state of a memory chip is not yet checked for all the other banks besides the selected bank # (No in S 14 ), the arbiter  242  selects another bank # (S 11 ). 
     When the busy state of the memory chip has been checked for all the banks other than the selected bank # (Yes in S 14 ), the arbiter  242  ends the second command determination method (end). 
     Next, the third command determination method will be described.  FIG.  5    is a flowchart of the third command determination method according to an embodiment. 
     The arbiter  242  selects one bank # according to an order of circulation using a round robin method or the like (S 21 ). 
     Next, the arbiter  242  determines whether a memory chip of the selected bank # is in a busy state based on the ready/busy signal Ry/By # (S 22 ). 
     When the memory chip of the selected bank # is not in the busy state (No in S 22 ), the arbiter  242  selects a second command as a command to be executed by the memory chip of the selected bank # (S 23 ). 
     When the second command is selected to be executed by the memory chip of the selected bank # (S 23 ), the arbiter  242  ends the third command determination method (end). 
     When the memory chip of the selected bank # is in the busy state (Yes in S 22 ), the arbiter  242  determines whether the busy state of the memory chip has been checked for all the banks other than the selected bank # (S 24 ). 
     When the busy state of the memory chip has not been checked for all the banks # other than the selected bank #(No in S 24 ), the arbiter  242  selects another bank # (S 21 ). 
     When the busy state of the memory chip has been checked for all the banks # other than the selected bank # (Yes in S 24 ), the arbiter  242  ends the third command determination method (end). 
     Next, the first command determination method according to an embodiment will be described using an example scenario.  FIG.  6    depicts commands stored in the command queue  241 - 0 , the command queue  241 - 1 , and the command queue  241 - 2 . In  FIG.  6   , the notation “Rs” indicates a read sense command, “Do” indicates a data-out command, “Di” indicates a data-in command, and “Pr” indicates a program command. 
       FIG.  7    depicts temporal changes of the commands stored in the command queue  241 - 0 , the command queue  241 - 1 , and the command queue  241 - 2 . For the sake of simplicity, the reference numerals  241 - 0 ,  241 - 1 , and  241 - 2  are omitted in parts (b)-(l) of  FIG.  7   . 
       FIG.  8    depicts temporal changes of commands input to the arbiter  242 . For the sake of simplicity, the reference numeral  242  is omitted in parts (b)-(l) of  FIG.  8   . In (b)-( 1 ) of  FIG.  8   , a command in a hatched entry is a command selected by the arbiter  242  as a command to be preferentially executed. 
       FIG.  9    is a timing chart illustrating an order of commands executed by the first command determination method according to an embodiment. In  FIG.  9   , the notation “tR” indicates a period (a waiting time) in which a memory chip that executes read sense command (Rs) is in a busy state, and “tP” indicates a period during which a memory chip that executes a program command (Pr) is in the busy state. Furthermore,  FIG.  9    illustrates a timing chart of signals flowing in an I/O signal line, corresponding to the various commands: read sense command (Rs), data-in command (Do), data-in command (Di), and program command (Pr). 
     As illustrated in  FIG.  6   , a read sense command (Rs) (which is first-type command) is stored at a head of the command queue  241 - 0 , read sense command (Rs) is stored at a head of the command queue  241 - 1 , and a data-in command (Di) (which is a second-type command) is stored at a head of the command queue  241 - 2 . As a result, Rs, Rs, and Di are input to the arbiter  242 , as illustrated in (a) of  FIG.  8   . 
     The arbiter  242  performs the process in S 1 , the process in S 2 , and the process in S 3  in  FIG.  3   . As a result, as illustrated in (a) of  FIG.  8   , the read sense command (Rs) in the upper stage of the depicted arbiter  242  is selected as the command to be executed. The selected command (Rs) is executed by the memory chip of the bank # 0  as shown in  FIG.  9   . 
     After that, as illustrated in (b) of  FIG.  7   , the command at the head of the command queue  241 - 0  is a data-out command (Do) (which is a second-type command), the command at the head of the command queue  241 - 1  is read sense command (Rs), and the command at the head of the command queue  241 - 2  is a data-in command (Di)). As a result, Do, Rs, and Di are input to the arbiter  242 , as illustrated in (b) of  FIG.  8   . 
     The arbiter  242  performs the process in S 1 , the process in S 2 , and the process S 3  in  FIG.  3   . As a result, as illustrated in (b) of  FIG.  8   , Rs in the middle stage of the depicted arbiter  242  is selected as the command to be executed. This selected command (Rs) is executed by the memory chip of the bank # 1  as shown in  FIG.  9   . 
     After that, as illustrated in (c) of  FIG.  7   , the command at the head of the command queue  241 - 0  is a data-out command (Do), the command at the head of the command queue  241 - 1  is a data-out command (Do), and the command at the head of the command queue  241 - 2  is a data-in command (Di). As a result, Do, Do, and Di are input to the arbiter  242 , as illustrated in (c) of  FIG.  8   . 
     The arbiter  242  performs the process in S 1 , the process in S 5 , the process in S 6 , and the process in S 7  in  FIG.  3   . As a result, as illustrated in (c) of  FIG.  8   , data-in command (Di) at the lower stage of the depicted arbiter  242  is selected as the command to be executed. The selected command (Di) is executed by the memory chip of the bank # 2  as shown in  FIG.  9   . 
     After that, as illustrated in (d) of  FIG.  7   , the command at the head of the command queue  241 - 0  is a data-out command (Do), the command at the head of the command queue  241 - 1  is also a data-out command (Do), and the command at the head of the command queue  241 - 2  is a program command (Pr) (which is a first-type command). As a result, Do, Do, and Pr are input to the arbiter  242 , as illustrated in (d) of  FIG.  8   . 
     The arbiter  242  performs the process in S 1 , the process in S 2 , and the process S 3  in  FIG.  3   . As a result, as illustrated in (d) of  FIG.  8   , the program command (Pr) is selected as the command to be executed. The selected command (Pr) is executed by the memory chip of the bank # 2  as shown in  FIG.  9   . 
     After that, as illustrated in (e) of  FIG.  7   , the command at the head of the command queue  241 - 0  is a data-out command (Do), the command at the head of the command queue  241 - 1  is also a data-out command (Do), and the command at the head of the command queue  241 - 2  is a read sense command (Rs). As a result, Do, Do, and Rs are input to the arbiter  242 , as illustrated in (e) of  FIG.  8   . 
     The arbiter  242  performs the process in S 1 , the process in S 2 , the process in S 3 , the process in S 5 , the process in S 6 , and the process in S 7  in  FIG.  3   . As a result, as illustrated in (e) of  FIG.  8   , the data-out command Do in the upper stage of the depicted arbiter  242  is selected as the command to be executed. The selected command (Do) is executed by the memory chip of the bank # 0  as shown in  FIG.  9   . 
     After that, as illustrated in (f) of  FIG.  7   , the command at the head of the command queue  241 - 0  is a read sense command (Rs), the command at the head of the command queue  241 - 1  is a data-out command (Do), and the command at the head of the command queue  241 - 2  is another read sense command (Rs). As a result, Rs, Do, and Rs are input to the arbiter  242 , as illustrated in (f) of  FIG.  8   . 
     The arbiter  242  performs the process in S 1 , the process in S 2 , and the process in S 3  in  FIG.  3   . As a result, as illustrated in (f) of  FIG.  8   , the Rs at the upper stage (corresponding to Rs at the head of the command queue  241 - 0  in (f) of  FIG.  7   ) is selected as the command to be executed. The selected command (Rs) is executed by the memory chip of the bank # 0  as shown in  FIG.  9   . 
     After that, as illustrated in (g) of  FIG.  7   , the command at the head of the command queue  241 - 0  is Do, the command at the head of the command queue  241 - 1  is Do, and the command at the head of the command queue  241 - 2  is Rs. As a result, Do, Do, and Rs are input to the arbiter  242 , as illustrated in (g) of  FIG.  8   . 
     The arbiter  242  performs the process in S 1 , the process in S 2 , the process in S 3 , the process in S 5 , the process in S 6 , and the process in S 7  in  FIG.  3   . As a result, as illustrated in (g) of  FIG.  8   , the data-out command (Do) at a middle stage of the depicted arbiter  242  is selected as the command to be executed. The selected command (Do) is executed by the memory chip of the bank # 1  as shown in  FIG.  9   . 
     After that, as illustrated in (h) of  FIG.  7   , the command at the head of the command queue  241 - 0  is Do, the command at the head of the command queue  241 - 1  is Di, and the command at the head of the command queue  241 - 2  is Rs. As a result, Do, Di, and Rs are input to the arbiter  242 , as illustrated in (h) of  FIG.  8   . 
     The arbiter  242  performs the process in S 1 , the process in S 2 , and the process in S 3  in  FIG.  3   . As a result, as illustrated in (h) of  FIG.  8   , read sense command (Rs) is selected as the command to be executed. The selected command (Rs) is executed by the memory chip of the bank # 2  as shown in  FIG.  9   . 
     After that, as illustrated in (i) of  FIG.  7   , the command at the head of the command queue  241 - 0  is Do, the command at the head of the command queue  241 - 1  is Di, and the command at the head of the command queue  241 - 2  is Do. As a result, Do, Di, and Do are input to the arbiter  242 , as illustrated in (i) of  FIG.  8   . 
     The arbiter  242  performs the process in S 1 , the process in S 5 , the process in S 6 , and the process in S 7  in  FIG.  3   . As a result, as illustrated in (i) of  FIG.  8   , data-in command (Di) is selected as the command to be executed. The selected command (Di) is executed by the memory chip of the bank # 1  as shown in  FIG.  9   . 
     After that, as illustrated in (j) of  FIG.  7   , the command at the head of the command queue  241 - 0  is Do, the command at the head of the command queue  241 - 1  is Pr, and the command at the head of the command queue  241 - 2  is Do. As a result, Do, Pr, and Do are input to the arbiter  242 , as illustrated in (j) of  FIG.  8   . 
     The arbiter  242  performs (the process in S 1  and the process in S 2 ), and the process in S 3  in  FIG.  3   . As a result, as illustrated in  FIG.  8 ( j ) , Pr is selected as the command to be executed. The selected command (Pr) is executed by the memory chip of the bank # 1  ( FIG.  9   ). 
     After that, as illustrated in (k) of  FIG.  7   , the command at the head of the command queue  241 - 0  is Do, the command at the head of the command queue  241 - 1  is null (i.e., there is no command), and the command at the head of the command queue  241 - 2  is Do. As a result, Do, null, and Do are input to the arbiter  242 , as illustrated in (k) of  FIG.  8   . 
     The arbiter  242  performs the process in S 1 , the process in S 5 , the process in S 6 , and the process in S 7  in  FIG.  3   . As a result, as illustrated in (k) of  FIG.  8   , the data-out command (Do) of the lower stage is selected as the command to be executed. The selected command (Do) is executed by the memory chip of the bank # 2  as shown in  FIG.  9   . 
     After that, as illustrated in ( 1 ) of  FIG.  7   , the command at the head of the command queue  241 - 0  is Do, the command at the head of the command queue  241 - 1  is null, and the command at the head of the command queue  241 - 2  is also null. As a result, only Do (or, alternatively, Do, null, null) is input to the arbiter  242 , as illustrated in ( 1 ) of  FIG.  8   . 
     The arbiter  242  performs the process in S 1 , the process in S 5 , the process in S 6 , and the process in S 7  in  FIG.  3   . As a result, as illustrated in ( 1 ) of  FIG.  8   , data-out command (Do) is selected as the command to be executed. The selected command (Do) is executed by the memory chip of the bank # 0  as shown in  FIG.  9   . 
     By adopting the command determination method of preferentially executing a first-type command (which is a command having a long busy period), as illustrated in  FIG.  9   , a plurality of command signals can be continuously input over one I/O signal line without interruption. Therefore, according to the above-described embodiments, it is possible to improve the processing capacity of a memory system while also reducing the power consumption of the memory system. 
     Next, a command determination method according to a first comparative example will be described.  FIG.  10    is a timing chart illustrating an order of commands executed by the command determination method according to the first comparative example. The command determination method according to the first comparative example is different from the first command determination method according to the above-described embodiments in that the method of preferentially executing a first-type command is not adopted. As illustrated in  FIG.  10   , in the command determination method according to the first comparative example, a period during which no command signal is input through an I/O signal line (a period with shaded-hatching) occurs. 
       FIG.  11    is a diagram illustrating another example of commands stored in the queue unit  241  (i.e., the command queues  241 - 0 ,  241 - 1 , and  241 - 2 ).  FIG.  11    corresponds to  FIG.  6   . In  FIG.  11   , the notation “Rs” indicates a read sense command (a first-type command), “Do” indicates a data-out command (a second-type command), “Di” indicates a data-in command (a second-type command), “Er” indicates an erase command (a first-type command), and “St” is a status read command (a second-type command). 
     The time required for a read sense command or an erase command transmitted to the memory chip  110  to occupy an I/O signal line is shorter than the time required for a data-in command, a data-out command, or a status read command transmitted to the memory chip  110  to occupy the I/O signal line. 
     The busy period required for the memory chip  110  to execute the read sense command or the erase command is longer than the busy period required for the memory chip  110  to execute the data-in command, the data-out command, or the status read command. 
       FIG.  12    is another timing chart illustrating the order of the commands executed by the first command determination method according to an embodiment.  FIG.  12    corresponds to  FIG.  9   . As illustrated in  FIG.  12   , a plurality of command signals can be continuously input to one I/O signal line without interruption. Therefore, it is possible to improve a processing capacity and reduce power consumption of the memory system. 
       FIG.  13    is another timing chart illustrating an order of commands executed by a command determination method according to a second comparative example. The command determination method according to the second comparative example is different from the first command determination method according to the present embodiment in that the method of preferentially executing a first-type command is not adopted. As illustrated in  FIG.  13   , in the command determination method according to the second comparative example, three periods during which no command signal is input to the I/O signal line occur and these periods are indicated in the figure with shaded-hatching. 
       FIG.  14    is a diagram illustrating another example of the commands stored in the command queue  241 - 0 , the command queue  241 - 1 , and the command queue  241 - 2  according to an embodiment. In  FIG.  14   , the command queue  241 - 0  and the command queue  241 - 1  both have entries for which no command is stored. 
     Next, the second command determination method according to an embodiment will be described.  FIG.  15    is a timing chart illustrating an order of commands executed by the second command determination method. 
     The second command determination method according to an embodiment is different from the first command determination method according to the above-described embodiments in that selection of a bank from other than a specific bank is temporarily prohibited. In  FIG.  15   , during a period T-lock, the bank # 2  is selected and the banks # 0  and # 1  are not selected. Even if the second command determination method according to this embodiment is used, a plurality of command signals can still be continuously input to the I/O signal line without interruption. Therefore, it is possible to improve a processing capacity and reduce power consumption of the memory system. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.