Patent Publication Number: US-2023153194-A1

Title: Semiconductor device

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2021-0158952, filed in the Korean Intellectual Property Office on Nov. 17, 2021, the entire disclosure of which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     The present disclosure relates to a semiconductor device capable of correcting an error of a codeword that is stored in a memory cell. 
     Recently, in order to increase the operation speed of a semiconductor device, a method for inputting/outputting multi-bit data in each clock cycle is used. Examples of the method include DDR 2 , DDR 3 , DDR 4 , and DDR 5  methods. When the input/output speed of data is increased, the probability that an error will occur while the data are transmitted is also increased. Therefore, a separate device and method for guaranteeing the reliability of data transmission are additionally required. 
     According to a method for guaranteeing the reliability of data transmission, an error check code that makes it possible to check whether an error has occurred may be generated and transmitted with data, whenever the data is transmitted. Examples of the error check code may include an error detection code (EDC) capable of detecting an occurrence of error, and an error correction code (ECC) capable of correcting an error when the error has occurred. 
     SUMMARY 
     In an embodiment, a semiconductor device may include: an error check execution signal generation circuit configured to generate an error check execution signal for performing an error check operation when an ECS (Error Check and Scrub) command that is generated based on a refresh command is input; and an ECS control circuit configured to generate an ECS active command and an ECS read command for performing the error check operation based on the ECS command and the error check execution signal, and successively generate the ECS read commands to perform the error check operation. 
     In another embodiment, a semiconductor device may include: an ECS control circuit configured to generate an ECS active command for performing an error check operation based on an ECS command and an error check execution signal, and then successively generate ECS read commands; and a select address generation circuit configured to output, during the error check operation, as a select row address and a select column address, a row address and a column address that are sequentially counted whenever the ECS active command and the ECS read command are input, and store the counted row address and column address when an error flag signal is input. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a block diagram illustrating a configuration of a memory device in accordance with an embodiment. 
         FIG.  2    is a block diagram illustrating a configuration based on an example of an ECS (Error Check and Scrub) command generation circuit included in the semiconductor device illustrated in  FIG.  1   . 
         FIG.  3    is a circuit diagram illustrating a configuration based on an example of a check flag signal generation circuit included in the semiconductor device illustrated in  FIG.  1   . 
         FIG.  4    is a block diagram illustrating a configuration based on an example of an ECS control circuit included in the semiconductor device illustrated in  FIG.  1   . 
         FIG.  5    is a block diagram illustrating a configuration based on an example of a clock code generation circuit included in the ECS control circuit illustrated in  FIG.  4   . 
         FIG.  6    is a circuit diagram illustrating a configuration based on an example of an ECS mode signal generation circuit included in the clock code generation circuit illustrated in  FIG.  5   . 
         FIG.  7    is a circuit diagram illustrating a configuration based on an example of an oscillation signal generation circuit included in the clock code generation circuit illustrated in  FIG.  5   . 
         FIG.  8    is a block diagram illustrating a configuration based on an example of a select address generation circuit included in the semiconductor device illustrated in  FIG.  1   . 
         FIG.  9    is a block diagram illustrating configurations of a memory bank and a sensing amplification circuit, which are included in the semiconductor device illustrated in  FIG.  1   . 
         FIGS.  10  to  13    are timing diagrams for describing an error check operation and ECS operation of the semiconductor device in accordance with the present embodiment. 
         FIG.  14    is a diagram illustrating a configuration of an electronic system in accordance with an embodiment to which the semiconductor device illustrated in  FIGS.  1  to  13    is applied. 
     
    
    
     DETAILED DESCRIPTION 
     In the descriptions of the following embodiments, the term “preset” indicates that the numerical value of a parameter is previously decided, when the parameter is used in a process or algorithm. According to an embodiment, the numerical value of the parameter may be set when the process or algorithm is started or while the process or algorithm is performed. 
     Terms such as “first” and “second”, which are used to distinguish among various components, are not limited by the components. For example, a first component may be referred to as a second component, and vice versa. 
     When one component is referred to as being “coupled” or “connected” to another component, it should be understood that the components may be directly coupled or connected to each other or coupled or connected to each other through another component interposed therebetween. On the other hand, when one component is referred to as being “directly coupled” or “directly connected” to another component, it should be understood that the components are directly coupled or connected to each other without another component interposed there between. 
     “Logic high level” and “logic low level” are used to describe the logic levels of signals. A signal with “logic high level” is distinguished from a signal with “logic low level.” For example, when a signal with a first voltage corresponds to a signal with a “logic high level,” a signal with a second voltage may correspond to a signal with a “logic low level.” According to an embodiment, a “logic high level” may be set to a voltage higher than a “logic low level.” According to an embodiment, the logic levels of signals may be set to different logic levels or opposite logic levels. For example, a signal with a logic high level may be set to have a logic low level according to an embodiment, and a signal with a logic low level may be set to have a logic high level according to an embodiment. 
     Hereafter, the teachings of the present disclosure will be described in more detail through embodiments. The embodiments are only used to exemplify the teachings of the present disclosure, and the scope of the present disclosure is not limited by the embodiments. 
     Some embodiments of the present disclosure are directed to a semiconductor device that performs an operation of correcting errors of codewords that are stored in memory cells, and storing the error-corrected codewords in the memory cells. 
     In accordance with some embodiments, the semiconductor device may perform the ECS operation that performs an error check operation of detecting errors of codewords that are stored in memory cells, correcting the errors of the codewords, and re-storing the codewords. Thus, the semiconductor device may perform the ECS operation that is capable of correcting the errors of the codewords that are stored in the memory cells, and re-storing the error-corrected codewords in the memory cells. 
     Furthermore, in accordance with some embodiments, the semiconductor device may perform the error check operation of detecting errors of the codewords that are stored in the memory cells, and then may perform the ECS operation only on an area in which the codeword that contains an error is stored, thereby reducing power consumption. 
       FIG.  1    is a block diagram illustrating a configuration of a semiconductor device  10  in accordance with an embodiment. The semiconductor device  10  may include a command decoder  101 , an ECS (Error Check and Scrub) command generation circuit  103 , an error check execution signal generation circuit  105 , a check flag signal generation circuit  107 , an ECS control circuit  109 , a select address generation circuit  111 , a memory bank  131 , a sensing amplification circuit  133 , a row control circuit  151 , a column control circuit  153 , an input/output control circuit  155 , an error correction circuit  170 , and a data buffer  190 . 
     The command decoder  101  may generate a refresh command REF by decoding a command CMD. The command decoder  101  may generate the refresh command REF to perform a refresh operation. The command CMD may include a plurality of bits with a logic level combination for generating the refresh command REF. 
     The ECS command generation circuit  103  may generate an ECS command AECS based on the refresh command REF. The ECS command generation circuit  103  may generate the ECS command AECS whenever the refresh command REF is generated a preset number of times. For example, the ECS command generation circuit  103  may generate the ECS command AECS whenever the refresh command REF is generated K times. Here, K may be set to a natural number. 
     The error check execution signal generation circuit  105  may generate an error check execution signal ECS_EXE based on the ECS command AECS and a check flag signal CHK_FLAG. The error check execution signal generation circuit  105  may generate an error check execution signal ECS_EXE that is disabled during an initialization operation. The error check execution signal generation circuit  105  may generate the error check execution signal ECS_EXE that is enabled when the ECS command AECS is input thereto and the check flag signal CHK_FLAG is input thereto. The initialization operation may be set to a reset operation and a power-up period in which the semiconductor device  10  starts an operation. 
     The check flag signal generation circuit  107  may generate the check flag signal CHK_FLAG based on an error flag signal EFLAG and an initialization check signal INIT_CHK. The check flag signal generation circuit  107  may generate the check flag signal CHK_FLAG that is enabled when the error flag signal EFLAG is input thereto. The check flag signal generation circuit  107  may generate the check flag signal CHK_FLAG that is disabled when the initialization check signal INIT_CHK is input. 
     The ECS control circuit  109  may generate the initialization check signal INIT_CHK, an ECS active command EACT, an ECS read command ERD, an ECS write command EWT, an ECS precharge command EPCG, and an end signal END based on the ECS command AECS and the error check execution signal ECS_EXE. The ECS control circuit  109  may generate the initialization check signal INIT_CHK to disable the check flag signal CHK_FLAG. The ECS control circuit  109  may generate the ECS active command EACT for an ECS active operation. The ECS control circuit  109  may generate the ECS read command ERD for an error check operation and an ECS read operation. The ECS control circuit  109  may generate the ECS write command EWT for an ECS write operation. The ECS control circuit  109  may generate the ECS precharge command EPCG for a precharge operation of memory cells on which the error check operation and the ECS operation have been performed. The ECS control circuit  109  may generate the end signal END to end the error check operation and the ECS operation. 
     The ECS control circuit  109  may generate the initialization check signal INIT_CHK to disable the check flag signal CHK_FLAG. The ECS control circuit  109  may generate the initialization check signal INIT_CHK to disable the check flag signal CHK_FLAG after the ECS active command EACT, the ECS read command ERD, the ECS write command EWT, and the ECS precharge command EPCG are repeatedly generated a preset number of times. 
     The ECS control circuit  109  may generate the ECS active command EACT and thereafter repeatedly generate the ECS read command ERD to output the codewords CW that are stored in the memory cells, during a period in which the error check execution signal ECS_EXE is disabled. The ECS control circuit  109  may repeatedly generate the ECS read command ERD after generating the ECS active command EACT to determine whether each of the codewords CW that are stored in memory cells contains an error, during a period in which the error check execution signal ECS_EXE is disabled. During a period in which the error check execution signal ECS_EXE is enabled, the ECS control circuit  109  may sequentially generate the ECS active command EACT, the ECS read command ERD, the ECS write command EWT, the ECS precharge command EPCG, and the end signal END such that the ECS operation is performed on the memory cells in which the codewords CW that contain an error are stored. 
     The select address generation circuit  111  may generate a select column address SCADD and a select row address SRADD based on the ECS active command EACT, the ECS read command ERD, the ECS write command EWT, and the check flag signal CHK_FLAG. Whenever the ECS active command EACT and the ECS read command ERD are generated, the select address generation circuit  111  may sequentially generate the select column address SCADD and the select row address SRADD to access memory cells on which the ECS operation is performed. Whenever the ECS active command EACT and the ECS write command EWT are generated, the select address generation circuit  111  may sequentially generate the select column address SCADD and the select row address SRADD to access memory cells on which the ECS operation is performed. During an error check operation, the select address generation circuit  111  may store an address for accessing a memory cell in which the codeword CW that contains an error is stored. During a period in which the check flag signal CHK_FLAG is generated, the select address generation circuit  111  may output the stored address as the select row address SRADD and the select column command SCADD. The stored address may include a row address (RADD of  FIG.  8   ) and a column address (CADD of  FIG.  8   ). 
     The memory bank  131  may include memory cells, each of which is coupled to a word line and a bit line. One or more of word lines, coupled to the memory cells, included in the memory bank  131 , may be selected by the select row address SRADD. One or more of bit lines, coupled to the memory cells, included in the memory bank  131 , may be selected by the select column address SCADD. The memory cells, included in the memory bank  131 , may be accessed through one or more word lines and one or more bit lines, which are selected. The numbers of the word lines and the bits lines, which are coupled to the memory cells that are included in the memory bank  131 , may be set to various values in different embodiments. The codeword CW with data and parity may be stored in each of the memory cells that are included in the memory bank  131 . 
     The sensing amplification circuit  133  may include a plurality of sense amplifiers (not illustrated). The sense amplifiers that are included in the sensing amplification circuit  133  may be coupled to the bit lines, coupled to the memory cells, included in the memory bank  131 , and may sense and amplify data that is loaded on the bit lines. 
     The row control circuit  151  may select, as a row path, one or more of the word lines that are coupled to the memory cells that are included in the memory bank  131  and selected by the select row address SRADD. The row control circuit  151  may perform an ECS active operation that loads data and parities, stored in the memory cells of the row path that is selected by the select row address SRADD, onto bit lines such that the data and parities are sensed and amplified by the sensing amplification circuit  133 . 
     The column control circuit  153  may control the input/output control circuit  155  such that data are input to/output from sense amplifiers that are selected by the select column command SCADD, among the sense amplifiers that are coupled to the memory cells of the row path. The column control circuit  153  may control the input/output control circuit  155  to perform the ECS read operation and the ECS write operation on the memory cells that are coupled to the sense amplifiers that are selected by the select column command SCADD, among the memory cells that are included in the memory bank  131  on which the ECS active operation has been performed. 
     The input/output control circuit  155  may control the data input/output between the sensing amplification circuit  133  and the error correction circuit  170  based on the ECS read command ERD and the ECS write command EWT. The input/output control circuit  155  may output the codeword CW, output from the memory bank  131 , to the error correction circuit  170  during the ECC read operation. The input/output control circuit  155  may store the codeword CW, received from the error correction circuit  170 , in the memory bank  131  during the ECC write operation. The codeword CW that is received from the error correction circuit  170  may include error-corrected data and parity. 
     The error correction circuit  170  may transmit/receive the codeword CW to/from the input/output control circuit  155  or transmit/receive Tx data TD to/from the data buffer  190  based on the ECS read command ERD and the ECS write command EWT. The error correction circuit  170  may generate the error flag signal EFLAG based on the codeword CW. The error correction circuit  170  may receive the codeword CW that is output through the input/output control circuit  155  when the ESC read operation is performed during the error check operation and may decode the codeword CW and generate the error flag signal EFLAG when an error is checked within the data and parity that are included in the decoded codeword CW. The error correction circuit  170  may generate the error-corrected codeword CW by performing an error correction operation when the ECS read operation is performed during the ECS operation. When the ECS write operation is performed, the error correction circuit  170  may transfer the error-corrected codeword CW to the input/output control circuit  155  to store the error-corrected codeword CW in the memory bank  131 . The error correction circuit  170  may be configured to correct an error that is contained in the codeword CW by using the error correction code ECC. 
     The data buffer  190  may transmit/receive Tx data TD to/from the error correction circuit  170  or transmit/receive Tx data TD to/from a controller (not illustrated) based on the ECS read command ERD and the ECS write command EWT. 
     The semiconductor device  10 , in accordance with the present embodiment, may perform the error check operation to sense memory cells in which the codewords CW that contain an error are stored and may perform the ECS operation only on the memory cells in which the codewords CW that contain an error are stored, thereby reducing the power consumption. 
       FIG.  2    is a block diagram illustrating a configuration of the ECS command generation circuit  103  in accordance with an embodiment. As illustrated in  FIG.  2   , the ECS command generation circuit  103  may include a refresh counter  21  and a code decoder  23 . 
     The refresh counter  21  may generate a refresh code RC by counting the refresh command REF. The refresh counter  21  may generate the refresh code RC that is initialized when the ECS command AECS is input. The refresh counter  21  may generate the refresh code RC that is counted whenever the refresh command REF is input. The refresh counter  21  may differently set the logic level combinations of bits that are contained in the refresh code RC whenever the refresh command REF is input. For example, when the refresh code RC is set to two bits, the logic level combination of the refresh code RC may be changed to ‘00’, ‘01’, ‘10’, or ‘11’, whenever the refresh command REF is input. The logic level combination ‘01’ of the refresh code RC indicates that the second bit RC&lt;2&gt; of the refresh code has a logic low level, and the first bit RC&lt;1&gt; of the refresh code has a logic high level. The number of bits that are contained in the refresh code RC may be set to various values in different embodiments. 
     The code decoder  23  may generate the ECS command AECS based on the refresh code RC. The code decoder  23  may generate the ECS command AECS when the refresh code RC is counted as a preset logic level combination. The code decoder  23  may generate the ECS command AECS when the refresh code RC has the preset logic level combination. For example, the code decoder  23  may generate the ECS command AECS when the logic level combination of the refresh code RC&lt;2:1&gt;, which is set as the refresh command REF is generated for the third time, is ‘10’. 
       FIG.  3    is a circuit diagram illustrating a configuration of the check flag signal generation circuit  107  in accordance with an embodiment. As illustrated in  FIG.  3   , the check flag signal generation circuit  107  may include a NOR gate  107 _ 1 , an inverter  107 _ 2 , and a NOR gate  107 _ 3 . 
     The check flag signal generation circuit  107  may generate the check flag signal CHK_FLAG based on the error flag signal EFLAG and the initialization check signal INIT_CHK. The check flag signal generation circuit  107  may generate the check flag signal CHK_FLAG that is enabled to a logic high level when the error flag signal EFLAG is input as a logic high level. The check flag signal generation circuit  107  may generate the check flag signal CHK_FLAG that is disabled to a logic low level when the initialization check signal INIT_CHK is input as a logic high level. The check flag signal generation circuit  107  may generate the check flag signal CHK_FLAG that is enabled to a logic high level until the initialization check signal INIT_CHK is input as a logic high level after the error flag signal EFLAG is input as a logic high level. The check flag signal generation circuit  107  may be implemented as an SR latch circuit. 
       FIG.  4    is a block diagram illustrating a configuration of the ECS control circuit  109  in accordance with an embodiment. As illustrated in  FIG.  4   , the ECS control circuit  109  may include a clock code generation circuit  41 , a check decoder  43 , and an operation decoder  45 . 
     The clock code generation circuit  41  may generate a clock code CLC based on the ECS command AECS and the end signal END. The clock code generation circuit  41  may generate the clock code CLC, the logic level combination of which is adjusted in synchronization with an oscillation signal (OSC of  FIG.  5   ) that is generated during a time period from a point of time at which the ECS command AECS is generated to a point of time at which the end signal END is generated. The clock code generation circuit  41  may generate the clock code CLC that is counted whenever the oscillation signal (OSC of  FIG.  5   ) is generated during the time period from the point of time at which the ECS command AECS is generated to the point of time at which the end signal END is generated. 
     The check decoder  43  may generate the initialization check signal INIT_CHK in order to disable the check flag signal CHK_FLAG. The check decoder  43  may generate the initialization check signal INIT_CHK to disable the check flag signal CHK_FLAG after the ECS active command EACT, the ECS read command ERD, the ECS write command EWT, and the ECS precharge command EPCG are repeatedly generated four times. 
     The check decoder  43  may generate the ECS active command EACT, the ECS read command ERD, the ECS precharge command EPCG, and the end signal END based on the error check execution signal ECS_EXE and the clock code CLC. The check decoder  43  may sequentially generate the ECS active command EACT, the ECS read command ERD, the ECS precharge command EPCG, and the end signal END in synchronization with the clock code CLC during a period in which the error check execution signal ECS_EXE is disabled. The check decoder  43  may sequentially generate the ECS active command EACT, the ECS read command ERD, the ECS precharge command EPCG, and the end signal END based on the clock code CLC during a period in which the error check execution signal ECS_EXE is disabled. During a period in which the error check execution signal ECS_EXE is disabled, the check decoder  43  may repeatedly generate the ECS read command ERD in order to determine whether each of the codewords CW contains an error. The number of times that the ECS read command ERD is repeatedly generated may be set to various values in different embodiments. 
     The check decoder  43  may sequentially generate the ECS precharge command EPCG and the end signal END after repeatedly generating the ECS read command ERD. The logic level combinations of the clock code CLC for generating the ECS active command EACT, the ECS read command ERD, the ECS precharge command EPCG, and the end signal END may be set to values different from one another. For example, the ECS active command EACT may be generated when the clock code CLC is counted 10 times and generated, and the ECS read command ERD may be generated whenever the clock code CLC is counted 20 times, 24 times, 28 times and 30 times and generated. 
     The operation decoder  45  may generate the ECS active command EACT, the ECS read command ERD, the ECS write command EWT, the ECS precharge command EPCG, and the end signal END based on the error check execution signal ECS_EXE and the clock code CLC. During a period in which the error check execution signal ECS_EXE is enabled, the operation decoder  45  may sequentially generate the ECS active command EACT, the ECS read command ERD, the ECS write command EWT, the ECS precharge command EPCG, and the end signal END in synchronization with the clock code CLC. The operation decoder  45  may sequentially generate the ECS active command EACT, the ECS read command ERD, the ECS write command EWT, the ECS precharge command EPCG, and the end signal END in order to perform the ECS operation on the memory cells in which the codewords CW are stored. The logic level combinations of the clock code CLC for generating the ECS active command EACT, the ECS read command ERD, the ECS precharge command EPCG, and the end signal END may be set to values different from one another. For example, the ECS active command EACT may be generated when the clock code CLC is counted 10 times and generated, the ECS read command ERD may be generated when the clock code CLC is counted 20 times and generated, and the ECS write command EWT may be generated when the clock code CLC is counted 28 times and generated. 
       FIG.  5    is a block diagram illustrating a configuration of the clock code generation circuit  41  in accordance with an embodiment. As illustrated in  FIG.  5   , the clock code generation circuit  41  may include an ECS mode signal generation circuit  411 , an oscillation signal generation circuit  413  and a clock counter  415 . 
     The ECS mode signal generation circuit  411  may generate an ECS mode signal ECS_MD based on the ECS command AECS and the end signal END. The ECS mode signal generation circuit  411  may generate the ECS mode signal ECS_MD that is enabled from a point of time at which the ECS command AECS is generated to a point of time at which the end signal END is generated. 
     The oscillation signal generation circuit  413  may generate an oscillation signal OSC based on the ECS mode signal ECS_MD. The oscillation signal generation circuit  413  may generate the oscillation signal OSC that toggles in each preset period when the ECS mode signal ECS_MD is generated at a logic high level. The oscillation signal generation circuit  413  may generate the oscillation signal OSC that toggles during a period in which the ECS mode signal ECS_MD is generated at a logic high level. 
     The clock counter  415  may generate the clock code CLC based on the oscillation signal OSC. The clock counter  415  may generate the clock code CLC that is counted whenever the oscillation signal OSC is input. The clock counter  415  may adjust the logic level combination of the clock code CLC by counting the oscillation signal OSC. For example, when the clock code CLC contains three bits, the clock counter  415  may generate the clock code CLC that sequentially has logic level combinations of ‘001’, ‘010’, ‘011’, ‘100’, ‘101’, ‘110’, and ‘111’ in synchronization with time points (hereafter, referred to as ‘rising edges’) that the oscillation signal OSC transitions from a logic low level to a logic high level. When the logic level combination of the clock code CLC is ‘110’, it indicates that the third bit CLC&lt;3&gt; and the second bit CLC&lt;2&gt; of the clock code each have a logic high level, and the first bit CLC&lt;1&gt; of the clock code has a logic low level. The clock counter  415  may generate the clock code CLC that is initialized when no pulse of the oscillation signal OSC is input. 
       FIG.  6    is a circuit diagram illustrating a configuration of the ECS mode signal generation circuit  411  in accordance with an embodiment. As illustrated in  FIG.  6   , the ECS mode signal generation circuit  411  may include a NOR gate  411 _ 1 , an inverter  411 _ 2 , and a NOR gate  411 _ 3 . 
     The ECS mode signal generation circuit  411  may generate the ECS mode signal ECS_MD based on the ECS command AECS, the end signal END, and a reset signal RST. The ECS mode signal generation circuit  411  may generate the ECS mode signal ECS_MD that is enabled to a logic high level when the ECS command AECS is input as a logic high level. The ECS mode signal generation circuit  411  may generate the ECS mode signal ECS_MD that is disabled to a logic low level when the end signal END is input as a logic high level. The ECS mode signal generation circuit  411  may generate the ECS mode signal ECS_MD that is disabled to a logic low level when the reset signal RST is input as a logic high level. The ECS mode signal generation circuit  411  may generate the ECS mode signal ECS_MD that is enabled to a logic high level until the end signal END is input as a logic high level after the ECS command AECS is input as a logic high level. The ECS mode signal generation circuit  411  may be implemented as an SR latch circuit. The reset signal RST may be set to a signal that is enabled to a logic high level during a reset operation of the semiconductor device  10 . 
       FIG.  7    is a circuit diagram illustrating a configuration of the oscillation signal generation circuit  413  in accordance with an embodiment. As illustrated in  FIG.  7   , the oscillation signal generation circuit  413  may include a NAND gate  413 _ 1  and inverters  413 _ 2  to  413 _ 5 . 
     The oscillation signal generation circuit  413  may generate the oscillation signal OSC that toggles in each preset period when the ECS mode signal ECS_MD is input as a logic high level. The NAND gate  413 _ 1  that is included in the oscillation signal generation circuit  413  may operate as an inverter when the ECS mode signal ESC_MD is input as a logic high level. The oscillation signal generation circuit  413  may operate as a ring oscillator when the ECS mode signal ECS_MD is input as a logic high level and may generate the oscillation signal OSC that toggles in each preset period. During a period in which the ECS mode signal ECS_MD is generated at a logic high level, the oscillation signal generation circuit  413  may operate as a ring oscillator and generate the oscillation signal OSC that toggles. 
       FIG.  8    is a block diagram illustrating a configuration of the select address generation circuit  111  in accordance with an embodiment. As illustrated in  FIG.  8   , the select address generation circuit  111  may include an address counter  51 , an input/output control signal generation circuit  53 , an address pipe  55 , and an address selection circuit  57 . 
     The address counter  51  may generate a row address RADD and a column address CADD based on the ECS active command EACT, the ECS read command ERD, and the ECS write command EWT. The address counter  51  may generate the row address RADD and the column address CADD that are sequentially counted whenever any one of the ECS read command ERD and the ECS write command EWT is input after the ECS active command EACT is input. The address counter  51  may generate the row address RADD and the column address CADD through which another memory cell can be accessed whenever any one of the ECS read command ERD and the ECS write command EWT is input after the ECS active command EACT is input. 
     The input/output control signal generation circuit  53  may generate an input control signal PIN based on the ECS read command ERD and the error flag signal EFLAG during an error check operation. For example, the input/output control signal generation circuit  53  may generate a first bit PIN&lt;1&gt; of the input control signal when the ESC read command ERD is generated and the error flag signal EFLAG is generated and may sequentially generate a second bit PIN&lt;2&gt;, a third bit PIN&lt;3&gt;, and a fourth bit PIN&lt;4&gt; of the input control signal whenever the error flag signal EFLAG is generated. The number of bits that are contained in the input control signal PIN may be set to various values in different embodiments. 
     The input/output control signal generation circuit  53  may generate an output control signal POUT based on the ECS read command ERD during an ECS operation. For example, the input/output control signal generation circuit  53  may generate a first bit POUT&lt;1&gt; of the output control signal when the ESC read command ERD is generated during the ECS operation and may sequentially generate a second bit POUT&lt;2&gt;, a third bit POUT&lt;3&gt;, and a fourth bit POUT&lt;4&gt; of the output control signal whenever the ESC read command ERD is generated. The number of bits that are contained in the output control signal POUT may be set to various values in different embodiments. 
     The address pipe  55  may store the row address RADD and the column address CADD based on the input control signal PIN and may output the row address RADD and the column address CADD, stored therein, as a pipe row address PRADD and a pipe column address PCADD based on the output control signal POUT. For example, the address pipe  55  may output the row address RADD and the column address CADD, stored when a J th  bit PIN&lt;J&gt; of the input control signal is generated, as the pipe row address PRADD and the pipe column address PCADD when a J th  bit POUT&lt;J&gt; of the output control signal is generated. Here, ‘J’ may be set to a natural number. 
     The address selection circuit  57  may generate the select row address SRADD and the select column address SCADD from the row address RADD, the column address CADD, the pipe row address PRADD, and the pipe column address PCADD based on the check flag signal CHK_FLAG. The address selection circuit  57  may select and output the row address RADD and the column address CADD as the select row address SRADD and the select column address SCADD during a period in which the check flag signal CHK_FLAG is disabled. The address selection circuit  57  may select and output the pipe row address RADD and the pipe column address CADD as the select row address SRADD and the select column address SCADD during a period in which the check flag signal CHK_FLAG is enabled. 
       FIG.  9    is a block diagram illustrating configurations of the memory bank  131  and the sensing amplification circuit  133 . As illustrated in  FIG.  9   , the memory bank  131  may include a first area  131 _ 1  and a second area  131 _ 2 . 
     The first area  131 _ 1  may include first to M th  word lines WL 1  to WLm. The second area  131 _ 2  may include (M+1) th  to N th  word lines WLm+1 to WLn. The number of the word lines that are included in the first and second areas  131 _ 1  and  131 _ 2  may be set to various values in different embodiments. 
     An error check operation Error Check on the first area  131 _ 1  in a case Error in which an error occurs will be described with reference to  FIG.  9   . 
     The first area  131 _ 1  may output a codeword CW that is stored in a memory cell (not illustrated) based on the ECS read command ERD that is repeatedly generated during the error check operation. 
     The sensing amplification circuit  133  may sense and amplify the codeword CW and may output the sensed and amplified codeword CW. At this time, because an error has occurred in the codeword CW, a read modify write operation RMW may be performed during the ECS operation. The read modify write operation RMW may indicate an operation of outputting the codeword CW when the ECS read command ERD is generated during the ECS operation and re-storing the error-corrected codeword CW at the same position when the ECS write command EWT is generated. 
     The error check operation on the first area  131 _ 1  in the case of “No Error” in which no error occurs will be described with reference to  FIG.  9   . 
     The first area  131 _ 1  may output a codeword CW that is stored in a memory cell (not illustrated) based on the ECS read command ERD that is repeatedly generated during the error check operation. 
     The sensing amplification circuit  133  may sense and amplify the codeword CW and may output the sensed and amplified codeword CW. At this time, because the codeword CW has no error, only the error check operation Error Check may be performed. 
     The error check operation Error Check on the second area  131 _ 2  in the case of “Error” in which an error has occurred will be described with reference to  FIG.  9   . 
     The second area  131 _ 2  may output a codeword CW that is stored in a memory cell (not illustrated) based on the ECS read command ERD that is repeatedly generated during an error check operation. 
     The sensing amplification circuit  133  may sense and amplify the codeword CW and may output the sensed and amplified codeword CW. At this time, because an error has occurred in the codeword CW, the read modify write operation RMW may be performed during the ECS operation. The read modify write operation RMW may indicate an operation of outputting the codeword CW when the ECS read command ERD is generated during the ECS operation and re-storing the error-corrected codeword CW at the same position when the ECS write command EWT is generated. 
     The error check operation on the second area  131 _ 2  in the case No Error in which no error occurs will be described with reference to  FIG.  9   . 
     The second area  131 _ 2  may output a codeword CW that is stored in a memory cell (not illustrated) based on the ECS read command ERD that is repeatedly generated during the error check operation. 
     The sensing amplification circuit  133  may sense and amplify the codeword CW and may output the sensed and amplified codeword CW. At this time, because the codeword CW has no error, only the error check operation Error Check may be performed. 
     The error check operation Error Check on the second area  131 _ 2  may be performed after the error check operation Error Check on the first area  131 _ 1  is completed. 
       FIG.  10    is a timing diagram for describing an operation of the semiconductor device  10  illustrated in  FIG.  1   . 
     As illustrated in  FIG.  10   , the ECS command AECS may be generated whenever the refresh command REF is generated K times. 
     An operation at time T 1  may be an operation that is performed when no error occurs in the codeword CW during the error check operation. 
     At time T 1 , the error check execution signal generation circuit  105  may generate the error check execution signal ECS_EXE that is disabled to a logic low level L during an initialization operation. 
     When no error occurs in the codeword CW, the check flag signal generation circuit  107  may receive the error flag signal EFLAG and generate the check flag signal CHK_FLAG that is disabled to a logic low level L. 
     The operation that is performed when no error occurs in the codeword CW during the error check operation will be described in more detail with reference to  FIG.  11   , which will be described below. 
     An operation at time T 2  may be an operation that is performed when an error has occurred in the codeword CW during the error check operation. 
     At time T 2 , the error check execution signal generation circuit  105  may generate the error check execution signal ECS_EXE that is disabled to a logic low level L during the initialization operation. 
     The check flag signal generation circuit  107  may receive the error flag signal EFLAG that is generated when an error has occurred in the codeword CW and may generate the check flag signal CHK_FLAG that is enabled to a logic high level H. 
     The operation that is performed when an error has occurred in the codeword CW during the error check operation will be described in more detail with reference to  FIG.  12   , which will be described below. 
     An operation at time T 3  may be an operation that is performed when an error has occurred in the codeword CW during the error check operation. In this case, the ECS operation may be performed. 
     At time T 3 , the error check execution signal generation circuit  105  may generate the error check execution signal ECS_EXE that is enabled to a logic high level H when the ECS command with a logic high level H and the check flag signal CHK_FLAG with a logic high level H are input. 
     The ECS control circuit  109  may sequentially generate the ECS active command EACT, the ECS read command ERD, the ECS write command EWT, the ECS precharge command EPCG, and the end signal END such that the ECS operation is performed on the memory cells in which each of the codewords CW that contains an error are stored. The operation of outputting the codeword CW to the error correction circuit  170  based on the ECS read command ERD and storing the error-corrected codeword CW based on the ECS write command EWT may be set to the read modify write operation RMW. 
     The operation of performing the ECS operation when an error occurs in the codeword CW during the error check operation will be described in more detail with reference to  FIG.  13   , which will be described below. 
       FIG.  11    is a timing diagram for describing an operation that is performed when no error occurs in the codeword CW during the error check operation. The error check operation illustrated in  FIG.  11    indicates the operation at time T 1  in  FIG.  10   . 
     At time T 11 , the ECS command generation circuit  103  may generate the ECS command AECS when the refresh command REF is generated a preset number of times or K times. 
     The error check execution signal generation circuit  105  may generate the error check execution signal ECS_EXE that is disabled to a logic low level during the initialization operation. 
     The ECS mode signal generation circuit  411  of the clock code generation circuit  41  may generate the ECS mode signal ECS_MD that is enabled to a logic high level at a point of time at which the ECS command AECS is generated. 
     The oscillation signal generation circuit  413  of the clock code generation circuit  41  may generate the oscillation signal OSC that toggles in each preset period when the ECS mode signal ECS_MD is generated at a logic high level. 
     The ECS control circuit  109  may generate the initialization check signal INIT_CHK in order to disable the check flag signal CHK_FLAG during a period in which the error check execution signal ECS_EXE is disabled. 
     At time T 12 , the ECS control circuit  109  may generate the ECS active command EACT in order to determine whether each of the codewords CW that is stored in the memory cells on which the ECS operation is performed contains an error during the period in which the error check execution signal ECS_EXE is disabled. 
     From time T 13  to time T 16 , the ECS control circuit  109  may repeatedly generate the ECS read command ERD in order to output the codewords CW that are stored in the memory cells. The ECS control circuit  109  may be implemented to generate the ECS read command ERD four times. In an embodiment, however, the ECS control circuit  109  may generate the ECS read command ERD various numbers of times. 
     From time T 13  to time T 16 , when the data and parity that are included in the decoded codeword CW contain no error, the error correction circuit  170  may receive the codeword CW that is output through the input/output control circuit  155  when the ESC read operation is performed during the error check operation and may decode the codeword CW and generate the error flag signal EFLAG that is disabled to a logic low level. 
     The check flag signal generation circuit  107  may receive the low-level error flag signal EFLAG that is generated when no error occurs in the codeword CW and may generate the check flag signal CHK_FLAG that is disabled to a logic low level. 
     At time T 17 , the ECS control circuit  109  may generate the ECS precharge command EPCG in order to perform a precharge operation on the memory cells on which the error check operation has been performed during a period in which the error check execution signal ECS_EXE is disabled. 
       FIG.  12    is a timing diagram for describing an operation that is performed when an error occurs in the codeword CW during the error check operation. The error check operation, illustrated in  FIG.  12   , indicates the operation at time T 2  in  FIG.  10   . 
     At time T 21 , the ECS command generation circuit  103  may generate the ECS command AECS when the refresh command REF is generated a preset number of times or K times. 
     The error check execution signal generation circuit  105  may generate the error check execution signal ECS_EXE that is disabled to a logic low level during the initialization operation. 
     The ECS mode signal generation circuit  411  of the clock code generation circuit  41  may generate the ECS mode signal ECS_MD that is enabled to a logic high level at a point of time at which the ECS command AECS is generated. 
     The oscillation signal generation circuit  413  of the clock code generation circuit  41  may generate the oscillation signal OSC that toggles in each preset period when the ECS mode signal ECS_MD is generated at a logic high level. 
     The ECS control circuit  109  may generate the initialization check signal INIT_CHK in order to disable the check flag signal CHK_FLAG during a period in which the error check execution signal ECS_EXE is disabled. 
     At time T 22 , during the period in which the error check execution signal ECS_EXE is disabled, the ECS control circuit  109  may generate the ECS active command EACT in order to determine whether each of the codewords CW that is stored in the memory cells on which the ECS operation is performed contains an error. 
     From time T 23  to time T 26 , the ECS control circuit  109  may repeatedly generate the ECS read command ERD in order to output the codewords CW that are stored in the memory cells. The ECS control circuit  109  may be implemented to generate the ECS read command ERD four times. In an embodiment, however, the ECS control circuit  109  may generate the ECS read command ERD various numbers of times. 
     At time T 25 , the error correction circuit  170  may receive the codeword CW output through the input/output control circuit  155  when the ESC read operation is performed during the error check operation and may decode the codeword CW and generate the error flag signal EFLAG that is enabled to a logic high level, when an error is checked from the data and parity that are included in the decoded codeword CW. 
     The select address generation circuit  111  may receive the high-level error flag signal EFLAG and store an address for accessing a memory cell in which a codeword is stored, the codeword containing an error that occurred during the error check operation. 
     The check flag signal generation circuit  107  may receive the high-level error flag signal EFLAG that is generated when an error occurs in the codeword CW and may generate the check flag signal CHK_FLAG that is disabled to a logic high level. 
     At time T 27 , the ECS control circuit  109  may generate the ECS precharge command EPCG in order to perform a precharge operation on the memory cells on which the error check operation has been performed during a period in which the error check execution signal ECS_EXE was disabled. 
       FIG.  13    is a timing diagram for describing the operation that is performed when the ECS operation is performed as an error occurs in the codeword CW during the error check operation. The error check operation illustrated in  FIG.  13    indicates the operation at time T 3  in  FIG.  10   . 
     At time T 31 , the ECS command generation circuit  103  may generate the ECS command AECS when the refresh command REF is generated a preset number of times or K times. 
     The error check execution signal generation circuit  105  may receive the high-level ECS command AECS and the high-level check flag signal CHK_FLAG and may generate the error check execution signal ECS_EXE that is enabled to a logic high level. 
     The ECS mode signal generation circuit  411  of the clock code generation circuit  41  may generate the ECS mode signal ECS_MD that is enabled to a logic high level at a point of time at which the ECS command AECS is generated. 
     The oscillation signal generation circuit  413  of the clock code generation circuit  41  may generate the oscillation signal OSC that toggles in each preset period when the ECS mode signal ECS_MD is generated at a logic high level. 
     At time T 32 , the ECS control circuit  109  may generate the ECS active command EACT in order to determine whether each of the codewords CW that is stored in the memory cells, on which the ECS operation is performed during a period in which the error check execution signal ECS_EXE is enabled, contains an error. 
     At time T 33 , the ECS control circuit  109  may generate the ECS read command ERD in order to output the codewords CW that are stored in the memory cells on which the ECS operation is performed. 
     During the error check operation, the select address generation circuit  111  may receive the high-level check flag signal CHK_FLAG and output an address that is stored therein as the select row address SRADD and the select column command SCADD in order to access a memory cell in which the codeword CW that contains an error is stored. 
     The memory bank  131  may output the codeword CW, stored in a memory cell that is selected by the select row address SRADD and the select column command SCADD, to the error correction circuit  170  through the input/output control circuit  155 . 
     The error correction circuit  170  may receive the codeword CW and generate the error-corrected codeword CW by performing the error correction operation. 
     At time T 34 , the ECS control circuit  109  may generate the ECS write command EWT in order to store the codeword CW in the memory cells on which the ECS operation is performed. 
     During the error check operation, the select address generation circuit  111  may receive the high-level check flag signal CHK_FLAG and output an address that is stored therein as the select row address SRADD and the select column command SCADD in order to access a memory cell in which the codeword CW that contains an error is stored. 
     The error correction circuit  170  may transfer the error-corrected codeword CW to the input/output control circuit  155  to store the error-corrected codeword CW in the memory bank  131 . 
     At time T 35 , the ECS control circuit  109  may generate the ECS precharge command EPCG in order to perform a precharge operation on the memory cells on which the ECS operation has been performed during a period in which the error check execution signal ECS_EXE was enabled. 
     The semiconductor device  10 , in accordance with the present embodiment, may perform the ECS operation of performing an error check operation of detecting errors of the codewords that are stored in memory cells, correcting the errors of the codewords, and re-storing the codewords. Thus, the semiconductor device  10  may perform the ECS operation that is capable of correcting the errors of the codewords that are stored in the memory cells, and re-storing the error-corrected codewords in the memory cells. Furthermore, the semiconductor device  10 , in accordance with the present embodiment, may perform the error check operation of detecting errors of the codewords that are stored in the memory cells and then perform the ECS operation only on an area in which the codeword that contains an error is stored, thereby reducing power consumption. 
       FIG.  14    is a block diagram illustrating a configuration of an electronic system  1000  in accordance with an embodiment. As illustrated in  FIG.  14   , the electronic system  1000  may include a host  1100  and a semiconductor system  1200 . 
     The host  1100  and the semiconductor system  1200  may transmit/receive signals to/from each other by using an interface protocol. Examples of the interface protocol used between the host  1100  and the semiconductor system  1200  may include an MMC (Multi-Media Card), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), PCI-E (Peripheral Component Interconnect-Express), ATA (Advanced Technology Attachment), SATA (Serial ATA), PATA (Parallel ATA), SAS (serial attached SCSI), USB (Universal Serial Bus) and the like. 
     The semiconductor system  1200  may include a controller  1300  and semiconductor devices  1400 (K:1). The controller  1300  may control the semiconductor devices  1400 (K:1) to perform an error check operation and an ECS operation based on a refresh command REF. Each of the semiconductor devices  1400 (K:1) may perform the error check operation and the ECS operation based on the refresh command REF, and thus, perform the ECS operation only on the memory cells in which the codewords CW that contains an error is stored. 
     Each of the semiconductor devices  1400 (K:1) may be implemented as the semiconductor device  10  illustrated in  FIG.  1   . In an embodiment, each of the semiconductor devices  1400 (K:1) may be implemented as one of a DRAM (dynamic random access memory), PRAM (Phase change Random Access Memory), RRAM (Resistive Random Access Memory), MRAM (Magnetic Random Access Memory) and FRAM (Ferroelectric Random Access Memory). 
     Although some embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as defined in the accompanying claims.