Patent Publication Number: US-6703642-B1

Title: Silicon carbide (SiC) gate turn-off (GTO) thyristor structure for higher turn-off gain and larger voltage blocking when in the off-state

Description:
This invention relates to an improvement in the design of high power, high temperature switches, more specifically, SiC gate turn off (GTO) thyristors. Conventional SiC GTO thyristors typically have a drift region made of p-type rather than n-type material adjacent to an n-type region with gate contacts. Conventional SiC GTO thyristor structures also typically have a thin highly doped p-type buffer layer below the relatively thick, low level p-type drift region. This is known as an asymmetrical GTO (gate turn-off) thyristor structure. Thyristors typically use complementary dopants for the drift region and the gated base region to create a pn junction between the two regions (i.e., if the drift region is p-type then the gated base region is n-type and vice versa.) 
     Examples of various conventional SiC GTO thyristors can be found in U.S. Pat. No. 5,831,289 to A. K. Agarwal, entitled “Silicon carbide gate turn-off thyristor arrangement;” U.S. Pat. No. 5,539,217 to J. A. Edmond, J. W. Palmour entitled, “Silicon carbide thyristor;” M. E. Levinshtein, J. W. Palmour, S. L. Rumyanetsev, and R. Singh, “Turnon process in 4H-SiC Thyristors,”  IEEE Trans. Elect. Dev . Vol 44, p. 1177, 1997; K. Xie, J. H. Zhao, J. R. Flemish, T. Burke, W. R. Buchwald, G. Lorenzo, and H. Singh, “A high current and high temperature 6H-SiC thyristor,”  IEEE Elect. Dev. Lett ., vol. 17, p 142, 1996; P. B. Shah and K. A. Jones, “Two-dimensional numerical investigation of the impact of material-parameter uncertainty on the steady-state performnance of passivated 4H-SiC thyristors,”  J Appl. Phys ., vol. 84, p. 4625, 1998; J. B. Casady, A. K. Agarwal, S. Seshadri, R. R. Siergiej, L. B. Rowland, M. F. Macmillan, D. C. Sheridan, P. A. Sanger, and C. D. Brandt., “4H SiC power devices for use in power electronic motor control,”  Solid State Electronics , vol. 42, p. 2165, 1998; and A. K. Agarwal, J. B. Casady, L. B. Rowland, S. Seshadri, R. R. Siergiej, W. F. Valek, and C. D. Brandt, “700 V Asymmetrical 4H-SiC Gate Turn-Off Thyristors (GTO),  IEEE Elect. Dev. Lett ., vol. 18, p. 518, 1997. 
     BACKGROUND 
     Silicon GTO thyristors have been commercially available since the 1960s. However they are not able to operate at the high temperatures that silicon carbide GTO thyristors can. Also silicon carbide GTO thyristors should be able to block larger voltages in the off-state, and conduct higher current densities in the on state than silicon GTO thyristors. These are the reasons for making GTO thyristors out of silicon carbide. However, because of material issues, the optimum structure for silicon GTO thyristors cannot be used for silicon carbide GTO thyristors . Thus, new designs are needed. 
     SiC GTO thyristors have only recently come of age because of the difficulty in producing good SiC. They are, for the most part, still only being used experimentally. A very intense effort is, however, underway in research laboratories throughout the world to improve the quality of SiC and the performance of SiC GTO thyristors. Ordinary silicon GTO thyristors are widely used in high power conditioning circuits, in high voltage DC systems, and in traction circuits. Other applications include motor control, power factor control, and other power conditioning circuits. Such systems are finding increased military applications and will be found in future electric or hybrid electric tanks, electric helicopters, and other vehicles used by the Army. 
     A thyristor is made up of layers of alternately doped n-type and p-type material. N-type and p-type refer to the majority carriers that are present in the region. In an n-type region “electrons” are the majority carriers of charge, and in a p-type region “holes” (the absence of electrons) are the majority carriers of charge. To make a region n-type, additional nitrogen atoms or “impurities” (donors, N D ) are typically added to the SiC crystal. To make a region p-type, aluminum impurities (acceptors, N A ) are typically added to the SiC crystal. The alternating semiconductor layers of the thyristor, in effect, make up two three-layer combinations where each is equivalent to a bipolar junction transistor. When the sum of the forward current gain across the two three layer combinations is greater than one, the thyristor will latch on and current will flow from anode to cathode. The thyristor will stay on until the anode to cathode current is interrupted. 
     The GTO thyristor has been a particularly successful design since it overcomes the problem of switching off anode to cathode current. A GTO thyristor can be switched on by a gate current of one polarity and switched off by a gate current of the opposite polarity. Known SiC GTO thyristors, are multi-layer pnpn devices. They have limited turn-off gain and turn-off speed and voltage blocking performance is limited as well. 
     OBJECTS OF THE INVENTION AND SUMMARY 
     Accordingly, it is a primary object of the present invention to provide a SiC GTO thyristor that has improved performance characteristics such as turn-off gain and turn off speed and voltage blocking and at the same time be highly reliable and inexpensive to manufacture and produce. 
     The foregoing objects are achieved, at least in part by a silicon carbide gate-turn-off thyristor that includes a p-type anode region, a n-type gated base region positioned beneath the anode region, a n-type drift region positioned beneath the gated base region and doped to a lower concentration of donors than that of the gated base region, a p-type buffer region positioned beneath the n-type drift region and doped with acceptors to a concentration whose magnitude lies between the doping concentration of the anode region and the drift region, and an n-type substrate positioned beneath the drift region. In another aspect of the invention of this application, a silicon or silicon carbide gate-turn-off thyristor includes a GTO thyristor structure with a thick buffer layer having a high, free-carrier recombination rate. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing objects and advantages of the present invention will be more fully understood from the following detailed description having reference to the appended drawings wherein: 
     FIG. 1 shows a cross section of a typical asymmetric SiC GTO thyristor structure; 
     FIG. 2 shows a cross section of the structure of a preferred embodiment of the invention of this application; 
     FIG. 3 shows a graph of the steady state current-voltage characteristics of both the prior art and a preferred embodiment of the invention as shown in FIG. 2; 
     FIG. 4 shows a graph of the turn-off gain and turn-off time seen with conventional devices; 
     FIG. 5 shows a graph of the improved turn-off gain and turn-off time seen with a preferred embodiment of the invention as shown in FIG. 2; 
     FIG. 6 shows a graph of the turn-off gain of a conventional SiC GTO when operating at higher cathode currents; 
     FIG. 7 shows a graph of the much improved turn-off gain of a preferred embodiment of the invention as shown in FIG. 2 when operating at higher cathode currents. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A typical asymmetric GTO thyristor structure is shown in FIG.  1 . The device includes an anode contact  10 , a p-type anode region  12  beneath contact  10  , an n-type gated base region  14  lying beneath anode region  12 , a gate contact  16  positioned on top of the part of gated base region  14  not covered by anode region  12 , a p-type drift region  18  beneath gated base region  14 , a highly doped p-type buffer layer  20  beneath drift region  18 , an n-type substrate  22  beneath buffer layer  20  and a cathode contact  24  beneath n-type substrate  22 . Typical dopant concentrations and thicknesses for prior art SiC GTO thyristors such as the device of FIG. 1, are shown in Table 1, below. 
     
       
         
           
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 Region number 
                 Dopant concentration 
                 Thickness 
               
               
                   
               
             
            
               
                 12 
                 N A  = 1 × 10 19  cm −3   
                 2 μm 
               
               
                 14 
                 N D  = 1 × 10 18  cm −3   
                 1 μm 
               
               
                 18 
                 N A  = 1 × 10 15  cm −3   
                 3 μm 
               
               
                 20 
                 N A  = 3 × 10 17  cm −3   
                 1 μm 
               
               
                 22 
                 N D  = 5 × 10 17  cm −3   
                 Substrate (300 μm) 
               
               
                   
               
            
           
         
       
     
     A preferred embodiment of the invention of this application is shown in FIG.  2 . The embodiment includes an anode contact  110 , a p-type anode region  112  beneath anode contact  110 , a highly doped n-type gated base region  114  lying beneath anode region  112 , a gate contact  116  positioned on top of the part of gated base region  114  not covered by anode region  112 , a low doped n-type region  118  beneath gated base region  114 , a p-type buffer region  120  beneath drift region  118 , an n-type substrate  122  beneath buffer layer  120  and a cathode contact  124  beneath n-type substrate  122 . Preferred dopant concentrations and thicknesses for the device of FIG. 2 are shown in Table 2, below. 
     
       
         
           
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                 Region number 
                 Dopant concentration 
                 Thickness 
               
               
                   
               
             
            
               
                 112 
                 N A  = 1 × 10 19  cm −3   
                 2 μm 
               
               
                 114 
                 N D  = 1 × 10 18  cm −3   
                 1 μm 
               
               
                 113 
                 N D  = 1 × 10 15  cm −3   
                 3 μm 
               
               
                 120 
                 N A  = 3 × 10 17  cm −3   
                 4 μm 
               
               
                 122 
                 N D  = 5 × 10 17  cm −3   
                 Substrate (300 μm) 
               
               
                   
               
            
           
         
       
     
     As can be seen, doping for the regions of the embodiment shown in FIG. 2 are conventional except for the drift region which is now n-type instead of p-type. Various other concentrations are, of course, also possible. The following ranges would be typical, with the exact concentrations to be selected depending on design considerations familiar to those of ordinary skill in the art: for p-type anode region  112 , N A &gt;1×10 19  cm 3 ; n-type gated base region  114 , 1×10 16 &lt;N D &lt;5×10 18 ; n-type drift region  118 , N D &lt;4×10 16 ; p-type buffer region  120 , 1×10 17 &lt;N A &lt;1×10 19 ; n type substrate  122 , N D &lt;5×10 18  is best though N D  can be higher. As with all SiC GTO thyristors, the devices should be passivated by depositing a passivation material on all exposed silicon carbide surfaces, such as silicon dioxide layers  26  and  126  shown in FIGS. 1 and 2, respectively. 
     Operation 
     The devices operate in essentially the same way. In the on-state, current flows from the anode to the cathode. The thyristor (pnpn structure) can be modeled as two bipolar transistors (a pnp and an npn transistor) coupled such that the collector current of one is the base drive current of the other. This coupling leads to a feedback mechanism that causes all the junctions to be forward biased at high currents. To turn off the GTO thyristor, a reverse bias pulse is applied at the gate contact. The reverse bias current extracts majority carriers from the gate region and this in turn through charge neutrality, also causes the minority carriers in the vicinity of the gate region to be removed. This initially breaks the thyristor action in the regions nearest the gate contacts. The current flowing in the device from anode to cathode is squeezed and forced to flow through a narrower region along the n+/p junction between regions  14  and  18 , or the n+/n junction between regions  114  and  118  in the invention. The portion of the thyristor closest to the gate contact turns off first, and as the gate pulse increases, the off region extends further from the gate contact along this junction. This process squeezes the anode-cathode current flow even more until the feedback is broken, the thyristor action ceases, and the GTO thyristor turns off. Unlike prior art devices, in the invention of this application current squeezing takes place along the n+/n junction. 
     When the device is off, the voltage drop occurs over the low doped n-type drift region  118 . In typical structures such as shown in FIG. 1, it occurs over the low doped p-type drift region  18 . Larger blocking voltages can be seen by increasing the drift region thickness, but simulation results indicate that in all cases by making the drift region n-type the maximum blocked voltage will be larger than if the drift region was p-type as done with prior art devices. The improved voltage blocking performance is indicated in FIG.  3 . 
     The preferred embodiment of FIG. 2 requires having region  120  (the p-type buffer layer) thicker than in prior art devices. Also it requires having the drift region  118  made of n-type instead of p-type material. Either of these improvements will result in better performance. The device turns-off as a gate turn-off thyristor because the gate turn-off operation occurs regardless of whether the low doped region adjacent to the n-type gated base region  114  is n-type or p-type. Significantly improved turn-off performance occurs because the thick region  120  now reduces the concentration of carriers in the drift region when the device is on, so it turns off faster. As seen in FIG. 3, voltage blocking performance is improved over prior art devices. The improved turn-off performance is demonstrated in FIGS. 4-7. In addition, improved performance resulting from increasing the thickness of the buffer region is expected in silicon thyristors as well. 
     This invention reduces the requirements on the control circuit at the gate by improving the turn-off gain. Also, it allows faster turn-off of SiC GTO thyristors. Furthermore, this invention will provide higher voltage blocking performance than conventionally designed SiC GTO thyristors of equal magnitude of drift region dopant concentrations and thickness because the n type material has a reduced impact ionization rate. 
     Having thus shown and described what are at present considered to be preferred embodiments of the present invention, it should be noted that the same have been made by way of illustration and not limitation. Accordingly, all modifications, alterations and changes coming within the spirit and scope of the present invention are herein meant to be included.