Patent Publication Number: US-2012043538-A1

Title: Process to make metal oxide thin film transistor array with etch stopping layer

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of co-pending U.S. patent application Ser. No. 12/405,897 (APPM/013123), filed Mar. 17, 2009, which claims benefit of U.S. Provisional Patent Application Ser. No. 61/038,289 (Attorney Docket No. APPM/013123L), filed Mar. 20, 2008. Each of the aforementioned related patent applications is herein incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     Embodiments of the present invention generally relate to a thin film transistor (TFT) fabrication method and a TFT produced by the method. 
     2. Description of the Related Art 
     Current interest in TFT arrays is particularly high because these devices may be used in liquid crystal active matrix displays (LCDs) of the kind often employed for computer and television flat panels. The LCDs may also contain light emitting diodes (LEDs) for back lighting. Further, organic light emitting diodes (OLEDs) have been used for active matrix displays, and these OLEDs utilize TFTs for addressing the activity of the displays. 
     TFTs made with amorphous silicon as the active material have become the key components of the flat panel display industry. There are two general types of TFTs in industry. The first type is called a top gate TFT because the gate electrode is located above the source and drain electrodes. The second type is called a bottom gate TFT because the gate electrode is located below the source and drain electrodes. In the bottom gate TFT structure, the source and drain electrodes are disposed over the active material layer. 
     The source and drain electrodes in a bottom gate TFT may be fabricated by depositing a metal layer over the active material layer and then etching the metal layer to define the source and drain electrodes. During the etching, the active material layer may be exposed to the plasma. Plasma exposure of the active material layer may negatively affect the performance of the TFT. To prevent plasma exposure of the active material layer, an etch stop may be used. Thus, the etch stop bottom gate TFTs generally have better performance than non-etch stop bottom gate TFTs. 
     An etch stop bottom gate TFT has an etch stop layer deposited between the active material layer and the metal layer used for the source and drain electrodes. The etch stop layer is blanket deposited and then etched using a mask such that the remaining portion of the etch stop is disposed over the gate electrode. Thereafter, the metal layer is blanket deposited followed by etching the active material layer and the metal layer with a mask. Then, the source and drain electrodes are defined by etching through the metal layer using a mask. Thus, the etch stop bottom gate TFT utilizes at least three masks for the patterning (i.e., to pattern the etch stop, to pattern the active material layer and metal layer, and to define the source and drain electrodes). The bottom gate TFTs without etch stops, by contrast, necessitate at least one less mask which therefore has made the bottom gate TFTs without etch stops the preferred TFT despite the better performance of the etch stop bottom gate TFTs. 
     Therefore, there is a need in the art for an etch stop bottom gate TFT fabrication method that utilizes fewer masks. 
     SUMMARY OF THE INVENTION 
     The present invention generally relates to TFTs and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may also comprise nitrogen and oxygen. To protect the active channel during source-drain electrode patterning, an etch stop layer may be deposited over the active layer. The etch stop layer prevents the active channel from being exposed to the plasma used to define the source and drain electrodes. The etch stop layer and the source and drain electrodes may be used as a mask when wet or dry etching the active material layer that is used for the active channel. 
     In one embodiment, a thin film transistor formation method comprises depositing and patterning a gate electrode over a substrate, depositing a gate dielectric layer over the gate electrode, and depositing a semiconductive active layer over the gate dielectric layer. The active layer may comprise oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, indium, cadmium, gallium, and tin. The active layer may be doped. The method also comprises depositing an etch stop layer over the active layer, forming a first mask over the etch stop layer, patterning the etch stop layer and removing the first mask. The method also comprises depositing a metal layer over the etch stop layer, forming a second mask over the metal layer, etching the metal layer to define a source electrode and a drain electrode and removing the second mask. The method also comprises etching the active layer and depositing a passivation layer over the source electrode and the drain electrode. 
     In another embodiment, a method comprises depositing a semiconductor layer over a substrate. The semiconductor layer may comprise oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, gallium, indium, cadmium, and tin. The semiconductor layer may comprise a dopant. The method also comprises depositing an etch stop layer over the semiconductor layer, forming a first mask over the etch stop layer, patterning the etch stop layer and removing the first mask. The method also comprises depositing a metal layer over the etch stop layer and the semiconductor layer, forming a second mask over the metal layer, etching the metal layer and removing the second mask. The method also comprises etching at least a portion of the semiconductor layer while using the metal layer and the etch stop layer as masks. 
     In another embodiment, a thin film transistor comprises a gate electrode disposed over a substrate, a gate dielectric layer disposed over the gate electrode, and a semiconductor layer disposed over the gate dielectric layer. The semiconductor layer may comprise oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, gallium, indium, cadmium, and tin. The semiconductor layer may be doped. A source electrode, a drain electrode, and an etch stop layer may be disposed over the semiconductor layer and between the source electrode and the drain electrode. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
         FIGS. 1A-1J  show a TFT in various stages of processing according to one embodiment of the invention. 
         FIG. 2  is a flow chart  200  of a TFT fabrication process according to one embodiment of the invention. 
         FIGS. 3A-3D  show a TFT in various stages of processing according to another embodiment of the invention. 
         FIG. 4  is a flow chart  400  of a TFT fabrication process according to another embodiment of the invention. 
     
    
    
     To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. 
     DETAILED DESCRIPTION 
     The present invention generally relates to TFTs and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may or may not be doped. The active channel may also comprise nitrogen and oxygen. To protect the active channel during source-drain electrode patterning, an etch stop layer may be deposited over the active layer. The etch stop layer prevents the active channel from being exposed to the plasma used to define the source and drain electrodes. The etch stop layer and the source and drain electrodes may be used as a mask when wet etching the active material layer that is used for the active channel. 
       FIGS. 1A-1J  show a TFT in various stages of processing according to one embodiment of the invention. In  FIG. 1A , a substrate  100  is shown. In one embodiment, the substrate  100  may comprise glass. In another embodiment, the substrate  100  may comprise a polymer. In another embodiment, the substrate  100  may comprise plastic. In another embodiment, the substrate  100  may comprise metal. 
     Over the substrate  100 , a gate electrode layer may be deposited. The gate electrode layer may be patterned to form the gate electrode  102  as shown in  FIG. 1B . The gate electrode  102  may comprise an electrically conductive layer that controls the movement of charge carriers within the TFT. The gate electrode  102  may comprise a metal such as chromium, molybdenum, aluminum, tungsten tantalum, copper, or combinations thereof. The gate electrode  102  may be formed using conventional techniques including sputtering, lithography, and etching. 
     A gate dielectric layer  104  may be deposited over the gate electrode  102  as shown in  FIG. 1C . The gate dielectric layer  104  may comprise silicon dioxide, silicon oxynitride, silicon nitride, or combinations thereof. The gate dielectric layer  104  may be deposited by well known deposition techniques including plasma enhanced chemical vapor deposition (PECVD). 
     Over the gate dielectric layer  104 , the active layer  106  may be formed as shown in  FIG. 1D . In one embodiment, the active layer  106  is annealed. In another embodiment, the active layer  106  is exposed to a plasma treatment. The annealing and/or plasma treatment may increase the mobility of the active layer  106 . The active layer  106  may comprise the compound having one or more elements selected from the group consisting of zinc, tin, gallium, cadmium, and indium. In one embodiment, the element may comprise an element having a filled d orbital. In another embodiment, the element may comprise an element having a filled f orbital. The active layer  106  may also comprise oxygen and nitrogen. In one embodiment, the compound may be doped. Suitable dopants that may be used include Al, Sn, Ga, Ca, Si, Ti, Cu, Ge, In, Ni, Mn, Cr, V, Mg, Si x N y , Al x O y , and SiC. In one embodiment, the dopant comprises aluminum. In one embodiment, the active layer  106  may comprise oxygen and one or more elements selected from the group consisting of zinc, tin, gallium, cadmium, and indium. 
     The active layer  106  may be deposited by reactive sputtering. The reactive sputtering method may be practiced in a physical vapor deposition (PVD) chamber for processing large area substrates, such as a 4300 PVD chamber, available from AKT America, Inc., a subsidiary of Applied Materials, Inc., Santa Clara, Calif. However, because the active layer produced according to the method may be determined by the structure and composition, it should be understood that the reactive sputtering method may have utility in other system configurations, including those systems configured to process large area round substrates and those systems produced by other manufacturers, including roll-to-roll process platforms. It is to be understood that other methods including chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin-on processes may be utilized to deposit the active layer  106 . 
     For PVD, a sputtering target may contain one or more of zinc, indium, tin, gallium, and cadmium. One or more dopants may also be present. The sputtering may comprise full reactive sputtering. Full reactive sputtering comprises sputtering a target that does not contain the reactive material in an atmosphere containing the reactive material. Full reactive sputtering is distinct from RF reactive sputtering where a target contains not only the metal, but also the reactant. In RF reactive sputtering, the material is sputtered and then further reacted with additional reactant provided in the reactive gas. 
     For the present invention, the sputtering target for full reactive sputtering may comprise one or more of zinc, indium, tin, gallium, and cadmium, and a dopant may or may not be present. No oxygen or nitrogen is present in the target. The sputtering target may be DC biased while an inert gas, a nitrogen containing gas, and an oxygen containing gas are introduced into the sputtering chamber. The nitrogen of the nitrogen containing gas and the oxygen of the oxygen containing gas then react with the one or more of zinc, indium, tin, gallium, and cadmium to deposit the layer on the substrate. In one embodiment, the inert gas may comprise argon. In one embodiment, the nitrogen containing gas may be selected from the group of nitrogen, nitrogen oxide, and combinations thereof. In one embodiment, the oxygen containing gas may be selected from the group of oxygen, ozone, nitrogen oxide, and combinations thereof. The active layer  106  may be crystalline or semicrystalline. The active layer  106  may not be amorphous. 
     Once the active layer  106  has been deposited, an etch stop layer may be deposited and etched using a mask to have an etch stop  108  disposed on the active layer  106  over the gate electrode  102  as shown in  FIG. 1E . The etch stop  108  may be formed by blanket depositing, followed by photoresist depositing, followed by pattern developing. The etch stop  108  may be patterned by plasma etching using one or more gases selected from the group consisting of fluorine containing etchants such as CF 4 , C 2 F 6 , CHF 3 , C 4 F 6 , oxygen, nitrogen, inert gases such as argon, or combinations thereof. In one embodiment, the etch stop layer  108  may comprise silicon nitride. In another embodiment, the etch stop layer  108  may comprise silicon oxynitride. In still another embodiment, the etch stop layer  108  may comprise silicon oxide. The etch stop layer may be deposited by well known deposition techniques including PECVD and spin-on coating. In one embodiment, the etch stop  108  may be pattern deposited utilizing a mask. After the etch stop  108  is formed, the photoresist mask may be removed. 
     Following fabrication of the etch stop  108 , a metal layer  110  may be deposited thereover as shown in  FIG. 1F . In one embodiment, the metal layer may comprise a metal such as aluminum, tungsten, molybdenum, chromium, tantalum, and combinations thereof. The metal layer  110  may then be patterned to define the source and drain electrodes  112 A,  112 B as shown in  FIG. 1G . The metal layer  110  may be patterned by depositing a photolithographic or photoresist mask thereon and etching utilizing the mask. The metal layer  110  may be etched utilizing a plasma etch. In one embodiment, the plasma etching may comprise exposing the metal layer  110  to a plasma containing a gas having an element selected from the group consisting of chlorine, oxygen, fluorine, or combinations thereof. During the etching, the active layer  106  that is not covered by the etch stop  108  may be exposed to the plasma, but the active layer  106  over the gate electrode  102  may not be exposed to the plasma due to the presence of the etch stop  108 . The active layer  106  exposed to the plasma may etch at a slower rate than the metal layer  110  when exposed to the plasma. In one embodiment, the active layer  106  may not etch at all when exposed to the plasma. After the source and drain electrodes  112 A,  112 B have been defined, the photoresist mask may be removed. 
     After the plasma etching, the etch stop  108  and the source and drain electrodes  112 A,  112 B may be used as a mask during wet etching of the active layer  106  as shown in  FIG. 1H . The etch stop  108  and the source and drain electrodes  112 A,  112 B etch at a slower rate than the active layer  106  when exposed to the wet etchant. In one embodiment, the etch stop  108  and the source and drain electrodes  112 A,  112 B may not etch at all when exposed to the wet etchant. Hence, no additional mask layer needs to be deposited and patterned to perform the etching. The source and drain electrodes  112 A,  112 B as well as the etch stop  108  function as a mask when etching the exposed active layer  106 . Thus, no additional mask is deposited or removed and fewer masks are used than in previous methods. The wet etchant may comprise any conventional wet etchant that may etch the effective for etching the active layer  106  without etching the etch stop  108  and the source and drain electrodes  112 A,  112 B. The etchant may comprise an acid with a pH of less than 3 of a base with a pH higher than 10. In one embodiment, the etchant may comprise diluted HCl. In another embodiment, the etchant may comprise the same liquid as used for developing the photoresist. 
     A display electrode  114  may then be deposited over the gate dielectric layer  104  as shown in  FIG. 1I . The display electrode  114  may comprise a metal such as aluminum, tungsten, molybdenum, chromium, tantalum, and combinations thereof. A passivation layer  116  may then be deposited over the structure as shown in  FIG. 1J . The passivation layer  116  may be deposited to a thickness between about 1000 Angstroms to about 5000 Angstroms. In one embodiment, the passivation layer  116  may comprise silicon dioxide or silicon nitride. 
       FIG. 2  is a flow chart  200  of a TFT fabrication process according to one embodiment of the invention. In step  202 , the gate electrode is deposited onto the substrate. The gate electrode may be deposited as a layer and then etched utilizing a photoresist mask as the pattern. In one embodiment, the gate electrode may be pattern deposited onto the substrate. In step  204 , a gate dielectric layer may be blanket deposited over the substrate and gate electrode. An active layer may then be deposited over the gate dielectric layer in step  206 . An etch stop layer may then be deposited in step  208 . Following the deposition of the etch stop layer, the etch stop layer may be patterned to define an etch stop portion over the active layer above the gate electrode. The patterning may comprise depositing a photoresist layer thereover, patterning the photoresist layer to create a mask, and etching to remove undesired portions of the etch stop layer. The mask is then removed. 
     A metal layer may then be deposited in step  210 . The metal layer will eventually become the source and drain electrodes. In step  212 , the source and drain electrodes may be defined by depositing a second mask, etching the metal layer and then removing the second mask. In step  214 , the active layer may then be etched by using the source and drain electrodes as well as the etch stop layer as a mask without depositing and removing another mask. A display electrode may then be deposited in step  216  over the gate dielectric layer that was exposed when the active layer was etched. A passivation layer may then be deposited over the entire structure in step  218 . 
       FIGS. 3A-3D  show a TFT in various stages of processing according to another embodiment of the invention.  FIG. 3A  shows a structure comprising a substrate  302 , a gate electrode  304 , a gate dielectric layer  306 , an active layer  308 , an etch stop  310 , and a metal layer  312 . The structure shown in  FIG. 3A  may be formed in a manner similar to that discussed above in regards to  FIGS. 1A-1F . 
     After the metal layer  312  is deposited, the metal layer  312  and the active layer  308  may be etched to expose a portion of the gate dielectric layer  306  as shown in  FIG. 3B . The etching may comprise depositing a photoresist mask over the metal layer  312  and etching utilizing the mask. The area above the etch stop  310  and the gate electrode  304  may not be etched. The source and drain electrodes  316 A,  316 B may then be defined by etching. A photoresist layer may be deposited over the exposed gate dielectric layer  306  and the metal layer  312 . The photoresist layer may then be pattered to produce a mask. The source and drain electrodes  316 A,  316 B may then be defined by etching using the photoresist mask as shown in  FIG. 3C . The photoresist mask may then be removed. The display electrode has not been shown for clarity, but it is to be understood that the display electrode may be deposited before the passivation layer  314  is deposited. 
     A passivation layer  314  may then be deposited over the source and drain electrodes  316 A,  316 B, the etch stop  310 , and the exposed gate dielectric  306  as shown in  FIG. 3D . The etch stop  310  may function as a passivation layer for the active channel. Thus, it may not be necessary to have a passivation layer directly on the etch stop  310 . 
       FIG. 4  is a flow chart  400  of a TFT fabrication process according to another embodiment of the invention. In step  402 , a metal layer may be deposited over an etch stop and an active layer that has been previously deposited. The etch stop and the active layer may be disposed over a gate dielectric layer, a gate electrode, and a substrate. 
     In step  404 , the metal layer and the active layer may be etched without etching the active channel. In so doing, the gate dielectric layer may be exposed. A passivation layer may then be deposited over the exposed gate dielectric layer as well as the metal layer in step  406 . The passivation layer may then be etched in step  408 . In etching the passivation layer, the source and drain electrodes may be defined by etching the metal layer to expose the etch stop that is disposed over the active layer in an area corresponding to the gate electrode. 
     In between the gate dielectric layer deposition, the active layer deposition, and the etch stop deposition, the substrate may be maintained under vacuum. By maintaining the substrate in a vacuum state between the depositions, the various layers of the TFT are not exposed to the atmosphere where undesirable contaminants in the air may contaminate the TFT. Thus, the TFT maintained in a vacuum state during and between the depositions may have good quality and be produced at a low cost. In between the depositions, the TFT may be exposed to surface treatment processes as desired. Additionally, after the active layer deposition and/or after the etch stop layer deposition, the TFT may be annealed. 
     By utilizing the source and drain electrodes as well as an etch stop as a mask, the active layer may be etched without depositing and removing an additional mask. Without the additional mask, several processing steps of prior art methods may be obsolete. By utilizing fewer masks, substrate throughput may be increased. 
     While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.