Patent Publication Number: US-7917105-B2

Title: RF power amplifier controller circuit with compensation for output impedance mismatch

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation application of, and claims priority under 35 U.S.C. §120 from, U.S. patent application Ser. No. 11/623,030, entitled, “RF Power Amplifier Controller Circuit with Compensation for Output Impedance Mismatch,” filed on Jan. 12, 2007, which application claims priority under 35 U.S.C. §119(e) from U.S. Provisional Patent Application No. 60/764,947, entitled “RF Power Amplifier with Efficiency Improvement for High Peak to Average Modulation Types,” filed on Feb. 3, 2006, and which application is a continuation-in-part application of, and claims the benefit under 35 U.S.C. §120 from, U.S. patent application Ser. No. 11/429,119, entitled “Power Amplifier Controller Circuit,” filed on May 4, 2006, the subject matter of all of which are incorporated by reference herein in their entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a circuit for controlling RF PAs (Radio Frequency Power Amplifiers), and more specifically, to an RF PA controller circuit that controls the supply voltage of a PA using a closed amplitude control loop with an amplitude correction signal. 
     2. Description of the Related Art 
     RF transmitters and RF power amplifiers are widely used in portable electronic devices such as cellular phones, laptop computers, and other electronic devices. RF transmitters and RF power amplifiers are used in these devices to amplify and transmit the RF signals remotely. RF PAs are one of the most significant sources of power consumption in these electronic devices, and their efficiency has a significant impact on the battery life on these portable electronic devices. For example, cellular telephone makers make great efforts to increase the efficiency of the RF PA circuits, because the efficiency of the RF PAs is one of the most critical factors determining the battery life of the cellular telephone and its talk time. 
       FIG. 1  illustrates a conventional RF transmitter circuit, including a transmitter integrated circuit (TXIC)  102  and an external power amplifier (PA)  104 . For example, the RF transmitter circuit may be included in a cellular telephone device using one or more cellular telephone standards (modulation techniques) such as UMTS (Universal Mobile Telephony System) or CDMA (Code Division Multiple Access), although the RF transmitter circuit may be included in any other type of RF electronic device. For purposes of illustration only, the RF transmitter circuit will be described herein as a part of a cellular telephone device. The TXIC  102  generates the RF signal  106  to be amplified by the PA  104  and transmitted  110  remotely by an antenna (not shown). For example, the RF signal  106  may be an RF signal modulated by the TXIC  102  according to the UMTS or CDMA standard. 
     The RF power amplifier  104  in general includes an output transistor (not shown) for its last amplification stage. When an RF modulated signal  106  is amplified by the RF PA  104 , the output transistor tends to distort the RF modulated signal  106 , resulting in a wider spectral occupancy at the output signal  110  than at the input signal  106 . Since the RF spectrum is shared amongst users of the cellular telephone, a wide spectral occupancy is undesirable. Therefore, cellular telephone standards typically regulate the amount of acceptable distortion, thereby requiring that the output transistor fulfill high linearity requirements. In this regard, when the RF input signal  106  is amplitude-modulated, the output transistor of the PA  104  needs to be biased in such a way that it remains linear at the peak power transmitted. This typically results in power being wasted during the off-peak of the amplitude of the RF input signal  106 , as the biasing remains fixed for the acceptable distortion at the peak power level. 
     Certain RF modulation techniques have evolved to require even more spectral efficiency, and thereby forcing the RF PA  104  to sacrifice more efficiency. For instance, while the efficiency at peak power of an output transistor of the PA  104  can be above 60%, when a modulation format such as WCDMA is used, with certain types of coding, the efficiency of the RF PA  104  falls to below 30%. This change in performance is due to the fact that the RF transistor(s) in the RF PA  104  is maintained at an almost fixed bias during the off-peak of the amplitude of the RF input signal  106 . 
     Certain conventional techniques exist to provide efficiency gains in the RF PA  104 . One conventional technique is EER (Envelope Elimination and Restoration). The EER technique applies the amplitude signal (not shown in  FIG. 1 ) and the phase signal (not shown in  FIG. 1 ) of the RF input signal  106  separately to 2 ports of the power amplifier  104 , i.e., its supply voltage port (Vcc)  108  and its RF input port  107 , respectively. However, the EER technique fails to provide significant efficiency gains, because the supply voltage  108  cannot be varied in an energy-efficient way to accommodate the large variations in the amplitude signal of the RF input signal  106  and thus it fails to provide a substantial energy efficiency gain while maintaining the required linear amplification of the RF signal in the RF PA  104 . This is mainly due to the difficulty in realizing a fast, accurate, wide range, and energy efficient voltage converter to drive the supply voltage of the RF PA  104 . 
     The conventional EER technique can function better only if a variable power supply with a very large variation range is used to adjust the supply voltage based on the amplitude signal of the RF input signal  106 , while not reducing the efficiency of the RF transmitter by power consumed by the power supply itself. However, the variable power supply, which is typically comprised of a linear regulator (not shown in  FIG. 1 ) that varies its output voltage on a fixed current load such as the PA in linear mode, by principle reduces the supply voltage at constant current and by itself consumes the power resulting from its current multiplied by the voltage drop across the linear regulator when there is a large drop in the amplitude signal of the RF input signal  106 . This results in no change in the overall battery power being consumed by the RF transmitter, because any efficiency gained in the RF PA  104  is mostly lost in the linear regulator itself. Variations of the EER technique, such as Envelope Following and other various types of polar modulation methods, likewise fails to result in any significant gain in efficiency in the RF transmitter, because the supply voltage is likewise adjusted based on the amplitude signal of the RF input signal  106  which inherently has large variations and thus has the same deficiencies as described above with respect to conventional EER techniques. 
     Quite often, the conventional methods of controlling a PA fail to address the amplitude-to-phase re-modulation (AM-to-PM) which occurs in a non-frequency linear device such as a PA. Thus, the conventional methods are not suitable for the common types of PAs for use in common mobile telephony or mobile data systems because the required spectral occupancy performance is compromised by the AM to PM distortion. 
     PAs are typically used in conjunction with band pass filters that have a high electric coefficient of quality. These filters are typically of the SAW (surface acoustic wave) type. Due to their high coefficient of quality, the filters exhibit a relatively high group delay. The group delay makes it very difficult for a correction loop to work around the arrangement of the SAW filter and the PA while still meeting the high bandwidth requirements needed for the correction of the AM-to-PM. 
     In addition, it is advantageous for a RF PA circuit to detect and act upon load variations at the antenna to which the RF PA circuit is coupled. Especially, it is advantageous if the RF PA circuit acts upon the load variation in a way which does not require an adjustment of power from the TXIC  102 . Load variations can occur, for example, when the antenna is placed near a metal object and the normal electromagnetic field pattern of the antenna is disturbed. Such load variations would typically cause reduction in the radiated power from the antenna, in part due to the absorption of the antenna&#39;s radiated energy by the object in its proximity, and also in part due to the resulting difference between the expected and actual load impedance driven by the PA (which is referred to herein as “antenna impedance mismatch”). 
     In some radio systems, the receiving base station can detect the level of radiated power received from the transmitting radio and command the radio to increase the power level from its RF PA to compensate for load variations at the antenna of the transmitting radio. However, this requires intervention from and communication with the receiving base station, and the transmitting radio itself is not able to adjust the power level on its own. In addition, the RF PA may already be transmitting at its maximum expected power level and therefore not be able to honor the command from the receiving base station to increase the transmitting power level. The RF PA cannot increase its output power beyond its maximum expected power level, because doing so would increase distortion in the signal amplified by the RF PA to unacceptable levels. 
     Of course, the RF PA may be designed for a higher expected maximum power level and therefore generate a higher output power level to compensate for load variations at the antenna without increasing distortion to unacceptable levels. However, such an RF PA would suffer from poorer efficiency when operated at normal power levels (when the antenna is not subject to load variation), because the RF PA in such case would have to operate at a greater backoff from its peak output power and thus operate at a greater distance from saturation. Thus, a tradeoff should be made between the efficiency of the RF PA under normal operating power levels and the ability of the RF PA to supply additional power to compensate for load variations at the antenna. 
     The RF output power leveling circuit may erroneously reduce the power of the RF PA when there are load variations at the antenna because of the directional coupler that may be employed in the RF PA circuit in line with the output of the RF PA. The RF output power leveling circuit is commonly employed in cellular radios and typically employs a directional coupler to measure, regulate, or control the output power from the RF PA. Typically, the output power from the forward coupled port of the directional coupler is correlated tightly to the radiated power from the antenna. However, when there are load variations at the antenna, the directional coupler may report a power level higher than the actual radiated power at the antenna, because the directional coupler does not measure the reduction in power delivered by the RF PA caused by the antenna impedance mismatch. Thus, the RF output power leveling circuit may erroneously reduce the power of the RF PA when there are load variations at the antenna. In addition, antenna impedance mismatch seen at the RF PA output may cause an increase in power dissipated by the PA, resulting in undesirable heating in the RF PA circuit. 
     Thus, there is a need for an RF PA system that is efficient over a wide variety of modulation techniques and results in a significant net decrease in power consumption by the RF PA circuit. There is also a need for a PA controller that can correct the AM to PM effects, while not relying on a PA specially designed for low AM to PM at the expense of efficiency. In addition, there is a need for a PA controller that can exclude the use of SAW filters from the path of the correction loop in the PA circuitry. There is also a need for an RF PA system that can be designed to operate at a higher maximum expected output power level to compensate for load variations at the antenna, without reduced efficiency operating at normal power levels. There is also a need for an RF PA system that can compensate for antenna load variation and an RF PA system that is protected against excessive power dissipation that can be caused by antenna impedance mismatch. Finally, there is a need for an RF PA system that can minimize the distortion in the PA output when an output match compensation circuit is employed. 
     SUMMARY OF THE INVENTION 
     One embodiment of the present invention disclosed is a power amplifier controller circuit for controlling a power amplifier based upon an amplitude correction signal or amplitude error signal. The power amplifier receives and amplifies an input signal to the power amplifier and generates an output signal, and the power amplifier controller circuit controls the power amplifier so that it operates in an efficient manner. 
     The PA controller circuit comprises an amplitude control loop and a phase control loop. The amplitude control loop determines the amplitude correction signal (also referred to herein as the amplitude error signal), which is indicative of the amplitude difference between the amplitude of the input signal and the attenuated amplitude of the output signal, and adjusts the supply voltage to the power amplifier based upon the amplitude correction signal. The phase control loop determines a phase error signal, which indicates a phase difference between phases of the input signal and the output signal, and adjusts the phase of the input signal based upon the phase error signal to match the phase of the output signal. Thus, the phase control loop corrects for unwanted phase modulation introduced by the AM to PM non-ideality of the power amplifier and thus reduces phase distortion generated by the power amplifier. 
     In a first embodiment of the present invention, the amplitude control loop comprises an amplitude comparator comparing the amplitude of the input signal with an attenuated amplitude of the output signal to generate an amplitude correction signal, and a power supply coupled to receive the amplitude correction signal and generating the adjusted supply voltage provided to the power amplifier based upon the amplitude correction signal. The power supply can be a switched mode power supply. By using the amplitude correction signal to control the supply voltage to the power amplifier, a high-efficiency yet low-bandwidth power supply such as the switched mode power supply may be used to provide the adjusted supply voltage to the power amplifier. 
     In a second embodiment of the present invention, the amplitude correction signal is split into two or more signals with different frequency ranges and provided respectively to different types of power supplies with different levels of efficiency to generate the adjusted supply voltage provided to the power amplifier. For example, in the second embodiment, the power supplies include a first power supply with a first efficiency and a second power supply with a second efficiency higher than the first efficiency. The first power supply receives a first portion of the amplitude correction signal in a first frequency range and generates a first adjusted supply output based upon the first portion of the amplitude correction signal, and the second power supply receives a second portion of the amplitude correction signal in a second frequency range lower than the first frequency range and generates a second adjusted supply output based upon the second portion of the amplitude correction signal. The first and second adjusted supply outputs are combined to form the adjusted supply voltage provided to the power amplifier. The first power supply can be a linear regulator, and the second power supply can be a switched mode power supply. By dividing the amplitude correction signal into two or more signals with different frequency ranges, the second embodiment of the present invention has the additional advantage that the switched mode power supply may be implemented with even narrower bandwidth as compared to the first embodiment without significantly sacrificing efficiency. A narrower bandwidth power supply or a variable power supply with a smaller range of voltage variation is easier to implement. 
     In a third embodiment of the present invention, the amplitude control loop further comprises a gain control module receiving the amplitude correction signal to generate a gain control signal, and a variable gain amplifier adjusting the amplitude of the input signal according to the gain control signal. The third embodiment has the advantage that it is possible to operate the power amplifier at any given depth beyond its compression point, resulting in an extra degree of freedom in designing the PA circuit. This is useful in optimizing the efficiency gain versus spectral occupancy performance. By adding the variable gain amplifier, the amplitude of variation of the control voltage to the PA is further reduced, resulting in further significant efficiency gains. 
     In a fourth embodiment of the present invention, the amplitude control loop compensates for impedance mismatch with the load by increasing the power delivered from the power amplifier to the load. This is done without disrupting the amplitude control loop operation by further reducing the attenuated amplitude of the output signal fed to the amplitude comparator. In addition, the amplitude control loop may also decrease the output power of the power amplifier upon detection of excessive power dissipation in the power amplifier. This is done by increasing the attenuated amplitude of the output signal fed to the amplitude comparator. 
     In a fifth embodiment of the present invention, the amplitude control loop further includes an output match compensation circuit that can adjust the output impedance of the power amplifier to more closely match the impedance of the load, upon detecting an impedance mismatch between the output of the power amplifier and the load. 
     The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings. 
         FIG. 1  illustrates a conventional RF transmitter circuit. 
         FIG. 2  illustrates an RF transmitter circuit including the PA controller in accordance with the present invention. 
         FIG. 3A  illustrates an RF power amplifier circuit, in accordance with a first embodiment of the present invention. 
         FIG. 3B  illustrates a method of controlling the amplitude control loop of a RF PA circuit, in accordance with the first embodiment of the present invention. 
         FIG. 4A  illustrates an RF power amplifier circuit, in accordance with a second embodiment of the present invention. 
         FIG. 4B  illustrates a method of controlling the amplitude control loop of a RF PA circuit, in accordance with the second embodiment of the present invention. 
         FIG. 5A  illustrates an RF power amplifier circuit, in accordance with a third embodiment of the present invention. 
         FIG. 5B  illustrates a method of controlling the amplitude control loop of a RF PA circuit, in accordance with the third embodiment of the present invention. 
         FIG. 6  illustrates a method of controlling the phase control loop of a RF power amplifier circuit in accordance with the present invention. 
         FIG. 7  illustrates simulation results of the changes in the waveform of the supply voltage  208  to the PA corresponding to the conventional polar control method, the first embodiment of  FIG. 3A , and the third embodiment of  FIG. 5A , for a typical commercial WCDMA PA with 3.4 V nominal supply voltage and WCDMA modulation using 3.84 Mchips per second. 
         FIG. 8  illustrates the simulation results of an example of a time domain waveform present at the node  509  of  FIG. 5A  for a typical commercial WCDMA PA with 3.4 V nominal supply voltage and WCDMA modulation using 3.84 Mchips per second. 
         FIG. 9  illustrates the simulation results of an example of a time domain waveform present at nodes  401  and  403  of  FIG. 5A  for a typical commercial WCDMA PA with 3.4 V nominal supply voltage and WCDMA modulation using 3.84 Mchips per second. 
         FIG. 10A  illustrates an RF power amplifier circuit, in accordance with a fourth embodiment of the present invention. 
         FIG. 10B  illustrates a method of controlling the amplitude control loop of a RF PA circuit, in accordance with the fourth embodiment of the present invention. 
         FIG. 10C  illustrates an RF power amplifier circuit, in accordance with a fifth embodiment of the present invention. 
         FIG. 10D  illustrates a method of controlling the amplitude control loop of a RF PA circuit, in accordance with the fifth embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     The Figures (FIG.) and the following description relate to preferred embodiments of the present invention by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of the claimed invention. 
     Reference will now be made to several embodiments of the present invention(s), examples of which are illustrated in the accompanying figures. Wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the present invention for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the invention described herein. 
       FIG. 2  illustrates an RF transmitter circuit including the PA controller  202  in accordance with the present invention. The PA controller  202  is placed between the transmitter IC  102  and the PA  104  to receive the RF signal  204  from the TXIC  102  and provide the RF signal  206  to the PA  104 , while controlling the PA  104  by way of an adjusted supply voltage  208 . The PA controller  202  is also placed between the power supply line (Vcc)  210  and the PA  104 . The PA  104  amplifies the RF signal  206  to output the amplified RF output signal  110 , which is also provided as a feedback signal back to the PA controller  202 . As will be explained below with reference to  FIGS. 3A ,  3 B,  4 A,  4 B,  5 A, and  5 B, the adjusted supply voltage  208  is generated by the PA controller  202  based on an amplitude correction signal (not shown in  FIG. 2 ) indicative of the difference between the attenuated amplitude of the feedback RF output signal  110  and the amplitude of the RF input signal  204 . Note that the term “amplitude correction signal” is used herein synonymously with the term “amplitude error signal.” The PA controller  202  adjusts the supply voltage (Vcc)  210  based upon the amplitude correction signal to generate the adjusted supply voltage  208  provided to the PA  104 , to optimize the efficiency of the PA  104 . An advantage of the PA controller  202  is that existing signal connections to the PA  104  and the TXIC  102  need not change when the PA controller  202  is inserted between the TXIC  102 , the PA  104 , and the supply voltage (Vcc)  210 . 
     The PA controller circuit  202  may also adjust the phase and amplitude of the signal  204  to allow for power control and PA ramping, in accordance with information received through the configuration signals  209 . Since the PA controller circuit  202  is aware of the voltage at the output and the current in the power amplifier  104 , it can also adjust for load variations at an antenna (not shown herein) that may be used with the PA. If a directional coupler (not shown) is used to feed the attenuated amplitude of the signal  204 , the PA controller  202  can adjust the forward power while controlling the PA operation point as it is aware of the voltage and current at node  208 . 
       FIG. 3A  illustrates an RF PA circuit, according to a first embodiment of the present invention. The RF PA circuit includes the PA  104 , and the PA controller  202  including a closed amplitude control loop and a closed phase control loop. 
     The phase control loop includes two limiters  312 ,  314 , a phase comparator  316 , a loop filter (PLF (Phase Loop Filter))  318 , and a phase shifter  320 . To achieve stability over all conditions, the phase comparator  316  is of an adequate type with a capture range greater than 2*PI. To achieve this, a combination of adjustable delay elements and frequency dividers may be used. Also a phase sub-ranging system can be used since the dynamic phase variations that the phase correction loop processes are limited in amplitude. A sub-ranging phase control block (not shown) could be one of the constituents of the phase comparator  316  used with this system. Advantages of using sub-ranging in the phase comparator  316  are stability and good noise. 
     The amplitude control loop includes an adjusted variable attenuator (RFFA (RF Feedback Attenuator))  306 , two matched amplitude detectors  302 ,  304 , a comparator  308 , and a switched mode power supply (SMPS)  310 . Note that the limiter  312  and the detector  302 , and the limiter  314  and the detector  304 , can be combined into a single limiter/power detector blocks without altering the functionality of the system. 
     Referring to  FIG. 3A , the phase control loop monitors the RF input signal  204  from the transmitter IC  102  (not shown in  FIG. 3A ) and compares the phase of the RF input signal  204  with the phase of the output signal  110  of the PA  104  attenuated  326  by the adjusted variable attenuator (RFFA)  306 , resulting in a control signal  319  that varies the phase of the RF signal  206  coming out of the phase shifter  320 . More specifically, the limiter  312  receives the RF input signal  204  from the TXIC  102  and outputs to the comparator  316  an amplitude limited signal  324  mathematically representative of the phase of its input signal. The limiter  314  also receives the output signal  110  of the PA  104  as attenuated  326  by the adjusted variable attenuator (RFFA)  306 , and outputs its phase signal  325  to the comparator  316 . The comparator  316  compares the phases of the output signals  324 ,  325  of the two limiters  314 ,  316 , and generates a phase error signal  317 . Note that the term “phase error signal” is used herein synonymously with the term “phase correction signal.” The phase error signal  317  is filtered by the loop filter (PLF)  318  to generate the phase control signal  319 . The loop filter  318  completes the phase loop and provides the necessary gain, bandwidth limitation, and loop stability required for the phase loop to function properly. The particular loop filter used here can be of any type, and can include multiple integration and derivation stages so as to satisfy the best loop performance. The types of the loop filter may include classical types I, II, and the like. A particularity of this phase loop design is that the group delay through the PA  104  must be taken into account for stability reasons. This is achieved by choosing the proper pole-zero placement in the loop filter and may include delay compensation. The phase control signal  319  is input to the phase shifter  320  to control the shifting of the phase of the input RF signal  206  so that the phase of the output signal  110  dynamically matches the phase of the transmitter signal  204 . 
     The function of the phase control loop is to counteract the AM (Amplitude Modulation) to PM (Phase Modulation) characteristics of the PA  104 , which is part of the normal distortion characteristics of transistor-based amplifiers, allowing for the phase of the RF signal to be the same at the output  110  of the PA  104  as it is at the input  204  of the phase shifter  320  and thus reducing phase distortion generated by the PA  104 . This phase control loop contributes to linearizing the PA  104  as the AM to PM phase shift of the PA  104  tends to become higher at higher power levels. By limiting the effects of AM to PM of the PA  104 , the phase control loop allows the PA  104  to function at higher power levels with less distortion for the output signal  110 , thus allowing the use of the PA  104  in more favorable efficiency conditions. In addition, the phase control loop also helps in correcting any additional AM to PM characteristics that the amplitude control loop (described below) may cause. While  FIG. 3A  shows the phase shifter circuit  320  controlling the input to the PA  104 , it is also possible to place the phase shifter  320  at the output of the PA  104  with the same benefits. 
     Note that the phase control loop is of the error correction only type. In other words, the phase control loop does not modify the phase of the input signal  204  to the PA  104  unless the PA  104  or the amplitude control loop introduces a phase error. Since the noise contributions of the feedback loops affect the overall signal quality of the RF transmitter, an error correction only loop such as the phase control loop shown in  FIG. 3A  by definition introduces only a small correction, hence has a low noise contribution. 
     The amplitude control loop is also of the error correction only type, and thus is referred to herein as the amplitude correction loop. Thus, amplitude control loop and amplitude correction loop are used synonymously herein. Referring to  FIG. 3A , the amplitude of the RF input signal  204  is monitored through the amplitude detector  302  and compared by the comparator  308  with the amplitude at the output  110  of the PA  104  as attenuated  326  by the adjusted variable attenuator (RFFA)  306 , seen through a matched amplitude detector  304 . The attenuator  306  is adjusted such that the output  110  of the PA  104  is at a desired level. This can be achieved though programming  321  the variable attenuator (RFFA)  306  by either a digital input to the PA controller  202  or by analog control of the variable attenuator (RFFA)  306 . The comparator  308  generates an error signal  309  indicating the difference between the amplitude of the input RF signal  204  and the attenuated amplitude  326  of the output RF signal  110 , referred to herein as the “amplitude correction signal”  309 . The amplitude correction signal  309  is fed into power supply  310 , which is a switch mode power supply (SMPS). The SMPS  310  generates an adjusted supply voltage  208  provided to one or more supply voltage pins of the PA  104  based upon the amplitude correction signal  309 . The adjusted supply voltage  208  in essence operates as a bias control signal that controls the operating point of the PA  104 . 
     For a given output power, adjusting the supply voltage  208  of the PA  104  has the effect of varying its gain, as well as changing its efficiency. For a given output power, lowering the supply voltage  208  to the PA  104  provides better efficiency for the PA  104 . The adjusted supply voltage  208  of the PA  104  is adjusted to ensure that the PA  104  stays in its most efficient amplification zone. Because adjusting the supply voltage  208  of the PA  104  does make a change to the gain of the PA  104 , the output amplitude of the PA  104  changes with the supply voltage  208  from the SMPS  310 , and the amplitude control loop can be closed. The principles of such operation can be explained as follows. 
     When the input to the PA  104  increases, the output of the PA  104  also increases. As the PA  104  stays in its linear region of operation, which corresponds to small input signals, its output will increase linearly with its input. Thus, both inputs to the comparator  308  will rise by the same amount, resulting in no error correction and no change to the supply voltage  208 . This is the case when the output power is relatively small and well below the saturation point. 
     As the input power continues to rise at the input of PA  104 , there will be a point beyond which the output of the PA  104  will no longer be directly proportional with the input to the PA  104 . The amplitude control loop will detect this error between the output and input of the PA  104 , and raise the supply voltage to the PA  104  such that the initially-desired output power is delivered, resulting in linear operation of the system, even with a non-linear PA  104 . 
     In a practical application, the PA  104  will be fully or partially saturated from its Vcc, for example, the highest 10 dB of its output power range, and as the RF modulation of the RF signal  204  forces the amplitude to vary, the amplitude control loop will only be actively controlling the supply voltage  208  to the PA  104  when the highest powers are required. For lower input power, the amplitude control loop will leave the supply voltage  208  at a fixed level because it detects no gain error, resulting in a fixed gain for the PA  104 . The depth beyond compression can be adjusted by setting the level of the input signal  204  and the level of the attenuator  306 , as well as the default supply voltage Vcc (not shown in  FIG. 3A ) to the PA  104 . This behavior is illustrated in  FIG. 7  where simulation results compare the behavior of the conventional polar architecture (with no feedback) where the supply voltage to the PA swings between 0.1 V and 2.9 V and reaches a minimum value around 0.1 V as shown with curve  701 , while the supply voltage  208  to the PA  104  in the first embodiment of  FIG. 3A  using the amplitude correction signal  309  does not drop below 0.5 V as shown with curve labeled  702 . The amplitude swing in the dual gain control method is clearly further reduced as indicated by curve  703 , as will be explained in detail below with respect to the third embodiment of the present invention with reference to  FIGS. 5A and 5B . 
     Varying the supply voltage to the PA  104  also results in a phase change. Thus, the phase control loop described above operates in conjunction with the amplitude control loop to maintain the accuracy of RF modulation at the output signal of the PA  104 . Note that the phase control loop is also an error correction loop only, and therefore minimally contributes to noise. 
     Furthermore, the amplitude correction loop has the advantage that an SMPS  310 , which does not consume any significant power by itself and thus actually increases the efficiency of the overall RF power amplifier circuit, can be used to generate the adjusted supply voltage  208  to the PA  104 . This is possible because the adjusted supply voltage  208  to the PA  104  is generated by the SMPS  310  based upon the amplitude correction signal  309  which by nature has a much narrower range of variation or fluctuation rather than the actual amplitude of the RF input signal  204  which by nature has a much wider range of variation or fluctuation. An SMPS  310  is easier to implement to follow the amplitude correction signal  309  with a narrow range of variation, but would be more difficult to implement if it had to follow the unmodified amplitude of the RF input signal  204 . This is related to the fact that the amplitude signal itself has its fastest variations when the amplitude itself is low. The amplitude correction loop does not need to make any changes to its output when the PA is operating in linear mode. For example, the amplitude correction signal  309  may be only active for the highest 10 dB of the actual output power variation. In contrast, the amplitude signal itself may vary by 40 dB, and varies much faster between −10 dBc to −40 dBc than it does between 0 dBc to −10 dBc. Thus the bandwidth requirements on the SMPS  310 , which are coupled with the rate of change of the voltage, are reduced when an amplitude correction signal  309  rather than the amplitude signal itself is used to control the supply of the PA  104 . The SMPS  310  does not consume any significant power by itself, and thus does not significantly contribute to usage of the battery power, and actually increases the efficiency of the RF power amplifier circuit. In contrast, a conventional polar modulation technique typically utilizes the amplitude signal itself to adjust the supply voltage to the PA  104 , which prevents the use of an SMPS  310  for wideband RF signals because of the higher bandwidth requirements. Therefore, conventional RF power amplifier control systems typically use linear regulators (rather than an SMPS) to adjust the supply voltage to the PA  104 . Such a linear regulator by itself consumes power resulting from its current multiplied by the voltage drop across the linear regulator. When there is a large drop in the amplitude signal, this can result in significant power being lost and results in none or little reduction in the overall battery power being consumed by the RF transmitter. This is because any efficiency gained in the RF PA is mostly lost in the linear regulator itself. 
     It should be clear that the efficiency of the PA  104  with the PA controller circuit of  FIG. 3A  remains high for a substantial range of output power levels, and that the efficiency does not decrease significantly as the output power of the level of the PA  104  is lowered. In contrast, a conventional PA  104  without such a PA controller circuit suffers from lower efficiency as the output power is lowered. This is because the typical PA operates at increasing distance from saturation when operating at lower power levels, whereas the PA using the PA controller circuit of  FIG. 3A  operates fully or partially saturated from its supply voltage. Thus, designing the PA with the PA controller circuit of  FIG. 3A  with the ability to provide extra power (e.g., 2 dB), for example to compensate for load variations at the antenna, does not result in a substantial reduction of efficiency compared to the PA operating at normal (e.g., 24 dBm) output power level. In contrast, the conventional PA without such a PA controller circuit would drop the efficiency significantly if it is designed to provide extra power to compensate for load variations at the antenna. Therefore, the PA controller of  FIG. 3A  is well-suited for compensating for load variations at the antenna, as will be explained below with reference to  FIGS. 10A-10D . 
       FIG. 3B  illustrates a method of controlling the amplitude control loop of a RF PA  104  in an RF PA circuit, according to the first embodiment of the present invention. Referring to both  FIGS. 3A and 3B , as the process begins  352 , the comparator  308  compares  354  the amplitude  323  of the RF input signal  204  with the attenuated amplitude  322  of the RF output signal  110  from the PA  104  to generate an amplitude correction signal  309 . The SMPS  310  generates  358  an adjusted supply voltage  208  provided to the PA  104  based upon the amplitude correction signal  309 , and the process ends  360 . 
       FIG. 4A  illustrates an RF PA circuit, according to a second embodiment of the present invention. The RF PA circuit illustrated in  FIG. 4A  is substantially the same as the RF transmitter circuit illustrated in  FIG. 3A , except that (i) the amplitude correction signal  309  is split into two signals, a high frequency amplitude correction signal  401  that is fed into a high frequency path including a linear regulator  402  and a low frequency amplitude correction signal  403  that is fed into a low frequency path including an SMPS  404  and that (ii) the outputs of the linear regulator  402  and the SMPS  404  are combined in the adder block  406  to generate the adjusted supply voltage  208  to the PA  104 . For example, a simple current adding node, a small, high frequency transformer or other types of active electronic solutions can be used as the adder block  406 . 
     The high frequency amplitude correction signal  401  is input to the linear regulator  402 , which generates the high frequency part  405  of the adjusted supply voltage  208 . The low frequency amplitude correction signal  403  is input to the SMPS  404 , which generates the low frequency part  407  of the adjusted supply voltage  208 . The adder block  406  combines the high frequency part  405  and the low frequency part  407  to generate the adjusted supply voltage  208  to the PA  104  in order to keep the PA  104  in an efficient operation range. 
     The amplitude correction signal  309  is split into the high frequency amplitude correction signal  401  and the low frequency amplitude correction signal  403  using the high pass filter  410  and the low pass filter  411 , respectively. The high frequency amplitude correction signal  401  comprised of components of the amplitude correction signal  309  higher than a predetermined frequency and the low frequency amplitude correction signal  403  is comprised of components of the amplitude correction signal  309  lower than the predetermined frequency. The predetermined frequency used to split the amplitude correction signal  309  can be set at any frequency, but is preferably set at an optimum point where the efficiency of the overall RF transmitter circuit becomes sufficiently improved. For example, the predetermined frequency can be as low as 1/20 th  of the spectrally occupied bandwidth for the RF signal. In other embodiments, the predetermined frequency may not be fixed but may be adjusted dynamically to achieve optimum performance of the RF transmitter circuit. 
     Power consumed by the linear regulator  401  from a power source such as a battery (not shown) for a given control voltage  208  on the PA  104  can be approximated as follows: 
     
       
         
           
             
               
                 
                   
                     P 
                     bat 
                   
                   ≈ 
                     
                   ⁢ 
                   
                     
                       
                         I 
                         pa 
                       
                       × 
                       
                         V 
                         pa 
                       
                     
                     + 
                     
                       Effl 
                       × 
                       
                         ( 
                         
                           Vcc 
                           - 
                           
                             V 
                             pa 
                           
                         
                         ) 
                       
                       × 
                       
                         I 
                         pa 
                       
                     
                   
                 
               
             
             
               
                 
                   ≈ 
                     
                   ⁢ 
                   
                     Effl 
                     × 
                     Vcc 
                     × 
                     
                       I 
                       pa 
                     
                   
                 
               
             
           
         
       
     
     with Effl=1.05, which is sufficiently close to 1 to allow for this approximation, where P bat  is the power from the battery, I pa  is the input current to the PA  104 , V pa  is the input supply voltage to the PA  104 , and Vcc is the supply voltage of the battery. In addition, power consumed by the SMPS  404  from a power source such as a battery (not shown) for a given control voltage  208  on the PA  104  can be approximated as follows:
 
 P   bat   =Effs*I   pa   *V   pa  
 
     with Effs=1.1, 
     and the efficiency of the switch (not shown) in the SMPS generally exceeding 90%. 
     If the average input voltage V pa  to the PA  104  is significantly lower than supply voltage Vcc of the battery, the SMPS  404  achieves much lower power consumption. While the linear regulator  402  is generally less efficient than the SMPS  404 , the linear regulator  402  processing the high frequency part  401  of the amplitude correction signal  309  does not make the overall RF PA circuit inefficient in any significant way, because most of the energy of the amplitude correction signal  309  is contained in the low frequency part  403  rather than the high frequency part  401 . This is explained below with reference to  FIGS. 8 and 9 . 
     Using both a high efficiency path comprised of the SMPS  404  carrying the low frequency portion  403  of the amplitude correction signal  309  and a low efficiency path comprised of the linear regulator  402  carrying the high frequency portion  401  of the amplitude correction signal  309  has the advantage that it is possible to use an SMPS  404  with a limited frequency response. In other words, the SMPS  404  need not accommodate for very high frequencies but just accommodates for a limited range of lower frequencies of the amplitude correction signal  309 , making the SMPS  404  much easier and more cost-effective to implement. Combining the SMPS  404  with the linear regulator  402  enables high bandwidths of operation accommodating for full frequency ranges of the amplitude correction signal  309  without sacrificing the overall efficiency of the RF PA circuit in any significant way, since most of the energy of the amplitude correction signal  309  that is contained in the low frequency part  403  of the amplitude correction signal  309  is processed by the more efficient SMPS  404  rather than the less efficient linear regulator  402 . 
     For example, Table 1 below illustrates the percentage of energy contained in the various frequency ranges in a hypothetical simple 4QAM (Quadrature Amplitude Modulation) signal used in WCDMA cellular telephones and the overall efficiency that can be expected to be achieved by the RF transmitter according to the embodiment of  FIG. 4A  with the assumptions of the particular operating conditions as illustrated in Table 1. The combined amplitude and phase spectrum is 4 MHz wide. 
     
       
         
           
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 4QAM Signal 
                 Below 
                 Above 
                   
               
               
                 PA current = 100 mA 
                 100 KHz 
                 100 KHz (up to 
               
               
                 Adjusted supply voltage 
                 (Through 
                 40 MHz) 
                 All 
               
               
                 208 to PA = 60% of Vbat 
                 SMPS 
                 (Through Linear 
                 Frequen- 
               
               
                 on average 
                 404) 
                 Regulator 402) 
                 cies 
               
               
                   
               
             
            
               
                 Percentage of energy in 
                 83% 
                 17% 
                 100% 
               
               
                 adjusted supply voltage 
               
               
                 208 to PA 104 in 
               
               
                 designated bandwidth 
               
               
                 Efficiency of 
                 90% 
                 57% 
                  71% 
               
               
                 conversion at 60% of Vbat 
               
               
                 Current from battery 
                 66.66 mA 
                 17.85 mA 
                 84.51 mA 
               
            
           
           
               
               
            
               
                 Power supply system 
                 71% 
               
               
                 efficiency using high and 
               
               
                 low bandwidth paths 
               
               
                   
               
            
           
         
       
     
     Despite the extremely narrow bandwidth (100 KHz) of the SMPS  404  shown in the example of Table 1, 71% efficiency in the RF power amplifier supply system according to the embodiment of  FIG. 4A  can be expected under the above hypothetical conditions by using a 90% efficient SMPS  404  combined with a 57% efficient linear regulator  402 . This is a very significant improvement over conventional PA controller systems that would typically use only a linear regulator under the same operating conditions and thus would be only 57% efficient. By using an SMPS  404  with an increased bandwidth, it is possible to improve the efficiency of the RF power amplifier even further. 
       FIG. 4B  illustrates a method of controlling the amplitude control loop of a RF PA in an RF PA circuit, in accordance with the second embodiment of the present invention.  FIG. 4B  is explained in conjunction with  FIG. 4A . Referring to both  FIGS. 4A and 4B , as the process begins  452 , the comparator  308  compares  454  the amplitude  323  of the RF input signal  204  with the attenuated amplitude  322  of the RF output signal  110  from the PA  104  to generate an amplitude correction signal  309 . The low frequency part  403  of the amplitude correction signal  309  is applied  456  to the high efficiency SMPS  404  while the high frequency part  401  of the amplitude correction signal  309  is applied  456  to the low efficiency linear regulator  402 . The supply voltage  208  to the PA  104  is adjusted  460  based upon the combination of the outputs  407 ,  405  of the high efficiency SMPS  404  and the low efficiency linear regulator  402 , and the process ends  462 . 
       FIG. 5A  illustrates an RF PA circuit, according to a third embodiment of the present invention. The RF transmitter circuit illustrated in  FIG. 5A  is substantially the same as the RF transmitter circuit illustrated in  FIG. 4A , except that the gain control block  506  and the variable gain amplifier  502  are added to provide an additional means to control the efficiency of the PA  104  and the overall RF transmitter circuit. Although the third embodiment of  FIG. 5A  is illustrated herein as an improvement to the second embodiment of  FIG. 4A , note that the same concepts of the third embodiment of  FIG. 5A  can also be used to improve the first embodiment of  FIG. 3A . 
     More specifically, the gain control block  506  receives the amplitude correction signal  309  and adjusts the gain of the variable gain amplifier  502  based upon the amplitude correction signal  309 , as well as passing the low frequency and high frequency parts  403 ,  401  of the amplitude correction signal  309  to the SMPS  404  and the linear regulator  402 , respectively, to generate the adjusted supply voltage  208  as explained above with reference to  FIG. 4A . By monitoring the amplitude of the amplitude correction signal  309  input to the gain control block  506 , a control signal  504  is created to further compensate the gain of the variable gain amplifier  502  before the PA  104 . This arrangement allows the use of even lower bandwidth for the PA controller system as compared to that of the second embodiment described in  FIG. 4A  above. Also the programmability of the output power can now be entirely left to the PA controller  202 , while in the embodiment of  FIG. 4A  changing the output power required a change in gain in the transmitter IC  102 . 
     With the addition of the variable gain amplifier  502  and the gain control block  506 , it is possible to use the PA  104  at any given depth beyond its compression point. The term “depth beyond compression” is used herein to refer to the difference between the averaged input compression level of the PA  104  and the actual averaged input power at the PA  104 . For instance, when the peak output power is required, the input to the PA  104  can be overdriven by 10 dB beyond the 1 dB compression point of the PA  104 . It is also possible to adjust the supply voltage of the PA  104  at the instant when the peak power is required, such that the 1 dB compression point is set higher and it is only necessary to overdrive the PA  104  input by 3 dB to obtain the same output peak power. A dynamic adjustment of both the input level and the supply voltage allows this loop system to reduce significantly further the amplitude of the control voltage  208 . 
     In the embodiment of  FIG. 5A , the independent programming of gain and compression point by the closed amplitude control loop also makes it possible to reduce the amount of high frequency energy that the power supply system (linear regulator) has to deliver to the PA  104 . This can be done by having the variable gain amplifier  502  correct for some of the gain error at a higher speed than the Vcc control loop (closed on node  208 ) can do, thus reducing the amount of correction that is to be done by the low efficiency, high frequency branch (linear regulator  401 ). Thus, the bandwidth of the signals at nodes  208  and  504  can be made to be significantly different. Since only a small fraction of the energy resides at high frequencies, there is only a small penalty in efficiency for reducing the bandwidth of the control at node  208  relative to the bandwidth at node  504 . The ratio of the two active bandwidths is part of the design trade-off for the whole system. The gain control block  506  adjusts the compression point while the gain loop remains closed through the variable gain amplifier  502 . This allows the RF controller system to search an optimum depth beyond compression (as measured by the absolute value of the amplitude correction signal  309  or alternatively by the averaged value of the gain control  504 ) and efficiency with less effect on the resulting signal quality. The search for the optimum depth beyond compression can be made by a slow control loop which monitors the absolute value of the amplitude correction signal  309 , as well as its derivative. Another alternative is to monitor the averaged value of the gain control signal  504 . In order to control the relative action of both amplitude controls  504  and  208 , and in particular control the maximum voltage at node  208 , a control system for the compression level of the variable gain amplifier  502  can be implemented. Because in the embodiment of  FIG. 5A  both the supply voltage  208  to the PA  104  and the input  508  to the PA  104  can be adjusted, this embodiment inherently offers greater flexibility in design by exploiting two sources of signal information for control. This allows to further reduce the amplitude of the variation of the voltage control signal  208 , as shown on  FIG. 7 , where the voltage with the smallest variation is the signal labeled  703 , corresponding to this third embodiment of  FIG. 5A . 
     In addition, the third embodiment of  FIG. 5A  is also well suited to process directly a polar representation of the RF signal. In this case, an amplitude signal from the TXIC  102  would couple to the amplitude detector  302  and a phase only signal from the TXIC  102  would be coupled to the variable gain amplifier  502  and the limiter  312 . 
       FIG. 5B  illustrates a method of controlling the amplitude control loop of a RF PA in an RF transmitter circuit, in accordance with the third embodiment of the present invention. The method illustrated in  FIG. 5B  is substantially the same as the method illustrated in  FIG. 4B , except that step  512  is added. In step  512 , the input signal  508  to the PA  104  is adjusted, by use of a variable gain amplifier  502 , based upon the amplitude correction signal  309 . Therefore, the method of  FIG. 5B  is provided with an additional means for controlling the efficiency of the PA  104  and the overall RF PA circuit. 
       FIG. 6  illustrates a method of controlling the phase control loop of a RF PA in an RF PA circuit in accordance with the present invention. The phase control method of  FIG. 6  can be used with any one of the methods of controlling the amplitude correction loops described in  FIGS. 3B ,  4 B,  5 B,  10 B, and  10 D, as shown in  FIGS. 3A ,  4 A,  5 A,  10 A, and  10 C. The method of  FIG. 6  will be explained in conjunction with  FIGS. 3A ,  4 A, and  5 A. 
     As the process begins  602 , the comparator  316  compares  604  the phase of the RF input signal  204  with the phase of the attenuated RF output signal  326  from the PA  104  to generate the phase error signal  317 . The phase error signal  316  is filtered  606  by the loop filter (PLF)  318  to generate the phase control signal  319 . The phase of the input RF signal  204  is shifted  608  based upon the phase control signal  319  so that the phase of the input signal  204  dynamically matches the phase of the output RF signal  110 , and the process ends  610 . 
       FIG. 7  illustrates simulation results of the changes in the waveform of the supply voltage  208  to the PA corresponding to the conventional polar control method, the first embodiment of  FIG. 3A , and the third embodiment of  FIG. 5A , for a typical commercial WCDMA PA with 3.4 V nominal supply voltage and WCDMA modulation using 3.84 Mchips per second. As explained previously, the adjusted supply voltage  208  generated by a conventional polar system as indicated by curve  701  varies the most with wide fluctuations, the adjusted supply voltage  208  generated by the first embodiment of  FIG. 3A  as indicated by curve  702  varies less than the curve  701 , and the adjusted supply voltage  703  generated by the third embodiment of  FIG. 5A  varies the least with only a little fluctuation. 
       FIG. 8  illustrates the simulation results of an example of a time domain waveform present at node  509  (which voltage would be the same as the voltage at node  309 ) of  FIG. 5A , and  FIG. 9  illustrates the simulation results of an example of a time domain waveform present at nodes  401  and  403  of  FIG. 5A , both for a typical commercial WCDMA PA with 3.4 V nominal supply voltage and WCDMA modulation using 3.84 Mchips per second. The loop voltage versus time on  FIG. 8  shows that the loops maintain a voltage much lower than 2.5 V most of the time, except for some short instants. This is due to the signal&#39;s amplitude characteristics which require high peaks but a much lower average. In  FIG. 9 , the voltages  401  and  403  are shown. They correspond to the voltage  309  (or  509 ) after filtering by a 100 kHz high pass filter  410  and a 100 kHz low pass filter  411 , respectively. It can be seen that the low pass filtered signal  403  is almost a DC signal of value 1.9 V, while the high pass filtered signal  401  is a band limited waveform having a low DC value and an rms value of only 0.2V. If the 1.9V is generated with an efficiency of 90% by an easy-to-realize low output bandwidth SMPS  404 , and the 0.2V is generated with an efficiency of 60% using a linear amplifier  402 , the signal  309  can be generated with a combined efficiency of (1.9+0.2)/(1.9/0.9+0.2/0.6)=87.5%. This is much better than generating the signal  309  using a linear regulator with an average efficiency of (1.9/3.4)/1.05=53%. While it should be understood that the calculations presented herein are engineering approximations, the potential benefit in battery life is clearly apparent through this example. 
       FIG. 10A  illustrates an RF power amplifier circuit, in accordance with a fourth embodiment of the present invention. The RF transmitter circuit illustrated in  FIG. 10A  is substantially the same as the RF transmitter circuit illustrated in  FIG. 5A , except that the antenna load detect circuit  1002  and the antenna load variation control circuit  1004  are added to provide means to compensate for impedance mismatch between the RF PA circuit and the antenna. Although the fourth embodiment of  FIG. 10A  is illustrated herein as an improvement to the third embodiment of  FIG. 5A , note that the same concepts of the fourth embodiment of  FIG. 10A  can also be used to improve the first embodiment of  FIG. 3A  or the second embodiment of  FIG. 4A . 
     The antenna load detect circuit  1002  detects load variation at the antenna as seen at the output  110  of the RF PA circuit. For example, the antenna load detect circuit  1002  may detect the impedance mismatch seen at the output  110  of the PA  110 , which indicates an antenna load mismatch. Impedance mismatch may be detected in a variety of ways, including (i) sensing the current into the PA  104 , (ii) sensing the reverse power port of the directional coupler (not shown) near the antenna, (iii) sensing the gain of the PA  104  under known supply voltage conditions, and/or (iv) sensing the VSWR (voltage standing wave ratio) at the output of the PA  104  and along a PCB trace. A combination of these sensed values together or separately may indicate to the antenna load detect circuit  1002  the level and angle of impedance mismatch at the output  104  of the PA, which information is passed onto the antenna load variation control circuit  1004 . Any other methods of detecting antenna load mismatch may also be used. 
     The antenna load variation control circuit  1004  generates a control signal  1008  that is used as the gain setting signal  321  to set the gain of the adjusted variable attenuator (RFFA)  306 . The control signal  1008  is generated in such a way as to compensate for the detected impedance mismatch. Specifically, the antenna load variation control circuit  1004  generates the control signal  1008  to increase the level of attenuation in the RFFA  306  and thereby decreasing the level of feedback output voltage  326  input to the amplitude comparator  308 . In turn, this would cause the adjusted supply voltage  208  to increase, thereby increasing the overall output power  110  of the PA  104  and compensating for the reduction in radiated power from the antenna caused by the antenna load mismatch. Note that the rate at which the output power  110  of PA  104  is adjusted in this manner, which is the rate of change of the detected impedance mismatch, is much lower than the bandwidth of the amplitude control loop, and so the compensating increase in power can be tracked accurately by the amplitude control loop. Additionally, the rate of change of the impedance mismatch is much slower than the modulation rate, and so has little effect on the tracking of the modulation. A benefit of this method of increasing the PA output power is that the RF input  204  from TXIC  102  does not need to change its level, thus obviating the need for an additional control signal to command TXIC  102  to adjust its output level. The TXIC  102  may be physically located in a different section of the radio, requiring a lengthy control line, and further, may not have a proper interface to accept such an additional control signal. 
     Although not shown in  FIG. 10A , in a less advantageous but still appropriate embodiment, the antenna load variation control circuit  1004  could also adjust the level of the RF input signal by a variety of means, including adjusting a variable attenuator, were one coupled to the input of the PA  104 , or commanding the TXIC  102  or a digital signal processor which generates the modulation (not shown) to adjust its output power, thereby increasing the overall output power  110  of the PA  104  and compensating for the reduction in radiated power from the antenna caused by the antenna load mismatch. 
     Also note that the current feeding the PA  104  at node  208  together with the adjusted supply voltage at node  208  may be sensed and input to the antenna load variation control circuit  1004 , as shown in  FIG. 10A . The power fed to the PA  104  can be determined by simply multiplying such voltage and current using a simple multiplier (not shown). If the power fed to the PA  104  is above a predetermined threshold (which may be determined by the rating of the PA for safe power consumption), the antenna load variation control circuit  1004  may then control the RFFA  306  to decrease its attenuation level to increase the output feedback voltage input to the amplitude comparator  308 . In turn, this results in reducing the adjusted supply voltage  208  and the overall output power of the PA  104  until a safe level of output power of the PA  104  is reached. 
     In addition, it is also possible to approximate the power dissipated in the PA  104  itself by subtracting a value approximating the output power of the PA  104  from the value of the voltage multiplied with the current entering the PA  104  at node  208 . The value approximating the output power of the PA  104  can be obtained by monitoring the forward coupled power port of the directional coupler (not shown) connected to the output of the PA  104 . If the power dissipated by the PA  104  is above a predetermined threshold (which may be determined by the rating of the PA for safe power dissipation), the antenna load variation control circuit  1004  may then control the RFFA  306  to decrease its attenuation level to increase the output feedback voltage input to the amplitude comparator  308 . In turn, this results in reducing the adjusted supply voltage  208  and the overall output power of the PA  104  until a safe level of power dissipation in the PA  104  is reached. 
       FIG. 10B  illustrates a method of controlling the amplitude control loop of a RF PA circuit, in accordance with the fourth embodiment of the present invention. The method illustrated in  FIG. 10B  is substantially the same as the method illustrated in  FIG. 5B , except that steps  1024  and  1022  are added. In step  1024 , the amplitude of the RF output signal is further attenuated by the RFFA  306  to increase the output power from the PA  104  in order to compensate for the reduction in the PA output power  104  that would have been caused by the impedance mismatch. In step  1022 , the attenuation of the amplitude of the RF output signal is decreased by the RFFA  306  to decrease the output power from the PA  104  in case the power fed to the PA  104  exceeds a safe predetermined threshold. These steps  1022  and  1024  are performed prior to step  454  to adjust the level of the output feedback voltage fed to the amplitude comparator  308 . 
       FIG. 10C  illustrates an RF power amplifier circuit, in accordance with a fifth embodiment of the present invention. The RF transmitter circuit illustrated in  FIG. 10C  is substantially the same as the RF transmitter circuit illustrated in  FIG. 5A , except that the antenna load detect circuit  1002 , the antenna load variation control circuit  1004 , and an output mismatch compensation circuit  1006  are added to provide means to compensate for impedance mismatch between the RF PA circuit and the antenna. In addition, the RF transmitter circuit illustrated in  FIG. 10C  is similar to the RF transmitter circuit illustrated in  FIG. 10A  except that the antenna load variation control circuit  1004  controls the output match compensation circuit  1006  rather than the gain setting signal  321  to the RFFA  306 . However, note that the fourth embodiment of  FIG. 10A  may be combined with the fifth embodiment of  FIG. 10C  to include the features of both embodiments. Although the fifth embodiment of  FIG. 10C  is illustrated herein as an improvement to the third embodiment of  FIG. 5A , note that the same concepts of the fifth embodiment of  FIG. 10C  can also be used to improve the first embodiment of  FIG. 3A  or the second embodiment of  FIG. 4A . 
     The antenna load detect circuit  1002  detects load variations and resulting impedance mismatches as explained above, which information is passed onto the antenna load variation control circuit  1004 . The antenna load variation control circuit  1004  controls the output match compensation circuit  1006  through a control signal  1010  generated based on the detected impedance mismatch. The output match compensation circuit  1006  transforms the output impedance of the PA  104  to more closely match the impedance toward the antenna, thus reducing the power loss caused by antenna impedance mismatch. The antenna load variation control circuit  1004  may, for example, cause the output match compensation circuit  1006  to step through a series of adjusted impedance transformations until an impedance mismatch is no longer detected by the antenna load variation control circuit  1004 . The output match compensation circuit  1006  may be implemented using, for example, varactor diodes to electronically adjust the capacitance within the output match compensation circuit  1006  to optimize the impedance match. Alternatively, FET (Field Effect Transistor) or PIN diode switches may enable or disable various parts of a circuit network within the output match compensation circuit  1006  to adjust its impedance and optimize the impedance match. Note that the output match compensation circuit  1006  may be implemented as part of the PA output matching network. 
     The use of the output match compensation circuit  1006  can add undesirable distortion to the PA output signal  1110 . This distortion may arise due to the high voltage swings present in the output match compensation circuit  1006 , which could modulate the capacitance of the varactor diodes (not shown) in the output match compensation circuit  1006 . Additionally, the impedance changes due to the opening or closing of the FET switches or PIN diodes may cause unwanted distortion in the output  110 . However, the closed amplitude control loop and/or closed phase control loop operations of the PA controller circuit of the present invention reduces this distortion and the distortion of the output match compensation circuit  1006 , and enables the use of the RF transmitter circuit of the fifth embodiment in  FIG. 10C  even in systems that are sensitive to distortion, such as WCDMA signals. 
       FIG. 10D  illustrates a method of controlling the amplitude control loop of a RF PA circuit, in accordance with the fifth embodiment of the present invention. The method illustrated in  FIG. 10D  is substantially the same as the method illustrated in  FIG. 5B , except that step  1026  is added. In step  1026 , the output impedance of the PA  104  is transformed by the output match compensation circuit  1006  to more closely match the impedance of the antenna. This provides additional means to the RF PA transmitter circuit of the fifth embodiment to compensate for load variation and output impedance mismatch. 
     Upon reading this disclosure, those of skill in the art will appreciate still additional alternative structural and functional designs for the RF power amplifier controller through the disclosed principles of the present invention. For example, although the embodiment in  FIG. 4B  splits the amplitude correction signal  309  into two frequency ranges, it is possible to split the amplitude correction signal  309  into more than two different frequency ranges for separate processing by adjustable power supply components. The power amplifier controller circuit can be used with any type of power amplifier for many different types of electronic devices, although the embodiments are described herein with respect to a RF PA controller used in cellular telephone applications. Examples of these applications include video signals and Manchester coded data transmissions. 
     For another example, digital techniques can be used to process some of the signals of the PA system described herein. Whether a signal is represented in an analog form or a digital form will not change the functionality or principles of operation of amplitude and phase control loops of the PA system according to various embodiments of the present invention. For instance, based on the observation of the amplitude error signal  309 , one could calculate a typical transfer function for the PA  104  and construct the signals that drive the PA at nodes  206 ,  208 , which is still a form of closed loop control. 
     Thus, while particular embodiments and applications of the present invention have been illustrated and described, it is to be understood that the invention is not limited to the precise construction and components disclosed herein and that various modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus of the present invention disclosed herein without departing from the spirit and scope of the invention as defined in the appended claims.