Patent Publication Number: US-2021193648-A1

Title: Compact protection device for protecting an integrated circuit against electrostatic discharge

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of United States Application for patent Ser. No. 16/406,534, filed May 8, 2019, which is a divisional of U.S. patent application Ser. No. 15/694,403, filed Sep. 1, 2017, now U.S. Pat. No. 10,340,265, which claims the priority benefit of French Application for Patent No. 1751731, filed on Mar. 3, 2017, the disclosures of which are hereby incorporated by reference in their entireties to the maximum extent allowable by law. 
    
    
     TECHNICAL FIELD 
     Embodiments relate to electronic devices, and notably those intended for the protection of components against electrostatic discharge (ESD: ElectroStatic Discharge). 
     BACKGROUND 
     In the field of microelectronics, an electrostatic discharge may occur at any time throughout the service life of an integrated circuit, and constitute a real problem for the reliability of the electronic components or modules of this integrated circuit, as well as a major cause of failure. 
     An electrostatic discharge generally results in a current peak varying in size (amplitude, magnitude) and brevity (time) between two terminals of an electronic module of the integrated circuit. 
     For an electrostatic discharge to take place, it is necessary that a first terminal of the module receives the discharge, e.g. on contact with an electrically charged body, and that a second terminal acts as a ground, e.g. by being in contact with a metal object. 
     Usually, an electrostatic discharge takes place when the integrated circuit is powered off, between two terminals from among the power supply terminal, the reference terminal, or one of the signal terminals, coupled to said module. 
     An ESD protection device is aimed at absorbing this current peak as much as possible in order to prevent it from flowing into the module, or a possible surge at the module&#39;s terminals. 
     There are various protections against electrostatic discharge, notably MOS hybrid operation transistors. 
     Hybrid operation transistors are MOS transistors comprising a parasitic bipolar transistor the operation of which involves an operation of this bipolar transistor and an operation of the MOS transistor in a sub-threshold mode. 
     The principle of a hybrid operation of a MOS transistor has been highlighted in the article by Galy, et al. “Ideal Gummel curves simulation of high current gain vertical BIMOS NPN transistor”, INT. J. ELECTRONICS, 1996, vol. 80 No. 6, 717-726 (incorporated by reference). This article is a theoretical study carried out on a vertical structure transistor having a gate length (channel length) of the order of a micron and validated by simulations, without any application of such a hybrid operation being mentioned. 
     Such a MOS hybrid operation transistor notably has the advantage of being resistant to ionizing radiation and it may generally be employed for mass consumer, space or military applications, in the digital and analogue fields. 
     The use of such a component in the context of the protection of circuits against electrostatic discharge has notably been described in International Patent Application No. WO 2011 089179 (and its U.S. equivalent patent publication 2013/0141824). 
     However, some ESD protection devices described in this international application may, in some cases, present some drawbacks. It has notably been observed that when the device is coupled between a signal terminal (input/output terminal) and a power supply terminal of the integrated circuit, and the environment of the integrated circuit is not correctly controlled, it is liable to be triggered during the operation of the integrated circuit (therefore in the absence of any electrostatic discharge), e.g. when the potential difference between the power supply terminal and the signal terminal is greater than or equal to the trigger threshold of the protection device. 
     This is liable to damage at least one part of the integrated circuit and/or generate operating errors. 
     There is, moreover, a need to reduce as much as possible the surface occupied by the protection device, in particular when it is distributed over the different signal terminals coupled to different electronic components or modules of the integrated circuit. 
     SUMMARY 
     According to one embodiment, an electronic device is provided that is capable of protecting an electronic component or module of an integrated circuit against electrostatic discharge occurring between any pair of terminals coupled to said component or module of an integrated circuit, and having a reduced footprint. 
     According to one aspect, an integrated circuit is provided, comprising: a power supply terminal intended to receive a power supply voltage, a reference terminal intended to receive a reference voltage, e.g. the ground, and at least one signal terminal intended to receive/transmit a signal, a first protection device coupled between said at least one signal terminal and the power supply terminal, at least one second protection device coupled between said at least one signal terminal and the reference terminal. 
     According to this aspect, the first protection device includes: a first MOS transistor a first electrode of which is coupled to said at least one signal terminal, a second electrode coupled to the power supply terminal, said at least one second protection device comprises a second MOS transistor a first electrode of which is coupled to said at least one signal terminal and a second electrode is coupled to the reference terminal, the gates of the first and second MOS transistors being directly or indirectly coupled to the reference terminal, and the substrate of the first and second transistors being coupled to the reference terminal via a common resistor. 
     Thus, an electronic component or module coupled to these three terminals is protected against electrostatic discharge occurring between the signal terminal and one or other of the reference and power supply terminals, and the connection of the substrate and the gate of the first transistor to a different terminal from the signal terminal advantageously makes it possible, when the integrated circuit is in operation, to prevent the gate of the first transistor from being polarized and the first transistor being triggered, i.e. switched on. 
     The gates of the first and second transistors may be directly coupled to the reference terminal, i.e. by a connection not involving any active or passive intermediate component, but only elements the only function of which is to transmit the signal, e.g. metal tracks, vias, etc. 
     As a variant, the gates of the first and second MOS transistors may be coupled to the reference terminal via a first trigger circuit, resulting therefore in an indirect coupling. 
     The first trigger circuit may be of any conventional structure and comprise, for example, another resistor connected between the gates of the first and second MOS transistors and the reference terminal, without any mutual connection between the gate and the substrate of each transistor. 
     However, it is more efficient for the first trigger circuit to comprise said common resistor. 
     Thus, the gate and the substrate of each MOS transistor are linked by this indirect coupling and the MOS transistor is in a configuration compatible with a hybrid operation of the type mentioned above. 
     According to one embodiment, the integrated circuit comprises a third protection device coupled between the power supply terminal and the reference terminal and including a third MOS transistor a first electrode of which is coupled to the power supply terminal and a second electrode is coupled to the reference terminal, and the gate of which is directly coupled to the reference terminal and the substrate is coupled to the reference terminal via the common resistor. 
     Thus, the integrated circuit is protected against electrostatic discharge flowing between the power supply terminal and the reference terminal. 
     According to another embodiment, the third MOS transistor a first electrode of which is coupled to the power supply terminal and a second electrode is coupled to the reference terminal, has its substrate coupled to the reference terminal via the common resistor, and its gate coupled to the reference terminal via a second trigger circuit. 
     Here again for reasons of efficiency, the second trigger circuit may comprise the common resistor. 
     Thus, here again the third protection device is compatible with the hybrid operation transistors, making it possible to improve the triggering of the protection devices. 
     According to one embodiment, the integrated circuit includes a first signal terminal and at least one second signal terminal, and at least one fourth protection device coupled between the first signal terminal and the second signal terminal and including a fourth MOS transistor a first electrode of which is coupled to the first signal terminal, a second electrode is coupled to the second signal terminal, the gate of which is directly coupled to the reference terminal, and the substrate of which is coupled to the reference terminal via the common resistor. 
     According to another embodiment, the fourth MOS transistor of this fourth protection device has its substrate coupled to the reference terminal via the common resistor, and its gate coupled to the reference terminal via a third trigger circuit. 
     The third trigger circuit may here again comprise the common resistor. 
     The transistors may be implemented in one and the same substrate and have mutually connected gates. 
     This notably makes it possible to have a more compact device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other advantages and features of the invention will appear on examining the detailed description of embodiments of the invention, in no way restrictive, and the accompanying drawings in which: 
         FIG. 1  is a schematic diagram of an electronic integrated circuit including electronic protection devices; 
         FIGS. 2 and 3  are schematic diagrams showing details of the electronic protection devices in  FIG. 1 ; 
         FIG. 4  is a schematic diagram of an electronic integrated circuit including electronic protection devices; 
         FIGS. 5 and 6  are schematic diagrams showing details of the electronic protection devices in  FIG. 4 ; 
         FIG. 7  is a schematic diagram of an electronic integrated circuit including electronic protection devices; 
         FIGS. 8 and 9  are schematic diagrams showing details of the electronic protection devices in  FIG. 7 ; and 
         FIG. 10  illustrates a top view of an integrated circuit. 
     
    
    
     DETAILED DESCRIPTION 
     In  FIG. 1 , the references DIS 1  and DIS 2  designate electronic protection devices for protecting at least one electronic component or module CMP of an electronic integrated circuit CI against electrostatic discharge (ESD according to an abbreviation well known to the person skilled in the art). 
     The electronic circuit CI comprises a power supply terminal B 1 , a reference terminal B 2  and a signal terminal B 3 , and the component CMP is coupled to each of these three terminals B 1 , B 2 , and B 3 . 
     As a guide, when the electronic circuit is in operation, the power supply terminal B 1  may receive a power supply signal, e.g. a positive voltage, the terminal B 2  may receive a reference signal, e.g. a constant negative voltage or a zero (ground) voltage. 
     The signal terminal B 3  may receive or transmit a data signal from or to the module CMP. 
     When the circuit CI is not in operation, the circuit CI may be subject to electrostatic discharge flowing between one or other of these terminals. 
     An electrostatic discharge usually results in a very short current pulse (e.g. a few microseconds) the amplitude of which is, for example, of the order of 2 amperes and typically occurs at the end of 10 nanoseconds. 
     This corresponds, for example, to a pulse potential difference applied between two terminals of the circuit CI through an R-L-C equivalent circuit, the peak voltage of which occurs at the end of 10 nanoseconds with an intensity of 1 to 4 kvolts HBM, e.g. 4 kvolts HBM for 2.5 amperes. 
     It is recalled here that the letters HBM are the abbreviation for “Human Body Model” well known to the person skilled in the art in the field of protection against electrostatic discharge and notably designate an electrical circuit aimed at modeling an electrostatic discharge delivered by a human being and usually used for testing the sensitivity of devices to electrostatic discharge. This HBM electrical circuit, which is the R-L-C equivalent circuit referred to above and to which a high voltage is applied, notably comprises a 100 pF capacitor which discharges through a 1.5 kilohm resistor in the device to be tested. Thus, in the present case, an electrostatic discharge of 4 kilovolts HBM means that a potential difference of 4 kilovolts is applied to the HBM electrical circuit. 
     Then it is advisable that this current pulse should flow through one of the protection devices DIS 1  and DIS 2  and not through the component CMP. 
     The devices DIS 1  and DIS 2  are consequently aimed at absorbing these current pulses occurring respectively between the power supply terminal B 1  and the signal terminal B 3 , and between the reference terminal B 2  and the signal terminal B 3 , or between the two terminals B 1  and B 2 . 
     As illustrated in  FIG. 2 , the devices DIS 1  and DIS 2  respectively include a first MOS transistor TR 1  and a second MOS transistor TR 2 , mounted in series between the power supply terminal B 1  and the reference terminal B 2 . 
     The drain D 1  of the first transistor TR 1  is coupled to the power supply terminal B 1 , the source S 1  of the first transistor TR 1  is coupled to the signal terminal B 3  and to the drain D 2  of the second transistor TR 2 , and the source S 2  of the second transistor TR 2  is coupled to the reference terminal B 2 . 
     The gate G 1  of the first transistor TR 1  and the gate G 2  of the second transistor TR 2  are directly coupled to the reference terminal B 2 . 
     A connection or a direct coupling is understood here as being a connection not involving any active or passive intermediate component, but only elements the only function of which is to transmit the signal, e.g. metal tracks, vias, etc. 
     The first transistor TR 1  is thus in a configuration commonly designated by the person skilled in the art by the abbreviation “GGNMOS” (for Gate Grounded NMOS). The substrate sb 1  of the first transistor TR 1  and the substrate sb 2  of the second transistor TR 2  are coupled here to the reference terminal B 2 , via a common resistor R 1 . For transistor threshold voltages of the order of 4 volts, the common resistor R 1  in this embodiment has a resistive value of 500 ohms. 
     However, according to the envisaged application, it would be possible to choose another resistance value. 
     In practice, the first transistor TR 1  and the second transistor TR 2  are implemented on one and the same substrate, as will be seen below. 
     In the presence of an electrostatic discharge flowing from the power supply terminal B 1  to the signal terminal B 3 , the voltage generated by the electrostatic discharge increases until it reaches the breakdown voltage of the drain-substrate junction of the first transistor TR 1 . 
     The substrate sb 1 , which corresponds here to the base of the parasitic bipolar transistor of the first MOS transistor TR 1 , is therefore polarized and the parasitic bipolar transistor (and therefore the first MOS transistor TR 1 ) is switched on. 
     As a guide, the transistor TR 1  is triggered here when the voltage at its terminals reaches 4.5 volts. 
     When the discharge flows in the other direction, i.e. from the signal terminal B 3  to the power supply terminal B 1 , the voltage generated by the electrostatic discharge increases until it reaches the breakdown voltage of the drain-substrate junction of the first transistor TR 1 . 
     The substrate sb 1 , which corresponds here to the base of the parasitic bipolar transistor of the first MOS transistor TR 1 , is therefore polarized and the parasitic bipolar transistor (and therefore the first MOS transistor TR 1 ) is switched on. 
     In this case, the triggering of the device DIS 1  is more progressive, i.e. for a voltage value at its terminals of less than 2.5 volts, the current intensity through the device DIS 1  increases linearly, and beyond 2.5 volts, the intensity of the current passing through the first device DIS 1  increases exponentially, while the voltage at the terminals of the first transistor TR 1  approaches 3.5 volts asymptotically. 
     When the discharge flows from the signal terminal B 3  to the reference terminal B 2 , the voltage generated by the electrostatic discharge increases until it reaches the breakdown voltage of the drain-substrate junction of the second transistor TR 2 . 
     The substrate sb 2 , which corresponds here to the base of the parasitic bipolar transistor of the second MOS transistor TR 2 , is therefore polarized and the parasitic bipolar transistor (and therefore the second MOS transistor TR 2 ) is switched on. 
     The second transistor TR 2  has a GGNMOS type configuration, and the reference terminal B 2  to which its gate G 2  and its substrate sb 2  are connected acts as a ground. 
     The second transistor TR 2  is triggered here for a voltage at its terminals equal to 4.2 volts. 
     When the discharge flows from the reference terminal B 2  to the signal terminal B 3 , the pulse is transmitted by the common resistor R 1  onto the substrate sb 2  of the second transistor TR 2  and by the direct connection onto the gate G 2  of the MOS transistor TR 2 . In this scenario, the second transistor TR 2  is triggered in the usual way, as soon as its gate-source voltage exceeds its threshold voltage. 
     The polarization of the substrate sb 2  makes it possible to lower the threshold voltage of the second transistor TR 2 . Here, the transistor is triggered for a voltage of 0.6 volts. 
     In the case of a current pulse flowing from the power supply terminal B 1  to the reference terminal B 2 , the voltage generated by the electrostatic discharge increases until it reaches the breakdown voltage of the drain-substrate junction of the first transistor TR 1 . 
     The substrate sb 1 , which corresponds here to the base of the parasitic bipolar transistor of the first MOS transistor TR 1 , is therefore polarized and the parasitic bipolar transistor of the first MOS transistor TR 1  is switched on. 
     The substrate sb 2  of the second MOS transistor TR 2  is also polarized owing to the connection between the substrates sb 1  and sb 2 , and the parasitic bipolar transistor of the second MOS transistor TR 2  is also switched on. 
     The first MOS transistor TR 1  and the second transistor TR 2  are then triggered for a voltage between the terminals B 1  and B 2  with a value of 4.2 volts. 
     In the case of a discharge flowing between the reference terminal B 2  and the power supply terminal B 1 , the discharge is transmitted simultaneously onto the gate G 1  of the first transistor TR 1 , onto the gate G 2  of the second transistor TR 2 , onto the substrate sb 1  of the first transistor TR 1  and onto the substrate sb 2  of the second transistor TR 2 . 
     The two transistors TR 1  and TR 2  are therefore triggered in the usual way in order to facilitate the flow of the electrostatic discharge. 
     Thus, the component CMP is protected against electrostatic discharge that may occur between any two of its three terminals B 1 , B 2  and B 3 . 
     And, the connection of the substrate sb 1  and of the gate G 1  of the first transistor TR 1  to a reference terminal B 2 , i.e. to a different terminal from the signal terminal B 3 , makes it possible, when the device is in operation and, for example, the potential difference between the power supply terminal and the signal terminal is above the trigger threshold of the transistor TR 1 , to prevent the gate G 1  of the first transistor TR 1  from being polarized and the first transistor TR 1  being triggered. 
     According to an embodiment illustrated in  FIG. 3 , it would be possible for the gate G 1  of the first transistor TR 1  and the gate G 2  of the second transistor TR 2  to be coupled to the reference terminal via the common resistor R 1 . 
     Thus, each transistor has its gate and its substrate mutually connected. 
     This allows a hybrid operation of the MOS transistors TR 1  and TR 2 . 
     In particular, the common resistor R 1  and the drain-gate capacitor of the first MOS transistor TR 1  form a first trigger resistive-capacitive element making it possible to transmit the electrostatic pulse onto the gate of the first MOS transistor TR 1 . Thus, in the presence of an electrostatic discharge at the terminals of the first MOS transistor TR 1 , the electrostatic pulse will be transmitted both onto the gate G 1  via drain-gate or source-gate capacitors, and onto the substrate sb 1  of the first MOS transistor TR 1  by the breakdown of the drain-substrate or source-substrate junction. 
     Similarly, the common resistor R 1  and the drain-gate capacitor of the second MOS transistor TR 2  form a first trigger resistive-capacitive element making it possible to transmit the electrostatic pulse onto the gate of the second MOS transistor TR 2 . Thus, in the presence of an electrostatic discharge at the terminals of the second MOS transistor TR 2 , the electrostatic pulse will be transmitted both onto the gate G 2  via drain-gate or source-gate capacitors, and onto the substrate sb 2  of the second MOS transistor TR 2  by the breakdown of the drain-substrate or source-substrate junction. 
     In addition, the presence of the connection between the gate and the substrate of each transistor allows the gate to further polarize thereby amplifying the combined MOS and bipolar effects, since the nearer the gate voltage approaches the threshold voltage of the MOS transistor, the more the current gain increases. 
     This is particularly advantageous in the case of a pulse between the power supply terminal B 1  and the signal terminal B 3  where the trigger threshold is then lowered to 2.5 volts, and in the case of a pulse flowing from the signal terminal B 3  to the reference terminal B 2 , where the threshold is lowered to 1.5 volts with respect to the embodiment previously described in connection with  FIG. 2 . 
     In this embodiment also, the connection of the substrate sb 1  and of the gate G 1  of the first transistor TR 1 , via the common resistor R 1 , to the reference terminal B 2 , i.e. to a different terminal from the signal terminal B 3 , makes it possible, when the device is in operation and, for example, the potential difference between the power supply terminal B 1  and the signal terminal B 3  is above the trigger threshold of the transistor TR 1 , to prevent the gate G 1  of the first transistor TR 1  from being polarized and the first transistor TR 1  being triggered. 
     According to an embodiment illustrated by  FIGS. 4 to 6 , it is also possible to couple a third protection device DIS 3  between the power supply terminal B 1  and the reference terminal B 2 . 
     This device comprises a third transistor TR 3 , the gate G 3  of which may be directly ( FIG. 5 ) or indirectly connected to the reference terminal via the common resistor R 1  ( FIG. 6 ). 
     Thus, according to the embodiment illustrated in  FIG. 5 , in the presence of an electrostatic discharge flowing from the power supply terminal B 1  to the reference terminal B 2 , the voltage generated by the current pulse increases until it reaches the breakdown voltage of the drain-substrate junction of the third MOS transistor TR 3 . 
     The substrate sb 3 , which corresponds here to the base of the parasitic bipolar transistor of the third MOS transistor TR 3 , is therefore polarized and the parasitic bipolar transistor is switched on. 
     The third transistor TR 3  has a GGNMOS type configuration, and the reference terminal B 2 , to which the gate G 3  of the third MOS transistor TR 3  is connected, acts as a ground. 
     Here, the transistor is triggered for a voltage at its terminals equal to 4.2 volts. 
     And, the propagation path of the electrostatic discharge is more direct than if the discharge were flowing from the power supply terminal B 1  to the reference terminal B 2  via the first transistor TR 1  and the second MOS transistor TR 2 , which makes it possible to prevent the presence of surges due to the current pulse flowing through the two transistors the resistive value of which is not zero. 
     In the presence of an electrostatic discharge flowing from the reference terminal B 2  to the power supply terminal B 1 , the current pulse is transmitted by the common resistor R 1  onto the substrate sb 3  of the third MOS transistor TR 3 , and by the direct connection onto the gate G 3  of the MOS transistor TR 3 . 
     In this scenario, the third transistor TR 3  is triggered in the usual way, as soon as its gate-source voltage exceeds its threshold voltage. 
     The polarization of the substrate sb 3  of the third MOS transistor TR 3  makes it possible to lower the threshold voltage of the third transistor TR 3 . Here, the third MOS transistor TR 3  is triggered for a voltage of 0.6 volts. In this case also, the propagation path is more direct than if the pulse were flowing between the reference terminal B 2  and the power supply terminal B 1  via the first MOS transistor TR 1  and the second MOS transistor TR 2 . 
     According to the embodiment illustrated in  FIG. 6 , the trigger threshold of the third MOS transistor TR 3  is lowered to 1.5 volts in the case of a discharge flowing from the power supply terminal B 1  to the reference terminal B 2 . 
     In the case of an electrostatic discharge flowing from the reference terminal B 2  to the power supply terminal B 1 , the current passing through the transistor increases linearly until the voltage at its terminals reaches 1.5 volts, then exponentially beyond 2.5 volts, while the voltage at these terminals approaches 3.5 volts asymptotically. 
     The circuit CI is thus protected against electrostatic discharge flowing between the power supply terminal B 1  and the reference terminal B 2 . 
     Whatever the embodiment, the protection devices DIS 1 , DIS 2  and DIS 3  may be implemented in parallel with the existing protection devices, e.g. diodes or thyristors. 
     Thus, in  FIG. 4 , two thyristors  1  and  2  mounted head to tail are coupled between the power supply terminal B 1  and the reference terminal B 2 . 
     The implementation of the protection devices DIS 1 , DIS 2  and DIS 3  is therefore compatible with the existing production processes comprising the implementation of other protection means. In this case, the existing devices may either operate in parallel with the devices DIS 1 , DIS 2  and/or DIS 3 , or be inhibited by the devices DIS 1 , DIS 2 , and/or DIS 3 . 
     It would be possible, as illustrated in  FIGS. 7 to 9 , for the integrated circuit CI to include a plurality of signal terminals, a first signal terminal B 3  and a second signal terminal B 4  which would be indirectly connected via an electronic module CMP 2 . 
     In the presence of an electrostatic discharge between the first signal terminal B 3  and the second signal terminal B 4 , it is advisable that this current pulse should flow through a protection device and not through the electronic module CMP 2 . 
     Thus, the integrated circuit CI comprises a fourth protection device DIS 4  coupled between the first signal terminal B 3  and the second signal terminal B 4 . 
     As illustrated in  FIG. 8 , the fourth protection device may comprise a fourth MOS transistor TR 4 , the gate G 4  of which is directly coupled to the reference terminal B 2 , and the substrate sb 4  of which is coupled to the reference terminal via the common resistor R 1 . 
     It would, however, be possible for the substrate sb 4  of the intermediate transistor TR 4  to be coupled to the second signal terminal B 4  via the common resistor R 2  to the protection circuits associated with the second signal terminal B 4 . 
     The fourth transistor TR 4  here has a GGNMOS type configuration. 
     In the presence of an electrostatic discharge between the first signal terminal B 3  and the second signal terminal B 4 , the voltage generated by the current pulse increases until it reaches the breakdown voltage of the drain-substrate junction of the fourth MOS transistor TR 4 . 
     The substrate sb 4 , which corresponds here to the base of the parasitic bipolar transistor of the fourth MOS transistor TR 4 , is therefore polarized and the parasitic bipolar transistor of the fourth transistor TR 4  is switched on. 
     According to a variant illustrated in  FIG. 9 , it would be possible for the intermediate transistor TR 4  to be a transistor in a configuration allowing a hybrid operation, having its gate G 4  and its substrate sb 4  directly mutually connected and coupled to the reference terminal B 2  via the common resistor R 1 . 
     This configuration makes it possible to further improve the triggering of the fourth transistor TR 4 . 
       FIG. 10  illustrates a top view of an integrated circuit CI comprising the first transistor TR 1 , the second transistor TR 2 , the third transistor TR 3 , and the common resistor R 1  according to the embodiment previously described in connection with  FIG. 5 . 
     The three transistors are implemented on one and the same substrate sb, delimited by an isolating trench STI and are implemented so as to share at least one of their electrodes. 
     In this embodiment, each transistor is duplicated, i.e. it actually comprises two identical transistors mounted in parallel. This is equivalent to one larger-sized transistor, which makes it possible to support the passage of the current pulse resulting from an electrostatic discharge. 
     However, each transistor could include any number of identical transistors mounted in parallel, the greater the number of identical transistors the larger being the size of the equivalent transistor. 
     Thus, the drain D 1  of the first transistor TR 1  and the drain D 3  of the third transistor TR 3  are merged and connected to the power supply terminal B 1  via vias and metal tracks, the source S 3  of the third transistor TR 3  and the source S 2  of the second transistor TR 2  are merged and connected to the reference terminal B 2  via vias and metal tracks, the source S 1  of the first transistor TR 1  and the drain D 2  of the second transistor TR 2  are merged and connected to the signal terminal B 3 . 
     The gates G 1 , G 2  and G 3  are mutually connected and coupled to the second terminal B 2  via vias and metal tracks. However, they could be connected to the common resistor R 1  via vias and metal tracks. 
     The substrate of each transistor is coupled to the common resistor R 1  via vias and metal tracks. 
     Thus, a particularly compact ESD protection system is obtained. 
     The substrate may be a bulk substrate or a silicon on insulator (SOI) substrate.