Patent Publication Number: US-11640367-B1

Title: Apparatus and methods for high-speed drivers

Description:
FIELD OF THE DISCLOSURE 
     Embodiments of the invention relate to electronics, and more particularly, to driver circuits for high-speed communications. 
     BACKGROUND 
     Serializer/deserializer (SerDes) systems can be used in a variety of applications such as telecommunications, optical networks, and/or chip-to-chip communication. 
     A SerDes system includes a serializer that converts two or more parallel input data streams into a high-speed serial data stream, and a deserializer that converts the high-speed serial data stream into two or more parallel output data streams of reduced speed. Thus, data transmission can be provided over a reduced number of lines to lower pin count. 
     SUMMARY OF THE DISCLOSURE 
     Apparatus and methods for high-speed drivers are provided herein. In certain embodiments, a high-speed driver multiplexes two or more data streams. The high-speed driver is implemented with a mux-then-driver topology that provides multiplexing in a predriver circuit. Thus, the multiplexer is eliminated from the full rate output path to relax timing. Driver amplitude control schemes are also disclosed in which a controllable driver includes a group of differential series source transistor (SST) driver slices that are connected in parallel with one another to drive a pair of output terminals, and a group of attenuator slices that are connected in parallel with one another across the pair of output terminals. Additionally, the controllable driver includes a control circuit that activates an attenuator slice for each SST driver slice that is decommissioned to provide output amplitude control. 
     In one aspect, a driver circuit includes an output terminal configured to provide an output data stream, and a first driver subcircuit configured to receive a first input data stream of a lower bit rate than the output data stream, and to drive the output terminal based on the first input data stream in response to a transition of a first clock signal. The first driver subcircuit includes a first driver transistor connected between a high supply voltage and the output terminal with no other transistors therebetween, a second driver transistor connected between a low supply voltage and the output terminal with no other transistors therebetween, a first pull-up predriver circuit configured to control the first driver transistor, and a first pull-down predriver configured to control the second driver transistor. 
     In another aspect, a serializer/deserializer (SerDes) system includes a deserializer, and a serializer including a driver. The driver includes an output terminal configured to provide an output data stream to the deserializer, and a first driver subcircuit configured to receive a first input data stream of a lower bit rate than the output data stream, and to drive the output terminal based on the first input data stream in response to a transition of a first clock signal. The first driver subcircuit includes a first driver transistor connected between a high supply voltage and the output terminal with no other transistors therebetween, a second driver transistor connected between a low supply voltage and the output terminal with no other transistors therebetween, a first pull-up predriver circuit configured to control the first driver transistor, and a first pull-down predriver configured to control the second driver transistor. 
     In another aspect, a method of multiplexing data streams is provided. The method includes providing an output data stream on an output terminal, receiving a first input data stream of a lower bit rate than the output data stream as an input to a first driver subcircuit, and driving the output terminal based on the first input data stream in response to a transition of a first clock signal using the first driver subcircuit, including controlling a first driver transistor connected between a high supply voltage and the output terminal with no other transistors therebetween using a first pull-up predriver, and controlling a second driver transistor connected between a low supply voltage and the output terminal with no other transistors therebetween using a first pull-down predriver. 
     In another aspect, a driver circuit includes a pair of output terminals configured to provide a differential output signal, a plurality of differential series source transistor (SST) driver slices electrically connected in parallel with one another and configured to drive the pair of output terminals, a plurality of attenuator slices connected in parallel with one another across the pair of output terminals, and a control circuit configured to selectively deactivate one or more of the differential SST driver slices to control an amplitude of the differential output signal, and to enable a corresponding number of the attenuator slices to provide output impedance compensation. 
     In another aspect, a method of output swing control in a driver circuit is provided. The method includes providing a differential output signal on a pair of output terminals, driving the pair of output terminals using a plurality of differential series source transistor (SST) driver slices electrically connected in parallel with one another, deactivating one or more of the differential SST driver slices to control an amplitude of the differential output signal, and enabling a corresponding number of a plurality of attenuator slices to provide output impedance compensation, wherein the plurality of attenuator slices are connected in parallel with one another across the pair of output terminals. 
     In another aspect, a serializer/deserializer (SerDes) system includes a deserializer, and a serializer comprising a driver including a pair of output terminals configured to provide a differential output signal to the deserializer, a plurality of differential series source transistor (SST) driver slices electrically connected in parallel with one another and configured to drive the pair of output terminals, a plurality of attenuator slices connected in parallel with one another across the pair of output terminals, and a control circuit configured to selectively deactivate one or more of the differential SST driver slices to control an amplitude of the differential output signal, and to enable a corresponding number of the attenuator slices to provide output impedance compensation. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1 A  is a schematic diagram of one embodiment of a multiplexing driver. 
         FIG.  1 B  is one example of a timing diagram for the multiplexing driver of  FIG.  1 A . 
         FIG.  2 A  is a schematic diagram of another embodiment of a multiplexing driver. 
         FIG.  2 B  is a schematic diagram of another embodiment of a multiplexing driver. 
         FIG.  3 A  is a schematic diagram of one embodiment of a driver half circuit for a multiplexing driver. 
         FIG.  3 B  is one example of a timing diagram for the driver half circuit of  FIG.  3 A . 
         FIG.  4 A  is a schematic diagram of another embodiment of a multiplexing driver. 
         FIG.  4 B  is one example of a timing diagram for the multiplexing driver of  FIG.  4 A . 
         FIG.  5 A  is a schematic diagram of another embodiment of a multiplexing driver. 
         FIG.  5 B  is one example of a timing diagram for the multiplexing driver of  FIG.  5 A . 
         FIG.  6    is a schematic diagram of another embodiment of a multiplexing driver. 
         FIG.  7 A  is a schematic diagram of one embodiment of a pull-up predriver circuit for a multiplexing driver. 
         FIG.  7 B  is one example of a timing diagram for the pull-up predriver circuit of  FIG.  7 A . 
         FIG.  8 A  is a schematic diagram of one embodiment of a driver quarter circuit for a multiplexing driver. 
         FIG.  8 B  is one example of a timing diagram for the driver quarter circuit of  FIG.  8 A . 
         FIG.  9    is a schematic diagram of one embodiment of a driver with controllable swing and constant output impedance. 
         FIG.  10 A  is a schematic diagram of another embodiment of a driver with controllable swing and constant output impedance. 
         FIG.  10 B  is a circuit diagram of a portion of the driver of  FIG.  10 A . 
         FIG.  11    is a graph of one example of driver amplitude reduction versus attenuation setting for the driver of  FIGS.  10 A and  10 B . 
         FIG.  12 A  is a graph of one example comparison of driver output swing versus attenuation setting for two implementations of drivers. 
         FIG.  12 B  is a graph of one example comparison of driver current versus attenuation setting for two implementations of drivers. 
         FIG.  12 C  is a graph of one example comparison of driver output impedance versus attenuation setting for two implementations of drivers. 
         FIG.  13    is a schematic diagram of one embodiment of a SerDes system. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways. In this description, reference is made to the drawings where like reference numerals may indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings. 
     A SerDes system can include a serializer that generates a high-speed serial data stream based on data streams associated with different time offsets or delays. For instance, in a half rate SerDes system, a serializer can combine a first half rate data stream and a second half rate data stream into a full rate data stream having a bit period, with the second half rate data stream delayed by the bit period relative to the first half rate data stream. 
     In certain embodiments herein, high-speed drivers for multiplexing two or more data streams are provided. The high-speed driver is implemented with a mux-then-driver topology that provides multiplexing in a predriver circuit. Thus, the multiplexer is eliminated from the full rate output path to relax timing. For example, in an implementation with two data streams, a timing constraint is relaxed by a factor of two. 
     Moreover, implementing the multiplexer in the predriver reduces a size of the multiplexing transistors relative to an implementation in which an explicit T-gate multiplexer is included along the output signal path. By reducing the size of the multiplexing transistors, the multiplexer size is shrunk and the total capacitance is reduced to achieve reduced power and a tighter output eye diagram. 
       FIG.  1 A  is a schematic diagram of one embodiment of a multiplexing driver  10 .  FIG.  1 B  is one example of a timing diagram for the multiplexing driver  10  of  FIG.  1 A . 
     With reference to  FIG.  1 A , the multiplexing driver  10  operates to multiplex an odd half rate data stream D ODD  (also referred to herein as an odd data stream) and an even half rate data stream D EVEN  (also referred to herein as an even data stream) to generate a full rate data stream D OUT . Thus, the multiplexing driver  10  provides two-way interleaving. 
     The multiplexing driver  10  receives the odd data stream D ODD  and the even data stream D EVEN , as well as a first clock signal CK 0  and a second clock signal CK 180  used for controlling timing of the data streams. In the example of  FIG.  1 B , the value of the odd data stream D ODD  becomes ready at the input of the multiplexing driver  10  before a rising edge of the first clock signal CK 0 , and the value is transferred to the full rate data stream D OUT  in response to a rising edge of the second clock signal CK 180 . Additionally, the value of the even data stream D EVEN  becomes ready at the input of the multiplexing driver  10  before a rising edge of the second clock signal CK 180 , and the value is transferred to the full rate data stream D OUT  in response to a rising edge of the first clock signal CK 0 . 
     In the example of  FIG.  1 B , annotations for an example full data rate of 32 gigabits per second (Gbps) are depicted. In this example, the half rate data streams operate at 16 Gbps and a corresponding bit interval of 62.5 picoseconds (ps), while the full rate data stream has a 31.25 ps bit interval. The first clock signal CK 0  and the second clock signal CK 180  operate at 16 gigahertz (GHz) with a bit period offset from one another. 
     When operating at a full data rate of 32 Gbps, the 31.25 ps bit period approaches the process limit for certain processes, such as 16 nanometer (nm) processes associated with an inverter fan-out two delay of about 5 ps. 
     To implement the multiplexing driver  10 , the odd data stream D ODD  could be provided to a first inverter that drives a first T-gate multiplexer, and the even data stream D EVEN  could be provided to a second inverter that drives a second T-gate multiplexer. Additionally, the first T-gate multiplexer could pass the odd data stream D ODD  to the output based on timing of the second clock signal CLK 180  (for instance, in response to a rising edge), while the second T-gate multiplexer could pass the even data stream D EVEN  to the output based on timing of the first clock signal CLK 0  (for instance, in response to a rising edge). 
     However, such an implementation has high output resistance due to a T-gate multiplexer being in series with each driver inverter. Furthermore, a large T-gate multiplexer size (to keep the output resistance low due to the series combination of transistors) results in high parasitic capacitance. Moreover, including a series output resistor for impedance matching (for instance, 50 Ohm) can further raise output resistance and slow timing. Furthermore, asymmetries in the logic gates used to drive the T-gate multiplexers leads to imbalances in rise/fall times and a data eye that is bimodal. 
     In certain embodiments herein, the multiplexing driver  10  is implemented using a mux-then-driver topology that provides multiplexing in a predriver circuit. Thus, the multiplexer is eliminated from the full rate output path, thereby relaxing timing constraints to allow handling of data streams of higher bit rates. 
       FIG.  2 A  is a schematic diagram of another embodiment of a multiplexing driver  40 . The multiplexing driver  40  includes a first driver half circuit  11 , a second driver half circuit  12 , an output resistor  13 , and an output pin or pad  14 . 
     As shown in  FIG.  2 A , the first driver half circuit  11  receives the even data stream D EVEN , the first clock signal CK 0 , and the second clock signal CK 180 , while the second driver half circuit  12  receives the odd data stream D ODD , the first clock signal CK 0 , and the second clock signal CK 180 . The first driver half circuit  11  operates to provide the even data stream D EVEN  to the output pad  14  based on timing of the first clock signal CK 0  (for instance, in response to a rising edge), while the second driver half circuit  12  operates to provide the odd data stream D ODD  to the output pad  14  based on timing of the second clock signal CK 180  (for instance, in response to a rising edge). 
     Thus, the first driver half circuit  11  and the second driver half circuit  12  operate in an alternating or ping-pong sequence. 
     The first driver half circuit  11  and the second driver half circuit  12  each include an output connected to the output pad  14  by way of the output resistor  13 . Including the output resistor  13  can aid in achieving a desired output impedance match, for instance, 50 Ohms or other desired output impedance value. The output resistor  13  can be implemented in a wide variety of ways including, but not limited to, using polysilicon or other resistive material having a geometry selected to achieve a target resistance value. In certain implementations, the output resistor  13  is trimmable and/or otherwise controllable to achieve an output resistance that provides compensation for variation. 
     In the illustrated embodiment, the first driver half circuit  11  includes a first driver p-type field effect transistor (PFET)  21 , a first driver n-type field effect transistor (NFET)  22 , a first pull-up predriver circuit  23 , and a first pull-down predriver circuit  24 . Additionally, the second driver half circuit  12  includes a second driver PFET  31 , a second driver NFET  32 , a second pull-up predriver circuit  33 , and a second pull-down predriver circuit  34 . The predriver circuits are implemented with multiplexing in accordance with the teachings herein. 
     Accordingly, the multiplexing driver  40  is advantageously implemented with multiplexing that is implemented in predriver stages, thereby allowing a connection to the output pad  14  that goes through a low number of transistors. 
     For example, as shown in  FIG.  2 A , the first driver half circuit  11  can drive the output pad  14  logically high using the first driver PFET  21 , which is connected in series with the output resistor  13  between a power supply voltage V DD  (also referred to herein as a high supply voltage) and the output pad  14  with no other transistors therebetween. Likewise, the first driver half circuit  11  can drive the output pad  14  logically low using the first driver NFET  22 , which is connected in series with the output resistor  13  between a ground voltage (also referred to herein as a low supply voltage or V SS ) and the output pad  14  with no other transistors therebetween. 
     Accordingly, timing constraints are relaxed by eliminating a multiplexer (for instance, a T-gate multiplexer in cascade with a driver inverter) from the output resistance path. 
     The NFETs and PFETs can be implemented in a wide variety of ways. In one example, the multiplexing driver  40  is fabricated in a complementary metal oxide semiconductor (CMOS) process, and the NFETs correspond to n-type metal oxide semiconductor (NMOS) transistors while the PFETs correspond to p-type metal oxide semiconductor (PMOS) transistors. 
       FIG.  2 B  is a schematic diagram of another embodiment of a multiplexing driver  50 . The multiplexing driver  50  of  FIG.  2 B  is similar to the multiplexing driver  40  of  FIG.  2 A , except that the multiplexing driver  50  is implemented in a differential configuration. 
     For example, the multiplexing driver  50  includes a first non-inverted (+) driver half circuit  11   a , a second non-inverted driver half circuit  12   a , a first output resistor  13   a , and a first output pad  14   a . The first non-inverted driver half circuit  11   a  operates to provide the non-inverted even data stream D EVEN+  to the first output pad  14   a  (which provides D OUT+ ) based on timing of the first non-inverted clock signal CK 0+ , while the second non-inverted driver half circuit  12   a  operates to provide the non-inverted odd data stream D ODD+  to the first output pad  14   a  based on timing of the second non-inverted clock signal CK 180+ . The first non-inverted driver half circuit  11   a  includes a first driver PFET  21   a , a first driver NFET  22   a , a first pull-up predriver circuit  23   a , and a first pull-down predriver circuit  24   a , while the second non-inverted driver half circuit  12   a  includes a second driver PFET  31   a , a second driver NFET  32   a , a second pull-up predriver circuit  33   a , and a second pull-down predriver circuit  34   a.    
     With continuing reference to  FIG.  2 B , the first inverted driver half circuit  11   b  operates to provide the inverted even data stream D EVEN−  to the second output pad  14   b  (which provides D OUT− ) based on timing of the first inverted clock signal CK 0− , while the second inverted driver half circuit  12   b  operates to provide the inverted odd data stream D ODD−  to the second output pad  14   b  based on timing of the second inverted clock signal CK 180− . The first inverted driver half circuit  11   b  includes a first driver PFET  21   b , a first driver NFET  22   b , a first pull-up predriver circuit  23   b , and a first pull-down predriver circuit  24   b , while the second inverted driver half circuit  12   b  includes a second driver PFET  31   b , a second driver NFET  32   b , a second pull-up predriver circuit  33   b , and a second pull-down predriver circuit  34   b.    
     Any of the driver circuits herein can be implemented differentially. By implementing a multiplexing predriver differentially, enhanced immunity against common-mode noise can be achieved. 
       FIG.  3 A  is a schematic diagram of one embodiment of a driver half circuit  70  for a multiplexing driver. For example, the driver half circuit  70  can connect to an output resistor  13  and an output pad  14  of the multiplexing driver as shown.  FIG.  3 B  is one example of a timing diagram for the driver half circuit  70  of  FIG.  3 A  when operating at 32 Gbps. 
     As shown in  FIG.  3 A , the driver half circuit  70  receives the even data stream D EVEN , the first clock signal CK 0 , and the second clock signal CK 180 . The driver half circuit  70  includes a driver PFET  21  (also referred to as driver PFET M 3 ), a driver NFET  22  (also referred to as driver NFET M 3 ′), a pull-up predriver circuit  63 , and a pull-down predriver circuit  64 . 
     In the illustrated embodiment, the pull-up predriver circuit  63  includes a pull-down data NFET M 1 , a pull-up data PFET M 2 , a multiplexing NFET M 4 , and a pre-charge PFET M 5 . As shown in  FIG.  3 A , the pull-up predriver circuit  63  controls activation of the driver PFET M 3  at a node Y that is pre-charged to V DD  by the pre-charge PFET M 5  when the first clock signal CK 0  is low. Additionally, the pull-up data PFET M 2  and the pull-down data NFET M 1  control the node X to one of V DD  or ground (V SS ) based on a state of the even data stream D EVEN . In response to the first clock signal CK 0  going high, the multiplexing NFET M 4  passes the value of node X to node Y to thereby control the driver PFET M 3 . 
     With continuing reference to  FIG.  3 A , the pull-down predriver circuit  64  includes a pull-up data PFET M 1 ′, a pull-down data NFET M 2 ′, a multiplexing PFET M 4 ′, and a pre-charge NFET M 5 ′. As shown in  FIG.  3 A , the pull-down predriver circuit  64  controls activation of the driver NFET M 3 ′ at a node Y′ that is pre-charged to ground by the pre-charge NFET M 5 ′ when the second clock signal CK 180  is high. Additionally, the pull-up data PFET M 1 ′ and the pull-down data NFET M 2 ′ control the node X′ to one of V DD  or ground based on a state of the even data stream D EVEN  In response to the second clock signal CK 180  going low, the multiplexing PFET M 4 ′ passes the value of node X′ to node Y′ to thereby control the driver MFET M 3 ′. 
     Thus, the pull-up predriver circuit  63  and the pull-down predriver circuit  64  operate in a first phase associated with pre-charge followed by a second phase in which the output is pulled up or down based on a state of the even data stream D EVEN . 
     By implementing the driver half circuit  70  in this manner, a number of performance enhancements are achieved including, but not limited to, a relaxed setup time (t setup ). 
     Table 1 below provides a summary of operation of the pull-up predriver circuit  63  over the first phase and the second phase. 
     
       
         
           
               
               
               
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 Phase 
                 CK 0   
                 CK 180   
                 D EVEN   
                 node Y 
                 M4 
                 M5 
               
               
                   
               
             
            
               
                 1 
                 Low 
                 high 
                 settling 
                 pre-charge 
                 off 
                 on 
               
               
                   
                   
                   
                   
                 to V DD   
                   
                   
               
               
                 2 
                 High 
                 low 
                 transparent 
                 pull-down 
                 on 
                 off 
               
               
                   
                   
                   
                   
                 when 
                   
                   
               
               
                   
                   
                   
                   
                 D EVEN  = l 
               
               
                   
               
            
           
         
       
     
       FIG.  4 A  is a schematic diagram of another embodiment of a multiplexing driver  100 .  FIG.  4 B  is one example of a timing diagram for the multiplexing driver  100  of  FIG.  4 A  when operating at 32 Gbps. The multiplexing driver  100  includes a first driver half circuit  70 , a second driver half circuit  80 , an output resistor  13 , and an output pad  14 . 
     The multiplexing driver  100  includes two half driver circuits implemented in accordance with the embodiment of  FIG.  3 A . For example, the multiplexing driver  100  includes the first half driver circuit  70 , as described earlier with respect to  FIG.  3 A . The multiplexing driver  100  further includes the second half driver circuit  80  used to control the output data stream Dom′ based on the odd data stream D ODD  and timing of the first clock signal CK 0  and the second clock signal CK 180 . 
     As shown in  FIG.  4 A , the second half driver circuit  80  includes a pull-down data NFET M 1 ″ (for pulling down node X″ when D ODD  is high), a pull-up data PFET M 2 ″, a driver PFET M 3 ″, a multiplexing NFET M 4 ″ (controlled by CK 180 ), a pre-charge PFET M 5 ″ (for pre-charging node Y″ to V DD  when CK 180  is low), a pull-up data PFET M 1 ′″ (for pulling up node X′″ when D ODD  is low), a pull-down data NFET M 2 ′″, a multiplexing PFET M 4 ′″ (controlled by CK 0 ), and a pre-charge NFET M 5 ′″ (for pre-charging node Y′″ to ground when CK 0  is high). 
       FIG.  5 A  is a schematic diagram of another embodiment of a multiplexing driver  210 .  FIG.  5 B  is one example of a timing diagram for the multiplexing driver  210  of  FIG.  5 A . 
     With reference to  FIG.  5 A , the multiplexing driver  210  generates a full rate data stream Dom′ by multiplexing a first quarter rate data stream Do, a second quarter rate data stream D 90 , a third quarter rate data stream D 180 , and a fourth quarter rate data stream D 270 . Thus, the multiplexing driver  210  provides four-way interleaving. 
     In addition to receiving the quarter rate data streams, the multiplexing driver  210  receives a first clock signal CK 0 , a second clock signal CK 90 , a third clock signal CK 180 , and a fourth clock signal CK 270  that are offset in phase from one another (by a bit interval of D OUT ). 
     In the example of  FIG.  5 B , annotations for operation at a full data rate of 56 Gbps are depicted. In this example, the quarter rate data streams operate at 14 Gbps and a corresponding bit interval of 71.8 ps, while the full rate data stream has a 17.8 ps bit interval. Furthermore, the clock signals operate at a 14 GHz with a bit period offset from one another. 
     By providing 4-way interleaving, higher output data rate can be achieved relative to 2-way interleaving or no interleaving. 
     In certain embodiments herein, the multiplexing driver  210  is implemented using a mux-then-driver topology that provides multiplexing in a predriver circuit. Thus, the multiplexer is eliminated from the full rate output path to relax timing constraints. 
       FIG.  6    is a schematic diagram of another embodiment of a multiplexing driver  260 . The multiplexing driver  260  includes a first driver quarter circuit  211 , a second driver quarter circuit  212 , a third driver quarter circuit  213 , a fourth driver quarter circuit  214 , an output resistor  215 , and an output pin or pad  216 . 
     As shown in  FIG.  6   , the first driver quarter circuit  211  receives the first data stream Do, the second driver quarter circuit  212  receives the second data stream D 90 , the third driver quarter circuit  213  receives the third data stream D 180 , and the fourth driver quarter circuit  214  receives the fourth data stream D 270 . The driver quarter circuits  211 - 214  are interleaved to drive the output pad  216  with their respective data streams based on timing of the first clock signal CK 0 , the second clock signal CK 90 , the third clock signal CK 180 , and the fourth clock signal CK 270 . 
     The driver quarter circuits  211 - 214  each include an output connected to the output pad  216  by way of the output resistor  215 . Including the output resistor  215  can aid in achieving a desired output impedance match, for instance, 50 Ohms or other desired output impedance value. 
     In the illustrated embodiment, the first driver quarter circuit  211  includes a first driver PFET  221 , a first driver NFET  222 , a first pull-up predriver circuit  223  for controlling the first driver PFET  221 , and a first pull-down predriver circuit  224  for controlling the first driver NFET  222 . Additionally, the second driver quarter circuit  212  includes a second driver PFET  231 , a second driver NFET  232 , a second pull-up predriver circuit  233  for controlling the second driver PFET  231 , and a second pull-down predriver circuit  234  for controlling the second driver NFET  232 . Furthermore, the third driver quarter circuit  213  includes a third driver PFET  241 , a third driver NFET  242 , a third pull-up predriver circuit  243  for controlling the third driver PFET  241 , and a third pull-down predriver circuit  244  for controlling the third driver NFET  242 . Additionally, the fourth driver quarter circuit  214  includes a fourth driver PFET  251 , a fourth driver NFET  252 , a fourth pull-up predriver circuit  253  for controlling the fourth driver PFET  251 , and a fourth pull-down predriver circuit  254  for controlling the fourth driver NFET  252 . 
     The multiplexing driver  260  is advantageously implemented with multiplexing in predriver stages, thereby allowing a connection to the output pad  216  that goes through a low number of transistors. For example, as shown in  FIG.  6   , each of the driver quarter circuits  211 - 214  can drive the output pad  216  to V DD  or ground (V SS ) through a single transistor. Accordingly, timing constraints are relaxed by eliminating a multiplexer (for instance, a T-gate multiplexer in cascade with a driver inverter) from the output resistance path. 
       FIG.  7 A  is a schematic diagram of one embodiment of a pull-up predriver circuit  280  for a multiplexing driver.  FIG.  7 B  is one example of a timing diagram for the pull-up predriver circuit  280  of  FIG.  7 A . 
     The pull-up predriver circuit  280  of  FIG.  7 A  illustrates one embodiment of the pull-up predriver circuit  233  of  FIG.  6   , and thus the pull-up predriver circuit  280  can be included as part of a driver quarter circuit. As shown in  FIG.  7 A , connections of the pull-up predriver circuit  280  to the second driver PFET  231  (also referred to as driver PFET M 3 ), the output resistor  215 , and the output pad  216  are depicted. 
     In the illustrated embodiment, the pull-up predriver circuit  280  includes a first multiplexing NFET M 1 , a data NFET M 2 , a second multiplexing NFET M 4 , a first pre-charge PFET M 5 , and a second pre-charge PFET M 6 . 
     As shown in  FIG.  7 A , the pull-up predriver circuit  280  controls activation of the driver PFET M 3  at a node Y that is pre-charged to V DD  by the first pre-charge PFET M 5  when the first clock signal CK 0  is low and by the second pre-charge PFET M 6  when the second clock signal CK 90  is low. The node Z is pulled low in response to the second clock signal CK 90  going high, and the data NFET M 2  pulls the node X to ground when the data stream D 90  is also high. The value of node X is passed to node Y through the second multiplexing NFET M 4 , which is controlled by the first clock signal CK 0 . 
     Thus, the pull-up predriver circuit  280  operates in multiple circuit phases. Table 2 below provides a summary of operation of the pull-up predriver circuit  280  over the phases. 
     
       
         
           
               
               
               
               
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                 Phase 
                 CK 0   
                 CK 90   
                 D 90   
                 node Y 
                 M4 
                 M1 
               
               
                   
               
             
            
               
                 1 
                 Low 
                 low 
                 settling 
                 pre-charge 
                 off 
                 off 
               
               
                   
                   
                   
                 after 
                 to V DD   
                   
                   
               
               
                   
                   
                   
                 transition 
                 (M5 + M6) 
                   
                   
               
               
                 2 
                 High 
                 low 
                 finishing 
                 pre-charge 
                 on 
                 off 
               
               
                   
                   
                   
                 settling 
                 to V DD   
                   
                   
               
               
                   
                   
                   
                   
                 (M6) 
                   
                   
               
               
                 3 
                 high 
                 high 
                 no change 
                 pull-down 
                 on 
                 on 
               
               
                   
                   
                   
                   
                 if D 90  = 1 
                   
                   
               
               
                 4 
                 Low 
                 high 
                 no change 
                 pre-charge 
                 off 
                 on 
               
               
                   
                   
                   
                   
                 to V DD   
                   
                   
               
               
                   
                   
                   
                   
                 (M5) 
               
               
                   
               
            
           
         
       
     
     The multi-phase circuit sequence is also graphically depicted in  FIG.  7 B . 
     The pull-up predriver circuit  280  of  FIG.  7 A  advantageously includes the fourth phase to turn-off the data NFET M 4  and pre-charge node Y quickly (for example, as quickly as CK 0  drops below the threshold voltage of the first pre-charge PFET M 5 ) rather than waiting for the whole transistor sequence M 1 , M 2 , and M 4  to turn off (in order). 
     Moreover, this pre-charge scheme provides fast performance time and/or low parasitic capacitance while avoiding a need for a separate pre-charge transistor for node X (for instance an additional transistor directly connected between V DD  and node X). 
       FIG.  8 A  is a schematic diagram of one embodiment of a driver quarter circuit  300  for a multiplexing driver.  FIG.  8 B  is one example of a timing diagram for the driver quarter circuit  300  of  FIG.  8 A  for operation at 56 Gbps. 
     The driver quarter circuit  300  is depicted with connections to the output resistor  215  and the output pad  216 . The driver quarter circuit  300  includes a driver PFET  231  (also referred to as driver PFET M 3 ), a driver NFET  232  (also referred to as driver NFET M 3 ′), a pull-up predriver circuit  280 , and a pull-down predriver circuit  290 . 
     The driver quarter circuit  300  is implemented with predriver circuits implemented in accordance with the embodiment of  FIG.  7 A . For example, the driver quarter circuit  300  includes the pull-up predriver circuit  280  as discussed above with reference to  FIG.  7 A , as well as the pull-down predriver circuit  290  which corresponds to a complementary version of the pull-up predriver circuit  280  in which transistor polarities and power supply connections are reversed and the clock signals are delayed by 180 degrees to provide inversion. 
     As shown in  FIG.  8 A , the pull-down predriver circuit  290  includes a first multiplexing PFET M 1 ′ (controlled by CK 270  and connected between V DD  and node Z′), a data PFET M 2 ′ (controlled by D 90  and connected between node Z′ and node X′), a second multiplexing PFET M 4 ′ (controlled by CK 180  and connected between node X′ and node Y′), a first pre-charge NFET M 5 ′ (controlled by CK 180  and connected between node Y′ and ground), and a second pre-charge NFET M 6 ′ (controlled by CK 270  and connected between node Y′ and ground). 
     The multi-phase circuit sequence of the driver quarter circuit  300  of  FIG.  8 A  is graphically depicted in  FIG.  8 B . 
     Drivers with Controllable Output Swing and Constant Output Impedance 
     In certain applications, such as SerDes, it is desirable for an output driver to have constant output impedance while at the same time having controllable output swing to achieve desired signal amplitude. For example, implementing a driver with variable output amplitude control allows for enhanced flexibility for achieving desired signal level. However, it is desirable for the change in output amplitude or swing to not degrade performance by changing the output impedance from a desired level. 
     Although current mode logic (CML) drivers can realize controllable swing and constant output impedance, CML drivers suffer from a number of undesirable characteristics, such as high power consumption. Series source transistor (SST) drivers offer improved power performance, but suffer from varying output impedance when the driver transistor size is changed to adjust output amplitude. 
     SST drivers with controllable output swing and constant output impedance are provided. In certain embodiments herein, a controllable driver includes a group of differential SST driver slices that are connected in parallel with one another to drive a pair of output terminals providing a differential output signal, and a group of attenuator slices that are connected in parallel with one another across the pair of output terminals. Each attenuator slice can be implemented to have an on-state resistance about equal to an on-state resistance of one of the differential SST driver slices. Additionally, the controllable driver includes a control circuit that activates an attenuator slice for each SST driver slice that is decommissioned to provide amplitude control. Thus, for every differential SST driver slice that is disabled for amplitude control, an attenuator slice is enabled. 
     Thus, the combined total number of active SST driver slices and active attenuator slices remains constant, and the output impedance remains at a desired value (for instance, 50 Ohms). 
     In certain implementations, the control circuit can be implemented to also disable any clock and data path circuits used to drive a differential SST driver slice that is disabled for amplitude control. By implementing the controllable driver in this manner, any additional current draw by the attenuator array is outweighed by a current reduction arising from disabling the clock and data path circuits leading to the decommissioned slices. 
       FIG.  9    is a schematic diagram of one embodiment of a driver  400  with controllable swing and constant output impedance. The driver  400  includes differential SST slices  401   a ,  401   b , . . .  401   i  operating in parallel with one another to drive a pair of output terminals V OUT+ /V OUT− . The driver  400  further includes attenuator slices  402   a ,  402   b , . . .  402   j  in parallel with one another across the pair of differential output terminals V OUT+ , V OUT− . The driver  400  further includes a control circuit  403  and data/clock path slices  404   a ,  404   b , . . .  404   i.    
     In the illustrated embodiment, the control circuit  403  generates a first group of enable signals EN 1   a , EN 1   b , . . . EN 1   i  for enabling the SST slices  401   a ,  401   b , . . .  401   i , respectively. Additionally, the control circuit  403  generates a second group of enable signals EN 2   a , EN 2   b , . . . EN 2   j  for enabling the attenuator slices  402   a ,  402   b , . . .  402   j , respectively. The number of SST slices i and the number of attenuator slices j can be the same or different. The control circuit  403  maintains a total number of active SST driver slices and active attenuator slices constant. Thus, for every differential SST driver slice that is disabled for amplitude control, an attenuator slice is enabled. 
     In certain implementations, each attenuator slice is implemented to have an on-state resistance about equal to an on-state resistance of one of the differential SST driver slices. For example, when operating at room temperature and nominal operating voltage, the on-state resistances can be within 20% of one another, or more particularly within 5%, for example, within 1%. Thus, the resistances of the attenuator slices and differential SST driver slices need not match exactly. 
     Although the attenuator slices and SST resistances can be implemented to be about equal in resistance, other implementations are possible. For example, making the attenuator resistance greater can provide increased amplitude control granularity. 
     In certain implementations, resistance tuning of the SST slices and/or attenuator slices can be provided to provide compensation for variation, for example, process, supply voltage, and/or temperature (PVT) variation. 
     Additionally or alternatively, the layouts and/or design topologies of the slices can be implemented such that the resistances of the SST slices and attenuator slices track each other to account for variation arising from manufacturing and/or operating conditions. 
     When the on-state resistances are about equal and the combined total number of active SST driver slices and active attenuator slices remains constant, the output impedance across attenuation settings remains constant at a desired value (for instance, 50 Ohms). 
     In certain implementations, the control circuit  403  can be implemented to also disable any clock and data path circuits used to drive a differential SST driver slice that is disabled for amplitude control. For example, in the illustrated embodiment, the data/clock path slices  404   a ,  404   b , . . .  404   i  also receive the enable signals EN 1   a , EN 1   b , . . . EN 1   i.    
       FIG.  10 A  is a schematic diagram of another embodiment of a driver  500  with controllable swing and constant output impedance. 
     The driver  500  is depicted as including [0 . . . n−m−1] number of active SST slices  501  and corresponding data signals D and inverted data signals DB. Each of the SST slices  501  includes a first driver PFET  511 , a first driver NFET  512 , a second driver PFET  513 , a second driver NFET  514 , a first output resistor  515 , and a second output resistor  516 . The SST slices  501  have an output resistance Rsst. The SST slices  501  drive a pair of output terminals (to generate a differential output voltage +Vout/−Vout) between which a first 50 Ohm load resistor  505  and a second 50 Ohm load resistor  506  are connected. 
     With continuing reference to  FIG.  10 A , the driver  500  is depicted with [0 . . . m−1] number of active attenuator slices  502  connected differentially across the pair of output terminals. Each of the attenuator slices  502  includes a first resistor  521 , a second resistor  522 , and a T-gate multiplexer includes an NFET  523  and a PFET  524 . The attenuator slices have an output resistance Rsst′. 
     In this embodiment, n represents the number of SST slices desired for nominal amplitude at 50 Ohm, and m is the number of decommissioned SST slices/activated attenuator slices. 
       FIG.  10 B  is a circuit diagram of a portion of the driver  500  of  FIG.  10 A . The circuit diagram depicts a pair of resistors of resistance R 1  representing a transistor resistance of the SST slices. Additionally, the circuit diagram depicts a capacitor of capacitance Cx (which can included for any of the differential drivers herein for common mode termination) and a pair of resistors of resistance R 2  representing the resistance of the attenuator slices. The diagram is annotated for a supply voltage (V DD ) of 1V and a ground voltage of 0V. In this circuit, the differential output voltage (V OUT+ −V OUT− ) of the driver is equal to V DD *(R 2 ∥50 Ohm)/((R 2 ∥50 Ohm)+R 1 ). 
       FIG.  11    is a graph of one example of driver amplitude reduction versus attenuation setting for the driver  500  of  FIGS.  10 A and  10 B . The x-axis represents the number of decommissioned SST slices and corresponding amplitude reduction. The output impedance is maintained at 50 Ohm across amplitude control settings. 
       FIG.  12 A  is a graph of one example comparison of driver output swing versus attenuation setting for two implementations of drivers. The graph includes a plot  601  for one implementation of the driver  500  of  FIGS.  10 A and  10 B , and a second plot  602  for an array of selectable SST slices without any attenuator slices. 
       FIG.  12 B  is a graph of one example comparison of driver current versus attenuation setting for two implementations of drivers. The graph includes a plot  603  for one implementation of the driver  500  of  FIGS.  10 A and  10 B , and a second plot  604  for an array of selectable SST slices without any attenuator slices. 
       FIG.  12 C  is a graph of one example comparison of driver output impedance versus attenuation setting for two implementations of drivers. The graph includes a plot  605  for one implementation of the driver  500  of  FIGS.  10 A and  10 B , and a second plot  606  for an array of selectable SST slices without any attenuator slices. 
     With reference to  FIGS.  12 A to  12 C , the total of SST slices and attenuator slices is selected to be 24 for the implementation of the driver  500 . Additionally, a 100 Ohm differential resistance is simulated. The results show a linear tradeoff between 1V AVDD current reduction and smaller swing. 
     Moreover, with respect to  FIG.  12 A , the attenuation plot  601  follows  FIG.  11    as expected while the attenuation plot  602  follows a more linear trend due to a different attenuation method. Additionally, the current plot  604  of  FIG.  12 B  sees current increase as front-end stages (slices  404   a ,  404   b , . . .  404   i  and slices  401   a ,  401   b , . . .  401   i  in  FIG.  9   ) are still active while the attenuation plot  602  of  FIG.  12 A  also induces additional cross-bar current within the output driver stage. Furthermore, with respect to  FIG.  12 C , the lower value of output impedance plot  606  is due to the 24 slices used in the simulation instead of 23 which would have increased the value by 4.3% (equal to 1/23) to 97.25 Ohm to match the output impedance plot  605  closer. 
       FIG.  13    is a schematic diagram of one embodiment of a SerDes system  700 . The SerDes system  700  includes a first semiconductor die  701  and a second semiconductor die  702  connected over a high-speed link  703 , which can be, for example, a pair of differential conductors. 
     The first semiconductor die  701  includes a serializer  704  that receives two or more incoming data streams of reduced bit rate relative to a high-speed data stream provided on the high-speed link  703 . The second semiconductor die  702  includes a deserializer  705  that generates two or more outgoing data streams of reduced bit rate based on the high-speed data stream received from the serializer  704 . 
     The serializer  704  includes a driver  706  implemented in accordance with one or more features of the present disclosure. For example, the driver  706  can include predriver circuitry  707  that provides multiplexing of the incoming data streams and/or can include SST swing control  708  using attenuator slices for output impedance control in accordance with the teachings herein. 
     CONCLUSION 
     The foregoing description may refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected). 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and/or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims. 
     Although the claims presented here are in single dependency format for filing at the USPTO, it is to be understood that any claim may depend on any preceding claim of the same type except when that is clearly not technically feasible.