Patent Publication Number: US-2020302068-A1

Title: Method for executing, with a microprocessor, a binary code containing a calling function and a called function

Description:
The invention relates to a method for executing, with a microprocessor, a binary code containing a calling function and a called function, which is called by this calling function. The invention also relates to:
         a binary code, a data-storage medium and a microprocessor for implementing this executing method, and   a compiler for generating this binary code.       

     To obtain information on a binary code or to cause the binary code to function in an unexpected way, many attacks are possible. For example buffer overflow attacks may be carried out. These attacks consist in replacing, in a call stack, the return address of the called function by another address set by the attacker. A buffer overflow may therefore be used to execute a code developed and designed by the attacker. 
     Using such attacks, an attacker can determine a secret key of a cryptographic system, bypass security mechanisms such as the verification of a PIN code during an authentication or simply prevent the execution of a function essential to the security of a critical system. 
     These attacks therefore cause an execution fault that, during the execution of the binary code, alters the control flow of the machine code. 
     The control flow corresponds to the order of execution followed during the execution of the machine code. Control flow is conventionally represented in the form of a graph known as the control flow graph. 
     The binary code of a function may be written to allow execution faults to be detected and signalled. When the binary code of a function is thus written, this binary code is qualified “binary code of a secure function”. Specifically, contrary to the binary code of an insecure function, this binary code is able to allow execution faults typically encountered in case of attacks to be signalled. 
     Various solutions have already been proposed for combating buffer overflow attacks. For example, mention may be made of the following solutions:
         the software solution known as the “canary technique”,   hardware solutions such as a hardware module that verifies that each datum stored in the call stack is correctly confined to the address range that is allocated thereto,   the storage of the return addresses not only in the call stack but also in a hidden stack not accessible to users.       

     These known solutions function correctly. However, they consume a substantial proportion of the memory space allocated to the call stack or require the use of hardware modules that are very specific to this task. 
     The objective here is to propose another method for executing a binary code that makes it more difficult to carry out buffer overflow attacks. 
     Therefore, one subject of the invention is a method for executing, with a microprocessor, a binary code containing a calling function and a called function, which is called by this calling function. 
     Another subject of the invention is a binary code, executable by a microprocessor, for implementing the executing method. 
     Another subject of the invention is a data-storage medium that is readable by a microprocessor, this data-storage medium containing the binary code. 
     Another subject of the invention is a microprocessor for implementing the executing method. 
     Lastly, another subject of the invention is a compiler able to automatically convert a source code of a function into a binary code of this function, wherein the compiler is able to automatically convert the source code into a binary code as claimed. 
    
    
     
       The invention will be better understood on reading the following description, which is given merely by way of nonlimiting example and with reference to the drawings, in which: 
         FIG. 1  is a schematic illustration of the architecture of an electronic device able to execute a binary code of a secure function; 
         FIG. 2  is a schematic illustration of the structure of an instruction line coding an instruction of the binary code executed by the device of  FIG. 1 ; 
         FIGS. 3 to 5  are schematic illustrations of various segments of the binary code of the secure function capable of being executed by the device of  FIG. 1 ; 
         FIG. 6  is a schematic illustration of various registers of the electronic device, said registers being used during the execution of the secure function; 
         FIG. 7  is a flowchart of a method for executing the binary code of the secure function; 
         FIG. 8  is a schematic illustration of the structure of a data line of the binary code executed by the device of  FIG. 1 ; 
         FIG. 9  is a flowchart of a detail of a step of the method of  FIG. 7  employed to secure the data stored in a call stack of the device of  FIG. 1 ; 
         FIG. 10  shows schematic illustrations of various segments of the binary code of the secure function capable of being executed by the device of  FIG. 1 ; 
         FIG. 11  is a flowchart of a detail of a step of the method of  FIG. 6  employed to make buffer overflow attacks more difficult; 
         FIG. 12  is a schematic illustration of a call stack of the device of  FIG. 1 ; 
         FIG. 13  is a schematic illustration of a compiler able to generate the binary code executed by the device of  FIG. 1 . 
     
    
    
     SECTION I: CONVENTIONS, NOTATIONS AND DEFINITIONS 
     In the figures, the same references have been used to designate the same elements. In the rest of this description, features and functions well known to those skilled in the art are not described in detail. 
     In this description, the following definitions have been adopted. 
     A “program” designates a set of one or more predefined functions that it is desired to make a microprocessor execute. 
     A “source code” is a representation of the program in a computer language, not being directly executable by a microprocessor and being intended to be converted by a compiler into a machine code directly executable by the microprocessor. 
     A program or code is said to be “directly executable” when it is able to be executed by a microprocessor without this microprocessor needing beforehand to compile it by means of a compiler or to interpret it by means of an interpreter. 
     An “instruction” designates a machine instruction executable by a microprocessor. Such an instruction consists of:
         an opcode, or operation code, coding the nature of the operation to be executed, and   one or more operands defining the one or more values of the parameters of this operation.       

     A “machine code” is a set of machine instructions. It is typically a question of a file containing a succession of bits having the value “0” or “1”, these bits coding the instructions to be executed by the microprocessor. The machine code is directly executable by the microprocessor, i.e. without requiring compilation or interpretation beforehand. 
     A “binary code” is a file containing a succession of bits having the value “0” or “1”. These bits code data and instructions to be executed by the microprocessor. Thus, the binary code contains at least one machine code and in addition, generally, digital data processed by this machine code. 
     An “instruction flow” is a succession of instructions arranged one after the other and that forms, in the machine code, an ordered succession of bits. The instruction flow starts with an initial instruction and ends with a final instruction. With respect to a given instruction of the instruction flow, the instructions located on the side of the initial instruction are called “preceding instructions” and the instructions located on the side of the final instruction are called “following instructions”. In this text, this instruction flow is divided in memory into a succession of basic blocks that are immediately consecutive or separated by data blocks. 
     In this text, a “basic block” is a group of successive instructions of the instruction flow that starts at a branch address and that ends with a single explicit or implicit branch instruction. An explicit branch instruction is characterized by the explicit presence of an opcode in the machine code that codes the branch instruction. An implicit branch instruction corresponds to the case where the execution of a proceeding basic block systematically continues with the execution of a following basic block located, in the machine code, immediately after the preceding basic block. In this case, given that in absence of explicit branch instruction, the instructions of the machine code are executed in order one after the other, it is not necessary to insert, at the end of the preceding basic block, an explicit instruction to branch to the following basic block. In this description, in this case the preceding basic block is said to end with an implicit branch instruction because this instruction is not explicitly coded in the machine code. In this case, the preceding basic block ends just before the branch address of the following basic block. In this application, the expression “branch instruction” designates an explicit branch instruction unless otherwise mentioned. Thus, the execution of a basic block systematically starts with the execution of its first instruction and systematically ends with the execution of the branch instruction that ends this basic block. A basic block contains no other branch instructions than that located at the end of this basic block. Thus, the instructions of a basic block are systematically all read by the microprocessor one after the other in the order that they are present in this basic block. The branch instruction may direct, when it is executed, the control flow systematically to the same branch address or, alternatively, to different branch addresses. The latter case is encountered, for example, when, at the end of the executed basic block, the control flow may continue to a first or alternatively to a second basic block. 
     A “branch instruction” is an instruction that, when it is executed by the microprocessor, triggers a jump to the branch address of another basic block. Typically, to this end, this instruction replaces the current value of the program counter with the value of the branch address. It will be recalled that the program counter contains the address of the next instruction to be executed by the microprocessor. In the absence of branch instruction, each time an instruction is executed, the program counter is incremented by the size of the instruction currently being executed. In the absence of branch instruction, the instructions are systematically executed sequentially one after the other in the order in which they are stored in a main memory. The branch instruction may be unconditional, i.e. the jump to the branch address is systematically carried out as soon as this instruction is executed. An unconditional branch instruction is for example the “JAL” instruction in the RISC-V instruction set. The branch instruction may also be conditional, i.e. the jump to the branch address is triggered on the execution thereof solely if a particular condition is met. For example, a conditional branch instruction is a “BRANCH” instruction in the RISC-V instruction set. The branch instruction may also be a call to a function. In this text, unless otherwise indicated, the term “branch instruction” designates both direct and indirect branch instructions. A direct branch instruction is a branch instruction that directly contains the numerical value of the branch address. An indirect branch instruction is an instruction to branch to a branch address contained in a memory or a register of the microprocessor. Thus, contrary to a direct branch instruction, an indirect branch instruction does not directly contain the numerical value of the branch address. For example, an indirect branch instruction is the “JALR” instruction of the RISC-V instruction set. 
     A “branch address” is the address in the main memory at which the first instruction line of a basic block is located. Below, branch address is spoken of even for basic blocks the first instruction of which is executed following the execution of an implicit branch instruction. 
     Execution of a function is spoken of to designate the execution of the instructions that perform this function. 
     For the sake of simplicity, in this description and in the figures, the instructions have not been shown in binary form, but rather in a symbolic form expressed in a higher-level language. 
     SECTION II: ARCHITECTURE OF THE DEVICE 
       FIG. 1  shows an electronic device  1  comprising a microprocessor  2 , a main memory  4  and a bulk storage medium  6 . For example, the device  1  is a computer, a smart phone, a tablet computer or the like. 
     The microprocessor  2  here comprises:
         an arithmetic logic unit  10 ;   a set  12  of registers;   a control module  14 ;   a data input/output interface  16 ,   a loader  18  of instructions including a program counter  26 ,   a queue  22  of instructions to be executed, and   a hardware security module  28 .       

     The memory  4  is configured to store the instructions and data of a binary code  30  of a program that must be executed by the microprocessor  2 . The memory  4  is a random-access memory. Typically, the memory  4  is a volatile memory. The memory  4  may be a memory external to the microprocessor  2  as shown in  FIG. 1 . In this case, the memory  4  is produced on a substrate that is mechanically separate from the substrate on which the various elements of the microprocessor  2  such as the unit  10  are produced. 
     Here, the memory  4  is divided into successive machine words of fixed length. Each machine word may be transferred in a single clock cycle from the memory  4  to a register of the microprocessor. To this end, the size N MM  of a machine word is equal to the maximum number of bits that can be simultaneously transferred from the memory  4  to a register of the set  12 . Here, the size N MM  is strictly larger than N inst  bits, where N inst  bits is the number of bits of the instructions of the instruction set of the microprocessor  2 . Typically, N inst  is an integer higher than or equal to 8, 16, 32 or 64. In this example, N inst  is equal to 32 and the size N MM  is equal to 128 bits. 
     Conventionally, the memory  4  is mainly divided into three portions:
         a first portion  42  containing the instructions to be executed,   a second portion  44  containing the data to be processed, and   a third portion  46  used to save the execution context of a function when it calls another function.
 
The portion  46  is known as the call stack. Therefore, below the portion  46  is also referred to as the “stack  46 ”.
       

     The binary code  30  notably comprises a machine code  32  of a secure function and a block  34  of data required to execute the binary code  30 . The machine code  32  and the block  34  are stored in the portions  42  and  44 , respectively. 
     Each secure function corresponds to a set of a plurality of lines of code, for example several hundred or thousand lines of code, which are stored at successive addresses in the memory  4 . Here, each code line corresponds to one machine word. Thus, one line of code is loaded into a register of the microprocessor  2  in a single read operation. Likewise, one line of code is written to the memory  4  by the microprocessor  2  in a single write operation. Each line of code corresponds to a single instruction or to a single datum. Below, when the line of code contains an instruction, it is referred to as a “instruction line”. When the line of code contains a datum, it is referred to as a “data line”. The structures of an instruction line and of a data line are described in detail with reference to  FIGS. 2 and 8 . 
     The block  34  is typically located in a predefined address range at the start of the binary code  30 . Thus, the execution of the binary code  30  starts with the loading and processing of the data of the block  34 . Here, the block  34  notably comprises:
         a cryptogram ka* obtained by encrypting a key ka using a public key pk CPU  of the microprocessor  2 , and   cryptograms iv msbi *, iv ctei *, iv lsbi , iv msbd *, iv cted *, iv pile *, iv ctep *, encrypted using the public key pk CPU , of various values intended to initialize the content of various registers of the microprocessor  2  in order to allow the binary code  30  to be decrypted.       

     By way of illustration, the microprocessor  2  has an RISC (Reduced Instruction Set Computer) architecture and employs the RISC-V instruction set. 
     Here, the unit  10  is an arithmetic logic unit of N inst  bits. 
     The loader  18  loads into the queue  22  the next instruction to be executed by the unit  10  from the portion  42  of the memory  4 . More precisely, the loader  18  loads the instruction to which the program counter  26  points. 
     The unit  10  is notably configured to execute, one after the other, instructions loaded into the queue  22 . The instructions loaded into the queue  22  are generally systematically executed in the order in which these instructions were stored in this queue  22 . The unit  10  is also capable of storing the result of these executed instructions in one or more registers of the set  12 . 
     In this description, “execution by the microprocessor  2 ” and “execution by the unit  10 ” will be used as synonyms. 
     The module  14  is configured to move data between the set  12  of registers and the interface  16 . The interface  16  is notably able to acquire data and instructions, for example, from the memory  4  and/or the medium  6  external to the microprocessor 
     The module  28  is capable of automatically executing the various operations described in detail in the following sections in order to secure the execution of the secure functions. The module  28  functions independently and without using the unit  10 . Thus, it is capable of processing lines of code before and/or after the latter are processed by the unit  10 . To this end, it notably comprises a secure non-volatile memory  29 . This memory  29  can only be accessed through the module  28 . In this embodiment, the module  28  is programmed beforehand, for example during its design, to execute operations such as the following operations:
         verifying the integrity and authenticity of a datum via a message authentication code (MAC),   constructing a message authentication code,   encrypting a datum to obtain a cryptogram,   decrypting a cryptogram to obtain a plaintext datum,   executing a preprogrammed function F iv .       

     The memory  29  is used to store the secret information required to implement the method of  FIG. 6 . Here, it therefore notably contains secret information stored beforehand before the start of the execution of the binary code  30 . In particular, it contains the following information stored beforehand:
         a secret key k′ used to verify the message authentication codes,   a secret private key sk CPU  that allows the data that were encrypted using the public key pk CPU  to be decrypted.       

     In this example of an embodiment, the set  12  comprises general registers that are usable to store any type of data. The size of each of these registers is, for example, equal to N MM . 
     A data exchange bus  24  that links the various components of the microprocessor  2  to one another is shown in  FIG. 1  in order to indicate that the various components of the microprocessor may exchange data between one another. 
     The medium  6  is typically a nonvolatile memory. For example, it is an EEPROM or flash memory. It here contains a backup copy  40  of the binary code  30 . Typically, this copy  40  is automatically copied to the memory  4  to restore the code  30 , for example, after an interruption in current or similar, or just before the execution of the code  30  starts. 
     SECTION III: SECURING THE MACHINE CODE 
     Here, the structure of the machine code of the secure function is described in the particular case of the machine code  32 . However, what is described in this particular case may be transposed without difficulty to any machine code of a secure function. 
     The machine code  32  comprises a succession of instruction lines LI j  stored one after the other in the memory  4 . Below, in this section, the index j is used to identify the instruction line LI j  among the other instruction lines of the machine code  32 . In addition, the index j is also used as an order number indicating in which order the lines LI j  are classed. Thus, the instruction line located immediately after the line LI j  is denoted LI j+1 . Each instruction line LI j  codes one instruction of the instruction set of the microprocessor  2 , this line being executable after decryption and decoding by the unit  10  of this microprocessor. 
     The structures of all the lines LI j  are identical. This structure is shown in detail in  FIG. 2  in the particular case of the line LI j . 
     The line LI j  comprises a cryptogram CI j *, a code MAC j , and a code ECC Lj . 
     The cryptogram CI j * is obtained by encrypting a concatenation CI j  using the secret key ka and an initialization vector iv k . More precisely, the cryptogram CI j * is obtained using the following relationship: CI j *=f ka (CI j ; iv k ), where f ka  is an encryption function corresponding to a decryption function f ka   −1  programmed beforehand in the module  28 . Typically, the function f ka  is a symmetric encryption function. Thus, the key ka allowing the cryptogram CI j * to be decrypted is stored beforehand in the memory  29  in order to allow the module  28  to decrypt this cryptogram CI j *. The initialization vector iv k  is constructed as described below in this section. 
     The concatenation CI j  is here the concatenation of an instruction I j  to be executed by the microprocessor  2  and of a code ECC Ij . The code ECC allows an error to be detected in the instruction I j  and, potentially, this error to be corrected. For example, the code ECC Ij  may be the code known by the acronym BCH (Bose, Ray-Chaudhuri, Hocquenghem), which has the advantage of being particularly easy to implement. However, any other known error detection or correction code may be employed. The size of the code ECC Ij  is larger than or equal to 1 or 2 or 3 bits and, generally, smaller than N inst . The size of the code ECC Ij  is dependent on the desired robustness. The larger the number of erroneous bits that it is desired to be capable of correcting in the instruction I j , the larger the size of the code ECC Ij  will be. 
     The code MAC j  is a code allowing the integrity and authenticity of the cryptogram CI j * to be verified. This code is commonly called a “message authentication code” (MAC). Such a code MAC j  is obtained by constructing a label from the cryptogram CI j *, which normally contains fewer bits than the cryptogram CI j *. This label is constructed using a preset function and the secret key k′ known only to the author of the binary code  30  and to the microprocessor  2 . Here, the key k′ is stored beforehand in the memory  29 . For example, the preset function is a hash function. In this case, generally, the label is the result of the application of this hash function to a combination, for example a concatenation of the cryptogram CI j * and of the key k′. 
     By way of example, to generate the cryptogram CI j * and the code MAC j , an authenticated encryption algorithm is used. This authenticated encryption algorithm may be chosen from the various entrants to the CAESAR (Competition for Authenticated Encryption: Security, Applicability, and Robustness) such as for example one of the algorithms designated by the following names: “ACORN”, “ASCON”, “SILC”, “CLOC”, “JAMBU”, “KETJE”. 
     The code ECC Lj  is an error correction code that allows an error in the cryptogram CI j * and code MAC j  to be detected and corrected. It is for example constructed as described in the case of the code ECC Ij . 
     The cryptogram CI Ij * and the codes ECC Ij , MAC j  and ECC Lj  are, typically, constructed at the moment at which the machine code  32  is generated. 
     Below, the address @ j  in the memory  4  at which the line LI j  is stored will be noted. 
     The machine code  32  is composed of a succession of basic blocks that must be executed one after the other. Here, the basic blocks may have a structure of a first or second type. Below, basic blocks that have a structure of the first type and a structure of the second type are called “block of the first type” and “block of the second type”, respectively. The first type of structure is used in the case of direct branching. The second type of structure is used in the case of indirect branching. 
       FIG. 3  shows the first type of structure. More precisely,  FIG. 3  shows a first arrangement of two basic blocks  50  and  52  of the machine code  32 . In this first arrangement, the basic blocks  50  and  52  are systematically executed one after the other. In the order of execution, the basic block  50  precedes the basic block  52 . In this figure and the following figures:
         the order of execution of the basic blocks is represented by an arrow that points from the preceding basic block to the following basic block,   a dashed arrow that points to a shown basic block indicates that the one or more basic blocks that precede this basic block have not been shown to simplify the figure,   a dashed arrow that points into empty space from a shown basic block indicates that the one or more basic blocks following this shown basic block have not been shown to simplify the figure,   the symbol “ . . . ” inside a basic block indicates that all the instruction lines of this basic block have not been shown.       

     Each basic block is composed of a succession of instruction lines that each contain the cryptogram CI j * of the instruction I j  to be executed and the code MAC j . In addition, each basic block starts with a branch address and ends with an instruction line that contains the cryptogram of a branch instruction. More precisely, in the case of the first type of structure, the first line of the basic block, i.e. the line located at the branch address, is the first instruction line of the basic block. Basic blocks of the first type contain no data line. 
     In  FIG. 3 , the symbols “@50” and “@52” beside the first line of each basic block designate the branch addresses of the basic blocks  50  and  52 , respectively. The symbol “@XX” designates the branch address of another basic block (not shown in  FIG. 3 ). 
     The symbol “Load iv lsbXX ” indicated in the penultimate instruction line of the basic block indicates that this instruction line contains the cryptogram of a direct load instruction. When the direct load instruction is executed by the microprocessor  2 , it causes a new value iv lsbXX  to be loaded into a register iv branch  of the microprocessor  2 . The value iv lsbxx  is contained directly in the instruction “Load iv lsbxx ”. In other words, the value iv lsbxx  is an operand of the “Load iv lsbxx  instruction. It will be noted that the value iv lsbxx  is here coded on 32 bits and therefore has the same length as an instruction. Thus, although in this text a direct load instruction is spoken of, in practice this instruction is generally implemented in the form of first and second instructions of 32 bits of the instruction set of the microprocessor  2 . Typically, when they are executed, the first instruction loads a first portion of the bits of the value iv lsbxx  into the register iv branch  and the second instruction loads the other bits of the value iv lsbxx  into this register iv branch . 
     The symbol “xx” in the value iv lsbxx  is an identifier of this value. Specifically, each time the instruction “Load iv lsbxx ” is executed, it causes a specific value to be loaded that allows the instruction lines of the following basic block to be decrypted. Thus, the symbol “Load iv lsb52 ” indicates that the value iv lsb52  is loaded into the register iv branch  before the start of the execution of the basic block  52 . 
     The symbol “Branch @XX” indicated in the last instruction line of the basic block indicates that the latter line contains the cryptogram of a direct branch instruction that, when it is executed by the microprocessor  2 , causes a direct branch to the branch address @XX. When it is executed, this instruction also causes the value contained in the register iv branch  to be loaded into a register iv lsbi  of the microprocessor  2 . The register iv lsbi  contains the 32 least significant bits of the initialization vector iv k  currently being used to decrypt the instruction lines. 
     In this embodiment, the vector iv k  is coded on 128 bits. The 32 most significant bits are stored in a register iv msbi . The 64 bits located between the 32 least significant bits and the 32 most significant bits are stored in one or more registers that are collectively designated by the term “register iv ctei ”. Each vector iv k  is therefore the result of the concatenation of the bits of the registers iv msbi , iv ctei  and iv lsbi . Here, the values contained in the registers iv msbi  and iv ctei  remain constant throughout the execution of the machine code. For example, the registers iv msbi  and iv ctei  are loaded with these constant values at the start of the execution of the machine code  32 . These constant values are obtained by decrypting the cryptograms iv msbi * and iv ctei * contained in the block  34 . 
     The same initialization vector iv k  is used to decrypt all the cryptograms CI j * of all the instruction lines of the same basic block BB k . The index k unambiguously identifies the basic block BB k  among all the basic blocks of the machine code  32 . In the figures and in the description below, the symbol iv k  is used to designate, in a general way, the initialization vector to be used to decrypt the instruction lines of the basic block BB k . In addition, in simple cases such as that shown in  FIG. 3  in which two basic blocks follow in the order of execution of the machine code  32 , the index k is also used to indicate the order in which these basic blocks are executed. For example, the notation BB k-1  is, in these simple cases, used to designate the preceding basic block systematically executed immediately before the basic block BB k . 
     Here, the initialization vector iv k  is unique to each basic block BB k . By “unique to each basic block” what is meant is the fact that the probability that two different basic blocks of the machine code  32  are encrypted with the same initialization vector iv k  is lower than one chance in 100 or in 1000. In particular, the expression “unique to each basic block” therefore covers the case where the initialization vectors iv k  of all the basic blocks are systematically different from one another. For example, in a simple embodiment, during the generation of the code  32 , the 32 least significant bits of the initialization vectors iv k  of each basic block are drawn randomly or pseudo-randomly from the set {1; . . . ; 2 Ninst }. 
     As shown in  FIG. 3 , in the code  32 , the 32 least significant bits of the initialization vector iv k  are loaded into the register iv branch  solely during the execution of a basic block preceding the basic block BB k . In  FIG. 3 , the initialization vector iv lsb52  required to decrypt the block  52  is loaded during the execution of the block  50 . 
       FIG. 4  shows another possible arrangement of a plurality of basic blocks of the code  32  in the particular case of two preceding basic blocks  60  and  62  and of one following basic block  64 . The blocks  60 ,  62  and  64  are basic blocks of the first type. Here, the blocks  60  and  64  are, for example, identical to the blocks  50  and  52 , respectively, except that the 32 least significant bits of the initialization vector of the block  64  are denoted “iv lsb64 ”. The block  62  is constructed as the block  60  and, in particular, it ends with two instruction lines that code the same instructions as those coded in the last two lines of the block  60 . However, even though these last two lines code the same instructions, the cryptograms of these instructions are different because the block  62  is encrypted using an initialization vector iv 62  different from the vector iv 60  used to encrypt the block  60 . The other instruction lines of the block  62  are different from those of the block  60 . 
       FIG. 5  shows one portion of the architecture of the machine code  32  when a function F 1  of the machine code  32  calls an external function F 2 . To this end, the machine code of the function F 1  contains a basic block  70  that ends with a call to the machine code  68  of the function F 2 . 
     The machine code  68  is arranged as described for the machine code  32 . It is therefore composed of a succession of basic blocks. To simplify  FIG. 5 , only the first basic block  80  and the last basic block  82  of this machine code  68  have been shown. Here, when the execution of the function F 2  has ended, i.e. after the execution of the block  82 , the execution of the machine code  32  continues with the execution of a basic block  72 . 
     The instruction lines of the blocks  70 ,  72 ,  80  and  82  are encrypted using vectors iv 70 , iv 72 , iv 80  and iv 82 , respectively. 
     Here, the machine code  32  is a dynamic code that was generated independently of the machine code  68 . For example, the machine code  68  was generated before or after the machine code  32  was generated. For example, the machine code  68  is the code of a function of a library of functions stored beforehand. In this case, typically, the machine code  68  may be called, at different times, by various machine codes. The address @80 of the block  80  is therefore not known at the moment at which the machine code  32  is compiled. For this reason, the block  70  ends with an instruction line containing the cryptogram of an indirect branch instruction denoted “BranchIV rd” in  FIG. 5 . When the instruction “BranchIV rd” is executed by the microprocessor  2 , it causes a jump to a branch address @ j  constructed from the current content of a register rd of the microprocessor  2 . The address @ j  is typically constructed from the content of the register rd using the following relationship: @ j =rd+offset+4, where:
         @ j  is the constructed address,   rd is the value contained in the register rd,   “offset” is a preset numerical value, and   the symbol “+4” indicates that a constant value is added to the result of the sum rd+offset so that the address @ j  is equal to the address of the instruction line that immediately follows that located at the address rd+offset.
 
Conventionally, the value “offset” is passed as an operand of the instruction “BranchIV rd”.
       

     At this stage, it will be noted that when the sum rd+offset corresponds to the address of the first line of a basic block, the sum rd+offset+4 corresponds to the address of the second line of this basic block. Thus, contrary to a conventional indirect branch instruction, the instruction “BranchIV” causes a jump directly to the second line of the following basic block. The first line of this following basic block is therefore not executed in this embodiment. 
     The register rd is loaded with a value allowing the address @80 to be constructed. Typically, the register rd is loaded with the value that allows the address @80 to be constructed, at the start of the execution of the binary code  30 , by a dynamic library loader or “loader” for short. This dynamic library loader is, for example, that of an operating system executed by the microprocessor  2 . Since the mechanism of dynamic library loaders is well known, it will not be described here. 
     Likewise, since the machine code  68  to be executed is not known at the moment of compilation of the machine code  32 , the vector iv 80  to be used to decrypt the instruction lines of this block  80  is also not known. It is therefore not possible to insert, during the compilation of the machine code  32 , the instruction “Load iv isb80 ”, which was described above, into the block  70  in order to cause the vector iv isb80  to be directly loaded into the register iv branch . Instead, during the generation of the machine code  32 , an instruction to indirectly load an initialization vector, which instruction is denoted “LoadIV rd”, is inserted just before the instruction “BranchIV rd”. When it is executed by the microprocessor  2 , the instruction “Load IV rd” causes:
         the content of the data line located at an address constructed from the content of the register rd to be read, then   the 32 least significant bits of the vector iv 80  to be constructed from the content of the read data line, then   the 32 least significant bits thus constructed to be loaded into the register iv branch .       

     Here, in the case of the instruction “LoadIV rd”, an address is constructed from the content of the register rd using the following relationship: @ k =rd+offset, where “rd” and “offset” are the same as those used in the instruction “BranchIV rd”. Thus, the constructed address is the address of the first line of the following basic block. Below, the address of the first line of the basic block BB k  is denoted @ k . 
     The block  80  is a basic block of the second type. A basic block BB k  of the second type is identical to a basic block of the first type except that the first line of this basic block contains a data line LD k  and not an instruction line. This line LD k  contains the data allowing the 32 least significant bits of the initialization vector iv k  used to encrypt the instruction lines of this basic block BB k  to be constructed. To this end, it contains a cryptogram, denoted iv lsbi * in the figures, of the 32 least significant bits of the vector iv k . In this embodiment, the cryptogram iv lsbi * is obtained using the following relationship iv lsbi *=f ka (iv lsbi ; iv j ), where:
         iv lsbi  is the value of the 32 least significant bits of the vector iv k ,   iv j  is an initialization vector, different from the vector iv k , used to encrypt the data lines, and   the function f ka  is the same as that described above in the case of the encryption of the instructions.       

     The structure of a data line such as the line LD k  is described below with reference to  FIG. 8 . 
     Similarly to as described for the vector iv k , the vector iv j  is coded on 128 bits. The 32 most significant bits are stored in a register iv msbd . The 32 least significant bits are stored in a register iv lsbd . The 64 bits located between the 32 least significant bits and the 32 most significant bits are stored in one or more registers collectively designated by the term “register iv cted ”. Each vector iv j  is therefore the result of the concatenation of the bits of the registers iv msbd , iv cted  and iv lsbd . Here, the contents of the registers iv msbd  and iv cted  remain constant throughout the execution of the machine code. For example, the registers iv msbd  and iv cted  are loaded with these constant values at the start of the execution of the machine code  32 . Preferably, the values loaded into the registers iv msbd  and iv cted  are different from those loaded into the registers iv msbi  and iv ctei . 
     The content of the register iv lsbd , which is used to encrypt the data, depends on the address @ k  at which the line LD k  is stored. Specifically, the module  28  contains a function F iv  programmed beforehand that, with each address @ j  of the memory  4 , associates a different value of the register iv lsbd . For example, the function F iv  is a hash or encryption function. There is therefore the following relationship: iv lsbd =F iv (@ j ), where iv lsbd  designates the content of the register iv lsbd . 
     The machine code  68  may be called from various basic blocks of the machine code  32  or from various machine codes. Thus, the basic block that must be executed after the basic block  82  depends on the basic block that called the machine code  68 . It is not known at the moment of generation of the machine code  68 . Therefore, just like the block  70 , the basic block  82  is a basic block of the first type that ends with an instruction line that codes an instruction “LoadIV ra” followed by an instruction line that codes the instruction “BranchIV ra”. The instructions “LoadIV ra” and “BranchIV ra” are identical to the instructions “LoadIV rd” and “BranchIV rd” described above, respectively, except that the register rd is replaced by the register ra. 
     When the code  68  is called from the block  70 , the return address @ 72  of the machine code  68  is typically saved in the register ra of the microprocessor  2 . If the machine code  68  itself calls another function, then the address @ 72  is saved in the call stack  46  and re-saved in the register ra just before the instructions “LoadIV ra” and “Branch IV ra” of the block  82  are executed. 
     The block  72  is a basic block of the second type. Its first line at the address @ 72  is therefore a data line that contains the cryptogram iv lsbi * required to construct the vector iv 72  that allows its instruction lines to be decrypted. 
       FIG. 6  shows the main registers described up to now. These registers may be registers of the set  12  and/or registers of the module  28 . Preferably, the registers of the module  28  are used to store the information used to encrypt or decrypt. Thus, preferably, the registers iv msbi , iv ctei , iv lsbi , iv msbd , iv cted , iv lsbd , iv pile , iv ctep , iv isbp , iv temp , iv branch , iv rnd  are registers contained in the memory  29 . In addition to the registers already described, the microprocessor  2  comprises registers iv cted , iv lsbd , iv pile , iv ctep , iv lsbp , iv temp , iv branch , iv rnd  and sp, which are described in more detail in the following sections. 
       FIG. 7  shows a method for executing the binary code  30  with the microprocessor  2 . 
     The method starts with a step  150  of delivering the binary code  30  to the memory  4 . To do this, for example, the microprocessor  2  copies the copy  40  to the memory  4  to obtain the binary code  30  stored in the memory  4 . 
     Next, in a phase  152 , the microprocessor  2  executes the binary code  30  and, in particular, the machine code  32 . 
     Optionally, the execution of the binary code  30  starts with a step  154  of authenticating the author of this binary code. If all the authentication was carried out with success, then the method continues with a step  162 . In contrast, if the authentication was not carried out with success, the module  28  then considers the authentication of the author of the binary code  30  to have failed and the method continues with a step  163 . In the step  163 , the execution of the binary code  30  is stopped. 
     In step  162 , the module  28  loads the cryptograms ka* and iv msbi *, iv ctei *, iv isbi *, iV msbd *, kf cted *, iV pile *, iv ctep * contained in the block  34  and decrypts them using the key sk CPU  contained in the memory  29 . The module  28  initializes the values contained in the registers iv msbi , iv ctei , iv isbi , iv msbd , iv cted , iv pile , iv ctep  using the decrypted cryptograms iv msbi *, iv ctei *, iv isbi *, iv msbd *, iv cted *, iv pile *, iv ctep *, respectively. At the end of step  162 , the key ka and the initialization vector iv k  used to decrypt the first basic block of the machine code  32  are contained in the memory  29 . 
     After the step  162 , the microprocessor  2  executes, one after the other, the basic blocks starting with the first basic block BB 1  of the machine code  32 . 
     The execution of each basic block consists in executing, in the order in which the instruction lines LI j  of this basic block are stored in the memory  4 , the instructions coded by each of these instruction lines. 
     For each of the instruction lines LI j  to be executed of the machine code  32 , the microprocessor  2  executes the following steps. 
     In a step  164 , the microprocessor  2  loads, into a register of the set  12 , the instruction line stored at the address @ j  contained in the program counter  26 . 
     Next, the module  28  proceeds to a step  166  of securing the instruction coded in the loaded instruction line. 
     The way in which step  166  works is now described in the case of the line LI j . More precisely, in step  166 , the module  28  carries out in succession the following operations. 
     In an operation  170 , the module  28  verifies whether there is an error in the cryptogram CI j * or the code MAC j  using the code ECC Lj  contained in the loaded line LI j . For example, to do this, the module  28  constructs, using a function programmed beforehand and the cryptogram CI j * and the code MAC j , a code ECC Lj ′. If the code ECC Lj ′ is different from the code ECC Lj , then an error is detected. If an error is detected, the module  28  immediately proceeds to a step  172 . 
     In step  172 , the module  28  triggers the signalling of an execution fault. 
     Here, in parallel to step  172 , if an error is detected, the module  28  proceeds with an operation  174 . In the operation  174 , it corrects the cryptogram CI j * and the code MAC j  using the information contained in the code ECC Lj . At the end of step  174 , the corrected cryptogram CI j * and the corrected code MAC j  are used instead of the cryptogram CI j * and code MAC j  contained in the line LI j , respectively. 
     The operation  170  notably allows faults introduced into the instruction line stored in the memory  4  to be detected and corrected. 
     At the end of the operation  174  or if no error was detected during the operation  170 , the method continues with an operation  176 . 
     During the operation  176 , the module  28  verifies the integrity and authenticity of the cryptogram CI j * using the code MAC j . For example, to do this, the module  28  constructs a label of the cryptogram CI j *, then encrypts this label with the key k′ contained in its memory  29 . If the cryptogram thus constructed is identical to the loaded code MAC j , then the integrity and authenticity of the cryptogram CI j * are confirmed. In this case, the module  28  proceeds with an operation  178 . In the contrary case, the module  28  proceeds with step  172 . 
     The operation  176  on the one hand allows the authenticity of the loaded line of code to be validated but also allows, during the operation  174 , it to be validated whether the cryptogram CI j * and/or the code MAC j  have been correctly corrected. The verification of authenticity prevents the replacement of the line of code with another line of code constructed by an author who did not know the key k′. 
     During the operation  178 , the module  28  decrypts the cryptogram CI j * using the key ka and the initialization vector iv k  to obtain the decrypted instruction I j  and the decrypted code ECC Ij . The key ka was stored in the memory  29  in step  162 . The vector iv k  required to decrypt the cryptogram CI j * was stored in the registers iv msbi  iv ctei  and iv lsbi  during the execution of the instruction “Branch @xx” or “BranchIV rd” or “BranchIV ra” coded in the basic block preceding the block that contains this currently processed line LI j . If the line LI j  is contained in the first basic block BB ini  of the machine code  32 , it is the initial values of the registers iV msbi , iv ctei  and iv lsbi  that are used. 
     Here, it is the execution of the branch instruction “Branch @xx” or “BranchIV rd” or “BranchIV ra”, by the unit  10 , that indicates to the module  28  that it must replace the content of the register iv isbi  with the content of the register iv branch . The content of the register iv branch  is updated during the execution of the instruction “Load iv xx ” or “LoadIV rd”” or “LoadIV ra” that proceeds the branch instruction. 
     Next, in an operation  180 , the module  28  stores the decrypted instruction I j  and the decrypted code ECC Ij  in the queue  22 . 
     Once the unit  10  has executed all the instructions that precede the instruction I j  in the queue  22 , i.e. when the instruction I j  is the next instruction to be executed by the unit  10 , the module  28  proceeds with an operation  184 . 
     During the operation  184 , the module  28  verifies whether there is an error in the instruction I j  contained in the queue  22  using the code ECC Ij  associated with the instruction I j  and contained in the same queue  22 . This operation is carried out in a similar way to the operation  170 . 
     If the module  28  detects an error, then it immediately proceeds with step  172 . In addition, in parallel, in an operation  186 , the module  28  corrects the instruction I j  using the code ECC Ij . The operation  186  is similar to the operation  174 . 
     Next, at the end of the operation  186  or if no error was detected in the operation  184 , the step  166  ends and the method continues with a step  190  of executing the instruction I j  with the unit  10 . 
     In step  190 , the unit  10  executes the instruction 
     As shown in  FIG. 7 , in parallel to step  190 , the method may comprise:
         a step  198  of securing the call stack  46 , and/or   a step  250  of securing the processed data.       

     These steps  198  and  250  are described in more detail in the following sections. 
     The operation  184  allows a modification of the instruction I j  made between the time at which it was stored in the queue  22  and the time at which it is executed by the unit  10  to be detected. 
     The operation  184  also allows an execution fault to be signalled if the control flow of the machine code  32  has been modified. Specifically, a modification of the control flow manifests itself by the fact that after the execution of the basic block BB k-1  it is not the basic block BB k  that is executed but another basic block BB t . In this case, during the execution of the block BB k-1 , the initialization vector iv k-1  is loaded into the registers iv msbi , iv ctei  and iv isbi . Thus, during the execution of the block BB t , the cryptogram CI j * is decrypted using the vector iv k  that corresponds to BB k  and not using the vector iv t  that corresponds to the block BB t . Therefore, the decryption of the cryptogram CI j * using the vector iv k  leads to the obtainment of an incorrect instruction I j  and of an incorrect code ECC Ij  and this is detected in the operation  184 . The operation  184  makes it possible to detect a disruption in the execution not only of the operation “Branch @XX” but also of the operation “BranchIV ra” or “BranchIV rd”. 
     The operation  184  also allows the permutation, in the memory  4 , of the two basic blocks BB k  and BB t  of the second type to be detected. Specifically, if the block BB k  is replaced by the block BB t , then, during the execution of the instruction “Load IV ra” of the block BB k-1 , the first data line of the block BB t  is decrypted using a vector iv j  constructed using the address @ k  and not using the address @ t . This therefore leads to an incorrect decryption of the cryptogram iv isbi * and therefore to an incorrect decryption of the first instruction line of the block BB t . This incorrect decryption of the first instruction line of the block BB t  is detected in the operation  184 . 
     During the execution of the machine code  32 , if attacks lead to the alteration of an instruction to be protected or to the modification of the control flow, the microprocessor  2  signals, in step  172 , a fault in the execution of the machine code  32 . 
     In response to such signalling, in a step  192 , the microprocessor  2  implements a plurality of countermeasures. Very many countermeasures are possible. The countermeasures implemented may have very different degrees of severity. For example, the countermeasures implemented may range from simply displaying or simply storing in memory an error message without interrupting the normal execution of the machine code  32  up to definitively taking the microprocessor  2  out of service. The microprocessor  2  is considered to be out of service when it is definitively placed in a state in which it is incapable of executing any machine code. Between these extreme degrees of severity, there are many other possible countermeasures such as:
         indicating, by way of a human-machine interface, the detection of faults,   immediately interrupting the execution of the machine code  32  and/or resetting it, and   deleting the machine code  32  from the memory  4  and/or deleting the backup copy  40  and/or deleting the secret data.       

     In addition, here the countermeasure implemented in step  192  may be selected depending on the detected error and therefore depending on the operation that led to the detection of this fault. For example, the selected countermeasure will change depending on whether the error was detected in operation  176  or  184 . 
     SECTION IV: SECURING THE DATA OF THE CALL STACK 
     Each time a calling function triggers the execution of a called function, the execution context of the calling function is saved in the stack  46 . In addition, the called function also saves in the stack  46  data such as local variables. 
     Similarly to the case of the instructions I j , a datum D j  stored in the stack  46  may be corrupted by buffer overflow attacks or by other types of attacks such as a fault-injection attack. 
     To make the stack  46  more robust to such attacks, here, each datum D j  stored in the stack  46  is coded in a respective line LD j . The line LD j  is a data line. Contrary to the instruction lines LI j  described in section III, each line LD j  codes a datum D j  to be processed by the microprocessor and not an instruction I j  executable by the unit  10 . 
     The structure of a line LD j  is shown in  FIG. 8 . Here, the structure of the line LD j  is identical to the structure of the line LI j  except that the cryptogram CI j * has been replaced by a cryptogram CD j *. Given that the codes MAC j  and ECC Lj  of the line LD j  are computed as already described in the case of the lines LI j , they are here designated by the same symbols and are not described again. 
     The cryptogram CD j * is obtained by encrypting, with the function f ka , a concatenation CD j . Here, the function f ka  is the same as that already described in the case of the lines LI j . Thus, the cryptogram CD j * is obtained using the following relationship: CD j *=f ka (CD j ; iv p ). The function f ka  is programmed beforehand in the module  28 . 
     Similarly to the vector iv k , the vector iv p  is coded on 128 bits. The 32 most significant bits are stored in a register iv pile  of the microprocessor  2 . The 32 least significant bits are stored in a register iv lsbp  of the microprocessor  2 . The 64 bits located between the 32 least significant bits and the 32 most significant bits are stored in one or more registers of the microprocessor  2  collectively designated by the term “register iv ctep ”. Each vector iv p  is therefore the result of the concatenation of the bits of the registers iv pile , iv ctep  and iv lsbp . Here, the content of the register iv ctep  remains constant throughout the whole execution of the machine code. For example, the register iv ctep  is loaded with this constant value at the start of the execution of the machine code  32 . Here, the value contained in the register iv ctep  is obtained by decrypting the cryptogram iv ctep * of the block  34 . For example, the register iv ctep  is loaded at the start of the execution of the code  32  with a constant value different from those contained in the registers iv ctei  and iv cted . 
     The content of the register iv lsbd , which is used to encrypt the data, depends on the address @ j  at which the line LD j  containing this datum is stored. Specifically, the module  28  uses the function F iv  described above. There is therefore the following relationship: iv lsbd =F iv (@ j ), where iv lsbd  designates the content of the register iv lsbp . 
     The concatenation CD j  is the concatenation of the datum D j  and of a code ECC Dj . The code ECC Dj  allows an error in the datum D j  to be detected and corrected. It is typically constructed as described for the code ECC Ij . 
     The cryptogram CD j * differs from the cryptogram CI j * in that the initialization vector iv p  used during the encryption of the concatenation CD j  changes depending on the address of the line LD j  and also each time a new function stores data in the stack  46 . 
     The way in which the data D j  saved in the stack  46  are secured will now be described in more detail with reference to the method of  FIG. 9  and in the particular case where they are implemented in combination with the teachings of the other sections. More precisely, the data D j  are secured each time the instruction executed in step  190  is an instruction to read or write a datum D j  from or to the stack  46 . The method of  FIG. 9  shows the operations executed in step  198  to secure the data D j . 
     Each time that, in the step  190 , the unit  10  executes an instruction that leads to a new datum D j  to be stored in a register, here denoted R j , of the set  12 , in an operation  252 , the module  28  computes the code ECC Dj  from the datum D j . This computed code ECC Dj  is then concatenated with the datum D j  in the register R j . 
     Subsequently, during a new execution of the step  190 , the unit  10  executes an instruction to store the datum D j  contained in the register R j  at the address @ j  in the stack  46 . 
     In response, during operation  254 , the module  28  constructs the line of code LD j  that must be stored at the address @ j  from the datum D j . To do this, during this operation, the module  28 :
         updates the content of the register iv lsbp  using the relationship iv lsbp =F iv (@ j ), then   encrypts the concatenation CD j  of the datum D j  and of the code ECC Dj  using the function f ka  and the initialization vector iv p  by using the following relationship: CD j *=f ka (CD j ; iv p ), then   computes the code MAC j  from the cryptogram CD j *, then   computes the code ECC Lj  from the cryptogram CD j * and from the computed code MAC j .       

     Next, the constructed line LD j  is transferred and stored in the stack  46  at the address @ j . 
     If the next instruction to be executed in step  190  is an instruction to load a line LD j , then, the unit  10  executes this instruction and the line LD j  is loaded into a register of the microprocessor  2 . Typically, this load instruction contains an operand that indicates at which address @ j  the line LD j  to be loaded is found. Here, when the unit  10  executes this load instruction, it loads the line LD j  into a register R j  of the set  12  for example. 
     Next, the module  28  executes operations  270 ,  274 ,  276  and  278  that are identical to the operations  170 ,  174 ,  176  and  178 , respectively, of the method of  FIG. 7 , except that it is the corresponding codes contained in the line LD j  that are used and not those contained in a line LI j . 
     In addition, during the operation  278 , the module  28  updates the content of the register iv lsbp  required to decrypt the cryptogram CD j * using the address a and the relationship iv lsbp =F iv (@ j ). 
     Once the cryptogram CD j * has been decrypted, in an operation  280 , the module  28  stores the decrypted datum D j  and the decrypted code ECC Dj  in the register R j , while waiting for this datum to be processed by the unit  10 . 
     When the next instruction that will be executed by the unit  10  is an instruction that processes the datum D j , the module  28  proceeds with operations  284  and  286 . The module  28  identifies that the next instruction to be executed will process the datum D j  because this instruction generally contains an operand that identifies the register R j  in which the datum D j  is stored. Operations  284  and  286  are, for example, identical to operations  184  and  186  of the method of  FIG. 7 , respectively, except that here it is the datum D j  and code ECC Dj  that are used and not the instruction I j  and the code ECC Ij . 
     Next, at the end of the operation  286  or if no error was detected in operation  284 , the unit  10  executes the instruction, which processes the datum D j . 
     The method for securing the data described here furthermore has the same advantages as those presented in section III notably because of the fact that the structure of the line LD j  is practically identical to that of the line LI j . 
     In addition, the fact of encrypting the datum D j  using an initialization vector iv lsbp  that depends on the address @ j  makes it possible to detect whether a line LD j  has been moved inside the stack  46 . Specifically, if two lines LD 1  and LD 2  are permutated, such a permutation of the lines LD 1  and LD 2  is not necessarily detected in operation  270  or  276 . In contrast, since the datum D 1  is encrypted with an initialization vector iv 1  that depends on the address @ 1 , if the line LD 1  is moved and is located at an address @ 2  in the stack  46 , during the loading of this line from this address @ 2 , the cryptogram CD 1 * will be decrypted using the initialization vector iv 2  and not using the vector iv 1 . Such an incorrect decryption of the datum D 1  and of the code ECC D1  is then detected in operation  284 . 
     SECTION V: SECURING AGAINST BUFFER OVERFLOW ATTACKS 
     As already explained with reference to  FIG. 5 , in the case of the RISC-V instruction set, when the function F 2  is called by the function F 1 , the return address @ra 2  to be used to continue the execution of the function F 1  after the execution of the function F 2  is stored in a register ra of the set  12 . In contrast, if during the execution of the function F 2 , a function F 3  is called, then, at this moment, the address @ra 2  and, more generally, the execution context of the function F 2 , is saved in the stack  46 . 
     The execution context notably comprises all the information necessary to restart the execution of the function F 2  once the execution of the function F 3  has ended. It furthermore comprises:
         the address @ra 2 ,   the value of a pointer sp that points to the top of the stack  46 ,   potentially, the values of certain data in the process of being processed by the function F 2 .       

     During its execution, the function F 3  may, it as well, save data in the stack  46 , in a predefined space of the memory called the “buffer”. It is possible to write to this buffer data that are greater in amount than the space allocated to this buffer for saving these data. This leads to what is known as “buffer overflow”. 
     When this buffer overflow is generated intentionally, it may be used to replace the address @ra 2  with another address @rat chosen by an attacker. Under these conditions, at the end of the execution of the functions F 2  and F 3 , it is not the function F 1  that is executed, but instructions located at the address @rat. A buffer overflow may therefore be used to divert the control flow to code developed and designed by an attacker. Typically, this type of attack is employed to bypass security measures and/or to obtain secret information on the operation of the secure function. 
     In this section, one solution for combating this type of attack is described. Here, this solution is described in the particular case where the teaching of the other sections, and in particular of section IV, is implemented at the same time. 
     More precisely, to make buffer overflow attacks more difficult, the vector iv p  used to encrypt the return address @ra 2  saved in the stack  46  is different from that used by the called function F 3  when data is saved in the stack  46 . 
     To this end, the prologue PF 3  and epilogue EF 3  of the call to the function F 3  are modified as shown in  FIG. 10 . 
       FIG. 10  is divided into three vertical columns designated by the references F 1 , F 2  and F 3 . The basic blocks of the functions F 1 , F 2  and F 3  are shown in columns F 1 , F 2  and F 3 , respectively. 
     The instruction lines of the basic blocks of the functions F 1 , F 2  and F 3  are secured as described in section III. Therefore, the basic blocks of the functions F 1 , F 2  and F 3  are, either basic blocks of the first type, or basic blocks of the second type such as described above. 
     The function F 1  comprises a basic block  202  and a basic block  204 . The block  202  is here a basic block of the first type. The basic block  202  ends with an instruction line that codes an instruction, denoted “Branch @F 2 ” in  FIG. 10 , to branch to the first instruction line of the first basic block  208  of the function F 2 . It will be recalled here that when the instruction denoted “Branch @F 2 ” is executed, the return address @ra 2  is stored in the register ra of the set  12 . 
     The basic block  204  is the basic block of the function F 1  that must be executed when the execution of the function F 2  ends. Its first line is therefore located at the address @ra 2 . Here, the execution of the basic block  204  is triggered following the execution of an indirect branch instruction located at the end of the function F 2 . Therefore, here, the basic block  204  is a basic block of the second type. 
     The function F 2  starts with the basic block  208  and ends with a basic block  214 . Here, these basic blocks  208  and  214  are basic blocks of the first type. 
     Between these blocks  204  and  214 , the function F 2  comprises a basic block  210  and a basic block  212 . The basic block  210  contains the instruction lines of the prologue PF 3 , which is executed by the microprocessor  2  before the start of the execution of the first basic block  220  of the function F 3 . 
     The last instruction line of the prologue PF 3  codes a direct branch instruction, denoted “Branch @F 3 ”, to branch to the first instruction line of the block  220 . During the execution of this instruction, the return address @ra 3  of the function F 3  is stored in the register ra. Therefore, beforehand, the address @ra 2  that was found in this register ra must be saved in the stack  46 . To this end, the prologue PF 3  contains an instruction line denoted “Store @ra 2 , @ j ” that, when it is executed by the microprocessor  2 , saves the address @ra 2  at the address a in the stack  46 . As explained in section IV, it is therefore a line LD j  containing a cryptogram CD j * constructed from the address @ra 2  that is saved at the address @ j  in the stack  46 . 
     It will be recalled here that the cryptogram CD j * is obtained using the vector iv p . This vector iv p  is the result of the concatenation of the bits contained in the registers iv pile , iv ctep  and iv lsbp . The content of the register iv lsbp  is equal to F iv (@ j ), where @ j  is the address in the stack  46  at which the datum must be saved. 
     Below, the value contained in the register iv pile  at the moment at which the instruction “Store @ra 2 , @ j ” is executed is denoted iv a . Thus, the address @ra 2  is encrypted using the value iv a  contained in the register iv pile  and the address @ j . 
     Next, between the instructions “Store @ra 2 , @ j ” and “Branch @F 3 ”, the prologue PF 3  contains instruction lines coding instructions to:
         save the value iv a  in the stack  46 , and   replace the value iv a  of the register iv pile  with a new value iv b .       

     To this end, the prologue PF 3  contains in succession:
         an instruction line coding an instruction denoted “LoadIV iv temp , iv pile ”,   an instruction line coding an instruction denoted “LoadIV iv pile , iv rnd ”, and   an instruction line coding an instruction denoted “StoreIV iv temp , @ j+1 ”.       

     When it is executed by the microprocessor  2 , the invention “LoadIV iv temp , iv pile ” causes the content of the register iv pile  to be stored in the register iv temp . Thus, after the execution of this instruction, the value iv a  is saved in the register iv temp . 
     When it is executed by the microprocessor  2 , the instruction “LoadIV iv rnd ” causes the content of the register iv rnd  to be stored in the register iv pile . 
     The register iv rnd  is here a register that is connected to a generator of random or pseudo-random numbers. Thus, each time its content is read from or loaded into another register, the register iv rnd  contains a new value constructed by the generator of random or pseudo-random numbers. 
     Thus, after the execution of the instruction “LoadIV iv pile , iv rnd ”, the register iv pile  contains the new value iv b  and this new value iv b  was generated randomly or pseudo-randomly. 
     When the extraction “StoreIV iv temp , @ j+1 ” is executed by the microprocessor  2 , it causes the value iv a  contained in the register iv temp  to be saved in the stack  46  at the address denoted @ j+1 . For example, the address @ j+1 , is the address that immediately follows the address @ j  in the stack  46 . Since the instruction “StoreIV iv temp , @ j+1 ” is executed after the instruction “LoadIV iv pile , iv rnd ”, the value iv a  is encrypted using the new value iv b  contained in the register iV pile . 
     Lastly, as already described in section III, the prologue PF 3  also contains an instruction line coding the instruction “Load IV isbxx ” to load into the register iv branch  the value that will be used to decrypt the instructions I j  of the following basic block, i.e., here, the basic block  220  of the function F 3 . 
     The block  212  is the basic block of the function F 2  that is executed just after the execution of the function F 3 . Since the execution of the basic block is triggered following the execution of an indirect branch, the block  212  is here a basic block of the second type. 
     The first basic block  220  of the function F 3  is a basic block of the first type. 
     The function F 3  ends with a basic block  222  of the first type that contains a first portion of the epilogue EF 3 . This first portion EF 3  ends with an instruction line that codes an instruction “BranchIV ra”. When the instruction “BranchIV ra” is executed by the microprocessor  2 , this causes a jump to the second line of the basic block  212 . This instruction is preceded by an instruction line containing the instruction “Load IV ra”. These instructions have already been explained in section III. 
     The epilogue EF 3  also contains a second portion that starts at the first instruction line of the block  212 . This second portion of the epilogue EF 3  contains in succession:
         an instruction line coding an instruction “Load IV iv pile , @ j+1 ”, then   an instruction line coding an instruction “Load ra, @ j ”.       

     The execution of the instruction “LoadIV iv pile , @ j+1 ” by the microprocessor  2  causes the decryption of the datum contained in the data line located at the address @ j+1 , and said datum to be loaded into the register iv pile . As explained above, during the execution of the prologue PF 3 , it is the cryptogram of the value iv a  encrypted using the value iv b  that is saved in this line. Thus, the execution of the instruction “LoadIV iv pile , @ j+1 ” causes the value iv b  contained in the register iv pile  to be replaced with the value iv a  saved in the stack  46 . 
     The execution of the instruction “Load ra, @ j ” causes the datum contained in the data line located at the address @ j  to be decrypted, and said datum to be loaded into the register ra. As explained above, during the execution of the prologue PF 3 , it is the cryptogram of the address @ra 2  encrypted using the value iv a  that is saved in this line. Thus, the execution of the instruction “Load ra, @ j ” causes the datum contained in this line to be decrypted and said datum to be loaded into the register ra. 
     The operation of the method for securing the stack  46  against buffer overflow attacks will now be described in more detail with reference to  FIGS. 11 and 12  in the particular case of the functions F 1 , F 2  and F 3  described above. The instructions of the functions F 1 , F 2  and F 3  are executed in accordance with the description given in section III. It is also assumed that the function F 1  is the main function, also known as the “main”, of the machine code  32 . 
     In a step  230 , during the execution of the function F 1 , the block  202  is executed in order to call the function F 2 . During the execution of the block  202 , the prologue of the call to the function F 2  is executed. The execution of this prologue causes the address @ra 2  to be loaded into the register ra of the microprocessor  2 . It also causes at least one portion of the execution context of the function F 1  to be saved in the stack  46 . Next, the instruction “Branch @F 2 ” is executed, this causing a jump to the first instruction line of the function F 2  located at the address @ 208 . 
     In a step  232 , the function F 2  executes. During its execution, the function F 2  saves in the stack  46  data DF 2  ( FIG. 12 ) such as, for example, local variables. Each time a datum is saved in the stack  46 , the method of section IV is implemented. During the execution of the function F 2 , the register iv pile  contains the value iv a . 
     In a step  234 , during the execution of the function F 2 , the block  210  is executed. The prologue PF 3  of the call to the function F 3  is then executed by the microprocessor  2 . 
     In step  234 , the operations conventionally executed during the execution of a prologue of a call to a function are carried out. Since these operations are conventional, they are not described here. It will simply be recalled that the execution of these operations causes various data of the execution context of the function F 2  to be saved in the stack  46 . These data for example comprise the value of a pointer sp that points to the top of the stack  46  and other information necessary to correctly restart the execution of the function F 2  after the execution of the function F 3 . In addition, the execution of the prologue PF 3  leads the instruction lines shown in  FIG. 10  to be executed one after the other. The execution of these instruction lines by the microprocessor  2  causes, in order:
         the address @ra 2  to be saved to the top of the stack  46 , then   the current value iv a  of the register iv pile  to be saved in the register iv temp , then   the new value iv b  to be loaded into the register iv pile , then   the value iv a  contained in the register iv temp  to be saved in the stack  46 , then   a new value to be loaded into the register iv lsbi  allowing the instruction lines LI j  of the block  220  to be decrypted, then   the first instruction line of the block  220  to be executed.       

     The address @ra 2  is saved in the stack  46  like all the other data saved in the stack, i.e. by implementing the method of section IV. The address @ra 2  is saved in the stack  46  at a moment at which the value contained in the register iv pile  is equal to the value iv a . Therefore, it is only a cryptogram @ra 2 * obtained by encrypting the address @ra 2  using the value iv a  that is stored in the stack  46 . In  FIG. 12 , this cryptogram is denoted “@ra 2 *”. Similarly, the value iv a  is saved in the stack  46  by implementing the method of section IV. At the moment at which the value iv a  is saved, the register iv pile  contains the value iv b . Thus, the cryptogram iv a * of the value iv a  saved in the stack  46  is obtained by encrypting the value iv a  using the value iv b . 
     In a step  236 , after the execution of the prologue PF 3 , the function F 3  is executed. During its execution, the function F 3  stores data DF 3  in the stack  46  by implementing the method of section IV. Here, the function F 3  is a leaf function, i.e. a function that calls no other functions during its execution. Under these conditions, the content of the register iv pile  is left unchanged between the execution of the prologue PF 3  and the execution of the epilogue EF 3 . Thus, each datum saved in the stack  46  by the function F 3  is encrypted using the value iv b , which is different from the value iv a . 
     In a step  238 , when the execution of the function F 3  ends, the epilogue EF 3  is executed. The execution of the epilogue EF 3  causes, in addition to the execution of the conventional operations of an epilogue:
         1) The cryptogram iv lsbxx * contained in the first data line of the block  212  to be decrypted and the decrypted value to be loaded into the register iv lsbi  (execution of the instruction “LoadIV ra”), then   2) The first instruction line of the block  212  to be jumped to (execution of the instruction “Branch IV ra”), then   3) The value iv b  contained in the register iv pile  to be replaced with the value iv a  (execution of the instruction “Load IV iv pile , @ j+1 ”), then   4) The address @ra 2  to be loaded from the stack  46  into the register ra (execution of the operation “Load ra, @ j ”).       

     Operations 1) and 2) above have already been described in detail in section III. 
     In operation 3) above, the cryptogram iv a * is read from the stack  46  then decrypted using the value contained in the register iv pile , i.e. using the value iv b . 
     During operation 4) above, the cryptogram @ra 2 * is read from the stack  46  and decrypted using the current value contained in the register iv pile , i.e., at this stage, using the value iv a . 
     Next, in an operation  240 , the execution of the function F 2  continues using the value iv a  contained in the register iv pile  to decrypt and encrypt the data DF 2  saved in the stack  46 . 
     In a step  242 , when the execution of the function F 2  has ended, the execution of the function F 1  restarts. To this end, the branch to the address @ra 2  contained in the register ra is executed. Here the switch from the execution of the function F 1  to the function F 2 , then the return from the execution of the function F 2  to the function F 1  are implemented as described in detail in the case of the functions F 2  and F 3 . 
     If a buffer overflow attack is carried out, forcing the function F 3  to store a datum that exceeds the size of the space allocated to save the data DF 3 , then the cryptogram @ra 2 * may be replaced by another cryptogram denoted @rat*. Since the replacement of the cryptogram @ra 2 * by the cryptogram @rat* occurs during the execution of the function F 3 , the cryptogram @rat* is the result of the encryption of an address @rat using the value iv b  currently contained in the register iv piie . 
     During the execution of the epilogue EF 3 , the cryptogram @rat* is decrypted using the value iv a  and not using the value iv b . Thus, the decrypted return address is different from the address @rat. The attacker can therefore not choose the address to which the control flow is diverted. 
     Lastly, in this embodiment, which also implements what was described in section IV, the attacker does not know the keys ka and k′. He cannot therefore correctly construct a code MAC j  and the cryptogram CD j * corresponding to the address @rat. Thus, if the data line containing the cryptogram @ra 2 * is replaced by a data line containing the cryptogram @rat*, such a replacement is detected during the verification operations  270  and  276 . Thus, an execution error is detected before the execution of the block  214 . 
     SECTION VI: SECURING THE DATA 
     The binary code  30 , in addition to the machine code  32 , may contain data to be processed during the execution of the machine code  32 . In addition, during the execution of the machine code  32 , the latter may generate data. These data are typically contained in portion  44  of the memory  4 . 
     What was described in section IV with respect to securing the data saved in the stack  46  is, preferably, also implemented to secure the data stored in portion  44 . In particular, each datum stored in portion  44  is coded in a line LD j  the structure of which is identical to the case of the stack  46 . Thus, a datum is written to and read from the portion  44  as described in section IV, except that the term “stack  46 ” must be replaced with the term “portion  44 ”. 
     SECTION VII: GENERATION OF THE BINARY CODE 
       FIG. 13  shows a compiler  300  able to automatically generate the binary code  30  from a source code  302 . To this end, the compiler  300  typically comprises a programmable microprocessor  304  and a memory  306 . The memory  306  contains the instructions and data required to, when they are executed by the microprocessor  304 , automatically generate the binary code  30  from the source code  302 . In particular, during the compilation of the source code  302 , the microprocessor  304  automatically generates the appropriate initialization vectors iv k  and the lines of code LI j  and LD j . During this compilation, the compiler  300  also automatically inserts, into the machine code, the instructions described above, in order to implement the methods of  FIGS. 7, 9 and 11 . It is within the ability of those skilled in the art to design and produce such a compiler given the explanations given in this description. For example, the compiler  30  automatically notes and identifies branch instructions and, depending on the identified branch instruction, automatically inserts, before and/or afterwards, the instructions required to implement the methods described here. 
     SECTION VIII: VARIANTS 
     Variants of the Device  1 : 
     The memory  4  may also be a nonvolatile memory. In this case, it is not necessary to copy the binary code  32  to this memory before launching its execution since it is already found therein. 
     As a variant, the memory  4  may also be an internal memory integrated into the microprocessor  2 . In the latter case, it is produced on the same substrate as the other elements of the microprocessor  2 . Lastly, in other configurations, the memory  4  is composed of a plurality of memories, certain of which are internal memories and others of which are external memories. 
     The main memory  4  may comprise a first volatile memory of large capacity and a second volatile memory of smaller capacity but in which read and write operations may be carried out more rapidly. The second memory is what is known as a cache memory. The cache memory may be a memory external to the microprocessor  2  or a memory internal to the microprocessor  2 . In certain embodiments, a plurality of cache memories of different levels may be used. 
     Many different hardware architectures may be used to produce the module  28 . In particular, the module  28  may be composed of a combination of a plurality of hardware blocks of the microprocessor  2  performing respective functions and each located in a different area of the chip of the microprocessor  2 . 
     In another embodiment, the module  28  is replaced by a software module that, when it is executed by the unit  10 , performs the same functions and operations as those described with respect to the module  28 . 
     Variants of the Way in which the Machine Code is Secured: 
     As a variant, only the structure of the second type, i.e. the structure described with reference to  FIG. 5 , is used for all the basic blocks of the machine code  32 . In this case, what was described above in the particular case of indirect branches also applies to the direct branches. 
     Other embodiments of the content of the first line of a block BB k  of the second type are possible. For example, this content is not necessarily encrypted. In another variant, this content is encrypted using a key other than the address @ k  of the first line. For example, the content of the first line is only encrypted with the key ka. The content of the first line of may also contain, instead of the cryptogram iv lsbi *, a cryptogram @ lsbi * of an address @ lsbi . In this case, when the instruction “Load IV ra” or “LoadIV rd” is executed, it causes the cryptogram @ lsbi*  to be read and decrypted in order to obtain the address @ lsbi . Next, the content from which the 32 least significant bits of the vector iv k  are constructed is read at the address @ lsbi . 
     To construct the vector iv k  from the address @ k , other embodiments are possible. For example, a lookup table is loaded into the memory  29  before or at the start of the execution of the code  32 . In this table, the content that allows the 32 least significant bits of the vector iv k  to be constructed is associated with each address @ k  of a block BB k  of the second type. For example, this content is identical to that described in the case where it is stored in the first line of the basic block of the second type. The operation of this embodiment is identical to that described above except that the instruction “LoadIV ra” or “LoadIV rd” causes, when it is executed by the microprocessor  2 , the content of the register iv lsbi , to be read from the lookup table and not from the first line of the basic block BB k . In this case, the basic blocks of the second type are replaced by basic blocks of the first type and the instruction “BranchIV rd” or “BranchIV ra” is modified to cause a jump to the first line of the following basic block and not to the second line of this basic block. 
     It is also not necessary to construct the vector iv k  using the contents of the registers iv msbi  and iv ctei . For example, as a variant, the contents of the registers iv msbi  and iv ctei  are constructed from the content of the register iv lsbi . For example, the vector iv k  coded on 128 bits is obtained by concatenating the 32 bits of the register iv lsbi  four times with themselves. In this case, the registers iv msbi  and iv ctei  may be omitted. 
     As a variant, certain functions or portions of the binary code  30  are insecure. To manage the execution of such a binary code, which comprises both a secure function and insecure functions, the instruction set of the microprocessor  2  may be completed by:
         an instruction to activate a secure operating mode of the microprocessor  2 , and   an instruction to deactivate this secure mode.       

     In this case, the instruction to activate the secure mode is located in the binary code  30  just before the call to the secure function and the instruction to deactivate the secure mode is located just after the end of the secure function. When the instruction to activate the secure mode is loaded by the microprocessor  2 , in response, the module  28  starts to process the following instructions and data of the binary code as described in the preceding sections. When the instruction to deactivate the secure mode is loaded by the microprocessor  2 , in response, the module  28  is deactivated. In the latter case, the following instructions and data of the binary code are not processed by the module  28  but loaded directly into the queue  22  or into the registers of the set  12 . 
     As a variant, an “update” instruction is added to the instruction set of the microprocessor. When this “update” instruction is executed by the microprocessor  2 , it causes the value currently contained in the register iv branch  to be loaded into the register iv lsbi . Thus, in this case, the use of a new initialization vector iv k  is triggered in a different manner than by execution of a branch instruction. In this case, the described method may also be implemented with implicit branch instructions. Specifically, the last instruction of a basic block that ends with an implicit branch instruction is then the “update” instruction. Instead of the “update” instruction being a separate instruction in the instruction set of the microprocessor, it is possible to add an additional bit to each instruction of the instruction set of the microprocessor  2  and to trigger the change of initialization vector iv k  solely when this additional bit takes a specific value. 
     The code ECC Ij  may be replaced by a simple error detection code only allowing an error to be detected in the instruction I J  with which it is concatenated. An error detection code does not allow the detected error to be corrected. In this case, the operation  186  of correcting the error is omitted. Thus, it soon as the module  28  detects an error in a decrypted instruction I j , for example, the execution of the secure function is systematically interrupted. 
     In a simpler variant, the code ECC Ij  is omitted. In this case, the cryptogram CI j * is merely the cryptogram of the instruction I j . In this embodiment, the microprocessor  2  is no longer capable of detecting modifications of the instruction I j  that occur between the time at which said instruction is stored in the queue  22  and the time at which it is executed by the unit  10 . 
     The code ECC Lj  may be replaced by a simple error detection code. In this case, the correcting operation  174  is omitted. 
     In another variant, the code ECC Lj  is constructed so as to only allow the detection of an error, either only in the cryptogram CI j * or only in the code MAC j . 
     The code ECC Lj  may be omitted. In this case, an error in the cryptogram CI j * or in the code MAC j  can be detected only during the execution of the operation  176  for verifying the integrity and authenticity of the cryptogram. It is generally more complex to detect an error with a MAC code than with a simple error detection code or a simple error correction code. In addition, when the code ECC Lj  is omitted, in the case where there is an error in the cryptogram CI j * or the code MAC j , it is not possible to correct this error. In the latter case, for example, the execution of the secure function is therefore systematically interrupted in case of error. 
     In another embodiment, it is the code MAC j  that is omitted. The operation  176  is then also omitted. 
     Variants of the Way in which the Data are Secured: 
     The structure of the lines LD j  used to secure the data saved in the memory  4  may be modified. In particular, the various variants of the structure of a line LI j  described above are applicable to the structure of the lines LD j . When the structure of the line LD j  is modified, the method of  FIG. 9  must be correspondingly modified to take into account these modifications. For example, if the code ECC Dj  is replaced by a simple error detection code, then the error-correcting operation  286  is omitted. Thus, as soon as the module  28  detects an error in a decrypted datum D j , for example, the execution of the secure function is systematically interrupted. 
     As a variant, the function F iv  is identical to the function f ka  except that it is applied to the address @ j . The function F iv  may also use the same encryption algorithm as the function f ka , but with an encryption key different from the key ka. 
     In a simpler variant, the function F iv  is the identity function. In this case, the contents of the registers iv lsbd  and iv lsbp  are systematically equal to the address @ j . 
     In other embodiments, to detect a movement of a line LD j , the code MAC j  is computed depending on the vector iv p . For example, in the case of a data line LD j  saved in the stack  46 , the code MAC j  is computed from the concatenation of the cryptogram CD j * and of the vector iv p . The code MAC j  may also be computed from a combination of the cryptogram CD j * and of the vector iv p , i.e. a combination such as the following one: CD j * XOR iv p . In the case where the code MAC j  depends on the vector iv p , then it may be used instead of the code ECC Dj  to detect an error in case of movement of the line LD j  in the stack  46 . Specifically, in this case, during the verification of the integrity and of the authenticity of the cryptogram CD j *, the module  28 :
         obtains the vector iv p  from the content of the registers iv pile , iv ctep  and iv lsbp , then   combines the cryptogram CD j * with the obtained vector iv p , then   verifies the integrity and authenticity of this combination using the code MAC j  contained in the same line LD j .
 
If this line LD j  has been moved, the obtained vector iv p  is different from that expected. As a result, the integrity of the combination of the cryptogram CD j * and of the vector iv p  cannot be verified, this triggering the signalling of an execution fault. It will be noted that, in this embodiment, it is possible to detect a movement of the line LD j  without even having to decrypt the cryptogram CD j *. In this variant, to detect a movement of the line LD j , the code ECC Dj  may be omitted.
       

     Similarly to what was described above with respect to the code MAC j , the code ECC Lj  may also be constructed so as to depend on the vector iv p . In this case, the movement of the line LD j  is detected during the verifications of the code ECC Lj . As a result, to detect a movement of the line LD j , the code ECC Dj  may be omitted. 
     In the embodiments described up to now, both the datum D j  and the code ECC Dj  are coded depending on the vector iv p  since the cryptogram CD j * is encrypted using this vector iv p . As a variant, either only the datum D j  or only the code ECC Dj  is coded depending on the vector iv p . For example, in the data line, the cryptogram of the datum D j  is obtained using an encryption function that does not use the vector iv p , whereas the cryptogram ECC Dj * of the code ECC Dj  is obtained using the encryption function f ka (ECC Dj ; iv p ). In this case, in the operation  278 , the module  28  decrypts the cryptogram of the datum D j  without using the vector iv p  and decrypts the cryptogram ECC Dj * using this vector iv p . Next, the rest of the method is identical to what was described above. In one simpler embodiment, since there is no need to code the datum D j  depending on the vector iv p , it is also possible to not encrypt it. For example, the line of code then contains the datum D j  in plaintext and the cryptogram ECC Dj *. As a result, in the operation  278 , the decryption of the datum D j  is omitted since it is enough to extract it from the bit range in which it is contained in the line LD j . 
     Conversely, it is also possible to modify the structure of the lines LD j  so that only the datum D j  is coded depending on the vector iv p . For example, the line LD j  contains a cryptogram D j * of the datum D j  obtained by encrypting it using the function f ka (D j ; iv p ) and a cryptogram ECC Dj * obtained by encrypting the code ECC Dj  using an encryption function independent of the vector iv p . In operation  270 , the module  28  decrypts the cryptogram D j * using the vector iv p  and decrypts the cryptogram ECC Dj * without using this vector iv p . 
     Up to now, it has been an encryption function that has been described by way of an example of an embodiment allowing the datum D j  or the code ECC Dj  to be coded depending on the vector iv p . This encryption function may however be none other than a simple “Exclusive OR” logic operation that compares the datum D j  and the vector iv p  or the code ECC Dj  and the vector iv p . 
     All the variants described in the particular case of securing data saved in the stack  46  apply to the case of securing data saved elsewhere in the memory  4 . In particular, these variants apply to the data line LD k  of the basic blocks of the second type. 
     Variants of the Way in which the Call Stack is Secured: 
     The way in which the stack  46  is secured was described for the particular case in which the return address @ra 2  is saved in the stack only at the moment at which the function F 2  calls the function F 3 . However, what was described also applies to situations in which the return address @ra 2  is saved in the stack  46  at the moment at which the function F 2  is called by the function F 1 . In this case, what was described above may be applied unchanged, except that it is the prologue and epilogue of the function F 2  that are modified. 
     The new value iv b  contained in the register iv pile  may be generated in many different ways. For example, the new value iv b  is equal to the value iv a  to which a preset increment has been added. In this case, the initial value contained in the register iv pile  is for example a predefined value loaded on start-up of the microprocessor  2 . 
     There are other possible ways of encrypting the address @ra 2  using an initialization vector different from that used to encrypt the data DF 3 . For example, as a variant, the prologue PF 3  is modified to perform in order the following operations when it is executed by the microprocessor  2 : 
     1) The value iv a  contained in the register iv pile  is saved in a register iv temp1 .
 
2) The value iv a  contained in the register iv pile  is replaced by a new value iv b  generated, for example, randomly as described above.
 
3) The address @ra 2  contained in the register ra is saved in the stack  46 . The cryptogram @ra 2 * stored in the stack  46  is therefore the result of the encryption of the address @ra 2  using the value iv b  currently contained in the register iv pile .
 
4) The value iv b  contained in the register iv pile  is saved in a register iv temp2 .
 
5) The value iv b  contained in the register iv pile  is replaced by the value iv a  contained in the register iv temp1 .
 
6) The value iv b  contained in the register iv temp2  is saved in the stack  46 . The cryptogram iv b * stored in the stack  46  is therefore the result of the encryption of the value iv b  using the value iv a  currently contained in the register iv pile .
 
     Next, during the execution of the function F 3 , each time data are saved in the stack  46 , said data are encrypted using the value iv a  contained in the register iv pile . This embodiment therefore indeed allows the address @ra 2  to be encrypted using an initialization vector different from that used to encrypt the data saved in the stack  46  during the execution of the function F 3 . The operation of this embodiment may be deduced from the explanations given with reference to  FIGS. 10 to 12 . 
     Other embodiments of the prologue PF 3  and of the epilogue EF 3  are possible. For example, if additional temporary registers are used, the order of the operations may be modified. Thus, for example, the cryptogram iv a * may be saved in the stack  46  before the cryptogram @ra 2 *. To do this, for example, it is necessary in succession to: 
     1) save the value iv a  in a temporary register iv temp3 ,
 
2) generate and save the value iv b  in the register iv pile ,
 
3) save the content of the register iv temp3  in the stack  46 ,
 
4) save the value iv b  in a register iv temp4 ,
 
5) restore the value iv a  to the register iv pile  on the basis of the content of the register iv temp3 ,
 
6) save the content of the register ra in the stack  46 ,
 
7) restore the value iv b  to the register iv pile  on the basis of the content of the register iv temp4 .
 
     As a variant, only the return address is encrypted before being saved in the stack  46 . The other data saved in the stack  46  are not encrypted or are encrypted using another key. For example, each return address saved in the stack  46  is encrypted, by the module  28 , with the key ka whereas the other data saved in the stack  46  are not encrypted. In this case, if a datum stored in the stack  46  causes a buffer overflow that replaces the cryptogram @ra 2 * with a cryptogram @rat*, then, after the execution of the functions F 3  and F 2 , the execution of the code continues with the execution of the instruction located at the address f ka   −1 (@rat*). However, the attacker does not know the key ka and can not therefore determine the address corresponding to f ka   −1 (@rat*). He cannot therefore predict to which address the execution of the code  30  will be diverted. This therefore also makes buffer overflow attacks more difficult. 
     In one much simpler embodiment, the data DF 3  saved in the stack  46  are not encrypted. In this case, the value iv a  and the data DF 3  saved in the stack  46  are not encrypted. However, even in this simplified case, the fact that the address @ra 2  saved in the stack  46  is encrypted in a different way to the data DF 3  makes buffer overflow attacks more difficult. 
     Variants Common to the Various Preceding Sections 
     From the moment that a line of code contains at least one of the elements of the group composed of a message authentication code, an error correction code and an error detection code, it is possible to detect a modification of the content of this line. Thus, to detect a modification of the content of an instruction line or a data line, only a single one of the elements of this group is necessary. 
     In one very simple embodiment, no error detection or correction codes and no codes MAC j  such as described above are employed. In this case, an error in the decryption of a datum or of an instruction may lead to the unit  10  being unable to execute an instruction and therefore to the abrupt stoppage of the execution of the machine code  30 . 
     The encryption and decryption were described in the particular case where the functions f ka  and f ka   −1  are encryption algorithms that use an “initialization vector” and, preferably, also a secret key ka. However, the functions f ka  and f ka   −1  may also be encryption/decryption algorithms in which an initialization vector is not necessary. However, if the term “initialization vector” is simply replaced by the term “key” everything that has been described here also applies to such an encryption/decryption algorithm. 
     The function used to generate the cryptogram CD j * may be different from that used to generate the cryptogram CI j *. For example, these two functions differ in that they use different encryption keys. 
     In another variant, the keys ka and k′ are the same. 
     The key ka may be stored beforehand in the memory  29 . In this case, the cryptogram ka* may be omitted from the block  34 . 
     The cryptogram k′* of the key k′ encrypted with the public key pk CPU  may be stored in the block  34 . In this case, there is no need for the key k′ to be stored beforehand in the memory  29 . 
     A line of code may be longer than one machine word. In this case, each line of code is composed of a plurality of machine words that are generally located at immediately consecutive memory addresses in the memory  4 . In this case, a line of code is loaded into the microprocessor  2  not in a single read operation, but by executing a plurality of read operations. Each read operation loads into the microprocessor a respective machine word of the line of code. 
     As a variant, the operation  176  or  276  are systematically followed by the operation  178  or  278  even if the integrity or authenticity of the cryptogram was not able to be confirmed. In this case, the operation  176  or  276  serves to trigger the signalling of an execution fault without interrupting the execution of the binary code. 
     Depending on the instruction set used by the microprocessor  2 , the described instructions, such as “LoadIV”, “BranchIV” and “StoreIV”, each correspond to a single instruction of this set or, in contrast, to a group of a plurality of instructions of this set. 
     Everything that was described in section III may be implemented independently of what was described in the other sections. For example, steps  198  and  250  may be omitted and the method of  FIG. 11  not implemented. 
     Everything that was described in section IV may be implemented independently of what was described in the other sections. For example, what was described in section IV may be implemented:
         in the context of a machine code devoid of indirect branch instruction and of instruction “LoadIV ra”,   without implementing the teaching of section III to secure the instructions of the machine code,   without implementing the teaching of section V to secure the stack  46  against buffer overflow attacks.       

     Everything that was described in section V may also be implemented independently of what was described in the other sections. For example, what was described in section V may be implemented:
         in the context of a machine code devoid of indirect branch instruction and of instruction “LoadIV ra”,   without implementing the teaching of section III to secure the instructions of the machine code,   without implementing the teaching of section VI to secure the data stored in portion  44  of the memory  4 .       

     All the embodiments described in this text and, in particular, the various variants, may be combined together. 
     SECTION IX: ADVANTAGES OF THE DESCRIBED EMBODIMENTS 
     Advantages in Securing the Machine Code: 
     Since the loading of the vector iv lsci  required to decrypt the instruction lines of the basic block BB k  is triggered during the execution of the basic block BB k-1 , the integrity of the control flow is ensured. Specifically, if following execution of the basic block BB k-1 , it is a basic block BB t  that is executed instead of the basic block BB k , then the instruction lines of the basic block BB t  are decrypted using the loaded vector iv k . The instruction lines of the basic block BB t  are therefore not decrypted using the vector iv t  used to encrypt these instruction lines of the basic block BB t . Thus, the decryption of the instruction lines of the block BB t  is incorrect, this being detected. It is therefore difficult to divert the flow of execution of the block BB k  to the block BB t . 
     The indirect load instruction does not directly contain the value of the vector iv k  but solely the identifier of a register intended to contain the address @ k  of the block BB k . Thus, the basic block BB k-1  only contains instructions that allow, at the moment of the execution of this basic block BB k-1 , this vector iv k  to be constructed from the content of the identified register. As a result, the basic block BB k-1  may be compiled independently of the following basic block BB k . By virtue of this, the use of an indirect branch at the end of a basic block is made possible while preserving the ability to control and guarantee the integrity of the control flow. 
     Recording the content to be loaded in the register iv lsbi  in the first line of the basic block of the second type allows this content to be easily loaded into the microprocessor. In addition, the insertion of such a first data line during the generation of the machine code is simple. 
     The fact that the content to be loaded in the register iv lsbi  is stored in the memory  4  in encrypted form, increases security. 
     The fact that the cryptogram iv isbi * is decrypted using the address @ j  makes the permutation, in the memory  4 , of two blocks of the second type difficult and detectable. 
     The encryption of the instructions I j  makes it possible to guarantee the confidentiality of the binary code  30 , this making reverse engineering of the binary code very difficult. The verification of the integrity of the cryptogram CI j * or CD j * allows modifications of the binary code caused, for example, by attacks such as the injection of faults into the memory  4  to be detected. Verifying the authenticity of the instructions and of the data makes it possible to detect and make very difficult the addition of additional instructions to the binary code  30  by an attacker who, for example, would like to insert therein malicious software such as viruses. Specifically, even if the attacker knows the algorithm used to encrypt the instructions I j  or the data D j , he will not know the secret key k′ used to construct the code MAC j . 
     The verification, using the code ECC Ij  or ECC Dj , of the existence of an error in the instruction I j  or the datum D j  just before it is used allows a modification of this instruction or of this datum D j  to be detected. Such modifications may be caused by fault injection. Thus, the use of the code ECC Ij  or ECC Dj  allows this type of attack to be detected. 
     The fact that the code ECC Ij  or ECC Dj  is an error correction code and not merely an error detection code allows the executing method to be made more robust with respect to fault-injection attacks. Specifically, in this case, the error correction code often allows the error introduced into the instruction I j  or into the datum D j  to be corrected so that despite the presence of such errors, the secure function continues to execute correctly. 
     The use of the code ECC Lj  allows an error in the cryptogram CI j * or CD j * or in the code MAC j  to be detected more rapidly than if only the code MAC j  were used for this purpose. The use of the code ECC Lj  therefore allows the execution of the binary code to be accelerated. 
     The use of an error correction code for the code ECC Lj  allows the claimed method to be made more robust with respect to fault-injection attacks that inject faults into the memory  4  or into the medium  6 . Specifically, in this case, the error correction code often allows the cryptogram CI j * or CD j * or the code MAC j  to be corrected so that, despite the presence of such errors, the secure function executes correctly. 
     Advantages of Securing Against Buffer Overflow Attacks: 
     The fact of encrypting the address @ra 2  of the calling function F 2  with a value iv a  different from the value iv b  used when saving the data DF 3  of the called function F 3  makes it possible to make buffer overflow attacks more difficult. 
     Encrypting the data stored in the stack  46  increases the security of the method. 
     Encrypting the data saved in the stack depending on a value that depends in addition on the address at which the datum is saved in the stack makes it possible to permit random access to the data encrypted and saved in the stack  46 , while making it difficult to permute two data lines stored in this call stack. 
     The use of an error detection code associated with each datum saved in the call stack makes it possible to detect whether the decryption of a datum has taken place correctly before this datum is exploited and processed during the execution of the machine code  30 . 
     The decryption and encryption of the address @ra 2  in addition to use of the key ka known only to and stored in the module  28  makes it possible to make the implementation of a buffer overflow attack even more difficult. 
     Making the code ECC Dj  an error correction code in addition allows a detected error to be corrected. This therefore allows the execution of the secure function to be continued even if an error was signalled.