Patent Publication Number: US-7915995-B2

Title: Compensation of field effect on polycrystalline resistors

Description:
PRIORITY CLAIM 
     The present application is a divisional of U.S. patent application Ser. No. 11/864,480 filed on Sep. 28, 2007, now U.S. Pat. No. 7,616,089, which is entitled, “Compensation Of Field Effect On Polycrystalline Resistors,” the contents of which is incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates in general to electrical circuitry, and more particularly, to the compensation of field effect on polycrystalline resistors. 
     2. Description of the Related Art 
     It is well known in the art of analog integrated circuitry that the resistance of polycrystalline silicon (also referred to as polysilicon, poly-Si or simply poly) varies with the applied voltage in a non-linear fashion in the presence of an electric field. This non-linearity is caused by an accumulation of carriers (and thus reduced resistance) in the presence of a positive electric field, or conversely, by a depletion of carriers (and thus increased resistance) in the presence of a negative electric field. Additional information regarding the non-linearity of polycrystalline silicon resistors can be found, for example, in Sze, S. M., Physics of Semiconductor Devices, 2 nd  Ed., pp. 362-366. 
     Because such non-linearity is undesirable in many applications, some conventional analog integrated circuits include features intended to reduce the non-linearity of polycrystalline resistors.  FIG. 1A  is a section view of a first prior art analog integrated circuit  100  that partially compensates for the non-linearity of a polycrystalline resistor. As shown, analog integrated circuit  100  includes a substrate well  102  coupled to ground, a polycrystalline resistor  106  over substrate well  102 , and a metallization layer  110  over polycrystalline resistor  106  that is coupled to Vdd. A first oxide layer  104  is interposed between substrate well  102  and polycrystalline resistor  106 , and a second oxide layer  108  is interposed between polycrystalline resistor  106  and metallization layer  110 . As is well known to those skilled in the art, oxide layers  104 ,  108  are dielectric layers that electrically isolate polycrystalline resistor  106  from metallization layer  110  and substrate well  102 . 
     Because metallization layer  110  and substrate well  102  are coupled to different potentials and accordingly have an electric field there between, the non-linearity of polycrystalline resistor  106  is reduced by partial cancellation of the field effect on polycrystalline resistor  106 . However, in practice, cancellation of the field effect in analog integrated circuit  100  is only partially successful because of asymmetry in the signal between Vdd and ground and differences in the thicknesses of oxide layers  104 ,  108  militated by other aspects of the design. In addition, circuit layout considerations often make it difficult to overlay each polycrystalline resistor  106  with a metallization layer  110 . 
       FIG. 1B  is a top plan view of a second prior art analog integrated circuit  120  that substantially cancels the field effect on a polycrystalline resistor by employing a “bootstrapped” resistor design. Analog integrated circuit  120  includes one or more series-connected polycrystalline segments  122   a - 122   c , which are each connected in parallel with a respective one of underlying well resistor(s)  124   a - 124   c . Well resistors  124   a - 124   c  are characterized by a well width W and a well-to-well distance D. 
     Although the bootstrapped resistor design employed in the embodiment of  FIG. 1B  can be effective in avoiding non-linear variations in resistivity to a first order approximation, both the well width W and well-to-well distance D are typically large, meaning that the use of bootstrapped resistors is inefficient in terms of die area (and therefore cost). Additional die area and power may also be consumed by a buffer required to drive the well resistors. 
     SUMMARY OF THE INVENTION 
     The present invention provides improved apparatus, systems and methods. According to one embodiment, a resistive circuit includes a first terminal and a second terminal and polycrystalline first and second resistive segments coupled between the first and second terminals. A third terminal A is coupled to the first resistive segment, and a third terminal B is coupled to the second resistive segment. The third terminal A has a first voltage with respect to the first terminal, and the third terminal B has a second voltage with respect to the second terminal. With this arrangement, the non-linearity of resistance of the first resistive segment at least partially compensates for non-linearity of resistance of the second resistive segment. 
     All objects, features, and advantages of the present invention will become apparent in the following detailed written description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The novel features believed characteristic of the invention are set forth in the appended claims. However, the invention, as well as a preferred mode of use, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings in which like and corresponding reference numerals identify like and corresponding reference numerals, wherein: 
         FIG. 1A  is a section view of a first resistor circuit in accordance with the prior art; 
         FIG. 1B  is a top plan view of a second resistor circuit in accordance with the prior art; 
         FIG. 2  depicts an isometric view of an idealized polycrystalline resistor circuit; 
         FIG. 3A  illustrates a first embodiment of a resistive circuit in accordance with the present invention; 
         FIG. 3B  depicts a second embodiment of a resistive circuit in accordance with the present invention; 
         FIG. 3C  illustrates a third embodiment of a resistive circuit in accordance with the present invention; 
         FIG. 3D  illustrates a fourth embodiment of a resistive circuit in accordance with the present invention; 
         FIG. 3E  depicts a fifth embodiment of a resistive circuit in accordance with the present invention; 
         FIG. 3F  illustrates a sixth embodiment of a resistive circuit in accordance with the present invention; 
         FIG. 3G  depicts a seventh embodiment of a resistive circuit in accordance with the present invention; 
         FIG. 3H  illustrates an eighth embodiment of a resistive circuit in accordance with the present invention; 
         FIG. 3I  illustrates a ninth embodiment of a resistive circuit in accordance with the present invention; 
         FIG. 4  depicts a voltage divider circuit in which resistive circuits in accordance with the present invention may be utilized; 
         FIG. 5A  illustrates a current-to-voltage converter in which a resistive circuit in accordance with the present invention may be utilized; 
         FIG. 5B  depicts an inverting gain amplifier circuit in which a resistive circuit in accordance with the present invention may be utilized; 
         FIG. 5C  illustrates a non-inverting gain amplifier circuit in which a resistive circuit in accordance with the present invention may be utilized; 
         FIG. 5D  depicts a difference amplifier circuit in which a resistive circuit in accordance with the present invention may be utilized; 
         FIG. 5E  illustrates an inverting gain amplifier circuit in which a resistive segments of differing lengths are utilized; and 
         FIG. 5F  depicts a difference amplifier circuit in which multiple techniques for compensating for the field effect on polycrystalline resistors are employed. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENT 
     With reference now to  FIG. 2 , there is depicted an isometric view of an idealized integrated circuit resistor  200 . As shown, integrated circuit resistor  200  includes a substrate well  202  coupled to ground, an isolation layer  204  overlying substrate well  202 , and a polycrystalline silicon segment  206  overlying isolation layer  204 . Polycrystalline silicon segment  206 , which is a rectangular prism characterized by a length L, height H, and width W, is coupled between first voltage terminal having voltage V 1  and a second voltage terminal having voltage V 2 , where voltage V 1  is a reference voltage such as ground and voltage V 2 &gt;voltage V 1 . It will be appreciated that in practice, length L of polycrystalline silicon segment  206  is not merely the minimum linear distance between the two voltage terminals, but is instead the total length through the polycrystalline silicon that current flows between the voltage terminals. 
     The potential difference between polycrystalline silicon segment  206  and substrate well  202  generates an electric field  210  that varies in magnitude along length L of polycrystalline silicon segment  206 . Because the resistivity of polycrystalline silicon segment  206  varies with the electric field magnitude, the resistivity at any given point x along length L of polycrystalline silicon segment  206  can be expressed as a function of the magnitude of the electric field Ē as follows:
 
ρ( x )= f ( Ē ).
 
Given the high doping concentrations that are typical of semiconductor fabrication (e.g., 10 20 /cm 3 ), f(Ē) can be expressed via Taylor series expansion as follows:
 
ρ( x )= f ( Ē )=ρ o (1+   B ·Ē ( x )+Σ),
 
where ρ o  is the bulk resistivity of the polycrystalline silicon,  B  is a fabrication process-dependent constant, and Σ represents the high order Taylor series expansion terms that can be neglected given the assumption of a high doping concentration. If the high order terms are neglected, the expression for resistivity can be simplified as follows:
 
ρ( x )≈ρ o (1 +  B ·Ē ( x )).
 
     Utilizing this approximation, the resistance R of polycrystalline silicon segment  206  can be computed by integrating the resistivity of each differential unit of polycrystalline silicon segment  206  over its length L as follows: 
             R   =         ∫   o   L     ⁢         ρ   ⁡     (   x   )         H   ·   W       ⁢           ⁢     ⅆ   x         =       ∫   o   L     ⁢           ρ   o     ⁡     (     1   +       B   _     ·       E   _     ⁡     (   x   )           )         H   ·   W       ⁢       ⅆ   x     .                 
If it is assumed that the electric field Ē exhibits linear variation over the length of polycrystalline silicon resistor  206 , and can therefore be represented as:
 
 Ē ( x )= kxê 
 
where x represents position, k is a constant and ê is a vector representing electric field polarity, then the resistance R of polycrystalline silicon segment  206  can be restated as:
 
             R   =         ∫   o   L     ⁢           ρ   o     ⁡     (     1   +       B   _     ·   k   ·   x   ·     e   ^         )         H   ·   W       ⁢     ⅆ   x         =           ρ   o     ⁢   L     HW     +       ∫   o   L     ⁢           ρ   o     ⁢   L     HW     ⁢   kx   ⁢     B   _     ⁢     e   ^     ⁢       ⅆ   x     .                   
Solving the integral yields:
 
             R   =             ρ   o     ⁢   L     HW     +           ρ   o     ⁢   k     HW     ⁢       L   2     2     ⁢     B   _     ⁢     e   ^         =           ρ   o     ⁢   L     HW     +           L   2     ⁢     ρ   o         2   ⁢   HW       ⁢   k   ⁢     B   _     ⁢     e   ^                 
as the 1 st  order approximation of the resistance R of polycrystalline silicon segment  206 .
 
     Given the foregoing approximation of resistance R, it is apparent that variations in resistance R are primarily due to the polarity of the electric field. Consequently, the present invention appreciates that compensation for the field effect on a given polycrystalline resistor can be achieved by segmenting the polycrystalline resistor into multiple resistive segments and by applying electric fields of opposite polarities to the resistive segments. 
     Referring now to  FIG. 3A , there is illustrated a section view of a first embodiment of a resistive circuit  300  in accordance with the present invention. As depicted, resistive circuit  300  includes a first terminal  302   a  characterized by voltage V 1  and a second terminal  302   b  characterized by voltage V 2 , where voltage V 2 &gt;voltage V 1 . Coupled between terminals  302   a ,  302   b  are multiple (in this case, two) resistive segments  304   a ,  304   b  formed of polycrystalline silicon or other resistive material subject to non-linear behavior when subjected to an electric field. Resistive segments  304  are spaced apart from one another and electrically coupled to each other, in this case in series, by a conductor  306 , such as a metal. 
     Resistive circuit  300  further includes multiple third terminals  308   a ,  308   b  equal in number to the number of resistive segments  304 . Each third terminal  308  is coupled at one end to an end of a respective resistive segment  304 , in this case at one of first and second terminals  302   a ,  302   b . That is, third terminal  308   a  is coupled to an end of a resistive segment  304   a  at first terminal  302   a , and third terminal  308   b  is coupled to an end of a resistive segment  304   b  at second terminal  302   b . Third terminals  308  are separated from resistive segments  304  by an isolation region  310 . Substantially no DC current flows in third terminals  308 . 
     By virtue of the connections of third terminals  308   a ,  308   b  to first and second terminals  302   a ,  302   b , respectively, third terminal  308   a  has a first voltage with respect to first terminal  302   a  and therefore applies to first resistive segment  304   a  a first electric field  312   a  having a first polarity. Third terminal  308   b  has a second voltage with respect to second terminal  302 B and therefore applies to second resistive segment  304   b  a second electric field  312   b  having an opposite second polarity. Consequently, the variation in impedance in resistive segment  304   a  due to the presence of an electric field  312   a  is offset by the variation in impedance in resistive segment  304   b  due to the presence of electric field  312   b . Assuming the number of resistive segments  304  is an even integer and the lengths of each pair of resistive segments  304   a ,  304   b  are equal as shown, the cumulative resistance of the overall resistive circuit  300  will be linear at least to a first order approximation despite the non-linearity of the resistances of the individual resistive segments  304 . Of course, even if the lengths of each pair of resistive segments  304   a ,  304   b  are not precisely equal but are only approximately equal (e.g., differ up to 20 or 30 percent), significant compensation for the non-linearity of resistive circuit  300  will still be achieved. 
     Resistive circuit  300  of  FIG. 3A  is only one of a large number of embodiments of resistive circuits that may be implemented in accordance with the present invention. For example, in a typical analog integrated circuit implementation in which a resistive circuit  300  is integrated in a substrate  301 , third terminals  308  are formed of metal, polycrystalline or a substrate well, isolation region  310  is formed of a dielectric material, such as silicon dioxide, that overlays third terminals  308 , and resistive segments  304  are formed of polycrystalline. However, it should be appreciated from the present disclosure that numerous alternative embodiments, including those not realized in integrated circuitry, are possible and included within the scope of the appended claims. In such alternative embodiments, numerous variations in materials and physical interrelationships of features are possible. For example, the material employed for the segmented third terminal can be any material capable of applying an electric field to the resistive segments, including, without limitation, the casing or packaging of a discrete resistor. Similarly, the isolation region can be implemented, without limitation, with a polymer or a gas phase material, such as air. In addition, the third terminals are not limited in position to underlying the resistive segments (as shown, for example, in  FIG. 3A ), but can instead be realized in any relation to the resistive segments in three-dimensional space. 
       FIG. 3B  depicts a second embodiment of a resistive circuit  314  in accordance with the present invention. The embodiment of  FIG. 3B  is identical to that of  FIG. 3A , except that the embodiment of  FIG. 3B  includes multiple third terminals for each resistive segment  304 . That is, third terminals  308   a   1  and  308   a   2  apply positive electric fields  312   a   1  and  312   a   2  to resistive segment  304   a , and third terminals  308   b   1  and  308   b   2  apply negative electric fields  312   b   1  and  312   b   2  to resistive segment  304   b . It will be appreciated that not all third terminals for a resistive circuit are required to be formed of the same material. For example, in some implementations, third terminals  308   a   1  and  308   b   1  are implemented as substrate wells, and some third terminals  308   a   2  and  308   b   2  are implemented with metallizations. 
       FIG. 3C  illustrates a third embodiment of a resistive circuit  316  in accordance with the present invention. The embodiment of  FIG. 3C  is similar to that of  FIG. 3A , except that third terminals  308   a ,  308   b  are directly connected to one another and are each electrically connected to the ends of resistive segments  304   a ,  304   b  distal from terminal  302   a ,  302   b . As a result of this connection, third terminal  308   a  applies a negative electric field to resistive segment  304   a , and third terminal  308   b  applies a positive electric field to resistive segment  304   b.    
       FIG. 3D  illustrates a fourth embodiment of a resistive circuit  320  in accordance with the present invention. The fourth embodiment of  FIG. 3D  employs a central connection of the segmented third terminal to the resistive segments similarly to the embodiment of  FIG. 3C , but includes multiple third terminals for each resistive segment  304  as described above with reference to  FIG. 3B . As depicted, third terminals  308   a   1  and  308   a   2  apply negative electric fields  312   a   1  and  312   a   2  to resistive segment  304   a , and third terminals  308   b   1  and  308   b   2  apply positive electric fields  312   b   1  and  312   b   2  to resistive segment  304   b . All of third terminals  308   a   1 ,  308   a   2 ,  308   b   1  and  308   b   2  are centrally connected by conductor  306 . 
       FIG. 3E  depicts a fifth embodiment of a resistive circuit  324  in accordance with the present invention. The fifth embodiment of  FIG. 3E  employs a central connection of the segmented third terminal to the resistive segments similarly to the embodiment of  FIG. 3C , but includes a buffer  326  coupled between conductor  306  and third terminals  308   a ,  308   b  in order to avoid losses due to current leakage from resistive segments  304   a ,  304   b  to third terminals  308   a ,  308   b.    
       FIG. 3F  illustrates a sixth embodiment of a resistive circuit  328  in accordance with the present invention. That sixth embodiment of  FIG. 3F  is similar to that of  FIG. 3D , but includes a buffer  326  coupled between conductor  306  and third terminals  308   a   1 ,  308   a   2 ,  308   b   1 , and  308   b   2  to avoid losses due to current leakage from resistive segments  304   a ,  304   b  to third terminals  308   a   1 ,  308   a   2 ,  308   b   1 , and  308   b   2 . 
       FIG. 3G  depicts a seventh embodiment of a resistive circuit  330  in accordance with the present invention. The seventh embodiment of  FIG. 3G  is similar to the first embodiment depicted in  FIG. 3A , except that the seventh embodiment includes a buffer  326   a  coupled between resistive segment  304   a  and third terminal  308   a  and a buffer  326   b  coupled between resistive segment  304   b  and third terminal  308   b  in order to avoid losses due to leakage currents. 
       FIG. 3H  illustrates an eighth embodiment of a resistive circuit  332  in accordance with the present invention. The eighth embodiment of  FIG. 3H  is similar to the second embodiment shown in  FIG. 3B , except that the eighth embodiment includes a respective one of buffers  326   a   1  and  326   a   2  coupled between resistive segment  304   a  and third terminals  308   a   1  and  308   a   2  and further includes a respective one of buffers  326   b   1  and  326   b   2  coupled between resistive segment  304   b  and third terminals  308   b   1  and  308   b   2  in order to avoid losses due to leakage currents. 
     Referring now to  FIG. 3I , there is depicted a section view of a ninth embodiment of a resistive circuit  340  in accordance with the present invention. As depicted, resistive circuit  300  includes a first terminal  302   a  characterized by voltage V 1  and a second terminal  302   b  characterized by voltage V 2 , where voltage V 2 &gt;voltage V 1 . Coupled in parallel between terminals  302   a ,  302   b  are multiple (in this case, two) resistive segments  304   a ,  304   b  formed of polycrystalline silicon or other resistive material subject to non-linear behavior when subjected to an electric field. Resistive segments  304  are spaced apart from one another. 
     Resistive circuit  340  further includes multiple third terminals  308   a ,  308   b  equal in number to the number of resistive segments  304 . Each third terminal  308  is coupled at one end to an end of a respective resistive segment  304 , in this case at one of first and second terminals  302   a ,  302   b . That is, third terminal  308   a  is coupled to an end of a resistive segment  304   a  at first terminal  302   a , and third terminal  308   b  is coupled to an end of a resistive segment  304   b  at second terminal  302   b . Third terminals  308  are separated from resistive segments  304  by an isolation region  310 . Substantially no DC current flows in third terminals  308 , and leakage currents can be reduced by implementing one of optional buffers  326   a  and  326   b  between each resistive segment  304   a ,  304   b  and its respective third terminal  308   a ,  308   b.    
     By virtue of the connections of third terminals  308   a ,  308   b  to first and second terminals  302   a ,  302   b , respectively, third terminal  308   a  has a first voltage with respect to first terminal  302   a  and therefore applies a first electric field  312   a  to first resistive segment  304   a , and third terminal  308   b  has a second voltage with respect to second terminal  302   b  and applies a second electric field  312   b  having a same polarity to second resistive segment  304   b . Consequently, the variation in impedance in resistive segment  304   a  due to the presence of an electric field  312   a  is offset by the variation in impedance in resistive segment  304   b  due to the presence of electric field  312   b.    
     In contrast to the series-connected embodiments of  FIGS. 3A-3H  described above, embodiments in which the resistive segments are connected in parallel generally do not achieve full compensation for non-linearity, but nevertheless can still achieve significant compensation (e.g., up to approximately 90%). 
     Resistive circuits in accordance with the present invention not only are capable of implementation in a number of different embodiments, as demonstrated above, but also are susceptible to a wide variety of circuit applications. For example,  FIG. 4  depicts a voltage divider circuit  400  in which resistive circuits in accordance with the present invention may be utilized. Voltage divider circuit  400  includes a resistor R 1   406  coupled between input terminal  402  and output terminal  404  and a resistor R 2   408  coupled between output terminal  404  and ground. With this configuration, the output voltage V out  is related to V in  as follows: 
               V   out     =         R     2   ⁢                   R   1     +     R   2         ·     V   in             
A resistive circuit in accordance with the present invention can be utilized to implement resistor R 1   406  and/or resistor R 2   408 .
 
     In addition, resistive circuits in accordance with the present invention can be applied to any of the wide number of amplifier circuits containing impedances, including those shown in  FIGS. 5A-5D . In these figures, explicit depiction of the third terminals is omitted to avoid obscuring the structure of the circuits. 
     Referring first to  FIG. 5A , there is depicted a current-to-voltage conversion circuit  500  having a resistor  504  that can be implemented utilizing a resistive circuit in accordance with the present invention. As shown, current-to-voltage conversion circuit  500  includes an amplifier  502  having a feedback resistor  504  coupled between its output and negative input, a current source  506  coupled to provide a current I to the negative input of amplifier  502 , and a ground voltage reference coupled to the positive input of amplifier  502 . The output voltage Vout of amplifier  502  is given by the following equation:
 
 V out= I×R  
 
As will be appreciated from the above equation, both the linearity and the absolute value of the resistor are important in obtaining the correct output voltage Vout.
 
       FIGS. 5B and 5C  respectively illustrate an inverting gain amplifier circuit  510  and a non-inverting gain amplifier circuit  520  that employ resistive circuits in accordance with the present invention. Each of amplifier circuits  510  and  512  includes an amplifier  512  having a feedback resistor R 2   516  coupled between its output and negative input and a resistor R 1   514  coupled to the negative input of amplifier  502 . In inverting gain amplifier circuit  510 , resistor R 1   514  is coupled to receive input voltage Vin, and the positive input of amplifier  512  is coupled to ground. Given this configuration, output voltage Vout for inverting gain amplifier circuit  510  is given as follows: 
             Vout   =       -     V   in       ·       R   2       R   1               
In non-inverting gain amplifier circuit  520 , the connection of amplifier inputs is reversed, with resistor R 1   514  being coupled to ground, and the positive input of amplifier  512  being coupled to receive input voltage Vin. With this configuration, output voltage Vout for non-inverting gain amplifier circuit  520  is given as:
 
             Vout   =       V   in     ⁡     (     1   +       R   2       R   1         )             
As described above, a resistive circuit in accordance with the present invention can be utilized to implement resistor R 1   514  and/or resistor R 2   516 .
 
     A resistive circuit in accordance with the present invention can also be utilized to implement any resistor within a difference amplifier circuit such as that shown in  FIG. 5D . Difference amplifier circuit  530  of  FIG. 5D  includes an amplifier  512  having a feedback resistor R 2   534   a  coupled between its output and negative input and a resistor R 1   532   a  coupled between the negative input of amplifier  512  and one side of input voltage Vin. Difference amplifier circuit  530  of  FIG. 5D  further includes a resistor R 1   532   b  coupled between the positive input of amplifier  512  and a second side of input voltage Vin. A resistor R 2   534   b  is coupled between the positive input of amplifier  512  and ground. The differential input voltage Vin presented to resistors R 1   532   a  and  532   b  is amplified to obtain output voltage Vout according to the following equation: 
             Vout   =       V   in     ·       R   2       R   1               
It will be appreciated that difference amplifier  530  can be utilized as a non-inverting amplifier by grounding the input of resistor R 1   532   a.  
 
     In the embodiments of resistive circuits described above, each pair of resistive segments has been described as comprising resistive segments of approximately the same length (e.g., L/2). However, according to present invention, compensation for the field effect on polycrystalline resistors can also be achieved in circuits having multiple resistors (e.g., amplifier circuits  510 ,  520  and  530  of  FIGS. 5B-5D ) by appropriate selection of the dimensions of resistive segments of differing sizes. To mathematically demonstrate compensation for the field effect in such cases, the following first order approximation of the resistance R of a polycrystalline resistor will be recalled from the preceding discussion: 
             R   =           ρ   o     ⁢   L     HW     +           L   2     ⁢     ρ   o         2   ⁢           ⁢   HW       ⁢   k   ⁢     B   _     ⁢     e   ^               
where H is height, W is width, L is length, ρ o  is bulk resistivity of the polycrystalline silicon. Given that k is a constant equal to the voltage applied to the resistor divided by the length L
 
               (       i   .   e   .     ,       Δ   ⋁       L   ⁢                 )     ,         
the above equation can be rewritten as follows:
 
     
       
         
           
             R 
             = 
             
               
                 
                   
                     
                       ρ 
                       o 
                     
                     ⁢ 
                     L 
                   
                   HW 
                 
                 + 
                 
                   
                     
                       
                         L 
                         2 
                       
                       ⁢ 
                       
                         ρ 
                         o 
                       
                     
                     
                       2 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       HW 
                     
                   
                   ⁢ 
                   
                     
                       Δ 
                       ⋁ 
                     
                     
                       L 
                       ⁢ 
                       
                           
                       
                     
                   
                   ⁢ 
                   
                     B 
                     _ 
                   
                   ⁢ 
                   
                     e 
                     ^ 
                   
                 
               
               = 
               
                 
                   
                     
                       ρ 
                       o 
                     
                     ⁢ 
                     L 
                   
                   HW 
                 
                 + 
                 
                   
                     
                       L 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         ρ 
                         o 
                       
                     
                     
                       2 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       HW 
                     
                   
                   ⁢ 
                   
                     Δ 
                     ⋁ 
                     
                       B 
                       _ 
                     
                   
                   ⁢ 
                   
                     e 
                     ^ 
                   
                 
               
             
           
         
       
     
     Consider now the inverting gain amplifier  540  shown in  FIG. 5E , which includes an amplifier  512 , a polycrystalline feedback resistor R 2   550  comprising resistive segments Ra  552  and Rb  554 , and a polycrystalline input resistor R 1   542  coupled between input voltage Vin and the negative input of amplifier  540 . In the depicted embodiment, feedback resistor R 2   550  and resistor R 1   542  are implemented similarly to the embodiment of  FIG. 3A , except that resistive segments Ra  552  and Rb  554  are of unequal lengths, and resistor R 1   542  is formed of a single resistive segment. As depicted, the third terminals of resistive segment Ra  552  and of input resistor R 1   542  are each coupled to ground, causing electric fields of the depicted polarities. 
     Utilizing the above equation, the resistances of each of input resistor R 1   542  and resistive segments Ra  552  and Rb  554  can be expressed as follows: 
               R   1     =           ρ   o     ⁢     L   1       HW     +           L   1     ⁢     ρ   o         2   ⁢   HW       ⁢     V   ⁢   in     ⁢           ⁢     B   _     ⁢     e   ^                       R   a     =           ρ   o     ⁢     L   a       HW     -           L   a     ⁢     ρ   o         2   ⁢   HW       ⁢       L   a         L   a     +     L   b         ⁢   Vout   ⁢           ⁢     B   _     ⁢     e   ^                       R   b     =           ρ   o     ⁢     L   b       HW     +           L   b     ⁢     ρ   o         2   ⁢   HW       ⁢       L   b         L   a     +     L   b         ⁢   Vout   ⁢     B   _     ⁢     e   ^               
Thus, the total resistance of feedback resistor R 2   550  can be expressed as a sum as follows:
 
                       R   a     +     R   b       =       ⁢           ρ   o     ⁢     L   a       HW     +         ρ   o     ⁢     L   b       HW     +           ρ   o     ⁢     L   b         2   ⁢   HW       ⁢       L   b         L   a     +     L   b         ⁢   Vout   ⁢           ⁢     B   _     ⁢     e   ^       -                     ⁢           ρ   o     ⁢     L   a         2   ⁢   HW       ⁢       L   a         L   a     +     L   b         ⁢   Vout   ⁢           ⁢     B   _     ⁢     e   ^                   =       ⁢           ρ   o     ⁡     (       L   a     +     L   b       )       HW     +           ρ   o     ⁡     (       L   b     -     L   a       )         2   ⁢   HW       ⁢   Vout   ⁢           ⁢     B   _     ⁢     e   ^                     
Remembering now that the output voltage for an inverting gain amplifier is given by:
 
               Vout   =       -     V   in       ·       R   2       R   1           ,         
the gain G of inverting gain amplifier  540  can be expressed as the ratio of R 2  to R 1  as follows:
 
             G   =         R   2       R   1       =           R   a     +     R   b         R   1       =       [           ρ   o     ⁡     (       L   a     +     L   b       )       HW     +           ρ   o     ⁡     (       L   b     -     L   a       )         2   ⁢   HW       ⁢   Vout   ⁢           ⁢     B   _     ⁢     e   ^         ]             ρ   o     ⁢     L   1       HW     +           ρ   o     ⁢     L   1         2   ⁢   HW       ⁢   Vin   ⁢     e   ^     ⁢     B   _                     
This equation can be further reduced through cancellation of terms to the following expression:
 
     
       
         
           
             G 
             = 
             
               
                 
                   [ 
                   
                     
                       ( 
                       
                         
                           L 
                           a 
                         
                         + 
                         
                           L 
                           b 
                         
                       
                       ) 
                     
                     + 
                     
                       
                         1 
                         2 
                       
                       ⁢ 
                       
                         ( 
                         
                           
                             L 
                             b 
                           
                           - 
                           
                             L 
                             a 
                           
                         
                         ) 
                       
                       ⁢ 
                       Vout 
                       ⁢ 
                       
                         e 
                         ^ 
                       
                       ⁢ 
                       
                         B 
                         _ 
                       
                     
                   
                   ] 
                 
                 
                   
                     L 
                     1 
                   
                   + 
                   
                     
                       1 
                       2 
                     
                     ⁢ 
                     
                       L 
                       1 
                     
                     ⁢ 
                     Vin 
                     ⁢ 
                     
                       e 
                       ^ 
                     
                     ⁢ 
                     
                       B 
                       _ 
                     
                   
                 
               
               ⁢ 
               
                 
 
               
               ⁢ 
               
                   
               
               = 
               
                 
                   [ 
                   
                     
                       
                         ( 
                         
                           
                             L 
                             a 
                           
                           + 
                           
                             L 
                             b 
                           
                         
                         ) 
                       
                       
                         L 
                         1 
                       
                     
                     + 
                     
                       
                         1 
                         2 
                       
                       ⁢ 
                       
                         
                           ( 
                           
                             
                               L 
                               b 
                             
                             - 
                             
                               L 
                               a 
                             
                           
                           ) 
                         
                         
                           L 
                           1 
                         
                       
                       ⁢ 
                       Vout 
                       ⁢ 
                       
                         e 
                         ^ 
                       
                       ⁢ 
                       
                         B 
                         _ 
                       
                     
                   
                   ] 
                 
                 
                   1 
                   + 
                   
                     
                       1 
                       2 
                     
                     ⁢ 
                     Vin 
                     ⁢ 
                     
                       e 
                       ^ 
                     
                     ⁢ 
                     
                       B 
                       _ 
                     
                   
                 
               
             
           
         
       
     
     Because the resistance of each of resistive segments Ra  552  and Rb  554  is proportional to its length, this expression can alternatively be stated as follows: 
             G   =           R   a     +     R   b         R   1       =           L   a     +     L   b         L   1       =       [         (       L   a     +     L   b       )       L   1       +       1   2     ⁢       (       L   b     -     L   a       )       L   1       ⁢   Vout   ⁢     e   ^     ⁢     B   _         ]       1   +       1   2     ⁢   Vin   ⁢     e   ^     ⁢     B   _                           Thus   ,     
     ⁢             L   a     +     L   b         L   1       ⁡     [     1   +       1   2     ⁢   Vin   ⁢     e   ^     ⁢     B   _         ]       =         (       L   a     +     L   b       )       L   1       +       1   2     ⁢       (       L   b     -     L   a       )       L   1       ⁢   Vout   ⁢     e   ^     ⁢     B   _                           1   2     ⁢         L   a     +     L   b         L   1       ⁢   Vin   ⁢     e   ^     ⁢     B   _       =       1   2     ⁢       (       L   b     -     L   a       )       L   1       ⁢   Vout   ⁢     e   ^     ⁢     B   _                           L   a     +     L   b         L   1       ⁢   Vin     =         (       L   b     -     L   a       )       L   1       ⁢   Vout                   Vout   Vin     =           L   a     +     L   b           L   b     -     L   a         =     G   =         L   a     +     L   b         L   1                 
Therefore, to achieve first order compensation for the field effect on the polycrystalline resistors of an amplifier circuit, it is sufficient if the following equation is satisfied:
 
 L   b   −L   a   =L   1 ,
 
assuming that electric fields of the same polarity are applied to resistive segment Rb  554  and input resistor R 1   542  and that an electric field of the opposite polarity is applied to resistive segment Ra  552 . For a non-inverting configuration, the same equation is applicable; however, it should be noted that complete compensation is achieved when L a =0.
 
     Thus, for amplifier and other circuits employing multiple polycrystalline resistors, compensation for the field effect can be achieved utilizing either or a combination of two techniques, namely, (1) the use of paired polycrystalline resistive segments of equal dimensions to which electric fields of opposite polarities are applied by a segmented third terminal and/or (2) the use of one or more polycrystalline resistive segments of appropriately selected dimensions to which specified electric fields are applied. To illustrate the use of these techniques in combination,  FIG. 5F  depicts an embodiment of a difference amplifier circuit that utilizes both of the techniques described herein to compensate for the field effect on polycrystalline resistors. 
     As shown in  FIG. 5F , difference amplifier circuit  560  includes an amplifier  512  having a feedback resistor R 2   570  coupled between its output and negative input. Feedback resistor R 2   570  comprises polycrystalline resistive segments Ra  572  and Rb  574  and a respective associated third terminal for each resistive segment. Difference amplifier circuit  560  also includes an input resistor R 1   562  coupled between the negative input of amplifier  512  and one side the input voltage Vin. Resistor R 1   562  comprises a single polycrystalline resistive segment and an associated third terminal. According to the rule set forth above, the field effect on resistors R 1   562  and R 2   570  is compensated for by setting the length of resistor R 1  equal to the difference in lengths of resistive segments Rb  574  and Ra  572  comprising resistor R 2   570 . Thus, compensation can be achieved utilizing fewer resistive segments and fewer third terminals than with the technique depicted in  FIG. 3A . 
     Difference amplifier circuit  560  further includes an input resistor R 3   580  coupled between the positive input of amplifier  512  and the second side of input voltage Vin, and difference amplifier circuit  560  also includes a resistor R 4   590  coupled between the positive input of amplifier  512  and ground. In order to compensate for the field effect for resistors R 3   580  and R 4   590 , each of resistors R 3   580  and R 4   590  is implemented as a pair of resistive segments (i.e., Rc  582 , Rd  584 , Re  592  and Rf  594 ) each having an associated third terminal, as described above with reference to  FIGS. 3A-3H . 
     As has been described, the present invention provides improved apparatus, systems and methods for compensating for the field effect on resistors formed of polycrystalline material, such as polycrystalline silicon. In accordance with the present invention, the compensation achieved by a resistive circuit in accordance with the present invention can either be complete or partial. 
     While the invention has been particularly shown as described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.