Patent Publication Number: US-2021184595-A1

Title: Systems and methods for controlling multi-level diode-clamped inverters using space vector pulse width modulation (svpwm)

Description:
BACKGROUND 
     The present disclosure generally relates to Space Vector PWM (SVPWM) control for multi-level diode-clamped inverters for various applications including Data Center (DC) applications. 
     DCs are one of the largest and fastest growing consumers of electricity in the world. In 2013, DCs in the U.S. consumed an estimated 91 billion kWhr of electricity, which is enough electricity to power all the households in New York City twice over. And the DCs in the U.S. are on track to consume an estimated 140 billion kWhr by 2020. 
     A Multi-level Medium Voltage Data Center Static Synchronous Compensator (DCSTATCOM) or a Multi-level Medium Voltage Uninterruptable Power Supply (MVUPS) with battery energy storage may be employed to ensure a reliable supply of power to DCs. DCSTATCOM or MVUPS connected in a shunt configuration at a point of common coupling (PCC) to a data center (DC) load, enables independent simultaneous control capability of both active (to provide UPS functionality, grid energy storage, and peak demand load supply) and reactive (to provide Power Factor (PF) correction, grid voltage stiffness, and transient stabilizer functions) power compensation for both DC and grid stabilization. 
     Multi-level voltage-fed PWM inverters are showing popularity in multi-megawatt DCSTATCOM or MVUPS applications due to easy sharing of large voltages between the series-connected IGBT devices and improvement of harmonic quality at the output compared to the existing two-level inverters with transformer systems. 
     SUMMARY 
     In aspects, the present disclosure features a control system for a multi-level inverter. The control system includes a digital logic circuit, a digital up/down counter, a processor, and memory. The digital logic circuit includes digital logic comparators, which include a first comparator and a second comparator, inverters, which include a first inverter, coupled to respective outputs of respective comparators, and AND gates including an AND gate having a first input and a second input. The first input is coupled to the output of the first inverter and the second input is coupled to the output of the second comparator. The control system further includes a digital up/down counter coupled to first inputs of the comparators. The up/down counter counts from 0 to T S /2 and then from T S /2 to 0 where T S  is the sampling period. 
     The control system further includes a processor and memory that identify a sector location based on an actual angle of a reference voltage vector, convert the actual angle into a converted angle located in a first sector, identify a reference region location based on the magnitude of the reference voltage vector and the converted angle in the first sector, select a switching sequence and turn-on time values based on the corresponding actual region location and actual sector, and transmit turn-on signal values to second inputs of the plurality of comparators to generate switching signals for IGBT drivers of a multi-level inverter. 
     In aspects, the digital logic circuit is a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC). In aspects, the processor is a digital signal processor (DSP). 
     In aspects, the number of the comparators and the number of the inverters is one less than the number of levels of the multi-level inverter. In aspects, the number of the AND gates is one less than the number of the comparators. 
     In aspects, the processor and memory are further configured to convert the reference voltage vector and the converted angle into X and Y coordinate point values in the first sector, and identify a region location based on the X and Y coordinate point values. 
     In aspects, the multi-level inverter is a five-level inverter, the comparators further include a third comparator and a fourth comparator, the inverters further include a second inverter, a third inverter, and a fourth inverter, the AND gates further include a second AND gate and a third AND gate, a first input of the second AND gate is coupled to the output of the second inverter and a second input of the second AND gate is coupled to the output of the third comparator, a first input of the third AND gate is coupled to the output of the third inverter and a second input of the third AND gate is coupled to the output of the fourth comparator, and the output of the first comparator, the outputs of the plurality of AND gates, and the output of the fourth inverter provide the switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter. 
     In aspects, the multi-level inverter is a four-level inverter, the comparators further include a third comparator, the inverters further include a second inverter and a third inverter, the plurality of AND gates further include a second AND gate, a first input of the second AND gate is coupled to the output of the second inverter and a second input of the second AND gate is coupled to the output of the third comparator, and the output of the first comparator, the outputs of the plurality of AND gates, and the output of the third inverter provide the switching signals. 
     In aspects, identifying a region location includes comparing the X and Y coordinate point values to segments of triangles, which represent regions, in a vector space. 
     In aspects, the turn-on time values and switching sequence are predetermined for each sector and region, and stored in a look-up table stored in the memory. 
     In aspects, the present disclosure features a method of controlling a multi-level inverter. The method includes identifying a sector location based on an actual angle of a reference voltage vector, converting the actual angle into a converted angle located in a first sector, identifying a region location based on the magnitude of the reference voltage vector and the converted angle in the first sector, selecting a switching sequence and turn-on signal values based on the corresponding region location in actual sector of reference voltage vector, transmitting turn-on time values to second inputs of the comparators to generate switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter, comparing each of the turn-on signals to a digital up/down counter signal to obtain comparison signals including a first comparison signal and a second comparison signal, inverting the comparison signals to obtain inverted signals including a first inverted signal, and performing a logical AND operation on the first inverted signal and the second comparison signal to obtain a switching signal for a corresponding driver that drives a power transistor of a multi-level inverter. 
     In aspects, the method further includes converting the reference voltage vector and the converted angle into X and Y coordinate point values, and identifying a region location based on the X and Y coordinate point values. 
     In aspects, identifying a region location includes comparing the X and Y coordinate point values to segments of triangles, which represent regions, in a vector space. 
     In aspects, the turn-on time values and switching sequences are predetermined for each sector and region, and stored in a look-up table stored in memory. 
     In aspects, the first comparison signal is a first gate drive switching signal (to generate either P 2  or N 2  switching states), the logical AND operation is performed on the first inverted signal and the second comparison signal to obtain a second switching signal (to generate either P 1  or N 1  switching states), the comparison signals further include a third comparison signal and a fourth comparison signal, the inverted signals further include a second inverted signal, a third inverted signal, and a fourth inverted signal, the method further includes performing a second logical AND operation on the second inverted signal and the third comparison signal to obtain a third switching signal (to generate O switching states), and performing a second logical AND operation on the second inverted signal and the third comparison signal to obtain a fourth switching signal (to generate either N 1  or P 1  switching states), and the fourth inverted signal is a fifth switching signal (to generate either N 2  or P 2  switching states). 
     In aspects, the present disclosure features an energy storage system including an energy storage device, a DC-DC converter coupled to the energy storage device, a multi-level inverter coupled to the DC-DC converter, and a multi-level inverter controller coupled to the multi-level inverter. The multi-level inverter controller includes a digital logic circuit. The digital logic circuit includes comparators including a first comparator and a second comparator, inverters, including a first inverter, coupled to respective outputs of respective comparators, and AND gates including a first AND gate having a first input and a second input. The first input is coupled to the output of the first inverter and the second input is coupled to the output of the second comparator. The multi-level inverter controller further includes a counter coupled to first inputs of the plurality of comparators and a processor and memory. The processor and memory identify a sector location based on an actual angle of a reference voltage vector, convert the actual angle into a converted angle located in a first sector, identify a region location based on the magnitude of the reference voltage vector and the converted angle in the first sector, select a switching sequence and turn-on signal values based on the corresponding region and actual reference voltage vector location, and transmit turn-on signal values to second inputs of the plurality of comparators to generate switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a system block diagram of a data center power supply system according to embodiments of the present disclosure; 
         FIG. 2  is a circuit diagram of a three-phase five-level diode-clamped inverter according to embodiments of the present disclosure; 
         FIGS. 3A and 3B  show a space vector diagram illustrating space voltage vectors of a three-phase five-level inverter according to embodiments of the present disclosure; 
         FIG. 4  is a space vector diagram illustrating space vectors indicating regions and switching times according to embodiments of the present disclosure; 
         FIG. 5  is a space vector diagram illustrating switching states and switching times of region  1  and sectors A-F for an example mode according to embodiments of the present disclosure; 
         FIG. 6  is a waveform diagram illustrating switching states for one phase of sectors A-F and region  1 ; 
         FIG. 7  is a waveform diagram illustrating a sequence of switching states of the three phases in regions  1 - 4  of sector A according to embodiments of the present disclosure; 
         FIGS. 8-12  are waveform diagrams illustrating generation of turn-on time signals and switching logic signals according to embodiments of the present disclosure; 
         FIG. 13  is a graphical diagram illustrating turn-on time values for one phase according to embodiments of the present disclosure; 
         FIG. 14  is a digital logic circuit for generating switching logic signals to drive power transistors of a multi-level diode-clamped inverter according to embodiments of the present disclosure; 
         FIG. 15  is a flow diagram of a method of identifying region and sector locations of a voltage vector according to embodiments of the present disclosure; 
         FIG. 16  is a SVPWM controller for a five-level diode-clamped inverter according to embodiments of the present disclosure; and 
         FIG. 17  is a flow diagram of a method of controlling a multi-level inverter according to embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The present disclosure relates to a processor and digital logic circuit-based hybrid controller and its implementation of SVPWM control strategies for multi-level diode-clamped inverters, e.g., multi-level diode-clamped inverters for Multi-level Medium Voltage Data Center Static Synchronous Compensator (DCSTATCOM) or Multi-level Medium Voltage Uninterruptable Power Supply (MVUPS) with battery energy storage for a data center (DC) load connected at a medium voltage (MV) level. MV operation reduces overall losses of DC components and hence improves overall efficiency of the system. 
     A control system of the present disclosure includes a digital logic circuit, such as a Field Programmable Gate Array (FPGA), and a processor, such as a digital signal processor (DSP) or a microprocessor. The processor samples a reference voltage vector V* and an angle Θ e *, and identifies a sector and region based on the sampled reference voltage vector V* and angle Θ e *. The processor then selects predefined switching sequences and pre-calculated turn-on time values based on the identified sector and region location of the reference voltage vector V*. The digital logic circuit generates PWM switching signals for driving power transistors of a multi-level diode-clamped inverter based on the turn-on time values and the selected switching sequences. 
     For multi-level inverters, the SVPWM control strategy is more suitable in comparison to sinusoidal PWM as the SVPWM control strategy offers significant flexibility to synthesize switching sequences of waveforms and is suitable for digital implementation by a processor, e.g., a DSP, and a digital logic circuit, e.g., an FPGA, forming a hybrid controller. 
     In SVPWM, the inverter voltage vectors, which correspond to the apexes of the triangle, which includes the reference voltage vector, are generally selected to minimize harmonics at the output in comparison to sinusoidal PWM. SVPWM also provides larger under modulation range that extends the modulation factor to 90.7% from the traditional value of 78.5% in sinusoidal PWM. 
     In the control systems of the present disclosure, a hybrid controller, which includes a processor and a digital logic circuit, is utilized to implement various control blocks to carry out the SVPWM control strategy. The PWM signal generation task for providing PWM switching signals to the gate driver for driving a power transistor is carried out by a digital logic circuit, e.g., an FPGA. The remaining tasks are performed by a processor, e.g., a DSP. Therefore, a less expensive hybrid processor and digital logic controller is used to implement an overall complex control strategy. Also, the control tasks are divided between a processor and a digital logic circuit to achieve a faster transient response at lower cost. 
     The systems and methods of the present disclosure may be applied to a Multi-level Medium Voltage Data Center Static Synchronous Compensator (DCSTATCOM) or Multi-level Medium Voltage Uninterruptable Power Supply (MVUPS), as described in U.S. application Ser. No. 14/481,904, entitled “Multi-level Medium Voltage Data Center Static Synchronous Compensator (DCSTATCOM) for Active and Reactive Power Control of Data Centers connected with Grid Energy Storage and Smart Green Distributed Energy Sources”, filed on Sep. 9, 2014, and U.S. application Ser. No. 14/594,073, entitled “Transformerless Multi-level Medium Voltage Uninterruptable Power Supply (UPS) System”, filed on Jan. 9, 2015, each of which are incorporated herein by reference in their entireties. 
       FIG. 1  is a system block diagram of a DCSTATCOM or MVUPS topology with a transfer switch  112  connected between a utility and a generator  110 , a static transfer switch  114 , a transformer  116 , and a DC IT load  118 . The DCSTATCOM or MVUPS systems include a battery energy storage block  120 , a battery management system (BMS) controller  130 , a bi-directional multi-level (ML) DC-DC converter  122 , a DC-DC converter controller  132 , a ML inverter  124  outputting medium voltage AC (V INV ) at the inverter output, and an SVPWM inverter controller  134  for controlling the ML inverter  124 . As described in more detail below, the SVPWM inverter controller  134  includes a processor and a digital logic circuit for generating PWM switching signals, which are applied to driver circuits (not shown) for driving power transistors (not shown) of the ML inverter  124 . 
       FIG. 2  is a circuit block diagram of a five-level diode-clamped inverter, which may be used as the ML inverter  124 , which converts DC voltage V DC  output from the converter  122  to three-phase AC voltage Vac. The five-level inverter includes power transistors or switches S 1U -S 8U , S 1V -S 8V , and S 1W -S 8W , and diodes connected together in a diode-clamped configuration to generate three phases U, V, and W of an AC voltage Vac. State O represents neutral point balancing so that the average current injected at O should be zero. States P 1  and P 2  represent positive bus voltages. States N 1  and N 2  represent negative bus voltages. 
     Switches S 1U -S 8U , S 1V -S 8V , and S 1W -S 8W  may be power transistors, such as IGBTS. IGBTS allow for higher voltages or currents and higher switching frequencies. The five-level inverter illustrated in  FIG. 2  allows for sharing of the high voltage among the switches S 1U -S 8U , S 1V -S 8V , and S 1W -S 8W , and reduces harmonic distortion. 
     The complexity of an inverter control system increases as the inverter level increases from three to five or above. A three-phase five-level diode-clamped inverter illustrated in  FIG. 2  is complex due to a high number of switching states, i.e., 5 3 =125 switching states, in comparison to a three-phase three-level inverter with a lower number of switching states, i.e., 3 3 =27 switching states. The inverter must have a very fast response time (in micro-seconds) to have appropriate control operation and safety aspects for IGBT devices. Also, the SVPWM strategy needs to perform many on-line calculations due to its large number of switching states (e.g., 125 for a five-level inverter) and large number of operating regions/triangles (e.g., 96 for a five-level inverter). Therefore, in embodiments, the control systems of the present disclosure incorporate a digital logic circuit, such as an FPGA, to perform partial logic functions. The digital logic circuit may form part of a hybrid controller, which includes a processor and the digital logic circuit. This hybrid controller is well suited to implement SVPWM control because it allows for much larger bandwidth control and provides faster response times. 
     The switching states of the five-level inverter are summarized in Table 1, where X is one of the phases U, V, and W; and P 2  (+V DC /2), P 1  (+V DC /4), O (0 V DC ), N 1  (−V DC /4), and N 2  (−V DC /2) are DC-bus points as shown in  FIG. 2 . 
     
       
         
           
               
               
               
               
               
               
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 Switching 
                   
                   
                   
                   
                   
                   
                   
                   
                   
               
               
                 States 
                 S 1X   
                 S 2X   
                 S 3X   
                 S 4X   
                 S 5X   
                 S 6X   
                 S 7X   
                 S 8X   
                 V XO   
               
               
                   
               
             
            
               
                 P 2   
                 ON 
                 ON 
                 ON 
                 ON 
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 +V DC /2 
               
               
                 P 1   
                 OFF 
                 ON 
                 ON 
                 ON 
                 ON 
                 OFF 
                 OFF 
                 OFF 
                 +V DC /4 
               
               
                 O 
                 OFF 
                 OFF 
                 ON 
                 ON 
                 ON 
                 ON 
                 OFF 
                 OFF 
                 0 
               
               
                 N 1   
                 OFF 
                 OFF 
                 OFF 
                 ON 
                 ON 
                 ON 
                 ON 
                 OFF 
                 −V DC /4 
               
               
                 N 2   
                 OFF 
                 OFF 
                 OFF 
                 OFF 
                 ON 
                 ON 
                 ON 
                 ON 
                 −V DC /2 
               
               
                   
               
            
           
         
       
     
     Referring to Table 1, in conjunction with  FIG. 2 , phase U, for example, is in state P 2  (positive bus voltage) when the switches S 1U -S 4U  are closed or “ON”, and switches S 5U -S 8U  are open or “OFF”. The phase V is in state P 1  (positive bus voltage that is less than P 2 ) when switches S 1U  and S 6U -S 8U  are open or OFF, and switches S 2U -S 5U  are closed or ON. The phase U is in state O when switches S 1U , S 2U , S 7U , and S 8U  are open or OFF and switches S 3U -S 6U  are closed or ON. 
     The phase U is in state N 1 , which corresponds to a negative bus voltage that is greater than a negative bus voltage that corresponds to state N 2 , when switches S 1U -S 3U  and S 8U  are turned off (i.e., open) and switches S 4U -S 7U  are turned on (i.e., closed). The phase U is in state N 2 , which corresponds to a negative bus voltage that is less than the negative bus voltage that corresponds to state N 1 , when switches S 1U -S 4U  are turned off (i.e., open) and switches S 5U -S 8U  are turned on (i.e., closed). 
       FIGS. 3A and 3B  show a space vector diagram illustrating space voltage vectors of a five-level diode-clamped inverter with 125 switching states and 96 operational triangles. There are 120 active switching states and the remaining 5 are zero states (P 2 P 2 P 2 , P 1 P 1 P 1 , OOO, N 1 N 1 N 1 , N 2 N 2 N 2 ) that lie at the origin.  FIGS. 3A and 3B  also show a hexagon having six sectors—sectors A-F, and each sector has sixteen regions—regions  1 - 16 , giving altogether 96 regions of operation. 
     In embodiments, the operation of a multi-level inverter, such as the multi-level inverter of  FIG. 2 , may be divided into multiple modes. As shown in  FIGS. 3A and 3B , the operation is divided into four modes—modes  1 - 4 . In Mode  1  ( 301 ), the command voltage vector V* trajectory covers region  1  of all six sectors, e.g., sectors A-F. In Mode  2  ( 302 ), the command voltage vector V* trajectory covers regions  2 ,  3 , and  4  of all sectors. In Mode  3  ( 303 ), the command voltage vector V* trajectory covers regions  5 ,  6 ,  7 ,  8 , and  9  of all sectors. In Mode  4  ( 304 ), the command voltage vector V* trajectory covers regions  10 ,  11 ,  12 ,  13 ,  14 ,  15 , and  16  of all sectors. 
     Operational Modes 
       FIG. 4  is a space vector diagram illustrating a sector A triangle formed by voltage vectors V 0 , V 10 , and V 14 . In Space Vector Pulse Width Modulation (SVPWM), the inverter voltage vectors V 3 , V 6 , and V 7 , which correspond to the apexes of the region  7  of the sector A triangle, which includes the reference or command voltage vector (V*)  412 , are generally selected to minimize harmonics at the output of the multi-level inverter. If the command voltage vector V* lies in region  7  ( 422 ), as shown in  FIG. 4 , the following two equations are satisfied for SVPWM: 
         V   6   T   a   +V   3   T   b   V   7   T   c   V*T   S   (1)
 
         T   a   +T   b   +T   c   =T   S   (2)
 
     where T a , T b , and T c  are respective time intervals of the nearest three voltage vectors in a particular triangle, and T S  is the sampling time. 
       FIG. 5  is a space vector diagram illustrating switching states and switching times of the three phases of region  1  and sectors A-F in Mode  1 . 
     In embodiments, the switching sequence is pre-defined (and may be stored in a look-up table in memory) and depends on the location of reference voltage vector (V*) in any particular region or triangle. The sequence in opposite sectors, e.g., A-D, B-E, and C-F, is selected to be of a complimentary nature to achieve capacitor neutral voltage balancing. 
       FIG. 6  is a waveform diagram showing the construction of AC voltage waveform patterns based on the sequences of switching states (P 2 , P 1 , O, N 1 , N 2 ) of the U phase in region  1  of sectors A-F (U A1 -U F1 ) for Mode  1  operation. The sequences of switching states are obtained from the space vector diagram of  FIG. 5  where the switching states for the three phases are defined at each of the voltage vectors. The first row  501  of switching states for voltage vector V 0  are switching states for the U phase, the second row  502  of switching states for voltage vector V 0  are switching states for the V phase, and the third row  503  of switching states for voltage vector V 0  are switching states for the W phase. Likewise, the first row  511  of switching states for voltage vector V 1  are switching states for the U phase, the second row  512  of switching states for voltage vector V 1  are switching states for the V phase, and the third row  513  of switching states for voltage vector V 1  are switching states for the W phase. Further, the first row  521  of switching states for voltage vector V 4  are switching states for the U phase, the second row  522  of switching states for voltage vector V 4  are switching states for the V phase, and the third row  523  of switching states for voltage vector V 4  are switching states for the W phase. 
     To construct the first half of the sequence of switching states for phase U, sector A, region  1  (U A1 ) ( 611   a ) over sampling period T S /2 ( 601 ), switching states are obtained from each of the voltage vectors in a counter-clockwise direction. The switching states are obtained from right to left in the first row of switching states assigned to each of the voltage vectors. 
     For example, the first switching state of the sequence U A1  is the right-most switching state in the first row  501  for voltage vector V 0 , which is N 2 . The second switching state of the sequence U A1  is the right-most switching state in the first row  511  for voltage vector V 1 , which is N 1 . The third switching state of the sequence U A1  is the right-most switching state in the first row  521  for voltage vector V 4 , which is N 1 . The fourth switching state of the sequence U A1  is the second switching state from the right in the first row  501  for voltage vector V 0 , which is N 1 . The fifth switching state of the sequence U A1  is the second switching state from the right in the first row  511  for voltage vector V 1 , which is O. The sixth switching state of the sequence U A1  is the second switching state from the right in the first row  521  for voltage vector V 4 , which is O. The seventh switching state of the sequence U A1  is the third switching state from the right in the first row  501  for voltage vector V 0 , which is O. 
     The eighth switching state of the sequence U A1  is the third switching state from the right in the first row  511  for voltage vector V 1 , which is P 1 . The ninth switching state of the sequence U A1  is the third switching state from the right in the first row  511  for voltage vector V 1 , which is P 1 . The tenth switching state of the sequence U A1  is the third switching state from the right in the first row  521  for voltage vector V 4 , which is P 1 . The eleventh switching state of the sequence U A1  is the fourth switching state from the right in the first row  501  for voltage vector V 0 , which is P 1 . 
     The twelfth switching state of the sequence U A1  is the fourth switching state from the right in the first row  511  for voltage vector V 1 , which is P 2 . The thirteenth switching state of the sequence U A1  is the fourth switching state from the right in the first row  521  for voltage vector V 4 , which is P 2 . The fourteenth switching state of the sequence U A1  is the fifth switching state from the right in the first row  501  for voltage vector V 0 , which is P 2 . 
     To construct the second half of the sequence of switching states for phase U, sector A, region  1  (U A1 ) ( 611   b ) over sampling period T S /2 ( 602 ), switching states are obtained from each of the voltage vectors in a clockwise direction. The switching states are obtained from left to right in the first row of switching states assigned to the voltage vectors. 
       FIG. 7  is a waveform diagram illustrating the construction of AC voltage waveform patterns based on the vector space diagram of  FIGS. 3A and 3B  in a manner similar to that described above with respect to  FIG. 6 .  FIG. 7  shows AC voltage waveform patterns for a sequence of switching states, e.g., P 2 , P 1 , O, N 1 , N 2 , of the three phases U, V, and Win regions  1 - 4  of sector A for operational modes  1  and  2 . The AC voltage waveform patterns include waveform patterns U A1  ( 611 ), V A1  ( 712 ), and W A1  ( 713 ), which were constructed based on the switching states obtained from region  1  in sector A. 
     Determination of Turn-on Times 
     PWM waveforms are established once switching turn-on time information is determined based on the following equations. 
     The turn-on time (T) is the sum function of weighted duty cycles T a , T b , and T c . Turn-on time T can be represented by the following equation: 
         T=f ( K   T-ON  of( T   a   ,T   b ,and  T   c )),  (3)
 
     where K T-ON  is a coefficient of time-weighted duty cycles of switching times T a , T b , and T c . Switching times T a , T b , and T c  may be determined based on the ‘average value’ principle, which simplifies the implementation. 
       FIG. 8  is a waveform diagram illustrating generation of turn-on time signals (U A1P2 , U A1P1 , U A1O , U A1N1 ) and switching logic signals (S UA1P2 , S UA1P1 , S UA1O , S UA1N1 , S UA1N2 ) of respective P 2 , P 1 , O, N 1 , N 2  voltage levels for waveform U A1  of sector A and region  1 . As shown in  FIG. 8 , the switching pattern during the first T S /2 interval is repeated inversely in the next T S /2 interval with appropriate segmentation of T a , T b , and T c . 
     Capacitor voltage balancing of multi-level diode-clamped voltage source inverters (VSI) of STATCOM and MVUPS is an issue as it supplies or absorbs both active and reactive power. Capacitor voltage balancing becomes more difficult as the numbers of capacitor to be balanced is increased, e.g., from two (for three-level) to four (for five-level). Thus, switching sequences in opposite sectors (viz., A-D, B-E, and C-F) are selected to be of a complimentary nature to achieve capacitor neutral voltage balancing. The time interval duty cycles T a , T b , T c  are distributed appropriately so as to generate symmetrical PWM waves with capacitor neutral point voltage balancing. 
     The turn-on time T 1  to establish the turn-on time signal (U A1P2 ) of the P 2  voltage level is calculated as follows: 
         T   1   =K   T-ON1-a-A1 ( T   a )+ K   T-ON1-b-A1 ( T   b )+ K   T-ON1-c-A1 ( T   c ),  (3a)
 
     where K T-ON1-a-A1  is a coefficient of time-weighted duty cycle T a , K T-ON1-b-A1  is a coefficient of time-weighted duty cycle T b , and K T-ON1-c-A1  is a coefficient of time-weighted duty cycle T c  of Sector A and Region  1 . 
     The K T-ON1-a-A1  value may be calculated as ⅜ (=⅛+⅛+⅛), the K T-ON1-b-A1  value may be calculated as ⅖ (= 1/10+ 1/10+ 1/10+ 1/10), and the K T-ON1-c-A1  value may be calculated as ⅜ (=⅛+⅛+⅛), as shown in  FIG. 8 . 
     Switching times (T a , T b , and T c ) are determined based on the ‘average value’ principle. Therefore, 
         T   1 =⅜* T   S /3+⅖* T   S /3+⅜* T   S /3=0.76* T   S /2  (3a1)
 
     The turn-on time T 2  to establish the turn-on time signal (U A1P1 ) of the P 1  voltage level is calculated as follows: 
         T   2   =K   T-ON2-a-A1 ( T   a )+ K   T-ON2-b-A1 ( T   b )+ K   T-ON2-c-A1 ( T   c ),  (3b)
 
     where K T-ON2-a-A1  is a coefficient of time-weighted duty cycle T a , K T-ON2-b-A1  is a coefficient of time-weighted duty cycle T b , and K T-ON2-c-A1  is a coefficient of time-weighted duty cycle T c  of Sector A and Region  1 . 
     The K T-ON2-a-A1  value may be calculated as ¼ (=⅛+⅛), the K T-ON2-b-A1  value may be calculated as 3/10 (= 1/10+ 1/10+ 1/10), and the K T-ON2-c-A1  value may be calculated as ¼ (=⅛+⅛), as shown in  FIG. 8 . 
     Switching times (T a , T b , and T c ) are determined based on the ‘average value’ principle. Therefore, 
         T   2 =¼* T   S /3+ 3/10* T   S /3+¼* T   S /3=0.53* T   S /2.  (3b1)
 
     Similarly, T 3  for U A1O  of the O voltage level and T 4  for U A1N1  of the N 1  voltage level are determined for waveform U A1  of Sector A and Region  1 . 
     After the turn-on time values are calculated, they may be stored in memory and used to generate the switching logic signals. As shown in  FIG. 8 , an up/down counter signal  805  starts below switching time T 4  (e.g., time equal to zero), increases through switching times T 4 -T 1  before reaching T S /2, then, after reaching T S /2, decreases through switching times T 1 -T 4 . Switching times T 1 -T 4  are compared to the up/down counter signal  805 , e.g., using comparators  1402 - 1408 , respectively of  FIG. 14 , to obtain the U A1P2  signal  810 , the U A1P1  signal  814 , the U A1O  signal  820 , and the U A1N1  signal  826 . The U A1P2  signal  810  is used as the switching signal S UA1P2 . The U A1P2  signal  810 , the U A1P1  signal  814 , the U A1O  signal  820 , and the U A1N1  signal  826 , are then inverted, e.g., by the inverters  1412 - 1418 , respectively of  FIG. 14 , to obtain the IU A1P2  signal  812 , the IU A1P1  signal  818 , the IU A1O  signal  824 , and the IU A1N1  signal  830 . The IU A1N1  signal  830  is used as the switching signal S UA1N1 . Then, the Boolean AND operation is performed on the IU A1P2  signal  812  and the U A1P1  signal  814 , e.g., using the AND gate  1422  of  FIG. 14 , to obtain the S UA1P1  switching signal  816 . The Boolean AND operation is also performed on the IU A1P1  signal  818  and the U A1O  signal  820 , e.g., using the AND gate  1424  of  FIG. 14 , to obtain the S UA1O  switching signal  822 . The Boolean AND operation is further performed on the IU A1O  signal  824  and the U A1N1  signal  826 , e.g., using the AND gate  1426  of  FIG. 14 , to obtain the S UA1N1  switching signal  828 . 
       FIG. 9  is a waveform diagram illustrating the generation of turn-on time signals (U B1N2 , U B1N1 , U B1O , U B1P1 ) and switching logic signals (S UB1N2 , S UB1N1 , S UB1O , S UB1P1 , S UB1P2 ) of respective N 2 , N 1 , O, P 1 , P 2  voltage levels for waveform U B1  of sector B and Region  1 . As shown in  FIG. 9 , the switching pattern during the first T S /2 interval  601  is repeated inversely in the next T S /2 interval  602  with appropriate segmentation of T a , T b , and T c . 
     The turn-on time value T 1  to establish the turn-on time signal (U B1N2 ) of N 2  voltage level may be calculated as follows: 
         T   1   =K   T-ON1-a-B1 ( T   a )+ K   T-ON1-b-B1 ( T   b )+ K   T-ON1-c-B1 ( T   c ),  (4a)
 
     where K T-ON1-a-B1  is a coefficient of the time-weighted duty cycle T a , K T-ON1-b-B1  is a coefficient of the time-weighted duty cycle T b , and K T-ON1-c-B1  is a coefficient of time-weighted duty cycle T c  of Sector B and Region  1 . 
     The K T-ON1-a-B1  value may be calculated as ⅜ (=⅛+⅛+⅛), the K T-ON1-b-B1  value may be calculated as ⅖ (= 1/10+ 1/10+ 1/10+ 1/10), and the K T-ON1-c-B1  value may be calculated as (⅛+⅛+⅛+⅛=) ½ as shown in  FIG. 9 . 
     Switching times T a , T b , and T c  are determined based on the average value principle. Therefore, 
         T   1 =⅜* T   S /3+⅖* T   S /3+½* T   S /3=0.85* T   S /2  (4a1)
 
     The turn-on time value T 2  to establish turn-on time signal U B1N1  of N 1  voltage level is calculated as follows: 
         T   2   =K   T-ON2-a-B1 ( T   a )+ K   T-ON2-b-B1 ( T   b )+ K   T-ON2-c-B1 ( T   c ),  (4b)
 
     where K T-ON2-a-B1  is a coefficient of time-weighted duty cycle T a , K T-ON2-b-B1  is a coefficient of time-weighted duty cycle T b , and K T-ON2-c-B1  is a coefficient of time-weighted duty cycle T c  of Sector B and Region  1 . 
     The K T-ON2-a-B1  value may be calculated as ¼ (=⅛+⅛), the K T-ON2-b-B1  value may be calculated as 3/10 (= 1/10+ 1/10+ 1/10) and the K T-ON2-c-B1  value may be calculated as ⅜ (=⅛+⅛+⅛) as shown in  FIG. 9 . 
     Switching times T a , T b , and T c  are determined based on the average value principle. Therefore, 
         T   2 =¼* T   S /3+ 3/10* T   S /3+⅜* T   S /3=0.61* T   S /2.  (4b1)
 
     Similarly, T 3  for U B1O  of the O voltage level and T 4  for U B1P1  of the P 1  voltage are determined for waveform U B1  of Sector B and Region  1 . 
     After the turn-on time values are calculated, they may be stored in memory and used to generate the switching logic signals. As shown in  FIG. 9 , the up/down counter signal  805  starts below switching time T 4  (e.g., a time equal to zero), increases through switching times T 4 -T 1  before reaching T S /2, then, after reaching T S /2, decreases through switching times T 1 -T 4 . Switching times T 1 -T 4  are compared to the up/down counter signal  805 , e.g., using comparators  1402 - 1408 , respectively of  FIG. 14 , to obtain the U B1N2  signal  910 , the U B1N1  signal  914 , the U B1O  signal  920 , and the U B1P1  signal  926 . The U B1N2  signal  910  is used as the switching signal S UB1N2 . 
     The U B1N2  signal  910 , the U B1N1  signal  914 , the U B1O  signal  920 , and the U B1P1  signal  926 , are then inverted, e.g., by the inverters  1412 - 1418 , respectively of  FIG. 14 , to obtain the IU B1N2  signal  912 , the IU B1N1  signal  918 , the IU B1O  signal  924 , and the IU B1P1  signal  930 . The IU B1P1  signal  930  is used as the switching signal S UB1P1 . Then, the Boolean AND operation is performed on the IU B1N2  signal  912  and the U B1N1  signal  914 , e.g., using the AND gate  1422  of  FIG. 14 , to obtain the S UB1N1  switching signal  916 . The Boolean AND operation is also performed on the IU B1N1  signal  918  and the U B1O  signal  920 , e.g., using the AND gate  1424  of  FIG. 14 , to obtain the Sumo switching signal  922 . The Boolean AND operation is further performed on the IU B1O  signal  924  and the U B1P1  signal  926 , e.g., using the AND gate  1426  of  FIG. 14 , to obtain the Sump′ switching signal  928 . 
       FIG. 10  is a waveform diagram illustrating the generation of turn-on time signals U A2P2 , U A2P1 , U A2O  and switching logic signals S UA2P2 , S UA2P1 , S UA2O , S UA2N1  of the respective P 2 , P 1 , O, N 1  voltage level for waveform U A2  of Sector A and Region  2 . 
     As shown in  FIG. 10 , the up/down counter signal  805  starts below switching time T 3 , increases through switching times T 3 -T 1  before reaching T S /2, then, after reaching T S /2, decreases through switching times T 1 -T 3 . Switching times T 1 -T 3  are compared to the up/down counter signal  805 , e.g., using comparators  1402 - 1406 , respectively of  FIG. 14 , to obtain the U A2P2  signal  1010 , the U A2P1  signal  1014 , and the U A2O  signal  1020 . The U A2P2  signal  1010  is used as the switching signal S UA2P2 . 
     The U A2P2  signal  1010 , the U A2P1  signal  1014 , and the U A2O  signal  1020 , are then inverted, e.g., by the inverters  1412 - 1416 , respectively of  FIG. 14 , to obtain the IU A2P2  signal  1012 , the IU A2P1  signal  1018 , and the IU A2O  signal  1024 . The IU A2O  signal  1024  is used as the switching signal S UA2N1 . Then, the Boolean AND operation is performed on the IU A2P2  signal  1012  and the U A2P1  signal  1014 , e.g., using the AND gate  1422  of  FIG. 14 , to obtain the S UA2P1  switching signal  1016 . The Boolean AND operation is also performed on the IU A2P1  signal  1018  and the U A2O  signal  1020 , e.g., using the AND gate  1424  of  FIG. 14 , to obtain the S UA2O  switching signal  1022 . 
       FIG. 11  is a waveform diagram illustrating the generation of turn-on time signals U A7P2 , U A7P1  and switching logic signals S UA7P2 , S UA7P1 , S UA7O  of the respective P 2 , P 1 , 0 voltage level for waveform U A7  of Sector A and Region  7 . 
     As shown in  FIG. 11 , the up/down counter signal  805  starts below switching time T 2 , increases through switching times T 2  and T 1  before reaching T S /2, then, after reaching T S /2, decreases through switching times T 1  and T 2 . Switching times T 1  and T 2  are compared to the up/down counter signal  805 , e.g., using comparators  1402  and  1404 , respectively of  FIG. 14 , to obtain the U A7P2  signal  1110  and the U A7P1  signal  1114 . The U A7P2  signal  1110  is used as the switching signal S UA7P2 . 
     The U A7P2  signal  1110  and the U A7P1  signal  1114  are then inverted, e.g., by the inverters  1412  and  1414 , respectively of  FIG. 14 , to obtain the IU A7P2  signal  1112  and the IU A7P1  signal  1118 . The IU A7P1  signal  1118  is used as the switching signal S UA7O . Then, the Boolean AND operation is performed on the IU A7P2  signal  1112  and the U A7P1  signal  1114 , e.g., using the AND gate  1422  of  FIG. 14 , to obtain the S UA7P1  switching signal  1116 . 
       FIG. 12  is a waveform diagram illustrating the generation of turn-on time signal U A13P2  and switching logic signals (S UA13P2 , S UA13P1 ) of the respective P 2 , P 1  voltage level for waveform U A13  of Sector A and Region  13 . 
     As shown in  FIG. 12 , the up/down counter signal  805  starts below switching time T 1  (e.g., time equal to zero), increases through switching time T 1  before reaching T S /2, then, after reaching T S /2, decreases through switching time T 1 . Switching time T 1  is compared to the up/down counter signal  805 , e.g., using comparator  1402 , to obtain the U A13P2  signal  1210 , which is used as the switching signal S UA13P2 . The U A13P2  signal  1210  is then inverted, e.g., by the inverter  1412  of  FIG. 14 , to obtain the IU A13P2  signal  1212 , which is used as the switching signal S UA13P1 . 
       FIG. 13  is a graphical diagram illustrating example turn-on time values T 1 , T 2 , T 3 , T 4  for phase U of all six sectors (Sectors A-F) and Region  1  based on the equations set forth above. As shown, the turn-on time values T 1 , T 2 , T 3 , T 4  are given for the switching states of each of the sectors. For phases V and W, the waveforms are similar to the waveforms in  FIGS. 8-12 , but are mutually phase shifted by the angle 2π/3. 
     PWM Signal Generation 
       FIG. 14  is a digital logic circuit for generating PWM switching signals for a five-level inverter. The digital logic circuit includes a first comparator  1402 , a second comparator  1404 , a third comparator  1406 , a fourth comparator  1408 , a first inverter  1412 , a second inverter  1414 , a third inverter  1416 , a fourth inverter  1418 , a first AND gate  1422 , a second AND gate  1424 , and a third AND gate  1426 . The inverters  1412 - 1418  are digital logic inverters and are connected to outputs of the comparators  1402 - 1408 , respectively. The AND gate  1422  has a first input connected to the output of the first inverter  1412  and a second input connected to the output of the second comparator  1404 , the AND gate  1424  has a first input connected to the output of the second inverter  1414  and a second input connected to the output of the third comparator  1406 ; and the AND gate  1426  has a first input connected to the output of the third inverter  1416  and a second input connected to the output of the fourth comparator  1408 . 
     The first inputs of the comparators  1402 - 1408  receive turn-on time values T 1 , T 2 , T 3 , and T 4 , respectively, and the second inputs of the comparators  1402 - 1408  receive the output from an up/down counter  1401 . The up/down counter  1401  counts over a sampling period T S  from 0 to T S /2 and from T S /2 to 0. The turn-on time values T 1 , T 2 , T 3 , and T 4  are compared with the output of the up/down counter  1401  using digital logic comparators  1402 - 1408  to generate turn-on pulse signals U A/C/EP2 , U A/C/EP1 , U A/C/EO , U A/C/EN1  for A/C/E sectors or U B/D/FN2 , U B/D/FN1 , U B/D/FO , U B/D/FP1  for B/D/F sectors. These turn-on pulse signals are then logically inverted with multiple inverters  1412 - 1418  and logically ANDed by AND gates  1422 - 1426  to generate switching logic signals S UA/C/EP2 , S UA/C/EP1 , S UA/C/EO , S UA/C/EN1 , S UA/C/EN2  for A/C/E sectors or S UB/D/FN2 , S UB/D/FN1 , S UB/D/FO , S UB/D/FP1 , S UB/D/FP2  for B/D/F sectors for all sectors and regions. The comparators  1402 - 1408 , the inverters  1412 - 1418 , and the AND gates  1422 - 1426  may be implemented by a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC) for high-bandwidth fast operation. 
     In embodiments, the number of comparators, inverters, and AND gates may be increased or decreased depending on the number of levels of the multi-level inverter. 
     As shown in  FIG. 8 , turn-on time values T 1 , T 2 , T 3 , T 4  are used to generate switching logic signals S UA1P2 , S UA1P1 , S UA1O , S UA1N1 , S UA1N2 . These switching logic signals are applied to gate drivers that drive respective power transistors, such as IGBT devices, to generate the U A1  waveform of Phase U. Turn-on time values T 1 , T 2 , T 3 , T 4  are used to generate switching logic signals for P 2 , P 1 , O, N 1 , N 2  in that respective order for all A, C, and E odd sectors. 
     As shown in  FIG. 9 , turn-on time values T 1 , T 2 , T 3 , T 4  are used to generate switching logic signals S UB1N2 , S UB1N1 , S UB1O , S UB1P1 , S UB1P2 . These switching logic signals are applied to gate drivers to drive respective power transistors to generate the U B1  waveform of Phase U in sector B of region  1 . Turn-on time values T 1 , T 2 , T 3 , T 4  are used to generate the switching logic signal for N 2 , N 1 , O, P 1 , P 2  in that respective order for all B, D, and F even sectors. 
     Similar signal processing is done for all other regions and V and W phases using the digital logic circuit. The turn-on time values T 1 , T 2 , T 3 , and T 4  are different for Phases V and W. Some portion of the same control circuit is used to generate switching logic signals based on the location of the voltage vector V* as shown in  FIGS. 10, 11, and 12 . 
     In embodiments, a single timer, counting from 0 to T S /2 and then back to 0, and one digital logic circuit is used for all Sectors and Regions. Therefore, the complexity of SVPWM is simplified using the control system according to the present disclosure. 
     Region and Sector Identification of Five-Level Inverter 
       FIG. 15  is a flow diagram of a method for determining region and sector locations of command voltage V*. In the beginning, the command or reference voltage V* and angle Θ e * are sampled. In step  1502 , the current sector location is identified based on the angle Θ e *. For easy implementation and calculation, all angles Θ e * located in sectors B-F are remapped to sector A (Θ e A) according to Table 2 below. Then, the command voltage V* and remapped angle Θ e A are converted into X and Y voltage vector coordinate point values. The X and Y voltage vector coordinate points are compared with a respective XY-line equation in a sector to determine the region. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 θ e * Location 
                 Sector 
                 θ eA   
               
               
                   
                   
               
             
            
               
                   
                 0 ≥ θ e * &lt; π/3 
                 A 
                 =θ e * 
               
               
                   
                 π/3 ≥ θ e * &lt; 2*π/3 
                 B 
                 =(θ e * − π/3) 
               
               
                   
                 2*π/3 ≥ θ e * &lt; π 
                 C 
                 =(θ e * − 2*π/3) 
               
               
                   
                 π ≥ θ e * &lt; 4*π/3 
                 D 
                 =(θ e * − π) 
               
               
                   
                 4*π/3 ≥ θ e * &lt; 5*π/3 
                 E 
                 =(θ e * − 4*π/3) 
               
               
                   
                 5*π/3 ≥ θ e * &lt; 2*π 
                 F 
                 =(θ e * − 5*π/3) 
               
               
                   
                   
               
            
           
         
       
     
     For example, as shown in  FIG. 15 , in step  1504 , it is determined whether the X-Y coordinate points are less than or equal to Y=−1.732X+0.866. If the result of the determination in step  1504  is false, it is determined whether the X-Y coordinate points are greater than or equal to Y=−1.732X−0.866 and the X coordinate point is greater than or equal to 0.5, in step  1505 . If the result of the determination in step  1505  is true, it is determined in step  1506  that the voltage vector V* is located in regions  5 ,  10 ,  11 , or  12 . 
     In step  1508 , it is determined whether the X-Y coordinate points are less than or equal to Y=−1.732X+1.299. If the result of the determination in step  1508  is true, the voltage vector is determined to be in region  5 , in step  1510 . If the result of the determination in step  1508  is false, it is determined whether the X-Y coordinate points are greater than or equal to Y=−1.732X−1.299 and X is greater than or equal to 0.75, in step  1512 . If the result of the determination in step  1512  is true, the voltage vector is determined to be in region  10 , in step  1514 . If the result of the determination in step  1512  is false, it is determined whether the Y coordinate point is greater than or equal to Y=0.2165, in step  1516 . If the result of the determination in step  1516  is true, the voltage vector is determined to be in region  12 , in step  1518 . If the result of the determination in step  1516  is false, the voltage vector is determined to be in region  11 , in step  1520 . 
     If the result of the determination in step  1505  is false, it is determined whether the Y coordinate point is greater than or equal to Y=0.433 in step  1522 . If the result of the determination in step  1522  is true, it is determined in step  1524  that the voltage vector V* is located in regions  9 ,  14 ,  15 , or  16 . In step  1526 , it is determined whether the X-Y coordinate points are greater than or equal to Y=1.732X−0.433. If the result of the determination in step  1526  is true, the voltage vector is determined to be in region  14 , in step  1528 . If the result of the determination in step  1526  is false, it is determined whether the X-Y coordinate points are less than or equal to Y=−1.732X+1.299, in step  1530 . If the result of the determination in step  1530  is true, the voltage vector is determined to be in region  9 , in step  1532 . If the result of the determination in step  1530  is false, it is determined whether the Y coordinate point is greater than or equal to Y=0.6495, in step  1534 . If the result of the determination in step  1534  is true, the voltage vector is determined to be in region  16 , in step  1536 . If the result of the determination in step  1534  is false, the voltage vector is determined to be in region  15 , in step  1538 . 
     If the result of the determination in step  1522  is false, it is determined in step  1540  that the voltage vector V* is located in regions  6 ,  7 ,  8 , or  13 . In step  1542 , it is determined whether the X-Y coordinate points are less than or equal to Y=1.732X−0.433. If the result of the determination in step  1542  is true, the voltage vector is determined to be in region  8 , in step  1544 . If the result of the determination in step  1542  is false, it is determined whether the X-Y coordinate points are greater than or equal to Y=−1.732X+1.299, in step  1546 . If the result of the determination in step  1546  is true, the voltage vector is determined to be in region  13 , in step  1548 . If the result of the determination in step  1546  is false, it is determined whether the Y coordinate point is less than or equal to Y=0.2165, in step  1550 . If the result of the determination in step  1550  is true, the voltage vector is determined to be in region  6 , in step  1552 . If the result of the determination in step  1550  is false, the voltage vector is determined to be in region  7 , in step  1554 . 
     If the result of the determination in step  1504  is true, it is determined in step  1556  that the voltage vector V* is located in regions  1 ,  2 ,  3 , or  4 . In step  1558 , it is determined whether the X-Y coordinate points are less than or equal to Y=−1.732X+0.433. If the result of the determination in step  1558  is true, the voltage vector is determined to be in region  1 , in step  1560 . If the result of the determination in step  1558  is false, it is determined whether the X-Y coordinate points are greater than or equal to Y=−1.732X−0.433 and the X coordinate point is greater than or equal to 0.25, in step  1562 . If the result of the determination in step  1562  is true, the voltage vector is determined to be in region  2 , in step  1564 . If the result of the determination in step  1562  is false, it is determined whether the Y coordinate point is greater than or equal to Y=0.2165, in step  1566 . If the result of the determination in step  1566  is true, the voltage vector is determined to be in region  4 , in step  1568 . If the result of the determination in step  1566  is false, the voltage vector is determined to be in region  3 , in step  1570 . 
     SVPWM Controller 
     Once turn-on time values T 1 , T 2 , T 3 , T 4  have been calculated for all P 2 , P 1 , O, N 1 , N 2  states of all phases, it is possible to evaluate them in real time with the help of a DSP and establish the Space Vector PWM waves with the help of FPGA-based single timer and single digital logic circuit as shown in  FIG. 14 . 
       FIG. 16  is a block diagram illustrating a control system for a five-level diode clamped inverter. The control system includes a processor, such as a digital signal processor (DSP), which is used to implement blocks  1602  and  1604 . Blocks  1602  and  1604  are easily implemented to carry out the SVPWM control strategy. 
     In block  1602 , the processor samples a reference voltage vector V* and an angle Θ e *, and identifies a sector and region based on the sampled reference voltage vector V* and angle Θ e *. In block  1604 , the processor selects predefined switching sequences and pre-calculated turn-on signal values T 1 , T 2 , T 3 , T 4  based on the identified sector and region location of the reference voltage vector V*. 
     The control system also includes a digital logic circuit  1606 , such as an FPGA, and an up/down counter for generating PWM switching signals. The digital logic circuit  1606 , such as the digital logic circuit of  FIG. 14 , generates PWM switching signals for the power transistor drivers based on the turn-on signal values T 1 , T 2 , T 3 , T 4  and the selected switching sequence. In embodiments, less expensive DSPs and FPGAs may be used because the overall control implementation is divided between a DSP and an FPGA circuit. 
     As described above, the overall control operation is divided into multiple modes (e.g., Modes  1 - 4 ) in terms of sector and region locations. A single digital logic circuit  1606  is used to generate switching logic signals for all the regions and sectors. This simplifies the control system and, in turn, reduces time to implement at minimum cost. Also, to simplify the control system, one up/down counter  1608  (counting from 0 to T S /2 and then from T S /2 to 0) with sampling period T S  may be utilized. 
       FIG. 17  is a flow diagram of a method of controlling a multi-level inverter according to embodiments of the present disclosure. After starting in step  1701 , a sector location is identified based on an actual angle of a reference voltage vector, in step  1702 . In step  1704 , the actual angle is converted into a converted angle located in a first sector and, in step  1706 , a region location is identified based on the magnitude of the reference voltage vector and the converted angle in the first sector. In step  1708 , a switching sequence and a plurality of turn-on signal values are selected based on the corresponding region location in the actual sector of the reference voltage vector. In step  1710 , turn-on signal values are transmitted to second inputs of the plurality of comparators to generate switching signals for a power transistor driver of a multi-level inverter. In step  1712 , each of the plurality of turn-on signals are compared to a digital up/down counter signal to obtain a plurality of comparison signals including a first comparison signal and a second comparison signal. In step  1714 , the plurality of comparison signals are inverted to obtain a plurality of inverted signals including a first inverted signal. Then, before ending in step  1717 , a logical AND operation is performed on the first inverted signal and the second comparison signal to obtain a switching signal for a corresponding driver that drives a power transistor of a multi-level inverter in step  1716 . 
     While several embodiments of the disclosure have been shown in the drawings and/or discussed herein, it is not intended that the disclosure be limited thereto, as it is intended that the disclosure be as broad in scope as the art will allow and that the specification be read likewise. Therefore, the above description should not be construed as limiting, but merely as exemplifications of particular embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the claims appended hereto.