Patent Publication Number: US-9898029-B2

Title: Temperature-compensated reference voltage generator that impresses controlled voltages across resistors

Description:
BACKGROUND 
     Field 
     Aspects of the present disclosure relate generally to generating temperature-compensated reference voltages, and more particularly, to a temperature-compensated reference voltage generator that generates temperature-compensated currents by impressing controlled voltages across resistors. 
     Background 
     A bandgap reference voltage source generates a reference voltage V REF  that is substantially constant over a defined (very wide) temperature range. In discrete circuit or integrated circuit (IC) applications, the reference voltage V REF  is used in many applications, such as for voltage regulation where a supply voltage is regulated based on the reference voltage. 
     The bandgap reference voltage generated is typically around 1.2 Volts because the source of the voltage is based on the 1.22 eV bandgap of silicon at zero (0) degree Kelvin. As the bandgap reference voltage V REF  is about 1.2 Volts, a bandgap reference voltage source requires a supply voltage greater than the 1.2 Volts, such as a supply voltage of 1.4 Volts to accommodate, for example, a 200 millivolt (mV) drain-to-source voltage Vds of a field effect transistor (FET) used for biasing the bandgap reference voltage. 
     Currently, because of continued reduction in the size of FETs used in ICs and the further need to reduce power consumption, many circuits operate with supply voltages below the bandgap voltage of 1.2 Volts. In response to such need, bandgap reference voltage sources have been designed to operate with supply voltage below 1.2 Volts. 
     SUMMARY 
     The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of such embodiments. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later. 
     An aspect of the disclosure relates to an apparatus configured to generate a temperature-compensated reference voltage. The apparatus includes first and second set of resistors; a current generator configured to generate a first temperature-compensated current through the first set of one or more resistors, wherein a first voltage is generated across the first set of one or more resistors based on the first temperature-compensated current; a control circuit configured to generate a second voltage across the second set of one or more resistors, wherein the second voltage is based on the first voltage, and wherein a second temperature-compensated current is generated through the second set of resistors based on the second voltage; and a third set of one or more resistors through which the second temperature-compensated current flows, wherein the temperature-compensated reference voltage is generated across the third set of one or more resistors based on the second temperature-compensated current. 
     Another aspect of the disclosure relates to a method for generating a temperature-compensated reference voltage. The method includes generating a first temperature-compensated current through a first set of one or more resistors, wherein a first voltage is generated across the first set of one or more resistors based on the first temperature-compensated current; generating a second voltage across a second set of one or more resistors, wherein the second voltage is based on the first voltage, and wherein a second temperature-compensated current is generated through the second set of resistors based on the second voltage; and applying the second temperature-compensated current through a third set of one or more resistors, wherein the temperature-compensated reference voltage is generated across the third set of one or more resistors. 
     Another aspect of the disclosure relates to an apparatus configured to generate a temperature-compensated reference voltage. The apparatus comprises means for generating a first temperature-compensated current through a first set of one or more resistors, wherein a first voltage is generated across the first set of one or more resistors based on the first temperature-compensated current; means for generating a second voltage across a second set of one or more resistors, wherein the second voltage is based on the first voltage, and wherein a second temperature-compensated current is generated through the second set of resistors based on the second voltage; and means for applying the second temperature-compensated current through a third set of one or more resistors, wherein the temperature-compensated reference voltage is generated across the third set of one or more resistors. 
     To the accomplishment of the foregoing and related ends, the one or more embodiments include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more embodiments. These aspects are indicative, however, of but a few of the various ways in which the principles of various embodiments may be employed and the description embodiments are intended to include all such aspects and their equivalents. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a schematic diagram of an exemplary apparatus for generating a temperature-compensated reference voltage in accordance with an aspect of the disclosure. 
         FIG. 2  illustrates a schematic diagram of another exemplary apparatus for generating a temperature-compensated reference voltage in accordance with another aspect of the disclosure. 
         FIG. 3  illustrates a schematic diagram of yet another exemplary apparatus for generating a temperature-compensated reference voltage in accordance with another aspect of the disclosure. 
         FIG. 4  illustrates a schematic diagram of still another exemplary apparatus for generating a temperature-compensated reference voltage in accordance with another aspect of the disclosure. 
         FIG. 5  illustrates a flow diagram of an exemplary method of generating a temperature-compensated reference voltage in accordance with another aspect of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts. 
       FIG. 1  illustrates a schematic diagram of an exemplary apparatus  100  for generating a temperature-compensated reference voltage V REF  in accordance with an aspect of the disclosure. 
     The apparatus  100  includes a sub-circuit  110  for generating a complementary to absolute temperature (CTAT) current I CTAT  (e.g., a negative temperature coefficient current). The sub-circuit  110  includes field effect transistor (FET) M 1 , resistor R 4 , and diode D 1 . The FET M 1 , which may be implemented with a p-channel metal oxide semiconductor (PMOS) FET, is coupled in series with the parallel-coupling of resistor R 4  and diode D 1  between a first voltage rail (e.g., Vdd) and a second voltage rail (e.g., ground). The FET M 1 , serving as a current source, is configured to generate a current I 1 , which is split between the resistor R 4  and diode D 1 . The voltage V A  formed across the diode D 1  has a negative temperature coefficient, e.g., a CTAT voltage. The voltage V A  is also across the resistor R 4 . Thus, an I CTAT  current is formed through resistor R 4 . 
     The apparatus  100  includes a sub-circuit  120  for generating a proportional to absolute temperature (PTAT) current. The sub-circuit  120  includes resistors R 5  and R 6 , a diode bank  125  of N parallel diodes D 21  to D 2 N, an operational amplifier (Op Amp)  130 , and FET M 2 . The FET M 2 , resistor R 5 , and diode bank  125  are coupled in series between Vdd and ground. The FET M 2 , which may be implemented with a PMOS FET, is also coupled in series with resistor R 6  between Vdd and ground. The Op Amp  130  includes a negative input terminal configured to receive the voltage V A  across the diode D 1 , a positive input terminal configured to receive a voltage V B  across the series connection of the resistor R 5  and diode bank  125 , and an output terminal coupled to the gates of FETs M 1  and M 2 . 
     Through negative feedback control, the Op Amp  130  controls the currents I 1  and I 2  through the FETs M 1  and M 2  via their respective gate voltages, such that voltage V B  is based on voltage V A  (e.g., substantially equal to each other, V B =V A ). Since the FETs M 1  and M 2  are configured to have the same size and also have their gates coupled together to form a current mirror, the currents I 1  and I 2  are also substantially the same. Since voltages V A  and V B  are the same, and resistors R 4  and R 6  are configured to have substantially the same resistance, the current through resistor R 6  is also a I CTAT  current, e.g., substantially the same as the current I CTAT  through resistor R 4 . 
     Accordingly, the current through diode D 1  is substantially the same as the combined current through the N parallel diodes D 21  to D 2 N of the diode bank  125 . The diodes D 21  and D 2 N of the diode bank  125  are each configured to be substantially the same as the diode D 1 . Thus, because the same current through diode D 1  is split among N diodes of the diode bank  125 , the current density through each of the diodes of the diode bank  125  is a factor of N less than the current density through diode D 1 . Because of the difference in current density, the diode bank  125  produces a CTAT voltage that is different than the CTAT voltage across diode D 1 . As a result, a voltage is produced across the resistor R 5  that has a positive temperature coefficient (e.g., a PTAT voltage). This produces a current I PTAT  through resistor R 5 . 
     The current I 2  produced by FET M 2  is a combination (e.g., sum) of the currents I PTAT  and I CTAT . Thus, by proper selection of the resistances of R 4 , R 5 , and R 6 , the current I 2  may be configured to be substantially constant over a defined range of temperatures. 
     The apparatus  100  further includes a sub-circuit  140  configured to generate the temperature-compensated reference voltage V REF  based on the temperature-compensated current I 2  through M 2 . The sub-circuit  140  includes FET M 3  and resistor R 1 . The temperature-compensated current I 2  is mirrored via the current mirror configuration of FETs M 2  and M 3  (e.g., the FETs are configured to have substantially the same size and the same gate-to-source voltage Vgs) to form a temperature-compensated current I 3 . The FET M 3 , which may also be implemented with a PMOS FET, is coupled in series with a resistor R 7  between Vdd and ground, which results in the temperature-compensated current I 3  flowing through resistor R 7  to form the temperature-compensated reference voltage V REF . 
     Thus, in order for the apparatus  100  to properly operate, the currents I 1 , I 2 , and I 2  generated by the current sources M 1 , M 2 , and M 3  should be substantially the same. However, due to the supply voltage Vdd being relatively low (e.g., sub 1V), the drain-to-source voltage Vds of FETs M 1  and M 2  may become relatively small due to the voltages V A  and V B  increasing with temperature reduction. In such case, the Vds of FETs M 1  and M 2  may be significantly smaller than the Vds of FET M 3 ; and hence, the FETs M 1  and M 2  may have output impedances different than the output impedance of FET M 3 . This produces a current mismatch between current I 3  and currents I 1  and I 2 , which produces error in the reference voltage V REF . 
     Additional mismatch among the currents I 1 , I 2 , and I 3  may be caused by mismatch in the FETs M 1 , M 2 , and M 3  due to process variation. 
       FIG. 2  illustrates a schematic diagram of another exemplary apparatus  200  for generating a temperature-compensated reference voltage V REF  in accordance with another aspect of the disclosure. The apparatus  200  is configured to address the problem associated with the FETs M 1 , M 2 , and M 3  having different drain-to-source voltages Vds; and hence, different output impedances which produce current mismatch among currents I 1 , I 2 , and I 3 . The apparatus  200  is similar to that of apparatus  100 , but includes a modified reference voltage V REF  generating sub-circuit  240  having an additional control circuit to ensure that the voltages across the current source FETs M 1 , M 2 , and M 3  are substantially the same. 
     In particular, in addition to the FET M 3  and resistor R 7 , the sub-circuit  240  includes an Op Amp  245  and a FET M 4 . The Op Amp  245  includes a positive input configured to receive the voltage V B , a negative input coupled to the drain of FET M 3 , and an output coupled to a gate of FET M 4 . The FET M 4 , which may be implemented with a PMOS FET, is coupled between FET M 3  and resistor R 7 . The reference voltage V REF  is generated at the drain of FET M 4 . 
     Due to negative feedback, the Op Amp  245  controls the gate of FET M 4  such that voltage V C  is substantially the same as voltage V B . Thus, the voltages across the current source FETs M 1 , M 2 , and M 3  are substantially the same. 
     Although this is an improvement over the apparatus  100  shown in  FIG. 1 , there is still error in the reference voltage V REF  due to mismatch between the current source FETs M 1 , M 2 , and M 3 . That is, even though the voltages across the FETs M 1 , M 2 , and M 3  may be made substantially the same through the negative feedback control provided by Op Amps  130  and  245  and FET M 4 , the currents I 1 , I 2 , and I 2  respectively through the FETs M 1 , M 2 , and M 3  may be different due to difference in their transconductance gains caused by process variations. This results in different currents I 1 , I 2 , and I 3 , which produces error in the reference voltage V REF . This error becomes more prevalent as the supply voltage Vdd is reduced. 
       FIG. 3  illustrates a schematic diagram of yet another exemplary apparatus  300  for generating a temperature-compensated reference voltage V REF  in accordance with another aspect of the disclosure. The concept behind the apparatus  300  stems from the fact that resistors may be made more consistent than FETs; and thus, better matching between the resistors may be achieved as compared to FETs. Accordingly, the concept behind apparatus  300  is to replace the current sources M 1 , M 2 , and M 3  with respective resistors R 1 , R 2 , and R 3  (having substantially equal resistance) and apply negative feedback control using Op Amps  130  and  245  to impress substantially the same voltages across the resistors R 1 , R 2 , and R 3 . This ensures that the currents I 1 , I 2 , and I 3  generated respectively through the resistors R 1 , R 2 , and R 3  are substantially the same, which leads to significant reduction in error in the reference voltage V REF . 
     In particular, the apparatus  300  includes a sub-circuit  310  configured to generate a I CTAT  current, a sub-circuit  320  configured to generate a I PTAT  current, and a sub-circuit  340  configured to generate a temperature-compensated reference voltage V REF . The sub-circuits  310 ,  320 , and  340  are respectively similar to sub-circuits  110 ,  120 , and  240  of apparatus  200 , but differ in that resistors R 1 , R 2 , and R 3  are substituted for the current source FETs M 1 , M 2 , and M 3 , respectively. In addition, the apparatus  300  further includes a FET M 10 , which may be implemented with a PMOS FET, coupled between the supply voltage rail Vdd and the resistors R 1 , R 2 , and R 3 . The output of the Op Amp  130  is coupled to the gate of FET M 10  to control a voltage V SB  at a node common to resistors R 1 , R 2 , and R 2 . This is called single-point biasing, where the negative feedback operates on a bias voltage (e.g., V SB ) at a single node. 
     Accordingly, the negative feedback control provided by Op Amp  130  forces the voltage V A  and V B  to be substantially the same. Thus, the voltage drops across the resistors R 1  and R 2  are equal to each other (V SB −V A =V SB −V B  because V A =V B ). Similarly, the negative feedback control produced by Op Amp  245  forces the voltages V B  and V C  to be substantially the same. Thus, the voltage drops across the resistors R 2  and R 3  are equal to each other (V SB −V B =V SB −V C  because V B =V C ). 
     Since the voltages across the resistors R 1 , R 2 , and R 3  are substantially the same, and the resistors R 1 , R 2 , and R 3  may be fabricated to have substantially the same resistance, the temperature-compensated currents I 1 , I 2 , and I 3  are substantially the same. This results in a significant reduction in the error in generating the reference voltage V REF . 
       FIG. 4  illustrates a schematic diagram of still another exemplary apparatus  400  for generating a temperature-compensated reference voltage V REF  in accordance with another aspect of the disclosure. The apparatus  400  may be an example of a more detailed implementation of reference voltage source  300 . The apparatus  400  includes a sub-circuit  410  configured to generate a I CTAT  current, a sub-circuit  420  configured to generate a I PTAT  current, and a sub-circuit  440  configured to generate a temperature-compensated reference voltage V REF . With some differences as noted below, the sub-circuits  410 ,  420 , and  440  are similar to sub-circuits  310 ,  320 , and  340  of apparatus  300 , respectively. The remaining circuitry of apparatus  400 , namely Op Amps  130  and  245  and FET M 10 , are substantially the same as that of apparatus  300 . 
     The differences between the apparatuses  400  and  300  are as follows: (1) resistor R 1  is replaced by series-coupled resistors R 11  and R 12 ; (2) resistor R 2  is replaced by series-coupled resistors R 21  and R 22 ; (3) resistor R 3  is replaced by series-coupled resistors R 31  and R 32 ; (4) resistor R 4  is replaced by series-coupled resistors R 41 -R 48 ; (5) resistor R 5  is replaced by a pair of series-coupled resistors R 51 -R 52  and R 53 -R 54  coupled in parallel with each other; (6) resistor R 6  is replaced by series-coupled resistors R 61 -R 68 ; (7) resistor R 7  is replaced by series-coupled resistors R 71 -R 74 ; (8) diode D 1  is replaced with diode-connected bipolar transistor Q 1 ; and (9) the diode bank  125  of parallel diodes D 21 -D 2 N is replaced by a diode bank  425  of parallel diode-connected bipolar transistors Q 21 -Q 2 N. 
     The principle of operation of apparatus  400  is essentially the same as that of apparatus  300 . The reasons for multiple resistors in apparatus  400  in place of single resistors in apparatus  300  are two folds: (1) Due to process requirements (e.g., limitations on the length-to-width ratio of a resistor), multiple resistors (each compliant with the process requirement) may need to be connected in series or in parallel to achieve the desired resistance; and (2) multiple resistors allow for process variations to be statistically averaged out for better control of the total resistance of each set of resistors. Note that the number and/or combination of resistors that replace each single resistor may vary in other implementations. It should be apparent to one of skill in the art that the concept disclosed herein is not limited to the particular implementation illustrated in  FIG. 4 . 
       FIG. 5  illustrates a flow diagram of an exemplary method  500  for generating a temperature-compensated reference voltage V REF  in accordance with another aspect of the disclosure. The method  500  includes generating a first temperature-compensated current through a first set of one or more resistors, wherein a first voltage is generated across the first set of one or more resistors based on the first temperature-compensated current (block  502 ). 
     With reference to  FIGS. 3-4 , examples of means for generating a first temperature-compensated current I 2  include the circuitry having: (1) resistor(s) R 1  (or R 11 -R 12 ), R 2  (or R 21 -R 22 ), R 4  (or R 41 -R 48 ), R 5  (or R 51 -R 54 ), and R 6  (or R 61 -R 68 ); (2) diode D 1  or diode-connected transistor Q 1 ; (3) diode bank  125  of diodes D 21 -D 2 N coupled in parallel or diode bank  425  of diode-connected transistors Q 21 -Q 2 N; and (4) control circuit including Op Amp  130  and transistor (e.g., FET) M 10 . The first temperature-compensated current I 2  flows through a first set of one or more resistor(s) R 2  or R 21 -R 22 , wherein a first voltage (V SB −V B ) is generated across the first set of one or more resistor(s) R 2  or R 21 -R 22  based on the first temperature-compensated current I 2 . 
     The method  500  includes generating a second voltage across a second set of one or more resistors, wherein the second voltage is based on the first voltage, and wherein a second temperature-compensated current is generated through the second set of resistors based on the second voltage (block  504 ). 
     With reference to  FIGS. 3-4 , examples of means for generating a second voltage include Op Amp  245  and transistor (e.g., FET) M 4 . Thus, the second voltage (V SB −V C ) is generated across the second set of one or more resistor(s) R 3  or R 31 -R 32 , wherein the second voltage (V SB −V C ) is based (e.g., substantially equal to) the first voltage (V SB −V B ), and wherein the second temperature-compensated current I 3  is generated through the second set of resistor(s) R 3  or R 31 -R 32  based on the second voltage (V SB −V C ). 
     The method  500  includes applying the second current through a third set of one or more resistors, wherein a temperature-compensated reference voltage is generated across the third set of one or more resistors (block  506 ). 
     With reference to  FIGS. 3-4 , examples of means for applying the second current through a third set of one or more resistors include the series-connection of the resistor R 3  or R 31 -R 32 , FET M 4 , and resistor(s) R 7  or R 71 -R 74 . Thus, the second current I 3  is applied through the third set of one or more resistor(s) R 7  or R 71 -R 74  to generate a temperature-compensated reference voltage V REF  across the third set of one or more resistor(s) R 7  or R 71 -R 74 . 
     The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.