Patent Publication Number: US-11650248-B2

Title: Electrical current measurement system

Description:
TECHNICAL FIELD 
     Embodiments of the subject matter described herein relate generally to a test system for measuring electrical current consumed by a device under test, and to a current-isolated voltage regulator suitable for use in the test system. 
     BACKGROUND 
     Electronic devices, systems, and components are routinely subjected to electrical tests during manufacturing and/or in an ongoing manner after deployment. For example, an electronic device can be tested to measure the amount of electrical current it consumes during different operating modes. An unusually low or high measured current can be an indicator of a fault, error, or manufacturing defect. 
     A low power consumption electronic device, such as a battery powered medical device, may utilize a switch-mode power supply (SMPS) that provides an as-needed switching scheme at low load currents that occur during the device&#39;s standby mode. In such a device, the switching during standby mode occurs on an as-needed basis. Accordingly, the switching period is often increased to a point where input filter capacitors become ineffective at smoothing the current. This results in a discontinuous input current that typically resembles a pulse train having high dynamic range. In this regard, the non-switching currents between “wake up” current pulses may be four to five orders of magnitude less than the switching pulses. As the switching period increases for a given pulse width (i.e., the duty cycle decreases), the overall current measurement accuracy becomes increasingly affected by the non-switching current. The combination of these factors adversely impact the effectiveness and accuracy of most readily available electrical current measurement systems, which are primarily designed to measure continuous current and/or current having a low dynamic range. As a result, measurement accuracy of discontinuous electrical current with high dynamic range suffers when such devices are tested with conventional (and economically feasible) current measurement equipment. 
     A test system that measures electrical current may include a voltage regulator to provide operating power to the device under test. A conventional low-dropout or linear voltage regulator utilizes the regulator input voltage to source certain components, such as an internal voltage reference and an error amplifier. Consequently, the input current of this type of voltage regulator will always be higher than the output current. Although this type of voltage regulator is appropriate in some applications, it may not be suitable in certain applications where it is desirable to have the output current match the input current. 
     BRIEF SUMMARY 
     Disclosed herein is a test system and related current measurement technique that can accurately and effectively measure the electrical current consumed by a device under test, where the current exhibits discontinuous and high dynamic range characteristics. Also disclosed herein are linear voltage regulators that operate in a current-isolated manner such that the regulator output current closely matches the regulator input current. Other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background. 
     A test system for measuring electrical current consumption of a device under test (DUT) is disclosed herein. The test system includes: a power capacitor with a power terminal and a ground terminal, and configured to provide capacitor voltage at the power terminal; a voltage regulator having a regulator input terminal and a regulator output terminal, and configured to generate a DUT operating voltage at the regulator output terminal based on an input voltage at the regulator input terminal; a switching circuit to regulate electrical connections between a direct current (DC) voltage source, the power capacitor, and the voltage regulator; and a controller coupled to the power capacitor, the voltage regulator, and the switching circuit. The controller is configurable to: control the switching circuit to place the test system into a charging state to charge the power capacitor with the DC voltage source; after the power capacitor has reached a charged voltage, control the switching circuit to place the test system into a measurement state such that the power capacitor provides the capacitor voltage to the voltage regulator; and after the power capacitor has reached a discharged voltage in response to loading, calculate electrical current provided by the power capacitor in a time period recorded during operation of the test system in the measurement state. The electrical current is calculated based on a sampled value of the charged voltage, a sampled value of the discharged voltage, and discharge characteristics of the power capacitor. 
     In accordance with certain embodiments, a test system for measuring electrical current consumption of a DUT includes: a power capacitor with a power terminal and a ground terminal, and configured to provide capacitor voltage at the power terminal; a voltage regulator with a regulator input terminal and a regulator output terminal, and configured to generate a DUT operating voltage at the regulator output terminal based on an input voltage at the regulator input terminal; a first switching element between a DC voltage source and the regulator input terminal; a second switching element between the DC voltage source and the power terminal of the power capacitor; and a controller coupled to the power capacitor, the voltage regulator, the first switching element, and the second switching element. The controller is configurable to: close the first and second switching elements to charge the power capacitor with the DC voltage source; after the power capacitor has reached a charged voltage, open the first and second switching elements such that the power capacitor provides the capacitor voltage to the voltage regulator; record a measurement start time associated with opening of the first switching element when the second switching element is open; after the power capacitor has reached a discharged voltage in response to loading, close the first switching element; record a measurement end time associated with closing of the first switching element when the second switching element is open; and calculate electrical current provided by the power capacitor between the measurement start time and the measurement end time, based on a sampled value of the charged voltage of the power capacitor, a sampled value of the discharged voltage of the power capacitor, and discharge characteristics of the power capacitor. 
     Also disclosed herein is an automated method of measuring electrical current of a DUT with a test system having a power capacitor, a voltage regulator to generate a DUT operating voltage for the DUT, a switching circuit to regulate electrical connections between a direct current (DC) voltage source, the power capacitor, and the voltage regulator, and a processor-based controller. The method involves: automatically controlling the switching circuit with the controller to place the test system into a charging state, such that the DC voltage source charges the power capacitor; after the power capacitor has reached a charged voltage, automatically controlling the switching circuit with the controller to transition the test system into a measurement state, such that the power capacitor provides capacitor voltage to the voltage regulator while the test system is in the measurement state, wherein the DUT is coupled to a regulator output terminal of the voltage regulator while the test system is in the measurement state; recording, with the controller, a measurement start time; after the power capacitor has reached a discharged voltage in response to operation of the DUT, automatically controlling the switching circuit with the controller to transition the test system into a post-measurement state; recording, with the controller, a measurement end time; calculating electrical current consumed by the DUT between the measurement start time and the measurement end time, based on a sampled value of the charged voltage, a sampled value of the discharged voltage, and discharge characteristics of the power capacitor; and generating the calculated electrical current as an output of the test system. 
     A linear voltage regulator is also disclosed herein. The linear voltage regulator includes: an input voltage terminal for a regulator input voltage; an output voltage terminal for a regulator output voltage; a series pass field-effect transistor coupled between the input voltage terminal and the output voltage terminal; a voltage reference source to provide a reference voltage for the linear voltage regulator, the voltage reference source powered by an independent voltage supply that is isolated from the input voltage terminal; a buffer amplifier with a buffer output, a positive buffer input coupled to the output voltage terminal, and a negative buffer input coupled to the buffer output, the buffer amplifier powered by the independent voltage supply; a feedback divider network coupled between the buffer output and a ground terminal, the feedback divider network providing a scaled output voltage at a divider output; and an error amplifier with an error output coupled to the transistor, a positive error input coupled to the divider output to receive the scaled output voltage, and a negative error input coupled to the voltage reference source to receive the reference voltage, the error amplifier powered by the independent voltage supply. Output of the error amplifier is based on a difference between the reference voltage and the scaled output voltage. The output of the error amplifier controls impedance of the transistor to adjust a regulator output voltage at the output voltage terminal. 
     Another embodiment of a linear voltage regulator is also disclosed. The linear voltage regulator includes: an input voltage terminal for a regulator input voltage; an output voltage terminal for a regulator output voltage; a series pass field-effect transistor coupled between the input voltage terminal and the output voltage terminal; a buffer amplifier with a buffer output, a positive buffer input coupled to the output voltage terminal, and a negative buffer input coupled to the buffer output, the buffer amplifier powered by an independent voltage supply that is isolated from the input voltage terminal; a feedback divider network coupled between the buffer output and a ground terminal, the feedback divider network providing a scaled output voltage at a divider output; an analog-to-digital converter (ADC) with an analog voltage input coupled to the divider output to receive the scaled output voltage, and having a first digital output interface to provide a digital representation of the scaled output voltage, the ADC powered by the independent voltage supply; a digital processing core having a first digital input interface coupled to the first digital output interface, and having a second digital output interface, the digital processing core configured to generate a digital control output at the second digital output interface based on a difference between the digital representation of the scaled output voltage and a digital representation of a reference voltage, the digital processing core powered by the independent voltage supply; and a digital-to-analog converter (DAC) with a second digital input interface coupled to the second digital output interface, and having an analog output coupled to the transistor. The DAC is configured to convert the digital control output into an analog control voltage and to provide the analog control voltage at the analog output. The analog control voltage controls impedance of the transistor to adjust a regulator output voltage at the output voltage terminal. The DAC is powered by the independent voltage supply. 
     A linear voltage regulator system is also disclosed herein. The system includes: an input voltage terminal for a regulator input voltage; an output voltage terminal for a regulator output voltage; a reference voltage terminal for a reference voltage; a series pass field-effect transistor coupled between the input voltage terminal and the output voltage terminal; and an error amplifier with an error output coupled to the transistor, a positive error input directly connected to the output voltage terminal to receive the regulator output voltage, and a negative error input coupled to the reference voltage terminal to receive the reference voltage. The error amplifier is powered by an independent voltage supply that is isolated from the input voltage terminal. An output of the error amplifier is based on a difference between the reference voltage and the regulator output voltage. The output of the error amplifier controls impedance of the transistor to adjust the regulator output voltage at the output voltage terminal. 
     This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete understanding of the subject matter may be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures. 
         FIG.  1    is a block diagram that depicts an embodiment of a test system in a typical testing environment; 
         FIG.  2    is a schematic diagram of an embodiment of a test system connected to a device under test; 
         FIG.  3    is a flow chart that illustrates an embodiment of an automated method of measuring electrical current of a device under test; 
         FIG.  4    is a graph that includes plots of voltage levels over time, as sampled during a typical current measurement test performed by the test system shown in  FIG.  2   ; and 
         FIGS.  5 - 7    are schematic diagrams of embodiments of a linear voltage regulator having isolated supply current. 
     
    
    
     DETAILED DESCRIPTION 
     The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description. 
     Techniques and technologies may be described herein in terms of functional and/or logical block components, and with reference to symbolic representations of operations, processing tasks, and functions that may be performed by various computing components or devices. Such operations, tasks, and functions are sometimes referred to as being computer-executed, processor-based, software-implemented, computer-implemented, or the like. It should be appreciated that the various block components shown in the figures may be realized by any number of hardware, software, and/or firmware components configured to perform the specified functions. For example, an embodiment of a system or a component may employ various integrated circuit components, e.g., memory elements, digital signal processing elements, logic elements, look-up tables, or the like, which may carry out a variety of functions under the control of one or more microprocessors or other control devices. 
     When implemented in software or firmware, various elements of the systems described herein are essentially the code segments or instructions that perform the various tasks. In certain embodiments, the program or code segments are stored in a tangible processor-readable medium, which may include any medium that can store or transfer information. Examples of a non-transitory and processor-readable medium include an electronic circuit, a semiconductor memory device, a ROM, a flash memory, an erasable ROM (EROM), a floppy diskette, a CD-ROM, an optical disk, a hard disk, or the like. 
     “Node”—As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, or the like, at which a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes may be realized by one physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even though received or output at a common node). 
     “Coupled”—The following description may refer to elements or nodes or features being “coupled” together. As used herein, unless expressly stated otherwise, “coupled” means that one element/node/feature is directly or indirectly joined to (or directly or indirectly communicates with) another element/node/feature, and not necessarily mechanically. Thus, although the schematic shown in  FIG.  2    depicts one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted test system. Furthermore, the connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in an embodiment of the subject matter. 
       FIG.  1    is a block diagram that depicts an embodiment of a test system  100  in a typical testing environment that includes a device under test (DUT)  102  coupled to the test system  100  in a way that allows the test system  100  to perform one or more electrical tests on the DUT  102 . The test system  100  may be implemented as a “bench test” component having a chassis or housing that contains various devices, elements, and electronic components. In certain embodiments, the test system  100  includes a power cord  104  with a standard alternating current (AC) power plug  106  to connect with a mains power source. Alternatively or additionally, the test system  100  can receive direct current (DC) operating voltage from an external power supply  108 , which obtains AC voltage from a mains power source via a power cord  110  and AC power plug  112 . In such an arrangement, the test system  100  may include at least one input interface  114  to obtain the DC voltage from the external power supply  108  (e.g., cable plug sockets, clip terminals, a connector, or the like). 
     The test system  100  includes at least one DUT power interface  118  that establishes an electrical connection  120  between a voltage regulator of the test system  100  and the DUT  102 . The DUT power interface  118  can be implemented in various form factors, depending on the configuration of the DUT  102 , the native power supply of the DUT  102 , the manner in which the DUT  102  is to be tested, and the like. For example, the DUT power interface  118  may include or cooperate with any of the following, without limitation: an electrical connector; cable plug sockets, clip terminals, an adapter, or the like. In certain embodiments, the DUT power interface  118  includes or cooperates with a DC voltage cord or cable that terminates with structure that emulates the shape and size of a battery that is normally used as the power source of the DUT  102  (such as a 1.5 volt AA battery). The terminating structure includes electrical contacts that simulate the positive and negative terminals of the DUT&#39;s battery, such that the voltage regulator of the test system  100  can provide operating voltage to the DUT  102  during testing. 
     The DUT  102  can be any electronic device having operating voltage and current specifications that are supported by the test system  100 . In this regard, the test system  100  must be able to generate sufficient DC operating voltage and current to power the DUT  102  during testing. In certain applications, the DUT  102  is a portable battery powered medical device, such as a personal insulin infusion device. In certain embodiments, the DUT  102  operates in a low power standby mode that is characterized by a discontinuous and high dynamic range standby current waveform. In accordance with a nonlimiting example, the standby current waveform includes discontinuous pulses that peak at approximately 100 mA and persist for only tens of microseconds, with intervening current of approximately 1.00 μA between the pulses, which may occur every 10-100 milliseconds. As mentioned previously, conventional current meters struggle to accurately measure current having such a high dynamic range. 
     The test system  100  disclosed here represents an effective, low cost, and elegant solution to the problem outlined above. The test system  100  employs a method of current measurement that is based on the charging and discharging characteristics of a power capacitor having a known, calibrated capacitance. The power capacitor serves as the source of power for the DUT  102 , and the charge on the capacitor is directly linked to the current being sourced or sinked, which is defined by physics and the electrical characteristics of the capacitor. The test system  100  uses the power capacitor to measure the total current consumed by the DUT  102  during a measurement time period, independent of the DUT&#39;s current waveform type, dynamic range, etc. As explained in more detail below, the test system  100  employs a circuit configuration that is automatically controlled to isolate the current path from the power capacitor to the DUT  102 . Any leakage current or quiescent current consumed by components of the test system  100  is negligible relative to the amount of current to be measured, or is isolated such that it has no impact on the current measurement. 
       FIG.  2    is a schematic diagram that depicts an embodiment of the test system  100  coupled to the DUT  102 . For the embodiment of  FIG.  2   , all of the illustrated items (other than the DUT  102 ) are part of the test system  100 . For the sake of clarity and simplicity, the power cord  104 , AC power plug  106 , input interface  114 , and DUT power interface  118  (see  FIG.  1   ) are not shown in  FIG.  2   . The illustrated embodiment of the test system  100  includes, without limitation: a power capacitor  202 ; a voltage regulator  204 ; a switching circuit having a first switching element  206  and a second switching element  208 ; a controller  210 ; a controller clock  212 ; a display device  214 ; a DC voltage source  216 ; one or more isolated power sources  217 ; a first current-isolating buffer  218 ; a second current-isolating buffer  220 ; a third current-isolating buffer  222 ; a diode  223 ; a capacitance calibration circuit  224 ; and various electrically conductive paths, traces, interconnects, or elements that serve to couple the components of the test system  100  together as needed. 
     The first switching element  206  is coupled between the DC voltage source  216  and a regulator input terminal  230  of the voltage regulator  204 . The second switching element  208  is coupled between the DC voltage source  216  and a power terminal  232  of the power capacitor  202  (the power terminal  232  is electrically coupled to the positive conductor or plate of the power capacitor  202 , as depicted in  FIG.  2   ). The power capacitor  202  has a ground terminal  234  that is electrically coupled to a ground potential of the test system  100 . The diode  223  has an anode  236  coupled to the power terminal  232  of the power capacitor  202 , and a cathode  238  coupled to the regulator input terminal  230  of the voltage regulator  204 . The voltage regulator  204  has a regulator output terminal  240  that can be coupled to the DUT  102  for testing purposes. In this regard, the DUT  102  can be removably connected to the test system  100  to establish the electrical coupling between the regulator output terminal  240  and the electronics of the DUT  102 . 
     The controller  210  is coupled to at least the power capacitor  202 , the voltage regulator  204 , the first switching element  206 , the second switching element  208 , the display device  214 , and the controller clock  212 . In accordance with the depicted implementation: the controller  210  is coupled to the voltage regulator  204  via an analog output port or terminal  244 ; the third current-isolating buffer  222  is coupled between the regulator output terminal  240  and the controller  210  via an analog input port or terminal  246 ; the controller  210  is coupled to the display device via a display output interface  248 ; the controller  210  is coupled to the controller clock via a clock interface  250 ; the second current-isolating buffer  220  is coupled between the power terminal  232  of the power capacitor  202  and a second voltage input terminal  252  of the controller  210 ; the controller  210  is coupled to the first switching element  206  via a first switch control port or terminal  254 ; the controller  210  is coupled to the second switching element  208  via a second switch control port or terminal  256 ; and the first current-isolating buffer  218  is coupled between the regulator input terminal  230  and a first voltage input terminal  258  of the controller  210 . In  FIG.  2   , the SW 1  and SW 2  labels represent switch control signals that are used to control the switching states of the first switching element  206  and the second switching element  208 , respectively. 
     The isolated power source(s)  217  are coupled to certain components, devices, or features of the test system  100  as appropriate to the particular embodiment. For the sake of clarity and simplicity, the various couplings associated with the isolated power source(s) are not depicted in  FIG.  2   . The capacitance calibration circuit  224  may be realized as a separate circuit module (as depicted in  FIG.  2   ), or it may be implemented with at least some of the other components and features of the test system  100 , such as the controller  210 , the voltage regulator  204 , the diode  223 , and corresponding interconnections. For the sake of clarity and simplicity, the various couplings associated with the capacitance calibration circuit are not depicted in  FIG.  2   . 
     The DC voltage source  216  provides operating voltage(s) for the test system  100 . In certain embodiments, the test system  100  includes the DC voltage source  216 , as depicted in  FIG.  2   . If internal to the test system  100 , the DC voltage source  216  can be powered by the mains power source. In some embodiments, however, the DC voltage source  216  may be external to the test system  100 . The DC voltage source  216  charges the power capacitor  202  when the second switching element  208  is closed, and provides a DC input voltage to the voltage regulator  204  when the first switching element  206  is closed. The voltage regulator  204  is configured and controlled to generate an appropriate DUT operating voltage at the regulator output terminal  240 , based on the DC input voltage that is present at the regulator input terminal  230 . Accordingly, the DC voltage source  216  provides a DC voltage that is high enough to charge the power capacitor  202  to its charged voltage level, and high enough to allow the voltage regulator  204  to generate the necessary operating voltage for the DUT  102 . In certain nonlimiting embodiments, the nominal operating voltage of the DUT  102  is 1.5 VDC, and the DC voltage source  216  provides 12.0 VDC. 
     The switching circuit includes at least the first switching element  206  and the second switching element  208 . The switching elements  206 ,  208  may be implemented as solid state (transistor-based) switches, or as electromechanical relays. Ideally, the switching elements  206 ,  208  consume little to no current. Transistor-based switches are appropriate if the amount of switch leakage current is low enough to be considered negligible, relative to the expected amount of DUT current to be measured. For example, if the measured DUT current is expected to be in the range of about one nanoamp or greater, then switches having leakage current in the picoamp range may be suitable for use in the test system (such that the ratio of measurement current to leakage current is at least 1000:1). Relays typically exhibit little to no leakage current and, therefore, are suitable for use in the test system  100 . 
     For this particular application, the capacitance of the power capacitor  202  should be stable across different working voltages, operating temperatures, environmental conditions, and the like. Accordingly, the type (composition) of the power capacitor  202  should provide a tightly controlled capacitance. For example, the power capacitor  202  may be a polypropylene film type, high voltage capacitor (e.g., generally greater than 100 volts). The capacitance can be selected to suit the needs and requirements of the particular application. For the example mentioned here (where the DC voltage source  216  provides 12 VDC, and the DUT  102  is powered by a 1.5 VDC source), the capacitance of the power capacitor  202  can be a value within the range of about 1.0 mF to about 10.0 mF (for smaller, low power devices). These capacitor sizes are readily available in polypropylene film. 
     The diode  223  is a passive component that may be a conventional off-the-shelf item. The diode  223  has very low reverse leakage, which should be in the range of about 1,000 times less than the intended measurement current. Accordingly, a silicon diode is best suited for this application (rather than a Schottky diode). The diode  223  does not consume any measurable quiescent current and, therefore, it can appear in the measured current flow path (as depicted in  FIG.  2   ). 
     The voltage regulator  204  is digitally controlled by the controller  210  such that the current consumed by the voltage regulator  204  is isolated, separated, or otherwise not considered in the measurement of the DUT current. The controller samples the regulator output voltage (at the analog input terminal  246 ) and generates an appropriate control signal (at the analog output terminal  244 ) to increase or decrease the regulator output voltage as needed in an ongoing manner. As explained in more detail below, the voltage regulator  204  is sourced by the isolated power source(s)  217  rather than by the DC voltage that appears at the regulator input terminal  230 . Consequently, the quiescent current consumed by the voltage regulator  204  is associated with the isolated power source(s)  217 , and the voltage regulator  204  operates in a current-isolated manner relative to the current consumed by the DUT  102  during testing. Additional details of the voltage regulator  204  are described below with reference to  FIGS.  5 - 7   . 
     Each of the current-isolating buffers  218 ,  220 ,  222  may be implemented as a unity gain operational amplifier having a conventional layout and configuration. Although not shown in  FIG.  2   , the current-isolating buffers  218 ,  220 ,  222  may include or cooperate with a simple voltage divider circuit if needed for compatibility with the analog inputs of the controller  210 . The current-isolating buffers  218 ,  220 ,  222  allow the controller  210  to sample the respective voltages, without consuming any measurable current. The current-isolating buffers  218 ,  220 ,  222  are powered by the isolated power source(s)  217 , and they have very low input leakage current. The input leakage current is low enough to make it negligible relative to the amount of DUT current that is to be measured. Thus, the measured DUT current remains accurate and precise even though the current-isolating buffers  218 ,  220 ,  222  branch off of the measurement current flow path. Stated another way, the buffers  218 ,  220 ,  222  are suitably configured and arranged to isolate the controller  210  from the test current flow path between the power capacitor  202  and the DUT  102 . 
     The test system  100  calculates the electrical current consumed by the DUT  102  during a measurement period of time, and generates the calculated current as an output. The display device  214  represents one type of output device that can be used to display the calculated current as an output. The display device  214  may be integrated with the housing or chassis of the test system  100 , or it may be realized as a separate peripheral component that connects to and/or communicates with the test system  100 . Any type of display technology and form factor can be utilized with the display device  214 , and the specific implementation details of the display device  214  will not be described here. In addition to, or instead of, the display device  214 , the test system  100  may include or cooperate with other output devices or systems, such as a printer, an audio transducer, a mechanical output device, or an interface that sends a notification, an email, a text message, an electronic report, or the like. 
     The controller  210  may be realized as one or more physical devices, such as a microcontroller unit, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system on a chip (SOC), or the like. In certain embodiments, the controller  210  is realized as a “single device” microcontroller unit that includes a processor core (e.g., a CPU), a storage medium for processor executable program instructions, an input/output interface, at least one digital-to-analog converter (DAC), at least one analog-to-digital converter (ADC), memory (volatile and nonvolatile), and other peripheral components or elements as needed. The controller  210  may be based on an off-the-shelf component that is programmed, configured, and/or customized for use in the test system  100 . To this end, the controller  210  is configurable to carry out the various processes, methods, operations, and functions described herein. 
     As mentioned previously, the test system  100  is designed, configured, and operated such that the current consumed by the DUT  102  can be accurately and precisely measured in an isolated manner. To this end, leakage current, quiescent current, and/or operating current consumed by certain components, devices, and elements of the test system  100  are minimized to the point where their contribution is negligible, or the sources of such current are isolated from the test current flow path. In this regard, the isolated power source(s)  217  may be utilized to provide operating voltage to one or more of the following items: the first switching element  206 ; the second switching element  208 ; the voltage regulator  204 ; the controller  210 ; the display device  214 ; the controller clock  212 ; the first current-isolating buffer  218 ; the second current-isolating buffer  220 ; the third current-isolating buffer  222 ; and the capacitance calibration circuit  224 . 
     As explained in more detail below, the known capacitance of the power capacitor  202  is used to calculate the current consumed by the DUT  102  during the measurement time period. Although the power capacitor  202  is chosen such that its capacitance is relatively stable and constant, it can still be susceptible to slight variation over time. Thus, it is important to have an accurate calibrated capacitance value. The capacitance calibration circuit  224  is couplable to the power capacitor  202  to calibrate the capacitance of the power capacitor  202 . Calibration may occur whenever the test system  100  is powered up, before each current measurement, daily, weekly, or the like. The capacitance calibration circuit  224  can be implemented to self-calibrate the test system  100  using, for example, a constant and known current source, which may cooperate with other components of the test system  100  to perform a calibration routine. When performing a calibration, the fixed current source (e.g., a constant 1.0 mA current) takes the place of the DUT  102 . For calibration, the unknown variable is the capacitance, which can be calculated based on the discharge characteristics of the power capacitor  202 . The calibrated capacitance can be saved for use as a known value for subsequent current measurements, where the unknown variable is the current consumed by the DUT  102 . The test system  100  itself may also be calibrated as needed, such as annually, monthly, or the like. Calibration of the test system  100  may require external calibration equipment to calibrate the voltage sources, the fixed current source that is used to obtain the calibrated capacitance, the ADCs and DACs of the controller  210 , etc. 
     The switching circuit is configured and controlled by the controller  210  to regulate electrical connections between the DC voltage source, the power capacitor  202 , and the voltage regulator  204 . In this regard, the controller  210  is configurable to control the switching circuit by independently opening and closing the switching elements  206 ,  208  as needed. The controller  210  activates or actuates the switching elements  206 ,  208  to place the test system  100  into different states or operating modes including, without limitation: a charging state; a measurement state; and a post-measurement state. 
     For the charging state, the controller  210  keeps the first and second switching elements  206 ,  208  closed to charge the power capacitor  202  with source voltage provided by the DC voltage source  216 . When both of the switching elements  206 ,  208  are closed, the diode  223  is not forward biased and, therefore, current does not flow through the diode  223 . Thus, the voltage of the power capacitor  202  can be sampled and monitored by the controller  210  via the second voltage input terminal  252 . While operating in the charging state, the source voltage of the DC voltage source  216  is present at the regulator input terminal  230 , which enables the voltage regulator  204  to generate a regulated DUT operating voltage for the DUT  102 . The DUT operating voltage can operate the DUT  102  while the power capacitor  202  is being charged. Accordingly, the DUT  102  can be initialized, prepared for testing, placed into its low current standby mode, or the like, while being sourced by the DC voltage source  216 . 
     For the measurement state, the controller  210  keeps the first and second switching elements  206 ,  208  open to provide the capacitor voltage to the regulator input terminal  230 . Opening the switching elements  206 ,  208  isolates the DC voltage source  216  from the other components of the test system  100 . Thus, while in the measurement state, the power capacitor  202  functions as the voltage source instead of the DC voltage source  216 —the power capacitor  202  provides its capacitor voltage to the voltage regulator  204  via the diode  223 . When both of the switching elements  206 ,  208  are open, the diode  223  is forward biased by the capacitor voltage and, therefore, the diode permits discharge of the power capacitor  202  by way of a test current flow path  270 . The test current flow path (depicted in dashed lines) runs from the power capacitor  202 , through the diode  223 , through the voltage regulator  204 , and to the DUT  102 , which represents the electrical load that consumes the power provided by the power capacitor  202 . While operating in the measurement state, the capacitor voltage is present at the regulator input terminal  230 , which enables the voltage regulator  204  to generate the regulated DUT operating voltage for the DUT  102  (assuming that the capacitor voltage remains high enough). While operating in the measurement state, the capacitor voltage can be sampled by the controller  210  (via the second voltage input terminal  252 ), and the voltage present at the regulator input terminal  230  can be sampled by the controller  210  (via the first voltage input terminal  258 ). 
     For the post-measurement state, the controller  210  keeps the first switching element  206  closed and the second switching element  208  open. While the test system  100  is in the post-measurement state, the DC voltage source  216  provides its voltage to the regulator input terminal  230  and to the cathode  238  of the diode  223 , via the first switching element  206 . In the post-measurement state, the diode  223  is reverse biased and, therefore, inhibits further discharge of the power capacitor  202 . Accordingly, the source voltage generated by the DC voltage source  216  can be sampled by the controller  210  (via the first voltage input terminal  258 ), and the discharged voltage of the power capacitor  202  can be sampled by the controller  210  (via the second voltage input terminal  252 ) when the test system  100  is in the post-measurement state. 
     Operation of the test system  100  will now be described with reference to  FIG.  3   , which is a flow chart that illustrates an embodiment of an automated current measurement process  300 . The process  300  is performed by the test system  100  to measure electrical current consumed by the DUT  102 . The description of the process  300  may refer to elements mentioned above in connection with  FIGS.  1  and  2   . It should be appreciated that the process  300  may include any number of additional or alternative tasks, the tasks shown in  FIG.  3    need not be performed in the illustrated order, and the process  300  may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. Moreover, one or more of the tasks shown in  FIG.  3    could be omitted from an embodiment of the process  300  as long as the intended overall functionality remains intact. 
     The process  300  may begin by calibrating the capacitance of the power capacitor  202  (task  302 ). As explained above, calibration need not be performed for each measurement and, therefore, task  302  may be performed periodically, in accordance with a particular schedule, or the like. Nonetheless, task  302  is shown for the sake of completeness. The following description of the process  300  assumes that the test system  100  has an accurate calibrated value of the capacitance, which can be used to calculate the amount of current consumed by the DUT  102  during the measurement period. The DUT  102  is connected to the test system  100  in an appropriate manner (task  304 ) to establish an electrical coupling between the regulator output terminal  240  and the electronics of the DUT  102 . In this way, the voltage regulator  204  can serve as the power source of the DUT  102 . 
     After the DUT  102  has been connected to the test system  100 , the current measurement routine begins. The test may begin automatically in response to connecting the DUT  102 , or it may require a user instruction or command. In certain embodiments, the test system  100  automatically controls the switching circuit with the controller  210  to place the test system into the charging state (task  306 ). As mentioned above, the controller  210  keeps the first and second switching elements  206 ,  208  closed while the test system  100  is in the charging state, such that the DC voltage source  216  charges the power capacitor  202 . Moreover, the DC voltage source  216  provides an input voltage to the voltage regulator  204 , which in turn provides an appropriate operating voltage to the DUT  102 . Accordingly, the DUT  102  can be initialized and otherwise prepared for the current measurement routine. 
     The charging state is maintained until the power capacitor  202  is charged (e.g., the capacitor voltage has reached a charged voltage level). If the power capacitor  202  has not reached the charged voltage (the “No” branch of query task  308 ), then the test system remains in the charging state. If the power capacitor  202  has reached the charged voltage (the “Yes” branch of query task  308 ), then the process  300  continues by automatically controlling the switching circuit with the controller  210  to transition the test system  100  from the charging state into the measurement state (task  310 ). In some embodiments, query task  308  involves comparing the capacitor voltage against a charged voltage threshold, such that the switching circuit is automatically controlled to place the test system  100  into the measurement state when the capacitor voltage reaches the charged voltage threshold. The controller  210  can sample the capacitor voltage at the second voltage input terminal  252  for purposes of this comparison. In some embodiments, query task  308  involves monitoring elapsed time after entering the charging state, such that the switching circuit is automatically controlled to place the test system into the measurement state when the elapsed time exceeds a charging time threshold. The controller  210  can maintain a counter or a timer (based on operation of the controller clock  212 ) to monitor the elapsed time. 
     This example assumes that the power capacitor  202  has reached its charged voltage and that the test system  100  has transitioned to the measurement state. As mentioned above, the controller  210  opens the first and second switching elements  206 ,  208  to place the test system  100  into the measurement state, and keeps them open while the test system operates in the measurement state. For the measurement state, the DC voltage source  216  is disconnected from the remaining components, and the power capacitor  202  provides its capacitor voltage to the voltage regulator  204 . In response to the transition to the measurement state, the controller  210  begins (or resumes) sampling the voltages at the first voltage input terminal  258  and the second voltage input terminal  252  (task  312 ), and records a measurement start time (task  314 ). In certain embodiments, tasks  310 ,  312 , and  314  are performed concurrently such that the measurement start time is recorded, the voltages are sampled, and the switching elements  206 ,  208  are opened at the same time. Thus, the measurement start time is associated with opening of the switching elements  206 ,  208 . 
     The measurement state is maintained until the power capacitor  202  has reached a discharged voltage in response to loading, i.e., operation of the DUT  102 . In this regard, the capacitor voltage drops over time due to current consumed by the DUT  102 . If the power capacitor  202  has not reached the discharged voltage (the “No” branch of query task  316 ), then the test system  100  remains in the measurement state. If the power capacitor  202  has reached the discharged voltage (the “Yes” branch of query task  316 ), then the process  300  continues by automatically controlling the switching circuit with the controller  210  to transition the test system  100  from the measurement state into the post-measurement state (task  318 ). The test system  100  is designed and operated such that the power capacitor  202  is not discharged too much during the measurement state, to ensure that the voltage characteristics of the power capacitor remain linear. 
     In some embodiments, query task  316  involves comparing the capacitor voltage against a minimum capacitor voltage threshold, such that the switching circuit is automatically controlled to place the test system  100  into the post-measurement state when the capacitor voltage is less than or equal to the minimum capacitor voltage threshold. The controller  210  can sample the capacitor voltage at the second voltage input terminal  252  for purposes of this comparison. For the example presented here, where the DC voltage source  216  provides 12 VDC, the minimum capacitor voltage threshold may be about 8 VDC. In some embodiments, query task  316  involves monitoring elapsed time after entering the measurement state (i.e., after opening of the switching elements  206 ,  208 ), such that the switching circuit is automatically controlled to place the test system  100  into the post-measurement state when the elapsed time is greater than or equal to a maximum time threshold. The controller  210  can maintain a counter or a timer (based on operation of the controller clock  212 ) to monitor this elapsed time. For the example presented here, the maximum time threshold may be on the order of one to two seconds. 
     This example assumes that the power capacitor  202  has reached the discharged voltage and that the test system  100  has transitioned to the post-measurement state. As mentioned above, the controller  210  closes the first switching element  206  and keeps the second switching element  208  open to place the test system  100  into the post-measurement state, and maintains those switch conditions while the test system  100  operates in the post-measurement state. For the post-measurement state, the DC voltage source  216  is coupled to: the cathode  238  of the diode  223 ; the input of the first current-isolating buffer  218 ; and the regulator input terminal  230 . The open state of the second switching element  208 , however, keeps the DC voltage source  216  disconnected from: the power capacitor  202 ; the anode  236  of the diode  223 ; and the input of the second current-isolating buffer  220 . Accordingly, the diode  223  is reverse biased, the power capacitor  202  no longer discharges, and the capacitor voltage (which is sampled at the second voltage input terminal  252 ) remains stable in the post-measurement state. Moreover, the voltage provided by the DC voltage source  216 , which corresponds to the charged voltage of the power capacitor  202 , can be sampled at the first voltage input terminal  258  in the post-measurement state. 
     In response to the transition to the post-measurement state, the controller  210  records a measurement end time (task  320 ). In certain embodiments, tasks  318  and  320  are performed concurrently such that the first switching element  206  is closed and the measurement end time is recorded at the same time. Thus, the measurement end time is associated with closing of the first switching element  206 . The controller  210  may stop sampling the voltages at the first voltage input terminal  258  and the second voltage input terminal  252  (task  322 ) at any suitable time following the transition to the post-measurement state. For reasons explained below, the controller  210  continues sampling these voltages in the post-measurement state for a period of time, to ensure that the voltages have stabilized. 
     The process  300  continues by calculating the electrical current provided by the power capacitor  202  (and consumed by the DUT  102 ) in a time period recorded during operation of the test system  100  in the measurement state (task  324 ). For this example, the time period is defined by the recorded measurement start time and the recorded measurement end time, and the calculation is based on a sampled value of the charged voltage of the power capacitor  202 , a sampled value of the discharged voltage of the power capacitor  202 , and discharge characteristics of the power capacitor  202 —namely, the relationship between capacitance and capacitor voltage over time with respect to electrical current. More specifically, the controller  210  calculates the electrical current consumed by the DUT  102  between the recorded measurement start time and the recorded measurement end time in accordance with the expression 
               i   =     C   ⁢         V   c     -     V   d           t   f     -     t   i             ,         
where: C is the known (calibrated) capacitance of the power capacitor; V c  is the sampled value of the charged voltage; V d  is the sampled value of the discharged voltage; t i  is the recorded measurement start time; and t f  is the recorded measurement end time. The controller  210  records the measurement start and end times, samples the capacitor voltage at the second voltage input terminal  252 , and samples the input voltage of the voltage regulator  204  at the first voltage input terminal  258 . Thus, the current consumed by the DUT  102  can be easily determined at task  324 .
 
     The process  300  continues by generating the calculated electrical current as an output of the test system  100  (task  326 ). For example, the display device  214  can be controlled and driven in an appropriate manner to display the calculated electrical current in any desired format, e.g., a numerical readout. For this particular example, the test system  100  displays the standby current consumed by the DUT  102  during the measurement time period, which is typically several seconds. The standby current represents an average of the instantaneous current measured over the recorded time period. 
       FIG.  4    is a graph that includes plots of voltage levels over time, as sampled during a typical current measurement test performed by the test system  100  shown in  FIG.  2   . The horizontal time axis indicates the measurement start time (t i ) and the measurement end time (t f ). The vertical voltage axis indicates the charged voltage (V c ) and the discharged voltage (V d ) of the power capacitor  202 . In  FIG.  4   , the dashed line plot  402  corresponds to the voltage present at the regulator input terminal  230 , the cathode  238  of the diode  223 , and the input of the first current-isolating buffer  218 . In other words, the plot  402  represents the voltage sampled at the first voltage input terminal  258  of the controller  210 . The solid line plot  404  corresponds to the voltage present at the power terminal  232  of the power capacitor  202 , the anode  236  of the diode  223 , and the input of the second current-isolating buffer  220 . In other words, the plot  404  represents the voltage sampled at the second voltage input terminal  252  of the controller  210 . The two plots  402 ,  404 , track each other during the charging state (before the measurement start time) and during the measurement state (between the measurement start time and the measurement end time), due to the status of the switching elements  206 ,  208  during that period of time. The two plots  402 ,  404  diverge at the measurement end time, due to the closure of the first switching element  206  (the second switching element  208  remains open). As explained above, the transition from the measurement state to the post-measurement state reconnects the DC voltage source  216  to the voltage regulator  204 , which makes the source voltage (i.e., the charged voltage) immediately available for sampling at the first voltage input terminal  258 . The capacitor voltage, however, remains stable in the post-measurement state. Accordingly, the discharged voltage of the power capacitor  202  is available for sampling at the second voltage input terminal  252 . 
     For the embodiment shown in  FIG.  2   , it is assumed that the charged voltage of the power capacitor  202  equals the voltage generated by the DC voltage source  216 . Accordingly, the charged voltage value may be sampled at the first voltage input terminal  258  at a sampling time that occurs before the measurement start time and/or at a sampling time that occurs after the measurement end time (i.e., while the test system  100  is in the post-measurement state). Alternatively or additionally, the charged voltage value may be sampled at the second voltage input terminal  252  at a sampling time that occurs before the measurement start time. 
     The embodiment of the test system  100  shown in  FIG.  2    samples the discharged voltage at the second voltage input terminal  252  at a sampling time that occurs after the measurement end time, while the capacitor voltage remains constant. For example, the test system  100  may wait a number of sampling periods or a designated amount of time before sampling the discharged voltage, or it may continue to sample the discharged voltage level but only consider sampled values obtained after the designated amount of time (e.g., 100 ms, one second, or the like). This sampling scheme takes into account the equivalent series resistance (ESR) of the power capacitor  202 . The effect of ESR on the sampled voltages is schematically depicted in  FIG.  4   . At the measurement start time, both plots  402 ,  404  exhibit a sudden voltage drop. This drop occurs when the switching elements  206 ,  208  are opened to insert the power capacitor  202  into the current flow path  270 ; the voltage drop is caused by the ESR of the power capacitor  202 . At the measurement end time, however, the power capacitor  202  is removed from the current flow path  270 . Consequently, the ESR of the power capacitor  202  results in a quick voltage recovery before the capacitor voltage stabilizes to its discharged voltage level. The controller  210  uses a sampled value of the stabilized capacitor voltage to calculate the current consumed by the DUT  102 . 
     Referring again to task  324  and the expression used to calculate the measured current, the charged voltage (V c ) may be sampled: at the first voltage input terminal  258  of the controller  210  at a sampling time that occurs before the measurement start time; at the first voltage input terminal  258  of the controller  210  at a sampling time that occurs after the measurement end time; and/or at the second voltage input terminal  252  of the controller  210  at a sampling time that occurs before the measurement start time. The discharged voltage (V d ) is sampled at the second voltage input terminal  252  at a sampling time that occurs after the measurement end time. Although not required, the charged voltage and the discharged voltage can be sampled at the same sampling time (while the test system  100  is in the post-measurement state). 
     The current measurement procedure described here can reliably and accurately measure the average current consumed by a DUT, even when the current exhibits a very high dynamic range and relatively low peak current values. The test system  100  described here can be fabricated from inexpensive and readily available parts and components, and can be modified as needed to effectively support different types of DUTs having different functional specifications, voltage requirements, and current consumption characteristics. 
     As mentioned above, the voltage regulator  204  is suitably configured and controlled such that its output current very closely matches its input current (i.e., any quiescent current consumed by the voltage regulator  204  is negligible relative to the amount of DUT current being measured). Linear voltage regulators are used to produce a constant output voltage from a varying input voltage of higher magnitude. Linear voltage regulators typically include a series pass transistor (which may be a MOSFET or a BJT), an error amplifier, a voltage reference, and a feedback divider network. The voltage reference establishes a fixed voltage value that is used for comparison purposes. The feedback divider network produces a scaled version of the output voltage with a reduction ratio equal to the desired output voltage divided by the reference voltage. The error amplifier compares the scaled output voltage against the reference voltage, and drives the series pass transistor to vary its resistance. Ideally, the transistor is driven to minimize the difference between the output voltage and the reference voltage. 
     A typical linear voltage regulator that follows conventional design methodologies includes three terminals: an input voltage terminal (VIN); an output voltage terminal (VOUT); and a ground terminal (GND). The input voltage is applied between the VIN and GND terminals, and the regulated output voltage is supplied between the VOUT and GND terminals. The series pass transistor places the VIN and VOUT terminals in a series circuit. Theoretically, the current flowing into the VIN terminal (I IN ) should be equal to the current flowing out of the VOUT terminal (I OUT ). However, I IN  is always higher than I OUT  (for such conventional voltage regulators) because the regulator inherently consumes an amount of current that is associated with operation of the voltage reference, the error amplifier, and the feedback divider network. Depending on the topology and implementation of the voltage regulator, the magnitude of the difference between I IN  and I OUT  is highly variable and may also vary depending on the applied load. 
     In some applications (e.g., the test system  100  described above), it may be desirable to have I IN  match I OUT . For example, such a scenario exists when it is necessary to precisely measure the applied load current without affecting the voltage on the VOUT terminal. If the I IN  is identical to I OUT , then a shunt resistor can be placed in series with the VIN terminal, and the voltage drop across the shunt resistor will be directly proportional to the magnitude of the I OUT  current. In this situation, the voltage drop across the shunt resistor will not affect the regulated output voltage of the voltage regulator, because the regulator will naturally account for the drop on the VIN terminal. 
     In accordance with certain embodiments described here, the current consumed by the voltage regulator itself is isolated from the current supplied to the load. The current-isolating design and configuration of the voltage regulator results in matching values of I IN  and I OUT , wherein any difference is negligible or de minimis relative to the magnitude of I IN  and I OUT . In this regard,  FIG.  2    depicts an implementation where the controller  210  controls the voltage regulator  204  without consuming current from the power capacitor  202 . Moreover, the voltage regulator  204 , the controller  210 , and the third current-isolating buffer  222  obtain operating voltage from the isolated power source(s)  217  rather than from the power capacitor  202 .  FIGS.  5 - 7    depict embodiments of a linear voltage regulator having isolated supply current. The test system  100  can be modified (if needed) to use the voltage regulators shown in  FIGS.  5 - 7   .  FIG.  5    depicts a linear voltage regulator  500  that is based on an analog design,  FIG.  6    depicts a linear voltage regulator  600  that includes or cooperates with an ADC, a DAC, and a processing core, and  FIG.  7    depicts a linear voltage regulator  700  that includes or cooperates with a DAC. 
     Referring to  FIG.  5   , the linear voltage regulator  500  generally includes, without limitation: a series pass transistor  502 ; an error amplifier  504 ; a voltage reference source  506  to provide a reference voltage for the voltage regulator  500 ; a buffer amplifier  508 ; a feedback divider network that includes a first resistor  510  and a second resistor  512 ; an input voltage terminal  514  (labeled VIN) for the regulator input voltage; an output voltage terminal  516  (labeled VOUT) for the regulator output voltage; a supply voltage terminal  518  (labeled VSPLY); and a ground terminal  520  (labeled GND). 
     To achieve appropriate current isolation, the series pass transistor  502  is a metal-oxide-semiconductor field-effect transistor (MOSFET). For the depicted embodiment, the transistor  502  is a p-channel enhancement mode MOSFET. The transistor  502  is coupled between the input voltage terminal  514  and the output voltage terminal  516 . More specifically, the source of the transistor  502  is coupled to the input voltage terminal  514 , the drain of the transistor  502  is coupled to the output voltage terminal  516 , and the gate of the transistor is coupled to the error output  530  of the error amplifier  504 . The feedback divider network is coupled between the buffer output  548  and the ground terminal  520 . A negative error input  532  of the error amplifier  504  is coupled to a positive terminal  534  of the voltage reference source  506 , and a positive error input  536  of the error amplifier  504  is coupled to the feedback divider network. More specifically, the positive error input  536  is coupled between the first and second resistors  510 ,  512 , which are connected in series with one another. Notably, the error amplifier  504  is powered by an independent voltage supply, which can be coupled between the supply voltage terminal  518  and the ground terminal  520  (the lines leading from the error amplifier  504  to the supply voltage terminal  518  and the ground terminal  520  represent the supply voltage connection). A negative terminal  540  of voltage reference source  506  is coupled to the ground terminal  520 , and the voltage reference source  506  is powered by the independent voltage supply (the voltage reference source  506  is coupled to the supply voltage terminal  518  to obtain the supply voltage). 
     The buffer amplifier  508  is configured as a unity gain follower having a high input impedance. The positive buffer input  544  of the buffer amplifier  508  is coupled to the drain of the transistor  502  and to the output voltage terminal  516 . The negative buffer input  546  of the buffer amplifier  508  is coupled to the buffer output  548  of the buffer amplifier  508  and to a first end  550  of the first resistor  510 . Notably, the buffer amplifier  508  is powered by the independent voltage supply (the lines leading from the buffer amplifier  508  to the supply voltage terminal  518  and the ground terminal  520  represent the supply voltage connection). The second end  552  of the first resistor  510  is coupled to a first end  554  of the second resistor  512  and to the positive error input  536  of the error amplifier  504 , as mentioned above. The second end  556  of the second resistor  512  is coupled to the ground terminal  520 , thus establishing the feedback divider network. The resistor values are chosen such that the feedback divider network provides a scaled output voltage (that ideally matches the reference voltage) at the divider output, which corresponds to the node defined by the second end  552  of the first resistor  510 , the first end  554  of the second resistor  512 , and the positive error input  536  of the error amplifier  504 . 
     The basic operating principle of the linear voltage regulator  500  is similar to that described above for a traditional three-terminal voltage regulator. In this regard, the output of the error amplifier  504  controls the impedance of the transistor  502  to adjust the regulator output voltage that appears at the output voltage terminal  516 . The output of the error amplifier  504  is produced based on the difference between the reference voltage that appears at the negative error input  532  and the scaled output voltage that appears at the positive error input  536 . For example, if the scaled output voltage is higher than the reference voltage, then the output voltage of the error amplifier  504  can be adjusted to incrementally increase the series pass resistance of the transistor  502  to reduce the regulator output voltage. Conversely, if the scaled output voltage is lower than the reference voltage, then the output voltage of the error amplifier  504  can be adjusted to incrementally decrease the series pass resistance of the transistor  502  to increase the regulator output voltage. 
     The voltage regulator  500  achieves supply current isolation by way of the buffer amplifier  508 . The buffer amplifier  508  is configured and arranged to operate as a unity gain (1:1) follower, such that the voltage at the buffer output  548  matches the voltage at the positive buffer input  544  (the output of the buffer amplifier  508 , rather than the transistor  502 , drives the feedback divider network). Current isolation is further achieved through the use of the supply voltage terminal  518  and the ground terminal  520 , which are coupled to provide source voltage and operating current to the error amplifier  504 , the voltage reference source  506 , and the buffer amplifier  508 —these components are powered by an independent voltage supply that is coupled to the supply voltage terminal  518 , which is isolated from the input voltage terminal  514 . Accordingly, the input voltage terminal  514  supplies current only to the output voltage terminal  516 , via the transistor  502 . The inherently high input impedance of the buffer amplifier  508  results in only a negligible amount of current drawn from the output voltage terminal  516 . 
     The transistor  502  is realized as a MOSFET (either NMOS or PMOS, although  FIG.  2    depicts a PMOS implementation) to take advantage of the extremely low gate-source and gate-drain currents. A MOSFET operating in near steady-state conditions has negligible gate-source and gate-drain currents, relative to the amount of series pass current. Furthermore, the high input impedance of the positive buffer input  544  of the buffer amplifier  508  ensures that the current flow into the positive buffer input  544  is negligible compared to the desired current measurement resolution (e.g., less than 1:1000). In this regard, the buffer amplifier  508  isolates the current flow path from the input voltage terminal  514  to the output voltage terminal  516 , such that the ratio of current flowing into the positive buffer input  544  to current flowing in the current flow path is less than 1:1000. As an example, if the desired current measurement resolution is 1.0 μA, the input impedance of the buffer amplifier  508  should be on the order of 1.0 GΩ or higher, such that the input current is 1.0 nA or less. 
     The independent voltage supply (which feeds the supply voltage terminal  518 ) supplies the quiescent current needed to operate the error amplifier  504 , the voltage reference source  506 , and the buffer amplifier  508 . This arrangement provides additional current isolation because the quiescent current is separate and distinct from the current that flows through the transistor  502 . 
     Referring to  FIG.  6   , the voltage regulator  600  generally includes, without limitation: a series pass transistor  602 ; a buffer amplifier  608 ; a feedback divider network that includes a first resistor  610  and a second resistor  612 ; an input voltage terminal  614  (labeled VIN); an output voltage terminal  616  (labeled VOUT); a supply voltage terminal  618  (labeled VSPLY); a ground terminal  620  (labeled GND); an ADC  670 ; a digital processing core  672 ; and a DAC  674 . The arrangement and configuration of the voltage regulator  600  are similar to that described above for the voltage regulator  500 . The illustrated embodiment of the voltage regulator  600 , however, replaces the error amplifier  504  with the combination of the ADC  670 , the processing core  672 , and the DAC  674 . Accordingly, for the sake of brevity and convenience, common or equivalent aspects of the voltage regulators  500 ,  600  will not be redundantly described in detail with reference to  FIG.  6   . 
     The series pass transistor  602  is realized as a MOSFET having its source coupled to the input voltage terminal  614 , its drain coupled to the output voltage terminal  616 , and its gate coupled to an analog output  630  of the DAC  674 . An analog voltage input  636  of the ADC  670  is coupled to the divider output of the feedback divider network to receive a scaled output voltage produced by the feedback divider network. More specifically, the analog voltage input  636  is coupled between the first and second resistors  610 ,  612 , which are connected in series with one another. The positive buffer input  644  of the buffer amplifier  608  is coupled to the drain of the transistor  602  and to the output voltage terminal  616 . The negative buffer input  646  of the buffer amplifier  608  is coupled to the buffer output  648  of the buffer amplifier  608  and to a first end  650  of the first resistor  610 . The second end  652  of the first resistor  610  is coupled to a first end  654  of the second resistor  612  and to the analog voltage input  636  of the ADC  670 , as mentioned above. The second end  656  of the second resistor  612  is coupled to the ground terminal  620 , thus establishing the feedback divider network. 
     Although depicted as separate blocks in  FIG.  6   , the ADC  670 , the processing core  672 , and the DAC  674  can be combined into a single device or component, depending on the desired implementation. For example, the ADC  670 , the processing core  672 , and the DAC  674  can be realized as features or elements of a microcontroller device. For the illustrated embodiment, the ADC  670  is coupled to the processing core  672  in an appropriate manner to communicate digital information to the processing core  672 . Likewise, the processing core  672  is coupled to the DAC  674  in an appropriate manner to communicate digital information to the DAC  674 . In this regard, the ADC  670  has a digital output interface  680 , which is coupled to a digital input interface  682  of the processing core  672 . Moreover, the processing core  672  has a digital output interface  684 , which is coupled to a digital input interface  686  of the DAC  674 . 
     The DAC  674  cooperates with a voltage reference source  688 , which provides a reference voltage for the digital-to-analog conversion. Similarly, the ADC  670  cooperates with a voltage reference source  690 , which provides a reference voltage for the analog-to-digital conversion. The reference voltage used by the DAC  674  will typically be higher than the reference voltage used by the ADC  670 . Accordingly, the voltage reference source  688  can be distinct and separate from the voltage reference source  690  (as shown). The ADC  670 , the processing core  672 , the DAC  674 , the buffer amplifier  608 , the voltage reference source  688 , and the voltage reference source  690  are powered by an independent voltage supply (as described above). Accordingly, these components are coupled to the supply voltage terminal  618  and the ground terminal  620 . For simplicity and clarity,  FIG.  6    does not show separate connections between the supply voltage terminal  618  and the voltage reference sources  688 ,  690 . 
     The basic operating principle of the linear voltage regulator  600  is similar to that described above for the voltage regulator  500 . The feedback divider network provides the scaled output voltage to the ADC  670 . The digital output interface  680  of the ADC  670  provides a digital representation of the scaled output voltage that appears at the analog voltage input  636 . The processing core  672  receives the digital representation of the scaled output voltage by way of its digital input interface  682 . The processing core  672  implements an algorithm that attempts to minimize the difference between the sampled voltage and a specified reference voltage. In this regard, the processing core  672  calculates a difference between the digital representation of the scaled output voltage and a digital representation of a programmed, stored, or otherwise designated reference voltage. The processing core  672  generates a digital control output at its digital output interface  684 , wherein the digital control output is based on the calculated difference. The digital control output is provided to the DAC  674 , by way of the digital input interface  686 . 
     The DAC  674  is configured and operated to convert the digital control output into a corresponding analog control voltage, which appears at the analog output  630  of the DAC  674 . The analog control voltage controls the impedance of the transistor  602  to adjust the regulator output voltage that appears at the output voltage terminal  616 . 
     As described above with reference to the voltage regulator  500 , the transistor  602 , the buffer amplifier  608 , and the independent voltage supply (that feeds the supply voltage terminal  618 ) cooperate to provide current isolation for the voltage regulator  600 . Accordingly, the input voltage terminal  614  supplies current only to the output voltage terminal  616 , via the transistor  602 . 
     Referring to  FIG.  7   , the voltage regulator  700  generally includes, without limitation: a series pass transistor  702 ; an error amplifier  704 ; an input voltage terminal  714  (labeled VIN) for the regulator input voltage; an output voltage terminal  716  (labeled VOUT) for the regulator output voltage; a supply voltage terminal  718  (labeled VSPLY) for an independent voltage supply; a ground terminal  720  (labeled GND); and a reference voltage terminal  721  (labeled VREF) for a reference voltage. Certain aspects of the voltage regulator  700  are similar to that described above for the voltage regulators  500 ,  600 . Accordingly, for the sake of brevity and convenience, common or equivalent aspects of the voltage regulators  500 ,  600 ,  700  will not be redundantly described in detail with reference to  FIG.  7   . 
     The series pass transistor  702  is realized as a MOSFET having its source coupled to the input voltage terminal  714 , its drain coupled to the output voltage terminal  716 , and its gate coupled to the error output  730  of the error amplifier  704 . A negative error input  732  of the error amplifier  704  is coupled to the reference voltage terminal  721  to receive the reference voltage. In certain embodiments, a positive error input  736  of the error amplifier  704  is directly connected to the drain of the transistor  702  and to the output voltage terminal  716  (in other words, no intervening components, devices, or elements are arranged between the output voltage terminal  716  and the positive error input  736 ). Thus, the error amplifier  704  directly receives the regulator output voltage in a feedback path. The error amplifier  704  is powered by an independent voltage supply, which can be coupled between the supply voltage terminal  718  and the ground terminal  720 . As mentioned previously, the independent voltage supply is isolated from the input voltage terminal  714 . 
     The illustrated embodiment of the voltage regulator  700  employs an external DAC  750  and an associated reference voltage source  752 . The DAC  750  and the reference voltage source  752  take the place of an internal voltage reference for the error amplifier  704 , a feedback divider network, and a 1:1 buffer amplifier (which are described above in the context of the voltage regulators  500 ,  600 ). The DAC  750  and the reference voltage source  752  obtain operating power from a source other than the voltage that serves as the input to the voltage regulator  700 . For example, the DAC  750  and the reference voltage source  752  may be powered by the independent voltage supply and/or by another auxiliary voltage supply (not shown in  FIG.  7   ). 
     The DAC  750  generates a fixed analog voltage that is equal to the desired regulator output voltage. The error amplifier  704  compares the voltage at the output voltage terminal  716  against the voltage applied to the reference voltage terminal  721 , and drives the series pass transistor  702  to maintain the minimum possible difference. The positive error input  736  of the error amplifier  704  has a very high impedance (as mentioned above with reference to the buffer amplifier  508 ) to limit the amount of current drawn from the output voltage terminal  716  by the error amplifier  704 . 
     The DAC  750  functions as a fixed reference voltage source, and its analog output is coupled to the reference voltage terminal  721 . The DAC  750  represents a digitally programmable component that can be configured to provide the desired reference voltage, up to a maximum voltage that is based on the voltage generated by the reference voltage source  752 . Thus, the reference voltage provided by the DAC  750  can be digitally programmed and adjusted to match the expected regulator output voltage present at the output voltage terminal  716 . In alternative implementations, a suitably configured analog voltage source or fixed voltage supply can be utilized instead of the DAC  750 . For example, if the regulator output voltage is expected to be 1.5 VDC, then an external 1.5 VDC voltage source can be coupled to the reference voltage terminal  721 . 
     The basic operating principle of the linear voltage regulator  700  is similar to that described above for the voltage regulator  500 . The regulator output voltage (not a scaled version of it) is fed directly to the positive error input  736  of the error amplifier  704 , and the external DAC  750  provides the desired reference voltage to negative error input  732  of the error amplifier  704 , by way of the reference voltage terminal  721 . The error amplifier  704  generates its output based on the difference between the reference voltage and the regulator output voltage, and the output controls the impedance of the transistor to adjust the regulator output voltage as needed. 
     While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application.