Patent Publication Number: US-11048996-B2

Title: Information processing apparatus, ising device, and information processing apparatus control method

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2016-112488, filed on Jun. 6, 2016, the entire contents of which are incorporated herein by reference. 
     FIELD 
     The embodiments discussed herein relate to an information processing apparatus, an ising device, and an information processing apparatus control method. 
     BACKGROUND 
     Neumann computers are not very suitable for solving multivariable optimization problems. However, to solve these problems, there is a method that uses an ising device (or a Boltzmann machine) that performs simulated annealing using an ising objective function. Such an ising device performs calculation by replacing a problem to be calculated with an ising model, which is a model representing the behavior of a ferromagnetic spin. 
     However, if an ising device is realized by software simulation, the number of units included in the ising device or the number of connections among the units increases as the number of variables handled by an optimization problem increases. As a result, the calculation time is extended. 
     There has conventionally been proposed a method of reducing the calculation time by realizing an ising device with hardware modules. There has also been proposed an ising device (also called a quantum computer) that solves an optimization problem by using quantum annealing, instead of simulated annealing. 
     See, for example, Japanese Laid-open Patent Publication Nos. 3-251947 and 6-68056. 
     However, an individual unit (bit) of a conventional ising device realized by hardware modules is not connected to all the other bits. Namely, there is a constraint on the number of connections. For example, in the case of a quantum computer whose total bit number is 2,000, an individual quantum bit is connected to six quantum bits. In the case of an ising device whose total bit number is about 20,000 and that performs simulated annealing, an individual bit is connected to five bits. 
     Since conventional ising devices map and solve problems under this constrain on the number of connections, if the problem size is large, the mapping will be difficult. 
     In view of the above points, it is an object of the embodiments to provide an information processing apparatus, an ising device, and an information processing apparatus control method that are capable of calculating a large-scale problem in which relatively many variables are used. 
     SUMMARY 
     According to one aspect, there is provided an information processing apparatus including: a plurality of ising devices arranged in a matrix and connected to each other via a bus; and a control device, wherein each of the ising devices includes: a plurality of neuron circuits that each hold a first value based on a sum of values each obtained by multiplying one of a plurality of output signals from a plurality of connection destination neuron circuits by one of a plurality of weight values each representing connection strength between a corresponding neuron circuit and one of the plurality of connection destination neuron circuits, outputs 0 or 1 in accordance with a result of comparison between a second value obtained by adding a noise value to the first value with a threshold, receives an update signal when any one of the output signals changes, calculates a change amount of the first value in accordance with the update signal, and updates the first value by adding or subtracting the change amount to or from the first value, a memory that holds connection destination information in which items of first address information that identify the respective connection destination neuron circuits, items of second address information that identify ising devices including the respective connection destination neuron circuits among all the plurality of ising devices, and items of identification information about the respective weight values are associated with each other, a control circuit that outputs, when a first output signal of a first connection destination neuron circuit included in a first ising device other than the ising device including the control circuit among all the plurality of connection destination neuron circuits changes, a value corresponding to the first output signal that has changed and the update signal based on the connection destination information, and a router that receives a mode set value and determines whether to connect at least two neighboring ising devices, or a neighboring ising device and the control circuit in accordance with the mode set value, wherein the control device transmits the mode set value to the router. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  illustrates an example of an information processing apparatus according to a first embodiment; 
         FIG. 2  illustrates an example of neuron circuits; 
         FIG. 3  illustrates an example of a probability P i  (h i ) with which a state x i  represents 1; 
         FIG. 4  illustrates an example of a method of setting initial values of chip addresses and mode set values; 
         FIG. 5  illustrates an example of scan FFs that set chip addresses; 
         FIG. 6  illustrates another example of scan chains; 
         FIG. 7  illustrates an example of a router; 
         FIG. 8  illustrates an example of a switch unit connected to a port “EAST”; 
         FIG. 9  illustrates an example of mode set values stored in a mode register; 
         FIG. 10  illustrates another example of switch control; 
         FIG. 11  is a timing chart illustrating an example of a mode set value change method; 
         FIG. 12  illustrates an example of a router to which a group of circuits that reproduce waveforms and timing is connected; 
         FIG. 13  illustrates how a waveform and timing are reproduced; 
         FIG. 14  illustrates a multi-drop bus function; 
         FIG. 15  illustrates an example of connection destination information; 
         FIG. 16  is a flowchart illustrating an example of an operation of the information processing apparatus; 
         FIG. 17  is a timing chart illustrating an operation example performed when weight values are written; 
         FIG. 18  illustrates progress of simulated annealing; 
         FIG. 19  illustrates an example of an operation of an ising device that receives an update signal; 
         FIG. 20  is a conceptual diagram of a neural network realized by the information processing apparatus according to the first embodiment; 
         FIG. 21  illustrates an example of an information processing apparatus according to a second embodiment; 
         FIG. 22  illustrates an example of an information processing apparatus according to a third embodiment; 
         FIG. 23  illustrates a faster calculation method using parallelization; 
         FIG. 24  illustrates an advantageous effect provided by the faster calculation method using parallelization; 
         FIG. 25  illustrates a faster calculation method using a quantum Monte Carlo method; and 
         FIG. 26  illustrates an example of an ising device including neuron circuits different from the neuron circuits illustrated in  FIG. 2 . 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Hereinafter, embodiments will be described with reference to the accompanying drawings, wherein like reference characters refer to like elements throughout. 
     First Embodiment 
       FIG. 1  illustrates an example of an information processing apparatus  1  according to a first embodiment. 
     The information processing apparatus  1  includes a plurality of (m) ising devices  2   a   1  to  2   am  arranged in a matrix and a control device  3 . 
     For example, each of the ising devices  2   a   1  to  2   am  is realized by a single semiconductor integrated circuit (a chip). Of all the ising devices  2   a   1  to  2   am , neighboring ising devices are connectable via buses  4   a  to  4   c . For example, data is transmitted via the bus  4   a , addresses are transmitted via the bus  4   b , and mode set values are transmitted via the bus  4   c.    
     The connection topology of the ising devices  2   a   1  to  2   am  is not limited to the example in  FIG. 1 . Other examples of the connection topology will be described with reference to  FIGS. 21 and 22 . 
     Each of the ising devices  2   a   1  to  2   am  includes elements as described below.  FIG. 1  illustrates elements included in the ising device  2   ak.    
     The ising device  2   ak  includes a plurality of (n) neuron circuits  10   a   1  to  10   an , a memory  11 , a control circuit  12 , a router  13 , and transmission and reception circuits  14   a  to  14   d.    
     For example, a circuit configuration based on an algorithm called “DeGloria algorithm” may be used for the neuron circuits  10   a   1  to  10   an.    
     Each of the neuron circuits  10   a   1  to  10   an  based on the DeGloria algorithm holds a value (a local field value) based on a sum of values each of which is obtained by multiplying one of a plurality of output signals from a plurality of connection destination neuron circuits by one of a plurality of weight values each of which represents connection strength between a corresponding neuron circuit and one of the plurality of connection destination neuron circuits. In addition, each of the neuron circuits  10   a   1  to  10   an  outputs 0 or 1 in accordance with a result of comparison between a value obtained by adding a noise value to the corresponding local field value and a threshold (for example, 0). In addition, when any one of the output signals from the plurality of connection destination neuron circuits changes, each of the neuron circuits  10   a   1  to  10   an  receives an update signal from the control circuit  12  and calculates a change amount of the local field value in accordance with the update signal. In addition, each of the neuron circuits  10   a   1  to  10   an  updates the local field value by adding or subtracting the change amount to or from the local field value prior to the change of the output signal. 
     An example of a circuit diagram of the neuron circuits  10   a   1  to  10   an  will be described below with reference to  FIG. 2 . 
     The memory  11  holds connection destination information  11   a  in which items of address information that identify the connection destination neuron circuits connected to the neuron circuits  10   a   1  to  10   an , items of address information that identify the ising devices including the connection destination neuron circuits, and items of identification information about the weight values are associated with each other. An example of the connection destination information  11   a  will be described below with reference to  FIG. 15 . 
     Hereinafter, each item of address information that identifies a connection destination neuron circuit will be referred to as an internal address, and each item of address information that identifies an ising device will be referred to as a chip address. For example, these internal addresses and chip addresses are determined by the control device  3  in advance in accordance with a problem to be calculated and are stored in a register (not illustrated) (or the memory  11 ). 
     For example, a semiconductor storage device such as a flash memory may be used as the memory  11 . 
     When the output signal of a connection destination neuron circuit changes, the control circuit  12  outputs the connection destination information  11   a  and an update signal based on a value corresponding to the output signal that has changed. For example, the update signal is a value corresponding to the output signal that has changed or a weight value selection signal based on identification information about a corresponding weight value. 
     The control circuit  12  receives the chip address of the ising device including the connection destination neuron circuit whose output signal value has changed and the internal address of the connection destination neuron circuit via the router  13 . Next, the control circuit  12  compares these addresses with the chip addresses and internal addresses stored in the connection destination information  11   a . For example, if the received addresses match the internal address and the chip address of any one of the connection destination neuron circuits connected to the neuron circuit  10   a   1 , the control circuit  12  supplies the value corresponding to the output signal that has changed to the neuron circuit  10   a   1 . Next, the control circuit  12  supplies a selection signal for selecting a weight value used by the neuron circuit  10   a   1  to the neuron circuit  10   a   1  in accordance with the weight value identification information associated with the internal addresses and the chip addresses. 
     In addition, when the output signal of any one of the neuron circuits  10   a   1  to  10   an  changes, the control circuit  12  supplies a value corresponding to the output signal that has changed and the address (internal address) of the neuron circuit whose output signal has changed to the router  13 . Next, the control circuit  12  supplies a section signal based on the weight value identification information between the neuron circuit whose output signal has changed and the other neuron circuits of all the neuron circuits  10   a   1  to  10   an  to the other neuron circuits, along with the value corresponding to the output signal that has changed. 
     For example, the weight value identification information among the neuron circuits in a single ising device is stored in the memory  11 . In addition, the connection destination information  11   a  may include the weight value identification information among the neuron circuits in a single ising device. 
     For example, the control circuit  12  that performs the above operation may be realized by using a comparator circuit, a selection circuit, etc. The control circuit  12  may be a processor. Examples of the processor include a central processing unit (CPU), a micro processing unit (MPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), and a programmable logic device (PLD). The processor may be a combination of at least two of a CPU, an MPU, a DSP, an ASIC, and a PLD. 
     The router  13  receives mode set values and determines whether to connect at least two neighboring ising devices or a neighboring ising device and the control circuit  12  via the buses  4   a  to  4   c  in accordance with the mode set values. 
     The mode set values are stored in a mode register  13   a , which includes scan flip flops (scan FFs), for example. Initial values of the mode set values are set by using a signal line  5  and a scan chain including the scan FFs. When the mode set values are changed, for example, the mode set values transmitted via the bus  4   c  are written in the mode register  13   a.    
     The transmission and reception circuits  14   a  to  14   d  are connected to the router  13  and are used to exchange information (mode set values, addresses, data) with the ising devices neighboring the ising device  2   ak.    
     Of all the ising devices  2   a   1  to  2   am , the control device  3  selects an ising device having a neuron circuit whose output signal value is allowed to be updated (annealed). The control device  3  sets the mode set values so that the address of the neuron circuit whose output signal changes, the output signal outputted from the selected ising device, and a value corresponding to the output signal that has changed are supplied to the ising devices including the connection destination neuron circuits connected to this neuron circuit. 
     In addition, the control device  3  writes weight values in accordance with the problem to be solved in memories of the neuron circuits of the ising devices  2   a   1  to  2   am.    
     For example, the control device  3  that performs the above operation may be realized by using a processor. Examples of the processor may be a CPU, an MPU, a DSP, an ASIC, or a PLD. The processor may be a combination of at least two of a CPU, an MPU, a DSP, an ASIC, and a PLD. The control device  3  may be a personal computer (PC). 
     (Example of Neuron Circuits Based on DeGloria Algorithm) 
       FIG. 2  illustrates an example of neuron circuits. 
       FIG. 2  illustrates an example of the neuron circuits  10   a   1 ,  10   ai , and  10   an  of the n neuron circuits  10   a   1  to  10   an  illustrated in  FIG. 1 . The neuron circuits other than the neuron circuit  10   a   1 ,  10   ai , and  10   an  of the neuron circuits  10   a   1  to  10   an  have the same circuit configuration. While not illustrated in  FIG. 1 , a noise generation circuit  14  and a random signal generation circuit  15  are included in the ising device  2   ak.    
     The neuron circuit  10   a   1  includes a register  20   a   1 , selection circuits  21   a   1  and  22   a   1 , a multiplier circuit  23   a   1 , an adder circuit  24   a   1 , a register  25   a   1 , an adder circuit  26   a   1 , a comparator circuit  27   a   1 , an XOR circuit  28   a   1 , and a register  29   a   1 . The neuron circuit  10   ai  includes a register  20   ai , selection circuits  21   ai  and  22   ai , a multiplier circuit  23   ai , an adder circuit  24   ai , a register  25   ai , an adder circuit  26   ai , a comparator circuit  27   ai , an XOR circuit  28   ai , and a register  29   ai . The neuron circuit  10   an  includes a register  20   an , selection circuits  21   an  and  22   an , a multiplier circuit  23   an , an adder circuit  24   an , a register  25   an , an adder circuit  26   an , a comparator circuit  27   an , an XOR circuit  28   an , and a register  29   an.    
     The register  20   a   1  holds N weight values W 11  to W 1N , the register  20   ai  holds N weight value W i1  to W iN , and the register  20   an  holds N weight values W n1  to W nN . The neuron circuits  10   a   1  to  10   an  are connected to (N-n) neuron circuits in the ising devices other than the ising device  2   ak.    
     For example, among the weight values W i1  to W iN  stored in the register  20   ai , each of the weight values W i1  to W in  represents connection strength between the neuron circuit  10   ai  and one of the other neuron circuits of the neuron circuits  10   a   1  to  10   an  in the ising device  2   ak . In contrast, among the weight values W i1  to W iN , each of the weight values W in+1  to W iN  represents connection strength between the neuron circuit  10   ai  and one of the (N−n) neuron circuits in the ising devices other than the ising device  2   ak . For example, when n=1,024 and N=1,152, the neuron circuit  10   ai  is connected to 128 neuron circuits in the ising devices other than the ising device  2   ak . Needless to say, these numbers n and N are not limited to the above examples. 
     The control device  3  sets the above weight values in accordance with the problem to be calculated and stores the weight values in the registers  20   a   1  to  20   an . The weight values may be stored in a memory such as a random access memory (RAM). 
     The selection circuit  21   a   1  selects and outputs one of the weight values W 11  to W 1N  stored in the register  20   a   1  in accordance with a selection signal supplied by the control circuit  12 . The selection circuit  21   ai  selects and outputs one of the weight values W i1  to W iN  stored in the register  20   ai  in accordance with the selection signal. The selection circuit  21   an  selects and outputs one of the weight values W n1  to W nN  stored in the register  20   an  in accordance with the selection signal. 
     For example, when the output signal of the neuron circuit  10   a   1  changes, the selection circuits  21   a   1 ,  21   ai , and  21   an  of the neuron circuits  10   a   1 ,  10   ai , and  10   an  select the weight values W 11 , W i1 , and W n1 , respectively, in accordance with the selection signal. 
     Each of the selection circuits  22   a   1  to  22   an  selects and outputs 1 or −1 in accordance with a value (0 or 1) corresponding to the changed output value of a connection destination neuron circuit. This value is outputted from the control circuit  12 . When the value corresponding to the output value that has changed is 0, the selection circuits  22   a   1  to  22   an  select and output −1. When the value is 1, the selection circuits  22   a   1  and  22   an  select and output 1. The reason will be described below. 
     The multiplier circuit  23   a   1  outputs a product of the value outputted by the selection circuit  21   a   1  and the value outputted by the selection circuit  22   a   1 . The multiplier circuit  23   ai  outputs a product of the value outputted by the selection circuit  21   ai  and the value outputted by the selection circuit  22   ai . The multiplier circuit  23   an  outputs a product of the value outputted by the selection circuit  21   an  and the value outputted by the selection circuit  22   an.    
     The adder circuit  24   a   1  adds up the value outputted by the multiplier circuit  23   a   1  and the value stored in the register  25   a   1  and outputs a sum. The adder circuit  24   ai  adds up the value outputted by the multiplier circuit  23   ai  and the value stored in the register  25   ai  and outputs a sum. The adder circuit  24   an  adds up the value outputted by the multiplier circuit  23   an  and the value stored in the register  25   an  and outputs a sum. 
     The register  25   a   1  captures the value outputted by the adder circuit  24   a   1  in synchronization with a clock signal (not illustrated). The register  25   ai  captures the value outputted by the adder circuit  24   ai  in synchronization with the clock signal (not illustrated). The register  25   an  captures the value outputted by the adder circuit  24   an  in synchronization with the clock signal (not illustrated). The registers  25   a   1  to  25   an  are flip flops, for example. The initial values of the registers  25   a   1  to  25   an  are bias values described below. 
     These values captured by the registers  25   a   1  to  25   an  are the local field values described above, which are denoted by h 1 , h i , and h n , respectively, in  FIG. 2 . 
     The adder circuit  26   a   1  adds a noise value outputted by the noise generation circuit  14  to the value outputted by the register  25   a   1  and outputs a sum. The adder circuit  26   ai  adds the noise value outputted by the noise generation circuit  14  to the value outputted by the register  25   ai  and outputs a sum. The adder circuit  26   an  adds the noise value outputted by the noise generation circuit  14  to the value outputted by the register  25   an  and outputs a sum. An example of the noise value will be described below. 
     The comparator circuit  27   a   1  outputs 1 when the value outputted by the adder circuit  26   a   1  is larger than a threshold. Otherwise, the comparator circuit  27   a   1  outputs 0. The comparator circuit  27   ai  outputs 1 when the value outputted by the adder circuit  26   ai  is larger than the threshold. Otherwise, the comparator circuit  27   ai  outputs 0. The comparator circuit  27   an  outputs 1 when the value outputted by the adder circuit  26   an  is larger than the threshold. Otherwise, the comparator circuit  27   an  outputs 0. 
     When the ising device  2   ak  performs an annealing operation, one of the comparator circuits  27   a   1  to  27   an  is randomly enabled by the random signal generation circuit  15 . The other comparator circuits are disabled. For example, the random signal generation circuit  15  may include linear feedback shift registers (LFSRs). 
     The XOR circuit  28   a   1  outputs 0 when the value outputted by the comparator circuit  27   a   1  and the value stored in the register  29   a   1  match. Otherwise, the XOR circuit  28   a   1  outputs 1. The XOR circuit  28   ai  outputs 0 when the value outputted by the comparator circuit  27   ai  and the value stored in the register  29   ai  match. Otherwise, the XOR circuit  28   ai  outputs 1. The XOR circuit  28   an  outputs 0 when the value outputted by the comparator circuit  27   an  and the value stored in the register  29   an  match. Otherwise, the XOR circuit  28   an  outputs 1. 
     The register  29   a   1  captures the value outputted by the comparator circuit  27   a   1  when the value outputted by the XOR circuit  28   a   1  is 1. As a result, the output signal (state) x 1  of the neuron circuit  10   a   1  changes (is updated). The register  29   ai  captures the value outputted by the comparator circuit  27   ai  when the value outputted by the XOR circuit  28   ai  is 1. As a result, the output signal (state) x i  of the neuron circuit  10   ai  changes. The register  29   an  captures the value outputted by the comparator circuit  27   an  when the value outputted by the XOR circuit  28   an  is 1. As a result, the output signal (state) x n  of the neuron circuit  10   an  changes. 
     These neuron circuits  10   a   1  to  10   an  are small-scale hardware modules that realize an operation of an ising energy function. For example, an ising energy function E(x) is defined by the following expression (1). 
     
       
         
           
             
               
                 
                   
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     The first term on the right side of expression 1 is directed to all the combinations of two neuron circuits selectable from all the neuron circuits without missing any neuron circuit or redundantly counting any neuron circuit. More specifically, the first term represents the sum of products, each of which is obtained by multiplying states of two neuron circuits by a weight value associated with the two neuron circuits. In expression 1, W ij =W ji , and W ii =0. 
     The second term on the right side of expression 1 represents the sum of products, each of which is obtained by multiplying a bias value of an individual one of the neuron circuits by a state of the individual one of the neuron circuits. In expression 1, b i  represents the bias value of the i-th neuron circuit. 
     To express the above energy function E(x) by using hardware modules, the neuron circuits  10   a   1  to  10   an  illustrated in  FIG. 2  calculate local field values h 1  to h n , respectively. For example, the local field value h i  of the neuron circuit  10   ai  is expressed by the following expression (2). 
     
       
         
           
             
               
                 
                   
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     The first term on the right side of expression 2 represents the sum of products, each of which is obtained by multiplying a weight value representing connection strength between the i-th neuron circuit  10   ai  and one of the neuron circuits connected to the neuron circuit  10   ai  by a state of that one neuron circuit. 
     When the state of only one of the neuron circuits in the information processing apparatus  1  is allowed to be updated at one time, an individual one of the connection destination neuron circuits adds or subtracts the amount of the change made by the update to or from the corresponding original local field value. 
     For example, when the state x j  (0 or 1) of a neuron circuit connected to the neuron circuit  10   ai  has changed to 1−x j , the change amount Δh i  of the local field value of the neuron circuit  10   ai  is expressed by the following expression (3).
 
Δ h   i   =h   i ∥ x     j     −1−x     j     −h   i   =W   ij (1−2 x   j )  (3)
 
     In expression (3), 1−2x j  represents +1 when the state x j  has changed from 0 to 1 and represents −1 when the state x j  has changed from 1 to 0. 
     This operation using 1−2x j  may be realized by using the selection circuit  22   ai  illustrated in  FIG. 2 . 
     (Example of Noise Value) 
     In the neuron circuits  10   a   1  to  10   an  as illustrated in  FIG. 2 , to perform simulated annealing, the comparator circuits  27   a   1  to  27   an  compare the values obtained by adding a noise value to the local field values h 1  to h n  with the above thresholds, respectively. 
     For example, the noise value is added so that a probability with which an individual one of the output values of the comparator circuits  27   a   1  to  27   an  (the states x 1  to x n  of the neuron circuits  10   a   1  to  10   an ) represents 1 accords with a sigmoid function. For example, the noise value is added so that a probability P i (h i ) with which the state x i  of the neuron circuit  10   ai  represents 1 satisfies the relationship of the following expression (4).
 
 P   i ( h   i )=1/[1+exp(− h   i   /T )]  (4)
 
     In expression (4), T represents an effective temperature. 
     To obtain the probability P i (h i ) as illustrated in expression (4), a probability density function p(ns) of a noise value ns to be added is expressed by the following expression (5).
 
 p ( ns )=exp(− h   i   /T )/[1+exp(− h   i   /T )] 2   (5)
 
       FIG. 3  illustrates an example of the probability P i (h i ) with which the state x i  represents 1. 
     The horizontal axis represents a value obtained by adding the noise value ns to the local field value h i , and the vertical axis represents the probability with which the state x i  represents 1. 
     A waveform  30  indicates the probability P i (h i ) with which the state x i  represents 1 when a sum of the noise value ns that accords with the probability density function p(ns) as illustrated in expression (5) and the local field value h i  is inputted to the comparator circuit  27   ai . A waveform  31  indicates the probability P i (h i ) with which the state x i  represents 1 when the local field value h i  is inputted to the comparator circuit  27   ai.    
     As indicated by the waveform  31 , if the noise value ns is not added to the local field value h i , when the local field value h i  is equal to or less than a threshold Vth, P i (h i )=0. However, when the local field value h i  exceeds the threshold Vth, P i (h i )=1. 
     In contrast, as indicated by the waveform  30 , if the noise value ns is added to the local field value h i , the probability P i (h i ) changes with the sigmoid function. 
     (Setting of Initial Values of Chip Addresses and Mode Set Values) 
       FIG. 4  illustrates an example of a method of setting initial values of chip addresses and mode set values. 
     For example, the ising devices  2   a   1  to  2   am  are connected to a single scan chain  40 . The control device  3  uses the scan chain  40  to set initial values of chip addresses and mode set values in the ising devices  2   a   1  to  2   am.    
       FIG. 5  illustrates an example of scan FFs that set chip addresses. 
     Scan FF units  13   b   1  to  13   bm  are connected in series with each other, and each one of the scan FF units  13   b   1  to  13   bm  includes scan FFs, the number of which corresponds to the bit number of the chip address of the corresponding one of the ising devices  2   a   1  to  2   am.    
     For example, when the bit number of the chip address is p bits, the scan FF unit  13   b   1  includes scan FFs  41   a   1  to  41   ap  connected in series with each other, as illustrated in  FIG. 5 . The scan FF unit  13   bm  also includes scan FFs  42   a   1  to  42   ap  connected in series with each other. 
     For example, the scan FF units  13   b   1  to  13   bm  are arranged in the routers of the respective ising devices  2   a   1  to  2   am.    
     From its terminal  44 , the control device  3  sequentially outputs the bit values of the chip addresses set in the ising devices  2   a   1  to  2   am  one bit at a time. In addition, the control device  3  outputs a clock signal from its terminal  45 . The clock signal is supplied to the scan FF units  13   b   1  to  13   bm  in a parallel manner. The bit values are transmitted to a downstream scan FF in synchronization with a rising edge (or a falling edge) of the clock signal. 
     After outputting the clock signal for m×p cycles, the control device  3  brings the logic level of a read enable signal outputted from its terminal  43  to an H (High) level, for example. As a result, the bit values are read from the scan FF units  13   b   1  to  13   bm , and the chip addresses are stored in registers (not illustrated) arranged in the scan FF units  13   b   1  to  13   bm , respectively. 
     For example, the initial values of the mode set values are stored in mode registers in the routers by using another scan chain (for example, in the mode register  13   a  in the router  13  in the case of the ising device  2   ak  in  FIG. 1 ). 
     While the scan chain  40  forms a single path in  FIG. 4 , the present embodiment is not limited to this example. 
       FIG. 6  illustrates another example of scan chains. 
       FIG. 6 , q scan chains  40   a   1  to  40   aq  are connected to the control device  3  in a parallel manner. Among the ising devices  2   a   1  to  2   am  arranged in a matrix, those ising devices arranged in the same row are connected to the same scan chain. 
     By connecting the scan chains in a parallel manner, the initial values of the chip addresses and the mode set values are allocated to the ising devices  2   a   1  to  2   am  more quickly than when the scan chain  40  is used. 
     (Configuration Example of Router  13 ) 
       FIG. 7  illustrates an example of the router  13 . 
     The router  13  includes five ports “NORTH”, “SOUTH”, “EAST”, “WEST”, and “LOCAL”, other than a port used for scan-in and scan-out. 
     For example, when transferring information transmitted from a neighboring ising device on the left side of the ising device  2   ak  in  FIG. 7  to a neighboring ising device on the right side in  FIG. 7 , the router  13  uses the two ports “EAST” and “WEST”. 
     When transferring information transmitted from a neighboring ising device to the ising device  2   ak  to the control circuit  12  or when transferring information transmitted from the control circuit  12  to a neighboring ising device, the router  13  uses the port “LOCAL”. 
     The router  13  also uses the port “LOCAL” when changing the mode set values stored in the mode register  13   a.    
       FIG. 8  illustrates an example of a switch unit  51  connected to the port “EAST”. 
     Information supplied via the port “EAST” is supplied to the switch unit  51  via a buffer circuit  50 . 
     The switch unit  51  includes switches  51   a  to  51   d . The switch  51   a  is connected between the output terminal of the buffer circuit  50  and the port “LOCAL”. The switch  51   b  is connected to the output terminal of the buffer circuit  50  and the port “NORTH”. The switch  51   c  is connected to the output terminal of the buffer circuit  50  and the port “WEST”. The switch  51   d  is connected to the output terminal of the buffer circuit  50  and the port “SOUTH”. 
     For example, the switches  51   a  to  51   d  are n channel metal-oxide semiconductor field effect transistors (MOSFETs). In this case, for example, when a gate voltage generated by a switch control circuit not illustrated in the router  13  is brought to an H level, the switches  51   a  to  51   d  are set to an on-state. When the gate voltage is brought to an L (Low) level, the switches  51   a  to  51   d  are set to an off-state. The switch control circuit generates the gate voltage in accordance with the mode set values stored in the mode register  13   a.    
       FIG. 9  illustrates an example of the mode set values stored in the mode register  13   a.    
       FIG. 9  illustrates an example of the mode set values for controlling switches in a switch unit connected to the five ports “NORTH”, “SOUTH”, “EAST”, “WEST”, and “LOCAL”. In the example in  FIG. 9 , the mode set values are represented by a group of control codes each of which is expressed by a combination of initial letters of two of the ports “NORTH”, “SOUTH”, “EAST”, “WEST”, and “LOCAL”. 
     For example, “EN” is a control code for controlling the switch  51   b  included in the switch unit  51  that is connected to the port “EAST” illustrated in  FIG. 8  and that determines connection or disconnection between the ports “EAST” and “NORTH”. 
     In addition, “WS” is a control code for controlling a switch included in a switch unit (not illustrated) that is connected to the “WEST” port and that determines connection or disconnection between the ports “WEST” and “SOUTH”. 
     An individual control code is represented by, for example, 0 or 1. When a control code is 0, the switch controlled by this control code is set to an off-state. When the control code is 1, the switch controlled by this control code is set to an on-state. 
     For example, when (EN, EW, ES, EL)=(1, 0, 0, 1), the switches  51   a  and  51   b  in the switch unit  51  illustrated in  FIG. 8  are set to an on-state while the switches  51   c  and  51   d  are set to an off-state. 
       FIG. 10  illustrates another example of switch control. 
     For example, instead of holding the above control codes as the mode set values, the mode register  13   a  may hold identification information indicating mode names. 
     In addition, a memory  13   c  in the router  13  holds a conversion table  13   c   1  indicating a relationship between the above identification information and control codes. 
     A switch control circuit  13   d  in the router  13  refers to the conversion table  13   c   1  stored in the memory  13   c  in the router  13  and determines the control codes from the above identification information. The switch control circuit  13   d  outputs a switch control signal based on the control codes and controls the switches  51   a  to  51   d , etc. 
     In this way, the number of bits of the mode set values stored in the mode register  13   a  is reduced, and the bandwidth needed to transfer the mode set values is reduced. 
       FIG. 11  is a timing chart illustrating an example of a mode set value change method. 
     When changing the mode set values stored in the mode register  13   a  in the router  13  in the ising device  2   ak , the control device  3  transmits the chip address of the ising device  2   ak  and mode set values via the buses  4   b  and  4   c . In addition, the control device  3  sets the logic level of a mode write enable signal transmitted via a control signal line not illustrated to an H level. 
     In response, the router  13  receives the mode write enable signal from one of the four ports “NORTH”, “SOUTH”, “EAST”, and “WEST” in accordance with the current mode set values. Next, in synchronization with a rising edge of the mode write enable signal (at timing t 1 ), the router  13  compares its own chip address with the chip address supplied from the port that has received the mode write enable signal. 
     If both the chip addresses match, the router  13  captures the mode set values from the port and updates the mode set values stored in the mode register  13   a  via the port “LOCAL”. 
     (Function of Reproducing Waveforms and Timing) 
     In the information processing apparatus  1  according to the present embodiment, signal transmission is performed within a chip and between chips. To reduce deformation of a signal waveform, for example, the following group of circuits is connected to the router  13 . 
       FIG. 12  illustrates an example of the router  13  to which a group of circuits that reproduce waveforms and timing is connected 
     In the example in  FIG. 12 , the transmission and reception circuit  14   b  receives a signal and transmits this signal to the transmission and reception circuit  14   d  via the router  13 , and the transmission and reception circuit  14   d  transmits this signal. However, the same circuit group is arranged for the signal transmission in a different direction. 
     Flip flops  60  and  61  connected in parallel with each other are arranged between the transmission and reception circuit  14   b  and the router  13 . In addition, a 2:1 multiplexer  62  and a buffer circuit  63  are arranged between the router  13  and the transmission and reception circuit  14   d.    
     For example, in synchronization with a rising edge of a clock signal clk outputted by a phase adjustment circuit  64 , the flip flop  60  captures the value of the signal supplied by the transmission and reception circuit  14   b  and outputs the value to the router  13 . For example, in synchronization with a falling edge of the clock signal clk outputted by the phase adjustment circuit  64 , the flip flop  61  captures the value of the signal supplied by the transmission and reception circuit  14   b  and outputs the value of the router  13 . 
     The 2:1 multiplexer  62  receives the two signals outputted by the flip flops  60  and  61  via the router  13  and outputs one of the signals, depending on the logic level (H or L level) of the clock signal clk. The output signal of the 2:1 multiplexer  62  is supplied to the transmission and reception circuit  14   d  via the buffer circuit  63 . 
     For example, the phase adjustment circuit  64  receives a global clock signal gclk from the control device  3 . Next, the phase adjustment circuit  64  outputs the clock signal clk obtained by adjusting the phase of the global clock signal gclk so that the flip flops  60  and can capture the signal outputted by the transmission and reception circuit  14   b  at the middle of the eye pattern of the signal. 
       FIG. 13  illustrates how a waveform and timing are reproduced. 
     The phase of the clock signal clk has been adjusted so that a rising edge at timing t 2  corresponds to about the middle of the eye pattern of a signal (Data in) supplied by the transmission and reception circuit  14   b.    
     The buffer circuit  63  outputs a signal (Data out) that lags the Data in by a predetermined time. By connecting the above circuit group to the router  13 , the Data out having approximately the same waveform as that of the Data in is obtained. 
     (Multi-Drop Bus Function) 
       FIG. 14  illustrates a multi-drop bus function. 
     In the information processing apparatus  1  according to the present embodiment, the buses  4   a  to  4   c  function as a multi-drop bus capable of exchanging signals among the connected ising devices  2   a   1  to  2   am  as illustrated in  FIG. 14 . For example, when the logic level of the mode write enable signal transmitted through a control signal line  4   d  for delivering control signals is set to an H level, an ising device whose chip address matches the chip address transmitted through the bus  4   b  captures the mode set values transmitted through the bus  4   c.    
     (Example of Connection Destination Information  11   a  Stored in Memory  11 ) 
       FIG. 15  illustrates an example of connection destination information. 
       FIG. 15  illustrates an example of connection destination information  70  associated with the neuron circuit  10   ai  illustrated in  FIG. 2  among the neuron circuits  10   a   1  to  10   an  in the ising device  2   ak.    
     In the connection destination information  70 , internal addresses that identify the connection destination neuron circuits, respectively, connected to the neuron circuit  10   ai , chip addresses that identify the ising devices including the connection destination neuron circuits, respectively, and weight value identification information are associated with each other. 
     For example, the first row in the connection destination information  70  indicates that the neuron circuit  10   ai  is connected to a neuron circuit whose internal address is 1 in an ising device whose chip address is 0. In addition, the first row indicates that the weight value identification information indicating connection between this neuron circuit and the neuron circuit  10   ai  is (i, n+1), in which n is the number of neuron circuits  10   a   1  to  10   an  in the ising device  2   ak . When n=1,024, the identification information is (i, 1025). 
     In addition, in the connection destination information  70 , n1 is the number of neuron circuits connected to the neuron circuit  10   ai  in the ising device whose chip address is 0. In addition, n2 is the number of neuron circuits connected to the neuron circuit  10   ai  in the ising device whose chip address is 2. 
     When the number of ising devices  2   a   1  to  2   am  is 1,024, the chip address is expressed by 10 bits, for example. 
     These items of correspondence information among the weight value identification information, the chip addresses, and the internal addresses are listed in the ascending order of the weight value identification information. 
     The connection destination information associated with the neuron circuits other than the neuron circuit  10   ai  of all the neuron circuits  10   a   1  to  10   an  in the ising device  2   ak  is configured in the same way. 
     (Example of Annealing Operation) 
     Hereinafter, an example of an operation (an annealing operation) of the information processing apparatus  1  controlled by the control device  3  will be described. 
       FIG. 16  is a flowchart illustrating an example of an operation of the information processing apparatus  1 . 
     First, for example, by using the scan chain  40  as illustrated in  FIG. 4  or the scan chains  40   a   1  to  40   aq  as illustrated in  FIG. 6 , the control device  3  sets initial values of the chip addresses and the mode set values in registers in the ising devices  2   a   1  to  2   am  (step S 1 ). For example, in the case of the ising device  2   ak , the control device  3  sets the initial values of the mode set values in the mode register  13   a  and sets the chip address in a register not illustrated in the router  13 . 
     Next, the control device  3  writes (sets) weight values in accordance with the problem to be calculated in registers (or memories) in the neuron circuits in the ising devices  2   a   1  to  2   am  (step S 2 ). 
       FIG. 17  is a timing chart illustrating an operation example performed when the weight values are written. 
     When writing weight values in the registers  20   a   1  to  20   an  in the neuron circuits  10   a   1  to  10   an  in the ising device  2   ak , the control device  3  transmits the chip address of the ising device  2   ak  and the weight values through the buses  4   a  and  4   b . For example, the control device  3  sets the logic level of a wait write enable signal to be transmitted through the control signal line  4   d  as illustrated in  FIG. 14  to an H level. 
     In accordance with the current mode set values, the router  13  receives the wait write enable signal from one of the four ports “NORTH”, “SOUTH”, “EAST”, and “WEST”. Next, in synchronization with a rising edge of the mode write enable signal (at timing t 3 ), the router  13  compares the chip address supplied from the port that has received the mode write enable signal with the chip address of the corresponding ising device. 
     Next, when both the chip addresses match, the router  13  captures the weight values from the above port and writes the weight values in the registers  20   a   1  to  20   an  via the port “LOCAL”. 
     The control device  3  writes weight values in the same way in registers (or memories) in the neuron circuits in the other ising devices. 
     Next, the control device  3  initializes the states of the neuron circuits in all the chips (the ising devices  2   a   1  to  2   an ) (step S 3 ). For example, the control device  3  resets the values in the registers holding the local field values of the neuron circuits via a control signal line not illustrated. 
     Next, among the ising devices  2   a   1  to  2   an , the control device  3  selects a single ising device (a chip to be annealed) that is operated to perform an annealing operation (step S 4 ). For example, the control device  3  randomly selects one of the ising devices  2   a   1  to  2   an . Next, by transmitting a control signal, the control device  3  disables the comparator circuits in the neuron circuits in the ising devices other than the selected ising device, the comparator circuits determining output signal values, so that the output signal values will not change. 
     In the selected ising device, a single neuron circuit whose state is allowed to be updated is randomly selected (step S 5 ). The following description will be made assuming that the ising device  2   ak  has been selected in step S 4 . In this case, the random signal generation circuit  15  allows updating one of the states of the neuron circuits  10   a   1  to  10   an.    
     For example, when updating of the state x i  of the neuron circuit  10   ai  is allowed, if a value obtained by adding a noise value to the local field value h i  exceeds a threshold, the state x i  is set to 1. When the original value of the state x i  is 0, the XOR  28   i  outputs 1 and notifies the control circuit  12  that the state x i  has been updated. 
     When notified that the state x i  has been updated, the control circuit  12  supplies a selection signal for causing the other neuron circuits in the ising device  2   ak  to select a weight value that represents connection strength with the neuron circuit  10   ai  and the value of the updated state x i . 
     When the number of operations of selecting a neuron circuit whose state is allowed to be updated is below a predetermined number cnt 1  (step S 6 : NO), the processing returns to step S 5 . 
     Each time the control device  3  selects a neuron circuit whose state is allowed to be updated, for example, the control device  3  causes the noise generation circuit  14  to gradually drop the amplitude of the noise. In this way, simulated annealing is performed. 
       FIG. 18  illustrates progress of simulated annealing. 
     The vertical axis represents energy E, and the horizontal axis represents combinations q K  of states of all the neuron circuits. The combinations q K  are represented by “000 . . . 0” to “111 . . . 1”.  FIG. 18  illustrates how the convergence into an optimal solution is achieved as the noise amplitude is dropped from W1 to W3. Dropping the noise amplitude means dropping the effective temperature T in expression (5). 
     When the noise amplitude is W1, even when an individual solution reaches a local solution q k1 , q k2 , q k4 , or q k5  (a solution when the energy represents a local minimal value), the local solution can change in the direction of higher energy. Thus, these solutions can shift from the local solutions. As the noise amplitude gradually drops to W2 and W3, the change of the individual solution is also gradually limited, and the convergence into an optimal solution q k3  (a solution when the energy represents a minimum value) is finally achieved. 
     In simulated annealing, since it takes time to achieve the convergence into an optimal solution, the number of operations of selecting a neuron circuit whose state is allowed to be updated is limited to the number cnt 1 . To obtain a solution having smaller energy, a quantum Monte Carlo method may be used, for example. 
     In the processing illustrated in  FIG. 16 , when the number of selection operations reaches the number cnt 1  (step S 6 : YES), the control circuit  12  notifies the router  13  of the internal address of the neuron circuit whose state has changed before and after the selection corresponding to the number cnt 1  and a value corresponding to the changed state. 
     The router  13  broadcasts the internal address and an update signal including the value corresponding to the changed state by using the buses  4   a  and  4   b , for example. When the number of neuron circuits  10   a   1  to  10   an  is n=1,024, the router  13  broadcasts up to 1,024 update signals. For example, the router  13  broadcasts the update signals in the ascending order of the internal addresses of the neuron circuits. 
     In this operation, the control device  3  sets the mode set values in accordance with the above method so that the update signals are broadcast to the ising devices  2   a   1  to  2   am  (except the ising device  2   ak ) (step S 7 ). 
     When an ising device receives the update signal and determines that the state of a connection destination neuron circuit connected to a neuron circuit included in the ising device has changed, the ising device updates the local field value of the neuron circuit (step S 8 ). 
       FIG. 19  illustrates an example of an operation of an ising device that receives an update signal. 
       FIG. 19  will be described by using the ising device  2   ak  illustrated in  FIG. 1  as an example. The illustration of the router  13 , etc. is omitted in  FIG. 19 . 
     Selection circuits  12   a   1  to  12   an  are included in the control circuit  12  illustrated in  FIG. 1 . The control circuit  12  receives the internal address of a neuron circuit whose state has changed of all the neuron circuits included in a chip to be annealed and a value corresponding to the changed state as an update signal via the buses  4   a  and  4   b  and the transmission and reception circuit  14   b.    
     For example, when x is supplied as the chip address of the chip to be annealed via the bus  4   b , if the control circuit  12  receives internal address  2  as an update signal, the control circuit  12  refers to connection destination information  11   a   1  to  11   an . In the connection destination information  11   a   1  to  11   an , the internal addresses of the connection destination neuron circuits of the neuron circuits  10   a   1  to  10   an , the chip addresses of the ising device including the connection destination neuron circuits, and weight value identification information are associated with each other. 
     As illustrated in  FIG. 19 , when the chip address is x, internal address  2  is included in the connection destination information  11   a   1 . In this case, the selection circuit  12   a   1  supplies the value of the changed state of the neuron circuit received as an update signal to the neuron circuit  10   a   1 . 
     While not illustrated, a selection signal for selecting a weight value is also supplied to the neuron circuit  10   a   1  in accordance with the weight value identification information corresponding to chip address x and internal address  2  in the connection destination information  11   a   1 . 
     The neuron circuit  10   a   1  updates the local field value in accordance with the selection signal and the value of the updated state. 
     Next, when the number of operations of selecting a chip to be annealed is less than a predetermined number cnt 2  (step S 9 : NO), the processing returns to step S 4 . 
     When the number of operations of selecting a chip to be annealed reaches the number cnt 2  (step S 9 : YES), the control device  3  ends the annealing operation. 
     The order of the above steps is not limited to the above example. For example, the control device  3  may set mode set values after step S 4 . 
     In addition, while the router  13  broadcasts the update signals when the number of selection operations reaches the number cnt 1  in the above example, the router may broadcast the update signals each time a neuron circuit is selected. 
     The control device  3  obtains a solution to the problem by reading the states of all the neuron circuits after the above processing. For example, by using a scan chain, the control device  3  reads the states of all the neuron circuits. 
     For example, the read states are displayed by a display device (not illustrated) connected to the control device  3 . 
     With the information processing apparatus  1 , each of the ising devices  2   a   1  to  2   am  having a plurality of neuron circuits includes a memory holding connection destination information including the addresses of connection destination neuron circuits and the addresses of the ising devices including the connection destination neuron circuits and a router capable of changing the connection destinations. In addition, each of the ising devices  2   a   1  to  2   am  reflects neuron states of other ising devices obtained via the corresponding router on its own neuron circuits in accordance with the connection destination information. In this way, the inter-neuron-circuit connection number is increased, and a large-scale operation is performed. 
     For example, while it is difficult to cause integrated circuits on a single chip to calculate an optimization problem in which 10 3  to 10 6  or more variables are used, since the information processing apparatus  1  functions as a single ising device by using many chips, the information processing apparatus  1  is able to perform such a calculation easily. 
       FIG. 20  is a conceptual diagram of a neural network realized by the information processing apparatus according to the present embodiment. 
     In the example in  FIG. 20 , a neural network is illustrated in which six neuron units (for example, neuron units  80 ) are interconnected. In each of the neuron units, eight neurons (for example, neurons  80   a ) are connected to with each other. 
     A single neuron unit corresponds to a single ising device (a chip), and a single neuron corresponds to a single neuron circuit. 
     While the number of connections among the neuron units could be a constraint when a problem mapping is performed (setting of the weight values=programming), in many cases programming is possible without problem if the number of connections among the neuron units is about 1/10 of the number of connections among the neuron units. 
     Second Embodiment 
       FIG. 21  illustrates an example of an information processing apparatus  1   a  according to a second embodiment. Like reference characters refer to like elements in  FIGS. 1 and 21 . 
     The connection topology of the ising devices (chips) of the information processing apparatus  1   a  according to the second embodiment differs from that of the information processing apparatus  1  in  FIG. 1 . 
     The connection topology of the chips of the information processing apparatus  1   a  is a one-dimensional (1D) torus. While the ising devices  2   a   1  to  2   am  are arranged in a matrix, among the plurality of ising devices arranged in a row, the ising devices arranged at both ends of the row are connected to each other via buses. 
     For example, as illustrated in  FIG. 21 , among the plurality of ising devices arranged in the first row, ising devices  2   ax  and  2   am  at both ends are connected to each other via buses  4   a   1  to  4   c   1 . 
     By using such a connection topology, the transmission and reception circuits of the ising devices around the periphery of the array of the ising devices  2   a   1  to  2   am  arranged in a matrix are used more. Thus, decrease in the bandwidth and the connection number is reduced. 
     As another example of the 1D torus, among the plurality of ising devices arranged in a column, the ising devices arranged at both ends of the column may be connected to each other via buses. 
     Third Embodiment 
       FIG. 22  illustrates an example of an information processing apparatus  1   b  according to a third embodiment. Like reference characters refer to like elements in  FIGS. 21 and 22 . 
     The connection topology of the ising devices (chips) of the information processing apparatus  1   b  according to the third embodiment differs from that of the information processing apparatus  1   a  illustrated in  FIG. 21 . 
     The connection topology of the chips of the information processing apparatus  1   b  is a two-dimensional (2D) torus. While ising devices  2   a   1  to  2   am  are arranged in a matrix, among the plurality of ising devices arranged in a row, the ising devices arranged at both ends of the row are connected to each other via buses. In addition, among the plurality of ising devices arranged in a column, the ising devices arranged at both ends of the column are also connected to each other via buses. 
     For example, as illustrated in  FIG. 22 , among the plurality of ising devices arranged in the first column, ising devices  2   a   1  and  2   am  at both ends of the column are connected to each other via buses  4   a   2  to  4   c   2 . 
     By using such a connection topology, the transmission and reception circuits of the ising devices around the periphery of the array of the ising devices  2   a   1  to  2   am  arranged in a matrix are used more. Thus, decrease in the bandwidth and the connection number is further reduced. 
     (Faster Calculation Method) 
     As described above, in simulated annealing, since it takes time to obtain an optimal solution, it is desirable that the following faster calculation method be used. 
       FIG. 23  illustrates a method of faster calculation method using parallelization. 
     For example, the control device  3  divides all neuron circuits  91   a   1  to  91   a M into a plurality of ensembles  90   a   1  to  90   az  with which the same problem is mapped. The ensembles  90   a   1  to  90   az  have the same connection relationship about a plurality of neuron circuits included therein (corresponding to setting of the weight values). In addition, the control device  3  sets weight values so that a neuron circuit belonging to one ensemble is not connected to any of the other neuron circuits belonging to any of the other ensembles. 
     The control device  3  performs annealing operations in a parallel manner by using each of the ensembles  90   a   1  to  90   az . The same temperature (noise width) is used among the ensembles  90   a   1  to  90   az.    
     Next, the control device  3  compares the energy values of the ensembles  90   a   1  to  90   az  obtained after the annealing operations and selects a combination of states of neuron circuits included in an ensemble having a minimum energy as a solution to the problem. 
     In this way, by solving the same problem in a parallel manner by using the plurality of ensembles  90   a   1  to  90   az , the time needed for the annealing operations (for example, the numbers cnt 1  and cnt 2  illustrated in  FIG. 16 ) is shortened. Even with the time shortened, a value closer to an optimal solution is still obtained. 
       FIG. 24  illustrates an advantageous effect provided by the faster calculation method using parallelization. 
       FIG. 24  illustrates a simulation result of the clock cycle number achieving the target accuracy rate 99% when an information processing apparatus performs parallel calculation on a problem that occurs randomly by using each of the ensembles  90   a   1  to  90   az  in  FIG. 23  as a single chip (a single ising device). The clock cycle number is the cycle number of a clock signal supplied to the registers  25   a   1  to  25   an  of the neuron circuits  10   a   1  to  10   an  illustrated in  FIG. 2 . In addition, each of the ensembles  90   a   1  to  90   az  includes 64 neuron circuits. 
     In  FIG. 24 , the vertical axis represents the clock cycle number, and the horizontal axis represents the parallelization number (the number of chips). 
     As illustrated in  FIG. 24 , the clock cycle number achieving the target accuracy rate 99% decreases as the parallelization number increases. For example, the clock cycle number when the parallelization number is 100 is less by three digits or more than that of when no parallelization is performed. Namely, faster calculation is achieved. 
     As a faster calculation method, a quantum Monte Carlo method may be applied. 
       FIG. 25  illustrates a faster calculation method using a quantum Monte Carlo method. Like reference characters refer to like elements in  FIGS. 23 and 25 . 
     In the quantum Monte Carlo method, as in the parallelization method illustrated in  FIG. 23 , while the same problem is mapped with each of a plurality of ensembles  90   a   1  to  90   az , neuron circuits of neighboring ensembles are connected to each other (the weight value is 1). For example, neuron circuits  91   a   1 ,  91   ai , and  91   aj  are connected to each other. 
     The control device  3  solves a problem by recognizing the problem as a large problem established by z ensembles  90   a   1  to  90   az.    
     Detailed description of the quantum Monte Carlo method will be omitted (about the quantum Monte Carlo method, see ‘M. Suzuki, “Relationship between d-Dimensional Quantal Spin Systems and (d+1)-Dimensional Ising Systems”, Progress of Theoretical Physics, Vol. 56, No. 5, pp. 1454-1469, (1976)’ and ‘G. E. Santoro, R. Martonak, E. Tosatti, and R. Car, “Theory of Quantum Annealing of an Ising Spin Glass”, Science Vol. 295, pp. 2427-2430, (2002)’. 
     (Another Example of Neuron Circuits) 
       FIG. 26  illustrates an example of an ising device  2   b  including neuron circuits different from the neuron circuits illustrated in  FIG. 2 . 
     The ising device  2   b  includes registers  20   b   1  to  20   b N. Each of the registers  20   b   1  to  20   b N holds weight values. The weight values include at least one weight value that indicates connection strength between a corresponding neuron circuit and one of the other neuron circuits within the chip and includes at least one weight value that indicates connection strength between the corresponding neuron circuit and one of the neuron circuits outside the chip. 
     For example, when the number of neuron circuits in the chip is n, the register  20   b   1  holds weight values W 12  to W 1n  each of which indicates connection strength between the first neuron circuit in the chip and one of the other neuron circuits in the chip. 
     In addition, assuming that the neuron circuits in the chip are connected to N-n neuron circuits outside the chip, the register  20   b N holds weight values W N1  to W Nn  each of which indicates connection strength between one of the neuron circuits in the chip and one of the N-n neuron circuits outside the chip. 
     In addition, the ising device  2   b  includes a plurality of (n) neuron circuits. For example,  FIG. 26  illustrates the i-th, j-th, and k-th neuron circuits  10   bi ,  10   bj , and  10   bk , respectively, of all the n neuron circuits. 
     The neuron circuit  10   bi  includes a selection circuit  21   bi , multiplier circuits  23   bi   1  to  23   bi N, an adder unit  24   bi , a noise&amp;bias circuit  26   bi , and a comparator circuit  27   bi . The neuron circuit  10   bj  includes a selection circuit  21   bj , multiplier circuits  23   bj   1  to  23   bj N, an adder unit  24   bj , a noise&amp;bias circuit  26   bj , and a comparator circuit  27   bj . The neuron circuit  10   bk  includes a selection circuit  21   bk , multiplier circuits  23   bk   1  to  23   bk N, an adder unit  24   bk , a noise&amp;bias circuit  26   bk , and a comparator circuit  27   bk.    
     Each of the neuron circuits  10   bi ,  10   bj , and  10   bk  calculates a local field value as illustrated in expression (2), adds a noise value thereto, compares a sum with a threshold, and outputs a comparison result. 
     Hereinafter, the neuron circuit  10   bi  will be described as an example. 
     In accordance with any of the selection signals 1 to n outputted from a random signal generation circuit  15   a , the selection circuit  21   bi  selects and outputs a group of weight values stored in any one of the registers  20   b   1  to  20   b N. 
     Each of the multiplier circuits  23   bi   1  to  23   bi N multiplies the state of an individual one of the N neuron circuits outputted by a control circuit  100  by a corresponding one of the weight values. 
     The adder unit  24   bi  adds up the values outputted by the multiplier circuits  23   bi   1  to  23   bi N. 
     The comparator circuit  27   bi  compares a value, which is obtained by adding a noise value and a bias value outputted by the noise&amp;bias circuit  26   bi  to the value outputted by the adder unit  24   bi , with a threshold and outputs a comparison result. 
     The control circuit  100  receives an updated value of a neuron circuit of another chip, the chip address of the chip including the neuron circuit, and the internal address of the neuron circuit via a router  13 . Next, when the control circuit  100  determines that the neuron circuit outside the chip is specified as a connection destination of the neuron circuits within the ising device  2   b  in accordance with the above connection destination information  70 , the control circuit  100  reflects the updated value on the neuron circuits  10   bi ,  10   bj , and  10   bk.    
     The ising device  2   b  also provides the same advantageous effect. 
     While an aspect of the information processing apparatus, an aspect of an ising device, and an aspect of an information processing apparatus control method of the present technique have been described in accordance with the above embodiments, the above embodiments are only examples. The present technique is not limited to the above embodiments. 
     The information processing apparatus, the ising device, and the information processing apparatus control method discussed herein are capable of calculating a large-scale problem in which relatively many variables are used. 
     All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.