Patent Publication Number: US-8126993-B2

Title: System, method, and computer program product for communicating sub-device state information

Description:
FIELD OF THE INVENTION 
     The present invention relates to resource management, and more particularly to obtaining state information from various resources. 
     BACKGROUND 
     Prior art  FIG. 1  illustrates a system  100  for managing a plurality of graphics processors, in accordance with the prior art. As shown, a pair of applications  102 ,  104  are included which deliver requests for completion of various graphics processing tasks. Typically, such applications  102 ,  104  are only capable of issuing requests to a single graphics processor. In other words, such applications  102 ,  104  are configured such that they assume that only one graphics processor exists. 
     In more recent systems like the system  100  shown, however, at least a pair of graphic processors  108 ,  110  is provided for carrying out the various graphics processor tasks. In order to provide interoperability among the multiple graphic processors  108 ,  110  and the single processor-equipped applications  102 ,  104 , a driver  106  is typically utilized. Specifically, the driver  106  provides an interface among the components such that the task requests issued by the applications  102 ,  104  may be divided among the different graphic processors  108 ,  110 . To this end, the applications  102 ,  104  do not see the graphic processors  108 ,  110  discreetly, but rather see them as a single device  112 , thus complying with the protocol of their task requests, etc. 
     Unfortunately, operation of drivers of the type mentioned above precludes applications (particularly those that are equipped to work with multiple graphics processors) from querying such graphics processors individually. There is thus a need for overcoming these and/or other problems associated with the prior art. 
     SUMMARY 
     A system, method, and computer program product are provided for communicating sub-device state information, utilizing a driver. In use, a plurality of sub-devices of a device is exposed to an application. A request may then be received from the application for state information associated with at least one of the sub-devices. In response to the request, the state information is provided to the application. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Prior art  FIG. 1  illustrates a system for managing a plurality of graphics processors, in accordance with the prior art. 
         FIG. 2  shows a method for communicating sub-device state information, in accordance with one embodiment. 
         FIG. 3  illustrates a system for communicating sub-device state information, in accordance with one embodiment. 
         FIG. 4  shows a method for identifying a plurality of devices and sub-devices, in accordance with another embodiment. 
         FIG. 5  is a block diagram of an exemplary embodiment of a motherboard for a multi-processor graphics processing system. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 2  shows a method  200  for communicating sub-device state information, in accordance with one embodiment. As shown, a plurality of sub-devices of a device is exposed to an application, utilizing a driver. See operation  202 . 
     In the context of the present description, such sub-devices may each include any device implemented on at least one semiconductor platform in the form of a semiconductor-based integrated circuit or chip. Further, the aforementioned sub-devices are associated in the form of a device such that the application perceives such association while, at the same time, is exposed to the distinct nature thereof. 
     Of course, the aforementioned application may refer to any software and/or hardware that is capable of utilizing the sub-devices. Further, the driver refers to any software capable of providing an interface between the application, and the sub-device and sub-devices. Even still, the sub-devices may be exposed in any manner that supports the remaining operations to be discussed hereinafter. 
     In one optional embodiment, such sub-devices may include separate graphics processors. As a further option, such sub-devices may include distinct graphics processing units (GPUs). More information regarding such embodiment will be set forth in greater detail during reference to  FIG. 3  et al. Of course, the sub-devices may each refer to any device that meets the definition set forth hereinabove. 
     By virtue of the exposure of operation  202 , a request may then be received from the application for state information associated with at least one of the sub-devices. See operation  204 . In the context of the present description, the state information may refer to performance information, temperature information, power information, and/or any information relating to a state of the particular sub-device. 
     In response to the request of operation  204 , the state information is provided to the application. See operation  206 . As an option, such request may be received by the aforementioned driver which, in turn, provides the requested state information in accordance with operation  206 . 
     More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing framework may or may not be implemented, per the desires of the user. It should be strongly noted that the following information is set forth for illustrative purposes and should not be construed as limiting in any manner. Any of the following features may be optionally incorporated with or without the exclusion of other features described. 
       FIG. 3  illustrates a system  300  for communicating sub-device state information, in accordance with one embodiment. As an option, the present system  300  may be the subject of the method  200  of  FIG. 2 . Of course, however, the system  300  may be used in any desired environment. Still yet, the above definitions apply during the following description. 
     As shown, a pair of applications  302 ,  304  are included which issue requests for completion of various processing tasks. Unlike the prior art system  100  of  FIG. 1 , such applications  302 ,  304  are capable of issuing requests to a device including a plurality sub-devices, as well as the sub-devices individually. To this end, such applications  302 ,  304  are configured to recognize separate devices  312 ,  316  each including one or more sub-devices  308 ,  310 , and  314 , as well as the sub-devices  308 ,  310 , and  314  themselves. As shown in  FIG. 3 , such sub-devices  308 ,  310 , and  314  may each include a separate graphics processor. 
     To accommodate such capability of the applications  302 ,  304 , a driver  306  is included for exposing not only the devices  312 ,  316 , but also the sub-devices  308 ,  310 , and  314 . To this end, the applications  302 ,  304  may issue requests with respect to the graphic processors  308 ,  310  discreetly, as well as the associated single device  312 , depending on a mode of operation. 
     Specifically, the sub-devices  308 ,  310 , and  314  are capable of operating in a first mode where a first sub-device  308  serves as a slave to a second sub-device  310 . An example of such master-slave operation will be set forth in greater detail during reference to  FIG. 5 . In one embodiment, such first mode of operation may be carried out in accordance with NVIDIA® SLI™ technology. More information regarding such technology may be found by reference to an application filed Nov. 17, 2004 under application Ser. No. 10/990,712, which is incorporated herein by reference in its entirety. 
     Still yet, the sub-devices  308 ,  310 , and  314  are capable of operating in a second mode where the first sub-device  308  and the second sub-device  310  operate independently. For example, such independent operation may be carried out without the master-slave operation, etc. 
     Thus, in use, the state information for the sub-devices  308 ,  310 , and  314  may be provided to the applications  302 ,  304  independent of whether the sub-devices  308 ,  310 , and  314  are operating in the first mode and the second mode. In other words, such sub-device state information may be accessed whether or not the system  300  is operating in the first or second mode. In the context of an embodiment where the first mode includes the foregoing NVIDIA® SLI™ technology, such technology need not necessarily be disabled for accessing the sub-device state information. 
     It should also be noted that, in the case of the device  316  and sub-device  314 , the device  316  includes a single sub-device  314 . To this end, in some embodiments, any state information of the device  316  is the same as that of the sub-device  314 . Thus, in such embodiments, any request for state information in association with the device  316  would provide such information about the sub-device  314 , and visa-versa. 
     In other embodiments where the device  316  includes a single sub-device  314 , a query to the device  316  may possibly yield different results with respect to a query to the sub-device  314 . Also, in still other embodiments, a request to the device  316  may be valid, while that same request may be invalid for the sub-device  314 . Just by way of example, such may be the case in situations where the device  316  includes a fan and/or power device(s) that can be queried, while the sub-device  314  does not. 
       FIG. 4  shows a method  400  for identifying a plurality of devices and sub-devices, in accordance with another embodiment. As an option, the present method  400  may be implemented in the context of the system  300  of  FIG. 3 , and the method  200  of  FIG. 2 . Of course, however, the method  400  may be implemented in any desired environment. Again, the definitions introduced hereinabove apply during the following description. 
     As shown, a number of devices (e.g. see, for example, the devices  312 ,  316  of  FIG. 3 , etc.) is determined in operation  402 . Specifically, in response to a request by an application (e.g. see, for example, the applications  302 ,  304  of  FIG. 3 , etc.), a number of devices may be identified by a driver (e.g. see, for example, the driver  306  of  FIG. 3 , etc.) and further exposed (e.g. communicated, etc.) to the requesting application. 
     To this end, the requesting application may allocate such devices by determining any identifier associated therewith, etc. See operation  404 . Such identifiers may be used for the purpose of referencing the same when making requests (e.g. for state information, etc.) thereafter. 
     Similarly, a number of sub-devices (e.g. see, for example, the sub-devices  308 ,  310 , and  314  of  FIG. 3 , etc.) is determined in operation  406 . Again, in response to a request by an application, a number of sub-devices may be identified by the driver and further exposed to the requesting application. Thus, the requesting application may allocate such sub-devices by determining any identifier associated therewith, etc. See operation  408 . Again, such identifiers may be used for the purpose of referencing the same when making requests (e.g. for state information, etc.) thereafter. 
     Table 1 illustrates an exemplary result of the allocation of operations  404  and  408 . 
                             TABLE 1                          Device_1             Sub-Device_A             Sub-Device_B           Device_2             Sub-Device_C             Sub-Device_D             Sub-Device_E           Device_3             Sub-Device_F                        
Of course, such allocation is set forth for illustrative purposes only and should not be construed as limiting in any manner.
 
       FIG. 5  is a block diagram of an exemplary embodiment of a motherboard for a multi-processor graphics processing system  500 , in accordance with another embodiment. As an option, the present system  500  may be the subject of the methods/systems of  FIGS. 2-4 . Of course, however, the system  500  may be used in any desired environment. Still yet, the above definitions apply during the following description. 
     While not shown, a motherboard  500  may be included within a desktop computer, server, laptop computer, palm-sized computer, tablet computer, game console, cellular telephone, computer based simulator, or the like. The motherboard  500  includes a host processor  550 , a main memory  510 , and a chipset  530  that is directly coupled to a bridge  535 . 
     In some embodiments of the motherboard  500 , a chipset  530  may include a system memory bridge and an input/output (I/O) bridge that may include several interfaces such as, Advanced Technology Attachment (ATA) bus, Universal Serial Bus (USB), Peripheral component interface (PCI), or the like. The bridge  535  provides an interface between the chipset  530  and a master graphics adapter  540  and a slave graphics adapter  560 . 
     It should be noted that such master graphics adapter  540  and slave graphics adapter  560  (and possibly even the one or more graphics processors that make up the same) may each constitute an example of the aforementioned sub-device, in the context of the present embodiment. Again, such embodiment should not be construed as limiting in any manner, as any sub-device may be utilized that meets the definition set forth earlier. 
     In some embodiments, interfaces  541  and  545  conform to an industry standard interface specification, such as peripheral component interface express (PCI-Express™). Furthermore, in one embodiment, the functionality of the bridge  535  is included within the chipset  530 . In another embodiment, the bridge  535  is omitted and chipset  530  interfaces directly with the master graphics adapter  540  and slave graphics adapter  560 . 
     The master graphics adapter  540  may take the form of a printed circuit board (PCB) which is coupled to connection  545  when installed in a first slot. The slave graphics adapter  560  is coupled to the connection  541  when installed in a second slot. In some embodiments, additional graphics adapters may be installed in additional slots and the bridge  535  may provide an interface for each additional slot. The master graphics adapter  540  and secondary graphics adapter  560  may each include one or more graphics processors and dedicated memory which may be used to store graphics data, such as texture maps, image data, and program instructions. 
     A primary connection between the master graphics adapter  540  and one or more slave graphics adapters  560  may be provided by the interfaces via the bridge  535 . In some embodiments, the primary connection couples the master graphics adapter  540  and one or more slave graphics adapters  560  through the bridge  535 , chipset  530 , and main memory  510  and data transfers between the master graphics adapter  540  and the one or more slave graphics adapters  560  are controlled by the host processor  550 . 
     A dedicated interface  545  provides a secondary connection between the master graphics adapter  540  and one or more slave graphics adapters  560 . The secondary connection is used to transfer pixel data produced by the slave graphics adapter  560  from the slave graphics adapter  560  to the master graphics adapter  540 , thereby offloading pixel data transfers from the primary connection. 
     Using the dedicated interface  545  between two or more graphics adapters facilitates efficient transfer of graphics data and synchronization signals between the two or more graphics adapters while reducing system bandwidth. Furthermore, users can easily install each graphics adapter as desired to improve rendering performance in terms of image quality or rendering speed. For example, two or more graphics adapters may be used to render images with improved image quality or two or more graphics adapters may be used to render images at a higher frame rate. 
     The dedicated interface  545  between the master graphics adapter  540  and slave graphics adapter  560  is provided by a connection device. The connection device may be a connector PCB with a socket affixed to opposing ends of the connector PCB. Conductive traces fabricated as part of the connector PCB directly connect pins of the socket on one end of the connector PCB to pins of the other socket on the opposing end of the connector PCB. 
     Another embodiment of a connection device includes a connector flexible cable with a socket affixed to each end of the connector flexible cable. The connector flexible cable includes wires within a flexible insulating wrapping that directly connect pins of one socket on one end of the connector flexible cable to pins of the other socket on the opposing end of the connector flexible cable. Those skilled in the art will recognize that other components and mechanisms may be employed to produce a connection device. 
     The dedicated interface  545  provides a multi-bit connection for several signals. For example, pixel data may be transferred from a slave graphics device to a master graphics device or to another slave graphics device using a number of single bit connections for data, a data valid signal, and a clock. The master graphics device outputs image data directly to a display device. In contrast, a slave graphics device outputs pixel data to a master graphics device, sometimes through another slave graphics device. The pixel data and data valid may be transferred on one or both edges of the clock. 
     One or more buffer management signals may also be connected between graphics adapters using the connection device. In some embodiments of the present invention, a buffer management signal indicates when all of the graphics processors producing pixel data for a display should swap buffers, i.e., swap the back buffer with the front buffer. Synchronization signals may also be transferred from a master graphics device to a slave graphics device to communicate the display raster position. 
     The master graphics adapter  540  outputs image data to a display device (e.g. the display  570 ). Examples of display devices known in the art include a cathode ray tube (CRT), flat panel display, or the like. The slave graphics adapter  560  may process a larger portion of an image than the master graphics adapter  540  and transfer pixel data for the larger portion of the image to the master graphics adapter  540  via the dedicated interface  545 . 
     In some embodiments, processing of the image may be distributed between the master graphics adapter  540  and one or more slave graphics adapters  560  based on the processing capability of each graphics adapter. Furthermore, a buffer swap and synchronization signals, e.g., horizontal sync, and vertical sync, may be transferred between the slave graphics adapter  560  and the primary graphics adapter  540  using the dedicated interface  545 . 
     While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.