Patent Publication Number: US-9841620-B2

Title: GOA circuit based on LTPS semiconductor thin film transistor

Description:
FIELD OF THE INVENTION 
     The present invention relates to a display technology field, and more particularly to a GOA circuit based on LTPS semiconductor thin film transistor. 
     BACKGROUND OF THE INVENTION 
     The Liquid Crystal Display (LCD) possesses advantages of thin body, power saving and no radiation to be widely used in many application scope, such as LCD TV, mobile phone, personal digital assistant (PDA), digital camera, notebook, laptop, and dominates the flat panel display field. 
     The GOA technology, i.e. the Gate Driver on Array technology utilizes the original array manufacture processes of the liquid crystal display panel to manufacture the driving circuit of the level scan lines on the substrate around the active area, to replace the external Integrated Circuit (IC) for accomplishing the driving of the level scan lines. The GOA technology can reduce the bonding procedure of the external IC and has potential to raise the productivity and lower the production cost. Meanwhile, it can make the liquid crystal display panel more suitable to the narrow frame or non frame design of display products. 
     With the development of the LTPS semiconductor TFT, the LTPS-TFT LCD also becomes the focus that people pay lots of attentions. Because the LTPS semiconductor has better order than amorphous silicon (a-Si) and the LTPS itself has extremely high carrier mobility which can be more than  100  times of the amorphous silicon semiconductor, which the GOA skill can be utilized to manufacture the gate driver on the TFT array substrate to achieve the objective of system integration and saving the space and the cost of the driving IC. 
     Please refer to  FIG. 1 . A GOA circuit based on LTPS semiconductor thin film transistor according to prior art comprises GOA units of a plurality of stages, and n is set to be a positive integer, and the nth stage GOA unit comprises: a first thin film transistor T 1 , and a gate of the first thin film transistor T 1  is electrically coupled to a Mth clock signal CK(M), and a source is electrically coupled to an output end G(n−1) of a former stage n−1th GOA unit, and a drain is electrically coupled to a third node K(n); a second thin film transistor T 2 , and a gate of the second thin film transistor T 2  is electrically coupled to the first node Q(n), and a source is electrically coupled to a M+1th clock signal CK(M+1), and a drain is electrically coupled to an output end G(n); a third thin film transistor T 3 , and a gate of the third thin film transistor T 3  is electrically coupled to a M+2th clock signal CK(M+2), and a drain is electrically coupled to the third node K(n), and a source is electrically coupled to an output end G(n+1) of a latter stage n+1th GOA unit; a fourth thin film transistor T 4 , and a gate of the fourth thin film transistor T 4  is electrically coupled to a M+3th clock signal CK(M+3), and a drain is electrically coupled to the output end G(n), and a source is electrically coupled to a constant low voltage level VGL; a fifth thin film transistor T 5 , and a gate of the fifth thin film transistor T 5  is electrically coupled to a constant high voltage level VGH, and a source is electrically coupled to the third node K(n), and a drain is electrically coupled to the first node Q(n); a sixth thin film transistor T 6 , a gate of the sixth thin film transistor T 6  is electrically coupled to the second node P(n), and a drain is electrically coupled to the third node K(n), and a source is electrically coupled to the constant low voltage level VGL; a seventh thin film transistor T 7 , and a gate of the seventh thin film transistor T 7  is electrically coupled to the second node P(n), and a drain is electrically coupled to the output end G(n), and a source is electrically coupled to the constant low voltage level VGL; an eighth thin film transistor T 8 , and a gate of the eighth thin film transistor T 8  is electrically coupled to the third node K(n), and a drain is electrically coupled to the second node P(n), and a source is electrically coupled to the constant low voltage level VGL; a ninth thin film transistor T 9 , and both a gate and a source of the ninth thin film transistor T 9  are electrically coupled to the M+1th clock signal CK(M+1), and a drain is electrically coupled to the second node P(n); a boost capacitor C 1 , and one end of the boost capacitor C 1  is electrically coupled to the first node Q(n), and the other end is electrically coupled to the output end G(n); a second capacitor C 2 , and one end of the second capacitor C 2  is electrically coupled to second node P(n), and the other end is electrically coupled to the constant low voltage level VGL. 
     The output unit comprises: a second thin film transistor, and a gate of the second thin film transistor is electrically coupled to the first node, and a source is electrically coupled to a Mth clock signal, and a drain is electrically coupled to an output end; and a bootstrap capacitor, and one end of the bootstrap capacitor is electrically coupled to a first node, and the other end is electrically coupled to the output end; with combination of  FIG. 1  and  FIG. 2 , the forward scan is illustrated, as forward scanning, the working process is: first, Both the Mth clock signal CK(M) and the output end G(n−1) of the former stage n−1th GOA unit provides high voltage level, and the first and the fifth thin film transistors T 1 , T 5  are on, and the firs node Q(n) is pre-charged to high voltage level; then, the Mth clock signal CK(M) and the output end G(n−1) of the former stage n−1th GOA unit drop to be low voltage level, and the M+1th clock signal CK(M+1) provides high voltage level, and the first node Q(n) is held to be high voltage level due to the storage function of the boost capacitor C 1 , and the second thin film transistor T 2  is on, and the output end G(n) outputs the high voltage level of the M+1th clock signal CK(M+1) to raise the first node Q(n) to be higher voltage level, and meanwhile, the eighth thin film transistor T 8  is on, and the second node P(n) is pulled down to be the constant low voltage level, and the sixth, seventh thin film transistors T 6 , T 7  are off; then, both the M+2clock signal CK(M+2) and the output end G(n+1) of the latter stage n+1th GOA unit provide high voltage level, and the first node Q(n) is still high voltage level, and the M+1th clock signal CK(M+1) drops to be low voltage level, and the output end G(n) outputs the low voltage of the M+1th clock signal CK(M+1); and then, the Mth clock signal provides high voltage level, again, and the output end G(n−1) of the former stage n−1th GOA unit is held to be low voltage level, and the first thin film transistor T 1  is on to pull down the first node Q(n) to be low voltage level, and the eighth thin film transistor T 8  is off; thereafter, the M+1th clock signal CK(M+1) provides high voltage level, and the ninth thin film transistor T 9  is on, and the second node P(n) is charged to be the high voltage level of the M+1th clock signal CK(M+1), and the sixth, seventh thin film transistors T 6 , T 7  are on to respectively keep pulling down the first node Q(n) and the output end G(n) to the constant low voltage level VGL, and under the function of the second capacitor C 2 , the second node P(n) is held to be high voltage level, and the sixth, seventh thin film transistors T 6 , T 7  are on to hold the low voltage levels of the first node Q(n) and the output end G(n). 
     In the aforesaid GOA circuit based on LTPS semiconductor thin film transistor according to prior art, for the GOA unit of any stage, the voltage level of the second node P(n) and the output signal of the output end G(n) are both controlled with the M+1th clock signal CK(M+1), and the first node Q(n) is charged and discharged through the Mth clock signal CK(M) and the M+2th clock signal CK(M+2). Such arrangement will increase the serious delay of the output, and result in the function failure of the GOA circuit. 
     SUMMARY OF THE INVENTION 
     An objective of the present invention is to provide a GOA circuit based on LTPS semiconductor thin film transistor, of which the clock signal is merely in charge of the output of the GOA unit of corresponding stage, which can effectively reduce the loading of the clock signal and it ensures that the entire loading of the clock signal after the GOA units of multiple stages are coupled. The present invention can promote the output stability of the GOA circuit. 
     For realizing the aforesaid objective, the present invention provides a GOA circuit based on LTPS semiconductor thin film transistor, comprising GOA units of a plurality of stages which are cascade coupled, and the GOA unit of each stage comprises: a scan control unit, a forward scan pull-down unit, a backward scan pull-down unit and an output unit; 
     n is set to be a positive integer and except the GOA units of the first, the second, the next to last and the last stages, in the nth stage GOA unit: 
     the scan control unit comprises: a first thin film transistor, and a gate of the first thin film transistor is electrically coupled to an output end of a two former stage n−2th GOA unit, and a source is electrically coupled to a forward scan direct current control signal, and a drain is electrically coupled to a source of a fourth thin film transistor; and a third thin film transistor, and a gate of the third thin film transistor is electrically coupled to an output end of a two latter stage n+2th GOA unit, and a drain is electrically coupled to the source of the fourth thin film transistor, and a source is electrically coupled to a backward scan direct current control signal; and the fourth thin film transistor, a gate of the fourth thin film transistor is electrically coupled to a constant high voltage level, and a drain is electrically coupled to a first node; 
     the forward scan pull-down unit comprises: a fifth thin film transistor, and a gate of the fifth thin film transistor is electrically coupled to the forward scan direct current control signal, and a source is electrically coupled to the constant high voltage level, and a drain is electrically coupled to a second node; a sixth thin film transistor, and a gate of the sixth thin film transistor is electrically coupled to the backward scan direct current control signal, and a drain is electrically coupled to the second node, and a source is electrically coupled to the constant low voltage level; a thirteenth thin film transistor, and a gate of the thirteenth thin film transistor is electrically coupled to the first node, and a drain is electrically coupled to the second node, and a source is electrically coupled to the constant low voltage level; a ninth thin film transistor, and a gate of the ninth thin film transistor is electrically coupled to the second node, and a source is electrically coupled to the constant low voltage level, and a drain is electrically coupled to the first node; and a tenth thin film transistor, a gate of the tenth thin film transistor is electrically coupled to the second node, and a source is electrically coupled to the constant low voltage level, and a drain is electrically coupled to and output end; 
     the backward scan pull-down unit comprises: an eighth thin film transistor, and a gate of the eighth thin film transistor is electrically coupled to the forward scan direct current control signal, and a source is electrically coupled to the constant low voltage level, and a drain is electrically coupled to a third node; a seventh thin film transistor, and a gate of the seventh thin film transistor is electrically coupled to the backward scan direct current control signal, and a source is electrically coupled to the constant high voltage level, and a drain is electrically coupled to the third node; a fourteenth thin film transistor, and a gate of the fourteenth thin film transistor is electrically coupled to the first node, and a drain is electrically coupled to the third node, and a source is electrically coupled to the constant low voltage level; an eleventh thin film transistor, a gate of the eleventh thin film transistor is electrically coupled to the third node, and a source is electrically coupled to the constant low voltage level, and a drain is electrically coupled to the first node; and a twelfth thin film transistor, and a gate of the twelfth thin film transistor is electrically coupled to the third node, and a source is electrically coupled to the constant low voltage level, and a drain is electrically coupled to the output end; 
     the output unit comprises: a second thin film transistor, and a gate of the second thin film transistor is electrically coupled to the first node, and a source is electrically coupled to a Mth clock signal, and a drain is electrically coupled to an output end; and a bootstrap capacitor, and one end of the bootstrap capacitor is electrically coupled to a first node, and the other end is electrically coupled to the output end; 
     voltage levels of the forward scan direct current control signal and the backward scan direct current control signal are opposite. 
     The voltage level of the first node, the voltage level of the second node and the voltage level of the third node are all controlled by the forward scan direct current control signal and the backward scan direct current control signal. 
     In the first stage GOA unit and the second stage GOA unit, the gate of the first thin film transistor is electrically coupled to a start signal. 
     In the next to last stage GOA unit and the last stage GOA unit, the gate of the third thin film transistor is electrically coupled to a start signal. 
     As the forward scan direct current control signal is high voltage level and the backward scan direct current control signal is low voltage level, the GOA circuit based on LTPS semiconductor thin film transistor performs a forward scan. 
     As the forward scan direct current control signal is low voltage level and the backward scan direct current control signal is high voltage level, the GOA circuit based on LTPS semiconductor thin film transistor performs a backward scan. 
     The clock signal comprises four clock signals: a first clock signal, a second clock signal, a third clock signal and a fourth clock signal. 
     The thin film transistors are all N type LTPS thin film transistors. 
     The present invention further provides a GOA circuit based on LTPS semiconductor thin film transistor, comprising GOA units of a plurality of stages which are cascade coupled, and the GOA unit of each stage comprises: a scan control unit, a forward scan pull-down unit, a backward scan pull-down unit and an output unit; 
     n is set to be a positive integer and except the GOA units of the first, the second, the next to last and the last stages, in the nth stage GOA unit: 
     the scan control unit comprises: a first thin film transistor, and a gate of the first thin film transistor is electrically coupled to an output end of a two former stage n−2th GOA unit, and a source is electrically coupled to a forward scan direct current control signal, and a drain is electrically coupled to a source of a fourth thin film transistor; and a third thin film transistor, and a gate of the third thin film transistor is electrically coupled to an output end of a two latter stage n+2th GOA unit, and a drain is electrically coupled to the source of the fourth thin film transistor, and a source is electrically coupled to a backward scan direct current control signal; and the fourth thin film transistor, a gate of the fourth thin film transistor is electrically coupled to a constant high voltage level, and a drain is electrically coupled to a first node; 
     the forward scan pull-down unit comprises: a fifth thin film transistor, and a gate of the fifth thin film transistor is electrically coupled to the forward scan direct current control signal, and a source is electrically coupled to the constant high voltage level, and a drain is electrically coupled to a second node; a sixth thin film transistor, and a gate of the sixth thin film transistor is electrically coupled to the backward scan direct current control signal, and a drain is electrically coupled to the second node, and a source is electrically coupled to the constant low voltage level; a thirteenth thin film transistor, and a gate of the thirteenth thin film transistor is electrically coupled to the first node, and a drain is electrically coupled to the second node, and a source is electrically coupled to the constant low voltage level; a ninth thin film transistor, and a gate of the ninth thin film transistor is electrically coupled to the second node, and a source is electrically coupled to the constant low voltage level, and a drain is electrically coupled to the first node; and a tenth thin film transistor, a gate of the tenth thin film transistor is electrically coupled to the second node, and a source is electrically coupled to the constant low voltage level, and a drain is electrically coupled to and output end; 
     the backward scan pull-down unit comprises: an eighth thin film transistor, and a gate of the eighth thin film transistor is electrically coupled to the forward scan direct current control signal, and a source is electrically coupled to the constant low voltage level, and a drain is electrically coupled to a third node; a seventh thin film transistor, and a gate of the seventh thin film transistor is electrically coupled to the backward scan direct current control signal, and a source is electrically coupled to the constant high voltage level, and a drain is electrically coupled to the third node; a fourteenth thin film transistor, and a gate of the fourteenth thin film transistor is electrically coupled to the first node, and a drain is electrically coupled to the third node, and a source is electrically coupled to the constant low voltage level; an eleventh thin film transistor, a gate of the eleventh thin film transistor is electrically coupled to the third node, and a source is electrically coupled to the constant low voltage level, and a drain is electrically coupled to the first node; and a twelfth thin film transistor, and a gate of the twelfth thin film transistor is electrically coupled to the third node, and a source is electrically coupled to the constant low voltage level, and a drain is electrically coupled to the output end; 
     the output unit comprises: a second thin film transistor, and a gate of the second thin film transistor is electrically coupled to the first node, and a source is electrically coupled to a Mth clock signal, and a drain is electrically coupled to an output end; and a bootstrap capacitor, and one end of the bootstrap capacitor is electrically coupled to a first node, and the other end is electrically coupled to the output end; 
     voltage levels of the forward scan direct current control signal and the backward scan direct current control signal are opposite; 
     wherein the voltage level of the first node, the voltage level of the second node and the voltage level of the third node are all controlled by the forward scan direct current control signal and the backward scan direct current control signal. 
     In the first stage GOA unit and the second stage GOA unit, the gate of the first thin film transistor is electrically coupled to a start signal. 
     In the next to last stage GOA unit and the last stage GOA unit, the gate of the third thin film transistor is electrically coupled to a start signal. 
     The benefits of the present invention are: the present invention provides a GOA circuit based on LTPS semiconductor thin film transistor to control the voltage levels of the first node, the second node and the third node with the forward scan direct current control signal and the backward scan direct current control signal. The clock signal is merely in charge of the output of the GOA unit of corresponding stage, which can effectively reduce the loading of the clock signal. It ensures that the entire loading of the clock signal after the GOA units of multiple stages are coupled to promote the output stability of the GOA circuit, and to realize the forward-backward scan of the GOA circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In order to better understand the characteristics and technical aspect of the invention, please refer to the following detailed description of the present invention is concerned with the diagrams, however, provide reference to the accompanying drawings and description only and is not intended to be limiting of the invention. 
       In drawings, 
         FIG. 1  is a circuit diagram of a GOA circuit based on LTPS semiconductor thin film transistor according to prior art; 
         FIG. 2  is a sequence diagram of forward scan corresponding to the GOA circuit based on LTPS semiconductor thin film transistor shown in  FIG. 1 ; 
         FIG. 3  is a circuit diagram of a GOA circuit based on LTPS semiconductor thin film transistor according to the present invention; 
         FIG. 4  is a sequence diagram of a GOA circuit based on LTPS semiconductor thin film transistor as performing a forward scan; 
         FIG. 5  is a sequence diagram of a GOA circuit based on LTPS semiconductor thin film transistor as performing a backward scan; 
         FIG. 6  is a circuit diagram of a first stage GOA unit of a GOA circuit based on LTPS semiconductor thin film transistor according to the present invention; 
         FIG. 7  is a circuit diagram of a second stage GOA unit of a GOA circuit based on LTPS semiconductor thin film transistor according to the present invention; 
         FIG. 8  is a circuit diagram of a next to last stage GOA unit of a GOA circuit based on LTPS semiconductor thin film transistor according to the present invention; 
         FIG. 9  is a circuit diagram of a last stage GOA unit of a GOA circuit based on LTPS semiconductor thin film transistor according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     For better explaining the technical solution and the effect of the present invention, the present invention will be further described in detail with the accompanying drawings and the specific embodiments. 
     Please refer to  FIG. 3 . The present invention provides a GOA circuit based on LTPS semiconductor thin film transistor, comprising GOA units of a plurality of stages which are cascade coupled, and the GOA unit of each stage comprises: a scan control unit  100 , a forward scan pull-down unit  200 , a backward scan pull-down unit  300  and an output unit  400 . 
     n is set to be a positive integer and except the GOA units of the first, the second, the next to last and the last stages, in the nth stage GOA unit: 
     the scan control unit  100  comprises: a first thin film transistor T 1 , and a gate of the first thin film transistor T 1  is electrically coupled to an output end G(n−2) of a two former stage n−2th GOA unit, and a source is electrically coupled to a forward scan direct current control signal U 2 D, and a drain is electrically coupled to a source of a fourth thin film transistor T 4 ; and a third thin film transistor T 3 , and a gate of the third thin film transistor T 3  is electrically coupled to an output G(n+2) end of a two latter stage n+2th GOA unit, and a drain is electrically coupled to the source of the fourth thin film transistor T 4 , and a source is electrically coupled to a backward scan direct current control signal D 2 U; and the fourth thin film transistor T 4 , a gate of the fourth thin film transistor T 4  is electrically coupled to a constant high voltage level control signal VGH, and a drain is electrically coupled to a first node Q(n); 
     the forward scan pull-down unit  200  comprises: a fifth thin film transistor T 5 , and a gate of the fifth thin film transistor T 5  is electrically coupled to the forward scan direct current control signal U 2 D, and a source is electrically coupled to the constant high voltage level VGH, and a drain is electrically coupled to a second node P 1 (n); a sixth thin film transistor T 6 , and a gate of the sixth thin film transistor T 6  is electrically coupled to the backward scan direct current control signal D 2 U, and a drain is electrically coupled to the second node P 1 (n), and a source is electrically coupled to the constant low voltage level VGL; a thirteenth thin film transistor T 13 , and a gate of the thirteenth thin film transistor T 13  is electrically coupled to the first node Q(n), and a drain is electrically coupled to the second node P 1 (n), and a source is electrically coupled to the constant low voltage level VGL; a ninth thin film transistor T 9 , and a gate of the ninth thin film transistor T 9  is electrically coupled to the second node P 1 (n), and a source is electrically coupled to the constant low voltage level VGL, and a drain is electrically coupled to the first node Q(n); and a tenth thin film transistor T 10 , a gate of the tenth thin film transistor T 10  is electrically coupled to the second node P 1 (n), and a source is electrically coupled to the constant low voltage level VGL, and a drain is electrically coupled to and output end G(n); 
     the backward scan pull-down unit  300  comprises: an eighth thin film transistor T 8 , and a gate of the eighth thin film transistor T 8  is electrically coupled to the forward scan direct current control signal U 2 D, and a source is electrically coupled to the constant low voltage level VGL, and a drain is electrically coupled to a third node P 2 (n); a seventh thin film transistor T 7 , and a gate of the seventh thin film transistor T 7  is electrically coupled to the backward scan direct current control signal D 2 U, and a source is electrically coupled to the constant high voltage level VGH, and a drain is electrically coupled to the third node P 2 (n); a fourteenth thin film transistor T 14 , and a gate of the fourteenth thin film transistor T 14  is electrically coupled to the first node Q(n), and a drain is electrically coupled to the third node P 2 (n), and a source is electrically coupled to the constant low voltage level VGL; an eleventh thin film transistor T 11 , a gate of the eleventh thin film transistor T 11  is electrically coupled to the third node P 2 (n), and a source is electrically coupled to the constant low voltage level VGL, and a drain is electrically coupled to the first node Q(n); and a twelfth thin film transistor T 12 , and a gate of the twelfth thin film transistor T 12  is electrically coupled to the third node P 2 (n), and a source is electrically coupled to the constant low voltage level VGL, and a drain is electrically coupled to the output end G(n); 
     the output unit  400  comprises: a second thin film transistor T 2 , and a gate of the second thin film transistor T 2  is electrically coupled to the first node Q(n), and a source is electrically coupled to a Mth clock signal CK(M), and a drain is electrically coupled to an output end G(n); and a bootstrap capacitor C 1 , and one end of the bootstrap capacitor C 1  is electrically coupled to a first node Q(n), and the other end is electrically coupled to the output end G(n). 
     Specifically, the thin film transistors are all N type LTPS thin film transistors. 
     Particularly, please refer to  FIG. 6 - FIG. 9 . In the first stage GOA unit and the second stage GOA unit, the gate of the first thin film transistor T 1  is electrically coupled to a start signal; in the next to last stage GOA unit and the last stage GOA unit, the gate of the third thin film transistor T 3  is electrically coupled to a start signal. 
     The GOA circuit based on LTPS semiconductor thin film transistor according to the present invention possesses the forward-backward scan function. The voltage levels of the forward scan direct current control signal U 2 D and the backward scan direct current control signal D 2 U are opposite. As the forward scan direct current control signal U 2 D is high voltage level and the backward scan direct current control signal D 2 U is low voltage level, the GOA circuit performs a forward scan. As the forward scan direct current control signal U 2 D is low voltage level and the backward scan direct current control signal D 2 U is high voltage level, the GOA circuit performs a backward scan. 
     With combination of  FIG. 4  and  FIG. 5 , the GOA circuit based on LTPS semiconductor thin film transistor comprises four clock signals: a first clock signal CK( 1 ), a second clock signal CK( 2 ), a third clock signal CK( 3 ) and a fourth clock signal CK( 4 ). Each clock signal corresponds to the GOA unit of one stage. For example: the first clock signal CK( 1 ) is inputted to the first stage GOA unit, and the second clock signal CK( 2 ) is inputted to the second stage GOA unit, and the third clock signal CK( 3 ) is inputted to the third stage GOA unit, and the fourth clock signal CK( 4 ) is inputted to the fourth stage GOA unit. The clock signal is merely employed to be outputted for the output end of the corresponding GOA unit. 
     Significantly, Either the GOA circuit based on LTPS semiconductor thin film transistor performs the forward scan or the backward scan, the clock signal CK(M) is merely in charge of the outputting of the output end G(n) of the corresponding GOA unit, and the voltage levels of the first node Q(n), the second node P 1 (n) and the third node P 2 (n) are all controlled by the forward scan direct current control signal U 2 D and the backward scan direct current control signal D 2 U, which can effectively reduce the loading of the clock signal. It ensures that the entire loading of the clock signal after the GOA units of multiple stages are coupled to promote the output stability of the GOA circuit. 
     With combination of  FIG. 3  and  FIG. 4 , the forward scan direct current control signal U 2 D is high voltage level and the backward scan direct current control signal D 2 U is low voltage level, and the GOA unit performs the forward scan, and the specific working process is: 
     stage 1, pre-charge stage: the output end G(n−2) of the two latter stage n−2th GOA unit and the forward scan direct current control signal U 2 D are both high voltage levels, and the first thin film transistor T 1  is on, and the fourth thin film transistor T 4  is controlled by the constant high voltage level VGH to be in on state all the time, and the first node Q(n) is pre-charged to the high voltage level by the forward scan direct current control signal U 2 D of high voltage level, and the thirteenth and fourteenth thin film transistors T 13 , T 14  controlled by the first node Q(n) are in on state, and the voltage levels of the second node P 1 (n) and the third node P 2 (n) are pulled down to the constant low voltage level VGL; 
     stage 2, high voltage level output stage: the output end G(n−2) of the n−2th GOA unit drops to be low voltage level, and the Mth clock signal CK(M) provides the high voltage level, and the first thin film transistor T 1  is off, and the first node Q(n) is held to be high voltage level under the storage function of the boost capacitor C 1 , and the second thin film transistor T 2  is on, and the high voltage level of the Mth clock signal CK(M) is outputted through the output end G(n), and raises the first node Q(n) to be the higher voltage level; 
     stage 3, low voltage level output stage: the Mth clock signal CK(M) provides low voltage level, and the first node Q(n) is kept to be high voltage level, and the second thin film transistor T 2  is on, and the low voltage level of the Mth clock signal CK(M) is outputted through the output end G(n); 
     stage 4, first node pull down stage: the output end G(n+2) of the n+2th GOA unit and the backward scan direct current control signal D 2 U are both low voltage levels, and the third thin film transistor T 3  is on, and the voltage level of the first node Q(n) is pulled down to the low voltage level by the backward scan direct current control signal D 2 U of the low voltage level; 
     stage 5, first node and output end pull down holding stage: after the first node Q(n) become low voltage levels, because the forward scan direct current control signal U 2 D is high voltage level and the backward scan direct current control signal D 2 U is low voltage level, the fifth thin film transistor T 5  is on and the sixth thin film transistor T 6  is off, the third node P 2 (n) is charged to be high voltage level by the constant high voltage level VGH, and the ninth and the tenth thin film transistors T 9 , T 10  controlled by the second node P 1 (n) are on, and the first node Q(n) and the output end G(n) are held to be low voltage level VGL. Meanwhile, the eighth thin film transistor T 8  is on, and the seventh thin film transistor T 7  is off, and the third node P 2 (n) is charged to be low voltage level by the constant low voltage level VGL, and the eleventh and the twelfth thin film transistors T 11 , T 12  controlled by the third node P 2 (n) are both off. 
     With combination of  FIG. 3  and  FIG. 5 , the forward scan direct current control signal U 2 D is low voltage level and the backward scan direct current control signal D 2 U is high voltage level, and the GOA unit performs the backward scan, and the specific working process is: 
     stage 1, pre-charge stage: the output end G(n+2) of the n+2th GOA unit and the backward scan direct current control signal D 2 U are both high voltage levels, and the third thin film transistor T 3  is on, and the fourth thin film transistor T 4  is controlled by the constant high voltage level VGH to be in on state all the time, and the first node Q(n) is pre-charged to the high voltage level by the backward scan direct current control signal D 2 U of high voltage level, and the thirteenth and fourteenth thin film transistors T 13 , T 14  controlled by the first node are in on state, and the voltage levels of the second node P 1 (n) and the third node P 2 (n) are pulled down to the constant low voltage level VGL; 
     stage 2, high voltage level output stage: the output end G(n+2) of the two latter stage n+2th GOA unit drops to be low voltage level, and the Mth clock signal CK(M) provides the high voltage level, and the third thin film transistor T 3  is off, and the first node Q(n) is held to be high voltage level under the storage function of the boost capacitor C 1 , and the second thin film transistor T 2  is on, and the high voltage level of the Mth clock signal CK(M) is outputted through the output end G(n), and raises the first node Q(n) to be the higher voltage level; 
     stage 3, low voltage level output stage: the Mth clock signal CK(M) provides low voltage level, and the first node Q(n) is kept to be high voltage level, and the second thin film transistor T 2  is on, and the low voltage level of the Mth clock signal CK(M) is outputted through the output end G(n); 
     stage 4, first node pull down stage: the output end G(n−2) of the two former stage n−2th GOA unit, and the forward scan direct current control signal U 2 D is the low voltage level, and the first thin film transistor T 1  is on, and the voltage levels of the first node Q(n) is pulled down to the low voltage level by the forward scan direct current control signal U 2 D of the low voltage level; 
     stage 5, first node and output end pull down holding stage: after the first node Q(n) become low voltage levels, because the backward scan direct current control signal D 2 U is high voltage level and the forward scan direct current control signal U 2 D is low voltage level, the eighth thin film transistor T 8  is off and the seventh thin film transistor T 7  is on, the third node P 2 (n) is charged to be high voltage level by the constant high voltage level VGH, and the eleventh and the twelfth thin film transistors T 11 , T 12  controlled by the third node P 2 (n) are on, and the first node Q(n) and the output end G(n) are held to be low voltage level VGL. Meanwhile, the fifth thin film transistor T 5  is off, and the sixth thin film transistor T 6  is on, and the second node P 1 (n) is charged to low voltage level by the constant low voltage level VGL, and the ninth and tenth thin film transistors T 9 , T 10  controlled by the second node P 1 (n) is off. 
     In conclusion, the GOA circuit based on LTPS semiconductor thin film transistor of the present invention controls the voltage levels of the first node, the second node and the third node with the forward scan direct current control signal and the backward scan direct current control signal. The clock signal is merely in charge of the output of the GOA unit of corresponding stage, which can effectively reduce the loading of the clock signal. It ensures that the entire loading of the clock signal after the GOA units of multiple stages are coupled to promote the output stability of the GOA circuit, and to realize the forward-backward scan of the GOA circuit. 
     Above are only specific embodiments of the present invention, the scope of the present invention is not limited to this, and to any persons who are skilled in the art, change or replacement which is easily derived should be covered by the protected scope of the invention. Thus, the protected scope of the invention should go by the subject claims.