Patent Publication Number: US-2023157009-A1

Title: Anti-fuse device and method

Description:
PRIORITY CLAIM 
     The present application is a continuation of U.S. application Ser. No. 17/317,162, filed May 11, 2021, which is a continuation of U.S. application No. 16/460,266, filed Jul. 2, 2019, now U.S. Pat. No. 11,031,407, issued Jun. 8, 2021, which claims the priority of U.S. Provisional Application No. 62/725,192, filed Aug. 30, 2018, each of which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     Integrated circuits (ICs) sometimes include one-time-programmable (“OTP”) memory elements to provide non-volatile memory (“NVM”) in which data are not lost when the IC is powered off. One type of NVM includes an anti-fuse bit integrated into an IC by using a layer of dielectric material (oxide, etc.) connected to other circuit elements. To program an anti-fuse bit, a programming electric field is applied across the dielectric material layer to sustainably alter (e.g., break down) the dielectric material, thus decreasing the resistance of the dielectric material layer. Typically, to determine the status of an anti-fuse bit, a read voltage is applied across the dielectric material layer and a resultant current is read. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS.  1 A- 1 F  are diagrams of an anti-fuse device, in accordance with some embodiments. 
         FIGS.  2 A- 2 D  are diagrams of an anti-fuse device, in accordance with some embodiments. 
         FIG.  3    is a flowchart of a method of operating a circuit, in accordance with some embodiments. 
         FIG.  4    is a flowchart of a method of manufacturing an anti-fuse device, in accordance with some embodiments. 
         FIG.  5    is a flowchart of a method of generating an IC layout diagram, in accordance with some embodiments. 
         FIGS.  6 A and  6 B  depict anti-fuse cell layout diagrams, in accordance with some embodiments. 
         FIG.  7    is a block diagram of an electronic design automation (EDA) system, in accordance with some embodiments. 
         FIG.  8    is a block diagram of an IC manufacturing system, and an IC manufacturing flow associated therewith, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     In various embodiments, an anti-fuse cell includes an anti-fuse device and two selection transistors configured to collectively couple the anti-fuse device to a bit line. In programming operations, the combination of the two transistors enables a more uniform electric field application than in approaches in which a single transistor couples an anti-fuse device to a bit line. In read operations, the resultant parallel current paths enable lower path resistance, reduced effects of device resistance variations, and increased current compared to approaches in which a single transistor couples an anti-fuse device to a bit line, thereby improving accuracy when detecting programmed status. 
       FIGS.  1 A- 1 F  are diagrams of an IC device  100 , in accordance with some embodiments. In some embodiments, IC device  100  is formed by executing some or all of the operations of method  400  and/or method  500  and/or is configured based on an IC layout diagram  600 A or  600 B, discussed below with respect to  FIGS.  4 - 6 B . In some embodiments, IC device  100  is included in an IC device  860  manufactured by an IC manufacturer/fabricator (“fab”)  850 , discussed below with respect to  FIG.  8   . 
       FIGS.  1 A,  1 D, and  1 E  depict cross-sectional views of IC device  100  along a plane A-A′ including X and Z directions, and  FIG.  1 B  depicts a plan view of IC device  100 , the X direction and a Y direction, and an intersection with plane A-A′ along the X direction.  FIG.  1 C  is a schematic representation of IC device  100  in an un-programmed state as depicted in  FIGS.  1 A and  1 D , and  FIG.  1 F  is a schematic representation of IC device  100  in a programmed state as depicted in  FIG.  1 E . 
     Each of  FIGS.  1 A- 1 F  depicts currents IBL 1  and IBL 2  generated in response to an applied voltage during operation of IC device  100 .  FIG.  1 D  further depicts an electric field EF generated in response to an applied voltage during operation of IC device  100  in an un-programmed state. 
     The depictions of IC device  100  in  FIGS.  1 A- 1 F  are simplified for the purpose of clarity.  FIGS.  1 A,  1 B,  1 D, and  1 E  depict views of IC device  100  with various features included and excluded to facilitate the discussion below. In various embodiments, IC device  100  includes one or more metal interconnects, contacts, vias, gate structure or other transistor elements, wells, isolation structures, or the like, in addition to the elements depicted in  FIGS.  1 A,  1 B,  1 D, and  1 E . 
     As depicted in  FIGS.  1 A- 1 F , IC device  100  includes a transistor MNR 0 , an anti-fuse device MNP 0 , and a transistor MNR 1  formed in a substrate  100 B. Substrate  100 B is a portion of a semiconductor wafer, e.g., a semiconductor wafer  853  discussed below with respect to  FIG.  8   , suitable for forming one or more IC devices, e.g., IC device  100 . In various embodiments, substrate  100 B includes n-type silicon or p-type silicon. 
     Substrate  100 B includes an active area AA in which a lower portion of IC device  100  is located. Active area AA is a continuous section of substrate  100 B having either n-type or p-type doping that includes various semiconductor structures, including source-drain (S/D) structures SD 1 -SD 4 . In some embodiments, active area AA is located within a well (not shown), i.e., either an n-well or a p-well, within substrate  100 B. 
     In some embodiments, active area AA is electrically isolated from other elements in substrate  100 B by one or more isolation structures (not shown), e.g., one or more shallow trench isolation (STI) structures. 
     S/D structures SD 1 -SD 4  are semiconductor structures configured to have a doping type opposite to that of other portions of active area AA. In the embodiment depicted in  FIGS.  1 A- 1 F , active area AA has p-type doping and S/D structures SD 1 -SD 4  have n-type doping, indicated as diodes D 1  and D 2  in  FIGS.  1 E and  1 F . 
     In some embodiments, S/D structures are configured to have lower resistivity than other portions of active area AA. In some embodiments, S/D structures SD 1 -SD 4  include one or more portions having doping concentrations greater than one or more doping concentrations otherwise present throughout active area AA. In various embodiments, S/D structures SD 1 -SD 4  include epitaxial regions of a semiconductor material, e.g., silicon, silicon-germanium (SiGe), and/or silicon-carbide (SiC). 
     Transistor MNR 0  includes at least a portion of S/D structure SD 1 , a portion of S/D structure SD 2 , and a portion of active area AA between S/D structures SD 1  and SD 2 ; anti-fuse device MNP 0  includes a portion of S/D structure SD 2 , a portion of S/D structure SD 3 , and a portion of active area AA between S/D structures SD 2  and SD 3 ; and transistor MNR 1  includes a portion of S/D structure SD 3 , at least a portion of S/D structure SD 4 , and a portion of active area AA between S/D structures SD 3  and SD 4 . Anti-fuse device MNP 0  thereby shares S/D structure SD 2  with transistor MNR 0  and shares S/D structure SD 3  with transistor MNR 1 . In various embodiments, transistor MNR 0  shares S/D structure SD 1  with at least one other IC device (not shown) and/or transistor MNR 1  shares S/D structure SD 4  with at least one other IC device (not shown). 
     Transistor MNR 0  includes a gate structure GR 0  overlying a dielectric layer (not labeled) and portions of each of S/D structures SD 1  and SD 2  along the Z direction. The portion of active area AA directly below gate structure GR 0  and between S/D structures SD 1  and SD 2  is thereby configured as a channel (not shown) of transistor MNR 0 . In various embodiments, gate structure GR 0  extends in the positive and/or negative Y direction and is included in one or more transistors (not shown) in addition to transistor MNR 0 . 
     Transistor MNR 1  includes a gate structure GR 1  overlying a dielectric layer (not labeled) and portions of each of S/D structures SD 3  and SD 4  along the Z direction. The portion of active area AA directly below gate structure GR 1  and between S/D structures SD 3  and SD 4  is thereby configured as a channel (not shown) of transistor MNR 1 . In various embodiments, gate structure GR 1  extends in the positive and/or negative Y direction and is included in one or more transistors (not shown) in addition to transistor MNR 1 . 
     Anti-fuse device MNP 0  includes a gate structure GP 0  overlying a dielectric layer OXP and portions of each of S/D structures SD 2  and SD 3  along the Z direction. S/D structures SD 2  and SD 3  are thereby configured to control voltage levels of the portion of active area AA directly below gate structure GP 0  and dielectric layer OXP, and between S/D structures SD 2  and SD 3 . In various embodiments, gate structure GP 0  extends in the positive and/or negative Y direction and is included in one or more anti-fuse devices (not shown) in addition to anti-fuse device MNP 0 . 
     Each of gate structures GR 0 , GR 1 , and GP 0  is a volume including one or more conductive materials, e.g., poly silicon, one or more metals, and/or one or more other suitable materials, substantially surrounded by one or more insulating materials, e.g., silicon dioxide and/or one or more other suitable materials, and is thereby configured to control a voltage provided to an underlying dielectric layer, e.g., dielectric layer OXP, of IC device  100 . 
     Dielectric layer OXP includes a layer of one or more dielectric materials configured so that, in operation, a sufficiently large electric field across the dielectric layer sustainably alters at least one of the dielectric materials, thereby significantly decreasing the resistance of the dielectric layer from a level prior to application of the electric field. Sustainably altering the dielectric material is also referred to as breaking down the dielectric material or as programming anti-fuse device MNP 0  and/or IC device  100 , in some embodiments. 
     In various embodiments, dielectric layer OXP includes one or more of silicon dioxide and/or a high-k dielectric material, e.g., a dielectric material having a k value higher than 3.8 or 7.0. In some embodiments, a high-k dielectric material includes aluminum oxide, hafnium oxide, lanthanum oxide, or another suitable material. 
     IC device  100  includes a via structure V 2  overlying and electrically connected to gate structure GP 0 . A via structure, e.g., via structure V 2 , is one or more conductive elements configured to electrically connect an underlying structure, e.g., gate structure GP 0 , to an overlying conductive path, e.g., a conductive path WLP 0  (not shown in  FIG.  1 B ). Via structure V 2  is depicted in  FIG.  1 B , and is included in the schematic representation of conductive path WLP 0  depicted in  FIGS.  1 A   1 C- 1 F. 
     A conductive path, e.g., conductive path WLP 0 , is one or more conductive elements configured to provide a low-resistance electrical connection between first and second circuit elements. In various embodiments, conductive elements, also referred to as conductors, are IC structures including one or more conductive materials, e.g., copper, tungsten, aluminum, gold, titanium, polysilicon, or other materials suitable for forming a low resistance path. In some embodiments, a conductive element is a segment of a metal zero layer of a manufacturing process used to form IC device  100 . 
     Conductive path WLP 0 , also referred to as a conductive or bias voltage line in some embodiments, is configured as at least part of a low-resistance electrical connection between via structure V 2  and a first voltage source (not shown) external to IC device  100  and configured to provide a voltage WLP 0 V, also referred to as a signal in some embodiments. Gate structure GP 0  of anti-fuse device MNP 0  is thereby electrically connected to conductive path WLP 0  through via structure V 2 , and anti-fuse device MNP 0  is thereby configured to receive voltage WLP 0 V from the first voltage source in operation. 
     IC device  100  includes a via structure V 1  overlying and electrically connected to gate structure GR 0 , a via structure V 3  overlying and electrically connected to gate structure GR 1 , and a conductive element WLRM 0  overlying and electrically connected to each of via structures V 1  and V 3 . Conductive element WLRM 0  is part of a conductive path WLR 1 . Via structures V 1  and V 3  and conductive element WLRM 0  are depicted in  FIG.  1 B , and are included in the schematic representation of conductive path WLR 1  depicted in  FIGS.  1 A   1 C- 1 F. 
     In the embodiment depicted in  FIG.  1 B , via structures V 1  and V 3  are configured to electrically connect respective gate structures GR 0  and GR 1  to conductive path WLR 1  through the single conductive element WLRM 0 , and thereby couple gate structures GR 0  and GR 1  to each other. In some embodiments, via structures V 1  and V 3  are configured to electrically connect respective gate structures GR 0  and GR 1  to conductive path WLR 1 , and thereby couple gate structures GR 0  and GR 1  to each other through one or more conductive elements in addition to or instead of conductive element WLRM 0 . 
     Conductive path WLR 1 , also referred to as a selection signal line in some embodiments, is configured to electrically connect gate structures GR 0  and GR 1  to a second voltage source (not shown) external to IC device  100  and configured to provide a voltage WLR 1 V. Gate structures GR 0  and GR 1  of respective transistors MNR 0  and MNR 1  are thereby electrically connected to conductive path WLR 1  through respective via structures V 1  and V 3 , and each of transistors MNR 0  and MNR 1  is thereby configured to receive voltage WLR 1 V from the second voltage source in operation. 
     IC device  100  includes a contact structure C 1  overlying and electrically connected to S/D structure SD 1 . A contact structure, e.g., contact structure C 1 , is one or more conductive elements configured to electrically connect a substrate structure, e.g., S/D structure SD 1 , in an active area, e.g., active area AA, to an overlying conductive path, e.g., a conductive path BL. 
     Conductive path BL, also referred to as a bit line in some embodiments, is represented schematically in  FIGS.  1 A and  1 C- 1 F  and is configured to electrically connect contact structure C 1  to a third voltage source (not shown) external to IC device  100  and configured to provide a voltage BLV. S/D structure SD 1  of transistor MNR 0  is thereby electrically connected to conductive path BL, and IC device  100  is thereby configured to receive voltage BLV from the third voltage source in operation. 
     IC device  100  includes a contact structure C 2  overlying and electrically connected to S/D structure SD 4 , and electrically connected to overlying conductive path BL. S/D structure SD 4  of transistor MNR 1  is thereby electrically connected to conductive path BL, and IC device  100  is thereby configured to receive voltage BLV from the third voltage source in operation. 
     In some embodiments, contact structures C 1  and C 2  are electrically connected to a same conductive element of conductive path BL, and S/D structures SD 1  and SD 4  are thereby configured to receive voltage BLV from conductive path BL through respective contact structures C 1  and C 2 . In some embodiments, contact structures C 1  and C 2  are electrically connected to separate conductive elements of conductive path BL, and S/D structures SD 1  and SD 4  are otherwise configured to receive voltage BLV from conductive path BL through respective contact structures C 1  and C 2 . 
     In operation, transistors MNR 0  and MNR 1  are thereby configured to be simultaneously switched on or off responsive to voltage WLR 1 V received at respective gate structures GR 0  and GR 1  and voltage BLV received at respective S/D structures SD 1  and SD 4 . In the embodiment depicted in  FIGS.  1 A- 1 F , each of transistors MNR 0  and MNR 1  is an n-type transistor and is switched on in response to a value of voltage WLR 1 V above a value of voltage BLV by an amount equal to or greater than a threshold voltage of the corresponding one of transistor MNR 0  or MNR 1 . 
     In some embodiments, each of transistors MNR 0  and MNR 1  is a p-type transistor and is switched on in response to a value of voltage WLR 1 V below a value of voltage BLV by an amount equal to or greater than a threshold voltage of the corresponding one of transistor MNR 0  or MNR 1 . In various embodiments, the threshold voltages of transistors MNR 0  and MNR 1  are a same voltage value or have values that differ from each other. 
     By the configuration of IC device  100  discussed above, anti-fuse device MNP 0  and transistor MNR 0  are coupled in series between conduction paths WLP 0  and BL, and anti-fuse device MNP 0  and transistor MNR 1  are coupled in series between conduction paths WLP 0  and BL. Transistor MNR 0  is coupled to a first terminal of anti-fuse device MNP 0  at S/D structure SD 2 , and transistor MNR 1  is coupled to a second terminal of anti-fuse device MNP 0  at S/D structure SD 3 . Transistors MNR 0  and MNR 1  are thereby configured in parallel, each of transistors MNR 0  and MNR 1  being coupled between anti-fuse device MNP 0  and conductive path BL. 
     In operation, transistor MNR 0  being switched on causes the corresponding channel to become conductive, thereby allowing voltage BLV to be transferred from S/D structure SD 1  to S/D structure SD 2  and allowing current IBL 1  to flow from S/D structure SD 2  to S/D structure SD 1  through the low resistance path of the channel. Transistor MNR 1  being switched on causes the corresponding channel to become conductive, thereby allowing voltage BLV to be transferred from S/D structure SD 4  to S/D structure SD 3  and allowing current IBL 2  to flow from S/D structure SD 3  to S/D structure SD 4  through the low resistance path of the channel. 
     In operation, when transistors MNR 0  and MNR 1  are switched on, voltage WLP 0 V at gate structure GP 0  causes a current Ic to flow through dielectric layer OXP. A magnitude and polarity of current Ic are determined based on a magnitude and polarity of the difference between the values of voltages WLP 0 V and BLV. In the embodiment depicted in  FIGS.  1 A- 1 F , a positive value of current Ic represents voltage WLP 0 V having a value greater than that of voltage BLV. 
     Current IBL 1  is a first component of current Ic and flows from anti-fuse device MNP 0  to S/D structure SD 1  in the negative X direction. Current IBL 2  is a second component of current Ic and flows from anti-fuse device MNP 0  to S/D structure SD 4  in the positive X direction. A sum of currents IBL 1  and IBL 2  is equal to current Ic and to a current IBL in conductive path BL. 
     Relative magnitudes of currents IBL 1  and IBL 2  are based on resistance values of the corresponding current paths between gate structure GP 0  and conductive path BL. Based on the configuration discussed above, IC device  100  includes parallel current paths through which currents IBL 1  and IBL 2  flow, and current IBL is based on the total current through the two current paths. In operation, IC device  100  is thereby configured such that transistors MNR 0  and MNR 1  simultaneously couple anti-fuse device MNP 0  to conduction path BL. 
     Compared to approaches in which a single transistor couples an anti-fuse device to a bit line through a single current path, IC device  100  enables an increased current during read operations, thereby improving the ability to detect a programmed status of an anti-fuse device, e.g., anti-fuse device MNP 0 . The improved ability is most pronounced in cases in which an anti-fuse device has been weakly programmed, i.e., has a large resistance value relative to a resistance value of a strongly programmed anti-fuse device. 
       FIG.  1 D  depicts an operation in which voltages WLP 0 V and BLV are applied to IC device  100  in an un-programmed state, as represented schematically in  FIG.  1 C . In the un-programmed state, dielectric layer OXP of anti-fuse device MNP 0  has a large resistance value relative to the programmed state such that current Ic, and therefore voltage drops corresponding to currents IBL 1  and IBL 2 , are small enough to be ignored in the operation. 
     Accordingly, as illustrated in  FIG.  1 D , voltage BLV received at S/D structure SD 1  is considered to be received at S/D structure SD 2  via switched-on transistor MNR 0 , and voltage BLV received at S/D structure SD 4  is considered to be received at S/D structure SD 3  via switched-on transistor MNR 1  in operation. In response to the difference between the values of voltage VLP 0 V at gate structure GP 0  and voltage BLV at S/D structures SD 2  and SD 3 , an overall electric field is generated in anti-fuse device MNP 0 , a portion of which is in active area AA and is represented in  FIG.  1 D  as electric field EF. 
     In the embodiment depicted in  FIG.  1 D , because transistors MNR 0  and MNR 1  are symmetrically configured along the X direction with respect to anti-fuse device MNP 0 , in operation, voltage BLV at S/D structures SD 2  and SD 3  causes electric field EF to have a symmetric profile between S/D structures SD 2  and SD 3 . 
     As depicted in  FIG.  1 D , the symmetric profile of electric field EF includes a first field strength at each of S/D structures SD 2  and SD 3 , and a second field strength at a center of the portion of active area AA between S/D structures SD 2  and SD 3  and directly below gate structure GP 0 , the second field strength being lower than the first field strength. 
     In some embodiments, transistors MNR 0  and MNR 1  are not symmetrically configured along the X direction with respect to anti-fuse device MNP 0  and, in operation, voltage BLV at S/D structures SD 2  and SD 3  causes electric field EF to have a non-symmetric profile between S/D structures SD 2  and SD 3  that otherwise varies between one or two field strengths at S/D structures SD 2  and SD 3  and a lower field strength at a point between S/D structures SD 2  and SD 3 . 
     In approaches in which a single transistor is used to apply a voltage to an un-programmed anti-fuse device, the resultant electric field has a non-symmetric profile in which a field strength adjacent to the transistor continues to decrease as a distance from the transistor increases. Compared to such single transistor approaches, IC device  100  is configured as discussed above to apply a more uniform electric field across dielectric layer OXP in operation. 
     During a programming operation, a location at which a dielectric breakdown occurs is a function of the strengths of both the dielectric material and the electric field throughout the dielectric layer. By improving the uniformity of the electric field, IC device  100  increases a number of locations at which dielectric breakdown potentially occurs compared to single transistor approaches. In applications in which IC device  100  is part of an anti-fuse array, the increase in potential dielectric breakdown locations lowers an average resistance value of programmed devices and reduces a number of devices weakly programmed to resistance values substantially above the average, compared to single transistor approaches. 
       FIG.  1 E  depicts an operation in which voltages WLP 0 V and BLV are applied to IC device  100  in a programmed state, as represented schematically in  FIG.  1 F . In the programmed state, dielectric layer OXP of anti-fuse device MNP 0  has a small resistance value relative to the un-programmed state and is represented as a resistor Rox at an arbitrary location within dielectric layer OXP. A resistor Rb 0  represents a substrate resistance value between resistor Rox and S/D structure SD 2 , a resistor Rb 1  represents a substrate resistance value between resistor Rox and S/D structure SD 3 , a diode D 0  represents a junction between active area AA and S/D structure SD 2 , and a diode D 1  represents a junction between active area AA and S/D structure SD 3 . 
     Resistor Rb 0  and diode D 0  coupled in series between resistor Rox and transistor MNR 0  are thereby configured as a first current path in which current IBL 1  flows in operation. Resistor Rb 1  and diode D 1  coupled in series between resistor Rox and transistor MNR 1  are thereby configured as a second current path in which current IBL 2  flows in operation. The first and second current paths are arranged in parallel such that, in operation, the total current IBL is a function of the parallel combination of resistors Rb 0  and Rb 1  in addition to the difference between voltages WLP 0 V and BLV relative to voltage drops across diodes D 0  and D 1 . 
     In a case in which resistor Rox corresponds to a dielectric breakdown in the center of dielectric layer OXP along the X direction, resistors Rb 0  and Rb 1  have a same resistance value equal to approximately half of a total resistance value of active area AA between S/D structures SD 2  and SD 3 . In this case, the parallel combination of resistors Rb 0  and Rb 1  has an equivalent resistance value equal to approximately one quarter of the total resistance value. In some embodiments, the center of dielectric layer OXP along the X direction corresponds to a midpoint between S/D structures SD 2  and SD 3 . 
     In cases in which resistor Rox corresponds to a dielectric breakdown in dielectric layer OXP at a location other than the center along the X direction, one of resistors Rb 0  or Rb 1  has a resistance value equal to less than half of the total resistance value, and the parallel combination of resistors Rb 0  and Rb 1  has an equivalent resistance value less than one quarter of the total resistance value. 
     Thus, in the programmed state, a maximum equivalent substrate resistance of the parallel current path configuration of IC device  100  is approximately one quarter of the total resistance value of active area AA between S/D structures SD 2  and SD 3 . 
     In approaches in which a single transistor is used to apply a voltage to a programmed anti-fuse device, the resultant single current path has a resistance value that can vary from less than one quarter of a total substrate resistance to a value approaching an entirety of the total substrate resistance depending on a location of a dielectric breakdown. Compared to such single transistor approaches, IC device  100  is configured as discussed above to achieve a lower average substrate resistance value and thereby a more uniform distribution of substrate resistance values in applications in which IC device  100  is part of an anti-fuse array. In read operations, the relatively lower and less variable substrate resistance values cause read currents to be relatively higher and less variable, and thereby more easily distinguished, compared to single transistor approaches. 
       FIGS.  2 A- 2 C  are diagrams of an IC device  200 , in accordance with some embodiments. In some embodiments, IC device  200  is formed by executing some or all of the operations of method  400  and/or method  500  and/or is configured based on an IC layout diagram  600 A or  600 B, discussed below with respect to  FIGS.  4 - 6 B . In some embodiments, IC device  200  is included in an IC device  860  manufactured by an IC manufacturer/fabricator (“fab”)  850 , discussed below with respect to  FIG.  8   . 
       FIG.  2 A  depicts a cross-sectional view of IC device  200  along plane A-A′ including the X and Z directions discussed above with respect to  FIGS.  1 A- 1 F ,  FIG.  2 B  depicts a plan view of IC device  200 - 1 , an embodiment of IC device  200 , and the X and Y directions,  FIG.  2 C  depicts a plan view of IC device  200 - 2 , an embodiment of IC device  200 , and the X and Y directions, and  FIG.  2 D  is a schematic representation of IC device  200 . 
     The depictions of IC device  200  in  FIGS.  2 A- 2 D  are simplified for the purpose of clarity.  FIGS.  2 A- 2 C  depict views of IC device  200  with various features included and excluded to facilitate the discussion below. In various embodiments, IC device  200  includes one or more metal interconnects, contacts, vias, gate structure or other transistor elements, wells, isolation structures, or the like, in addition to the elements depicted in  FIGS.  2 A- 2 C . 
     IC device  200  includes anti-fuse device MNP 0  and transistors MNR 0  and MNR 1  including S/D structures SD 1 -SD 4  and portions of active area AA, contact structures C 1  and C 2 , via structures V 1 -V 3 , conductive element WLRM 0 , and conductive paths WLR 1  and WLP 0 , each discussed above with respect to  FIGS.  1 A- 1 F . IC device  200  also includes an anti-fuse device MNP 1  and transistors MNR 2  and MNR 3  including S/D structures SD 4 -SD 7  and portions of active area AA, a contact structure C 3 , via structures V 4 -V 6 , a conductive element WLRM 1 , and conductive paths WLR 2  and WLP 1 . 
     Anti-fuse device MNP 1 , transistors MNR 2  and MNR 3 , S/D structures SD 4 -SD 7 , contact structure C 3 , via structures V 4 -V 6 , conductive element WLRM 1 , and conductive paths WLR 2  and WLP 1  have configurations that correspond to those of anti-fuse device MNP 0 , transistors MNR 0  and MNR 1 , S/D structures SD 1 -SD 4 , contact structures C 1  and C 2 , via structures V 1 -V 3 , conductive element WLRM 0 , and conductive paths WLR 1  and WLP 0 , respectively, as discussed above with respect to  FIGS.  1 A- 1 F ; thus, detailed descriptions thereof are omitted. 
       FIGS.  2 A- 2 D  depict currents IBL 1  and IBL 2 , and  FIGS.  2 A and  2 D  depict current IBL, each discussed above with respect to  FIGS.  1 A- 1 F .  FIGS.  2 A- 2 D  also depict currents IBL 3  and IBL 4  discussed below. 
     As depicted in  FIGS.  2 A- 2 D , each of transistors MNR 1  and MNR 2  includes a portion of S/D structure SD 4 , transistors MNR 1  and MNR 2  thereby sharing S/D structure SD 4 . Similarly, anti-fuse device MNP 1  shares S/D structure SD 5  with transistor MNR 2  and shares S/D structure SD 6  with transistor MNR 3 . In some embodiments, transistor MNR 3  shares S/D structure SD 7  with at least one other IC device (not shown). 
     Via structure V 5  overlies and electrically connects a gate structure (not labeled) of anti-fuse device MNP 1  to conductive path WLP 1 . Via structure V 5  is depicted in  FIGS.  2 B and  2 C , and is included in the schematic representation of conductive path WLP 1  depicted in  FIGS.  2 A and  2 D . 
     Conductive path WLP 1 , also referred to as a conductive or bias voltage line in some embodiments, is configured as at least part of a low-resistance electrical connection between via structure V 5  and a fourth voltage source (not shown) external to IC device  200  and configured to provide a voltage WLP 1 V, also referred to as a signal in some embodiments. The gate structure of anti-fuse device MNP 1  is thereby electrically connected to conductive path WLP 1  through via structure V 5 , and anti-fuse device MNP 1  is thereby configured to receive voltage WLP 1 V from the fourth voltage source in operation. 
     Via structure V 4  overlies and electrically connects a gate structure (not labeled) of transistor MNR 2  to conductive element WLRM 1 , and via structure V 6  overlies and electrically connects a gate structure (not labeled) of transistor MNR 3  to conductive element WLRM 1 . Conductive element WLRM 1  is part of conductive path WLR 2 . Via structures V 4  and V 6  and conductive element WLRM 1  are depicted in  FIGS.  2 B and  2 C , and are included in the schematic representation of conductive path WLR 2  depicted in  FIGS.  2 A and  2 D . 
     In the embodiment depicted in  FIGS.  2 B and  2 C , via structures V 4  and V 6  are configured to electrically connect the gate structures of transistors MNR 2  and MNR 3  to conductive path WLR 2  through the single conductive element WLRM 1 , and thereby couple the gate structures of transistors MNR 2  and MNR 3  to each other. In some embodiments, via structures V 4  and V 6  are configured to electrically connect respective gate structures of transistors MNR 2  and MNR 3  to conductive path WLR 2 , and thereby couple the gate structures of transistors MNR 2  and MNR 3  to each other through one or more conductive elements in addition to or instead of conductive element WLRM 1 . 
     Conductive path WLR 2 , also referred to as a selection signal line in some embodiments, is configured to electrically connect the gate structures of transistors MNR 2  and MNR 3  to a fifth voltage source (not shown) external to IC device  200  and configured to provide a voltage WLR 2 V. The gate structures of transistors MNR 2  and MNR 3  are thereby electrically connected to conductive path WLR 2  through respective via structures V 4  and V 6 , and each of transistors MNR 2  and MNR 3  is thereby configured to receive voltage WLR 2 V from the fifth voltage source in operation. 
     Contact structure C 3  overlies S/D structure SD 7  and is configured to electrically connect S/D structure SD 7  to conductive path BL. S/D structure SD 7  of transistor MNR 3  is thereby configured to receive voltage BLV from the third voltage source in operation. 
     In some embodiments, contact structures C 1 , C 2 , and C 3  are electrically connected to a same conductive element of conductive path BL, and S/D structures SD 1 , SD 4 , and SD 7  are thereby configured to receive voltage BLV from conductive path BL through respective contact structures C 1 , C 2 , and C 3 . In various embodiments, one or more of contact structures C 1 , C 2 , and C 3  are electrically connected to separate conductive elements of conductive path BL, and S/D structures SD 1 , SD 4 , and SD 7  are otherwise configured to receive voltage BLV from conductive path BL through respective contact structures C 1 , C 2 , and C 3 . 
       FIG.  2 B  depicts IC device  200 - 1 , an embodiment of IC device  200  in which via structures V 1 , V 3 , V 4 , and V 6  and conductive elements WLRM 0  and WLRM 1  are positioned at locations away from active area AA in the positive Y direction, and via structures V 2  and V 5  are positioned at locations away from active area AA in the negative Y direction. In some embodiments, via structures V 1 , V 3 , V 4 , and V 6  and conductive elements WLRM 0  and WLRM 1  are positioned at locations away from active area AA in the negative Y direction, and via structures V 2  and V 5  are positioned at locations away from active area AA in the positive Y direction. 
     In the embodiment depicted in  FIG.  2 B , via structures V 1 , V 3 , V 4 , and V 6  and conductive elements WLRM 0  and WLRM 1  are aligned with each other in the X direction and via structures V 2  and V 5  are aligned with each other in the X direction. In various embodiments, one or more of via structures V 1 , V 3 , V 4 , and/or V 6  and/or conductive elements WLRM 0  and/or WLRM 1  is not aligned with another one or more of via structures V 1 , V 3 , V 4 , and/or V 6  and/or conductive elements WLRM 0  and/or WLRM 1  in the X direction and/or via structures V 2  and V 5  are not aligned with each other in the X direction. 
       FIG.  2 C  depicts IC device  200 - 2 , an embodiment of IC device  200  in which via structures V 1 , V 3 , and V 5  and conductive element WLRM 0  are positioned at locations away from active area AA in the positive Y direction, and via structures V 2 , V 4 , and V 6  and conductive element WLRM 1  are positioned at locations away from active area AA in the negative Y direction. In some embodiments, via structures V 1 , V 3 , and V 5  and conductive element WLRM 0  are positioned at locations away from active area AA in the negative Y direction, and via structures V 2 , V 4 , and V 6  and conductive element WLRM 1  are positioned at locations away from active area AA in the positive Y direction. 
     In the embodiment depicted in  FIG.  2 C , via structures V 1 , V 3 , and V 5  and conductive element WLRM 0  are aligned with each other in the X direction and via structures V 2 , V 4 , and V 6  and conductive element WLRM 1  are aligned with each other in the X direction. In various embodiments, one or more of via structures V 1 , V 3 , and/or V 5  and/or conductive element WLRM 0  is not aligned with another one or more of via structures V 1 , V 3 , and/or V 5  and/or conductive element WLRM 0  in the X direction and/or one or more of via structures V 2 , V 4 , and/or V 6  and/or conductive element WLRM 1  is not aligned with another one or more of via structures V 2 , V 4 , and/or V 6  and/or conductive element WLRM 1  in the X direction. 
     In operation, transistors MNR 2  and MNR 3  are configured as discussed above to be simultaneously switched on or off responsive to voltage WLR 2 V received at their respective gate structures, and to voltage BLV received at respective S/D structures SD 4  and SD 7 , in the manner discussed above with respect to transistors MNR 0  and MNR 1 . When transistors MNR 2  and MNR 3  are switched on, voltage WLP 1 V at the gate structure of anti-fuse device MNP 1  causes anti-fuse device MNP 1  to be biased in the manner discussed above with respect to anti-fuse device MNP 0 , and causes currents IBL 3  and IBL 4  to flow as depicted in  FIGS.  2 A- 2 D  and in the manner discussed above with respect to respective currents IBL 1  and IBL 2 . 
     Accordingly, in operation, current IBL 3  flows from anti-fuse device MNP 1  to S/D structure SD 4  in the negative X direction, current IBL 4  flows from anti-fuse device MNP 1  to S/D structure SD 7  in the positive X direction, and a sum of currents IBL 3  and IBL 4  is equal to current IBL in conductive path BL. 
     IC device  200  is configured so that only one of anti-fuse devices MNP 0  or MNP 1  is biased at a time, current IBL thereby alternatively including the pair of currents IBL 1  and IBL 2  or the pair of currents IBL 3  and IBL 4 . In various embodiments, IC device  200  includes one or more anti-fuse devices (not shown) in addition to anti-fuse devices MNP 0  and MNP 1 , and is configured so that current IBL alternatively includes one more pairs of currents (not shown) in addition to pairs of currents IBL 1  and IBL 2  and currents IBL 3  and IBL 4 . 
     In the embodiment depicted in  FIGS.  2 A- 2 D , IC device  200  includes a single active area AA, conductive path WLP 0  is electrically connected to a single anti-fuse device MNP 0 , conductive path WLP 1  is electrically connected to a single anti-fuse device MNP 1 , conductive path WLR 1  is electrically connected to a single pair of transistors MNR 0  and MNR 1 , and conductive path WLR 2  is electrically connected to a single pair of transistors MNR 2  and MNR 3 . In various embodiments, IC device  200  includes one or more additional active areas (not shown) including one or more additional pairs of anti-fuse devices (not shown) such that one or more of conductive path WLP 0  is electrically connected to a plurality of anti-fuse devices including anti-fuse device MNP 0 , conductive path WLP 1  is electrically connected to a plurality of anti-fuse devices including anti-fuse device MNP 1 , conductive path WLR 1  is electrically connected to a plurality of pairs of transistors including pair of transistors MNR 0  and MNR 1 , or conductive path WLR 2  is electrically connected to a plurality of pairs of transistors including pair of transistors MNR 2  and MNR 3 . 
     By the configuration discussed above, IC device  200  includes a plurality of anti-fuse devices, e.g., anti-fuse devices MNP 0  and MNP 1 , each anti-fuse device corresponding to a pair of transistors, e.g., transistors MNR 0  and MNR 1  and transistors MNR 2  and MNR 3 , configured as discussed above with respect to IC device  100  and  FIGS.  1 A- 1 F . IC device  200  is thereby configured to be capable of realizing the benefits discussed above with respect to IC device  100 . 
       FIG.  3    is a flowchart of a method  300  of operating a circuit, in accordance with some embodiments. Method  300  is usable with a circuit including an anti-fuse device, e.g., IC device  100  discussed above with respect to  FIGS.  1 A- 1 F  or IC device  200  discussed above with respect to  FIGS.  2 A- 2 D . 
     In some embodiments, operating a circuit using method  300  includes performing a program or read operation on the anti-fuse device. In some embodiments, operating the circuit using method  300  includes breaking down a dielectric layer, e.g., dielectric layer OXP discussed above with respect to IC device  100  and  FIGS.  1 A- 1 F . 
     The sequence in which the operations of method  300  are depicted in  FIG.  3    is for illustration only; the operations of method  300  are capable of being executed in sequences that differ from that depicted in  FIG.  3   . In some embodiments, operations in addition to those depicted in  FIG.  3    are performed before, between, during, and/or after the operations depicted in  FIG.  3   . In some embodiments, the operations of method  300  are a subset of operations of a method of operating a memory array. 
     At operation  310 , a voltage is received at a gate of an anti-fuse device. Receiving the voltage includes receiving the voltage having a voltage value configured to perform a program or read operation on the anti-fuse device. 
     In some embodiments, the anti-fuse device is one anti-fuse device of a plurality of anti-fuse devices, and receiving the voltage includes selecting the anti-fuse device from the plurality of anti-fuse devices. In some embodiments, receiving the voltage includes receiving the voltage at gates of a subset, e.g., a column, of the plurality of anti-fuse devices. 
     In various embodiments, receiving the voltage includes receiving voltage WLP 0 V at gate structure GP 0  of anti-fuse device MNP 0 , discussed above with respect to  FIGS.  1 A- 2 D , or the gate structure of anti-fuse device MNP 1 , discussed above with respect to  FIGS.  2 A- 2 D . 
     In some embodiments, receiving the voltage includes receiving the voltage through a via structure. In some embodiments, receiving the voltage through the via structure includes receiving the voltage through via structure V 2  or V 5 , discussed above with respect to  FIGS.  1 A- 2 D . 
     At operation  320 , the anti-fuse device is coupled to a bit line using a first transistor and a second transistor simultaneously. Coupling the anti-fuse device to the bit line includes simultaneously switching on the first and second transistors, thereby providing parallel current paths between the anti-fuse device and the bit line. 
     In some embodiments, coupling the anti-fuse device to the bit line includes coupling anti-fuse device MNP 0  to conductive path BL using transistors MNR 0  and MNR 1 , discussed above with respect to  FIGS.  1 A- 2 D , or coupling anti-fuse device MNP 1  to conductive path BL using transistors MNR 2  and MNR 3 , discussed above with respect to  FIGS.  2 A- 2 D . 
     In some embodiments, using the first transistor and the second transistor simultaneously includes receiving a same signal at a gate of the first transistor and a gate of the second transistor. In some embodiments, receiving the same signal includes the first transistor receiving the signal through a first via and the second transistor receiving the signal through a second via. In some embodiments, receiving the signal through the first via includes receiving the signal from a conductive element, e.g., a metal segment, and receiving the signal through the second via includes receiving the signal from the same conductive element. In various embodiments, receiving the signal from the conductive element includes receiving the signal from conductive element WLRM 0  or WLRM 1 , discussed above with respect to  FIGS.  1 B,  2 B, and  2 C . 
     In some embodiments, the first and second transistors are one transistor pair of a plurality of transistor pairs, and receiving the same signal includes selecting the first and second transistors from the plurality of transistor pairs. In some embodiments, receiving the same signal includes receiving one signal of a plurality of signals corresponding to a subset, e.g., a row or word, of a plurality of anti-fuse devices corresponding to the plurality of transistor pairs. In some embodiments, receiving the same signal includes receiving one of voltages WLR 1 V or WLR 2 V, discussed above with respect to  FIGS.  1 A- 2 D . 
     In some embodiments, coupling the anti-fuse device to the bit line includes the anti-fuse device receiving a voltage from the bit line. In some embodiments, receiving the voltage from the bit line includes transferring the voltage from a first S/D structure of the first transistor to an S/D structure shared by the first transistor and the anti-fuse device, and transferring the voltage from a first S/D structure of the second transistor to an S/D structure shared by the second transistor and the anti-fuse device. In some embodiments, receiving the voltage from the bit line includes receiving voltage BLV from conductive path BL, discussed above with respect to  FIGS.  1 A- 2 D . 
     In some embodiments, coupling the anti-fuse device to the bit line includes causing the anti-fuse device to change from an un-programmed state to a programmed state. In some embodiments, coupling the anti-fuse device to the bit line includes applying an electric field to a dielectric layer of the anti-fuse device, the electric field having a symmetry based on the first transistor and the second transistor. In some embodiments, coupling the anti-fuse device to the bit line includes programming the anti-fuse device by breaking down the dielectric layer between the gate and a portion of a substrate between the first transistor and the second transistor. In some embodiments, coupling the anti-fuse device to the bit line includes applying an electric field to dielectric layer OXP, discussed above with respect to  FIGS.  1 A- 2 D . 
     In some embodiments, coupling the anti-fuse device to the bit line includes generating a current in the bit line, the current including a first component flowing through the first transistor in a first direction and a second component flowing through the second transistor in a second direction opposite the first direction. In some embodiments, the first component flows through a first contact structure, the second component flows through a second contact structure, and the anti-fuse device and first and second transistors are positioned between the first and second contact structures. In some embodiments, the first and second components flow through contact structures C 1  and C 2  or through contact structures C 2  and C 3 , discussed above with respect to  FIGS.  1 A- 2 D . 
     In some embodiments, generating the current in the bit line includes generating the current at a location of a dielectric breakdown in the dielectric layer of the anti-fuse device. In some embodiments, generating the current in the bit line includes generating the current through parallel substrate current paths based on the location of the dielectric breakdown. The parallel substrate current paths have an equivalent substrate resistance value based on the location of the dielectric breakdown, and generating the current is based on a maximum equivalent substrate resistance value corresponding to the dielectric breakdown location at a midpoint between the first and second transistors. In some embodiments, generating the current in the bit line includes generating the current based on resistors Rb 0  and Rb 1 , discussed above with respect to  FIGS.  1 E and  1 F . 
     In some embodiments, the anti-fuse device is one anti-fuse device of a plurality of anti-fuse devices, e.g., an anti-fuse array, and generating the current in the bit line includes generating the current as part of a read operation on the plurality of anti-fuse devices. 
     At operation  330 , in some embodiments, a second voltage is received at a gate of a second anti-fuse device, and the second anti-fuse device is coupled to a second bit line using a third transistor and a fourth transistor simultaneously. The anti-fuse device and the second anti-fuse device are included in a plurality of anti-fuse devices, and receiving the second voltage includes selecting the second anti-fuse device from the plurality of anti-fuse devices. In various embodiments, selecting the second anti-fuse device includes selecting the second anti-fuse device separately from selecting the anti-fuse device or selecting the anti-fuse device and the second anti-fuse device simultaneously. 
     In various embodiments, receiving the second voltage at the gate of the second anti-fuse device includes receiving the second voltage at the second anti-fuse device in a same active area as the anti-fuse device or in an active area different from an active area of the anti-fuse device. 
     In various embodiments, coupling the second anti-fuse device to the second bit line includes coupling the anti-fuse and second anti-fuse devices to a same bit line or to different bit lines. 
     In some embodiments, receiving the second voltage includes receiving voltage WLP 1 V at the gate of anti-fuse device MNP 1 , and using the third and fourth transistors includes using transistors MNR 2  and MNR 3 , discussed above with respect to  FIGS.  2 A- 2 D . 
     In some embodiments, coupling the second anti-fuse device to the second bit line includes generating a second current in the second bit line, the second current including a first component flowing through the third transistor in the second direction and a second component flowing through the fourth transistor in the first direction. In some embodiments, the first component of the second current flows through a contact structure shared between the third transistor and the second transistor of the anti-fuse device. 
     In some embodiments, the first component of the second current flows through contact structure C 2  shared between the transistor MNR 2  and transistor MNR 1  of anti-fuse device MNP 0 , discussed above with respect to  FIGS.  2 A- 2 D . 
     By executing some or all of the operations of method  300 , an operation, e.g., a program or read operation, is performed on a circuit in which an anti-fuse device receives a voltage and is coupled to a bit line using first and second transistors simultaneously, thereby achieving the benefits discussed above with respect to IC device  100 . 
       FIG.  4    is a flowchart of a method  400  of manufacturing an anti-fuse device, in accordance with some embodiments. Method  400  is operable to form any of IC devices  100  or  200 , discussed above with respect to  FIGS.  1 A- 2 D . 
     The sequence in which the operations of method  400  are depicted in  FIG.  4    is for illustration only; the operations of method  400  are capable of being executed simultaneously and/or in sequences that differ from that depicted in  FIG.  4   . In some embodiments, operations in addition to those depicted in  FIG.  4    are performed before, between, during, and/or after the operations depicted in  FIG.  4   . 
     In some embodiments, one or more operations of method  400  are a subset of operations of a method of forming a memory array. In some embodiments, one or more operations of method  400  are a subset of operations of an IC manufacturing flow, e.g., an IC manufacturing flow discussed below with respect to a manufacturing system  800  and  FIG.  8   . 
     At operation  410 , an anti-fuse device is formed on a substrate, e.g., substrate  100 B discussed above with respect to  FIGS.  1 A- 2 D . Forming the anti-fuse device includes forming a first gate structure, a first S/D structure in an active area, and a second S/D structure in the active area, the first gate structure partially overlying each of the first and second S/D structures. 
     Forming the first and second S/D structures includes performing one or more manufacturing operations in accordance with forming S/D structures SD 2  and SD 3  and active area AA, discussed above with respect to  FIGS.  1 A- 2 D . Forming the first gate structure includes performing one or more manufacturing operations in accordance with forming gate structure GP 0 , and forming the anti-fuse device thereby includes performing one or more manufacturing operations in accordance with forming anti-fuse device MNP 0 , discussed above with respect to  FIGS.  1 A- 2 D . 
     In some embodiments, forming the anti-fuse device includes constructing an electrical connection between the first gate structure and a conductive path configured to carry a first voltage. Constructing the electrical connection includes performing one or more manufacturing operations in accordance with constructing via structure V 2  and, in some embodiments, some or all of conductive path WLP 0 , discussed above with respect to  FIGS.  1 A- 2 D . 
     In some embodiments, forming the anti-fuse device includes forming one anti-fuse device as part of forming a plurality of anti-fuse devices, e.g., an anti-fuse device array. 
     At operation  420 , a first transistor including the first S/D structure and a second transistor including the second S/D structure are formed. Forming the first and second transistors includes forming the first transistor at a position away from the anti-fuse device in a first direction, and forming the second transistor at a position away from the anti-fuse device in a second direction opposite the first direction, the anti-fuse device thereby being formed between the first and second transistors. 
     Forming the first transistor includes forming a second gate structure and a third S/D structure in the active area, the second gate structure partially overlying each of the first and third S/D structures. Forming the second transistor includes forming a third gate structure and a fourth S/D structure in the active area, the third gate structure partially overlying each of the second and fourth S/D structures. 
     Forming the third and fourth S/D structures includes performing one or more manufacturing operations in accordance with forming S/D structures SD 1  and SD 4 , discussed above with respect to  FIGS.  1 A- 2 D . Forming the second and third gate structures includes performing one or more manufacturing operations in accordance with forming respective gate structures GR 0  and GR 1 , and forming the first and second transistors thereby includes performing one or more manufacturing operations in accordance with forming respective transistors MNR 0  and MNR 1 , discussed above with respect to  FIGS.  1 A- 2 D . 
     In some embodiments, forming the first and second transistors includes forming one transistor pair as part of forming a plurality of transistor pairs of a corresponding plurality of anti-fuse devices, e.g., an anti-fuse device array. 
     At operation  430 , an electrical connection between gates of the first and second transistors is constructed. Constructing the electrical connection includes constructing an electrical connection between each of the second and third gate structures and a conductive path configured to carry a second voltage. Constructing the electrical connection includes performing one or more manufacturing operations in accordance with forming via structures V 1  and V 3 , discussed above with respect to  FIGS.  1 A- 2 D . 
     In some embodiments, constructing the electrical connection includes constructing a conductive segment in a metal zero layer of the manufacturing process. In some embodiments, constructing the electrical connection includes performing one or more manufacturing operations in accordance with forming conductive element WLRM 0 , discussed above with respect to  FIGS.  1 A- 2 D . 
     In some embodiments, constructing the electrical connection includes constructing the electrical connection between gates of one transistor pair as part of constructing electrical connections between gates of a plurality of transistor pairs of a corresponding plurality of anti-fuse devices, e.g., an anti-fuse device array. 
     At operation  440 , an electrical connection between the third S/D structure of the first transistor and the fourth S/D structure of the second transistor is constructed. Constructing the electrical connection includes constructing an electrical connection between each of the third and fourth S/D structures and a conductive path configured to carry a third voltage. Constructing the electrical connection includes performing one or more manufacturing operations in accordance with forming contact structures C 1  and C 2 , discussed above with respect to  FIGS.  1 A- 2 D . 
     In some embodiments, constructing the electrical connection includes constructing a conductive segment in a metal zero layer of the manufacturing process. In some embodiments, constructing the electrical connection includes performing one or more manufacturing operations in accordance with forming conductive path BL, discussed above with respect to  FIGS.  1 A- 2 D . 
     In some embodiments, constructing the electrical connection includes constructing the electrical connection between S/D structures of one transistor pair as part of constructing electrical connections between S/D structures of a plurality of transistor pairs of a corresponding plurality of anti-fuse devices, e.g., an anti-fuse device array. 
     The operations of method  400  are usable to form an IC device that includes at least one anti-fuse device positioned between a pair of electrically connected transistors and is thereby configured to have the properties, and thus the benefits, discussed above with respect to IC devices  100  and  200 . 
       FIG.  5    is a flowchart of a method  500  of generating an IC layout diagram, in accordance with some embodiments. In some embodiments, generating the IC layout diagram includes generating an IC layout diagram, e.g., IC layout diagram  600 A or  600 B discussed below, of an IC device, e.g., IC device  100  or  200  discussed above with respect to  FIGS.  1 A- 2 D , manufactured based on the generated IC layout diagram. Non-limiting examples of IC devices include memory circuits, logic devices, processing devices, signal processing circuits, and the like. 
     In some embodiments, some or all of method  500  is executed by a processor of a computer. In some embodiments, some or all of method  500  is executed by a processor  702  of EDA system  700 , discussed below with respect to  FIG.  7   . 
     Some or all of the operations of method  500  are capable of being performed as part of a design procedure performed in a design house, e.g., design house  820  discussed below with respect to  FIG.  8   . 
     In some embodiments, the operations of method  500  are performed in the order depicted in  FIG.  5   . In some embodiments, the operations of method  500  are performed simultaneously and/or in an order other than the order depicted in  FIG.  5   . In some embodiments, one or more operations are performed before, between, during, and/or after performing one or more operations of method  500 . 
       FIGS.  6 A and  6 B  are depictions of non-limiting examples of respective IC layout diagrams  600 A and  600 B generated by executing one or more operations of method  500 , in some embodiments. In addition to IC layout diagram  600 A or  600 B, each of  FIGS.  6 A and  6 B  includes the X and Y directions, discussed above with respect to  FIGS.  1 B,  2 B, and  2 C . 
     IC layout diagrams  600 A and  600 B are simplified for the purpose of clarity. In various embodiments, one or more of IC layout diagrams  600 A and  600 B includes features in addition to those depicted in  FIGS.  6 A and  6 B , e.g., one or more transistor elements, power rails, isolation structures, wells, conductive elements, or the like. 
     Each of IC layout diagrams  600 A and  600 B corresponds to an anti-fuse cell and includes a first cell bit CB 1  including layout components corresponding to anti-fuse device MNP 0  and transistors MNR 0  and MNR 1 , discussed above with respect to  FIGS.  1 A- 2 D , and a bit line region BLR discussed below. In some embodiments, one or both of IC layout diagrams  600 A or  600 B does not include bit line region BLR. 
     In the embodiments depicted in  FIGS.  6 A and  6 B , IC layout diagram  600 A includes a second cell bit CB 2 A, and IC layout diagram  600 B includes a second cell bit CB 2 B. Each of cell bits CB 2 A and CB 2 B includes layout components corresponding to anti-fuse device MNP 1  and transistors MNR 2  and MNR 3 , discussed above with respect to  FIGS.  2 A- 2 D . Cell bits CB 2 A and CB 2 B differ in the arrangement of the layout components as discussed below. In various embodiments, one or both of IC layout diagrams  600 A or  600 B does not include corresponding cell bit CB 2 A or CB 2 B, and/or includes one or more additional cell bits (not shown) in addition to cell bit CB 1  and, if present cell bit CB 2 A or CB 2 B. 
     Cell bit CB 1  includes gate regions G 1 -G 3  intersecting an active region AR, via regions VR 1 -VR 3  overlying respective gate regions G 1 -G 3 , a conductive region WLRR 0  overlying via regions VR 1  and VR 3  and intersecting gate regions G 1 -G 3 , and contact regions CR 1  and CR 2  overlying active region AR and underlying bit line region BLR. In the embodiment depicted in  FIGS.  6 A and  6 B , via regions VR 1  and VR 3  and conductive region WLRR 0  are positioned at locations away from active region AR in the positive Y direction, and via region VR 2  is positioned at a location away from active region AR in the negative Y direction. In some embodiments, via regions VR 1  and VR 3  and conductive region WLRR 0  are positioned at locations away from active region AR in the negative Y direction, and via region VR 2  is positioned at a location away from active region AR in the positive Y direction. 
     Each of cell bits CB 2 A and CB 2 B includes gate regions G 4 -G 6  intersecting active region AR, via regions VR 4 -VR 6  overlying respective gate regions G 4 -G 6 , a conductive region WLRR 1  overlying via regions VR 4  and VR 6  and intersecting gate regions G 4 -G 6 , and contact regions CR 2  and CR 3  overlying active region AR and underlying bit line region BLR. Cell bit CB 2 A includes via regions VR 4  and VR 6  and conductive region WLRR 1  aligned with via regions VR 1  and VR 3  and conductive region WLRR 0  of cell bit CB 1  in the X direction, and via region VR 5  aligned with via region VR 2  of cell bit CB 1  in the X direction. Cell bit CB 2 B includes via region VR 5  aligned with via regions VR 1  and VR 3  and conductive region WLRR 0  of cell bit CB 1  in the X direction, and via regions VR 4  and VR 6  and conductive region WLRR 1  aligned with via region VR 2  of cell bit CB 1  in the X direction. 
     By the configurations depicted in  FIGS.  6 A and  6 B  and discussed above, active region AR and contact region CR 2  are included in each of cell bits CB 1 , CB 2 A, and CB 2 B. In some embodiments, bit line region BLR is included in each of cell bits CB 1 , CB 2 A, and CB 2 B. 
     An active region, e.g., active region AR, is a region in the IC layout diagram included in a manufacturing process as part of defining an active area, also referred to as an oxide diffusion or definition (OD), in a semiconductor substrate in which one or more IC device features, e.g., a source/drain region, is formed. In various embodiments, an active area is an n-type or p-type active area of a planar transistor or a fin, field-effect transistor (FinFET). In some embodiments, active region AR is included in a manufacturing process as part of defining active area AA discussed above with respect to  FIGS.  1 A- 2 D . 
     A gate region, e.g., a gate region G 1 -G 6 , is a region in the IC layout diagram included in the manufacturing process as part of defining a gate structure in the IC device including at least one of a conductive material or a dielectric material. In various embodiments, one or more gate structures corresponding to a gate region includes at least one conductive material overlying at least one dielectric material. In some embodiments, gate regions G 1 -G 3  are included in a manufacturing process as part of defining respective gate structures GR 0 , GP 0 , and GR 1  discussed above with respect to  FIGS.  1 A- 2 D , and gate regions G 4 -G 6  are included in a manufacturing process as part of defining gate structures of transistor MNR 2 , anti-fuse device MNP 1 , and transistor MNR 3 , respectively, discussed above with respect to  FIGS.  2 A- 2 D . 
     A conductive region, e.g., conductive region WLRR 0  or WLRR 1  or bit line region BLR, is a region in the IC layout diagram included in the manufacturing process as part of defining one or more segments of one or more conductive layers in the IC device. In various embodiments, one or more conductive regions, e.g., one or more of conductive regions WLRR 0  or WLRR 1  or bit line region BLR, corresponds to one or more segments of a same or different conductive layers in the IC device. In various embodiments, a conductive region corresponds to one or more of a metal zero, a metal one, or a higher metal layer in the IC device. In some embodiments, conductive regions WLRR 0  or WLRR 1  or bit line region BLR are included in a manufacturing process as part of defining conductive elements WLRM 0  and WLRM 1  and conduction path BL, respectively, discussed above with respect to  FIGS.  1 A- 2 D . 
     A via region, e.g., a via region VR 1 -VR 6 , is a region in the IC layout diagram included in the manufacturing process as part of defining one or more segments of one or more conductive layers in the IC device configured to form an electrical connection between one or more conductive elements corresponding to a conductive region, e.g., conductive region WLRR 0  or WLRR 1 , and a gate structure corresponding to a gate region, e.g., a respective gate region G 1 -G 6 . In various embodiments, the one or more conductive layer segments formed based on a via region includes a via between a corresponding gate structure and a corresponding conductive element in an overlying metal layer, e.g., a metal zero layer, of the IC device. In some embodiments, via regions VR 1 -VR 6  are included in a manufacturing process as part of defining respective via structures V 1 -V 6  discussed above with respect to  FIGS.  1 A- 2 D . 
     A contact region, e.g., a contact region CR 1 -CR 3  is a region in the IC layout diagram included in the manufacturing process as part of defining one or more segments of one or more conductive layers in the IC device configured to form an electrical connection between the one or more conductive elements based on a conductive region, e.g., bit line region BLR, and the active area based on an active region, e.g., active region AR. In various embodiments, the one or more conductive layer segments formed based on a contact region includes a contact between the active area based on the active region and the one or more conductive elements based on the conductive region in an overlying metal layer, e.g., a metal zero layer, of the IC device. In some embodiments, contact regions CR 1 -CR 3  are included in a manufacturing process as part of defining respective contact structures C 1 -C 3  discussed above with respect to  FIGS.  1 A- 2 D . 
     At operation  510 , in some embodiments, an active region is intersected with first, second, and third gate regions, thereby defining a location of an anti-fuse structure between locations of first and second transistors. The first gate region corresponds to the first transistor including adjacent portions of the active region, the third gate region corresponds to the second transistor including adjacent portions of the active region, and the second gate region corresponds to the anti-fuse structure including adjacent portions of the active region between the first and second gate regions and between the second and third gate regions. 
     The first, second, and third gate regions have a spacing corresponding to a gate pitch of a manufacturing process such that the second gate region is offset from each of the first and third gate regions by a distance corresponding to the gate pitch. 
     Intersecting the active region with the first, second, and third gate regions includes extending each of the first, second, and third gate regions to an area outside the active region along a direction perpendicular to a direction along which the active region extends. In various embodiments, intersecting the active region with the first, second, and third gate regions includes extending one or more of the first, second, or third gate regions to intersect one or more active regions in addition to the active region. 
     In some embodiments, intersecting the active region with the first, second, and third gate regions is part of intersecting the active region with a plurality of gate regions that includes one or more gate regions in addition to the first, second, and third gate regions. In some embodiments, the one or more additional gate regions include one or more dummy gate regions. 
     Defining the location of the anti-fuse structure in the active region includes defining a rectangle or other area usable in a manufacturing process for positioning one or more dielectric layers capable of being sustainably altered by a sufficiently strong electric field. 
     Defining the locations of the first and second transistors in the active region includes defining a rectangle or other area usable in a manufacturing process for positioning one or more dielectric layers capable of controlling a channel in the active area corresponding to the active region. Defining the locations of each of the first and second transistors includes each of the first and second transistors being adjacent to the anti-fuse structure. 
     In the non-limiting examples depicted in  FIGS.  6 A and  6 B , intersecting the active region with the first, second, and third gate regions includes intersecting active region AR with respective gate regions G 1 -G 3 . In some embodiments, intersecting the active region with the first, second, and third gate regions includes intersecting active region AR with respective gate regions G 4 -G 6 . 
     At operation  520 , the active region is overlaid with first and second contact regions, the first, second, and third gate regions being between the first and second contact regions. Overlying the active region with the first contact region defines a location of an electrical connection between a portion of the active region included in the first transistor and the first contact region, and overlying the active region with the second contact region defines a location of an electrical connection between the portion of the active region included in the second transistor and the second contact region. 
     In some embodiments, overlying the active region with the first and second contact regions is part of overlying the active region with a plurality of contact regions that includes one or more contact regions in addition to the first and second contact regions, and overlying the active region with the one or more additional contact regions defines one or more additional locations of one or more electrical connections between portions of the active region included in one or more additional transistors and the one or more additional contact regions. 
     In the non-limiting examples depicted in  FIGS.  6 A and  6 B , overlying the active region with the first and second contact regions includes overlying active region AR with respective contact regions CR 1  and CR 2 . In some embodiments, overlying the active region with the first and second contact regions includes overlying active region AR with contact region CR 3 . 
     At operation  530 , in some embodiments, the active region and first and second contact regions are overlaid with a first conductive region. Overlying the active region and first and second contact regions with the first conductive region includes intersecting each of gate regions G 1 -G 3  with the first conductive region. 
     Overlying the first contact region with the first conductive region defines a location of an electrical connection between the first contact region and the first conductive region, and overlying the second contact region with the first conductive region defines a location of an electrical connection between the second contact region and the first conductive region. 
     In some embodiments, the first and second contact regions are included in a plurality of contact regions that includes one or more contact regions in addition to the first and second contact regions, and overlying the active region and first and second contact regions includes overlying one or more contact regions in addition to the first and second contact regions. Overlying the one or more additional contact regions defines one or more locations of electrical connections between the one or more additional contact regions and the first conductive region. 
     In the non-limiting examples depicted in  FIGS.  6 A and  6 B , overlying the active region and the first and second contact regions with the first conductive region includes overlying active region AR and contact regions CR 1  and CR 2  with bit line region BLR. In some embodiments, overlying the active region and the first and second contact regions with the first conductive region includes overlying contact region CR 3  with bit line region BLR. 
     At operation  540 , in some embodiments, the first gate region is overlaid with a first via region, the second gate region is overlaid with a second via region, the third gate region is overlaid with a third via region, and the first and third via regions are overlaid with a second conductive region. In some embodiments, the second via region is overlaid with a third conductive region. 
     Overlying the first gate region with the first via region defines a location of an electrical connection between the first gate region and the first via region, overlying the second gate region with the second via region defines a location of an electrical connection between the second gate region and the second via region, and overlying the third gate region with the third via region defines a location of an electrical connection between the third gate region and the third via region. 
     In some embodiments, overlying the first, second, and third gate regions with respective first, second, and third via regions includes overlying the fourth, fifth, and sixth gate regions with respective fourth, fifth, and sixth via regions, thereby defining locations of electrical connections between the fourth, fifth, and sixth gate regions and the respective fourth, fifth, and sixth via regions. 
     Overlying the first and third via regions with the second conductive region defines locations of electrical connections between the first and second via regions and the second conductive region. In some embodiments, overlying the second via region with the third conductive region defines an electrical connection between the second via region and the third conductive region. 
     In some embodiments, overlying the first and third via regions with the second conductive region includes overlying the fourth and sixth via regions with a fourth conductive region, thereby defining locations of electrical connections between the fourth and sixth via regions and the fourth conductive region. In some embodiments, overlying the second via region with the third conductive region includes overlying the fifth via region with a fifth conductive region, thereby defining an electrical connection between the fifth via region and the fifth conductive region. 
     In the non-limiting examples depicted in  FIGS.  6 A and  6 B , overlying the first, second, and third gate regions with the first, second, and third via regions includes overlying gate regions G 1 -G 3  with respective via regions VR 1 -VR 3 , and overlying the first and third via regions with the second conductive region includes overlying via regions VR 1  and VR 3  with conductive region WLRR 0 . In some embodiments, overlying the second via region with the third conductive region includes overlying via region VR 2  with a third conductive region (not shown). 
     In the non-limiting examples depicted in  FIGS.  6 A and  6 B , in some embodiments, overlying the fourth, fifth, and sixth gate regions with the fourth, fifth, and sixth via regions includes overlying gate regions G 4 -G 6  with respective via regions VR 4 -VR 6 , and overlying the fourth and sixth via regions with the fourth conductive region includes overlying via regions VR 4  and VR 6  with conductive region WLRR 1 . In some embodiments, overlying the fifth via region with the fifth conductive region includes overlying via region VR 5  with a fifth conductive region (not shown). 
     At operation  550 , in some embodiments, the IC layout diagram is stored in a storage device. In various embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in a non-volatile, computer-readable memory or a cell library, e.g., a database, and/or includes storing the IC layout diagram over a network. In some embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram over network  714  of EDA system  700 , discussed below with respect to  FIG.  7   . 
     At operation  560 , in some embodiments, the IC layout diagram is placed in an IC layout diagram of an anti-fuse array. In some embodiments, placing the IC layout diagram in the IC layout diagram of the anti-fuse array includes rotating the IC layout diagram about one or more axes or shifting the IC layout diagram relative to one or more additional IC layout diagrams in one or more directions. 
     At operation  570 , in some embodiments, at least one of one or more semiconductor masks, or at least one component in a layer of a semiconductor IC is fabricated based on the IC layout diagram. Fabricating one or more semiconductor masks or at least one component in a layer of a semiconductor IC is discussed below with respect to  FIG.  8   . 
     At operation  580 , in some embodiments, one or more manufacturing operations are performed based on the IC layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more lithographic exposures based on the IC layout diagram. Performing one or more manufacturing operations, e.g., one or more lithographic exposures, based on the IC layout diagram is discussed below with respect to  FIG.  8   . 
     By executing some or all of the operations of method  500 , an IC layout diagram, e.g., IC layout diagram  600 A or  600 B, is generated in which an anti-fuse cell includes an anti-fuse device positioned between a pair of electrically connected transistors and is thereby configured to have the properties, and thus the benefits, discussed above with respect to IC devices  100  and  200 . Further, compared to approaches in which an anti-fuse cell includes an anti-fuse device positioned between a single selection transistor and a dummy gate region, the IC layout diagram, e.g., IC layout diagram  600 A or  600 B, generated by executing some or all of the operations of method  500  is capable of achieving the referenced benefits without increasing a size of an anti-fuse cell. 
       FIG.  7    is a block diagram of an electronic design automation (EDA) system  700 , in accordance with some embodiments. 
     In some embodiments, EDA system  700  includes an APR system. Methods described herein of designing layout diagrams representing wire routing arrangements, in accordance with one or more embodiments, are implementable, for example, using EDA system  700 , in accordance with some embodiments. 
     In some embodiments, EDA system  700  is a general purpose computing device including a processor  702  and a non-transitory, computer-readable storage medium  704 . Computer-readable storage medium  704 , amongst other things, is encoded with, i.e., stores, computer program code  706 , i.e., a set of executable instructions. Execution of instructions  706  by processor  702  represents (at least in part) an EDA tool which implements a portion or all of, e.g., method  500  described above with respect to  FIG.  5    (hereinafter, the noted processes and/or methods). 
     Processor  702  is electrically coupled to computer-readable storage medium  704  via a bus  708 . Processor  702  is also electrically coupled to an I/O interface  710  by bus  708 . A network interface  712  is also electrically connected to processor  702  via bus  708 . Network interface  712  is connected to a network  714 , so that processor  702  and computer-readable storage medium  704  are capable of connecting to external elements via network  714 . Processor  702  is configured to execute computer program code  706  encoded in computer-readable storage medium  704  in order to cause system  700  to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor  702  is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. 
     In one or more embodiments, computer-readable storage medium  704  is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium  704  includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium  704  includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD). 
     In one or more embodiments, computer-readable storage medium  704  stores computer program code  706  configured to cause system  700  (where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, computer-readable storage medium  704  also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, computer-readable storage medium  704  stores library  707  of standard cells including anti-fuse cell IC layout diagrams as disclosed herein, e.g., IC layout diagrams  600 A and/or  600 B discussed above with respect to  FIGS.  6 A and  6 B . 
     EDA system  700  includes I/O interface  710 . I/O interface  710  is coupled to external circuitry. In one or more embodiments, I/O interface  710  includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor  702 . 
     EDA system  700  also includes network interface  712  coupled to processor  702 . Network interface  712  allows system  700  to communicate with network  714 , to which one or more other computer systems are connected. Network interface  712  includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems  700 . 
     System  700  is configured to receive information through I/O interface  710 . The information received through I/O interface  710  includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor  702 . The information is transferred to processor  702  via bus  708 . EDA system  700  is configured to receive information related to a UI through I/O interface  710 . The information is stored in computer-readable medium  704  as user interface (UI)  742 . 
     In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EDA system  700 . In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. 
     In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like. 
       FIG.  8    is a block diagram of IC manufacturing system  800 , and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using manufacturing system  800 . 
     In  FIG.  8   , IC manufacturing system  800  includes entities, such as a design house  820 , a mask house  830 , and an IC manufacturer/fabricator (“fab”)  850 , that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device  860 . The entities in system  800  are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house  820 , mask house  830 , and IC fab  850  is owned by a single larger company. In some embodiments, two or more of design house  820 , mask house  830 , and IC fab  850  coexist in a common facility and use common resources. 
     Design house (or design team)  820  generates an IC design layout diagram  822 . IC design layout diagram  822  includes various geometrical patterns, e.g., an IC layout diagram  600 A or  600 B discussed above with respect to  FIGS.  6 A and  6 B , designed for an IC device  860 , e.g., IC device  100  or  200 , discussed above with respect to  FIGS.  1 A- 2 D . The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device  860  to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram  822  includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house  820  implements a proper design procedure to form IC design layout diagram  822 . The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram  822  is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram  822  can be expressed in a GDSII file format or DFII file format. 
     Mask house  830  includes mask data preparation  832  and mask fabrication  844 . Mask house  830  uses IC design layout diagram  822  to manufacture one or more masks  845  to be used for fabricating the various layers of IC device  860  according to IC design layout diagram  822 . Mask house  830  performs mask data preparation  832 , where IC design layout diagram  822  is translated into a representative data file (“RDF”). Mask data preparation  832  provides the RDF to mask fabrication  844 . Mask fabrication  844  includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)  845  or a semiconductor wafer  853 . The design layout diagram  822  is manipulated by mask data preparation  832  to comply with particular characteristics of the mask writer and/or requirements of IC fab  850 . In  FIG.  8   , mask data preparation  832  and mask fabrication  844  are illustrated as separate elements. In some embodiments, mask data preparation  832  and mask fabrication  844  can be collectively referred to as mask data preparation. 
     In some embodiments, mask data preparation  832  includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram  822 . In some embodiments, mask data preparation  832  includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem. 
     In some embodiments, mask data preparation  832  includes a mask rule checker (MRC) that checks the IC design layout diagram  822  that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram  822  to compensate for limitations during mask fabrication  844 , which may undo part of the modifications performed by OPC in order to meet mask creation rules. 
     In some embodiments, mask data preparation  832  includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab  850  to fabricate IC device  860 . LPC simulates this processing based on IC design layout diagram  822  to create a simulated manufactured device, such as IC device  860 . The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram  822 . 
     It should be understood that the above description of mask data preparation  832  has been simplified for the purposes of clarity. In some embodiments, data preparation  832  includes additional features such as a logic operation (LOP) to modify the IC design layout diagram  822  according to manufacturing rules. Additionally, the processes applied to IC design layout diagram  822  during data preparation  832  may be executed in a variety of different orders. 
     After mask data preparation  832  and during mask fabrication  844 , a mask  845  or a group of masks  845  are fabricated based on the modified IC design layout diagram  822 . In some embodiments, mask fabrication  844  includes performing one or more lithographic exposures based on IC design layout diagram  822 . In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)  845  based on the modified IC design layout diagram  822 . Mask  845  can be formed in various technologies. In some embodiments, mask  845  is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask  845  includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask  845  is formed using a phase shift technology. In a phase shift mask (PSM) version of mask  845 , various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication  844  is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer  853 , in an etching process to form various etching regions in semiconductor wafer  853 , and/or in other suitable processes. 
     IC fab  850  includes wafer fabrication  852 . IC fab  850  is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab  850  is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business. 
     IC fab  850  uses mask(s)  845  fabricated by mask house  830  to fabricate IC device  860 . Thus, IC fab  850  at least indirectly uses IC design layout diagram  822  to fabricate IC device  860 . In some embodiments, semiconductor wafer  853  is fabricated by IC fab  850  using mask(s)  845  to form IC device  860 . In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram  822 . Semiconductor wafer  853  includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer  853  further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). 
     Details regarding an integrated circuit (IC) manufacturing system (e.g., system  800  of  FIG.  8   ), and an IC manufacturing flow associated therewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 20150278429, published Oct. 1, 2015, U.S. Pre-Grant Publication No. 20140040838, published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entireties of each of which are hereby incorporated by reference. 
     In some embodiments, an IC device includes an active area positioned in a substrate, first and second contact structures overlying and electrically connected to the active area, a conductive element overlying and electrically connected to each of the first and second contact structures, an anti-fuse transistor device including a dielectric layer between a gate structure and the active area, a first selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the first contact structure, and a second selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the second contact structure. In some embodiments, the active area extends in a first direction, and the first and second selection transistors are symmetrically configured along the first direction with respect to the anti-fuse transistor device. In some embodiments, the conductive element is a first conductive element extending in a first metal layer of the IC device, and the IC device includes a first via structure overlying and electrically connected to a gate structure of the first selection transistor, a second via structure overlying and electrically connected to a gate structure of the second selection transistor, and a second conductive element adjacent to the first conductive element in the first metal layer, wherein the second conductive element overlies and is electrically connected to each of the first and second via structures. In some embodiments, the IC device includes a third via structure overlying and electrically connected to the gate structure of the anti-fuse transistor device, wherein the third via structure and the second conductive element are positioned on opposite sides of the first conductive element. In some embodiments, the active area includes first through fourth S/D structures, the first contact structure overlies and is electrically connected to the first S/D structure, the second contact structure overlies and is electrically connected to the second S/D structure, the third S/D structure extends between the first selection transistor and the anti-fuse transistor device, and the fourth S/D structure extends between the second selection transistor and the anti-fuse transistor device. In some embodiments, the active area has p-type doping and each of the first through fourth S/D structures has n-type doping. In some embodiments, a current path between the anti-fuse transistor device and the conductive element includes a first component extending in the active area from the anti-fuse transistor device to the first contact structure in a first direction and a second component extending in the active area from the anti-fuse transistor device to the second contact structure in a second direction opposite the first direction. 
     In some embodiments, an IC device includes an active area positioned in a substrate, first through third contact structures overlying and electrically connected to the active area, a conductive element overlying and electrically connected to each of the first through third contact structures, first and second anti-fuse transistor devices, each including a dielectric layer between a corresponding gate structure and the active area, a first selection transistor overlying the active area adjacent to each of the first anti-fuse transistor device and the first contact structure, a second selection transistor overlying the active area adjacent to each of the first anti-fuse transistor device and the second contact structure, a third selection transistor overlying the active area adjacent to each of the second anti-fuse transistor device and the second contact structure, and a fourth selection transistor overlying the active area adjacent to each of the second anti-fuse transistor device and the third contact structure. In some embodiments, the active area extends in a first direction, the first and second selection transistors are symmetrically configured along the first direction with respect to the first anti-fuse transistor device, and the third and fourth selection transistors are symmetrically configured along the first direction with respect to the second anti-fuse transistor device. In some embodiments, the conductive element is a first conductive element extending in a first metal layer of the IC device, and the IC device includes first through fourth via structures overlying and electrically connected to respective gate structures of the first through fourth selection transistors, a second conductive element adjacent to the first conductive element in the first metal layer, wherein the second conductive element overlies and is electrically connected to each of the first and second via structures, and a third conductive element adjacent to the first conductive element in the first metal layer, wherein the third conductive element overlies and is electrically connected to each of the third and fourth via structures. In some embodiments, the second and third conductive elements are aligned along the first direction. In some embodiments, the second and third conductive elements are positioned on opposite sides of the first conductive element. In some embodiments, the active area includes first through seventh S/D structures, the first contact structure overlies and is electrically connected to the first S/D structure, the second contact structure overlies and is electrically connected to the second S/D structure, the third contact structure overlies and is electrically connected to the third S/D structure, the fourth S/D structure extends between the first selection transistor and the first anti-fuse transistor device, the fifth S/D structure extends between the second selection transistor and the first anti-fuse transistor device, the sixth S/D structure extends between the third selection transistor and the second anti-fuse transistor device, and the seventh S/D structure extends between the fourth selection transistor and the second anti-fuse transistor device. In some embodiments, the active area has p-type doping and each of the first through seventh S/D structures has n-type doping. 
     In some embodiments, a method of operating a circuit includes receiving a voltage at a gate of an anti-fuse transistor device overlying an active area positioned in a substrate, receiving a signal at each of a gate of a first selection transistor positioned between the anti-fuse transistor and a first contact structure coupled between the active area and a bit line and a gate of a second selection transistor coupled between the anti-fuse transistor device and a second contact structure coupled between the active area and the bit line, and in response to the signal having a first voltage value, switching on each of the first and second selection transistors. In some embodiments, switching on each of the first and second selection transistors includes applying an electric field to a dielectric layer of the anti-fuse transistor device, the electric field having a symmetry based on the first selection transistor and the second selection transistor. In some embodiments, switching on each of the first and second selection transistors includes coupling the anti-fuse transistor device to a bit line through each of the first and second contact structures. In some embodiments, coupling the anti-fuse transistor device to the bit line through the first contact structure includes generating a first bit line current component flowing in a first direction, and coupling the anti-fuse transistor device to the bit line through the second contact structure includes generating a second bit line current component flowing in a second direction opposite the first direction. In some embodiments, switching on each of the first and second selection transistors is part of performing a write operation on an anti-fuse device array comprising the anti-fuse transistor device. In some embodiments, switching on each of the first and second selection transistors is part of performing a read operation on an anti-fuse device array comprising the anti-fuse transistor device. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.