Patent Publication Number: US-9892787-B2

Title: Multi-time programmable non-volatile memory cell and associated circuits

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of CN application No. 201610207913.X, filed on Apr. 5, 2016, and incorporated herein by reference. 
     TECHNICAL FIELD 
     The present invention relates to electrical circuit, more particularly but not exclusively relates to multi-time programmable memory cell and associated circuits. 
     BACKGROUND 
     Multi-time programmable (MTP) storage devices are widely used as non-volatile memory (NVM) when designing integrated circuits recently for an advantage of multi-time programming within endurance limits. One of the multi-time programmable storage devices has a Floating gate Avalanche-injection Metal-Oxide Semiconductor (FAMOS) MTP memory circuit, which usually has a current-sense amplifier configured to compare a memory current signal with a reference current signal. Stored information of the FAMOS MTP memory circuit will be read out according to a comparison result of the current-sense amplifier. However, an additional reference circuit is needed to generate the reference current signal, and the additional reference circuit may mismatch with the FAMOS MTP memory circuit and may induce instability. 
     Therefore, a MTP memory circuit with higher stability, less silicon area, and lower power dissipated is needed. 
     SUMMARY 
     It is one of the objects of the present invention to provide a multi-time programmable memory cell, and associated circuits employing the multi-time programmable memory cell. 
     One embodiment of the present invention discloses a multi-time programmable cell, comprising: a differential multi-time programmable memory cell, comprising a memory module configured to store data, the differential multi-time programmable memory cell is configured to erase the data stored in the memory module via an erase operation, write the data into the memory module via a write operation, read out the data stored in the memory module and provide a first balance signal and a second balance signal accordingly via a read operation, and load a first load control signal and a second load control signal and provide the first balance signal and the second balance signal via a load operation; and a second-level latch cell, coupled to the differential multi-time programmable memory cell to receive the first balance signal and the second balance signal, and the second-level latch cell is configured to provide an output signal based on the first balance signal, the second balance signal, a first latch control signal and a second latch control signal; wherein the second-level latch cell is configured to generate a sampled signal via sampling the first balance signal and the second balance signal, and the second-level latch cell is configured to provide the output signal based on the sampled signal; and wherein the sampled signal is being stored during when the first latch control signal is at a first state and the second latch control signal is at a second state, and the sampled signal is being held during when the first latch control signal is in the second state and the second latch control signal is in the first state. 
     Another embodiment of the present invention discloses a multi-time programmable cell, comprising: a memory module, configured to store a data with a multi-time programmable capability; an erase module, configured to erase the data stored in the memory module based on an erase control signal; a write module, configured to store a first programming signal and a second programming signal into the memory module in accordance with a first programming control signal and a second programming control signal, wherein the first programming control signal and the second programming control signal are logically complementary, and the first programming signal and the second programming signal are logically complementary; a read module, configured to read out the data stored in the memory module and provide a first read signal and a second read signal accordingly based on a read control signal, wherein the first read signal and the second read signal are logically complementary; a load module, configured to provide a first load signal and a second load signal according to a first load control signal and a second load control signal, wherein the first load control signal and the second load control signal are logically complementary, and the first load signal and the second load signal are logically complementary; a latch module, configured to provide a first balance signal and a second balance signal in response in part to the first read signal and the second read signal, and in response in part to the first load signal and the second load signal; a balance module, configured to sample the first balance signal and the second balance signal and provide a sampled signal in response to the first balance signal and the second balance signal, wherein the sampled signal is being stored during when a first latch control signal is at a first state and the second latch control signal is at a second state, and wherein the sampled signal is being held during when the first latch control signal is in the second state and the second latch control signal is in the first state; and a single-ended output module, configured to provide an output signal in response to the sampled signal. 
     Yet another embodiment of the present invention discloses a circuit configured to achieve a function of a D flip-flop, comprising: a logic array, configured to receive a data signal and a clock signal, provide a first load control signal and a second load control signal based on the data signal, and provide a first latch control signal and a second latch control signal based on the clock signal; a differential multi-time programmable memory cell, coupled to the logic array to receive the first load control signal and the second load control signal, the differential multi-time programmable memory cell is configured to provide a first balance signal and a second balance signal in response to the first load control signal and the second load control signal via a load operation; and a second-level latch cell, coupled to the differential multi-time programmable memory cell to receive the first balance signal and the second balance signal, coupled to the logic array to receive the first latch control signal and the second latch control signal, configured to generate a sampled signal in response to the first balance signal and the second balance signal, and configured to provide an output signal in response to the sampled signal; wherein the sampled signal is being stored during when the first latch control signal is at a first state and the second latch control signal is at a second state; and wherein the sampled signal is being held during when the first latch control signal is in the second state and the first latch control signal is in the first state. 
     Yet another embodiment of the present invention discloses a circuit configured to achieve a function of a register, comprising: a sequence logic unit, configured to receive an address signal, a first signal comprising one of a clock signal and a request signal, and a reading-and-writing enable signal, and is configured to provide an enable control signal, a first latch control signal, a second latch control signal and a load enable signal based on the address signal, the first signal, and the reading-and-writing enable signal; a load logic unit, coupled to the sequence logic unit to receive the load enable signal and configured to receive a data signal, the load logic unit is configured to provide a first load control signal and a second load control signal based on the load enable signal and the data signal; a write logic unit, configured to receive a write signal and an output signal, and provide a first programming control signal and a second programming control signal based on the write signal and the output signal; a differential multi-time programmable memory cell, coupled to the sequence logic unit to receive the enable control signal, coupled to the load logic unit to receive the first load control signal and the second load control signal, coupled to the write logic unit to receive the first programming control signal and the second programming control signal, and the differential multi-time programmable memory cell is configured to provide a first balance signal and a second balance signal based on the enable control signal, the first load control signal, the second load control signal, the first programming control signal, and the second programming signal, wherein the differential multi-time programmable memory cell is capable to erase a stored data via an erase operation, store the data in response to the first programming control signal and the second programming control signal via a write operation, read out the stored data and provide the first balance signal and the second balance signal accordingly via a read operation, and load the first load control signal and the second load control signal and provide the first balance signal and the second balance signal accordingly via a load operation; and a second-level latch cell, coupled to the differential multi-time programmable memory cell to receive the first balance signal and the second balance signal, coupled to the sequence logic unit to receive the first latch control signal and the second latch control signal, configured to generate a sampled signal in response to the first balance signal and the second balance signal, and configured to provide the output signal based on the sampled signal; wherein the sampled signal is being stored during when the first latch control signal is at a first state and the second latch control signal is at a second state; and wherein the sampled signal is being held during when the first latch control signal is in the second state and the first latch control signal is in the first state. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments are described with reference to the following drawings. 
         FIG. 1  illustrates a block diagram of a differential multi-time programmable non-volatile memory cell  100  according to an embodiment of the present invention. 
         FIG. 2  schematically illustrates a multi-time programmable memory cell  200  according to an embodiment of the present invention. 
         FIG. 3  schematically illustrates a multi-time programmable memory cell  300  according to an embodiment of the present invention. 
         FIG. 4  schematically illustrates a multi-time programmable memory cell  400  according to an embodiment of the present invention. 
         FIG. 5  illustrates a block diagram of a multi-time programmable non-volatile memory cell  500  according to another embodiment of the present invention. 
         FIG. 6  schematically illustrates a circuit  600  employing multi-time programmable non-volatile memory cell  500  according to an embodiment of the present invention. 
         FIG. 7  schematically illustrates a circuit  700  employing multi-time programmable non-volatile memory cell  500  according to an embodiment of the present invention. 
         FIG. 8  illustrates a timing diagram of circuit  700  according to an embodiment of the present invention. 
         FIG. 9  schematically illustrates multi-time programmable non-volatile memory cell  500  according to an embodiment of the present invention. 
         FIG. 10  schematically illustrates multi-time programmable non-volatile memory cell  500  according to another embodiment of the present invention. 
     
    
    
     The use of the same reference label in different drawings indicates the same or like components. 
     DETAILED DESCRIPTION 
     In the present application, numerous specific details are provided, such as examples of circuits, components, and methods, to provide a thorough understanding of embodiments of the invention. These embodiments are exemplary, not to confine the scope of the invention. Persons of ordinary skill in the art will recognize, however, that the invention can be practiced without one or more of the specific details. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention. Some phrases are used in some exemplary embodiments. However, the usage of these phrases is not confined to these embodiments. 
     Several embodiments of the present invention are described below with reference to a multi-time programmable non-volatile memory cell and associated circuits employing the multi-time programmable non-volatile memory cell. 
       FIG. 1  illustrates a block diagram of a differential multi-time programmable non-volatile memory cell  100  with one-bit according to an embodiment of the present invention. Referring to  FIG. 1 , differential multi-time programmable non-volatile memory cell  100  comprises a memory module  101 , a write module  102 , a read module  103 , and an erase module  104 . Memory module  101  which can be multi-time programmed has a terminal  11 , a terminal  12 , and a terminal  13 . Terminal  11  of memory module  101  is coupled to erase module  104 , and memory module  101  performs an erase operation under the control of erase module  104 . Terminal  12  and terminal  13  of memory module  101  are coupled to both write module  102  and read module  103 , and memory module  101  performs a write operation under the control of write module  102  and performs a read operation under the control of read module  103 . 
     Write module  102  is configured to write data into memory module  101  in accordance with a programming control signal PROG_HI and a programming control signal PROG_LO. In one embodiment, write module  102  comprises a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first input terminal of write module  102  is configured to receive programming control signal PROG_HI, the second input terminal of write module  102  is configured to receive programming control signal PROG_LO, the first output terminal of write module  102  is configured to provide a programming signal W_H to terminal  12  of memory module  101 , and the second output terminal of write module  102  is configured to provide a programming signal W_L to terminal  13  of memory module  101 . In one embodiment, programming control signal PROG_H and programming control signal PROG_L are differential signals, namely logical complementary signals. For example, programming control signal PROG_H is at logic high, programming control signal PROG_L is at logic low, and vice versa. In one embodiment, programming signal W_H and programming signal W_L are differential signals, namely logical complementary signals. For example, programming signal W_H is at logic high, programming signal W_L is at logic low, and vice versa. 
     Read module  103  is configured to read out the data stored in memory module  101  in accordance with a read control signal READ. In one embodiment, read module  103  comprises a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. The first input terminal and the second input terminal of read module  103  are respectively coupled to terminal  12  and terminal  13  of memory module  101  to receive a differential signal from memory module  101 , the third input terminal of read module  103  is configured to receive read control signal READ, and the first output terminal of read module  103  is configured to provide read signal R_H and the second output terminal of read module  103  is configured to provide read signal R_L based on the data stored in memory module  101 . In one embodiment, read signal R_H and read signal R_L are differential signals, namely logical complementary signals. For example, read signal R_H is at logic high, read signal R_L is at logic low, and vice versa. 
     Erase module  104  is configured to erase the data stored in memory module  101  in accordance with an erase control signal ERASE. In one embodiment, erase module  104  comprises an input terminal and an output terminal, wherein the input terminal of erase module  104  is configured to receive the erase control signal ERASE, and the output terminal of erase module  104  is coupled to terminal  11  of memory module  101  to erase the data stored in memory module  101  based on the erase control signal ERASE. 
     In one embodiment, during the erase operation, write module  102  and read module  103  are non-activated, namely the write operation and the read operation are prohibited. And once erase control signal ERASE is activated, e.g., at logic high, the data stored in memory module  101  is erased. In one embodiment, during the write operation, erase control signal ERASE and read control signal READ are non-activated, namely read module  103  and erase module  104  are non-activated, and the read operation and the erase operation are prohibited. Once programming control signal PROG_H and programming control signal PROG_L are activated, the data is stored into memory module  101  via write module  102  in accordance with programming control signal PROG_H and programming control signal PROG_L. In one embodiment, during the read operation, erase control signal ERASE, programming control signal PROG_H and programming control signal PROG_L are non-activated, namely write module  102  and erase module  104  are non-activated, and the write operation and the erase operation are prohibited. Once read control signal READ is activated, read module  103  is configured to read out the data stored in memory module  101 . 
     In one embodiment, differential multi-time programmable non-volatile memory cell  100  further comprises a latch module  105 , a load module  106 , an output module  107 , and an enable module  108 . 
     In accordance with a load control signal LOAD_HI and a load control signal LOAD_LO, load module  106  is configured to provide data to latch module  105 . In one embodiment, load module  106  has a first input terminal configured to receive load control signal LOAD_HI, a second input terminal configured to receive load control signal LOAD_LO, a first output terminal configured to provide a load signal L_H, and a second output terminal configured to provide a load signal L_L. In one embodiment, load control signal LOAD_HI and load control signal LOAD_LO are differential signals, namely logical complementary signals. For example, load control signal LOAD_HI is at logic high, load control signal LOAD_LO is at logic low, and vice versa. In one embodiment, load signal L_H and load signal L_L are differential signals, namely logical complementary signals. For example, load signal L_H is at logic high, load signal L_L is at logic low, and vice versa. 
     Latch module  105  is configured to provide a latch signal SideX and a latch signal SideY either in accordance with read signal R_H and read signal R_L or in accordance with load signal L_H and load signal L_L. In one embodiment, latch module  105  comprises a first input terminal, a second input terminal, a first output terminal configured to provide latch signal SideX, and a second output terminal configured to provide latch signal SideY, wherein the first input terminal of latch module  105  is configured to receive read signal R_H from read module  103  or receive load signal L_H from load module  106 , and the second input terminal of latch module  105  is configured to receive read signal R_L from read module  103  or receive load signal L_L from load module  106 . In one embodiment, latch signal SideX and latch signal SideY are differential signals, namely logical complementary signals. For example, latch signal SideX is at logic high, latch signal SideY is at logic low, and vice versa. In one embodiment, when read signal READ is activated and load control signals LOAD_HI and LOAD_LO are non-activated, the data stored in memory module  101  is read out to latch module  105  via read module  103 . In another embodiment, when load control signals LOAD_HI and LOAD_LO are activated and read signal READ is non-activated, data is loaded to latch module  105  to provide latch signals SideX and SideY via load module  106  in accordance with load control signals LOAD_HI and LOAD_LO. 
     Enable module  108  is configured to set a default state for an output signal OUT_HI and an output signal OUT_LO. In one embodiment, enable module  108  comprises an input terminal configured to receive an enable control signal ENI, a first output terminal configured to provide an enable signal E_H, and a second output terminal configured to provide an enable signal E_L. 
     Output module  107  is configured to provide output signal OUT_HI and output signal OUT_LO either in accordance with latch signal SideX and latch signal SideY, or in accordance with enable signal E_H and enable signal E_L. In one embodiment, output module  107  comprises a first input terminal, a second input terminal, a first output terminal configured to provide output signal OUT_HI, and a second output terminal configured to provide output signal OUT_LO, wherein the first input terminal of output module  107  is coupled to latch module  105  and enable module  108  to receive either latch signal SideX or enable signal E_H, and the second input terminal of output module  107  is coupled to latch module  105  and enable module  108  to receive either latch signal SideY or enable signal E_L. 
     In one embodiment, when differential multi-time programmable non-volatile memory cell  100  is powered up, a reset operation is executed to set output signals OUT_HI and OUT_LO the default state (e.g., OUT_HI=OUT_LO=“1”) before any other operation by asserting enable control signal ENI, while de-asserting load control signals LOAD_HI and LOAD_LO, read control signal READ, and programming control signals PROG_HI and PROG_LO, for one example, ENI=“1”, LOAD_HI=“0”, LOAD_LO=“0”, READ=“0”, PROG_HI=“0”, and PRGO_LO=“0”. 
     In one embodiment, the load operation is executed when enable control signal ENI is inactivated and followed by load control signal LOAD_HI and load control signal LOAD_LO being activated. Load module  106  is operated to provide load signal L_H and load signal L_L to latch module  105 , and output module  107  is configured to provide output signal OUT_HI and output signal OUT_LO in accordance with load signal L_H and load signal L_L. 
     In one embodiment, memory module  101  is initially unprogrammed. The write operation is executed when programming control signal PROG_HI and programming control signal PROG_LO are activated and when read control signal READ, load control signal LOAD_HI and load control signal LOAD_LO are non-activated, memory module  101  is programmed in accordance with programming signal W_H and programming signal W_L. In one embodiment, the erase operation is executed before the write operation to erase the data stored in memory module  101  and to resume memory module  101  initially unprogrammed. 
     In one embodiment, the read operation is executed when read control signal READ is activated and when load control signal LOAD_HI, load control signal LOAD_LO, programming control signal PROG_HI, and programming control signal PROG_LO are non-activated, the data stored in memory module  101  is read out to latch module  105 , and then output signal OUT_HI and output signal OUT_LO are provided accordingly via output module  107 . 
       FIG. 2  schematically illustrates a multi-time programmable memory cell  200  according to an embodiment of the present invention. 
     In one embodiment, memory module  101  has a differential structure comprising a floating gate avalanche-injection metal-oxide semiconductor (FAMOS) MPF 1  and a FAMOS MPF 2 . FAMOS MPF 1  and FAMOS MPF 2  respectively have a source, a drain and a floating gate. The source of FAMOS MPF 1  and the source of FAMOS MPF 2  are coupled together to receive a supply voltage VCC, the drain of FAMOS MPF 1  is utilized as terminal  12  of memory module  101 , the drain of FAMOS MPF 2  is utilized as terminal  13  of memory module  101 . The floating gate of FAMOS MPF 1  is coupled to one terminal of an erase capacitor C 1 , the floating gate of FAMOS MPF 2  is coupled to one terminal of an erase capacitor C 2 , the other terminal of erase capacitor C 1  and the other terminal of erase capacitor C 2  are coupled together as terminal  11  of memory module  101 . In the embodiment shown in  FIG. 2 , FAMOS MPF 1  and FAMOS MPF 2  are P type for illustrative purposes. However, one of ordinary skill in the art to which the invention pertains should understand that FAMOS MPF 1  and FAMOS MPF 2  may be substituted by N type switches. 
     In one embodiment, terminal  11  of memory module  101  receives an erase voltage VCG, and the erase operation is executed by controlling erase voltage VCG. For example, when erase control signal ERASE is activated, erase voltage VCG is controlled to erase the data stored in the memory module  101  via enlarging a voltage difference between supply voltage VCC and erase voltage VCG, for example the voltage difference between supply voltage VCC and erase voltage VCG equals tripled supply voltage VCC. 
     In one embodiment, write module  102  has a differential structure comprising an N-type metal oxide semiconductor field effect transistor (NMOS) MN 1  and an NMOS MN 2 . Both NMOS MN 1  and NMOS MN 2  respectively have a drain, a source and a gate. The source of NMOS MN 1  and the source of NMOS MN 2  are coupled to a logic ground GND, the drain of NMOS MN 1  utilized as the first output terminal of write module  102  is coupled to the drain of FAMOS MPF 1  to provide programming signal W_H, the drain of NMOS MN 2  utilized as the second output terminal of write module  102  is coupled to the drain of FAMOS MPF 2  to provide programming signal W_L, the gate of NMOS MN 1  utilized as the first input terminal of write module  102  is configured to receive programming control signal PROG_HI, and the gate of NMOS MN 2  utilized as the second input terminal of write module  102  is configured to receive programming control signal PROG_LO. 
     In one embodiment, read module  103  has a differential structure comprising a P-type metal oxide semiconductor field effect transistor (PMOS) MP 3  and a PMOS MP 4 . Both PMOS MP 3  and PMOS MP 4  respectively have a source, a drain and a gate. The source of PMOS MP 3  utilized as the first input terminal of read module  103  is coupled to the drain of FAMOS MPF 1 , the source of PMOS MP 4  utilized as the second input terminal of read module  103  is coupled to the drain of FAMOS MPF 2 , the gate of PMOS MP 3  and the gate of PMOS MP 4  are coupled together to receive read control signal READ, the drain of PMOS MP 3  utilized as the first output terminal of read module  103  is configured to provide read signal R_H, and the drain of PMOS MP 4  utilized as the second output terminal of read module  103  is configured to provide read signal R_L. 
     In one embodiment, load module  106  has a differential structure comprising a PMOS MP 7  and a PMOS MP 8 . Both PMOS MP 7  and PMOS MP 8  respectively have a drain, a source and a gate. The drain of PMOS MP 7  utilized as the first output terminal of load module  106  is coupled to the drain of PMOS MP 3 , the drain of PMOS MP 8  utilized as the second output terminal of load module  106  is coupled to the drain of PMOS MP 4 . The source of PMOS MP 7  and the source of PMOS MP 8  are coupled together to receive supply voltage VCC, the gate of PMOS MP 7  utilized as the first input terminal of load module  106  is configured to receive load control signal LOAD_HI, and the gate of PMOS MP 8  utilized as the second input terminal of load module  106  is configured to receive load control signal LOAD_LO. 
     In one embodiment, latch module  105  is configured to latch load signal L_H and load signal L_L provided by load module  106 , and is configured to latch read signal R_H and read signal R_L provided by read module  103 . In one embodiment, latch module  105  comprises a PMOS MP 5 , a PMOS MP 6 , an NMOS MN 3  and an NMOS MN 4 . PMOS MP 5 , PMOS MP 6 , NMOS MN 3  and NMOS MN 4  respectively have a drain, a source and a gate. The source of PMOS MP 5  utilized as the first input terminal of latch module  105  is coupled to the drain of PMOS MP 3  and the drain of PMOS MP 7  to receive read signal R_H and/or load signal L_H, the source of PMOS MP 6  utilized as the second input terminal of latch module  105  is coupled to the drain of PMOS MP 4  and the drain of PMOS MP 8  to receive read signal R_L and/or load signal L_L. The gate of PMOS MP 5 , the gate of NMOS MN 3 , the drain of PMOS MP 6  and the drain of NMOS MN 4  are coupled together as the first output terminal of latch module  105  to provide latch signal SideX. The gate of PMOS MP 6 , the gate of NMOS MN 4 , the drain of PMOS MP 5 , and the drain of NMOS MN 3  are coupled together as the second output terminal of latch module  105  to provide latch signal SideY. And the source of NMOS MN 3  and the source of NMOS MN 4  are coupled to logic ground GND. 
     In one embodiment, enable module  108  has a differential structure comprising an NMOS MN 5  and an NMOS MN 6 , both NMOS MN 5  and NMOS MN 6  respectively have a drain, a source and a gate. The drain of NMOS MN 6  utilized as the first output terminal of enable module  108  is configured to provide enable signal E_H, the drain of NMOS MN 5  utilized as the second output terminal of enable module  108  is configured to provide enable signal E_L, the source of NMOS MN 5  and the source of NMOS MN 6  are coupled to logic ground GND, the gate of NMOS MN 5  and the gate of NMOS MN 6  are coupled together as the input terminal of enable module  108  to receive enable control signal ENI. 
     In one embodiment, output module  107  comprises a first buffer comprising a PMOS MP 10  and an NMOS MN 7 , a second buffer comprising a PMOS MP 11  and an NMOS MN 8 . PMOS MP 10 , PMOS MP 11 , NMOS MN 7  and NMOS MN 8  respectively have a drain, a source and a gate. The source of PMOS MP 11  and the source of PMOS MP 10  are coupled to supply voltage VCC, the source of NMOS MN 8  and the source of NMOS MN 7  are coupled to logic ground GND, the gate of PMOS MP 10  and the gate of NMOS MN 7  coupled together as the first input terminal of output module  107  are coupled to latch module  105  and/or enable module  108  to receive latch signal SideX and/or enable signal E_H, the gate of PMOS MP 11  and the gate of NMOS MN 8  coupled together as the second input terminal of output module  107  are coupled to latch module  105  and/or enable module  108  to receive latch signal SideY and/or enable signal E_L, the drain of PMOS MP 10  and the drain of NMOS MN 7  coupled together as the first output terminal of output module  107  are configured to provide output signal OUT_HI, and the drain of PMOS MP 11  and the drain of NMOS MN 8  coupled together as the second output terminal of output module  107  are configured to provide output signal OUT_LO. 
     In one embodiment, the reset operation is executed firstly when multi-time programmable memory cell  200  is powered up. In the embodiment shown in  FIG. 2 , the reset operation is executed when enable control signal ENI is activated, e.g., at logic high, NMOS MN 5  and NMOS MN 6  are turned ON, enable signal E_H and enable signal E_L are at logic low. While load control signal LOAD_HI, load control signal LOAD_LO, and read control signal READ are at logic high to maintain non-activated, and programming control signal PROG_HI and programming control signal PROG_LO are at logic low to maintain non-activated. PMOS MP 10  is turned ON and NMOS MN 7  is turned OFF in response to low logical enable signal E_H and low logical enable signal E_L, and output signal OUT_HI is set at logic high accordingly. PMOS MP 11  is turned ON and NMOS MN 8  is turned OFF in response to low logical enable signal E_H and low logical enable signal E_L, and output signal OUT_LO is set at logic high accordingly. In another embodiment, output signal OUT_HI and output signal OUT_LO may be set at logic low by the reset operation. 
     In one embodiment, load control signal LOAD_HI being at logic low and load control signal LOAD_LO being at logic high are activated to execute the load operation, PMOS MP 7  is turned ON, PMOS MP 8  is turned OFF, latch module  105  receives high logical load signal L_H and low logical load signal L_L, and then provides low logical latch signal SideX and high logical latch signal SideY. Accordingly, output signal OUT_HI is at logic high and output signal OUT_LO is at logic low. In another embodiment, load control signal LOAD_HI being at logic high and load control signal LOAD_LO being at logic low are activated to execute the load operation, PMOS MP 7  is turned OFF, PMOS MP 8  is turned ON, latch module  105  receives low logical load signal L_H and high logical load signal L_L, and then provides high logical latch signal SideX and low logical latch signal SideY. Accordingly, output signal OUT_HI is at logic low and output signal OUT_LO is at logic high. 
     In one embodiment, during the write operation, read control signal READ, load control signal LOAD_HI and load control signal LOAD_LO are respectively at logic high to be non-activated. In one embodiment, programming control signal PROG_HI being at logic high and programming control signal PROG_LO being at logic low are activated to execute the write operation, FAMOS MPF 1  and FAMOS MPF 2  are programmed via write module  102 , that is NMOS MN 1  is turned ON to program FAMOS MPF 1  at high logic state, and NMOS MN 2  is turned OFF to program FAMOS MPF 2  at low logic state. In another embodiment, programming control signal PROG_HI being at logic low and programming control signal PROG_LO being at logic high are activated to execute the write operation, FAMOS MPF 1  and FAMOS MPF 2  are programmed via write module  102 , that is NMOS MN 1  is turned OFF to program FAMOS MPF 1  at low logic state, and NMOS MN 2  is turned ON to program FAMOS MPF 2  at high logic state. 
     In one embodiment, during the read operation, programming control signal PROG_HI and programming control signal PROG_LO are non-activated, e.g., at logic low, to deactivate write module  102 , and both NMOS MN 1  and NMOS MN 2  are turned OFF. Load control signal LOAD_HI and load control signal LOAD_LO are non-activated, e.g., at logic high, to deactivate load module  106 , and both PMOS MP 7  and PMOS MP 8  are turned OFF. When read control signal READ is activated, read module  103  reads out the state of FAMOS MPF 1  and provides read signal R_H accordingly, and reads out the state of FAMOS MPF 2  and provides read signal R_L accordingly. In one embodiment, read control signal READ is an analog signal, and read control signal READ being activated comprises being less than supply voltage VCC to turn ON PMOS MP 3  and PMOS MP 4 . For example, FAMOS MPF 1  was programmed at the state “1”, FAMOS MPF 2  was programmed at the state “0”, and when read control signal READ is activated, read signal R_H is at logic high and read signal R_L is at logic low, latch module  105  provides latch signal SideX at logic low and latch signal SideY at logic high, thus output signal OUT_HI becomes at logic high and output signal OUT_LO becomes at logic low accordingly. 
       FIG. 3  schematically illustrates a multi-time programmable memory cell  300  according to an embodiment of the present invention. Multi-time programmable memory cell  300  is same as multi-time programmable memory cell  200 , excepting that multi-time programmable memory cell  300  does not include load module  106 . 
       FIG. 4  schematically illustrates a multi-time programmable memory cell  400  according to an embodiment of the present invention. Multi-time programmable memory cell  400  has different latch module  405  compared with multi-time programmable memory cell  200 . Latch module  405  is configured to latch load signal L_H and load signal L_L provided by load module  106 . In one embodiment, latch module  406  comprises NMOS MN 3  and NMOS MN 4 . The drain of NMOS MN 3  and the gate of NMOS MN 4  utilized as a first input terminal of latch module  405  are coupled to the drain of PMOS MP 3  and the drain of PMOS MP 7  to receive read signal R_H and/or load signal L_H, while the drain of NMOS MN 3  and the gate of NMOS MN 4  are also utilized as a second output terminal of latch module  405  to provide latch signal SideY. The drain of NMOS MN 4  and the gate of NMOS MN 3  utilized as a second input terminal of latch module  405  are coupled to the drain of PMOS MP 4  and the drain of PMOS MP 8  to receive read signal R_L and/or load signal L_L, while the drain of NMOS MN 4  and the gate of NMOS MN 3  are also utilized as a first output terminal of latch module  405  to provide latch signal SideX. The source of NMOS MN 3  and the source of NMOS MN 4  are coupled to logic ground GND. 
       FIG. 5  illustrates a block diagram of a multi-time programmable non-volatile memory cell  500  with one-bit according to another embodiment of the present invention. Multi-time programmable non-volatile memory cell  500  comprises a differential MTP cell  801  and a second-level latch cell  802 , wherein differential MTP cell  801  comprises memory module  101 , write module  102 , read module  103 , erase module  104 , and latch module  105 , and wherein second level latch cell  802  comprises a balance module  501 , a sample control module  502 , a hold control module  503 , a default setting module  504 , and a single-ended output module  505 . In one embodiment, differential MTP cell  801  is configured to erase the data stored in memory module  101  via the erase operation, to program memory module  101 , i.e., write the data into memory module  101  via the write operation, to provide a balance signal B_HI and a balance signal B_LO by reading out the data stored in memory module  101  via the read operation, to provide balance signal B_HI and balance signal B_LO according to load control signal LOAD_HI and load control signal LOAD_LO via the load operation. In one embodiment, second-level latch cell  802  is configured to provide output signal OUT based on balance signal B_HI and balance signal B_LO under control of a latch control signal LAT_S and a latch control signal LAT_SB. In one embodiment, differential MTP cell  801  further comprises load module  106  and/or enable module  108 . Memory module  101 , write module  102 , read module  103 , erase module  104 , latch module  105 , load module  106 , and enable module  108  have been detailed described above. In one embodiment, multi-time programmable non-volatile memory cell  500  may be utilized as a D flip-flop. 
     In the embodiment shown in  FIG. 5 , differential MTP cell  801  is configured to provide balance signal B_LO according to latch signal SideX or enable signal E_H, and provide balance signal B_HI according to latch signal SideY or enable signal E_L. In one embodiment, balance module  501  is configured to provide sampled signal SEN via sampling balance signal B_HI and balance signal B_LO, and single-ended output module  505  is configured to provide output signal OUT according to sampled signal SEN. In one embodiment, sampled signal SEN is being stored when latch control signal LAT_S is at a first state and latch control signal LAT_SB is at a second state; and sampled signal SEN is being held when latch control signal LAT_S is in the second state and latch control signal LAT_SB is in the first state. 
     Balance module  501  is configured to balance differential output load of balance signal B_HI and balance signal B_LO for ensuring correctness of output signal OUT. In one embodiment, balance module  501  has a first input terminal coupled to latch module  105  and/or enable module  108  to receive balance signal B_HI, a second input terminal coupled to latch module  105  and/or enable module  108  to receive balance signal B_LO, a third input terminal configured to receive a sample control signal S_H, a fourth input terminal configured to receive a sample control signal S_L, and an output terminal configured to provide sampled signal SEN according to balance signal B_HI and balance signal B_LO under control of sample control signal S_H and sample control signal S_L. 
     Sample control module  502  controls balance module  501  to sample balance signal B_HI and balance signal B_LO in accordance with latch control signal LAT_S and latch control signal LAT_SB. In one embodiment, sample control module  502  has a first input terminal configured to receive latch control signal LAT_S, a second input terminal configured to receive latch control signal LAT_SB, a first output terminal configured to provide sample control signal S_H, and a second output terminal configured to provide sample control signal S_L. In one embodiment, sampled signal SEN is being stored under control of sample control module  502 . 
     Single-ended output module  505  is configured to provide output signal OUT based on sampled signal SEN. In one embodiment, single-ended output module  505  has a first input terminal coupled to the output terminal of balance module  501  to receive sampled signal SEN, a second input terminal configured to receive a hold control signal H_H, a third input terminal configured to receive a hold control signal H_L, a fourth input terminal configured to receive a default control signal D_H, a fifth input terminal configured to receive a default control signal D_L, and an output terminal configured to provide output signal OUT. 
     Hold control module  503  is configured to control sampled signal SEN being held based on latch control signal LAT_S and latch control signal LAT_SB, so that single-ended output module  505  is controlled to provide output signal OUT based on sampled signal SEN. In one embodiment, hold control module  503  comprises a first input terminal configured to receive latch control signal LAT_S, a second input terminal configured to receive latch control signal LAT_SB, a first output terminal configured to provide hold control signal H_H, and a second output terminal configured to provide hold control signal H_L. 
     Default setting module  504  is configured to set a default value of output signal OUT in accordance with set signal SET or reset signal RESET. In one embodiment, default setting module  504  has an input terminal configured to receive set signal SET or reset signal RESET, a first output terminal configured to provide default control signal D_H, and a second output terminal configured to provide default control signal D_L. 
     In the embodiment shown in  FIG. 5 , multi-time programmable non-volatile memory cell  500  has storage function and a function of flip and flop. And multi-time programmable non-volatile memory cell  500  has strong competitiveness when used in large array with different output logic design package for erasable, less silicon area, and simple and flexible extended structure. Besides, multi-time programmable non-volatile memory cell  500  has higher stability and reliability since no additional reference current signal is needed. 
     In one embodiment, multi-time programmable non-volatile memory cell  500  is compatible with timing sequence of D flip-flop.  FIG. 6  schematically illustrates a circuit  600  employing multi-time programmable non-volatile memory cell  500  utilized as a D flip-flop according to an embodiment of the present invention. Circuit  600  comprises a logic array  601  and multi-time programmable non-volatile memory cell  500 . 
     Logic array  601  receives a data signal DATA_IN and a clock signal CLOCK, provides load control signal LOAD_HI and load control signal LOAD_LO in accordance with data signal DATA _IN, and provides latch control signal LAT_S and latch control signal LAT_SB in accordance with clock signal CLOCK. 
     Multi-time programmable non-volatile memory cell  500  provides output signal OUT based on load control signal LOAD_HI, load control signal LOAD_LO, latch control signal LAT_S, latch control signal LAT_SB, and set signal SET or reset signal RESET. In one embodiment, when clock signal CLOCK is at a first status, e.g., a rising edge, then latch control signal LAT_S is at logic high, and latch control signal LAT_SB is at logic low, sampled signal SEN is being stored, sample control module  502  controls balance module  501  to achieve a first level latch, that is to provide sampled signal SEN by latching out balance signal B_HI and balance signal B_LO; and when clock signal is at a second status, e.g., a falling edge, then latch control signal LAT_S is at logic low, and latch control signal LAT_SB is at logic high, sample control module  502  controls sampled signal SEN being held, hold control module  503  controls single-ended output module  505  to achieve a second level latch, that is to provide output signal OUT by latching out sampled signal SEN. In one embodiment, when set signal SET or reset signal RESET is activated, defaulting setting module  504  controls single-ended output module  505  to provide output signal OUT equaling the default value, e.g., at logic high or at logic low. 
       FIG. 7  schematically illustrates a circuit  700  employing multi-time programmable non-volatile memory cell  500  utilized as a register according to an embodiment of the present invention. Circuit  700  comprises multi-time programmable non-volatile memory cell  500 , a sequence logic unit  803 , a load logic unit  804 , and a write logic unit  805 , wherein multi-time programmable non-volatile memory cell  500  comprises differential MTP cell  801  and second-level latch cell  802  as shown in  FIG. 5 . 
     Sequence logic unit  803  provides a load enable signal LOAD, enable control signal ENI, latch control signal LAT_S, and latch control signal LAT_SB according to different application. In one embodiment, sequence logic unit  803  comprises a first input terminal configured to receive an address signal ADDRESS, a second input terminal configured to receive clock signal CLOCK or a request signal REQ, a third input terminal configured to receive a reading-and-writing enable signal WR, a first output terminal configured to provide latch control signal LAT_S, a second output terminal configured to provide latch control signal LAT_SB, a third output terminal configured to provide enable control signal ENI, and a fourth output terminal configured to provide load enable signal LOAD. In one embodiment, when circuit  700  is utilized as an asynchronous register, the second input terminal of sequence logic unit  803  is configured to receive request signal REQ. In another embodiment, when circuit  700  is utilized a synchronous register synchronous with clock signal CLOCK, the second input terminal of sequence logic unit  803  is configured to receive clock signal CLOCK. In one embodiment, sequence logic unit  803  further comprises a power terminal coupled to supply voltage VCC, and ground terminal coupled to logic ground GND. 
     Load logic unit  804  provides load control signal LOAD_HI and load control signal LOAD_LO based on load enable signal LOAD and data signal DATA_IN. In one embodiment, load logic unit  804  comprises a first input terminal coupled to sequence logic unit  803  to receive load enable signal LOAD, a second input terminal configured to receive data signal DATA_IN, a first output terminal, and a second output terminal, wherein when load enable signal LOAD is activated, the first output terminal of load logic unit  804  is configured to provide load control signal LOAD_HI and the second output terminal of load logic unit  804  is configured to provide load control signal LOAD_LO in accordance with data signal DATA_IN. In one embodiment, load logic unit  804  further comprises a power terminal coupled to supply voltage VCC, and a ground terminal coupled to logic ground GND. 
     Write logic unit  805  provides programming control signal PROG_HI and programming control signal PROG_LO based on a write signal PROGRAM and output signal OUT. In one embodiment, write logic unit  805  comprises a first input terminal configured to receive write signal PROGRAM, a second input terminal coupled to second-level latch cell  802  to receive output signal OUT, a first output terminal, and a second output terminal, wherein when write signal PROGRAM is activated, the first output terminal of write logic unit  805  is configured to provide programming control signal PROG_HI, and the second output terminal of write logic unit  805  is configured to provide programming control signal PROG_LO based on output signal OUT. In one embodiment, write logic unit  805  further comprises a power terminal coupled to supply voltage VCC, and a ground terminal coupled to logic ground GND. 
     Differential MTP cell  801  is coupled to sequence logic unit  803  to receive enable control signal ENI, coupled to load logic unit  804  to receive load control signal LOAD_HI and load control signal LOAD_LO, coupled to write logic unit  805  to receive programming control signal PROG_HI and programming control signal PROG_LO, and differential MTP cell  801  is configured to provide balance signal B_HI and balance signal B_LO based on enable control signal ENI, load control signal LOAD_HI, load control signal LOAD_LO, programming control signal PROG_HI, and programming control signal PROG_LO. In one embodiment, differential MTP cell  801  further receives read control signal READ, and provides balance signal B_HI and balance signal B_LO further based on read control signal READ. In one embodiment, differential MTP cell  801  further comprises a power terminal coupled to supply voltage VCC, and a ground terminal coupled to logic ground GND. In one embodiment, differential MTP cell  801  comprises memory module  101 , write module  102 , read module  103 , latch module  105  or latch module  405 , load module  106 , and enable module  108  as shown in  FIGS. 1-7 . 
     Second-level latch cell  802  is coupled to differential MTP cell  801  to receive balance signal B_HI and balance signal B_LO, coupled to sequence logic unit  803  to receive latch control signal LAT_S and latch control signal LAT_SB, and is configured to provide output signal OUT based on a set signal SET or a reset signal RESET, balance signal B_HI, balance signal B_LO, latch control signal LAT_S, and latch control signal LAT_SB. In one embodiment, second-level latch cell  802  further comprises a power terminal coupled to supply voltage VCC, and a ground terminal coupled to logic ground GND. 
       FIG. 8  illustrates a timing diagram of circuit  700  according to an embodiment of the present invention. Circuit  700  is compatible with timing sequence of a general register. In  FIG. 8 , waveforms shown from top to below are reset signal RESET, reading-and-writing enable signal WR, address signal ADDRESS, data signal DATA_IN, clock signal CLOCK, erase control signal ERASE, write signal PROGRAM, supply voltage VCC, and erase voltage VCG. As shown in  FIG. 8 , activated write signal PROGRAM (e.g., at logic high) is followed after activated erase signal ERASE (e.g., at logic high), that is the erase operation is executed before the write operation to erase data stored in multi-time programmable non-volatile memory cell  500 . In the embodiment shown in  FIG. 8 , when erase control signal ERASE and write signal PROGRAM are respectively non-activated (e.g., at logic low), both supply voltage VCC and erase voltage VCG equal a standard supply voltage, e.g., 3.3V; when erase control signal ERASE becomes activated (e.g., at logic high), supply voltage VCC increases to twice a programming voltage, erase voltage VCG decreases to negative, thus a difference between supply voltage VCC and erase voltage VCG increases to erase the data stored in multi-time programmable non-volatile memory cell  500 . When erase control signal ERASE becomes non-activated (e.g., at logic low) again, the erase operation is completed. And then write signal PROGRAM becomes activated (e.g., at logic high), both supply voltage VCC and erase voltage VCG equal the programming voltage which is higher than the standard supply voltage, and when write signal PROGRAM becomes non-activated (e.g., at logic low) again, both supply voltage VCC and erase voltage VCG resume to equal the standard supply voltage. 
       FIG. 9  schematically illustrates multi-time programmable non-volatile memory cell  500  according to an embodiment of the present invention. In one embodiment, supply voltage VCC is used to power multi-time programmable non-volatile memory cell  500 , and logic ground GND is used to provide ground reference for multi-time programmable non-volatile memory cell  500 . 
     In one embodiment, balance module  501  comprises a complementary metal-oxide-semiconductor (CMOS) inverter comprising a PMOS MP 100  and an NMOS MN 80 , and a CMOS inverter comprising a PMOS MP 110  and an NMOS MN 9 . PMOS MP 100 , PMOS MP 110 , NMOS MN 80  and NMOS MN 9  have a drain, a source and a gate respectively. The gate of PMOS MP 100  and the gate of NMOS MN 80  are coupled together as the first input terminal of balance module  501  to receive balance signal B_HI, the gate of PMOS MP 110  and the gate of NMOS MN 9  are coupled together as the second input terminal of balance module  501  to receive balance signal B_LO, the source of PMOS MP 100  and the source of PMOS MP 110  are coupled together as the third input terminal of balance module  501  to receive sample control signal S_H, the drain of PMOS MP 100  and the drain of NMOS MN 80  are coupled together as the output terminal of balance module  501 , the drain of PMOS MP 110  is coupled to the drain of NMOS MN 9 , and the source of NMOS MN 80  and the source of NMOS MN 9  are coupled together as the fourth input terminal of balance module  501  to receive sample control signal S_L. 
     In one embodiment, sample control module  502  comprises a PMOS MP 9  and a NMOS MN 70 , both PMOS MP 9  and NMOS MN 70  have a drain, a source and a gate respectively. The source of PMOS MP 9  is coupled to supply voltage VCC, the gate of PMOS MP 9  is utilized as the second input terminal of sample control module  502  to receive latch control signal LAT_SB, the drain of PMOS MP 9  utilized as the first output terminal of sample control module  502  is coupled to the source of PMOS MP 100  and the source of PMOS MP 110  to provide sample control signal S_H, the source of NMOS MN 70  is coupled to logic ground GND, the gate of NMOS MN 70  utilized as the first input terminal of sample control module  502  is configured to receive latch control signal LAT_S, the drain of NMOS MN 70  utilized as the second output terminal of sample control module  502  is coupled to the source of NMOS MN 80  and the source of NMOS MN 9  to provide sample control signal S_L. 
     In one embodiment, when latch control signal LAT_S is at logic high and logic control signal LAT_SB is at logic low, sample control module  502  operates to connect supply voltage VCC to the source of PMOS MP 100  and the source of PMOS MP 110  via turning ON PMOS MP 9 , and sample control module  502  operates to connect the source of NMOS MN 80  and the source of NMOS MN 9  to logic ground GND via turning ON NMOS MN 70 . Sampled signal SEN is being stored in response to balance signal B_HI and balance signal B_LO. In one embodiment, when balance signal B_HI is at logic low and balance signal B_LO is at logic high, PMOS MP 100  is turned ON, NMOS MN 80  is turned OFF, PMOS MP 110  is turned OFF, NMOS MN 9  is turned ON, and sampled signal SEN is being stored at logic high. In another embodiment, when balance signal B_HI is at logic high and balance signal B_LO is at logic low, PMOS MP 100  is turned OFF, NMOS MN 80  is turned ON, PMOS MP 110  is turned ON, NMOS MN 9  is turned OFF, and sampled signal SEN is being stored at logic low. 
     In one embodiment, hold control module  503  comprises a PMOS MP 14  and an NMOS MN 12 , both PMOS MP 14  and NMOS MN 12  have a drain, a source, and a gate respectively. The source of PMOS MP 14  is coupled to supply voltage VCC, the gate of PMOS MP 14  utilized as the first input terminal of hold control module  503  is configured to receive latch control signal LAT_S, the drain of PMOS MP 14  utilized as the first output terminal of hold control module  503  is configured to provide hold control signal H_H, the source of NMOS MN 12  is coupled to the logic ground GND, the gate of NMOS MN 12  utilized as the second input terminal of hold control module  503  is configured to receive latch control signal LAT_SB, and the drain of NMOS MN 12  utilized as the second output terminal of hold control module  503  is configured to provide hold control signal H_L. 
     In one embodiment, when latch control signal LAT_S is at logic low and latch control signal LAT_SB is at logic high, sampled signal SEN is being held, that is sampled signal is not varied with balance signal B_HI and balance signal B_LO, hold control module  503  operates to connect a source of a PMOS MP 15  to supply voltage VCC via turning ON PMOS MP 14 , and hold control module  503  operates to connect a source of an NMOS MN 13  to logic ground GND. Output signal OUT is provided by single-ended output module  505  based on reset signal RESET and/or sampled signal SEN. 
     In one embodiment, default setting module  504  comprises a PMOS MP 12  and an NMOS MN 10 , both PMOS MP 12  and NMOS MN 10  have a drain, a source and a gate respectively. The source of PMOS MP 12  is coupled to supply voltage VCC, the gate of PMOS MP 12  and the gate of NMOS MN 10  utilized as the input terminal of default setting module  504  are coupled to receive reset signal RESET, the drain of PMOS MP 12  utilized as the output terminal of default setting module  504  is configured to provide default control signal D_H, the source of NMOS MN 10  is coupled to logic ground GND, and the drain of NMOS MN 10  utilized as the second output terminal of default setting module  504  is configured to provide default control signal D_L. 
     In one embodiment, when reset signal RESET is at logic high, PMOS MP 12  is turned OFF, NMOS MN 10  is turned ON, default control signal D_L is at logic low, and output signal OUT is reset at logic low. In one embodiment, when reset signal RESET is at logic low, PMOS MP 12  is turned ON, NMOS MN 10  is turned OFF, default control signal D_H is at logic high, a source of a PMOS MP 13  is coupled to supply voltage VCC, and output signal OUT is provided based on sampled signal SEN. For example, when sampled signal SEN is at logic high, NMOS MN 110  is turned ON, PMOS MP 13  is turned OFF, and output signal OUT is at logic low accordingly; and when sampled signal SEN is at logic low, NMOS MN 110  is turned OFF, PMOS MP 13  is turned ON, and output signal OUT is at logic high accordingly. 
     Single-ended output module  505  comprises a CMOS inverter comprising PMOS MP 13  and an NMOS MN 11 , and a CMOS inverter comprising PMOS MP 15  and NMOS MN 13 . PMOS MP 13 , PMOS MP 15 , NMOS MN 13 , and NMOS MN 15  have a drain, a source and a gate respectively. The gate of PMOS MP 13 , the gate of NMOS MN 11 , the drain of PMOS MP 15 , and the drain of NMOS MN 13  are coupled together as the first input terminal of single-ended output module  505  to receive sampled signal SEN, the source of PMOS MP 13  utilized as the fourth input terminal of single-ended output module  505  is coupled to the drain of PMOS MP 12  to receive default control signal D_H, the source of PMOS MP 15  utilized as the second input terminal of single-ended output module  505  is coupled to the drain of PMOS MP 14  to receive hold control signal H_H, the drain of PMOS MP 13 , the drain of NMOS MN 11 , the gate of PMOS MP 15 , and the gate of NMOS MN 13  are coupled together as the fifth input terminal of single-ended output module  505  to receive default control signal D_L from the drain of NMOS MN 10 . The source of NMOS MN 11  is coupled to logic ground GND, the source of NMOS MN 13  utilized as the third input terminal of single-ended output module  505  is coupled to the drain of NMOS MN 12  to receive hold control signal H_L. In the embodiment shown in  FIG. 9 , the drain of PMOS MP 13 , the drain of NMOS MN 11 , the gate of PMOS MP 15 , and the gate of NMOS MN 13  are coupled as the output terminal of single-ended output module  505 . 
       FIG. 10  schematically illustrates multi-time programmable non-volatile memory cell  500  according to another embodiment of the present invention. The embodiment of  FIG. 10  shows different balance module  701  and single-ended output module  705 . In the embodiment shown in  FIG. 9 , default setting module  504  receives activated reset signal RESET to reset output signal OUT at logic low, and in the embodiment shown in  FIG. 10 , default setting module  504  receives activated set signal SET to set output signal OUT at logic high. 
     Balance module  701  comprises PMOS MP 100 , PMOS MP 110 , NMOS MN 80 , and NMOS MN 9 . Different with balance module  501 , in the embodiment shown in  FIG. 10 , the drain of PMOS MP 110  and the drain of NMOS MN 9  are coupled together as an output terminal of balance module  701 . 
     In one embodiment, when latch control signal LAT_S is at logic high and latch control signal LAT_SB is at logic low, \sample control module  502  operates to controlling balance module  701  to sample balance signal B_HI and balance signal B_LO via turning ON PMOS MP 9  and turning ON NMOS MN 70 . In one embodiment, when balance signal B_HI is at logic low and balance signal B_LO is at logic high, PMOS MP 100  and NMOS MN 9  are turned ON, NMOS MN 80  and PMOS MP 110  are turned OFF, sampled signal SEN is being stored at logic low accordingly. In another embodiment, when balance signal B_HI is at logic high and balance signal B_LO is at logic low, PMOS MP 100  and NMOS MN 9  are turned OFF, NMOS MN 80  and PMOS MP 110  are turned ON, sampled signal SEN is being stored at logic high accordingly. 
     Single-ended output module  705  comprises PMOS MP 13 , PMOS MP 15 , NMOS MN 11  and NMOS MN 13 . Different with single-ended output module  505 , in the embodiment shown in  FIG. 10 , the drain of PMOS MP 15  and the drain of NMOS MN 13  are coupled together as an output terminal of single-ended output module  705 . 
     In one embodiment, when latch control signal LAT_S is at logic low and latch control signal LAT_SB is at logic high, sampled signal SEN is being held under control of hold control module  503  via turning ON PMOS MP 14  and turning ON NMOS MN 12 . Output signal OUT is provided based on set signal SET and/or sampled signal SEN. When set signal SET is at logic high, NMOS MN 10  is turned ON, default control signal D_L is at logic low to turn ON PMOS MP 15 , and output signal OUT is at logic high accordingly. When set signal SET is at logic low, NMOS MN 10  is turned OFF, single-ended output module  506  is configured to provide output signal OUT based on sampled signal SEN, for example, output signal OUT is at logic high when sampled signal SEN is being held at logic high, and output signal OUT is at logic low when sampled signal is being held at logic low. 
     It should be noted that “logic high” and “logic low” abovementioned may be substituted with each other since different logic circuit may have a same operation result. 
     While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.