Patent Publication Number: US-8543870-B2

Title: Circuit for detecting and recording chip fails and the method thereof

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a circuit design, and more particularly, to a circuit design for detecting and recording chip fails. 
     2. Description of the Related Art 
     In circuit design, it is not uncommon for the chip to fail during the test stage. Therefore, debugging, i.e. locating the problem that causes the chip to fail, is extremely important, and may even comprise a majority of the time needed to produce the product. Debugging fails on chips can be very costly and time consuming, especially if there are no probe pads available when they are needed in the debugging process. Therefore, there is a need to design a circuit and method to detect and record chip fails. 
     SUMMARY OF THE INVENTION 
     The circuit for detecting and recording chip fails according to one embodiment of the present invention comprises a common error bus, a plurality of fail detector modules and a control center. Each of the plurality of fail detector modules is configured to receive at least a data signal to determine an occurrence of a chip fail and to correspondingly broadcast a fail code on the common error bus when the common error bus is not busy. The control center is configured to record a fail code from the common error bus and to report the recorded fail code when required. 
     The method for detecting and recording chip fails according to one embodiment of the present invention comprises the steps of: receiving at least a data signal to determine an occurrence of a chip fail; broadcasting a fail code of the chip fail on a common error bus when the common error bus is not busy; collecting the fail code from the common error bus and storing the chip fail into a memory; and retrieving and reporting the fail code when requested. 
     The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, and form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes as those of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The objectives and advantages of the present invention will become apparent upon reading the following description and upon referring to the accompanying drawings of which: 
         FIG. 1  shows a flowchart of the method for detecting and recording chip fails according to an embodiment of the present invention; 
         FIG. 2  shows the block diagram of a circuit for detecting and recording chip fails according to an embodiment of the present invention; 
         FIG. 3  shows the block diagram of a common error bus according to an embodiment of the present invention; 
         FIG. 4  shows the block diagram of a fail detector module according to an embodiment of the present invention; 
         FIG. 5  shows the block diagram of a control center according to an embodiment of the present invention; and 
         FIG. 6  shows a waveform of different signal lines when applying the method and circuit for detecting and recording chip fails provided by an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  shows a flowchart of the method for detecting and recording chip fails according to an embodiment of the present invention. In step  101 , at least a data signal is received, and step  102  is executed. In step  102 , whether a chip fail occurs is determined according to the at least one received data signal. If a chip fail occurs, step  103  is executed; otherwise, step  101  is executed. In step  103 , whether the status of a common error bus is busy is determined. If the status of the common error bus is busy, step  103  is executed; otherwise, step  104  is executed. In step  104 , a fail code of the chip fail is broadcasted on the common error bus, and step  105  is executed. In step  105 , the status of the common error bus is set as busy, and step  106  is executed. In step  106 , the fail code is collected from the common error bus and is stored into a memory, and step  107  is executed. In step  107 , the status of the common error bus is reset as idle, and step  108  is executed. In step  108 , whether a request for reading the memory is received is determined. If a request for reading the memory is received, step  109  is executed; otherwise, step  108  is executed. In step  109 , the fail code is retrieved from the memory and is reported, and the present method is finished. 
     In some embodiments of the present invention, in step  102 , the occurrence of a chip fail is determined according to two received data signals. In some embodiments of the present invention, in step  104 , every bit of the fail code is broadcasted in parallel; while in other embodiments of the present invention, in step  104 , each bit of the fail code is broadcasted serially. In some embodiments of the present invention, in step  104 , the broadcasting of the fail code on the common error bus is synchronous with a bus clock signal. 
       FIG. 2  shows the block diagram of a circuit for detecting and recording chip fails according to an embodiment of the present invention. The circuit  200  shown in  FIG. 2  can be used to implement the method shown in  FIG. 1 . As shown in  FIG. 2 , the circuit  200  comprises a first fail detector module  202 , a second fail detector module  204 , a control center  206  and a common error bus  208 . The first fail detector module  202  and the second fail detector module  204  are both configured to individually receive two data signals to determine an occurrence of a chip fail and to correspondingly broadcast a fail code on the common error bus  208  when the common error bus  208  is not busy. As can be seen from  FIG. 2 , the first fail detector module  202  received the data signals of A 0  and B 0 , while the second fail detector module  204  received the data signals of A 1  and B 1 , wherein the data signals A 0 , B 0 , A 1  and B 1  can be internal signals from a chip. The control center  206  is configured to record a fail code from the common error bus  208  and to report the recorded fail code when required. 
     When a chip fail occurs, which is reflected by the combination of the data signals A 0  and B 0  or A 1  and B 1 , and the common error bus  208  is not busy, either the first fail detector module  202  or the second fail detector module  204  will broadcast a fail code on the common error bus  208 . Accordingly, the control center  206  collects the fail code and reports the fail code when requested. According to the reported fail code, the source or the cause of the chip fail can be determined. 
       FIG. 3  shows a block diagram of the common error bus  208  shown in  FIG. 2 . As shown in  FIG. 3 , the common error bus  208  comprises three data lines: a bus status line  302 , a bus clock line  304  and a bus data line  306 . The bus status line  302  is used to carry a bus state signal indicating either an idle state or a busy state of the common error bus  208 . The bus clock line  304  is used to carry a bus clock signal. The bus data line  306  is used to carry a fail code from either the first fail detector module  202  or the second fail detector module  204  to the control center  206 . 
       FIG. 4  shows a block diagram of the first fail detector module  202  shown in  FIG. 2 . The second fail detector module  204  has a structure similar to that of the first fail detector module  202 . As shown in  FIG. 4 , the first fail detector module  202  comprises a combinational logic  402  and a data transmission block  404 . The combinational logic  402 , comprising gate logics of  406  to  430 , includes a plurality of input ports to receive the data signals A 0  and B 0 , the bus state signal, the bus clock signal and a reset signal and a plurality of output ports to provide a local busy signal and the bus state signal, and is configured to provide the bus state signal indicating the busy state of the common error bus  208  and to instruct the data transmission block  404  to broadcast a fail code when the combinational logic  402  determines an occurrence of a chip fail according to the data signals A 0  and B 0 , and to provide the bus state signal indicating the idle state of the common error bus  208  when the combinational logic  402  receives the reset signal. The data transmission block  404  includes a plurality of input ports to receive the bus clock signal, the reset signal and the local busy signal and an output port to broadcast a fail code on the bus data line  306  of the common error bus  208 , and is configured to broadcast a fail code on the bus data line  306  when receiving the local busy signal and to stop broadcasting when receiving the reset signal. 
     In some embodiments of the present invention, the data transmission block  404  broadcasts every bit of the fail code in parallel, while in other embodiments of the present invention, the data transmission block  404  broadcasts each bit of the fail code serially. The first fail detector module  202  and the second fail detector module  204  correspond to different fail codes such that when a fail code is reported, the source of the fail code can be determined. 
       FIG. 5  shows a block diagram of the control center  206  shown in  FIG. 2 . As shown in  FIG. 5 , the control center  206  comprises a control logic  502 , a memory array  504  and a data request logic  506 . The control logic  502  includes a plurality of input ports to receive the bus state signal, the bus clock signal and a fail code from the common error bus  208  and an output port to store the fail code to the memory array  504  through a write port of the memory array  504 , and is configured to collect a fail code from the common error bus  208  and store the collected fail code to the memory array  504  when the state of the common error bus  208  indicated by the bus state signal is busy. The data request logic  506  includes a plurality of input ports to receive the bus clock signal and a request signal and an output port to report a fail code retrieved from the memory array  504  through a read port of the memory array  504 , and is configured to read a fail code from the memory array  504  and report the read fail code when receiving the request signal. 
       FIG. 6  shows a waveform of different signal lines in the first fail detector module  202 . As shown in  FIG. 6 , when the combination of the data signal A 0  and B 0  indicates a chip fail, the output local busy signal of the combinational logic  402  is activated. Accordingly, the combinational logic  402  outputs the bus state signal with logic high indicating a busy state of the common error bus  208 , and the data transmission block  404  broadcasts a fail code on the common error bus  208 . In addition, when a reset signal is received, the broadcasting of the fail code stops, and the status of the common error bus  208  is reset. 
     In conclusion, the method and circuit for detecting and recording chip fails according to embodiments of the present invention are most applicable for, but not limited to, use with systems to record internal fails or conditions. This is done by first monitoring for internal fails and when an internal fail is detected, sending a fail code to a common error bus. The fail code propagates to a control center where it is recorded. The fail code can then be read to determine where and what type of fail occurred. 
     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof. 
     Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.