Patent Publication Number: US-7593255-B2

Title: Integrated circuit for programming a memory element

Description:
BACKGROUND 
     One type of memory is resistive memory. Resistive memory utilizes the resistance value of a memory element to store one or more bits of data. For example, a memory element programmed to have a high resistance value may represent a logic “1” data bit value and a memory element programmed to have a low resistance value may represent a logic “0” data bit value. Typically, the resistance value of the memory element is switched electrically by applying a voltage pulse or a current pulse to the memory element. 
     One type of resistive memory is phase change memory. Phase change memory uses a phase change material in the resistive memory element. The phase change material exhibits at least two different states. The states of the phase change material may be referred to as the amorphous state and the crystalline state, where the amorphous state involves a more disordered atomic structure and the crystalline state involves a more ordered lattice. The amorphous state usually exhibits higher resistivity than the crystalline state. Also, some phase change materials exhibit multiple crystalline states, e.g. a face-centered cubic (FCC) state and a hexagonal closest packing (HCP) state, which have different resistivities and may be used to store bits of data. In the following description, the amorphous state generally refers to the state having the higher resistivity and the crystalline state generally refers to the state having the lower resistivity. 
     Phase changes in the phase change materials may be induced reversibly. In this way, the memory may change from the amorphous state to the crystalline state—“set”—and from the crystalline state to the amorphous state—“reset”—in response to temperature changes. The temperature changes of the phase change material may be achieved by driving current through the phase change material itself or by driving current through a resistive heater adjacent the phase change material. With both of these methods, controllable heating of the phase change material causes controllable phase change within the phase change material. 
     A phase change memory including a memory array having a plurality of memory cells that are made of phase change material may be programmed to store data utilizing the memory states of the phase change material. One way to read and write data in such a phase change memory device is to control a current and/or a voltage pulse that is applied to the phase change material. The temperature in the phase change material in each memory cell generally corresponds to the applied level of current and/or voltage to achieve the heating. 
     To achieve higher density phase change memories, a phase change memory cell can store multiple bits of data. Multi-bit storage in a phase change memory cell can be achieved by programming the phase change material to have intermediate resistance values or states, where the multi-bit or multilevel phase change memory cell can be written to more than two states. If the phase change memory cell is programmed to one of three different resistance levels, 1.5 bits of data per cell can be stored. If the phase change memory cell is programmed to one of four different resistance levels, two bits of data per cell can be stored, and so on. 
     To program a phase change memory cell to an intermediate resistance value, the amount of crystalline material coexisting with amorphous material and hence the cell resistance is controlled via a suitable write strategy. The amount of crystalline material coexisting with amorphous material should be precisely controlled to ensure consistent resistance values for multi-bit storage. Consistent resistance values having a narrow distribution of the different resistance levels ensure that a sufficient sensing margin can be obtained. 
     For these and other reasons, there is a need for the present invention. 
     SUMMARY 
     One embodiment provides an integrated circuit. The integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element by iteratively applying a variable program pulse to the memory element until a resistance of the memory element crosses a first reference resistance. The variable program pulse is adjusted for each iteration such that the resistance of the memory element approaches the first reference resistance. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. 
         FIG. 1  is a block diagram illustrating one embodiment of a system. 
         FIG. 2  is a diagram illustrating one embodiment of a memory device. 
         FIG. 3  is a diagram illustrating one embodiment of a phase change element in four different states. 
         FIG. 4  is a graph illustrating one embodiment of resistance versus pulse current for programming a phase change element. 
         FIG. 5  is a flow diagram illustrating one embodiment of a method for programming a phase change element. 
         FIG. 6  is a graph illustrating another embodiment of resistance versus pulse current for programming a phase change element. 
         FIG. 7  is a flow diagram illustrating another embodiment of a method for programming a phase change element. 
         FIG. 8  is a graph illustrating another embodiment of resistance versus pulse current for programming a phase change element. 
         FIG. 9  is a flow diagram illustrating another embodiment of a method for programming a phase change element. 
         FIG. 10  is a graph illustrating another embodiment of resistance versus pulse current for programming a phase change element. 
         FIG. 11  is a flow diagram illustrating another embodiment of a method for programming a phase change element. 
         FIG. 12  is a graph illustrating another embodiment of resistance versus pulse current for programming a phase change element. 
         FIG. 13  is a flow diagram illustrating another embodiment of a method for programming a phase change element. 
     
    
    
     DETAILED DESCRIPTION 
     In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. 
     It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise. 
       FIG. 1  is a block diagram illustrating one embodiment of a system  90 . System  90  includes a host  92  and a memory device  100 . Host  92  is communicatively coupled to memory device  100  through communication link  94 . Host  92  includes a computer (e.g., desktop, laptop, handheld), portable electronic device (e.g., cellular phone, personal digital assistant (PDA), MP3 player, video player, digital camera), or any other suitable device that uses memory. Memory device  100  provides memory for host  92 . In one embodiment, memory device  100  includes a phase change memory device or other suitable resistive or resistivity changing material memory device. 
       FIG. 2  is a diagram illustrating one embodiment of memory device  100 . In one embodiment, memory device  100  is an integrated circuit or part of an integrated circuit. Memory device  100  includes a write circuit  124 , a controller  120 , a memory array  101 , and a sense circuit  126 . Memory array  101  includes a plurality of phase change memory cells  104   a - 104   d  (collectively referred to as phase change memory cells  104 ), a plurality of bit lines (BLs)  112   a - 112   b  (collectively referred to as bit lines  112 ), and a plurality of word lines (WLs)  110   a - 110   b  (collectively referred to as word lines  110 ). 
     A selected memory cell  104  is programmed to a desired intermediate resistance state by using an iterative process. The iterative process includes applying variable program pulses to the selected memory cell until the resistance of the selected memory cell crosses a reference resistance. A parameter or parameters of the variable program pulse are adjusted for each iteration. The parameter or parameters are adjusted such that the resistance of the selected memory cell gradually approaches the reference resistance. Once the resistance of the selected memory cell crosses the reference resistance, the selected memory cell is programmed to the desired intermediate resistance state. 
     In one embodiment, the variable program pulses include partial set pulses. In one embodiment, the initial partial set pulse is preceded by a fixed reset pulse. In another embodiment, each partial set pulse is preceded by the fixed reset pulse. In another embodiment, the variable program pulses include partial reset pulses. In this embodiment, each partial reset pulse is optionally preceded by the fixed reset pulse. The reset and/or variable program pulses are applied to the selected memory cell until the resistance of the selected memory cell reaches the desired resistance state or until a maximum number of iterations is exceeded. If the maximum number of iterations is exceeded, the selected memory cell is considered to be defective and programming of the selected memory cell is terminated. 
     As used herein, the term “electrically coupled” is not meant to mean that the elements must be directly coupled together and intervening elements may be provided between the “electrically coupled” elements. 
     Memory array  101  is electrically coupled to write circuit  124  through signal path  125 , to controller  120  through signal path  121 , and to sense circuit  126  through signal path  127 . Controller  120  is electrically coupled to write circuit  124  through signal path  128  and to sense circuit  126  through signal path  130 . Each phase change memory cell  104  is electrically coupled to a word line  110 , a bit line  112 , and a common or ground  114 . Phase change memory cell  104   a  is electrically coupled to bit line  112   a , word line  110   a , and common or ground  114 , and phase change memory cell  104   b  is electrically coupled to bit line  112   a , word line  110   b , and common or ground  114 . Phase change memory cell  104   c  is electrically coupled to bit line  112   b , word line  110   a , and common or ground  114 , and phase change memory cell  104   d  is electrically coupled to bit line  112   b , word line  110   b , and common or ground  114 . 
     Each phase change memory cell  104  includes a phase change element  106  and a transistor  108 . While transistor  108  is a field-effect transistor (FET) in the illustrated embodiment, in other embodiments, transistor  108  can be another suitable device such as a bipolar transistor or a 3D transistor structure. In other embodiments, a diode or diode-like structure is used in place of transistor  108 . In this case, a diode and phase change element  106  is coupled in series between each cross point of word lines  110  and bit lines  112 . 
     Phase change memory cell  104   a  includes phase change element  106   a  and transistor  108   a . One side of phase change element  106   a  is electrically coupled to bit line  112   a , and the other side of phase change element  106   a  is electrically coupled to one side of the source-drain path of transistor  108   a . The other side of the source-drain path of transistor  108   a  is electrically coupled to common or ground  114 . The gate of transistor  108   a  is electrically coupled to word line  110   a.    
     Phase change memory cell  104   b  includes phase change element  106   b  and transistor  108   b . One side of phase change element  106   b  is electrically coupled to bit line  112   a , and the other side of phase change element  106   b  is electrically coupled to one side of the source-drain path of transistor  108   b . The other side of the source-drain path of transistor  108   b  is electrically coupled to common or ground  114 . The gate of transistor  108   b  is electrically coupled to word line  110   b.    
     Phase change memory cell  104   c  includes phase change element  106   c  and transistor  108   c . One side of phase change element  106   c  is electrically coupled to bit line  112   b  and the other side of phase change element  106   c  is electrically coupled to one side of the source-drain path of transistor  108   c . The other side of the source-drain path of transistor  108   c  is electrically coupled to common or ground  114 . The gate of transistor  108   c  is electrically coupled to word line  110   a.    
     Phase change memory cell  104   d  includes phase change element  106   d  and transistor  108   d . One side of phase change element  106   d  is electrically coupled to bit line  112   b  and the other side of phase change element  106   d  is electrically coupled to one side of the source-drain path of transistor  108   d . The other side of the source-drain path of transistor  108   d  is electrically coupled to common or ground  114 . The gate of transistor  108   d  is electrically coupled to word line  110   b.    
     In another embodiment, each phase change element  106  is electrically coupled to a common or ground  114  and each transistor  108  is electrically coupled to a bit line  112 . For example, for phase change memory cell  104   a , one side of phase change element  106   a  is electrically coupled to common or ground  114 . The other side of phase change element  106   a  is electrically coupled to one side of the source-drain path of transistor  108   a . The other side of the source-drain path of transistor  108   a  is electrically coupled to bit line  112   a.    
     In one embodiment, each phase change element  106  includes a phase change material that may be made up of a variety of materials. Generally, chalcogenide alloys that contain one or more elements from group VI of the periodic table are useful as such materials. In one embodiment, the phase change material of phase change element  106  is made up of a chalcogenide compound material, such as GeSbTe, SbTe, GeTe or AgInSbTe. In another embodiment, the phase change material is chalcogen free, such as GeSb, GaSb, InSb, or GeGaInSb. In other embodiments, the phase change material is made up of any suitable material including one or more of the elements Ge, Sb, Te, Ga, As, In, Se, and S. 
     Each phase change element  106  may be changed from an amorphous state to a crystalline state or from a crystalline state to an amorphous state under the influence of temperature change. The amount of crystalline material coexisting with amorphous material in the phase change material of one of the phase change elements  106   a - 106   d  thereby defines two or more states for storing data within memory device  100 . In the amorphous state, a phase change material exhibits significantly higher resistivity than in the crystalline state. Therefore, the two or more states of phase change elements  106   a - 106   d  differ in their electrical resistivity. In one embodiment, the two or more states are two states and a binary system is used, wherein the two states are assigned bit values of “0” and “1”. In another embodiment, the two or more states are three states and a ternary system is used, wherein the three states are assigned bit values of “0”, “1”, and “2”. In another embodiment, the two or more states are four states that can be assigned multi-bit values, such as “00”, “01”, “10”, and “11”. In other embodiments, the two or more states can be any suitable number of states in the phase change material of a phase change element. 
     Controller  120  includes a microprocessor, microcontroller, or other suitable logic circuitry for controlling the operation of memory device  100 . Controller  120  controls read and write operations of memory device  100  including the application of control and data signals to memory array  101  through write circuit  124  and sense circuit  126 . In one embodiment, controller  120  includes a counter  132 . Counter  132  counts the number of iterations used to program a memory cell  104 . If the number of iterations reaches a predetermined value, the memory cell being programmed is considered to be defective and the programming is terminated. 
     In one embodiment, write circuit  124  provides voltage pulses through signal path  125  and bit lines  112  to memory cells  104  to program the memory cells. In other embodiments, write circuit  124  provides current pulses through signal path  125  and bit lines  112  to memory cells  104  to program the memory cells. 
     Sense circuit  126  reads each of the two or more states of memory cells  104  through bit lines  112  and signal path  127 . In one embodiment, to read the resistance of one of the memory cells  104 , sense circuit  126  provides current that flows through one of the memory cells  104 . Sense circuit  126  then reads the voltage across that one of the memory cells  104 . In another embodiment, sense circuit  126  provides voltage across one of the memory cells  104  and reads the current that flows through that one of the memory cells  104 . In another embodiment, write circuit  124  provides voltage across one of the memory cells  104  and sense circuit  126  reads the current that flows through that one of the memory cells  104 . In another embodiment, write circuit  124  provides current that flows through one of the memory cells  104  and sense circuit  126  reads the voltage across that one of the memory cells  104 . 
     During a write operation of phase change memory cell  104   a , word line  110   a  is selected to activate transistor  108   a . With word line  110   a  selected, a reset current or voltage pulse is selectively enabled by write circuit  124  and sent through bit line  112   a  to phase change element  106   a  thereby heating phase change element  106   a  above its melting temperature. After the current or voltage pulse is turned off, phase change element  106   a  quickly quench cools into its substantially amorphous and highest resistance state. A variable programming current or voltage pulse is then selectively enabled by write circuit  124  and sent through bit line  112   a  to phase change element  106   a  thereby heating phase change element  106   a . The programming pulse includes a partial set pulse or a partial reset pulse to change the resistance of phase change element  106   a.    
     The resistance of phase change element  106   a  is then read to determine whether the resistance has crossed a desired reference resistance. If the resistance of phase change element  106   a  has crossed the desired reference resistance, programming of phase change element  106   a  is complete. If the resistance of phase change element  106   a  has not crossed the desired reference resistance, one or more additional reset pulses and/or modified programming pulses are selectively enabled by write circuit  124  and sent through bit line  112   a  to phase change element  106   a . Each additional programming pulse is adjusted from the previous programming pulse such that the resistance of phase change element  106   a  gradually approaches the desired reference resistance. 
     The process is repeated until the resistance of phase change element  106   a  crosses the desired reference resistance or until counter  132  reaches a predetermined value. In this way, phase change element  106   a  is programmed to an amorphous state, crystalline state, or partially crystalline and partially amorphous state during this write operation. Phase change memory cells  104   b - 104   d  and other phase change memory cells  104  in memory array  101  are programmed similarly to phase change memory cell  104   a  using similar current or voltage pulses. 
       FIG. 3  is a diagram illustrating one embodiment of a phase change element  202  in four different states at  200   a ,  200   b ,  200   c , and  200   d . Phase change element  202  includes a phase change material  204  that is laterally surrounded by insulation material  206 . In other embodiments, phase change element  202  can have any suitable geometry including phase change material  204  in any suitable geometry and insulation material  206  in any suitable geometry. 
     Phase change material  204  is electrically coupled at one end to a first electrode  208  and at the other end to a second electrode  210 . Pulses are provided to phase change element  202  via first electrode  208  and second electrode  210 . The current path through phase change material  204  is from one of the first electrode  208  and second electrode  210  to the other one of the first electrode  208  and second electrode  210 . In one embodiment, each of the phase change elements  106   a - 106   d  is similar to phase change element  202 . Phase change element  202  provides a storage location for storing bits of data. 
     Insulation material  206  can be any suitable insulator, such as SiO 2 , SiO x , SiN, fluorinated silica glass (FSG), boro-phosphorous silicate glass (BPSG), or boro-silicate glass (BSG). First electrode  208  and second electrode  210  can be any suitable electrode material, such as TiN, TaN, W, WN, Al, C, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, or Cu. 
     Phase change material  204  is programmed into one of four states to store two bits of data. A selection device, such as an active device like a transistor  108  ( FIG. 2 ) or diode, is coupled to first electrode  208  to control the application of pulses to phase change material  204 . The pulses melt phase change material  204  and program one of the four states into phase change material  204 . At  200   a , a large fraction  222  of phase change material  204  has been programmed to change the resistance through phase change material  204  and phase change element  202 . At  200   b , a small fraction  212  of phase change material  204  has been programmed to change the resistance through phase change material  204  and phase change element  202 . At  200   c , a medium sized fraction  214  of phase change material  204  has been programmed to change the resistance through phase change material  204  and phase change element  202 . At  200   d , a large fraction  216 , which is substantially all of phase change material  204 , has been programmed to change the resistance through phase change material  204  and phase change element  202 . 
     The size and state of the programmed fraction is related to the resistance through phase change material  204  and phase change element  202 . The four different phase change fractions at  200   a - 200   d  provide four states in phase change material  204 , and phase change element  202  provides a storage location for storing two bits of data. In one embodiment, the state of phase change element  202  at  200   a  is a “00”, the state of phase change element  202  at  200   b  is a “01”, the state of phase change element  202  at  200   c  is a “10”, and the state of phase change element  202  at  200   d  is a “11”. In another embodiment, the state of phase change element  202  at  200   a  is a “11”, the state of phase change element  202  at  200   b  is a “10”, the state of phase change element  202  at  200   c  is a “01”, and the state of phase change element  202  at  200   d  is a “00”. 
     At  200   a , phase change material  204  is programmed to a substantially amorphous state. During a write operation of phase change element  202 , a write pulse is selectively enabled by the selection device and sent through first electrode  208  and phase change material  204 . The write pulse heats phase change material  204  above its melting temperature and phase change material  204  is quickly cooled to achieve the substantially amorphous state at  200   a . After the write operation, phase change material  204  includes crystalline state phase change material at  218  and  220 , and amorphous state phase change material at  222 . The substantially amorphous state at  200   a  is the highest resistance state of phase change element  202 . 
     To program phase change material  204  into one of the other three states  200   b - 200   d , a first fixed pulse (i.e., a reset pulse) resets phase change element  202  to the substantially amorphous state and a second variable pulse (i.e., a programming pulse) programs phase change element  202  to the desired resistance state. In one embodiment, the first fixed pulse is optional if the second variable pulse includes a partial reset pulse. The pulses are iteratively applied until the resistance of phase change element  202  crosses a reference resistance for the desired resistance state. 
     At  200   b , reset and programming pulses are provided to program the small volume fraction  212  into a crystalline state. The crystalline state is less resistive than the amorphous state and phase change element  202  at  200   b  has a lower resistance than phase change element  202  in the substantially amorphous state at  200   a . The partially crystalline and partially amorphous state at  200   b  is the second highest resistance state of phase change element  202 . 
     At  200   c , reset and programming pulses are provided to program the medium volume fraction  214  into a crystalline state. Since the crystalline fraction  214  is larger than the crystalline faction  212  and the crystalline state is less resistive than the amorphous state, phase change element  202  at  200   c  has a lower resistance than phase change element  202  at  200   b  and phase change element  202  in the substantially amorphous state at  200   a . The partially crystalline and partially amorphous state at  200   c  is the second lowest resistance state of phase change element  202 . 
     At  200   d , reset and programming pulses are provided to program substantially all of the phase change material  216  into the crystalline state. Since the crystalline state is less resistive than the amorphous state, phase change element  202  at  200   d  has a lower resistance than phase change element  202  at  200   c , phase change element  202  at  200   b , and phase change element  202  in the substantially amorphous state at  200   a . The substantially crystalline state at  200   d  is the lowest resistance state of phase change element  202 . In other embodiments, phase change element  202  can be programmed into any suitable number of resistance values or states. 
       FIG. 4  is a graph  300   a  illustrating one embodiment of resistance versus pulse current for programming a phase change element. Graph  300   a  includes pulse current in amps on x-axis  302  and cell resistance in ohms on y-axis  304 . The resistance values for optimized or fixed reset pulses are indicated by line  306  and the resistance values for variable program pulses are indicated by curve  308 . 
     An optimized reset pulse resets the phase change element to the substantially amorphous state (i.e., the highest resistance state) as illustrated at  200   a  in  FIG. 3 . In one embodiment, the variable program pulse includes a set pulse that sets the phase change element to the substantially crystalline state (i.e., the lowest resistance state) as illustrated at  200   d  in  FIG. 3 . In another embodiment, the variable program pulse includes a partial set pulse that sets the phase change element to an intermediate resistance state, such as illustrated at  200   b  and  200   c  in  FIG. 3 . The partial set pulse and the resulting resistance is represented by the left side of the U-shaped curve  308 . In another embodiment, the variable program pulse includes a partial reset pulse that resets the phase change element to an intermediate resistance state, such as illustrated at  200   b  or  200   c  in  FIG. 3 . The partial reset pulse and the resulting resistance is represented by the right side of the U-shaped curve  308 . 
     In one embodiment, to program a selected phase change element to a resistance state between resistance R 1   310  and resistance R 2   312 , the variable program pulse includes a partial set pulse. An iterative process as described below with reference to  FIG. 5  is used to program the selected phase change element to a resistance state between resistance R 1   310  and resistance R 2   312 . The selected phase change element is programmed iteratively from the high resistance side (i.e., from above resistance R 1   310 ) of the partial set pulse region as indicated at  314   a.    
       FIG. 5  is a flow diagram illustrating one embodiment of a method  400  for programming a phase change element. At  402 , the initial reset pulse and program pulse parameters are loaded. The initial program pulse parameters are selected such that the initial program pulse will program the phase change element to a resistance greater than resistance R 1   310 . At  404 , the reset pulse is applied to the phase change element to reset the phase change element to the highest resistance state. At  406 , the resistance (R) of the phase change element is read and the resistance is compared to resistance R 1   310 . If the resistance of the phase change element is greater than resistance R 1   310 , then at  408  the program pulse is applied to the phase change element to program the phase change element to a resistance less than the current resistance of the phase change element. At  410 , the next parameter for the program pulse is loaded. The next parameter increases the amplitude, and/or width, and/or tail of the program pulse such that the next program pulse programs the phase change element to a resistance less than the current resistance of the phase change element. Control then returns to  406  where the resistance of the phase change element is again read and compared to resistance R 1   310 . 
     If the resistance of the phase change element is less than resistance R 1   310 , then at  412  the resistance of the phase change element is compared to resistance R 2   312 . If the resistance of the phase change element is greater than resistance R 2   312 , then at  414  programming of the phase change element is complete. If the resistance of the phase change element is less than resistance R 2   312 , then at  416  the reset pulse and/or program pulse parameters may be adjusted. In one embodiment, the program pulse parameters are restored to the initial conditions from  402 . In another embodiment, the step size for the adjustment of the program pulse parameters at  410  is changed. In yet another embodiment, the current program pulse parameters are unchanged. Control then returns to  404  where the reset pulse is again applied to the phase change element and the process repeats. The process repeats until the resistance of the phase change element is less than resistance R 1   310  and greater than resistance R 2   312 . If a count of the iterations reaches a predetermined value, the phase change element is considered defective and the programming process is terminated. 
       FIG. 6  is a graph  300   b  illustrating another embodiment of resistance versus pulse current for programming a phase change element. Graph  300   b  is similar to graph  300   a  previously described and illustrated with reference to  FIG. 4 , except that graph  300   b  includes arrow  314   b  and resistance R 1   310  has been removed. In this embodiment, to program a selected phase change element to a resistance state just below resistance R 2   312 , the variable program pulse includes a partial set pulse. An iterative process as described below with reference to  FIG. 7  is used to program the selected phase change element to a resistance state just below resistance R 2   312 . The selected phase change element is programmed iteratively from the high resistance side (i.e., from above resistance R 2   312 ) of the partial set pulse region as indicated at  314   b.    
       FIG. 7  is a flow diagram illustrating another embodiment of a method  430  for programming a phase change element. At  432 , the initial reset pulse and program pulse parameters are loaded. The initial program pulse parameters are selected such that the initial program pulse will program the phase change element to a resistance greater than resistance R 2   312 . At  434 , the reset pulse is applied to the phase change element to reset the phase change element to the highest resistance state. At  436 , the program pulse is applied to the phase change element to program the phase change element to a resistance less than the highest resistance state. 
     At  438 , the resistance of the phase change element is read and the resistance is compared to resistance R 2   312 . If the resistance of the phase change element is less than resistance R 2   312 , then at  440  programming of the phase change element is complete. If the resistance of the phase change element is greater than resistance R 2   312 , then at  442  the next parameter for the program pulse is loaded. The next parameter increases the amplitude, and/or width, and/or tail of the program pulse such that the next program pulse programs the phase change element to a resistance less than the current resistance of the phase change element. Control then returns to  434  where the reset pulse is again applied to the phase change element and the process repeats. The process repeats until the resistance of the phase change element crosses resistance R 2   312 , such that the resistance of the phase change element is less than resistance R 2   312 . If a count of the iterations reaches a predetermined value, the phase change element is considered defective and the programming process is terminated. 
       FIG. 8  is a graph  300   c  illustrating another embodiment of resistance versus pulse current for programming a phase change element. Graph  300   c  is similar to graph  300   a  previously described and illustrated with reference to  FIG. 4 , except that graph  300   c  includes arrow  314   c  and resistance R 1   310  has been removed. In this embodiment, to program a selected phase change element to a resistance state just above resistance R 2   312 , the variable program pulse includes a partial set pulse. An iterative process as described below with reference to  FIG. 9  is used to program the selected phase change element to a resistance state just above resistance R 2   312 . The selected phase change element is programmed iteratively from the low resistance side (i.e., from below resistance R 2   312 ) of the partial set pulse region as indicated at  314   c.    
       FIG. 9  is a flow diagram illustrating another embodiment of a method  460  for programming a phase change element. At  462 , the initial reset pulse and program pulse parameters are loaded. The initial program pulse parameters are selected such that the initial program pulse will program the phase change element to a resistance less than resistance R 2   312 . In one embodiment, the initial program pulse parameters are selected such that the initial program pulse is an optimized set pulse. At  464 , the reset pulse is applied to the phase change element to reset the phase change element to the highest resistance state. At  466 , the program pulse is applied to the phase change element to program the phase change element to a resistance less than the highest resistance state. 
     At  468 , the resistance of the phase change element is read and the resistance is compared to resistance R 2   312 . If the resistance of the phase change element is greater than resistance R 2   312 , then at  470  programming of the phase change element is complete. If the resistance of the phase change element is less than resistance R 2   312 , then at  472  the next parameter for the program pulse is loaded. The next parameter decreases the amplitude, and/or width, and/or tail of the program pulse such that the next program pulse programs the phase change element to a resistance greater than the current resistance of the phase change element. Control then returns to  464  where the reset pulse is again applied to the phase change element and the process repeats. The process repeats until the resistance of the phase change element crosses resistance R 2   312 , such that the resistance of the phase change element is greater than resistance R 2   312 . If a count of the iterations reaches a predetermined value, the phase change element is considered defective and the programming process is terminated. 
       FIG. 10  is a graph  300   d  illustrating another embodiment of resistance versus pulse current for programming a phase change element. Graph  300   d  is similar to graph  300   a  previously described and illustrated with reference to  FIG. 4 , except that graph  300   d  includes arrow  314   d  and resistance R 1   310  has been removed. In this embodiment, to program a selected phase change element to a resistance state just below resistance R 2   312 , the variable program pulse includes a partial reset pulse. An iterative process as described below with reference to  FIG. 11  is used to program the selected phase change element to a resistance state just below resistance R 2   312 . The selected phase change element is programmed iteratively from the high resistance side (i.e., from above resistance R 2   312 ) of the partial reset pulse region as indicated at  314   d.    
       FIG. 11  is a flow diagram illustrating another embodiment of a method  500  for programming a phase change element. At  502 , the initial reset pulse and program pulse parameters are loaded. The initial program pulse parameters are selected such that the initial program pulse will program the phase change element to a resistance greater than resistance R 2   312 . At  504 , the reset pulse is optionally applied to the phase change element to reset the phase change element to the highest resistance state. In one embodiment, applying the reset pulse at  504  is excluded and the method proceeds from  502  directly to  506 . At  506 , the program pulse is applied to the phase change element to program the phase change element to a resistance less than the highest resistance state. 
     At  508 , the resistance of the phase change element is read and the resistance is compared to resistance R 2   312 . If the resistance of the phase change element is less than resistance R 2   312 , then at  510  programming of the phase change element is complete. If the resistance of the phase change element is greater than resistance R 2   312 , then at  512  the next parameter for the program pulse is loaded. The next parameter decreases the amplitude, and/or increases the width, and/or increases the tail of the program pulse such that the next program pulse programs the phase change element to a resistance less than the current resistance of the phase change element. Control then returns to  504  where the reset pulse is again optionally applied to the phase change element and the process repeats. The process repeats until the resistance of the phase change element crosses resistance R 2   312 , such that the resistance of the phase change element is less than resistance R 2   312 . If a count of the iterations reaches a predetermined value, the phase change element is considered defective and the programming process is terminated. 
       FIG. 12  is a graph  300   e  illustrating another embodiment of resistance versus pulse current for programming a phase change element. Graph  300   e  is similar to graph  300   a  previously described and illustrated with reference to  FIG. 4 , except that graph  300   e  includes arrow  314   e  and resistance R 1   310  has been removed. In this embodiment, to program a selected phase change element to a resistance state just above resistance R 2   312 , the variable program pulse includes a partial reset pulse. An iterative process as described below with reference to  FIG. 13  is used to program the selected phase change element to a resistance state just above resistance R 2   312 . The selected phase change element is programmed iteratively from the low resistance side (i.e., from below resistance R 2   312 ) of the partial reset pulse region as indicated at  314   e.    
       FIG. 13  is a flow diagram illustrating another embodiment of a method  530  for programming a phase change element. At  532 , the initial reset pulse and program pulse parameters are loaded. The initial program pulse parameters are selected such that the initial program pulse will program the phase change element to a resistance less than resistance R 2   312 . At  534 , the reset pulse is optionally applied to the phase change element to reset the phase change element to the highest resistance state. In one embodiment, applying the reset pulse at  534  is excluded and the method proceeds from  532  directly to  536 . At  536 , the program pulse is applied to the phase change element to program the phase change element to a resistance less than the highest resistance state. 
     At  538 , the resistance of the phase change element is read and the resistance is compared to resistance R 2   312 . If the resistance of the phase change element is greater than resistance R 2   312 , then at  540  programming of the phase change element is complete. If the resistance of the phase change element is less than resistance R 2   312 , then at  542  the next parameter for the program pulse is loaded. The next parameter increases the amplitude, and/or decreases the width, and/or decreases the tail of the program pulse such that the next program pulse programs the phase change element to a resistance greater than the current resistance of the phase change element. Control then returns to  534  where the reset pulse is again optionally applied to the phase change element and the process repeats. The process repeats until the resistance of the phase change element crosses resistance R 2   312 , such that the resistance of the phase change element is greater than resistance R 2   312 . If a count of the iterations reaches a predetermined value, the phase change element is considered defective and the programming process is terminated. 
     Embodiments provide a method for programming phase change elements to a target resistance state. An iterative process is used to gradually approach the desired resistance state from a higher resistance or from a lower resistance. A binary comparison process is used to determine whether a phase change element is programmed to the target resistance state. Therefore, the sensed resistance of the phase change element is not converted to a digital value to implement the embodiments. Thus, embodiments reduce the time used to program the memory elements while increasing the precision of the programmed resistance compared to typical programming methods. 
     While the specific embodiments described herein substantially focused on using phase change memory elements, the embodiments can be applied to any suitable type of resistance or resistivity changing memory elements. 
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.