Patent Publication Number: US-6711724-B2

Title: Semiconductor integrated circuit device having pipeline stage and designing method therefor

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method of designing a semiconductor integrated circuit device, and to a semiconductor integrated circuit device, and more particularly to a method of designing a semiconductor integrated circuit device capable of reducing overhead such as clock skews and clock jitters when designing a pipeline in an integrated circuit device, and to a configuration of a semiconductor integrated circuit device manufactured according to such designing method. 
     2. Description of the Background Art 
     In an LSI large scale integrated circuit), a synchronous multi-stage pipeline for processing/transferring a signal synchronously with a clock signal so as to transfer the signal/data at high speed, is widely used. In constituting such a synchronous multi-stage pipeline, flip-flops or latches are normally used as transfer circuits. 
     FIG. 9 is a diagram showing an example of the configuration of a two-stage pipeline constituted by flip-flops. In FIG. 9, the two-stage pipeline includes a flip-flop circuit FF 01  which transfers an input signal IN synchronously with a clock signal CLK 01 , a logic circuit LG 1  which performs a predetermined logic processing on the signal applied from flip-flop circuit FF 01  and outputs a resultant signal, a flip-flop circuit FF 02  which transfers the output signal of logic circuit LG 1  synchronously with a clock signal CLK 02 , a logic circuit LG 2  which performs a predetermined logic processing on the signal applied from flip-flop FF 02  and outputs a resultant signal, and a flip-flop circuit FF 03  which transfers the output signal of logic circuit LG 2  synchronously with a clock signal CLK 03  and generates an output signal/data OUT. 
     Since logic circuits LG 1  and LG 2  each perform a logic processing on the received signal for outputting, logic circuits LG 1  and LG 2  have logic delays L 01  and L 02  in the propagation of the signals, respectively. 
     Normally, logic circuits LG 1  to LG 2  each receive a plurality of signals and performs a logic processing. In the description given hereinafter, though not particularly mentioned, a flip-flop circuit FF transfers one or a plurality of signals. The number of signals transferred by flip-flop circuit FF is determined according to the configuration of a logic circuit LG arranged at the subsequent stage. 
     Flip-flop circuit FF 01  has setup time SUP 11  and hold time HLD 11  for clock signal CLK 01 . In addition, flip-flop circuit FF 01  has output delay time TPD 11  since a trigger edge of clock signal CLK 01  is applied until a valid signal is outputted. 
     Flip-flop circuit FF 02  has setup time SUP 12  and hold time HLD 12  and output delay time TPD 12 . 
     Flip-flop circuit FF 03  has setup time SUP 13  and hold time HLD 13  and output delay time TPD 13 . 
     Further, fixed skews due to uncertain factors of clock signals, as described later, exist for the clock signals applied to flip-flop circuits FF 01  to FF 03 , respectively. 
     FIG. 10 is a diagram showing output delay time TPD, setup time SUP and hold time HLD shown in FIG.  9 . FIG. 10 shows parameters in a case where flip-flop circuits FF 01  to FF 03  are each a rising edge trigger type flip-flop that latches and outputs a signal applied at the rising edge of clock signal CLK. 
     Setup time SUP is a time period for which input signal SIN is kept in a definite state with respect to the rising edge of clock signal CLK. Hold time HLD is a time period required for input signal SIN to be kept in a definite state since the rising edge of clock signal CLK. Output delay time TPD is a time period required since clock signal CLK rises until the output signal SOUT of the flip-flop circuit is made definite. 
     Normally, setup time SUP is determined under the worst condition for the operating parameters of transistors which constitute a flip-flop. Hold time HLD is calculated using the best operating parameters of the transistors which constitute the flip-flop. 
     Clock signal CLK has a period TK. 
     As shown in FIG. 11, clock signals CLK 01  to CLK 03  are applied from a clock distribution circuit  110  which receives a clock signal CLK 0  generated from a clock generation circuit  100 . Clock distribution circuit  110  transfers applied clock signal CLK 0  to the respective the flip-flop circuits in the pipeline. 
     Clock generation circuit  100  is constructed by, for example, a PLL (phase locked loop), and generates internal clock signal CLK 0  synchronized in phase with an external clock signal such as a system clock. Clock distribution circuit  110  takes various configurations such as a tree-like clock network and a fishbone type clock distribution circuit according to the configuration of this pipeline. 
     Clock signals CLK 01  to CLK 03  are transferred through predetermined routes, respectively. Therefore, clock signals CLK 01  to CLK 03  applied to flip-flop circuits FF 01  to FF 03  shown in FIG. 9 each have clock signal ambiguities referred to as a skew or a jitter. Thus, clock signals CLK 01  to CLK 03  are deviated from an ideal edge of a clock signal. 
     Here, in the description given hereinafter, “clock skew” is defined as a spatial clock signal deviation caused by process variation and uneven interconnection in clock distribution circuit  110 . Namely, a clock skew indicates the phase deviation of a clock signal caused depending on the positional relationship between each of flip-flop circuits FF 01  to FF 03  and clock generation circuit  100 . 
     As for the clock skews, fixed factors caused by the unevenness of interconnections and process variations based on layout dependency and uncertain factors dependent on unpredictable process variations and the power supply voltage change, temperature change in clock distribution circuit  110  and other are separately considered. The unevenness of interconnections indicates variations in line width and interconnection length and such. Layout dependent process variations indicate the variations of operating characteristics due to the variations of impurity concentration dependent on the layout in transistors constituting a repeater which is included in clock distribution circuit  110  and which transmits the clock signal. 
     A “clock jitter” is defined as a temporal clock signal deviation caused by the power supply voltage fluctuation, temperature fluctuation or the like in clock generation circuit (PLL)  100 . It is, therefore, assumed that only uncertain factors exist for the clock jitters. Since the clock jitter is the temporal deviation of the clock signal, similar clock jitters occur to the respective flip-flop circuits. 
     Referring back to FIG. 9, a clock skew SKW 01  between flip-flop circuits FF 01  and FF 02  and a clock skew SKW 02  between flip-flop circuits FF 02  and FF 03  are fixed factor components of the clock skew. In addition, a clock skew between flip-flop circuits FF 01  and FF 03  is denoted by a reference symbol SKWA, which is also a fixed factor component of the clock skew. The fixed factor of the clock skew can take both positive and negative values. The fixed factor (SKW 01 , SKW 02 ) of a skew of a clock signal delayed in phase from a given clock signal has a positive value (cycle time can be made longer with respect to a logic circuit at the preceding stage). Further, the fixed factor of the skew of a clock signal faster in phase than this clock signal takes a negative value. 
     The clock skew uncertain factor between flip-flop circuits FF 01  and FF 02  is equal to that between flip-flop circuits FF 02  and FF 03 , and these factors are each defined to be an absolute value SKWET. This is because they are uncertain factors and the worst case is always supposed. 
     Furthermore, the clock jitter between flip-flop circuits FF 01  and FF 02  is equal to that between flip-flop circuits FF 02  and FF 03 , and these jitters are each defined to be an absolute value JTR. It is noted that clock jitter JTR is a value per one cycle TK of the clock signal. 
     A skew MRG is defined to be the sum of jitter component JTR and clock skew uncertain factor SKWET. 
     Each of logic circuits LG 1  and LG 2  needs to perform a predetermined logic processing on the signal applied thereto and to transfer the resultant signal to the flip-flop at the next stage within a period of one cycle TK of clock signal CLK 0 . 
     FIG. 12 shows a time period (logic delay time) L which each of logic circuits LG 1  and LG 1  can use within one cycle period of clock signal CLK. Referring to FIG. 12, a period of one cycle TK of clock signal CLK covers output delay time TPD, signal logic delay time L of a logic circuit, jitter JTR, clock skew uncertain factor SKWET, setup time SUP of the flip-flop in the next stage, and clock skew fixed factor SKW of the flip-flop at the next stage. Jitter JTR indicates the magnitude of the changing range of the phase of the trigger edge (rising edge) of clock signal CLK. 
     In FIG. 12, therefore, it is necessary that each of logic circuits LG 1  and LG 2  satisfies the following setup conditional expressions: 
     
       
           L   01 ≦ TK−TPD   01 − SUP   02 + SKW   01 − SKWET−JTR   (1); and 
       
     
     
       
           L   02 ≦ TK−TPD   02 − SUP   03 + SKW   02 − SKWET−JTR   (2). 
       
     
     As for the hold time, logic delay time L 01  and L 02  of respective logic circuits LG 1  and LG 2  need to satisfy the following hold conditions since it is necessary to prevent the output signal of a flip-flop circuit from changing within the hold time of the flip-flop circuit at the next stage: 
     
       
           LH   01 ≧ HLD   02 − TPDH   01 + SKWH   01 + SKWETH   (3); and 
       
     
     
       
           LH   02 ≧ HLD   03 − TPDH   02 + SKWH   02 + SKWETH   (4). 
       
     
     The reason why no jitter JTR appears in the above hold conditional expressions is that a jitter occurs in each clock signal and the jitter components of the respective clock signals cancels out one another. 
     If LSI manufacturing process variations are considered, in general, it is often to use different values between the delay time used for the setup conditions and that used for the hold conditions. This is done for the following reasons. In a setup conditional expression, the case of the setup time being longer has to be taken into account. In a hold conditional expression, the case of the minimum hold time has to be taken into account in view of the conditions under which the flip-flop circuit in the next stage propagates a signal at the highest rate. 
     Therefore, by attaching symbol “H” to the ends of the corresponding reference symbols of the respective parameters under the setup conditions related to delay time, it is indicated that the parameters are those for the hold conditions. The logical delay time and the output delay time indicating the delay of the output of the flip-flop circuit relative to the rise of the clock signal are denoted by LH and TPDH, respectively. In addition, clock skews are in some cases considered under different conditions, as well. Therefore, by attaching symbol “H” to the end of the reference symbols related to the clock skews for the setup conditions, respectively, it is indicated that the parameters are those for the hold conditions. 
     In expressions (1) to (4), a part of or all of the fixed factors such as layout dependent process variations are in some cases required to be considered in clock skew uncertain factor SKWET, if they cannot be accurately calculated or there are restrictions on a CAD (computer-aided design) tool. For example, if a certain constant value is used for the clock skew between arbitrary flip-flop circuits due to the restrictions on the CAD tool, it is required to set the fixed factors SKW 01  and SKW 02  of the clock skew to 0 and to contain the maximum clock skew in the uncertain factor SKWET of the clock skew. In contrast, if variations due to the power supply voltage change, temperature change or the like can be accurately calculated or controlled, a part of or all of clock skew uncertain factor SKWET and jitter JTR can be considered in each of clock skew fixed factors SKW 01  and SKW 02  in some cases. 
     The following is defined for the variations of the uncertain factor: 
     
       
         
           SKWET+JTR=MRG. 
         
       
     
     Under this definition, above-stated setup conditional expressions (1) and (2) are modified as follows: 
     
       
           L   01 ≦ TK−TPD   01 − SUP   02 + SKW   01 − MRG   (5); and 
       
     
     
       
           L   02 ≦ TK−TPD   02 − SUP   03 + SKW   02 − MRG   (6). 
       
     
     If only the maximum clock skew in an entire clock distribution system is considered for the clock skews, the clock skew maximum value is included in uncertain factor MRG, whereby setup conditional expressions (5) and (6) can be modified as follows: 
     
       
           L   01 ≦ TK−TPD   01 − SUP   02 − MRG   (7); and 
       
     
     
       
           L   02 ≦ TK−TPD   02 − SUP   03 − MRG   (8). 
       
     
     Conditional expressions (7) and (8) are normally used when a pipeline is designed using flip-flops. In conditional expressions (5) and (6), a clock skew is calculated for each clock signal propagation path individually and logic circuits are designed according to the respective individual calculated values. In conditional expressions (7) and (8), all the paths (pipeline stages) are designed according to the maximum clock skew. Therefore, there exists a path (pipeline stage) to which longer logic delay time L than the logic delay time of an actual logic circuit is allocated between certain flip-flops. 
     From expressions (5) and (6), the condition for logic delay time L 1 +L 2  between two pipeline stages is expressed as follows: 
     
       
           L   01 + L   02 ≦2 ·TK−TPD   01 − TPD   02 − SUP   02 − SUP   03 + SKW   01 + SKW   02 −2 ·MRG   (9). 
       
     
     If the clock skew fixed factor between flip-flop circuits FF 01  and FF 03  is defined as SKWA as shown in FIG. 9, this clock skew fixed factor SKWA can be regarded as the sum of the clock skew fixed factors of the respective pipeline stages. Namely, the following expression is defined: 
     
       
           SKW   01 + SKW   02 = SKWA.   
       
     
     If using this conditional expression, expression (9) can be modified as follows: 
     
       
           L   01 + L   02 ≦2 ·TK−TPD   01 − TPD   02 − SUP   02 − SUP   03 + SKWA− 2 ·MRG   (10) 
       
     
     
       
         ≦2 ·TK−TPD   01 − TPD   02 − SUP   02 − SUP   03 + SKWA− 2·( SKWET+JTR).   
       
     
     If the average delay time till the output of a flip-flop from the clock input of the flip flop is defined as Tpd and the average setup time of the flip-flops is defined as Sup, then the average value of the permissible maximum logic delay time between the two pipeline stages can be considered as follows: 
     
       
           L   01 + L   02 =2 ·TK− 2 Tpd− 2 ·Sup+SKW− 2 ·MRG   (11). 
       
     
     FIG. 13 is a schematic diagram showing the configuration of a three-stage pipeline using flip-flops. In FIG. 13, the three-stage pipeline includes flip-flop circuits FF 11  to FF 14  which transfer signals applied thereto synchronously with clock signals CLK 11  to CLK 14 , respectively, a logic circuit LG 11  which performs a logic processing on the signal/data received from flip-flop circuit FF 11  and transfers the resultant signal/data to flip-flop circuit FF 12 , a logic circuit LG 12  which performs a logic processing on the signal/data received from flip-flop circuit FF 12  and transfers the resultant signal/data to flip-flop circuit FF 13 , and a logic circuit LG 13  which performs a logic processing on the signal/data received from flip-flop circuit FF 13  and transfers the resultant signal/data to flip-flop circuit FF 14 . 
     For flip-flop circuit FF 11 , output delay time TPD 11 , setup time SUP 11 , and hold time HLD 11  are defined. For flip-flop circuit FF 12 , output delay time TPD 12 , setup time SUP 12 , and hold time HLD 12  are defined. For flip-flop circuit FF 13 , output delay time TPD 13 , setup time SUP 13 , and hold time HLD 13  are defined. For flip-flop circuit FF 14 , output delay time TPD 14 , setup time SUP 14 , and hold time HLD 14  are defined. 
     For clock signals CLK 11  to CLK 14  applied to flip-flop circuits FF 11  to FF 14 , respectively, uncertain factor MRG of the clock skew is defined. 
     Clock skew fixed factor SKW 11  exists between clock signals CLK 12  and CLK 11 , clock skew fixed factor SKW 12  exists between clock signals CLK 12  and CLK 13 , and clock skew fixed factor SKW 13  exists between clock signals CLK 13  and CLK 14 . Clock skew fixed factor SKWA exists between clock signals CLK 14  and CLK 11  to flip-flop circuits FF 14  and FF 11 , respectively. 
     In the three-stage pipeline shown in FIG. 13, if logic circuits LG 11 , LG 12  and LG 13  have logic delay time L 11 , L 12  and L 13 , respectively, logic delay time L 11  to L 13  is required to satisfy the following setup conditional expressions and the following hold conditional expressions as in the case of the two-stage pipeline stated above. 
     
       
           L   11 ≦ TK−TPD   11 − SUP   12 − SKW   11 − MRG   (12); 
       
     
     
       
           L   12 ≦ TK−TPD   12 − SUP   13 − SKW   12 − MRG   (13); 
       
     
     
       
           L   13 ≦ TK−TPD   13 − SUP   14 − SKW   13 − MRG   (14); 
       
     
     
       
           LH   11 ≧ HLD   12 − TPDH   11 + SKWH   11 + SKWETH   (15); 
       
     
     
       
           LH   12 ≧ HLD   13 − TPDH   12 + SKWH   12 + SKWETH   (16); and 
       
     
     
       
           LH   13 ≧ HLD   14 − TPDH   13 + SKWH   13 + SKWETH   (17). 
       
     
     In expressions (15) to (17), the logic delay times of logic circuits LG 11  to LG 13  for the hold conditions are respectively denoted by reference symbols LH 11  to LH 13 . Likewise, the output delay times of flip-flop circuits for the hold conditions are denoted by reference symbols TPDH 11  to TPDH 13 , respectively. Likewise, as for the clock skew fixed factors, the clock skews for the hold conditions are denoted by reference symbols SKWH 11  to SKWH 13  and SKWETH, respectively. 
     In the above expressions, MRG is given by the sum of jitter JTR and clock skew uncertain factor SKWET as in the case of the two-stage pipeline. The reason why the jitter component is not considered in the hold conditional expressions is that a jitter similarly occurs to each clock signal and the jitters cancels out one another under the hold conditions as in the case of the two-stage pipeline. 
     In addition, clock skew fixed factor SKWA between flip-flop circuits FF 14  and FF 11  can be regarded as the sum of clock skew fixed factors SKW 11 , SKW 12  and SKW 13 . Therefore, from expressions (12) to (14), the condition for logic delay time L 11 +L 12 +L 13  between the three pipeline stages is expressed as follows: 
     
       
           L   11 + L   12 + L   13 ≦3 ·TK−TPD   11 − TPD   12 − TPD   13 − SUP   12 − SUP   13 − SUP   14 − SKWA− 3 ·MRG   (18). 
       
     
     If the average delay time of the outputs of the flip-flops relative to input of the associated clock signals of the flip-flops is defined as Tpd and the average setup time of the flip-flops is defined as Sup, then the average permissible maximum logic delay time between the three pipeline stages can be regarded as follows: 
     
       
           L   11 + L   12 + L   13 =3 ·TK− 3· Tpd− 3 ·Sup+SKWA− 3 ·MRG   (19). 
       
     
     From conditional expressions (11) and (19), it is appreciated that if a pipeline is designed using flip-flops, it is necessary to consider output delay time Tpd, clock skew uncertain factor MRG and setup time Sup by as many as the number of pipeline stages included between arbitrary flip-flops. 
     With the improvement of the operating frequency of LSI, a clock cycle becomes shorter. In addition, with the high integration and miniaturization of transistors and interconnections, the influence of process variations becomes greater. Accordingly, the ratio of uncertain factors, such as skews and jitters, in the clock cycle increases. Further, as the operating frequency increases, it has become more difficult to improve delay time TPD of the output of a flip-flop from the clock input of the flip-flop and setup time SUP of the flip-flop. Therefore, the influence of output delay time TPD, clock skew uncertain factor MRG and setup time SUP on the logic delay time increases, thereby making it difficult to design a pipeline and making it impossible to optimally design a pipeline which operates at high speed. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a method of designing a semiconductor integrated circuit device allowing easy designing of a pipeline which operates at high speed. 
     It is another object of the present invention to provide a method of designing a pipeline, capable of decreasing the influence of the operating parameters, clock skews and the like of flip-flop circuits. 
     It is still another object of the present invention to provide a semiconductor integrated circuit device which includes a pipeline optimally designed to operate at high speed. 
     A method of designing a semiconductor integrated circuit device according to the present invention is a method of designing a semiconductor integrated circuit device which includes a pipeline including a plurality of flip-flop circuits each transferring a signal synchronously with a basic clock signal, and includes the steps of: designing the pipeline using the flip-flop circuits with the assumption that a cycle period of a transfer clock signal is given by a sum of a cycle of the basic clock signal and a gain time obtained by replacing a flip-flop circuit in the pipeline with latch circuits; setting the cycle period of the transfer clock signal to the cycle period of the basic clock signal to detect an error path in the designed pipeline; dividing the flip-flop circuit related to the error path into a plurality of latch circuits operating complementarily with each other and synchronously with the clock signal; and dividing a logic circuit related to the error path by the plurality of latch circuits such that a predetermined conditional inequality for signal propagation delay is satisfied for logic circuit stages related to the respective latch circuits, thereby rearranging the logic circuits. 
     A semiconductor integrated circuit device according to the first aspect of the present invention includes: a first flip-flop circuit transferring a received signal synchronously with a clock signal; a first latch circuit operating complementarily to the first flip-flop circuit and synchronously with the clock signal, and transferring and latching an applied signal; a first logic circuit arranged between the first flip-flop circuit and the first latch circuit, performing a logic processing on a signal applied from the first flip-flop circuit, and transferring the resultant signal to the first latch circuit; a second latch circuit operating complementarily to the first latch circuit and synchronously with the clock signal, and transferring and latching the applied signal; a second logic circuit arranged between the first latch circuit and the second latch circuit, performing a logic processing on the signal received from the first latch circuit, and transferring a resultant signal to the second latch circuit; a second flip-flop circuit operating complementarily to the second latch circuit and synchronously with the clock signal, and transferring the applied signal; and a third logic circuit arranged between the second latch circuit and the second flip-flop circuit, performing a logic processing on the signal from the second latch circuit, and transferring a resultant signal to the second flip-flop circuit. The first and second latch circuits and the first and second flip-flop circuits are arranged so as to satisfy the following conditions: 
     
       
           L   1 ≦ TK−TPDF   1 − SUPL   1 + SKW   1 − SKET−JTR   (1); 
       
     
     
       
           L   2 ≦ TK−TPDL   1 − SUPL   2 + SKW   2 − SKET−JTR   (2); 
       
     
     
       
           L   3 ≦ TK−TPDL   2 − SUPF   2 + SKW   3 − SKET−JTR   (3); 
       
     
     
       
           L   1 + L   2 ≦(1 +HDY )· TK−TPDF   1 − SUPL   2 + SKW   4 − SKET−JTR·K   1 − THR   1   (4); 
       
     
     
       
           L   2 + L   3 ≦(1 +LDY )· TK−TPDL   1 − SUPF   2 + SKW   5 − SKET−JTR·K   2 − THR   2   (5); 
       
     
     
       
           L   1 + L   2 + L   3 ≦2 ·TK−TPDF   1 − SUPF   2 + SKWA−SKET−JTR·K   3 − THR   1 − THR   2   (6); 
       
     
     
       
           L   1 ≧ HLDL   1 − TPDFH   1 + SKWH   1 + SKETH   (7); 
       
     
     
       
           L   2 ≧ HLDL   2 − TPDLH   1 + SKWH   2 + SKETH   (8); and 
       
     
     
       
           L   3 ≧ HLDF   2 − TPDLH   2 + SKWH   3 + SKWETH   (9). 
       
     
     In the above conditions, L 1 , L 2  and L 3  indicate logic delay time of the first, second and third logic circuits, respectively; TK indicates the cycle period of the basic clock signal; TPDF 1  indicates a delay of a signal output of the first flip-flop circuit from the clock signal; TPDL 1  and TPDL 2  indicate delays of output signals of the first and second latch circuits relative to the clock signal; SKW 1 , SKW 2  and SKW 3  indicate skews of the clock signal for a clock signal applied to the circuit at a preceding stage, respectively; SKW 4  indicates a skew of the clock signal applied to the second latch circuit for the clock signal applied to the first flip-flop circuit; SKW 5  indicates the skew of the clock signal applied to the first latch circuit for the clock signal applied to the second flip-flop circuit; and SKWA indicates the skew of the clock signal applied to the second flip-flop circuit for the clock signal applied to the first flip-flop circuit; SUPL 1 , SUPL 2  and SUPF 2  indicate setup time of the first latch circuit, setup time of the second latch circuit, and setup time of the third latch circuit, respectively. 
     SKET indicates a fixed skew of the clock signal; JTR indicates a jitter of the clock signal for the clock signal of the circuit at the preceding stage; THR 1  and THR 2  indicate signal propagation delay time of the first latch circuit and signal propagation delay time of the second latch circuit, respectively, relative to the respective input clock signals; HDY and LDY indicate duties of the latching periods of the clock signal applied to the first and second latch circuits, respectively; K 1 , K 2  and K 3  indicate coefficients representing cycle dependency of the jitter; HLDL 1  and HLDL 2  and HLDF 2  indicate hold time of the first latch circuit, the second latch circuit and the second flip-flop circuit for the clock signal, respectively; TPDFH 1 , TPDLH 1  and TPDLH 2  indicate delays of output signals of the first flip-flop circuit, the first latch circuit and the second latch circuit relative to the clock signal for the hold condition; SKWH 1 , SKWH 2  and SKWH 3  indicate skews of the clock signal for the clock signal applied to the circuit at the preceding stage for the hold condition; and SKETH indicates the fixed skew caused by the uncertain factor of the clock signal. 
     A semiconductor integrated circuit device according to the second aspect of the present invention includes: a first flip-flop circuit transferring an applied signal synchronously with a clock signal; a first logic circuit performing a logic processing on the signal from the first flip-flop circuit, and outputting the resultant signal; a first latch circuit operating complementarily to the first flip-flop circuit and synchronously with the clock signal, and transferring and latching an output signal of the first logic circuit; a second logic circuit performing the logic processing on the signal from the first latch circuit, and outputting the resultant signal; a second latch circuit operating complementarily to the first latch circuit and synchronously with the clock signal, and transferring and latching the output signal of the second logic circuit; a third logic circuit performing the logic processing on the output signal of the second latch circuit, and outputting the resultant signal; a third latch circuit operating complementarily to the second latch circuit and synchronously with the clock signal, and transferring and latching the output signal of the third logic circuit; a fourth logic circuit performing the logic processing on the output signal of the third latch circuit, and outputting the resultant signal; a fourth latch circuit operating complementarily to the third latch circuit and synchronously with the clock signal, and transferring and latching the output signal of the fourth logic circuit; a fifth logic circuit performing the logic processing on the output signal of the fourth latch circuit, and outputting the resultant signal; and a second flip-flop circuit operating in phase with the fourth latch circuit synchronously with the clock signal, and transferring the output signal of the fifth logic circuit. The logic delay time L 1  to L 5  of the first to fifth logic circuits, respectively, satisfy the following conditions: 
     
       
           L   1 ≦ TK−TPDF   1 − SUPL   1 + SKW   1 − MRG   (1); 
       
     
     
       
           L   2 ≦ TK−TPDL   1 − SUPL   2 + SKW   2 − MRG   (2); 
       
     
     
       
           L   3 ≦ TK−TPDL   2 − SUPL   3 + SKW   3 − MRG   (3); 
       
     
     
       
           L   4 ≦ TK−TPDL   3 − SUPL   4 + SKW   4 − MRG   (4); 
       
     
     
       
           L   5 ≦ TK−TPDL   4 − SUPF   2 + SKW   5 − MRG   (5); 
       
     
     
       
           L   1 + L   2 ≦(1 +HDY )· TK−TPDF   1 − SUPL   2 − SKW   21 − MRGJ   1 − THR   1   (6); 
       
     
     
       
           L   2 + L   3 ≦(1 +LDY )· TK−TPDL   1 − SUPL   3 − SKW   22 − MRGJ   2 − THR   2   (7); 
       
     
     
       
           L   3 + L   4 ≦(1 +HDY )· TK−TPDL   2 − SUPL   4 − SKW   23 − MRGJ   1 − THR   3   (8); 
       
     
     
       
           L   4 + L   5 ≦(1 +LDY )· TK−TPDL   3 − SUPF   2 − SKW   24 − MRGJ   2 − THR   4   (9); 
       
     
     
       
           L   1 + L   2 + L   3 ≦2 ·TK−TPDF   1 − SUPL   3 − SKW   31 − MRGJ   3 − THR   1 − THR   2   (10); 
       
     
     
       
           L   2 + L   3 + L   4 ≦2 ·TK−TPDL   1 − SUPL   4 − SKW   32 − MRGJ   3 − THR   2 − THR   3   (11); 
       
     
     
       
           L   3 + L   4 + L   5 ≦2 ·TK−TPDL   2 − SUPF   2 − SKW   33 − MRGJ   3 − THR   3 − THR   4   (12); 
       
     
     
       
           L   1 + L   2 + L   3 + L   4 ≦(2 +HDY )· TK−TPDF   1 − SUPL   4 − SKW   41 − MRGJ   4 − THR   1 − THR   2 − THR   3   (13); 
       
     
     
       
           L   2 + L   3 + L   4 + L   5 ≦(2 +LDY )· TK−TPDL   1 − SUPF   2 − SKW   42 − MRGJ   5 − THR   2 − THR   3 − THR   4   (14); 
       
     
     
       
           L   1 + L   2 + L   3 + L   4 + L   5 ≦3 ·TK−TPDF   1 − SUPF   2 − SKW   51 − MRGJ−THR   1 − THR   2 − THR   3 − THR   4   (15); 
       
     
     
       
           L   1 ≧ HLDL   1 − TPDFH   1 + SKWH   1 + MRGH   (16); 
       
     
     
       
           L   2 ≧ HLDL   2 − TPDLH   1 + SKWH   2 + MRGH   (17); 
       
     
     
       
           L   3 ≧ HLDL   3 − TPDLH   2 + SKWH   3 + MRGH   (18); 
       
     
     
       
           L   4 ≧ HLDL   4 − TPDLH   3 + SKWH   4 + MRGH   (19); and 
       
     
     
       
           L   5 ≧ HLDF   2 − TPDLH   4 + SKWH   5 + MRGH   (20). 
       
     
     In the above conditions, TK indicates the cycle period of the basic clock signal; TPDF 1  indicates a delay time of a signal output of the first flip-flop circuit relative the clock signal; TPDL 1  to TPDL 4  indicate delays of output signals of the first to fourth latch circuits relative to a trigger edge of the clock signal; SUPL 1  to SUPL 4  indicate setup time of the first to fourth latch circuits for the clock signal; SUPF 2  indicates the setup time of the second flip-flop circuit for the clock signal; SKW 1  to SKW 5  indicate skews of the clock signal for a clock signal applied to a circuit at the preceding stage; SKW 21  to SKW 24  indicate skews of clock signals for consecutive two stages of logic circuits of the first to fifth logic circuits; SKW 31  to SKW 33  indicate skews of clock signals for consecutive three stages of logic circuits of the first to fifth logic circuits; SKW 41  and SKW 42  indicate skews of clock signals of the first to fifth logic circuits for consecutive four stages of logic circuits; SKW 51  indicates the skew of the clock signal applied to the second flip-flop circuit for the clock signal applied to the first flip-flop circuit; THR 1  to THR 4  indicate signal propagation delay time of the first to fourth latch circuits; HDY indicates a duty of the clock signal in a latching period of each of the first and third latch circuit; LDY indicates the duty of the clock signal in the latching state of each of the second and fourth latch circuit; MRG indicates a margin of the clock signal for a component including a jitter; MRGJ 1  to MRGJ 5  indicate margins for the clock signal with cycle dependency of the jitter taken into account; HLDL 1  to HLDL 4  indicate hold time of the first to fourth latch circuits for the clock signal, respectively; HLDF 2  indicates the hold time of the second flip-flop circuit for the clock signal; TPDF 1  indicates the delay of the output signal of the first flip-flop circuit from the trigger edge of the clock signal for the hold condition; TPDLH 1  to TPDLH 4  indicate the delays of output signals of the first to fourth latch circuits relative to the trigger edge of the clock signal; SKWH 1  to SKWH 5  indicate the skews of the clock signal for the clock signal applied to the circuit at the preceding stage for the hold conditions; and MRGH indicates the margin for the clock signal for the hold conditions. 
     By replacing a flip-flop circuit by a pair of complementarily operating latch circuits, it is possible to replace the output delay time of the flip-flop circuit, clock skews and the like by the data through time of the latch circuits. It is thereby possible to set the permissible maximum logic delay time of the pipeline stage of interest longer and to mitigate the conditions on the arrangement of the logic circuits. 
     In addition, since the inequalities are used as the conditional expressions, it is possible to provide an allowance for the arrangement position of each latch circuit when arranging the latch circuits, resulting in easy division of the logic circuit. 
     Furthermore, by dividing the logic circuit by the latch circuits, a path having a margin in logic delay time is formed. Therefore, by rearranging the circuits on this path, it is possible to reduce a circuit area. 
     Moreover, by arranging such a pipeline in the semiconductor integrated circuit device, it is possible to achieve a semiconductor integrated circuit device which stably operates synchronously with a high-speed clock signal. 
     The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram showing the configuration of a two-stage pipeline according to the first embodiment of the present invention; 
     FIG. 2 is a diagram showing an example of the configuration of a low active latch circuit shown in FIG. 1; 
     FIG. 3 is a signal waveform diagram representing an operation of the low active latch circuit shown in FIG. 2; 
     FIG. 4 is a diagram showing one example of the configuration of a high active latch circuit shown in FIG. 1; 
     FIG. 5 is a signal waveform diagram representing an operation of the high active latch circuit shown in FIG. 4; 
     FIGS. 6A to  6 D are flow chart showing a pipeline designing flow according to the first embodiment of the present invention; 
     FIG. 7 is a schematic diagram showing the configuration of a three-stage pipeline according to the second embodiment of the present invention; 
     FIGS. 8A to  8 D are flow chart showing a pipeline designing flow in the second embodiment of the present invention; 
     FIG. 9 is a schematic diagram showing the configuration of a two-stage pipeline according to a flip-flop design; 
     FIG. 10 shows parameters shown in FIG. 9; 
     FIG. 11 is a schematic diagram showing the configuration of a clock distribution system for the pipeline; 
     FIG. 12 is a view showing the relationship between the logic delay time of the logic circuit of the two-stage pipeline and the parameters; and 
     FIG. 13 is a schematic diagram showing the configuration of a three-stage pipeline according to a flip-flop design. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     [First Embodiment] 
     FIG. 1 is a schematic diagram showing the configuration of a multiple-stage pipeline according to the first embodiment of the present invention. The multiple-stage pipeline shown in FIG. 1 is equivalent in configuration to the two-stage pipeline shown in FIG. 9, except that flip-flop circuit FF 02  is replaced by latch circuits LL 11  and LH 02 . According to this configuration, the configuration of logic circuits constituting the pipeline differs for different insertion positions of latch circuits LL 01  and LH 02 . A logic circuit LG 03  is arranged between flip-flop circuit FF 01  and latch circuit LL 01 . A logic circuit LG 04  is arranged between latch circuits LL 01  and LH 02 . A logic circuit LG 05  is arranged between latch circuit LH 02  and flip-flop circuit FF 03 . 
     Latch circuits LL 01  and LL 02  transfer/latch one or a plurality of signals/data synchronously with clock signals CLK 04  and CLK 05 , respectively, depending on the circuit configuration of the respective logic circuits. 
     Clock signals CLK 01  and CLK 03  are applied to flip-flop circuits FF 01  and FF 03 , respectively. Flip-flop circuits FF 01  and FF 03  output the applied signals synchronously with the rise of clock signals CLK 01  and CLK 03 , respectively. 
     Latch circuit LL 01  is a low active latch circuit. When a clock signal CLK 04  is at L level, latch circuit LL 01  turns into a through state in which latch circuit LL 01  allows the applied signal to pass. When clock signal CLK 04  is at H level, latch circuit LL 01  turns into a latching state to isolate the input and output thereof. 
     Latch circuit LH 02  is a high active latch circuit. When a clock signal CLK 05  is at H level, latch circuit LH 02  turns into the through state. When clock signal CLK 5  is at L level, latch circuit LH 02  turns into the latching state. 
     Output delay time TPD 01 , setup time SUP 01  and hold time HLD 01  are defined for flip-flop circuit FF 01 . Output delay time TPDL 01 , setup time SUPL 01  and hold time HLDL 01  are defined for latch circuit LL 01 . 
     Output delay time TPDL 02 , setup time SUPL 02  and hold time HLDL 02  are defined for latch circuit LH 02 . 
     Output delay time TPD 03 , setup time SUP 03  and hold time HLD 03  are defined for flip-flop circuit FF 03 . 
     For each of clock signals CLK 01 , CLK 03 , CLK 04  and CLK 05  applied to flip-flop circuits FF 01  and FF 03  and latch circuits LL 01  and LH 02 , respectively, clock skew uncertain factor MRG exists. 
     Logic circuits LG 03  to LG 05  have logic delay time L 03 , L 04  and L 05 , respectively. 
     FIG. 2 is a diagram showing an example of the configuration of low active latch circuit LL 01  shown in FIG.  1 . In FIG. 2, the configuration of a low active latch which transfers/latches one signal is shown. In low active latch circuit LL, the low active latch shown in FIG. 2 is arranged for each of the output signals/data of logic circuit LG 03  at the preceding stage. 
     In FIG. 2, low active latch circuit LL (LL 01 ) (low active latch) includes cascaded inverters  1  and  2  which receive clock signal CLK (CLK 04 ), a CMOS transmission gate  3  which is selectively rendered conductive in accordance with the signals at outputs A and B of inverters  1  and  2 , respectively and which allows a signal applied to an input D to pass when rendered conductive, an inverter  4  which receives the signal transferred through CMOS transmission gate  3 , an inverter  5  which inverts the output signal of inverter  4  for transmission to an output Q, an inverter  6  which inverts the output signal of inverter  4 , and a CMOS transmission gate  7  which is rendered conductive in response to the output signals of inverters  1  and  2  complementarily to CMOS transmission gate  3  and transferring the output signal of inverter  6  to the input of inverter  4  when rendered conductive. 
     In low active latch circuit (low active latch) LL, when clock signal CLK is at H level, the output signal of inverter  1  attains L level, the output signal of inverter  2  attains H level, CMOS transmission gate  3  turns into a nonconductive state and CMOS transmission gate  7  turns into a conductive state. In this state, inverters  4  and  6  constitute a latch circuit, low active latch circuit LL turns into a latching state and input D and output Q are disconnected from each other. 
     On the other hand, when clock signal CLK is at L level, the output signal of inverter  1  attains H level, the output signal of inverter  2  attains L level, CMOS transmission gate  3  turns into a conductive state and CMOS transmission gate  7  turns into a nonconductive state. Therefore, the signal applied to input D is transmitted to output Q through CMOS transmission gate  3  and inverters  4  and  5 , and low active latch circuit LL turns into a through state. 
     As shown in FIG. 3, low active latch circuit LL has setup time SUPL and hold time HLDL for the rising edge of clock signal CLK. On the other hand, output delay time TPDL of low active latch circuit LL is defined with respect to the falling edge of clock signal CLK. This is because the output delay time of the low active latch circuit indicates a response delay generated when the low active latch circuit changes from a latching state to a through state and the output signal of low active latch circuit LL changes. 
     As shown in FIG. 3, if the signal applied to input D changes when low active latch circuit LL is in a through state, the output Q of the low active latch circuit LL changes with a delay of propagation delay time (data though time) THR thereof. 
     FIG. 4 is a diagram showing an example of the configuration of high active latch circuit LH 02  shown in FIG.  1 . In FIG. 4, a high active latch circuit has a configuration of a high active latch arranged for one signal. The high active latch shown in FIG. 4 is arranged for each of the output signals/data of logic circuit LG 04  at the preceding stage. 
     In FIG. 4, high active latch circuit LH (LH 02 ) (high active latch) includes cascaded inverters  11  and  12  which receive clock signal CLK (CLK 05 ), a CMOS transmission gate  13  which is selectively rendered conductive in accordance with signals from outputs C and E of inverters  11  and  12 , respectively and allows a signal/data applied to input D to pass when rendered conductive, an inverter  14  which inverts the signal transferred through CMOS transfer gate  13 , an inverter  15  which inverts the output signal of inverter  14  for transmission to output Q, an inverter  16  which inverts the output signal of inverter  14 , and a CMOS transmission gate  17  which is rendered conductive in response to the output signals of inverters  11  and  12  complementarily to CMOS transmission gate  13 , for transmitting the output signal of inverter  16  to the input of inverter  14  when rendered conductive. 
     In high active latch circuit LH, when clock signal CLK is at L level, the output signal of inverter  11  attains H level, the output signal of inverter  12  attains L level, CMOS transmission gate  13  turns into a nonconductive state and CMOS transmission gate  17  turns into a conductive state. Accordingly, high active latch circuit LH turns into a latching state, in which input D and output Q are disconnected from each other. In this latching state, inverters  14  and  16  latch a signal/data. 
     When clock signal CLK is at H level, the output signal of inverter  11  attains L level, the output signal of inverter  12  attains H level, CMOS transmission gate  13  turns into a conductive state and CMOS transmission gate  17  turns into a nonconductive state. In this state, high active latch circuit LH turns into a through state in which the signal/data applied to input D is transferred to output Q. 
     In the high active latch circuit shown in FIG. 4, setup time SUPL and hold time HLDL are defined for the falling edge of clock signal CLK and output delay time TPDL is defined for the rising edge of clock signal CLK as shown in FIG.  5 . In addition, in high active latch circuit LH, propagation delay time (data through time) THR required until the signal applied to input D is transferred to output Q exists. 
     Referring back to FIG. 1, a clock skew fixed factor SKW 03  exists between the clock signal of flip-flop circuit FF 01  and that of latch circuit LL 01 . A clock skew fixed factor SKW 04  exists between the clock signals of latch circuits LL 01  and LH 02 . A clock skew fixed factor SKW 05  exists between the clock signal of latch circuit LH 02  and that of flip-flop circuit FF 03 . 
     In addition, a clock skew fixed factor SKW 06  exists between the clock signal of flip-flop circuit FF 01  and that of latch circuit LH 02 . A clock skew fixed factor SKW 07  exists between the clock signal of latch circuit LL 01  and that of flip-flop circuit FF 03 . 
     A clock skew fixed factor SKWA exists between the clock signals of flip-flop circuits FF 01  and FF 03 . 
     Since a clock jitter uncertain factor is considered to have cycle or period dependency, jitter JTR per one clock cycle is multiplied by a coefficient. 
     Under these conditions, logic delay time L 03  to L 05  of the respective logic circuits in the pipeline shown in FIG. 1 are required to satisfy the following setup conditional expressions (20) to (25) and hold conditional expressions (26) to (28). 
     
       
           L   03 ≦ TK−TPD   01 − SUPL   01 + SKW   03 − SKWET−JTR   (20); 
       
     
     
       
           L   04 ≦ TK−TPDL   01 − SUPL   02 + SKW   04 − SKWET−JTR   (21); 
       
     
     
       
           L   05 ≦ TK−TPDL   02 − SUP   03 + SKW   05 − SKWET−JTR   (22); 
       
     
     
       
           L   03 + L   04 ≦(1 +HDY )· TK−TPD   01 − SUPL   02 + SKW   06 − SKWET−JTR·K   01 − THR   01   (23); 
       
     
     
       
           L   04 + L   05 ≦(1 +LDY )· TK−TPDL   01 − SUP   03 + SKW   07 − SKWET−JTR·K   02 − THR   02   (24); 
       
     
     
       
           L   03 + L   04 + L   05 ≦2 ·TK−TPD   01 − SUP   03 + SKWA−SKWET−JTR·K   03 − THR   01 − THR   02   (25); 
       
     
     
       
           LH   03 ≧ HLDL   01 − TPDH   01 + SKWH   03 + SKWETH   (26); 
       
     
     
       
           LH   04 ≧ HLDL   02 − TPDLH   01 + SKWH   04 + SKWETH   (27); and 
       
     
     
       
           LH   05 ≧ HLD   03 − TPDLH   02 + SKWH   05 + SKWETH   (28). 
       
     
     In the above expressions, THR 01  and THR 02  indicate the data through time of latch circuit LL 01  and that of latch circuit LH 02 , respectively. For the hold conditions, different parameter values are used and symbol “H” is attached to the ends of corresponding parameter symbols for the setup conditions, respectively. The same holds for the following description with respect to the parameter symbols for the setup conditions. Though different in symbols, the logic delay time of each of the logic circuits in an actually designed pipeline satisfies both the setup conditions and the hold conditions. 
     HDY and LDY indicate the ratios of the H-level period and L-level period of the clock signal to one cycle period of the clock signal, respectively. It is assumed that the relationship of HDY+LDY=1 holds. 
     The delay time (output delay time TPD) of the output of flip-flop circuit FF 01  relative to the clock input thereto can be considered to be equal to that used in the above-stated conditional expression (10) for the following reason. Although logic circuits LG 01  and LG 03  differ in overall configuration, the configuration of the part of the circuit connected to flip-flop circuit FF 01  is the same as that shown in FIG.  9 . 
     In addition, the setup time of flip-flop circuit FF 03  does not significantly differ from that shown in FIG. 9 since the logical paths over several stages preceding this flip-flop circuit FF 03  are equal to those in FIG.  9 . Accordingly, in conditional expressions (20) to (25), the same values are used for output delay time TPD 01  and setup time SUP 03  as those used in conditional expression (10). 
     A clock jitter or the like changes according to the change of the cycle period of the clock signal. Normally, a jitter in a one-cycle time period is greater than that over a two-cycle time period. In this way, it may be considered that a jitter value becomes greater as the clock cycle period of interest is longer (the number of logic paths between the associated clock signals increases). Therefore, coefficients K 01  to K 03  indicating the cycle period dependencies of the clock jitter uncertain factor are normally not less than 1 and coefficient K 03  often takes a value greater than the values of coefficients K 01  and K 02 . 
     HDY and LDY indicate duties of the H-level period and L-level period of clock signal CLK, respectively. If the values of duties HDY and LDY cannot be accurately calculated or controlled, it is necessary to include these duties HDY and LDY in clock skew uncertain factor SKWET. 
     Further, to be strict, data through time THR 02  in conditional expression (25) differs in value from that in conditional expression (24). However, since logic paths over several stages preceding high active latch circuit LH 02  are the same for the both conditions, the data through time is considered not to significantly differ between both the conditions and the same value is used for both the conditions. 
     Furthermore, to be strict, the values of logic delay time L 03  to L 05  used in conditional expressions (20) to (25) differ. However, for the same reason, they are considered not to significantly differ and the same values are used for the respective logic delay time L 03  to L 05  in conditional expressions (20) to (25). 
     If reference is made to conditional expressions (26) to (28) which represent the hold conditions, it is appreciated that they are equivalent to conditional expressions (3) and (4) for the hold conditions set in designing a pipeline with only flip-flops, and that the number of conditional expressions simply increases by one. 
     If a clock jitter is assumed to have no cycle period dependency, the following condition can be considered to hold: coefficients K 01 =K 02 =K 03 =1. Under this assumption, if it is defined that SKWET+JTR=MRG as in the case of the flip-flop design, then setup conditional expressions (20) to (25) can be modified as follows: 
     
       
           L   03 ≦ TK−TPDL   01 − SUPL   01 + SKW   03 − MRG   (29); 
       
     
     
       
           L   04 ≦ TK−TPDL   01 − SUPL   02 + SKW   04 − MRG   (30); 
       
     
     
       
           L   05 ≦ TK−TPDL   02 − SUP   03 + SKW   05 − MRG   (31); 
       
     
     
       
           L   03 + L   04 ≦(1 +HDY )· TK−TPD   01 − SUPL   02 + SKW   06 − MRG−THR   01   (32); 
       
     
     
       
           L   04 + L   05 ≦(1 +LDY )· TK−TPDL   01 − SUP   03 + SKW   07 − MRG−THR   02   (33); and 
       
     
     
       
           L   03 + L   04 + L   05 ≦2 ·TK−TPD   01 − SUP   03 + SKWA−MRG−THR   01 − THR   02   (34). 
       
     
     The average delay time of the outputs of flip-flops relative to the clock input of the corresponding flip-flops, the average setup time of the flip-flops, and the average data through time of latch circuits LL 01  and LH 02  are defined as Tpd, Sup and Thr, respectively. The average permissible maximum logic delay time in the two-stage pipeline configuration is expressed as follows: 
     
       
           L   03 + L   04 + L   05 =2 ·TK−Tpd−Sup+SKWA−MRG− 2· Thr   (35). 
       
     
     As shown in FIG. 1, if a pipeline is designed using latch circuits, data Tpd, MRG and Sup need to be considered only once in the pipeline of two stages. That is, by constituting logic circuits using latch circuits with penalty of data though time Thr corresponding to the number of these latch circuits, it is possible to partially cancel data Tpd, MRG and Sup. However, it should be noted that even if conditional expressions (29) to (34) are all satisfied, the maximum delay time in expression (34) or (35) may not be effectively used in some case, depending on the conditions of logic delay times L 03  to L 05 . 
     The right sides of conditional expressions (10) and (34) each represent the permissible maximum logic delay time in two-stage pipeline. It is seen that if the difference between the right sides of conditional expressions (10) and (34) is obtained, the pipeline configuration in which the latch circuits are used is advantageous in delay time by the value of the following MRTP 2 ·2: 
     
       
           MRTP   2 ·2 =TPD   02 + SUP   02 + MRG−THR   01 − THR   02   (36). 
       
     
     Accordingly, if the values of data through time THR 01  and THR 02  of the latch circuits are sufficiently small, the value of conditional expression (36) becomes positive and the pipeline design using the latch circuits is advantageous over that using only flip-flop circuits in terms of delay time. 
     MRTP 2 ·2 in conditional expression (36) indicates the gain of the two-stage pipeline. A gain MRTP 2  of one stage pipeline is expressed as follows: 
     
       
           MRTP   2 =(½)·( TPD   02 + SUP   02 + MRG−THR   01 − THR   02 )  (37). 
       
     
     In addition, if the difference between the right sides of conditional expressions (11) and (35) is obtained to be reduced into a gain in a one-stage pipeline, then the permissible maximum delay time of the pipeline design using the latch circuits can be increased by the following value: 
     
       
           MRTP   2 =(½)·( Tpd+Sup+MRG− 2 ·Thr )  (38). 
       
     
     If the condition of MRG&gt;&gt;Tpd+Sup−2·Thr is satisfied, conditional expression (38) can be further simplified and the pipeline design using the latch circuits is advantageous by the following value: 
     
       
           MRTP   2 =(½)· MRG   (39). 
       
     
     If the cycle period dependency of the uncertain factors of the clock skew and the clock jitter are considered, it is necessary to obtain the difference between the right sides of conditional expressions (10) and (25). In this case, it is seen that if the difference is reduced into to the gain of one stage pipeline, the pipeline design using the latch circuits is advantageous by the following value: 
     
       
           MRTP   2 =(½)·{ Tpd+Sup+SKWET +(2− K   3 )· JTR− 2 ·Thr}   (40). 
       
     
     If the values of conditional expressions (37) to (40) which indicate a gain in latch design are greater, the logic delay time can be made longer by making use of the advantage of the latch design. Therefore, by designing a pipeline using latch circuits in accordance with the following designing flow, the pipeline can be easily designed. 
     Step 01: Design a pipeline using flip-flops with the clock cycle period assumed being “TK+MRTP 2 ”. 
     Step 02: Detect a critical path on which a setup error occurs for a target clock cycle period TK. 
     Step 03: Divide one flip-flop related to an error path into a low active latch circuit and a high active latch circuit. If the flip-flop circuit is a rising edge type circuit, the low active latch circuit is arranged at a preceding stage and the high active latch circuit is arranged at a subsequent stage. Conversely, if the flip-flop circuit is a falling edge circuit, the high active latch circuit is arranged at a preceding stage and the low active latch circuit is arranged at a subsequent stage. 
     Step 04: Move the logic circuit of the error path partially or entirely to a location between the latches so as to satisfy conditional expressions (20) to (28) or (29) to (34). 
     FIGS. 6A to  6 D are diagrams showing latch design procedures for the two-stage pipeline according to the first embodiment. Referring to FIGS. 6A to  6 D, the latch design procedures for the two-stage pipeline will be described. 
     As shown in FIG. 6A, in step 01, one cycle period of the clock signal is set to TK+MRTP 2  and a pipeline having a necessary number of stages is formed using flip-flop circuits. To eventually constitute the pipeline using latch circuits, clock cycle period TK+MRTP 2  accounting for latch gain MRTP 2 , rather than target clock cycle TK, is used. It is ideal to calculate gain MRTP 2  using the most accurate conditional expression (40). However, if it is difficult to actually apply conditional expression (40) to the flip-flop design due to restrictions by the use of an existing logic configuring or synthesis tool, the reduction of logic design time and others, then any one of conditional expressions (37) to (39) can be used. 
     In FIG. 6A, flip-flop circuits FFA to FFD are arranged, a logic circuit LGA is arranged between flip-flop circuits FFA and FFB, a logic circuit LGB is arranged between flip-flop circuits FFB and FFC and a logic circuit LGC is arranged between flip-flop circuits FFC and FFD. 
     Next, as shown in FIG. 6B, in step 02, the clock cycle period is returned to normal cycle period TK and an error path on which an error occurs (for the setup conditions) is detected. The reason for detecting a path on which an error occurs for the setup conditions is as follows. The logic circuits are so arranged as to satisfy the hold and setup conditions under the state that the clock signal cycle period is long. If the clock signal cycle period is set to a target cycle period, the hold conditions are satisfied. Therefore, it is unnecessary to detect an error for the hold conditions and error path detection time is thereby reduced. 
     In FIG. 6B, logic circuit LGB is detected as the error path. To detect this error path, a calculation method using a logic configuring or synthesis tool, a method of performing the calculation in the back annotation for extracting inductance, capacitance, resistance and the others to calculate delay time, or other method can be used. 
     The flip-flop circuit related to the error path is replaced by a low active latch circuit and a high active latch circuit. If any of the flip-flop circuits at the preceding stage and the subsequent stage of this error path can be divided into latch circuits, the flip-flop circuit to be divided is determined according to the delay conditions of the preceding path and the subsequent path. If this flip-flop circuit to be divided is a rising edge type flip-flop circuit, low active latch circuit LL is arranged at the preceding stage and high active latch circuit LH is arranged in the subsequent stage. In FIG. 6C, flip-flop circuit FFC in the rear of the error path is replaced by a low active latch circuit LLA and a high active latch circuit LHA. 
     Next, as shown in FIG. 6D, in step  04 , logic circuits LGB and LGC related to the error path are divided into three logic circuits LGKA, LGKB and LGKC in accordance with conditional expressions (26) to (28) for the hold conditions and conditional expressions (20) to (25) or (29) to (34) for the setup conditions, as latch design conditional expressions. As a result of this division, logic circuit LGKA is arranged between flip-flop circuit FFB and low active latch circuit LLA, logic circuit LGKB is arranged between latch circuits LLA and LHA, and logic circuit LGKC is arranged between high active latch circuit LHA and flip-flop circuit FFB. 
     A two-clock period 2·TK is allocated to the path from flip-flop circuits FFB to FFD. 
     For the pipeline stages constituted of logic circuits LGKA to LGKC, gain MRTP 2 ·2 in the maximum logic delay time can be obtained compared with a case of using flip-flop circuits. That is, it is possible to increase the logic delay time that can be inserted into one pipeline stage. The increase MRTP 2  of the permissible logic delay time makes it possible to improve delay convergence time and to expect the reduction of the design time period accordingly. It is also possible to incorporate a more complicated logic into each pipeline stage. 
     Furthermore, because of the increased allowable logic delay time, the number of paths each having a margin for the actual delay time increases. On such a path, a logic improvement such as the adjustment of a transistor size or the change of a 2-input AND gate into a 4-input AND gate can be made, thereby making it possible to reduce the area of the logic circuit. 
     Moreover, since inequalities are used as the conditional expressions for the logic delay time of the logic circuits, it is possible to provide a margin on a position of inserting a latch circuit. Compared with a case of uniquely determining a latch circuit insertion position, it is possible to easily achieve a logic circuit division and the optimization of divided logic circuits. 
     [Second Embodiment] 
     FIG. 7 is a schematic diagram showing the configuration of a pipeline according to the second embodiment of the present invention. The pipeline shown in FIG. 7 is equivalent to the three-stage pipeline shown in FIG. 13, with flip-flop circuit FF 12  replaced by latch circuits LL 15  and LH 16 , and with flip-flop circuit FF 13  replaced by latch circuits LL 17  and LH 18 . Latch circuits LL 15  and LL 17  are low active latch circuits, and latch circuits LH 16  and LH 18  are high active latch circuits. By dividing a flip-flop circuit into latch circuits, a logic circuit is also divided by the latch circuits. 
     A logic circuit LG 14  is arranged between a flip-flop circuit FF 11  and a low active latch circuit LL 15 , and a logic circuit LG 15  is arranged between latch circuits LL 15  and LH 16 . A logic circuit LG 16  is arranged between latch circuits LH 16  and LL 17 , and a logic circuit LG 17  is arranged between latch circuits LL 17  and LH 18 . A logic circuit LG 18  is arranged between high active latch circuit LH 18  and a flip-flop circuit FF 14 . Logic circuits LG 14  to LG 18  have logic delay time L 14  to L 18 , respectively. 
     Flip-flop circuits FF 11  and FF 14  each take in and output received signals at the rising edge of corresponding clock signals. Therefore, a low active latch circuit LL which turns into a through state when the corresponding clock signal is at L level and a high active latch circuit which turns into a through state when the corresponding clock signal is at H level, are alternately arranged in this order. 
     For flip-flop circuit FF 11 , output delay time TPD 11 , setup time SUP 11  and hold time HLD 11  are defined. 
     For low active latch circuit LL 15 , output delay time TPDL 15 , setup time SUPL 15  and data through time THR  15  and hold time HLDL 15  are defined. 
     For high active latch circuit LH 16 , output delay time TPDL 16 , setup time SUPL 16  and data through time THR  16  and hold time HLDL 16  are defined. 
     For low active latch circuit LL 17 , output delay time TPDL 17 , setup time SUPL 17  and data through time THR  17  and hold time HLDL 17  are defined. 
     For high active latch circuit LH 18 , output delay time TPDL 18 , setup time SUPL 18  and data through time THL  18  and hold time HLDL 18  are defined. 
     For flip-flop circuit FF 14 , output delay time TPD 14 , setup time SUP 14  and hold time HLD 14  are defined. 
     Clock signals CLK 11  and CLK 14  are applied to flip-flop circuits FF 11  and FF 14 , respectively. Clock signals CLK 15 , CLK 16 , CLK 17  and CLK 18  are applied to latch circuits LL 15 , LH 16 , LL 17  and LH 18 , respectively. 
     A clock skew fixed factor SKW 14  exists between the clock signals of latch circuit LL 15  and flip-flop circuit FF 11 . A clock skew fixed factor SKW 15  exists between the clock signals of latch circuits LL 15  and LH 16 . A clock skew fixed factor SKW 16  exists between the clock signals of latch circuits LH 16  and LL 17 . A clock skew fixed factor SKW 17  exists between the clock signals of latch circuits LL 17  and LH 18 . A clock skew fixed factor SKW 18  exists between the clock signals of latch circuit LH 18  and flip-flop circuit FF 14 . 
     A clock skew fixed factor SKW 19  exists between the clock signals of flip-flop circuit FF 11  latch circuit LH 16 . A clock skew fixed factor SKW 21  exists between the clock signals of latch circuits LH 16  and LH 18 . A clock skew fixed factor SKW 20  exists between the clock signals of latch circuits LL 15  and LL 17 . A clock skew fixed factor SKW 22  exists between the clock signals of latch circuit LL 17  and flip-flop circuit FF 14 . 
     A clock skew fixed factor SKW 23  exists between the clock signals of latch circuit LL 17  and flip-flop circuit FF 11 . A clock skew fixed factor SKW 24  exists between the clock signals of latch circuits LL 15  and LH 18 . A clock skew fixed factor SKW 25  exists between the clock signals of flip-flop circuit FF 14  and latch circuit LH 16 . 
     A clock skew fixed factor SKW 26  exists between the clock signals of latch circuit LH 18  and flip-flop circuit FF 11 . A clock skew fixed factor SKW 27  exists between the clock signals of flip-flop circuit FF 14  and latch circuit LL 15 . A clock skew fixed factor SKA exists between the clock signals of flip-flop circuits FF 14  and FF 15 . 
     Further, for the clock signals to flip-flop circuits FF 11  and FF 14  and latch circuits LL 15 , LH 16 , LL 17  and LH 18 , clock skew uncertain factor MRG including a jitter exists. 
     This clock jitter uncertain factor is assumed to have no cycle period dependency and is defined as JTR+SKWET=MRG. If a clock jitter has cycle period dependency, it is taken into account as in the case of the two-stage pipeline. 
     It is assumed that logic circuits LG 15  to LG 18  have logic delay time L 14  to L 18 , respectively and that the logics of the three-stage pipeline between flip-flop circuits FF 11  and FF 14  are exactly the same as those of the pipeline according to the flip-flop design shown in FIG. 13, then logic delay time LL 14  to LL 18  are required to satisfy the following conditional expressions (41) to (51) for setup conditions and conditional expressions (56) to (60) for hold conditions: 
     
       
           L   14 ≦ TK−TPD   11 − SUPL   15 − SKW   14 − MRG   (41); 
       
     
     
       
           L   15 ≦ TK−TPDL   15 − SUPL   16 − SKW   15 − MRG   (42); 
       
     
     
       
           L   16 ≦ TK−TPDL   16 − SUPL   17 − SKW   16 − MRG   (43); 
       
     
     
       
           L   17 ≦ TK−TPDL   17 − SUPL   18 − SKW   17 − MRG   (44); 
       
     
     
       
           L   18 ≦ TK−TPDL   18 − SUP   14 − SKW   18 − MRG   (45); 
       
     
     
       
           L   14 + L   15 ≦(1 +HDY )· TK−TPD   11 − SUPL   16 − SKW   19 − MRG   1 (= MRG )− THR   15   (46); 
       
     
     
       
           L   15 + L   16 ≦(1 +LDY )· TK−TPDL   15 − SUPL   17 − SKW   20 − MRG   2 (= MRG )− THR   16   (47); 
       
     
     
       
           L   16 + L   17 ≦(1 +HDY )· TK−TPDL   16 − SUPL   18 − SKW   21 − MRG   1 (= MRG )− THR   17   (48); 
       
     
     
       
           L   17 + L   18 ≦(1 +LDY )· TK−TPDL   17 − SUP   14 − SKW   22 − MRG   2 (= MRG )− THR   18   (49); 
       
     
     
       
           L   14 + L   15 + L   16 ≦2 ·TK−TPD   11 − SUPL   17 − SKW   23 − MRG   3 (= MRG )− THR   15 − THR   16   (50); 
       
     
     
       
           L   15 + L   16 + L   17 ≦2 ·TK−TPDL   15 − SUPL   18 − SKW   24 − MRG   3 (= MRG )− THR   16 − THR   17   (51); 
       
     
     
       
           L   16 + L   17 + L   18 ≦2 ·TK−TPDL   16 − SUP   14 − SKW   25 − MRG   3 (= MRG )− THR   17 − THR   18   (52); 
       
     
     
       
           L   14 + L   15 + L   16 + L   17 ≦(2 +HDY )· TK−TPD   11 − SUPL   18 − SKW   26 − MRG   4 (= MRG )− THR   15 − THR   16 − THR   17   (53); 
       
     
     
       
           L   15 + L   16 + L   17 + L   18 ≦(2 +LDY )· TK−TPDL   15 − SUP   14 − SKW   27 − MRG   5 (= MRG )− THR   16 − THR   17 − THR   18   (54); 
       
     
     
       
           L   14 + L   15 + L   16 + L   17 + L   18 ≦3 ·TK−TPD   11 − SUP   14 − SKWA−MRG   6 (= MRG )− THR   15 − THR   16 − THR   17 − THR   18   (55); 
       
     
     
       
           LH   14 ≧ HLDL   15 − TPD   11 + SKWH   14 + SKWETH   (56); 
       
     
     
       
           LH   15 ≧ HLDL   16 − TPDL   15 + SKWH   15 + SKWETH   (57); 
       
     
     
       
           LH   16 ≧ HLDL   17 − TPDL   16 + SKWH   16 + SKWETH   (58); 
       
     
     
       
           LH   17 ≧ HLDL   18 − TPDL   17 + SKWH   17 + SKWETH   (59); and 
       
     
     
       
           LH   18 ≧ HLD   14 − TPDL   18 + SKWH   18 + SKWETH   (60); 
       
     
     In the above expressions, MRG 1  to MRG 5  are values obtained considering the cycle period dependency of a clock jitter. If the clock jitter has no cycle period dependency, MRG 1  to MRG 5  are all equal to MRG. 
     The average delay time of the outputs of flip-flops from the clock inputs of the flip-flops, the average setup time of the flip-flops, and the average data through time of latch circuits are defined as Tpd, Sup and Thr, respectively. Then, the average permissible maximum logic delay time in this three-stage pipeline is expressed from conditional expression (55) as follows: 
     
       
           L   14 + L   15 + L   16 + L   17 + L   18 =3 ·TK−Tpd−Sup+SKWA−MRG −4 ·Thr   (61). 
       
     
     Therefore, this conditional expression (61) indicates that if a pipeline is designed using latch circuits as shown in FIG. 7, parameters Tpd, MRG and Sup need to be considered only once in the three-stage pipeline. That is, by constituting circuits using latch circuits with the penalty of the sum of data though times THR corresponding to the number of these latch circuits, it is possible to partially cancel parameters Tpd, MRG and Sup. 
     The right sides of conditional expressions (18) and (55) indicate the permissible maximum logic delay time over three-stage pipeline. If the difference between the right sides of conditional expressions (18) and (55) is obtained and the differential value is reduced into the gain of one pipeline stage, then it is possible to lengthen the maximum delay time by using the latch circuits by the following value MRTP 3 : 
     
       
           MRTP   3 =(⅓)·( TPD   12 + TPD   13 + SUP   12 + SUP   13 +2 ·MRG−THR   15 − THR   16 − THR   17 − THR   18 )  (62). 
       
     
     If the difference between the right sides of conditional expressions (19) and (62) is obtained and the differential value is reduced into to the gain of one pipeline stage, then it is possible to lengthen the maximum delay time of the pipeline using the latch circuits by the following value: 
     
       
           MRTP   3 =(⅓)·(2 ·Tpd +2 ·Sup +2 ·MRG −4 ·Thr )  (63). 
       
     
     If the condition of 2·MRG&gt;&gt;2·Tpd+2·Sup−4·Thr holds, it is possible to further simplify conditional expression (63) and the pipeline design using the latch circuits is advantageous by the following value: 
     
       
           MRTP   3 = MRG ·⅔  (64). 
       
     
     If gain MRTP 3  in the pipeline design using the latch circuits is great, the logic delay time can be made longer by making use of the advantage of the latch design. Therefore, the three-stage pipeline can be manufactured in accordance with the following steps. 
     Step 11: Design the pipeline using flip-flop circuits with the clock cycle period being the sum of target clock cycle period TK and gain MRTP 3 . 
     Step 12: Detect a critical path on which a setup error occurs for a target clock cycle period TK. 
     Step 13: Divide each of two flip-flops related to an error path into a low active latch circuit and a high active latch circuit. 
     Step 14: Move the logic circuit of the error path to a location between the latches so as to satisfy conditional expressions (41) to (60). 
     FIGS. 8A to  8 D are schematic diagrams illustrating the latch design procedures for the pipeline according to the second embodiment of the present invention. Referring to FIGS. 8A to  8 D, the three-stage pipeline design procedures according to the second embodiment of the present invention will be described. 
     In FIG. 8A, as step  11 , first, the setup conditions and the hold conditions employed in normally constituting a pipeline utilizing flip-flops are used. To consider a latch design, however, the pipeline is designed using a clock cycle period “TK+MRTP 3 ” for accounting for latch gain MRTP 3 , rather than target clock cycle TK. For this gain MRTP 3 , any of conditional expressions (62) to (64) is employed. However, if a factor indicating the cycle period dependency of a clock jitter is considered, the expression for gain MRTP 3  becomes a complicated equation, as in constituting the two-stage pipeline. In FIG. 8A, logic circuits LGA to LGE are arranged in respective subsequent stages of flip-flop circuits FFA to FFE. The output of logic circuit LGE in the final stage is applied to a flip-flop circuit FFF. 
     Next, as shown in FIG. 8B, in step  12 , the cycle of the clock signal is set at target cycle period TK and a critical path on which a setup error occurs is detected as in the case of the first embodiment. In order to detect this error path, as in the case of the first embodiment, various means such as a calculation on a logic synthesis tool and a calculation in back annotation can be employed. In FIG. 8B, a state in which logic circuit LGC becomes an error path is shown by way of example. 
     Next, as shown in FIG. 8C, in step S 13 , two flip-flop circuits related to this critical path are selected. In selecting the two flip-flop circuits, following three cases can be considered. Namely, first, the two flip-flop circuits (FFB and FFC) at the preceding stage of the error path are selected. Secondly, the flip-flop circuit (FFC) on an error path starting point side and the flip-flop circuit (FFD) at the subsequent stage of the error path are selected. Thirdly, the flip-flop circuit (FFD) at the subsequent stage of the error path and the flip-flop circuit (FFB) in the further subsequent stage are selected. 
     If each of the flip-flop circuit under any conditions out of the above conditions can be divided into latch circuits, the two flip-flop circuits to be divided are determined according to conditions such as a delay time at the preceding stage and the delay of the subsequent stage. If the selected flip-flop circuits are rising edge type flip-flop circuits, each flip-flop circuit is divided such that a low active latch circuit is arranged at the preceding stage and a high active latch circuit is arranged at the subsequent stage. Conversely, if the selected flip-flop circuits are falling edge type flip-flop circuits, each flip-flop circuit is divided such that a high active latch circuit is arranged at the preceding stage and a low active latch circuit is arranged at the subsequent stage. In FIG. 8C, flip-flop circuits FFC and FFD at preceding and subsequent stages of this error path, respectively, are selected. Flip-flop circuit FFC is divided into a low active latch circuit LLA and a high active latch circuit LHA. Flip-flop circuit FFD is divided into a low active latch circuit LLB and a high active latch circuit LHB. 
     Next, referring to FIG. 8D, in step  14 , the logic circuits (LGB to LGD) in the three-stage pipeline are divided into five logic circuit sections in accordance with the latch design conditional expressions, i.e., conditional expressions (56) to (60) for the hold conditions and conditional expressions (41) to (55) for the setup conditions. In FIG. 8D, logic circuits LGB to LGD are divided into logic circuits LGKA to LGKE. Specifically, logic circuit LGKA is arranged between flip-flop circuit FFB and low active latch circuit LLA, logic circuit LGKB is arranged between latch circuits LLA and LHA, and logic circuit LGKC is arranged between latch circuits LHA and LLB. Logic circuit LGKD is arranged between latch circuits LLB and LHB. Logic circuit LGKE is arranged between latch circuit LHB and flip-flop circuit FFE. Flip-flop circuit FFB to flip-flop circuit FFE correspond to three pipeline stages and have a clock cycle period of 3·TK. 
     Accordingly, by using steps  11  to  14  in the flow for the latch design, it is possible to increase the logic delay time which can be inserted into one pipeline stage. The increase of the allowable logic delay time can reduce a design time period due to the improvement of delay convergence time. In addition, it is possible to incorporate a more complex logic circuit between the pipeline stages. Besides, since the number of paths sufficient in delay time increases, it is possible to reduce a circuit area by logic improvement as in the case of the first embodiment. 
     In addition, as in the case of the first embodiment, since inequalities are used as the conditional expressions for the logic delay time, it is possible to provide an allowance on—a position of arranging a latch circuit. It is possible to easily rearrange logic circuits by dividing flip-flop circuits and to optimize logic circuits after the division. 
     [General Configuration] 
     The latch designs in the two-stage pipeline and the three-stage pipeline have been described above. It is also possible to similarly consider the configuration of a pipeline having four or more stages and the mixture of the two-stage pipeline configuration and the three-stage pipeline configuration. It is noted, however, that if the number of pipeline stages increases, the delay gain of the latch design relative to that of the design using flip-flop circuits increases but the scale of the conditional expressions become greater and the design becomes complicated. Normally, if an N-stage pipeline is designed using latch circuits, a gain MRTPN per one pipeline stage is expressed as follows: 
     
       
           MRTPN=( 1 /N )·{( N −1) Tpd +( N −1) Sup +( N −1)· MRG −2·( N −1)· Thr}.   
       
     
     In addition, as an example of the ambiguity factors of the clock signal, clock skews and clock jitters have been described. However, by considering the other design factors and conditions, the same advantages can be obtained if these clock signal ambiguities can be expressed by the conditional expressions given so far or similar expressions. 
     Further, even if falling edge type flip-flop circuits for outputting signals/data synchronously with the fall of clock signals are employed as flip-flop circuits in place of the rising edge type flip-flop circuits for outputting signals/data at the rising edge of clock signals, the same advantages can be provided. 
     Furthermore, in the inequalities for the hold conditions, the logic delay time is denoted by the different reference symbol from that of the logic delay time for the setup conditions. However, as described in the first embodiment, the logic delay time of each logic circuit in an actually designed pipeline satisfies both the setup and hold conditions. 
     As stated so far, according to the present invention, the clock cycle period is set longer by a predetermined value and the logic circuits are arranged, and the flip-flop circuits related to an error path on which an error for the target clock cycle occurs are replaced by latch circuits to rearrange the logic circuits in the pipeline design using flip-flop circuits. It is, therefore, possible to increase the permissible maximum logic delay time of a logic path in a pipeline and to easily design a pipeline. 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.