Patent Publication Number: US-11641191-B2

Title: Ring oscillator circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of Italian Patent Application No. 102021000015647, filed on Jun. 15, 2021, which application is hereby incorporated herein by reference. 
     TECHNICAL FIELD 
     The description relates to oscillator circuits, in particular to ring oscillator circuits. 
     BACKGROUND 
     Ring oscillators are used in electronics in a wide range of applications. Ring oscillators may be used in digital circuits, for instance, to produce an internal clock reference signal (e.g., for a state machine or a central processing unit, CPU). Ring oscillators may also be used in analog circuits, for instance, to produce a time base (e.g., for a switched capacitor filter, a charge pump circuit, a sample-and-hold circuit, and the like). 
     Current starved ring oscillators are conventional ring oscillators that include a current limiter to control power consumption. 
     Amongst the advantages of current starved ring oscillators are high speed and/or low power consumption. Additionally, temperature compensation may be achieved in current starved ring oscillators by means of proper sizing, considering a single (e.g., fixed) oscillation frequency. 
     On the other hand, the drawbacks of current starved ring oscillators may include start/stop transients with uncontrolled frequency. Additionally, conventional current starved ring oscillators may be hard to tune (e.g., compensate) versus temperature for multiple oscillation frequencies. 
     Therefore, there is a need in the art to provide improved current starved ring oscillators that are easy to tune versus temperature. In particular, it may be desirable to provide improved current starved ring oscillators that are easy to tune versus temperature at different oscillation frequencies. Additionally, it may be desirable to provide improved current starved ring oscillators that can provide fast start/stop operation (e.g., with a reduced or virtually absent start/stop transient phase). 
     SUMMARY 
     Various embodiments provide ring oscillators. Various other embodiments provide an improved current starved ring oscillator. 
     In one or more embodiments, a ring oscillator may comprise a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node. The oscillator supply voltage node may be configured to provide an oscillator supply voltage. The ring oscillator may comprise a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage. The current generator circuit may be configured to inject a current into the oscillator supply voltage node. Each inverter stage may comprise a first low-side transistor and a second low-side transistor coupled in series between the reference voltage node and an output node of the respective inverter stage, and a first high-side transistor coupled between the oscillator supply voltage node and the output node of the respective inverter stage. The first low-side transistor and the first high-side transistor may have respective control terminals coupled to an input node of the respective inverter stage to receive therefrom a respective inverter control signal. The second low-side transistor may have a control terminal coupled to the oscillator supply voltage node to receive the oscillator supply voltage. The ring oscillator may further comprise a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node. The first bias control transistor may have a control terminal configured to receive an oscillator control signal indicative of whether the ring oscillator circuit is in an active operation state or in an inactive operation state, and the second bias control transistor may have a control terminal coupled to the oscillator supply voltage node to receive the oscillator supply voltage. The first bias control transistor may be configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative of the ring oscillator circuit being in an inactive operation state. 
     One or more embodiments may thus facilitate temperature compensation as well as fast start/stop operation of the ring oscillator, resulting in a reduced or virtually absent start/stop transient phase. 
     In one or more embodiments, the conductivity of the first low-side transistors operating in a conductive state may be higher than the conductivity of the respective second low-side transistors operating in a conductive state. 
     In one or more embodiments, a conductive channel of the first low-side transistors may be shorter than a conductive channel of the respective second low-side transistors. 
     In one or more embodiments, each inverter stage may comprise a second high-side transistor coupled in series to the first high-side transistor between the oscillator supply voltage node and the output node of the respective inverter stage. The second high-side transistor may have a control terminal coupled to the reference voltage node. 
     In one or more embodiments, the second high-side transistor of a last inverter stage in the chain of cascade-coupled inverter stages may have a control terminal configured to receive the oscillator control signal. 
     In one or more embodiments, the conductivity of the first high-side transistors and/or the second high-side transistors operating in a conductive state may be higher than the conductivity of the respective first low-side transistors operating in a conductive state and higher than the conductivity of the respective second low-side transistors operating in a conductive state. 
     In one or more embodiments, a conductive channel of the first high-side transistors and/or the second high-side transistors may be shorter than a conductive channel of the respective first low-side transistors and shorter than a conductive channel of the respective second low-side transistors. 
     In one or more embodiments, a ring oscillator circuit may comprise an output control transistor coupled between an output node of the ring oscillator circuit and the reference voltage node. The output control transistor may have a control terminal configured to receive the oscillator control signal, and may be configured to selectively couple the reference voltage node and the output node of the ring oscillator circuit in response to the oscillator control signal being indicative of the ring oscillator circuit being in an inactive operation state. 
     In one or more embodiments, each inverter stage may comprise a plurality of second low-side transistors arranged in parallel. The second low-side transistors arranged in parallel may have different conductivity values when operating in a conductive state. The second low-side transistors arranged in parallel may have respective control terminals selectively couplable to the oscillator supply voltage node as a function of respective frequency selection signals. The biasing circuit may include a plurality of second bias control transistors arranged in parallel. The second bias control transistors arranged in parallel may have different conductivity values when operating in a conductive state. The second bias control transistors arranged in parallel may have respective control terminals selectively couplable to the oscillator supply voltage node as a function of the respective frequency selection signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       One or more embodiments will now be described, by way of example only, with reference to the annexed figures. 
         FIG.  1    is a circuit diagram exemplary of a ring oscillator; 
         FIG.  2    is a circuit diagram exemplary of a portion of a ring oscillator; 
         FIG.  3    is a diagram exemplary of possible time behavior of signals in a balanced ring oscillator; 
         FIG.  4    is a diagram exemplary of possible time behavior of signals in an unbalanced ring oscillator; 
         FIG.  5    is a circuit diagram exemplary of a ring oscillator according to one or more embodiments of the present description; 
         FIG.  6    is a circuit diagram exemplary of a portion of a ring oscillator according to one or more embodiments of the present description; 
         FIG.  7    is a circuit diagram exemplary of an equivalent circuit of the low-side portion of an inverter stage of a ring oscillator according to one or more embodiments of the present description, during a discharge phase of the oscillation period; 
         FIG.  8    is a circuit diagram exemplary of an inverter stage of a ring oscillator according to one or more embodiments of the present description; and 
         FIG.  9    is a circuit diagram exemplary of a biasing circuit of a ring oscillator according to one or more embodiments of the present description. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured. 
     Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular configurations, structures, or characteristics may be combined in any adequate way in one or more embodiments. 
     The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments. 
     Throughout the figures annexed herein, unless the context indicates otherwise, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for the sake of brevity. 
     By way of introduction to the detailed description of exemplary embodiments, reference may first be made to  FIG.  1   , which is a circuit diagram exemplary of a current starved ring oscillator  10  (also referred to simply as ring oscillator in the present description, for the sake of brevity only). 
     A ring oscillator  10  comprises a chain of inverter stages  12 , e.g., five inverter stages  12   A ,  12   B ,  12   C ,  12   D ,  12   E  as exemplified in  FIG.  1   . Each inverter stage  12  comprises an input node and an output node, with the output node of each inverter stage in the chain coupled to the input node of a subsequent inverter stage in the chain. The output node of the last inverter stage of the chain (e.g.,  12   E ) is coupled to the input node of the first inverter stage of the chain (e.g.,  12   A ). The input (clock) signals CK received at the input nodes of the inverter stages are respectively designated herein as CK A , CK B , CK C , CK D , CK E . As exemplified in  FIG.  1   , each inverter stage is coupled between an oscillator supply voltage node  14  and a common reference voltage node  16 . The oscillator supply voltage node  14  may provide a common oscillator supply voltage V RO_SUPPLY , and the reference voltage node  16  may provide a common reference voltage V GND  (e.g., 0 V). Each inverter stage  12  may comprise a respective n-channel MOS transistor MN (e.g., MN A , MN B , MN C , MN D , MN E ) having a source terminal coupled to the reference voltage node  16  and a drain terminal coupled to the output node of the respective inverter stage, and a respective p-channel MOS transistor MP (e.g., MP A , MP B , MP C , MP D , MP E ) having a source terminal coupled to the oscillator supply voltage node  14  and a drain terminal coupled to the output node of the respective inverter stage. The gate terminals of the n-channel MOS transistors MN and of the p-channel MOS transistors MP may be coupled to the input nodes of the respective inverter stages. All the transistors MN may have their bulk terminal connected to the reference voltage node  16 , and all the transistors MP may have their bulk terminal connected to the oscillator supply voltage node  14 . 
     A capacitance C RO  may be coupled between the oscillator supply voltage node  14  and the common reference voltage node  16 . The person skilled in the art will understand that the capacitance C RO  can be either an intrinsic capacitance at node  14  or an external capacitance added on purpose to increase the capacitance value at node  14 , so as to improve the stability of the oscillator supply voltage V RO_SUPPLY . In one or more embodiments, the capacitance C RO  may be an external capacitor whose capacitance adds up to the intrinsic one. 
     The ring oscillator  10  may comprise a current generator  18  coupled between the oscillator supply voltage node  14  and a further supply voltage node  20  (e.g., a system supply voltage node) that provides a system supply voltage V DD , e.g., higher than the oscillator supply voltage V RO_SUPPLY . The current generator  18  may force a current I OSC  to flow (e.g., may inject a current I OSC ) into the oscillator supply voltage node  14 , thereby controlling (e.g., limiting) the value of the oscillator current I OSC . The oscillation swing (e.g., the maximum signal amplitude at the output node of the last inverter stage  12   E ) is limited to the oscillator supply voltage V RO_SUPPLY  at node  14 . The voltage level V RO_SUPPLY  in turn depends on the value of the current I OSC  and on the sizing of the inverter stages  12 . 
     In a ring oscillator  10  as exemplified in  FIG.  1   , the oscillation frequency depends on the voltage V RO_SUPPLY  at node  14  and on the capacitive load at the output node of each inverter stage  12 . The global oscillation period T OSC  is equal to n times the propagation delay T D  of each inverter stage (i.e., T OSC =n*T D ), n being the number of chained inverter stages  12  (e.g., in the case exemplified herein where the ring oscillator  10  comprises five inverter stages, T OSC =5*T D ). In a simplified model, the propagation delay T D  of each inverter stage  12  is equal to the sum of two components, i.e., the rising edge time T RE  and the falling edge time T FE : T D =T RE +T FE . 
     In a conventional current starved ring oscillator, providing satisfactory temperature compensation may rely on finding the correct tuning between different variables, leading to an unclear design procedure. For instance, given the oscillation frequency F OSC , the minimum system supply voltage V DD,min  (at node  20 ) and the power consumption level as target specifications, the available design parameters may include the value of the current I OSC  and/or the buffer sizing (e.g., sizing of the inverter stages  12 ). 
     Additionally, in a conventional current starved ring oscillator, (dynamic) tuning of the oscillation frequency F OSC  (e.g., to provide oscillation at multiple frequencies) may rely on varying the value of the current I OSC , thereby affecting the accuracy of the temperature compensation, which is usually obtained for a single working point (i.e., temperature compensation may be effective only for a single value of the oscillator current I OSC ). 
     Additionally, operation of a conventional current starved ring oscillator may include a start transient during which the oscillator operates at a frequency (initial frequency) not corresponding to the target frequency. In some applications, fast oscillator start/stop operation may be desirable (e.g., for use in charge pump circuits, or to generate timing phases for reading circuitry in a memory, and the like). A stabilization period can be requested after a stop or at start up to restart the oscillation. The oscillator can be started periodically (e.g., to refresh internal voltages such as the oscillator supply voltage V RO_SUPPLY ), but an additional oscillator may be required (e.g., a low consumption oscillator). 
     Operation of a ring oscillator  10  as exemplified in  FIG.  1    may be further understood with reference to  FIGS.  2 ,  3  and  4    discussed below. 
       FIG.  2    is a circuit diagram exemplary of a portion of the ring oscillator  10 , illustrating in particular the inverter stages  12   C ,  12   D  and the respective input signal CK C , intermediate signal CK D , and output signal CK E . Additionally,  FIG.  2    illustrates the capacitances C OSC,C  and C OSC,D  (e.g., intrinsic capacitances) at the output nodes of the inverter stages  12   C  and  12   D , which affect the propagation delay T D  of the inverter stages. It will be understood that  FIG.  2    refers to a portion of the ring oscillator  10  by way of example, and that similar operation may take place in other portions of the ring oscillator  10 . 
       FIG.  3    is a diagram exemplary of possible time behavior of signals CK C  (dotted line), CK D  (solid line) and CK E  (dash-and-dot line) in the ring oscillator  10  exemplified in  FIG.  2   , according to a first example where the p-channel MOS transistors MP and the n-channel MOS transistors MN in the inverter stages  12  are balanced (e.g., they have similar conductivity in the ON state). 
     During each of the (e.g., five) time slots T D =T RE +T FE , the amount of current sunk from the oscillator supply voltage node  14  is equal to I OSC , insofar as a current I OSC  is forced to flow into node  14  by the current generator  18 . Such a condition provides an equilibrium point in the oscillator supply voltage node  14 , with the oscillator supply voltage V RO_SUPPLY  comprised between the reference voltage of node  16  (e.g., 0 V) and the system supply voltage V DD  (e.g., 0 V&lt;V RO_SUPPLY &lt;V DD ). In such a case, the current driven by each p-channel MOS transistor MP can be computed as I P =C OSC *V RO_SUPPLY /T RE . 
     The average current sunk from the oscillator supply voltage node  14  during each “commutation interval” T D  can thus be computed as I P *T RE /T D =I OSC . 
     Therefore, as a result of an increase of the current I P , the rising edge time T RE  decreases provided that the commutation interval T D  remains the same; so, the falling edge time T FE  increases. 
       FIG.  4    is a diagram exemplary of possible time behavior of signals CK C  (dotted line), CK D  (solid line) and CK E  (dash-and-dot line) in the ring oscillator  10  exemplified in  FIG.  2   , according to a second example where the p-channel MOS transistors MP and the n-channel MOS transistors MN in the inverter stages  12  are unbalanced. In particular,  FIG.  4    is exemplary of a case where the p-channel MOS transistors MP are (much) faster than the re-channel MOS transistors MN. 
     In the case exemplified in  FIG.  4   , the rising edge time T RE  may amount to a short portion of the (overall) commutation interval T D . Such a condition can be approximated as if at least one n-channel MOS transistor is always conductive (i.e., in an ON state) in any phase of the oscillation. Given the above approximation, the n-channel MOS transistor should be polarized during the discharge phase to sink a current I N  equal to the current I OSC  forced to flow into the oscillator supply voltage node  14 , according to the following equations:
 
 I   N   *T   FE   /T   D   =I   OSC   →I   N   ≈I   OSC if T   RE   «T   FE  
 
     Therefore, unbalanced sizing of the p-channel MOS transistors and the n-channel MOS transistors of the inverter stages  12  (e.g., with the p-channel MOS transistors being much more conductive than the n-channel MOS transistors) may have one or more of the following implications:
         with V RO_SUPPLY &gt;0 the n-channel MOS transistors sink a constant current I N  equal to I OSC  during the conductive (e.g., ON) phase;   as a result of a short rising edge time T RE , the n-channel MOS transistors have their gate terminals biased to the oscillator supply voltage V RO_SUPPLY  during the respective falling edge time slot T FE  (e.g., constantly biased to V RO_SUPPLY );   the oscillator supply voltage V RO_SUPPLY  should be equal to the gate-source voltage V GS  needed to force through the n-channel MOS transistors the current I OSC  (e.g., on the drain terminal);   as a result of the size of the n-channel MOS transistors being such that the transistors operate at their null point at a current level I N ≈I OSC , the oscillator supply voltage V RO_SUPPLY  at node  14  may be compensated with respect to temperature variations.       

     In the context of the present description, the definition of “null point biasing” is based on the recognition that, for any n-channel MOS transistor, it is possible to define, as a function of the transistor size (e.g., width-to-length ratio W/L), a value of the drain current (I D ) where the gate-source voltage V GS  is constant with respect to temperature. In such a biasing point, the temperature derivatives of the threshold voltage (V TH ) of the n-channel MOS transistor and the overdrive voltage (V OD =V GS −V TH ) of the n-channel MOS transistor compensate each other so as to maintain constant the drain current, provided that the n-channel MOS transistor operates in saturation. 
     Therefore, in one or more embodiments, the p-channel MOS transistors being (much) faster than the n-channel MOS transistors, and the n-channel MOS transistors being biased at null point versus current I OSC  may result in the oscillator supply voltage V RO_SUPPLY  at node  14  being constant with respect to temperature variations (null point voltage of the n-channel MOS transistors), so that the oscillation will be constant with respect to temperature variations due to a constant oscillator supply voltage V RO_SUPPLY  and a constant oscillator current I OSC , as per the equations below: 
     
       
         
           
             
               
                 V 
                 
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                 V 
                 thn 
               
             
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                         2 
                       
                       
                         
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                     · 
                     
                       L 
                       W 
                     
                   
                   2 
                 
                 ~ 
                 Constant 
               
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               at 
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               Null 
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               Point 
             
           
         
       
       
         
           
             
               
                 T 
                 OSC 
               
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               N 
             
             · 
             
               
                 
                   C 
                   OSC 
                 
                 · 
                 
                   V 
                   
                     RO 
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                     _ 
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                     SUPPLY 
                   
                 
               
               
                 I 
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     Therefore, one or more embodiments may relate to a current starved ring oscillator  50  as exemplified in  FIG.  5   . 
     A ring oscillator  50  comprises a chain of inverter stages  52 , e.g., five inverter stages  52   A ,  52   B ,  52   C ,  52   D ,  52   E  as exemplified in  FIG.  5   . Each inverter stage  52  comprises an input node and an output node, with the output node of each inverter stage in the chain coupled to the input node of a subsequent inverter stage in the chain. The output node of the last inverter stage of the chain (e.g.,  52   E ) is coupled to the input node of the first inverter stage of the chain (e.g.,  52   A ). The input (clock) signals CK received at the input nodes of the inverter stages are respectively designated herein as CK A , CK B , CK C , CK D , CK E . As exemplified in  FIG.  5   , each inverter stage is coupled between an oscillator supply voltage node  54  and a common reference voltage node  56 . The oscillator supply voltage node  54  may provide a common oscillator supply voltage V RO_SUPPLY , and the reference voltage node  56  may provide a common reference voltage V GND  (e.g., 0 V). 
     Each inverter stage  52  may comprise two n-channel MOS transistors N L  (e.g., N LA , N LB , N LC , N LD , N LE ) and N F  (e.g., N FA , N FB , N FC , N FD , N FE ) arranged in series between the reference voltage node  56  and the output node of the inverter stage. For instance, transistors N F  may have their source terminals coupled to the reference voltage node  56  and their drain terminals coupled to the source terminals of the respective transistors N L . Transistors N L  may have their drain terminals coupled to the output nodes of the respective inverter stages. All the transistors N L  and N F  may have their bulk terminals connected to the reference voltage node  56 . The gate terminals of the transistors N F  may be coupled to the input nodes of the respective inverter stages. The gate terminals of the transistors N L  may be coupled to the oscillator supply voltage node  54  to receive the oscillator supply voltage V RO_SUPPLY . 
     Each inverter stage  52  may comprise a p-channel MOS transistor P F1  (e.g., P F1A , P F1B , P F1C , P F1D , P F1E ) having a source terminal coupled to the oscillator supply voltage node  54  and a drain terminal coupled to the output node of the inverter stage. All the transistors P F1  may have their bulk terminals connected to the oscillator supply voltage node  54 . The gate terminals of the transistors P F1  may be coupled to the input nodes of the respective inverter stages. 
     Optionally, each inverter stage  52  may comprise a further p-channel MOS transistor P F2  (e.g., P F2A , P F2B , P F2C , P F2D , P F2E ) arranged in series with the respective transistor P F1 . For instance, transistors P F1  may have their source terminals coupled to the oscillator supply voltage node  54  and their drain terminals coupled to the source terminals of the respective transistors P F2 . Transistors P F2  may have their drain terminals coupled to the output nodes of the respective inverter stages. All the transistors P F2  may have their bulk terminals connected to the oscillator supply voltage node  54 . The gate terminals of the transistors P F2  may be coupled to the reference voltage node  56  to receive the reference voltage V GND  (e.g., 0 V). Optionally, the gate terminal of the further transistor P F2  of the last inverter stage of the inverter chain (e.g., transistor P F2E  in the example of  FIG.  5   ) may be configured to receive a control signal StartP generated as discussed in the following. 
     In one or more embodiments, transistors N L  and N F  may have different dimensions, insofar as they are designed to play a different role in the switching activity of the inverter stages  52 . In particular, the channels of transistors N L  may have a width W N  and a length L L . The channels of transistors N F  may have the same width W N  and a different (e.g., shorter) length L S . Therefore, the low-side current flow line of each inverter stage  52  may comprise two n-channel MOS transistors, with a first resistive transistor N L  not oscillating and having a gate terminal biased constantly at V RO_SUPPLY , and a second highly conductive transistor N F  oscillating as driven by the respective signal CK. The second transistor N F  may be designed to have a low load for oscillation, thereby facilitating oscillation at a high frequency. 
     In one or more embodiments, transistors P F1  and P F2  may have the same dimensions, insofar as they are designed to play a similar role in the switching activity of the inverter stages  52 . In particular, the channels of transistors P F1  may have a width W P  and a length L min . The channels of transistors P F2  may have the same width W P  and the same length L min . 
     In one or more embodiments, the p-channel MOS transistors P F1  and P F2  may be designed to be (much) more conductive than the n-channel MOS transistors N L  and N F  when operated in the ON state, e.g., by selecting the length L min  to be (much) shorter than the lengths L L  and L S . Therefore, the ring oscillator  50  may be substantially unbalanced. 
     In one or more embodiments as exemplified in  FIG.  5   , a ring oscillator  50  may comprise a biasing circuit  500 . The basing circuit  500  may comprise a current generator  58  coupled between the oscillator supply voltage node  54  and a further supply voltage node  60  (e.g., a system supply voltage node) providing a system supply voltage V DD , e.g., higher than the oscillator supply voltage V RO_SUPPLY . The current generator  58  may force a current I OSC  to flow into the oscillator supply voltage node  54  by (e.g., the current generator  58  may inject a current I OSC  into node  54 ). 
     The biasing circuit  500  may comprise an input terminal  502  configured to receive a control signal StartOsc. The control signal StartOsc may be asserted (e.g., set to 1) when the ring oscillator is expected to produce an oscillating output voltage, and may be de-asserted (e.g., set to 0) when the ring oscillator is not expected to produce an oscillating output voltage. The biasing circuit  500  may comprise an inverter circuit  504  configured to receive the control signal StartOsc and to produce an output signal StartP that substantially corresponds to an inverted replica of the control signal StartOsc. The biasing circuit  500  may comprise two n-channel MOS transistors N LZ  and N FZ  arranged in series between the reference voltage node  56  and the oscillator supply voltage node  54 . For instance, transistor N FZ  may have a source terminal coupled to the reference voltage node  56  and a drain terminal coupled to the source terminal of transistor N LZ . Transistor N LZ  may have a drain terminal coupled to the oscillator supply voltage node  54 . Transistors N LZ  and N FZ  may have their bulk terminals connected to the reference voltage node  56 . The gate terminal of transistor N FZ  may be coupled to the output of the inverter circuit  504  to receive the control signal StartP. The gate terminal of transistor N LZ  may be coupled to the oscillator supply voltage node  54  to receive the oscillator supply voltage V RO_SUPPLY . Transistors N LZ  and N FZ  may be sized substantially as the pairs of transistors N L  and N F  in the inverter stages  52 . In particular, the channel of transistor N LZ  may have a width W N  and a length L L . The channel of transistor N FZ  may have the same width W N  and a different length L S . 
     The biasing circuit  500  may comprise a capacitance C RO  coupled between the oscillator supply voltage node  54  and the common reference voltage node  56 . As previously discussed, the capacitance C RO  can be either an intrinsic capacitance at node  54  or an external capacitance added on purpose to increase the capacitance value at node  54 , so as to improve the stability of the oscillator supply voltage V RO_SUPPLY . In one or more embodiments, the capacitance C RO  may be an external capacitor whose capacitance adds up to the intrinsic one. 
     In one or more embodiments, a ring oscillator  50  may further comprise an n-channel MOS transistor  62  having a selectively conductive channel arranged between the output node of the ring oscillator  50  (e.g., the output terminal of the last inverter stage, exemplified herein by the inverter stage  52   E ) and the reference voltage node  56 . For instance, transistor  62  may have a source terminal coupled to the reference voltage node  56  and a drain terminal coupled to the output node of the ring oscillator  50 . The bulk terminal of transistor  62  may be connected to the reference voltage node  56 . The gate terminal of transistor  62  may be coupled to the output node of the inverter circuit  504  to receive the control signal StartP. 
     Operation of a ring oscillator  50  as exemplified in  FIG.  5    may be further understood with reference to  FIGS.  6  and  7   .  FIG.  6    is a circuit diagram exemplary of a portion of a ring oscillator  50 , in particular exemplary of the inverter stages  52   B  and  52   C .  FIG.  7    is a circuit diagram exemplary of an equivalent representation of the low-side portion of the inverter stage  52   B  during a discharge phase of the respective oscillation period. 
     As exemplified in  FIG.  7   , during oscillation of the ring oscillator  50 , the gate terminals of the transistors N L  and N F  in the low-side portion of a certain inverter stage (e.g., the second inverter stage  52   B , purely by way of example) are biased at V RO_SUPPLY  during the respective discharge phase (i.e., when the high-side portion of the inverter is in a non-conductive state and the low-side portion of the inverter is in a conductive state), insofar as transistors NL are constantly biased at V RO_SUPPLY  and transistors NF receive a driving signal CK that switches between V GND  (e.g., 0 V) and V RO_SUPPLY . Polarization of the series arrangement of transistors N L  and N F  is equivalent to a constant biasing at I OSC  on an equivalent series transistor having length L EQ =L L +L S . The equivalent transistor may be biased in null point at I OSC , thereby providing temperature compensation of the oscillator supply voltage V RO_SUPPLY  at null point. 
     In one or more embodiments, the transistor N FZ  driven by signal StartP may be turned off during oscillation of the ring oscillator  50  (e.g., when StartOsc=1 and StartP=0) and may be turned on while the ring oscillator  50  is inactive (e.g., when StartOsc=0 and StartP=1) in order to keep the oscillator supply voltage V RO_SUPPLY  at node  54  close to oscillation operating value. By having the oscillator supply voltage V RO_SUPPLY  biased very close to the oscillation operating voltage before starting the oscillator  50 , the oscillations may rapidly reach a regime value upon activation of the ring oscillator  50 . This may facilitate reducing or even avoiding a transient (out-of-specification) phase at the start of the ring oscillator  50 . 
     In one or more embodiments, a high oscillation frequency (e.g., around 900 MHz) may be achieved resorting to a series arrangement of two n-channel MOS transistors in the low-side portion of the inverter stages  52 . In particular, a MOS transistor with a long channel (N L , having length L L ) does not switch and has a gate terminal constantly biased at V RO_SUPPLY , and a MOS transistor with a short channel (N F , having length L S ) switches under the control of a respective control signal CK, providing a low loading for oscillations at high frequencies. 
     Additionally, unbalanced sizing of the high-side p-channel MOS transistors and the low-side n-channel MOS transistors (e.g., with the p-channel transistors being more conductive than the n-channel transistors) may result in fast rising edges and slow falling edges of the signals CK. 
     One or more embodiments may thus provide a clear design procedure for the design of a ring oscillator  50 . In particular, the design procedure may set certain parameters of the ring oscillator  50  as target parameters. The target parameters may include a minimum system supply voltage V DD,min , an oscillation frequency F OSC , and/or a power consumption level (e.g., a value of the oscillator current I OSC ). Once set the parameters above, the design procedure may include selecting the size W/L (width to length ratio) of the equivalent n-channel MOS transistor for the low-side portions of the inverter stages in order to obtain a value of oscillator supply voltage V RO_SUPPLY  compatible with the minimum system supply voltage V DD,min  at the null biasing point of the equivalent n-channel MOS transistor. For instance, V RO_SUPPLY  may be selected to be approximately equal to V DD,min −0.1V to maintain the current generator  58  in saturation. The width to length ratio W/L of the equivalent n-channel MOS transistor may be selected such that V RO_SUPPLY  is the gate voltage at null point with current I OSC  flowing in the equivalent n-channel MOS transistor. At this stage, the length L S  of switching transistor N F  may be selected to be short enough to fulfill the capacitance target (C OSC ) to meet the desired oscillation frequency F OSC . The length L L  of non-switching transistor N L  may be selected to be equal to the difference in lengths, as L L =L−L S . As indicated in the equation below, the capacitance of the n-channel MOS transistor N F  may be selected to meet the desired oscillation frequency F OSC : 
     
       
         
           
             
               T 
               OSC 
             
             = 
             
               
                 
                   
                     1 
                     
                       F 
                       OSC 
                     
                   
                   ~ 
                   N 
                 
                 · 
                 
                   
                     
                       C 
                       OSC 
                     
                     · 
                     
                       V 
                       
                         RO 
                         ⁢ 
                         _ 
                         ⁢ 
                         SUPPLY 
                       
                     
                   
                   
                     I 
                     OSC 
                   
                 
               
               = 
               
                 N 
                 · 
                 
                   
                     ( 
                     
                       
                         C 
                         PMOS 
                       
                       + 
                       
                         
                           C 
                           NMOS 
                         
                         · 
                         
                           V 
                           
                             RO 
                             ⁢ 
                             _ 
                             ⁢ 
                             SUPPLY 
                           
                         
                       
                     
                   
                   
                     I 
                     OSC 
                   
                 
               
             
           
         
       
     
     In one or more embodiments as exemplified in  FIG.  8   , a ring oscillator  50  may be configured to provide operation at multiple (e.g., selectable) oscillation frequencies while preserving temperature compensation at any such frequency. 
     In particular,  FIG.  8    is a circuit diagram exemplary of a single inverter stage  52 ′ as possibly provided in a ring oscillator  50 . The person skilled in the art will understand that a single inverter stage  52 ′ is illustrated in  FIG.  8    for the sake of ease of illustration only, and that a ring oscillator  50  may comprise a chain of inverter stages  52 ′ as previously discussed with reference to  FIG.  5   . In one or more embodiments, the low-side portion of each inverter stage  52 ′ may comprise two (or more) resistive n-channel MOS transistors N L1 , N L2  arranged in parallel in the place of a single n-channel MOS transistor N L . The transistors N L1  and N L2  may have the same width W N  and different lengths L L1  and L L2 , respectively. 
     The gate terminal of each of the transistors N L1 , N L2  is configured to receive the voltage V RO_SUPPLY  via a respective selectively activatable buffer (e.g., inverter) circuit  80   1 ,  80   2 . For instance, the gate terminal of transistor N L1  may be coupled to the output node of an inverter  80   1  arranged between nodes  54  and  56 , which may receive a control signal F 1  at a respective input node  801 . The gate terminal of transistor N L2  may be coupled to the output node of an inverter  80   2  arranged between nodes  54  and  56 , which may receive a control signal F 2  at a respective input node  802 . Therefore, if F 1 =1 and F 2 =0 the inverter stage  52 ′ operates via the series arrangement of transistors N F  and N L2 , and if F 1 =0 and F 2 =1 the inverter stage  52 ′ operates via the series arrangement of transistors N F  and N L1 . Since transistors Nu, N L2  have different lengths and are designed to have null biasing point at different values of the current I OSC , then I OSC2 ≠I OSC1  and F OSC2 ≠F OSC1 . 
     In one or more embodiments as exemplified with reference to  FIG.  8   , the biasing circuit may be modified accordingly, providing two (or more) resistive n-channel MOS transistors N LZ1 , N LZ2  arranged in parallel in the place of a single n-channel MOS transistor N LZ .  FIG.  9    is a circuit diagram exemplary of such a modified biasing circuit  500 ′. The transistors N LZ1  and N LZ2  may have the same width W N  and different lengths L L1  and L L2 , respectively. 
     The gate terminal of each of the transistors N LZ1 , N LZ2  is configured to receive the voltage V RO_SUPPLY  via the respective selectively activatable buffer (or inverter) circuit  80   1 ,  80   2 . For instance, the gate terminal of transistor NN LZ1  may be coupled to the output node of inverter  80   1  and the gate terminal of transistor N LZ2  may be coupled to the output node of inverter  80   2 . 
     The person skilled in the art will understand that either signal F 1  or signal F 2  may assume a high logic value (e.g., 1) according to the selected oscillation frequency. In one or more embodiments, more than two resistive n-channel MOS transistors may be provided in parallel, so that more than two selectable oscillation frequencies may be provided. Additionally or alternatively, the oscillation frequency may be selected by operating a combination of such MOS transistors (e.g., depending on the combinations of logic values of the control signals F 1 , F 2 , . . . ). 
     One or more embodiments may thus provide one or more of the following advantages:
         a well-defined design method to obtain a good trade-off between oscillation frequency F OSC , power consumption, and minimum system supply voltage V DD,min ;   temperature compensation obtained by null point biasing of the low-side n-channel transistors;   possibility of tuning the oscillator circuit at more than one frequency while maintaining a temperature compensation; and   fast start/stop operation of the oscillator circuit without using additional circuitry (e.g., without using an additional oscillator) insofar as the oscillation frequency may be at regime when the oscillator starts, thereby avoiding the risk of out-of-spec frequency for logic blocks that receive the output signal from the oscillator circuit.       

     Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection. 
     The extent of protection is determined by the annexed claims. 
     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.