Patent Publication Number: US-10312804-B2

Title: Power supply apparatus with power factor correction using fixed on and off periods

Description:
CROSS-REFERENCE 
     This application is the US national stage of International Patent Application No. PCT/JP2016/053542 filed on Feb. 5, 2016. 
     TECHNICAL FIELD 
     The present invention relates to a power supply apparatus that supplies DC power to a load, and more particularly, to a power supply apparatus that can improve efficiency. 
     BACKGROUND 
     A conventional power supply apparatus that supplies DC power to a load is shown in Japanese Patent Application Laid-Open Publication No. H9-47024. A circuit diagram of the conventional power supply apparatus is shown in  FIG. 6 . The power supply apparatus  400  shown in  FIG. 6  is configured as a step-down AC-DC convertor having a full-wave rectifier circuit  410 , a low-pass filter  480 , a power supply circuit  430  for supplying DC power to a load  420 , and a control circuit  440  for controlling the power supply circuit  4300 . The full-wave rectifier circuit  4100  converts an AC voltage Vac of an AC power source  10  to a DC voltage (pulsating DC voltage) Vdc obtained by full-rectifying the AC voltage Vac. An N-type MOSFET is used as a switching element T 431  of the power supply circuit  430 . The power supply circuit  430  has a power factor correction (PFC) function for suppressing an amplitude of a harmonic current less than a limit value (referred to as “PFC Standard”). The control circuit  440  turns on the switching element T 431  in a fixed control period and turns off the switching element T 431  when a drain current of the switching element T 431  (voltage drop across a current detecting resistor R 431 ) becomes larger than a threshold value. 
     In the power supply apparatus  400  shown in  FIG. 6 , when the switching element T 431  is turned on, a current I 1  flows through a path formed by the full-wave rectifier circuit  410 , the low-pass filter  480 , an inductor L 431 , a parallel circuit consisting of the load  420  and a capacitor C 431 , the switching element T 431 , the current detecting resistor R 431 , and the earth (ground). At this time, electromagnetic energy is accumulated in the inductor L 431  (inductance L). When the switching element T 431  is turned off, a flywheel current I 3  caused by the electromagnetic energy accumulated in the inductor L 431  flows through a path formed by the inductor L 431 , the parallel circuit consisting of the load  420  and the capacitor C 431 , a diode D 431  (referred to as “flywheel diode”). 
     In the power supply apparatus  400  shown in  FIG. 6 , a magnitude (amplitude) of the current I 1  is variable in accordance with a magnitude (amplitude) of the DC voltage Vdc. Thus, a power factor cos θ of AC input power (θ: phase difference between AC voltage Vac and AC input current Iac) approaches “1”. 
     The current I 1  does not flow while the switching element T 431  is off. That is, the current I 1  intermittently flows. Therefore, harmonic currents are included in the current I 1 . A low-pass filter  480  is provided to prevent the harmonic currents from propagating to the AC power source side. 
     PRIOR ART DOCUMENT 
     Patent Document 
     Patent literature No. 1: Japanese Patent Application Laid-Open Publication No. H9-47024 
     SUMMARY OF THE INVENTION 
     The low-pass filter  480  provided in the above-described conventional power supply apparatus  400  is composed of a capacitors having a small capacitance and an inductors having a large inductance in order to prevent a reduction of the power factor. In general, to increase the inductance of an inductor, a larger number of turns of the wire forming the inductor is required. Since the size of an inductor becomes large if the inductor is formed using a thick wire, it is necessary to form the inductor using a thin wire in order to minimize the size of the inductor. But, if the inductor is formed using a thin wire, the resistance of the inductor increases, thereby increasing inductor losses. 
     Thus, there is a limit to improving the efficiency of the above-described conventional power supply apparatus owing to losses from the inductor comprising the low-pass filter that prevents harmonic currents from flowing. 
     Further, the above-described conventional power supply apparatus  400  includes the current detecting resistor R 431  for detecting the drain current of the switching element T 431  and is configured such that the switching element T 431  is turned off when the voltage drop across the current detecting resistor R 431  (drain current of the switching element T 431 ) becomes larger than the threshold value. Therefore, the control circuit is complicated and the cost of the power supply apparatus is relatively high. 
     It is therefore one object of the present teachings to disclose a power supply apparatus that can improve efficiency with a simple structure and at a low cost. 
     A power supply apparatus according to a first aspect of the present invention comprises a first DC power source that generates a DC voltage obtained by rectifying an AC voltage between a positive electrode and a negative electrode, a power supply circuit arranged between the first DC power source and a load, and a control circuit for controlling the power supply circuit. 
     Preferably, a DC power source having a rectifier circuit that converts the AC voltage to the DC voltage (pulsating DC voltage) obtained by rectifying the AC voltage is used as the first DC power source. Typically, a full-wave rectifier circuit is used as the rectifier circuit. The terms “positive electrode” and “negative electrode” are used as terms that mean portions where the DC voltage is generated. 
     The power supply circuit has first and second capacitors, first and second inductors, a diode, and a first switching element. 
     The control circuitry is configured to turn on the first switching element during a fixed on-period Mon and turns off the first switching element during a fixed off-period Moff (=M−Mon) in each fixed control period M. For example, the control circuit controls the first switching element in synchronization with the clock signal that is H-level (or L-level) during a first period Ka equal to the on-period Mon and is L-level (or H-level) during a second period Kb equal to the off-period Moff in each clock signal period M equal to the control period M. 
     The power supply apparatus is configured such that when the first switching element is turned on, a discharging current caused by electric charge accumulated in the second capacitor flows through a path formed by the first inductor, a parallel circuit consisting of the first capacitor and the load, and the first switching element. Further, the power supply apparatus is configured such that when the first switching element is turned off, a flywheel current caused by an electromagnetic energy, that is accumulated in the first inductor while the first switching element is on, flows through a path formed by the parallel circuit consisting of the first capacitor and the load and the diode, and at the same time, a charging current is supplied from the first DC power source to the second capacitor via the second inductor. 
     Moreover, the power supply apparatus is configured such that the charging current continues to flow while the first switching element is off. For example, inductance of the second inductor, capacitance of the second capacitor, and the off-period Moff of the first switching element are set appropriately. 
     In the first aspect, since the current is continuously supplied from the DC power source during the control period M, harmonic components included in the current can be significantly suppressed. Thus, a power factor of an AC input power can be improved, and harmonic currents can be prevented from propagating to an AC power source side. Therefore, it is possible to remove the low-pass filter used in the conventional power supply apparatus, and thereby to downsize the power supply apparatus and improve efficiency. Further, parts and processes for detecting the current flowing through the first switching element are not required. Thus, it is possible to simplify a configuration. Moreover, since the low-pass filter and the parts for detecting the current are not required, it is possible to construct the power supply apparatus at low cost. 
     A power supply apparatus according to a second aspect of the present invention, similar to the first concept, comprises a first DC power source, a power supply circuit, and a control circuit. In the second aspect, the power supply circuit different from the power supply apparatus of the first aspect is used. That is, the power supply circuit of the first aspect is configured as a buck converter, while the power supply circuit of the second aspect is configured as a buck-boost converter. 
     The power supply circuit of the second aspect, similar to the power supply circuit of the first aspect, has first and second capacitors, first and second inductors, a diode, and a first switching element. 
     In the second aspect, the power supply apparatus is configured such that when the first switching element is turned on, a discharging current caused by electric charge accumulated in the second capacitor flows through a path formed by the first inductor and the first switching element. Further, the power supply apparatus is configured such that when the first switching element is turned off, a flywheel current caused by an electromagnetic energy, that is accumulated in the first inductor while the first switching element is on, flows through a path formed by the diode and a parallel circuit consisting of the first capacitor and a load, and at the same time, a charging current is supplied from the first DC power source to the second capacitor via the second inductor. 
     Moreover, similar to the first aspect, the power supply apparatus is configured such that the charging current continues to flow while the first switching is off. 
     The power supply apparatus according to the second aspect can achieve the same effect as the power supply apparatus according to the first aspect. 
     In a modification of the power supply apparatus according to the first or the second aspect, the control period M, L 2  representing inductance of the second inductor, and Cp representing capacitance of the second capacitor are set such that [M&lt;π×(L 2 ×Cp) 1/2 ] is satisfied. 
     In this modification, the power supply apparatus can be easily configured such that the current is continuously supplied from the DC power source during the control period M. 
     In a different modification of the power supply apparatus according to the first or the second aspect, the power supply apparatus is configured such that the flywheel current disappears within a period when the switching element is off. For example, the off-period Moff of the switching element is set appropriately. 
     In this modification, it is possible to prevent a reduction of efficiency and a disturbance of a current waveform that are caused by turning on the switching element at a time when the flywheel current is flowing. 
     In a different modification of the power supply apparatus according to the first or the second aspect, the control circuit has a second DC power source that generates a predetermined DC voltage between a first terminal and a second terminal and an on-period setting circuit that sets the on-period Mon of the switching element. Since the control period M is fixed, when the on-period Mon is set, the off-period Moff (=M−Mon) is also set. 
     The on-period setting circuit has first and second P-type MOSFETs, first and second N-type MOSFETs, first to third resistors, a third capacitor, and a second switching element. 
     Between the first terminal and the second terminal of the second DC power source, the first P-type MOSFET, the first resistor, the first N-type MOSFET, and the second resistor are arranged in series. A gate and a drain each of the first P-type MOSFET and the first N-type MOSFET are short-circuited. Thus, this series circuit constitutes a constant current circuit. 
     Further, between the first terminal and the second terminal of the second DC power source, the second P-type MOSFET, the second N-type MOSFET, and the third resistor are arranged in series. A gate of the second P-type MOSFET is connected to the gate of the first P-type MOSFET and a gate of the second N-type MOSFET is connected to the gate of the first N-type MOSFET. The third capacitor and the second switching element are arranged in parallel with the third resistor. 
     In this modification, a ratio of a channel width of the first P-type MOSFET to that of the second P-type MOSFET, a ratio of a channel width of the first N-type MOSFET to that of the second N-type MOSFET, and a ratio of resistance of the second resistor to that of the third resistor (ratio of resistance values) are set such that when the second switching element is on, a voltage between terminals (drain-source voltage) of the second P-type MOSFET is larger than a voltage between terminals of the second N-type MOSFET, and when the second switching element is off and the third capacitor is fully charged, the voltage between terminals of the second P-type MOSFET is smaller than the voltage between terminals of the second N-type MOSFET. Further, the second switching element is turned off at a start time of the control period M. The on-period setting circuit sets a period, that is from the start time of the control period M to a time when the voltage between terminals of the second P-type MOSFET becomes smaller than the voltage between terminals of the second N-type MOSFET, as the on-period Mon. 
     In this modification, it is possible to easily adjust a length of the on-period Mon of the switching element. 
     In another modification of the power supply apparatus according to the first or the second aspect, a third DC power source that generates a predetermined DC voltage between the positive electrode and the negative electrode is used instead of the first DC power source that generates the DC voltage obtained by rectifying the AC voltage between the positive electrode and the negative electrode. Preferably, a battery is used as the third DC power source. 
     In this modification, it is possible to suppress generation of harmonic components, and to provide a step-down DC-DC converter that is not necessary to detect a current flowing through the first switching element. 
     The power supply apparatus of the present invention can improve efficiency with a simple structure at a low cost. 
     Other features, effects and advantages of the present invention will be readily understood with reference to the specification, claims and accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram showing a first embodiment of the power supply apparatus of the present invention. 
         FIG. 2  is a circuit diagram showing a second embodiment of the power supply apparatus of the present invention. 
         FIG. 3  is a chart showing simulated waveforms of the first embodiment. 
         FIG. 4  is the enlarged view of the part IV in  FIG. 3   
         FIG. 5  is a circuit diagram showing a third embodiment of the power supply apparatus of the present invention. 
         FIG. 6  is a circuit diagram showing a conventional power supply apparatus. 
     
    
    
     DETAILED DESCRIPTION 
     The following detailed description is merely intended to teach a person skilled in the art detailed information for practicing preferred application examples of the present invention. The technical scope of the present invention is not limited by the detailed description, but is defined by the description of the claims. Therefore, combinations of features and steps within the following detailed description may not be necessary to practice the present invention in the broadest sense, and are merely intended to teach some representative examples of the present invention in the detailed description which is given with reference numerals included in the accompanying drawings. 
     Hereinafter, preferred embodiments of the present invention will be explained with reference to the drawings. 
     In the following description, a power supply apparatus of the present invention is configured as a step-down AC-DC converter that comprises a full-wave rectifier circuit for converting an AC voltage to a DC voltage and supplies DC power to a load having light emitting diodes (LEDs). Of course, the power supply apparatus of the present invention can be configured to supply DC power to various loads other than LEDs. 
     Furthermore, unless otherwise specified, the terms “voltage” and “current” are used as terms meaning respectively “magnitude of the voltage” and “magnitude of the current”. 
     First Embodiment 
       FIG. 1  is a circuit diagram showing a first embodiment  100  of the power supply apparatus of the present invention. The power supply apparatus  100  of the first embodiment comprises a full-wave rectifier circuit  110  that converts an AC voltage Vac from an AC power source  10  to a DC voltage Vdc, a power supply circuit  130 , a control circuit  140 , a power circuit  160 , and a drive signal output circuit  170 . 
     The full-wave rectifier circuit  110  has diodes D 111 -D 114  that are bridge-connected and generates the DC voltage Vdc, that is obtained by full-wave rectifying the AC voltage Vac applied between AC input terminals a and b, between a positive electrode c and a negative electrode d. The DC voltage Vdc is a pulsating DC voltage having a magnitude (amplitude) that varies in accordance with a magnitude (amplitude) of the AC voltage Vac. 
     In this embodiment, the negative electrode d of the full-wave rectifier circuit  110  is grounded. Therefore, grounding any one of terminals means that the terminal is connected to the negative electrode d. 
     In this embodiment, a full-wave rectifying circuit  110  is a representative example of “a first DC power source” of the present invention. 
     The power supply circuit  130  is arranged between the positive electrode c and the negative electrode d of the full-wave rectifier circuit  110  and between one terminal  131  and the other terminal  132  of the load  120 , and supplies DC power to the load  120 . 
     A configuration of the power supply circuit  130  will be explained. 
     A capacitor C 131  having capacitance C 1  is arranged between the one terminal  131  and the other terminal  132  of the load  120 . 
     An inductor L 131  having inductance L 1  and an inductor L 132  having inductance L 2  are arranged in series between the one terminal  131  of the load  120  and the positive electrode c. Here, the inductor L 131  is connected to the one terminal  131  and the inductor L 132  is connected to the positive electrode c. 
     A switching element T 131  is arranged between the other terminal  132  of the load  120  and the ground. In this embodiment, an N-type MOSFET is used as the switching element T 131 . 
     A capacitor C 132  having capacitance Cp is arranged between the ground and a connection point r where the inductor L 131  and the inductor L 132  are connected. 
     A diode (flywheel diode) D 131  is arranged between the other terminal  132  of the load  120  and the connection point r. Here, an anode of the diode D 131  is connected to the other terminal  132  and a cathode is connected to the connection point r. 
     A switching element T 131  is a representative example of “a first switching element” of the present invention, a capacitor C 131  is a representative example of “a first capacitor” of the present invention, a capacitor C 132  is a representative example of “a second capacitor” of the present invention, an inductor L 131  is a representative example of “a first inductor” of the present invention, and an inductor L 132  is a representative example of “a second inductor” of the present invention. 
     The power circuit  160  is arranged between the positive electrode c and the ground, and has a resistor R 161 , a Zener diode ZD 161 , and a capacitor C 161 . The power circuit  160  supplies a voltage Vzd determined by a Zener voltage of the Zener diode ZD 161  to the control circuit  140  and the drive signal output circuit  170 . 
     The drive signal output circuit  170  is arranged between a connection point (voltage Vzd) where the resistor R 161  and the Zener diode ZD 161  are connected and the ground, and has a switch SW 171 , resistors R 171  and R 172 . When the switch SW 171  is turned on, the drive signal output circuit  170  outputs a H-level drive signal, that instructs start of supplying DC power to the load  120 , to a clock signal generating circuit  141  of the control circuit  140 . 
     The control circuit  140  has the clock signal generating circuit  141  and a drive circuit  142 . 
     The clock signal generating circuit  141  outputs a clock signal to an input terminal of the drive circuit  142  when a H-level drive signal is input from the drive signal output circuit  170 . 
     The drive circuit  142  has switching elements T 142   a  and T 142   b  that are connected in series between the ground and the DC voltage Vzd generated by the power circuit  160 . In this embodiment, a P-type MOSFET is used as the switching element T 142   a  and an N-type MOSFET is used as the switching element T 142   b . A connection point (output terminal) where the switching elements T 142   a  and T 142   b  are connected is connected to a gate of the switching element T 131  of the power supply circuit  130 . The drive circuit  142  generates a drive voltage for turning on the switching element T 131  or a drive voltage for turning off the switching element T 131  to the output terminal based on the clock signal input to the input terminal. 
     In this embodiment, the clock signal generating circuit  141  generates a clock signal that becomes H-level during a first fixed period Ka and L-level during a second fixed period Kb (=M−Ka) in each fixed clock signal period M. 
     And, at the output terminal of the drive circuit  142 , H-level drive voltage for turning on the switching element T 131  is generated during the first period Ka when the clock signal is H-level, and L-level drive voltage for turning off the switching element T 131  is generated during the second period Kb when the clock signal is L-level. 
     In this embodiment, the switching element T 131  is turned on during a fixed on-period Mon (=first period Ka of the clock signal) and turned off during a fixed off-period Moff (=second period Kb of the clock signal) in each fixed control period M (=clock signal period M). That is, in this embodiment, the on-period Mon of T 131  is equal (including “substantially equal”) to the first period Ka of the clock signal and the off-period Moff of T 131  is equal (including “substantially equal”) to the second period Kb of the clock signal. 
     In this embodiment, any parts for detecting a current flowing through the switching element T 131  are not provided, and processes for detecting a current and comparing the current with a threshold value are not performed. 
     Next, an operation of the power supply apparatus  100  of this embodiment will be explained. 
     In the following, each element may be represented by only reference numeral. For example, the switching element T 131  being an N-type MOSFET may be represented by “T 131 ”. 
     When the switch SW 171  is turned off, L-level drive signal is output from the drive signal output circuit  170 . Accordingly, T 131  is kept off. When T 131  is off, a current I 1  (charging current of the capacitor C 132 ) flows through a path formed by the full-wave rectifier circuit  110  (DC voltage Vdc), the inductor L 132 , the capacitor C 132 , and the ground. 
     When the switch SW 171  is turned on in this state, H-level drive signal is output from the drive signal output circuit  170 . Accordingly, the clock signal generating circuit  141  starts to generate the clock signal. 
     The drive circuit  142  generates H-level drive voltage for turning on T 131  at the output terminal during the first period Ka when the clock signal is H-level. 
     When T 131  is turned on, a current I 2  (discharging current of the capacitor C 132 ), that is caused by electric charge accumulated in the capacitor C 132 , flows through a path formed by the capacitor C 132 , the inductor L 131 , a parallel circuit consisting of the load  120  and the capacitor C 131 , T 131 , and the ground. At this time, an electromagnetic energy [L 1 ×(I 2 ) 2 /2] is accumulated in the inductor L 131 . 
     When T 131  is on, the voltage at the point r becomes lower than Vdc due to discharging of the capacitor C 132 . As a result, even while T 131  is on, the current I 1  flows through the path formed by the full-wave rectifier circuit  110 , the inductor L 132 , the capacitor C 132 , and the ground. 
     Further, the drive circuit  142  generates L-level drive voltage for turning off T 131  at the output terminal during the second period Kb when the clock signal is L-level. 
     When T 131  is turned off, a current I 3  (flywheel current), that is caused by the electromagnetic energy accumulated in the inductor L 131 , flows through a path formed by the inductor L 131 , the parallel circuit consisting of the load  120  and the capacitor C 131 , and the diode D 131 . 
     At the same time, the current I 1  flows through the path formed by the full-wave rectifier circuit  110 , the inductor L 132 , the capacitor C 132 , and the ground. As a result, the electric charge that is discharged while T 131  is on is replenished to the capacitor C 132 . 
     In this embodiment, the clock signal period M, the inductance L 2  of the inductor L 132  and the capacitance Cp of the capacitor C 132  are set such that the current I 1  continues to flow while T 131  is off. It will be described in detail later. 
     As described above, the current I 1  flows even while T 131  is on. Further, the power supply apparatus  100  is configured such that the current I 1  continues to flow while T 131  is off. 
     Thus, the current I 1  continues to flow during one clock signal period M (=Ka+Kb), that is, during one control period M (=on-period Ma+off-period Mb). As a result, the current I 1  is obtained by adding a current component an amplitude of which is synchronized with the DC voltage (pulsating DC voltage) Vdc to a current component an amplitude of which varies with the control period M. 
     Here, a current obtained by adding the current I 1  to a current flowing through the power circuit  160  is equal to an absolute value of the AC input current Iac. Accordingly, continuing to flow the current I 1  even while T 131  is off means that the AC input current Iac continues to flow during one control period M (=one clock signal period M) of T 131 , and thereby it is possible to suppress generation of harmonic currents included in the AC current Iac. 
     Therefore, it is possible to remove the low-pass filter  480  used in the conventional power supply apparatus  400  shown in  FIG. 6 . As a result, it is possible to improve the efficiency of the power supply apparatus and also to significantly reduce a size of a product shape. 
     Next, each operation of the power supply apparatus  100  of this embodiment will be explained. Each waveform is shown in  FIGS. 3 and 4 . Each waveform shown in  FIGS. 3 and 4  will be described later. 
     First, charging and discharging operations of the capacitor C 132  are explained. 
     When T 131  is turned on, as described above, the current I 2  caused by discharging of the capacitor C 132  flows. Since a resistance value of a path through which the current I 2  flows is very small, an ultimate current value (saturated current value) of the current I 2  becomes very large and the current I 2  increases linearly immediately after the current I 2  starts to flow. 
     If VLED represents a voltage of the load  120  (load voltage) and VCp represents a voltage at a positive terminal of the capacitor C 132  (voltage at the point r), a voltage VL 1  across terminals of the inductor L 131  when T 131  is turned on is represented by equation (1). 
     
       
         
           
             
               
                 
                   
                     VL 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   = 
                   
                     
                       L 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                       × 
                       
                         
                           dI 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                         dt 
                       
                     
                     = 
                     
                       VCp 
                       - 
                       VLED 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     VCp decreases due to discharging of the capacitor C 132  during the on-period of T 131 . 
     VCp is greater than Vdc ([VCp&gt;Vdc]) at a time when T 131  is turned on, then decreases rapidly during the on-period of T 131 . VCp becomes equal to Vdc ([VCp=Vdc]) in the decreasing process. And VCp becomes smaller than Vdc ([VCp&lt;Vdc]) at a time when T 131  shifts from on to off. 
     Since a position where VCp is equal to Vdc ([VCp=Vdc]) is, as described below, at a midpoint of a variable range of VCp or near the midpoint, an average value of VCp in the on-period of T 131  can be approximated by Vdc. 
     By using this approximation, equation (1) can be rewritten to equation (2). 
     
       
         
           
             
               
                 
                   
                     
                       dI 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                     dt 
                   
                   ≈ 
                   
                     
                       Vdc 
                       - 
                       VLED 
                     
                     
                       L 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     That is, a rate of increase (increase slope) of I 2  is proportional to (Vdc−VLED) and is inversely proportional to L 1 . 
     Vdc can be considered constant in one control period M. Further, it is assumed that T 131  is turned on at a time [t=t 0 (=0)], I 2  is zero [I 2 =0] at the time [t=t 0 ]. Accordingly, I 2  is expressed by equation (3). 
     
       
         
           
             
               
                 
                   
                     I 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   ≈ 
                   
                     
                       
                         Vdc 
                         - 
                         VLED 
                       
                       
                         L 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     × 
                     t 
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     From equation (3), it can be understood that I 2  increases linearly with the rate of increase that is proportional to (Vdc−VLED) and inversely proportional to L 1 . 
     It is assumed that T 131  shifts from on to off a time [t=t 1 ], electric discharge quantity Q 1  that is discharged from the capacitor C 132  during the on-period Mon of T 131  is expressed by equation (4). In this case, since T 131  is turned on from the time [t=t 0 ] to the time [t=t 1 ], the on-period Mon is equal to t 1  [Mon=t 1 ]. Here, an initial value of the electric discharge quantity Q 1  is zero. 
     
       
         
           
             
               
                 
                   
                     
                       Q 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                     = 
                     
                       
                         
                           ∫ 
                           0 
                           
                             t 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                         ⁢ 
                         
                           I 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                           ⁢ 
                           dt 
                         
                       
                       = 
                       
                         
                           
                             Vdc 
                             - 
                             VLED 
                           
                           
                             2 
                             × 
                             L 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                         × 
                         t 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           1 
                           2 
                         
                       
                     
                   
                   ⁢ 
                   
                       
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     Since T 131  is on during the first period Ka when the clock signal is H-level, the on-period Mon of T 131  is fixed. Therefore, the electric discharge quantity Q 1  of the capacitor C 132  during the on-period Mon (=t 1 ) of T 131  is proportional to (Vdc−VLED). 
     From equation (4), the electric discharge quantity Q 1  is proportional to a square of the on-period Mon (=t 1 ) of T 131 . Accordingly, if the on-period Mon of T 131  varies, the electric discharge quantity Q 1  is significantly changed. Therefore, fixing the on-period Mon of T 131  makes an effect that a variation of the electric discharge quantity Q 1  can be prevented. 
     If it is assumed that Vdc is constant in one control period M, the electric charge quantity of the capacitor C 132  in the off-period Moff of T 131  is equal to the electric discharge quantity Q 1  of the capacitor C 132  in the on-period Mon (=t 1 ) of T 131 . 
     However, in practice, Vdc pulsates in a longer period than the control period M, and thereby Vdc slightly varies even in the control period M. If ΔVdc represents an amount of variation of Vdc (voltage difference) in one control period M of T 131 , ΔVdc becomes plus [ΔVdc&gt;0] in a increasing process of Vdc, and becomes zero [ΔVdc=0] when Vdc is a peak value, and becomes minus [ΔVdc&lt;0] in an decreasing process of Vdc. 
     In the increasing process of Vdc, an amount of electric charge (ΔVdc×Cp) is charged in the capacitor C 132 , and in the decreasing process of Vdc, an amount of electric charge (ΔVdc×Cp) is discharged from the capacitor C 132 . Accordingly, the electric charge quantity of the capacitor C 132  in one control period M of T 131  (hereinafter referred to as “Cp electric charge quantity”) is expressed by equation (5).
 
 Cp  electric charge quantity= Q 1+Δ Vdc×Cp   (5)
 
     If the capacitance Cp of C 132  is set such that (ΔVdc×Cp) is negligible small compared to Q 1  [(ΔVdc×Cp)«Q 1 ], the Cp electric charge quantity can be regarded as equal to the electric discharge quantity Q 1 . 
     The Cp electric charge quantity is supplied by the AC input current Iac. Therefore, if it is assumed that the Cp electric charge quantity is regarded as equal to the electric discharge quantity Q 1 , the AC input current Iac in the control period M is determined by the electric discharge quantity Q 1 . 
     If the electric discharge quantity Q 1  is proportional to (Vdc−VLED), the AC input current Iac is proportional to (Vac−VLED). That is, if it can be regarded that VLED is constant, the AC input current Iac is varies in synchronization with the variation of the AC voltage Vac. 
     Next, the flywheel current I 3  that flows when T 131  is turned off will be explained. 
     When T 131  is turned off, the drain voltage of T 131  is raised by a counter electromotive force generated in the inductor L 131 . Thus, the diode D 131  is forward biased, and thereby the flywheel current I 3  flows through the path formed by the inductor L 131 , the parallel circuit consisting of the load  120  and the capacitor C 131 , and the diode D 131 . When VD 1  represents a forward voltage drop of the diode D 131 ,  13  is expressed by equation (6). 
     
       
         
           
             
               
                 
                   
                     
                       L 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                       × 
                       
                         
                           dI 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           3 
                         
                         dt 
                       
                     
                     + 
                     VLED 
                     + 
                     
                       VD 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   = 
                   0 
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     T 131  is turned on at the time t 0  (=0) and turned off at the time t 1 . When I 3 ( t ) represents I 3  at the time t 1 , I 3  can be expressed by equation (7). 
     
       
         
           
             
               
                 
                   
                     I 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                   
                   = 
                   
                     
                       
                         - 
                         
                           
                             VLED 
                             + 
                             
                               VD 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                           
                             L 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                       
                       × 
                       
                         ( 
                         
                           t 
                           - 
                           
                             t 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                         ) 
                       
                     
                     + 
                     
                       I 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                       ⁢ 
                       
                         ( 
                         
                           t 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     Here, equation (8) is established. 
     
       
         
           
             
               
                 
                   
                     
                       I 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                       ⁢ 
                       
                         ( 
                         
                           t 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         ) 
                       
                     
                     = 
                     
                       I 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                       ⁢ 
                       
                         ( 
                         
                           t 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         ) 
                       
                     
                   
                   ⁢ 
                   
                     
 
                   
                   ⁢ 
                   
                     
                       I 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                       ⁢ 
                       
                         ( 
                         
                           t 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         ) 
                       
                     
                     ≈ 
                     
                       
                         
                           Vdc 
                           - 
                           VLED 
                         
                         
                           L 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                       × 
                       t 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
     Accordingly, equation (7) can be rewritten to equation (9). 
     
       
         
           
             
               
                 
                   
                     I 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                   
                   = 
                   
                     
                       
                         - 
                         
                           
                             VLED 
                             + 
                             
                               VD 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                           
                             L 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                       
                       × 
                       
                         ( 
                         
                           t 
                           - 
                           
                             t 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                         ) 
                       
                     
                     + 
                     
                       
                         
                           Vdc 
                           - 
                           VLED 
                         
                         
                           L 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                       × 
                       t 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
     When t 2  represents a time when I 3  becomes zero [I 3 =0], equation (10) is satisfied. 
     
       
         
           
             
               
                 
                   
                     0 
                     = 
                     
                       
                         
                           - 
                           
                             
                               VLED 
                               + 
                               
                                 VD 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                             
                             
                               L 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                         
                         × 
                         
                           ( 
                           
                             
                               t 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                             - 
                             
                               t 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                           ) 
                         
                       
                       + 
                       
                         
                           
                             Vdc 
                             - 
                             VLED 
                           
                           
                             L 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                         × 
                         t 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                   
                   ⁢ 
                   
                     
 
                   
                   ⁢ 
                   
                     
                       ( 
                       
                         
                           t 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                         - 
                         
                           t 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                       ) 
                     
                     = 
                     
                       
                         
                           Vdc 
                           - 
                           VLED 
                         
                         
                           VLED 
                           + 
                           
                             VD 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                       
                       × 
                       t 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
     If the off-period Moff of T 131  is shorter than (t 2 −t 1 ), T 131  will be turned on in a state where the flywheel current I 3  is flowing through the diode D 131 . In this case, since a turn-off current of the diode D 131  becomes large, a large current momentarily flows through the path formed by the capacitor C 132 , the diode D 131 , T 131 , and the ground, and thereby the capacitor C 132  discharges. This current does not flow through the load  120 , and so causes a reduction in efficiency. 
     Further, If T 131  is turned on in a state where the flywheel current I 3  is flowing, I 2  varies by the flywheel current I 3 , and thereby the electric discharge quantity Q 1  of the capacitor C 132  varies. If the electric discharge quantity Q 1  varies, I 1 , i.e. the AC input current Iac varies, and thereby a waveform of the AC input current Iac is disturbed. 
     Therefore, it is necessary to set the off-period Moff of T 131  such that the flywheel current I 3  disappears within the off-period Moff of T 131 . 
     For example, when Vac is 100V, VLED is 15V, and VD 1  is 0.6V, a maximum value of Vdc is about 141V, and (t 2 −t 1 ) is [8.08×t 1 ( ms )]. That is, in this case, in order that I 3  disappears within the off-period Moff of T 131 , it is necessary to set the off-period Moff of T 131  8.08 times longer than the on-period Mon. 
     Next, I 1  when T 131  is turned off will be explained. 
     It is assumed that T 131  shifts from on to off at the time t 1 . When I 1 ( t ) and VCp(t 1 ) represent respectively I 1  and VCp at the time t 1 , I 1  is expressed by equation (11). 
     
       
         
           
             
               
                 
                   
                     Vdc 
                     - 
                     
                       VCp 
                       ⁡ 
                       
                         ( 
                         
                           t 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         ) 
                       
                     
                   
                   = 
                   
                     
                       L 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                       × 
                       
                         
                           dI 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         dt 
                       
                     
                     + 
                     
                       
                         1 
                         Cp 
                       
                       × 
                       
                         
                           ∫ 
                           
                             t 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                           t 
                         
                         ⁢ 
                         
                           I 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                           ⁢ 
                           dt 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
     Equation (12) is obtained by solving equation (11) on the condition that the Vdc is constant. 
     
       
         
           
             
               
                 
                   
                     
                       I 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                     = 
                     
                       
                         
                           
                             
                               
                                 [ 
                                 
                                   Vdc 
                                   - 
                                   
                                     VCp 
                                     ⁡ 
                                     
                                       ( 
                                       
                                         t 
                                         ⁢ 
                                         
                                             
                                         
                                         ⁢ 
                                         1 
                                       
                                       ) 
                                     
                                   
                                 
                                 ] 
                               
                               2 
                             
                             × 
                             
                               Cp 
                               
                                 L 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                           
                           + 
                           
                             I 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                             ⁢ 
                             
                               
                                 ( 
                                 
                                   t 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                                 ) 
                               
                               2 
                             
                           
                         
                       
                       × 
                       
                         SIN 
                         ⁡ 
                         
                           ( 
                           
                             
                               
                                 t 
                                 - 
                                 
                                   t 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                               
                               
                                 
                                   L 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   2 
                                   × 
                                   Cp 
                                 
                               
                             
                             + 
                             φ 
                           
                           ) 
                         
                       
                     
                   
                   ⁢ 
                   
                     
 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     φ 
                     = 
                     
                       
                         SIN 
                         
                           - 
                           1 
                         
                       
                       [ 
                       
                         
                           I 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                           ⁢ 
                           
                             ( 
                             
                               t 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                             ) 
                           
                         
                         
                           
                             
                               
                                 
                                   [ 
                                   
                                     Vdc 
                                     - 
                                     
                                       VCp 
                                       ⁡ 
                                       
                                         ( 
                                         
                                           t 
                                           ⁢ 
                                           
                                               
                                           
                                           ⁢ 
                                           1 
                                         
                                         ) 
                                       
                                     
                                   
                                   ] 
                                 
                                 2 
                               
                               × 
                               
                                 Cp 
                                 
                                   L 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   2 
                                 
                               
                             
                             + 
                             
                               I 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                               ⁢ 
                               
                                 
                                   ( 
                                   
                                     t 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     1 
                                   
                                   ) 
                                 
                                 2 
                               
                             
                           
                         
                       
                       ] 
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
     Since the capacitor C 132  discharges when T 131  is on, [Vdc−VCp(t 1 )] becomes plus at the time t 1  when T 131  shifts from on to off. Thus, 
     I 1  flows from Vdc to the capacitor C 132  via the inductor L 132  (C 132  is charged). When I 1  flows, VCp increases. I 1  is, as represented by equation (12), a portion of a sine wave that has a phase advance ϕ at the time t 1 . 
     The period of the sine wave is represented as follows.
 
2π√{square root over ( L 2)} Cp  
 
     Also, I 1  has a peak value at a time when the following condition is satisfied. 
     
       
         
           
             
               
                 
                   t 
                   - 
                   
                     t 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                 
                 
                   
                     L 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                     × 
                     Cp 
                   
                 
               
               + 
               φ 
             
             = 
             
               n 
               2 
             
           
         
       
     
     This condition can be rewritten as follows. 
     
       
         
           
             
               ( 
               
                 t 
                 - 
                 
                   t 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
               
               ) 
             
             = 
             
               
                 ( 
                 
                   
                     n 
                     2 
                   
                   - 
                   φ 
                 
                 ) 
               
               × 
               
                 
                   L 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                   × 
                   Cp 
                 
               
             
           
         
       
     
     At this time, Vdc is equal to VCp [Vdc−VCp=0]. 
     Then, VCp increases beyond Vdc, but I 1  decreases. 
     VCp rapidly decreases in the next on-period of T 131 , and I 1  is inverted from decreasing to increasing in this on-period. The one period is completed at the start time of the next off-period of T 131 . 
     That is, one period (=control period M) of a waveform of I 1  that starts from the time t 1  when T 131  shifts from on to off has a waveform that consists of a portion of a half period of a sine wave and is convex upward. I 1  has a waveform that consists of upwardly convex waveforms connected in series. 
     A waveform of I 1  will be explained (see  FIGS. 3 and 4 ). 
     When T 131  is turned off at the time t 1 , I 1  increases. Thus, the plus terminal voltage (voltage at the point r) VCp of the capacitor C 132  increases. When [Vdc−VCp] varies according to the increase of VCp, I 1  is also varies. At this time, the inductor L 132  acts such that a variation of I 1  is minimized. Here, I 1  has a peak value at a time t 3  when Vdc is equal to VCp [Vdc=VCp]. A slope of I 1  becomes zero at the time t 3  and becomes the smallest before and after the time t 3 . That is, a variation of a waveform is minimized in a case that the waveform has a peak value at the time t 3  that is an intermediate point ([Vdc=VCp]) of the control period M (=off-period Moff+on-period Mon) starting from the time t 1 . In this case, I 1  has a waveform (a part of the upwardly convex sine wave) that becomes maximal at the midpoint t 3  and minimal at both end points of the control period M starting from the time t 1 . 
     Even though the waveform of I 1  may be deviated from this waveform due to some disturbance, the waveform of I 1  returns to this waveform by the action of the inductor L 132 . 
     A waveform of VCp corresponding to I 1  will be explained (see  FIGS. 3 and 4 ). 
     VCp becomes smaller than Vdc [Vdc&gt;VCp] by discharging of the capacitor C 132  in the on-period Mon [time t 0 ˜time t 1 ] of T 131  and becomes larger than Vdc [Vdc&lt;VCp] by charging of the capacitor C 132  in the off-period Moff of T 131  [time t 1 ˜time t 0 ]. That is, the waveform of VCp becomes minimal at the time t 1  when T 131  is turned off. Then, it increases until the time t 3  that is the midpoint ([Vdc=VCp]) along a slight downwardly convex curve. Further, it increases along a slight upwardly convex curve. Then, it becomes maximal at the time t 0  when T 131  shifts from off to on. Then, it decreases in the next on-period Mon of T 131  [time t 0 ˜time t 1 ]. And then, it becomes minimal at the time t 1  when T 131  shifts from on to off. 
     As indicated in equation (4), if the on-period Mon [time t 0 ˜time t 1 ] of T 131  is constant, the electric discharge quantity Q 1  is proportional to [Vdc−VLED]. 
     Further, the AC input current Iac is advanced in phase by the amount of charge [ΔVdc×Cp] indicated in equation (5) with respect to the AC voltage Vac. As described above, if Cp is set such that (ΔVdc×Cp) is negligible small compared to Q 1  [Q 1 »(ΔVdc×Cp)] in the control period M, an integral value of I 1  in the control period M (=Cp electric charge quantity) is approximately equal to the electric discharge quantity Q 1 , and thereby it is possible to ignore the phase advance of the AC input current Iac with respect to the AC voltage Vac. 
     A variation width of the convex waveform of I 1  (difference between a maximal value and a minimal value) depends on a ratio of the control period M to a half period [π×(L 2 ×Cp) 1/2 ] of the sine wave representing the convex waveform of I 1 . If the half period of the sine wave is longer than the control period M, I 1  continues to flow as the charging current of the capacitor C 132  during the control period M of T 131 . As the half period of the sine wave is longer than the control period M, the variation width of the convex waveform of I 1  becomes smaller, and harmonic components included in the AC input current Iac become smaller. 
     As described above, since the average value of I 1  in the control period M is proportional to (Vdc−VLED), if I 1  continues to flow during the control period M, the AC input current Iac is proportional to (Vdc−VLED). Thus, I 1  is synchronized with the AC voltage Vac and includes less harmonic components, and thereby this embodiment can satisfy the Harmonic Current Standard (EN61000-3-2). 
     The following is a summary of the above.
     1) In the case that T 131  is turned on and off at the fixed control period M, if the on-period Mon of T 131  is fixed, the electric discharge quantity Q 1  discharged from the capacitor C 132  (capacitance Cp) is proportional to (Vdc-VLED).
       The electric discharge quantity Q 1  is supplied as the current I 2  to the load  120  during the on-period Mon of T 131 , and simultaneously the electromagnetic energy is accumulated in the inductor L 131  (inductance L 1 ). The electromagnetic energy accumulated in the inductor L 131  is supplied to the load  120  as the flywheel current I 3  during the off-period Moff of T 131 .   
       2) When ΔVdc represents the amount of variation of Vdc in the control period M and Cp is set such that (ΔVdc×Cp) is negligible small compared to the electric discharge quantity Q 1 , the electric charge quantity charged in the capacitor C 132  (capacitance Cp) by the current I 1  flowing from Vdc through the inductor L 132  (inductance L 2 ) in the control period M is equal to the electric discharge quantity Q 1  discharged from the capacitor C 132  in the control period M.
       This can be likened to that the capacitor C 132  operates as a measuring cup for measuring the amount of charge proportional to (Vdc-VLED) by fixing the on-period Mon of T 131  in the fixed control period M.   Thus, the AC input current Iac proportional to (Vdc-VLED) flows in each control period M.   That is, by fixing the on-period Mon of T 131 , it is possible to improve the accuracy of the measurement of the amount of charge by the capacitor C 132 .   
       3) The current I 1  that charges the capacitor C 132  via the inductor L 132  in the off-period Moff of T 131  is expressed as a half-wave or a part thereof of a sine wave. If L 2  and Cp is set such that the half of the sine wave [π×(L 2 ×Cp) 1/2 ] is longer than the control period M, the current I 1  flowing through the inductor L 132 , i.e., the AC input current Iac flows continuously during the control period M.
       Thus, it is possible to suppress a variation of the AC input current Iac in every period M, and it is possible to suppress harmonic components included in the AC input current Iac.   
       4) It is ideal that an average value of I 1  in every control period M is proportional to Vdc. However, when Vdc is smaller than VLED [Vdc&lt;VLED], I 1  does not flow. After that, when Vdc becomes larger than VLED [Vdc&gt;VLED], I 1  begins to flow. If I 1  is proportional to Vdc, I 1  increases stepwise from zero, and thereby harmonic components of which frequencies are close to that of the fundamental wave of the AC input current Iac increase.
       On the other hand, if I 1  is proportional to (Vds-VLED), when Vdc becomes larger than VLED [Vdc&gt;VLED] and I 1  begins to flow, I 1  increases smoothly from zero. As a result, it is possible to suppress generation of harmonic components.   
       

     Second Embodiment 
     As described above, by fixing the control period M, the on-period Mon and the off-period Moff in the control period M, harmonic components included in the AC input current Iac can be suppressed. 
     On the other hand, if the on-period Mon and the off-period Moff in the control period M remains to be fixed, an output power increases when the AC voltage Vac becomes larger than a rated value. Further, it is impossible to adjust a light quantity of the LED used as the load. In order to prevent the output power from increasing when the AC voltage increases beyond the rated value and to be able to adjust the light quantity of the LED used as the load, it is necessary to be able to adjust the on-period Mon in the control period M. 
     A second embodiment comprises an on-period setting circuit that can optionally set the on-period Mon in the control period M of the switching element. Because the control period M (=Mon+Moff) is fixed, when the on-period Mon is set, the off-period Moff (=M−Mon) is also set 
     A circuit diagram of a power supply apparatus  200  of the second embodiment is shown in  FIG. 2 . The power supply apparatus  200  of the second embodiment comprises, similar to the first embodiment, a full-wave rectifier circuit  210 , a power supply circuit  230 , a control circuit  240 , a power circuit  260 , and a drive signal output circuit  270 . 
     The power supply apparatus  200  according to the second embodiment has the control circuit  240  different from the control circuit  140  of the power supply apparatus  100  according to the first embodiment. Therefore, in the following, only a configuration of the control circuit  240  will be explained. In  FIG. 2 , a component designated with the same reference numeral except for the third digit that is designated to the component shown in  FIG. 1  is the same component that is shown in  FIG. 1 . 
     The control circuit  240  has a clock signal generating circuit  241 , a drive circuit  242 , and an on-period setting circuit  250 . The clock signal generating circuit  241  and the drive circuit  242  are the same respectively as the clock signal generating circuit  141  and the drive circuit  142  of the control circuit  140  of the first embodiment. 
     In this embodiment, a clock signal period M of a clock signal generated from the clock signal generating circuit  241  is equal to a control period M of the switching element T 231 . However, a first period Ka when the clock signal is H-level and a second period Kb when the clock signal is L-level are different respectively from on-period Ma and off-period Mb of the switching element T 231 . 
     The on-period setting circuit  250  sets the on-period Mon of the switching element T 231  based on the clock signal generated from the clock signal generating circuit  241  at a fixed clock signal period M. 
     The on-period setting circuit  250  has switching elements T 251 -T 257 , resistors R 251 -R 253 , a variable resistor (volume) R 254 , a capacitor C 251 , Schmitt trigger ST 251 , D flip-flop DFF  251 , AND gate AND 251 , and an inverter INV 251 . In this embodiment, P-type MOSFETs are used as switching elements T 251  and T 253 , and N-type MOSFETs are used as switching elements T 252  and T 254 -T 257 . 
     Between the ground and the voltage Vzd generated by the power circuit  260 , a series circuit composed of T 251 , R 251 , T 252 , and R 252  is arranged. A gate and a drain each of T 251  and T 252  are short-circuited. Further, between the ground and Vzd, a series circuit composed of T 253 , T 254 , and R 253  is arranged. A gate of T 253  is connected to the gate of T 251 , and a current mirror circuit is constituted by T 251  and T 253 . A gate of T 254  is connected to the gate of T 252 , and a current mirror circuit is constituted by T 252  and T 254 . 
     Further, C 251  and T 255  are arranged in parallel with R 253 . 
     An output terminal of AND 251  is connected to a gate of T 255  via INV 251 , and also connected to an input terminal of the drive circuit  242 . 
     Each input terminal of AND 251  is connected to an output terminal of the drive signal output circuit  270 , an inverted output terminal (−Q) of DFF  251 , or the output terminal of the clock signal generating circuit  241  respectively. 
     A voltage at a point s where the drains of T 253  and T 254  are connected is input to a clock terminal (CLK) of DFF 251  via ST 251 . When H-level signal is input to the clock terminal (CLK) of DFF 251 , the inverted output terminal (−Q) of DFF 251  becomes L-level. Further, when L-level signal is input to a reset terminal (R bar) of DFF 251 , DFF 251  is reset (inverted output terminal (−Q) becomes H-level). 
     Further, between the ground and Vzd, a series circuit composed of R 254  and T 257  is arranged. A gate and a drain of T 257  are short-circuited. 
     A gate of T 256  is connected to the gate of T 257 , a drain of T 256  is connected to a point where R 251  and T 252  are connected, and a source of T 256  is connected to the ground. A current mirror circuit is constituted by T 256  and T 257 . 
     The power circuit  260  that generates a predetermined voltage Vzd is a representative example of “a second DC power source” of the present invention. Either one of a connection point where the resistor R 261  and the Zener diode ZD 261  are connected or the ground is a representative example of “a first terminal of the second DC power source”, and the other is a representative example of “a second terminal of the second DC power source” of the present invention. 
     T 251  and T 253  are representative examples of “first and second P-type MOSFETs” of the present invention, T 252  and T 254  are representative examples of “first and second N-type MOSFETs” of the present invention, T 255  is a representative example of “a second switching element” of the present invention, R 251 -R 253  are representative examples of “first to third resistances” of the present invention, and C 251  is a representative example of “a third capacitor” of the present invention. 
     Next, an operation of the control circuit  240  will be explained. Here, I 4  represents a current flowing through R 251 , I 5  represents a current flowing through R 252 , I 6  represents a current flowing through T 253  and T 254 , and I 7  represents a drain current of T 256 . 
     First, an operation of the control circuit  240  in a case that on-period adjustment function is not provided will be explained. This corresponds to a case that [I 7 =0] and [I 4 =I 5 ] are satisfied in  FIG. 2 . 
     A channel width of T 253  constituting the current mirror circuit with T 251  is set to be larger than a channel width of T 251 . A channel width of T 254  constituting the current mirror circuit with T 252  is set to be smaller than a channel width of T 252 . Resistance value of R 253  is set to be by a ratio of the channel width of T 252  to the channel width of T 254  inversely proportional to resistance value of R 252 . 
     If it is set so, when T 255  is off and C 251  is fully charged, a source voltage of T 254  becomes equal to a source voltage of T 252 , and thereby I 4  being equal to I 5  becomes larger than I 6  [I 4 =I 5 &gt;I 6 ]. 
     The channel width of T 253  is set such that a current which is larger than I 4  can flow through T 253 . Therefore, I 6  flowing through T 253  and T 254  becomes equal to a saturated current of T 254 . On the other hand, I 6  flowing through T 253  at this time is an unsaturated current. Therefore, a potential of the point s increases, and the output signal of ST 251  becomes H-level. 
     In this state, when T 255  is turned on, the capacitor C 251  discharges, and a source of T 254  is grounded. Thus, a voltage between the gate and the source of T 254  becomes larger than a voltage between the gate and the source of T 252  by a voltage (R 252 ×I 5 ), and so a current that can flow through T 254  increases. 
     The channel width of T 253  is set to be larger than the channel width of T 251 , but is set such that I 6 , that flows when the source of T 254  is grounded, does not exceed a maximum current that can flow through T 254  in that state. Thus, I 6  flowing in that state is a saturated current of T 253 , but is an unsaturated current for T 254 . Therefore, the potential of the point s is reduced, and thereby the output signal of ST 251  becomes L-level. 
     A relationship between the clock signal and the potential of point s will be explained. 
     When the drive signal of L-level is output from the drive signal output circuit  270 , an output signal of AND 251  is L-level. In this case, T 231  is turned off, but T 255  is turned on. Thus, the source of T 254  is grounded, and the saturated current of T 253  flows as I 6 . Therefore, the potential of the point s becomes L-level, and thereby the output signal of ST 251  becomes L-level. 
     When the drive signal of H-level is output from the drive signal output circuit  270  and the clock signal becomes L-level, DFF  251  is reset, and thereby the inverted output terminal (−Q) becomes H-level. In this state, when the clock signal becomes H-level, the drive signal of H-level is output from AND 251  to the drive circuit  242 , and thereby T 231  is turned on. At the same time, the gate of T 255  is grounded by INV 251 , and thereby T 255  is turned off. 
     When T 255  is turned off, I 6  flows through a parallel circuit consisting of R 253  and C 251 . Thus, C 251  is charged, and a voltage drop occurs across R 253 . In this state, I 6  is a constant current because I 6  is the saturated current of T 253 . Thus, the source voltage of T 254  increases linearly. 
     When the source voltage of T 254  approaches the source voltage of T 252 , the drain current of T 254  shifts from the unsaturated current to the saturated current, and thereby I 6  decreases. Accordingly, the drain current of T 253  shifts from the saturated current to the unsaturated current. Therefore, the potential of the point s rapidly increases, and thereby the output signal of ST 251  becomes H-level. 
     When H-level signal from ST 251  is input to the clock terminal (CLK) of DFF  251 , the inverted output terminal (−Q) of DFF  251  becomes L-level. Thus, the output signal of AND 251  becomes L-level, and thereby T 231  is turned off. At the same time, T 255  is turned on. Thus, the potential of the point s decreases, and thereby the output signal of ST 251  becomes L-level. 
     In this embodiment, the on-period Mon of T 231  is from a time when the clock signal rises to H-level to a time when the output signal of ST 251  is inverted from L-level to H-level caused by that the capacitor C 251  is charged and then the potential of the point s becomes a predetermined potential. 
     In this embodiment, the first period Ka when the clock signal is H-level is set to exceed a period that is from the time when the clock signal rises to H-level (start time of the first period Ka) until the output signal of ST 251  is inverted from L-level to H-level caused by that the potential of the point s becomes the predetermined potential. 
     When the clock signal becomes L-level, DFF  251  is reset, and thereby the inverted output terminal (−Q) becomes H-level. 
     The off-period Moff of T 231  is from the time when the output terminal of ST 251  is inverted from L-level to H-level to a time when the clock signal next rises to H-level next (start time of the next first period Ka). 
     That is, the on-period setting circuit  250  sets a period from the start time of the first period Ka until a predetermined time elapses as the on-period Mon of T 231 . The off-period Moff of T 231  is from the time when the predetermined time has elapsed to a stat time of the next first period Ka. 
     Next, an operation in a case where I 7  is an arbitrary value that is other than zero will be explained. 
     The on-period Mon of T 231  varies according to the rate of increase of the source voltage of T 254 . Thus, for example, if the capacitance of the capacitor C 251  is increased, the rate of increase of the source voltage of T 254  becomes gentler, and thereby the on-period Mon of T 231  becomes longer. 
     Further, the on-period Mon of T 231  is proportional to (resistance value of the resistor R 252 ×I 5 ). Thus, for example, if reducing I 5 , the on-period Mon of T 231  becomes shorter. 
     In this embodiment, by flowing a current I 7  corresponding to an adjustment amount that is set by the variable resistor R 254 , the current I 5  (=I 4 −I 7 ) is adjusted, and thereby the on-period Mon of T 231  is adjusted. 
     A drain current I 7  of T 256  is inversely proportional to a resistance value of the variable resistor R 254  which is arranged between Vzd and a drain of T 257  constituting the current mirror circuit with T 256 . 
     When I 7  flows, I 5  (=I 4 −I 7 ) decreases. When I 5  decreases, the source voltage of T 252  (=resistance value of the resistor R 252 ×I 5 ) also decreases. 
     As a result, a period from a time when T 255  shifts from on to off until the output signal of ST 251  shifts from L-level to H-level caused by that the potential of the point s increases to the predetermined potential is shortened (becomes shorter). 
     That is, an on-period Mon of T 231  becomes shorter by a time interval corresponding to I 7  depended on R 254  than that of T 231  which is set without any I 7  (any adjustment amount is not set). 
     The clock signal period M (=control period M) is fixed. Therefore, the off-period Moff of T 231  is extended than the off-period Moff when I 7  is zero by the time interval according to I 7  set by R 254  (becomes longer). 
     When I 7  flows and the source voltage of T 252  decreases, a voltage applied to R 251  increases and I 4  increases. When I 4  increases, the saturated current of T 253  increases and thereby the rate of increase of the source voltage of T 253  increases. Therefore, although a rate of decrease of the on-period Mon of T 231  is slightly larger than a rate of decrease of I 5 , the purpose of shortening the on-period Mon of T 231  is achieved. 
     By shortening (reducing) the on-period Mon of T 231  in the fixed control period M, it is possible to prevent an increase of the output power due to an increase of the AC voltage Vac. Further, it is possible to reduce the amount of light of LED that is used as the load. 
     In this embodiment, the on-period setting circuit  250  sets a period from the start time of the first period Ka of the clock signal until a predetermined time adjusted by the adjustment amount that is set by an adjustment amount setting circuit (variable resistor R 254 ) elapses as the on-period Mon of T 231 . 
       FIG. 3  and  FIG. 4  show results obtained by simulating the power supply apparatus  100  of the first embodiment. Here,  FIG. 4  is an enlarged view of a portion IV (31 ms-31.12 ms) in  FIG. 3 . 
     Circuit parameters used in the simulation are as follows. Vac: AC100V (effective voltage), 60 Hz, L 1 : 30 μH, L 2 : 600 μH, Cp: 0.5 μF, C 1 : 2000 μF, control period (clock signal period): 30 μs [on-period (H-level period): 4.509 μs], average value of VLED: 26.3V, average value of the load current: 2.92 A. 
     The adjustment of the control period M and the on-period Mon in the control period M is performed by using an analog circuit, but of course, it may be carried out by software by using a microcomputer or the like. 
     In  FIG. 3 , a horizontal axis represents time (unit: ms), a first vertical axis represents voltage of a graph (A) (unit: V), a second vertical axis represents current of a graph (C) (unit: A). 
     The graph (A) represents DC voltage Vdc, the graph (C) represents current (charging current) I 1  supplied from Vdc to the capacitor C 132 . 
       FIG. 4  is the enlarged view of the portion IV in  FIG. 3 . A graph (B) (positive terminal voltage VCp of the capacitor C 132 ) and a graph (D) [current (I 2 +I 3 ) flows through the inductor L 131 ] are not shown in  FIG. 3 , but added to  FIG. 4 . Voltage value of the graph (B) is represented by a first vertical axis of  FIG. 4  (unit: V) and current value of the graph (D) is represented by a third axis of  FIG. 4  (unit: A). 
     Vdc can be regarded as a constant value in the enlarged view shown in  FIG. 4 . 
     VCp becomes larger than Vdc [VCp&gt;Vdc] in a later half of the off-period Moff of T 131  (between times t 1  and t 0 ), and becomes maximal at an end time of the off-period Moff. 
     When T 131  shifts from off to on (time t 0 ), VCp rapidly decreases along an upwardly convex parabola. This is because that since the electric discharge quantity Q 1  of the capacitor C 132  is proportional to the square of the on-period Mon (between times t 0  and t 1 ) as represented by the equation (4), when ΔVCp represents a decrease amount from a maximal value of VCp, [ΔVCp=Q 1 /Cp] is satisfied. 
     VCp becomes minimal at the time t 1  when T 131  shifts from off to on. At this time, VCp is smaller than Vdc [VCp&lt;Vdc]. 
     Thereafter, I 1  increases by the action of a voltage difference (Vdc−Vcp) and the inductor L 132 , and VCp increases as the capacitor C 132  is charged. At a time t 3  when VCp is equal to Vdc [VCp=Vdc], I 1  reaches a peak (maximal). Thereafter, VCp continues to increase by a counter electromotive force of the inductor L 132 , but I 1  turns to decrease. 
     I 1  has an upwardly convex waveform that is a part of the sine wave represented by the equation (12), and reaches a peak (maximal) at the midpoint (time t 3 ) of the off-period Moff of T 131  (between times t 1  and t 0 ) and becomes minimal at the time t 1  when T 131  shifts from on to off. The reason why I 1  has such waveform is that, as described above, the inductor L 132  acts such that a gradient of I 1  is minimized. 
     Although VCp increases approximately linearly in the off-period of T 131  (between times t 1  and t 0 ), a point where VCp is equal to Vdc [VCp=Vdc] is slightly delayed from a point where I 1  reaches a peak. Therefore, the entire waveform of VCp is relatively under Vdc. This is because that VCp is lowered from Vdc by a voltage drop caused by that I 1  flows through an internal resistor (0.8Ω) of the inductor L 132 . 
     A current (I 2 +I 3 ) flowing through the inductor L 131  linearly increases in the on-period Mon of T 131  (between times t 0  and t 1 ), and then linearly decreases when T 131  shifts from on to off, and disappears within the off-period Moff (between times t 1  and t 0 ). The portion that linearly increases in the on-period Mon of T 131  represents I 2 . The portion that linearly decreases in the off-period Moff of T 131  represents I 3 . 
     From the result of the simulation, it is found that the power factor is 99.7% and the efficiency is 95.2%, and thereby harmonic currents satisfy the Class C of the Standard (EN61000-3-2). 
     Third Embodiment 
     A circuit diagram of a third embodiment  300  of the power supply apparatus of the present invention is shown in  FIG. 5 . 
     In the third embodiment, a configuration of a power supply circuit  330  is different from the power supply circuit  130  of the first embodiment. Therefore, in the following, only a configuration of the power supply circuit  330  will be explained. 
     In  FIG. 5 , a component designated with the same reference numeral except for the third digit that is designated to the component shown in  FIG. 1  is the same component that is shown in  FIG. 1 . 
     The power supply circuit  330 , similar to the power supply circuit  130  of the first embodiment, comprises first and second capacitors C 331  and C 332 , first and second inductors L 331  and L 332 , a diode (flywheel diode) D 331 , and a first switching element T 331 . 
     In this embodiment, between a positive electrode c and the ground, the inductor L 332  having inductance L 2  and the capacitor C 332  having capacitance Cp are arranged in series. 
     The inductor L 331  having inductance L 1  and the switching element T 331  are arranged in series to the capacitor C 332 . 
     A series circuit composed of the diode D 331  and a parallel circuit consisting of the capacitor C 331  having capacitance C 1  and a load  320  is arranged in parallel with the inductor L 331 . An anode of the diode D 331  is connected to a connection point where the inductor L 331  and the switching element T 331  are connected. Therefore, a polarity each of LEDs  321  used as the load  320  is inverted. 
     When T 331  is turned on, a discharging current I 2  caused by electric charge accumulated in the capacitor C 332  flows through a path formed by the inductor L 331 , T 331  and the ground. At this time, due to the presence of the diode D 331 , a current does not flow through the parallel circuit consisting of the capacitor C 331  and the load  320 . 
     When T 331  is turned off, a flywheel current I 3 , that is caused by an electromagnetic energy accumulated in the inductor L 331  while T 331  is on, flows through a path formed by the diode D 331  and the parallel circuit consisting of the capacitor C 331  and the load  320 . At the same time, a charging current I 1  from Vdc flows to the capacitor C 332  via the inductor L 332 . 
     The electric discharge quantity Q 1  of the capacitor C 332  in the on-period of T 331  is represented by equation (13) that is obtained by replacing (Vdc−VLED) with Vdc in the above-mentioned equation (4). 
     
       
         
           
             
               
                 
                   
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                           ⁢ 
                           1 
                         
                       
                       ⁢ 
                       
                         I 
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                         2 
                         ⁢ 
                         dt 
                       
                     
                     = 
                     
                       
                         Vdc 
                         
                           2 
                           × 
                           L 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
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                       t 
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                   13 
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     In the equation (13), as the equation (4), t 1  represents the on-period Mon of T 331 , Vdc represents pulsating DC voltage, and L 1  represents inductance of L 331 . 
     As for a calculation method for calculating I 2  and I 3  in  FIG. 5 , it is possible to apply the same calculation method for calculating I 2  and I 3  in  FIG. 1  by setting VLED in the above-mentioned equation (1) to zero [VLED=0] and replacing (Vdc−VLED) in equations (2) to (4) and (8) to (10) with Vdc. A method for calculating I 1  is the same as the calculation method for calculating I 1  in  FIG. 1 . 
     Accordingly, this embodiment can also realize a stable PFC control by setting such that I 3  disappears within the off-period Moff of T 331 , for example, by setting the inductance L 2  of the inductor L 332  and the capacitance Cp of the capacitor C 332  such that the half period [π×(L 2 ×Cp) 1/2 ] of the sine wave of I 1  is longer than the control period M. 
     The power supply circuit  130  of the first embodiment operates as a buck converter and the power supply circuit  330  of the third embodiment operates as a buck-boost converter. The power supply circuit  330  of the third embodiment has following features as compared with the power supply circuit  130  of the first embodiment.
         1) The electric discharge quantity Q 1  in the first embodiment depends on (Vdc−VLED) as represented by the equation (4). Therefore, when VLED varies, also the electric discharge quantity Q 1  varies accordingly. In contrast, the electric discharge quantity Q 1  in the third embodiment does not include VLED as represented by the equation (13). Therefore, it is possible to realize the stable PFC control without being affected by variations of VLED.   2) In the first embodiment, I 1  does not flow in a state where Vdc is smaller than VLED [Vdc&lt;VLED].
           In contrast, in the third embodiment, there is not such constraint. Therefore, I 1  flows even when Vdc decreases (range in where I 1  flows is expanded). This contributes to suppression of harmonic components of I 1 .   
               

     In the first embodiment  100  (second embodiment  200 ), the inductor L 131  (L 231 ), the parallel circuit consisting of the load  120  ( 220 ) and the capacitor C 131  (C 231 ) are connected in series. Therefore, even if positions of the inductor L 131  (L 231 ) and the parallel circuit consisting of the load  120  ( 220 ) and the capacitor C 131  (C 231 ) are changed, the resulting effect does not change. 
     Further, in the first embodiment  100  and the second embodiment  200 , the DC power source having the full-wave rectifier circuit that converts the AC voltage to the pulsating DC voltage obtained by full-wave rectifying the AC voltage is used. However, a battery or the like may be used as the DC power source. The reason is that the DC power source such as a battery can be regarded as a DC power source that generates a pulsating DC voltage having an infinite period. In a case where the battery or the like is used as the DC power source, it is not necessary to consider a phase shift of the AC input current to the AC voltage (power factor) unlike in the case where the DC power source having the full-wave rectifier is used, but the effect of suppressing harmonic components included in the current supplied from the DC power source is maintained. Therefore, there are such effects that it is possible to remove or reduce the size of the low-pass filter for suppressing harmonic components and it is possible to eliminate parts and current detecting processes for detecting the current flowing through the switching element. 
     In this embodiment, a DC power source such as a battery or the like is a representative example of “a third DC power source” of the present invention. 
     The present invention is not limited to the configuration described in the detailed description. Various modifications, additions, and deletes are possible without departing from the scope and the spirit of the present invention. 
     The power supply apparatus for supplying DC power to the load having light-emitting diodes has been explained. However, the power supply apparatus of the present invention can be used for supplying DC power to various loads other than light-emitting diodes. 
     The value of the elements forming each circuit (e.g., inductance, capacitance, resistance) can be suitably set according to a type of the load, and so on. 
     A FET is preferably used as the switching element for supplying power to the load. Of course, an element other than a FET can be used as the switching element. 
     In the embodiments, it is configured that the switching element is turned on when the clock signal is H-level and turned off when the clock signal is L-level. It can be configured that the switching element is turned on when the clock signal is L-level and turned off when the clock signal is H-level. 
     DESCRIPTION OF THE REFERENCE NUMERALS 
     
         
           10  . . . AC power source, 
           100 ,  200 ,  300 ,  400  . . . power supply apparatus, 
           110 ,  210 ,  310 ,  410  . . . full-wave rectifier circuit, 
           120 ,  220 ,  320 ,  420  . . . load, 
           121 ,  221 ,  321 ,  421  . . . light-emitting diode (LED), 
           130 ,  230 ,  330 ,  430  . . . power supply circuit, 
           140 ,  240 ,  340 ,  440  . . . control circuit, 
           141 ,  241 ,  341  . . . clock signal generating circuit, 
           142 ,  242 ,  342  . . . drive circuit, 
           160 ,  260 ,  360  . . . power circuit, 
           170 ,  270 ,  370  . . . drive signal output circuit, 
           250  . . . on-period setting circuit, 
           480  . . . low-pass filter, 
         L 131 , L 132 , L 231 , L 232 , L 331 , L 332 , L 431 , L 481 , L 482  . . . inductor, 
         C 131 , C 132 , C 231 , C 232 , C 251 , C 331 , C 332  C 431 , C 481 , C 482  . . . capacitor, 
         D 131 , D 231 , D 331 , D 431  . . . flywheel diode, 
         T 131 , T 231 , T 255 , T 331 , T 431  . . . switching element, and 
         R 254  . . . variable resistor (adjustment amount setting circuit).