Patent Publication Number: US-6703908-B1

Title: I/O impedance controller

Description:
STATEMENT OF RIGHTS IN INVENTION 
     The United States Government has rights to use this invention pursuant to subcontract B338314 issued by the University of California, which operates Lawrence Livermore National Laboratory for the United States Department of Energy under Contract No. W-7405-ENG-48. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     The present invention relates generally to the field of electronics, and more particularly to an impedance controller for an electronic circuit. 
     BACKGROUND 
     Voltage, temperature, and processing causes the impedance of an output driver in an electronic circuit to vary. This variation can add noise, increase the power, and reduce the data transfer rate of the driver. In the prior art, variations in impedance due to environmental and processing parameters have been compensated for using analog circuitry, and in particular a low pass filter (LPF) to filter out a certain range of noise frequency. Such filters, however, are typically custom devices and are not available in most circuit design macro libraries. It is desirable, however, that a digital design be provided for this purpose, thus allowing the impedance compensating circuitry to be implemented with most macro libraries. Furthermore, there are other limitations in the art concerning impedance compensation that would be desirable to address, as discussed further below. 
     SUMMARY OF THE INVENTION 
    
    
     The present invention, in the various example embodiments illustrated herein, provides an all-digital impedance control circuit. This design potentially enables faster data transfer rates, quieter systems, and reduced power compensation, as compared to analog circuits for this purpose. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1-3 illustrate various example embodiments of methods according to the present invention. 
     FIGS. 4-6 illustrate various example embodiments of apparatus according to the present invention. 
     FIGS. 7-11,  12 A- 12 B,  13 A- 13 B and  14  illustrate further example embodiments of apparatus according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     In the following detailed description of the invention reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. 
     Referring now to FIGS. 1-3, there is described various example embodiments of the methods of the present invention. FIG. 1 illustrates a first example embodiment  10  of the method, wherein the impedance of a digital circuit is controlled using an all-digital impedance control circuit  12 , and wherein one or more control bits are used to tune the output impedance. According to a further aspect of this embodiment, the impedance control circuit is fabricated using circuit components found in a standard macro library of a computer aided design system. 
     Referring now to FIG. 2, there is illustrated another example embodiment  20  of the methods of the present invention, wherein there is provided an impedance control circuit for an output driver on an integrated circuit (“IC”) device. According to this embodiment, a resistor divider network is formed with the output driver and a resistor off the IC device so that the divider network produces an output voltage  22 , the output voltage of the divider network is compared with a reference voltage  24 , and the output impedance of the output driver is adjusted to attempt to match the output voltage of the divider network and the reference voltage  26 . 
     According to another example embodiment  30  shown in FIG. 3, the divider network is over-sampled  32 , the results are stored  34 , this process is repeated  36 , and the results are averaged over multiple over sampling operations  38 . The impedance is controlled with a plurality of bits forming a word, and the value of the word is updated by only one least significant bit at a time  39 . According to one example aspect of this method, a sequencer is used to determine when to update the bits. According to another example aspect, the sequencer is disabled to monitor the updating of the bits or to cause all updates to be sent to system drivers. According to yet another example aspect an impedance controller circuit carries out the above-described methods, and the controller is monitored and overridden by test data registers. According to yet another example aspect, a mid count is used to bypass the sampler for test purposes during system operation. 
     Referring now to FIGS. 4-6, there is illustrated various example embodiments of apparatus according to the present invention. FIG. 4 illustrates a first example embodiment  40  of the apparatus, wherein the impedance of a digital output circuit  44  is controlled using an all-digital impedance control circuit  42 , and wherein one or more control bits are used to tune the output impedance. According to a further aspect of this embodiment, the impedance control circuit is fabricated using circuit components found in a standard macro library of a computer aided design system. 
     Referring now, to FIG. 5, there is illustrated another example embodiment  50  of the apparatus of the present invention, wherein there is provided an impedance control circuit for an output driver on an integrated circuit (“IC”) device. According to this embodiment, a resistor divider network  55  is formed with the output driver circuit  52  and a resistor  54  off the IC device so that the divider network  55  produces an output voltage Vout, and the output voltage of the divider network is compared with a reference voltage Vref. The output impedance of the output driver circuit  52  is adjusted with the impedance update circuit  59  to attempt to match the output voltage Vout of the divider network  55  and the reference voltage Vref. 
     According to another example embodiment  60  shown in FIG. 6, the divider network is over-sampled with sampling circuit  62  which stores the results and repeats this process in order to average the results over multiple sampling operations. Further, in this or the other example apparatus embodiments described above, the impedance is controlled with a plurality of bits forming a word, and the value of the word is updated by only one least significant bit at a time. According to one example aspect of this apparatus, a sequencer is used to determine when to update the bits. According to another example aspect, the sequencer is disabled to monitor the updating of the bits or to cause all updates to be sent to system drivers. According to yet another example aspect of the apparatus, the control mechanisms are monitored and overridden by test data registers. According to yet another example aspect, a mid count is used to bypass the sampler for test purposes during system operation. 
     Referring now to FIGS. 7-14, there is illustrated further example embodiments of the invention wherein the impedance controller is a RLM macro used to generate the digital code to the input control bits (referred to for example as “PVT code” herein below) of an output circuit module, wherein the input control bits specify the output impedance characteristics of the output circuit module (for example the “APF I/O” circuits described in co-pending application entitled “Method and Apparatus for Communicating Computer Data from One Point to Another Over a Communications Medium,” filed on even date herewith, and assigned to the same assignee as the present patent) so that a correct output impedance is produced by the output circuit over all process, voltage, and temperature environments. A top level block diagram of an impedance controller for such a module is shown in FIG.  7 . It consists of two identical logic blocks called icntrl herein, one for the Nfet control, and the other one for Pfet control. FIG. 8 is a table giving the pin assignments for an impedance controller according to this example embodiment. The detail implementation of icntrl is discuss below. 
     FIG. 9 gives a brief description of the input and output pin assignment of the logic block icntrl. FIG. 7 illustrates the mapping between the 24 Test Data Register bits to the input of control. Input pin, sel_npfet is hardwired to VDD for Nfet control and to VSS for Pfet control. Output pin, pvt_sys is the 8-bit PVT code goes to the system I/O, bit O is the base bit, and is always at VDD; pvt ref is the 8.5-bit PVT code goes to the reference I/O, bit O is the half bit and bit  1  is the base bit which is always on. 
     As shown in FIG. 11 block cntrl is made up of several logic sections, as follows: 
     In the input stage the input signal from reference I/O is latched with sys_clk running at very low frequency. In this section, Control pin, sel_npfet is used to either buffering or inverting the input signal, it determines if the controller is used to control nfet or pfet accordingly. Control pin, tdr_overid is used to override the input signal from reference I/O with tdr_in, signal controller by the JTAG TDR(test data register). 
     The filtering stage, due to presence of noise, uses two digital filters to process the signal from input section. Control pin sel_filter is used to select between these two filters. The detail block diagram of the filters is illustrated in FIG. 10, implementing Yk=ak+a*Yk−1, where a is ½ or 1 depending on sel_filter. The sequence in which the filter operates is controlled by four internal signals: f_updated_yk, f_reset_yk, f_reset_acc, f_acc_clk_en. These four signals are generated in Sampling Controller where a 7-bit binary counter is implemented. f_reset_yk is tied to sys_reset pin, and f_acc_clk_en is teid to the inverse of sys_disable. f_update_yk is active during full count, and f_reset_acc is active druing zero count. During initial system reset, Sampling Counter is set to zero count; f_reset_yk and f_reset_acc are active which set the Yk register and accumulator to zero. After reset, Sampling Counter starts counting up and accumulator starts to accumulate input samples either by adding to or subtracting from it through Adder. When Sampling Counter count up to full count, f_udpate_yk is active, the current value of the Adder is passed to Yk register, and previous value stored in Yk register (Yk−1) is divided by 1 or 2, depending on the selection of the filter and added with the value in Accumulator (Yk) through Adder. The value of Adder, sum of Yk+a*Yk−1 is examined, if overflow occurs, over_flow signal is set, and if underflow occurs, under_flow signal is set. These two signals are passed to Sequencer to register the sequence, and to 4 bit counter to counting up or down accordingly to produce a higher or lower pvt code. if either overflow or underflow occur, Yk register is set to zero, otherwise, current value of Yk is kept which will become Yk−1 next time around. When Sampling Counter reach zero count again, f_reset_acc is set and the whole process described above starts over again. 
     In the sequencer section, several sequences where pvt code toggling back and forth around the correct pvt code are recognized and a recycle signal is produced upon recognition to lock in those pvt code that goes to the system I/O. 
     The 4 bit Counter operates such that depending on whether overflow is set or underflow is set, this binary counter will count up and down to produce a new PVT code. 
     In the Thermodecoder section, the actual PVT code is decoded from 4 bit binary counter. It ensures that only one bit of 8 bit PVT code changes state at one time when 4 bit binary counter update to a new PVT code. 
     The Hold Resiger section consists of a set of latches clocked by the sys_clk to produce latched version of PVT code, and hold the PVT code if recycle signal from sequencer goes low. The hold feature can be deactivated by setting the seq_bypass pin low. 
     The Output Stage section is basically a 3 to 1 mux selecting among the generated PVT code, tdr_bits, and mid count bits controlled by 2 input pins, sel_tdr and sel_mid. 
     FIGS. 12A-12B illustrate the hook up of the impedance controller and an I/O circuit with the R on  of the Pfet  102  equal to the R on  of Nfet  100 . 
     FIGS. 13A-13B illustrate the hook up of the impedance controller and a I/O circuit who&#39;s impendance is symmetric like GTL+. Where the R on  resistance of the Nfet is only 7 ohm, but the R on  of the Pfet is 35 ohm. In this embodiment the pad transfer impedance is also accounted for in the Nfet reference IO. The GTL+driver is described in “GTL+Driver” U.S. patent application Ser. No.: 09/620,679, filed herewith, the description of which is incorporated herein by reference. 
     EXAMPLE OPERATION 
     The APF impedance controller(imp_cntrl) along with BCMR(reference IO) and BDAPF(system IO) form a close loop for the normal operation, where impedance controll take the feedback from reference IO, generate and update the proper PVT code to both reference and system IOs. The operation of one icntrl controller logic is described in the truth table of FIG.  13 . 
     The PVT code provided by the Impedance Controller can be preloaded in 4 ways: 
     1. When sys_clk is running, if sys_disable is low, sys_reset is held high. All the counters will be set to the mid count. The thermodecoder will hold the pvt code to mid count. If sys_disable is high or if the sys_clk is stopped, all the registers in the controller are inactive, and hold it&#39;s previous value, PVT code will be keep constant. 
     2. When control pin tdr_overid is held high by the JTAG TDR(Test Data Register), input from reference IO(comp_in) will be overridden by the tdr_in. It is controlled by the JTAG and is toggled to the PVT count desired. 
     3. When control pin sel_tdr is held high by the JTAG TDR, PVT code will be replaced by what is in the tdr_bits. 
     4. When control pin sel_mid count is high, PVT code will be set to mid count. 
     According to one example embodiment of the invention, a clock of 10 Mhz or less is used, with 6.25 Mhz being one preferred rate. In addition, edge rate and skew meet IBMs SA-27E lowest requirements in another embodiment. In one sample embodiment, just another RLM, not wired RLM. According to another embodiment, one impedance controller is required for each NI channel, ad the BCMR I/Os used as a impedance reference I/Os must be in the center of the NI I/Os to trace their PVT. According to another example embodiment, the controller logic can be placed anywhere. The padxfer metal must match the padxfer metal of the NI I/Os in that channel. According to yet another example embodiment, the Estimated cell count is 10 k cells. In still yet another example embodiment, during normal operation, sys_clk should be active and running at very low frequency (suggested 6.25 mhz), sys_reset and sys_disable should be set to low. In this scenario, the controller will update to a new set of PVT code every 256 cycle or 41 us(assuming sys_clk running at 6.25 mhz).