Patent Publication Number: US-6661681-B2

Title: Power converter apparatus with a circuit for preventing destruction of a power device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-136436, filed May 7, 2001, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to a power converter apparatus using a power device, and more particularly to a power converter apparatus used in an inverter system for compressors and fan motors of air conditioners, refrigerators, etc., motors of washers, etc., and hydraulic control motors. 
     2. Description of the Related Art 
     In a conventional inverter system, a control section (e.g. MCU) for PWM (pulse width modulation) control and a power device (e.g. an IGBT (insulated Gate Bipolar Transistor) and a gate drive IC) for supplying current to the winding of a motor are coupled by a photocoupler. Thus, even if the potential of the winding of the motor has accidentally dropped to a ground potential level and shorted, the abnormality of the high-side device can be told to the control section from the high-side driver IC via the photocoupler. Upon receiving the information on the abnormality, the control section stops the ON-instruction to the power device. Thereby, the power device can be protected. 
     FIG. 1 is a circuit diagram showing the structure of a conventional power converter apparatus using photocouplers. 
     As is shown in FIG. 1, the power converter apparatus comprises a control section (MCU) M 101 ; photocouplers PC 101  to PC 106 ; voltage power supplies V 101  to V 106 ; clocked inverters CI 101  to CI 106 ; IGBTs (Insulated Gate Bipolar Transistor)  101  to  106 ; and resistors R 101  to R 112 . A load motor L 101  is connected to the IGBTs  101  to  103 . 
     The system shown in FIG. 1 has the following problems. 
     Since the system requires six photocouplers, the manufacturing cost is high. Since there is a delay in transmission time of the photocouplers PC 101  to PC 106 , an error is great between the time of an order from the control section M 101  and the time of execution of the order. Four power supplies V 102  to V 105  are necessary as control power supplies. Thus, the power converter apparatus shown in FIG. 1 is not preferable in terms of both the cost and performance of the system. 
     Under the circumstances, most of modern power converter apparatuses have recently adopted a microcomputer direct driving system (photocoupler-less system) and a single power supply. 
     FIG. 2 is a circuit diagram showing the structure of a conventional bootstrap-type power converter using a microcomputer direct driving system and a single power supply. 
     As is shown in FIG. 2, the power converter apparatus comprises a control section (MCU) M 101 ; clocked-inverters CI 101  to C 109 ; voltage power supplies V 101  and V 106 ; IGBTs  101  to  106 ; transistors TR 101  to TR 103 ; diodes D 101  to D 103 ; capacitors C 101  to C 103 ; and resistors R 113  to R 115 . 
     In this power converter apparatus, the high-side driving IC of the power device (IGBT  101 ,  102 ,  103 ) has the withstand voltage, which the photocouplers have to bear in the prior art. However, because of the problem of tolerable power, a control instruction from the control section M 101  is sent to the high-side block by means of an edge pulse, and the edge pulse, in turn, is converted to a normal pulse within the high-side block. 
     As has been mentioned above, the transmission of signals from the low-side block to the high-side block within the high-side IC is effected by level-shifting using the edge pulse. Specifically, this is effected by short-time conduction of the high-withstand-voltage n-channel MOSFETs (TR 101  to TR 103 ). If the level-shifting n-channel MOSFETs (TR 101  to TR 103 ) (source-grounded) are turned on, current flows in the resistors R 113  to R 115  connected to the drains of these n-channel MOSFETs. At this time, voltage variations occurring between both ends of the resistors R 113  to R 115  are detected by the high-side block, and thereby signals are transmitted. 
     In general, in an inverter system used in a 100V commercial line, a voltage-doubler rectifier DC line is converter-controlled. Thus, the power device is required to have a withstand voltage of 600V, including a surge voltage. The above-mentioned level-shifting MOSFETs (TR 101  to TR 103 ) are also required to have a withstand voltage of 600V. 
     A high-withstand-voltage p-channel MOSFET is necessary for signal transmission from the high-side block to the low-side block. It is not possible, however, to realize a 600V p-channel MOSFET at a feasible cost. 
     Thus, when the high-side output section has shorted at a ground potential level, a large current flows. Even if the flow of large current is detected and a gate voltage to the IGBT is cut off by self-excess-current protection, the abnormality cannot be told to the low-side block. Consequently, the control section M 101  is unaware of the short-circuit state of the high-side block at a ground potential level, and continues to send a turn-on instruction. In that event, enormous energy is applied to the high-side IGBT, leading to immediate destruction. 
     In the conventional system, the low-side power device (IGBT) can be protected against short-circuit to the voltage power supply. However, the high-side power device cannot be protected against short-circuit to the ground potential. The reason why the low-side power device can be protected against short-circuit to the voltage power supply is as follows. The low-side reference potential is equal to the reference potential of the control section. Thus, in the event of abnormality, information on the abnormality can be told to the control section from the low-side driver IC, and a turn-off instruction can be issued to the low-side power device. 
     However, if power to the high side is stopped when a large current in the high-side power device has been detected, the inverter system will halt even in the case of instantaneous flow of large current and the system will not function. Thus, this method cannot be used. 
     BRIEF SUMMARY OF THE INVENTION 
     According to an aspect of the present invention, there is provided a power converter apparatus comprising: a detection circuit which detects whether a power device is in a short-circuit state; a control circuit which sets, when the detection circuit has detected that the power device is in the short-circuit state, the power device in an inoperable state for a predetermined time period, and restores the power device to an operable state after the passing of the predetermined time period; and a time period generating circuit which defines the predetermined time period for setting the power device in the inoperable state, by measuring a time from the detection of the short-circuit state by the detection circuit. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
     FIG. 1 is a circuit diagram showing the structure of a conventional power converter apparatus using photocouplers; 
     FIG. 2 is a circuit diagram showing the structure of a conventional bootstrap-type power converter apparatus using a microcomputer direct driving system and a single power supply; and 
     FIG. 3 is a circuit diagram showing the structure of a power converter apparatus according to an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     An embodiment of the present invention will now be described with reference to the accompanying drawings. 
     FIG. 3 is a circuit diagram showing the structure of a power converter apparatus according to an embodiment of the invention. 
     As is shown in FIG. 3, the power converter apparatus comprises an IGBT  11 , an edge-pulse generating circuit  12 , a bootstrap circuit  13 , a gate control circuit  14 , a short-detection circuit  15 , and an input-prohibit circuit  16 . 
     The edge-pulse generating circuit  12  comprises an edge-pulse circuit  12 A, a comparator CP 1 , diodes D 1  and D 2 , MOS transistors TR 1  and TR 2 , resistors R 1  to R 4 , and a voltage power supply V 1 . The edge-pulse generating circuit  12  receives an input signal IN and outputs an edge-pulse. 
     The bootstrap circuit  13  comprises a capacitor C 1  for bootstrap, comparators CP 2  and CP 3 , resistors R 5  to R 10 , and diodes D 3 , D 4  and D 5 . The bootstrap circuit  13  outputs a generated high voltage to the gate control circuit  14 . 
     The gate control circuit  14  comprises an exclusive NOR gate (EXNOR)  14 A, a filter circuit  14 B, a NOR gate  14 C. The gate control circuit  14  provides a gate voltage to the gate of the IGBT  11  for controlling the operation thereof. 
     The short-detection circuit  15  comprises a comparator CP 4 , a filter circuit  15 A, a latch circuit RH 1 , a power on/reset circuit  15 B, and resistors R 11  to R 14 . The short-detection circuit  15  detects a voltage at a sensing emitter terminal of the IGBT  11  by means of the comparator CP 4 . When the voltage of this emitter terminal is at a predetermined level or more, the output of the comparator CP 4  is input to a C terminal of the latch circuit RH 1  via the filter circuit  15 A. The latch circuit RH 1  delivers to an input terminal of the NOR gate  14 C a signal for turning on the IGBT  11 . 
     The input-prohibit circuit  16  comprises a NAND gate  16 A and six series-connected latch circuits RH 2  to RH 7 . When the short-detection circuit  15  has detected the short-circuit state of the IGBT  11 , the input-prohibit circuit  16  sets a predetermined time period for turning off the IGBT  11 . In other words, the input-prohibit circuit  16  sets an input prohibition time period within which an operational voltage input to the gate of the IGBT  11  is prohibited. In addition, the input-prohibit circuit  16  sets a dead time for eliminating noise or disturbance, after the power is switched on. 
     The power converter apparatus having the above structure operates as follows. 
     After the power is switched on, the input-prohibit circuit  16  sets the dead time for eliminating noise or disturbance. Once the dead time has passed, the edge-pulse generating circuit  12  and bootstrap circuit  13  generate a high voltage. When this high voltage has exceeded a predetermined voltage level, a signal voltage is supplied to the gate control circuit  14 . Upon receiving the signal voltage, the gate control circuit  14  outputs to the gate of the IGBT  11  a gate voltage for controlling the operation of the IGBT  11 . 
     While the IGBT  11  is operating, the short-detection circuit  15  detects a current flowing out of the sensing emitter terminal of the IGBT  11 . If the detection result of the short-detection circuit  15  shows that the IGBT  11  is in a short-circuit state, that is, if the comparator CP 4  has confirmed that the emitter voltage is at a predetermined level or more, the comparator CP 4  delivers a signal voltage to the latch circuit RH 1  via the filter circuit  15 A. 
     Upon receiving the signal voltage, the latch circuit RH 1  outputs to the NOR gate  14 C of gate control circuit  14  a signal for turning off the IGBT  11 . Thereby, the gate control circuit  14  turns off the IGBT  11 . 
     At the same time as the latch circuit RH 1  outputs the signal for turning off the IGBT  11 , the latch circuit RH 1  outputs a signal for starting the input prohibition time period to an input terminal of the NAND gate  16 A of input-prohibit circuit  16 . Thus, a counter comprising the latch circuits RH 2  to RH 7 , which use the input pulse from the inverter control circuit as an oscillation source, begins to operate. The input pulse is divided up to a duration enough to protect the IGBT  11 , and the IGBT  11  is protected with the obtained duration used as the input prohibition time period. 
     Thereafter, when the last stage (latch circuit RH 7 ) of the frequency-division counter of the input-prohibit circuit  16  has become active, the latch circuit RH 1  and the frequency-division counter comprising the latch circuits RH 2  to RH 7  are reset. Thereby, the signal voltage for turning off the IGBT  11 , which is output to the gate control circuit  14 , is stopped and the input prohibition time period is terminated. 
     For example, when the PWM frequency is 3 kHz, a time period of 21 ms is obtained by the input-prohibit circuit  16  with 6 division. The IGBT  11  can be protected by the input prohibition time period of 15 ms. If the input-prohibit circuit  16  is used, the input prohibition time period is terminated, i.e. the protection is released, after the passing of 21 ms. Thereafter, the PWM signal from the control circuit such as a microcomputer is made acceptable once again. Accordingly, if the system is normal, the normal inverter control state is restored. 
     On the other hand, when the high side is shorted to the ground potential from the viewpoint of hardware, a large current flows once again due to the detection of the short-circuit state, and the off-latch is effected by the short-detection circuit  15 . As a result, the IGBT  11  is turned off for a predetermined time period. By the repetition of this operation, the motor control current output from the IGBT  11  becomes abnormal and, as a result, the system halts due to defective position detection, etc. However, the IGBT  11  is not destroyed and can be perfectly protected. 
     As has been described above, according to the present embodiment, when the short-circuit state of the IGBT has been detected, the IGBT is stopped only for a predetermined time period, and then the operable state is restored. Thereby, destruction of the IGBT can be prevented, and the inverter system can normally be operated. 
     According to the embodiment of the present invention, there is provided a power converter apparatus capable of preventing destruction of the power device, without halting the inverter system. 
     Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.