Patent Publication Number: US-6707258-B2

Title: Plasma display panel driving method and apparatus

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims priority to and the benefit of Korean Patent Application No. 2002-26449 filed on May 14, 2002 in the Korean Intellectual Property Office, the content of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     (a) Field of the Invention 
     The present invention relates to a plasma display panel (PDP) driving device and method. More specifically, the present invention relates to a sustain and discharge circuit of a PDP. 
     (b) Description of the Related Art 
     In general, a PDP is a flat plate display for displaying characters or images using plasma generated by gas discharge. Pixels ranging from hundreds of thousands to more than millions are arranged in a matrix form according to the size of the PDP. PDPs are categorized as direct current (DC) PDPs and alternating current (AC) PDPs according to patterns of the waveforms of applied driving voltages and structures of discharge cells. 
     Current directly flows in discharge spaces while a voltage is supplied to the DC PDP, because electrodes of the DC PDP are exposed to the discharge spaces. Therefore, a resistor for restricting the current must be provided to the DC PDP. On the other hand, in the case of the AC PDP, the current is restricted due to the natural formation of a capacitance component because a dielectric layer covers the electrodes. The AC PDP has a longer life than the DC PDP, since the electrodes are protected against shock caused by ions during discharge. 
     In general, a method for driving the AC PDP includes a reset period, an addressing period, a sustain period, and an erase period. 
     In the reset period, the states of the respective cells are reset in order to smoothly address the cells. In the addressing period, the cells that are turned on and the cells that are not turned on in a panel are selected, and wall charges are accumulated to the cells that are turned on (i.e., the addressed cells). In the sustain period, discharge is performed in order to actually display pictures on the addressed cells. In the erase period, the wall charges of the cells are reduced to thereby terminate sustain-discharge. 
     In the AC PDP, since a sustain electrode and a scan electrode for sustain and discharge of the PDP operate as a capacitive load, a capacitor is provided between the scan electrode and the sustain electrode, and it will be equivalently referred to as a panel capacitor hereinafter. Therefore, reactive power is required in addition to the discharging power in order to apply waveforms for the sustain-discharge to the scan and sustain electrodes. A circuit for recovering and re-using the reactive power is referred to as a power recovery circuit. L. F. Weber discloses the power recovery circuits in U.S. Pat. Nos. 4,866,349 and 5,081,400, and Ooba also discloses them in Japanese Patent no. 2,755,201. 
     However, the sustain and discharge circuit proposed by the Weber patent requires an external capacitor used for a power recovery capacitor, the electric potential of which is to maintain half Vs. To achieve this, the capacity of the power recovery capacitor must be much greater than that of the panel capacitor. 
     Also, since the circuit proposed by Ooba has a voltage rising period of an X (or Y) electrode of the panel capacitor that is matched with a voltage falling period of the Y (or X) electrode, it cannot be applied to a PDP that requires different rising and falling periods. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention a power recovery PDP is provided. In one aspect of the present invention, a device for driving a PDP is provided, the PDP having a plurality of scan electrodes and sustain electrodes alternately arranged in pairs, wherein a panel capacitor is formed between the scan electrode and the sustain electrode. A first sustain and discharge unit is coupled to a first electrode of the panel capacitor, and coupled between a first power source for supplying a first voltage and a second power source for supplying a second voltage, for operating so that the first electrode may be maintained to be one of the first and the second voltages. A second sustain and discharge unit is coupled to a second electrode of the panel capacitor, and coupled between the first power source and the second power source so that the second electrode may be maintained to be one of the first and the second voltages. A charge and discharge unit, including at least one inductor coupled to the panel capacitor, is provided for converting a voltage at the second electrode into the second voltage to store energy in the inductor, using the energy stored in the inductor to convert the voltage at the first electrode into the first voltage, converting the voltage at the first electrode into the second voltage to store energy in the inductor, and using the energy stored in the inductor to convert the voltage at the second electrode into the first voltage. 
     The charge and discharge unit converts the voltages at the second and the first electrodes into the second and the first voltages, maintains the voltages at the first and the second electrodes to be the first and the second voltages, respectively, converts the voltages at the first and the second electrodes into the second and the first voltages, and maintains the voltages at the first and the second electrodes to be the second and the first voltages, respectively. 
     In another aspect of the present invention, a method for driving a PDP is provided, the PDP having a panel capacitor formed between a plurality of scan electrodes and a plurality of sustain electrodes alternately arranged with the scan electrodes, at least one inductor coupled to the panel capacitor, and a driver coupled between a first power source for supplying a first voltage and a second power source for supplying a second voltage. (a) The panel capacitor&#39;s voltages are maintained at a first electrode and a second electrode to be the second voltage and the first voltage, respectively. (b) The voltage at the second electrode is converted into the second voltage and storing energy in the inductor. (c) The energy stored in the inductor is used to convert the voltage at the first electrode into the first voltage; (d) maintaining the voltages at the first and the second electrodes to be the first and the second voltages, respectively. (e) The voltage at the first electrode is converted into the second voltage and storing energy in the inductor. (f) The energy stored in the inductor is used to convert the voltage at the second electrode into the first voltage. 
     In still another aspect of the present invention, a method for driving a PDP is provided, the PDP having a panel capacitor formed between a plurality of first and second electrodes alternately arranged in pairs, a first switch and a second switch coupled in series between a first power source for supplying a first voltage and a second power source for supplying a second voltage, wherein a point where the first and the second switches meet is coupled to the first electrode of the panel capacitor, a third switch and a fourth switch coupled in series between the first power source and the second power source, wherein a point where the third and the fourth switches meet is coupled to the second electrode of the panel capacitor, at least one inductor having one end coupled to the point where the first and the second switches meet, and a fifth switch and a sixth switch respectively coupled to the inductor, wherein a point where the fifth and sixth switches meet is coupled to the point where the third and fourth switches meet. (a) The second and the third switches are turned on to maintain voltages at the first and the second electrodes to be the second and the first voltages. (b) The third switch is turned off and the sixth switch is turned on to convert the voltage at the second electrode into the second voltage. (c) The second switch is turned off and the fourth switch is turned on to convert the voltage at the first electrode into the first voltage and maintain the voltage at the second electrode to be the second voltage. (d) The sixth switch is turned off and the first switch is turned on to maintain the voltages at the first and the second electrodes to be the first and the second voltages. (e) The first switch is turned off and the fifth switch is turned on to convert the voltage at the first electrode into the second voltage. (f) The fourth switch is turned off and the second switch is turned on to convert the voltage at the second electrode into the first voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a PDP according to an embodiment of the present invention. 
     FIG. 2 shows a sustain and discharge circuit according to a first embodiment of the present invention. 
     FIGS. 3A through 3F show current paths of respective modes according to the first embodiment of the present invention. 
     FIG. 4 shows an operational timing diagram of the PDP according to the first embodiment of the present invention. 
     FIGS. 5A through 5F show current paths of respective modes according to a second embodiment of the present invention. 
     FIG. 6 shows an operational timing diagram of the PDP according to the second embodiment of the present invention. 
     FIG. 7 shows a conventional operational timing diagram of the PDP. 
     FIG. 8 shows a sustain and discharge circuit according to a third embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     A PDP driving device and method according to certain embodiments of the present invention will be described with reference to drawings. Only certain embodiments of the invention have been shown and described. As will be realized, the invention is capable of modification without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and the invention is not merely limited to the embodiments disclosed. 
     FIG. 1 shows a PDP according to an embodiment of the present invention. As shown, the PDP includes plasma panel  100 , address driver  200 , scan/sustain driver  300 , and controller  400 . 
     Plasma panel  100  includes a plurality of address electrodes A 1  through Am arranged in the column direction, a plurality of scan electrodes Y 1  through Yn (referred to as Y electrodes hereinafter) arranged in the row direction, and a plurality of sustain electrodes X 1  through Xn (referred to as X electrodes hereinafter) alternately arranged with the Y electrodes in the row direction. The X electrodes X 1  through Xn are generated to be matched with respective Y electrodes Y 1  through Yn, and their one ends are commonly coupled. Controller  400  receives external video signals, generates an address driving control signal and a sustain and discharge signal, and respectively supplies the signals to address driver  200  and scan and sustain driver  300 . 
     Address driver  200  receives the address driving control signal from controller  400 , and supplies display data signals for selecting discharging cells to be displayed to the respective address electrodes. Scan and sustain driver  300  receives the sustain and discharge signal from controller  400 , and alternately inputs sustain and discharge pulses to the Y electrodes and the X electrodes. The sustain and discharge process is generated in the discharge cell selected according to the input sustain and discharge pulses. 
     Referring to FIGS. 2 through 4, a sustain and discharge circuit of scan and sustain driver  300  according to the first embodiment of the present invention will now be described. FIG. 2 shows a sustain and discharge circuit according to a first embodiment of the present invention. FIGS.  3 ( a ) through  3 ( f ) show current paths of respective modes according to the first embodiment of the present invention. FIG. 4 shows an operational timing diagram of the PDP according to the first embodiment of the present invention. 
     As shown in FIG. 2, the sustain and discharge circuit includes first and second sustain and discharge units  322  and  324 , and charge and discharge unit  326 . First and second sustain and discharge units  322  and  324  include switches S 1  through S 4 , and charge and discharge unit  326  includes switches S 5  and S 6  and an inductor L. 
     Switches S 1  and S 2  are coupled in series between first power source V 1  and a second power source V 2 , a point where switches S 1  and S 2  meet is coupled to the X electrode of panel capacitor Cp, switches S 3  and S 4  are coupled in series between first and second power sources V 1  and V 2 , and a point where switches S 3  and S 4  meet is coupled to the Y electrode of panel capacitor Cp. 
     Switches S 5  and S 6  are coupled in parallel to one end of inductor L, and a point where switches S 5  and S 6  meet is coupled to the point where switches S 3  and S 4  meet. 
     Referring to FIG. 2, switches S 1  through S 6  are denoted as MOSFETs, and without being restricted to them, any other types of switches may be used. The switches may have body diodes of a pn junction separation configuration of a semiconductor IC. 
     Also, the sustain and discharge circuit may further include diodes D 1  and D 2  between inductor L and switches S 6  and S 5 , and in this instance, diodes D 1  and D 2  break the current that may flow because of the body diodes of switches S 6  and S 5 . 
     Referring to FIGS. 3A through 3F and  4 , sequential variations of the operation of the sustain and discharge circuit will be described. Here, the variations have six modes, and the variations are generated according to manipulations of switches S 1  through S 6 . The LC resonance is not a continuous oscillation, and it is generated when switches S 5  and S 6  are turned on. Namely, the LC resonance represents variations of the voltage and the current caused by the combination of inductor L with panel capacitor Cp. 
     The voltages supplied by first and second power sources V 1  and V 2  are defined to be V 1  and V 2 , respectively. 
     (1) Mode  1  (M 1 ) 
     Referring to FIG.  3 A and an interval M 1  of FIG. 4, the operation of mode  1  will now be described. 
     In mode  1 , switches S 2  and S 3  are turned on, and a current path is formed in order of first power source V 1 , switch S 3 , panel capacitor Cp, switch S 2 , and second power source V 2 , and hence, X and Y electrode voltages Vx and Vy at panel capacitor Cp are maintained at V 2  and V 1 , respectively. 
     (2) Mode  2  (M 2 ) 
     Referring to FIG.  3 B and an interval M 2  of FIG. 4, the operation of mode  2  will now be described. 
     In mode  2 , switch S 3  is turned off and switch S 6  is turned on while switch S 2  is turned on. Current IL at inductor L is increased because of the LC resonance formed from the current path in order of the Y electrode of the panel capacitor, switch S 6 , diode D 1 , and inductor L, and Y electrode voltage Vy at panel capacitor Cp is decreased to V 2 . That is, the energy charged to panel capacitor Cp is stored in inductor L, and since switch S 2  is turned on, X electrode voltage Vx at panel capacitor Cp is maintained to be V 2 . 
     (3) Mode  3  (M 3 ) 
     Referring to FIG.  3 C and an interval M 3  of FIG. 4, the operation of mode  3  will now be described. 
     Switch S 2  is turned off and switch S 4  is turned on when current IL flowing to inductor L reaches a maximum value. X electrode voltage Vx is then increased to V 1  because of current IL flowing to inductor L. That is, the energy stored in inductor L in mode  2  is used to increase X electrode voltage Vx, and since switch S 4  is turned on, Y electrode voltage Vy at panel capacitor Cp is maintained to be V 2 . 
     (4) Mode  4  (M 4 ) 
     Referring to FIG.  3 D and an interval M 4  of FIG. 4, the operation of mode  4  will now be described. 
     Switch S 1  is turned on, and switch S 6  is turned off when current IL flowing to inductor L reaches OA. Since switches S 1  and S 4  are turned on, the X and Y electrode voltages are continuously maintained to be V 1  and V 2 . 
     (5) Mode  5  (M 5 ) 
     Referring to FIG.  3 E and an interval M 5  of FIG. 4, the operation of mode  5  will now be described. 
     In mode  5  (M 5 ), switch S 1  is turned off and switch S 5  is turned on while switch S 4  is turned on. An LC resonance is then formed according to a current path in order of the X electrode of panel capacitor Cp, inductor L, diode D 2 , and switch S 5 . Current IL flowing to inductor L is increased and X electrode voltage Vx at panel capacitor Cp is reduced to V 2  because of the LC resonance. That is, the energy charged to panel capacitor Cp is stored in inductor L, and since switch S 4  is turned on, Y electrode voltage Vy is maintained to be V 2 . 
     (6) Mode  6  (M 6 ) 
     Referring to FIG.  3 F and an interval M 6  of FIG. 4, the operation of mode  6  will now be described. 
     When current IL flowing to inductor L becomes maximum, switch S 2  is turned on and switch S 4  is turned off. Y electrode voltage Vy at panel capacitor Cp is then increased to V 1  because of current IL flowing to inductor L, and current IL is decreased to OA. That is, Y electrode voltage Vy at panel capacitor Cp is increased using the energy stored in inductor L, and since switch S 2  is turned on, X electrode voltage Vx is maintained to be V 2 . 
     According to the first embodiment, rising interval M 3  of X electrode voltage Vx and falling interval M 2  of the Y electrode voltage, and falling interval M 5  of X electrode voltage Vx and rising interval M 6  of the Y electrode voltage, respectively become different. 
     In the first embodiment, a falling interval of one electrode voltage is set to be faster than a rising interval of another electrode voltage, and further, a rising interval of one electrode voltage may be set to be faster than a falling interval of another electrode voltage. A corresponding embodiment will be described with reference to FIGS. 5A through 5F and  6 . 
     FIGS. 5A through 5F show current paths of respective modes according to a second embodiment of the present invention, and FIG. 6 shows an operational timing diagram of the PDP according to the second embodiment of the present invention. 
     As shown, the operation of the PDP according to the second embodiment of the present invention is matched with that of the first embodiment of the present invention, except for the operation of modes  2 ,  3 ,  5 , and  6 . 
     In detail, as shown in FIGS. 5B and 6, switches S 3  and S 6  are turned on in mode  2  (M 2 ) to maintain Y electrode voltage Vy to be V 1 , and increase X electrode voltage Vx to V 1  through the LC resonance. As shown in FIGS. 5C and 6, switches S 1  and S 6  in mode  3  (M 3 ) are turned on to maintain the X electrode voltage to be V 1  and reduce the Y electrode voltage to V 2 . That is, the rising interval of the X electrode voltage is set to be faster than the falling interval of Y electrode voltage Vy. As shown in FIGS. 5D and 6, switches S 1  and S 4  are turned on to maintain X and Y electrode voltages Vx and Vy to be V 1  and V 2 , respectively. 
     As shown in FIGS. 5E and 6, switches S 1  and S 5  are turned on in mode  5  (M 5 ) to maintain X electrode voltage Vx to be V 1  and increase Y electrode voltage Vy to V 1  through the LC resonance. As shown in FIGS. 5F and 6, switches S 3  and S 5  are turned on in mode  6  (M 6 ) to maintain Y electrode voltage Vy to be V 1  and reduce X electrode voltage Vx to V 2 . After this, switches S 2  and S 3  are turned on in the like manner of mode  1  (Ml) to maintain X and Y electrode voltages Vx and Vy to be V 2  and V 1 , respectively. 
     In the first and the second embodiments of the present invention, the power may be recovered without using an external power recovery capacitor. 
     In the first and the second embodiments, the rising interval of one electrode voltage and the falling interval of another electrode voltage are differently set. Further, it is possible to identically set the falling interval and the rising interval in the like manner of the method disclosed by Ooba. Namely, as shown in mode  2  (M 2 ) of FIG. 7, X and Y electrode voltages Vx and Vy may concurrently fall and rise respectively by concurrently turning switches S 2  and S 3  off and turning switch S 6  on. 
     The falling interval and the rising interval of the both electrode voltages of panel capacitor Cp may be set to be identical, but in this case, it is impossible to use a PDP that requires different rising and falling intervals. Also, the PDP&#39;s power consumption is reduced and corresponding luminance is improved when the rising and falling intervals are differentiated in the like manners of the first and the second embodiments, differing from the case of identical rising and falling intervals of both electrode voltages. That is, the efficiency of the PDP is increased. 
     In the first and the second embodiments, a single inductor is used to change X and Y electrode voltages Vx and Vy. In addition, a first inductor for increasing X electrode voltage Vx and decreasing Y electrode voltage Vy, and a second inductor for decreasing X electrode voltage Vx and increasing Y electrode voltage Vy may be used, which will be described referring to FIG.  8 . 
     FIG. 8 shows a sustain and discharge circuit according to a third embodiment of the present invention. 
     As shown, the sustain and discharge circuit according to the third embodiment has a configuration matched with that of the first embodiment except that the sustain and discharge circuit according to the third embodiment includes two inductors L 1  and L 2 . 
     In detail, in the third embodiment, ends of inductors L 1  and L 2  are coupled to ends of switches S 6  and S 5  respectively, and other ends of inductors L 1  and L 2  are coupled in parallel to a point where switches S 1  and S 2  meet. The sustain and discharge circuit according to the third embodiment may further include diodes D 1  and D 2 . Diode D 1  is coupled between inductor L 1  and switch S 6 , and diode D 2  is coupled between inductor L 2  and switch S 5 . Further, diode D 1  may be coupled between inductor L 1  and the point where switches S 1  and S 2  meet, and diode D 2  may be coupled between inductor L 2  and the point where switches S 1  and S 2  meet. 
     The driving timing method according to the first and the second embodiments may be applied to the PDP driving method including a sustain and discharge circuit according to the third embodiment. In this instance, excluding that current flowing inductor L 1  in modes  2  and  3  (M 2  and M 3 ) is different from current flowing inductor L 2  in modes  5  and  6  (M 5  and M 6 ), the operation of the third embodiment is identical with the operation of the first or the second embodiment. 
     For example, referring to FIG. 4, respective Y electrode voltages Vy fall and X electrode voltages Vx rise according to the current path in order of panel capacitor Cp, switch S 6 , diode D 1 , and inductor L 1  in modes  2  and  3  (M 2  and M 3 ). Respective X electrode voltages Vx fall and Y electrode voltages Vy rise according to the current path in order of panel capacitor Cp, inductor L 2 , diode D 2 , and switch S 5  in modes  5  and  6  (M 5  and M 6 ). 
     According to the present invention, the power may be recovered without using an external capacitor, and the rising and falling intervals of the X and Y electrode voltages become different, and accordingly, this method may be applied to a PDP that requires different rising and falling intervals. The power consumption is also reduced and the luminance is improved compared to a case in which the rising and falling intervals are matched. 
     While this invention has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.