Patent Publication Number: US-2023135742-A1

Title: Semiconductor device and method for fabricating the same

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation application of U.S. application Ser. No. 16/859,959, filed on Apr. 27, 2020, which is a division of U.S. application Ser. No. 15/859,775, filed on Jan. 2, 2018. The contents of these applications are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a method for fabricating semiconductor device, and more particularly to a method for dividing fin-shaped structure to form single diffusion break (SDB) structure. 
     2. Description of the Prior Art 
     With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate. 
     In current FinFET fabrication, after shallow trench isolation (STI) is formed around the fin-shaped structure part of the fin-shaped structure and part of the STI could be removed to form a trench, and insulating material is deposited into the trench to form single diffusion break (SDB) structure or isolation structure. However, the integration of the SDB structure and metal gate fabrication still remains numerous problems. Hence how to improve the current FinFET fabrication and structure has become an important task in this field. 
     SUMMARY OF THE INVENTION 
     According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure. 
     According to another aspect of the present invention, a semiconductor device includes: a fin-shaped structure on a substrate; a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure; and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion comprise different widths. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a top view illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. 
         FIG.  2    illustrates a cross-sectional view of  FIG.  1    for fabricating the semiconductor device along the sectional line AA′. 
         FIGS.  3 - 10    illustrate a method for fabricating the semiconductor device following  FIG.  2   . 
         FIG.  11    illustrates a structural view of a semiconductor device according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIGS.  1 - 10   , in which  FIG.  1    is a top view illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention,  FIG.  2    illustrates a cross-sectional view of  FIG.  1    for fabricating the semiconductor device along the sectional line AA′, and  FIGS.  3 - 10    illustrate a method for fabricating the semiconductor device following  FIG.  2   . As shown in  FIGS.  1 - 2   , a substrate  12 , such as a silicon substrate or silicon-on-insulator (SOI) substrate is first provided, and a plurality of fin-shaped structures  14  are formed on the substrate  12 . It should be noted that even though four fin-shaped structures  14  are disposed on the substrate  12  in this embodiment, it would also be desirable to adjust the number of fin-shaped structures  14  depending on the demand of the product, which is also within the scope of the present invention. 
     Preferably, the fin-shaped structures  14  of this embodiment could be obtained by a sidewall image transfer (SIT) process. For instance, a layout pattern is first input into a computer system and is modified through suitable calculation. The modified layout is then defined in a mask and further transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process. In this way, several sacrificial layers distributed with a same spacing and of a same width are formed on a substrate. Each of the sacrificial layers may be stripe-shaped. Subsequently, a deposition process and an etching process are carried out such that spacers are formed on the sidewalls of the patterned sacrificial layers. In a next step, sacrificial layers can be removed completely by performing an etching process. Through the etching process, the pattern defined by the spacers can be transferred into the substrate underneath, and through additional fin cut processes, desirable pattern structures, such as stripe patterned fin-shaped structures could be obtained. 
     Alternatively, the fin-shaped structures  14  could also be obtained by first forming a patterned mask (not shown) on the substrate,  12 , and through an etching process, the pattern of the patterned mask is transferred to the substrate  12  to form the fin-shaped structures  14 . Moreover, the formation of the fin-shaped structures  14  could also be accomplished by first forming a patterned hard mask (not shown) on the substrate  12 , and a semiconductor layer composed of silicon germanium is grown from the substrate  12  through exposed patterned hard mask via selective epitaxial growth process to form the corresponding fin-shaped structures  14 . These approaches for forming fin-shaped structure are all within the scope of the present invention. 
     Next, a shallow trench isolation (STI)  16  is formed around the fin-shaped structures  14 . In this embodiment, the formation of the STI  16  could be accomplished by conducting a flowable chemical vapor deposition (FCVD) process to form a silicon oxide layer on the substrate  12  and covering the fin-shaped structures  14  entirely. Next, a chemical mechanical polishing (CMP) process along with an etching process are conducted to remove part of the silicon oxide layer so that the top surface of the remaining silicon oxide is slightly lower than the top surface of the fin-shaped structures  14  for forming the STI  16 . 
     Next, gates structures  18 ,  20 ,  22 ,  24  or dummy gates are formed on the fin-shaped structure  14 . In this embodiment, the formation of the gate structures  18 ,  20 ,  22 ,  24  could be accomplished by a gate first process, a high-k first approach from gate last process, or a high-k last approach from gate last process. Since this embodiment pertains to a high-k last approach, a gate dielectric layer or interfacial layer, a gate material layer made of polysilicon, and a selective hard mask could be formed sequentially on the substrate  12 , and a photo-etching process is then conducted by using a patterned resist (not shown) as mask to remove part of the gate material layer and part of the gate dielectric layer through single or multiple etching processes. After stripping the patterned resist, gate structures  18 ,  20 ,  22 ,  24  each composed of a patterned gate dielectric layer  26  and a patterned material layer  28  are formed on the fin-shaped structure  14 . 
     Next, at least a spacer  30  is formed on the sidewalls of the each of the gate structures  18 ,  20 ,  22 ,  24 , a source/drain region  32  and/or epitaxial layer  34  is formed in the fin-shaped structure  14  adjacent to two sides of the spacer  30 , and selective silicide layers (not shown) could be formed on the surface of the source/drain regions  32 . In this embodiment, the spacer  30  could be a single spacer or a composite spacer, such as a spacer including but not limited to for example an offset spacer and a main spacer. Preferably, the offset spacer and the main spacer could include same material or different material while both the offset spacer and the main spacer could be made of material including but not limited to for example SiO 2 , SiN, SiON, SiCN, or combination thereof. The source/drain regions  32  could include n-type dopants or p-type dopants depending on the type of device being fabricated. 
     Next, a contact etch stop layer (CESL)  36  is formed on the gate structures  18 ,  20 ,  22 ,  24  and the STI  16 , and an interlayer dielectric (ILD) layer  38  is formed on the CESL  36 . Next, a planarizing process such as CMP is conducted to remove part of the ILD layer  38  and part of the CESL  36  for exposing the gate material layer  28  made of polysilicon, in which the top surface of the gate material layer  28  is even with the top surface of the ILD layer  36 . 
     Next, as shown in  FIG.  3   , a replacement metal gate (RMG) process is conducted to transform the gate structures  18 ,  20 ,  22 ,  24  into metal gates. For instance, the RMG process could be accomplished by first performing a selective dry etching or wet etching process using etchants including but not limited to for example ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer  28  and even gate dielectric layer  26  from each of the gate structures  18 ,  20 ,  22 ,  24  for forming recesses (not shown) in the ILD layer  38 . 
     Next, a selective interfacial layer  40  or gate dielectric layer (not shown), a high-k dielectric layer  42 , a work function metal layer  44 , and a low resistance metal layer  46  are formed in the recesses, and a planarizing process such as CMP is conducted to remove part of low resistance metal layer  46 , part of work function metal layer  44 , and part of high-k dielectric layer  42  to form metal gates  48 ,  50 ,  52 ,  54 . In this embodiment, the gate structures or metal gates  48 ,  50 ,  58 ,  54  fabricated through high-k last process of a gate last process preferably includes an interfacial layer  40  or gate dielectric layer (not shown), a U-shaped high-k dielectric layer  42 , a U-shaped work function metal layer  44 , and a low resistance metal layer  46 . 
     In this embodiment, the high-k dielectric layer  42  is preferably selected from dielectric materials having dielectric constant (k value) larger than 4. For instance, the high-k dielectric layer  50  may be selected from hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), barium strontium titanate (Ba x Sr 1-x TiO 3 , BST) or a combination thereof. 
     In this embodiment, the work function metal layer  44  is formed for tuning the work function of the metal gate in accordance with the conductivity of the device. For an NMOS transistor, the work function metal layer  44  having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is not limited thereto. For a PMOS transistor, the work function metal layer  44  having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto. An optional barrier layer (not shown) could be formed between the work function metal layer  44  and the low resistance metal layer  46 , in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). Furthermore, the material of the low-resistance metal layer  46  may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof. 
     Next, as shown in  FIG.  4   , an etching process is conducted to remove part of the low resistance metal layer  46 , part of the work function metal layer  44 , and part of the high-k dielectric layer  42  for forming recesses  56 . 
     Next, as shown in  FIG.  5   , a hard mask  58  is formed to fill the recesses  56  and disposed on the CESL  36  and the ILD layer  38 . In this embodiment, the hard mask  58  is made of dielectric material including but not limited to for example silicon nitride. 
     Next, as shown in  FIG.  6   , a patterned mask such as a patterned resist  60  is formed on the hard mask  58 , in which the patterned resist  60  includes an opening  62  exposing part of the hard mask  58  surface. 
     Next, as shown in  FIG.  7   , an etching process or more specifically one or more etching processes are conducted by using the patterned resist  60  as mask to remove part of the hard mask  58 , part of the CESL  36 , part of the spacer  30 , and part of the metal gate  52  for forming a trench  64  in the ILD layer  38  and the hard mask  58  directly above the metal gate  52 , and the patterned resist  60  is removed thereafter. In this embodiment, the removal of part of the hard mask  58  could be accomplished by using an etching gas such as but not limited to for example carbon tetrafluoride (CF 4 ). 
     Next, as shown in  FIG.  8   , another etching process or one or more additional etching process could be conducted by using the patterned hard mask  58  as mask to remove the remaining metal gate  52  and part of the fin-shaped structure  14  directly under the metal gate  52 . This forms a substantially T-shaped trench  66  in the spot of the original metal gate  52  and the lower portion of the trench  66  is preferably extended into the fin-shaped structure  14 . In this embodiment, the removal of the remaining metal gate  52  could be accomplished by using an etching such as but not limited to for example sulfur hexafluoride (SF 6 ). 
     It should be noted that since the trench  66  is formed by removing the original metal gate  52 , the extending direction of the trench  66  is preferably the same as the extending direction of the original gate structure  22  or metal gate  52 . In other words, in contrast to the fin-shaped structures  14  extending along a first direction (such as X-direction) shown in  FIG.  1   , the trench  66  is preferably extending along a second direction (such as Y-direction) orthogonal to the first direction. 
     Next, as shown in  FIG.  9   , a liner  68  and a dielectric layer  70  are sequentially formed on the hard mask  58  and filled into the trench  66 , in which the liner  68  and the dielectric layer  70  are preferably made of different material while the two layers  68  and  70  could be selected from the group consisting of silicon oxide and silicon nitride. For example, it would be desirable to sequentially deposit a liner  68  made of silicon nitride and a dielectric layer  70  made of silicon oxide into the trench  66 , or sequentially deposit a liner  68  made of silicon oxide and a dielectric layer  70  made of silicon nitride into the trench  66 , which are all within the scope of the present invention. 
     Next, as shown in  FIG.  10   , a planarizing process such as CMP and/or etching back process is conducted to remove part of the dielectric layer  70 , part of the liner  68 , and part of the hard mask  58  so that the top surface of the remaining dielectric layer  70  and liner  68  is even with the top surface of the ILD layer  38  and the remaining hard mask  58  to form a single diffusion break (SDB) structure  72 . Similar to the extending direction of the trench  66 , the SDB structure  72  formed at this stage is also extending along a second direction (such as Y-direction) orthogonal to the first direction (such as X-direction) of the fin-shaped structures  14  shown in  FIG.  1   . 
     Referring again to  FIG.  10   , which further illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown in  FIG.  10   , the semiconductor device includes a fin-shaped structure  14  on the substrate  12 , gate structure or metal gate  48 ,  50 ,  54  disposed on the fin-shaped structure  14 , an ILD layer  38  surrounding the metal gates  48 ,  50 ,  54 , a SDB structure  72  disposed in the ILD layer  38  and the fin-shaped structure  14 , a spacer  30  around the metal gates  48 ,  50 ,  54 , and the SDB structures  72 , and a CESL  36  disposed between the spacers  30 . 
     Viewing from a more detailed perspective, the SDB structure  72  further includes a bottom portion  76  and a top portion  78  on the bottom portion  76 , in which the top portion  78  and the bottom portion  76  include different widths, or more specifically the width of the top portion  78  is preferably greater than the width of the bottom portion  76 . Each of the top portion  78  and the bottom portion  76  also includes a liner  68  and a dielectric layer  70  disposed on the liner  68  and the liner  68  and the dielectric layer  70  are preferably made of different material. 
     It should be noted that the spacers  30  surrounding the metal gates  48 ,  50 ,  54  and the SDB structure  72  preferably include different heights. For instance, the top surface of the spacer  30  surrounding the metal gate  50  is even with the top surface of the ILD layer  38  and higher than the top surface of the spacer  30  surrounding the SDB structure  72 , and the top surface of the spacer  30  surrounding the SDB structure  72  on the other hand is even with the top surfaces of the bottom portion  76  and the CESL  36 . It should also be noted that even though the CESL  36  has a relatively U-shaped cross-section, the top surface of the CESL  36  adjacent to the SDB structure  72  is slightly lower than the top surface of the CESL  36  adjacent to the metal gate  50 . 
     Referring to  FIG.  11   ,  FIG.  11    illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown in  FIG.  11   , it would also be desirable to conduct the planarizing process including a CMP process and/or etching back to remove part of the dielectric layer  70 , part of the liner  68 , and part of the hard mask  58  for forming the SDB structure  72  while forming an air gap  74  within the SDB structure  72 , which is also within the scope of the present invention. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.