Patent Publication Number: US-6906593-B2

Title: Frequency compensation of wide-band resistive gain amplifier

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
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   STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
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   BACKGROUND OF THE INVENTION 
   The present invention relates to techniques for compensating for parasitic capacitance associated with the gain resistors of an operational amplifier circuit, and in particular compensating for the extra phase shift introduced by the parasitic poles due to this parasitic capacitance. 
     FIG. 1  illustrates a resistive gain amplifier circuit having an operational amplifier  10  with resistors R 1 , R 2 , R 3  and R 4  connected between a voltage input  12  and a voltage output  14 . A switch  16  determines a connection to the inverting input of operational amplifier  10  between a point A (between R 4  and R 3 ), a point B (between R 3  and R 2 ), and a point C (between R 2  and R 1 ). Depending upon which position is selected, the gain of the amplifier is varied accordingly. Each of the resistors, when constructed on a semiconductor chip, will have associated parasitic capacitance between the resistor and the substrate. These parasitic capacitances are modeled in the circuit of  FIG. 1  as capacitors between the resistor and ground (since the substrate is grounded). Thus, resistor R 4  has parasitic capacitance C 42  and C 41 . Resistor R 3  has parasitic capacitance C 32  and C 31 . Resistor R 2  has parasitic capacitance C 22  and C 21 . Resistor R 1  has parasitic capacitance C 12  and C 11 . Also shown in  FIG. 1  are the load resistance and capacitance, RL and CL, connected to ground. 
   A problem with the circuit of  FIG. 1  is that for high-frequency gain, the parasitic capacitances cause a degradation of the phase margin to the point of instability, rendering such high gain stages difficult to frequency compensate. 
   Depending on the type of resistor material, i.e., diffusion or polysilicon, the capacitors are either junction capacitors or polysilicon-to-substrate capacitances. These capacitances, together with the resistors, introduce additional phase shift in the feedback loop, degrading the phase margin and frequency stability of the operational amplifier. The effect on the phase margin becomes more severe for larger resistors or wider band amplifiers as the extra poles due to these resistor/capacitor (RC) circuits are pulled into the bandwidth of the amplifier. 
   One approach to dealing with a parasitic capacitance or resistor is shown in U.S. Pat. No. 6,472,942. This patent adds a parallel capacitance in order to compensate for the parasitic substrate capacitance. In other words, this patent attempts to create a zero to compensate for the pole induced by the parasitic capacitance. A similar approach is shown in U.S. Pat. No. 6,005,280. Here, a resistor is shown extending over two different n-wells. One of the n-wells is connected to ground, and the other is connected to the output. Again, this attempts to put a zero on top of a pole in order to compensate for the parasitic capacitance. 
   U.S. Pat. No. 5,880,634 also shows a method for compensating for the parasitic capacitance by canceling out the parasitic capacitance. This is done by including a compensation capacitor C c  adding a value equal to ⅙ of the parasitic capacitance. 
   BRIEF SUMMARY OF THE INVENTION 
   The present invention provides a unique and straightforward technique for minimizing the effect of parasitic capacitance in a resistive gain amplifier. Instead of the resistors being formed directly over the substrate, or over an oxide of the substrate, a semiconductor element (e.g., an n-well) is used between the resistor and the substrate. For resistors in the input circuit, this semiconductor element or n-well is connected to the voltage input rather than ground. For the resistors in the feedback loop circuit, the semiconductor element or n-well is connected to the voltage output of the operational amplifier. The insertion of this semiconductor element or n-well provides the ability to programmably connect the parasitic capacitance to somewhere other than ground. By connecting the parasitic capacitance to the voltage input or voltage output, the ground connection is eliminated, eliminating the pole introduced by the parasitic capacitance. Thus, there is no need to delicately match a compensation capacitor or use the other techniques of the prior art. 
   In one embodiment, a number of resistors are included between the voltage input and the voltage output, and these resistors can be programmably connected to vary the number of resistors in either the input circuit or the feedback circuit. The n-wells in which these resistors are formed can be correspondingly connected, programmably, to either the voltage input or the voltage output depending upon where the resistor itself is connected. Thus, the poles associated with the parasitic capacitances are changed to transmission zeros, significantly improving the phase margin of the operational amplifier circuit. 
   For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a circuit diagram of a prior art operational amplifier with programmable gain. 
       FIG. 2  is a circuit diagram of an embodiment of the present invention applied to the circuit of FIG.  1 . 
       FIG. 3  is cross-sectional view of one embodiment of a resistor in an n-well according to the present invention. 
       FIG. 4  is a diagram illustrating an n-well with multiple elements for programming a resistor size according to an embodiment of the present invention. 
       FIG. 5  is a circuit diagram illustrating the logic for providing the connections to an operational amplifier circuit according to the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2  illustrates the principle of the present invention applied to the circuit of FIG.  1 . As can be seen, the parasitic capacitances C 31 , C 32 , C 41  and C 42  are now connected to the voltage input  12  rather than ground as in FIG.  1 . Similarly, parasitic capacitances C 22 , C 21 , C 12  and C 11  are connected to the voltage output  14  rather than ground. These connections are for the particular configuration where node B is connected to the inverting input of operational amplifier  10 , putting resistors R 1  and R 2  in the feedback loop and resistors R 3  and R 4  in the input circuit. The ability to connect the capacitances as shown is provided by using a semiconductor layer to enable a connection between the resistor and substrate. In one embodiment, this is done using an n-well as illustrated in FIG.  3 . 
     FIG. 3  is a cross-sectional view showing a semiconductor structure with a p-substrate  20  above which is an n-well  22 . Placed over the n-well is a polysilicon resistor  24 . Although shown as a serpentine arrangement for the resistor, other structures could be used. Resistor  24  has contact regions  26  and  28  for making the connections to the resistor as desired. Also, a connection  30  to the n-well is provided, enabling the n-well to be connected either to the voltage input or voltage output. Typically, the p-substrate  20  is connected to ground. Thus, absent the n-well, the parasitic capacitance would be connected to ground as illustrated in FIG.  1 . 
     FIG. 4  illustrates one alternate resistor structure in which an n-well region  32  includes a number of polysilicon regions  34  that can be interconnected by metal layers  36  as shown to provide programmable sizes for the resistor. As illustrated, a group of four polysilicon strips are connected together to provide the resistors, but other sizes could be used as well. For example, all regions could be connected together, only one could be used, etc. 
     FIG. 5  is a diagram illustrating the connection logic according to one embodiment of the present invention. This embodiment shows six resistors instead of the four resistors of prior diagrams. These resistors are R 5 -R 10 . Shown is a switching circuit  40  that can alternately connect to nodes  42  (between R 5  and R 6 ),  43 ,  44 ,  46  or  48 . Shown beneath the resistors are the n-wells in which the resistors are formed. The n-wells for resistors R 5  and RIO are shown already connected to the voltage input  12  and the voltage output  14 , respectively. The remaining n-wells are connected to transistor switches such as switches  50 ,  52 ,  54  and  56  that can connect the n-well to either voltage input  12  or voltage output  14 . These transistors are controlled by a logic circuit  60  that determines where the n-wells are connected. Logic circuit  60  responds to a digital value in a register  62  that is input through a programming input  64 . Register  62  programs switch  40  to select the combination of resistors and thus program the gain of the operational amplifier circuit. Logic  60  observes this programming and accordingly programs the n-wells so that the n-wells associated with resistors in the input circuit are connected to the voltage input  12 , while the n-wells associated with the feedback circuit are connected to the output  14 . Logic circuit  60  could be eliminated in one embodiment, with register  62  directly connecting to the transistor switches or other types of switches connecting the n-wells to the voltage input or voltage output. 
   As will be understood by those of skill in the art, the present invention could be embodied in other specific forms without departing from the essential characteristics thereof. For example, eight resistors could be used instead of six, or any other number for the programmable circuit. Instead of an n-well, any other conductive or semi-conductive layer could be used as the plate of the capacitor. For example, a metal layer could be used for a metal resistor. Instead of polysilicon resistors, the resistors could be P+ material. The switches could be transmission gates or any other type of switching circuit. Accordingly, the foregoing description is intended to be illustrative, but not limiting, of the scope of the invention that is set forth in the following claims.