Patent Publication Number: US-7211894-B2

Title: Capacitor-related systems for addressing package/motherboard resonance

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This is a divisional of prior U.S. patent application Ser. No. 10/602,096, filed Jun. 23, 2003 now U.S. Pat. No. 6,992,387. 

   BACKGROUND 
   Integrated circuit packages provide physical protection to an integrated circuit. Packages may also provide thermal and electrical management to the integrated circuit. More specifically, an integrated circuit package may dissipate heat generated by an integrated circuit and electrically connect the integrated circuit to external circuitry. In the latter regard, a conventional package may provide power and ground planes as well as integrated capacitors for distributing and routing electrical signals between an integrated circuit and a motherboard. The transmission of these signals often results in unwanted resonance between the motherboard and the package, which negatively affects the performance of the integrated circuit. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a side elevation of a system according to some embodiments. 
       FIG. 2  is a top view of a capacitor pad design according to some embodiments. 
       FIG. 3  is a side cutaway view of a package including a capacitor pad design according to some embodiments. 
       FIG. 4  is a top view of a capacitor pad design according to some embodiments. 
       FIG. 5A  includes a representation of an upper surface and terminals extending from a lower surface of a device according to some embodiments. 
       FIG. 5B  illustrates connections between terminals and conductive planes of the  FIG. 5A  device according to some embodiments. 
       FIG. 5C  is a graphical comparison of impedance profiles for the  FIG. 5A  device and for a conventional device according to some embodiments. 
       FIG. 6A  includes a representation of terminals extending from an upper surface and terminals extending from a lower surface of a device according to some embodiments. 
       FIG. 6B  illustrates connections between terminals and conductive planes of the  FIG. 6A  device according to some embodiments. 
       FIG. 6C  is a graphical comparison of impedance profiles for the  FIG. 6A  device and for a conventional device according to some embodiments. 
       FIG. 7A  includes a representation of an upper surface and terminals extending from a lower surface of a device according to some embodiments. 
       FIG. 7B  illustrates connections between terminals and conductive planes of the  FIG. 7A  device according to some embodiments. 
       FIG. 7C  is a graphical comparison of impedance profiles for the  FIG. 7A  device and for a conventional device according to some embodiments. 
       FIG. 8A  includes a representation of terminals extending from an upper surface and terminals extending from a lower surface of a device according to some embodiments. 
       FIG. 8B  illustrates connections between terminals and conductive planes of the  FIG. 8A  device according to some embodiments. 
       FIG. 8C  is a graphical comparison of impedance profiles for the  FIG. 8A  device and for a conventional device according to some embodiments. 
       FIG. 9A  includes a representation of terminals extending from a surface of a device according to some embodiments. 
       FIG. 9B  illustrates conductive planes of the  FIG. 9A  device according to some embodiments. 
       FIG. 9C  is a graphical comparison of impedance profiles for the  FIG. 9A  device and for a conventional device according to some embodiments. 
       FIG. 10A  includes a representation of terminals extending from a surface of a device according to some embodiments. 
       FIG. 10B  illustrates conductive planes of the  FIG. 10A  device according to some embodiments. 
       FIG. 11A  includes a representation of terminals extending from a surface of a device according to some embodiments. 
       FIG. 11B  illustrates conductive planes of the  FIG. 11A  device according to some embodiments. 
       FIG. 12A  includes a representation of terminals extending from a surface of a device according to some embodiments. 
       FIG. 12B  illustrates conductive planes of the  FIG. 12A  device according to some embodiments. 
       FIG. 13  includes a representation of terminals extending from a surface of a device according to some embodiments. 
       FIG. 14  includes a representation of terminals extending from a surface of a device according to some embodiments. 
       FIG. 15  includes a representation of terminals extending from a surface of a device according to some embodiments. 
   

   DETAILED DESCRIPTION 
     FIG. 1  is a side elevation of system  100  according to some embodiments. System  100  includes integrated circuit  200 , package  300 , motherboard  400  and memory  500 . Integrated circuit  200  may be fabricated using any suitable substrate material and fabrication technique and may provide any functions to system  100 . In some embodiments, integrated circuit  200  is a microprocessor chip having a silicon substrate. 
   Package  300  may comprise any ceramic, organic, and/or other suitable material. Package  300  is electrically coupled to circuit  200  by Controlled Collapse Chip Connect (C4) solder bumps  250 . Package  300  therefore comprises an interface compatible with C4 solder bumps  250 . In some embodiments, package  300  is electrically coupled to circuit  200  via wirebonds. Capacitors  310  through  340  are mounted on package  300 . Terminals of capacitors  310  through  340  may be mounted using surface mount techniques on power and ground pads of package  300 . Power and ground pads according to some embodiments will be described in detail below. 
   Pins  350  couple package  300  to motherboard  400 . In this regard, package  300  and pins  350  may comprise a flip-chip pin grid array to interface with a socket (not shown) of motherboard  400 . According to some embodiments, package  300  is a surface-mountable substrate such as an Organic Land Grid Array substrate that may be mounted directly on motherboard  400  or mounted on a pinned interposer which mates with a socket of motherboard  400 . Packaging systems other than those mentioned above may be used in conjunction with some embodiments. 
   Integrated circuit  200  may communicate with memory  500  through package  300  and motherboard  400 . Memory  500  may comprise any type of memory for storing data, such as a Single Data Rate Random Access Memory, a Double Data Rate Random Access Memory, or a Programmable Read Only Memory. 
     FIG. 2  is a top view of a capacitor pad design according to some embodiments.  FIG. 2  shows power plane  302  of package  300 . Power plane  302  may be designed to carry a supply voltage to circuit  200 . Accordingly, any of C4 balls  250  may connect to power plane  302  to receive the supply voltage. 
   Power plane  302  includes power pad  304 . Power pad  304  may receive a terminal of a circuit element such as a capacitor. Power pad  304  may simply comprise a region of power plane  302  and/or may comprise material that is built up on the region to facilitate reception of the terminal. 
   Ground pad  306  may receive a second terminal of the circuit element. As will be described below, ground pad  306  is electrically coupled to a ground plane of package  300 . Accordingly, ground pad  306  may be surrounded by non-conducting region  307  to avoid short-circuiting the ground plane with power plane  302 . Ground pad  306  is electrically coupled to a ground plane of package  300  through via area  308 . Via area  308  is substantially coplanar with ground pad  306  and is electrically coupled to ground pad  306  by trace  309 . Via area  308  is separated from ground pad  306  in that via area is not to receive a terminal of the circuit element. 
     FIG. 3  shows a side cutaway view of package  300  and capacitor  310  according to some embodiments.  FIG. 3  shows power plane  302 , power pad  304 , ground pad  306 , and non-conducting region  307  of  FIG. 2 . Also shown are terminals  312  and  314  of capacitor  310  coupled to ground pad  306  and power pad  304 , respectively. Ground plane  316  may provide circuit  200  with a path to ground and is coupled to via area  308  by via  318 . 
   In operation, current flows consecutively through power plane  302 , power pad  306 , terminal  314 , terminal  312 , ground pad  306 , trace  309 , via area  308 , via  318 , and ground plane  316 . Conventional systems do not include trace  309  or via area  308 . Rather, via  318  may be located at the location shown in  FIG. 3  by a dotted line. The longer current path may cause the equivalent series resistance of capacitor  310  to be greater than that of conventional systems. Accordingly, some embodiments may provide an efficient system to reduce resonance between package  300  and motherboard  400  by increasing an equivalent series resistance of package capacitors. 
     FIG. 4  illustrates a second capacitor pad design according to some embodiments. The design includes power plane  302 , which includes power pad  304  to receive a terminal of a circuit element. Also included are ground pad  306  to receive a second terminal of the circuit element and via area  308 . Via area  308  of  FIG. 4  is substantially coplanar with ground pad  306 , is separated from ground pad  306 , and is electrically coupled to ground pad  306  by trace  309 . The  FIG. 4  design also comprises a via (not shown to electrically couple via area  308  to a ground plane (not shown). 
     FIG. 5A  includes representations of a device according to some embodiments. Shown in  FIG. 5  are two representations of device  600 . Device  600  may comprise one or more individual capacitors according to some embodiments. Any of capacitors  310  through  340  may comprise device  600  according to some embodiments. In this regard, any of the devices described below may be disposed on package  300  similarly to capacitors  310  through  340 . 
   As shown, upper surface  605  of device  600  consists of the material of which device  600  is composed. This material may be ceramic, organic, plastic and/or any other suitable material. Lower surface  610  of device  600  includes the aforementioned material as well as terminals  611  through  618 . Terminals  611  through  618  may comprise pins, surface mount terminals, or any other type of device terminal. Terminals  611  through  614  are associated with a first polarity (positive), while terminals  615  through  618  are associated with a second polarity (negative). 
     FIG. 5B  is a side cutaway representation of device  600  according to some embodiments. The representation shows terminals  617 ,  613 ,  618  and  614 , each of which is coupled to several conductive planes. In particular, terminal  617  is coupled to each of conductive planes  620  through  627  and terminal  618  is coupled to conductive planes  620  through  622 . Conductive planes  620  through  627  are therefore associated with the same polarity (negative) as are terminals  617  and  618 . Terminal  614  is coupled to each of conductive planes  630  through  637  and terminal  613  is coupled to conductive planes  630  through  632 . As above, conductive planes  630  through  637  are associated with the same polarity (positive) as are terminals  613  and  614 . 
   Each of the conductive planes  630  through  637  is separated from at least one of conductive planes  620  through  627  by a dielectric material. Accordingly, a capacitance is present between two terminals of device  600  that are associated with different polarities. For example, a first capacitance is present between terminal  617  and  613 . A second capacitance is also present between terminals  618  and  614 . According to some embodiments, a sum of the first capacitance and the second capacitance is substantially equal to the capacitance between terminals  617  and  614 . 
     FIG. 5C  is a graphical comparison of impedance profiles for device  600  and for a conventional device according to some embodiments. In a conventional device, each terminal that is associated with a given polarity is connected to all planes of the device that are also associated with the given polarity. As a result, a same capacitance is present between any two terminals of opposite polarity. 
     FIG. 5C  illustrates that embodiments may provide a more uniform impedance profile than a conventional device by connecting the first and the second capacitances of device  600  in parallel. The existence of fewer terminals for each capacitance also may increase the equivalent series resistance of the total capacitance. Each of these factors may reduce resonance between a motherboard and a package on which device  600  is mounted. 
     FIG. 6A  includes representations of a device according to some embodiments. Device  700  may comprise one or more individual capacitors according to some embodiments. In contrast to device  600 , upper surface  705  of device  700  consists of package material and terminals  710  through  717 . 
   Terminals  710  through  713  are associated with a first polarity (positive), and terminals  714  through  717  are associated with a second polarity (negative). Lower surface  720  includes the package material as well as terminals  721  through  728 . Terminals  721  through  724  are associated with the first polarity, while terminals  725  through  728  are associated with the second polarity. The presence of terminals on surface  705  and surface  720  may facilitate manufacture and/or use of device  700 . 
     FIG. 6B  is a side cutaway representation of device  700  according to some embodiments. Terminals  727 ,  723 ,  728  and  724  are coupled to conductive planes in an arrangement similar to terminals  617 ,  613 ,  618  and  614  of  FIG. 5B . Additionally, terminal  716  is coupled to each of conductive planes  720  through  727  and terminal  717  is coupled to conductive planes  725  through  727 . Terminal  713  is coupled to each of conductive planes  730  through  737  and terminal  712  is coupled to conductive planes  735  through  737 . 
   Terminals  727 ,  723 ,  728  and  724  are configured similarly to terminals  617 ,  613 ,  618  and  614  of device  600  and therefore operate as described above. Terminals  716 ,  712 ,  717 , and  713  also operate similarly to terminals  617 ,  613 ,  618  and  614  of device  600 . More particularly, a first capacitance is present between terminal  716  and  712 , a second capacitance is present between terminals  717  and  713 , and a sum of the first capacitance and the second capacitance is substantially equal to the capacitance between terminals  713  and  716 . 
     FIG. 6C  is a graphical comparison of impedance profiles for device  700  and for a conventional device according to some embodiments. The impedance profile for device  700  is similar to that illustrated in  FIG. 5C  for device  600 , since terminals of each surface of device  700  are configured similarly to the terminals of device  600 . 
     FIG. 7A  includes representations of a device according to some embodiments. Device  800  is similar to device  600  in that no terminals are present on upper surface  805 . Moreover, lower surface  810  includes terminals  811  through  814  associated with a first polarity (positive), and terminals  815  through  818  associated with a second polarity (negative). 
   The side cutaway representation of device  800  shown in  FIG. 7B  is also similar to device  600 . However, terminal  818  is coupled to more conductive planes than terminal  813 . As a result, a first capacitance is present between terminal  817  and  813 , a second capacitance is present between terminals  813  and  818 , and third capacitance is present between terminals  817  and  814 . The three different capacitances may result in an impedance profile such as that illustrated in  FIG. 7C . The impedance profile may be flatter than that provided by embodiments such as device  600  and  700  because of the additional impedance power droop resulting from the third capacitance. 
     FIG. 8A  includes representations of a device according to some embodiments. Device  900  is similar to device  700  in that terminals are located both on upper surface  905  and on lower surface  910 . As shown in  FIG. 8B , device  900  is unlike device  700  in that terminals  913  and  922  are connected to a different number of conductive planes. However, terminals  913  and  927  are connected to an equal number of conductive planes. 
   By virtue of the foregoing arrangement, terminals on each surface of device  900  provide three different capacitances. The capacitances may be similar to the three capacitances present at the terminals of device  800 . Accordingly, the impedance profile of device  900  shown in  FIG. 8C  is similar to the impedance profile of  FIG. 7C . 
     FIG. 9A  is a representation of terminals extending from a surface of device  1000  according to some embodiments. Device  1000  may provide a plurality of capacitances. In particular, a first capacitance may appear between terminals  1001  and  1002 , while a second capacitance may appear between any one of terminals  1004 ,  1006 , and  1007  and any one of terminals  1003 ,  1005 , and  1008 . 
     FIG. 9B  illustrates conductive planes of device  1000  according to some embodiments. Conductive plane  1010  includes portion  1011  and portion  1013 , which are discontinuous from one another. Conductive plane  1010  may be associated with a first polarity. In this regard, conductive plane  1010  defines interfaces  1012 ,  1014 ,  1016 , and  1018  for coupling conductive plane  1010  to terminals  1001 ,  1003 ,  1005 , and  1008 , which are also associated with the first polarity. 
   Conductive plane  1020  includes discontinuous portions  1021  and  1023 . Conductive plane  1020  may be associated with a second polarity and may include interfaces  1022 ,  1024 ,  1026 , and  1028  for coupling conductive plane  1020  to terminals that are also associated with the second polarity. Such terminals according to the illustrated embodiments are terminals  1002 ,  1004 ,  1006 , and  1007 . 
   Device  1000  may be constructed by placing alternating layers of conductive plane  1010  and conductive plane  1020  on top of one another. The layers may be separated by a dielectric. In some embodiments, a dielectric is disposed between portion  1011  and portion  1021  and the same or a separate dielectric is disposed between portion  1013  and portion  1023 . 
     FIG. 9C  shows an impedance profile of device  1000  according to some embodiments. The impedance profile is flatter than an impedance profile of existing systems because of the additional impedance droop provided by the additional capacitor of device  1000 . 
     FIG. 10A  illustrates device  1100  according to some embodiments. Device  1100  provides three capacitances. As shown in  FIG. 10B , conductive planes  1110  and  1120  of device  1100  appear similar to conductive planes  1010  and  1020  of device  1000 , but conductive planes  1110  and  1120  are split into three discontinuous portions. Each of planes  1110  and  1120  is associated with a different polarity, and each portion of a plane includes interfaces for coupling terminals that are associated with the polarity of the plane. Device  1100  may be constructed similarly to device  1000 . Device  1100  may provide an impedance profile that is flatter than the impedance profile of device  1000  due to an additional impedance droop provided by the additional capacitor of device  1100 . 
     FIGS. 11A through 12B  each illustrate a different device providing multiple capacitances. Each device comprises a first conductive plane including three discontinuous portions, a second conductive plane including three discontinuous portions, and a dielectric disposed between at least one portion of the first conductive plane and at least one portion of the second conductive plane. Each conductive plane also defines interfaces for coupling terminals that are associated with a polarity of the conductive plane. 
     FIGS. 13 through 15  also illustrate devices providing multiple capacitances. The devices include more than eight terminals. However, each device includes at least a first conductive plane including at least two discontinuous portions, a second conductive plane including at least two discontinuous portions, and a dielectric disposed between at least one portion of the first conductive plane and at least one portion of the second conductive plane. Moreover, each conductive plane defines interfaces to which terminals that are associated with a polarity of the conductive plane may be coupled. 
   Each of the embodiments described above and illustrated herein may provide a more uniform impedance profile than a conventional device. The existence of fewer terminals per individual capacitance also may increase the equivalent series resistance of the total capacitance. These factors may reduce resonance between a motherboard and a package on which a device according to some embodiments is mounted. 
   The several embodiments described herein are solely for the purpose of illustration. Embodiments may include any currently or hereafter-known versions of the elements described herein. Therefore, persons skilled in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.