Patent Publication Number: US-10313471-B2

Title: Persistent-memory management

Description:
REFERENCE TO RELATED APPLICATION 
     This application is a continuation of and claims priority to U.S. patent application Ser. No. 15/298,119, filed on Oct. 19, 2016 and titled “Persistent-Memory Management,” the entirety of which is hereby incorporated by reference herein. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates generally to storage access and control. More specifically, but not by way of limitation, this disclosure relates to managing persistent-memory devices. 
     BACKGROUND 
     A computing device can have various types of memory devices. Examples of the memory devices can include registers and caches within a central processing unit of the computing device. The registers and caches can have relatively low latency due to the position of the registers and caches within the central processing unit. But the registers and caches can have a relatively small amount of storage space. And registers and caches can be volatile (i.e., the registers and caches can lose their data when powered off). 
     Another example of a type of memory device includes random access memory (RAM) that is physically positioned outside of, but close to, the central processing unit. RAM can have a larger amount of storage space than registers and caches, but RAM can also have higher latency than the registers and caches due to the distance between the RAM and the central processing unit. RAM can also be volatile. 
     Another example of a type of memory device includes a hard drive that is physically positioned farther from the central processing unit than the RAM. The hard drive can have a larger amount of storage space than RAM, but the hard drive can also have higher latency than the RAM due to the distance between the hard drive and the CPU. The hard drive may be particularly useful for storing large amounts of data for long periods of time, because the hard drive can be non-volatile (i.e., the hard drive can retain data even when powered off), unlike the registers, caches, and RAM. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of an example of a system for managing persistent-memory devices according to some aspects. 
         FIG. 2  is a block diagram of an example of a computing device according to some aspects, 
         FIG. 3  is a flow chart showing an example of a process for managing persistent-memory devices according to some aspects. 
         FIG. 4  is a flow chart showing an example of a process for performing a write operation according to some aspects. 
         FIG. 5  is a flow chart showing an example of a process for recreating a file according to some aspects. 
     
    
    
     DETAILED DESCRIPTION 
     There can be disadvantages to using hard drives to store data in certain situations. For example, hard drives can have a high amount of latency as compared to other types of memory devices, such as registers, caches, and random access memory (RAM). Further, hard drives can fail or become damaged more easily than other types of memory devices. And if a hard drives fails or becomes damaged, the data stored on the hard drive can be corrupted or irretrievably lost. 
     Some examples of the present disclosure overcome one or more of the abovementioned issues by (i) storing data in a persistent-memory device, rather than a hard drive, of a computing device and (ii) storing a copy of the data in another persistent-memory device of another, remotely located computing device. In some examples, by storing the data in the persistent-memory device, the latency and performance issues associated with hard drives can be reduced or eliminated. And by storing a copy of the data in the other persistent-memory device of the remotely located computing device, a backup of the data is available should one of the computing devices fail. 
     Persistent-memory devices can be loosely categorized as falling between RAM and hard drives on a spectrum of storage capacity and performance. For example, persistent-memory devices can have more storage space than RAM. But persistent-memory devices can also have higher latency than RAM and worse performance (e.g., can access data more slowly) than RAM (but as technology progresses, persistent-memory devices are more readily approaching the low latency and faster performance of RAM). Conversely, persistent-memory devices can have less storage space than hard drives. But persistent-memory devices can have lower latency (e.g., by orders of magnitude) and better performance than hard drives. The lower latency and better performance can make persistent-memory devices more suitable than hard drives for storing data. 
     Some examples of the present disclosure can be implemented as a highly available system. A highly available system can include multiple computing devices that (i) share data to provide redundancy or quick access to the data, (ii) detect failures (e.g., a computing device shutting down or having an error), (iii) correct the failures, or any combination of these. In one example, the highly available system can include a first computing device that stores data in a local persistent-memory device and a copy of the data in another persistent-memory device of a second computing device. If the second computing device needs the data (e.g., to perform one or more operations), the second computing device has quick and immediate access to the copy of the data, without having to request the data from the first computing device. Also, if the first computing device has an error or otherwise fails, the second computing device can still access the copy of the data. And, after the error or failure is corrected, the first computing device can obtain the data from the second computing device and use the data as needed (e.g., to restore the first computing device to a previous state). 
     In some examples, the first computing device can synchronously store the data in the local persistent-memory device and the copy of the data in the other persistent-memory device. For example, the first computing device can use a central processing unit to perform a first write operation to store the data in the local persistent-memory device. The first computing device can substantially simultaneously (e.g., at the same time or within a short duration of time, such within two microseconds of one another) use a memory controller to perform a second write operation that causes the copy of the data to be stored in the other persistent-memory device. The memory controller can have remote direct memory access (RDMA) capabilities for causing the copy of the data to be stored in the other persistent-memory device, Performing the first write operation and the second write operation substantially simultaneously can enable an operating system or application executing on the central processing unit, which may be waiting for the write operations to be completed, to experience a low amount of latency, In some examples, performing the second write operation using RDMA, which can have lower latency than other types of memory protocols, can also reduce the amount of latency experienced by the operating system or application. 
     Some or examples of the present disclosure can be implemented at least in part by a storage stack of a computing device (e.g., a Linux-based computing device). A stack can be a software-based component or buffer used for storing requests that are to be handled. A storage stack can be a stack for storing data-storage requests and data-retrieval requests. In some examples, the storage stack of the first computing device, the second computing device, or both can be modified to implement some or all of the examples described herein. For example, the storage stack of the first computing device can be modified to cause the first computing device to automatically perform the second write operation each time the first computing device performs the first write operation. 
     In some examples, the first write operation, the second write operation, or both of these can be substantially “hidden” from (e.g., performed substantially independently of) the central processing unit, an operating system executing on the central processing unit, an application (e.g., a higher-level application) running within the operating system, or any combination of these. Performing memory operations in a manner that is hidden from or substantially independent of the central processing unit, the operating system, or an application running within the operating system can be referred to as transparency. 
     In some examples, some or all of the abovementioned features can be combined to form a storage system that is persistent memory-based, highly available, synchronous, and transparent, 
     These illustrative examples are given to introduce the reader to the general subject matter discussed here and are not intended to limit the scope of the disclosed concepts. The following sections describe various additional features and examples with reference to the drawings in which like numerals indicate like elements but, like the illustrative examples, should not be used to limit the present disclosure. 
       FIG. 1  is a block diagram of an example of a system  100  for managing persistent-memory devices  106   a - c  according to some aspects. The persistent-memory devices  106   a - c  can be included in respective computing devices  102   a - c  that form the system  100 . 
     The computing devices  102   a - c  can be in communication with one another via a network  114 , such a local access network (LAN). The network  114  can include one or more subnetworks, a wide area network (WAN), the Internet, or any combination of these. The computing devices  102   a - c  can and communicate with one another via one or more wired or wireless network-interface components, such as a serial interface, an IEEE 802.11 interface, an infiniband interface, or any combination of these. 
     Each of the computing devices  102   a - c  can include a central processing unit, such as central processing unit  104   a,  and a persistent-memory device, such as persistent-memory device  106   a.  Each persistent-memory device can be communicatively coupled to a respective central processing unit. The persistent-memory device is non-volatile. The persistent-memory device can be byte-addressable or block-addressable. A byte-addressable memory device can be a memory device in which each memory address refers to a single block of eight bits, which can be referred to as a byte. A block-addressable memory device can be a memory device in which data is read and written in a fixed chunk-size (e.g., a chunk-size of 4096 bytes). 
     The central processing unit can perform operations (e.g., memory operations). Examples of the operations can include a write operation for writing data to a memory device, such as persistent-memory device  106   a  or another memory device; a read operation for reading data from a memory device; or both of these. 
     Each of the computing devices  102   a - c  can include a memory controller, such as memory controller  108   a,  communicatively coupled to a respective persistent-memory device, such as persistent-memory device  106   a,  The memory controller can perform operations for controlling the persistent-memory device. Examples of the operations can include a read operation for reading data from the persistent-memory device, another read operation for reading data from a remote persistent-memory device, a write operation for storing data on the persistent-memory device, another write operation for storing data on the remote persistent-memory device, or any combination of these. 
     The memory controllers  108   a - c  can have RDMA capabilities (e.g., can implement an RDMA protocol, such as RFC 5040) for exchanging data between the persistent-memory devices  106   a - c  of the computing devices  102   a - c.  The RDMA capabilities can enable the computing devices  102   a - c  to read data and store data in each other&#39;s persistent-memory devices  106   a - c,  without involving the central processing units  104   a - c,  operating systems or applications executing on the central processing units  104   a - c,  or any combination of these. To implement RDMA, the memory controllers  108   a - c  can each include a transport layer that employs a transport protocol. The transport protocol can enable the memory controllers  108   a - c  to communicate with one another, via the network  114 , independently of the central processing units  104   a - c.  In other examples, the memory controllers  108   a - c  can implement additional or alternative protocols (e.g., an internet protocol) for communicating with one another directly (e.g., independently of the central processing units  104   a - c ), 
     As a particular example, the central processing unit  104   a  of computing device  102   a  can execute a first write operation to store data in persistent-memory device  106   a,  which can be a local persistent-memory device with respect to the computing device  102   a.  The data can be a file  110 , a command, an instruction, or any combination of these. The memory controller  108   a  can additionally or alternatively execute a second write operation to store a copy of the data (e.g., the copy of the file  112   a ) in persistent-memory device  106   b  of computing device  102   b.  For example, the memory controller  108   a  can perform a RDMA write operation to store the copy of the data in the persistent-memory device  106   b.  The memory controller  108   a  can additionally or alternatively execute a third write operation to store another copy of the data (e.g., the copy of the file  112   b ) in persistent-memory device  106   c  of computing device  102   c.  The memory controller  108   a  can perform the second write operation and the third write operation synchronously or sequentially (e.g., one write operation can immediately follow the other). The computing device  102   a  can cause any number of copies of the data to be stored in any number and combination of remote computing devices  102   b - c.    
     In some examples, the computing devices  102   a - c  can implement an erasure coding (e.g., via an erasure coding protocol, such as RAID-5 or RAID-6) to distribute, store, and/or recover data. Erasure coding can include dividing data into fragments. The fragments can be encoded, expanded (e.g., to include redundant segments of the data), or both of these. The modified fragments (expanded and/or encoded fragments) can then be stored among multiple memory devices, such as memory devices on local computing devices, remote computing devices, or any combination of these. As a particular example, the computing device  102   a  can cause data to be fragmented, encoded, and distributed among the other computing devices  102   b - c  according to an erasure-coding scheme. Erasure coding can result in the total amount of data that is saved across on the computing devices  102   b - c  being smaller than using other methods, thereby saving computing resources. 
     In some examples, the computing devices  102   a - c  can allocate portions of their respective persistent-memory devices  106   a - c  for storing local data and remote data. For example, the memory controller  108   a  can allocate a first segment of the persistent-memory device  106   a  for storing local data, a second segment of the persistent-memory device  106   a  for storing data from computing device  102   b,  and a third segment of the persistent-memory device  106   a  for storing data from computing device  102   c.  The first segment, second segment, and third segment of the persistent-memory device  106   a  can be the same size or different sizes. The computing devices  102   a - c  can allocate any number and combination of segments, of any sizes, for storing local data, remote data, or both. The number, combination, and sizes of the segments can be customized or configured by a user and may be fixed or variable. 
     In some examples, the memory controller  108   a  can receive a request to store data from the memory controller  108   c.  The memory controller  108   a  can determine which segment of the persistent-memory device  106   a  is associated with the memory controller  108   c.  For example, the memory controller  108   a  can determine which segment is associated with the computing device  102   c  that includes the memory controller  108   c  by consulting a lookup table or database that correlates the computing devices  102   b - c  with segments of the persistent-memory device  106   a.  The computing device  102   a  can then store the data in the segment of the persistent-memory device  106   a  that is associated with the memory controller  108   c.    
     Although the memory controllers  108   a - c  are shown in FIG,  1  as independent components within their respective computing devices  102   a - c,  in other examples, the memory controllers  108   a - c  can be (or can be included in) network-interface components or other hardware of the computing devices  102   a - c.  One example of a network-interface component is a network interface controller (NIC), The memory controller  108   a  can be included in the network interface controller. The network interface controller may be able to separately establish both (i) communications between the central processing units  104   a - b  of computing devices  102   a - b,  and (ii) communications between the memory controllers  108   a - b  of the computing device  102   a - b.  This can enable the memory controllers  108   a - b  to transmit commands to one another and receive commands from one another, independent of the central processing units  104   a - b.    
     In some examples, the computing devices  102   a - c  may execute an application for controlling the persistent-memory device  106   a.  For example, the central processing unit  104  can execute the application. The application can be independent of an operating system and a higher-level application executing within the environment of the operating system. In such an example, the operating system and the higher-level application may not be aware of the memory operations being performed, providing a level of transparency. 
     The system  100  can be a highly available system. For example, the computing devices  102   a - c  can poll one another or otherwise communicate with one another to determine if a computing device  102   a  or an application running on a computing device  102   a  has failed. If so, the remaining computing devices  102   b - c  can reroute data or traffic; run a correction process to restart the computing device  102   a,  the application, or otherwise correct the failure; or any combination of these. This can ensure that the computing devices and applications executing thereon are highly available to users. As another example, the computing devices  102   b - c  may rely on the file data in the file  110  to perform operations. By storing the copies of the file  112   a - b  on the computing devices  102   b - c,  the computing devices  102   b - c  can quickly and easily access the file data, without having to request the file  110  from the computing device  102   a  and wait for the computing device  102   a  to provide the file  110 . This can ensure that the file data is highly available for use by the computing devices  102   b - c.    
     The system  100  shown in  FIG. 1  is for illustrative purposes. Other systems can include any number and combination of computing devices having any number and combination of the features discussed above. Also, the examples described above are for illustrative purposes. Any number and combination of the central processing units  104   a - c  and memory controllers  108   a - c  can perform any number and combination of the write operations and other functions discussed above. Further, some examples of the present disclosure can be implemented using other types of memory devices, such as battery-backed dynamic random access memory (DRAM), an example of which may be non-volatile dual in-line memory module (NVDIMM)); magnetoresistive random-access memory (MRAM); or other persistent memory technologies. 
       FIG. 2  is a block diagram of an example of a computing device  102  according to some aspects. The computing device  102  can include a central processing unit  104 , a persistent-memory device  106 , a memory controller  108 , or any combination of these. In some examples, some or all of the components shown in  FIG. 2  can be integrated into a single structure, such as a single housing. In other examples, some or all of the components shown in  FIG. 2  can be distributed (e.g., in separate housings) and in electrical communication with each other. 
     The central processing unit  104  can include one or more processing devices  202   a.  Non-limiting examples of a processing device  202   a  can include a Field-Programmable Gate Array (FPGA), an application-specific integrated circuit (ASIC), a microprocessor, etc. 
     The central processing unit  104  can include a memory device, such as memory device  204   a,  or can be communicatively coupled to a memory device, such as memory device  204   c,  via a bus. The processing device  202   a  can execute instructions stored in the memory device to perform operations. The memory device can be volatile or non-volatile. Non-limiting examples of the memory device can include electrically erasable and programmable read-only memory (EEPROM), flash memory, a persistent-memory device, or any other type of non-volatile memory. In some examples, at least some of the memory device can include a medium (e.g., a computer-readable medium) from which the central processing unit can read instructions. The medium can include electronic, optical, magnetic, or other storage devices capable of providing the processing device  202   a  with computer-readable instructions or other program code. Non-limiting examples of the medium include (but are not limited to) magnetic disk(s), memory chip(s), read-only memory (ROM), random-access memory (RAM), an ASIC, a configured processor, optical storage, or any other medium from which the processing device  202   a  can read instructions. The instructions can include processor-specific instructions generated by a compiler or an interpreter from code written in any suitable computer-programming language, including, for example, C, C++, etc. 
     The memory controller  108  can include hardware components, software components, or both of these. For example, the memory controller  108  can include a processing device  202   b.  The processing device  202   b  can have any of the features discussed above with respect to processing device  202   a,  The memory controller  108  can additionally or alternatively include a memory device  204   b.  The memory device  204   b  can be communicatively coupled to a processing device (e.g., processing device  202   b  or processing device  202   a ) via a bus. The memory device  204   b  can have any of the features discussed above with respect to the memory devices  204   a,    204   c,  The memory device  204   b  can include instructions that are executable by the processing device (e.g., processing device  202   b  or the processing device  202   a ) for causing the processing device to perform operations. The memory controller  108  can additionally or alternatively include other circuitry, such as a resistor, integrated circuit, capacitor, multiplexer, demultiplexer, analog-to-digital converter, digital-to-analog converter, inductor, or any combination of these. Although the memory controller  108  is depicted as being separate from the central processing unit  104 , in other examples the memory controller  108  can be integrated with the central processing unit  104 . For example, the memory controller  108  can include a program-code module stored in the memory device  204   a  of the central processing unit  104 . 
     In some examples, the computing device  102  can include a database  206 . In some examples, the database  206  can include information that maps computing devices to particular segments of the persistent-memory device  106 . Although the database  206  is depicted as being within memory device  204   b,  in other examples the database  206  can be included in memory device  204   a  or memory device  204   c.    
     In some examples, the persistent-memory device  106  can include multiple segments, such as segments  208   a - c,  of the same size or different sizes. The computing device  102  can store data (e.g., as discussed above with respect to  FIG. 1 ) from remote computing devices in the segments. 
     In some examples, the segments of a persistent memory device can have one or more associated settings. Examples of the settings can include a compression setting (e.g., indicating if data is to be compressed before it is stored in the segment); an encryption setting or encoding setting (e.g., indicating if data is to be encrypted or encoded before it is stored in the segment); an availability setting (e.g., indicating if the segment is available for storing data from a remote computing device or the local computing device); an erasure coding setting (e.g., indicating if an erasure coding scheme is to be applied to data before the data is stored in the segment); or any combination of these. In some examples, the settings can be user customizable. The computing device  102  can store data in a segment of a persistent memory device according to one or more of the settings associated with the segment. 
     For example, the central processing unit  104  can determine (e.g., by accessing a database stored in memory, such as memory device  204   a  or memory device  204   c ) if an encryption setting associated with segment  208   a  is turned on or turned off. If the encryption setting is turned on, the computing device  102  can cause data to be encrypted before the data is stored in the segment  208   a,  If the encryption setting is turned off, the computing device  102  can cause data to be stored in the segment in the data&#39;s original (e.g., unencrypted) format. 
     As another example, the memory controller  108  can determine (e.g., by accessing database  206 ) if a segment of a remote persistent-memory device of a remote computing device has a particular setting or combination of settings. The memory controller  108  can cause data to be stored in the remote persistent-memory device in accordance with the setting(s). For example, the memory controller  108  can determine if an encryption setting for a particular segment of a remote persistent-memory device is turned on or turned off. If the compression setting is turned on, the memory controller  108  can cause data to be compressed before the data is stored in the segment of the remote, persistent memory device. If the compression setting is turned off, the memory controller  108  can cause data to be stored in the segment of the remote, persistent memory device in the data&#39;s original (e.g., uncompressed) format. 
     In some examples, the computing device  102  can include a network-interface component  210 . An example of the network interface component  210  can include a network interface controller (NIC). The network interface component  210  can be for establishing or facilitating a network connection. In some examples, the network interface component  210  can include a wired interface (e.g., Ethernet, USB, IEEE 1394), a wireless interface (e.g., IEEE 802.11, Bluetooth, or a radio interface for accessing a cellular telephone network), or any combination of these. Although the network interface component  210  is depicted in  FIG. 1  as being separate from the memory controller  108 , in other examples the network interface component  210  can include the memory controller  108 . In some examples, the network interface component  210  can perform one or more functions discussed with respect to the memory controller  108 . For example, the network interface component  210  can perform an RDMA read operation, an RDMA write operation, or both of these. 
     The computing device  102  shown in  FIG. 2  is for illustrative purposes. Other examples can include any number and combination of the components shown in  FIG. 2 , and the components can have any number and combination of the features discussed above. 
     The computing devices  102  can implement the process shown in  FIG. 3  for managing persistent-memory devices. Some examples can include more, fewer, or different steps than the steps depicted in  FIG. 3 . The steps below are described with reference to components described above with regard to  FIGS. 1-2 . 
     Turning to  FIG. 3 , in block  302 , the central processing unit  104   a  of the computing device  102   a  performs a first write operation. The first write operation can cause the file  110  to be stored in the persistent-memory device  106   a  of the computing device  102   a.  The file  110  can include a set of bytes. 
     In some examples, the first write operation can cause the file  110  to be directly stored in the persistent-memory device  106  of the computing device  102   a.  Directly storing the file  110  in the persistent-memory device  106   a  can include storing the file  110  in the persistent-memory device  106   a  without first storing the file  110  in another memory device, such as a buffer (e.g., a hardware buffer) or an intermediary memory device between the memory controller  108   a  and the persistent-memory device  106   a.    
     In other examples, the first write operation can cause the file  110  to be indirectly stored in the persistent-memory device  106   a  of the computing device  102   a.  For example, the central processing unit  104   a  can store the file  110  in an intermediary memory device before ultimately storing the file  110  in the persistent-memory device  106   a.    
     In block  304 , the memory controller  108   a  of the computing device  102   a  performs a second write operation independently of (e.g., separately from) the central processing unit  104   a.  The memory controller  108   a  can perform the second write operation based on (or in response to) a command from the central processing unit  104   a.  The second write operation can include instructing another memory controller  108   b  of another computing device  102   b  to store a copy of the file  112   a  in another persistent-memory device  106   b  of the other computing device  102   b.    
     For example, the second write operation can include transmitting an instruction (e.g., command) to the other memory controller  108   b  to cause the other memory controller  108   b  to directly store the copy of the file  112   a  in the persistent-memory device  106   b.  An example of the instruction can be an RDMA write instruction. The other memory controller  108   b  can receive the instruction and, in response to the instruction, directly store the copy of the file  112   a  in the persistent-memory device  106   b.  Directly storing the copy of the file  112   a  in the persistent-memory device  106   b  can include storing the copy of the file  112   a  in the persistent-memory device  106   b  without first storing the copy of the file  112   a  in another memory device, such as a buffer or an intermediary memory device. 
     In some examples, the second write operation can include instructing the other memory controller  108   b  of the other computing device  102   b  to indirectly store a copy of the file  112   a  in another persistent-memory device  106   b  of the other computing device  102   b.  This may cause the memory controller  108   b  to store the copy of the file  112   a  in an intermediary memory device before ultimately storing the copy of the file  112   a  in the persistent-memory device  106   b.    
     In some examples, the central processing unit  104   a  can determine that the first write operation has been performed or is to be performed. Based on determining that the first write operation has been performed or is to be performed, the central processing unit  104   a  can automatically cause the memory controller  108   a  to perform the second write operation. For example, the central processing unit  104   a  can automatically transmit a command to the memory controller  108   a  to cause the memory controller  108   a  to perform the second write operation (e.g., substantially simultaneously to the first write operation being performed by the central processing unit  104   a ). In one example, any time the central processing unit  104   a  determines that the first write operation has been performed or is to be performed, the central processing unit  104   a  can cause the memory controller  108   a  to also automatically perform the second write operation. This can enable data to easily be mirrored or shared between the computing devices  102   a - b,  with minimal user involvement. 
     In some examples, the memory controller  108   a  can perform the second write operation according to one or more of the steps shown in  FIG. 4 . And some examples can include more, fewer, or different steps than the steps depicted in  FIG. 4 . 
     In block  402 , the memory controller  108   a  stores a first portion of the copy of the file  112   a  in a first persistent-memory device of a first computing device. For example, the memory controller  108   a  can split the copy of the file  112   a  into a first segment and a second segment, and cause the first segment to be stored on the persistent-memory device  106   b  of computing device  102   b.  The memory controller  108   a  can cause the first segment to be stored on the persistent-memory device  106   b  by transmitting an instruction to the memory controller  108   b  to cause the memory controller  108   b  to store the first segment in the persistent-memory device  106   b.    
     In block  404 , the memory controller  108   a  stores a second portion of the copy of the file  112   a  in a second persistent-memory device of a second computing device. For example, the memory controller  108   a  can cause the second segment to be stored on the persistent-memory device  106   c  by transmitting an instruction to the memory controller  108   c  to cause the memory controller  108   c  to store the second segment in the persistent-memory device  106   c.    
     In some examples, the first portion of the copy of the file  112   a  and the second portion of the copy of the file  112   a  can collectively form the entire copy of the file  112   a,  In other examples, the copy of the file  112   a  can be divided into more than two segments, with each segment having the same size or different sizes. The copy of the file  112   a  can be split into any number and combination of segments that are stored on any number and combination of computing devices. 
     In block  406 , the memory controller  108   a  updates a database, such as database  206 , to indicate that the first portion of the copy of the file is stored on the first computing device and the second portion of the copy of the file is stored on the second computing device. For example, the memory controller  108   a  can include a new entry in the database or modify an existing entry in the to indicate that the first portion of the copy of the file  112   a  is stored on the computing device  102   b  and the second portion of the copy of the file  112   b  is stored on the computing device  102   c.    
     In some examples, some or all of the computing devices  102   a - c  can maintain a database, such as database  206 , indicating where some or all of the portions of the copies of files are stored. If a computing device  102   a  wants to recreate a file (e.g., because the file has been lost or damaged), the computing device  102   a  can access the database and obtain the respective portions of the copy of the file from the respective computing devices  102   b - c.  The computing device  102   a  can then combine the portions together to recreate the file. An example of such a process is described with respect to  FIG. 5 . 
     In block  502 , the memory controller  108   a  determines that a first portion of the copy of the file  112   a  is stored on a first computing device  102   b  and a second portion of the copy of the file  112   b  is stored on a second computing device  102   c.  For example, the memory controller  108   a  can access a database  206  to map the first portion to the first computing device  102   b  and the second portion to the second computing device  102   c.    
     In block  504 , the memory controller  108   a  retrieves the first portion of the copy of the file  112   a  from the first computing device  102   b  and the second portion of the copy of the file  112   b  from the second computing device  102   c.  For example, the memory controller  108   a  can transmit a first command to the memory controller  108   b  to cause the memory controller  108   b  to obtain the data for the first portion of the copy of the file  112   a  and communicate (e.g., via the network  114 ) the data back to the memory controller  108   a.  The memory controller  108   a  can also transmit a second command to the memory controller  108   c  to cause the memory controller  108   c  to obtain the data for the second portion of the copy of the file  112   b  and communicate the data back to the memory controller  108   a.    
     In block  506 , the memory controller  108   a  recreates the file by combining the first portion of the copy of the file  112   a  and the second portion of the copy of the file  112   b.  For example, the memory controller  108   a  can prepend or append the first portion of the copy of the file  112   a  to the second portion of the copy of the file  112   b.  Alternatively, the memory controller  108   a  can communicate the first portion of the copy of the file  112   a  and the second portion of the copy of the file  112   b  to the central processing unit  104   a,  which can recreate the file by integrating together the first portion of the copy of the file  112   a  and the second portion of the copy of the file  112   b.    
     In some examples, the memory controller  108   a  can perform some or all of the steps of  FIG. 5  in response to an event. The event can include a user input, a software request, a request from another computing device  102   b - c,  a shutdown of the computing device  102   a,  a restart of the computing device  102   a,  a software failure (e.g., program failure, operating system failure, or firmware failure), a hardware failure, or any combination of these. 
     Although the description of  FIGS. 3-5  is provided with reference to the memory controller  108   a  performing the steps, in other examples the central processing unit  104   a  or other hardware can additionally or alternatively perform some or all of the steps. For example, a memory-management application that is executing on the central processing unit  104   a  can perform the first write operation, the second write operation, or both of these. The memory-management application can be independent of an operating system executing on the central processing unit  104   a.  Alternatively, the memory-management application can run within the operating system as a background process or driver. This can enable the memory-management application to be substantially hidden from the user, or otherwise minimally interfere with the user&#39;s operation of the operating system. 
     Also, although the description of  FIGS. 3-5  is described with reference to a file  110  for simplicity, other examples can be implemented using any type, combination, and amount of data (e.g., one or more bytes of data). 
     The foregoing description of certain examples, including illustrated examples, has been presented only for the purpose of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Numerous modifications, adaptations, and uses thereof will be apparent to those skilled in the art without departing from the scope of the disclosure.