Patent Publication Number: US-2003222701-A1

Title: Level shifter having plurality of outputs

Description:
RELATED APPLICATION  
     [0001] This application is a continuation-in-part of U.S. patent application Ser. No. 10/062,872 filed Jan. 31, 2002, now abandoned. 
    
    
     
       BACKGROUND OF THE INVENTION  
       [0002] 1. Field of the Invention  
       [0003] The present invention relates to a level shifter, and more particularly, to a level shifter for generating a plurality of output voltages having a plurality of levels.  
       [0004] 2. Description of the Related Art  
       [0005] Referring to FIG. 1, in general, a level shifter is used to interface a circuit driven by a low voltage V DDL  with a circuit driven by a high voltage V DDH  in a circuit including the low voltage V DDL  and the high voltage V DDH .  
       [0006] However, a conventional voltage level shifter outputs only one selected from either 0V or a power supply applied to the voltage level shifter according to an input signal. Thus, when a voltage having a plurality of levels is required, at least two or more voltage level shifters are required.  
       SUMMARY OF THE INVENTION  
       [0007] To solve the above problems, it is an object of the present invention to provide a level shifter for generating a plurality of output voltages having a plurality of levels.  
       [0008] Accordingly, to achieve the object, there is provided a level shifter. The level shifter includes a first level shifter for receiving an input signal and a first power supply through load transistor and outputting a first output voltage having a level the same as that of a ground voltage or the second power supply according to the input signal, a first control signal having a value in which the first output voltage is inverted, and a second control signal having the same value as that of the first output voltage, and an output voltage generator for receiving the first power supply and a second power supply having a level different from that of the first power supply and outputting a second output voltage having a level equivalent to either the first power supply or the second power supply according to the first and second control signals.  
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0009] The above objects and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:  
     [0010]FIG. 1 is a block diagram illustrating that a circuit for operating at a logic level is interfaced with a circuit for operating at a high voltage level by a level shifter;  
     [0011]FIG. 2 is a block diagram of a level shifter according to the present invention;  
     [0012]FIG. 3 is a detailed circuit diagram of FIG. 2;  
     [0013]FIG. 4 illustrates a waveform of an input signal and an output signal of the level shifter according to the present invention; and  
     [0014]FIG. 5 illustrates results of simulation of the operation of the level shifter according to the present invention.  
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
     [0015] Hereinafter, the present invention will be described in detail by describing preferred embodiments of the invention with reference to the accompanying drawings.  
     [0016]FIG. 2 is a block diagram of a level shifter according to the present invention, and FIG. 3 is a detailed circuit diagram of FIG. 2. In the embodiment, two input power supplies, that is, first and second power supplies V DDH  and V DDL  are applied to the level shifter. The first power supply V DDH  (referred to as maximum voltage in FIG. 4) has a level higher than the second power supply V DDL , and the second power supply V DDL  (referred to as intermediate voltage) has a level between a ground voltage and the first input power supply. Referring to FIG. 2, a first level shifter  203  receives an input signal IN and the first power supply V DDH  through load transistor. The first power supply V DDH  has a voltage level required to be interfaced with a high voltage circuit to which the level shifter is connected. The first level shifter  203  outputs voltages according to the input signal IN, for example, the first level shifter  203  outputs the ground voltage (0V) when the input signal IN is logic low (0) and outputs a first output voltage OUT 1  having a voltage level the same as that of the second power supply V DDL  when the input signal IN is logic high (1) according to the input signal IN. The first level shifter  203  outputs first and second control signals for controlling an output voltage generator  201  for generating a second output voltage OUT 2 . The output voltage generator  201  receives the first and second power supplies V DDH  and V DDL  and generates the second output voltage OUT 2  according to the first and second control signals, which are output from the first level shifter  203 . The second output voltage OUT 2  has the same level as that of the first power supply V DDH  or the second power supply V DDL . Thus, the first output voltage OUT 1  and the second output voltage OUT 2  having different levels according to the logic level of the input signal IN are simultaneously generated. The load transistor  302  is used to provide a means to drop some of the voltage between the first power supply V DDH  and the first level shifter  203  and protect the first level shifter  203  from the first power supply V DDH .  
     [0017] The embodiment will be described in greater detail with reference to FIG. 3.  
     [0018] The output voltage generator  201  includes two PMOS transistors  301  and  303 . The first level shifter  203  includes two PMOS transistors, that is, first and second PMOS transistors  305  and  307 , two NMOS transistors, that is, first and second NMOS transistors  309  and  311 , and an inverter  313 . In a MOS transistor, a reverse bias should be applied to PN junction between a source and a substrate (or body) and PN junction between a drain and a substrate. In the embodiment, the same input power supply V DDH  is applied to sources of the first and second PMOS transistors  305  and  307  through Load Transistor, and the maximum value of the first output voltage OUT 1  is also V DDL , and thus, a body is connected to a source so that a reverse bias is applied to PN junction between a source and a body and to PN junction between a drain and a body. However, different input voltages are applied to sources of a third PMOS transistor  301  and a fourth PMOS transistor  303 , and the second output voltage OUT 2  is transited between the first power supply V DDH  and the second power supply V DDL , and thus, a body of a third and fourth PMOS transistors are connected to the first power supply V DDH  so that a reverse bias is applied to PN junction between a source and a body and to PN junction between a drain and a body. The load transistor  302  composed to thin or thick gate high voltage PMOSFET and gate is GND, drain is connected to the sources of the first and second PMOS transistors  305  and  307 , and drain is connected to the first power supply V DDH . The load transistor  302  is used to provide a means to drop some of the voltage between the first power supply V DDH  and the first level shifter  203  and to protect the first level shifter  203  from the first power supply V DDH .  
     [0019] All MOS transistors in the first level shifter  203  can be implemented with MOS transistor. The third  301  and fourth PMOS transistor  303  can be implemented with one of a thin gate high voltage MOS transistor or a thick gate high voltage MOS transistor. The thin or thick gate high voltage transistor is very different device structure from MOS transistor in general. Also, The thin or thick gate high voltage transistor has the breakdown voltage of a gate more than MOS transistor, resulting in applying a high voltage. The first control signal shown in FIG. 2 is a signal, which is commonly connected to a gate of the first PMOS transistor  305 , a drain of the first NMOS transistor  309 , and a gate of the second PMOS transistor  307 , and controls the operation of the third PMOS transistor  301  depending on each transistor, which is turned on/off according to the input signal IN. The second control signal shown in FIG. 2 can be constituted of an extra circuit but in the embodiment, is a signal, which is the same as the first output voltage OUT 1 , controls the operation of the fourth PMOS transistor  303 .  
     [0020] Hereinafter, the detailed operation will be described with reference to FIG. 3. First, the detailed operation of the first level shifter  203  will be described. The input signal IN having a logic signal level (here, the same level as that of the second power supply V DDL ) is connected to a gate of the first NMOS transistor  309 , and the input signal IN, which is inverted by the inverter  313 , is connected to a gate of the second NMOS transistor  311 . The drains of the first and second NMOS transistors  309  and  311  are grounded together. When the input signal IN is logic signal low, the first NMOS transistor  309  is turned off, and the second NMOS transistor  311  is turned on. As a result, the first PMOS transistor  305  is turned on, the second PMOS transistor  307  is turned off, and thus, the first output voltage OUT 1  becomes 0V. Simultaneously, the third PMOS transistor  301  is turned off, the fourth PMOS transistor  303  is turned on, and thus, the first input power supply V DDH  is output as the second output voltage OUT 2 .  
     [0021] Next, a case where the input signal IN is logic signal high will be described. When the input signal IN is logic signal high (here, the same level as that of the second power supply VDDL), the first NMOS transistor  309  is turned on, and the second NMOS transistor  311  id turned off. As a result, the first PMOS transistor  305  is turned off, the second PMOS transistor  307  is turned on, and thus, the first output voltage OUT 1  becomes the second power supply VDDL. Simultaneously, the third PMOS transistor  301  is turned on, the fourth PMOS transistor  303  is turned off, and thus, the second power supply VDDL is output as the second output voltage OUT 2 . Likewise, the level shifter simultaneously generates the first output voltage OUT 1  and the second output voltage OUT 2  having different levels.  
     [0022]FIG. 4 illustrates a waveform of an input signal and an output signal of the level shifter according to the present invention, and FIG. 5 illustrates results of simulation of the operation of the level shifter according to the present invention. When input  501  is logic low, the first output voltage OUT 1  ( 503 ) is 0V, and the first input power supply V DDH  ( 507 ) is output as the second output voltage OUT 2  ( 505 ). When the input  501  is logic high, the second input power supply V DDH  ( 507 ) is output as the first output voltage OUT 1  ( 503 ), and the second input power supply V DDL  ( 507 ) is output as the second output voltage OUT 2  ( 505 ). In the embodiment, the first input power supply V DDH  ( 507 ) is 10V, and the second input power supply V DDL  ( 507 ) is 5V. The embodiment is limited to the first through fifth PMOS transistors and the first and second NMOS transistors but each of the transistors can be implemented with a 3-terminal element having a different configuration by reconnecting each of terminals.  
     [0023] As described above, the level shifter for generating a plurality of output voltages having a plurality of levels according to the present invention can output voltages having levels different according to a power supply applied to one level shifter, and thus, interface a low voltage circuit with a high voltage circuit can be very easily made and various applications thereof are possible.  
     [0024] While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.