Patent Publication Number: US-2002003273-A1

Title: Igfet with silicide contact on ultra-thin gate

Description:
BACKGROUND OF THE INVENTION  
       [0001] 1. Field of the Invention  
       [0002] The present invention relates to integrated circuit manufacturing, and more particularly to forming insulated-gate field-effect transistors with silicide contacts.  
       [0003] 2. Description of Related Art  
       [0004] An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect tnansistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in order to modulate the longitudinal conductance of the channel.  
       [0005] In typical IGFET processing, the source and drain are formed by introducing dopants of a second conductivity type (P or N) into the semiconductor substrate of a first conductivity type N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate and the source and drain.  
       [0006] Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, the polysilicon is anisotropically etched to provide a gate which provides a mask during formation of the source and drain by ion implantation, and then the implanted dopant is activated using a high-temperature anneal that would otherwise melt the aluminum.  
       [0007] An important parameter in IGFETs is the threshold voltage (V T ), which is the minimum gate voltage required to induce the channel. For enhancement-mode devices, the positive gate voltage of an N-channel device must be larger than some threshold voltage before a conducting channel is induced, and the negative gate voltage of a P-channel device must be more negative than some threshold voltage to induce the required positive charge (mobile holes) in the channel.  
       [0008] Since it is very important to reduce the series resistance of the gate, source and drain for submicron devices, several techniques have been developed to improve contact resistance. One such approach is to use a refractory metal silicide to contact these regions. With this approach, a thin layer of refractory metal is deposited over the structure, and then heat is applied to form a silicide wherever the refractory metal is adjacent to silicon (including single crystal silicon and polysilicon). Thereafter, an etch is applied that removes unreacted refractory metal over spacers adjacent to opposing sidewalls of the gate to prevent bridging silicide contacts for the gate, source and drain. Various silicides, including PtSi, MoSi 2 , CoSi 2  and TiSi 2  have been used for this purpose. For instance, the sheet resistance of titanium silicide (TiSi 2 ) is as low as 3 to 6 Ω/sq, whereas heavily doped polysilicon exhibits a sheet resistance on the order of 15 to 30 Ω/sq. Another advantage to this approach is that the silicide contacts for the gate, source and drain are formed simultaneously and are self-aligned by the spacers. This self-aligned silicide is sometimes referred to as “salicide.”  
       [0009] After the silicide contacts are formed, typically an oxide layer is formed over the device, contact windows are etched in the oxide layer to expose the silicide contacts, a blanket layer of metallization is deposited over the oxide layer and into the contact windows to provide interconnect metailization, selected regions of the interconnect metallization are removed, and then a passivation layer is deposited over the substrate.  
       [0010] Although refractory metals and their silicides have adequately high melting points, they usually do not provide suitable replacements for polysilicon as the gate. For instance, the oxides of refractory metals are typically of poor quality, and in some cases volatile (Mo and W oxides). In addition, it may be difficult to obtain consistent threshold voltages due to impurities in the sources of the refractory metals. Polysilicon, on the other hand, has a known work function and forms a highly reliable interface with the underlying gate oxide.  
       [0011] In conventional processes, a polysilicon gate is often used as an implant mask during implantation of source/drain regions, so that essentially none of the dopants that impinge upon the polysilicon gate are implanted into the underlying channel region of the substrate. Otherwise, implanting a substantial amount of such dopants into the channel region may produce unwanted changes to the threshold voltage. The precise thickness needed for a given polysilicon gate will depend on various parameters, such as the implant energy, implant dosage, dopant species, acceptable range of threshold voltages, etc. However, polysilicon gates often have a thickness on the order of 2000 to 3000 angstroms. After the source and drain are formed, if titanium silicide contacts are desired, a typical thickness for a subsequently deposited titanium layer is on the order of 250 angstroms, and after applying a thermal cycle, the ensuing titanium silicide contacts have a thickness of about 600 to 650 angstroms. Although forming the titanium silicide contact on the polysilicon gate consumes several hundred angstroms of polysilicon, the final thickness of the polysilicon gate typically exceeds 1000 angstroms and is far greater than the thickness of the titanium silicide contact. Furthermore, even if a thicker titanium layer is applied, it becomes difficult to form titanium silicide contacts with a thickness that exceeds 1000 angstroms, which in turn limits the amount of polysilicon that will be consumed.  
       [0012] Accordingly, a need exists for a method of fabricating an IGFET that provides a low resistivity gate with the desired work function.  
       SUMMARY OF THE INVETION  
       [0013] A primary object of the invention is to provide an IGFET with an ultra-thin gate. This is accomplished using a silicide reaction that consumes a majority of the gate.  
       [0014] In accordance with one aspect of the invention, a method of making an IGFET includes forming a gate over a semiconductor substrate, forming a source and a drain in the substrate, depositing a contact material over the gate, and reacting the contact material with the gate to form a silicide contact on the gate and consume at least one-half of the gate.  
       [0015] By consuming such a large amount of the gate, a relatively thin gate can be converted into an ultra-thin gate with a thickness on the order of 100 to 200 angstroms. This provides for extremely low gate resistance.  
       [0016] In the preferred embodiment, the bottom surface of the gate is essentially undoped before reacting the contact material with the gate, and reacting the contact material with the gate pushes a peak concentration of a dopant in the gate towards the substrate so that a heavy concentration of the dopant is pushed to the bottom surface of the gate without being pushed into the substrate. In this manner, the snowplow effect is utilized by which an advancing silicide phase pushes the encountered dopant towards the substrate in order to heavily dope the gate down to the gate oxide interface. This avoids forming a depletion layer in the gate that might otherwise increase the effective thickness of the gate oxide and reduce drain current.  
       [0017] As exemplary materials, the contact material is a refractory metal such as titanium, the gate is polysilicon, and the dopant is arsenic.  
       [0018] A key advantage of the invention is that a highly miniaturized IGFET can be provided with an ultra-thin polysilicon gate having a well-controlled doping profile, thereby providing a low-resistance gate as well as the desired threshold voltage and drain current. 
     
    
    
     [0019] These and other objects, features and advantages of the invention will be further described and more readily apparent from a review of the detailed description of the preferred embodiments which follows.  
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0020] The following detailed description of the preferred embodiments can best be understood when read in conjunction with the following drawings, in which:  
     [0021] FIGS.  1 A- 1 J show cross-sectional views of successive process steps for forming an IGFET with a silicide contact on an ultra-thin gate in accordance with an embodiment of the invention.  
    
    
     DETAILED DESCRIPTION OF TIHE PREFERRED EMBODIMENTS  
     [0022] In the drawings, depicted elements are not necessarily drawn to scale and like or similar elements may be designated by the same reference numeral throughout the several views.  
     [0023] In FIG. 1A, silicon substrate  102  suitable for integrated circuit manufacture includes a P-type epitaxial surface layer disposed on a P+ base layer (not shown). The epitaxial surface layer provides an active region with a boron background concentration on the order of 1×10 16 atoms/cm 3 , a &lt;100&gt;orientation and a resistivity of 12 ohm-cm. Substrate  102  can be subjected to a threshold voltage implant, a punch-through implant, and a well implant as is conventional. For convenience of illustration, dielectric isolation such as field oxides between adjacent active regions is not shown. A blanket layer of gate oxide  104 , composed of silicon dioxide (SiO 2 ), is formed on the top surface of substrate  102  using tube growth at a temperature of 700 to 1000° C. in an O 2  containing ambient. Gate oxide  104  has a thickness in the range of 30 to 100 angstroms. Thereafter, a blanket layer of undoped polysiLicon  106  is deposited by low pressure chemical vapor deposition (LPCVD) on the top surface of gate oxide  104 . Polysilicon  106  has a thickness of 750 angstroms. If desired, polysilicon  106  can be doped in situ as deposition occurs, or doped before a subsequent etch step by implanting arsenic with a dosage in the range of 1×10 15  to 5×10 5  atoms/cm 2  and an energy in the range of 2 to 10 kiloelectron-volts. However, it is generally preferred that polysilicon  106  be initially doped after a subsequent etch step as described below.  
     [0024] In FIG. 1B, photoresist  108  is deposited on polysilicon  106  and patterned to selectively expose polysilicon  106 . Photoresist  108  is patterned using a photolithographic system, such as a step and repeat optical projection system, in which deep ultraviolet light from a mercury-vapor lamp is projected through a reticle and a focusing lens to obtain the desired image pattern. For illustration purposes, the minimum resolution of the photolithographic system is 3500 angstroms (0.35 microns). Thereafter, photoresist  108  is developed and the irradiated portions are removed, so that photoresist  108  has a length (or linewidth) of 3500 angstroms.  
     [0025] In FIG. 1C, a dry etch is applied that removes polysilicon  106  outside photoresist  108  while photoresist  108  protects the underlying portions of polysilicon  106 . The remaining (unetched) polysilicon  106  provides polysilicon gate  110 . The dry etch is highly selective of polysilicon and nonselective of silicon dioxide so that only a negligible amount of gate oxide  104  is removed and substrate  102  is unaffected. After etching occurs, gate  110  includes planar top surface  112 , planar bottom surface  114 , and opposing vertical sidewals  116 . Gate  110  has a thickness (or distance between surfaces  112  and  114 ) of 750 angstroms, and a length (or distance between sidewalls  116 ) of 3500 angstroms.  
     [0026] In FIG. 1D, photoresist  108  is stripped, and lightly doped source and drain regions are implanted into the substrate by subjecting the structure to ion implantation of arsenic, indicated by arrows  118 , at a dose in the range of 1×10 13  to 5×10 14  atoms/cm 2  and a relatively low implant energy of about 10 kiloelectron-volts, using gate  110  as an implant mask for the underlying region of substrate  102 . As a result, lightly doped source/drain regions  120  and  122  are implanted into substrate  102  outside gate  110  and are self-aligned to sidewalls  116  of gate  110 . Lightly doped source/drain regions  120  and  122  are doped N- with an arsenic concentration in the range of about 1×10 17  to 5×10 18  atoms/cm 3 . The arsenic is also implanted into gate  110 , although essentially all the arsenic that impinges upon gate  110  is implanted into gate  110  without reaching gate oxide  104  or substrate  102 .  
     [0027] Furthermore, the arsenic implanted into gate  110  has a peak concentration about  150  angstroms below top surface  112  (and about 600 angstroms above bottom surface  114 ) and a straggle above and below the peak concentration of about 100 angstroms. As such, essentially none of the arsenic is implanted into the lowest 200 angstroms of gate  110 , which remains essentially undoped.  
     [0028] In FIG. 1E, an oxide layer with a thickness of 1500 angstroms is conformally deposited over the exposed surfaces by plasma enhanced chemical vapor deposition at a temperature in the range of 300 to 450° C. Thereafter, the structure is subjected to an anisotropic reactive ion etch that forms oxide spacers  126  adjacent to sidewalls  116 . Spacers  126  cover portions of lightly doped source/drain regions  120  and  122 .  
     [0029] In FIG. 1F, heavily doped source and drain regions are implanted into the substrate by subjecting the structure to ion implantation of arsenic, indicated by arrows  128 , at a dose in the range of 1×10 15  to 5×10 15  atoms/cm 2  and a relatively low implant energy of about 10 kiloelectron-volts, using gate  110  and spacers  126  as an implant mask for the underlying region of substrate  102 . As a result, heavily doped source/drain regions  130  and  132  are implanted in substrate  102  and are self-aligned to the outside edges of spacers  126 . Heavily doped source/drain regions  130  and  132  are doped N+ with an arsenic concentration in the range of about 1×10 18  to 1×10 20  atoms/cm 3 . Furthermore, the peak concentration and straggle of the arsenic indicated by arrows  128  that is implanted into gate  110  are located at about the same positions as those of the arsenic indicated by arrows  118 .  
     [0030] In FIG. 1G, the device is annealed to remove crystalline damage and to drive-in and activate the implanted dopants by applying a rapid thermal anneal on the order of 950 to 1050° C. for 10 to 30 seconds. Source regions  120  and  130  form a source and drain regions  122  and  132  form a drain for an N-channel IGFET in substrate  102  that is controlled by gate  110 . Since the arsenic diffuses both vertically and laterally, lightly doped source/drain regions  120  and  122  extend slightly beneath the gate  110 , and heavily doped source/drain regions  130  and  132  extend slightly beneath spacers  126 . The arsenic, however, tends to diffuse much more slowly than other dopants such as phosphorus and boron. Therefore, the arsenic diffuses only slightly, and the lowest 200 angstroms of gate  110  remains essentially undoped after the drive-in step.  
     [0031] In FIG. 1H, a blanket layer of titanium  134  with a thickness of about 300 angstroms is sputter deposited over substrate  102 . Preferably, titanium  134  is deposited directly on gate  110  and heavily doped source and drain regions  130  and  132  without any intervening native oxide. The exposed silicon surfaces can be cleaned by putting substrate  102  into a sputtering system and ion etching or milling away a thin surface layer. Alternatively, a brief wet chemical etch can be used. Other techniques are feasible so long as native oxide or other surface contaminants that might otherwise adversely affect the subsequent formation of silicide contacts are avoided.  
     [0032] In FIG. 1I, a rapid thermal anneal on the order of 700° C. for 30 seconds is applied in a nitrogen ambient to react titanium  134  with the silicon surfaces that contact it. Silicon atoms in gate  110  and substrate  102  diffuse into and react with the adjacent regions of titanium  134 , and the reaction consumes or absorbs a substantial amount of the underlying silicon. The reaction converts titanium  134  into titanium silicide contacts  136 ,  138  and  140 , which are in ohmic contact with heavily doped source region  130 , heavily doped drain region  132 , and gate  110 , respectively. However, titanium  134  on spacers  126  remains unreacted. The ratio of titanium silicide to the original titanium is about 2.5 to 1, so titanium silicide contacts  136 ,  138  and  140  each have a thickness of about 750 angstroms. Although the theoretical ratio of titanium to consumed silicon is reported as about 2.3 to 1, Applicants find that in actual practice, this ratio is about 2 to 1. Therefore, titanium silicide contacts  136  and  138  each consume about 600 angstroms of substrate  102 , and titanium silicide contact  140  consumes about 600 angstroms of gate  110 . Advantageously, in doing so, the reaction drastically reduces the thickness of gate  110  from about 750 angstroms to about 150 angstroms, thereby converting gate  110  from a relatively thin gate into an ultra-thin gate.  
     [0033] Furthermore, the arsenic implanted into gate  110  is pushed towards substrate  102  in snowplow fashion. That is, the invention makes use of the so-called “snowplow” effect in which a dopant can be piled up in front of an interface during its growth motion. In particular, as titanium silicide contact  140  is formed, the interface between titanium silicide contact  140  and gate  110  advances beyond both the peak concentration and straggle of the arsenic implanted into gate  110 . The advancing interface collects and sweeps ahead of it in snowplow fashion most of the arsenic implanted into gate  110 . As a result, a narrow accumulation region of arsenic is formed just ahead of the advancing interface. It is contemplated that the accumulation region of arsenic has a higher arsenic concentration than the original peak concentration of the arsenic implanted into gate  110 . It is further contemplated that the accumulation region of arsenic provides heavy doping throughout the entire gate  110  after titanium silicide contact  140  is formed. Moreover, although the arsenic is pushed to the interface of gate  110  and gate oxide  104 , essentially none of the arsenic is pushed through gate oxide  104  into substrate  102 , thereby assuring that the IGFET remains an enhancement-mode device and providing a well-controlled threshold voltage while avoiding a depletion region at the bottom of gate  110  that might otherwise increase the effective thickness of gate oxide  104 .  
     [0034] Also, as is seen, titanium silicide contacts  136  and  138  push heavily doped source/drain regions  130  ard  132 , respectively, further into substrate  102 .  
     [0035] In FIG. 1J, the unreacted titanium (including titanium nitride) on spacers  126  is stripped, and a subsequent anneal at 800° C. for 30 seconds is applied to lower the resistivity of titanium silicide contacts  136 ,  138  and  140 .  
     [0036] Further processing steps in the fabrication of IGFETs typically include forming a thick oxide layer over the active regions, forming contact windows in the oxide layer to expose the silicide contacts, forming appropriate interconnect metallization such as aluminum in the contact windows, and forming a passivation layer. In addition, subsequent high-temperature process steps can be used to supplement or replace the anneal step to provide the desired anneal, activation, and drive-in functions.  
     [0037] These further processing steps are conventional and need not be repeated herein. Likewise the principal processing steps disclosed herein may be combined with other steps readily apparent to those skilled in the art.  
     [0038] The present invention includes numerous variations to the embodiment described above. For instance, the gate can be various conductors, and the gate insulator can be various dielectrics. The contact material that is reacted with the gate to form the silicide contacts is preferably a refractory metal. Moreover, a titanium contact material can be deposited on native oxide on the gate, source and drain, since forming titanium silicide contacts reduces or eliminates the native oxide. Therefore, a titanium contact material need not be deposited directly on the gate, source and drain. The subsequent anneal after the unreacted titanium is removed is optional. The conductivity types can be reversed. Suitable N-type dopants include arsenic and phosphorus; suitable P-type dopants include boron B 10 , boron B 11 , and BF x  species such as BF 2 .  
     [0039] If P-type dopants are implanted into the gate, a nitrided gate oxide may be preferred to reduce or eliminate diffusion of the dopants through the gate oxide into the substrate. Furthermore, the doping concentration of the gate should be limited, since too high a doping concentration may inhibit silicide formation and increase sheet resistance. For instance, the doping concentration of arsenic in the gate should not exceed 2×10 20  atoms/cm 3 .  
     [0040] Preferably, the contact material consumes at least one-half of the gate, at which point the gate has a thickness of at most 500 angstroms and the silicide contact on the gate is thicker than the gate. More preferably, the contact material consumes at least three-quarters of the gate, at which point the gate has a thickness in the range of 100 to 200 angstroms and the silicide contact on the gate is at least twice as thick as the gate.  
     [0041] The invention is particularly well-suited for fabricating N-channel MOSFETs, P-channel MOSFETs, and other types of IGFETs, particularly for high-performance microprocessors where high circuit density is essential. Although only a single IGFET has been shown for purposes of illustration, it is understood that in actual practice, many devices are fabricated on a single semiconductor wafer as widely practiced in the art. Accordingly, the invention is well-suited for use in an integrated circuit chip, as well as an electronic system including a microprocessor, a memory and a system bus.  
     [0042] Those skilled in the art will readily implement the steps necessary to provide the structures and methods disclosed herein, and will understand that the process parameters, materials, and dimensions are given by way of example only and can be varied to achieve the desired structure as well as modifications which are within the scope of the invention. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope and spirit of the invention as set forth in the following claims.