Patent Publication Number: US-10325877-B2

Title: Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application is a continuation of and hereby claims priority to co-pending U.S. patent application Ser. No. 14/997,774, filed on Jan. 18, 2016, which claims priority to U.S. provisional patent application Ser. No. U.S. 62/273,145, filed on Dec. 30, 2015, the entirety of each of which is hereby incorporated by reference herein for all purposes. 
    
    
     FIELD 
     The following description relates generally to wire bond wires for vertical integration. More particularly, the following description relates to wire bond wires interconnected to various surfaces of a package for multi-level interconnection with separate surface mount and wire bond mounting surfaces. 
     BACKGROUND 
     Microelectronic assemblies generally include one or more ICs, such as for example one or more packaged dies (“chips”) or one or more dies. One or more of such ICs may be mounted on a circuit platform, such as a wafer such as in wafer-level-packaging (“WLP”), printed board (“PB”), a printed wiring board (“PWB”), a printed circuit board (“PCB”), a printed wiring assembly (“PWA”), a printed circuit assembly (“PCA”), a package substrate, an interposer, or a chip carrier. Additionally, one IC may be mounted on another IC. An interposer may be a passive or an active IC, where the latter includes one or more active devices, such as transistors for example, and the former does not include any active device but may include one or more passive devices, such as capacitors, inductors, and/or resistors. Furthermore, an interposer may be formed like a PWB, namely without any circuit elements, such as without any passive or active devices. Additionally, an interposer may include at least one through-substrate-via. 
     An IC may include conductive elements, such as pathways, traces, tracks, vias, contacts, pads such as contact pads and bond pads, plugs, nodes, or terminals for example, that may be used for making electrical interconnections with a circuit platform. These arrangements may facilitate electrical connections used to provide functionality of ICs. An IC may be coupled to a circuit platform by bonding, such as bonding traces or terminals, for example, of such circuit platform to bond pads or exposed ends of pins or posts or the like of an IC; or an IC may be coupled to a circuit platform by soldering. Additionally, a redistribution layer (“RDL”) may be part of an IC to facilitate a flip-chip configuration, die stacking, or more convenient or accessible position of bond pads for example. 
     Some passive or active microelectronic devices may be used in a System-in-Package (“SiP”) or other multi-die/component package. However, some SiPs may take up too much area for some applications. Moreover, for some low-profile applications, some SiPs may be used; however, forming a SiP for stacking using through substrate vias may be too expensive for some applications. 
     Accordingly, it would be desirable and useful to provide vertical integration for a SiP. 
     BRIEF SUMMARY 
     An apparatus relates generally to a vertically integrated microelectronic package. In such an apparatus, a circuit platform has an upper surface and a lower surface opposite the upper surface thereof. The upper surface of the circuit platform has a wire bond-only surface area. A first microelectronic device is coupled to the upper surface of the circuit platform in the wire bond-only surface area. First wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the first wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. Second wire bond wires are coupled to the upper surface of the circuit platform in the wire bond-only surface area and are coupled to the upper surface of the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. The protective layer has a lower surface and an upper surface opposite the lower surface thereof with the lower surface of the protective layer being in contact with the upper surface of the circuit platform. The upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires. 
     An apparatus relates generally to an inverted vertically integrated microelectronic package. In such an apparatus, a circuit platform has an upper surface and a lower surface opposite the upper surface thereof. The lower surface of the circuit platform has a wire bond-only surface area. A first microelectronic device is coupled to the lower surface of the circuit platform in the wire bond-only surface area. First wire bond wires are coupled to and extend away from a lower surface of the first microelectronic device. A second microelectronic device in a face-up orientation is coupled to lower ends of the first wire bond wires in a surface mount-only area. The second microelectronic device is located below and at least partially underlaps the first microelectronic device. Second wire bond wires are coupled to and extend away from the lower surface of the circuit platform in the wire bond-only surface area and are coupled to the lower surface of the first microelectronic device. A protective layer is disposed under the circuit platform and the first microelectronic device. The protective layer has a lower surface and an upper surface opposite the lower surface thereof with the upper surface of the protective layer being in contact with the lower surface of the circuit platform. The lower surface of the protective layer has the surface mount-only area. The lower surface of the protective layer has the second microelectronic device disposed thereon in the face-up orientation in the surface mount-only area for coupling to the lower ends of the first wire bond wires. 
     An apparatus generally relates to a microelectronic component. In such an apparatus, there is a substrate having a first upper surface. A conductive layer is disposed on the first upper surface including wire bond pads and flip-chip pads respectively having first upper surfaces and second upper surfaces. A solder mask is disposed on the first upper surface between the wire bond pads and the flip-chip pads. The solder mask has a second upper surface disposed above the first upper surfaces and the second upper surfaces. A eutectic layer is disposed on the first upper surfaces and the second upper surfaces. Wire bond wires are respectively bonded to the wire bond pads. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING(S) 
       Accompanying drawing(s) show exemplary embodiment(s) in accordance with one or more aspects of exemplary apparatus(es) or method(s). However, the accompanying drawings should not be taken to limit the scope of the claims, but are for explanation and understanding only. 
         FIG. 1A  is a block diagram of a side view depicting an exemplary conventional system-in-package (“SiP”). 
         FIG. 1B  is a block diagram of a side view depicting another exemplary conventional SiP. 
         FIG. 2  is a corner top-down perspective view depicting an exemplary portion of a conventional electric-magnetic interference (“EMI”) shielding. 
         FIGS. 3A and 3B  are top views of block diagrams depicting respective exemplary SiPs with EMI shielding. 
         FIG. 4  is a block diagram of a cross-sectional side view depicting an exemplary SiP with EMI shielding. 
         FIG. 5  is a block diagram of a cross-sectional side view depicting an exemplary SiP with a conductive cover and with signal wire bond wires in an EMI shielding region under the conductive cover. 
         FIG. 6  is a block diagram of a cross-sectional side view depicting an exemplary SiP with EMI shielding using an upper substrate. 
         FIG. 7  is a block diagram of a top-down view depicting an exemplary portion of a SiP prior to addition of an upper conductive surface of a Faraday cage. 
         FIG. 8  is a block diagram of a top-down view depicting an exemplary portion of another SiP prior to addition of an upper conductive surface of a Faraday cage. 
         FIG. 9A  is a block diagram of a cross-sectional side view depicting an exemplary portion of a package-on-package (“PoP”) device with EMI shielding. 
         FIG. 9B  is a block diagram of a cross-sectional side view depicting an exemplary portion of another PoP device with EMI shielding. 
         FIG. 10  is a block diagram of a cross-sectional side view depicting an exemplary portion of another SiP 
         FIG. 11A  is a block diagram of a cross-sectional side view depicting an exemplary portion of a SiP. 
         FIG. 11B  is a block diagram of a cross-sectional side view depicting an exemplary portion of another SiP. 
         FIGS. 12A through 12D  are respective block diagrams of cross-sectional side views depicting exemplary portions of respective SiPs. 
         FIGS. 13A through 13D  are respective block diagrams of cross-sectional side views depicting exemplary portions of respective SiPs with vertically integrated microelectronic packages. 
         FIGS. 14A through 14D  are respective block diagrams of cross-sectional side views depicting exemplary SiPs for a vertically integrated microelectronic package. 
         FIGS. 15A through 15D  are respective block diagrams of cross-sectional side views depicting an exemplary SiP. 
         FIGS. 16A and 16B  are respective block diagrams of cross-sectional side views depicting exemplary SiPs  100 . 
         FIGS. 17A through 17C  are respective block diagrams of cross-sectional side views depicting exemplary inverted SiPs. 
         FIGS. 18A through 18D  are block diagrams of side views depicting a progression formation of wire bond pads and flip-chip pads on a same substrate. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous specific details are set forth to provide a more thorough description of the specific examples described herein. It should be apparent, however, to one skilled in the art, that one or more other examples or variations of these examples may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same number labels are used in different diagrams to refer to the same items; however, in alternative examples the items may be different. 
     Exemplary apparatus(es) and/or method(s) are described herein. It should be understood that the word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any example or feature described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other examples or features. 
     Interference in microelectronic devices may come from electric-magnetic interference (“EMI”) and/or radio frequency interference (“RFI”). The following description of interference shielding may be used for either or both of these types of interference. However, for purposes of clarity by way of example and not limitation, generally only shielding from EMI is described below in additional detail. 
       FIG. 1A  is a block diagram of a side view depicting an exemplary conventional system-in-package (“SiP”). In SiP  10 , there may be coupled to a package substrate  19  one or more active microelectronic devices  11 , passive microelectronic devices  12 , and/or IC dies  13 . In this example, IC die  13 , which may be a passive or active die, may be subject to EMI. IC die  13  may be wire bonded to package substrate  19  with wire bonds  15  for carrying input/output signals among other signals, a power supply voltage and a ground reference voltage. 
     Package substrate  19  may be formed of thin layers called laminates or laminate substrates. Laminates may be organic or inorganic. Examples of materials for “rigid” package substrates include an epoxy-based laminate such as FR4 or FR5, a resin-based laminate such as bismaleimide-triazine (“BT”), a ceramic substrate (e.g. a low temperature co-fired ceramic (“LTCC”)), a glass substrate, or other form of rigid package substrate. Moreover, a package substrate  19  herein may be a PCB or other circuit board. Other known details regarding conventional SiP  10  are not described for purposes of clarity. 
       FIG. 1B  is a block diagram of a side view depicting another exemplary conventional SiP  10 . SiP  10  of  FIG. 1B  is the same as SiP  10  of  FIG. 1A , except rather than wire bonds  15 , flip-chip (“FC”) interconnects, such as microbumps,  17  are used. Even though microbump interconnects  17  are illustratively depicted, other types of die-surface mount interconnects may be used. Moreover, microbump interconnects  17  may be used in addition to wire bonds  15 , though not illustratively depicted in  FIG. 1B . 
       FIG. 2  is a corner top-down perspective view depicting an exemplary portion of a conventional EMI shielding  20 . In conventional EMI shielding  20 , a top electrically conductive plate  23  may be disposed over a bottom conductive plate  24 , where such bottom conductive plate  24  has a larger surface area than such top conductive plate  23 . 
     Conductive plates  23  and  24  may be respectively coupled to a package substrate  19  with rows of wire bonds  21  and  22 . Thus, two sides of top plate  23  may be wire bonded with corresponding rows of wire bonds  21 , and likewise two sides of bottom plate  24  may be wire bonded with corresponding rows of wire bonds  22 . Non-electrically conductive spacers (not shown) may be used to insulate wire bonds  21  from bottom conductive plate  24 . A microelectronic device (not shown) to be EMI shielded may be sandwiched between top and bottom conductive plates  23  and  24 . This type of EMI shielding with wire bonding may be too bulky for many applications. Furthermore, there may be gaps on opposite sides with respect to wire bonds providing side EMI shielding. 
     Interference Shielding 
       FIGS. 3A and 3B  are top views of block diagrams depicting respective exemplary SiPs  100  with EMI shielding. Each of SiPs  100  may include a package substrate  19  having coupled to an upper surface  132  thereof one or more active microelectronic devices  11 , one or more passive microelectronic devices  12 , and wire bond wires  131 , where lower ends of such wire bond wires  131  may be coupled to an upper surface  132  of package substrate  19 . Upper surface  132  may be a conductive surface. Wire bond wires  131  may include wire diameters equal to or less than approximately 0.0508 millimeters (2 mils). 
     A portion of wire bond wires  131  may be positioned to define a shielding region  133 . Along those lines, rows and columns of a BVA arrangement  136  of wire bond wires  131  may be used to encircle or otherwise surround a shielding region  133 . Upper ends of at least a subset of such wire bond wires  131  surrounding a shielding region  133  may be used to support conductive surface  130 , and such conductive surface  130  may be over such shielding region  133  for covering thereof. 
     Conductive surface  130  may be a rigid or flexible surface which is electrically conductive. In an implementation, conductive surface  130  may be flexible, such as a flexible conductive coating on a surface of a flexible sheet. In another implementation, a rigid plate may provide a conductive surface. A rigid plate may be made of a conductive material. However, a conductive coating may be sprayed or painted on a rigid plate or a flexible sheet. In the example of  FIG. 3B , conductive surface  130  may have holes  137  for allowing upper portions of at least some of wire bond wires  131  defining a shielding region  133  to extend through conductive surface  130 , as described below in additional detail. 
       FIG. 4  is a block diagram of a cross-sectional side view depicting an exemplary SiP  100  with EMI shielding. SiP  100  may include a package substrate  19  having coupled to an upper surface  132  thereof one or more active microelectronic devices  11 , one or more passive microelectronic devices  12 , and wire bond wires  131 , where upper ends of such wire bond wires  131  may be coupled to a conductive surface  130 . Even though a SiP  100  is described, another type of microelectronic package having protection from EMI may be used. 
     Package substrate  19  has an upper surface  132  and a lower surface  149  opposite the upper surface. Package substrate  19  may have a ground plane  140  and vias  142  located between surfaces  132  and  149 , where vias  142  may be interconnected to such ground plane  140  for electrical conductivity. 
     Wire bond wires  131  may be coupled to ground plane  140  with vias  142 . Some wire bond wires  131  may be mechanically coupled to upper surface  132  with ball bonds  141  for electrical conductivity; however, in other implementations, other types of bonding may be used. Moreover, not all wire bond wires  131  need be coupled to ground plane  140 . Some wire bond wires  131  may be used for carrying supply voltages or signals within SiP  100 . Some wire bond wires  131  may be used for coupling to other devices within SiP  100 . 
     An active or passive microelectronic device  145  may be coupled to upper surface  132  of package substrate  19 . Microelectronic device  145  may include an active integrated circuit die and/or a passive component. A passive component may be, e.g., a capacitor, an inductor, or a resistor, or any combination thereof. 
     Microelectronic device  145  may be coupled to package substrate  19  with ball or bump interconnects and/or wire bond wires, as previously described. Moreover, microelectronic device  145  may be coupled to upper surface  132  with an adhesive or an underfill layer (not shown). 
     Microelectronic device  145  may be disposed in a dielectric protective material which may be provided as dam fill or a molding layer (“molding layer”)  143 . Such molding layer  143  may be an encapsulant or a molding material for at least covering an upper surface and sidewalls of microelectronic device  145 . Wire bond wires  131  may be disposed around sidewalls of microelectronic device  145 . 
     Conductive surface  130  may be located upon or coupled to a top or upper surface  146  of dielectric protective material molding layer  143 . However, in another implementation a top surface of dielectric protective material molding layer  143  may be at a higher level than tips  148  of wire bond wires  131 , as described below in additional detail. Conductive surface  130  may be positioned over wire bond wires  131  associated with Faraday cage  153 . Upper ends or tips  148  of such wire bond wires  131  may be mechanically coupled to conductive surface  130 . This coupling may be with a heated press bonding or other form of mechanical coupling. 
     Faraday cage  153  may be a combination of a portion of ground plane  140  interconnected to wire bond wires  131 , such as with vias  142 , supporting a conductive surface  130 . In another implementation, there may be a gap  144  between conductive surface  130  and tips  148  of some of wire bond wires  131 . Along those lines, a bottom of conductive surface  130 , such as of a conductive plate for example, may be attached to or rest upon a top surface of dielectric protective material molding layer  143 , and height of dielectric protective material molding layer  143  may be greater than height of wire bond wires  131 . 
     Thus, a conductive surface  130  may be positioned over a portion of wire bond wires  131  with upper ends or tips  148  thereof spaced apart from conductive surface  130 . However, a configuration with a gap  144  may provide a less effective Faraday cage  153 , and so for purposes of clarity by way of example and not limitation, it shall be assumed that there is no gap. 
     Wire bond wires  131  coupled to ground plane  140  projecting or extending upwardly away from upper surface  132  of package substrate  19  may be arrayed. Along those lines, even though single rows and columns of a Bond Via Array™ or BVA® arrangement  136  of wire bond wires  131  may be present in an implementation, multiple rows and/or multiple columns of wire bond wires  131  of a BVA arrangement  136 , may be present along one or more sides of a shielding region  133 . 
     To recapitulate, some of wire bond wires  131 , such as in BVA arrangement  136  defining a shielding region  133 , may be positioned to provide such a shielding region  133  for microelectronic device  145  from or with respect to EMI. Another portion of wire bond wires  131  located outside of shielding region  133  may not be used for EMI shielding. Moreover, one or more other active or passive microelectronic devices  11  and/or  12  may be coupled to substrate  19  and be located outside of shielding region  133  and not part of, or positioned for such shielding region. 
       FIG. 5  is a block diagram of a cross-sectional side view depicting an exemplary SiP  100  with a conductive cover  150  and with signal wire bond wires  131   s  in an EMI shielding region under conductive cover  150 . SiP  100  of  FIG. 5  is the same as SiP  100  of  FIG. 4 , but with the following differences. 
     In this example, a portion of wire bond wires  131  have a height that is greater than a height of another portion of wire bond wires  131 . Both sets of wire bond wires  131  may be positioned proximate to and around microelectronic device  145 . However, the portion of wire bond wires  131  that are taller may be for providing a shielding region  133  for microelectronic device  145  with respect to EMI. Whereas, the other portion of wire bond wires  131  that are shorter (“wire bond wires  131   s ”) may be signal wires coupling microelectronic device  145  to conductors of package substrate  19 . Some of such shorter wire bond wires  131   s  may be within a Faraday cage  153 . Heights of taller wire bond wires  131  may be limited by low-profile package applications. 
     Conductive cover  150  may be coupled to upper surface  132  of package substrate  19 . Conductive cover  150  may cover components of SiP  100  coupled to upper surface  132  including microelectronic device  145 , microelectronic devices  11 ,  12  and wire bond wires  131 . Wire bond wires  131  not part of BVA arrangement  136  may interconnect conductive cover  150  and ground plane  140 . This coupling may be used to reduce internal noise. However, Faraday cage  153  may be located under cover  150  for internal EMI shielding. Optionally, conductive surface  130  may be omitted in favor of using conductive cover  150  as an upper conductive surface of Faraday cage  153 , with or without a gap  144  between tips  148  and an underside of conductive cover  150 . 
     Some wire bond wires  131  within BVA arrangement  136  may be signal wires, namely wire bond wires  131   s . Wire bond wires  131   s  may not be coupled to ground plane  140 , but may be coupled to traces (not shown) of package substrate  19 . Tips of wire bond wires  131   s  may be bonded or soldered to microelectronic device  145  prior to use of dielectric protective material molding layer  143 . In another implementation, dielectric protective material molding layer  143  may be omitted with respect to microelectronic device  145 . 
     Wire bond wires  131   s  may be bonded to upper surfaces of one or more of passive microelectronic devices  12  or active microelectronic devices  11 . These wire bond wires  131   s  may be for interconnection within SiP  100 . 
       FIG. 6  is a block diagram of a cross-sectional side view depicting an exemplary SiP  100  with EMI shielding using an upper substrate  169 . SiP  100  of  FIG. 6  is the same as SiP  100  of  FIG. 5 , but without a conductive cover  150  and with the following differences. 
     Upper substrate  169  may include vias  162  and a ground plane  160 . Tips or upper ends  148  of wire bond wires  131  may be interconnected to vias  162  along a bottom surface of upper substrate  169  with interconnects  161 , such as with micro balls or microbumps for example, for coupling to ground plane  160 . Interconnects  161  may be disposed on an upper surface  168  of dielectric protective material molding layer  143 . Ground plane  160  may provide an upper conductive surface  130  of Faraday cage  153 . 
     Another microelectronic device  165 , whether active or passive, may be coupled to a top surface of upper substrate  169 . Microelectronic device  165  may be coupled with wire bond wires  15  to vias or traces of substrate  169 ; however, micro balls or microbumps may be used in another implementation. Microelectronic device  165  may be coupled outside of Faraday cage  153 . 
       FIG. 7  is a block diagram of a top-down view depicting an exemplary portion of a SiP  100  prior to addition of an upper conductive surface  130  of a Faraday cage  153 . Bond pads  170  may be positioned proximate to and around microelectronic device  145  for coupling wire bond wires  131  respectively thereto for providing shielding region  133  of Faraday cage  153 . Shielding region  133  may be defined within a BVA arrangement  136 . 
     Bond pads  170  may be spaced apart from one another around sides of dielectric protective material molding layer  143 . Microelectronic device  145  in dielectric protective material molding layer  143  may be located in a central portion of shielding region  133 . A pad-to-pad pitch  171  of bond pads  170  may be equal to or less than approximately 250 microns. Pitch  171  of bond pads  170  may be selected for frequencies associated with interference, such as EMI and/or RFI, to shield microelectronic device  145  from EMI and/or RFI. Moreover, microelectronic device  145  may be an interference radiator, and thus such shielding may be to protect other components of SiP  100  from interference generated by microelectronic device  145 . 
     Even though single rows and columns of bond pads  170  are illustratively depicted, in another implementation there may be more than one or two rows and/or columns. Moreover, rows and/or columns of bond pads  170  may be interleaved with respect to one another to provide denser shielding. Effectively, wire bond wires  131  may be used to provide a low pass filter Faraday cage for reducing EMI with respect to operation of microelectronic device  145 . Along those lines, placement of bond pads  170 , and thus wire bond wires  131  may, though need not be, uniform. Wire bond wires  131  may be placed and/or adjusted for density tailored to shield a particular range of frequencies to or from microelectronic device  145 . 
       FIG. 8  is a block diagram of a top-down view depicting an exemplary portion of another SiP  100  prior to addition of an upper conductive surface  130  of a Faraday cage  153 . In this example, two rows and two columns of a BVA arrangement  136  of wire bond wires  131  are used to define a shielding region  133 . In this example, spacing between rows and columns is interleaved to provide a denser pattern of wire bond wires  131 . 
     In this example, some of wire bond wires  131  of BVA arrangement  136  are for carrying signals, namely wire bond wires  131   s . Along those lines, interconnects  180  may be formed for extending from microelectronic device  145  outside of dielectric protective material molding layer  143  for interconnection with wire bond wires  131   s , which may include one or more signal wires. 
       FIG. 9A  is a block diagram of a cross-sectional side view depicting an exemplary portion of a package-on-package (“PoP”) device  190  with EMI shielding. PoP device  190  may include an upper SiP  100 U stacked on top of a lower SiP  100 L. PoP device  190  may include one or more other microelectronic devices outside of a shielding region as well as other details, such as previously described with reference to  FIGS. 3A through 8  for example. Accordingly, previously described details for SiPs  100  are not described hereinbelow for purposes of clarity and not limitation. 
     A lower package substrate  19 L of a lower SiP  100 L may include a lower ground plane  140 L having lower wire bond wires  131 L extending upwardly from an upper surface of lower package substrate  19 L. Such lower wire bond wires  131 L and ground plane  140 L may be interconnected to one another, such as with vias and ball bonds as previously described, for forming a lower portion of a Faraday cage  153 . Tips  148  of lower wire bond wires  131 L may be bonded or coupled with interconnects  191  to pads and vias therefor along an underneath side of upper package substrate  19 U. 
     Optionally, upper package substrate  19 U may include an upper ground plane  140 U for forming a Faraday cage  153  as a stack of two Faraday cages, namely an upper Faraday cage  192 U and a lower Faraday cage  192 L. Each of Faraday cages  192 U and  192 L may include respective packaged microelectronic devices  145 U and  145 L respectively coupled to upper surfaces of package substrates  19 U and  19 L. 
     Upper ground plane  140 U of upper substrate  19 U may be located over a lower microelectronic device  145 L, so tips or upper ends  148  of lower wire bond wires  131 L may be interconnected to pads or contacts with interconnects  191  along an underside surface of upper package substrate  19 U for electrical coupling to upper ground plane  140 U. Upper wire bond wires  131 U and optional ground plane  140 U may be interconnected to one another, such as with vias and ball bonds as previously described, for forming an upper portion of a Faraday cage  153 . Tips  148  of upper wire bond wires  131 U may be bonded or coupled to conductive surface  130  for completing such upper Faraday cage  192 U. 
     In another implementation, vias of upper substrate package  19 U may interconnect lower wire bond wires  131 L with upper wire bond wires  131 U without being connected to an upper ground plane  140 U to form a “two-story” or bi-level Faraday cage  153  for two microelectronic devices  145 U,  145 L. Even though only two levels are illustratively depicted, more than two levels may be used in other implementations. 
       FIG. 9B  is a block diagram of a cross-sectional side view depicting an exemplary portion of another PoP device  190  with EMI shielding. PoP device  190  may include one or more other microelectronic devices outside of a shielding region as well as other details, such as previously described with reference to  FIGS. 3A through 9A  for example. Accordingly, previously described details for SiPs  100  are not described hereinbelow for purposes of clarity and not limitation. 
     PoP device  190  of  FIG. 9B  may be the same as PoP device  190  of  FIG. 9A , except with the following differences. PoP device  190  of  FIG. 9B  may include signal wire bond wires  131   s . Signal wire bond wires  131   s  may be located within Faraday cage  153 , including within Faraday cage  192 U. 
     Signal wire bond wires  131   s  in this configuration may extend upwardly from an upper surface of a lower microelectronic device  145 L. Tips or upper ends  148  of wire bond wires  131   s  extending from an upper surface of lower microelectronic device  145 L may be interconnected to an underneath side of upper package substrate  19 U, such as with interconnects  191 . Vias and/or traces (not shown) may electrically couple upper and low microelectronic devices  145  with signal wire bond wires  131   s . Moreover, lower substrate package  19 L may include vias and/or traces (not shown) for interconnection with lower microelectronic device  145 . 
       FIG. 10  is a block diagram of a cross-sectional side view depicting an exemplary portion of another SiP  100 . SiP  100  may include one or more other microelectronic devices outside of a shielding region as well as other details, such as previously described with reference to  FIGS. 3A through 9B  for example. Accordingly, previously described details for SiPs  100  are not described hereinbelow for purposes of clarity and not limitation. 
     In this example, wire bond wires  131  and a microelectronic device  145 , such as an IC die, are protected by a dielectric protective material molding layer  143 . Microelectronic device  145  may be interconnected with microbump interconnects  17  to an upper surface of package substrate  19  prior to depositing or injecting dielectric protective material molding layer  143 . Likewise, wire bond wires  131  may be ball bonded to an upper surface of package substrate  19  prior to depositing or injecting dielectric protective material molding layer  143 . 
     Optionally, signal wire bond wires  131   s  may be ball bonded to an upper surface  201  of microelectronic device  145  prior to depositing or injecting dielectric protective material molding layer  143 . Signal wire bond wires  131   s  thus may be within a shielding region  133  of a Faraday cage  153 . 
     Tips or upper ends  148  of wire bond wires  131 , as well as optional signal wire bond wires  131   s , may extend above an upper surface  202  of dielectric protective material molding layer  143 . Solder balls or other interconnect eutectic masses  204  may be deposited onto tips  148  for subsequent interconnection, such as described elsewhere herein. 
     Vertical Integration without Interference Shielding 
       FIG. 11A  is a block diagram of a cross-sectional side view depicting an exemplary portion of a SiP  100 .  FIG. 11B  is a block diagram of a cross-sectional side view depicting an exemplary portion of another SiP  100 . With simultaneous reference to  FIGS. 11A and 11B , SiPs  100  respectively illustratively depicted in those figures are further described. Each of SiPs  100  may include one or more other microelectronic devices as well as other details, such as previously described. Accordingly, previously described details for SiP  100  are not described hereinbelow for purposes of clarity and not limitation. 
     Each of SiPs  100  includes a vertically integrated microelectronic package  200 . Each of microelectronic packages  200  includes a substrate  19  having an upper surface  132  and a lower surface  149  opposite the upper surface. Package substrate  19  may have located between surfaces  132  and  149  a ground plane  140  and vias  142  interconnected to such ground plane for electrical conductivity. 
     A microelectronic device  145  may be coupled to upper surface  132  of substrate  19 , where microelectronic device is a passive microelectronic device. Along those lines, in a SiP  100  there may be one or more of either or both passive or active microelectronic devices coupled to upper surface  132 . This means there are upper surfaces of such microelectronic devices that in the past may have gone unused for vertical integration, such as by having bonding wire bond wires attached to such upper surfaces of such microelectronic devices as described herein. 
     Along those lines, wire bond wires  131  may be coupled to and extend away from the upper surface  132  of substrate  19 , and wire bond wires  231  may be coupled to and extend away from an upper surface  201  of microelectronic device  145 . Wire bond wires  131  and  231  may be mechanically coupled to upper surfaces  132  and  201 , respectively, with ball bonds  141  for electrical conductivity. However, in other implementations, other types of bonding may be used. Wire bond wires  231  are shorter in length than wire bond wires  131 . 
     With reference to  FIG. 11A , wire bond wires  131  may have an overall finished length  261 , and wire bond wires  231  may have an overall finished length  262 . However, finished heights of wire bond wires  131  and  231  may be approximately the same. Tips or upper ends  148  of wire bond wires  131  and  231  may extend above an upper surface  202  of molding layer  143 . 
     Upper ends  148  may be coterminous for being generally coplanar. Solder balls or other interconnect eutectic masses  204  may be deposited on upper surface  202  respectively over upper ends  148  for forming interconnects with pads (not shown) on a front face underside of an active or a passive microelectronic device  165 . 
     A passive microelectronic device  145  may be coupled to upper surface  132  of package substrate  19 . Microelectronic device  145  may include conductive traces and may include only passive components. A passive component may include one or more of a capacitor, an inductor, or a resistor, or any combination thereof. 
     Microelectronic device  145  may be coupled to package substrate  19  with ball or bump interconnects and/or wire bond wires, as previously described. Moreover, microelectronic device  145  may be coupled to upper surface  132  with an adhesive or an underfill layer (not shown). 
     In this implementation, microelectronic device  145 , as well as a microelectronic device  165 , may have orientations facing downwardly, namely face-down orientations, toward upper surface  132  of substrate  19 . However, in another implementation, microelectronic device  165  may have a front side face facing upwardly away from an upper surface  132  of substrate  19 . 
     A microelectronic device  165  may be coupled above uppermost surface  202  of molding layer  143 . In an implementation, a microelectronic device  165  may be coupled to upper ends  148  of wire bond wires  131  and  231  with eutectic masses  204  or other mechanical interconnects. Microelectronic device  165  may be located above microelectronic device  145  and at least partially overlap such microelectronic device  145 . 
     Molding layer  143  may have an uppermost surface  202  and a lowermost surface  252  opposite the uppermost surface. Molding layer  143  may be disposed for surrounding portions of lengths  261  and  262  for both wire bond wires  131  and  231 . Upper ends  148  may not be covered with molding layer  143 , such as by use of a mold assist film for an injection molding for example. In another implementation, molding layer  143  may temporarily completely cover lengths  261  and  262  followed by an etch back to reveal upper ends  148 . 
     In an implementation of a vertically integrated microelectronic package  200 , microelectronic device  145  may be disposed in molding layer  143 . Along those lines, in an implementation, microelectronic device  145  may be completely located between uppermost surface  202  and lowermost surface  252  of molding layer  143 . Wire bond wires  131  may be disposed around sidewalls  203  of microelectronic device  145  though not for interference shielding in this example implementation. 
     Wire bond wires  131  may be coupled to ground plane  140  for projecting or extending upwardly away from upper surface  132  of package substrate  19  and may be arrayed. Along those lines, even though single rows and columns of a BVA® arrangement of wire bond wires  131  and/or  231  may be present in an implementation, multiple rows and/or multiple columns of such wire bond wires may be in a BVA® arrangement. 
     In an implementation of vertically integrated microelectronic package  200 , microelectronic device  165 , which is a passive microelectronic device, may be used. However, in another implementation of vertically integrated microelectronic package  200 , microelectronic device  165 , which is an active microelectronic device, may be used. 
     With reference to  FIG. 11B , inner wire bond wires  131   i  may have an overall finished length  263 , and wire bond wires  231  may have an overall finished length  264 . Outer wire bond wires  131   o  may have an overall finished height  261 , as previously described with reference to  FIG. 11A . Finished heights of wire bond wires  131   i  and  231  may be approximately the same after forming. Upper ends  148  of wire bond wires  131   i  and  231  may generally even with one another. 
     Upper ends  148  of wire bond wires  131   i  and  231  may be coterminous for being generally coplanar. Solder balls or other interconnect eutectic masses  274  may couple a lower surface of an active or passive microelectronic device  271  respectively to upper ends  148  of wire bond wires  131   i  and  231  for forming interconnects with pads (not shown) on a front face underside of an active or passive microelectronic device  271 . A molding material may be injected to form molding material layer  143  with microelectronic device  271  in place, and thus a lower surface of microelectronic device  271  may be in contact with molding material of molding layer  143 . For molding, a mold assist film may be used to allow tips  148  of outer wire bond wires  131   o  to extend above upper surface  202  of molding layer  143 , as well as pads or other interconnects (not shown) of microelectronic device  271 . In another implementation, molding layer  143  may temporarily completely cover lengths  261  followed by an etch back to reveal upper ends  148  thereof. 
     Microelectronic device  271  may be coupled to and located above microelectronic device  145  and may at least partially overlap microelectronic device  145 . Along those lines, microelectronic device  271  may laterally extend outside a perimeter of microelectronic device  145  for interconnection of inner wire bond wires  131   i  between upper surface  132  of substrate  19  and a lower surface of microelectronic device  271  facing such upper surface  132 . Wire bond wires  131   i , as well as wire bond wires  131   o , may be disposed around sidewalls  203  of microelectronic device  145  though not for interference shielding in this example implementation. 
     Again, a passive microelectronic device  145  may be coupled to upper surface  132  of package substrate  19 . Microelectronic device  145  may include conductive traces and may include only active components, only passive components or a combination thereof. A passive component may include a capacitor, an inductor, or a resistor, or any combination thereof. Microelectronic device  145  may be coupled to package substrate  19  with ball or bump interconnects and/or wire bond wires, as previously described. Moreover, microelectronic device  145  may be coupled to upper surface  132  with an adhesive or an underfill layer (not shown). 
     Molding layer  143  may have an uppermost surface  202  and a lowermost surface  252  opposite the uppermost surface. Molding layer  143  may be disposed for surrounding portions of lengths  261  of wire bond wires  131   o  and for surrounding lengths  263  and  264  for both wire bond wires  131   i  and  231 . 
     In an implementation of vertically integrated microelectronic package  200 , microelectronic device  145  may be disposed in molding layer  143  and completely located between uppermost surface  202  and lowermost surface  252  of molding layer  143 . Microelectronic device  271  may be disposed in molding layer  143  and at least partially located between uppermost surface  202  and lowermost surface  252  of molding layer  143 . Microelectronic device  165  may be coupled above uppermost surface  202  of molding layer  143 . 
     For a passive microelectronic device  271 , microelectronic device  271  may include conductive traces and may include only passive components. Microelectronic device  271  may include an RDL. A passive component may be a capacitor, an inductor, or a resistor, or any combination thereof. In this implementation, microelectronic devices  145  and  271 , as well as microelectronic device  165 , have orientations facing downwardly, namely face-down orientations, toward upper surface  132  of substrate  19 . However, in another implementation, microelectronic device  165  and/or microelectronic device  271  may have a front side face facing upwardly away from an upper surface  132  of substrate  19 . 
     In an implementation of vertically integrated microelectronic package  200 , microelectronic device  165 , which is a passive microelectronic device, may be used. However, in another implementation of vertically integrated microelectronic package  200 , microelectronic device  165 , which is an active microelectronic device, may be used. A microelectronic device  165  may be coupled above uppermost surface  202  of molding layer  143  for interconnection with microelectronic device  271 . In an implementation, a microelectronic device  165  may be coupled to an upper surface of microelectronic device  271  with eutectic masses  204  or other mechanical interconnects for electrical conductivity. 
     Microelectronic device  165  may be located above microelectronic device  271  and at least partially overlap such microelectronic device  271 . Along those lines, a microelectronic device  165  may be coupled above uppermost surface  202  of molding layer  143  for interconnection with upper ends  148  of outer wire bond wires  131   o , as well as interconnection with an upper surface of microelectronic device  271 . 
     Wire bond wires  131   i  and  131   o  may be coupled to ground plane  140  for projecting or extending upwardly away from upper surface  132  of package substrate  19  and may be arrayed. Along those lines, even though single rows and columns of a BVA® arrangement of wire bond wires  131   i ,  131   o , and/or  231  may be present in an implementation, multiple rows and/or multiple columns of such wire bond wires may be in a BVA® arrangement. 
       FIG. 12A  is a block diagram of a cross-sectional side view depicting an exemplary portion of another SiP  100 . SiP  100  of  FIG. 12A  may be the same as in  FIG. 11A , except for the following details. In this implementation of a vertically integrated microelectronic package  200 , microelectronic device  165  may be cantilevered for laterally extending over and above a wire bond wire  131 . Along those lines, upper ends  148  of wire bond wires  131  may be interconnected with eutectic masses  204  to a lower surface of a microelectronic device  165 . 
       FIG. 12B  is a block diagram of a cross-sectional side view depicting an exemplary portion of another SiP  100 . SiP  100  of  FIG. 12B  may be the same as in  FIG. 11B , except for the following details. In this implementation of a vertically integrated microelectronic package  200 , microelectronic device  165  is not cantilevered for laterally extending over and above a wire bond wire  131   i . Along those lines, microelectronic device  165  and microelectronic device  271  may have approximately equal surface areas for lower and upper surfaces respectively thereof. 
       FIG. 12C  is a block diagram of a cross-sectional side view depicting an exemplary portion of another SiP  100  with or without integrated wire bond wire EMI shielding. SiP  100  of  FIG. 12C  may be the same as in  FIG. 12A , except for the following details. In this implementation of a vertically integrated microelectronic package  200 , microelectronic device  165  is cantilevered for laterally extending over and above wire bond wires  131  on both a right and a left side of microelectronic device  145  in the figure. Along those lines, upper ends  148  of wire bond wires  131  may be interconnected with eutectic masses  204  to a lower surface of a microelectronic device  165 . Accordingly, it should be appreciated that wire bond wires  131  disposed around a microelectronic device and interconnected to a microelectronic device  165  may be used for fan-out. 
       FIG. 12D  is a block diagram of a cross-sectional side view depicting an exemplary portion of another SiP  100  with or without integrated wire bond wire EMI shielding. SiP  100  of  FIG. 12D  may be the same as in  FIG. 12B , except for the following details. In this implementation of a vertically integrated microelectronic package  200 , microelectronic device  165  is not cantilevered for laterally extending over and above a wire bond wire  131   o . Along those lines, microelectronic device  165  and microelectronic device  271  may have approximately equal surface areas for lower and upper surfaces respectively thereof. Along those lines, upper ends  148  of wire bond wires  131   i  may be interconnected with eutectic masses  274  to a lower surface of a microelectronic device  271 . Accordingly, it should be appreciated that wire bond wires  131   i  disposed around a microelectronic device  145  and interconnected to a microelectronic device  271  may be used for fan-out. 
       FIG. 13A  is a block diagram of a cross-sectional side view depicting an exemplary SiP  100  with a vertically integrated microelectronic package  200 . In this implementation, a vertically integrated microelectronic package  200  may be a stand-alone package coupled to substrate  19  as in  FIG. 12D  of a SiP  100 . As components of SiP  100  have been previously described, such as with reference to  FIG. 4  for example, such description is not repeated. 
     In this implementation, eutectic masses  274 , such as solder balls, are formed on an upper surface  202  of molding layer  143 , on a redistribution layer, or on tips of the wire bond wire bond wires  131   i  and  231 . Eutectic masses  274  interconnect upper ends  148  of wire bond wires  131   i  and  231  to a lower surface of microelectronic device  271 . In another implementation, eutectic masses  274  may be encapsulated in molding layer  143 . In this example, a lower surface of microelectronic device  271  is not in contact with an upper surface  202  of molding layer  143 . 
     Moreover, in this example implementation, signal wire bond wires  131   s  may be encapsulated in molding material of molding layer  143 , excluding contact ends thereof. Signal wire bond wires  131   s  may be shorter than inner wire bond wires  131   i  and may be as previously described for interconnection with a microelectronic device  145 . Along those lines, microelectronic device  271  may be coupled to upper ends  148  of a taller portion of wire bond wires  131  coupled to upper surface  132 , such as wire bond wires  131   i . Microelectronic device  271  may further be coupled to upper ends  148  of wire bond wires  231 . Another portion of wire bond wires  131  coupled to upper surface  132 , such as signal wire bond wires  131   s , may have upper ends  148  thereof coupled to an upper surface of microelectronic device  145 , such as previously described. 
     Optionally, wire bond wires  331  may be coupled to one or more upper surfaces of active microelectronic devices  11  and/or passive microelectronic devices  12 , which microelectronic devices  11  and/or  12  are directly coupled to an upper surface  132  of substrate  19 . 
     Other details regarding SiP  100  of  FIG. 13A  have been previously described, and thus are not repeated for purposes of clarity and not limitation. 
       FIG. 13B  is a block diagram of a cross-sectional side view depicting another exemplary SiP  100  with a vertically integrated microelectronic package  200 . In this implementation, a vertically integrated microelectronic package  200  may be a stand-alone package coupled to substrate  19  as in  FIG. 13A  of a SiP  100 . As components of SiP  100  have been previously described, such as with reference to  FIG. 4  for example, such description is not repeated. 
     SiP  100  of  FIG. 13B  is similar to SiP  100  of  FIG. 13A , except for the following differences. In SiP  100  of  FIG. 13B , vertically integrated microelectronic package  200  omits microelectronic device  271 . Thus, a microelectronic device  165  may be directly coupled to an upper surface  202  of molding layer  143  with eutectic masses  204 , such as previously described. 
       FIG. 13C  is a block diagram of a cross-sectional side view depicting yet another exemplary SiP  100  with a vertically integrated microelectronic package  200 . In this implementation, a vertically integrated microelectronic package  200  may be a stand-alone package coupled to substrate  19  as in  FIG. 13A  of a SiP  100 . As components of SiP  100  have been previously described, such as with reference to  FIG. 4  for example, such description is not repeated. 
     SiP  100  of  FIG. 13C  is similar to SiP  100  of  FIG. 13A , except for the following differences. In SiP  100  of  FIG. 13C , vertically integrated microelectronic package  200  has some wire bond wires  131   i  encapsulated in molding material of molding layer  143  as previously described and has some wire bond wires  131   i  not encapsulated in molding material of molding layer  143 . 
       FIG. 13D  is a block diagram of a cross-sectional side view depicting still yet another exemplary SiP  100  with a vertically integrated microelectronic package  200 . In this implementation, a vertically integrated microelectronic package  200  may be a stand-alone package coupled to substrate  19  as in  FIG. 13B  of a SiP  100 . As components of SiP  100  have been previously described, such as with reference to  FIG. 4  for example, such description is not repeated. 
     SiP  100  of  FIG. 13D  is similar to SiP  100  of  FIG. 13B , except for the following differences. In SiP  100  of  FIG. 13D , vertically integrated microelectronic package  200  does not have wire bond wires  131  encapsulated in molding material of molding layer  143 . 
       FIG. 14A  is a block diagram of a cross-sectional side view depicting further another exemplary SiP  100  with a vertically integrated microelectronic package  200 . As SiP  100  of  FIG. 14A  is similar to SiPs  100  previously described herein, generally only the differences are described below in additional detail for purposes of clarity. 
     In this example implementation, a circuit platform  400  may be a package substrate such as package substrate  19 , a die substrate or interposer, a lead frame, or a routing layer, such as an RDL for example. In this example, a passive microelectronic device  271  is generally represented as a circuit platform  401 , which may be a routing layer, a die substrate or interposer, or a package substrate. Vertical wire bond wires  131   i  may interconnect an upper surface  405  of circuit platform  400  to a lower surface  403  of circuit platform  401 . In this example, microelectronic device  145  is a wire bond-only device, which has a lower surface  406  thereof coupled to an upper surface  405  of circuit platform  401  with an epoxy or other adhesive layer  402  between such facing surfaces. 
     Microelectronic device  145  may be in a face-up orientation. Wire bond wires  131   s  may interconnect an upper surface  405  of circuit platform  401  to an upper surface  407  of microelectronic device  145 . Shorter vertical wire bond wires  231  may interconnect an upper surface  407  of microelectronic device  145  with a lower surface  403  of circuit platform  401 . 
     Dielectric protective material molding layer  143  may be a molding layer or a dam-fill layer and, while shown only covering a portion of the SIP, may alternatively cover any or all of the components in the SIP  100 . Microelectronic device  145  may be coupled with adhesive layer  402  to circuit platform  400 , followed by wire bonding wire bond wires  131   s  and  231 . Wire bond wires  231  and  131   i  may be coupled to a lower surface  403  of circuit platform  401 , prior to adding a molding or dam-filling layer of dielectric protective material molding layer  143 . Dielectric protective material may provide a more rigid structure than just having wire bond wires  131   i  and  231  support circuit platform  401 , as a lower surface  403  and at least portions of a sidewall surface(s)  404  may be covered with such dielectric protective material molding layer  143 . 
       FIG. 14B  is a block diagram of a cross-sectional side view depicting further yet another exemplary SiP  100  with a vertically integrated microelectronic package  200 . As SiP  100  of  FIG. 14B  is similar to SiP  100  of  FIG. 14A , generally only the differences are described below in additional detail. 
     In addition to wire bond wires  231  on an upper surface  407  of microelectronic device  145 , another microelectronic device  410  may have a lower surface thereof coupled to an upper surface of microelectronic device  145  with another epoxy or other adhesive layer  402  between such facing surfaces. Another set of interconnects provided with vertical wire bond wires  432  may be coupled between an upper surface of microelectronic device  410  and a lower surface  403  of circuit platform  401  for electrical communication between microelectronic device  410  and circuit platform  401 . Microelectronic devices  145  and  410  may in combination form a die stack with both of such devices in a face-up orientation for wire bonding to upper surfaces thereof. 
     Furthermore, in addition to having a starting placement of wire bond wires  231  and microelectronic device  410  on upper surface  407  of microelectronic device  145 , another set of wire bond wires  431  may be coupled to upper surface  407  for interconnection with an upper surface  408  of microelectronic device  410 . Wire bond wires  431  may arc over for coupling to upper surface  408 . These wire bond wires  431  may thus interconnect upper faces of microelectronic devices  145  and  410  to one another. Microelectronic devices  145  and  410  may be active devices, passive devices, or a combination of active and passive devices. 
     With simultaneous reference to  FIGS. 14A and 14B , coupled to circuit platform  401  may be either or both a surface mount technology (“SMT”) component, which may be an active or a passive SMT microelectronic device  165 , and a wire bond mount component, such as an active or a passive wire bond microelectronic device  411 . An active or a passive SMT microelectronic device  165  may be mounted face down to an upper surface  441  of circuit platform  401 , and an active or a passive wire bond microelectronic device  411  may be mounted face-up to upper surface  441  of circuit platform  401 . 
       FIG. 14C  is a block diagram of a cross-sectional side view depicting still further yet another exemplary SiP  100  with a vertically integrated microelectronic package  200 . As SiP  100  of  FIG. 14B  is similar to SiP  100  of  FIGS. 14A and 14B , generally only the differences are described below in additional detail. 
     In this example implementation, a lower surface of an interposer or other circuit platform  414  is interconnected to contacts on an upper surface of a face-up microelectronic device  145  with microbumps or other small form factor interconnects  413 . An upper surface of interposer  414  is interconnected to contacts on a lower surface of a face-down microelectronic device  416  with microbumps or other small form factor interconnects  415 . Distal ends of wire bond wires  131   s  may be coupled to an upper surface of interposer  414  for interconnection to an upper surface  405  of circuit platform  400 . Proximal or lower ends of wire bond wires  231  may be coupled to an upper surface of interposer  414 , with distal or upper ends of such wire bond wires coupled to lower surface  403  of circuit platform  401 . By using an interposer  414  and flip-chip or like microelectronic device  416 , more area for wire bond wires  231  and/or  131   s  may be provided, along with more interconnections between microelectronic devices  145  and  416 . 
       FIG. 14D  is the block diagram of  FIG. 14C , though with a molding layer of a protective dielectric material  143  covering circuit platform  400 . This molding layer of protective dielectric material  143  provides interconnect surface  418  above an upper surface  405  of circuit platform  400 . Wire bond wires  131  and  331  may have tips or upper ends thereof extend above surface  418  for interconnection of one or more passive or active circuits. 
     These are some of a variety of implementations of a vertically integrated microelectronic package  200  for a SiP  100 . These or other implementations may be provided in accordance with the description herein. However, above implementations with intermingling of SMT and wire bond devices have been described. As described in additional detail below, surfaces or at least portions thereof may be reserved for either SMT-only or wire bond-only devices. 
     Vertical Integration with Separation of Mounting Surface Types 
     Routings, such as traces and vias, over large distances with respect to coupling microelectronic devices, including without limitation one or more VLSI die, in a multi-die package coupled to a circuit board may result in significant current-resistance drops (“IR drops”) or voltage drops. Along those lines, conventionally, VLSI dies have been designed with bond pads or other wire bond contacts at or around a periphery of such dies or packages for interconnection of wire bonds. Moreover, as VLSI dies and multi-die packages become larger, distances to active areas or distances to components, respectively, becomes longer, and these longer distances may result in correspondingly larger IR drops. With respect to VLSI dies and multi-die packages, differences in lengths of, as well as differences in parasitic effects on, routings may cause differences or variations in signals transported thereon. With respect to integrated circuit dies, these on-chip differences may be referred to as on-chip variation (“OCV”). Such differences may affect voltage level, timing (i.e., signal propagation delay), and/or signal interaction, as well as other parameters. In some instances, a VLSI die or a multi-die package may be slowed and/or draw additional power to account for such OCVs or IR drops. 
     With the above context borne in mind, routing distances, such as for VLSI dies and/or SiPs are further described. To reduce the effect of IR drops, capacitance may be added, as is known, to adjust a resistance-capacitance (“RC”) timing delay. However, capacitors may be large and not readily integrated into a VLSI process, and thus external capacitors may be coupled to a VLSI die. SiP applications may include without limitation one or more VLSI die wire bonded to a platform along with one or more SMT components coupled to a same platform. SiPs may be used in RF as well as other applications, which may include surface mount components, such as oscillators, capacitors, couplers, and/or diplexers among other components. 
     In a SiP, wire bond and surface mount components may be mounted together on a same mounting surface. Along those lines, surface mount components may be coupled to a package substrate, such as an interposer or a lead frame, or a routing layer, such as an RDL, with gaps between such surface mount components for subsequent mounting of wire bond components to such package substrate or routing layer. These gaps may be sufficiently wide to avoid having solder flux and/or solder, or other material associated with a eutectic coupling, contaminate wire bonding pads or wire bonding contacts. This spacing effectively increases IR drops by increasing distances between components. 
     As described below in additional detail, a SiP or other multi-microelectronic device package may have a circuit platform which has a wire bond-only surface or has a portion for two or more wire bond-only components without any surface mount technology (“SMT”) components between such two or more wire bond-only components. A molding or dam-fill layer may be added over and on such circuit platform of wire bonded components, such as one or more VLSI die for example, to provide a surface mount-only area, namely a surface mount technology-only (“SMT-only”) surface area (“SMT-only area”), which at least partially corresponds to such wire bond-only surface area or surface area portion (“wire bond-only area”). 
       FIG. 15A  is a block diagram of a cross-sectional side view depicting an exemplary SiP  100 . SiP  100  is a vertically integrated microelectronic package including a circuit platform  400  having an upper surface  405  and a lower surface  505  opposite such upper surface thereof. Balls or other interconnects  501  may be coupled to lower surface  505 . One or more integrated circuit dies or other microelectronic devices  502  and/or  503  may be coupled to upper surface  405 . In this example, integrated circuit dies  502  are coupled to upper surface  405  with microbumps  413 . In this example, integrated circuit dies  503  are coupled to upper surface  405  with an adhesive layer  402 . Moreover, in this example, integrated circuit dies  502  and  503  are active components, but in another implementation one or more of such integrated circuit dies  502  and/or  503  may be passive components. 
     A portion  508  of the area of upper surface  405  may be a wire bond-only area for coupling of one or more integrated circuit dies  503 , and another portion  509  of the area of upper surface  405  may be an SMT-only area for coupling of one or more integrated circuit dies  502 . To avoid flux or other contamination of an SMT-only area from contaminants associated with wire bonding, areas  508  and  509  may be spaced apart from one another by a gap area  507 . 
     SMT integrated circuit dies  502  may be coupled in a face-down orientation in SMT-only area  509 , and wire bonded integrated circuit dies  503  may be coupled in a face-up orientation in wire bond-only area  508 . Wire bond wires  131  may be coupled to and extend away from wire bond-only area  508  of upper surface  405  for interconnection to a passive microelectronic device  512 . Wire bond wires  131  may be outside of a perimeter of a corresponding integrated circuit die  503 . 
     Wire bond wires  231  may be coupled to and extend away from an upper surface  407  of microelectronic device  503  for interconnection to a passive microelectronic device  512 , where wire bond wires  231  may be shorter than wire bond wires  131 . Wire bond wires  231  may be inside of a perimeter of a corresponding integrated circuit die  503 . Passive microelectronic device  512  may be located above and at least partially overlap upper surface  407 . 
     Microelectronic device  512  may be coupled to upper ends of wire bond wires  131  and  231 . Wire bond wires  531  may be coupled to upper surface  405  in wire bond-only area  508  and to upper surface  407 . Wire bond wires  509  may be coupled to upper surfaces  407  of neighboring integrated circuit dies  503  in wire bond-only area  508 . Along those lines, one or more passive microelectronic devices  512  may be above and within wire bond-only area  508 . Neighboring integrated circuit dies  503  within wire bond-only area  508  may have wire bond wires, such as wire bond wires  531  and  131 , coupled to upper surface  405  between sidewalls/perimeters of such integrated circuit dies  503  without any SMT devices in such space between such integrated circuit dies  503 . 
     A molding layer  143  may be disposed over circuit platform  400  and one or more microelectronic devices  502  and  503 . Molding layer  143  may be disposed for surrounding at least portions of lengths of wire bond wires  131  and  231  and for covering wire bond wires  509  and  531 . Along those lines, upper ends of wire bond wires  131  and  231  may extend above an upper surface  202  of molding layer  143 . Molding layer  143  may have a lower surface  252  in contact with upper surface  405  and may have an upper surface  202  opposite such lower surface  252 . Upper surface  202  may be an SMT-only surface or have a portion thereof which is SMT-only, such as SMT-only portion or area  510 . SMT-only area  510  may be opposite to and may correspond with wire bond-only area  508 . 
     One or more passive microelectronic devices  512  may be disposed on upper surface  202  in a face-down orientation for coupling contacts thereof to upper ends of wire bond wires  131  and  231 . This SMT coupling may be performed by a Thermosonic bonding or reflow soldering operation. 
     To recapitulate, one or more integrated circuit dies  502  and/or  503  may be disposed in molding layer  143 , thus completely located between upper surfaces  202  and  405 . However, one or more microelectronic devices  512  may be coupled above upper surface  202  in an SMT-only area  510 , which may correspond to a wire bond-only area  508 . 
     By positioning one or more microelectronic devices  512  in close proximity to an integrated circuit die  503  by use of wire bond wires  131  and  231 , as compared routings, such as traces and vias, through a circuit board resulting in over longer distances, significant reductions in IR drops may be obtained. Moreover, because differences in lengths of, as well as differences in parasitic effects on, routings may cause differences or variations in signals transported thereon, by having shorter distances to travel these differences may be reduced by use of wire bond wires  131  and  231 . 
     To reduce the effect of IR drops, capacitance may be added, as is known, to adjust an RC timing delay. However, capacitors may be large and not readily integrated into a VLSI process, and thus external capacitors may be coupled to a VLSI die. Thus, by having an ability to have capacitors significantly larger than those in a VLSI die, RC timing delay may be more readily addressed. Moreover, such additional capacitance may be added to a central region of a VLSI die, where RC delay from signals from bond pads around a periphery of such a VLSI die may take a significant amount of time to reach a central interior region of such a VLSI die. SiPs  100  may be used in RF as well as other applications, which may include surface mount components, such as oscillators, capacitors, couplers, and/or diplexers among other passive SMT components  512  coupled to surface  202 . 
     In a SiP  100 , wire bond and surface mount components may be mounted together on separate mounting surfaces. Along those lines, wire bond components may be coupled to a package substrate, such as an interposer or a lead frame, or a routing layer, such as an RDL, with narrower gaps in wire bond-only area  508  between such wire bond components than a mix of SMT and wire bond components mounted in an area outside of such wire bond-only area  508  to such package substrate or routing layer. Gaps between components in a wire bond-only area  508  may be sufficiently wide to avoid having solder flux and/or solder, or other material associated with a eutectic coupling, contaminate neighboring wire bonding pads but such gaps may be substantially narrower than gaps for having SMT components in such mix. This wire bond-only spacing effectively decreases IR drops by decreasing distances between components, namely by effectively relocating for example a passive microelectronic device  512  to upper surface  202  rather than mounting such component on lower surface  252 . 
     As described above in additional detail, a SiP  100  or other multi-microelectronic device package  100  may have a circuit platform  400  which has a wire bond-only surface  508  or has a surface portion  508  for wire bond-only components without any SMT components between such wire bond-only components. A molding or dam-fill layer  143  may be added over and on such circuit platform and wire bonded components, such as one or more VLSI die for example, to provide an SMT-only surface area  202  corresponding to such wire bond-only surface or surface portion  508 . 
     Because an external capacitor for a passive microelectronic device  512  may be used for an integrated circuit die  503 , such passive microelectronic device may be orders of magnitude greater than an internal capacitor of integrated circuit die  503 . Along those lines, passive microelectronic device  512  may have a capacitance of 0.1 or more microfarads. In addition to such a larger capacitance, a larger frequency of response may be obtained for an integrated circuit die  503  using such a close proximity external passive microelectronic device  512 . Along those lines, a capacitor for a passive microelectronic device  512  may be coupled to an integrated circuit die  503  for a frequency response of 1 or more GHz. It should be appreciated that capacitance and inductance are “competing” forces. However, by having short wires for wire bond wires  131  and  231  in comparison to having an external capacitor coupled to a PCB, self-inductance may be reduced allowing for such a frequency of response. Along those lines, wire bond wires  131  may have approximately a nanohenry or less of self-inductance, and of course, shorter wire bond wires  231  may have less self-inductance than longer wire bond wires  131 . 
     Even though a passive microelectronic device  512  is described, an active microelectronic device  511  may be coupled to an upper surface  202 , as described below in additional detail.  FIG. 15B  is a block diagram of a cross-sectional side view depicting another exemplary SiP  100 . SiP  100  is a vertically integrated microelectronic package including a circuit platform  400  having an upper surface  405  and a lower surface  505  opposite such upper surface thereof. Balls or other interconnects  501  may be coupled to lower surface  505 . 
     One or more integrated circuit dies or other microelectronic devices  503  may be coupled to upper surface  405 . In this example, integrated circuit dies  503  are coupled to upper surface  405  with an adhesive layer  402 . Moreover, in this example, integrated circuit dies  503  are active components, but in another implementation one or more of such integrated circuit dies  503  may be passive components. 
     At least a portion of the area of upper surface  405  may be a wire bond-only area  508  for coupling of one or more integrated circuit dies  503 . Along those lines, in an implementation, upper surface  405  may be a wire bond-only surface, with no portion thereof for SMT coupling of any integrated circuit die  502 . Therefore, gaps provided by gap areas  507  may be avoided for a more densely packed surface with wire bond-only components, such as integrated circuit dies  503 , as avoiding flux or other contamination of an SMT-only area from contaminants associated with wire bonding may be provided by having a wire bond-only upper surface  405 . 
     Wire bonded integrated circuit dies  503  may be coupled in a face-up orientation in wire bond-only area  508 , and other wire bonded integrated circuit dies  503 - 1  may be coupled with adhesive layers  402 - 1  on upper surfaces  407  of corresponding wire bonded integrated circuit dies  503 . Wire bonded integrated circuit dies  503 - 1  may be coupled in a face-up orientation for wire bond wires  531 - 1  coupled between upper surfaces  407  of integrated circuit dies  503  and  503 - 1 . Wire bonded integrated circuit dies  503 - 1  may be coupled in a face-up orientation for wire bond wires  531 - 2  coupled between upper surface  252  and upper surfaces  407  of integrated circuit dies  503 - 1 . A portion of wire bond wires  531 - 1  and/or  531 - 2  may extend above an upper surface  202 . 
     Wire bond wires  131  may be coupled to and extend away from wire bond-only area  508  of upper surface  405  for interconnection to a passive microelectronic device  512  or an active microelectronic device  511 . Wire bond wires  131  may be outside of a perimeter of a corresponding integrated circuit die  503 . 
     Wire bond wires  231  may be coupled to and extend away from an upper surface  407  of a microelectronic device  503  for interconnection to a passive microelectronic device  512 , where wire bond wires  231  may be shorter than wire bond wires  131 . Wire bond wires  231 - 1  may be coupled to and extend away from an upper surface  407  of a microelectronic device  503 - 1  for interconnection to a passive microelectronic device  412 , where wire bond wires  231 - 1  may be shorter than wire bond wires  231 . Wire bond wires  231 - 1  may be inside of a perimeter of a corresponding integrated circuit die  503 - 1 . Passive microelectronic devices  412  may be located above and at least partially overlap upper surfaces  407  of both of microelectronic devices  503  and  503 - 1 . 
     Microelectronic devices  512  may be coupled to upper ends of wire bond wires  131  and  231 , and microelectronic devices  412412  may be coupled to upper ends of wire bond wires  231 - 1 . Wire bond wires  531  may be coupled to upper surface  405  in wire bond-only area  508  and to an upper surface  407  of integrated circuit die  503 , and wire bond wires  531 - 1  may be coupled to an upper surface  407  of an integrated circuit die  503  in wire bond-only area  508  and to an upper surface  407  of an integrated circuit die  503 - 1  of a die stack of wire bonded-only integrated circuit dies  503  and  503 - 1 . Wire bond wires  509  may be coupled to upper surfaces  407  of neighboring integrated circuit dies  503  in wire bond-only area  508 . Along those lines, one or more passive microelectronic devices  512  may be above and within wire bond-only area  508 . Neighboring integrated circuit dies  503  within wire bond-only area  508  may have wire bond wires bonded to upper surface  405 , such as wire bond wires  131 ,  531  and  531 - 2 , between sidewalls/perimeters of such integrated circuit dies  503  without any SMT devices in such space between such integrated circuit dies  503  within wire bond-only area  508 . 
     A molding layer  143  may be disposed over circuit platform  400  and one or more microelectronic devices  503  and  503 - 1 . Molding layer  143  may be disposed for surrounding at least portions of lengths of wire bond wires  131 ,  231  and  231 - 1  and for covering wire bond wires  509  and  531 , as well as all or at least portions of wire bond wires  532 - 1  and/or  531 - 2 . Along those lines, upper ends of wire bond wires  131 ,  231  and  231 - 1  may extend above an upper surface  202  of molding layer  143 . Molding layer  143  may have a lower surface  252  in contact with upper surface  405  and may have an upper surface  202  opposite such lower surface  252 . Upper surface  202  may be an SMT-only surface or have a portion thereof which is SMT-only, such as SMT-only portion or area  510 . SMT-only area  510  may be opposite to and may correspond with wire bond-only area  508 . 
     One or more active or passive microelectronic devices  511 ,  512  and/or  412  may be disposed on upper surface  202  in a face-down orientation for coupling contacts thereof to upper ends of wire bond wires  131 ,  231  and  231 - 1 . This coupling may be performed by a Thermosonic or reflow operation. One or more of active or passive microelectronic devices  511 ,  512  and/or  512 - 1  may be an integrated passive device (“IPD”), such as to provide an array of resistors, capacitors, couplers, diplexers, or the like as SMT passive devices. Such packaged devices may be coupled by solder printing (“reflow”) with all such packaged devices having previously been packaged in a less contaminant environment clean room than that associated with reflow. 
     In another implementation, wire bond wires  531 - 1  and  531 - 2  may be completely covered by molding layer  143 . It should be understood that by having an SMT-only surface  202 , SMT components need not be exposed to heating associated with wire bond wiring. In this example, passive microelectronic devices  412  may be centrally located to integrated circuit dies  503 - 1 ; however, in another implementation, such interconnections may be offset from a central location of an integrated circuit die. 
     By separating SMT and wire bond surfaces, planar area of a package or module may be reduced. Accordingly, for planar area limited applications, such a package or module as described herein may be used. Additionally, such a module or package may have an external capacitor closer to an integrated circuit die than routing through a PCB. Moreover, having larger capacitors, larger resistors, or other external passive components in comparison to chip internal capacitances and resistances, means that fewer capacitors and fewer resistors may be used in a chip. Again, a lower IR drop and a lower self-inductance may be obtained as compared with external capacitors coupled to an integrated circuit die through a PCB. Moreover, parasitic values associated with routing through a PCB may likewise be avoided by using embedded wire bond wires, such as wire bond wires  131 ,  231 , and  231 - 1 . Moreover, for an RF application, less mismatch in compensation, such as bandgap and/or filter mismatch, may be obtained by having a shorter distance using embedded wire bond wires. 
       FIG. 15C  is a block diagram of a cross-sectional side view depicting yet another exemplary SiP  100 . As SiP  100  of  FIG. 15C  is similar to that of  FIG. 15B , generally only the differences are described below in additional detail for purposes of clarity and not limitation. In the example implementation of  FIG. 15C , a VLSI die  503  displacing a large planar area is illustratively depicted. Along those lines, bond pads  541  on an upper surface  407  of such VLSI die  503  may be disposed around a periphery thereof for interconnection with wire bond wires  531  and/or  509 . In some implementations, such bond pads  541  may be removed from active areas of such a VLSI die  503  centrally located thereto. Therefore, coupling of an external capacitor through peripherally located bond pads  541  may lessen impact of such capacitance with respect to such centrally located active area transistors and/or other components. However, by having centrally located bond pads  541  interconnected to a passive microelectronic device  512  via wire bond wires  231 , propagation delay and parasitic influences of such routing to peripheral bond pads may be avoided. 
       FIG. 15D  is a block diagram of a cross-sectional side view depicting still yet another exemplary SiP  100 . As SiP  100  of  FIG. 15D  is similar to that of  FIG. 15C , generally only the differences are described below in additional detail for purposes of clarity and not limitation. In the example implementation of  FIG. 15D , a VLSI die  503  displacing an even larger planar area is illustratively depicted. In this example, bond pads  541  on an upper surface  407  of such VLSI die  503  disposed around a periphery thereof for interconnection with wire bond wires  531  and/or  509  may be even further removed from active areas. In this example, more than one passive microelectronic device  512  is coupled to centrally located bond pads  541  via wire bond wires  231  to reduce IR drop, propagation delay and/or parasitic influences of routing to peripheral bond pads thereof. 
       FIGS. 16A and 16B  are respective block diagrams of a cross-sectional side view depicting exemplary SiPs  100 . As SiPs  100  of  FIGS. 16A and 16B  are similar to that of  FIGS. 15B through 15C , generally only the differences are described below in additional detail for purposes of clarity. In the example implementation of  FIG. 16A , circuit platform  400  is thinned for a low profile application. In the example implementation of  FIG. 16B , a removable circuit platform  400  is removed for a direct attachment application, such as to a lead frame or next level assembly or die. 
       FIGS. 17A through 17C  are respective block diagrams of a cross-sectional side view depicting exemplary inverted SiPs  100 . As SiPs  100  of  FIGS. 17A through 17C  are same or similar to SiPs  100  previously described herein, generally only differences are described for purposes of clarity and not limitation. 
     With reference to  FIG. 17A , balls  501  may be removed from circuit platform  400  for disposition on SMT-only surface  202 . Thus, an SMT-only surface  202  of molding layer  143  may include coupling of balls  501  to contact pads  502  thereof. Thickness of balls  501  may be greater than thickness of one or more SMT components, such as passive SMT microelectronic device  512  for example, coupled to surface  202 . Ends of wire bond wires  131  and/or  231 , which may be attached to contact pads  502 , may be directly coupled to balls  501 . In this example, by having embedded wire bond wires  231 , which may be eBVA™ wires, directly coupled between an integrated circuit die  503  or  503 - 1  in a face-down orientation and an externally accessible ball  501 , additional ESD circuitry may be added to such integrated circuit die. Along those lines, a passive SMT microelectronic device  512  may at least partially underlap an integrated circuit die  503  or  503 - 1 , where such passive SMT microelectronic device  512  is in a face-up orientation. 
     With reference to  FIG. 17B , SiP  100  of  FIG. 17B  is the same as that of  FIG. 17A , except surface  505  of circuit platform  400  is used for coupling wire bond integrated circuit dies  503  and  503 - 1  with an adhesive layer  402 , such as previously described as with reference to coupling to surfaces  405  and  407 , respectively. Moreover, wire bond wires  509 ,  531  and  531 - 1  may be used for interconnecting such integrated circuit dies  503  and  503 - 1  above surface  505 , such as previously described though for surface  405 . In this example, surface  505  may be a wire bond-only surface. 
     With reference to  FIG. 17C , SiP  100  of  FIG. 17C  is the same as that of  FIG. 17A , except surface  505  of circuit platform  400  is used for coupling SMT integrated circuit dies  502  with flip-chip microbumps  413 . Moreover, microbumps  413  may be used for coupling SMT integrated circuit dies  502  above surface  505 , such as previously described though for surface  405 . In this example, surface  505  may be an SMT-only surface. 
     Wire Bond on Solder 
     It has been assumed that wire bond wires are wirebonded onto a conductive metal layer, such as copper for example. However, as described below in additional detail, wire bond wires may be wirebonded onto solder. Along those lines, Electroless Nickel (Ni) Electroless Palladium (Pd) Immersion Gold (Au) (“ENEPIG”) is a surface finish for substrate fabrication, such as for ICs. However, as IC manufacturers move away from ENEPIG substrates for flip-chip applications, having a substrate with a mix of copper with an organic surface protection (“OSP”) layer and an ENEPIG finish is problematic. Along those lines, as described below in additional detail a copper OSP uses a solder-on-pad (“SOP”) for a laminated surface, where wire bond wires, such as of BVA™ pins, are bonded onto such solder. 
       FIGS. 18A through 18D  are block diagrams of side views depicting a progression formation of wire bond pads and flip-chip pads on a same substrate  600 . Substrate  600  may be a package substrate or other substrate as described hereinabove for a SiP or other microelectronic component  650 . Along those lines, wire bond pads with solder as described below in additional detail may be used for above-described wire bond wires, such as ball bonded for example, to such pads. 
     With reference to  FIG. 18A , substrate  600  may have deposited, plated, or otherwise formed on an upper surface  605  thereof a conductive layer  603 , such as a layer of copper or other conductive metallic layer for example. Conductive layer  603  may be patterned for providing both wire bond pads  601  and flip-chip or like small form factor pads  602  on upper surface  605 . 
     A solder mask  604  may be deposited and patterned. Along those lines, an upper surface  616  of conductive layer  603  may be below an upper surface  615  of solder mask  604 , and portions of solder mask  604  may be located between neighboring pads of pads  601  and  602 . Along those lines solder mask  604  may have gaps  606  for access to wire bond pads  601  and narrower gaps  607  for access to flip-chip pads  602 . 
     With reference to  FIG. 18B , solder or other eutectic pads  608  and  609  of a solder or other eutectic layer may be printed onto upper surfaces  616  of pads  601  and  602 . The ratio of a surface area of an exposed upper surface  616  of a wire bond pad  601  to a surface area of a lower surface  617  of a solder pad  608  resting thereon may be substantially smaller than the ratio of a surface area of an exposed upper surface  616  of a wire bond pad  602  to a surface area of a lower surface  617  of a solder pad  609  resting thereon. A portion of each of solder pads  608  and  609  may be higher than upper surface  615  of solder mask  604 , and a portion of solder pad  609  may overlap onto upper surface  615 . Upper surface  615  is above or higher than upper surfaces  616 . 
     With reference to  FIG. 18C , after reflow of solder pads  608  and  609 , solder thereof may spread out, and a volume of flux may be eliminated. Along those lines, a solder pad  608  may spread out over what was an exposed surface area of wire bond pad  601  corresponding thereto. Along those lines, upper surfaces  611  of solder pads  608  after reflow may be below or lower than upper surface  615  of solder mask layer  604 . However, upper surfaces  613  of solder pads  609  after reflow may be above, and may overlap, upper surface  615  of solder mask layer  604 . Optionally, after reflow, solder pads  609  may be tamped down for flattening. 
     With reference to  FIG. 18D , wire bond wires, such as wire bond wires  131  for example, may be bonded, such as ball, stitch or otherwise, to solder pads  608 . Along those lines, solder along upper surfaces  611  of solder pads  608  may adhere to copper, palladium or other material of wire bond wires  131 . A flip-chip IC die  649  may have flip-chip contacts  648 , such as microbumps for example, respectively coupled to solder pads  609 . 
     While the foregoing describes exemplary embodiment(s) in accordance with one or more aspects of the invention, other and further embodiment(s) in accordance with the one or more aspects of the invention may be devised without departing from the scope thereof, which is determined by the claim(s) that follow and equivalents thereof. Claim(s) listing steps do not imply any order of the steps. Trademarks are the property of their respective owners.