Patent Publication Number: US-6992896-B2

Title: Stacked chip electronic package having laminate carrier and method of making same

Description:
CROSS-REFERENCE TO CO-PENDING APPLICATION 
     This application is a continuation-in-part of application Ser. No. 10/394,107, filed Mar. 24, 2003 and entitled “Multi-Chip Electronic Package Having Laminate Carrier” (inventors: L Fraley et al), which is a continuation-in-part of application Ser. No. 10/354,000, filed Jan. 30, 2003, now U.S. Pat. No. 6,828,514 and entitled, “High Speed Circuit Board And Method For Fabrication” (inventors: B. Chan et al). 
    
    
     TECHNICAL FIELD 
     The present invention relates, in general, to an electronic package for mounting of integrated circuits, and in particular, to an organic, multi-layered laminated interconnect structure for use in such a package. 
     BACKGROUND OF THE INVENTION 
     Organic laminate substrates, for example printed circuit boards and chip carriers, have been and continue to be developed for many applications. One such chip carrier is sold under the name HyperBGA by the assignee of this invention. (HyperBGA is a registered trademark of Endicott Interconnect Technologies, Inc.) These are expected to displace ceramic substrates in many chip carrier applications, because of reduced cost and enhanced electrical performance. The use of a multi-layered interconnect structure such as an organic, laminate chip carrier for interconnecting a semiconductor chip to a printed circuit board in an electronic package introduces many challenges, one of which is the reliability of the connection joints between the semiconductor chip and the organic chip carrier and another of which is the reliability of the connection joints between the organic chip carrier and the printed circuit board. 
     As semiconductor chip input/output (I/O) counts increase beyond the capability of peripheral lead devices and as the need for both semiconductor chip and printed circuit board miniaturization increases, area array interconnects are the preferred method for making large numbers of connections between a semiconductor chip and an organic chip carrier (such as the aforementioned HyperBGA chip carrier) and between the organic chip carrier and a printed circuit board. If the coefficient of thermal expansion (CTE) of the semiconductor chip, the organic chip carrier, and the printed circuit board are substantially different from one another, industry standard semiconductor chip array interconnections to the organic chip carrier can exhibit high stress during operation (thermal cycling). Similarly, the industry standard ball grid array (BGA) interconnections between the organic chip carrier and printed circuit board can also exhibit high stress during operation. Significant reliability concerns may then become manifest by failure of the connections or even failure of the integrity of the semiconductor chip (chip cracking). These reliability concerns significantly inhibit design flexibility. For example, semiconductor chip sizes may be limited or interconnect sizes, shapes and spacing may have to be customized beyond industry standards to reduce these stresses. These limitations may limit the electrical performance advantages of the organic electronic package or add significant cost to the electronic package. Typically a semiconductor chip has a CTE of 2–3 parts per million per degree Celsius (ppm/° C.) while a standard printed circuit board has a much greater CTE of 17–20 ppm/° C. 
     One example of an organic chip carrier designed to overcome such CTE and related problems is defined in U.S. Pat. No. 6,351,393 (J. S. Kresge et al) which includes a specific thermal internally conductive layer designed to prevent failure between the single chip and the carrier solder connections, and those between the carrier and base substrate (e.g., PCB) on which it is positioned. This patent is incorporated herein by reference. 
     Other examples of various electronic packages such as the above are shown and described in the following documents: 
     
       
         
           
               
             
               
                   
               
             
            
               
                 U.S. Patents 
               
               
                   
               
            
           
           
               
               
               
               
            
               
                   
                 4,882,454 
                 November 1989 
                 Peterson et al 
               
               
                   
                 5,072,075 
                 December 1991 
                 Lee et al 
               
               
                   
                 5,121,190 
                 June 1992 
                 Hsiao et al 
               
               
                   
                 5,483,421 
                 January 1996 
                 Gedney et al 
               
               
                   
                 5,615,087 
                 March 1997 
                 Wieloch 
               
               
                   
                 5,661,089 
                 August 1997 
                 Wilson 
               
               
                   
                 5,798,563 
                 August 1998 
                 Fielchenfeld et al 
               
               
                   
                 5,838,063 
                 November 1998 
                 Sylvester 
               
               
                   
                 5,894,173 
                 April 1999 
                 Jacobs et al 
               
               
                   
                 5,900,675 
                 May 1999 
                 Appelt et al 
               
               
                   
                 5,926,377 
                 July 1999 
                 Nakao et al 
               
               
                   
                 5,982,630 
                 November 1999 
                 Bhatia 
               
               
                   
                   
               
            
           
           
               
            
               
                 Foreign Patent Documents 
               
               
                   
               
            
           
           
               
               
               
               
            
               
                   
                 JP 
                   1-307294 
                 December 1989 
               
               
                   
                 JP 
                   6-112271 
                 April 1994 
               
               
                   
                 JP 
                   9-232376 
                 September 1997 
               
               
                   
                 JP 
                  10-209347 
                 August 1998 
               
               
                   
                 JP 
                  11-087560 
                 March 1999 
               
               
                   
                 JP 
                 2000-022071 
                 January 2000 
               
               
                   
                 JP 
                 2000-024150 
                 January 2000 
               
               
                   
                   
               
            
           
         
       
     
     In order to increase the operational characteristics of such modules, the addition of more than one chip to the upper surface of a chip substrate has been considered. However, due to the operating temperatures of such added chips, especially if placed in a closely spaced orientation, a much higher temperature compensating substrate material, ceramic, has usually been required, especially when the substrate having the chips is to be mounted on and coupled to an organic substrate such as a typical PCB. Examples are described in the following IBM Technical Disclosure Bulletins (TDBs): 
     
       
         
           
               
               
               
             
               
                   
               
             
            
               
                 July 1978 
                 Multi Chip Cooling Plate 
                 pp 745–746 
               
               
                 Febraury 1982 
                 Simultaneous Chip Placement -  
                 pp 4647–4649 
               
               
                   
                 Multi-Chip Modules 
               
               
                 November 1987 
                 High Performance 
                 pp 437–439 
               
               
                   
                 Multi-Chip Module 
               
               
                 August 1988 
                 Low-Cost, High-Power, Multi-Chip 
                 pp 451–452 
               
               
                   
                 Module Design 
               
               
                 September 1993 
                 Thermally Conductive Substrate 
                 pp 623–624 
               
               
                   
                 Mounted Multi-Chip Module Cap 
               
               
                   
               
            
           
         
       
     
     The use of ceramic, however, poses many problems, a primary one of which is handling. Ceramic is a relatively brittle material capable of cracking and chipping if handled improperly, especially during manufacture and shipping. Ceramic is also a relatively difficult material to process, especially to the multi-depth level where several individual layers of insulative and interconnecting conductive materials are needed to satisfy many operational requirements. 
     Chip carriers of non-ceramic material have been proposed, but these typically possess various drawbacks. In U.S. Pat. No. 5,574,630, for example, three chips are mounted on a substrate comprised of silica-filled polytetrafluoroethylene (PTFE) but require individual vias to pass through the carrier&#39;s entire thickness to connect to desired connections on the opposite side. Additionally, this structure in turn mandates utilization of a complex “power/ground assembly” of several layers having specific CTEs and other properties, thus resulting in a very expensive final assembly and one that is relatively difficult to construct. 
     Yet another non-ceramic substrate embodiment for having more than one chip thereon is described in U.S. Pat. No. 6,246,010. Unfortunately, the substrates described herein require semiconductor chips which are extremely thin (less than 100 μm, preferably less than 50 μm, and “most preferably” less than 20 μm). Understandably, such thinned chips are incapable of adequately providing the much greater operational capabilities as required by today&#39;s more powerful chips (e.g., those of the application specific integrated circuit (ASIC) variety). Typically, such chips operate at much higher temperatures than other types (e.g., those of the dynamic random access memory (DRAM) variety). 
     In grandparent pending application Ser. No. 10/354,000, cited above, there is defined a PCB which is capable of providing high speed interconnections between two or more components such as chips or modules (chip carriers) mounted thereon. This PCB is specifically designed to accommodate the increased operational requirements for electronic structures such as electronic modules which mount on the PCBs and are coupled together through the board&#39;s circuitry. One particular increase that this PCB accommodates is the need for higher frequency connections between the mounted components, which connections, as stated, occur through the underlying host PCB. Such connections are subjected to the detrimental effects, e.g., signal deterioration, caused by the inherent characteristics of such known PCB wiring. For example, signal deterioration is expressed in terms of either the “rise time” or the “fall time” of the signal&#39;s response to a step change. The deterioration of the signal can be quantified with the formula (Z 0 *C)/2, where Z 0  is the transmission line characteristic impedance, and C is the amount of the via capacitance. In a wire having a typical 50 ohm transmission line impedance, a plated through hole via having a capacitance of 4 pico farad (pf) would represent a 100 pico-second (ps) rise-time (or fall time) degradation, as compared to a 12.5 ps degradation with a 0.5 pf buried via of the present invention, as discussed below. This difference is significant in systems operation at 800 MHz or faster, where there are associated signal transition rates of 200 ps or faster. 
     A typical high performance PCB, prior to the ones defined in Ser. No. 10/354,000 and Ser. No. 10/394,107, has not been able to provide wiring densities beyond a certain point due to limitations imposed by the direct current (DC) resistance maximum in connections between components (especially chips). Similarly, high speed signals demand wider lines than normal PCB lines to minimize the “skin effect” losses in long lines. To produce a PCB with all wide lines would be impractical, primarily because of the resulting excessive thickness needed for the final board. Such increased thicknesses are obviously unacceptable from a design standpoint. 
     Various PCBs are described in the following documents: 
     
       
         
           
               
             
               
                   
               
             
            
               
                 U.S. Patents 
               
            
           
           
               
               
               
               
            
               
                   
                 4,902,610 
                 Febraury 1990 
                 C. Shipley 
               
               
                   
                 5,336,855 
                 September 1994 
                 J. Kahlert et al 
               
               
                   
                 5,418,690 
                 May 1995 
                 R. Conn et al 
               
               
                   
                 5,768,109 
                 June 1998 
                 J. Gulick et al 
               
               
                   
                 5,891,869 
                 April 1999 
                 S. Lociuro et al 
               
               
                   
                 5,894,517 
                 April 1999 
                 J. Hutchison et al 
               
               
                   
                 6,023,211 
                 Febraury 2000 
                 J. Somei 
               
               
                   
                 6,075,423 
                 June 2000 
                 G. Saunders 
               
               
                   
                 6,081,430 
                 June 2000 
                 G. La Rue 
               
               
                   
                 6,146,202 
                 November 2000 
                 S. Ramey et al 
               
               
                   
                 6,222,740 
                 April 2001 
                 K. Bovensiepen et al 
               
               
                   
                 6,431,914 
                 August 2002 
                 T. Billman 
               
               
                   
                 6,495,772 
                 December 2002 
                 D. Anstrom et al 
               
               
                   
                 US2002/0125967 
                 September 2002 
                 R. Garrett et al 
               
            
           
           
               
            
               
                 Foreign Patent Document 
               
            
           
           
               
               
               
               
            
               
                   
                 JP4025155A2 
                 January 1992 
                 O. Takashi 
               
               
                   
                   
               
            
           
         
       
     
     The teachings of these documents are incorporated herein by reference. 
     The unique characteristics of the PCBs in Ser. No. 10/354,000 and Ser. No. 10/394,107 allow it to be able to assure high frequency connections while still utilizing relatively standard PCB manufacturing processes to produce the final structure. In these pending applications, incorporated herein by reference, a portion of the PCB is dedicated to utilizing relatively wider lines than the remaining, lower portion of the PCB, which includes lines and spacings known in the PCB field. 
     The use of such a structure or the like or a similar substrate of a material other than ceramic or not possessing the severe drawbacks of previous non-ceramic materials as mentioned above and which is capable of providing high speed or other effective coupling between two or more chips (especially high temperature chips such as ASIC chips) on one surface thereof as defined herein, yet which can then be directly electrically coupled to a second underlying substrate such as a typical PCB to also couple said chips to the PCB&#39;s circuitry, is believed to constitute a significant advancement in the art. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     It is, therefore, a primary object of the present invention to enhance the art of chip carriers including more than one chip as part thereof, known in the ceramic substrate art also as multi-chip electronic packages (or modules). 
     It is another object of the invention to provide such a package which assures high speed connections between the chips thereon, while attaining effective electrical coupling with the underlying circuitized substrate (e.g., PCB) on which one or more of the carriers of the invention may be mounted. 
     It is a further object of the invention to provide such a package which is capable of providing such connections for high temperature chips such as those of the ASIC variety, while assuring a minimum of substrate upper surface area is utilized. 
     It is still another object of the invention to provide such a package which can be produced in a cost effective manner while assuring a final structure of robust construction. 
     Further, it is another object of the invention to provide a package-substrate assembly utilizing the package of the invention as part thereof, the assembly thus benefiting from the unique advantages of the multi-chip carrier defined herein. 
     Finally, it is an object of the invention to provide a method of making an electronic package including a chip carrier and plurality of chips mounted on one surface thereof, which method can be completed in a facile and relatively inexpensive manner, thus resulting in a final end product of reduced cost. 
     According to one aspect of the invention, there is provided a multi-chip electronic package comprising an organic, laminate chip carrier including a plurality of electrically conductive planes spacedly positioned therein and separated by respective layers of dielectric material, the chip carrier including a plurality of electrical contacts on a first surface thereof and a plurality of electrical conductors on a second surface thereof, selected ones of the electrical contacts being electrically coupled to selected ones of the electrical conductors, and first and second semiconductor chips positioned on the first surface of said organic, laminate chip carrier in a stacked orientation, each semiconductor chip electrically coupled to selected ones of the electrical contacts. 
     According to another aspect of the invention, there is provided a method of making a multi-chip package wherein the method comprises the steps of providing an organic, laminate chip carrier having first and second surfaces and including a plurality of electrically conductive planes spacedly positioned therein and separated by respective layers of dielectric material, providing a plurality of electrical contacts on the first surface of the organic, laminate chip carrier, providing a plurality of electrical conductors on the second surface of the organic, laminate chip carrier, selected ones of the electrical contacts being electrically coupled to selected ones of the electrical conductors, and positioning first and second semiconductor chips on the first surface of the organic, laminate chip carrier in a stacked orientation and electronically coupling the first and second semiconductor chips to the selected ones of the electrical contacts. 
     According to a third aspect of the invention, there is provided an electronic package assembly which includes a circuitized substrate including a plurality of electrically conductive members thereon, an organic laminate chip carrier including a plurality of electrically conductive planes spacedly positioned therein and separated by respective layers of dielectric material, the chip carrier including a plurality of electrical contacts on a first surface thereof and a plurality of electrical conductors on a second surface thereof, selected ones of the electrical contacts being electrically coupled to selected ones of the electrical conductors, first and second semiconductor chips spacedly positioned on the first surface of the organic, laminate chip carrier in a stacked orientation and electrically coupled to selected ones of the electrical contacts, and a plurality of electrically conductive elements electrically connecting the selected ones of the electrical conductors on the second surface of the organic, laminate chip carrier to respective ones of the electrically conductive members on the circuitized substrate. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a side-elevational view, partly in section, illustrating the multi-chip electronic package of Ser. No. 10/394,107; 
         FIG. 2  is a side-elevational view of the package of  FIG. 1  further including a quantity of encapsulant and a cover member thereon; 
         FIG. 3  is an alternative embodiment of the package of  FIG. 1 , illustrating the use of a stiffener member and cover and heat sinking member as part thereof; 
         FIG. 4  is a side-elevational view illustrating an alternative embodiment of the package of Ser. No. 10/394,107; 
         FIG. 5  is a perspective view of an information handling system adapted for using one or more of the multi-chip electronic packages of the instant invention and/or the complete assemblies (including an underlying PCB) therein; 
         FIG. 6  is a side-elevational view, in section, of one portion of an organic, laminate chip carrier which, when combined with at least one other portion, may be used as the chip carrier for the instant invention; 
         FIG. 7  is a side-elevational view, in section, of another portion of a laminate chip carrier; 
         FIG. 8  is an assembled, elevational view, in section, illustrating an organic, laminate chip carrier which can be used in the instant invention; 
         FIG. 9  is another embodiment of an organic, laminate chip carrier which may be used in the instant invention; 
         FIG. 10  represents another aspect of a multilayered laminate chip carrier capable of being used in the instant invention; 
         FIG. 11  represents a side-elevational view, in section, of yet another embodiment of an organic chip carrier usable in the present invention; 
         FIG. 12  is a top plan view of a circuit pattern that may be used on the organic, laminate chip carrier of the present invention; 
         FIG. 13  is a side-elevational view, as taken along the line  8 — 8  in  FIG. 12 . It is understood that the embodiment of  FIG. 13  represents only a portion of the organic, laminate chip carrier capable of being used in the present invention. 
         FIG. 14  is an enlarged, side elevational view, partly in section, of an electronic package according to one embodiment of the invention; and 
         FIG. 15  is a much enlarged, partial side elevational view of a stacked chip arrangement according to an alternative embodiment of the invention. 
     
    
    
     BEST MODE FOR CARRYING OUT THE INVENTION 
     For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in connection with the above-described drawings. It is understood that like numerals will be used to indicate like elements from FIG. to FIG. 
     As stated above, the term “high speed” as used herein is meant signals of high frequency. Examples of such signal frequencies attainable for the multilayered chip carriers and circuitized substrates (e.g., PCBs) defined herein and as produced using the methods taught herein include those within the range of from about 3.0 to about 10.0 gigabits per second (GPS). These examples are not meant to limit this invention, however, because frequencies outside this range, including those higher, are attainable. As further understood from the following, the carrier products produced herein may be formed of at least two separate multilayered portions (subassemblies) which have themselves been formed prior to bonding to each other. At a minimum, each of these separate portions will include at least one dielectric layer and one conductive layer, with most likely embodiments including several layers of each as part thereof. Examples are provided below and are just that (only examples) and the numbers of layers shown and described are not meant to limit the scope of this invention. 
     The products as defined herein are particularly adapted for use in what can be termed “information handling systems”. By the term “information handling system” as used herein shall mean any instrumentality or aggregate of instrumentalities primarily designed to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, measure, detect, record, reproduce, handle or utilize any form of information, intelligence or data for business, scientific, control or other purposes. Examples include personal computers and larger processors such as servers, mainframes, etc. An example is shown in  FIG. 5 , as a server, and is seen to include at least one multi-chip package and a circuitized substrate having the package mounted thereon within the server&#39;s housing. 
     In  FIG. 1 , there is shown the multi-chip electronic package  1  of Ser. No. 10/394,107, the package comprising an organic, laminate chip carrier  2  and a plurality of semiconductor chips  3  located on the carrier. Organic, laminate chip carrier  2 , which can function as the carrier for the present invention, includes a plurality of conductive planes  4  spacedly positioned within the carrier and separated by respective layers of dielectric material  5 . Carrier  2  further includes a plurality of electrical contacts  6  (one shown) on the carrier&#39;s upper surface, each contact in turn designed for being electrically coupled to a respective conductive member (e.g., a solder ball  7 ) which in turn couples the contact to a corresponding contact site (not shown) on the undersurface of chip  3 . Such chip sites are well known and further description is not believed necessary. Each of the chips  3  is coupled through the internal circuitry of carrier  2  to respective ones of electrical conductors  8  (only one shown) which in turn are capable of being electrically coupled (i.e., utilizing a plurality of solder balls  9  to respective contact sites (not shown) on an underlying circuitized substrate  10 , a primary example being a multi-layered PCB. Chips  3 , using the circuitry on the upper surface of carrier  2  and possibly portions thereof within the carrier, may be electrically coupled to one another depending on the operational requirements for the final product. As further seen in  FIG. 1 , the individual contacts  6  do not necessarily directly couple to a respective conductor by a linear (here, vertical) connection such as a plated through hole extending from the top of the carrier through the entire thickness thereof. This carrier, in such simplified form, may comprise the carrier for the present invention. 
     In  FIG. 1 , both chips, unlike those of the present invention, occupy a substantially coplanar orientation on the upper surface of carrier  2  and are spaced apart from one another. In one example, each chip may possess length and width dimensions of about 10 mils and 20 mils, respectively, and may be coupled to the carrier using a plurality of solder balls  7  having a number within the range of from about 1,000 to about 3,000. It is understood that the carrier of  FIG. 1 , and the one of the present invention, is not limited to these dimensions or numbers and that others are readily acceptable. Each chip for the  FIG. 1  (Ser. No. 10/394,107) may be an ASIC chip or other type, depending on product operational requirements. 
     In one embodiment, carrier  2  includes an upper, high-speed portion  11  and a lower portion  12  in which signals pass at lower frequencies. A more specific example of this particular construction will be defined hereinbelow. The dielectric material for carrier  2  may be selected from a variety of known PCB dielectric materials, including known fiberglass-reinforced epoxy resin, Driclad (a registered trademark of the assignee of this invention), PTFE, Nelco 6000SI, Rogers 4300, Polyclad LD621 (see below), etc. Therefore, it does not necessarily need to be comprised of PTFE. It is also possible that carrier  2 , if used in the present invention ( FIGS. 13 and 14 ), may include a thermally conductive member  13  therein. If so utilized, the thermally conductive member  13  may be comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections provided by solder balls  7  and  9 . Thermally conductive member  13  can be a suitable metal comprised of nickel, copper, molybdenum, or iron. Preferably, the thermally conductive layer also functions as a ground plane. The preferred thermally conductive member (which has a CTE of close to zero) is a three layered structure comprised of a first, outer layer of copper, a second, interim layer of an alloy of about 34% to about 38% nickel (preferably about 36% nickel) and about 62% to about 66% iron (preferably about 63% iron), and a third, outer layer of copper. The overall CTE of thermally conductive member  13  is from about 4 to about 8 ppm/° C. Preferably, about 72% to about 80% of the thickness of the thermally conductive layer is the nickel-iron alloy and about 20% to about 28% of the thickness of the thermally conductive layer is copper. A suitable 36% nickel-63% iron alloy is available from Texas Instruments Incorporated (Attleboro, Mass.). Alternatively, the thermally conductive member can be formed solely of a single metal alloy such as about 36% nickel-about 63% iron alloy. The thickness of the thermally conductive member is preferably from only about 1 mil to about 3 mils. The thickness and choice of material for the member will determine the CTE of the member and, significantly, can be used to control the CTE of the multi-layered chip carrier when used in combination with the other elements defined herein. When the overall CTE of the multi-layered interconnect structure is controlled to a value of about 10 to about 12 ppm/° C., a significant advantage is achieved. Strain control on the solder connections is realized and localized regions of high strain are avoided during operation of the package (when assembled to a circuitized substrate and in field operation), an important feature if two or more chips are used and in close proximity to one another. The overall strain between the semiconductor chips  12 , with a CTE of about 2–3 ppm/° C., and the circuitized substrate, with a CTE of about 17–20 ppm/° C., is thus significantly reduced in magnitude. Further description of this member is provided in U.S. Pat. No. 6,351,393, incorporated herein by reference. Carrier  2  is thus an excellent component for use with the present invention. 
     Chip carrier  2  may also include an internal capacitor structure therein, such as described in U.S. Pat. No. 6,370,012, also incorporated herein by reference. As defined therein, the capacitor structure is a parallel capacitor suitable for use in chip carriers or the like designed for being positioned on an underlying substrate such as a PCB. In the structure of U.S. Pat. No. 6,370,012, the capacitor preferably includes at least one internal conductive layer, two additional conductor layers added on opposite sides of the internal conductor and inorganic dielectric material (preferably an oxide layer) on the second conductor layer&#39;s outer surfaces. Alternatively, a suitable dielectric material such as berium titanate applied to the second conductive layer may be utilized. Further, the capacitor in this cited patent includes outer conductor layers atop the inorganic dielectric material to thus form a parallel capacitor between the internal and added conductive layers and the outer conductors. Further description is found in U.S. Pat. No. 6,370,012. 
     In  FIG. 2 , the package  1  of  FIG. 1  is shown to further include a quantity of encapsulant material  14  (in phantom) which lies on the upper surface of carrier  2  and substantially surrounds the semiconductor chips  3 , including the underlying solder ball connections  7 . Such encapsulant can be used in the present invention shown in  FIGS. 14 and 15 . Encapsulant materials are known in the packaging art and further description is not believed necessary. Suitable examples can be found in one more of the documents cited hereinabove. Package  1  in  FIG. 2  is also shown to include a heat sinking cover member  15  (also in phantom) which lies atop the formed encapsulant and in thermal contact with the upper surfaces of the semiconductor chips  3 . Member  15 , also usable in the present invention, thus serves to facilitate heat removal from the chips during operation thereof. In one example, cover member  15  is preferably of copper, but may also be aluminum or other sound, thermally conductive material. 
     In  FIG. 3 , package  11  is shown as including a stiffener member  16  (in phantom) which rests atop the upper surface of carrier  2  and substantially surrounds the spacedly positioned chips and is also spaced therefrom. The stiffener member further includes a heat-sinking cover member  17  (in phantom) located on an upper surface thereof and a heat-sinking member  18 , in phantom, located thereon. Stiffener  16  is preferably of stainless steel material while heat-sinking cover member  17  is preferably copper or aluminum and the heat-sinking member  18  preferably aluminum and including a plurality of upward projections as shown in  FIG. 3 . The heat-sinking cover member  17  is designed for receiving heat from chips  3  to in turn pass the heat through to the larger heat-sinking member  18  to thus facilitate thermal removal from package  11  during operation thereof. This arrangement, like encapsulant  14 , is also usable in the present invention of  FIGS. 14 and 15 . 
     The above heat-sinking components serve to effectively remove the relatively high heat as produced by powerful chips such as those of the ASIC variety, as described above. The additional use of the internal thermally conductive member further assures an effective operating product which will not disrupt or result in damage to the relatively delicate solder connections formed both between the chip and carrier and, if utilized, between the carrier and underlying substrate. 
     In  FIG. 4  there is shown an alternative embodiment of an electronic package  1 ′ defined in Ser. No. 10/394,107. Package  1 ′ includes a carrier  2  similar to that described above and preferably utilizes solder elements  9  or the like to couple the carrier to the underlying substrate  10 . Package  1 ′ differs from package  1  in  FIGS. 1–4 , however, by the utilization of substantially vertically oriented chips  3 ′ (unlike those taught in  FIGS. 14 and 15 ) which are preferably electrically coupled to respective contacts  6  on the carrier&#39;s upper surface by respective solder balls  7 ′. Chips  3 ′ are also preferably oriented substantially parallel to one another and, as understood, possess a width (or length) dimension extending into the page from the viewer&#39;s viewpoint. These chips may include surface contact sites similar to those in  FIG. 1  with appropriate circuitry extending to the outer (lower) edge thereof such that connections using solder balls  7 ′ can occur. Chip carrier  2 , like that in  FIGS. 1–4 , may also include an internal thermally conductive member (not shown) and/or capacitor (not shown) as described hereinabove. 
     The embodiment of  FIG. 4  may also include encapsulant material and a heat-sinking cover member such as shown in  FIG. 2 , or, alternatively, a stiffener, heat-sinking cover and heat-sink member as shown in  FIG. 3 . Further description is thus not believed necessary. 
     In  FIG. 5 , there is shown an information handling system  19  in which the subject invention of  FIGS. 14 and 15  may be utilized. By way of example, system  19  may be a server (as shown), a personal computer, mainframe or similar information handling system known in the art. It is well-known in the information handling systems art that these structures include circuit boards and electronic packages as part thereof. In the instant invention, system  19  is shown to include a circuitized substrate  10  (in phantom) having the multi-chip electronic package  101  of  FIG. 14  (or  FIG. 15 ) thereon. The positioning relationship of the substrate and package is for illustration purposes only in that this assembly can also be located at other locations within system  19 , including substantially perpendicular to the orientation shown. It is also understood that several such assemblies may be utilized in such a system, depending on the operational requirements thereof. If the system is a computer, server, mainframe or the like, it will include a central processing unit (CPU), one or more input/output (I/O) devices, and one or more random access storage devices. It may also include various peripheral devices functionally operable therewith, including keyboards, mice, displays, printers, speakers and modems. The components, including positioning thereof within or in operational relationship to a computer, server, mainframe, etc., are well known in the art and further description not deemed necessary. 
     In  FIGS. 6 and 7 , there are shown two embodiments of multilayered portions  20  and  20 ′, usable in the substrate of the invention. Portions  20  and  20 ′, when bonded to another multilayered portion, may form the chip carrier according to one embodiment of the invention. Accordingly, portions  20  and  20 ′ will be defined herein as second portions while the other portion will be referred to as the first (or base) portion. It is to be understood that in accordance with the broad aspects of this invention, at least one second portion is to be bonded to at least one first portion such that this second portion lies substantially along the external portions of the final carrier product. It is also understood that one or more of such second portions may be bonded to the base, first portion, including on opposite sides thereof such as depicted in  FIGS. 8–11 . Most significantly, the second portions as defined herein are specifically designed for providing high frequency (high speed) connections between semiconductor chips mounted (e.g., soldered) to the second portions and/or otherwise electrically coupled thereto. Importantly, the first or base portion will not necessarily require such capability but instead can be formed in the regular manner for most current PCBs, many of which are described in the above-listed documents. This thus allows the utilization of known PCB manufacturing techniques to produce a resulting chip carrier with significantly increased capability such that chips secured thereto can be connected at higher speeds than heretofore attainable. Such connections are considered essential in the rapidly expanding packaging art, due primarily to the corresponding increased requirements of such components. The present invention as defined herein thus provides a significant advancement in the art. 
     In  FIG. 6 , multilayered portion  20  is shown as including a central conducting plane  21  which, in a preferred embodiment, serves as a power plane. Plane  21  is surrounded by two layers of dielectric material  23 , shown in the drawing as one continuous structure due to the bonding (lamination) of both layers onto plane  21 . On the external surfaces of dielectric material  23  are located additional conductive planes  25  and  27 , which in a preferred embodiment of the invention (if portion  20  is to be used) comprise a series of signal lines. Portion  20  can thus be simply referred to as a 2S1P structure, meaning it comprises two signal planes and one power plane. A conductive through hole  29  is also provided to connect the upper signal plane  25  with lower plane  27 . In a preferred embodiment, the conductive through hole is a plated through hole (PTH), produced using known technologies. The formation of portion  20  is accomplished using known PCB procedures, including lamination of the aforementioned dielectric layers and deposition (e.g., plating) of the external signal planes. Further process description is thus not believed necessary. 
     As mentioned, portion  20  is designed for providing high speed (high frequency) connections between chips located on the upper surface of the carrier&#39;s substrate and coupled thereto when portion  20  is formed in combination with another multilayered portion to form a final carrier. In order to provide such high speed connections, therefore, the individual signal lines in portion  20  (and  20 ′) preferably possess a width of from about 0.005 inch to about 0.010 inch and a thickness of 0.0010 to about 0.0020 inch. The corresponding dielectric layers each possess a thickness of from about 0.008 inch to about 0.010 inch. The material for planes  21 ,  25  and  27  is preferably copper, but other conductive materials are possible. The preferred dielectric material  23  is a low loss dielectric, one example being Polyclad LD621, available from Cookson Electronics, located in West Franklin, N.H. Additional materials include Nelco 6000SI, available from Park Nelco, located in Newburgh, N.Y. and Rogers 4300, available from Rogers Corporation, located in Rogers, Conn. These materials have a low dielectric constant and loss factor to provide the optimum operational capabilities for the structure. Other materials possessing dielectric loss ≦0.01, and preferably less than &lt;0.005 would be suitable for use in both portions  20  and  20 ′. Again, this dielectric material need not be PTFE. 
     It is understood that the above thicknesses and defined materials are not meant to limit the scope of this invention, in that others are possible while attaining the desired results taught herein. It is also understood that the second portion of this structure, if used, can include the aforedefined thermally conductive member and/or internal capacitor structure therein. In one example, using the aforementioned thicknesses, widths and materials, it was possible to provide a second portion  20  (and  20 ′) capable of passing signals at a signal frequency within the range of from about 3 to about 10 GPS. This is also not meant to limit the invention in that higher frequencies, e.g., 12 GPS, are possible with relatively insignificant modification to one or more of the above materials, parameters, etc. The resulting overall thickness for portion  20  as defined, according to one embodiment, is about 0.140 inch. 
     Although it is not a necessary requirement, the aforementioned widths and thicknesses for the conductive planes and dielectric layers will normally be thicker than those for the base or first multilayered portion to which portions  20  and  20 ′ will be bonded. That is, the base portions will typically include much less thickness and width dimensions for the conductive planes and dielectrics used therein, such widths, thicknesses and materials being typical of those of known PCB structures used today. Thus, further description will not be necessary. 
       FIG. 8  illustrates an embodiment of a chip carrier  30 , also usable in the present invention, in which two second portions  20  are utilized, each of these portions located on opposite sides of a common first multilayered portion  31 . First portion  31  is illustrated, for simplification purposes, as a singular dielectric layer including outer conductive layers  33  and  35  thereon. In one embodiment, layers  33  and  35  are power or ground planes, depending on the operational requirements of the final board  30 . In a preferred embodiment, portion  31  will include several (e.g., twenty) conductive planes therein of mixed signal and ground and/or power capabilities and a corresponding plurality (e.g., nineteen) of dielectric layers. In its simplest form, portion  31  (and  31 ′ in  FIGS. 9–11 ) will include at least one signal plane passing signals therealong at a first frequency. As indicated earlier, both conductive planes and dielectric layers used in the first multilayered portion  31  are typically those utilized in a conventional PCB. Therefore, in one example, portion  31  may include conductive signal lines having widths of about 0.003 inch to about 0.010 inch and corresponding thicknesses of 0.0005 inch. The dielectric layers each include an initial thickness of about 0.010 inch. First portion  31 , being of such multilayered construction, is laminated together to bond the several conductive dielectric layers to form the first portion  31 . Additionally, second portions  20  are similarly formed as separate, multilayered subassemblies as described above. In the next step, a dielectric layer  41  (e.g., conventional pre-preg or thermoplastic material) is added to opposite sides of the interim first portion  31  and another dielectric layer  43  is added to each of the outermost surfaces of portions  20 . This structure is now laminated to form a singular, multilayered organic chip carrier, using standard lamination processing, for use in the present invention. Because of the structural characteristics explained above and herein, at least some of the signal planes in second portions  20  and  20 ′ will provide higher frequency signal passage than at least some of the signal lines in the conventional first portions  31  and  31 ′. In a preferred embodiment, all signal lines in the external portions will possess such superior capabilities compared to the signal layers of the first portions these are bonded to. 
     To access one or more of the outer conductive planes on each portion  20 , openings  45  are provided within the outer dielectric layers  43 . This is preferably done by laser or photoprinting operations known in the art. Following removal of the dielectric material, an outer conductive layer  51  is added on opposite sides of the structure in  FIG. 8 , including within the openings in the dielectric. At this point, connections for components are provided on carrier  30  that couple to the signal lines of portions  20  which in turn will assure high speed signal passage along these signal lines, including those on the upper and lower surfaces of each portion  20 , to the second chip (not shown in  FIG. 8 ) also coupled to the circuitry of the same portion  20 , e.g., at a site to the left of the viewer in  FIG. 8 . Such connection would also be provided through an opening in conductive material  51  as shown in  FIG. 8 . 
     It is understood in  FIG. 8  that two or more semiconductor chips, as shown in  FIGS. 14 and 15 , can be mounted on each of the opposite sides of carrier  30  and coupled together with high frequency signals, should the carrier include a modified lower surface or other means to couple it to PCB  10  (i.e.,  FIG. 1 ). The carrier of the present invention is thus able to uniquely couple two or more chips on opposite surfaces thereof to assure a finished chip carrier assembly possessing far greater operational capabilities than heretofore known in the art. (In a typical embodiment, however, carrier  30  will only include one upper high speed portion and one lower speed portion, the latter including bottom conductors such as shown in  FIG. 14 .) 
     For additional coupling, another layer of dielectric material  55  may also be added to cover the conductive planes  51 , in which case, connection to the conductive material  51  within opening  45  would be accomplished by a similar opening and conductive material  61  in  FIG. 8  to electrically couple chips on one side of carrier  30 . A plated through hole (PTH)  71  may be utilized to extend through the entire thickness of carrier  30 , as illustrated to the right in  FIG. 8 . Such a through hole could be formed using conventional techniques and would include, e.g., a thin plated layer of conductive material (e.g., copper) on the surfaces thereof. This through hole may also be used to accept a conductive pin or the like if such an added component is desired. PTH  71  can also couple one or more components to internal conductive planes in the carrier&#39;s base or first portion  31 . 
     In  FIG. 8 , the single semiconductor chip shown coupled to the conductive material  61  (or, alternatively, directly to material  51  should material  61  not be utilized) is represented by the numeral  77  and the connecting solder ball by the numeral  79  (not  7  as in  FIG. 1 ). 
     Returning to  FIG. 7 , the portion  20 ′ includes similar components to those of portion  20  in  FIG. 6  but represents an alternative embodiment for forming a multilayered carrier using the teachings herein. Portion  20 ′ includes as part thereof the 2S1P portion  20  therein. Dielectric layers  81  are added on opposite surfaces of portion  20 , following which conductive layers  83  are then applied, e.g., via plating. The conductive layers  83  are preferably ground or power planes and are coupled together by a plated through hole  85  as shown. Like portion  20 , several such through holes are utilized in the second portions to provide such connections. Only one is shown in both  FIGS. 6 and 7  for illustration purposes. Dielectric layers  81  are preferably of similar material as the low loss dielectric layers used in portion  20 . The layers of portion  20 ′, like portion  20 , are assembled using conventional lamination processing. 
     In  FIG. 9 , two second portions  20 ′ are shown bonded to a common, interim multilayered first portion  31 ′ which, in one embodiment and as stated above, includes several internal conductive planes (not shown) bonded by a corresponding number of individual dielectric layers (also not shown). The embodiment of  FIG. 7  thus represents a simpler means of producing a final carrier ( 30 ′ in  FIG. 9 ) because of the fewer lamination steps necessary during the final bonding operations. That is, it is only necessary to laminate the three previously formed multilayered structures  20 ′ and  31 ′ shown in  FIG. 9 . Again, it is noteworthy, and, most likely, that only one outer portion  20 ′ will be bonded to an underlying conventional portion  31 ′ in accordance with the teachings herein. Following complete lamination, an outer dielectric layer  55 ′ may be added to the structure and a conductive opening  51 ′ provided therein using similar techniques to those defined for providing the opening  45  and conductive material  51  in  FIG. 8 . A plated through hole  85  will couple any chip joined to material  51 ′ to the top and/or bottom layers of portion  20 ′, if desired. To couple the outermost surfaces of carrier  30 ′, a common through hole  71 ′ is provided, similarly to through hole  71  in  FIG. 8 . Such a through hole would preferably include the plated conductive material  73 ′ similar to that in  FIG. 8 . 
     Of further significance, the through holes  71  and  71 ′ can be used to electrically couple one or more of the chips to the internal wiring of the first multilayered portions  31  and  31 ′, respectively, thus providing a direct electrical connection between these components and the interim structure. Thus, the carrier defined herein may provide the unique capability of assuring coupling between chips on one side of the carrier in addition to coupling of these same chips to internal conductive planes of the base or first portion of the carrier&#39;s overall structure. Such dual coupling represents a significant aspect of the invention because it results in a final carrier product having greater operational capabilities than heretofore known products. 
     In  FIGS. 10 and 11 , there are shown two alternative carrier embodiments  30 ″ and  30 ′″, respectively, that can be used in the present invention. The structure of carrier  30 ″ in  FIG. 10  is similar to that shown in  FIG. 9  with the addition of a conductive through hole  91  extending from an outer surface of the carrier to one of the conductive planes of portion  20 ′. Coupling of a pinned component (i.e., the pin  93  shown in  FIGS. 10 and 11 ) is thus also possible, in addition to the aforedefined coupling of additional electronic components. In the embodiment of  FIG. 11 , an elongated opening  95  is provided through the portion  31 ′ (and the lower portion  20 ′, if used). The reason for providing opening  95  is to provide proper clearance for inserting pin  93 . Opening  95  can be preformed (drilled) on  31 ′ and  20 ′ (if used) before final lamination, contrasting to the conventional method of “back drilling” in order to eliminate the unused portion of the PTH. Back drilling removes a portion of the PTH layer of copper. This reduces the capacitive effects of the PTH when dealing with high speed signals. Back drilling is expensive and difficult to perform. The construction provided negates the need for back drilling and achieves the same effects. 
       FIGS. 12 and 13  represent another embodiment of a second portion  20 ″ which can be used in the carrier of the invention. Understandably,  FIG. 13  is a sectional view taken along the line  8 — 8  in  FIG. 12  and serves to illustrate one embodiment of the respective widths of conductors on the upper surface of portion  20 ″. The through holes located at respective ends of the broader width conductors are also shown. In this arrangement, the broader width conductors  101  serve as signal lines to interconnect plated through holes  103  at the opposite ends thereof. In comparison, the narrower width signal lines  105  extend in paired relationship between the respective outer pairs of the wider lines  101 . In one embodiment, lines  101  may possess a width of from about 0.003 inch to about 0.010 inch while the corresponding internal, narrower lines each may possess a width of 0.02 inch to about 0.10. These lines were spaced apart a distance of from about 0.03 inch to about 0.10 inch. The purpose of providing the greater width lines  101  on opposite sides of the paired narrower signal lines  105  is to provide proper trace impedance control as well as signal shielding to minimize noise coupling amongst signal lines. As seen in  FIG. 13 , these lines are positioned on opposite sides of portion  20 ″, with the narrower lines  105  located externally of an interim conductive (e.g., power) plane  106  coupled to the center PTH  103 . This arrangement provides the advantageous feature of a continuous reference plane that can provide maximum signal shielding. This provides for simpler construction of subcomposites and also allows for sections with Z connections that can have different dielectric thicknesses; for example, fast signals vs. slower signals. Although such a pattern is shown, however, it is understood that in a preferred embodiment of the invention, each of the solder balls  79  ( FIG. 14 ) will be coupled to a singular contact arranged in a pattern similar to the pattern of the balls immediately under the chip. The above pattern may be used to interconnect respective balls on one chip to another chip, when the chips are oriented in the specific orientation according to preferred embodiments of the invention (see more below). 
     In  FIG. 14 , there is shown a multi-chip electronic package  111  according to one embodiment of the invention. Package  111  includes an organic, laminate chip carrier  300  including therein a plurality of electrically conductive planes spacedly positioned and separated by respective layers of dielectric material, similar to the structures defined hereinabove. Carrier  300  may also include the aforementioned thermally conductive member  13  substantially essentially positioned therein, in addition to a plurality of conductive plated through holes  71 ″ for connecting respective opposed layers of conductors, e.g., signal planes. Conductive material  61  is also utilized within provided openings located within the upper outer surface layer of the carrier and, if desired, also within the lower, opposing outer surface area to connect the relatively large solder ball conductors  99  which, as shown, electrically couple the package to the lower circuitized substrate PCB  10 . The use of internal conductive planes and separating dielectric layers is described in detail above and further description is not believed necessary. The cross-sectional configuration depicted in  FIG. 14  is representative of one embodiment of such a cross-section and may differ from that described in the foregoing illustrations, while still usable in the present invention. 
     Package  111  differs significantly from those described above, however, through the unique positioning of a pair of semiconductor chips in a stacked orientation on the upper surface of carrier  300 . In one example, a first, lower chip  77 ′ (preferably an ASIC chip) is electrically coupled to respective conductors on an upper surface of the carrier using a plurality of solder balls  79 . Additionally, a second chip  77 ″ (preferably a memory chip) is secured to the upper surface of chip  77 ′, preferably using either a suitable adhesive known in the industry or, in the example illustrated in  FIG. 15 , such an adhesive in combination with a plurality of smaller solder balls  79 ′. An appropriate encapsulant is shown substantially surrounding the solder balls  79  and  79 ′ as is known in the art. 
     Package  111  may also include additional, spaced semiconductor chips  77 ′ also electrically coupled to the carrier&#39;s upper surface (as shown) for providing additional operational capabilities for the instant invention. Each additional chip  77 ′ is also preferably an ASIC chip but the invention is not limited thereto as a memory chip (e.g., DRAM or SRAM) may be used. 
     Second chip  77 ″, secured to lower chip  77 ′, is electrically coupled to outer conductors on the carrier&#39;s upper surface using a plurality of wirebond connections  113 . Wirebond connections for coupling semiconductor chips are known and further description is not believed necessary. Of significance, however, is that the upper, second chip  77 ″ is wirebonded while in place atop the lower chip  77 ′. Thus, the lower chip is first electrically coupled using solder balls  79  to securely position it in place and form a second electrical connection with the desired electrical contacts on the carrier&#39;s upper surface. Thereafter, second chip  77 ″ is then adhesively bonded and, uniquely, wirebonded such that the second chip&#39;s contact sites  115  are coupled to the respective contacts using connections  113 . Finally, a quantity of encapsulant  14 ′ (shown in phantom) is then positioned over the stacked chip arrangement and serves to protect the arrangement in the manner described above for encapsulant  14  ( FIG. 2 ). 
     Although only one large solder ball  99  is shown for connecting package  111  to PCB  10 , it is understood that each of the solder balls  99  are similarly coupled to PCB  10 . 
     Thus, one or both of the semiconductor chips in the stacked arrangement may be coupled indirectly to PCB  10  in addition to also being coupled to one another, if desired. Still further, the stacked chip arrangement may be coupled to one or more of the adjacent chips  77 ′. The result is an electronic package having significant operating capabilities to uniquely couple several semiconductor chips to a common PCB. Although only four chips are depicted in  FIG. 14 , it is within the scope of the invention to utilize more than one pair of stacked chips on carrier  300  as well as more singular, separate chips  77 ′, depending on the operational requirements for package  111 . The invention is thus not limited to the particular number or orientation depicted in  FIG. 14 . Such a capabiloity is considered extgremely important, especially considering that the carrier is not of ceramic dielectric material. 
     The partial view in  FIG. 15 , as mentioned, illustrates an alternative positioning of the stacked chips on carrier  300  to thus represent a slightly different package  111 ′. The difference, as mentioned, involves the utilization of smaller solder balls  79 ′ to serve as thermal connections between both chips and also space chip  77 ′ from chip  77 ″ at a desired spacing. 
     Thus there has been shown and described a multi-chip electronic package which comprises an organic, laminate chip carrier and a pair of semiconductor chips positioned on a first surface thereof in a stacked orientation. There has also been shown and described an electronic package assembly which includes the aforementioned carrier and semiconductor chips in combination with a circuitized substrate (e.g., PCB) in which a plurality of electrically conductive elements (e.g., solder balls) are used to connect the chip carrier to the substrate. Significantly, the organic, laminate chip carrier of the invention is capable of having two or more semiconductor chips electrically coupled thereto which may be coupled together and/or coupled to electrical conductors on the undersurface (opposite side) of the carrier. Of further significance, these chips may be coupled in a high-speed manner so as to assure higher frequency signal passage therebetween, thus resulting in a final product structure possessing greater capabilities than heretofore known in the art. The invention is able to attain these capabilities using a carrier comprised substantially of organic laminate material such as described herein which, as defined herein, will not deform or otherwise be harmed as a result of the relatively high temperature operation of the semiconductor chips during package operation and positioning on the desired underlying circuitized substrate. The chip carrier may in turn thus be comprised of at least two portions formed in accordance with the teachings herein. Additionally, the carrier may include an internal capacitor structure such as defined and/or a thermally conductive member as part thereof designed to specifically prevent separation (disconnection) between the respective solder balls which form the connections between at least one of the chips and carrier and those, if utilized, between the undersurface of the carrier and the corresponding substrate. The invention as defined herein thus possesses many significant advantages over known chip carriers of the multi-chip variety, while utilizing a substantially organic laminate body as a main portion thereof. The method defined herein for assembling this structure can also be conducted using many known PCB procedures and thus at a relatively lower cost than other processes used to form carriers of this type, particularly those made primarily of ceramic material. 
     While there have been shown and described what are at present the preferred embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims.