Patent Publication Number: US-11645212-B2

Title: Dynamic processing speed

Description:
BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG.  1    is a block diagram illustrating a system having a dynamic processing speed. 
       FIG.  2    is an isometric illustration of rate controlled integrated circuit device stack. 
       FIG.  3    is an isometric illustration of a high-bandwidth memory (HBM) compatible rate controlled integrated circuit device stack. 
       FIG.  4    illustrates an example processing array. 
       FIG.  5    illustrates an example processing node of a processing element. 
       FIG.  6    illustrates an example distribution of memory bandwidth to processing elements. 
       FIG.  7    is a flowchart illustrating a method of operating a processing array. 
       FIG.  8    is a block diagram of a processing system. 
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     In an embodiment, an interconnected stack of one or more Dynamic Random Access Memory (DRAM) die has one or more processor die(s). The processor die may be attached and interconnected vertically with the DRAM die(s) by shared through-silicon via (TSV) connections that carry data and control signals throughout the stack. The processor die may include one or more arrays of processing elements. These processing elements may be designed and/or architected for the fast execution of, for example, general purpose computing, graphics rendering, signal processing, artificial intelligence, neural network, and/or machine learning tasks. 
     In an embodiment, the processing elements may include interfaces that allow direct access to memory banks on one or more DRAMs in the stack. These additional (e.g., per processing element) direct interfaces may allow the processing elements to have direct access to the data in the DRAM stack. This more direct access allows more rapid access to the data in the DRAM stack for tasks such as (but not limited to): rapidly loading weights to switch between neural network models, overflow for large neural network models, and rapidly storing and/or retrieving activations. 
     In an embodiment, based on the size/type of operands being processed, and the memory bandwidth of the direct interfaces, rate calculation circuitry on the processor die determines the speed each processing element and/or processing nodes within each processing element are operated. This helps prevent the processing nodes from spending time waiting for data to arrive via the direct interface thereby improving power efficiency. 
       FIG.  1    is a block diagram illustrating a system having a dynamic processing speed. In  FIG.  1   , processing system  100  includes processing element array  110 , memory  130 , and array control  160 . Array control  160  includes rate calculator  161 . Processing element array  110  includes processing elements  111 - 113 . Processing element array  110  is operatively coupled to memory  130  and array control  160 . Array control  160  is operatively coupled to processing element array  110  to, among other functions, control operations, data flows, processing speeds, and/or configurations of processing element array  110 . 
     In an embodiment, processing element array  110  may be arranged in a two-dimensional array. Each of the processing elements  111 - 113  of processing element array  110  includes or is coupled to memory  130 . The processing elements  111 - 113  of processing element array  110  may be intercoupled to the nearest neighbor processing elements  111 - 113 . Thus, a processing element  111 - 113  may be intercoupled to four adjacent processing elements  111 - 113 . This nearest neighbor intercoupling allows data to flow from processing element  111 - 113  to processing element  111 - 113  in the two directions (e.g., left or right, and toward the front or toward the back.) These dataflows are reconfigurable by array control  160  so that they may be optimized for the task (e.g., matrix multiplication) and/or workload (e.g., size of matrices.) Thus, for example, the data flows of the array may be configured into one or more loops or fabrics that flow data in order to accomplish different parts of a calculation. 
     In an embodiment, the processing elements  111 - 113  of processing element array  110  may be arranged are arranged in a three-dimensional array. Each of the processing elements  111 - 113  includes or is coupled to memory  130 . The processing elements  111 - 113  of processing element array  110  may be intercoupled to the nearest neighbor processing elements  111 - 113  in three dimensions. Thus, a processing element  111 - 113  on a first die may be intercoupled to a first processing element  111 - 113  on a second die that is located directly above the processing element  111 - 113 , a second processing element  111 - 113  on a third die that is located directly below the processing element  111 - 113 , and the four adjacent processing elements  111 - 113  on the first die. 
     This three-dimensional nearest neighbor intercoupling allows data to flow from processing element  111 - 113  to processing element  111 - 113  in the three directions (e.g., up or down, left or right, and toward the front or toward the back.) These dataflows are reconfigurable by array control  160  so that they may be optimized for the task (e.g., matrix multiplication) and/or workload (e.g., size of matrices.) Thus, for example, the data flows of the array may be configured into one or more loops that periodically recycle data in order to accomplish different parts of a calculation. 
     In an embodiment, based on information about the operands needed and results produced by processing elements  111 - 113  of processing element array  110 , array control  160  sets the operating rate of processing elements  111 - 113 . For example, processing elements  111 - 113  may have a maximum operating rate of 1 billion instructions per second (GIPS). Each instruction being executed may, for example, require one 32-bit operand be received from memory  130 . Thus, each of processing elements  111 - 113  would, if operated at 1 GIPS, require 4 GB/s of data be received from memory  130 . If, however, memory  130  can only supply 2 GB/s of data to each processing element  111 - 113 , the rate that processing elements  111 - 113  complete instructions will be limited to 0.5 GIPS by the supply of data from memory  130 . Thus, for this example, based on the information that each instruction being executed by processing elements  111 - 113  requires one 32-bit operand be received from memory  130 , and the information that memory  130  can supply a maximum of 2 GB/s of data to each processing element  111 - 113 , array control  160  would configure one or more clock signals to processing elements  111 - 113  of processing element array  110  such that processing elements  111 - 113  are operated at 0.5 GIPS. In this manner, the rate that processing elements  111 - 113  are operating (0.5 GIPS) more efficiently matches the maximum rate that memory  130  is supplying operands to processing elements  111 - 113 . 
     In an embodiment, the rate that operands, results, and/or instructions are communicated between (i.e., read or written) processing elements  111 - 113  of processing element array  110  and memory  130  may be limited by the bandwidth of memory  130 . For example, processing elements  111 - 113  may have a maximum operating rate of 1 billion instructions per second (GIPS). Each instruction being executed may, for example, require one 32-bit operand be received from memory  130 . Thus, each of processing elements  111 - 113  would, if operated at 1 GIPS, require 4 GB/s of data be received from memory  130 . If, however, memory  130  can only supply 2 GB/s of data to each processing element  111 - 113 , the rate that processing elements  111 - 113  complete instructions will be limited to 0.5 GIPS by the supply of data from memory  130 . 
     In an embodiment, array control  160  receives operand information via one or more indicators embedded in instructions to be processed by processing elements  111 - 113 . In another embodiment, a register or other indicator in array control  160  is set to provide operand information. In an embodiment, array control  160  includes a look-up table that relates operand information and memory  130  bandwidth to operating rates for processing elements  111 - 113 . In an embodiment, operand information comprises the data types to be (or are being) communicated with memory  130 . An example of this type of table is illustrated in Table 1. Additional tables may relate operand information from other sources (e.g., registers, SRAM, DRAM, flash, etc.) to operating rates for processing elements  111 - 113 . 
     
       
         
           
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 Input operand 
                 Memory 130 channel 
                 Memory 130 channel 
               
               
                 data size for 
                 bandwidth option 1: 
                 bandwidth option 2: 
               
               
                 one operand 
                 25.6 GB/s 
                 32 GB/s 
               
               
                   
               
             
            
               
                  8-bit 
                 1.6 GIPS 
                 2 GIPS 
               
               
                 16-bit 
                 0.8 GIPS 
                 1 GIPS 
               
               
                 32-bit 
                 0.4 GIPS 
                 0.5 GIPS   
               
               
                   
               
            
           
         
       
     
       FIG.  2    is an isometric illustration of rate controlled integrated circuit device stack. In  FIG.  2   , processing system  200  comprises integrated circuit die  211 , memory device die  231 , and memory device die  232 . Integrated circuit die  211 , memory device die  231 , and memory device die  232  are stacked with each other. Integrated circuit die  211  includes a two-dimensional array with 3 rows and 4 columns of processing elements (PEs) with controllers  211   aa - 211   cd . In other words, die  211 , and processing elements  211   aa - 211   cd  in particular include memory controller circuitry and other processing circuitry (e.g., an array of processing nodes, an ALU, a CPU, a GPU, DSP, etc.). Integrated circuit die  211  also include rate control  260 . 
     Memory device die  231  is illustrated with two-dimensional array with 3 rows and 4 columns of memory regions  231   aa - 231   cd . Likewise, memory device die  232  is illustrated with two-dimensional array with 3 rows and 4 columns of memory regions  232   aa - 232   cd . It should be understood that the selection of 3 rows and 4 columns is merely for the purposes of illustration. Any number of rows and/or columns are contemplated. Note that in  FIG.  2   , some DRAM regions (e.g., DRAM regions  231   ca - 231   cc    232   ca - 232   cc ) are obscured by die  211  or memory device die  231  and are therefore not visible in  FIG.  2   . 
     In an embodiment of processing system  200 , each PE/controller  211   aa - 211   cd  of integrated circuit die  211  is intercoupled to its nearest neighbors in the left and right directions and the front and back directions. In another embodiment of processing system  200 , one or more of PE/controllers  211   aa - 211   cd  (including all) of integrated circuit die  211  may not be intercoupled to another of PE/controllers  211   aa - 211   cd  or intercoupled to more than one of the other PE/controllers  211   aa - 211   cd . In these embodiments, a two-dimensional array is illustrated in  FIG.  2    as being on integrated circuit die  211 . The intercoupling may comprise intercoupling circuitry that includes, but is not limited to, input and/or output (I/O) circuitry, buffer circuitry, parallel buses, serial busses, through-silicon via (TSV) connections, and the like. Thus, for example, PE/controller  211   bb  lies between PE/controller  211   ba  and PE/controller  211   bc  in the left and right directions. PE/controller  211   bb  therefore may be intercoupled with both PE/controller  211   ba  and PE/controller  211   bc . Also, as an example, PE/controller  211   bb  lies between PE/controller  211   cb  and PE/controller  211   ab  in the front and back directions. PE/controller  211   bb  may therefore also be intercoupled with PE/controller  211   cb  and PE/controller  211   ab . This pattern of being intercoupled with zero, one, or more, of the respective adjacent left-to-right (if present) and front-to-back (if present) PE/controller  211   aa - 211   cd  may be repeated for any number of and combinations of PE/controllers  211   aa - 211   cd.    
     In an embodiment, PE/controllers  211   aa - 211   cd  and DRAM regions  231   aa - 231   cd    232   aa - 232   cd  have the same size such that each PE/controllers  211   aa - 211   cd  on integrated circuit die  211  lies above respective DRAM regions  231   aa - 231   cd    232   aa - 232   cd  on memory device die  231  and memory device die  232 . Each PE/controller  211   aa - 211   cd  is also intercoupled with the corresponding DRAM regions  231   aa - 231   cd    232   aa - 232   cd  that are above (or in another embodiment, below) that respective PE/controller  211   aa - 211   cd . In other words, DRAM region  231   aa  lies directly below PE/controller  211   aa  and is intercoupled with PE/controller  211   aa ; DRAM region  232   aa  also lies directly below PE/controller  211   aa  and is intercoupled with PE/controller  211   aa ; DRAM region  231   ab  lies directly below PE/controller  211   ab  and is intercoupled with PE/controller  211   ab ; DRAM region  232   ab  also lies directly below PE/controller  211   ab  and is intercoupled with PE/controller  211   ab , and so on. This vertical intercoupling is illustrated in  FIG.  2    by the bidirectional arrows running from PE/controllers  211   aa - 211   ad  on integrated circuit die  211  to corresponding DRAM regions  231   aa - 231   cd    232   aa - 232   cd  on memory device die  231  and memory device die  232 . It should be understood that PE/controllers  211   ba - 211   cd  on integrated circuit die  211  are intercoupled to corresponding DRAM regions  231   ba - 231   cd    232   ba - 232   cd  on memory device die  231  and memory device die  232 . However, these arrows have been omitted from  FIG.  2    because integrated circuit die  211  or memory device die  231  is at least partially obscuring them in the isometric view of  FIG.  2   . 
     It should be understood that, for the sake of brevity and clarity, only three dies  211 ,  231 , and  232  are illustrated in  FIG.  2   . One or more additional dies, with additional two-dimensional arrays of PE/controllers, and/or DRAMs may be stacked with dies  211 ,  231 , and  232  and intercoupled with PE/controllers  211   aa - 211   cd  in a like manner. These additional dies may form additional layers of two-dimensional PE/controller arrays so that the resulting three-dimensional PE/controller array has more than one layer in the vertical direction. Similarly, additional dies may form additional layers of memory devices so that the resulting three-dimensional memory device array has more than two layers in the vertical direction. 
     Each PE/controller  211   aa - 211   cd  may have associated memory which may be DRAM or SRAM (not shown in  FIG.  2   .) PE/controllers  211   aa - 211   cd  may include both processing logic, controller logic, and the associated memory on the same die. Rate control  260  is operatively coupled to each of PE/controllers  211   aa - 211   cd . Rate control  260  is operatively coupled to each of PE/controllers  211   aa - 211   cd  to, based on the operands and/or results being communicated with DRAM regions  231   aa - 231   cd    232   aa - 232   cd  and/or internal memory/registers, control the rate that PE/controllers  211   aa - 211   cd  are operated. In particular, rate control  260  may change the frequency of one or more clocks being supplied to the processing element circuitry of PE/controllers  211   aa - 211   cd.    
     In an embodiment, the rate that operands, results, and/or instructions are communicated between (i.e., read or written) each PE/controller  211   aa - 211   cd  and DRAM regions  231   aa - 231   cd    232   aa - 232   cd  on memory device die  231  may be limited by the bandwidth of DRAM regions  231   aa - 231   cd    232   aa - 232   cd . For example, each PE/controller  211   aa - 211   cd  may have a maximum operating rate of 1 billion instructions per second (GIPS). Each instruction being executed may, for example, require one 32-bit operand be received from an associated DRAM region  231   aa - 231   cd    232   aa - 232   cd . Thus, each of PE/controller  211   aa - 211   cd  would, if operated at 1 GIPS, require 4 GB/s of data be received from an associated DRAM region  231   aa - 231   cd    232   aa - 232   cd . If, however, DRAM regions  231   aa - 231   cd    232   aa - 232   cd  can only supply 2 GB/s of data to its associated PE/controller  211   aa - 211   cd , the rate that PE/controller  211   aa - 211   cd  complete instructions will be limited to 0.5 GIPS by the supply of data from its associated DRAM regions  231   aa - 231   cd    232   aa - 232   cd.    
     In an embodiment, based on information about the operands needed by PE/controller  211   aa - 211   cd , rate control  260  sets the operating rate of PE/controllers  211   aa - 211   cd . Thus, for the previous example, rate control  260 , based on the information that each instruction being executed by PE/controllers  211   aa - 211   cd  requires one 32-bit operand be received from DRAM regions  231   aa - 231   cd    232   aa - 232   cd , and the information that DRAM regions  231   aa - 231   cd    232   aa - 232   cd  can supply a maximum of 2 GB/s of data to each PE/controller  211   aa - 211   cd , rate control  260  would configure one or more clock signals to PE/controller  211   aa - 211   cd  such that PE/controllers  211   aa - 211   cd  are operated at 0.5 GIPS. In this manner, the rate that PE/controllers  211   aa - 211   cd  are operating (0.5 GIPS) more efficiently matches the maximum rate that DRAM regions  231   aa - 231   cd    232   aa - 232   cd  are supplying operands to PE/controllers  211   aa - 211   cd.    
     In an embodiment, rate control  260  receives operand information via one or more indicators embedded in instructions to be processed by PE/controllers  211   aa - 211   cd . In another embodiment, a register or other indicator in rate control  260  is set to provide operand information. In an embodiment, rate control  260  includes a look-up table that relates operand information and DRAM region  231   aa - 231   cd    232   aa - 232   cd  bandwidth to operating rates for PE/controllers  211   aa - 211   cd . In an embodiment, operand information comprises the data types to be (or are being) communicated with associated DRAM regions  231   aa - 231   cd    232   aa - 232   cd . An example of this type of table was illustrated in Table 1. Additional tables may relate operand information from other sources (e.g., registers, SRAM, DRAM, flash, etc.) to operating rates for DRAM regions  231   aa - 231   cd    232   aa - 232   cd.    
     In  FIG.  2   , die  211  is illustrated as having a single rate control block  260  that controls all of PE/controllers  211   aa - 211   cd . It should be understood, however, that each PE/controllers  211   aa - 211   cd  may have its own rate control inside it (not shown in  FIG.  2   ). Similarly, subsets of PE/controllers  211   aa - 211   cd  (e.g., a row of PE/controllers  211   aa - 211   ad ) may be controlled by a single rate control such that there are multiple rate controls  260  (not shown in  FIG.  2   ). 
       FIG.  3    is an isometric illustration of a high-bandwidth memory (HBM) compatible rate controlled integrated circuit device stack. In  FIG.  3   , assembly  300  includes processing/controller die  310  stacked with DRAM die  370 . It should be understood that additional DRAM dies are included in assembly  300 . However, these are not illustrated in  FIG.  3    because of illustration constraints. Assembly  300  may be, for example, an implementation of system  100  or system  200 . Processing/controller die  310  includes channel connections (e.g., TSVs)  350 , PE/controllers  310   a - 310   d , and rate control  360 . PE/controllers  310   a - 310   d  include and/or are coupled to TSV connections  317   a - 317   d , respectively. In an embodiment, channel connections  350  of processing/controller die  310  are connection compatible with an HBM standard. In an embodiment, PE/controllers  310   a - 310   d  are or correspond to at least a portion of PE array  110  and/or PE/controllers  211   aa - 211   cd . Thus, for example, die  310  may be an implementation and/or example of die  211 . 
     DRAM die  370  includes channel connections (e.g., TSVs)  375  and DRAM regions  370   a - 370   d . In an embodiment, each DRAM memory region might consist of one or more DRAM memory banks and may include additional circuitry (e.g. to control, connect to, and/or drive TSV connections  317   a - 317   d , and/or included DRAM banks). DRAM regions  370   a ,  370   c , and  370   d  include and/or are coupled to TSV connections  377   a ,  377   c , and  377   d , respectively. DRAM region  370   b  also includes and/or is coupled to TSV connections. However, in  FIG.  3   , these TSV connections are obscured by processing/controller die  310  and are therefore not illustrated in  FIG.  3   . In an embodiment, channel  375  of DRAM die  370  are connection compatible with an HBM standard. 
     TSV connections  317   a ,  317   c , and  317   d  of PE/controllers  310   a ,  310   c , and  310   d  of processing/controller die  310  are aligned with TSV connections  377   a ,  377   c , and  377   d  of DRAM regions  370   a ,  370   c , and  370   d  of DRAM die  370 , respectively and the TSV connections of the other DRAM dies in assembly  300 . Likewise, TSV connections  317   b  of PE/controller  310   b  of processing/controller die  310  are aligned with the obscured (in  FIG.  3   ) TSV connections of DRAM region  370   b . Channel connections  350  of processing/controller die  310  are aligned with channel connections  375  of DRAM die  370  and the channel connections of the other DRAM dies in assembly  300 . Thus, when processing/controller die  310 , DRAM die  370 , and the other DRAM dies in assembly  300  are stacked with each other, TSV connections  317   a - 317   d  of PE/controllers  310   a - 310   d  of processing/controller die  310  are electrically connected to TSV connections (e.g.,  377   a ,  377   c , and  377   d ) of DRAM regions  370   a - 370   d  of DRAM die  370  and the TSV connections of the other DRAM dies in assembly  300 . This is illustrated in  FIG.  3    by TSV representations  315   a ,  315   c , and  315   d . Likewise, channel connections  350  of processing/controller die  310  are electrically connected with channel connections  375  of DRAM die  370  and the channel connections of the other DRAM dies in assembly  300 . This is illustrated in  FIG.  3    by TSV representation  315 . 
     TSV connections between PE/controllers  310   a - 310   d , DRAM regions  370   a - 370   d , and the other DRAM regions in assembly  300  form direct channels and allow PE/controllers  310   a - 310   d  to access DRAM regions  370   a - 370   d  and the DRAM regions of the other DRAM dies in assembly  300 . TSV connections between PE/controllers  310   a - 310   d , DRAM regions  370   a - 370   d , and the DRAM regions of the other DRAM dies in assembly  300  form direct channels and allow PE/controllers  310   a - 310   d  to access DRAM regions  370   a - 370   d  and the DRAM regions of the other DRAM dies in assembly  300  without the data flowing via channel connections  350  and/or channel connections  375 . In addition, the direct channels formed by TSV connections between PE/controllers  310   a - 310   d , DRAM regions  370   a - 370   d , and the DRAM regions of the other DRAM dies in assembly  300  allow PE/controllers  310   a - 310   d  to access respective DRAM regions  370   a - 370   d  and the DRAM regions of the other DRAM dies in assembly  300  independently of each other. PE/controllers  310   a - 310   d  accessing respective DRAM regions  370   a - 370   d  and the DRAM regions of the other DRAM dies in assembly  300  independently of each other allow PE/controllers  310   a - 310   d  to access respective DRAM regions  370   a - 370   d  and the DRAM regions of the other DRAM dies in assembly  300  in parallel and/or concurrently—thereby providing a high memory-to-processing element bandwidth and lower latency. 
     In an embodiment, the direct channels formed by the TSV connections between PE/controllers  310   a - 310   d , DRAM regions  370   a - 370   d , and the DRAM regions of the other DRAM dies in assembly  300  may be made in a common bus type configuration. Communication of commands, addresses, and data between PE/controllers  310   a - 310   d , DRAM regions  370   a - 370   d , and the DRAM regions of the other DRAM dies in assembly  300  on respective common command/address and data busses may use time-division multiplexing. Communication of commands, addresses, and data between PE/controllers  310   a - 310   d , DRAM regions  370   a - 370   d , and the DRAM regions of the other DRAM dies in assembly  300  on a respective common bus may use time-division multiplexing by assigning each of DRAM regions  370   a - 370   d , and the DRAM regions of the other DRAM dies in assembly  300  a repeating time slot to communicate with the PE/controller  310   a - 310   d  on the common bus. 
     Rate control  360  is operatively coupled to each of PE/controllers  310   a - 310   d . Rate control  360  is operatively coupled to each of PE/controllers  310   a - 310   d  to, based on the operands and/or results being communicated with DRAM regions  370   a - 370   d  and/or internal memory/registers, control the rate that PE/controllers  310   a - 310   d  are operated. In particular, rate control  360  may change the frequency of one or more clocks being supplied to the processing element circuitry of PE/controllers  310   a - 310   d.    
     In an embodiment, the rate that operands, results, and/or instructions are communicated between (i.e., read or written) each PE/controllers  310   a - 310   d  and DRAM regions  370   a - 370   d  may be limited by the bandwidth of DRAM regions  370   a - 370   d . For example, each PE/controllers  310   a - 310   d  may have a maximum operating rate of 1 billion instructions per second (GIPS). Each instruction being executed may, for example, require one 16-bit operand be received from an associated DRAM region  370   a - 370   d . Thus, each of PE/controllers  310   a - 310   d  would, if operated at 1 GIPS, require 2 GB/s of data be received from an associated DRAM region  370   a - 370   d . If DRAM regions  370   a - 370   d  can supply 2 GB/s of data to its associated PE/controllers  310   a - 310   d , the rate that PE/controllers  310   a - 310   d  complete instructions may be set to 1.0 GIPS by rate control  360 . If, however, each instruction being executed requires one 32-bit operand be received from an associated DRAM region  370   a - 370   d . Because DRAM regions  370   a - 370   d  can only supply 2 GB/s of data to its associated PE/controllers  310   a - 310   d , the rate that PE/controllers  310   a - 310   d  complete instructions may be set to 0.5 GIPS by rate control  360 . 
     In an embodiment, based on information about the operands needed by PE/controllers  310   a - 310   d , rate control  360  sets the operating rate of PE/controllers  310   a - 310   d . Thus, for example, based on the information that each instruction being executed by PE/controllers  310   a - 310   d  requires one 32-bit operand be received from DRAM regions  370   a - 370   d , and the information that DRAM regions  370   a - 370   d  can supply a maximum of 2 GB/s of data to each PE/controllers  310   a - 310   d , rate control  260  would configure one or more clock signals to PE/controllers  310   a - 310   d  such that PE/controllers  310   a - 310   d  are operated at 0.5 GIPS. In this manner, the rate that PE/controllers  310   a - 310   d  are operating (0.5 GIPS) more efficiently matches the maximum rate that DRAM regions  370   a - 370   d  are supplying operands to and/or storing results from PE/controllers  310   a - 310   d.    
     In an embodiment, rate control  360  receives operand information via one or more indicators embedded in instructions to be processed by PE/controllers  310   a - 310   d . In another embodiment, a register or other indicator in rate control  360  is set to provide operand information. In an embodiment, rate control  360  includes a look-up table that relates operand information and DRAM regions  370   a - 370   d  bandwidth to operating rates for PE/controllers  310   a - 310   d . In an embodiment, operand information comprises the data types to be (or are being) communicated with associated DRAM regions  370   a - 370   d . An example of this type of table was illustrated in Table 1. Additional tables may relate operand information from other sources (e.g., registers, SRAM, DRAM, flash, etc.) to operating rates for DRAM regions  370   a - 370   d.    
     It should be understood, that one or more of the functions, operations, configurations, etc. described herein with respect to system  100  and system  200  may also be accomplished by assembly  300 . Thus, for the sake of brevity, a discussion of these functions, operations, configurations, etc. will not be repeated herein in with respect to  FIG.  3    and assembly  300 . 
       FIG.  4    illustrates an example processing array. In  FIG.  4   , processing element  410  comprises processing nodes  411   aa - 411   pp , DRAM regions  431   aa - 431   pp , optional input buffer circuitry  416 , and optional output buffer circuitry  417 . Processing nodes  411   aa - 411   pp  and associated directly accessed DRAM regions  431   aa - 431   pp  are arranged in a two dimensional grid (array). Processing nodes  411   aa - 411   pp  are arranged such that each processing node  411   aa - 411   pp  receives an input from the top of the page direction and may provide an output (result) to the next processing node to the right. Processing nodes  411   aa - 411   pp  may forward the received input to the next processing node below it. The top row  411   aa - 411   ab  of the array of processing element  410  receives respective inputs from input buffer circuitry  416 . The righthand most column of the array of processing element  410  provides respective outputs to output buffer circuitry  417 . It should be understood that processing element  410  is configured as a systolic array. Thus, each processing node  411   aa - 411   pp  in the systolic array of processing element  410  may work in lock step with its neighbors. 
     In  FIG.  4   , processing nodes  411   aa - 411   pp  may be interpreted to represent a 16×16 (a through p rows and a through p columns) processing node  411   aa - 411   pp  array. However, it should be understood that this is merely an example. Any number of rows and any number of columns of processing nodes  411   aa - 411   pp  may be implemented. 
     In an embodiment, based on information about the operands needed by Processing nodes  411   aa - 411   pp , the operating rate of processing nodes  411   aa - 411   pp  is set. Thus, for example, based on the information that each instruction being executed by processing nodes  411   aa - 411   pp  requires one 32-bit operand be received from directly accessed DRAM regions  431   aa - 431   pp , and the information that directly accessed DRAM regions  431   aa - 431   pp  can supply a maximum of 2 GB/s of data to each processing node  411   aa - 411   pp , processing nodes would be operated in lock step at 0.5 GIPS. In this manner, the rate that processing nodes  411   aa - 411   pp  are operating (0.5 GIPS) more efficiently matches the maximum rate that DRAM regions  431   aa - 431   pp  are supplying operands to and/or storing results from DRAM regions  431   aa - 431   pp.    
       FIG.  5    illustrates an example processing node of a processing element. Processing node  542  may be, or be a part of, processing element array  110 , processing elements  111 - 113 , PE/controllers  211   aa - 211   cd , and/or PE/controllers  310   a - 310   d . Processing node  542  comprises processing system  543 . Processing system  543  includes 8-bit operand processing circuitry  591 , 16-bit operand processing circuitry,  592  and 32-bit operand processing circuitry  593 . 
     Processing system  543 , and 8-bit operand processing circuitry  591 , 16-bit operand processing circuitry  592 , and 32-bit operand processing circuitry  593 , in particular, may include and/or implement one or more of the following: a memory functions (e.g., a register) and/or SRAM); multiply functions, addition (accumulate) functions, and/or activation functions. For example, 8-bit processing circuitry  591  may comprise an 8-bit arithmetic logic unit to process 8-bit operands as inputs; 16-bit processing circuitry  592  may comprise a 16-bit arithmetic logic unit to process 16-bit operands as inputs; and/or 32-bit processing circuitry  593  may comprise a 32-bit arithmetic logic unit to process 32-bit operands as inputs. 
     In an embodiment, processing node  542  receives at least one value may be received from the next processing node above processing node  542  (or an input to the processing element) and may be provided to processing system  543 . Processing system  543  may be, or include, an application specific integrated circuit (ASIC) device, a graphics processor unit (GPU), a central processing unit (CPU), a system-on-chip (SoC), or an integrated circuit device that includes many circuit blocks such as ones selected from graphics cores, processor cores, and MPEG encoder/decoders, etc. 
     The output of processing node  542  and/or processing system  543  may be provided to the next processing node to the right (or an output of the processing element.) The at least one value that was received from the next processing node above processing node  542  (or an input to the processing element) may be provided to the next processing node below. 
       FIG.  6    illustrates an example distribution of memory bandwidth to processing elements. In  FIG.  6   , system  600  includes a direct (vertical) channel  617  between a processing element (e.g. PE/controllers  310   a ) and a DRAM region (e.g., DRAM region  370   a ) is accessed (read or write) using N number of bits. These N number of bits are distributed to M number of processing nodes  640   aa - 640   bb  (e.g., processing nodes  411   aa - 411   pp ). Thus, each processing node  640   aa - 640   bb  accesses the direct channel using N/M number of bits. 
     For example, if direct channel  617  has 256 bits and operates at 1 GHz, the amount of data communicated via direct channel  617  is 32 GB/s. If there are sixteen (16) processing nodes  640   aa - 640   bb , each processing node can communicate (e.g., read or write) 2 GB/s via the direct channel using 16 bits of the direct channel. If, for example, each processing node  640   aa - 640   bb  is receiving one (1) 16-bit operand per instruction executed, processing nodes  640   aa - 640   bb  are operated (e.g., by rate control  360 ) at 1 GIPS. If, in another example, each processing node  640   aa - 640   bb  is receiving two (2) 16-bit operands per instruction executed, processing nodes  640   aa - 640   bb  are operated (e.g., by rate control  360 ) at 0.5 GIPS. Thus, it should be understood that processing nodes  640   aa - 640   bb  may be operated at different processing rates based on the operand requirements of the instructions being processed and the amount of direct channel bandwidth allocated to each of processing nodes  640   aa - 640   bb.    
       FIG.  7    is a flowchart illustrating a method of operating a processing array. One or more steps illustrated in  FIG.  6    may be performed by, for example, system  100 , system  200 , assembly  300 , system  400 , system  500 , and/or their components. By a plurality of processing elements on a processor die, respective ones of a plurality of memory arrays on a memory device electrically coupled to, and stacked with, the processor die are accessed independently of the other of the processing elements via respective array access interfaces ( 602 ). For example, PE/controllers  211   aa - 211   cd  on processor die  211  may access memory regions  231   aa - 231   cd  independently of the other of PE/controllers  211   aa - 211   cd  accessing their associated memory regions  231   aa - 231   cd.    
     A first operand size indicator associated with a first operand size corresponding to data being communicated between the respective ones of the plurality of memory arrays and the plurality of processing elements is determined ( 704 ). For example, rate control  260  may determine, receive, or calculate information about the size of operands, results, and/or instructions being communicated (or are to be communicated) between (i.e., read or written) each PE/controller  211   aa - 211   cd  and DRAM regions  231   aa - 231   cd    232   aa - 232   cd . The processing elements are operated at a frequency that is selected based on the first operand size indicator ( 706 ). For example, based on the information about the size of operands, results, and/or instructions being communicated (or are to be communicated) between (i.e., read or written) each PE/controllers  211   aa - 211   cd  and DRAM regions  231   aa - 231   cd    232   aa - 232   cd , rate control  260  may select an operating frequency for PE/controllers  211   aa - 211   cd . In another example, based on information that each instruction being executed by PE/controllers  211   aa - 211   cd  requires one 32-bit operand be received from directly accessed DRAM regions  431   aa - 431   bb , and the information that directly accessed DRAM regions  231   aa - 231   cd    232   aa - 232   cd  can supply a maximum of 32 GB/s of data to the sixteen (16) processing nodes of PE/controllers  211   aa - 211   cd , rate control  260  would operate PE/controllers  211   aa - 211   cd  at 0.5 GIPS. In this manner, the rate that the sixteen (16) processing nodes of PE/controllers  211   aa - 211   cd  are operating (0.5 GIPS) more efficiently matches the maximum rate that DRAM regions  231   aa - 231   cd    232   aa - 232   cd  are supplying operands to and/or storing results from DRAM regions  231   aa - 231   cd    232   aa - 232   cd.    
     The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of system  100 , system  200 , assembly  300 , system  400 , processing node  542 , system  600 , and their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves. 
     Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3½ inch floppy media, CDs, DVDs, and so on. 
       FIG.  8    is a block diagram illustrating one embodiment of a processing system  800  for including, processing, or generating, a representation of a circuit component  820 . Processing system  800  includes one or more processors  802 , a memory  804 , and one or more communications devices  806 . Processors  802 , memory  804 , and communications devices  806  communicate using any suitable type, number, and/or configuration of wired and/or wireless connections  808 . 
     Processors  802  execute instructions of one or more processes  812  stored in a memory  804  to process and/or generate circuit component  820  responsive to user inputs  814  and parameters  816 . Processes  812  may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and/or verify electronic circuitry and/or generate photomasks for electronic circuitry. Representation  820  includes data that describes all or portions of system  100 , system  200 , assembly  300 , system  400 , processing node  542 , system  600 , and their components, as shown in the Figures. 
     Representation  820  may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation  820  may be stored on storage media or communicated by carrier waves. 
     Data formats in which representation  820  may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email 
     User inputs  814  may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters  816  may include specifications and/or characteristics that are input to help define representation  820 . For example, parameters  816  may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and/or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.). 
     Memory  804  includes any suitable type, number, and/or configuration of non-transitory computer-readable storage media that stores processes  812 , user inputs  814 , parameters  816 , and circuit component  820 . 
     Communications devices  806  include any suitable type, number, and/or configuration of wired and/or wireless devices that transmit information from processing system  800  to another processing or storage system (not shown) and/or receive information from another processing or storage system (not shown). For example, communications devices  806  may transmit circuit component  820  to another system. Communications devices  806  may receive processes  812 , user inputs  814 , parameters  816 , and/or circuit component  820  and cause processes  812 , user inputs  814 , parameters  816 , and/or circuit component  820  to be stored in memory  804 . 
     Implementations discussed herein include, but are not limited to, the following examples: 
     Example 1: A device, comprising: a memory die comprising a plurality of memory arrays; and, a processor die, stacked with the memory die, comprising a plurality of processing elements that communicate data directly with respective ones of the plurality of memory arrays, the processor die including sensing circuitry to select a processing speed for the processing elements based on an operand size being communicated between the processing elements and the memory arrays. 
     Example 2: The device of example 1, wherein the processing elements include first circuitry configured to process operands having a first size and second circuitry configured to process operands having a second size. 
     Example 3: The device of example 2, wherein an instruction being executed by a processing element determines which of the first circuitry and the second circuitry is selected. 
     Example 4: The device of example 3, wherein the sensing circuitry selects the processing speed based at least in part on the instruction. 
     Example 5: The device of example 1, wherein processing speed selection is further based on a communication bandwidth between the processing elements and the memory arrays. 
     Example 6: The device of example 1, wherein processing speed selection is further based on an access cycle time of the memory arrays. 
     Example 7: The device of example 1, wherein the plurality of processing elements communicate data directly with respective ones of the plurality of memory arrays using through-silicon via (TSVs). 
     Example 8: A device, comprising: a memory device die comprising a plurality of memory arrays, the memory arrays to be accessed independently of the other of the plurality of memory arrays via respective array access interfaces; and, a processor die comprising a plurality of processing elements, the processor die electrically coupled to, and stacked with, the memory device die, each of the processing elements connected to at least one array access interface to communicate data directly with a respective memory array, the processor die including circuitry configured to determine an operand size being communicated with the memory device die by the processing elements and to, based on the operand size, select a clock frequency to be supplied to the processing elements. 
     Example 9: The device of example 8, wherein the processing elements include first circuitry configured to process operands having a first size and second circuitry configured to process operands having a second size. 
     Example 10: The device of example 9, wherein an instruction being executed by a processing element determines which of the first circuitry and the second circuitry is selected. 
     Example 11: The device of example 10, wherein the clock frequency selected is based at least in part on the instruction. 
     Example 12: The device of example 8, wherein clock frequency selection is further based on a communication bandwidth between the processing elements and the memory arrays. 
     Example 13: The device of example 8, wherein clock frequency selection is further based on an access cycle time of the memory arrays. 
     Example 14: The device of example 8, wherein the array access interfaces are connected to the plurality of processing elements using through-silicon via (TSVs). 
     Example 15: A method, comprising: accessing, by a plurality of processing elements on a processor die, respective ones of a plurality of memory arrays on a memory device die electrically coupled to, and stacked with, the processor die, independently of the other of the processing elements via respective array access interfaces; determining a first operand size indicator associated with a first operand size corresponding to data being communicated between the respective ones of the plurality of memory arrays and the plurality of processing elements; and, operating the processing elements at a first operating frequency that is selected based on the first operand size indicator. 
     Example 16: The method of example 15, further comprising: determining a second operand size indicator associated with a second operand size corresponding to data being communicated between the respective ones of the plurality of memory arrays and the plurality of processing elements; and, operating the processing elements at a second operating frequency that is selected based on the second operand size indicator. 
     Example 17: The method of example 16, wherein determining the first operand size indicator is based on a first instruction to be executed by the processing elements. 
     Example 18: The method of example 17, wherein determining the second operand size indicator is based on a second instruction to be executed by the processing elements. 
     Example 19: The method of example 16, wherein determining the first operand size indicator is based on a first instruction that is to be repeatedly executed by the processing elements. 
     Example 20: The method of example 19, wherein determining the second operand size indicator is based on a second instruction to be repeatedly executed by the processing elements. 
     The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.