Patent Publication Number: US-11645174-B2

Title: Recovery flow with reduced address lock contention in a content addressable storage system

Description:
FIELD 
     The field relates generally to information processing systems, and more particularly to storage in information processing systems. 
     BACKGROUND 
     Various types of content addressable storage (CAS) systems are known. Typical CAS systems allow data pages of one or more logical storage volumes to be accessed using content-based signatures that are computed from content of respective ones of the data pages. Such CAS system arrangements facilitate implementation of deduplication and compression. For example, the storage system need only maintain a single copy of a given data page even though that same data page may be part of multiple logical storage volumes. Although these and other CAS systems typically provide a high level of storage efficiency through deduplication and compression, problems can arise under certain conditions. For example, a CAS system generally includes a volatile write cache that temporarily stores write data that is later “destaged” to a persistent data storage location. For write requests received by the CAS system, address locks are placed on corresponding data pages until the destaging of those data pages from the write cache is completed. However, the clearing of such address locks can be unduly delayed in the presence of a storage node failure in a distributed implementation of the CAS system, leading to performance degradations. 
     SUMMARY 
     Illustrative embodiments provide techniques for recovery flow with reduced address lock contention in a CAS system. For example, some embodiments are configured to issue write cache metadata preload commands as part of a recovery flow. Such a “recovery flow” as the term is broadly used herein encompasses a wide variety of different types of inter-node messaging and associated processing operations. The recovery flow in some embodiments is illustratively initiated upon detection of a failure of at least one storage node that impacts a write cache destaging process of the CAS system. The preloading of metadata that is performed responsive to the write cache metadata preload commands serves to accelerate the release of address locks acquired on respective data pages as part of the write cache destaging process, thereby facilitating failure recovery and improving system performance. 
     In one embodiment, an apparatus comprises at least one processing device comprising a processor coupled to a memory. The processing device is configured to detect a failure of at least one storage node that impacts a write cache destaging process in a distributed CAS system comprising a plurality of storage nodes each associated with one or more storage devices, and responsive to the detected failure, to issue one or more write cache metadata preload commands to direct one or more other ones of the storage nodes to preload from their associated storage devices metadata characterizing one or more data pages that are subject to the write cache destaging process. 
     The processing device illustratively comprises at least a portion of a distributed storage controller of the distributed CAS system. 
     The storage nodes of the distributed CAS system are illustratively interconnected in a mesh network, although other interconnection arrangements may be used. 
     Each of at least a subset of the storage nodes of the distributed CAS system illustratively comprises a set of processing modules configured to communicate with corresponding sets of processing modules on other ones of the storage nodes, with a given such set of processing modules comprising at least a routing module, a control module and a data module, and the sets of processing modules of the storage nodes of the distributed CAS system collectively comprising at least a portion of a storage controller of the distributed CAS system. 
     In some embodiments, address locks are placed on respective ones of a plurality of data pages targeted by one or more write requests to be destaged from a write cache of the distributed CAS system as part of the write cache destaging process. 
     Detecting a failure of at least one storage node that impacts a write cache destaging process in some embodiments comprises detecting a failure of a data module of a particular storage node that is associated with one or more storage devices that store one or more data pages targeted by one or more write requests to be destaged from a write cache of the distributed CAS system as part of the write cache destaging process. The failure is illustratively detected prior to acquisition of the address locks. For example, the failure may be detected prior to initiation of the write cache destaging process, where the address locks are acquired as part of the write cache destaging process. In these and other embodiments, each of the one or more write cache metadata preload commands is illustratively issued as part of or otherwise in conjunction with an initial step of the write cache destaging process. 
     Each of the one or more write cache metadata preload commands illustratively comprises a remote procedure call (RPC), although other types of command formats can be used in other embodiments. 
     In some embodiments, issuing one or more write cache metadata preload commands to direct one or more other ones of the storage nodes to preload from their associated storage devices metadata characterizing one or more data pages that are subject to the write cache destaging process comprises issuing the one or more write cache metadata preload commands from a first one of the storage nodes to at least a second one of the storage nodes. For example, a plurality of write cache metadata preload commands may be issued from a control module of the first storage node to respective ones of a plurality of data modules of respective ones of the second storage node and one or more additional ones of the storage nodes. 
     Additionally or alternatively, issuing one or more write cache metadata preload commands to direct one or more other ones of the storage nodes to preload from their associated storage devices metadata characterizing one or more data pages that are subject to the write cache destaging process illustratively comprises issuing multiple write cache metadata preload commands to respective ones of a plurality of data modules that are associated with a designated write cache destage batch of the write cache destaging process. 
     In some embodiments, the write cache destaging process is delayed until each of the one or more write cache metadata preload commands issued for a designated write cache destage batch is acknowledged as complete. 
     These and other illustrative embodiments include, without limitation, apparatus, systems, methods and processor-readable storage media. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a block diagram of an information processing system comprising a CAS system incorporating functionality for recovery flow with reduced address lock contention in an illustrative embodiment. 
         FIG.  2    shows an example relationship between routing, control and data modules of a CAS system in an illustrative embodiment. 
         FIGS.  3 A,  3 B and  3 C  show examples of respective first, second and third stages in processing a write request in an illustrative embodiment. These figures are collectively referred to herein as  FIG.  3   . 
         FIG.  4    is a flow diagram of a process for recovery flow with reduced address lock contention in a CAS system in an illustrative embodiment. 
         FIGS.  5  and  6    show examples of processing platforms that may be utilized to implement at least a portion of an information processing system in illustrative embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Illustrative embodiments will be described herein with reference to exemplary information processing systems and associated computers, servers, storage devices and other processing devices. It is to be appreciated, however, that these and other embodiments are not restricted to the particular illustrative system and device configurations shown. Accordingly, the term “information processing system” as used herein is intended to be broadly construed, so as to encompass, for example, processing systems comprising cloud computing and storage systems, as well as other types of processing systems comprising various combinations of physical and virtual processing resources. An information processing system may therefore comprise, for example, at least one data center or other cloud-based system that includes one or more clouds hosting multiple tenants that share cloud resources. Numerous different types of enterprise computing and storage systems are also encompassed by the term “information processing system” as that term is broadly used herein. 
       FIG.  1    shows an information processing system  100  configured in accordance with an illustrative embodiment. The information processing system  100  comprises a plurality of host devices  101 - 1 ,  101 - 2 , . . .  101 -N, collectively referred to herein as host devices  101 , and a CAS system  102 . The host devices  101  are configured to communicate with the CAS system  102  over a network  104 . 
     The host devices  101  illustratively comprise servers or other types of computers of an enterprise computer system, cloud-based computer system or other arrangement of multiple compute nodes associated with respective users. 
     For example, the host devices  101  in some embodiments illustratively provide compute services such as execution of one or more applications on behalf of each of one or more users associated with respective ones of the host devices. Such applications illustratively generate input-output (IO) operations that are processed by the CAS system  102 . The term “input-output” as used herein refers to at least one of input and output. For example, IO operations may comprise write requests and/or read requests directed to logical addresses of a particular logical storage volume of the CAS system  102 . These and other types of IO operations are also generally referred to herein as IO requests. 
     The CAS system  102  illustratively comprises processing devices of one or more processing platforms. For example, the CAS system  102  can comprise one or more processing devices each having a processor and a memory, possibly implementing virtual machines and/or containers, although numerous other configurations are possible. 
     The CAS system  102  can additionally or alternatively be part of cloud infrastructure such as an Amazon Web Services (AWS) system. Other examples of cloud-based systems that can be used to provide at least portions of the CAS system  102  include Google Cloud Platform (GCP) and Microsoft Azure. 
     The host devices  101  and the CAS system  102  may be implemented on a common processing platform, or on separate processing platforms. The host devices  101  are illustratively configured to write data to and read data from the CAS system  102  in accordance with applications executing on those host devices for system users. 
     The term “user” herein is intended to be broadly construed so as to encompass numerous arrangements of human, hardware, software or firmware entities, as well as combinations of such entities. Compute and/or storage services may be provided for users under a Platform-as-a-Service (PaaS) model, an Infrastructure-as-a-Service (IaaS) model and/or a Function-as-a-Service (FaaS) model, although it is to be appreciated that numerous other cloud infrastructure arrangements could be used. Also, illustrative embodiments can be implemented outside of the cloud infrastructure context, as in the case of a stand-alone computing and storage system implemented within a given enterprise. 
     The network  104  is assumed to comprise a portion of a global computer network such as the Internet, although other types of networks can be part of the network  104 , including a wide area network (WAN), a local area network (LAN), a satellite network, a telephone or cable network, a cellular network, a wireless network such as a WiFi or WiMAX network, or various portions or combinations of these and other types of networks. The network  104  in some embodiments therefore comprises combinations of multiple different types of networks each comprising processing devices configured to communicate using Internet Protocol (IP) or other communication protocols. 
     As a more particular example, some embodiments may utilize one or more high-speed local networks in which associated processing devices communicate with one another utilizing Peripheral Component Interconnect express (PCIe) cards of those devices, and networking protocols such as InfiniBand, Gigabit Ethernet or Fibre Channel. Numerous alternative networking arrangements are possible in a given embodiment, as will be appreciated by those skilled in the art. 
     The CAS system  102  comprises a plurality of storage devices  106  and an associated storage controller  108 . The storage devices  106  store data of a plurality of storage volumes. The storage volumes illustratively comprise respective logical units (LUNs) or other types of logical storage volumes. The stored data comprises metadata pages  110  and user data pages  112 , both described in more detail elsewhere herein. The storage devices  106  and storage controller  108  are distributed across multiple storage nodes  115 . The CAS system  102  further comprises a write cache  116  and a write cache journal  118 , both also illustratively distributed across the storage nodes  115  of the CAS system  102 . 
     The storage devices  106  of the CAS system  102  illustratively comprise solid state drives (SSDs). Such SSDs are implemented using non-volatile memory (NVM) devices such as flash memory. Other types of NVM devices that can be used to implement at least a portion of the storage devices  106  include non-volatile random access memory (NVRAM), phase-change RAM (PC-RAM), magnetic RAM (MRAM), resistive RAM, spin torque transfer magneto-resistive RAM (STT-MRAM), and Intel Optane™ devices based on 3D XPoint™ memory. These and various combinations of multiple different types of NVM devices may also be used. For example, hard disk drives (HDDs) can be used in combination with or in place of SSDs or other types of NVM devices. 
     However, it is to be appreciated that other types of storage devices can be used in CAS system  102  in other embodiments. For example, a given storage system as the term is broadly used herein can include a combination of different types of storage devices, as in the case of a multi-tier storage system comprising a flash-based fast tier and a disk-based capacity tier. In such an embodiment, each of the fast tier and the capacity tier of the multi-tier storage system comprises a plurality of storage devices with different types of storage devices being used in different ones of the storage tiers. For example, the fast tier may comprise flash drives while the capacity tier comprises hard disk drives. The particular storage devices used in a given storage tier may be varied in other embodiments, and multiple distinct storage device types may be used within a single storage tier. The term “storage device” as used herein is intended to be broadly construed, so as to encompass, for example, SSDs, HDDs, flash drives, hybrid drives or other types of storage devices. 
     In some embodiments, the CAS system  102  illustratively comprises a scale-out all-flash content addressable storage array such as an XtremIO™ storage array from Dell EMC of Hopkinton, Mass. A wide variety of other types of storage arrays can be used in implementing a given one of the CAS system  102  in other embodiments, including by way of example one or more VNX®, VIVIAX®, Unity™ or PowerMax™ storage arrays, commercially available from Dell EMC. Additional or alternative types of storage products that can be used in implementing a given storage system in illustrative embodiments include software-defined storage, cloud storage, object-based storage and scale-out storage. Combinations of multiple ones of these and other storage types can also be used in implementing a given storage system in an illustrative embodiment. 
     The term “storage system” as used herein is therefore intended to be broadly construed, and should not be viewed as being limited to CAS systems based on flash memory or other types of NVM storage devices. A given storage system as the term is broadly used herein can comprise, for example, network-attached storage (NAS), storage area networks (SANs), direct-attached storage (DAS) and distributed DAS, as well as combinations of these and other storage types, including software-defined storage. 
     In some embodiments, communications between the host devices  101  and the CAS system  102  comprise Small Computer System Interface (SCSI) or Internet SCSI (iSCSI) commands. Other types of SCSI or non-SCSI commands may be used in other embodiments, including commands that are part of a standard command set, or custom commands such as a “vendor unique command” or VU command that is not part of a standard command set. The term “command” as used herein is therefore intended to be broadly construed, so as to encompass, for example, a composite command that comprises a combination of multiple individual commands. Numerous other commands can be used in other embodiments. 
     For example, although in some embodiments certain commands used by the host devices  101  to communicate with the CAS system  102  illustratively comprise SCSI or iSCSI commands, other embodiments can implement IO operations utilizing command features and functionality associated with NVM Express (NVMe), as described in the NVMe Specification, Revision 1.3, May 2017, which is incorporated by reference herein. Other storage protocols of this type that may be utilized in illustrative embodiments disclosed herein include NVMe over Fabric, also referred to as NVMeoF, and NVMe over Transmission Control Protocol (TCP), also referred to as NVMe/TCP. 
     A particular one of the host devices  101 , namely a first host device  101 - 1 , is shown in greater detail than the other host devices  101  in  FIG.  1   . The first host device  101 - 1 , like the other host devices  101  of the system  100 , interacts over the network  104  with the CAS system  102 . Such interaction illustratively includes generating IO operations, such as read and write requests, and sending such requests over the network  104  for processing by the CAS system  102 . The CAS system  102  in this embodiment implements functionality for recovery flow with reduced address lock contention, as will be described in more detail below. The recovery flow in some embodiments is associated with recovery from a failure of at least a portion of one or more of the storage nodes  115 . 
     The above-noted functionality illustratively includes the performance of a process for recovery flow with reduced address lock contention in the CAS system  102 , such as the example process to be described below in conjunction with  FIG.  4   . References herein to “recovery flow with reduced address lock contention” are intended to be broadly construed, so as to encompass various types of performance improvements relative to conventional approaches to recovery flow processing, and should not be viewed as requiring any particular level of address contention avoidance or other performance measures. 
     The storage controller  108  and the CAS system  102  may further include one or more additional modules and other components typically found in conventional implementations of storage controllers and storage systems, although such additional modules and other components are omitted from the figure for clarity and simplicity of illustration. 
     The host device  101 - 1  comprises a processor  120  coupled to a memory  122 . The host device  101 - 1  is therefore an example of what is more generally referred to herein as a processing device comprising a processor coupled to a memory. The processor  120  executes application processes of one or more applications on behalf of each of one or more users of the host device  101 - 1 . Such application process execution results in the generation of read operations and write operations that are directed by the host device  101 - 1  to the CAS system  102  in the manner disclosed herein. 
     The IO operations generated by the application processes may be placed in one or more IO queues to await further processing by the host device  101 - 1 . Such IO queues may be implemented as part of the memory  122  of the host device  101 - 1 , but could be implemented elsewhere in the host device  101 - 1 . 
     In some embodiments, the host device  101 - 1  comprises a multi-path input-output (MPIO) driver configured to control delivery of IO operations from the host device  101 - 1  to the CAS system  102  over selected ones of a plurality of paths through the network  104 . The paths are illustratively associated with respective initiator-target pairs, with each of a plurality of initiators of the initiator-target pairs comprising a corresponding host bus adaptor (HBA) of the host device  101 - 1 , and each of a plurality of targets of the initiator-target pairs comprising a corresponding port of the CAS system  102 . 
     The MPIO driver may comprise, for example, an otherwise conventional MPIO driver, such as a PowerPath® driver from Dell EMC. Other types of MPIO drivers from other driver vendors may be used. 
     The term “MPIO driver” as used herein is intended to be broadly construed, and such a component is illustratively implemented at least in part as a combination of software and hardware. For example, the MPIO driver can comprise one or more software programs running on processor  120  of host device  101 - 1 . 
     The MPIO driver is configured to deliver IO operations selected from its corresponding IO queues to the CAS system  102  via selected ones of multiple paths over the network  104 . The sources of the IO operations stored in the IO queues illustratively include respective application processes of one or more applications executing on the host device  101 - 1 . For example, IO operations can be generated by each of multiple processes of a database application or other type of application running on the host device  101 - 1 . Such processes issue IO operations for delivery to the CAS system  102  over the network  104 . Other types of sources of IO operations may be present in a given implementation of system  100 . 
     The host device  101 - 1  in directing an IO operation to the CAS system  102  illustratively sends one or more corresponding commands to CAS system  102  over a particular path selected by its MPIO driver, although other arrangements can be used. A given IO operation can therefore comprise one or more commands in a particular storage protocol that the host device  101 - 1  uses to communicate with the CAS system  102 . 
     Each of the additional host devices  101 - 2  through  101 -N is assumed to be configured in substantially the same manner described above for the first host device  101 - 1 . It is also possible that different host devices of different types can each generate IO operations for delivery to the CAS system  102 . 
     The CAS system  102  is illustratively implemented as a distributed storage system, also referred to herein as a clustered storage system, in which each of at least a subset of the storage nodes  115  comprises a set of processing modules configured to communicate with corresponding sets of processing modules on other ones of the storage nodes  115 . The sets of processing modules of the storage nodes of the CAS system  102  collectively comprise at least a portion of the storage controller  108  of the CAS system  102 . For example, in some embodiments the sets of processing modules of the storage nodes collectively comprise a distributed storage controller of the distributed CAS system  102 . A “distributed CAS system” as that term is broadly used herein is intended to encompass any CAS system that, like the CAS system  102 , is distributed across multiple storage nodes. 
     In the CAS system  102 , logical addresses of data pages are mapped to physical addresses of the data pages using respective content-based signatures that are generated from those data pages. The data pages illustratively include user data pages  112 . Metadata pages  110  are typically handled in a different manner, as will be described. 
     The term “page” as used in this and other contexts herein is intended to be broadly construed so as to encompass any of a wide variety of different types of blocks that may be utilized in a block storage device of a storage system. Different native page sizes are generally utilized in different storage systems of different types. For example, XtremIO™ X1 storage arrays utilize a native page size of 8 kilobytes (KB), while XtremIO™ X2 storage arrays utilize a native page size of 16 KB. Larger native page sizes of 64 KB and 128 KB are utilized in VMAX® V2 and VMAX® V3 storage arrays, respectively. The native page size generally refers to a typical page size at which the storage system ordinarily operates, although it is possible that some storage systems may support multiple distinct page sizes as a configurable parameter of the system. Each such page size of a given storage system may be considered a “native page size” of the storage system as that term is broadly used herein. 
     A given “page” as the term is broadly used herein should therefore not be viewed as being limited to any particular range of fixed sizes. In some embodiments, a page size of 8 KB is used, but this is by way of example only and can be varied in other embodiments. For example, page sizes of 4 KB, 16 KB or other values can be used. Accordingly, illustrative embodiments can utilize any of a wide variety of alternative paging arrangements for organizing data pages of the CAS system  102 . 
     Also, the term “storage volume” as used herein is intended to be broadly construed, and should not be viewed as being limited to any particular format or configuration. 
     The content-based signatures utilized in some embodiments illustratively comprise respective hash digests of respective data pages of a storage volume. A given one of the hash digests is generated in illustrative embodiments by applying a secure hashing algorithm to content of a corresponding one of the data pages of the storage volume. For example, a given hash digest can be generated by application of a hash function such as the well-known Secure Hashing Algorithm 1 (SHA1) to the content of its corresponding data page. Other types of secure hashing algorithms, such as SHA2 or SHA256, or more generally other hash functions, can be used in generating content-based signatures herein. 
     A given hash digest in illustrative embodiments is unique to the particular content of the page from which it is generated, such that two pages with exactly the same content will have the same hash digest, while two pages with different content will have different hash digests. It is also possible that other types of content-based signatures may be used, such as hash handles of the type described elsewhere herein. A hash handle generally provides a shortened representation of its corresponding hash digest. More particularly, the hash handles are shorter in length than respective hash digests that are generated by applying a secure hashing algorithm to respective ones of the data pages. Hash handles are considered examples of “content-based signatures” as that term is broadly used herein. 
     As indicated above, the storage controller  108  in this embodiment is implemented as a distributed storage controller that comprises sets of processing modules distributed over the storage nodes  115 . The storage controller  108  is therefore also referred to herein as a distributed storage controller. 
     It is assumed in some embodiments that the processing modules of the distributed storage controller  108  are interconnected in a full mesh network, such that a process of one of the processing modules can communicate with processes of any of the other processing modules. Commands issued by the processes can include, for example, RPCs directed to other ones of the processes. 
     The sets of processing modules of the distributed storage controller  108  illustratively comprise control modules  108 C, data modules  108 D, routing modules  108 R and at least one management module  108 M. Again, these and possibly other processing modules of the distributed storage controller  108  are illustratively interconnected with one another in the full mesh network, such that each of the modules can communicate with each of the other modules, although other types of networks and different module interconnection arrangements can be used in other embodiments. 
     The management module  108 M of the distributed storage controller in this embodiment may more particularly comprise a system-wide management module, also referred to herein as a system manager. Other embodiments can include multiple instances of the management module  108 M implemented on different ones of the storage nodes  115 . It is therefore assumed that the distributed storage controller  108  comprises one or more management modules  108 M. 
     A wide variety of alternative configurations of nodes and processing modules are possible in other embodiments. Also, the term “storage node” as used herein is intended to be broadly construed, and may comprise a node that implements storage control functionality but does not necessarily incorporate storage devices. 
     The processing modules of the distributed storage controller  108  as disclosed herein utilize metadata structures that include logical layer and physical layer mapping tables to be described below. It is to be appreciated that these particular tables are only examples, and other tables or metadata structures having different configurations of entries and fields can be used in other embodiments. The logical layer and physical layer mapping tables in this embodiment illustratively include the following: 
     1. An address-to-hash (“A2H”) table. The A2H table illustratively comprises a plurality of entries accessible utilizing logical addresses as respective keys, with each such entry of the A2H table comprising a corresponding one of the logical addresses, a corresponding one of the hash handles, and possibly one or more additional fields. 
     2. A hash-to-data (“H2D”) table. The H2D table illustratively comprises a plurality of entries accessible utilizing hash handles as respective keys, with each such entry of the H2D table comprising a corresponding one of the hash handles, a physical offset of a corresponding one of the data pages, and possibly one or more additional fields. 
     3. A hash metadata (“HMD”) table. The HMD table illustratively comprises a plurality of entries accessible utilizing hash handles as respective keys. Each such entry of the HMD table comprises a corresponding one of the hash handles, a corresponding reference count and a corresponding physical offset of one of the data pages. A given one of the reference counts denotes the number of logical pages in the storage system that have the same content as the corresponding data page and therefore point to that same data page via their common hash digest. The HMD table illustratively comprises at least a portion of the same information that is found in the H2D table. Accordingly, in other embodiments, those two tables can be combined into a single table, illustratively referred to as an H2D table, an HMD table or another type of physical layer mapping table providing a mapping between hash values, such as hash handles or hash digests, and corresponding physical addresses of data pages. 
     4. A physical layer based (“PLB”) table. The PLB table illustratively comprises a plurality of entries accessible utilizing physical offsets as respective keys, with each such entry of the PLB table comprising a corresponding one of the physical offsets, a corresponding one of the hash digests, and possibly one or more additional fields. 
     As indicated above, the hash handles are generally shorter in length than the corresponding hash digests of the respective data pages, and each illustratively provides a short representation of the corresponding full hash digest. For example, in some embodiments, the full hash digests are 20 bytes in length, and their respective corresponding hash handles are illustratively only 4 or 6 bytes in length. 
     Again, the logical layer and physical layer mapping tables referred to above are examples only, and can be varied in other embodiments. For example, other types of hash-to-physical (“H2P”) mapping tables may be used in addition to or in place of the above-noted H2D, HMD and/or PLB tables. 
     In some embodiments, certain ones of the above-described mapping tables are maintained by particular modules of a distributed storage controller. For example, the mapping tables maintained by the control modules  108 C illustratively comprise at least one A2H table and possibly also at least one H2D table. The A2H tables are utilized to store address-to-hash mapping information and the H2D tables are utilized to store hash-to-data mapping information, in support of mapping of logical addresses for respective pages to corresponding physical addresses for those pages via respective hashes or other types of content-based signatures, as described in further detail elsewhere herein. 
     The control modules  108 C may further comprise additional components such as respective messaging interfaces that are utilized by the control modules  108 C to process routing-to-control messages received from the routing modules  108 R, and to generate control-to-routing messages for transmission to the routing modules  108 R. Such messaging interfaces can also be configured to process instructions and other messages received from the management module  108 M and to generate messages for transmission to the management module  108 M. 
     The data modules  108 D comprise respective control interfaces. These control interfaces support communication between the data modules  108 D and the control modules  108 C. Also included in the data modules are respective SSD interfaces. These SSD interfaces support communications with corresponding ones of the storage devices  106  of the distributed CAS system  102 . 
     The above-described processing module arrangements are presented by way of example only, and can be varied in other embodiments. 
     In some embodiments, a given data path of the CAS system  102  comprises a particular one of the routing modules  108 R, a particular one of the control modules  108 C and a particular one of the data modules  108 D, each configured to handle different stages of the data path. For example, a given IO request can comprise a read request or a write request received in the particular control module from the particular routing module. The particular control module processes the received IO request to determine the particular data module that has access to the one or more data pages targeted by that IO request. 
     Communication links may be established between the various processing modules of the storage controller  108  using well-known communication protocols such as TCP/IP and remote direct memory access (RDMA). For example, respective sets of IP links used in data transfer and corresponding messaging could be associated with respective different ones of the routing modules  108 R. 
     In some embodiments, at least portions of the functionality for recovery flow with reduced address lock contention in the CAS system are distributed over at least the control modules  108 C and data modules  108 D of storage controller  108 . Numerous other arrangements are possible. For example, portions of the functionality can be implemented in the one or more management modules  108 , or using other types and arrangements of modules within or outside of the storage controller  108 . 
     As indicated previously, the storage devices  106  are configured to store metadata pages  110  and user data pages  112 , and may also store additional information not explicitly shown such as, for example, one or more system checkpoints and/or snapshots of storage volumes, and one or more write journals such as the write cache journal  118 . The metadata pages  110  and the user data pages  112  in some embodiments are illustratively stored in respective designated metadata and user data areas of the storage devices  106 . Accordingly, metadata pages  110  and user data pages  112  may be viewed as corresponding to respective designated metadata and user data areas of the storage devices  106 . 
     As noted above, a given “page” as the term is broadly used herein should not be viewed as being limited to any particular range of fixed sizes. In some embodiments, a page size of 8 KB is used, but this is by way of example only and can be varied in other embodiments. For example, page sizes of 4 KB, 16 KB or other values can be used. Accordingly, illustrative embodiments can utilize any of a wide variety of alternative paging arrangements for organizing the metadata pages  110  and the user data pages  112 . 
     The user data pages  112  are part of a plurality of LUNs configured to store files, blocks, objects or other arrangements of data, each also generally referred to herein as a “data item,” on behalf of users of the CAS system  102 . Each such LUN may comprise particular ones of the above-noted user data pages  112  of the user data area. The user data stored in the user data pages  112  can include any type of user data that may be utilized in the system  100 . The term “user data” herein is therefore also intended to be broadly construed. 
     A given storage volume for which content-based signatures are generated, illustratively by signature generators implemented in respective ones of the control modules  108 R and/or elsewhere in the storage nodes  115 , can comprise a set of one or more LUNs, each including multiple ones of the user data pages  112  stored in storage devices  106 . 
     The CAS system  102  in the embodiment of  FIG.  1    is configured to generate hash metadata providing a mapping between content-based digests of respective ones of the user data pages  112  and corresponding physical locations of those pages in the user data area. Content-based digests generated using hash functions are also referred to herein as “hash digests.” Such hash digests or other types of content-based digests are examples of what are more generally referred to herein as “content-based signatures” of the respective user data pages  112 . The hash metadata generated by the CAS system  102  is illustratively stored as metadata pages  110  in the metadata area. The generation and storage of the hash metadata is assumed to be performed under the control of the storage controller  108 . 
     Each of the metadata pages  110  characterizes a plurality of the user data pages  112 . For example, in a given set of n user data pages representing a portion of the user data pages  112 , each of the user data pages is characterized by a LUN identifier, an offset and a content-based signature. The content-based signature is generated as a hash function of content of the corresponding user data page. Illustrative hash functions that may be used to generate the content-based signature include the above-noted SHA1 secure hashing algorithm, or other secure hashing algorithms known to those skilled in the art, including SHA2, SHA256 and many others. The content-based signature is utilized to determine the location of the corresponding user data page within the user data area of the storage devices  106 . 
     Each of the metadata pages  110  in the present embodiment is assumed to have a signature that is not content-based. For example, the metadata page signatures may be generated using hash functions or other signature generation algorithms that do not utilize content of the metadata pages as input to the signature generation algorithm. Also, each of the metadata pages is assumed to characterize a different set of the user data pages. 
     A given set of metadata pages representing a portion of the metadata pages  110  in an illustrative embodiment comprises metadata pages having respective signatures. Each such metadata page characterizes a different set of n user data pages. For example, the characterizing information in each metadata page can include the LUN identifiers, offsets and content-based signatures for each of the n user data pages that are characterized by that metadata page. It is to be appreciated, however, that the user data and metadata page configurations described above are examples only, and numerous alternative user data and metadata page configurations can be used in other embodiments. 
     Ownership of a user data logical address space within the CAS system  102  is illustratively distributed among the control modules  108 C. 
     The functionality for recovery flow with reduced address lock contention in the CAS system  102  in this embodiment is assumed to be distributed across multiple distributed processing modules, including at least a subset of the processing modules  108 C,  108 D,  108 R and  108 M of the distributed storage controller  108 . 
     For example, the management module  108 M of the storage controller  108  may include a recovery flow logic instance that engages corresponding recovery flow logic instances in all of the control modules  108 C in order to support recovery flow with reduced address lock contention in the CAS system  102 . 
     In some embodiments, each of the user data pages  112  has a fixed size such as, for example, 8 KB, and its content-based signature is a 20-byte signature generated using the SHA1 secure hashing algorithm. Also, each page has a LUN identifier and an offset, and so is characterized by &lt;lun_id, offset, signature&gt;. 
     The content-based signature in the present example comprises a content-based digest of the corresponding data page. Such a content-based digest is more particularly referred to as a “hash digest” of the corresponding data page, as the content-based signature is illustratively generated by applying a hash function such as the SHA1 secure hashing algorithm to the content of that data page. The full hash digest of a given data page is given by the above-noted 20-byte signature. The hash digest may be represented by a corresponding “hash handle,” which in some cases may comprise a particular portion of the hash digest. The hash handle illustratively maps on a one-to-one basis to the corresponding full hash digest within a designated cluster boundary or other specified storage resource boundary of a given storage system. In arrangements of this type, the hash handle provides a lightweight mechanism for uniquely identifying the corresponding full hash digest and its associated data page within the specified storage resource boundary. The hash digest and hash handle are both considered examples of “content-based signatures” as that term is broadly used herein. 
     Examples of techniques for generating and processing hash handles for respective hash digests of respective data pages are disclosed in U.S. Pat. No. 9,208,162, entitled “Generating a Short Hash Handle,” and U.S. Pat. No. 9,286,003, entitled “Method and Apparatus for Creating a Short Hash Handle Highly Correlated with a Globally-Unique Hash Signature,” both of which are incorporated by reference herein. 
     The storage controller  108  in this example is configured to group consecutive pages into page groups, to arrange the page groups into slices, and to assign the slices to different ones of the control modules  108 C. For example, if there are 1024 slices distributed evenly across the control modules  108 C, and there are a total of 16 control modules in a given implementation, each of the control modules “owns” 1024/16=64 slices. In such arrangements, different ones of the slices are assigned to different ones of the control modules  108 C such that control of the slices within the storage controller  108  of the CAS system  102  is substantially evenly distributed over the control modules  108 C of the storage controller  108 . 
     The data modules  108 D allow a user to locate a given user data page based on its signature. Each metadata page also has a size of 8 KB and includes multiple instances of the &lt;lun_id, offset, signature&gt; for respective ones of a plurality of the user data pages  112 . Such metadata pages  110  are illustratively generated by the control modules  108 C but are accessed using the data modules  108 D based on a metadata page signature. 
     The metadata page signature in this embodiment is a 20-byte signature but is not based on the content of the metadata page. Instead, the metadata page signature is generated based on an 8-byte metadata page identifier that is a function of the LUN identifier and offset information of that metadata page. 
     If a user wants to read a user data page having a particular LUN identifier and offset, the corresponding metadata page identifier is first determined, then the metadata page signature is computed for the identified metadata page, and then the metadata page is read using the computed signature. In this embodiment, the metadata page signature is more particularly computed using a signature generation algorithm that generates the signature to include a hash of the 8-byte metadata page identifier, one or more ASCII codes for particular predetermined characters, as well as possible additional fields. The last bit of the metadata page signature may always be set to a particular logic value so as to distinguish it from the user data page signature in which the last bit may always be set to the opposite logic value. 
     The metadata page signature is used to retrieve the metadata page via the data module. This metadata page will include the &lt;lun_id, offset, signature&gt; for the user data page if the user page exists. The signature of the user data page is then used to retrieve that user data page, also via the data module. 
     Write requests processed in the CAS system  102  each illustratively comprise one or more IO operations directing that at least one data item of the CAS system  102  be written to in a particular manner. A given write request is illustratively received in the CAS system  102  from one of the host device  101  over network  104 . In some embodiments, a write request is received in the distributed storage controller  108  of the CAS system  102 , and directed from one processing module to another processing module of the distributed storage controller  108 . For example, a received write request may be directed from a routing module  108 R of the distributed storage controller  108  to a particular control module  108 C of the distributed storage controller  108 . Other arrangements for receiving and processing write requests from one or more of the host devices  101  can be used. 
     The term “write request” as used herein is intended to be broadly construed, so as to encompass one or more IO operations directing that at least one data item of a storage system be written to in a particular manner. A given write request is illustratively received in a storage system from a host device. 
     In some embodiments, the control modules  108 C, data modules  108 D and routing modules  108 R of the storage nodes  115  communicate with one another over a high-speed internal network such as an InfiniBand network. The control modules  108 C, data modules  108 D and routing modules  108 R coordinate with one another to accomplish various IO processing tasks, as described elsewhere herein. 
     The write requests from the host devices identify particular data pages to be written in the CAS system  102  by their corresponding logical addresses each comprising a LUN ID and an offset. 
     As noted above, a given one of the content-based signatures illustratively comprises a hash digest of the corresponding data page, with the hash digest being generated by applying a hash function to the content of that data page. The hash digest may be uniquely represented within a given storage resource boundary by a corresponding hash handle. 
     The CAS system  102  illustratively utilizes a two-level mapping process to map logical block addresses to physical block addresses. In some embodiments, the first level of mapping uses an A2H table and the second level of mapping uses an HMD table, with the A2H and HMD tables corresponding to respective logical and physical layers of the content-based signature mapping within the CAS system  102 . The HMD table or a given portion thereof in some embodiments disclosed herein is more particularly referred to as an H2D table or H2P table, although it is to be understood that these and other mapping tables or other data structures referred to herein can be varied in other embodiments. 
     The first level of mapping using the A2H table associates logical addresses of respective data pages with respective content-based signatures of those data pages. This is also referred to as logical layer mapping. 
     The second level of mapping using the HMD table associates respective ones of the content-based signatures with respective physical storage locations in one or more of the storage devices  106 . This is also referred to as physical layer mapping. 
     Examples of these and other metadata structures utilized in illustrative embodiments were described elsewhere herein. These particular examples illustratively include respective A2H, H2D, HMD and PLB tables. In some embodiments, the A2H and H2D tables are utilized primarily by the control modules  108 C, while the HMD and PLB tables are utilized primarily by the data modules  108 D. 
     For a given write request, hash metadata comprising at least a subset of the above-noted tables is updated in conjunction with the processing of that write request. 
     The A2H, H2D, HMD and PLB tables described above are examples of what are more generally referred to herein as “mapping tables” of respective distinct types. Other types and arrangements of mapping tables or other content-based signature mapping information may be used in other embodiments. 
     Such mapping tables are still more generally referred to herein as “metadata structures” of the CAS system  102 . It should be noted that additional or alternative metadata structures can be used in other embodiments. References herein to particular tables of particular types, such as A2H, H2D, HMD and PLB tables, and their respective configurations, should be considered non-limiting and are presented by way of illustrative example only. Such metadata structures can be implemented in numerous alternative configurations with different arrangements of fields and entries in other embodiments. 
     The logical block addresses or LBAs of a logical layer of the CAS system  102  correspond to respective physical blocks of a physical layer of the CAS system  102 . The user data pages of the logical layer are organized by LBA and have reference via respective content-based signatures to particular physical blocks of the physical layer. 
     Each of the physical blocks has an associated reference count that is maintained within the CAS system  102 . The reference count for a given physical block indicates the number of logical blocks that point to that same physical block. 
     In releasing logical address space in the storage system, a dereferencing operation is generally executed for each of the LBAs being released. More particularly, the reference count of the corresponding physical block is decremented. A reference count of zero indicates that there are no longer any logical blocks that reference the corresponding physical block, and so that physical block can be released. 
     It should also be understood that the particular arrangement of storage controller processing modules  108 C,  108 D,  108 R and  108 M as shown in the  FIG.  1    embodiment is presented by way of example only. Numerous alternative arrangements of processing modules of a distributed storage controller may be used to implement functionality for recovery flow with reduced address lock contention in a CAS system in a clustered storage system or other type of distributed storage system in other embodiments. 
     Additional examples of content addressable storage functionality implemented in some embodiments by control modules  108 C, data modules  108 D, routing modules  108 R and management module(s)  108 M of distributed storage controller  108  can be found in U.S. Pat. No. 9,104,326, entitled “Scalable Block Data Storage Using Content Addressing,” which is incorporated by reference herein. Alternative arrangements of these and other storage node processing modules of a distributed storage controller in a CAS system can be used in other embodiments. 
     As indicated above, the CAS system  102  illustratively comprises storage nodes  115  interconnected in a mesh network, with each such storage node comprising a set of processing modules configured communicate with corresponding sets of processing modules on other ones of the storage nodes. A given such set of processing modules comprises at least a routing module, a control module and a data module, with the sets of processing modules of the storage nodes  115  of the CAS system  102  collectively comprising at least a portion of the storage controller  108  of the CAS system  102 . 
     The storage nodes  115  and their respective sets of processing modules are managed by a system manager, illustratively implemented as a management module  108 M within the set of processing modules on at least one of the storage nodes  115 . Each storage node  115  illustratively comprises a CPU or other type of processor, a memory, a network interface card (NIC) or other type of network interface, and a subset of the storage devices  106 , possibly arranged as part of a disk array enclosure (DAE) of the storage node. These and other references to “disks” herein are intended to refer generally to storage devices, including SSDs, and should therefore not be viewed as limited in any way to spinning magnetic media. 
     An example of the operation of the CAS system  102  in processing IO operations will now be described with reference to  FIG.  2   , which shows the relationship between routing, control and data modules of one possible distributed implementation of CAS system  102  in an illustrative embodiment. More particularly,  FIG.  2    illustrates a portion  200  of the CAS system  102 , showing a routing module  108 R-x, a control module  108 C-y and a data module  108 D-z in a distributed implementation of the storage controller  108 . The routing module  108 R-x, the control module  108 C-y and the data module  108 D-z are also denoted in this embodiment as an R-module, a C-module and a D-module, respectively. 
     These modules are respective processing modules of the storage controller  108 , and are potentially located on different ones of the storage nodes  115  of the distributed CAS system  102 . For example, each of the storage nodes  115  of the distributed CAS system  102  illustratively comprises at least one R-module, at least one C-module and at least one D-module, although many other storage node configurations are possible. In the present embodiment, the routing module  108 R-x, the control module  108 C-y and the data module  108 D-z are assumed to be on respective different storage nodes x, y and z of the distributed CAS system  102 . The storage nodes x, y and z represent respective particular ones of the storage nodes  115 . The storage node z that implements the D-module  108 D-z comprises a subset of the storage devices  106  of the distributed CAS system  102 , with the subset of storage devices  106  on storage node z being denoted as storage devices  106 - z . Each of the other storage nodes  115  of the distributed CAS system  102  similarly has a different subset of the storage devices  106  associated therewith. 
     It is assumed in this example that the distributed CAS system  102  manages data using a fixed-size page granularity (e.g., 4 KB, 8 KB or 16 KB), also referred to herein as the native page size of the distributed CAS system  102 . A unique hash digest is computed for each of the data pages by a content-based signature generator, illustratively using SHA1 or another secure hashing algorithm of the type described elsewhere herein. 
     In the distributed CAS system  102 , routing modules  108 R such as R-module  108 R-x illustratively include a SCSI command parser as shown, although other command parsers for other storage protocols can be used in other embodiments. The routing modules  108 R receive IO requests from the host device  101 - 1 , parse the corresponding SCSI commands and route them to the appropriate control modules  108 C, which may be located on different storage nodes  115 , illustratively using an address-to-control (“A2C”) table. The A2C table maps different portions of a logical address space of the distributed CAS system  102  across different ones of the control modules  108 C. A given IO request can be sent by the host device  101 - 1  to any of the routing modules  108 R of the distributed CAS system  102 . 
     The control modules  108 C such as control module  108 C-y receive the IO requests from the routing modules  108 R, and use mapping tables such as the above-described A2H and H2D tables to identify the appropriate data modules  108 D that store the corresponding data pages in the distributed CAS system  102 . This illustratively includes performing a logical address to hash mapping as shown in the figure. 
     In processing read requests, the C-module  108 C-y retrieves from the A2H table the hash digests of the corresponding requested pages, and sends read requests to the appropriate data modules  108 D based on the H2D table. 
     In processing write requests, the C-module  108 C-y illustratively computes the hash digests of the data pages based on the write data, sends write requests to the corresponding data modules  108 D as determined from the H2D table, and updates the A2H table. Other aspects of processing write requests using write cache  116  and write cache journal  118  will be described below in conjunction with  FIG.  3   . 
     The data modules  108 D such as D-module  108 D-z are responsible for the physical storage of the data pages, and use mapping tables such as the above-described HMD and PLB tables and/or other types of H2P tables to determine the physical location of a given data page in the subset of storage devices  106  associated with that data module, using a hash digest, hash handle or other content-based signature supplied by a control module. This illustratively includes performing a hash to physical location mapping as shown in the figure. Such a hash to physical location mapping can utilize an H2P table of the type described elsewhere herein, illustratively comprising at least portions of the above-noted HMD and PLB tables. The data modules  108 D in some embodiments additionally store a copy or “mirror” of such metadata in a memory of the respective corresponding storage nodes  115 , in order to optimize performance by reducing accesses to the associated storage devices  106  during system operation. 
     The host device  101 - 1  illustratively sends an IO request to a particular one of the routing modules  108 R, possibly using random selection or another type of algorithm such as round robin to select a particular routing module for a particular IO request. Such selection can be implemented as part of a path selection algorithm performed by an MPIO driver of the host device  101 - 1 , in order to select a particular path comprising an initiator-target pair for delivery of the IO request to the CAS system  102 . 
     The particular example described above in conjunction with  FIG.  2    should not be construed as limiting in any way, and a wide variety of other implementations of the CAS system  102  are possible. 
     As indicated above, the processing of write requests in the CAS system  102  makes use of the write cache  116  and the write cache journal  118 , as will now be described in more detail with reference to  FIGS.  3 A,  3 B and  3 C . These figures show respective first, second and third stages in the processing of a write request, with the stages also being referred to herein as Stage 1, Stage 2 and Stage 3, respectively. 
     The write cache  116  illustratively comprises a volatile memory of the CAS system  102  for temporarily storing data pages associated with write requests received from the host device  101 - 1  or other ones of the host devices  101 . The write cache  116  is backed up by the write cache journal  118  that stores persisted copies of the write data. The write data of the write cache  116  is later “destaged” to a persistent data storage location in the storage devices  106 . For write requests received by the CAS system  102 , address locks are placed on corresponding data pages, illustratively by associated ones of the control modules  108 C, until the destaging of those data pages from the write cache  116  is completed. 
     As indicated previously herein, the clearing of such address locks can be unduly delayed in the presence of a storage node failure, such as a failure of a given one of the storage nodes  115  or a particular one of its processing modules, illustratively one of the data modules  102 D, with each such scenario being considered an example of a “storage node failure” as that term is broadly used herein. A given storage node failure therefore need not be a complete failure of an entire storage node, but could instead be a failure of one or more components of the storage node, while other components of the storage node remain operational. 
     Illustrative embodiments herein advantageously provide a recovery flow for dealing with such a storage node failure, which can accelerate the release of address locks in the presence of the storage node failure, thereby improving system performance. For example, some embodiments allow the write cache destaging process to be completed more quickly than would otherwise be possible in the presence of the storage node failure, so as to allow the address locks placed as part of the write cache destaging process to also be more quickly released, thereby reducing address lock contention in the CAS system  102 . 
     In the absence of a storage node failure, a given write request targeting a particular data page in the CAS system  102  is illustratively processed by one of the control modules  108 C and one of the data modules  108 D in accordance with the following multi-stage process, the primary steps of which correspond generally to Stage 1, Stage 2 and Stage 3 of respective  FIGS.  3 A,  3 B and  3 C : 
     1. Front-end write request processing by control module. This is a synchronous stage handled by a particular control module, initiated upon receipt of the write request from one of the routing modules  108 R. The data page is stored in an entry of the write cache  116  and persisted in the write cache journal  118 , and the write request is then acknowledged back to the host device. The A2H table entry corresponding to the logical address of the data page being written is updated to point to the entry of the data page in the write cache  116 . 
     2. Write cache destaging to data module. This is an asynchronous stage initiated by the control module to destage the data page to its appropriate destination data module. This stage more particularly implements an example write cache destaging process that includes the following steps:
         (a) Control module acquires address lock for data page;   (b) Control module sends destage request to data module;   (c) Data module loads associated metadata into RAM if not already loaded;   (d) Data module writes data page and associated metadata and replies to control module with the hash digest of the data page;   (e) Control module updates its A2H table to include the hash digest of the data page; and   (f) Control module releases address lock for data page.       

     3. Background destaging from data module to storage device. This is an asynchronous stage initiated by the data module that persists the data page to a storage device associated with the data module. The data module stores the data page in the storage device and then updates its H2P table to point to the corresponding physical location. 
     Referring now more particularly to the diagrams of  FIGS.  3 A,  3 B and  3 C , respective first, second and third stages of the above-described write request handling process are shown in more detail. Again, these stages are referred to elsewhere herein as Stage 1, Stage 2 and Stage 3, respectively. Other types and arrangements of write request processing stages can be used in other embodiments. 
       FIG.  3 A  shows a sequence diagram illustrating a first stage in the write request handling process, carried out by a given control module  108 C, also referred to in this example as control module  108 C-j or CM j . 
     At  300 , CM j  receives a write request from host device  101 - 1  over network  104 , via a particular one of the routing modules  108 R which is omitted from the figure for clarity and simplicity of illustration. 
     At  302 , CM j  writes the data associated with the received write request to the write cache  116 . For example, CM j  adds the data as a new entry in the write cache  116 , with the new entry being denoted as entry WC k . 
     At  304 , CM j  also writes the data associated with the received write request to the write cache journal  118 . The data may be written to the write cache  116  and the write cache journal  118  synchronously or asynchronously in any order. 
     At  306 , CM j  updates the A2H table for the logical address (“A”) associated with the write request to point to the entry in the write cache, e.g., A-&gt;WC k . 
     At  308 , CM j  sends an acknowledgement (“ACK”) of the write request back to the host device  101 - 1 . 
       FIG.  3 B  shows a sequence diagram illustrating a second stage in the write request handling process, carried out by control module CM j  and a given data module  108 D, also referred to in this example as data module  108 D-i or DM i . This second stage of the write request handling process is illustratively performed asynchronously with the first stage, but in other embodiments may be performed synchronously with the first stage. 
     At  310 , CM j  acquires an address lock on the data page targeted by the write request. 
     At  312 , CM j  sends a destage request to DM i . The address lock is therefore acquired prior to sending the destage request in this embodiment. 
     At  314 , DM i  fetches the data from the write cache  116  and saves it to a volatile memory associated with DM i , e.g., RAM or other volatile memory. 
     At  316 , DM i  adds an entry for the write cache entry, WC k , to a back-end destage list, which can be in the form of a table or other data structure. The back-end destage list illustratively comprises a plurality of entries for respective destage requests received by DM i  from respective ones of the control modules  108 C. A given such entry in the back-end destage list illustratively comprises a write cache entry field and a control module field, but may include additional or alternative information in other embodiments. The write cache entry field contains information that identifies the corresponding write cache entry. More particularly, the write cache entry field of the back-end destage list includes a value of WC k  indicating that this entry corresponds to the write cache entry WC k . The control module field in the back-end destage list data structure contains information that identifies the corresponding requesting control module CM j  for which the given entry has been added to the back-end destage list. 
     At  318 , DM i  calculates a content-based signature, illustratively a hash handle (“HH”), for the data. Other types of content-based signatures can be used in other embodiments, as described elsewhere herein. 
     At  320 , DM i  updates the H2P table for the calculated HH to point to the write cache entry, e.g., HH-&gt;WC k . 
     At  322 , DM i  replies to CM j  with the calculated HH. 
     At  324 , CM j  updates the A2H table for the logical address (“A”) associated with the write request to point to the HH, e.g., A-&gt;HH. 
     At  326 , CM j  releases the address lock that it previously acquired on the data page targeted by the write request. 
     The second stage as described above may be viewed an example of what is more generally referred to herein as a “write cache destaging process.” That term as broadly used herein can encompass other types of additional or alternative processing operations, and may include at least portions of one or more other stages. 
     At the completion of the second stage, the data associated with the write request is still not written to the storage devices  106 . The data is stored in the volatile memories of the write cache  116  (e.g., entry WC k ) and the data module DM i , and is persisted in the write cache journal  118  for backup and recovery purposes. 
       FIG.  3 C  shows a sequence diagram illustrating a third stage in the write request handling process, carried out by data module DM i . This third stage of the write request handling process is illustratively performed asynchronously with the first and second stages, but in other embodiments may be performed synchronously with one or both of the other stages. 
     At  330 , DM i  persists the data to the storage devices  106 , e.g., by writing the data to a physical address on the storage devices  106  based on the content-based signature or in another manner. 
     At  332 , DM i  updates the H2P table for the calculated HH to point to the corresponding physical address at which the data has been stored, e.g., HH-&gt;Physical Address. 
     At  334 , DM i  removes the entry previously created in the back-end destage list for write cache entry WC k  and destage requester CM j . 
     At the completion of the third stage, the data is persisted in the storage devices  106  so the corresponding write cache entry and its write cache journal entry are no longer needed, and can be deleted. 
     As indicated previously, the above-described multi-stage process for handling a given write request is performed in the absence of a storage node failure. 
     If a storage node failure were to occur, the CAS system  102  is illustratively configured to implement a recovery flow of the type disclosed herein, with reduced address lock contention using write cache metadata preload commands. 
     Without such a recovery flow, certain types of failures can lead to excessive address lock contention in conjunction with write cache destaging. For example, assume that the detected failure is a failure of a particular one of the data modules  108 D on one of the storage nodes  115 . The data module after replacement and/or restart will initiate a lengthy loading process in which it loads its metadata including its H2P table into memory. 
     During that time, the data module will still need to service write cache destage requests received from the control modules. However, since the relevant metadata may not yet be loaded into memory, the data module will have to continue the loading process, which can significantly increase the destaging time relative to that which would normally be required absent the failure. Moreover, the control modules have acquired address locks on the data pages to be destaged, which prevents other IO operations from accessing those data pages until the write cache destaging process is complete and the address locks have been released. This causes increased levels of address lock contention and associated adverse impacts on system performance. The problem is further aggravated because the write cache destaging process typically operates on a batch of data pages, so all destaged data pages must wait for all the metadata loads of all data pages in the batch before the write cache destaging process can be completed. 
     These and other problems are overcome in illustrative embodiments by using a recovery flow with reduced address lock contention as disclosed herein. 
     In implementing functionality for recovery flow with reduced address lock contention, the storage controller  108  of CAS system  102  is configured to detect a failure of at least one of the storage nodes  115  that impacts a destaging process of the write cache  116  in the CAS system  102 , and responsive to the detected failure, to issue one or more write cache metadata preload commands to direct one or more other ones of the storage nodes  115  to preload from their associated storage devices  106  metadata characterizing one or more data pages that are subject to the write cache destaging process. 
     As indicated above, the detected failure can comprise, for example, a complete failure of a given one of the storage nodes  115 , or a failure of a particular component of a given one of the storage nodes  115 , such as a failure of a data module  108 D of that storage node. A wide variety of other types of failures can be detected in other embodiments and used to trigger issuance of write cache metadata preload commands as disclosed herein. 
     As indicated previously, address locks are placed on respective ones of a plurality of data pages targeted by one or more write requests to be destaged from the write cache  116  of the CAS system  102  as part of the write cache destaging process. For example, the control modules  108 R are illustratively configured to place address locks on data pages that are targeted by respective write requests currently in the process of being destaged from the write cache  116 . The address lock for a given page remains in place until the destaging of its corresponding write request from the write cache  116  is completed. 
     Detecting a failure of at least one of the storage nodes  115  that impacts the write cache destaging process in some embodiments more particularly comprises detecting a failure of a data module  108 D of a particular storage node that is associated with one or more storage devices  106  that store one or more data pages targeted by one or more write requests to be destaged from the write cache  116  as part of the write cache destaging process. The failure is illustratively detected prior to acquisition of the address locks. For example, the failure may be detected prior to initiation of the write cache destaging process, where the address locks are acquired as part of the write cache destaging process. In these and other embodiments, each of the one or more write cache metadata preload commands is illustratively issued as part of or otherwise in conjunction with an initial step of the write cache destaging process. 
     Each of the one or more write cache metadata preload commands illustratively comprises a corresponding RPC, although other types of command formats can be used in other embodiments. 
     In some embodiments, issuing one or more write cache metadata preload commands to direct one or more other ones of the storage nodes  115  to preload from their associated storage devices  106  metadata characterizing one or more data pages that are subject to the write cache destaging process more particularly comprises issuing the one or more write cache metadata preload commands from a first one of the storage nodes  115  to at least a second one of the storage nodes  115 . For example, a plurality of write cache metadata preload commands may be issued from a control module  108 R of the first storage node to respective ones of a plurality of data modules  108 D of respective ones of the second storage node and one or more additional ones of the storage nodes. 
     Additionally or alternatively, issuing one or more write cache metadata preload commands to direct one or more other ones of the storage nodes  115  to preload from their associated storage devices  106  metadata characterizing one or more data pages that are subject to the write cache destaging process illustratively comprises issuing multiple write cache metadata preload commands to respective ones of a plurality of data modules  108 D that are associated with a designated write cache destage batch of the write cache destaging process. The write cache destage batch illustratively comprises a set of write requests targeting particular data pages that are accessible via the associated data modules  108 D. 
     In some embodiments, the write cache destaging process is delayed until each of the one or more write cache metadata preload commands issued for a designated write cache destage batch is acknowledged as complete. 
     These and other operations associated with recovery flow with reduced address lock contention in the CAS system  102  are illustratively performed at least in part by or under the control of the storage controller  108  and at least a subset of its processing modules  108 C,  108 D,  108 R and  108 M. 
     As a more particular example, a given one of the control modules  108 R prior to taking the address lock of the data page in step (a) of the write cache destaging process outlined above will perform the following operations: 
     1. The control module issues write cache metadata preload commands via RPCs to each of the data modules  108 D that are part of the write cache destage batch. The write cache metadata preload commands provide an instruction to these data modules that a write cache destaging process is imminent, and that the relevant metadata to be used in that process should therefore be loaded immediately. The write cache metadata preload commands in this embodiment are issued only as part of a recovery flow in conjunction with a detected storage node failure, and therefore will not adversely impact other IO requests attempting the access the data page in the absence of such a storage node failure. 
     2. After all of the write cache metadata preload commands are acknowledged as complete by their respective data modules, the write cache destaging process can continue in the manner previously described, with the control module acquiring address lock for the data page in step (a) of the write cache destaging process. 
     It is to be appreciated that these operations are only an example, and can be varied in other embodiments. Also, other types of write cache destaging processes with different arrangements of steps can be used. 
     The above-described embodiments advantageously decouple the write cache destaging process from the data module metadata loading, by directing the data modules to preload the metadata before the address locks are taken by the control modules as part of the write cache destaging process. 
     As a result, the address locks placed in conjunction with the write cache destaging process do not interfere with the metadata preloading of the data modules, and address lock contention is thereby reduced. For example, in some embodiments, address lock contention during the recovery flow is reduced to substantially the same level that is experienced during normal operation without any storage node failure. Accordingly, IO processing latency in the CAS system  102  is not adversely impacted by long waits for release of address locks, and timeouts of IO requests are avoided. 
     The CAS system  102  in the  FIG.  1    embodiment is assumed to be implemented using at least one processing platform, with each such processing platform comprising one or more processing devices, and each such processing device comprising a processor coupled to a memory. Such processing devices can illustratively include particular arrangements of compute, storage and network resources. 
     As indicated previously, the host device  101 - 1  and possibly the other host devices  101 - 2  through  101 -N may be implemented in whole or in part on the same processing platform as the CAS system  102  or on a separate processing platform. 
     The term “processing platform” as used herein is intended to be broadly construed so as to encompass, by way of illustration and without limitation, multiple sets of processing devices and associated storage systems that are configured to communicate over one or more networks. For example, distributed implementations of the system  100  are possible, in which certain components of the system reside in one data center in a first geographic location while other components of the system reside in one or more other data centers in one or more other geographic locations that are potentially remote from the first geographic location. Thus, it is possible in some implementations of the system  100  for the host device  101 - 1  and the CAS system  102  to reside in different data centers. Numerous other distributed implementations of the host device  101 - 1  and the CAS system  102  are possible. 
     Additional examples of processing platforms utilized to implement host devices  101  and CAS system  102  in illustrative embodiments will be described in more detail below in conjunction with  FIGS.  5  and  6   . 
     It is to be appreciated that these and other features of illustrative embodiments are presented by way of example only, and should not be construed as limiting in any way. 
     Accordingly, different numbers, types and arrangements of system components such as host devices  101 , CAS system  102 , network  104 , storage devices  106 , storage controller  108 , write cache  116 , write cache journal  118 , processor  120  and memory  122  can be used in other embodiments. 
     It should be understood that the particular sets of modules and other components implemented in the system  100  as illustrated in  FIGS.  1  through  3    are presented by way of example only. In other embodiments, only subsets of these components, or additional or alternative sets of components, may be used, and such components may exhibit alternative functionality and configurations. 
     The operation of the information processing system  100  will now be described in further detail with reference to the flow diagram of the illustrative embodiment of  FIG.  4   , which implements a process for recovery flow with reduced address lock contention in a CAS system. The process may be viewed as an example of an algorithm implemented at least in part by the storage controller  108  and its processing modules  108 C,  108 D,  108 R and  108 M distributed over the storage nodes  115  of CAS system  102 . For example, such an algorithm is illustratively carried out by one or more instances of recovery flow logic of the storage controller  108 . 
     The process as illustrated in  FIG.  4    includes steps  400  through  410 , and is described in the context of CAS system  102  but is more generally applicable to a wide variety of other types of information processing systems each comprising at least one host device and at least one CAS system. 
     In step  400 , a write request is received in the CAS system  102 . For example, the write request is illustratively received by one of the routing modules  108 R from the host device  101 - 1  and sent by the receiving routing module  108 R to a particular one of the control modules  108 C for further processing. It should once again be noted that Stage 1 of the write request processing as illustrated in  FIG.  3 A  omits the routing module for clarity and simplicity of illustration. The write request illustratively originates from an application process executing on the processor  120  of the host device  101 - 1 . 
     In step  402 , a determination is made as to whether or not a storage node failure is detected. Examples of storage node failures were described above, and include, by way of example, a failure of an entire storage node or a failure of a data module of a storage node. Multiple storage node failures can also be detected in this step. If a storage node failure has been detected, the process moves to step  404 , and otherwise moves to step  406  as shown. 
     In step  404 , Stage 1 of the write request processing as shown in  FIG.  3 A  is performed, less receipt of the write request in step  300  which in this illustrative embodiment is received in step  400 . Other references to Stage 1 in this embodiment are similarly assumed to begin with the processing operations of a control module following its initial receipt of the write request. The process then continues with steps  408  and  410  as part of a recovery flow with reduced address lock contention as disclosed herein. 
     In step  406 , Stages 1, 2 and 3 of the write request processing as shown in respective  FIGS.  3 A,  3 B and  3 C  are performed. This is the normal processing performed for write requests in the absence of a storage node failure, and therefore outside of the recovery flow with reduced address lock contention. The process then returns to step  400  as shown in order to process another write request. 
     In step  408 , write cache metadata preload commands are sent to any data modules impacted by the detected storage node failure. For example, such write cache metadata preload commands are illustratively sent by the control module that is processing the write request to each of a plurality of data modules that are impacted by a write cache destaging process. This may include all data modules that are part of a given write cache destage batch. 
     In step  410 , Stages 2 and 3 of the write request processing as shown in respective  FIGS.  3 B and  3 C  are performed in the normal way, with acquisition of address lock at the beginning of Stage 2 and release of address lock at the end of Stage 2. The process then returns to step  400  as shown in order to process another write request. 
     It should be noted that steps  400  through  410  are iterated for respective ones of multiple write operations, and different portions of the process can overlap with other portions of the process, possibly across the different iterations. For example, additional iterations of some of the steps can be initiated while previous iterations of other ones of the steps are still in progress. Accordingly, the steps are shown in sequential order for clarity and simplicity of illustration only, and certain steps can at least partially overlap with other steps. 
     The particular processing operations and other system functionality described in conjunction with the flow diagram of  FIG.  4    are presented by way of illustrative example only, and should not be construed as limiting the scope of the disclosure in any way. Alternative embodiments can use other types of processing operations for recovery flow with reduced address lock contention in a CAS system. For example, as indicated above, the ordering of the process steps may be varied in other embodiments, or certain steps may be performed at least in part concurrently with one another rather than serially. Also, one or more of the process steps may be repeated periodically, or multiple instances of the process can be performed in parallel with one another in order to implement a plurality of different recovery flow processes for respective different distributed CAS systems or portions thereof within a given information processing system. 
     Functionality such as that described in conjunction with the flow diagram of  FIG.  4    can be implemented at least in part in the form of one or more software programs stored in memory and executed by a processor of a processing device such as a computer or server. As will be described below, a memory or other storage device having executable program code of one or more software programs embodied therein is an example of what is more generally referred to herein as a “processor-readable storage medium.” 
     For example, a storage controller such as storage controller  108  in CAS system  102  that is configured to perform the steps of the  FIG.  4    process can be implemented as part of what is more generally referred to herein as a processing platform comprising one or more processing devices each comprising a processor coupled to a memory. 
     A given such processing device may correspond to one or more virtual machines or other types of virtualization infrastructure such as Docker containers or Linux containers (LXCs). The host devices  101 , storage controller  108 , as well as other system components, may be implemented at least in part using processing devices of such processing platforms. For example, respective distributed modules of storage controller  108  can be implemented in respective containers running on respective ones of the processing devices of a processing platform. 
     Accordingly, the storage controller  108  is configured to support functionality for recovery flow with reduced address lock contention of the type previously described in conjunction with  FIGS.  1  through  4   . For example, recovery flow logic instances implemented on respective ones of the control modules  108 C are configured to control performance of a process such as that shown in  FIG.  4   , in order to achieve recovery flow with reduced address lock contention in the CAS system  102 . 
     Illustrative embodiments of a storage system with functionality for recovery flow with reduced address lock contention in a CAS system as disclosed herein can provide a number of significant advantages relative to conventional arrangements. 
     For example, these embodiments advantageously accelerate the release of address locks in the presence of a storage node failure, relative to the undue delay in address lock release that might otherwise occur absent use of the techniques disclosed herein, thereby improving system performance. 
     Some embodiments advantageously decouple a write cache destaging process from the data module metadata loading, by directing the data modules to preload the metadata before the address locks are taken by the control modules as part of the write cache destaging process. 
     As a result, the address locks placed in conjunction with the write cache destaging process do not interfere with the metadata preloading of the data modules, and address lock contention is thereby substantially reduced. 
     For example, in some embodiments, address lock contention during the recovery flow is reduced to substantially the same level that is experienced during normal operation without any storage node failure. 
     Accordingly, IO processing latency in illustrative embodiments is not adversely impacted by long waits for release of address locks, and timeouts of IO requests are avoided. 
     It is to be appreciated that the particular advantages described above and elsewhere herein are associated with particular illustrative embodiments and need not be present in other embodiments. Also, the particular types of information processing system features and functionality as illustrated in the drawings and described above are exemplary only, and numerous other arrangements may be used in other embodiments. 
     Illustrative embodiments of processing platforms utilized to implement host devices and storage systems with functionality for recovery flow with reduced address lock contention in a CAS system will now be described in greater detail with reference to  FIGS.  5  and  6   . Although described in the context of system  100 , these platforms may also be used to implement at least portions of other information processing systems in other embodiments. 
       FIG.  5    shows an example processing platform comprising cloud infrastructure  500 . The cloud infrastructure  500  comprises a combination of physical and virtual processing resources that may be utilized to implement at least a portion of the information processing system  100 . The cloud infrastructure  500  comprises multiple virtual machines (VMs) and/or container sets  502 - 1 ,  502 - 2 , . . .  502 -L implemented using virtualization infrastructure  504 . The virtualization infrastructure  504  runs on physical infrastructure  505 , and illustratively comprises one or more hypervisors and/or operating system level virtualization infrastructure. The operating system level virtualization infrastructure illustratively comprises kernel control groups of a Linux operating system or other type of operating system. 
     The cloud infrastructure  500  further comprises sets of applications  510 - 1 ,  510 - 2 , . . .  510 -L running on respective ones of the VMs/container sets  502 - 1 ,  502 - 2 , . . .  502 -L under the control of the virtualization infrastructure  504 . The VMs/container sets  502  may comprise respective VMs, respective sets of one or more containers, or respective sets of one or more containers running in VMs. 
     In some implementations of the  FIG.  5    embodiment, the VMs/container sets  502  comprise respective VMs implemented using virtualization infrastructure  504  that comprises at least one hypervisor. Such implementations can provide functionality for recovery flow with reduced address lock contention in a CAS system of the type described above using one or more processes running on a given one of the VMs. For example, each of the VMs can implement recovery flow logic instances and/or other components for implementing functionality for recovery flow with reduced address lock contention in the CAS system  102 . 
     A hypervisor platform may be used to implement a hypervisor within the virtualization infrastructure  504 . Such a hypervisor platform may comprise an associated virtual infrastructure management system. The underlying physical machines may comprise one or more distributed processing platforms that include one or more storage systems. 
     In other implementations of the  FIG.  5    embodiment, the VMs/container sets  502  comprise respective containers implemented using virtualization infrastructure  504  that provides operating system level virtualization functionality, such as support for Docker containers running on bare metal hosts, or Docker containers running on VMs. The containers are illustratively implemented using respective kernel control groups of the operating system. Such implementations can also provide functionality for recovery flow with reduced address lock contention in a CAS system of the type described above. For example, a container host device supporting multiple containers of one or more container sets can implement one or more instances of recovery flow logic and/or other components for implementing functionality for recovery flow with reduced address lock contention in the CAS system  102 . 
     As is apparent from the above, one or more of the processing modules or other components of system  100  may each run on a computer, server, storage device or other processing platform element. A given such element may be viewed as an example of what is more generally referred to herein as a “processing device.” The cloud infrastructure  500  shown in  FIG.  5    may represent at least a portion of one processing platform. Another example of such a processing platform is processing platform  600  shown in  FIG.  6   . 
     The processing platform  600  in this embodiment comprises a portion of system  100  and includes a plurality of processing devices, denoted  602 - 1 ,  602 - 2 ,  602 - 3 , . . .  602 -K, which communicate with one another over a network  604 . 
     The network  604  may comprise any type of network, including by way of example a global computer network such as the Internet, a WAN, a LAN, a satellite network, a telephone or cable network, a cellular network, a wireless network such as a WiFi or WiMAX network, or various portions or combinations of these and other types of networks. 
     The processing device  602 - 1  in the processing platform  600  comprises a processor  610  coupled to a memory  612 . 
     The processor  610  may comprise a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), graphics processing unit (GPU) or other type of processing circuitry, as well as portions or combinations of such circuitry elements. 
     The memory  612  may comprise random access memory (RAM), read-only memory (ROM), flash memory or other types of memory, in any combination. The memory  612  and other memories disclosed herein should be viewed as illustrative examples of what are more generally referred to as “processor-readable storage media” storing executable program code of one or more software programs. 
     Articles of manufacture comprising such processor-readable storage media are considered illustrative embodiments. A given such article of manufacture may comprise, for example, a storage array, a storage disk or an integrated circuit containing RAM, ROM, flash memory or other electronic memory, or any of a wide variety of other types of computer program products. The term “article of manufacture” as used herein should be understood to exclude transitory, propagating signals. Numerous other types of computer program products comprising processor-readable storage media can be used. 
     Also included in the processing device  602 - 1  is network interface circuitry  614 , which is used to interface the processing device with the network  604  and other system components, and may comprise conventional transceivers. 
     The other processing devices  602  of the processing platform  600  are assumed to be configured in a manner similar to that shown for processing device  602 - 1  in the figure. 
     Again, the particular processing platform  600  shown in the figure is presented by way of example only, and system  100  may include additional or alternative processing platforms, as well as numerous distinct processing platforms in any combination, with each such platform comprising one or more computers, servers, storage devices or other processing devices. 
     For example, other processing platforms used to implement illustrative embodiments can comprise converged infrastructure such as VxRail™, VxRack™, VxRack™ FLEX, VxBlock™ or Vblock® converged infrastructure from Dell EMC. 
     It should therefore be understood that in other embodiments different arrangements of additional or alternative elements may be used. At least a subset of these elements may be collectively implemented on a common processing platform, or each such element may be implemented on a separate processing platform. 
     As indicated previously, components of an information processing system as disclosed herein can be implemented at least in part in the form of one or more software programs stored in memory and executed by a processor of a processing device. For example, at least portions of the functionality for recovery flow with reduced address lock contention provided by one or more components of a storage system as disclosed herein are illustratively implemented in the form of software running on one or more processing devices. 
     It should again be emphasized that the above-described embodiments are presented for purposes of illustration only. Many variations and other alternative embodiments may be used. For example, the disclosed techniques are applicable to a wide variety of other types of information processing systems, host devices, storage systems, storage nodes, storage devices, storage controllers, write caches, write cache journals, recovery flow logic instances and other components. Also, the particular configurations of system and device elements and associated processing operations illustratively shown in the drawings can be varied in other embodiments. Moreover, the various assumptions made above in the course of describing the illustrative embodiments should also be viewed as exemplary rather than as requirements or limitations of the disclosure. Numerous other alternative embodiments within the scope of the appended claims will be readily apparent to those skilled in the art.