Patent Publication Number: US-2023161109-A1

Title: Communication systems having co-packaged optical modules

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to U.S. provisional patent application 63/245,005 filed on Sep. 16, 2021, the entire content of which is herein incorporated by reference. 
    
    
     TECHNICAL FIELD 
     This document describes communication systems having co-packaged optical modules. 
     BACKGROUND 
     This section introduces aspects that can help facilitate a better understanding of the disclosure. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is in the prior art or what is not in the prior art. 
     As the input/output (I/O) capacities of electronic processing chips increase, electrical signals may not provide sufficient input/output capacity across the limited size of a practically viable electronic chip package. An alternative may be to interconnect electronic chip packages using optical signals. 
     SUMMARY OF THE INVENTION 
     In a general aspect, an apparatus includes a first substrate, a socket coupled to the first substrate, a support structure coupled to the first substrate and defining an opening, and an interface module. The interface module can be inserted through the opening in the support structure and removably coupled to the socket, and can include a photonic integrated circuit that is configured to perform at least one of (i) receive optical signals and generate electrical signals based on the received optical signals, or (ii) receive electrical signals and generate optical signals based on the received electrical signals. The apparatus includes a plurality of optical fiber cables, in which a portion of the optical fiber cables extend from the interface module in the direction that is substantially orthogonal to the first substrate. 
     In some implementations, the apparatus includes a compression plate movable between a first position and a second position, in which when the compression plate is in the first position, the compression plate is configured to apply a force to the interface module to press the interface module against the socket, and when the compression plate is in the second position, the compression plate is configured to reduce the force applied to the interface module as compared to when the compression plate is in the first position. The apparatus also includes a fastening device configured to operate in at least one of a first state or a second state, in which when the fastening device is in the first state, the fastening device is configured to secure the compression plate in the first position relative to the support structure, and when the fastening device is in the second state, the fastening device is configured to release the compression plate from the first position and allow the compression plate to move from the first position to the second position. 
     Implementations can include one or more of the following features. The compression plate includes a first surface, a second surface, and an edge between the first and second surfaces. When the compression plate is in the first position, the first surface faces the interface module and the second surface faces away from the interface module, the one or more holes in the compression plate extend between the first surface and the second surface, the one or more holes have one or more openings at the edge of the compression plate. The bolt is configured to be inserted into the one or more holes of the compression plate through the one or more openings at the edge of the compression plate. 
     In some implementations, the bolt includes a U-shaped bolt, the compression plate includes a set of two holes, the support structure includes a set of two holes, and the U-shaped bolt includes two legs that are configured to be inserted into the set of two holes in the support structure and the set of two holes in the compression plate to secure the compression plate at the first position relative to the support structure. 
     In an aspect, the fastening device includes one or more screws that are configured to be inserted into one or more screw holes in the support structure and one or more screw holes in the compression plate to secure the compression plate at the first position relative to the support structure. 
     In an aspect, the support structure includes a lattice structure defining a plurality of openings to allow a plurality of interface modules to pass through the openings and be removably coupled to a plurality of sockets. In some implementations, the apparatus includes a data processor transmitting electrical signals between the data processor and plurality of interface modules 
     In some examples, the apparatus includes a wave spring positioned between the compression plate and the interface module. The apparatus includes a thermal bridge material positioned between the compression plate and the interface module. The socket includes compression interposes. The apparatus includes an optical cable optically coupled to the photonic integrated circuit, in which the compression plate defines an opening that allows the optical cable to pass through. 
     The apparatus includes a data processor electrically coupled to the first substrate; wherein the photonic integrated circuit is configured to perform at least one of (i) receive optical signals, generate electrical signals based on the received optical signals, and transmit the electrical signals to the data processor, or (ii) receive electrical signals from the data processor, generate optical signals based on the electrical signals, and output the optical signals. The data processor includes data processor is mounted on the first substrate. In some implementations, the data processor is mounted on a second substrate that is electrically coupled to the first substrate. In some implementations, the first substrate and the second substrate are electrically coupled to a printed circuit board, and the first substrate is electrically coupled to the second substrate through electrical signal lines on or in the printed circuit board. In some implementations, the apparatus includes a housing having a front panel, in which the first substrate is placed in the housing and positioned behind the front panel, and the first substrate has a main surface that is oriented at an angle in a range of 0 to 45 degrees relative to the front panel. In some implementations, the first substrate is oriented parallel to the front panel. 
     In some implementations, the apparatus includes a plurality of first substrates, a plurality of sockets, each socket being coupled to a corresponding first substrate. The support structure includes a lattice structure having a plurality of openings defining a plurality of openings, each opening corresponding to one of the sockets. The apparatus includes a plurality of interface modules, in which each interface module includes a photonic integrated circuit, each interface module is inserted through a corresponding opening in the lattice structure and removably coupled to a corresponding socket. The apparatus includes a plurality of compression plates, in which each compression plate when in a first position is configured to apply a force to a corresponding interface module to press the interface module against a corresponding socket 
     The apparatus includes one or more data processors electrically coupled to the plurality of first substrates; wherein the photonic integrated circuits are configured to receive optical signals, generate electrical signals based on the received optical signals, and transmit the electrical signals to the one or more data processors. In some examples, each of the one or more data processors includes at least one of a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, an application specific integrated circuit (ASIC), or a storage device. 
     In some examples, the interface module of the apparatus includes a second substrate having a first set of electrical contacts on a first surface and a second set of electrical contacts on a second surface, the co-packaged optical module includes a photonic integrated circuit having a set of electrical contacts, and the socket includes a set of electrical contacts. In some examples, the first set of electrical contacts on the first surface of the second substrate are electrically coupled to the electrical contacts of the photonic integrated circuit, and the second set of electrical contacts on the second surface of the second substrate are electrically coupled to the electrical contacts of the socket. In some implementations, the first set of electrical contacts on the first surface of the second substrate has a higher packing density than the second set of electrical contacts on the second surface of the second substrate. 
     In an aspect, the apparatus includes one or more first substrates, a data processor electrically coupled to the one or more first substrates, a plurality of sockets coupled to the one or more first substrates, and a lattice structure mechanically coupled to the one or more first substrates and defining a plurality of openings, each opening corresponding to one of the sockets, in which the openings allow communication interface modules to be inserted through the openings and be removably coupled to the sockets. In some examples, the apparatus includes a plurality of optical fiber cables, in which a portion of the optical fiber cables extend from communication interface modules in the direction that is substantially orthogonal to the first substrate. 
     The apparatus includes a plurality of compression modules, each compression module being associated with a corresponding socket, in which the compression module is configured to operate in a first state and a second state, when the compression module is in the first state, the compression module is configured to secure a communication interface module coupled to the socket by applying a compression force to press the communication interface module against the socket, wherein when the compression module is in the second state, the compression module is configured to release the communication interface module to allow the communication interface module to be removed from the socket. 
     In some examples, the apparatus includes a housing having a front panel includes the one or more first substrates are placed inside the housing and positioned behind the front panel, each of the one or more first substrates has a main surface that is oriented at an angle in a range of 0 to 45 degrees relative to the front panel, and each of the one or more first substrates is spaced apart from the front panel not more than 12 inches. 
     The apparatus includes communication interface modules, in which each communication interface module includes a co-packaged optical module that is configured to perform at least one of (i) receive optical signals, generate electrical signals based on the received optical signals, and send the electrical signals to the data processor, or (ii) receive electrical signals from the data processor, generate optical signals based on the received electrical signals, and output the optical signals. 
     The apparatus includes optical cables optically coupled to the co-packaged optical modules, in which each compression module defines an opening that allows at least one of the optical cables to pass through and be optically coupled to a co-packaged optical module that is being compressed by the compression module. In some implementations, the at least one of the compression modules includes a compression plate movable between a first position and a second position, in which when a communication interface module is coupled to a socket corresponding to the compression module and the compression plate is in the first position, the compression plate is configured to apply a force to the communication interface module to press the communication interface module against the socket. The communication interface module is coupled to a socket corresponding to the compression module and the compression plate is in the second position, the compression plate is configured to reduce the force applied to the communication interface module as compared to when the compression plate is in the first position, and allow the communication interface module to be removed from the socket. 
     In some implementations, the at least one of the compression modules includes a fastening device configured to operate in a first state or a second state, in which when the fastening device is in the first state, the fastening device is configured to secure the compression plate in the first position relative to the lattice structure. When the fastening device is in the second state, fastening device is configured to release the compression plate from the first position and allow the compression plate to move from the first position to the second position. 
     In some implementations, the compression plate defines one or more holes, the lattice structure defines one or more holes, and the fastening device includes a bolt that is configured to be inserted into the one or more holes of the lattice structure and the one or more holes of the compression plate to secure the compression plate at the first position relative to the lattice structure. The compression plate includes a first surface, a second surface, and an edge between the first and second surfaces. When the compression plate is in the first position, the first surface faces the corresponding communication interface module and the second surface faces away from the communication interface module, the one or more holes in the compression plate extend in the compression plate between the first surface and the second surface, the one or more holes have one or more openings at the edge of the compression plate. The bolt is configured to be inserted into the one or more holes of the compression plate through the one or more openings at the edge of the compression plate. The bolt includes a U-shaped bolt, the compression plate includes a set of two holes, the lattice structure includes a set of two holes, and the U-shaped bolt includes two legs that are configured to be inserted into the set of two holes in the lattice structure and the set of two holes in the compression plate to secure the compression plate at the first position relative to the lattice structure 
     The fastening device includes one or more screws that are configured to be inserted into one or more screw holes in the lattice structure and one or more screw holes in the compression plate to secure the compression plate at the first position relative to the lattice structure. In some implementations, at least one of the sockets includes compression interposers. 
     In some implementations, the apparatus includes a wave spring positioned between the compression plate and the communication interface module. The apparatus includes a thermal bridge material positioned between the compression plate and the communication interface module. 
     In an aspect, an apparatus includes a lattice structure defining a plurality of openings, a plurality of sockets, each socket corresponding to one of the openings, and a plurality of interface modules, in which each interface module includes a photonic integrated circuit, each interface module passes one of the openings of the lattice structure and is coupled to one of the sockets. The apparatus includes a plurality of optical fiber cables, in which each optical fiber cable is optically coupled to one of the photonic integrated circuits, wherein a portion of the optical fiber cables extend from one of the interface modules in the direction that is substantially orthogonal to the lattice structure. In some implementations, the apparatus includes a plurality of compression modules, in which each compression module is associated with a corresponding socket and interface module, the compression module is configured to operate in a first state and a second state. When the compression module is in the first state, the compression module is configured to apply a force to the interface module to press the interface module against the socket and when the compression module is in the second state, the compression module is configured to release the interface module to allow the interface module to be removed from the socket. In some implementations, each compression module defines an opening that allows a corresponding optical fiber cable to pass through and be optically coupled to a corresponding photonic integrated circuit. 
     In an aspect, a method includes providing a first substrate and a socket that is coupled to the first substrate and providing a support structure that is coupled to the first substrate, in which the support structure defines an opening. The method includes passing an interface module through the opening of the support structure and coupling the interface module to the socket, in which the interface module includes a photonic integrated circuit that is configured to perform at least one of (i) receive optical signals and generate electrical signals based on the received optical signals, or (ii) receive electrical signals and generate optical signals based on the received electrical signals. The method includes a plurality of optical fiber cables, in which a portion of the optical fiber cables extend from the interface module in the direction that is substantially orthogonal to the first substrate. 
     In some implementations, the method includes using a compression plate to apply a force to press the interface module against the socket and securing the compression plate at a predetermined position relative to the support structure to cause the compression plate to maintain the force applied to the interface module. 
     In some implementations, the method includes passing an optical fiber cable through an opening defined by the compression plate, and optically coupling the optical fiber cable to the interface module. The method includes securing the compression plate at the predetermined position relative to the support structure includes passing a bolt through one or more holes defined by the support structure and one or more holes defined by the compression plate. In some implementations, the method includes passing the bolt through the one or more holes defined by the support structure and the one or more holes defined by the compression plate includes passing two legs of a U-shaped bolt through two holes defined by the support structure and two holes defined by the compression plate. 
     The method includes providing a data processor electrically coupled to the first substrate, and transmitting electrical signals between the data processor and the interface module. In some implementations, the data processor includes at least one of a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, an application specific integrated circuit (ASIC), or a storage device. In some implementations, the data processor is connected to an opposite side of the first substrate relative to the interface modules. 
     In an aspect, an apparatus includes a first substrate having a first side and a second side, a plurality of electrical connectors attached to the first side of the first substrate, in which each electrical connector includes a plurality of electrical contacts, and a first lattice structure that defines a plurality of first openings, in which each first opening is configured to enable an interface module to pass through and be coupled to one of the electrical connectors on the first side of the first substrate. The apparatus includes a first printed circuit board positioned between the first substrate and the first lattice structure, in which the first printed circuit board has one or more openings to enable one or more interface modules to pass through and be coupled to some of the electrical connectors on the first side of the first substrate. 
     In some implementations, the first printed circuit board of the apparatus includes electrical connectors configured to receive at least one of electrical power, data signals, or control signals. In some implementations the first printed circuit board is electrically coupled to the first substrate, and the at least one of electrical power, data signals, or control signals is or are transmitted from the first printed circuit board to the first substrate. The apparatus includes a data processor electrically coupled to the first substrate. In some implementations, the data processor includes at least one of a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, an application specific integrated circuit (ASIC), or a storage device. In some implementations, the data processor is mounted on the second side of the first substrate. 
     In some implementations, the apparatus includes at least one of the at least one of electrical power, data signals, or control signals is or are transmitted from the first printed circuit board to the first substrate, and from the first substrate to the data processor. 
     In some implementations, the apparatus includes a second substrate, in which the data processor is mounted on the second substrate, and the second substrate is electrically coupled to the first substrate. 
     In some implementations, the apparatus includes a second printed circuit board, in which the second substrate is electrically coupled to the second printed circuit board, the first substrate is electrically coupled to the second printed circuit board, and the second substrate is electrically coupled to the first substrate through electrical signal lines on or in the second printed circuit board. 
     In some implementations, the apparatus includes one or more interface modules, in which each interface module passes one of the openings in the first lattice structure and is coupled to one of the electrical connectors on the first side of the first substrate. Each interface module is configured to perform at least one of (i) receive first signals from a data cable, generate second signals based on the first signals, and transmit the second signals to a data processor electrically coupled to the first substrate, or (ii) receive first signals from a data processor electrically coupled to the first substrate, generate second signals based on the first signals, and output the second signals. 
     In some examples, each interface module apparatus includes a photonic integrated circuit, the data cable includes an optical fiber cable, and the photonic integrated circuit is configured to perform at least one of (i) receive optical signals from the optical fiber cable, generate electrical signals based on the optical signals, and transmit the electrical signals to the data processor, or (ii) receive electrical signals from the data processor, generate optical signals based on the electrical signals, and output the optical signals. 
     In some examples, the apparatus includes at least one of the electrical connectors attached to the first side of the first substrate comprise a plurality of sockets mounted on the first side of the first substrate includes compression interposers. The apparatus includes a first set of one or more components mounted on the first side of the first substrate. The first lattice structure defines a second opening that enables the first set of one or more components mounted on the first side of the first substrate to pass through the one or more openings in the first printed circuit board and protrude through or partially through the second opening defined by the first lattice structure. 
     In some examples, the apparatus includes the first set of one or more components that are configured to support a data processor electrically coupled to the first substrate. The first set of one or more components includes at least one of a capacitor, a filter, or a power converter. The apparatus of includes the first lattice structure that has a first portion that extends through the one or more openings in the first printed circuit board and contacts the first side of the first substrate. 
     In some examples, the apparatus includes a housing having a front panel, wherein the first substrate, the first lattice, and the first printed circuit board are disposed in the housing, and the first lattice structure is disposed between the front panel and the first printed circuit board. The apparatus includes a main surface of the first substrate is oriented at an angle in a range between 0 to 45° relative to a main surface of the front panel. The apparatus includes the main surface of the first substrate is oriented at an angle in a range between 0 to 5° relative to the main surface of the front panel. In some implementations, the front panel includes the first lattice structure. 
     In some implementations, the apparatus includes a heat dissipating device thermally coupled to the data processor. The apparatus includes a second lattice structure disposed between the first substrate and the heat dissipating device. The second lattice structure defines a plurality of openings, and the data processor protrudes through or partially through one of the openings. The apparatus includes a plurality of components mounted on the second side of the first substrate, in which the plurality of components protrude through or partially through the one or more openings. 
     In some implementations, the apparatus includes the first lattice structure, the first printed circuit board, the first substrate, the second lattice structure, and the heat dissipating device are fastened together. The second lattice structure has lips that function as a backstop to prevent crushing of an interface between the first substrate and the first printed circuit board when the force is applied to fasten the first printed circuit board and the first substrate together. The first substrate includes a substrate made of at least one of ceramic or organic high density build-up. 
     In some implementations, the apparatus includes a half width 2U rackmount server, in which the first substrate, the first lattice structure, and the first printed circuit board are part of the rackmount server. The first lattice structure includes at least 32 first openings and a second opening that is larger than the first openings, each first opening has a dimension of at least 12 mm by 12 mm, each first opening enables an optoelectronic interface module to pass through, and the first openings are spaced apart at distances to support XSR channel compliance. 
     In an aspect, an apparatus includes a first substrate having a first side and a second side, a data processor electrically coupled to electrical contacts on the second side of the first substrate. The apparatus includes a first lattice structure that defines a plurality of first openings, in which each first opening is configured to enable an optoelectronic interface module to pass through and be coupled to electrical contacts on the first side of the first substrate. The optoelectronic interface module is configured to perform at least one of (i) receive optical signals from an optical fiber cable, generate electric signals based on the optical signals, and transmit the electrical signals to the data processor through the electrical contacts on the first side of the first substrate, or (ii) receive electrical signals from the data processor through the electrical contacts on the first side of the first substrate, generate optical signals based on the electrical signals, and output the optical signals through an optical fiber cable. The apparatus includes a first printed circuit board positioned between the first substrate and the first lattice structure, in which the first printed circuit board has one or more openings to enable the optoelectronic interface modules to pass through and be coupled to the electrical contacts on the first side of the first substrate. 
     In an aspect, a method includes assembling a first substrate, a first printed circuit board, and a first lattice structure to form a first module, in which the first printed circuit board is positioned between the first substrate and the first lattice structure. The first substrate has a first surface and a second surface, the first surface has a plurality of electrical contacts. The first printed circuit board defines one or more openings, the first lattice structure defines a plurality of first openings, each first opening has a dimension configured to enable an interface module to pass through the first opening in the first lattice structure and an opening in the first printed circuit board and be coupled to some of the electrical contacts on the first surface of the first substrate. 
     In some implementations, the method includes assembling a first lattice structure, a first printed circuit board, a first substrate, and a second lattice structure to form a first module, in which the first printed circuit board is positioned between the first substrate and the first lattice structure, and the first substrate is positioned between the first printed circuit board and the second lattice structure. The first substrate has a first surface and a second surface, the first surface has a plurality of electrical contacts. The first printed circuit board defines one or more openings, the first lattice structure defines a plurality of first openings, each first opening has a dimension configured to enable an interface module to pass through the first opening in the first lattice structure and an opening in the first printed circuit board and be coupled to some of the electrical contacts on the first surface of the first substrate. 
     In some implementations, the method includes electrically coupling a data processor to the second side of the first substrate, defining a second opening using the second lattice structure, and protruding the data processor through or partially through the second opening. 
     In some implementations, the method includes thermally coupling a heat dissipating device to the data processor. The method includes preventing, by use of lips in the second lattice structure to function as a backstop, crushing of an interface between the first substrate and the first printed circuit board when force is applied to fasten the first printed circuit board and the first substrate together. 
     In an aspect, a method includes providing electric power to a data processor electrically coupled to a first substrate, in which the electric power is provided through a first printed circuit board to the first substrate, and from the first substrate to the data processor. The method includes transmitting an optical signal from an optical fiber cable to a photonic integrate circuit that is part of a co-packaged optical module that is inserted into a first opening defined by a first lattice structure and a second opening defined by the first printed circuit board, in which the first printed circuit board is positioned between the first substrate and the first lattice structure, and the first lattice structure aids in an alignment of the co-packaged optical module with electrical contacts on a surface of the first substrate. The method includes generating, at the photonic integrated circuit, providing at least one of electrical power, data signals, or control signals. The method includes transmitting the at least one of electrical power, data signals, or control signals from the first printed circuit board to the data processor through the first substrate. 
     In an aspect, an apparatus includes a substrate, a socket coupled to the substrate, and a compression plate configured to selectively operate in a first state or a second state, when the compression plate operates in the first state the compression plate applies a force to compresses an interface module against the socket. When the compression plate operates in the second state the compression plate removes or reduces the force applied to the interface module. The interface module includes a photonic integrated circuit, and the compression plate defines an opening to allow an optical cable to pass through and optically couple to the interface module. 
     In some implementations the apparatus includes a lattice structure and a fastening device, in which the lattice structure is attached to the substrate. The fastening device is configured to move between a first position that secures the compression plate relative to the lattice structure, and a second position that releases the compression plate from the lattice structure. 
     The apparatus includes compression plate that define one or more holes, the lattice structure has a sidewall that defines one or more holes, and the fastening device includes a bolt that is configured to be inserted into the one or more holes of the lattice structure and the one or more holes of the compression plate to secure the compression plate in the first position relative to the lattice structure. In some implementations, the bolt includes a U-shaped bolt, the compression plate defines a set of two holes, the sidewall of the lattice structure defines a set of two holes, and the U-shaped bolt includes two legs that are configured to be inserted into the set of two holes in the sidewall of the lattice structure and the set of two holes in the compression plate to secure the compression plate in the first position relative to the lattice structure. In some implementations, the apparatus includes a wave spring positioned between the compression plate and the interface module. The apparatus includes the socket, in which the socket includes compression interposers. In some implementations, the socket includes an LGA socket. The apparatus includes the optical cable. 
     In some implementations, the apparatus includes a data processor electrically coupled to the substrate; in which the photonic integrated circuit is configured to perform at least one of (i) receive optical signals, generate electrical signals based on the received optical signals, and transmit the electrical signals to the data processor, or (ii) receive electrical signals from the data processor, generate optical signals based on the electrical signals, and output the optical signals. 
     In some implementations, the data processor includes at least one of a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, an application specific integrated circuit (ASIC), or a storage device. 
     In some implementations, the apparatus includes at least half of the substrate that includes at least one of ceramic or organic high density build-up. 
     In an aspect, an apparatus includes a substrate, a plurality of sockets electrically coupled to the substrate, a lattice structure mechanically coupled to the substrate and defining a plurality of openings, each opening corresponding to one of the sockets. The apparatus includes a plurality of compression modules, in which each compression module is associated with a corresponding socket, each compression module includes a compression plate and a fastening device. The compression plate is configured to selectively compress a communication interface module against a corresponding socket or release the communication interface module from the socket, and the fastening device is configured to selectively secure the compression plate relative to the lattice structure or release the compression plate from the lattice structure. In some implementations, the apparatus includes a data processor electrically coupled to the substrate. 
     In some implementations, includes the communication interface modules, in which each communication interface module includes a co-packaged optical module that is configured to perform at least one of (i) receive optical signals, generate electrical signals based on the received optical signals, and send the electrical signals to the data processor, or (ii) receive electrical signals from the data processor, generate optical signals based on the received electrical signals, and output the optical signals. 
     In some implementations, the apparatus includes optical cables optically coupled to the communication interface modules, in which each compression module defines an opening that allows an optical cable to pass through and optically couple to the corresponding communication interface module that is compressed by the compression module against the corresponding socket. 
     In some implementations, the fastening device of the apparatus includes a bolt that is configured to be inserted into one or more holes of the lattice structure and one or more holes of the compression plate to secure the compression plate relative to the lattice structure. In some implementations, the apparatus includes a wave spring positioned between each of the compression plate and the corresponding communication interface module. The sockets of the apparatus include compression interposers. In some implementations, the data processor includes at least one of a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, an application specific integrated circuit (ASIC), or a storage device. The apparatus includes at least half of the substrate includes at least one of ceramic or organic high density build-up. 
     In an aspect, an apparatus includes a substrate configured to support a data processing integrated circuit, a first lattice structure that defines a plurality of openings, and a printed circuit board positioned between the substrate and the first lattice structure, in which the printed circuit board defines a first opening that is configured to overlap a footprint of the data processing integrated circuit. In some implementations, the apparatus includes the printed circuit board includes electrical connectors configured to receive at least one of electrical power, data signals, or control signals. The printed circuit board is electrically coupled to the substrate and the printed circuit board is configured to transmit the at least one of electrical power, data signals, or control signals to the substrate. 
     In some implementations, the apparatus includes the substrate that is configured to transmit the at least one of electrical power, data signals, or control signals to the data processing integrated circuit. The substrate of the apparatus includes a front side and a rear side, the data processing integrated circuit is mounted on the rear side of the substrate, the first lattice structure includes a front lattice structure, the printed circuit board is positioned between the substrate and the front lattice structure, the front side of the substrate faces the printed circuit board, at least one electronic component that supports the data processing integrated circuit is mounted on the front side of the substrate and protrudes through or partially through the first opening in the printed circuit board. 
     In some implementations, the apparatus includes the at least one electronic component that supports the data processing integrated circuit includes at least one of a capacitor, a filter, a power converter, or a voltage regulator. The apparatus includes a communication interface electrically coupled to the front side of the substrate, and the communication interface protrudes through or partially through the first opening or a second opening defined by the printed circuit board. 
     In some implementations, the apparatus includes a plurality of communication interfaces electrically coupled to the front side of the substrate, and the communication interfaces protrude through or partially through the first opening or one or more additional openings defined by the printed circuit board. The substrate of the apparatus includes a front side and a rear side, the first lattice structure includes a rear lattice structure, the printed circuit board is positioned between the substrate and the rear lattice structure, the rear side of the substrate faces the printed circuit board, the data processing integrated circuit is mounted on the rear side of the substrate and protrudes through or partially through the first opening in the printed circuit board. 
     In some implementations, the apparatus includes at least one socket that is attached to the front side of the substrate, the socket is configured to be electrically coupled to a communication interface module that includes a photonic integrated circuit. 
     In some implementations, the communication interface module of the apparatus is configured to perform at least one of (i) receive first signals from a data cable, generate second signals based on the first signals, and transmit the second signals to the data processing integrated circuit, or (ii) receive first signals from the data processing integrated circuit, generate second signals based on the first signals, and output the second signals. 
     In some implementations, the communication interface module of the apparatus includes a photonic integrated circuit, the data cable includes an optical fiber cable, and the photonic integrated circuit is configured to perform at least one of (i) receive optical signals from the optical fiber cable, generate electrical signals based on the optical signals, and transmit the electrical signals to the data processing integrated circuit, or (ii) receive electrical signals from the data processing integrated circuit, generate optical signals based on the electrical signals, and output the optical signals. 
     In an aspect, an apparatus includes a first substrate having a first side and a second side, a second substrate electrically coupled to the first substrate, and a data processor electrically coupled to the first substrate, in which the data processor is mounted on the second substrate. The apparatus includes a plurality of electrical connectors attached to the first side of the first substrate, in which each electrical connector includes a plurality of electrical contacts. 
     In a general aspect, a system includes: a housing that has a front panel; a substrate that is positioned at a distance from the front panel, in which a data processor is mounted on the substrate; and a pluggable module. The pluggable module includes a co-packaged optical module, at least one first optical connector, a first fiber optic cable that is optically coupled between the co-packaged optical module and the first optical connector, and a fiber guide that is positioned between the co-packaged optical module and the first optical connector and provides mechanical support for the co-packaged optical module and the first optical connector. The co-packaged optical module is configured to receive optical signals from the first optical connector, generate electrical signals based on the received optical signals, and transmit the electrical signals to the data processor. The pluggable module has a shape that enables at least some part of the pluggable module to pass through an opening in the front panel to enable the co-packaged optical module to be coupled to the substrate. 
     Implementations can include one or more of the following features. 
     The first optical connector can be configured to mate with a corresponding optical connector of an external fiber optic cable. 
     The first optical connector can include a multi-fiber push on (MPO) connector. 
     The fiber guide can have a length configured such that when the pluggable module is inserted through the opening in the front panel and the co-packaged optical module is coupled to the substrate or a module mounted on the substrate, the at least one first optical connector is in a vicinity of the front panel to enable a user to attach at least one external fiber optic cable to the at least one first optical connector. 
     The fiber guide can have a length configured such that when the pluggable module is inserted through the opening in the front panel and the co-packaged optical module is coupled to the substrate or a module mounted on the substrate, the at least one first optical connector has a front surface that is flush with, or protrudes from, a front surface of the front panel to enable a user to attach at least one external fiber optic cable to the at least one first optical connector. 
     The fiber guide can have a length configured such that when the pluggable module is inserted through the opening in the front panel and the co-packaged optical module is coupled to the substrate or a module mounted on the substrate, the at least one first optical connector has a front face that is within an inch of a front surface of the front panel. 
     The fiber guide can have a length of at least one inch. 
     The fiber guide can have a length of at least two inches. 
     The fiber guide can have a length of at least four inches. 
     The pluggable module can include at least two first optical connectors, and each optical connector can be configured to be mated with an optical connector of an external fiber optic cable. 
     The pluggable module can include at least four first optical connectors, and each optical connector can be configured to be mated with an optical connector of an external fiber optic cable. 
     The first fiber optic cable can include a fiber pigtail. 
     The substrate can have a main surface that is oriented at an angle in a range of 0 to 45 degrees relative to the front panel. 
     The substrate can be oriented parallel to the front panel. 
     The system can include an inlet fan mounted near the front panel and configured to increase an air flow across a surface of at least one of (i) the co-packaged optical module, or (ii) a heat dissipating device thermally coupled to the co-packaged optical module. 
     The system can include two or more pluggable modules. Each pluggable module can include a co-packaged optical module, at least one first optical connector, a first fiber optic cable that is optically coupled between the co-packaged optical module and the first optical connector, and a fiber guide that is positioned between the co-packaged optical module and the first optical connector. The fiber guides can be configured to allow air blown from the inlet fan to flow past the fiber guides and carry away heat generated by the co-packaged optical module. 
     The system can include a laser module configured to provide optical power to the co-packaged optical module. 
     The system can include a second optical connector optically coupled to the laser module. The pluggable module can include a third optical connector that is configured to mate with the second optical connector when the pluggable module is coupled to the substrate. The first optical connector can be optically coupled to the co-packaged optical module to enable the co-packaged optical module to receive the optical power from the laser module. 
     The fiber guide can include at least one of metal or a thermal conductive material. 
     The fiber guide can include a hollow tube. 
     The fiber guide can be rigid along a direction from the first optical connector to the co-packaged optical module and can have a strength sufficient to withstand a compression force exerted on the pluggable module when the pluggable module is inserted through the opening in the front panel and coupled to the substrate. 
     The fiber guide can have a spatial fan-out design such that a first portion of the fiber guide near the co-packaged optical module has a smaller dimension compared to the dimension of a second portion of the fiber guide near the at least one first optical connector. 
     The at least one first optical connector can have an overall footprint that is larger than a footprint of the co-packaged optical module. 
     The data processor can include at least a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, an application specific integrated circuit (ASIC), or a storage device. 
     A photon supply can be disposed in, on, or near the fiber guide, and the photon supply can be configured to provide optical power supply light to the co-packaged optical module. 
     The photon supply can be thermally coupled to an inner surface or an outer surface of the fiber guide, and the fiber guide can be configured to assist in dissipating heat from the photon supply. 
     The system can include guide rails configured to guide the co-packaged optical module as the co-packaged optical module move from a first position near the front panel to a second position near the substrate. 
     The system can include a co-packaged optical module (CPO) mount attached to the substrate, the guide rails can be configured to provide rigid connections between the CPO mount and the front panel or a front portion of the fiber guide. 
     The system can include a co-packaged optical module (CPO) mount and a bolster plate, in which the co-packaged optical module is mounted on the substrate through the CPO mount, the bolster plate is positioned to the rear of the substrate and configured to exert a force in a front direction when the guide rails are fastened to a front portion of the fiber guide or to the front panel. 
     In another general aspect, an apparatus includes: a pluggable module includes a co-packaged optical module, at least one first optical connector, a first fiber optic cable that is optically coupled between the co-packaged optical module and the first optical connector, and a fiber guide that is positioned between the co-packaged optical module and the first optical connector and provides mechanical support for the co-packaged optical module and the first optical connector. The co-packaged optical module is configured to receive optical signals from the at least one first optical connector, and generate electronic signals based on the optical signals. 
     Implementations can include one or more of the following features. The fiber guide can include at least one of metal or a thermal conductive material. 
     The fiber guide can include a hollow tube. 
     The fiber guide can be rigid along a direction from the first optical connector to the co-packaged optical module and can have a strength sufficient to withstand a compression force exerted on the pluggable module when the pluggable module is inserted through an opening in a front panel of a housing and coupled to the substrate. 
     The fiber guide can have a spatial fan-out design such that a first portion of the fiber guide near the co-packaged optical module has a smaller dimension compared to the dimension of a second portion of the fiber guide near the at least one first optical connector. 
     The at least one first optical connector can have an overall footprint that is larger than a footprint of the co-packaged optical module 
     In another general aspect, a rackmount server includes: a housing having a front panel and a rear panel. The front panel defines an opening, and the rear panel is at a first distance from the front panel. The rackmount server includes a substrate that is positioned at a second distance from the front panel. The second distance is less than one-third of the first distance. The rackmount server includes a data processor that is mounted on the substrate. The substrate has a main surface that is oriented at an angle in a range of 0 to 45 degrees relative to the front panel. In some examples, the substrate can have electrical contacts that are configured to the electrically coupled to electrical contacts of a co-packaged optical module. In some examples, a first module is mounted on the substrate, and the first module has electrical contacts that are configured to the electrically coupled to electrical contacts of a co-packaged optical module. 
     Implementations can include one or more of the following features. The substrate can be oriented substantially parallel to the front panel. 
     The opening in the front panel can be configured to allow a pluggable module that includes the co-packaged optical module to be inserted through the opening to enable the co-packaged optical module to be electrically coupled to the electrical contacts on the substrate or the electrical contacts on the first module mounted on the substrate. 
     The rackmount server can include the pluggable module. 
     The pluggable module can include the co-packaged optical module, at least one first optical connector, a first fiber optic cable that is optically coupled between the co-packaged optical module and the first optical connector, and a fiber guide that is positioned between the co-packaged optical module and the first optical connector and provides mechanical support for the co-packaged optical module and the first optical connector. 
     The co-packaged optical module can be configured to receive optical signals from the first optical connector, generate electrical signals based on the received optical signals, and transmit the electrical signals to the data processor. 
     The data processor can include at least a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, an application specific integrated circuit (ASIC), or a storage device. 
     In another general aspect, a system includes: a substrate made of at least one of ceramic or organic high density build-up; a data processor mounted on a rear side of the substrate; a co-packaged optical module. The co-packaged optical module is removably coupled to a front side of the substrate and configured to receive optical signals from an optical connector, generate electrical signals based on the received optical signals, and transmit the electrical signals to the data processor. The system includes a printed circuit board attached to the rear side of the substrate, in which the printed circuit board includes an opening, and the data processor protrudes or partially protrudes through the opening, and the printed circuit board provides electrical power to the data processor through the substrate. 
     Other aspects include other combinations of the features recited above and other features, expressed as methods, apparatus, systems, program products, and in other ways. 
     Particular embodiments of the subject matter described in this specification can be implemented to realize one or more of the following advantages. The data processing system has a high power efficiency, a low construction cost, a low operation cost, and high flexibility in reconfiguring optical network connections. 
     The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the invention will become apparent from the description, the drawings, and the claims. 
     Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. In case of conflict with patent applications or patent application publications incorporated herein by reference, the present specification, includes definitions, will control. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not to-scale. The dimensions of the various features can be arbitrarily expanded or reduced for clarity. 
         FIG.  1    is a block diagram of an example optical communication system. 
         FIG.  2    is a schematic side view of an example data processing system. 
         FIG.  3    is a schematic side view of an example integrated optical device. 
         FIG.  4    is a schematic side view of an example data processing system. 
         FIG.  5    is a schematic side view of an example integrated optical device. 
         FIGS.  6  and  7    are schematic side views of examples of data processing systems. 
         FIG.  8    is an exploded perspective view of an integrated optical communication device. 
         FIGS.  9  and  10    are diagrams of example layout patterns of optical and electrical terminals of integrated optical devices. 
         FIGS.  11 ,  12 ,  13 , and  14    are schematic side views of examples of data processing systems. 
         FIGS.  15  and  16    are bottom views of examples of integrated optical devices. 
         FIG.  17    is a diagram showing various types of integrated optical communication devices that can be used in a data processing system. 
         FIG.  18    is a diagram of an example octal serializers/deserializers block. 
         FIG.  19    is a diagram of an example electronic communication integrated circuit. 
         FIG.  20    is a functional block diagram of an example data processing system. 
         FIG.  21    is a diagram of an example rackmount data processing system. 
         FIGS.  22  to  28    are top view diagrams of examples of rackmount data processing systems incorporating optical interconnect modules. 
         FIG.  29    is a diagram of an example rackmount data processing system incorporating multiple optical interconnect modules. 
         FIGS.  30  and  31    are block diagrams of example data processing systems. 
         FIG.  32    is a schematic side view of an example data processing system. 
         FIG.  33    is a diagram of an example electronic communication integrated circuit that includes octal serializers/deserializers blocks. 
         FIG.  34    is a flow diagram of an example process for processing optical and electrical signals using a data processing system. 
         FIG.  35 A  is a diagram an optical communications system. 
         FIGS.  35 B and  35 C  are diagrams of co-packaged optical interconnect modules. 
         FIGS.  36  and  37    are diagrams of examples of optical communications systems. 
         FIGS.  38  and  39    are diagrams of examples of serializers/deserializers blocks. 
         FIGS.  40 A,  40 B,  41 A,  41 B, and  42    are diagrams of examples of bus processing units. 
         FIG.  43    is an exploded view of an example of a front-mounted module of a data processing system. 
         FIG.  44    is an exploded view of an example of the internals of an optical module. 
         FIG.  45    is an assembled view of the internals of an optical module. 
         FIG.  46    is an exploded view of an optical module. 
         FIG.  47    is an assembled view of an optical module. 
         FIG.  48    is a diagram of a portion of a grid structure and a circuit board. 
         FIG.  49    is a diagram showing a lower mechanical part prior to insertion into the grid structure. 
         FIG.  50    is a diagram of an example of a partially populated front-view of an assembled system. 
         FIG.  51 A  is a front view of an example of the mounting of the module. 
         FIG.  51 B  is a side view of an example of the mounting of the module. 
         FIG.  52 A  is a front view of an example of the mechanical connector structure and an optical module mounted within a grid structure. 
         FIG.  52 B  is a side view of an example of the mechanical connector structure and an optical module mounted within a grid structure. 
         FIGS.  53  and  54    are diagrams of an example of an assembly that includes a fiber cable, an optical fiber connector, a mechanical connector module, and a grid structure. 
         FIGS.  55 A and  55 B  are perspective views of the mechanisms shown in  FIGS.  53  and  54    before the optical fiber connector is inserted into the mechanical connector structure. 
         FIG.  56    is a perspective view showing that the optical module and the mechanical connector structure are inserted into the grid structure. 
         FIG.  57    is a perspective view showing that the optical fiber connector is mated with the mechanical connector structure. 
         FIGS.  58 A to  58 D  are diagrams of an example an optical module that includes a latch mechanism. 
         FIG.  59    is a diagram of an alternative example of the optical module. 
         FIGS.  60 A and  60 B  are diagrams of an example implementation of the lever and the latch mechanism in the optical module with connector. 
         FIG.  61    is a diagram of cross section of the module viewed from the front mounted in the assembly with the connector. 
         FIGS.  62  to  65    are diagrams showing cross-sectional views of an example of a fiber cable connection design. 
         FIG.  66    is a map of electrical contact pads. 
         FIG.  67    is a top view of an example of a rackmount server. 
         FIG.  68 A  is a top view of an example of a rackmount server. 
         FIG.  68 B  is a diagram of an example of a front panel of the rackmount server. 
         FIG.  68 C  is a perspective view of an example of a heat sink. 
         FIG.  69 A  is a top view of an example of a rackmount server. 
         FIG.  69 B  is a diagram of an example of a front panel of the rackmount server. 
         FIG.  70    is a top view of an example of a rackmount server. 
         FIG.  71 A  is a top view of an example of a rackmount server. 
         FIG.  71 B  is a front view of the rackmount server. 
         FIG.  72    is a top view of an example of a rackmount server. 
         FIG.  73 A  is a top view of an example of a rackmount server. 
         FIG.  73 B  is a front view of the rackmount server. 
         FIG.  74 A  is a top view of an example of a rackmount server. 
         FIG.  74 B  is a front view of the rackmount server. 
         FIG.  75 A  is a top view of an example of a rackmount server. 
         FIG.  75 B  is a front view of the rackmount server. 
         FIG.  75 C  is a diagram of the air flow in the rackmount server. 
         FIG.  76    is a diagram of a network rack that includes a plurality of rackmount servers. 
         FIG.  77 A  is a side view of an example of a rackmount server. 
         FIG.  77 B  is a top view of the rackmount server. 
         FIG.  78    is a top view of an example of a rackmount server. 
         FIG.  79    is a block diagram of an example of an optical communication system. 
         FIG.  80 A  is a diagram of an example of an optical communication system. 
         FIG.  80 B  is a diagram of an example of an optical cable assembly used in the optical communication system of  FIG.  80 A . 
         FIG.  80 C  is an enlarged diagram of the optical cable assembly of  FIG.  80 B . 
         FIG.  80 D  is an enlarged diagram of the upper portion of the optical cable assembly of  FIG.  80 B . 
         FIG.  80 E  is an enlarged diagram of the lower portion of the optical cable assembly of  FIG.  80 B . 
         FIG.  81    is a block diagram of an example of an optical communication system. 
         FIG.  82 A  is a diagram of an example of an optical communication system. 
         FIG.  82 B  is a diagram of an example of an optical cable assembly. 
         FIG.  82 C  is an enlarged diagram of the optical cable assembly of  FIG.  82 B . 
         FIG.  82 D  is an enlarged diagram of the upper portion of the optical cable assembly of  FIG.  82 B . 
         FIG.  82 E  is an enlarged diagram of the lower portion of the optical cable assembly of  FIG.  82 B . 
         FIG.  83    is a block diagram of an example of an optical communication system. 
         FIG.  84 A  is a diagram of an example of an optical communication system. 
         FIG.  84 B  is a diagram of an example of an optical cable assembly. 
         FIG.  84 C  is an enlarged diagram of the optical cable assembly of  FIG.  84 B . 
         FIGS.  85  to  87 B  are diagrams of examples of data processing systems. 
         FIG.  88    is a diagram of an example of connector port mapping for an optical fiber interconnection cable. 
         FIGS.  89  and  90    are diagrams of examples of fiber port mapping for optical fiber interconnection cables. 
         FIGS.  91  and  92    are diagrams of examples of viable port mapping for optical fiber connectors of universal optical fiber interconnection cables. 
         FIG.  93    is a diagram of an example of a port mapping for an optical fiber connector that is not appropriate for a universal optical fiber interconnection cable. 
         FIGS.  94  and  95    are diagrams of examples of viable port mapping for optical fiber connectors of universal optical fiber interconnection cables. 
         FIG.  96    is a top view of an example of a rackmount server. 
         FIG.  97 A  is a perspective view of the rackmount server of  FIG.  96   . 
         FIG.  97 B  is a perspective view of the rackmount server of  FIG.  96    with the top panel removed. 
         FIG.  98    is a diagram of the front portion of the rackmount server of  FIG.  96   . 
         FIG.  99    includes perspective front and rear views of the front panel of the rackmount server of  FIG.  96   . 
         FIG.  100    is a top view of an example of a rackmount server. 
         FIGS.  101 ,  102 ,  103 A, and  103 B  are diagrams of examples of optical fiber connectors. 
         FIGS.  104  and  105    are a top view and a front view, respectively, of an example of a rackmount device that includes a vertical printed circuit board on which co-packaged optical modules are mounted. 
         FIG.  106    is a diagram of an example of an optical cable assembly. 
         FIG.  107    is a front view diagram of the rackmount device with the optical cable assembly. 
         FIG.  108    is a top view diagram of an example of a rackmount device that includes a vertical printed circuit board on which co-packaged optical modules are mounted. 
         FIG.  109    is a front view diagram of the rackmount device with the optical cable assembly. 
         FIGS.  110  and  111    are a top view and a front view, respectively, of an example of a rackmount device. 
         FIG.  112    is diagram of an example of a rackmount device with example parameter values. 
         FIGS.  113  and  114    show another example of a rackmount device with example parameter values. 
         FIGS.  115  and  116    are a top view and a front view, respectively, of an example of a rackmount device. 
         FIGS.  117  to  122    are diagrams of examples of systems that include co-packaged optical modules. 
         FIG.  123    is a side view of an example of a rackmount server that has a hinged front panel. 
         FIGS.  124  to  127    are diagrams of examples of rackmount servers that have pluggable modules. 
         FIG.  128    is a diagram of an example of a fiber guide that includes one or more photon supplies. 
         FIG.  129    is a diagram of an example of a rackmount server that includes guide rails/cage to assist the insertion of fiber guides. 
         FIG.  130    is a diagram of an example of a CPO module with a compression plate. 
         FIG.  131    is a diagram of an example of a compression plate. 
         FIG.  132    is a diagram of an example of a U-shaped bolt. 
         FIG.  133    is a diagram of an example of a wave spring. 
         FIGS.  134  and  135 A to  135 C  are diagrams of an example of compression plates secured to a front lattice structure. 
         FIG.  136    is an exploded front perspective view of an example of an assembly in a rackmount system that includes a substrate, a printed circuit board, a front lattice structure, a rear lattice structure, and a heat dissipating device. 
         FIG.  137    is an exploded rear perspective view of an example of the assembly shown in  FIG.  136   . 
         FIG.  138    is an exploded top view of an example of the assembly shown in  FIG.  136   . 
         FIG.  139    is an exploded side view of an example of the assembly shown in  FIG.  136   . 
         FIG.  140    is a front perspective view of an example of the assembly that has been fastened together. 
         FIG.  141    is a front perspective view of an example of the assembled assembly without the front lattice structure. 
         FIG.  142    is a front perspective view of an example of the substrate, the rear lattice structure, and the heat dissipating device that have been fastened together. 
         FIG.  143    is a front perspective view of an example of the rear lattice structure and the heat dissipating device that have been fastened together. 
         FIG.  144    is a front perspective view of an example of the heat dissipating device and the screws. 
         FIG.  145    is a rear perspective view of an example of the assembly that has been fastened together. 
         FIG.  146    is a rear perspective view of an example of the assembly without the rear lattice structure. 
         FIG.  147    is a rear perspective view of an example of the front lattice structure, the printed circuit board, and the substrate that have been fastened together. 
         FIG.  148    is a rear perspective view of an example of the front lattice structure and the printed circuit board that have been fastened together. 
         FIG.  149    is a rear perspective view of an example of the front lattice structure. 
         FIG.  150    is a diagram of an example of a configuration for connecting a data processing chip to CPO modules. 
         FIGS.  151  to  153    are diagrams of examples of an assembly in a rackmount system that includes a substrate, a printed circuit board, a front lattice structure, a rear lattice structure, and a heat dissipating device. 
         FIG.  154    is a diagram of an example of a CPO module. 
         FIGS.  155 A and  155 B  are perspective views of examples of LGA sockets, optical modules, and compression plates. 
         FIG.  156    is a front view of an example of an array of compression plates. 
         FIG.  157    is a front perspective view of an example of an assembly that includes a substrate, optical modules, and compression plates. 
         FIG.  158    is a top view of an example of an assembly that includes a substrate, a data processing integrated circuit, optical modules, and compression plates. 
         FIG.  159    is a side view of an example of a rackmount server that has a hinge-mounted front panel. 
         FIG.  160    is a top view of an example of a rackmount server that has a hinge-mounted front panel. 
         FIG.  161    is a diagram of an example of an optical cable. 
     
    
    
     DETAILED DESCRIPTION 
     This document describes a novel system for high bandwidth data processing, including novel input/output interface modules for coupling bundles of optical fibers to data processing integrated circuits (e.g., network switches, central processing units, graphics processor units, tensor processing units, digital signal processors, and/or other application specific integrated circuits (ASICs)) that process the data transmitted through the optical fibers. In some implementations, the data processing integrated circuit is mounted on a circuit board positioned near the input/output interface module through a relatively short electrical signal path on the circuit board. The input/output interface module includes a first connector that allows a user to conveniently connect or disconnect the input/output interface module to or from the circuit board. The input/output interface module includes a second connector that allows the user to conveniently connect or disconnect the bundle of optical fibers to or from the input/output interface module. In some implementations, a rack mount system having a front panel is provided in which the circuit board (which supports the input/output interface modules and the data processing integrated circuits) is vertically mounted in an orientation substantially parallel to, and positioned near, the front panel. In some examples, the circuit board functions as the front panel or part of the front panel. The second connectors of the input/output interface modules face the front side of the rack mount system to allow the user to conveniently connect or disconnect bundles of optical fibers to or from the system. 
     In some implementations, a feature of the high bandwidth data processing system is that, by vertically mounting the circuit board that supports the input/output interface modules and the data processing integrated circuits to be near the front panel, or configuring the circuit board as the front panel or part of the front panel, the optical signals can be routed from the optical fibers through the input/output interface modules to the data processing integrated circuits through relatively short electrical signal paths. This allows the signals transmitted to the data processing integrated circuits to have a high bit rate (e.g., over 50 Gbps) while maintaining low crosstalk, distortion, and noise, hence reducing power consumption and footprint of the data processing system. 
     In some implementations, a feature of the high bandwidth data processing system is that the cost of maintenance and repair can be lower compared to traditional systems. For example, the input/output interface modules and the fiber optic cables are configured to be detachable, a defective input/output interface module can be replaced without taking apart the data processing system and without having to re-route any optical fiber. Another feature of the high bandwidth data processing system is that, because the user can easily connect or disconnect the bundles of the optical fibers to or from the input/output interface modules through the front panel of the rack mount system, the configurations for routing of high bit rate signals through the optical fibers to the various data processing integrated circuits is flexible and can easily be modified. For example, connecting a bundle of hundreds of strands of optical fibers to the optical connector of the rack mount system can be almost as simple as plugging a universal serial bus (USB) cable into a USB port. A further feature of the high bandwidth data processing system is that the input/output interface module can be made using relatively standard, low cost, and energy efficient components so that the initial hardware costs and subsequent operational costs of the input/output interface modules can be relatively low, compared to conventional systems. 
     In some implementations, optical interconnects can co-package and/or co-integrate optical transponders with electronic processing chips. It is useful to have transponder solutions that consume relatively low power and that are sufficiently robust against significant temperature variations as may be found within an electronic processing chip package. In some implementations, high speed and/or high bandwidth data processing systems can include massively spatially parallel optical interconnect solutions that multiplex information onto relatively few wavelengths and use a relatively large number of parallel spatial paths for chip-to-chip interconnection. For example, the relatively large number of parallel spatial paths can be arranged in two-dimensional arrays using connector structures such as those disclosed in U.S. patent application Ser. No. 16/816,171, filed on Mar. 11, 2020, and incorporated herein by reference in its entirety. U.S. patent application Ser. No. 16/816,171 is provided in Appendix A. 
       FIG.  1    shows a block diagram of a communication system  100  that incorporates one or more novel features described in this document. In some implementations, the system  100  includes nodes  101 _ 1  to  101 _ 6  (collectively referenced as  101 ), which in some embodiments can each include one or more of: optical communication devices, electronic and/or optical switching devices, electronic and/or optical routing devices, network control devices, traffic control devices, synchronization devices, computing devices, and data storage devices. The nodes  101 _ 1  to  101 _ 6  can be suitably interconnected by optical fiber links  102 _ 1  to  102 _ 12  (collectively referenced as  102 ) establishing communication paths between the communication devices within the nodes. The optical fiber links  102  can include the fiber-optic cables described in U.S. patent application Ser. No. 16/822,103 filed on Mar. 18, 2020 and incorporated herein by reference in its entirety. U.S. patent application Ser. No. 16/822,103 is provided in Appendix D. The system  100  can also include one or more optical power supply modules  103  producing one or more light outputs, each light output comprising one or more continuous-wave (CW) optical fields and/or one or more trains of optical pulses for use in one or more of the optical communication devices of the nodes  101 _ 1  to  101 _ 6 . For illustration purposes, only one such optical power supply module  103  is shown in  FIG.  1   . A person of ordinary skill in the art will understand that some embodiments can have more than one optical power supply module  103  appropriately distributed over the system  100  and that such multiple power supply modules can be synchronized, e.g., using some of the techniques disclosed in U.S. patent application Ser. No. 16/847,705 filed on Apr. 14, 2020 and incorporated herein by reference in its entirety. U.S. patent application Ser. No. 16/847,705 is provided in Appendix B. 
     Some end-to-end communication paths can pass through an optical power supply module  103  (e.g., see the communication path between the nodes  101 _ 2  and  101 _ 6 ). For example, the communication path between the nodes  101 _ 2  and  101 _ 6  can be jointly established by the optical fiber links  102 _ 7  and  102 _ 8 , whereby light from the optical power supply module  103  is multiplexed onto the optical fiber links  102 _ 7  and  102 _ 8 . 
     Some end-to-end communication paths can pass through one or more optical multiplexing units  104  (e.g., see the communication path between the nodes  101 _ 2  and  101 _ 6 ). For example, the communication path between the nodes  101 _ 2  and  101 _ 6  can be jointly established by the optical fiber links  102 _ 10  and  102 _ 11 . Multiplexing unit  104  is also connected, through the link  102 _ 9 , to receive light from the optical power supply module  103  and, as such, can be operated to multiplex said received light onto the optical fiber links  102 _ 10  and  102 _ 11 . 
     Some end-to-end communication paths can pass through one or more optical switching units  105  (e.g., see the communication path between the nodes  101 _ 1  and  101 _ 4 ). For example, the communication path between the nodes  101 _ 1  and  101 _ 4  can be jointly established by the optical fiber links  102 _ 3  and  102 _ 12 , whereby light from the optical fiber links  102 _ 3  and  102 _ 4  is either statically or dynamically directed to the optical fiber link  102 _ 12 . 
     As used herein, the term “network element” refers to any element that generates, modulates, processes, or receives light within the system  100  for the purpose of communication. Example network elements include the node  101 , the optical power supply module  103 , the optical multiplexing unit  104 , and the optical switching unit  105 . 
     Some light distribution paths can pass through one or more network elements. For example, optical power supply module  103  can supply light to the node  101 _ 4  through the optical fiber links  102 _ 7 ,  102 _ 4 , and  102 _ 12 , letting the light pass through the network elements  101 _ 2  and  105 . 
     Various elements of the communication system  100  can benefit from the use of optical interconnects, which can use photonic integrated circuits comprising optoelectronic devices, co-packaged and/or co-integrated with electronic chips comprising integrated circuits. 
     As used herein, the term “photonic integrated circuit” (or PIC) should be construed to cover planar lightwave circuits (PLCs), integrated optoelectronic devices, wafer-scale products on substrates, individual photonic chips and dies, and hybrid devices. A substrate can be made of, e.g., one or more ceramic materials, or organic “high density build-up” (HDBU). Example material systems that can be used for manufacturing various photonic integrated circuits can include but are not limited to III-V semiconductor materials, silicon photonics, silica-on-silicon products, silica-glass-based planar lightwave circuits, polymer integration platforms, lithium niobate and derivatives, nonlinear optical materials, etc. Both packaged devices (e.g., wired-up and/or encapsulated chips) and unpackaged devices (e.g., dies) can be referred to as planar lightwave circuits. 
     Photonic integrated circuits are used for various applications in telecommunications, instrumentation, and signal-processing fields. In some implementations, a photonic integrated circuit uses optical waveguides to implement and/or interconnect various circuit components, such as for example, optical switches, couplers, routers, splitters, multiplexers/demultiplexers, filters, modulators, phase shifters, lasers, amplifiers, wavelength converters, optical-to-electrical (O/E) and electrical-to-optical (E/O) signal converters, etc. For example, a waveguide in a photonic integrated circuit can be an on-chip solid light conductor that guides light due to an index-of-refraction contrast between the waveguide&#39;s core and cladding. A photonic integrated circuit can include a planar substrate onto which optoelectronic devices are grown by an additive manufacturing process and/or into which optoelectronic devices are etched by a subtractive manufacturing processes, e.g., using a multi-step sequence of photolithographic and chemical processing steps. 
     In some implementations, an “optoelectronic device” can operate on both light and electrical currents (or voltages) and can include one or more of: (i) an electrically driven light source, such as a laser diode; (ii) an optical amplifier; (iii) an optical-to-electrical converter, such as a photodiode; and (iv) an optoelectronic component that can control the propagation and/or certain properties (e.g., amplitude, phase, polarization) of light, such as an optical modulator or a switch. The corresponding optoelectronic circuit can additionally include one or more optical elements and/or one or more electronic components that enable the use of the circuit&#39;s optoelectronic devices in a manner consistent with the circuit&#39;s intended function. Some optoelectronic devices can be implemented using one or more photonic integrated circuits. 
     As used herein, the term “integrated circuit” (IC) should be construed to encompass both a non-packaged die and a packaged die. In a typical integrated circuit-fabrication process, dies (chips) are produced in relatively large batches using wafers of silicon or other suitable material(s). Electrical and optical circuits can be gradually created on a wafer using a multi-step sequence of photolithographic and chemical processing steps. Each wafer is then cut (“diced”) into many pieces (chips, dies), each containing a respective copy of the circuit that is being fabricated. Each individual die can be appropriately packaged prior to being incorporated into a larger circuit or be left non-packaged. 
     The term “hybrid circuit” can refer to a multi-component circuit constructed of multiple monolithic integrated circuits, and possibly some discrete circuit components, all attached to each other to be mountable on and electrically connectable to a common base, carrier, or substrate. A representative hybrid circuit can include (i) one or more packaged or non-packaged dies, with some or all of the dies including optical, optoelectronic, and/or semiconductor devices, and (ii) one or more optional discrete components, such as connectors, resistors, capacitors, and inductors. Electrical connections between the integrated circuits, dies, and discrete components can be formed, e.g., using patterned conducting (such as metal) layers, ball-grid arrays, solder bumps, wire bonds, etc. Electrical connections can also be removable, e.g., by using land-grid arrays and/or compression interposers. The individual integrated circuits can include any combination of one or more respective substrates, one or more redistribution layers (RDLs), one or more interposers, one or more laminate plates, etc. 
     In some embodiments, individual chips can be stacked. As used herein, the term “stack” refers to an orderly arrangement of packaged or non-packaged dies in which the main planes of the stacked dies are substantially parallel to each other. A stack can typically be mounted on a carrier in an orientation in which the main planes of the stacked dies are parallel to each other and/or to the main plane of the carrier. 
     A “main plane” of an object, such as a die, a photonic integrated circuit, a substrate, or an integrated circuit, is a plane parallel to a substantially planar surface thereof that has the largest sizes, e.g., length and width, among all exterior surfaces of the object. This substantially planar surface can be referred to as a main surface. The exterior surfaces of the object that have one relatively large size, e.g., length, and one relatively small size, e.g., height, are typically referred to as the edges of the object. 
       FIG.  2    is a schematic cross-sectional diagram of a data processing system  200  that includes an integrated optical communication device  210  (also referred to as an optical interconnect module), a fiber-optic connector assembly  220 , a package substrate  230 , and an electronic processor integrated circuit  240 . The data processing system  200  can be used to implement, e.g., one or more of devices  101 _ 1  to  101 _ 6  of  FIG.  1   .  FIG.  3    shows an enlarged cross-sectional diagram of the integrated optical communication device  210 . 
     Referring to  FIGS.  2  and  3   , the integrated optical communication device  210  includes a substrate  211  having a first main surface  211 _ 1  and a second main surface  211 _ 2 . The main surfaces  211 _ 1  and  211 _ 2 , respectively, include arrays of electrical contacts  212 _ 1  and  212 _ 2 . In some embodiments, the minimum spacing d 1  between any two contacts within the array of contacts  212 _ 1  is larger than the minimum spacing d 2  between any two contacts within the array of contacts  212 _ 2 . In some embodiments the minimum spacing between any two contacts within the array of contacts  212 _ 2  is between 40 and 200 micrometers. In some embodiments, the minimum spacing between any two contacts within the array of contacts  212 _ 1  is between 200 micrometers and 1 millimeter. At least some of the contacts  212 _ 1  are electrically connected through the substrate  211  with at least some of the contacts  212 _ 2 . In some embodiments, the contacts  212 _ 1  can be permanently attached to a corresponding array of electrical contacts  232 _ 1  on the package substrate  230 . In some embodiments, the contacts  212 _ 1  can include mechanisms to allow the device  210  to be removably connected to the package substrate  230 , as indicated by a double arrow  233 . For example, the system can include mechanical mechanisms (e.g., one or more snap-on or screw-on mechanisms) to hold the various modules in place. In some embodiments, the contacts  212 _ 1 ,  212 _ 2 , and/or  232 _ 1  can include one or more of solder balls, metal pillars, and/or metal pads, etc. In some embodiments, the contacts  212 _ 1 , and/or  232 _ 1  can include one or more of spring-loaded elements, compression interposers, and/or land-grid arrays. 
     In some embodiments, the integrated optical communication device  210  can be connected to the electronic processor integrated circuit  240  using traces  231  embedded in one or more layers of the package substrate  230 . In some embodiments, the processor integrated circuit  240  can include monolithically embedded therein an array of serializers/deserializers (SerDes)  247  electrically coupled to the traces  231 . In some embodiments, the processor integrated circuit  240  can include electronic switching circuitry, electronic routing circuitry, network control circuitry, traffic control circuitry, computing circuitry, synchronization circuitry, time stamping circuitry, and data storage circuitry. In some implementations, the processor integrated circuit  240  can be a network switch, a central processing unit, a graphics processor unit, a tensor processing unit, a digital signal processor, or an application specific integrated circuit (ASIC). 
     Because the electronic processor integrated circuit  240  and the integrated communication device  210  are both mounted on the package substrate  230 , the electrical connectors or traces  231  can be made shorter, as compared to mounting the electronic processor integrated circuit  240  and the integrated communication device  210  on separate circuit boards. Shorter electrical connectors or traces  231  can transmit signals that have a higher data rate with lower noise, lower distortion, and/or lower crosstalk. 
     In some implementations, the electrical connectors or traces can be configured as differential pairs of transmission lines, e.g., in a ground-signal-ground-signal-ground configuration. In some examples, the speed of such signal links can be 10 Gbps or more; 56 Gbps or more; 112 Gbps or more; or 224 Gbps or more. 
     In some implementations, the integrated optical communication device  210  further includes a first optical connector part  213  having a first surface  213 _ 1  and a second surface  213 _ 2 . The connector part  213  is configured to receive a second optical connector part  223  of the fiber-optic connector assembly  220 , optically coupled to the connector part  213  through the surfaces  213 _ 1  and  223 _ 2 . In some embodiments the connector part  213  can be removably attached to the connector part  223 , as indicated by a double-arrow  234 , e.g., through a hole  235  in the package substrate  230 . In some embodiments the connector part  213  can be permanently attached to the connector part  223 . In some embodiments, the connector parts  213  and  223  can be implemented as a single connector element combining the functions of both the connector parts  213  and  223 . 
     In some implementations, the optical connector part  223  is attached to an array of optical fibers  226 . In some embodiments, the array of optical fibers  226  can include one or more of: single-mode optical fiber, multi-mode optical fiber, multi-core optical fiber, polarization-maintaining optical fiber, dispersion-compensating optical fiber, hollow-core optical fiber, or photonic crystal fiber. In some embodiments, the array of optical fibers  226  can be a linear (1D) array. In some other embodiments, the array of optical fibers  226  can be a two-dimensional (2D) array. For example, the array of optical fibers  226  can include 2 or more optical fibers, 4 or more optical fibers, 10 or more optical fibers, 100 or more optical fibers, 500 or more optical fibers, or 1000 or more optical fibers. Each optical fiber can include, e.g., 2 or more cores, or 10 or more cores, in which each core provides a distinct light path. Each light path can include a multiplex of, e.g., 2 or more, 4 or more, 8 or more, or 16 or more serial optical signals, e.g., by use of wavelength division multiplexing channels, polarization-multiplexed channels, coherent quadrature-multiplexed channels. The connector parts  213  and  223  are configured to establish light paths through the first main surface  211 _ 1  of the substrate  211 . For example, the array of optical fibers  226  can includes n1 optical fibers, each optical fiber can include n2 cores, and the connector parts  213  and  223  can establish n1×n2 light paths through the first main surface  211 _ 1  of the substrate  211 . Each light path can include a multiplex of n3 serial optical signals, resulting in a total of n1×n2×n3 serial optical signals passing through the connector parts  213  and  223 . In some embodiments, the connector parts  213  and  223  can be implemented, e.g., as disclosed in U.S. patent application Ser. No. 16/816,171. 
     In some implementations, the integrated optical communication device  210  further includes a photonic integrated circuit  214  having a first main surface  214 _ 1  and a second main surface  214 _ 2 . The photonic integrated circuit  214  is optically coupled to the connector part  213  through its first main surface  214 _ 1 , e.g., as disclosed in in U.S. patent application Ser. No. 16/816,171. For example, the connector part  213  can be configured to optically couple light to the photonic integrated circuit  214  using optical coupling interfaces, e.g., vertical grating couplers or turning mirrors. In the example above, a total of n1×n2×n3 serial optical signals can be coupled through the connector parts  213  and  223  to the photonic integrated circuit  214 . Each serial optical signal is converted to a serial electrical signal by the photonic integrated circuit  214 , and each serial electrical signal is transmitted from the photonic integrated circuit  214  to a deserializer unit, or a serializer/deserializer unit, described below. 
     In some embodiments, the connector part  213  can be mechanically connected (e.g., glued) to the photonic integrated circuit  214 . The photonic integrated circuit  214  can contain active and/or passive optical and/or opto-electronic components including optical modulators, optical detectors, optical phase shifters, optical power splitters, optical wavelength splitters, optical polarization splitters, optical filters, optical waveguides, or lasers. In some embodiments, the photonic integrated circuit  214  can further include monolithically integrated active or passive electronic elements such as resistors, capacitors, inductors, heaters, or transistors. 
     In some implementations, the integrated optical communication device  210  further includes an electronic communication integrated circuit  215  configured to facilitate communication between the array of optical fibers  226  and the electronic processor integrated circuit  240 . A first main surface  215 _ 1  of the electronic communication integrated circuit  215  is electrically coupled to the second main surface  214 _ 2  of the photonic integrated circuit  214 , e.g., through solder bumps, copper pillars, etc. The first main surface  215 _ 1  of the electronic communication integrated circuit  215  is further electrically connected to the second main surface  211 _ 2  of the substrate  211  through the array of electrical contacts  212 _ 2 . In some embodiments, the electronic communication integrated circuit  215  can include electrical pre-amplifiers and/or electrical driver amplifiers electrically coupled, respectively, to photodetectors and modulators within the photonic integrated circuit  214  (see also  FIG.  14   ). In some embodiments, the electronic communication integrated circuit  215  can include a first array of serializers/deserializers (SerDes)  216  (also referred to as a serializers/deserializers module) whose serial inputs/outputs are electrically connected to the photodetectors and the modulators of the photonic integrated circuit  214  and a second array of serializers/deserializers  217 , whose serial inputs/outputs are electrically coupled to the contacts  212 _ 1  through the substrate  211 . Parallel inputs of the array of serializers/deserializers  216  can be connected to parallel outputs of the array of serializers/deserializers  217  and vice versa through a bus processing unit  218 , which can be, e.g., a parallel bus of electrical lanes, a cross-connect device, or a re-mapping device (gearbox). For example, the bus processing unit  218  can be configured to enable switching of the signals, allowing the routing of signals to be re-mapped. For example, N×50 Gbps electrical lanes can be remapped into N/2×100 Gbps electrical lanes, N being a positive even integer. An example of a bus processing unit  218  is shown in  FIG.  40 A . 
     For example, the electronic communication integrated circuit  215  includes a first serializers/deserializers module that includes multiple serializer units and multiple deserializer units, and a second serializers/deserializers module that includes multiple serializer units and multiple deserializer units. The first serializers/deserializers module includes the first array of serializers/deserializers  216 . The second serializers/deserializers module includes the second array of serializers/deserializers  217 . 
     In some implementations, the first and second serializers/deserializers modules have hardwired functional units so that which units function as serializers and which units function as deserializers are fixed. In some implementations, the functional units can be configurable. For example, the first serializers/deserializers module is capable of operating as serializer units upon receipt of a first control signal, and operating as deserializer units upon receipt of a second control signal. Likewise, the second serializers/deserializers module is capable of operating as serializer units upon receipt of a first control signal, and operating as deserializer units upon receipt of a second control signal. 
     Signals can be transmitted between the optical fibers  226  and the electronic processor integrated circuit  240 . For example, signals can be transmitted from the optical fibers  226  to the photonic integrated circuit  214 , to the first array of serializers/deserializers  216 , to the second array of serializers/deserializers  217 , and to the electronic processor integrated circuit  240 . Similarly, signals can be transmitted from the electronic processor integrated circuit  240  to the second array of serializers/deserializers  217 , to the first array of serializers/deserializers  216 , to the photonic integrated circuit  214 , and to the optical fibers  226 . 
     In some implementations, the electronic communication integrated circuit  215  is implemented as a first integrated circuit and a second integrated circuit that are electrically coupled each other. For example, the first integrated circuit includes the array of serializers/deserializers  216 , and the second integrated circuit includes the array of serializers/deserializers  217 . 
     In some implementations, the integrated optical communication device  210  is configured to receive optical signals from the array of optical fibers  226 , generate electrical signals based on the optical signals, and transmit the electrical signals to the electronic processor integrated circuit  240  for processing. In some examples, the signals can also flow from the electronic processor integrated circuit  240  to the integrated optical communication device  210 . For example, the electronic processor integrated circuit  240  can transmit electronic signals to the integrated optical communication device  210 , which generates optical signals based on the received electronic signals, and transmits the optical signals to the array of optical fibers  226 . 
     In some implementations, the photodetectors of the photonic integrated circuit  214  convert the optical signals transmitted in the optical fibers  226  to electrical signals. In some examples, the photonic integrated circuit  214  can include transimpedance amplifiers for amplifying the currents generated by the photodetectors, and drivers for driving output circuits (e.g., driving optical modulators). In some examples, the transimpedance amplifiers and drivers are integrated with the electronic communication integrated circuit  215 . For example, the optical signal in each optical fiber  226  can be converted to one or more serial electrical signals. For example, one optical fiber can carry multiple signals by use of wavelength division multiplexing. The optical signals (and the serial electrical signals) can have a high data rate, such as 50 Gbps, 100 Gbps, or more. The first serializers/deserializers module  216  converts the serial electrical signals to sets of parallel electrical signals. For example, each serial electrical signal can be converted to a set of N parallel electrical signals, in which N can be, e.g., 2, 4, 8, 16, or more. The first serializers/deserializers module  216  conditions the serial electrical signals upon conversion into sets of parallel electrical signals, in which the signal conditioning can include, e.g., one or more of clock and data recovery, and signal equalization. The first serializers/deserializers module  216  sends the sets of parallel electrical signals to the second serializers/deserializers module  217  through the bus processing unit  218 . The second serializers/deserializers module  217  converts the sets of parallel electrical signals to high speed serial electrical signals that are output to the electrical contacts  212 _ 2  and  212 _ 1 . 
     The serializers/deserializers module (e.g.,  216 ,  217 ) can perform functions such as fixed or adaptive signal pre-distortion on the serialized signal. Also, the parallel-to-serial mapping can use a serialization factor M different from N, e.g., 50 Gbps at the input to the first serializers/deserializers module  216  can become 50×1 Gbps on a parallel bus, and two such parallel buses from two serializers/deserializers modules  216  having a total of 100×1 Gbps can then be mapped to a single 100 Gbps serial signal by the serializers/deserializers module  217 . An example of the bus processing unit  218  for performing such mapping is shown in  FIG.  40 B . Also, the high-speed modulation on the serial side can be different, e.g., the serializers/deserializers module  216  can use 50 Gbps Non-Return-to-Zero (NRZ) modulation whereas the serializers/deserializers module  217  can use 100 Gbps Pulse-Amplitude Modulation 4-Level (PAM4) modulation. In some implementations, coding (line coding or error-correction coding) can be performed at the bus processing unit  218 . The first and second serializers/deserializers modules  216  and  217  can be commercially available high quality, low power serializers/deserializers that can be purchased in bulk at a low cost. 
     In some implementations, the package substrate  230  can include connectors on the bottom side that connects the package substrate  230  to another circuit board, such as a motherboard. The connection can use, e.g., fixed (e.g., by use of solder connection) or removable (e.g., by use of one or more snap-on or screw-on mechanisms). In some examples, another substrate can be provided between the electronic processor integrated circuit  240  and the package substrate  230 . 
     Referring to  FIG.  4   , in some implementations, a data processing system  250  includes an integrated optical communication device  252  (also referred to as an optical interconnect module), a fiber-optic connector assembly  220 , a package substrate  230 , and an electronic processor integrated circuit  240 . The data processing system  250  can be used, e.g., to implement one or more of devices  101 _ 1  to  101 _ 6  of  FIG.  1   . The integrated optical communication device  252  is configured to receive optical signals, generate electrical signals based on the optical signals, and transmit the electrical signals to the electronic processor integrated circuit  240  for processing. In some examples, the signals can also flow from the electronic processor integrated circuit  240  to the integrated optical communication device  252 . For example, the electronic processor integrated circuit  240  can transmit electronic signals to the integrated optical communication device  252 , which generates optical signals based on the received electronic signals, and transmits the optical signals to the array of optical fibers  226 . 
     The system  250  is similar to the data processing system  200  of  FIG.  2    except that in the system  250 , in the direction of the cross section of the figure, a portion  254  of the top surface of the photonic integrated circuit  214  is not covered by the first serializers/deserializers module  216  and the second serializers/deserializers module  217 . For example, the portion  254  can be used to couple to other electronic components, optical components, or electro-optical components, either from the bottom (as shown in  FIG.  4   ) or from the top (as shown in  FIG.  6   ). In some examples, the first serializers/deserializers module  216  can have a high temperature during operation. The portion  254  is not covered by the first serializers/deserializers module  216  and can be less thermally coupled to the first serializers/deserializers module  216 . In some examples, the photonic integrated circuit  214  can include modulators that modulate the phases of optical signals by modifying the temperature of waveguides and thereby modifying the refractive indices of the waveguides. In such devices, using the design shown in the example of  FIG.  4    can allow the modulators to operate in a more thermally stable environment. 
       FIG.  5    shows an enlarged cross-sectional diagram of the integrated optical communication device  252 . In some implementations, the substrate  211  includes a first slab  256  and a second slab  258 . The first slab  256  provides electrical connectors to fan out the electrical contacts, and the second slab  258  provides a removable connection to the package substrate  230 . The first slab  256  includes a first set of contacts arranged on the top surface and a second set of contacts arranged on the bottom surface, in which the first set of contacts has a fine pitch and the second set of contacts has a coarse pitch. The minimum distance between contacts in the second set of contacts is greater than the minimum distance between contacts in the first set of contacts. The second slab  258  can include, e.g., spring-loaded contacts  259 . 
     Referring to  FIG.  6   , in some implementations, a data processing system  260  includes an integrated optical communication device  262  (also referred to as an optical interconnect module), a fiber-optic connector assembly  270 , a package substrate  230 , and an electronic processor integrated circuit  240 . The data processing system  260  can be used, e.g., to implement one or more of devices  101 _ 1  to  101 _ 6  of  FIG.  1   . The integrated optical communication device  262  includes a photonic integrated circuit  264 . The photonic integrated circuit  264  can include components that perform functions similar to those of the photonic integrated circuit  214  of  FIGS.  2 - 5   . The integrated optical communication device  262  further includes a first optical connector part  266  that is configured to receive a second optical connector part  268  of the fiber-optic connector assembly  270 . For example, snap-on or screw-on mechanisms can be used to hold the first and second optical connector parts  266  and  268  together. 
     The connector parts  266  and  268  can be similar to the connector parts  213  and  223 , respectively, of  FIG.  4   . In some examples, the optical connector part  268  is attached to an array of optical fibers  272 , which can be similar to the fibers  226  of  FIG.  4   . 
     The photonic integrated circuit  264  has a top main surface and bottom main surface. The terms “top” and “bottom” refer to the orientations shown in the figure. It is understood that the devices described in this document can be positioned in any orientation, so for example the “top surface” of a device can be oriented facing downwards or sideways, and the “bottom surface” of the device can be oriented facing upwards or sideways. A difference between the photonic integrated circuit  264  and the photonic integrated circuit  214  ( FIG.  4   ) is that the photonic integrated circuit  264  is optically coupled to the connector part  268  through the top main surface, whereas the photonic integrated circuit  214  is optically coupled to the connector part  213  through the bottom main surface. For example, the connector part  266  can be configured to optically couple light to the photonic integrated circuit  214  using optical coupling interfaces, e.g., vertical grating couplers or turning mirrors, similar to the way that the connector part  213  optically couples light to the photonic integrated circuit  214 . 
     The integrated optical communication devices  252  ( FIG.  4   ) and  262  ( FIG.  6   ) provide flexibility in the design of the data processing systems, allowing the fiber-optic connector assembly  220  or  270  to be positioned on either side of the package substrate  230 . 
     Referring to  FIG.  7   , in some implementations, a data processing system  280  includes an integrated optical communication device  282  (also referred to as an optical interconnect module), a fiber-optic connector assembly  270 , a package substrate  230 , and an electronic processor integrated circuit  240 . The data processing system  280  can be used, e.g., to implement one or more of devices  101 _ 1  to  101 _ 6  of  FIG.  1   . 
     The integrated optical communication device  282  includes a photonic integrated circuit  284 , a circuit board  286 , a first serializers/deserializers module  216 , a second serializers/deserializers module  217 , and a control circuit  287 . The photonic integrated circuit  284  can include components that perform functions similar to those of the photonic integrated circuit  214  ( FIGS.  2 - 5   ) and  264  ( FIG.  6   ). The control circuit  287  controls the operation of the photonic integrated circuit  284 . For example, the control circuit  287  can control one or more photodetector and/or modulator bias voltages, heater voltages, etc., either statically or adaptively based on one or more sensor voltages that the control circuit  287  can receive from the photonic integrated circuit  284 . The integrated optical communication device  282  further includes a first optical connector part  288  that is configured to receive a second optical connector part  268  of the fiber-optic connector assembly  270 . The optical connector part  268  is attached to an array of optical fibers  272 . 
     The circuit board  286  has a top main surface  290  and a bottom main surface  292 . The photonic integrated circuit  284  has a top main surface  294  and bottom main surface  296 . The first and second serializers/deserializers modules  216 ,  217  are mounted on the top main surface  290  of the circuit board  286 . The top main surface  294  of the photonic integrated circuit  284  has electrical terminals that are electrically coupled to corresponding electrical terminals on the bottom main surface  292  of the circuit board  286 . In this example, the photonic integrated circuit  284  is mounted on a side of the circuit board  286  that is opposite to the side of the circuit board  286  on which the first and second serializers/deserializers modules  216 ,  217  are mounted. The photonic integrated circuit  284  is electrically coupled to the first serializers/deserializers  216  by electrical connectors  300  that pass through the circuit board  286  in the thickness direction. In some embodiments, the electrical connectors  300  can be implemented as vias. 
     The connector part  288  has dimensions that are configured such that the fiber-optic connector assembly  270  can be coupled to the connector part  288  without bumping into other components of the integrated optical communication device  282 . The connector part  288  can be configured to optically couple light to the photonic integrated circuit  284  using optical coupling interfaces, e.g., vertical grating couplers or turning mirrors, similar to the way that the connector part  213  or  266  optically couples light to the photonic integrated circuit  214  or  264 , respectively. 
     When the integrated optical communication device  282  is coupled to the package substrate  230 , the photonic integrated circuit  284  and the control circuit  287  are positioned between the circuit board  286  and the package substrate  230 . The integrated optical communication device  282  includes an array of contacts  298  arranged on the bottom main surface  292  of the circuit board  286 . The array of contacts  298  is configured such that after the circuit board  286  is coupled to the package substrate  230 , the array of contacts  298  maintains a thickness d 3  between the circuit board  286  and the package substrate  230 , in which the thickness d 3  is slightly larger than the thicknesses of the photonic integrated circuit  284  and the control circuit  287 . 
     Referring to  FIGS.  4 - 7   , a serializer/deserializer module, a set of drivers and transimpedance amplifiers, or some combination therein may be included in an example integrated optical device, data processing system, etc. In some examples, the set of drivers and transimpedance amplifiers may be monolithically integrated into a photonic integrated circuit or into a serializiers/deserializers module. Referring to  FIG.  6   , for example, the serializer/deserializer modules may alternatively be a set of drivers and transimpedance amplifiers. 
       FIG.  8    is an exploded perspective view of the integrated optical communication device  282  of  FIG.  7   . The photonic integrated circuit  284  includes an array of optical coupling components  310 , e.g., vertical grating couplers or turning mirrors, as disclosed in U.S. patent application Ser. No. 16/816,171, that are configured to optically couple light from the optical connector part  288  to the photonic integrated circuit  214 . The optical coupling components  310  are densely packed and have a fine pitch so that optical signals from many optical fibers can be coupled to the photonic integrated circuit  284 . For example, the minimum distance between adjacent optical coupling components  310  can be as small as, e.g., 5 μm, 10 μm, 50 μm, or 100 μm. 
     An array of electrical terminals  312  arranged on the top main surface  294  of the photonic integrated circuit  284  are electrically coupled to an array of electrical terminals  314  arranged on the bottom main surface  292  of the circuit board  286 . The array of electrical terminals  312  and the array of electrical terminals  314  have a fine pitch, in which the minimum distance between two adjacent electrical terminals can be as small as, e.g., 10 μm, 40 μm, or 100 μm. An array of electrical terminals  316  arranged on the bottom main surface of the first serializers/deserializers  216  are electrically coupled to an array of electrical terminals  318  arranged on the top main surface  290  of the circuit board  286 . An array of electrical terminals  320  arranged on the bottom main surface of the second serializers/deserializers module  217  are electrically coupled an array of electrical terminals  322  arranged on the top main surface  290  of the circuit board  286 . 
     For example, the arrays of electrical terminals  312 ,  314 ,  316 ,  318 ,  320 , and  322  have a fine pitch (or fine pitches). For simplicity of description, in the example of  FIG.  8   , for each of the arrays of electrical terminals  312 ,  314 ,  316 ,  318 ,  320 , and  322 , the minimum distance between adjacent terminals is d 2 , which can be in the range of, e.g., 10 μm to 200 μm. In some examples, the minimum distance between adjacent terminals for different arrays of electrical terminals can be different. For example, the minimum distance between adjacent terminals for the arrays of electrical terminals  314  (which are arranged on the bottom surface of the circuit board  286 ) can be different from the minimum distance between adjacent terminals for the arrays of electrical terminals  318  arranged on the top surface of the circuit board  286 . The minimum distance between adjacent terminals for the arrays of electrical terminals  316  of the first serializers/deserializers  216  can be different from the minimum distance between adjacent terminals for the arrays of electrical terminals  320  of the second serializers/deserializers module  217 . 
     An array of electrical terminals  324  arranged on the bottom main surface of the circuit board  286  are electrically coupled to the array of contacts  298 . The array of electrical terminals  324  can have a coarse pitch. For example, the minimum distance between adjacent electrical terminals is d 1 , which can be in the range of, e.g., 200 μm to 1 mm. The array of contacts  298  can be configured as a module that maintains a distance that is slightly larger than the thicknesses of the photonic integrated circuit  284  and the control circuit  287  (which is not shown in  FIG.  8   ) between the integrated optical communication device  282  and the package substrate  230  after the integrated optical communication device  282  is coupled to the package substrate  230 . The array of contacts  298  can include, e.g., a substrate that has embedded spring loaded connectors. 
       FIG.  9    is a diagram of an example layout design for optical and electrical terminals of the integrated optical communication device  282  of  FIGS.  7  and  8   .  FIG.  9    shows the layout of the optical and electrical terminals when viewed from the top or bottom side of the device  282 . In this example, the photonic integrated circuit  284  has a width of about 5 mm and a length of about 2.2 mm to 18 mm. For the example in which the length of the photonic integrated circuit  284  is about 2.2 mm, the optical signals provided to the photonic integrated circuit  284  can have a total bandwidth of about 1.6 Tbps. For the example in which the length of the photonic integrated circuit is about 18 mm, the optical signals provided to the photonic integrated circuit can have a total bandwidth of about 12.8 Tbps. The width of the integrated optical communication device  282  can be about 8 mm. 
     An array  330  of optical coupling components  310  is provided to allow optical signals to be provided to the photonic integrated circuit  284  in parallel. The first serializers/deserializers  216  include an array  332  of electrical terminals  316  arranged on the bottom surface of the first serializers/deserializers  216 . The second serializers/deserializers module  217  include an array  334  of electrical terminals  320  arranged on the bottom surface of the second serializers/deserializers module  217 . The arrays  332  and  334  of electrical terminals  316 ,  320  have a fine pitch, and the minimum distance between adjacent terminals can be in the range of, e.g., 40 μm to 200 μm. An array  336  of electrical terminals  324  is arranged on the bottom main surface of the circuit board  286 . The array  336  of electrical terminals  324  has a coarse pitch, and the minimum distance between adjacent terminals can be in the range of, e.g., 200 μm to 1 mm. For example, the array  336  of electrical terminals  324  can be part of a compression interposer that has a pitch of about 400 μm between terminals. 
       FIG.  10    is a diagram of an example layout design for optical and electrical terminals of the integrated optical communication device  210  of  FIG.  2   .  FIG.  10    shows the layout of the optical and electrical terminals when viewed from the top or bottom side of the device  210 . In this embodiment, the photonic integrated circuit  214  is implemented as a single chip. In some embodiments, the photonic integrated circuit  214  can be tiled across multiple chips. Likewise, the electronic communication integrated circuit  215  is implemented as a single chip in this embodiment. In some embodiments, the electronic communication integrated circuit  215  can be tiled cross multiple chips. In this embodiment, the electronic communication integrated circuit  215  is implemented using 16 serializers/deserializers blocks  216 _ 1  to  216 _ 16  that are electrically connected to the photonic integrated circuit  214  and 16 serializers/deserializers blocks  217 _ 1  to  217 _ 16 , which are electrically connected to an array of contacts  212 _ 1  by electrical connectors that pass through the substrate  211  in the thickness direction. The 16 serializers/deserializers blocks  216 _ 1  to  216 _ 16  are electrically coupled to the 16 serializers/deserializers blocks  217 _ 1  to  217 _ 16  by bus processing units  218 _ 1  to  218 _ 16 , respectively. In this embodiment, each serializers/deserializers block ( 216  or  217 ) is implemented using 8 serial differential transmitters (TX) and 8 serial differential receivers (RX). In order to transfer the electrical signals from the serializers/deserializers blocks  217  to ASIC  240 , a total of 8×16×2=256 electrical differential signal contacts  212 _ 1  in addition to 8×17×2=272 ground (GND) contacts  212 _ 1  can be used. Other contact arrangements that beneficially reduce crosstalk, e.g., placing a ground contact between every pair of TX and RX contacts, can also be used as will be appreciated by a person skilled in the art. The transmitter contacts are collectively referenced as  340 , the receiver contacts are collectively referenced as  342 , and the ground contacts are collectively referenced as  344 . 
     The electrical contacts of the serializers/deserializers blocks  216 _ 1  to  216 _ 12  and  217 _ 1  to  217 _ 12  have a fine pitch, and the minimum distance between adjacent terminals can be in the range of, e.g., 40 μm to 200 μm. The electrical contacts  212 _ 1  have a coarse pitch, and the minimum distance between adjacent terminals can be in the range of, e.g., 200 μm to 1 mm. 
       FIG.  11    is a schematic side view of an example data processing system  350 , which includes an integrated optical communication device  374 , a package substrate  230 , and a host application specific integrated circuit  240 . The integrated optical communication device  374  and the host application specific integrated circuit  240  are mounted on the top side of the package substrate  230 . The integrated optical communication device  374  includes a first optical connector  356  that allows optical signals transmitted in optical fibers to be coupled to the integrated optical communication device  374 , in which a portion of the optical fibers connected to the first optical connector  356  are positioned at a region facing the bottom side of the package substrate  230 . 
     The integrated optical communication device  374  includes a photonic integrated circuit  352 , a combination of drivers and transimpedance amplifiers (D/T)  354 , a first serializers/deserializers module  216 , a second serializers/deserializers module  217 , the first optical connector  356 , a control module  358 , and a substrate  360 . The host application specific integrated circuit  240  includes an embedded third serializers/deserializers module  247 . 
     In this example, the photonic integrated circuit  352 , the drivers and transimpedance amplifiers  354 , the first serializers/deserializers module  216 , and the second serializers/deserializers module  217  are mounted on the top side of the substrate  360 . In some embodiments, the drivers and transimpedance amplifiers  354 , the first serializers/deserializers module  216 , and the second serializers/deserializers module  217  can be monolithically integrated into a single electrical chip. The first optical connector  356  is optically coupled to the bottom side of the photonic integrated circuit  352 . The control module  358  is electrically coupled to electrical terminals arranged on the bottom side of the substrate  360 , whereas the photonic integrated circuit  352  is connected to electrical terminals arranged on the top side of the substrate  360 . The control module  358  is electrically coupled to the photonic integrated circuit  352  through electrical connectors  362  that pass through the substrate  360  in the thickness direction. In some embodiments, the substrate  360  can be removably connected to the package substrate  230 , e.g., using a compression interposer or a land grid array. 
     The photonic integrated circuit  352  is electrically coupled to the drivers and transimpedance amplifiers  354  through electrical connectors  364  on or in the substrate  360 . The drivers and transimpedance amplifiers  354  are electrically coupled to the first serializers/deserializers module  216  by electrical connectors  366  on or in the substrate  360 . The second serializers/deserializers module  216  has electrical terminals  370  on the bottom side that are electrically coupled to electrical terminals  366  arranged on the bottom side of the substrate  360  through electrical connectors  368  that pass through the substrate  360  in the thickness direction. The electrical terminals  370  have a fine pitch, whereas the electrical terminals  366  have a coarse pitch. The electrical terminals  366  are electrically coupled to the third serializers/deserializers module  247  through electrical connectors on or in the package substrate  230 . 
     In some implementations, optical signals are converted by the photonic integrated circuit  352  to electrical signals, which are conditioned by the first serializers/deserializers module  216  (or the second serializers/deserializers module  217 ), and processed by the host application specific integrated circuit  240 . The host application specific integrated circuit  240  generates electrical signals that are converted by the photonic integrated circuit  352  into optical signals. 
       FIG.  12    is a schematic side view of an example data processing system  380 , which includes an integrated optical communication device  382 , a package substrate  230 , and a host application specific integrated circuit  240 . The integrated optical communication device  382  is similar to the integrated optical communication device  374  ( FIG.  11   ), except that the transimpedance amplifiers and drivers are implemented in a separate chip  384  from the chip housing the serializers/deserializers modules  216  and  217 . In some implementations, a serializer/deserializer module, a set of drivers and transimpedance amplifiers, or some combination therein may be included in an example data processing system. In some examples, the set of drivers and transimpedance amplifiers may be monolithically integrated into a photonic integrated circuit or into a serializiers/deserializers module. 
       FIG.  13    is a schematic side view of an example data processing system  390  that includes an integrated optical communication device  402 , a package substrate  230 , and a host application specific integrated circuit (not shown in the figure). The integrated optical communication device  402  includes photonic integrated circuit  392 , a first serializers/deserializers module  394 , a second serializers/deserializers module  396 , a third serializers/deserializers module  398 , and a fourth serializers/deserializers module  400  that are mounted on a substrate  410 . The photonic integrated circuit  392  can include transimpedance amplifiers and drivers, or such amplifiers and/or drivers can be included in the serializers/deserializers modules  394  and  398 . The first serializers/deserializers module  394  and the second serializers/deserializers module  396  are positioned on the right side of the photonic integrated circuit  392 . The third serializers/deserializers module  398  and the fourth serializers/deserializers module  400  are positioned on the left side of the photonic integrated circuit  392 . Here, the term “left” and “right” refer to the relative positions shown in the figure. It is understood that the system  390  can be positioned in any orientation so that the first serializers/deserializers module  394  and the second serializers/deserializers module  396  are not necessarily at the right side of the photonic integrated circuit  392 , and the third serializers/deserializers module  398  and the fourth serializers/deserializers module  400  are not necessarily at the left side of the photonic integrated circuit  392 . 
     The photonic integrated circuit  392  receives optical signals from a first optical connector  404 , generates serial electrical signals based on the optical signals, sends the serial electrical signals to the first and second serializers/deserializers modules  394  and  398 . The first and second serializers/deserializers modules  394  and  398  generate parallel electrical signals based on the received serial electrical signals, and send the parallel electrical signals to the third and fourth serializers/deserializers modules  396  and  400 , respectively. The third and fourth serializers/deserializers modules  396  and  400  generate serial electrical signals based on the received parallel electrical signals, and send the serial electrical signals to electrical terminals  406  and  408 , respectively, arranged on the bottom side of the substrate  410 . 
     The first optical connector  404  is optically coupled to the bottom side of the photonic integrated circuit  392 . In some embodiments, the optical connector  404  can also be placed on the top of the photonic integrated circuit  392  and couple light to the top side of the photonic integrated circuit  392  (not shown in the figure). The first optical connector  404  is optically coupled to a second optical connector, which in turn is optically coupled to a plurality of optical fibers. In the configuration shown in  FIG.  13   , the first optical connector  404 , the second optical connector, and/or the optical fibers pass through an opening  412  in the package substrate  230 . The electrical terminals  406  are arranged on the right side of the first optical connector  404 , and the electrical terminals  408  are arranged on the left side of the first optical connector  404 . The electrical terminals  406  and  408  are configured such that the substrate  410  can be removably coupled to the package substrate  230 . 
       FIG.  14    is a schematic side view of an example data processing system  420  that includes an integrated optical communication device  428 , a package substrate  230 , and a host application specific integrated circuit (not shown in the figure). The integrated optical communication device  428  includes a photonic integrated circuit  422  (which does not include a transimpedance amplifier and driver), a first serializers/deserializers module  394 , a second serializers/deserializers module  396 , a third serializers/deserializers module  398 , and a fourth serializers/deserializers module  400  that are mounted on a substrate  410 . The integrated optical communication device  428  includes a first set of transimpedance amplifiers and driver circuits  424  positioned at the right of the photonic integrated circuit  422 , and a second set of transimpedance amplifiers and driver circuits  426  positioned at the left of the photonic integrated circuit  422 . The first set of transimpedance amplifiers and driver circuits  424  is positioned between the photonic integrated circuit  422  and a first serializers/deserializers module  394 . The second set of transimpedance amplifiers and driver circuits  424  is positioned between the photonic integrated circuit  422  and a third serializers/deserializers module  398 . 
     In some implementations, the integrated optical communication device  402  (or  408 ) can be modified such that the first optical connector  404  couples optical signals to the top side of the photonic integrated circuit  392  (or  422 ). 
     In some implementations, a serializer/deserializer module, a set of drivers and transimpedance amplifiers, or some combination therein may be included in an example integrated optical communication device (e.g., integrated optical communication device  428 ), data processing system (e.g., data processing system  420 .) In some examples, the set of drivers and transimpedance amplifiers may be monolithically integrated into a photonic integrated circuit or into a serializiers/deserializers module. 
       FIG.  32    is a schematic side view of an example data processing system  510  that includes an integrated optical communication device  512 , a package substrate  230 , and a host application specific integrated circuit (not shown in the figure). The integrated optical communication device  512  includes a substrate  514  that includes a first slab  516  and a second slab  518 . The first slab  516  provides electrical connectors to fan out the electrical contacts. The first slab  516  includes a first set of contacts arranged on the top surface and a second set of contacts arranged on the bottom surface, in which the first set of contacts has a fine pitch and the second set of contacts has a coarse pitch. The second slab  518  provides a removable connection to the package substrate  230 . A photonic integrated circuit  524  is mounted on the bottom side of the first slab  516 . A first optical connector  520  passes through an opening in the substrate  514  and couples optical signals to the top side of the photonic integrated circuit  524 . 
     A first serializers/deserializers module  394 , a second serializers/deserializers module  396 , a third serializers/deserializers module  398 , and a fourth serializers/deserializers module  400  are mounted on the top side of the first slab  516 . The photonic integrated circuit  524  is electrically coupled to the first and third serializers/deserializers modules  394  and  398  by electrical connectors  522  that pass through the substrate  514  in the thickness direction. For example, the electrical connectors  522  can be implemented as vias. In some examples, drivers and transimpedance amplifiers can be integrated in the photonic integrated circuit  524 , or integrated in the serializers/deserializers modules  394  and  398 . In some examples, the drivers and transimpedance amplifiers can be implemented in a separate chip (not shown in the figure) positioned between the photonic integrated circuit  524  and the serializers/deserializers modules  394  and  398 , similar to the example in  FIG.  14   . A control chip (not shown in the figure) can be provided to control the operation of the photonic integrated circuit  512 . 
       FIG.  15    is a bottom view of an example of the integrated optical communication device  428  of  FIG.  14   . The photonic integrated circuit  422  includes modulator and photodetector blocks on both sides of a center line  432  in the longitudinal direction. The photonic integrated circuit  422  includes a fiber coupling region  430  arranged either at the bottom side of the photonic integrated circuit  392  or at the top side of the photonic integrated circuit (see  FIG.  32   ), in which the fiber coupling region  430  includes multiple optical coupling elements  310 , e.g., receiver optical coupling elements (RX), transmitter optical coupling elements (TX), and remote optical power supply (e.g.,  103  in  FIG.  1   ) optical coupling elements (PS). 
     Complementary metal oxide semiconductor (CMOS) transimpedance amplifier and driver blocks  424  are arranged on the right side of the photonic integrated circuit  424 , and CMOS transimpedance amplifier and driver blocks  426  are arranged on the left side of the photonic integrated circuit  424 . A first serializers/deserializers module  394  and a second serializers/deserializers module  396  are arranged on the right side of the CMOS transimpedance amplifier and driver blocks  424 . A third serializers/deserializers module  398  and a fourth serializers/deserializers module  400  are arranged on the left side of the CMOS transimpedance amplifier and driver blocks  426 . 
     In this example, each of the first, second, third, and fourth serializers/deserializers module  394 ,  396 ,  398 ,  400  includes 8 serial differential transmitter blocks and 8 serial differential receiver blocks. The integrated optical communication device  428  has a width of about 3.5 mm and a length of slightly more than about 3.6 mm. 
       FIG.  16    is a bottom view of an example of the integrated optical communication device  428  of  FIG.  14   , in which the electrical terminals  406  and  408  are also shown. As shown in the figure, the electrical terminals  406  and  408  have a coarse pitch, the minimum distance between terminals in the array of electrical terminals  406  or  408  is much larger than the minimum distance between terminals in the array of electrical terminals of the first, second, third, and fourth serializers/deserializers modules  394 ,  396 ,  398 , and  400 . For example, the array of electrical terminals  406  and  408  can be part of a compression interposer that has a pitch of about 400 μm between terminals. 
     In some implementations, the electrical terminals (e.g.,  406  and  408 ) can be arranged in a configuration as shown in  FIG.  66   .  FIG.  66    shows a pad map  1020  that shows the locations of various contact pads as viewed from the bottom of the package. The contact pads occupy an area that is 9.8 mm square, in which 400 μm pitch pads are used. 
     The middle rectangle  1022  is a cutout that connects the photonic integrated circuit to the optics that leave from the top of the module. The bigger rectangle  1024  represents the photonic integrated circuit. The two gray rectangles  1026   a ,  1026   b  represent circuitry in a serializers/deserializers chip. The serializers/deserializers chip is on positioned the top of the package, and the photonic integrated circuit is positioned on the bottom of the package. The overlap between the photonic integrated circuit and the serializers/deserializers is designed so that vias (not shown in the figure) can directly connect these two integrated circuits through the package. 
     In the examples of the data processing systems shown in  FIGS.  2 - 8 ,  11 - 14 , and  32   , the integrated optical communication device (e.g.,  210 ,  252 ,  262 ,  282 ,  374 ,  382 ,  402 ,  428 ,  512 , which includes the photonic integrated circuit and the serializers/deserializers modules) is mounted on the package substrate  230  on the same side (top side in the examples shown in the figures) as the electronic processor integrated circuit (or host application specific integrated circuit)  240 . The data processing systems can also be modified such that the integrated optical communication device is mounted on the package substrate  230  on the opposite side as the electronic processor integrated circuit (or host application specific integrated circuit)  240 . For example, the electronic processor integrated circuit  240  can be mounted on the top side of the package substrate  230  and one or more integrated optical communication devices of the form disclosed in  FIGS.  2 - 8 ,  11 - 14 , and  32    can be mounted on the bottom side of the package substrate  230 . 
       FIG.  17    is a diagram showing four types of integrated optical communication devices that can be used in a data processing system  440 . In these examples, the integrated optical communication device does not include serializers/deserializers modules. At least some of the signal conditioning is performed by the serializers/deserializers module(s) in the digital application specific integrated circuit. The integrated optical communication device is mounted on the side of the printed circuit board that is opposite to the side on which the digital application specific integrated circuit is mounted, allowing the connectors to be short. 
     In a first example, the data processing system includes a digital application specific integrated circuit  444  mounted on the top side of a substrate  442 , and an integrated optical communication device  448  mounted on the bottom side of the first circuit board. In some implementations, the integrated optical communication device  448  includes a photonic integrated circuit  450  and a set of transimpedance amplifiers and drivers  452  that are mounted on the bottom side of a substrate  454  (e.g., a second circuit board). The top side of the photonic integrated circuit  450  is electrically coupled to the bottom side of the substrate  454 . A first optical connector part  456  is optically coupled to the bottom side of the photonic integrated circuit  450 . The first optical connector part  456  is configured to be optically coupled to a second optical connector part  458  that is optically coupled to a plurality of optical fibers (not shown in the figure). An array of electrical terminals  460  is arranged on the top side of the substrate  454  and configured to enable the integrated optical communication device  448  to be removably coupled to the substrate  442 . 
     The optical signals from the optical fibers are processed by the photonic integrated circuit  450 , which generates serial electrical signals based on the optical signals. The serial electrical signals are amplified by the set of transimpedance amplifiers and drivers  452 , which drives the output signals that are transmitted to a serializers/deserializers module  446  embedded in the digital application specific integrated circuit  444 . 
     In a second example, an integrated optical communication device  462  can be mounted on the bottom side of the substrate  442  to provide an optical/electrical communications interface between the optical fibers and the digital application specific integrated circuit  444 . The integrated optical communication device  462  includes a photonic integrated circuit  464  that is mounted on the bottom side of a substrate  454  (e.g., a second circuit board). The top side of the photonic integrated circuit  464  is electrically coupled to the bottom side of the substrate  454 . A first optical connector part  456  is optically coupled to the bottom side of the photonic integrated circuit  450 . An array of electrical terminals  460  is arranged on the top side of the substrate  454  and configured to enable the integrated optical communication device  462  to be removably coupled to the substrate  442 . The integrated optical communication device  462  is similar to the integrated optical communication device  448 , except that either the photonic integrated circuit  464  or the serializers/deserializers module  446  includes the set of transimpedance amplifiers and driver circuitry. In some examples, the serializers/deserializers module  446  is configured to directly accept electrical signals emerging from photonic integrated circuit  464 , e.g., by having a high enough receiver input impedance that converts the photocurrent generated within the photonic integrated circuit  464  to a voltage swing suitable for further electrical processing. For example, the serializers/deserializers module  446  is configured to have a low transmitter output impedance, and provide an output voltage swing that allows direct driving of optical modulators embedded within the photonic integrated circuit  464 . 
     In a third example, an integrated optical communication device  466  can be mounted on the bottom side of the substrate  442  to provide an optical/electrical communications interface between the optical fibers and the digital application specific integrated circuit  444 . The integrated optical communication device  466  includes a photonic integrated circuit  468  that is mounted on the top side of a substrate  470  (e.g., a second circuit board). The bottom side of the photonic integrated circuit  468  is electrically coupled to the top side of the substrate  470 . A first optical connector part  456  is optically coupled to the bottom side of the photonic integrated circuit  468 . An array of electrical terminals  460  is arranged on the top side of the substrate  470  and configured to enable the integrated optical communication device  466  to be removably coupled to the substrate  442 . In some examples, either the photonic integrated circuit  468  or the serializers/deserializers module  446  includes the set of transimpedance amplifiers and driver circuitry. In some examples, the serializers/deserializers module  446  is configured to directly accept electrical signals emerging from the photonic integrated circuit  464 . 
     In a fourth example, an integrated optical communication device  472  can be mounted on the bottom side of the substrate  442  to provide an optical/electrical communications interface between the optical fibers and the digital application specific integrated circuit  444 . The integrated optical communication device  472  includes a photonic integrated circuit  474  and a set of transimpedance amplifiers and drivers  476  that are mounted on the top side of a substrate  470  (e.g., a second circuit board). The bottom side of the photonic integrated circuit  474  is electrically coupled to the top side of the substrate  470 . A first optical connector part  456  is optically coupled to the bottom side of the photonic integrated circuit  468 . An array of electrical terminals  460  is arranged on the top side of the substrate  470  and configured to enable the integrated optical communication device  466  to be removably coupled to the substrate  442 . The integrated optical communication device  472  is similar to the integrated optical communication device  466 , except that neither the photonic integrated circuit  464  nor the serializers/deserializers module  446  include a set of transimpedance amplifiers and driver circuitry, and the set of transimpedance amplifiers and drivers  476  is implemented as a separate integrated circuit. 
     In some implementations, a serializer/deserializer module, a set of drivers and transimpedance amplifiers, or some combination therein may be included in an example integrated optical communication device (e.g., integrated optical communication device  472 ), data processing system (e.g., data processing system  440 .) In some examples, the set of drivers and transimpedance amplifiers may be monolithically integrated into a photonic integrated circuit or into a serializiers/deserializers module. As an example, the PIC  464  may include a set of monolithically integrated drivers and transimpedance amplifiers. 
       FIG.  18    is a diagram of an example octal serializers/deserializers block  480  that includes 8 serial differential transmitters (TX)  482  and 8 serial differential receivers (RX)  484 . Each serial differential receiver  484  receives a serial differential signal, generates parallel signals based on the serial differential signal, and provides the parallel signals on the parallel bus  488 . Each serial differential transmitter  482  receives parallel signals from the parallel bus  488 , generates a serial differential signal based on the parallel signals, and provides the serial differential signal on an output electrical terminal  490 . The serializers/deserializers block  480  outputs and/or receives parallel signals through a parallel bus interface  492 . 
     In the examples described above, such as those shown in  FIGS.  2 - 14   , the integrated optical communication device (e.g.,  210 ,  252 ,  262 ,  282 ,  374 ,  382 ,  402 ,  428 ) includes a first serializers/deserializers module (e.g.,  216 ,  394 ,  398 ) and a second serializers/deserializers module (e.g.,  217 ,  396 ,  400 ). The first serializers/deserializers module serially interfaces with the photonic integrated circuit, and the second serializers/deserializers module serially interfaces with the electronic processor integrated circuit or host application specific integrated circuit (e.g.,  240 ). In some implementations, the electronic communication integrated circuit  215  includes an array of serializers/deserializers that can be logically partitioned into a first sub-array of serializers/deserializers and a second sub-array of serializers/deserializers. The first sub-array of serializers/deserializers corresponds to the serializers/deserializers module (e.g.,  216 ,  394 ,  398 ), and the second sub-array of serializers/deserializers corresponds to the second serializers/deserializers module (e.g.,  217 ,  396 ,  400 ). 
       FIG.  38    is a diagram of an example octal serializers/deserializers block  480  coupled to a bus processing unit  218 . The octal serializers/deserializers block  480  includes 8 serial differential transmitters (TX 1  to TX 8 )  482  and 8 serial differential receivers (RX 1  to RX 4 )  484 . In some implementations, the transmitters and receivers are partitioned such that the transmitters TX 1 , TX 2 , TX 3 , TX 4  and receivers RX 1 , RX 2 , RX 3 , RX 4  form a first serializers/deserializers module  840 , and the transmitters TX 5 , TX 6 , TX 7 , TX 8  and receivers RX 5 , RX 6 , RX 7 , RX 8  form a second serializers/deserializers module  842 . Serial electrical signals received at the receivers RX 1 , RX 2 , RX 3 , RX 4  are converted to parallel electrical signals and routed by the bus processing unit  218  to the transmitters TX 5 , TX 6 , TX 7 , TX 8 , which convert the parallel electrical signals to serial electrical signals. For example, the photonic integrated circuit can send serial electrical signals to the receivers RX 1 , RX 2 , RX 3 , RX 4 , and the transmitters TX 5 , TX 6 , TX 7 , TX 8  can transmit serial electrical signals to the electronic processor integrated circuit or host application specific integrated circuit. 
     For example, the bus processing unit  218  can re-map the lanes of signals and perform coding on the signals, such that the bit rate and/or modulation format of the serial signals output from the transmitters TX 5 , TX 6 , TX 7 , TX 8  can be different from the bit rate and/or modulation format of the serial signals received at the receivers RX 1 , RX 2 , RX 3 , RX 4 . For example, 4 lanes of T Gbps NRZ serial signals received at the receivers RX 1 , RX 2 , RX 3 , RX 4  can be re-encoded and routed to transmitters TX 5 , TX 6  to output 2 lanes of 2×T Gbps PAM4 serial signals. 
     Similarly, serial electrical signals received at the receivers RX 5 , RX 6 , RX 7 , RX 8  are converted to parallel electrical signals and routed by the bus processing unit  218  to the transmitters TX 1 , TX 2 , TX 3 , TX 4 , which convert the parallel electrical signals to serial electrical signals. For example, the electronic processor integrated circuit or host application specific integrated circuit can send serial electrical signals to the receivers RX 5 , RX 6 , RX 7 , RX 8 , and the transmitters TX 1 , TX 2 , TX 3 , TX 4  can transmit serial electrical signals to the photonic integrated circuit. 
     For example, the bus processing unit  218  can re-map the lanes of signals and perform coding on the signals, such that the bit rate and/or modulation format of the serial signals output from the transmitters TX 1 , TX 2 , TX 3 , TX 4  can be different from the bit rate and/or modulation format of the serial signals received at the receivers RX 5 , RX 6 , RX 7 , RX 8 . For example, 2 lanes of 2×T Gbps PAM4 serial signals received at receivers RX 5 , RX 6  can be re-encoded and routed to the transmitters TX 5 , TX 6 , TX 7 , TX 8  to output 4 lanes of T Gbps NRZ serial signals. 
       FIG.  39    is a diagram of another example octal serializers/deserializers block  480  coupled to a bus processing unit  218 , in which the transmitters and receivers are partitioned such that the transmitters TX 1 , TX 2 , TX 5 , TX 6  and receivers RX 1 , RX 2 , RX 5 , RX 6  form a first serializers/deserializers module  850 , and the transmitters TX 3 , TX 4 , TX 7 , TX 8  and receivers RX 3 , RX 4 , RX 7 , RX 8  form a second serializers/deserializers module  852 . Serial electrical signals received at the receivers RX 1 , RX 2 , RX 5 , RX 6  are converted to parallel electrical signals and routed by the bus processing unit  218  to the transmitters TX 3 , TX 4 , TX 7 , TX 8 , which convert the parallel electrical signals to serial electrical signals. For example, the photonic integrated circuit can send serial electrical signals to the receivers RX 1 , RX 2 , RX 5 , RX 6 , and the transmitters TX 3 , TX 4 , TX 7 , TX 8  can transmit serial electrical signals to the electronic processor integrated circuit or host application specific integrated circuit. 
     Similarly, serial electrical signals received at the receivers RX 3 , RX 4 , RX 7 , RX 8  are converted to parallel electrical signals and routed by the bus processing unit  218  to the transmitters TX 1 , TX 2 , TX 5 , TX 6 , which convert the parallel electrical signals to serial electrical signals. For example, the electronic processor integrated circuit or host application specific integrated circuit can send serial electrical signals to the receivers RX 3 , RX 4 , RX 7 , RX 8 , and the transmitters TX 1 , TX 2 , TX 5 , TX 6  can transmit serial electrical signals to the photonic integrated circuit. 
     In some implementations, the bus processing unit  218  can re-map the lanes of signals and perform coding on the signals, such that the bit rate and/or modulation format of the serial signals output from the transmitters TX 3 , TX 4 , TX 7 , TX 8  can be different from the bit rate and/or modulation format of the serial signals received at the receivers RX 1 , RX 2 , RX 5 , RX 6 . Similarly, the bus processing unit  218  can re-map the lanes of signals and perform coding on the signals such that the bit rate and/or modulation format of the serial signals output from the transmitters TX 1 , TX 2 , TX 5 , TX 6  can be different from the bit rate and/or modulation format of the serial signals received at the receivers RX 4 , RX 4 , RX 7 , RX 8 . 
       FIGS.  38  and  39    show two examples of how the receivers and transmitters can be partitioned to form the first serializers/deserializers module and the second serializers/deserializers module. The partitioning can be arbitrarily determined based on application, and is not limited to the examples shown in  FIGS.  38  and  39   . The partitioning can be programmable and dynamically changed by the system. 
       FIG.  19    is a diagram of an example electronic communication integrated circuit  480  that includes a first octal serializers/deserializers block  482  electrically coupled to a second octal serializers/deserializers block  484 . For example, the electronic communication integrated circuit  480  can be used as the electronic communication integrated circuit  215  of  FIGS.  2  and  3   . The first octal serializers/deserializers block  482  can be used as the first serializers/deserializers module  216 , and the second octal serializers/deserializers block  484  can be used as the second serializers/deserializers module  217 . For example, the first octal serializers/deserializers block  482  can receive 8 serial differential signals, e.g., through electrical terminals arranged at the bottom side of the block, and generate 8 sets of parallel signals based on the 8 serial differential signals, in which each set of parallel signals is generated based on the corresponding serial differential signal. The first octal serializers/deserializers block  482  can condition serial electrical signals upon conversion into the 8 sets of parallel signals, such as performing clock and data recovery, and/or signal equalization. The first octal serializers/deserializers block  482  transmits the 8 sets of parallel signals to the second octal serializers/deserializers block  484  through a parallel bus  485  and a parallel bus  486 . The second octal serializers/deserializers block  484  can generate 8 serial differential signals based on the 8 sets of parallel signals, in which each serial differential signal is generated based on the corresponding set of parallel signals. The second octal serializers/deserializers block  484  can output the 8 serial differential signals through, e.g., electrical terminals arranged at the bottom side of the block. 
     Multiple serializers/deserializers blocks can be electrically coupled to multiple serializers/deserializers blocks through a bus processing unit that can be, e.g., a parallel bus of electrical lanes, a static or a dynamically reconfigurable cross-connect device, or a re-mapping device (gearbox).  FIG.  33    is a diagram of an example electronic communication integrated circuit  530  that includes a first octal serializers/deserializers block  532  and a second octal serializers/deserializers block  534  electrically coupled to a third octal serializers/deserializers block  536  through a bus processing unit  538 . In this example, the bus processing unit  538  is configured to enable switching of the signals, allowing the routing of signals to be re-mapped, in which 8×50 Gbps serial electrical signals using NRZ modulation that are serially interfaced to the first and second octal serializers/deserializers blocks  532  and  534  are re-routed or combined into 8×100 Gbps serial electrical signals using PAM4 modulation that are serially interfaced to the third octal serializers/deserializers block  536 . An example of the bus processing unit  538  is shown in  FIG.  41 A . In some examples, the bus processing unit  538  enables N lanes of T Gbps serial electrical signals to be remapped into N/M lanes of M×T Gbps serial electrical signals, N and M being positive integers, T being a real value, in which the N serially interfacing electrical signals can be modulated using a first modulation format and the M serially interfacing electrical signals can be modulated using a second modulation format. 
     In some other examples, the bus processing unit  538  can allow for redundancy to increase reliability. For example, the first and the second serializers/deserializers blocks  532  and  534  can be jointly configured to serially interface to a total of N lanes of T×N/(N−k) Gbps electrical signals, while the third serializers/deserializers block  536  can be configured to serially interface to N lanes of T Gbps electrical signals. The bus processing unit  538  can then be configured to remap the data from only N-k out of the N lanes serially interfacing to the first and the second serializers/deserializers blocks  532  and  534  (carrying an aggregate bit rate of (N−k)×T×N/(N−k)=T×N) to the third serializers/deserializers block  536 . This way, the bus processing unit  538  allows fork out of N serially interfacing electrical links to the first and the second serializers/deserializers blocks  532  and  534  to fail while still maintaining an aggregate of T×N Gbps of data serially interfacing to the third serializers/deserializers block  536 . The number k is a positive integer. In some embodiments, k can be approximately 1% of N. In some other embodiments, k can be approximately 10% of N. In some embodiment, the selection of which N−k of the N serially interfacing electrical links to the first and the second serializers/deserializers blocks  532  and  534  to remap to the third serializers/deserializers block  536  using bus processing unit  538  can be dynamically selected, e.g., based on signal integrity and signal performance information extracted from the serially interfacing signals by the serializers/deserializers blocks  532  and  534 . An example of the bus processing unit  538  is shown in  FIG.  41 B , in which N=16, k=2, T=50 Gbps. 
     In some examples, using the redundancy technique discussed above, the bus processing unit  538  enables N lanes of T×N/(N−k) Gbps serial electrical signals to be remapped into N/M lanes of M×T Gbps serial electrical signals. The bus processing unit  538  enables k out of N serially interfacing electrical links to fail while still maintaining an aggregate of T×N Gbps of data serially interfacing to the third serializers/deserializers block  536 . 
       FIG.  20    is a functional block diagram of an example data processing system  200 , which can be used to implement, e.g., one or more of devices  101 _ 1  to  101 _ 6  of  FIG.  1   . Without implied limitation, the data processing system  200  is shown as part of the node  101 _ 1  for illustration purposes. The data processing system  200  can be part of any other network element of the system  100 . The data processing system  200  includes an integrated communication device  210 , a fiber-optic connector assembly  220 , a package substrate  230 , and an electronic processor integrated circuit  240 . 
     The connector assembly  220  includes a connector  223  and a fiber array  226 . The connector  223  can include multiple individual fiber-optic connectors  423 _i (i∈{R 1  . . . RM; S 1  . . . SK; T 1  . . . TN} with K, M, and N being positive integers). In some embodiments, some or all of the individual connectors  423 _i can form a single physical entity. In some embodiments some or all of the individual connectors  423 _i can be separate physical entities. When operating as part of the network element  101 _ 1  of the system  100 , (i) the connectors  423 _S 1  through  423 _SK can be connected to optical power supply  103 , e.g., through link  102 _ 6 , to receive supply light; (ii) the connectors  423 _R 1  through  423 _RM can be connected to the transmitters of the node  101 _ 2 , e.g., through the link  102 _ 1 , to receive from the node  101 _ 2  optical communication signals; and (iii) the connectors  423 _T 1  through  423 _TN can be connected to the receivers of the node  101 _ 2 , e.g., through the link  102 _ 1 , to transmit to the node  101 _ 2  optical communication signals. 
     In some implementations, the communication device  210  includes an electronic communication integrated circuit  215 , a photonic integrated circuit  214 , a connector part  213 , and a substrate  211 . The connector part  213  can include multiple individual optical connectors  413 _i to photonic integrated circuit  214  (i∈{R 1  . . . RM; S 1  . . . SK; T 1  . . . TN} with K, M, and N being positive integers). In some embodiments, some or all of the individual connectors  413 _i can form a single physical entity. In some embodiments some or all of the individual connectors  413 _i can be separate physical entities. The optical connectors  413 _i are configured to optically couple light to the photonic integrated circuit  214  using optical coupling interfaces  414 , e.g., vertical grating couplers, turning mirrors, etc., as disclosed in U.S. patent application Ser. No. 16/816,171. 
     In operation, light entering the photonic integrated circuit  214  from the link  102 _ 6  through coupling interfaces  414 _S 1  through  414 _SK can be split using an optical splitter  415 . The optical splitter  415  can be an optical power splitter, an optical polarization splitter, an optical wavelength demultiplexer, or any combination or cascade thereof, e.g., as disclosed in U.S. patent application Ser. No. 16/847,705 and in U.S. patent application Ser. No. 16/888,890, filed on Jun. 1, 2020, which is incorporated herein by reference in its entirety. U.S. patent application Ser. No. 16/888,890 is provided as Appendix C. In some embodiments, one or more splitting functions of the splitter  415  can be integrated into the optical coupling interfaces  414  and/or into optical connectors  413 . For example, in some embodiments, a polarization-diversity vertical grating coupler can be configured to simultaneously act as a polarization splitter  415  and as a part of optical coupling interface  414 . In some other embodiments, an optical connector that includes a polarization-diversity arrangement can simultaneously act as an optical connector  413  and as a polarization splitter  415 . 
     In some embodiments, light at one or more outputs of the splitter  415  can be detected using a receiver  416 , e.g., to extract synchronization information as disclosed in U.S. patent application Ser. No. 16/847,705. In various embodiments, the receiver  416  can include one or more p-i-n photodiodes, one or more avalanche photodiodes, one or more self-coherent receivers, or one or more analog (heterodyne/homodyne) or digital (intradyne) coherent receivers. In some embodiments, one or more opto-electronic modulators  417  can be used to modulate onto light at one or more outputs of the splitter  415  data for communication to other network elements. 
     Modulated light at the output of the modulators  417  can be multiplexed in polarization or wavelength using a multiplexer  418  before leaving the photonic integrated circuit  214  through optical coupling interfaces  414 _T 1  through  414 _TN. In some embodiments, the multiplexer  418  is not provided, i.e., the output of each modulator  417  can be directly coupled to a corresponding optical coupling interface  414 . 
     On the receiver side, light entering the photonic integrated circuit  214  through a coupling interfaces  414 _R 1  through  414 _RM from, e.g., the link  101 _ 2 , can first be demultiplexed in polarization and/or in wavelength using an optical demultiplexer  419 . The outputs of the demultiplexer  419  are then individually detected using receivers  421 . In some embodiments, the demultiplexer  419  is not provided, i.e., the output of each coupling interface  414 _R 1  through  414 _RM can be directly coupled to a corresponding receiver  421 . In various embodiments, the receiver  421  can include one or more p-i-n photodiodes, one or more avalanche photodiodes, one or more self-coherent receivers, or one or more analog (heterodyne/homodyne) or digital (intradyne) coherent receivers. 
     The photonic integrated circuit  214  is electrically coupled to the integrated circuit  215 . In some implementations, the photonic integrated circuit  214  provides a plurality of serial electrical signals to the first serializers/deserializers module  216 , which generates sets of parallel electrical signals based on the serial electrical signals, in which each set of parallel electrical signal is generated based on a corresponding serial electrical signal. The first serializers/deserializers module  216  conditions the serial electrical signals, demultiplexes them into the sets of parallel electrical signals and sends the sets of parallel electrical signals to the second serializers/deserializers module  217  through a bus processing unit  218 . In some implementations, the bus processing unit  218  enables switching of signals and performs line coding and/or error-correcting coding functions. An example of the bus processing unit  218  is shown in  FIG.  42   . 
     The second serializers/deserializers module  217  generates a plurality of serial electrical signals based on the sets of parallel electrical signals, in which each serial electrical signal is generated based on a corresponding set of parallel electrical signal. The second serializers/deserializers module  217  sends the serial electrical signals through electrical connectors that pass through the substrate  211  in the thickness direction to an array of electrical terminals  500  that are arranged on the bottom surface of the substrate  211 . For example, the array of electrical terminals  500  configured to enable the integrated communication device  210  to be easily coupled to, or removed from, the package substrate  230 . 
     In some implementations, the electronic processor integrated circuit  240  includes a data processor  502  and an embedded third serializers/deserializers module  504 . The third serializers/deserializers module  504  receives the serial electrical signals from the second serializers/deserializers module  217 , and generates sets of parallel electrical signals based on the serial electrical signals, in which each set of parallel electrical signal is generated based on a corresponding serial electrical signal. The data processor  502  processes the sets of parallel signals generated by the third serializers/deserializers module  504 . 
     In some implementations, the data processor  502  generates sets of parallel electrical signals, and the third serializers/deserializers module  504  generates serial electrical signals based on the sets of parallel electrical signals, in which each serial electrical signal is generated based on a corresponding set of parallel electrical signal. The serial electrical signals are sent to the second serializers/deserializers module  217 , which generates sets of parallel electrical signals based on the serial electrical signals, in which each set of parallel electrical signal is generated based on a corresponding serial electrical signal. The second serializers/deserializers module  217  sends the sets of parallel electrical signals to the first serializers/deserializers module  216  through the bus processing unit  218 . The first serializers/deserializers module  216  generates serial electrical signals based on the sets of parallel electrical signals, in which each serial electrical signal is generated based on a corresponding set of parallel electrical signals. The first serializers/deserializers module  216  sends the serial electrical signals to the photonic integrated circuit  214 . The opto-electronic modulators  417  modulate optical signals based on the serial electrical signals, and the modulated optical signals are output from the photonic integrated circuit  214  through optical coupling interfaces  414 _T 1  through  414 _TN. 
     In some embodiments, supply light from the optical power supply  103  includes an optical pulse train, and synchronization information extracted by the receiver  416  can be used by the serializers/deserializers module  216  to align the electrical output signals of the serializers/deserializers module  216  with respective copies of the optical pulse trains at the outputs of the splitter  415  at the modulators  417 . For example, the optical pulse train can be used as an optical power supply at the optical modulator. In some such implementations, the first serializers/deserializers module  216  can include interpolators or other electrical phase adjustment elements. 
     Referring to  FIG.  21   , in some implementations, a data processing system  540  includes an enclosure or housing  542  that has a front panel  544 , a bottom panel  546 , side panels  548  and  550 , a rear panel  552 , and a top panel (not shown in the figure). The system  540  includes a printed circuit board  558  that extends substantially parallel to the bottom panel  546 . A data processing chip  554  is mounted on the printed circuit board  558 , in which the chip  554  can be, e.g., a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, or an application specific integrated circuit (ASIC). 
     At the front panel  544  are pluggable input/output interfaces  556  that allow the data processing chip  554  to communicate with other systems and devices. For example, the input/output interfaces  556  can receive optical signals from outside of the system  540  and convert the optical signals to electrical signals for processing by the data processing chip  554 . The input/output interfaces  556  can receive electrical signals from the data processing chip  554  and convert the electrical signals to optical signals that are transmitted to other systems or devices. For example, the input/output interfaces  556  can include one or more of small form-factor pluggable (SFP), SFP+, SFP28, QSFP, QSFP28 or QSFP56 transceivers. The electrical signals from the transceiver outputs are routed to the data processing chip  554  through electrical connectors on or in the printed circuit board  558 . 
       FIG.  22    is a diagram of a top view of an example data processing system  560  that includes a housing  562  having side panels  564  and  566 , and a rear panel  568 . The system  560  includes a vertically mounted printed circuit board  570  that functions as the front panel. The surface of the printed circuit board  570  is substantially perpendicular to the bottom panel of the housing  562 . The term “substantially perpendicular” is meant to take into account of manufacturing and assembly tolerances, so that if a first surface is substantially perpendicular to a second surface, the first surface is at an angle in a range from 85° to 95° relative to the second surface. On the printed circuit board  570  are mounted a data processing chip  572  and an integrated communication device  574 . In some examples, the data processing chip  572  and the integrated communication device  574  are mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the printed circuit board  570 . The data processing chip  572  can be, e.g., a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, or an application specific integrated circuit (ASIC). A heat sink  576  is provided on the data processing chip  572 . 
     The integrated communication device  574  includes a photonic integrated circuit  586  and an electronic communication integrated circuit  588  mounted on a substrate  594 . The electronic communication integrated circuit  588  includes a first serializers/deserializers module  590  and a second serializers/deserializers module  592 . The printed circuit board  570  can be similar to the package substrate  230  ( FIGS.  2 ,  4 ,  11 - 14   ), the data processing chip  572  can be similar to the electronic processor integrated circuit or application specific integrated circuit  240 , and the integrated communication device  574  can be similar to the integrated communication device  210 ,  252 ,  374 ,  382 ,  402 ,  428 . In some embodiments, the integrated communication device  574  is soldered to the printed circuit board  570 . In some other embodiments, the integrated communication device  574  is removably connected to the printed circuit board  570 , e.g., via a land grid array or a compression interposer. Related holding fixtures including snap-on or screw-on mechanisms are not shown in the figure. 
     The integrated communication device  574  includes a first optical connector  578  that is configured to receive a second optical connector  580  that is coupled to a bundle of optical fibers  582 . The integrated communication device  574  is electrically coupled to the data processing chip  572  through electrical connectors  584  on or in the printed circuit board  570 . Because the data processing chip  572  and the integrated communication device  574  are both mounted on the printed circuit board  570 , the electrical connectors  584  can be made shorter, compared to the electrical connectors that electrically couple the transceivers  556  to the data processing chip  554  of  FIG.  21   . Using shorter electrical connectors  584  allows the signals to have a higher data rate with lower noise, lower distortion, and/or lower crosstalk. Mounting the printed circuit board  570  perpendicular to the bottom panel of the housing allows for more easily accessible connections to the integrated communication device  574  that may be removed and re-connected without, e.g., removing the housing from a rack. 
     The printed circuit board  570  can be secured to the side panels  564  and  566 , and the bottom and top panels of the housing using, e.g., brackets, screws, clips, and/or other types of fastening mechanisms. The surface of the printed circuit board  570  can be oriented perpendicular to bottom panel of the housing, or at an angle (e.g., between −60° to 60°) relative to the vertical direction (the vertical direction being perpendicular to the bottom panel). The printed circuit board  570  can have multiple layers, in which the outermost layer (i.e., the layer facing the user) has an exterior surface that is configured to be aesthetically pleasing. 
     The first optical connector  578 , the second optical connector  580 , and the bundle of optical fibers  582  can be similar to those shown in  FIGS.  2 ,  4 , and  11 - 16   . As described above, the bundle of fibers  582  can include 10 or more optical fibers, 100 or more optical fibers, 500 or more optical fibers, or 1000 or more optical fibers. The optical signals provided to the photonic integrated circuit  586  can have a high total bandwidth, e.g., about 1.6 Tbps, or about 12.8 Tbps, or more. 
     Although  FIG.  22    shows one integrated communication device  574 , there can be additional integrated communication devices  574  that are electrically coupled to the data processing chip  572 . The data processing system  560  can include a second printed circuit board (not shown in the figure) oriented parallel to the bottom panel of the housing  562 . The second printed circuit board can support other optical and/or electronic devices, such as storage devices, memory chips, controllers, power supply modules, fans, and other cooling devices. 
     In some examples of the data processing system  540  ( FIG.  21   ), the transceiver  556  can include circuitry (e.g., integrated circuits) that perform some type of processing of the signals and/or the data contained in the signals. The signals output from the transceiver  556  need to be routed to the data processing chip  554  through longer signal paths that place a limit on the data rate. In some data processing systems, the data processing chip  554  outputs processed data that are routed to one of the transceivers and transmitted to another system or device. Again, the signals output from the data processing chip  554  need to be routed to the transceiver  556  through longer signal paths that place a limit on the data rate. By comparison, in the data processing system  560  ( FIG.  22   ), the electrical signals that are transmitted between the integrated communication devices  574  and the data processing chip  572  pass through shorter signal paths and thus support a higher data rate. 
       FIG.  23    is a diagram of a top view of an example data processing system  600  that includes a housing  602  having side panels  604  and  606 , and a rear panel  608 . The system  600  includes a vertically mounted printed circuit board  610  that functions as the front panel. The surface of the printed circuit board  610  is substantially perpendicular to the bottom panel of the housing  602 . A data processing chip  572  is mounted on an interior side of the printed circuit board  610 , and an integrated communication device  612  is mounted on an exterior side of the printed circuit board  610 . In some examples, the data processing chip  572  is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the printed circuit board  610 . In some embodiments, the integrated communication device  612  is soldered to the printed circuit board  610 . In some other embodiments, the integrated communication device  612  is removably connected to the printed circuit board  610 , e.g., via a land grid array or a compression interposer. Related holding fixtures including snap-on or screw-on mechanisms are not shown in the figure. A heat sink  576  is provided on the data processing chip  572 . 
     The integrated communication device  612  includes a photonic integrated circuit  614  and an electronic communication integrated circuit  588  mounted on a substrate  618 . The electronic communication integrated circuit  588  includes a first serializers/deserializers module  590  and a second serializers/deserializers module  592 . The integrated communication device  612  includes a first optical connector  578  that is configured to receive a second optical connector  580  that is coupled to a bundle of optical fibers  582 . The integrated communication device  612  is electrically coupled to the data processing chip  572  through electrical connectors  616  that pass through the printed circuit board  610  in the thickness direction. Because the data processing chip  572  and the integrated communication device  612  are both mounted on the printed circuit board  610 , the electrical connectors  616  can be made shorter, thereby allowing the signals to have a higher data rate with lower noise, lower distortion, and/or lower crosstalk. Mounting the integrated communication device  612  on the outside of the printed circuit board  610  perpendicular to the bottom panel of the housing and accessible from outside the housing allows for more easily accessible connections to the integrated communication device  612  that may be removed and re-connected without, e.g., removing the housing from a rack. 
     In some examples, the data processing chip  572  is mounted on the rear side of the substrate, and the integrated communication device  612  are removably attached to the front side of the substrate, in which the substrate provides high speed connections between the data processing chip  572  and the integrated communication device  612 . For example, the substrate can be attached to a front side of a printed circuit board, in which the printed circuit board includes an opening that allows the data processing chip  572  to be mounted on the rear side of the substrate. The printed circuit board can provide from a motherboard electrical power to the substrate (and hence to the data processing chip  572  and the integrated communication device  612 , and allow the data processing chip  572  and the integrated communication device  612  to connect to the motherboard using low-speed electrical links. 
     The printed circuit board  610  can be secured to the side panels  604  and  606 , and the bottom and top panels of the housing using, e.g., brackets, screws, clips, and/or other types of fastening mechanisms. The surface of the printed circuit board  610  can be oriented perpendicular to bottom panel of the housing, or at an angle (e.g., between −60° to 60°) relative to the vertical direction (the vertical direction being perpendicular to the bottom panel). The printed circuit board  610  can have multiple layers, in which the portion of the outermost layer (i.e., the layer facing the user) not covered by the integrated communication device  612  has an exterior surface that is configured to be aesthetically pleasing. 
       FIGS.  24 - 27    below illustrate four general designs in which the data processing chips are positioned near the input/output communication interfaces.  FIG.  24    is a top view of an example data processing system  630  in which a data processing chip  640  is mounted near an optical/electrical communication interface  644  to enable high bandwidth data paths (e.g., one, ten, or more Gigabits per second per data path) between the data processing chip  640  and the optical/electrical communication interface  644 . In this example, the data processing chip  640  and the optical/electrical communication interface  644  are mounted on a circuit board  642  that functions as the front panel of an enclosure  632  of the system  630 , thus allowing optical fibers to be easily coupled to the optical/electrical communication interface  644 . In some examples, the data processing chip  640  is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the circuit board  642 . 
     The enclosure  632  has side panels  634  and  636 , a rear panel  638 , a top panel, and a bottom panel. In some examples, the circuit board  642  is perpendicular to the bottom panel. In some examples, the circuit board  642  is oriented at an angle in a range −60° to 60° relative to a vertical direction of the bottom panel. The side of the circuit board  642  facing the user is configured to be aesthetically pleasing. 
     The optical/electrical communication interface  644  is electrically coupled to the data processing chip  640  by electrical connectors  646  on or in the circuit board  642 . The circuit board  642  can be a printed circuit board that has one or more layers. The electrical connectors  646  can be signal lines printed on the one or more layers of the printed circuit board  642  and provide high bandwidth data paths (e.g., one or more Gigabits per second per data path) between the data processing chip  640  and the optical/electrical communication interface  644 . 
     In a first example, the data processing chip  640  receives electrical signals from the optical/electrical communication interface  644  and does not send electrical signals to the optical/electrical communication interface  644 . In a second example, the data processing chip  640  receives electrical signals from, and sends electrical signals to, the optical/electrical communication interface  644 . In the first example, the optical/electrical communication interface  644  receives optical signals from optical fibers, generates electrical signals based on the optical signals, and sends the electrical signals to the data processing chip  640 . In the second example, the optical/electrical communication interface  644  also receives electrical signals from the data processing chip, generates optical signals based on the electrical signals, and sends the optical signals to the optical fibers. 
     An optical connector  648  is provided to couple optical signals from the optical fibers to the optical/electrical communication interface  644 . In this example, the optical connector  648  passes through an opening in the circuit board  642 . In some examples, the optical connector  648  is securely fixed to the optical/electrical communication interface  644 . In some examples, the optical connector  648  is configured to be removably coupled to the optical/electrical communication interface  644 , e.g., by using a pluggable and releasable mechanism, which can include one or more snap-on or screw-on mechanisms. 
     The optical/electrical communication interface  644  can be similar to, e.g., the integrated communication device  210  ( FIG.  2   ),  252  ( FIG.  4   ),  374  ( FIG.  11   ),  382  ( FIG.  12   ),  402  ( FIG.  13   ), and  428  ( FIG.  14   ). In some examples, the optical/electrical communication interface  644  can be similar to the integrated optical communication device  448 ,  462 ,  466 ,  472  ( FIG.  17   ), except that the optical/electrical communication interface  644  is mounted on the same side of the circuit board  642  as the data processing chip  640 . The optical connector  648  can be similar to, e.g., the first optical connector part  213  ( FIGS.  2 ,  4   ), the first optical connector  356  ( FIGS.  11 ,  12   ), the first optical connector  404  ( FIGS.  13 ,  14   ), and the first optical connector part  456  ( FIG.  17   ). In some examples, a portion of the optical connector  648  can be part of the optical/electrical communication interface  644 . In some examples, the optical connector  648  can also include the second optical connector part  223  ( FIGS.  2 ,  4   ),  458  ( FIG.  17   ) that is optically coupled to the optical fibers.  FIG.  24    shows that the optical connector  648  passes through the circuit board  642 . In some examples, the optical connector  648  can be short so that the optical fibers pass through, or partly through, the circuit board  642 . In some examples, the optical connector is not attached vertically to a photonic integrated circuit that is part of the optical/electrical communication interface  644  but rather can be attached in-plane to the photonic integrated circuit using, e.g., V-groove fiber attachments, tapered or un-tapered fiber edge coupling, etc., followed by a mechanism to direct the light interfacing to the photonic integrated circuit to a direction that is substantially perpendicular to the photonic integrated circuit, such as one or more substantially 90-degree turning mirrors, one or more substantially 90-degree bent optical fibers, etc. Any such solution is conceptually included in the vertical optical coupling attachment schematically visualized in  FIGS.  24 - 27   . 
       FIG.  25    is a top view of an example data processing system  650  in which a data processing chip  670  is mounted near an optical/electrical communication interface  652  to enable high bandwidth data paths (e.g., one, ten, or more Gigabits per second per data path) between the data processing chip  670  and the optical/electrical communication interface  652 . In this example, the data processing chip  670  and the optical/electrical communication interface  652  are mounted on a circuit board  654  that is positioned near a front panel  656  of an enclosure  658  of the system  630 , thus allowing optical fibers to be easily coupled to the optical/electrical communication interface  652 . In some examples, the data processing chip  670  is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the circuit board  654 . 
     The enclosure  658  has side panels  660  and  662 , a rear panel  664 , a top panel, and a bottom panel. In some examples, the circuit board  654  and the front panel  656  are perpendicular to the bottom panel. In some examples, the circuit board  654  and the front panel  656  are oriented at an angle in a range −60° to 60° relative to a vertical direction of the bottom panel. In some examples, the circuit board  654  is substantially parallel to the front panel  656 , e.g., the angle between the surface of the circuit board  654  and the surface of the front panel  656  can be in a range of −5° to 5°. In some examples, the circuit board  654  is at an angle relative to the front panel  656 , in which the angle is in a range of −45° to 45°. 
     The optical/electrical communication interface  652  is electrically coupled to the data processing chip  670  by electrical connectors  666  on or in the circuit board  654 , similar to those of the system  630 . The signal path between the data processing chip  670  and the optical/electrical communication interface  652  can be unidirectional or bidirectional, similar to that of the system  630 . 
     An optical connector  668  is provided to couple optical signals from the optical fibers to the optical/electrical communication interface  652 . In this example, the optical connector  668  passes through an opening in the front panel  656  and an opening in the circuit board  654 . The optical connector  668  can be securely fixed, or releasably connected, to the optical/electrical communication interface  652 , similar to that of the system  630 . 
     The optical/electrical communication interface  652  can be similar to, e.g., the integrated communication device  210  ( FIG.  2   ),  252  ( FIG.  4   ),  374  ( FIG.  11   ),  382  ( FIG.  12   ),  402  ( FIG.  13   ), and  428  ( FIG.  14   ). In some examples, the optical/electrical communication interface  652  can be similar to the integrated optical communication device  448 ,  462 ,  466 ,  472  ( FIG.  17   ), except that the optical/electrical communication interface  652  is mounted on the same side of the circuit board  654  as the data processing chip  640 . The optical connector  668  can be similar to, e.g., the first optical connector part  213  ( FIGS.  2 ,  4   ), the first optical connector  356  ( FIGS.  11 ,  12   ), the first optical connector  404  ( FIGS.  13 ,  14   ), and the first optical connector part  456  ( FIG.  17   ). In some examples, the optical connector is not attached vertically to a photonic integrated circuit that is part of the optical/electrical communication interface  652  but rather can be attached in-plane to the photonic integrated circuit using, e.g., V-groove fiber attachments, tapered or un-tapered fiber edge coupling, etc., followed by a mechanism to direct the light interfacing to the photonic integrated circuit to a direction that is substantially perpendicular to the photonic integrated circuit, such as one or more substantially 90-degree turning mirrors, one or more substantially 90-degree bent optical fibers, etc. In some examples, a portion of the optical connector  668  can be part of the optical/electrical communication interface  652 . In some examples, the optical connector  668  can also include the second optical connector part  223  ( FIGS.  2 ,  4   ),  458  ( FIG.  17   ) that is optically coupled to the optical fibers.  FIG.  25    shows that the optical connector  668  passes through the front panel  656  and the circuit board  654 . In some examples, the optical connector  668  can be short so that the optical fibers pass through, or partly through, the front panel  656 . The optical fibers can also pass through, or partly through, the circuit board  654 . 
     In the examples of  FIGS.  24  and  25   , only one optical/electrical communication interface ( 544 ,  652 ) is shown in the figures. It is understood that the systems  630 ,  650  can include multiple optical/electrical communication interfaces that are mounted on the same circuit board as the data processing chip to enable high bandwidth data paths (e.g., one, ten, or more Gigabits per second per data path) between the data processing chip and each of the optical/electrical communication interfaces. 
       FIG.  26    is a top view of an example data processing system  680  in which a data processing chip  682  is mounted near optical/electrical communication interfaces  684   a ,  684   b ,  684   c  (collectively referenced as  684 ) to enable high bandwidth data paths (e.g., one, ten, or more Gigabits per second per data path) between the data processing chip  682  and each of the optical/electrical communication interfaces  684 . The data processing chip  682  is mounted on a first side of a circuit board  686  that functions as a front panel of an enclosure  688  of the system  680 . In some examples, the data processing chip  682  is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the circuit board  686 . The optical/electrical communication interfaces  684  are mounted on a second side of the circuit board  686 , in which the second side faces the exterior of the enclosure  688 . In this example, the optical/electrical communication interfaces  684  are mounted on an exterior side of the enclosure  688 , allowing optical fibers to be easily coupled to the optical/electrical communication interfaces  684 . 
     The enclosure  688  has side panels  690  and  692 , a rear panel  694 , a top panel, and a bottom panel. In some examples, the circuit board  686  is perpendicular to the bottom panel. In some examples, the circuit board  686  is oriented at an angle in a range −60° to 60° relative to a vertical direction of the bottom panel. 
     Each of the optical/electrical communication interfaces  684  is electrically coupled to the data processing chip  682  by electrical connectors  696  that pass through the circuit board  686  in the thickness direction. For example, the electrical connectors  696  can be configured as vias of the circuit board  686 . The signal paths between the data processing chip  682  and each of the optical/electrical communication interfaces  684  can be unidirectional or bidirectional, similar to those of the systems  630  and  650 . 
     For example, the system  680  can be configured such that signals are transmitted unidirectionally between the data processing chip  682  and one of the optical/electrical communication interfaces  684 , and bidirectionally between the data processing chip  682  and another one of the optical/electrical communication interfaces  684 . For example, the system  680  can be configured such that signals are transmitted unidirectionally from the optical/electrical communication interface  684   a  to the data processing chip  682 , and unidirectionally from the data processing chip to the optical/electrical communication interface  684   b  and/or optical/electrical communication interface  684   c.    
     Optical connectors  698   a ,  698   b ,  698   c  (collectively referenced as  698 ) are provided to couple optical signals from the optical fibers to the optical/electrical communication interfaces  684   a ,  684   b ,  684   c , respectively. The optical connectors  698  can be securely fixed, or releasably connected, to the optical/electrical communication interfaces  684 , similar to those of the systems  630  and  650 . 
     The optical/electrical communication interface  684  can be similar to, e.g., the integrated communication device  210  ( FIG.  2   ),  252  ( FIG.  4   ),  374  ( FIG.  11   ),  382  ( FIG.  12   ),  402  ( FIG.  13   ),  428  ( FIG.  14   ), and  512  ( FIG.  32   ), except that the optical/electrical communication interface  684  is mounted on the side of the circuit board  686  opposite to the side of the data processing chip  682 . In some examples, the optical/electrical communication interface  684  can be similar to the integrated optical communication device  448 ,  462 ,  466 ,  472  ( FIG.  17   ). The optical connector  698  can be similar to, e.g., the first optical connector part  213  ( FIGS.  2 ,  4   ), the first optical connector  356  ( FIGS.  11 ,  12   ), the first optical connector  404  ( FIGS.  13 ,  14   ), the first optical connector part  456  ( FIG.  17   ), and the first optical connector part  520  ( FIG.  32   ). In some examples, the optical connector is not attached vertically to a photonic integrated circuit that is part of the optical/electrical communication interface  684  but rather can be attached in-plane to the photonic integrated circuit using, e.g., V-groove fiber attachments, tapered or un-tapered fiber edge coupling, etc., followed by a mechanism to direct the light interfacing to the photonic integrated circuit to a direction that is substantially perpendicular to the photonic integrated circuit, such as one or more substantially 90-degree turning mirrors, one or more substantially 90-degree bent optical fibers, etc. In some examples, a portion of the optical connector  668  can be part of the optical/electrical communication interface  652 . In some examples, the optical connector  668  can also include the second optical connector part  223  ( FIGS.  2 ,  4   ),  458  ( FIG.  17   ) that is optically coupled to the optical fibers. 
     In some examples, the optical/electrical communication interfaces  684  are securely fixed (e.g., by soldering) to the circuit board  686 . In some examples, the optical/electrical communication interfaces  684  are removably connected to the circuit board  686 , e.g., by use of mechanical mechanisms such as one or more snap-on or screw-on mechanisms. An advantage of the system  680  is that in case of a malfunction at one of the optical/electrical communication interfaces  684 , the faulty optical/electrical communication interface  684  can be replaced without opening the enclosure  688 . 
       FIG.  27    is a top view of an example data processing system  700  in which a data processing chip  702  is mounted near optical/electrical communication interfaces  704   a ,  704   b ,  704   c  (collectively referenced as  704 ) to enable high bandwidth data paths (e.g., one, ten, or more Gigabits per second per data path) between the data processing chip  702  and each of the optical/electrical communication interfaces  704 . The data processing chip  702  is mounted on a first side of a circuit board  706  that is positioned near a front panel of an enclosure  710  of the system  700 , similar to the configuration of the system  650  ( FIG.  25   ). In some examples, the data processing chip  702  is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the circuit board  706 . The optical/electrical communication interfaces  704  are mounted on a second side of the circuit board  708 . In this example, the optical/electrical communication interfaces  704  pass through openings in the front panel  708 , allowing optical fibers to be easily coupled to the optical/electrical communication interfaces  704 . 
     The enclosure  710  has side panels  712  and  714 , a rear panel  716 , a top panel, and a bottom panel. In some examples, the circuit board  706  and the front panel  708  are oriented at an angle in a range −60° to 60° relative to a vertical direction of the bottom panel. In some examples, the circuit board  706  is substantially parallel to the front panel  708 , e.g., the angle between the surface of the circuit board  706  and the surface of the front panel  708  can be in a range of −5° to 5°. In some examples, the circuit board  706  is at an angle relative to the front panel  708 , in which the angle is in a range of −45° to 45°. 
     Each of the optical/electrical communication interfaces  704  is electrically coupled to the data processing chip  702  by electrical connectors  718  that pass through the circuit board  706  in the thickness direction, similar to those of the system  680  ( FIG.  26   ). The signal paths between the data processing chip  702  and each of the optical/electrical communication interfaces  704  can be unidirectional or bidirectional, similar to those of the system  630  ( FIG.  24   ),  650  ( FIG.  25   ), and  680  ( FIG.  26   ). 
     Optical connectors  716   a ,  716   b ,  716   c  (collectively referenced as  716 ) are provided to couple optical signals from the optical fibers to the optical/electrical communication interfaces  704   a ,  704   b ,  704   c , respectively. The optical connectors  716  can be securely fixed, or releasably connected, to the optical/electrical communication interfaces  704 , similar to those of the systems  630 ,  650 , and  680 . 
     The optical/electrical communication interface  704  can be similar to, e.g., the integrated communication device  210  ( FIG.  2   ),  252  ( FIG.  4   ),  374  ( FIG.  11   ),  382  ( FIG.  12   ),  402  ( FIG.  13   ),  428  ( FIG.  14   ), and  512  ( FIG.  32   ), except that the optical/electrical communication interface  704  is mounted on the side of the circuit board  706  opposite to the side of the data processing chip  702 . In some examples, the optical/electrical communication interface  704  can be similar to the integrated optical communication device  448 ,  462 ,  466 ,  472  ( FIG.  17   ). The optical connector  716  can be similar to, e.g., the first optical connector part  213  ( FIGS.  2 ,  4   ), the first optical connector  356  ( FIGS.  11 ,  12   ), the first optical connector  404  ( FIGS.  13 ,  14   ), the first optical connector part  456  ( FIG.  17   ), and the first optical connector part  520  ( FIG.  32   ). In some examples, the optical connector is not attached vertically to a photonic integrated circuit that is part of the optical/electrical communication interface  704  but rather can be attached in-plane to the photonic integrated circuit using, e.g., V-groove fiber attachments, tapered or un-tapered fiber edge coupling, etc., followed by a mechanism to direct the light interfacing to the photonic integrated circuit to a direction that is substantially perpendicular to the photonic integrated circuit, such as one or more substantially 90-degree turning mirrors, one or more substantially 90-degree bent optical fibers, etc. In some examples, a portion of the optical connector  716  can be part of the optical/electrical communication interface  704 . In some examples, the optical connector  716  can also include the second optical connector part  223  ( FIGS.  2 ,  4   ),  458  ( FIG.  17   ) that is optically coupled to the optical fibers. 
     In some examples, the optical/electrical communication interfaces  704  are securely fixed (e.g., by soldering) to the circuit board  706 . In some examples, the optical/electrical communication interfaces  704  are removably connected to the circuit board  706 , e.g., by use of mechanical mechanisms such as one or more snap-on or screw-on mechanisms. An advantage of the system  700  is that in case of a malfunction at one of the optical/electrical communication interfaces  704 , the faulty optical/electrical communication interface  704  can unplugged or decoupled from the circuit board  706  and replaced without opening the enclosure  710 . 
       FIG.  28    is a top view of an example data processing system  720  in which a data processing chip  722  is mounted near an optical/electrical communication interface  724  to enable high bandwidth data paths (e.g., one, ten, or more Gigabits per second per data path) between the data processing chip  720  and the optical/electrical communication interface  724 . The data processing chip  722  is mounted on a first side of a circuit board  730  that functions as a front panel of an enclosure  732  of the system  720 . In some examples, the data processing chip  722  is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the circuit board  730 . The optical/electrical communication interface  724  is mounted on a second side of the circuit board  730 , in which the second side faces the exterior of the enclosure  732 . In this example, the optical/electrical communication interface  724  is mounted on an exterior side of the enclosure  732 , allowing optical fibers  734  to be easily coupled to the optical/electrical communication interface  724 . 
     The enclosure  688  has side panels  736  and  738 , a rear panel  740 , a top panel, and a bottom panel. In some examples, the circuit board  730  is perpendicular to the bottom panel. In some examples, the circuit board  730  is oriented at an angle in a range −60° to 60° relative to a vertical direction of the bottom panel. 
     The optical/electrical communication interface  724  includes a photonic integrated circuit  726  mounted on a substrate  728  that is electrically coupled to the circuit board  730 . The optical/electrical communication interface  724  is electrically coupled to the data processing chip  722  by electrical connectors  742  that pass through the circuit board  730  in the thickness direction. For example, the electrical connectors  742  can be configured as vias of the circuit board  730 . The signal paths between the data processing chip  722  and the optical/electrical communication interface  724  can be unidirectional or bidirectional, similar to those of the systems  630 ,  650 ,  680 , and  700 . 
     An optical connector  744  is provided to couple optical signals from the optical fibers  734  to the optical/electrical communication interface  724 . The optical connector  744  can be securely fixed, or removably connected, to the optical/electrical communication interface  744 , similar to those of the systems  630 ,  650 ,  680 , and  700 . 
     In some implementations, the optical/electrical communication interface  724  can be similar to, e.g., the integrated communication device  448 ,  462 ,  466 , and  472  of  FIG.  17   . The optical signals from the optical fibers are processed by the photonic integrated circuit  726 , which generates serial electrical signals based on the optical signals. For example, the serial electrical signals are amplified by a set of transimpedance amplifiers and drivers (which can be part of the photonic integrated circuit  726  or a serializers/deserializers module in the data processing chip  722 ), which drives the output signals that are transmitted to the serializers/deserializers module embedded in the data processing chip  722 . 
     The optical connector  744  includes a first optical connector  746  and a second optical connector  748 , in which the second optical connector  748  is optically coupled to the optical fibers  734 . The first optical connector  746  can be similar to, e.g., the first optical connector part  213  ( FIGS.  2 ,  4   ), the first optical connector  356  ( FIGS.  11 ,  12   ), the first optical connector  404  ( FIGS.  13 ,  14   ), the first optical connector part  456  ( FIG.  17   ), and the first optical connector part  520  ( FIG.  32   ). The second optical connector  748  can be similar to the second optical connector part  223  ( FIGS.  2 ,  4   ) and  458  ( FIG.  17   ). In some examples, the optical connector is not attached vertically to the photonic integrated circuit  726  but rather can be attached in-plane to the photonic integrated circuit using, e.g., V-groove fiber attachments, tapered or un-tapered fiber edge coupling, etc., followed by a mechanism to direct the light interfacing to the photonic integrated circuit to a direction that is substantially perpendicular to the photonic integrated circuit, such as one or more substantially 90-degree turning mirrors, one or more substantially 90-degree bent optical fibers, etc. 
     In some examples, the optical/electrical communication interface  724  is securely fixed (e.g., by soldering) to the circuit board  730 . In some examples, the optical/electrical communication interface  724  is removably connected to the circuit board  730 , e.g., by use of mechanical mechanisms such as one or more snap-on or screw-on mechanisms. An advantage of the system  720  is that in case of a malfunction of the optical/electrical communication interface  724 , the faulty optical/electrical communication interface  724  can be replaced without opening the enclosure  732 . 
     In each of the examples in  FIGS.  24 ,  25 ,  26 ,  27 , and  28   , the optical/electrical communication interface  644 ,  652 ,  684 ,  704 , and  724  can be electrically coupled to the circuit board  642 ,  654 ,  686 ,  706 , and  730 , respectively, using electrical contacts that include one or more of spring-loaded elements, compression interposers, and/or land-grid arrays. 
       FIG.  29    is a diagram of an example data processing system  750  that includes a vertically mounted circuit board  752  that enables high bandwidth data paths (e.g., one, ten, or more Gigabits per second per data path) between data processing chips  758  and optical/electrical communication interfaces  760 . The data processing chips  758  and the optical/electrical communication interfaces  760  are mounted on the circuit board  752 , in which each data processing chip  758  is electrically coupled to a corresponding optical/electrical communication interface  760 . The data processing chips  758  are electrically coupled to one another by electrical connectors (e.g., electrical signal lines on one or more layers of the circuit board  752 ). 
     The data processing chips  758  can be similar to, e.g., the electronic processor integrated circuit, data processing chip, or host application specific integrated circuit  240  ( FIGS.  2 ,  4 ,  6 ,  7 ,  11 ,  12   ), digital application specific integrated circuit  444  ( FIG.  17   ), data processor  502  ( FIG.  20   ), data processing chip  572  ( FIGS.  22 ,  23   ),  640  ( FIG.  24   ),  670  ( FIG.  25   ),  682  ( FIG.  26   ),  702  ( FIG.  27   ), and  722  ( FIG.  28   ). Each of the data processing chips  758  can be, e.g., a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, or an application specific integrated circuit (ASIC). 
     Although the figure shows that the optical/electrical communication interfaces  760  are mounted on the side of the circuit board  752  facing the front panel  754 , the optical/electrical communication interfaces  760  can also be mounted on the side of the circuit board  752  facing the interior of the enclosure  756 . The optical/electrical communication interfaces  760  can be similar to, e.g., the integrated communication devices  210  ( FIGS.  2 ,  3 ,  10   ),  252  ( FIGS.  4 ,  5   ),  262  ( FIG.  6   ), the integrated optical communication devices  282  ( FIGS.  7 - 9   ),  374  ( FIG.  11   ),  382  ( FIG.  12   ),  390  ( FIG.  13   ),  428  ( FIG.  14   ),  402  ( FIGS.  15 ,  16   ),  448 ,  462 ,  466 ,  472  ( FIG.  17   ), the integrated communication devices  574  ( FIG.  22   ),  612  ( FIG.  23   ), and the optical/electrical communication interfaces  644  ( FIG.  24   ),  652  ( FIG.  25   ),  684  ( FIG.  26   ),  704  ( FIG.  27   ). 
     The circuit board  752  is positioned near a front panel  754  of an enclosure  756 , and optical signals are coupled to the optical/electrical communication interfaces  760  through optical paths that pass through openings in the front panel  754 . This allows users to conveniently removably connect optical fiber cables  762  to the input/output interfaces  760 . The position and orientation of the circuit board  752  relative to the enclosure  756  can be similar to, e.g., those of the circuit board  654  ( FIG.  25   ) and  706  ( FIG.  27   ). 
     In some implementations, the data processing system  750  can include multiple types of optical/electrical communication interfaces  760 . For example, some of the optical/electrical communication interfaces  760  can be mounted on the same side of the circuit board  752  as the corresponding data processing chip  758 , and some of the optical/electrical communication interfaces  760  can be mounted on the opposite side of the circuit board  752  as the corresponding data processing chip  758 . Some of the optical/electrical communication interfaces  760  can include first and second serializers/deserializers modules, and the corresponding data processing chips  758  can include third serializers/deserializers modules, similar to the examples in  FIGS.  2 - 8 ,  11 - 14 ,  20 ,  22 , and  23   . Some of the optical/electrical communication interfaces  760  can include no serializers/deserializers module, and the corresponding data processing chips  758  can include serializers/deserializers modules, similar to the example of  FIG.  17   . Some of the optical/electrical communication interfaces  760  can include sets of transimpedance amplifiers and drivers, either embedded in the photonic integrated circuits or in separate chips external to the photonic integrated circuits. Some of the optical/electrical communication interfaces  760  do not include transimpedance amplifiers and drivers, in which sets of transimpedance amplifiers and drivers are included in the corresponding data processing chips  758 . 
     In the example shown in  FIG.  29   , the circuit board  752  is placed near the front panel  754 . In some examples, the circuit board  752  can also function as the front panel, similar to the examples in  FIGS.  22 - 24 ,  26 , and  28   . 
       FIG.  30    is a diagram of an example high bandwidth data processing system  800  that can be similar to, e.g., systems  200  ( FIGS.  2 ,  20   ),  250  ( FIG.  4   ),  260  ( FIG.  6   ),  280  ( FIG.  7   ),  350  ( FIG.  11   ),  380  ( FIG.  12   ),  390  ( FIG.  13   ),  420  ( FIG.  14   ),  560  ( FIG.  22   ),  600  ( FIG.  23   ),  630  ( FIG.  24   ), and  650  ( FIG.  25   ) described above. A first optical signal  770  is transmitted from an optical fiber to a photonic integrated circuit  772 , which generates a first serial electrical signal  774  based on the first optical signal. The first serial electrical signal  774  is provided to a first serializers/deserializers module  776 , which converts the first serial electrical signal  774  to a third set of parallel signals  778 . The first serializers/deserializers module  776  conditions the serial electrical signal upon conversion into the parallel electrical signals, in which the signal conditioning can include, e.g., one or more of clock and data recovery, and signal equalization. The third set of parallel signals  778  is provided to a second serializers/deserializers module  780 , which generates a fifth serial electrical signal  782  based on the third set of parallel signals  778 . The fifth serial electrical signal  782  is provided to a third serializers/deserializers module  784 , which generates a seventh set of parallel signals  786  that is provided to a data processor  788 . 
     In some implementations, the photonic integrated circuit  772 , the first serializers/deserializers module  776 , and the second serializers/deserializers module  780  can be mounted on a substrate of an integrated communication device, an optical/electrical communication interface, or an input/output interface module. The first serializers/deserializers module  776  and the second serializers/deserializers module  780  can be implemented in a single chip. In some implementations, the third serializers/deserializers module  784  can be embedded in the data processor  788 , or the third serializers/deserializers module  784  can be separate from the data processor  788 . 
     The data processor  788  generates an eighth set of parallel signals  790  that is sent to the third serializers/deserializers module  784 , which generates a sixth serial electrical signal  792  based on the eighth set of parallel signals  790 . The sixth serial electrical signal  792  is provided to the second serializers/deserializers module  780 , which generates a fourth set of parallel signals  794  based on the sixth serial electrical signal  792 . The second serializers/deserializers module  780  can condition the serial electrical signal  792  upon conversion into the fourth set of parallel electrical signals  794 . The fourth set of parallel signals  794  is provided to the first serializers/deserializers module  780 , which generates a second serial electrical signal  796  based on the fourth set of parallel signals  794  that is sent to the photonic integrated circuit  772 . The photonic integrated circuit  772  generates a second optical signal  798  based on the second serial electrical signal  796 , and sends the second optical signal  798  to an optical fiber. The first and second optical signals  770 ,  798  can travel on the same optical fiber or on different optical fibers. 
     A feature of the system  800  is that the electrical signal paths traveled by the first, fifth, sixth, and second serial electrical signals  774 ,  782 ,  792 ,  796  are short (e.g., less than 5 inches), to allow the first, fifth, sixth, and second serial electrical signals  782 ,  792  to have a high data rate (e.g., up to 50 Gbps). 
       FIG.  31    is a diagram of an example high bandwidth data processing system  810  that can be similar to, e.g., systems  680  ( FIG.  26   ),  700  ( FIG.  27   ), and  750  ( FIG.  29   ) described above. The system  810  includes a data processor  812  that receives and sends signals from and to multiple photonic integrated circuits. The system  810  includes a second photonic integrated circuit  814 , a fourth serializers/deserializers module  816 , a fifth serializers/deserializers module  818 , and a sixth serializers/deserializers module  820 . The operations of the second photonic integrated circuit  814 , a fourth serializers/deserializers module  816 , a fifth serializers/deserializers module  818 , and a sixth serializers/deserializers module  820  can be similar to those of the first photonic integrated circuit  772 , the first serializers/deserializers module  776 , the second serializers/deserializers module  780 , and the third serializers/deserializers module  784 . The third serializers/deserializers module  784  and the sixth serializers/deserializers module  820  can be embedded in the data processor  812 , or be implemented in separate chips. 
     In some examples, the data processor  812  processes first data carried in the first optical signal received at the first photonic integrated circuit  772 , and generates second data that is carried in the fourth optical signal output from the second photonic integrated circuit  814 . 
     The examples in  FIGS.  30  and  31    include three serializers/deserializers modules between the photonic integrated circuit and the data processor, it is understood that the same principles can be applied to systems that has only one serializers/deserializers module between the photonic integrated circuit and the data processor. 
     In some implementations, signals are transmitted unidirectionally from the photonic integrated circuit  772  to the data processor  788  ( FIG.  30   ). In that case, the first serializers/deserializers module  776  can be replaced with a serial-to-parallel converter, the second serializers/deserializers module  780  can be replaced with a parallel-to-serial converter, and the third serializers/deserializers module  784  can be replaced with a serial-to-parallel converter. In some implementations, signals are transmitted unidirectionally from the data processor  812  ( FIG.  31   ) to the second photonic integrated circuit  814 . In that case, the sixth serializers/deserializers module  820  can be replaced with a parallel-to-serial converter, the fifth serializers/deserializers module  818  can be replaced with a serial-to-parallel converter, and the fourth serializers/deserializers module  816  can be replaced with a parallel-to-serial converter. 
     It should be appreciated by those of ordinary skill in the art that the various embodiments described herein in the context of coupling light from one or more optical fibers, e.g.,  226  ( FIGS.  2  and  4   ) or  272  ( FIGS.  6  and  7   ) to the photonic integrated circuit, e.g.,  214  ( FIGS.  2  and  4   ),  264  ( FIG.  6   ), or  296  ( FIG.  7   ) will be equally operable to couple light from the photonic integrated circuit to one or more optical fibers. This reversibility of the coupling direction is a general feature of at least some embodiments described herein, including some of those using polarization diversity. 
     The example optical systems disclosed herein should only be viewed as some of many possible embodiments that can be used to perform polarization demultiplexing and independent array pattern scaling, array geometry re-arrangement, spot size scaling, and angle-of-incidence adaptation using diffractive, refractive, reflective, and polarization-dependent optical elements, 3D waveguides and 3D printed optical components. Other implementations achieving the same set of functionalities are also covered by the spirit of this disclosure. 
     For example, the optical fibers can be coupled to the edges of the photonic integrated circuits, e.g., using fiber edge couplers. The signal conditioning (e.g., clock and data recovery, signal equalization, or coding) can be performed on the serial signals, the parallel signals, or both. The signal conditioning can also be performed during the transition from serial to parallel signals. 
     In some implementations, the data processing systems described above can be used in, e.g., data center switching systems, supercomputers, internet protocol (IP) routers, Ethernet switching systems, graphics processing work stations, and systems that apply artificial intelligence algorithms. 
     In the examples described above in which the figures show a first serializers/deserializers module (e.g.,  216 ) placed adjacent to a second serializers/deserializers module (e.g.,  217 ), it is understood that a bus processing unit  218  can be positioned between the first and second serializers/deserializers modules and perform, e.g., switching, re-routing, and/or coding functions described above. 
     In some implementations, the data processing systems described above includes multiple data generators that generate large amounts of data that are sent through optical fibers to the data processors for processing. For example, an autonomous driving vehicle (e.g., car, truck, train, boat, ship, submarine, helicopter, drone, airplane, space rover, or space ship) or a robot (e.g., an industrial robot, a helper robot, a medical surgery robot, a merchandise delivery robot, a teaching robot, a cleaning robot, a cooking robot, a construction robot, an entertainment robot) can include multiple high resolution cameras and other sensors (e.g., LIDARs (Light Detection and Ranging), radars) that generate video and other data that have a high data rate. The cameras and/or sensors can send the video data and/or sensor data to one or more data processing modules through optical fibers. The one or more data processing modules can apply artificial intelligence technology (e.g., using one or more neural networks) to recognize individual objects, collections of objects, scenes, individual sounds, collections of sounds, and/or situations in the environment of the vehicle and quickly determine appropriate actions for controlling the vehicle or robot. 
       FIG.  34    is a flow diagram of an example process for processing high bandwidth data. A process  830  includes receiving  832  a plurality of channels of first optical signals from a plurality of optical fibers. The process  830  includes generating  834  a plurality of first serial electrical signals based on the received optical signals, in which each first serial electrical signal is generated based on one of the channels of first optical signals. The process  830  includes generating  836  a plurality of sets of first parallel electrical signals based on the plurality of first serial electrical signals, and conditioning the electrical signals, in which each set of first parallel electrical signals is generated based on a corresponding first serial electrical signal. The process  830  includes generating  838  a plurality of second serial electrical signals based on the plurality of sets of first parallel electrical signals, in which each second serial electrical signal is generated based on a corresponding set of first parallel electrical signals. 
     In some implementations, a data center includes multiple systems, in which each system incorporates the techniques disclosed in  FIGS.  22  to  29    and the corresponding description. Each system includes a vertically mounted printed circuit board, e.g.,  570  ( FIG.  22   ),  610  ( FIG.  23   ),  642  ( FIG.  24   ),  654  ( FIG.  25   ),  686  ( FIG.  26   ),  706  ( FIG.  27   ),  730  ( FIG.  28   ),  752  ( FIG.  29   ) that functions as the front panel of the housing or is substantially parallel to the front panel. At least one data processing chip and at least one integrated communication device or optical/electrical communication interface are mounted on the printed circuit board. The integrated communication device or optical/electrical communication interface can incorporate techniques disclosed in  FIGS.  2 - 22  and  30 - 34    and the corresponding description. Each integrated communication device or optical/electrical communication interface includes a photonic integrated circuit that receives optical signals and generates electrical signals based on the optical signals. The optical signals are provided to the photonic integrated circuit through one or more optical paths (or spatial paths) that are provided by, e.g., cores of the fiber-optic cables, which can incorporate techniques described in U.S. patent application Ser. No. 16/822,103. A large number of parallel optical paths (or spatial paths) can be arranged in two-dimensional arrays using connector structures, which can incorporate techniques described in U.S. patent application Ser. No. 16/816,171. 
       FIG.  35 A  shows an optical communications system  1250  providing high-speed communications between a first chip  1252  and a second chip  1254  using co-packaged optical interconnect modules  1258  similar to those shown in, e.g.,  FIGS.  2 - 5  and  17   . Each of the first and second chips  1252 ,  1254  can be a high-capacity chip, e.g., a high bandwidth Ethernet switch chip. The first and second chips  1252 ,  1254  communicate with each other through an optical fiber interconnection cable  1734  that includes a plurality of optical fibers. In some implementations, the optical fiber interconnection cable  1734  can include optical fiber cores that transmit data and control signals between the first and second chips  802 ,  804 . The optical fiber interconnection cable  1734  also includes one or more optical fiber cores that transmit optical power supply light from an optical power supply or photon supply to photonic integrated circuits that provide optoelectronic interfaces for the first and second chips  1252 ,  1254 . The optical fiber interconnection cable  1734  can include single-core fibers or multi-core fibers. Each single-core fiber includes a cladding and a core, typically made from glasses of different refractive indices such that the refractive index of the cladding is lower than the refractive index of the core to establish a dielectric optical waveguide. Each multi-core optical fiber includes a cladding and multiple cores, typically made from glasses of different refractive indices such that the refractive index of the cladding is lower than the refractive index of the core. More complex refractive index profiles, such as index trenches, multi-index profiles, or gradually changing refractive index profiles can also be used. More complex geometric structures such as non-circular cores or claddings, photonic crystal structures, photonic bandgap structures, or nested antiresonant nodeless hollow core structures can also be used. 
     The example of  FIG.  35 A  illustrates a switch-to-switch use case. An external optical power supply or photon supply  1256  provides optical power supply signals, which can be, e.g., continuous-wave light, one or more trains of periodic optical pulses, or one or more trains of non-periodic optical pulses. The power supply light is provided from the photon supply  1256  to the co-packaged optical interconnect modules  1258  through optical fibers  1730  and  1732 , respectively. For example, the optical power supply  1256  can provide continuous wave light, or both pulsed light for data modulation and synchronization, as described in U.S. patent application Ser. No. 16/847,705. This allows the first chip  1252  to be synchronized with the second chip  1254 . 
     For example, the photon supply  1256  can correspond to the optical power supply  103  of  FIG.  1   . The pulsed light from the photon supply  1256  can be provided to the link  102 _ 6  of the data processing system  200  of  FIG.  20   . In some implementations, the photon supply  1256  can provide a sequence of optical frame templates, in which each of the optical frame templates includes a respective frame header and a respective frame body, and the frame body includes a respective optical pulse train. The modulators  417  can load data into the respective frame bodies to convert the sequence of optical frame templates into a corresponding sequence of loaded optical frames that are output through optical fiber link  102 _ 1 . 
     The implementation shown in  FIG.  35 A  uses a packaging solution corresponding to  FIG.  35 B , whereby in contrast to  FIG.  17    substrates  454  and  460  are not used and the photonic integrated circuit  464  is directly attached to the serializers/deserializers module  446 .  FIG.  35 C  shows an implementation similar to  FIG.  5   , in which the photonic integrated circuit  464  is directly attached to the serializers/deserializers  216 . 
       FIG.  36    shows an example of an optical communications system  1260  providing high-speed communications between a high-capacity chip  1262  (e.g., an Ethernet switch chip) and multiple lower-capacity chips  1264   a ,  1264   b ,  1264   c , e.g., multiple network interface cards (NICs) attached to computer servers) using co-packaged optical interconnect modules  1258  similar to those shown in  FIG.  35 A . The high-capacity chip  1262  communicates with the lower-capacity chips  1264   a ,  1264   b ,  1264   c  through a high-capacity optical fiber interconnection cable  1740  that later branches out into several lower-capacity optical fiber interconnection cables  1742   a ,  1742   b ,  1742   c  that are connected to the lower-capacity chips  1264   a ,  1264   b ,  1264   c , respectively. This example illustrates a switch-to-servers use case. 
     An external optical power supply or photon supply  1266  provides optical power supply signals, which can be continuous-wave light, one or more trains of periodic optical pulses, or one or more trains of non-periodic optical pulses. The power supply light is provided from the photon supply  1266  to the optical interconnect modules  1258  through optical fibers  1744 ,  1746   a ,  1746   b ,  1746   c , respectively. For example, the optical power supply  1266  can provide both pulsed light for data modulation and synchronization, as described in U.S. patent application Ser. No. 16/847,705. This allows the high-capacity chip  1262  to be synchronized with the lower-capacity chips  1264   a ,  1264   b , and  1264   c.    
       FIG.  37    shows an optical communications system  1270  providing high-speed communications between a high-capacity chip  1262  (e.g., an Ethernet switch chip) and multiple lower-capacity chips ( 1264   a ,  1264   b , e.g., multiple network interface cards (NICs) attached to computer servers) using a mix of co-packaged optical interconnect modules  1258  similar to those shown in  FIG.  35    as well as conventional pluggable optical interconnect modules  1272 . 
     An external optical power supply or photon supply  1274  provides optical power supply signals, which can be continuous-wave light, one or more trains of periodic optical pulses, or one or more trains of non-periodic optical pulses. For example, the optical power supply  1274  can provide both pulsed light for data modulation and synchronization, as described in U.S. patent application Ser. No. 16/847,705. This allows the high-capacity chip  1262  to be synchronized with the lower-capacity chips  1264   a  and  1264   b.    
     Some aspects of the systems  1250 ,  1260 , and  1270  are described in more detail in connection with  FIGS.  79  to  84 B . 
       FIG.  43    shows an exploded view of an example of a front-mounted module  860  of a data processing system that includes a vertically mounted printed circuit board  862 , a host application specific integrated circuit  864  mounted on the back-side of the circuit board  862 , and a heat sink  866 . In some examples, the host application specific integrated circuit  864  is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the circuit board  862 . The front module  860  can be, e.g., the front panel of the housing of the data processing system, similar to the configuration shown in  FIG.  26   , or positioned near the front panel of the housing, similar to the configuration shown in  FIG.  27   . Three optical module with connectors, e.g.,  868   a ,  868   b ,  868   c , collectively referenced as  868 , are shown in the figure. Additional optical module with connectors can be used. The data processing system can be similar to, e.g., the data processing system  680  ( FIG.  26   ) or  700  ( FIG.  27   ). The printed circuit board  862  can be similar to, e.g., the printed circuit board  686  ( FIG.  26   ) or  706  ( FIG.  27   ). The application specific integrated circuit  864  can be similar to, e.g., the application specific integrated circuit  682  ( FIG.  26   ) or  702  ( FIG.  27   ). The heat sink  866  can be similar to, e.g., the heat sink  576  ( FIG.  23   ). The optical module with connector  868  includes an optical module  880  (see  FIGS.  44 ,  45   ) and a mechanical connector structure  900  (see  FIGS.  46 ,  47   ). The optical module  880  can be similar to, e.g., the optical modules  648  ( FIG.  26   ) or  704  ( FIG.  27   ). 
     The optical module with connector  868  can be inserted into a first grid structure  870 , which can function as both (i) a heat spreader/heat sink and (ii) a mechanical holding fixture for the optical module with connectors  868 . The first grid structure  870  includes an array of receptors, each receptor can receive an optical module with connector  868 . When assembled, the first grid structure  870  is connected to the printed circuit board  862 . The first grid structure  870  can be firmly held in place relative to the printed circuit board  862  by sandwiching the printed circuit board  862  in between the first grid structure  870  and a second structure  872  (e.g., a second grid structure) located on the opposite side of the printed circuit board  862  and connected to the first grid structure  870  through the printed circuit board  862 , e.g., by use of screws. Thermal vias between the first grid structure  870  and the second structure  872  can conduct heat from the front-side of the printed circuit board  862  to the heat sink  866  on the back-side of the printed circuit board  862 . Additional heat sinks can also be mounted directly onto the first grid structure  870  to provide cooling in the front. 
     The printed circuit board  862  includes electrical contacts  876  configured to electrically connect to the removable optical module with connectors  868  after the removable optical module with connectors  868  are inserted into the first grid structure  870 . The first grid structure  870  can include an opening  874  at the location in which the host application specific integrated circuit  864  is mounted on the other side of the printed circuit board  862  to allow for components such as decoupling capacitors to be mounted on the printed circuit board  862  in immediate lateral vicinity to the host application specific integrated circuit  864 . 
       FIGS.  44  and  45    show an exploded view and an assembled view, respectively, of the optical module  880 , which can be similar to the integrated optical communication device  512  of  FIG.  32   . The optical module  880  includes an optical connector part  882  (which can be similar to the first optical connector  520  of  FIG.  32   ) that can either directly or through an (e.g., geometrically wider) upper connector part  884  receive light from fibers embedded in a second optical connector part (not shown in  FIGS.  44 ,  45   ), which can be similar to, e.g., the optical connector part  268  of  FIGS.  6  and  7   ). In the example shown in  FIGS.  44 ,  45   , a matrix of fibers, e.g., 2×18 fibers, can be optically coupled to the optical connector part  882 . For example, the optical connector part  882  can have a configuration similar to the fiber coupling region  430  of  FIG.  15    that is configured to couple 2×18 fibers. The upper connector part  884  can also include alignment structures  886  (e.g., holes, grooves, posts) to receive corresponding mating structures of the second optical connector part. 
     The optical connector part  882  is inserted through an opening  888  of a substrate  890  and optically coupled to a photonic integrated circuit  896  mounted on the underside of the substrate  890 . The substrate  890  can be similar to the substrate  514  of  FIG.  32   , and the photonic integrated circuit  896  can be similar to the photonic integrated circuit  524 . A first serializers/deserializers chip  892  and a second serializers/deserializers chip  894  are mounted on the substrate  890 , in which the chip  892  is positioned on one side of the optical connector part  882 , and the chip  894  is positioned on the other side of the optical connector part  882 . The first serializers/deserializers chip  892  can include circuitry similar to, e.g., the third serializers/deserializers module  398  and the fourth serializers/deserializers module  400  of  FIG.  32   . The second serializers/deserializers chip  894  can include circuitry similar to, e.g., the first serializers/deserializers module  394  and the second serializers/deserializers module  396 . A second slab  898  (which can be similar to the second slab  518  of  FIG.  32   ) can be provided on the underside of the substrate  890  to provide a removable connection to a package substrate (e.g.,  230 ). 
       FIGS.  46  and  47    show an exploded view and an assembled view, respectively, of a mechanical connector structure  900  built around the functional optical module  880  of  FIGS.  44 ,  45   . In this example embodiment, the mechanical connector structure  900  includes a lower mechanical part  902  and an upper mechanical part  904  that together receive the optical module  880 . Both lower and upper mechanical connector parts  902 ,  904  can be made of a heat-conducting and rigid material, e.g., a metal. 
     In some implementations, the upper mechanical part  904 , at its underside, is brought in thermal contact with the first serializers/deserializers chip  892  and the second serializers/deserializers chip  894 . The upper mechanical part  904  is also brought in thermal contact with the lower mechanical part  902 . The lower mechanical part  902  includes a removable latch mechanism, e.g., two wings  906  that can be elastically bent inwards (the movement of the wings  906  are represented by a double-arrow  908  in  FIG.  47   ), and each wing  906  includes a tongue  910  on an outer side. 
       FIG.  48    is a diagram of a portion of the first grid structure  870  and the circuit board  862 . Grooves  920  are provided on the walls of the first grid structure  870 . As shown in the figure, the printed circuit board  862  has electrical contacts  876  that can be electrically coupled to electrical contacts on the second slab  898  of the optical module  880 . 
     Referring to  FIG.  49   , when the lower mechanical part  902  is inserted into the first grid structure  870 , the tongues  910  (on the wings  906  of the lower mechanical part  902 ) can snap into corresponding grooves  920  within the first grid structure  870  to mechanically hold the optical module  880  in place. The position of the tongues  910  on the wings  906  is selected such that when the mechanical connector structure  900  and the optical module  880  are inserted into the first grid structure  870 , the electrical connectors at the bottom of the second slab  898  are electrically coupled to the electrical contacts  876  on the printed circuit board  862 . For example, the second slab  898  can include spring-loaded contacts that are mated with the contacts  876 . 
       FIG.  50    shows the front-view of an assembled front module  860 . Three optical module with connectors (e.g.,  868   a ,  868   b ,  868   c ) are inserted into the first grid structure  870 . In some embodiments, the optical modules  880  are arranged in a checkerboard pattern, whereby adjacent optical modules  880  and the corresponding mechanical connector structure  900  are rotated by 90 degrees such as to not allow any two wings to touch. This facilitates the removal of individual modules. In this example, the optical module with connector  868   a  is rotated 90 degrees relative to the optical module with connectors  868   b ,  868   c.    
       FIG.  51 A  shows a first side view of the mechanical connector structure  900 .  FIG.  51 B  shows a cross-sectional view of the mechanical connector structure  900  along a plane  930  shown in  FIG.  51 A . 
       FIG.  52 A  shows a first side view of the mechanical connector structure  900  mounted within the first grid structure  870 .  FIG.  52 B  shows a cross-sectional view of the mechanical connector structure  900  mounted within the first grid structure  870  along a plane  940  shown in  FIG.  52 A . 
       FIG.  53    is a diagram of an assembly  958  that includes a fiber cable  956  that includes a plurality of optical fibers, an optical fiber connector  950 , the mechanical connector module  900 , and the first grid structure  870 . The optical fiber connector  950  can be inserted into the mechanical connector module  900 , which can be further inserted into the first grid structure  870 . The printed circuit board  862  is attached to the first grid structure  870 , in which the electrical contacts  876  face electrical contacts  954  on the bottom side of the second slab  898  of the optical module  880 . 
       FIG.  53    shows the individual components before they are connected.  FIG.  54    is a diagram that shows the components after they are connected. The optical fiber connector  950  includes a lock mechanism  952  that disables the snap-in mechanism of the mechanical connector structure  900  so as to lock in place the mechanical connector structure  900  and the optical module  880 . In this example embodiment, the lock mechanism  952  includes studs on the optical fiber connector  950  that insert between the wings  906  and the upper mechanical part  904  of the mechanical connector module  900 , hence disabling the wings  906  from elastically bending inwards and consequentially locking the mechanical connector structure  900  and the optical module  880  in place. Further, the mechanical connector structure  900  includes a mechanism to hold the optical fiber connector  950  in place, such as a ball-detent mechanism as shown in the figure. When the optical fiber connector  950  is inserted into the mechanical connector structure  900 , spring-loaded balls  962  on the optical fiber connector  950  engage detents  964  in the wings  906  of the mechanical connector structure  900 . The springs push the balls  962  against the detents  964  and secure the optical fiber connector  950  in place. 
     To remove the optical module  880  from the first grid structure  870 , the user can pull the optical fiber connector  950  and cause the balls  962  to disengage from the detents  964 . The user can then bend the wings  906  inwards so that the tongues  910  disengage from the grooves  920  on the walls of the first grid structure  870 . 
       FIGS.  55 A and  55 B  show perspective views of the mechanisms shown in  FIGS.  53  and  54    before the optical fiber connector  950  is inserted into the mechanical connector structure  900 . As shown in  FIG.  55 B , the lower side of the optical connector  950  includes alignment structures  960  that mate with the alignment structures  886  ( FIG.  44   ) on the upper connector part  884  of the optical module  880 .  FIG.  55 B  also shows the photonic integrated circuit  896  and the second slab  898  that includes electrical contacts (e.g., spring-loaded electrical contacts). 
       FIG.  56    is a perspective view showing that the optical module  880  and the mechanical connector structure  900  are inserted into the first grid structure  870 , and the optical fiber connector  950  is separated from the mechanical connector structure  900 . 
       FIG.  57    is a perspective view showing that the optical fiber connector  950  is mated with the mechanical connector structure  900 , locking the optical module  880  within the mechanical connector structure  900 . 
       FIGS.  58 A to  58 D  show an alternate embodiment in which an optical module with connector  970  includes a latch mechanism  972  that acts as a mechanical fastener that joins the optical module  880  to the printed circuit board  862  using the first grid structure  870  as a support. For example, the user can easily attach or remove the optical module with connector  970  by pressing a lever  974  activating the latch mechanism  972 . The lever  974  is built in a way that it does not block the optical fibers (not shown in the figure) coming out of the optical module with connector  970 . Alternatively, an external tool can be used as a removable lever. 
       FIG.  59    is a view of an optical module  1030  that includes an optical engine with a latch mechanism used to realize the compression and attachment of the optical engine to the printed circuit board. The module  1030  is similar to the example shown in  FIG.  58 B  but without the compression interposer.  FIGS.  60 A and  60 B  show how the latch mechanism can be used for securing (with enough compression force) and removing the optical engine. 
       FIGS.  60 A and  60 B  show an example implementation of the lever  974  and the latch mechanism  972  in the optical module  1030 .  FIG.  60 A  shows an example in which the lever  974  is pushed down, causing the latch mechanism  972  to latch on to a support structure  976 , which can be part of the first grid structure  870 .  FIG.  60 B  shows an example in which the lever  974  is pulled up, causing the latch mechanism  972  to be released from the support structure  976 . 
       FIG.  61    is a diagram of an example of a fiber cable connection design  980  that includes nested fiber optic cable and co-packaged optical module connections. In this design, a co-packaged optical module  982  is removably coupled to a co-packaged optical port  1000  formed in a support structure, such as the first grid structure  870 , and a fiber connector  983  is removably coupled to the co-packaged optical module  982 . The fiber connector  983  is coupled to a fiber cable  996  that includes a plurality of optical fibers. The fiber cable connection can be designed to be, e.g., MTP/MPO (Multi-fiber Termination Push-on/Multi-fiber Push On) compatible, or compatible to new standards as they emerge. Multi-fiber push on (MPO) connectors are commonly used to terminate multi-fiber ribbon connections in indoor environments and conforms to IEC-61754-7; EIA/TIA-604-5 (FOCIS 5) standards. 
     In some implementations, the co-packaged optical module  982  includes a mechanical connector structure  984  and a smart optical assembly  986 . The smart optical assembly  986  includes, e.g., a photonic integrated circuit (e.g.,  896  of  FIG.  44   ), and components for guiding light, power splitting, polarization management, optical filtering, and other light beam management before the photonic integrated circuit. The components can include, e.g., optical couplers, waveguides, polarization optics, filters, and/or lenses. The mechanical connector structure  984  includes one or more fiber connector latches  988  and one or more co-packaged optical module latches  990 . The mechanical connector structure  984  can be inserted into the co-packaged optical port  1000  (e.g., formed in the first grid structure  870 ), in which the co-packaged optical module latches  990  engage grooves  992  in the walls of the first grid structure  870 , thus securing the co-packaged optical module  982  to the co-packaged optical port  1000 , and causing the electrical contacts of the smart optical assembly  986  to be electrically coupled to the electrical contacts  876  on the printed circuit board  862 . When the fiber connector  983  is inserted into the mechanical connector structure  984 , the fiber connector latches  988  engage grooves  994  in the fiber connector  983 , thus securing the fiber connector  983  to the co-packaged optical module  982 , and causing the fiber cable  996  to be optically coupled to the smart optical assembly  986 , e.g., through optical paths in the fiber connector  983 . 
     In some examples, the fiber connector  983  includes guide pins  998  that are inserted into holes in the smart optical assembly  986  to improve alignment of optical components (e.g., waveguides and/or lenses) in the fiber connector  983  to optical components (e.g., optical couplers and/or waveguides) in the smart optical assembly  986 . In some examples, the guide pins  998  can be chamfered shaped, or elliptical shaped that reduces wear. 
     In some implementations, after the fiber connector  983  is installed in the co-packaged optical module  982 , the fiber connector  983  prevents the co-packaged optical module latches  990  from bending inwards, thus preventing the co-packaged optical module  982  from being inserted into, or released from, the co-packaged optical port  1000 . To couple the fiber cable  996  to the data processing system, the co-packaged optical module  982  is first inserted into the co-packaged optical port  1000  without the fiber connector  983 , then the fiber connector  983  is inserted into the mechanical connector structure  984 . To remove the fiber cable  996  from the data processing system, the fiber connector  983  can be removed from the mechanical connector structure  984  while the co-packaged optical module  982  is still coupled to the co-packaged optical port  1000 . 
     In some implementations, the nested connection latches can be designed to allow the co-packaged optical module  982  to be inserted in, or removed from, the co-packaged optical port  1000  when a fiber cable is connected to the co-packaged optical module  982 . 
       FIGS.  62  and  63    are diagrams showing cross-sectional views of an example of a fiber cable connection design  1010  that includes nested fiber optic cable and co-packaged optical module connections.  FIG.  62    shows an example in which a fiber connector  1012  is removably coupled to a co-packaged optical module  1014 .  FIG.  63    shows an example in which the fiber connector  1012  is separated from the co-packaged optical module  1014 . 
       FIGS.  64  and  65    are diagrams showing additional cross-sectional views of the fiber cable connection design  1010 . The cross-sections are made along planes that vertically cut through the middle of the components shown in  FIGS.  62  and  63   .  FIG.  64    shows an example in which the fiber connector  1012  is removably coupled to the co-packaged optical module  1014 .  FIG.  65    shows an example in which the fiber connector  1012  is separated from the co-packaged optical module  1014 . 
     The following describes rack unit thermal architectures for rackmount systems (e.g.,  560  of  FIG.  22 ,  600    of  FIG.  23 ,  630    of  FIG.  24 ,  680    of  FIG.  26 ,  720    of  FIG.  28 ,  750    of  FIG.  29 ,  860    of  FIG.  43   ) that include data processing chips (e.g.,  572  of  FIGS.  22 ,  23 ,  640    of  FIG.  24 ,  682    of  FIG.  26 ,  722    of  FIG.  28 ,  758    of  FIG.  29 ,  864    of  FIG.  43   ) that are mounted on vertically oriented circuit boards that are substantially vertical to the bottom surfaces of the system housings or enclosures. In some implementations, the rack unit thermal architectures use air cooling to remove heat generated by the data processing chips. In these systems, the heat-generating data processing chips are positioned near the input/output interfaces, which can include, e.g., one or more of the integrated optical communication device  448 ,  462 ,  466 , or  472  of  FIG.  17   , the integrated communication device  574  of  FIG.  22  or  612    of  FIG.  23   , the optical/electrical communication interface  644  of  FIG.  24 ,  684    of  FIG.  26 ,  724    of  FIG.  28   , or  760  of  FIG.  29   , or the optical module with connector  868  of  FIG.  43   , that are positioned at or near the front panel to enable users to conveniently connect/disconnect optical transceivers to/from the rackmount systems. The rack unit thermal architectures described in this specification include mechanisms for increasing airflow across the surfaces of the data processing chips, or heat sinks thermally coupled to the data processing chips, taking into consideration that a substantial portion of the surface area on the front panel of the housing needs to be allocated to the input/output interfaces. 
     Referring to  FIG.  67   , a data server  1140  suitable for installation in a standard server rack can include a housing  1042  that has a front panel  1034 , a rear panel  1036 , a bottom panel  1038 , a top panel, and side panels  1040 . For example, the housing  1042  can have a 2 rack unit (RU) form factor, having a width of about 482.6 mm (19 inches) and a height of 2 rack units. One rack unit is about 44.45 mm (approximately 1.75 inches). A printed circuit board  1042  is mounted on the bottom panel  1038 , and at least one data processing chip  1044  is electrically coupled to the printed circuit board  1042 . A microcontroller unit  1046  is provided to control various modules, such as power supplies  1048  and exhaust fans  1050 . In this example, the exhaust fans  1050  are mounted at the rear panel  1036 . For example, single mode optical connectors  1052  are provided at the front panel  1034  for connection to external optical cables. Optical interconnect cables  1036  transmit signals between the single mode optical connectors  1052  and the at least one data processing chip  1044 . The exhaust fans  1050  mounted at the rear panel  1036  cause the air to flow from the front side to the rear side of the housing  1042 . The directions of air flow are represented by arrows  1058 . Warm air inside the housing  1042  is vented out of the housing  1042  through the exhaust fans  1050  at the rear panel  1036 . In this example, the front panel  1034  does not include any fan in order to maximize the area used for the single mode optical connectors  1052 . 
     For example, the data server  1300  can be a network switch server, and the at least one data processing chip  1044  can include at least one switch chip configured to process data having a total bandwidth of, e.g., about 51.2 Tbps. The at least one switch chip  1044  can be mounted on a substrate  1054  having dimensions of, e.g., about 100 mm×100 mm, and co-packaged optical modules  1056  can be mounted near the edges of the substrate  1054 . The co-packaged optical modules  1056  convert input optical signals received from the optical interconnect cables  1036  to input electrical signals that are provided to the at least one switch chip  1044 , and converts output electrical signals from the at least one switch chip  1044  to output optical signals that are provided to the optical interconnect cables  1036 . When any of the co-packaged optical modules  1056  fails, the user needs to remove the network switch server  1030  from the server rack and open the housing  1042  in order to repair or replace the faulty co-packaged optical module  1056 . 
     Referring to  FIGS.  68 A and  68 B , in some implementations, a rackmount server  1060  includes a housing or case  1062  having a front panel  1064  (or face plate), a rear panel  1036 , a bottom panel  1038 , a top panel, and side panels  1040 . For example, the housing  1062  can have a form factor of 1RU, 2RU, 3RU, or 4RU, having a width of about 482.6 mm (19 inches) and a height of 1, 2, 3, or 4 rack units. A first printed circuit board  1066  is mounted on the bottom panel  1038 , and a microcontroller unit  1046  is electrically coupled to the first printed circuit board  1066  and configured to control various modules, such as power supplies  1048  and exhaust fans  1050 . 
     In some implementations, the front panel  1064  includes a second printed circuit board  1068  that is oriented in a vertical direction, e.g., substantially perpendicular to the first circuit board  1066  and the bottom panel  1038 . In the following, the second printed circuit board  1068  is referred to as the vertical printed circuit board  1068 . The figures shows that the second printed circuit board  1066  forms part of the front panel  1064 , but in some examples the second printed circuit board  1066  can also be attached to the front panel  1064 , in which the front panel  1064  includes openings to allow input/output connectors to pass through. The second printed circuit board  1066  includes a first side facing the front direction relative to the housing  1062  and a second side facing the rear direction relative to the housing  1062 . At least one data processing chip  1070  is electrically coupled to the second side of the vertical printed circuit board  1068 , and a heat dissipating device or heat sink  1072  is thermally coupled to the at least one data processing chip  1070 . In some examples, the at least one data processing chip  1070  is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the printed circuit board  1068 .  FIG.  68 C  is a perspective view of an example of the heat dissipating device or heat sink  1072 . For example, the heat dissipating device  1072  can include a vapor chamber thermally coupled to heat sink fins. The exhaust fans  1050  mounted at the rear panel  1036  cause the air to flow from the front side to the rear side of the housing  1042 . The directions of air flow are represented by arrows  1078 . Warm air inside the housing  1042  is vented out of the housing  1042  through the exhaust fans  1050  at the rear panel  1036 . 
     Co-packaged optical modules  1074  (also referred to as the optical/electrical communication interfaces) are attached to the first side (i.e., the side facing the front exterior of the housing  1062 ) of the vertical printed circuit board  1068  for connection to external fiber cables  1076 . Each fiber cable  1076  can include an array of optical fibers. By placing the co-packaged optical modules  1074  on the exterior side of the front panel  1064 , the user can conveniently service (e.g., repair or replace) the co-packaged optical modules  1074  when needed. Each co-packaged optical module  1074  is configured to convert input optical signals received from the external fiber cable  1076  into input electrical signals that are transmitted to the at least one data processing chip  1070  through signal lines in or on the vertical printed circuit board  1068 . The co-packaged optical module  1074  also converts output electrical signals from the at least one data processing chip  1070  into output optical signals that are provided to the external fiber cables  1076 . Warm air inside the housing  1062  is vented out of the housing  1062  through the exhaust fans  1050  mounted at the rear panel  1036 . 
     For example, the at least one data processing chip  1070  can include a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, or an application specific integrated circuit (ASIC). For example, each co-packaged optical module  1074  can include a module similar to the integrated optical communication device  448 ,  462 ,  466 , or  472  of  FIG.  17   , the integrated optical communication device  210  of  FIG.  20   , the integrated communication device  612  of  FIG.  23   , the optical/electrical communication interface  684  of  FIG.  26 ,  724    of  FIG.  28   , or  760  of  FIG.  29   , the integrated optical communication device  512  of  FIG.  32   , or the optical module with connector  868  of  FIG.  43   . For example, each fiber cable  1076  can include the optical fibers  226  ( FIGS.  2 ,  4   ),  272  ( FIGS.  6 ,  7   ),  582  ( FIG.  22 ,  23   ), or  734  ( FIG.  28   ), or the optical fiber cable  762  ( FIG.  762   ),  956  ( FIG.  53   ), or  996  ( FIG.  61   ). 
     For example, the co-packaged optical module  1074  can include a first optical connector part (e.g.,  456  of  FIG.  17 ,  578    of  FIG.  22  or  23 ,  746    of  FIG.  28   ) that is configured to be removably coupled to a second optical connector part (e.g.,  458  of  FIG.  17 ,  580    of  FIG.  22  or  23 ,  748    of  FIG.  28   ) that is attached to the external fiber cable  1076 . For example, the co-packaged optical module  1074  includes a photonic integrated circuit (e.g.,  450 ,  464 ,  468 , or  474  of  FIG.  17 ,  586    of  FIG.  22 ,  618    of  FIG.  23   , or  726  of  FIG.  28   ) that is optically coupled to the first optical connector part. The photonic integrated circuit receives input optical signals from the first optical connector part and generates input electrical signals based on the input optical signals. At least a portion of the input electrical signals generated by the photonic integrated circuit are transmitted to the at least one data processing chip  1070  through electrical signal lines in or on the vertical printed circuit board  1068 . For example, the photonic integrated circuit can be configured to receive output electrical signals from the at least one data processing chip  1070  and generate output optical signals based on the output electrical signals. The output optical signals are transmitted through the first and second optical connector parts to the external fiber cable  1076 . 
     In some examples, the fiber cable  1076  can include, e.g., 10 or more cores of optical fibers, and the first optical connector part is configured to couple 10 or more channels of optical signals to the photonic integrated circuit. In some examples, the fiber cable  1076  can include 100 or more cores of optical fibers, and the first optical connector part is configured to couple 100 or more channels of optical signals to the photonic integrated circuit. In some examples, the fiber cable  1076  can include 500 or more cores of optical fibers, and the first optical connector part is configured to couple 500 or more channels of optical signals to the photonic integrated circuit. In some examples, the fiber cable  1076  can include 1000 or more cores of optical fibers, and the first optical connector part is configured to couple 1000 or more channels of optical signals to the photonic integrated circuit. 
     In some implementations, the photonic integrated circuit can be configured to generate first serial electrical signals based on the received optical signals, in which each first serial electrical signal is generated based on one of the channels of first optical signals. Each co-packaged optical module  1074  can include a first serializers/deserializers module that includes serializer units and deserializer units, in which the first serializers/deserializers module is configured to generate sets of first parallel electrical signals based on the first serial electrical signals and condition the electrical signals, and each set of first parallel electrical signals is generated based on a corresponding first serial electrical signal. Each co-packaged optical module  1074  can include a second serializers/deserializers module that includes serializer units and deserializer units, in which the second serializers/deserializers module is configured to generate second serial electrical signals based on the sets of first parallel electrical signals, and each second serial electrical signal is generated based on a corresponding set of first parallel electrical signals. 
     In some examples, the rackmount server  1060  can include 4 or more co-packaged optical modules  1074  that are configured to be removably coupled to corresponding second optical connector parts that are attached to corresponding fiber cables  1076 . For example, the rackmount server  1060  can include 16 or more co-packaged optical modules  1074  that are configured to be removably coupled to corresponding second optical connector parts that are attached to corresponding fiber cables  1076 . In some examples, each fiber cable  1076  can include 10 or more cores of optical fibers. In some examples, each fiber cable  1076  can include 100 or more cores of optical fibers. In some examples, each fiber cable  1076  can include 500 or more cores of optical fibers. In some examples, each fiber cable  1076  can include 1000 or more cores of optical fibers. Each optical fiber can transmit one or more channels of optical signals. For example, the at least one data processing chip  1070  can include a network switch that is configured to receive data from an input port associated with a first one of the channels of optical signals, and forward the data to an output port associated with a second one of the channels of optical signals. 
     In some implementations, the co-packaged optical modules  1074  is removably coupled to the vertical printed circuit board  1068 . For example, the co-packaged optical modules  1074  can be electrically coupled to the vertical printed circuit board  1068  using electrical contacts that include, e.g., spring-loaded elements, compression interposers, or land-grid arrays. 
     Referring to  FIGS.  69 A and  69 B , in some implementations, a rackmount server  1080  includes a housing  1082  having a front panel  1084 . The rackmount server  1080  is similar to the rackmount server  1060  of  FIG.  68 A , except that one or more fans are mounted on the front panel  1084 , and one or more air louvers installed in the housing  1082  to direct air flow towards the heat dissipating device. For example, the rackmount server  1080  can include a first inlet fan  1086   a  mounted on the front panel  1084  to the left of the vertical printed circuit board  1068 , and a second inlet fan  1086   b  mounted on the front panel  1084  to the right of the vertical printed circuit board  1068 . The terms “right” and “left” refer to relative positions of components shown in the figure. It is understood that, depending on the orientation of a device having a first and second modules, a first module that is positioned to the “left” or “right” of a second module can in fact be to the “right” or “left” (or any other relative position) of the second module. The inlet and exhaust fans operate in a push-pull manner, in which the inlet fans  1086   a  and  1086   b  (collectively referenced as  1086 ) pull cool air into the housing  1082 , and the exhaust fans  1050  push warm air out of the housing  1082 . The inlet fans  1086  in the front panel or face plate  1064  and the exhaust fans  1050  on the backside of the rack generate a pressure gradient through the housing or case to improve air cooling compared to standard 1RU implementations that include on backside exhaust fans. 
     In some implementations, a left air louver  1088   a  and a right air louver  1088   b  are installed in the housing  1082  to direct airflow toward the heat dissipating device  1072 . The air louvers  1088   a ,  1088   b  (collectively referenced as  1088 ) partitions the space in the housing  1082  and forces air to flow from the inlet fans  1086   a  and  1086   b , pass over surfaces of fins of the heat dissipating device  1072 , and towards an opening  1090  between distal ends of the air louvers  1088 . The directions of air flow near the inlet fans  1086   a  and  1086   b  are represented by arrows  1092   a  and  1092   b . The air louvers  1088  increase the amount of air flows across the surfaces of the heat sink fins and enhance the efficiency of heat removal. The heat sink fins are oriented to extend along planes that are substantially parallel to the bottom surface  1038  of the housing  1082 . For example, the air louvers  1088  can have a curved shape, e.g., an S-shape as shown in the figure. The curved shape of the air louvers  1088  can be configured to maximize the efficiency of the heat sink. In some examples, the air louvers  1088  can also have a linear shape. 
     For example, the heat sink can be a plate-fin heat sink, a pin-fin heat sink, or a plate-pin-fin heat sink. The pins can have a square or circular cross section. The heat sink configuration (e.g., pin pitch, length of pins or fins) and the louver configuration can be designed to optimize heat sink efficiency. 
     For example, the co-packaged optical modules  1074  can be electrically coupled to the vertical printed circuit board  1068  using electrical contacts that include, e.g., spring-loaded elements, compression interposers, or land-grid arrays. For example, when compression interposers are used, the vertical circuit board  1068  can be positioned such that the face of compression interposers of the co-packaged optical module  1074  is coplanar with the face plate  1064  and the inlet fans  1086 . 
     Referring to  FIG.  70   , in some implementations, a rackmount server  1090  is similar to the rackmount server  1080  of  FIG.  69   , which includes inlet fans mounted on the front panel. The inlet fans of the rackmount server  1090  are slightly rotated, as compared to the inlet fans of the rackmount server  1080  to improve efficiency of the heat sink. The rotational axes of the inlet fans, instead of being parallel to the front-to-rear direction relative to the housing  1082 , can be rotated slightly inwards. For example, the rotational axis of a left inlet fan  1092   a  can be rotated slightly clockwise and the rotational axis of a right inlet fan  1092   b  can be rotated slightly counter-clockwise, to enhance the air flow across the surfaces of the heat sink fins, further improving the efficiency of heat removal. 
     In some implementations heat removal efficiency can be improved by positioning the vertical circuit board  1068  and the heat dissipating device  1072  further toward the rear of the housing so that a larger amount of air flows across the surface of the fins of the heat dissipating device  1072 . 
     Referring to  FIGS.  71 A to  71 B , a rackmount server  1100  includes a housing  1102  having a front panel or face plate  1104 , in which the portion of the face plate  1104  where the compression interposers for the co-packaged optical module  1074  are located are inset by a distance d with respect to the original face plate  1104 . The face plate  1104  has a recessed portion or an inset portion  1106  that is offset at a distance d (referred to as the “front panel inset distance”) toward the rear of the housing  1102  relative to the other portions (e.g., the portions on which the inlet fans  1086   a  and  1086   b  are mounted) of the front panel  1104 . The inset portion  1106  is referred to as the “recessed front panel,” “recessed face plate,” “front panel inset,” or “face plate inset.” The vertical printed circuit board  1068  is attached to the inset portion  1106 , which includes openings to allow the co-packaged optical modules  1074  to pass through. The inset portion  1106  is configured to have sufficient area to accommodate the co-packaged optical modules  1074 . 
     By providing the inset portion  1106  in the front panel  1104 , the fins of the heat dissipating device  1072  can be more optimally positioned to be closer to the main air flow generated by the inlet fans  1086 , while maintaining serviceability of the co-packaged optical modules  1074 , e.g., allowing the user to repair or replace damaged co-packaged optical modules  1074  without opening the housing  1102 . The heat sink configuration (e.g., pin pitch, length of pins or fins) and the louver configuration can be designed to optimize heat sink efficiency. In addition, the front panel inset distance d can be optimized to improve heat sink efficiency. 
     Referring to  FIG.  72   , in some implementations, a rackmount server  1110  is similar to the rackmount server  1100  of  FIG.  71   , except that the server  1110  includes a heat dissipating device  1112  that has fins  1114   a  and  1114   b  that extend beyond the edge of the vertical printed circuit board  1068  and closer to the inlet fans  1086   a ,  1086   b , as compared to the fins in the example of  FIG.  71   . The configuration of the fins (e.g., the shapes, sizes, and number of fins) can be selected to maximize the efficiency of heat removal. 
     Referring to  FIGS.  73 A and  73 B , in some implementations, a rackmount server  1120  includes a housing  1122  having a front panel  1124 , a rear panel  1036 , a bottom panel  1038 , a top panel, and side panels  1040 . The width and height of the housing  1122  can be similar to those of the housing  1062  of  FIG.  68 A . The server  1120  includes a first printed circuit board  1066  that extends parallel to the bottom panel  1038 , and one or more vertical printed circuit boards, e.g.,  1126   a  and  1126   b  (collectively referenced as  1126 ), that are mounted perpendicular to the first printed circuit board  1066 . The server  1120  includes one or more inlet fans  1086  mounted on the front panel  1124  and one or more exhaust fans  1050  mounted on the rear panel  1036 . The air flow in the housing  1122  is generally in the front-to-rear direction. The directions of the air flows are represented by the arrows  1134 . 
     Each vertical printed circuit board  1126  has a first surface and a second surface. The first surface defines the length and width of the vertical printed circuit board  1126 . The distance between the first and second surfaces defines the thickness of the vertical printed circuit board  1126 . The vertical printed circuit board  1126   a  or  1126   b  is oriented such that the first surface extends along a plane that is substantially parallel to the front-to-rear direction relative to the housing  1122 . At least one data processing chip  1128   a  or  1128   b  is electrically coupled to the first surface of the vertical printed circuit board  1126   a  or  1126   b , respectively. In some examples, the at least one data processing chip  1128   a  or  1128   b  is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the printed circuit board  1126   a  or  1126   b . A heat dissipating device  1130   a  or  1130   b  is thermally coupled to the at least one data processing chip  1128   a  or  1128   b , respectively. The heat dissipating device  1130  includes fins that extend along planes that are substantially parallel to the bottom panel  1038  of the housing  1122 . The heat sinks  1130   a  and  1130   b  are positioned directly behind to the inlet fans  1086   a  and  1086   b , respectively, to maximize air flow across the fins and/or pins of the heat sinks  1130 . 
     At least one co-packaged optical module  1132   a  or  1132   b  is mounted on the second side of the vertical printed circuit board  1126   a  or  1126   b , respectively. The co-packaged optical modules  1132  are optically coupled, through optical interconnection links, to optical interfaces (not shown in the figure) mounted on the front panel  1124 . The optical interfaces are optically coupled to external fiber cables. The orientations of the vertical printed circuit boards  1126  and the fins of the heat dissipating devices  1130  are selected to maximize heat removal. 
     Referring to  FIGS.  74 A to  74 B , in some implementations, a rackmount server  1150  includes vertical printed circuit boards  1152   a  and  1152   b  (collectively referenced as  1152 ) that have surfaces that extend along planes substantially parallel to the front-to-rear direction relative to the housing or case, similar to the vertical printed circuit boards  1126   a  and  1126   b  of  FIG.  73   . The rackmount server  1150  includes a housing  1154  that has a modified front panel or face plate  1156  that has an inset portion  1158  configured to improve access and field serviceability of co-packaged optical modules  1160   a  and  1160   b  (collectively referenced as  1160 ) that are mounted on the vertical printed circuit boards  1152   a  and  1152   b , respectively. The inset portion  1158  is referred to as the “front panel inset” or “face plate inset.” The inset portion  1158  has a width w that is selected to enable hot-swap, in-field serviceability of the co-packaged optical modules  1160  to avoid the need to take the rackmount server  1150  out of service for maintenance. 
     For example, the inset portion  1158  includes a first wall  1162 , a second wall  1164 , and a third wall  1166 . The first wall  1162  is substantially parallel to the second wall  1164 , and the third wall  1166  is positioned between the first wall  1162  and the second wall  1164 . For example, the first wall  1162  extends along a direction that is substantially parallel to the front-to-rear direction relative to the housing  1122 . The vertical printed circuit board  1152   a  is attached to the first wall  1162  of the inset portion  1158 , and the vertical printed circuit board  1152   b  is attached to the first wall  1162  of the inset portion  1158 . The first wall  1162  includes openings to allow the co-packaged optical modules  1160   a  to pass through, and the second wall  1164  includes openings to allow the co-packaged optical modules  1160   b  to pass through. For example, an inlet fan  1086   c  can be mounted on the third wall  1166 . 
     Each vertical printed circuit board  1152  has a first surface and a second surface. The first surface defines the length and width of the vertical printed circuit board  1152 . The distance between the first and second surfaces defines the thickness of the vertical printed circuit board  1152 . The vertical printed circuit board  1152   a  or  1152   b  is oriented such that the first surface extends along a plane that is substantially parallel to the front-to-rear direction relative to the housing  1154 . At least one data processing chip  1170   a  or  1170   b  is electrically coupled to the first surface of the vertical printed circuit board  1152   a  or  1152   b , respectively. In some examples, the at least one data processing chip  1170   a  or  1170   b  is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the printed circuit board  1152   a  or  1152   b . A heat dissipating device  1168   a  or  1168   b  is thermally coupled to the at least one data processing chip  1170   a  or  1170   b , respectively. The heat dissipating device  1168  includes fins that extend along planes that are substantially parallel to the bottom panel  1038  of the housing  1154 . The heat sinks  1168   a  and  1168   b  are positioned directly behind to the inlet fans  1086   a  and  1086   b , respectively, to maximize air flow across the fins and/or pins of the heat sinks  1168   a  and  1168   b.    
     Referring to  FIGS.  75 A to  75 B , in some implementations, a rackmount server  1180  includes a housing  1182  having a front panel  1184  that has an inset portion  1186  (referred to as the “front panel inset” or “face plate inset”). For example, the inset portion  1186  includes a first wall  1188  and a second wall  1190  that are oriented to make it easier for the user to connect or disconnect the fiber cables (e.g.,  1076 ) to the server  1180 , or to service the co-packaged optical modules  1074 . For example, the first wall  1188  can be at an angle θ 1  relative to a nominal plane  1192  of the front panel  1184 , in which 0&lt;θ 1 &lt;90°. The second wall  1190  can be at an angle θ 2  relative to the nominal plane  1192  of the front panel, in which 0&lt;θ 2 &lt;90°. The angles θ 1  and θ 2  can be the same or different. The nominal plane  1192  of the front panel  1184  is perpendicular to the side panels  1040  and the bottom panel. 
     For example, a first vertical printed circuit board  1152   a  is attached to the first wall  1188 , and a second vertical printed circuit board  1152   b  is attached to the second wall  1190 . Comparing the rackmount server  1180  with the rackmount servers  1060  of  FIG.  68 A,  1080    of  FIG.  69 A, and  1100    of  FIG.  71   , the server  1180  has a larger front panel area due to the angled front panel inset and can be connected to more fiber cables. 
     Positioning the first and second walls  1188 ,  1190  at an angle between 0 and 90° relative to the nominal plane of the front panel improves access and field serviceability of the co-packaged optical modules. Comparing the rackmount server  1180  with the rackmount server  1150  of  FIG.  74 A , the server  1180  allows the user to more easily access the co-packaged optical modules that are positioned farther away from the nominal plane of the front panel. The angles θ 1  and θ 2  are selected to strike a balance between increasing the number of fiber cables that can be connected to the server and providing easy access to all of the co-packaged optical modules of the server. The front panel inset width and angle are configured to enable hot-swap, in-field serviceability to avoid taking the switch and rack out of service for maintenance. 
     For examples, intake fans  1086   a  and  1086   b  can be mounted on the front panel  1184 . Outside air is drawn in by the intake fans  1086   a ,  1086   b , passes through the surfaces of the fins and/or pins of the heatsinks  1168   a ,  1168   b , and flows towards the rear of the housing  1182 . Examples of the flow directions for the air entering through the intake fans  1186   a  and  1186   b  are represented by arrows  1198   a ,  1198   b ,  1198   c , and  1198   d.    
     Referring to  FIGS.  75 B and  75 C , in some implementations, the front panel  1184  includes an upper air vent  1194   a  and baffles to direct outside air to enter through the upper air vent  1194   a , flows downward and rearward such that the air passes over the surfaces of some of the fins and/or pins of the heat sinks  1186  (e.g., including the fins and/or pins closer to the top of the heat sinks  1186 ) and then flows toward an intake fan  1086   c  mounted at or near the distal or rear end of the front panel inset portion  1186 . The front panel  1184  includes a lower air vent  1194   b  and baffles to direct outside air to enter through the lower air vent  1194   b , flows upward and rearward such that the air passes over the surfaces of some of the fins and/or pins of the heat sinks  1186  (e.g., including the fins and/or pins closer to the bottom of the heat sinks  1186 ) and then flows toward the intake fan  1086   c . Examples of the air flows through the upper and lower air vents  1194   a ,  1194   b  to the intake fan  1086   c  are represented by arrows  1196   a ,  1196   b ,  1196   c , and  1196   d  in  FIG.  75 C . 
     For example, fiber cables connected to the co-packaged optical modules  1074  can block air flow for the intake fan  1086   c  if the intake fan  1086   c  is configured to receive air through openings directly in front of the intake fan  1086   c . By using the upper air vent  1194   a , the lower air vent  1194   b , and the baffles to direct air flow as described above, the heat dissipating efficiency of the system can be improved (as compared to not having the air vents  1194  and the baffles). 
     Referring to  FIG.  76   , in some implementations, a network switch system  1210  includes a plurality of rackmount switch servers  1212  installed in a server rack  1214 . The network switch rack includes a top of the rack switch  1216  that routes data among the switch servers  1212  within the network switch system  1210 , and serves as a gateway between the network switch system  1210  and other network switch systems. The rackmount switch servers  1212  in the network switch system  1210  can be configured in a manner similar to any of the rackmount servers described above or below. 
     In some implementations, the examples of rackmount servers shown in in  FIGS.  68 A,  69 A, and  70    can be modified by positioning the vertical printed circuit board behind the front panel. The co-packaged optical modules can be optically connected to fiber connector parts mounted on the front panel through short optical connection paths, e.g., fiber jumpers. 
     Referring to  FIGS.  77 A and  77 B , in some implementations, a rackmount server  1220  includes a housing  1222  having a front panel  1224 , a rear panel  1036 , a top panel  1226 , a bottom panel  1038 , and side panels  1040 . The front panel  1224  can be opened to allow the user to access components without removing the rackmount server  1220  from the rack. A vertically mounted printed circuit board  1230  is positioned substantially parallel to the front panel  1224  and recessed from the front panel  1224 , i.e., spaced apart at a small distance (e.g., less than 6 inches, or less than 3 inches, or less than 2 inches) to the rear of the front panel  1224 . The printed circuit board  1230  includes a first side facing the front direction relative to the housing  1222  and a second side facing the rear direction relative to the housing  1222 . At least one data processing chip  1070  is electrically coupled to the second side of the vertical printed circuit board  1226 , and a heat dissipating device or heat sink  1072  is thermally coupled to the at least one data processing chip  1070 . In some examples, the at least one data processing chip  1070  is mounted on a substrate (e.g., a ceramic substrate), and the substrate is attached to the printed circuit board  1226 . 
     Co-packaged optical modules  1074  (also referred to as the optical/electrical communication interfaces) are attached to the first side (i.e., the side facing the front exterior of the housing  1222 ) of the vertical printed circuit board  1230 . In some examples, the co-packaged optical modules  1074  are mounted on a substrate that is attached to the vertical printed circuit board  1230 , in which electrical contacts on the substrate are electrically coupled to corresponding electrical contacts on the vertical printed circuit board  1230 . In some examples, the at least one data processing chip  1070  is mounted on the rear side of the substrate, and the co-packaged optical modules  1074  are removably attached to the front side of the substrate, in which the substrate provides high speed connections between the at least one data processing chip  1070  and the co-packaged optical modules  1074 . For example, the substrate can be attached to a front side of the printed circuit board  1068 , in which the printed circuit board  1068  includes one or more openings that allow the at least one data processing chip  1070  to be mounted on the rear side of the substrate. The printed circuit board  1068  can provide from a motherboard electrical power to the substrate (and hence to the at least one data processing chip  1070  and the co-packaged optical modules  1074 , and allow the at least one data processing chip  1070  and the co-packaged optical modules  1074  to connect to the motherboard using low-speed electrical links. An array of co-packaged optical modules  1074  can be mounted on the vertical printed circuit board  1230  (or the substrate), similar to the examples shown in  FIGS.  69 B and  71 B . The electrical connections between the co-packaged optical modules  1074  and the vertical printed circuit board  1070  (or the substrate) can be removable, e.g., by using land-grid arrays and/or compression interposers. The co-packaged optical modules  1074  are optically connected to first fiber connector parts  1232  mounted on the front panel  1224  through short fiber jumpers  1234   a ,  1234   b  (collectively referenced as  1234 ). When the front panel  1224  is closed, the user can plug a second fiber connector part  1236  into the first fiber connector part  1232  on the front panel  1224 , in which the second fiber connector part  1236  is connected to an optical fiber cable  1238  that includes an array of optical fibers. 
     In some implementations, the rackmount server  1220  is pre-populated with co-packaged optical modules  1074 , and the user does not need to access the co-packaged optical modules  1074  unless the modules need maintenance. During normal operation of the rackmount server  1220 , the user mostly accesses the first fiber connector parts  1232  on the front panel  1224  to connect to fiber cables  1238 . 
     One or more intake fans, e.g.,  1086   a ,  1086   b , can be mounted on the front panel  1224 , similar to the examples shown in  FIGS.  69 A and  70   . The positions and configurations of the intake fans  1086 , the heat sink  1072 , and the air louvers  1088   a ,  1088   b  are selected to maximize the heat transfer efficiency of the heat sink  1072 . 
     The rackmount server  1220  can have a number of advantages. By placing the vertical printed circuit board  1230  at a recessed position inside the housing  1222 , the vertical printed circuit board  1230  is better protected by the housing  1222 , e.g., preventing users from accidentally bumping into the circuit board  1230 . By orienting the vertical printed circuit board  1230  substantially parallel to the front panel  1224  and mounting the co-packaged optical modules  1074  on the side of the circuit board  1230  facing the front direction, the co-packaged optical modules  1074  can be accessible to users for maintenance without the need to remove the rackmount server  1220  from the rack. 
     In some implementations, the front panel  1224  is coupled to the bottom panel  1038  using a hinge  1228  and configured such that the front panel  1224  can be securely closed during normal operation of the rackmount server  1220  and easily opened for maintenance. For example, if a co-packaged optical module  1074  fails, a technician can open and rotate the front panel  1224  down to a horizontal position to gain access to the co-packaged optical module  1074  to repair or replace it. For example, the movements of the front panel  1224  is represented by the bi-directional arrow  1250 . In some implementations, different fiber jumpers  1234  can have different lengths, depending on the distance between the parts that are connected by the fiber jumpers  1234 . For example, the distance between the co-packaged optical module  1074  and the first fiber connector part  1232  connected by the fiber jumper  1234   a  is less than the distance between the co-packaged optical module  1074  and the first fiber connector part  1232  connected by the fiber jumper  1234   b , so the fiber jumper  1234   a  can be shorter than the fiber jumper  1234   b . This way, by using fiber jumpers with appropriate lengths, it is possible to reduce the clutter caused by the fiber jumpers  1234  inside the housing  1222  when the front panel  1224  is closed and in its vertical position. 
     In some implementations, the front panel  1224  can be configured to be opened and lifted upwards using lift-up hinges. This can be useful when the rackmount server is positioned near the top of the rack. In some examples, the front panel  1224  can be coupled to the side panel  1040  by using a hinge so that the front panel  1224  can be opened and rotated sideways. In some examples, the front panel can include a left front subpanel and a right front subpanel, in which the left front subpanel is coupled to the left side panel  1040  by using a first hinge, and the right front subpanel is coupled to the right panel  1040  by using a second hinge. The left front subpanel can be opened and rotated towards the left side, and the right front subpanel can be opened and rotated towards the right side. These various configurations for the front panel enable protection of the vertical printed circuit board  1230  and convenient access to the co-packaged optical modules  1074 . 
     In some examples, the front panel can have an inset portion, similar to the example shown in  FIG.  71 A , in which the vertical printed circuit board is in a recessed position relative to the inset portion of the front panel, i.e., at a small distance to the rear of the inset portion of the front panel. The front panel inset distance, the distance between the vertical printed circuit board and the front panel inset portion, and the air louver configuration can be selected to maximize the heat sink efficiency. 
     Referring to  FIG.  78   , in some implementations, a rackmount server  1240  can be similar to the rackmount server  1150  of  FIG.  74 A , except that the vertical printed circuit boards are at recessed positions relative to the walls of the inset portion of the front panel. For example, a vertical printed circuit board  1152   a  is in a recessed position relative to a first wall  1242   a  of an inset portion  1244 , i.e., the vertical printed circuit board  1152   a  is spaced apart a small distance to the left from the first wall  1242   a . A vertical printed circuit board  1152   b  is in a recessed position relative to a second wall  1242   b  of the inset portion  1244 , i.e., the vertical printed circuit board  1152   b  is spaced apart a small distance to the right from the second wall  1242   b.    
     For example, the first wall  1242   a  can be coupled to the bottom or top panel through hinges so that the first wall  1242   a  can be closed during normal operation of the rackmount server  1240  and opened for maintenance of the server  1240 . The distance w 2  between the first wall  1242   a  and the second wall  1242   b  is selected to be sufficiently large to enable the first wall  1242   a  and the second wall  1242   b  to be opened properly. This design has advantages similar to those of the rackmount server  1220  in  FIGS.  77 A,  77 B . 
     In some implementations, a rackmount server can be similar to the rackmount server  1180  shown in  FIGS.  75 A to  75 C , except that the vertical printed circuit boards are at recessed positions relative to the walls of the inset portion of the front panel. For example, a first vertical printed circuit board is in a recessed position relative to the first wall  1188  of the inset portion  1186 , and a second vertical printed circuit board is in a recessed position relative to the second wall  1190  of the inset portion  1186 . For example, the first wall  1188  can be coupled to the bottom or top panel through hinges so that the first wall  1188  can be closed during normal operation of the rackmount server and opened for maintenance of the server. The angles θ 1  and θ 2  are selected to enable the first wall  1188  and the second wall  1190  to be opened properly. This design has advantages similar to those of the rackmount server  1220  in  FIGS.  77 A,  77 B . 
     A feature of the thermal architecture for the rackmount units (e.g., the rackmount servers  1060  of  FIG.  68 A,  1090    of  FIGS.  69 A,  70 ,  1100    of  FIGS.  71 A,  72 ,  1120    of  FIG.  73 A,  1150    of  FIG.  74 A,  1180    of  FIG.  75 A,  1220    of  FIG.  77 B, and  1240    of  FIG.  78   ) described above is the use of co-packaged optical modules or optical/electrical communication interfaces that have higher bandwidth per module or interface, as compared to conventional designs. For example, each co-packaged optical module or optical/electrical communication interface can be coupled to a fiber cable that carries a large number of densely packed optical fiber cores.  FIG.  9    shows an example of the integrated optical communication device  282  in which the optical signals provided to the photonic integrated circuit can have a total bandwidth of about 12.8 Tbps. By using co-packaged optical modules or optical/electrical communication interfaces that have higher bandwidth per module or interface, the number of co-packaged optical modules or optical/electrical communication interfaces required for a given total bandwidth for the rackmount unit is reduced, so the amount of area on the front panel of the housing reserved for connecting to optical fibers can be reduced. Therefore, it is possible to add one or more inlet fans on the front panel to improve thermal management while still maintaining or even increasing the total bandwidth of the rackmount unit, as compared to conventional designs. 
     In some implementations, for the examples shown in  FIGS.  72 ,  74 A,  75 A, and  78   , and the variations in which the vertical printed circuit boards are at recessed positions relative to the front panel, the shape of each of the top and bottom panels of the housing can have an inset portion at the front that corresponds to the inset portion of the front panel. This makes it more convenient to access the co-packaged optical modules or the optical connector parts mounted on the front panel without being hindered by the top and bottom panels. In some implementations, the server rack (e.g.,  1214  of  FIG.  76   ) is designed such that front support structures of the server rack also have inset portions that correspond to the insert portions of the front panels of the rackmount servers installed in the server rack. For example, a custom server rack can be designed to install rackmount servers that all have the inset portions similar to the inset portion  1158  of  FIG.  74 A . For example, a custom server rack can be designed to install rackmount servers that all have the inset portions similar to the inset portion  1186  of  FIG.  75 A . In such examples, the inset portions extend vertically from the bottom-most server to the top-most server without any obstruction, making it easier for the user to access the co-packaged optical modules or optical connector parts. 
     In some implementations, for the examples shown in  FIGS.  72 ,  74 A,  75 A, and  78   , and the variations in which the vertical printed circuit boards are at recessed positions relative to the front panel, the shape of the top and bottom panels of the housing can be similar to standard rackmount units, e.g., the top and bottom panels can have a generally rectangular shape. 
     In the examples shown in  FIGS.  68 A,  68 B,  69 A to  75 C, and  77 A to  78   , a grid structure similar to the grid structure  870  shown in  FIG.  43    can be attached to the vertical printed circuit board. The grid structure can function as both (i) a heat spreader/heat sink and (ii) a mechanical holding fixture for the co-packaged optical modules (e.g.,  1074 ) or optical/electrical communication interfaces. 
       FIGS.  96  to  97 B  are diagrams of an example of a rackmount server  1820  that includes a vertically oriented circuit board  1822  positioned at a front portion of the rackmount server  1820 .  FIG.  96    shows a top view of the rackmount server  1820 ,  FIG.  97 A  shows a perspective view of the rackmount server  1820 , and  FIG.  97 B  shows a perspective view of the rackmount server  1820  with the top panel removed. The rackmount server  1820  has an active airflow management system that is configured to remove heat from a data processor during operation of the rackmount server  1820 . 
     Referring to  FIGS.  96 ,  97 A, and  97 B , in some implementations, the rackmount server  1820  includes a housing  1824  that has a front panel  1826 , a left side panel  1828 , a right side panel  1840 , a bottom panel  1841 , a top panel  1843 , and a rear panel  1842 . The front panel  1826  can be similar to the front panels in the examples shown in  FIGS.  68 A,  68 B,  69 A to  72 ,  77 A, and  77 B . For example, the vertically oriented circuit board  1822  can be part of the front panel  1826 , or attached to the front panel  1826 , or positioned in a vicinity of the front panel  1826 , in which a distance between the circuit board  1822  and the front panel  1826  is not more than, e.g., 6 inches. A data processor  1844  (which can be, e.g., a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, or an application specific integrated circuit)(see  FIG.  99   ) is mounted on the circuit board  1822 . 
     A heat dissipating module  1846 , e.g., a heat sink, is thermally coupled to the data processor  1844  and configured to dissipate heat generated by the data processor  1828  during operation. The heat dissipating module  1846  can be similar to the heat dissipating device  1072  of  FIGS.  68 A,  68 C,  69 A,  70 , and  71 A . In some examples, the heat dissipating module  1846  includes heat sink fins or pins having heat dissipating surfaces configured to optimize heat dissipation. In some examples, the heating dissipating module  1846  includes a vapor chamber thermally coupled to heat sink fins or pins. The rackmount server  1820  can include other components, such as power supply units, rear outlet fans, one or more additional horizontally oriented circuit boards, one or more additional data processors mounted on the horizontally oriented circuit boards, and one or more additional air louvers, that have been previously described in other embodiments of rackmount servers and are not repeated here. 
     In some implementations, the active airflow management system includes an inlet fan  1848  that is positioned at a left side of the heat dissipating module  1846  and oriented to blow incoming air to the right toward the heat dissipating module  1846 . A front opening  1850  provides incoming air for the inlet fan  1848 . The front opening  1850  can be positioned to the left of the inlet fan  1848 . In the example of  FIG.  96   , the circuit board  1822  is substantially parallel to the front panel  1826 , and the rotational axis of the inlet fan  1848  is substantially parallel to the plane of the circuit board  1822 . The inlet fan  1848  can also be oriented slightly differently. For example, the rotational axis of the inlet fan  1848  can be at an angle θ relative to the plane of the front panel  1826 , the angle θ being measured along a plane parallel to the bottom panel  1841 , in which θ≤45°, or in some examples θ≤25°, or in some examples θ≤5°, or in some examples θ=0°. 
     In some implementations, a baffle or an air louver  1852  (or internal panel or internal wall) is provided to guide the air entering the opening  1850  towards the inlet fan  1848 . An arrow  1854  shows the general direction of airflow from the opening  1850  to the inlet fan  1848 . In some examples, the air louver  1852  extends from the left side panel  1828  of the housing  1840  to a rear edge of the inlet fan  1848 . The air louver  1852  can be straight or curved. In some examples, the air louver  1852  can be configured to guide the inlet air blown from the inlet fan  1848  towards the heat dissipating module  1846 . For example, the air louver  1852  can extend from the left side panel  1828  to the left edge of the heat dissipating module  1846 . For example, the air louver  1852  can extend from the left side panel  1828  to a position at or near the rear of the heat dissipating module  1846 , in which the position can be anywhere from the left rear portion of the heat dissipating module  1846  to the right rear portion of the heat dissipating module  1846 . The air louver  1852  can extend from the bottom panel  1841  to the top panel  1843  in the vertical direction. An arrow  1856  shows the general direction of air flow through and out of the heating dissipating module  1846 . 
     For example, the air louver  1852 , a front portion of the left side panel  1828 , the front panel  1826 , the circuit board  1822 , a front portion of the bottom panel  1841 , and a front portion of the top panel  1843  can form an air duct that guides the incoming cool air to flow across the heat dissipating surface of the heat dissipating module  1846 . Depending on the design, the air duct can extend to the left edge of the heat dissipating module  1846 , to a middle portion of the heat dissipating module  1846 , or extend approximately the entire length (from left to right) of the heat dissipating module  1846 . 
     The inlet fan  1848  and the air louver  1852  are designed to improve airflow across the heat dissipating surface of the heat dissipating module  1846  to optimize or maximize heat dissipation from the data processor  1844  through the heat dissipating module  1846  to the ambient air. Different rackmount servers can have vertically mounted circuit boards with different lengths, can have data processors with different heat dissipation requirements, and can have heat dissipating modules with different designs. For example, the heat sink fins and/or pins can have different configurations. The inlet fan  1848  and the air louver  1852  can also have any of various configurations in order to optimize or maximize the heat dissipation from the data processor  1844 . In the example of  FIG.  96   , the inlet fan  1848  directs air to flow generally in a direction (in this example, from left to right) that is parallel to the front panel across the heat dissipating surface of the heat dissipating module  1846 . In some implementations, the front opening can be positioned to the right side of the front panel, and the inlet fan can be positioned to the right side of the heat dissipating module and direct air to flow from right to left across the heat dissipating surface of the heat dissipating module. The air louver can be modified accordingly to optimize airflow and heat dissipation from the data processor. 
       FIG.  98    is a diagram showing the front portion of the rackmount server  1820 . The baffle or air louver  1852 , a portion of the bottom panel  1841 , a portion of the top panel  1843 , and a portion of the left side panel  1828  form a duct that directs external air toward the inlet fan  1848 . A safety mechanism (not shown in the figure), such as a protective mesh, that allows air to substantially freely pass through while blocking larger objects, such as users&#39; fingers, can be placed across the opening  1850 . 
     In some examples, orienting the inlet fan to face towards the side direction instead of the front direction (as in the examples shown in  FIGS.  69 A and  71 A ) can improve the safety and comfort of users operating the rackmount server  1820 . In some examples, orienting the inlet fan towards the side direction instead of the front direction can avoid the presence of a region in the heat dissipating module having little to no air flow. In the example of  FIG.  71 A , the left and right inlet fans blow air toward the left and right side regions, respectively, of the heat dissipating device  1072 . The incoming air is drawn toward the rear of the heat dissipating module due to the air pressure gradient generated by the front and rear inlet fans. In some cases, the incoming air entering the left side of the heat dissipating device  1072  is drawn toward the rear of the heat dissipating device  1072  before reaching the middle part of the heat dissipating device  1072 . Similarly, the incoming air entering the right side of the heat dissipating device  1072  is drawn toward the rear of the heat dissipating device  1072  before reaching the middle part of the heat dissipating device  1072 . As a result, near the middle or middle-front region of the heat dissipating device  1072  there may be a region having little to no air flow, reducing the efficiency of heat dissipation. The design shown in  FIGS.  96  to  98    avoids or reduces this problem. 
     The front panel  1826  includes openings or interface ports  1860  that allow the rackmount server  1820  to be coupled to optical fiber cables and/or electrical cables. In some implementations, co-packaged optical modules  1870  can be inserted into the interface ports  1860 , in which the co-packaged optical modules  1870  function as optical/electrical communication interfaces for the data processor  1844 . The co-packaged optical modules have been described earlier in this document. 
       FIG.  99    includes an upper diagram  1880  that shows a perspective front view of an example of the front panel  1826 , and a lower diagram  1882  that shows a perspective rear view of the front panel  1826 . The lower diagram  1882  shows the data processor  1844  mounted to the back side of the vertically oriented circuit board  1822 . The front panel  1826  includes openings or interface ports  1860  that allow insertion of communication interface modules, such as co-packaged optical modules, that provide interfaces between the data processor  1844  and external optical or electrical cables. The optical and electrical signal paths between the data processor  1844  and the co-packaged optical modules have been previously described in this document. 
       FIG.  100    is a diagram of a top view of an example of a rackmount server  1890  that includes a vertically oriented circuit board  1822  positioned at a front portion of the rackmount server  1890 . A data processor  1844  is mounted on the circuit board  1822 , and a heat dissipating module  1846  is thermally coupled to the data processor  1844 . The rackmount server  1890  has an active airflow management system that is configured to remove heat from the data processor  1844  during operation. The rackmount server  1890  includes components that are similar to those of the rackmount server  1820  ( FIG.  96   ) and are not otherwise described here. 
     In some implementations, the active airflow management system includes an inlet fan  1894  that is positioned at a left side of the heat dissipating module  1846  and oriented to blow inlet air to the right toward the heat dissipating module  1846 . A front opening  1850  allows incoming air to pass to the inlet fan  1894 . The front opening  1850  can be positioned to the left of the inlet fan  1894 . For example, the inlet fan  1894  can have a rotational axis that is at an angle θ relative to the front panel  1826 , in which θ≤45°. In some examples, θ≤25°. In some examples, θ≤5°. In some examples, the circuit board  1822  is substantially parallel to the front panel  1826 , and the rotational axis of the inlet fan  1894  is substantially parallel to the circuit board  1822 . An inlet fan  1894 , 
     In some implementations, a first baffle or air louver  1892  is provided to guide air from the opening  1850  towards the inlet fan  1894 , and from the inlet fan  1894  towards the heat dissipating module  1846 . A second baffle or air louver  1908  is provided to guide air from the right portion of the heat dissipating module  1846  toward the rear of the rackmount server  1890 . The first and second air louvers  1892 ,  1894  can extend from the bottom panel to the top panel in the vertical direction. 
     An arrow  1902  shows a general direction of airflow from the opening  1850  to the inlet fan  1894 . An arrow  1904  shows a general direction of airflow from the inlet fan  1894  to, and through, a center portion the heat dissipating module  1846 . An arrow  1906  shows a general direction of airflow through, and exiting, the right portion of the heat dissipating module  1846 . The first air louver  1892 , a front portion of the left panel, a front portion of the top panel, a front portion of the bottom panel, the front panel  1826 , the circuit board  1822 , and the second air louver  1908  in combination form a duct that channels the air to flow through the entire heat dissipating module  1846 , or a substantial portion of the heat dissipating module  1846 , thereby increasing the efficiency of heat dissipation from the data processor  1844 . 
     In this example, the first air louver  1892  includes a left curved section  1896 , a middle straight section  1898 , and a right curved section  1900 . The left curved section  1896  extends from the left side panel to the inlet fan  1894 . The left curved section  1896  directs incoming air to turn from flowing in the rear direction to flowing in the left-to-right direction. The middle straight section  1898  is positioned to the rear of the heat dissipating module  1846  and extends from the inlet fan  1894  to beyond the center portion of the heat dissipating module  1846 . The middle straight section  1898  directs the air to flow generally in a left-to-right direction through a substantial portion (e.g., more than half) of the heat dissipating module  1846 . The right curved section  1900  and the second air louver  1908  in combination guide the air to turn from flowing in the left-to-right direction to flowing in a rear direction. The designs of the first and second air louvers  1892 ,  1908  are selected to optimize the heat dissipation efficiency. The heat dissipating module  1846  can have a design that is different from what is shown in the figure, and the first and second air louvers  1892 ,  1908  can also be modified accordingly. 
     In the example of  FIG.  100   , the inlet fan  1894  directs air to flow generally in a direction (in this example, from left to right) that is parallel to the front panel  1826  across the heat dissipating surface of the heat dissipating module  1846 . In some implementations, the front opening can be positioned to the left side of the front panel, and the inlet fan can be positioned to the right side of the heat dissipating module and direct air to flow from right to left across the heat dissipating surface of the heat dissipating module. The first and second air louvers can be modified accordingly to optimize airflow and heat dissipation from the data processor. 
       FIGS.  35 A to  37    show examples of optical communications systems  1250 ,  1260 ,  1270  in which in each system an optical power supply or photon supply provides optical power supply light to photonic integrated circuits hosted in multiple communication devices (e.g., optical transponders), and the optical power supply is external to the communication devices. The optical power supply can have its own housing, electrical power supply, and control circuitry, independent of the housings, electrical power supplies, and control circuitry of the communication devices. This allows the optical power supply to be serviced, repaired, or replaced independent of the communication devices. Redundant optical power supplies can be provided so that a defective external optical power supply can be repaired or replaced without taking the communication devices off-line. The external optical power supply can be placed at a convenient centralized location with a dedicated temperature environment (as opposed to being crammed inside the communication devices, which may have a high temperature). The external optical power supply can be built more efficiently than individual power supply units, as certain common parts such as monitoring circuitry and thermal control units can be amortized over many more communication devices. The following describes implementations of the fiber cabling for remote optical power supplies. 
       FIG.  79    is a system functional block diagram of an example of an optical communication system  1280  that includes a first communication transponder  1282  and a second communication transponder  1284 . Each of the first and second communication transponders  1282 ,  1284  can include one or more co-packaged optical modules described above. Each communication transponder can include, e.g., one or more data processors, such as network switches, central processing units, graphics processor units, tensor processing units, digital signal processors, and/or other application specific integrated circuits (ASICs). In this example, the first communication transponder  1282  sends optical signals to, and receives optical signals from, the second communication transponder  1284  through a first optical communication link  1290 . The one or more data processors in each communication transponder  1282 ,  1284  process the data received from the first optical communication link  1290  and outputs processed data to the first optical communication link  1290 . The optical communication system  1280  can be expanded to include additional communication transponders. The optical communication system  1280  can also be expanded to include additional communication between two or more external photon supplies, which can coordinate aspects of the supplied light, such as the respectively emitted wavelengths or the relative timing of the respectively emitted optical pulses. 
     A first external photon supply  1286  provides optical power supply light to the first communication transponder  1282  through a first optical power supply link  1292 , and a second external photon supply  1288  provides optical power supply light to the second communication transponder  1284  through a second optical power supply link  1294 . In one example embodiment, the first external photon supply  1286  and the second external photon supply  1288  provide continuous wave laser light at the same optical wavelength. In another example embodiment, the first external photon supply  1286  and the second external photon supply  1288  provide continuous wave laser light at different optical wavelengths. In yet another example embodiment, the first external photon supply  1286  provides a first sequence of optical frame templates to the first communication transponder  1282 , and the second external photon supply  1288  provides a second sequence of optical frame templates to the second communication transponder  1284 . For example, as described in U.S. patent Ser. No. 16/847,705, each of the optical frame templates can include a respective frame header and a respective frame body, and the frame body includes a respective optical pulse train. The first communication transponder  1282  receives the first sequence of optical frame templates from the first external photon supply  1286 , loads data into the respective frame bodies to convert the first sequence of optical frame templates into a first sequence of loaded optical frames that are transmitted through the first optical communication link  1290  to the second communication transponder  1284 . Similarly, the second communication transponder  1284  receives the second sequence of optical frame templates from the second external photon supply  1288 , loads data into the respective frame bodies to convert the second sequence of optical frame templates into a second sequence of loaded optical frames that are transmitted through the first optical communication link  1290  to the first communication transponder  1282 . 
       FIG.  80 A  is a diagram of an example of an optical communication system  1300  that includes a first switch box  1302  and a second switch box  1304 . Each of the switch boxes  1302 ,  1304  can include one or more data processors, such as network switches. The first and second switch boxes  1302 ,  1304  can be separated by a distance greater than, e.g., 1 foot, 3 feet, 10 feet, 100 feet, or 1000 feet. The figure shows a diagram of a front panel  1306  of the first switch box  1302  and a front panel  1308  of the second switch box  1304 . In this example, the first switch box  1302  includes a vertical ASIC mount grid structure  1310 , similar to the grid structure  870  of  FIG.  43   . A co-packaged optical module  1312  is attached to a receptor of the grid structure  1310 . The second switch box  1304  includes a vertical ASIC mount grid structure  1314 , similar to the grid structure  870  of  FIG.  43   . A co-packaged optical module  1316  is attached to a receptor of the grid structure  1314 . The first co-packaged optical module  1312  communicates with the second co-packaged optical module  1316  through an optical fiber bundle  1318  that includes multiple optical fibers. Optional fiber connectors  1320  can be used along the optical fiber bundle  1318 , in which shorter sections of optical fiber bundles are connected by the fiber connectors  1320 . 
     In some implementations, each co-packaged optical module (e.g.,  1312 ,  1316 ) includes a photonic integrated circuit configured to convert input optical signals to input electrical signals that are provided to a data processor, and convert output electrical signals from the data processor to output optical signals. The co-packaged optical module can include an electronic integrated circuit configured to process the input electrical signals from the photonic integrated circuit before the input electrical signals are transmitted to the data processor, and to process the output electrical signals from the data processor before the output electrical signals are transmitted to the photonic integrated circuit. In some implementations, the electronic integrated circuit can include a plurality of serializers/deserializers configured to process the input electrical signals from the photonic integrated circuit, and to process the output electrical signals transmitted to the photonic integrated circuit. The electronic integrated circuit can include a first serializers/deserializers module having multiple serializer units and deserializer units, in which the first serializers/deserializers module is configured to generate a plurality of sets of first parallel electrical signals based on a plurality of first serial electrical signals provided by the photonic integrated circuit, and condition the electrical signals, in which each set of first parallel electrical signals is generated based on a corresponding first serial electrical signal. The electronic integrated circuit can include a second serializers/deserializers module having multiple serializer units and deserializer units, in which the second serializers/deserializers module is configured to generate a plurality of second serial electrical signals based on the plurality of sets of first parallel electrical signals, and each second serial electrical signal is generated based on a corresponding set of first parallel electrical signals. The plurality of second serial electrical signals can be transmitted toward the data processor. 
     The first switch box  1302  includes an external optical power supply  1322  (i.e., external to the co-packaged optical module) that provides optical power supply light through an optical connector array  1324 . In this example, the optical power supply  1322  is located internal of the housing of the switch box  1302 . Optical fibers  1326  are optically coupled to an optical connector  1328  (of the optical connector array  1324 ) and the co-packaged optical module  1312 . The optical power supply  1322  sends optical power supply light through the optical connector  1328  and the optical fibers  1326  to the co-packaged optical module  1312 . For example, the co-packaged optical module  1312  includes a photonic integrated circuit that modulates the power supply light based on data provided by a data processor to generate a modulated optical signal, and transmits the modulated optical signal to the co-packaged optical module  1316  through one of the optical fibers in the fiber bundle  1318 . 
     In some examples, the optical power supply  1322  is configured to provide optical power supply light to the co-packaged optical module  1312  through multiple links that have built-in redundancy in case of malfunction in some of the optical power supply modules. For example, the co-packaged optical module  1312  can be designed to receive N channels of optical power supply light (e.g., N1 continuous wave light signals at the same or at different optical wavelengths, or N1 sequences of optical frame templates), N1 being a positive integer, from the optical power supply  1322 . The optical power supply  1322  provides N1+M1 channels of optical power supply light to the co-packaged optical module  1312 , in which M1 channels of optical power supply light are used for backup in case of failure of one or more of the N1 channels of optical power supply light, M1 being a positive integer. 
     The second switch box  1304  receives optical power supply light from a co-located optical power supply  1330 , which is, e.g., external to the second switch box  1304  and located near the second switch box  1304 , e.g., in the same rack as the second switch box  1304  in a data center. The optical power supply  1330  includes an array of optical connectors  1332 . Optical fibers  1334  are optically coupled to an optical connector  1336  (of the optical connectors  1332 ) and the co-packaged optical module  1316 . The optical power supply  1330  sends optical power supply light through the optical connector  1336  and the optical fibers  1334  to the co-packaged optical module  1316 . For example, the co-packaged optical module  1316  includes a photonic integrated circuit that modulates the power supply light based on data provided by a data processor to generate a modulated optical signal, and transmits the modulated optical signal to the co-packaged optical module  1312  through one of the optical fibers in the fiber bundle  1318 . 
     In some examples, the optical power supply  1330  is configured to provide optical power supply light to the co-packaged optical module  1316  through multiple links that have built-in redundancy in case of malfunction in some of the optical power supply modules. For example, the co-packaged optical module  1316  can be designed to receive N2 channels of optical power supply light (e.g., N2 continuous wave light signals at the same or at different optical wavelengths, or N2 sequences of optical frame templates), N2 being a positive integer, from the optical power supply  1322 . The optical power supply  1322  provides N2+M2 channels of optical power supply light to the co-packaged optical module  1312 , in which M2 channels of optical power supply light are used for backup in case of failure of one or more of the N2 channels of optical power supply light, M2 being a positive integer. 
       FIG.  80 B  is a diagram of an example of an optical cable assembly  1340  that can be used to enable the first co-packaged optical module  1312  to receive optical power supply light from the first optical power supply  1322 , enable the second co-packaged optical module  1316  to receive optical power supply light from the second optical power supply  1330 , and enable the first co-packaged optical module  1312  to communicate with the second co-packaged optical module  1316 .  FIG.  80 C  is an enlarged diagram of the optical cable assembly  1340  without some of the reference numbers to enhance clarity of illustration. 
     The optical cable assembly  1340  includes a first optical fiber connector  1342 , a second optical fiber connector  1344 , a third optical fiber connector  1346 , and a fourth optical fiber connector  1348 . The first optical fiber connector  1342  is designed and configured to be optically coupled to the first co-packaged optical module  1312 . For example, the first optical fiber connector  1342  can be configured to mate with a connector part of the first co-packaged optical module  1312 , or a connector part that is optically coupled to the first co-packaged optical module  1312 . The first, second, third, and fourth optical fiber connectors  1342 ,  1344 ,  1346 ,  1348  can comply with an industry standard that defines the specifications for optical fiber interconnection cables that transmit data and control signals, and optical power supply light. 
     The first optical fiber connector  1342  includes optical power supply (PS) fiber ports, transmitter (TX) fiber ports, and receiver (RX) fiber ports. The optical power supply fiber ports provide optical power supply light to the co-packaged optical module  1312 . The transmitter fiber ports allow the co-packaged optical module  1312  to transmit output optical signals (e.g., data and/or control signals), and the receiver fiber ports allow the co-packaged optical module  1312  to receive input optical signals (e.g., data and/or control signals). Examples of the arrangement of the optical power supply fiber ports, the transmitter ports, and the receiver ports in the first optical fiber connector  1342  are shown in  FIGS.  80 D,  89 , and  90   . 
       FIG.  80 D  shows an enlarged upper portion of the diagram of  FIG.  80 B , with the addition of an example of a mapping of fiber ports  1750  of the first optical fiber connector  1342  and a mapping of fiber ports  1752  of the third optical fiber connector  1346 . The mapping of fiber ports  1750  shows the positions of the transmitter fiber ports (e.g.,  1753 ), receiver fiber ports (e.g.,  1755 ), and power supply fiber ports (e.g.,  1751 ) of the first optical fiber connector  1342  when viewed in the direction  1754  into the first optical fiber connector  1342 . The mapping of fiber ports  1752  shows the positions of the power supply fiber ports (e.g.,  1757 ) of the third optical fiber connector  1346  when viewed in the direction  1756  into the third optical fiber connector  1346 . 
     The second optical fiber connector  1344  is designed and configured to be optically coupled to the second co-packaged optical module  1316 . The second optical fiber connector  1344  includes optical power supply fiber ports, transmitter fiber ports, and receiver fiber ports. The optical power supply fiber ports provide optical power supply light to the co-packaged optical module  1316 . The transmitter fiber ports allow the co-packaged optical module  1316  to transmit output optical signals, and the receiver fiber ports allow the co-packaged optical module  1316  to receive input optical signals. Examples of the arrangement of the optical power supply fiber ports, the transmitter ports, and the receiver ports in the second optical fiber connector  1344  are shown in  FIGS.  80 E,  89 , and  90   . 
       FIG.  80 E  shows an enlarged lower portion of the diagram of  FIG.  80 B , with the addition of an example of a mapping of fiber ports  1760  of the second optical fiber connector  1344  and a mapping of fiber ports  1762  of the fourth optical fiber connector  1348 . The mapping of fiber ports  1760  shows the positions of the transmitter fiber ports (e.g.,  1763 ), receiver fiber ports (e.g.,  1765 ), and power supply fiber ports (e.g.,  1761 ) of the second optical fiber connector  1344  when viewed in the direction  1764  into the second optical fiber connector  1344 . The mapping of fiber ports  1762  shows the positions of the power supply fiber ports (e.g.,  1767 ) of the fourth optical fiber connector  1348  when viewed in the direction  1766  into the fourth fiber connector  1348 . 
     The third optical connector  1346  is designed and configured to be optically coupled to the power supply  1322 . The third optical connector  1346  includes optical power supply fiber ports (e.g.,  1757 ) through which the power supply  1322  can output the optical power supply light. The fourth optical connector  1348  is designed and configured to be optically coupled to the power supply  1330 . The fourth optical connector  1348  includes optical power supply fiber ports (e.g.,  1762 ) through which the power supply  1322  can output the optical power supply light. 
     In some implementations, the optical power supply fiber ports, the transmitter fiber ports, and the receiver fiber ports in the first and second optical fiber connectors  1342 ,  1344  are designed to be independent of the communication devices, i.e., the first optical fiber connector  1342  can be optically coupled to the second switch box  1304 , and the second optical fiber connector  1344  can be optically coupled to the first switch box  1302  without any re-mapping of the fiber ports. Similarly, the optical power supply fiber ports in the third and fourth optical fiber connectors  1346 ,  1348  are designed to be independent of the optical power supplies, i.e., if the first optical fiber connector  1342  is optically coupled to the second switch box  1304 , the third optical fiber connector  1346  can be optically coupled to the second optical power supply  1330 . If the second optical fiber connector  1344  is optically coupled to the first switch box  1302 , the fourth optical fiber connector  1348  can be optically coupled to the first optical power supply  1322 . 
     The optical cable assembly  1340  includes a first optical fiber guide module  1350  and a second optical fiber guide module  1352 . The optical fiber guide module depending on context is also referred to as an optical fiber coupler or splitter because the optical fiber guide module combines multiple bundles of fibers into one bundle of fibers, or separates one bundle of fibers into multiple bundles of fibers. The first optical fiber guide module  1350  includes a first port  1354 , a second port  1356 , and a third port  1358 . The second optical fiber guide module  1352  includes a first port  1360 , a second port  1362 , and a third port  1364 . The fiber bundle  1318  extends from the first optical fiber connector  1342  to the second optical fiber connector  1344  through the first port  1354  and the second port  1356  of the first optical fiber guide module  1350  and the second port  1362  and the first port  1360  of the second optical fiber guide module  1352 . The optical fibers  1326  extend from the third optical fiber connector  1346  to the first optical fiber connector  1342  through the third port  1358  and the first port  1354  of the first optical fiber guide module  1350 . The optical fibers  1334  extend from the fourth optical fiber connector  1348  to the second optical fiber connector  1344  through the third port  1364  and the first port  1360  of the second optical fiber guide module  1352 . 
     A portion (or section) of the optical fibers  1318  and a portion of the optical fibers  1326  extend from the first port  1354  of the first optical fiber guide module  1350  to the first optical fiber connector  1342 . A portion of the optical fibers  1318  extend from the second port  1356  of the first optical fiber guide module  1350  to the second port  1362  of the second optical fiber guide module  1352 , with optional optical connectors (e.g.,  1320 ) along the paths of the optical fibers  1318 . A portion of the optical fibers  1326  extend from the third port  1358  of the first optical fiber connector  1350  to the third optical fiber connector  1346 . A portion of the optical fibers  1334  extend from the third port  1364  of the second optical fiber connector  1352  to the fourth optical fiber connector  1348 . 
     The first optical fiber guide module  1350  is designed to restrict bending of the optical fibers such that the bending radius of any optical fiber in the first optical fiber guide module  1350  is greater than the minimum bending radius specified by the optical fiber manufacturer to avoid excess optical light loss or damage to the optical fiber. For example, the minimum bend radii can be 2 cm, 1 cm, 5 mm, or 2.5 mm. Other bend radii are also possible. For example, the fibers  1318  and the fibers  1326  extend outward from the first port  1354  along a first direction, the fibers  1318  extend outward from the second port  1356  along a second direction, and the fibers  1326  extend outward from the third port  1358  along a third direction. A first angle is between the first and second directions, a second angle is between the first and third directions, and a third angle is between the second and third directions. The first optical fiber guide module  1350  can be designed to limit the bending of optical fibers so that each of the first, second, and third angles is in a range from, e.g., 30° to 180°. 
     For example, the portion of the optical fibers  1318  and the portion of the optical fibers  1326  between the first optical fiber connector  1342  and the first port  1354  of the first optical fiber guide module  1350  can be surrounded and protected by a first common sheath  1366 . The optical fibers  1318  between the second port  1356  of the first optical fiber guide module  1350  and the second port  1362  of the second optical fiber guide module  1352  can be surrounded and protected by a second common sheath  1368 . The portion of the optical fibers  1318  and the portion of the optical fibers  1334  between the second optical fiber connector  1344  and the first port  1360  of the second optical fiber guide module  1352  can be surrounded and protected by a third common sheath  1369 . The optical fibers  1326  between the third optical fiber connector  1346  and the third port  1358  of the first optical fiber guide module  1350  can be surrounded and protected by a fourth common sheath  1367 . The optical fibers  1334  between the fourth optical fiber connector  1348  and the third port  1364  of the second optical fiber guide module  1352  can be surrounded and protected by a fifth common sheath  1370 . Each of the common sheaths can be laterally flexible and/or laterally stretchable, as described in, e.g., U.S. patent application Ser. No. 16/822,103. 
     One or more optical cable assemblies  1340  ( FIGS.  80 B,  80 C ) and other optical cable assemblies (e.g.,  1400  of  FIG.  82 B,  82 C,  1490    of  FIG.  84 B,  84 C ) described in this document can be used to optically connect switch boxes that are configured differently compared to the switch boxes  1302 ,  1304  shown in  FIG.  80 A , in which the switch boxes receive optical power supply light from one or more external optical power supplies. For example, in some implementations, the optical cable assembly  1340  can be attached to a fiber-optic array connector mounted on the outside of the front panel of an optical switch, and another fiber-optic cable then connects the inside of the fiber connector to a co-packaged optical module that is mounted on a circuit board positioned inside the housing of the switch box. The co-packaged optical module (which includes, e.g., a photonic integrated circuit, optical-to-electrical converters, such as photodetectors, and electrical-to-optical converters, such as laser diodes) can be co-packaged with a switch ASIC and mounted on a circuit board that can be vertically or horizontally oriented. For example, in some implementations, the front panel is mounted on hinges and a vertical ASIC mount is recessed behind it. See the examples in  FIGS.  77 A,  77 B, and  78   . The optical cable assembly  1340  provides optical paths for communication between the switch boxes, and optical paths for transmitting power supply light from one or more external optical power supplies to the switch boxes. The switch boxes can have any of a variety of configurations regarding how the power supply light and the data and/or control signals from the optical fiber connectors are transmitted to or received from the photonic integrated circuits, and how the signals are transmitted between the photonic integrated circuits and the data processors. 
     One or more optical cable assemblies  1340  and other optical cable assemblies (e.g.,  1400  of  FIG.  82 B,  82 C,  1490    of  FIG.  84 B,  84 C ) described in this document can be used to optically connect computing devices other than switch boxes. For example, the computing devices can be server computers that provide a variety of services, such as cloud computing, database processing, audio/video hosting and streaming, electronic mail, data storage, web hosting, social network, supercomputing, scientific research computing, healthcare data processing, financial transaction processing, logistics management, weather forecast, or simulation, to list a few examples. The optical power light required by the optoelectronic modules of the computing devices can be provided using one or more external optical power supplies. For example, in some implementations, one or more external optical power supplies that are centrally managed can be configured to provide the optical power supply light for hundreds or thousands of server computers in a data center, and the one or more optical power supplies and the server computers can be optically connected using the optical cable assemblies (e.g.,  1340 ,  1400 ,  1490 ) described in this document and variations of the optical cable assemblies using the principles described in this document. 
       FIG.  81    is a system functional block diagram of an example of an optical communication system  1380  that includes a first communication transponder  1282  and a second communication transponder  1284 , similar to those in  FIG.  79   . The first communication transponder  1282  sends optical signals to, and receives optical signals from, the second communication transponder  1284  through a first optical communication link  1290 . The optical communication system  1380  can be expanded to include additional communication transponders. 
     An external photon supply  1382  provides optical power supply light to the first communication transponder  1282  through a first optical power supply link  1384 , and provides optical power supply light to the second communication transponder  1284  through a second optical power supply link  1386 . In one example, the external photon supply  1282  provides continuous wave light to the first communication transponder  1282  and to the second communication transponder  1284 . In one example, the continuous wave light can be at the same optical wavelength. In another example, the continuous wave light can be at different optical wavelengths. In yet another example, the external photon supply  1282  provides a first sequence of optical frame templates to the first communication transponder  1282 , and provides a second sequence of optical frame templates to the second communication transponder  1284 . Each of the optical frame templates can include a respective frame header and a respective frame body, and the frame body includes a respective optical pulse train. The first communication transponder  1282  receives the first sequence of optical frame templates from the external photon supply  1382 , loads data into the respective frame bodies to convert the first sequence of optical frame templates into a first sequence of loaded optical frames that are transmitted through the first optical communication link  1290  to the second communication transponder  1284 . Similarly, the second communication transponder  1284  receives the second sequence of optical frame templates from the external photon supply  1382 , loads data into the respective frame bodies to convert the second sequence of optical frame templates into a second sequence of loaded optical frames that are transmitted through the first optical communication link  1290  to the first communication transponder  1282 . 
       FIG.  82 A  is a diagram of an example of an optical communication system  1390  that includes a first switch box  1302  and a second switch box  1304 , similar to those in  FIG.  80 A . The first switch box  1302  includes a vertical ASIC mount grid structure  1310 , and a co-packaged optical module  1312  is attached to a receptor of the grid structure  1310 . The second switch box  1304  includes a vertical ASIC mount grid structure  1314 , and a co-packaged optical module  1316  is attached to a receptor of the grid structure  1314 . The first co-packaged optical module  1312  communicates with the second co-packaged optical module  1316  through an optical fiber bundle  1318  that includes multiple optical fibers. 
     As discussed above in connection with  FIGS.  80 A to  80 E , the first and second switch boxes  1302 ,  1304  can have other configurations. For example, horizontally mounted ASICs can be used. A fiber-optic array connector attached to a front panel can be used to optically connect the optical cable assembly  1340  to another fiber-optic cable that connects to a co-packaged optical module mounted on a circuit board inside the switch box. The front panel can be mounted on hinges and a vertical ASIC mount can be recessed behind it. The switch boxes can be replaced by other types of server computers. 
     In an example embodiment, the first switch box  1302  includes an external optical power supply  1322  that provides optical power supply light to both the co-packaged optical module  1312  in the first switch box  1302  and the co-packaged optical module  1316  in the second switch box  1304 . In another example embodiment, the optical power supply can be located outside the switch box  1302  (cf.  1330 ,  FIG.  80 A ). The optical power supply  1322  provides the optical power supply light through an optical connector array  1324 . Optical fibers  1392  are optically coupled to an optical connector  1396  and the co-packaged optical module  1312 . The optical power supply  1322  sends optical power supply light through the optical connector  1396  and the optical fibers  1392  to the co-packaged optical module  1312  in the first switch box  1302 . Optical fibers  1394  are optically coupled to the optical connector  1396  and the co-packaged optical module  1316 . The optical power supply  1322  sends optical power supply light through the optical connector  1396  and the optical fibers  1394  to the co-packaged optical module  1316  in the second switch box  1304 . 
       FIG.  82 B  shows an example of an optical cable assembly  1400  that can be used to enable the first co-packaged optical module  1312  to receive optical power supply light from the optical power supply  1322 , enable the second co-packaged optical module  1316  to receive optical power supply light from the optical power supply  1322 , and enable the first co-packaged optical module  1312  to communicate with the second co-packaged optical module  1316 .  FIG.  82 C  is an enlarged diagram of the optical cable assembly  1400  without some of the reference numbers to enhance clarity of illustration. 
     The optical cable assembly  1400  includes a first optical fiber connector  1402 , a second optical fiber connector  1404 , and a third optical fiber connector  1406 . The first optical fiber connector  1402  is similar to the first optical fiber connector  1342  of  FIGS.  80 B,  80 C,  80 D , and is designed and configured to be optically coupled to the first co-packaged optical module  1312 . The second optical fiber connector  1404  is similar to the second optical fiber connector  1344  of  FIGS.  80 B,  80 C,  80 E , and is designed and configured to be optically coupled to the second co-packaged optical module  1316 . The third optical connector  1406  is designed and configured to be optically coupled to the power supply  1322 . The third optical connector  1406  includes first optical power supply fiber ports (e.g.,  1770 ,  FIG.  82 D ) and second optical power supply fiber ports (e.g.,  1772 ). The power supply  1322  outputs optical power supply light through the first optical power supply fiber ports to the optical fibers  1392 , and outputs optical power supply light through the second optical power supply fiber ports to the optical fibers  1394 . The first, second, and third optical fiber connectors  1402 ,  1404 ,  1406  can comply with an industry standard that defines the specifications for optical fiber interconnection cables that transmit data and control signals, and optical power supply light. 
       FIG.  82 D  shows an enlarged upper portion of the diagram of  FIG.  82 B , with the addition of an example of a mapping of fiber ports  1774  of the first optical fiber connector  1402  and a mapping of fiber ports  1776  of the third optical fiber connector  1406 . The mapping of fiber ports  1774  shows the positions of the transmitter fiber ports (e.g.,  1778 ), receiver fiber ports (e.g.,  1780 ), and power supply fiber ports (e.g.,  1782 ) of the first optical fiber connector  1402  when viewed in the direction  1784  into the first optical fiber connector  1402 . The mapping of fiber ports  1776  shows the positions of the power supply fiber ports (e.g.,  1770 ,  1772 ) of the third optical fiber connector  1406  when viewed in the direction  1786  into the third optical fiber connector  1406 . In this example, the third optical fiber connector  1406  includes 8 optical power supply fiber ports. 
     In some examples, optical connector array  1324  of the optical power supply  1322  can include a first type of optical connectors that accept optical fiber connectors having 4 optical power supply fiber ports, as in the example of  FIG.  80 D , and a second type of optical connectors that accept optical fiber connectors having 8 optical power supply fiber ports, as in the example of  FIG.  82 D . In some examples, if the optical connector array  1324  of the optical power supply  1322  only accepts optical fiber connectors having 4 optical power supply fiber ports, then a converter cable can be used to convert the third optical fiber connector  1406  of  FIG.  82 D  to two optical fiber connectors, each having 4 optical power supply fiber ports, that is compatible with the optical connector array  1324 . 
       FIG.  82 E  shows an enlarged lower portion of the diagram of  FIG.  82 B , with the addition of an example of a mapping of fiber ports  1790  of the second optical fiber connector  1404 . The mapping of fiber ports  1790  shows the positions of the transmitter fiber ports (e.g.,  1792 ), receiver fiber ports (e.g.,  1794 ), and power supply fiber ports (e.g.,  1796 ) of the second optical fiber connector  1404  when viewed in the direction  1798  into the second optical fiber connector  1404 . 
     The port mappings of the optical fiber connectors shown in  FIGS.  80 D,  80 E,  82 D, and  82 E  are merely examples. Each optical fiber connector can include a greater number or a smaller number of transmitter fiber ports, a greater number or a smaller number of receiver fiber ports, and a greater number or a smaller number of optical power supply fiber ports, as compared to those shown in  FIGS.  80 D,  80 E,  82 D, and  82 E . The arrangement of the relative positions of the transmitter, receiver, and optical power supply fiber ports can also be different from those shown in  FIGS.  80 D,  80 E,  82 D, and  82 E . 
     The optical cable assembly  1400  includes an optical fiber guide module  1408 , which includes a first port  1410 , a second port  1412 , and a third port  1414 . The optical fiber guide module  1408  depending on context is also referred as an optical fiber coupler (for combining multiple bundles of optical fibers into one bundle of optical fiber) or an optical fiber splitter (for separating a bundle of optical fibers into multiple bundles of optical fibers). The fiber bundle  1318  extends from the first optical fiber connector  1402  to the second optical fiber connector  1404  through the first port  1410  and the second port  1412  of the optical fiber guide module  1408 . The optical fibers  1392  extend from the third optical fiber connector  1406  to the first optical fiber connector  1402  through the third port  1414  and the first port  1410  of the optical fiber guide module  1408 . The optical fibers  1394  extend from the third optical fiber connector  1406  to the second optical fiber connector  1404  through the third port  1414  and the second port  1412  of the optical fiber guide module  1408 . 
     A portion of the optical fibers  1318  and a portion of the optical fibers  1392  extend from the first port  1410  of the optical fiber guide module  1408  to the first optical fiber connector  1402 . A portion of the optical fibers  1318  and a portion of the optical fibers  1394  extend from the second port  1412  of the optical fiber guide module  1408  to the second optical fiber connector  1404 . A portion of the optical fibers  1394  extend from the third port  1414  of the optical fiber connector  1408  to the third optical fiber connector  1406 . 
     The optical fiber guide module  1408  is designed to restrict bending of the optical fibers such that the radius of curvature of any optical fiber in the optical fiber guide module  1408  is greater than the minimum radius of curvature specified by the optical fiber manufacturer to avoid excess optical light loss or damage to the optical fiber. For example, the optical fibers  1318  and the optical fibers  1392  extend outward from the first port  1410  along a first direction, the optical fibers  1318  and the optical fibers  1394  extend outward from the second port  1412  along a second direction, and the optical fibers  1392  and the optical fibers  1394  extend outward from the third port  1414  along a third direction. A first angle is between the first and second directions, a second angle is between the first and third directions, and a third angle is between the second and third directions. The optical fiber guide module  1408  is designed to limit the bending of optical fibers so that each of the first, second, and third angles is in a range from, e.g., 30° to 180°. 
     For example, the portion of the optical fibers  1318  and the portion of the optical fibers  1392  between the first optical fiber connector  1402  and the first port  1410  of the optical fiber guide module  1408  can be surrounded and protected by a first common sheath  1416 . The optical fibers  1318  and the optical fibers  1394  between the second optical fiber connector  1404  and the second port  1412  of the optical fiber guide module  1408  can be surrounded and protected by a second common sheath  1418 . The optical fibers  1392  and the optical fibers  1394  between the third optical fiber connector  1406  and the third port  1414  of the optical fiber guide module  1408  can be surrounded and protected by a third common sheath  1420 . Each of the common sheaths can be laterally flexible and/or laterally stretchable. 
       FIG.  83    is a system functional block diagram of an example of an optical communication system  1430  that includes a first communication transponder  1432 , a second communication transponder  1434 , a third communication transponder  1436 , and a fourth communication transponder  1438 . Each of the communication transponders  1432 ,  1434 ,  1436 ,  1438  can be similar to the communication transponders  1282 ,  1284  of  FIG.  79   . The first communication transponder  1432  communicates with the second communication transponder  1434  through a first optical link  1440 . The first communication transponder  1432  communicates with the third communication transponder  1436  through a second optical link  1442 . The first communication transponder  1432  communicates with the fourth communication transponder  1438  through a third optical link  1444 . 
     An external photon supply  1446  provides optical power supply light to the first communication transponder  1432  through a first optical power supply link  1448 , provides optical power supply light to the second communication transponder  1434  through a second optical power supply link  1450 , provides optical power supply light to the third communication transponder  1436  through a third optical power supply link  1452 , and provides optical power supply light to the fourth communication transponder  1438  through a fourth optical power supply link  1454 . 
       FIG.  84 A  is a diagram of an example of an optical communication system  1460  that includes a first switch box  1462  and a remote server array  1470  that includes a second switch box  1464 , a third switch box  1466 , and a fourth switch box  1468 . The first switch box  1462  includes a vertical ASIC mount grid structure  1310 , and a co-packaged optical module  1312  is attached to a receptor of the grid structure  1310 . The second switch box  1464  includes a co-packaged optical module  1472 , the third switch box  1466  includes a co-packaged optical module  1474 , and the third switch box  1468  includes a co-packaged optical module  1476 . The first co-packaged optical module  1312  communicates with the co-packaged optical modules  1472 ,  1474 ,  1476  through an optical fiber bundle  1478  that later branches out to the co-packaged optical modules  1472 ,  1474 ,  1476 . 
     In one example embodiment, the first switch box  1462  includes an external optical power supply  1322  that provides optical power supply light through an optical connector array  1324 . In another example embodiment, the optical power supply can be located external to switch box  1462  (cf.  1330 ,  FIG.  80 A ). Optical fibers  1480  are optically coupled to an optical connector  1482 , and the optical power supply  1322  sends optical power supply light through the optical connector  1482  and the optical fibers  1480  to the co-packaged optical modules  1312 ,  1472 ,  1474 ,  1476 . 
       FIG.  84 B  shows an example of an optical cable assembly  1490  that can be used to enable the optical power supply  1322  to provide optical power supply light to the co-packaged optical modules  1312 ,  1472 ,  1474 ,  1476 , and enable the co-packaged optical module  1312  to communicate with the co-packaged optical modules  1472 ,  1474 ,  1476 . The optical cable assembly  1490  includes a first optical fiber connector  1492 , a second optical fiber connector  1494 , a third optical fiber connector  1496 , a fourth optical fiber connector  1498 , and a fifth optical fiber connector  1500 . The first optical fiber connector  1492  is configured to be optically coupled to the co-packaged optical module  1312 . The second optical fiber connector  1494  is configured to be optically coupled to the co-packaged optical module  1472 . The third optical fiber connector  1496  is configured to be optically coupled to the co-packaged optical module  1474 . The fourth optical fiber connector  1498  is configured to be optically coupled to the co-packaged optical module  1476 . The fifth optical fiber connector  1500  is configured to be optically coupled to the optical power supply  1322 .  FIG.  84 C  is an enlarged diagram of the optical cable assembly  1490 . 
     Optical fibers that are optically coupled to the optical fiber connectors  1500  and  1492  enable the optical power supply  1322  to provide the optical power supply light to the co-packaged optical module  1312 . Optical fibers that are optically coupled to the optical fiber connectors  1500  and  1494  enable the optical power supply  1322  to provide the optical power supply light to the co-packaged optical module  1472 . Optical fibers that are optically coupled to the optical fiber connectors  1500  and  1496  enable the optical power supply  1322  to provide the optical power supply light to the co-packaged optical module  1474 . Optical fibers that are optically coupled to the optical fiber connectors  1500  and  1498  enable the optical power supply  1322  to provide the optical power supply light to the co-packaged optical module  1476 . 
     Optical fiber guide modules  1502 ,  1504 ,  1506 , and common sheaths are provided to organize the optical fibers so that they can be easily deployed and managed. The optical fiber guide module  1502  is similar to the optical fiber guide module  1408  of  FIG.  82 B . The optical fiber guide modules  1504 ,  1506  are similar to the optical fiber guide module  1350  of  FIG.  80 B . The common sheaths gather the optical fibers in a bundle so that they can be more easily handled, and the optical fiber guide modules guide the optical fibers so that they extend in various directions toward the devices that need to be optically coupled by the optical cable assembly  1490 . The optical fiber guide modules restrict bending of the optical fibers such that the bending radiuses are greater than minimum values specified by the optical fiber manufacturers to prevent excess optical light loss or damage to the optical fibers. 
     The optical fibers  1480  that extend from the include optical fibers that extend from the optical  1482  are surrounded and protected by a common sheath  1508 . At the optical fiber guide module  1502 , the optical fibers  1480  separate into a first group of optical fibers  1510  and a second group of optical fibers  1512 . The first group of optical fibers  1510  extend to the first optical fiber connector  1492 . The second group of optical fibers  1512  extend toward the optical fiber guide modules  1504 ,  1506 , which together function as a 1:3 splitter that separates the optical fibers  1512  into a third group of optical fibers  1514 , a fourth group of optical fibers  1516 , and a fifth group of optical fibers  1518 . The group of optical fibers  1514  extend to the optical fiber connector  1494 , the group of optical fibers  1516  extend to the optical fiber connector  1496 , and the group of optical fibers  1518  extend to the optical fiber connector  1498 . In some examples, instead of using two 1:2 split optical fiber guide modules  1504 ,  1506 , it is also possible to use a 1:3 split optical fiber guide module that has four ports, e.g., one input port and three output ports. In general, separating the optical fibers in a 1:N split (N being an integer greater than 2) can occur in one step or multiple steps. 
       FIG.  85    is a diagram of an example of a data processing system (e.g., data center)  1520  that includes N servers  1522  spread across K racks  1524 . In this example, there are 6 racks  1524 , and each rack  1524  includes 15 servers  1522 . Each server  1522  directly communicates with a tier 1 switch  1526 . The left portion of the figure shows an enlarged view of a portion  1528  of the system  1520 . A server  1522   a  directly communicates with a tier 1 switch  1526   a  through a communication link  1530   a . Similarly, servers  1522   b ,  1522   c  directly communicate with the tier 1 switch  1526   a  through communication links  1530   b ,  1530   c , respectively. The server  1522   a  directly communicates with a tier 1 switch  1526   b  through a communication link  1532   a . Similarly, servers  1522   b ,  1522   c  directly communicate with the tier 1 switch  1526   b  through communication links  1532   b ,  1532   c , respectively. Each communication link can include a pair of optical fibers to allow bi-directional communication. The system  1520  bypasses the conventional top-of-rack switch and can have the advantage of higher data throughput. The system  1520  includes a point-to-point connection between every server  1522  and every tier 1 switch  1526 . In this example, there are 4 tier 1 switches  1526 , and 4 fiber pairs are used per server  1522  for communicating with the tier 1 switches  1526 . Each tier-1 switch  1526  is connected to N servers, so there are N fiber pairs connected to each tier-1 switch  1526 . 
     Referring to  FIG.  86   , in some implementations, a data processing system (e.g., data center)  1540  includes tier-1 switches  1526  that are co-located in a rack  1540  separate from the N servers  1522  that are spread across K racks  1524 . Each server  1522  has a direct link to each of the tier-1 switches  1526 . In some implementations, there is one fiber cable  1542  (or a small number &lt;&lt;N/K of fiber cables) from the tier-1 switch rack  1540  to each of the K server racks  1524 . 
       FIG.  87 A  is a diagram of an example of a data processing system  1550  that includes N=1024 servers  1552  spread across K=32 racks  1554 , in which each rack  1554  includes N/K=1024/32=32 servers  1552 . There are 4 tier-1 switches  1556  and an optical power supply  1558  that is co-located in a rack  1560 . 
     Optical fibers connect the servers  1552  to the tier-1 switches  1556  and the optical power supply  1558 . In this example, a bundle of 9 optical fibers is optically coupled to a co-packaged optical module  1564  of a server  1552 , in which 1 optical fiber provides the optical power supply light, and 4 pairs of (a total of 8) optical fibers provide 4 bi-directional communication channels, each channel having a 100 Gbps bandwidth, for a total of 4×100 Gbps bandwidth in each direction. Because there are 32 servers  1552  in each rack  1554 , there are a total of 256+32=288 optical fibers that extend from each rack  1554  of servers  1552 , in which 32 optical fibers provide the optical power supply light, and 256 optical fibers provide 128 bi-directional communication channels, each channel having a 100 Gbps bandwidth. 
     For example, at the server rack side, optical fibers  1566  (that are connected to the servers  1552  of a rack  1554 ) terminate at a server rack connector  1568 . At the switch rack side, optical fibers  1578  (that are connected to the switch boxes  1556  and the optical power supply  1558 ) terminate at a switch rack connector  1576 . An optical fiber extension cable  1572  is optically coupled to the server rack side and the switch rack side. The optical fiber extension cable  1572  includes 256+32=288 optical fibers. The optical fiber extension cable  1572  includes a first optical fiber connector  1570  and a second optical fiber connector  1574 . The first optical fiber connector  1570  is connected to the server rack connector  1568 , and the second optical fiber connector  1574  is connected to the switch rack connector  1576 . At the switch rack side, the optical fibers  1578  include 288 optical fibers, of which 32 optical fibers  1580  are optically coupled to the optical power supply  1558 . The 256 optical fibers that carry 128 bi-directional communication channels (each channel having a 100 Gbps bandwidth in each direction) are separated into four groups of 64 optical fibers, in which each group of 64 optical fibers is optically coupled to a co-packaged optical module  1582  in one of the switch boxes  1556 . The co-packaged optical module  1582  is configured to have a bandwidth of 32×100 Gbps=3.2 Tbps in each direction (input and output). Each switch box  1556  is connected to each server  1552  of the rack  1554  through a pair of optical fibers that carry a bandwidth of 100 Gbps in each direction. 
     The optical power supply  1558  provides optical power supply light to co-packaged optical modules  1582  at the switch boxes  1556 . In this example, the optical power supply  1558  provides optical power supply light through 4 optical fibers to each co-packaged optical module  1582 , so that a total of 16 optical fibers are used to provide the optical power supply light to the 4 switch boxes  1556 . A bundle of optical fibers  1584  is optically coupled to the co-packaged optical module  1582  of the switch box  1556 . The bundle of optical fibers  1584  includes 64+16=80 fibers. In some examples, the optical power supply  1558  can provide additional optical power supply light to the co-packaged optical module  1582  using additional optical fibers. For example, the optical power supply  1558  can provide optical power supply light to the co-packaged optical module  1582  using 32 optical fibers with built-in redundancy. 
     Referring to  FIG.  87 B , the data processing system  1550  includes an optical fiber guide module  1590  that helps organize the optical fibers so that they are directed to the appropriate directions. The optical fiber guide module  1590  also restricts bending of the optical fibers to be within the specified limits to prevent excess optical light loss or damage to the optical fibers. The optical fiber guide module  1590  includes a first port  1592 , a second port  1594 , and a third port  1596 . The optical fibers that extend outward from the first port  1592  are optically coupled to the switch rack connector  1576 . The optical fibers that extend outward from the second port  1594  are optically coupled to the switch boxes. The optical fibers that extend outward from the third port  1596  are optically coupled to the optical power supply  1558 . 
       FIG.  88    is a diagram of an example of the connector port mapping for an optical fiber interconnection cable  1600 , which includes a first optical fiber connector  1602 , a second optical fiber connector  1604 , optical fibers  1606  that transmit data and/or control signals between the first and second optical fiber connectors  1602 ,  1604 , and optical fibers  1608  that transmit optical power supply light. Each optical fiber terminates at an optical fiber port  1610 , which can include, e.g., lenses for focusing light entering or exiting the optical fiber port  1610 . The first and second optical fiber connectors  1602 ,  1604  can be, e.g., the optical fiber connectors  1342  and  1344  of  FIGS.  80 B,  80 C , the optical fiber connectors  1402  and  1404  of  FIGS.  82 B,  82 C , or the optical fiber connectors  1570  and  1574  of  FIG.  87 A . The principles for designing the optical fiber interconnection cable  1600  can be used to design the optical cable assembly  1340  of  FIGS.  80 B,  80 C , the optical cable assembly  1400  of  FIGS.  82 B,  82 C , and the optical cable assembly  1490  of  FIGS.  84 B,  84 C . 
     In the example of  FIG.  88   , each optical fiber connector  1602  or  1604  includes 3 rows of optical fiber ports, each row including 12 optical fiber ports. Each optical fiber connector  1602  or  1604  includes 4 power supply fiber ports that are connected to optical fibers  1608  that are optically coupled to one or more optical power supplies. Each optical fiber connector  1602  or  1604  includes 32 fiber ports (some of which are transmitter fiber ports, and some of which are receiver fiber ports) that are connected to the optical fibers  1606  for data transmission and reception. 
     In some implementations, the mapping of the fiber ports of the optical fiber connectors  1602 ,  1604  are designed such that the interconnection cable  1600  can have the most universal use, in which each fiber port of the optical fiber connector  1602  is mapped to a corresponding fiber port of the optical fiber connector  1604  with a 1-to-1 mapping and without transponder-specific port mapping that would require fibers  1606  to cross over. This means that for an optical transponder that has an optical fiber connector compatible with the interconnection cable  1600 , the optical transponder can be connected to either the optical fiber connector  1602  or the optical fiber connector  1604 . The mapping of the fiber ports is designed such that each transmitter port of the optical fiber connector  1602  is mapped to a corresponding receiver port of the optical fiber connector  1604 , and each receiver port of the optical fiber connector  1602  is mapped to a corresponding transmitter port of the optical fiber connector  1604 . 
       FIG.  89    is a diagram showing an example of the fiber port mapping for an optical fiber interconnection cable  1660  that includes a pair of optical fiber connectors, i.e., a first optical fiber connector  1662  and a second optical fiber connector  1664 . The optical fiber connectors  1662  and  1664  are designed such that either the first optical fiber connector  1662  or the second optical fiber connector  1664  can be connected to a given communication transponder that is compatible with the optical fiber interconnection cable  1660 . The diagram shows the fiber port mapping when viewed from the outer edge of the optical fiber connector into the optical fiber connector (i.e., toward the optical fibers in the interconnection cable  1660 ). 
     The first optical fiber connector  1662  includes transmitter fiber ports (e.g.,  1614   a ,  1616   a ), receiver fiber ports (e.g.,  1618   a ,  1620   a ), and optical power supply fiber ports (e.g.,  1622   a ,  1624   a ). The second optical fiber connector  1664  includes transmitter fiber ports (e.g.,  1614   b ,  1616   b ), receiver fiber ports (e.g.,  1618   b ,  1620   b ), and optical power supply fiber ports (e.g.,  1622   b ,  1624   b ). For example, assume that the first optical fiber connector  1662  is connected to a first optical transponder, and the second optical fiber connector  1664  is connected to a second optical transponder. The first optical transponder transmits first data and/or control signals through the transmitter ports (e.g.,  1614   a ,  1616   a ) of the first optical fiber connector  1662 , and the second optical transponder receives the first data and/or control signals from the corresponding receiver fiber ports (e.g.,  1618   b ,  1620   b ) of the second optical fiber connector  1664 . The transmitter ports  1614   a ,  1616   a  are optically coupled to the corresponding receiver fiber ports  1618   b ,  1620   b  through optical fibers  1628 ,  1630 , respectively. The second optical transponder transmits second data and/or control signals through the transmitter ports (e.g.,  1614   b ,  1616   b ) of the second optical fiber connector  1664 , and the first optical transponder receives the second data and/or control signals from the corresponding receiver fiber ports ( 1618   a ,  1620   a ) of the first optical fiber connector  1662 . The transmitter port  1616   b  is optically coupled to the corresponding receiver fiber port  1620   a  through an optical fiber  1632 . 
     A first optical power supply transmits optical power supply light to the first optical transponder through the power supply fiber ports of the first optical fiber connector  1662 . A second optical power supply transmits optical power supply light to the second optical transponder through the power supply fiber ports of the second optical fiber connector  1664 . The first and second power supplies can be different (such as the example of  FIG.  80 B ) or the same (such as the example of  FIG.  82 B ). 
     In the following description, when referring to the rows and columns of fiber ports of the optical fiber connector, the uppermost row is referred to as the 1 st  row, the second uppermost row is referred to as the 2 nd  row, and so forth. The leftmost column is referred to as the 1 st  column, the second leftmost column is referred to as the 2 nd  column, and so forth. 
     For an optical fiber interconnection cable having a pair of optical fiber connectors (i.e., a first optical fiber connector and a second optical fiber connector) to be universal, i.e., either one of the pair of optical fiber connectors can be connected to a given optical transponder, the arrangement of the transmitter fiber ports, the receiver fiber ports, and the power supply fiber ports in the optical fiber connectors have a number of properties. These properties are referred to as the “universal optical fiber interconnection cable port mapping properties.” The term “mapping” here refers to the arrangement of the transmitter fiber ports, the receiver fiber ports, and the power supply fiber ports at particular locations within the optical fiber connector. The first property is that the mapping of the transmitter, receiver, and power supply fiber ports in the first optical fiber connector is the same as the mapping of the transmitter, receiver, and power supply fiber ports in the second optical fiber connector (as in the example of  FIG.  89   ). 
     In the example of  FIG.  89   , the individual optical fibers connecting the transmitter, receiver, and power supply fiber ports in the first optical fiber connector to the transmitter, receiver, and power supply fiber ports in the second optical fiber connector are parallel to one another. 
     In some implementations, each of the optical fiber connectors includes a unique marker or mechanical structure, e.g., a pin, that is configured to be at the same spot on the co-packaged optical module, similar to the use of a “dot” to denote “pin  1 ” on electronic modules. In some examples, such as those shown in  FIGS.  89  and  90   , the larger distance from the bottom row (the third row in the examples of  FIGS.  89  and  90   ) to the connector edge can be used as a “marker” to guide the user to attach the optical fiber connector to the co-packaged optical module connector in a consistent manner. 
     The mapping of the fiber ports of the optical fiber connectors of a “universal optical fiber interconnection cable” has a second property: When mirroring the port map of an optical fiber connector and replacing each transmitter port with a receiver port as well as replacing each receiver port with a transmitter port in the mirror image, the original port mapping is recovered. The mirror image can be generated with respect to a reflection axis at either connector edge, and the reflection axis can be parallel to the row direction or the column direction. The power supply fiber ports of the first optical fiber connector are mirror images of the power supply fiber ports of the second optical fiber connector. 
     The transmitter fiber ports of the first optical fiber connector and the receiver fiber ports of the second optical fiber connector are pairwise mirror images of each other, i.e., each transmitter fiber port of the first optical fiber connector is mirrored to a receiver fiber port of the second optical fiber connector. The receiver fiber ports of the first optical fiber connector and the transmitter fiber ports of the second optical fiber connector are pairwise mirror images of each other, i.e., each receiver fiber port of the first optical fiber connector is mirrored to a transmitter fiber port of the second optical fiber connector. 
     Another way of looking at the second property is as follows: Each optical fiber connector is transmitter port-receiver port (TX-RX) pairwise symmetric and power supply port (PS) symmetric with respect to one of the main or center axes, which can be parallel to the row direction or the column direction. For example, if an optical fiber connector has an even number of columns, the optical fiber connector can be divided along a center axis parallel to the column direction into a left half portion and a right half portion. The power supply fiber ports are symmetric with respect to the main axis, i.e., if there is a power supply fiber port in the left half portion of the optical fiber connector, there will also be a power supply fiber port at the mirror location in the right half portion of the optical fiber connector. The transmitter fiber ports and the receiver fiber ports are pairwise symmetric with respect to the main axis, i.e., if there is a transmitter fiber port in the left half portion of the optical fiber connector, there will be a receiver fiber port at a mirror location in the right half portion of the optical fiber connector. Likewise, if there is a receiver fiber port in the left half portion of the optical fiber connector, there will be a transmitter fiber port at a mirror location in the right half portion of the optical fiber connector. 
     For example, if an optical fiber connector has an even number of rows, the optical fiber connector can be divided along a center axis parallel to the row direction into an upper half portion and a lower half portion. The power supply fiber ports are symmetric with respect to the main axis, i.e., if there is a power supply fiber port in the upper half portion of the optical fiber connector, there will also be a power supply fiber port at the mirror location in the lower half portion of the optical fiber connector. The transmitter fiber ports and the receiver fiber ports are pairwise symmetric with respect to the main axis, i.e., if there is a transmitter fiber port in the upper half portion of the optical fiber connector, there will be a receiver fiber port at a mirror location in the lower half portion of the optical fiber connector. Likewise, if there is a receiver fiber port in the upper half portion of the optical fiber connector, there will be a transmitter fiber port at a mirror location in the lower half portion of the optical fiber connector. 
     The mapping of the transmitter fiber ports, receiver fiber ports, and power supply fiber ports follow a symmetry requirement that can be summarized as follows:
         (i) Mirror all ports on either one of the two connector edges.   (ii) Swap TX (transmitter) and RX (receiver) functionality on the mirror image.   (iii) Leave mirrored PS (power supply) ports as PS ports.   (iv) The resulting port map is the same as the original one.       

     Essentially, a viable port map is TX-RX pairwise symmetric and PS symmetric with respect to one of the main axes. 
     The properties of the mapping of the fiber ports of the optical fiber connectors can be mathematically expressed as follows:
         Port matrix M with entries PS=0, TX=+1, RX=−1;   Column-mirror operation  ;   Row-mirror operation  M;   A viable port map either satisfies − =M or − M=M.       

     In some implementations, if a universal optical fiber interconnection cable has a first optical fiber connector and a second optical fiber connector that are mirror images of each other after swapping the transmitter fiber ports to receiver fiber ports and swapping the receiver fiber ports to transmitter fiber ports in the mirror image, and the mirror image is generated with respect to a reflection axis parallel to the column direction, as in the example of  FIG.  89   , then each optical fiber connector should be TX-RX pairwise symmetric and PS symmetric with respect to a center axis parallel to the column direction. If a universal optical fiber interconnection cable has a first optical fiber connector and a second optical fiber connector that are mirror images of each other after swapping the transmitter and receiver fiber ports in the mirror image, and the mirror image is generated with respect to a reflection axis parallel to the row direction, as in the example of  FIG.  90   , then each optical fiber connector should be TX-RX pairwise symmetric and PS symmetric with respect to a center axis parallel to the row direction. 
     In some implementations, a universal optical fiber interconnection cable:
         a. Comprises n_trx strands of TX/RX fibers and np strands of power supply fibers, in which 0≤n_p≤n_trx.   b. The n_trx strands of TX/RX fibers are mapped 1:1 from a first optical fiber connector to the same port positions on a second optical fiber connector through the optical fiber cable, i.e. the optical fiber cable can be laid out in a straight manner without leading to any cross-over fiber strands.   c. Those connector ports that are not 1:1 connected by TX/RX fibers may be connected to power supply fibers via a break-out cable.       

     In some implementations, a universal optical module connector has the following properties:
         a. Starting from a connector port map PM 0 .   b. First mirror port map PM 0  either across the row dimension or across the column dimension.   c. Mirroring can be done either across a column axis or across a row axis.   d. Replace TX ports by RX ports and vice versa.   e. If at least one mirrored and replaced version of the port map again results in the starting port map PM 0 , the connector is called a universal optical module connector.       

     In  FIG.  89   , the arrangement of the transmitter, receiver, and power supply fiber ports in the first optical fiber connector  1662 , and the arrangement of the transmitter, receiver, and power supply fiber ports in the second optical fiber connector  1664  have the two properties described above. First property: When looking into the optical fiber connector (from the outer edge of the connector inward toward the optical fibers), the mapping of the transmitter, receiver, and power supply fiber ports in the first optical fiber connector  1662  is the same as the mapping of the transmitter, receiver, and power supply fiber ports in the optical fiber connector  1664 . Row 1, column 1 of the optical fiber connector  1662  is a power supply fiber port ( 1622   a ), and row 1, column 1 of the optical fiber connector  1664  is also a power supply fiber port ( 1622   b ). Row 1, column 3 of the optical fiber connector  1662  is a transmitter fiber port ( 1614   a ), and row 1, column 3 of the optical fiber connector  1664  is also a transmitter fiber port ( 1614   b ). Row 1, column 10 of the optical fiber connector  1662  is a receiver fiber port ( 1618   a ), and row 1, column 10 of the optical fiber connector  1664  is also a receiver fiber port ( 1618   b ), and so forth. 
     The optical fiber connectors  1662  and  1664  have the second universal optical fiber interconnection cable port mapping property described above. The port mapping of the optical fiber connector  1662  is a mirror image of the port mapping of the optical fiber connector  1664  after swapping each transmitter port to a receiver port and swapping each receiver port to a transmitter port in the mirror image. The mirror image is generated with respect to a reflection axis  1626  at the connector edge that is parallel to the column direction. The power supply fiber ports (e.g.,  1662   a ,  1624   a ) of the optical fiber connector  1662  are mirror images of the power supply fiber ports (e.g.,  1622   b ,  1624   b ) of the optical fiber connector  1664 . The transmitter fiber ports (e.g.,  1614   a ,  1616   a ) of the optical fiber connector  1662  and the receiver fiber ports (e.g.,  1618   b ,  1620   b ) of the optical fiber connector  1664  are pairwise mirror images of each other, i.e., each transmitter fiber port (e.g.,  1614   a ,  1616   a ) of the optical fiber connector  1662  is mirrored to a receiver fiber port (e.g.,  1618   b ,  1620   b ) of the optical fiber connector  1664 . The receiver fiber ports (e.g.,  1618   a ,  1620   a ) of the optical fiber connector  1662  and the transmitter fiber ports (e.g.,  1618   b ,  1620   b ) of the optical fiber connector  1664  are pairwise mirror images of each other, i.e., each receiver fiber port (e.g.,  1618   a ,  1620   a ) of the optical fiber connector  1662  is mirrored to a transmitter fiber port (e.g.,  1618   b ,  1620   b ) of the optical fiber connector  1664 . 
     For example, the power supply fiber port  1622   a  at row 1, column 1 of the optical fiber connector  1662  is a mirror image of the power supply fiber port  1624   b  at row 1, column 12 of the optical fiber connector  1664  with respect to the reflection axis  1626 . The power supply fiber port  1624   a  at row 1, column 12 of the optical fiber connector  1662  is a mirror image of the power supply fiber port  1622   b  at row 1, column 1 of the optical fiber connector  1664 . The transmitter fiber port  1614   a  at row 1, column 3 of the optical fiber connector  1662  and the receiver fiber port  1618   b  at row 1, column 10 of the optical fiber connector  1604  are pairwise mirror images of each other. The receiver fiber port  1618   a  at row 1, column 10 of the optical fiber connector  1662  and the transmitter fiber port  1614   b  at row 1, column 3 of the optical fiber connector  1664  are pairwise mirror images of each other. The transmitter fiber port  1616   a  at row 3, column 3 of the optical fiber connector  1662  and the receiver fiber port  1620   b  at row 3, column 10 of the optical fiber connector  1664  are pairwise mirror images of each other. The receiver fiber port  1620   a  at row 3, column 10 of the optical fiber connector  1662  and the transmitter fiber port  1616   b  at row 3, column 3 of the optical fiber connector  1664  are pairwise mirror images of each other. 
     In addition, and as an alternate view of the second property, each optical fiber connector  1662 ,  1664  is TX-RX pairwise symmetric and PS symmetric with respect to the center axis that is parallel to the column direction. Using the first optical fiber connector  1662  as an example, the power supply fiber ports (e.g.,  1622   a ,  1624   a ) are symmetric with respect to the center axis, i.e., if there is a power supply fiber port in the left half portion of the first optical fiber connector  1662 , there will also be a power supply fiber port at the mirror location in the right half portion of the first optical fiber connector  1662 . The transmitter fiber ports and the receiver fiber ports are pairwise symmetric with respect to the main axis, i.e., if there is a transmitter fiber port in the left half portion of the first optical fiber connector  1662 , there will be a receiver fiber port at a mirror location in the right half portion of the first optical fiber connector  1662 . Likewise, if there is a receiver fiber port in the left half portion of the optical fiber connector  1662 , there will be a transmitter fiber port at a mirror location in the right half portion of the optical fiber connector  1662 . 
     If the port mapping of the first optical fiber connector  1662  is represented by port matrix M with entries PS=0, TX=+1, RX=−1, then − =M, in which   represents the column-mirror operation, e.g., generating a mirror image with respect to the reflection axis  1626 . 
       FIG.  90    is a diagram showing another example of the fiber port mapping for an optical fiber interconnection cable  1670  that includes a pair of optical fiber connectors, i.e., a first optical fiber connector  1672  and a second optical fiber connector  1674 . In the diagram, the port mapping for the second optical fiber connector  1674  is the same as that of optical fiber connector  1672 . The optical fiber interconnection cable  1670  has the two universal optical fiber interconnection cable port mapping properties described above. 
     First property: The mapping of the transmitter, receiver, and power supply fiber ports in the first optical fiber connector  1672  is the same as the mapping of the transmitter, receiver, and power supply fiber ports in the second optical fiber connector  1674 . 
     Second property: The port mapping of the first optical fiber connector  1672  is a mirror image of the port mapping of the second optical fiber connector  1674  after swapping each transmitter port to a receiver port and swapping each receiver port to a transmitter port in the mirror image. The mirror image is generated with respect to a reflection axis  1640  at the connector edge parallel to the row direction. 
     Alternative view of the second property: Each of the first and second optical fiber connectors  1672 ,  1674  is TX-RX pairwise symmetric and PS symmetric with respect to the central axis that is parallel to the row direction. For example, the optical fiber connector  1672  can be divided in two halves along a central axis parallel to the row direction. The power supply fiber ports (e.g.,  1678 ,  1680 ) are symmetric with respect to the center axis. The transmitter fiber ports (e.g.,  1682 ,  1684 ) and the receiver fiber ports (e.g.,  1686 ,  1688 ) are pairwise symmetric with respect to the center axis, i.e., if there is a transmitter fiber port (e.g.,  1682  or  1684 ) in the upper half portion of the first optical fiber connector  1672 , then there will be a receiver fiber port (e.g.,  1686 ,  1688 ) at a mirror location in the lower half of the optical fiber connector  1672 . Likewise, if there is a receiver fiber port in the upper half portion of the optical fiber connector  1672 , then there is a transmitter fiber port at a mirror location in the lower half portion of the optical fiber connector  1672 . In the example of  FIG.  90   , the middle row  1690  should all be power supply fiber ports. 
     In general, if the port mapping of the first optical fiber connector is a mirror image of the port mapping of the second optical fiber connector after swapping the transmitter and receiver ports in the mirror image, the mirror image is generated with respect to a reflection axis at the connector edge parallel to the row direction (as in the example of  FIG.  90   ), and there is an odd number of rows in the port matrix, then the center row should all be power supply fiber ports. If the port mapping of the first optical fiber connector is a mirror image of the port mapping of the second optical fiber connector after swapping the transmitter and receiver ports in the mirror image, the mirror image is generated with respect to a reflection axis at the connector edge parallel to the column direction, and there is an odd number of columns in the port matrix, then the center column should all be power supply fiber ports. 
       FIG.  91    is a diagram of an example of a viable port mapping for an optical fiber connector  1700  of a universal optical fiber interconnection cable. The optical fiber connector  1700  includes power supply fiber ports (e.g.,  1702 ), transmitter fiber ports (e.g.,  1704 ), and receiver fiber ports (e.g.,  1706 ). The optical fiber connector  1700  is TX-RX pairwise symmetric and PS symmetric with respect to the center axis that is parallel to the column direction. 
       FIG.  92    is a diagram of an example of a viable port mapping for an optical fiber connector  1710  of a universal optical fiber interconnection cable. The optical fiber connector  1710  includes power supply fiber ports (e.g.,  1712 ), transmitter fiber ports (e.g.,  1714 ), and receiver fiber ports (e.g.,  1716 ). The optical fiber connector  1710  is TX-RX pairwise symmetric and PS symmetric with respect to the center axis that is parallel to the column direction. 
       FIG.  93    is a diagram of an example of a port mapping for an optical fiber connector  1720  that is not appropriate for a universal optical fiber interconnection cable. The optical fiber connector  1720  includes power supply fiber ports (e.g.,  1722 ), transmitter fiber ports (e.g.,  1724 ), and receiver fiber ports (e.g.,  1726 ). The optical fiber connector  1720  is not TX-RX pairwise symmetric with respect to the center axis that is parallel to the column direction, or the center axis that is parallel to the row direction. 
       FIG.  94    is a diagram of an example of a viable port mapping for a universal optical fiber interconnection cable that includes a pair of optical fiber connectors, i.e., a first optical fiber connector  1800  and a second optical fiber connector  1802 . The mapping of the transmitter, receiver, and power supply fiber ports in the first optical fiber connector  1800  is the same as the mapping of the transmitter, receiver, and power supply fiber ports in the second optical fiber connector  1802 . The port mapping of the first optical fiber connector  1800  is a mirror image of the port mapping of the second optical fiber connector  1802  after swapping the transmitter and receiver ports in the mirror image. The mirror image is generated with respect to a reflection axis  1804  at the connector edge parallel to the column direction. The optical fiber connector  1800  is TX-RX pairwise symmetric and PS symmetric with respect to the center axis  1806  that is parallel to the column direction. 
       FIG.  95    is a diagram of an example of a viable port mapping for a universal optical fiber interconnection cable that includes a pair of optical fiber connectors, i.e., a first optical fiber connector  1810  and a second optical fiber connector  1812 . The mapping of the transmitter, receiver, and power supply fiber ports in the first optical fiber connector  1810  is the same as the mapping of the transmitter, receiver, and power supply fiber ports in the second optical fiber connector  1812 . The port mapping of the first optical fiber connector  1810  is a mirror image of the port mapping of the second optical fiber connector  1812  after swapping the transmitter and receiver ports in the mirror image. The mirror image is generated with respect to a reflection axis  1814  at the connector edge parallel to the column direction. The optical fiber connector  1810  is TX-RX pairwise symmetric and PS symmetric with respect to the center axis  1816  that is parallel to the column direction. 
     In the example of  FIG.  95   , the first, third, and fifth rows each has an even number of fiber ports, and the second and fourth rows each has an odd number of fiber ports. In general, a viable port mapping for a universal optical fiber interconnection cable can be designed such that an optical fiber connector includes (i) rows that all have even numbers of fiber ports, (ii) rows that all have odd numbers of fiber ports, or (iii) rows that have mixed even and odd numbers of fiber ports. A viable port mapping for a universal optical fiber interconnection cable can be designed such that an optical fiber connector includes (i) columns that all have even numbers of fiber ports, (ii) columns that all have odd numbers of fiber ports, or (iii) columns that have mixed even and odd numbers of fiber ports. 
     The optical fiber connector of a universal optical fiber interconnection cable does not have be a rectangular shape as shown in the examples of  FIGS.  89 ,  90 ,  92  to  95   . The optical fiber connectors can also have an overall triangular, square, pentagonal, hexagonal, trapezoidal, circular, oval, or n-sided polygon shape, in which n is an integer larger than 6, as long as the arrangement of the transmitter, receiver, and power supply fiber ports in the optical fiber connectors have the three universal optical fiber interconnection cable port mapping properties described above. 
     In the examples of  FIGS.  80 A,  82 A,  84 A, and  87 A , the switch boxes (e.g.,  1302 ,  1304 ) includes co-packaged optical modules (e.g.,  1312 ,  1316 ) that is optically coupled to the optical fiber interconnection cables or optical cable assemblies (e.g.,  1340 ,  1400 ,  1490 ) through fiber array connectors. For example, the fiber array connector can correspond to the first optical connector part  213  in  FIG.  20   . The optical fiber connector (e.g.,  1342 ,  1344 ,  1402 ,  1404 ,  1492 ,  1498 ) of the optical cable assembly can correspond to the second optical connector part  223  in  FIG.  20   . The port map (i.e., mapping of power supply fiber ports, transmitter fiber ports, and receiver fiber ports) of the fiber array connector (which is optically coupled to the photonic integrated circuit) is a mirror image of the port map of the optical fiber connector (which is optically coupled to the optical fiber interconnection cable). The port map of the fiber array connector refers to the arrangement of the power supply, transmitter, and receiver fiber ports when viewed from an external edge of the fiber array connector into the fiber array connector. 
     As described above, universal optical fiber connectors have symmetrical properties, e.g., each optical fiber connector is TX-RX pairwise symmetric and PS symmetric with respect to one of the main or center axes, which can be parallel to the row direction or the column direction. The fiber array connector also has the same symmetrical properties, e.g., each fiber array connector is TX-RX pairwise symmetric and PS symmetric with respect to one of the main or center axes, which can be parallel to the row direction or the column direction. 
     In some implementations, a restriction can be imposed on the port mapping of the optical fiber connectors of the optical cable assembly such that the optical fiber connector can be pluggable when rotated by 180 degrees, or by 90 degrees in the case of a square connector. This results in further port mapping constraints. 
       FIG.  101    is a diagram of an example of an optical fiber connector  1910  having a port map  1912  that is invariant against a 180-degree rotation. Rotating the optical fiber connector  1910  180 degrees results in a port map  1914  that is the same as the port map  1912 . The port map  1912  also satisfies the second universal optical fiber interconnection cable port mapping property, e.g., the optical fiber connector is TX-RX pairwise symmetric and PS symmetric with respect to the center axis parallel to the column direction. 
       FIG.  102    is a diagram of an example of an optical fiber connector  1920  having a port map  1922  that is invariant against a 90-degree rotation. Rotating the optical fiber connector  1920  180 degrees results in a port map  1924  that is the same as the port map  1922 . The port map  1922  also satisfies the second universal optical fiber interconnection cable port mapping property, e.g., the optical fiber connector is TX-RX pairwise symmetric and PS symmetric with respect to the center axis parallel to the column direction. 
       FIG.  103 A  is a diagram of an example of an optical fiber connector  1930  having a port map  1932  that is TX-RX pairwise symmetric and PS symmetric with respect to the center axis parallel to the column direction. When mirroring the port map  1932  to generate a mirror image  1934  and replacing each transmitter port with a receiver port as well as replacing each receiver port with a transmitter port in the mirror image  1934 , the original port map  1932  is recovered. The mirror image  1934  is generated with respect to a reflection axis at the connector edge parallel to the column direction. 
     Referring to  FIG.  103 B , the port map  1932  of the optical fiber connector  1930  is also TX-RX pairwise symmetric and PS symmetric with respect to the center axis parallel to the row direction. When mirroring the port map  1932  to generate a mirror image  1936  and replacing each transmitter port with a receiver port as well as replacing each receiver port with a transmitter port in the mirror image  1936 , the original port map  1932  is recovered. The mirror image  1936  is generated with respect to a reflection axis at the connector edge parallel to the row direction. 
     In the examples of  FIGS.  69 A to  78 ,  96  to  98 , and  100   , one or more fans (e.g.,  1086 ,  1092 ,  1848 ,  1894 ) blow air across the heatsink (e.g.,  1072 ,  1114 ,  1130 ,  1168 ,  1846 ) thermally coupled to the data processor (e.g.,  1844 ). The co-packaged optical modules can generate heat, in which some of the heat can be directed toward the heatsink and dissipated through the heatsink. To further improve heat dissipation from the co-packaged optical modules, in some implementations, the rackmount system includes two fans placed side-by-side, in which a first fan blows air toward the co-packaged optical modules that are mounted on a front side of the printed circuit board (e.g.,  1068 ), and a second fan blows air toward the heatsink that is thermally coupled to the data processor mounted on a rear side of the printed circuit board. 
     In some implementations, the one or more fans can have a height that is smaller than the height of the housing (e.g.,  1824 ) of the rackmount server (e.g.,  1820 ). The co-packaged optical modules (e.g.,  1074 ) can occupy a region on the printed circuit board (e.g.,  1068 ) that extends in the height direction greater than the height of the one or more fans. One or more baffles can be provided to guide the cool air from the one or more fans or intake air duct to the heatsink and the co-packaged optical modules. One or more baffles can be provided to guide the warm air from the heatsink and the co-packaged optical modules to an air duct that directs the air toward the rear of the housing. 
     When the one or more fans have a height that is smaller than the height of the housing (e.g.,  1824 ), the space above and/or below the one or more fans can be used to place one or more remote laser sources. The remote laser sources can be positioned near the front panel and also near the co-packaged optical modules. This allows the remote laser sources to be serviced conveniently. 
       FIG.  104    shows a top view of an example of a rackmount device  1940 . The rackmount device  1940  includes a vertically oriented printed circuit board  1230  positioned at a distance behind a front panel  1224  that can be closed during normal operation of the device, and opened for maintenance of the device, similar to the configuration of the rackmount server  1220  of  FIG.  77 A . A data processing chip  1070  is electrically coupled to the rear side of the vertical printed circuit board  1230 , and a heat dissipating device or heat sink  1072  is thermally coupled to the data processing chip  1070 . Co-packaged optical modules  1074  are attached to the front side (i.e., the side facing the front exterior of the housing  1222 ) of the vertical printed circuit board  1230 . A first fan  1942  is provided to blow air across the co-packaged optical modules  1074  at the front side of the printed circuit board  1230 . A second fan  1944  is provided to blow air across the heatsink  1072  to the rear of the printed circuit board  1230 . The first and second fans  1942 ,  1944  are positioned at the left of the printed circuit board  1230 . Cooler air (represented by arrows  1946 ) is directed from the first and second fans  1942 ,  1944  toward the heatsink  1072  and the co-packaged optical modules  1074 . Warmer air (represented by arrows  1948 ) is directed from the heatsink  1072  and the co-packaged optical modules  1074  through an air duct  1950  positioned at the right of the printed circuit board  1230  toward the rear of the housing. 
       FIG.  105    shows a front view of the rackmount device  1940  when the front panel  1224  is opened to allow access to the co-packaged optical modules  1074 . The first and second fans  1942 ,  1944  have a height that is smaller than the height of the region occupied by the co-packaged optical modules  1074 . A first baffle  1952  directs the air from the fan  1942  to the region where the co-packaged optical modules  1074  are mounted, and a second baffle  1954  directs the air from the region where the co-packaged optical modules  1074  are mounted to the air duct  1950 . 
     In this example, the first and second fans  1942 ,  1944  have a height that is smaller than the height of the housing of the rackmount device  1940 . Remote laser sources  1956  can be positioned above and below the fans. Remote laser sources  1956  can also be positioned above and below the air duct  1950 . 
     For example, a switch device having a 51.2 Tbps bandwidth can use thirty-two 1.6 Tbps co-packaged optical modules. Two to four power supply fibers (e.g.,  1326  in  FIG.  80 A ) can be provided for each co-packaged optical module, and a total of 64 to 128 power supply fibers can be used to provide optical power to the 32 co-packaged optical modules. One or two laser modules at 500 mW each can be used to provide the optical power to each co-packaged optical module, and 32 to 64 laser modules can be used to provide the optical power to the 32 co-packaged optical modules. The 32 to 64 laser modules can be fitted in the space above and below the fans  1942 ,  1944  and the air duct  1950 . 
     For example, the area  1958   a  above the fans  1942 ,  1944  can have an area (measured along a plane parallel to the front panel) of about 16 cm×5 cm and can fit about 28 QSFP cages, and the area  1958   b  below the fans can have an area of about 16 cm×5 cm and can fit about 28 QSFP cages. The area  1958   c  above the air duct  1950  can have an area of about 8 cm×5 cm and can fit about 12 QSFP cages, and the area  1958   d  below the air duct  1950  can have an area of about 8 cm×5 cm and can fit about 12 QSFP cages. Each QSFP cage can include a laser module. In this example, a total of 80 QSFP cages can be fit above and below the fans and the air duct, allowing 80 laser modules to be positioned near the front panel and near the co-packaged optical modules, making it convenient to service the laser modules in the event of malfunction or failure. 
     Referring to  FIGS.  106  and  107   , an optical cable assembly  1960  includes a first fiber connector  1962 , a second fiber connector  1964 , and a third fiber connector  1966 . The first fiber connector  1962  can be optically connected to the co-packaged optical module  1074 , the second fiber connector  1964  can be optically connected to the laser module, and the third fiber connector  1966  can be optically connected to the fiber connector part (e.g.,  1232  of  FIG.  77 A ) at the front panel  1224 . The first fiber connector  1962  can have a configuration similar to that of the fiber connector  1342  of  FIGS.  80 C,  80 D . The second fiber connector  1964  can have a configuration similar to that of the fiber connector  1346 . The third fiber connector  1964  can have a configuration similar to that of the first fiber connector  1962  but without the power supply fiber ports. The optical fibers  1968  between the first fiber connector  1962  and the third fiber connector  1966  perform the function of the fiber jumper  1234  of  FIG.  77 A . 
       FIG.  108    is a diagram of an example of a rackmount device  1970  that is similar to the rackmount device  1940  of  FIGS.  104 ,  105 ,  107   , except that the optical axes of the laser modules  1956  are oriented at an angle θ relative to the front-to-rear direction, 0&lt;θ&lt;90°. This can reduce the bending of the optical fibers that are optically connected to the laser modules  1956 . 
       FIG.  109    is a diagram showing the front view of the rackmount device  1970 , with the optical cable assembly  1960  optically connected to modules of the rackmount device  1970 . When the laser modules  1956  are oriented at an angle θ relative to the front-to-rear direction, 0&lt;θ&lt;90°, fewer laser modules  1956  can be placed in the spaces above and below the fans  1942 ,  1944  and the air duct  1950 , as compared to the example of  FIGS.  104 ,  105 ,  107   , in which the optical axes of the laser modules  1956  are oriented parallel to the front-to-rear direction. In the example of  FIG.  109   , a total of 64 laser modules are placed in the spaces above and below the fans  1942 ,  1944  and the air duct  1950 . 
       FIG.  110    is a top view diagram of an example of a rackmount device  1980  that is similar to the rackmount device  1940  of  FIGS.  104 ,  105 ,  107   , except that the optical axes of the laser modules  1956  are oriented parallel to the front panel  1224 . This can reduce the bending of the optical fibers that are optically connected to the laser modules  1956 . 
       FIG.  111    is a front view diagram of the rackmount device  1980 , with the optical cable assembly  1960  optically connected to modules of the rackmount device  1980 . The laser modules  1956   a  are positioned to the left side of the space above and below the fans  1942 ,  1944 . Sufficient space (e.g.,  1982 ) is provided at the right of the laser modules  1956   a  to allow the user to conveniently connect or disconnect the fiber connectors  1964  to the laser modules  1956   a . The laser modules  1956   b  are positioned above and below the air duct  1950 . Sufficient space (e.g.,  1984 ) is provided at the left of the laser modules  1956   b  to allow the user to conveniently connect or disconnect the fiber connectors  1964  to the laser modules  1956   b.    
     Referring to  FIG.  112   , a table  1990  shows example parameter values of the rackmount device  1940 . 
       FIGS.  113  and  114    show another example of a rackmount device  2000  and example parameter values. 
       FIGS.  115  and  116    are a top view and a front view, respectively, of the rackmount device  2000 . An upper baffle  2002  and a lower baffle  2004  are provided to guide the air flowing from the fans  1942 ,  1944  to the heatsink  1072  and the co-packaged optical modules  1074 , and from the heatsink  1072  and the co-packaged optical modules  1074  to the air duct  1950 . In this example, portions of the upper and lower baffles  2002 ,  2004  form portions of the upper and lower walls of the air duct  1950 . 
     The upper baffle  2002  includes a cutout or opening  2006  that allows optical fibers  2008  to pass through. As shown in  FIG.  116   , the optical fibers  2008  extend from the co-packaged optical modules  1074   a  upward, through the cutout or opening  2006  in the upper baffle  2002 , and extend toward the laser modules  1956  along the space above the upper baffle  2002 . The upper baffle  2002  allows the optical fibers  2008  to be better organized to reduce the obstruction to the air flow caused by the optical fibers  2008 . The lower baffle  2004  has a similar cutout or opening to help organize the optical fibers that are optically connected to the laser modules located in the space below the fans  1942 ,  1944 . 
       FIG.  117    is a top view diagram of a system  2010  that includes a front panel  2012 , which can be rotatably coupled to the lower panel by a hinge. The front panel  2012  includes an air inlet grid  2014  and an array of fiber connector parts  2016 . Each fiber connector part  2016  can be optically coupled to the third fiber connector  1966  of the cable assembly  1960  of  FIG.  106   . In some implementations, the hinged front panel includes a mechanism that shuts off the remote laser source modules  1956 , or reduces the power to the remote laser source modules  1956 , once the flap is opened. This prevents the technicians from being exposed to harmful radiation. 
       FIG.  118    is a diagram of an example of a system  2120  that includes a recirculating reservoir that circulates a coolant to carry heat away from the data processor, which for example can be a switch integrated circuit. In this example, the data is immersed in the coolant, and the inlet fan is used to blow air across the surface of the co-packaged optical modules to a heat dissipating device thermally coupled to the co-packaged optical modules. 
       FIGS.  119  to  122    are examples that provide heat dissipating solutions for co-packaged optical modules, taking into consideration the locations of “hot aisles” in data centers. In case it is desirable that fiber cabling be done on the back side of a rack (where hot air is blown out, hence “hot aisle”), one can either use a duct inside the box to transfer cold air to the co-packaged optical modules that are now mounted on the back side ( FIG.  121   ) or one can use fiber jumper cables to connect the co-packaged optical modules that are still facing the front aisle (towards the cold aisle) to connect to a “back-panel” facing the hot aisle ( FIG.  122   ). 
     In the example of  FIG.  104   , the printed circuit board  1230  is positioned a short distance from the front panel  1224  to improve air flow between the printed circuit board  1230  and the front panel  1224  to help dissipate heat generated by the co-packaged optical modules  1074 . The following describes a mechanism that allows the user to conveniently connect the co-packaged optical module to an optical fiber cable using a pluggable module that has a rigid structure that spans the distance between the co-packaged optical modules and the front panel. 
     Referring to  FIG.  123   , in some implementations, a rackmount server  12300  can have a hinge-mounted front panel, similar to the example shown in  FIG.  77 A . The rackmount server  12300  includes a housing  12302  having a top panel  12304 , a bottom panel  12306 , and a front panel  12308  that is coupled to the bottom panel  12306  using a hinge  12324 . A vertically mounted substrate  12310  is positioned substantially perpendicular to the bottom panel  12306  and recessed from the front panel  12308 . The substrate  12310  includes a first side facing the front direction relative to the housing  12302  and a second side facing the rear direction relative to the housing  12302 . At least one electronic processor or data processing chip  12312  is electrically coupled to the second side of the vertical substrate  12310 , and a heat dissipating device or heat sink  12314  is thermally coupled to the at least one data processing chip  12312 . Co-packaged optical modules  12316  (or optical interconnect modules) are attached to the first side of the vertical substrate  12310 . The substrate  12310  provides high-speed connections between the co-packaged optical modules  12316  and the data processing chip  12312 . The co-packaged optical module  12316  is optically connected to a first fiber connector part  12318 , which is optically connected through a fiber pigtail  12320  to one or more second fiber connector parts  12322  mounted on the front panel  12308 . 
     In the example of  FIG.  123   , the front panel  12308  is rotatably connected to the bottom panel by the hinge  12324 . In other examples, the front panel can be rotatably connected to the top panel or the side panel so as to flap upwards or to flap sideways when opened. 
     For example, the electronic processor  12312  can be a network switch, a central processor unit, a graphics processor unit, a tensor processing unit, a neural network processor, an artificial intelligence accelerator, a digital signal processor, a microcontroller, or an application specific integrated circuit (ASIC). For example, the electronic processor  12312  can be a memory device or a storage device. In this context, processing of data includes writing data to, or reading data from, the memory or storage device, and optionally performing error correction. The memory device can be, e.g., random access memory (RAM), which can include, e.g., dynamic RAM (DRAM) or static RAM (SRAM). The storage device can include, e.g., solid state memory or drive, which can include, e.g., one or more non-volatile memory (NVM) Express® (NVMe) SSD (solid state drive) modules, or Intel® Optane™ persistent memory. The example of  FIG.  123    shows one electronic processor  12312 , through there can also be multiple electronic processors  12312  mounted on the substrate  12310 . In some examples, the substrate  12310  can also be replaced by a circuit board. 
     The co-packaged optical module (or optical interconnect module)  12316  can be similar to, e.g., the integrated optical communication device  262  of  FIG.  6   ;  282  of  FIGS.  7 - 9   ;  462 ,  466 ,  448 ,  472  of  FIG.  17   ;  612  of  FIG.  23   ;  684  of  FIG.  26   ;  704  of  FIG.  27   ;  724  of  FIG.  28   ; the co-packaged optical module  1074  of  FIGS.  68 A,  69 A,  70 ,  71 A ;  1132  of  FIG.  73 A ;  1160  of  FIG.  74 A ;  1074  of  FIGS.  75 A,  75 B,  77 A,  77 B,  104 ,  107 ,  109 ,  116   ;  1312  of  FIGS.  80 A,  82 A,  84 A ; or  1564 ,  1582  of  FIG.  87 A . In the example of  FIG.  123   , the optical interconnect module or co-packaged optical module  12316  does not necessarily have to include serializers/deserializers (SerDes), e.g.,  216 ,  217  of  FIGS.  2  to  8  and  10  to  12   . The optical interconnect module or co-packaged optical module  12316  can include the photonic integrated circuit without any serializers/deserializers. For example, the serializers/deserializers can be mounted on the circuit board separate from the optical interconnect module or co-packaged optical module  12316 . 
       FIG.  159    is a side view of an example of a rackmount server  15900  that has a hinge-mounted front panel. The rackmount server  15900  includes a housing  15902  having a top panel  15904 , a bottom panel  15906 , and an upper swivel front panel  15908  that is coupled to a lower fixed front panel  15930  using a hinge  15910 . In some examples, the hinge can be attached to the side panel so that the front panel is opened horizontally. A horizontally mounted host printed circuit board  15912  is attached to the bottom panel  15906 . A vertically mounted printed circuit board  15914 , which can be, e.g., a daughter-card, is positioned substantially vertically and perpendicular to the bottom panel  15906  and recessed from the front panel  15908 . A package substrate  15916  is attached to the front side of the vertical printed circuit board  15914 . At least one electronic processor or data processing chip  15918  is electrically coupled to the rear side of the package substrate  15916 , and a heat dissipating device or heat sink  15920  is thermally coupled to the at least one data processing chip  15918 . Co-packaged optical modules  15922  (or optical interconnect modules) are removably attached to the front side of the package substrate  15916 . The package substrate  15916  provides high-speed connections between the co-packaged optical modules  15922  and the data processing chip  15918 . The co-packaged optical module  15922  is optically connected to a first fiber connector part  15924 , which is optically connected through a fiber pigtail  15926  to one or more second fiber connector parts  15928  attached to the back side of the front panel  15908 . The second fiber connector parts  15928  can be optically connected to optical fiber cables that pass through openings in the hinged front panel  15908 . 
     For example, the fiber connector  15928  can be connected to the backside of the front panel  15908  during replacement of the CPO module  15922 . The CPO module  15922  can be unplugged from the connector (e.g., an LGA socket) on the package substrate  15916 , and be disconnected from the first fiber connector part  15924 . 
     For example, one or more rows of pluggable external laser sources (ELS)  15932  can be in standard pluggable form factor accessible from the lower fixed part  15930  of the front panel with rear blind-mate connectors. Optical fibers  15934  transmit the power supply light from the laser sources  15932  to the CPO modules  15922 . The external laser sources  15932  are electrically connected to a conventionally (horizontal) oriented system printed circuit board or the vertically oriented daughterboard. In this example, the row(s) of pluggable external laser sources  15932  is/are positioned below the datapath optical connection. The pluggable external laser sources  15932  do not need to connect to the CPO substrate because there are no high-speed signals that require proximity. 
     In some implementations, as shown in  FIG.  160   , external laser sources can be located behind the hinged front panel (not user accessible without opening the door) and can then be front-mating similar to typical optical pluggables.  FIG.  160    is a top view of an example of a rackmount server  16000  that is similar to the rackmount server  15900  of  FIG.  159    except that one or more rows of external laser sources  16002  are placed inside the housing  15902 . Optical fibers  15934  transmit the power supply light from the laser sources  16002  to the CPO modules  15922 . 
       FIG.  161    is a diagram of an example of the optical cable  15926  that optically couples the CPO modules  15922  to the optical fiber cables at the front panel  15908 . The optical cable  15926  includes a first multi-fiber push on (MPO) connector  16100 , a laser supply MPO connector  16102 , four datapath MPO connectors  16104 , and a jumper cable  16106  that includes optical fibers that optically connect the MPO connectors. In this example, the optical cable  15926  supports a total bandwidth of 1.6 Tb/s, including 16 full-duplex 400G DR4+ signals (100G per fiber) plus 4 ELS connections. 
     The first MPO connector  16100  is optically coupled to the CPO module  15922  and includes, e.g., 36 fiber ports (e.g., 3 rows of fiber ports, each row having 12 fiber ports, similar to the fiber ports shown in  FIGS.  80 D,  80 E,  82 D,  82 E,  89  to  93   ), which includes 4 power supply fiber ports and 32 data fiber ports. The laser supply MPO connector  16102  is optically coupled to the external laser source, such as  15932  ( FIG.  159   ) or  16002  ( FIG.  160   ). The datapath MPO connectors  16104  are optically coupled to external optical fiber cables. For example, each external optical fiber cable can support a 400GBASE-DR4 link, so the four datapath MPO connectors  16104  can support 16 full-duplex 400G DR4+ signals (100G per fiber). The jumper cable  16106  fans the MPO connector  16100  out to datapath MPOs  16104  on the front panel  15908  (e.g., 4×400G DR4+ using 4×1×12 MPOs or 2×800G DR8+ using 2×2×12 MPOs) and the laser supply MPO  16102 . For example, the optical cable  15926  can be DR-16+ (e.g., 1.6 Tb/s at 100G per fiber, gray optics, ˜2 km reach). This architecture also supports FR-n (WDM). 
     In this example, the CPO module  15922  is configured to support 4×400 Gb/s=1.6 Tb/s data rate. The jumper cable  16106  includes four (4) power supply optical fibers  15934  that optically connect four (4) power supply fiber ports of the laser supply MPO connector  16102  to the corresponding power supply fiber ports of the first MPO connector  16100 . The jumper cable  16106  includes four (4) sets of eight (8) data optical fibers. The eight (8) data optical fibers  16106  optically connect eight (8) transmit or receive fiber ports of each datapath MPO connector  16104  to the corresponding transmit or receive fiber ports of the first MPO connector  16100 . For example, the power supply optical fibers  15934  can be polarization maintaining optical fibers. The fan-out cable  16106  can handle multiple functions including merging the external laser source and data paths, splitting of external light source between multiple CPO modules  15922 , and handling polarization. Regarding the force requirement on the CPO module&#39;s connector, the optical connector leverages an MPO type connection and can have a similar or smaller force as compared to a standard MPO connector. 
     Referring to  FIG.  124   , in some implementations, a rackmount server  12400  has a front panel  12402  (which can be, e.g., fixed) and a vertically mounted substrate  12310  recessed from the front panel  12402 . The front panel  12402  has openings that allow pluggable modules  12404  to be inserted. Each pluggable module  12404  includes a co-packaged optical module  12316 , one or more multi-fiber push on (MPO) connectors  12406 , a fiber guide  12408  that mechanically connects the co-packaged optical module  12316  to the one or more multi-fiber push on connectors  12406 , and a fiber pigtail  12410  that optically connects the co-packaged optical module  12316  to the one or more multi-fiber push on connectors  12406 . For example, the length of the fiber guide  12408  is designed such that when the pluggable module  12404  is inserted into the opening of the front panel  12402  and the co-packaged optical module  12316  is electrically coupled to the vertically mounted substrate  12310 , the one or more multi-fiber push on connectors  12406  are near the front panel, e.g., flush with, or slightly protrude from, the front panel  12402  so that the user can conveniently attach external fiber optic cables. For example, the front face of the connectors  12406  can be within an inch, or half an inch, or one-fourth of an inch, of the front surface of the front panel  12402 . 
     For example, the housing  12302  can include guide rails or guide cage  12412  that help guide the pluggable modules  12404  so that the electrical connectors of the co-packaged optical modules  12316  are aligned with the electrical connectors on the printed circuit board. 
     In some implementations, the rackmount server  12400  has inlet fans mounted near the front panel  12402  and blow air in a direction substantially parallel to the front panel  12402 , similar to the examples shown in  FIGS.  96  to  98 ,  100 ,  104 ,  105 ,  107  to  116   . The height h 1  of the fiber guide  12408  (measured along a direction perpendicular to the bottom panel) can be designed to be smaller than the height h 2  of the multi-fiber push on connectors  12406  so that there is space  12412  between adjacent fiber guides  12408  (in the vertical direction) to allow air to flow between the fiber guides  12408 . The fiber guide  12408  can be a hollow tube with inner dimensions sufficiently large to accommodate the fiber pigtail  12410 . The fiber guide  12408  can be made of metal or other thermally conductive material to help dissipate heat generated by the co-packaged optical module  12316 . The fiber guide  12408  can have arbitrary shapes, e.g., to optimize thermal properties. For example, the fiber guide  12408  can have side openings, or a web structure, to allow air to flow pass the fiber guide  12408 . The fiber guide  12408  is designed to be sufficiently rigid to enable the pluggable module  12404  to be inserted and removed from the rackmount server  12400  multiple times (e.g., several hundred times, several thousand times) under typical usage without deformation. 
       FIG.  125    includes various views of an example of a rackmount server  12500  that includes CPO front-panel pluggable modules  12502 . Each pluggable module  12502  includes a co-packaged optical module  12504  that is optically coupled to one or more array connectors, such as multi-fiber push on connectors  12506 , through a fiber pigtail  12508 . In this example, each co-packaged optical module  12504  is optically coupled to 2 array connectors  12506 . The pluggable module  12502  includes a rigid fiber guide  12510  that approximately spans the distance between the front panel and the vertically mounted printed circuit board. 
     A front view  12512  (at the upper right of  FIG.  125   ) shows an example of a front panel  12514  with an upper group of array connectors  12516 , a lower group of array connectors  12518 , a left group of array connectors  12520 , and a right group of array connectors  12522 . Each rectangle in the front view  12512  represents an array connector  12506 . In this example, each group of array connectors  12516 ,  12518 ,  12520 ,  12522  includes 16 array connectors  12506 . 
     A front view  12524  (at the middle right of  FIG.  25   ) shows an example of a recessed vertically mounted printed circuit board  12526  on which an application specific integrated circuit (ASIC) or data processing chip  12312  is mounted on the rear side and not shown in the front view  12524 . The printed circuit board  12526  has an upper group of electrical contacts  12528 , a lower group of electrical contacts  12530 , a left group of electrical contacts  12532 , and a right group of electrical contacts  12534 . Each rectangle in the front view  12524  represents an array of electrical contacts associated with one co-packaged optical module  12504 . In this example, each group of electrical contacts  12528 ,  12530 ,  12532 ,  12534  includes 8 arrays of electrical contacts that are configured to be electrically coupled to the electrical contacts of 8 co-packaged optical modules  12504 . In this example, each co-packaged optical module  12504  is optically coupled to two array connectors  12506 , so the number of rectangles shown in the front view  12512  is twice the number of squares shown in the front view  12524 . The front panel  12514  includes openings that allow insertion of the pluggable modules  12502 . In this example, each opening has a size that can accommodate two array connectors  12506 . 
     A top view  12536  (at the lower right of  FIG.  125   ) of the front portion of the rackmount server  12500  shows a top view of the pluggable modules  12506 . In the top view  12536 , the two left-most pluggable modules  12538  include co-packaged optical modules  12504  that are electrically coupled to the electrical contacts in the left group of electrical contacts  12532  shown in the front view  12524 , and include array connectors  12506  in the left group of array connectors  12520  shown in the front view  12512 . In the top view  12536 , the two right-most pluggable modules  12540  include co-packaged optical modules  12504  that are electrically coupled to the electrical contacts in the right group of electrical contacts  12534  shown in the front view  12524 , and include array connectors  12506  in the right group of array connectors  12522  shown in the front view  12512 . In the top view  12536 , the four middle pluggable modules  12542  include co-packaged optical modules  12504  that are electrically coupled to the electrical contacts in the upper group of electrical contacts  12528  shown in the front view  12524 , and include array connectors  12506  in the upper group of array connectors  12516  shown in the front view  12512 . 
     The front view  12524  (at the middle right of  FIG.  125   ) shows a first inlet fan  12544  that blows air from left to right across the space between the front panel  12514  and the printed circuit board  12526 . The top view  12536  (at the lower right of  FIG.  125   ) shows the first inlet fan  12544  and a second inlet fan  12546 . The first inlet fan  12544  is mounted at the front side of the printed circuit board  12526  and blows air across the pluggable modules  12502  to help dissipate the heat generated by the co-packaged optical modules  12504 . The second inlet fan  12546  is mounted at the rear side of the printed circuit board  12526  and blows air across the data processing chip  12312  and the heat dissipating device  12314 . 
     As shown in the front view  12512  (at the upper right of the  FIG.  125   ), the front panel  12514  includes an opening  12548  that provides incoming air for the front inlet fans  12544 ,  12546 . A protective mesh or grid can be provided at the opening  12548 . 
     A left side view  12550  (at the middle left of  FIG.  125   ) of the front portion of the rackmount server  12500  shows pluggable modules  12552  that correspond to the upper group of array connectors  12516  in the front view  12512  and the upper group of electrical contacts  12528  in the front view  12524 . The left side view  12550  also shows pluggable modules  12554  that correspond to the lower group of array connectors  12518  in the front view  12512  and the lower group of electrical contacts  12530  in the front view  12524 . As shown in the left side view  12550 , guide rails or guide cage  12556  can be provided to help guide the pluggable modules  12502  so that the electrical connectors of the co-packaged optical modules  12504  are aligned with the electrical contacts on the printed circuit board  12526 . The pluggable modules  12502  can be fastened at the front panel  12514 , e.g., using clip mechanisms. 
     A left side view  12558  of the front portion of the rackmount server  12500  shows pluggable modules  12560  that correspond to the left group of array connectors  12520  in the front view  12512  and the left group of electrical contacts  12532  in the front view  12524 . 
     In this example, the fiber guides  12510  for the pluggable modules  12502  that correspond to the left and right groups of array connectors  12520 ,  12522 , and the left and right groups of electrical contacts  12532 ,  12534  are designed to have smaller heights so that there are gaps between adjacent fiber guides  12510  in the vertical direction to allow air to flow through. 
     In some implementations, each co-packaged optical module can receive optical signals from a large number of fiber cores, and each co-packaged optical module can be optically coupled to external fiber optic cables through three or more array connectors that occupy an overall area at the front panel that is larger than the overall area occupied by the co-packaged optical module on the printed circuit board. 
     Referring to  FIG.  126   , in some implementations, a rackmount server  12600  is designed to use pluggable modules  12602  having a spatial fan-out design. Each pluggable module  12602  includes a co-packaged optical module  12604  that is optically coupled, through a fiber pigtail  12606 , to one or more array connectors  12608  that have an overall area larger than the area of the co-packaged optical module  12604 . The area is measured along the plane parallel to the front panel. In this example, each co-packaged optical module  12604  is optically coupled to 4 array connectors  12608 . The pluggable module  12602  includes a tapered fiber guide  12610  that is narrower near the co-packaged optical module  12604  and wider near the array connectors  12608 . 
     A front view  12612  (at the upper right of  FIG.  126   ) shows an example of a front panel  12614  that can accommodate an array of 128 array connectors  12608  arranged in 16 rows and 8 columns. The front view  12524  (at the middle right of  FIG.  126   ) of the recessed printed circuit board  12526  and the top view (at the lower right of  FIG.  126   ) of the front portion of the rackmount server  12600  are similar to corresponding views in  FIG.  125   . 
     A left side view  12616  (at the middle left of  FIG.  126   ) shows an example of pluggable modules  12602  that have co-packaged optical modules that are connected to the upper and lower groups of electrical contacts on the printed circuit board  12526 . A left side view  12618  (at the lower left of  FIG.  126   ) shows an example of pluggable modules  12602  that have co-packaged optical modules that are connected to the left group of electrical contacts on the printed circuit board  12526 . As shown in the left side view  12618 , guide rails or guide cage  12620  can be provided to help guide the pluggable modules  12602  so that the electrical contacts of the co-packaged optical modules  12604  are aligned with corresponding electrical contacts on the printed circuit board  12526 . 
     For example, the rackmount server  12400 ,  12500 ,  12600  can be provided to customers with or without the pluggable modules. The customer can insert as many pluggable modules as needed. 
     Referring to  FIG.  127   , in some implementations, a CPO front panel pluggable module  12700  can include a blind mate connector  12702  that is designed receive optical power supply light. A portion of the fiber pigtail  12714  is optically coupled to the blind mate connector  12702 .  FIG.  127    includes a side view  12704  of a rackmount server  12706  that includes laser sources  12708  that provide optical power supply light to the co-packaged optical modules  12710  in the pluggable modules  12700 . The laser sources  12708  are optically coupled, through optical fibers  12712 , to optical connectors  12714  that are configured to mate with the blind-mate connectors  12702  on the pluggable modules  12700 . When the pluggable module  12700  is inserted into the rackmount server  12706 , the electrical contacts of the co-packaged optical module  12710  contacts the corresponding electrical contacts on the printed circuit board  12526 , and the blind-mate connector  12702  mates with the optical connector  12714 . This allows the co-packaged optical module  12710  to receive optical signals from external fiber optic cables and the optical power supply light through the fiber pigtail  12714 . 
     In some implementations, to prevent the light from the laser source  12708  from harming operators of the rackmount server  12706 , a safety shut-off mechanism is provided. For example, a mechanical shutter can be provided on disconnection of the blind-mate connector  12702  from the optical connector  12712 . As another example, electrical contact sensing can be used, and the laser can be shut off upon detecting disconnection of the blind-mate connector  12702  from the optical connector  12712 . 
     Referring to  FIG.  128   , in some implementations, one or more photon supplies  12800  can be provided in the fiber guide  12408  to provide power supply light to the co-packaged optical module  12316  through one or more power supply optical fibers  12802 . The one or more photon supplies  12800  can be selected to have a wavelength (or wavelengths) and power level (or power levels) suitable for the co-packaged optical module  12316 . Each photon supply  12800  can include, e.g., one or more diode lasers having the same or different wavelengths. 
     Electrical connections (not shown in the figure) can be used to provide electrical power to the one or more photon supplies  12800 . In some implementations, the electrical connections are configured such that when the co-packaged optical module  12316  is removed from the substrate  12310 , the electrical power to the one or more photon supplies  12800  is turned off. This prevents light from the one or more photon supplies  12800  from harming operators. Additional signals lines (not shown in the figure) can provide control signals to the photon supply  12800 . In some embodiments, electrical connections to the photon supplies  12800  are made to the system through the CPO module  12316 . In some embodiments, electrical connections to the photon supplies  12800  use parts of the fiber guide  12408 , which in some embodiments is made from electrically conductive materials. In some embodiments, the fiber guide  12408  is made of multiple parts, some of which are made from electrically conductive materials and some of which are made from electrically insulating materials. In some embodiments, two electrically conductive parts are mechanically connected but electrically separated by an electrical insulating part. 
     For example, the photon supply  12800  is thermally coupled to the fiber guide  12408 , and the fiber guide  12408  can help dissipate heat from the photon supply  12800 . 
     In some examples, the CPO module  12316  is coupled to spring-loaded elements or compression interposers mounted on the substrate  12310 . The force required to press the CPO module  12316  into the spring-loaded elements or the compression interposers can be large. The following describes mechanisms to facilitate pressing the CPO module  12361  into the spring-loaded elements or the compression interposers. 
     Referring to  FIG.  129   , in some implementations, a rackmount server includes a substrate  12310  that is attached to a printed circuit board  12906 , which has an opening to allow the data processing chip  12312  to protrude or partially protrude through the opening and be attached to the substrate  12310 . The printed circuit board  12906  can have many functions, such as providing support for a large number of electrical power connections for the data processing chip  12312 . The CPO module  12316  can be mounted on the substrate  12310  through a CPO mount or a front lattice  12902 . A bolster plate  12914  is attached to the rear side of the printed circuit board  12906 . Both the substrate  12310  and the printed circuit board  12906  are sandwiched between the CPO mount or front lattice  12902  and the bolster plate  12914  to provide mechanical strength so that CPO modules  12316  can exert the required pressure onto the substrate  12310 . Guide rails/cage  12900  extend from the front panel  12904  or the front portion of the fiber guide  12408  to the bolster plate  12914  and provide rigid connections between the CPO mount  12902  and the front panel  12904  or the front portion of the fiber guide  12408 . 
     Clamp mechanisms  12908 , such as screws, are used to fasten the guide rails/cage  12900  to the front portion of the fiber guide  12408 . After the CPO module  12316  is initially pressed into the spring-loaded elements or the compression interposers, the screws  12908  are tightened, which pulls the guide rails/cage  12900  forward, thereby pulling the bolster plate  12914  forward and provide a counteracting force that pushes the spring-loaded elements or the compression interposers in the direction of the CPO module  12316 . Springs  12910  can be provided between the guide rails  12900  and the front portion of the fiber guide  12408  to provide some tolerance in the positioning of the front portion of the fiber guide  12408  relative to the guide rails  12900 . 
     The right side of  FIG.  129    shows front views of the guide rails/cage  12900 . For example, the guide rails  12900  can include multiple rods (e.g., four rods) that are arranged in a configuration based on the shape of the front portion of the fiber guide  12408 . If the front portion of the fiber guide  12408  has a square shape, the four rods of the guide rails  12900  can be positioned near the four corners of the front portion of the squared-shaped fiber guide  12408 . In some examples, a guide cage  12912  can be provided to enclose the guide rails  12900 . The guide rails  12900  can also be used without the guide cage  12912 . 
     As described above, in some examples, the CPO module  12316  ( FIG.  123   ) is coupled to spring-loaded elements or compression interposers mounted on the substrate  12310 , and the force required to press the CPO module  12316  into the spring-loaded elements or the compression interposers can be large. The following describes a press plate insert to lock (PPIL) technique that makes it easier to attach and detach the CPO modules. 
     Referring to  FIG.  130   , in some implementations, a compression plate  13000  is used to apply a force to press the CPO module  12316  against a compression socket  13002 , and a U-shaped bolt  13010  is used to fasten the compression plate  13000  to a front lattice structure  13008 . An example of the compression plate  13000  is shown in  FIG.  131   , an example of the U-shaped bolt is shown in  FIG.  132   , and an example of the front lattice structure  13008  is shown in  FIGS.  134  and  135   . For example, the compression socket  13002  is mounted on a substrate  12310 , and the compression socket  13002  includes compression interposers. The CPO module  12316  includes a photonic integrated circuit  13004  that is mounted on a substrate  13006 . For example, the photonic integrated circuit  13004  can be similar to the photonic integrated circuit  214  ( FIG.  2  to  5   ),  450 , or  464  ( FIG.  17   ), and the substrate  13006  can be similar to the substrate  211  ( FIG.  2  to  5   ) or  454  ( FIG.  17   ). The bottom side of the substrate  13006  includes electrical contacts that are electrically coupled to electrical contacts in the compression socket  13002 . 
     The front lattice structure  13008  is attached to the substrate  12310 , and the U-shaped bolt  13010  is inserted into holes in the sidewalls of the front lattice structure  13008  and holes in the compression plate  13000  to secure the compression plate  13000  in place relative to the front lattice structure  13008 . In this example, the front lattice structure  13008  includes a first sidewall  13008   a  and a second sidewall  13008   b . The first sidewall  13008   a  includes two through-holes. As shown in the example of  FIG.  135 B , the second sidewall  13008   b  includes two partial-through-holes that do not entirely pass through the second sidewall  13008   b . This allows another CPO module to be inserted in the space to the right of the second sidewall  13008   b , and another U-shaped bolt  13010   b  to secure the other CPO module to the sidewalls of the front lattice structure  13008 . In this example, the U-shaped bolt  13010   a  is inserted from the left of the first sidewall  13008   a , through the two through-holes in the first sidewall  13008   a , through the two through-holes in the compression plate  13000 , and into the two partial-through-holes in the second sidewall  13008   b  of the front lattice structure  13008 . 
     Alternatively, as shown in the example of  FIG.  135 C , the second sidewall  13008   b  can include full through-holes and the U-shaped bolt  13010   a  can completely pass through the second sidewall  13008   b . A second CPO module can be inserted in the space to the right of the second sidewall  13008   b  using another U-shaped bolt  13010   b  to secure the second CPO module to the sidewalls of the front lattice structure  13008 . In this example, the through-holes in the second sidewall  13008   b  for securing the second CPO module can be laterally offset from the through-holes in the second sidewall  13008   b  securing the first CPO module. 
     In some implementations, a wave spring  13012  is positioned between the compression plate  13000  and the CPO module  12316  to distribute the compression load to the CPO module  12316 . A groove can be cut on the bottom side of the compression plate  13000  to prevent the wave spring  13012  from sliding around on the top surface of the outer shell of the photonic integrated circuit  13004  during assembly. An example of the wave spring  13012  is shown in  FIG.  133   . The wave spring  13012  can also provide tolerance in the positioning and dimensions of the CPO module  12316 . 
     Referring to  FIG.  130   , in some implementation, a thermal bridge  13007  is positioned between the compression plate  13000  and the CPO module  12316  to dissipate heat from the CPO module  12316  and other related components, e.g., a photonic integrated circuit  13004 . The thermal bridge  13007  may include a series of interleaved parallel plates with integrated mechanical springs that compress the interleaved parallel plates to conform between a heat sink (e.g., compression plate  13000 ) and a heat source (e.g., CPO module  12316 ). In some implementations, the thermal bridge  13007  includes a thermal pad formed of compressible material (e.g., a block of single material, a composite at least one material) and a bridge with vertically aligned teeth to allow the teeth to move in the vertical direction (e.g., to close) against the thermal pad and compress the bridge into an effective shape to reduce heat dissipation. 
       FIG.  131    is a diagram of an example of the compression plate  13000 . The compression plate  13000  can be made of a stiff material, e.g., steel, titanium, copper, or brass. The compression plate  13000  defines an opening  13100  to allow an optical fiber cable to pass through and be connected to the CPO module  12316 . The compression plate  13000  defines two through-holes  13102   a  and  13102   b  (collectively referenced as  13102 ) that allow two arms of the U-shaped bolt  13010  to pass through. In this figure, the through-holes  13102  are not drawn to scale. The hole diameter is configured to be smaller than the plate thickness. The compression plate  13000  can be made relatively thick (e.g., 1 mm to 5 mm) to enhance rigidity. 
       FIG.  132    is a diagram of an example of the U-shaped bolt  13010 . The U-shaped bolt  13010  can be made of, e.g., stainless steel, titanium, copper, or brass, and includes two arms  13200   a  and  13200   b  (collectively referenced as  13200 ) that can be inserted into the through-holes and partial-through-holes in the sidewalls  13008   a ,  13008   b  of the front lattice structure  13008 , and the through-holes  13102   a  and  13102   b  in the compression plate  13000  to lock the compression plate  13000  in place. The U-shaped bolt  13010  can have a one-piece design, e.g., made by bending an elongated thin rod to the required shape. 
       FIG.  133    is a diagram of an example of the wave spring  13012 . The wave spring  13012  can also have other configurations. 
       FIG.  134    is a perspective view of an example of the front lattice structure  13008 .  FIG.  135    is a top view of a portion of the front lattice structure  13008 . In this example, the front lattice structure  13008  defines a larger opening  13400  near the center region, and several smaller openings  13402  around the larger opening  13400 . When the front lattice structure  13008  is attached to the substrate  12310  as shown in  FIG.  129   , the position of the center opening  13400  corresponds to the position of the data processing chip  12312  on the other side (e.g., rear side) of the substrate  12310 . One or more components can be mounted on the front side of the substrate  12310  to support the data processor chip  12312  on the rear side of the substrate  12310 . For example, the one or more components can include one or more capacitors, one or more filters, and/or one or more power converters. The one or more components have certain thicknesses and protrude through or partially through the opening  13400 . 
     Each of the openings  13402  allows a CPO module  12316  to pass through and be coupled to a corresponding compression socket  13002 . In the example shown in  FIG.  134   , the front lattice structure  13008  defines 32 openings  13402  that allow the insertion of 32 CPO modules  12316 . The dimensions of this configuration support a half width 2U rack with 12 mm square optical module footprint. The openings  13402  are spaced apart at distances to support XSR channel compliance. 
       FIGS.  134 ,  135 A, and  135 B  show an example in which an outer CPO module is locked in place using a compression plate  13000   a  and a U-shaped bolt  13010   a , and an inner CPO module is locked in place using a compression plate  13000   b  and a U-shaped bolt  13010   b  without a lateral offset between the bolts (e.g.,  13010   a ,  13010   b ) and hence requiring partial-through-holes in the portion of the lattice between the CPO modules.  FIG.  135 C  shows an example in which a lateral offset is provided between the bolts and allowing the bolts to pass through complete through-holes in the portion of the lattice between the CPO modules. The term “outer CPO module” refers to a CPO module positioned closer to the outer edges of the front lattice structure  13008 , and the term “inner CPO module” refers to a CPO module positioned closer to the inner edges of the front lattice structure  13008 . 
     In some implementations, instead using a bolt (or clip) having arms that pass through holes in the sidewalls of the front lattice structure  13008  and holes in the compression plate  13000 , a clamp or screws (e.g., spring-loaded screws) can be used to fasten or lock the compression plate  13000  in place relative to the front lattice structure  13008 . 
       FIG.  136    is an exploded front perspective view of an example of an assembly  13600  in a rackmount system  13630 . In some implementations, the assembly  13600  includes the data processing chip  12312  mounted on a substrate  13602 , a printed circuit board  13604 , a front lattice structure  13606 , a rear lattice structure  13608 , and a heat dissipating device  13610 . The printed circuit board  13604  is positioned between the substrate  13602  and the front lattice structure  13606 . The rear lattice structure  13608  is positioned between the substrate  13602  and the heat dissipating device  13610 . The assembly  13600  can be placed in a housing  13634  of the rackmount system  13630 . The housing  13634  has a front panel, and the substrate  13602  has a main surface (e.g., the front surface) that is at an angle in a range from 0 to 45° relative to the plane of the front panel. In some examples, the main surface of the substrate  13602  is substantially parallel to (e.g., in a range from 0 to 5°) relative to the plane of the front panel. 
     As discussed in more detail below in connection with  FIG.  151   , in an alternative embodiment, the printed circuit board  13604  can be positioned between the substrate  13602  and the rear lattice structure  13626 . 
     For example, the printed circuit board  13604  is used to facilitate the provision of electrical power, control signals, and/or data signals to the data processing chip  12312 . The substrate  13602  can be, e.g., a ceramic substrate that is more expensive than a printed circuit board of comparable size, and it may be difficult to cost effectively manufacture the ceramic substrate sufficiently large to accommodate all the necessary connectors. The outer dimensions of the substrate  13602  can be smaller than the outer dimensions of the printed circuit board  13604 . Connectors  13612  can be mounted on the printed circuit board  13604  for receiving electrical power, control signals, and/or data signals. The connectors  13612  can have a size sufficiently large that can be conveniently handled by an operator. For example, the connectors  13612  can be Molex connectors or other types of connectors. The front surface of the substrate  13602  has electrical contacts  13632  that are electrically coupled to electrical contacts on the rear surface of the printed circuit board  13604 . The electrical contacts allow the electrical power, control signals, and/or data signals to be transmitted from the printed circuit board  13604  to the data processing chip  12312  through the substrate  13602 . In some examples, the connectors  13612  are configured to mate with external connectors in a direction parallel to the plane of the printed circuit board  13604 . In some examples, the connectors  13612  are configured to mate with external connectors in a direction perpendicular to the plane of the printed circuit board  13604 , and the signal lines extend in a rearward direction. This can reduce the spaces to the left and to the right of the printed circuit board  13604  that are need to accommodate the signal wires. The connectors  13612  and the signal lines connected to the connectors  13612  can also be used to transmit signals from the data processing chip  12312  to other parts of the system. 
     This construction enables the delivery of power and other signals external to the system, maintaining the ASIC and module attachment directly to the package substrate. The delivery of power and other signals can be achieved through, e.g., land grid arrays, ball grid arrays, pin grid arrays, or sockets on the front side of the package substrate  13602  that connect to the printed circuit board  13604 . The printed circuit board  13604  can include any of the usual printed circuit board components, including the connectors  13612 . The printed circuit board connectors  13612  enable power and signal delivery through the connectors  13612 , which are then transferred to the package substrate  13602 . The package substrate  13602  is preferably attached to the printed circuit board  13604  during assembly and then placed in the rear lattice structure assembly. 
     The front lattice structure  13606  defines several openings  13614  that allow CPO modules  12316  to pass through and be coupled to electrical contacts or sockets  13616  mounted on the front side of the substrate  13602 . The printed circuit board  13604  defines an opening  13618  to allow the CPO modules  12316  to pass through. The front lattice structure  13606  has an overhang  13700  ( FIG.  137   ) that extends through the opening  13618  and is attached to the front side of the substrate  13602 . The front lattice structure  13606  can be made of, e.g., steel or copper. The figure shows that the printed circuit board  13604  defines a single large central opening  13618 , similar to a “picture frame.” In other examples, it is also possible to divide the opening  13618  into two or more smaller openings. 
     Electrical components can be mounted on the front side of the substrate  13602  in a first region occupying approximately the same footprint as the data processing chip  12312 , which is on the rear side of the substrate  13600 . The electrical components support the data processing chip  12312  and can include, e.g., one or more capacitors, one or more filters, and/or one or more power converters. The front lattice structure  13606  defines a larger opening  13620  in the central region that occupies a slightly larger footprint than the first region. The electrical components mounted on the front surface of the substrate  13602  protrude through or partially through the opening  13618  in the printed circuit board  13604 . and protrude through or partially through the opening  13620  in the front lattice structure  13606 . 
     In some implementations, the front lattice structure  13606  can have a configuration similar to that of the front lattice structure  13008  of  FIG.  134   , and the CPO modules  12316  can be pressed by compression plates  13000  against corresponding sockets  13002 . U-shaped bolts  13010  can be used to secure the compression plates  13000  to the sidewalls of the front lattice structure  13606 . 
     The rear lattice structure  13608  defines a central opening  13622  that is slightly larger than the data processing chip  12312 . The data processing chip  12312  protrudes through or partially through the opening  13622  and is thermally coupled to the heat dissipating device  13610 . The rear lattice structure  13608  defines several openings  13624  that generally correspond to the openings  13614  in the front lattice structure  13606 . Electronic components  13702  ( FIG.  137   ) can be mounted on the rear side of the substrate  13602  to support the CPO modules  12316  that are coupled to the front side of the substrate  13612 . The electronic components  13702  can protrude through or partially through the openings  13624  in the rear lattice structure  13608 . The electronic components  13702  can include, e.g., capacitors for power integrity, microcontrollers, and/or separately regulated power supplies that can isolate the optical module power domains. The rear lattice structure  13608  can be made of, e.g., ______. 
     In some implementations, screws  13628  are used to fasten the front lattice structure  13606 , the printed circuit board  13604 , the substrate  13602 , the rear lattice structure  13608 , and the heat dissipating device  13610  together. The rear lattice structure  13608  has lips  13626  that function as a backstop to prevent crushing of the interface (e.g., land grid arrays, pin grid arrays, ball grid arrays, sockets, or other electrical connectors) between the substrate  13602  and the printed circuit board  13604  when force is applied to fasten the front lattice structure  13606 , the printed circuit board  13604 , the substrate  13602 , the rear lattice structure  13608 , and the heat dissipating device  13610  together. In this example, the lips  13626  are formed near the upper and lower edges on the front side of the rear lattice structure  13608 . It is also possible to form the lips  13626  near the right and left edges on the front side of the rear lattice structure  13608 , or at other locations on the front side of the rear lattice structure  13608 . 
       FIG.  137    is an exploded rear perspective view of an example of the assembly  13600 . The front lattice structure  13606  has an overhang  13700  that extends through the opening  13618  in the printed circuit board  13604  and is attached to the front side of the substrate  13602 . The data processing chip  12312  mounted on the rear side of the substrate  13602  extends through or partially through the opening  13622  in the rear lattice structure  13608  and is thermally coupled to the heat dissipating device  13610 . For example, a thermally conductive gel or pad can be positioned between the data processing chip  12312  and the heat dissipating device  13610 . The electronic components  13702  mounted on the rear side of the substrate  13602  extends through or partially through the openings  13624  in the rear lattice structure  13608 . The upper lip  13626  extends over the upper edge of the substrate  13602  and contacts the rear side of the printed circuit board  13604 , and the lower lip  13626  extends under the lower edge of the substrate  13602  and contacts the rear side of the printed circuit board  13604 . 
     In this example, the connectors  13612  include male Molex connectors configured to receive female Molex connectors along a direction parallel to the plane of the printed circuit board  13604 . It is also possible to configure the connectors  13612  to receive connectors along a direction perpendicular to the plane of the printed circuit board  13604  so that the signal lines extend in a rearward direction. 
       FIG.  138    is an exploded top view of an example of the assembly  13600 . In this example, the width of the overhang  13700  of the front lattice structure  13606  is selected to be slightly smaller than that of the opening  13618  of the printed circuit board  13604 . The width of the printed circuit board  13604  can be almost as wide as the inner width of the housing  13634 . The connectors  13612  are positioned near the left and right edges of the printed circuit board  13604  at locations to provide sufficient space to accommodate the signal lines that are connected to the connectors  13612 . The width of the substrate  13602  and the width of the rear lattice structure  13608  are selected so that they fit in the space between the connectors  13612  near the left edge of the printed circuit board  13604  and the connectors  13612  near the right edge of the printed circuit board  13604 . 
       FIG.  139    is an exploded side view of an example of the assembly  13600 . In this example, the height of the overhang  13700  of the front lattice structure  13606  is selected to be slightly smaller than that of the opening  13618  of the printed circuit board  13604 . The height of the printed circuit board  13604  can be almost as tall as the inner height of the housing  13634 . The height of the substrate  13602  is selected so that the substrate  13602  fits in the space between the upper lip  13626  and the lower lip  13626 . 
       FIG.  140    is a front perspective view of an example of the assembly  13600  that has been fastened together. The overhang  13700  of the front lattice structure  13606  contacts the front surface of the substrate  13604 , and the electronic components that support the data processing chip  12312  extend through or partially through the opening  13618  in the printed circuit board  13604  and the opening  13620  in the front lattice structure  13606 . The sidewalls of the front lattice structure  13606  function as guides for aligning the CPO modules  12316  to the sockets  13616  on the front surface of the substrate  13602 . The large printed circuit board  13604  has more surface area to mount connectors  13612  for providing electrical power, control signals, and/or data signals to the data processing chip  12312 . The assembly  13600  is vertically mounted, e.g., the substrate  13602  is substantially vertical with respect to the top or bottom panel of the housing  13634  and substantially parallel to the front panel. The assembly  13600  is positioned near the front panel, e.g., not more than 12 inches from the front panel. The front panel can be opened to allow an operator to easily access the CPO modules  12316 , e.g., to insert or remove the CPO modules  12316  into or from the sockets  13616 . 
       FIG.  141    is a front perspective view of an example of the assembled assembly  13600  without the front lattice structure  13606 . The printed circuit board  13604  is shaped similar to a “picture frame” and the opening  13618  is configured to allow the CPO modules  12316  to be coupled to the sockets  13616 , and to provide space to accommodate the various electronic components mounted on the front side of the substrate  13602  that support the data processing chip  12312  on the rear side of the substrate  13602 . 
       FIG.  142    is a front perspective view of an example of the assembled assembly  13600  without the printed circuit board  13604  and the front lattice structure  13606 . Electrical contacts or sockets  13616  (each socket can include a plurality of electrical contacts) are provided on the front side of the substrate  13602 , in which the electrical contacts or sockets  13616  are configured to be coupled to the CPO modules  12316 . In this example, arrays of electrical contacts  13632  are provided at the left and right regions of the substrate  13602 . For example, power converters can be mounted on the printed circuit board  13604  to receive electric power that has a higher voltage (e.g., 12V or 24V) and a lower current, and output electric power that has a lower voltage (e.g., 1.5V) and a higher current. In some implementations, the data processing chip  12312  can require more than 100 A of peak current during certain periods of time. By providing a large number of electrical contacts  13632 , the overall resistance to the higher current can be made smaller. 
       FIG.  143    is a front perspective view of an example of the assembled rear lattice structure  13608  and the heat dissipating device  13610 . The rear lattice structure  13608  defines an opening  13622  to provide space for the data processing chip  12312  mounted on the rear side of the substrate  13602 . The rear lattice structure  13608  defines openings  13624  to provide space for the components  13702  mounted on the rear side of the substrate  13602 , in which the components support the CPO modules  12316  coupled to the electrical contacts  13616  on the front side of the substrate  13602 . The upper and lower lips  13626  prevent crushing of the interface (e.g., land grid arrays, pin grid arrays, ball grid arrays, sockets, or other electrical connectors) between the substrate  13602  and the printed circuit board  13604  when force is applied to fasten the front lattice structure  13606 , the printed circuit board  13604 , the substrate  13602 , the rear lattice structure  13608 , and the heat dissipating device  13610  together. 
       FIG.  144    is a front perspective view of an example of the heat dissipating device  13610  and the screws  13628 . The heat dissipating device  13610  can include fins that extend in the horizontal direction. For example, an inlet fan (e.g.,  12546  of  FIG.  125   ) blows air in the horizontal direction across the fins to help carry away the heat generated by the data processing chip  12312 . 
       FIG.  145    is a rear perspective view of an example of the assembly  13600  in which the front lattice structure  13606 , the printed circuit board  13604 , the substrate  13602 , the rear lattice structure  13608 , and the heat dissipating device  13610  have been fastened together. The heat dissipating device  13610  as shown in the figure includes horizontal fins, but can also have other configurations, such as having pins or posts, such as those shown in  FIG.  68 C . The heating dissipating device  13610  can include a vapor chamber thermally coupled to the heat sink fins or pins. 
       FIG.  146    is a rear perspective view of an example of the assembly  13600  without the rear lattice structure  13608 . The data processing chip  12312  protrudes through or partially through the opening  13622  in the rear lattice structure  13608 . The components  13702  protrude through or partially through the openings  13624  in the rear lattice structure  13608 . 
       FIG.  147    is a rear perspective view of an example of the front lattice structure  13606 , the printed circuit board  13604 , and the substrate  13602  that have been fastened together.  FIG.  148    is a rear perspective view of an example of the front lattice structure  13606  and the printed circuit board  13604  that have been fastened together. The overhang  13700  of the front lattice structure  13606  extends into the opening  13618  in the printed circuit board  13604 .  FIG.  149    is a rear perspective view of an example of the front lattice structure  13606 . 
     Referring to  FIG.  150   , in some implementations, a data processing chip  15000  is mounted on a substrate (e.g., a ceramic substrate)  15002 , which is electrically coupled to a first side of a printed circuit board  15004 . A CPO module  15006  is mounted on a substrate (e.g., a ceramic substrate)  15008 , which is electrically coupled to a second side of the printed circuit board  15004 . The configuration shown in  FIG.  150    can be used in any of the systems or assemblies described above that includes a data processing chip communicating with one or more CPO modules. 
       FIG.  151    shows, in the right portion of the figure, a top view of an example of an assembly  15100 , suitable for use in a rackmount system, that includes a vertical printed circuit board  13604  (e.g., a daughter card) that is positioned between a package substrate  13602  (also referred to as a CPO substrate) and a rear lattice structure  13626 . The package substrate  13602  is positioned between the printed circuit board  13604  and a front lattice structure  13606 . In this example, each CPO module  12316  is removably attached to a high-speed LGA socket  15104  that is mounted on the front side of the package substrate  13602 . The data processing chip  13612  (which in this example is a switch ASIC) is mounted on the rear side of the package substrate  13602 . The high-speed LGA socket  15104  is electrically coupled to high-speed LGA pads  15106  on the front surface of the package substrate  13602 . High speed traces  15102  within the package substrate  13602  provides high speed signal connections between the CPO modules  12316  and the data processing chip  13612 . 
     In this example, the printed circuit board  13604  defines an opening that allows the data processing chip  13612  to pass through to be thermally coupled to a heat dissipating device  13610 . The printed circuit board  13604  is a “picture frame” with a cut-out for the switch ASIC  13612 . The package substrate  13602  has power and low-speed contact pads  15108  on the rear side for attaching to the vertical printed circuit board  13604  (the “picture frame” daughter card) for receiving electrical power and low-speed control signals from the printed circuit board  13604 . The power and low-speed contact pads  15108  are relatively large (e.g., about 1 mm), as compared to the high-speed LGA pads  15106 . The power and low-speed contact pads  15108  is positioned between the CPO substrate  13602  and the printed circuit board  13604 , and do not impact the mounting of the heat sink  13610  to the data processing chip  13612 . 
     In some implementations, the printed circuit board  13604  defines an opening that is large enough to accommodate the data processor (e.g., switch ASIC)  13612  and additional components that are mounted on the rear side of the substrate  13602 , in which the additional components support the CPO modules  12316 . The additional components can include, e.g., one or more capacitors, filters, power converters, or voltage regulators. In some examples, instead of having one large opening, the printed circuit board  13604  can define multiple openings that are positioned to allow the data processor  13612  and the additional components to protrude through or partially through. 
       FIG.  151    shows, in the left portion of the figure, a perspective rear view of the package substrate  13602 , the CPO module  12316 , and compression plates  15110 . As shown in this diagram, in some implementations, there can be a large number (e.g., several hundred or thousand) of power and low-speed contact pads  15108  to allow routing of a large amount of power to the data processing chip  13612  and the CPO modules  12316 . In this example, each compression plate  15110  has an integrated heat sink  15112  for dissipating the heat generated by the CPO module  12316 . 
     Referring to  FIG.  152   , in some implementations, the CPO modules  12316  can easily be removed from the package substrate  13602  for replacement or repair. For example, a fiber connector is attached to the CPO module  12316 , which is attached to the LGA socket  15104 , which is removably attached to the package substrate  13602 . The compression plate  15110  presses down on the CPO module  12316  and is secured relative to the front and rear lattice structures  13606 ,  13626  using the U-shaped bolts  13010  and spring-loaded screws  15200 . The compression plate  15110  can have a latch for latching the fiber connector  12318 . If a CPO module  12316  malfunctions, the technician and remove the screws  15200 , remove the U-shaped bolts  13010 , and detach the CPO module  12316  from the LGA socket  15104 , or detach the LGA socket from the package substrate  13602 . 
       FIG.  153    is a diagram showing an example of a process  15300  for assembling the assembly  15100 . The front lattice structure  13606  is attached  15302  to the CPO substrate  13602 , and the CPO substrate  13602  is attached  15304  to the printed circuit board  13604 . The heat sink  13610  is thermally coupled to the data processing chip  13612 . This diagram shows the front side of the CPO substrate  13602 , the data processing chip  13612  is mounted on the other side of the CPO substrate  13602  and not shown in the figure. The diagram  15306  shows the assembly  15100  ready for insertion of the CPO modules  12316 . The diagram  15308  shows CPO modules  12316  with compression plates  15110  inserted into the front lattice structure  13606 , and before attachment of the optical fibers. 
       FIG.  154    is a diagram showing an example of a CPO module  12316  having a lid  15400  to protect the CPO module  12316 . Also shown is a compression plate  15110  with an integrated heat sink  15112 . In this example, screws  15402  are used to secure the compression plate  15110  to the front lattice structure  13606  and/or the package substrate  13602  and/or the vertical printed circuit board  13604  and/or the rear lattice structure  13626 . 
       FIG.  155 A  is a rear perspective view of an example of the LGA socket  15104 , the optical module  12316 , and the compression plate  15110 .  FIG.  155 B  is a front perspective view of an example of the LGA socket  15104 , the optical module  12316 , and the compression plate  15110 . In  FIGS.  155 A and  155 B , the LGA socket  15104  has been inserted into the front lattice structure  13606 , ready for insertion or attachment of the optical module  12316  and the compression plate  15110 . 
       FIG.  156    is a front view (assuming the printed circuit board  13604  is vertically mounted in a rackmount server) of an example of an array of compression plates  15110  mounted on the front lattice structure  13606 . The front lattice structure  13606  includes an opening  13400  for placing components that support the data processor chip  12312  on the rear side of the substrate  12310 . For example, the one or more components can include one or more decoupling capacitors, one or more filters, and/or one or more voltage regulators, if needed. The one or more components have certain thicknesses and protrude through or partially through the opening  13400 . 
       FIG.  157    is a front perspective view of an example of the assembly  15100 . Several CPO modules  12316  with lids  15400  are mounted on the front side of the package substrate  13602 . The CPO modules  12316  are pressed against the package substrate  13602  by compression plates  15110  having integrated heat sinks  15112 . 
       FIG.  158    is a top view of an example of the assembly  15100 . The switch ASIC  13612  is mounted on the rear side of the package substrate  13602 . Several CPO modules  12316  with lids  15400  are mounted on the front side of the package substrate  13602 . The CPO modules  12316  are pressed against the package substrate  13602  by compression plates  15110  having integrated heat sinks  15112 . 
       FIGS.  156  to  158    show compression plates  15110  on top of (or in front of) the optical modules  12316  showing the fiber connector receptacles. Under the compression plates is a baseplate (which is referred to as the lattice or honeycomb structure) that is mounted with screws through the system printed circuit board  13602  to the rear lattice  13626  or ASIC heatsink  13610  on the backside. In addition, or alternatively, a clip-based or bolt-based design similar to the design shown in  FIGS.  130  to  135 C  can be used to secure the compression plates  15110  to the front lattice structure  13606 . 
       FIG.  136    is an exploded front perspective view of an example of an assembly  13600  in a rackmount system  13630 . In some implementations, the assembly  13600  includes the data processing chip  12312  mounted on a substrate  13602 , a printed circuit board  13604 , a front lattice structure  13606 , a rear lattice structure  13608 , and a heat dissipating device  13610 . The printed circuit board  13604  is positioned between the substrate  13602  and the front lattice structure  13606 . The rear lattice structure  13608  is positioned between the substrate  13602  and the heat dissipating device  13610 . The assembly  13600  can be placed in a housing  13634  of the rackmount system  13630 . The housing  13634  has a front panel, and the substrate  13602  has a main surface (e.g., the front surface) that is at an angle in a range from 0 to 45° relative to the plane of the front panel. In some examples, the main surface of the substrate  13602  is substantially parallel to (e.g., in a range from 0 to 5°) relative to the plane of the front panel. 
     While this disclosure includes references to illustrative embodiments, this specification is not intended to be construed in a limiting sense. Various modifications of the described embodiments, as well as other embodiments within the scope of the disclosure, which are apparent to persons skilled in the art to which the disclosure pertains are deemed to lie within the principle and scope of the disclosure, e.g., as expressed in the following claims. 
     Some embodiments can be implemented as circuit-based processes, including possible implementation on a single integrated circuit. 
     Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value or range. 
     It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this disclosure can be made by those skilled in the art without departing from the scope of the disclosure, e.g., as expressed in the following claims. 
     The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures. 
     Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence. 
     Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the disclosure. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.” 
     Unless otherwise specified herein, the use of the ordinal adjectives “first,” “second,” “third,” etc., to refer to an object of a plurality of like objects merely indicates that different instances of such like objects are being referred to, and is not intended to imply that the like objects so referred-to have to be in a corresponding order or sequence, either temporally, spatially, in ranking, or in any other manner. 
     Also for purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements. 
     As used herein in reference to an element and a standard, the term compatible means that the element communicates with other elements in a manner wholly or partially specified by the standard, and would be recognized by other elements as sufficiently capable of communicating with the other elements in the manner specified by the standard. The compatible element does not need to operate internally in a manner specified by the standard. 
     The described embodiments are to be considered in all respects as only illustrative and not restrictive. In particular, the scope of the disclosure is indicated by the appended claims rather than by the description and figures herein. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope. 
     The description and drawings merely illustrate the principles of the disclosure. It will thus be appreciated that those of ordinary skill in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the disclosure and are included within its spirit and scope. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof. 
     The functions of the various elements shown in the figures, including any functional blocks labeled or referred to as “processors” and/or “controllers,” can be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions can be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which can be shared. Moreover, explicit use of the term “processor” or “controller” should not be construed to refer exclusively to hardware capable of executing software, and can implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage. Other hardware, conventional and/or custom, can also be included. Similarly, any switches shown in the figures are conceptual only. Their function can be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context. 
     As used in this application, the term “circuitry” can refer to one or more or all of the following: (a) hardware-only circuit implementations (such as implementations in only analog and/or digital circuitry); (b) combinations of hardware circuits and software, such as (as applicable): (i) a combination of analog and/or digital hardware circuit(s) with software/firmware and (ii) any portions of hardware processor(s) with software (including digital signal processor(s)), software, and memory(ies) that work together to cause an apparatus, such as a mobile phone or server, to perform various functions); and (c) hardware circuit(s) and or processor(s), such as a microprocessor(s) or a portion of a microprocessor(s), that requires software (e.g., firmware) for operation, but the software does not need to be present when it is not needed for operation.” This definition of circuitry applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the term circuitry also covers an implementation of merely a hardware circuit or processor (or multiple processors) or portion of a hardware circuit or processor and its (or their) accompanying software and/or firmware. The term circuitry also covers, for example and if applicable to the particular claim element, a baseband integrated circuit or processor integrated circuit for a mobile device or a similar integrated circuit in server, a cellular network device, or other computing or network device. 
     It should be appreciated by those of ordinary skill in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the disclosure.