Patent Publication Number: US-7898321-B2

Title: Driver circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to Japanese Patent Application Ser. No. 2008-027120, entitled “Driver Circuit,” filed on Feb. 7, 2008, which is hereby incorporated by reference for all purposes. 
     TECHNICAL FIELD 
     The invention relates generally to driver circuitry and, more particularly, to driver circuitry for light emitting elements. 
     BACKGROUND 
     In recent years, applications in which LEDs or light-emitting diodes are used have become popular. Accompanying this trend, a number of LED driver ICs or integrated circuits have been used in to control the LEDs. An example of a convention LED driver is shown in  FIG. 1 , and a timing diagram corresponding to the general operation of the convention LED drive of  FIG. 1  is shown in  FIG. 2 . Now, turning to  FIG. 1 , the reference numeral  100  generally designates the conventional LED driver. LED driver  100  is generally comprised of current source  102 , amplifier  102 , and transistors N 1  through N 4  (NMOS FETs) and P 1  (PMOS FET). 
     In operation, transistors N 1  and N 2  operate as a current mirror circuit so that when reference current Iref flows through transistor N 2 , the mirror current also flows through transistor N 1 , forming output current Io. If transistor 1  N 2  and N 1  have the same general structure and the size ratio (generally, 1:n), output current Io will be determined by the following equation: 1o=n*Iref. In principle, a constant current can be obtained; however, in practice, the output current Io will vary with changes in the output voltage due to the Early effect, which is undesirable. 
     One way of reducing this variation in the output current due to the Early effect is to employ the configuration of transistors N 1  and N 5 , which are cascade-connected. Here, transistor N 5  operates to suppress variations in the output current despite variations in the output voltage. To accomplish this, amplifier  104  is used to control the transistor N 5 , where the non-inverting input terminal of amplifier  104  is connected to the gate electrode of transistor N 2  that sets reference current Iref and where the inverting input terminal of amplifier  104  is connected to the source terminal of output transistor N 5  on the upper side of the cascade connection. Additionally, the output of amplifier  104  is connected to the gate terminal of transistor N 5 . Amplifier  104  operates to generally ensure that the voltage at the non-inverting input terminal and voltage at the inverting input terminal (the drain voltage of transistor N 5 ) are generally the same. As a result, the gate and drain voltages of transistors N 2  and N 1 , which form a current mirror circuit are the same, so that the circuit operation is unaffected by changes in the output voltage. Thus, amplifier  104  operates as a negative feedback circuit, and the gate potential of output transistor N 5  is controlled corresponding to variations in the output voltage, so that the output current can be kept constant. 
     Now turning to  FIG. 2 , a timing diagram of the operation of the driver  100  is shown. At time t 1 , control signal transitions to from logic high to logic low. At time t 1 , the voltage at node s 1  remains at logic high, while the voltage at node s 2  transitions to logic high and the voltage at node s 3  transitions to logic low. This results in the voltage at node s 4  having to increase between times t 1  and t 2 . Thus, the output current is not constant during the period from time t 1  to t 2 . Therefore, there is a need for a circuit that provides a generally constant output current. 
     SUMMARY 
     A preferred embodiment of the present invention, accordingly, provides an apparatus. The apparatus comprises a current source that is adapted to provide a reference current; a current mirror that is coupled to the current source; a transistor that is coupled to the current mirror; an amplifier having a first input, a second input, and an output, wherein the first input of the amplifier is coupled to the current mirror, and wherein the second input of the amplifier is coupled to a node between the transistor and the current mirror, and wherein the output of the amplifier is coupled to the control electrode of the transistor; and a presetting circuit that is coupled to the control electrode of the transistor, wherein the presetting circuit presets the potential of the control electrode of the transistor to a level that allows current driving of the transistor with a predetermined timing after a control signal is received. 
     In accordance with a preferred embodiment of the present invention, the presetting circuit further comprises a delay circuit that is adapted to receive the control signal; logic that is coupled to the delay circuit; a current generating circuit that is coupled to the logic; and a second transistor that is coupled between the current generating circuit and the control electrode of the first transistor and that is coupled the logic at its control electrode. 
     In accordance with a preferred embodiment of the present invention, the current generating circuit further comprises a third transistor that is coupled to the logic at its control electrode; a second current mirror that is coupled to the third transistor; a third current mirror that is coupled to the second current mirror; and a fourth transistor that is coupled to the third current mirror. 
     In accordance with a preferred embodiment of the present invention, the current generating circuit further comprises a third transistor that is coupled to the logic at its control electrode; a second current mirror that is coupled to the third transistor; a fourth transistor that is coupled to the second current mirror, wherein the fourth transistor is diode-connected; a fifth transistor that is coupled to the fourth transistor; a sixth transistor that is coupled to the second current mirror; a seventh transistor that is coupled to the second current mirror and the sixth transistor, wherein the seventh transistor is diode connected; a eighth transistor that is coupled to the second current mirror, the sixth transistor, and the seventh transistor; and a ninth transistor that is coupled to the eighth transistor and the first terminal of the amplifier. 
     In accordance with a preferred embodiment of the present invention, the logic further comprises a NAND gate that is coupled to the delay circuit; and an inverter that is coupled to the NAND gate. 
     In accordance with a preferred embodiment of the present invention, the delay further comprises a first inverter that is adapted to receive the control signal; and a second inverter that is coupled to the first inverter. 
     In accordance with a preferred embodiment of the present invention, the apparatus further comprises a control circuit that is coupled to the current mirror and the transistor, wherein the control circuit is adapted to receive the control signal. 
     In accordance with a preferred embodiment of the present invention, the control circuit further comprise a second transistor that is coupled between the current mirror and ground and that is adapted to receive the control signal at its control electrode; and a third transistor that is coupled between the output of the amplifier and the current mirror. 
     In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a current source that is adapted to provide a reference current; a current mirror that is coupled to the current source; a first transistor that is coupled to the current mirror; an amplifier having a first input, a second input, and an output, wherein the first input of the amplifier is coupled to the current mirror, and wherein the second input of the amplifier is coupled to a node between the first transistor and the current mirror, and wherein the output of the amplifier is coupled to the control electrode of the first transistor; an control circuit that is coupled to the current mirror and to the control electrode of the first transistor, wherein the control circuit is adapted to receive a control signal; a delay circuit that is coupled to the control circuit and that is adapted to receive the control signal; logic that is coupled to the delay circuit; a current generating circuit that is coupled to the logic; and a second transistor that is coupled between the current generating circuit and the control electrode of the first transistor and that is coupled the logic at its control electrode. 
     In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a current source that is adapted to provide a reference current; a first FET that is coupled to the current source at its drain, wherein the first FET is diode-connected; a second FET that is coupled to the gate of the first transistor at its gate; a third FET that is coupled to the drain of the second FET at its source and that is adapted to be coupled to an light-emitting diode at its source; an amplifier having a first input, a second input, and an output, wherein the first input of the amplifier is coupled to the gate of the first FET, and wherein the second input of the amplifier is coupled to the source of the second FET, and wherein the output of the amplifier is coupled to the gate of the third FET; an control circuit that is coupled to the gates of the second and third FETs, wherein the control circuit is adapted to receive a control signal; a delay circuit that is coupled to the control circuit and that is adapted to receive the control signal; logic that is coupled to the delay circuit; and a current generating circuit that is coupled to the logic; and a second transistor that is coupled between the current generating circuit and the control electrode of the first transistor and that is coupled the logic at its control electrode. 
     In accordance with a preferred embodiment of the present invention, the control circuit further comprises a fourth FET that is coupled between the gate of the second FET and ground and that is adapted to receive the control signal at its gate; a fifth FET that is coupled between the gate and source of the third FET and that is adapted to receive the control signal at its gate; and a sixth FET that is coupled between the gates of the first and second FET and that is adapted to receive the control signal at its gate. 
     The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a circuit diagram of a conventional driver; 
         FIG. 2  is a timing diagram of the operation of the driver of  FIG. 1 ; 
         FIG. 3  is a circuit diagram for a driver in accordance with a preferred embodiment of the present invention; 
         FIG. 4  is a timing diagram of the operation of the driver of  FIG. 3 ; and 
         FIG. 5  is a circuit diagram for a driver in accordance with a preferred embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. 
     Referring to  FIG. 3  of the drawings, the reference numeral  300  generally designates an LED driver circuit in accordance with a preferred embodiment of the present invention. The driver  300  generally comprises an output circuit or section  302  and a presetting circuit  304 . Preferably, the presetting circuit  304  comprises a delay circuit  306 , logic  308 , and a current generating circuit  310 , while the output circuit  302  is generally comprised of transistors Q 1  through Q 6  and amplifier  312 . 
     In output circuit  302 , transistors Q 1  and Q 2  (preferably NMOS FETs) operate to generally provide the output current Io. Preferably, the source of transistor Q 2  is coupled to ground (or reference potential Vss), and the drain is coupled to the source of transistor Q 1  at node s 4 . Output terminal TO is generally formed at the drain of transistor Q 1 , and the cathode of the LED D 1  (as the load) is coupled to output terminal TO. Here, one or more LEDs are connected in series between the drain of transistor Q 1  and the power supply voltage VDD (e.g., 17 V). 
     Additionally, the gate of transistor Q 2  is preferably coupled to the drain of transistor Q 4  (preferably a PMOS FET) at node s 2 , and diode-connected transistor Q 6  (preferably an NMOS FET) is coupled to the source of transistor Q 4  at its gate. A current source  314  is preferably coupled to the drain of transistor Q 6 , while the source is preferably coupled to ground. Additionally, transistor Q 5  is preferably coupled between node s 2  and ground. In this configuration, transistor Q 4  operates as an active low switch (and a portion of the control circuit that is actuated when the control signal OE is logic low), and transistor Q 5  operates as an active high switch (and a portion of the control circuit that is actuated when the control signal OE is logic high). Each of transistors Q 4  and Q 5  allows the gates of transistors Q 6  and Q 2  to be coupled to one another so as to form a current mirror. 
     The amplifier  312  is preferably coupled to node s 4  at its inverting input terminal and to node s 1  at its non-inverting terminal. The output terminal of amplifier  312  is preferably coupled to the gate of transistor Q 1 , and transistor Q 3  (preferably an NMOS FET) is coupled between nodes s 3  and s 4 . Amplifier  312  generally provides feedback to transistor Q 1 , while transistor Q 3  operates as a switch (and a portion of the control circuit) that is actuated by the control signal OE. 
     The presetting circuit  304  is also preferably coupled to the output circuit  302  to generally presets the potential or voltage of the gate of the transistor Q 1  to a potential or voltage that allows current driving of transistor Q 1  with a predetermined timing after a control signal OE is received. To accomplish this, delay circuit  306  receives the control signal OE. The logic  308  is preferably coupled the delay circuit  306  and is preferably coupled to the current generating circuit  310 . 
     Preferably, the delay circuit  306  is comprised of inverters  316  and  318 , resistor R and capacitor C. Inverter  316  is preferably CMOS inverter that is generally comprised of transistor Q 7  (preferably an NMOS FET) and transistor Q 8  (preferably PMOS FET). Inverter  318  (which is generally coupled to the inverter  316  at node s 5 ) is preferably a CMOS inverter that is generally comprised of transistor Q 10  (preferably an NMOS FET) and transistor Q 9  (preferably PMOS FET). Resistor R is generally coupled to inverter  318  at node s 6 , and capacitor C is generally coupled between node s 9  and ground. Resistor R and capacitor C form time constant circuit or RC time constant circuit, which has the function of delaying for a predetermined time the transfer of the output level of inverter  318  to the next stage. 
     Logic  308  is generally comprised of NAND gate  320  and inverter  322 . NAND gate is preferably a CMOS NAND gate that is generally comprised of transistors Q 11  and Q 12  (preferably PMOS FETs) and transistors Q 13  and Q 14  (preferably NMOS FETs). Inverter  316  is preferably CMOS inverter that is generally comprised of transistor Q 16  (preferably an NMOS FET) and transistor Q 15  (preferably PMOS FET). NAND gate  320  is generally coupled to delay circuit at node s 9  and generally coupled to inverter  322  at node s 8 . 
     Preferably, coupled to logic  308  is the current generating circuit  310 . Circuit generating circuit is generally comprised of transistors Q 20  through Q 23  (preferably PMOS FETs), transistors Q 17  through Q 19  (preferably an NMOS transistors). Preferably, transistor Q 23  is coupled between power supply Vcc and transistors Q 20  and Q 21  (arranged as a current mirror, while transistor Q 17  is coupled between ground and transistors Q 18  and Q 19  (arranged as a current mirror). Additionally, the gate of transistor Q 17  is preferably coupled to node s 8 , and the gate of transistor Q 23  is coupled to node s 8 . Transistor Q 22  is preferably coupled between nodes s 10  and s 3 , while its gate is preferably coupled to node s 7 . Thus, current generating circuit  310  is able to provide a generally constant current with a clamping function. 
     Now turning to  FIG. 4  of the drawings, a timing diagram for the operation of the driver  300  can be seen. At time t 1 , control signal OE transitions from logic high to logic low at time turning off transistors Q 3  and Q 5  and turning on transistor Q 4 . Thus, node s 1  remains at logic high and nodes s 2 , s 3 , and s 5  transition to logic high. The voltage at node s 9  also begins to decay as capacitor C is charged. During the decay, the voltage at node s 9  decreases to a point at time t 2  to cause NAND gate  320  to transition node s 7  (which is the pre-control signal for transistor Q 22 ) from logic high to logic low. This allows the voltage at node s 4  and the output current Io to remain generally constant by using transistor Q 22  and current mirrors Q 18 , Q 19 , Q 20 , and Q 21  to provide a supplementary charge to the gate of transistor Q 1 . Thus, it is clear that amplifier  312  is able to charge the gate of transistor Q 1  to the desired gate potential or voltage quickly, so that it is possible to reduce the delay time and to make it possible for the transient response characteristics to be reached quickly. 
     As can be seen, resistor R and capacitor C determined the time constant (RC) for the delay  306 . This delay time is set so that it is generally equal to the time required for amplifier  312  to charge the gate of transistor Q 22 . For example, it is set corresponding to the transient response characteristics of the amplifier  312 . 
     Now turning to  FIG. 5 , another example configuration of the LED driver  500  can be seen. Generally, driver  500  has a similar structure to that of driver  300 , namely in the output circuit  302 , the delay circuit  306 , logic  308 , and transistor Q 22 . A difference between driver  300  and driver  500  is generally in the configuration of the current generating circuit. A reason for this difference is that, when the gate of transistor Q 1  is charged via transistor Q 22 , there may exist a variation in the gate potential due to the supplementary charging. Also, because the charge current is high, the current from the current mirror itself should be increased, so that it is necessary to increase the current not needed for charging although it is transient. 
     Circuit  510  generally comprises transistors Q 17 , Q 23 , Q 20 , Q 21 , and Q 25  through Q 29 . Transistor Q 23  is preferably coupled to current mirror (transistors Q 20  and Q 21 ). Transistor Q 20  is preferably coupled to diode-connect transistor Q 25  (preferably an NMOS FET), which is preferably coupled to transistor Q 17 . Transistor Q 21  is preferably coupled to transistors Q 29  (preferably a NMOS FET), diode-connected transistor Q 27  (preferably a PMOS FET), and transistor Q 26  (preferably an NMOS FET). Additionally, transistor Q 28  (preferably a PMOS FET) is preferably coupled to transistor Q 27 . 
     To increase the driving ability of circuit  510  (as compared to circuit  310 ), the drain of transistor Q 29  is coupled to supply Vcc. The gate of transistor Q 28  is connected to the non-inverting input terminal of amplifier  312 . The potential of the non-inverting input terminal is at the same potential that of node s 4 . The potential of the source of transistor Q 27  is represented as the voltage at node s 4  (V s4 ) plus the threshold voltage of transistor Q 28  (V TH1 ) plus the threshold voltage of transistor Q 27  (V TH2 ). This potential at node s 12  becomes the gate potential of transistor Q 29 . The current driven by transistor Q 29  flows through transistor Q 22  to charge the gate of transistor Q 1 . In this case, the gate potential of charged transistor Q 1  is the potential obtained by subtracting threshold voltage of transistor Q 29  (V TH3 ) from the gate potential of transistor Q 29 . Consequently, gate potential at node s 3  can be determined by the following equation:
 
V s3 =V s4 +V TH1 +V TH2 −V TH3   (1)
 
Here, if the threshold voltages are equal (V TH1 =V TH2 =V TH3 =V T , equation 2 can be reduced as follows:
 
V s3 =V s4 +V T   (2)
 
This is the potential obtained by adding the threshold voltage of transistor Q 1  to source voltage Vs 4  of output transistor Q 1 , and it is the originally desired gate potential. Thus, the circuit is such that the gate potential that is supplementarily charged is independent of variations in the power supply voltage.
 
     Also, when there is a demand to increase the charging current, by increasing the size of transistor Q 29  driven as a source-follower, it is possible to improve the current driving ability without increasing the bias current of circuit  510 . 
     Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.