Patent Publication Number: US-6214229-B1

Title: Treatment system for removing phosphorus

Description:
BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming mask read-only memory (ROM) devices in the manufacture of integrated circuit devices. 
     (2) Description of the Prior Art 
     Mask read-only memory (ROM) devices are memory arrays where the contents are permanently hard coded. Mask ROM is used, for example, for core or boot-up programming in microcomputer systems. Though the contents of the memory array cannot be altered, the mask ROM integrated circuit can be produced for less money than a comparably sized programmable device, such as electrically erasable programmable ROM (EEPROM). In addition, the data in a mask ROM is typically less prone to data errors resulting from programming problems or data loss due to environmental conditions. 
     The key technology in the mask ROM is typically the MOS transistor. Each cell in the mask ROM array is comprised of a MOS transistor. Each transistor has been pre-programmed to a given state during the manufacturing process. The state of the transistor, either logical “0” or “1,” is determined by the fixed threshold voltage of the transistor. 
     Referring now to FIG. 1, a cross sectional representation of a prior art integrated circuit device is illustrated. The cross section shows a partially completed mask ROM device of the prior art. A semiconductor substrate  10  is shown. Field oxide (FOX) regions  14  have been defined in the semiconductor substrate  10 . The active device area for the mask ROM is the area of the substrate  10  between the field oxide regions  14 . A sacrificial oxide layer  18  has been formed overlying the semiconductor substrate  10 . 
     In the typical prior art process, a coding implantation  26  is performed at this part of the mask ROM process. In the coding implantation  26 , doping ions are implanted into the semiconductor substrate  10  where defined by the coding mask  22 . The coding implantation  26  will alter the voltage threshold (V t ) of the completed MOS transistor by creating a coding threshold region  30  near the surface of the semiconductor substrate  10  where the doping concentration is either greater or lesser than the comparable region in non-implanted devices. 
     A typical mask ROM scenario could be the assignment of a logical “1” to transistors with high V t  and a logical “0” to transistors with low V t . If the ion implantation used in the coding implant will cause the V t  to increase, then the mask used to pattern the photoresist  22  will have openings only overlying logical “1” transistors. 
     Referring now to FIG. 2, after the coding implantation, the sacrificial oxide layer  18  is removed. A gate oxide layer  32  is formed overlying the semiconductor substrate  10 . A polysilicon layer  38  is deposited overlying the gate oxide layer  32 . The polysilicon layer  38  and the gate oxide layer  32  are then patterned to form the gate electrode  38  for the mask ROM device. Additional processing steps for forming lightly doped drains, sidewall spacers , and source and drain junctions, would also occur but are not illustrated here. 
     Note that the coding implantation occurs relatively early in the mask ROM manufacturing sequence. This is an important observation. The data contents, often a microcomputer program, are permanently encoded into the mask ROM as soon as the coding implant is performed. If the designers of the mask ROM application require a programming change after the integrated circuit or circuit batch has passed the coding implantation, it is too late. The circuits either must be used as they were originally coded, or they must be scrapped. In practice, code changes are a common occurrence. Preferably, the coding process step would be as late in the processing sequence as possible. A relatively later coding step in the process helps to prevent scrap, provides better service to the applications customer, and increases the economic viability of the mask ROM manufacturer. 
     Several prior art approaches disclose methods to form mask ROM devices in the manufacture of an integrated circuit device. U.S. Pat. No. 5,378,647 to Hong discloses a method to form a mask ROM device using polysilicon bit lines and a back gate construction. The bit pattern is formed by selective removal of the polysilicon layer. U.S. Pat. No. 5,589,414 to Wann et al discloses a prior art method to code a mask ROM by selectively implanting the channel area through the polysilicon gate. Photoresist is used to protect non-implanted gates and source and drain regions. This invention also teaches a method to code a mask ROM where a thin first polysilicon gate layer is formed. The code implant is performed through the thin polysilicon gate. The second polysilicon layer is deposited, and the transistor is completed. U.S. Pat. No. 5,751,040 to Chen et al teaches a process to form a mask ROM device with a vertical channel. U.S. Pat. No. 5,831,314 to Wen discloses a process to form a trench-shaped ROM device. 
     SUMMARY OF THE INVENTION 
     A principal object of the present invention is to provide an effective and very manufacturable method of forming mask read-only memory (ROM) devices in the manufacture of integrated circuits. 
     A further object of the present invention is to provide a method to code mask ROM devices later in the processing sequence. 
     Another further object of the present invention is to provide a method to code mask ROM devices by ion implantation after formation of the gate electrode and the source and drain regions. 
     Another further object of the present invention is to protect the mask ROM source and drain regions with a buffer layer to prevent bit-line to bit-line code leakage due to the high energy ion implantation used in coding. 
     In accordance with the objects of this invention, a new method of forming mask ROM in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided with field oxide areas defined and a gate oxide layer overlying the semiconductor substrate. A gate electrode layer is deposited overlying the gate oxide layer. The gate electrode layer and the gate oxide layer are patterned to form gate electrodes. Ions are implanted to form source and drain junctions. A buffer layer is deposited overlying the gate electrodes, the source and drain junctions, and the field oxide areas. The buffer layer is etched down to expose the gate electrodes while leaving a protective thickness of the buffer layer overlying the source and drain junctions. Ions are implanted through the gate electrodes into the semiconductor substrate to selectively code the mask ROM devices and to complete the mask ROM devices in the manufacture of the semiconductor device. A coding mask controls the ion implantation to selectively code the mask ROM. The buffer layer prevents the ions from penetrating into the source and drain areas. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the accompanying drawings forming a material part of this description, there is shown: 
     FIGS. 1 and 2 schematically illustrate in cross-section a partially completed prior art integrated circuit device. 
     FIGS. 3 through 9 schematically illustrate in cross-section the preferred embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The embodiment discloses the application of the present invention to the formation of mask ROM in the manufacture of an integrated circuit device. It should be clear to those experienced in the art that the present invention can be applied and extended without deviating from the scope of the present invention. 
     Referring now particularly to FIG. 3, there is shown a cross section of a partially completed integrated circuit device of the preferred embodiment. A semiconductor substrate  50 , typically consisting of monocrystalline silicon, is provided. Field oxide areas  54  are defined in the semiconductor substrate  50 . The areas between the field oxide areas  54  are the active areas of the devices. A gate oxide layer  58  is formed overlying the semiconductor substrate  50 . The gate oxide layer  58  serves as the electrode dielectric for the subsequently formed mask ROM device. The gate oxide layer  58  is formed by a conventional process such as low-pressure chemical vapor deposition (LPCVD) or by thermal oxidation. The gate oxide layer  58  is preferably formed to a thickness of between about 100 Angstroms and 200 Angstroms. 
     An important feature of the present invention is the gate electrode layer  62 . The gate electrode layer  62  is deposited overlying the gate oxide layer  58 . The gate electrode layer  62  may comprise one of the group containing: polysilicon, polycide and silicide. 
     The thickness of the gate electrode layer  62  is a critical component in the present invention. The process of the present invention performs the coding ion implantation after the formation of the gate electrodes and the source and drain junctions. Therefore, the implanted ions must pass through the gate electrodes and into the underlying channel regions in the semiconductor substrate  50 . As the thickness of the gate electrode layer  62  is increased, the energy required for the ion implantation also increases. Unfortunately, if the ion implantation energy is too great, the ions will also penetrate into unwanted areas and possibly cause junction leakage between bit-lines. Finally, if the gate electrode layer  62  is too thin, the resistivity of the gates will increase and cause a degradation of circuit performance. The gate electrode layer  62  preferably comprises polysilicon deposited by LPCVD to a thickness of between about 2,500 Angstroms and 3,500 Angstroms. 
     Referring now to FIG. 4, the gate electrode layer  62  and the gate oxide layer  58  are patterned to form gate electrodes and word lines  62  for the mask ROM device. The patterning is conventionally performed using a photolithographic sequence of coating with photoresist, exposing through a mask, developing, and etching. 
     Referring now to FIG. 5, the mask ROM device is depicted after implantation of lightly doped drains  66 , formation of sidewall spacers  74 , and implantation of source and drain junctions  70 . The lightly doped drains  66  are conventionally implanted and are self-aligned to the gate electrodes  62 . The sidewall spacers  74  may comprise silicon nitride or silicon dioxide. The sidewall spacers  74  are conventionally formed using a plasma sputter-deposition process. The source and drain junctions  70  are conventionally implanted and are self-aligned to the sidewall spacers  74 . 
     Referring now to FIG. 6, an important feature of the present invention is illustrated. A buffer layer  78  is deposited overlying the gate electrodes  62 , the source and drain junctions  70 , and the field oxide areas  54 . The buffer layer  78  will protect the source and drain junctions  70  during the subsequent coding ion implantation. The buffer layer  78  will prevent ion infiltration into unwanted areas of the circuit. The buffer layer  78  preferably comprises a bottom anti-reflective coating (BARC) that may be an organic material. The buffer layer  78  may also comprise a spin-on glass (SOG) material. The buffer layer  78  is preferably BARC deposited to a thickness of between about 1,000 Angstroms and 2,500 Angstroms. 
     Referring now to FIG. 7, another important part of the present invention is illustrated. The buffer layer  78  is etched down to expose the gate electrodes  62  while leaving a protective thickness of the buffer layer  78  overlying the source and drain junctions. The buffer layer  78  must be removed from the gate electrodes  62  so that it does not inhibit the implantation of ions through the gate electrode layer  62  during the code implantation. In addition, the etching down removes any oxide that may have formed over the gate electrode  62  and thus improves the implantation capability. Conversely, a significant thickness of the buffer layer  78  must be left overlying the source and drain junctions  70  in the semiconductor substrate  50  to protect and shield this part of the device from the implantation. 
     The etching down step is preferably performed using a dry etching process with an O 2  base. After the etching down step, a protective thickness of between about 700 Angstroms and 1,500 Angstroms of the buffer layer  78  is left overlying the source and drain junctions. 
     Referring now to FIG. 8, another important feature of the present invention is illustrated. Ions are implanted  86  through the gate electrodes  62  to code the mask ROM devices. The ion implantation  86  is performed in a selective fashion. A masking layer  82  of photoresist is used to block or permit passage of the ions into selected devices. The masking photoresist  82  is patterned, for example, using a photolithographic process that opens the photoresist  82  where selective mask ROM cells are to be implanted. 
     The implantation of the ions  86  through the gate electrode layer  62  forms an implanted region  90  under the gate electrode  62  in the channel region of the transistor. The presence of the implanted region alters the V t  of the transistor to the desired value for the code. For example, for N-code, phosphorous ions may be implanted at an energy of between 160 KeV and 180 KeV and a dosage of between about 1×10 13  atoms/cm 2  and 5×10 13  atoms/cm 2 . For P-code, boron ions may be implanted at an energy of between about 100 KeV and 140 KeV and a dosage of between about 8×10 13  atoms/cm 2  and 2×10 14  atoms/cm 2 . 
     The presence of the buffer layer  78  overlying the source and drain junctions  70  prevents ions from implanting into the semiconductor substrate  50  in the junctions and under the bird&#39;s beak area of the field oxide region  54 . If ions were to implant in the bird&#39;s beak area, this would cause junction leakage and result in bit-line to bit-line leakage. 
     Referring now to FIG. 9, the buffer layer  78  is removed. A dielectric layer  94  is deposited conventionally to insulate the mask ROM device. After patterning contact openings, a metal layer  98  is deposited overlying the dielectric layer  94 . The metal layer  98  is patterned to form desired connectivity and the mask ROM device is completed in the manufacture of the integrated circuit device. 
     Experimental data confirms the viability and effectiveness of the novel approach of the present invention for forming mask ROM devices. The prior art mask ROM process illustrated in FIGS. 1 and 2 performs the coding implant after the formation of the sacrificial oxide layer but before the formation of the gate electrodes and the source and drain junctions. This prior art process produces an exemplary yield of about 85%. By comparison, the preferred embodiment of the present invention produces a yield of about 74%. It is believed that fine-tuning the process of the invention will allow further yield improvement. In addition, the preferred embodiment of the present invention is found to postpones the critical coding implantation step ten days further into the processing cycle. This delay in coding allows the manufacturer to process material up to the coding operation and hold this material until it is needed by a customer with a final masking code design. The customer then will receive finished product ten days sooner. The manufacturer will also tend to scrap less product due to last minute code changes. 
     Finally, experimental material has been processed excluding the critical buffer layer. That is, the process of the present invention was performed without protecting the source and drain junctions during the coding implantation. The experimental yield of 0% confirms the need and effectiveness of the buffer layer. The high energy required to implant the channel area through the gate electrode causes a great deal of residual and undesirable implantation. The bit line to bit line leakage is too great to allow for any device yield. 
     As shown in the preferred embodiments, the present invention provides a very manufacturable process for forming mask ROM devices in an integrated circuit device. The application of the present invention in the preferred embodiments forms the mask ROM devices up to and including the gate electrodes and the source and drain junctions. The coding implantation is then selectively performed with a buffer layer overlying the source and drain junction to prevent unwanted ion implantation. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.