Patent Publication Number: US-7902677-B1

Title: Composite layered chip package and method of manufacturing same

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a composite layered chip package that includes a plurality of subpackages stacked and a method of manufacturing the same. 
     2. Description of the Related Art 
     In recent years, a reduction in weight and an improvement in performance have been demanded of mobile devices typified by cellular phones and notebook personal computers. Accordingly, there has been a demand for higher integration of electronic components for use in mobile devices. Higher integration of electronic components has been demanded also for achieving an increase in capacity of semiconductor memory. 
     As an example of highly integrated electronic components, a system-in-package (hereinafter referred to as SiP), especially an SiP utilizing a three-dimensional packaging technology for stacking a plurality of semiconductor chips, has attracting attention in recent years. In the present application, a package that includes a plurality of semiconductor chips (hereinafter, also simply referred to as chips) stacked is called a layered chip package. Since the layered chip package allows a reduction in wiring length, it provides the advantage of allowing acceleration of the operation of circuits and a reduction in stray capacitance of wiring, as well as the advantage of allowing higher integration. 
     Major examples of the three-dimensional packaging technology for fabricating a layered chip package include a wire bonding method and a through electrode method. According to the wire bonding method, a plurality of chips are stacked on a substrate, and a plurality of electrodes formed on each chip are connected to external connecting terminals formed on the substrate by wire bonding. According to the through electrode method, a plurality of through electrodes are formed in each of the chips to be stacked and inter-chip wiring is performed through the use of the through electrodes. 
     The wire bonding method has the problem that it is difficult to reduce the distance between the electrodes so as to avoid contact between wires, and the problem that the high resistances of the wires hinder the acceleration of the operation of circuits. 
     The through electrode method is free from the above-mentioned problems of the wire bonding method. Unfortunately, however, the through electrode method requires a large number of steps for forming the through electrodes in chips, and consequently increases the cost for the layered chip package. According to the through electrode method, forming the through electrodes in chips requires a series of steps as follows: forming a plurality of holes for the plurality of through electrodes in a wafer that is to be cut later into a plurality of chips; forming an insulating layer and a seed layer in the plurality of holes and on the top surface of the wafer; forming a plurality of through electrodes by filling the plurality of holes with metal such as Cu by plating; and removing unwanted portions of the seed layer. 
     According to the through electrode method, the through electrodes are formed by filling metal into holes having relatively high aspect ratios. Consequently, voids or keyholes are prone to occur in the through electrodes due to poor filling of the holes with metal, so that the reliability of wiring formed by the through electrodes tends to be reduced. 
     According to the through electrode method, an upper chip and a lower chip are physically joined to each other by connecting the through electrodes of the upper and lower chips by means of, for example, soldering. The through electrode method therefore requires that the upper and lower chips be accurately aligned and then joined to each other at high temperatures. When the upper and lower chips are joined to each other at high temperatures, however, misalignment between the upper and lower chips can occur due to expansion and contraction of the chips, which often results in electrical connection failure between the upper and lower chips. 
     U.S. Pat. No. 5,953,588 discloses a manufacturing method for a layered chip package as described below. In this method, a plurality of chips cut out from a processed wafer are embedded into an embedding resin and then a plurality of leads are formed to be connected to each chip, whereby a structure called a neo-wafer is fabricated. Next, the neo-wafer is diced into a plurality of structures each called a neo-chip. Each neo-chip includes one or more chips, resin surrounding the chip(s), and a plurality of leads. The plurality of leads connected to each chip each have an end face exposed at a side surface of the neo-chip. Next, a plurality of types of neo-chips are laminated into a stack. In the stack, the respective end faces of the plurality of leads connected to the chips of each layer are exposed at the same side surface of the stack. 
     Keith D. Gann, “Neo-Stacking Technology”, HDI Magazine, December 1999, discloses fabricating a stack by the same method as U.S. Pat. No. 5,953,588, and forming wiring on two side surfaces of the stack. 
     The manufacturing method disclosed in U.S. Pat. No. 5,953,588 involves a number of process steps and this raises the cost for the layered chip package. According to the method, after the plurality of chips cut out from a processed wafer are embedded into the embedding resin, the plurality of leads are formed to be connected to each chip to thereby fabricate the neo-wafer, as described above. Accurate alignment between the plurality of chips is therefore required when fabricating the neo-wafer. This is also a factor that raises the cost for the layered chip package. 
     U.S. Pat. No. 7,127,807 B2 discloses a multilayer module formed by stacking a plurality of active layers each including a flexible polymer substrate with at least one electronic element and a plurality of electrically-conductive traces formed within the substrate. U.S. Pat. No. 7,127,807 B2 further discloses a manufacturing method for a multilayer module as described below. In the manufacturing method, a module array stack is fabricated by stacking a plurality of module arrays each of which includes a plurality of multilayer modules arrayed in two orthogonal directions. The module array stack is then cut into a module stack which is a stack of a plurality of multilayer modules. Next, a plurality of conductive lines are formed at the respective side surfaces of the plurality of multilayer modules included in the module stack. The module stack is then separated into individual multilayer modules. 
     With the multilayer module disclosed in U.S. Pat. No. 7,127,807 B2, it is impossible to increase the proportion of the area occupied by the electronic element in each active layer, and consequently it is difficult to achieve higher integration. 
     For a wafer to be cut into a plurality of chips, the yield of the chips, that is, the rate of conforming chips with respect to all chips obtained from the wafer, is 90% to 99% in many cases. Since a layered chip package includes a plurality of chips, the rate of layered chip packages in which all of the plurality of chips are conforming ones is lower than the yield of the chips. The larger the number of chips included in each layered chip package, the lower the rate of layered chip packages in which all of the chips are conforming ones. 
     A case will now be considered where a memory device such as a flash memory is formed using a layered chip package. For a memory device such as a flash memory, a redundancy technique of replacing a defective column of memory cells with a redundant column of memory cells is typically employed so that the memory device can normally function even when some memory cells are defective. The redundancy technique can also be employed in the case of forming a memory device using a layered chip package. This makes it possible that, even if some of memory cells included in any chip are defective, the memory device can normally function while using the chip including the defective memory cells. Suppose, however, that a chip including a control circuit and a plurality of memory cells has become defective due to, for example, a wiring failure of the control circuit, and the chip cannot function normally even by employing the redundancy technique. In such a case, the defective chip is no longer usable. While the defective chip can be replaced with a conforming one, it increases the cost for the layered chip package. 
     US 2007/0165461 A1 discloses a technique of identifying one or more defective flash memory dies in a flash memory device having a plurality of flash memory dies, and disabling memory access operations to each identified die. 
     In the case of forming a memory device using a layered chip package, one or more defective chips included in the layered chip package may be identified and disabled in the same way as the technique disclosed in US 2007/0165461 A1. 
     If, however, a layered chip package including a predetermined number of chips is able to implement a memory device having a desired memory capacity only when all the chips included in the layered chip package are conforming, simply disabling a defective chip included in the layered chip package cannot achieve the implementation of the memory device having such a desired memory capacity. 
     OBJECT AND SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a composite layered chip package including a plurality of semiconductor chips stacked and its manufacturing method, the composite layered chip package being capable of providing, even if it includes a malfunctioning semiconductor chip, the same functions as those for the case where no malfunctioning semiconductor chip is included. 
     A composite layered chip package according to the present invention includes a plurality of subpackages stacked, every two vertically adjacent subpackages being electrically connected to each other. Each of the plurality of subpackages includes: a main body having a top surface, a bottom surface and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body. The main body has a main part, the main part including at least one first-type layer portion and having a top surface and a bottom surface. 
     For any two vertically adjacent subpackages, the main body of the lower subpackage further has a plurality of first terminals that are arranged on the top surface of the main part and electrically connected to the wiring, while the main body of the upper subpackage further has a plurality of second terminals that are arranged on the bottom surface of the main part and electrically connected to the wiring. The plurality of second terminals of the main body of the upper subpackage are electrically connected to the plurality of first terminals of the main body of the lower subpackage. The main part of the main body of at least one of the plurality of subpackages further includes at least one second-type layer portion. Each of the first-type layer portion and the second-type layer portion includes a semiconductor chip. The first-type layer portion further includes a plurality of electrodes, each of the electrodes being electrically connected to the semiconductor chip and having an end face located at the at least one of the side surfaces of the main body on which the wiring is disposed, whereas the second-type layer portion does not include the plurality of electrodes. The wiring is electrically connected to the end faces of the plurality of electrodes. 
     In the composite layered chip package according to the present invention, the semiconductor chip of the first-type layer portion may be a normally functioning one whereas the semiconductor chip of the second-type layer portion may be a malfunctioning one. 
     In the composite layered chip package according to the present invention, the main body of a lowermost one of the plurality of subpackages may further have the plurality of second terminals. 
     In the composite layered chip package according to the present invention, the main body of an uppermost one of the plurality of subpackages may further have the plurality of first terminals. 
     In the composite layered chip package according to the present invention, the respective main bodies of all of the plurality of subpackages may each have the plurality of first terminals and the plurality of second terminals. 
     In the composite layered chip package according to the present invention, the semiconductor chip may have four side surfaces, and each of the first-type layer portion and the second-type layer portion may further include an insulating portion that covers at least one of the four side surfaces of the semiconductor chip. In this case, the insulating portion may have at least one end face that is located at the at least one of the side surfaces of the main body on which the wiring is disposed. 
     A manufacturing method for the composite layered chip package according to the present invention includes the steps of: fabricating a plurality of subpackages; and stacking the plurality of subpackages and, for any two vertically adjacent subpackages, electrically connecting the plurality of second terminals of the upper subpackage to the plurality of first terminals of the lower subpackage. 
     In the manufacturing method for the composite layered chip package according to the present invention, the semiconductor chip of the first-type layer portion may be a normally functioning one whereas the semiconductor chip of the second-type layer portion may be a malfunctioning one. 
     In this case, the step of fabricating the plurality of subpackages may include, as a series of steps for forming each subpackage, the step of fabricating at least one substructure that includes a plurality of preliminary layer portions arrayed, each of the preliminary layer portions being intended to be made into any one of the layer portions included in the main part, the substructure being intended to be cut later at the position of the boundary between every adjacent preliminary layer portions; and the step of fabricating the subpackage by using the at least one substructure. The step of fabricating the at least one substructure may include the steps of: fabricating a pre-substructure wafer including a plurality of pre-semiconductor-chip portions that are arrayed and intended to be made into the individual semiconductor chips; distinguishing the plurality of pre-semiconductor-chip portions included in the pre-substructure wafer into normally functioning pre-semiconductor-chip portions and malfunctioning pre-semiconductor-chip portions; and forming the plurality of electrodes in the normally functioning pre-semiconductor-chip portions while not forming the plurality of electrodes in the malfunctioning pre-semiconductor-chip portions, so as to make the pre-substructure wafer into the substructure. 
     The step of forming the plurality of electrodes may include the steps of: forming a photoresist layer that is intended to be used for forming the plurality of electrodes and includes a plurality of areas corresponding to all the pre-semiconductor-chip portions; forming a frame by patterning the photoresist layer by photolithography, the frame having a plurality of openings that are intended to accommodate the plurality of electrodes later; and forming the plurality of electrodes in the plurality of openings of the frame. 
     In the manufacturing method for the composite layered chip package according to the present invention, the main body of a lowermost one of the plurality of subpackages may further have the plurality of second terminals. 
     In the manufacturing method for the composite layered chip package according to the present invention, the main body of an uppermost one of the plurality of subpackages may further have the plurality of first terminals. 
     In the manufacturing method for the composite layered chip package according to the present invention, the respective main bodies of all of the plurality of subpackages may each have the plurality of first terminals and the plurality of second terminals. 
     In the manufacturing method for the composite layered chip package according to the present invention, the semiconductor chip may have four side surfaces, and each of the first-type layer portion and the second-type layer portion may further include an insulating portion that covers at least one of the four side surfaces of the semiconductor chip. In this case, the insulating portion may have at least one end face that is located at the at least one of the side surfaces of the main body on which the wiring is disposed. 
     The composite layered chip package according to the present invention includes a plurality of subpackages stacked. For any two vertically adjacent subpackages, the plurality of second terminals of the main body of the upper subpackage are electrically connected to the plurality of first terminals of the main body of the lower subpackage. The main part of the main body of each of the plurality of subpackages includes at least one first-type layer portion. The main part of the main body of at least one of the plurality of subpackages further includes at least one second-type layer portion. The first-type layer portion includes a plurality of electrodes, each of the electrodes being electrically connected to the semiconductor chip and having an end face located at the at least one of the side surfaces of the main body on which the wiring is disposed, whereas the second-type layer portion does not include the plurality of electrodes. According to the present invention, a package including a plurality of semiconductor chips stacked can be easily implemented by stacking a plurality of subpackages, the package being capable of providing, even if it includes a malfunctioning semiconductor chip, the same functions as those for the case where no malfunctioning semiconductor chip is included. 
     Other and further objects, features and advantages of the present invention will appear more fully from the following description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a perspective view of a composite layered chip package according to an embodiment of the invention. 
         FIG. 2  is a perspective view showing the composite layered chip package of  FIG. 1  as viewed from below. 
         FIG. 3  is an exploded perspective view of the composite layered chip package of  FIG. 1 . 
         FIG. 4  is an exploded perspective view of the composite layered chip package of  FIG. 2 . 
         FIG. 5  is a perspective view of the composite layered chip package of  FIG. 1  drawn such that respective end faces of a plurality of electrodes are visible. 
         FIG. 6  is a side view of the composite layered chip package of  FIG. 1 . 
         FIG. 7  is a perspective view showing a layer portion included in the composite layered chip package of  FIG. 1 . 
         FIG. 8  is a cross-sectional view showing a part of the device included in the semiconductor chip. 
         FIG. 9  is a plan view showing a pre-substructure wafer fabricated in a step of a manufacturing method for the composite layered chip package according to the embodiment of the invention. 
         FIG. 10  is a magnified plan view showing a part of the pre-substructure wafer of  FIG. 9 . 
         FIG. 11  shows a cross section taken along line  11 - 11  of  FIG. 10 . 
         FIG. 12  is a plan view showing a step that follows the step shown in  FIG. 10 . 
         FIG. 13  shows a cross section taken along line  13 - 13  of  FIG. 12 . 
         FIG. 14  is a cross-sectional view showing a step that follows the step shown in  FIG. 13 . 
         FIG. 15  is a cross-sectional view showing a step that follows the step shown in  FIG. 14 . 
         FIG. 16  is an explanatory diagram showing an example of the configuration of an exposure apparatus for use in the manufacturing method for the composite layered chip package according to the embodiment of the invention. 
         FIG. 17  is a flow chart showing an exposure step for forming the plurality of electrodes in the manufacturing method for the composite layered chip package according to the embodiment of the invention. 
         FIG. 18A  and  FIG. 18B  are cross-sectional views showing a step that follows the step shown in  FIG. 15 . 
         FIG. 19A  and  FIG. 19B  are cross-sectional views showing a step that follows the step shown in  FIG. 18A  and  FIG. 18B . 
         FIG. 20A  and  FIG. 20B  are cross-sectional views showing a step that follows the step shown in  FIG. 19A  and  FIG. 19B . 
         FIG. 21  is a plan view showing the step of  FIG. 20A . 
         FIG. 22  is a cross-sectional view showing a step that follows the step shown in  FIG. 20A  to  FIG. 21 . 
         FIG. 23  is a cross-sectional view showing a step that follows the step shown in  FIG. 22 . 
         FIG. 24  is a cross-sectional view showing a step that follows the step shown in  FIG. 23 . 
         FIG. 25  is a cross-sectional view showing a part of a first layered substructure fabricated in a step that follows the step shown in  FIG. 24 . 
         FIG. 26  is a perspective view showing a second layered substructure fabricated in a step that follows the step shown in  FIG. 25 . 
         FIG. 27  is a side view of the second layered substructure of  FIG. 26 . 
         FIG. 28  is a perspective view showing a first example of a block obtained by cutting the second layered substructure. 
         FIG. 29  is a perspective view showing a second example of a block obtained by cutting the second layered substructure. 
         FIG. 30  is a perspective view showing a third example of a block obtained by cutting the second layered substructure. 
         FIG. 31  is an explanatory diagram showing a step that follows the step shown in  FIG. 28  to  FIG. 30 . 
         FIG. 32  is a perspective view showing a plurality of block assemblies arrayed in a step that follows the step shown in  FIG. 31 . 
         FIG. 33  is a cross-sectional view showing a step of the process for forming the wiring in the embodiment of the invention. 
         FIG. 34  is a cross-sectional view showing a step that follows the step shown in  FIG. 33 . 
         FIG. 35  is a cross-sectional view showing a step that follows the step shown in  FIG. 34 . 
         FIG. 36  is a cross-sectional view showing a step that follows the step shown in  FIG. 35 . 
         FIG. 37  is a cross-sectional view showing a step that follows the step shown in  FIG. 36 . 
         FIG. 38  is an explanatory diagram showing a step that follows the step shown in  FIG. 37 . 
         FIG. 39  is a perspective view showing a subpackage that includes eight layer portions. 
         FIG. 40  is a perspective view showing a subpackage that includes only a single layer portion. 
         FIG. 41  is a perspective view showing a subpackage that includes two layer portions. 
         FIG. 42  is a perspective view showing a subpackage that includes three layer portions. 
         FIG. 43  is a perspective view showing a subpackage that includes four layer portions. 
         FIG. 44  is a perspective view showing four subpackages stacked. 
         FIG. 45  is a side view showing connecting parts of the terminals of two vertically adjacent subpackages. 
         FIG. 46  is an explanatory diagram for explaining misalignment between the terminals of two vertically adjacent subpackages. 
         FIG. 47  is a perspective view showing an example of a manufacturing method for an electronic component that includes a plurality of subpackages stacked. 
         FIG. 48  is a perspective view showing a first modification example of the composite layered chip package of the embodiment of the invention. 
         FIG. 49  is perspective view showing a second modification example of the composite layered chip package of the embodiment of the invention. 
         FIG. 50  is perspective view showing a first modification example of the subpackage of the embodiment of the invention. 
         FIG. 51  is perspective view showing a second modification example of the subpackage of the embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A preferred embodiment of the present invention will now be described in detail with reference to the drawings. Reference is first made to  FIG. 1  to  FIG. 6  to describe the configuration of a composite layered chip package according to the embodiment of the invention.  FIG. 1  is a perspective view of the composite layered chip package according to the embodiment of the invention.  FIG. 2  is a perspective view showing the composite layered chip package of  FIG. 1  as viewed from below.  FIG. 3  is an exploded perspective view of the composite layered chip package of  FIG. 1 .  FIG. 4  is an exploded perspective view of the composite layered chip package of  FIG. 2 .  FIG. 5  is a perspective view of the composite layered chip package of  FIG. 1  drawn such that respective end faces of a plurality of electrodes are visible.  FIG. 6  is a side view of the composite layered chip package of  FIG. 1 . 
     The composite layered chip package  1  according to the present embodiment includes a plurality of subpackages stacked, every two vertically adjacent subpackages being electrically connected to each other.  FIG. 1  to  FIG. 6  show an example where the composite layered chip package  1  includes two subpackages  1 A and  1 B, the subpackage  1 A being placed on the subpackage  1 B.  FIG. 3  and  FIG. 4  show the state where the subpackages  1 A and  1 B are separated from each other. In the following description, any subpackage will be generally designated by reference numeral  1 S. 
     Each of the subpackages  1 A and  1 B includes a main body  2  having a top surface  2   a , a bottom surface  2   b , and four side surfaces  2   c ,  2   d ,  2   e  and  2   f . The side surfaces  2   c  and  2   d  face toward opposite directions. The side surfaces  2   e  and  2   f  face toward opposite directions. Each of the subpackages  1 A and  1 B further includes wiring  3  disposed on at least one of the side surfaces of the main body  2 . In the example shown in  FIG. 1  to  FIG. 6 , the wiring  3  is disposed on the side surface  2   c  of the main body  2 . The main body  2  has a main part  2 M that includes at least one first-type layer portion  10 A. The main part  2 M has a top surface  2 Ma and a bottom surface  2 Mb. 
     The main body  2  of the lower subpackage  1 B further has a plurality of first terminals  4  that are arranged on the top surface  2 Ma of the main part  2 M and electrically connected to the wiring  3 . The main body  2  of the upper subpackage  1 A further has a plurality of second terminals  5  that are arranged on the bottom surface  2 Mb of the main part  2 M and electrically connected to the wiring  3 . The plurality of second terminals  5  of the main body  2  of the upper subpackage  1 A are electrically connected to the plurality of first terminals  4  of the main body  2  of the lower subpackage  1 B. 
     As shown in  FIG. 6 , the composite layered chip package  1  may include a sealing part  6  that is made of an insulating material and fills the gap between the subpackages  1 A and  1 B. 
     If the composite layered chip package  1  includes three or more subpackages  1 S stacked, any two vertically adjacent subpackage  1 S shall be configured as follows. The main body  2  of the lower subpackage  1 S has the plurality of first terminals  4 ; the main body  2  of the upper subpackage  1 S has the plurality of second terminals  5 ; and the second terminals  5  of the main body  2  of the upper subpackage  1 S are electrically connected to the first terminals  4  of the main body  2  of the lower subpackage  1 S. 
     In the present embodiment, the main body  2  of the lowermost subpackage  1 S may further have the plurality of second terminals  5 , and the main body  2  of the uppermost subpackage  15  may further have the plurality of first terminals  4 . The respective main bodies  2  of all of the plurality of subpackages  15  may each have the plurality of first terminals  4  and the plurality of second terminals  5 . In the example shown in  FIG. 1  to  FIG. 6 , the main bodies  2  of both of the subpackages  1 A and  1 B each have the plurality of first terminals  4  and the plurality of second terminals  5 . Consequently, in this case, the main body  2  of the lowermost subpackage  1 B has the plurality of second terminals  5 , and the main body  2  of the uppermost subpackage  1 A has the plurality of first terminals  4 . 
     Each of the terminals  4  and  5  may include a bump formed of solder, for example. In this case, the terminals  4  and  5  are electrically connected to each other by bonding the bump of the terminal  4  and the bump of the terminal  5  to each other. 
     The main part  2 M of the main body  2  of at least one of the plurality of subpackages  1 S further includes at least one second-type layer portion  10 B. As will be described in detail later, each of the first-type layer portion  10 A and the second-type layer portion  10 B includes a semiconductor chip. The first-type layer portion  10 A further includes a plurality of electrodes that are each electrically connected to the semiconductor chip and that each have an end face located at the at least one of the side surfaces of the main body  2  on which the wiring  3  is disposed, whereas the second-type layer portion  10 B does not include any electrodes that each have an end face located at the at least one of the side surfaces of the main body  2  on which the wiring  3  is disposed. The wiring  3  is electrically connected to the end faces of the plurality of electrodes. The semiconductor chip of the first-type layer portion  10 A is a normally functioning one whereas the semiconductor chip of the second-type layer portion  10 B is a malfunctioning one. 
     In the example shown in  FIG. 1  to  FIG. 6 , the main part  2 M of the main body  2  of the subpackage  1 A includes six first-type layer portions  10 A and two second-type layer portions  10 B, whereas the main part  2 M of the main body  2  of the subpackage  1 B includes two first-type layer portions  10 A and no second-type layer portion  10 B. 
     When the main part  2 M of the main body  2  includes a plurality of layer portions regardless of the types of the layer portions, the plurality of layer portions are stacked on each other between the top surface  2 Ma and the bottom surface  2 Mb of the main part  2 M. Every two vertically adjacent layer portions are bonded to each other with an adhesive, for example. Hereinafter, any layer portion will be generally designated by reference numeral  10 . 
     With a plurality of layer portions  10  included in the main part  2 M of its main body  2 , a subpackage  1 S itself is a layered chip package, which is combined with one or more other subpackages  1 S to constitute the composite layered chip package  1 . 
       FIG. 7  is a perspective view showing a part of the first-type layer portion  10 A. As shown in  FIG. 7 , the layer portion  10 A includes a semiconductor chip  30 . The semiconductor chip  30  has: a first surface  30   a  with a device formed thereon; a second surface  30   b  opposite to the first surface  30   a ; a first side surface  30   c  and a second side surface  30   d  that face toward opposite directions; and a third side surface  30   e  and a fourth side surface  30   f  that face toward opposite directions. The side surfaces  30   c ,  30   d ,  30   e  and  30   f  respectively face toward the side surfaces  2   c ,  2   d ,  2   e  and  2   f  of the main body  2 . 
     The layer portion  10 A further includes: an insulating portion  31  that covers at least one of the four side surfaces of the semiconductor chip  30 ; and a plurality of electrodes  32  electrically connected to the semiconductor chip  30 . The insulating portion  31  has at least one end face  31   a  that is located at the at least one of the side surfaces of the main body  2  on which the wiring is disposed. In the example shown in  FIG. 7 , the insulating portion  31  covers all of the four side surfaces of the semiconductor chip  30 , and has four end faces  31   a  located at the four side surfaces of the main body  2 . 
     The second-type layer portion  10 B includes its semiconductor chip  30  and insulating portion  31  as does the first-type layer portion  10 A, but does not include the plurality of electrodes  32 . As previously mentioned, the semiconductor chip  30  of the first-type layer portion  10 A is a normally functioning one whereas the semiconductor chip  30  of the second-type layer portion  10 B is a malfunctioning one. Hereinafter, a normally functioning semiconductor chip  30  will be referred to as a conforming semiconductor chip  30 , and a malfunctioning semiconductor chip  30  will be referred to as a defective semiconductor chip  30 . 
     In the layer portion(s) other than the uppermost one in a main body  2 , the insulating portion  31  also covers the first surface  30   a  of the semiconductor chip  30  and the plurality of electrodes  32 . In the uppermost layer portion in a main body  2 , the insulating portion  31  does not cover the first surface  30   a  of the semiconductor chip  30 . If the uppermost layer portion is the first-type layer portion  10 A, the plurality of electrodes  32  are not covered by the insulating portion  31  but are exposed. The plurality of electrodes  32  of the uppermost layer portion  10 A also function as the plurality of terminals  4 . Note that the uppermost layer portion may also be configured so that the insulating portion  31  covers the first surface  30   a  of the semiconductor chip  30  and the plurality of electrodes  32 , and that the terminals  4  are formed on the insulating portion  31  aside from the electrodes  32 . 
     The second-type layer portion  10 B may include any electrode or wiring as long as the electrode or wiring is other than one that is configured to be electrically connected to the semiconductor chip  30  and to have an end face located at the at least one of the side surfaces of the main body  2  on which the wiring  3  is disposed. For example, the second-type layer portion  10 B may include an electrode that is electrically connected to the semiconductor chip  30  but does not have an end face located at the at least one of the side surfaces of the main body  2  on which the wiring  3  is disposed, and/or wiring intended for connecting the terminals of the semiconductor chip  30  to each other. 
     The semiconductor chip  30  may be a memory chip that constitutes a memory such as a flash memory, DRAM, SRAM, MRAM, PROM, or FeRAM. In such a case, it is possible to implement a large-capacity memory by using the composite layered chip package  1  including a plurality of semiconductor chips  30 . With the composite layered chip package  1  according to the present embodiment, it is also possible to easily implement a memory of various capacities such as 64 GB (gigabytes), 128 GB, and 256 GB, by changing the number of the semiconductor chips  30  to be included in the composite layered chip package  1 . 
     In the case where the semiconductor chip  30  includes a plurality of memory cells and where one or more of the memory cells are defective, the semiconductor chip  30  is still conforming if it can function normally by employing the redundancy technique. 
     The semiconductor chips  30  are not limited to memory chips, and may be used for implementing other devices such as CPUs, sensors, and driving circuits for sensors. The composite layered chip package  1  according to the present embodiment is particularly suitable for implementing an SiP. 
     Reference is now made to  FIG. 8  to describe an example of the device included in the semiconductor chip  30 . By way of example, the following description will be given for a case where the device included in the semiconductor chip  30  is a circuit including a plurality of memory cells that constitute a memory.  FIG. 8  shows one of the plurality of memory cells. 
     The memory cell  40  includes a source  42  and a drain  43  formed near a surface of a P-type silicon substrate  41 . The source  42  and the drain  43  are both N-type regions. The source  42  and the drain  43  are disposed at a predetermined distance from each other so that a channel composed of a part of the P-type silicon substrate  41  is provided between the source  42  and the drain  43 . The memory cell  40  further includes an insulating film  44 , a floating gate  45 , an insulating film  46 , and a control gate  47  that are stacked in this order on the surface of the substrate  41  at the location between the source  42  and the drain  43 . The memory cell  40  further includes an insulating layer  48  that covers the source  42 , the drain  43 , the insulating film  44 , the floating gate  45 , the insulating film  46  and the control gate  47 . The insulating layer  48  has contact holes that open at the tops of the source  42 , the drain  43  and the control gate  47 , respectively. The memory cell  40  includes a source electrode  52 , a drain electrode  53 , and a control gate electrode  57  that are formed on the insulating layer  48  at locations above the source  42 , the drain  43  and the control gate  47 , respectively. The source electrode  52 , the drain electrode  53  and the control gate electrode  57  are connected to the source  42 , the drain  43  and the control gate  47 , respectively, through the corresponding contact holes. 
     Next, a description will be given of a manufacturing method for the composite layered chip package  1  according to the present embodiment. The manufacturing method for the composite layered chip package  1  according to the present embodiment includes the steps of: fabricating a plurality of subpackages  15 ; and stacking the plurality of subpackages  1 S and, for any two vertically adjacent subpackages  1 S, electrically connecting the plurality of second terminals  5  of the upper subpackage  1 S to the plurality of first terminals  4  of the lower subpackage  1 S. 
     The step of fabricating the plurality of subpackages  1 S includes, as a series of steps for forming each subpackage  1 S, the step of fabricating at least one substructure that includes a plurality of preliminary layer portions arrayed, each of the preliminary layer portions being intended to be made into any one of the layer portions  10  included in the main part  2 M, the substructure being intended to be cut later at the position of the boundary between every adjacent preliminary layer portions; and the step of fabricating the subpackage  1 S by using the at least one substructure. 
     The step of fabricating at least one substructure will now be described in detail with reference to  FIG. 9  to  FIG. 25 . The following description will be given for a case where a plurality of substructures are fabricated. In the step of fabricating at least one substructure, a pre-substructure wafer  101  is first fabricated. The pre-substructure wafer  101  includes a plurality of pre-semiconductor-chip portions  30 P that are arrayed and intended to be made into the individual semiconductor chips  30 .  FIG. 9  is a plan view of the pre-substructure wafer  101 .  FIG. 10  is a magnified plan view showing a part of the pre-substructure wafer  101  of  FIG. 9 .  FIG. 11  shows a cross section taken along line  11 - 11  of  FIG. 10 . 
     Specifically, in the step of fabricating the pre-substructure wafer  101 , a semiconductor wafer  100  having two surfaces that face toward opposite directions is subjected to processing, such as a wafer process, at one of the two surfaces to thereby fabricate the pre-substructure wafer  101  that includes the plurality of pre-semiconductor-chip portions  30 P arrayed, each of the pre-semiconductor-chip portions  30 P including a device. In the pre-substructure wafer  101 , the plurality of pre-semiconductor-chip portions  30 P may be arrayed in a row, or in a plurality of rows such that a number of pre-semiconductor-chip portions  30 P are arrayed both in vertical and horizontal directions. In the following description, assume that the plurality of pre-semiconductor-chip portions  30 P in the pre-substructure wafer  101  are arrayed in a plurality of rows such that a number of pre-semiconductor-chip portions  30 P are arrayed both in vertical and horizontal directions. The semiconductor wafer  100  may be a silicon wafer, for example. The wafer process is a process in which a semiconductor wafer is processed into a plurality of devices that are not yet separated into a plurality of chips. For ease of understanding,  FIG. 9  depicts the pre-semiconductor-chip portions  30 P larger relative to the semiconductor wafer  100 . For example, if the semiconductor wafer  100  is a 12-inch wafer and the top surface of each pre-semiconductor-chip portion  30  is 8 to 10 mm long at each side, then 700 to 900 pre-semiconductor-chip portions  30 P are obtainable from a single semiconductor wafer  100 . 
     As shown in  FIG. 11 , the pre-semiconductor-chip portions  30 P include a device-forming region  33  that is formed near one of the surfaces of the semiconductor wafer  100 . The device-forming region  33  is a region where devices are formed by processing the one of the surfaces of the semiconductor wafer  100 . The pre-semiconductor-chip portions  30 P further include a plurality of electrode pads  34  that are arranged on the device-forming region  33 , and a passivation film  35  that is made of an insulating material and disposed over the device-forming region  33 . The passivation film  35  has a plurality of openings for exposing the top surfaces of the plurality of electrode pads  34 . The plurality of electrode pads  34  are located at positions corresponding to the plurality of electrodes  32  to be formed later, and are electrically connected to the devices formed in the device-forming region  33 . Hereinafter, the surface of the pre-substructure wafer  101  located closer to the plurality of electrode pads  34  and the passivation film  35  will be referred to as a first surface  101   a . The surface on the opposite side will be referred to as a second surface  101   b.    
     In the step of fabricating at least one substructure, next, a wafer sort test is performed to distinguish the plurality of pre-semiconductor-chip portions  30 P included in the pre-substructure wafer  101  into normally functioning pre-semiconductor-chip portions and malfunctioning pre-semiconductor-chip portions. In this step, a probe of a testing device is brought into contact with the plurality of electrode pads  34  of each pre-semiconductor-chip portion  30 P so that whether the pre-semiconductor-chip portion  30 P functions normally or not is tested with the testing device. In  FIG. 9 , the pre-semiconductor-chip portions  30 P marked with “NG” are malfunctioning ones, and the other pre-semiconductor-chip portions  30 P are normally functioning ones. This step provides location information on the normally functioning pre-semiconductor-chip portions  30 P and the malfunctioning pre-semiconductor-chip portions  30 P in each pre-substructure wafer  101 . The location information is used in an exposure step for forming a frame to be described later. 
       FIG. 12  is a plan view showing a step that follows the step shown in  FIG. 10 .  FIG. 13  shows a cross section taken along line  13 - 13  of  FIG. 12 . In this step, a plurality of grooves  104  that open at the first surface  101   a  of the pre-substructure wafer  101  are formed in the pre-substructure wafer  101  so as to define the respective areas of the plurality of pre-semiconductor-chip portions  30 P. At the positions of the boundaries between every two adjacent pre-semiconductor-chip portions  30 P, the grooves  104  are formed to pass through the boundaries between every two adjacent pre-semiconductor-chip portions  30 P. The grooves  104  are formed such that their bottoms do not reach the second surface  101   b  of the pre-substructure wafer  101 . The grooves  104  are each 10 to 150 μm wide, for example. The grooves  104  are each 30 to 150 μm deep, for example. For example, the grooves  104  may be formed using a dicing saw, or by etching such as reactive ion etching. A pre-polishing substructure main body  105  is thus formed by the pre-substructure wafer  101  with the plurality of grooves  104  formed therein. 
       FIG. 14  shows a step that follows the step shown in  FIG. 13 . In this step, an insulating layer  106  is formed to fill the plurality of grooves  104  of the pre-polishing substructure main body  105  and to cover the plurality of electrode pads  34 . The insulating layer  106  is to become a part of the insulating portion  31  later. The insulating layer  106  may be formed of a resin such as an epoxy resin or a polyimide resin. The insulating layer  106  may also be formed of a photosensitive material such as a polyimide resin containing a sensitizer. 
       FIG. 15  shows a step that follows the step shown in  FIG. 14 . In this step, a plurality of openings  106   a  for exposing the plurality of electrode pads  34  are formed in the insulating layer  106 . If the insulating layer  106  is formed of a photosensitive material, the openings  106   a  of the insulating layer  106  may be formed by photolithography. If the insulating layer  106  is formed of a non-photosensitive material, the openings  106   a  of the insulating layer  106  may be formed by selectively etching the insulating layer  106 . The insulating layer  106  may include a first layer that fills the plurality of grooves  104 , and a second layer that covers the first layer and the plurality of electrode pads  34 . In this case, the openings  106   a  are formed in the second layer. Both of the first layer and the second layer may be formed of a resin such as an epoxy resin or a polyimide resin. The second layer may be formed of a photosensitive material such as a polyimide resin containing a sensitizer. If the second layer is formed of a photosensitive material, the openings  106   a  may be formed in the second layer by photolithography. If the second layer is formed of a non-photosensitive material, the openings  106   a  may be formed in the second layer by selectively etching the second layer. The first layer may be flattened at the top by, for example, ashing or chemical mechanical polishing (CMP), and then the second layer may be formed on the first layer. 
     Next, performed is the step of forming the plurality of electrodes  32  in the normally functioning pre-semiconductor-chip portions  30 P while not forming the plurality of electrodes  32  in the malfunctioning pre-semiconductor-chip portions  30 P. This step includes the steps of: forming a photoresist layer that is intended to be used for forming the plurality of electrodes  32  per pre-semiconductor-chip portion  30 P and includes a plurality of areas corresponding to all the pre-semiconductor-chip portions  30 P; forming a frame by patterning the photoresist layer by photolithography, the frame having a plurality of openings that are intended to accommodate the plurality of electrodes  32  later, the openings being formed in areas of the photoresist layer that correspond to the normally functioning pre-semiconductor-chip portions  30 P; and forming the plurality of electrodes  32  so that they are accommodated in the plurality of openings of the frame. 
     Reference is now made to  FIG. 16  to describe an example of the configuration of an exposure apparatus for use in the step of forming the frame. The exposure apparatus shown in  FIG. 16  is a stepping projection exposure apparatus, or a so-called stepper. The exposure apparatus includes: a mask stage  210  for retaining a mask  201 ; a driving device  211  for driving the mask stage  210  to move or replace the mask  201 ; a wafer stage  220  for retaining a wafer  202 ; a moving mechanism  221  for moving the wafer stage  220 ; a driving device  222  for driving the moving mechanism  221 ; a reduction projection optical system  203 ; an illumination device  204 ; a detection device  240  for detecting the location of the wafer  202 ; and a control device  250  for controlling the illumination device  204 , the driving devices  211  and  222  and the detection device  240 . 
     The mask stage  210  is disposed above the wafer stage  220 . The reduction projection optical system  203  is disposed between the mask stage  210  and the wafer stage  220 . The illumination device  204  is disposed above the mask stage  210  and applies light for exposure to the mask  201 . 
     The moving mechanism  221  is capable of moving the wafer stage  220  in X, Y and Z directions shown in  FIG. 16  and capable of changing the angle of inclination of the wafer stage  220  with respect to the X-Y plane. The X direction and the Y direction are orthogonal to each other and are both orthogonal to the direction of the optical axis of the reduction projection optical system  203 . The Z direction is parallel to the direction of the optical axis of the reduction projection optical system  203 . The detection device  240  detects the location of the surface of the wafer  202  and the angle of inclination of the surface of the wafer  202  with respect to the X-Y plane. 
     The control device  250  has a microprocessor unit (MPU), read only memory (ROM) and random access memory (RAM). 
     To expose the wafer  202  to light using this exposure apparatus, a plurality of pattern projection regions are defined on the surface of the wafer  202 . A ray bundle emitted from the illumination device  204  passes through the mask  201  and is applied to one of the pattern projection regions by the reduction projection optical system  203 . The mask pattern of the mask  201  is thereby projected onto the one of the pattern projection regions via the reduction projection optical system  203  so as to perform the process of exposing the one of the pattern projection regions. After performing the process of exposing the one of the pattern projection regions based on the mask pattern, the exposure apparatus moves the wafer  202  in the X or Y direction, and performs the same exposure process for a next one of the pattern projection regions. 
     Next, with reference to the flowchart of  FIG. 17 , a description will be given of the step of exposing the photoresist layer to light in order to form the frame to be used for forming the plurality of electrodes  32 . The following description will be given for situations where the photoresist layer is of negative type. The photoresist layer of negative type is soluble in a developing solution for the portions unirradiated with light, and becomes insoluble in the developing solution for the portions irradiated with light. In this exposure step, the photoresist layer is exposed to light so that a latent image corresponding to the plurality of electrodes  32  is formed in the areas of the photoresist layer that correspond to the normally functioning pre-semiconductor-chip portions  30 P while any latent image corresponding to the plurality of electrodes  32  is not formed in the areas of the photoresist layer that correspond to the malfunctioning pre-semiconductor-chip portions  30 P. In the exposure step, first, among the plurality of pattern projection regions corresponding to the plurality of pre-semiconductor-chip portions  30 P, a pattern projection region corresponding to a first pre-semiconductor-chip portion  30 P is selected to be exposed by the exposure apparatus of  FIG. 16  (Step S 101 ). Next, the control device  250  judges whether the pre-semiconductor-chip portion  30 P corresponding to the selected pattern projection region is a normally functioning one or not (Step S 102 ). The location information on the normally functioning pre-semiconductor-chip portions  30 P and the malfunctioning pre-semiconductor-chip portions  30 P in each pre-substructure wafer  101  obtained by the wafer sort test is input to and held by the control device  250 . The control device  250  makes a judgment in Step S 102  based on the location information. 
     If the pre-semiconductor-chip portion  30 P is judged as a normally functioning one (Y) in Step S 102 , the area of the photoresist layer corresponding to the normally functioning pre-semiconductor-chip portion  30 P is exposed to light in a pattern corresponding to the plurality of electrodes  32  (hereinafter referred to as an electrode pattern) by using a mask  201  that has the electrode pattern (Step S 103 ). Specifically, the electrode pattern is such a pattern that the parts of the pattern projection region where to form the openings to accommodate the electrodes  32  later are not irradiated with light while the other parts of the pattern projection region are irradiated with light. As a result of this exposure, the latent image corresponding to the plurality of electrodes  32  is formed in the area of the photoresist layer corresponding to the normally functioning pre-semiconductor-chip portion  30 P. To be more specific, after this exposure, the area of the photoresist layer corresponding to the normally functioning pre-semiconductor-chip portion  30 P remains soluble in the developing solution for the parts where to form the openings to accommodate the electrodes  32  later, and becomes insoluble in the developing solution for the other parts. 
     If the pre-semiconductor-chip portion  30 P is judged as a malfunctioning one (N) in Step S 102 , the area of the photoresist layer corresponding to the malfunctioning pre-semiconductor-chip portion  30 P is subjected to an overall exposure by using a mask  201  that entirely passes light, or without using any mask  201  (Step S 104 ). As a result, any latent image corresponding to a plurality of electrodes that are connected to the malfunctioning pre-semiconductor-chip portion  30 P and each have an end face located at the at least one of the side surfaces of the main body  2  on which the wiring  3  is disposed is not formed in the area of the photoresist layer corresponding to the malfunctioning pre-semiconductor-chip portion  30 P. To be more specific, the entire area of the photoresist layer corresponding to the malfunctioning pre-semiconductor-chip portion  30 P becomes insoluble in the developing solution. If the second-type layer portion  10  includes any electrode or wiring that is other than one configured to be electrically connected to the defective semiconductor chip  30  and to have an end face located at the at least one of the side surfaces of the main body  2  on which the wiring  3  is disposed, an exposure is performed in Step S 104  so that a latent image corresponding to such an electrode or wiring is formed, instead of the overall exposure. In this case also, any latent image corresponding to a plurality of electrodes that are connected to the malfunctioning pre-semiconductor-chip portion  30 P and each have an end face located at the at least one of the side surfaces of the main body  2  on which the wiring  3  is disposed is not formed in the area of the photoresist layer corresponding to the malfunctioning pre-semiconductor chip portion  30 P. 
     After Step S 103  or S 104  is performed, the control device  250  judges whether the pattern projection region that has undergone the exposure in Step S 103  or S 104  is the region corresponding to the last pre-semiconductor-chip portion  30 P or not (Step S 105 ). If the pattern projection region is judged as corresponding to the last pre-semiconductor-chip portion  30 P (Y), the exposure step ends. If the pattern projection region is judged as not corresponding to the last pre-semiconductor-chip portion  30 P (N), a pattern projection region corresponding to a next pre-semiconductor-chip portion  30 P is selected to be exposed (Step S 106 ) and the process is repeated from Step S 102 . 
       FIG. 18A  and  FIG. 18B  show a step that follows the step shown in  FIG. 15 .  FIG. 18A  shows areas corresponding to the normally functioning pre-semiconductor-chip portions  30 P.  FIG. 18B  shows areas corresponding to the malfunctioning pre-semiconductor-chip portions  30 P. 
     In the step shown in  FIG. 18A  and  FIG. 18B , first, a photoresist layer  108 P including a plurality of areas corresponding to all the pre-semiconductor-chip portions  30 P is formed. Next, as shown in  FIG. 18A , the areas of the photoresist layer  108 P that correspond to the normally functioning pre-semiconductor-chip portions  30 P are exposed to light in the electrode pattern in Step S 103  of  FIG. 17  by using a mask  201 A that has the electrode pattern. On the other hand, the areas of the photoresist layer  108 P that correspond to the malfunctioning pre-semiconductor-chip portions  30 P are subjected to an overall exposure in Step S 104  of  FIG. 17 , as shown in  FIG. 18B . 
       FIG. 19A  and  FIG. 19B  show a step that follows the step shown in  FIG. 18A  and  FIG. 18B .  FIG. 19A  shows areas corresponding to the normally functioning pre-semiconductor-chip portions  30 P.  FIG. 19B  shows areas corresponding to the malfunctioning pre-semiconductor-chip portions  30 P. In this step, the photoresist layer  108 P is developed with a developing solution. A frame  108  is thereby formed. In the areas corresponding to the normally functioning pre-semiconductor-chip portions  30 P, as shown in  FIG. 19A , a plurality of openings  108   a  to accommodate the plurality of electrodes  32  later are formed in the frame  108 . On the other hand, in the areas corresponding to the malfunctioning pre-semiconductor-chip portions  30 P, no openings  108   a  are formed in the frame  108  as shown in  FIG. 19B . 
       FIG. 20A ,  FIG. 20B  and  FIG. 21  show a step that follows the step shown in  FIG. 19A  and  FIG. 19B .  FIG. 20A  and  FIG. 21  show areas corresponding to the normally functioning pre-semiconductor-chip portions  30 P.  FIG. 20B  shows areas corresponding to the malfunctioning pre-semiconductor-chip portions  30 P.  FIG. 20A  shows a cross section taken along line  20 A- 20 A of  FIG. 21 . In this step, the plurality of electrodes  32  are formed in the plurality of openings  108   a  of the frame  108  by, for example, plating, in the areas corresponding to the normally functioning pre-semiconductor-chip portions  30 P as shown in  FIG. 20A . The plurality of electrodes  32  are formed such that part of each of the electrodes  32  lies on the insulating layer  106 . The electrodes  32  are connected to the electrode pads  34  through the openings  106   a . In the areas corresponding to the malfunctioning pre-semiconductor-chip portions  30 P, as shown in  FIG. 20B , the plurality of electrodes  32  are not formed since the plurality of openings  108   a  are not formed in the frame  108 . A pre-polishing substructure  109  shown in  FIG. 20A ,  FIG. 20B  and  FIG. 21  is thereby fabricated. The pre-polishing substructure  109  has a first surface  109   a  corresponding to the first surface  101   a  of the pre-substructure wafer  101 , and a second surface  109   b  corresponding to the second surface  101   b  of the pre-substructure wafer  101 . 
     The electrodes  32  are formed of a conductive material such as Cu. In the case of forming the electrodes  32  by plating, a seed layer for plating is formed on the insulating layer  106  before forming the photoresist layer. Next, the photoresist layer is formed on the seed layer. The photoresist layer is then patterned by photolithography to thereby form the frame  108 . Next, plating layers that are intended to constitute respective portions of the electrodes  32  are formed by plating on the seed layer in the openings  108   a  of the frame  108 . The plating layers are 5 to 15 μm thick, for example. Next, the frame  108  is removed, and portions of the seed layer other than those lying under the plating layers are also removed by etching. The electrodes  32  are thus formed by the plating layers and the remaining portions of the seed layer under the plating layers. 
       FIG. 22  shows a step that follows the step shown in  FIG. 20A  to  FIG. 21 . In this step, using an insulating adhesive, the pre-polishing substructure  109  is initially bonded to a plate-shaped jig  112  shown in  FIG. 22  with the first surface  109   a  of the pre-polishing substructure  109  arranged to face a surface of the jig  112 . Hereinafter, the pre-polishing substructure  109  bonded to the jig  112  will be referred to as a first pre-polishing substructure  109 . The reference numeral  113  in  FIG. 22  indicates an insulating layer  113  formed by the adhesive. 
     Next, the second surface  109   b  of the first pre-polishing substructure  109  is polished. This polishing is performed until the plurality of grooves  104  are exposed. By polishing the second surface  109   b  of the first pre-polishing substructure  109 , the first pre-polishing substructure  109  is thinned. This forms a substructure  110  in the state of being bonded to the jig  112 . The substructure  110  has a thickness of 30 to 100 μm, for example. Hereinafter, the substructure  110  bonded to the jig  112  will be referred to as a first substructure  110 . The first substructure  110  has a first surface  110   a  corresponding to the first surface  109   a  of the first pre-polishing substructure  109 , and a second surface  110   b  opposite to the first surface  110   a . The second surface  110   b  is the polished surface. By polishing the second surface  109   b  of the first pre-polishing substructure  109  until the plurality of grooves  104  are exposed, the plurality of pre-semiconductor-chip portions  30 P are separated from each other into individual semiconductor chips  30 . 
       FIG. 23  shows a step that follows the step shown in  FIG. 22 . In this step, using an insulating adhesive, a pre-polishing substructure  109  is initially bonded to the first substructure  110  bonded to the jig  112 . The pre-polishing substructure  109  is bonded to the first substructure  110  with the first surface  109   a  arranged to face the polished surface, i.e., the second surface  110   b , of the first substructure  110 . Hereinafter, the pre-polishing substructure  109  to be bonded to the first substructure  110  will be referred to as a second pre-polishing substructure  109 . The insulating layer  113  formed by the adhesive between the first substructure  110  and the second pre-polishing substructure  109  covers the plurality of electrodes  32  of the second pre-polishing substructure  109 , and is to become part of the insulating portion  31  later. 
     Next, although not shown, the second surface  109   b  of the second pre-polishing substructure  109  is polished. This polishing is performed until the plurality of grooves  104  are exposed. By polishing the second surface  109   b  of the second pre-polishing substructure  109 , the second pre-polishing substructure  109  is thinned. This forms a second substructure  110  in the state of being bonded to the first substructure  110 . The second substructure  110  has a thickness of, for example, 30 to 100 μm, as does the first substructure  110 . 
     The same step as shown in  FIG. 23  may subsequently be repeated to form three or more substructures  110  stacked.  FIG. 24  shows the case where four substructures  110  are formed into a stack. 
       FIG. 25  shows a step that follows the step shown in  FIG. 24 . After the same step as shown in  FIG. 23  is repeated to form a predetermined number of substructures  110  into a stack, the stack of the predetermined number of substructures  110  is released from the jig  112 .  FIG. 25  shows an example where a stack of eight substructures  110  is formed. 
     Next, as shown in  FIG. 25 , the insulating layer  113  is removed from the uppermost substructure  110  of the stack. This exposes the plurality of electrodes  32  of the uppermost substructure  110 . The exposed plurality of electrodes  32  also function as the plurality of terminals  4 . In addition, the plurality of terminals  5  are formed on the bottom surface of the lowermost substructure  110  of the stack. Consequently, there is formed a first layered substructure  115  including the plurality of substructures  110  stacked. Each substructure  110  includes a plurality of preliminary layer portions  10 P arrayed. Each preliminary layer portion  10 P is to be made into any one of the layer portions  10  included in the main part  2 M of the main body  2 . The substructures  110  are to be cut later at the positions of the boundaries between every adjacent preliminary layer portions  10 P. In  FIG. 25 , the reference numeral  110 C indicates the cutting positions of the substructures  110 . The first layered substructure  115  includes a plurality of pre-separation main bodies  2 P arrayed. The plurality of pre-separation main bodies  2 P are to be separated from each other into individual main bodies  2  later. In the example shown in  FIG. 25 , each pre-separation main body  2 P includes eight preliminary layer portions  10 P. 
     Hereinafter, the process for fabricating a subpackage by using at least one substructure will be described in detail with reference to  FIG. 26  to  FIG. 38 . The following will describe an example where the first layered substructure  115  of  FIG. 25 , which includes eight substructures  110  stacked, is used to fabricate a plurality of subpackages each including eight layer portions  10 . 
       FIG. 26  and  FIG. 27  show a step that follows the step shown in  FIG. 25 . In this step, a plurality of first layered substructures  115  are stacked and every two vertically adjacent first layered substructures  115  are bonded to each other to thereby fabricate a second layered substructure  120 .  FIG. 26  and  FIG. 27  show an example where ten first layered substructures  115  are stacked to fabricate the second layered substructure  120 . Every two vertically adjacent first layered substructures  115  are bonded to each other with an adhesive so as to be easily detachable. In this example, as shown in  FIG. 27 , the second layered substructure  120  includes ten first layered substructures  115  stacked, each of the first layered substructures  115  including eight substructures  110  stacked. That is, the second layered substructure  120  includes 80 substructures  110  stacked. Suppose that each individual substructure  110  has a thickness of 50 μm. Ignoring the thickness of the adhesive that bonds every two vertically adjacent substructures  110  to each other and the thickness of the adhesive that bonds every two vertically adjacent first layered substructures  115  to each other, the second layered substructure  120  has a thickness of 50 μm×80, i.e., 4 mm. 
       FIG. 28  to  FIG. 30  show a step that follows the step shown in  FIG. 26  and  FIG. 27 . In this step, the second layered substructure  120  is cut into at least one block  121  in which a plurality of pre-separation main bodies  2 P are arrayed both in the direction of stacking of the first layered substructures  115  and in a direction orthogonal thereto.  FIG. 28  to  FIG. 30  show first to third examples of the block  121 , respectively. 
     In the first example of the block  121  shown in  FIG. 28 , ten pre-separation main bodies  2 P are arrayed in the direction of stacking of the first layered substructures  115 , and three are arrayed in the direction orthogonal to the direction of stacking of the first layered substructures  115 . In this example, the block  121  includes 30 pre-separation main bodies  2 P. 
     In the second example of the block  121  shown in  FIG. 29 , ten pre-separation main bodies  2 P are arrayed in the direction of stacking of the first layered substructures  115 , and four are arrayed in the direction orthogonal to the direction of stacking of the first layered substructures  115 . In this example, the block  121  includes 40 pre-separation main bodies  2 P. 
     In the third example of the block  121  shown in  FIG. 30 , ten pre-separation main bodies  2 P are arrayed in the direction of stacking of the first layered substructures  115 , and five are arrayed in the direction orthogonal to the direction of stacking of the first layered substructures  115 . In this example, the block  121  includes 50 pre-separation main bodies  2 P. 
       FIG. 31  shows a step that follows the step shown in  FIG. 28  to  FIG. 30 . In this step, a plurality of jigs  122  are used to array two or more blocks  121  to form a block assembly  130 . The plurality of jigs  122  are combined to form a frame for surrounding the block assembly  130 .  FIG. 31  shows an example where 19 blocks  121  shown in  FIG. 29  are arrayed to form the block assembly  130 . In this example, the block assembly  130  includes 19 blocks  121 , each block  121  includes 40 pre-separation main bodies  2 P, and each pre-separation main body  2 P includes 8 preliminary layer portions  10 P. That is, the block assembly  130  includes 19×40, i.e., 760 pre-separation main bodies  2 P, and 19×40×8, i.e., 6080 preliminary layer portions  10 P. All the pre-separation main bodies  2 P included in the block assembly  130  are arranged so that their respective surfaces on which the wiring  3  is to be formed later face toward the same direction, i.e., upward. 
       FIG. 32  shows a step that follows the step shown in  FIG. 31 . In this step, a plurality of jigs  122  are used to array a plurality of block assemblies  130  in one plane. All the pre-separation main bodies  2 P included in the plurality of block assemblies  130  are arranged so that their respective surfaces on which the wiring  3  is to be formed later face toward the same direction, i.e., upward.  FIG. 32  shows an example where 16 block assemblies  130  are arrayed in one plane. In such a case, the 16 block assemblies  130  include 760×16, i.e., 12160 pre-separation main bodies  2 P, and 6080×16, i.e., 97280 preliminary layer portions  10 P. 
     In the present embodiment, the wiring  3  is then simultaneously formed for all the pre-separation main bodies  2 P that are included in the plurality of block assemblies  130  arrayed as shown in  FIG. 32 . The step of forming the wiring  3  will be described with reference to  FIG. 33  to  FIG. 37 . 
     In the step of forming the wiring  3 , as shown in  FIG. 33 , the plurality of jigs  122  and the plurality of block assemblies  130  shown in  FIG. 32  are placed on a flat top surface of a jig  132 . The plurality of block assemblies  130  are thereby arrayed in one plane. In such a state, the top surfaces of the jigs  122  are located at a level slightly lower than that of the top surfaces of the block assemblies  130 . 
     In the step of forming the wiring  3 , a resin layer  133  is then formed to cover the top surfaces of the jigs  122  and the top surfaces of the block assemblies  130 . The resin layer  133  may be formed by applying an uncured resin and then curing the resin, or by using a dry film. 
       FIG. 34  shows a step that follows the step shown in  FIG. 33 . In this step, the resin layer  133  is polished by, for example, CMP, until the top surfaces of the plurality of block assemblies  130  are exposed. The plurality of block assemblies  130  and the resin layer  133  are thereby flattened at the top. 
       FIG. 35  shows a step that follows the step shown in  FIG. 34 . In this step, first, a seed layer  134  for plating is formed over the top surfaces of the plurality of block assemblies  130  and the resin layer  133 . Next, a photoresist layer is formed on the seed layer  134 . The photoresist layer is then patterned by photolithography to thereby form a frame  135 . The frame  135  has a plurality of openings in which a plurality of units of wiring  3  corresponding to the plurality of pre-separation main bodies  2 P are to be accommodated later. Although not shown in  FIG. 35 , the frame  135  includes a plurality of portions located above the respective surfaces of all the pre-separation main bodies  2 P included in the plurality of block assemblies  130  on which the wiring  3  is to be formed. These plurality of portions have the respective openings to accommodate the wiring  3  later. 
       FIG. 36  shows a step that follows the step shown in  FIG. 35 . In this step, first, a plating layer  136  that is intended to constitute part of the wiring  3  is formed in each of the openings of the frame  135  by plating. Next, the frame  135  is removed. For the sake of convenience,  FIG. 36  shows the plating layer  136  in a rectangular shape for each block  121 . Actually, however, the plating layer  136  is formed in a shape corresponding to the wiring  3  for each pre-separation main body  2 P. 
       FIG. 37  shows a step that follows the step shown in  FIG. 36 . In this step, first, portions of the seed layer  134  other than those lying under the plating layers  136  are removed by etching. The wiring  3  is thus formed by the plating layers  136  and the remaining portions of the seed layer  134  under the plating layers  136 . The wiring  3  is formed for each of the pre-separation main bodies  2 P. Next, the jigs  122  and the resin layer  133  remaining on the jigs  122  are removed. 
     The process for fabricating a subpackage then proceeds to the step of separating the plurality of pre-separation main bodies  2 P each provided with the wiring  3  from each other so as to form a plurality of subpackages. This step will be described with reference to  FIG. 38 . In the step, first, the block  121  is cut at the positions of the boundaries between every two pre-separation main bodies  2 P that are adjacent to each other in the direction orthogonal to the direction of stacking of the pre-separation main bodies  2 P. This produces a plurality of stacks shown in portion (a) of  FIG. 38 . Each of the stacks includes a plurality of pre-separation main bodies  2 P stacked. In each of the stacks, every two adjacent pre-separation main bodies  2 P are easily detachably bonded to each other by the adhesive used to bond every two vertically adjacent first layered substructures  115  when fabricating the second layered substructure  120  in the step of  FIG. 26  and  FIG. 27 . Next, the plurality of pre-separation main bodies  2 P included in the stack shown in portion (a) of  FIG. 38  are separated from each other. This makes the pre-separation main bodies  2 P into main bodies  2 , whereby a plurality of subpackages  1 S, each of which includes the main body  2  and the wiring  3 , are formed. Portion (b) of  FIG. 38  shows one of the subpackages  1 S. 
     A plurality of subpackages  1 S are thus fabricated through the series of steps that have been described with reference to  FIG. 9  to  FIG. 38 . So far the description has dealt with the case where a plurality of subpackages (layered chip packages)  1 S each including eight layer portions  10  are fabricated by using the first layered substructure  115  that includes eight stacked substructures  110  shown in  FIG. 25 . In the present embodiment, however, the number of the substructures  110  to be included in the first layered substructure  115  can be changed to fabricate a plurality of types of subpackages (layered chip packages)  1 S with different numbers of layer portions  10 . Moreover, in the present embodiment, a structure composed of a single substructure  110  with the plurality of terminals  5  formed on the bottom surface of the substructure  110  may be fabricated instead of the first layered substructure  115 , and such a structure may be used instead of the first layered substructure  115  to fabricate a plurality of subpackages  1 S through the series of steps described with reference to  FIG. 26  to  FIG. 38 . In this case, each of the subpackages  1 S includes only a single layer portion. 
       FIG. 39  to  FIG. 43  show examples of a plurality of types of subpackages having different numbers of layer portions  10  that can be fabricated according to the present embodiment.  FIG. 39  shows a subpackage  1 S that includes eight layer portions  10 .  FIG. 40  shows a subpackage  1 S that includes only a single layer portion  10 .  FIG. 41  shows a subpackage  1 S that includes two layer portions  10 .  FIG. 42  shows a subpackage  1 S that includes three layer portions  10 .  FIG. 43  shows a subpackage  1 S that includes four layer portions  10 . 
     The subpackage  1 S of the present embodiment has the wiring  3  disposed on at least one of the side surfaces of the main body  2 . The main body  2  has at least either of the first terminals  4  which are arranged on the top surface  2 Ma of the main part  2 M and the second terminals  5  which are arranged on the bottom surface  2 Mb of the main part  2 M. The first terminals  4  and the second terminals  5  are both electrically connected to the wiring  3 . With the subpackage  1 S of such a configuration, it is easy to establish electrical connection between a plurality of subpackages  1 S. For example, according to the present embodiment, it is possible to establish electrical connection between two or more subpackages  1 S by stacking the two or more subpackages  1 S on each other and connecting the second terminals  5  of the main body  2  of the upper subpackage  1 S to the first terminals  4  of the main body  2  of the lower subpackage  1 S. 
     According to the present embodiment, a plurality of subpackages  15  whose respective main bodies  2  each have the second terminals  5  may be mounted on a wiring board, and the wiring of the wiring board and the second terminals  5  of the subpackages  1 S may be used to establish electrical connection between the plurality of subpackages  1 S. In such a case, if the respective main bodies  2  of the subpackages  1 S mounted on a single wiring board each have the first terminals  4 , the first terminals  4  of one of the subpackages  15  may be electrically connected to the first terminals  4  of another one of the subpackages  1 S by wire bonding, for example. 
     The subpackage  15  is preferably such one that the main body  2  has both the first terminals  4  and the second terminals  5 . With such a subpackage  1 S, it is possible to stack three or more subpackages  1 S and establish electrical connection therebetween.  FIG. 44  shows an example where four subpackages  1 S are stacked and electrically connected to each other, the respective main bodies  2  of the four subpackages  1 S each having both the first terminals  4  and the second terminals  5 . 
     Moreover, the present embodiment facilitates the alignment between every two vertically adjacent subpackages  1 S when stacking a plurality of subpackages  1 S. This advantageous effect will now be described with reference to  FIG. 45  and  FIG. 46 .  FIG. 45  is a side view showing connecting parts of the terminals of two vertically adjacent subpackages  1 S.  FIG. 46  is an explanatory diagram for explaining misalignment between the terminals of two vertically adjacent subpackages  1 S. 
     In the example shown in  FIG. 45  and  FIG. 46 , the terminal  4  includes a rectangular conductor pad  4 A and a solder bump  4 B formed on the conductor pad  4 A. Similarly, the terminal  5  includes a rectangular conductor pad  5 A and a solder bump  5 B formed on the conductor pad  5 A. Here, two orthogonal sides of the conductor pad  4 A will be denoted by L 1  and L 2 . L 1  and L 2  are both 30 to 60 μm, for example. The conductor pad  5 A has the same shape as that of the conductor pad  4 A. 
     In the example shown in  FIG. 45 , the corresponding terminals  4  and  5  of the two vertically adjacent subpackages  1 S are electrically connected in the following way. The solder bumps  4 B and  5 B of the corresponding terminals  4  and  5  are put into contact with each other. By applying heat and pressure, the solder bumps  4 B and  5 B are melted, and then cured to bond the terminals  4  and  5 . 
       FIG. 46  shows a state where the terminals  4  and  5  are out of alignment. The state where the terminals  4  and  5  are out of alignment refers to the state where the edges of the conductor pad  4 A and those of the conductor pad  5 A do not coincide in position with each other when viewed in a direction perpendicular to the plane of the conductor pads  4 A and  5 A. In the present embodiment, the corresponding terminals  4  and  5  may be out of alignment as long as the terminals  4  and  5  can be bonded with a sufficiently small resistance at the interface between the terminals  4  and  5 . Assuming that L 1  and L 2  are 30 to 60 μm, the maximum permissible misalignment between the terminals  4  and  5  is smaller than L 1  and L 2  yet several tens of micrometers. 
     According to the present embodiment, some misalignment between the terminals  4  and  5  is thus acceptable when stacking a plurality of subpackages  1 S. This facilitates the alignment between two vertically adjacent subpackages  15 . Consequently, according to the present embodiment, it is possible to reduce the manufacturing cost of an electronic component that includes a plurality of subpackages  1 S stacked. 
       FIG. 47  shows an example of the method of manufacturing an electronic component that includes a plurality of subpackages  1 S stacked. The method shown in  FIG. 47  uses a heatproof container  141 . The container  141  has an accommodating part  141   a  in which a plurality of subpackages  1 S can be stacked and accommodated. The accommodating part  141   a  has such a size that the side surfaces of the subpackages  1 S accommodated in the accommodating part  141   a  and the inner walls of the accommodating part  141  leave a slight gap therebetween. In this method, the plurality of subpackages  1 S are stacked and accommodated in the accommodating part  141   a  of the container  141 , and then the container  141  and the plurality of subpackages  1 S are heated at temperatures at which the solder bumps  4 B and  5 B melt. This melts the solder bumps  4 B and  5 B of the terminals  4  and  5 , whereby the terminals  4  and  5  of every two vertically adjacent subpackages  1 S are bonded to each other. According to this method, it is possible to perform the alignment between the plurality of subpackages  1 S easily by stacking and accommodating the subpackages  15  in the accommodating part  141   a  of the container  141 . This makes it easy to manufacture an electronic component that includes a plurality of subpackages  1 S stacked. 
     The composite layered chip package  1  according to the present embodiment includes a plurality of subpackages  1 S stacked. For any two vertically adjacent subpackages  1 S of the composite layered package  1 , the plurality of second terminals  5  of the main body  2  of the upper subpackage  15  are electrically connected to the plurality of first terminals  4  of the main body  2  of the lower subpackage  1 S. The main part  2 M of the main body  2  of each of the plurality of subpackages  1 S includes at least one first-type layer portion  10 A. The main part  2 M of the main body  2  of at least one of the plurality of subpackages  1 S further includes at least one second-type layer portion  10 B. The first-type layer portion  10 A includes a conforming semiconductor chip  30 . The second-type layer portion  10 B includes a defective semiconductor chip  30 . The first-type layer portion  10 A includes a plurality of electrodes  32  that are electrically connected to the semiconductor chip  30  and that each have an end face located at the at least one of the side surfaces of the main body  2  on which the wiring  3  is disposed, whereas the second-type layer portion  10 B does not include the electrodes  32 . 
     The manufacturing method for the composite layered chip package  1  according to the present embodiment includes the steps of fabricating a plurality of subpackages  1 S; and stacking the plurality of subpackages  1 S and electrically connecting, for any two vertically adjacent subpackages  1 S, the plurality of second terminals  5  of the upper subpackage  1 S to the plurality of first terminals  4  of the lower subpackage  1 S. 
     The step of fabricating the plurality of subpackages  1 S includes, as a series of steps for forming each subpackage  1 S, the step of fabricating at least one substructure  110  that includes a plurality of preliminary layer portions  10 P arrayed, each of the preliminary layer portions  10 P being intended to be made into any one of the layer portions  10  included in the main part  2 M, the substructure  110  being intended to be cut later at the position of the boundary between every adjacent preliminary layer portions  10 P; and the step of fabricating the subpackage  1 S by using the at least one substructure  110 . The step of fabricating the at least one substructure  110  includes the steps of: fabricating a pre-substructure wafer  101  including a plurality of pre-semiconductor-chip portions  30 P that are arrayed and intended to be made into the individual semiconductor chips  30 ; distinguishing the plurality of pre-semiconductor-chip portions  30 P included in the pre-substructure wafer  101  into normally functioning pre-semiconductor-chip portions  30 P and malfunctioning pre-semiconductor-chip portions  30 P; and forming the plurality of electrodes  32  in the normally functioning pre-semiconductor-chip portions  30 P while not forming the plurality of electrodes  32  in the malfunctioning pre-semiconductor-chip portions  30 P, so as to make the pre-substructure wafer  101  into the substructure  110 . 
     The step of forming the plurality of electrodes  32  includes the steps of forming a photoresist layer  108 P that is intended to be used for forming the plurality of electrodes  32  and includes a plurality of areas corresponding to all the pre-semiconductor-chip portions  30 P; forming a frame  108  by patterning the photoresist layer  108 P by photolithography, the frame  108  having a plurality of openings  108   a  that are intended to accommodate the plurality of electrodes  32  later; and forming the plurality of electrodes  32  in the plurality of openings  108   a  of the frame  108 . 
     According to the present embodiment, a package including a plurality of semiconductor chips  30  stacked can be easily implemented by stacking a plurality of subpackages  1 S, the package being capable of providing, even if it includes a defective semiconductor chip  30 , the same functions as those for the case where no defective semiconductor chip  30  is included. This advantageous effect will now be described in detail. 
     By way of example, a description will be given of a case where a layered chip package that includes eight conforming semiconductor chips  30  is required. In this case, if there is fabricated a layered chip package including only eight semiconductor chips  30  and if one or more of the eight semiconductor chips  30  are defective, simply disabling the defective semiconductor chip(s)  30  cannot make the layered chip package meet the above requirement. The defective semiconductor chip(s)  30  can be replaced with conforming semiconductor chip(s)  30  to remake the layered chip package, but this raises the manufacturing cost for the layered chip package. 
     According to the present embodiment, if, for example, a first subpackage  1 S includes eight semiconductor chips  30  and one or more of the eight semiconductor chips  30  are defective, a second subpackage  1 S having as many conforming semiconductor chip(s)  30  as the foregoing defective semiconductor chip(s)  30  can be stacked with the first subpackage  1 S to constitute a composite layered chip package  1 . The resulting composite layered chip package  1  provides the same functions as those of a layered chip package that includes eight conforming semiconductor chips  30  and no defective semiconductor chip  30 . 
     For example, in the composite layered chip package  1  shown in  FIG. 1  to  FIG. 6 , the subpackage  1 A includes six first-type layer portions  10 A and two second-type layer portions  10 B, while the subpackage  1 B includes two first-type layer portions  10 A. The composite layered chip package  1  thus includes eight first-type layer portions  10 A and two second-type layer portions  10 B. Since the two second-type layer portions  10 B do not include the plurality of electrodes  32  connected to the wiring  3 , the use of the two defective semiconductor chips  30  included in the two second-type layer portions  10 B is disabled. The composite layered chip package  1  shown in  FIG. 1  to  FIG. 6  therefore provides the same functions as those of a layered chip package that includes eight conforming semiconductor chips  30  stacked and no defective semiconductor chip  30 . 
     As previously described, according to the present embodiment, it is possible to easily stack a plurality of subpackages  1 S and electrically connect them to each other. Consequently, according to the present embodiment, a composite layered chip package  1  including a plurality of semiconductor chips  30  stacked can be easily implemented by stacking a plurality of subpackages  1 S, the composite layered chip package  1  being capable of providing, even if it includes a defective semiconductor chip  30 , the same functions as those for the case where no defective semiconductor chip  30  is included. 
     In the present embodiment, a composite layered chip package  1  including a required number of conforming semiconductor chips  30  can be formed by combining a plurality of subpackages  1 S in various configurations.  FIG. 48  and  FIG. 49  show examples where a composite layered chip package  1  including eight conforming semiconductor chips  30  is formed by combining a plurality of subpackages  15  in different configurations from the configuration of the example of  FIG. 1  to  FIG. 6 . 
     The composite layered chip package  1  shown in  FIG. 48  includes two subpackages  1 C and  1 D that are stacked and electrically connected to each other. The subpackage  1 C includes seven first-type layer portions  10 A and a single second-type layer portion  10 B. The subpackage  1 D includes a single first-type layer portion  10 A and a single second-type layer portion  10 B. 
     This composite layered chip package  1  thus includes eight first-type layer portions  10 A and two second-type layer portions  10 B. 
     The composite layered chip package  1  shown in  FIG. 49  includes three subpackages  1 E,  1 F and  1 G that are stacked and electrically connected to each other. The subpackage  1 E includes three first-type layer portions  10 A. The subpackage  1 F includes two first-type layer portions  10 A and a single second-type layer portion  10 B. The subpackage  1 G includes three first-type layer portions  10 A. This composite layered chip package  1  thus includes eight first-type layer portions  10 A and a single second-type layer portion  10 B. 
     The composite layered chip package  1  shown in  FIG. 48  and that shown in  FIG. 49  each provide the same functions as those of a layered chip package that includes eight conforming semiconductor chips  30  stacked and no defective semiconductor chip  30 . 
     Although not shown in the drawings, there are many configurations that can form a composite layered chip package  1  with eight conforming semiconductor chips  30  aside from the illustrated configurations. For example, a subpackage  1 S that includes seven first-type layer portions  10 A and a single second-type layer portion  10 B may be combined with a subpackage  1 S that includes only a single first-type layer portion  10 A as its layer portion  10  as shown in  FIG. 40 . This also provides a composite layered chip package  1  with eight conforming semiconductor chips  30 . 
     Suppose, in the present embodiment, that the plurality of semiconductor chips  30  included in the composite layered chip package  1  are memory chips with a capacity of N bits each (N is a natural number). Suppose also that the number of the first-type layer portions  10 A included in the composite layered chip package  1 , i.e., the number of conforming semiconductor chips  30  included in the composite layered chip package  1 , is eight. In such a case, the composite layered chip package  1  can implement a memory of N bytes in capacity. Here, it is easy to recognize the capacities of the memory chips and the capacity of the memory to be implemented by the composite layered chip package  1 . This advantageous effect is also obtainable when the number of the first-type layer portions  10  included in the composite layered chip package  1  is a multiple of 8. 
     If a layer portion  10  including a defective semiconductor chip  30  has electrodes  32  that are electrically connected to the semiconductor chip  30  and that each have an end face located at the at least one of the side surfaces of the main body  2  on which the wiring  3  is disposed, the electrodes  32  are connected to the wiring  3 . In this case, the electrodes  32  connected to the defective semiconductor chip  30  can produce capacitances and inductances that are unnecessary for a device to be implemented by the subpackage  1 S, such as a memory device, and/or produce a stray capacitance between themselves and other electrodes  32  connected to a conforming semiconductor chip  30 . This hinders the acceleration of operation of the device such as a memory device. 
     In contrast, according to the present embodiment, as described above, the second-type layer portion  10 B including a defective semiconductor chip  30  does not have the electrodes  32  that are electrically connected to the semiconductor chip  30  and that each have an end face located at the at least one of the side surfaces of the main body  2  on which the wiring  3  is disposed. Therefore, in the subpackage  1 S, the second-type layer portion  10  which includes a defective semiconductor chip  30  can be regarded as merely an insulating layer. The present embodiment thus makes it possible to disable the use of a defective semiconductor chip  30  and reduce the problems resulting from wiring connected to the defective semiconductor chip  30 . 
     Possible layouts of the wiring  3  and the terminals  4  and  5  in a subpackage  1 S are not limited to the example shown in  FIG. 1  to  FIG. 6 .  FIG. 50  and  FIG. 51  show examples of a subpackage  1 S having the wiring  3  and the terminals  4  and  5  in a layout different from that of the example shown in  FIG. 1  to  FIG. 6 . 
     In the subpackage  1 S shown in  FIG. 50 , the wiring  3  is disposed on the two side surfaces  2   c  and  2   d  of the main body  2 . The main body  2  of this subpackage  1 S has a plurality of terminals  4 . Some of the terminals  4  are arranged on an area of the top surface  2 Ma of the main part  2 M near the side surface  2   c , and the other terminals  4  are arranged on an area of the top surface  2 Ma near the side surface  2   d . The terminals  4  arranged near the side surface  2   c  are electrically connected to the wiring  3  that is disposed on the side surface  2   c . The terminals  4  arranged near the side surface  2   d  are electrically connected to the wiring  3  that is disposed on the side surface  2   d . Although not shown in the diagram, the main body  2  further has a plurality of terminals  5 . Some of the terminals  5  are arranged on an area of the bottom surface  2 Mb of the main part  2 M near the side surface  2   c , and the other terminals  5  are arranged on an area of the bottom surface  2 Mb near the side surface  2   d . The terminals  5  arranged near the side surface  2   c  are electrically connected to the wiring  3  that is disposed on the side surface  2   c . The terminals  5  arranged near the side surface  2   d  are electrically connected to the wiring  3  that is disposed on the side surface  2   d.    
     In the subpackage  1 S shown in  FIG. 51 , the wiring  3  is disposed on the side surface  2   c  of the main body  2 . The main body  2  of this subpackage  1 S has a plurality of terminals  4 . Some of the terminals  4  have conductor pads  4 A arranged on an area of the top surface  2 Ma of the main part  2 M near the side surface  2   c , and are electrically connected to the wiring  3 . The other terminals  4  have conductor pads  4 A arranged on an area of the top surface  2 Ma near the side surface  2   d , and are electrically connected to the wiring  3 . Although not shown in the diagram, the main body  2  further has a plurality of terminals  5 . Some of the terminals  5  have conductor pads  5 A arranged on an area of the bottom surface  2 Mb of the main part  2 M near the side surface  2   c , and are electrically connected to the wiring  3 . The other terminals  5  have conductor pads  5 A arranged on an area of the bottom surface  2 Mb near the side surfaces  2   d , and are electrically connected to the wiring  3 . 
     According to the present embodiment, in a layered chip package, i.e., a subpackage  1 S including a plurality of semiconductor chips  30  stacked, the stacked semiconductor chips  30  are electrically connected to each other by the wiring  3  that is disposed on at least one of the side surfaces of the main body  2 . Consequently, the present embodiment is free from the problems of the wire bonding method, that is, the problem that it is difficult to reduce the distance between electrodes so as to avoid contact between wires, and the problem that the high resistances of the wires hinder the acceleration of operation of the circuit. 
     As compared with the through electrode method, the present embodiment has the following advantages. First, the present embodiment does not require the formation of through electrodes in each chip and consequently does not require a large number of steps for forming through electrodes in each chip. 
     According to the present embodiment, electrical connection between the plurality of semiconductor chips  30  is established by the wiring  3  disposed on at least one of the side surfaces of the main body  2 . The present embodiment thus provides higher reliability of electrical connection between chips as compared with the case where through electrodes are used to establish electrical connection between chips. 
     Furthermore, according to the present embodiment, it is possible to easily change the line width and thickness of the wiring  3 . Consequently, it is possible to easily cope with future demands for finer wiring  3 . 
     The through electrode method requires that the through electrodes of upper and lower chips be connected to each other by means of, for example, soldering at high temperatures. In contrast, according to the present embodiment, it is possible to form the wiring  3  at lower temperatures since the wiring  3  can be formed by plating. According to the present embodiment, it is also possible to bond the plurality of layer portions  10  to each other at low temperatures. Consequently, it is possible to prevent the chips  30  from suffering damage from heat. 
     The through electrode method further requires accurate alignment between upper and lower chips in order to connect the through electrodes of the upper and lower chips to each other. In contrast, according to the present embodiment, electrical connection between the semiconductor chips  30  is established not at an interface between two vertically adjacent layer portions  10  but through the use of the wiring  3  disposed on at least one of the side surfaces of the main body  2 . The alignment between the plurality of layer portions  10  therefore requires lower accuracy than that required for the alignment between a plurality of chips in the through electrode method. 
     In the present embodiment, the manufacturing method for a subpackage  1 S including a plurality of semiconductor chips  30  stacked, i.e., the manufacturing method for a layered chip package, includes the steps of fabricating a plurality of substructures  110 ; fabricating a plurality of first layered substructures  115  by using the plurality of substructures  110 , each of the plurality of first layered substructures  115  including a plurality of substructures  110  stacked; and producing a plurality of layered chip packages by using the plurality of first layered substructures  115 . Each of the first layered substructures  115  includes a plurality of pre-separation main bodies  2 P arrayed. The plurality of pre-separation main bodies  2 P are to be separated from each other into the individual main bodies  2  later. 
     The step of producing a plurality of layered chip packages includes the steps of fabricating a second layered substructure  120  by stacking a plurality of first layered substructures  115  and bonding every two adjacent first layered substructures  115  to each other; cutting the second layered substructure  120  into at least one block  121  in which a plurality of pre-separation main bodies  2 P are arrayed both in the direction of stacking of the first layered substructures  115  and in a direction orthogonal thereto; forming the wiring  3  simultaneously for the plurality of pre-separation main bodies  2 P included in the at least one block  121 ; and separating the plurality of pre-separation main bodies  2 P each provided with the wiring  3  from each other so as to form a plurality of layered chip packages. 
     Such a manufacturing method for a layered chip package makes it possible to simultaneously form a plurality of sets of the terminals  4  and  5  corresponding to a plurality of layered chip packages in the step of fabricating the first layered substructures  115 . Moreover, according to the manufacturing method, the wiring  3  is formed simultaneously for the plurality of pre-separation main bodies  2 P included in one or more blocks  121 . This makes it possible to form a plurality of units of wiring  3  corresponding to the plurality of layered chip packages simultaneously. Here, it is unnecessary to perform alignment between the plurality of pre-separation main bodies  2 P included in each block  121 . Consequently, according to the manufacturing method, layered chip packages capable of being electrically connected to each other easily can be mass-produced at low cost and in a short time. 
     In the step of forming the wiring  3  in the foregoing manufacturing method, two or more blocks  121  may be arrayed with all the pre-separation main bodies  2 P included therein arranged so that their respective surfaces on which the wiring  3  is to be formed face toward the same direction. Then, the wiring  3  may be formed simultaneously for all the pre-separation main bodies  2 P included in the two or more blocks  121 . This makes it possible to simultaneously form the wiring  3  for a greater number of pre-separation main bodies  2 P. 
     The foregoing manufacturing method for a layered chip package allows a reduction in the number of steps and consequently allows a reduction in cost for the layered chip package, as compared with the manufacturing method for a layered chip package disclosed in U.S. Pat. No. 5,953,588. 
     According to the manufacturing method for a layered chip package of the present embodiment, the first layered substructure  115  is fabricated by the method described with reference to  FIG. 22  to  FIG. 25 . This makes it possible to easily reduce the thickness of a plurality of substructures  110  that constitute the first layered substructure  115  while preventing damage to the substructures  110 . The present embodiment thus allows a high-yield manufacture of a layered chip package that achieves a reduction in size and a high level of integration. 
     In the present embodiment, the first layered substructure  115  can be fabricated by a method other than that described with reference to  FIG. 22  to  FIG. 25 . For example, the first layered substructure  115  may be fabricated by bonding two pre-polishing substructures  109  to each other with their respective first surfaces  109   a  arranged to face each other, polishing the two second surfaces  109   b  of the two pre-polishing substructures  109  to fabricate a stack including two substructures  110 , and laminating a plurality of such stacks. Alternatively, the first layered substructure  115  may be fabricated by bonding two substructures  110  to each other with their respective second surfaces  110   b  arranged to face each other to thereby fabricate a stack including the two substructures  110 , and laminating a plurality of such stacks. 
     The present invention is not limited to the foregoing embodiment, and various modifications may be made thereto. For example, in the foregoing embodiment, a plurality of blocks  121  are arrayed to form a block assembly  130 , and a plurality of block assemblies  130  are further arrayed to form the wiring  3  simultaneously for all the pre-separation main bodies  2 P included in the plurality of block assemblies  130 . However, the wiring  3  may be simultaneously formed for all pre-separation main bodies  2 P included in a single block assembly  130 , or for all pre-separation main bodies  2 P included in a single block  121 . 
     After the plurality of pre-separation main bodies  2 P each provided with the wiring  3  are separated from each other into a plurality of main bodies  2 , additional wiring may be formed on the main bodies  2 . 
     In addition, a photoresist layer of positive type may be used in the step of exposing the photoresist layer to light for forming the frame  108  to be used to form the plurality of electrodes  32 . In such a case, the light transmitting areas and the light blocking areas of the mask are inverted as compared with the case of using a photoresist layer of negative type. 
     It is apparent that the present invention can be carried out in various forms and modifications in the light of the foregoing descriptions. Accordingly, within the scope of the following claims and equivalents thereof, the present invention can be carried out in forms other than the foregoing most preferred embodiments.