Patent Publication Number: US-2022236919-A1

Title: Storage System and Method for Host Memory Access

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 16/874,101, filed May 14, 2020, which is hereby incorporated by reference. 
    
    
     BACKGROUND 
     Due to the limited amount of volatile memory in a storage system, some storage systems use volatile memory in a host to compensate for its limited volatile memory resources. For example, storage systems that operate under the Universal Flash Storage (UFS) specification can use a Unified Memory Architecture (UMA) to provide the storage system with master access to portions of the host&#39;s volatile memory. UMA enables a UFS storage system to manage the host volatile memory through a set of low-level commands that are initiated by the storage system. Typically, UMA requires hardware changes to the controllers in both the host and the storage system. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a block diagram of a non-volatile storage system of an embodiment. 
         FIG. 1B  is a block diagram illustrating a storage module of an embodiment. 
         FIG. 1C  is a block diagram illustrating a hierarchical storage system of an embodiment. 
         FIG. 2A  is a block diagram illustrating components of the controller of the non-volatile storage system illustrated in  FIG. 1A  according to an embodiment. 
         FIG. 2B  is a block diagram illustrating components of the non-volatile storage system illustrated in  FIG. 1A  according to an embodiment. 
         FIG. 3A  is a block diagram illustrating standard read and write mapping of an embodiment. 
         FIG. 3B  is a block diagram illustrating direct memory access (DMA) read and write mapping of an embodiment. 
         FIG. 4  is a flow diagram of an embodiment for a read host memory command. 
         FIG. 5  is a flow diagram of an embodiment for a write host memory command. 
         FIG. 6  is a flow diagram of an embodiment for a read performance booster. 
         FIG. 7  is a flow diagram of an embodiment for fast powerup/wakeup. 
         FIG. 8  is a flow diagram of an embodiment for an enhanced read ahead cache. 
         FIG. 9  is a flow diagram of an embodiment for an enhanced write cache. 
         FIG. 10  is a block diagram of a host and a storage system of an embodiment. 
         FIG. 11  is a flow diagram of an embodiment for a backup write cache. 
         FIG. 12  is a flow diagram of an embodiment for an enhanced write cache. 
     
    
    
     DETAILED DESCRIPTION 
     Overview 
     By way of introduction, the below embodiments relate to a storage system and method for host memory access. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a write command from a host that is recognized by the storage system as a read host memory command; receive a read command from the host that is recognized by the storage system as a write host memory command; receive data from the host for storage in the storage system memory; prior to the data being written in the storage system memory; send the data to the host for storage in a host memory; and read the data back from the host memory in response to an error in writing the data to the storage system memory. 
     In some embodiments, the error is caused by a power loss. 
     In some embodiments, the controller is further configured to send the data to the host for storage in a different location in the host memory than a location that initially stored the data. 
     In some embodiments, the storage system further comprises a volatile memory, configured to store the data received from the host, wherein the controller is further configured to clear the data from the volatile memory prior to receiving confirmation of a successful write of the data in the storage system memory. 
     In some embodiments, the storage system memory comprises a three-dimensional memory. 
     In some embodiments, the controller is further configured to receive an indication from the host that the host will ignore a timeout of the write command and/or the read command. 
     In some embodiments, the controller is further configured to avoid hibernation to allow the storages system to continue accessing the host memory. 
     In some embodiments, the controller is further configured to avoid hibernation in response to a flag set in the storage system. 
     In some embodiments, the controller is further configured to reseed data to a same offset in the host memory multiple times. 
     In another embodiment, a method is provided that is performed in a storage system in communication with a host, the storage system comprising a storage system memory, and the host comprising a host memory. The method comprises receiving a write command from the host that is recognized by the storage system as a read host memory command; receiving a read command from the host that is recognized by the storage system as a write host memory command; storing data of different types in different areas of the host memory; and streaming data from one of the areas of memory and writing the data in the storage system memory. 
     In some embodiments, the different types comprise different expected access or change frequencies. 
     In some embodiments, the different types comprise different metadata characteristics. 
     In some embodiments, the streaming is performed in response to the data being aligned in the host memory to a predetermined write granularity. 
     In some embodiments, the predetermined write granularity comprises a page size. 
     In some embodiments, the streaming is performed in response to a flush command from the host. 
     In some embodiments, the method further comprises receiving an indication from the host that the host will ignore a timeout of the write command and/or the read command. 
     In some embodiments, the method further comprises avoiding hibernation to allow the storages system to continue accessing the host memory. 
     In some embodiments, hibernation is avoided in response to recognizing that the write command is a read host memory command and/or in response to recognizing that the read command is a write host memory command. 
     In some embodiments, hibernation is avoided in response to a flag set in the storage system. 
     In another embodiment, a storage system is provided comprising a storage system memory; means for receiving a command from a host that establishes a communication channel that allows the storage system to access a host memory in the host; and means for, in response to receiving the command, using the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. 
     Other embodiments are possible, and each of the embodiments can be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the attached drawings. 
     Embodiments 
     Storage systems suitable for use in implementing aspects of these embodiments are shown in  FIGS. 1A-1C .  FIG. 1A  is a block diagram illustrating a non-volatile storage system  100  (sometimes referred to herein as a storage device or just device) according to an embodiment of the subject matter described herein. Referring to  FIG. 1A , non-volatile storage system  100  includes a controller  102  and non-volatile memory that may be made up of one or more non-volatile memory die  104 , As used herein, the term die refers to the collection of non-volatile memory cells, and associated circuitry for managing the physical operation of those non-volatile memory cells, that are formed on a single semiconductor substrate. Controller  102  interfaces with a host system and transmits command sequences for read, program, and erase operations to non-volatile memory die  104 . 
     The controller  102  (which may be a non-volatile memory controller (e.g., a flash, resistive random-access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random-access memory (MRAM) controller)) can take the form of processing circuitry, a microprocessor or processor, and a computer-readable medium that stores computer-readable program code (e.g., firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, for example. The controller  102  can be configured with hardware and/or firmware to perform the various functions described below and shown in the flow diagrams. Also, some of the components shown as being internal to the controller can also be stored external to the controller, and other components can be used. Additionally, the phrase “operatively in communication with” could mean directly in communication with or indirectly (wired or wireless) in communication with through one or more components, which may or may not be shown or described herein. 
     As used herein, a non-volatile memory controller is a device that manages data stored on non-volatile memory and communicates with a host, such as a computer or electronic device. A non-volatile memory controller can have various functionality in addition to the specific functionality described herein. For example, the non-volatile memory controller can format the non-volatile memory to ensure the memory is operating properly, map out bad non-volatile memory cells, and allocate spare cells to be substituted for future failed cells. Some part of the spare cells can be used to hold firmware to operate the non-volatile memory controller and implement other features. In operation, when a host needs to read data from or write data to the non-volatile memory, it can communicate with the non-volatile memory controller. If the host provides a logical address to which data is to be read/written, the non-volatile memory controller can convert the logical address received from the host to a physical address in the non-volatile memory. (Alternatively, the host can provide the physical address.) The non-volatile memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid pages of data to a new block, so the full block can be erased and reused). Also, the structure for the “means” recited in the claims can include, for example, some or all of the structures of the controller described herein, programmed or manufactured as appropriate to cause the controller to operate to perform the recited functions. 
     Non-volatile memory die  104  may include any suitable non-volatile storage medium, including resistive random-access memory (ReRAM), magnetoresistive random-access memory (MRAM), phase-change memory (PCM), NAND flash memory cells and/or NOR flash memory cells. The memory cells can take the form of solid-state (e.g., flash) memory cells and can be one-time programmable, few-time programmable, or many-time programmable. The memory cells can also be single-level cells (SLC), multiple-level cells (MLC), triple-level cells (TLC), or use other memory cell level technologies, now known or later developed. Also, the memory cells can be fabricated in a two-dimensional or three-dimensional fashion. 
     The interface between controller  102  and non-volatile memory die  104  may be any suitable flash interface, such as Toggle Mode  200 ,  400 , or  800 . In one embodiment, storage system  100  may be a card based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternate embodiment, storage system  100  may be part of an embedded storage system. 
     Although, in the example illustrated in  FIG. 1A , non-volatile storage system  100  (sometimes referred to herein as a storage module) includes a single channel between controller  102  and non-volatile memory die  104 , the subject matter described herein is not limited to having a single memory channel. For example, in some storage system architectures (such as the ones shown in  FIGS. 1B and 1C ), 2, 4, 8 or more memory channels may exist between the controller and the memory device, depending on controller capabilities. In any of the embodiments described herein, more than a single channel may exist between the controller and the memory die, even if a single channel is shown in the drawings. 
       FIG. 113  illustrates a storage module  200  that includes plural non-volatile storage systems  100 . As such, storage module  200  may include a storage controller  202  that interfaces with a host and with storage system  204 , which includes a plurality of non-volatile storage systems  100 . The interface between storage controller  202  and non-volatile storage systems  100  may be a bus interface, such as a serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe) interface, or double-data-rate (DDR) interface. Storage module  200 , in one embodiment, may be a solid state drive (SSD), or non-volatile dual in-line memory module (NVDIMM), such as found in server PC or portable computing devices, such as laptop computers, and tablet computers. 
       FIG. 1C  is a block diagram illustrating a hierarchical storage system. A hierarchical storage system  250  includes a plurality of storage controllers  202 , each of which controls a respective storage system  204 . Host systems  252  may access memories within the storage system via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Express (NVMe) or fiber channel over Ethernet (FCoE) interface. In one embodiment, the system illustrated in  FIG. 1C  may be a rack mountable mass storage system that is accessible by multiple host computers, such as would be found in a data center or other location where mass storage is needed.  10050   FIG. 2A  is a block diagram illustrating components of controller  102  in more detail. Controller  102  includes a front end module  108  that interfaces with a host, a back end module  110  that interfaces with the one or more non-volatile memory die  104 , and various other modules that perform functions which will now be described in detail, A module may take the form of a packaged functional hardware unit designed for use with other components, a portion of a program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry that usually performs a particular function of related functions, or a self-contained hardware or software component that interfaces with a larger system, for example. Modules of the controller  102  may include a host DRAM accessor  111 , which is discussed in more detail below, and can be implemented in hardware or software/firmware. The host DRAM accessor  111  can be configured to perform the algorithms and methods discussed below and shown in the attached drawings. 
     Referring again to modules of the controller  102 , a buffer manager/bus controller  114  manages buffers in random access memory (RAM)  116  and controls the internal bus arbitration of controller  102 . A read only memory (ROM)  118  stores system boot code. Although illustrated in  FIG. 2A  as located separately from the controller  102 , in other embodiments one or both of the RAM  116  and ROM  118  may be located within the controller. In yet other embodiments, portions of RAM and ROM may be located both within the controller  102  and outside the controller. 
     Front end module  108  includes a host interface  120  and a physical layer interface (PHY)  122  that provide the electrical interface with the host or next level storage controller. The choice of the type of host interface  120  can depend on the type of memory being used. Examples of host interfaces  120  include, but are not limited to, Universal Flash Storage (UFS), SATA, SATA Express, serially attached small computer system interface (SAS), Fibre Channel, universal serial bus (USB), PCIe, and NVMe. The host interface  120  typically facilitates transfer for data, control signals, and timing signal s. 
     Back end module  110  includes an error correction code (ECC) engine  124  that encodes the data bytes received from the host, and decodes and error corrects the data bytes read from the non-volatile memory. A command sequencer  126  generates command sequences, such as program and erase command sequences, to be transmitted to non-volatile memory die  104 . A RAID (Redundant Array of Independent Drives) module  128  manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the memory device  104 . In some cases, the RAID module  128  may be a part of the ECC engine  124 . A memory interface  130  provides the command sequences to non-volatile memory die  104  and receives status information from non-volatile memory die  104 . In one embodiment, memory interface  130  may be a double data rate (DDR) interface, such as a Toggle Mode  200 ,  400 , or  800  interface. A flash control layer  132  controls the overall operation of back end module  110 . 
     The storage system  100  also includes other discrete components  140 , such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with controller  102 . In alternative embodiments, one or more of the physical layer interface  122 , RAID module  128 , media management layer  138  and buffer management/bus controller  114  are optional components that are not necessary in the controller  102 . 
       FIG. 2B  is a block diagram illustrating components of non-volatile memory die  104  in more detail. Non-volatile memory die  104  includes peripheral circuitry  141  and non-volatile memory array  142 . Non-volatile memory array  142  includes the non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells and/or NOR flash memory cells in a two dimensional and/or three dimensional configuration. Non-volatile memory die  104  further includes a data cache  156  that caches data. Peripheral circuitry  141  includes a state machine  152  that provides status information to the controller  102 . 
     Returning again to  FIG. 2A , the flash control layer  132  (which will be referred to herein as the flash translation layer (FTL) or, more generally, the “media management layer,” as the memory may not be flash) handles flash errors and interfaces with the host. In particular, the FTL, which may be an algorithm in firmware, is responsible for the internals of memory management and translates writes from the host into writes to the memory  104 . The FTL may be needed because the memory  104  may have limited endurance, may only be written in multiples of pages, and/or may not be written unless it is erased as a block. The FTL understands these potential limitations of the memory  104 , which may not be visible to the host. Accordingly, the FTL attempts to translate the writes from host into writes into the memory  104 . 
     The FTL may include a logical-to-physical address (L2P) map (sometimes referred to herein as a table or data structure) and allotted cache memory. In this way, the FTL translates logical block addresses (“LBAs”) from the host to physical addresses in the memory  104 . The FTL can include other features, such as, but not limited to, power-off recovery (so that the data structures of the FTL can be recovered in the event of a sudden power loss) and wear leveling (so that the wear across memory blocks is even to prevent certain blocks from excessive wear, which would result in a greater chance of failure). 
     As mentioned above, due to the limited amount of volatile memory (e.g., static random-access memory (SRAM)) in a storage system, some storage systems use volatile memory (e.g., dynamic random-access memory (DRAM)) in a host to compensate for its limited volatile memory resources. For example, as shown in  FIG. 3A , host memory can have an area mapped for standard read operations (i.e., an area designated for storing data read from the storage system by the host) and an area mapped for standard write operations (i.e., an area designated for storing data to be written to the storage system by the host). However, as shown in  FIG. 3B , the host memory can also have an area that is mapped for both read and write operations performed by the storage system (i.e., an area designated for use by the storage system to read and write data). 
     Different mechanisms can be used to allow the storage system to access this area in the host memory. For example, storage systems that operate under the Universal Flash Storage (UFS) specification can use a Unified Memory Architecture (UMA) to provide the storage system with master access to portions of the host&#39;s volatile memory. UMA enables a UFS storage system to manage the host volatile memory through a set of low-level commands that are initiated by the storage system. Typically, UMA requires hardware changes to the controllers in both the host and storage system. Because of this, UMA was never adopted by the industry. 
     The following embodiments can be used to provide a storage system with access to the host&#39;s volatile memory even in a UT&#39;S environment without hardware changes to the storage system and host, thereby overcoming the disadvantages of UMA while still providing its advantages and allowing these embodiments to be more easily adopted than UMA. Further, unlike UMA, which is initiated by the storage system, these embodiments can be initiated by the host. That is, in the UFS protocol, the host controller is the master, and the storage system is the slave. Hence, the storage system cannot initiate commands to the host master. However, in these embodiments, once a command is issued by the host master, the storage system controller slave determines when and how the data is transferred, and it allows the storage system to take control over data transfer operations. Further, these embodiments keep the host command open, essentially opening a communication channel between the host volatile memory and the storage system&#39;s controller, where the storage system&#39;s controller will be able to master the data transfers from/to the host&#39;s volatile memory. 
     It should be noted that while these examples are discussed in terms of a UFS storage system, these embodiments can be used with any storage system, and the claims should not be limited to UFS. It should also be noted that while some of the below examples refer to the host&#39;s volatile memory as DRAM and the storage system&#39;s volatile memory as SRAM, other types of memory can be used in the host and/or storage system. 
     In one embodiment, the storage system  100  (e.g., the controller  102 ) receives a command from the host that establishes a communication channel between host memory in the host and the storage system  100 . In response to this command, the controller  102  can write data to and/or read data from the host memory via the communication channel. That is, unlike the UMA process, which is initiated by the storage system, the opening of the communication channel in this embodiment is initiated by the host. 
     The command sent by the host to open the communication channel can take any suitable form. For example, as shown in the flow diagram  400  in  FIG. 4 , in one embodiment, the host  50  sends a standard write command to the storage system  100  as a Universal Flash Storage Protocol Information Unit (UPIU) command. The command parameters for the write command can be command name (e.g., Read Host Memory), start address (the starting physical address of the host memory), and allocation length (the size of the allocated range in the host memory). 
     When the storage system  100  receives such a write command, it recognizes the write command as a read host memory command and does not execute the stated write command (if the write command contains a logical block address or data, the storage system  100  can ignore those items). Instead, in response to receiving the write command, the storage system  100  sends a command to read the host memory by sending the host  50  an identification of a location in the host memory that the storage system  100  wants to read. For example, as shown in  FIG. 4 , the identification of the location in the host memory can be sent as part of a ready-to-transfer (RTT) response to the write command and can comprise an address offset and payload size. In response to receiving that information, the host  50  sends the requested data to the host (e.g., via a Data Out UPIU signal). In one embodiment, the host is configured keep the write command open and ignore timeouts, so the storage system  100  can keep sending requests to read data from the host memory at will. The response UM to close out the write command can be sent from the storage system  100  during power off, for example. In this way, the communication channel will be kept open as long as the host wants to allow the storage system  100  access to the host memory. 
     In addition to or instead of a write command that is recognized by the storage system  100  as a read host memory command, the host  50  can send the storage system  100  a read command that is recognized by the storage system  100  as a write host memory command. This is shown in the flow diagram  500  in  FIG. 5 . In this example, the host  50  sends a standard read command to the storage system  100  as a UPIU command with the same command parameters as the write command, but with the command name being Write Host Memory. In response, the storage system  100  ignores the explicit read command and instead understands that a channel is open to write data to the host memory. In this example, the storage system  100  sends data in UPIU packets. As with the write command discussed above, the host keeps the communication channel open (ignoring any timeouts), so the storage system  100  can keep sending requests to write data from the host memory at will. The response UPIU to close out the read command can be sent from the storage system  100  during power off, for example. 
     By sending both a read host memory command and a write host memory command, the host  50  can establish the two-way channel between the host memory and the storage system  100 , leaving the storage system in charge of when and how it wants to access the host memory. 
     The use of such a communication channel can be used for any suitable purpose. The following paragraphs provide several examples of use cases. However, it should be understood that these are merely examples, and other use cases can be used. 
     Turning again to the drawings  FIG. 6  is flow diagram  600  illustrating the use of this embodiment as a read performance booster. Here, there is an initialization phase in which both the read and write channels to the host memory (here, DRAM)  25  are established. Next, the storage system  100  sends part or all of a logical-to-physical (L2P) address table to the host  50  for storage in the host memory  25 . This is desirable in situations where there is not enough space available in the storage system&#39;s volatile memory to store the table (resulting in a delay in accessing the table from the storage system&#39;s non-volatile memory  104 ). That is, after the host  50  sends a standard read command to the storage system  100 , the storage system  100  can take the logical block address from that command and read the appropriate entry from the table stored in the host memory  25  (using the read host memory command), instead of incurring the time penalty of reading the table from the storage system&#39;s non-volatile memory  104 . 
     As another example, which is shown in the flow diagram  700  in  FIG. 7 , the storage system  100  can use the write host memory command to store, in the host memory  25 , data that was stored in the storage system&#39;s volatile memory (e.g., SRAM) prior to a sleep or power-down operation. That way, when the storage system  100  powers up, it can read the data back from the host memory  25  and store it in its SRAM, which is faster than if the storage system  100  had to store and read that data from its non-volatile memory  104 . 
     As yet another example, which is shown in the flow diagram  800  in  FIG. 8 , these embodiments can allow the storage system  100  to use the host memory as an enhanced read ahead cache. Here, after the storage system  100  reads data requested by the host  50  using a regular read command, the storage system  100  attempts to predict the next address that the host  50  may want read. For example, if the host  50  requested to read LBA X, the storage system  100  may predict that the host  50  will next want to read LBA X+1. So, using these embodiments, the storage system  100  can read LBA X+1 and store its data in the host memory  25 . That way, if the host  50  later sends a read command to the storage system  100  for LBA X+1, the storage system  100  can read the data from the host memory  25  and return it to the host  50  instead of reading the data from the storage system&#39;s  100  non-volatile memory  104 , thus saving time. 
     Similarly, as shown in the flow diagram  900  in  FIG. 9 , the storage system  100  can use the host memory  25  as an enhance write cache. More specifically, when the host  50  sends the storage system  100  a write command with a data payload, instead of storing the data in the storage system&#39;s volatile memory prior to committing it to the storage system&#39;s non-volatile memory  104 , the storage system  100  can write the data to the host memory  25  (using the host memory  25  as the storage system&#39;s internal cache). Later, the storage system  100  can read the data from the host memory  25  and flush it into the storage system&#39;s non-volatile memory  104 . 
     For privacy purposes, the data that is saved to the host memory  25  may be encrypted. Most UFS hosts  50  already include in-line an Advanced Encryption Standard (AES) engine, which encrypts/decrypts data that is stored in/read from the storage system  100 . Due to the symmetric nature of AES, when the storage system  100  writes data to the host memory  25 , the host  50  automatically encrypts the data in DATA IN UPIU and decrypts the data when read in DATA OUT UPIU. 
     As another example, these embodiments can be used to provide a backup write cache. As shown in  FIG. 10 , when the host  50  sends data to be written in the memory  104  of the storage system  100 , the storage system  100  stores the data in SRAM (or other volatile memory)  1010  prior to sending it to the memory  104  for storage. After the SRAM  1010  sends the data to the memory  104 , the SRAM  110  can be used to store other data. However, even though the data is sent from the DRAM  1010  to the memory  104 , it may not immediately be committed to the memory  104 . For example, after the memory  104  receives the data from the SRAM  1010 , it stores the data in its internal latches/registers and then programs the non-volatile memory cells with the data from there. If there is a power loss to the memory  104  during this process (power can be supplied to the NAND via a VCC pin and to other components via a Vccq pin), data that is stored in the latch but not yet committed to the memory cells would be lost. Data can also be host if a programming failure occurred. 
     It may be desired to maintain the data in the SRAM  1010  until the data is actually committed to the memory cells. As this can slow down performance, the storage system  100  can have a second SRAM  1020  to provide double buffer functionality. In this way, if the first SRAM  1010  is being used to continue to store data as a precaution, the second SRAM  1020  can be used to store incoming data for the next write operation. After the data stored in the first SRAM  1010  is committed to the memory cells in the memory  102 , the first SRAM  1010  can be freed for another write operation. At that time the second SRAM  1020  may continue to store data as a precaution for its write operation. So, at any given time, one of the buffers can be used to store data as a precaution, while the other is free to store incoming data, and vice versa. 
     By using these embodiments, the host memory  25  can be used as one of the backup buffers (a “backup cache”), allowing the storage system  100  to have a single buffer instead of a double buffer. This can reduce the expense of the storage system  100  without sacrificing performance. In operation, when the host  50  sends data to the storage system  100  to be written in the memory  103 , the storage system  100  can store that data in its SRAM, as before. However, after the data is sent from the SRAM to the memory  104 , the storage system  100  can transfer the data from the SRAM to the host memory  25 . That way, if there is a power loss, programming error, or other problem, the storage system  100  can retrieve the data from the host memory  25  and reattempt to program the memory  104 . (The data would not be recovered from the storage system&#39;s SRAM because, at that point, if the SRAM would contain different data.) As can be seen by this example, this embodiment provide better utilization of the storage system&#39;s SRAM, hence saving half the required buffer space in the storage system  100 . Again, instead of requiring two buffers in the storage system  100  (one for power loss protection and one for new data), only one buffer is used in the storage system  100 , with the second buffer being the host memory  25 . 
       FIG. 11  is a flow diagram  1100  that illustrates this backup write cache mechanism. First, there is an initialization phase in which both the read and write channels to the host memory  25  are established by the host  50  sending open DMA write and read commands. Next, the storage system  100  receives a write command from the host with data to be written in the memory  104  of the storage system  100 . The storage system  100  stores that data in its SRAM for later writing and sends a copy of that data back to the host memory  25  for storage as a backup using the established open communication channel. In the example in  FIG. 11 , this process is repeated for two 4 kilobyte (KB) units of data to align the data into pages prior to write to increase efficiency. It should be noted that, depending on the size of the data sent in the write command and the size of a page, more than two units of data can be received prior to attempting to write to the memory  104 , or a write to the memory  104  can occur for just one unit of data. In any event, as shown in  FIG. 11 , the copies of the data are stored in different 4 KB units of the host memory  25  than the units that stored the original data sent to the storage system  100 . 
     Next, the storage system  100  sends the data stored in its SRAM to the memory  104 . Before receiving confirmation that the data was successfully stored in the non-volatile memory cells of the memory  104 , the storage system  100  is free to clear the cache and use the SRAM for other data, as the data is backed-up in the host memory  25 . If a disruptive power event occurs before or during the programming of the data in the memory  104 , the storage system  100  will need to retrieve the backup data from the host memory  25 . As shown in  FIG. 11 , this is done using the established communication channel. When the backup data is received, the storage system  100  programs the memory  104  with that data. 
     In yet another example, these embodiments can be used to provide an improvement to the enhanced write cache described above. More specifically, in this embodiment, the storage system  100  may separate data into different areas in the host memory  25  based on metadata characteristics, such as hot versus cold data (streams). Hot data can refer to data that is expected to be accessed and/or changed/updated relatively frequency or quickly (e.g., temporary data), whereas cold data can refer to data that is expected to be accessed and/or changed/updated relatively less frequently or quickly (e.g., a photo). Each data stream can be placed in a different area of the host memory  25 , so that when the storage system  100  stores the data in the host memory  25  for caching, it would place hot data together and cold data together. In one embodiment, the host  50  provides the storage system  100  with information on the locations in the host memory  25  designated for hot data and cold data. 
       FIG. 12  is a flow diagram  1200  that illustrates this enhanced write cache mechanism. This diagram illustrates two use cases: where data is aligned and written to memory blocks without a synchronization command from the host, and where data is placed in memory blocks as a result of a synchronization command from the host. First, there is an initialization phase in which both the read and write channels to the host memory  25  are established by the host  50  sending open DMA write and read commands. Next, the host  50  sends data to the storage system  100  that identifies the locations in the host memory  25  designed for hot data (“Stream A”) and the locations in the host memory  25  designed for cold data (“Stream B”). The storage system  100  then sends hot and cold data to the appropriate locations in the host memory  25 . 
     At the appropriate time (such as when the hot stream data is aligned to optimal NAND write granularity (e.g., page size)), the storage system  100  reads Stream A from the host memory  25  and writes it into the storage system&#39;s memory  104 . Similarly, when the cold stream data is aligned to optimal NAND write granularity, the storage system  100  reads Stream B from the host memory  25  and writes it into the storage system&#39;s memory  104 . In addition to or instead of using data alignment as a trigger for write, the storage system  100  can write Stream A and/or Stream B to memory  104  in response to a synchronization cache (flush) command. 
     There are many alternatives that can be used with these embodiments. For example, as mentioned above, the host  50  can be configured to keep the write and/or read commands open and ignore timeouts, so the storage system  100  can keep sending requests to read data from the host memory  25  at will. The response UPIU to close out the write and/or read command can be sent from the storage system  100  during power off, for example. In this way, the communication channel will be kept open as long as the host  50  wants to allow the storage system  100  access to the host memory  25 . In an alternate embodiment, the host  50  can provide the storage system  100  with an indication in the write and/or read command that the command is an open channel command or otherwise inform the storage system  100  that the command has a long timeout (e.g., that the host  50  will ignore a timeout of the write command and/or the read command). 
     Another alternative relates to hibernation. In some environments, after a lack of communication activity on the interface between the host and the storage system, the storage system can be placed into hibernation mode. However, with the open communication channel mechanism of the above embodiments, it may be desired to avoid hibernation because, at some point, the storage system  100  may want to access the host memory  25 . Accordingly, in one embodiment, the controller  102  of the storage system  100  is configured to avoid hibernation to allow the storages system  100  to continue accessing the host memory  25 . This can be triggered in response to the controller  102  recognizing that the write command is a read host memory command and/or in response to recognizing that the read command is a write host memory command. Alternatively, this can be triggered in response to a flag set in the storage system  100 . 
     Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration. 
     The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material. 
     Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically, contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are examples, and memory elements may be otherwise configured. 
     The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure. 
     In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon. 
     The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and wordlines. 
     A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate). 
     As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements in each column. The columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array. 
     By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-z) memory device levels. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration. 
     Typically, in a monolithic three dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels. 
     Then again, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device. 
     Associated circuitry is typically required for operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may have circuitry used for controlling and driving memory elements to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements. 
     One of skill in the art will recognize that this invention is not limited to the two dimensional and three dimensional structures described but cover all relevant memory structures within the spirit and scope of the invention as described herein and as understood by one of skill in the art. 
     It is intended that the foregoing detailed description be understood as an illustration of selected forms that the invention can take and not as a definition of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of any of the embodiments described herein can be used alone or in combination with one another.