Patent Publication Number: US-2023152839-A1

Title: Output signal generation circuit

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 17/737,620, filed on May 5, 2022, which is a continuation of U.S. application Ser. No. 17/236,650, filed on Apr. 21, 2021 (now U.S. Pat. No. 11,347,257, issued on May 31, 2022), which is a continuation of U.S. application Ser. No. 16/941,738, filed on Jul. 29, 2020 (now U.S. Pat. No. 11,009,904, issued on May 18, 2021), which is a continuation of U.S. application Ser. No. 15/678,153, filed on Aug. 16, 2017 (now U.S. Pat. No. 11,068,016, issued on Jul. 20, 2021), which claims priority from a Japanese Patent Application No. 2016-160422 filed on Aug. 18, 2016, the contents of which are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     Technical Field 
     The present invention relates to an output signal generation circuit that generates an output signal to the outside. 
     Background Art 
     In recent years, various devices such as smartphones, household appliances, industrial machinery, and vehicles, for example, have become highly computerized, and can perform complex and precise operations. Such high performance machinery is provided with input devices such as a multiple sensors and buttons, memory, a display, and output devices (functional units) such as speakers or motors. Also, such machinery is provided with a control device that receives various information from the multiple input devices, and controls the operation of the output devices. 
     The control device is, for example, a microcontroller including a semiconductor integrated circuit connected to the aforementioned input/output devices installed in various types of machinery. The control device receives a signal indicating a specific piece of information from an input device, and then, after performing an operation process, generates a signal to operate an output device and outputs this signal to the output device, for example. 
     Japanese Patent Application Laid-Open Publication No. 2004-355163 discloses a microcomputer having an interface with an external device, for example. Also, Japanese Patent Application Laid-Open Publication No. 2006-211494 discloses a clock signal supply circuit that supplies a clock signal to a sequential circuit installed in a semiconductor integrated circuit, and a semiconductor system including the same. 
     SUMMARY OF THE INVENTION 
     As mentioned above, in recent years, control devices that control the operation of functional units are expected to perform multiple information processes and generate and transmit/receive multiple signals required by such processes. Therefore, when generating a signal indicating information for functional units in the control device or the like, for example, it is expected that signals for a wide range of applications will be generated and outputted. 
     The present invention takes into consideration such points, and one problem to be resolved by the present invention is to provide an output signal generation circuit that can generate output signals for a wide range of applications including a plurality of pieces of information. 
     According to an aspect of the invention, there is provided an output signal generation circuit, including a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal. 
     The output signal generation circuit of the present invention superimposes second information on the first pulse signal including the first information, and generates the second pulse signal, which is one pulse signal including a plurality of pieces of information. Thus, one signal can be outputted for a wide range of applications. Therefore, it is possible to configure an information generation device that generates various information with a few number of signal lines or terminals, for example. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1 A  is a block diagram showing a configuration of an information generation device according to Embodiment 1, and a functional unit connected to the information generation device, and  FIG.  1 B  is a block diagram showing a configuration of an output signal generation circuit according to Embodiment 1. 
         FIG.  2    is a circuit diagram showing a configuration example of the output signal generation circuit according to Embodiment 1. 
         FIG.  3    is a timing chart showing pulse signals outputted from the output signal generation circuit according to Embodiment 1. 
         FIG.  4 A  is a block diagram showing a configuration of an information generation device according to Embodiment 2, and  FIG.  4 B  shows a configuration of an output signal generation circuit according to Embodiment 2. 
         FIG.  5    is a timing chart showing pulse signals outputted from the output signal generation circuit according to Embodiment2. 
         FIG.  6    is a timing chart showing pulse signals outputted from the output signal generation circuit according to Embodiment 2. 
         FIG.  7 A  is a block diagram showing a configuration of an information generation device according to Embodiment 3, and  FIG.  7 B  shows a configuration of an output signal generation circuit according to Embodiment 3. 
         FIGS.  8 A and  8 B  are timing charts showing pulse signals outputted from the output signal generation circuit according to Embodiment 3. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Below, embodiments of the present invention will be explained in detail. 
     Embodiment 1 
       FIG.  1 A  is a block diagram showing a configuration of an information generation device  10  according to Embodiment 1, and a functional unit  20  connected to the information generation device  10 . The information generation device  10  constitutes a microcontroller, for example. The functional unit  20  includes a plurality (two in the present embodiment) of functional blocks  21  and  22 . The functional block  21  is a light-emitting element array for a display panel, and the functional block  22  is a speaker, for example. The configuration of the functional blocks  21  and  22  is not limited thereto. The functional blocks  21  and  22  simply need be a circuit block such as a motor, a heater, or a communication device that executes various functions by being driven by the information generation device  10 . 
     The information generation device  10  is configured to perform various processes by acquiring information from input devices such as sensors, counters, and buttons (not shown), for example, and has an information generation circuit  11  that is configured to generate information to operate the functional unit  20 . The information generation circuit  11  generates data signals D 1  and D 2  (first and second data signals) indicating a plurality (two in the present embodiment) of pieces of information. Also, the information generation device  10  has an output signal generation circuit  12  (hereinafter referred to simply as the “signal generation circuit”) that is configured to generate a control signal CS (hereinafter referred to as the “output signal”) that controls the operation of the functional blocks  21  and  22  of the functional unit  20  on the basis of the data signals D 1  and D 2  generated by the information generation circuit  11 . The signal generation circuit  12  outputs the output signal CS to the functional unit  20 . 
     In the present embodiment, the functional blocks  21  and  22  are provided with extraction units EX 1  and EX 2  that are configured to receive the output signal CS and extract, respectively, the data signals D 1  and D 2  from the output signal CS. The functional blocks  21  and  22  operate on the basis of the data signals D 1  and D 2 . That is, the data signal D 1  generated by the information generation circuit  11  includes information (first information) for operating the functional block  21 , and the data signal D 2  includes information (second information) for operating the functional block  22 . 
       FIG.  1 B  is a block diagram showing a configuration of the output signal generation circuit  12 . As shown in  FIG.  1 B , the signal generation circuit  12  has a first pulse generation circuit  12 A that is configured to generate a first pulse signal PS 1  on the basis of the first data signal D 1  (first information), a second pulse generation circuit  12 B that is configured to generate a second pulse signal PS 2  on the basis of the first pulse signal PS 1  and the second data signal D 2  (second information), and an output circuit  12 C that is configured to generate the output signal CS to output the second pulse signal PS 2  to the functional unit  20 . 
     First, the first pulse generation circuit  12 A pulses the first data signal D 1  and generates the first pulse signal PS 1 . The first pulse signal PS 1  is supplied to the second pulse generation circuit  12 B. The second pulse generation circuit  12 B pulses the first and second data signals D 1  and D 2  on the basis of the first data signal D 1 , the second data signal D 2 , and the first pulse signal PS 1 , and generates the second pulse signal PS 2 . The second pulse signal PS 2  is supplied to the output circuit  12 C. In the present embodiment, the output circuit  12 C selects whether to output or stop outputting the second pulse signal PS 2  and generates the output signal CS. 
       FIG.  2    is a circuit diagram showing a configuration of the signal generation circuit  12 . In the present embodiment, the signal generation circuit  12  controls signals inputted to and outputted from a general purpose input/output (GPIO) port P of the microcontroller. The signal generation circuit  12  is configured so as to generate signals to be outputted from a plurality of ports, but  FIG.  2    shows only one port P. 
     An oscillation signal OS (reference signal) from an oscillation circuit OC is supplied to the pulse generation circuits  12 A and  12 B of the signal generation circuit  12 . Also, the data signal D 1  is supplied to the pulse generation circuit  12 A. The pulse generation circuit  12 A generates the pulse signal PS 1  on the basis of the oscillation signal OS and the data signal Dl. In the present embodiment, the pulse generation circuit  12 A generates the pulse signal PS 1  based on the data signal D 1  after performing frequency division on the oscillation signal OS. 
     The pulse generation circuit  12 B has a frequency division circuit DV that is configured to perform frequency division on the oscillation signal OS on the basis of the oscillation signal OS and the data signals D 1  and D 2 , and generate a frequency division signal DS. Also, the pulse generation circuit  12 B has an AND circuit LG 1  that is configured to output the logical conjunction of the pulse signal PS 1  and the frequency division signal DS to generate the pulse signal PS 2 . The output signal from the AND circuit LG 1  is supplied to the output circuit  12 C as the pulse signal PS 2 . 
     In the present embodiment, the output circuit  12 C includes a NAND circuit LG 2 , an AND circuit LG 3 , transistors TR 1  and TR 2 , switches SW 1  and SW 2 , and a resistor R. As shown in  FIG.  2   , the pulse signal PS 2 , an output enable signal EN, and an N-channel open drain-setting signal ODN are inputted to the NAND circuit LG 2 . The gate of the transistor TR 1  is connected to the output terminal of the NAND circuit LG 2 . 
     The pulse signal PS 2 , the output enable signal EN, and a P-channel open drain-setting signal ODP are inputted to the AND circuit LG 3 . The gate of the transistor TR 2  is connected to the output terminal of the AND circuit LG 3 . The transistor TR 1  is a P-channel MOSFET and the transistor TR 2  is an N-channel MOSFET. A power source is connected to the drain of the transistor TR 1 . The drain of the transistor TR 2  is connected to the source of the transistor TR 1 . The source of the transistor TR 2  is grounded. The drain of the transistor TR 2  is connected to the port P. 
     The first terminal of the resistor R is connected to the source of the transistor TR 1 , and the second terminal of the resistor R is connected to the first terminals of the switches SW 1  and SW 2 . The second terminal of the switch SW 1  is connected to the power source, and the second terminal of the switch SW 2  is grounded. The switch SW 1  is switched between being conductive and being non-conductive by a pull-up setting signal PU. The switch SW 2  is switched between being conductive and being non-conductive by a pull-down setting signal PD. 
     The pulse signal PS 2  is supplied selectively to the port P (that is, outputted to the functional unit  20 ) by the output enable signal EN. Also, the N-channel and P-channel open drain-setting signals ODN and ODP and the pull-up setting signal PU and pull-down setting signal PD are used to control the level of the output signal CS, switch between signal input mode and output mode at the port P, or the like. In this manner, the output circuit  12 C performs output control on the pulse signal PS 2  and supplies the output signal CS to the port P. 
       FIG.  3    is a timing chart showing pulse signals PS 1  and PS 2  generated by the signal generation circuit  12 . As shown in  FIG.  3   , the pulse generation circuit  12 A outputs the pulse signal PS 1  indicating the first information on the basis of the data signal D 1 . Also, in the present embodiment, the frequency division circuit DV outputs the frequency division signal DS, which is a clock signal with a fixed period generated by performing frequency division on the oscillation signal OS. 
     Therefore, the pulse signal PS 2 , which is the logical conjunction of the pulse signal PS 1  and the frequency division signal DS, has a waveform such that the frequency division signal DS is outputted when the pulse signal PS 1  is at an H level (first logic level). In the present embodiment, the pulse generation circuit  12 B generates the pulse signal PS 2  in which the frequency division signal DS is outputted when the pulse signal PS 1  rises, and output of the frequency division signal DS is stopped when the pulse signal PS 1  falls. 
     In other words, the pulse signal PS 2  includes periods when the first data signal D 1  is outputted (in the present embodiment, periods in which the pulse signal PS 1  is at an L level (second logic level)), and periods when the first and second data signals D 1  and D 2  are outputted (periods when the pulse signal PS 1  is at an H level). 
     If the narrowest possible pulse width (minimum pulse width) of the pulse signal PS 1  is a first pulse width W 1 , the pulse width of the frequency division signal DS is narrower than the first pulse width W 1 . In other words, in the present embodiment, the first pulse generation circuit  12 A generates the first pulse signal PS 1  in which the first pulse width W 1  is the minimum pulse width, on the basis of the first information (first data signal D 1 ). Also, the second pulse generation circuit  12 B generates the second pulse signal PS 2  having a second pulse width W 2  that is narrower than the first pulse width W 1 , and in which the first information and the second information (first and second data signals D 1  and D 2 ) are superimposed. Additionally, the output circuit  12 C outputs the second pulse signal PS 2  as the output signal CS to the outside. 
     The pulse generation circuit  12 A may be configured to selectively pulse a plurality of pieces of information (data signals) to generate the pulse signal PS 1  in order to use the port P as the output port for various signals, for example. In such a case, the pulse generation circuit  12 A would have a circuit that receives a plurality of data signals D 1  from the information generation circuit  11  and pulses them, and a selector (not shown) that selectively outputs the pulsed signals as the pulse signals PS 1 , for example. 
     Also, data included in the data signal D 1  may be communication data for serial communication, timer data indicating time information counted by a counter, or measurement data measured by a sensor. 
     Also, in the present embodiment, a case was described in which the output signal CS is supplied to two functional blocks  21  and  22 , but the output signal CS is not limited to being supplied thereto. For example, the output signal CS may be supplied to only the functional block  21 . In such a case, the output signal CS 2  includes two operation parameters of the functional block  21  as data signals D 1  and D 2 , for example. Specifically, in one example, if the functional block  21  is a display panel, then the data signal D 1  includes information indicating the light-emitting element to which conduction is enabled, and the data signal D 2  includes information indicating the light emission luminance. 
     In this manner, in the present embodiment, the signal generation circuit  12  has a first pulse generation circuit  12 A that generates a first pulse signal PS 1  that includes the first information and has the first pulse width W 1  as the minimum pulse width, a second pulse generation circuit  12 B that generates a second pulse signal PS 2  that has a second pulse width W 2  that is smaller than the first pulse width W 1  and is a signal in which the second information is superimposed on the first pulse signal PS 1 , and an output circuit  12 C that outputs the second pulse signal PS 2  as the output signal CS to the outside. Thus, an output signal CS that is compatible with a wide range of applications can be generated. 
     Also, the pulse signal PS 2  (output signal CS) is supplied to the two functional blocks  21  and  22  of the functional unit  20 , for example. The functional blocks  21  and  22  are configured so as to extract information used in respective operations thereof from the pulse signal PS 2 , and operate on the basis of this information. In other words, the signal generation circuit  12  generates one output signal CS that allows the two functional blocks  21  and  22  to operate. Therefore, the signal generation circuit  12  can generate the output signal CS in which signals for operating the plurality of functional blocks  21  and  22  are superimposed. This also enables configuration of an information generation device  10  that performs various types of information generation with a small number of control terminals (small number of ports) and a small number of signal lines. 
     In the present embodiment, a case was described in which the signal generation circuit  12  generates an output signal CS outputted from the GPIO port, but the signal generation circuit  12  can generate other signals for external output. For example, the output signal CS generated by the signal generation circuit  12  may be a digital signal or an analog signal. If a digital signal is outputted as the output signal CS, for example, then the first pulse width W 1  (minimum pulse width) of the pulse signal PSI generated by the pulse generation circuit  12 A corresponds to the clock period (bit period) of the pulse signal PS 1 . 
     On the other hand, if an analog signal is outputted as the output signal CS, for example, then the pulse generation circuits  12 A and  12 B of the signal generation circuit  12  would be configured to generate analog pulse signals as the first and second pulse signals PS 1  and PS 2 . Furthermore, the output circuit  12 C would be configured as an element such as an analog switch. 
     In the present embodiment, a case was described in which the frequency division signal DS is a synchronous signal synchronized to the pulse signal PS 1 . However, in the case of a configuration in which information is extracted by the functional unit  20 , which received the pulse signal PS 2 , for example, then there is no need for the frequency division signal DS to be synchronized with the pulse signal PS 1 . The frequency division circuit DV may generate an asynchronous signal that is not synchronized to the pulse signal PSI as the frequency division signal DS, for example. Regardless of whether the frequency division signal DV is synchronized to the pulse signal PS 1 , the logical conjunction of the frequency division signal DV and the pulse signal PS 1  would be outputted as the pulse signal PS 2 . 
     Embodiment 2 
       FIG.  4 A  is a block diagram showing a configuration of an information generation device  30  according to Embodiment 2. In the present embodiment, an information generation circuit  31  is configured to generate three data signals D 1 , D 2 , D 3  (information). Also, a signal generation circuit  32  is configured to generate an output signal CS 1  on the basis of the data signals D 1 , D 2 , and D 3  and output the output signal. The output signal CS 1  can be supplied to the functional unit  20  shown in  FIG.  1 A , for example. 
       FIG.  4 B  shows a configuration of the signal generation circuit  32 . The signal generation circuit  32  has a similar configuration to the signal generation circuit  12 , other than the configuration of a pulse generation circuit  32 A (second pulse generation circuit). The pulse generation circuit  32 A has a frequency control unit FC that is configured to control the frequency of the frequency division signal DS 1 , that is, the frequency division number of the oscillation signal OS, generated by the frequency division circuit DV on the basis of the data signals D 1  to D 3 . The frequency division circuit DV generates a frequency division signal DS 1  for frequency division of the oscillation signal OS on the basis of the control signal FS supplied from the frequency control unit FC. 
     The frequency division signal DS 1  generated by the frequency division circuit DV is inputted to the AND circuit LG 1  together with the pulse signal PS 1  generated by the pulse generation circuit  12 A, and is outputted from the AND circuit LG 1  as a pulse signal PS 3  (second pulse signal). The pulse signal PS 3  is supplied to the output circuit  12 C, and is outputted to the outside as the output signal CS 1 . 
     The data signals D 1  to D 3  are supplied to the frequency control unit FC. The frequency control unit FC generates a control signal FS (frequency control signal) that controls the frequency division number of the frequency division signal DS 1 , that is, the frequency of the pulse signal PS 3 , on the basis of the data signals D 1  to D 3 . Specifically, in the present embodiment, the frequency control unit FC switches the frequency of the pulse signal PS 3  between a period during which the data signals D 1  and D 2  are outputted and a period during which the data signals D 1  and D 3  are outputted. The frequency control unit FC supplies the control signal FS to the frequency division circuit DV. 
       FIG.  5    is a timing chart showing the pulse signal PS 3  generated by the signal generation circuit  32 . In the present embodiment, the frequency control unit FC detects the fall of the pulse signal PS 1 , and switches the control signal FS during the fall of the pulse signal PS 1  or while the pulse signal PS 1  is at an L level. In the present embodiment, the frequency control unit FC switches the control signal FS such that the frequency of the pulse signal PS 3  differs between the H level periods P 11  and P 12  of the pulse signal PS 1 . 
     Specifically, as shown in  FIG.  5   , the frequency control unit FC generates the control signal FS such that the frequency division number is ½ during the first H level period P 11  of the pulse signal PS 1 , and ¼ during the second H level period P 12 . The frequency division circuit DV performs a frequency division of ½ on the oscillation signal OS during the first H level period P 11 , and, after the first H level period P 11 , switches the frequency division number to ¼. 
     Also, as shown in  FIG.  5   , in the present embodiment the oscillation signal OS generated by the oscillation circuit OC and the pulse signal PS 1  generated by the pulse generation circuit  12 A are asynchronous signals that are not synchronized with each other. Therefore, the frequency division circuit DV generates an asynchronous signal that is not synchronized to the pulse signal PS 1  as the frequency division signal DS 1 . The pulse signal PS 2  is outputted as the logical conjunction of the frequency division signal DS 1  and the pulse signal PS 1 , which are not synchronized to each other. 
     In this manner, in the present embodiment, the pulse generation circuit  32 A has the frequency control unit FC, which controls the frequency of the pulse signal PS 3  so as to switch the frequency division number of the frequency division signal DS such that third information is superimposed on the pulse signal PS 3 . Thus, the pulse generation circuit  32 A is configured such that the frequency division circuit DV generates differing frequencies (frequency division numbers) of the frequency division signal DS 1 . Therefore, the pulse generation circuit  32 A generates the pulse signal PS 3  having differing frequencies depending on the period. 
     As a result, it is possible to retain (superimpose) differing information for each period in which the frequency of the pulse signal PS 3  differs. Specifically, it is possible to output the pulse signal PS 3  so as to include the first and second data signals D 1  and D 2  (first and second information) during the first H level period P 11 , and first and third data signals D 1  and D 3  (first and third information) during the second H level period P 12 , for example. 
     As shown in  FIG.  6   , the oscillation circuit OC and the pulse generation circuit  12 A may be configured such that the oscillation signal OS and the pulse signal PS 1  are in synchronization with each other. In other words, the frequency division circuit DV may generate a synchronous signal that is synchronized to the pulse signal PS 1  as the frequency division signal DS 1 . Whether or not to synchronize the frequency division signal DS 1  with the pulse signal PS 1  can be selected according to characteristics of the external device (functional block  21  and the like, for example) receiving the pulse signal PS 2 . 
     If extracting information according to the frequency at the external device, for example, the frequency division circuit DV need not generate a frequency division signal DS 1  that is synchronized with the pulse signal PS 1 . If the frequency division circuit DV generates a frequency division signal DS 1  that is asynchronous with the pulse signal PS 1 , there is no need to provide a synchronization circuit or the like in the frequency division circuit DV. Therefore, it is possible to configure the frequency division circuit DV, the pulse generation circuit  32 A, and the signal generation circuit  32  with a simple configuration. 
     Also, in the present embodiment, the pulse width of the pulse signal PS 3  differs depending on the period in which the signal is generated, but the pulse width (pulse width corresponding to the pulse width W 2  of the pulse signal PS 2 ; see  FIG.  3   ) is narrower than the minimum pulse width W 1  of the pulse signal PS 1 . 
     In this manner, in the present embodiment, the signal generation circuit  32  generates one pulse signal PS 3  based on the third information in addition to the first and second information. Thus, an output signal CS 1  that is compatible with a wide range of applications can be generated. This also enables configuration of an information generation device  30  that performs various types of information generation with a small number of signal lines and terminals. 
     Embodiment 3 
       FIG.  7 A  is a block diagram showing a configuration of an information generation device  40  according to Embodiment 3. The information generation device  40  includes an information generation circuit  41  and a signal generation circuit  42 . The signal generation circuit  41  is configured to generate data signals D 1  and D 2  and supply the signals to the signal generation circuit  42 . The signal generation circuit  42  is configured to generate an output signal CS 2  on the basis of the data signals D 1  and D 2 , and output the output signal. The output signal CS 2  is supplied to the functional unit  20  shown in  FIG.  1 A , for example. 
       FIG.  7 B  shows a configuration of the signal generation circuit  42 . The signal generation circuit  42  has a similar configuration to the signal generation circuit  12 , other than the configuration of a pulse generation circuit  42 A (second pulse generation circuit). The pulse generation circuit  42 A generates a pulse signal PS 4  (second pulse signal) in which the first information and second information are superimposed on the basis of the first and second data signals D 1  and D 2 , and supplies the pulse signal to the output circuit  12 C. 
     In the present embodiment, the pulse generation circuit  42 A has a level switching unit LC that is configured to switch the outputted level of the frequency division signal DS generated by the frequency division circuit DV, an AND circuit LG 1 , an OR circuit LG 4 , and a selector SEL. In the present embodiment, the pulse signal PS 1  generated by the pulse generation circuit  12 A and the frequency division signal DS generated by the frequency division circuit DV are inputted to the AND circuit LG 1  and the OR circuit LG 4 . The OR circuit LG 4  is configured to output the logical disjunction of the pulse signal PS 1  and the frequency division signal DS. 
     The input terminals of the selector SEL are connected to the output terminals of the AND circuit LG 1  and the OR circuit LG 4 . Also, the level switching unit LC is connected to the control terminal of the selector SEL. The output terminal of the selector SEL is connected to the output circuit  12 C. The level switching unit LC is configured to generate a switching signal LS (level control signal) that switches the output level of the frequency division signal DS and supplies the switching signal to the selector SEL. The signal in which the output level was switched is supplied from the selector SEL to the output circuit  12 C as the pulse signal PS 4 . The output circuit  12 C is configured to output the output signal CS 2  based on the pulse signal PS 4  to the outside. 
       FIGS.  8 A and  8 B  are timing charts showing the pulse signal PS 4  generated by the signal generation circuit  42 . The pulse signal PS 4  generated by the pulse generation circuit  42 A changes according to the level of the switching signal LS generated by the level switching unit LC.  FIG.  8 A  shows a timing chart of the pulse signal PS 4  for when the switching signal LS is at an L level.  FIG.  8 B  is a timing chart of the pulse signal PS 4  for when the switching signal LS is at an H level. 
     As shown in  FIG.  8 A , when the switching signal LS is at an L level, a pulse signal PS 4  similar to the pulse signal PS 2  generated by the signal generation circuit  12  is generated from the signal generation circuit  42 . On the other hand, as shown in  FIG.  8 B , when the switching signal LS is at an H level, the pulse signal PS 4  has a waveform in which the frequency division signal DS is outputted when the pulse signal PS 1  is at an L level and the pulse signal PS 1  is outputted when the pulse signal PS 1  is at an H level. 
     More specifically, in the present embodiment, as shown in  FIGS.  8 A and  8 B , the data periods of the pulse signal PS 1  are periods P 21 , P 22 , P 23 , P 24 , and P 25 . In this case, as shown in  FIG.  8 A , if the switching signal LS is at an L level, the periods P 22  and P 24  are periods during which to output the data signals D 1  and D 2 , and other periods are when the data signal D 1  is outputted. On the other hand, as shown in  FIG.  8 B , if the switching signal LS is at an H level, the periods P 21 , P 23 , and P 25  are periods during which to output the data signals D 1  and D 2 , and other periods are when the data signal D 1  is outputted. 
     In other words, the level switching unit LC supplies to the selector SEL the switching signal LS, which switches whether, in the pulse signal PS 4 , to output the frequency division signal DS when the pulse signal PS 1  is at a first logic level (H level), or to output the frequency division signal DS when the pulse signal PS 1  is at a second logic level (L level). 
     In this manner, in the present embodiment, level switching for when the pulse signal PS 4  is to be superimposed on the second data signal D 2  is performed by the level switching unit LC. Therefore, it is possible to generate and output an output signal CS 2  for a wide range of applications, and it is possible to configure an information generation device  40  that performs various types of information generation with a small number of signal lines and terminals. 
     The embodiments above can be combined with each other. For example, the signal generation circuit  42  of Embodiment 3 may be provided with the frequency control unit FC of Embodiment 2. In such a case, the timing for switching the frequency would be during level switching. In other words, if the level switching unit LC outputs the frequency division signal DS when the pulse signal PS 1  is at an L level (as shown in  FIG.  8 B ), the frequency control unit FC would control the switching timing of the control signal FS such that the frequency division number is switched when the pulse signal PS 1  rises. 
     As described above, the signal generation circuit of the present invention has a first pulse generation circuit  12 A that generates a first pulse signal PS 1  that indicates the first information, a second pulse generation circuit  12 B ( 32 A,  42 A) that generates a second pulse signal PS 2  (PS 3 , PS 4 ) that has a pulse width that is smaller than the first pulse signal PS 1  on the basis of the first information and the second information, and an output circuit  12 C that outputs the second pulse signal PS 2  as the output signal CS. Thus, the output signal CS, which is compatible with a wide range of applications, can be generated and outputted.