Patent Publication Number: US-7596734-B2

Title: On-Chip AC self-test controller

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 11/323,449 filed Dec. 30, 2005, now U.S. Pat. No. 7,430,698, which is a continuation of U.S. patent application Ser. No. 10/131,554 filed Apr. 24, 2002, now U.S. Pat. No. 7,058,866, the contents of which are incorporated by reference herein in their entirety. 

   GOVERNMENT RIGHTS 
   This invention was made with Government support under subcontract B338307 under prime contract W-7405-ENG-48 awarded by the Department of Energy. The Government has certain rights in this invention. 

   FIELD OF THE INVENTION 
   The present invention relates generally to a method of performing an AC self-test on an integrated circuit, and more particularly to performing the AC self-test using the same system clock that is utilized during normal system operation. 
   BACKGROUND 
   As the design of integrated circuits has progressed, more and more circuitry is being disposed in increasingly dense patterns and it has become correspondingly more difficult to test and diagnose such circuits. Several methodologies for performing integrated circuit testing use level sensitive scan design (LSSD) techniques to facilitate circuit testing and diagnosis. Integrated circuit devices of interest typically contain blocks of combinatorial logic paths whose inputs and outputs are supplied to certain memory elements. In an LSSD system, the memory elements are configurable to become shift register latches (SRLs). During test mode, these SRLs are capable of storing predetermined data patterns through a shifting operation. A plurality of SRLs can comprise a scan path with the output signals from the latch strings supplied to a signature register or multiple input signature register (MISR) for comparison and analysis with known results. During operation of the circuit in the normal system environment, the SRLs function as memory elements passing signals to be processed from one combinatorial block to another and at the same time typically receiving input signals for subsequent application to combinatorial logic blocks in subsequent clock cycles. The SRLs play a significant role in establishing and defining stable logic outputs at appropriate points in a machine cycle. Thus, the SRLs serve a dual purpose, one during test and one during normal system operation. Typically, one or more test clocks are supplied to the SRLs during system test. The operation of these clocks must be coordinated and tuned to exhibit the proper waveforms during system test in order to ensure accurate test results. 
   The scan operations and SRLs described above can be used to measure timing characteristics on an integrated circuit. Screening out integrated circuits with timing problems becomes essential as the number of integrated circuits that can pass low frequency tests but fail high frequency tests increases. 
   SUMMARY 
   An exemplary embodiment of the present invention is a system for performing AC self-test on an integrated circuit that includes a system clock for normal operation. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. Input to the logic circuit includes data from the first test register and output from the logic circuit is stored in the second test register. The self-test circuitry includes an AC self-test controller and a clock splitter. Input to the clock splitter includes the system clock and the AC self-test controller. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     Referring now to the figures, which are exemplary embodiments, and wherein the like elements are numbered alike: 
       FIG. 1  is a diagram of a clock pulse and a shift register latch (SRL) used in an exemplary embodiment of the present invention; 
       FIG. 2  depicts the relationship between a series of SRLs used during AC test and the clock pulse used to drive the AC test; 
       FIG. 3  is a block diagram of the components of an exemplary embodiment of the present invention including a controller and a clock splitter; 
       FIG. 4  is the internal timing diagram of an exemplary embodiment of the present invention; and 
       FIG. 5  is a block diagram of an alternative exemplary embodiment of a portion of the AC self-test controller with two delay elements deleted. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention discloses a method to perform an AC self-test using a scheme that renders distribution and tuning of control signals to the clock splitters noncritical. In an exemplary embodiment, the AC self-test is performed by first initializing all the shift register latches (SRLs) with test data using a process that is known in the art. The initializing can be performed by scanning all the SRLs within the integrated circuit with a set of pseudo random data by pulsing the scan clocks as many times as needed to fill the SRLs with data. The A clock is typically the scan clock the causes the test data at the L 1  input port to enter the L 1  latch and the B clock is typically the scan clock that causes the data from the L 1  latch to enter the L 2  latch and the input port of the next L 1  latch in the chain. The A clock should pulse last so that L 1  and L 2  contain different data at the end of the scan or initialization operation. 
   Once the SRLs are initialized, the AC self-test of the present invention is performed at operating frequency to check if the stored data can be transferred through the critical path successfully.  FIG. 1  depicts an AC self-test clocking sequence  114  that can be used to implement the present invention and be applied after scanning has been completed. The exemplary embodiment in  FIG. 1  depicts a single step operation but the invention can be expanded to include operations of multiple steps. The sequence is: a long ZC clock pulse  116 , an at speed ZB clock pulse  122 , an at speed ZC clock pulse  124 , and finally a long ZB clock pulse  120 . The middle two at speed pulses  122   124 , performing a single step operation, test the logic at operating speed. The length of time that it takes for the two at speed pulses  122   124  to execute is also referred to as the cycle time  118 . The cycle time  118  is the time period during which the AC at speed self-test is performed. The long ZC clock pulse  116  at the beginning is to allow plenty of time to condition the L 1  portion of the SRL  102  with stable data prior to the AC self-test. Similarly, the long ZB clock pulse  120  at the end is to ensure that the L 2  portion of the SRL  104  has stable data prior to scanning out for verification.  FIG. 1  also depicts an exemplary SRL  100  that can be used to implement the present invention. The SRL  100  contains two latches, L 1   102  and L 2   104 . When ZC  106  is pulsed, or at a high state, data from the data input port Din  108  is latched into L 1   102 . When ZB  110  is pulsed, or at a high state, data from L 1   102  is latched into L 2   104  and output through the L 2   104  output port, Dout  112 . The ZB  110  clock pulse is also referred to as a data launch pulse and the ZC  106  clock pulse is also referred to as a data capture pulse. 
     FIG. 2  depicts the relationship between a series of SRLs used during AC self-test and the clock pulses, ZC  106  and ZB  110 , used to drive the AC self-test in an embodiment of the present invention. The exemplary AC self-test depicted in  FIG. 2  begins at SRL- 1   202 . Data has already been loaded into Din  108  either through the initialization process described above or because SRL- 1   202  is not the first SRL  100  in a chain of SRLs. The long ZC clock pulse  116  results in data being moved from Din  108  into the L 1  of SRL- 1   202  and in stabilizing the data in L 1  of SRL- 1   202 . Then, the long ZC clock pulse  116  ends and the ZB at speed pulse  122  begins. This causes the data from the gate between the data input port Din  108  and L 1  of SRL- 1   202  to be closed. In addition, it causes the data in the L 1  of SRL- 1   202  to be moved into the L 2  of SRL- 1   202 , into the Dout  112  of SRL- 1   202  and into the next block of logic  204  resulting in output  218 . When the at speed ZB pulse  122  ends, the at speed ZC pulse  124  begins. When this occurs the gate between the L 1  and L 2  of SRL- 1   202  is closed and the data that is output from the logic  218  is then input into the L 1  of SRL- 2   206 . Next, the long ZB clock pulse  120  occurs and the ZC at speed clock pulse  124  ends, causing the gate between the input  218  and the L 1  of SRL- 2   206  to be closed. In addition, the data in the L 1  of SRL- 2   206  is sent to the L 2  of SRL- 2   206 , the output  212  of the L 2  of SRL- 2   206  is sent to the logic  208  and output  228  is collected to be input to the L 1  of SRL- 3  on the next ZC clock pulse. 
   During AC self-test the integrated circuit is being tested to determine if any timing errors exist on the integrated circuit. Timing errors can occur because a logic path is too long, a logic path is too short, the ZC  106  and ZB  110  pulses are not exactly synchronous, or a combination of these factors. In the case of a long logic path, data is output from the logic  218  and loaded into the L 1  of SRL- 2   206  before the next ZC pulse  124  ends or returns to zero. Otherwise the data being loaded into the L 1  of SRL- 2   206  by the next ZC pulse  124  will be incorrect. Another possible error occurs if the logic path is short and the rising edge of the ZB clock  120  runs a little early and/or the falling edge of the ZC clock  124  runs a little late. In this case, there is the risk that the logic path will be exercised twice before the ZC pulse ends. In this case, the first data launched by pulse  122 , of the ZB clock  110 , through the short logic path will be overwritten by the second data launched by pulse  120 , of the ZB clock  110 , and therefore produce incorrect results. 
     FIG. 3  is a block diagram of the components of an exemplary embodiment of the present invention that can be used to create the clock pulse  114  shown in  FIG. 1 . The embodiment includes self-test circuitry  300  which comprises an AC self-test controller  302  and a clock splitter  304 .  FIG. 3  shows the design of the controller  302  and the logic representation of the clock splitter  304 . In an exemplary embodiment, one controller is shared by all on-chip clock splitters  304  and one clock splitter  304  may drive many SRLs  100 . The controller  302  is designed to condition the clock splitter  304  to generate the desirable ZC  106  and ZB  110  waveforms for implementing the present invention. The ZC  106  clock pulse is received from the capture pulse output terminal  394  on the clock splitter  304 . The ZB  110  clock pulse is received from the launch pulse output terminal  396  on the clock splitter  304 . The controller  302  consists of one set/reset SRL  308  and four staging SRLs  306 . In addition, the controller  302  includes a system reset input  322 , a start_ac_test input  320  and a OR gate  324  to determine if the controller  302  should be reset. As shown in  FIG. 3 , the output from the set/reset SRL  308 , “v”  310  is input into the C  370  and EN  372  input terminals of the clock splitter  304 . The output from the first three staging SRLs, “p”  312 , “q”  314 , and “r”  316  are input into an OR gate  326  resulting in the output “t”  328 . The output “t”  328  is then input to an AND gate  330  along with the inverted  334  value of “s”  318 , the output from the last staging SRL  306 . The result from the AND gate  330  is the value “w”  332  which is input to the PG 1   366  and B  368  input pins on the clock splitter  304 . 
   The portion of the controller depicted at the bottom of the diagram, the clocking generator  392  controls the input to the oscillator clock (OSC)  374  on the clock splitter  304 . The output of the set/reset latch  308 , “v”  310  is input to an AND gate  342 . Also input to the AND gate  342  is the value of “q”  314 , the output of the second staging SRL  306  after it has been sent through a half cycle delay, referred to as delay- 1   338 . The output from the AND gate  342 , “z”  344 , is input to the DO  390  of the selector  346 . The input to D 1   398  on the selector  346  is the system clock  340  denoted as “CLOCK”. The selection of D 0   390  or D 1   398  in the selector  346  is controlled by the input to an AND gate  360 . The output of the first staging SRL  306 , “p”  312  is input into delay- 2   350 , which is a three-quarter cycle delay, resulting in the value “x”  354  which is one input to the AND gate  360 . The output of the third staging SRL  306 , “r”  316  is input into delay- 3   352 , which is a one-quarter cycle delay, and then inverted  356 , resulting in the value “y”  358  which is the other input to the AND gate  360 . The result of the AND gate  360  controls whether D 0   390  or D 1   398  is selected by the SD  388  in the selector  346 . When SD is equal to “0”, D 0   390  is selected. When SD is equal to “1”, D 1   398  is selected. The output from the selector  346  is an OSC signal  348  which is input to the OSC  374  on the clock splitter. 
   The timing critical area of the controller is the three well tuned delay lines: delay- 1   338 , delay- 2   350 , and delay- 3   352 . The delay- 1   338  is tuned to a value of approximately half a cycle time; the delay- 2   350  is about three fourths of the cycle time; and the value of delay- 3   352  is about one quarter of the cycle time. 
   The clock splitter  304  is integrated on the chip. Wiring for an exemplary clock splitter  304  that can be used by an embodiment of the present invention is shown in  FIG. 3 . Inputs to the clock splitter  304  are as described in reference to the controller  302 . Output from the clock splitter  304  comes from the launch pulse output terminal  396  which is input to the ZB clock pulse  110 . Another output from the clock splitter  304  comes from the capture pulse output terminal  394  which is input to the ZC clock pulse  106 . The output from the clock splitter  304  is input to the SRLs as described in reference to  FIG. 1  and  FIG. 2 . An example of wiring for an exemplary clock splitter  304  is shown in  FIG. 3 . The values of EN  372  and OSC  374  are input to a NAND gate  384 . The output of the NAND gate  384  is input to another NAND gate  382  along with C  370 . The result of the NAND gate  382  is input to an AND gate  386  along with B  368  resulting in the launch data output terminal which is input to the ZB clock signal  1110 . The output from the NAND gate  382  is also input to a NOR gate  380  along with PG 1   366  after it has been put through a NOT gate  378 . The result is the capture data output terminal  394  which is input to clock pulse ZC  106 . ZB and ZC are complements of each other during AC test and during system mode. Note that the PG 1   366  and B  368  pins of the clock splitter  304  are tied together at  362  only during AC test. A hardwired representation is shown just for clarity in the context of this invention. Similarly, note that the C  370  and EN  372  pins of the clock splitter  304  are tied together at  364  only during AC test. Again, a hardwired representation is shown just for clarity in the context of this invention. 
     FIG. 4  is a timing diagram associated with the exemplary embodiment of the present invention depicted in  FIG. 3 .  FIG. 4  illustrates how the desired waveforms for ZC  106  and ZB  110  are generated. A continuously running CLOCK  340  is applied to the D 1   398  pin of the selector  346  after conventional scanning has been done. A single pulse “start_ac test”  320  is asserted. The controller  302  will then generate the proper waveforms for the PG 1 /B  362  and C/EN  364  pins at cycle boundaries with the C/EN  364  pulse being wider than the PG 1 /B  362  pulse by one cycle at both ends. The SD signal  388  of the selector is designed to be wide enough to envelope a single CLOCK  340  pulse at cycle  4 . The delay elements delay- 2   350  and delay- 3   352  are used to provide margins at both ends of SD  388 . D 0   390  of the selector  346  is switched at the middle of the AC test single step operation so that there will be a long ZC  106  generated at the beginning and a long ZB  110  generated at the end of the AC test sequence. The delay element delay- 1   338  is for this purpose and is less critical than delay- 2   350  and delay- 3   352 . The entire AC operation depicted in the embodiment shown in  FIG. 4  requires 6 cycles to perform. 
   It is understood that there is more than one way to implement the AC self-test controller  302 .  FIG. 5  is another embodiment of the clocking generator portion  392  of the controller  302  that could be used to produce the waveform shown in  FIG. 1 .  FIG. 5  shows a scheme which eliminates two delay elements, in the clocking generator section  392  of the controller  302 , by taking advantage of the fact that the L 1  output of the SRL  100  is offset by half a cycle with respect to its L 2  output. The output from the set/reset latch  308 , “v”  310  is input to an AND gate  342  along with the L 1  output of SRL- 4   502  which is between “q”  314  and “r”  316 . SRL- 4  is the third staging SRL  306  depicted in  FIG. 3 . The result is “z”  344  which is input to D 0   390  of the selector  346 . The CLOCK  340  is input to the D 1   398  input pin of the selector  346 , the same as in  FIG. 3 . SD  388  is set as a result of the output of an AND gate  360 . One input to the AND gate  360  is the L 1  output of SRL- 3  which is between “p”  312  and “q”  314 . SRL- 3  is the second staging SRL  306  depicted in  FIG. 3 . The other input is the same as that depicted in  FIG. 3 , the value “r”  316  input into delay- 3   352 , then inverted  356 , resulting in “y”  358 . 
   The present invention utilizes the same system clock, CLOCK  340 , that is utilized by the integrated circuit during normal system operation. The CLOCK  340  that is input to the controller  302  will connect to the OSC directly during normal operation. This allows the CLOCK  340  to be optimized for both normal operation and AC testing. Therefore, additional clocks for testing, which may introduce additional errors and require additional optimizing are not necessary. Another advantage to using the present invention is that the tuning of delay elements is concentrated in the controller region. Consequently, the control signals to the clock splitters remain timing non-critical. The only distribution issue is the tuning of the OSC wire (known as the “clock tree”) which is a design consideration in its own right even without the AC test implemented. 
   As described above, the present invention can be embodied in the form of computer-implemented processes and apparatuses for practicing those processes. The present invention can also be embodied in the form of computer program code containing instructions embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other computer-readable medium, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. The present invention can also be embodied in the form of computer program code, for example, whether stored in a storage medium, loaded into and/or executed by a computer or transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. When implemented on a general-purpose microprocessor, the computer program code segments configure the microprocessor to create specific logic circuits. 
   While the invention has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiments for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims. Moreover, the use of the terms first, second, etc. do not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another.