Patent Publication Number: US-11398383-B2

Title: Semiconductor structure and method for forming the same

Description:
BACKGROUND 
     Field of the Disclosure 
     The present disclosure relates to a semiconductor structure, and in particular, it relates to a silicide layer of a semiconductor structure. 
     Description of the Related Art 
     In order to increase element density in a flash memory device and improve its overall performance, existing technologies for fabricating flash memory devices continue to focus on scaling down the size of the elements. However, in scaling down the minimum size of the features (e.g., contacts), new challenges arise. Therefore, there is a need in the industry to improve the method of fabricating flash memory devices to overcome problems caused by scaling down the size of the elements. 
     SUMMARY 
     In some embodiments of the disclosure, a method for forming a semiconductor structure is provided. The method includes forming a gate electrode layer over a semiconductor substrate, forming a first spacer layer to cover a sidewall of the gate electrode layer, recessing the first spacer layer to expose an upper portion of the sidewall of the gate electrode layer, forming a metal material to cover an upper surface and the upper portion of the sidewall of the gate electrode layer, reacting a semiconductor material of the gate electrode layer with the metal material using an anneal process to form a silicide layer, and removing the metal material after the anneal process. 
     In some embodiments of the disclosure, a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a gate electrode layer disposed over the semiconductor substrate, a silicide layer wrapping around an upper portion of the gate electrode layer, and a first spacer layer surrounding a lower portion of the gate electrode layer. The silicide layer includes a central portion and a peripheral portion around the central portion. A first bottom surface of the peripheral portion is located at a same level as an upper surface of the first spacer layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure can be further understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIGS. 1A-1N  illustrate cross-sectional views of forming a semiconductor structure at various stages in accordance with some embodiments of the present disclosure. 
         FIG. 1J-1  is a portion of the semiconductor structure of  FIG. 1J  to illustrate additional details in accordance with some embodiments of the present disclosure. 
         FIG. 2  illustrates a modification of the semiconductor structure of  FIG. 1N  in accordance with some embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The present disclosure is described in detail with reference to the figures of the embodiments of the present disclosure. It should be appreciated, however, that the present disclosure can be embodied in a wide variety of implements and is not limited to embodiments described in the disclosure. Various features may be arbitrarily drawn at different scales for the sake of simplicity and clarity. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. 
       FIGS. 1A-1N  illustrates cross-sectional views of forming a semiconductor structure at various stages in accordance with some embodiments of the present disclosure. 
       FIG. 1A  illustrates a cross-sectional view of a semiconductor structure  100  which includes a memory cell array region  50 A and a periphery circuitry region  50 P. A semiconductor structure  100  is provided, in accordance with some embodiments. The semiconductor structure  100  includes a semiconductor substrate  102 . In some embodiments, the semiconductor substrate  102  is an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In some embodiments, the semiconductor substrate  102  may be a semiconductor-on-insulator (SOI) substrate. 
     The semiconductor substrate  102  includes various device regions such as a memory cell array region  50 A and a periphery circuitry region  50 P, in accordance with some embodiments. The memory cell array region  50 A includes memory cells  104  which are operable as data storage, in accordance with some embodiments. The periphery circuitry region  50 P includes periphery circuitry devices which are configured as transistors, such as metal-oxide-semiconductor field effect transistors (MOSFETs), in accordance with some embodiments. The periphery circuitry devices in the periphery circuitry region  50 P are operable to access and/or control (e.g. performs read/write/erase operation) the memory cells  104  in the memory cell array region  50 A, in accordance with some embodiments. 
     The memory cells  104  are flash memories, such as NOR-type flash memories, in accordance with some embodiments. Openings  105  are formed between the memory cells  104  and expose the upper surface of the semiconductor substrate  102 , in accordance with some embodiments. The memory cells  104  are stacked structures, each of which includes a tunneling oxide (Tox) layer  106 , a floating gate  108 , a gate dielectric layer  110 , a control gate  112 , a conductive layer  114 , a first mask pattern  116  and a second mask pattern  118  sequentially formed over the semiconductor substrate  102 , in accordance with some embodiments. 
     In some embodiments, the tunneling oxide layer  106  is made of silicon oxide; the floating gate  108  and the control gate  112  are made of a semiconductor material (such as polysilicon); the gate dielectric layer  110  is a tri-layer structure including oxide-nitride-oxide (ONO); the conductive layer  114  is made of metal such as tungsten (W), copper (Co), aluminum (Al), or another suitable material or metal silicide such as WSi x ; the first mask pattern  116  is made of nitride (such as silicon nitride); and the second mask pattern  118  is made of oxide (such as silicon oxide). In some embodiments, the first mask pattern  116  and the second mask pattern  118  are configured to define the pattern of the memory cell  104  during the patterning process (including photolithography and etching processes). 
     A gate structure  120  is formed in the periphery circuitry region  50 P of the semiconductor substrate  102 , in accordance with some embodiments. The gate structure  120  and source/drain regions subsequently formed on opposite sides of the gate structure  120  collectively build a transistor. The transistor is used as a component of the periphery circuitry devices and is electrically coupled to the memory cell  104  in the memory cell array region  50 A through a multilayer interconnect structure subsequently formed there above. 
     The gate structure  120  includes a gate dielectric layer  122  formed over the upper surface of the semiconductor substrate  102  and a gate electrode layer  124  formed over the gate dielectric layer  122 , in accordance with some embodiments. In some embodiments, the gate dielectric layer  122  is made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the gate electrode layer  124  is made of conductive material such as a semiconductor material (such as polysilicon). In some embodiments, the semiconductor material of the gate electrode layer  124  is doped to increase the conductivity of the semiconductor material. 
     A capping layer  126  is formed over the upper surface of the gate electrode layer  124 , in accordance with some embodiments. In some embodiments, the capping layer  126  is made of a dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. The capping layer  126  protects the gate structure  120  from being damaged due to the etching process during the patterning process for forming the memory cells  104 , in accordance with some embodiments. 
       FIG. 1B  illustrates a cross-sectional view of a semiconductor structure  100  after the formation of spacer materials  128 ,  130  and  132 . A first spacer material  128 , a second spacer material  130  and a third spacer material  132  are sequentially formed over the semiconductor structure  100 , in accordance with some embodiments. The first spacer material  128  covers and conformally extends along the upper surface of the semiconductor substrate  102 , the sidewalls and the upper surfaces of the memory cells  104 , the sidewalls of the gate structure  120 , and the sidewalls and the upper surface of the capping layer  126 , in accordance with some embodiments. In some embodiments, the first spacer material  128  is made of silicon oxide. 
     The second spacer material  130  covers and conformally extends along the upper surface of the first spacer material  128 , in accordance with some embodiments. In some embodiments, the second spacer material  130  is made of silicon nitride. The first spacer material  128  and the second spacer material  130  partially fill the openings  105 , in accordance with some embodiments. 
     The third spacer material  132  is formed over the second spacer material  130 , in accordance with some embodiments. The third spacer material  132  covers the memory cells  104  and the gate structure  120  and fills remainders of the openings  105 , in accordance with some embodiments. In some embodiments, the third spacer material  132  is made of silicon oxide formed by such as tetraethylorthosilicate (TEOS). 
       FIG. 1C  illustrates a cross-sectional view of a semiconductor structure  100  after the formation of spacer layers  133 P. An etching process is performed on the third spacer material  132  in the periphery circuitry region  50 P to form a pair of spacer layers  133 P on the opposite sidewalls of the gate structure  120 , in accordance with some embodiments. In some embodiments, an etching mask (not shown) such as photoresist is first formed using a photolithography process to cover the memory cell array region  50 A, and an etching process such as anisotropic dry etching is then performed on the semiconductor structure  100 . 
     The etching process removes portions of the third spacer material  132  formed over the upper surface of the semiconductor substrate  102  and the upper surface of the capping layer  126  until the second spacer material  130  is exposed, in accordance with some embodiments. After the etching process, portions of the third spacer material  132  along the sidewalls of the gate structure  120  remain as the spacer layers  133 P, in accordance with some embodiments. An etching byproduct (such as a polymer) created by the dry etching process piles on the semiconductor structure  100 , e.g., along the sidewalls of the gate structure  120 , such that lateral etching amount of the third spacer material  132  deceases as the etching depth increase, in accordance with some embodiments. As a result, the spacer layers  133 P formed along sidewalls of the gate structure  120  have upwardly decreasing widths. 
     After the spacer layers  133 P are formed, the etching mask over the memory cell array region  50 A is removed using a process such as an ashing process, and an etching mask (not shown, such as a photoresist) is formed using a photolithography process to cover the periphery circuitry region  50 P, in accordance with some embodiments. An etching process such as wet etching is performed on the semiconductor structure  100  to remove the third spacer material  132  in the memory cell array  50 A until the second spacer material  130  is exposed, in accordance with some embodiments. The third spacer layer  132  in the memory cell array  50 A is removed entirely, in accordance with some embodiments. The etching mask over the periphery circuitry region  50 P is removed using a process such as an ashing process, in accordance with some embodiments. 
       FIG. 1D  illustrates a cross-sectional view of a semiconductor structure  100  after the formation of spacer layers  131 A and  131 P. An etching process such as dry etching is performed on the second spacer material  130  to form a pair of spacer layers  131 A on the opposite sidewalls of the memory cell  104  and a pair of spacer layers  131 P on the opposite sidewalls of the gate structure  120 , in accordance with some embodiments. 
     In the memory cell array region  50 A, the etching process removes horizontal portions of the second spacer material  130  (e.g., along the upper surface of the semiconductor substrate  102  and the upper surfaces of the memory cells  104 ) until the first spacer material  128  is exposed, in accordance with some embodiments. Vertical portions of the second spacer material  130  (e.g., along the sidewalls of the memory cell  104 ) remain as the spacer layers  131 A, in accordance with some embodiments. 
     In the periphery circuitry region  50 P, the etching process removes horizontal portions of the second spacer material  130  uncovered by the spacer layers  133 P (e.g., along the upper surface of the semiconductor substrate  102  and the upper surface of the gate structure  120 ) until the first spacer material  128  is exposed, in accordance with some embodiments. Vertical portions of the second spacer material  130  along the sidewalls of the gate structure  120  and horizontal portions of the second spacer material  130  covered by the spacer layers  133 P remain as the spacer layers  131 P, in accordance with some embodiments. The spacer layer  131 P has an L-shape profile in the cross-sectional view, in accordance with some embodiments. 
       FIG. 1E  illustrates a cross-sectional view of a semiconductor structure  100  after the formation of spacer layers  129 A and  129 P. An etching process such as dry etching is performed on the first spacer material  128  to form a pair of spacer layers  129 A on the opposite sides of the memory cell  104  and a pair of spacer layers  129 P on the opposite sides of the gate structure  120 , in accordance with some embodiments. 
     In the memory cell array region  50 A, the etching process removes horizontal portions of the first spacer material  128  uncovered by the spacer layer  131 A (e.g., along the upper surface of the semiconductor substrate  102  and the upper surfaces of the memory cells  104 ) until the upper surface of the semiconductor substrate  102  and the second mask patterns  118  of the memory cells  104  are exposed, in accordance with some embodiments. Vertical portions of the first spacer material  128  (e.g., along the sidewalls of the memory cell  104 ) and horizontal portions of the first spacer material  128  covered by the spacer layers  131 A remain as the spacer layers  129 A, in accordance with some embodiments. The spacer layer  129 A has an L-shape profile in the cross-sectional view, in accordance with some embodiments. The spacer layers  129 A and the spacer layers  131 A in combination form cell spacer structures on the opposite sides of the memory cells  104 , in accordance with some embodiments. The cell spacer structure is a bi-layer structure including oxide-nitride (ON). 
     In the periphery circuitry region  50 P, the etching process removes horizontal portions of the first spacer material  128  uncovered by the spacer layer  131 P (e.g., along the upper surface of the semiconductor substrate  102  and the upper surface of the gate structure  120 ) until the semiconductor substrate  102  and the capping layer  126  are exposed, in accordance with some embodiments. Vertical portions of the first spacer material  128  along the sidewalls of the gate structure  120  and horizontal portions the first spacer material  128  covered by the spacer layers  131 P remain as the spacer layers  129 P, in accordance with some embodiments. The spacer layer  129 P has an L-shape profile in the cross-sectional view, in accordance with some embodiments. The spacer layers  129 P, the spacer layers  131 P and the spacer layer  133 P in combination form gate spacer structures on the opposite sides of the gate structure  120 , in accordance with some embodiments. The gate structure  120  is a tri-layer structure including oxide-nitride-oxide (ONO). In some embodiments, the capping layer  126  protects the gate electrode layer  124  from being damaged due to the etching process. 
       FIG. 1F  illustrates a cross-sectional view of a semiconductor structure  100  after the formation of a sacrificial layer  134  and source/drain regions  136 A and  136 P. A sacrificial layer  134  is formed to cover and extend along the semiconductor substrate  102 , the cell spacer structure (including spacer layers  129 A and  131 A), the memory cells  104 , the gate spacer structure (including spacer layers  129 P,  131 P and  133 P), and the capping layer  126 , in accordance with some embodiments. The sacrificial layer  134  may be referred to as a screen oxide and configured to increase the quality of a subsequent ion implantation process. 
     In some embodiments, the sacrificial layer  134  is made of a thin oxide layer such as silicon oxide. 
     An ion implantation process is performed on the semiconductor structure  100  to form source/drain regions  136 A in the semiconductor substrate  102  at the memory cell array region  50 A and source/drain regions  136 P in the semiconductor substrate  102  at the periphery circuitry region  50 P, in accordance with some embodiments. The gate structure  120  and an adjacent pair of source/drain regions  136 P build a transistor in the periphery circuitry region  50 P, which is used as a component of periphery circuitry device, in accordance with some embodiments. A source/drain region  136 A and a source/drain region  135 P which are located at a boundary between the memory cell array region  50 A and the periphery circuitry region  50 P, may share a common doped region. 
       FIG. 1G  illustrate a cross-sectional view of a semiconductor structure  100  after the removal of the sacrificial layer  134  and the capping layer  126 . An etching process is performed on the semiconductor structure  100  to remove the sacrificial layer  134  and the capping layer  126 , in accordance with some embodiments. In some embodiments, the etching process is wet etching. Because the sacrificial layer  134  is thin (e.g., with a thickness of about 10 nm to about 15 nm), an oxide layer (e.g., TESO oxide with a thickness of about 3 nm to about 7 nm) may be formed over the sacrificial layer  134  before the etching process, which may prevent the semiconductor surface of the semiconductor substrate  102  and the gate electrode layer  124  being damage due to etching process. After the etching process, the upper surface of the semiconductor substrate  102 , the upper surface of the gate electrode layer  124  of the gate structure  120  are exposed. Metal silicide is to be formed on these exposed surfaces. 
       FIG. 1H  illustrates a cross-sectional view of a semiconductor structure  100  after a trimming process for the gate spacer structure. An etching process is performed on the semiconductor structure  100  to trim the gate spacer structure in the periphery circuitry region  50 P, in accordance with some embodiments. The etching process recesses upper portions of the spacer layers  129 P and upper portions of the spacer layers  133 P, thereby forming recesses  138  and  140  respectively, in accordance with some embodiments. The spacer layers  131 P remain unetched during the etching process, in accordance with some embodiments. The recessed spacer layer  129 P and the recessed spacer layer  133 P are referred to as a spacer layer  129 P′ and a spacer layer  133 P′ respectively, in accordance with some embodiments. As-trimmed gate spacer structure includes the spacer layer  131 P protruding from between the spacer layer  129 P′ and the spacer layer  133 P′, in accordance with some embodiments. In addition, the spacer layer  129 P′ and the spacer layer  133 P′ each have a substantially flat upper surface, in accordance with some embodiments. The upper surface of the spacer layer  129 P′ and the upper surface of the spacer layer  133 P′ are located at substantially the same level, in accordance with some embodiments. 
     In some embodiments, an etching mask may be formed over the memory cell array region  50 A before the trimming process and removed after the trimming process. In some other embodiments where no etching mask is formed over the memory cell array region  50 A, the second mask patterns  118  and the spacer layers  129 A are also etched. 
     In some embodiments, the etching process is a dry chemical etching process which uses gas phase dilute hydrofluoric (dHF) acid as an etchant. During the etching process, the oxide of the spacer layers  129 P and  133 P has a different etching selectivity than the nitride of the spacer layer  131 P. In specific, the etching rate of the nitride of the spacer layer  131 P is much less than the etching rate of the oxide of the spacer layers  129 P and  133 P, in accordance with some embodiments. 
     In addition, during the etching process, the dry chemical etching process may maintain the lateral etching amount as the etching depth increases, in accordance with some embodiment. That is, during the etching process, the material of the spacer layer  129 P and/or an etching byproduct do not remain in the recess  138  on the sidewall of the gate electrode layer  124  and the sidewall of the spacer layer  131 P. Similarly, the material of the spacer layer  133 P and/or an etching byproduct do not remain in the recess  140  on the other of the sidewall of the spacer layer  131 P. As a result, after the etching process, upper portions of the sidewalls of the gate electrode layer  124  are exposed from the recesses  138 , in accordance with some embodiments. Metal silicide are to be formed on these exposed surfaces. Opposite sidewalls of the vertical portions of the spacer layers  131 P have upper portions  131 S which are exposed from the recesses  138  and  140 , in accordance with some embodiments. 
     In some embodiments, the etching process recesses the spacer layer  129 P and the spacer layer  133 P to a depth D 1  which is in a range from about 3 nm to about 30 nm, such as about 3 nm. In some embodiments, the vertical portion of the spacer layer  129  has a thickness D 2  along the sidewall of the gate structure  120 . The thickness D 2  is in a range from about 15 nm to about 60 nm, such as about 30 nm. In some embodiments, the ratio of the depth D 1  to the thickness D 2  is in a range from about 0.05 to about 2, such as about 0.17. The etching depth D 1  (or the ratio of the depth D 1  to the thickness D 2 ) may be optimized for transistor performance consideration. For example, if the etching depth D 1  (or the ratio of the depth D 1  to the thickness D 2 ) is too small, the contact area of a subsequently formed metal material with the upper portion  124 S of the sidewalls of the gate electrode layer  124  is too small. This will be described in detail below. For example, if the etching depth D 1  (or the ratio of the depth D 1  to the thickness D 2 ) is too large, the gate leakage current of the resulting transistor may increase. In some embodiments, the gate structure  120  has a thickness D 2  in a range from about 200 nm to about 300 nm. 
       FIG. 1I  illustrates a cross-sectional view of a semiconductor structure  100  after the formation of a metal material  152  for silicide layers. A metal material  152  is deposited over the semiconductor structure  100 , in accordance with some embodiments. Before the metal material  152  is formed, the exposed semiconductor surfaces of the semiconductor substrate  102  and the gate electrode layer  124  may be cleaned using an etching process to remove native oxide formed on the semiconductor surfaces of the semiconductor substrate  102  and the gate electrode layer  124 . The clean process and the deposition process may be performed in-situ in the same equipment, thereby preventing the exposed semiconductor surfaces from being exposed to an oxygen-containing ambient during the semiconductor substrate  102  is transferred from a cleaning chamber to a deposition chamber where the metal material  152  is deposited. 
     In the memory cell array region  50 A, the metal material  152  covers and extends along the semiconductor substrate  102 , the cell spacer structures, and the memory cells  104 , in accordance with some embodiments. The metal material  152  is in direct contact with the semiconductor material (e.g., silicon) of the semiconductor substrate  102  at the upper surface of the semiconductor substrate  102 , in accordance with some embodiments. 
     In the periphery circuitry region  50 P, the metal material  152  covers and extends along the semiconductor substrate  102 , the gate spacer structures, and the gate structure  120 , in accordance with some embodiments. The metal material  152  fills the recesses  138  and  140  to abut the upper surface of the spacer layer  133 P′ and the upper surface of the vertical portion of the spacer layer  129 P′, in accordance with some embodiments. The metal material  152  wraps around the protruding portion of the spacer layer  131 P and the upper portion of the gate electrode layer  124 , in accordance with some embodiments. The metal material  152  is in direct contact with the semiconductor material (e.g., silicon) of the gate electrode layer  124  at the upper surface and the upper portions  124 S ( FIG. 1H ) of the sidewalls of the gate electrode layer  124 , in accordance with some embodiments. As such, the metal material  152  covers the corners between the upper surface and the sidewall of the gate electrode layer  124 , in accordance with some embodiments. 
     In some embodiments, the metal material  152  is cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), or another material suitable for forming silicide. 
       FIG. 1J  illustrates a cross-sectional view of a semiconductor structure  100  after the formation of silicide layers  154  and  156 . An anneal process is performed on the semiconductor structure  100  to form a silicide layer  154  on the gate electrode layer  124  and silicide layers  156  on the source/drain regions  156 A and  156 P, in accordance with some embodiments. The silicide layers  154  and  156  may also be referred to as self-aligned silicide (salicide). During the anneal process, the semiconductor material (such as silicon) of the semiconductor substrate  102  and the gate electrode layer  124  is reacted with the metal material  152 , such that portions of the semiconductor material contacting the metal material  152  are transformed into metal silicide, such as cobalt silicide (CoSi), nickel silicide (NiSi), titanium silicide (TiSi), tungsten silicide (WSi), or another suitable metal silicide. Portions of the gate electrode layer  124  unreacted with the metal material  152  are referred to as a gate electrode layer  124 ′, in accordance with some embodiments. In some embodiments, the anneal process may be performed at a temperature of about 250° C. to about 450° C. for a duration of about 30 seconds to about 30 minutes. 
     After the silicide layer  154  and  156  are formed, portions of the metal material  152  unreacted with the semiconductor material are removed, thereby exposing the recesses  138  and  140  again, in accordance with some embodiments. In some embodiments, the recess  138  exposes the sidewalls of the silicide layer  154 . In some embodiments, the removal process is a wet etching process. 
       FIG. 1J-1  is an area A shown in  FIG. 1J  to illustrate additional details of the silicide layer  154 . The silicide layer  154  has an inverted U-shape in the cross-sectional view, in accordance with some embodiments. The silicide layer  154  includes a central portion  154 C and peripheral portions  154 P, in accordance with some embodiments. The peripheral portions  154 P are located around the central portion  154 C and at the edges (or corner) of the original gate structure  124 , in accordance with some embodiments. In some embodiments, the peripheral portions  154 P of the silicide layer  154  may have a bottom surface  154 B 2  which is located at a level below, equal to or above the bottom surface  154 B 1  of the central portion  154 C of the silicide layer  154 , in accordance with some embodiments. 
     It is noted that in an instance where the metal material is formed only over the upper surface of the gate electrode layer, a silicide layer may be formed with a poor thickness uniformity, because the silicide layer may have a much thinner thickness at the edge of the gate electrode layer than a thickness at the center of the gate electrode layer. Or, there is no silicide layer formed at the edge of the gate electrode layer. It may limit the process window of a photolithography process during a subsequent patterning process for forming a contact opening to the gate structure. For example, when a contact plug formed in the contact opening lands on the edge of the gate structure where no silicide layer is formed, an open circuit may happen, thereby reducing the performance of the semiconductor device. 
     In the embodiments of the present disclosure, because of the trimming process, the metal material  152  is in contact with the upper surface and the upper portions  124 S ( FIG. 1H ) of the sidewalls of the gate electrode layer  124 , thereby covering the corner of the gate electrode layer  124 . As a result, the silicide layer  154  formed has the peripheral portions  154 P with a greater thickness at the edge of the gate electrode layer  124 ′, which may improve the uniformity of the silicide layer  154 , e.g., a better uniformity. Therefore, the process window of a photolithography process may be enlarged during a subsequent patterning process for forming a contact opening to the gate structure. For example, overlay window and/or critical dimension (CD) window may be enlarged, thereby increasing the reliability and the manufacturing yield of the semiconductor device. A thickness D 4  of the central portion  154 C of the silicide layer  154  is less than a thickness D 5  of the peripheral region  154 P of the silicide layer  154 , in accordance with some embodiments. 
     In some embodiments, the thickness D 4  of the central portion  154 C of the silicide layer  154  is in a range from about 10 nm to about 30 nm. In some embodiments, the thickness D 5  of the peripheral region  154 P of the silicide layer  154  is in a range from about 15 nm to about 45 nm. The ratio of the thickness D 5  to the thickness D 4  may be optimized for transistor performance consideration. For example, if the thickness D 5  to the thickness D 4  is too small, the process window of a subsequent photolithography process may be not enough. For example, if the thickness D 5  to the thickness D 4  is too large, the gate leakage current of the resulting transistor may increase. 
     Because the peripheral region  154 P of the silicide layer  154  is formed by self-align, the sidewall of the peripheral region  154 P is not covered by the spacer layer  129 P′, in accordance with some embodiments. The upper surface  129 T of the spacer layer  129 P′ and the bottom surface  154 B 2  of the peripheral region  154 P of the silicide layer  154  are located at substantially the same level, in accordance with some embodiments. The silicide layer  154  wraps around the upper portion of the gate electrode layer  124 ′, and the spacer layer  129 P′ surrounds the lower portion of the gate electrode layer  124 ′, in accordance with some embodiments. The sidewall of the upper portion of the gate electrode layer  124 ′ is indented from the sidewall of the lower portion of the gate electrode layer  124 ′ by a distance, e.g., substantially equal to a width D 6  of the peripheral region  154 P, in accordance with some embodiments. The sidewall of the lower portion of the gate electrode layer  124 ′ is aligned with the sidewall of the peripheral region  154 P of the silicide layer  154 , in accordance with some embodiments. The upper surface  131 T of the spacer layer  131 P is located at a higher level than the upper surface  129 T of the spacer layer  129 P′ and the upper surface  133 T of the spacer layer  133 P′, in accordance with some embodiments. 
     In some embodiments, the peripheral region  154 P of the silicide layer  154  has a width D 6 . In some embodiments, the ratio of the thickness D 5  to the width D 6  is in a range from about 1.5 to about 3. In some embodiments, the ratio of width D 6  to width D 7  is in a range from about 20 to about 100. 
       FIG. 1K  illustrates a cross-sectional view of a semiconductor structure  100  after the formation of a protection layer  160 . A protection layer  160  is formed to cover and extend along the silicide layers  156 , cell spacer structures (including spacers  129 A and  131 A), the memory cells  104 , gate spacer structure (including spacers  129 P′,  131 P and  133 P′), and the silicide layers  154 , in accordance with some embodiments. The protection layer  160  fills the recesses  138  and  140  to abut the upper surface  133 T of the spacer layer  133 P′ and the upper surface  129 T of the vertical portion of the spacer layer  129 P′, in accordance with some embodiments. 
       FIGS. 1L-1N  illustrate cross-sectional views of the formation of contact plugs  178  and  180  to the source/drain regions and a contact plug  182  to the gate structure. 
     A polysilicon layer  170  is formed using a deposition process and a patterning process to cover the memory cell array region  50 A of the semiconductor structure  100  and fill remainders of the openings  105 , as shown in  FIG. 1L , in accordance with some embodiments. The polysilicon layer  170  partially covers a memory cell  104  near the boundary between the memory cell array region  50 A and the periphery circuitry region  50 P, in accordance with some embodiments. An etching stop layer  172  is conformally formed over the semiconductor structure  100 , and an interlayer dielectric layer  174  is then formed over the etching stop layer  172 , in accordance with some embodiments. Afterward, a removal process is performed on the interlayer dielectric layer  174  and the etching stop layer  172 . For example, a first chemical mechanical polishing (CMP) process is performed on the interlayer dielectric layer  174  until the etching stop layer  172  formed over the polysilicon layer  170  is exposed. Next, the etching stop layer  172  formed over the polysilicon layer  170  is removed using a process such as wet etching. A second CMP process is then performed on the interlayer dielectric layer  174  and the polysilicon layer  170 , such that the upper surface of the interlayer dielectric layer  174  is substantially coplanar with the upper surface of the polysilicon layer  170 , in accordance with some embodiments. 
     A patterning process is performed on the polysilicon layer  170  to form sacrificial contract plugs  171  in the openings  105  between the memory cells  104 , as shown in  FIG. 1M , in accordance with some embodiments. Mask elements  176  are then formed over the memory cells  104  to fill the spaces between the sacrificial contract plugs  171 , in accordance with some embodiments. In some embodiments, the mask element  176  is made of nitride such as silicon nitride. 
     The sacrificial contract plugs  171  and the protection layer  160  below the sacrificial contract plugs  171  are etched away to form contact opening (not shown) exposing the silicide layer  156  formed on the source/drain region  136 A, in accordance with some embodiments. 
     A patterning process (including a photolithography process and an etching process) is performed on the interlayer dielectric layer  174 , the etching process  172  and the protection layer  160  to form a contact opening (not shown) exposing the silicide layer  156  formed on the source/drain region  136 P and a contact opening (not shown) exposing the silicide layer  154  formed on the gate structure  120 , in accordance with some embodiments. 
     A barrier layer  184  is conformally formed along the sidewalls and the bottom surface of the contact openings, and a conductive material  186  is then formed to fill remainders of the contact opening, as shown in  FIG. 1N , in accordance with some embodiments. The barrier layer  184 A and the conductive material  186  formed above the mask element  176  and the interlayer dielectric layer  174  may be removed using CMP process, thereby forming contact plugs  178 ,  180  and  182 , in accordance with some embodiments. The contact plugs  178  land on the silicide layers  156  on the source/drain regions  136 A; the contact plug  180  lands on the silicide layer  156  on the source/drain regions  136 P; and contact plug  182  lands on the silicide layer  154  on the gate structure  120 , in accordance with some embodiments. 
     In some embodiments, additional components may be formed over the semiconductor structure  100  of  FIG. 1N , thereby producing a semiconductor memory device such as a flash memory device, in accordance with some embodiments. For example, a multilayer interconnect structure (e.g., including conductive lines and vias in intermetal dielectric layers) may be formed over the semiconductor structure  100  to electrically couple the memory cell  104  in the memory cell array region  50 A and the periphery circuitry device in the periphery circuitry region  50 P. 
       FIG. 2  illustrates a modification of the semiconductor structure of  FIG. 1N  in accordance with some embodiments of the present disclosure.  FIG. 2  shows a transistor structure which is similar to the transistor structure shown in  FIG. 1N  except that a contact plug  182  shown in  FIG. 2  lands on the silicide layer  154  at the edge of the gate structure  120 . In detail, the contact plug  182  overlays and contacts the peripheral portion  154 P of the silicide layer  154 . Because the silicide layer  154  includes the peripheral portion  154 P with a greater thickness, the problem of the open circuit described above may be avoided. 
     As described above, the embodiments of the present disclosure provide a method for forming a semiconductor structure. By trimming the gate spacer structure (e.g., recessing the spacer layer  129 P and  133 P), the metal material for forming the silicide layer can cover the upper surface and the upper portion of the sidewalls of the gate electrode layer. As a result, in the embodiments of the present disclosure, the silicide layer formed has a greater thickness at the edge (or corner) of the gate electrode layer. Therefore, the process window of forming the contact plug to the gate structure may be enlarged, thereby increasing the reliability and the manufacturing yield of the semiconductor device. 
     While the disclosure has been described by way of example and in terms of the preferred embodiments, it should be understood that the disclosure is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.