Patent Publication Number: US-2003225802-A1

Title: Enable generator EG, and method of mapping data using the EG

Description:
FIELD OF THE INVENTION  
       [0001] The present invention relates to a method of converting a lower bit rate data stream into a higher bit rate data stream with a low jitter, and to this end, to a method of mapping, and to systems utilizing the methods.  
       BACKGROUND OF THE INVENTION  
       [0002] Converting a lower bit rate data stream incoming a converter, into a higher bit rate data stream outgoing the converter, is usually provided by inserting between binary words of the incoming lower rate data stream so-called “silent” binary words which fill extra positions not carrying information in the outgoing higher rate data stream. The “silent” portions are usually provided by temporary disabling transmission of information bits of the incoming data stream.  
       [0003] The presence of such “silent” positions in the real data create a so-called jitter effect which shows itself as sharp undesired changes in the frequency and amplitude of the “netto” information when filtered from the outgoing signal. Long and unequal time distances between the “silent” positions in the outgoing data stream degrade the quality of transmission.  
       [0004] U.S. Pat. No. 6,226,661 teaches one method of obtaining distributed jitter in sample rate conversion, and describes a technique of converting bit rates using binary ratios to express bit rates relation. The method requires complex calculations and compensation of phase differences introduced by the converter.  
       [0005] To the best of the Applicant&#39;s knowledge, no simple practical solutions are described in the prior art to obtain low jitter bit rate conversions, which would enable conversion of any bit rate to a required one by easy adjusting the converter.  
       [0006] Also, no methods are described, which would propose a low jitter mapping of a low bit rate data stream into a high bit rate data stream.  
       OBJECT OF THE INVENTION  
       [0007] It is therefore an object of the present invention to provide a simple technique of enabling/disabling signals generation to ensure low jitter transmission of an incoming lower rate data stream by an outgoing higher rate data stream, and a technique of mapping using such an enable generator.  
       SUMMARY OF THE INVENTION  
       [0008] There is firstly proposed a cyclic generator of enabling/disabling signals (Enable Generator—EG) suitable for converting an incoming data stream with a bit rate R1 into an outgoing data stream with a higher bit rate R2, wherein R1≅mR2/n, m&lt;n , m and n—integers, the EG having a number of internal states ≦n and being capable of generating periodic enabling/disabling output signals such that the disable signals are optimally distributed among the enable signals.  
       [0009] The integers m and n are the EG parameters selected so as to provide m enable signals for n clocks of the bit rate R2. The meaning “clocks” is to be understood herein as time intervals between periodic, accurately spaced synchronization signals serving a particular bit rate. Depending on a particular implementation, one or more bits of information can be transmitted per one clock (said time interval).  
       [0010] It should be mentioned, however, that sometimes in the specification the term “clock” is used in the meaning of a synchronization frequency proportional to a particular bit rate.  
       [0011] It will further be shown that the parameters m, n can also be adjustable to maintain stable, error free bit rate conversion.  
       [0012] In other words, the EG disable signals occur between the EG enable signals with a minimal periodicity, so that the single disable signals are almost uniformly distributed between the enable ones.  
       [0013] It should be noted that the disable signal can be either a preselected signal different from the enable signal, or (preferably) just an absence of the enable signal in the predetermined timing.  
       [0014] In the most preferred embodiment, the EG, to ensure the above requirement, is capable of generating enabling/disabling signals according to the following rules:  
       [0015] a) selecting an initial state S of the generator, S&lt;n;  
       [0016] b) at a clock of bit rate R2 of the outgoing data stream, obtaining a current state of the generator S′=S+μm  
       [0017] c) if S′≧n , enabling transmission of a bit from data of the incoming data stream, and replacing the current state S′ with (S′−n);  
       [0018] if S′&lt;n , disabling transmission of a bit of the incoming data stream, without changing the current state S′,  
       [0019] d) at the next clock, repeating from step b, while using the current state as a new initial state.  
       [0020] Mathematically, the above algorithm can be written down as the following two operations, taking place per one clock of the R2 bit rate:  
         E =( S+m ) divn    
         S =( S+m ) modn    
       [0021] The generator as described above can be used in various cases of data transmission.  
       [0022] A simple idea of selecting m and n parameters of the EG to convert an incoming data stream having a bit rate R1 to an outgoing data stream having a bit rate R2 allows using one common internal bit rate (clock) R2 in a chip handling at its inputs a number of incoming data streams with respective different bit rates R1′, R1″ . . . and outputting one or more outgoing data streams respectively having these same bit rates R1′, R1″ . . . or bit rates derived therefrom (say, multiples thereof). To implement this idea, at least at the inputs of the chip, respective differently adjusted EG generators are provided each cooperating with a FIFO, to convert the incoming data streams&#39; bit rates into the common internal bit rate R2, so that the core of the chip operates at said common internal bit rate R2.  
       [0023] For example, a chip of this type may be required for implementing such network elements as regenerators, transponders, or the like.  
       [0024] Preferably, a particular input FIFO can be used for storing data inputted at the bit rate (clock) R1, the corresponding EG can be used for creating enable-disable signals which are used a) for reading the FIFO at the clock R2 thus creating an internal data stream at the clock R2, and b) for transmitting a corresponding internal stream of the enabling/disabling signals in parallel with the internal data stream. Both these internal streams can be transformed in the chip for handling the particular incoming data stream, and finally utilized at the corresponding output for creating the outgoing data stream at the clock R1 or kR1. The number of outgoing data streams may be unequal to the number of incoming data streams.  
       [0025] The proposed EG also allows suggesting a new method of low-jitter mapping of an incoming (client&#39;s) data stream, into a succession of data frames of an outgoing data stream having a higher bit rate, wherein each of the frames comprises an overhead portion and a payload portion,  
       [0026] the method comprises:  
       [0027] using a first cyclic generator of enable/disable signals (EG) as described above, to control filling the payload portion of each data frame of the outgoing data stream with information bits of the incoming data stream diluted with stuffing bits, wherein the filling is performed at the bit rate R2, the incoming data stream has the bit rate R1, and R1≅mR2/n, m&lt;n, m and n are integers;  
       [0028] using at least one predetermined location in the overhead portion of at least one of said data frames to indicate an internal state of the EG corresponding to a suitable payload portion, for further de-mapping of said portion.  
       [0029] The filling of the payload is performed by inserting the information bits when the EG generates enable signals, and inserting stuffing bits when the EG does not generate enable signals.  
       [0030] The high bit rate outgoing data stream can be, for example, one of standard data streams belonging to well known telecommunication technologies such as SDH, SONET, OTN, PDH.  
       [0031] For example, the predetermined location (S-location) may constitute any non-specified overhead byte in the first frame. The information in such a byte, whenever is read at a receiving site, serves as a de-mapping key i.e., informs a de-mapper about the internal state of the first EG at which the mapping of the first frame payload was started. Position of the S-location in the overhead may correspond to a particular payload bit, or row of the first frame from which the mapping started. Actually, the state may be transmitted once and be used up to any random fault distresses the system. After a fault, the state must be refreshed. So, in the absence of faults, the EG internal state may be transmitted only once. However, it may be transmitted each frame, or even several times per one frame if so desired, either for confirming the initial internal state or for updating a current internal state.  
       [0032] In other words, the above-described method of low-jitter mapping is logically followed by de-mapping at a receiving end with the aid of a second EG identical to the first EG, wherein the de-mapping comprises:  
       [0033] adjusting the second EG to have parameters m and n respectively identical to said parameters of the first EG,  
       [0034] obtaining (reading) the internal state of the first EG from said predetermined location of the overhead portion of one of said frames and setting the second EG into the obtained internal state,  
       [0035] using the second EG to read the incoming data stream, from the payload portion corresponding to the internal state, at the bit rate RI.  
       [0036] The mapping may be a so-called synchronous mapping, wherein the parameters m and n are respectively constant and known in advance. In other words, m and n are known in advance both at a transmitting side and at the receiver side, and both the first EG and the second EG can be adjusted for the whole transmission session.  
       [0037] In practice, the mapping is usually performed when both R1 and R2 may slightly change, so the m/n ratio is not constant. In this case, there is proposed a method of asynchronous mapping, wherein the ratio m/n #const, the method further comprising  
       [0038] monitoring ratio between the bit rates R1 and R2 (by monitoring depth of the FIFO) periodically adjusting the ratio m/n to (m/n)t in the first EG generator according to the current ratio between R1 and R2, and  
       [0039] for further de-mapping, simultaneously indicating in a predetermined location of the overhead portions of the data frames, information enabling obtaining the adjusted ratio (m/n), actual for a particular period of transmission.  
       [0040] The above method enables regulating the mapping by using a current (m/n)t up to a new adjusted ratio (m/n)t is obtained.  
       [0041] To maintain the bit rate R2 constant in conditions when RI and/or R2 drift from their initial values, at least one of the current actual parameters n, m is to be updated thereby adjusting the ratio (m/n)t .  
       [0042] The indication of such an adjustment can be performed by inserting current binary values of m, n in predetermined places of the overhead portion of the data frames of the outgoing data stream at a pre-determined moment of time, for obtaining (m/n)t at the receiving site.  
       [0043] The step of de-mapping at the receiving site, preferably, will further comprise reading the updated parameters m and n from the overhead portion of a frame and adjusting the second EG to the obtained parameters m, n up to receiving newly updated said parameters.  
       [0044] The above-described methods suppose using relatively simple and easily modified means for converting an incoming data stream having an arbitrary bit rate, into a higher bit rate outgoing data stream.  
       [0045] Owing to that, the same concept may be applied for enveloping and transmitting a number of client&#39;s data streams via a high rate transport data stream while preserving the advantage of low jitter.  
       [0046] Therefore, a method is further provided for transporting, with a low jitter, “k” incoming data streams having arbitrary bit rates, by “k” SONET/SDH lower order data streams further multiplexed into a SONET/SDH higher order data stream, the method comprising mapping each of said incoming data streams into a corresponding lower order SDH/SONET data stream according to the above-described mapping methods, and  
       [0047] multiplexing the obtained “k” lower order SONET/SDH data streams into the higher order transport data stream using a bit-interleaving principle.  
       [0048] There are also proposed suitable systems for low jitter mapping and a system for low jitter data transport which will be described below. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0049]FIG. 1 a —is a diagram schematically illustrating the principle of the proposed generator of enable/disable signals (EG).  
     [0050]FIG. 1 b —is a flow-chart of the EG.  
     [0051]FIG. 1 c —is an exemplary table illustrating transitions between internal states of the EG, and output enabling signals.  
     [0052]FIG. 2—is a block-diagram of a system schematically illustrating a mapping/demapping principle using the proposed EG.  
     [0053]FIG. 3—is a modified diagram showing how asynchronous mapping can be implemented.  
     [0054]FIG. 4—is a schematic block diagram illustrating the transmission of a number of incoming data streams using one transport data stream and the above-described mapping/de-mapping principle.  
     [0055]FIG. 5—is a schematic block diagram illustrating a system handling a number of incoming and outgoing streams having different clocks, while utilizing a common internal clock inside the system. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
     [0056]FIG. 1 a  schematically illustrates a circular diagram of the proposed cyclic enable generator (EG). The function of the EG is to generate enable/disable signals for reading data incoming (say, a FIFO) with an arbitrary client bitrate R1, at another bit rate—for example, to allow further transmittion of this data with this another bitrate R2, wherein R1=mR2/n (R2, for example, is any selected SDH rate), wherein both m and n are integers and m&lt;n. The meaning of the ratio is that for each n clocks of the enable generator EG (i.e., for each n clocks of R2) there will be m clocks with enabling signals to transform the bit rate R1 into bitrate R2.  
     [0057]FIG. 1 a  illustrates the diagram for an exemplary case where n=9, m=5.  
     [0058] To begin its operation, the generator EG defines an initial state (condition) S within a cycle being n clocks,  
     [0059] at each clock the generator changes the state so that S′=S+m,  
     [0060] and acts as follows:  
     [0061] if S′&gt;n , a bit from the incoming data is transmitted (ENABLED), and the condition S′ replaced by S′−n=S+m-n;  
     [0062] if S′&lt;n , no bit of the incoming data is transmitted (DISABLED), and the condition S′ remains the same.  
     [0063] The mathematically written algorithm is illustrated in FIG. 1 b , and is performed by the EG at each clock of R2 bit rate:  
       E ( S+m ) divn,    
       S ′=( S+m ) modn.    
     [0064] Let S=2. In the table, shown in FIG. 1 c , one may see that the disabling signals are maximally uniformly distributed among the enabling ones. It should be noted that the EG of this particular example has nine different internal states, i.e., as many as the number “n” of clocks. However, the number of different internal states may be less than “n”, i.e. the EG may not pass some specific states. How the numbers m and n are selected in real schemes? Naturally, the ratio of real bit rates R1/R2 can be obtained since the real bit rates are known. According to the above equation, R1/R2=m/n. If one of the parameters (say, n) is selected, the other parameter m, with a particular accuracy, can be found as m=(R1/R2)n. In real EG schemes, n can be selected to be  106  or even more, the values n and m are preferably held in binary registers (the structure of EG is not shown).  
     [0065] Accuracy of the proposed EG can be set in advance by selecting the length of binary registers assigned for the parameters “m” and “n”. For example, registers of 20 bits enable representing numbers in the order of millions, and allow converting bitrates differing in small values with a mistake close to ±0.5 single PPM values (i.e., values expressing bitrate changes of 0 to 0.5 Pulses Per Million). For example, the PPM required for bit rates in SDH networks should not exceed ±4.6 PPM. Therefore, the mentioned length of the EG registers is sufficiently accurate for SDH applications.  
     [0066]FIG. 2 schematically illustrates a system  10  where a first enable generator EG1 marked  12  is used for mapping a data stream having bitrate RI into informational payloads  14  of frames  16 , with a bit rate R2. The frames  16  (for example, SDH frames each comprising a payload portion  14  and an overhead portion  15 ) are transmitted from a transmitter site  25  to a receiver site  27 . The transmitter site comprises a transmitter Rx  18 , a FIFO  20 , EGI  12  and a circuit  22  which will be called an overhead synchronized reader (OHSR). The receiver site  27  symmetrically comprises an overhead synchronized writer OHSW  24 , a second enable generator EG2 marked  26 , a FIFO  28  and a receiver  30 .  
     [0067] Enable generators  12  and  26  are identical. FIG. 2 illustrates a version of synchronous mapping, i.e., such where the parameters m, n themselves, and the ratio m/n are preset and constant. The generators  12  and  26  are preliminarily adjusted to the required ratio between the bit rates R1 and R2, by setting registers m and n therein. Such a mapping can be utilized when the R1 and R2 are synchronized in advance, for example created by one and the same source, say R2 is created by a PLL circuit from R1. Using the enable generator  12  capable of uniformly diluting enable signals with disable signals, the mapping can be provided with a very low and, most important, distributed jitter. Exact algorithm of the EG may vary. The frame  16  is formed from the data stored in the FIFO  20  by combined action of the EGI and OHSR. The function of OHSR is to distinguish between the overhead and payload portions of the frame and to ensure insertion of an initial state S of the EG1 in a predetermined location  32  of the overhead  15 . Further, when the OHSR declares a payload zone, and the EG1 gives an enable write signal, the payload  14  will be filled by data from the FIFO periodically stuffed at those positions which correspond to disable signals of the EG1. By doing this, the distributed stuffing is provided, which results in the controlled distributed jitter.  
     [0068] To enable further de-mapping data from the frame  16  and the following frames, and re-conversion thereof into the bit rate R1, indication of the S corresponding to the mapping pattern should be found in at least one of the frames arriving to the receiving site. This indication is allocated by OHSW, forwarded to the EG2 ( 26 ) and stored in it, so as to ensure that EG2 will start operating beginning from the state S. The payload portion of the frame  16  is detected by the OHSW  24  and written into FIFO  28  as is, with the rate R2. The EG2 ( 26 ) will enable reading only the data “netto” from FIFO  28 , since it starts operating from the state S and uses the same values of the m,n parameters. The data “netto” without stuffing will therefore be read from the FIFO  28  and transmitted to the receiver  30  with the bit rate R1.  
     [0069]FIG. 3 illustrates a modified system  40  suitable for a case of asynchronous mapping (m/n const). Such a mapping can be useful where one or both of the bit rates R1, R2 vary in time, to avoid errors in converting the data. When the real ratio between the bit rates changes, FIFO  20  may suffer from the following two critical conditions. A critical condition of the approaching overflow of the FIFO would appear if the bit rate R1 increases/bit rate R2 decreases, and a critical condition of fast emptying of the FIFO occurs from the opposite reasons. These conditions can be detected by a detector D ( 21 ) of the FIFO depth.  
     [0070] To overcome this problem without creating errors, the mapping mechanism should be adjusted and therefore it inevitably becomes asynchronous.  
     [0071] The asynchronous mapping suggests adjusting the m/n ratio from time to time, based on monitoring the FIFO condition. By doing this, the output (R2) bit rate can be maintained constant.  
     [0072] For example, the EG generator  20  may slightly reduce the rate of emptying the FIFO, if the FIFO is close to emptying, so “m” can be reduced. And vise versa. The generator may be adjusted from the point of m, from the point of n, or both.  
     [0073] Whenever either of the parameters m, n are updated in a transmitted frame and in the enabling generator at the transmitting site, the de-mapping site should be informed about it, too. It will happen if the receiving site is informed in advance, what are the places in the OH area where the updated information on m,n appears and what is the time to update the enabling generator after that. To do that, the Inventors propose indicating the changed parameter(s) in pre-set locations  31 ,  33  of the overhead portion of the transmitted data stream. This information enables obtaining the adjusted ratio (m/n) t  actual for a particular period of transmission for further de-mapping.  
     [0074] To provide de-mapping at the receiving site, the OHSW  24  should detect the presence of updating information on m and/or n in the pre-set locations  31 ,  33  of the frame overhead, and forward it to the EG2 ( 26 ) together with the information on S in the location  32 . The EG  26  will therefore be adjusted to de-map the suitable portion of data according to the updated ratio (m/n) t . The EG  12  and EG  26  will work according to the updated conditions up to the ratio is changed due to any new fluctuations in the bit rates R1 and/or R2.  
     [0075]FIG. 4 shows that the mapping principle mentioned above can be used for “packing” a number of lower rate data streams into a higher rate data stream, while preserving the advantage of distributed stuffing (and jitter).  
     [0076] In a system  50 , three lower rate data streams from clients A,B and C having respective rates R1A, R1B, R1C, are mapped into three STM-1 SDH data streams, all having a standard SDH rate (R2). Each of the three left side parallel branches of the system is provided with its own EG (not shown) set for its own combination of the parameters m and n. Each of the STM-1 data streams carries data supplied by the corresponding lower rate data stream. In this example, every STM-1 frame also carries information S on the state of the corresponding EG and information on the parameters m and n or their change. This information is indicated in predetermined locations of the overhead of the standard STM-1 frame. These locations may be different for different data streams R1A, R1B, R1C, but form the point of modularity of the systems they are preferably the same.  
     [0077] Four STM-1 streams may further be multiplexed into one STM-4 high order data stream. Out of the four STM-1 streams, three STM-1s respectively comprising the data of R1A, R1B, R1C will be used. The remaining fourth STM-1 may comprise any data to be transmitted via the same SDH transmitting line with the bit rate R2. In this particular example, this stream is idle, i.e. comprises all stuffing bits.  
     [0078] Owing to the bit-interleaving principle of multiplexing, the information comprised in all four STM-1 streams will be uniformly mixed in the STM-4 data stream and thereby the jitter will remain uniform even in case the fourth (stranger) data stream comprises only stuffing bits.  
     [0079] The obtained STM-4 data stream will be finally de-multiplexed at the receiving site, upon which each relevant STM-1 stream can be de-mapped using information on the suitable S, m, n preserved in the overhead of the STM-1 frames, and utilizing the corresponding EG (not shown) which is to be set according to the received S, m and n.  
     [0080] The advantage of such a mapping is that one may, using a modular and easily adjustable equipment, combine a number of data streams having different non-standard bit rates into one higher rate transport data stream.  
     [0081]FIG. 5 schematically illustrates a chip  60  intended for handling a number of incoming data streams D, F, . . . K having different bit rates (clocks) R1d, R1f, . . . R1k. In the chip, each of the incoming data streams (say, a stream symbolically called I with the bit rate R1i) is converted, using a corresponding input FIFO(ii) and a corresponding enable generator EG(i), into a) an internal data stream having the internal clock R2 carrying data (i) and thus marked R2i and b) an internal stream of enable/disable signals marked E(i). It should be noted that, for maintaining the stable conversion, the FIFO depth can be monitored similarly to the manner illustrated in FIG. 3, and parameters m, n of the enable generator EGi can be adjusted accordingly. In the chip, the mentioned internal streams can be modified owing to handling the incoming data streams: for example, performing for them a FEC (Forward Error Correction) operation, overhead processing, and the like. Such operations may change the internal enable data stream and, consequently, a pattern of the parallel internal data stream. When outputting the processed data stream, the modified internal data stream Ri′ can be written into a corresponding output FIFO (io) using its parallel internal enable data stream Ei′. From the FIFO (io), information can be outputted at the initial bit rate (clock) R1i, thus forming the output data stream I′. In this drawing, the outgoing data streams are shown fully symmetric to the incoming data streams, both from the point of their quantity and their output clocks. The system  60  can serve, for example, as a network regenerator for a number of data streams. However, the system (a chip) can be designed to output a number of outgoing data streams non equal to the number of incoming data streams. Moreover, the outgoing data streams may have clocks derived from the clocks of the respective incoming data streams, for example as it takes place in optical transponders.  
     [0082] It should be appreciated that, in the frame of the inventive concept, other implementations of the enabling generator can be found and various modifications of the mapping-demapping technique, as well as of a chip utilizing a common internal clock can be proposed, which should all be considered parts of the invention.