Patent Publication Number: US-2022224349-A1

Title: Calibration scheme for a non-linear adc

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
     This application claims priority from India provisional patent application No. 202141001383 filed on Jan. 12, 2021 which is hereby incorporated by reference in its entirety. 
     TECHNICAL FIELD 
     This description relates generally to analog to digital converters (ADCs), and more particularly to using a lookup-table in ADCs. 
     BACKGROUND 
     In many electronic devices, an analog input signal is converted to a digital output signal using an analog to digital converter (ADC). The ADC used for digitizing a signal in a radio-frequency (RF) sampling receiver may be required to operate at high speed. Such speeds may be in the order of giga samples per second (GSPS). However, there is a need to correct the non-linearity of the high-speed ADCs. 
     SUMMARY 
     In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum. 
     The present disclosure also relates to a method of operating an analog to digital converter (ADC). The method includes generating a delay signal responsive to a calibration signal, providing the delay signal to a backend ADC, the backend ADC having a first stage of a plurality of stages, measuring an error count of the first stage by a calibration engine, the error count is an absolute difference in a number of ones and zeroes generated by the first stage, and storing a delay value of the first stage in the calibration engine for which the error count is minimum. 
     The present disclosure also relates to a device that includes a processor, a memory coupled to the processor, and an analog to digital converter (ADC). The ADC is coupled to the processor and the memory. The ADC, having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a circuit, according to an example embodiment; 
         FIG. 2  is a block diagram of a portion of the circuit illustrated in  FIG. 1 , according to an example embodiment; 
         FIG. 3  is a block diagram of a portion of the circuit illustrated in  FIG. 1 , according to an example embodiment; 
         FIG. 4  is a flowchart of a method of operation of a circuit, according to an example embodiment; 
         FIG. 5  is a flowchart of a method of operation of a circuit, according to an example embodiment; 
         FIG. 6  is a graph which illustrates AND-gate delay and comparator delay generated by an AND gate and a delay comparator, respectively, in a stage of a backend ADC, according to an example embodiment; 
         FIG. 7  is a graph which illustrates output-signal delay of a stage as a function of the input-signal delay of the stage of a backend ADC, according to an example embodiment; 
         FIGS. 8A and 8B . are graphs which illustrates output-signal delay of different stages as a function of the input-signal delay of a backend ADC, according to an example embodiment; and 
         FIG. 9  is a block diagram of an example device  900  in which several aspects of example embodiments can be implemented. 
     
    
    
     The same reference numbers or other reference designators are used in the drawings to designate the same or similar (structurally and/or functionally) features. 
     DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS 
       FIG. 1  is a block diagram of a circuit  100 , according to an example embodiment. The circuit  100  includes a calibration engine  102 , a digital to analog converter (DAC)  104 , a multiplexer M  112 , a voltage to delay (VD) block  106 , a backend analog to digital converter (ADC)  124  and a storage circuit  108 . The DAC  104  is coupled between the calibration engine  102  and the multiplexer M  112 . The multiplexer M  112  is also coupled to the calibration engine  102 . In one version, the multiplexer M  112  is controlled by the calibration engine  102 . The multiplexer M  112  receives an input voltage Vin  110 . The VD block  106  is coupled to the multiplexer M  112  and the calibration engine  102 . The backend ADC  124  is coupled to the VD block  106  and the calibration engine  102 . The storage circuit  108  is coupled to the backend ADC  124  and the calibration engine  102 . The storage circuit  108  may be constructed of digital memory circuits, register, flip-flops, RAM, ROM, transitory memory, part of a conventional memory circuit and/or part of a digital processor system. 
     The VD block  106  includes a preamplifier array  116  and a delay multiplexer DM  120 . The preamplifier array  116  is coupled to the multiplexer M  112  and includes one or more preamplifiers. The delay multiplexer DM  120  is coupled to the preamplifier array  116 . The backend ADC  124  is coupled to the delay multiplexer DM  120 . The backend ADC  124  may include multiple stages, such as a first stage and a second stage as illustrated in  FIG. 3 . Each stage includes a delay block, an AND gate and a delay comparator. The calibration engine  102  is coupled to the multiple stages in the backend ADC  124 . The calibration engine  102 , in one example, includes an accumulator. The accumulator is coupled to the multiple stages in the backend ADC  124 . The calibration engine  102 , in one example, is or is a part of, a processing unit, a digital signal processor (DSP), a processor and/or a programmable logic device. The calibration engine  102  may include memory, logic and/or software. 
     In some example embodiments, each of the components of the VD block  106  are capable of communicating with the calibration engine  102  independently, and with other components of the circuit  100 . Each block or component of the circuit  100  may also be coupled to other blocks in  FIG. 1 . Those connections are not described herein. The circuit  100  may include one or more conventional components that are not described herein for simplicity of the description. 
     The circuit  100 , in one example, is an analog to digital converter where the VD block  106  performs a voltage-to-delay function and the backend ADC  124  perform a delay-to-digital function. The circuit  100  operates in a delay-calibration mode, a memory-calibration mode and a mission mode. The mission mode is also referred as normal operation mode. The delay-calibration mode and the memory-calibration mode are now explained, in that order. 
     The calibration engine  102  generates multiple input codes which, in some example embodiments, correspond to a range of a known analog signal. In one example, the multiple input codes range from a minimum input code to a maximum input code. The multiple input codes, in one example, are uniformly distributed both in terms of frequency and step size. Step size, in one version, is a difference between two consecutive input codes. The DAC  104  generates calibration signal in response to each of the multiple input codes. For example, the DAC  104  generates a first calibration signal (e.g. a first analog calibration signal) in response to a first input code of the multiple input codes. The first calibration signal is received by the VD block  106 . 
     The multiplexer M  112 , in both delay-calibration mode and memory-calibration mode, provides the first calibration signal to the preamplifier array  116 . The multiplexer M  112 , in one example, is controlled by the calibration engine  102 . Each pre-amplifier in the VD block  106  has a different threshold voltage. As illustrated in  FIG. 2 , each pre-amplifier in the preamplifier array  116  includes a first input connected to the output of the multiplexer M  112  (to receive the input signal, Vin  110  or the calibration signal from the DAC  104 ) and a second input coupled to a threshold voltage. Each pre-amplifier in the preamplifier array  116 , in both delay-calibration mode and memory-calibration mode, compares the first calibration signal to a threshold voltage (e.g. the threshold voltage associated with each preamplifier in the preamplifier array  116 ). The delay multiplexer DM  120  generates a delay signal based on an output of one of the preamplifiers. 
     The first stage in the backend ADC  124  generates a digital bit in response to the delay signal from the delay multiplexer DM  120 . Thus, the calibration engine  102  generates multiple input codes; the DAC  104  generates multiple calibration signals in response to the multiple input codes; and the VD block  106  generates multiple delay signals in response to the multiple calibration signals; and the first stage in the backend ADC  124  generates multiple digital bits in response to the multiple delay signals. These multiple digital bits generated by the first stage represents a digital code generated by the first stage in response to the multiple input codes generated by the calibration engine  102 . 
     The delay-calibration mode, in one example, includes multiple cycles. In one cycle, the calibration engine  102  modifies a delay value of a first delay block in the first stage. The calibration engine  102  generates multiple input codes. The first stage in the backend ADC  124  generates a digital code in response to the multiple input codes. The accumulator in the calibration engine  102  measures an error count of the first stage. The error count is an absolute difference in a number of ones and zeroes in the digital code. Based on the error count, the calibration engine  102  modifies the delay value of the first delay block in the subsequent cycle. The calibration engine  102  measure the error counts generated by the first stage in multiple such cycles. The calibration engine  102  stores a delay value of the first stage for which the error count of the first stage is minimum. This delay value is the delay value (or calibrated delay value) of the first delay block in the first stage. In one example, the circuit  100  uses a binary search or other known technique to find the delay value for which error count is minimum. A non-linearity at an output of a stage of backend ADC  124  is caused by a non-linear transfer function of that stage. The delay-calibration mode calibrates the stage to define an optimal gain for that stage across a range defined by multiple input codes. 
     The calibration engine  102  subsequently calibrates the delay value of a second delay block in the second stage. This includes multiple cycles as well. In one cycle, the calibration engine  102  modifies a delay value of the second delay block in the second stage. The calibration engine  102  generates multiple input codes. The second stage generates a digital code in response to the multiple input codes. The accumulator in the calibration engine  102  measures an error count of the second stage. The error count is an absolute difference in a number of ones and zeroes in the digital code. Based on the error count, the calibration engine  102 , in the subsequent cycle, modifies the delay value of the second delay block. The calibration engine  102  measures the error counts generated by the second stage in multiple such cycles. The calibration engine  102  stores the delay value of the second stage for which the error count of the second stage is minimum. This delay value is the delay value (or calibrated delay value) of the second delay block in the second stage. 
     In the same way, the calibration engine  102  measures an error count of each stage of the multiple stages in the backend ADC  124  across multiple cycles, and also stores a delay value of each stage of the backend ADC  124 . The delay value (or calibrated delay value) for each stage of the multiple stages in the backend ADC  124  are used subsequently during other modes of operation of the circuit  100 . In one example, the delay values are used to correct any non-linearities introduced in the backend ADC  124 . The delay-calibration mode is explained in detail in connection with circuit  300  illustrated in  FIG. 3 . 
     In the memory-calibration mode, the calibration engine  102  generates multiple input codes. The multiple input codes, in some example embodiments, correspond to a range of a known analog signal. The DAC  104  generates a calibration signal in response to an input code of the multiple input codes. The VD block  106  generates a delay signal in response to the calibration signal. The backend ADC  124  generates an output code in response to the delay signal. The storage circuit  108  stores the input code at an address associated with the corresponding output code. For example, the storage circuit  108  stores a first input code at an address corresponding to the first output code, and the storage circuit  108  stores a second input code at an address corresponding to a second output code. In one example embodiment, the storage circuit  108  maintains, for all input codes, a look-up table to store an input code at an address corresponding to an associated output code. For example, in one version, when an output code  100  is generated corresponding to the input code  010 , the input code  010  is stored at the address  100  in the look-up table. Thus, the look-up table in the storage circuit  108  is populated in the memory-calibration mode with the input codes at respective addresses of output codes. 
     In the mission mode, the multiplexer M  112  provides the input voltage Vin  110  to the VD block  106 . The multiplexer M  112 , in one example embodiment, is controlled by the calibration engine  102 . The VD block  106  generates a delay signal in response to the input voltage Vin  110 . The backend ADC  124  generates a raw code in response to the delay signal. An input code stored at an address corresponding to the raw code is generated as a final output  130  by the circuit  100 . For each value of the input voltage Vin  110 , the raw code is matched to an address of the output code, and the input code stored at the address is provided as the final output  130 . Thus, the mission mode represents, in one version, normal operation of the circuit  100  in which an analog signal (such as a radio frequency analog signal) is received as Vin  110  and converted to a digital (e.g. binary) representation via the VD block  106 , the backend ADC  124  and the storage circuit  108 . The final output  130  is thus a digital representation of the analog signal Vin  110 . 
     The multiplexer M  112 , the VD block  106 , the backend ADC  124  and the storage circuit  108  form one channel in the circuit  100 . The circuit  100  can be implemented with two or more channels. In one example embodiment, each channel may be implemented in parallel with other channels. A second channel would include a second multiplexer, a second VD block, a second backend ADC and a second storage circuit. The second backend ADC in the second channel may be similar to the backend ADC  124  but both are calibrated separately as both may have different transfer functions because of manufacturing variations. Multiple channels allow the flexibility to have one channel in calibration mode (delay-calibration mode or memory-calibration mode) and the other channels operate in mission mode. Multiple channels also allow flexibility to have one or more channels in delay-calibration mode, one or more channels in memory-calibration mode and other channels in mission mode. Thus, when one or more channels are being calibrated, remaining channels are used in mission mode for analog to digital conversion. In one example, all the channels are calibrated using the DAC  104 , and all channels are controlled by the calibration engine  102 . In some example embodiments, there is no need to perform any matching between the channels as the backend ADC in each channel is calibrated independently. This also reduces the requirement of background estimation and calibration algorithms. 
     The combination of the preamplifier array  116 , the delay multiplexer DM  120  and the backend ADC  124 , in one example, acts as a non-linear ADC or delay-based ADC. Though this combination is highly non-linear, the circuit  100  is highly linear and operates at high speed with relaxed area and power requirements. The circuit  100  scales well with technology nodes. The circuit  100  pushes the high linearity requirement on the DAC  104 . This is advantageous because it is relatively less difficult to design and implement analog circuits for operation at lower speed with linearity and accuracy. According to the present disclosure, the backend ADC  124  may be designed to run at high speed by compromising linearity. However, with the backend ADC  124  operating in conjugation with the look-up table in the storage circuit  108 , the circuit  100  behaves like a linear analog to digital converter (ADC). Likewise, the storage circuit  108  may be implemented in digital circuits, and be configured for high speed. 
     Interfacing external analog signals to fast digital processing cores generally requires an ADC. With higher speeds in transmission of data, the ADC may be required to operate at very high speeds and with a good signal-to-noise ratio. Without the benefits of some example embodiments, such constraints could result in large power dissipation and large area requirements for the supporting integrated circuit. These issues may be especially prominent at fast sampling rates (for example, sampling rates in the order of giga-samples per second (GSPS)) because of analog non-idealities which may limit performance. The example embodiments of circuit  100  provides a backend ADC  124  with the lookup-table approach that can open up wide architectures using one or more non-linear ADCs but can be calibrated to provide the superior performance of a highly linear ADC. 
     In delay-calibration mode, a delay value of each delay block in the backend ADC  124  is calibrated and fixed. This ensures that the circuit  100  has a minimum gain throughout multiple input codes (which corresponds to a range of a known analog signal) generated by the calibration engine  102 . The gain of circuit  100  is affected by delay value of each stage in the backend ADC  124 , and the delay-calibration mode ensures that the delay value of each stage is calibrated optimally for the circuit  100  to operate as a linear high-speed ADC. The delay-calibration mode allows circuit  100  to act as a linear ADC as delays of each stage in the backend ADC  124  is calibrated to achieve optimal gain across a range defined by multiple input codes. 
     Hence, the circuit  100  does not require any complex algorithms or hardware for digital conversion of the input voltage Vin  110 . This reduces the area and power requirements of the circuit  100 . Thus, the circuit  100  is capable of being used in RF sampling receivers which operate at speeds of GSPS. The circuit  100  scales well with technology nodes and is capable of supporting high GSPS transfer rates in future technology nodes. 
       FIG. 2  is a block diagram of a portion of the circuit  100  illustrated in  FIG. 1 , according to an example embodiment. The preamplifier array  116  includes multiple preamplifiers from  1  to n, where n is an integer, for example, pre-amp  216   a , pre-amp  216   b  to pre-amp  216   n . In one example embodiment, one or more preamplifiers is a threshold integrated preamplifier (a preamplifier with a fixed threshold). The delay multiplexer DM  120  is coupled to the multiple preamplifiers in the preamplifier array  116 . The backend ADC  124  is coupled to an output of the delay multiplexer DM  120 . The calibration engine  102  is coupled to each preamplifier in the preamplifier array  116  via input line  240 , the delay multiplexer DM  120  and the backend ADC  124 . The calibration engine  102 , in one example, reset the preamplifiers through input line  240 . 
     In operation, the preamplifier array  116  receives the input voltage Vin  110 , in mission mode, from the multiplexer M  112 . Similar to amplifiers 54-60 of U.S. Pat. No. 10,673,456 (which is hereby incorporated by reference in its entirety), each preamplifier receives a different threshold voltage. For example, the pre-amp  216   a  receives a threshold voltage Vt 1 , the pre-amp  216   b  receives a threshold voltage Vt 2  and the pre-amp  216   n  receives a threshold voltage Vtn. In one example, Vt 1 &lt;Vt 2 &lt;Vtn. The threshold voltages Vt 1 , Vt 2  to Vtn are generated using, in one example embodiment, a voltage divider  230 . In one version, the pre-amp  216   n  is coupled to a voltage supply directly or through a resistor. Each preamplifier generates a first and a second output signals (differential output signals) based on the difference between the input voltage Vin  110  and the threshold voltage. For example, the pre-amp  216   a  generates differential signals—a first output signal OUT_M 1  and a second output signal OUT P 1 . Similarly, the pre-amp  216   n  generates differential signals—a first output signal OUT_Mn and a second output signal OUT_Pn. 
     Similar to the operation of multiplexer 211 in U.S. Pat. No. 10,673,452 (which is hereby incorporated by reference in its entirety), the delay multiplexer DM  120  receives the first and the second output signal (differential output signals) from each preamplifier of the multiple preamplifiers. The delay multiplexer DM  120  generates a delay signal  202  based on an output of one of the preamplifiers. The delay signal  202  includes a first delay signal OUT_M and a second delay signal OUT_P, and corresponds to the output signals of a preamplifier whose threshold voltage is closest to the input voltage Vin  110 . For example, if the magnitude of the input voltage Vin  110  is closest to the threshold voltage Vt 1  of the pre-amp  216   a , the first delay signal OUT_M and the second delay signal OUT_P corresponds to the first and second output signals OUT_M 1  and OUT_P 1  of the pre-amp  216   a . On the other hand, if the magnitude of the input voltage Vin  110  is closest to the threshold voltage Vt 2  of the pre-amp  216   b , the first delay signal OUT_M and the second delay signal OUT_P corresponds to the first and second output signals OUT_M 2  and OUT_P 2  of the pre-amp  216   b . In one example, the calibration engine  102  controls the delay multiplexer DM  120  to select the output signals of a preamplifier whose threshold voltage is closest to the input voltage Vin  110 . In another example, the calibration engine  102  controls the delay multiplexer DM  120  in calibration mode (both delay-calibration mode and memory-calibration mode), and a high-speed logic controls the delay multiplexer DM  120  in the mission mode. In some example embodiments, the high-speed logic includes a processor, memory, digital logic and/or a state machine. 
     In some example embodiments, the VD block  106  (combination of the preamplifier array  116  and the delay multiplexer DM  120 ) converts the input voltage Vin  110  into delay signal  202  (OUT_P and OUT_M), such that the timings of the delay signal  202  (OUT_P and OUT_M) are representative of the input voltage Vin  110 . The VD block  106 , which may be used to generate the delay signal  202  (OUT_P and OUT_M) based on the input voltage Vin  110 , may be constructed and operated, for example, as described in U.S. Pat. No. 10,673,456 (based on U.S. patent application Ser. No. 16/410,698). The VD block  106  may include, for example, a conversion and folding circuit described in U.S. Pat. No. 10,673,456, which includes multiple preamplifiers for converting a voltage signal into delay signal, and also includes a folding block that contains multiple logic gates for selecting earlier-arriving and later-arriving ones of the first delay signal OUT_M and a second delay signal OUT_P. 
     Examples of voltage-to-delay devices which may be incorporated within the VD block  106 , and used to generate the delay signal  202  (OUT_P and OUT_M) based on the input voltage Vin  110 , are illustrated in U.S. patent application Ser. No. 17/131,981, filed Dec. 23, 2020. A voltage-to-delay device constructed in accordance with U.S. patent application Ser. No. 17/131,981 may have, for example, first and second comparators connected to first and second lines carrying complementary voltages representative of the input voltage Vin  110 , for generating first and second output signals during an active phase when the complementary voltages reach a suitable threshold voltage, such that delay between the output signals is representative of the input voltage Vin  110 . The present disclosure is not limited, however, to the devices and processes described in detail herein. Other suitable devices may perform a suitable voltage-to-delay function within the VD block  106 . As noted above, the entire disclosures of U.S. Pat. No. 10,673,456 and U.S. patent application Ser. No. 17/131,981 are incorporated herein by reference. 
     The preamplifiers (pre-amp  216   a , pre-amp  216   b  to pre-amp  216   n ) within the preamplifier array  116  have varying gains (e.g. “gain” as used herein may mean voltage gain, current gain or a delay—as discussed in more detail below, amplifiers/comparators have different delays based on the input signals) as a result of various factors, which may include design, process, input voltage Vin  110 , and/or temperature. In one example, the gains and ranges of the preamplifier pre-amp  216   a , pre-amp  216   b  to pre-amp  216   n  may be adjusted, and preferably matched across the preamplifier array  116 . The preamplifier array  116  and the backend ADC  124  enables the circuit  100  to operate as a high-speed and high-performance analog to digital converter (ADC). 
       FIG. 3  is a block diagram of a portion of the circuit  100  illustrated in  FIG. 1 , according to an example embodiment. The backend ADC  124  includes multiple stages illustrated as: a first stage  310   a , a second stage  310   b  to an n th  stage  310   n , where n is an integer greater than or equal to one and is not necessary equivalent to the value of n used in  FIG. 2 . Each stage includes a delay block, an AND gate and a delay comparator. For example, the first stage  310   a  includes a delay block  304   a , an AND gate  306   a  and a delay comparator  308   a . Similarly, the second stage  310   b  includes a delay block  304   b , an AND gate  306   b  and a delay comparator  308   b . The illustrated AND gates are merely examples, however, of logic gates that may be employed according to this disclosure. If desired, this disclosure may be implemented with or without AND gates and/or with or without gates other than AND gates. Further, in the illustrated configuration, the AND gates  306   a ,  306   b  to  306   n  may be essentially identical to each other, and the delay comparators  308   a ,  308   b  to  308   n  may be essentially identical to each other. 
     The calibration engine  102  is coupled to the multiple stages in the backend ADC  124 . The calibration engine  102  includes a first multiplexer MUX 1   314  and an accumulator  316 . The accumulator  316  includes a second multiplexer MUX 2   322 , an adder  324  and a register  326 . The delay block in each stage of the backend ADC  124  is coupled to the calibration engine  102 . For example, the delay block  304   a , the delay block  304   b  to the delay block  304   n  are coupled to the calibration engine  102 . The delay comparator in each stage of the backend ADC  124  is coupled to the first multiplexer MUX 1   314  in the calibration engine  102 . For example, the delay comparator  308   a , the delay comparator  308   b  to the delay comparator  308   n  are coupled to the first multiplexer MUX 1   314  in the calibration engine  102 . 
     The accumulator  316  is coupled to the first multiplexer MUX 1   314 . The second multiplexer MUX 2   322  is coupled to the first multiplexer MUX 1   314 . The adder  324  is coupled to the second multiplexer MUX 2   322  and the register  326 . It is understood that the calibration engine  102  can include multiple other parts which are not illustrated here for simplicity. The calibration engine  102  may include one or more conventional components that are not described herein for simplicity of the description. Multiple components of backend ADC  124  may be coupled to and communicate with the calibration engine  102 . However, these connections are not shown in  FIG. 3  for simplicity. 
     In operation, signals AN and BN (where N=1, 2 . . . n, for first stage  310   a , second stage  310   b  to  n   th  stage  310   n  respectively) are received by respective ones of the AND gates  306   a ,  306   b  to  306   n . The AND gates  306   a ,  306   b  to  306 ( n −1) generate corresponding signals AN′. For example, AND gate  306   a  receives signal A 1  and B 1  and generates A 1 ′. For each one of the AND gates, the timing of the leading edge of signal AN′ tracks the timing of the leading edge of the later-arriving of signals AN and BN. 
     The circuit  100  operates in a delay-calibration mode, a memory-calibration mode and a mission mode. The delay-calibration mode and the memory-calibration mode are now explained, in that order. The calibration engine  102  generates multiple input codes. The multiple input codes, in some example embodiments, correspond to a range of a known analog signal. In one example, the multiple input codes range from a minimum input code to a maximum input code. The multiple input codes, in one example, are uniformly distributed both in terms of frequency and step size. Step size, in one version, is a difference between two consecutive input codes. The DAC  104  generates calibration signal in response to each of the multiple input codes. For example, the DAC  104  generates a first calibration signal (e.g. a first analog calibration signal) in response to a first input code of the multiple input codes. The first calibration signal is received by the VD block  106 . 
     The multiplexer M  112 , in both delay-calibration mode and memory-calibration mode, provides the first calibration signal to the preamplifier array  116 . The multiplexer M  112 , in one example, is controlled by the calibration engine  102 . Each pre-amplifier in the VD block  106  has a different threshold voltage. As discussed in connection with  FIG. 2 , the delay multiplexer DM  120  outputs a delay signal  302  based on an output of one of the preamplifiers. The delay signal  302  includes differential signals (a first delay signal OUT_M and a second delay signal OUT_P), and corresponds to the output signals of a preamplifier whose threshold voltage is closest to the calibration signal. In one example, the calibration engine  102  enables the delay multiplexer DM  120  in calibration mode (both delay-calibration mode and memory-calibration mode), and a high-speed logic enables the delay multiplexer DM  120  in the mission mode. In some example embodiments, the high-speed logic includes a processor, memory, digital logic and/or a state machine. 
     The backend ADC  124  receives the delay signal  302  (OUT_P and OUT_M) from VD block  106 . The timings of the first delay signal OUT_M and a second delay signal OUT_P have a delay which is representative of the input voltage Vin  110 . The first stage  310   a  in the backend ADC  124  generates a digital bit in response to the delay signal  302  from the delay multiplexer DM  120 . Thus, the calibration engine  102  generates multiple input codes, the VD block  106  generates multiple delay signals in response to multiple input codes and the first stage  310   a  in the backend ADC  124  generates multiple digital bits in response to the multiple delay signals. These multiple digital bits generated by the first stage  310   a  represents a digital code generated by the first stage in response to the multiple input codes generated by the calibration engine  102 . Thus, the digital code includes multiple digital bits, and a digital bit corresponds to an input code. 
     The delay-calibration mode may be implemented over multiple cycles. For example, with reference to a delay calibration of the first stage  310   a , in one cycle, the calibration engine  102  modifies a delay value D 1   312   a  of the delay block  304   a  in the first stage  310   a . The calibration engine  102  generates multiple input codes. The first stage  310   a  in the backend ADC  124  generates a digital code in response to the multiple input codes. The digital code from the first stage  310   a  is provided to the accumulator  316  in the calibration engine  102  through the first multiplexer MUX 1   314 . The accumulator  316  in the calibration engine  102  measures an error count of the first stage  310   a . The error count is an absolute difference in a number of ones and zeroes in the digital code. 
     In operation, the accumulator  316  processes the digital bits in the digital code serially, in one version. The accumulator  316  includes the second multiplexer MUX 2   322  which receives the digital bit from the first multiplexer MUX 1   314 . Based on the digital bit, the second multiplexer MUX 2   322  generates one of the inputs, +1 or −1. The adder  324  adds a previous value of the error count which is stored in the register  326  to the input received from the second multiplexer MUX 2   322 , and generates a new value of the error count. This new value of the error count is stored in the register  326 . 
     Based on the error count stored in the register  326 , the calibration engine  102  modifies the delay value D 1   312   a  of the delay block  304   a  in a subsequent cycle (e.g. a next cycle). The calibration engine  102  measures the error count generated by the first stage  310   a  in multiple such cycles. The calibration engine  102  stores a delay value of the first stage  310   a  for which the error count of the first stage  310   a  is minimum. This delay value is the delay value D 1   312   a  of the delay block  304   a  in the first stage  310   a . The delay value D 1   312   a  of the first stage  310   a  is stored in a memory location (not shown in  FIG. 3 ) specific to the first stage  310   a . Thus, the calibration engine  102  provides multiple input codes over multiple cycles, and a delay value of a stage (for example the first stage  310   a ) is iteratively modified until the delay-calibration mode for that stage is complete. A non-linearity at an output of a stage of backend ADC  124  is caused by a non-linear transfer function of that stage. The delay-calibration mode calibrates the stage to define an optimal gain for that stage across a range defined by multiple input codes. For example, the stored delay value D 1   312   a  of the first stage  310   a  is used to compensate any non-linearity caused by the non-linear transfer function of the first stage  310   a . Hence, the delay calibration mode calibrates the first stage  310   a  to achieve an optimal gain for the first stage  310   a  across a range defined by multiple input codes. 
     Once the first stage  310   a  is calibrated, the calibration engine  102  calibrates a delay value D 2   312   b  of the delay block  304   b  in the second stage  310   b . This includes multiple cycles as well. In one cycle, the calibration engine  102  modifies the delay value D 2   312   b  of the delay block  304   b  in the second stage  310   b . The calibration engine  102  generates multiple input codes. The second stage  310   b  generates a digital code in response to the multiple input codes. The accumulator  316  in the calibration engine  102  measures an error count of the second stage  310   b . The error count is an absolute difference in a number of ones and zeroes in the digital code. Based on the error count stored in the register  326 , the calibration engine  102  modifies the delay value D 2   312   b  of the delay block  304   b  in the subsequent cycle. The calibration engine  102  measures the error count generated by the second stage  310   b  in multiple such cycles. The calibration engine  102  stores a delay value of the second stage  310   b  for which the error count of the second stage  310   b  is minimum. This delay value is the delay value D 2   312   b  of the delay block  304   b  in the second stage  310   b . The delay value D 2   312   b  may be stored in a memory location (not shown in  FIG. 3 ) specific to the second stage  310   b  or in the same memory as the stored delay value D 1   312   a  or in a separate memory. 
     In the same way, the calibration engine  102  measures an error count of each stage of the multiple stages in the backend ADC  124  across multiple cycles, and also stores a delay value of each stage of the backend ADC  124 . Based on the error count of each stage, the delay value, for each stage is modified by the calibration engine  102  to get optimal uniform gain till that stage. Thus, the delay calibration mode may be performed iteratively whereby a delay value of a stage is calibrated over one or more cycles followed by calibrating a delay value of a next stage. During the calibration-mode, each stage ( 310   a ,  310   b  . . .  310   n ) is iteratively calibrated and a corresponding delay value (D 1 , D 2  . . . Dn) is generated and stored, as described above. The delay value (or calibrated delay value) for each stage of the multiple stages in the backend ADC  124  are used subsequently during other modes of operation of the circuit  100 . Thus, the circuit  100  uses a single accumulator  316  for calibrating all the stages in the backend ADC  124 . 
     In the memory-calibration mode, the calibration engine  102  generates multiple input codes. The multiple input codes, in some example embodiments, correspond to a range of a known analog signal. The DAC  104  generates a calibration signal in response to an input code of the multiple input codes. The VD block  106  generates a delay signal in response to the calibration signal. The backend ADC  124  generates an output code in response to the delay signal. The delay values of multiple stages in the backend ADC  124  stored during the delay-calibration mode are used in the memory calibration mode to generate the output code. The storage circuit  108  stores the input code at an address associated with the corresponding output code. For example, the storage circuit  108  stores a first input code at an address corresponding to the first output code, and the storage circuit  108  stores a second input code at an address corresponding to a second output code. In one example embodiment, the storage circuit  108  maintains, for all input codes, a look-up table to store an input code at an address corresponding to an associated output code. For example, in one version, when an output code  100  is generated corresponding to the input code  010 , the input code  010  is stored at the address  100  in the look-up table. Thus, the look-up table in the storage circuit  108  is populated in the memory-calibration mode with the input codes at respective addresses of output codes. 
     In the mission mode, the multiplexer M  112  provides the input voltage Vin  110  to the VD block  106 . The multiplexer M  112 , in one example embodiment, is controlled by the calibration engine  102 . The VD block  106  generates a delay signal in response to the input voltage Vin  110 . The backend ADC  124  generates a raw code in response to the delay signal. An input code stored at an address corresponding to the raw code is generated as a final output  130  by the circuit  100 . For each value of the input voltage Vin  110 , the raw code is matched to an address of the output code, and the input code stored at the address is provided as the final output  130 . Thus, when the input voltage Vin  110  is received by the circuit  100 , a digital code corresponding to the input voltage Vin  110  is generated by the circuit  100  and the look-up table in the storage circuit  108  is used by the circuit  100  in conversion of the input voltage Vin  110  to the digital code. 
     In delay-calibration mode, a delay value of each delay block in the backend ADC  124  is calibrated and fixed. This ensures that the circuit  100  has a minimum gain throughout multiple codes (which corresponds to a range of a known analog signal) generated by the calibration engine  102 . The gain of circuit  100  is affected by delay value of each stage in the backend ADC  124 , and the delay-calibration mode ensures that the delay value of each stage is calibrated optimally for the circuit  100  to operate as a linear high-speed ADC. The delay-calibration mode allows circuit  100  to act as a linear ADC as delays of each stage in the backend ADC  124  is calibrated to achieve optimal gain across a range defined by multiple input codes. 
     Hence, the circuit  100  does not require any complex algorithms or hardware for digital conversion of the input voltage Vin  110 . This reduces the area and power requirements of the circuit  100 . Thus, the circuit  100  is capable of being used in RF sampling receivers which operate at speeds of GSPS. The circuit  100  scales well with technology nodes and is capable of supporting high GSPS transfer rates in future technology nodes. 
       FIG. 4  is a flowchart  400  of a method of operation of a circuit, according to an example embodiment. The flowchart  400  is described in connection with the circuit  100  of  FIG. 1  and/or its components illustrated in  FIG. 2  and  FIG. 3 . The flowchart  400  illustrates a methodology for operating a circuit in delay calibration mode. At step  402 , a delay signal is generated in response to a calibration signal. In circuit  100 , the calibration engine  102  generates multiple input codes. The multiple input codes, in some example embodiments, correspond to a range of a known analog signal. In one example, the multiple input codes range from a minimum input code to a maximum input code. The multiple input codes, in one example, are uniformly distributed both in terms of frequency and step size. Step size, in one version, is a difference between two consecutive input codes. The DAC  104  generates calibration signal in response to each of the multiple input codes. For example, the DAC  104  generates a first calibration signal (e.g. a first analog calibration signal) in response to a first input code of the multiple input codes. The VD block  106  receives the calibration signal and generates the delay signal. The VD block  106  includes the preamplifier array  116  and the delay multiplexer DM  120 . The multiplexer M  112  provides the first calibration signal to the preamplifier array  116 . The multiplexer M  112 , in one example, is controlled by the calibration engine  102 . Each pre-amplifier in the VD block  106  has a different threshold voltage. Each pre-amplifier in the preamplifier array  116 , in both delay-calibration mode and memory-calibration mode, compares the first calibration signal to a threshold voltage (e.g. the threshold voltage associated with each preamplifier in the preamplifier array  116 ). The delay multiplexer DM  120  generates the delay signal based on an output of one of the preamplifiers. As explained in connection with  FIG. 3 , the delay signal  302  includes a first delay signal OUT_M and a second delay signal OUT_P, and corresponds to the output signals of a preamplifier whose threshold voltage is closest to the calibration signal. 
     At step  404 , the delay signal is provided to a backend ADC. The backend ADC includes a first stage of multiple stages. The error count of the first stage is measured by the calibration engine, at step  406 . The error count is an absolute difference in a number of ones and zeroes generated by the first stage. The backend ADC  124  includes multiple stages illustrated in  FIG. 3  as first stage  310   a , a second stage  310   b  to an nth stage  310   n . Each stage includes a delay block, an AND gate and a delay comparator. 
     The first stage  310   a  in the backend ADC  124  generates a digital bit in response to the delay signal  302  from the delay multiplexer DM  120 . The calibration engine  102  generates multiple input codes; the VD block  106  generates multiple delay signals in response to the multiple input codes; and the first stage  310   a  in the backend ADC  124  generates multiple digital bits in response to the multiple delay signals. These multiple digital bits generated by the first stage  310   a  represents a digital code generated by the first stage in response to the multiple input codes generated by the calibration engine  102 . 
     The first stage  310   a  in the backend ADC  124  generates a digital code in response to the multiple input codes. The digital code from the first stage  310   a  is provided to the accumulator  316  in the calibration engine  102  through the first multiplexer MUX 1   314 . The accumulator  316  in the calibration engine  102  measures an error count of the first stage  310   a . The error count is the absolute difference in a number of ones and zeroes in the digital code. 
     At step  408 , a delay value of the first stage is stored in the calibration engine for which the error count is minimum. In circuit  100 , the calibration engine  102  stores a delay value of the first stage  310   a  for which the error count of the first stage  310   a  is minimum. This delay value is the delay value D 1   312   a  of the delay block  304   a  in the first stage  310   a.    
     The circuit  100  operates in a delay-calibration mode which may be implemented over multiple cycles. For example, with reference to a delay calibration of the first stage  310   a , in one cycle, the calibration engine  102  modifies a delay value D 1   312   a  of the delay block  304   a  in the first stage  310   a . The calibration engine  102  generates multiple input codes. The first stage  310   a  in the backend ADC  124  generates a digital code in response to the multiple input codes. The digital code from the first stage  310   a  is provided to the accumulator  316  in the calibration engine  102  through the first multiplexer MUX 1   314 . The accumulator  316  in the calibration engine  102  measures an error count of the first stage  310   a . The error count is the absolute difference in a number of ones and zeroes in the digital code. 
     Based on the error count, the calibration engine  102  modifies the delay value D 1   312   a  of the delay block  304   a  in a subsequent cycle (e.g. a next cycle). The calibration engine  102  measures the error count generated by the first stage  310   a  in multiple such cycles. The calibration engine  102  stores a delay value of the first stage  310   a  for which the error count of the first stage  310   a  is minimum. This delay value is the delay value D 1   312   a  (or calibrated delay value) of the delay block  304   a  in the first stage  310   a . The delay value D 1   312   a  of the first stage  310   a  is stored in a memory location (not shown in  FIG. 3 ) specific to the first stage  310   a . Thus, the calibration engine  102  provides multiple input codes over multiple cycles, and a delay value of a stage (for example the first stage  310   a ) is iteratively modified until the delay-calibration mode for that stage is complete. A non-linearity at an output of a stage of backend ADC  124  is caused by a non-linear transfer function of that stage. The delay-calibration calibration mode calibrates the stage to define an optimal gain for that stage across a range defined by multiple input codes. For example, the stored delay value D 1   312   a  of the first stage  310   a  is used to compensate any non-linearity caused by the non-linear transfer function of the first stage  310   a . Hence, the delay calibration mode calibrates the first stage  310   a  to achieve an optimal gain for the first stage  310   a  across a range defined by multiple input codes. 
     Once the first stage  310   a  is calibrated, the calibration engine  102  calibrates a delay value D 2   312   b  of the delay block  304   b  in the second stage  310   b . This includes multiple cycles as well. In one cycle, the calibration engine  102  modifies the delay value D 2   312   b  of the delay block  304   b  in the second stage  310   b . The calibration engine  102  generates multiple input codes. The second stage  310   b  generates a digital code in response to the multiple input codes. The accumulator  316  in the calibration engine  102  measures an error count of the second stage  310   b . The error count is an absolute difference in a number of ones and zeroes in the digital code. Based on the error count, the calibration engine  102 , in the subsequent cycle, modifies the delay value D 2   312   b  of the delay block  304   b . The calibration engine  102  measures the error count generated by the second stage  310   b  in multiple such cycles. The calibration engine  102  stores a delay value of the second stage  310   b  for which the error count of the second stage  310   b  is minimum. This delay value is the delay value D 2   312   b  (or calibrated delay value) of the delay block  304   b  in the second stage  310   b . The delay value D 2   312   b  may be stored in a memory location (not shown in  FIG. 3 ) specific to the second stage  310   b  or in the same memory as the stored delay value D 1   312   a  or in a separate memory. 
     In the same way, the calibration engine  102  measures an error count of each stage of the multiple stages in the backend ADC  124  across multiple cycles, and also stores a delay value (or calibrated delay value) of each stage of the backend ADC  124 . Based on the error count of each stage, the delay value, for each stage is modified by the calibration engine  102  to compensate for non-linearities in the delay of each stage. Thus, the delay calibration mode may be performed iteratively whereby a delay value of a stage is calibrated over one or more cycles followed by calibrating a delay value of a next stage. The delay value for each stage of the multiple stages in the backend ADC  124  are used subsequently during other modes of operation of the circuit  100 . 
     The method enables the circuit  100 , in delay-calibration mode, to calibrate and fix a delay value of each delay block in the backend ADC  124 . This ensures that the circuit  100  has a minimum gain throughout multiple codes generated by the calibration engine  102 . The gain of circuit  100  is affected by delay value (which, for example, is subject to irregularities and non-linearities based on semiconductor manufacturing variations and temperature-dependent factors) of each stage in the backend ADC  124 , and the method through the delay-calibration mode ensures that the delay value of each stage is calibrated optimally for the circuit  100  to operate as a high-speed ADC. The delay-calibration mode allows circuit  100  to act as a linear ADC as delays of each stage in the backend ADC  124  is calibrated to achieve optimal gain across a range defined by multiple input codes. 
     Hence, the method provides that the circuit  100  does not require any complex algorithms or hardware for digital conversion of the input voltage Vin  110 . Thus, the method of some example embodiments ensures that the circuit  100  is capable of being used in RF sampling receivers which operate at speeds of GSPS. The circuit  100  scales well with technology nodes and is capable of supporting high GSPS transfer rates in future technology nodes. 
       FIG. 5  is a flowchart  500  of a method of operation of a circuit, according to an example embodiment. The flowchart  500  is described in connection with the circuit  100  of  FIG. 1  and/or its components illustrated in  FIG. 2  and  FIG. 3 . The flowchart  500  illustrates calibrating multiple stages  310   a ,  310   b  to  310   n  using the delay calibration mode which, for example, includes multiple cycles. At step  502 , a delay value of stage k is set. In circuit  100 , for example, the backend ADC  124  includes multiple stages illustrated in  FIG. 3  as first stage  310   a , a second stage  310   b  to an nth stage  310   n . Each stage includes a delay block, an AND gate and a delay comparator. The calibration engine  102  sets a delay value D 1   312   a  of the delay block  304   a  in the first stage  310   a.    
     At step  504 , a calibration engine generates multiple input codes. For example, in circuit  100 , the calibration engine  102  generates multiple input codes. The first stage  310   a  (or stage k) in the backend ADC  124  generates a digital code in response to the multiple input codes. The digital code from the first stage  310   a  (or stage k) is provided to the accumulator  316  in the calibration engine  102 . At step  506 , a number of ones (c 1 ) and zeroes (c 0 ) at output of stage k is counted. An absolute error count (E) is measured from a difference in the number of ones (c 1 ) and zeroes (c 0 ). 
         E=|c 1− c 0|  (1)
 
     The accumulator  316  in the calibration engine  102  measures an error count of the first stage  310   a  (or stage k). The error count is an absolute difference in a number of ones and zeroes in the digital code generated by the first stage  310   a  (or stage k). At step  508 , it is determined if search (calibration of stage k) is complete. The search (or calibration of stage k) is considered complete when the error count at the output of stage k has been obtained for all the input codes. In one version, search is considered complete when there is a change in sign of the error count (E) for stage k. In another example embodiment, search is considered complete when a minimum absolute value of error count (E) is achieved. If the search (calibration of stage k) is complete, the method proceeds to step  512  else the method proceeds to step  520 . 
     At step  512 , the delay value for stage k is modified. The delay value is modified based on the error count (E) (or relative counts of ones and zeroes) for that stage. If the error count (E) is greater than zero, the delay value of the stage k is incremented and if the error count (E) is less than zero, the delay value of the stage k is decremented. In circuit  100 , for example, based on the error count (or counts of ones and zeroes), the calibration engine  102 , modifies the delay value D 1   312   a  of the delay block  304   a  in the first stage  310   a . In one version, if the error count is greater than a threshold, the delay value of the delay block  304   a  is incremented, and if the error count is lesser than a threshold, the delay value of the delay block  304   a  is decremented. 
     Steps  504  to  512  are repeated until the search (or delay calibration) is complete for stage k. In one version, steps  504  to  512  are repeated until there is a change in sign of the error count (E) for stage k. In another example embodiment, steps  504  to  512  are repeated until a minimum absolute value of error count (E) is achieved. In circuit  100  as well, the delay calibration mode may include multiple cycles. In one example, the delay calibration starts from the first stage  310   a  (k=1), at step  502 . In each cycle of step  504  to  512 , the calibration engine  102  iteratively modifies the delay value D 1   312   a  of the delay block  304   a . The calibration engine  102  measures the error count generated by the first stage  310   a  in multiple such cycles. 
     At step  520 , the delay of stage k is fixed for which minimum absolute value of the error count (E) is achieved. In circuit  100 , the calibration engine  102  stores a delay value of the first stage  310   a  for which the absolute value of error count of the first stage  310   a  is minimum. This delay value is the delay value D 1   312   a  of the delay block  304   a  in the first stage  310   a . At step  524 , in a system having n stages where n is the last stage, the method compares if k is equal to n. At step  526 , if the method has not reached the last stage, k is incremented by one, in one example. In another example, k is incremented by an integer greater than 1. Thereafter, all the steps illustrated in flowchart  500  are repeated for stage k+1. 
     At step  528 , if the method has reached the last stage (n), the system resets and the steps illustrated in flowchart  500  are repeated from first stage to nth stage. Similarly, in circuit  100 , the calibration engine  102  measures an error count of each stage of the multiple stages in the backend ADC  124  across multiple cycles, and also stores a delay value of each stage of the backend ADC  124 . The delay value for each stage of the multiple stages in the backend ADC  124  are used subsequently during other modes of operation of the circuit  100 . In some example embodiments, step  528  is optional. 
     The method illustrated by flowchart  500  enables the circuit  100 , in delay-calibration mode, to calibrate and compensate for a delay value of each delay block in the backend ADC  124 . This ensures that the circuit  100  has a minimum gain throughout multiple codes generated by the calibration engine  102 . The gain of circuit  100  is affected by delay value of each stage in the backend ADC  124 , and the method through the delay-calibration mode ensures that the delay value of each stage is calibrated optimally for the circuit  100  to operate as a high-speed ADC. The method allows circuit  100  to act as a linear ADC as delays of each stage in the backend ADC  124  is calibrated to achieve optimal gain across a range defined by multiple input codes. 
     Hence, the method provides that the circuit  100  does not require any complex algorithms or hardware for digital conversion of the input voltage Vin  110 . This reduces the area and power requirements of the circuit  100 . Thus, the method ensures that the circuit  100  is capable of being used in RF sampling receivers which operate at speeds of GSPS. The circuit  100  scales well with technology nodes and is capable of supporting high GSPS transfer rates in future technology nodes. 
       FIG. 6  is a graph which illustrates AND-gate delay and comparator delay generated by an AND gate and a delay comparator, respectively, in a stage of a backend ADC, according to an example embodiment. The graph is explained in connection with the backend ADC  124  illustrated in  FIG. 3 . The graph includes an X-axis (T_IN) and a Y-axis (Output Delay). The AND-gate (for example the AND gates  306   a ,  306   b  to  306   n ) delay and the comparator (for example the delay comparators  308   a ,  308   b  to  308   n ) delay are functions of input-signal delay, according to an example embodiment. The input-signal delay is delay between the signals received by the AND gate or by the delay comparator. As illustrated, the AND-gate delay  602  contributed by a respective AND gate is linearly related to the absolute value of an input-signal delay T_IN, where the input-signal delay T_IN is the difference in timing between signals AN and BN input into the respective AND gate, where N is an integer and N is equal to 1 for the first stage  310   a  and N is equal to 2 for second stage  310   b . In the illustrated configuration, the relationship of the AND gate delay  602  to the input-signal delay T_IN is linear regardless of whether AN or BN leads or follows. 
     Signals AN and BN are also applied to the inputs of the delay comparators, causing the delay comparators to generate corresponding signal BN′. For each one of the delay comparators (for example  308   a  and  308   b ), the timing of the leading edge of signal BN′ tracks the timing of the leading edge of the earlier-arriving of signals AN and BN. In particular, for each one of the delay comparators, the timing of the leading edge of signal BN′ is equal to (1) the timing of the leading edge of the earlier-arriving of signals AN and BN plus (2) a comparator delay  604  that is logarithmically inversely related to the absolute value of the input-signal delay T_IN (in other words, comparator delay is greater for input values that are more similar, and if the difference between the two inputs to the comparator is greater, the comparator delay is less). 
       FIG. 7  is a graph which illustrates output-signal delay of a stage as a function of the input-signal delay of the stage of a backend ADC, according to an example embodiment. Subtracting the AND gate-delay  602  from the comparator delay  604  yields the output-signal delay T_OUT for any given single-bit stage for example, the first stage  310   a . When the absolute value of the input-signal delay T_IN is less than a threshold delay T_THRES, then the output-signal delay T_OUT is a positive value (meaning that the leading edge of signal BN′ generated by the respective delay comparator lags the leading edge of signal AN′ generated by the respective AND gate. On the other hand, when the absolute value of the input-signal delay T_IN is greater than the threshold delay T_THRES, then the output-signal delay T_OUT is a negative value (meaning that the leading edge of signal AN′ leads the leading edge of corresponding signal BN′). The positive or negative character of the output-signal delay T_OUT is reported to the calibration engine  102 . 
     In operation, the delay comparator  308   a  issues a first sign signal (“1” or “0”) to the calibration engine  102 . The first sign signal (an example of a digital signal in accordance with this disclosure) is based on which one of the leading edges of signals A 1  and B 1  is first received by the delay comparator  308   a , such that the first sign signal reflects the order of the leading edges of signals A 1  and B 1  applied to the delay comparator  308   a . The AND gate  306   a  and the delay comparator  308   a  generate signals A 1 ′ and B 1 ′ which are applied to the second stage  310   b . The delay comparator  308   b  outputs a second sign signal (“1” or “0”) to the calibration engine  102 . The second sign signal is based on which one of the leading edges of the signals A 2  and B 2  is first received by the delay comparator  308   b , such that the second sign signal reflects the order of the leading edges of the signals A 2  and B 2  applied to the delay comparator  308   b.    
     Since the delay between signals A 1  and B 1  can be predicted as a function of the input voltage Vin  110 , and vice versa, and since the delay between the signals AN′ and BN′ output by a successive stage can be predicted as a function of the signals AN and BN received from the preceding stage, and vice versa, the sign signals output by the delay comparators of the cascade of stages can be predicted as a function of the input voltage Vin  110 , and vice versa. Therefore, a code made up of the sign signals may be reliably compared to a predetermined correlation to determine an approximation of the input voltage Vin  110 . In operation, the timings of the signals A 1  and B 1  are functionally (that is, predictably) related to the timings of the signals OUT_P and OUT_M whose timing is correlated to the input voltage Vin  110 , as discussed above. The timings of the signals A 1 ′ and B 1 ′ are functionally (that is, predictably) related to the timings of the signals A 1  and B 1 , and so on. Thus, since the timings of the signals OUT_P and OUT_M are functionally (that is, predictably) related to the input voltage Vin  110 , the timings of the signals on lines A 1 , B 1 , A 1 ′, B 1 ′, and so on, which determine the sign signals used to make up the output code, are also functionally related to the input voltage Vin  110 . 
       FIGS. 8A and 8B  are graphs which illustrates output-signal delay of different stages as a function of the input-signal delay of a backend ADC, according to an example embodiment. As discussed in connection with  FIG. 7 , subtracting the AND gate-delay  602  from the comparator delay  604  yields the output-signal delay T_OUT for any given single-bit stage for example, the first stage  310   a . When the absolute value of the input-signal delay T_IN is less than a threshold delay T_THRES, then the output-signal delay T_OUT is a positive value (meaning that the leading edge of signal BN′ generated by the respective delay comparator lags the leading edge of signal AN′ generated by the respective AND gate. On the other hand, when the absolute value of the input-signal delay T_IN is greater than the threshold delay T_THRES, then the output-signal delay T_OUT is a negative value (meaning that the leading edge of signal AN′ leads the leading edge of corresponding signal BN′). 
     Graph  802   a  represents an output signal delay for a first and a second stage in a traditional circuit. Graph  802   b  represents an output signal delay for the first stage  310   a  and the second stage  310   b  of circuit  100 . Graph  804   a  represents an output signal delay for a third and a fourth stage in a traditional circuit. Graph  804   b  represents an output signal delay for the third stage  310   c  and a fourth stage  310   d  of circuit  100 . Thus, from graph  802   a , gain profile of second stage is asymmetric, higher gain at toggling point and lower gain at extreme points. In addition, if correction is performed to correct the asymmetric nature of second stage, it results in error during calibration of subsequent stages. Also, calibration of second stage at toggling points of third stage results in error during calibration of subsequent stages. However, circuit  100  is able to address all these challenges. As represented by graph  802   b , the circuit  100  provides a symmetric gain profile for second stage  310   b . The circuit  100  uses a delay calibration mode which ensures delay value of each stage in the backend ADC  124  is calibrated. Similarly, graph  804   b  illustrates that the circuit  100  provides a symmetric gain profile for the third stage  310   c  and the fourth stage  310   d.    
     The calibration engine  102  measures an error count of each stage of the multiple stages in the backend ADC  124  across multiple cycles, and also stores a delay value of each stage of the backend ADC  124 . The error count is an absolute difference in a number of ones and zeroes in the digital code generated by a stage. The delay value (or calibrated delay value) for each stage of the multiple stages in the backend ADC  124  are used subsequently during other modes of operation of the circuit  100 . These delay values (or calibrated delay values) of each stage distribute asymmetricity across the range of input codes making gain uniform. Thus, as illustrated by graphs  802   b  and  804   b , the delay-calibration mode ensures that the delay value of each stage is calibrated optimally for the circuit  100  to operate as a high-speed ADC. The calibration mode ensures better standard deviation resulting in more uniform gain across regions. Also, circuit  100  provides for averaging in each stage during delay calibration which makes it more robust to noise. 
       FIG. 9  is a block diagram of an example device  900  in which several aspects of example embodiments can be implemented. The device  900  is, or in incorporated into or is part of, a server farm, a vehicle, a communication device, a transceiver, a personal computer, a gaming platform, a computing device, or any other type of electronic system. The device  900  may include one or more conventional components that are not described herein for simplicity of the description. 
     In one example, the device  900  includes a processor  902  and a memory  906 . The processor  902  can be a CISC-type (complex instruction set computer) CPU, RISC-type CPU (reduced instruction set computer), a digital signal processor (DSP), a processor, a CPLD (complex programmable logic device) or an FPGA (field programmable gate array). 
     The memory  906  (which can be memory such as RAM, flash memory, or disk storage) stores one or more software applications (e.g., embedded applications) that, when executed by the processor  902 , performs any suitable function associated with the device  900 . 
     The processor  902  may include memory and logic, which store information frequently accessed from the memory  906 . The device  900  includes a circuit  910 . In one example, the processor  902  may be placed on the same printed circuit board (PCB) or card as the circuit  910 . In another example, the processor  902  is external to the device  900 . The circuit  910  can function as an analog to digital converter. 
     The circuit  910  is similar, in connection and operation, to the circuit  100  of  FIG. 1 . The circuit  910  includes a calibration engine (for example, calibration engine  102 ), a digital to analog converter (DAC)(e.g. DAC  104 ), a multiplexer (e.g. multiplexer M  112 ), a voltage to delay (VD) block (e.g. VD block  106 ), a backend analog to digital converter (ADC) (e.g. backend ADC  124 ) and a storage circuit (e.g. storage circuit  108 ). The VD block includes a preamplifier array (e.g. preamplifier array  116 ) and a delay multiplexer DM (e.g. delay multiplexer DM  120 ). The multiplexer receives an input voltage Vin. The preamplifier array includes multiple preamplifiers (e.g. as illustrated in  FIG. 2 ). 
     The VD block perform a voltage-to-delay function. The backend ADC perform a delay-to-digital function. Similar to the description above, the circuit  910  operates in a delay-calibration mode, a memory-calibration mode and a mission mode. 
     The term “couple” is used throughout. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal provided by device A. 
     A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or re-configurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof. 
     As used herein, the terms “terminal”, “node”, “interconnection”, “pin” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component. 
     A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party. 
     While the use of particular transistors are described herein, other transistors (or equivalent devices) may be used instead. For example, a p-type metal-oxide-silicon FET (“MOSFET”) may be used in place of an n-type MOSFET with little or no changes to the circuit. Furthermore, other types of transistors may be used (such as bipolar junction transistors (BJTs)). 
     Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor. 
     Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means +/−10 percent of the stated value. 
     Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.