Patent Publication Number: US-9429605-B2

Title: Techniques for determining a resistance value

Description:
REFERENCE TO RELATED APPLICATION 
     This application is a non-provisional of U.S. Provisional Application No. 61/823,134 filed on May 14, 2013. 
     BACKGROUND 
     Many sensors provide information in the form of a time-varying resistance. For example, a thermistor is a type of resistor whose resistance varies significantly with temperature. Thermistors are widely used as inrush current limiters, temperature sensors, self-resetting overcurrent protectors, and self-regulating heating elements. A resistance temperature detector (RTD) is another example of a sensor that provides information in the form of a time-varying resistance. RTDs differ from thermistors in that the material used in a thermistor is generally a ceramic or polymer, while an RTD uses pure metals. 
     Moreover, sensors that provide a time-varying resistance are not limited to those where resistance varies with temperature; and other ambient environmental conditions can also be measured by sensors that use a time-varying resistance. For example, pressure can be measured by pressure transducers, such as in the form of piezoelectric sensors. The piezoresistive effect describes change in the electrical resistivity of a semiconductor when mechanical stress is applied. 
     Whatever the exact condition being measured, it is important to accurately measure the resistance value of resistors in order to accurately determine the corresponding ambient environmental condition. The present disclosure provides improved techniques for determining such resistance values. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows an embodiment of a system for determining a resistance value. 
         FIG. 2  shows another embodiment of a system for determining a resistance value. 
         FIG. 3  shows a table of sample values that can be used to tune currents for first and second conditioning circuits to limit or avoid saturation of an ADC element. 
         FIG. 4  shows another embodiment of a system for determining a resistance value. 
     
    
    
     DETAILED DESCRIPTION 
     One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout. The drawings are not necessarily drawn to scale. 
       FIG. 1  illustrates a system  100  to measure an ambient environmental condition by using a sensor with a time-varying resistance. In this system, a sensing resistor  102  (e.g., off-chip thermistor) has a resistance value that changes in time to reflect a time-varying, ambient environmental condition near the sensing resistor  102 . For example, the resistance could represent an ambient temperature condition, an ambient pressure condition, an ambient optical condition, an ambient ionization condition, or some other ambient environmental condition. Note that although the sensing resistor  102  is illustrated as being off-chip in system  100 , sensing resistor  102  could also be arranged on-chip on other embodiments. 
     To accurately determine the resistance of sensing resistor  102 , an integrated circuit (IC)  104  is coupled to the sensing resistor  102 . The IC  104  includes first and second conditioning circuits  106 ,  108 . The first and second conditioning circuits  106 ,  108  have first and second outputs, respectively, which are coupled to first and second inputs of an analog to digital conversion (ADC) element  110 . The first conditioning circuit  106  is coupled to the sensing resistor  102  and provides a first voltage V 1  to ADC element  110 , where a first voltage level of the first voltage V 1  is based on the resistance of the sensing resistor  102 . The second conditioning circuit  108  provides a second voltage V 2  to ADC element, where a second voltage level of the second voltage V 2  is based on a resistance of an on-chip reference resistor. The on-chip reference resistor is matched to the sensing resistor  102  and is calibrated to be independent of the ambient environmental condition to be measured. The ADC element  110  provides a multi-bit digital value, D[X], at its output  112 , based on differences between V 1  and V 2 . This multi-bit value, D[X], is indicative of the ambient environmental condition measured by the off-chip sensor  102  at a given time. 
     Notably, rather than being based solely on the first voltage V 1  derived from the resistance of sensing sensor  102 , the multi-bit digital value provided by ADC element  110  is based on a ratio of the first and second voltages (V 1  and V 2 ). This ratioing is useful because, while the sensing resistor  102  has a resistance that changes in time to reflect corresponding changes in the ambient environmental condition, the on-chip reference resistor in second conditioning circuit  108  is calibrated such that the second voltage V 2  is a substantially fixed reference voltage that is independent of the ambient environmental condition which the sensing resistor  102  is to measure. Thus, by evaluating differences in resistance between the sensing resistor  102  and on-chip resistor, the IC  104  can accurately determine the ambient environmental condition. 
     Using the ratio between V 1  and V 2  (or equivalently between currents I 1  and I 2  from first and second conditioning circuits  106 ,  108 ) is efficient because it provides protection against process variation. If this ratioing technique were not used (e.g., if ADC measurements were made solely on V 1  for example), process variation could cause voltage (or current) readings to be different over different manufactured ICs, and this difference could cause inaccuracies in determining the resistance of sensing resistors  102  read by different ICs. 
     To further improve the accuracy with which the measured ambient environmental condition is determined, a feedback path  114 , which includes a logic circuit  116 , is included on the IC  104 . By making use of the feedback path  114 , the logic circuit  116  selectively adjusts the currents provided to the sensing resistor  102  and on-chip resistor based on the multi-bit digital value D[X} on ADC output  112 . By tuning these currents, the logic circuit  116  can help to ensure that a continually reasonable current level is provided through the sensing resistor  102  as it changes its resistance over temperature. Thus, for example, as temperature decreases (causing resistance of sensing resistor  102  to increase), the logic circuit  116  can increase the current through sensing resistor  102  to ensure the currently is large enough to provide accurate sensing of the increased sensing resistance. Further, the logic circuit  116  can also selectively adjust the first voltage V 1  and/or second voltage V 2  based on the multi-bit digital value D[X] on ADC output  112 . By tuning V 1  and/or V 2 , the logic circuit  102  can keep the voltage within a desired operating range of the ADC element  110 , to help to limit or avoid saturation of the ADC element  110 , and thereby further improve accuracy with which the resistance of sensing resistor  102  is determined. 
       FIG. 2  illustrates a more detailed system  200  which includes first and second conditioning circuits ( 202 ,  204 ), ADC element  206 , and logic circuit  208 . The logic circuit  208  is arranged on a feedback path  210  between a multi-bit digital output  212  and the first and second conditioning circuits ( 202 ,  204 ). A negative temperature coefficient (NTC) resistor  214  can be arranged off-chip, and a reference resistor  216  can be arranged on-chip with the other illustrated components. 
     The NTC resistor  214  is made of a material whose electrical resistivity is inversely proportional with temperature, typically in a defined temperature range. Thus, by measuring the electrical resistivity of the NTC resistor  214 , and comparing the measured resistivity to some expected electrical resistivity curve for the material of the NTC resistor, the system  200  can determine the ambient temperature. 
     For the first conditioning circuit  202 , NTC resistor  214  is included in a first current mirror  218  inside of which the voltages and currents are settled to values dependent of the resistance value of NTC resistor  214  and other physical constants. The current from one leg of the first current mirror (e.g., current I 1  on first current leg or current I 2  on second current leg) is mirrored as output current (I NTC ) and converted into a voltage (V NTC ), which is inversely proportional to the resistance value of the NTC resistor  214 . 
     Similarly, for the second conditioning circuit  204 , the reference resistor  216  is included in a second current mirror  220  in a similar manner. The current from one leg of the second current mirror (e.g., current I 1 ′ on third current leg or current I 2 ′ on fourth current leg) is mirrored as output current (I REF ) and converted into a voltage (V REF ). The reference resistor  216  is calibrated during a chip fabrication process so the reference current I ref  and reference voltages V ref  are substantially independent of changes in the ambient environmental condition measured by NTC resistor  214 . For example, if the NTC resistor  216  is to measure temperature, the system  200  can include a separate on-chip temperature sensor to sense an on-chip temperature during operation, and to tune current through the reference resistor  216  to keep I ref  (and V ref ) substantially constant over an operating temperature range of the system. To this end, a memory element in the system (not shown) can store a look-up table of calibration values, and tune current levels through the second current mirror  220  based on measured temperature to keep I ref  (and V ref ) substantially constant over the operating temperature range. 
     By observing a current or voltage (e.g., V NTC ) from the first conditioning circuit  202  and comparing it to a current or voltage (e.g., V Ref ) from the second conditioning circuit  204 , the ADC element  206  can provide a multi-bit output, D[X], whose digital value corresponds to the ambient environmental condition (e.g., temperature) measured by the NTC resistor  214 . By using a ratio of V NTC  and V REF ,  FIG. 2 &#39;s system provides a significant advantage in process variation independence. 
     More particularly, the output currents I out  (i.e., I ntc  and I ref  in  FIG. 2 ) can be calculated as follows: 
               I   out     =       1   R     ⁢     kt   q     ⁢   ln   ⁢           ⁢     (     N   ·   M     )             
where k is Boltzmann&#39;s constant, T is the absolute temperature of the IC, q is the elementary charge, R is the resistance value of NTC or reference resistor, M is a bipolar area multiplicity factor and N is a pmos current mirror multiplicity factor within the first or second conditioning circuits  202 ,  204 . In practical implementations, M and N can be realized for each of the first and second conditioning circuits  202 ,  204  by arranging a first integer number, M, of bipolar transistors in parallel and arranging a second integer number, N, of pmos transistors in parallel within each of the first and second conditioning circuits  202 ,  204 .
 
     Furthermore, in order to have a linear dependency on the NTC resistance, the ratio of reference and NTC currents is evaluated by the ADC element as follows: 
                 I   ref       I   NTC       =             V   T       R   REF       ⁢   ln   ⁢           ⁢     (       M   REF     ·     N   REF       )             V   T       R   NTC       ⁢   ln   ⁢           ⁢     (       M   NTC     ·     N   NTC       )         =       R   NTC       R   REF               
where V T =kT/q.
 
     The output currents (I ref , I NTC ) from the first and second conditioning blocks are furthermore converted into voltages by first and second current to voltage converters ( 222 ,  224 , respectively) and used as inputs for the ADC element. 
               V   NTC     =       I   NTC     ·     R     I   ⁢           ⁢   2   ⁢           ⁢   V_NTC                   and               V   REF     =       I   REF     ·     R     I   ⁢           ⁢   2   ⁢   V_REF                       V   NTC     =         R   ref     ·       I   ref       I   NTC         =     Rgain   ·   Rref   ·       V   ref       V   NTC                 
where R gain  is the ratio of the current to voltage conversion resistors:
 
     
       
         
           
             Rgain 
             = 
             
               
                 R 
                 
                   I 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                   ⁢ 
                   V_ntc 
                 
               
               
                 R 
                 
                   I 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                   ⁢ 
                   V_ref 
                 
               
             
           
         
       
     
     For the ADC element  206  to consistently operate in its most linear region, the logic circuit  208  evaluates the multi-bit digital value D[X] to determine if the multi-bit digital value falls within a plurality of predetermined resistance ranges. The logic circuit  208  can induce different electrical characteristics for each of the first and second conditioning circuits  202 ,  204  for each range, wherein the selected electrical characteristics for the first and second conditioning circuits are based on which predetermined resistance range the multi-bit digital value falls into at a given time. 
     For example, to keep an appropriate current passing through R NTC , Range_Select 1  and Range_Select 2  in  FIG. 2  act as control signals to tune the current along the current legs of the first and second current mirrors  218 ,  220  through R NTC , R REF . This can be achieved by Range_Select 1  and Range_Select 2  enabling different numbers of bipolar and/or pmos transistors in the current mirrors based on the multi-bit digital value to achieve different M factors and/or N factors to “tune” I ntc  and I ref . Further, Range_Select 1  and Range_Select 2  can also change the gains or resistances of first and second current to voltage elements  224 ,  226 , thereby tuning VNTC and VREF; to limit saturation of ADC element  206 . 
     A description of one example of range separation and limits can be found in the table illustrated in  FIG. 3 . To better explain how  FIG. 2 &#39;s system  200  operates in light of  FIG. 3 &#39;s table, an example is now discussed. This example shows five discrete ranges of operation which help limit ADC saturation, compared to examples where only one range is used. For simplicity, this example only illustrates changes in the N multiplicity factors (e.g., number of PMOS transistors used to provide current for the first and second conditioning circuits), and assumes the M multiplicity factors are constant (e.g., number of BJTs providing current is fixed for the first and second conditioning circuits  202 ,  204 ). However, it will be appreciated that other embodiments could tune the M multiplicity factors and leave the N multiplicity factors fixed, or could change the M-multiplicity factors as well as the N-multiplicity factors. Further, the present disclosure is not limited to the use of five discrete ranges, but any number of discrete ranges can be used. 
     Consider that at a first time in this example, the ambient temperature near the NTC resistor  214  is 100° C. In looking at the second line ( 302 ) of  FIG. 3 &#39;s table, we can see that the resistance of the NTC resistor  214  is relatively low at this temperature (between 215 and 1.3 k). Hence, the ADC element  206  will output a multi-bit value, D[X], which can be a 12-bit word that ranges from 0000_0000_0000 to 1111_1111_1111 over this second resistance range and which reflects the measured NTC value, and the logic element  208  will set the N multiplicity factors N NTC  and N REF  values to 0.20 and 0.20, respectively, as seen in  FIG. 3 &#39;s table. 
     If the ambient temperature decreases but remains between 55.82° C. and 117.70° C., the resistance of the NTC resistor  214  will increase and the ADC element  206  will correspondingly update the multi-bit value, D[X], to reflect this increased NTC resistance value. So long as the multi-bit value, D[X], indicates that the NTC resistance value remains within a single one of the five discrete ranges, the logic circuit  208  keeps the N-multiplicity factors unchanged for the first and second conditioning circuits  202 ,  204 . Thus, if the ambient temperature drops to 56° C., the logic circuit  208  will still maintain the N NTC  and N REF  values at 0.20 and 0.20, respectively. 
     However, when the ambient temperature changes over to the next discrete range as evidenced by the multi-bit digital value D[X], the logic circuit  208  then induces a change in the N-multiplicity factors to limit saturation of the ADC element  206 . Essentially, to keep the voltage V NTC  within desired operating region of ADC element  206 , the gain or resistance of current to voltage converters  224 ,  226  can be changed to re-zero the present V NTC  at the baseline operating voltage and divide the next discrete range into 2^12 discrete resistance values (i.e., digital output values of 0000_0000_0000 to 1111_1111_1111 over the next discrete resistance range). For example, if the ambient temperature continues to fall to 50° C., the resistance of NTC resistor  214  will increase to about 1.3 kOhm, as can be seen from the third line ( 304 ) of  FIG. 3 &#39;s table. This will correspondingly change the ratio between V NTC  and V REF , and the ADC element  206  will correspondingly update D[X] to reflect the increased NTC resistance (again, over a full range of digital ADC output values for this third range). Upon seeing the switch to the third discrete range, the logic circuit  208  changes the N NTC  and N REF  values to 0.8 and 0.8, respectively, as can be seen in  FIG. 3 . This increases the currents I NTC , I REF  so they stay within regulated levels. 
     If the ambient temperature decreases further, the resistance of the NTC resistor  214  will further increase and the ADC element  206  will correspondingly update the multi-bit value to reflect this further increased NTC resistance value. Thus, when the ambient temperature changes over to the next, e.g., fourth, discrete range as evidenced by the multi-bit digital value, the logic circuit  208  then induces another change in the N-multiplicity factors to keep current through RNTC at reasonable levels. For example, if the ambient temperature continues to fall to 0° C. (within the fourth line  306  of  FIG. 3 &#39;s table), the resistance of NTC resistor will increase to more than 20 kOhm. Upon seeing the D[X] value is approaching the fourth discrete range, the logic circuit  208  changes the N NTC  and N REF  values to 2.00 and 0.8, respectively, and changes the gains/resistances of the current to voltage converters  224 ,  226  to re-zero the present V NTC  at the baseline operating voltage and divide the fourth discrete range into 2^12 discrete resistance values (i.e., digital output values of 0000_0000_0000 to 1111_1111_1111 over the fourth discrete resistance range). 
     Thus, the logical circuit  208  provides a control signal e.g, Range_Select_ 1  and Range_Select_ 2 , to selectively enable different numbers of transistors within first and second current mirrors  218 ,  220  for different corresponding multi-bit digital values. For a first multi-bit digital value, the first and second paths each have a first number of transistors enabled (e.g, Range  2 : N NTC =N ref =0.20), and for a second different multi-bit digital value the first and second paths have a third number and fourth number of transistors being enabled (Range  3  or Range  4 ). The transition from the second range to the third range illustrates an example where the third and fourth numbers are the same (i.e., 0.80 and 0.80 for N NTC  and N REF ), but are each different from the first number. Thus, the transition from the third range to the fourth range illustrates an example where a third number is the same as a first number (i.e., both are 0.80), but different from the fourth number (i.e., 2.0). 
     Similarly, the control signal, e.g., Range_Select 1  and Range_Select 2  also changes the resistance or gain of the current to voltage converters  224 ,  226  to keep VNTC within the desired operating input range of the ADC element  206 . For example, as shown by numeral  250  in  FIG. 2 , the gain or resistance of current to voltage converters  224 ,  226  can be changed by changing a resistance value through which the reference or NTC current passes. In the circuit  250 , R 1 , R 2 , and RN can each have a different value, and the Range_Select control signal can control switching element to control which resistor I Ref  (or I NTC , not illustrated) passes. 
       FIG. 4  shows another embodiment of a system  400  for determining a resistance, such as a resistance of a NTC sensor  402 . Like the previous embodiments, this embodiment can be implemented as an IC  404 , wherein a pin of the IC is coupled to one terminal of NTC resistor  402  and the other terminal of the NTC resistor is coupled to ground. The system  400  can also be implemented as stand-alone components, for example, arranged on a breadboard. 
     The system includes amplifiers A 1 , A 2 , and A 3 , and reference resistors RRef. Amplifier A 1  establishes a sensed current value, INTO, representing the resistance value of RNTC, and Amplifier A 2  establishes a reference current value, IREF. These currents are converted to voltages VNTC and Vref, and are supplied to inputs of amplifier A 3 . Amplifier A 3  then provides an output whose level is indicative of a difference or ratio between Vref, and VNTC. Because Vref is calibrated to be largely independent of temperature, this difference or ratio between Vref and VNTC is indicative of the change in resistance of RNTC due to temperature change. ADC element then converts this voltage from A 3  to a multi-bit digital value, which is indicative of the resistance of RNTC. 
     More particularly, amplifier A 1  keeps sources, gates and drains of MP 1 , MP 2  at the same potential, such that the current through diode D 1  equals the current through the external resistor NTC. In the same way, amplifier A 2 , transistors MP 3 , MP 4 , MN 2 , resistor Rref, and diode D 2  generate a reference current through D 2 . Amplifier A 3  has as inputs the voltages on the diodes D 1  and D 2  and its output controls the gates of the PMOS transistors (MP 1 -MP 4 ) used to mirror the reference current and the NTC current. By setting the value of the resistor Rref the current limit through the NTC is settled, for example to a current value where self heating effects are less than a threshold value. When the current value exceeds this threshold value (i.e., when self heating effects become significant), a warning signal can be generated. The correct reading of the NTC is done as long as this limitation doesn&#39;t appear. 
     It will be appreciated that the embodiments illustrated and described above are but a few examples contemplated as falling within the scope of the present disclosure. For example, although the transistors in  FIG. 2  have been shown as MOS-type devices or bipolar junction transistors (BJTs), other types of transistors could also be used in place of the illustrated transistors. For example, BJTs could be substituted for the MOS-type devices, or vice versa, and other type of transistors such as JFETs, HEMTs, or FinFETs, for example could also be used. In addition, although the illustrated circuit examples show p-type devices and/or n-type devices, for example, it will be appreciated that the polarities of these devices can be switched in other embodiments along with a corresponding change in applied biases. Other combinations are also contemplated as falling within the scope of this disclosure. 
     Thus, some embodiments disclosed herein relate to an integrated circuit (IC) for determining a time-variant resistance of a sensing resistor. A resistance of the sensing resistor at a given time reflects an ambient environmental condition near the sensing resistor at that time. The IC includes a first conditioning circuit to provide a first voltage based on the resistance of the sensing resistor, and a second conditioning circuit to provide a second voltage based on a resistance of an on-chip reference resistor. An ADC element provides a multi-bit digital value based on a ratio of the first and second voltages. The multi-bit digital value is indicative of the ambient environmental condition measured by the sensing resistor. A logic circuit selectively adjusts the first and second voltages based on the multi-bit digital value to limit or avoid saturation of the ADC element. 
     Other embodiments relate to an apparatus. The apparatus includes a sensor having a time-varying resistance, wherein a resistance of the sensor at a given time reflects an ambient environmental condition near the sensor at that time. A first circuit provides a first voltage based on the resistance of the sensor. A second circuit provides a second voltage which has a substantially fixed voltage level that is independent of changes in the ambient environmental condition. An ADC element provides a multi-bit digital value based on a ratio of the first and second voltages. The multi-bit digital value is indicative of the resistance of the sensor and a corresponding ambient environmental condition. A logic circuit selectively adjusts the first and second voltages independent of one another based on the multi-bit digital value. 
     It will be appreciated that identifiers such as “first” and “second” do not imply any type of ordering or placement with respect to other elements; but rather “first” and “second” and other similar identifiers are just generic identifiers. In addition, it will be appreciated that the term “electrically connected” includes direct and indirect connections. For example, if element “a” is electrically connected to element “b”, element “a” can be electrically connected directly to element “b” and/or element “a” can be electrically connected to element “b” through element “c”, so long as there is an operable electrical connection between elements “a” and “b”. 
     While the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.