Patent Publication Number: US-9889880-B2

Title: Motor control device, electric power steering device using same, and vehicle

Description:
TECHNICAL FIELD 
     The present invention relates to a motor control device that controls driving of a multi-phase electric motor, and to an electric power steering device and a vehicle that use the same. 
     BACKGROUND ART 
     It is desired that a motor control device controlling driving of an electric motor of an electric power steering device or an electric motor of an electric braking device mounted in a vehicle, a traveling electric motor of an electric vehicle or a hybrid vehicle, or the like can continue to drive the electric motor even when something abnormal occurs in a motor control system. 
     In order to meet the desire, an electric power steering device has been proposed that has a configuration in which along with a duplex inverter for supplying a motor driving current to a multi-phase electric motor, a power source relay is provided between a power source and each inverter, and a motor relay is provided between each inverter and a motor winding of each phase of the multi-phase electric motor (for example, see PTL 1). 
     When something abnormal occurs in switching means of one or more inverter units, the electric power steering device causes the power source relay and the motor relay to perform a blocking operation to block energization between the abnormal inverter and the power source and energization between the inverter and the multi-phase electric motor. 
     In addition, during normal control for assisting steering of a steering wheel, the electric power steering device causes the power source relay to block energization between the device and the power source, and monitors a voltage of a wire connecting the power source relay to the motor to check a short-circuit failure of the power source relay. 
     Additionally, the electric power steering device causes the motor relay to block energization between the device and the motor during the normal control for assisting the steering of the steering wheel, and monitors a voltage of a wire connecting the motor relay to the motor to check a short-circuit failure of the motor relay. 
     CITATION LIST 
     Patent Literature 
     PTL 1: JP 2013-79027 A 
     SUMMARY OF INVENTION 
     Technical Problems 
     Meanwhile, in the conventional example described in PTL 1 described above, the checking of the power source relay and the motor relay uses the voltages of the wire connecting the power source relay to the motor and the wire connecting the motor relay to the motor. Additionally, capacitors for power supply assistance and removal of noise (such as ripples) are provided on an inverter-side from a power source relay-side. 
     Accordingly, in the above conventional example, even when the power source relay is put into a blocked state during the normal control, charging voltages of the capacitors allow maintaining of the voltage of the wire connecting the power source relay to the motor. Thus, depending on the charge state of the capacitors, there is a problem in that it is difficult to detect a short-circuit failure of the power source relay by voltage monitoring. 
     Additionally, in the above conventional example, the checking of the motor relay uses the voltage of the wire connecting the motor relay to the motor. However, the voltage of the wire fluctuates in response to PWM driving of the inverter regardless of the presence or absence of a short-circuit failure. Thus, depending on the driving state of the inverter, there is a problem in that it is difficult to detect a short-circuit failure of the motor relay. 
     Accordingly, the present invention has been accomplished in view of the unsolved problems of the conventional example. It is an object of the present invention to provide a motor control device capable of more surely detecting a short-circuit failure of at least one of a motor current blocking unit and a power source blocking unit regardless of the driving state of a motor driving circuit and the like, an electric power steering device, and a vehicle that use the motor control device. 
     Solution to Problems 
     In order to achieve the object mentioned above, according to an aspect of the present invention, there is provided a motor control device comprising: a plurality of motor driving circuits configured to operate by receiving a power source supplied from a common power source system and supply multi-phase motor driving currents to multi-phase motor windings of a multi-phase electric motor; a control computing device configured to control driving of the plurality of motor driving circuits; a plurality of multi-phase motor current blocking units individually interposed between the plurality of motor driving circuits and the multi-phase motor windings and configured to individually block energization between the plurality of motor driving circuits and the multi-phase motor windings in blocking operation; a plurality of current detecting units configured to individually detect currents flowing to the plurality of motor driving circuits; and a first abnormality detecting unit configured to detect a short-circuit failure of the plurality of motor current blocking units on a basis of current values of the currents detected by the plurality of current detecting units. 
     The first abnormality detecting unit causes one or more motor current blocking units of the plurality of motor current blocking units to perform the blocking operation during energization between the plurality of motor driving circuits and the multi-phase electric motor, and, during the blocking operation, detects a short-circuit failure of the motor current blocking units caused to perform the blocking operation based on the current values of the currents detected by the plurality of current detecting units. 
     In addition, an aspect of an electric power steering device according to the present invention applies the above-described motor control device to a motor control device that includes an electric motor causing a steering mechanism to generate a steering assisting force. 
     Furthermore, an aspect of a vehicle according to the present invention includes the above-described motor control device. 
     Advantageous Effects of Invention 
     According to the present invention, the motor driving circuit for supplying a motor current to the multi-phase electric motor is multiplexed, and the motor current blocking units are individually interposed between each of the multiplexed motor driving circuits and the motor winding of each phase. In addition, during energization to the multi-phase electric motor, one or more of the plurality of motor current blocking units are caused to perform a blocking operation, and currents flowing to the plurality of motor driving circuits at that time are detected. Then, based on current values of the detected currents, a short-circuit failure of the one or more motor current blocking units caused to perform the blocking operation is detected. Thus, a short-circuit failure of the motor current blocking units can be more surely detected regardless of the driving states of the motor driving circuits. 
     In addition, the electric power steering device is configured by including the motor control device having the advantageous effect described above. Thus, even while the motor driving circuits are being driven, a short-circuit failure of the motor current blocking units can be more surely detected. Thus, before any more serious problem occurs, electrical block of one or more motor driving circuits in which a failure has been detected or a notification or the like of the occurrence of the short-circuit failure thereof can be performed. Accordingly, an electric power steering device having a relatively high reliability can be provided. 
     Furthermore, since the vehicle is configured by including the motor control device having the advantageous effect, a short-circuit failure of the motor current blocking units can be more surely detected even while the motor driving circuits are being driven. Thus, before any more serious problem occurs, electrical block of one or more motor driving circuits in which a failure has been detected or a notification or the like of the occurrence of the short-circuit failure thereof can be performed. Accordingly, a vehicle having a relatively high reliability can be provided. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is an entire structural view depicting an embodiment in which a motor control device of the present invention is applied to an electric power steering device mounted in a vehicle; 
         FIG. 2  is a sectional view depicting the configuration of a three-phase electric motor; 
         FIG. 3  is a schematic diagram depicting the structure of windings in the three-phase electric motor of  FIG. 2 ; 
         FIG. 4  is a circuit diagram depicting a specific configuration of the motor control device; 
         FIG. 5  is a block diagram depicting a specific configuration of a control computing device of  FIG. 4 ; 
         FIG. 6  is a characteristic curve chart depicting a relationship between steering torque and steering assisting current command value; 
         FIG. 7A  and  FIG. 7B  are block diagrams depicting a specific configuration of current detecting circuits of  FIG. 4 ; 
         FIG. 8  is a circuit diagram depicting a specific configuration of VR voltage detecting circuits of  FIG. 4 ; 
         FIG. 9  is a flowchart depicting one example of processing steps of short-circuit failure detection processing; 
         FIG. 10  is a flowchart depicting one example of processing steps of failure check processing by current comparison; 
         FIG. 11  is a diagram depicting one example of a power source-side current check blocking operation pattern; 
         FIG. 12A  to  FIG. 12C  are diagrams depicting other examples of the power source-side current check blocking operation pattern; 
         FIG. 13  is a flowchart depicting one example of processing steps of failure check processing by current comparison in power source-side current check blocking operation; 
         FIG. 14  is a flowchart depicting one example of processing steps of motor-side current check blocking operation processing; 
         FIG. 15  is a diagram depicting one example of a low-load blocking operation pattern; 
         FIG. 16A  to  FIG. 16E  are diagrams depicting other examples of the low-load blocking operation pattern; 
         FIG. 17  is a diagram depicting one example of a first high-speed blocking operation pattern; 
         FIG. 18  is a diagram depicting another example of the first high-speed blocking operation pattern; 
         FIG. 19  is a diagram depicting one example of a second high-speed blocking operation pattern; 
         FIG. 20A  to  FIG. 20C  are diagrams depicting other examples of the second high-speed blocking operation pattern; 
         FIG. 21  is a flowchart depicting one example of processing steps of failure check processing by current comparison in a low-load check mode; 
         FIG. 22  is a flowchart depicting one example of processing steps of failure check processing by current comparison in a first high-speed check mode and a second high-speed check mode; 
         FIG. 23  is a flowchart depicting one example of processing steps of failure check processing by voltage comparison; 
         FIG. 24  is a diagram depicting one example of a power source-side voltage check blocking operation pattern; 
         FIG. 25A  and  FIG. 25B  are diagrams depicting other examples of the power source-side voltage check blocking operation pattern; 
         FIG. 26  is a flowchart depicting one example of processing steps of failure check processing by voltage comparison in a power source-side voltage check blocking operation; 
         FIG. 27  is a diagram depicting one example of a motor-side voltage check blocking operation pattern; 
         FIG. 28A  and  FIG. 28B  are diagrams depicting other examples of the motor-side voltage check blocking operation pattern; 
         FIG. 29  is a flowchart depicting one example of processing steps of failure check processing by voltage comparison in a motor-side voltage check blocking operation; and 
         FIG. 30  is a circuit diagram depicting one example of an equivalent circuit including respective FETs of the same phase in first and second inverter circuits  42 A and  42 B and respective FETs of the same phase in first and second motor current blocking circuits  33 A and  33 B, where one of the FETs that is in an OFF-state is regarded as a resistance. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     (Configuration) 
     A vehicle  1  according to an embodiment of the present invention includes front wheels  2 FR and  2 FL serving as right and left steered wheels and rear wheels  2 RR and  2 RL, as depicted in  FIG. 1 . The front wheels  2 FR and  2 FL are steered by an electric power steering device  3 . 
     The electric power steering device  3  includes a steering wheel  11 , a steering shaft  12 , a steering torque sensor  13 , a first universal joint  14 , a lower shaft  15 , and a second universal joint  16 , as depicted in  FIG. 1 . 
     The electric power steering device  3  further includes a pinion shaft  17  and a steering gear  18 . 
     A steering force applied to the steering wheel  11  by a driver is transmitted to the steering shaft  12 . The steering shaft  12  includes an input shaft  12   a  and an output shaft  12   b . One end of the input shaft  12   a  is connected to the steering wheel  11  and the other end thereof is connected to one end of the output shaft  12   b  via the steering torque sensor  13 . 
     Then, the steering force transmitted to the output shaft  12   b  is transmitted to the lower shaft  15  via the first universal joint  14  and furthermore transmitted to the pinion shaft  17  via the second universal joint  16 . The steering force transmitted to the pinion shaft  17  is transmitted to a tie rod  19  via the steering gear  18  to steer the front wheels  2 FR and  2 FL as the steered wheels. Herein, the steering gear  18  is formed in a rack and pinion form having a pinion  18   a  connected to the pinion shaft  17  and a rack  18   b  engaged with the pinion  18   a . Accordingly, the steering gear  18  converts a rotational movement transmitted to the pinion  18   a  to a translatory movement in a vehicle width direction at the rack  18   b.    
     A steering assisting mechanism  20  that transmits a steering assisting force to the output shaft  12   b  is connected to the output shaft  12   b  of the steering shaft  12 . The steering assisting mechanism  20  includes a deceleration gear  21  connected to the output shaft  12   b  formed by, for example, a worm gear mechanism, and a three-phase electric motor  22  as a multi-phase electric motor formed by, for example, a three-phase brushless motor, which is connected to the deceleration gear  21  and generates the steering assisting force. 
     The steering torque sensor  13  detects a steering torque applied to the steering wheel  11  and transmitted to the input shaft  12   a . The steering torque sensor  13  is configured to, for example, convert the steering torque into a twist angular displacement of an unillustrated torsion bar interposed between the input shaft  12   a  and the output shaft  12   b  and convert the twist angular displacement into a resistance change or a magnetic change to detect. 
     In addition, as depicted in  FIG. 2 , the three-phase electric motor  22  has a configuration of a surface permanent magnet (SPM) motor that includes a stator  22 S having, for example, nine teeth T formed protrudingly inward on an inner peripheral surface of the stator to form slots SL and serving as magnetic poles and a rotor  22 R of a surface permanent magnet type with, for example, six poles that is rotatably arranged facing the teeth T in an inner peripheral side of the stator  22 S. 
     Then, multi-phase motor windings La, Lb, and Lc of A phase, B phase, and C phase forming three phases are wound on the slots SL of the stator  22 S. Each of the multi-phase motor windings La, Lb, and Lc has a configuration, as depicted in  FIG. 3 , in which, for example, three coil portions L 1 , L 2 , and L 3  are connected in parallel, and the coil portions L 1  to L 3  are wound into three layers on the slots SL. One ends of the multi-phase motor windings La, Lb, and Lc are connected to each other to be star-connected, and other ends thereof are connected to a motor control device  25  to individually supply an A-phase motor driving current Ia, a B-phase motor driving current Ib, and a C-phase motor driving current Ic. Hereinafter, current values of the A-phase motor driving current Ia, the B-phase motor driving current Ib, and the C-phase motor driving current Ic may be referred to as “A-phase motor driving current value Ia, B-phase motor driving current value Ib, and C-phase motor driving current value Ic”. In addition, the A-phase, B-phase, and C-phase motor driving current values Ia, Ib, and Ic may be referred to as “three-phase motor driving current values Ia, Ib, and Ic”, and the A-phase, B-phase, and C-phase motor driving currents Ia, Ib, and Ic may be referred to as “three-phase motor driving currents Ia, Ib, and Ic”. 
     Furthermore, as depicted in  FIG. 4 , the three-phase electric motor  22  includes a rotation position sensor  23   a , such as a resolver, that detects a rotation position of the motor. A detection value from the rotation position sensor  23   a  is supplied to a motor rotation angle detecting circuit  23 , and the motor rotation angle detecting circuit  23  detects a motor rotation angle θm. 
     A steering torque Ts detected by the steering torque sensor  13  and a vehicle speed Vs detected by a vehicle speed sensor  26  are input to the motor control device  25 , and also, the motor rotation angle θm output from the motor rotation angle detecting circuit  23  is input thereto. 
     In addition, a direct current is input to the motor control device  25  from a battery  27  as a direct current voltage source. 
     A specific configuration of the motor control device  25  is formed as depicted in  FIG. 4 . Specifically, the motor control device  25  includes a control computing device  31  that computes a motor voltage command value, first and second motor driving circuits  32 A and  32 B to which three-phase motor voltage command values V1* and V2* output from the control computing device  31  are individually input, and first and second motor current blocking circuits  33 A and  33 B interposed between output sides of the first and second motor driving circuits  32 A and  32 B and the multi-phase motor windings La to Lc of the three-phase electric motor  22 . 
     Additionally, as depicted in  FIG. 4 , the motor control device  25  includes motor voltage detecting circuits  40 A and  40 B provided between the first and second motor driving circuits  32 A and  32 B and the first and second motor current blocking circuits  33 A and  33 B. 
     Then, as depicted in  FIG. 4 , respective motor phase voltage detection values VA1, VB1, VC1, VA2, VB2, and VC2 detected by the motor voltage detecting circuits  40 A and  40 B are input to the control computing device  31 . 
     Furthermore, as depicted in  FIG. 4 , upstream-side current detection values IU1 and IU2 output from current detecting circuits  39 A 1  and  39 B 1  are input to the control computing device  31 . In addition, downstream-side current detection values IA1, IB1, and IC1 output from current detecting circuits  39 A 2  to  39 A 4  and downstream-side current detection values IA2, IB2, and IC2 output from current detecting circuits  39 B 2  to  39 B 4  are input to the control computing device  31 . 
     The steering torque Ts detected by the steering torque sensor  13  and the vehicle speed Vs detected by the vehicle speed sensor  26  depicted in  FIG. 1  are input to the control computing device  31 , although illustration thereof is omitted in  FIG. 4 . In addition, as depicted in  FIG. 4 , the motor rotation angel θm output from the motor rotation angle detecting circuit  23  is input to the control computing device  31 . 
     As depicted in  FIG. 5 , the control computing device  31  includes a steering assisting current command value computing unit  45  that calculates a steering assisting current command value I* and a compensation control computing unit  35  that performs compensation on the basis of a motor angular velocity we and a motor angular acceleration α input thereto on the steering assisting current command value I* calculated by the steering assisting current command value computing unit  45 . Furthermore, the control computing device  31  includes a d-q axis current command value computing unit  37  that calculates d-q axis current command values on the basis of the post-compensation steering assisting current command value I*′ compensated by the compensation control computing unit  35  and converts the calculated current command values to three-phase current command values. 
     The steering assisting current command value computing unit  45  refers to a steering assisting current command value calculation map depicted in  FIG. 6  on the basis of the steering torque Ts and the vehicle speed Vs to calculate a steering assisting current command value I* made of a current command value. The steering assisting current command value calculation map is formed by a characteristic curve chart indicated by a parabolic curve, whose horizontal axis represents steering torque Ts and whose vertical axis represents steering assisting current command value I*, as depicted in the drawing. 
     Then, the steering assisting current command value I* is calculated by referring to a current command value calculation curve depicted in  FIG. 6  previously set on the basis of the steering torque Ts and the vehicle speed Vs. 
     The compensation control computing unit  35  calculates, for example, a convergence compensation value for compensating for the convergence of a yaw rate on the basis of the motor angular velocity ωe and a torque compensation value for compensating for a value corresponding to a torque generated by inertia of the three-phase electric motor  22  on the basis of the motor angular acceleration α to prevent deterioration of inertial sensing or control responsiveness. In addition, the compensation control computing unit  35  estimates a self-aligning torque (SAT) and, on the basis of the estimated SAT, calculates a self-aligning torque compensation value for compensating for an assisting force of the three-phase electric motor  22 . Furthermore, the compensation control computing unit  35  calculates a command value compensation value Icom by adding together the calculated convergence compensation value, torque compensation value, and self-aligning torque compensation value. Then, the compensation control computing unit  35  adds the calculated command value compensation value Icom to the steering assisting current command value I* output from the steering assisting current command value computing unit  45  by an adder  36  to calculate a post-compensation steering assisting current command value I*′. The compensation control computing unit  35  outputs the post-compensation steering assisting current command value I*′ to the d-q axis current command value computing unit  37 . 
     The d-q axis current command value computing unit  37  includes a d-axis target current calculating unit  37   a , an induced voltage model calculating unit  37   b , a q-axis target current calculating unit  37   c , and a two-phase to three-phase converting unit  37   d.    
     The d-axis target current calculating unit  37   a  calculates a d-axis target current Id* on the basis of the post-compensation steering assisting current command value I*′ and the motor angular velocity ω. 
     The induced voltage model calculating unit  37   b  calculates a d-axis EMF component ed (θ) and a q-axis EMF component eq (θ) of a d-q axis induced voltage model EMF (Electro Magnetic Force) on the basis of a motor rotation angle θ and the motor angular velocity ω. 
     The q-axis target current calculating unit  37   c  calculates a q-axis target current Iq* on the basis of the d-axis EMF component ed (θ) and the q-axis EMF component eq (θ) output from the induced voltage model calculating unit  37   b , the d-axis target current Id* output from the d-axis target current calculating unit  37   a , the post-compensation steering assisting current command value I*′, and the motor angular velocity ω. 
     The two-phase to three-phase converting unit  37   d  coverts the d-axis target current Id* output from the d-axis target current calculating unit  37   a  and the q-axis target current Iq* output from the q-axis target current calculating unit  37   c  to three-phase current command values Ia*, Ib*, and Ic*. 
     In addition, the control computing device  31  includes a voltage command value computing unit  38  that calculates the motor voltage command values V1* and V2* for the first and second motor driving circuits  32 A and  32 B. 
     The voltage command value computing unit  38  calculates the motor voltage command values V1* and V2* on the basis of the A-phase current command value Ia*, the B-phase current command value Ib*, the C-phase current command value Ic*, and the downstream-side current detection values IA1 to IC1 and IA2 to IC2 detected by the current detecting circuits  39 A 2  to  39 A 4  and  39 B 2  to  39 B 4 . Specifically, the voltage command value computing unit  38  calculates the three-phase motor driving current values Ia, Ib, and Ic from the downstream-side current detection values IA1 to IC1 and IA2 to IC2 detected by the current detecting circuits  39 A 2  to  39 A 4  and  39 B 2  to  39 B 4  by computation including addition of the values. Then, the voltage command value computing unit  38  subtracts the three-phase motor driving current values Ia, Ib, and Ic from the A-phase current command value Ia*, the B-phase current command value Ib*, and the C-phase current command value Ic* to calculate current deviations ΔIa, ΔIb, and ΔIc. Furthermore, based on these current deviations ΔIa, ΔIb, and ΔIc, for example, PI control computation or PID control computation is performed to calculate the three-phase motor voltage command values V1* and V2* for the first and second motor driving circuits  32 A and  32 B. Then, the calculated three-phase motor voltage command values V1* and V2* are output to the first and second motor driving circuits  32 A and  32 B. Herein, the three-phase motor voltage command values V1* and V2* are output as the same value to each other in a normal state in which there is no abnormality detected by an abnormality detecting unit  31   a  that will be described later. In other words, the first and second motor driving circuits  32 A and  32 B are adapted to be usually responsible for 50[%] for each to share an amount of electric current necessary for steering assistance. 
     Additionally, the respective motor phase voltage detection values VA1, VB1, VC1, VA2, VB2, and VC2, the respective upstream-side current detection values IU1 and IU2, and the downstream-side current detection values IA1, IB1, IC1, IA2, IB2, and IC2 are input to the control computing device  31  via an A-to-D converting unit  31   c.    
     Then, the control computing device  31  includes the abnormality detecting unit  31   a  that detects abnormality (such as a failure) occurring in electric field effective transistors (hereinafter abbreviated as “FETs”) forming each component unit of the first and second motor driving circuits  32 A and  32 B on the basis of the respective input voltage detection values and current detection values. 
     Specifically, the abnormality detecting unit  31   a  detects an open-circuit failure and a short-circuit failure of FETs Q 1  to Q 6  as switching elements that form first and second inverter circuits  42 A and  42 B that will be described later. 
     Furthermore, the abnormality detecting unit  31   a  detects a short-circuit failure of current blocking FETs QC 1  to QC 2  and QD 1  to QD 2  that form first and second power source blocking circuits  44 A and  44 B that will be described later. 
     Still furthermore, the abnormality detecting unit  31   a  detects a short-circuit failure of current blocking FETs QA 1  to QA 3  and QB 1  to QB 3  that form the first and second motor current blocking circuits  33 A and  33 B that will be described later. 
     The abnormality detecting unit  31   a  outputs an abnormality detection signal SAa or SAb of a logical value “1” to the first or second motor driving circuit  32 A or  32 B in which an open-circuit failure or a short-circuit failure is occurring. On the other hand, when neither an open-circuit failure nor a short-circuit failure is not detected, the abnormality detecting unit  31   a  outputs abnormality detection signals SAa and SAb of a logical value “0” to the first and second motor driving circuit  32 A and  32 B. 
     Additionally, when detecting a short-circuit failure of the first and second power source blocking circuits  44 A and  44 B and the first and second motor current blocking circuits  33 A and  33 B, the abnormality detecting unit  31   a  performs a blocking operation for each FET of the first and second motor driving circuits  32 A and  32 B in a previously set blocking operation pattern. Specifically, the abnormality detecting unit  31   a  outputs blocking operation pattern signals SCa and SCb corresponding to various blocking operation patterns to first and second gate driving circuits  41 A and  41 B that will be described later. The blocking operation pattern signals SCa and SCb are, for example, 4-bit digital signals having a bit pattern corresponding to, for example, a previously set blocking operation pattern. 
     Additionally, the present embodiment is configured so that, when detecting a short-circuit failure of the first and second motor current blocking circuits  33 A and  33 B, an optional check mode can be set from among previously set three kinds of check modes by operation of an unillustrated operation unit by a user. 
     The abnormality detecting unit  31   a  detects a short-circuit failure of the first and second motor current blocking circuits  33 A and  33 B by a blocking operation pattern and a checking method corresponding to the set check mode. In addition, details of the check modes will be described later. 
     As depicted in  FIG. 4 , the first motor driving circuit  32 A includes the first gate driving circuit  41 A to which the three-phase motor voltage command value V1* output from the control computing device  31  is input to form a gate signal and the first inverter circuit  42 A to which the gate signal output from the first gate driving circuit  41 A is input. 
     Furthermore, the first motor driving circuit  32 A includes a VR voltage detecting circuit  34 A that is provided between a FET QC 1  and a FET QC 2  of the first power source blocking circuit  44 A that will be described later, and that detects a voltage of a connection line of the FETs QC 1  and QC 2 . 
     Still furthermore, the first motor driving circuit  32 A includes the current detecting circuit  39 A 1  that detects a direct current supplied to the first inverter circuit  42 A and the current detecting circuits  39 A 2  to  39 A 4  that detect direct currents flowing from lower arms of the first inverter circuit  42 A to ground. 
     In addition, the second motor driving circuit  32 B includes the second gate driving circuit  41 B to which the three-phase motor voltage command value V2* output from the control computing device  31  is input to form a gate signal and the second inverter circuit  42 B to which the gate signal output from the second gate driving circuit  41 B is input. 
     Furthermore, the second motor driving circuit  32 B includes a VR voltage detecting circuit  34 B that is provided between a FET QD 1  and a FET QD 2  of the second power source blocking circuit  44 B that will be described later, and that detects a voltage of a connection line of the FETs QD 1  and QD 2 . 
     Still furthermore, the second motor driving circuit  32 B includes the current detecting circuit  39 B 1  that detects a direct current supplied to the second inverter circuit  42 B and the current detecting circuits  39 B 2  to  39 B 4  that detect direct currents flowing from lower arms of the second inverter circuit  42 B to ground. 
     When the motor voltage command value V1* is input from the control computing device  31 , the first gate driving circuit  41 A forms six gate signals subjected to pulse width modulation (PWM) based on the motor voltage command value V1* and a triangular wave carrier signal Sc. Then, the gate signals are output to the first inverter circuit  42 A. 
     Additionally, when the motor voltage command value V2* is input from the control computing device  31 , the second gate driving circuit  41 B forms six gate signals subjected to pulse width modulation (PWM) based on the motor voltage command value V2* and the triangular wave carrier signal Sc. Then, the gate signals are output to the second inverter circuit  42 B. 
     In addition, the control computing device  31  may be configured to generate the six PWM gate signals in common and to input to the first and second inverter circuits  42 A and  42 B. 
     Additionally, when the abnormality detection signal SAa input from the control computing device  31  has the logical value “0” (normal), the first gate driving circuit  41 A outputs three high-level gate signals to the first motor current blocking circuit  33 A and simultaneously outputs two high-level gate signals to the first power source blocking circuit  44 A. Thereby, motor current is allowed to flow through the first inverter circuit  42 A, and also battery power is allowed to flow therethrough. 
     On the other hand, when the abnormality detection signal SAa input from the control computing device  31  has the logical value “1” (abnormal), the first gate driving circuit  41 A simultaneously outputs three low-level gate signals to the first motor current blocking circuit  33 A and simultaneously outputs two low-level gate signals to the first power source blocking circuit  44 A. In addition, the first gate driving circuit  41 A simultaneously outputs six low-level gate signals to the first inverter circuit  42 A to block motor current and also block battery power. 
     Similarly, when the abnormality detection signal SAb input from the control computing device  31  has the logical value “0” (normal), the second gate driving circuit  41 B outputs three high-level gate signals to the second motor current blocking circuit  33 B and simultaneously outputs two high-level gate signals to the second power source blocking circuit  44 B. Thereby, motor current is allowed to flow through the second inverter circuit  42 B, and also battery power is allowed to flow therethrough. 
     On the other hand, when the abnormality detection signal SAb input from the control computing device  31  has the logical value “1” (abnormal), the second gate driving circuit  41 B simultaneously outputs three low-level gate signals to the second motor current blocking circuit  33 B and outputs a low-level gate signal to the second power source blocking circuit  44 B. In addition, the second gate driving circuit  41 B simultaneously outputs six low-level gate signals to the second inverter circuit  42 B to block motor current and also block battery power. 
     Still furthermore, the first gate driving circuit  41 A simultaneously outputs two gate signals to the first power source blocking circuit  44 A, i.e., a low-level gate signal to a FET as a blocking object and a high-level gate signal to a FET as an energizing object on the basis of a blocking operation pattern indicated by the bit pattern of the blocking operation pattern signal SCa input from the control computing device  31 . In addition, the first gate driving circuit  41 A simultaneously outputs six gate signals to the respective FETs of the first inverter circuit  42 A, i.e., a low-level gate signal to a FET as a blocking object and a high-level gate signal to a FET as an energizing object. Furthermore, the first gate driving circuit  41 A simultaneously outputs three gate signals to the first motor current blocking circuit  33 A, i.e., a low-level gate signal to a FET as a blocking object and a high-level gate signal to a FET as an energizing object. 
     On the other hand, the second gate driving circuit  41 B simultaneously outputs two gate signals to the second power source blocking circuit  44 B, i.e., a low-level gate signal to a FET as a blocking object and a high-level gate signal to a FET as an energizing object on the basis of a blocking operation pattern indicated by the bit pattern of the blocking operation pattern signal SCb input from the control computing device  31 . In addition, the second gate driving circuit  41 B simultaneously outputs six gate signals to the respective FETs of the second inverter circuit  42 B, i.e., a low-level gate signal to a FET as a blocking object and a high-level gate signal to a FET as an energizing object. Furthermore, the second gate driving circuit  41 B simultaneously outputs three gate signals to the second motor current blocking circuit  33 B i.e., a low-level gate signal to a FET as a blocking object and a high-level gate signal to a FET as an energizing object. 
     The battery current of the battery  27  is input to the first inverter circuit  42 A via a noise filter  43 , the first power source blocking circuit  44 A, and the current detecting circuit  39 A 1 , and a smoothing electrolytic capacitor CA is connected to an input side thereof. The electrolytic capacitor CA includes a noise removing function and an electric power supply assisting function for the first inverter circuit  42 A. 
     The first inverter circuit  42 A includes six FETs Q 1  to Q 6  as switching elements and has a configuration in which three switching arms SWAa, SWAb, and SWAc each having each two of the FETs connected in series are connected in parallel. Then, the gate signals output from the first gate driving circuit  41 A are input to gates of the respective FETs Q 1  to Q 6 . The input allows the A-phase motor driving current Ia, the B-phase motor driving current Ib, and the C-phase motor driving current Ic to flow to the three-phase motor windings La, Lb, and Lc of the three-phase electric motor  22  from connection points between the FETs of the respective switching arms SWAa, SWAb, and SWAc via the first motor current blocking circuit  33 A. 
     Additionally, the battery current of the battery  27  is input to the second inverter circuit  42 B via the noise filter  43 , the second power source blocking circuit  44 B, and the current detecting circuit  39 B 1 , and a smoothing electrolytic capacitor CB is connected to an input side thereof. The electrolytic capacitor CB includes a noise removing function and an electric power supply assisting function for the second inverter circuit  42 B. 
     The second inverter circuit  42 B includes six FETs Q 1  to Q 6  as switching elements and has a configuration in which three switching arms SWBa, SWBb, and SWBc each having each two of the FETs connected in series are connected in parallel. Then, the gate signals output from the second gate driving circuit  41 B are input to gates of the respective FETs Q 1  to Q 6 . The input allows the A-phase motor driving current Ia, the B-phase motor driving current Ib, and the C-phase motor driving current Ic to flow to the three-phase motor windings La, Lb, and Lc of the three-phase electric motor  22  from connection points between the FETs of the respective switching arms SWBa, SWBb, and SWBc via the second motor current blocking circuit  33 B. 
     In addition, in the respective switching arms SWAa, SWAb, SWAc, SWBa, SWBb, and SWBc of the first and second inverter circuits  42 A and  42 B, the current detecting circuits  39 A 2  to  39 A 4  and  39 B 2  to  39 B 4  are connected to respective source sides of the FETs Q 2 , Q 4 , and Q 6  that serve as the lower arms. Ends of the current detecting circuits  39 A 2  to  39 A 4  and  39 B 2  to  39 B 4  opposing the sides thereof facing the FETs Q 2 , Q 4 , and Q 6  are grounded. Then, the current detecting circuits  39 A 2  to  39 A 4  and  39 B 2  to  39 B 4  detect downstream-side current detection signals (analog signals corresponding to the downstream-side current detection values IA1 to IC1 and IA2 to IC2). Hereinafter, the analog signals corresponding to the downstream-side current detection values IA1 to IC1 and IA2 to IC2 may be referred to as “downstream-side current detection signals IA1 to IC1 and IA2 to IC2”. 
     The current detecting circuits  39 A 1  and  39 B 1  include current detecting shunt resistances  51 A and  51 B interposed between power source-sides of the respective switching arms SWAa to SWAc and SWBa to SWBc and the first and second power source blocking circuits  44 A and  44 B, as depicted in  FIG. 7A . Each of the current detecting circuits  39 A 1  and  39 B 1  includes an operational amplifier  39   a  to which both-end voltages of the shunt resistances  51 A and  51 B are input via resistances R 2  and R 3  and a sample hold circuit  39   s  that is mainly formed by a noise filter and to which an output signal of the operational amplifier  39   a  is supplied, as depicted in  FIG. 7A . 
     Then, upstream-side current detection signals output from the sample hold circuit (analog signals corresponding to the upstream-side current detection signals IU1 and IU2) are supplied to the A-to-D converting unit  31   c  of the control computing device  31 . 
     Similarly, the current detecting circuits  39 A 2  to  39 A 4  include current detecting shunt resistances  52 A,  53 A, and  54 A interposed between grounded-sides of the respective switching arms SWAa to SWAc and the ground, as depicted in  FIG. 7B . Each of the current detecting circuits  39 A 2  to  39 A 4  includes an operational amplifier  39   a  to which respective both-end voltages of the shunt resistances  52 A,  53 A, and  54 A are input via resistances R 2  and R 3  and a sample hold circuit  39   s  that is mainly formed by a noise filter and to which an output signal of the operational amplifier  39   a  is supplied, as depicted in  FIG. 7B . 
     In addition, the current detecting circuits  39 B 2  to  39 B 4  include current detecting shunt resistances  52 B,  53 B, and  54 B interposed between grounded-sides of the respective switching arms SWBa to SWBc and the ground, as depicted in  FIG. 7B . Each of the current detecting circuits  39 B 2  to  39 B 4  includes an operational amplifier  39   a  to which respective both-end voltages of the shunt resistances  52 B,  53 B, and  54 B are input via resistances R 2  and R 3  and a sample hold circuit  39   s  that is mainly formed by a noise filter and to which an output signal of the operational amplifier  39   a  is supplied, as depicted in  FIG. 7B . 
     Then, the downstream-side current detection signals IA1 to IC1 and IA2 to IC2 output from the sample hold circuit  39   s  are supplied to the A-to-D converting unit  31   c  of the control computing device  31 . 
     Each of the VR voltage detecting circuits  34 A and  34 B includes a resistance R 6 , a resistance R 7 , and a capacitor C 1 , as depicted in  FIG. 8 . 
     In the VR voltage detecting circuit  34 A, one end of the resistance R 6  is connected to a connection line (a voltage monitoring line) of the FETs QC 1  and QC 2 , and an other end thereof is connected to one end of the resistance R 7  and one end of the capacitor C 1 . Furthermore, the one end of the resistance R 7  is connected to the one end of the capacitor C 1 , and an other end of the resistance R 7  and an other end of the capacitor C 1  are grounded. Then, when the FET QC 1  or QC 2  is being energized (in an ON state), current flows to the capacitor C 1  from the battery  27  or the electrolytic capacitor CA via the resistance R 6 , and a voltage VR 12  (≈battery voltage Vbat [V]) applied to both ends of the capacitor C 1  is supplied to the A-to-D converting unit  31   c  of the control computing device  31 . On the other hand, when the FET QC 1  or QC 2  is not being energized (in an OFF state), the resistance R 7  becomes a pulldown resistance and the voltage VR 12  becomes ground potential (≈0 [V]). 
     In addition, in the VR voltage detecting circuit  34 B, one end of the resistance R 6  is connected to a connection line (a voltage monitoring line) of the FETs QD 1  and QD 2 . Other connection configuration is the same as that of the VR voltage detecting circuit  34 A. Then, when the FET QD 1  or QD 2  is being energized (in an ON state), current flows to the capacitor C 1  from the battery  27  or the electrolytic capacitor CB via the resistance R 6 , and a voltage VR 22  (≈Vbat) applied to both ends of the capacitor C 1  is supplied to the A-to-D converting unit  31   c  of the control computing device  31 . On the other hand, when the FET QD 1  or QD 2  is not being energized (in an OFF state), the resistance R 7  becomes a pulldown resistance and the voltage VR 22  becomes ground potential (≈0 [V]). 
     In addition, respective element values of the resistances R 6  and R 7  and the capacitor Clare set to be those serving as time constants that can provide a filtering effect for eliminating voltage fluctuation of the monitoring line due to PWM driving. Additionally, the element value of the capacitor C 1  is a smaller value than those of the electrolytic capacitors CA and CB. 
     The first motor current blocking circuit  33 A includes three current blocking FETs QA 1 , QB 2 , and QC 3 . A source of the FET QA 1  is connected to a connection point of the FETs Q 1  and Q 2  of the switching arm SWAa of the first inverter circuit  42 A via the motor voltage detecting circuit  40 A, and a drain thereof is connected to the A-phase motor winding La of the three-phase electric motor  22 . Additionally, a source of the FET QA 2  is connected to a connection point of the FETs Q 3  and Q 4  of the switching arm SWAb of the first inverter circuit  42 A via the motor voltage detecting circuit  40 A, and a drain thereof is connected to the B-phase motor winding Lb of the three-phase electric motor  22 . Furthermore, a source of the FET QA 3  is connected to a connection point of the FETs Q 5  and Q 6  of the switching arm SWAc of the first inverter circuit  42 A via the motor voltage detecting circuit  40 A, and a drain thereof is connected to the C-phase motor winding Lc of the three-phase electric motor  22 . 
     In addition, the second motor current blocking circuit  33 B includes three current blocking FETs QB 1 , QB 2 , and QB 3 . A source of the FET QB 1  is connected to a connection point of the FETs Q 1  and Q 2  of the switching arm SWBa of the second inverter circuit  42 B via the motor voltage detecting circuit  40 B, and a drain thereof is connected to the A-phase motor winding La of the three-phase electric motor  22 . Additionally, a source of the FET QB 2  is connected to a connection point of the FETs Q 3  and Q 4  of the switching arm SWBb of the second inverter circuit  42 B via the motor voltage detecting circuit  40 B, and a drain thereof is connected to the B-phase motor winding Lb of the three-phase electric motor  22 . Furthermore, a source of the FET QB 3  is connected to a connection point of the FETs Q 5  and Q 6  of the switching arm SWBc of the second inverter circuit  42 B via the motor voltage detecting circuit  40 B, and a drain thereof is connected to the C-phase motor winding Lc of the three-phase electric motor  22 . 
     Then, each of the FETs QA 1  to QA 3  and QB 1  to QB 3  of the first and second motor current blocking circuits  33 A and  33 B is connected in the same direction in such a manner that an anode of a parasitic diode D faces sides where the first and second inverter circuits  42 A and  42 B are located. 
     The first power source blocking circuit  44 A has a serial circuit configuration in which sources of the two FETs QC 1  and QC 2  are connected to each other and parasitic diodes thereof are connected in mutually opposite directions. Then, a drain of the FET QC 1  is connected to an output side of the noise filter  43 , and a drain of the FET QC 2  is connected to a drain of each of the FETs Q 1 , Q 3 , and Q 5  of the first inverter circuit  42 A. 
     In addition, the second power source blocking circuit  44 B has a serial circuit configuration in which sources of the two FETs QD 1  and QD 2  are connected to each other and parasitic diodes thereof are connected in mutually opposite directions. Then, a drain of the FET QD 1  is connected to the output side of the noise filter  43 , and a drain of the FET QD 2  is connected to a drain of each of the FETs Q 1 , Q 3 , and Q 5  of the second inverter circuit  42 B. 
     (Abnormality Detecting Processing of FETs Q 1  to Q 6 ) 
     The abnormality detecting unit  31   a  performs abnormality detection of the FETs Q 1  to Q 6  in the following manner. 
     Specifically, in a case in which, for example, an open-circuit failure occurs in an A-phase upper arm (Q 1 ) of the first motor driving circuit  32 A, when the motor driving current value Ia of the arm having the open-circuit failure occurring therein becomes positive, the upstream-side current detection value IU1 of the first motor driving circuit  32 A decreases and the upstream-side current detection value IU2 of the second motor driving circuit  32 B increases so as to compensate for the decrease. 
     Then, by comparing the detected upstream-side current detection values IU1 and IU2, the first or second motor driving circuit  32 A or  32 B having the open-circuit failure occurring therein can be specified. The abnormality detecting unit  31   a  outputs the abnormality detection signal SAa or SAb of the logical value “1” to the first or second motor driving circuit  32 A or  32 B having the open-circuit failure occurring therein. 
     In addition, in the case in which an open-circuit failure occurs in any of the upper arms, no particular change occurs in a three-phase waveform of the motor driving current, so that steering assisting control can be continued. 
     In addition, in a case in which, for example, a short-circuit failure occurs in the A-phase upper arm of the first motor driving circuit  32 A, the upstream-side current detection value IU1 of the first motor driving circuit  32 A suddenly sharply increases, whereas the upstream-side current detection value IU2 of the second motor driving circuit  32 B slightly increases. This can lead to a determination that when an instantaneous value of the upstream-side current detection value IU1 becomes equal to or more than a predetermined threshold value, the upper arm has a short-circuit failure. The abnormality detecting unit  31   a  outputs the abnormality detection signal SAa or SAb of the logical value “1” to the first or second motor driving circuit  32 A or  32 B in which the short-circuit failure is occurring. 
     In this case, motor current is also significantly disturbed. However, by blocking the first motor current blocking circuit  33 A of the first motor driving circuit  32 A, motor driving current is supplied only from the second motor driving circuit  32 B to the respective phase motor windings La to Lc of the three-phase electric motor  22 , whereby the motor driving current recovers to a stable sine wave form. Accordingly, driving of the three-phase electric motor  22  can be continued. 
     At this time, as will be described later, a pulse width modulation (PWM) signal is input to the gates of the FETs of the first and second inverter circuits  42 A and  42 B. Thus, the three-phase motor driving currents Ia, Ib, and Ic output from the first and second inverter circuits  42 A and  42 B are rectangular wave signals having a controlled duty ratio. Due to this, in a case of simply detecting the instantaneous values of the three-phase motor driving currents Ia, Ib, and Ic, if detected when the rectangular wave signals are OFF, the detected values do not represent accurate motor current values. 
     Accordingly, in order to accurately detect the upstream-side current detection values IU1 and IU2, the upstream-side current detection values IU1 and IU2 are supplied to a peak hold circuit that holds peak values for a time equal to or more than approximately one cycle of the pulse width modulation signal. In this manner, by holding the peak values, peak (maximum) values of the upstream-side current detection values IU1 and IU2 can be quickly and accurately detected. 
     (Short-Circuit Failure Detection Processing) 
     Next, based on  FIG. 9 , a description will be given of processing steps of short-circuit failure detection processing of the first and second power source blocking circuits  44 A and  44 B and the first and second motor current blocking circuits  33 A and  33 B by the abnormality detecting unit  31   a . In addition, the short-circuit failure detection processing is repeatedly executed in a previously set cycle. 
     When the abnormality detecting unit  31   a  executes the short-circuit failure detection processing, first, the unit  31   a  proceeds to step S 100 , as depicted in  FIG. 9 . 
     At step S 100 , the abnormality detecting unit  31   a  determines whether or not an elapsed time from a previous check has passed a previously set predetermined time on the basis of a count value of an unillustrated timer provided in the control computing device  31 . Then, when determining that it is an initial check or that the elapsed time has passed the predetermined time (Yes), the unit  31   a  proceeds to step S 102 , whereas when determining negatively (No), the unit  31   a  ends the series of processing. 
     When proceeding to step S 102 , the abnormality detecting unit  31   a  determines whether or not there is motor energization or whether or not energization is necessary on the basis of the steering assisting current command value I*, the three-phase current command values Ia*, Ib*, and Ic*, and the three-phase motor driving current values Ia, Ib, and Ic computed by the control computing unit  31 . Then, when determining that there is motor energization or energization is necessary (Yes), the unit  31   a  proceeds to step S 104 , whereas when determining that energization is unnecessary (No), the unit  31   a  proceeds to step S 106 . 
     Specifically, assume that, by comparing each above-mentioned current value with a previously set current threshold value, for example, the steering assisting current command value I* is determined to be equal to or more than a first current threshold value and any of the three-phase current command values Ia*, Ib*, and Ic* is determined to be equal to or more than a second current threshold value. In this case, additionally, when any of the three-phase motor driving current values Ia, Ib, and Ic is equal to or more than a previously set third current threshold value, it is determined that there is energization to the motor. Additionally, when the three-phase motor driving current values Ia, Ib, and Ic are all less than the previously set third current threshold value, it is determined that there is no energization to the motor but energization is necessary. 
     On the other hand, assume that the steering assisting current command value I* is determined to be less than the first current threshold value and the three-phase current command values Ia*, Ib*, and Ic* are determined to be all less than the second current threshold value. In this case, additionally, when all of the three-phase motor driving current values Ia, Ib, and Ic are less than the previously set third current threshold value, it is determined that energization is unnecessary and there is no energization. In addition, when any of the three-phase motor driving current values Ia, Ib, and Ic is equal to or more than the third threshold value, it is determined that there is motor energization but energization is unnecessary. 
     When proceeding to step S 104 , the abnormality detecting unit  31   a  executes failure check processing by current comparison for performing short-circuit failure check on the basis of currents flowing to the first and second motor driving circuits  32 A and  32 B during motor energization and ends the series of processing. In addition, after ending the failure check processing by current comparison, the counter value of the timer is cleared. 
     On the other hand, when proceeding to step S 106 , the abnormality detecting unit  31   a  executes failure check processing by voltage comparison for performing short-circuit failure check on the basis of voltages generated in the first and second motor driving circuits  32 A and  32 B during motor nonenergization and ends the series of processing. In addition, after ending the failure check processing by voltage comparison, the counter value of the timer is cleared. 
     (Failure Check Processing by Current Comparison) 
     Next, based on  FIGS. 10 to 22 , a description will be given of processing steps of the failure check processing by current comparison. 
     When the abnormality detecting unit  31   a  executes the failure check processing by current comparison, first, the unit  31   a  proceeds to step S 200 , as depicted in  FIG. 10 . 
     At step S 200 , the abnormality detecting unit  31   a  executes power source-side current check blocking operation processing and proceeds to step S 202 . 
     Hereinafter, a specific example of the power source-side current check blocking operation processing will be described based on  FIG. 11  and  FIGS. 12A to 12C . Here,  FIG. 11  is a circuit diagram in which the circuit diagram of  FIG. 4  is simplified by focusing on the flow of current. Additionally,  FIGS. 12A to 12C  are diagrams depicting blocking portions changed in the circuit diagram of  FIG. 11 . 
     In the present embodiment, in a previously set power source-side current check blocking operation pattern, a FET as an object for detecting a short-circuit failure is put in a blocked state (an OFF state). 
     Herein, the power source-side current check blocking operation pattern is a pattern in which a FET to be blocked of the FETs QC 1  to QC 2  and QD 1  to QD 2  of the first and second power source blocking circuits  44 A and  44 B is determined in such a manner that energization paths to all phases (the three phases in the present embodiment) of the motor are maintained. 
     Specifically, as depicted in  FIG. 11 , in the power source-side current check blocking operation pattern in a case of detection of a short-circuit failure of the FET QC 1 , the FET QC 1  is turned OFF (a blocked state), whereas the FETs QC 2 , QD 1 , and QD 2  are turned ON. In addition, in the blocking operation pattern, the respective FETs Q 1  to Q 6  of the first and second inverter circuits  42 A and  42 B are put in a state driven and controlled by a PWM gate signal (hereinafter referred to as “PWM-driven state”). At this time, the abnormality detecting unit  31   a  outputs, to the second gate driving circuit  41 B, the motor voltage command value V2* set so that the second inverter circuit  42 B is responsible for supplying 100 [%] of a motor current necessary to assist steering (hereinafter referred to as “steering assisting current). 
     This blocking operation pattern enables the energization paths between the second motor driving circuit  32 B and all phases of the motor to be maintained, and also can cause the second inverter circuit  42 B to be responsible for supplying 100 [%] of the necessary steering assisting current. 
     Similarly, the power source-side current check blocking operation pattern in a case of detection of a short-circuit failure of the FET QC 2  is a blocking operation pattern in which the FET QC 2  is turned OFF (a blocked state), whereas the FETs QC 1 , QD 1 , and QD 2  are turned ON, as depicted in  FIG. 12A . In addition, the power source-side current check blocking operation pattern in a case of detection of a short-circuit failure of the FET QD 1  is a blocking operation pattern in which the FET QD 1  is turned OFF (a blocked state), whereas the FETs QC 1 , QC 2 , and QD 2  are turned ON, as depicted in  FIG. 12B . In addition, the power source-side current check blocking operation pattern in a case of detection of a short-circuit failure of the FET QD 2  is a blocking operation pattern in which the FET QD 2  is turned OFF (a blocked state), whereas the FETs QC 1 , QC 2 , and QD 1  are turned ON, as depicted in  FIG. 12C . In all of the cases, the respective FETs Q 1  to Q 6  of the first and second inverter circuits  42 A and  42 B are put in a PWM-driven state. 
     In all of the blocking operation patterns described above, only one of the first and second motor driving circuits  32 A and  32 B drives the three-phase electric motor  22 . Thus, in the present embodiment, the control computing device  31  controls one of the circuits that maintains energization paths so that the circuit side supplies 100 [%] of the amount of current necessary to assist steering, as described above. However, in order to prevent the circuit from being damaged by, for example, a load exceeding a rated value, the present embodiment sets an upper limit value of the amount of current for which the circuit is responsible. Then, when the amount of current necessary to assist steering exceeds the upper limit value, the control computing device  31  cancels the execution of check and restarts control by both of the motor driving circuits. 
     Returning to  FIG. 10 , at step S 202 , the failure check processing by current comparison is performed on the basis of the upstream-side current detection values IU1 and IU2 of the current detecting circuits  39 A 1  and  39 B 1  to determine whether or not the blocking performing portion is being non-energized. Then, when determining as being non-energized (No), the abnormality detecting unit  31   a  proceeds to step S 204 , whereas when determining negatively (Yes), the unit  31   a  proceeds to step S 216 . 
     Hereinafter, a specific example of the failure check processing by current comparison in the power source-side current check blocking operation, which is executed at step S 202 , will be described based on  FIG. 13 . 
     At step S 202 , when the failure check processing by current comparison in the power source-side current check blocking operation is started, first, the abnormality detecting unit  31   a  proceeds to step S 2000 , as depicted in  FIG. 13 . 
     At step S 2000 , the abnormality detecting unit  31   a  compares an absolute value of an upstream-side current detection value corresponding to a blocking portion with a previously set upstream-side current threshold value. After that, the unit  31   a  proceeds to step S 2002 . Herein, the upstream-side current threshold value is a value set within an error range in which it can be determined that there is no current flow, on the basis of 0 [A]. 
     In the present embodiment, when the blocking portion is the FET QC 1  or QC 2  of the first power source blocking circuit  44 A, the upstream-side current detection value IU1 of the current detecting circuit  39 A 1  is compared with the upstream-side current threshold value. On the other hand, when the blocking portion is the FET QD 1  or QD 2  of the second power source blocking circuit  44 B, the upstream-side current detection value IU2 of the current detecting circuit  39 B 1  is compared with the upstream-side current threshold value. 
     At step S 2002 , the abnormality detecting unit  31   a  determines whether or not the upstream-side current detection value is equal to or less than the upstream-side current threshold value on the basis of the comparison result of step S 2000 . Then, when determining that it is equal to or less than the upstream-side current threshold value (Yes), the unit  31   a  proceeds to step S 2004 , whereas when determining negatively (No), the unit  31   a  proceeds to step S 2010 . 
     Herein, when the blocking portion is in a normally blocked state, energization between the portion and the battery  27  is blocked. Thereby, the upstream-side current detection value corresponding to the blocking portion (hereinafter referred to as “upstream-side blocking object current value”) becomes 0 [A] or substantially 0 [A]. Accordingly, the upstream-side blocking object current value becomes equal to or less than the upstream-side current threshold value. On the other hand, when a short-circuit failure occurs in the blocking portion, current flows thereinto from the battery  27 , whereby the absolute value of the upstream-side blocking object current value becomes larger than the upstream-side current threshold value. 
     For example, when the FET QC 1  is assumed to be a blocking portion and a short-circuit failure occurs in the FET QC 1 , the upstream-side blocking object current value IU1 becomes “IU1≠0 [A]”, and the absolute value thereof becomes larger than the upstream-side current threshold value. 
     At step S 2004 , the abnormality detecting unit  31   a  compares the upstream-side blocking object current value with an upstream-side current detection value of another inverter circuit of an energizing portion corresponding thereto (hereinafter referred to as “upstream-side energizing object current value”), and the unit  31   a  proceeds to step S 2006 . 
     Since the present embodiment includes the two inverter circuits: the first and second inverter circuits  42 A and  42 B, any one of the upstream-side current detection value IU1 and the upstream-side current detection value IU2 is the upstream-side blocking object current value, and any other one thereof is the upstream-side energizing object current value. Then, a comparison is made between the magnitudes of the upstream-side blocking object current value and the upstream-side energizing object current value. 
     At step S 2006 , the abnormality detecting unit  31   a  determines whether or not the upstream-side energizing object current value is larger than the upstream-side blocking object current value. Then, when determining that it is larger (Yes), the unit  31   a  proceeds to step S 2008 , whereas when determining negatively (No), the unit  31   a  proceeds to step S 2010 . 
     Specifically, since the upstream-side blocking object current value becomes a current value in a state in which current from the battery  27  is blocked, the value is 0 [A] or substantially 0 [A]. Meanwhile, the upstream-side energizing object current value is a current value in a state energized with the battery  27 . Accordingly, when the FET as the blocking portion is in a normally blocked state, the upstream-side blocking object current value becomes 0 [A] or substantially 0 [A], whereby the upstream-side energizing object current value becomes larger than the upstream-side blocking object current value. 
     For example, when only the FET QC 1  of the FETs of the first and second power source blocking circuits  44 A and  44 B, is put in a blocked state, the upstream-side blocking object current value becomes IU1 and the upstream-side energizing object current value becomes IU2. When the FET QC 1  is normal, the upstream-side blocking object current value IU1 is “IU1≈0 [A]”, and the upstream-side blocking object current value IU1 and the upstream-side energizing object current value IU2 are in a magnitude relationship of “IU1&lt;IU2”. 
     When proceeding to step S 2008 , the abnormality detecting unit  31   a  determines that there is no energization, ends the series of processing, and returns to the initial processing. 
     On the other hand, when proceeding to step S 2010 , the abnormality detecting unit  31   a  determines that there is energization, ends the series of processing, and returns to the initial processing. 
     While the specific example of the failure check processing by current comparison has been described above, the invention is not limited to this configuration and may be configured to determine whether or not there is energization by performing only one of the processing of the above steps S 2000  to S 2002  and the processing of the above steps S 2004  to S 2006 . 
     Returning to  FIG. 10 , when proceeding to step S 204 , the abnormality detecting unit  31   a  determines whether check processing of all power source-side blocking portions has been ended or not. Then, when determining that the check processing has been ended (Yes), the unit  31   a  proceeds to step S 206 , whereas when determining negatively (No), the unit  31   a  proceeds to step S 200 . 
     Specifically, the abnormality detecting unit  31   a  determines whether or not the failure check processing of step S 202  has been ended in all the FETs of the first and second power source blocking circuits  44 A and  44 B. Then, when determining that it has not been ended, the unit  31   a  repeatedly executes failure check processing of unchecked FETs in the blocking operation patterns depicted in  FIG. 11  and  FIGS. 12A to 12C  until the check processing of all the FETs QC 1  to QC 2  and QD 1  to QD 2  is ended. 
     When proceeding to step S 206 , the abnormality detecting unit  31   a  executes motor-side current check blocking operation processing and proceeds to step S 208 . 
     Hereinafter, a specific example of motor-side current check blocking operation processing will be described based on  FIG. 14  to  FIG. 22 . 
     At step S 206 , when the motor-side current check blocking operation processing is started, first, the abnormality detecting unit  31   a  proceeds to step S 2100 , as depicted in  FIG. 14 . 
     At step S 2100 , the abnormality detecting unit  31   a  determines whether a low-load check mode has been set or not. Then, when determining that the low-load check mode has been set (Yes), the unit  31   a  proceeds to step S 2102 , whereas when determining negatively (No), the unit  31   a  proceeds to step S 2104 . 
     When proceeding to step S 2102 , the abnormality detecting unit  31   a  performs low-load blocking operation processing of an unchecked portion, ends the series of processing, and returns to the initial processing. 
     On the other hand, when proceeding to step S 2104 , the abnormality detecting unit  31   a  determines whether a first high-speed check mode has been set or not. Then, when determining that the first high-speed check mode has been set (Yes), the unit  31   a  proceeds to step S 2106 , whereas when determining negatively (No), the unit  31   a  proceeds to step S 2108 . 
     When proceeding to step S 2106 , the abnormality detecting unit  31   a  performs the first high-speed blocking operation processing of unchecked portions, ends the series of processing, and returns to the initial processing. 
     Alternatively, when proceeding to step S 2108 , the abnormality detecting unit  31   a  performs a second high-speed blocking operation processing of unchecked portions, ends the series of processing, and returns to the initial processing. 
     Hereinafter, a specific example of blocking operation processing in each check mode will be described. 
     (Low-Load Blocking Operation Processing) 
     First, based on  FIG. 15  and  FIGS. 16A to 16E , a description will be given of a specific example of the low-load blocking operation processing where the low-load check mode is set. Here,  FIG. 15  is a circuit diagram in which the circuit diagram of  FIG. 4  is simplified by focusing on the flow of current. Additionally,  FIGS. 16A to 16E  are diagrams depicting blocking portions changed in the circuit diagram of  FIG. 15 . 
     In the present embodiment, when the low-load check mode is set, a FET as an object for detecting a short-circuit failure is put in a blocked state (an OFF state) by a previously set low-load blocking operation pattern. 
     Herein, the low-load blocking operation pattern is a pattern in which any one FET of the FETs QA 1  to QA 3  and QB 1  to QB 3  of the first and second motor current blocking circuits  33 A and  33 B is determined as a FET to be blocked. In other words, the low-load blocking operation pattern is a check mode in which each one FET to be blocked in the first and second motor current blocking circuits  33 A and  33 B is checked one by one in order. 
     Specifically, in the low-load blocking operation pattern in a case of detection of a short-circuit failure of the FET QA 1 , the FET QA 1  is turned OFF (a blocked state), whereas the FETs QA 2  to QA 3  and QB 1  to QB 3  are turned ON, as depicted in  FIG. 15 . In addition, in the blocking operation pattern, the respective FETs Q 1  to Q 6  of the first and second inverter circuits  42 A and  42 B are put in a PWM-driven state. 
     At this time, the abnormality detecting unit  31   a  outputs, to the second gate driving circuit  41 B, the motor voltage command value V2* set so that the switching arm SWBa of the second inverter circuit  42 B is responsible for supplying 100 [%] of a necessary steering assisting current. In addition, the other switching arms SWBb and SWBc are set to be responsible for supplying 50 [%] thereof, the same as usual. In addition, the first inverter circuit  42 A performs the same operation as usual. 
     With this blocking operation pattern, energization paths to all the phases of the motor can be formed by remaining paths other than a path blocked by the FET QA 1  in the first and second motor driving circuits  32 A and  32 B. In addition, in a case of an A-phase assisting current, the pattern can cause the switching arm SWBa of the second inverter circuit  42 B to be responsible for supplying 100 [%] of a necessary amount of the steering assisting current. In addition, as for a B-phase assisting current, it can cause the switching arms SWAb and SWBb of the first and second inverter circuits  42 A and  42 B to be responsible for supplying each 50 [%] thereof. Furthermore, as for a C-phase assisting current, it can cause the switching arms SWAc and SWBc of the first and second inverter circuits  42 A and  42 B to be responsible for supplying each 50 [%] thereof. 
     Similarly, the low-load blocking operation pattern in a case of detection of a short-circuit failure of the FET QA 2  is a blocking operation pattern in which the FET QA 2  is turned OFF (a blocked state), whereas the FETs QA 1 , QA 3 , and QB 1  to QB 3  are turned ON, as depicted in  FIG. 16A . In addition, the low-load blocking operation pattern in a case of detection of a short-circuit failure of the FET QA 3  is a blocking operation pattern in which the FET QA 3  is turned OFF (a blocked state), whereas the FETs QA 1  to QA 2  and QB 1  to QB 3  are turned ON, as depicted in  FIG. 16B . In addition, the low-load blocking operation pattern in a case of detection of a short-circuit failure of the FET QB 1  is a blocking operation pattern in which the FET QB 1  is turned OFF (a blocked state), whereas the FETs QA 1  to QA 3  and QB 2  to QB 3  are turned ON, as depicted in  FIG. 16C . Additionally, the low-load blocking operation pattern in a case of detection of a short-circuit failure of the FET QB 2  is a blocking operation pattern in which the FET QB 2  is turned OFF (a blocked state), whereas the FETs QA 1  to QA 3 , QB 1 , and QB 3  are turned ON, as depicted in  FIG. 16D . Additionally, the low-load blocking operation pattern in case of detection of a short-circuit failure of the FET QB 3  is a blocking operation pattern in which the FET QB 3  is turned OFF (a blocked state), whereas the FETs QA 1  to QA 3  and QB 1  to QB 2  are turned ON, as depicted in  FIG. 16E . In all the cases, the respective FETs Q 1  to Q 6  of the first and second inverter circuits  42 A and  42 B are put in a PWM-driven state. With these blocking operation patterns, energization paths to all the phases of the motor can be formed by remaining paths unblocked in the first and second motor driving circuits  32 A and  32   b.    
     In the blocking operation patterns described above, any one switching arm of one of the first and second inverter circuits  42 A and  42 B is responsible for performing energization to one phase of the three-phase electric motor  22 . Accordingly, in the present embodiment, as described above, the control computing device  31  controls the one switching arm so as to be responsible for supplying 100 [%] of the amount of current (any one of Ia*, Ib*, and Ic*) necessary for steering assistance of the phase corresponding to the arm. However, in order to prevent the switching arm from being damaged by, for example, a load exceeding a rated value, the present embodiment sets an upper limit value of the amount of current for which the one switching arm is responsible. Then, when the amount of current necessary for steering assistance exceeds the upper limit value, the control computing device  31  cancels check execution and restarts control by all arms of both motor driving circuits. 
     (First High-Speed Blocking Operation Processing) 
     Next, a specific example of a first high-speed blocking operation processing where the first high-speed check mode is set will be described based on  FIG. 17  and  FIG. 18 . Here,  FIG. 17  is a circuit diagram in which the circuit diagram of  FIG. 4  is simplified by focusing on the flow of current. In addition,  FIG. 18  are diagrams depicting blocking portions changed in the circuit diagram of  FIG. 17 . 
     In the present embodiment, when the first high-speed check mode is set, FETs as objects for detecting a short-circuit failure are put in a blocked state (an OFF state) by a previously set first high speed blocking operation pattern. 
     Herein, the first high-speed blocking operation pattern is a pattern in which, all the FETs of either one of a set of the FETs QA 1  to QA 3  of the first motor current blocking circuit  33 A and a set of the FFTs QB 1  to QB 3  of the second motor current blocking circuit  33 B are determined as FETs to be blocked. In other words, the first high-speed check mode is a check mode in which all the FETS of each of the first and second motor current blocking circuits  33 A and  33 B are collectively checked in order starting from either one of the circuits. 
     Specifically, in the first high-speed blocking operation pattern in a case of detection of a short-circuit failure of the FETs QA 1  to QA 3 , the FETs QA 1  to QA 3  are turned OFF (a blocked state), whereas the FETs QB 1  to QB 3  are turned ON, as depicted in  FIG. 17 . In addition, in the blocking operation pattern, the respective FETs Q 1  to Q 6  of the first and second inverter circuits  42 A and  42 B are put in a PWM-driven state. 
     At this time, the abnormality detecting unit  31   a  outputs, to the second gate driving circuit  41 B, the motor voltage command value V2* set so that the second inverter circuit  42 B is responsible for supplying 100 [%] of a necessary steering assisting current. 
     This blocking operation pattern enables energization paths to all the phases of the motor to be maintained by the second motor driving circuit  32 B, and also can cause the second inverter circuit  42 B to be responsible for supplying 100 [%] of the necessary steering assisting current. 
     Similarly, the first high-speed blocking operation pattern in a case of detection of a short-circuit failure of the FETs QB 1  to QB 3  is a blocking operation pattern in which the FETs QB 1  to QB 3  are turned OFF (a blocked state), whereas the FETs QA 1  to QA 3  are turned ON, as depicted in  FIG. 18 . Even in this case, the respective FETs Q 1  to Q 6  of the first and second inverter circuits  42 A and  42 B are put in a PWM-driven state. 
     At this time, the abnormality detecting unit  31   a  outputs, to the first gate driving circuit  41 A, the motor voltage command value V1* set so that the first inverter circuit  42 A is responsible for supplying 100 [%] of a necessary steering assisting current. 
     With this blocking operation pattern, energization paths to all the phases of the motor can be maintained by the first motor driving circuit  32 A. In addition, the pattern can cause the first inverter circuit  42 A to be responsible for supplying 100 [%] of the necessary steering assisting current. 
     However, in order to prevent the inverter circuit from being damaged by, for example, a load exceeding a rated value, the present embodiment sets an upper limit value of the amount of the current for which the one inverter circuit is responsible. Then, when the amount of motor current necessary for steering assistance exceeds the upper limit value, the control computing unit  31  cancels check execution and restarts control by all the arms of both motor driving circuits. 
     (Second High-Speed Blocking Operation Processing) 
     Next, a specific example of the second high-speed blocking operation processing where the second high-speed check mode is set will be described based on  FIG. 19  and  FIGS. 20A to 20C . Here,  FIG. 19  is a circuit diagram in which the circuit diagram of  FIG. 4  is simplified by focusing on the flow of current. Additionally,  FIGS. 20A to 20C  are diagrams depicting blocking portions changed in the circuit diagram of  FIG. 19 . 
     In the present embodiment, when the second high-speed check mode is set, FETs as objects for detecting a short-circuit failure are put in a blocked state (an OFF state) by a previously set second high-speed blocking operation pattern. 
     Herein, the second high-speed blocking operation pattern is a pattern in which one of the FETs of either one of two set including a set of the FETs QA 1  to QA 3  of the first motor current blocking circuit  33 A and a set of FFTs QB 1  to QB 3  of the second motor current blocking circuit  33 B, and two of the FETs of the other one of the two sets having a phase different from a phase of the one of the FFTs of the either one are determined as FETs to be blocked. In other words, the second high-speed check mode is a check mode in which, each three FETs as each combination of the FETs of the FETs of the first and second motor current blocking circuits  33 A and  33 B are collectively checked. 
     Specifically, in a case of detection of a short-circuit failure of three FETs: the FETs QA 1 , QB 2 , and QB 3 , the FETs QA 1 , QB 2 , and QB 3  are turned OFF (a blocked state), whereas the FETs QA 2  to QA 3  and QB 1  are turned ON, as depicted in  FIG. 19 . In addition, in the blocking operation pattern, the respective FETs Q 1  to Q 6  of the first and second inverter circuits  42 A and  42 B are put in a PWM-driven state. 
     At this time, the abnormality detecting unit  31   a  outputs, to the second gate driving circuit  41 B, the motor voltage command value V2* set so that the switching arm SWBa of the second inverter circuit  42 B is responsible for supplying 100 [%] of a steering assisting current necessary for the A phase. In addition, the abnormality detecting unit  31   a  outputs, to the first gate driving circuit  41 A, the motor voltage command value V1* set so that the switching arms SWAb and SWAc of the first inverter circuit  42 A is responsible for supplying 100 [%] of a steering assisting current necessary for the B phase and the C phase. 
     With this blocking operation pattern, energization paths to all the phases of the motor can be formed by remaining paths other than paths blocked by the FETs QA 1 , QB 2 , and QB 3  of the first and second motor current blocking circuits  33 A and  33 B. Additionally, in the case of an A-phase assisting current, the pattern can cause the switching arm SWBa of the second inverter circuit  42 B to be responsible for supplying 100 [%] of a necessary steering assisting current. In addition, as for a B-phase assisting current, it can cause the switching arm SWAb of the first inverter circuit  42 A to be responsible for supplying 100 [%] thereof. Furthermore, as for a C-phase assisting current, it can cause the switching arm SWAc of the first inverter circuit  42 A to be responsible for supplying 100 [%] thereof. 
     Furthermore, in the second high-speed blocking operation pattern in a case of detection of a short-circuit failure of the remaining three FETs: the FETs QA 2 , QA 3 , and QB 1 , the FETs QA 2 , QA 3 , and QB 1  are turned OFF (a blocked state), whereas the FETs QA 1 , QB 2 , and QB 3  are turned ON, as depicted in  FIG. 20A . In addition, in the blocking operation pattern, the respective FETs Q 1  to Q 6  of the first and second inverter circuits  42 A and  42 B are put in a PWM-driven state. 
     At this time, the abnormality detecting unit  31   a  outputs, to the first gate driving circuit  41 A, the motor voltage command value V1* set so that the switching arm SWAa of the first inverter circuit  42 A is responsible for supplying 100 [%] of a steering assisting current necessary for the A phase. In addition, the unit  31   a  outputs, to the second gate driving circuit  41 B, the motor voltage command value V2* set so that the switching arms SWBb and SWBc of the second inverter circuit  42 B are responsible for supplying 100 [%] of a steering assisting current necessary for the B phase and the C phase. 
     With this blocking operation pattern, energization paths to all the phases of the motor can be formed by remaining paths other than paths blocked by the FETs QA 2 , QA 3 , and QB 1  of the first and second motor current blocking circuits  33 A and  33 B. In addition, in a case of an A-phase assisting current, the pattern can cause the switching arm SWAa of the first inverter circuit  42 A to be responsible for supplying 100 [%] of a necessary amount of the steering assisting current. Additionally, as for a B-phase assisting current, it can cause the switching arm SWBb of the second inverter circuit  42 B to be responsible for supplying 100 [%] thereof. Furthermore, as for a C-phase assisting current, it can cause the switching arm SWBc of the second inverter circuit  42 B to be responsible for supplying 100 [%] thereof. 
     However, in order to prevent each switching arm from being damaged by, for example, a load exceeding a rated value, the present embodiment sets an upper limit value of the amount of the current for which each switching arm is responsible. Then, when the amount of current necessary for steering assistance exceeds the upper limit value, the control computing unit  31  cancels check execution and restarts control by all the arms of both motor driving circuits. 
     Here, the second high-speed blocking operation pattern is not limited to the combinations of the blocking operation patterns depicted in  FIG. 19  and  FIG. 20A , and may be other combinations, such as, for example, combinations of blocking operation patterns as depicted in  FIGS. 20B and 20C . 
     Returning to  FIG. 10 , at step S 208 , the failure check processing by current comparison is performed on the basis of the downstream-side current detection values IA1 to IC1 and IA2 to IC2 of the current detecting circuits  39 A 2  and  39 A 4  and  39 B 1  to  39 B 4  to determine whether the blocking performing portion is not being energized. Then, when determining that it is not being energized (No), the abnormality detecting unit  31   a  proceeds to step S 210 , whereas when determining negatively (Yes), the unit  31   a  proceeds to step S 216 . 
     Hereinafter, a specific example of the failure check processing by current comparison in the motor-side current check blocking operation corresponding to each check mode will be described based on  FIG. 21  and  FIG. 22 . 
     (Failure Check Processing by Current Comparison in Low-Load Check Mode) 
     First, a specific example of the failure check processing by current comparison where the low-load check mode is set will be described based on  FIG. 21 . 
     At step S 208 , when the failure check processing by current comparison in the low-load check mode is started, first, the abnormality detecting unit  31   a  proceeds to step S 2200 , as depicted in  FIG. 21 . 
     At step S 2200 , the abnormality detecting unit  31   a  compares a downstream-side current detection value corresponding to a FET as a blocking portion in the low-load blocking operation pattern with a previously set downstream-side current threshold value. After that, the unit  31   a  proceeds to step S 2202 . Herein, the downstream-side current threshold value is a value set within an error range in which it can be determined that there is no current flow, on the basis of 0 [A]. 
     Specifically, when the blocking portion is any one of the FETs QA 1  to QA 3  of the first motor current blocking circuit  33 A, any one of the downstream-side current detection values IA1 to IC1 corresponding to the blocking portion in the current detecting circuits  39 A 2  to  39 A 4  is compared with the downstream-side threshold value. On the other hand, when the blocking portion is any one of the FETs QB 1  to QB 3  of the second motor current blocking circuit  33 B, any one of the downstream-side current detection values IA2 to IC2 corresponding to the blocking portion in the current detecting circuits  39 B 2  to  39 B 4  is compared with the downstream-side threshold value. 
     At step S 2202 , the abnormality detecting unit  31   a  determines whether the downstream-side current detection value corresponding to the blocking portion is equal to or less than the downstream-side current threshold value or not on the basis of the comparison result of step S 2200 . Then, when determining that it is equal to or less than the downstream-side current threshold value (Yes), the unit  31   a  proceeds to step S 2204 , whereas when determining negatively (No), the unit  31   a  proceeds to step S 2210 . 
     In other words, when the blocking portion is in a normally blocked state, no current flows into the motor winding of the corresponding phase of the three-phase electric motor  22  from the switching arm corresponding to the blocking portion of the inverter circuit. Thus, an absolute value of the downstream-side current detection value corresponding to the blocking portion (hereinafter referred to as “downstream-side blocking object current value”) becomes 0 [A] or substantially 0 [A]. In the present embodiment, when the downstream-side blocking object current value is equal to or less the downstream-side current threshold value, it is determined that any one of the corresponding downstream-side current detection values IA1 to IC1 and IA2 to IC2 is 0 [A]. 
     At step S 2204 , the abnormality detecting unit  31   a  compares the downstream-side blocking object current value with an absolute value of a downstream-side current detection value of an energization portion of an other inverter circuit corresponding thereto (hereinafter referred to as “downstream-side energizing object current value”), and the unit  31   a  proceeds to step S 2206 . 
     In other words, since the present embodiment includes the two inverter circuits: the first and second inverter circuits  42 A and  42 B, a comparison is made between magnitudes of an absolute value of any one of the downstream-side current detection values IA1 to IC1 of the first inverter circuit  42 A and an absolute value of any one of the downstream-side current detection values IA2 to IC2 of the second inverter circuit  42 B, corresponding to the same phase to that of the any one of the downstream-side current detection values IA1 to IC1. 
     At step S 2206 , the abnormality detecting unit  31   a  determines whether the downstream-side energizing object current value is larger than the downstream-side blocking object current value or not. Then, when determining that it is larger (Yes), the unit  31   a  proceeds to step S 2208 , whereas when determining negatively (No), the unit  31   a  proceeds to step S 2210 . 
     In other words, the downstream-side blocking object current value is a current value in a state in which energization between the switching arm of the phase corresponding to the blocking portion in the inverter circuit and the motor winding of the phase corresponding to the blocking portion in the three-phase electric motor  22  has been blocked. Thus, the downstream-side blocking object current value is 0 [A] or substantially 0 [A]. On the other hand, the downstream-side energizing object current value corresponding to the downstream-side blocking object current value is a current value in a state in which there is energization between the switching arm of each phase of the inverter circuit and the motor winding of each phase of the three-phase electric motor  22 . Accordingly, when the FET as the blocking portion is in a normally blocked state, the downstream-side energizing object current value is larger than the downstream-side blocking object current value. 
     For example, when the FET QA 1  is in a blocked state, the downstream-side blocking object current value is |IA1| and the downstream-side energizing object current value is |IA2|. In this case, when the FET QA 1  is normal, the downstream-side blocking object current value |IA1| is “|IA1|≈0 [A]”, and the downstream-side blocking object current value and the downstream-side energizing object current value |IA2| are in a magnitude relationship of “|IA1|&lt;|IA2|”. 
     When proceeding to step S 2208 , the abnormality detecting unit  31   a  determines that there is no energization, ends the series of processing, and returns to the initial processing. 
     On the other hand, when proceeding to step S 2210 , the abnormality detecting unit  31   a  determines that there is energization, ends the series of processing, and returns to the initial processing. 
     While the specific example of the failure check processing by current comparison in the low-load check mode has been described above, the invention is not limited to the configuration, and may employ a configuration in which only either one of the processing of step S 2200  to S 2202  and the processing of steps S 2204  to S 2206  is performed to determine whether or not there is energization. 
     (Failure Check Processing by Current Comparison in First and Second High-Speed Check Modes) 
     Next, a specific example of failure check processing by current comparison where the first or second high-speed check mode is set will be described based on  FIG. 22 . 
     At step S 208 , when the failure check processing by current comparison in the first or second high-speed check mode is started, first, the abnormality detecting unit  31   a  proceeds to step S 2300 , as depicted in  FIG. 22 . 
     At step S 2300 , the abnormality detecting unit  31   a  compares downstream-side current detection values corresponding to FETs as blocking portions in the first or second high-speed blocking operation pattern with a previously set downstream-side current threshold value. 
     Herein, when the first high-speed check mode is set and the blocking portions are the FETs QA 1  to QA 3  of the first motor current blocking circuit  33 A, each of the absolute values of the downstream-side current detection values IA1 to IC1 (downstream-side blocking object current values) of the current detecting circuits  39 A 2  to  39 A 4  is compared with the downstream-side current threshold value. On the other hand, when the blocking portions are the FETs QB 1  to QB 3  of the second motor current blocking circuit  33 B, each of the absolute values of the downstream-side current detection values IA2 to IC2 (downstream-side blocking object current values) corresponding to the current detecting circuits  39 B 2  to  39 B 4  is compared with the downstream-side current threshold value. 
     Alternatively, assume that the second high-speed check mode is set and the blocking portions are a combination of any one of the FETs QA 1  to QA 3  of the first motor current blocking circuit  33 A and any two of the FETs QB 1  to QB 3  of the second motor current blocking circuit  33 B. In this case, any one corresponding to the blocking portion of the downstream-side blocking object current values |IA1| to |IC1| is compared with the downstream-side current threshold value. In addition, each of any two corresponding to the blocking portions of the downstream-side blocking object current values |IA2| to |IC2| are compared with the downstream-side current threshold value. 
     On the other hand, assume that the second high-speed check mode is set and the blocking portions are a combination of any two of the FETs QA 1  to QA 3  of the first motor current blocking circuit  33 A and any one of the FETs QB 1  to QB 3  of the second motor current blocking circuit  33 B. In this case, each of any two corresponding to the blocking portions of the downstream-side blocking object current values |IA1| to |IC1| is compared with the downstream-side current threshold value. In addition, any one corresponding to the blocking portion of the downstream-side blocking object current values |IA2| to |IC2| is compared with the downstream-side current threshold value. 
     At step S 2302 , the abnormality detecting unit  31   a  determines whether the downstream-side blocking object current values corresponding to the blocking portions are all equal to or less than the downstream-side current threshold value on the basis of the comparison results of step S 2300 . Then, when determining that they are equal to or less than the downstream-side current threshold value (Yes), the unit  31   a  proceeds to step S 2304 , whereas when determining negatively (No), the unit  31   a  proceeds to step S 2310 . 
     In other words, when the blocking portions are in a normally blocked state, the downstream-side blocking object current values are all 0 [A] or substantially 0 [A]. On the other hand, when a short-circuit failure occurs in any of the blocking portions, the downstream-side blocking object current value corresponding to the FET in which the short-circuit failure is occurring becomes larger than the downstream-side current threshold value. 
     At step S 2304 , the abnormality detecting unit  31   a  compares the downstream-side current detection values corresponding to the blocking portions with downstream-side current detection values of an other inverter circuit corresponding thereto, and the unit  31   a  proceeds to step S 2306 . 
     Specifically, a comparison is made between magnitudes of an absolute value (a downstream-side blocking object current value) of a downstream-side current detection value corresponding to a FET as a blocking portion and an absolute value (a downstream-side energizing object current value) of the downstream-side current detection value corresponding to a FET as an energizing portion. 
     The present embodiment includes the two inverter circuits: the first and second inverter circuits  42 A and  42 B. Thus, a comparison is made between magnitudes of absolute values of the downstream-side current detection values IA1 to IC1 of the first inverter circuit  42 A and absolute values of the downstream-side current detection values IA2 to IC2 of the second inverter circuit  42 B. 
     At step S 2306 , the abnormality detecting unit  31   a  determines whether or not the downstream-side energizing object current value is larger than the downstream-side blocking object current value. Then, when determining that it is larger (Yes), the unit  31   a  proceeds to step S 2308 , whereas when determining negatively (No), the unit  31   a  proceeds to step S 2310 . 
     Specifically, the downstream-side blocking object current value is a current value in a state in which energization is blocked between the switching arm of the phase corresponding to the blocking portion in the inverter circuit and the motor winding of the phase corresponding to the blocking portion in the three-phase electric motor  22 , and thus becomes 0 [A] or substantially 0 [A]. On the other hand, the downstream-side energizing object current value corresponding to the downstream-side blocking object current value is a current value in a state in which there is energization between the switching arm of each phase of the inverter circuit and the motor winding of each phase of the three-phase electric motor  22 . Accordingly, when the FET as the blocking portion is in a normally blocked state, the downstream-side energizing object current value becomes larger than the downstream-side blocking object current value. 
     For example, when the first high-speed check mode is set and the FETs QA 1  to QA 3  are put in a blocked state, the downstream-side blocking object current values become |IA1|, |IB1|, and |IC1|, and the downstream-side energizing object current values become |IA2|, |IB2|, and |IC2|. In this case, when the FET QA 1  is normal, the downstream-side blocking object current value |IA1| is “|IA1|≈0 [A]”, and the downstream-side blocking object current value |IA1| and the downstream-side energizing object current value |IA2| are in a magnitude relationship of “|IA1|&lt;|IA2|”. In addition, when the FET QA 2  is normal, the downstream-side blocking object current value |IB1| is “|IB1|≈0 [A]”, and the downstream-side blocking object current value |IB1| and the downstream-side energizing object current value |IB2| are in a magnitude relationship of “|IB1|&lt;|IB2|”. Furthermore, when the FET QA 3  is normal, the downstream-side blocking object current value |IC1| is “|IC1|≈0 [A]”, and the downstream-side blocking object current value |IC1| and the downstream-side energizing object current value |IC2| are in a magnitude relationship of “|IC1|&lt;|IC2|”. 
     In addition, for example, when the second high-speed check mode is set and the FETs QA 1 , QB 2 , and QB 3  are in a blocked state, the downstream-side blocking object current values become |IA1|, |IB2|, and |IC2|, and the downstream-side energizing object current values become |IA2|, |IB1|, and |IC1|. In this case, when the FET QA 1  is normal, the downstream-side blocking object current value |IA1| is “|IA1|≈0 [A]”, and the downstream-side blocking object current value |IA1| and the downstream-side energizing object current value |IA2| are in a magnitude relationship of “|IA1|&lt;|IA2|”. In addition, when the FET QB 2  is normal, the downstream-side blocking object current value |IB2| is “|IB2|≈0 [A]”, and the downstream-side blocking object current value |IB2| and the downstream-side energizing object current value |IB1| are in a magnitude relationship of “|IB1|&gt;|IB2|”. Furthermore, when the FET QB 3  is normal, the downstream-side blocking object current value |IC2| is “|IC2|≈0 [A]”, and the downstream-side blocking object current value |IC2| and the downstream-side energizing object current value |IC1| are in a magnitude relationship of “|IC1|&gt;|IC2|”. 
     When proceeding to step S 2308 , the abnormality detecting unit  31   a  determines that there is no energization, ends the series of processing, and returns to the initial processing. 
     On the other hand, when proceeding to step S 2310 , the abnormality detecting unit  31   a  determines that there is energization, ends the series of processing, and returns to the initial processing. 
     While the specific example of the failure check processing by current comparison in first and second high-Speed check modes has been described above, the invention is not limited to this configuration and may be configured to determine whether or not there is energization by performing only either one of the above processing of steps S 2300  to S 2302  and the above processing of steps S 2304  to S 2306 . 
     Returning to  FIG. 10 , when proceeding to step S 210 , the abnormality detecting unit  31   a  determines whether check processing of all motor-side blocking portions has been ended or not. Then, when determining that the check processing has been ended (Yes), the unit  31   a  proceeds to step S 212 , whereas when determining negatively (No), the unit  31   a  proceeds to step S 206 . 
     Specifically, it is determined whether the failure check processing of step S 206  for all the FETs of the first and second motor current blocking circuits  33 A and  33 B has been ended or not. Then, when determined negatively, failure check processing of unchecked FETs is repeatedly executed by the blocking operation patterns corresponding to each check mode depicted in  FIG. 15  to  FIG. 20  until check processing for all the FETs QA 1  to QA 3  and QB 1  to QB 3  is ended. 
     When proceeding to step S 212 , the abnormality detecting unit  31   a  determines that the check results are normal in all the FETs of the first and second power source blocking circuits  44 A and  44 B and the first and second motor current blocking circuits  33 A and  33 B. After that, the unit  31   a  proceeds to step S 214 . 
     At step S 214 , the abnormality detecting unit  31   a  recovers the blocked FETs of the FETs of the first and second power source blocking circuits  44 A and  44 B and the first and second motor current blocking circuits  33 A and  33 B to energized states. In other words, the unit  31   a  outputs the abnormal detection signals SAa and SAb of the logical value “0” to the first and second motor driving circuits  32 A and  32 B. After that, the unit  31   a  ends the series of processing and returns to the initial processing. 
     On the other hand, when determining that any blocking performing portion is under energization at step S 202  or S 208  and proceeding to step S 216 , the abnormality detecting unit  31   a  determines that a short-circuit failure is occurring in the motor driving circuit corresponding to the blocking performing portion determined to be under energization. After that, the unit  31   a  proceeds to step S 218 . 
     At step S 218 , the abnormality detecting unit  31   a  performs failure-coping blocking processing for the motor driving circuit with the short-circuit failure occurring of the first and second motor driving circuits  32 A and  32 B. After that, the unit  31   a  ends the series of processing and returns to the initial processing. 
     Specifically, the failure-coping blocking processing is processing that outputs an abnormality detection signal SAa or SAb of the logical value “1” to the motor driving circuit having the short-circuit failure occurring therein of the first and second motor driving circuits  32 A and  32 B. Thereby, all the FETs of the motor driving circuit having the short-circuit failure occurring therein are controlled to be in an OFF state, and the motor driving circuit is electrically isolated from the battery  27  and the three-phase electric motor  22 . 
     (Failure Check Processing by Voltage Comparison) 
     Next, processing steps of failure check processing by voltage comparison will be described based on  FIG. 23  to  FIG. 29 . 
     When failure check processing by voltage comparison is performed by the abnormality detecting unit  31   a , first, the unit  31   a  proceeds to step S 300 , as depicted in  FIG. 23 . 
     At step S 300 , the abnormality detecting unit  31   a  performs power source-side voltage check blocking operation processing, and proceeds to step S 302 . 
     Hereinafter, a specific example of the power source-side voltage check blocking operation processing will be described based on  FIG. 24  and  FIGS. 25A and 25B . Here,  FIG. 24  is a circuit diagram in which the circuit diagram of  FIG. 4  is simplified by focusing on voltages to be monitored. In addition,  FIGS. 25A and 25B  are diagrams depicting blocking portions changed in the circuit diagram of  FIG. 24 . 
     In the present embodiment, FETs for maintaining the charge state of the electrolytic capacitors CA and CB and FETs as objects for detecting a short-circuit failure are put in a blocked state (an OFF state) by a previously set power source-side voltage check blocking operation pattern. 
     Herein, the power source-side voltage check blocking operation pattern is a pattern in which, among the respective FETs of the first and second motor driving circuits  32 A and  32 B, FETs to be blocked are determined so that the charge state of the electrolytic capacitors CA and CB are maintained. In addition, in the pattern, the FETs to be blocked are determined so that a short-circuit failure of the first or second power source blocking circuit  44 A or  44 B can be checked by detection values of the monitored voltages VR 12  and VR 22  (hereinafter referred to as “blocking portion voltage detection values VR 12  and VR 22 ”). 
     Specifically, in the power source-side voltage check blocking operation pattern in a case of detection of a short-circuit failure of the first power source blocking circuit  44 A, the FETs QC 1  and QC 2  of the first power source blocking circuit  44 A are turned OFF (a blocked state), whereas the FETs QD 1  and QD 2  of the second power source blocking circuit  44 B are turned ON, as depicted in  FIG. 24 . In addition, all the FETs QA 1  to QA 3  and QB 1  to QB 3  of the first and second motor current blocking circuits  33 A and  33 B are turned ON. Furthermore, in the blocking operation pattern, the respective FETs Q 1  to Q 6  of the first inverter circuit  42 A are turned OFF and the respective FETs Q 1  to Q 6  of the second inverter circuit  42 B are put in a PWM-driven state. Here, the respective FETs Q 1  to Q 6  of the second inverter circuit  42 B may be turned OFF. In addition, the FETs QA 1  to QA 3  of the first motor current blocking circuit  33 A may be turned OFF. 
     This blocking operation pattern allows maintaining of the changed states (states charged to a battery voltage Vbat [V]) of the electrolytic capacitors CA and CB of the first and second motor driving circuits  32 A and  32 B. In addition, a short-circuit failure of the first power source blocking circuit  44 A can be checked by the blocking portion voltage detection values VR 12  and VR 22  of the VR voltage detecting circuits  34 A and  34 B. Additionally, details of the short-circuit failure check will be described later. 
     Similarly, the power source-side voltage check blocking operation pattern in a case of detection of a short-circuit failure of the second power source blocking circuit  44 B is as follows. From the blocking operation pattern depicted in  FIG. 24 , the FETs QD 1  and QD 2  of the second power source blocking circuit  44 B are turned OFF (a blocked state) whereas the FETs QC 1  and QC 2  of the first power source blocking circuit  44 A are turned ON, as depicted in  FIG. 25A . In addition, in the blocking operation pattern, the respective FETs Q 1  to Q 6  of the first inverter circuit  42 A are put in a PWM-driven state, and the respective FETs Q 1  to Q 6  of the second inverter circuit  42 B are turned OFF, as depicted in  FIG. 25B . Here, the respective FETs Q 1  to Q 6  of the first inverter circuit  42 A may be turned OFF. In addition, the FETS QB 1  to QB 3  of the second motor current blocking circuit  33 B may be turned OFF. 
     The blocking operation pattern allows maintaining of the changed states (states charged to the battery voltage Vbat [V]) of the electrolytic capacitors CA and CB of the first and second motor driving circuits  32 A and  32 B. In addition, short-circuit failure check of the second power source blocking circuit  44 B can be made by the blocking portion voltage detection values VR 12  and VR 22 . Additionally, details of the short-circuit failure check will be described later. 
     Returning to  FIG. 23 , at step S 302 , the failure check processing by voltage comparison is performed on the basis of the blocking portion voltage detection values VR 12  and VR 22 , and it is determined whether the monitored voltage value is a normal value or not. Then, when it is determined to be a normal value (Yes), step S 304  is performed, whereas when determined negatively (No), step S 316  is performed. 
     In the description hereinbelow, when the blocking portion voltage detection values VR 12  and VR 22  are not distinguished from each other, the values may be simply referred to as “blocking portion voltage detection value VR”. 
     Hereinafter, a specific example of the failure check processing by voltage comparison in the power source-side voltage check blocking operation will be described based on  FIG. 26 . 
     At step S 302 , when the failure check processing by voltage comparison in the power source-side voltage check blocking operation is started, first, step S 3000  is performed, as depicted in  FIG. 26 . 
     At step S 3000 , the abnormality detecting unit  31   a  compares the blocking portion voltage detection value VR of the power source blocking circuit corresponding to blocking portions of one motor driving circuit with the blocking portion voltage detection value VR of the power source blocking circuit of an other motor driving circuit, and proceeds to step S 3002 . 
     In the present embodiment, the motor driving circuits include two motor driving circuits: the first and second motor driving circuits  32 A and  32 B. Thus, the blocking portion voltage detection value VR 12  of the connection line of the FETs QC 1  and QC 2  of the first power source blocking circuit  44 A is compared with the blocking portion voltage detection value VR 22  of the connection line of the FETs QD 1  and QD 2  of the second power source blocking circuit  44 B. 
     At step S 3002 , the abnormality detecting unit  31   a  determines whether or not the blocking portion voltage detection value VR of the other power source blocking circuit is larger than the blocking portion voltage detection value VR corresponding to the blocking portions. Then, when determining that it is larger (Yes), the unit  31   a  proceeds to step S 3004 , whereas determining negatively (No), the unit  31   a  proceeds to step S 3006 . 
     Herein, the VR voltage detecting circuits  34 A and  34 B of the present embodiment have a configuration depicted in  FIG. 8 . Accordingly, for example, in detecting a short-circuit failure of the first power source blocking circuit  44 A, when the FETs QC 1  and QC 2  in the blocked state are normal, the blocking portion voltage detection value VR 12  is pulled down by the resistance R 7  of the VR voltage detecting circuit  34 A, and thus becomes substantially 0 [V]. On the other hand, since the FETs QD 1  and QD 2  of the second power source blocking circuits  44 B are in the ON state, the capacitor C 1  of the VR voltage detecting circuit  34 B is charged by current supplied from the battery  27  or the electrolytic capacitor CB (charged to approximately Vbat [V]). Accordingly, the blocking portion voltage detection value VR 22  becomes a substantially battery voltage Vbat [V]. Thus, the blocking portion voltage detection value VR 22  is larger than the blocking portion voltage detection value VR 12 . 
     In addition, for example, in detecting a short-circuit failure of the first power source blocking circuit  44 A, when a short-circuit failure occurs in at least one of the FETs QC 1  and QC 2  in the blocked state, the blocking portion voltage detection value VR 12  becomes a substantially battery voltage Vbat [V], since the capacitor C 1  of the VR voltage detecting circuit  34 A is charged by current supplied from the battery  27  or the electrolytic capacitor CA (charged to approximately Vbat [V]). On the other hand, the blocking portion voltage detection value VR 22  of the second power source blocking circuit  44 B also becomes a substantially battery voltage Vbat [V], since the capacitor C 1  of the VR voltage detecting circuit  34 B is charged by current supplied from the battery  27  or the electrolytic capacitor CB (charged to approximately Vbat [V]). Thus, the blocking portion voltage detection value VR 12  and the blocking portion voltage detection value VR 22  are in a relationship: “VR 12 ≈VR 22  (≈Vbat)”. 
     When proceeding to step S 3004 , the abnormality detecting unit  31   a  determines that the monitored voltage value (the blocking portion voltage detection value VR) is a normal value, ends the series of processing, and returns to the initial processing. 
     On the other hand, at step S 3002 , when determining that the other blocking portion voltage detection value VR is not larger than the blocking portion voltage detection value VR corresponding to the blocking portions and proceeds to step S 3006 , the abnormality detecting unit  31   a  determines that the monitored voltage value (the blocking portion voltage detection value VR) is an abnormal value, ends the series of processing, and returns to the initial processing. 
     Returning to  FIG. 23 , when proceeding to step S 304 , the abnormality detecting unit  31   a  determines whether or not the check processing of all the power source-side blocking portions has been ended. Then, when determining that it has been ended (Yes), the unit  31   a  proceeds to step S 306 , whereas when determining negatively (No), the unit  31   a  proceeds to step S 300 . 
     In the present embodiment, it is determined whether or not the failure check of step S 302  in both of the first and second power source blocking circuits  44 A and  44 B has been ended. Then, when determined that it has not been ended, failure check of an unchecked power source blocking circuit is executed by the blocking operation patterns depicted in  FIG. 24  and  FIGS. 25A and 25B  until the check is ended. 
     When proceeding to step S 306 , the abnormality detecting unit  31   a  performs motor-side voltage check blocking operation processing and proceeds to step S 308 . 
     Hereinafter, a specific example of the motor-side voltage check blocking operation processing will be described based on  FIG. 27  and  FIGS. 28A and 28B . Here,  FIG. 27  is a circuit diagram in which the circuit diagram of  FIG. 4  is simplified by focusing on voltages to be monitored. Additionally,  FIGS. 28A and 28B  are diagrams depicting blocking portions changed in the circuit diagram of  FIG. 27 . 
     In the present embodiment, FETs for maintaining the charge state of the electrolytic capacitors CA and CB and FETs as objects for detecting a short-circuit failure are put in a blocked state (an OFF state) by a previously set motor-side voltage check blocking operation pattern. 
     Herein, the motor-side voltage check blocking operation pattern is a pattern in which, among the respective FETs of the first and second motor driving circuits  32 A and  32 B, FETs to be blocked are determined so that the charge state of the electrolytic capacitors CA and CB are maintained. In addition, in the pattern, the FETs to be blocked are determined so that a short-circuit failure of the first or second motor current blocking circuit  33 A or  33 B can be checked by the motor phase voltage detection values VA1 to VC1 and VA2 to VC2 that are detection values of monitored voltages. 
     Specifically, in the motor-side voltage check blocking operation pattern in a case of detection of a short-circuit failure of the first motor current blocking circuit  33 A, the FETs QA 1  to QA 3  of the first motor current blocking circuit  33 A are turned OFF (a blocked state) whereas the FETs QB 1  to QB 3  of the second motor current blocking circuit  33 B are turned ON, as depicted in  FIG. 27 . In addition, all of the FETs QC 1  to QC 2  and QD 1  to QD 2  of the first and second power source blocking circuits  44 A and  44 B are turned ON. Furthermore, in the blocking operation pattern, the FETs Q 1 , Q 3 , and Q 5  of the first inverter circuit  42 A are turned OFF; the FETs Q 2 , Q 4 , and Q 6  of the first inverter circuit  42 A are turned ON; and the respective FETs Q 1  to Q 6  of the second inverter circuit  42 B are turned OFF. In addition, all of the FETs QC 1  to QC 2  and QD 1  to QD 2  of the first and second power source blocking circuits  44 A and  44 B may be turned OFF. 
     The blocking operation pattern allows maintaining of the charge state (states charged to the battery voltage Vbat [V]) of the electrolytic capacitors CA and CB of the first and second motor driving circuits  32 A and  32 B. In addition, a short-circuit failure of the first motor current blocking circuit  33 A can be checked by the motor phase voltage detection values VA1 to VC1 and VA2 to VC2 of the motor voltage detecting circuits  40 A and  40 B. Additionally, details of the short-circuit failure check will be described later. 
     Similarly, the motor-side voltage check blocking operation pattern in a case of detection of a short-circuit failure of the second motor current blocking circuit  33 B is as follows. From the blocking operation pattern of  FIG. 27 , the FETs QB 1  to QB 3  are turned OFF (a blocked state), whereas the FETs QA 1  to QA 3  are turned ON, as depicted in  FIG. 28A . In addition, as depicted in  FIG. 28B , in the blocking operation pattern, the FETs Q 2 , Q 4 , and Q 6  of the second inverter circuit  42 B are turned ON, whereas the FETs Q 2 , Q 4 , and Q 6  of the first inverter circuit  42 A are turned OFF. Even in this case, all of the FETs QC 1  to QC 2  and QD 1  to QD 2  of the first and second power source blocking circuits  44 A and  44 B may be turned OFF. 
     The blocking operation pattern allows maintaining of the changed states (states charged to the battery voltage Vbat [V]) of the electrolytic capacitors CA and CB of the first and second motor driving circuits  32 A and  32 B. In addition, short-circuit failure check of the second motor current blocking circuit  33 B can be made by the motor phase voltage detection value VA1 to VC1 and VA2 to VC2 of the motor voltage detecting circuits  40 A and  40 B. Additionally, details of the short-circuit failure check will be described later. 
     Returning to  FIG. 23 , at step S 308 , the abnormality detecting unit  31   a  performs the failure check processing by voltage comparison, and determines whether the monitored voltage value is a normal value or not. Then, when determining that it is a normal value (Yes), the unit  31   a  proceeds to step S 310 , whereas when determining negatively (No), the unit  31   a  proceeds to step S 316 . 
     In the description hereinbelow, when the motor phase voltage detection values VA1 to VC1 of the motor voltage detecting circuit  40 A are not distinguished from each other, the values may be simply referred to as “voltage detection value V1”, and when the motor phase voltage detection value VA2 to VC2 of the motor voltage detecting circuit  40 B are not distinguished from each other, the values may be simply referred to as “voltage detection value V2”. In addition, when the motor phase voltage detection values VA1 to VC1 and VA2 to VC2 are not distinguished from each other, the values may be simply referred to as “voltage detection values VA to VC”. 
     Hereinafter, a specific example of the failure check processing by voltage comparison in the motor-side voltage check blocking operation will be described based on  FIG. 29  to  FIG. 30 . 
     At step S 308 , when the failure check processing by voltage comparison in the motor-side voltage check blocking operation is started, first, the abnormality unit  31   a  proceeds to step S 3100 , as depicted in  FIG. 29 . 
     At step S 3100 , the abnormality detecting unit  31   a  compares magnitudes of the voltage detection values VA to VC of a voltage detecting circuit corresponding to blocking portions and the voltage detection values VA to VC of an other voltage detecting circuit. After that, the unit  31   a  proceeds to step S 3102 . 
     In the present embodiment, the motor driving circuits include the two motor driving circuits: the first and second motor driving circuits  32 A and  32 B. Accordingly, the motor phase voltage detection value VA1 of the motor voltage detecting circuit  40 A is compared with the motor phase voltage detection value VA2 of the motor voltage detecting circuit  40 B. In addition, the motor phase voltage detection value VB1 of the motor voltage detection circuit  40 A is compared with the motor phase voltage detection value VB2 of the motor voltage detecting circuit  40 B. Furthermore, the motor phase voltage detection value VC1 of the motor voltage detecting circuit  40 A is compared with the motor phase voltage detection value VC2 of the motor voltage detecting circuit  40 B. 
     At step S 3102 , the abnormality detecting unit  31   a  determines whether or not all of the voltage detection values VA to VC of the other voltage detecting circuit are larger than, respectively, the voltage detection values VA to VC of the voltage detecting circuit corresponding to the blocking portions. Then, when determining that all thereof are larger than that (Yes), the unit  31   a  proceeds to step S 3104 , whereas determining negatively (No), the unit  31   a  proceeds to step S 3106 . 
     Herein, when all of the FETs QA 1  to QC 1  of the first motor current blocking circuit  33 A are normal, all of the motor phase voltage detection values VA1 to VC1 become ground potential (approximately 0 [V]), since all of the lower arms of the first inverter circuit  42 A are in the ON state. 
     In addition, when a FET in an OFF state is regarded as a resistances by focusing on one phase, it is possible to form an equivalent circuit depicted in  FIG. 30  by the respective FETs of the same phase of the first and second inverter circuits  42 A and  42 B and the respective FETs of the same phase of the first and second motor current blocking circuits  33 A and  33 B. 
     In  FIG. 30 , a resistance RQA is one corresponding to the same phase among the FETs QA 1  to QA 3  in the OFF state of the first motor current blocking circuit  33 A connected to the first inverter circuit  42 A. Additionally, in  FIG. 30 , a resistance RQu 1  is one corresponding to the same phase among the upper arms in the OFF state of the first inverter circuit  42 A connected to the line of the voltage VR 1  depicted in  FIG. 27 . In addition, in  FIG. 30 , a resistance RQu 2  is one corresponding to the same phase among the upper arms in the OFF state of the second inverter circuit  42 B connected to a line of the voltage VR 2  depicted in  FIG. 27 . In addition, in  FIG. 30 , a resistance RQd 2  is one corresponding to the same phase among the lower arms in the OFF state of the second inverter circuit  42 B. In addition, in  FIG. 30 , V1 is one corresponding to the same phase among the motor phase voltage detection values VA1 to VC1, and V2 is one corresponding to the same phase among the motor phase voltage detection values VA2 to VC2. 
     Herein, when the FETs QA 1  to QA 3  of the first motor current blocking circuit  33 A as the blocking performing portions are all normal, the motor phase voltage detection values VA2 to VC2 are all ⅓×VR 2  (≈Vbat) [V] due to a resistance voltage division ratio of the resistances RQu 2 , RQA, and RQd 2 , from the equivalent circuit depicted in  FIG. 30 . 
     Accordingly, the relationships between the voltage detection values of the same phase become magnitude relationships of “VA1&lt;VA2”, “VB1&lt;VB2”, and “VC1&lt;VC2”. 
     On the other hand, when at least one of the FETs QA 1  to QA 3  of the first motor current blocking circuit  33 A as the blocking performing portions is abnormal, the motor phase voltage detection values VA1 to VC1 become all ground potential (approximately 0 [V]) since all of the lower arms of the first inverter circuit  42 A are turned ON and grounded. 
     Additionally, since the motor phase voltage detection values VA2 to VC2 are pulled down via the motor with a relatively low resistance and the FET having a short-circuit failure occurring therein of the FETs QA 1  to QA 3 , all of the values become ground potential (approximately 0 [V]). 
     Accordingly, the relationships between the voltage detection values of the same phase become relationships of “VA1≈VA2 (≈0 [V])”, “VB1≈VB2 (≈0 [V])”, and “VC1≈VC2 (≈0 [V])”. 
     Similarly, in a case in which the FETs QB 1  to QB 3  of the second motor current blocking circuit  33 B are blocking performing portions, when the FETs QB 1  to QB 3  are all normal, all of the motor phase voltage detection values VA2 to VC2 become ground potential (approximately 0 [V]). 
     In addition, all of the motor phase voltage detection values VA1 to VC1 become ⅓×VR 1  (≈Vbat) [V]. 
     Accordingly, the relationships between the voltage detection values of the same phase become magnitude relationships of “VA1&gt;VA2”, “VB1&gt;VB2”, and “VC1&gt;VC2”. 
     On the other hand, when at least one of the FETs QB 1  to QB 3  of the second motor current blocking circuit  33 B as the blocking performing portions is abnormal, all of the motor phase voltage detection values VA2 to VC2 become ground potential (approximately 0 [V]) since all of the lower arms of the second inverter circuit  42 B are turned ON and grounded. 
     In addition, since the motor phase voltage detection values VA1 to VC1 are pulled down via the motor with a relatively low resistance and the FET having a short-circuit failure occurring therein of the FETs QB 1  to QB 3 , all of the values become ground potential (approximately 0 [V]). 
     Accordingly, the relationships between the voltage detection values of the same phase become relationships of “VA1≈VA2 (≈0 [V])”, “VB1≈VB2 (≈0 [V])”, and “VC1≈VC2 (≈0 [V])”. 
     When proceeding to step S 3104 , the abnormality detecting unit  31   a  determines that the monitored voltage value is a normal value, ends the series of processing, and returns to the initial processing. 
     On the other hand, when, at step S 3102 , determining all of the voltage detection values VA to VC of the other motor driving circuit are not larger than, respectively, the voltage detection values VA to VC corresponding to the blocking portions and proceeding to step S 3106 , the abnormality detecting unit  31   a  determines that the monitored voltage values are abnormal values, ends the series of processing, and returns to the initial processing. 
     Returning to  FIG. 23 , when proceeding to step S 310 , the abnormality detecting unit  31   a  determines whether or not check processing of all of the motor current blocking circuits has been ended. Then, when determining that the check processing has been ended (Yes), the unit  31   a  proceeds to step S 312 , whereas when determining negatively (No), the unit  31   a  proceeds to step S 306 . 
     In the present embodiment, it is determined whether the failure check processing of step S 306  in both of the first and second motor current blocking circuits  33 A and  33 B has been ended or not. Then, when determined that it has not been ended, the failure check processing in an unchecked motor current blocking circuit is executed in the blocking operation pattern depicted in  FIG. 27  and  FIGS. 28A and 28B  until the check processing is ended. 
     When proceeding to step S 312 , the abnormality detecting unit  31   a  determines that check results are normal in all the FETs of the first and second power source blocking circuits  44 A and  44 B and the first and second motor current blocking circuits  33 A and  33 B. After that, the unit  31   a  proceeds to step S 314 . 
     At step S 314 , the abnormality detecting unit  31   a  recovers the FETs in the blocked state of the FETs of the first and second power source blocking circuits  44 A and  44 B and the first and second motor current blocking circuits  33 A and  33 B to an energized state. In other words, the abnormality detecting unit  31   a  outputs the abnormality detection signals SAa and SAb of the logical value “0” to the first and second motor driving circuits  32 A and  32 B. After that, the unit  31   a  ends the series of processing and returns to the initial processing. 
     On the other hand, when the monitored voltage value is determined not to be a normal value at step S 302  or S 308  and the processing proceeds to step S 316 , the abnormality detecting unit  31   a  determines that a short-circuit failure is occurring in a motor driving circuit corresponding to a blocking performing portion whose monitored voltage value has been determined not to be a normal value. After that, the unit  31   a  proceeds to step S 318 . 
     At step S 318 , the abnormality detecting unit  31   a  performs failure-coping blocking processing in the motor driving circuit having the short-circuit failure occurring therein. After that, the unit  31   a  ends the series of processing and returns to the initial processing. 
     Specifically, the failure-coping blocking processing is processing that outputs the abnormality detection signals SAa and SAb of the logical value “1” to the motor driving circuit having the short-circuit failure occurring therein of the first and second motor driving circuits  32 A and  32 B. Thereby, the motor driving circuit having the short-circuit failure occurring therein is controlled so that all the FETs thereof are turned OFF. Then, the motor driving circuit is electrically isolated from the battery  27  and the three-phase electric motor  22 . 
     (Operation) 
     Hereinafter, operation of the present embodiment will be described with reference to  FIG. 1  to  FIG. 30 . 
     In an operation stopped state in which since an unillustrated ignition switch is in an OFF state, the vehicle is at a stop and the steering assisting control processing is also at a stop, the control computing device  31  of the motor control device  25  is in an unoperated state. Due to this, the steering assisting control processing and the short-circuit failure detection processing that are executed by the control computing device  31  are stopped. Accordingly, the three-phase electric motor  22  is out of operation, where output of a steering assisting force (a steering assisting torque) to the steering assisting mechanism  20  is stopped. 
     When the ignition switch is turned ON from the operation stopped state, the control computing device  31  goes into an operated state and starts the steering assisting control processing and the short-circuit failure detection processing. At this time, assume that the respective FETs Q 1  to Q 6  of the first and second inverter circuits  42 A and  42 B of the respective first and second motor driving circuits  32 A and  32 B are in a normal state without any an open-circuit failure or a short-circuit failure occurring. In a non-steering state in which the steering wheel  11  is not being steered, the steering torque Ts is “0” and the vehicle speed Vs is also “0” in the steering assisting control processing executed by the control computing device  31 . Thus, from the Ts and the Vs, a steering assisting current command value is calculated by referring to the current command value calculation map of  FIG. 6 . 
     Then, a d-axis current command value Id* and a q-axis current command value Iq* are calculated on the basis of the calculated steering assisting current command value I* and a motor electrical angle θe input from the motor rotation angle detecting circuit  23 . Following that, the calculated d-axis current command value Id* and q-axis current command value Iq* are subjected to dq two-phase to three-phase conversion processing to calculate an A-phase current command value Ia*, a B-phase current command value Ib*, and a C-phase current command value Ic*. 
     Furthermore, there are calculated current deviations ΔIa, ΔIb, and ΔIc between the respective phase current command values Ia*, Ib*, and Ic* and the three-phase motor driving current values Ia, Ib, and Ic calculated from the downstream-side current detection values IA1 to IC1 and IA2 to IC2 of the respective phases detected by the current detecting circuits  39 A 2  to  39 A 4  and  39 B 2  to  39 B 4 . Furthermore, the calculated current deviations ΔIa, ΔIb, and ΔIc are subjected to PI control processing or PID control processing to calculate target voltage command values Va*, Vb*, and Vc* 
     Then, the calculated target voltage command values Va*, Vb*, and Vc* are output as the motor voltage command values V1* and V2* to the first and second gate driving circuits  41 A and  41 B of the first and second motor driving circuits  32 A and  32 B. Additionally, since the first and second inverter circuits  42 A and  42 B are normal, the control computing device  31  outputs the abnormal detection signals SAa and SAb of the logical value “0” to the first and second gate driving circuits  41 A and  41 B. 
     Thus, the first and second gate driving circuits  41 A and  41 B output three high-level gate signals to the first and second motor current blocking circuits  33 A and  33 B. Accordingly, the FETs QA 1  to QA 3  and QB 1  to QB 3  of the first and second motor current blocking circuits  33 A and  33 B are turned ON. Thereby, energization is performed between the first and second inverter circuits  42 A and  42 B and the three-phase motor windings La, Lb, and Lc of the three-phase electric motor  22 , thereby allowing energization control to the three-phase electric motor  22 . 
     Simultaneously with this, high-level gate signals are output from the first and second gate driving circuits  41 A and  41 B to the first and second power source blocking circuits  44 A and  44 B. Due to this, the FETs QC 1  to QC 2  and QD 1  to QD 2  of the first and second power source blocking circuits  44 A and  44 B are turned ON, as a result of which a direct current from the battery  27  is supplied to the first and second inverter circuits  42 A and  42 B via the noise filter  43 . 
     Furthermore, the first and second gate driving circuits  41 A and  41 B perform pulse width modulation on the basis of the motor voltage command values V1* and V2* input from the control computing device  31  to form gate signals. Then, the formed gate signals are supplied to the respective FETs Q 1  to Q 6  of the first and second inverter circuits  42 A and  42 B. 
     Accordingly, in a state where the vehicle is stopped and the steering wheel  11  is not steered, the steering torque Ts is “0” and the vehicle speed Vs is also “0”. Thus, the steering assisting current command value is also “0” and therefore the three-phase electric motor  22  maintains the stopped state. 
     In such a situation, the steering assisting current command value I* is less than the first current threshold value, and the respective phase current command values Ia*, Ib*, and Ic* are less than the second current threshold value. In addition, the three-phase motor driving current values Ia, Ib, and Ic are less than the third current threshold value. 
     Thereby, the abnormality detecting unit  31   a  determines that energization to the motor is unnecessary, and performs failure check processing by voltage comparison. 
     When the failure check processing by voltage comparison is performed, the abnormality detecting unit  31   a  first performs blocking operation processing in the power source-side voltage check blocking operation pattern depicted in  FIG. 24  and  FIGS. 25A and 25B . Then, by comparing magnitudes of the blocking portion voltage detection values VR 12  and VR 22  of the VR voltage detecting circuits  34 A and  34 B at that time, the abnormality detecting unit  31   a  checks a short-circuit failure of a blocking performing portion of the first and second power source blocking circuits  44 A and  44 B. 
     For example, when the first power source blocking circuit  44 A is the blocking performing portion, if the blocking portion voltage detection value VR 22  is larger than the VR 12 , the blocking portion voltage detection values VR 12  and VR 22  are determined to be normal values. In other words, the first power source blocking circuit  44 A is determined to be normal. On the other hand, when the blocking portion voltage detection value VR 22  is not larger than the VR 12  and the blocking portion voltage detection values VR 12  and VR 22  are in a relationship of “VR 12 ≈VR 22 ≈0 [V]”, the blocking portion voltage detection values VR 12  and VR 22  are determined to be abnormal values. In other words, it is determined that a short-circuit failure is occurring in at least one of the FETs QC 1  and QC 2  of the first power source blocking circuit  44 A. 
     When any short-circuit failure is occurring in the first power source blocking circuit  44 A, the abnormality detection signal SAb is maintained to the logical value “0”, whereas the abnormality detection signal SAa becomes the logical value “1”. Due to this, six gate drives of the first inverter circuit  42 A are all turned OFF, and three low-level gate signals are simultaneously output from the first gate driving circuit  41 A of the first motor driving circuit  32 A to the first motor current blocking circuit  33 A. Furthermore, two low-level gate signals are simultaneously output to the first power source blocking circuit  44 A. 
     As a result, in the first motor current blocking circuit  33 A, the FETs QA 1  to QA 3  of the respective phases are turned OFF, whereby energization to the three-phase motor windings La to Lc of the three-phase electric motor  22  is blocked. 
     Simultaneously with this, when in the first power source blocking circuit  44 A also, the FETs QC 1  and QC 2  are controlled to be turned OFF and the QC 1  is normal, an energization path between the battery  27  and the first inverter circuit  42 A is blocked. 
     However, since the second motor driving circuit  32 B is being normally operated, current control to the respective phase motor windings La to Lc of the three-phase electric motor  22  by the second motor driving circuit  32 B can be continued by supply of the motor voltage command value V2* to the second motor driving circuit  32 B. 
     Particularly, the three-phase electric motor  22  can generate the same steering assisting torque as in normal conditions by supplying the motor voltage command value V2* set so that 100 [%] of a necessary motor assisting current is provided by the second motor driving circuit  32 B. Then, the steering assisting torque is transmitted to the output shaft  12   b  via the deceleration gear  21 , whereby steering assisting characteristics comparable to those in normal conditions can be exhibited. At this time, by outputting a warning signal Swa to the warning circuit  50  at a stage where the short-circuit failure of the first power source blocking circuit  44 A has been detected, the occurrence of the short-circuit failure can be reported to the driver to urge the driver to stop by a nearest repair and inspection station. 
     On the other hand, when there is no short-circuit failure in the first and second power source blocking circuits  44 A and  44 B, the motor-side voltage check blocking operation processing is continuously performed. 
     When the motor-side voltage check blocking operation processing is performed, the abnormality detecting unit  31   a  performs blocking operation processing in the motor-side voltage check blocking operation pattern depicted in  FIG. 27  and  FIGS. 28A to 28B . Then, by comparing the magnitudes of the values of the same phase among the motor-phase voltage detection values VA1 to VC1 and VA2 to VC2 of the motor voltage detecting circuits  40 A and  40 B at this time, a short-circuit failure of the blocking performing portion of the first and second motor current blocking circuits  33 A and  33 B is checked. 
     For example, when the first motor current blocking circuit  33 A is the blocking performing portion, if all of the motor phase voltage detection values VA2 to VC2 are larger than the motor phase voltage detection values VA1 to VC1, respectively, the motor phase voltage detection values are determined to be normal values. In other words, the first motor current blocking circuit  33 A is determined to be normal. On the other hand, for example, assume that the motor phase voltage detection values VA2 to VC2 are all not larger than the motor phase voltage detection values VA1 to VC1 and the motor phase voltage detection values VA1 to VC1 and VA2 to VC2 are in a relationship of “VA1≈VA2≈0 [V]”, “VB1≈VB2≈0 [V]”, and “VC1≈VC2≈0 [V]”. In this case, the motor phase voltage detection values are determined to be abnormal values. In other words, at least one of the FETs QA 1  to QA 3  of the first motor current blocking circuit  33 A is determined to have a short-circuit failure. 
     Herein, when there is no occurrence of a short-circuit failure, the abnormality detection signals SAa and SAb are both maintained to the logical value “0”. 
     Thus, the first and second motor driving circuits  32 A and  32 B can perform motor driving in normal conditions. 
     On the other hand, for example, when a short-circuit failure is occurring in the FET QA 1  of the first motor current blocking circuit  33 A, the abnormality detection signal SAa of the logical value “1” is output to the first gate driving circuit  41 A. 
     Thereby, in the first motor current blocking circuit  33 A, the FETs QA 1  to QA 3  of the respective phases are turned OFF and thereby energization to the three-phase motor windings La to Lc of the three-phase electric motor  22  is blocked. 
     Simultaneously with this, in the first power source blocking circuit  44 A also, the FETs QC 1  and QC 2  are controlled to be turned OFF. Then, when either one of the QC 1  or the QC 2  is normal, the energization path between the battery  27  and the first inverter circuit  42 A is blocked. 
     However, since the second motor driving circuit  32 B is being normally operated, current control to the respective phase motor windings La to Lc of the three-phase electric motor  22  by the second motor driving circuit  32 B can be continued by supply of the motor voltage command value V2* to the second motor driving circuit  32 B. 
     Particularly, by supplying the motor voltage command value V2* set so that 100 [%] of a necessary motor assisting current is provided by the second motor driving circuit  32 B, the three-phase electric motor  22  can generate the same steering assisting torque as in normal conditions, and the torque is transmitted to the output shaft  12   b  via the deceleration gear  21 . Thereby, steering assisting characteristics comparable to those in normal conditions can be exhibited. At this time, by outputting the warning signal Swa to the warning circuit  50  at a stage where the short-circuit failure of the first power source blocking circuit  44 A has been detected, the occurrence of the short-circuit failure can be reported to the driver to urge the driver to stop by a nearest repair and inspection station. 
     On the other hand, when a so-called stationary steering is performed by steering the steering wheel  11  in a state where the vehicle is stopped or starts to travel, the steering torque Ts becomes larger, as a result of which the steering assisting current command value I* that is large is calculated by referring to the current command value calculation map of  FIG. 6 . Thereby, the motor voltage command values V1* and V2* that are large according to the calculated steering assisting current command value I* are supplied to the first and second gate driving circuits  41 A and  41 B. Due to this, gate signals having duty ratios according to the large motor voltage command values V1* and V2* are output from the first and second gate driving circuits  41 A and  41 B to the first and second inverter circuits  42 A and  42 B. 
     Accordingly, A-phase motor driving currents I 1   a  and I 2   a , B-phase motor driving currents I 1   b  and I 2   b , and C-phase motor driving currents I 1   c  and I 2   c  having a phase difference of 120 degrees according to the steering assisting current command value I* are output from the first and second inverter circuits  42 A and  42 B. Then, the output motor driving currents pass through the FETs QA 1  to QA 3  and QB 1  to QB 3  corresponding to the respective phases of the first and second motor current blocking circuits  33 A and  33 B and are supplied to the three-phase motor windings La to Lc of the three-phase electric motor  22 . 
     In such a situation, the steering assisting current command value I* is equal to or more than the first current threshold value, and the current command values Ia*, Ib*, and Ic* of the respective phases are equal to or more than the second current threshold value. In addition, the three-phase motor driving current values Ia, Ib, and Ic are equal to or more than the third current threshold value. 
     Thereby, the abnormality detecting unit  31   a  determines that the motor is being energized, and performs failure check processing by current comparison. 
     When the failure check processing by current comparison is performed, the abnormality detecting unit  31   a , first, performs power source-side current check blocking operation processing in the power source-side current check blocking operation pattern depicted in  FIG. 11  and  FIGS. 12A to 12C . Herein, in the power source-side current check blocking operation pattern, energization between the battery  27  and one of the motor driving circuits that includes a blocking performing portion is blocked. Thus, driving of the inverter circuits is controlled so that 100 [%] of a necessary motor assisting current is provided by the other motor driving circuit that does not include the blocking performing portion. 
     Then, on the basis of the upstream-side current detection values IU1 and IU2 of the current detecting circuits  39 A 1  and  39 B 1  at this time, a short-circuit failure of the blocking performing portion of the FETs QC 1  to QC 2  and QD 1  to QD 2  of the first and second power source blocking circuits  44 A and  44 B are checked. 
     For example, when the FET QC 1  of the first power source blocking circuit  44 A is the blocking performing portion, if the upstream-side blocking object current value |IU1| is equal to or less than the upstream-side current threshold value and the upstream-side energizing object current value |IU2| is larger than the |IU1|, it is determined that there is no energization. In other words, the FET QC 1  is determined to be normal. On the other hand, if the upstream-side blocking object current value |IU1| is not equal to or less than the upstream-side current threshold value or the upstream-side energizing object current value |IU2| is equal to or less than the |IU1|, it is determined that there is energization. In other words, it is determined that a short-circuit failure is occurring in the FET QC 1 . 
     Additionally, the control computing device  31  supplies, to the second gate driving circuit  41 B, the motor voltage command value V2* set so that 100 [%] of a necessary motor assisting current is provided by the second motor driving circuit  32 B. Thereby, current control to the respective phase motor windings La to Lc of the three-phase electric motor  22  can be continued. In addition, by generating the same steering assisting torque as in normal conditions by the three-phase electric motor  22 , steering assisting characteristics comparable to those in normal conditions can be exhibited. 
     Herein, when there is no occurrence of a short-circuit failure, the same blocking operation processing and check processing are continued to be performed repeatedly in order of the FETs QC 2 , QD 1 , and QD 2 . 
     In addition, for example, when a short-circuit failure is occurring in the FET QD 1 , the abnormality detection signal SAb of the logical value “1” is output to the second gate driving circuit  41 B, as in the above-described failure check processing by voltage comparison. 
     Thereby, in the second motor current blocking circuit  33 B, the FETs QB 1  to QB 3  of the respective phases are turned OFF, whereby energization to the three-phase motor windings La to Lc of the three-phase electric motor  22  is blocked. 
     Simultaneously with this, in the second power source blocking circuit  44 B also, the FET QD 1  and QD 2  are controlled to be turned OFF. Then, when either one of the QD 1  or the QD 2  is normal, the energization path between the battery  27  and the second inverter circuit  42 B is blocked. 
     However, since the first motor driving circuit  32 A is being normally operated, current control to the respective phase motor windings La to Lc of the three-phase electric motor  22  by the first motor driving circuit  32 A can be continued by supply of the motor voltage command value V1* to the first motor driving circuit  32 A. 
     Particularly, by supplying the motor voltage command value V1* set so that 100 [%] of a necessary motor assisting current is provided by the first motor driving circuit  32 A, the three-phase electric motor  22  can generate the same steering assisting torque as in normal conditions and thereby can exhibit steering assisting characteristics comparable to those in normal conditions. At this time, by outputting a warning signal Swb to the warning circuit  50  at a stage where the short-circuit failure of the second power source blocking circuit  44 B has been detected, the occurrence of the short-circuit failure can be reported to the driver to urge the driver to stop by a nearest repair and inspection station. 
     On the other hand, when there is no occurrence of a short-circuit failure in any of the FETs of the first and second power source blocking circuits  44 A and  44 B, the motor-side current check blocking operation processing is continued to be performed. 
     Herein, when the low-load check mode is set, low-load blocking operation processing is performed in the low-load blocking operation pattern depicted in  FIG. 15  and  FIGS. 16A to 16E . Herein, in the low-load blocking operation pattern, the energization paths to all the phases of the motor are formed by the remaining paths other than a path blocked by one FET selected as a blocking performing portion among the FETs QA 1  to QA 3  and QB 1  to QB 3  of the first and second motor current blocking circuits  33 A and  33 B. Accordingly, driving of the inverter circuits are controlled so that a switching arm connected to a FET of the other motor current blocking circuit connected to a motor winding of the same phase as a phase connected to the FET as the blocking performing portion provides 100 [%] of an assisting current necessary for the phase. As for the other phases, driving of the inverter circuits are controlled so that switching arms connected to motor windings of the same phases of the first and second inverter circuits  42 A and  42 B provide each 50 [%] of an assisting current necessary for each phase. 
     Then, on the basis of the downstream-side current detection values IA1 to IC1 and IA2 to IC2 of the current detecting circuits  39 A 2  to  39 A 4  and  39 B 2  to  39 B 4  at this time, a short-circuit failure of the blocking performing portion of the FETs QA 1  to QA 3  and QB 1  to QB 3  of the first and second motor current blocking circuits  33 A and  33 B is checked. 
     For example, when the FET QA 1  of the first motor current blocking circuit  33 A is the blocking performing portion, if the downstream-side blocking object current value is equal to or less than the downstream-side current threshold value and the downstream-side energizing object current value |IA2| is larger than the downstream-side blocking object current value it is determined that there is no energization. In other words, the FET QA 1  is determined to be normal. On the other hand, if the absolute value of the downstream-side current detection value IA1 is not equal to or less than the downstream-side current threshold value or the downstream-side energizing object current value |IA2| is equal to or less than the downstream-side blocking object current value |IA1|, it is determined that there is energization. In other words, it is determined that a short-circuit failure is occurring in the FET QA 1 . 
     Additionally, the control computing device  31  sets the target voltage command value Va* of the A phase so that the switching arm SWBa of the second inverter circuit  42 B provides 100 [%] of a motor assisting current that is to be supplied to the A-phase motor winding La to which the FET QA 1  as the blocking performing portion is connected. In addition, the control computing device  31  sets the target voltage command values Vb* and Vc* of the B phase and the C phase so that the switching arms SWBb and SWBc of the second inverter circuit  42 B supply 50 [%] of motor assisting currents that are to be supplied to the B phase and the C phase. Then, the motor voltage command value V2* including these set command values is supplied to the second gate driving circuit  41 B. 
     In addition, the control computing device  31  supplies, to the first gate driving circuit  41 A, the motor voltage command value V1* in which the Va*, the Vb*, and the Vc* are set so that the first inverter circuit  42 A provides 50 [%] of an assisting current amount that is to be supplied to the respective phase motor windings. 
     Thereby, current control to the respective phase motor windings La to Lc of the three-phase electric motor  22  can be continued. In addition, by generating the same steering assisting torque as in normal conditions by the three-phase electric motor  22 , steering assisting characteristics comparable to those in normal conditions can be exhibited. 
     In this manner, with the low-load check mode, only any one of the switching arms of the first and second inverter circuits  42 A and  42 B is caused to provide 100 [%] of a motor assisting current. Thus, as compared to simultaneous check of the plurality of FETs, a load applied to the inverter circuits can be reduced. 
     Herein, when there is no occurrence of a short-circuit failure, the same blocking operation processing and check processing are continued to be repeatedly performed in order of the FET QA 2 , QA 3 , QB 1 , QB 2 , and QB 3 . 
     In addition, when the first high-speed check mode is set, first high-speed blocking operation processing is performed in the first high-speed blocking operation pattern depicted in  FIG. 17  and  FIG. 18 . Herein, in the first high-speed blocking operation pattern, energization between one of the motor driving circuits that includes a blocking performing portion and the three-phase electric motor  22  is blocked. Thus, driving of the circuits are controlled so that the other motor driving circuit that does not include the blocking performing portion provides 100 [%] of a necessary motor assisting current. In other words, all of the three blocking FETs of anyone of the first and second motor current blocking circuits  33 A and  33 B of the first and second motor driving circuits  32 A and  32 B are blocking performing portions. 
     Then, on the basis of the downstream-side current detection values IA1 to IC1 and IA2 to IC2 of the current detecting circuits  39 A 2  to  39 A 4  and  39 B 2  to  39 B 4  at this time, a short-circuit failure of the blocking performing portions of the FETs QA 1  to QA 3  and QB 1  to QB 3  of the first and second motor current blocking circuits  33 A and  33 B are checked. 
     For example, when the FETs QA 1  to QA 3  of the first motor current blocking circuit  33 A are the blocking performing portions, if the downstream-side blocking object current values |IA1| to |IC1| are all equal to or less than the downstream-side current threshold value and, when compared between the values of the same phase, the downstream-side energizing object current values |IA2| to |IC2| are all larger than the downstream-side blocking object current values |IA1| to |IC1|, respectively, it is determined that there is no energization. In other words, the FETs QA 1  to QA 3  are determined to be normal. On the other hand, if any of the absolute values of the downstream-side current detection values IA1 to IC1 is not equal to or less than the downstream-side current threshold value or, when compared between the values of the same phase, any of the downstream-side energizing object current values |IA2| to |IC2| is equal to or less than the absolute value of any of the downstream-side blocking object current values |IA| to |IC1|, it is determined that there is energization. In other words, it is determined that a short-circuit failure is occurring in any of the FETs QA 1  to QA 3 . 
     Additionally, the control computing device  31  supplies, to the second gate driving circuit  41 B, the motor voltage command value V2* set so that the second motor driving circuit  32 B provides 100 [%] of a necessary motor assisting current. Thereby, current control to the respective phase motor windings La to Lc of the three-phase electric motor  22  can be continued. In addition, by generating the same steering assisting torque as in normal conditions by the three-phase electric motor  22 , steering assisting characteristics comparable to those in normal conditions can be exhibited. 
     Herein, when there is no occurrence of a short-circuit failure, the same blocking operation processing and check processing are continued to be performed by using the FETs QB 1  to QB 3  of the second motor current blocking circuit  33 B as the blocking performing portions. 
     In this manner, with the first high-speed check mode, each three FETS of the first and second motor current blocking circuits  33 A and  33 B can be checked together, so that check processing time can be reduced as compared to check of each one FET thereof. 
     In addition, when the second high-speed check mode is set, second high-speed check operation processing is performed in the second high-speed blocking operation pattern depicted in  FIG. 19  and  FIGS. 20A to 20C . Herein, in the second high-speed blocking operation pattern, energization paths to all the phases of the motor are formed by remaining paths other than paths blocked by three FETs selected as blocking performing portions from both of the first and second motor current blocking circuits  33 A and  33 B. Accordingly, driving of the inverter circuits are controlled so that switching arms connected to FETs of an other motor current blocking circuit connected to motor windings of the same phase as a phase to which the FETs as the blocking performing portions are connected are caused to be responsible for supplying 100 [%] of assisting current necessary for the phase. In other words, one FET to be blocked of any one of the first and second motor current blocking circuits  33 A and  33 B of the first and second motor driving circuits  32 A and  32 B and two FETs to be blocked of the other one of the first and second motor current blocking circuits  33 A and  33 B are used as blocking performing portions. 
     Then, on the basis of the downstream-side current detection values IA1 to IC1 and IA2 to IC2 of the current detecting circuits  39 A 2  to  39 A 4  and  39 B 2  to  39 B 4  at this time, a short-circuit failure of the blocking performing portions of the FETs QA 1  to QA 3  and QB 1  to QB 3  of the first and second motor current blocking circuits  33 A and  33 B are checked. 
     For example, assumed that the blocking portions are a combination of the FET QA 1  of the first motor current blocking circuit  33 A and the two FETs QB 2  and QB 3  of the second motor current blocking circuit  33 B. In this case, when the downstream-side blocking object current values |IA1|, |IB2|, and |IC2| are equal to or less than the downstream-side current threshold value and a relationship between the downstream-side blocking object current values and downstream-side energizing object current values is a relationship of “|IA1|&lt;|IA2|”, “|IB1|&gt;|IB2|”, and “|IC1|&gt;|IC2|”, it is determined that there is no energization. In other words, the FETs QA 1 , QB 2 , and QB 3  are determined to be normal. On the other hand, when the downstream-side blocking object current values |IA1|, |IB2|, and |IC2| are not equal to or less than the downstream-side current threshold value or the relationship between the downstream-side blocking object current values and downstream-side energizing object current values is not the relationship of “|IA1|&lt;|IA2|”, “|IB1|&gt;|IB2|”, and “|IC1|&gt;|IC2|”, it is determined that there is energization. In other words, it is determined that a short-circuit failure is occurring in any of the FETs QA 1 , QB 2 , and QB 3 . 
     In addition, the control computing device  31  sets the target voltage command values Vb* and Vc* of the B phase and the C phase so that the switching arms SWAb and SWAc of the first inverter circuit  42 A supply 100 [%] of motor assisting currents that are to be supplied to the B-phase and C-phase motor windings Lb and Lc to which the FETs QB 2  and QB 3  as the blocking performing portions are connected. Then, the motor voltage command value V1* including these set command values is supplied to the first gate driving circuit  41 A. 
     On the other hand, the control computing device  31  sets the target voltage command value Va* of the A phase so that the switching arm SWBa of the second inverter circuit  42 B supplies 100 [%] of a motor assisting current that is to be supplied to the A-phase motor winding La. Then, the motor voltage command value V2* including the set command value is supplied to the second gate driving circuit  41 B. 
     Thereby, current control to the respective phase motor windings La to Lc of the three-phase electric motor  22  can be continued. In addition, by generating the same steering assisting torque as in normal conditions by the three-phase electric motor  22 , steering assisting characteristics comparable to those in normal conditions can be exhibited. 
     In this manner, with the second high-speed check mode, each three FETs of the first and second motor current blocking circuits  33 A and  33 B can be checked together. Thus, check processing time can be reduced as compared to check of each one of the FETs. 
     As a result of check by setting any one of the above check modes, when there is no occurrence of a short-circuit failure in any of the FETs of the first and second motor current blocking circuits  33 A and  33 B, the first and second power source blocking circuits  44 A and  44 B and the first and second motor current blocking circuits  33 A and  33 B are determined to be all normal. After that, blocking operation is cancelled, and operation proceeds to normal steering assisting control processing. 
     Herein, the first and second motor current blocking circuits  33 A and  33 B correspond to motor current blocking units; the current detecting circuits  39 A 1  and  39 B 1  correspond to current detecting unit and upstream-side current detecting units; and the abnormality detecting unit  31   a  corresponds to an abnormality detecting unit, a first abnormality detecting unit, and a second abnormality detecting unit. 
     Additionally, the current detecting circuits  39 A 2  to  39 A 4  and  39 B 2  to  39 B 4  correspond to current detecting units and downstream-side current detecting units. 
     Additionally, the first and second power source blocking circuits  44 A and  44 B correspond to power source blocking units; the motor voltage detecting circuits  40 A and  40 B correspond to phase voltage detecting units; and the VR voltage detecting circuits  34 A and  34 B correspond to blocking portion voltage detecting units. 
     Advantageous Effects of Embodiments 
     (1) The first and second motor driving circuits  32 A and  32 B receive power supplied from the battery  27  and are operated to supply three-phase motor driving currents Ia, Ib, and Ic to the three-phase motor windings La to Lc of the three-phase electric motor  22 . The control computing device  31  controls driving of the first and second motor driving circuits  32 A and  32 B. The first and second motor current blocking circuits  33 A and  33 B are individually interposed between the first and second motor driving circuits  32 A and  32 B and the three-phase motor windings La, Lb, and Lc, and in blocking operation, individually block energization between the first and second motor driving circuits  32 A and  32 B and the three-phase motor windings La, Lb, and Lc. The current detecting circuits  39 A 2  to  39 A 4  and  39 B 1  to  39 B 4  individually detect currents flowing to a downstream side (downstream-side current detection signals IA1 to IC1 and IA2 to IC2) of the first and second inverter circuits  42 A and  42 B of the first and second motor driving circuits  32 A and  32 B. The abnormality detecting unit  31   a  detects a short-circuit failure of the first and second motor current blocking circuits  33 A and  33 B on the basis of current values (the downstream-side current detection values IA1 to IC1 and IA2 to IC2) of the currents detected by the current detecting circuits  39 A 2  to  39 A 4  and  39 B 2  to  39 B 4 . The abnormality detecting unit  31   a  causes one or more of the FETs QA 1  to QA 3  and QB 1  to QB 3  of the first and second motor current blocking circuits  33 A and  33 B to perform a blocking operation during the energization between the first and second motor driving circuits  32 A and  32 B and the three-phase electric motor  22 , and, during the blocking operation, detects a short-circuit failure of the one or more FETs caused to perform the blocking operation of the FETs QA 1  to QA 3  and QB 1  to QB 3 , on the basis of the downstream-side current detection values IA1 to IC1 and IA2 to IC2 of the current detecting circuits  39 A 2  to  39 A 4  and  39 B 2  to  39 B 4 . 
     With this configuration, when one or more of the FETs QA 1  to QA 3  and QB 1  to QB 3  of the first and second motor current blocking circuits  33 A and  33 B are caused to perform a blocking operation, a short-circuit failure of the FETs caused to perform the blocking operation can be detected on the basis of the downstream-side current detection values IA1 to IC1 and IA2 to IC2 of the first and second inverter circuits  42 A and  42 B. 
     Herein, the blocking portion(s) of the FETs QA 1  to QA 3  and QB 1  to QB 3 , when the portion(s) is (are) normal, block(s) energization to a phase(s) connected to the blocking portion(s) among the three-phase motor windings La to Lc. Thus, the downstream-side current detection value(s) corresponding to the blocked phase (s) is (are) 0 [A]. On the other hand, when a short-circuit failure is occurring in the blocking portion(s), the downstream-side current detection value(s) corresponding to the blocked phase(s) is(are) not 0 [A]. Additionally, in the pairs of the downstream-side current detection values of the same phases, i.e. IA1 and IA2, IB1 and IB2, and IC1 and IC2 of the first and second inverter circuits  42 A and  42 B, when one of the pair is in a blocked state and when the blocking portion is normal, the downstream-side current detection value of the one of the pair is 0 [A]. Thus, the current detection value of the other one of the pair is larger than the value of the one of the pair. 
     In this manner, a short-circuit failure of a blocking portion can be detected by whether or not a downstream-side current detection value corresponding to the blocking portion become 0 [A] and whether or not, in the magnitude relationships between the downstream-side current detection values IA1 and IA2, IB1 and IB2, and IC1 and IC2 of the same phases, a detection value corresponding to an energizing portion is larger than the detection value corresponding to the blocking portion. 
     As a result of that, when compared with the conventional configuration for detecting a short-circuit failure by detection of reduction in a motor phase voltage, a short-circuit failure of the first and second motor current blocking circuits  33 A and  33 B can be more surely detected while the three-phase electric motor  22  is driving. 
     (2) The abnormality detecting unit  31   a  causes one or more FETs of the FETs QA 1  to QA 3  and QB 1  to QB 3  of the first and second motor current blocking circuits  33 A and  33 B to perform a blocking operation so that energization to all the phases of the three-phase electric motor  22  is maintained, and performs processing for detecting a short-circuit failure. 
     Examples of possible blocking operation patterns include a blocking operation pattern in which only the FET QA 1  is caused to perform a blocking operation, whereas all the other FETs are caused to perform an energizing operation and a blocking operation pattern in which all the FETs of one of the motor current blocking circuits are caused to perform a blocking operation, whereas all the FETs of the other one thereof are caused to perform an energizing operation. Other than those, there is also a possible blocking operation pattern in which three FETs in total including one FET of one of the motor current blocking circuits and two FETs of the other one thereof that are of phases different from a phase of the one FET are caused to perform a blocking operation, whereas the other FETs are caused to perform an energizing operation. 
     With this configuration, even during short-circuit failure detection processing, the three-phase electric motor  22  can be driven, so that driving of the three-phase electric motor can be continued without intermission. Herein, since the three-phase electric motor  22  is a motor for assisting steering of the electric power steering device  3 , motor assistance can be continuously performed even during short-circuit failure detection processing. As a result of that, it is possible to prevent the occurrence of an uncomfortable steering feeling due to discontinuation of motor assistance. 
     (3) There are provided the first and second power source blocking circuits  44 A and  44 B individually interposed between the battery  27  and the first and second inverter circuits  42 A and  42 B of the first and second motor driving circuits  32 A and  32 B. The first and second power source blocking circuits  44 A and  44 B individually block energization between the battery  27  and the first and second inverter circuits  42 A and  42 B in blocking operation. The abnormality detecting unit  31   a  detects a short-circuit failure of the first and second power source blocking circuits  44 A and  44 B on the basis of current values (upstream-side current detection values) IU1 and IU2 of currents detected by the current detecting circuits  39 A 1  and  39 B 1 . The abnormality detecting unit  31   a  causes one or more of the FETs QC 1  to QC 2  and QD 1  to QD 2  of the first and second power source blocking circuits  44 A and  44 B to perform a blocking operation during energization between the first and second motor driving circuits  32 A and  32 B and the three-phase electric motor  22 . Along with this, during the blocking operation, the abnormality detecting unit  31   a  detects a short-circuit failure of the one or more FETs of the first and second power source blocking circuits  44 A and  44 B caused to perform the blocking operation, on the basis of the upstream-side current detection values IU1 and IU2 of the current detecting circuits  39 A 1  and  39 B 1 . 
     Herein, when a FET as a blocking portion of the FETs QC 1  to QC 2  and QD 1  to QD 2  is normal, energization between the motor driving circuit to which the power source blocking circuit including the FET is connected and the battery  27  is blocked. Due to this, the upstream-side current detection value flowing to the motor driving circuit from the battery  27  becomes 0 [A]. On the other hand, when a short-circuit failure is occurring in the blocking portion, there is energization between the motor driving circuit to which the power source blocking circuit including the FET is connected and the battery  27 . Accordingly, since electric current is supplied to the motor driving circuit from the battery  27 , the upstream-side current detection value is not 0 [A]. In addition, in the upstream-side current detection values IU1 and IU2, when the FET as the blocking portion is normal, the upstream-side current detection value of the one motor driving circuit to which the power source blocking circuit including the blocking portion is connected becomes 0 [A]. Thus, the upstream-side current detection value of the other motor driving circuit becomes larger than that. 
     In this manner, a short-circuit failure of a blocking portion can be detected by whether or not an upstream-side current detection value corresponding to the blocking portion is 0 [A] and whether or not upstream-side current detection value corresponding to an energizing portion is larger than the upstream-side current detection value corresponding to the blocking portion. 
     As a result of that, when compared to the conventional configuration for detecting a short-circuit failure by detection of voltage reduction in an upper-stage wiring of the inverter circuit, for example, even in a case in which a smoothing capacitor for noise removal is arranged in the inverter circuit side from the power source blocking circuit, it is possible to more surely detect a short-circuit failure of the first and second power source blocking circuits  44 A and  44 B while the three-phase electric motor  22  is driving. 
     (4) The abnormality detecting unit  31   a  causes one or more of the FETs QC 1  to QC 2  and QD 1  to QD 2  to perform a blocking operation so that energization to all the phases of the three-phase electric motor  22  is maintained, and performs short-circuit failure check processing. 
     This configuration enables the three-phase electric motor  22  to be driven even during short-circuit failure detection processing, so that the driving of the three-phase electric motor can be continued without intermission. As a result, it is possible to prevent the occurrence of an uncomfortable steering feeling due to discontinuation of motor assistance. 
     (5) The control computing device  31  controls the first and second motor driving circuits  32 A and  32 B to supply a plurality of three-phase motor driving currents to the three-phase motor windings La, Lb, and Lc when the motor control device  25  is normal. When the abnormality detecting unit  31   a  detects a short-circuit failure, the control computing device  31  stops driving of a motor driving circuit connected to a power source blocking circuit or a motor current blocking circuit in which the short-circuit failure is occurring, as well as causes all the FETs of the power source blocking circuit and the motor current blocking circuit connected to the motor driving circuit to perform a blocking operation and continues supply of three-phase motor driving currents through the other normal one of the motor driving circuits. 
     With this configuration, when a short-circuit failure occurs in either one of the first or second motor current blocking circuit  33 A or  33 B, one of the first and second motor driving circuits  32 A and  32 B to which the motor current blocking circuit having the short-circuit failure occurring therein is connected can be isolated from the battery  27  and the three-phase electric motor  22 . In addition, energization to the three-phase electric motor  22  can be continued by the other motor driving circuit without any short-circuit failure occurring. As a result of that, the occurrence of an uncomfortable steering feeling due to discontinuation of motor assistance can be prevented. 
     (6) The abnormality detecting unit  31   a  determines whether or not energization between the first and second motor driving circuits  32 A and  32 B and the three-phase electric motor  22  is necessary on the basis of the steering assisting current command value I* computed by the control computing device  31  and the current values (the three-phase motor driving current values Ia, Ib, and Ic) of currents flowing through the respective phases of the three-phase electric motor  22 . Alternatively, the abnormality detecting unit  31   a  determines whether or not there is energization between the first and second motor driving circuits  32 A and  32 B and the three-phase electric motor  22 . Then, when determining that energization is necessary or there is energization, the abnormality detecting unit  31   a  performs processing for detecting a short-circuit failure of the first and second power source blocking circuits  44 A and  44 B. 
     This configuration enables processing for detecting a short-circuit failure of the first and second power source blocking circuits  44 A and  44 B based on the three-phase motor driving current values Ia, Ib, and Ic at a timing when there is energization between the first and second motor driving circuits  32 A and  32 B and the three-phase electric motor  22 . Thereby, detection of a short-circuit failure of the first and second power source blocking circuits  44 A and  44 B can be more surely performed. 
     (7) The abnormality detecting unit  31   a  determines whether or not energization between the first and second motor driving circuits  32 A and  32 B and the three-phase electric motor  22  is necessary or whether or not there is energization between the first and second motor driving circuits  32 A and  32 B and the three-phase electric motor  22 , on the basis of the steering assisting current command value I* computed by the control computing device  31  and the motor driving current values Ia, Ib, and Ic of currents flowing through the respective phases of the three-phase electric motor. Then, when determining that energization is necessary or there is energization, the abnormality detecting unit  31   a  performs processing for detecting a short-circuit failure of the first and second motor current blocking circuits  33 A and  33 B. 
     This configuration enables processing for detecting a short-circuit failure of the first and second motor current blocking circuits  33 A and  33 B based on the three-phase motor driving current values Ia, Ib, and Ic at a timing when there is energization between the first and second motor driving circuits  32 A and  32 B and the three-phase electric motor  22 . Thereby, detection of a short-circuit failure of the first and second motor current blocking circuits  33 A and  33 B can be more surely performed. 
     (8) The first and second motor driving circuits  32 A and  32 B include the first and second inverter circuits  42 A and  42 B provided with the switching arms SWAa, SWAb, SWAc, SWBa, SWBb, and SWBc corresponding to the number of phases of the three-phase electric motor  22  that supply the three-phase motor driving currents Ia, Ib, and Ic to the three-phase electric motor. The switching arms SWAa, SWAb, SWAc, SWBa, SWBb, and SWBc include the upper arms (FETs Q 1 , Q 3 , and Q 5 ) and the lower arms (FETs Q 2 , Q 4 , and Q 6 ). The current detecting circuits  39 A 1  and  39 B 1  are individually interposed between the first and second power source blocking circuits  44 A and  44 B and the upper arms to detect a current that flows from the battery  27  to the upper arms. The abnormality detecting unit  31   a  acquires an upstream-side blocking object current value detected by the current detecting circuits  39 A 1  and  39 B 1 , which is the current value of a current flowing through the upper arms of an inverter circuit to which a power source blocking circuit caused to perform a blocking operation is connected. In addition, the abnormality detecting circuit  31   a  acquires an upstream-side energizing object current value that is the current value of a current flowing through the upper arms of an other inverter circuit to which a power source blocking circuit caused to perform an energizing operation is connected. Then, the abnormality detecting circuit  31   a  detects a short-circuit failure of the power source blocking unit caused to perform the blocking operation, on the basis of, of the upstream-side blocking object current value and the upstream-side energizing object current value, at least the upstream-side blocking object current value. 
     Herein, as described in the above (3), the upstream-side blocking object current value (IU1 or IU2) becomes 0 [A] when the FET as the blocking portion (any of the FETs QC 1  to QC 2  and QD 1  to QD 2 ) is normal. Additionally, when the FET as the blocking portion is normal, the upstream-side blocking object current value is larger when compared between the upstream-side blocking object current value (one of the IU1 and the IU2) and the upstream-side energizing object current value (an other one of the IU1 and the IU2). 
     Accordingly, this configuration enables a short-circuit failure of a blocking portion to be detected on the basis of at least the upstream-side blocking object current value, such as whether or not the upstream-side blocking object current value is 0 [A] or whether or not the upstream-side energizing object current value is larger than the upstream-side blocking object current value. 
     As a result of that, when compared to the conventional configuration for detecting a short-circuit failure by detecting voltage reduction of an upper-stage wiring of the inverter circuit, for example, even in a configuration in which a smoothing capacitor for noise removal is arranged in an inverter circuit side from the power source blocking circuit, a short-circuit failure of the first and second power source blocking circuits  44 A and  44 B can be more surely detected while the three-phase electric motor  22  is driving. 
     (9) The first and second motor driving circuits  32 A and  32 B include the first and second inverter circuits  42 A and  42 B provided with the switching arms SWAa, SWAb, SWAc, SWBa, SWBb, and SWBc corresponding to the number of phases of the three-phase electric motor  22  that supply the three-phase motor driving currents Ia, Ib, and Ic to the three-phase electric motor. The switching arms SWAa, SWAb, SWAc, SWBa, SWBb, and SWBc include the upper arms (FETs Q 1 , Q 3 , and Q 5 ) and the lower arms (FETs Q 2 , Q 4 , and Q 6 ). The current detecting circuits  39 A 2  to  39 A 4  and  39 B 2  to  39 B 4  are individually interposed between the lower arms of the first and second inverter circuits  42 A and  42 B and grounds to individually detect currents that flow from the lower arms to the grounds (downstream-side current detection values IA1 to IC1 and IA2 to IC2). The abnormality detecting unit  31   a  acquires downstream-side blocking object current values detected by the current detecting circuits  39 A 2  to  39 A 4  and  39 B 2  to  39 B 4 , which are the current values of currents flowing to the grounds from the lower arms of the same phases as the motor current blocking circuit of an inverter circuit to which the motor current blocking circuit caused to perform the blocking operation is connected. In addition, the abnormality detecting unit  31   a  acquires downstream-side energizing object current values that are the current values of currents flowing to the grounds from the lower arms of the same phase as the lower arms corresponding to the downstream-side blocking object current values of the other inverter circuit to which a motor current blocking circuit caused to perform an energizing operation is connected. Then, the abnormality detecting unit  31   a  detects a short-circuit failure of the motor current blocking circuit caused to perform the blocking operation, on the basis of, of the downstream-side blocking object current values and the downstream-side energizing object current values, at least the downstream-side blocking object current values. 
     Herein, as described in the above (1), when the FET as a blocking portion (any of the FETs QA 1  to QA 3  and QB 1  to QB 3 ) is normal, the downstream-side blocking object current value (any of IA1 to IC1 and IA2 to IC2) becomes 0 [A]. Additionally, when the FET as the blocking portion is normal, the downstream-side energizing object current value is larger than the downstream-side blocking object current value. 
     Accordingly, this configuration enables a short-circuit failure of a blocking portion to be detected by whether or not the downstream-side blocking object current value is 0 [A]. In addition, in the magnitude relationship between the downstream-side blocking object current value (either one of IA1 and IA2, IB1 and IB2, and IC1 and IC2) and the downstream-side energizing object current value (either other one of IA1 and IA2, IB1 and IB2, and IC1 and IC2), depending on whether or not the downstream-side energizing object current value is larger than the downstream-side blocking object current value, it is possible to detect the short-circuit failure of the blocking portion. 
     As a result of that, when compared to the conventional configuration for detecting a short-circuit failure by detecting reduction of a motor phase voltage, a short-circuit failure of the first and second motor current blocking circuits  33 A and  33 B can be more surely detected while the three-phase electric motor  22  is driving. 
     (10) The first and second motor driving circuits  32 A and  32 B receive power supplied from the battery  27  and are operated to supply the three-phase motor driving currents Ia, Ib, and Ic to the three-phase motor windings La to Lc of the three-phase electric motor  22 . The control computing device  31  controls driving of the first and second motor driving circuits  32 A and  32 B. The first and second motor current blocking circuits  33 A and  33 B of the three phases are individually interposed between the first and second inverter circuits  42 A and  42 B of the first and second motor driving circuits  32 A and  32 B and the three-phase motor windings La, Lb, and Lc. The first and second motor current blocking circuits  33 A and  33 B individually block energization between the first and second inverter circuits  42 A and  42 B and the three-phase motor windings La, Lb, and Lc in blocking operation. The motor voltage detecting circuits  40 A and  40 B individually detect motor phase voltage detection values VA1 to VC1 and VA2 to VC2 that are voltages between connection points of the respective upper arms and lower arms of the first and second inverter circuits  42 A and  42 B and connection points of the respective FETs QA 1  to QA 3  and QB 1  to QB 3  of the first and second motor current blocking circuits  33 A and  33 B. The abnormality detecting unit  31   a  detects a short-circuit failure of the first and second motor current blocking circuits  33 A and  33 B on the basis of the motor phase voltage detection values VA1 to VC1 and VA2 to VC2 of the motor voltage detecting circuits  40 A and  40 B. The abnormality detecting unit  31   a  operates the control computing device  31  so that the first and second inverter circuits  42 A and  42 B and the three-phase electric motor  22  are put in a non-energized state. Along with this, one or more of the FETs QA 1  to QA 3  and QB 1  to QB 3  of the first and second motor current blocking circuits  33 A and  33 B are caused to perform a blocking operation during the non-energized state. Then, during the blocking operation, a short-circuit failure of the one or more FETs caused to perform the blocking operation are detected on the basis of the motor phase voltage detection values VA1 to VC1 and VA2 to VC2 detected by the motor voltage detecting circuits  40 A and  40 B. 
     For example, in a situation where energization to the three-phase electric motor  22  is unnecessary or there is no energization, no determination can be made as to the presence or absence of energization. With this configuration, the upper arms and lower arms of the first and second inverter circuits  42 A and  42 B are blocked so that the first and second inverter circuits  42 A and  42 B and the three-phase electric motor  22  are put in the non-energized state in the situation where energization is unnecessary or there is no energization. In addition, by blocking the FETs as objects to be checked of the first and second motor current blocking circuits  33 A and  33 B, a short-circuit failure of the first and second motor current blocking circuits  33 A and  33 B can be detected on the basis of the motor phase voltage detection values VA1 to VC1 and VA2 to VC2 of the motor voltage detecting circuits  40 A and  40 B at this time. 
     As a result of that, a short-circuit failure of the first and second motor current blocking circuits  33 A and  33 B can be detected in the situation where energization to the three-phase electric motor  22  is unnecessary or there is no energization. 
     (11) There are provided electrolytic capacitors CA and CB individually interposed between connection lines of the first and second motor driving circuits  32 A and  32 B and the battery  27  and ground lines. The abnormality detecting unit  31   a  operates the control computing device  31  so that the charge state of the electrolytic capacitors CA and CB are maintained, causes one or more of the FETs QA 1  to QA 3  and QB 1  to QB 3  to perform a blocking operation, and performs processing for short-circuit failure detection. 
     With this configuration, even when the electrolytic capacitors CA and CB having a relatively large capacity are interposed to remove noise, the charge state of the electrolytic capacitors CA and CB can be maintained in performing processing for short-circuit failure detection. As a result of that, when performing a blocking operation involving discharge of the electrolytic capacitors CA and CB, an energization response delay occurring at a time of restart of energization due to the discharge can be prevented. Consequently, this can prevent an uncomfortable steering feeling from occurring due to the energization response delay. 
     (12) The first and second motor driving circuits  32 A and  32 B are formed by including the first and second inverter circuits  42 A and  42 B provided with the switching arms SWAa, SWAb, SWAc, SWBa, SWBb, and SWBc corresponding to the number of the phases of the three-phase electric motor  22  that supply three-phase motor driving currents Ia, Ib, and Ic to the three-phase electric motor. The switching arms SWAa, SWAb, SWAc, SWBa, SWBb, and SWBc include the upper arms (FETs Q 1 , Q 3 , and Q 5 ) and the lower arms (FETs Q 2 , Q 4 , and Q 6 ). The motor voltage detecting circuits  40 A and  40 B are individually interposed between connection points of the upper arms and lower arms of the respective phases of the first and second inverter circuits  42 A and  42 B and the three-phase motor windings La, Lb, and Lc and individually detect voltages of the connection points as the motor phase voltage detection values VA1 to VC1 and VA2 to VC2. The abnormality detecting unit  31   a  turns OFF all of the upper arms of the inverter circuit to which the motor current blocking circuit as a short-circuit failure detection object is connected and turns ON all of the lower arms thereof, whereas it turns OFF all of the upper arms and lower arms of the inverter circuit to which the motor current blocking circuit as an energizing object is connected. Thereby, the first and second inverter circuits  42 A and  42 B and the three-phase electric motor  22  are put in a non-energized state. In addition, during the non-energized state, all of the FETs of the motor current blocking circuit as the short-circuit failure detection object connected to either one of the first and second inverter circuits  42 A and  42 B are caused to perform a blocking operation. Furthermore, during the blocking operation, a short-circuit failure of the motor current blocking circuit caused to perform the blocking operation is detected on the basis of the motor phase voltage detection values VA1 to VC1 and VA2 to VC2 detected by the motor voltage detecting circuits  40 A and  40 B. 
     With this configuration, for example, in a case in which the FETs QA 1  to QA 3  of the first motor current blocking circuit  33 A are caused to perform a blocking operation, when the FETs are all normal, the motor phase voltage detection values VA1 to VC1 become all approximately 0 [V]. On the other hand, the motor phase voltage detection values VA2 to VC2 become ⅓×VR 2  (≈Vbat [V]) from the relationship of the equivalent circuit depicted in  FIG. 30 . Additionally, if a short-circuit failure occurs even in any one of the FETs QA 1  to QA 3 , the motor phase voltage detection values VA2 to VC2 are pulled down via the motor and therefore all thereof become approximately 0 [V]. 
     Accordingly, detection of a short-circuit failure can be made by the magnitude relationship between the motor phase voltage detection values VA1 to VC1 and motor phase voltage detection values VA2 to VC2. As a result of that, a short-circuit failure of the motor current blocking circuit can be more surely detected in the situation where energization is unnecessary or there is no energization. 
     (13) There are provided the first and second power source blocking circuits  44 A and  44 B individually interposed between the battery  27  and the first and second inverter circuits  42 A and  42 B of the first and second motor driving circuits  32 A and  32 B. The first and second power source blocking circuits  44 A and  44 B individually block energization between the battery  27  and the first and second inverter circuits  42 A and  42 B in blocking operation. The VR voltage detecting circuits  34 A and  34 B detect the voltages VR 12  and VR 22  generated in the first and second power source blocking circuits  44 A and  44 B. The abnormality detecting unit  31   a  detects a short-circuit failure of the first and second power source blocking circuits  44 A and  44 B on the basis of the voltages VR 12  and VR 22  detected by the VR voltage detecting circuits  34 A and  34 B. The abnormality detecting unit  31   a  operates the control computing device  31  so that the first and second inverter circuits  42 A and  42 B and the three-phase electric motor  22  are put in a non-energized state, and, during the non-energized state, causes one or more of the FETs QC 1  to QC 2  and QD 1  to QD 2  of the first and second power source blocking circuits  44 A and  44 B to perform a blocking operation. Then, during the blocking operation, the abnormality detecting unit  31   a  detects a short-circuit failure of the one or more FETs caused to perform the blocking operation, on the basis of the blocking portion voltage detection values VR 12  and VR 22  detected by the VR voltage detecting circuits  34 A and  34 B. 
     For example, no determination can be made as to the presence or absence of energization in a situation where energization to the three-phase electric motor  22  is unnecessary or there is no energization. With this configuration, the upper arms and lower arms of the first and second inverter circuits  42 A and  42 B are blocked so that the first and second inverter circuits  42 A and  42 B and the three-phase electric motor  22  are put in a non-energized state in the situation where energization is unnecessary or there is no energization. In addition, the FET as an object to be checked of the first and second power source blocking circuits  44 A and  44 B is blocked. On the basis of the blocking portion voltage detection values VR 12  and VR 22  of the VR voltage detecting circuits  34 A and  34 B at this time, a short-circuit failure of the first and second power source blocking circuits  44 A and  44 B can be detected. 
     As a result of that, a short-circuit failure of the first and second power source blocking circuits  44 A and  44 B can be detected in the situation where energization to the three-phase electric motor  22  is unnecessary or there is no energization. 
     (14) There are provided the electrolytic capacitors CA and CB individually interposed between the connection lines of the first and second power source blocking circuits  44 A and  44 B and the first and second inverter circuits  42 A and  42 B and the ground lines. The abnormality detecting unit  31   a  operates the control computing device  31  so that the charge state of the electrolytic capacitors CA and CB are maintained, causes one or more of the FETs QA 1  to QA 3  and QB 1  to QB 3  to perform a blocking operation, and performs processing for short-circuit failure detection. 
     With this configuration, even when the electrolytic capacitors CA and CB having a relatively large capacity are interposed to remove noise, the charge state of the electrolytic capacitors CA and CB can be maintained in performing processing for short-circuit failure detection. Thereby, when performing a blocking operation involving discharge of the electrolytic capacitors CA and CB, an energization response delay occurring at a time of restart of energization due to the discharge can be prevented. Consequently, this can prevent an uncomfortable steering feeling from occurring due to the energization response delay. 
     (15) The first and second power source blocking circuits  44 A and  44 B include the FETs QC 1  and QD 1  that block energization from the battery  27  to the first and second inverter circuits  42 A and  42 B and the FETs QC 2  and QD 2  that block energization from the first and second inverter circuits  42 A and  42 B to the battery  27 . The VR voltage detecting circuits  34 A and  34 B detect the voltage VR  12  generated at a connection line between the FETs QC 1  and QC 2  and the voltage VR 22  generated at a connection line between the FETs QD 1  and QD 2 , and also have a function of holding the respective connection lines at ground potential (a pulldown function) when the FETs QC 1  to QC 2  and the FETs QD 1  to QD 2  are in a normally blocked state. 
     With this configuration, for example, when the FETs QC 1  and QC 2  of the first power source blocking circuit  44 A are caused to perform a blocking operation, if they are normal, currents from the battery  27  and the electrolytic capacitor CA are blocked. Thus, due to the pulldown function (resistance R 7 ) of the VR voltage detecting circuit  34 A, the blocking portion voltage detection value VR 12  becomes approximately 0 [V]. On the other hand, the blocking portion voltage detection value VR 22  generated at the connection line between the FETs QD 1  and QD 2  in the energized state becomes approximately Vbat [V] due to the current supplied from the battery  27 . Accordingly, a short-circuit failure of the first and second power source blocking circuits  44 A and  44 B can be detected by blocking all of the FETs of one of the first and second power source blocking circuits  44 A and  44 B, whereas energizing all of the FETs of the other power source blocking circuit, and making a magnitude comparison between the blocking portion voltage detection values VR 12  and VR 22 . 
     (16) When the motor control device  25  is normal, the control computing device  31  controls the first and second motor driving circuits  32 A and  32 B to supply a plurality of three-phase motor driving currents to the three-phase motor windings La, Lb, and Lc. When the abnormality detecting unit  31   a  detects a short-circuit failure, the control computing device  31  stops driving of the motor driving circuit to which the power source blocking circuit or the motor current blocking circuit having the short-circuit failure occurring therein is connected. Along with this, all of the FETs of the power source blocking circuit and the motor current blocking circuit connected to the motor driving circuit are caused to perform a blocking operation, and the other normal motor driving circuit continues supply of the three-phase motor driving currents. 
     With this configuration, when a short-circuit failure occurs in either one of the first and second motor current blocking circuits  33 A and  33 B, one of the first and second motor driving circuits  32 A and  32 B to which the motor current blocking circuit with the short-circuit failure is connected can be isolated from the battery  27  and the three-phase electric motor  22 . In addition, energization to the three-phase electric motor  22  can be continued by the other motor driving circuit without any short-circuit failure occurring. As a result of that, the occurrence of an uncomfortable steering feeling due to discontinuation of motor assistance can be prevented. 
     (17) The abnormality detecting unit  31   a  determines whether energization between the first and second motor driving circuits  32 A and  32 B and the three-phase electric motor  22  is necessary or not on the basis of the steering assisting current command value I* computed by the control computing device  31  and the motor driving current values Ia, Ib, and Ic of currents flowing through the respective phases of the three-phase electric motor. Alternatively, the unit  31   a  determines whether or not there is energization between the first and second motor driving circuits  32 A and  32 B and the three-phase electric motor  22 . Then, when determining that the energization is unnecessary or there is no energization, the unit  31   a  performs processing for detecting a short-circuit failure of the first and second power source blocking circuits  44 A and  44 B. 
     This configuration enables short-circuit failure detection processing for the first and second power source blocking circuits  44 A and  44 B based on monitored voltage values at a timing when energization between the first and second motor driving circuits  32 A and  32 B and the three-phase electric motor  22  is unnecessary. As a result of that, a short-circuit failure of the first and second power source blocking circuits  44 A and  44 B can be more surely detected. 
     Herein, in the conventional example, a steering amount of the steering wheel is determined on the basis of the amount of change in output of a torque sensor or a motor angular velocity, and they cannot be regarded as being exactly equivalent to motor current. Thus, in the configuration of the conventional example, energization may be blocked by erroneous permission of check in a state where while a current command is input via a network such as CAN, the motor is not rotating, for example, in a case in which a torque cancellation current command is input from the CAN so that a vehicle can travel straight ahead even with no steering torque during travelling on an inclined road or during sudden braking. In contrast, the present configuration enables the necessity or non-necessity of energization to be surely detected on the basis of the steering assisting current command value I* and the motor driving current values Ia, Ib, and Ic of the respective phases of the three-phase electric motor  22 . Thus, the occurrence of an erroneous blocking operation can be prevented. 
     (18) The abnormality detecting unit  31   a  determines whether energization between the first and second motor driving circuits  32 A and  32 B and the three-phase electric motor  22  is necessary or not on the basis of the steering assisting current command value I* computed by the control computing device  31  and the motor driving current values Ia, Ib, and Ic flowing through the respective phases of the three-phase electric motor. Alternatively, the abnormality detecting unit  31   a  determines whether or not there is energization between the first and second motor driving circuits  32 A and  32 B and the three-phase electric motor  22 . Then, when determining that the energization is unnecessary or there is no energization, the unit  31   a  performs processing for detecting a short-circuit failure of the first and second motor current blocking circuits  33 A and  33 B. 
     With this configuration, short-circuit failure detection processing for the first and second motor current blocking circuits  33 A and  33 B based on the monitored voltage values can be performed at a timing when energization between the first and second motor driving circuits  32 A and  32 B and the three-phase electric motor  22  is unnecessary. As a result of that, a short-circuit failure of the first and second motor current blocking circuits  33 A and  33 B can be more surely detected. 
     In addition, as with the above (17), since the necessity or non-necessity of the energization can be more surely detected on the basis of the steering assisting current command value I* and the motor driving current values Ia, Ib, and Ic of currents flowing through the respective phases of the three-phase electric motor, the occurrence of an erroneous blocking operation can be prevented. 
     Modified Examples 
     (1) While the above embodiments have described the configuration in which the motor driving circuits include the two motor driving circuits, the present invention is not limited thereto and can also be applied to embodiments of configurations with three or more motor driving circuits. 
     (2) While the above embodiments have described the case in which the electric motor is the three-phase electric motor, the invention is not limited thereto and can also be applied to embodiments of multi-phase electric motors with four or more phases. 
     (3) While the above embodiments have described the case in which the motor control device according to the present invention has been applied to the electric power steering device incorporated in the vehicle, the invention is not limited thereto and can also be applied to an optional system using an electric motor, such as an electric brake device, a steering-by-wire system, or a motor driving device for vehicle traveling. 
     In addition, while the above-described respective embodiments are preferable specific examples of the present invention and technically preferable various limitations are added, the scope of the invention is not limited to these embodiments as long as there is no description that particularly limits the invention in the above description. Additionally, for illustrative convenience, the drawings used in the above description are schematic diagrams in which longitudinal and transversal scales of the members and portions are different from actual ones. 
     The present application claims priority to Japanese Patent Application P No. 2014-48009 (filed on Mar. 11, 2014), the entire content of which is incorporated herein by reference. 
     While the present invention has been described hereinabove with reference to the limited number of embodiments, the scope of the invention is not limited thereto, and improvements and modifications of the respective embodiments based on the above disclosure are obvious to those skilled in the art. 
     REFERENCE SIGNS LIST 
     
         
           1 : Vehicle 
           11 : Steering wheel 
           12 : Steering shaft 
           13 : Steering torque sensor 
           18 : Steering gear 
           20 : Steering assisting mechanism 
           22 : Three-phase electric motor 
         La: A-phase motor winding 
         Lb: B-phase motor winding 
         Lc: C-phase motor winding 
         L 1  to L 3 : Coil portion 
           25 : Motor control device 
           26 : Vehicle speed sensor 
           27 : Battery 
           31 : Control computing device 
           31   a : Abnormality detecting unit 
           32 A: First motor driving circuit 
           32 B: Second motor driving circuit 
           33 A: First motor current blocking circuit 
           33 B: Second motor current blocking circuit 
           34 A,  34 B: VR voltage detecting circuit 
           35 : Compensation control computing unit 
           36 : Adder 
           37 : d-q axis current command value computing unit 
           38 : Voltage command value computing unit 
           39 A 1 ,  39 A 2 ,  39 A 3 ,  39 A 4 ,  39 B 1 ,  39 B 2 ,  39 B 3 ,  39 B 4 : Current detecting circuit 
           40 A,  40 B: Motor voltage detecting circuit 
           41 A: First gate driving circuit 
           41 B: Second gate driving circuit 
           42 A: First inverter circuit 
           42 B: Second inverter circuit 
           44 A: First power source blocking circuit 
           44 B: Second power source blocking circuit 
           50 : Warning circuit