Patent Publication Number: US-7723928-B2

Title: Ballast control IC with minimal internal and external components

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application is a divisional of U.S. patent application Ser. No. 10/899,622 filed Jul. 27, 2004 and entitled BALLAST CONTROL IC WITH MINIMAL INTERNAL AND EXTERNAL COMPONENTS, which is a divisional of U.S. patent application Ser. No. 10/337,738, filed Jan. 7, 2003, now U.S. Pat. No. 7,019,471, entitled BALLAST CONTROL IC WITH MINIMAL INTERNAL AND EXTERNAL COMPONENTS, which is a divisional of U.S. patent application Ser. No. 09/883,397, filed Jun. 19, 2001, now U.S. Pat. No. 6,525,492, entitled “BALLAST CONTROL IC WITH MINIMAL INTERNAL AND EXTERNAL COMPONENTS” which application claims the benefit of U.S. Provisional Application No. 60/212,643, filed Jun. 19, 2000. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an electronic ballast for controlling fluorescent or high-intensity discharge lamps, and more particularly, to an electronic ballast that requires fewer internal and external components. 
   2. Description of the Related Art 
   Electronic ballasts for controlling fluorescent or high-intensity discharge (HID) lamps usually require electronics necessary for preheating the lamp filaments, striking the lamp, driving the lamp to a given power, detecting lamp fault conditions, and safely deactivating the circuit. 
   Electronic ballasts for gas discharge circuits have recently come into widespread use because of the availability of power MOSFET switching devices and insulated gate bipolar transistors (“IGBTs”) that can replace previously used power bipolar switching devices. Monolithic gate driver circuits, such as the IR2155 sold by International Rectifier Corporation and described in U.S. Pat. No. 5,545,955, the disclosure of which is incorporated herein by reference in its entirety, have been devised for driving the power MOSFETs or IGBTs in electronic ballasts. 
   The IR2155 gate driver IC offers significant advantages over prior circuits: The driver is packaged in a conventional DIP or SOIC package. The package contains internal level shifting circuitry, under voltage lockout circuitry, deadtime delay circuitry, and additional logic circuitry and inputs so that the driver can self-oscillate at a frequency determined by external resistors R T  and capacitors C T . 
   Although the IR2155 offers a vast improvement over prior ballast control circuits, it lacks a number of desirable features such as the following: (i) a start-up procedure which ensures a flash-free start without an initial high voltage pulse across the lamp, (ii) non-zero voltage switching protection circuitry, (iii) over-temperature shutdown circuitry, (iv) DC bus and AC on/off control circuitry, and (v) near or below resonance detection circuitry. 
   U.S. Pat. No. 6,211,623 to Wilhelm et al. issued Apr. 3, 2001 and having common assignment with the present application discloses an electronic ballast which addresses limitations of the IR2155, such as those discussed above. The electronic ballast is identified by the assignee, International Rectifier Corporation, as the IR2157. 
   The ballast control circuit of the &#39;623 patent, as in commonly known ballasts, requires an implementation of the preheat timer that includes a comparator for comparing the CPH pin against a fixed threshold. In addition, the oscillator circuit requires more than one comparator. These and other configuration details result in additional components being required both inside and outside the chip. Accordingly, the prior art could be improved upon by providing a ballast control IC which performs the primary ballast functions while minimizing the internal and external component count. Applications for such ballasts would include linear fluorescent lamps, compact fluorescent lamps (CFL), cold-cathode fluorescent lamps (CCFL), high-intensity discharge (HID) lamps, and flat fluorescent lamps. 
   SUMMARY OF THE INVENTION 
   The present invention overcomes the deficiencies of the prior art, such as those described above, by providing an electronic ballast that utilizes fewer comparators and combines the functionality of sub-circuits, thereby reducing the number of internal and external components required. 
   More specifically, the chip of the present invention includes an oscillator circuit that advantageously requires only one comparator circuit. In addition, a lamp preheat circuit uses a preheat resistor parallel to the timing resistor to program preheat frequency, and the voltage at the gate of a MOSFET switch is ramped to gradually disconnect the preheat pin (and thus the preheat resistor) from the frequency timing input. Also, the preheat circuit ramp is utilized as a ramp for lamp ignition as well, thus saving on circuit components. Further, the preheat capacitor input is used as a convenient delay for connecting a DC bus sensing resistor to a DC bus sensing input. 
   The integrated circuit of the present invention includes circuitry for performing the following functions: micro-power start-up current, programmable preheat frequency, programmable ignition-current or over-current, programmable preheat time, programmable ignition ramp, programmable running or minimum frequency, programmable dead-time, programmable low DC bus frequency-shift reset, external shutdown pin, and high- and low-side 600V half-bridge driver outputs for driving two MOSFETs or IGBTs connected in a classic totem-pole configuration. 
   Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a state diagram showing the functionality incorporated into a ballast control integrated circuit according to the present invention. 
       FIG. 2  is a typical connection diagram for driving a single fluorescent lamp with the ballast control circuit of the present invention. 
       FIG. 3  illustrates a basic block diagram of the ballast control circuit of the present invention. 
       FIG. 4  is a detailed schematic of oscillator circuitry of the integrated ballast control circuit according to the present invention 
       FIG. 5  is a schematic illustration of preheat circuitry according to a preferred embodiment of the present invention. 
       FIG. 6  is a schematic diagram of start-up and low DC bus frequency-shift reset circuitry of the integrated ballast control circuit of the present invention. 
       FIG. 7  is a timing diagram for the ballast control circuit of the present invention. 
   

   DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION 
   Overview 
   Referring first to  FIG. 1 , a state diagram is shown that is incorporated into the operation of the integrated circuit (IC)  2  of the present invention for controlling an electronic (rapid start) fluorescent lamp ballast.  FIG. 2  illustrates a typical connection diagram for driving a single fluorescent lamp  4  with the integrated circuit  2  of the present invention.  FIG. 3  illustrates a basic block diagram of the integrated circuit  2  of the present invention. Many of the aspects of the present invention shown in  FIGS. 1-3  are similar to the disclosure of U.S. Pat. No. 6,211,623 to Wilhelm et al. issued Apr. 3, 2001 and incorporated herein by reference, and will be discussed further below. However, significant aspects and advantages of the present invention, particularly with respect to oscillator  10 , preheat circuit  40  and start-up circuit  50  shown in  FIG. 3 , will be discussed, as follows: 
   Oscillator: 
     FIG. 4  is a detailed schematic of oscillator circuit  10  according to the present invention. In contrast to prior ballast ICs, the oscillator circuit advantageously requires only one comparator  12  and therefore significantly reduces the layout space required for implementation into silicon. Accordingly, the overall size of the IC can be reduced. 
   Operationally, the minus (−) input of comparator  12 , Vth, initially is at ⅗ VCC, which is established by the voltage divider formed by five resistors  14 ,  16 ,  18 ,  20 , and  22  of equal resistance connected in series between VCC and COM. The on/off control signal  ENABLE  is a logic ‘high’, therefore turning MOSFET  24  ‘on’ which keeps the timing capacitor C T  discharged to COM through dead-time resistor  28 . Pin CT serves as the plus (+) input of comparator  12  and is initially at COM, therefore the output of comparator  12  is a logic ‘low.’ 
   Switch  30  is ‘off’ initially due to the output of OR gate  32  being ‘high’ when  ENABLE  is ‘high.’ Pin RT is therefore at the same potential as pin CT due to their connection through timing resistor R T . Once  ENABLE  goes ‘low’ (see Timing Diagram,  FIG. 7 ), MOSFET switch  24  is ‘opened’ and switch  30  is ‘closed’. As a result, timing capacitor C T  charges exponentially towards VCC through timing resistor R T  at a rate given by the following equation: 
               V   CT     ⁡     (   t   )       =     VCC   (     1   -     ⅇ       -   t     RC         )           
where,
         R=resistance of timing resistor R T  [Ohms]   C=capacitance of timing capacitor C T  [Farads]   t=time [Seconds]       
   When the voltage on pin CT exceeds ⅗ VCC, the output of comparator  12  goes ‘high’ causing switch  36  to ‘close,’ switch  30  to ‘open,’ and switch  24  to ‘close.’ Timing capacitor C T  then discharges exponentially towards COM through dead-time resistor  28  at a rate given by: 
   
     
       
         
           
             
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   Closing switch  36  changes the threshold at pin CT from ⅗ VCC to ⅓ VCC. In doing so, inherent positive feedback forces the comparator output to transition quickly with a single edge. When capacitor C T  discharges below ⅓ VCC, the output of comparator  12  goes ‘low’ again, and the cycle repeats itself. 
   This charging and discharging of CT between ⅗ VCC and ⅓ VCC continues indefinitely until the  ENABLE  signal goes once again ‘high’. During steady state oscillations, the charging and discharge times are given as: 
             Charging   ⁢     :     ⁢           ⁢       v   CT     ⁡     (   t   )         =       (     VCC   -       1   3     ⁢   VCC       )     ⁢     (     1   -     ⅇ       -   t       RC   ·   CT           )                     Discharging   ⁢     :     ⁢           ⁢       v   CT     ⁡     (   t   )         =       3   5     ⁢   VCC   ⁢           ⁢     ⅇ       -   t       RT   ·   CT                 
The charging time determines the ‘on’ time of gate drive signals HO and LO (see Timing Diagram,  FIG. 7 ). The discharge time determines the dead-time between gate drive signals HO and LO (see Timing Diagram,  FIG. 7 ). This preferred oscillator of the present invention results in less circuitry than oscillator circuits of previous ballast ICs, specifically requiring only one comparator. The oscillator is ratiometric with VCC and is therefore independent of VCC. The threshold values selected are arbitrary.
 
Preheat Timer and Ignition Ramp
 
     FIG. 5  is a schematic illustration of preheat circuit  40  according to a preferred embodiment of the present invention. Advantageously, preheat circuit  40  does not require any comparators. 
   During preheat, it is necessary for the IC to oscillate at a higher preheat frequency. This is followed by a smooth downward sweep through the ignition frequency to the final running or minimum frequency. To do this, an external capacitor C PH  is charged linearly from COM to VCC through an internal 5 μA current source  44  flowing out of the CPH pin. The CPH pin is also connected to the gate of a PMOS transistor  46  which connects pin RPH to pin RT. In this configuration, resistor R T  is connected in parallel with resistor R PH  such that the oscillator frequency is higher during preheat. Since the threshold of the PMOS is about 1.5 volts, the preheat period is defined as the time it takes for capacitor C PH  to ramp from COM to (VCC−1.5 volts). As capacitor C PH  continues to charge from (VCC−1.5V) to VCC, switch  46  opens slowly, which slowly disconnects pin RPH from RT. This causes the frequency to transition slowly from the preheat frequency to the final running frequency. (See Timing Diagram,  FIG. 7 ). 
   The advantageous features of preheat circuit  40  are: 1) using a resistor R PH  parallel to resistor R T  to program the preheat frequency; 2) ramping the voltage at the gate of PMOS  46  to disconnect the RPH pin smoothly from the RT pin; and 3) using the existing capacitor C PH  ramp as the ramp for ignition as well. Classical implementation of the preheat timer requires a comparator for comparing the CPH pin against a fixed threshold. By combining the above-noted three functions in preheat circuit  40  of the present invention, a ‘comparator-less’ pre-heat timer is realized, thereby reducing the overall size of the IC. 
   Start-Up Circuitry and Low DC Bus Frequency-Shift Reset: 
   Start-up and low DC bus frequency-shift reset circuitry  50  is shown in the schematic of  FIG. 6 . The circuit senses the DC bus and properly resets the circuit back to preheat mode if the DC bus decreases below a level where the lamp can extinguish. Failure to do this can result in the lamp extinguishing during a brown-out line condition and not being re-ignited when the AC input returns. Decreasing the DC bus also can cause hard-switching at the half-bridge output which can damage or destroy the power MOSFETs or IGBTs. It is therefore convenient to increase the frequency as the DC bus decreases such that the ballast operating point always remains above resonance and no hard-switching occurs. 
   Circuit  50  of the present invention achieves this by using the VDC pin to sense the DC bus. If VDC decreases below (VCC−10.9V), the CPH pin is pulled down linearly with the VDC pin. This gradually will re-connect RPH with RT and therefore gradually shift the frequency higher. 
   The 10.9V threshold is achieved with a PNP transistor  52 , and the two 5.1 zener diodes  54  and  56 , connected in series. The base of transistor  52  is connected to pin VDC, the collector of transistor  52  is connected to COM, and the emitter is connected to the anode of the lower diode  54 . The cathode of the upper diode is then connected to pin CPN. In this configuration, the frequency is not increased until VDC goes below the two zener voltages (10.2V) plus the emitter-to-base voltage of transistor  52  (≃0.7)=10.9V.  FIG. 8  depicts this graphically. 
   To program the DC bus level at which the frequency shift occurs, an external resistor  58  (R SUPPLY ), with an internal resistor  60 , form a voltage divided ratio of the DC bus at pin VDC. To further reduce external component count, resistor  58  also supplies micro-power start-up current to the IC. As the DC bus increases at ballast turn-on, current flows from the DC bus, through the resistor  58 , into pin VDC, through the existing ESD diode  62  connected between VDC and VCC. 
   Once VCC exceeds the positive-going under-voltage lock-out threshold, UVLO (+), an external charge pump (or other form of supply) connected to VCC through an external diode  63  takes over as the supply for VCC and increases VCC up to the internal zener clamp voltage (see Timing Diagram,  FIG. 7 ). Resistor  60  then is connected internally to pin VDC through MOSFET  64  when CPH exceeds the threshold voltage (≃½ VCC) of Schmitt trigger  66 . This occurs at approximately half way through the preheat time. The CPH pin is used as a convenient delay for connecting RVDC to pin VDC, which also contributes to reducing the overall size of the IC. 
   State Diagram 
   Referring back now to  FIG. 1 , the integrated circuit  2  of the present invention advantageously executes a very specific set of instructions to control the lamp  4  and protect the ballast. The IC accurately controls and properly performs the functions of: powering up and down the IC  2  and the half-bridge (MOSFETs  6  and  8 ); preheating and striking the lamp; running the lamp; sensing for numerous possible fault conditions; and recovering from these fault conditions based on normal lamp maintenance. 
   The state machine operates between five basic modes of operation based on the status of the various inputs to the IC. These five modes of operation include: 
   1) under voltage lockout mode; 
   2) preheat mode; 
   3) ignition ramp mode; 
   4) run mode; and 
   5) fault mode. 
     FIG. 2  illustrates the pinouts of the IC  2 , including all of its inputs and outputs. The inputs to the chip include: 
   1) VCC 
   2) VDC 
   3) SD 
   4) CS 
   5) CPH 
   6) CT 
   7) RT 
   VCC represents both an input to be sensed and the primary low voltage supply to the IC. In addition to these seven inputs, the IC surface junction temperature represents an eighth input. The outputs of the IC include: 
   1) HO 
   2) LO 
   3) RPH 
   4) RUN 
   5) DT 
   The supplies to the IC include: 
   1) VCC 
   2) COM 
   3) VB 
   4) VS 
   The general description for the IC functions of the present invention are as follows: 
   Under-Voltage Lock-Out Mode (UVLO) 
   The under-voltage lock-out mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on threshold of the IC. The undervoltage lock-out is designed to maintain an ultra low supply current of less than 150 uA, and to guarantee the IC is fully functional before the high and low side output drivers are activated.  FIG. 1  shows an efficient supply voltage using the start-up current of the ballast IC together with a charge pump from the ballast output stage (resistor  58 , capacitors  70 ,  72 , D CP1  and D CP2 ). 
   The start-up capacitors  70 ,  72  (C VCC ) are charged by current through supply resistor  58  (R SUPPLY ) minus the start-up current drawn by the IC. Resistor  58  is connected to VCC internally through a diode, and is chosen to fulfill two functions. The first is to provide twice the maximum start-up current to guarantee ballast start-up at low line input voltage. The second is to set the IC reset threshold in case of a decreasing DC bus (described in more detail above). Once the capacitor voltage on VCC reaches the start-up threshold, and the SD pin is below 4.5 volts, the IC turns on and HO and LO begin to oscillate. Capacitors  70 ,  72  begin to discharge due to the increase in IC operating current. 
   During the discharge cycle, the rectified current from the charge pump charges the capacitor above the IC turn-off threshold. The charge pump and the internal 15.6V zener clamp of the IC take over as the supply voltage. The start-up capacitors  70 ,  72  and snubber capacitor  80  must be selected such that enough supply current is available over all ballast operating conditions. A bootstrap diode  82  and supply capacitor  84  comprise the supply voltage for the high side driver circuitry. To guarantee that the high-side supply is charged up before the first pulse on pin HO, the first pulse from the output drivers comes from the LO pin. During undervoltage lock-out mode, the high- and low-side driver outputs HO and LO are both low, pin CT is connected internally to COM to disable the oscillator, and pin CPH is connected internally to COM for resetting the preheat time. 
   Preheat Mode (PH) 
   The preheat mode is defined as the state the IC is in when the lamp filaments are being heated to their correct emission temperature. This is necessary for maximizing lamp life and reducing the required ignition voltage. The ballast control IC enters preheat mode when VCC exceeds the UVLO positive-going threshold. HO and LO begin to oscillate at the preheat frequency with 50% duty cycle and with a dead-time which is set by the value of the external timing capacitor C T , and internal deadtime resistor, RDT. Pin CPH is disconnected from COM and an internal 1 uA current source ( FIG. 3 ) charges the external preheat time capacitor on CPH linearly. The over-current protection on pin CS is disable during preheat. The preheat frequency is determined by the parallel combination of resistors R PH  and R T , together with timing capacitor C T . Capacitor C T  charges and discharges between ⅓ and ⅗ of VCC (see Timing Diagram,  FIG. 7 ). C T  is charged expontentially through the parallel combination of R T  and R PH  connected internally to VCC through MOSFET  36 . The charge time of C T  from ⅓ and ⅗ VCC is the on-time of the respective output gate driver, HO or LO. Once CT exceeds ⅗ VCC, MOSFET  36  is turned off, disconnecting RT and RPH from VCC. Capacitor C T  then is discharged exponentially through an internal resistor, RDT, through MOSFET  24  to COM. The discharge time of timing capacitor C T  from ⅗ to ⅓ VCC is the dead-time (both off) of the output gate drivers, HO and LO. The selected values of capacitor C T  together with RDT (resistor  28 ) therefore program the desired dead-time (see Design Equations 1 and 2). Once capacitor C T  discharges below ⅓ VCC, MOSFET  24  is turned off, disconnecting RDT from COM, and MOSFET  36  is turned on, connecting RT and RPH again to VCC. The frequency remains at the present frequency until the voltage on pin CPH exceeds 13V and the IC enters Ignition Mode. During the preheat mode, both the over-current protection and the DC bus under-voltage reset are enabled when pin CPH exceeds 7.5V. 
   Ignition Mode (IGN) 
   The ignition mode is defined as the state the IC is in when a high voltage is being established across the lamp necessary for igniting the lamp. The ballast control IC enters ignition mode when the voltage on pin CPH exceeds 13V. 
   Pin CPH is connected internally to the gate of a p-channel MOSFET  46  of preheat circuit  40  (see  FIG. 5 ) that connects pin RPH with pin RT. As pin CPH exceeds 13V, the gate-to-source voltage of MOSFET  46  begins to fall below the turn-on threshold of MOSFET  46 . As pin CPH continues to ramp towards VCC, MOSFET switch  46  turns off slowly. This results in preheat resistor R PH  being disconnected smoothly from timing resistor R T , and therefore causing the operating frequency to ramp smoothly from the preheat frequency, through the ignition frequency, to the final run frequency. The over-current threshold on pin CS will protect the ballast against a non-strike or open-filament lamp fault condition. The voltage on pin CS is defined by the lower half-bridge MOSFET current flowing through the external current sensing resistor R CS . Current sensing resistor R CS  therefore programs the maximum allowable peak ignition current (and therefore peak ignition voltage) of the ballast output stage. The peak ignition current must not exceed the maximum allowable current ratings of the output stage MOSFETs. If this voltage exceeds the internal threshold of 1.3V, the IC will enter FAULT mode and both gate driver outputs HO and LO will be latched low. 
   Run Mode (RUN) 
   Once the lamp has successfully ignited, the ballast enters the run mode. The run mode is defined as the state the IC is in when the lamp arc is established and the lamp is being driven to a given power level. The run mode oscillating frequency is determined by the timing resistor R T  and timing capacitor C T  (see Design Equations 3 and 4 in the following section). Should hard-switching occur at the half-bridge at any time due to an open-filament or lamp removal, the voltage across the current sensing resistor R CS  will exceed the internal threshold of 1.3 volts and the IC will enter FAULT mode. Both gate driver outputs, HO and LO, will be latched low. 
   DC Bus Under-Voltage Reset: 
   If the voltage of the DC bus decreases too far during a brown-out line condition or over-load condition, the resonant output stage to the lamp can shift near or below resonance. This can produce hard-switching at the half-bridge which can damage the half-bridge switches. To protect against this, pin VDC measures the DC bus voltage and pulls down on pin CPH linearly as the voltage on pin VDC decreases 10.9V below VCC. This causes the p-channel MOSFET  46  ( FIG. 4 ) to close as the DC bus decreases and the frequency to shift higher to a safe operating point above resonance. The DC bus level at which the frequency shifting occurs is set by the external resistor  58  and internal RVDC resistor. By pulling down on pin CPH, the ignition ramp is also reset. Therefore, should the lamp extinguish due to very low DC bus levels, the lamp will be automatically ignited as the DC bus increases again. The internal RVDC resistor is connected between pin VDC and COM when CPH exceeds 7.5V (during preheat mode). This allows for resistor  58  to serve also as the start-up resistor for the IC, therefore minimizing component count. 
   Fault Mode (FAULT) 
   If the voltage at the current sensing pin, CS, exceeds 1.3 volts at any time after the preheat mode, the IC enters fault mode and both gate driver outputs, HO and LO, are latched in the ‘low’ state. CPH is discharged to COM to reset the preheat time, and CT is discharged to COM for disabling the oscillator. To exit the fault mode, VCC must be recycled back below the UVLO negative-going turn-off threshold, or, the shutdown pin, SD, must be pulled above 5.1 volts. Either of these conditions will force the IC to enter UVLO mode (see State Diagram, page 2). Once VCC is above the turn-on threshold and SD is below 4.5 volts, the IC will begin oscillating again in the preheat mode. 
   Design Equations 
   The design equations for implementing the ballast IC of the present invention are as follows: 
   Step 1: Program Dead-Time 
   The dead-time between the gate driver outputs HO and LO is programmed with timing capacitor C T  and internal dead-time resistor  28  (see  FIG. 4 ). The dead-time is the discharge time of capacitor C T  from ⅗ VCC to ⅓ VCC and is given as: 
                     t   DT     =       C   T     ·     1475   ⁢           [   Seconds   ]         ⁢     
     ⁢   or           (   1   )                 C   T     =         t   TD     1475     ⁢           [   Farads   ]             (   2   )               
Step 2: Program Run Frequency
 
   The final run frequency is programmed with timing resistor R T  and timing capacitor C T . The charge time of capacitor C T  from ⅓ VCC to ⅗ VCC determines the on-time of HO and LO gate driver outputs. The run frequency is therefore given as: 
                     f   RUN     =       1     2   ·       C   T     ⁡     (       0.51   ·     R   T       +   1475     )           ⁢           [   Hertz   ]       ⁢     
     ⁢   or           (   3   )                 R   T     =       1     1.02   ·     C   T     ·     f   RUN         -     2892   ⁢           [   Ohms   ]               (   4   )               
Step 3: Program Preheat Frequency
 
   The preheat frequency is programmed with timing resistor R T  and preheat resistor R PH  and timing capacitor C T . Timing resistor R T  and preheat resistor R PH  are connected in parallel internally for the duration of the preheat time. The preheat frequency is therefore given as: 
                   f   PH     =       1     2   ·     C   T     ·     (         0.51   ·     R   T     ·     R   PH           R   T     +     R   PH         +   1475     )         ⁢           [   Hertz   ]             (   5   )                 R   PH     =           (       1     1.02   ⁣       ·   C     -     ·     f   PH             -   2892     )     ·     R   T           R   T     -     (       1     1.02   ⁣     ·     C   T     ·     f   PH           -   2892     )         ⁢           [   Ohms   ]             (   6   )               
Step 4: Program Preheat Time
 
   The preheat time is defined by the time it takes for capacitor C PH  on pin CPH to charge up to 13 volts. An internal current source of 5 μA flows out of pin CPH. The preheat time is therefore given as:
 
 t   PH   =C   PH ·2.6 e 6 [Seconds]  (7)
 
or
 
 C   PH   =t   PH ·0.385 e− 6 [Farads]  (8)
 
Step 5: Program Maximum Ignition Current
 
   The maximum ignition current is programmed with the external resistor RCS and an internal threshold of 1.3 volts. This threshold determines the over-current limit of the ballast, which can be exceeded when the frequency ramps down towards resonance during ignition and the lamp does not ignite. The maximum ignition current is given as: 
   
     
       
         
           
             
               
                 
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   Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.