Patent Publication Number: US-7595700-B2

Title: LC quadrature oscillator having phase and amplitude mismatch compensator

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   Embodiments of the invention relate generally to an LC quadrature oscillator, and more particularly, to a phase and amplitude mismatch compensator that compensates for phase and amplitude mismatches between I/Q clock signals generated by the LC quadrature oscillator. 
   2. Description of the Related Art 
   In general, an LC quadrature oscillator includes two LC oscillators that are cross-coupled with each other to generate I/Q clock signals. During operation of the LC quadrature oscillator, there are LC mismatches (e.g., inductance and/or capacitance mismatches) between the two LC oscillators such the I/Q clock signals generated in the LC quadrature oscillator have phase and amplitude mismatches. These phase and amplitude mismatches between the I/Q clock signals generated in the LC quadrature oscillator can degrade the system performance when the LC quadrature oscillator is used in a clock and data recovery (CDR) circuit or an image reject receiver that requires exact I/Q clock signals for signal processing. For example, the phase and amplitude mismatches between the I/Q clock signals can increase a bit-error rate (BER) of a CDR circuit and reduce an image rejection ratio (IRR) of an image reject receiver. Therefore, there is a need for an accurate phase and amplitude mismatch compensator for an LC quadrature oscillator. 
   SUMMARY OF THE INVENTION 
   According to an example embodiment of the invention, there is an LC quadrature oscillator. The LC quadrature oscillator may include a first LC oscillator that generates at least one first clock signal, a second LC oscillator that generates at least one second clock signal, where the at least one first and second clock signals form I/Q clock signals, and a mismatch compensator that compensates for phase and amplitude mismatches of the I/Q clock signals, wherein the mismatch compensator includes an amplitude mismatch detector. 
   According to another example embodiment of the invention, there is a mismatch compensation method. The method may include generating at least one first clock signal using a first LC oscillator, generating at least one second clock signal using a second LC oscillator, where the at least one first and second clock signals form I/Q clock signals, and compensating for phase and amplitude mismatches of the I/Q clock signals using a mismatch compensator that includes an amplitude mismatch detector. 
   According to yet another example embodiment of the invention, there is a system. The system may include a first LC oscillator that generates at least one first clock signal, a second LC oscillator that generates at least one second clock signal, where the at least one first and second clock signals form I/Q clock signals, and means for compensating for phase and amplitude mismatches associated with the I/Q clock signals. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Having thus described the invention in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein: 
       FIG. 1  provides an example block diagram of an LC quadrature oscillator having a phase and amplitude mismatch compensator, according to an example embodiment of the invention. 
       FIG. 2A  provides an example block diagram of an illustrative amplitude mismatch detector, according to an example embodiment of the invention. 
       FIG. 2B  provides an example circuit diagram of an illustrative rectifier, according to an example embodiment of the invention. 
       FIG. 3  provides an example circuit diagram of an illustrative LC oscillator, according to an example embodiment of the invention. 
       FIG. 4  provides simulated waveforms of an LC quadrature oscillator in which a phase and amplitude mismatch compensator is not utilized, according to an example embodiment of the invention. 
       FIG. 5  provides simulated waveforms of an LC quadrature oscillator in which a phase and amplitude mismatch compensator is utilized, according to an example embodiment of the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Embodiments of the present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. Indeed, these inventions may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like numbers refer to like elements throughout. 
     FIG. 1  is a block diagram illustrating an example LC quadrature oscillator  100 , according to an example embodiment of the invention. In particular, the LC quadrature oscillator  100  may include a first LC voltage controlled oscillator (VCO)  110  and a second LC voltage controlled oscillator  120  that are cross-coupled to each other in order to generate clock signals such as I/Q clock signals (e.g., two of CLK 0 , CLK 90 , CLK 180 , CLK 270 ) that are 90 degrees out of phase from each other. According to an example embodiment of the invention, the first LC oscillator  110  may generate the Q clock signals (CLK 90 , CLK 270 ) while the second LC oscillator  120  may generate the I clock signals (CLK 0 , CLK 180 ). With respect to the cross-coupling, the Q clock signals (CLK 90 , CLK 270 ) generated by LC oscillator  110  may be provided as an input to the LC oscillator  120 . Likewise, the I clock signals (CLK 0 , CLK 180 ) generated by the LC oscillator  120  may be provided as an input to the LC oscillator  110 . The LC quadrature oscillator  100  may also include a phase and amplitude mismatch compensator  125  that detects and compensates for phase and amplitude mismatches between the I/Q clock signals generated in the two LC oscillators  110 ,  120 . 
   Still referring to  FIG. 1 , the phase and amplitude mismatch compensator  125  may be comprised of an amplitude mismatch detector  130 , a transconductor  140  in communication with the amplitude mismatch detector  130 , and a capacitor  150  in communication with the output of the transconductor  140 . The amplitude mismatch detector  130  may be operative to detect amplitudes of the I/Q clock signals generated by the two LC oscillators  110 ,  120 . The amplitude mismatch detector  130  may output the detected amplitudes  135   a ,  135   b  of the I/Q clock signals to the transconductor  140 . The transconductor  140  may be operative to determine a difference between the detected amplitudes  135   a ,  135   b  of the I/Q clock signals and output a current signal representing the determined difference. The capacitor  150  may be operative to convert the current signal received from the transconductor  140  into a voltage signal  145 , which may be provided to the second LC oscillator  120  of the two LC oscillators  110 ,  120 . As will be described in further detail below, the voltage signal  145  may be utilized in configuring or adjusting an operation of the LC oscillator  120  so that LC mismatches between the LC oscillators  110 ,  120  may be compensated for. In an alternative embodiment of the invention, the voltage signal  145  may alternatively or additionally be provided to the first LC oscillator  110  of the two oscillators  110 ,  120 . 
   It will be also be appreciated that according to an example embodiment of the invention, the phase and amplitude mismatch compensator  125  may utilize an amplitude mismatch detector  130 , but no phase mismatch detector associated with phase detections, for use in detecting and compensating for phase and amplitude mismatch of the I/Q clock signals generated by the LC quadrature oscillators  110 ,  120 . According to an example embodiment of the invention, the phase and amplitude mismatch compensator  125  may have an accurate phase resolution because the amplitude mismatch detector  130  may not need a much higher bandwidth than the oscillation frequency of I/Q clock signals to detect an amplitude mismatch. Simplified equations (1) and (2) below illustrate phase and amplitude mismatches versus LC mismatches between two LC oscillators which are cross-coupled with each other. 
   
     
       
         
           
             
               
                 
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   In equations (1) and (2), ΔV is amplitude mismatch of the I/Q clock signals, θ is phase mismatch of the I/Q clock signals, R is resistance of an LC tank of an LC oscillator  110 ,  120 , α is the ratio of coupling transconductance versus negative transconductance in the LC quadrature oscillator  100 , Δω is the difference between self oscillation frequencies of two LC oscillators  110 ,  120  which are cross-coupled with each other, and parameter γ indicates if the LC quadrature oscillator  100  is operating in a current-limited regime or voltage-limited regime. A parameter γ of 1 indicates that the LC quadrature oscillator  100  is operating in a voltage-limited regime while a parameter γ of 0 indicates that the LC quadrature oscillator  100  operates in current-limited regime. Consequently, the parameter γ is a value between 0 and 1. According to an embodiment of the invention, the phase and amplitude mismatch compensator  125  may operate most effectively when the parameter γ is 0—that is, when the LC quadrature oscillator  100  is operating in a current-limited regime. 
   As shown in equations (1) and (2), the amplitude mismatch ΔV and the phase mismatch θ have an approximately linear relationship with each other. According to an example embodiment of the invention, based upon this approximately linear relationship, the LC quadrature oscillator  100  may utilize an amplitude mismatch detector  130  with no a phase mismatch detector to detect both phase and amplitude mismatches of the I/Q clock signals of the two LC oscillators  110 ,  120 . Indeed, based upon this approximately linear relationship, a correction of amplitude errors based upon the amplitude mismatch detector  130  may likewise correct for phase errors as well, according to an example embodiment of the invention. 
     FIG. 2A  illustrates a block diagram of an amplitude mismatch detector  130  according to the present invention. The amplitude mismatch detector  130  may include a first rectifier  231  and a second rectifier  232 . The first rectifier  231  may receive the I-clock signals CLK 0  and CLK 180 , and determine the resulting I-clock amplitude signal OUT_I  233 . Likewise, the second rectifier  232  may receive the Q-clock signals CLK 90  and CLK 270 , and determine the resulting Q-clock amplitude signal OUT_Q  234 . 
     FIG. 2B  illustrates an example circuit diagram of a rectifier  231  according to an example embodiment of the invention. The rectifier  231  may include transistors M 1   240 , M 2   241 , and M 3   242 . The transistor M 1   240  may include a source  240   a , a drain  240   b , and a gate  240   c . The transistor M 2   241  may include a source  241   a , a drain  241   b , and a gate  241   c . The transistor M 3   243  may include a source  243   a , a drain  243   b , and a gate  243   c . As shown in  FIG. 2B , the source  240   a  of transistor M 1   240  may be connected to the source  241   a  of transistor M 2   241 . Likewise, the drain  240   b  of transistor M 1   240  may be connected to the drain  241   b  of transistor M 2   241 . Additionally, the drain  242   b  of transistor M 3   242  may be connected to the sources  240   a ,  241   a  of respective transistors M 1   240  and M 2   241 . The output port OUT_I  233  of the rectifier  231  may be provided between the drain  242   b  of transistor M 3   242  and the sources  240   a ,  241   a  of respective transistors M 1   240  and M 2   241 , according to an example embodiment of the invention. 
   Still referring to  FIG. 2B , the rectifier  231  may also include a resistor R 1   245  and a capacitor C 1   247  that is connected to the gate  240   c  of transistor M 1   240 . Likewise, a resistor R 2   246  and a capacitor C 2   248  may be connected to the gate  241   c  of transistor M 2   241 . According to an embodiment of the invention, the capacitors C 1   247 , C 2   248  may perform DC blocking while the resistors R 1   245 , E 2   246  may provide DC bias to the respective transistors M 1   240 , M 2   241 . It will be appreciated that while  FIG. 2B  illustrates an example block diagram of rectifier  231 , the block diagram is also applicable to rectifier  232  as well. For example, the block diagram of  FIG. 2B  may be alternately illustrated as accepting clock signals CLK 90  and CLK 270  instead of clock signals CLK 0  and CLK  180 . Indeed, other variations to the block diagram of  FIG. 28  are available without departing from example embodiments of rectifiers. 
     FIG. 3  is an example circuit diagram of an illustrative an LC oscillator  120 , according to an embodiment of the invention. The LC oscillator  120  may include a plurality of variable capacitors, including a main varactor C 11   302  and a compensating varactor C 12   304 . The capacitance of main varactor C 11   302  may be configured according to frequency voltage V FREQ . Likewise, the capacitance of compensating varactor C 12   304  may be configured according to control voltage V CTRL  received from the a phase and amplitude mismatch compensator  125 . The main varactor C 11   302  may be operative in controlling the oscillating frequency of each LC oscillator  110 ,  120 . The compensating varactor C 12   304  may be operative to compensate for LC mismatches between two LC oscillators  110 ,  120  that are cross-coupled with each other. According to an example embodiment of the invention, the size of the compensating varactor C 12   304  may be adjusted or configured to be relatively smaller than the size of the main varactor C 11   302  but also large enough to cover the range of LC mismatches to be compensated. For an example, if LC mismatches are to be compensated 1%, the size of the compensating varactor C  12  may be designed to be 1% of the total size of the main varactor C 11   302  and the compensating varactor C 12 . 
   Still referring to  FIG. 3 , the LC oscillator  120  may also include transistors M 11   311 , M 12   312 , M 13   313 , M 14   314 , and M 15   315 . Transistor M 11   311  may include a source  311   a , a drain  311   b , and a gate  311   c . Transistor M 12   312  may include a source  312   a , a drain  312   b , and a gate  312   c . Transistor M 13   313  may include a source  313   a , a drain  313   b , and a gate  313   c . Likewise, transistor M 14   314  may include a source  314   a , a drain  314   b , and a gate  314   c . Similarly, transistor M 15   315  may include a source  315   a , a drain  315   b , and a gate  315   c.    
   In  FIG. 3 , the source  311   a  of transistor M 11   311  may be connected to the source  312   a  of transistor M 12   312 . The drain  311   b  of transistor M 11   311  may also be connected to the drain  312   b  of transistor M 12   312 . Likewise, the source  313   a  of transistor M 13   313  may be connected to the source  314   a  of transistor M 14   314 . The drain  314   b  of transistor M 14   314  may also be connected to the drain  314   b  of transistor M 14   314 . Additionally, a drain  315   b  of transistor M 15   315  may be connected to the sources  311   a ,  312   a ,  313   a , and  314   a  of respective transistors M 11   311 , M 12   312 , M 13   313 , and M 14   314 . 
   As shown in  FIG. 3 , a first input port IN+ (e.g., CLK 90 ) may be provided at the gate  311   c  of transistor M 11   311  while a second input port IN− (e.g., CLK 270 ) may be provided at the gate  314   c  of transistor  314 . In addition, a first output port OUT− (e.g., CLK 0 ) shared by the varactors C 11   302 , C 12   304  may be connected to an inductor L 11   322 , drains  311   b ,  312   b , and gate  313   c . A second output port OUT+ (e.g., CLK 180 ) shared by the varactors C 11   302 , C 12   304  may be connected to an inductor L 12   320 , drains  313   b ,  314   b , and gate  312   c.    
   It will be appreciated that while  FIG. 3  illustrates an example block diagram of an illustrative LC oscillator  120 , the block diagram is also applicable to the LC oscillator  110  as well. It will be appreciated that variations of the block diagram of  FIG. 3  are available without departing from example embodiments of the invention. 
     FIG. 4  illustrates simulated waveforms for I/Q clock signals CLK 0 , CLK 90  and a control voltage V CTRL  signal  145  for configuring or adjusting an operation of the LC oscillator  120  in an LC quadrature oscillator  100  when a phase and amplitude mismatch compensator  125  is not utilized, according to an example embodiment of the invention. As shown in a  FIG. 4 , when an LC mismatch is added and the phase and amplitude mismatch compensator  125  is not utilized, the amplitude and phase mismatches in the I/Q clock signals are present due to LC mismatches in between the LC oscillators  110 ,  120 . By contrast,  FIG. 5  illustrates simulated waveforms for I/Q clock signals CLK 0 , CLK 90  and control voltage V CTRL  signal  145  in an LC quadrature oscillator  100  when the phase and amplitude mismatch compensator  125  is utilized, according to an example embodiment of the invention. As shown in  FIG. 5 , when the LC mismatch is added and the phase and amplitude mismatch compensator  125  is utilized, the amplitude and phase mismatches in the I/Q clock signals are substantially eliminated. Accordingly, in  FIG. 5 , the phase and amplitude mismatch compensator  125  is operative to remove LC mismatches between the two LC oscillators  110 ,  120 . 
   Many modifications and other embodiments of the inventions set forth herein will come to mind to one skilled in the art to which these inventions pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the inventions are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.