Patent Publication Number: US-11645971-B2

Title: Light emitting diode package and display apparatus including the same

Description:
CROSS-REFERENCE TO THE RELATED APPLICATION 
     This application claims priority to Korean Patent Application No. 10-2020-0076757, filed on Jun. 23, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Field 
     Methods, apparatuses and systems consistent with example embodiments relate to a light-emitting diode (LED) package and a display apparatus including the same, and more particularly, to an LED package including a pixel driving integrated circuit and a display apparatus including the LED package. 
     2. Related Art 
     LEDs are being used as a light source for various electronic products, in addition to a light source for lighting devices. Particularly, LEDs are being widely used as a light source for various kinds of display apparatuses included in televisions (TVs), portable phones, personal computers (PCs), notebook PCs, tablet PCs, wearable devices, electronic signboards, etc. 
     In this related art, display apparatuses including a liquid crystal display panel and a backlight have been used. However, recently LED displays which include three small LED chips configure one pixel have been proposed. LED displays do not need a separate backlight, and thus, are easy to be highly integrated and have better light efficiency than liquid crystal display (LCD) apparatuses. Also, by changing the arrangement of LED chips, an aspect ratio of a screen may be freely selected and a large-area screen may be implemented, thereby providing various types of display apparatuses. 
     SUMMARY 
     Example embodiments provide a light-emitting diode (LED) package and a display apparatus including the same, in which the reliability of an operation is increased even when a low-luminance operation is performed, and luminance non-uniformity is prevented, thereby realizing excellent screen quality. 
     According to an aspect of an example embodiment, an LED package includes: a first LED pixel including a plurality of first LED chips; and a first pixel driving integrated circuit configured to drive the plurality of first LED chips according to an active matrix (AM) mode using entirety of a first frame period. The first pixel driving integrated circuit includes: a first storage area configured to store first frame data of each of the plurality of first LED chips; a second storage area configured to store duty ratio compensation data of each of the plurality of first LED chips; a pulse width modulation (PWM) data calculator configured to perform an arithmetic operation on the first frame data provided from the first storage area and the duty ratio compensation data provided from the second storage area to generate PWM data; and a PWM data generator configured to adjust an emission duty ratio based on the PWM data. 
     According to an aspect of another example embodiment, an LED package includes a first LED pixel including a plurality of first LED chips; a first pixel driving integrated circuit configured to drive the plurality of first LED chips based on an AM PWM mode of controlling a time for which a driving current is applied thereto in a first frame period; and a package substrate on which the plurality of first LED chips and the first pixel driving integrated circuit are disposed. The first pixel driving integrated circuit includes: a deserializer configured to receive serial data from an external controller, extract and store first frame data of each of the plurality of first LED chips from the serial data, and provide the first frame data; a first storage area configured to store the first frame data provided from the deserializer; a second storage area configured to store duty ratio compensation data of each of the plurality of first LED chips; a PWM data calculator configured to perform an arithmetic operation on the first frame data provided from the first storage area and the duty ratio compensation data provided from the second storage area to generate PWM data; a constant current generator configured to generate a reference current based on a source voltage; a PWM data generator configured to generate a plurality of first driving currents applied to the plurality of first LED chips based on a clock signal, a PWM clock signal, the PWM data provided from the PWM data calculator, and the reference current provided from the constant current generator; a data input pad configured to receive the serial data; a data output pad configured to output data, other than the first frame data, of the serial data; a power pad configured to receive the source voltage; a first clock pad configured to receive the clock signal; a second clock pad configured to receive the PWM clock signal; and a ground pad connected to the plurality of first LED chips. 
     According to an aspect of another example embodiment, a display apparatus includes a printed circuit board; a plurality of light-emitting diode (LED) packages disposed on a first surface of the printed circuit board; and a controller disposed on a second surface opposite to the first surface of the printed circuit board, the controller being configured to control driving of the plurality of LED packages. Each of the plurality of LED packages includes: a first LED pixel including a plurality of first LED chips; and a first pixel driving integrated circuit configured to drive the plurality of first LED chips based on an active matrix (AM) mode using entirety of a first frame period. The first pixel driving integrated circuit includes: a first storage area configured to store first frame data of each of the plurality of first LED chips; a second storage area configured to store duty ratio compensation data of each of the plurality of first LED chips; a pulse width modulation (PWM) data calculator configured to perform an arithmetic operation on the first frame data provided from the first storage area and the duty ratio compensation data provided from the second storage area to generate PWM data; and a PWM data generator configured to adjust an emission duty ratio based on the PWM data. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects and features will become more apparent from the following description of example embodiments with reference to the accompanying drawings in which: 
         FIG.  1    is a perspective view illustrating a light-emitting diode (LED) package according to example embodiments; 
         FIG.  2    is a circuit diagram for describing a pixel driving integrated circuit of  FIG.  1   ; 
         FIGS.  3  to  5 ,  6 A,  6 B,  6 C and  6 D  are diagrams for describing an operation of the pixel driving integrated circuit of  FIG.  2   ; 
         FIG.  7    is a circuit diagram for describing a pixel driving integrated circuit according to example embodiments; 
         FIG.  8    is a circuit diagram for describing a pixel driving integrated circuit according to example embodiments; 
         FIG.  9    is a circuit diagram for describing a pixel driving integrated circuit according to example embodiments; 
         FIG.  10    is a circuit diagram for describing a pixel driving integrated circuit according to example embodiments; 
         FIG.  11    is a perspective view illustrating an LED package according to example embodiments; 
         FIG.  12    is a perspective view illustrating an LED package according to example embodiments; 
         FIG.  13    is a perspective view illustrating an LED package according to example embodiments; 
         FIG.  14    is a perspective view for describing a display apparatus according to example embodiments; 
         FIG.  15    is a plan view illustrating the enlargement of a region CX 1  of  FIG.  14   ; and 
         FIG.  16    is a cross-sectional view of the display apparatus of  FIG.  14   . 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1    is a perspective view illustrating a light-emitting diode (LED) package  1000  according to example embodiments. 
     Referring to  FIG.  1   , the LED package  1000  may include an LED pixel and a pixel driving integrated circuit  300 . The LED pixel may include a plurality of LED chips  200  mounted on the pixel driving integrated circuit  300 , and the LED chips  200  and the pixel driving integrated circuit  300  may be mounted on a package substrate  100 . An external connection terminal  400  such as a solder or a bump may be connected to a lower portion of the package substrate  100 , and a sealing member  500  covering the LED chips  200  and the pixel driving integrated circuit  300  may be further provided. 
     In some example embodiments, the LED chips  200  may include first to third LED chips  210  to  230  disposed on the pixel driving integrated circuit  300 , and the first to third LED chips  210  to  230  may emit light having different colors. For example, the first LED chip  210  may emit red light, the second LED chip  220  may emit green light, and the third LED chip  230  may emit blue light. In this case, the LED package  1000  may be a red, blue, green (RGB) package for full color. 
     In some example embodiments, the first to third LED chips  210  to  230  may emit light having the same color. For example, each of the first to third LED chips  210  to  230  may be an LED chip which emits white light. In this case, the LED package  1000  may be a multi white package for vivid color. 
     In some other example embodiments, colors of light emitted from the first to third LED chips  210  to  230  may further include at least one of various colors such as cyan, yellow, and magenta. 
     The LED chips  200  may be disposed on a top surface of the pixel driving integrated circuit  300 , and thus, light emitted from the LED chips  200  may not be blocked by the pixel driving integrated circuit  300 . 
     The pixel driving integrated circuit  300  may be disposed under the LED chips  200 , and the LED chips  200  may be driven based on an active matrix (AM) mode. Here, the AM mode refer to an addressing method applied to flat display apparatuses. In a display apparatus driven based on the AM mode, each of pixels may include a storage element (for example, a capacitor) for driving a corresponding pixel and a transistor which is programmable for each signal. Pixels included in one scan line may be programmed for a certain time (a frame time/the number of scan lines) on the basis of an external signal. Also, a capacitor included in each of the pixels may hold a voltage of a corresponding pixel, and thus, each pixel may continuously emit light for the other time of a frame. In a process of displaying a moving image by using a display apparatus, a motion may be cut at a certain time interval and may be continuously displayed, and in this case, a time interval corresponding to one scene may be referred to as a frame time. 
     The pixel driving integrated circuit  300  may drive the LED chips  200  on the basis of a pulse width modulation (PWM) mode of a multimode. The pixel driving integrated circuit  300  may adjust a pulse width of a driving current (i.e., an application time of the driving current) flowing through the LED chips  200  during one frame period, for controlling the luminance of the LED chips  200 . 
     The pixel driving integrated circuit  300  may drive the LED chips  200  by performing a duty ratio compensation operation of compensating for a luminance characteristic of each of the LED chips  200 . For example, the duty ratio compensation operation may be performed by using one of a first mode and a second mode. The first mode may be a mode for performing a multiplication operation on first frame data of each of the LED chips  200  and duty ratio compensation data of each of the LED chips  200 , and the second mode may be a mode for performing an addition operation on the first frame data of each of the LED chips  200  and the duty ratio compensation data of each of the LED chips  200 . 
     In example embodiments, the duty ratio compensation operation may be performed by using one of the first mode and the second mode on the basis of the duty ratio compensation data obtained based on a luminance characteristic value of each of the LED chips  200 . For example, when one of the LED chips  200  has luminance which is lower than target luminance, the duty ratio compensation data may include duty ratio compensation information for the first mode (i.e., a multiplication operation). When one of the LED chips  200  has low luminance in a low grayscale or has an abnormal turn-on problem, such as flickering, the duty ratio compensation data may include duty ratio compensation information for the second mode (i.e., an addition operation). A method of calculating duty ratio compensation data on the basis of the luminance characteristic value of each of the LED chips  200  will be described below in detail with reference to  FIGS.  6 A to  6 D . 
     In example embodiments, a duty ratio compensation operation may be performed on all of the first to third LED chips  210  to  230  by using the first mode. In other example embodiments, a duty ratio compensation operation may be performed on all of the first and second LED chips  210  and  220  by using the first mode, and a duty ratio compensation operation may be performed on the third LED chip  230  by using the second mode. In other example embodiments, a duty ratio compensation operation may be performed on all of the first and third LED chips  210  and  230  by using the first mode, and a duty ratio compensation operation may be performed on the second LED chip  220  by using the second mode. A driving method based on a duty ratio compensation operation of the pixel driving integrated circuit  300  will be described below in detail with reference to  FIGS.  3  to  5  and  6 A to  6 D . 
     The pixel driving integrated circuit  300  may be electrically connected to the package substrate  100 , on the package substrate  100 . For example, various wiring structures including a through silicon via (TSV) may be disposed in the pixel driving integrated circuit  300 . The pixel driving integrated circuit  300  may be configured to be electrically connected to the package substrate  100  through a connection terminal such as a solder or a conductive bump. The pixel driving integrated circuit  300  may include a plurality of pads for connecting the package substrate  100  to the pixel driving integrated circuit  300 . The plurality of pads may be provided on a bottom surface of the pixel driving integrated circuit  300 . The plurality of pads may include a data input pad  311  (see  FIG.  2   ), a data output pad  312  (see  FIG.  2   ), a power pad  313  (see  FIG.  2   ), a plurality of clock pads  314  and  315  (see  FIG.  2   ), and a ground pad  316  (see  FIG.  2   ). 
     In the example embodiment of  FIG.  1   , the LED chips  200  may be implemented as a flip chip type. In detail, the LED chips  200  may be connected to the pixel driving integrated circuit  300  through at least one electrode. Also, the pixel driving integrated circuit  300  under the LED chips  200  may include at least one pad for an electrical connection with the LED chips  200 . The LED chips  200  may be electrically connected to the pixel driving integrated circuit  300  by a conductive adhesive material such as eutectic metal, paste, or a solder. 
     The LED chips  200  and the pixel driving integrated circuit  300  may be mounted on the package substrate  100  and may communicate with an external controller  1400  (see  FIG.  16   ) through the package substrate  100  and an external printed circuit board (PCB)  1300  (see  FIG.  16   ). 
     The package substrate  100  may include a plurality of pads for an electrical connection with the pixel driving integrated circuit  300 . The plurality of pads of the package substrate  100  may include a data input pad, a clock pad, a power pad, a data output pad, and a ground pad and may be disposed between the package substrate  100  and the pixel driving integrated circuit  300  so as not to be exposed. An adhesive member such as epoxy, silicone, acrylate, or paste for fixing the plurality of pads therebetween may be disposed between the pixel driving integrated circuit  300  and the package substrate  100 . 
     The LED chips  200  and the pixel driving integrated circuit  300  may be fixed on the package substrate  100  by the sealing member  500  having light-transmitting properties. The sealing member  500  may include an epoxy resin and a silicone resin. The sealing member  500  may further include a filler such as fused silica or carbon black. 
     According to example embodiments, the pixel driving integrated circuit  300  may perform a duty ratio compensation operation through a multiplication operation or an addition operation on the basis of the luminance characteristic value of each of the first to third LED chips  210  to  230 . Therefore, even when the first to third LED chips  210  to  230  have different luminance characteristic values, light having uniform luminance may be emitted from the LED package  1000 . In other words, in terms of binning of the LED chips  200 , even when the LED package  1000  is manufactured by using the LED chips  200  having a relatively large luminance deviation, the LED package  1000  may emit light having good quality (or uniform luminance), thereby decreasing the manufacturing cost of the LED package  1000 . Moreover, the LED package  1000  may enable a display apparatus to display an image where a luminance deviation is compensated for in a grayscale, and thus may increase image quality and may prevent flickering in a low grayscale, thereby increasing the reliability of an operation of a display apparatus including the LED package  1000 . 
       FIG.  2    is a circuit diagram for describing the pixel driving integrated circuit  300  of  FIG.  1   . 
     Referring to  FIG.  2   , the pixel driving integrated circuit  300  may include a plurality of pads  311  to  316 , a deserializer  320 , a first storage area  330 , a second storage area  340 , a PWM data calculator  350 , a constant current generator  360 , and a PWM data generator  370 . 
     The deserializer  320  may receive serial data SDAT from the external controller  1400  (see  FIG.  16   ) through the data input pad  311 , extract and store first frame data of the LED chips  200  from the serial data SDAT, and distribute and output the frame data. 
     In some example embodiments, the first frame data may include pieces of frame data DFR 1 , DFR 2 , and DFR 3  of the LED chips  200  and control data CONT for controlling the PWM data generator  370 . The control data CONT may include a command and clock match data. For example, the pieces of frame data DFR 1 , DFR 2 , and DFR 3  may include grayscale data of an image signal and may further include additional grayscale data to correct undesirable low efficiency and/or wavelength shift for a certain pixel. 
     The deserializer  320  may output serial data SDAT′ other than frame data corresponding to a corresponding pixel driving integrated circuit  300  among the serial data SDAT without separate processing. The serial data SDAT′ may be output through the data output pad  312  and may be provided to a subsequent LED package (for example, an LED package of a next scan line). In a display apparatus  2000  (see  FIG.  14   ), a plurality of LED packages may be serially connected to one another, and serial data SDAT corresponding to one frame period may include pieces of frame data of a plurality of LED packages. 
     For example, an LED package of a first scan line may obtain only frame data thereof and may output the other data to an LED package of a second scan line, and the LED package of the second scan line may obtain only frame data thereof and may output the other data to an LED package of a third scan line. In this manner, LED packages of first to last scan lines may each obtain frame data thereof. 
     The first storage area  330  may store pieces of frame data DFR 1 , DFR 2 , and DFR 3  which are data for respectively driving the first to third LED chips  210  to  230 . The first storage area  330  may store the pieces of frame data DFR 1 , DFR 2 , and DFR 3  provided from the deserializer  320  and may output the pieces of frame data DFR 1 , DFR 2 , and DFR 3  to the PWM data calculator  350 . 
     In example embodiments, the first storage area  330  may be implemented in the form of a latch, a register, or a buffer and may include at least one of volatile memories such as static random access memory (SRAM) and dynamic random access memory (DRAM) and/or non-volatile memories such as electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistance random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM). 
     The second storage area  340  may store pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  respectively including duty ratio compensation coefficients of the first to third LED chips  210  to  230  and may output the pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  to the PWM data calculator  350 . The pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  may respectively include duty ratio compensation coefficients a 1 , a 2 , and a 3  (see  FIG.  4   ) calculated based on the luminance characteristic values of the first to third LED chips  210  to  230 . Also, the pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  may include information which is calculated based on the luminance characteristic values of the first to third LED chips  210  to  230 , for determining a mode (for example, the first mode or the second mode) of a duty ratio compensation operation. 
     In example embodiments, the second storage area  340  may be implemented in the form of a latch, a register, or a buffer and may include at least one of volatile memories such as SRAM and DRAM and/or non-volatile memories such as EEPROM, flash memory, PRAM, RRAM, NFGM, PoRAM, MRAM, and FRAM. 
     The PWM data calculator  350  may perform a duty ratio compensation operation on the basis of the pieces of frame data DFR 1 , DFR 2 , and DFR 3  provided from the first storage area  330  and the pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  provided from the second storage area  340  to generate pieces of PWM data DCP 1 , DCP 2 , and DCP 3  and may output the pieces of PWM data DCP 1 , DCP 2 , and DCP 3  to the PWM data generator  370 . 
     In example embodiments, the PWM data calculator  350  may include a first calculator  352  and a second calculator  354 . The PWM data calculator  350  may perform a duty ratio compensation operation on the basis of one of the first mode and the second mode. The first mode may be an operation mode of performing a multiplication operation on the pieces of frame data DFR 1 , DFR 2 , and DFR 3  provided from the first storage area  330  and the pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  provided from the second storage area  340 . The first mode may be performed by the first calculator  352 , and the first calculator  352  may include a shifter for a multiplication operation. The second mode may be an operation mode of performing an addition operation on the pieces of frame data DFR 1 , DFR 2 , and DFR 3  provided from the first storage area  330  and the pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  provided from the second storage area  340 . The second mode may be performed by the second calculator  354 , and the second calculator  354  may include an adder for an addition operation. 
     For example, the pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  provided from the second storage area  340  to the PWM data calculator  350  may include k-bits (where k is a natural number of 4 or more) data. The pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  may include data of 1 bit for selecting one mode from among the first mode and the second mode and data of k−1 bits indicating a duty ratio compensation coefficient on the basis of the luminance characteristic values of the LED chips  200 . Here, the data of 1 bit for selecting the one mode from among the first mode and the second mode may be referred to as a mode selection bit MDS (see  FIG.  4   ). 
     For example, the duty ratio compensation data DCC 1  for the first LED chip  210  may include a mode selection bit MDS (for example, data “0”) indicating a duty ratio compensation operation of the first mode, and in this case, the first calculator  352  of the PWM data calculator  350  may perform a multiplication operation on the frame data DFR 1  provided from the first storage area  330  and the duty ratio compensation data DCC 1  provided from the second storage area  340  to generate the PWM data DCP 1  and may output the PWM data DCP 1  to the PWM data generator  370 . 
     For example, the duty ratio compensation data DCC 2  for the second LED chip  220  may include a mode selection bit MDS (for example, data “1”) indicating a duty ratio compensation operation of the second mode, and in this case, the second calculator  354  of the PWM data calculator  350  may perform an addition operation on the frame data DFR 2  provided from the first storage area  330  and the duty ratio compensation data DCC 2  provided from the second storage area  340  to generate the PWM data DCP 2  and may output the PWM data DCP 2  to the PWM data generator  370 . 
     The constant current generator  360  may receive a source voltage VDD through the power pad  313  and may generate a reference current on the basis of the source voltage VDD. For example, the constant current generator  360  may include a current mirror. 
     The PWM data generator  370  may generate a plurality of driving currents DI 1 , DI 2 , and DI 3  applied to the first to third LED chips  210  to  230  on the basis of a clock signal CLK received through the first clock pad  314 , a PWM clock signal PCLK received through the second clock pad  315 , the control data CONT provided from the deserializer  320 , the pieces of PWM data DCP 1 , DCP 2 , and DCP 3  provided from the PWM data calculator  350 , and the reference current provided from the constant current generator  360 . 
     The driving currents DI 1 , DI 2 , and DI 3  may be generated based on the PWM mode. For example, a pulse width (for example, an application time of the driving current DI 1 ) of the driving current DI 1  applied to the first LED chip  210  may be adjusted based on the PWM data DCP 1 , a pulse width of the driving current DI 2  applied to the second LED chip  220  may be adjusted based on the PWM data DCP 2 , and a pulse width of the driving current DI 3  applied to the third LED chip  230  may be adjusted based on the PWM data DCP 3 . 
     For example, the clock signal CLK for driving the PWM data generator  370  may have a first frequency, and the PWM clock signal PCLK for modulating the PWM may have a second frequency which is higher than the first frequency, for precisely adjusting pulse widths of the driving currents DI 1 , DI 2 , and DI 3 . 
     In some example embodiments, a unit emission time of each of the first to third LED chips  210  to  230  may be equal to or greater than a period of the PWM clock signal PCLK. In some example embodiments, the unit emission time of each of the first to third LED chips  210  to  230  may be N (where N is an integer of 2 or more) times the period of the PWM clock signal PCLK. For example, the unit emission time of each of the first to third LED chips  210  to  230  may be a multiple of the period of the PWM clock signal PCLK. 
     Each of the first to third LED chips  210  to  230  may include an anode electrode, which receives a corresponding driving current of the driving currents DI 1 , DI 2 , and DI 3  from the PWM data generator  370 , and a cathode electrode connected to the ground pad  316  which provides a ground voltage GND. 
       FIGS.  3  to  5  and  6 A to  6 D  are diagrams for describing an operation of the pixel driving integrated circuit of  FIG.  2   . 
       FIG.  3    is a timing diagram showing data D_STG 1  stored in the first storage area  330 , data D_STG 2  stored in the second storage area  340 , and data D_PDG stored in the PWM data generator  370 , in one frame period of the pixel driving integrated circuit  300 . 
     Referring to  FIGS.  2  and  3   , the pixel driving integrated circuit  300  may drive the first to third LED chips  210  to  230  in the AM mode which entirely uses one frame period. The pixel driving integrated circuit  300  may perform a duty ratio compensation operation on the basis of the data D_STG 1  stored in the first storage area  330  and the data D_STG 2  stored in the second storage area  340  to calculate the data D_PDG stored in the PWM data generator  370 , a first frame period FR 1 , a second frame period FR 2 , and a third frame period FR 3  which are sequentially connected to one another. 
     For example, the first to third frame periods FR 1 , FR 2 , and FR 3  may each include an initial period FRI, an emission period FRE, and a reset period FRS. 
     In the first frame period FR 1 , during the emission period FRE, the pixel driving integrated circuit  300  may receive and distribute the first frame data D_FR 1 , and the first storage area  330  may store the first frame data D_FR 1 . Also, during the emission period FRE, the second storage area  340  may store duty ratio compensation data DCC_FR 1  of each of the first to third LED chips  210  to  230 . In the first frame period FR 1 , the PWM data generator  370  may not generate a driving current, and thus, the first to third LED chips  210  to  230  may not emit light. For example, the PWM data generator  370  may not generate the data D_PDG in the first frame period FR 1 . 
     In the second frame period FR 2  after the first frame period FR 1 , during the initial period FRI, the first frame data D_FR 1  stored in the first storage area  330  may be provided to the PWM data calculator  350 , and the duty ratio compensation data DCC_FR 1  stored in the second storage area  340  may be provided to the PWM data calculator  350 . The PWM data calculator  350  may perform a duty ratio compensation operation on the first frame data D_FR 1  and the duty ratio compensation data DCC_FR 1  (for example, the first calculator  352  may perform a multiplication operation, or the second calculator  354  may perform an addition operation), and thus, the PWM data generator  370  may generate the driving current DI_FR 1  on the basis of a result obtained by performing the duty ratio compensation operation. During the emission period FRE of the second frame period FR 2 , the first to third LED chips  210  to  230  may emit light on the basis of the driving current DI_FR 1 . 
     In the second frame period FR 2 , during the emission period FRE, the pixel driving integrated circuit  300  may receive and distribute the second frame data D_FR 2 , and the first storage area  330  may store the second frame data D_FR 2 . In the third frame period FR 3  after the second frame period FR 2 , during the initial period FRI, the PWM data calculator  350  may perform a duty ratio compensation operation on the second frame data D_FR 2  stored in the first storage area  330  and the duty ratio compensation data DCC_FR 2  stored in the second storage area  340  (for example, the first calculator  352  may perform a multiplication operation, or the second calculator  354  may perform an addition operation), and thus, the PWM data generator  370  may generate the driving current DI_FR 2  on the basis of a result obtained by performing the duty ratio compensation operation. During the emission period FRE of the third frame period FR 3 , the first to third LED chips  210  to  230  may emit light on the basis of the driving current DI_FR 2 . Likewise, during the emission period FRE of the third frame period FR 3 , the pixel driving integrated circuit  300  may receive and distribute the third frame data D_FR 3 , and the first storage area  330  may store the third frame data D_FR 3 , and the second storage area  340  may store the duty ratio compensation data DCC_FR 3 . 
       FIG.  4    is a schematic diagram illustrating a configuration of each of pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3 . 
     Referring to  FIG.  4   , the pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  provided from the second storage area  340  to the PWM data calculator  350  may include data of k bits (where k is a natural number of 4 or more). The pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  may include data of 1 bit for selecting one mode from among the first mode and the second mode and data of k−1 bits including a duty ratio compensation coefficient on the basis of the luminance characteristic values of the LED chips  200 . Here, the data of 1 bit for selecting one mode from among the first mode and the second mode may be referred to as a mode selection bit MDS. 
     As illustrated in  FIG.  4   , when the pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  include data of 5 bits, each of the pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  may include data of 1 bit corresponding to a mode selection bit MDS and data of 4 bits corresponding to duty ratio compensation coefficients a 1 , a 2 , and a 3 . However, the number of bits of the mode selection bit MDS is not limited to the illustration of  FIG.  4   , and the mode selection bit MDS may be implemented with 2 bits or more. Also, the number of bits of the duty ratio compensation coefficients a 1 , a 2 , and a 3  is not limited to the illustration of  FIG.  4   , and the duty ratio compensation coefficients a 1 , a 2 , and a 3  may each be implemented with fewer bits or more bits. 
       FIG.  5    is a timing diagram showing a plurality of driving currents DI 1 , DI 2 , and DI 3  applied to the first to third LED chips  210  to  230 . 
     Referring to  FIG.  5   , the driving current DI 1  applied to the first LED chip  210  may have a first level I 1  and a first pulse width W 1 F, the driving current DI 2  applied to the second LED chip  220  may have a second level  12  and a second pulse width W 2 F, and the driving current DI 3  applied to the third LED chip  230  may have a third level  13  and a third pulse width W 3 F. As a width of a driving current increases, the LED chips  200  may emit light having a higher grayscale (or luminance). 
     The driving current DI 1  applied to the first LED chip  210  may have the first level I 1  and the first pulse width W 1 F, and thus, the first LED chip  210  may emit light for a first time period corresponding to the first pulse width W 1 F. For example, the first pulse width W 1 F may be a pulse width (an application time) obtained by performing a multiplication operation on a first input pulse width W 1 I and a first duty ratio compensation coefficient a 1 . For example, the first frame data DFR 1  stored in the first storage area  330  may include information about the first input pulse width W 1 I, and the duty ratio compensation data DCC 1  stored in the second storage area  340  may include information about the first duty ratio compensation coefficient a 1  and information about a multiplication operation. When the first LED chip  210  has a luminance characteristic which is lower than target luminance, the first duty ratio compensation coefficient a 1  may have a value which is greater than 1. Therefore, the first LED chip  210  may emit light for the first time period corresponding to the first pulse width W 1 F obtained by performing a multiplication operation on the first duty ratio compensation coefficient a 1  and the first input pulse width W 1 I of the first LED chip  210 , and the first LED chip  210  may have luminance corresponding to (or similar to the target luminance) the target luminance. As the first duty ratio compensation coefficient a 1  has the value which is greater than 1, the first pulse width W 1 F may be wider than the first input pulse width W 1 I, and the first LED chip  210  may be compensated to have a relatively brighter luminance. 
     Similarly, the driving current DI 2  applied to the second LED chip  220  may have a second level  12  and a second pulse width W 2 F, and thus, the second LED chip  220  may emit light for a second time period corresponding to the second pulse width W 2 F. For example, the second pulse width W 2 F may be a pulse width (an application time) obtained by performing an addition operation on a second input pulse width W 2 I and a second duty ratio compensation coefficient a 2 . For example, the frame data DFR 2  stored in the first storage area  330  may include information about the second input pulse width W 2 I, and the duty ratio compensation data DCC 2  stored in the second storage area  340  may include information about the second duty ratio compensation coefficient a 2  and information about an addition operation. The second LED chip  220  may be configured so that duty ratio compensation is performed based on the second duty ratio compensation coefficient a 2  and an addition operation when a flickering phenomenon such as unstable flickering occurs in the second LED chip  220  in a low grayscale. Therefore, the second LED chip  220  may emit light for the second time period corresponding to the second pulse width W 2 F obtained by performing an addition operation on the second duty ratio compensation coefficient a 2  and the second input pulse width W 2 I of the second LED chip  220 , and the second LED chip  220  may have luminance corresponding to (or similar to the target luminance) the target luminance and may prevent unstable flickering in the low grayscale. As the second duty ratio compensation coefficient a 2  is being added to the second input pulse width W 2 I, the second pulse width W 2 F may be wider than the second input pulse width W 2 I, and the second LED chip  220  may be compensated to have a relatively brighter luminance. 
     Similarly, the driving current DI 3  applied to the third LED chip  230  may have a third level  13  and a third pulse width W 3 F, and thus, the third LED chip  230  may emit light for a third time period corresponding to the third pulse width W 3 F. For example, the third pulse width W 3 F may be a pulse width (an application time) obtained by performing a multiplication operation on a third input pulse width W 3 I and a third duty ratio compensation coefficient a 3 . For example, the frame data DFR 3  stored in the first storage area  330  may include information about the third input pulse width W 3 I, and the duty ratio compensation data DCC 3  stored in the second storage area  340  may include information about the third duty ratio compensation coefficient a 3  and information about a multiplication operation. When the third LED chip  230  has a luminance characteristic which is higher than the target luminance, the third duty ratio compensation coefficient a 3  may have a value which is less than 1. Therefore, the third LED chip  230  may emit light for the third time period corresponding to the third pulse width W 3 F obtained by performing a multiplication operation on the third duty ratio compensation coefficient a 3  and the third input pulse width W 3 I of the third LED chip  230 , and the third LED chip  230  may have luminance corresponding to (or similar to the target luminance) the target luminance. As the third duty ratio compensation coefficient a 3  has the value which is less than 1, the third pulse width W 3 F may be narrower than the third input pulse width W 3 I, and the third LED chip  230  may be compensated to have a relatively dimmer luminance. 
     In embodiments, the first level I 1 , the second level  12 , and the third level  13  may be the same. Due to a process distribution and a wavelength difference between emitted light, the first to third LED chips  210  to  230  may have different luminance characteristics with respect to a forward voltage Vf and a current and may differ in wavelength shift. Therefore, it may be difficult to apply a PWM mode of controlling a level of a current to adjust a grayscale, and when a PWM mode of controlling an emission time to adjust a grayscale in a state where a level of a current is fixed is applied, wavelength shift caused by an input current or problems such as a distribution and low efficiency caused by a low current may be prevented and emission efficiency may be increased. However, example embodiments are not limited thereto, and in other example embodiments, the pixel driving integrated circuit  300  may further include a current adjuster and may be configured so that at least one of the first level I 1 , the second level  12 , and the third level  13  has a different value. 
       FIG.  6 A  is a flowchart illustrating a method of determining duty ratio compensation data, according to example embodiments.  FIG.  6 B  is a schematic graph for describing a multiplication operation method of  FIG.  6 A .  FIG.  6 C  is a schematic graph for describing an addition operation method of  FIG.  6 A .  FIG.  6 D  is a schematic diagram showing duty ratio compensation data obtained in each operation of  FIG.  6 A . In detail,  FIGS.  6 A to  6 D  schematically illustrate an exemplary method of determining duty ratio compensation data for generating the pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  of the LED chips  210  to  230  stored in the second storage area  340  of the pixel driving integrated circuit  300 . 
     Referring to  FIGS.  6 A to  6 D , the LED chips  200  may be turned on at an initial duty ratio in operation S 110 . 
     Luminance of light emitted from the LED chips  200  may be measured in operation S 120 . Measurement luminance LMk 0  of each of the LED chips  200  may be obtained. For example, measurement luminances LM 10 , LM 20 , and LM 30  of the first to third LED chips  210  to  230  may be obtained. 
     In example embodiments, as illustrated in  FIG.  6 B , the measurement luminance LMk 0  of each of the LED chips  200  may be obtained by sweeping a pulse width of a driving current (or an application time of the driving current) applied to the LED chips  200 . For example, by gradually increasing the pulse width (or the application time) of the driving current applied to the LED chips  200 , emission intensity of each pulse width may be measured. 
     A duty ratio multiplication compensation coefficient axk may be calculated based on a ratio of target luminance LMT to the measurement luminance LMk 0  of each of the LED chips  200  in operation S 130 . For example, first to third duty ratio compensation coefficients ax 1 , ax 2 , and ax 3  may be calculated based on a ratio of the target luminance LMT to each of the measurement luminances LM 10 , LM 20 , and LM 30  of the first to third LED chips  210  to  230 . 
     In example embodiments, in a case where luminance is measured by sweeping a pulse width of a driving current applied to the LED chips  200 , the duty ratio multiplication compensation coefficient axk may be calculated based on the following Equation 1:
 
 axk=S _ LMT/S _ LMk 0  (Equation 1)
 
     In Equation 1, axk may denote a duty ratio multiplication compensation coefficient of a k th  LED chip, S_LMk 0  may denote a slope of measurement luminance with respect to a pulse width of the k th  LED chip, and S_LMT may denote a slope of target luminance with respect to the pulse width) 
     For example, when the slope S_LMk 0  of the measurement luminance LMk 0  of each of the LED chips  200  is less than the slope S_LMT of the target luminance LMT, the duty ratio multiplication compensation coefficient axk may have a value which is greater than 1. When the slope S_LMk 0  of the measurement luminance LMk 0  of each of the LED chips  200  is greater than the slope S_LMT of the target luminance LMT, the duty ratio multiplication compensation coefficient axk may have a value which is less than 1. 
     According to an example embodiment shown in the timing diagram of  FIG.  5   , a slope S_LMk 0  of the measurement luminance LM 10  of the first LED chip  210  may be less than the slope S_LMT of the target luminance LMT, and a first duty ratio multiplication compensation coefficient ax 1  may have a value which is greater than 1. A slope S_LMk 0  of the measurement luminance LM 20  of the second LED chip  220  may be less than the slope S_LMT of the target luminance LMT, and a second duty ratio multiplication compensation coefficient ax 2  may have a value which is greater than 1. Also, a slope S_LMk 0  of the measurement luminance LM 30  of the third LED chip  230  may be greater than the slope S_LMT of the target luminance LMT, and a third duty ratio multiplication compensation coefficient ax 3  may have a value which is less than 1. 
     The LED chips  200  may be turned on at a compensation duty ratio in operation S 140 . The compensation duty ratio may have a value obtained by performing a multiplication operation on an initial duty ratio and the duty ratio multiplication compensation coefficient axk. For example, when the duty ratio multiplication compensation coefficient axk is greater than 1, the compensation duty ratio may be greater than the initial duty ratio, and when the duty ratio multiplication compensation coefficient axk is less than 1, the compensation duty ratio may be less than the initial duty ratio. 
     Luminance of light emitted from each of the LED chips  200  may be measured, and first measurement luminance LMk 1  of each of the LED chips  200  may be obtained in operation S 150 . For example, first measurement luminances LM 11 , LM 21 , and LM 31  of the first to third LED chips  210  to  230  may be obtained. 
     In operation S 160 , a luminance difference between the first measurement luminance LMk 1  of each of the LED chips  200  and the target luminance LMT may be compared with a luminance deviation reference value LMS. In example embodiments, the luminance deviation reference value LMS may include about 10% or less, about 5% or less, about 3% or less, about 2% or less, or about 1% or less of the target luminance LMT, but is not limited thereto and the luminance deviation reference value LMS may vary based on a characteristic needed for an application including the LED package  1000 . 
     For example, when the luminance difference between the first measurement luminance LMk 1  of each of the LED chips  200  and the target luminance LMT is equal to or less than the luminance deviation reference value LMS, the duty ratio multiplication compensation coefficient axk may be stored in the second storage area  340  in operation S 170 . 
     For example, when the luminance difference between the first measurement luminance LMk 1  of each of the LED chips  200  and the target luminance LMT is greater than the luminance deviation reference value LMS, an additional operation may be performed on a duty ratio addition compensation coefficient ayk from a luminance difference between the measurement luminance LMk 0  of each of the LED chips  200  and the target luminance LMT in operation S 180 . 
     The duty ratio addition compensation coefficient ayk may correspond to a difference value between the target luminance LMT and the measurement luminance LMk 0 . The duty ratio addition compensation coefficient ayk may be a compensation coefficient for an addition operation performed on a duty ratio. 
     In example embodiments, in a case where luminance is measured by sweeping a pulse width of a driving current applied to the LED chips  200 , the duty ratio addition compensation coefficient ayk may be determined as an arithmetic average of luminance difference values between the target luminance LMT and the measurement luminance LMk 0  of the LED chips  200  obtained at a plurality of sampling points P 1 , P 2 , . . . , and Pn (for example, obtained in a plurality of pulse widths), and the duty ratio addition compensation coefficient ayk may be calculated based on the following Equation 2:
 
 ayk =(Δ LM 1+Δ LM 2+ . . . +Δ LMn )/ n   (Equation 2)
 
     In Equation 2, ayk may denote a duty ratio addition compensation coefficient of the k th  LED chip, n may denote the number of sampling points (for example, n may be 3 to 10), ΔLM 1  may denote a difference between target luminance and measurement luminance at a first sampling point P 1 , ΔLM 2  may denote a difference between target luminance and measurement luminance at a second sampling point P 2 , and ΔLMn may denote a difference between target luminance and measurement luminance at an n th  sampling point Pn). 
     Subsequently, the LED chips  200  may be turned on at an additionally-calculated compensation duty ratio in operation S 140 . The additionally-calculated compensation duty ratio may have a value obtained through an addition operation performed on the initial duty ratio and the duty ratio addition compensation coefficient ayk. 
     Luminance of light emitted from each of the LED chips  200  may be measured in operation S 150 . Second measurement luminance LMk 2  of each of the LED chips  200  may be obtained. 
     In operation S 160 , a luminance difference between the second measurement luminance LMk 2  of each of the LED chips  200  and the target luminance LMT may be compared with the luminance deviation reference value LMS. For example, when the luminance difference between the second measurement luminance LMk 1  of each of the LED chips  200  and the target luminance LMT is equal to or less than the luminance deviation reference value LMS, the duty ratio addition compensation coefficient ayk may be stored in the second storage area  340  in operation S 170 . 
     According to an example embodiment shown in the timing diagram of  FIG.  5   , the first and third LED chips  210  and  230  may store first and third duty ratio multiplication compensation coefficients ax 1  and ax 3 , obtained from a ratio of the target luminance LMT to the measurement luminances LM 10  and LM 30 , in the second storage area  340 , and the second LED chip  220  may store second duty ratio addition compensation coefficient ay 2 , obtained from a difference between the measurement luminance LM 20  and the target luminance LMT through an additional operation, in the second storage area  340 . That is, the first duty ratio compensation coefficient a 1  may correspond to a value of the first duty ratio multiplication compensation coefficient ax 1 , the second duty ratio compensation coefficient a 2  may correspond to a value of the second duty ratio addition compensation coefficient ay 2 , and the third duty ratio compensation coefficient a 3  may correspond to a value of the third duty ratio multiplication compensation coefficient ax 3 . 
     In this case, the pieces of duty ratio compensation data DCC 1  and DCC 3  of the first and third LED chips  210  and  230  may each include data of 1 bit (for example, a mode selection bit MDS of “0”) for performing a duty ratio compensation operation on the basis of the first mode corresponding to a multiplication operation. The duty ratio compensation data DCC 2  of the second LED chip  220  may include data of 1 bit (for example, a mode selection bit MDS of “1”) for performing a duty ratio compensation operation on the basis of the second mode corresponding to an addition operation. 
     For example, the duty ratio compensation data DCC 1  of the first LED chip  210  may include k bits, which may include a mode selection bit MDS (for example, data “0”) for selecting the first mode and data of k−1 bits including the first duty ratio compensation coefficient a 1  based on a luminance characteristic value of the first LED chip  210 . The duty ratio compensation data DCC 2  of the second LED chip  220  may include k bits, which may include a mode selection bit MDS (for example, data “1”) for selecting the second mode and data of k−1 bits including the second duty ratio compensation coefficient a 2  based on a luminance characteristic value of the second LED chip  220 . The duty ratio compensation data DCC 3  of the third LED chip  230  may include k bits, which may include a mode selection bit MDS (for example, data “0”) for selecting the first mode and data of k−1 bits including the third duty ratio compensation coefficient a 3  based on a luminance characteristic value of the third LED chip  230 . 
     In  FIGS.  4  to  6 D , an example embodiment has been described where a duty ratio compensation operation of the first mode corresponding to a multiplication operation is performed on the first and third LED chips  210  and  230 , and a duty ratio compensation operation of the second mode corresponding to an addition operation is performed on the second LED chip  220 . However, example embodiments are not limited thereto, and in other example embodiments, various combinations where a duty ratio compensation operation of one of the first mode and the second mode is performed may be implemented. 
     When the duty ratio compensation coefficients a 1 , a 2 , and a 3  of all pixels are calculated, a compensation method may end. 
     A method of determining the pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  according to example embodiments may be performed in a process of manufacturing the LED package  1000 . In this case, the pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  of the first to third LED chips  210  to  230  may be determined in a process of manufacturing the LED package  1000  and may be stored in the second storage area  340 , and a plurality of duty ratio-compensated driving currents DI 1 , DI 2 , and DI 3  where a duty ratio has been compensated for based on the pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  stored in the second storage area  340  may be applied to the first to third LED chips  210  to  230  in a process of performing operations of the first to third LED chips  210  to  230 . In other example embodiments, a method of determining the pieces of duty ratio compensation data DCC 1 , DCC 2 , and DCC 3  may be periodically performed in a process of performing an operation of the LED package  1000 , and the newly determined duty ratio compensation coefficients a 1 , a 2 , and a 3  may be stored in the second storage area  340  again. 
     Generally, in a passive matrix (PM) mode, N (where N is an integer of 2 or more) LED packages may be serially connected to one another and may be driven by one integrated circuit. One frame period is divided into N division periods and one LED package is driven during one division period. In this case, in a low grayscale period, when flickering occurs before a sufficient voltage is applied to an LED chip, a flickering phenomenon may occur. Also, an afterimage or a ghost phenomenon occurs where a previous pixel blurredly re-emits light due to a parasitic capacitance which occurs in an LED package due to flickering between pixels. 
     On the other hand, in an AM mode according to example embodiments, each LED package may include a pixel driving integrated circuit, and thus, even when N number of LED packages are serially connected to one another, each of the LED packages may be driven by using an entirety of one frame period. Therefore, in contrast to the passive matrix mode, a turn-on time of one LED package may increase, and thus, the above-described flickering phenomenon may not occur. Also, an emission operation of a current frame may be performed based on frame data of a previous frame, and a reset period FRS may be between adjacent frame periods, whereby the above-described ghost phenomenon may not occur. 
     Also, in the LED package  1000  according to example embodiments, the pixel driving integrated circuit  300  may perform a duty ratio compensation operation through a multiplication operation or an addition operation on the basis of the luminance characteristic value of each of the first to third LED chips  210  to  230 . Therefore, even when the first to third LED chips  210  to  230  have different luminance characteristic values, light having uniform luminance may be emitted from the LED package  1000 . In other words, in terms of binning of the LED chips  200 , even when the LED package  1000  is manufactured by using the LED chips  200  having a relatively large luminance deviation, the LED package  1000  may emit light having uniform luminance, thereby decreasing the manufacturing cost of the LED package  1000 . Moreover, the LED package  1000  may enable a display apparatus to display an image where a luminance deviation is compensated for in a grayscale, and thus may increase image quality and may prevent flickering in a low grayscale, thereby increasing the reliability of an operation of a display apparatus including the LED package  1000 . 
       FIG.  7    is a circuit diagram for describing a pixel driving integrated circuit  300 A according to example embodiments. In  FIG.  7   , the same reference numerals as  FIGS.  1  to  6 D  refer to the same elements. 
     Referring to  FIG.  7   , the pixel driving integrated circuit  300 A may further include a detector  380 . When an electrical defect occurs in at least one of first to third LED chips  210  to  230 , the detector  380  may detect the electrical defect to generate a failure detection signal FDS. For example, the electrical defect may include an undesired short circuit or open between the first to third LED chips  210  to  230  and the pixel driving integrated circuit  300 A. 
     In some example embodiments, the failure detection signal FDS may be fed back to an external controller ( 1400  of  FIG.  16   ). In this case, the external controller may limit driving of the first to third LED chips  210  to  230  on the basis of the failure detection signal FDS. The pixel driving integrated circuit  300 A may further include a feedback pad for providing the failure detection signal FDS to the external controller. 
     In some other example embodiments, the failure detection signal FDS may be fed back to the first storage area  330 , and the first storage area  330  may limit (for example, masking) driving of the first to third LED chips  210  to  230  on the basis of the failure detection signal FDS. 
     In some other example embodiments, the failure detection signal FDS may be fed back to a PWM data generator  370 , and the PWM data generator  370  may limit (for example, masking) driving of the first to third LED chips  210  to  230  on the basis of the failure detection signal FDS. 
       FIG.  8    is a circuit diagram for describing a pixel driving integrated circuit  300 B according to example embodiments. 
     Referring to  FIG.  8   , the pixel driving integrated circuit  300 B may further include a clock generator  385 , and the first clock pad  314  (see  FIG.  2   ) and the second clock pad  315  (see  FIG.  2   ) may be omitted. 
     Frame data distributed by a deserializer  320  may further include clock data CCON. The clock generator  385  may generate a clock signal CLK and a PWM clock signal PCLK on the basis of the clock data CCON. 
       FIG.  9    is a circuit diagram for describing a pixel driving integrated circuit  300 C according to example embodiments. 
     Referring to  FIG.  9   , the pixel driving integrated circuit  300 C may further include an oscillator  390 , and the second clock pad  315  (see  FIG.  2   ) may be omitted. 
     The oscillator  390  may generate a PWM clock signal PCLK on the basis of a clock signal CLK received through a first clock pad  314 . For example, the oscillator  390  may include a ring oscillator, an RC oscillator, a crystal oscillator, or a temperature compensation crystal oscillator, but is not limited thereto. 
       FIG.  10    is a circuit diagram for describing a pixel driving integrated circuit  300 D according to example embodiments. 
     Referring to  FIG.  10   , the pixel driving integrated circuit  300 D may include an electrostatic discharge (ESD) protection circuit  395 . The ESD protection circuit  395  may be connected to a power pad  313 . The ESD protection circuit  395  may protect elements of the pixel driving integrated circuit  300 D from a large amount of electric charges which flow in from the outside when an ESD event occurs. In other example embodiments, the ESD protection circuit  395  may be further connected to a ground pad  316 . 
     The pixel driving integrated circuit  300 D may further include an ESD protection circuit connected to at least one of a data input pad  311 , a data output pad  312 , and first and second clock pads  314  and  315 . 
       FIG.  11    is a perspective view illustrating an LED package  1001  according to example embodiments. 
     Referring to  FIG.  11   , the LED package  1001  may include a package substrate  101 , first to third LED chips  210  to  230 , a pixel driving integrated circuit  301 , an external connection terminal  400 , a plurality of bonding wires  420 , and a sealing member  500 . 
     The package substrate  101  and the pixel driving integrated circuit  301  may be connected to each other by a wire bonding manner by using the plurality of bonding wires  420 . The package substrate  101  may include a plurality of pads  111  to  116 , which are electrically connected to a plurality of pads  311  to  316  of the pixel driving integrated circuit  301  and are horizontally apart from the pixel driving integrated circuit  301 . The plurality of pads  111  to  116  may include a data input pad  111 , a data output pad  112 , a power pad  113 , a plurality of clock pads  114  and  115 , and a ground pad  116 . 
     The pixel driving integrated circuit  301  may include the plurality of pads  311  to  316  which are electrically connected to the package substrate  101  and are provided on a top surface (i.e., a surface opposite to a surface facing the package substrate  101 ) of the pixel driving integrated circuit  301 . For example, the plurality of pads  311  to  316  may include a data input pad  311 , a data output pad  312 , a power pad  313 , a plurality of clock pads  314  and  315 , and a ground pad  316 . The plurality of pads  111  to  116  of the package substrate  101  may be connected to the plurality of pads  311  to  316  of the pixel driving integrated circuit  301  by the plurality of bonding wires  420 . 
       FIG.  12    is a perspective view illustrating an LED package  1002  according to example embodiments. 
     Referring to  FIG.  12   , the LED package  1002  may include a package substrate  102 , first to third LED chips  212 ,  222 , and  232 , a pixel driving integrated circuit  302 , an external connection terminal  400 , a plurality of bonding wires  420  and  430 , and a sealing member  500 . 
     The package substrate  102  and the pixel driving integrated circuit  302  may be connected to each other by a wire bonding manner by using the plurality of bonding wires  420  and  430 . The first to third LED chips  212 ,  222 , and  232  may include an epi-up chip (i.e., a non-flip chip), and thus, may be connected to the pixel driving integrated circuit  302  by a bonding wire manner. 
     The package substrate  102  may be substantially the same as the package substrate  101  of  FIG.  11   , and thus, a repetitive description thereof is omitted. 
     The pixel driving integrated circuit  302  may further include first to third pads  318 A,  318 B, and  318 C for electrical connections with the first to third LED chips  212 ,  222 , and  232 . The bonding wires  420  may be for electrically connecting the package substrate  102  to the pixel driving integrated circuit  302 . The bonding wires  430  may be for electrically connecting the first to third LED chips  212 ,  222 , and  232  to the pixel driving integrated circuit  302 . In detail, the bonding wires  430  may respectively connect the first to third LED chips  212 ,  222 , and  232  to the first to third pads  318 A,  318 B, and  318 C. 
       FIG.  13    is a perspective view illustrating an LED package  1003  according to example embodiments. 
     Referring to  FIG.  13   , the LED package  1003  may include a plurality of LED chips  203 A,  203 B,  203 C, and  203 D and a plurality of pixel driving integrated circuits  303 A,  303 B,  303 C, and  303 D and may further include a package substrate  103 , a sealing member  503 , and a plurality of bonding wires  420 . 
     Unlike the LED package  1000  having a single structure of  FIG.  1    where one LED pixel and one pixel driving integrated circuit  300  are provided on one package substrate  100 , in the LED package  1003  of  FIG.  13   , a plurality of LED pixels and the plurality of pixel driving integrated circuits  303 A,  303 B,  303 C, and  303 D may be provided on one package substrate  103 . Particularly, in the example embodiment of  FIG.  13   , a 4-in-1 structure where four LED pixels are provided on one package substrate  103  is illustrated. However, example embodiments are not limited thereto, and an M-in-1 structure where M (where M is a natural number of 2 or more) number of LED pixels are provided on one package substrate may be widely applied. 
     As illustrated in  FIG.  13   , by using a connection wiring  140  included in the package substrate  103 , a data output terminal of the pixel driving integrated circuit  303 A may be connected to a data input terminal of the pixel driving integrated circuit  303 B, and a data output terminal of the pixel driving integrated circuit  303 C may be connected to a data input terminal of the pixel driving integrated circuit  303 D. As described above, because the 4-in-1 structure is applied, the number of lower pins of the package substrate  103  may decrease, and thus, high-resolution data may be processed at a high speed. 
       FIG.  14    is a perspective view for describing a display apparatus  2000  according to example embodiments.  FIG.  15    is a plan view illustrating the enlargement of a region CX 1  of  FIG.  14   .  FIG.  16    is a cross-sectional view of the display apparatus  2000  of  FIG.  14   . 
     Referring to  FIGS.  14  to  16   , the display apparatus  2000  may include an LED module  1200  including a plurality of LED packages  1100 , a PCB  1300 , and a controller  1400 . 
     The PCB  1300  may be referred to as a module board and may include a complicated internal wiring for connecting the plurality of LED packages  1100  to the controller  1400 . 
     The plurality of LED packages  1100  may be disposed on a first surface of the PCB  1300  and may include one of the LED packages  1000 ,  1001 ,  1002 , and  1003  illustrated in  FIGS.  1  to  13   . Each of the plurality of LED packages  1100  may configure one pixel of the display apparatus  2000 , and the plurality of LED packages  1100  may be arranged to configure rows and columns in an X direction and a Y direction on the PCB  1300 . In  FIG.  14   , a case where the display apparatus  2000  includes the plurality of LED packages  1100  arranged in a 15*15 matrix form is illustrated, but example embodiments are not limited thereto. The display apparatus  2000  may include a plurality of LED packages which are variously arranged, for example, 1024*768, 1920*1080, etc., based on a resolution which is to be realized. 
     The controller  1400  may be disposed on a second surface opposite to the first surface of the PCB  1300  and may control driving of the plurality of LED packages  1100 . For example, the controller  1400  may provide a signal and power for driving a pixel driving integrated circuit included in each of the plurality of LED packages  1100 . In  FIG.  14   , only one controller  1400  is illustrated, but example embodiments are not limited thereto, and a plurality of controllers may be disposed on the second surface of the PCB  1300 . The number of controllers may be determined based on the total number of LED packages  1100  and the number of LED packages driven by one controller  1400 . 
     As illustrated in  FIG.  15   , the display apparatus  2000  may further include a first partition wall structure  1210  which defines a region, where the plurality of LED packages  1100  are disposed, of the PCB  1300 . Also, each of the plurality of LED packages  1100  may be disposed to be surrounded by a second partition wall structure  1220 . Each of the plurality of LED packages  1100  may be electrically isolated by the second partition wall structure  1220  and may be independently driven as a separate pixel. In some example embodiments, the first and second partition wall structures  1210  and  1220  may each include a black matrix, but are not limited thereto. 
     As illustrated in  FIG.  16   , LED packages  1100  disposed in the same row or column may be serially connected to one another through wirings  1310  of the PCB  1300 . Therefore, each of the LED packages  1100  may obtain only frame data thereof from among pieces of serial data transferred from the controller  1400  and may transfer the other data to a next LED package. 
     While aspects of example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.