Patent Publication Number: US-10782559-B2

Title: Reflective liquid crystal display panel

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This is a divisional application of and claims the priority benefit of U.S. patent application Ser. No. 15/494,550, filed on Apr. 24, 2017, now allowed, which claims the priority benefit of Chinese patent application serial no. 201611244038.9, filed on Dec. 29, 2016. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of the specification. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to a liquid crystal display panel, and particularly relates to a reflective liquid crystal display panel. 
     Description of Related Art 
     In recent years, E-papers and E-books are quickly developed. Under the needs of low power consumption, the E-papers and the E-books generally adopt a reflective display device to display images, where an adopted display medium includes liquid crystal, electrophoretic display medium, electrochromic display medium, electrolytic precipitation display medium, etc., and a reflective liquid crystal display with liquid crystal draws extensive attention. Generally, if only a text is displayed, two gray scales of black and white are enough, though if a color graded image is displayed while considering the low power consumption, the two gray scales of black and white are not enough. Presently, the reflective liquid crystal display still has a problem of inadequate number of gray scales that causes a poor visual effect, so that it is one of the targets to be achieved by related researchers to expand the number of gray scales. 
     SUMMARY OF THE INVENTION 
     The invention is directed to a reflective liquid crystal display panel, which is adapted to display 16 gray scale levels, so as to achieve a good visual effect. 
     The invention provides a reflective liquid crystal display panel having a display area and a periphery area surrounding the display area, and including a plurality of pixel units disposed in the display area, where each of the pixel units includes a first substrate, one first signal line, four second signal lines, a first pixel structure, a second pixel structure, a third pixel structure, a fourth pixel structure, a second substrate, and a liquid crystal layer. The one first signal line and the four second signal lines are disposed on the first substrate. The first pixel structure, the second pixel structure, the third pixel structure and the fourth pixel structure are electrically connected to one of the four second signal lines respectively and are electrically connected to the first signal line, where the first pixel structure, the second pixel structure, the third pixel structure and the fourth pixel structure respectively include an active component and a reflective pixel electrode electrically connected to the active component, and a reflection area ratio of the first pixel structure, the second pixel structure, the third pixel structure and the fourth pixel structure is one of 1:2:4:8 and 2:1:4:8. The second substrate is located opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. 
     According to the above description, each of the pixel units includes the first pixel structure, the second pixel structure, the third pixel structure and the fourth pixel structure with the reflection area ratio of one of 1:2:4:8 and 2:1:4:8, and the first pixel structure, the second pixel structure, the third pixel structure and the fourth pixel structure are electrically connected to one of the four second signal lines respectively and are electrically connected to the first signal line. The reflective liquid crystal display panel of the invention has a novel structure, and is adapted to display 16 gray scale levels to achieve a good visual effect. 
     In order to make the aforementioned and other features and advantages of the invention comprehensible, several exemplary embodiments accompanied with figures are described in detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
         FIG. 1  is a top view of a reflective liquid crystal display panel according to a first embodiment of the invention. 
         FIG. 2  is a cross-sectional view along a section line A-A′ of  FIG. 1 . 
         FIG. 3  is a top view of a reflective liquid crystal display panel according to a second embodiment of the invention. 
         FIG. 4  is a partial cross-sectional view of a reflective liquid crystal display panel according to a third embodiment of the invention. 
         FIG. 5  is a top view of a reflective liquid crystal display panel according to a fourth embodiment of the invention. 
         FIG. 6  is a cross-sectional view along a section line A-A′ of  FIG. 5 . 
         FIG. 7  is a top view is of a reflective liquid crystal display panel according to a fifth embodiment of the invention. 
         FIG. 8  is a cross-sectional view along a section line A-A′ of  FIG. 7 . 
         FIG. 9  is a partial cross-sectional view of a reflective liquid crystal display panel according to a sixth embodiment of the invention. 
         FIG. 10  is a top view of a reflective liquid crystal display panel according to a seventh embodiment of the invention. 
         FIG. 11  is a cross-sectional view along a section line A-A′ of  FIG. 10 . 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
       FIG. 1  is a top view of a reflective liquid crystal display panel according to a first embodiment of the invention.  FIG. 2  is a cross-sectional view along a section line A-A′ of  FIG. 1 . 
     Referring to  FIG. 1  and  FIG. 2 , the reflective liquid crystal display panel  10  has a display area AA and a periphery area BB outside the display area AA. In the present embodiment, the periphery area BB, for example, surrounds the display area AA. The reflective liquid crystal display panel  10  includes a plurality of pixel units U disposed in the display area AA. In detail, each of the pixel units U includes a first substrate  100 , one first signal line, four second signal lines, a first pixel structure P 1 , a second pixel structure P 2 , a third pixel structure P 3 , a fourth pixel structure P 4 , a second substrate  110 , and a liquid crystal layer  120 . In the present embodiment, the first signal line is exemplified by a data line DL, and the four second signal lines are exemplified by a first scan line SL 1 , a second scan line SL 2 , a third scan line SL 3  and a fourth scan line SL 4 . Moreover, in the present embodiment, the pixel unit U further includes a common electrode layer  130 , an insulation layer PV, a cover layer BP, a counter electrode layer  140  and a spacer PS. Moreover, in the present embodiment, the reflective liquid crystal display panel  10  further includes a thin-film transistor integrated gate driver  150  disposed in the periphery area BB. For simplicity&#39;s sake, only one pixel unit U is illustrated in  FIG. 1 , though the reflective liquid crystal display panel  10  is actually composed of a plurality of pixel units U arranged in an array, and the second substrate  120 , the counter electrode layer  140 , the liquid crystal layer  120 , the cover layer BP, the insulation layer PV and the gate insulation layer GI, etc., are omitted in  FIG. 1 . 
     In the present embodiment, an operation mode of the reflective liquid crystal display panel  10  is, for example, an electrically controlled birefringence (EBC) mode, a vertical alignment (VA) mode, a twist nematic (TN) mode, an in plane switch (IPS) mode, a fringe field switch (FFS) mode, an optical compensation bend (OCB) mode. Therefore, the reflective liquid crystal display panel  10  of the present embodiment is not limited to  FIG. 1  and  FIG. 2 , and those skilled in the art should understand that the reflective liquid crystal display panel  10  can be further configured with other required components, such as an alignment film, a polarizing plate. 
     Moreover, in the present embodiment, the scanning frequency of the reflective liquid crystal display panel  10  is higher than 0 and less than or equal to 20 Hz, and is preferably 1 Hz to 15 Hz. Namely, the reflective liquid crystal display panel  10  is adapted to implement low-frequency operations to achieve a power-saving effect. 
     The material of the first substrate  100  can be glass, quartz or organic polymer. The second substrate  110  is located opposite to the first substrate  100 . The material of the second substrate  110  can be glass, quartz or organic polymer. 
     The liquid crystal layer  120  is disposed between the first substrate  100  and the second substrate  110 . In detail, the liquid crystal layer  120  includes a plurality of liquid crystal molecules (not shown), and proper liquid crystal molecules are selected according to different operation modes. 
     The counter electrode layer  140  is disposed on the second substrate  110 , and is located between the second substrate  110  and the liquid crystal layer  120 . The material of the counter electrode layer  140  is, for example, a high transmittance material such as indium-tin oxide, indium-zinc oxide, aluminium-tin oxide, aluminium-zinc oxide or a combination thereof. Moreover, in the present embodiment, the liquid crystal molecules in the liquid crystal layer  120  are driven by an electric field between pixel structures and the counter electrode layer  140 . 
     The first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3 , the fourth scan line SL 4 , the data line DL are disposed on the first substrate  100 . The extending direction of the first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3  and the fourth scan line SL 4  is different from the extending direction of the data line DL, and preferably the extending direction of the first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3  and the fourth scan line SL 4  is perpendicular to the extending direction of the data line DL. 
     Moreover, the first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3  and the fourth scan line SL 4  are located in one layer, and the data line DL is located in another layer. The gate insulation layer GI is located between the four scan lines (SL 1 , SL 2 , SL 3 , SL 4 ) and the data line DL, which will be described in detail below. Considering conductivity, the first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3 , the fourth scan line SL 4  and the data line DL are generally made of metal. However, the invention is not limited thereto, and according to other embodiments, the first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3 , the fourth scan line SL 4  and the data line DL may also be made of other conductive materials such as alloy, nitride of a metal material, oxide of a metal material, nitroxide of a metal material, or a stacked layer of the metal materials and the aforementioned other conductive materials. 
     The first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  are electrically connected to one of the first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3  and the fourth scan line SL 4 , respectively, and the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  are electrically connected to the data line DL. In detail, in the present embodiment, the first pixel structure P 1  is electrically connected to the first scan line SL 1 , the second pixel structure P 2  is electrically connected to the second scan line SL 2 , the third pixel structure P 3  is electrically connected to the fourth scan line SL 4 , and the fourth pixel structure P 4  is electrically connected to the third scan line SL 3 . 
     In the present embodiment, the first pixel structure P 1  includes an active component T 1 , a reflective pixel electrode PE 1  and a capacitor electrode CE 1 ; the second pixel structure P 2  includes an active component T 2 , a reflective pixel electrode PE 2  and a capacitor electrode CE 2 ; the third pixel structure P 3  includes an active component T 3 , a reflective pixel electrode PE 3  and a capacitor electrode CE 3 ; and the fourth pixel structure P 4  includes an active component T 4 , a reflective pixel electrode PE 4  and a capacitor electrode CE 4 . 
     In the present embodiment, the active component T 1 , the active component T 2 , the active component T 3  and the active component T 4  can be bottom gate thin-film transistors or top gate thin-film transistors, and the active component T 1  includes a gate G 1 , a channel layer CH 1 , a drain D 1  and a source S 1 ; the active component T 2  includes a gate G 2 , a channel layer CH 2 , a drain D 2  and a source S 2 ; the active component T 3  includes a gate G 3 , a channel layer CH 3 , a drain D 3  and a source S 3 ; and the active component T 4  includes a gate G 4 , a channel layer CH 4 , a drain D 4  and a source S 4 . 
     Taking the bottom gate thin-film transistor as an example, the gate G 1  and the first scan line SL 1  are a continuous conductive pattern; the gate G 2  and the second scan line SL 2  are a continuous conductive pattern; the gate G 3  and the fourth scan line SL 4  are a continuous conductive pattern; and the gate G 4  and the third scan line SL 3  are a continuous conductive pattern. Which presents that the gate G 1  is electrically connected to the first scan line SL 1 ; the gate G 2  is electrically connected to the second scan line SL 2 ; the gate G 3  is electrically connected to the fourth scan line SL 4 ; and the gate G 4  is electrically connected to the third scan line SL 3 . Namely, in the present embodiment, the gates G 1 -G 4  and the first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3 , the fourth scan line SL 4  belong to a same layer. 
     The channel layers CH 1 -CH 4  are respectively located above the gates G 1 -G 4 . In the present embodiment, the material of the channel layers CH 1 -CH 4  is, for example, amorphous silicon or an oxide semiconductor material, where the oxide semiconductor material includes indium-gallium-zinc oxide (IGZO), zinc oxide, tin oxide, indium-zinc oxide, gallium-zinc oxide (GZO), zinc-tin oxide (ZTO) or indium-tin oxide, etc. Namely, in the present embodiment, the active components T 1 -T 4  are, for example, amorphous silicon thin-film transistors or oxide semiconductor thin-film transistors. However, the invention is not limited thereto, and in other embodiments, the active components T 1 -T 4  can also be low temperature polysilicon thin-film transistors. 
     The source S 1  and the drain D 1  are located above the channel layer CH 1 ; the source S 2  and the drain D 2  are located above the channel layer CH 2 ; the source S 3  and the drain D 3  are located above the channel layer CH 3 ; and the source S 4  and the drain D 4  are located above the channel layer CH 4 . The sources S 1 -S 4  and the data line DL are a continuous conductive pattern, which represents that the sources S 1 -S 4  are all electrically connected to the data line DL. The drains D 1 -D 4  and the capacitor electrodes CE 1 -CE 4  respectively form a continuous conductive pattern, which represents that the drains D 1 -D 4  are electrically connected to the capacitor electrodes CE 1 -CE 4 , respectively. Moreover, in the present embodiment, the drains D 1 -D 4 , the sources S 1 -S 4  and the capacitor electrodes CE 1 -CE 4  and the data line DL belong to the same layer. 
     In the present embodiment, the gate insulation layer GI is further configured between the gate G 1  and the channel layer CH 1 , between the gate G 2  and the channel layer CH 2 , between the gate G 3  and the channel layer CH 3 , and between the gate G 4  and the channel layer CH 4 , where the gate insulation layer GI forms on the first substrate  110  and covers the gates G 1 -G 4 ; and the insulation layer PV further covers the active component T 1 , the active component T 2 , the active component T 3  and the active component T 4  to protect the active component T 1 , the active component T 2 , the active component T 3  and the active component T 4 . The material of the gate insulation layer GI and the insulation layer PV can be an inorganic material, an organic material or a combination thereof, where the inorganic material is, for example, silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the aforementioned materials; and the organic material is, for example, a polymer material such as polyimide resin, epoxy resin or acrylic resin. 
     Moreover, in the present embodiment, the cover layer BP is further configured on the insulation layer PV to cover the active component T 1 , the active component T 2 , the active component T 3  and the active component T 4 . In detail, in the present embodiment, the top of the cover layer BP includes a plurality of bumps X, i.e. the cover layer BP has an uneven surface. The material of the cover layer BP can be an inorganic material, an organic material or a combination thereof, where the inorganic material is, for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the aforementioned materials; and the organic material is, for example, a polymer material such as polyimide resin, epoxy resin or acrylic resin. 
     Moreover, in the present embodiment, the capacitor electrode CE 4  of the fourth pixel structure P 4  includes a capacitor electrode portion CE 4   a , a capacitor electrode portion CE 4   b  and a capacitor electrode portion CE 4   c , where the capacitor electrode portion CE 4   a  and the capacitor electrode portion CE 4   b  are respectively disposed at two sides of the second scan line SL 2 , and the capacitor electrode portion CE 4   b  and the capacitor electrode portion CE 4   c  are respectively disposed at two sides of the first scan line SL 1 . In detail, in order to decrease a parasitic capacitance on the first scan line SL 1  and the second scan line SL 2 , the capacitor electrode portion CE 4   a , the capacitor electrode portion CE 4   b  and the capacitor electrode portion CE 4   c  are not directly connected to each other. 
     The reflective pixel electrodes PE 1 -PE 4  are electrically connected to the active components T 1 -T 4 , respectively. The reflective pixel electrode PE 1  is electrically connected to the capacitor electrode CE 1  through a contact hole H 1 , and the contact hole H 1  is disposed in the cover layer BP and the insulation layer PV to expose a part of the capacitor electrode CE 1 . Moreover, the reflective pixel electrode PE 2  is electrically connected to the capacitor electrode CE 2  through a contact hole H 2 , and the contact hole H 2  is disposed in the cover layer BP and the insulation layer PV to expose a part of the capacitor electrode CE 2 . Moreover, the reflective pixel electrode PE 3  is electrically connected to the capacitor electrode CE 3  through a contact hole H 3 , and the contact hole H 3  is disposed in the cover layer BP and the insulation layer PV to expose a part of the capacitor electrode CE 3 . 
     Moreover, the reflective pixel electrode PE 4  is electrically connected to the capacitor electrode portion CE 4   a , the capacitor electrode portion CE 4   b  and the capacitor electrode portion CE 4   c  of the capacitor electrode CE 4  respectively through a contact hole H 4   a , a contact hole H 4   b  and a contact hole H 4   c , and the contact hole H 4   a , the contact hole H 4   b , the contact hole H 4   c  are all disposed in the cover layer BP and the insulation layer PV to respectively expose the capacitor electrode portion CE 4   a , the capacitor electrode portion CE 4   b  and the capacitor electrode portion CE 4   c  of the capacitor electrode CE 4 . In detail, as described above, since the capacitor electrode portion CE 4   a , the capacitor electrode portion CE 4   b  and the capacitor electrode portion CE 4   c  of the capacitor electrode CE 4  are not directly connected to each other, the reflective pixel electrode PE 4  is electrically connected to the capacitor electrode portion CE 4   a , the capacitor electrode portion CE 4   b  and the capacitor electrode portion CE 4   c  respectively through the contact hole H 4   a , the contact hole H 4   b  and the contact hole H 4   c , such that the capacitor electrode CE 4  and the common electrode layer  130  (which is described in detail later) may construct a proper storage capacitor. 
     The material of the reflective pixel electrodes PE 1 -PE 4  is, for example, Ag, Al or other conductive materials with high reflectivity. The thickness of the reflective pixel electrodes PE 1 -PE 4  is, for example, between 50 nm and 200 nm. Moreover, in order to avoid oxidation of the reflective pixel electrodes PE 1 -PE 4  to influence the reflectivity, a transparent protection layer can be respectively configured on the reflective pixel electrodes PE 1 -PE 4 , and the material thereof is, for example, a transparent conductive material such as indium-tin oxide, indium-zinc oxide, aluminium-tin oxide, aluminium-zinc oxide. 
     Moreover, in the present embodiment, the reflective pixel electrodes PE 1 -PE 4  cover the bumps X on the cover layer BP, such that the reflective pixel electrodes PE 1 -PE 4  may have uneven surfaces, and the reflective liquid crystal display panel  10  may improve light reflectivity and reflection viewing angle distribution. 
     Moreover, in the present embodiment, an area ratio of the reflective pixel electrode PE 1 , the reflective pixel electrode PE 2 , the reflective pixel electrode PE 3  and the reflective pixel electrode PE 4  is 1:1:2:4. Moreover, the capacitor electrode CE 1  of the first pixel structure P 1  has the same or similar area with the capacitor electrode CE 2  of the second pixel structure P 2 . 
     It should be noted that in all of the embodiments of the invention, the area proportion relationship (for example, the area ratio of the reflective pixel electrode PE 1 , the reflective pixel electrode PE 2 , the reflective pixel electrode PE 3  and the reflective pixel electrode PE 4  is 1:1:2:4) includes an error range allowed in any technical field of the invention, i.e. the error range is within a range of ±10% of an accurate value. For example, the area ratio of the reflective pixel electrode PE 1  and the reflective pixel electrode PE 2  of 1:1 covers the situation of the area ratio of the reflective pixel electrode PE 1  and the reflective pixel electrode PE 2  of 1:0.9-1.2, and the area error range of the reflective pixel electrode PE 3  and the reflective pixel electrode PE 4  is also the same. 
     In the present embodiment, the pixel unit U further includes a common electrode layer  130 , which is disposed on the first substrate  100  and is electrically isolated from the reflective pixel electrodes PE 1 -PE 4 . In detail, in the present embodiment, the common electrode layer  130  includes a common electrode pattern CM 1 , a common electrode pattern CM 2 , a common electrode pattern CM 3 , a common electrode pattern CM 4   a , a common electrode pattern CM 4   b , a common electrode pattern CM 4   c  respectively corresponding to the capacitor electrode CE 1  of the first pixel structure P 1 , the capacitor electrode CE 2  of the second pixel structure P 2 , the capacitor electrode CE 3  of the third pixel structure P 3 , the capacitor electrode portion CE 4   a  of the fourth pixel structure P 4 , the capacitor electrode portion CE 4   b  of the fourth pixel structure P 4  and the capacitor electrode portion CE 4   c  of the fourth pixel structure P 4 . Moreover, in the present embodiment, the common electrode layer  130  and the gates G 1 -G 4 , the first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3  and the fourth scan line SL 4  belong to the same layer. 
     In this way, the common electrode pattern CM 1  of the common electrode layer  130  and the capacitor electrode CE 1  of the first pixel structure P 1  construct a storage capacitor Cst 1 ; the common electrode pattern CM 2  of the common electrode layer  130  and the capacitor electrode CE 2  of the second pixel structure P 2  construct a storage capacitor Cst 2 ; the common electrode pattern CM 3  of the common electrode layer  130  and the capacitor electrode CE 3  of the third pixel structure P 3  construct a storage capacitor Cst 3 ; the common electrode pattern CM 4   a  of the common electrode layer  130  and the capacitor electrode portion CE 4   a  of the fourth pixel structure P 4  construct a storage capacitor Cst 4   a ; the common electrode pattern CM 4   b  of the common electrode layer  130  and the capacitor electrode portion CE 4   b  of the fourth pixel structure P 4  construct a storage capacitor Cst 4   b ; the common electrode pattern CM 4   c  of the common electrode layer  130  and the capacitor electrode portion CE 4   c  of the fourth pixel structure P 4  construct a storage capacitor Cst 4   c ; and the gate insulation layer GI located between the capacitor electrodes CE 1 -CE 4   c  and the common electrode patterns CM 1 -CM 4   c  serve as a capacitor dielectric layer of the storage capacitors Cst 1 -Cst 4   c.    
     It should be noted that in the present embodiment, since the area ratio of the reflective pixel electrode PE 1  of the first pixel structure P 1 , the reflective pixel electrode PE 2  of the second pixel structure P 2 , the reflective pixel electrode PE 3  of the third pixel structure P 3 , and the reflective pixel electrode PE 4  of the fourth pixel structure P 4  is 1:1:2:4, and the capacitor electrode CE 1 , the common electrode pattern CM 1  respectively have the same areas as those of the capacitor electrode CE 2 , the common electrode pattern CM 2 , so the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  may all own a proper storage capacitor area. In this way, under the low frequency operation, the reflective liquid crystal display panel  10  of the present embodiment with a problem of abnormal image display caused by failure of charge retention due to an excessively small storage capacitor area can be avoided. 
     According to another aspect, in the present embodiment, the common electrode pattern CM 1  and the common electrode pattern CM 4   c  are connected to each other to form a common electrode line CL 1 ; the common electrode pattern CM 2  and the common electrode pattern CM 4   b  are connected to each other to form a common electrode line CL 2 ; the common electrode pattern CM 4   a  is a part of a common electrode line CL 3 ; the common electrode pattern CM 3  is a part of a common electrode line CL 4 ; and the common electrode line CL 1 , the common electrode line CL 2 , the common electrode line CL 3  and the common electrode line CL 4  are all electrically connected to a common voltage Vcom. 
     In the present embodiment, the pixel unit U further includes a spacer PS disposed between the first substrate  100  and the second substrate  110  and covering a part of the reflective pixel electrode PE 1 . In detail, in the present embodiment, the spacer PS is disposed on the counter electrode layer  140 , and extends to the reflective pixel electrode PE 1  of the first pixel structure P 1  (shown in  FIG. 2 ). The material of the spacer PS is, for example, a photoresist material or other opaque materials. 
     It should be noted that in the present embodiment, even if the area ratio of the reflective pixel electrode PE 1 , the reflective pixel electrode PE 2 , the reflective pixel electrode PE 3  and the reflective pixel electrode PE 4  is 1:1:2:4, by configuring the spacer PS, the region where the spacer PS is located in the pixel unit U does not exist the liquid crystal molecules, so as to achieve an effect that the reflection area ratio of the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure is actually 1:2:4:8. In detail, regarding a reflection area of the reflective pixel electrode PE 1  after the area occupied by the spacer PS is deducted, the reflection area of the reflective pixel electrode PE 1  actually used for reflecting environment light is only about ½ of the original area, and the reflection areas of the reflective pixel electrode PE 2 , the reflective pixel electrode PE 3 , the reflective pixel electrode PE 4  are not changed, so that the reflection area ratio of the reflective pixel electrode PE 1 , the reflective pixel electrode PE 2 , the reflective pixel electrode PE 3  and the reflective pixel electrode PE 4  is actually 1:2:4:8. In other words, viewing from a direction perpendicular to the first substrate  100 , the area ratio of the spacer PS, the reflective pixel electrode PE 1 , reflective pixel electrode PE 2 , the reflective pixel electrode PE 3  and the reflective pixel electrode PE 4  can be 0.5:1:1:2:4. Similar to the aforementioned description, the area proportion relationship includes an error range allowed in any technical field of the invention, i.e. the error range is within a range of ±10% of an accurate value. In this way, as the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  have the specific reflection area ratio, the reflective liquid crystal display panel  10  may display 16 gray scale levels, so as to achieve a good visual effect. 
     Moreover, in the present embodiment, the spacer PS is overlapped with a part of the reflective pixel electrode PE 1 , though the invention is not limited thereto. In other embodiments, in order to avoid a light leakage phenomenon caused by the reflective pixel electrode PE 1  under the spacer PS, the reflective pixel electrode PE 1  can also be disposed at a position that is not aligned with the spacer PS, i.e. the spacer PS and the reflective pixel electrode PE 1  are not overlapped, so as to achieve the reflection area ratio of the reflective pixel electrode PE 1 , the reflective pixel electrode PE 2 , the reflective pixel electrode PE 3  and the reflective pixel electrode PE 4  of 1:2:4:8. In this way, the reflective liquid crystal display panel  10  still includes the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  with the reflection area ratio of 1:2:4:8, and can be used for displaying 16 gray scale levels. 
     Moreover, in the present embodiment, one pixel unit U includes four pixel structures (i.e. the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4 ), and the reflection area ratio thereof is 1:2:4:8, so that by using the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  to control the liquid crystal layer  120 , one pixel unit U is capable of display 16 gray scale levels. For example, when the liquid crystal layer  120  corresponding to the first pixel structure P 1  allows the environment light to pass therethrough, and the liquid crystal layer  120  corresponding to the second, the third and the fourth pixel structures P 2 -P 4  does not allow the environment light to pass therethrough, the reflection area capable of reflecting the environment light corresponding to the first pixel structure P 1  in one pixel unit U is 1/15 of all of the reflection area, and is defined as one gray scale state. For another example, when the liquid crystal layer  120  corresponding to the first pixel structure P 1  and the second pixel structure P 2  allows the environment light to pass therethrough, and the liquid crystal layer  120  corresponding to the third pixel structures P 3  and the fourth pixel structures P 4  does not allow the environment light to pass therethrough, the reflection area capable of reflecting the environment light corresponding to the first pixel structure P 1  and the second pixel structure P 2  in one pixel unit U is 3/15 of all of the reflection area, and is defined as another gray scale state, and deduced by analogy, 16 gray scale levels can be used for permutation and combination, though the invention is not limited thereto. In other embodiments, one pixel unit U may also include a fifth pixel structure, i.e. one pixel unit may include five pixel structures, and by making the reflection area ratio thereof to be 1:2:4:8:16, 32 gray scale levels can be achieved. 
     In the present embodiment, the reflective liquid crystal display panel  10  further includes a thin-film transistor integrated gate driver  150  disposed in the periphery area BB. In detail, the thin-film transistor integrated gate driver  150  includes a plurality of thin-film transistors, and the thin-film transistor integrated gate driver  150  is formed on the first substrate  100  together with formation of the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4 . Namely, in the present embodiment, the reflective liquid crystal display panel  10  adopts the gate driver on array (GOA) technique. 
     Moreover, in the present embodiment, the first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3  and the fourth scan line SL 4  of each of the pixel units U are electrically connected to the thin-film transistor integrated gate driver  150 . Therefore, compared to a reflective liquid crystal display panel with the same resolution and each of the pixel units therein includes two data lines and two scan lines, by using only one data line DL to simultaneously drive four active components T 1 -T 4  in each of the pixel units U and by adopting the GOA technique to achieve the scan function, the reflective liquid crystal display panel  10  may have decreased manufacturing cost. 
     According to the first embodiment, it is known that the pixel unit U at least includes the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  with the reflection area ratio of 1:2:4:8, such that the reflective liquid crystal display panel  10  may at least display 16 gray scale levels to achieve a good visual effect. Moreover, as the area ratio of the reflective pixel electrode PE 1  of the first pixel structure P 1 , the reflective pixel electrode PE 2  of the second pixel structure P 2 , the reflective pixel electrode PE 3  of the third pixel structure P 3 , and the reflective pixel electrode PE 4  of the fourth pixel structure P 4  is 1:1:2:4, and the capacitor electrode CE 1  and the common electrode pattern CM 1  respectively have the same areas as those of the capacitor electrode CE 2  and the common electrode pattern CM 2 , the reflective liquid crystal display panel  10  with the problem of abnormal image display caused by an excessively small storage capacitor area can be avoided, such that a good image display effect is achieved. Moreover, since in the reflective liquid crystal display panel  10 , only one data line DL is adopted to simultaneously drive four active components T 1 -T 4 , and the GOA technique is adopted to achieve the scan function, the manufacturing cost thereof can be effectively decreased. 
       FIG. 3  is a top view of a reflective liquid crystal display panel according to a second embodiment of the invention. In detail, the embodiment of  FIG. 3  is similar to the embodiment of  FIG. 1  to  FIG. 2 , where the same or like reference numerals in the drawings denote the same or like elements, and thus their description will be omitted. 
     According to  FIG. 3  and  FIG. 1 , it is known that a main difference between the reflective liquid crystal display panel  10 ′ and the reflective liquid crystal display panel  10  is that the spacer PS in the reflective liquid crystal display panel  10 ′ is configured to cover a part of the reflective pixel electrode PE 2 , while the spacer PS in the reflective liquid crystal display panel  10  is configured to cover a part of the reflective pixel electrode PE 1 . 
     In this way, in the reflective liquid crystal display panel  10 ′ of the present embodiment, by configuring the spacer PS, the region where the spacer PS is located in the pixel unit U does not exist the liquid crystal molecules, such that the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  with the area ratio of 1:1:2:4 may actually achieve the effect of the reflection area ratio of 2:1:4:8. In detail, regarding a reflection area of the reflective pixel electrode PE 2  after the area occupied by the spacer PS is deducted, the reflection area of the reflective pixel electrode PE 2  actually used for reflecting environment light is only about ½ of the original area, and the reflection areas of the reflective pixel electrode PE 1 , the reflective pixel electrode PE 3 , the reflective pixel electrode PE 4  are not changed, so that the reflection area ratio of the reflective pixel electrode PE 1 , the reflective pixel electrode PE 2 , the reflective pixel electrode PE 3  and the reflective pixel electrode PE 4  is actually 2:1:4:8. In other words, viewing from the direction perpendicular to the first substrate  100 , the area ratio of the spacer PS, the reflective pixel electrode PE 1 , the reflective pixel electrode PE 2 , the reflective pixel electrode PE 3  and the reflective pixel electrode PE 4  can be 0.5:1:1:2:4. Similar to the aforementioned description, the area proportion relationship includes the error range allowed in any technical field of the invention, i.e. the error range is within a range of ±10% of an accurate value. It should be noted that as described above, as the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  have the specific reflection area ratio, the reflective liquid crystal display panel  10 ′ may display 16 gray scale levels, so as to achieve a good visual effect. 
       FIG. 4  is a partial cross-sectional view of a reflective liquid crystal display panel according to a third embodiment of the invention. A top view of the reflective liquid crystal display panel  20  of  FIG. 4  may refer to  FIG. 1 , where a cross-section position of  FIG. 4  may refer to the position of the section line A-A′ of  FIG. 1 . Moreover, the embodiment of  FIG. 4  is similar to the embodiment of  FIG. 1  and  FIG. 2 , and the same or like reference numerals in the drawings denote the same or like elements, and thus their description will be omitted. 
     According to  FIG. 2  and  FIG. 4 , it is known that a difference between the reflective liquid crystal display panel  20  and the reflective liquid crystal display panel  10  is that the pixel unit U in the reflective liquid crystal display panel  20  includes a light-shielding pattern BM disposed on the second substrate  110  and shielding a part of the reflective pixel electrode PE 1  along a perpendicular projection direction of the second substrate  110 , and none spacer is configured. The material of the light-shielding pattern BM is, for example, an opaque material such as black resin or a light-shielding metal (for example, chromium). 
     In detail, in the present embodiment, by configuring the light-shielding pattern BM to shield a part of a reflected light coming from the reflective pixel electrode PE 1  of the first pixel structure P 1 , even if the area ratio of the reflective pixel electrode PE 1  of the first pixel structure P 1 , the reflective pixel electrode PE 2  of the second pixel structure P 2 , the reflective pixel electrode PE 3  of the third pixel structure P 3 , and the reflective pixel electrode PE 4  of the fourth pixel structure P 4  is 1:1:2:4, the reflection area ratio of the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  is still 1:2:4:8. In other words, viewing from the direction perpendicular to the first substrate  100 , the area ratio of the light-shielding pattern BM, the reflective pixel electrode PE 1 , the reflective pixel electrode PE 2 , the reflective pixel electrode PE 3 , and the reflective pixel electrode PE 4  can be 0.5:1:1:2:4. Similarly, as described in the first embodiment, the area proportion relationship of the present embodiment includes an error range allowed in any technical field of the invention, i.e. the error range is within a range of ±10% of an accurate value. In this way, as the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  have the specific reflection area ratio, the reflective liquid crystal display panel  20  may display 16 gray scale levels, so as to achieve a good visual effect. 
     Moreover, in the present embodiment, the light-shielding pattern BM is disposed on the second substrate  110 , though those skilled in the art should understand that the light-shielding pattern BM can also be disposed on the first substrate  100 . 
     Moreover, according to the first embodiment, the second embodiment and the third embodiment, it is known that the light-shielding pattern BM in the reflective liquid crystal display panel  20  can also be configured to shield a part of the reflective pixel electrode PE 2  along the perpendicular projection direction of the second substrate  110  (not shown), such that the pixel unit U at least includes the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  with the reflection area ratio of 2:1:4:8. In other words, viewing from the direction perpendicular to the first substrate  100 , the area ratio of the light-shielding pattern BM, the reflective pixel electrode PE 1 , the reflective pixel electrode PE 2 , the reflective pixel electrode PE 3  and the reflective pixel electrode PE 4  can be 0.5:1:1:2:4. Now, the area ratio of the reflective pixel electrode PE 1  of the first pixel structure P 1 , the reflective pixel electrode PE 2  of the second pixel structure P 2 , the reflective pixel electrode PE 3  of the third pixel structure P 3 , and the reflective pixel electrode PE 4  of the fourth pixel structure P 4  is 1:1:2:4. 
       FIG. 5  is a top view of a reflective liquid crystal display panel according to a fourth embodiment of the invention.  FIG. 6  is a cross-sectional view along a section line A-A′ of  FIG. 5 . The reflective liquid crystal display panel  30  of  FIG. 5  is similar to the reflective liquid crystal display panel  10  of  FIG. 1 , and a main difference there between lies in a different configuration structure of the third pixel structure P 3  and the fourth pixel structure P 4 , where the same or like reference numerals in the drawings denote the same or like elements, and thus their description will be omitted. In the following description, only the difference between of the reflective liquid crystal display panels  30  and  10  is described. 
     Referring to  FIG. 5  and  FIG. 6 , in the present embodiment, the third pixel structure P 3  is electrically connected to the third scan line SL 3 , and the fourth pixel structure P 4  is electrically connected to the fourth scan line SL 4 . Namely, in the present embodiment, the gate G 3  of the active component T 3  and the third scan line SL 3  are a continuous conductive pattern, and the gate G 4  of the active component T 4  and the fourth scan line SL 4  are a continuous conductive pattern. 
     Moreover, in the present embodiment, the capacitor electrode CE 3  of the third pixel structure P 3  includes a capacitor electrode portion CE 3   a  and a capacitor electrode portion CE 3   b , where the capacitor electrode portion CE 3   a  and the capacitor electrode portion CE 3   b  are respectively disposed at two sides of the second scan line SL 2 . In detail, in order to decrease a parasitic capacitance on the second scan line SL 2 , the capacitor electrode portion CE 3   a  and the capacitor electrode portion CE 3   b  of the capacitor electrode CE 3  are not directly connected. 
     The capacitor electrode CE 4  of the fourth pixel structure P 4  includes a capacitor electrode portion CE 4   d , a capacitor electrode portion CE 4   e , a capacitor electrode portion CE 4   f  and a capacitor electrode portion CE 4   g , where the capacitor electrode portion CE 4   d  and the capacitor electrode portion CE 4   e  are respectively disposed at two sides of the third scan line SL 3 , the capacitor electrode portion CE 4   e  and the capacitor electrode portion CE 4   f  are respectively disposed at two sides of the second scan line SL 2 , and the capacitor electrode portion CE 4   f  and the capacitor electrode portion CE 4   g  are respectively disposed at two sides of the first scan line SL 1 . In detail, in order to decrease parasitic capacitances on the first scan line SL 1 , the second scan line SL 2  and the third scan line SL 3 , the capacitor electrode portion CE 4   d , the capacitor electrode portion CE 4   e , the capacitor electrode portion CE 4   f  and the capacitor electrode portion CE 4   g  of the capacitor electrode CE 4  are not directly connected. 
     Moreover, in the present embodiment, the common electrode pattern CM 3   a  of the common electrode layer  130  corresponds to the capacitor electrode portion CE 3   a  of the third pixel structure P 3 ; the common electrode pattern CM 3   b  of the common electrode layer  130  corresponds to the capacitor electrode portion CE 3   b  of the third pixel structure P 3 ; the common electrode pattern CM 4   d  of the common electrode layer  130  corresponds to the capacitor electrode portion CE 4   d  of the fourth pixel structure P 4 ; the common electrode pattern CM 4   e  of the common electrode layer  130  corresponds to the capacitor electrode portion CE 4   e  of the fourth pixel structure P 4 ; the common electrode pattern CM 4   f  of the common electrode layer  130  corresponds to the capacitor electrode portion CE 4   f  of the fourth pixel structure P 4 ; and the common electrode pattern CM 4   g  of the common electrode layer  130  corresponds to the capacitor electrode portion CE 4   g  of the fourth pixel structure P 4 . 
     In the present embodiment, the common electrode pattern CM 3   b  and the common electrode pattern CM 4   f  are a continuous conductive pattern, and the common electrode pattern CM 3   a  and the common electrode pattern CM 4   e  are a continuous conductive pattern. Moreover, in the present embodiment, the common electrode pattern CM 1  and the common electrode pattern CM 4   g  are connected to each other to form a common electrode line CL 1 ; the common electrode pattern CM 2 , the common electrode pattern CM 3   b  and the common electrode pattern CM 4   f  are connected to each other to form a common electrode line CL 2 ; the common electrode pattern CM 3   a  and the common electrode pattern CM 4   e  are a part of a common electrode line CL 3 ; the common electrode pattern CM 4   d  is a part of a common electrode line CL 4 ; and the common electrode line CL 1 , the common electrode line CL 2 , the common electrode line CL 3  and the common electrode line CL 4  are all electrically connected to the common voltage Vcom. 
     Therefore, in the present embodiment, in order to make the third pixel structure P 3  to have a proper storage capacitor area, the reflective pixel electrode PE 3  of the third pixel structure P 3  is electrically connected to the capacitor electrode portion CE 3   a  and the capacitor electrode portion CE 3   b  respectively through a contact hole H 3   a  and a contact hole H 3   b , such that the capacitor electrode portion CE 3   a  and the common electrode pattern CM 3   a  of the common electrode layer  130  construct a storage capacitor Cst 3   a , and the capacitor electrode portion CE 3   b  and the common electrode pattern CM 3   b  of the common electrode layer  130  construct a storage capacitor Cst 3   b . The contact hole H 3   a  is disposed in the cover layer BP and the insulation layer PV to expose a part of the capacitor electrode portion CE 3   a , and the contact hole H 3   b  is disposed in the cover layer BP and the insulation layer PV to expose a part of the capacitor electrode portion CE 3   b.    
     In order to make the fourth pixel structure P 4  to have a proper storage capacitor area, the reflective pixel electrode PE 4  of the fourth pixel structure P 4  is electrically connected to the capacitor electrode portion CE 4   d , the capacitor electrode portion CE 4   e , the capacitor electrode portion CE 4   f  and the capacitor electrode portion CE 4   g  respectively through a contact hole H 4   d , a contact hole H 4   e , a contact hole H 4   f  and a contact hole H 4   g , such that the capacitor electrode portion CE 4   d  and the common electrode pattern CM 4   d  of the common electrode layer  130  construct a storage capacitor Cst 4   d ; the capacitor electrode portion CE 4   e  and the common electrode pattern CM 4   e  of the common electrode layer  130  construct a storage capacitor Cst 4   e ; the capacitor electrode portion CE 4   f  and the common electrode pattern CM 4   f  of the common electrode layer  130  construct a storage capacitor Cst 4   f ; and the capacitor electrode portion CE 4   g  and the common electrode pattern CM 4   g  of the common electrode layer  130  construct a storage capacitor Cst 4   g . The contact hole H 4   d  is disposed in the cover layer BP and the insulation layer PV to expose the capacitor electrode portion CE 4   d , the contact hole H 4   e  is disposed in the cover layer BP and the insulation layer PV to expose the capacitor electrode portion CE 4   e , the contact hole H 4   f  is disposed in the cover layer BP and the insulation layer PV to expose the capacitor electrode portion CE 4   f , and the contact hole H 4   g  is disposed in the cover layer BP and the insulation layer PV to expose the capacitor electrode portion CE 4   g.    
     According to the first embodiment and the fourth embodiment, it is known that although a configuration structure of the third pixel structure P 3  and the fourth pixel structure P 4  of the reflective liquid crystal display panel  30  is different from that of the third pixel structure P 3  and the fourth pixel structure P 4  of the reflective liquid crystal display panel  10 , since the pixel unit U also at least includes the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  with the reflective area ratio of 1:2:4:8, the reflective liquid crystal display panel  30  may at least display 16 gray scale levels to achieve a good visual effect. Moreover, similarly, as the area ratio of the reflective pixel electrode PE 1  of the first pixel structure P 1 , the reflective pixel electrode PE 2  of the second pixel structure P 2 , the reflective pixel electrode PE 3  of the third pixel structure P 3 , and the reflective pixel electrode PE 4  of the fourth pixel structure P 4  is 1:1:2:4, and the capacitor electrode CE 1  and the common electrode pattern CM 1  respectively have the same areas as those of the capacitor electrode CE 2  and the common electrode pattern CM 2 , the reflective liquid crystal display panel  30  with the problem of abnormal image display caused by an excessively small storage capacitor area can be avoided, such that a good image display effect is achieved. Moreover, similarly, in the reflective liquid crystal display panel  30 , only one data line DL is adopted in each of the pixel units U to simultaneously drive four active components T 1 -T 4 , and the GOA technique is adopted to achieve the scan function, the manufacturing cost can be effectively decreased. 
     Moreover, based on the first embodiment, the second embodiment and the fourth embodiment, it is known that the reflective liquid crystal display panel  30  may be adopted the same design concept to configure the spacer PS for covering a part of the reflective pixel electrode PE 2  (not shown) to replace the original design of the fourth embodiment where the spacer PS is configured to cover a part of the reflective pixel electrode PE 1 , so as to achieve the effect that the pixel unit U at least includes the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  with the actual reflection area ratio of 2:1:4:8. Alternatively, a light-shielding pattern (not shown) can be adopted to replace the aforementioned spacer PS to achieve the same invention effect. Other design conditions are the same with that of the fourth embodiment, and detail thereof is not repeated. 
     Moreover, in the embodiments of  FIG. 1  to  FIG. 6 , the first signal line is the data line DL, and the four second signal lines are the first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3  and the fourth scan line SL 4 , though the invention is not limited thereto. In other embodiments, the first signal line can also be a scan line, and the four second signal lines can be four data lines.  FIG. 7  and  FIG. 8  are described in detail below. 
       FIG. 7  is a top view of a reflective liquid crystal display panel according to a fifth embodiment of the invention.  FIG. 8  is a cross-sectional view along a section line A-A′ of  FIG. 7 . It should be noted that the reflective liquid crystal display panel  40  of  FIG. 7  is similar to the reflective liquid crystal display panel  10  of  FIG. 1 , and a main difference there between is that the pixel unit U of the reflective liquid crystal display panel  40  includes one scan line SL and four data lines (i.e. the a first data line DL 1 , a second data line DL 2 , a third data line DL 3  and a fourth data line DL 4 ), and the pixel unit U of the reflective liquid crystal display panel  10  includes one data line DL and four scan lines (i.e. the first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3  and the fourth scan line SL 4 ), and the reflective liquid crystal display panel  40  further includes a multiplexer  460 , where the same or like reference numerals in the drawings denote the same or like elements, and thus their description will be omitted. The differences of the two embodiments are described below. 
     Referring to  FIG. 7  and  FIG. 8 , in the present embodiment, the first data line DL 1 , the second data line DL 2 , the third data line DL 3 , the fourth data line DL 4  and the scan line SL are disposed on the first substrate  100 . The extending direction of the first data line DL 1 , the second data line DL 2 , the third data line DL 3  and the fourth data line DL 4  is different from the extending direction of the scan line SL, and preferably the extending direction of the first data line DL 1 , the second data line DL 2 , the third data line DL 3  and the fourth data line DL 4  is perpendicular to the extending direction of the scan line SL. 
     Moreover, the first data line DL 1 , the second data line DL 2 , the third data line DL 3  and the fourth data line DL 4  are located in one layer, and the scan line SL is located in another layer. The gate insulation layer GI is located between the four data lines (DL 1 , DL 2 , DL 3  and DL 4 ) and the scan line SL. Considering conductivity, the first data line DL 1 , the second data line DL 2 , the third data line DL 3 , the fourth data line DL 4  and the scan line SL are generally made of metal. However, the invention is not limited thereto, and in other embodiments, the first data line DL 1 , the second data line DL 2 , the third data line DL 3 , the fourth data line DL 4  and the scan line SL may also be made of other conductive materials such as alloy, nitride of a metal material, oxide of a metal material, nitroxide of a metal material, or a stacked layer of the metal materials and the aforementioned other conductive materials. 
     In the present embodiment, the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  are respectively and electrically connected to one of the first data line DL 1 , the second data line DL 2 , the third data line DL 3  and the fourth data line DL 4 , and the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  are electrically connected to the scan line SL. In detail, in the present embodiment, the first pixel structure P 1  is electrically connected to the first data line DL 1 , the second pixel structure P 2  is electrically connected to the second data line DL 2 , the third pixel structure P 3  is electrically connected to the fourth data line DL 4 , and the fourth pixel structure P 4  is electrically connected to the third data line DL 3 . 
     Moreover, in the present embodiment, the gates G 1 -G 4  and the scan line SL are a continuous conductive pattern, which represents that the gates G 1 -G 4  are electrically connected to the scan line SL. Namely, in the present embodiment, the gates G 1 -G 4  and the scan line SL belong to the same layer. 
     In the present embodiment, the source S 1  and the first data line DL 1  are a continuous conductive pattern; the source S 2  and the second data line DL 2  are a continuous conductive pattern; the source S 3  and the fourth data line DL 4  are a continuous conductive pattern; and the source S 4  and the third data line DL 3  are a continuous conductive pattern, which represents that the source Si is electrically connected to the first data line DL 1 ; the source S 2  is electrically connected to the second data line DL 2 ; the source S 3  is electrically connected to the fourth data line DL 4 ; and the source S 4  is electrically connected to the third data line DL 3 . Namely, in the present embodiment, the drains D 1 -D 4 , the sources S 1 -S 4 , the capacitor electrodes CE 1 -CE 4 , the first data line DL 1 , the second data line DL 2 , the third data line DL 3  and the fourth data line DL 4  all belong to the same layer. 
     In the present embodiment, the capacitor electrode portion CE 4   a  and the capacitor electrode portion CE 4   b  of the fourth pixel structure P 4  are respectively disposed at two sides of the third data line DL 3 , and the capacitor electrode portion CE 4   b  and the capacitor electrode portion CE 4   c  are respectively disposed at two sides of the second data line DL 2 . In detail, since the capacitor electrode CE 4  and the second data line DL 2 , the third data line DL 3  belong to the same layer, the capacitor electrode portions CE 4   a -CE 4   c  of the capacitor electrode CE 4  cannot be directly connected to each other. 
     In the present embodiment, the common electrode layer  130  includes a plurality of common electrode patterns CM 5 -CM 8 , where the common electrode pattern CM 5  corresponds to the capacitor electrode CE 1  of the first pixel structure P 1  and the capacitor electrode portion CE 4   c  of the fourth pixel structure P 4 ; the common electrode pattern CM 6  corresponds to the capacitor electrode CE 2  of the second pixel structure P 2  and the capacitor electrode portion CE 4   b  of the fourth pixel structure P 4 ; the common electrode pattern CM 7  corresponds to the capacitor electrode CE 4   a  of the fourth pixel structure P 4 ; and the common electrode pattern CM 8  corresponds to the capacitor electrode CE 3  of the third pixel structure P 3 . 
     In this way, the common electrode pattern CM 5  of the common electrode layer  130  and the capacitor electrode CE 1  of the first pixel structure P 1  construct a storage capacitor Cst 1 ; the common electrode pattern CM 6  of the common electrode layer  130  and the capacitor electrode CE 2  of the second pixel structure P 2  construct a storage capacitor Cst 2 ; the common electrode pattern CM 8  of the common electrode layer  130  and the capacitor electrode CE 3  of the third pixel structure P 3  construct a storage capacitor Cst 3 ; the common electrode pattern CM 7  of the common electrode layer  130  and the capacitor electrode portion CE 4   a  of the fourth pixel structure P 4  construct a storage capacitor Cst 4   a ; the common electrode pattern CM 6  of the common electrode layer  130  and the capacitor electrode portion CE 4   b  of the fourth pixel structure P 4  construct a storage capacitor Cst 4   b ; the common electrode pattern CM 5  of the common electrode layer  130  and the capacitor electrode portion CE 4   c  of the fourth pixel structure P 4  construct a storage capacitor Cst 4   c ; and the gate insulation layer GI located between the capacitor electrodes CE 1 -CE 4  and the common electrode patterns CM 5 -CM 8  serves as a capacitor dielectric layer of the storage capacitors Cst 1 -Cst 4   c.    
     Moreover, in the present embodiment, the common electrode patterns CM 5 -CM 8  are connected to each other to form a common electrode line CL, where the common electrode line CL is electrically connected to the common voltage Vcom. 
     In the present embodiment, the reflective liquid crystal display panel  40  further includes a plurality of multiplexers  460  disposed in the periphery area BB. In detail, in the present embodiment, the first data line DL 1 , the second data line DL 2 , the third data line DL 3 , the fourth data line DL 4  in each of the pixel units are electrically connected to one of the plurality of multiplexers  460 , i.e. the multiplexer  460  is a 1-to-4 multiplexer. In this way, compared to the reflective liquid crystal display panel with the same resolution where each of the pixel units includes two data lines and two scan lines, by using only one scan line SL in each of the pixel units U to simultaneously drive four active components T 1 -T 4  and by configuring the multiplexer  460  to reduce the number of lines used for transmitting the driving signal, the manufacturing cost of the reflective liquid crystal display panel  40  is decreased. As described above, for simplicity&#39;s sake, only one pixel unit U and the corresponding multiplexer  460  are illustrated in  FIG. 7 , though the reflective liquid crystal display panel  40  is actually composed of a plurality of pixel units U arranged in an array, and includes a plurality of the multiplexers  460 . 
     According to the first embodiment and the fifth embodiment, it is known that the pixel unit U of the reflective liquid crystal display panel  40  also at least includes the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  with the reflection area ratio of 1:2:4:8, such that the reflective liquid crystal display panel  40  may at least display 16 gray scale levels to achieve good visual effect. Moreover, similarly, since the area ratio of the reflective pixel electrode PE 1  of the first pixel structure P 1 , the reflective pixel electrode PE 2  of the second pixel structure P 2 , the reflective pixel electrode PE 3  of the third pixel structure P 3 , and the reflective pixel electrode PE 4  of the fourth pixel structure P 4  is 1:1:2:4, and the capacitor electrode CE 1 , the common electrode pattern CM 1  respectively have the same areas as those of the capacitor electrode CE 2  and the common electrode pattern CM 2 , the reflective liquid crystal display panel  40  with the problem of abnormal image display caused by excessively small storage capacitor area can be avoided, so as to achieve a good image display effect. 
     Moreover, based on the first embodiment, the second embodiment and the fifth embodiment, it is known that the reflective liquid crystal display panel  40  may be adopted the same design concept to configure the spacer PS for covering a part of the reflective pixel electrode PE 2  (not shown) to replace the original design of the fifth embodiment where the spacer PS is configured to cover a part of the reflective pixel electrode PE 1 , so as to achieve the effect that the pixel unit U at least includes the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  with the actual reflection area ratio of 2:1:4:8. Other design conditions are the same with that of the fifth embodiment, and detail thereof is not repeated. 
     Moreover, according to the fifth embodiment, it is known that in the reflective liquid crystal display panel  40 , by using only one scan line SL in each of the pixel units U to simultaneously drive the four active components T 1 -T 4  and by configuring the multiplexer  460  to reduce the number of lines used for transmitting the driving signal, the manufacturing cost of the reflective liquid crystal display panel  40  is decreased. 
       FIG. 9  is a partial cross-sectional view of a reflective liquid crystal display panel according to a sixth embodiment of the invention. Referring to  FIG. 7  for a top view of the reflective liquid crystal display panel  50  of  FIG. 9 , where the position of the section line A-A′ of  FIG. 7  can be referred for a cross-section position of  FIG. 9 . Moreover, the embodiment of  FIG. 9  is similar to the embodiment of  FIG. 7  and  FIG. 8 , so that the same or like reference numerals in the drawings denote the same or like elements, and thus their description will be omitted. 
     Referring to  FIG. 8  and  FIG. 9 , it is known that a main difference between the reflective liquid crystal display panel  40  and the reflective liquid crystal display panel  50  is that in the reflective liquid crystal display panel  50 , the pixel unit U includes a light-shielding pattern  5 BM configured on the second substrate  110  and shielding a part of the reflective pixel electrode PE 1  along a vertical projection direction of the second substrate  110 , and includes none spacer. The material of the light-shielding pattern  5 BM is, for example, black resin or a light-shielding metal (for example, chromium), that has lower reflectivity. 
     In detail, in the present embodiment, by configuring the light-shielding pattern  5 BM to shield a part of the reflected light coming from the reflective pixel electrode PE 1  of the first pixel structure P 1 , even if the area ratio of the reflective pixel electrode PE 1  of the first pixel structure P 1 , the reflective pixel electrode PE 2  of the second pixel structure P 2 , the reflective pixel electrode PE 3  of the third pixel structure P 3 , and the reflective pixel electrode PE 4  of the fourth pixel structure P 4  is 1:1:2:4, the reflection area ratio of the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  is still 1:2:4:8. In other words, viewing from the direction perpendicular to the first substrate  100 , the area ratio of the light-shielding pattern  5 BM, the reflective pixel electrode PE 1 , the reflective pixel electrode PE 2 , the reflective pixel electrode PE 3 , and the reflective pixel electrode PE 4  can be 0.5:1:1:2:4. Similar to the first embodiment, the area proportion relationship of the present embodiment includes an error range allowed in any technical field of the invention, i.e. the error range is within a range of ±10% of an accurate value. In this way, as the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  have the specific reflection area ratio, the reflective liquid crystal display panel  50  may display 16 gray scale levels, so as to achieve a good visual effect. 
     Moreover, in the present embodiment, the light-shielding pattern  5 BM is disposed on the second substrate  110 , though those skilled in the art should understand that the light-shielding pattern  5 BM can also be disposed on the first substrate  100 . 
     According to the fifth embodiment and the sixth embodiment, it is known that as the pixel unit U at least includes the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  with the reflection area ratio of 1:2:4:8, the reflective liquid crystal display panel  50  may at least display 16 gray scale levels, so as to achieve the good visual effect. 
     Moreover, according to the first embodiment, the second embodiment and the sixth embodiment, it is known that the reflective liquid crystal display panel  50  may be adopted the same design concept to configure the light-shielding pattern  5 BM to shield a part of the reflective pixel electrode PE 2  (not shown) along the vertical projection direction of the second substrate  110  to replace the original design of the sixth embodiment where the light-shielding pattern  5 BM is configured to cover a part of the reflective pixel electrode PE 1 , so as to achieve the effect that the pixel unit U at least includes the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  with the actual reflection area ratio of 2:1:4:8. Other design conditions are the same with that of the sixth embodiment, and detail thereof is not repeated. 
       FIG. 10  is a top view of a reflective liquid crystal display panel according to a seventh embodiment of the invention.  FIG. 11  is a cross-sectional view along a section line A-A′ of  FIG. 10 . The reflective liquid crystal display panel  60  of  FIG. 10  is similar to the reflective liquid crystal display panel  40  of  FIG. 7 , and a difference there between is that a configuration structure of the third pixel structure P 3  and the fourth pixel structure P 4  of the reflective liquid crystal display panel  60  is different from that of the third pixel structure P 3  and the fourth pixel structure P 4  of the reflective liquid crystal display panel  40 , where the same or like reference numerals in the drawings denote the same or like elements, and thus their description will be omitted. In the following description, only the difference between the reflective liquid crystal display panels  60  and  40  is described. 
     Referring to  FIG. 10  and  FIG. 11 , in the present embodiment, the third pixel structure P 3  is electrically connected to the third data line DL 3 , and the fourth pixel structure P 4  is electrically connected to the fourth data line DL 4 . Namely, in the present embodiment, the source S 3  of the active component T 3  and the third data line DL 3  are a continuous conductive pattern, and the source S 4  of the active component T 4  and the fourth data line DL 4  are a continuous conductive pattern. 
     Moreover, in the present embodiment, the capacitor electrode CE 3  of the third pixel structure P 3  includes a capacitor electrode portion CE 3   c  and a capacitor electrode portion CE 3   d , where the capacitor electrode portion CE 3   c  and the capacitor electrode portion CE 3   d  are respectively configured at two sides of the third data line DL 3 . In detail, since the capacitor electrode CE 3  and the third data line DL 3  belong to the same layer, the capacitor electrode portions CE 3   c -CE 3   d  of the capacitor electrode CE 3  cannot be directly connected to each other. 
     The capacitor electrode CE 4  of the fourth pixel structure P 4  includes a capacitor electrode portion CE 4   h , a capacitor electrode portion CE 4   i , a capacitor electrode portion CE 4   j  and a capacitor electrode portion CE 4   k , where the capacitor electrode portion CE 4   h  and the capacitor electrode portion CE 4   i  are respectively disposed at two sides of the fourth data line DL 4 , the capacitor electrode portion CE 4   i  and the capacitor electrode portion CE 4   j  are respectively disposed at two sides of the third data line DL 3 , the capacitor electrode portion CE 4   j  and the capacitor electrode portion CE 4   k  are respectively disposed at two sides of the second data line DL 2 . In detail, since the capacitor electrode CE 4  and the second data line DL 2 , the third data line DL 3  and the fourth data line DL 4  belong to the same layer, the capacitor electrode portions CE 4   h -CE 4   k  of the capacitor electrode CE 4  cannot be directly connected to each other. 
     Moreover, in the present embodiment, the common electrode pattern CM 5  of the common electrode layer  130  corresponds to the capacitor electrode CE 1  of the first pixel structure P 1  and the capacitor electrode portion CE 4   k  of the fourth pixel structure P 4 ; the common electrode pattern CM 6  of the common electrode layer  130  corresponds to the capacitor electrode CE 2  of the second pixel structure P 2 , the capacitor electrode CE 3   d  of the third pixel structure P 3 , and the capacitor electrode portion CE 4   j  of the fourth pixel structure P 4 ; the common electrode pattern CM 7  of the common electrode layer  130  corresponds to the capacitor electrode CE 3   c  of the third pixel structure P 3  and the capacitor electrode portion CE 4   i  of the fourth pixel structure P 4 ; and the common electrode pattern CM 8  of the common electrode layer  130  corresponds to the capacitor electrode CE 4   h  of the fourth pixel structure P 4 . 
     Therefore, in the present embodiment, in order to make the third pixel structure P 3  to have a proper storage capacitor area, the reflective pixel electrode PE 3  of the third pixel structure P 3  is electrically connected to the capacitor electrode portion CE 3   c  and the capacitor electrode portion CE 3   d  respectively through a contact hole H 3   c  and a contact hole H 3   d , such that the capacitor electrode portion CE 3   c  and the common electrode pattern CM 7  of the common electrode layer  130  construct a storage capacitor Cst 3   c , and the capacitor electrode portion CE 3   d  and the common electrode pattern CM 6  of the common electrode layer  130  construct a storage capacitor Cst 3   d . The contact hole H 3   c  is disposed in the cover layer BP and the insulation layer PV to expose the capacitor electrode portion CE 3   c , and the contact hole H 3   d  is disposed in the cover layer BP and the insulation layer PV to expose the capacitor electrode portion CE 3   d.    
     In order to make the fourth pixel structure P 4  to have a proper storage capacitor area, the reflective pixel electrode PE 4  of the fourth pixel structure P 4  is electrically connected to the capacitor electrode portion CE 4   h , the capacitor electrode portion CE 4   i , the capacitor electrode portion CE 4   j  and the capacitor electrode portion CE 4   k  respectively through a contact hole H 4   h , a contact hole H 4   i , a contact hole H 4   j  and a contact hole H 4   k , such that the capacitor electrode portion CE 4   h  and the common electrode pattern CM 8  of the common electrode layer  130  construct a storage capacitor Cst 4   h ; the capacitor electrode portion CE 4   i  and the common electrode pattern CM 7  of the common electrode layer  130  construct a storage capacitor Cst 4   i ; the capacitor electrode portion CE 4   j  and the common electrode pattern CM 6  of the common electrode layer  130  construct a storage capacitor Cst 4   j ; and the capacitor electrode portion CE 4   k  and the common electrode pattern CM 5  of the common electrode layer  130  construct a storage capacitor Cst 4   k . The contact hole H 4   h  is disposed in the cover layer BP and the insulation layer PV to expose the capacitor electrode portion CE 4   h , the contact hole H 4   i  is disposed in the cover layer BP and the insulation layer PV to expose the capacitor electrode portion CE 4   i , the contact hole H 4   j  is disposed in the cover layer BP and the insulation layer PV to expose a part of the capacitor electrode portion CE 4   j , and the contact hole H 4   k  is disposed in the cover layer BP and the insulation layer PV to expose a part of the capacitor electrode portion CE 4   k.    
     According to the fifth embodiment and the seventh embodiment, it is known that although a configuration structure of the third pixel structure P 3  and the fourth pixel structure P 4  of the reflective liquid crystal display panel  60  is different from that of the third pixel structure P 3  and the fourth pixel structure P 4  of the reflective liquid crystal display panel  40 , since the pixel unit U also at least includes the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  with the reflective area ratio of 1:2:4:8, the reflective liquid crystal display panel  60  may at least display 16 gray scale levels to achieve a good visual effect. Moreover, similarly, as the area ratio of the reflective pixel electrode PE 1  of the first pixel structure P 1 , the reflective pixel electrode PE 2  of the second pixel structure P 2 , the reflective pixel electrode PE 3  of the third pixel structure P 3 , and the reflective pixel electrode PE 4  of the fourth pixel structure P 4  is 1:1:2:4, and the capacitor electrode CE 1  and the common electrode pattern CM 1  respectively have the same areas as those of the capacitor electrode CE 2  and the common electrode pattern CM 2 , the reflective liquid crystal display panel  60  with the problem of abnormal image display caused by an excessively small storage capacitor area can be avoided, such that a good image display effect is achieved. Moreover, similarly, since in the reflective liquid crystal display panel  60 , only one data line DL is adopted in each of the pixel units U to simultaneously drive four active components T 1 -T 4 , and the multiplexer  460  is configured to decrease the number of lines used for transmitting the driving signal, the manufacturing cost thereof can be effectively decreased. 
     Moreover, based on the first embodiment, the second embodiment and the seventh embodiment, it is known that the reflective liquid crystal display panel  60  may be adopted the same design concept to configure the spacer PS for covering a part of the reflective pixel electrode PE 2  (not shown) to replace the original design of the seventh embodiment where the spacer PS is configured to cover a part of the reflective pixel electrode PE 1 , so as to achieve the effect that the pixel unit U at least includes the first pixel structure P 1 , the second pixel structure P 2 , the third pixel structure P 3  and the fourth pixel structure P 4  with the actual reflection area ratio of 2:1:4:8. Alternatively, a light-shielding pattern (not shown) can be adopted to replace the aforementioned spacer PS to achieve the same invention effect. Other design conditions are the same with that of the seventh embodiment, and detail thereof is not repeated. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.