Patent Publication Number: US-10762019-B2

Title: Bus sharing scheme

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This Application is a Continuation of U.S. patent application Ser. No. 14/540,238, filed on Nov. 13, 2014, now U.S. Pat. No. 9,720,865, which is a Continuation of U.S. patent application Ser. No. 13/893,201, filed May 13, 2013, now U.S. Pat. No. 8,890,600, issued on Nov. 18, 2014, which is a continuation of U.S. patent application Ser. No. 12/496,579, filed Jul. 1, 2009, now U.S. Pat. No. 8,441,298, issued May 14, 2013, which claims priority to U.S. Provisional Patent Application No. 61/077,466, filed Jul. 1, 2008, all of which are incorporated by reference herein in their entirety. 
    
    
     TECHNICAL FIELD 
     This disclosure relates generally to analog circuits, and more particularly to sharing buses in the analog domain. 
     BACKGROUND 
     Buses having a plurality of lines connect circuit components to each other, as well as to input and output ports. Utilizing one line for each possible interconnection can result in a great number of lines. Each line consumes device space, i.e., real estate, both for the line itself and for spacing around the line. 
     SUMMARY 
     The following is a summary of embodiments of the invention in order to provide a basic understanding of some aspects. This summary is not intended to identify key/critical elements of the embodiments or to delineate the scope of the embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later. 
     In one example, transmission gates selectively connect a plurality of General Purpose Input Output (GPIO) pads to a bus line of an analog bus. Alternating selective connections between the transmission gates allows the GPIO pads to share the bus line, saving real estate in an embodiment. The transmission gates may also be controlled in other ways to provide dynamic configuration of the circuit, such as connecting the GPIO pads to each other over the bus line. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  shows a system utilizing a plurality of switches to share analog lines between I/O ports in an embodiment. 
         FIG. 1B  shows a variation of the system of  FIG. 1A  utilizing a plurality of switches to share analog and digital lines between I/O ports in an embodiment. 
         FIG. 1C  illustrates examples of the switching components located on the analog lines of the system shown in  FIGS. 1A and 1B  in an embodiment. 
         FIG. 1D  illustrates an alternative example of the switching component located on the digital lines of the system shown in  FIG. 1B  in an embodiment. 
         FIG. 2  shows a system similar to the system shown in  FIG. 1A  but having additional switching components in an embodiment. 
         FIG. 3  shows a system utilizing a plurality of bus networks in an electronic device in an embodiment. 
         FIG. 4A  shows a system similar to the system shown in  FIG. 3  but having additional switching components in an embodiment. 
         FIG. 4B  shows a variation of the system of  FIG. 4A  in an embodiment. 
         FIGS. 5A and 5B  (collectively referred to as “ FIG. 5 ” hereinafter) show partial views that together form a single complete view that shows an example circuit utilizing a bus sharing scheme in an embodiment. 
     
    
    
     DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS 
     Several examples of the present application will now be described with reference to the accompanying drawings. Various other examples of the invention are also possible and practical. This application may be exemplified in many different forms and should not be construed as being limited to the examples set forth herein. 
       FIG. 1A  shows a system  100  utilizing a plurality of switches to share analog lines between I/O ports in an embodiment. 
     Unlike some circuits where there is a one-to-one correspondence between bus lines and General Purpose Input/Output (GPIO) ports, the example system  100  has a plurality of GPIO pads selectively connected to each bus line. For example, the pads  2 A and  3 A are both selectively connected to bus line  11  via transmission gates  4 A and  5 A respectively. It is noted that the bus lines can be connected to analog components such as, but not limited to, ADCs, DACs, comparators, etc. 
     It should be appreciated that the above-described concept may save real estate. For example, in another system with eight GPIO pads, eight bus lines are specified. In the present example, four bus lines are used for the eight GPIO pads  2 A- 2 D and  3 A-D due to the switching scheme. For example, bus line  11  can be used by either of the pads  2 A or  3 A, at any given time. 
     In an embodiment, one bus line is connected to multiple ports simultaneously. For example, both switches  4 A and  5 A can be closed at the same time to connect bus line  11  to both pads  2 A and  3 A. 
     Alternatively, both pads  2 A and  3 A can be simultaneously opened to disconnect both of these pads  2 A and  3 A. This could be used to free up the bus line  11  to send signals between internal components  15  (either analog or digital or both) that are also selectively connected to the bus line  11 . In other words, the bus line  11  is not only shared between I/O ports, but also can be shared with internal components  15  using the switching scheme. 
     The switching scheme described above can be further extended by adding additional switching components along the bus lines  11 - 14  themselves. For example, switches can be added at the dashed box  66 . These switches, if added, break each of the bus lines  11 - 14  into sub bus lines that can be combined by closing a respective one of the switching components of dashed box  66 . Such switches could allow, for example, pads  2 A and  3 A to connect to different sub bus lines at one time, but connect to each other through joined sub bus lines at another time. 
     It should be understood that the transmission gates  4 A-D and  5 A- 5 D can be controlled in any known fashion. For example, registers could be arranged for each gate and set or unset according to a request (whether generated by a user or an internal component). Or in other examples, an internal logic function controls the transmission gates. Or in another example, some portion of the transmission gates may be controlled by the internal logic while another portion is controlled according to register settings. In any case, the transmission gates may be controlled by a controller, and here controller  99  may be operating all the switching components (namely in this example switching components  4 A- 4 D and  5 A- 5 D) to share access to the bus lines (and provide pad interconnections and internal component interconnections as needed). 
     In the present example, the I/O ports  2 A- 2 D and  3 A- 3 D are general purpose I/O ports. In other examples, any I/O ports can be used. Furthermore, the principles described above can be applied independently of I/O ports. For example, on-chip circuit components can be connected to the bus lines and the bus lines may or may not also connect to I/O ports. 
     Although the bus lines  11 - 14  are referred to as “analog” bus lines, meaning that these bus lines have transmission characteristics selected for analog transmissions, in some examples digital signals may be sent in through the pads. For example, a digital signal may be sent over one of the pads to an internal DAC, and then sent back as an analog signal over the same or another one of the bus lines  11 - 14  to a different pad, for example. 
     As discussed in greater detail in co-pending U.S. patent application Ser. No. 12/496,590, entitled “Multifunction Input/Output Circuit”, which is herein incorporated by reference in its entirety, a multifunction I/O interface cell and controller can allow an I/O pad to be used for multiple purposes depending on the settings of the controller. It should be appreciated that each of the I/O pads described herein can be selectively connected to their respective bus lines through the multifunction I/O interface cell to expand configurability. 
       FIG. 1B  shows a variation of the system of  FIG. 1A  utilizing a plurality of switches to share analog and digital bus lines between I/O ports in an embodiment. 
     The variant system of  FIG. 1B  utilizes logic gates  8 A-D and  9 A-D to selectively connect the pads  2 A-D and  3 A-D to each other and internal digital components via digital bus lines  21 A-C,  22 A-C,  23 A-C, and  24 A-C. In the present example, the logic gates  8 A-D and  9 A-D are multiplexers, although in other examples different types of logic gates may be used. 
     The two-to-one multiplexer  8 A receives inputs including the connection extending to pad  2 A and the digital bus line  21 A. The multiplexer  8 A output is connected to digital bus line  21 B, which could then be directly connected to an internal digital component (or even selectively connected to one of a plurality of digital components). The same digital bus line  21 B is then fed into an input of the multiplexer  9 A, as shown. 
     Similar to the previously discussed dashed box  66 , the digital side may be modified to include logic gates along the bus lines  21 B,  22 B,  23 B, and  24 B. Such logic gates could be tri-state drivers, instead of the two-to-one multiplexers. 
       FIG. 1C  illustrates examples of the switching components located on the bus lines of the system shown in  FIGS. 1A and 1B  in an embodiment. 
     The transmission gates  4 A-D and  5 A-D shown in  FIG. 1A  may be of any type. One possible type of transmission gate is the NMOS transistor of  FIG. 1C . The type of transmission gate may be selected based on the expected characteristics of the signals to be connected to the pad  2 A. 
     If the different signals that may be connected to the pad  2 A have a wide range of operating characteristics, then transmission gates connected in parallel for the switching components may be utilized. For example, if the pad  2 A may provide high or low voltage signals depending on register settings, the switching component selectively connecting the pad  2 A to the bus line  11  may be an NMOS and PMOS transistor connected in parallel. This concept may be extended to add additional transistor types in parallel according to the characteristics of the signals received over I/O pads. 
       FIG. 1D  illustrates an alternative example of the switching component located on the digital bus lines of the system shown in  FIG. 1B  in an embodiment. 
     As discussed previously, the logic gates used for the switching components of  FIG. 1B  are not limited to a multiplexer. The digital tri-state driver illustrated in  FIG. 1D  may also be used for selectively connecting the I/O pads to the digital bus lines. One difference between the digital tri-state driver and the multiplexer example is that the digital tri-state driver selectively connects the pad  2 A to a single bus line, instead of two sub bus lines. 
     The input of the tri-state driver is connected to the pad  2 A, while the output is connected to a digital bus line. The enable is driven by the controller  99 . In the present example the tri-state driver is an inverter, e.g. if enabled, the illustrated tri-state driver outputs a low signal when receiving a high signal. In other examples, a non-inverting tri-state driver can be used. 
       FIG. 2  shows a system  101  similar to the system shown in  FIG. 1A  but having additional switching components in an embodiment. 
     The system  101  includes pads  2 A and  3 A. The ellipses  16  represent the other pads, which are not shown for ease of illustration. 
     The pad  2 A can be selectively connected to more than one of the bus lines, due to the additional switching components  4 A′. In the example, the number of analog switching components (e.g. including  4 A and  4 A′) corresponding to the pad  2 A is equal to the number of bus lines. In other examples, there may be less of the additional switches  4 A′, such as one switch to provide pad  2 A with access to one of the other bus lines  12 - 14 . The exact number and placement of the additional analog switches  4 A′ may depend on specifications and capability. A similar concept can be extended to the digital bus lines  21 - 24 , e.g. the addition of digital switching components  8 A′. 
     It is noted that the number of additional switches corresponding to each pad, for example the number of switches  4 A′ corresponding to pad  2 A, can be different than to another pad, for example the number of switches  5 A′ corresponding to pad  3 A. For that matter, some pads may have additional switches while other pads do not have any additional switches. The exact number and placement of the additional switches  4 A′,  5 A′,  8 A′, and  9 A′ may depend on specifications and capability. 
       FIG. 3  shows a system utilizing a plurality of bus networks in an electronic device in an embodiment. 
     In this case, two sets of four-line bus networks are shown, in systems  100  and  201  of common chip  200 . In this example, the second system  201  may have the same or different number of bus lines  31 - 34 , I/O ports  42 A-D and  43 A-D, and switches  6 A-D and  7 A-D. The four additional bus lines are  31 - 34 , which connect to I/O ports  42 A-D and  43 A-D. By using two separate shared bus networks, the length of bus lines on the circuit may be reduced, which may optimize performance and size. While  FIG. 3  shows an example with two shared bus networks, a device may have any number of shared networks. 
     Referring now to  FIGS. 3 and 5  in combination, the example circuit shown in  FIG. 5  illustrates the concept of separate networks of shared buses, as discussed above. In this example circuit of  FIG. 5 , there are four shared bus networks  74 ,  75 ,  76 , and  77 . For example, the upper networks  74  and  75  are separated from the lower two networks  76  and  77 . 
       FIG. 4A  shows a system similar to the system shown in  FIG. 3  but having additional switching components in an embodiment. 
     The addition of connections  91 A,  92 A,  93 A, and  94 A, as well as the switching components  91 B,  92 B,  93 B, and  94 B, allows two separate networks of shared buses of the same chip  200  to be selectively connected. For example, switch  91 B may be closed to connect pad  2 A to pad  42 A. It should be apparent that this allows two sub-wires to operate separately within different networks of buses at one time. At another time, the two sub-wires are combined to become one global wire extending between the different networks of buses. 
     Referring now to  FIGS. 4A and 5  in combination, the example circuit shown in  FIG. 5  illustrates the concept of selectively connected networks of shared buses, as discussed above. The vertically oriented line of switches  84  in the top middle of the example circuit of  FIG. 5  selectively connects shared bus networks  74  and  75 . The vertically oriented line of switches  85  in the bottom middle of the example circuit of  FIG. 5  selectively connects shared bus networks  76  and  77 . 
       FIG. 4B  shows a variation of the system shown in  FIG. 4A  in an embodiment. 
       FIG. 4B  shows a variant system  300  similar to the system  200 . In the system  300 , each pad  2 A-D and  3 A-D is selectively connected to both of the buses of the different bus networks. For example, pad  2 A is selectively connected to bus line  11  via switching component  4 A, and also selectively connected to bus line  31  via switching component  95 B (using connection  95 A). 
     Thus, the pad  2 A may connect to more than one bus network at the same time. This may be useful, for example, if bus line  11  were unavailable, pad  2 A could temporarily “borrow” a bus line  31  of another bus. The bus of bus lines  31 - 34  may be a bus typically used by other pads (as shown in  FIG. 4A ), or a bus that is used by internal components and not typically used by other pads (as shown in  FIG. 4B ). 
     The other connections  96 A,  97 A,  98 A,  85 A,  86 A,  87 A, and  88 A, as well as the other switching components  96 B,  97 B,  98 B,  85 B,  86 B,  87 B, and  88 B, may provide selective connections as shown. Such selective connections may be all controlled by the controller  99 , as previously discussed. 
     Several examples have been described above with reference to the accompanying drawings. Various other examples are also possible and practical. The system may be exemplified in many different forms and should not be construed as being limited to the examples set forth above. 
     The figures listed above illustrate examples of the application and the operation of such examples. In the figures, the size of the boxes is not intended to represent the size of the various physical components. Where the same element appears in multiple figures, the same reference numeral is used to denote the element in all of the figures where it appears. 
     Only those parts of the various units are shown and described which are necessary to convey an understanding of the examples to those skilled in the art. Those parts and elements not shown may be conventional and known in the art. 
     The system described above can use dedicated processor systems, micro controllers, programmable logic devices, or microprocessors that perform some or all of the operations described herein. For example, any of such devices may be used to control switching in a shared bus scheme. Some of the operations described above may be implemented in software and other operations may be implemented in hardware.