Patent Publication Number: US-8981380-B2

Title: Monolithic integration of silicon and group III-V devices

Description:
The present application claims the benefit of and priority to a pending provisional application entitled “Monolithic Integration of Silicon and Group III-V Devices and Efficient Circuits Utilizing Same,” Ser. No. 61/339,190 filed on Mar. 1, 2010. The disclosure in that pending provisional application is hereby incorporated fully by reference into the present application. 
    
    
     DEFINITION 
     In the present application, “group semiconductor” or “group III-V device” or similar terms refers to a compound semiconductor that includes at least one group III element and at least one group V element, such as, but not limited to, gallium nitride (GaN), gallium arsenide (GaAs), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN) and the like. Analogously, “III-nitride semiconductor” refers to a compound semiconductor that includes nitrogen and at least one group III element, such as, but not limited to, GaN, AlGaN, InN, AlN, InGaN, InAlGaN and the like. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to semiconductor device fabrication, and more particularly to silicon and group III-V semiconductor device fabrication. 
     2. Background Art 
     GaN HEMTs (Gallium Nitride High Electron Mobility Transistors), or generally III-nitride HEMTs, GaN FETs, or III-nitride transistors (and even more generally group III-V transistors), are known and utilized due to, for example, their high breakdown voltage and high switching speed. The group III-V transistors can be used in conjunctions with silicon devices in various circuits. For example, a particular silicon device, which can be used with group III-V transistors, is a silicon diode, such as a silicon Schottky diode. In a particular application, the silicon diode can be arranged in parallel with a group III-V transistor, where the anode of the silicon diode is connected to the source of the group III-V transistor and the cathode of the silicon diode is connected to the drain of the group III-V transistor. In another application, the silicon diode can be arranged in series with a group III-V transistor, where the cathode of the silicon diode is connected to the source of the group III-V transistor. 
     However, the fabrication of group III-V devices, such as, GaN transistors, is often not compatible with popular and commonly used silicon devices. Thus, GaN (or III-nitride) devices, for example, are often manufactured separate from silicon devices, typically resulting in two dies (for example a GaN die and a silicon die), which must be interconnected at the package level. The separate dies increase fabrication cost, packaging cost, area consumed on a PC board, and result in increased parasitic inductance, capacitance and resistance due to interconnections required at the packaging level and the PC board level. Moreover, due to increased assembly cost and complexity, and reduced throughput, the separate dies present severe disadvantages. 
     Thus, there is a need to overcome the drawbacks and deficiencies in the art by providing a solution where, for example, a semiconductor device can include a silicon device monolithically integrated with a group III-V device. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to monolithic integration of silicon and group III-V semiconductor devices, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a cross-sectional view of an exemplary group III-V semiconductor device. 
         FIG. 2A  shows an exemplary circuit, including a silicon device and a group III-V transistor, which can be implemented according to one embodiment of the present invention. 
         FIG. 2B  shows an exemplary monolithically integrated device, in accordance with one embodiment of the present invention, corresponding to the circuit in  FIG. 2A . 
         FIG. 3  shows an expanded view of a portion of an exemplary monolithically integrated device, in accordance with one embodiment of the present invention, corresponding to the monolithically integrated device in  FIG. 2B . 
         FIG. 4A  shows an exemplary circuit, including a silicon device and a group III-V transistor, which can be implemented according to one embodiment of the present invention. 
         FIG. 4B  shows an exemplary monolithically integrated device, in accordance with one embodiment of the present invention, corresponding to the circuit in  FIG. 4A . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is directed to monolithic integration of silicon and group III-V semiconductor devices. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention. 
     The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings. 
       FIG. 1  shows a cross-sectional view of exemplary group III-V semiconductor device  100 , and more particularly shows a III-Nitride high electron mobility transistor (HEMT). In other embodiments group III-V semiconductor device  100  can comprise, for example, a III-nitride FET, or other group III-V transistors not specifically discussed herein. Substrate N+  102  is shown, which can be a silicon layer in a silicon substrate heavily doped with N+dopants, or it can be a silicon N+ doped layer epitaxially grown on a substrate of sapphire or silicon carbide. A lightly doped epitaxial silicon layer shown as Epi N− layer  104  is formed atop Substrate N+  102 . 
     As shown in  FIG. 1 , group III-V semiconductor device  100  further includes buffer layer  106 , which can be, for example, an aluminum nitride (AlN) layer, situated over Epi N− layer  104 . In group III-V semiconductor device  100 , optional transition layers, such as transition layers  108  and  110  comprising aluminum gallium nitride (AlGaN), can be formed over the AlN layer with varying amounts of aluminum concentration. In the example shown, the aluminum concentration of the transition layers is higher closer to buffer layer  106  and lower closer to GaN layer  112 . Thus, transition layer  108  generally has a greater aluminum concentration relative to transition layer  110 . 
     Also shown in  FIG. 1 , gallium nitride (GaN) layer  112  is formed over buffer layer  106 , or over the optional transition layers in some embodiments. Furthermore, a relatively thin AlGaN layer  114  is formed over GaN layer  112 . At the interface of AlGaN layer  114  and GaN layer  112  a two-dimensional electron gas (2DEG) is created, as known in the art. 
     In the present example, group III-V semiconductor device  100  includes source electrode (also referred to as “source terminal”)  116  and drain electrode  118  (also referred to as “drain terminal”) and gate electrode  120  formed over gate insulator  122 . While  FIG. 1  shows an insulated gate, the gate of group III-V semiconductor device  100  does not have to be an insulated gate. For example, in other embodiments the gate can be a Schottky gate. Also, various embodiments of group III-V semiconductor device  100  can be made to operate as a depletion mode device (normally on) or an enhancement mode device (normally off). 
     Although group III-V semiconductor devices, such as, group III-V semiconductor device  100 , are known and used due to, for example, their high breakdown voltage and high switching speed, their fabrication is often not compatible with popular and commonly used silicon devices. Fabrication of group III-V semiconductor devices, for example, GaN (or III-nitride) devices, separate from silicon devices, typically results in two dies (for example a GaN die and a silicon die), which must be interconnected at the package level. The separate dies increase fabrication cost, packaging cost, area consumed on a PC board, and result in increased parasitic inductance, capacitance and resistance due to interconnections required at the packaging level and the PC board level. Moreover, due to increased assembly cost and complexity, and reduced throughput, the separate dies present severe disadvantages. 
     In one embodiment, the invention provides a III-nitride device (for example a GaN HEMT) monolithically integrated (i.e. integrated on a common substrate of a common die) with a silicon device. Such monolithic integration is disclosed by reference to a popular circuit used in high voltage, high power applications, that is the example of a silicon Schottky diode coupled in parallel with the source and drain of a GaN HEMT. In another example, the silicon Schottky diode is coupled in series with the GaN HEMT. The resulting monolithically integrated device can be used, for example, in a number of high voltage, high power switching applications. In one embodiment, a silicon P-N junction diode can be used instead of the silicon Schottky diode used in the present exemplary embodiment. 
     Referring now to  FIG. 2A ,  FIG. 2A  shows an exemplary circuit, including a silicon device and a group III-V transistor, which can be implemented according to one embodiment of the present invention. In  FIG. 2A , exemplary circuit  200  comprises silicon Schottky diode  226  coupled in parallel with the source and drain of GaN HEMT  228 . As shown in  FIG. 2A , the anode of silicon Schottky diode  226  is connected to the source of GaN HEMT  228  at node  230 , while the cathode of silicon Schottky diode  226  is connected to the drain of GaN HEMT  228  at node  232 . Circuit  200  is shown having three terminals which can be connected to external circuits: terminal  233  connected to node  232 , terminal  231  connected to node  230 , and terminal  234  connected to the gate of GaN HEMT  228 . In conventional implementations of circuit  200 , Schottky diode  226  and GaN HEMT  228  comprise discrete electrical components formed on different substrates of different dies. However, the present invention provides for monolithic integration of silicon Schottky diode  226  and GaN HEMT  228 , for example, as shown and described in relation to  FIG. 2B . 
     Referring to  FIG. 2B ,  FIG. 2B  shows an exemplary monolithically integrated device, in accordance with one embodiment of the present invention, corresponding to the circuit in  FIG. 2A . In  FIG. 2B , GaN HEMT structure  250  includes a group III-V transistor formed over “substrate N+  202 ,” i.e. a heavily doped N type silicon substrate in the present example. Various features of GaN HEMT structure  250  in  FIG. 2B  have been discussed in relation to  FIG. 1  and are not repeated in relation to  FIG. 2B . For example, elements in  FIG. 2B  can correspond to elements having similar reference numerals in  FIG. 1 . In other words, AlGaN layer  214 , GaN layer  212 , and transition layers  210  and  208  can correspond to AlGaN layer  114 , GaN layer  112 , and transition layers  110  and  108  in  FIG. 1 , and so on. Although GaN HEMT structure  250  is used as an example, the invention&#39;s concepts apply to GaN FETs, as wells as HEMTs and FETs made by use of different III-nitride or group III-V transistor structures. 
     As shown in  FIG. 2B , source  216  (also referred to as “source terminal”) of GaN HEMT structure  250  is connected to Epi N− layer  204 , a lightly doped epitaxially grown silicon region, through interconnect metal connection  236  and via  238 , referred to as an “anode via,” in  FIG. 2B . Metal contact  240 , at the bottom of anode via  238 , comprises Schottky metal, for example, platinum, aluminum or other appropriate metals. In one embodiment, Epi N− layer  204  is not used, and anode via  238  reaches silicon substrate  202 . 
     A Schottky diode is produced in region  300  of Epi N− layer  204 , which is circled in  FIG. 2B  and shown in more detail as expanded structure  300  in  FIG. 3 . Drain  218  (also referred to as “drain terminal”) of GaN HEMT structure  250  is connected through interconnect metal connection  242  and via  244 , referred to as a “cathode via,” to substrate N+  202 , for example to an N+ silicon layer  202 . Thus, the anode of silicon Schottky diode  226  in  FIG. 2A  can correspond to metal contact  240 , and the cathode of silicon Schottky diode  226  in  FIG. 2A  can correspond to substrate N+  202  connected to drain  218  through cathode via  244 . 
     In GaN HEMT structure  250 , anode via  238  extends along the group III-V transistor to contact the anode of the silicon diode and cathode via  244  and cathode via  244  extends along the group III-V transistor to contact the cathode of the silicon diode. Anode and cathode vias  238  and  244  generally do not have the same depth. It is preferable that metal contact  240  contact Epi N− layer  204  instead of substrate N+  202 , since the interface of metal contact  240  and substrate N+  202  would have too high of a reverse bias leakage current and would also have reduced break down voltage. Thus, metal contact  240  can interface with Epi N− layer  204  to produce good Schottky contact and to support a higher breakdown voltage. Epi N− layer  204  can be, for example, about 0.5 to 10 microns thick. By making Epi N− layer  204  thicker, the breakdown voltage of the device can be increased. 
     It is noted that in  FIG. 2A , the source of GaN HEMT  228  is coupled to the anode of silicon Schottky diode  226  at node  230 , which can correspond to connection  236  in  FIG. 2B . Connection  236  can be made by use of contacts and interconnect metal in various forms and layouts and techniques as known in the art. Similarly, in  FIG. 2A  the drain of GaN HEMT  228  is coupled to the cathode of silicon Schottky diode  226  at node  232 , which can correspond to connection  242  in  FIG. 2B . Connection  242  can be made by use of contacts and interconnect metal in various forms and layouts and techniques as known in the art. It is also noted that, similar to group III-V semiconductor device  100  in  FIG. 1 , GaN HEMT structure  250  in  FIG. 2B  can be an enhancement mode or depletion mode FET. 
     To further improve breakdown voltage, for example, to raise breakdown voltage above 30 or 40 volts, reference is made to  FIG. 3 , which shows an expanded view of region  300  showing the Schottky diode structure in more detail. In  FIG. 3 , substrate N+  302 , Epi N− layer  304 , buffer  306 , anode via  338 , and metal contact  340  correspond respectively to substrate N+  202 , Epi N− layer  204 , buffer layer  206 , anode via  238 , and metal contact  240  in  FIG. 2 . 
     To overcome early breakdown at corners  346  and  348  of the Schottky diode, P+ regions, for example, angled P+ implants can be used adjacent corners  346  and  348  where metal contact  340  would be deposited. According to a preferred method, immediately prior to filling anode via  338 , P+ angled implanting is performed at corners  346  and  348  of the trench. Typical P+ dopants, such as Boron can be used. The sealing of corners  346  and  348  with P+ regions results in a “merged Schottky” device, which combines a P-N junction with the Schottky diode. Instead of implanting P+ dopants, the center region of the anode can be blocked or masked so that P+ dopants can only diffuse into the corners of the region where metal contact  340  would interface with Epi N− layer  304 . The combined device is a Schottky diode with P-N junctions at corners  346  and  348 . There is still a Schottky action in the center of metal contact  340  situated between the P+ regions. 
     P+ regions at corners  346  and  348  increase breakdown voltage capability for two reasons. First, the P-N junctions (i.e. at corners  346  and  348 ) help spread-out the electric field to reduce electric field crowding at corners  346  and  348 . Second, when the Schottky diode is reverse biased, there would be extended depletion regions near corners  346  and  348  at the P+ regions, which pinch off the Schottky diode and reduce the reverse leakage current so that higher voltages can be used due to a lower leakage current and higher breakdown voltage of this merged Schottky diode and P-N junction configuration. In a particular example, P+ regions at corners  346  and  348  can raise breakdown voltage of the Schottky diode to 100 volts or more. 
     It is noted that use of a silicon Schottky diode, as opposed to a GaN Schottky diode presents advantages. For example, the forward bias voltage of the silicon Schottky diode is much lower than the forward bias voltage of a GaN Schottky diode. Moreover, to make GaN Schottky diodes, metals such as gold or copper or nickel are needed for Schottky metal in metal contact  340 , which are not generally compatible with silicon processing. The monolithic integrated device of the present invention can however be fabricated in a silicon fabrication house, thus resulting in significant cost savings. As noted above, in one embodiment, a silicon P-N junction diode can be used instead of the silicon Schottky diode used in the above exemplary embodiment. 
     Referring now to  FIG. 4A ,  FIG. 4A  shows an exemplary circuit, including a silicon device and a group III-V transistor, which can be implemented according to one embodiment of the present invention. In  FIG. 4A , exemplary circuit  400  comprises silicon Schottky diode  426  coupled in series with GaN HEMT  428  to produce an efficient and high voltage rectifier device.  FIG. 4A  shows that the cathode of silicon Schottky diode  426  is connected to source of GaN HEMT  428  at node  432 . Circuit  400  is shown having three terminals which can be connected to external circuits: terminal  430  connected to the anode of silicon Schottky diode  426 , terminal  434  connected to the gate of GaN HEMT  428 , and terminal  446  connected to the drain of GaN HEMT  428 . 
     Now Referring to  FIG. 4B ,  FIG. 4B  shows an exemplary monolithically integrated device, in accordance with one embodiment of the present invention, corresponding to circuit  400  in  FIG. 4A . The monolithically integrated structure is shown in  FIG. 4B  as GaN HEMT structure  450  and will be briefly discussed since, in many aspects, this series structure is similar to the parallel structure of  FIG. 2B . For example, elements in  FIG. 4B  can correspond to elements having similar reference numerals in  FIG. 2B . In other words, AlGaN layer  414 , GaN layer  412 , and transition layers  410  and  408  can correspond to AlGaN layer  214 , GaN layer  212 , and transition layers  210  and  208  in  FIG. 2B  and so on. 
     As shown in  FIG. 4B , anode via  438  extends to Epi N− layer  404  and is coupled to the anode of the silicon Schottky diode, which is formed by metal contact  440  at the bottom of anode via  438 . The top surface of anode via  438  can be connected by interconnect metal to ground or an external node (not shown in  FIG. 4B ). The cathode of the silicon Schottky diode is routed by cathode via  444  to the top surface of the die and is connected to source  416  of GaN HEMT  450  by interconnect metal represented by connection  424 , which can correspond to node  432  in  FIG. 4A . In one embodiment, a silicon P-N junction diode can be used instead of the silicon Schottky diode used in the present exemplary embodiment. 
     Thus, a monolithically integrated structure for implementing the series connection of a silicon Schottky diode and a GaN HEMT (or other group III-V transistor) is disclosed, which results in a high voltage and efficient rectifier device. Other aspects of implementation discussed in relation to  FIG. 2B  can also be used in relation to  FIG. 4B , but are not specifically repeated or discussed here. 
     According to various embodiments as discussed above, the present invention achieves silicon devices monolithically integrated with GaN (or generally group III-V) devices. Thus, according to the present invention, group III-V semiconductor devices can be fabricated with silicon only devices on a single die, thereby reducing fabrication cost, packaging cost, and area consumed on a PC board. Furthermore, parasitic inductance, capacitance, and resistance can be reduced by removing interconnections at the packaging level and the PC board level. In one example, a monolithically integrated device comprises a silicon Schottky diode and a group III-V semiconductor device connected in parallel to form a high voltage and efficient power switch. In another example, silicon Schottky diode and group III-V semiconductor device are connected in series to form a high voltage and efficient rectifier device. 
     From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would appreciate that changes can be made in form and detail without departing from the spirit and the scope of the invention. Thus, the described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.