Patent Publication Number: US-2017373101-A1

Title: Ffs mode array substrate and manufacturing method thereof

Description:
FIELD OF THE INVENTION 
     The present invention relates to a display field, and more particularly to an FFS mode array substrate and a manufacturing method thereof. 
     BACKGROUND OF THE INVENTION 
     Liquid crystal display (LCD) technology driven by an active array uses a dual-polarization characteristic to control an arrangement direction of liquid crystal molecules by applying an electric field, so as to carry out a switching control for an optical path travel direction of a backlight source. According to different electric field applying directions to the liquid crystal molecules, the LCD display mode is divided into a TN (Twist Nematic) series mode, a VA (Vertical Alignment) series mode, and an IPS (In-Plane Switching) series mode. The VA series mode is to apply a longitudinal electric field to the liquid crystal molecules, and the IPS series mode is to apply a transverse electric field to the liquid crystal molecules. In the IPS series mode, according to different applying transverse electric fields, it is further divided into an IPS mode and an FFS mode, etc. Each of the pixel units of the FFS display mode has an upper layer electrode and a lower layer electrode, namely a pixel electrode and a common electrode, and the lower layer common electrode is laid with an entire surface method in an aperture region. The FFS display mode has the advantages of: high penetration ratio, large viewing angle, and lower color shift, so that it has become a widely applied LCD display technology. 
     For improving the stability of an oxide TFT (thin film transistor), an etch stop layer (ESL) structure has been widely adopted, and the structure can efficaciously decrease influences for back channels from external environment factors and etching damage of source and drain electrodes. However, a manufacturing method of a traditional FFS display mode with the ESL structure requires an increased number of masks, so that the process complexity and the manufacturing cost are increased. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to provide an FFS mode array substrate and a manufacturing method thereof, so as to solve a technical problem: in the conventional technology, a manufacturing method of a traditional FFS display mode with an ESL structure requires an increased number of masks, so that the process complexity and the manufacturing cost are increased. 
     For solving the above-mentioned problem, the present invention provides technical solutions as follows: 
     One embodiment of the present invention provides a manufacturing method of an FFS mode array substrate, which comprises steps of: 
     forming a base layer, wherein the base layer is provided with a gate electrode and a channel semiconductor layer;
 
depositing a second insulation layer on the base layer, and forming a first through hole and a second through hole which are used to expose the channel semiconductor layer;
 
depositing a pixel electrode layer on the second insulation layer, wherein the pixel electrode layer is provided with a plurality of pixel electrode regions and first spacing regions located between each two of the pixel electrode regions;
 
depositing a first metal layer on the pixel electrode layer, wherein the first metal layer is provided with a source electrode region, a drain electrode region, and a second spacing region located between the source electrode region and the drain electrode region;
 
coating a first photoresist layer on the first metal layer, and removing photoresist of the first photoresist layer which corresponds to the first spacing regions and the second spacing regions;
 
etching the first metal layer and the pixel electrode layer to respectively form a source electrode and a drain electrode in the source electrode region and the drain electrode region of the first metal layer, and to form a plurality of pixel electrodes in the pixel electrode regions of the pixel electrode layer;
 
removing the first photoresist layer, and removing the first metal layer which is on the pixel electrodes; and
 
depositing a third insulation layer on the source electrode, the drain electrode, the pixel electrodes and the second insulation layer.
 
     In the manufacturing method of the FFS mode array substrate according to the present invention, the step of forming the base layer further includes steps of: 
     forming the gate electrode on a glass substrate;
 
depositing a first insulation layer and a semiconductor layer on the glass substrate and the gate electrode in order, wherein the semiconductor layer is provided with a channel region, a common electrode region, and a third spacing region located between the channel region and the common electrode region;
 
coating a second photoresist layer on the semiconductor layer, and removing photoresist of the second photoresist layer which corresponds to the third spacing region;
 
etching the semiconductor layer to form the channel semiconductor layer on the channel region of the semiconductor layer and to form a to-be-doped semiconductor layer on the common electrode region of the semiconductor layer;
 
removing the second photoresist layer which is on the to-be-doped semiconductor layer, and doping the to-be-doped semiconductor layer to form a common electrode layer; and
 
removing the second photoresist layer which is on the channel semiconductor layer;
 
wherein the second insulation layer is deposited on the channel semiconductor layer, the common electrode layer and the first insulation layer.
 
     In the manufacturing method of the FFS mode array substrate according to the present invention, two doped regions which respectively correspond to the first through hole and the second through hole are disposed on the channel semiconductor layer, and the step of removing the second photoresist layer which is on the channel semiconductor layer includes steps of: 
     removing the second photoresist layer which is on the two doped regions of the channel semiconductor layer; doping the two doped regions to transform semiconductor of the doped regions into conductors; and then removing the rest second photoresist layer on the channel semiconductor layer. 
     In the manufacturing method of the FFS mode array substrate according to the present invention, the step of forming the base layer further includes steps of: 
     depositing a common electrode layer and a second metal layer on the glass substrate in order, wherein the second metal layer is provided with a gate electrode region, and the common electrode layer is provided with a common electrode region, a TFT region, and a fourth spacing region located between the common electrode region and the TFT region;
 
coating a third photoresist layer on the second metal layer, and removing photoresist of the third photoresist layer which corresponds to the fourth spacing region;
 
etching the second metal layer and the common electrode layer to form a plurality of common electrodes on the common electrode region of the common electrode layer and to form the gate electrode on the gate electrode region of the second metal layer;
 
removing the third photoresist layer and the second metal layer which are above the common electrodes in order, and removing the third photoresist layer which is on the gate electrode;
 
depositing a first insulation layer on the common electrode layer, the gate electrode and the glass substrate, and forming the channel semiconductor layer on the first insulation layer;
 
wherein the second insulation layer is deposited on the channel semiconductor layer and the first insulation layer.
 
     In the manufacturing method of the FFS mode array substrate according to the present invention, the second insulation layer and the third insulation layer both include silicon nitride or silica. 
     In the manufacturing method of the FFS mode array substrate according to the present invention, the channel semiconductor layer includes indium gallium zinc oxide. 
     The present invention further provides an FFS mode array substrate, which comprises: 
     a base layer provided with a gate electrode and a channel semiconductor layer thereon;
 
a second insulation layer deposited on the base layer, wherein a first through hole and a second through hole exposing the channel semiconductor layer are formed in the second insulation layer;
 
a pixel electrode layer deposited on the second insulation layer, wherein the pixel electrode layer is provided with a plurality of pixel electrodes;
 
a source electrode and a drain electrode formed on the pixel electrode layer; and
 
a third insulation layer formed on the source electrode, the drain electrode, the pixel electrodes and the second insulation layer.
 
     In the FFS mode array substrate according to the present invention, the base layer further includes: 
     a glass substrate provided with a gate electrode thereon;
 
a first insulation layer formed on the glass substrate and the gate electrode; and
 
a semiconductor layer formed on the first insulation layer, wherein the semiconductor layer includes a channel region and a common electrode region;
 
the channel region of the semiconductor layer forms a channel semiconductor layer; and semiconductor of the common electrode region of the semiconductor layer is doped to form a common electrode layer;
 
wherein the second insulation layer is formed on the channel semiconductor layer, the common electrode layer and the first insulation layer.
 
     In the FFS mode array substrate according to the present invention, the base layer further includes: 
     a glass substrate;
 
a common electrode layer formed on the glass substrate, wherein the gate electrode is formed on the common electrode layer; and
 
a first insulation layer formed on the common electrode layer, the gate electrode and the glass substrate;
 
wherein the channel semiconductor layer is formed on the first insulation layer and is located above the gate electrode; and the second insulation layer is deposited on the channel semiconductor layer and the first insulation layer.
 
     In the FFS mode array substrate according to the present invention, the channel semiconductor layer includes indium gallium zinc oxide. 
     In the present invention, the source electrode and the drain electrode are formed on the pixel electrode layer, so that in the manufacturing process, the source electrode, the drain electrode and the pixel electrodes can be simultaneously formed by using a single mask, and therefore it has beneficial effects to shorten the process and improve the manufacturing efficiency. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic structural view of an FFS mode array substrate according to a first preferred embodiment of the present invention; 
         FIG. 2  is a schematic structural view of an FFS mode array substrate according to a second preferred embodiment of the present invention; 
         FIG. 3  is a flow chart of a manufacturing method of the FFS mode array substrate according to the preferred embodiment of the present invention; 
         FIGS. 4A-4I  are schematic manufacturing views of the manufacturing method of the FFS mode array substrate according to the first preferred embodiment of the present invention; and 
         FIGS. 5A-5J  are schematic manufacturing views of the manufacturing method of the FFS mode array substrate according to the second preferred embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The foregoing objects, features, and advantages adopted by the present invention can be best understood by referring to the following detailed description of the preferred embodiments and the accompanying drawings. Furthermore, the directional terms described in the present invention, such as upper, lower, front, rear, left, right, inside, outer, side, etc., are only directions with reference to the accompanying drawings, so that the used directional terms are used to describe and understand the present invention, but the present invention is not limited thereto. 
     In the drawings, units with similar structures use the same numerals. 
     Refer now to  FIG. 1 , which is a schematic structural view of an FFS mode array substrate according to a first preferred embodiment of the present invention. An FFS mode array substrate according to the preferred embodiment comprises: a glass substrate  11 , a gate electrode  12 , a semiconductor layer (not labeled in  FIG. 1 ), a first insulation layer  14 , a second insulation layer  20 , a pixel electrode layer  30 , a source electrode  41 , a drain electrode  42 , and a third insulation layer  50 , wherein the glass substrate  11 , the gate electrode  12 , the semiconductor layer (not labeled in  FIG. 1 ), and the first insulation layer  14  are composed into a base layer. 
     Specifically, the gate electrode  12  is formed on the glass substrate  11 ; the first insulation layer  14  is formed on the glass substrate  11  and the gate electrode  12 ; and the semiconductor layer is formed on the first insulation layer  14 . In the embodiment, the semiconductor layer is provided with a channel region, a common electrode region, and a third spacing region (not labeled) located between the channel region and the common electrode region. The channel region is used to form a channel semiconductor layer  13  of a thin film transistor, and the channel semiconductor layer  13  is located above the gate electrode  12 . The semiconductor layer in the common electrode region is used to form a common electrode layer  15  by a doping process. The semiconductor layer in the third spacing region is removed by a photoetching process. 
     The second insulation layer  20  is formed on the first insulation layer  14 , the common electrode layer  15 , and the channel semiconductor layer  13 . A first through hole and a second through hole which are used to expose the channel semiconductor layer  13  are formed in the second insulation layer  20  by a photoetching process. The pixel electrode layer  30  is formed on the second insulation layer  20 , and the pixel electrode layer  30  is provided with contact portions  30   a  located in a thin film transistor region and a plurality of pixel electrodes located beside the thin film transistor region, wherein the contact portions  30   a  contact with the channel semiconductor layer  13  through the first through hole and the second through hole. The source electrode  41  and the drain electrode  42  are both formed on the contact portions  30   a  of the pixel electrode layer  30 , and are electrically connected with the channel semiconductor layer  13  by the contact portions  30   a . The third insulation layer  50  is formed on the second insulation layer  20 , the source electrode  41 , the drain electrode  42 , and the pixel electrode layer  30 . 
     The semiconductor layer adopts an indium gallium zinc oxide (IGZO), namely the channel semiconductor layer  13  adopts the indium gallium zinc oxide (IGZO), but it is not limited thereto. 
     The first insulation layer  14  is made of silicon nitride and/or silica, which is mainly used to separate the gate electrode  12  from the common electrode layer  15 . The thickness of the first insulation layer  14  is in a range from 100 to 300 nanometers. 
     The second insulation layer  20  is made of silicon nitride and/or silica, which is mainly used to separate the pixel electrode layer  30  from the common electrode layer  15 . The thickness of the second insulation layer  20  is in a range from 50 to 150 nanometers. 
     The third insulation layer  50  is made of silicon nitride, which is a flat layer in the embodiment and mainly used to protect the pixel electrodes, the source electrode  41 , and the drain electrode  42 . 
     The pixel electrode layer  30  is an indium tin oxide (ITO) transparent electrode layer or an indium zinc oxide (IZO) transparent electrode layer, and the thickness thereof is in a range from 10 to 100 nanometers. 
     Additionally, in the embodiment, two doped regions which respectively correspond to the first through hole and the second through hole are disposed on the channel semiconductor layer  13 . The doped regions of the channel semiconductor layer  13  are doped, so that semiconductor of the regions is transformed into conductor, so as to decrease an impedance effect of the channel semiconductor layer  13 . 
     In the embodiment, the source electrode  41  and the drain electrode  42  are formed on the pixel electrode layer  30 , so that in the manufacturing process, the source electrode  41 , the drain electrode  42 , and the pixel electrodes can be simultaneously formed by using a single mask, and therefore it has beneficial effects to shorten the process and improve the manufacturing efficiency. 
     Additionally, by forming the channel semiconductor layer  13  and the common electrode layer  15  in the same layer, they can be formed by using a single mask, and the common electrode layer  15  can be formed by doping the common electrode region of the semiconductor layer, so that it further shortens the process and improves the manufacturing efficiency. 
     Refer now to  FIG. 2 , which is a schematic structural view of an FFS mode array substrate according to a second preferred embodiment of the present invention. An FFS mode array substrate according to the preferred embodiment comprises: a glass substrate  11 , a gate electrode  12 , a channel semiconductor layer  13 , a common electrode layer  15 , a first insulation layer  14 , a second insulation layer  20 , a pixel electrode layer  30 , a source electrode  41 , a drain electrode  42 , and a third insulation layer  50 , wherein the glass substrate  11 , the gate electrode  12 , the channel semiconductor layer  13 , the common electrode layer  15 , and the first insulation layer  14  are composed into a base layer. 
     Specifically, the common electrode layer  15  is formed on the glass substrate  11 ; the gate electrode  12  is formed on the common electrode layer  15 ; the first insulation layer  14  is formed on the glass substrate  11 , the common electrode layer  15  and the gate electrode  12 ; and the channel semiconductor layer  13  is formed on the first insulation layer  14  and is located above the gate electrode  12 . The second insulation layer  20  is formed on the first insulation layer  14  and the channel semiconductor layer  13 . A first through hole and a second through hole which are used to expose the channel semiconductor layer  13  are formed in the second insulation layer  20  by a photoetching process. The pixel electrode layer  30  is formed on the second insulation layer  20 , and the pixel electrode layer  30  is provided with contact portions  30   a  located in a thin film transistor region and a plurality of pixel electrodes located beside the thin film transistor region, wherein the contact portions  30   a  contact with the channel semiconductor layer  13  through the first through hole and the second through hole. The third insulation layer  50  is formed on the second insulation layer  20 , the source electrode  41 , the drain electrode  42 , and the pixel electrode layer  30 . 
     The channel semiconductor layer  13  adopts an indium gallium zinc oxide (IGZO), but it is not limited thereto. 
     The first insulation layer  14  is made of silicon nitride and/or silica, which is mainly used to separate the gate electrode  12  from the common electrode layer  15 . The thickness of the first insulation layer  14  is in a range from 100 to 300 nanometers. 
     The second insulation layer  20  is made of silicon nitride and/or silica, which is mainly used to separate the pixel electrode layer  30  from the common electrode layer  15 . The thickness of the second insulation layer  20  is in a range from 50 to 150 nanometers. 
     The third insulation layer  50  is made of silicon nitride, which is a flat layer in the embodiment and mainly used to protect the pixel electrodes, the source electrode  41 , and the drain electrode  42 . 
     The pixel electrode layer  30  is an indium tin oxide (ITO) transparent electrode layer or an indium zinc oxide (IZO) transparent electrode layer, and the thickness thereof is in a range from 10 to 100 nanometers. 
     In the embodiment, the source electrode  41  and the drain electrode  42  are formed on the pixel electrode layer  30 , so that in the manufacturing process, the source electrode  41 , the drain electrode  42 , and the pixel electrodes  30  can be simultaneously formed by using a single mask, and therefore it has beneficial effects to shorten the process and improve the manufacturing efficiency. 
     Additionally, by forming the gate electrode  12  on the pixel electrode layer  30 , they can be formed by using a single mask, so that in the manufacturing process, the gate electrode  12  and the pixel electrode layer  30  can be formed by using a single mask, so that it further shortens the process and improves the manufacturing efficiency. 
     Refer now to  FIG. 3 , which is a flow chart of a manufacturing method of the FFS mode array substrate according to the first preferred embodiment of the present invention. The manufacturing method comprises following steps of: 
     S 301 : forming a base layer, wherein the base layer is provided with a gate electrode and a channel semiconductor layer; 
     S 302 : depositing a second insulation layer on the base layer, and forming a first through hole and a second through hole which are used to expose the channel semiconductor layer; 
     S 303 : depositing a pixel electrode layer on the second insulation layer, wherein the pixel electrode layer is provided with a plurality of pixel electrode regions and first spacing regions located between each two of the pixel electrode regions; 
     S 304 : depositing a first metal layer on the pixel electrode layer, wherein the first metal layer is provided with a source electrode region, a drain electrode region, and a second spacing region located between the source electrode region and the drain electrode region; 
     S 305 : coating a first photoresist layer on the first metal layer, and removing photoresist of the first photoresist layer which corresponds to the first spacing regions and the second spacing regions; 
     S 306 : etching the first metal layer and the pixel electrode layer to respectively form a source electrode and a drain electrode in the source electrode region and the drain electrode region of the first metal layer, and to form a plurality of pixel electrodes in the pixel electrode regions of the pixel electrode layer; 
     S 307 : removing the first photoresist layer, and removing the first metal layer which is on the pixel electrodes; and 
     S 308 : depositing a third insulation layer on the source electrode, the drain electrode, the pixel electrodes, and the second insulation layer. 
     The above-mentioned steps are described in detail below by referring  FIGS. 4A-4I . 
     In the step S 301 , which specifically includes following sub steps of: 
     S 31 : forming the gate electrode on a glass substrate; 
     S 32 : depositing a first insulation layer and a semiconductor layer on the glass substrate and the gate electrode, in order, wherein the semiconductor layer is provided with a channel region, a common electrode region, and a third spacing region located between the channel region and the common electrode region; 
     S 33 : coating a second photoresist layer on the semiconductor layer, and removing photoresist of the second photoresist layer which corresponds to the third spacing region; 
     S 34 : etching the semiconductor layer to form the channel semiconductor layer on the channel region of the semiconductor layer and to form a to-be-doped semiconductor layer on the common electrode region of the semiconductor layer; 
     S 35 : removing the second photoresist layer which is on the to-be-doped semiconductor layer, and doping the to-be-doped semiconductor layer to form a common electrode layer; and 
     S 36 : removing the second photoresist layer which is on the channel semiconductor layer. 
     The second insulation layer is deposited on the channel semiconductor layer, the common electrode layer, and the first insulation layer. 
     In the step S 31 , as shown in  FIG. 4A , the material of the gate electrode  12  is selected from a group consisting of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), or any stack combination thereof, and is deposited and formed by a method of physical vapor deposition (PVD). The step S 32  follows thereafter. 
     In the step S 32 , as shown in  FIG. 4B , the first insulation layer  14  is made of silicon nitride and/or silica, and is deposited and formed by a method of chemical vapor deposition (CVD), and is mainly used to separate the gate electrode  12  from the common electrode layer  15 . The thickness of the first insulation layer  14  is in a range from 100 to 300 nanometers. The semiconductor layer  1315  adopts an indium gallium zinc oxide (IGZO), and is deposited and formed by a method of physical vapor deposition (PVD). The semiconductor layer is divided into a channel region  1 A, a common electrode region  1 B, and a third spacing region  1 C located between the channel region  1 A and the common electrode region  1 B. The step S 33  follows thereafter. 
     In the step S 33 , as shown in  FIG. 4C , the second photoresist layer  100  is processed by a half tone mask process (HTM) or a gray tone mask process (GTM), so as to remove photoresist of the second photoresist layer which corresponds to the third spacing region. The step S 34  follows thereafter. 
     In the step S 34 , as shown in  FIG. 4D , when etching the semiconductor layer  1315 , a dry etching or a wet etching can be adopted. In the step S 35 , when doping the to-be-doped semiconductor layer to form the common electrode layer  15 , a plasma treatment process with hydrogen (H) or helium (He) can be adopted. The step S 36  follows thereafter. 
     In the step S 36 , as shown in  FIG. 4E , when removing the second photoresist layer  100  from the channel semiconductor layer  13 , a photoresist oxidized method can be adopted. The step S 302  follows thereafter. 
     In the step S 302 , as shown in  FIG. 4F , when depositing the second insulation layer on the channel semiconductor layer, the common electrode layer, and the first insulation layer of the base layer, the second insulation layer is made of silicon nitride and/or silica, and mainly used to separate the pixel electrode layer  30  from the common electrode layer  15 . The thickness of the second insulation layer  20  is in a range from 50 to 150 nanometers. The first through hole  20   a  and the second through hole  20   b  expose the channel semiconductor layer, respectively. The step S 303  follows thereafter. 
     In the step S 303 , as shown in  FIG. 4G , the pixel electrode layer is an indium tin oxide (ITO) transparent electrode layer or an indium zinc oxide (IZO) transparent electrode layer, and the thickness thereof is in a range from 10 to 100 nanometers. In the step S 304 , the first metal layer  40  is deposited and formed by a method of physical vapor deposition (PVD). The step S 305  follows thereafter. 
     In the step S 305 , by a half tone mask process (HTM) or a gray tone mask process (GTM), the second photoresist layer is processed and the photoresist of the second photoresist layer which corresponds to the third spacing region is removed. 
     In the step S 306 , when etching the first metal layer  40  and the pixel electrode layer  30 , a wet etching process can be adopted, so as to respectively form the source electrode  41  and the drain electrode  42 , and to form the pixel electrodes in the pixel electrode regions of the pixel electrode layer  30 . 
     In the step S 307 , when removing the first photoresist layer, a method is to oxidize and then remove it. When removing the first metal layer  40 , a common technology can be adopted, so it does not give unnecessary details. After removing the first metal layer, the structure is like  FIG. 4H . The step S 308  follows thereafter. 
     In the step S 308 , as shown in  FIG. 4I , the third insulation layer  50  is made of silicon nitride, which is a flat layer in the embodiment, and mainly used to protect the pixel electrodes, the source electrode  41 , and the drain electrode  42 . 
     Additionally, in the embodiment, two doped regions which respectively correspond to the first through hole  20   a  and the second through hole  20   b  are disposed on the channel semiconductor layer  13 . The step S 36  includes: 
     Removing the second photoresist layer which is on the two doped regions of the channel semiconductor layer; doping the two doped regions, so that the semiconductor of the regions is transformed into conductors, so as to decrease an impedance effect of the channel semiconductor layer; and then removing the rest second photoresist layer on the channel semiconductor layer. By this step, an impedance of the channel semiconductor layer can be decreased. 
     In the embodiment, the source electrode  41  and the drain electrode  42  are formed on the pixel electrode layer  30 , so that in the manufacturing process, the source electrode  41 , the drain electrode  42 , and the pixel electrodes can be simultaneously formed by using a single mask, and therefore it has beneficial effects to shorten the process and improve the manufacturing efficiency. 
     Additionally, by forming the channel semiconductor layer  13  and the common electrode layer  15  in the same layer, they can be formed by using a single mask, and the common electrode layer  15  can be formed by doping the common electrode region of the semiconductor layer, so that it further shorten the process and improve the manufacturing efficiency. 
     The manufacturing method of the FFS mode array substrate according to the second preferred embodiment of the present invention comprises following steps of: 
     S 301 : forming a base layer, wherein the base layer is provided with a gate electrode and a channel semiconductor layer; 
     S 302 : depositing a second insulation layer on the base layer, and forming a first through hole and a second through hole which are used to expose the channel semiconductor layer; 
     S 303 : depositing a pixel electrode layer on the second insulation layer, wherein the pixel electrode layer is provided with a plurality of pixel electrode regions and first spacing regions located between each two of the pixel electrode regions; 
     S 304 : depositing a first metal layer on the pixel electrode layer, wherein the first metal layer is provided with a source electrode region, a drain electrode region, and a second spacing region located between the source electrode region and the drain electrode region; 
     S 305 : coating a first photoresist layer on the first metal layer, and removing photoresist of the first photoresist layer which corresponds to the first spacing regions and the second spacing regions; 
     S 306 : etching the first metal layer and the pixel electrode layer to respectively form a source electrode and a drain electrode in the source electrode region and the drain electrode region of the first metal layer, and to form a plurality of pixel electrodes in the pixel electrode regions of the pixel electrode layer; 
     S 307 : removing the first photoresist layer, and removing the first metal layer which is on the pixel electrodes; and 
     S 308 : depositing a third insulation layer on the source electrode, the drain electrode, the pixel electrodes, and the second insulation layer. 
     The step S 301  specifically includes following steps of: 
     S 351 : depositing a common electrode layer and a second metal layer on the glass substrate, in order, wherein the second metal layer is provided with a gate electrode region, and the common electrode layer is provided with a common electrode region, a TFT (thin film transistor region) region, and a fourth spacing region located between the common electrode region and the TFT region; 
     S 352 : coating a third photoresist layer on the second metal layer, and removing photoresist of the third photoresist layer which corresponds to the fourth spacing region; 
     S 353 : etching the second metal layer and the common electrode layer to form a plurality of common electrodes on the common electrode region of the common electrode layer and to form the gate electrode on the gate electrode region of the second metal layer; 
     S 354 : removing the third photoresist layer and the second metal layer which are above the common electrodes, in order, and removing the third photoresist layer which is on the gate electrode; 
     S 355 : depositing a first insulation layer on the common electrode layer, the gate electrode, and the glass substrate, and forming the channel semiconductor layer on the first insulation layer. 
     The glass substrate  11 , the gate electrode  12 , the channel semiconductor layer  13 , the common electrode layer  15 , and the first insulation layer  14  are composed into a base layer. The second insulation layer  20  is deposited on the channel semiconductor layer  13  and the first insulation layer  14 . 
     The above-mentioned steps are described in detail below by referring  FIGS. 5A-5J . 
     In the step S 351 , as shown in  FIG. 5A , the common electrode layer  15  is an indium tin oxide (ITO) transparent electrode layer or an indium zinc oxide (IZO) transparent electrode layer, and is deposited and formed by a method of physical vapor deposition (PVD). The thickness thereof is in a range from 10 to 100 nanometers. The second metal layer  120  is deposited and formed by a method of physical vapor deposition (PVD), and the material thereof is selected from a group consisting of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), or any stack combination thereof. The step S 352  follows thereafter. 
     In the step S 352 , as shown in  FIG. 5B , the third photoresist layer  300  is processed by a half tone mask process (HTM) or a gray tone mask process (GTM), so as to remove photoresist of the third photoresist layer which corresponds to the fourth spacing region. The step S 353  follows thereafter. 
     In the step S 353 , as shown in  FIG. 5C , when etching the second metal layer  120  and the common electrode layer  15 , a wet etching can be adopted, so as to form the common electrodes on the common electrode region of the common electrode layer  15  and to form the gate electrode  12  on the gate electrode region of the second metal layer  120 . The step S 354  follows thereafter. 
     In the step S 354 , when removing the third photoresist layer which is on the common electrodes, a method is to oxidize and then remove it, as shown in  FIG. 5D . When removing the second metal layer which is on the common electrode layer, an etching method can be adopted, shown in  FIG. 5E . The step S 355  follows thereafter. 
     In the step S 355 , as shown in  FIG. 5G , when depositing the first insulation layer on the common electrode layer, the gate electrode, and the glass substrate, a method of chemical vapor deposition (CVD) can be adopted, and the first insulation layer  14  is made of silicon nitride and/or silica, and is deposited and formed by the method of CVD. The channel semiconductor layer  13  adopts an indium gallium zinc oxide (IGZO), and is deposited and formed by a method of physical vapor deposition (PVD). The step S 302  follows thereafter. 
     In the step  3302 , as shown in  FIG. 5H , when depositing the second insulation layer  20  on the channel semiconductor layer  13  and the first insulation layer  14  of the base layer, the second insulation layer is made of silicon nitride and/or silica, and mainly used to separate the pixel electrode layer  30  from the common electrode layer  15 . The thickness of the second insulation layer  20  is in a range from 50 to 150 nanometers. The first through hole  20   a  and the second through hole  20   b  expose the channel semiconductor layer  13 , respectively. The step S 303  follows thereafter. 
     In the step S 303 , the pixel electrode layer  30  is an indium tin oxide (ITO) transparent electrode layer or an indium zinc oxide (IZO) transparent electrode layer, and the thickness thereof is in a range from 10 to 100 nanometers. 
     In the step S 304 , the first metal layer is deposited and formed by a method of physical vapor deposition (PVD). The step S 305  follows thereafter. 
     In the step S 305 , by a half tone mask process (HTM) or a gray tone mask process (GTM), the first photoresist layer is processed and the photoresist of the first photoresist layer which corresponds to the third spacing region is removed. 
     In the step S 306 , as shown in  FIG. 5I , when etching the first metal layer  40  and the pixel electrode layer  30 , a wet etching process can be adopted, so as to respectively form the source electrode  41  and the drain electrode  42 , and to form the pixel electrodes in the pixel electrode regions of the pixel electrode layer  30 . The step S 307  follows thereafter. 
     In the step S 307 , when removing the first photoresist layer, a method is to oxidize and then remove it. When removing the first metal layer, a common technology can be adopted, so it does not give unnecessary details. The step S 308  follows thereafter. 
     In the step S 308 , as shown in  FIG. 5J , the third insulation layer  50  is made of silicon nitride, which is a flat layer in the embodiment, and mainly used to protect the pixel electrodes, the source electrode  41 , and the drain electrode  42 . 
     In the embodiment, the source electrode  41  and the drain electrode  42  are formed on the pixel electrode layer  30 , so that in the manufacturing process, the source electrode  41 , the drain electrode  42 , and the pixel electrodes  30  can be simultaneously formed by using a single mask, and therefore it has beneficial effects to shorten the process and improve the manufacturing efficiency. 
     Additionally, by forming the gate electrode  12  on the pixel electrode layer  30 , they can be formed by using a single mask, so that in the manufacturing process, the gate electrode  12  and the pixel electrode layer  30  can be formed by using a single mask, so that it further shortens the process and improves the manufacturing efficiency. 
     The present invention has been described with preferred embodiments thereof and it is understood that many changes and modifications to the described embodiment can be carried out without departing from the scope and the spirit of the invention that is intended to be limited only by the appended claims.