Patent Publication Number: US-11038469-B2

Title: Power amplification module

Description:
This is a continuation of U.S. patent application Ser. No. 16/240,868 filed on Jan. 7, 2019, which is a continuation of U.S. patent application Ser. No. 15/629,146 filed Jun. 21, 2017, which is a continuation of U.S. patent application Ser. No. 15/179,417 filed on Jun. 10, 2016 which is a divisional of U.S. patent application Ser. No. 14/640,341 filed on Mar. 6, 2015 which claims priority from Japanese Patent Application No. 2014-059025 filed on Mar. 20, 2014 and Japanese Patent Application No. 2014-255478 filed on Dec. 17, 2014. The contents of these applications are incorporated herein by reference in their entireties. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a power amplification module. 
     Background Art 
     In a mobile communication device, such as a mobile phone, a power amplification module (power amplifier module) is used in order to amplify the power of a radio frequency (RF) signal to be transmitted to a base station. This power amplification module includes a power amplifier which amplifies the RF signal, and a bias circuit which supplies a bias current to a transistor constituting the power amplifier. 
       FIG. 10  is a diagram showing a configuration example of a power amplification module using an emitter follower type (common collector) bias circuit (for example, Patent Document 1). A bias circuit  1000  supplies a bias current to a bipolar transistor T 100  constituting a power amplifier  1010 , and has an emitter follower configuration. A battery voltage V BAT  is applied to the collector of a bipolar transistor T 110  constituting a bias circuit  1000 . 
     In this configuration, if the bipolar transistors T 100  and T 110  are, for example, heterojunction bipolar transistors (HBT), the base-emitter voltage V BE  of each bipolar transistor is about 1.3 V, and thus, the battery voltage V BAT  of about 2.8 V is required in order to drive the bipolar transistor T 110 . For this reason, in general, the minimum voltage of the battery voltage V BAT  is, for example, about 2.9 V. 
     On the other hand, in recent years, in a mobile communication device, such as a mobile phone, there has been demand for decreasing the minimum voltage of the battery voltage V BAT  to about 2.5 V in order to improve a talking time or a communication time. However, in the configuration using the emitter follower (common collector) type bias circuit  1000  described above, the battery voltage V BAT  of about 2.8 V is required, and thus, it is not possible to cope with this requirement. 
     Accordingly, as a configuration capable of operating a bias circuit with a lower battery voltage V BAT , a configuration in which a FET is used in a bias circuit has been suggested.  FIG. 11  is a diagram showing a configuration example of a power amplification module using a FET in a bias circuit (for example, Patent Document 2). As shown in  FIG. 11 , a FET (F 100 ) is used in a bias circuit  1100  which supplies a bias current to a bipolar transistor T 100  of a power amplifier  1010 . 
     However, as disclosed in Patent Document 2, a FET is used in the bias circuit, thereby making the battery voltage V BAT  for operating the bias circuit a low voltage. However, in the configuration disclosed in Patent Document 2, resistors R 100  and R 110  which output a control voltage to be applied to the gate of the FET (F 100 ) are different in temperature characteristics from the bipolar transistor T 100 . For this reason, in the configuration disclosed in Patent Document 2, the gain of the power amplifier  1010  fluctuates with change in temperature. 
     CITATION LIST 
     Patent Documents 
     [Patent Document 1] JP11-330866 A 
     [Patent Document 2] JP2010-233171 A 
     SUMMARY OF THE INVENTION 
     The invention has been accomplished in consideration of this situation, and an object of the invention is to provide a power amplification module capable of achieving low-voltage driving and improving temperature characteristics. 
     A power amplification module according to an aspect of the invention includes a first bipolar transistor which amplifies and outputs a radio frequency signal input to the base of the first bipolar transistor, a current source which outputs a control current, a second bipolar transistor which is connected to an output terminal of the current source, a first current out of the control current being input to the collector of the second bipolar transistor, a control voltage generation circuit which is connected to the output terminal of the current source and generates a control voltage according to a second current out of the control current, a first FET, the drain of the first FET being supplied with a power supply voltage, the source of the first FET being connected to the base of the first bipolar transistor, and the gate of the first FET being supplied with the control voltage, and a second FET, the drain of the second FET being supplied with the power supply voltage, the source of the second FET being connected to the base of the second bipolar transistor, and the gate of the second FET being supplied with the control voltage. 
     According to the invention, it is possible to provide a power amplification module capable of achieving low-voltage driving and improving temperature characteristics. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram showing a configuration example of a transmission unit including a power amplification module according to an embodiment of the invention. 
         FIG. 2  is a block diagram showing the configuration of a power amplification module. 
         FIG. 3  is a diagram showing an example of the configurations of a power amplifier and a bias circuit. 
         FIG. 4  is a simulation result showing an example of fluctuation in bias current I BIAS  due to variation in threshold voltage V TH  of FETs in a bias circuit. 
         FIG. 5  is a configuration example for increasing a one-round loop gain in the bias circuit. 
         FIG. 6  is a simulation result showing an example of fluctuation in bias current I BIAS  due to variation in threshold voltage V TH  of FETs in a bias circuit. 
         FIG. 7  is a simulation result showing an example of fluctuation in bias current I BIAS  according to variation in pair property of threshold voltages of FETs in the bias circuit. 
         FIG. 8  is a diagram showing an example of the configuration of the bias circuit for suppressing an influence of variation in pair property of threshold voltages of FETs. 
         FIG. 9  is a simulation result showing an example of fluctuation in bias current I BIAS  due to variation in threshold voltage V TH1  of a FET in a bias circuit. 
         FIG. 10  is a diagram showing a configuration example of a power amplification module using an emitter follower (common collector) type bias circuit. 
         FIG. 11  is a diagram showing a configuration example of a power amplification module using a FET in a bias circuit. 
         FIG. 12  is a diagram showing an example of the configuration of the power amplification module for suppressing a leak current. 
         FIG. 13  is a diagram showing the configuration of an example bias circuit. 
         FIG. 14  is a diagram showing the configuration of an example bias circuit. 
         FIG. 15  is a diagram showing the configuration of an example bias circuit. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, embodiments of the invention will be described referring to the drawings.  FIG. 1  is a diagram showing the configuration example of a transmission unit  100  including a power amplification module  130 . The transmission unit  100  is, for example used to transmit various signals, such as sound or data, to a base station from a mobile communication device, such as a mobile phone. Although the mobile communication device includes a reception unit which receives signals from the base station, description of the reception unit will be omitted. 
     As shown in  FIG. 1 , the transmission unit  100  includes a modulation section  110 , a transmission power control section  120 , a power amplification module  130 , a front-end section  140 , and an antenna  150 . 
     The modulation section  110  modulates an input signal based on a modulation system, such as high speed uplink packet access (HSUPA) or long term evolution (LTE), and generates an RF signal for radio transmission. The frequency of the RF signal is, for example, about hundreds of MHz to several GHz. 
     The transmission power control section  120  adjusts the power of the RF signal based on a transmission power control signal and outputs the RF signal. The transmission power control signal is generated based on, for example, an adaptive power control (APC) signal transmitted from the base station. For example, the base station measures a signal from the mobile communication device, thereby transmitting the APC signal to the mobile communication device as a command to adjust transmission power in the mobile communication device to an appropriate level. 
     The power amplification module  130  amplifies the power of the RF signal (RF IN ) output from the transmission power control section  120  to a level necessary for transmission to the base station and outputs an amplified signal (RF OUT ). 
     The front-end section  140  performs filtering on the amplified signal, switching between the amplified signal and the reception signal received from the base station, or the like. The amplified signal output from the front-end section  140  is transmitted to the base station through the antenna  150 . 
       FIG. 2  is a block diagram showing the configuration of a power amplification module  130 A which is an example of the power amplification module  130 . As shown in  FIG. 2 , the power amplification module  130 A includes power amplifiers  200 A and  200 B, bias circuits  210 A and  210 B, a bias control circuit  220 , matching circuits (MN: Matching Networks)  230 A,  230 B, and  230 C, and inductors L 1  and L 2 . 
     The power amplifiers  200 A and  200 B amplify the input RF signal and output the amplified signal. In the power amplification module  130 A, the power amplifier  200 A becomes an initial-stage (drive-stage) amplifier, and the power amplifier  200 B becomes a back-stage (power-stage) amplifier. In the configuration shown in  FIG. 2 , although the power amplifiers are provided in a two-stage configuration, a power amplifier may be provided in a single-stage configuration or power amplifiers may be provided in a three or more-stage configuration. 
     The bias circuits  210 A and  210 B supply a bias current to the power amplifiers  200 A and  200 B based on a bias control voltage V BIAS  supplied from the bias control circuit  220 . 
     The bias control circuit  220  outputs the bias control voltage V BIAS  for controlling the bias current to the bias circuits  210 A and  210 B. The bias control circuit  220  can adjust the output level of the bias control voltage V BIAS  in order to vary the gains of the power amplifiers  200 A and  200 B. 
     The matching circuits  230 A,  230 B, and  230 C are provided for impedance matching between the front and back circuits, and can be configured using, for example, a capacitor or an inductor. 
       FIG. 3  is a diagram showing examples of the configurations of the power amplifier  200 A and the bias circuit  210 A. The configurations of the power amplifier  200 B and the bias circuit  210 B shown in  FIG. 2  are the same as the configurations of the power amplifier  200 A and the bias circuit  210 A, and thus description thereof will be omitted. 
     As shown in  FIG. 3 , the power amplifier  200 A includes a bipolar transistor T 1 . The bipolar transistor T 1  is, for example, a HBT. In the bipolar transistor T 1 , a power supply voltage V cc  is applied to the collector through an inductor L 1 , the emitter is grounded, and an RF signal (RF IN1 ) is input to the base through the matching circuit  230 A. The base of the bipolar transistor T 1  is also supplied with a bias current I BIAS  from the bias circuit  210 A. An amplified signal (RF OUT1 ) of the RF signal (RF IN1 ) is output from the collector of the bipolar transistor T 1 . 
     A bias circuit  210 A- 1  which is an example of the bias circuit  210 A includes a current source  300 , a bipolar transistor T 2 , resistors R 1  and R 2 , FETs (F 1 , F 2 ), and a capacitor C 1 . 
     The current source  300  generates a control current I CTRL  according to the bias control voltage V BIAS  using the battery voltage V BAT  as a power supply voltage. 
     In the bipolar transistor T 2 , the collector is connected to an output terminal of the current source  300 , and the emitter is grounded. A current I 1  which is a part of the control current I CTRL  output from the current source  300  is input to the collector of the bipolar transistor T 2 . Similarly to the bipolar transistor T 1 , the bipolar transistor T 2  is, for example, a HBT. The bipolar transistor T 2  can have a size smaller than the bipolar transistor T 1 . The size of the bipolar transistor refers to an area occupied by the number of fingers of the transistor. 
     The resistor R 1  and the resistor R 2  connected in series are connected to the output terminal of the current source  300 . A current I 2 , which is a part of the control current I CTRL  output from the current source  300 , is input to the resistor R 1  and the resistor R 2 . The resistors R 1  and R 2  constitute a control voltage generation circuit which generates a control voltage V CTRL  according to the current I 2 . 
     In the FET F 1 , the drain is supplied with the battery voltage V BAT  as a power supply voltage, the source is connected to the base of the bipolar transistor T 1 , and the gate is supplied with the control voltage V CTRL . In the FET F 2 , the drain is supplied with the battery voltage V BAT  as a power supply voltage, the source is connected to the base of the bipolar transistor T 2 , and the gate is supplied with the control voltage V CTRL . The FETs (F 1 , F 2 ) can be depletion type FETs. The FET F 2  can have a size smaller than the FET F 1 . The size of the FET refers to an occupancy area of a gate width and a gate length. 
     In the capacitor C 1 , one end is connected to the output terminal of the current source  300 , and the other end is grounded. 
     In the bias circuit  210 A- 1  having this configuration, the bias current I BIAS  is supplied from the source of the FET F 1  to the base of the bipolar transistor T 1 . Hereinafter, the operation of the bias circuit  210 A- 1  will be described. 
     The FETs (F 1 , F 2 ) and the bipolar transistor T 2  operate with the control current I CTRL  from the current source  300 . If the potential of point Q (the base potential of the bipolar transistor T 2 ) shown in  FIG. 3  rises with the operation of the FET F 2 , the current I 1  flowing in the bipolar transistor T 2  increases. If the current I 1  increases, the current I 2  flowing in the resistors R 1  and R 2  decreases. If the current I 2  decreases, the control voltage V CTRL  falls. If the control voltage V CTRL  falls, a current I 3  flowing in the FET F 2  decreases, and the current I 1  flowing in the bipolar transistor T 2  decreases. If the current I 1  decreases, the current I 2  flowing in the resistors R 1  and R 2  increases. If the current I 2  increases, the control voltage V CTRL  rises. If the control voltage V CTRL  rises, the current I 3  flowing in the FET F 2  increases, and the current I 1  flowing in the bipolar transistor T 2  increases. 
     In this way, in the bias circuit  210 A- 1 , a closed loop operation is performed, and the control voltage V CTRL  settles at a certain point. The bias current I BIAS  according to the control voltage V CTRL  is output from the source of the FET F 1 . Accordingly, the bias current I BIAS  becomes a current according to the bias control voltage V BIAS . 
     In this closed loop, the control voltage V CTRL  supplied to the gate of the FET F 1  changes according to the temperature characteristics of the bipolar transistor T 2  and the FET F 2 . Accordingly, the bias current I BIAS  supplied to the bipolar transistor T 1  changes according to the temperature characteristics of the bipolar transistor T 2  and the FET F 2 . The temperature characteristics of the bipolar transistor T 1  are the same as the temperature characteristics of the bipolar transistor T 2 . The temperature characteristics of the FET F 1  are the same as the temperature characteristics of the FET F 2 . Accordingly, change in the bias current I BIAS  according to the temperature characteristics of the bipolar transistor T 2  and the FET F 2  is also made according to the temperature characteristics of the bipolar transistor T 1  and the FET F 1 . With this, it is possible to suppress fluctuation in gain of the power amplification module  130  due to change in temperature. 
     In the bias circuit  210 A- 1 , since the FET F 1  is used as a transistor connected to the base of the bipolar transistor T 1 , even if the battery voltage V BAT  is about 2.5 V, the bias circuit  210 A- 1  is operable. When the FET F 1  is a depletion type FET, even if the battery voltage V BAT  is about 2.0 V, it is possible to operate the bias circuit  210 A- 1 . 
     In  FIG. 3 , although the power amplifier  200 A and the bias circuit  210 A have been described, the same applies to the power amplifier  200 B and the bias circuit  210 B. Accordingly, the power amplification module  130 A can be driven with the battery voltage V BAT  which is a low voltage of about 2.5 V (or about 2.0 V), and can have improved temperature characteristics. 
     On the other hand, there is variation in threshold voltage V TH  of the FETs (F 1 , F 2 ) used in the bias circuit  210 A- 1  shown in  FIG. 3 . It is considered that this variation causes fluctuation in bias current I BIAS  output from the FET F 1  to the base of the bipolar transistor T 1 , and also causes fluctuation in gain of the power amplification module  130 A. 
       FIG. 4  is a simulation result showing an example of fluctuation in bias current I BIAS  due to variation in threshold voltage V TH  of the FETs (F 1 , F 2 ) in the bias circuit  210 A- 1  shown in  FIG. 3 . In  FIG. 4 , the horizontal axis represents the control current I CTRL  (A) which is output from the current source  300 , and the vertical axis represents the bias current I BIAS  (mA). In the example shown in  FIG. 4 , when the threshold voltage V TH  is increased or decreased from the reference by 0.1 V, fluctuation of about 10 mA occurs in the bias current I BIAS . 
     In order to reduce the influence of variation in threshold voltage V TH  of the FETs (F 1 , F 2 ), increasing the one-round loop gain G in the above-described closed loop when viewed from the Q point in the bias circuit  210 A- 1  may be considered. 
     If the gain of the bipolar transistor T 2  is Q, the emitter resistance of the bipolar transistor T 2  is R e , and the resistance values of the resistors R 1  and R 2  are respectively R 1  and R 2 , a one-round loop gain G in the bias circuit  210 A- 1  shown in  FIG. 3  is G=(Q/R e )×(R 1 +R 2 )×{R 2 /(R 1 +R 2 )}=(Q/R e )×R 2 . Accordingly, if the resistance value of the resistor R 2  is set to a large value, the one-round loop gain G can be increased. However, setting the resistance value of the resistor R 2  to a large value leads to an increase in chip size. 
       FIG. 5  is a configuration example for increasing the one-round loop gain G in the bias circuit  210 A. A bias circuit  210 A- 2  shown in  FIG. 5  includes a bipolar transistor T 3  instead of the resistor R 1  in the bias circuit  210 A- 1  shown in  FIG. 3 . Other configurations are the same as those shown in  FIG. 3 , and thus, description thereof will not be repeated. In the bipolar transistor T 3 , the collector is supplied with the battery voltage V BAT , the emitter is connected to one end of the resistor R 2 , and the base is connected to the output terminal of the current source  300 . 
     In the bias circuit  210 A- 2  shown in  FIG. 5 , the current I 2  which is a part of the control current I CTRL  from the current source  300  is input to the base of the bipolar transistor T 3 . A current I 4 , obtained by amplifying the current I 2 , is output from the emitter of the bipolar transistor T 3 , and the current I 4  is converted to the control voltage V CTRL  by the resistor R 2 . That is, the bipolar transistor T 3  and the resistor R 2  constitute a control voltage generation circuit which generates the control voltage V CTRL  according to the current I 2 . 
     If the current amplification factor of the bipolar transistor T 3  is hFE T3 , the one-round loop gain G in the bias circuit  210 A- 2  shown in  FIG. 5  is G=(Q/re)×R 2 ×hFE T3 . The current amplification factor hFE T3  of the bipolar transistor T 3  is, for example, a magnitude of about 100. Accordingly, in the bias circuit  210 A- 2  shown in  FIG. 5 , it is possible to increase the one-round loop gain G by the current amplification factor of the bipolar transistor T 3  without setting the resistance value of the resistor R 2  to a large value. With this, it is possible to suppress fluctuation in gain of the power amplification module  130 A due to variation in threshold voltage V TH  of the FETs (F 1 , F 2 ). 
       FIG. 6  is a simulation result showing an example of fluctuation in bias current I BIAS  due to variation in threshold voltage V TH  of the FETs (F 1 , F 2 ) in the bias circuit  210 A- 2  shown in  FIG. 5 . In  FIG. 6 , the horizontal axis represents the control current I CTRL  (A) which is output from the current source  300 , and the vertical axis represents the bias current I BIAS  (MA) In the example shown in  FIG. 6 , when the threshold voltage V TH  is increased or decreased from the reference by 0.1 V, the fluctuation width of the bias current I BIAS  is less than 1 mA. In this way, it is understood from the simulation result that the use of the configuration shown in  FIG. 5  can allow suppression of fluctuation in bias current I BIAS  due to variation in threshold voltage V TH  of the FETs (F 1 , F 2 ). 
     On the other hand, in the bias circuit  210 A- 2  shown in  FIG. 5 , variation in pair property may occur in the threshold voltage of the FETs (F 1 , F 2 ). Variation in pair property of the threshold voltages of the FETs (F 1 , F 2 ) is the difference between the threshold voltage V TH1  of the FET F 1  and the threshold voltage V TH2  of the FET F 2  in the same module.  FIG. 7  is a simulation result showing an example of fluctuation in bias current I BIAS  according to variation in pair property of the threshold voltages of the FETs (F 1 , F 2 ) in the bias circuit  210 A- 2  shown in  FIG. 5 . In  FIG. 7 , the horizontal axis represents the control current I CTRL  (A) which is output from the current source  300 , and the vertical axis represents the bias current I BIAS  (mA). In the example shown in  FIG. 7 , fluctuation of about 10 to 20 mA occurs in the bias current I BIAS  due to variation (±10 mV) in pair property of the threshold voltages of the FETs (F 1 , F 2 ). 
       FIG. 8  is a diagram showing an example of the configuration of the bias circuit  210 A for suppressing the influence of variation in pair property of the threshold voltages of the FETs (F 1 , F 2 ). A bias circuit  210 A- 3  shown in  FIG. 8  includes a resistor R 3  instead of the FET F 2  shown in  FIG. 5 . Other configurations are the same as those shown in  FIG. 5 , and thus, description will not be repeated. In the bias circuit  210 A- 3  shown in  FIG. 8 , the source of the FET F 1  is connected to the base of the bipolar transistor T 1  and is connected to one end of the resistor R 3 . The other end of the resistor R 3  is connected to the base of the bipolar transistor T 2 . That is, in the bias circuit  210 A- 3  shown in  FIG. 8 , the FET F 1  is used to generate the control voltage V CTRL  by the closed loop and to supply the bias current I BIAS  to the bipolar transistor T 1 . In the bias circuit  210 - 3  shown in  FIG. 8 , since only one FET is used, variation in pair property does not occur. 
       FIG. 9  is a simulation result showing an example of fluctuation in bias current I BIAS  due to variation in threshold voltage V TH1  of the FET F 1  in the bias circuit  210 A- 3  shown in  FIG. 8 . In  FIG. 9 , the horizontal axis represents the control current I CTRL  (A) which is output from the current source  300 , and the vertical axis represents the bias current I BIAS  (mA). In the example shown in  FIG. 9 , when the threshold voltage V TH1  is increased or decreased from the reference by 0.1 V, the fluctuation width of the bias current I BIAS  is less than 1 mA. In this way, it is understood that the use of the configuration shown in  FIG. 8  can allow suppression of fluctuation in bias current I BIAS  due to variation in threshold voltage V TH1  of the FET F 1 . 
     That is, in the bias circuit  210 A- 3  shown in  FIG. 8 , variation in pair property of the threshold voltages of the FETs (F 1 , F 2 ) does not occur, and it is possible to suppress fluctuation in bias current I BIAS  due to variation in threshold voltage V TH1  of the FET F 1 . Accordingly, it is possible to suppress fluctuation in gain of the power amplification module  130 A. 
     On the other hand, in the bias circuit  210 A, for example, if a difference is generated between the base-emitter voltages of the bipolar transistors T 1  and T 2  or the threshold voltages of the FETs (F 1 , F 2 ) due to manufacturing variation (variation in pair property), even when the control current I CTRL  is substantially zero, a leak current may flow in the bipolar transistor T 1 . 
       FIG. 12  is a diagram showing an example of the configuration of the power amplification module  130  for suppressing a leak current. A power amplification module  130 B shown in  FIG. 12  includes bias circuits  210 A′ and  210 B′ instead of the bias circuits  210 A and  210 B in the power amplification module  130 A shown in  FIG. 2 . The power amplification module  130 B also includes a power supply control circuit  1300 . In the power amplification module  130 B, other configurations are the same as those of the power amplification module  130 A, and thus, these configurations are represented by the same reference numerals and description thereof will not be repeated. 
     The bias circuits  210 A′ and  210 B′ are the same as the bias circuits  210 A and  210 B of the power amplification module  130 A, except that a regulation voltage V REG  is supplied as a power supply voltage. The details will be described below. 
     The power supply control circuit  1300  outputs the regulation voltage V REG  based on the battery voltage V BAT  and an amplification control signal CTRL AMP . The amplification control signal CTRL AMP  is a signal which indicates whether or not to perform the amplification of the RF signal in the power amplifiers  200 A and  200 B. 
     When the amplification control signal CTRL AMP  indicates performing the amplification of the RF signal in the power amplifiers  200 A and  200 B, the power supply control circuit  1300  outputs the battery voltage V BAT  as the regulation voltage V REG . 
     When the amplification control signal CTRL AMP  indicates not performing the amplification of the RF signal in the power amplifiers  200 A and  200 B, the power supply control circuit  1300  reduces the regulation voltage V REG . Specifically, for example, the power supply control circuit  1300  sets the regulation voltage V REG  to a zero level. In this case, the power supply control circuit  1300  may reduce the regulation voltage V REG  to a level (for example, less than 2.0 V), at which the bipolar transistor T 1  does not operate, instead of the zero level. 
       FIG. 13  is a diagram showing the configuration of a bias circuit  210 A′- 1  which is an example of the bias circuit  210 A′. The configuration of the bias circuit  210 B′ is the same as that of the bias circuit  210 A′, and thus, description thereof will not be repeated. The same configurations as those in the bias circuit  210 A- 1  shown in  FIG. 3  are represented by the same reference numerals, and description thereof will not be repeated. 
     As shown in  FIG. 13 , in the bias circuit  210 A′- 1 , the regulation voltage V REG  is supplied as a power supply voltage to the drains of the FETs (F 1 , F 2 ). As described above, when the amplification of the RF signal is not performed in the power amplifier  200 A, the regulation voltage V REG  falls to, for example, the zero level. Accordingly, in this case, it is possible to suppress a leak current from flowing in the bipolar transistor T 1 . 
     Similarly, the bias circuits  210 A- 2  and  210 A- 3  shown in  FIGS. 5 and 8  can be changed to a configuration in which the regulation voltage V REG  is supplied as a power supply voltage. Specifically, as an example of the bias circuit  210 A′, the configurations of bias circuits  210 A′- 2  and  210 A′- 3  shown in  FIGS. 14 and 15  can be used. 
     As above, these embodiments have been described. According to the power amplification module  130  of this embodiment, the FET F 1  can be used as a transistor for generating the bias current I BIAS  whereby the battery voltage V BAT  can be operable even at about 2.5 V. The control voltage V CTRL  which is supplied to the gate of the FET F 1  is controlled using the bipolar transistor T 2  having the same temperature characteristics as the bipolar transistor T 1  and the FET F 2  having the same temperature characteristics as the FET F 1 , whereby it is possible to suppress fluctuation in gain of the power amplification module  130  due to change in temperature. 
     According to these embodiments, as shown in  FIG. 5 , the bipolar transistor T 3  can be used as a circuit for generating the control voltage V CTRL , whereby it is possible to increase the gain of the closed loop which generates the control voltage V CTRL  and to reduce the influence of variation in threshold voltage of the FET. With this, it is possible to suppress fluctuation in gain of the power amplification module  130 . 
     According to these embodiments, in the configuration shown in  FIG. 3 or 5 , the sizes of the bipolar transistor T 2  and the FET F 2  for generating the control voltage V CTRL  can be made smaller than the sizes of the bipolar transistor T 1  and the FET F 1 . With this, it is possible to reduce current consumption in a circuit which generates the control voltage V CTRL . 
     According to these embodiments, the FETs (F 1 , F 2 ) can be depletion type FETs, whereby it is possible to operate the power amplification module  130  even if the battery voltage V BAT  is about 2.0 V. 
     According to these embodiments, as shown in  FIG. 8 , one FET F 1  can be used to generate the control voltage V CTRL  and to supply the bias current I BIAS , whereby it is possible to suppress fluctuation in gain of the power amplification module  130  due to variation in pair property. 
     According to these embodiments, as shown in  FIGS. 12 to 15 , when the amplification of the RF signal is not performed in the power amplifiers  200 A and  200 B, the power supply voltage which is supplied to the FETs constituting the bias circuits  210 A′ and  210 B′ falls, whereby it is possible to suppress a leak current from flowing in the bipolar transistor T 1 . 
     The respective embodiments described above facilitate understanding of the invention and are not to be interpreted as limiting the invention. The invention may be altered and improved without departing from the gist of the invention, and equivalents are intended to be embraced therein. That is, those skilled in the art can appropriately modify the embodiments, and these modifications are also encompassed within the scope of the invention as long as the modifications include the features of the invention. For example, the components included in the embodiments and the arrangements, the materials, the conditions, the shapes, the sizes, and the like of the components are not limited to the illustrated ones and can be varied appropriately. The components included in the embodiments can be combined as long as the combination is technically possible, and the combined components are also encompassed within the scope of the invention as long as the combined components include the features of the invention. 
     DESCRIPTION OF REFERENCE NUMERALS 
     
         
         
           
               100  transmission unit 
               110  modulation section 
               120  transmission power control section 
               130  power amplification module 
               140  front-end section 
               150  antenna 
               200  power amplifier 
               210  bias circuit 
               220  bias control circuit 
               230  matching circuit 
               300  current source 
             T 1  to T 3  bipolar transistor 
             F 1  to F 2  FET 
             R 1  to R 3  resistor 
             C 1  capacitor