Patent Publication Number: US-11650285-B2

Title: Chirp frequency non-linearity mitigation in radar systems

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
     This application claims priority from U.S. patent application Ser. No. 14/826,045 filed on Aug. 13, 2015 which is hereby incorporated by reference in its entirety. 
     TECHNICAL FIELD 
     The present disclosure relate generally to radars and more particularly to mitigation of non-linearity of chirps generated in radars. 
     BACKGROUND 
     The use of radars in automotive and industrial applications is evolving rapidly. Radar finds use in number of applications associated with a vehicle such as collision warning, blind spot warning, lane change assist, parking assist and rear collision warning. In industrial environment, radar finds use in determining relative position and relative velocity of obstacles around the radar. Pulse radar and FMCW (Frequency Modulated Continuous Wave) radar are predominately used in such applications. 
     In an FMCW radar, a synthesizer generates a ramp segment by frequency modulating a transmit signal. The ramp segment is also referred as a chirp signal. The ramp segment is amplified and emitted by one or more transmit units. The ramp segment is scattered by one or more obstacles to generate a scattered signal. The scattered signal is received by one or more receive units in the FMCW radar. A signal obtained by mixing the ramp segment and the scattered signal is termed as an IF (intermediate frequency) signal. The frequency (f) of the IF signal is proportional to the distance (d) of the obstacle from the FMCW radar and also to the slope (S) of the ramp segment. 
     The IF signal is sampled by an ADC (analog to digital converter). A sampled data generated by the ADC is processed by processor to obtain a position and a velocity of one or more obstacles. In one kind of FMCW radar, the processor performs FFT (fast fourier transform) on the sampled data. A peak in the FFT spectrum represents an obstacle and a location of the peak in the FFT spectrum is proportional to a relative distance of the obstacle from the FMCW radar. 
     An ideal synthesizer generates a linear ramp segment i.e. frequency varies linearly with time. A corresponding FFT spectrum obtained provides the information of the one or more obstacles. However, practical synthesizer generates a non-linear chirp signal due to finite settling time of the synthesizer. A non-linear chirp signal is one whose frequency does not vary linearly with time. The non-linearity in the chirp signal results in smearing (or overlapping) of peaks in the FFT spectrum which makes the detection of closely spaced obstacles difficult. Further, the smearing of peaks results in ghost objects since a point object will appear as multiple objects. Ghost objects are objects falsely detected by the FMCW radar which are not present in reality. The frequency non-linearity in the chirp signal therefore results in false detection of ghost objects and failure of detection of objects present in reality. 
     SUMMARY 
     According to an aspect of the disclosure, a radar apparatus is disclosed. The radar apparatus includes a transmit unit that generates a first signal in response to a reference clock and a feedback clock. The first signal is scattered by one or more obstacles to generate a second signal. A receive unit receives the second signal and generates N samples corresponding to the second signal. N is an integer. A conditioning circuit is coupled to the transmit unit and the receive unit. The conditioning circuit receives the N samples corresponding to the second signal, and generates N new samples using an error between the feedback clock and the reference clock. 
    
    
     
       BRIEF DESCRIPTION OF THE VIEWS OF DRAWINGS 
         FIG.  1    illustrates a radar apparatus, according to an embodiment; 
         FIG.  2    illustrates a block diagram of a frequency error estimator, according to an embodiment; 
         FIG.  3    illustrates a block diagram of a sigma-delta modulator error estimation unit, according to an embodiment; and 
         FIG.  4    illustrates waveforms that illustrate an FFT output obtained in a radar apparatus, according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       FIG.  1    illustrates a radar apparatus  100 , according to an embodiment. The radar apparatus  100  includes a transmit unit  110 , a receive unit  140 , a conditioning circuit  155  and a processor  160 . The transmit unit  110  includes a ramp generator  102 . A sigma-delta modulator (SDM)  104  is coupled to the ramp generator  102 . A synthesizer  112  is coupled to the SDM  104 . A reference crystal  106  generates a reference clock F ref    108 , and provides the reference clock F ref    108  to the synthesizer  112 . A power amplifier (PA)  126  is coupled to the synthesizer  112 . A transmit antenna unit  128  is coupled to the PA  126 . In one example, the transmit unit  110  includes a plurality of transmit antenna units. 
     The synthesizer  112  includes a divider  114 , a phase error pulse generator  116 , a charge pump  118 , a loop filter  120  and a VCO (voltage controlled oscillator)  122 . The phase error pulse generator  116  is coupled to the divider  114  and the reference crystal  106 . The charge pump  118  is coupled to the phase error pulse generator  116 , and the loop filter  120  is coupled to the charge pump  118 . The VCO  122  is coupled to the loop filter  120 . An output of the VCO  122  is provided to the divider  114  as a feedback. The PA  126  receives the output of the VCO  122 . 
     The receive unit  140  includes a receive antenna unit  142 , a (LNA) low noise amplifier  144 , a mixer  146 , an IF (intermediate frequency) filter  148  and an ADC (analog to digital converter)  150 . The LNA  144  is coupled to the receive antenna unit  142 . The mixer  146  is coupled to the transmit unit  110  and to the LNA  144 . The IF filter  148  is coupled to the mixer  146 , and the ADC  150  is coupled to the IF filter  148 . 
     The radar apparatus  100  includes the conditioning circuit  155 . The conditioning circuit  155  is coupled to the transmit unit  110  and the receive unit  140 . The conditioning circuit  155  includes a frequency error estimator  152 , a filter  154  and an ADC output modifier  156 . The frequency error estimator  152  is coupled to the phase error pulse generator  116  in the transmit unit  110 . The filter  154  is coupled to the frequency error estimator  152 , and the ADC output modifier  156  is coupled to the filter  154 . In one version, the filter  154  is a low pass filter. A processor  160  is coupled to the ADC output modifier  156 . In one version, the ADC output modifier  156  is part of the processor  160 . The radar apparatus  100  as illustrated has one transmit unit and one receive unit. In another example, the radar apparatus  100  includes multiple transmit units and multiple receive units. The radar apparatus  100  may include one or more additional components known to those skilled in the relevant art and are not discussed here for simplicity of the description. 
     The operation of the radar apparatus  100  illustrated in  FIG.  1    is explained now. The phase error pulse generator  116  receives the reference clock F ref    108 , and a feedback clock from the divider  114 . The reference clock F ref    108  is a constant frequency signal. The phase error pulse generator  116  generates a pulse once in every time period of the reference clock F ref    108 . The phase error pulse generator  116  also generates an additional digital signal that denotes whether the feedback clock is leading or lagging in phase as compared to the reference clock F ref    108 . The pulse along with the additional digital signal generated by the phase error pulse generator  116  represents an error between the feedback clock and the reference clock F ref    108 . Thus, the phase error pulse generator  116  estimates the error between the feedback clock and the reference clock F ref    108 . The error between the feedback clock and the reference clock F ref    108  represents a time difference between a positive edge of the feedback clock and a positive edge of the reference clock F ref    108 . 
     The charge pump  118  generates a voltage signal in response to the error received from the phase error pulse generator  116 . The voltage signal is proportional to a phase error between the feedback clock and the reference clock F ref    108 . The loop filter  120  attenuates the voltage signal received from the charge pump  118  to filter a high frequency noise, and thus generates a low frequency signal. 
     The VCO  122  generates a first signal  124 . The VCO  122  alters an output phase and a frequency of the first signal  124  based on the low frequency signal received from the loop filter  120 . Thus, the first signal  124  is phase locked to the reference clock F ref    108 , and hence the phase error is eliminated. The frequency of the first signal  124  generated by the VCO  122  is proportional to a frequency of the reference clock F ref    108 . In one example, the frequency of the first signal  124  is 80 GHz, and the frequency of the reference clock F ref    108  is 12 GHz. Therefore, proportionality constant is 6.667 (when 80 is divided by 12). The first signal  124  is also provided to the divider  114  as a feedback. 
     Since, the frequency of the first signal  124  is related to the frequency of the reference clock F ref    108  by the proportionality constant, the divider  114  is configured to divide the first signal  124  by the proportionality constant. The ramp generator  102  generates a fractional division control word. The fractional division control word is, in one example, a factional number by which the first signal  124  is to be divided. The sigma-delta modulator (SDM)  104  generates an integer division control word which is a sequence of integers from the fractional division control word. 
     The divider  114  in the synthesizer  112  receives the integer division control word and the first signal  124 . The divider  114  divides the first signal  124  by the integer division control word to generate the feedback clock. In one version, the fractional division control word is 6.667 which is equal to the proportionality constant. The SDM  104  generates the sequence of integers (6,7,7) from the fractional division control word. The sequence of integers divides the first signal  124  by 6, 7, 7 respectively, thereby generating the feedback clock. The divider  114  divides the first signal  124  to generate the feedback clock whose frequency matches the frequency of the reference clock F ref    108 . 
     The power amplifier (PA)  126  receives the first signal  124  from the synthesizer  112  and amplifies the first signal  124 . In one version, the PA  126  performs one or more of the following operation on the first signal  124 : frequency multiplication or division, phase and/or frequency modulation and amplification. The first signal  124  is transmitted by the transmit antenna unit  128 . In an example, the first signal  124  is a ramp segment also called as chirp. The chirp has a starting frequency and a slope. The starting frequency is a frequency at the beginning of the chirp. The slope of the chirp is a rate of change of frequency of the chirp during duration of the chirp. An ideal slope is a desired slope of the chirp. The first signal  124  is scattered by one or more obstacles to generate a second signal  145 . 
     The receive unit  140  receives the second signal  145 . The second signal  145 , in one version, is a ramp segment. The receive antenna unit  142  receives the second signal  145 . The LNA  144  amplifies the second signal  145 . The mixer  146  is configured to mix the second signal  145  and the first signal  124  to generate an IF (intermediate frequency) signal. The IF filter  148  generates a filtered IF signal from the IF signal. In one version, the IF filter  148  filters the IF signal to generate the filtered IF signal. The ADC  150  samples the filtered IF signal to generate N samples corresponding to the second signal  145 . 
     The frequency error estimator  152  is coupled to the phase error pulse generator  116  in the transmit unit  110 . The frequency error estimator  152  generates an instantaneous frequency error signal from the error between the feedback clock and the reference clock F ref    108 . The filter  154  low pass filters the instantaneous frequency error signal to generate a filtered frequency error signal. The filtered frequency error signal represents a difference between a desired frequency of the first signal  124  and an actual frequency of first signal  124  generated by the synthesizer  112 . A slope of the first signal  124  at a given instant is referred as instantaneous slope. A slope error is proportional to the filtered frequency error signal. The slope error is a difference between the instantaneous slope of the first signal  124  and the ideal slope. The slope error represents a rate of change of filtered frequency error signal over time. 
     The ADC output modifier  156  receives the N samples corresponding to the second signal  145  from the ADC  150 . N is an integer. In one example, the filter  154  is part of the frequency error estimator  152 , and the frequency error estimator  152  generates the filtered frequency error signal. 
     The ADC output modifier  156  generates a new sampling time instants of the N samples from the filtered frequency error signal. The ADC output modifier  156  also estimates coefficients of a polynomial to be fitted to the N samples using the new sampling time instants. The ADC output modifier  156  resamples the N samples using the estimated coefficients, and generates the N new samples. Thus, the conditioning circuit  155  receives the N samples corresponding to the second signal  145  from the receive unit  140  and generates N new samples using the error between the feedback clock and the reference clock F ref    108 . 
     The processor  160  determines a position and a velocity of the one or more obstacles from the N new samples. The radar apparatus  100  provides for real time estimation of non-linearity in the first signal  124  or the chirp. A frequency non-linearity in the transmitted first signal  124  is also present as a sampling time jitter in the IF signal generated in the receive unit  140 . This sampling time jitter is estimated in the synthesizer  112 , the frequency error estimator  152  and the filter  154 . The sampling time jitter is corrected in the ADC output modifier  156 . 
     The radar apparatus  100  utilizes the phase error pulse generator  116  in the synthesizer  112  to estimate the non-linearity in the first signal  124 . The radar apparatus  100  does not estimates polynomial coefficients for the ADC output modifier  156 . Also, the radar apparatus  100  does not require a known reference target to estimate the non-linearity in the first signal  124 . The radar apparatus  100  can work without any offline calibration for the non-linearity in the first signal  124 . 
     In one example, the radar apparatus  100  utilizes offline calibration. In offline calibration, the filtered frequency error signal generated by the filter  154  is stored in a non-volatile memory. The filtered frequency error signal is averaged over multiple chirps before storing in the non-voltage memory. This storage is performed during or after manufacturing of the radar apparatus  100  i.e. before the radar apparatus  100  is deployed on-field or before the radar apparatus  100  is put into use. The filtered frequency error signal generated by the filter  154  during actual operation is then rejected by the ADC output modifier  156 . The ADC output modifier  156  uses the data stored in the non-volatile memory. This improves an accuracy of the radar apparatus  100 . 
     In another example, the radar apparatus  100  utilizes pseudo offline calibration. The pseudo offline calibration is performed when the radar apparatus  100  has been deployed on-field. Even before the first signal  124  (or the chirp) is transmitted by the transmit antenna unit  128 , the filtered frequency error signal generated by the filter  154  is stored in a non-volatile memory. The filtered frequency error signal is averaged over multiple chirps before storing in the non-voltage memory. The filtered frequency error signal generated by the filter  154  during actual operation is then rejected by the ADC output modifier  156 . The ADC output modifier  156  uses the data stored in the non-volatile memory. 
     The radar apparatus  100  generates the first signal  124  which is non-linear. Thus, the first signal  124  is a non-linear chirp. The phase error pulse generator  116  in the synthesizer  112  estimates the non-linearity in the first signal  124 . The frequency error estimator  152  generates an instantaneous frequency error signal from the error between the feedback clock and the reference clock F ref    108 . The filter  154  low pass filters the instantaneous frequency error signal to generate a filtered frequency error signal. 
     The non-linearity in the first signal  124  is compensated by processing an output of the ADC  150  based on the filtered frequency error signal. As discussed earlier, the slope error is proportional to the filtered frequency error signal. The non-linearity in the first signal  124  is compensated in the following way. When the instantaneous slope is different from the ideal slope, the N samples obtained from the ADC  150  are skipped or interpolated. For example, when the instantaneous slope is half of the ideal slope, alternate samples of the N samples obtained from the ADC  150  are skipped. When the instantaneous slope is twice of the ideal slope, the N samples obtained from the ADC  150  are interpolated by two to generate new samples. The skipping and interpolation are performed finely through digital resampling of the N samples from the ADC  150  to generate the N new samples. 
       FIG.  2    illustrates a block diagram of a frequency error estimator  200 , according to an embodiment. The frequency error estimator  200  is analogous to the frequency error estimator  152  in connection and operation. The frequency error estimator  200  includes a TDC (time-to-delay converter)  204 . A multiplier  206  is coupled to the TDC  204 . 
     A sigma-delta modulator (SDM) error estimation unit  210  receives an integer division control word N int    212  and a fractional division control word N frac    214 . The integer division control word N int    212  is similar to the integer division control word generated by the ramp generator  102 . The fractional division control word N frac    214  is similar to the fractional division control word generated by the SDM  104 . A subtractor  216  is coupled to the multiplier  206  and the SDM error estimation unit  210 . A difference filter  218  is coupled to the subtractor  216 . 
     The operation of the frequency error estimator  200  illustrated in  FIG.  2    is explained now. It is understood that the following solution is one of the many ways of implementing frequency error estimator  200  and variations, and alternative constructions are apparent and well within the spirit and scope of the disclosure. The frequency error estimator  200  is explained in connection with the radar apparatus  100  (illustrated in  FIG.  1   ). The first signal  124  transmitted by the transmit unit  110  is a non-linear signal and hence, also referred as non-linear chirp signal. A phase of the first signal  124  transmitted by the transmit unit  110  is defined as: 
                       ϕ     non   ⁢     -     ⁢   ideal       ⁡     (   t   )       =       2   ⁢   π   ⁢           ⁢     f   c     ⁢   t     +     2   ⁢   π   ⁢     B     T   r       ⁢       t   2     2       +       ϕ   e     ⁡     (   t   )                 (   1   )               
where, B is a bandwidth of the first signal, T r  is a duration of the first signal, f c  is a start frequency of the first signal and ϕ e (t) is an instantaneous non-linearity in the transmitted first signal which is defined as:
 
                       ϕ   e     ⁡     (   t   )       =     2   ⁢   π   ⁢       ∫   0   t     ⁢         f   e     ⁡     (   t   )       ⁢     ∂   t                   (   2   )               
where, f e  is an instantaneous frequency of the first signal  124 . The first signal  124  is scattered by one or more obstacles to generate the second signal  145 .
 
     The second signal  145  is received by the receive unit  140  after a delay t d . The mixer  146  mixes the first signal  124  from the transmit unit  110  and the second signal  145  to generate the IF (intermediate frequency) signal. A phase of the IF signal is defined as: 
                       Δϕ     non   ⁢     -     ⁢   ideal       ⁡     (   t   )       =           ϕ     non   ⁢     -     ⁢   ideal       ⁡     (     t   -     t   d       )       -       ϕ     non   ⁢     -     ⁢   ideal       ⁡     (   t   )         =         -   2     ⁢   π   ⁢           ⁢     f   c     ⁢     t   d       +         π   ⁢           ⁢   B       T   r       ⁡     [         (     t   -     t   d       )     2     -     t   2       ]       +       φ   e     ⁡     (     t   -     t   d       )       -       φ   e     ⁡     (   t   )                   (   3   )               
Using Taylor Series expansion for equation 3,
 
                           φ   e     ⁡     (     t   -     t   d       )       ≈         φ   e     ⁡     (   t   )       -       t   d     ⁢       ∂       φ   e     ⁡     (   t   )           ∂   t             =         φ   e     ⁡     (   t   )       -     2   ⁢   π   ⁢           ⁢     t   d     ⁢       f   e     ⁡     (   t   )             ,           (   4   )                   Δϕ     non   ⁢     -     ⁢   ideal       ⁡     (     nT   s     )       =         ϕ   o     -     2   ⁢   π   ⁢           ⁢       St   d     ⁡     (       nT   s     +         f   e     ⁡     (     nT   s     )       S       )       ⁢   where   ⁢           ⁢   S       =     B     T   r                 (   5   )               
where, T s  is a sampling time period of the ADC  150 . Equation 5 illustrates that the non-linearity in the first signal  124  results in sampling of the IF signal at incorrect time instance. This is referred as sampling jitter.
 
     A non-linearity in the first signal  124  also occurs at an output of the phase error pulse generator  116 . The TDC  204  is coupled to the phase error pulse generator  116  and receives an error between the feedback clock and the reference clock F ref    108 . The TDC  204  converts the error between the feedback clock and the reference clock F ref    108  to a phase error. 
     The multiplier  206  converts the phase error to a first signal phase error by multiplying with 2πF ref N frac , where F ref  is the reference clock  108  and N frac  is the fractional division control word  214 . Thus, the first signal phase error is defined as:
 
{tilde over (ϕ)} err   [nT   ref ]=2π F   ref   N   frac   t   err   TDC   [nT   ref ]  (6)
 
where, t err   TDC  is a quantized version of the error between the feedback clock and the reference clock F ref    108 .
 
     The SDM error estimation unit  210  estimates an additional phase error associated with the sigma-delta modulator  104 . The sigma-delta modulator  104  induces quantization error which is systematic in nature and is compensated from the first signal phase error using the subtractor  216 . The additional phase error is defined as: 
     
       
         
           
             
               
                 
                   
                     sdm_err 
                     ⁡ 
                     
                       [ 
                       n 
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                   = 
                   
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                           n 
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                                 N 
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                               ⁡ 
                               
                                 [ 
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     The subtractor  216  subtracts the additional phase error from the first signal phase error to generate an instantaneous phase error which is defined as:
 
{tilde over (ϕ)} err   [nT   ref ]=2π F   ref   N   frac   t   err   TDC   [nT   ref   ]−sdm _ err[nT   ref ]  (8)
 
     The difference filter  218  generates an instantaneous frequency error signal  220  by differentiating the instantaneous phase error as defined below:
 
 f   e   [n]=φ   err   [n]−ϕ   err   [n− 1]  (9)
 
     The filter  154  low pass filters the instantaneous frequency error signal to generate a filtered frequency error signal. The sampling jitter in the IF signal as illustrated in equation 5 is corrected through the ADC output modifier  156  using the instantaneous frequency error signal  220  illustrated in equation 9. 
     The IF filter  148  generates a filtered IF signal from the IF signal. The ADC  150  samples the filtered IF signal to generate N samples corresponding to the second signal  145 . The N samples are obtained for T r  which is the duration of the first signal  124 . These samples along with their new sampling time instants (obtained from filtered frequency error signal as illustrated in equation 9) are provided to the ADC output modifier  156 . In one example, the ADC output modifier is a 3 rd  order ADC output modifier. 
     A 3 rd  order ADC output modifier requires 4 successive samples of the N samples for polynomial evaluation. The coefficients for polynomial expansion are estimated using a closed-form matrix inversion defined as: 
                       [           y   ⁡     (       T   in     ⁡     [   1   ]       )                 y   ⁡     (       T   in     ⁡     [   2   ]       )                 y   ⁡     (       T   in     ⁡     [   3   ]       )                 y   ⁡     (       T   in     ⁡     [   4   ]       )             ]       14243     Incoming   ⁢           ⁢   samples         =         [         1           T   in     ⁡     [   1   ]               T   in   2     ⁡     [   1   ]               T   in   3     ⁡     [   1   ]               1           T   in     ⁡     [   2   ]               T   in   2     ⁡     [   2   ]               T   in   3     ⁡     [   2   ]               1           T   in     ⁡     [   3   ]               T   in   2     ⁡     [   3   ]               T   in   3     ⁡     [   3   ]               1           T   in     ⁡     [   4   ]               T   in   2     ⁡     [   4   ]               T   in   3     ⁡     [   4   ]             ]       14444244443     Vander   ⁢           ⁢   Monde   ⁢           ⁢   Matrix         ⁢       [           a   0               a   1               a   2               a   3           ]       {         Polynominal           Coefficinet                       (   10   )               
where y(T in [n]) is the n th  sample from the ADC  150  and T in [n] is defined in equation 5. Once the coefficients {a0,a1,a2,a3} for polynomial fit are known using equation 9, the polynomial is evaluated at desired time instants mT s  defined as
 
 ŷ ( mT   s )= a   0   +a   1 ( mT   s )+ a   2 ( mT   s ) 2   +a   3 ( mT   s ) 3   (11)
 
     Thus, the radar apparatus  100  is able to efficiently determine a position and a velocity of one or more obstacles from ŷ(mT s ) instead of using samples from the ADC  150 . In one embodiment, the SDM error estimation unit  210  is not part of the frequency error estimator  200 . 
       FIG.  3    illustrates a block diagram of a sigma-delta modulator (SDM) error estimation unit  300 , according to an embodiment. The SDM error estimation unit  300  is analogous to the sigma-delta modulator (SDM) error estimation unit  210  (illustrated in  FIG.  2   ) in connection and operation. The SDM error estimation unit  300  receives the integer division control word N int    312  and the fractional division control word N frac    314 . 
     A division unit  316  divides the fractional division control word N frac    314  by the integer division control word N int    312  to generate a division ratio. A subtraction unit  318  subtracts the division ratio from 1 to generate a subtracted output. An integrator unit  320  integrates the subtracted output for N samples to generate an integrated output. 
     A multiplier  324  is used to multiply the integrated output by a constant to generate a modified integrated output. In one example, the constant is 2π. A delay unit  326  receives an output of the multiplier  324  and generates an additional phase error  330  from the modified integrated output. In one example, the delay unit  326  generates an additional phase error  330  by delaying the modified integrated output. The additional phase error  330  is associated with the sigma-delta modulator  104  (illustrated in  FIG.  1   ). The additional phase error  330  is defined as: 
     
       
         
           
             
               
                 
                   
                     sdm_err 
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                           n 
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                                 [ 
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       FIG.  4    illustrates waveforms that illustrate an FFT output obtained in a radar apparatus, according to an embodiment. The waveform A illustrates an FFT output obtained in a conventional radar apparatus. As illustrated, waveform A illustrates smearing of peaks resulting in ghost objects and hence false detection. The smearing of peaks is a result of non-linearity in a ramp segment transmitted by the conventional radar apparatus. 
     The waveform B illustrates an FFT output obtained in the radar apparatus  100 . Although the first signal  124  (or the ramp segment) transmitted by the radar apparatus  100  is non-linear, the problem of smearing of peaks in the radar apparatus  100  does not occur since the apparatus  100  employs real-time chirp linearity mitigation. The peaks obtained in the FFT output represent point objects at a defined distance from the radar apparatus  100 . 
     In the foregoing discussion, the terms “connected” means at least either a direct electrical connection between the devices connected or an indirect connection through one or more passive intermediary devices. The term “circuit” means at least either a single component or a multiplicity of passive or active components, that are connected together to provide a desired function. The term “signal” means at least one current, voltage, charge, data, or other signal. Also, the terms “connected to” or “connected with” (and the like) are intended to describe either an indirect or direct electrical connection. Thus, if a first device is coupled to a second device, that connection can be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. It is to be noted that the terms ‘object’ and ‘obstacle’ have been used interchangeably in this disclosure. 
     One having ordinary skill in the art will understand that the present disclosure, as discussed above, may be practiced with steps and/or operations in a different order, and/or with hardware elements in configurations which are different than those which are disclosed. Therefore, although the disclosure has been described based upon these preferred embodiments, it should be appreciated that certain modifications, variations, and alternative constructions are apparent and well within the spirit and scope of the disclosure. In order to determine the metes and bounds of the disclosure, therefore, reference should be made to the appended claims.