Patent Publication Number: US-2023137738-A1

Title: Ferroelectric memory structure

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 110140923, filed on Nov. 3, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to a memory structure, and particularly relates to a ferroelectric memory structure. 
     Description of Related Art 
     The ferroelectric memory is a non-volatile memory and has the advantage that the stored data will not disappear even after being powered off. In addition, compared with other non-volatile memory, the ferroelectric memory has the characteristics of high reliability and fast operation speed. However, how to make a single ferroelectric memory cell have multiple storage states without increasing the area of the ferroelectric memory cell is the goal of continuous efforts. 
     SUMMARY OF THE INVENTION 
     The invention provides a ferroelectric memory structure, which can make a single ferroelectric memory cell have multiple storage states without increasing the area of the ferroelectric memory cell. 
     The invention provides a ferroelectric memory structure, which includes a substrate, a ferroelectric capacitor structure, and a switch device. The ferroelectric capacitor structure is disposed on the substrate. The ferroelectric capacitor structure includes at least one first electrode, first dielectric layers, a second electrode, and a ferroelectric material layer. The at least one first electrode and the first dielectric layers are alternately stacked. The second electrode penetrates through the first electrode. The ferroelectric material layer is disposed between the first electrode and the second electrode. The switch device is electrically connected to the ferroelectric capacitor structure. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the ferroelectric capacitor structure may be disposed between the switch device and the substrate. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the switch device may be a transistor. The switch device may include a channel layer, a third electrode, a fourth electrode, a fifth electrode, and a second dielectric layer. The channel layer is disposed on the ferroelectric capacitor structure. The third electrode and the fourth electrode are disposed on the ferroelectric capacitor structure and located on two sides of the channel layer. The fifth electrode is disposed on the channel layer. The second dielectric layer is disposed between the fifth electrode and the channel layer. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the channel layer of the switch device may be electrically connected to the second electrode of the ferroelectric capacitor structure. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the third electrode of the switch device may be electrically connected to the second electrode of the ferroelectric capacitor structure. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the material of the channel layer may be an oxide semiconductor. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ), or copper gallium oxide (CuGaO 2 ). 
     According to an embodiment of the invention, in the ferroelectric memory structure, the material of the third electrode and the material of the fourth electrode may be an N-type oxide semiconductor or a P-type oxide semiconductor. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the N-type oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium zinc oxide (IZO), and the N-type oxide semiconductor may have an N-type dopant. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the P-type oxide semiconductor may include cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ), or copper gallium oxide (CuGaO 2 ), and the P-type oxide semiconductor may have a P-type dopant. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the switch device may be disposed between the ferroelectric capacitor structure and the substrate. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the switch device may be a transistor. The switch device may include a third electrode, a second dielectric layer, a channel layer, a fourth electrode, and a fifth electrode. The third electrode is disposed on the substrate. The second dielectric layer is disposed on the third electrode and the substrate. The channel layer is disposed on the second dielectric layer and located above the third electrode. The fourth electrode and fifth electrode are disposed on the second dielectric layer and located on two sides of the channel layer. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the channel layer of the switch device may be electrically connected to the second electrode of the ferroelectric capacitor structure. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the fourth electrode of the switch device may be electrically connected to the second electrode of the ferroelectric capacitor structure. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the fourth electrode and fifth electrode may partially cover the channel layer. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the material of the channel layer may be an oxide semiconductor. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ), or copper gallium oxide (CuGaO 2 ). 
     According to an embodiment of the invention, in the ferroelectric memory structure, the material of the fourth electrode and the fifth electrode may be an N-type oxide semiconductor or a P-type oxide semiconductor. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the N-type oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium zinc oxide (IZO), and the N-type oxide semiconductor may have an N-type dopant. 
     According to an embodiment of the invention, in the ferroelectric memory structure, the P-type oxide semiconductor may include cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ), or copper gallium oxide (CuGaO 2 ), and the P-type oxide semiconductor may have a P-type dopant. 
     Based on the above description, in the ferroelectric memory structure according to the invention, the ferroelectric capacitor structure includes at least one first electrode and the first dielectric layers alternately stacked, the second electrode penetrates through the first electrode, and the ferroelectric material layer is disposed between the first electrode and the second electrode. In addition, the first electrode can be used as a weighting state electrode. Therefore, when operating the ferroelectric memory structure, the impedance (e.g., capacitance) of the ferroelectric capacitor structure can be adjusted by applying voltage to the first electrode and the second electrode respectively. In this way, a single ferroelectric memory cell can have multiple storage states without increasing the area of the ferroelectric memory cell. 
     In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, several exemplary embodiments accompanied with figures are described in detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
         FIG.  1    is a cross-sectional view illustrating a ferroelectric memory structure according to some embodiments of the invention. 
         FIG.  2    is a schematic perspective view illustrating a ferroelectric capacitor structure in  FIG.  1   . 
         FIG.  3    is a cross-sectional view illustrating a ferroelectric memory structure according to other embodiments of the invention. 
         FIG.  4    is a cross-sectional view illustrating a ferroelectric memory structure according to other embodiments of the invention. 
         FIG.  5    is a cross-sectional view illustrating a ferroelectric memory structure according to other embodiments of the invention. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the present invention. For the sake of easy understanding, the same components in the following description will be denoted by the same reference symbols. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
       FIG.  1    is a cross-sectional view illustrating a ferroelectric memory structure according to some embodiments of the invention.  FIG.  2    is a schematic perspective view illustrating a ferroelectric capacitor structure in  FIG.  1   .  FIG.  3    is a cross-sectional view illustrating a ferroelectric memory structure according to other embodiments of the invention. 
     Referring to  FIG.  1    and  FIG.  2   , a ferroelectric memory structure  10  includes a substrate  100 , a ferroelectric capacitor structure  102 , and a switch device  104 . The substrate  100  may be a semiconductor substrate such as a silicon substrate. In the present embodiment, the ferroelectric capacitor structure  102  may be disposed between the switch device  104  and the substrate  100 , but the invention is not limited thereto. 
     The ferroelectric capacitor structure  102  is disposed on the substrate  100 . The ferroelectric capacitor structure  102  includes at least one electrode  106 , dielectric layers  108 , an electrode  110 , and a ferroelectric material layer  112 . At least one electrode  106  and the dielectric layers  108  are alternately stacked. The electrode  106  can be used as a weighting state electrode. The material of the electrode  106  is, for example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, or an alloy thereof. The material of the dielectric layer  108  is, for example, a dielectric material such as silicon oxide, silicon nitride, or hafnium nitride. In the present embodiment, the number of electrodes  106  is, for example, multiple, but the number of electrodes  106  is not limited to the number shown in the figure. As long as the number of electrodes  106  is at least one, it falls within the scope of the invention. 
     The electrode  110  penetrates through the electrode  106 . In addition, the electrode  110  may penetrate through at least a portion of the dielectric layers  108 . The electrode  110  may be used as a bulk electrode. The material of the electrode  110  is, for example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, or an alloy thereof. 
     The ferroelectric material layer  112  is disposed between the electrode  106  and the electrode  110 . The material of the ferroelectric material layer  112  may include hafnium zirconium oxide (HfZrO x , HZO), lead zirconate titanate (Pb[Zr x Ti 1-x ]O 3 , PZT), strontium titanium oxide (SrTiO 3 , STO), barium titanate (BaTiO 3 , BTO), or bismuth ferrite (BiFeO 3 , BFO). 
     Furthermore, the ferroelectric capacitor structure  102  may include at least one ferroelectric capacitor FC, wherein each of the ferroelectric capacitors FC may include one electrode  106 , the electrode  110 , and the ferroelectric material layer  112 . In the present embodiment, the ferroelectric capacitor structure  102  may include a plurality of ferroelectric capacitors FC electrically connected to each other, but the invention is not limited thereto. In some embodiments, the ferroelectric capacitors FC may share the electrode  110  and the ferroelectric material layer  112 . Moreover, the number of ferroelectric capacitors FC is not limited to the number shown in the figure. As long as the number of ferroelectric capacitors FC is at least one, it falls within the scope of the invention. 
     The switch device  104  is electrically connected to the ferroelectric capacitor structure  102 . In the present embodiment, the switch device  104  may be disposed on the ferroelectric capacitor structure  102 . In the present embodiment, the switch device  104  may be a transistor, but the invention is not limited thereto. The switch device  104  may include a channel layer  114 , an electrode  116 , an electrode  118 , an electrode  120 , and a dielectric layer  122 . The channel layer  114  is disposed on the ferroelectric capacitor structure  102 . The material of the channel layer  114  may be an oxide semiconductor. In some embodiments, the oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ), or copper gallium oxide (CuGaO 2 ). 
     The electrode  116  and the electrode  118  are disposed on the ferroelectric capacitor structure  102  and located on two sides of the channel layer  114 . The electrode  116  and the electrode  118  may be used as one and the other of the source and the drain, respectively. In the present embodiment, the electrode  116  may be used as a source, and the electrode  118  may be used as a drain. The material of electrode  116  and the material of electrode  118  may be an N-type oxide semiconductor or a P-type oxide semiconductor. In some embodiments, the N-type oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium zinc oxide (IZO), and the N-type oxide semiconductor may have an N-type dopant. In some embodiments, the P-type oxide semiconductor may include cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ), or copper gallium oxide (CuGaO 2 ), and the P-type oxide semiconductor may have a P-type dopant. 
     The electrode  120  is provided on the channel layer  114 . The electrode  120  may be used as a gate. The material of the electrode  120  is, for example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, or an alloy thereof. 
     The dielectric layer  122  is disposed between the electrode  120  and the channel layer  114 . In some embodiments, the dielectric layer  122  may be further disposed between the electrode  120  and the electrode  116  and between the electrode  120  and the electrode  118 . The dielectric layer  122  may be used as a gate dielectric layer. The material of the dielectric layer  122  is, for example, a dielectric material such as silicon oxide, silicon nitride, or hafnium nitride. 
     In the present embodiment, as shown in  FIG.  1   , the channel layer  114  of the switch device  104  may be electrically connected to the electrode  110  of the ferroelectric capacitor structure  102 , so that the switch device  104  may be electrically connected to the ferroelectric capacitor structure  102 , but the invention is not limited thereto. In other embodiments, as shown in  FIG.  3   , the electrode  116  of the switch device  104  may be electrically connected to the electrode  110  of the ferroelectric capacitor structure  102 , so that the switch device  104  may be electrically connected to the ferroelectric capacitor structure  102 . 
     In addition, the ferroelectric memory structure  10  may further include other required dielectric layers (for isolation) and/or other required interconnect structures (for electrical connection), and the description thereof is omitted here. 
     Hereinafter, Table 1 is used to illustrate various storage states of the ferroelectric memory cell MC of the ferroelectric memory structure  10 . The ferroelectric memory cell MC of the ferroelectric memory structure  10  may include the ferroelectric capacitor structure  102  and the switch device  104  electrically connected to each other. By controlling the voltages applied to the electrode  106  and the electrode  110 , the ferroelectric capacitor FC may have a polarization state of “positive (+) direction” or a polarization state of “negative (-) direction”. When the ferroelectric capacitor FC has the polarization state of “positive (+) direction”, the ferroelectric capacitor FC may have a low impedance (e.g., low capacitance C L ). When the ferroelectric capacitor FC has the polarization state of “negative (-) direction”, the ferroelectric capacitor FC may have a high impedance (e.g., high capacitance C H ). Therefore, the impedance (e.g., capacitance) of each of the ferroelectric capacitors FC can be adjusted by the voltages applied to the electrode  106  and the electrode  110 . In this way, when operating the ferroelectric memory cell MC, the electrode  106  can be used as a weighting state electrode, and the impedance (e.g., capacitance) of the ferroelectric capacitor structure  102  can be adjusted by applying voltage to the electrode  106  and the electrode  110  respectively, so that a single ferroelectric memory cell MC can have multiple storage states. In the present embodiment, the impedance is, for example, a capacitance, but the invention is not limited thereto. 
     For example, the ferroelectric capacitor structure  102  may include n electrodes  106 , and “n” may be an integer greater than or equal to 1. As shown in Table 1, in the case where the ferroelectric capacitor structure  102  includes n electrodes  106  (e.g., weighting state electrodes WE1~WEn in Table 1), the ferroelectric capacitor structure  102  may include n ferroelectric capacitors FC electrically connected to each other. Therefore, the ferroelectric memory cell MC of the ferroelectric memory structure  10  may have n+1 storage states (i.e., “storage states 0~n” in Table 1).  
     
       
         
          TABLE 1
           
               
               
               
               
               
             
               
                 weighting state electrode 
                 WE1 
                 WE2 
                 WE3 
                 ... WEn 
               
             
            
               
                 storage state 0: nC L 
 
                 C L 
 
                 C L 
 
                 C L 
 
                 ...C L 
 
               
               
                 storage state 1: 1C H  + (n-1)C L 
 
                 C H 
 
                 C L 
 
                 C L 
 
                 ...C L 
 
               
               
                 storage state 2: 2C H  + (n-2)C L 
 
                 C H 
 
                 C H 
 
                 C L 
 
                 ...C L 
 
               
               
                 storage state 3: 3C H  + (n-3)C L 
 
                 C H 
 
                 C H 
 
                 C H 
 
                 ...C L 
 
               
               
                 ⋮ 
                 ⋮ 
                 ⋮ 
                 ⋮ 
                 ⋮ 
               
               
                 storage state n: nC H 
 
                 C H 
 
                 C H 
 
                 C H 
 
                 ...C H 
 
               
            
           
         
       
     
     Based on the above embodiment, in the ferroelectric memory structure  10 , the ferroelectric capacitor structure  102  includes at least one electrode  106  and the dielectric layers  108  alternately stacked, the electrode  110  penetrates through the electrode  106 , and the ferroelectric material layer  112  is disposed between the electrode  106  and the electrode  110 . In addition, the electrode  106  can be used as a weighting state electrode. Therefore, when operating the ferroelectric memory structure  10 , the impedance (e.g., capacitance) of the ferroelectric capacitor structure  102  can be adjusted by applying voltage to the electrode  106  and the electrode  110  respectively. In this way, a single ferroelectric memory cell MC can have multiple storage states without increasing the area of the ferroelectric memory cell MC. 
       FIG.  4    is a cross-sectional view illustrating a ferroelectric memory structure according to other embodiments of the invention.  FIG.  5    is a cross-sectional view illustrating a ferroelectric memory structure according to other embodiments of the invention. 
     Referring to  FIG.  1    and  FIG.  4   , the difference between the ferroelectric memory structure  20  of  FIG.  4    and the ferroelectric memory structure  10  of  FIG.  1    is as follows. In the ferroelectric memory structure  20  of  FIG.  4   , the switch device  204  may be disposed between the ferroelectric capacitor structure  102  and the substrate  100 . In the present embodiment, the switch device  204  may be disposed on the substrate  100 , and the ferroelectric capacitor structure  102  may be disposed on the switch device  204 . 
     The switch device  204  is electrically connected to the ferroelectric capacitor structure  102 . In the present embodiment, the switch device  204  may be a transistor. The switch device  204  may include an electrode  220 , a dielectric layer  222 , a channel layer  214 , an electrode  216 , and an electrode  218 . The electrode  220  is disposed on the substrate  100 . The electrode  220  may be used as a gate. The material of the electrode  220  is, for example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, or an alloy thereof. 
     The dielectric layer  222  is disposed on the electrode  220  and the substrate  100 . The dielectric layer  222  may be used as a gate dielectric layer. The material of the dielectric layer  222  is, for example, a dielectric material such as silicon oxide, silicon nitride, or hafnium nitride. 
     The channel layer  214  is disposed on the dielectric layer  222  and located above the electrode  220 . The material of the channel layer  214  may be an oxide semiconductor. In some embodiments, the oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ), or copper gallium oxide (CuGaO 2 ). 
     The electrode  216  and the electrode  218  are disposed on the dielectric layer  222  and located on two sides of the channel layer  214 . In some embodiments, the electrode  216  and the electrode  218  may partially cover the channel layer  214 . The electrode  216  and the electrode  218  may be used as one and the other of the source and the drain, respectively. In the present embodiment, the electrode  216  may be used as a source, and the electrode  218  may be used as a drain. The material of electrode  216  and the material of electrode  218  may be an N-type oxide semiconductor or a P-type oxide semiconductor. In some embodiments, the N-type oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium zinc oxide (IZO), and the N-type oxide semiconductor may have an N-type dopant. In some embodiments, the P-type oxide semiconductor may include cobalt oxide (CoO x ), nickel oxide (NiO x ), strontium copper oxide (SrCu 2 O x ), copper aluminum oxide (CuAlO 2 ), copper indium oxide (CuInO 2 ), or copper gallium oxide (CuGaO 2 ), and the P-type oxide semiconductor may have a P-type dopant. 
     In the present embodiment, as shown in  FIG.  4   , the channel layer  214  of the switch device  204  may be electrically connected to the electrode  110  of the ferroelectric capacitor structure  102 , so that the switch device  204  may be electrically connected to the ferroelectric capacitor structure  102 , but the invention is not limited thereto. For example, as shown in  FIG.  4   , the electrode  110  may penetrate through the electrode  106  and the dielectric layer  108  to be electrically connected to the channel layer  214 . In other embodiments, as shown in  FIG.  5   , the electrode  216  of the switch device  204  may be electrically connected to the electrode  110  of the ferroelectric capacitor structure  102 , so that the switch device  204  may be electrically connected to the ferroelectric capacitor structure  102 . For example, as shown in  FIG.  5   , the electrode  110   may penetrate through the electrode  106  and the dielectric layer  108  to be electrically connected to the electrode  216 . 
     In addition, the same or similar components in the ferroelectric memory structure  20  and the ferroelectric memory structure  10  are represented by the same or similar symbols, and the same or similar content (e.g., operation method) in the ferroelectric memory structure  20  and the ferroelectric memory structure  10  can be referred to the description of the ferroelectric memory structure  10  in the above-mentioned embodiment, which will not be described here. Furthermore, the ferroelectric memory structure  20  may further include other required dielectric layers (for isolation) and/or other required interconnect structures (for electrical connection), and the description thereof is omitted here. 
     Based on the above embodiment, in the ferroelectric memory structure  20 , the ferroelectric capacitor structure  102  includes at least one electrode  106  and the dielectric layers  108  alternately stacked, the electrode  110  penetrates through the electrode  106 , and the ferroelectric material layer  112  is disposed between the electrode  106  and the electrode  110 . In addition, the electrode  106  can be used as a weighting state electrode. Therefore, when operating the ferroelectric memory structure  20 , the impedance (e.g., capacitance) of the ferroelectric capacitor structure  102  can be adjusted by applying voltage to the electrode  106  and the electrode  110  respectively. In this way, a single ferroelectric memory cell MC can have multiple storage states without increasing the area of the ferroelectric memory cell MC. 
     In summary, in the ferroelectric memory structure of the aforementioned embodiments, the ferroelectric capacitor structure includes at least one weighting state electrode and the dielectric layers alternately stacked, and the weighting state electrode can be used to adjust the impedance (e.g., capacitance) of the ferroelectric capacitor structure. Therefore, a single ferroelectric memory cell can have multiple storage states without increasing the area of the ferroelectric memory cell. 
     Although the invention has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the invention. Accordingly, the scope of the invention is defined by the attached claims not by the above detailed descriptions.