Patent Publication Number: US-9405275-B2

Title: Time-to-digital converter and related method

Description:
PRIORITY CLAIM 
     This application claims the benefit to and is a continuation of U.S. patent application Ser. No. 13/973,504, filed on Aug. 22, 2013 and entitled “Time-to-Digital Converter and Related Method,” which application is incorporated herein by reference. 
    
    
     BACKGROUND 
     The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node (e.g., shrinking the process node towards the sub-20 nm node). 
     A shift to all-digital phase-locked loops (ADPLLs) has accompanied the shrinking of the semiconductor process node. The ADPLL replaces analog components of analog PLLs with digital components, and in some cases, adopts a different architecture completely. One component common to many ADPLL architectures is a time-to-digital converter, or TDC. The TDC converts time information to a coded digital signal. In general, doubling TDC resolution can improve phase noise of the ADPLL by 6 dbC/Hz. Improved resolution also increases jitter measurement circuit accuracy. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a diagram showing a TDC circuit in accordance with various embodiments of the present disclosure; 
         FIG. 2  is a diagram showing a phase interpolator in accordance with various embodiments of the present disclosure; 
         FIG. 3  is a waveform diagram showing operation of the phase interpolator in accordance with various embodiments of the present disclosure; 
         FIG. 4  is a diagram showing a TDC circuit in accordance with various embodiments of the present disclosure; 
         FIG. 5  is a flowchart of a method for digitizing time delay between two signals; 
         FIGS. 6-8  are exemplary waveform diagrams of signals of a delay line; and 
         FIG. 9  is a diagram of a TDC circuit in accordance with various embodiments of the present disclosure;  FIG. 9A  is an alternate embodiment to that shown in  FIG. 9 , and  FIG. 9B  is another alternate embodiment to that shown in  FIG. 9 . 
     
    
    
     DETAILED DESCRIPTION 
     The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments. 
     Embodiments will be described with respect to a specific context, namely time-to-digital converter (TDC) circuits and related methods. Other embodiments may also be applied, however, to other types of converter and/or delay line circuits. 
     Throughout the various figures and discussion, like reference numbers refer to like objects or components. Also, although singular components may be depicted throughout some of the figures, this is for simplicity of illustration and ease of discussion. A person having ordinary skill in the art will readily appreciate that such discussion and depiction can be and usually is applicable for many components within a structure. 
     In the following disclosure, a novel TDC circuit and method are introduced. The TDC circuit uses a phase interpolator to increase resolution of the TDC circuit beyond one inverter delay. 
       FIG. 1  is a diagram showing a TDC circuit  10  in accordance with various embodiments of the present disclosure. The TDC circuit  10  includes at least a delay line  100 , a first readout circuit  110 , a second readout circuit  120 , and a phase interpolator  130 . The delay line  100  receives an input signal S 0  at a node  151 , and outputs output signals S 1 , S 2 , . . . , SN-1, SN. The first readout circuit  110  latches the output signals S 1 , S 2 , . . . , SN-1, SN synchronously based on a first clock CK 1  at a node  155 . In some embodiments, the first clock CK 1  is a periodic electrical signal having a first frequency. 
     The phase interpolator  130  generates a second clock CK 2  at a node  156  based on the first clock CK 1  and an interpolator clock CKX. The second readout circuit  120  latches the output signals S 1 , S 2 , . . . , SN-1, SN synchronously between the first clock CK 1  and the interpolator clock CKX based on the second clock CK 2 . In some embodiments, the first, second, and interpolator clocks CK 1 -CK 2 , CKX are electrical signals having alternating high and low periods occurring at first, second, and third ratios (duty cycles) and at first, second, and third frequencies, respectively. In some embodiments, the first, second and third frequencies are the same, and the first, second and third ratios are the same. 
     A first inverter  101  of the delay line  100  has an input terminal electrically connected to the node  151 , and an output terminal electrically connected to a node  152 . The first inverter  101  inverts the input signal S 0  to generate a first signal S 1  having opposite logical level of the input signal S 0 . For example, when the input signal S 0  is logic low, the first signal S 1  is logic high. 
     A second inverter  102  of the delay line  100  has an input terminal electrically connected to the node  152 , and an output terminal electrically connected to a node  153 . The second inverter  102  inverts the first signal S 1  to generate a second signal S 2  having opposite logical level of the first signal S 1 . For example, when the first signal S 1  is logic high, the second signal S 2  is logic low. 
     A third inverter  103  of the delay line  100  has an input terminal electrically connected to the node  153 . The third inverter  103  inverts the second signal S 2  to generate a third signal S 3  having opposite logical level of the second signal S 2 . For example, when the second signal S 1  is logic low, the third signal S 3  is logic high. 
     An Nth inverter  104  of the delay line  100  has an input terminal electrically connected to a node  154 . The Nth inverter  104  inverts (N-1)th signal SN-1 to generate an Nth signal SN having opposite logical level of the (N-1)th signal SN-1. For example, when the (N-1)th SN-1 is logic high, the Nth signal SN is logic low. Number N of the first through Nth inverters  101 ,  102 ,  103 , . . . ,  104  may be designed to achieve an acceptable tradeoff between resolution, area, power consumption, and other desirable circuit performance parameters. Although shown having more than four inverters, embodiments in which the delay line  100  includes fewer than four inverters (e.g., three or two inverters) are also contemplated herein. 
     A first flip-flop  111  of the first readout circuit  110  is a D-type flip-flop, and has an input terminal (D), a non-inverting output terminal (Q), and a clock (or, “enable”) terminal (CK). The input terminal of the first flip-flop  111  is electrically connected to the node  151 . The clock terminal of the first flip-flop  111  is electrically connected to the node  155 . A first output signal S 11  generated by the first flip-flop  111  is read out from the non-inverting output terminal. In some embodiments, the output is read out from the inverting output terminal. In some embodiments, the first flip-flop  111  captures logical level (e.g., “high” or “low”) of the input signal S 0  at edges (e.g., rising edges) of the first clock CK 1 . 
     A second flip-flop  112  of the first readout circuit  110  is a D-type flip-flop, and has an input terminal (D), an inverting output terminal (Q), and a clock (or, “enable”) terminal (CK). The input terminal of the second flip-flop  112  is electrically connected to the node  152 . The clock terminal of the second flip-flop  112  is electrically connected to the node  155 . A second output signal S 12  generated by the second flip-flop  112  is read out from the inverting output terminal. In some embodiments, the output is read out from the non-inverting output terminal. In some embodiments, the second flip-flop  112  captures logical level (e.g., “high” or “low”) of the first signal S 1  at edges (e.g., rising edges) of the first clock CK 1 . 
     A third flip-flop  113  of the first readout circuit  110  is a D-type flip-flop, and has an input terminal (D), a non-inverting output terminal (Q), and a clock (or, “enable”) terminal (CK). The input terminal of the third flip-flop  113  is electrically connected to the node  153 . The clock terminal of the third flip-flop  113  is electrically connected to the node  155 . A third output signal S 13  generated by the third flip-flop  113  is read out from the non-inverting output terminal. In some embodiments, the output is read out from the inverting output terminal. In some embodiments, the third flip-flop  113  captures logical level (e.g., “high” or “low”) of the second signal S 2  at edges (e.g., rising edges) of the first clock CK 1 . 
     An Nth flip-flop  114  of the first readout circuit  110  is a D-type flip-flop, and has an input terminal (D), a non-inverting output terminal (Q), and a clock (or, “enable”) terminal (CK). The input terminal of the Nth flip-flop  114  is electrically connected to the node  154 . The clock terminal of the second flip-flop  114  is electrically connected to the node  155 . An Nth output signal SN generated by the Nth flip-flop  114  is read out from the non-inverting output terminal. In some embodiments, the output is read out from the inverting output terminal. In some embodiments, the second flip-flop  114  captures logical level (e.g., “high” or “low”) of the (N-1)th signal SN-1 at edges (e.g., rising edges) of the first clock CK 1 . Number N of the first through Nth flip-flops  111 ,  112 ,  113 , . . . ,  114  may be the same as the number N of the first through Nth inverters  101 ,  102 ,  103 , . . . ,  104 . Although shown having more than four flip-flops, embodiments in which the first readout circuit  110  includes fewer than four flip-flops (e.g., three or two flip-flops) are also contemplated herein. 
     A first flip-flop  121  of the second readout circuit  120  is a D-type flip-flop, and has an input terminal (D), a non-inverting output terminal (Q), and a clock (or, “enable”) terminal (CK). The input terminal of the first flip-flop  121  is electrically connected to the node  151 . The clock terminal of the first flip-flop  121  is electrically connected to the node  156 . A first delayed output signal S 21  generated by the first flip-flop  121  is read out from the non-inverting output terminal. In some embodiments, the output is read out from the inverting output terminal. In some embodiments, the first flip-flop  121  captures logical level (e.g., “high” or “low”) of the input signal S 0  at edges (e.g., rising edges) of the second clock CK 2 . 
     A second flip-flop  122  of the second readout circuit  120  is a D-type flip-flop, and has an input terminal (D), an inverting output terminal ( Q ), and a clock (or, “enable”) terminal (CK). The input terminal of the second flip-flop  122  is electrically connected to the node  152 . The clock terminal of the second flip-flop  122  is electrically connected to the node  156 . A second delayed output signal S 22  generated by the second flip-flop  122  is read out from the inverting output terminal. In some embodiments, the output is read out from the non-inverting output terminal. In some embodiments, the second flip-flop  122  captures logical level (e.g., “high” or “low”) of the first signal S 1  at edges (e.g., rising edges) of the second clock CK 2 . 
     A third flip-flop  123  of the second readout circuit  120  is a D-type flip-flop, and has an input terminal (D), a non-inverting output terminal (Q), and a clock (or, “enable”) terminal (CK). The input terminal of the third flip-flop  123  is electrically connected to the node  153 . The clock terminal of the third flip-flop  123  is electrically connected to the node  156 . A third output signal S 23  generated by the third flip-flop  123  is read out from the non-inverting output terminal. In some embodiments, the output is read out from the inverting output terminal. In some embodiments, the third flip-flop  123  captures logical level (e.g., “high” or “low”) of the second signal S 2  at edges (e.g., rising edges) of the second clock CK 2 . 
     An Nth flip-flop  124  of the second readout circuit  120  is a D-type flip-flop, and has an input terminal (D), a non-inverting output terminal (Q), and a clock (or, “enable”) terminal (CK). The input terminal of the Nth flip-flop  124  is electrically connected to the node  154 . The clock terminal of the second flip-flop  124  is electrically connected to the node  156 . An Nth output signal S 2 N generated by the Nth flip-flop  124  is read out from the non-inverting output terminal. In some embodiments, the output is read out from the inverting output terminal. In some embodiments, the second flip-flop  124  captures logical level (e.g., “high” or “low”) of the (N-1)th signal SN-1 at edges (e.g., rising edges) of the second clock CK 2 . Number N of the first through Nth flip-flops  121 ,  122 ,  123 , . . . ,  124  may be the same as the number N of the first through Nth inverters  101 ,  102 ,  103 , . . . ,  104 . Although shown having more than four flip-flops, embodiments in which the second readout circuit  120  includes fewer than four flip-flops (e.g., three or two flip-flops) are also contemplated herein. 
       FIG. 2  is a diagram showing the phase interpolator  130  in accordance with various embodiments of the present disclosure.  FIG. 3  is a waveform diagram showing operation of the phase interpolator  130  in accordance with various embodiments of the present disclosure. The phase interpolator  130  is configured to generate the second clock CK 2  having edges between consecutive edges of the first clock CK 1  and the interpolator clock CKX. Shown in  FIG. 3 , a third rising edge  303  of the interpolator clock CK 2  is after a first rising edge  301  of the first clock CK 1 , and before a second rising edge  302  of the interpolator clock CKX. In some embodiments, time Δt 1  between the first rising edge  301  and the third rising edge  303  is approximately equal to time Δt 2  between the second rising edge  302  and the third rising edge  303 . In some embodiments, the times Δt 1 , Δt 2  are each substantially 50% of the time between the first rising edge  301  and the second rising edge  302 . 
     Referring again to  FIG. 2 , a first inverter of the phase interpolator  130  includes a P-type transistor  131  and an N-type transistor  133 . Gate electrodes of the P-type transistor  131  and the N-type transistor  133  are electrically connected to a node  135 . Drain electrodes of the P-type transistor  131  and the N-type transistor  133  are electrically connected to a node  136 . A second inverter of the phase interpolator  130  includes a P-type transistor  132  and an N-type transistor  134 . Gate electrodes of the P-type transistor  132  and the N-type transistor  134  are electrically connected to the node  155 . Drain electrodes of the P-type transistor  132  and the N-type transistor  134  are electrically connected to the node  136 . A third inverter  137  has an input terminal electrically connected to the node  136 , and an output terminal electrically connected to the node  156 . 
     The first clock CK 1  is applied to the gate electrodes of the P-type transistor  131  and the N-type transistor  133  at the node  135 . The interpolator clock CKX is applied to the gate electrodes of the P-type transistor  132  and the N-type transistor  134  at the node  155 . The phase interpolator  130  outputs the second clock CK 2  at the node  156 . 
     Prior to the first rising edge  301 , first voltage level of the first clock CK 1  is low (e.g., 0 Volts), and second voltage level of the interpolator clock CKX is low (e.g., 0 Volts). The first voltage level being low turns off the N-type transistor  133 , and turns on the P-type transistor  131 . The second voltage level being low turns off the N-type transistor  134 , and turns on the P-type transistor  132 . With the P-type transistors  131 ,  132  turned on, voltage at the node  136  is pulled high, and voltage at the node  156  is pulled low by the third inverter  137 . 
     During and after the first rising edge  301 , the N-type transistor  133  is turned on, and the P-type transistor  131  is turned off. The voltage at the node  136  transitions from high to low at a speed determined at least by sizes (e.g., width/length ratios) of the P-type transistor  132  and the N-type transistor  133 . The third inverter  137  inverts the transition from high to low at the node  136  to the third rising edge  303  at the node  156 . 
     After the second rising edge  302 , the N-type transistors  133 ,  134  are turned on, and the P-type transistors  131 ,  132  are turned off. The voltage at the node  136  is pulled completely low (e.g., to ground) by the N-type transistors  133 ,  134 , and the voltage at the node  156  is pulled completely high (e.g., to an upper power supply voltage VDD) by the third inverter  137 . 
     The architecture shown in  FIG. 2  is only one type of phase interpolator. Embodiments using other architectures for the phase interpolator  130  are also contemplated herein. 
       FIG. 4  is a diagram showing a TDC circuit  40  in accordance with various embodiments of the present disclosure. The TDC circuit  40  is similar in some respects to the TDC circuit  20  of  FIG. 2 , with like reference numerals representing similar components. The TDC circuit  20  includes M readout circuits  110 ,  120 , . . . ,  410 . The first readout circuit  110  is clocked by the first clock CK 1 . The second readout circuit  120  is clocked by the second clock CK 2 . The Mth readout circuit  410  is clocked by an Mth clock CKM. The first to Mth clocks CK 1 , CK 2 , . . . , CKM have different phases. For example, for M=4, phases of the first to fourth clocks CK 1 , CK 2 , . . . , CK 4  may be substantially 0%, 25%, 50%, and 75%, respectively. For M=3, phases of the first to third clocks CK 1 , CK 2 , CK 3  may be substantially 0, T/3, and 2T/3, where T is delay between the first rising edge  301  and the second rising edge  302 . Increasing M increases resolution of the TDC circuit  40 . The Mth readout circuit  410  outputs N readout signals SM 1 , SM 2 , . . . , SMN. 
     In some embodiments, the Mth clock CKM is generated by an (M-1)th phase interpolator  430  similar to the phase interpolator  130 . Taking the architecture shown in  FIG. 2  as an example for illustration, P-type transistors of the (M-1)th phase interpolator  430  may have different size than the P-type transistors  131 ,  132  of the phase interpolator  130 . In some embodiments, N-type transistors of the (M-1)th phase interpolator  430  have different size than the N-type transistors  133 ,  134  of the phase interpolator  130 . This allows the (M-1)th phase interpolator  430  to generate the Mth clock CKM with different phase than the second clock CK 2 . 
       FIG. 5  is a flowchart of a method  50  for digitizing time delay between two signals. In some embodiments, the method  50  is performed by the TDC circuit  10  of  FIG. 1  or the TDC circuit  40  of  FIG. 4 . A signal, such as the signal S 0 , is received  500  by a delay line, such as the delay line  100 . In some embodiments, the signal is a clock. In some embodiments, the signal is generated based on a clock. The delay line outputs signals, such as the output signals S 1 -SN. In some embodiments, the output signals S 1 -SN correspond to number of inverter delays of the delay line. For example, the output signal S 3  may correspond to three inverter delays, and the output signal S 7  may correspond to seven inverter delays. The output signals are received  510  by a first readout circuit (e.g., the first readout circuit  110 ) clocked by a first clock (e.g., the first clock CK 1 ). The first readout circuit receives the first clock, and captures the output signals on an edge (e.g., a rising edge) of the first clock. The output signals are received  520  by a second readout circuit (e.g., the second readout circuit  120 ) clocked by a second clock (e.g., the second clock CK 2 ). In some embodiments, the second clock differs in phase from the first clock by less than one inverter delay. In some embodiments, further readout circuits clocked by further clocks (such as in the TDC circuit  40 ) receive the output signals. In some embodiments, the second clock is generated by a phase interpolator based on the first clock and an interpolator clock. Readout signals of the first and second readout circuits (e.g., the output signals S 11 -S 1 N, S 21 -S 2 N) are decoded  530  to determine time information of the signal. In some embodiments, the time information is the time delay between the signal and a reference clock. 
       FIGS. 6-8  are exemplary waveform diagrams of the signals S 0 -S 6  of the delay line  100 . Odd signals (e.g., S 1 , S 3 , S 5 ) of the signals S 0 -S 6  are shown barred as an aid to the reader. In the examples shown in  FIGS. 6-8 , the inverters  101 ,  102 ,  103 , . . . ,  104  of the delay line  100  number six.  FIGS. 6 and 7  are examples of waveforms of the TDC circuit  10  of  FIG. 1 .  FIG. 8  is an example of the TDC circuit  40  of  FIG. 4  for four readout circuits and four clocks CK 1 -CK 4 . Referring to  FIG. 6 , at the rising edge of the first clock CK 1  (shown by an arrow and dotted line), the input signal S 0  and the first signal S 1  are at high voltage, whereas the second through sixth signals S 2 -S 6  are at low voltage ([S 10 :S 16 ]=“0000011”). At the rising edge of the second clock CK 2  (shown by an arrow and a solid line), the input signal S 0  and the first signal S 1  are at high voltage, whereas the second through sixth signals S 2 -S 6  are at low voltage ([S 20 :S 26 ]=“0000011”). Using the method  50 , the output signals S 10 -S 16 , S 20 -S 26  are decoded to form a decoder signal having value “00000000001111”. The decoder signal has double the resolution of the output signals S 10 -S 16  read out by the first readout circuit  110  due to insertion of the output signals S 20 -S 26  read out by the second readout circuit  120 . 
     In another example shown in  FIG. 7 , at the rising edge of the first clock CK 1  (shown by an arrow and dotted line), the input signal S 0  is at high voltage, whereas the first through sixth signals S 1 -S 6  are at low voltage ([S 10 :S 16 ]=“0000001”). At the rising edge of the second clock CK 2  (shown by an arrow and a solid line), the input signal S 0  and the first signal S 1  are at high voltage, whereas the second through sixth signals S 2 -S 6  are at low voltage ([S 20 :S 26 ]=“0000011”). Using the method  50 , the output signals S 10 -S 16 , S 20 -S 26  are decoded to form a decoder signal having value “00000000000111”. The decoder signal has double the resolution of the output signals S 10 -S 16  read out by the first readout circuit  110  due to insertion of the output signals S 20 -S 26  read out by the second readout circuit  120 . 
     In some embodiments, the insertion is performed by alternating first digits of the output signals S 10 -S 16  with second digits of the output signals S 20 -S 26 . For example, the decoder signal may be generated as a string of digits ordered as: [S 10 , S 20 , S 11 , S 21 , S 12 , S 22 , . . . , S 16 , S 26 ], where each first digit is followed by the corresponding second digit. 
     In the example shown in  FIG. 8  four readout circuits and four clocks CK 1 -CK 4  are used to perform the method  50 . At the rising edge of the first clock CK 1 , the input signal S 0  is at high voltage, whereas the first through sixth signals S 1 -S 6  are at low voltage ([S 10 :S 16 ]=“0000001”). At the rising edge of the second clock CK 2 , the input signal S 0  and the first signal S 1  are at high voltage, whereas the second through sixth signals S 2 -S 6  are at low voltage ([S 20 :S 26 ]=“0000011”). At the rising edge of the third clock CK 3 , the input signal S 0  and the first signal S 1  are at high voltage, whereas the second through sixth signals S 1 -S 6  are at low voltage ([S 30 :S 36 ]=“0000011”). At the rising edge of the fourth clock CK 4 , the input signal S 0  and the first signal S 1  are at high voltage, whereas the second through sixth signals S 2 -S 6  are at low voltage ([S 40 :S 46 ]=“0000011”). Using the method  50 , the output signals S 10 -S 16 , S 20 -S 26  are decoded to form a decoder signal having value “0000 . . . 000001111111” and width of 28 digits (bits). The decoder signal has quadruple the resolution of the output signals S 10 -S 16  read out by the first readout circuit  110  due to insertion of the output signals S 20 -S 26  read out by the second readout circuit  120 , the output signals S 30 -S 36  read out by the third readout circuit, and the output signals S 40 -S 46  read out by the fourth readout circuit. 
       FIG. 9  is a diagram of a TDC circuit  90  in accordance with various embodiments of the present disclosure. In some embodiments, the TDC circuit  90  is used with a clock and data recovery (CDR) circuit or a delay-locked loop (DLL) circuit. The TDC circuit  90  shares many features of the TDC circuit  10  of  FIG. 1 , with like reference numerals referring to like components. In some embodiments, only one readout circuit (the first readout circuit  110 ) is included in the TDC circuit  90 . A multiplexer  900  is also included in the TDC circuit  90 . The multiplexer  900  is controlled by a selection signal that has two phases Φ 1 , Φ 2 . In the first phase Φ 1 , the first clock CK 1  is outputted from the multiplexer  900  to the clock terminals of the first to Nth flip-flops  111 - 114  of the first readout circuit  110 . In the second phase Φ 2 , the second clock CK 2 , which is generated by the phase interpolator  130  based on the first clock CK 1  and the interpolator clock CKX, is outputted from the multiplexer  900  to the clock terminals. As a result, odd bits of the decoder signal are generated in the first phase Φ 1  at a rising edge of the first clock CK 1 , and even bits of the decoder signal are generated in the second phase Φ 2  at a subsequent rising edge of the second clock CK 2  interpolated off of a subsequent rising edge of the first clock CK 1 . The TDC circuit  90  saves area relative to the TDC circuits  10 ,  40 , but requires at least two clock periods of the first clock CK 1  to generate the decoder signal. In some embodiments, further clocks, such as the third through Nth clocks CK 3 -CKN, are inputted to the multiplexer  900 , and the multiplexer  900  selects the first through Nth clocks CK 1 -CKN sequentially to generate the decoder signal over N clock periods of the first clock CK 1 . In such embodiments, the TDC circuit  90  includes further phase interpolators electrically connected to input terminals of the multiplexer  900 , as illustrated by  FIG. 9A . 
     In some embodiments, the second readout circuit  120  is included in the TDC circuit  90 , and a further multiplexer is electrically connected to the clock terminals of the first through Nth flip-flops  121 - 124  of the second readout circuit  120 , as shown in  FIG. 9B . The first through Nth clocks CK 1 -CKN are split evenly as inputs to the multiplexer  900  and the further multiplexer. For example, the first and second clocks CK 1 , CK 2  are inputted to the multiplexer  900 , and the third and fourth clocks CK 3 , CK 4  are inputted to the further multiplexer. In the first phase Φ 1 , the first clock CK 1  is applied to the first readout circuit  110 , and the third clock CK 3  is applied to the second readout circuit  120 . In the second phase Φ 2 , the second clock CK 2  is applied to the first readout circuit  110 , and the fourth clock CK 4  is applied to the second readout circuit  120 . The output signals S 11 -S 1 N, S 21 -S 2 N of the first and second readout circuits  110 ,  120  are then decoded to generate the decoder signal. By extension, greater numbers of readout circuits, multiplexers, phase interpolators, and clocks can be arranged as described to generate the decoder signal having finer resolution than provided by a single inverter read by a single readout circuit. 
     Embodiments may achieve advantages. The second readout circuit  120  and phase interpolator  130  allow the TDC circuit  10  to have double the resolution of the first readout circuit  110 . The TDC circuit  40  can have triple, quadruple, or even ten times the resolution of the first readout circuit  110 . Increased resolution in the TDC circuits  10 ,  40 ,  90  improves system performance of a circuit that uses the TDC circuits  10 ,  40  or  90 , such as an ADPLL, a DLL, or a CDR circuit. Jitter measurement accuracy can also be improved. 
     In accordance with various embodiments of the present disclosure, a device includes a delay line, a first readout circuit electrically connected to the delay line, a second readout circuit electrically connected to the delay line, and a phase interpolator electrically connected to the second readout circuit. 
     In accordance with various embodiments of the present disclosure, a device includes a delay line, a readout circuit electrically connected to the delay line, a multiplexer electrically connected to the readout circuit, and a phase interpolator electrically connected to the multiplexer. 
     In accordance with various embodiments of the present disclosure, a method includes (a) receiving a signal by a delay line; (b) receiving output signals of the delay line by a first readout circuit clocked by a first clock; (c) receiving the output signals of the delay line by a second readout circuit clocked by a second clock having different phase than the first clock; and (d) decoding readout signals of the first and second readout circuits to determine time information of the signal. 
     Embodiments described herein may provide for a method that includes receiving a signal by a delay line, and receiving a first clock signal and phase interpolating therefrom a second clock signal. The method includes selecting the first clock signal or the second clock signal in response to a control signal and outputting the selected first clock signal or second clock signal to a readout circuit, and receiving output signals from the delay line using the readout circuit while clocking the readout circuit at the selected first clock signal or second clock signal. 
     In another aspect, embodiments described herein may provide for a device having a delay line having a delay line input and having a plurality of delay line outputs, each delay line output configured to output an inverted value of a previous delay line output. The device includes a readout circuit having a clock input and a plurality of signal inputs, each input corresponding to a respect delay line output, and a multiplexor coupled to the clock input of the readout circuit, the multiplexor configured to output a clock signal or a phase interpolated clock signal. 
     In yet another aspect, embodiments described herein may provide for a device a delay line configured to receive a signal. The device may further include a phase interpolator circuit configured to receive a first clock signal and an interpolator clock signal and phase interpolating therefrom a second clock signal, and a multiplexor configured to receive the first clock signal and the second clock signal and to output either the first clock signal or the second clock signal in response to a selection signal. A readout circuit is clocked by the first clock and configured to receive output signals of the delay line, and a second readout circuit is clocked by the second clock signal and configured to receive the output signals of the delay line. The device may further include a decoder configured to decode readout signals of the readout circuit and second readout circuit to determine time information of the signal. 
     As used in this application, “or” is intended to mean an inclusive “or” rather than an exclusive “or”. In addition, “a” and “an” as used in this application are generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Also, at least one of A and B and/or the like generally means A or B or both A and B. Furthermore, to the extent that “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”. Moreover, the term “between” as used in this application is generally inclusive (e.g., “between A and B” includes inner edges of A and B). 
     Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.