Patent Publication Number: US-6211699-B1

Title: High performance CML to CMOS converter

Description:
FIELD OF THE INVENTION 
     The present invention relates to integrated circuits which use both bipolar and CMOS logic levels. More particularly, the present invention relates to an improved high performance circuit for converting current mode logic (CML) voltage levels to CMOS compatible voltage levels. 
     BACKGROUND OF THE INVENTION 
     Integrated circuits which utilize differential bipolar current mode logic (CML) have different voltage ranges with respect to logic high and logic low voltage levels than CMOS technologies. Accordingly, the use of both bipolar and CMOS technologies in a single integrated circuit requires a conversion of current mode logic (CML) differential voltage levels to CMOS compatible voltage level converters or vice versa. For example, it is well known in the art that a typical CML circuit operates with a differential swing of two to three hundred millivolts. In contrast, a typical CMOS circuit operates according to a single ended voltage within a specified voltage range. For example, with a power supply voltage of 3.0 volts, a voltage of 2.5 V to 3.0 V represents a logic high voltage level and a voltage of 0 V to 0.5 V represents a logic low voltage level. As can be readily understood, the combination of CML and CMOS circuitry in a single integrated circuit requires a differential to single-ended conversion and a level conversion. 
     FIG. 1 a  illustrates the basic circuitry for a prior art CML to CMOS voltage converter. An incoming CML voltage signal is applied across terminals A and AN, with A representing the non-inverted voltage signal and AN representing the inverted voltage signal. The terminal A is coupled to the base of a first npn bipolar junction transistor QN 1 . The collector of the transistor QN 1  is coupled to a first terminal of a resistor R 10 . A second terminal of the resistor R 10  is coupled to a high voltage supply Vcc. The emitter of the transistor QN 1  is coupled to the emitter of a second npn bipolar junction transistor QN 2 . The emitters of each of the transistors QN 1  and QN 2  are coupled to a low voltage supply Vss through a first current source I S1 . Preferably, the current source I S1 , is comprised of a NMOS transistor N 100  which is driven by a biasing voltage, V BIAS , coupled to the gate of the NMOS transistor N 100 . The base of the transistor QN 2  is coupled to the terminal AN, while the collector of the transistor QN 2  is coupled to a first terminal of a resistor R 20 . A second terminal of the resistor R 20  is coupled to the high voltage supply Vcc. The base of a third npn bipolar junction transistor QN 3  is also coupled to the first terminal of the resistor R 20  and to the collector of the transistor QN 2 . The collector of the transistor QN 3  is coupled to the high voltage supply Vcc, while the emitter of the transistor QN 3  is coupled to the source of a first PMOS transistor T 10  and the source of a second PMOS transistor T 20 . The drain of the first PMOS transistor T 10  is coupled to the gate of the first PMOS transistor T 10  and the gate of a third PMOS transistor T 30 . The drain of the first PMOS transistor T 10  is further coupled to the low voltage supply Vss, through a second current source, I S2 . The second current source I 2  is comprised of an NMOS transistor N 200  which is driven by the biasing voltage, VBIAS, which is coupled to the gate of the NMOS transistor N 200 . The drain of the second PMOS transistor T 20  is coupled to an output node B. The gate of the second PMOS transistor T 20  is coupled to the gate of a fourth PMOS transistor T 40  and the drain of the fourth PMOS transistor T 40 . The drain of the fourth PMOS transistor T 40  is coupled to the low voltage supply Vss through a third current source, I S3 . The third current source I 3  is comprised of an NMOS transistor N 300  which is driven by the biasing voltage V BIAS , coupled to the gate of the NMOS transistor N 300 . The source of the fourth PMOS transistor T 40  is coupled to the emitter of a fourth npn bipolar junction transistor QN 4 . The collector of the transistor QN 4  is coupled to the high voltage supply Vcc. The base of the transistor QN 4  is coupled to the collector of the transistor QN 1  and the first terminal of the resistor R 10 . The source of the third PMOS transistor T 30  is also coupled to the emitter of the fourth bipolar junction transistor QN 4 . The drain of the third PMOS transistor T 30  is coupled to the drain and the gate of a first NMOS transistor N 10  and the gate of a second NMOS transistor N 20 . The source of the first NMOS transistor N 10  and the source of the second NMOS transistor N 20  are each coupled to the low voltage supply Vss. The drain of the second NMOS transistor N 20  is coupled to the output node B. The output node B drives a CMOS buffer V 10 . 
     The internal circuitry of the CMOS buffer V 10  is depicted in FIG. 1 b . As shown in FIG. 1 b , the CMOS buffer V 10  includes a PMOS transistor P 1  having a source connected to the high voltage supply Vcc, a gate coupled to the output node B and a drain coupled to an output node Q. The CMOS buffer V 10  further includes an NMOS transistor N 1  having a drain which is coupled to the output node Q. The gate of the NMOS transistor N 1  is coupled to the output node B and the source of the NMOS transistor N 1  is coupled to the low voltage supply Vss. 
     Referring again to FIG. 1 a , when the differential voltage signal at the terminals A and AN is configured such that A is higher than AN, the transistor QN 1  is turned on, while the transistor QN 2  is off. In this state, an output voltage level measured at the output node B is switched toward the low voltage level Vss. The output voltage at the node B falls to very nearly the level of Vss when the transistor N 20  sinks current out of the node B. As the voltage signal at the terminal A becomes inactive and the voltage signal at the terminal AN goes active, the output voltage at the output node B switches and begins to increase toward the high voltage level Vcc. However, due to the voltage drop associated with the bipolar junction transistors QN 3 , the voltage at the output node B will not reach the same voltage level as Vcc; but, rather, will actually only rise to the level of Vcc less one V BE  voltage level of the transistor QN 3  and the drain to source saturation voltage level of the transistor T 20 . Typically, this voltage may be as high as 0.8-1.0 volts, depending upon the operating conditions. Because the voltage at the output node B can fall to very nearly the level of Vss, but cannot rise to very nearly the level of Vcc, the voltage level at the output node B will not vary symmetrically with respect to the supply rails Vcc and Vss. This results in different rise and fall times for the voltage at the output Q of the CMOS buffer V 10  because the input threshold of the CMOS buffer V 10  is centered about ½Vcc. 
     Consider now the CMOS buffer of FIG. 1 b . Ideally, when the NMOS transistor N 1  is on, the PMOS transistor P 1  should be off, and the voltage at the output Q will be driven low toward Vss. Conversely, when the PMOS transistor P 1  is on, the NMOS transistor N 1  should be off, and the voltage at the output Q will be driven high toward Vss. However, if the voltage at the node B is not driven high enough, the PMOS transistor P 1  will not be completely turned off when the NMOS transistor N 1  is on. In these circumstances, current will continue to flow through P 1  to the output Q as current is drawn from the output Q through the NMOS transistor N 1 . Under these circumstances, the fall time required for the voltage level at the output Q to reach Vss will take longer than the rise time required for the voltage level at the output Q to reach Vcc. Accordingly, the voltage at the output Q will have an unsymmetrical duty cycle. 
     When such a prior art CML to CMOS converter is utilized for converting a clock signal from CML to CMOS, the converted clock signal will not have a constant duty cycle since the rise time and fall time will differ. This is undesirable in critical CMOS applications where a symmetric duty cycle is needed. 
     Additionally, it may be desirable to have both a CMOS output signal and its inverted complement, that are matched and track each other over process and temperature variations. In prior art CML to CMOS converters, the complement of the output voltage is often generated by using a CMOS inverter and simply inverting the output. One problem with such a method is the association of a delay with the inverter. In such cases, the complement will not be in synch with the uncomplemented output voltage; but, instead, will be delayed by a small fraction of time associated with the inverter. In many critical applications, such as the generation of CMOS compatible clocking signals, this delay in time is unacceptable. This problem has been overcome in the past by inverting the output voltage twice (in parallel with an inverter used for the complement) in order to obtain a new output voltage having the same frequency and period of the original output voltage. 
     FIG. 2 illustrates a prior art method for generating an inverted or complementary output signal. As shown, a CML signal is input to a CML to CMOS converter  500  at the input terminal I. A CMOS signal is output from the converter  500  at the output terminal OUT. The output terminal OUT is coupled to a first inverter X 1  and a second inverter X 2 . The output from the first inverter X 1  is input to a third inverter X 3 . The output from the second inverter X 2  is the inverted or complementary output signal NOUT, while the output from the third inverter X 3  is the original output signal. Each of the inverters X 1 , X 2 , and X 3  has an associated timing delay, with the inverter X 1  having a delay of T 1 , the inverter X 2  having a delay of T 2 , and the inverter X 3  having a delay of T 3 . As described above, in prior art configurations the inverters X 1 , X 2 , and X 3  are each chosen such that the sum of the delays for the first and third inverters T 1 +T 3  is approximately equal to the delay of the second inverter T 2 . In this way, the output signal OUT and the inverted or complementary output signal are in synch. However, such circuitry is often complicated and difficult to design and the delays may vary under differing operating conditions such that obtaining optimized synchronization is extremely difficult. Delay matching involved adjusting the geometries of CMOS gate width and length to control delay of one signal with respect to another. Process variations, such as threshold voltage over temperature, do not make this an optimized solution for critical timing applications. 
     Accordingly, what is needed is an improved design which allows the converter to reach the desired high output voltage level required for CMOS circuitry so as to maintain a relatively constant duty cycle. What is further needed is a CML to CMOS converter which can output both the CMOS signal and its inverted complement, without any delay between the two voltage signals such that both signals are in synch without the need for complicated circuitry. 
     SUMMARY OF THE INVENTION 
     The present invention is a current mode logic (CML) to CMOS converter which includes a differential bipolar CML input stage, a current source/current sink stage, and an output stage. The converter is able to convert a CML input voltage differential to a CMOS compatible voltage signal having high and low voltage levels which are symmetric with respect to supply rails. This enables the CML to CMOS converter to form an output signal having a constant duty cycle when a clock signal is applied to the converter. The bipolar input stage receives an incoming CML voltage differential signal and adjusts the relative voltage levels, increasing the high and decreasing the low voltage levels, thereby creating a greater swing between voltage levels. Utilizing the adjusted CML voltage differential signal, the current source/current sink stage drives the output stage by maintaining equal current source and current sink levels to and from the output stage, ensuring that the output voltage rises and falls symmetrically to the supply high and low voltage levels, thereby maintaining a constant duty cycle. 
     A first pair of NMOS transistors, coupled to the output stage through a set of PMOS transistors make up the current source and drive current to the output stage from a high input voltage rail whenever the input differential is logic zero or negative. A first pair of PMOS transistors, coupled to the output stage through a set of NMOS transistors make up the current sink and draw current from the input capacitance of the first output buffer/inverter stage thus driving this node to a low input voltage rail whenever the input differential voltage is positive. The transistors are arranged and biased in order to ensure that the current sink transistors are never on as current is sourced to the output stage from the high input voltage rail. Conversely, the current source transistors are never on as current is sunk from the output stage to the low input voltage rail. In addition, the current source is configured to drive a level of current that is substantially equal to a level of current that the current sink draws from the output stage. Therefore, the output signal has substantially equal rise and fall times. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 a  illustrates a schematic diagram of a prior art CML to CMOS converter. 
     FIG. 1 b  illustrates a schematic diagram of the CMOS buffer of FIG.  1 . 
     FIG. 2 illustrates a schematic diagram of a prior art circuit for generating an inverted output signal. 
     FIG. 3 illustrates a schematic diagram of a CML to CMOS converter of the present invention. 
     FIG. 4 illustrates a schematic diagram of a first alternative embodiment of a CML to CMOS converter of the present invention having a cascode current source arrangement. 
     FIG. 5 illustrates a schematic diagram of a second alternative embodiment of the CML to CMOS converter of the present invention having a complementary outputs. 
     FIG. 6 illustrates a schematic diagram of a third alternative embodiment of the CML to CMOS converter of the present invention having a level shift arrangement which includes diodes. 
     FIG. 7 shows a schematic diagram of a fourth alternative embodiment of the CML to CMOS converter of the present invention depicting an preferred biasing arrangement. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention is a current mode logic (CML) to CMOS converter which includes a differential bipolar CML input stage, a current pump (a current source/sink stage), and an output stage. The converter is able to convert a differential CML input signal to a CMOS compatible voltage signal having high and low voltage levels which are symmetric with respect to high and low voltage supply rails to enable the CML to CMOS converter to form an output signal having a constant duty cycle when the converter is driven by a constant duty cycle input signal. The bipolar input stage receives an incoming differential CML signal and steps the voltage levels up, by decreasing the low voltage levels, thereby creating a voltage signal having a greater swing between the high and low levels. Utilizing this converted voltage signal, the current source/sink stage drives the output stage by maintaining an equal current source and current sink to and from the output stage, ensuring that an internal node voltage driving the CMOS buffer output stage rises and falls symmetrically relative to the supply levels, thereby maintaining a constant duty cycle. 
     The current pump includes a current source circuit and a current sink circuit for driving current to and drawing current from the output stage, respectively. A first pair of source coupled NMOS transistors, coupled to the output stage through a set of two PMOS transistors, source current to the output stage from a high input voltage rail whenever the differential input voltage signal is negative. A first pair of source coupled PMOS transistors, coupled to the output stage through a set of two NMOS transistors, sink current from the output stage to a low input voltage rail whenever the differential input voltage signal is positive. The transistors are arranged and biased in order to ensure that the current sink transistors are never on as current is sourced to the output stage from the high input voltage rail. Conversely, the current source transistors are never on as current is sunk from the output stage to the low input voltage rail. 
     FIG. 3 illustrates a schematic diagram of a preferred embodiment of the CML to CMOS converter of the present invention. As shown, a differential CML voltage signal is applied across complementary input terminals A and AN to the converter of the present invention, where the voltage signal at the terminal A represents the positive voltage signal and the voltage signal at the terminal AN represents the complement or inverted voltage signal. The terminal A is coupled to the base of a first npn bipolar junction transistor QN 10 , while the terminal AN is coupled to the base of a second npn bipolar junction transistor QN 20 . The collector of the transistor QN 10  and the collector of the transistor QN 20  are both coupled to a high voltage supply Vcc. The emitter of the transistor QN 10  is coupled to a first terminal of a resistor R 1 . A second terminal of the resistor R 1  is coupled to the base of a third npn bipolar junction transistor QN 30 , which is part of a first differential pair of transistors, and to a low voltage supply Vss through a first current source, I 1 . The first current source I 1  preferably includes an npn bipolar junction transistor T 100  which is driven by a biasing voltage V BIAS  coupled to the base of the transistor T 100 . 
     The emitter of the transistor QN 20  is coupled to a first terminal of a resistor R 2 . A second terminal of the resistor R 2  is coupled to the base of fourth npn bipolar junction transistor QN 40 , which is also part of the first differential pair of transistors, and to the low input voltage supply Vss through a second current source, I 2 . The second current source I 2  preferably includes an npn bipolar junction transistor T 200  which is driven by the biasing voltage V BIAS  coupled to the base of the transistor T 200 . The emitters of the first differential pair of transistors QN 30  and QN 40  are coupled together and tied to the low voltage supply Vss through a third current source,  1   3 . The third current source  1   3  preferably includes an npn bipolar junction transistor T 300  which is driven by the biasing voltage V BIAS  coupled to the base of the transistor T 300 . The collectors of each transistor QN 30  and QN 40  in the first differential pair are both coupled to the high voltage supply Vcc. The collector of the transistor QN 30  is coupled to the high voltage supply Vcc through a first node C and a resistor R 3 , while the collector of the transistor QN 40  is coupled to the high voltage supply Vcc through a second node CN and a resistor R 4 . Together, the components QN 10 , QN 20 , QN 30 , QN 40 , QN 50 , QN 60 , R 1 , R 2 , R 3 , R 4 , R 5  and R 7  make up a bipolar input stage  200 . 
     In operation, when the incoming voltage signal at the terminal A is higher than the incoming voltage signal at the terminal AN, the transistors QN 10 , QN 20  and QN 30  are turned on and the transistor QN 40  is turned off. In this state, the voltage at the node C is driven low, while the voltage at the node CN is driven high. Conversely, when the incoming voltage signal at the terminal A is lower than the incoming voltage signal at the terminal AN, the transistor QN 30  is turned off and the transistors QN 10 , QN 20  and QN 40  are turned on. In this state, the voltage at the node C is driven high, while the voltage at the node CN is driven low. Accordingly, the bipolar input stage converts the differential incoming current mode signal at the terminals A and AN to a voltage signal having minimum and maximum voltages levels corresponding to the high input supply Vcc and a voltage lower than Vcc set by the current source I 3  and one of the resistors R 3  or R 4 . The transistors QN 10  and QN 20  are always biased to be turned on as these transistors only function as buffers/level shifters. 
     Referring again to FIG. 3, the base of a fifth npn bipolar junction transistor QN 50  is coupled to the node CN, while the base of a sixth npn bipolar junction transistor QN 60  is coupled to the node C. The collectors of each of the transistors QN 50  and QN 60  are coupled to the high voltage supply Vcc. The emitter of the transistor QN 50  is coupled to a first terminal of a resistor R 5 . A second terminal of the resistor R 5  is coupled to the gate of a PMOS transistor P 10 , and the first terminal of a resistor R 6 . A second terminal of the resistor R 6  is coupled to the gate of an NMOS transistor N 10  and to the low voltage supply Vss through a current source I b1 . The current source I b1  preferably includes a bipolar junction transistor T 400  which is driven by the constant voltage V BIAS  coupled to the base of the transistor T 400 . The emitter of the transistor QN 60  is coupled to a first terminal of a resistor R 7 . A second terminal of the resistor R 7  is coupled to the gate of a PMOS transistor P 20  and the first terminal of a resistor R 8 . A second terminal of the resistor R 8  is coupled to the gate of an NMOS transistor N 20  and to the low voltage supply Vss through a current source I b2  The current source I b2  preferably includes a bipolar junction transistor T 500  which is driven by the constant voltage V BIAS  coupled to the base of the transistor. 
     The source of the PMOS transistor P 10  and the source of the PMOS transistor P 20  are both coupled to the high voltage supply Vcc through a fourth current source, I 4 . The drain of the PMOS transistor P 10  is coupled to the low voltage supply Vss through a dummy load L 1 . The drain of the PMOS transistor P 20  is coupled to the drain of an NMOS transistor N 40 , the gate of the NMOS transistor N 40  and the gate of an NMOS transistor N 30 . The source of the NMOS transistor N 30  and the source of the NMOS transistor N 40  are both coupled to the low voltage supply Vss. The drain of the transistor N 30  is coupled to an output node OUT. The current from the current source I 4  either flows through the PMOS transistor P 20  and then through the NMOS transistor N 40  or through the PMOS transistor P 10  and the dummy load Li. Because the NMOS transistors N 40  and N 30  are configured as a current mirror, when the current from the current source I 4  is directed through the NMOS transistor N 40 , the NMOS transistor N 30  attempts to mirror and sink the same level of current from the output node OUT. Together, the four transistors P 10 , P 20 , N 30  and N 40  form a current sink circuit, which when activated draws current from the output node OUT, thereby decreasing a voltage level at the output node OUT. 
     The source of the NMOS transistor N 10  and the source of the NMOS transistor N 20  are both coupled together and tied to the low voltage supply Vss through a fifth current source, I 5 . The drain of the NMOS transistor N 10  is coupled to the high voltage supply Vcc through a dummy load L 2 . The drain of the NMOS transistor N 20  is coupled to the drain of a PMOS transistor P 40 , the gate of the PMOS transistor P 40 , and the gate of a PMOS transistor P 30 . The source of the PMOS transistor P 30  and the source of the PMOS transistor P 40  are both coupled to the high voltage supply Vcc. The drain of the PMOS transistor P 30  is coupled to the output node OUT. The current from the current source I 5  either flows through the NMOS transistor N 20  and the PMOS transistor P 40  or through the NMOS transistor N 10  and the dummy load L 2 . Because the PMOS transistors P 40  and P 30  are configured as a current mirror, when the current for the current source I 5  is drawn from the PMOS transistor P 40  the PMOS transistor P 30  attempts to source the same level of current to the output node OUT. Together, the four transistors N 10 , N 20 , P 30  and P 40  form a current source circuit, which when activated supplies current to the output node OUT, thereby increasing a voltage level at the output node OUT. 
     The output node OUT is coupled to a CMOS buffer  300  which includes a single PMOS transistor P 1  and a single NMOS transistor N 1 . The output node OUT is coupled to the gates of the PMOS transistor P 1  and the NMOS transistor N 1 . The source of the PMOS transistor P 1  is coupled to the high voltage supply Vcc, while the source of the NMOS transistor N 1  is coupled to the low voltage supply Vss. The drains of the PMOS transistor P 1  and the NMOS transistor N 1  are coupled together, thereby forming a buffered output node BOUT. Preferably this first input stage is designed to minimize the input capacitance seen at the node OUT by the current source and sink transistors P 30  and N 30 , respectively, This is achieved by using minimum MOS device geometries if possible. Preferably, the turn-on/turn-off or threshold voltage required to activate each of the transistors P 1  and N 1  is equal to approximately one half of the high voltage supply Vcc. It will be apparent that additional CMOS buffers used in series may be utilized to help square off transitions in the voltage level at the output node OUT. 
     In operation, when the voltage at the node C is high and the voltage at the node CN is low (as discussed earlier, this occurs when the incoming voltage signal at terminal A is low and the signal at terminal AN is high), the transistors QN 60  and QN 50  provide a voltage level shifting function through the resistors R 5  and R 6  or through the resistors R 7  and R 8  to the gates of the PMOS transistors P 10  and P 20  and the NMOS transistors N 10  and N 20 . In this state, the voltage at the gate of the PMOS transistor P 20  increases while the voltage at the gate of the PMOS transistor P 10  decreases. This turns the transistor P 20  off, and turns the transistor P 10  on. Concurrently, the voltage at the gate of the NMOS transistor N 20  increases, while the voltage at the gate of the NMOS transistor N 10  is decreased. This causes the NMOS transistor N 10  to turn off, while the NMOS transistor N 20  turns on. As the NMOS transistor N 20  draws more current down from the high voltage supply Vcc, the voltage at the gates of the PMOS transistors P 30  and P 40  begins to decrease, activating the PMOS transistors P 40  and P 30 . As the PMOS transistor P 30  is activated, current is sourced down from the high input voltage source Vcc to the output node OUT, thereby causing a voltage level measured at the output node OUT to increase in a predetermined manner. 
     Conversely, when the voltage at the node C is low and the voltage at the node CN is high (as discussed earlier, this occurs when the incoming voltage signal at the terminal A is high and the voltage signal at the terminal AN is low), the transistors QN 50  and QN 60  provide a level shifting function through the resistors R 5  and R 6  or through the resistors R 7  and R 8  to the gates of the PMOS transistors P 10  and P 20  and the NMOS transistors N 10  and N 20 . In this state, the voltage at the gate of the PMOS transistor P 10  is increased, while the voltage at the gate of the PMOS transistor P 20  is decreased. As the voltage at the gate of the PMOS transistor P 10  is increased, the transistor P 10  shuts off. Meanwhile, as the voltage at the gate of the PMOS transistor P 20  is decreased, it becomes more active, drawing more current from the high voltage supply Vcc. As the PMOS transistor P 20  draws more current from the high voltage supply Vcc, the voltage at the gates of the NMOS transistors N 30  and N 40  increases until the NMOS transistor N 30  becomes active. Because the voltage at the gate of the NMOS transistor N 10  is greater than the voltage at the gate of the NMOS transistor N 20 , the transistor N 10  is conducting while the transistor N 20  is turned off. As this occurs, the NMOS transistor N 10  draws more current down from the high voltage supply Vcc through the dummy load L 2  to the low voltage supply Vss. Meanwhile, as the voltage at the base of the NMOS transistor N 20  decreases, the transistor N 20  draws less current from the high voltage supply Vcc and the PMOS transistor P 30  turns off. As this occurs, the PMOS transistors P 30  and P 40  turn off. With the PMOS transistor P 30  off, and the NMOS transistor N 30  active, the voltage at the output node OUT begins to drop as the NMOS transistor N 30  sinks current from the output node OUT to the low input voltage source Vss. 
     The dummy load L 1  is designed to match the impedance of the NMOS transistors N 30  and N 40  in order to ensure that the current source capability of PMOS differential pair P 10 /P 20  remains constant as the transistors P 10  and P 20  cross through their common switch point thereby ensuring a more stable current sink circuit operation. The differential switch point is when differential voltage at the respective gates of the transistors P 10  and P 20  equals zero. The differential capacitance seen by both is balanced. The dummy load L 2  is designed to match the impedance of the PMOS transistors P 30  and P 40  in order to ensure that the current source I 5  remains constant whether the NMOS transistor N 10  or the NMOS transistor N 20  is on, thereby ensuring a more stable current source circuit operation. 
     As explained earlier, the PMOS transistor pair P 10  and P 20 , along with the NMOS transistors N 30  and N 40  form a current sink circuit, drawing current from the output node OUT to the low input voltage source Vss, thereby causing the voltage level to decrease. Furthermore, the NMOS transistor pair N 10  and N 20 , along with the PMOS transistors P 30  and P 40  form a current source circuit, which when activated sends current from the high input voltage source Vcc through the output node OUT, thereby increasing the voltage level at the output node OUT. The PMOS and NMOS transistors for the current sink circuit and the current source circuit are each arranged and biased in order to sink and source an equal amount of current to the output node OUT, such that the rate of change of voltage rise and drop at the output node OUT remains controlled. Moreover, the current source circuit and current sink circuit ensure that the voltage at the output node VOUT drives the CMOS buffer  300  properly such that when the PMOS transistor P 1  of the CMOS buffer  300  is on, the NMOS transistor N 1  of the CMOS buffer  300  is off, and when the NMOS transistor N 1  of the CMOS buffer  300  is on, the PMOS transistor P 1  of the CMOS buffer  300  is off. In this way, the CML to CMOS converter of the present invention produces an output voltage signal having a stable duty cycle. 
     As shown, FIG. 4 is identical to the diagram of FIG. 3 except that the current source I 4  is replaced with a cascode current source arrangement including PMOS transistors P 50 , P 51 , P 52 , P 60  and P 61  and a current source I REF . In addition, the current source  1   5  is replaced with a cascode current source arrangement including NMOS transistors N 50 , N 60  and N 61 . More particularly, the sources of the transistors P 10 , P 20  are coupled to the drain of the PMOS transistor P 52 . The source of the PMOS transistor P 50  is coupled to the drain of the PMOS transistor P 51 . The drain of the PMOS transistor P 50  is coupled to first terminal of current source I REF  and to the gates of the PMOS transistors P 51 , P 52  and P 61 . A second terminal of the current source I REF  is coupled to the low voltage supply Vss. The source of the PMOS transistor P 60  is coupled to the drain of the PMOS transistor P 61 . The gates of the PMOS transistors P 50  and P 60  are coupled to receive a bias voltage V BIAS1 . The drains of the PMOS transistors P 51 , P 52  and P 61  are coupled to the high voltage supply Vcc. 
     Additionally, the sources of the NMOS transistors N 10 , N 20  are coupled to the drain of the NMOS transistor N 50 . The gate of the NMOS transistor N 60  is coupled to receive a bias voltage V BIAS2 . The source of the NMOS transistor N 60  is coupled to the drain of the NMOS transistor N 61 . The sources of the NMOS transistors N 50  and N 61  are coupled to the low voltage supply Vss. The drain of the PMOS transistor P 60  is coupled to the drain of the NMOS transistor N 60  and to the gates of the NMOS transistors N 50  and N 60 . 
     The use of these cascoded transistor arrangements for the current sources I 4 , I 5  aids in forming constant and equal current flows to the transistors P 10 , P 20  and from the transistors N 10 , N 20 . 
     In many applications, it is desirable to have both an output voltage signal and its inverted complement. Accordingly, the present invention may be configured to provide both an original output voltage and an inverted complement, both of which are in synch. FIG. 5 illustrates an additional alternative embodiment of the CML to CMOS converter of the present invention which may be used to provide both an original CMOS level output voltage and its inverted complement. For simplification, the same reference symbols and numbers are used where appropriate in labeling the circuit components as those used in FIG.  3 . 
     As shown in FIG. 5, a differential voltage in the form of complementary signals is applied to the terminals A and AN of the converter. The terminal A is coupled to the base of a first bipolar junction transistor QN 10 , while the terminal AN is coupled to the base of a second bipolar junction transistor QN 20 . The collector of the transistor QN 10  and the collector of the transistor QN 20  are both coupled to a high voltage supply Vcc. The emitter of the transistor QN 10  is coupled to a first terminal of a resistor R 1 . A second terminal of the resistor R 1  is coupled to the base of a third bipolar junction transistor QN 30 , which is part of a first differential pair of transistors, and to a low voltage supply Vss through a current source I 1 . The current source, I 1 , is preferably comprised of an npn bipolar junction transistor T 100  which is driven by a constant voltage V BIAS  coupled to the base of the transistor T 100 . The emitter of the transistor QN 20  is coupled to a first terminal of a resistor R 2 . A second terminal of the resistor R 2  is coupled to the base of a fourth bipolar junction transistor QN 40 , which is also part of the first differential pair of transistors, and to the low voltage supply Vss through a second current source I 2 . The current source I 2  is preferably comprised of an npn bipolar junction transistor T 200  which is driven by the constant voltage V BIAS  coupled to the base of the transistor T 200 . The emitters of the differential pair of transistors QN 30  and QN 40  are coupled together and tied to the low voltage supply Vss through a third current source I 3 . The third current source I 3  preferably includes an npn bipolar junction transistor T 300  which is driven by the constant voltage V BIAS  coupled to the base of the transistor T 300 . The collectors of each transistor in the first differential pair QN 30  and QN 40  are both coupled to the high voltage supply Vcc. The collector of the transistor QN 30  is coupled to the high voltage supply Vcc through a first node C and a resistor R 3 , while the collector of the transistor QN 40  is coupled to the high voltage supply Vcc through a second node CN and a resistor R 4 . Together, all of these components (QN 10 , QN 20 , QN 30 , QN 40 , QN 50 , QN 60  R 1 , R 2 , R 3 , R 4 , R 5  and R 7 ) make up a bipolar input stage which is designated by the broken lines  200 . 
     In operation, when the incoming voltage signal at the terminal A is high and the incoming voltage signal at the terminal AN is low, the transistors QN 10 , QN 20  and QN 30  are turned on and the transistor QN 40  is turned off. In this state, the voltage at the node C is driven low, while the voltage at the node CN is driven high. Conversely, when the incoming voltage signal at the terminal A is low and the incoming voltage signal at the terminal AN is high, the transistor QN 30  is turned off and the transistors QN 10 , QN 20  and QN 40  are each turned on. In this state, the voltage at the node C is driven high, while the voltage at the node CN is driven low. 
     Referring again to FIG. 5, the base of a fifth bipolar junction transistor QN 50  is coupled to the node CN, while the base of a sixth bipolar junction transistor QN 60  is coupled to the node C. The collectors of each of the transistors QN 50  and QN 60  are coupled to the high voltage supply Vcc. In certain circumstances, these transistors QN 50  and QN 60  could be coupled to the high voltage supply Vcc through a PMOS transistor which would turn off for conserving power in a power down mode of operation. The emitter of the transistor QN 50  is coupled to a first terminal of a resistor R 5 . A second terminal of the resistor R 5  is coupled to the gate of a PMOS transistor P 10 , and the first terminal of a resistor R 6 . A second terminal of the resistor R 6  is coupled to the gate of an NMOS transistor N 10  and to the low voltage supply Vss through a current source I b1 . The current source I b1  preferably includes a bipolar junction transistor T 400  which is driven by the constant voltage V BIAS  coupled to the base of the transistor T 400 . The emitter of the transistor QN 60  is coupled to a first terminal of a resistor R 7 . A second terminal of the resistor R 7  is coupled to the gate of a PMOS transistor P 20  and the first terminal of a resistor R 8 . A second terminal of the resistor R 8  is coupled to the gate of an NMOS transistor N 20  and to the low voltage supply Vss through a current source I b2 . The current source I b2  preferably includes a bipolar junction transistor T 500  which is driven by the constant voltage V BIAS  coupled to the base of the transistor. 
     As illustrated in FIG. 5, the source of the PMOS transistor P 10  and the source of the PMOS transistor P 20  are both coupled together and tied to the high voltage supply Vcc through a fourth current source I 4 . The drain of the PMOS transistor P 10  is coupled to the gate and the drain of an NMOS transistor N 70  and the gate of an NMOS transistor N 80 . The source of the NMOS transistor N 70 , and the source of the NMOS transistor N 80  are both coupled to the low voltage supply Vss. The drain of the PMOS transistor P 20  is also coupled to the gate and the drain of an NMOS transistor N 40  and the gate of an NMOS transistor N 30 . The source of the NMOS transistor N 40  and the source of the NMOS transistor N 30  are both coupled to the low voltage supply Vss. The drain of the NMOS transistor N 30  is coupled to the output node OUT, while the drain of the NMOS transistor N 80  is coupled to the inverted output node NOUT. Together, the transistors P 10 , N 70  and N 80  and the transistors P 20 , N 30  and N 40 , form two separate current mirror circuits which are configured to sink current, however, not at the same time. When activated, the transistors P 20 , N 30  and N 40  function to sink current from the output node OUT, thereby decreasing the voltage level at the output node OUT. Likewise, when activated, the transistors P 10 , N 70  and N 80  function to sink current from the inverted output node NOUT, thereby decreasing the voltage level at the inverted output node NOUT. As will be described in further detail below, these separate current mirror circuits sink current from either the output node OUT or the inverted output node NOUT at any one time; but, will not sink current from both nodes at the same time. 
     The source of the NMOS transistor NlO and the source of the NMOS transistor N 20  are both coupled together and tied to the low voltage supply Vss through a fifth current source I 5 . The drain of the NMOS transistor N 10  is coupled to the gate and the drain of a PMOS transistor P 70 , and the gate of a PMOS transistor P 80 . The source of the PMOS transistor P 70  and the source of the PMOS transistor P 80  are both coupled to the high voltage supply Vcc. The drain of the NMOS transistor N 20  is also coupled to the gate and the drain of a PMOS transistor P 40 , and the gate of a PMOS transistor P 30 . The source of the PMOS transistor P 40  and the source of the PMOS transistor P 30  are each coupled to the high voltage supply Vcc. The drain of the PMOS transistor P 30  is coupled to the output node OUT, while the drain of the PMOS transistor P 80  is coupled to the inverted output node NOUT. The transistors N 10 , P 70  and P 80  and also N 20  and P 30 , P 40  form two separate current source circuits that are configured to be independently active such that they cannot source current at the same time. When activated, the transistors N 20 , P 30  and P 40  source current to the output node OUT, thereby increasing the voltage level at the output node OUT. Likewise, when activated, the transistors N 10 , P 70  and P 80  source current to the inverted output node NOUT, thereby increasing the voltage level at the inverted output node NOUT. 
     In short, FIG. 5 differs from the circuit depicted in FIG. 3 in two ways. First, the drain of the NMOS transistor N 10  is longer tied directly to the high voltage supply Vcc through the dummy load L 2 . Instead, the drain of the NMOS transistor N 10  is coupled to a second set of PMOS transistors P 70  and P 80 . Second, the drain of the PMOS transistor P 10  is no longer tied directly to the low voltage supply through the dummy load L 1 . Instead, the drain of the PMOS transistor P 10  is coupled to a second set of NMOS transistors N 70  and N 80 . The second set of PMOS transistors P 70  and P 80 , along with the second set of NMOS transistors N 70  and N 80  are each coupled to the inverted output node NOUT. 
     Much like the operation of the circuit described in FIG. 3, in the alternative embodiment of FIG. 5, when the voltage at the node C is high and the voltage at the node CN is low (as discussed earlier, this occurs when the incoming voltage signal at the terminal A is low and the incoming voltage signal at the terminal AN is high), the transistors QN 50  and QN 60  level shift the differential voltage down by one Vbe plus a ΔV to the gate inputs of the NMOS transistors N 10 , N 20  and the PMOS transistors P 10 , P 20 . In this state, the voltage at the gate of the PMOS transistor P 20  increases while the voltage at the gate of the PMOS transistor P 10  decreases. This turns the transistor P 20  off, while drawing more current through the transistor P 10  from the high voltage supply Vcc. As this occurs voltage at the gate of the NMOS transistor N 80  increases. Meanwhile, the voltage at the gate of the NMOS transistor N 20  is increased, while the voltage at the gate of the NMOS transistor N 10  is decreased. This causes the NMOS transistor N 10  to turn off, while causing the NMOS transistor N 20  to draw more current from the high voltage supply Vcc, thereby activating the PMOS transistor P 30 . As the PMOS transistor P 30  is activated, current is sourced down from the high voltage supply Vcc to the output node OUT, thereby causing the voltage at the output node OUT to increase. Alternately, a current sink is created as current is drawn down from the inverted output node NOUT through the NMOS transistor N 70 , thereby causing the voltage at the inverted output node NOUT to decrease. 
     Conversely, when the voltage at the node C is low and the voltage at the node CN is high (as discussed earlier, this occurs when the incoming voltage signal at the terminal A is high and the incoming voltage signal at the terminal AN is low), the transistors QN 50  and QN 60  level shift this differential voltage down by one Vbe plus a ΔV to the gate inputs of the NMOS transistors N 10 , N 20  and the PMOS transistors P 10 , P 20  . In this state, the voltage at the gate of the PMOS transistor P 10  is increased, while the voltage at the gate of the PMOS transistor P 20  is decreased. As the voltage at the gate of the PMOS transistor P 10  is increased, the transistor turns off, and as the voltage at the gate of the PMOS transistor P 20  is decreased, it becomes more active, drawing more current from the high voltage supply Vcc through the current source I 4 . This condition causes the voltage at the gate of the NMOS transistor N 30  to increase until it becomes active. Once active, the NMOS transistor N 30  will sink current down from the output node OUT to the low voltage supply Vss. 
     Additionally, the voltage at the gate of the NMOS transistor N 10  is increased causing the transistor to draw more current down from the high voltage supply Vcc. In this state, the voltage at the gate of the PMOS transistor P 80  decreases as current is drawn down through the NMOS transistor N 10 , until the PMOS transistor P 80  becomes active. When the PMOS transistor P 80  becomes active, current is drawn down through from the high voltage supply Vcc to the inverted output node NOUT. 
     As has been described earlier, the circuit shown in FIG. 5 is designed to ensure that when current is sourced to the output node OUT, the same amount of current is sunk from the inverted output node NOUT. Likewise, when current is sourced to the inverted output node NOUT, the same amount of current is sunk from the output node OUT. At no time is current simultaneously sourced to both the output node OUT and the inverted output node NOUT and current is not simultaneously sunk from both the output node OUT and the inverted output node NOUT. The transistor turn-on and turn-off or threshold values and the biasing for the fourth and fifth current sources I 4  and I 5  are set to arrange the current sink and current source to be equal amounts of current, such that the voltage rise and drop at the output node OUT and the inverted output node NOUT remain constan. Thus, the duty cycle of the input signal will not experience significant duty cycle distortion at the output. 
     FIG. 6 illustrates a schematic diagram of a third alternative embodiment of the CML to CMOS converter of the present invention having a level shift arrangement which includes diodes QN 70  and QN 80 . The circuit illustrated in FIG. 6 differs from that illustrated in FIG. 3 in that the resistor R 5  is omitted (replaced with a short) and the resistor R 6  is replaced with an npn bipolar transistor QN 70  configured as a diode such that its anode is coupled to the emitter of the transistor QN 50  and to the gate of the NMOS transistor N 10 , and its cathode is coupled to the gate of the PMOS transistor P 10  and to the current source I b1 . In addition, the resistor R 7  is omitted (replaced with a short) and the resistor R 8  is replaced with an npn bipolar transistor QN 80  configured as a diode such that its anode is coupled to the emitter of the transistor QN 60  and to the gate of the NMOS transistor N 20  and its cathode is coupled to the gate of the PMOS transistor P 20  and to the current source I b2 . 
     Finally, FIG. 7 shows a detailed schematic for an alternative embodiment of the CML to CMOS converter of the present invention. In FIG. 7, the NMOS transistors MN 9  and MN 10  perform the same functions as the NMOS transistors N 10  and N 20  described above in FIG. 5, the PMOS transistors MP 1  IN and MP 12 N perform the same functions as the PMOS transistors P 70  and P 80  described above in FIG. 5, and the PMOS transistors MP 11  and MP 12  perform the same function as the PMOS transistors P 40  and P 30  described above in FIG.  5 . Accordingly, the transistors MN 10 , MP 11  and MP 12  operate as a current source circuit for driving current to the output node VO 1 , while the transistors MN 9 , MP 11 N and MP 12 N operate as a current source circuit for driving current to the inverted output node V 01 N. 
     Additionally, in FIG. 7, the PMOS transistors MP 9  and MP 10  perform the same functions as the PMOS transistors P 10  and P 20  described above in FIG.  5 . The NMOS transistors MN 14  and MN 15  perform the same functions as the NMOS transistors N 30  and N 40  described above in FIG. 5, while the NMOS transistors MN 14 N and MN 15 N perform the same function as the NMOS transistors N 70  and N 80  described above in FIG.  5 . Accordingly, the transistors MP 10 , MN 14  and MN 15  operate as a current sink circuit for drawing current from the output node V 01 , while the transistors MP 9 , MNl 4 N and MN 15 N operate as a current sink circuit for drawing current from the inverted output node VOIN. 
     The additional transistors which are shown in FIG. 7 reflect an optimal biasing configuration which may be utilized in order to further ensure that the amount of current driven to either output node V 01  or V 01 N is equal to the amount of current drawn from such node, thereby creating an output voltage signal that has a symmetrical rise and fall time characteristic which translates to a constant duty cycle at either output node V 01  or V 01 N. 
     The present invention has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles of construction and operation of the invention. Such reference herein to specific embodiments and details thereof is not intended to limit the scope of the claims appended hereto. It will be apparent to those skilled in the art that modifications may be made in the embodiment chosen for illustration without departing from the spirit and scope of the invention. Specifically, it will be apparent to one of ordinary skill in the art that the device of the present invention could be implemented in several different ways and the apparatus disclosed above is only illustrative of the preferred embodiment of the invention and is in no way a limitation. For example, it would be within the scope of the invention to vary the values of the various components, current levels, and voltage levels disclosed herein.