Patent Publication Number: US-5894495-A

Title: Adaptive digital filter

Description:
The present invention relates to adaptive digital filters. 
     Digital filters can be applied for the purpose of echo cancellation during bidirectional transmission of signals via a single transmission channel. The coefficients of the digital filter are chosen such that the impulse response function of the digital filter matches the impulse response function of the transmission channel. If a signal s, transmitted via the transmission channel, is fed into the digital filter, the output e of the digital filter is equal to the echo received from the transmission channel. By subtracting the output signal e of the digital filter from a received signal s&#39; the echo of the transmitted signal s is eliminated and a result signal f is obtained. 
     If the impulse response function of the transmission channel is not known or if it changes from time to time, the coefficients of the digital filter may be newly calculated and adapted, for example, using a LMS (least mean square) algorithm. Digital filters with coefficients being adapted during filter operation are referred to as adaptive digital filters. 
     FIG. 1 shows the structure of a known adaptive digital filter 100. The filter comprises a shift register 102 with N register steps 102 0 , 102 1 , 102 2  . . . 102 N-3 , 102 N-2 , 102 N-1  for storing N symbols s 0 , s 1 , s 2  . . . s N-3 , s N-2 , s N-1  of a digital signal s, a coefficient memory 103 comprising N coefficient registers 103 0 , 103 1 , 103 2  . . . 103 N-3 , 103 N-2 , 103 N-1  for storing N filter coefficients c 0 , c 1 , c 2  . . . c 3 , c N-2 , c N-1 , N multipliers 104 0 , 104 1 , 104 2  . . . 104 N-3 , 104 N-2 , 104 N-1 , each of which is assigned to one of said register steps 102 0 , 102 1 , 102 2  . . . 102 N-3 , 102 N-2 , 102 N-1  and to a corresponding one of said coefficient registers 103 0 , 103 1 , 103 2  . . . 103 N-3 , 103 N-2 , 103 N-1 , and an adder 105. 
     A digital symbol s n  of a transmitted signal s is fed into the first register step 102 0  depending on a clock signal. Prior thereto the symbols stored in the steps 102 1 , 102 2  . . . 102 N-3 , 102 N-2  are shifted into the respective next step of the shift register 102 every time before a new symbol sn is fed into the first register step 102 0 . Thereby, a symbol history of the digital signal s is stored in the register steps of the shift register 102. After a new symbol s n  has been fed into the first register step 102 0  of the shift register 102, every symbol s 0 , s 1 , s 2  . . . s N-3 , s N-2 , s N-1  of the signal history is multiplied by the respective multiplier 104 0 , 104 1 , 104 2  . . . 104 N-3 , 104 N-2 , 104 N-1  with the corresponding filter coefficient c 0 , c 1 , c 2  . . . c N-3 , c N-2 , c N-1 . Subsequently, the multiplication results are added by the adder 105. The output of the adder 105 is the output signal e of the digital filter. 
     As also shown in FIG. 1, the known adaptive digital filter 1 further comprises a first group of N multipliers 106 1 , 106 2 , 106 3  . . . 106 N-3 , 106 N-2 , 106 N-1 , a second group of N multipliers 107 1 , 107 2 , 107 3  . . . 107 N-3 , 107 N-2 , 107 N-1  and N adders 108 1 , 108 2 , 108 3  . . . 108 N-3 , 108 N-2 , 108 N-1 , respectively assigned to an individual one of said register steps 102 0 , 102 1 , 102 2  . . . 102 N-3 , 102 N-2 , 102 N-1  of the shift register 102 and the corresponding coefficients c 0 , c 1 , c 2  . . . c N-3 , c N-2 , c N-1 . 
     In order to adapt the filter coefficients to match the channel response, the result signal f, obtained by subtracting the filter output signal e from the received signal s&#39; and the symbols s 0 , s 1 , s 2  . . . s N-3 , s N-2 , s N-1  of a digital signal s, stored in the register steps 102 0 , 102 1 , 102 2  . . . 102 N-3 , 102 N-2 , 102 N-1  are multiplied by the multipliers 106 1 , 106 2 , 106 3  . . . 106 N-3 , 106 N-2 , 106 N-1  of the first group, the output signals of which are supplied to the multipliers 107 1 , 107 2 , 107 3  . . . 107 N-3 , 107 N-2 , 107 N-1  of the second group where they are multiplied with a scaling factor α. Each of the output signals of the multipliers 107 1 , 107 2 , 107 3  . . . 107 N-3 , 107 N-2 , 107 N-1  of the second group is added by a respective one of adders 108 1 , 108 2 , 108 3  . . . 108 N-3 , 108 N-2 , 108 N-1  to a respective one of previously stored filter coefficients c 0 , c 1 , c 2  . . . c N-3 , c N-2 , c N-1 . The sums are stored as new, adapted coefficients c 0 , c 1 , c 2  . . . c N-3 , c N-2 , c N-1  in the respective one of the coefficient registers 103 0 , 103 1 , 103 2  . . . 103 N-3 , 103 N-2 , 103 N-1 . 
     An adaptive digital filter structure can be implemented by means of an integrated circuit in different ways, depending on the operation requirements. If fastest operation is needed, the hardware to perform the required filter computations and the coefficient adapting computations for all N symbols of the symbol history is implemented in parallel, as shown in FIG. 1. Only one clock cycle per symbol s n  is needed to compute the filter output signal e, but the maximum chip area is required. 
     In many applications the operational speed is less critical, so that the number of multipliers and adders may be reduced. The available multipliers and adders are used to perform the required filter and coefficient adapting computations for all N symbols of the symbol history in a serial manner. This multiple usage of a hardware structure is called &#34;resource sharing&#34;. 
     FIG. 2 shows a conventional realization of resource sharing for an adaptive digital filter with a symbol history of N symbols. In this particular case, the hardware to perform the required filter and coefficient adapting computations is provided such that only three symbols of the symbol history may be handled simultaneously in parallel. 
     Three multipliers 140 A , 140 B  and 140 C  are provided to multiply three successive symbols of the symbol history stored in the shift register 120 with the three corresponding coefficients stored in a coefficient RAM 130. The adaptive digital filter further comprises a first group of three multipliers 160 A , 160 B  and 160 C , a second group of three multipliers 170 A , 170 B  and 170 C  and three adders 180 A , 180 B  and 180 C  to simultaneously adapt three successive coefficients stored in a coefficient RAM 130. 
     The operation of the adaptive digital filter of FIG. 2 is controlled by a controller 111 and two multiplexers 109 and 110. Since the coefficients are stored in a coefficient RAM 130, which can be addressed according to known addressing techniques, additional multiplexers can be avoided but may be used in an alternative design. During filter operation, three successive register steps and the three corresponding coefficients are selected to be operated on in parallel. In other words, during a first cycle the register steps 120 0 , 120 1 , and 120 2  are connected to the three multipliers 140 A , 140 B  and 140 C , the first group of three multipliers 160 A , 160 B  and 160 C  and the three corresponding coefficients c 0 , c 1  and c 2  are selected and fed to the three multipliers 140 A , 140 B  and 140 C  and the three adders 180 A , 180 B  and 180 C . During the second cycle the register steps 120 3 , 120 4  and 120 5  are connected to the three multipliers 140 A , 140 B  and 140 c , the first group of three multipliers 160 A , 160 B  and 160 C  and the three corresponding coefficients c 3 , c 4  and c 5  are selected and fed to the three multipliers 140 A , 140 B  and 140 C  and the three adders 180 A , 180 B  and 180 C . Likewise all register steps and coefficients to N-3, N-2 and N-1 are processed. 
     The output of the adder 150 for each cycle is stored in an intermediate register 112, the content of which is input into the adder 150 during the next cycle, until all N filter coefficients and symbols of the symbol history have been processed. Accordingly, N/3 cycles are required to compute an output value e for every new symbol s n . 
     The known approach of resource sharing in an adaptive digital filter leads to a substantial reduction of required chip area although additional structures, for example the controller and the two multiplexers, are necessary. The reduction is achieved by providing only a limited number of filter computation and coefficient adapting means. The chip area required by an individual one of said filter computation and coefficient adapting means is determined by the magnitude of the largest symbol and/or coefficient to be processed. 
     Nevertheless, it is desired to further reduce the required chip area of the adaptive digital filter. 
     Therefore, it is the object of the invention to propose an adaptive digital filter requiring a further reduced chip area. 
     This object is solved by an adaptive digital filter device, comprising storage means 2 for storing a plurality of digital symbols s 0 , s 1 , s 2  . . . s N-3 , s N-2 , s N-1  representing the symbol history of a signal s; coefficient storage means 3 for storing a plurality of filter coefficients c 0 , c 1 , c 2  . . .c N-3 , c N-2 , c N-1  each of which corresponds to one of said of symbols s 0 , s 1 , s 2  . . . s N-3 , s N-2 , s N-1  ; first and second filter computation means 4 A , 4 B  for performing filter computations on the basis of said symbols and said filter coefficients; adding means 5 for adding the output of said first and second filter computation means 4 A , 4 B  and for outputting a filter value e; first and second coefficient adapting means 7 A , 7 B  for adapting said filter coefficients c 0 , c 1 , c 2  . . . c N-3 , c N-2 , c N-1  stored in said coefficient storage means 3; and control means 6 for controlling the operation of the adaptive digital filter; characterized in that said first and second filter computation means 4 A , 4 B  are connected to said coefficient storage means 3 with a different bit width to receive coefficients c 0 , c 1  . . . c N/2-2 , c N/2-1 , c N/2 , c N/2+1  . . . c N-2 , c N-1  having different magnitudes and/or said first and second coefficient adapting means 7 A , 7 B  are connected to said coefficient storage means 3 with a different bit width to receive coefficients c 0 , c 1  . . . c N/2-2 , c N/2-1  ; c N/   2 , c N/2+1  . . . c N   31  2, c N-1  having different magnitudes. 
     By introducing a different bit width for the connection of the first and second filter computation means 4 A , 4 B  and/or for the first and second coefficient adapting means 7 A , 7 B  to the coefficient storage means 3 a reduction of the size of the first or second filter computation means 4 A , 4 B  and/or of the first or second coefficient adapting means 7 A , 7 B  and thus of the required chip area is achieved. If, for example, the bit width for the connection of the second filter computation means 4 B  and for the second coefficient adapting means 7 B  is smaller than the bit width for the connection of the first filter computation means 4 A  and for the first coefficient adapting means 7 A , the hardware structure of the second filter computation means 4 B  and the second coefficient adapting means 7 B  requires less chip area due to the lower bit resolution in comparison with the first filter computation means 4 A  and the first coefficient adapting means 7 A . In the prior art, the same bit resolution is used for all filter computation means and all coefficient adapting means so that in comparison with the present invention a larger chip area is needed. 
     Further, by introducing a different bit widths for the connections of the first and second filter computation means 4 A , 4 B  and/or for the first and second coefficient adapting means 7 A , 7 B  the coefficients are stored with different bit resolutions and the chip area for the coefficient storage means 3 and likewise of the area for the buses for connecting the coefficient storage means 3 is reduced and excessive capacitive loads caused by the buses are avoided. Thus, the object of the invention can also be solved by providing a coefficient storage means 3 with reduced size for storing coefficients of different bit resolution. 
     Still further, the reduction of the resolution of the means for filter computation 4 allows to reduce the hardware and the size of the adding means 5. 
     In the following the invention will be described with reference to embodiments and drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a known adaptive digital filter with full parallel realization. 
     FIG. 2 shows a known adaptive digital filter with N/3 type resource sharing. 
     FIG. 3 shows an adaptive digital filter according to the present invention. 
     FIG. 4 shows several examples of transmission channel impulse response functions. 
     FIG. 5 shows a storage means for storing the symbols of the symbol history of an adaptive digital filter according to the present invention. 
     FIG. 6 shows a coefficient adapting means of an adaptive digital filter according to the present invention. 
     FIG. 7 shows a coefficient storage means of an adaptive digital filter with N/3 type resource sharing according to the present invention. 
     FIG. 8 shows an adding means of an adaptive digital filter with N/3 type resource sharing according to the present invention. 
    
    
     In FIG. 3, a first embodiment of the adaptive digital filter according to the present invention is shown. The adaptive digital filter 1 comprises storage means 2 for storing N symbols s 0 , s 1 , s 2  . . . s N-3 , s N-2 , s N-1  representing the symbol history of a digital signal s and a coefficient storage means 3 comprising N storage locations for storing N filter coefficients c 0 , c 1 , c 2  . . . c N-3 , c N-2 , c N-1 , each of which corresponds to one of said N symbols. The adaptive digital filter 1 further comprises first and second filter computation means 4 A , 4 B  for performing filter computations on the basis of said symbols and said filter coefficients, for example for multiplying one of said symbols s 0 , s 1 , s 2  . . . s N-3 , s N-2 , s N-1  with the corresponding filter coefficient c 0 , c 1 , c 2  . . . c N-3 , c N-2 , c N-1 . The first filter computation means 4 A  is connected to the coefficient storage means 3 with a larger bit width than the second filter computation means 4 B . In other words, the bit resolution of the first filter computation means 4 A  is higher than the bit resolution of the second filter computation means 4 B . The results of the filter computations performed by said first and second filter computation means 4 A , 4 B  are supplied to adding means 5 which is capable of adding the results and a value stored in an intermediate storage location 51. control means 6 are connected to said storage means 2, said a coefficient storage means 3, said first and second filter computation means 4 A , 4 B  and said adding means 5 to control the operation thereof as follows. 
     In accordance with an first clock signal, the previously stored symbols s 0 , s 3 , s 2  . . . s N-3 , s N-2  are shifted within said storage means 2 by one step to form new symbols s 1 , s 2  . . . s N-3 , s N-2 , s N-1 , respectively, and a symbol s n  of said signal s is fed into said storage means 2 to form a new symbol s 0  Depending on a second clock signal, the control means 6 start the filter computation operation. In a first cycle, the 1st symbol s 0  and the corresponding coefficient c 0  are supplied to said first filter computation means 4 A  and the (N/2)-th symbol s N/2  and the corresponding coefficient c N/2  are supplied to said second filter computation means 4 B . The adding means 5 receive the results of the filter computations performed by said filter computation means 4 A , 4 B  and are controlled to add the results and store the sum in the intermediate storage location 51 replacing any previously stored value. In a second cycle, the 2nd symbol s 1  and the corresponding filter coefficient c 1  are supplied to said first filter computation means 4 A  and the (N/2+1)-th symbol s N/2+1  and the corresponding coefficient c N/2+1  are supplied to the second filter computation means 4 B . The adding means 5 receive the results of the filter computations performed by said filter computation means 4 A , 4 B  and are controlled to add the results as well as the value stored in the intermediate storage location 51 and to store the sum in the intermediate storage location 51 replacing any previously stored value. The latter cycle is repeated for the 3rd to (N/2-1)-th symbols s 3  . . . s N/2-1  and corresponding coefficients c 3  . . . . c N/2-1  and the (N/2+2)-th to (N)-the symbol s N/2+2  . . . s N-1  and corresponding coefficients c N/2+2  . . . c N-1 . The filter computations are completed for all N symbols and the corresponding N coefficients after N/2 cycles. Thereafter, the value stored in the intermediate storage location 51 is output as the filter value e. 
     Furthermore, the adaptive digital filter 1 shown in FIG. 3 comprises first and second coefficient adapting means 7 A , 7 B  for adapting said filter coefficients c 0 , c 1 , c 2  . . . c N-3 , c N-2 , c N-1 . The first coefficient adapting means 7 A  is connected to the coefficient storage means 3 with a larger bit width than the second coefficient adapting means 7 B . In other words, the bit resolution of the first coefficient adapting means 7 A  is higher than the bit resolution of the second coefficient adapting means 7 B . A coefficient adapting value a, preferably computed on the basis of the filter output e, for example by subtracting the filter output e from a received signal s&#39;, is supplied to the coefficient adapting means 7 A , 7 B . The control means 6 control the coefficient adapting operation simultaneously with the filter computations as follows. 
     After new symbols s 0 , s 1 , s 2  . . . s N-3 , s N-2 , s N-1  have been formed in accordance with the first clock signal, in the first cycle depending on the second clock signal, the 1st symbol s 0  and the corresponding coefficient c 0  are supplied to said first coefficient adapting means 7 A  and the (N/2)-th symbol s N/2  and the corresponding coefficient c N/2  are supplied to said second filter coefficient adapting means 7 B . The first and second coefficient adapting means 7 A , 7 B  compute adapted coefficients c 0  and c N/2  and store the adapted coefficients in the respective storage locations in the coefficient storage means 3. In the second cycle, the 2nd symbol s 1  and the corresponding filter coefficient c 1  are supplied to said first coefficient adapting means 7 A  and the (N/2+1)-th symbol s N/2+1  and the corresponding coefficient c N/2+1  are supplied to the second coefficient adapting means 7 B . Again, the first and second coefficient adapting means 7 A , 7 B  compute adapted coefficients c 1  and c N/2+1  and store the adapted coefficients in the respective storage locations in the coefficient storage means 3. The latter cycle is repeated for the 3rd to (N/2-1)-th symbols s 3  . . . s N/2-1  and corresponding coefficients c 3  . . . c N/2-1  and the (N/2+2)-th to (N)-the symbol s N/2+2  . . . s N-1  and corresponding coefficients c N/2+2  . . . c N-1 . The coefficient adapting operation is also completed for all N coefficients after N/2 cycles. 
     As mentioned above, the bit widths of the connections of the first filter computation means 4 A  and the first coefficient adapting means 7 A  with the coefficient storage means 3 are different from the bit widths of said connections of the second filter computation means 4 B  and of the second coefficient adapting means 7 B  and thus the bit resolution of the first filter computation means 4 A  and the first coefficient adapting means 7 A  is different from the bit resolution of the second filter computation means 4 B  and the second coefficient adapting means 7 B . The underlying principle is outlined in the following: as it can be observed in FIG. 4, the examples of transmission channel impulse response functions show a characteristic attenuation which progresses with the time after pulse emission. Accordingly, the magnitude of the respective filter coefficients c 0 , c 1  . . . c N-2 , c N-1  also decreases and the filter operations are performed with, for increasing n, progressively smaller coefficients. The invention proposes an adaptive digital filter having a hardware structure which reflects said decreasing magnitude in form of a partially reduced bit resolution of specific circuit components. In the case of the embodiment described with respect to FIG. 3, the magnitude of the filter coefficients c 0 , c 1  . . . c N/2-2 , c N/2-1  connected to the first filter computation means 4 A  and to the first coefficient adaption means 7 A  is larger than the magnitude of the filter coefficients c N/2 , c N/2+1  . . . c N-2 , c N-1  connected to the second filter computation means 4 B  and to the second coefficient adaption means 7 B . In accordance with the invention, the connections of the second filter computation means 4 B  and the second coefficient adapting means 7 B  with the coefficient storage means 3 is realized with smaller bit width than said connections of the first filter computation means 4 A  and of the first coefficient adapting means 7 A  and thus the second filter computation means 4 B  is realized with smaller bit resolution than the first filter computation means 4 A  and the second coefficient adapting means 7 B  is realized with smaller bit resolution than the first coefficient adapting means 7 A  and the coefficients are stored with different bit resolution in the coefficient storage means 3. Thereby, the hardware and the needed chip area are reduced. 
     It is understood, that in other embodiments of the present invention the bit width of the connection of second filter computation means 4 B  with the coefficient storage means 3 can be realized with smaller bit resolution than said connection of the first filter computation means 4 A  while the bit widths of said connections of the first and second coefficient adapting means 7 B , 7 B  can realized with equal bit width or vice versa. In other words, in other embodiments of the present invention the second filter computation means 4 B  can be realized with smaller bit resolution than the first filter computation means 4 A  while the first and second coefficient adapting means 7 B , 7 B  can realized with equal bit resolution or vice versa. 
     It is also understood, that further embodiments of the present invention with a larger number of filter computation means 7 and a larger number of coefficient adapting means 4 are possible and further, that the N symbols s 0 , s 1  . . . s N-2 , s N-1  of the symbol history and the corresponding N filter coefficients c n , c 1  . . . c N-2 , c N-1  can be assigned in any suitable order to the available filter computation means 4 and also can be assigned in any suitable order to the available coefficient adapting means 7. 
     In a second embodiment of the adaptive digital filter according to the present invention, the first and second filter computation means 4 A , 4 B  and the first and second coefficient adapting means 7 A , 7 A  and the adding means 5 are connected to a first and a second clock, instead of being connected to the control means 6. In this case the filter operation differs from the one described above as follows: in accordance with a signal from the first clock the intermediate storage location 51 of the adding means 5 is initialized with the value zero. In accordance with a signal from the second clock the first and second filter computation means 4 A , 4 B , as described above, compute a result value from the input values supplied by the storage means 2 and the coefficient storage means 3, both being controlled by control means 6 as described above. The first and the second coefficient adapting means 7 A , 7 B , as described above, compute a result value from the input values supplied by the storage means 2 and the coefficient storage means 3, both being controlled by control means 6 as described above, and the coefficient adapting value a. Further, the adding means 5 receive the results of the filter computations performed by said filter computation means 4 A , 4 B  and add the results and the value stored in the intermediate storage location 51 and store the sum in the intermediate storage location 51 replacing any previously stored value. 
     FIG. 5 shows an example the storage means 2 of the adaptive digital filter according to the present invention. It comprises a shift register 21 with N register steps 21 0 , 21 1  . . . 21 N-2 , 21 N-1  for storing the N symbols s 0 , s 1  . . . s N-2 , s N-1  representing the symbol history of the signal s and four multiplexers 22 1  -22 4 , controlled by the control means 6. The multiplexers 22 1  and 22 3  are connected to the register steps 21 0 , 21 1  . . . 21 N/2-2 , 21 N/2-1  of the shift register 21 and the multiplexers 22 2  and 22 4  are connected to the register steps 21 N/2 , 21 N/2+1  . . . 21 N-2 , 21 N-1  of the shift register 21. Further, the multiplexer 22 1 , is connected to the filter computation means 4 A , the multiplexer 22 2  is connected to the filter computation means 4 B  the multiplexer 22 3  is connected to the coefficient adapting means 7 A  and the multiplexer 224 is connected to the coefficient adapting means 7 B . 
     During filter operation the multiplexers are controlled by the control means 6 such that for each cycle the multiplexers 22 1  and 22 3  are connected to one of the register steps s 0 , s 1  . . . s N/2-2 , s N/2-1  and likewise the multiplexers 22 2  and 22 4  are connected to one of the register steps s N/2 , s N/2+1  . . . s N-2 , s N-1  to operate in parallel. In other words, during a first cycle the register step s 0  is connected to the first filter computation means 4 A  and to the first coefficient adapting means 7 A  and the register step s N/2  is connected to the second filter computation means 4 B  and to the second coefficient adapting means 7 B . During the second cycle the register steps s 1  is connected to the first filter computation means 4 A  and to the first coefficient adapting means 7 A  and the register step s N/2+1  is connected to the second filter computation means 4 B  and to the second coefficient adapting means 7 B  and likewise for the following cycles all register steps to N-3, N-2 and N-1. 
     It is understood that in other embodiments of the present invention the storage means 2 of FIG. 5 can be realized with only two multiplexers, either with the multiplexers 22 1 , 22 2  or with the multiplexers 22 3 , 22 4 . In this case both, the first filter computation means 4 A  and the first coefficient adapting means 7 A  are connected to the multiplexer 22 1 , or to the multiplexer 22 3 , respectively, and both, the second filter computation means 4 B  and the second coefficient adapting means 7 B  are connected to the multiplexer 22 2  or to the multiplexer 22 4 , respectively. 
     The filter computation means 4 B  and 4 B  preferably consist each of one multiplier which each is connected to the storage means 2, to the coefficient storage means 3 and to the adding means 5. During filter operation the multipliers multiply a symbol of the symbol history with the corresponding filter coefficient and the result signal is supplied to the adding means 5. 
     FIG. 6 shows a coefficient adapting means 7 of the adaptive digital filter according to the present invention. It comprises a multiplier 71 and an adder 72. The multiplier 71 is connected to receive the coefficient adapting value a and is connected to receive an input signal from the storage means 2. The adder 72 is connected to receive a signal from the multiplier 71 and from the coefficient storage means 3 and is connected to supply a result value to the coefficient storage means 3. During coefficient adapting operation the multiplier 71 multiplies the coefficient adapting value a with the input from the storage means 3 and supplies the result value to the adder 72. The adder 72 adds the result value and the input from the coefficient storage means 3 and supplies the sum to the coefficient storage means 3. 
     FIG. 7 shows an example of coefficient storage means 3 of the adaptive digital filter with N3 type resource sharing according to the present invention. The coefficient storage means 3 consists of a RAM of the size 24×60 bit for storing coefficients of different bit width. The adaptive digital filter of this embodiment has N=72 coefficients and three coefficient adapting means 7 A , 7 B  and 7 C  and three filter computation means 4 A , 4 B  and 4 C . The RAM 3 is connected to the control means 6 and connected to receive an input from each of the three coefficient adapting means 7 A , 7 B  and 7 C  an to supply an output to each of the three filter computation means 4 A , 4 B  and 4 C  and to each of the three coefficient adapting means 7 A , 7 B  and 7 C . The RAM is addressed by the control means 6 such that the coefficients are read/written in three groups with the first group of 24 coefficients (c 0 , c 1  . . . c 22 , c 23 ) being stored with a resolution of 24 bits, the second group of 24 coefficients (c 24 , c 25  . . . c 46 , c 47 ) being stored with a resolution of 20 bits and the third group of 24 coefficients (c 48 , c 49  . . . c 70 , c 71 ) being stored with a resolution of 16 bits. 
     FIG. 8 shows a adding means 5 and three filter computation means 4 A , 4 B  and 4 C  of the adaptive digital filter with N/3 type resource sharing according to the present invention. The bit resolution of the first filter computation means 4 A  is larger than the bit resolution of the second filter computation means 4 B  which bit resolution is larger than the bit resolution of the third filter computation means 4 C . The adding means 5 consists of three adders 52, 53 and 54 and of an intermediate storage location 51. The first adder 52 has a smaller bit resolution than the second adder 53 and is connected to receive an input value from the third filter computation means 4 C  and from the second filter computation means 4 B . The second adder 53 has a smaller bit resolution than the third adder 54 and is connected to receive an input from the first adder 52 and from the first filter computation means 4 A . The third adder 54 is connected to receive an input from the second adder 53 and from the intermediate storage location 51. The intermediate storage location 51 is connected to receive an input from the third adder 54 and outputs the filter signal e. 
     The operation of the adding means 5 is controlled by the control means 6. During a typical operation cycle of the adding means 5, the first adder 52 adds the values received from the third filter computation means 4 C  and from the second filter computation means 4 B . The second adder 53 adds the value received from the first filter computation means 4 A  and the result value from the first adder 52. The third adder 54 adds the result value from the second adder 53 and the value stored in the intermediate storage location 51 and stores the result in the intermediate storage location 51 overwriting any previously stored value.