Patent Publication Number: US-7216262-B2

Title: RAM diagnostic read circuit providing external integrated circuit RAM failure diagnosis and method

Description:
BACKGROUND OF THE INVENTION 
     Integrated circuits include many imbedded random access memories (RAMs) of many different sizes and offering different options (single, dual, multi-port). These RAMs sometimes fail in the field, even after passing manufacturing tests. For example, integrated circuits may include multiple RAMs used to buffer data flow. Failures may occur in such RAMs for both inbound and outbound data flow. The failures may occur intermittently depending on data pattern and voltages. Once failure occurs, it is difficult to determined the contents of the failing RAMs because the RAMs are imbedded within the integrated circuit. Failing bits and addresses thus must be inferred by examining actual data flow and working backwards to determine what would reasonably have been expected to have gone through the failing RAM. However, many uncertainties can be left in this type of analysis. Furthermore, this form of analysis consumes an inordinate amount of time. 
     When RAMs fail in the field, there are no readily available options to diagnose the failures as they occur. The imbedded RAMs are usually tested by imbedded built-in self-test (BIST) circuits which are small logic blocks that run a variety of tests (checkerboard, walking ones/zeros, etc.). Sometimes, the RAMs are tested through external testers, although this is not as effective due to lower pattern coverage and slower speed resulting in longer test durations. However, once in the field, a failure cannot be diagnosed through an external tester. Further, a BIST is limited in its ability to detect or diagnose failures. While a BIST may detect most failures during manufacturing, no BIST will have tests comprehensive enough to detect all possible failure modes. The reason for this is that a field failure mode will often be undetectable by BIST algorithms. 
     An example is when a RAM, imbedded in an integrated circuit, experiences a parity error in a data stream. It is often quite difficult to disengage the RAM from the data flow to determine exactly what section or portion of the RAM failed. BIST blocks only go through a predetermined sequence of write and read commands to test RAMs with specific data patterns. A BIST block cannot easily read the exact content of a failing RAM without going through its predetermined sequence. 
     Hence, there is a need in the art for a means by which RAM failures may be readily diagnosed immediately after failure occurs, even while the integrated circuit is engaged in processing data flows in the field. One or more embodiments of the present invention address such needs. 
     SUMMARY  
     In accordance with one embodiment of the present invention, a diagnostic read circuit transfers the content of any RAM imbedded in an integrated circuit and delivers the entire contents external to the integrated circuit for examination. Data can be delivered through a scan chain, dedicated external pins or internal buses that then go through external pins. The diagnostic read circuit can share any number of pins to be enabled and to deliver data externally. The diagnostic read circuit may include an address generator to ensure all RAM data contents are read, a data register for temporarily storing RAM data contents until ready to be delivered externally, and a sequence controller to initiate and control a RAM diagnostic read. 
     In accordance with further embodiments of the present invention, an integrated circuit comprises a random access memory, and a diagnostic read circuit, either stand alone or imbedded in a built-in self-test circuit, that reads memory storage errors in the random access memory and provides random access memory data contents externally when a memory storage error is detected in the random access memory. 
     In accordance with another embodiment of the present invention, the diagnostic read circuit may be imbedded in a BIST and share the address generator and data register. 
     The data register may be coupled to an external pin or pins of the integrated circuit. Alternatively, the integrated circuit may include a scan chain coupling the data register to an external pin. Alternatively, the data register may be coupled to an external, already defined bus in the integrated circuit. 
     In accordance with other embodiments of the invention, an address generator provides data storage addresses to the random access memory for the fetching of the stored data. The fetched data and the data storage addresses are provided from the integrated circuit for external analysis responsive to a detected error in data storage. The data storage addresses may be transferred external to the integrated circuit through, for example, a scan chain, external pin or pins, or an external bus. 
     In accordance with a further embodiment of the present invention, an integrated circuit, performs a method to allow a read of a RAM at any time and to provide the read memory contents for external analysis. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing aspects and many of the attended advantages of this invention will become more readily appreciated as the same become better understood by reference to the following non-limiting detailed description, when taken in conjunction with the accompanying drawings, wherein: 
         FIG. 1  is a block diagram of an integrated circuit including a diagnostic read circuit which may be by itself or embedded in a BIST circuit embodying the present invention embedded with a scan chain and a plurality of random access memories to be tested by the BIST; 
         FIG. 2  is a block diagram of the diagnostic read circuit of  FIG. 1  embodying the present invention; and 
         FIG. 3  is a block diagram of the BIST circuit of  FIG. 1  embodying the present invention. 
     
    
    
     DETAILED DESCRIPTION  
     The following discussion is presented to enable a person skilled in the art to make and use the invention. The general principles described herein may be applied to embodiments and applications other than those detailed below without departing from the spirit and scope of the present invention. The present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein. 
       FIG. 1  shows an integrated circuit  10  embodying the present invention. The integrated circuit includes a JTAG controller  12 , a plurality of random access memories (RAMs)  14  and  16  to be tested, and a diagnostic read circuit  18  by itself or embedded in a BIST circuit embodying the present invention and which is embedded in a scan chain  20 . The integrated circuit further includes various means to access the diagnostic read circuit or BIST  18  including, for example, a DR enable external pin  64  for receiving an externally generated DR enable signal, an internally generated DR enable signal  63 , or the JTAG controller  12 . The integrated circuit further includes a scan chain input pin  62 , Jx, DR output external pin  22 , and a scan chain output external pin  24 . As may be appreciated by those skilled in the art, the Jx, DR pin  22  may comprise a plurality of external pins. In addition to the foregoing, the integrated circuit  10  may include other logic and scan chains as generally represented at  26 . 
       FIG. 2  shows one diagnostic read circuit embodiment of the invention. The diagnostic read circuit  18  generally includes a sequence controller  50 , an address generator  52 , and a data register  54 . 
     As will be noted in  FIG. 1  and  FIG. 2 , the address generator  52  of the diagnostic read circuit  18  provides retrieval addresses to the RAMs  14  and  16  over address bus  30 . The sequence controller  50  provides control signals to the RAMs  14  and  16  over bus  32 . The sequence controller also, as will be noted in  FIG. 2 , provides control signals to the address generator  52 , and the data register  54  over bus  34 . The address generator  52  generates the data storage and retrieval addresses which are conveyed to the RAMs  14  and  16 . The data register  54  receives data read from the RAMs  14  and  16  over a bus  36 . 
     When a data storage error of a RAM is detected, the diagnostic read circuit is invoked. This may occur by a control signal received from the JTAG controller  12 , by a DR enable signal  63 , or other control signal provided at pin  64 . The sequence controller  50  then causes the address generator  52  to generate all of the addresses of the RAMS  14  thru  16 . The RAMS are preferably addressed in parallel to conserve time. The fetched or retrieved data of the RAM  14  thru  16 , as the RAMS are addressed, is conveyed to the data register  54 . For each word of data retrieved from the RAMS  14  thru  16 , the sequence controller  50  will then cause the data register to output the retrieved data to external pin  22  (or external pins) to present the data for external analysis. Alternatively, the data register may provide the retrieved data to the scan chain  20  for outputting at pin  24 . 
     Along with the retrieved data, the diagnostic read circuit  18  may also provide the RAM addresses used during the data retrieval. The address may also be provided to the external pin  24  through the scan chain  20 . 
       FIG. 3  shows a diagnostic read circuit imbedded in a BIST circuit  100 . The BIST circuit  100  and the diagnostic read circuit have address generator  52  and data register  54  in common. The diagnostic read sequence controller  50  is imbedded in the BIST sequence controller  150 . 
     As will be noted in  FIG. 1  and  FIG. 3 , the BIST circuit  100  may provide read and write data storage and retrieval addresses to the RAMs  14  thru  16  over address bus  30 . In addition, the BIST  18  may provide preset data to the RAMs  14  thru  16  over data input bus  32  and reads data from the RAMs  14  thru  16  over data bus  36 . As will be noted in  FIG. 3 , the BIST circuit  18  also includes the BIST sequence controller  150 , a data generator  56 , and a comparator  58 . 
     The address generator  52  generates the data storage and retrieval addresses which are conveyed to the RAMs  14  thru  16 . The data generator  56  generates preset data which is written into the RAMs  14  thru  16  during a BIST test of the RAMs  14  thru  16 . The data register  54  receives data read from the RAMs  14  thru  16 . The comparator  58  detects errors in the RAM data storage. More specifically, the comparator compares the data in the data generator  56 , which is the preset data written into the RAMs  14  thru  16 , to the data read from the RAMs  14  thru  16  contained within the data register  54  to detect data storage errors in RAMs  14  thru  16 . 
     In accordance with this embodiment of the present invention, a BIST test of RAMs  14  thru  16  may be enabled first by the issuance of a direct command to the BIST circuit  100  to read through all of the addresses of the RAMs  14  thru  16 . This initial command may be issued through the JTAG controller  12 , a scan chain input signal  62 , or other means. A BIST test is separate and distinct from a diagnostic read. 
     When a RAM error is detected, the read RAM data is conveyed from the data register  54  external to the integrated circuit  10  to enable diagnosis of the data storage error external to the integrated circuit. The read data may be conveyed external to the integrated circuit by various means, including but not limited to, external pin  24  through the scan chain  20  embedded with the diagnostic read circuit or BIST circuit  100 , directly to external pins Jx or DR pin  22 , or internal/external integrated circuit buses. 
     As in the previous embodiment, along with the read data, the addresses used to address the RAMs can also be provided to external pins. The addresses may be provided directly to external pin  22  or through the scan chain  20  to the external pin  24 , or other means such as internal/external integrated circuit buses. 
     The initial diagnostic read command may be invoked when a RAM is determined to have failed. This determination may be based upon parity errors which stop the integrated circuit from processing further data. This may even halt all operation of the integrated circuit. Hence, under such circumstances, RAM tests may be enabled at a leisurely pace by enabling the appropriate scan chains, JTAG controllers, or by generating specific control signals. In other instances where integrated circuit architectures provide continuous data flow, diagnostic read commands may be triggered immediately such as by the generation of the DR enable signals. 
     Although the RAM addresses may be provided to the external pins in response to a detected storage error, this may be unnecessary in some instances. For example, if the address sequences are already known by external diagnostic software, it may be possible to dispense with providing the memory addresses externally of the integrated circuit. 
     When invoking a diagnostic read through a scan chain, the address sequence must be preserved for subsequent reads to ensure complete reading of all bits in the RAM or RAMs. The process of scanning out data through a scan chain destroys the address sequence and all data stored in any registers, latches, or flip-flops. Reconfiguring these storage elements to a scan chain, then transferring data out serially will result in these storage elements being overridden by previous data in the same scan chain. The scan chain will have to be reloaded with the next sequence of addresses to be read from RAMs. An alternative approach is to transfer the diagnostic read data onto a nearby scan chain or JTAG chain while the BIST circuit is cycling through all RAM addresses and data bits.