Patent Publication Number: US-2023154555-A1

Title: Method and apparatus for providing wear leveling

Description:
GOVERNMENT LICENSE RIGHTS 
     This invention was made with Government support under PathForward Project with Lawrence Livermore National Security (Prime Contract No. DE-AC52-07NA27344, Subcontract No. B620717) awarded by the Department of Energy (DOE). The Government has certain rights in this invention. 
    
    
     BACKGROUND OF THE DISCLOSURE 
     Integrated circuits are used in computing devices such as, but not limited to, smart phones, tablets, wearables, laptops, desktops, internet servers, printers, and other devices. Some integrated circuits that include processors such as central processing units (CPUs), graphics processing units (GPUs), or other logic units such as arithmetic logic units (ALUs), and memories such as random access memories (RAMs) and other memory devices employ a network of temperature sensors that are monitored by thermal control logic that may be located on die with the components being monitored or may be off die. Monitoring of the temperatures of various components or integrated circuit die regions allows thermal control logic to change operating frequencies of the processors, or reroute memory mapping in memories to avoid creating hot spots on an integrated circuit. Typically these known systems provide short term based temperature monitoring. For example, integrated circuits may be packaged in any suitable manner including stacking of dies in a common package to form a three dimensional stacked package or may be configured in a two dimensional manner. Known systems attempt to use the temperature sensors to detect hot spots in integrated circuit regions and if the circuit region is a memory device, for example, the thermal control logic may map memory accesses to other memory regions that are not determined to be hot spots. However, this is typically done using short term temperature data which is then reset upon power down or during power reduction conditions. Similarly, the control of processors is also carried out using distributed thermal sensors so that in a multi-core processor, for example, different cores that are detected to be overly hot are controlled by changing frequency operation, or execution threads are moved to cooler cores. However, as with the memory thermal leveling systems, the workload leveling systems also use short term temperature data which is then reset upon power down or is reset in power reduction modes. 
     As such, task executions including memory accesses (read and/or write accesses) as well as thread execution operations in processors, are controlled based on short term thermal temperature information which is typically reset upon an integrated circuit being powered down. However, long-term thermally accelerated faults can be exhibited via several mechanisms such as negative biased temperature instability (NBTI) and electromigration. Where multiple components such as logic or memory dies have thermal coupling, such as when they are integrated in a 3D package or otherwise located within proximity of one another, the hot components may cause long term wear-out for themselves and nearby components. 
     Also in some situations thermal detection may not be a best approach for wear leveling. It would be desirable to have an improved wear spreading mechanism for die regions and/or among dies of integrated circuits. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The disclosure will be more readily understood in view of the following description when accompanied by the below figures and wherein like reference numerals represent like elements, wherein: 
         FIG.  1    is a block diagram illustrating an apparatus that provides thermal wear spreading among a plurality of thermal die regions in accordance with one example set forth in the disclosure; 
         FIG.  2    is a flowchart illustrating a method for providing thermal wear spreading among the plurality of thermal die regions in an integrated circuit in accordance with one example set forth in the disclosure; 
         FIG.  3    is a block diagram illustrating an apparatus that employs thermal wear spreading operation in accordance with one example set forth in the disclosure; 
         FIG.  4    is a flowchart illustrating a method for providing thermal wear spreading in accordance with one example set forth in the disclosure; 
         FIG.  5    is a block diagram illustrating data stored in persistent memory in accordance with one example set forth in the disclosure; 
         FIG.  6    is a block diagram illustrating one example of thermal wear spreading logic in accordance with the disclosure; 
         FIG.  7    is a block diagram illustrating one example of wear spreading logic in accordance with the disclosure; 
         FIG.  8    is a flow chart illustrating one example of a method for controlling wear spreading in accordance with the disclosure; 
         FIG.  9    is a block diagram illustrating data stored in persistent memory in accordance with one example set forth in the disclosure; and 
         FIG.  10    is a block diagram illustrating data stored in persistent memory in accordance with one example set forth in the disclosure. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Exemplary embodiments provide wear spreading among die regions (i.e., one or more circuits) in an integrated circuit or among dies by using operating condition data in addition to or instead of environmental data such as temperature data, from each of a plurality of die regions. Control logic, also referred to as wear spreading logic, produces a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data wherein the operating condition data is based on at least one of the following operating characteristics: frequency of operation of the plurality of die regions, an operating voltage of the plurality of die regions, an activity level of the plurality of die regions, a timing margin of the plurality of die regions and a number of detected faults of the plurality of die regions. The method and apparatus spreads wear among the plurality of same type of die regions by controlling task execution among the plurality of die regions using the die region wear-out data. Task execution includes any operation of a circuit or group of circuits such as non-processor related operations and/or processor and memory operations. 
     In one example, the wear spreading logic stores, in persistent memory, the die region wear-out data, and spreads wear among the plurality of die regions by generating wear-out control data that controls at least one of: thread execution among a plurality of functional units that are processing cores, remapping of memory addresses for a die region of memory and operation of other functional units such as non-processor circuitry. In some embodiments, the wear spreading logic accrues the operating condition data over the life of each respective region of the plurality of regions. 
     In one example, the operating condition data is based more than one operating characteristic and instead is based on a plurality of different operating characteristics, from the group consisting of: the frequency of operation of the plurality of die regions, the operating voltage of the plurality of die regions, temperature data of the plurality of die regions, the activity level of the plurality of die regions, the timing margin of the plurality of die regions and the number of detected faults of the plurality of die regions. In one example, the wear spreading logic combines operating condition data associated with differing types of operating characteristics from each of the plurality of die regions and spreads wear among the plurality of die regions by generating wear-out control data based on the combined operating condition data associated with differing types of operating characteristics of each of the plurality of die regions. 
     In one example, a plurality of operating ranges are used and the die region wear-out data includes data representing a cumulative amount of time each of the plurality of die regions has spent in each of the plurality of operating ranges. The wear spreading logic is further operative to generate the wear-out control data by combining the cumulative amount of time each of the plurality of die regions has spent in each of the plurality of operating ranges. 
     In one example, the wear spreading logic is operative to categorize each of the plurality of die regions into a wear-out level based on the die region wear-out data, order threads in a manner indicative of an amount of wear-out a thread is determined to cause when executing, and assign threads such that a thread causing a lower amount of wear-out is assigned to a die region having a higher wear-out level with respect to another die region. Individual instructions or groups of instructions can be spread if desired. 
     In one example, the wear spreading logic is further operative to determine die region wear-out data by combining die region wear-out data from multiple operating ranges, and spread wear among the plurality of die regions by controlling task execution among the plurality of die regions using the die region wear-out level data. 
     In another embodiment, environmental data is used so that thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies is provided by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory. 
     In one example, an apparatus includes at least one integrated circuit having a plurality of thermal die regions. Temperature sensors produce temperature data associated with the plurality of thermal die regions. Thermal wear spreading logic uses the temperature data to produce die region wear-out data representing a cumulative amount of time each of the plurality of thermal die regions has spent at a temperature level based on the temperature data. The thermal wear spreading logic spreads thermal wear among the plurality of thermal die regions by controlling task execution among the plurality of thermal die regions using the die region wear-out data. 
     In some embodiments, the thermal wear spreading logic stores, in persistent memory, the die region wear-out data and the thermal wear spreading logic spreads thermal wear among the plurality of thermal die regions by generating wear-out control data that controls another or both of thread execution among a plurality of processing cores or remapping of memory addresses for a die region of memory. In one example, the thermal wear spreading logic accrues the temperature data over the life of each respective thermal region of the plurality of thermal regions. 
     In one example, the temperature level includes a plurality of temperature ranges and the die region wear-out data includes data representing a cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges. In one example, the thermal wear spreading logic generates the wear-out control data by combining the cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges. 
     In another example, the thermal wear spreading logic spreads thermal wear among the plurality of thermal die regions based on temperature data that is not accumulated over the life of a respective thermal region and is operative to prioritize the spreading of thermal wear among the plurality of thermal die regions based on temperature data that is not accumulated over the life of a respective thermal region over the spreading of thermal wear among the plurality of thermal die regions using the die region wear-out data. 
     In one example, the thermal wear spreading logic categorizes each of the plurality of die regions into a wear-out level based on the die region wear-out data, orders threads in a manner indicative of an amount of heat a thread is determined to cause when executing, and assigns threads such that a thread causing a lower amount of heat is assigned to a die region having a higher wear-out level with respect to another die region. 
     In one example, the thermal wear spreading logic determines die region wear-out data by combining die region wear-out data from multiple temperature ranges and spreads thermal wear among the plurality of thermal die regions by controlling task execution among the plurality of thermal die regions using the die region wear-out level data. 
     In another example, an apparatus includes at least one integrated circuit package having a plurality of stacked dies each with a plurality of thermal die regions. The apparatus includes temperature sensors that provide temperature data associated with the plurality of thermal die regions. The apparatus includes persistent memory such as non-volatile RAM, a hard drive or other persistent memory. The apparatus also includes the thermal wear spreading logic that uses the temperature data to produce die region wear-out data representing a cumulative amount of time each of the plurality of thermal die regions has spent in each of a plurality of temperature ranges based on the temperature data and spreads thermal wear among the plurality of thermal die regions by controlling task execution among the plurality of thermal die regions using the die region wear-out data. The thermal wear spreading logic stores, in the persistent memory, the die region wear-out data. The thermal wear spreading spreads thermal wear among the plurality of thermal die regions by generating wear-out control data that controls at least one of: thread execution among a plurality of processing cores and remapping of memory addresses for a die region of memory. 
     A method for providing thermal wear spreading among a plurality of thermal die regions in an integrated circuit includes producing, such as by thermal control logic, die region wear-out data representing a cumulative amount of time each of the plurality of thermal die regions has spent at a temperature level based on temperature data from each of the plurality of die regions and spreading thermal wear among the plurality of thermal die regions by controlling task execution among the plurality of thermal die regions using the die region wear-out data. 
     In one example, the method includes storing, in persistent memory, the die region wear-out data and wherein spreading thermal wear among the plurality of thermal die regions includes generating wear-out control data that controls at least one of: thread execution among a plurality of processing cores and remapping of memory addresses for a die region of memory. 
     In one example, the die region wear-out data is based on temperature data accrued over the life of each respective thermal region of the plurality of thermal regions. Also, in one example, the temperature level includes a plurality of temperature ranges and wherein the die region wear-out data includes data representing a cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges. Also, the method includes generating the wear-out control data by combining the cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges. 
     In one example, the method includes prioritizing a short term thermal spreading operation over long term thermal spreading operations. For example, the method includes spreading thermal wear among the plurality of thermal die regions based on temperature data that is not accumulated over the life of a respective thermal region and prioritizing the spreading of thermal wear among the plurality of thermal die regions based on temperature data that is not accumulated over the life of a respective thermal region over the spreading of thermal wear among the plurality of thermal die regions using the die region wear-out data. 
     In one example, the method includes categorizing each of the plurality of die regions into a wear-out level based on the die region wear-out data, and ordering threads in a manner indicative of an amount of heat a thread is determined to cause when executing. The method includes spreading thermal wear among the plurality of thermal die regions using the die region wear-out data by assigning threads such that a thread causing a lower amount of heat is assigned to a die region having a higher wear-out level with respect to another die region. 
     In another example, the method includes determining die region wear-out level data by combining die region wear-out data from multiple temperature ranges and wherein spreading thermal wear among the plurality of thermal die regions includes controlling task execution among the plurality of thermal die regions using the die region wear-out level data. 
       FIG.  1    illustrates an example of an apparatus  100  such as, but not limited to, a server, smart phone, tablet, wearable device, printer, game console, or any other suitable device that employs integrated circuits. In this example, the apparatus includes one or more integrated circuits  102  that include processing cores such as central processing unit (CPU) cores, graphics processing unit (GPU) cores, a combination thereof or any other suitable cores that execute programmable instructions. The integrated circuit may also include arithmetic logic units (ALUs). In addition, the apparatus includes non-persistent memory  104  such as dynamic RAM (DRAM) or any other suitable non-persistent memory which may also be an integrated circuit die which is die stacked with the integrated circuit  102 . The apparatus also includes persistent memory  106  such as non-volatile RAM (NVRAM) that may be implemented as an integrated circuit also stacked with the integrated circuit  102  and  104  or may be a hard drive, or any other persistent memory that stores data when power is removed from the persistent memory. 
     The apparatus  100  also includes thermal wear spreading logic  108  that is implemented as a programmable controller, state machine, or any other suitable logic that may be separate from or integrated with any of the integrated circuits  102 ,  104  and  106 . Each of the integrated circuits  102  and  104  include distributed temperature sensors  109  configured to sense temperature of various die regions as known in the art. The temperature sensors  109  provide temperature data  110  to the thermal wear spreading logic  108 . This may take any suitable form including a push or pull operation, storing the temperature data in registers or memories that is then accessed by the thermal wear spreading logic  108 , or any other suitable technique. 
     The thermal wear spreading logic  108  produces die region wear-out data  112  from the temperature data  110 , representing a cumulative amount of time each of the thermal die regions have spent at a temperature level. For example, the die region wear-out data  112  which in one example is a historical temperature log of the amount of time a thermal die region has spent in one or more different temperature ranges. For example the die region wear-out data  112  shows that a CPU core has spent several weeks or months at a temperature level of 100 degrees Celsius or higher. This die region wear-out data  112  is accumulated and stored in persistent memory  106  so that it is not lost during power downs and is considered long term information that is used to determine whether native biased temperature instability and electromigration is occurring on a per thermal region or per die basis. In one example, the thermal control logic  108  compares the die region wear-out data  112  to die region wear-out threshold data that may be provided by a manufacturer of the die or determined through testing so that if die region wear-out data exceeds the threshold data, the die region is considered to have too high of a wear-out level and spreading from the die region to a cooler region occurs (see e.g.,  FIG.  5   ). 
     In another example, as further described below, die region wear-out data  112  instead of being a historical temperature log for a given die region that represents a cumulative amount of time that a die region has spent at a temperature level, may instead be a summation of the amount of time that a thermal die region has spent at a temperature level where the temperature level is a single temperature range or plurality of ranges (see e.g.,  FIG.  5   ). In one example, each die region is tracked to determine how long it has been operating in a specific temperature range. This data is accumulated from the initial power on of the respective integrated circuit. 
     When an undesirable level of wear-out is detected for a thermal die region, the thermal control logic  108  generates wear-out control data  114  to spread thermal wear among die regions (including between dies). The wear-out control data  114  is used to spread thermal wear among the plurality of thermal die regions by (including between dies), for example, controlling task execution among the plurality of die regions based on the die region wear-out data  112 . The wear-out control data  114  causes, for example, a different processing core to execute a given thread such as one that is cooler (i.e., less wear-out) than another processing core. In another example, another task execution that is carried out in response to the wear-out control data  114  is a memory access remapping so that read or write operations are moved to different memory locations either across integrated circuits or within different memory banks of a same die memory. 
     Referring also to  FIG.  2   , a method for providing thermal wear spreading among the plurality of thermal die regions is illustrated. The method is carried out by the thermal wear spreading logic  108  in one example. As shown in block  200 , the method begins by, for example, accumulating temperature data  110  from multiple die regions from one or more dies using temperature sensors  109 . As shown in block  204 , the method includes producing die region wear-out data  112 . The die region wear-out data  112  represents a cumulative amount of time that each of the plurality of thermal die regions has spent at a relevant temperature level, based on the temperature data  110 . In one example, the die region wear-out data  112  includes a historical temperature log for each thermal die region that is monitored, or a subset thereof. In one example the temperature data  110  is accrued over the life of each respective thermal region of the plurality of thermal regions. For example, the die region wear-out data  112  is maintained in the persistent memory  106  for multiple thermal die regions even after a power shut off condition corresponding to those thermal die regions has occurred. As such, if a die that includes CPU cores, GPU cores or other logic units have been powered down, the die region wear-out data  112  that has been recorded is maintained in the persistent memory  106 . This data is accumulated over the life of the die or integrated circuit so that it can be determined when to replace a particular die or integrated circuit before it fails. 
     In one example, the temperature data  110  that is used is based on a threshold such that the temperature level can be a predetermined level such as 100 degrees Celsius or any other suitable level above which the thermal wear spreading logic  108  records the amount of time that a thermal die region spends at or above the temperature level. As used herein, temperature level also includes a single temperature range, multiple temperature ranges or a single temperature if desired. In another example, the die region wear-out data  112  is calculated and stored as an average temperature that is measured from the temperature data  110  over a period of time, so the thermal wear spreading logic  108 , determines how long on average a particular thermal die region has spent at (which includes above or below a threshold) a particular temperature level, including, for example, within one or more temperature ranges or beyond a temperature threshold. 
     As shown in block  206 , the method includes spreading thermal wear among the plurality of thermal die regions by controlling task execution among the plurality of thermal die regions using the die region wear-out data. Task execution includes any suitable operation that reduces wear-out for a die or die region and in one example includes changing cores or logic units that executes threads, changing memory locations that are used, changing an operating frequency of a core or logic unit, changing an operating voltage of a core, memory or logic unit, or any other suitable operation that reduces wear-out. The method, in one example also includes storing, in the persistent memory  106 , the die region wear-out data  112  so that it can be accumulated over the life of a particular die or thermal die region. The method also includes spreading of the thermal wear among the plurality of thermal die regions by generating the wear-out control data  114  to control thread execution among the plurality of processing cores, remapping of memory addresses for a die region of memory, or any combination thereof or other operations. The method repeats as shown in block  208  as needed to continually monitor for wear-out conditions. 
     Referring to  FIGS.  3 - 5   , an example of the apparatus  100  includes a first processor  300 , such as a CPU die, a second processor  302  such as a GPU die, a memory die  304  that includes the non-persistent memory. It will also be recognized that the various operations may be combined in a single die or the apparatus may include other dies which are in a 3D stacked architecture or in any other suitable format. The CPU die includes a plurality of logic units  306  such as a plurality of CPU cores. Similarly, the GPU die includes a plurality of logic units  308  including GPU cores. A thread scheduler  310  routes threads to the various CPU cores and thread scheduler  312  routes threads to the various GPU cores. As used herein a processor is logic that executes executable instructions including a core. Temperature data  110  from distributed temperature sensors  109  on the various CPU cores, GPU cores and thermal die memory regions  104  are provided to the thermal control logic  108  as previously illustrated in  FIG.  1   . The dies  300 ,  302  and  304  are considered integrated circuits each having a plurality of thermal die regions. Temperature sensors  109  are coupled to the plurality of thermal die regions, as known in the art, and provide temperature data  110  associated with the plurality of die regions. The thermal wear spreading logic  108  produces die region wear-out data  112  that is stored in the persistent memory  106 . 
     For example, when the thermal wear spreading logic  108  determines that a particular thermal die region has been operating for the period of time at a temperature level that is beyond a die region wear-out threshold, the thermal wear spreading logic  108  issues the wear-out control data  114  to control the appropriate task operation to spread thermal wear to other thermal die regions that can accommodate the task. By way of example, the wear-out control data  114  instructs a thread scheduler ( 310  or  312 ) of a processor  306  or  308  to route threads from one processing core that is beyond a desired amount of time at a temperature level to a core that has less wear-out (a cooler temperature profile). It will be recognized that the thread schedulers and thermal control logic  108  can be implemented as part of an operating system or other software executing on one or more processors. 
     If the task relates to a memory access task such as a write operation to memory, in another example, the wear-out control data  114  is communicated to a memory controller  309  which remaps the memory addresses to a memory region having less wear-out compared to the region determined to have an undesirable amount of wear-out. The thermal control logic  108  or memory controller  309  employs a data remap table  320  or software page tables to remap memory accesses to different regions of memory that have a lower amount of determined wear-out level to spread the thermal wear to die regions that have a lower amount of die region wear-out. It will be recognized that override options may also be desirable to override a thermal wear leveling controller&#39;s execution unit for certain threads. For example, it may be more important for the system to be able to execute a given thread even if the wear-out level is at a “high” level. The method spreads out thermal wear among differing dies in a stacked arrangement or within a die as desired. 
     Stated another way, the thermal control logic  108  issues the wear-out control data  114  to the memory controller  309  which causes the address remap operation  320  to remap memory addresses to cooler memory banks that have a lower wear-out level. The thermal control logic  108  issues the wear-out control data  114  to the appropriate thread scheduler  310  or  312  when threads need to be rescheduled to processing cores that have a lower wear-out level compared to a processing core that has a high wear-out level as determined by the thermal control logic  108  using the die region wear-out data  112 . 
     Referring also to  FIG.  5   , in one example, the temperature level  501  includes a plurality of temperature ranges as opposed to, for example, a single range or a particular temperature. For example, the thermal wear spreading logic  108  tracks how long (e.g., days, weeks, months) a particular die region has spent at a temperature level  501 , in this example, in a temperature range  502 , for example, of 20-40 degrees Celsius, how long that same die region has spent in the temperature range  504  of 41-80 degrees Celsius and how long the thermal die region spent over its life in the temperature range  506  of 81-100 degrees Celsius. However, any suitable number of ranges and temperature ranges may be employed. The thermal wear spreading logic  108  then combines the die region wear-out data  112  corresponding to each of the temperature ranges for a particular die region identified by die region identification data  508  and hence generates wear-out control data  114  by combining a cumulative amount of time each of the plurality of thermal die regions has spent in each of the plurality of temperature ranges to produce wear-out level data  601 . This is generally represented by the equation below where (w) represents weighting if desired: 
       Wear-out level data_ Reg n =Σ(Range  A )( w 1)+(Range  B )( w 2)+(Range  C )( w 3)
 
     and comparing the combined amount to the wear-out threshold data  500 . In another example, where the die region wear-out data  112  is a thermal log of cumulative temperature changes over different times (different time stamps), the thermal control logic  108  instead calculates a rate of change of temperature to determine whether wear-out exists. For example when the rate of temperature change of a die region exceeds a rate of change wear-out threshold, the thermal control logic  108  controls task execution to avoid the thermal die region that has exhibited an abnormal rate of change of temperature. 
     The disclosed wear-out based thermal spreading technique described herein can be combined with conventional short term thermal spreading operations—those that do not accumulate temperature data over life of thermal regions to provide a more robust thermal spreading system. For example, as shown in  FIG.  4   , a method of providing thermal wear spreading among the plurality of thermal die regions begins in block  400  and in block  402 , the thermal wear spreading logic  108  determines if a conventional short term thermal spreading operation should override thermal wear spreading based on wear-out data. For example, if a thermal die region is exceeding its critical temperature, the short term thermal spreading operation in the logic  108  will take appropriate action to avoid the overheating of the thermal region, such as spreading threads if the thermal die region is in a processing core or remap memory addresses to a cooler memory region if a particular memory bank is getting too hot. In this example, the wear-out control data  114  does not have to be issued since the integrated circuit may be operating under conditions in the short term that need resolution immediately. As such, the thermal wear spreading logic  108  may use a conventional thermal spreading operation to spread thermal wear among the plurality of thermal die regions based on temperature data that is not accumulated over the life of the respective thermal region. 
     As shown in block  404 , if no thermal spreading is required using conventional short term based thermal spreading techniques, the method includes producing die region wear-out data per die region that represents a cumulative amount of time that each die region has spent at a temperature level. For purposes of example only, the die region will, by way of example, be a processing core and spreading the thermal wear will be the controlling of thread execution. As noted above, the die region wear-out data  112  in one example is a historical log that represents a cumulative amount of time each of a plurality of die regions has spent at a temperature level wherein a temperature level may be at a single temperature, a single temperature range, a plurality of ranges of temperatures or any other suitable designation as desired. 
     The method includes categorizing each of the plurality of die regions into a wear-out level, such as a high wear-out level, medium wear-out level or low wear-out level or any other suitable categories, based on the die region wear-out data  112 . For example, as shown in block  406 , categorizing each die region into a wear-out level includes in one example, comparing the average temperature between CPU cores on a CPU die and determining the relative temperature difference among the cores. For example, when an imbalance is identified such as when one processing core is 10% more worn than another core, it is categorized as a high wear-out core such that future threads are routed to other cores until their wear-out level increases to the same level. As another example, each die region may be assigned to a high, medium, low temperature category such that the cumulative amount of time that each thermal die region spends at a high temperature, medium temperature and low temperature is recorded. When a die region is determined to have spent an undesirable time at high temperature it is designated as a highly worn region where after threads are assigned through other less worn cores. Any other suitable techniques to determine levels of wear-out may also be utilized. 
     As shown in block  408 , the method also includes ordering threads in a manner indicative of an amount of heat a thread is determined to cause when executing. For example, as noted in block  410 , ordering of the threads include measuring processing cores while running threads to see how hot cores get. The thermal control logic  108 , an operating system, application or other software may also perform the operation. As an alternative, an application provides hints to the thermal control logic  108  and/or operating system or other component which can indicate that a particular application has code that causes a particular core to run at a high temperature. Other techniques may include using performance counter information or other measurements to determine the hottest and coldest logic units or memory regions, as desired. 
     As shown in block  412 , the method includes sending the thread that causes the hottest temperature to a logic unit (e.g., core) having a lowest wear-out temperature level (considered a low wear-out category) and assigning threads such that the thread causing the lower amount of heat is assigned to a die region have a higher wear-out level with respect to another die region. Likewise, thermal spreading will include using the die wear-out data to assign threads such that the thread causing a high amount of heat is assigned to a die region having a lower wear-out level with respect to another die region. 
     As shown in block  414 , the method includes determining whether it is time to reevaluate the historical temperature log data which is the die region wear-out data  112  in this example. For example, temperature data is updated on a periodic basis so that once threads are reassigned to regions that have less wear-out, it may be necessary to reevaluate the die region wear-out data  112  that is being accumulated to determine whether reassignment is necessary for other regions or the current die region. 
       FIG.  6    is a block diagram illustrating one example of the thermal control logic  108 . As noted above, the thermal control logic  108  in one example is a suitably programmed processor, however it may also be a state machine or any other suitable logic and may be centralized or distributed on the die for which it is controlling thermal wear or may control thermal wear among other dies. In this example, the thermal control logic  108  includes wear-out determination logic  600 , and a comparator  602 . The wear-out determination logic  600  receives the temperature data  110  and using the temperature data, produces the die region wear-out data representing a cumulative amount of time each of the plurality of thermal die regions has spent at a temperature level. Counters are used to accumulate how long each die region spreads in a particular temperature range. As noted above with respect to  FIG.  5   , in one example the wear-out determination logic  108  generates the wear-out level data  601  per die region. The comparator  602  receives the wear-out level data  601 . The wear-out determination logic  600  also causes the die region wear-out threshold data  500  for the particular die region to be provided to the comparator  602  using the region ID data  508 . The comparator  602  compares the wear-out level data  601  to the die region wear-out threshold data  500 . In one example, if the wear-out level data  601  exceeds the die region threshold data  500 , then the comparator  602  generates the wear-out control data  114  to cause the spreading of thermal wear among the plurality of thermal die regions as previously noted above. 
     The above apparatus and method provide a mechanism to measure, monitor and control thermal-induced wear-out, where the control mechanisms spread out the thermal wear to multiple components and if desired, among all areas of all components where possible, attempting to maximize the overall system lifetime before integrated circuits or packages need to be replaced. One of the many advantages that results includes increasing the life of independent devices such as memory stacked vertically above a GPU die. For example, the above operations can increase the lifetime of packages that tightly integrate memory with CPUs, GPUs, APUs or other processing units. Data centers with super computers will have improved lifetime of integrated circuits. Better energy efficiency and performance can be achieved without a negative effect of increased temperatures over long periods of time. 
     In one example, for each thermal die region, a persistent memory, such as flash, NVRAM, hard disk, PCM or other NVM, store the amount of time each die region spends in a desired temperature range. This information is used by thermal control logic  108  for thermal wear leveling. Thermal wear leveling spreads out a thermal profile of each die region including over multiple dies if desired, over time such as on the order of weeks or other suitable time frame. Monitoring and logging of time spent at each temperature is recorded at a much finer granularity, if desired especially if integrated circuit die activity creates transient hot spots. 
     When making task schedule decisions, the thermal control logic  108  causes a scheduling control mechanism such as an operating system, thread scheduler, instruction scheduler or other mechanism to attempt to schedule the most power consuming task to the least thermally worn out die region (such as memory, ALU, core or other die region). Over time, the scheduling attempts to equal wear-out in each region. This serves to maximize the time before failure of any single part of the system, thereby maximizing a lifetime of the integrated circuit, stacked dies, or IC package. 
     It is contemplated that the components that are thermally coupled may have separate thermal controllers. For example, a GPU die vertically stacked with a memory die may have its own thermal controller, a memory such as DRAM or other memory may have its own thermal controller and a CPU die vertically stacked over memory may have its own memory controller. As such, a distributed thermal controlled system is contemplated as well as a centralized thermal control system. Distributed systems can negotiate management of activities on each die so that, for example, operations slated for one die may be scheduled to operate on another die that has less wear-out. It is also contemplated that certain components may have more control over the control of dynamic thermal profiling and would be the main decision makers. For example, in a GPU die with vertical memory die stacking, the GPU would be the main decision maker, but not exclusive decision maker if desired, as the memory die could rearrange its configuration as well using die memory mapping. Other arrangements will also be recognized by those of ordinary skill in the art. 
     In other examples, there may be two or more dies, such as a GPU die over another GPU die that have similar thermal profile control capabilities, that negotiate which die reduces heat generation in certain regions and that die is used to level out the thermal wear. A protocol for exchanging of thermal and performance cost information between coupled dies may also be employed. Thermal profile information may be combined with fault detection information in order to anticipate the occurrence of hard failures. For example, the thermal control logic is configured to anticipate when a fault will occur for one of the regions or dies using error rates reported from hardware and detected using error detection codes (EDC) or logic timing failures using timing error detection using ring oscillators. If the error rates or logic timing delays exceed a threshold, thermal wear mitigation actions may be triggered. The profile information is related to local or system level scheduling entities in order to avoid system downtime. 
     Spreading of the thermal wear among a plurality of thermal die regions may be done in a hardware configuration for example, such as a CPU or GPU instruction scheduler choosing which compute units to use for particular instructions or work groups by selecting a processing core and assigning threads to the core such that a thread causing the lower amount of heat is assigned to a die region having a higher wear-out level with respect to another die region. In another example, an operating system may use its thread scheduler to decide which compute units to map the threads to in a similar manner. 
     In another example, electrical wear is detected and used as a basis for wear leveling operations. Instead of employing only environmental data such as temperature data which indicates an environmental condition of a die region, operating condition data taken from one or more die regions is used. As with the above examples, die regions include one or more circuits (i.e., blocks) including any suitable circuits including functional units, processor cores, subsystems therein or any other desired circuit. 
     As shown in  FIG.  7   , an apparatus  700  that employs operating condition data  702  is similar to that shown in  FIG.  1   . However, instead of, or in addition to temperature data, a plurality of sensors  703  provides sensed operating condition data  702  to wear spreading logic  704 . The wear spreading logic  704  not only operates in a similar manner as wear spreading logic  108  when using temperature data only, but can operate in a different or additional manner as further described below. In a similar manner as noted above, the wear spreading logic  704  produces die region wear-out data  706  that represents a cumulative amount of time each of the plurality of die regions has spent at an operating condition, also referred to as an operating point, based on operating condition data  702  from each of the plurality of die regions. Although not shown, the temperature data  110  may also be used in addition to the operating condition data  702  such that the die region wear-out data is based not only on operating condition data  702  but also on temperature data  110  as previously described above. 
     In this example, the operating condition data  702  is based on at least one of the following operating characteristics of the plurality of die regions: frequency of operations of the plurality of die regions, an operating voltage of the plurality of die regions, an activity level of the plurality of die regions, a timing margin of the plurality of die regions, and a number of detected faults of the plurality of die regions. The control logic  704  spreads wear among the plurality of die regions of the same type by controlling task execution as previously described above among the plurality of die regions using the die region wear-out data  706 . 
     In a similar manner, as noted above, the die region wear-out data  706  is stored in persistent memory  106 . The spreading of the wear among the plurality of die regions includes generating wear-out control data  708  that controls at least one of thread execution among the plurality of processing cores, remapping of memory addresses for a die region of memory and/or operation of other functional units (i.e., circuits) in the integrated circuit. In one example, the die region wear-out data  706  is based on operating condition data associated with each of the plurality of die regions accrued over the life of each respective region in the plurality of regions in a similar manner as noted above. 
     An operating condition is, in one example, the operating point of the circuit when the sensors acquire the sensed data. The operating condition data is accumulated over time such as by summing data over multiple operating points (e.g., sensed samples at different times). In another example, accumulating operating condition data is done by accumulating data indicating whether a die region is operating above or below a particular frequency or voltage or within a range of frequencies or voltages, at a plurality of operating ranges different activity levels, or any other suitable operating point or range in a similar manner as that described with respect to  FIG.  5   . For example, the die region wear-out data  706  can be accumulated for different frequency ranges, activity levels and/or voltage ranges as further described with respect to  FIG.  10   . 
     In another example, instead of employing a single operating characteristic such as only frequency or voltage, a combination of operating characteristic data is used to produce die region wear-out data. For example, the combination of frequency and voltage is employed, or the combination of frequency, voltage and temperature, or any other suitable combination of operating characteristics and environmental data may be employed. In one example, the operating characteristics that are combined are from the group consisting of a plurality of: the frequency of operation of the plurality of die regions, the operating voltage of the plurality of die regions, the activity level of the plurality of die regions, temperature level of the plurality of die regions, the timing margin of the plurality of die regions and a number of detected faults of the plurality of die regions. Timing margin is defined as the amount of time that a signal arrives at a destination circuit before the associated clock edge arrives, i.e. it is a measure of how close the clock is to “overtaking” the signal (which would result in possibly wrong data being used at the destination). Activity level is defined as the fraction of time that a circuit or block is used. i.e. if a block is being used for only 1 out of every 4 cycles on average, the activity level is 25%. Detected faults are errors such as soft errors that can occur in data storage circuits such as when a state change occurs by itself (without an intended cause). 
       FIG.  8    illustrates a method of operation carried out, for example, by the control logic  704 . As illustrated, the method provides wear spreading among the plurality of die regions in an integrated circuit and starts in block  800 . As shown in block  804 , the method includes producing die region wear-out data representing a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data from each of the plurality of die regions. For example, the amount of time that a particular die region, as evidenced by the amount of time a particular circuit within the die region has been operating at sensed levels is used and/or above a particular frequency, voltage, activity level or other operating characteristic or within a range of voltage frequencies or activity levels is recorded in persistent memory. The operating condition data is based on operating characteristics of the die region and in particular operating characteristics of the circuits of the die region at issue such as, but not limited to, the frequency of operation of the circuits in the particular die regions, an operating voltage of the circuits of the plurality of the die regions, an activity level of the circuits in the die regions, a timing margin of the plurality of the circuits in the die regions, and a number of detected faults of the circuits in the monitored die regions. As shown in block  806 , the method includes spreading wear among the plurality of die regions, namely spreading wear among the same type of circuits from the differing die regions, by controlling task execution among the plurality of die regions using the die region wear-out data. As shown in block  808 , the method can continue to accumulate die region wear-out data over the life of the integrated circuit or circuits and continue to spread wear-out as needed. 
       FIG.  9    is a modified version of  FIG.  3    illustrating the use of operating condition data  702 . However, it will be recognized that temperature data  110  can also be combined with the operating condition data as further set forth below. In one example, the control logic  704  combines die region wear-out data  706  associated with the differing types of operating condition data such as combining wear-out data associated with the frequency of operation of a die region with wear-out data based on the operating voltage of the same die region, for each of a plurality of same type die regions. 
     As illustrated by the equation below, the wear-out level of a die region such as a particular block or circuit is, in one example, considered to be a function of the frequency of operation of the block, the voltage applied to the block and the sensed temperature of the block and any other environmental data or operating condition data as desired. Where the circuit includes multiple blocks, the wear-out data from each block is summed to get a combined wear-out level on a circuit basis. 
     
       
         
           
             
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     In one example, if desired, the die region wear-out data  706  which is the accumulated time that a die region has spent at a particular operating condition, within a particular range, or other parameter based on operating condition data, is weighted, and the differing types of condition data with associated weights are summed to get wear-out data for a particular die region which includes on a per block level or multiple block levels if desired. 
     For example the wear-out data in one example for a given die region and time period using frequency and voltage is represented as Equation: Wear_during_time_period=voltage*0.2+frequency*0.4, where 0.2 and 0.4 are weighting factors. These values are accumulated over time (such as by simple summation) to generate the wear level of the die region. Wear levels are compared for the same type of die regions (e.g., circuit in the die regions) and the die region with the lower wear level is the one that has tasks added to it from the die region having the higher wear level. 
     In one example, the control logic  706  spreads wear among the plurality of same type of die regions by generating wear-out control data  708  based on wear-out data that is a combination of operating condition data (and environmental data if desired) associated with differing types of operating characteristics from each of the plurality of die regions. For example, as shown by the above Equation, differing types of operating condition data such as that associated with frequency and voltage are used for the decision as to whether too much wear is being detected for a given die region. In addition, if desired, environmental data such as temperature data is also combined (and weighted if desired) so that the wear-out control data  708  is based on a combination of sensor data associated with the frequency, voltage and temperature of the die regions being monitored. 
       FIG.  10    is another embodiment where wear-out data  706  from multiple operating ranges is used to determine the wear-out level data. In this example, instead of using temperature ranges as illustrated above with respect to  FIG.  5   , operating condition data  702  such as voltage ranges, differing frequency ranges, different activity level ranges, different timing margin levels or ranges of detected faults of the plurality of die regions are employed or any other suitable operating characteristic of the circuit or circuits associated with the die region. 
     In this example, voltage ranges are shown, however any suitable ranges for any of the operating characteristics may be employed. In a similar manner as previously described, there is region wear-out threshold data  500  associated with each region which has associated region ID data  508 . The threshold data  500  is determined empirically through testing or produced by a manufacturer through suitable modeling. However, instead of temperature ranges, voltage range  1000  is shown, a second voltage range  1002  is shown and a third voltage range  1003  is shown. A voltage sensor associated with each die region or circuit or group of circuits within the die region provides the operating condition data, in this case voltage data. Other types of sensors  703  include frequency detection sensors, activity level sensors such as counters that are maintained by a driver, or other process that determines the amount of activity that a given circuit is processing, such as the number of memory reads and writes in a period of time, the number of instructions executed in a period of time, or any other suitable indicator of activity for a die region and in particular, the one or more circuits within the die region. In addition, the timing margin of the die region can also be determined using conventional techniques, as well as a number of detected faults associated with a given die region. Differing ranges for each of the operating characteristics are employed in this example. As previously described, the die region wear-out level data is determined by combining the die region wear-out data  706  from the multiple operating ranges  1000 ,  1002  and  1003 . Spreading wear among the plurality of die regions including controlling task execution among the plurality of die regions using the die region wear-out level data. The region wear-out threshold data  500  is employed in the same manner as previously described above including the description with respect to  FIG.  6   . 
     As such, as described herein, at least one integrated circuit has a plurality of die regions. However, the die regions may be located in different integrated circuits. Wear spreading is controlled so that die regions having the same circuit types are interchanged so that die regions having the same type of circuits that have a low level of wear are assigned additional tasks away from the same type of circuit that is experiencing a high level of wear. In one example, when comparing two die regions having the same circuit types, whichever die region has the lower wear-out level will be assigned a task from the other die region having a higher wear-out level. However, any suitable strategy may be employed. 
     The electrical operating condition sensors  703  that sense, for example, voltage level, frequencies of operation, activity levels, timing margins, fault levels or other operating characteristics are employed in addition to or instead of environmental sensors such as temperature sensors  109 . Wear spreading logic  704  receives the operating condition data  702  from the respective sensors and produces die region wear-out data  706 . The wear spreading logic  704  is also referred to as the control logic. 
     Examples of wear leveling control mechanisms include, for example, hardware where a hardware instruction scheduler chooses which compute units to issue instructions for work groups to, software such as an operating system that decides which compute units to map threads to, data migration logic that decides to migrate data closer to the chosen compute units in order to maintain performance and minimize latency. This is done via the hardware data remap table or software page tables as noted above. In addition, pinning of threads to data paths may be employed for example an override option is provided to override the wear leveling controller&#39;s execution unit application for certain threads if desired. 
     Among other advantages, employing die region wear-out data that represents a cumulative amount of time each of a plurality of die regions has spent at an operating condition based on operating condition data, provides additional important criteria from which to decide whether spreading wear among a plurality of die regions should be carried out. In addition, combining operating condition data associated with differing types of operating characteristics from each of the plurality of die regions can provide improved detection and decision making since additional data such as the combination of frequency, temperature and voltage information can provide more accurate wear decisions. In addition or alternatively, only die region wear-out data based on operating characteristics may be employed. 
     The above detailed description and the examples described therein have been presented for the purposes of illustration and description only and not for limitation. For example, the operations described may be done in any suitable manner. It is therefore contemplated that the present embodiments cover any and all modifications, variations or equivalents that fall within the scope of the basic underlying principles disclosed above and claimed herein. Furthermore, while the above description describes hardware in the form of a processor executing code, hardware in the form of a state machine or dedicated logic capable of producing the same effect, other structures are also contemplated.