Patent Publication Number: US-11658110-B2

Title: Semiconductor device and method for manufacturing the semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-029695, filed Feb. 25, 2020, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the semiconductor device. 
     BACKGROUND 
     When a via plug is disposed on a metal interconnect, the metal interconnect sometimes deteriorates due to the influence of the via plug. Such a deterioration in the metal interconnect needs to be prevented. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
         FIG.  1 A  and  FIG.  1 B  are cross-sectional views showing the structure of a semiconductor device according to a first embodiment. 
         FIG.  2 A  and  FIG.  2 B  are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. 
         FIG.  3 A  and  FIG.  3 B  are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. 
         FIG.  4 A  and  FIG.  4 B  are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. 
         FIG.  5 A  and  FIG.  5 B  are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. 
         FIG.  6    is a cross-sectional view showing an example of structure of the semiconductor device according to the first embodiment. 
         FIG.  7    is a cross-sectional view showing another example of the structure of the semiconductor device according to the first embodiment. 
         FIG.  8    is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. 
         FIG.  9    is a cross-sectional view showing the structure of a columnar portion according to the second embodiment. 
         FIG.  10    is a cross-sectional view illustrating a method for manufacturing the semiconductor device according to the second embodiment. 
         FIG.  11 A  and  FIG.  11 B  are cross-sectional views showing an example of a structure of the semiconductor device according to the second embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments provide a semiconductor device which can prevent a deterioration in an interconnect due to the influence of a plug, and a method for manufacturing the semiconductor device. 
     In general, according to one embodiment, a semiconductor device may include an interconnect including a first layer, and a second layer provided on the first layer and including copper. The device may also include a plug provided on the interconnect and including a third layer including titanium and nitrogen, and a fourth layer provided on the third layer and including tungsten. In some embodiments, the chlorine concentration in the third layer is not more than 5.0×10 21  atoms/cm 3  (or is less than or equal to 5.0×10 21  atoms/cm 3 ), and the oxygen concentration at the interface between the third layer and the fourth layer is not more than 5.0×10 21  atoms/cm 3  (or is less than or equal to 5.0×10 21  atoms/cm 3 ). 
     Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In  FIG.  1    through  FIG.  11   , the same symbols are used for the same or similar components or elements, and a duplicate description thereof is omitted. 
     First Embodiment 
       FIG.  1 A  and  FIG.  1 B  are cross-sectional views showing the structure of a semiconductor device according to a first embodiment. 
     As shown in  FIG.  1 A or  1 B , the semiconductor device of this embodiment may include a substrate  1 , an interlayer insulating film  2 , a plurality of interconnects  3 , an interlayer insulating film  4 , an interlayer insulating film  5 , and a via plug  6 . Each interconnect  3  includes a barrier metal layer  3   a , which is an example of a first layer, and an interconnect material layer  3   b , which is an example of a second layer. The via plug  6  includes a barrier metal layer  6   a , which is an example of a third layer, and a plug material layer  6   b , which is an example of a fourth layer. 
       FIG.  1 A  illustrates a case where the via plug  6  is formed on the interconnect  3  without any misalignment between them, while  FIG.  1 B  illustrates a case where the via plug  6  is formed on the interconnect  3  with some misalignment between them. Hereinafter, the structure of the semiconductor device of this embodiment will be described mainly with reference to  FIG.  1 A  and sometimes also to  FIG.  1 B . 
     The substrate  1  is, for example, a semiconductor substrate such as a silicon (Si) substrate.  FIG.  1 A  shows an X direction and a Y direction which are parallel to the surface of the substrate  1  and perpendicular to each other, and a Z direction perpendicular to the surface of the substrate  1 . In this embodiment, a +Z direction is treated as an upward direction, and a −Z direction as a downward direction. The −Z direction may or may not coincide with the direction of gravitational force. 
     The interlayer insulating film  2  is formed on the substrate  1 . The interlayer insulating film  2  may be formed either directly or via another layer on the substrate  1 . The interlayer insulating film  2  is, for example, a silicon oxide film (SiO 2  film). 
     The plurality of interconnects  3  are formed in the interlayer insulating film  2 , and provided in the same interconnect layer.  FIG.  1 A  illustrates three interconnects  3  as an example. The interconnects  3  extend in the Y direction, and are arranged side-by-side in the X direction. The interconnects  3  may be formed, for example, by forming interconnect trenches in the interlayer insulating film  2 , and sequentially forming the barrier metal layer  3   a  and the interconnect material layer  3   b  in the interconnect trenches to fill the interconnect trenches with the layers. Accordingly, the barrier metal layer  3   a  of  FIG.  1 A  faces the side surface and the bottom surface of the interconnect material layer  3   b . The barrier metal layer  3   a  is, for example, a metal film including titanium (Ti), and is a Ti film in the illustrated embodiment. The interconnect material layer  3   b  is, for example, a metal film including copper (Cu), and is a Cu film in the illustrated embodiment. The barrier metal layer  3   a  may be another metal film including titanium, or a metal film containing no titanium. Examples of such a barrier metal layer  3   a  include a TiN (titanium nitride) film, a Ta (tantalum) film, and/or a TaN (tantalum nitride) film. 
     The interlayer insulating film  4  and the interlayer insulating film  5  are formed in this order on the interlayer insulating film  2  and on the interconnects  3 . The interlayer insulating film  4  is, for example, a silicon carbonitride (SiCN) film. The interlayer insulating film  5  is, for example, a silicon oxide film. 
     The via plug  6  is formed in the interlayer insulating films  4  and  5 , and is provided on one of the interconnects  3 .  FIG.  1 A  illustrates a case where the via plug  6  is provided on the central interconnect  3  of the three interconnects  3 . The via plug  6  may be formed, for example, by forming a via hole on the interconnect  3  and in the interlayer insulating films  4  and  5 , and sequentially forming the barrier metal layer  6   a  and the plug material layer  6   b  in the via hole to fill the via hole with the layers. Accordingly, the barrier metal layer  6   a  of  FIG.  1 A  faces the side surface and the bottom surface of the plug material layer  6   b . The barrier metal layer  6   a  is, for example, a metal film including titanium (Ti), and is a TiN film in the illustrated embodiment. The plug material layer  6   b  is, for example, a metal film including tungsten (W), and is a W film in the illustrated embodiment. The via plug  6  of this embodiment has, for example, a circular planar shape. 
     The via plug  6  of  FIG.  1 A  is in contact with the upper surface of the interconnect  3 . On the other hand, the via plug  6  of  FIG.  1 B  is in contact with the upper surface and the side surface of the interconnect  3 . The via plugs  6  are both electrically connected to the interconnect  3 . 
     Details of the via plug  6  of this embodiment will be further described with reference to  FIG.  1 A . 
     The via plug  6  of this embodiment contains chlorine (Cl) in the barrier metal layer  6   a , and contains oxygen (O) in the vicinity of the interface between the barrier metal layer  6   a  and the plug material layer  6   b . For example, when TiCl 4  gas is used upon the formation of the barrier metal layer  6   a , chlorine will enter the barrier metal layer  6   a . On the other hand, during the formation of the via plug  6  in a chamber, oxygen remaining in the chamber adheres to the surface of the barrier metal layer  6   a , and the oxygen will enter the vicinity of the interface between the barrier metal layer  6   a  and the plug material layer  6   b . Chlorine and oxygen may be present in the via plug  6  from other causes. 
     However, the chlorine and oxygen in the via plug  6  may react with the copper of the interconnect material layer  3   b , causing a deterioration in the interconnect material layer  3   b . In particular, corrosion of the copper of the interconnect material layer  3   b  may occur, causing a defect in the interconnect  3 . 
     In view of the above, the via plug  6  of this embodiment is formed such that the chlorine concentration in the barrier metal layer  6   a  is not more than 5.0×10 21  atoms/cm 3  (or is less than or equal to 5.0×10 21  atoms/cm 3 ), and the oxygen concentration at the interface between the barrier metal layer  6   a  and the plug material layer  6   b  is not more than 5.0×10 21  atoms/cm 3  (or is less than or equal to 5.0×10 21  atoms/cm 3 ). This makes it possible to prevent copper and oxygen in the via plug  6  from deteriorating the interconnect material layer  3   b.    
     Experiments revealed that a high chlorine concentration in the barrier metal layer  6   a  caused a phenomenon of disappearance of the interconnect material layer  3   b  due to copper corrosion and a phenomenon of segregation of chlorine at the bottom of the interconnect material layer  3   b . Experiments also revealed that these phenomena did not substantially occur when the chlorine concentration in the barrier metal layer  6   a  was decreased to not more than 5.0×10 21  atoms/cm 3  (or decreased to less than or equal to 5.0×10 21  atoms/cm 3 ). Therefore, in this embodiment, the chlorine concentration in the barrier metal layer  6   a  is set to be not more than 5.0×10 21  atoms/cm 3  (or set to be less than or equal to 5.0×10 21  atoms/cm 3 ). 
     If a chamber for the formation of the via plug  6  is open to the atmosphere between the step of forming the barrier metal layer  6   a  and the step of forming the plug material layer  6   b , then the oxygen concentration at the interface between the barrier metal layer  6   a  and the plug material layer  6   b  will increase. This is because air and moisture enter the chamber by opening to the atmosphere. Experiments revealed that the above-described phenomena occurred when such opening to the atmosphere was performed and then the plug material layer  6   b  was formed. Experiments also revealed that when the plug material layer  6   b  was formed without performing such opening to the atmosphere, the oxygen concentration in the vicinity of the interface between the barrier metal layer  6   a  and the plug material layer  6   b  decreased to not more than 5.0×10 21  atoms/cm 3  (or decreased to less than or equal to 5.0×10 21  atoms/cm 3 ), and the above-described phenomena did not substantially occur. Therefore, in this embodiment, the oxygen concentration at the interface between the barrier metal layer  6   a  and the plug material layer  6   b  is set to be not more than 5.0×10 21  atoms/cm 3  (or set to be less than or equal to 5.0×10 21  atoms/cm 3 ). 
     An example of a method for thus decreasing the chlorine concentration and the oxygen concentration will now be described with reference to  FIG.  2    through  FIG.  5   . 
       FIG.  2    through  FIG.  5    are cross-sectional views illustrating a method for manufacturing the semiconductor device of the first embodiment. 
       FIG.  2 A  and  FIG.  2 B  are cross-sectional views corresponding to  FIG.  1 A  and  FIG.  1 B , respectively. The same holds true for  FIG.  3 A  through  FIG.  5 B . A method for manufacturing the semiconductor device of this embodiment will be described mainly with reference to  FIG.  2 A ,  FIG.  3 A ,  FIG.  4 A  and  FIG.  5 A  and sometimes also to  FIG.  2 B ,  FIG.  3 B ,  FIG.  4 B  and  FIG.  5 B . 
     First, the interlayer insulating film  2  may be formed on the substrate  1 , and the plurality of interconnects  3  may be formed in the interlayer insulating film  2 . Thereafter, the interlayer insulating film  4  and the interlayer insulating film  5  may be sequentially formed on the interlayer insulating film  2  and on the interconnects  3  ( FIG.  2 A ). The interconnects  3  may be formed by forming a plurality of interconnect trenches in the interlayer insulating film  2 , and sequentially forming the barrier metal layer  3   a  and the interconnect material layer  3   b  in the interconnect trenches to fill the interconnect trenches with the layers. The barrier metal layer  3   a  is, for example, a Ti film formed by sputtering. The interconnect material layer  3   b  is, for example, a Cu film formed by plating. 
     Next, a via hole H, reaching one of the interconnects  3 , may be formed in the interlayer insulating films  4  and  5  ( FIG.  2 A ). As a result, the upper surface of the interconnect  3  may become exposed in the via hole H. In  FIG.  2 B , the via hole H may be misaligned with the interconnect  3 , and the upper surface and the side surface of the interconnect  3  may be exposed in the via hole H. 
     Next, the barrier metal layer  6   a  may be formed over the entire surface of the substrate  1  ( FIG.  3 A ). As a result, the barrier metal layer  6   a  may be formed on the side surface and the bottom surface of the via hole H. The barrier metal layer  6   a  is, for example, a TiN film formed by CVD (Chemical Vapor Deposition) using a first gas including titanium and chlorine, and a second gas including nitrogen and hydrogen. For example, the first gas includes TiCl 4  gas and the second gas includes NH 3  (ammonia) gas. The barrier metal layer  6   a , formed by using these gases, may contain chlorine as an impurity. 
     In the step of  FIG.  3 A , after the formation of the barrier metal layer  6   a , a chlorine removal treatment may be performed to remove chlorine from the barrier metal layer  6   a . The chlorine removal treatment is carried out, for example, by heat-treating the barrier metal layer  6   a  with NH 3  gas for at least 30 seconds at the same temperature as that in the formation of the barrier metal layer  6   a . The chlorine removal treatment can adjust the chlorine concentration in the barrier metal layer  6   a  to be not more than 5.0×10 21  atoms/cm 3  (or to be less than or equal to 5.0×10 21  atoms/cm 3 ). 
     The step of  FIG.  3 A  may also be permed, for example, in the following manner. First, the substrate  1  after the step of  FIG.  2 A  may be carried into a chamber of a plasma CVD apparatus. This apparatus is, for example, a parallel plate-type plasma CVD apparatus including a heating stage that functions as a lower electrode, and a shower head that functions as an upper electrode. Next, after introducing TiCl 4  gas, H 2  (hydrogen) gas and Ar (argon) gas into the chamber, a high-frequency voltage may be applied between the electrodes (first treatment). A Ti film may be formed over the entire surface of the substrate  1  by the plasma CVD treatment. The Ti film may contain chlorine. Next, an NH 3  plasma treatment using NH 3  gas and Ar gas may be performed in the chamber (second treatment). This treatment may allow chlorine in the Ti film to react with NH 3  to form ammonium chloride which vaporizes. Chlorine can thus be removed from the Ti film. Simultaneously with the reaction of chlorine with NH 3 , the Ti film may react with NH 3  and changes to a TiN film (barrier metal layer  6   a ). A barrier metal layer  6   a  having a chlorine concentration of not more than 5.0×10 21  atoms/cm 3  (or a chlorine concentration of less than or equal to 5.0×10 21  atoms/cm 3 ) may be formed in this manner. 
     In this embodiment, the barrier metal layer  6   a  may be formed by alternately repeating the first treatment including supplying the first gas under plasma conditions, and the second treatment including supplying the second gas under plasma conditions. Accordingly, the barrier metal layer  6   a  may include a TiN film formed by the repetition of the first and second treatments. Thus, the barrier metal layer  6   a  of this embodiment may be formed by alternately supplying the first gas and the second gas. 
     In some embodiments, the higher the temperature is in the chamber during the first and second treatments, the lower the chlorine concentration is in the barrier metal layer  6   a . However, if the temperature in the chamber is too high, it is possible that the copper of the interconnect material layer  3   b  may condense, thereby reducing the reliability of the interconnects  3 . Therefore, the first and second treatments of this embodiment may be performed in the chamber at a temperature of not less than 300° C. and not more than 430° C. (or a temperature of greater than equal to 300° C. and less than equal to 430° C.). This is because if the temperature is less than 300° C., it is possible that the chlorine concentration in the barrier metal layer  6   a  cannot be sufficiently decreased. If the temperature is more than 430° C., it is possible that copper may condense. By forming the barrier metal layer  6   a  at a temperature of not less than 300° C. and not more than 430° C. (or a temperature of greater than or equal to 300° C. and less than or equal to 430° C.) according to this embodiment, it becomes possible to decrease the chlorine concentration in the barrier metal layer  6   a  while preventing condensation of the copper of the interconnect material layer  3   b.    
     Next, the plug material layer  6   b  may be formed over the entire surface of the substrate  1  ( FIG.  4 A ). As a result, the plug material layer  6   b  may be formed in the via hole H and on the barrier metal layer  6   a . The plug material layer  6   b  is, for example, a W (Tungsten) film formed by CVD (Chemical Vapor Deposition) using a gas containing tungsten. The gas includes, for example, a WF 6  gas (F represents fluorine). 
     The plug material layer  6   b  of this embodiment may be formed under vacuum conditions continuous from the formation of the barrier metal layer  6   a . In particular, the plug material layer  6   b  may be formed in the same chamber as the chamber in which the barrier metal layer  6   a  was formed, and in some embodiments, the substrate  1  is not carried out of the chamber between the step of forming the barrier metal layer  6   a  and the step of forming the plug material layer  6   b . Furthermore, in some embodiments, the chamber is not open to the atmosphere between the step of forming the barrier metal layer  6   a  and the step of forming the plug material layer  6   b . The plug material layer  6   b  can therefore be formed such that the oxygen concentration at the interface between the barrier metal layer  6   a  and the plug material layer  6   b  is not more than 5.0×10 21  atoms/cm 3  (or less than or equal to 5.0×10 21  atoms/cm 3 ). 
     Next, the surface of the plug material layer  6   b  may be planarized by CMP (Chemical Mechanical Polishing) ( FIG.  5 A ). As a result, the plug material layer  6   b  and the barrier metal layer  6   a , lying outside the via hole H, may be removed to form the via plug  6  in the via hole H. The via plug  6  of this embodiment may be formed in contact with the interconnect  3 , and therefore is electrically connected to the interconnect  3 . The same holds true for the via plug  6  of  FIG.  5 B . 
     Thereafter, various interlayer insulating films, interconnect layers, plug layers, etc. may be formed on the substrate  1 . The semiconductor device of this embodiment thus can be manufactured. 
       FIG.  6    is a cross-sectional view showing an example of a structure of the semiconductor device of the first embodiment.  FIG.  6    is a cross-sectional view corresponding to  FIG.  1 B . 
       FIG.  6    shows a width w 1  of the upper surface of the interconnect  3  and a diameter w 2  of the via plug  6  at the level of the upper surface of the interconnect  3 . In this embodiment, the width w 1  of the interconnect  3  may be set to be larger than the diameter w 2  of the via plug  6  (w 1 &gt;w 2 ), and the difference between the width w 1  of the interconnect  3  and the diameter w 2  of the via plug  6  may be set to be small. For example, the difference between the width w 1  of the interconnect  3  and the diameter w 2  of the via plug  6  may be set to be not more than 15 nm ((w 1 −w 2 )≤15 nm). The width w 1  of the interconnect  3  is, for example, about 20 nm, and the diameter w 2  of the via plug  6  is, for example, about 10 nm. 
     When the via plug  6  is formed on the interconnect  3  with a misalignment between them, the distance of the misalignment of the via plug  6  may generally be about 15 nm at the maximum. Accordingly, if the difference between the width w 1  of the interconnect  3  and the diameter w 2  of the via plug  6  is not more than 15 nm (or is less than or equal to 15 nm), it is possible that part of the bottom surface of the via plug  6  may be formed outside the upper surface of the interconnect  3 . In  FIG.  6   , part of the bottom surface of the via plug  6  may be formed outside the upper surface of the interconnect  3 ; therefore, part of the upper end of the barrier metal layer  3   a  may be in contact with the barrier metal layer  6   a  of the via plug  6 . 
     The symbol U denotes that upper end of the barrier metal layer  3   a  of the interconnect  3  which is in contact with the barrier metal layer  6   a  of the via plug  6 . The barrier metal layer  3   a  shown in  FIG.  6    may have the right-hand upper end and the left-hand upper end, and the right-hand upper end corresponds to the upper end U in contact with the barrier metal layer  6   a.    
     The upper end U of the barrier metal layer  3   a  may be exposed in the via hole H in the step of  FIG.  2 B . Accordingly, upon the formation of the barrier metal layer  6   a  in the step of  FIG.  3 B , chlorine may diffuse through the inside the barrier metal layer  3   a  or through the interface between the barrier metal layer  3   a  and the interconnect material layer  3   b , and chlorinate the surface of the barrier metal layer  3   a . The chlorination of the surface of the barrier metal layer  3   a  may reduce the adhesion between the barrier metal layer  3   a  and the interconnect material layer  3   b , thus reducing the reliability of the interconnects  3 . 
     Therefore, in this embodiment, the upper end U of the barrier metal layer  3   a  may be nitrided by, for example, NH 3  heat treatment or NH 3  plasma treatment. This makes it possible to prevent chlorine from diffusing from the upper end U of the barrier metal layer  3   a  through the inside the barrier metal layer  3   a  or through the interface between the barrier metal layer  3   a  and the interconnect material layer  3   b . By thus preventing the diffusion of chlorine, it becomes possible to prevent the reduction in the adhesion between the barrier metal layer  3   a  and the interconnect material layer  3   b , thereby preventing the reduction in the reliability of the interconnect  3 . 
       FIG.  6    shows a nitrided portion R formed in the barrier metal layer  3   a  and located at and near the upper end U of the barrier metal layer  3   a . The nitrided portion R may be formed by nitriding the upper end U and its vicinity of the barrier metal layer  3   a  before the formation of the barrier metal layer  6   a . The barrier metal layer  3   a  is, for example, a Ti film, and the nitrided portion R is, for example, a TiN film.  FIG.  6    shows the size or thickness h of the nitrided portion R in the height direction (Z direction). The size h of the nitrided portion R in the height direction is, for example, not more than 10 nm (h≤10 nm). 
     In this embodiment, the main component of the barrier metal layer  3   a  may be titanium (Ti), and the main component of the interconnect material layer  3   b  may be copper (Cu). This makes it possible to diffuse a small amount of Ti atoms from the barrier metal layer  3   a  into the interconnect material layer  3   b , thereby improving the reliability of the interconnect  3 . When the main component of the barrier metal layer  3   a  is titanium, the nitrided portion R may be a TiN film. Accordingly, the surface of the interconnect material layer  3   b  can be covered with the nitrided portion R which is a TiN film, and with the barrier metal layer  6   a  which is a TiN film. Thus, the surface of the interconnect material layer  3   b  can be covered with the same material (TiN). This makes it possible to prevent a reduction in the adhesion between the barrier metal layer  3   a  and the interconnect material layer  3   b  due to different materials covering the surface of the interconnect material layer  3   b , thereby preventing a reduction in the reliability of the interconnect  3 . 
     The reduction in the reliability of the interconnect  3  can also be prevented by forming a TiN film as the barrier metal layer  3   a  in the step of  FIG.  2 B . 
       FIG.  7    is a cross-sectional view showing another example of the structure of the semiconductor device of the first embodiment.  FIG.  7    is a cross-sectional view corresponding to  FIG.  1 A . 
     As described above, the via plug  6  of this embodiment is formed, for example, by forming the via hole H in the interlayer insulating films  4  and  5 , and sequentially forming the barrier metal layer  6   a  and the plug material layer  6   b  in the via hole H to fill the via hole H with the layers. Accordingly, the barrier metal layer  6   a  may include a side portion that faces the side surface of the plug material layer  6   b , and a bottom portion that faces the bottom surface of the plug material layer  6   b . The side portion of the barrier metal layer  6   a  may be an example of a first portion, and the bottom portion of the barrier metal layer  6   a  may be an example of a second portion. 
       FIG.  7    shows a thickness T 1  of the side portion of the barrier metal layer  6   a , and a thickness T 2  of the bottom portion of the barrier metal layer  6   a . In this embodiment, the thickness T 1  of the side portion of the barrier metal layer  6   a  may be set to be smaller than the thickness T 2  of the bottom portion of the barrier metal layer  6   a  (T 1 &lt;T 2 ), for example, not more than one-half of the thickness T 2  of the bottom portion of the barrier metal layer  6   a  (T 1 ≤T 2 /2). Such a barrier metal layer  6   a  may be formed, for example, by depositing the barrier metal layer  6   a  by plasma CVD. 
     By making the thickness T 1  of the side portion of the barrier metal layer  6   a  small while making the thickness T 2  of the bottom portion of the barrier metal layer  6   a  large according to this embodiment, it becomes possible to reduce the volume of the barrier metal layer  6   a  while securing a long distance between the interconnect material layer  3   b  and the plug material layer  6   b . It therefore becomes possible to reduce the amount of chlorine atoms in the barrier metal layer  6   a , thereby further reducing corrosion of the interconnect material layer  3   b.    
     As described hereinabove, in some embodiments, the via plug  6  of this embodiment is formed such that the chlorine concentration in the barrier metal layer  6   a  is not more than 5.0×10 21  atoms/cm 3  (or is less than or equal to 5.0×10 21  atoms/cm 3 ), and the oxygen concentration at the interface between the barrier metal layer  6   a  and the plug material layer  6   b  is not more than 5.0×10 21  atoms/cm 3  (or is less than or equal to 5.0×10 21  atoms/cm 3 ). Therefore, according to this embodiment, it becomes possible to prevent a deterioration in the interconnect  3  due to the influence of the via plug  6 . 
     The interconnect  3  and the via plug  6  are, for example, a bit line and a via plug for the bit line, respectively, of a three-dimensional memory. A specific example of the interconnect  3  and the via plug  6  according to a second embodiment will now be described. 
     Second Embodiment 
       FIG.  8    is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. The semiconductor device of  FIG.  8    is a three-dimensional memory obtained by bonding an array wafer and a circuit wafer together, and includes an array section C 1  from the array wafer, and a circuit section C 2  from the circuit wafer. 
     The array section C 1  may include a memory cell array  11  including a plurality of memory cells arranged three-dimensionally, an insulating film  12  on the memory cell array  11 , and an interlayer insulating film  13  located below the memory cell array  11 . The insulating film  12  is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film  13  is, for example, a silicon oxide film, or a stacked film composed of a silicon oxide film and other insulating film. 
     The circuit section C 2  may be provided under the array section C 1 . The symbol S denotes a bonding interface between the array section C 1  and the circuit section C 2 . The circuit section C 2  may include an interlayer insulating film  14 , and a substrate  15  located below the interlayer insulating film  14 . The interlayer insulating film  14  is, for example, a silicon oxide film, or a stacked film composed of a silicon oxide film and other insulating film. The substrate  15  is, for example, a semiconductor substrate such as a silicon substrate.  FIG.  8    shows an X direction and a Y direction which are parallel to the surface of the substrate  15  and perpendicular to each other, and a Z direction perpendicular to the surface of the substrate  15 . In this embodiment, a +Z direction is treated as an upward direction, and a −Z direction as a downward direction. The −Z direction may or may not coincide with the direction of gravitational force. 
     The array section C 1  may include word lines WL and a source line SL as a plurality of electrode layers in the memory cell array  11 .  FIG.  8    shows a step-like structural portion  21  of the memory cell array  11 . Each word line WL may be electrically connected to a word interconnect layer  23  via a contact plug  22 . Columnar portions CL, penetrating the plurality of word lines WL, may be each electrically connected to a bit line BL via a via plug  24 , and electrically connected to the source line SL. The source line SL may include a first layer SL 1  which is a semiconductor layer, and a second layer SL 2  which is a metal layer. The symbol V denotes a via plug provided under the bit line BL. 
     The circuit section C 2  may include a plurality of transistors  31 . Each transistor  31  may include a gate electrode  32  provided on the substrate  15  via a gate insulating film, and a source diffusion layer and a drain diffusion layer, both not shown, provided in the substrate  15 . The circuit section C 2  may also include a plurality of contact plugs  33  provided on the source diffusion layers and the drain diffusion layers of the transistors  31 , an interconnect layer  34  provided on the contact plugs  33  and including a plurality of interconnects, and an interconnect layer  35  provided on the interconnect layer  34  and including a plurality of interconnects. 
     The circuit section C 2  may further include an interconnect layer  36  provided on the interconnect layer  35  and including a plurality of interconnects, a plurality of via plugs  37  provided on the interconnect layer  36 , and a plurality of metal pads  38  provided on the via plugs  37 . Each metal pad  38  is, for example, a Cu (copper) layer or an Al (aluminum) layer. The circuit section C 2  may function as a control circuit (logic circuit) for controlling the operation of the array section C 1 . The control circuit may be composed of the transistors  31 , etc., and may be electrically connected to the metal pads  38 . 
     The array section C 1  may include a plurality of metal pads  41  provided on the metal pads  38 , and a plurality of via plugs  42  provided on the metal pads  41 . The array section C 1  may also include an interconnect layer  43  provided on the via plugs  42  and including a plurality of interconnects, and an interconnect layer  44  provided on the interconnect layer  43  and including a plurality of interconnects. Each metal pad  41  is, for example, a Cu layer or an Al layer. The above-described via plug V is provided in the interconnect layer  43 . 
     The array section C 1  may further include a plurality of via plugs  45  provided on the interconnect layer  44 , a metal pad  46  provided on the via plugs  45  and on the insulating film  12 , and a passivation film  47  provided on the metal pad  46  and on the insulating film  12 . The metal pad  46  is, for example, a Cu layer or an Al layer, and functions as an external connection pad (bonding pad) of the semiconductor device of  FIG.  8   . The passivation film  47  is, for example, an insulating film such as a silicon oxide film, and has an opening P in which the upper surface of the metal pad  46  is exposed. The metal pad  46  can be connected to a mounting substrate or another device via the opening P by means of, for example, bonding wires, solder balls, or metal bumps. 
       FIG.  9    is a cross-sectional view showing the structure of the columnar portion CL of the second embodiment. 
     As shown in  FIG.  9   , the memory cell array  11  includes the plurality of word lines WL and the plurality of insulating layers  51 , stacked alternately on the interlayer insulating film  13  ( FIG.  8   ). Each word line WL is, for example, a W (tungsten) layer. Each insulating layer  51  is, for example, a silicon oxide film. 
     The columnar portion CL may include a block insulating film  52 , a charge storage layer  53 , a tunnel insulating film  54 , a channel semiconductor layer  55 , and a core insulating film  56 , formed in this order. The charge storage layer  53  is, for example, a silicon nitride film, and is formed on the side surfaces of the word lines WL and the insulating layers  51  via the block insulating film  52 . The charge storage layer  53  may also be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer  55  is, for example, a polysilicon layer, and is formed on the side surface of the charge storage layer  53  via the tunnel insulating film  54 . Each of the block insulating film  52 , the tunnel insulating film  54  and the core insulating film  56  is, for example, a silicon oxide film or a metal insulating film. 
       FIG.  10    is a cross-sectional view illustrating a method for manufacturing the semiconductor device of the second embodiment.  FIG.  10    shows an array wafer W 1  including a plurality of array sections C 1 , and a circuit wafer W 2  including a plurality of circuit sections C 2 . The array wafer W 1  is also called a memory wafer, and the circuit wafer W 2  is also called a CMOS wafer. 
     It is to be noted that the direction of the array wafer W 1  of  FIG.  10    is opposite to the direction of the array section C 1  of  FIG.  8   . In this embodiment, the semiconductor device may be manufactured by bonding the array wafer W 1  and the circuit wafer W 2  together.  FIG.  10    shows the array wafer W 1  before it is inverted for the bonding, while  FIG.  8    shows the array portion C 1  after the wafer W 1  is inverted for the bonding and bonded to the wafer W 2 , and is then diced. 
     In  FIG.  10   , the symbol S 1  denotes the upper surface of the array wafer W 1 , and the symbol S 2  denotes the upper surface of the circuit wafer W 2 . The array wafer W 1  may include a substrate  16  provided under the insulating film  12 . The substrate  16  is, for example, a semiconductor substrate such as a silicon substrate. 
     In this embodiment, as shown in  FIG.  10   , a memory cell array  11 , an insulating film  12 , an interlayer insulating film  13 , a step-like structural portion  21 , metal pads  41 , etc. may be formed on the substrate  16  of the array wafer W 1 , while an interlayer insulating film  14 , transistors  31 , metal pads  38 , etc. are formed on the substrate  15  of the circuit wafer W 2 . For example, via plugs  45 , an interconnect layer  44 , an interconnect layer  43 , via plugs  42 , and the metal pads  41  may be sequentially formed on the substrate  16 , while contact plugs  33 , an interconnect layer  34 , an interconnect layer  35 , an interconnect layer  36 , via plugs  37 , and metal pads  38  are sequentially formed on the substrate  15 . Next, the array wafer W 1  and the circuit wafer W 2  may be bonded together by the application of mechanical pressure, whereby the interlayer insulating film  13  and the interlayer insulating film  14  are bonded together. Next, the array wafer W 1  and the circuit wafer W 2  may be annealed at 400° C., whereby the metal pads  41  and the metal pads  38  are bonded together. 
     Subsequently, the substrate  15  may be thinned by CMP (Chemical Mechanical Polishing), and the substrate  16  is removed by CMP. Thereafter, the array wafer W 1  and the circuit wafer W 2  may be diced into chips. The semiconductor device of  FIG.  8    may be manufactured in this manner. The metal pad  46  and the passivation film  47  may be formed on the insulating film  12  after the thinning of the substrate  15  and the removal of the substrate  16 . 
     Though in this embodiment an array wafer W 1  and a circuit wafer W 2  are bonded together, it is possible to bond array wafers W 1  together. The description given above with reference to  FIG.  8    through  FIG.  10   , and the description given below with reference to  FIG.  11    are applicable to the case of bonding array wafers W 1  together. 
     While  FIG.  8    shows the interface between the interlayer insulating film  13  and the interlayer insulating film  14 , or between the metal pads  41  and the metal pads  38 , the interface generally cannot be observed after the above-described annealing. However, the site where the interface existed can be estimated, for example, from the inclination of the side surface of each metal pad  41  or the side surface of each metal pad  38 , or by detecting a misalignment between the side surface of each metal pad  41  and the side surface of the corresponding metal pad  38 . 
     The structure of the semiconductor device of the first embodiment may be applicable to the array section C 1  of the second embodiment. Hereinafter, example of such a structure will be described with reference to  FIG.  11   . 
       FIG.  11 A  and  FIG.  11 B  are cross-sectional views showing an example of a structure of the semiconductor device of the second embodiment. 
     The semiconductor device of this embodiment may be obtained by applying the structure of the semiconductor device of the first embodiment to the array section C 1  of the second embodiment.  FIG.  11 A  illustrates a case where a via plug  6  is formed on an interconnect  3  without any misalignment with the interconnect  3 , while  FIG.  11 B  illustrates a case where a via plug  6  is formed on an interconnect  3  with some misalignment with the interconnect  3 . It is to be noted that the semiconductor device of this embodiment has been manufactured through bonding of the array wafer W 1  and the circuit wafer W 2 ; therefore, the direction of the array section C 1  in  FIG.  11 A  and  FIG.  11 B  is opposite to the direction of the semiconductor device in  FIG.  1 A  and  FIG.  1 B . 
     Hereinafter, structure of the semiconductor device of this embodiment will be described with reference to  FIG.  11 A . The description is applicable to  FIG.  11 B . 
     In the manufacturing of the semiconductor device of this embodiment, the steps of  FIG.  2    through  FIG.  5    are first performed to produce an array wafer W 1  having the structure shown in  FIG.  1 A ; however, the interlayer insulating film  2 , the interconnects  3 , the interlayer insulating film  4 , the interlayer insulating film  5 , and the via plug  6  may be formed on the substrate  16  instead of the substrate  1 . Next, as described above with reference to  FIG.  10   , the array wafer W 1  and a circuit wafer W 2  may be bonded together, followed by dicing, etc. The semiconductor device of  FIG.  11 A  may be manufactured in this manner. 
     The interconnect  3  and the via plug  6  according to this embodiment are, for example, the bit line BL and the via plug V, shown in  FIG.  8   . It is to be noted that while the via plug  6  may be formed over the interconnect  3  in  FIG.  1 A , the via plug  6  (via plug V) is formed under the interconnect  3  (bit line BL) in  FIG.  8    and  FIG.  11 A . When the direction of the semiconductor device shown in  FIG.  8    and  FIG.  11 A  is inverted, the via plug  6  (via plug V) may lie over the interconnect  3  (bit line BL). 
     As described above with reference to the first embodiment, the via plug  6  of this embodiment may be formed such that the chlorine concentration in the barrier metal layer  6   a  is not more than 5.0×10 21  atoms/cm 3  (or is less than or equal to 5.0×10 21  atoms/cm 3 ), and the oxygen concentration at the interface between the barrier metal layer  6   a  and the plug material layer  6   b  is not more than 5.0×10 21  atoms/cm 3  (or is less than or equal to 5.0×10 21  atoms/cm 3 ). This makes it possible to prevent a deterioration in the interconnect  3  due to the influence of the via plug  6 . The interconnect  3  and the via plug  6  are, for example, the bit line BL and the via plug V. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.