Patent Publication Number: US-2023155032-A1

Title: Semiconductor device and manufacturing method of semiconductor device

Description:
TECHNICAL FIELD 
     One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module. 
     Note that in this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a storage device are each one embodiment of a semiconductor device. It can be sometimes said that a display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a storage device, a semiconductor circuit, an imaging device, an electronic device, and the like include a semiconductor device. 
     Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. One embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. 
     BACKGROUND ART 
     In recent years, semiconductor devices have been developed to be mainly used for LSI, CPUs, memories, and the like. A CPU is an assembly of semiconductor elements which each include a chip of a semiconductor integrated circuit (including at least a transistor and a memory) processed from a semiconductor wafer and an electrode serving as a connection terminal. 
     A semiconductor circuit (IC chip) of an LSI, a CPU, a memory, or the like is mounted on a circuit board, for example, a printed wiring board, to be used as one of components of a variety of electronic devices. 
     A technique by which a transistor is formed using a semiconductor thin film formed over a substrate having an insulating surface has been attracting attention. The transistor is used in a wide range of electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to the transistor and further, an oxide semiconductor has been attracting attention as another material. 
     It is known that a transistor using an oxide semiconductor has an extremely low leakage current in a non-conduction state. For example, Patent Document 1 discloses a low-power-consumption CPU utilizing a feature of a low leakage current of the transistor using an oxide semiconductor. Furthermore, for example, Patent Document 2 discloses a storage device that can retain stored contents for a long time by utilizing a feature of a low leakage current of the transistor using an oxide semiconductor. 
     Non-Patent Document 1 discloses a technique relating to a silicon oxide film formed using a PEALD (Plasma Enhanced ALD) method as an insulating film used for a transistor (see Non-Patent Document 1). 
     In recent years, demand for an integrated circuit with higher density has risen with reductions in size and weight of electronic devices. Furthermore, the productivity of a semiconductor device including an integrated circuit is desired to be improved. 
     REFERENCE 
     Patent Document 
     [Patent Document 1] Japanese Published Patent Application No. 2012-257187 
     [Patent Document 2] Japanese Published Patent Application No. 2011-151383 
     Non-Patent Document 
     Non-Patent Document 1 
     Tatsunori Murata et. al, Low-Temperature Silicon Oxide Offset Spacer Using Plasma-Enhanced Atomic Layer Deposition for High-k/Metal Gate Transistor, Japanese Journal of Applied Physics 49 (2010) 
     SUMMARY OF THE INVENTION 
     Problems to be Solved by the Invention 
     An object of one embodiment of the present invention is to provide a semiconductor device with a small variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable reliability. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with a high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. 
     Note that the descriptions of these objects do not preclude the existence of other objects. One embodiment of the present invention does not have to achieve all these objects. Other objects are apparent from the descriptions of the specification, the drawings, the claims, and the like, and other objects can be derived from the descriptions of the specification, the drawings, the claims, and the like. 
     Means for Solving the Problems 
     One embodiment of the present invention is a method for manufacturing a semiconductor device. In the method for manufacturing a semiconductor device, a first insulating film is formed; an oxide film is formed over the first insulating film; first heat treatment is performed; a first conductive film and a second insulating film are sequentially formed over the oxide film; the first insulating film, the oxide film, the first conductive film, and the second insulating film are processed into island shapes to form a first insulator, an oxide, a conductive layer, and a first insulating layer; a second insulator is formed over the first insulator, the oxide, the conductive layer, and the first insulating layer; a third insulator is formed over the second insulator; an opening reaching the oxide is formed in the conductive layer, the first insulating layer, the second insulator, and the third insulator; by the formation of the opening, a first conductor and a second conductor are formed from the conductive layer and a fourth insulator and a fifth insulator are formed from the first insulating layer; second heat treatment is performed; a third insulating film is formed over the third insulator and the opening; a fourth insulating film is formed over the third insulating film; a fifth insulating film is formed over the fourth insulating film; microwave treatment is performed; a second conductive film is formed over the fifth insulating film; and CMP treatment is performed on the third insulating film, the fourth insulating film, the fifth insulating film, and the second conductive film until a top surface of the third insulator is exposed, to form a sixth insulator, a seventh insulator, an eighth insulator, and a third conductor; and the formation of the fourth insulating film is performed by a PEALD method using a precursor containing silicon but not containing hydrocarbon, an oxidizing gas, and a dilution gas. 
     In the above, preferably, the film formation by the PEALD method includes a first step of introducing the gas containing silicon but not containing hydrocarbon, the oxidizing gas, and the dilution gas into a reaction chamber; a second step of stopping the gas containing silicon but not containing hydrocarbon and purging the gas containing silicon but not containing hydrocarbon that remains in the reaction chamber; a third step of applying a high frequency power to generate plasma based on the oxidizing gas and the dilution gas; and a fourth step of stopping the high frequency power, and when the first to fourth steps are regarded as one cycle, the cycle is performed one time or more and 800 times or less. 
     In the above, preferably, the gas containing silicon but not containing hydrocarbon contains one or more of SiH 4 , Si 2 H 6 , SiF 4 , SiCl 4 , SiBr 4 , SiH 2 Cl 2 , and SiH 2 I 2 , the oxidizing gas contains one or more of O 2 , O 3 , N 2 O, NO 2 , H 2 O, H 2 O 2 , and CO 2 , and the dilution gas contains one or more of N 2 , He, Ne, Ar, Kr, and Xe. 
     In the above, preferably, the gas containing silicon but not containing hydrocarbon is SiH 4 , the oxidizing gas is N 2 O, and the dilution gas is N 2 . 
     In the above, the pressure of the reaction chamber in the first step is preferably greater than or equal to 400 Pa and less than or equal to 1000 Pa. 
     In the above, the temperature of the first heat treatment is preferably higher than a temperature of the second heat treatment. 
     Another embodiment of the present invention is a semiconductor device including an oxide; a first conductor and a second conductor over the oxide; a first insulator over the first conductor; a second insulator over the second conductor; a third insulator over the first insulator and the second insulator; a fourth insulator over the third insulator; a fifth insulator that is over the oxide and is located between the first conductor and the second conductor; a sixth insulator over the fifth insulator; a seventh insulator over the sixth insulator; and a third conductor over the seventh insulator. The third conductor includes a region overlapping with the oxide, the fifth insulator has a region that is in contact with each of the oxide, the first conductor, the second conductor, and the first to fourth insulators, the sixth insulator contains hydrogen, nitrogen, oxygen, and silicon, a hydrogen concentration of a film of the sixth insulator measured by a SIMS analysis method is greater than or equal to 1×10 19  atoms/cm 3  and less than or equal to 3×10 20  atoms/cm 3 , and a nitrogen concentration of the film of the sixth insulator measured by the SIMS analysis method is greater than or equal to 3×10 19  atoms/cm 3  and less than or equal to 1×10 21  atoms/cm 3 . 
     In the above, the seventh insulator preferably contains hafnium. 
     In the above, a thickness of the seventh insulator is preferably greater than or equal to 0.5 nm and less than or equal to 5.0 nm. 
     In the above, a thickness of the sixth insulator is preferably greater than or equal to 0.5 nm and less than or equal to 15.0 nm. 
     In the above, the oxide is preferably an oxide semiconductor containing any one or more of In, Ga, and Zn. 
     Effect of the Invention 
     According to one embodiment of the present invention, a semiconductor device with a small variation in transistor characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with favorable reliability can be provided. According to another embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with a high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided. 
     Note that the descriptions of these effects do not preclude the existence of other effects. One embodiment of the present invention does not have to have all these effects. Other effects are apparent from the descriptions of the specification, the drawings, the claims, and the like, and other effects can be derived from the descriptions of the specification, the drawings, the claims, and the like. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1 A  is a top view of a semiconductor device of one embodiment of the present invention. 
         FIG.  1 B  to  FIG.  1 D  are cross-sectional views of the semiconductor device of one embodiment of the present invention. 
         FIG.  2 A  is a top view of a semiconductor device of one embodiment of the present invention. 
         FIG.  2 B  to  FIG.  2 D  are cross-sectional views of the semiconductor device of one embodiment of the present invention. 
         FIG.  3 A  and  FIG.  3 B  are each a cross-sectional view of a semiconductor device of one embodiment of the present invention. 
         FIG.  4 A  is a diagram showing the classification of crystal structures of IGZO.  FIG.  4 B  is a diagram showing an XRD spectrum of a CAAC-IGZO film.  FIG.  4 C  is a diagram showing a nanobeam electron diffraction pattern of a CAAC-IGZO film. 
         FIG.  5    is a flow chart showing a process of one embodiment of the present invention. 
         FIG.  6 A  and  FIG.  6 B  are diagrams showing deposition sequences of one embodiment of the present invention. 
         FIG.  7 A  is a top view illustrating a method for manufacturing a semiconductor device of one embodiment of the present invention.  FIG.  7 B  to  FIG.  7 D  are cross-sectional views illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention. 
         FIG.  8 A  is a top view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention.  FIG.  8 B  to  FIG.  8 D  are cross-sectional views illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention. 
         FIG.  9 A  is a top view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention.  FIG.  9 B  to  FIG.  9 D  are cross-sectional views illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention. 
         FIG.  10 A  is a top view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention.  FIG.  10 B  to  FIG.  10 D  are cross-sectional views illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention. 
         FIG.  11 A  is a top view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention.  FIG.  11 B  to  FIG.  11 D  are cross-sectional views illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention. 
         FIG.  12 A  is a top view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention.  FIG.  12 B  to  FIG.  12 D  are cross-sectional views illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention. 
         FIG.  13 A  is a top view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention.  FIG.  13 B  to  FIG.  13 D  are cross-sectional views illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention. 
         FIG.  14 A  is a top view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention.  FIG.  14 B  to  FIG.  14 D  are cross-sectional views illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention. 
         FIG.  15 A  is a top view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention.  FIG.  15 B  to  FIG.  15 D  are cross-sectional views illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention. 
         FIG.  16 A  is a top view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention.  FIG.  16 B  to  FIG.  16 D  are cross-sectional views illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention. 
         FIG.  17 A  is a top view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention.  FIG.  17 B  to  FIG.  17 D  are cross-sectional views illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention. 
         FIG.  18 A  is a top view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention.  FIG.  18 B  to  FIG.  18 D  are cross-sectional views illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention. 
         FIG.  19    is a top view illustrating a microwave treatment apparatus according to one embodiment of the present invention. 
         FIG.  20    is a cross-sectional view illustrating the microwave treatment apparatus according to one embodiment of the present invention. 
         FIG.  21    is a cross-sectional view illustrating the microwave treatment apparatus according to one embodiment of the present invention. 
         FIG.  22    is a cross-sectional view illustrating a microwave treatment apparatus according to one embodiment of the present invention. 
         FIG.  23 A  is a planar view of a semiconductor device according to one embodiment of the present invention.  FIG.  23 B  and  FIG.  23 C  are cross-sectional views of the semiconductor device according to one embodiment of the present invention. 
         FIG.  24    is a cross-sectional view illustrating a structure of a storage device according to one embodiment of the present invention. 
         FIG.  25    is a cross-sectional view illustrating a structure of a storage device according to one embodiment of the present invention. 
         FIG.  26    is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 
         FIG.  27 A  and  FIG.  27 B  are cross-sectional views of semiconductor devices according to one embodiment of the present invention. 
         FIG.  28    is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 
         FIG.  29 A  is a block diagram of a structure example of a storage device according to one embodiment of the present invention.  FIG.  29 B  is a perspective view of a structure example of the storage device according to one embodiment of the present invention. 
         FIG.  30 A  to  FIG.  30 H  are circuit diagrams of structure examples of storage devices according to one embodiment of the present invention. 
         FIG.  31 A  and  FIG.  31 B  are schematic views of semiconductor devices according to one embodiment of the present invention. 
         FIG.  32 A  and  FIG.  32 B  are diagrams illustrating examples of electronic components. 
         FIG.  33 A  to  FIG.  33 E  are schematic views of storage devices according to one embodiment of the present invention. 
         FIG.  34 A  to  FIG.  34 H  are diagrams illustrating electronic devices according to one embodiment of the present invention. 
         FIG.  35    is a diagram illustrating a structure of a sample in Example according to one embodiment of the present invention. 
         FIG.  36 A  to  FIG.  36 C  show SIMS analysis results in Example according to one embodiment of the present invention. 
         FIG.  37 A  to  FIG.  37 C  show SIMS analysis results in Example according to one embodiment of the present invention. 
         FIG.  38    is a diagram illustrating a sequence in Example according to one embodiment of the present invention. 
         FIG.  39    is a diagram showing thicknesses of oxide films in Example according to one embodiment of the present invention. 
         FIG.  40 A  to  FIG.  40 C  are schematic diagrams illustrating a structure in Example according to one embodiment of the present invention. 
         FIG.  41    is an energy diagram of each state in Example according to one embodiment of the present invention. 
     
    
    
     MODE FOR CARRYING OUT THE INVENTION 
     Hereinafter, embodiments are described with reference to the drawings. Note that the embodiments can be implemented with many different modes, and it is readily understood by those skilled in the art that modes and details thereof can be changed in various ways without departing from the spirit and scope thereof. Thus, the present invention should not be interpreted as being limited to the description of the embodiments below. 
     In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, they are not limited to the illustrated scale. Note that the drawings schematically illustrate ideal examples, and embodiments of the present invention are not limited to shapes, values, and the like shown in the drawings. For example, in the actual manufacturing process, a layer, a resist mask, or the like might be unintentionally reduced in size by treatment such as etching, which might not be reflected in the drawings for easy understanding. Furthermore, in the drawings, the same reference numerals are used in common for the same portions or portions having similar functions in different drawings, and repeated description thereof is omitted in some cases. Furthermore, the same hatch pattern is used for the portions having similar functions, and the portions are not especially denoted by reference numerals in some cases. 
     Furthermore, especially in a top view (also referred to as a “plan view”), a perspective view, or the like, the description of some components might be omitted for easy understanding of the invention. In addition, some hidden lines and the like might not be illustrated. 
     The ordinal numbers such as “first” and “second” in this specification and the like are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, the term “first” can be replaced with the term “second”, “third”, or the like as appropriate. In addition, the ordinal numbers in this specification and the like do not sometimes correspond to the ordinal numbers that are used to specify one embodiment of the present invention. 
     Moreover, in this specification and the like, terms for describing arrangement, such as “over” and “under”, are used for convenience for describing the positional relation between components with reference to drawings. The positional relationship between components is changed as appropriate in accordance with a direction in which the components are described. Thus, without limitation to terms described in this specification, the description can be changed appropriately depending on the situation. 
     When this specification and the like explicitly state that X and Y are connected, for example, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are regarded as being disclosed in this specification and the like. Accordingly, without being limited to a predetermined connection relationship, for example, a connection relationship shown in drawings or texts, another connection relationship than that shown in drawings or texts is also regarded as disclosed in the drawings or the texts. Here, X and Y each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer). 
     In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. In addition, the transistor includes a region where a channel is formed (hereinafter also referred to as a channel formation region) between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, a channel formation region refers to a region through which a current mainly flows. 
     Furthermore, functions of a source and a drain are sometimes interchanged with each other when transistors having different polarities are used or when the direction of current is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can sometimes be interchanged with each other in this specification and the like. 
     Note that a channel length refers to, for example, a distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor (or a portion where current flows in a semiconductor when a transistor is in an on state) and a gate electrode overlap each other or a channel formation region in a top view of the transistor. Note that in one transistor, channel lengths in all regions do not necessarily have the same value. In other words, the channel length of one transistor is not fixed to one value in some cases. Thus, in this specification, the channel length is any one of the values, the maximum value, the minimum value, or the average value in a channel formation region. 
     A channel width refers to, for example, the length of a channel formation region in a direction perpendicular to a channel length direction in a region where a semiconductor (or a portion where current flows in a semiconductor when a transistor is in an on state) and a gate electrode overlap each other, or a channel formation region in a top view of the transistor. Note that in one transistor, channel widths in all regions do not necessarily have the same value. In other words, the channel width of one transistor is not fixed to one value in some cases. Thus, in this specification, the channel width is any one of the values, the maximum value, the minimum value, or the average value in a channel formation region. 
     Note that in this specification and the like, depending on the transistor structure, a channel width in a region where a channel is actually formed (hereinafter also referred to as an “effective channel width”) is sometimes different from a channel width shown in a top view of a transistor (hereinafter also referred to as an “apparent channel width”). For example, in a transistor whose gate electrode covers a side surface of a semiconductor, the effective channel width is larger than the apparent channel width, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor whose gate electrode covers a side surface of a semiconductor, the proportion of a channel formation region formed in the side surface of the semiconductor is increased in some cases. In that case, the effective channel width is larger than the apparent channel width. 
     In such a case, the effective channel width is sometimes difficult to estimate by actual measurement. For example, estimation of an effective channel width from a design value requires assumption that the shape of a semiconductor is known. Accordingly, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure the effective channel width accurately. 
     In this specification, the simple term “channel width” refers to an apparent channel width in some cases. Alternatively, in this specification, the simple term “channel width” refers to an effective channel width in some cases. Note that values of a channel length, a channel width, an effective channel width, an apparent channel width, and the like can be determined, for example, by analyzing a cross-sectional TEM image and the like. 
     Note that impurities in a semiconductor refer to, for example, elements other than the main components of a semiconductor. For example, an element with a concentration lower than 0.1 atomic % can be regarded as an impurity. When an impurity is contained, for example, the density of defect states in a semiconductor increases and the crystallinity decreases in some cases. In the case where the semiconductor is an oxide semiconductor, examples of an impurity which changes the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor; hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen are given as examples. Note that water also serves as an impurity in some cases. In addition, oxygen vacancies (also referred to as Vo) are formed in an oxide semiconductor in some cases by entry of impurities, for example. 
     Note that in this specification and the like, silicon oxynitride is a material that contains more oxygen than nitrogen in its composition. Moreover, silicon nitride oxide is a material that contains more nitrogen than oxygen in its composition. Similarly, aluminum oxynitride refers to a material that contains more oxygen than nitrogen in its composition. Moreover, aluminum nitride oxide refers to a material that contains more nitrogen than oxygen in its composition. Similarly, hafnium oxynitride refers to a material that contains more oxygen than nitrogen in its composition. Moreover, a hafnium nitride oxide is a material that contains more nitrogen than oxygen in its composition. 
     In this specification and the like, the term “insulator” can be replaced with an insulating film or an insulating layer. Furthermore, the term “conductor” can be replaced with a conductive film or a conductive layer. Moreover, the term “semiconductor” can be replaced with a semiconductor film or a semiconductor layer. 
     In this specification and the like, “parallel” indicates a state where two straight lines are placed at an angle greater than or equal to −10° and less than or equal to 10°. Accordingly, the case where the angle is greater than or equal to −5° and less than or equal to 5° is also included. Furthermore, “substantially parallel” indicates a state where two straight lines are placed at an angle greater than or equal to −30° and less than or equal to 30°. Moreover, “perpendicular” indicates a state where two straight lines are placed at an angle greater than or equal to 80° and less than or equal to 100°. Accordingly, the case where the angle is greater than or equal to 85° and less than or equal to 95° is also included. Furthermore, “substantially perpendicular” indicates a state where two straight lines are placed at an angle greater than or equal to 60° and less than or equal to 120°. 
     In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as an OS), and the like. For example, in the case where a metal oxide is used in a semiconductor layer of a transistor, the metal oxide is referred to as an oxide semiconductor in some cases. That is, an OS transistor can also be called a transistor including a metal oxide or an oxide semiconductor. 
     In this specification and the like, “normally off” means that a drain current per micrometer of channel width flowing through a transistor when no potential is applied to a gate or the gate is supplied with a ground potential is 1×10 −20  A or lower at room temperature, 1×10 −18  A or lower at 85° C., or 1×10 −16  A or lower at 125° C. 
     Embodiment 1 
     In this embodiment, an example of a semiconductor device including a transistor  200  of one embodiment of the present invention and a manufacturing method thereof are described with reference to  FIG.  1    to  FIG.  22 D . 
     &lt;Structure Example of Semiconductor Device&gt; 
     A structure of a semiconductor device including the transistor  200  is described with reference to  FIG.  1   .  FIG.  1 A  to  FIG.  1 D  are a top view and cross-sectional views of the semiconductor device including the transistor  200 .  FIG.  1 A  is a top view of the semiconductor device.  FIG.  1 B  to  FIG.  1 D  are cross-sectional views of the semiconductor device. Here,  FIG.  1 B  is a cross-sectional view of a portion indicated by dashed-dotted line A 1 -A 2  in  FIG.  1 A , and is a cross-sectional view of the transistor  200  in the channel length direction.  FIG.  1 C  is a cross-sectional view of a portion indicated by dashed-dotted line A 3 -A 4  in  FIG.  1 A , and is a cross-sectional view of the transistor  200  in the channel width direction.  FIG.  1 D  is a cross-sectional view of a portion indicated by dashed-dotted line A 5 -A 6  in  FIG.  1 A . Note that for clarity of the drawing, some components are omitted in the top view of  FIG.  1 A . 
     The semiconductor device of one embodiment of the present invention includes an insulator  212  over a substrate (not illustrated), an insulator  214  over the insulator  212 , the transistor  200  over the insulator  214 , an insulator  280  over the transistor  200 , an insulator  282  over the insulator  280 , an insulator  283  over the insulator  282 , an insulator  274  over the insulator  283 , and an insulator  285  over the insulator  283  and the insulator  274 . The insulator  212 , the insulator  214 , the insulator  280 , the insulator  282 , the insulator  283 , the insulator  285 , and the insulator  274  each function as an interlayer film. In addition, the semiconductor device also includes a conductor  240  (a conductor  240   a  and a conductor  240   b ) that is electrically connected to the transistor  200  and functions as a plug. Note that an insulator  241  (an insulator  241   a  and an insulator  241   b ) is provided in contact with a side surface of the conductor  240  functioning as a plug. A conductor  246  (a conductor  246   a  and a conductor  246   b ) electrically connected to the conductor  240  and functioning as a wiring is provided over the insulator  285  and the conductor  240 . The insulator  283  is in contact with part of the top surface of the insulator  214 , the side surface of the insulator  216 , the side surface of the insulator  222 , the side surface of the insulator  275 , the side surface of the insulator  280 , and the side surface of the insulator  282 . 
     The insulator  241   a  is provided in contact with an inner wall of an opening formed in the insulator  280 , the insulator  282 , the insulator  283 , and the insulator  285 , and the conductor  240   a  is provided in contact with the side surface of the insulator  241   a . The insulator  241   b  is provided in contact with an inner wall of an opening formed in the insulator  280 , the insulator  282 , the insulator  283 , and the insulator  285 , and the conductor  240   b  is provided in contact with the side surface of the insulator  241   b . The insulator  241  has a structure in which a first insulator is provided in contact with the inner wall of the opening and a second insulator is provided on the inner side of the first insulator. The conductor  240  has a structure in which a first conductor is provided in contact with the side surface of the insulator  241  and a second conductor is provided on the inner side of the first conductor. The top surface of the conductor  240  can be substantially level with the top surface of the insulator  285  in a region overlapping with the conductor  246 . 
     Although the first insulator of the insulator  241  and the second conductor of the insulator  241  are stacked in the transistor  200 , the present invention is not limited thereto. For example, the insulator  241  may have a single-layer structure or a stacked-layer structure of three or more layers. Although the first conductor of the conductor  240  and the second conductor of the conductor  240  are stacked in the transistor  200 , the present invention is not limited thereto. For example, the conductor  240  may have a single-layer structure or a stacked-layer structure of three or more layers. In the case where a component has a stacked-layer structure, layers may be distinguished by ordinal numbers corresponding to the formation order. 
     [Transistor  200 ] 
     As illustrated in  FIG.  1 A  to  FIG.  1 D , the transistor  200  includes an insulator  216  over the insulator  214 , a conductor  205  (a conductor  205   a  and a conductor  205   b ) provided to be embedded in the insulator  214  or the insulator  216 , an insulator  222  over the insulator  216  and the conductor  205 , an insulator  224  over the insulator  222 , an oxide  230   a  over the insulator  224 , an oxide  230   b  over the oxide  230   a , a conductor  242   a  over the oxide  230   b , an insulator  271   a  over the conductor  242   a , a conductor  242   b  over the oxide  230   b , an insulator  271   b  over the conductor  242   b , an insulator  252  over the oxide  230   b , an insulator  250  (an insulator  250   a  and an insulator  250   b ) over the insulator  252 , a conductor  260  (a conductor  260   a  and a conductor  260   b ) over the insulator  250   b  and overlapping with part of the oxide  230   b , and an insulator  275  over the insulator  222 , the insulator  224 , the oxide  230   a , the oxide  230   b , the conductor  242   a , the conductor  242   b , the insulator  271   a , and insulator  271   b . Here, as illustrated in  FIG.  1 B  and  FIG.  1 C , the insulator  252  is in contact with the side surface of the conductor  242 , the side surface of the insulator  271 , the side surface of the insulator  275 , the insulator  222 , the side surface of the insulator  224 , the insulator  250   a , the side surface of the oxide  230  (the oxide  230   a  and the oxide  230   b ), and the insulator  280 . The top surface of the conductor  260  is placed to be substantially level with the uppermost surface of the insulator  252 , the uppermost surface of the insulator  250  and the top surface of the insulator  280 . The insulator  282  is in contact with the top surfaces of the conductor  260 , the insulator  250 , and the insulator  280 . 
     Hereinafter, the oxide  230   a  and the oxide  230   b  are collectively referred to as the oxide  230  in some cases. The conductor  242   a  and the conductor  242   b  are collectively referred to as the conductor  242  in some cases. The insulator  271   a  and the insulator  271   b  are collectively referred to as the insulator  271  in some cases. 
     An opening reaching the oxide  230   b  is provided in the insulator  280  and the insulator  275 . The insulator  252 , the insulator  250 , and the conductor  260  are positioned in the opening. The conductor  260 , the insulator  252 , and the insulator  250  are provided between the conductor  242   a  and the conductor  242   b  and between the insulator  271   a  and the insulator  271   b  in the channel length direction of the transistor  200 . The insulator  250  includes a region in contact with the side surface of the conductor  260  and a region in contact with the bottom surface of the conductor  260 . 
     The oxide  230  preferably includes the oxide  230   a  placed over the insulator  224  and the oxide  230   b  placed over the oxide  230   a . Including the oxide  230   a  under the oxide  230   b  makes it possible to inhibit diffusion of impurities into the oxide  230   b  from components formed below the oxide  230   a.    
     Although a structure in which two layers, the oxide  230   a  and the oxide  230   b , are stacked as the oxide  230  in the transistor  200  is described, the present invention is not limited thereto. For example, the oxide  230  may be provided as a single layer of the oxide  230   b  or to have a stacked-layer structure of three or more layers, or the oxide  230   a  and the oxide  230   b  may each have a stacked-layer structure. 
     The conductor  260  functions as a first gate (also referred to as a top gate) electrode, and the conductor  205  functions as a second gate (also referred to as a back gate) electrode. The insulator  252  and the insulator  250  function as a first gate insulator, and the insulator  222  and the insulator  224  function as a second gate insulator. The conductor  242   a  functions as one of a source and a drain, and the conductor  242   b  functions as the other of the source and the drain. At least part of a region of the oxide  230  overlapping with the conductor  260  functions as a channel formation region. 
       FIG.  3 A  is an enlarged view of the vicinity of the channel formation region in  FIG.  1 B . Supply of oxygen to the oxide  230   b  forms the channel formation region in a region between the conductor  242   a  and the conductor  242   b . As illustrated in  FIG.  3 A , the oxide  230   b  includes a region  230   bc  functioning as the channel formation region of the transistor  200  and a region  230   ba  and a region  230   bb  that are provided to sandwich the region  230   bc  and function as a source region and a drain region. At least part of the region  230   bc  overlaps with the conductor  260 . In other words, the region  230   bc  is provided between the conductor  242   a  and the conductor  242   b . The region  230   ba  is provided to overlap with the conductor  242   a , and the region  230   bb  is provided to overlap with the conductor  242   b.    
     The region  230   bc  functioning as the channel formation region has a smaller amount of oxygen vacancies or a lower impurity concentration than those of the regions  230   ba  and  230   bb , in other words, the region  230   bc  is a high-resistance region with a low carrier concentration. Thus, the region  230   bc  can be regarded as being i-type (intrinsic) or substantially i-type. 
     The region  230   ba  and the region  230   bb  functioning as the source region and the drain region are each a low-resistance region with an increased carrier concentration because they include a large amount of oxygen vacancies or have a high concentration of an impurity such as hydrogen, nitrogen, or a metal element. In other words, the region  230   ba  and the region  230   bb  are each an n-type region having a higher carrier concentration and a lower resistance than those of the region  230   bc.    
     The carrier concentration in the region  230   bc  functioning as the channel formation region is preferably lower than or equal to 1×10 18  cm 3 , further preferably lower than 1×10 17  cm 3 , still further preferably lower than 1×10 16  cm 3 , yet further preferably lower than 1×10 13  cm 3 , yet still further preferably lower than 1×10 12  cm′. Note that the lower limit of the carrier concentration in the region  230   bc  functioning as the channel formation region is not particularly limited and can be, for example, 1×10 −9  cm −3 . 
     Between the region  230   bc  and the region  230   ba  or the region  230   bb , a region having a carrier concentration that is lower than or substantially equal to the carrier concentrations in the region  230   ba  and the region  230   bb  and higher than or substantially equal to the carrier concentration in the region  230   bc  may be formed. That is, the region functions as a junction region between the region  230   bc  and the region  230   ba  or the region  230   bb . The hydrogen concentration in the junction region is lower than or substantially equal to the hydrogen concentrations in the region  230   ba  and the region  230   bb  and higher than or substantially equal to the hydrogen concentration in the region  230   bc  in some cases. The amount of oxygen vacancies in the junction region is smaller than or substantially equal to the amounts of oxygen vacancies in the region  230   ba  and the region  230   bb  and larger than or substantially equal to the amount of oxygen vacancies in the region  230   bc  in some cases. 
     Although  FIG.  3 A  illustrates an example in which the region  230   ba , the region  230   bb , and the region  230   bc  are formed in the oxide  230   b , the present invention is not limited thereto. For example, the above regions may be formed not only in the oxide  230   b  but also in the oxide  230   a.    
     In the oxide  230 , the boundaries between the regions are difficult to detect clearly in some cases. The concentration of a metal element and an impurity element such as hydrogen or nitrogen, which is detected in each region, may be gradually changed not only between the regions but also in each region. That is, the region closer to the channel formation region preferably has a lower concentration of a metal element and an impurity element such as hydrogen or nitrogen. 
     In the transistor  200 , a metal oxide functioning as a semiconductor (such a metal oxide is hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide  230  (the oxide  230   a  and the oxide  230   b ) including the channel formation region. 
     The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, further preferably 2.5 eV or more. With the use of such a metal oxide having a large band gap, the off-state current of the transistor can be reduced. 
     As the oxide  230 , it is preferable to use, for example, a metal oxide such as an In-M-Zn oxide containing indium, an element M, and zinc (the element M is one or more kinds selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like). Alternatively, an In—Ga oxide, an In—Zn oxide, or an indium oxide may be used as the oxide  230 . 
     The atomic ratio of In to the element M in the metal oxide used as the oxide  230   b  is preferably greater than the atomic ratio of In to the element M in the metal oxide used as the oxide  230   a.    
     The oxide  230   a  is placed under the oxide  230   b , whereby impurities and oxygen can be inhibited from diffusing into the oxide  230   b  from components formed below the oxide  230   a.    
     When the oxide  230   a  and the oxide  230   b  contain a common element (as the main component) besides oxygen, the density of defect states at an interface between the oxide  230   a  and the oxide  230   b  can be made low. Since the density of defect states at the interface between the oxide  230   a  and the oxide  230   b  can be made low, the influence of interface scattering on carrier conduction is small, and a high on-state current can be obtained. 
     The oxide  230   b  preferably has crystallinity. It is particularly preferable to use a CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide  230   b.    
     The CAAC-OS is a metal oxide having a dense structure with high crystallinity and a small amount of impurities or defects (e.g., oxygen vacancies (Vo)). In particular, after the formation of a metal oxide, heat treatment is performed at a temperature at which the metal oxide does not become a polycrystal (e.g., 400° C. to 600° C.), whereby a CAAC-OS having a dense structure with higher crystallinity can be obtained. When the density of the CAAC-OS is increased in such a manner, diffusion of impurities or oxygen in the CAAC-OS can be further reduced. 
     On the other hand, a clear crystal grain boundary is difficult to observe in the CAAC-OS; thus, it can be said that a reduction in electron mobility due to the crystal grain boundary is less likely to occur. Thus, a metal oxide including a CAAC-OS is physically stable. Therefore, the metal oxide including a CAAC-OS is resistant to heat and has high reliability. 
     If impurities and oxygen vacancies exist in a region of an oxide semiconductor where a channel is formed, a transistor using the oxide semiconductor might have variable electrical characteristics and poor reliability. In some cases, hydrogen in the vicinity of an oxygen vacancy forms a defect that is the oxygen vacancy into which hydrogen enters (hereinafter sometimes referred to as VoH), which generates an electron serving as a carrier. Therefore, when the region of the oxide semiconductor where a channel is formed includes oxygen vacancies, the transistor tends to have normally-on characteristics (even when no voltage is applied to the gate electrode, the channel exists and current flows through the transistor). Thus, impurities, oxygen vacancies, and VoH are preferably reduced as much as possible in the region of the oxide semiconductor where a channel is formed. In other words, it is preferable that the region of the oxide semiconductor where a channel is formed have a reduced carrier concentration and be of an i-type (intrinsic) or substantially i-type. 
     As a countermeasure to the above, an insulator containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen) is provided in the vicinity of the oxide semiconductor and heat treatment is performed, so that oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies and VoH. However, supply of an excess amount of oxygen to the source region or the drain region might cause a decrease in the on-state current or field-effect mobility of the transistor  200 . Furthermore, a variation of oxygen supplied to the source region or the drain region on the substrate plane leads to a variation in characteristics of the semiconductor device including the transistor. 
     Therefore, the region  230   bc  functioning as the channel formation region in the oxide semiconductor is preferably an i-type or substantially i-type region with reduced carrier concentration, whereas the region  230   ba  and the region  230   bb  functioning as the source region and the drain region are preferably n-type regions with high carrier concentrations. That is, it is preferable that oxygen vacancies and VoH in the region  230   bc  of the oxide semiconductor be reduced and the region  230   ba  and the region  230   bb  not be supplied with an excess amount of oxygen. 
     Thus, in this embodiment, microwave treatment is performed in an oxygen-containing atmosphere in a state where the conductor  242   a  and the conductor  242   b  are provided over the oxide  230   b  so that oxygen vacancies and VoH in the region  230   bc  can be reduced. Here, the microwave treatment refers to, for example, treatment using an apparatus including a power source that generates high-density plasma with the use of a microwave. 
     The microwave treatment in an oxygen-containing atmosphere converts an oxygen gas into plasma using a high-frequency wave such as a microwave or RF (Radio Frequency) and activates the oxygen plasma. At this time, the region  230   bc  can be irradiated with the high-frequency wave such as the microwave or RF. By the effect of the plasma, the microwave, or the like, VoH in the region  230   bc  can be cut; thus, hydrogen (H) can be removed from the region  230   bc  and an oxygen vacancy (Vo) can be filled with oxygen. That is, the reaction “VoH H+Vo” occurs in the region  230   bc , so that the hydrogen concentration in the region  230   bc  can be reduced. As a result, oxygen vacancies and VoH in the region  230   bc  can be reduced to lower the carrier concentration. 
     In the microwave treatment in an oxygen-containing atmosphere, the high-frequency wave such as the microwave or RF, the oxygen plasma, or the like is blocked by the conductor  242   a  and the conductor  242   b  and does not affect the region  230   ba  nor the region  230   bb . In addition, the effect of the oxygen plasma can be reduced by the insulator  271  and the insulator  280  that are provided to cover the oxide  230   b  and the conductor  242 . Hence, a reduction in VoH and supply of an excess amount of oxygen do not occur in the region  230   ba  or the region  230   bb  in the microwave treatment, preventing a decrease in carrier concentration. 
     In particular, the above effect is large when the microwave treatment is performed in an oxygen-containing atmosphere after deposition of an insulating film to be the insulator  250   b . In addition, it is preferable that microwave treatment be performed in an oxygen-containing atmosphere after deposition of an insulating film to be the insulator  252  and another microwave treatment be further performed in an oxygen-containing atmosphere after the deposition of the insulating film to be the insulator  250   a  and another microwave treatment be further performed in an oxygen-containing atmosphere after the deposition of the insulating film to be the insulator  250   b . By performing the microwave treatment in an oxygen-containing atmosphere through the insulator  252 , the insulator  250   a  or the insulator  250   b  in such a manner, oxygen can be efficiently supplied into the region  230   bc . In addition, the insulator  252  is provided to be in contact with the side surface of the conductor  242  and the surface of the region  230   bc , whereby an excess amount of oxygen is prevented from being supplied to the region  230   bc , and the side surface of the conductor  242  can be prevented from being oxidized. Furthermore, the side surface of the conductor  242  can be prevented from being oxidized when an insulating film to be the insulator  250   a  is formed. 
     The oxygen supplied into the region  230   bc  has any of a variety of forms such as an oxygen atom, an oxygen molecule, an oxygen radical (an O radical, an atom or a molecule having an unpaired electron, or an ion). Note that the oxygen supplied into the region  230   bc  has any one or more of the above forms, particularly preferably an oxygen radical. Furthermore, when the microwave treatment is performed in an oxygen-containing atmosphere after the deposition of the insulating film to be the insulator  250   b , the film quality of the insulator  252 , the insulator  250   a , and the insulator  250   b  can be improved, leading to higher reliability of the transistor  200 . 
     In the above manner, oxygen vacancies and VoH can be selectively removed from the region  230   bc  serving as a channel formation region, whereby the region  230   bc  can be an i-type or substantially i-type region. Furthermore, supply of an excess amount of oxygen to the region  230   ba  and the region  230   bb  functioning as the source region and the drain region can be inhibited and the n-type conductivity can be maintained. As a result, a change in the electrical characteristics of the transistor  200  can be inhibited, and thus a variation in the electrical characteristics of the transistors  200  in the substrate plane can be inhibited. 
     With the above structure, a semiconductor device with a small variation in transistor characteristics can be provided. A semiconductor device with favorable reliability can also be provided. A semiconductor device having favorable electrical characteristics can be provided. 
     As illustrated in  FIG.  1 C , a curved surface may be provided between a side surface of the oxide  230   b  and a top surface of the oxide  230   b  in a cross-sectional view of the transistor  200  in the channel width direction. In other words, an end portion of the side surface and an end portion of the top surface may be curved (hereinafter referred to as rounded). 
     The radius of curvature of the curved surface is preferably greater than 0 nm and less than the thickness of the oxide  230   b  in a region overlapping with the conductor  242 , or less than half of the length of a region that does not have the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than or equal to 20 nm, preferably greater than or equal to 1 nm and less than or equal to 15 nm, and further preferably greater than or equal to 2 nm and less than or equal to 10 nm. Such a shape can improve the coverage of the oxide  230   b  with the insulator  250  and the conductor  260 . 
     The oxide  230  preferably has a stacked-layer structure of a plurality of oxide layers with different chemical compositions. Specifically, the atomic ratio of the element M to a metal element that is a main component of the metal oxide used as the oxide  230   a  is preferably greater than the atomic ratio of the element M to a metal element that is a main component of the metal oxide used as the oxide  230   b . Moreover, the atomic ratio of the element M to In in the metal oxide used as the oxide  230   a  is preferably greater than the atomic ratio of the element M to In in the metal oxide used as the oxide  230   b . Furthermore, the atomic ratio of In to the element Min the metal oxide used as the oxide  230   b  is preferably greater than the atomic ratio of In to the element M in the metal oxide used as the oxide  230   a.    
     The oxide  230   b  is preferably an oxide having crystallinity, such as a CAAC-OS. An oxide having crystallinity, such as a CAAC-OS, has a dense structure with small amounts of impurities and defects (e.g., oxygen vacancies) and high crystallinity. This can inhibit oxygen extraction from the oxide  230   b  by the source electrode or the drain electrode. This can reduce oxygen extraction from the oxide  230   b  even when heat treatment is performed; thus, the transistor  200  is stable with respect to high temperatures in a manufacturing process (what is called thermal budget). 
     Here, the conduction band minimum gradually changes at a junction portion of the oxide  230   a  and the oxide  230   b . In other words, the conduction band minimum at the junction portion of the oxide  230   a  and the oxide  230   b  continuously changes or is continuously connected. To achieve this, the density of defect states in a mixed layer formed at the interface between the oxide  230   a  and the oxide  230   b  is preferably made low. 
     Specifically, when the oxide  230   a  and the oxide  230   b  contain a common element as a main component besides oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide  230   b  is an In-M-Zn oxide, an In-M-Zn oxide, an M-Zn oxide, an oxide of the element M, an In—Zn oxide, indium oxide, or the like may be used as the oxide  230   a.    
     Specifically, as the oxide  230   a , a metal oxide with a composition of In:M:Zn=1:3:4 [atomic ratio] or in the neighborhood thereof, or a composition of In:M:Zn=1:1:0.5 [atomic ratio] or in the neighborhood thereof is used. As the oxide  230   b , a metal oxide with a composition of In:M:Zn=1:1:1 [atomic ratio] or in the neighborhood thereof, or a composition of In:M:Zn=4:2:3 [atomic ratio] or in the neighborhood thereof can be used. Note that a composition in the neighborhood includes the range of ±30% of an intended atomic ratio. Gallium is preferably used as the element M. 
     When the metal oxide is deposited by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide and may be the atomic ratio of a sputtering target used for depositing the metal oxide. 
     When the oxide  230   a  and the oxide  230   b  have the above structure, the density of defect states at the interface between the oxide  230   a  and the oxide  230   b  can be made low. Thus, the influence of interface scattering on carrier conduction is small, and the transistor  200  can have a high on-state current and excellent frequency characteristics. 
     At least one of the insulator  212 , the insulator  214 , the insulator  271 , the insulator  275 , the insulator  282 , the insulator  283 , and the insulator  285  preferably functions as a barrier insulating film, which inhibits diffusion of impurities such as water and hydrogen from the substrate side or above the transistor  200  into the transistor  200 . Thus, for at least one of the insulator  212 , the insulator  214 , the insulator  271 , the insulator  275 , the insulator  282 , the insulator  283 , and the insulator  285 , it is preferable to use an insulating material having a function of inhibiting diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N 2 O, NO, or NO 2 ), or copper atoms (an insulating material through which the impurities are less likely to pass). Alternatively, it is preferable to use an insulating material having a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) (an insulating material through which the oxygen is less likely to pass). 
     Note that in this specification, a barrier insulating film refers to an insulating film having a barrier property. A barrier property in this specification means a function of inhibiting diffusion of a targeted substance (also referred to as having low permeability). In addition, a barrier property in this specification means a function of capturing and fixing (also referred to as gettering) a targeted substance. 
     An insulator having a function of inhibiting diffusion of oxygen and impurities such as water and hydrogen is preferably used for the insulator  212 , the insulator  214 , the insulator  271 , the insulator  275 , the insulator  282 , the insulator  283 , and the insulator  285 ; for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, silicon nitride, which has a higher hydrogen barrier property, is preferably used for the insulator  212 , the insulator  275 , and the insulator  283 . For example, aluminum oxide or magnesium oxide, which has a function of capturing or fixing hydrogen well, is preferably used for the insulator  214 , the insulator  271 , the insulator  282 , and the insulator  285 . In this case, impurities such as water and hydrogen can be inhibited from diffusing to the transistor  200  side from the substrate side through the insulator  212  and the insulator  214 . Impurities such as water and hydrogen can be inhibited from diffusing to the transistor  200  side from an interlayer insulating film and the like which are provided outside the insulator  285 . Alternatively, oxygen contained in the insulator  224  and the like can be inhibited from diffusing to the substrate side through the insulator  212  and the insulator  214 . Alternatively, oxygen contained in the insulator  280  and the like can be inhibited from diffusing to above the transistor  200  through the insulator  282  and the like. In this manner, it is preferable that the transistor  200  be surrounded by the insulator  212 , the insulator  214 , the insulator  271 , the insulator  275 , the insulator  282 , the insulator  283 , and the insulator  285 , which have a function of inhibiting diffusion of oxygen and impurities such as water and hydrogen. 
     Here, an oxide having an amorphous structure is preferably used for the insulator  212 , the insulator  214 , the insulator  271 , the insulator  275 , the insulator  282 , the insulator  283 , and the insulator  285 . For example, a metal oxide such as AlOx (x is a given number greater than 0) or MgO y  (y is a given number greater than 0) is preferably used. In such a metal oxide having an amorphous structure, an oxygen atom has a dangling bond and sometimes has a property of capturing or fixing hydrogen with the dangling bond. When such a metal oxide having an amorphous structure is used as the component of the transistor  200  or provided around the transistor  200 , hydrogen contained in the transistor  200  or hydrogen present around the transistor  200  can be captured or fixed. In particular, hydrogen contained in the channel formation region of the transistor  200  is preferably captured or fixed. The metal oxide having an amorphous structure is used as the component of the transistor  200  or provided around the transistor  200 , whereby the transistor  200  and a semiconductor device which have favorable characteristics and high reliability can be manufactured. 
     Although each of the insulator  212 , the insulator  214 , the insulator  271 , the insulator  275 , the insulator  282 , the insulator  283 , and the insulator  285  preferably has an amorphous structure, a region having a polycrystalline structure may be partly formed. Alternatively, each of the insulator  212 , the insulator  214 , the insulator  271 , the insulator  275 , the insulator  282 , the insulator  283 , and the insulator  285  may have a multilayer structure in which a layer having an amorphous structure and a layer having a polycrystalline structure are stacked. For example, a stacked-layer structure in which a layer having a polycrystalline structure is formed over a layer having an amorphous structure may be employed. 
     The insulator  212 , the insulator  214 , the insulator  271 , the insulator  275 , the insulator  282 , the insulator  283 , and the insulator  285  can be deposited by a sputtering method, for example. Since a sputtering method does not need to use hydrogen as a deposition gas, the hydrogen concentrations in the insulator  212 , the insulator  214 , the insulator  271 , the insulator  275 , the insulator  282 , the insulator  283 , and the insulator  285  can be reduced. Note that the deposition method is not limited to a sputtering method, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like can be used as appropriate. 
     The resistivities of the insulator  212 , the insulator  275 , and the insulator  283  are preferably low in some cases. For example, by setting the resistivities of the insulator  212 , the insulator  275 , and the insulator  283  to approximately 1×10 13  Ωcm, the insulator  212 , the insulator  275 , and the insulator  283  can sometimes reduce charge up of the conductor  205 , the conductor  242 , the conductor  260 , or the conductor  246  in treatment using plasma or the like in the manufacturing process of a semiconductor device. The resistivities of the insulator  212 , the insulator  275 , and the insulator  283  are preferably higher than or equal to 1×10 10  Ωcm and lower than or equal to 1×10 15  Ωcm. 
     The insulator  216 , the insulator  274 , and the insulator  280  each preferably have a lower permittivity than the insulator  214 . When a material with a low permittivity is used for an interlayer film, parasitic capacitance generated between wirings can be reduced. For the insulator  216 , the insulator  274 , and the insulator  280 , silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like is used as appropriate, for example. 
     The conductor  205  is placed to overlap with the oxide  230  and the conductor  260 . Here, the conductor  205  is preferably provided to be embedded in an opening formed in the insulator  216 . Part of the conductor  205  is embedded in the insulator  214  in some cases. 
     The conductor  205  includes the conductor  205   a  and the conductor  205   b . The conductor  205   a  is provided in contact with a bottom surface and a sidewall of the opening. The conductor  205   b  is provided to be embedded in a recessed portion formed in the conductor  205   a . Here, the top surface of the conductor  205   b  is substantially level with the top surfaces of the conductor  205   a  and the insulator  216 . 
     Here, for the conductor  205   a , it is preferable to use a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2 , or the like), and a copper atom. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like). 
     When the conductor  205   a  is formed using a conductive material having a function of inhibiting diffusion of hydrogen, impurities such as hydrogen contained in the conductor  205   b  can be prevented from diffusing into the oxide  230  through the insulator  224  and the like. When the conductor  205   a  is formed using a conductive material having a function of inhibiting diffusion of oxygen, the conductivity of the conductor  205   b  can be inhibited from being lowered because of oxidation. As the conductive material having a function of inhibiting diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Thus, a single layer or a stacked layer of the above conductive material is used as the conductor  205   a . For example, titanium nitride is used for the conductor  205   a.    
     Moreover, the conductor  205   b  is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. For example, tungsten is used for the conductor  205   b.    
     The conductor  205  sometimes functions as a second gate electrode. In that case, by changing a potential applied to the conductor  205  not in conjunction with but independently of a potential applied to the conductor  260 , the threshold voltage (Vth) of the transistor  200  can be controlled. In particular, Vth of the transistor  200  can be higher in the case where a negative potential is applied to the conductor  205 , and the off-state current can be reduced. Thus, a drain current at the time when a potential applied to the conductor  260  is 0 V can be lower in the case where a negative potential is applied to the conductor  205  than in the case where the negative potential is not applied to the conductor  205 . 
     The electric resistivity of the conductor  205  is designed in consideration of the potential applied to the conductor  205 , and the thickness of the conductor  205  is determined in accordance with the electric resistivity. The thickness of the insulator  216  is substantially equal to that of the conductor  205 . The conductor  205  and the insulator  216  are preferably as thin as possible in the allowable range of the design of the conductor  205 . When the thickness of the insulator  216  is reduced, the absolute amount of impurities such as hydrogen contained in the insulator  216  can be reduced, reducing the amount of the impurities to be diffused into the oxide  230 . 
     As illustrated in  FIG.  1 A , the conductor  205  is preferably provided to be larger than a region of the oxide  230  that does not overlap with the conductor  242   a  or the conductor  242   b . As illustrated in  FIG.  1 C , it is particularly preferable that the conductor  205  extend to a region outside end portions of the oxide  230   a  and the oxide  230   b  in the channel width direction. That is, the conductor  205  and the conductor  260  preferably overlap each other with the insulators therebetween on the outer side of a side surface of the oxide  230  in the channel width direction. With this structure, the channel formation region of the oxide  230  can be electrically surrounded by the electric field of the conductor  260  functioning as a first gate electrode and the electric field of the conductor  205  functioning as the second gate electrode. In this specification, a transistor structure in which a channel formation region is electrically surrounded by electric fields of a first gate and a second gate is referred to as a surrounded channel (S-channel) structure. 
     In this specification and the like, a transistor having the S-channel structure refers to a transistor having a structure in which a channel formation region is electrically surrounded by the electric fields of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like is different from a Fin-type structure and a planar structure. With the S-channel structure, resistance to a short-channel effect can be enhanced, that is, a transistor in which a short-channel effect is less likely to occur can be provided. 
     Furthermore, as illustrated in  FIG.  1 C , the conductor  205  is extended to function as a wiring as well. However, without limitation to this structure, a structure in which a conductor functioning as a wiring is provided below the conductor  205  may be employed. In addition, the conductor  205  is not necessarily provided in each transistor. For example, the conductor  205  may be shared by a plurality of transistors. 
     Although the transistor  200  having a structure in which the conductor  205  is a stack of the conductor  205   a  and the conductor  205   b  is illustrated, the present invention is not limited thereto. For example, the conductor  205  may be provided to have a single-layer structure or a stacked-layer structure of three or more layers. 
     The insulator  222  and the insulator  224  function as a gate insulator. 
     It is preferable that the insulator  222  have a function of inhibiting diffusion of hydrogen (e.g., at least one of a hydrogen atom, a hydrogen molecule, and the like). In addition, it is preferable that the insulator  222  have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like). For example, the insulator  222  preferably has a function of inhibiting diffusion of one or both of hydrogen and oxygen more than the insulator  224 . 
     As the insulator  222 , an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material, is preferably used. For the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. In the case where the insulator  222  is formed using such a material, the insulator  222  functions as a layer that inhibits release of oxygen from the oxide  230  to the substrate side and diffusion of impurities such as hydrogen from the periphery of the transistor  200  into the oxide  230 . Thus, providing the insulator  222  can inhibit diffusion of impurities such as hydrogen into the transistor  200  and inhibit generation of oxygen vacancies in the oxide  230 . Moreover, the conductor  205  can be inhibited from reacting with oxygen contained in the insulator  224  and the oxide  230 . 
     Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above insulator, for example. Alternatively, the insulator may be subjected to nitriding treatment. A stack of silicon oxide, silicon oxynitride, or silicon nitride over these insulators may be used for the insulator  222 . 
     For example, a single layer or stacked layers of an insulator containing what is called a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba,Sr)TiO 3  (BST) may be used for the insulator  222 . As miniaturization and high integration of transistors progress, a problem such as a leakage current may arise because of a thinner gate insulator. When a high-k material is used for an insulator functioning as the gate insulator, a gate potential at the time when the transistor operates can be reduced while the physical thickness is maintained. 
     Silicon oxide or silicon oxynitride, for example, can be used as appropriate for the insulator  224  that is in contact with the oxide  230 . 
     In a manufacturing process of the transistor  200 , heat treatment is preferably performed with a surface of the oxide  230  exposed. For example, the heat treatment is performed at a temperature higher than or equal to 100° C. and lower than or equal to 600° C., preferably higher than or equal to 350° C. and lower than or equal to 550° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This can supply oxygen to the oxide  230  to reduce oxygen vacancies (Vo). The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for released oxygen, after heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere successively after heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more, and then another. 
     Note that oxygen adding treatment performed on the oxide  230  can promote a reaction in which oxygen vacancies in the oxide  230  are repaired with supplied oxygen, i.e., a reaction of “Vo+O→null”. Furthermore, hydrogen remaining in the oxide  230  reacts with supplied oxygen, so that the hydrogen can be removed as H 2 O (dehydration). This can inhibit recombination of hydrogen remaining in the oxide  230  with oxygen vacancies and formation of VoH. 
     Note that the insulator  222  and the insulator  224  may each have a stacked-layer structure of two or more layers. In that case, without limitation to a stacked-layer structure formed of the same material, a stacked-layer structure formed of different materials may be employed. The insulator  224  may be formed into an island shape so as to overlap with the oxide  230   a . In this case, the insulator  275  is in contact with a side surface of the insulator  224  and a top surface of the insulator  222 . 
     The conductor  242   a  and the conductor  242   b  are provided in contact with a top surface of the oxide  230   b . Each of the conductor  242   a  and the conductor  242   b  functions as a source electrode or a drain electrode of the transistor  200 . 
     For the conductor  242  (the conductor  242   a  and the conductor  242   b ), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. As another example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are each a conductive material that is not easily oxidized or a material that maintains the conductivity even after absorbing oxygen. 
     Note that hydrogen contained in the oxide  230   b  or the like diffuses into the conductor  242   a  or the conductor  242   b  in some cases. In particular, when a nitride containing tantalum is used for the conductor  242   a  and the conductor  242   b , hydrogen contained in the oxide  230   b  or the like is likely to diffuse into the conductor  242   a  or the conductor  242   b , and the diffused hydrogen is bonded to nitrogen contained in the conductor  242   a  or the conductor  242   b  in some cases. That is, hydrogen contained in the oxide  230   b  or the like is absorbed by the conductor  242   a  or the conductor  242   b  in some cases. 
     In addition, an oxide may be provided between the oxide  230   b  and the conductor  242  in some cases. Specifically, the oxide is over and in contact with the oxide  230   b  and the conductor  242  is provided with the top surface of the oxide. 
     The oxide preferably has a function of inhibiting passage of oxygen. The oxide having a function of inhibiting passage of oxygen is preferably placed between the oxide  230   b  and the conductor  242  functioning as the source electrode and the drain electrode, in which case the electric resistance between the oxide  230   b  and the conductor  242  can be reduced. Such a structure can improve the electrical characteristics of the transistor  200  and the reliability of the transistor  200  in some cases. 
     A metal oxide containing the element M may be used as the oxide. In particular, aluminum, gallium, yttrium, or tin is preferably used as the element M. The concentration of the element M in the oxide is preferably higher than that in the oxide  230   b . Furthermore, gallium oxide may be used for the oxide. A metal oxide such as an In-M-Zn oxide may be used as the oxide. Specifically, the atomic ratio of the element M to In in the metal oxide used as the oxide is preferably greater than the atomic ratio of the element M to In in the metal oxide used as the oxide  230   b . The thickness of the oxide is preferably greater than or equal to 0.5 nm and less than or equal to 5 nm, further preferably greater than or equal to 1 nm and less than or equal to 3 nm, still further preferably greater than or equal to 1 nm and less than or equal to 2 nm. The oxide preferably has crystallinity. In the case where the oxide has crystallinity, release of oxygen from the oxide  230  can be favorably inhibited. When the oxide has a hexagonal crystal structure, for example, release of oxygen from the oxide  230  can sometimes be inhibited. 
     No curved surface is preferably formed between a side surface of the conductor  242  and a top surface of the conductor  242 . When no curved surface is formed in the conductor  242 , the conductor  242  can have a large cross-sectional area in the channel width direction as illustrated in  FIG.  1 D . Accordingly, the conductivity of the conductor  242  is increased, so that the on-state current of the transistor  200  can be increased. 
     The insulator  271   a  is provided in contact with the top surface of the conductor  242   a , and the insulator  271   b  is provided in contact with the top surface of the conductor  242   b . The insulator  271  preferably functions as at least a barrier insulating film against oxygen. Thus, the insulator  271  preferably has a function of inhibiting oxygen diffusion. For example, the insulator  271  preferably has a function of inhibiting diffusion of oxygen more than the insulator  280 . For example, a nitride containing silicon such as silicon nitride may be used for the insulator  271 . The insulator  271  preferably has a function of capturing impurities such as hydrogen. In that case, for the insulator  271 , a metal oxide having an amorphous structure, for example, an insulator such as aluminum oxide or magnesium oxide, may be used. It is particularly preferable to use aluminum oxide having an amorphous structure or amorphous aluminum oxide for the insulator  271  because hydrogen can be captured or fixed more effectively in some cases. Accordingly, the transistor  200  and a semiconductor device which have favorable characteristics and high reliability can be manufactured. 
     The insulator  275  is provided to cover the insulator  224 , the oxide  230   a , the oxide  230   b , the conductor  242 , and the insulator  271 . The insulator  275  preferably has a function of capturing and fixing hydrogen. In that case, the insulator  275  preferably includes silicon nitride, or a metal oxide having an amorphous structure, for example, an insulator such as aluminum oxide or magnesium oxide. 
     When the above insulator  271  and the insulator  275  are provided, the conductor  242  can be surrounded by the insulators having a barrier property against oxygen. That is, oxygen contained in the insulator  224  and the insulator  280  can be prevented from diffusing into the conductor  242 . As a result, the conductor  242  can be inhibited from being directly oxidized by oxygen contained in the insulator  224  and the insulator  280 , so that an increase in resistivity and a reduction in on-state current can be inhibited. 
     The insulator  252  and the insulator  250  function as the gate insulator. Thus, the insulator  252  is preferably a barrier insulating film having a function of inhibiting oxygen diffusion. Thus, as the insulator  252 , an insulator containing an oxide of one or both of aluminum and hafnium is preferably used. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used. In this embodiment, aluminum oxide is used as the insulator  252 . The insulator  250  is preferably in contact with a top surface of the insulator  252 . The insulator  250  can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like. In particular, silicon oxide and silicon oxynitride, which have thermal stability, are preferable. 
     As in the insulator  224 , the concentration of impurities such as water and hydrogen in the insulator  250  (the insulator  250   a  and the insulator  250   b ) is preferably reduced. The thickness of the insulator  250  is preferably greater than or equal to 1 nm and less than or equal to 20 nm. In particular, the thickness of the insulator  250   a  is preferably greater than or equal to 0.5 nm and less than or equal to 15.0 nm. 
     In the case where the insulator  250  has a stacked-layer structure of two layers as illustrated in  FIG.  1 B  and  FIG.  1 C , it is preferable that the insulator  250   a  that is a lower layer be formed using an insulator that is likely to transmit oxygen and the insulator  250   b  that is an upper layer be formed using an insulator having a function of inhibiting oxygen diffusion. With such a structure, oxygen contained in the insulator  250   a  can be inhibited from diffusing into the conductor  260 . That is, a reduction in the amount of oxygen supplied to the oxide  230  can be inhibited. In addition, oxidation of the conductor  260  due to oxygen contained in the insulator  250   a  can be inhibited. For example, it is preferable that the insulator  250   a  be provided using any of the above-described materials that can be used for the insulator  250  and the insulator  250   b  be provided using an insulator containing an oxide of one or both of aluminum and hafnium. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used. 
     In this embodiment, hafnium oxide is used as the insulator  250   b . The thickness of the insulator  250   b  is greater than or equal to 0.5 nm and less than or equal to 5.0 nm, preferably greater than or equal to 1.0 nm and less than or equal to 5.0 nm, further preferably greater than or equal to 1.0 nm and less than or equal to 3.0 nm. 
     The insulator  250   a  can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, and is preferably formed by a PEALD (Plasma-Enhanced ALD) method using a gas  401  (precursor) containing silicon but not containing hydrocarbon, an oxidizing gas (reactant)  402 , and a dilution gas  405 . 
     The ALD method includes a thermal ALD method, in which a precursor and a reactant react with each other only by a thermal energy, a PEALD method, in which a reactant excited by plasma is used, for example. 
     An ALD method, which enables an atomic layer to be deposited one by one using self-limiting characteristics by atoms, has advantages such as deposition of an extremely thin film, deposition on a component with a high aspect ratio, deposition of a film with a small number of defects such as pinholes, deposition with excellent coverage, and low-temperature deposition. The use of plasma in a PEALD method is sometimes preferable because deposition at a lower temperature is possible. Note that some of precursors usable in an ALD method contain carbon or the like. Thus, in some cases, a film provided by an ALD method contains impurities such as carbon in a larger amount than a film provided by another deposition method. Note that impurities can be quantified by secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). 
     In this embodiment, a PEALD method is used. As the gas containing silicon but not containing hydrocarbon, SiH 4 , Si 2 H 6 , SiF 4 , SiCl 4 , SiBr 4 , SiH 2 Cl 2 , SiH 2 I 2 , or the like can be used. As the oxidizing gas  402 , O 2 , O 3 , N 2 O, NO 2 , H 2 O, or the like can be used. As the dilution gas, one or more of Na, He, Ne, Ar, Kr, Xe, and the like can be used. In this embodiment, SiH 4 , N 2 O, and Na are used as the gas  401  containing silicon but not containing hydrocarbon, the oxidizing gas  402 , and the dilution gas  405 , respectively. 
       FIG.  5    illustrates a process flow chart showing a process in which silicon oxide to be the insulator  250   a  is formed by a PEALD method using SiH 4  as the gas  401  containing silicon but not containing hydrocarbon, N 2 O as the oxidizing gas  402 , and Na as the dilution gas  405 .  FIG.  6 A  shows a deposition sequence. 
     First, SiH 4 , N 2 O, and Na are introduced into a reaction chamber (ON), and the pressure in the reaction chamber is kept constant (Step S 01 ). As for the flow rate ratio between the flow rate of SiH 4  and the flow rate of N 2 O to which the flow rate of Na is added, when the flow rate of SiH 4  is 1, the flow rate of N 2 O to which the flow rate of Na is added is higher than or equal to 10 and lower than or equal to 3000, preferably higher than or equal to 10 and lower than or equal to 800, further preferably higher than or equal to 50 and lower than or equal to 400. In addition, as for the flow rate ratio between the flow rate of N 2 O and the flow rate of Na, when the flow rate of N 2 O is 1, the flow rate of N 2  is greater than or equal to 0.1 and less than or equal to 10, preferably greater than or equal to 0.5 and less than or equal to 8, further preferably greater than or equal to 1 and less than or equal to 5. The pressure in the reaction chamber is higher than or equal to 200 Pa and lower than or equal to 1200 Pa, preferably higher than or equal to 400 Pa and lower than or equal to 1000 Pa, further preferably higher than or equal to 600 Pa and lower than or equal to 800 Pa. The substrate temperature is higher than or equal to 100° C. and lower than or equal to 500° C., preferably higher than or equal to 200° C. and lower than or equal to 400° C. The substrate is not necessarily heated, and deposition may be performed at room temperature. 
     Next, the introduction of SiH 4  is stopped (OFF), N 2 O and Na are introduced as introduction gases, and SiH 4  remaining in the reaction chamber is purged (Step S 02 ). 
     Next, high-frequency power  403  is applied to the reaction chamber (ON), and plasma based on N 2 O and N 2  is generated. The high frequency is preferably higher than or equal to 13.56 MHz and lower than or equal to 60 MHz. When SiHx adsorbed onto a formation surface in Step S 01  is oxidized by N 2 O and N 2  plasma, silicon oxide of approximately one molecular layer can be formed (Step S 03 : deposition step). Note that nitrogen supplied by N 2 O and N 2  plasma is contained in the silicon oxide in some cases. Silicon oxide containing nitrogen is referred to as silicon oxynitride in some cases. 
     Next, application of the high-frequency power  403  is stopped (OFF) (Step S 04 ). 
     When Step S 01  to Step S 04  described above are regarded as one cycle and repeated until a desired thickness is obtained, silicon oxide to be the insulator  250   a  can be formed. The number of cycles is more than or equal to 1 and less than or equal to 800. As shown in  FIG.  6 B , in Step S 02 , a step of evacuation to a vacuum may be added in which the introduction of SiH 4 , N 2 O and N 2  is stopped (OFF) and SiH 4 , N 2 O and N 2  remaining in the reaction chamber are evacuated. At this time, the introduction of SiH 4  and the introduction of N 2 O and N 2  may be stopped at a time, or the introduction of N 2 O and N 2  may be stopped after stopping the introduction of SiH 4 . The introduction of N 2 O and N 2  is preferably restarted (ON) before the start of Step S 03 . 
     The silicon oxide to be the insulator  250   a  that is formed in the above can be a favorable insulator with reduced concentrations of hydrogen and carbon, as compared with silicon oxide that is formed by a PECVD method using SiH 4  and N 2 O. 
     In the PECVD method using SiH 4  and N 2 O, high-frequency power is applied in the state where SiH 4  and N 2 O are introduced to generate plasma, so that SiH 4  is decomposed in the plasma and a large number of hydrogen radicals are generated, and thus hydrogen enters the silicon oxide to be the insulator  250   a.    
     In contrast, in the PEALD method using SiH 4 , N 2 O and N 2  that is one embodiment of the present invention, high-frequency power is not applied while SiH 4 , N 2 O and N 2  are introduced in Step S 01  above, remaining SiH 4  is purged in Step S 02 , and then high-frequency power is applied in the state where N 2 O and N 2  are introduced to generate plasma in Step S 03 ; thus, generation of hydrogen radicals can be inhibited. Accordingly, entry of hydrogen into the silicon oxide to be the insulator  250   a  can be inhibited. In the PEALD method using SiH 4 , N 2 O and N 2 , SiH 4  is used as a precursor, and a precursor containing an impurity such as carbon, e.g., an organic precursor containing hydrocarbon, is not used; thus, entry of hydrocarbon, an impurity such as carbon, or the like into the silicon oxide to be the insulator  250   a  can be inhibited. The silicon oxide formed in such a manner is a denser film with a reduced impurity concentration, and thus diffusion of In from the region  230   bc  in the oxide  230   b  into the silicon oxide to be the insulator  250   a  can be prevented. 
     As described above, in one embodiment of the present invention, the dilution gas N 2  is added to the oxidizing gas N 2 O and then the precursor SiH 4  is oxidized, and thereby silicon oxide can be formed. By adding the dilution gas N 2  to the oxidizing gas N 2 O, the use amount of the oxidizing gas N 2 O can be reduced, leading to reduction the manufacturing cost, which is preferable. 
     The insulator  252  is provided to be in contact with the side surface of the conductor  242 , whereby the oxidation of the side surface of the conductor  242  can be prevented, for the side surface of the conductor  242  is not directly exposed to the plasma due to the oxidizing gas in the formation of the insulator  250   a.    
     The concentration of impurities in the silicon oxide to be the insulator  250   a  is preferably reduced as much as possible; however, the lower limit may be set depending on the measurement accuracy or the like of SIMS analysis. The hydrogen concentration in the silicon oxide to be the insulator  250   a  is preferably higher than or equal to 1×10 19  atoms/cm 3  and lower than or equal to 3×10 20  atoms/cm 3 , further preferably higher than or equal to 3×10 18  atoms/cm 3  and lower than or equal to 1×10 20  atoms/cm 3  in SIMS analysis. The carbon concentration in the silicon oxide to be the insulator  250   a  is preferably higher than or equal to 1×10 18  atoms/cm 3  and lower than or equal to 5×10 20  atoms/cm 3 , further preferably higher than or equal to 5×10 18  atoms/cm 3  and lower than or equal to 1×10 20  atoms/cm 3  in the SIMS analysis. The silicon oxide to be the insulator  250   a  contains nitrogen, and the nitrogen concentration is preferably higher than or equal to 3×10 19  atoms/cm 3  and lower than or equal to 1×10 21  atoms/cm 3 , further preferably higher than or equal to 1×10 19  atoms/cm 3  and lower than or equal to 2×10 20  atoms/cm 3  in the SIMS analysis. Furthermore, the concentration of In contained in the silicon oxide to be the insulator  250   a  is preferably lower than or equal to 1.0×10 19  atoms/cm 3 , further preferably lower than or equal to 1.0×10 18  atoms/cm 3 , still further preferably lower than or equal to 1.0×10 17  atoms/cm 3  in the SIMS analysis. 
     Note that in the case where silicon oxide to be the insulator  250   a  is in contact with the insulator  252 , the above carbon concentration, nitrogen concentration, and In concentration in the insulator are concentrations in a region at a distance of greater than or equal to 1 nm apart from an interface between the silicon oxide and the insulator  252  in some cases. 
     As described above, when the silicon oxide to be the insulator  250   a  is formed by the PEALD method, which is one embodiment of the present invention, using a gas (precursor) containing silicon but not containing hydrocarbon, an oxidizing gas (reactant), and a dilution gas, a transistor can have excellent electric characteristics and high reliability. 
     In the case where silicon oxide, silicon oxynitride, or the like is used for the insulator  250   a , the insulator  250   b  may be formed using an insulating material that is a high-k material having a high relative dielectric constant. The gate insulator having a stacked-layer structure of the insulator  250   a  and the insulator  250   b  can be thermally stable and can have a high dielectric constant. Thus, a gate potential that is applied during operation of the transistor can be reduced while the physical thickness of the gate insulator is maintained. In addition, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. 
     The insulator  250  may have a single-layer structure or a stacked-layer structure of three or more layers. For example, as illustrated in  FIG.  3 B , an insulator  250   c  may be provided between the insulator  250   b  and the conductor  260   a . Any of the above-described insulators that can be used for the insulator  250   b  may be used as the insulator  250   c . As the insulator  250   c , a barrier insulating film against hydrogen is preferably used. This can prevent diffusion of impurities such as hydrogen contained in the conductor  260  into the insulator  250   b , the insulator  250   a , and the oxide  230   b . For example, silicon nitride deposited by a PEALD method may be used as the insulator  250   c.    
     A metal oxide may be provided between the insulator  250  and the conductor  260 . The metal oxide preferably inhibits diffusion of oxygen from the insulator  250  into the conductor  260 . Providing the metal oxide that inhibits diffusion of oxygen inhibits diffusion of oxygen from the insulator  250  into the conductor  260 . That is, a reduction in the amount of oxygen supplied to the oxide  230  can be inhibited. Moreover, oxidation of the conductor  260  due to oxygen in the insulator  250  can be inhibited. 
     Note that the metal oxide may function as part of the first gate electrode. For example, a metal oxide that can be used as the oxide  230  can be used as the metal oxide. In that case, when the conductor  260   a  is deposited by a sputtering method, the metal oxide can have a reduced electric resistance value to serve as a conductor. Such a conductor can be referred to as an OC (Oxide Conductor) electrode. 
     With the metal oxide, the on-state current of the transistor  200  can be increased without a reduction in the influence of the electric field from the conductor  260 . Since a distance between the conductor  260  and the oxide  230  is kept by the physical thicknesses of the insulator  250  and the metal oxide, a leakage current between the conductor  260  and the oxide  230  can be inhibited. Moreover, when the stacked-layer structure of the insulator  250  and the metal oxide is provided, the physical distance between the conductor  260  and the oxide  230  and the intensity of electric field applied to the oxide  230  from the conductor  260  can be easily adjusted as appropriate. 
     The conductor  260  functions as the first gate electrode of the transistor  200 . The conductor  260  preferably includes the conductor  260   a  and the conductor  260   b  placed over the conductor  260   a . For example, the conductor  260   a  is preferably placed to cover a bottom surface and a side surface of the conductor  260   b . Moreover, as illustrated in  FIG.  1 B  and  FIG.  1 C , the top surface of the conductor  260  is substantially level with the uppermost surface of the insulator  250 . Although the conductor  260  has a two-layer structure of the conductor  260   a  and the conductor  260   b  in  FIG.  1 B  and  FIG.  1 C , the conductor  260  may have a single-layer structure or a stacked-layer structure of three or more layers. 
     For the conductor  260   a , a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule, and a copper atom is preferably used. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like). 
     In addition, when the conductor  260   a  has a function of inhibiting diffusion of oxygen, the conductivity of the conductor  260   b  can be inhibited from being lowered because of oxidation due to oxygen contained in the insulator  250 . As the conductive material having a function of inhibiting diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. 
     The conductor  260  also functions as a wiring and thus is preferably formed using a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used for the conductor  260   b . The conductor  260   b  may have a stacked-layer structure; for example, a stacked-layer structure of the conductive material and titanium or titanium nitride may be employed. 
     In the transistor  200 , the conductor  260  is formed in a self-aligned manner to fill the opening formed in the insulator  280  and the like. The formation of the conductor  260  in this manner allows the conductor  260  to be placed properly in a region between the conductor  242   a  and the conductor  242   b  without alignment. 
     As illustrated in  FIG.  1 C , in the channel width direction of the transistor  200 , with reference to a bottom surface of the insulator  222 , the level of the bottom surface of the conductor  260  in a region where the conductor  260  and the oxide  230   b  do not overlap is preferably lower than the level of a bottom surface of the oxide  230   b . When the conductor  260  functioning as the gate electrode covers the side surface and the top surface of the channel formation region of the oxide  230   b  with the insulator  250  and the like therebetween, the electric field of the conductor  260  can easily act on the entire channel formation region of the oxide  230   b . Thus, the on-state current of the transistor  200  can be increased and the frequency characteristics of the transistor  200  can be improved. With a reference to the bottom surface of the insulator  222 , the difference between the level of the bottom surface of the conductor  260  in a region where the conductor  260  do not overlap the oxide  230   a  or the oxide  230   b  and the level of the bottom surface of the oxide  230   b  is greater than or equal to 0 nm and less than or equal to 100 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm, further preferably greater than or equal to 5 nm and less than or equal to 20 nm. 
     The insulator  280  is provided over the insulator  275 , and the opening is formed in a region where the insulator  250  and the conductor  260  are to be provided. In addition, the top surface of the insulator  280  may be planarized. 
     The insulator  280  functioning as an interlayer film preferably has a low permittivity. When a material with a low permittivity is used for an interlayer film, parasitic capacitance generated between wirings can be reduced. The insulator  280  is preferably provided using a material similar to that for the insulator  216 , for example. In particular, silicon oxide and silicon oxynitride, which have thermal stability, are preferable. Materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are particularly preferable because a region containing oxygen to be released by heating can be easily formed. 
     The concentration of impurities such as water and hydrogen in the insulator  280  is preferably reduced. Oxide containing silicon such as silicon oxide, silicon oxynitride, or the like is used as appropriate for the insulator  280 , for example. 
     The insulator  282  and the insulator  285  preferably function as barrier insulating films that inhibit impurities such as water and hydrogen from diffusing into the insulator  280  from above and preferably have a function of capturing impurities such as hydrogen. The insulator  282  and the insulator  285  preferably function as barrier insulating films that inhibit passage of oxygen. For each of the insulator  282  and the insulator  285 , a metal oxide having an amorphous structure, for example, an insulator such as aluminum oxide can be used. The insulator  282 , which has a function of capturing impurities such as hydrogen, is provided in contact with the insulator  280  in a region sandwiched between the insulator  212  and the insulator  283 , whereby impurities such as hydrogen contained in the insulator  280  and the like can be captured and the amount of hydrogen in the region can be constant. It is preferable to use, in particular, aluminum oxide having an amorphous structure or amorphous aluminum oxide for the insulator  282  and the insulator  285  because hydrogen can be captured or fixed more effectively in some cases. Accordingly, the transistor  200  and a semiconductor device which have favorable characteristics and high reliability can be manufactured. 
     The insulator  283  functions as a barrier insulating film that inhibits impurities such as water and hydrogen from diffusing into the insulator  280  from above. The insulator  283  is placed over the insulator  282 . The insulator  283  is preferably formed using a nitride containing silicon such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by a sputtering method may be used for the insulator  283 . When the insulator  283  is deposited by a sputtering method, high-density silicon nitride where a void or the like is less likely to be formed can be formed. To obtain the insulator  283 , silicon nitride deposited by a PEALD method or a CVD method may be stacked over silicon nitride deposited by a sputtering method. 
     For the conductor  240   a  and the conductor  240   b , a conductive material containing tungsten, copper, or aluminum as its main component is preferably used. The conductor  240   a  and the conductor  240   b  may each have a stacked-layer structure. 
     In the case where the conductor  240  has a stacked-layer structure, a conductive material having a function of inhibiting passage of impurities such as water and hydrogen is preferably used for a conductor in contact with the insulator  285 , the insulator  283 , the insulator  282 , the insulator  280 , the insulator  275 , and the insulator  271 . For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. The conductive material having a function of inhibiting passage of impurities such as water and hydrogen may be used as a single layer or stacked layers. Moreover, impurities such as water and hydrogen contained in a layer above the insulator  283  can be inhibited from entering the oxide  230  through the conductor  240   a  and the conductor  240   b.    
     For the insulator  241   a  and the insulator  241   b , for example, a barrier insulating film that can be used for the insulator  275  or the like may be used. For the insulator  241   a  and the insulator  241   b , for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator  241   a  and the insulator  241   b  are provided in contact with the insulator  283 , the insulator  282 , and the insulator  271 , impurities such as water and hydrogen contained in the insulator  280  or the like can be inhibited from entering the oxide  230  through the conductor  240   a  and the conductor  240   b . In particular, silicon nitride is suitable because of its high blocking property against hydrogen. Furthermore, oxygen contained in the insulator  280  can be prevented from being absorbed by the conductor  240   a  and the conductor  240   b.    
     When the insulator  241   a  and the insulator  241   b  each have a stacked-layer structure illustrated in  FIG.  1 B , a first insulator in contact with an inner wall of the opening formed in the insulator  280  and the like and a second insulator on the inner side of the first insulator are preferably formed using a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen. 
     For example, aluminum oxide deposited by an ALD method may be used as the first insulator and silicon nitride deposited by a PEALD method may be used as the second insulator. With this structure, oxidation of the conductor  240  can be inhibited, and hydrogen can be prevented from entering the conductor  240 . 
     The conductor  246  (the conductor  246   a  and the conductor  246   b ) functioning as a wiring may be placed in contact with a top surface of the conductor  240   a  and a top surface of the conductor  240   b . The conductor  246  is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. Furthermore, the conductor may have a stacked-layer structure and may be a stack of titanium or titanium nitride and the conductive material, for example. Note that the conductor may be formed to be embedded in an opening provided in an insulator. 
     &lt;Component Materials of Semiconductor Device&gt; 
     Component materials that can be used for the semiconductor device are described below. 
     &lt;&lt;Substrate&gt;&gt; 
     As a substrate where the transistor  200  is formed, an insulator substrate, a semiconductor substrate, or a conductor substrate is used, for example. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate using silicon or germanium as a material and a compound semiconductor substrate including silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Another example is a semiconductor substrate having an insulator region in the semiconductor substrate described above, e.g., an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Other examples include a substrate including a metal nitride and a substrate including a metal oxide. Other examples include an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator. Alternatively, these substrates provided with elements may be used. Examples of the element provided for the substrate include a capacitor element, a resistor, a switching element, a light-emitting element, and a storage element. 
     &lt;&lt;Insulator&gt;&gt; 
     Examples of the insulator include an insulating oxide, an insulating nitride, an insulating oxynitride, an insulating nitride oxide, an insulating metal oxide, an insulating metal oxynitride, and an insulating metal nitride oxide. 
     As miniaturization and high integration of transistors progress, for example, a problem such as a leakage current may arise because of a thinner gate insulator. When a high-k material is used for the insulator functioning as a gate insulator, the voltage during operation of the transistor can be lowered while the physical thickness of the gate insulator is maintained. In contrast, when a material with a low dielectric constant is used for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Thus, a material is preferably selected depending on the function of an insulator. 
     Examples of the insulator with a high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium. 
     Examples of the insulator with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin. 
     When a transistor using a metal oxide is surrounded by an insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, the transistor can have stable electrical characteristics. As the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, a single layer or stacked layers of an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum are used. Specifically, as the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride can be used. 
     The insulator functioning as the gate insulator is preferably an insulator including a region containing oxygen to be released by heating. For example, when a structure is employed in which silicon oxide or silicon oxynitride including a region containing oxygen to be released by heating is in contact with the oxide  230 , oxygen vacancies included in the oxide  230  can be compensated for. 
     &lt;&lt;Conductor&gt;&gt; 
     As a conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like; an alloy containing any of the above metal elements; an alloy containing a combination of the above metal elements; or the like. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferable because they are oxidation-resistant conductive materials or materials that retain their conductivity even after absorbing oxygen. Alternatively, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used. 
     A stack of a plurality of conductive layers formed of the above materials may be used. For example, a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen may be employed. Alternatively, a stacked-layer structure combining a material containing the above metal element and a conductive material containing nitrogen may be employed. Alternatively, a stacked-layer structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed. 
     In the case where an oxide is used for the channel formation region of the transistor, the conductor functioning as the gate electrode preferably employs a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. When the conductive material containing oxygen is provided on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region. 
     For the conductor functioning as the gate electrode, it is preferable to use, in particular, a conductive material containing oxygen and a metal element contained in the metal oxide where the channel is formed. Alternatively, a conductive material containing the above metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Indium gallium zinc oxide containing nitrogen may be used. With the use of such a material, hydrogen contained in the metal oxide where the channel is formed can be captured in some cases. Alternatively, hydrogen entering from an external insulator or the like can be captured in some cases. 
     &lt;&lt;Metal Oxide&gt;&gt; 
     The oxide  230  is preferably formed using a metal oxide functioning as a semiconductor (an oxide semiconductor). A metal oxide that can be used as the oxide  230  of the present invention is described below. 
     The metal oxide preferably contains at least indium or zinc. In particular, indium and zinc are preferably contained. Furthermore, aluminum, gallium, yttrium, tin, or the like is preferably contained in addition to them. Furthermore, one kind or a plurality of kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like may be contained. 
     Here, the case where the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, or tin. Examples of other elements that can be used as the element Minclude boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. Note that a combination of two or more of the above elements may be used as the element M. 
     Note that in this specification and the like, a metal oxide containing nitrogen is also collectively referred to as a metal oxide in some cases. A metal oxide containing nitrogen may be referred to as a metal oxynitride. 
     &lt;Classification of Crystal Structures&gt; 
     First, the classification of crystal structures of an oxide semiconductor is described with reference to  FIG.  4 A .  FIG.  4 A  is a diagram showing the classification of crystal structures of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn). 
     As shown in  FIG.  4 A , an oxide semiconductor is roughly classified into “Amorphous”, “Crystalline”, and “Crystal”. “Amorphous” includes completely amorphous. “Crystalline” includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). Note that “Crystalline” excludes single crystal, poly crystal, and completely amorphous. “Crystal” includes single crystal and poly crystal. 
     Note that the structures in the thick frame in  FIG.  4 A  are in an intermediate state between “Amorphous” and “Crystal”, and belong to a new crystalline phase. That is, these structures are completely different from “Amorphous”, which is energetically unstable, and “Crystal”. 
     A crystal structure of a film or a substrate can be evaluated with an X-Ray Diffraction (XRD) spectrum.  FIG.  4 B  shows an XRD spectrum, which is obtained by GIXD (Grazing-Incidence XRD) measurement, of a CAAC-IGZO film classified into “Crystalline”. Note that a GIXD method is also referred to as a thin film method or a Seemann—Bohlin method. The XRD spectrum that is shown in  FIG.  4 B  and obtained by GIXD measurement is hereinafter simply referred to as an XRD spectrum. The CAAC-IGZO film in  FIG.  4 B  has a composition in the neighborhood of In:Ga:Zn=4:2:3 [atomic ratio]. The CAAC-IGZO film in  FIG.  4 B  has a thickness of 500 nm. 
     As shown in  FIG.  4 B , a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis alignment is detected at  20  of around 31° in the XRD spectrum of the CAAC-IGZO film. As shown in  FIG.  4 B , the peak at  20  of around 31° is asymmetric with respect to the axis of the angle at which the peak intensity is detected. 
     A crystal structure of a film or a substrate can also be evaluated with a diffraction pattern obtained by a nanobeam electron diffraction (NBED) method (such a pattern is also referred to as a nanobeam electron diffraction pattern).  FIG.  4 C  shows a diffraction pattern of the CAAC-IGZO film.  FIG.  4 C  shows a diffraction pattern obtained by the NBED in which an electron beam is incident in the direction parallel to the substrate. The CAAC-IGZO film in  FIG.  4 C  has a composition in the neighborhood of In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm. 
     As shown in  FIG.  4 C , a plurality of spots indicating c-axis alignment are observed in the diffraction pattern of the CAAC-IGZO film. 
     &lt;&lt;Structure of Oxide Semiconductor&gt;&gt; 
     Oxide semiconductors might be classified in a manner different from that in  FIG.  4 A  when classified in terms of the crystal structure. Oxide semiconductors are classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor, for example. Examples of the non-single-crystal oxide semiconductor include the above-described CAAC-OS and nc-OS. Other examples of the non-single-crystal oxide semiconductor include a polycrystalline oxide semiconductor, an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor. 
     Here, the above-described CAAC-OS, nc-OS, and a-like OS are described in detail. 
     [CAAC-05] 
     The CAAC-OS is an oxide semiconductor that has a plurality of crystal regions each of which has c-axis alignment in a particular direction. Note that the particular direction refers to the film thickness direction of a CAAC-OS film, the normal direction of the surface where the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystal region refers to a region having a periodic atomic arrangement. When an atomic arrangement is regarded as a lattice arrangement, the crystal region also refers to a region with a uniform lattice arrangement. The CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and the region has distortion in some cases. Note that the distortion refers to a portion where the direction of a lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where a plurality of crystal regions are connected. That is, the CAAC-OS is an oxide semiconductor having c-axis alignment and having no clear alignment in the a-b plane direction. 
     Note that each of the plurality of crystal regions is formed of one or more fine crystals (crystals each of which has a maximum diameter of less than 10 nm). In the case where the crystal region is formed of one fine crystal, the maximum diameter of the crystal region is less than 10 nm. In the case where the crystal region is formed of a large number of fine crystals, the size of the crystal region may be approximately several tens of nanometers. 
     In the case of an In-M-Zn oxide (the element M is one or more kinds selected from aluminum, gallium, yttrium, tin, titanium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, an (M,Zn) layer) are stacked. Indium and the element M can be replaced with each other. Therefore, indium may be contained in the (M,Zn) layer. In addition, the element M may be contained in the In layer. Note that Zn may be contained in the In layer. Such a layered structure is observed as a lattice image in a high-resolution TEM image, for example. 
     When the CAAC-OS film is subjected to structural analysis by out-of-plane XRD measurement with an XRD apparatus using θ/2θ scanning, for example, a peak indicating c-axis alignment is detected at  20  of 31° or around 31°. Note that the position of the peak indicating c-axis alignment (the value of 20) may change depending on the kind, composition, or the like of the metal element contained in the CAAC-OS. 
     For example, a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that one spot and another spot are observed point-symmetrically with a spot of the incident electron beam passing through a sample (also referred to as a direct spot) as the symmetric center. 
     When the crystal region is observed from the particular direction, a lattice arrangement in the crystal region is basically a hexagonal lattice arrangement; however, a unit lattice is not always a regular hexagon and is a non-regular hexagon in some cases. A pentagonal lattice arrangement, a heptagonal lattice arrangement, and the like are included in the distortion in some cases. Note that a clear crystal grain boundary (grain boundary) cannot be observed even in the vicinity of the distortion in the CAAC-OS. That is, formation of a crystal grain boundary is inhibited by the distortion of lattice arrangement. This is probably because the CAAC-OS can tolerate distortion owing to a low density of arrangement of oxygen atoms in the a-b plane direction, an interatomic bond distance changed by substitution of a metal atom, and the like. 
     A crystal structure in which a clear crystal grain boundary is observed is what is called polycrystal. It is highly probable that the crystal grain boundary becomes a recombination center and captures carriers and thus decreases the on-state current and field-effect mobility of a transistor, for example. Thus, the CAAC-OS in which no clear crystal grain boundary is observed is one of crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that Zn is preferably contained to form the CAAC-OS. For example, an In—Zn oxide and an In—Ga—Zn oxide are suitable because they can inhibit generation of a crystal grain boundary as compared with an In oxide. 
     The CAAC-OS is an oxide semiconductor with high crystallinity in which no clear crystal grain boundary is observed. Thus, in the CAAC-OS, reduction in electron mobility due to the crystal grain boundary is less likely to occur. Moreover, since the crystallinity of an oxide semiconductor might be decreased by entry of impurities, formation of defects, or the like, the CAAC-OS can be regarded as an oxide semiconductor that has small amounts of impurities and defects (e.g., oxygen vacancies). Thus, an oxide semiconductor including the CAAC-OS is physically stable. Therefore, the oxide semiconductor including the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable with respect to high temperatures in the manufacturing process (what is called thermal budget). Accordingly, the use of the CAAC-OS for the OS transistor can extend the degree of freedom of the manufacturing process. 
     [Nc-OS] 
     In the nc-OS, a microscopic region (e.g., a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. In other words, the nc-OS includes a fine crystal. Note that the size of the fine crystal is, for example, greater than or equal to 1 nm and less than or equal to 10 nm, particularly greater than or equal to 1 nm and less than or equal to 3 nm; thus, the fine crystal is also referred to as a nanocrystal. Furthermore, there is no regularity of crystal orientation between different nanocrystals in the nc-OS. Thus, the orientation in the whole film is not observed. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor by some analysis methods. For example, when an nc-OS film is subjected to structural analysis using out-of-plane XRD measurement with an XRD apparatus using θ/2θ scanning, a peak indicating crystallinity is not detected. Furthermore, a diffraction pattern like a halo pattern is observed when the nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter greater than the diameter of a nanocrystal (e.g., greater than or equal to 50 nm). Meanwhile, in some cases, a plurality of spots in a ring-like region with a direct spot as the center are observed in the obtained electron diffraction pattern when the nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter nearly equal to or less than the diameter of a nanocrystal (e.g., greater than or equal to 1 nm and less than or equal to 30 nm). 
     [a-like OS] 
     The a-like OS is an oxide semiconductor having a structure between those of the nc-OS and the amorphous oxide semiconductor. The a-like OS includes a void or a low-density region. That is, the a-like OS has low crystallinity as compared with the nc-OS and the CAAC-OS. Moreover, the a-like OS has higher hydrogen concentration in the film than the nc-OS and the CAAC-OS. 
     &lt;&lt;Structure of Oxide Semiconductor&gt;&gt; 
     Next, the above-described CAC-OS is described in detail. Note that the CAC-OS relates to the material composition. 
     [CAC-OS] 
     The CAC-OS refers to one composition of a material in which elements constituting a metal oxide are unevenly distributed with a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size, for example. Note that a state in which one or more metal elements are unevenly distributed and regions including the metal element(s) are mixed with a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size in a metal oxide is hereinafter referred to as a mosaic pattern or a patch-like pattern. 
     In addition, the CAC-OS has a composition in which materials are separated into a first region and a second region to form a mosaic pattern, and the first regions are distributed in the film (this composition is hereinafter also referred to as a cloud-like composition). That is, the CAC-OS is a composite metal oxide having a composition in which the first regions and the second regions are mixed. 
     Here, the atomic ratios of In, Ga, and Zn to the metal elements contained in the CAC-OS in an In—Ga—Zn oxide are denoted by [In], [Ga], and [Zn], respectively. For example, the first region in the CAC-OS in the In—Ga—Zn oxide has [In] higher than [In] in the composition of the CAC-OS film. Moreover, the second region has [Ga] higher than [Ga] in the composition of the CAC-OS film. For example, the first region has higher [In] than the second region and has lower [Ga] than the second region. Moreover, the second region has higher [Ga] than the first region and has lower [In] than the first region. 
     Specifically, the first region includes indium oxide, indium zinc oxide, or the like as its main component. The second region includes gallium oxide, gallium zinc oxide, or the like as its main component. That is, the first region can be referred to as a region containing In as its main component. The second region can be referred to as a region containing Ga as its main component. 
     Note that a clear boundary between the first region and the second region cannot be observed in some cases. 
     For example, energy dispersive X-ray spectroscopy (EDX) is used to obtain EDX mapping, and according to the EDX mapping, the CAC-OS in the In—Ga—Zn oxide has a structure in which the region containing In as its main component (the first region) and the region containing Ga as its main component (the second region) are unevenly distributed and mixed. 
     In the case where the CAC-OS is used for a transistor, a switching function (on/off switching function) can be given to the CAC-OS owing to the complementary action of the conductivity derived from the first region and the insulating property derived from the second region. That is, the CAC-OS has a conducting function in part of the material and has an insulating function in another part of the material; as a whole, the CAC-OS has a function of a semiconductor. Separation of the conducting function and the insulating function can maximize each function. Accordingly, when the CAC-OS is used for a transistor, high on-state current (I on ), high field-effect mobility (μ), and excellent switching operation can be achieved. 
     An oxide semiconductor has various structures with different properties. Two or more kinds among the amorphous oxide semiconductor, the polycrystalline oxide semiconductor, the a-like OS, the CAC-OS, the nc-OS, and the CAAC-OS may be included in the oxide semiconductor of one embodiment of the present invention. 
     &lt;Transistor Including Oxide Semiconductor&gt; 
     Next, the case where the above oxide semiconductor is used for a transistor is described. 
     When the above oxide semiconductor is used for a transistor, a transistor with high field-effect mobility can be achieved. In addition, a transistor having high reliability can be achieved. 
     An oxide semiconductor with a low carrier concentration is preferably used for a channel formation region of the transistor. For example, the carrier concentration in an oxide semiconductor in the channel formation region is lower than or equal to 1×10 17  cm −3 , preferably lower than or equal to 1×10 15  cm −3 , further preferably lower than or equal to 1×10 13  cm −3 , still further preferably lower than or equal to 1×10 11  cm −3 , yet further preferably lower than 1×10 10  cm −3 , and higher than or equal to 1×10 −9  cm −3 . In order to reduce the carrier concentration in an oxide semiconductor film, the impurity concentration in the oxide semiconductor film is reduced so that the density of defect states can be reduced. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. Note that an oxide semiconductor with a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. 
     A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and accordingly has a low density of trap states in some cases. 
     Electric charge trapped by the trap states in the oxide semiconductor takes a long time to disappear and might behave like fixed electric charge. Thus, a transistor whose channel formation region is formed in an oxide semiconductor with a high density of trap states has unstable electrical characteristics in some cases. 
     Accordingly, in order to obtain stable electrical characteristics of a transistor, reducing the impurity concentration in an oxide semiconductor is effective. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable that the impurity concentration in an adjacent film be also reduced. Examples of impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon. 
     &lt;Impurity&gt; 
     Here, the influence of each impurity in the oxide semiconductor is described. 
     When silicon or carbon, which is one of Group 14 elements, is contained in the oxide semiconductor, defect states are formed in the oxide semiconductor. Thus, the concentration of silicon or carbon in the channel formation region in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of an interface with in the channel formation region in the oxide semiconductor (the concentrations obtained by SIMS) are each set lower than or equal to 2×10 18  atoms/cm 3 , preferably lower than or equal to 2×10 17  atoms/cm 3 . 
     When the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are formed and carriers are generated in some cases. Thus, a transistor using an oxide semiconductor that contains an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Thus, the concentration of an alkali metal or an alkaline earth metal in the channel formation region in the oxide semiconductor, which is obtained by SIMS, is lower than or equal to 1×10 18  atoms/cm 3 , preferably lower than or equal to 2×10 16  atoms/cm 3 . 
     Furthermore, when the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type by generation of electrons serving as carriers and an increase in carrier concentration. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. When nitrogen is contained in the oxide semiconductor, a trap state is sometimes formed. This might make the electrical characteristics of the transistor unstable. Therefore, the concentration of nitrogen in the channel formation region in the oxide semiconductor, which is obtained by SIMS, is set lower than 5×10 19  atoms/cm 3 , preferably lower than or equal to 5×10 18  atoms/cm 3 , further preferably lower than or equal to 1×10 18  atoms/cm 3 , still further preferably lower than or equal to 5×10 17  atoms/cm 3 . 
     Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, and thus forms an oxygen vacancy in some cases. Entry of hydrogen into the oxygen vacancy generates an electron serving as a carrier in some cases. Furthermore, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier in some cases. Thus, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Accordingly, hydrogen in the channel formation region in the oxide semiconductor is preferably reduced as much as possible. Specifically, the hydrogen concentration in the channel formation region in the oxide semiconductor, which is obtained by SIMS, is set lower than 1×10 20  atoms/cm 3 , preferably lower than 5×10 19  atoms/cm 3 , further preferably lower than 1×10 19  atoms/cm 3 , still further preferably lower than 5×10 18  atoms/cm 3 , yet still further preferably lower than 1×10 18  atoms/cm 3 . 
     When an oxide semiconductor with sufficiently reduced impurities is used for the channel formation region of the transistor, stable electrical characteristics can be given. 
     &lt;&lt;Other Semiconductor Materials&gt;&gt; 
     A semiconductor material that can be used for the oxide  230  is not limited to the above metal oxides. A semiconductor material that has a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the oxide  230 . For example, a single element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layered material functioning as a semiconductor (also referred to as an atomic layer material or a two-dimensional material) is preferably used as a semiconductor material. In particular, a layered material functioning as a semiconductor is preferably used as a semiconductor material. 
     Here, in this specification and the like, the layered material generally refers to a group of materials having a layered crystal structure. In the layered crystal structure, layers formed by covalent bonding or ionic bonding are stacked with bonding such as the Van der Waals force, which is weaker than covalent bonding or ionic bonding. The layered material has high electrical conductivity in a monolayer, that is, high two-dimensional electrical conductivity. When a material that functions as a semiconductor and has high two-dimensional electrical conductivity is used for a channel formation region, a transistor having a high on-state current can be provided. 
     Examples of the layered material include graphene, silicene, and chalcogenide. Chalcogenide is a compound containing chalcogen. Chalcogen is a general term of elements belonging to Group 16, which includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenide include transition metal chalcogenide and chalcogenide of Group 13 elements. 
     For the oxide  230 , a transition metal chalcogenide functioning as a semiconductor is preferably used, for example. Specific examples of the transition metal chalcogenide which can be used for the oxide  230  include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), molybdenum telluride (typically MoTe 2 ), tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten telluride (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2 ), zirconium sulfide (typically ZrS 2 ), and zirconium selenide (typically ZrSe 2 ). 
     &lt;Manufacturing Method of Semiconductor Device&gt; 
     Next, a method for manufacturing the semiconductor device that is one embodiment of the present invention and is illustrated in  FIG.  1 A  to  FIG.  1 D  is described with reference to  FIG.  7 A  to  FIG.  18 D . 
     Note that A of each drawing is a top view. Moreover, B of each drawing is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A 1 -A 2  in A of each drawing, and is also a cross-sectional view in the channel length direction of the transistor  200 . Furthermore, C of each drawing is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A 3 -A 4  in A of each drawing, and is also a cross-sectional view in the channel width direction of the transistor  200 . Furthermore, D of each drawing is a cross-sectional view of a portion indicated by dashed-dotted line A 5 -A 6  in A of each drawing. Note that for clarity of the drawing, some components are not illustrated in the top view of A of each drawing. 
     Hereinafter, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. 
     Examples of the sputtering method include an RF sputtering method in which a high-frequency power source is used as a sputtering power source, a DC sputtering method in which a DC power source is used, and a pulsed DC sputtering method in which a voltage applied to an electrode is changed in a pulsed manner. An RF sputtering method is mainly used in the case where an insulating film is deposited, and a DC sputtering method is mainly used in the case where a metal conductive film is deposited. The pulsed DC sputtering method is mainly used in the case where a compound such as an oxide, a nitride, or a carbide is deposited by a reactive sputtering method. 
     Note that the CVD method can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Moreover, the CVD method can be classified into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method depending on a source gas to be used. 
     A high-quality film can be obtained at a relatively low temperature by a plasma enhanced CVD method. Furthermore, a thermal CVD method is a deposition method that does not use plasma and thus enables less plasma damage to an object to be processed. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like), or the like included in a semiconductor device might be charged up by receiving electric charge from plasma. In that case, accumulated electric charge might break the wiring, the electrode, the element, or the like included in the semiconductor device. In contrast, such plasma damage does not occur in the case of a thermal CVD method, which does not use plasma, and thus the yield of the semiconductor device can be increased. In addition, a thermal CVD method does not cause plasma damage during deposition, so that a film with few defects can be obtained. 
     As an ALD method, a thermal ALD method, in which a precursor and a reactant react with each other only by a thermal energy, a PEALD method, in which a reactant excited by plasma is used, and the like can be used. 
     Unlike a deposition method in which particles ejected from a target or the like are deposited, a CVD method and an ALD method are deposition methods in which a film is formed by gas phase reaction at a surface of an object to be processed. Thus, a CVD method and an ALD method are deposition methods that enable favorable step coverage almost regardless of the shape of an object to be processed. In particular, an ALD method has excellent step coverage and excellent thickness uniformity and thus is suitable for covering a surface of an opening portion with a high aspect ratio, for example. On the other hand, an ALD method has a relatively low deposition rate, and thus is preferably used in combination with another deposition method with a high deposition rate, such as a CVD method, in some cases. 
     By a CVD method, a film with a certain composition can be deposited depending on the flow rate ratio of the source gases. For example, by a CVD method, by changing the flow rate ratio of the source gases during the deposition, a film in which the composition is continuously changed can be deposited. In the case where the film is deposited while the flow rate ratio of the source gases is changed, as compared to the case where the film is deposited using a plurality of deposition chambers, the time taken for the deposition can be shortened because the time taken for transfer and pressure adjustment is omitted. Thus, the productivity of the semiconductor device can be increased in some cases. 
     By an ALD method, a film with a certain composition can be deposited by concurrently introducing a plurality of precursors with different compositions or controlling the number of the introduction of each of the plurality of precursors with different compositions in one cycle. 
     First, a substrate (not illustrated) is prepared, and the insulator  212  is deposited over the substrate (see  FIG.  7 A  to  FIG.  7 D ). The insulator  212  is preferably deposited by a sputtering method. By using a sputtering method that does not need to use hydrogen as a deposition gas, the hydrogen concentration in the insulator  212  can be reduced. Without limitation to a sputtering method, the insulator  212  may be deposited by a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. 
     In this embodiment, for the insulator  212 , silicon nitride is deposited by a pulsed DC sputtering method using a silicon target in an atmosphere containing a nitrogen gas. The use of the pulsed DC sputtering method can inhibit generation of particles due to arcing on the target surface, achieving more uniform film thickness. In addition, by using the pulsed voltage, rising and falling in discharge can be made steep as compared with the case where a high-frequency voltage is used. As a result, power can be supplied to an electrode more efficiently to improve the sputtering rate and film quality. 
     The use of an insulator through which impurities such as water and hydrogen are less likely to pass, such as silicon nitride, can inhibit diffusion of impurities such as water and hydrogen contained in a layer below the insulator  212 . When an insulator through which copper is less likely to pass, such as silicon nitride, is used for the insulator  212 , even in the case where a metal that is likely to diffuse, such as copper, is used for a conductor in a layer (not illustrated) below the insulator  212 , upward diffusion of the metal through the insulator  212  can be inhibited. 
     Next, the insulator  214  is deposited over the insulator  212  (see  FIG.  7 A  to  FIG.  7 D ). The insulator  214  is preferably deposited by a sputtering method. By using a sputtering method that does not need to use hydrogen as a deposition gas, the hydrogen concentration in the insulator  214  can be reduced. Without limitation to a sputtering method, the insulator  214  may be deposited by a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. 
     In this embodiment, for the insulator  214 , aluminum oxide is deposited by a pulsed DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas. The use of the pulsed DC sputtering method can achieve more uniform film thickness and improve the sputtering rate and film quality. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen supplied to a layer below the insulator  214  can be controlled depending on the amount of the RF power applied to the substrate. The RF power is higher than or equal to 0 W/cm 2  and lower than or equal to 1.86 W/cm 2 . In other words, the supply amount of oxygen can be changed to be appropriate for the characteristics of the transistor, with the RF power used at the time of forming the insulator  214 . Accordingly, an appropriate amount of oxygen for improving the reliability of the transistor can be supplied. The RF frequency is preferably 10 MHz or higher. The typical frequency is 13.56 MHz. The higher the RF frequency is, the less damage the substrate gets. 
     A metal oxide having an amorphous structure and an excellent function of capturing or fixing hydrogen, such as aluminum oxide, is preferably used for the insulator  214 . In this case, the insulator  214  captures or fixes hydrogen contained in the insulator  216  and the like and prevents the hydrogen from diffusing into the oxide  230 . In particular, it is preferable to use aluminum oxide having an amorphous structure or amorphous aluminum oxide for the insulator  214  because hydrogen can be captured or fixed more effectively in some cases. Accordingly, the transistor  200  and a semiconductor device which have favorable characteristics and high reliability can be manufactured. 
     Next, the insulator  216  is deposited over the insulator  214 . The insulator  216  is preferably deposited by a sputtering method. By using a sputtering method that does not need to use hydrogen as a deposition gas, the hydrogen concentration in the insulator  216  can be reduced. Without limitation to a sputtering method, the insulator  216  may be deposited by a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. 
     In this embodiment, for the insulator  216 , silicon oxide is deposited by a pulsed DC sputtering method using a silicon target in an atmosphere containing an oxygen gas. The use of the pulsed DC sputtering method can achieve more uniform film thickness and improve the sputtering rate and film quality. 
     The insulator  212 , the insulator  214 , and the insulator  216  are preferably successively deposited without exposure to the air. For example, a multi-chamber deposition apparatus is used. As a result, the amounts of hydrogen in the deposited insulator  212 , insulator  214 , and insulator  216  can be reduced, and furthermore, entry of hydrogen into the films in intervals between deposition steps can be inhibited. 
     Then, an opening reaching the insulator  214  is formed in the insulator  216 . Examples of the opening include a groove and a slit. A region where an opening is formed is referred to as an opening portion in some cases. Wet etching can be used for the formation of the opening; however, dry etching is preferably used for microfabrication. As the insulator  214 , it is preferable to select an insulator that functions as an etching stopper film used in forming the groove by etching the insulator  216 . For example, in the case where silicon oxide or silicon oxynitride is used for the insulator  216  in which the groove is to be formed, silicon nitride, aluminum oxide, or hafnium oxide is preferably used for the insulator  214 . 
     As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus including the parallel plate electrodes may have a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure may be employed in which different high-frequency voltages are applied to one of the parallel plate electrodes. Alternatively, a structure may be employed in which high-frequency voltages with the same frequency are applied to the parallel plate electrodes. Alternatively, a structure may be employed in which high-frequency voltages with different frequencies are applied to the parallel plate electrodes. Alternatively, a dry etching apparatus including a high-density plasma source can be used. As the dry etching apparatus including a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus or the like can be used, for example. 
     After the formation of the opening, a conductive film to be the conductor  205   a  is deposited. The conductive film to be the conductor  205   a  desirably includes a conductor having a function of inhibiting passage of oxygen. For example, tantalum nitride, tungsten nitride, or titanium nitride can be used. Alternatively, a stacked-layer film of the conductor having a function of inhibiting passage of oxygen and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film to be the conductor  205   a  can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. 
     In this embodiment, titanium nitride is deposited as the conductive film to be the conductor  205   a . When such a metal nitride is used for a layer under the conductor  205   b , oxidation of the conductor  205   b  by the insulator  216  or the like can be inhibited. Furthermore, even when a metal that is likely to diffuse, such as copper, is used for the conductor  205   b , the metal can be prevented from diffusing to the outside through the conductor  205   a.    
     Next, a conductive film to be the conductor  205   b  is deposited. Tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used for the conductive film to be the conductor  205   b . The conductive film can be deposited by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is deposited for the conductive film to be the conductor  205   b.    
     Next, by performing CMP treatment, the conductive film to be the conductor  205   a  and the conductive film to be the conductor  205   b  are partly removed to expose the insulator  216  (see  FIG.  7 A  to  FIG.  7 D ). As a result, the conductor  205   a  and the conductor  205   b  remain only in the opening portion. Note that the insulator  216  is partly removed by the CMP treatment in some cases. 
     Next, the insulator  222  is deposited over the insulator  216  and the conductor  205  (see  FIG.  8 A  to  FIG.  8 D ). An insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited as the insulator  222 . Note that as the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator  222  has a barrier property against hydrogen and water, hydrogen and water contained in components provided around the transistor  200  are inhibited from diffusing into the transistor  200  through the insulator  222 , and generation of oxygen vacancies in the oxide  230  can be inhibited. 
     The insulator  222  can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, for the insulator  222 , hafnium oxide is deposited by an ALD method. 
     Sequentially, heat treatment is preferably performed. The heat treatment is performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C., further preferably higher than or equal to 320° C. and lower than or equal to 450° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, in the case where the heat treatment is performed in a mixed atmosphere of a nitrogen gas and an oxygen gas, the proportion of the oxygen gas may be approximately 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for released oxygen, after heat treatment is performed in a nitrogen gas or inert gas atmosphere. 
     The gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment is 1 ppb or less, preferably 0.1 ppb or less, further preferably 0.05 ppb or less. The heat treatment using a highly purified gas can prevent entry of moisture or the like into the insulator  222  and the like as much as possible. 
     In this embodiment, as the heat treatment, treatment is performed with a flow rate ratio of a nitrogen gas and an oxygen gas of 4 slm:1 slm at 400° C. for one hour after the deposition of the insulator  222 . By the heat treatment, impurities such as water and hydrogen contained in the insulator  222  can be removed, for example. In the case where an oxide containing hafnium is used for the insulator  222 , the insulator  222  is partly crystallized by the heat treatment in some cases. The heat treatment can also be performed after the deposition of the insulator  224 , for example. 
     Next, an insulating film  224 A is deposited over the insulator  222  (see  FIG.  8 A  to  FIG.  8 D ). The insulating film  224 A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, for the insulating film  224 A, silicon oxide is deposited by a sputtering method. By using a sputtering method that does not need to use hydrogen as a deposition gas, the hydrogen concentration in the insulating film  224 A can be reduced. The hydrogen concentration in the insulating film  224 A is preferably reduced because the insulating film  224 A is in contact with the oxide  230   a  in a later step. 
     Next, an oxide film  230 A and an oxide film  230 B are deposited in this order over the insulating film  224 A (see  FIG.  8 A  to  FIG.  8 D ). Note that it is preferable to deposit the oxide film  230 A and the oxide film  230 B successively without exposure to the air. By the deposition without exposure to the air, impurities or moisture from the atmospheric environment can be prevented from being attached onto the oxide film  230 A and the oxide film  230 B, so that the vicinity of an interface between the oxide film  230 A and the oxide film  230 B can be kept clean. 
     The oxide film  230 A and the oxide film  230 B can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. An ALD method is preferably employed for the deposition of the oxide film  230 A and the oxide film  230 B, in which case a film with a uniform thickness can be formed even in a groove or an opening having a high aspect ratio. Employing a PEALD method is preferable because the oxide film  230 A and the oxide film  230 B can be formed at a lower temperature than that in the case of employing a thermal ALD method. In this embodiment, the oxide film  230 A and the oxide film  230 B are deposited by a sputtering method. 
     For example, in the case where the oxide film  230 A and the oxide film  230 B are deposited by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. Increasing the proportion of oxygen contained in the sputtering gas can increase the amount of excess oxygen in the deposited oxide films. In the case where the oxide films are deposited by a sputtering method, the above In-M-Zn oxide target or the like can be used. 
     In particular, when the oxide film  230 A is deposited, part of oxygen contained in the sputtering gas is supplied to the insulator  224  in some cases. Thus, the proportion of oxygen contained in the sputtering gas is higher than or equal to 70%, preferably higher than or equal to 80%, further preferably 100%. 
     In the case where the oxide film  230 B is formed by a sputtering method and the proportion of oxygen contained in the sputtering gas for deposition is higher than 30% and lower than or equal to 100%, preferably higher than or equal to 70% and lower than or equal to 100%, an oxygen-excess oxide semiconductor is formed. In a transistor using an oxygen-excess oxide semiconductor for its channel formation region, relatively high reliability can be obtained. Note that one embodiment of the present invention is not limited thereto. In the case where the oxide film  230 B is formed by a sputtering method and the proportion of oxygen contained in the sputtering gas for deposition is higher than or equal to 1% and lower than or equal to 30%, preferably higher than or equal to 5% and lower than or equal to 20%, an oxygen-deficient oxide semiconductor is formed. In a transistor using an oxygen-deficient oxide semiconductor for its channel formation region, relatively high field-effect mobility can be obtained. Furthermore, when the deposition is performed while the substrate is being heated, the crystallinity of the oxide film can be improved. 
     In this embodiment, the oxide film  230 A is deposited by a sputtering method using an oxide target with In:Ga:Zn=1:3:4 [atomic ratio]. In addition, the oxide film  230 B is deposited by a sputtering method using an oxide target with In:Ga:Zn=4:2:4.1 [atomic ratio], an oxide target with In:Ga:Zn=1:1:1 [atomic ratio], or an oxide target with In:Ga:Zn=1:1:0.5 [atomic ratio]. Note that each of the oxide films is preferably formed so as to have characteristics required for the oxide  230   a  and the oxide  230   b  by selecting the deposition conditions and the atomic ratios as appropriate. 
     The insulating film  224 A, the oxide film  230 A, and the oxide film  230 B are preferably formed by a sputtering method without exposure to the air. For example, a multi-chamber deposition apparatus is used. As a result, entry of hydrogen into the insulating film  224 A, the oxide film  230 A, and the oxide film  230 B in intervals between deposition steps can be inhibited. 
     Next, heat treatment is preferably performed. The heat treatment can be performed in a temperature range where the oxide film  230 A and the oxide film  230 B do not become polycrystals, i.e., at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 400° C. and lower than or equal to 600° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, in the case where the heat treatment is performed in a mixed atmosphere of a nitrogen gas and an oxygen gas, the proportion of the oxygen gas may be approximately 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for released oxygen, after heat treatment is performed in a nitrogen gas or inert gas atmosphere. 
     The gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. The heat treatment using a highly purified gas can prevent entry of moisture or the like into the oxide film  230 A, the oxide film  230 B, and the like as much as possible. 
     In this embodiment, the heat treatment is performed at 450° C. for one hour with the flow rate ratio of nitrogen gas to oxygen gas being 4 slm: 1 slm. By the heat treatment using the oxygen gas, impurities such as carbon, water and hydrogen in the oxide film  230 A and the oxide film  230 B can be reduced, for example. Furthermore, the reduction of impurities in the films improves the crystallinity of the oxide film  230 B, thereby offering a dense structure with higher density. Thus, crystalline regions in the oxide film  230 A and the oxide film  230 B are expanded, so that in-plane variations of the crystalline regions in the oxide film  230 A and the oxide film  230 B can be reduced. Accordingly, an in-plane variation of electrical characteristics of the transistor  200  can be reduced. 
     Next, a conductive film  242 A is deposited over the oxide film  230 B (see  FIG.  8 A  to  FIG.  8 D ). The conductive film  242 A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, for the conductive film  242 A, tantalum nitride is deposited by a sputtering method. Note that heat treatment may be performed before the deposition of the conductive film  242 A. This heat treatment may be performed under reduced pressure, and the conductive film  242 A may be successively deposited without exposure to the air. The treatment can remove moisture and hydrogen adsorbed onto the surface of the oxide film  230 B, and further can reduce the moisture concentration and the hydrogen concentration in the oxide film  230 A and the oxide film  230 B. The heat treatment is preferably performed at a temperature higher than or equal to 100° C. and lower than or equal to 400° C. In this embodiment, the heat treatment is performed at 200° C. 
     Next, an insulating film  271 A is deposited over the conductive film  242 A (see  FIG.  8 A  to  FIG.  8 D ). The insulating film  271 A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film  271 A, an insulating film having a function of inhibiting passage of oxygen is preferably used. For example, for the insulating film  271 A, aluminum oxide or silicon nitride may be deposited by a sputtering method. 
     Note that the conductive film  242 A and the insulating film  271 A are preferably deposited by a sputtering method without exposure to the air. For example, a multi-chamber deposition apparatus is used. As a result, the amounts of hydrogen in the conductive film  242 A and the insulating film  271 A can be reduced, and furthermore, entry of hydrogen into the films in intervals between deposition steps can be inhibited. In the case where a hard mask is provided over the insulating film  271 A, a film to be the hard mask is preferably successively formed without exposure to the air. 
     Next, the insulating film  224 A, the oxide film  230 A, the oxide film  230 B, the conductive film  242 A, and the insulating film  271 A are processed into island shapes by a lithography method to form the insulator  224 , the oxide  230   a , the oxide  230   b , a conductive layer  242 B, and an insulating layer  271 B (see  FIG.  9 A  to  FIG.  9 D ). Here, the insulator  224 , the oxide  230   a , the oxide  230   b , the conductive layer  242 B, and the insulating layer  271 B are formed such that at least parts thereof are overlapped with the conductor  205 . A dry etching method or a wet etching method can be used for the processing. A dry etching method is suitable for microfabrication. The insulating film  224 A, the oxide film  230 A, the oxide film  230 B, the conductive film  242 A, and the insulating film  271 A may be processed under different conditions. 
     Note that in the lithography method, first, a resist is exposed to light through a mask. Next, a region exposed to light is removed or left using a developing solution, so that a resist mask is formed. Then, etching process through the resist mask is conducted, whereby a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape. The resist mask may be formed through, for example, exposure of the resist to KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be employed in which a gap between a substrate and a projection lens is filled with liquid (e.g., water) in light exposure. Alternatively, an electron beam or an ion beam may be used instead of the light. Note that a mask is unnecessary in the case of using an electron beam or an ion beam. Note that the resist mask can be removed by a dry etching process such as ashing, a wet etching process, a wet etching process after a dry etching process, or a dry etching process after a wet etching process. 
     In addition, a hard mask formed of an insulator or a conductor may be used under the resist mask. In the case of using a hard mask, a hard mask with a desired shape can be formed in the following manner: an insulating film or a conductive film that is the material of the hard mask is formed over the conductive film  242 A, a resist mask is formed thereover, and then the hard mask material is etched. The etching of the conductive film  242 A and the like may be performed after removing the resist mask or with the resist mask remaining. In the latter case, the resist mask sometimes disappears during the etching. The hard mask may be removed by etching after the etching of the conductive film  242 A and the like. Meanwhile, the hard mask is not necessarily removed when the hard mask material does not affect later steps or can be utilized in later steps. In this embodiment, the insulating layer  271 B is used as a hard mask. 
     Here, the insulating layer  271 B functions as a mask for the conductive layer  242 B; thus, as illustrated in  FIG.  9 B  to  FIG.  9 D , the conductive layer  242 B does not have a curved surface between the side surface and the top surface. Thus, end portions at the intersections of the side surfaces and the top surfaces of the conductor  242   a  and the conductor  242   b  illustrated in  FIG.  1 B  and  FIG.  1 D  are angular. The cross-sectional area of the conductor  242  in the case where the end portion at the intersection of the side surface and the top surface of the conductor  242  is angular is larger than that in the case where the end portion is rounded. Accordingly, the resistance of the conductor  242  is reduced, so that the on-state current of the transistor  200  can be increased. 
     Furthermore, as illustrated in  FIG.  9 B  to  FIG.  9 D , the sections of the insulator  224 , the oxide  230   a , the oxide  230   b , the conductive layer  242 B, and the insulating layer  271 B may have tapered shapes. In this specification and the like, a tapered shape indicates a shape in which at least part of a side surface of a structure is inclined to a substrate surface. For example, the angle formed between the inclined side surface and the substrate surface (the angle is also referred to as a taper angle) is preferably less than 90°. Each of the insulator  224 , the oxide  230   a , the oxide  230   b , the conductive layer  242 B, and the insulating layer  271 B may have a taper angle greater than or equal to 60° and less than 90°. With such tapered shapes on the sections, the coverage with the insulator  275  and the like can be improved in a later step, so that defects such as a void can be reduced. 
     Not being limited to the above, the insulator  224 , the oxide  230   a , the oxide  230   b , the conductive layer  242 B, and the insulating layer  271 B may be processed to have side surfaces that are substantially perpendicular to the top surface of the insulator  222 . With this structure, a plurality of the transistors  200  can be provided with high density in a small area. 
     A by-product generated in the above etching step is sometimes formed in a layered manner on the side surfaces of the insulator  224 , the oxide  230   a , the oxide  230   b , the conductive layer  242 B, and the insulating layer  271 B. In this case, the layered by-product is formed between the insulator  275  and the insulator  224 , the oxide  230   a , the oxide  230   b , the conductive layer  242 B, and the insulating layer  271 B. Hence, the layered by-product formed in contact with the top surface of the insulator  222  is preferably removed. 
     Next, the insulator  275  is formed to cover the insulator  224 , the oxide  230   a , the oxide  230   b , the conductive layer  242 B, and the insulating layer  271 B (see  FIG.  10 A  to  FIG.  10 D ). Here, it is preferable that the insulator  275  be in close contact with the top surface of the insulator  222  and the side surface of the insulator  224 . The insulator  275  can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator  275  is preferably formed using an insulating film having a function of inhibiting passage of oxygen. For example, as the insulator  275 , aluminum oxide may be deposited by a sputtering method, and silicon nitride may be deposited thereover by a PEALD method. When the insulator  275  has such a stacked-layer structure, the function of inhibiting diffusion of impurities such as water or hydrogen and oxygen is improved in some cases. 
     In this manner, the oxide  230   a , the oxide  230   b , and the conductive layer  242 B can be covered with the insulator  275  and the insulating layer  271 B, which have a function of inhibiting diffusion of oxygen. This structure can suppress direct diffusion of oxygen from the insulator  280  or the like into the insulator  224 , the oxide  230   a , the oxide  230   b , and the conductive layer  242 B in a later step. 
     Next, an insulating film to be the insulator  280  is deposited over the insulator  275 . The insulating film can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. A silicon oxide film may be deposited by a sputtering method as the insulating film, for example. When the insulating film is deposited by a sputtering method in an oxygen-containing atmosphere, the insulator  280  containing excess oxygen can be formed. Since hydrogen is not used as a deposition gas in the sputtering method, the concentration of hydrogen in the insulator  280  can be reduced. Note that heat treatment may be performed before the insulating film is deposited. The heat treatment may be performed under reduced pressure, and the insulating film may be successively deposited without exposure to the air. The treatment can remove moisture and hydrogen adsorbed onto the surface of the insulator  275  and the like, and further can reduce the moisture concentration and the hydrogen concentration in the oxide  230   a , the oxide  230   b , and the insulator  224 . For the heat treatment, the above heat treatment conditions can be used. 
     Next, the insulating film to be the insulator  280  is subjected to CMP treatment, so that the insulator  280  with a flat top surface is formed (see  FIG.  10 A  to  FIG.  10 D ). Note that, for example, silicon nitride may be deposited over the insulator  280  by a sputtering method and CMP treatment may be performed on the silicon nitride until the insulator  280  is reached. 
     Then, part of the insulator  280 , part of the insulator  275 , and part of the insulating layer  271 B, part of the conductive layer  242 B are processed to form an opening reaching the oxide  230   b . The opening is preferably formed to overlap with the conductor  205 . The insulator  271   a , the insulator  271   b , the conductor  242   a , and the conductor  242   b  are formed through the formation of the opening (see  FIG.  11 A  to  FIG.  11 D ). 
     As illustrated in  FIG.  11 B  and  FIG.  11 C , the side surfaces of the insulator  280 , the insulator  275 , and the insulator  271  and the conductor  242  may be tapered. The taper angle of the insulator  280  is larger than that of the conductor  242  in some cases. Although not illustrated in  FIG.  11 A  to  FIG.  11 C , the upper portion of the oxide  230   b  is removed in some cases when the opening is formed. 
     The part of the insulator  280 , the part of the insulator  275 , the part of the insulating layer  271 B, and the part of the conductive layer  242 B can be processed by a dry etching method or a wet etching method. A dry etching method is suitable for microfabrication. The processing may be performed under different conditions. For example, the part of the insulator  280  may be processed by a dry etching method, the part of the insulator  275  and the part of the insulating layer  271 B may be processed by a wet etching method, and the part of the conductive layer  242 B may be processed by a dry etching method. 
     Here, impurities might be attached onto the side surface of the oxide  230   a , the top surface and the side surface of the oxide  230   b , the side surface of the conductor  242 , the side surface of the insulator  280 , and the like or the impurities might be diffused thereinto. A step of removing the impurities may be performed. In addition, a damaged region might be formed on the surface of the oxide  230   b  by the above dry etching. The damaged region may be removed. The impurities come from components contained in the insulator  280 , the insulator  275 , part of the insulating layer  271 B, and the conductive layer  242 B; components contained in a member of an apparatus used to form the opening; and components contained in a gas or a liquid used for etching, for instance. Examples of the impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine. 
     In particular, impurities such as aluminum and silicon hinder the oxide  230   b  from becoming a CAAC-OS. It is thus preferable to reduce or remove impurity elements such as aluminum and silicon, which hinder the oxide from becoming a CAAC-OS. For example, the concentration of aluminum atoms in the oxide  230   b  and in the vicinity thereof is lower than or equal to 5.0 atomic %, preferably lower than or equal to 2.0 atomic %, further preferably lower than or equal to 1.5 atomic %, still further preferably lower than or equal to 1.0 atomic %, and yet further preferably lower than 0.3 atomic %. 
     Note that in a metal oxide, a region that is hindered from becoming a CAAC-OS by impurities such as aluminum and silicon and becomes an amorphous-like oxide semiconductor (a-like OS) is referred to as a non-CAAC region in some cases. In the non-CAAC region, the density of the crystal structure is reduced to increase VoH; thus, the transistor is likely to be normally on. Hence, the non-CAAC region in the oxide  230   b  is preferably reduced or removed. 
     In contrast, the oxide  230   b  preferably has a layered CAAC structure. In particular, the CAAC structure preferably reaches a lower edge portion of a drain in the oxide  230   b . Here, in the transistor  200 , the conductor  242   a  or the conductor  242   b , and its vicinity function as a drain. In other words, the oxide  230   b  in the vicinity of the lower edge portion of the conductor  242   a  (conductor  242   b ) preferably has a CAAC structure. In this manner, the damaged region of the oxide  230   b  is removed and the CAAC structure is formed also in the edge portion of the drain, which significantly affects the drain withstand voltage, so that variation in the electrical characteristics of the transistor  200  can be further suppressed. In addition, the reliability of the transistor  200  can be improved. 
     In order to remove impurities and the like attached to the surface of the oxide  230   b  in the above etching step, cleaning treatment is performed. Examples of the cleaning method include wet cleaning using a cleaning solution (also can be referred to as wet etching process), plasma treatment using plasma, and cleaning by heat treatment, and any of these cleanings may be performed in combination as appropriate. The cleaning treatment sometimes makes the groove portion deeper. 
     The wet cleaning may be performed using an aqueous solution in which ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like is diluted with carbonated water or pure water; pure water; carbonated water; or the like. Alternatively, ultrasonic cleaning using such an aqueous solution, pure water, or carbonated water may be performed. Alternatively, such cleaning methods may be performed in combination as appropriate. 
     Note that in this specification and the like, in some cases, an aqueous solution in which hydrofluoric acid is diluted with pure water is referred to as diluted hydrofluoric acid, and an aqueous solution in which ammonia water is diluted with pure water is referred to as diluted ammonia water. The concentration, temperature, and the like of the aqueous solution may be adjusted as appropriate in accordance with an impurity to be removed, the structure of a semiconductor device to be cleaned, or the like. The concentration of ammonia in the diluted ammonia water is higher than or equal to 0.01% and lower than or equal to 5%, preferably higher than or equal to 0.1% and lower than or equal to 0.5%. The concentration of hydrogen fluoride in the diluted hydrofluoric acid is higher than or equal to 0.01 ppm and lower than or equal to 100 ppm, preferably higher than or equal to 0.1 ppm and lower than or equal to 10 ppm. 
     A frequency higher than or equal to 200 kHz, preferably higher than or equal to 900 kHz is used for the ultrasonic cleaning. Damage to the oxide  230   b  and the like can be reduced with this frequency. 
     The cleaning treatment may be performed a plurality of times, and the cleaning solution may be changed in every cleaning treatment. For example, the first cleaning treatment may use diluted hydrofluoric acid or diluted ammonia water and the second cleaning treatment may use pure water or carbonated water. 
     As the cleaning treatment in this embodiment, wet cleaning using diluted hydrofluoric acid is performed. The cleaning treatment can remove impurities that are attached onto the surfaces of the oxide  230   a , the oxide  230   b , and the like or diffused into the oxide  230   a , the oxide  230   b , and the like. Furthermore, the crystallinity of the oxide  230   b  can be increased. 
     After the etching or the cleaning treatment, heat treatment may be performed. The heat treatment is performed at higher than or equal to 100° C. and lower than or equal to 450° C., preferably higher than or equal to 350° C. and lower than or equal to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxide  230   a  and the oxide  230   b  to reduce oxygen vacancies. In addition, the crystallinity of the oxide  230   b  can be improved by the heat treatment. The heat treatment may be performed under reduced pressure. Alternatively, heat treatment may be performed in an oxygen atmosphere, and then heat treatment may be successively performed in a nitrogen atmosphere without exposure to the air. 
     Next, an insulating film  252 A is formed (see  FIG.  12 A  to  FIG.  12 D ). The insulating film  252 A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is formed as the insulating film  252 A by an ALD method. Furthermore, the insulating film  252 A needs to be formed on the bottom and side surfaces of the opening formed in the insulator  280  and the like so as to have good coverage. By an ALD method, an atomic layer can be deposited one by one on the bottom and side surfaces of the opening, whereby the insulating film  252 A can be formed in the opening with good coverage. 
     Next, it is preferable to perform microwave treatment in an atmosphere containing oxygen (see  FIGS.  12 A to  12 D ). Here, the microwave treatment refers to, for example, treatment using an apparatus including a power source that generates high-density plasma with the use of a microwave. Note that in this specification and the like, a microwave refers to an electromagnetic wave having a frequency from 300 MHz to 300 GHz, inclusive in some cases. 
     Here, dotted lines in  FIG.  12 B  to  FIG.  12 D  indicate high-frequency oxygen plasma such as microwaves or RF, oxygen radicals, or the like. The microwave treatment is preferably performed with a microwave treatment apparatus including a power source for generating high-density plasma using microwaves, for example. Here, the frequency of the microwave treatment apparatus is set to greater than or equal to 300 MHz and less than or equal to 300 GHz, preferably greater than or equal to 2.4 GHz and less than or equal to 2.5 GHz, for example, 2.45 GHz. The electric power of the power source that applies microwaves of the microwave treatment apparatus is set to higher than or equal to 1000 W and lower than or equal to 10000 W, preferably higher than or equal to 2000 W and lower than or equal to 5000 W. A power source may be provided to the microwave treatment apparatus to apply RF to the substrate side. Oxygen radicals at a high density can be generated with high-density plasma. Furthermore, application of RF to the substrate side allows oxygen ions generated by the high-density plasma to introduce the oxide  230   b  efficiently. 
     The microwave treatment is preferably performed under reduced pressure, and the pressure may be higher than or equal to 10 Pa and lower than or equal to 1000 Pa, preferably higher than or equal to 300 Pa and lower than or equal to 700 Pa. The treatment temperature may be lower than or equal to 750° C., preferably lower than or equal to 500° C., and is approximately 400° C., for example. The oxygen plasma treatment can be followed successively by heat treatment without exposure to air. For example, the temperature may be higher than or equal to 100° C. and lower than or equal to 750° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C. 
     Furthermore, the microwave treatment is performed using an oxygen gas and an argon gas, for example. Here, the oxygen flow rate ratio (O 2 /O 2 +Ar) is higher than 0% and lower than or equal to 100%. The oxygen flow rate ratio (O 2 /O 2 +Ar) is preferably higher than 0% and lower than or equal to 50%. The oxygen flow rate ratio (O 2 /O 2 +Ar) is further preferably higher than or equal to 10% and lower than or equal to 40%. The oxygen flow rate ratio (O 2 /O 2 +Ar) is still further preferably higher than or equal to 10% and lower than or equal to 30%. The carrier concentration in the region  230   bc  can be reduced by thus performing the microwave treatment in an atmosphere containing oxygen. In addition, the carrier concentrations in the region  230   ba  and the region  230   bb  can be prevented from being excessively reduced by preventing an excessive amount of oxygen from being introduced into the chamber in the microwave treatment. 
     As illustrated in  FIG.  12 B  to  FIG.  12 D , the microwave treatment in an oxygen-containing atmosphere can convert an oxygen gas into plasma using a high-frequency wave such as a microwave or RF, and apply the oxygen plasma to a region of the oxide  230   b  which is between the conductor  242   a  and the conductor  242   b . At this time, the region  230   bc  can also be irradiated with the high-frequency wave such as the microwave or RF. In other words, the high-frequency oxygen plasma such as a microwave or RF, or the like can be applied to the region  230   bc  in  FIG.  3 A . The effect of the plasma, the microwave, or the like enables VoH in the region  230   bc  to be cut, and hydrogen H to be removed from the region  230   bc . That is, the reaction “VoH→H+Vo” occurs in the region  230   bc , so that the concentration of VoH in the region  230   bc  can be reduced. As a result, oxygen vacancies and VoH in the region  230   bc  can be reduced to lower the carrier concentration. In addition, oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator  250  can be supplied to oxygen vacancies formed in the region  230   bc , thereby further reducing oxygen vacancies and lowering the carrier concentration in the region  230   bc.    
     By contrast, the conductor  242   a  and the conductor  242   b  are provided over the region  230   ba  and the region  230   bb  illustrated in  FIG.  3 A . The conductor  242  preferably functions as a blocking film preventing the effect caused by the microwave, the high-frequency wave such as RF, the oxygen plasma, or the like in the microwave treatment in an atmosphere containing oxygen. Therefore, the conductor  242  preferably has a function of blocking an electromagnetic wave greater than or equal to 300 MHz and less than or equal to 300 GHz, for example, greater than or equal to 2.4 GHz and less than or equal to 2.5 GHz. 
     As illustrated in  FIG.  12 B  to  FIG.  12 D , the effect of the high-frequency oxygen plasma such as a microwave or RF, or the like is blocked by the conductor  242   a  and the conductor  242   b , and thus does not reach the region  230   ba  and the region  230   bb . Hence, a reduction in VoH and supply of an excess amount of oxygen due to the microwave treatment do not occur in the region  230   ba  and the region  230   bb , preventing a decrease in carrier concentration. 
     In the above manner, oxygen vacancies and VoH can be selectively removed from the region  230   bc  in the oxide semiconductor, whereby the region  230   bc  can be an i-type or substantially i-type region. Furthermore, supply of an excess amount of oxygen to the region  230   ba  and the region  230   bb  functioning as the source region and the drain region can be inhibited and the n-type conductivity can be maintained. As a result, a change in the electrical characteristics of the transistor  200  can be inhibited, and thus a variation in the electrical characteristics of the transistors  200  in the substrate plane can be inhibited. 
     In the microwave treatment, thermal energy is directly transmitted to the oxide  230   b  in some cases owing to an electromagnetic interaction between the microwave and a molecule in the oxide  230   b . The oxide  230   b  might be heated by this thermal energy. Such heat treatment is sometimes referred to as microwave annealing. When microwave treatment is performed in an atmosphere containing oxygen, an effect equivalent to that of oxygen annealing is sometimes obtained. In the case where hydrogen is contained in the oxide  230   b , it is probable that the thermal energy is transmitted to the hydrogen in the oxide  230   b  and the hydrogen activated by the energy is released from the oxide  230   b.    
     Next, an insulating film  250 A is deposited (see  FIG.  13 A  to  FIG.  13 D ). Heat treatment may be performed before the deposition of the insulating film  250 A; the heat treatment may be performed under reduced pressure, and the insulating film  250 A may be successively deposited without exposure to the air. The heat treatment is preferably performed in an oxygen-containing atmosphere. Such treatment can remove moisture and hydrogen adsorbed onto the surface of the oxide  230   b  and the like, and further can reduce the moisture concentration and the hydrogen concentration in the oxide  230   a  and the oxide  230   b . The heat treatment is preferably performed at a temperature higher than or equal to 100° C. and lower than or equal to 400° C. 
     The insulating film  250 A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film  250 A is preferably deposited by a deposition method using a gas in which hydrogen atoms are reduced or removed. This can reduce the hydrogen concentration in the insulating film  250 A. The hydrogen concentration in the insulating film  250 A is preferably reduced because the insulating film  250 A becomes the insulator  250  that is in contact with the oxide  230   b  in a later step. 
     The insulating film  250 A is preferably deposited by a PEALD method using a gas (precursor) containing silicon but not containing hydrocarbon, an oxidizing gas (reactant), and a dilution gas. The thickness of the insulator  250 , which functions as a gate insulating film of the miniaturized transistor  200 , needs to be extremely small (e.g., approximately greater than or equal to 5 nm and less than or equal to 30 nm) and have a small variation. In contrast, a PEALD method is a deposition method in which introduction of a precursor and introduction of a reactant (oxidizer) and a dilution gas are alternately performed, and the film thickness can be adjusted with the number of repetition times of the cycle; thus, accurate control of the film thickness is possible. Thus, the accuracy of the gate insulating film required by the miniaturized transistor  200  can be achieved. When a PEALD method is employed, deposition can be performed at a relatively low substrate temperature. Note that in the PEALD method, the introduction of the precursor and application of high frequency power in the state that the reactant (oxidizing agent) and the dilution gas are introduced are alternately performed in some cases. 
     When a gas (precursor) containing silicon but not containing hydrocarbon, an oxidizing gas (reactant), and a dilution gas are used, entry of hydrogen into the insulating film  250 A and the oxide  230   b  can be inhibited. Furthermore, a precursor containing an impurity such as carbon, e.g., an organic precursor having hydrocarbon, is not used; thus, entry of hydrocarbon, an impurity such as carbon, or the like into the insulating film  250 A can be inhibited. In this manner, a denser film not containing an impurity or the like can be formed, and thus diffusion of In from the oxide  230   b  into the insulating film  250 A through the insulating film  252 A can be prevented. 
     In this embodiment, for the deposition of the insulating film  250 A, according to the process flow in  FIG.  5    and the sequences shown in  FIG.  6 A  and  FIG.  6 B , Step S 01  to Step S 04  are regarded as one cycle and repeated until a desired thickness is obtained. 
     Next, an insulating film  250 B is deposited (see  FIG.  13 A  to  FIG.  13 D ). The insulating film  250 B can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film  250 B is preferably formed using an insulator having a function of inhibiting diffusion of oxygen. With such a structure, oxygen contained in the insulator  250   a  can be inhibited from diffusing into the conductor  260 . That is, a reduction in the amount of oxygen supplied to the oxide  230  can be inhibited. In addition, oxidation of the conductor  260  due to oxygen contained in the insulator  250   a  can be inhibited. For example, the insulating film  250 A can be formed using the above-described material that can be used for the insulator  250 , and the insulating film  250 B can be formed using a material similar to that for the insulator  222 . 
     Specifically, for the insulating film  250 B, a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like, or a metal oxide that can be used for the oxide  230  can be used. In particular, an insulator containing an oxide of one or both of aluminum and hafnium is preferably used. 
     In this embodiment, hafnium oxide is deposited for the insulating film  250 B by a thermal ALD method. 
     After the insulating film  250 B is deposited, microwave treatment may be performed (see  FIG.  13 A  to  FIG.  13 D ). The microwave treatment may be performed under the conditions for the above-described microwave treatment after deposition of the insulating film  250 A. Alternatively, microwave treatment may be performed after the deposition of the insulating film  250 B without the microwave treatment after the deposition of the insulating film  250 A. 
     Heat treatment may be performed while the reduced pressure is maintained after each of microwave treatment after the deposition of the insulating film  252 A and the insulating film  250 A and microwave treatment after the deposition of the insulating film  250 B. Such treatment enables hydrogen in the insulating film  252 A, the insulating film  250 A, the insulating film  250 B, the oxide  230   b , and the oxide  230   a  to be removed efficiently. Part of hydrogen is gettered by the conductor  242  (the conductor  242   a  and the conductor  242   b ) in some cases. Alternatively, while the reduced pressure after the microwave treatment is maintained, heat treatment may be repeated a plurality of times. The repetition of the heat treatment enables hydrogen in the insulating film  250 A, the oxide  230   b , and the oxide  230   a  to be removed more efficiently. Note that the temperature of the heat treatment is preferably higher than or equal to 300° C. and lower than or equal to 500° C. The microwave treatment, i.e., the microwave annealing may also serve as the heat treatment. The heat treatment is not necessarily performed in the case where the oxide  230   b  and the like are adequately heated by the microwave annealing. 
     Furthermore, the microwave treatment improves the film quality of the insulating film  252 A, the insulating film  250 A and the insulating film  250 B, thereby inhibiting diffusion of hydrogen, water, impurities, and the like. Accordingly, hydrogen, water, impurities, and the like can be inhibited from diffusing into the oxide  230   b , the oxide  230   a , and the like through the insulator  250  in a later step such as deposition of a conductive film to be the conductor  260  or later treatment such as heat treatment. 
     Next, a conductive film to be the conductor  260   a  and a conductive film to be the conductor  260   b  are deposited in this order. The conductive film to be the conductor  260   a  and the conductive film to be the conductor  260   b  can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film to be the conductor  260   a  is deposited by an ALD method, and the conductive film to be the conductor  260   b  is deposited by a CVD method. 
     Then, the insulating film  252 A, the insulating film  250 A, the insulating film  250 B, the conductive film to be the conductor  260   a , and the conductive film to be the conductor  260   b  are polished by CMP treatment until the insulator  280  is exposed, whereby the insulator  252 , the insulator  250   a , the insulator  250   b , and the conductor  260  (the conductor  260   a  and the conductor  260   b ) are formed (see  FIG.  14 A  to  FIG.  14 D ). Accordingly, the insulator  252  is placed to cover the opening reaching the oxide  230   b . The conductor  260  is placed to fill the opening with the insulator  252  and the insulator  250  therebetween. 
     Then, heat treatment may be performed under conditions similar to those for the above heat treatment. In this embodiment, treatment is performed at 400° C. in a nitrogen atmosphere for one hour. The heat treatment can reduce the moisture concentration and the hydrogen concentration in the insulator  250  and the insulator  280 . After the heat treatment, the insulator  282  may be deposited successively without exposure to the air. 
     Next, the insulator  282  is formed over the insulator  252 , the insulator  250 , the conductor  260 , and the insulator  280  (see  FIG.  15 A  to  FIG.  15 D ). The insulator  282  can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator  282  is preferably deposited by a sputtering method. Since hydrogen is not needed to be used as a deposition gas in the sputtering method, the hydrogen concentration in the insulator  282  can be reduced. 
     In this embodiment, for the insulator  282 , aluminum oxide is deposited by a pulsed DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas. The use of the pulsed DC sputtering method can achieve more uniform film thickness and improve the sputtering rate and film quality. 
     Next, an etching mask is formed over the insulator  282  by a lithography method and parts of the insulator  282 , the insulator  280 , the insulator  275 , the insulator  222 , and the insulator  216  are processed until the top surface of the insulator  214  is reached (see  FIG.  16 A  to  FIG.  16 D ). Wet etching can be used for the processing; however, dry etching is preferably used for microfabrication. 
     Next, heat treatment may be performed. The heat treatment is performed at higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 400° C. and lower than or equal to 600° C. The heat treatment is preferably performed at a temperature lower than that of the heat treatment performed after the deposition of the oxide film  230 B. Note that the heat treatment is performed in an atmosphere of a nitrogen gas or an inert gas. By the heat treatment, oxygen contained in the insulator  280  and hydrogen bonded to the oxygen can be released to the outside from the side surface of the insulator  280  formed by the processing of the insulator  282 , the insulator  280 , the insulator  275 , the insulator  222 , and the insulator  216 . Moreover, oxygen contained in the insulator  280  and hydrogen bonded to the oxygen can be released to the outside. Note that the hydrogen bonded to oxygen is released as water. Thus, unnecessary oxygen and hydrogen contained in the insulator  280  can be reduced. 
     Next, the insulator  283  is formed over the insulator  282  (see  FIG.  17 A  to  FIG.  17 D ). The insulator  283  can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator  283  is preferably deposited by a sputtering method. By using a sputtering method that does not need to use hydrogen as a deposition gas, the hydrogen concentration in the insulator  283  can be reduced. The insulator  283  may be a multilayer. For example, silicon nitride may be deposited by a sputtering method and silicon nitride may be deposited over the silicon nitride by an ALD method. Surrounding the transistor  200  by the insulator  283  and the insulator  214  that have a high barrier property can prevent entry of moisture and hydrogen from the outside. 
     Next, the insulator  274  is formed over the insulator  283 . The insulator  274  can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, for the insulator  274 , silicon oxide is deposited by a CVD method. 
     Next, the insulator  274  is polished by CMP treatment until the insulator  283  is exposed, whereby a top surface of the insulator  274  is planarized (see  FIG.  17 A  to  FIG.  17 D ). The top surface of the insulator  283  is partly removed by the CMP treatment in some cases. 
     Next, the insulator  285  is formed over the insulator  274  and the insulator  283  (see  FIG.  18 A  to  FIG.  18 D ). The insulator  285  can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator  285  is preferably deposited by a sputtering method. By using a sputtering method that does not need to use hydrogen as a deposition gas, the hydrogen concentration in the insulator  285  can be reduced. 
     In this embodiment, for the insulator  285 , aluminum oxide is deposited by a pulsed DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas. The use of the pulsed DC sputtering method can achieve more uniform film thickness and improve the sputtering rate and film quality. 
     Subsequently, openings reaching the conductor  242  are formed in the insulator  271 , the insulator  275 , the insulator  280 , the insulator  282 , the insulator  283 , and the insulator  285  (see  FIG.  18 A  and  FIG.  18 B ). The openings can be formed by a lithography method. Note that the openings in the top view in  FIG.  18 A  have a circular shape; however, the shapes of the openings are not limited thereto. For example, the openings in the top view may have an almost circular shape such as an elliptical shape, a polygonal shape such as a quadrangular shape, or a polygonal shape such as a quadrangular shape with rounded corners. 
     Subsequently, an insulating film to be the insulator  241  is deposited and the insulating film is subjected to anisotropic etching, so that the insulator  241  is formed (see  FIG.  18 B ). The insulating film to be the insulator  241  can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film to be the insulator  241 , an insulating film having a function of inhibiting passage of oxygen is preferably used. For example, preferably, aluminum oxide is deposited by an ALD method and silicon nitride is deposited there over by a PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen. 
     As an anisotropic etching for the insulating film to be the insulator  241 , a dry etching method may be employed, for example. When the insulator  241  is provided on the sidewall portions of the openings, passage of oxygen from the outside can be inhibited and oxidation of the conductor  240   a  and the conductor  240   b  to be formed next can be prevented. Furthermore, impurities such as water and hydrogen contained in the insulator  280  can be prevented from diffusing into the conductor  240   a  and the conductor  240   b.    
     Next, a conductive film to be the conductor  240   a  and the conductor  240   b  is deposited. The conductive film desirably has a stacked-layer structure which includes a conductor having a function of inhibiting passage of impurities such as water and hydrogen. For example, a stacked layer of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be employed. The conductive film can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. 
     Then, part of the conductive film to be the conductor  240   a  and the conductor  240   b  is removed by CMP treatment to expose the top surface of the insulator  285 . As a result, the conductive film remains only in the openings, so that the conductor  240   a  and the conductor  240   b  having flat top surfaces can be formed (see  FIG.  18 A  to  FIG.  18 D ). Note that part of the top surface of the insulator  285  is sometimes removed by the CMP treatment. 
     Next, a conductive film to be the conductor  246  is deposited. The conductive film can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. 
     Then, the conductive film to be the conductor  246  is processed by a lithography method, thereby forming the conductor  246   a  in contact with the top surface of the conductor  240   a  and the conductor  246   b  in contact with the top surface of the conductor  240   b . At this time, part of the insulator  285  in a region where the insulator  285  does not overlap with the conductor  246   a  or the conductor  246   b  is sometimes removed. 
     Through the above process, the semiconductor device including the transistor  200  illustrated in  FIG.  1 A  to  FIG.  1 D  can be manufactured. As illustrated in  FIG.  7 A  to  FIG.  18 D , the transistor  200  can be manufactured in accordance with the method for manufacturing the semiconductor device described in this embodiment. 
     &lt;Microwave Treatment Apparatus&gt; 
     A microwave treatment apparatus that can be used for the above method for manufacturing the semiconductor device is described below. 
     First, a structure of a manufacturing apparatus that hardly allows entry of impurities in manufacturing a semiconductor device or the like is described with reference to  FIG.  19    to  FIG.  22   . 
       FIG.  19    schematically illustrates a top view of a single wafer multi-chamber manufacturing apparatus  2700 . The manufacturing apparatus  2700  includes an atmosphere-side substrate supply chamber  2701  including a cassette port  2761  for storing a substrate and an alignment port  2762  for performing alignment of a substrate; an atmosphere-side substrate transfer chamber  2702  for transferring a substrate from the atmosphere-side substrate supply chamber  2701 ; a load lock chamber  2703   a  for carrying in a substrate and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure; an unload lock chamber  2703   b  for carrying out a substrate and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure; a transfer chamber  2704  for transferring a substrate in a vacuum; a chamber  2706   a ; a chamber  2706   b ; a chamber  2706   c ; and a chamber  2706   d.    
     Furthermore, the atmosphere-side substrate transfer chamber  2702  is connected to the load lock chamber  2703   a  and the unload lock chamber  2703   b , the load lock chamber  2703   a  and the unload lock chamber  2703   b  are connected to the transfer chamber  2704 , and the transfer chamber  2704  is connected to the chamber  2706   a , the chamber  2706   b , the chamber  2706   c , and the chamber  2706   d.    
     Note that gate valves GV are provided in connecting portions between the chambers so that the chambers other than the atmosphere-side substrate supply chamber  2701  and the atmosphere-side substrate transfer chamber  2702  can be each independently kept in a vacuum state. Furthermore, the atmosphere-side substrate transfer chamber  2702  is provided with a transfer robot  2763   a , and the transfer chamber  2704  is provided with a transfer robot  2763   b . With the transfer robot  2763   a  and the transfer robot  2763   b , a substrate can be transferred inside the manufacturing apparatus  2700 . 
     The back pressure (total pressure) in the transfer chamber  2704  and each of the chambers is, for example, lower than or equal to 1×10 −4  Pa, preferably lower than or equal to 3×10 −5  Pa, further preferably lower than or equal to 1×10 −5  Pa. Furthermore, the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 18 in the transfer chamber  2704  and each of the chambers is, for example, lower than or equal to 3×10 −5  Pa, preferably lower than or equal to 1×10 −5  Pa, further preferably lower than or equal to 3×10 −6  Pa. Furthermore, the partial pressure of a gas molecule (atom) having m/z of 28 in the transfer chamber  2704  and each of the chambers is, for example, lower than or equal to 3×10 −5  Pa, preferably lower than or equal to 1×10 −5  Pa, further preferably lower than or equal to 3×10 −6  Pa. Furthermore, the partial pressure of a gas molecule (atom) having m/z of 44 in the transfer chamber  2704  and each of the chambers is, for example, lower than or equal to 3×10 −5  Pa, preferably lower than or equal to 1×10 −5  Pa, further preferably lower than or equal to 3×10 −6  Pa. 
     Note that the total pressure and the partial pressure in the transfer chamber  2704  and each of the chambers can be measured using a mass analyzer. For example, Qulee CGM-051, a quadrupole mass analyzer (also referred to as Q-mass) produced by ULVAC, Inc. can be used. 
     Furthermore, the transfer chamber  2704  and the chambers each desirably have a structure in which the amount of external leakage or internal leakage is small. For example, the leakage rate in the transfer chamber  2704  and each of the chambers is less than or equal to 3×10 −6  Pa·m 3 /s, preferably less than or equal to 1×10 −6  Pa·m 3 /s. Furthermore, for example, the leakage rate of a gas molecule (atom) having m/z of 18 is less than or equal to 1×10 −7  Pa·m 3 /s, preferably less than or equal to 3×10 −8  Pa·m 3 /s. Furthermore, for example, the leakage rate of a gas molecule (atom) having m/z of 28 is less than or equal to 1×10 −5  Pa·m 3 /s, preferably less than or equal to 1×10 −6  Pa·m 3 /s. Furthermore, for example, the leakage rate of a gas molecule (atom) having m/z of 44 is less than or equal to 3×10 −6  Pa·m 3 /s, preferably less than or equal to 1×10 −6  Pa·m 3 /s. 
     Note that a leakage rate can be derived from the total pressure and partial pressure measured using the above-described mass analyzer. The leakage rate depends on external leakage and internal leakage. The external leakage refers to inflow of gas from the outside of a vacuum system through a minute hole, a sealing defect, or the like. The internal leakage is due to leakage through a partition, such as a valve, in a vacuum system or released gas from an internal member. Measures need to be taken from both aspects of external leakage and internal leakage in order that the leakage rate can be set to less than or equal to the above-described value. 
     For example, open/close portions of the transfer chamber  2704  and each of the chambers are preferably sealed with a metal gasket. For the metal gasket, metal covered with iron fluoride, aluminum oxide, or chromium oxide is preferably used. The metal gasket achieves higher adhesion than an O-ring and can reduce the external leakage. Furthermore, with the use of passive metal covered with iron fluoride, aluminum oxide, chromium oxide, or the like, the release of gas containing impurities released from the metal gasket is inhibited, so that the internal leakage can be reduced. 
     Furthermore, for a member of the manufacturing apparatus  2700 , aluminum, chromium, titanium, zirconium, nickel, or vanadium, which releases a small amount of gas containing impurities, is used. Furthermore, an alloy containing iron, chromium, nickel, and the like covered with the above-described metal, which releases a small amount of gas containing impurities, may be used. The alloy containing iron, chromium, nickel, and the like is rigid, resistant to heat, and suitable for processing. Here, when surface unevenness of the member is reduced by polishing or the like to reduce the surface area, the release of gas can be reduced. 
     Alternatively, the above-described member of the manufacturing apparatus  2700  may be covered with iron fluoride, aluminum oxide, chromium oxide, or the like. 
     The member of the manufacturing apparatus  2700  is preferably formed using only metal when possible, and in the case where a viewing window formed of quartz or the like is provided, for example, the surface is preferably thinly covered with iron fluoride, aluminum oxide, chromium oxide, or the like to inhibit release of gas. 
     An adsorbed substance present in the transfer chamber  2704  and each of the chambers does not affect the pressure in the transfer chamber  2704  and each of the chambers because it is adsorbed onto an inner wall or the like; however, it causes a release of gas when the transfer chamber  2704  and each of the chambers are evacuated. Thus, although there is no correlation between the leakage rate and the exhaust rate, it is important that the adsorbed substance present in the transfer chamber  2704  and each of the chambers be desorbed as much as possible and exhaust be performed in advance with the use of a pump having high exhaust capability. Note that the transfer chamber  2704  and each of the chambers may be subjected to baking to promote desorption of the adsorbed substance. By the baking, the desorption rate of the adsorbed substance can be increased about tenfold. The baking is performed at higher than or equal to 100° C. and lower than or equal to 450° C. At this time, when the adsorbed substance is removed while an inert gas is introduced into the transfer chamber  2704  and each of the chambers, the desorption rate of water or the like, which is difficult to desorb simply by exhaust, can be further increased. Note that when the inert gas to be introduced is heated to substantially the same temperature as the baking temperature, the desorption rate of the adsorbed substance can be further increased. Here, a rare gas is preferably used as the inert gas. 
     Alternatively, treatment for evacuating the transfer chamber  2704  and each of the chambers is preferably performed a certain period of time after a heated inert gas such as a rare gas, heated oxygen, or the like is introduced to increase the pressure in the transfer chamber  2704  and each of the chambers. The introduction of the heated gas can desorb the adsorbed substance in the transfer chamber  2704  and each of the chambers, and impurities present in the transfer chamber  2704  and each of the chambers can be reduced. Note that this treatment is effective when repeated more than or equal to 2 times and less than or equal to 30 times, preferably more than or equal to 5 times and less than or equal to 15 times. Specifically, an inert gas, oxygen, or the like at a temperature higher than or equal to 40° C. and lower than or equal to 400° C., preferably higher than or equal to 50° C. and lower than or equal to 200° C. is introduced, so that the pressure in the transfer chamber  2704  and each of the chambers can be kept to be higher than or equal to 0.1 Pa and lower than or equal to 10 kPa, preferably higher than or equal to 1 Pa and lower than or equal to 1 kPa, further preferably higher than or equal to 5 Pa and lower than or equal to 100 Pa in the time range of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. After that, the transfer chamber  2704  and each of the chambers are evacuated in the time range of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes. 
     Next, the chamber  2706   b  and the chamber  2706   c  are described with reference to a schematic cross-sectional view illustrated in  FIG.  20   . 
     The chamber  2706   b  and the chamber  2706   c  are chambers in which microwave treatment can be performed on an object, for example. Note that the chamber  2706   b  is different from the chamber  2706   c  only in the atmosphere in performing the microwave treatment. The other structures are common and thus collectively described below. 
     The chamber  2706   b  and the chamber  2706   c  each include a slot antenna plate  2808 , a dielectric plate  2809 , a substrate holder  2812 , and an exhaust port  2819 . Furthermore, a gas supply source  2801 , a valve  2802 , a high-frequency generator  2803 , a waveguide  2804 , a mode converter  2805 , a gas pipe  2806 , a waveguide  2807 , a matching box  2815 , a high-frequency power source  2816 , a vacuum pump  2817 , and a valve  2818  are provided outside the chamber  2706   b  and the chamber  2706   c , for example. 
     The high-frequency generator  2803  is connected to the mode converter  2805  through the waveguide  2804 . The mode converter  2805  is connected to the slot antenna plate  2808  through the waveguide  2807 . The slot antenna plate  2808  is placed in contact with the dielectric plate  2809 . Furthermore, the gas supply source  2801  is connected to the mode converter  2805  through the valve  2802 . Then, gas is transferred to the chamber  2706   b  and the chamber  2706   c  through the gas pipe  2806  that runs through the mode converter  2805 , the waveguide  2807 , and the dielectric plate  2809 . Furthermore, the vacuum pump  2817  has a function of exhausting gas or the like from the chamber  2706   b  and the chamber  2706   c  through the valve  2818  and the exhaust port  2819 . Furthermore, the high-frequency power source  2816  is connected to the substrate holder  2812  through the matching box  2815 . 
     The substrate holder  2812  has a function of holding a substrate  2811 . For example, the substrate holder  2812  has a function of an electrostatic chuck or a mechanical chuck for holding the substrate  2811 . Furthermore, the substrate holder  2812  has a function of an electrode to which electric power is supplied from the high-frequency power source  2816 . Furthermore, the substrate holder  2812  includes a heating mechanism  2813  therein and has a function of heating the substrate  2811 . 
     As the vacuum pump  2817 , a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used, for example. Furthermore, in addition to the vacuum pump  2817 , a cryotrap may be used. The use of the cryopump and the cryotrap is particularly preferable because water can be efficiently exhausted. 
     Furthermore, for example, the heating mechanism  2813  may be a heating mechanism that uses a resistance heater or the like for heating. Alternatively, a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas for heating may be used. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. In GRTA, heat treatment is performed using a high-temperature gas. An inert gas is used as the gas. 
     Furthermore, the gas supply source  2801  may be connected to a purifier through a mass flow controller. As the gas, a gas whose dew point is −80° C. or lower, preferably −100° C. or lower is preferably used. For example, an oxygen gas, a nitrogen gas, or a rare gas (an argon gas or the like) is used. 
     As the dielectric plate  2809 , silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria) is used, for example. Furthermore, another protective layer may be further formed on a surface of the dielectric plate  2809 . For the protective layer, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, yttrium oxide, or the like is used. The dielectric plate  2809  is exposed to an especially high density region of high-density plasma  2810  described later; thus, provision of the protective layer can reduce the damage. Consequently, an increase in the number of particles or the like during the treatment can be inhibited. 
     The high-frequency generator  2803  has a function of generating a microwave at, for example, higher than or equal to 0.3 GHz and lower than or equal to 3.0 GHz, higher than or equal to 0.7 GHz and lower than or equal to 1.1 GHz, or higher than or equal to 2.2 GHz and lower than or equal to 2.8 GHz. The microwave generated by the high-frequency generator  2803  is propagated to the mode converter  2805  through the waveguide  2804 . The mode converter  2805  converts the microwave propagated in the TE mode into a microwave in the TEM mode. Then, the microwave is propagated to the slot antenna plate  2808  through the waveguide  2807 . The slot antenna plate  2808  is provided with a plurality of slot holes, and the microwave passes through the slot holes and the dielectric plate  2809 . Then, an electric field is generated below the dielectric plate  2809 , and the high-density plasma  2810  can be generated. In the high-density plasma  2810 , ions and radicals based on the gas species supplied from the gas supply source  2801  are present. For example, oxygen radicals are present. 
     At this time, the quality of a film or the like over the substrate  2811  can be modified by the ions and radicals generated in the high-density plasma  2810 . Note that it is preferable in some cases to apply a bias to the substrate  2811  side using the high-frequency power source  2816 . As the high-frequency power source  2816 , an RF (Radio Frequency) power source with a frequency of 13.56 MHz, 27.12 MHz, or the like may be used, for example. The application of a bias to the substrate side allows ions in the high-density plasma  2810  to efficiently reach a deep portion of an opening portion of the film or the like over the substrate  2811 . 
     For example, in the chamber  2706   b  or the chamber  2706   c , oxygen radical treatment using the high-density plasma  2810  can be performed by introducing oxygen from the gas supply source  2801 . 
     Next, the chamber  2706   a  and the chamber  2706   d  are described with reference to a schematic cross-sectional view illustrated in  FIG.  21   . 
     The chamber  2706   a  and the chamber  2706   d  are chambers in which an object can be irradiated with an electromagnetic wave, for example. Note that the chamber  2706   a  is different from the chamber  2706   d  only in the kind of the electromagnetic wave. The other structures have many common portions and thus are collectively described below. 
     The chamber  2706   a  and the chamber  2706   d  each include one or more lamps  2820 , a substrate holder  2825 , a gas inlet  2823 , and an exhaust port  2830 . Furthermore, a gas supply source  2821 , a valve  2822 , a vacuum pump  2828 , and a valve  2829  are provided outside the chamber  2706   a  and the chamber  2706   d , for example. 
     The gas supply source  2821  is connected to the gas inlet  2823  through the valve  2822 . The vacuum pump  2828  is connected to the exhaust port  2830  through the valve  2829 . The lamp  2820  is provided to face the substrate holder  2825 . The substrate holder  2825  has a function of holding a substrate  2824 . Furthermore, the substrate holder  2825  includes a heating mechanism  2826  therein and has a function of heating the substrate  2824 . 
     As the lamp  2820 , a light source having a function of emitting an electromagnetic wave such as visible light or ultraviolet light may be used, for example. For example, a light source having a function of emitting an electromagnetic wave which has a peak at a wavelength longer than or equal to 10 nm and shorter than or equal to 2500 nm, longer than or equal to 500 nm and shorter than or equal to 2000 nm, or longer than or equal to 40 nm and shorter than or equal to 340 nm can be used. 
     As the lamp  2820 , a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp can used, for example. 
     For example, part or the whole of electromagnetic wave emitted from the lamp  2820  is absorbed by the substrate  2824 , so that the quality of a film or the like over the substrate  2824  can be modified. For example, generation or reduction of defects or removal of impurities can be performed. Note that generation or reduction of defects, removal of impurities, or the like can be efficiently performed while the substrate  2824  is heated. 
     Alternatively, for example, the electromagnetic wave emitted from the lamp  2820  may generate heat in the substrate holder  2825  to heat the substrate  2824 . In this case, the substrate holder  2825  does not need to include the heating mechanism  2826  therein. 
     For the vacuum pump  2828 , refer to the description of the vacuum pump  2817 . Furthermore, for the heating mechanism  2826 , refer to the description of the heating mechanism  2813 . Furthermore, for the gas supply source  2821 , refer to the description of the gas supply source  2801 . 
     A microwave treatment apparatus that can be used in this embodiment is not limited to the above. A microwave treatment apparatus  2900  illustrated in  FIG.  22    can be used. The microwave treatment apparatus  2900  includes a quartz tube  2901 , the exhaust port  2819 , the gas supply source  2801 , the valve  2802 , the high-frequency generator  2803 , the waveguide  2804 , the gas pipe  2806 , the vacuum pump  2817 , and the valve  2818 . Furthermore, the microwave treatment apparatus  2900  includes a substrate holder  2902  that holds a plurality of substrates  2811  ( 2811 _ 1  to  2811 _ n , n is an integer greater than or equal to 2) in the quartz tube  2901 . The microwave treatment apparatus  2900  may further include a heating means  2903  outside the quartz tube  2901 . 
     The substrate placed in the quartz tube  2901  is irradiated with the microwave generated by the high-frequency generator  2803 , through the waveguide  2804 . The vacuum pump  2817  is connected to the exhaust port  2819  through the valve  2818  and can adjust the pressure inside the quartz tube  2901 . The gas supply source  2801  is connected to the gas pipe  2806  through the valve  2802  and can introduce a desired gas into the quartz tube  2901 . The heating means  2903  can heat the substrate  2811  in the quartz tube  2901  to a desired temperature. Alternatively, the heating means  2903  may heat the gas which is supplied from the gas supply source  2801 . With the use of the microwave treatment apparatus  2900 , the substrate  2811  can be subjected to heat treatment and microwave treatment at the same time. Alternatively, the substrate  2811  can be heated and then subjected to microwave treatment. Alternatively, the substrate  2811  can be subjected to microwave treatment and then heat treatment. 
     All of the substrate  2811 _ 1  to the substrate  2811 _ n  may be substrates to be treated where a semiconductor device or a storage device is to be formed, or some of the substrates may be dummy substrates. For example, the substrate  2811 _ 1  and the substrate  2811 _ n  may be dummy substrates and the substrate  2811 _ 2  to the substrate  2811 _ n −1 may be substrates to be treated. 
     Alternatively, the substrate  2811 _ 1 , the substrate  2811 _ 2 , the substrate  2811 _ n −1, and the substrate  2811 _ n  may be dummy substrates and the substrate  2811 _ 3  to the substrate  2811 _ n −2 may be substrates to be treated. A dummy substrate is preferably used, in which case a plurality of substrates to be treated can be uniformly treated at the time of microwave treatment or heat treatment and a variation between the substrates to be treated can be reduced. For example, a dummy substrate is preferably placed over the substrate to be treated which is the closest to the high-frequency generator  2803  and the waveguide  2804 , in which case the substrate to be treated is inhibited from being directly exposed to a microwave. 
     With the use of the above-described manufacturing apparatus, the quality of a film or the like can be modified while the entry of impurities into an object is inhibited. 
     Variation Example 1 of Semiconductor Device 
     Examples of the semiconductor device of one embodiment of the present invention are described below with reference to  FIG.  2 A  to  FIG.  2 D . 
       FIG.  2 A  is a top view of the semiconductor device. Moreover,  FIG.  2 B  is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A 1 -A 2  in  FIG.  2 A . Furthermore,  FIG.  2 C  is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A 3 -A 4  in  FIG.  2 A . Furthermore,  FIG.  2 D  is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A 5 -A 6  in  FIG.  2 A . Note that for clarity of the drawing, some components are omitted in the top view of  FIG.  2 A . 
     Note that in the semiconductor device illustrated in  FIG.  2 A  to  FIG.  2 D , components having the same functions as the components included in the semiconductor device described in &lt;Structure example of semiconductor device&gt; are denoted by the same reference numerals. Note that the materials described in detail in &lt;Structure example of semiconductor device&gt; can also be used as component materials of the semiconductor devices in this section. 
     A semiconductor device illustrated in  FIG.  2 A  to  FIG.  2 D  is a variation example of the semiconductor device illustrated in  FIG.  1 A  to  FIG.  1 D . The semiconductor device illustrated in  FIG.  2 A  to  FIG.  2 D  is different from the semiconductor device illustrated in  FIG.  1 A  to  FIG.  1 D  in that the insulator  283  is in contact with part of a top surface of the insulator  212 . Accordingly, the transistor  200  is placed in a region sealed with the insulator  283  and the insulator  212 . With the above structure, entry of hydrogen contained in a region outside the sealed region into the sealed region can be inhibited. Although  FIG.  2 A  to  FIG.  2 D  illustrate the transistor  200  having a structure in which the insulator  212  and the insulator  283  are each provided to have a single-layer structure, the present invention is not limited thereto. For example, the insulator  212  and the insulator  283  may each be provided to have a stacked-layer structure of two or more layers. 
     Variation Example 2 of Semiconductor Device 
     An example of the semiconductor device that is one embodiment of the present invention will be described below with reference to  FIG.  23   . 
       FIG.  23 A  is a top view of a semiconductor device  500 . In  FIG.  23 A , the x-axis is parallel to the channel length direction of the transistor  200 , and the y-axis is perpendicular to the x-axis.  FIG.  23 B  is a cross-sectional view taken along the dashed-dotted line A 1 -A 2  in  FIG.  23 A , which corresponds to a cross-sectional view in the channel length direction of the transistor  200 .  FIG.  23 C  is a cross-sectional view taken along the dashed-dotted line A 3 -A 4  in  FIG.  23 A , which corresponds to a cross-sectional view of an opening region  400  and its vicinity thereof. Note that for clarity of the drawing, some components are omitted in the top view in  FIG.  23 A . 
     Note that in the semiconductor device illustrated in  FIG.  23 A  to  FIG.  23 C , components having the same functions as the components in the semiconductor device described in &lt;Structure example of semiconductor device&gt; are denoted by the same reference numerals. Note that also in this section, the materials described in detail in &lt;Structure example of semiconductor device&gt; can be used as component materials of the semiconductor device. 
     The semiconductor device  500  illustrated in  FIG.  23 A  to  FIG.  23 C  is a variation example of the semiconductor device illustrated in  FIG.  1 A  to  FIG.  1 D . The semiconductor device  500  illustrated in  FIG.  23 A  to  FIG.  23 C  is different from the semiconductor device in  FIG.  1 A  to  FIG.  1 D  in that the opening region  400  is formed in the insulator  282  and the insulator  280 . Moreover, a sealing portion  265  is formed to surround a plurality of transistors  200 , which is a different point from the semiconductor device illustrated in  FIG.  1 A  to  FIG.  1 D . 
     The semiconductor device  500  includes a plurality of transistors  200  and a plurality of opening regions  400  arranged in a matrix. In addition, a plurality of conductors  260  functioning as gate electrodes of the transistors  200  are provided to extend in the y-axis direction. The opening regions  400  are provided in regions not overlapping with the oxide  230  or the conductor  260 . The sealing portion  265  is formed so as to surround the plurality of transistors  200 , the plurality of conductors  260 , and the plurality of opening regions  400 . Note that the number, the position, and the size of the transistors  200 , the conductors  260 , and the opening regions  400  are not limited to those illustrated in  FIG.  23    and may be set as appropriate in accordance with the design of the semiconductor device  500 . 
     As illustrated in  FIG.  23 B  and  FIG.  23 C , the sealing portion  265  is provided to surround the plurality of transistors  200  and the insulator  216 , the insulator  222 , the insulator  275 , the insulator  280 , and the insulator  282 . In other words, the insulator  283  is provided to cover the insulator  216 , the insulator  222 , the insulator  275 , the insulator  280 , and the insulator  282 . In the sealing portion  265 , the insulator  283  is in contact with a top surface of the insulator  214 . In the sealing portion  265 , an insulator  274  is provided between the insulator  283  and the insulator  285 . The top surface of the insulator  274  is substantially level with the uppermost surface of the insulator  283 . As the insulator  274 , an insulator similar to the insulator  280  can be used. 
     Such a structure enables the plurality of transistors  200  to be surrounded by the insulator  283 , the insulator  214 , and the insulator  212 . One or more of the insulator  283 , the insulator  214 , and the insulator  212  preferably function as a barrier insulating film against hydrogen. Accordingly, entry of hydrogen contained in the region outside the sealing portion  265  into a region in the sealing portion  265  can be inhibited. 
     As illustrated in  FIG.  23 C , the insulator  282  in the opening region  400  has an opening. In the opening region  400 , the insulator  280  may have a groove to overlap with the opening in the insulator  282 . The depth of the groove of the insulator  280  is preferably adjusted so that the top surface of the insulator  275  is exposed at the deepest portion. For example, the depth of the groove may be approximately greater than or equal to ¼ and less than or equal to ½ of the maximum thickness of the insulator  280 . 
     As illustrated in  FIG.  23 C , the insulator  283  inside the opening region  400  is in contact with the side surface of the insulator  282  and the side and top surfaces of the insulator  280 . Part of the insulator  274  is formed in the opening region  400  to fill the depression portion formed in the insulator  283 , in some cases. At this time, the top surface of the insulator  274  formed in the opening region  400  is substantially level with the uppermost surface of the insulator  283 , in some cases. 
     When heat treatment is performed in such a state that the opening region  400  is formed and the insulator  280  is exposed in the opening of the insulator  282 , part of oxygen contained in the insulator  280  can be made to diffuse outwardly from the opening region  400  while oxygen is supplied to the oxide  230 . This enables oxygen to be sufficiently supplied to the region functioning as the channel formation region and its vicinity in the oxide semiconductor layer from the insulator  280  containing oxygen to be released by heating, and also prevents an excess amount of oxygen from being supplied thereto. 
     At this time, hydrogen contained in the insulator  280  can be bonded to oxygen and released to the outside through the opening region  400 . The hydrogen bonded to oxygen is released as water. Thus, the amount of hydrogen contained in the insulator  280  can be reduced, and hydrogen contained in the insulator  280  can be prevented from entering the oxide  230 . 
     In  FIG.  23 A , the shape of the opening region  400  in the top view is substantially rectangular; however, the present invention is not limited to the shape. For example, the shape of the opening region  400  in the top view can be a rectangular shape, an elliptical shape, a circular shape, a rhombus shape, or a shape obtained by combining any of the above shapes. The area and arrangement interval of the opening regions  400  can be set as appropriate in accordance with the design of the semiconductor device including the transistor  200 . For example, in the region where the density of the transistors  200  is low, the area of the opening region  400  may be increased or the arrangement interval of the opening regions  400  may be narrowed. For example, in the region where the density of the transistors  200  is high, the area of the opening region  400  may be decreased, or the arrangement interval of the opening regions  400  may be increased. 
     According to one embodiment of the present invention, a novel transistor can be provided. According to another embodiment of the present invention, a semiconductor device with a high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. According to another embodiment of the present invention, a highly reliable semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. 
     At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with any of those in the other embodiments and the other examples described in this specification. 
     Embodiment 2 
     In this embodiment, one embodiment of a semiconductor device is described with reference to  FIG.  24    to  FIG.  28   . 
     [Storage Device  1 ] 
       FIG.  24    illustrates an example of a semiconductor device (a storage device) of one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, the transistor  200  is provided above a transistor  300 , and a capacitor  100  is provided above the transistor  300  and the transistor  200 . The transistor  200  described in the above embodiment can be used as the transistor  200 . 
     The transistor  200  is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor  200  has a low off-state current, a storage device that uses the transistor  200  can retain stored data for a long time. In other words, such a storage device does not require refresh operation or has extremely low frequency of the refresh operation, which leads to a sufficient reduction in power consumption of the storage device. 
     In the semiconductor device illustrated in  FIG.  24   , a wiring  1001  is electrically connected to a source of the transistor  300 , and a wiring  1002  is electrically connected to a drain of the transistor  300 . In addition, a wiring  1003  is electrically connected to one of the source and the drain of the transistor  200 , a wiring  1004  is electrically connected to the first gate of the transistor  200 , and a wiring  1006  is electrically connected to the second gate of the transistor  200 . A gate of the transistor  300  and the other of the source and the drain of the transistor  200  are electrically connected to one electrode of the capacitor  100 , and a wiring  1005  is electrically connected to the other electrode of the capacitor  100 . 
     The storage device illustrated in  FIG.  24    can form a memory cell array when arranged in a matrix. 
     &lt;Transistor  300 &gt; 
     The transistor  300  is provided on a substrate  311  and includes a conductor  316  functioning as a gate, an insulator  315  functioning as a gate insulator, a semiconductor region  313  formed of part of the substrate  311 , and a low-resistance region  314   a  and a low-resistance region  314   b  functioning as a source region and a drain region. The transistor  300  may be a p-channel transistor or an n-channel transistor. 
     Here, in the transistor  300  illustrated in  FIG.  24   , the semiconductor region  313  (part of the substrate  311 ) where a channel is formed has a protruding shape. In addition, the conductor  316  is provided to cover a side surface and a top surface of the semiconductor region  313  with the insulator  315  therebetween. Note that a material adjusting the work function may be used for the conductor  316 . Such a transistor  300  is also referred to as a FIN-type transistor because it utilizes a protruding portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the protruding portion may be included in contact with an upper portion of the protruding portion. Furthermore, although the case where the protruding portion is formed by processing part of the semiconductor substrate is described here, a semiconductor film having a protruding shape may be formed by processing an SOI substrate. 
     Note that the transistor  300  illustrated in  FIG.  24    is an example and the structure is not limited thereto; an appropriate transistor is used in accordance with a circuit structure or a driving method. 
     &lt;Capacitor  100 &gt; 
     The capacitor  100  is provided above the transistor  200 . The capacitor  100  includes a conductor  110  functioning as a first electrode, a conductor  120  functioning as a second electrode, and an insulator  130  functioning as a dielectric. Here, for the insulator  130 , the insulator that can be used as the insulator  283  described in the above embodiment is preferably used. 
     For example, a conductor  112  and the conductor  110  can be formed at the same time. Note that the conductor  112  has a function of a plug or a wiring that is electrically connected to the capacitor  100 , the transistor  200 , or the transistor  300 . 
     Although the conductor  112  and the conductor  110  having a single-layer structure are illustrated in  FIG.  24   , a stacked-layer structure of two or more layers may be employed without being limited to the single-layer structure. For example, between a conductor having a barrier property and a conductor having high conductivity, a conductor that is highly adhesive to the conductor having a barrier property and the conductor having high conductivity may be formed. 
     The insulator  130  can be provided as stacked layers or a single layer using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride. 
     For example, for the insulator  130 , a stacked-layer structure of a material with high dielectric strength such as silicon oxynitride and a high permittivity (high-k) material is preferably used. In the capacitor  100  having such a structure, a sufficient capacitance can be ensured owing to the high permittivity (high-k) insulator, and the dielectric strength can be increased owing to the insulator with high dielectric strength, so that the electrostatic breakdown of the capacitor  100  can be inhibited. 
     Examples of the high permittivity (high-k) material (a material having a high dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium. 
     Examples of a material with high dielectric strength (a material having a low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin. 
     &lt;Wiring Layer&gt; 
     Wiring layers provided with an interlayer film, a wiring, a plug, and the like may be provided between the components. A plurality of wiring layers can be provided in accordance with design. Here, a plurality of conductors functioning as plugs or wirings are collectively denoted by the same reference numeral in some cases. Furthermore, in this specification and the like, a wiring and a plug electrically connected to the wiring may be a single component. That is, there are cases where part of a conductor functions as a wiring and part of a conductor functions as a plug. 
     For example, an insulator  320 , an insulator  322 , an insulator  324 , and an insulator  326  are sequentially stacked over the transistor  300  as interlayer films. A conductor  328 , a conductor  330 , and the like that are electrically connected to the capacitor  100  or the transistor  200  are embedded in the insulator  320 , the insulator  322 , the insulator  324 , and the insulator  326 . Note that the conductor  328  and the conductor  330  function as a plug or a wiring. 
     The insulators functioning as interlayer films may also function as planarization films that cover uneven shapes therebelow. For example, a top surface of the insulator  322  may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve planarity. 
     A wiring layer may be provided over the insulator  326  and the conductor  330 . For example, in  FIG.  24   , an insulator  350 , an insulator  352 , and an insulator  354  are stacked sequentially. Furthermore, a conductor  356  is formed in the insulator  350 , the insulator  352 , and the insulator  354 . The conductor  356  functions as a plug or a wiring. 
     Similarly, a conductor  218 , a conductor (the conductor  205 ) included in the transistor  200 , and the like are embedded in an insulator  210 , the insulator  212 , the insulator  214 , and the insulator  216 . Note that the conductor  218  has a function of a plug or a wiring that is electrically connected to the capacitor  100  or the transistor  300 . In addition, an insulator  150  is provided over the conductor  120  and the insulator  130 . 
     Here, like the insulator  241  described in the above embodiment, an insulator  217  is provided in contact with a side surface of the conductor  218  functioning as a plug. The insulator  217  is provided in contact with an inner wall of an opening formed in the insulator  210 , the insulator  212 , the insulator  214 , and the insulator  216 . That is, the insulator  217  is provided between the conductor  218  and each of the insulator  210 , the insulator  212 , the insulator  214 , and the insulator  216 . Note that the conductor  205  and the conductor  218  can be formed in parallel; thus, the insulator  217  is sometimes formed in contact with the side surface of the conductor  205 . 
     As the insulator  217 , an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used, for example. Since the insulator  217  is provided in contact with the insulator  210 , the insulator  212 , the insulator  214 , and the insulator  222 , entry of impurities such as water and hydrogen into the oxide  230  through the conductor  218  from the insulator  210 , the insulator  216 , or the like can be inhibited. In particular, silicon nitride is suitable because of its high blocking property against hydrogen. Moreover, oxygen contained in the insulator  210  or the insulator  216  can be prevented from being absorbed by the conductor  218 . 
     The insulator  217  can be formed in a manner similar to that of the insulator  241 . For example, silicon nitride can be deposited by a PEALD method and an opening reaching the conductor  356  can be formed by anisotropic etching. 
     Examples of an insulator that can be used as an interlayer film include an insulating oxide, an insulating nitride, an insulating oxynitride, an insulating nitride oxide, an insulating metal oxide, an insulating metal oxynitride, and an insulating metal nitride oxide. 
     For example, when a material having a low dielectric constant is used for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Thus, a material is preferably selected depending on the function of an insulator. 
     For example, as the insulator  150 , the insulator  210 , the insulator  352 , the insulator  354 , and the like, an insulator having a low dielectric constant is preferably included. For example, the insulator preferably includes silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, a resin, or the like. Alternatively, the insulator preferably has a stacked-layer structure of a resin and silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide. When silicon oxide or silicon oxynitride, which is thermally stable, is combined with a resin, the stacked-layer structure can have thermal stability and a low dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon and aramid), polyimide, polycarbonate, and acrylic. 
     When a transistor using an oxide semiconductor is surrounded by an insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, the electrical characteristics of the transistor can be stable. Thus, the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen can be used for the insulator  214 , the insulator  212 , the insulator  350 , and the like. 
     As the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, a single layer or stacked layers of an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used. 
     Specifically, as the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; silicon nitride oxide; silicon nitride; or the like can be used. 
     As the conductor that can be used for a wiring or a plug, a material containing one or more kinds of metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. Alternatively, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used. 
     For example, for the conductor  328 , the conductor  330 , the conductor  356 , the conductor  218 , the conductor  112 , and the like, a single layer or stacked layers of conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material that is formed using the above materials can be used. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is preferable to use tungsten. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance. 
     &lt;Wiring or Plug in Layer Provided with Oxide Semiconductor&gt; 
     In the case where an oxide semiconductor is used in the transistor  200 , an insulator including an excess-oxygen region is provided in the vicinity of the oxide semiconductor in some cases. In that case, an insulator having a barrier property is preferably provided between the insulator including the excess-oxygen region and a conductor provided in the insulator including the excess-oxygen region. 
     For example, in  FIG.  24   , the insulator  241  is preferably provided between the conductor  240  and the insulator  224  and the insulator  280  each including excess oxygen. Since the insulator  241  is provided in contact with the insulator  222 , the insulator  282 , and the insulator  283 , the insulator  224  and the transistor  200  can be sealed with the insulators having a barrier property. 
     That is, the insulator  241  can inhibit excess oxygen contained in the insulator  280  from being absorbed by the conductor  240 . In addition, providing the insulator  241  can inhibit diffusion of hydrogen, which is an impurity, into the transistor  200  through the conductor  240 . 
     The insulator  241  is preferably formed using an insulating material having a function of inhibiting diffusion of oxygen and impurities such as water and hydrogen. For example, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like is preferably used. In particular, silicon nitride is preferable because of its high blocking property against hydrogen. Other than that, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can be used, for example. 
     As described in the above embodiment, the transistor  200  may be sealed with the insulator  212 , the insulator  214 , the insulator  282 , and the insulator  283 . Such a structure can inhibit entry of hydrogen contained in the insulator  274 , the insulator  150 , or the like into the insulator  280  or the like. 
     Here, the conductor  240  penetrates the insulator  283  and the insulator  282 , and the conductor  218  penetrates the insulator  214  and the insulator  212 ; however, as described above, the insulator  241  is provided in contact with the conductor  240 , and the insulator  217  is provided in contact with the conductor  218 . This can reduce the amount of hydrogen entering the inside of the insulator  212 , the insulator  214 , the insulator  282 , and the insulator  283  through the conductor  240  and the conductor  218 . In this manner, the transistor  200  is sealed with the insulator  212 , the insulator  214 , the insulator  282 , the insulator  283 , the insulator  241 , and the insulator  217 , so that impurities such as hydrogen contained in the insulator  274  or the like can be inhibited from entering from the outside. 
     &lt;Dicing Line&gt; 
     A dicing line (sometimes referred to as a scribe line, a dividing line, or a cutting line) which is provided when a large-sized substrate is divided into semiconductor elements so that a plurality of semiconductor devices are each taken as a chip is described below. Examples of a dividing method include the case where a groove (a dicing line) for dividing the semiconductor elements is formed on the substrate, and then the substrate is cut along the dicing line to divide (split) it into a plurality of semiconductor devices. 
     Here, for example, as illustrated in  FIG.  24   , a region in which the insulator  283  and the insulator  214  are in contact with each other is preferably designed to overlap the dicing line. That is, an opening is provided in the insulator  282 , the insulator  280 , the insulator  275 , the insulator  224 , the insulator  222 , and the insulator  216  in the vicinity of a region to be the dicing line that is provided on an outer edge of the memory cell including the plurality of transistors  200 . 
     That is, in the opening provided in the insulator  282 , the insulator  280 , the insulator  275 , the insulator  222 , and the insulator  216 , the insulator  214  is in contact with the insulator  283 . 
     For example, an opening may be provided in the insulator  282 , the insulator  280 , the insulator  275 , the insulator  222 , the insulator  216 , and the insulator  214 . With such a structure, in the opening provided in the insulator  282 , the insulator  280 , the insulator  275 , the insulator  222 , the insulator  216 , and the insulator  214 , the insulator  212  is in contact with the insulator  283 . Here, the insulator  212  and the insulator  283  may be formed using the same material and the same method. When the insulator  212  and the insulator  283  are formed using the same material and the same method, the adhesion therebetween can be increased. For example, silicon nitride is preferably used. 
     With the structure, the transistors  200  can be surrounded by the insulator  212 , the insulator  214 , the insulator  282 , and the insulator  283 . Since at least one of the insulator  212 , the insulator  214 , the insulator  282 , and the insulator  283  has a function of inhibiting diffusion of oxygen, hydrogen, and water, even when the substrate is divided into circuit regions each of which is provided with the semiconductor elements described in this embodiment to be processed into a plurality of chips, entry and diffusion of impurities such as hydrogen and water from the direction of the side surface of the divided substrate into the transistor  200  can be prevented. 
     With the structure, excess oxygen in the insulator  280  and the insulator  224  can be prevented from diffusing to the outside. Accordingly, excess oxygen in the insulator  280  and the insulator  224  is efficiently supplied to the oxide where the channel is formed in the transistor  200 . The oxygen can reduce oxygen vacancies in the oxide where the channel is formed in the transistor  200 . Thus, the oxide where the channel is formed in the transistor  200  can be an oxide semiconductor with a low density of defect states and stable characteristics. That is, the transistor  200  can have a small variation in the electrical characteristics and higher reliability. 
     Note that although the capacitor  100  of the storage device illustrated in  FIG.  24    has a planar shape, the storage device described in this embodiment is not limited thereto. For example, the capacitor  100  may have a cylindrical shape as illustrated in  FIG.  25   . Note that the structure below and including the insulator  150  of a storage device illustrated in  FIG.  25    is similar to that of the semiconductor device illustrated in  FIG.  24   . 
     The capacitor  100  illustrated in  FIG.  25    includes the insulator  150  over the insulator  130 , an insulator  142  over the insulator  150 , a conductor  115  placed in an opening formed in the insulator  150  and the insulator  142 , an insulator  145  over the conductor  115  and the insulator  142 , a conductor  125  over the insulator  145 , and an insulator  152  over the conductor  125  and the insulator  145 . Here, at least parts of the conductor  115 , the insulator  145 , and the conductor  125  are placed in the opening formed in the insulator  150  and the insulator  142 . 
     The conductor  115  functions as a lower electrode of the capacitor  100 , the conductor  125  functions as an upper electrode of the capacitor  100 , and the insulator  145  functions as a dielectric of the capacitor  100 . The capacitor  100  has a structure in which the upper electrode and the lower electrode face each other with the dielectric sandwiched therebetween on a side surface as well as a bottom surface of the opening in the insulator  150  and the insulator  142 ; thus, the capacitance per unit area can be increased. Thus, the deeper the opening is, the larger the capacitance of the capacitor  100  can be. Increasing the capacitance per unit area of the capacitor  100  in this manner can promote miniaturization or higher integration of the semiconductor device. 
     An insulator that can be used as the insulator  280  can be used as the insulator  152 . The insulator  142  preferably functions as an etching stopper at the time of forming the opening in the insulator  150  and is formed using an insulator that can be used as the insulator  214 . 
     The shape of the opening formed in the insulator  150  and the insulator  142  when seen from above may be a quadrangular shape, a polygonal shape other than a quadrangular shape, a polygonal shape with rounded corners, or a circular shape including an elliptical shape. Here, the area where the opening and the transistor  200  overlap each other is preferably large in the top view. Such a structure can reduce the area occupied by the semiconductor device including the capacitor  100  and the transistor  200 . 
     The conductor  115  is placed in contact with the opening formed in the insulator  142  and the insulator  150 . A top surface of the conductor  115  is preferably substantially level with a top surface of the insulator  142 . Furthermore, a bottom surface of the conductor  115  is in contact with the conductor  110  through an opening in the insulator  130 . The conductor  115  is preferably deposited by an ALD method, a CVD method, or the like; for example, a conductor that can be used for the conductor  205  is used. 
     The insulator  145  is placed to cover the conductor  115  and the insulator  142 . The insulator  145  is preferably deposited by an ALD method or a CVD method, for example. The insulator  145  can be provided to have stacked layers or a single layer using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride. As the insulator  145 , an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used, for example. 
     For the insulator  145 , a material with high dielectric strength, such as silicon oxynitride, or a high permittivity (high-k) material is preferably used. Alternatively, a stacked-layer structure of a material with high dielectric strength and a high permittivity (high-k) material may be used. 
     Examples of the high permittivity (high-k) material (a material having a high dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium. The use of such a high-k material can ensure sufficient capacitance of the capacitor  100  even when the insulator  145  has a large thickness. When the insulator  145  has a large thickness, generation of a leakage current between the conductor  115  and the conductor  125  can be inhibited. 
     Examples of the material with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin. For example, it is possible to use an insulating film in which silicon nitride (SiNx) deposited by a PEALD method, silicon oxide (SiO x ) deposited by a PEALD method, and silicon nitride (SiNx) deposited by a PEALD method are stacked in this order. Alternatively, an insulating film in which zirconium oxide, silicon oxide deposited by an ALD method, and zirconium oxide are stacked in this order can be used. The use of such an insulator with high dielectric strength can increase the dielectric strength and inhibit electrostatic breakdown of the capacitor  100 . 
     The conductor  125  is placed to fill the opening formed in the insulator  142  and the insulator  150 . The conductor  125  is electrically connected to the wiring  1005  through a conductor  140  and a conductor  153 . The conductor  125  is preferably deposited by an ALD method, a CVD method, or the like and may be formed using a conductor that can be used as the conductor  205 , for example. 
     The conductor  153  is provided over an insulator  154  and is covered with an insulator  156 . The conductor  153  can be formed using a conductor that can be used as the conductor  112 , and the insulator  156  can be formed using an insulator that can be used as the insulator  152 . Here, the conductor  153  is in contact with a top surface of the conductor  140  and functions as a terminal of the capacitor  100 , the transistor  200 , or the transistor  300 . 
     [Storage Device  2 ] 
       FIG.  26    illustrates an example of a semiconductor device (a storage device) of one embodiment of the present invention. 
     &lt;Structure Example of Memory Device&gt; 
       FIG.  26    is a cross-sectional view of a semiconductor device including a memory device  290 . The memory device  290  illustrated in  FIG.  26    includes a capacitor device  292  besides the transistor  200  illustrated in  FIG.  1 A  to  FIG.  1 D .  FIG.  26    corresponds to a cross-sectional view of the transistor  200  in the channel length direction. 
     The capacitor device  292  includes the conductor  242   b ; the insulator  271   b  provided over the conductor  242   b ; the insulator  275  provided in contact with a top surface of the insulator  271   b , a side surface of the insulator  271   b , and a side surface of the conductor  242   b ; and a conductor  294  over the insulator  275 . In other words, the capacitor device  292  forms a MIM (Metal-Insulator-Metal) capacitor. Note that one of a pair of electrodes included in the capacitor device  292 , i.e., the conductor  242   b , can also serve as the source electrode of the transistor. The dielectric layer included in the capacitor device  292  can also serve as a protective layer provided in the transistor, i.e., the insulator  271  and the insulator  275 . Thus, the manufacturing process of the capacitor device  292  can also serve as part of the manufacturing process of the transistor, improving the productivity of the semiconductor device. Furthermore, one of a pair of electrodes included in the capacitor device  292 , that is, the conductor  242   b , also serves as the source electrode of the transistor; therefore, the area in which the transistor and the capacitor device are placed can be reduced. 
     Note that the conductor  294  can be formed using, for example, a material that can be used for the conductor  242 . 
     &lt;Variation Example of Memory Device&gt; 
     Examples of a semiconductor device of one embodiment of the present invention including the transistor  200  and the capacitor device  292 , which are different from the example described above in &lt;Structure example of memory device&gt;, are described below with reference to  FIG.  27 A ,  FIG.  27 B , and  FIG.  28   . Note that in the semiconductor devices illustrated in  FIG.  27 A ,  FIG.  27 B , and  FIG.  28   , structures having the same function as those included in the semiconductor devices described in the above embodiment and &lt;Structure example of memory device&gt; (see  FIG.  26   ) are denoted by the same reference numerals. Note that the materials described in detail in the above embodiment and &lt;Structure example of memory device&gt; can be used as component materials of the transistor  200  and the capacitor device  292  in this section. The memory devices in  FIG.  27 A ,  FIG.  27 B ,  FIG.  28   , and the like are, but not limited to, the memory device illustrated in  FIG.  26   . 
     Variation Example 1 of Memory Device 
     An example of a semiconductor device  600  of one embodiment of the present invention including a transistor  200   a , a transistor  200   b , a capacitor device  292   a , and a capacitor device  292   b  is described below with reference to  FIG.  27 A . 
       FIG.  27 A  is a cross-sectional view of the semiconductor device  600  including the transistor  200   a , the transistor  200   b , the capacitor device  292   a , and the capacitor device  292   b  in the channel length direction. Here, the capacitor device  292   a  includes the conductor  242   a ; the insulator  271   a  over the conductor  242   a ; the insulator  275  in contact with a top surface of the insulator  271   a , a side surface of the insulator  271   a , and a side surface of the conductor  242   a ; and a conductor  294   a  over the insulator  275 . The capacitor device  292   b  includes the conductor  242   b ; the insulator  271   b  over the conductor  242   b ; the insulator  275  in contact with the top surface of the insulator  271   b , the side surface of the insulator  271   b , and the side surface of the conductor  242   b ; and a conductor  294   b  over the insulator  275 . 
     The semiconductor device  600  has a line-symmetric structure with respect to dashed-dotted line A 3 -A 4  as illustrated in  FIG.  27 A . A conductor  242   c  serves as both one of a source electrode and a drain electrode of the transistor  200   a  and one of a source electrode and a drain electrode of the transistor  200   b . An insulator  271   c  is provided over the conductor  242   c . In addition, the conductor  240  functioning as a plug also connects the conductor  246  functioning as a wiring to the transistor  200   a  and the transistor  200   b . With the above connection structure between the two transistors, the two capacitor devices, the wiring, and the plug, a semiconductor device that can be miniaturized or highly integrated can be provided. 
     The structure examples of the semiconductor device illustrated in  FIG.  27 A  can be referred to for the structures and the effects of the transistor  200   a , the transistor  200   b , the capacitor device  292   a , and the capacitor device  292   b.    
     Variation Example 2 of Memory Device 
     In the above description, the transistor  200   a , the transistor  200   b , the capacitor device  292   a , and the capacitor device  292   b  are given as examples of components of the semiconductor device; however, the semiconductor device described in this embodiment is not limited thereto. For example, as illustrated in  FIG.  27 B , a structure may be employed in which the semiconductor device  600  and a semiconductor device having a structure similar to that of the semiconductor device  600  are connected through a capacitor portion. In this specification, the semiconductor device including the transistor  200   a , the transistor  200   b , the capacitor device  292   a , and the capacitor device  292   b  is referred to as a cell. For the structures of the transistor  200   a , the transistor  200   b , the capacitor device  292   a , and the capacitor device  292   b , the above description of the transistor  200   a , the transistor  200   b , the capacitor device  292   a , and the capacitor device  292   b  can be referred to. 
       FIG.  27 B  is a cross-sectional view in which the semiconductor device  600  including the transistor  200   a , the transistor  200   b , the capacitor device  292   a , and the capacitor device  292   b , and a cell having a structure similar to that of the semiconductor device  600  are connected through a capacitor portion. 
     As illustrated in  FIG.  27 B , the conductor  294   b  functioning as one electrode of the capacitor device  292   b  included in the semiconductor device  600  also serves as one electrode of a capacitor device included in a semiconductor device  601  having a structure similar to that of the semiconductor device  600 . Although not illustrated, the conductor  294   a  functioning as one electrode of the capacitor device  292   a  included in the semiconductor device  600  also serves as one electrode of a capacitor device included in a semiconductor device on the left side of the semiconductor device  600 , that is, a semiconductor device adjacent to the semiconductor device  600  in the A 1  direction in  FIG.  27 B . The cell on the right side of the semiconductor device  601 , that is, the cell in the A 2  direction in  FIG.  27 B , has a similar structure. That is, a cell array (also referred to as a memory device layer) can be formed. With such a structure of the cell array, space between adjacent cells can be reduced; thus, the projected area of the cell array can be reduced and high integration can be achieved. When the cells illustrated in  FIG.  27 B  are arranged in a matrix, a matrix-shape cell array can be formed. 
     When the transistor  200   a , the transistor  200   b , the capacitor device  292   a , and the capacitor device  292   b  are formed to have the structures described in this embodiment as described above, the area of the cell can be reduced and the semiconductor device including a cell array can be miniaturized or highly integrated. 
     Furthermore, the cell array may have a stacked-layer structure instead of a single-layer structure.  FIG.  28    illustrates a cross-sectional view of n layers of cell arrays  610  that are stacked. When a plurality of cell arrays (a cell array  610 _ 1  to a cell array  610 _ n ) are stacked as illustrated in  FIG.  28   , cells can be integrally placed without increasing the area occupied by the cell arrays. In other words, a 3D cell array can be formed. 
     At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with any of those in the other embodiments and the other examples described in this specification. 
     Embodiment 3 
     In this embodiment, a storage device including a transistor in which an oxide is used as a semiconductor (hereinafter, sometimes referred to as an OS transistor) and a capacitor (hereinafter, sometimes referred to as an OS memory device) of one embodiment of the present invention is described with reference to  FIG.  29 A ,  FIG.  29 B , and  FIG.  30 A  to  FIG.  30 H . The OS memory device is a storage device that includes at least a capacitor and an OS transistor that controls the charging and discharging of the capacitor. Since the OS transistor has an extremely low off-state current, the OS memory device has excellent retention characteristics and thus can function as a nonvolatile memory. 
     &lt;Structure Example of Storage Device&gt; 
       FIG.  29 A  illustrates a structure example of the OS memory device. A storage device  1400  includes a peripheral circuit  1411  and a memory cell array  1470 . The peripheral circuit  1411  includes a row circuit  1420 , a column circuit  1430 , an output circuit  1440 , and a control logic circuit  1460 . 
     The column circuit  1430  includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging wirings. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the wirings are connected to the memory cell included in the memory cell array  1470 , and are described later in detail. The amplified data signal is output as a data signal RDATA to the outside of the storage device  1400  through the output circuit  1440 . The row circuit  1420  includes, for example, a row decoder and a word line driver circuit, and can select a row to be accessed. 
     As power supply voltages from the outside, a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit  1411 , and a high power supply voltage (VIL) for the memory cell array  1470  are supplied to the storage device  1400 . Control signals (CE, WE, and RE), an address signal ADDR, and a data signal WDATA are also input to the storage device  1400  from the outside. The address signal ADDR is input to the row decoder and the column decoder, and the data signal WDATA is input to the write circuit. 
     The control logic circuit  1460  processes the control signals (CE, WE, and RE) input from the outside, and generates control signals for the row decoder and the column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. Signals processed by the control logic circuit  1460  are not limited thereto, and other control signals are input as necessary. 
     The memory cell array  1470  includes a plurality of memory cells MC arranged in a matrix and a plurality of wirings. Note that the number of wirings that connect the memory cell array  1470  to the row circuit  1420  depends on the structure of the memory cell MC, the number of memory cells MC in a column, and the like. The number of wirings that connect the memory cell array  1470  to the column circuit  1430  depends on the structure of the memory cell MC, the number of memory cells MC in a row, and the like. 
     Note that  FIG.  29 A  illustrates an example in which the peripheral circuit  1411  and the memory cell array  1470  are formed on the same plane; however, this embodiment is not limited to the example. For example, as illustrated in  FIG.  29 B , the memory cell array  1470  may be provided to overlap part of the peripheral circuit  1411 . For example, the sense amplifier may be provided below the memory cell array  1470  so that they overlap with each other. 
       FIG.  30 A  to  FIG.  30 H  illustrate structure examples of a memory cell that can be used as the memory cell MC. 
     [DOSRAM] 
       FIG.  30 A  to  FIG.  30 C  illustrate circuit structure examples of a memory cell of a DRAM. In this specification and the like, a DRAM using a memory cell including one OS transistor and one capacitor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) in some cases. A memory cell  1471  illustrated in  FIG.  30 A  includes a transistor M 1  and a capacitor CA. Note that the transistor M 1  includes a gate (sometimes referred to as a top gate) and a back gate. 
     A first terminal of the transistor M 1  is connected to a first terminal of the capacitor CA. A second terminal of the transistor M 1  is connected to a wiring BIL. The gate of the transistor M 1  is connected to a wiring WOL. The back gate of the transistor M 1  is connected to a wiring BGL. A second terminal of the capacitor CA is connected to a wiring LL. 
     The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring LL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. In the time of data writing and data reading, the wiring LL may be at a ground potential or a low-level potential. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M 1 . When a given potential is applied to the wiring BGL, the threshold voltage of the transistor M 1  can be increased or decreased. 
     Here, a memory cell  1471  illustrated in  FIG.  30 A  corresponds to the storage device illustrated in  FIG.  26   . That is, the transistor M 1  and the capacitor CA correspond to the transistor  200  and the capacitor device  292 , respectively. 
     The circuit structure of the memory cell MC is not limited to that of the memory cell  1471 , and the circuit structure can be changed. For example, as in a memory cell  1472  illustrated in  FIG.  30 B , the back gate of the transistor M 1  may be connected not to the wiring BGL but to the wiring WOL in the memory cell MC. Alternatively, for example, the transistor M 1  may be a single-gate transistor, that is, a transistor without a back gate in the memory cell MC as in a memory cell  1473  illustrated in  FIG.  30 C . 
     In the case where the semiconductor device described in any of the above embodiments is used in the memory cell  1471  and the like, the transistor  200  can be used as the transistor M 1 , and the capacitor  100  can be used as the capacitor CA. When an OS transistor is used as the transistor M 1 , the leakage current of the transistor M 1  can be extremely low. That is, with the use of the transistor M 1 , written data can be retained for a long time, and thus the frequency of the refresh operation for the memory cell can be decreased. Alternatively, refresh operation for the memory cell can be unnecessary. In addition, since the transistor M 1  has an extremely low leakage current, multi-level data or analog data can be retained in the memory cell  1471 , the memory cell  1472 , and the memory cell  1473 . 
     In the DOSRAM, when the sense amplifier is provided below the memory cell array  1470  so that they overlap with each other as described above, the bit line can be shortened. This reduces bit line capacitance, which can reduce the storage capacitance of the memory cell. 
     [NOSRAM] 
       FIG.  30 D  to  FIG.  30 G  each illustrate a circuit structure example of a gain-cell memory cell including two transistors and one capacitor. A memory cell  1474  illustrated in  FIG.  30 D  includes a transistor M 2 , a transistor M 3 , and a capacitor CB. Note that the transistor M 2  includes a top gate (simply referred to as a gate in some cases) and a back gate. In this specification and the like, a storage device including a gain-cell memory cell using an OS transistor as the transistor M 2  is referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM) in some cases. 
     A first terminal of the transistor M 2  is connected to a first terminal of the capacitor CB. A second terminal of the transistor M 2  is connected to a wiring WBL. The gate of the transistor M 2  is connected to the wiring WOL. The back gate of the transistor M 2  is connected to the wiring BGL. A second terminal of the capacitor CB is connected to the wiring CAL. A first terminal of the transistor M 3  is connected to a wiring RBL. A second terminal of the transistor M 3  is connected to a wiring SL. A gate of the transistor M 3  is connected to the first terminal of the capacitor CB. 
     The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. In the time of data writing and data reading, a high-level potential is preferably applied to the wiring CAL. In the time of data retaining, a low-level potential is preferably applied to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M 2 . The threshold voltage of the transistor M 2  can be increased or decreased by applying a given potential to the wiring BGL. 
     Here, the memory cell  1474  illustrated in  FIG.  30 D  corresponds to the storage device illustrated in  FIG.  24    and  FIG.  25   . That is, the transistor M 2 , the capacitor CB, the transistor M 3 , the wiring WBL, the wiring WOL, the wiring BGL, the wiring CAL, the wiring RBL, and the wiring SL correspond to the transistor  200 , the capacitor  100 , the transistor  300 , the wiring  1003 , the wiring  1004 , the wiring  1006 , the wiring  1005 , the wiring  1002 , and the wiring  1001 , respectively. 
     The circuit structure of the memory cell MC is not limited to that of the memory cell  1474 , and the circuit structure can be changed as appropriate. For example, as in a memory cell  1475  illustrated in  FIG.  30 E , the back gate of the transistor M 2  may be connected not to the wiring BGL but to the wiring WOL in the memory cell MC. Alternatively, for example, the transistor M 2  may be a single-gate transistor, that is, a transistor without a back gate in the memory cell MC as in a memory cell  1476  illustrated in  FIG.  30 F . For example, the memory cell MC may have a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL as in a memory cell  1477  illustrated in  FIG.  30 G . 
     In the case where the semiconductor device described in any of the above embodiments is used in the memory cell  1474  and the like, the transistor  200  can be used as the transistor M 2 , the transistor  300  can be used as the transistor M 3 , and the capacitor  100  can be used as the capacitor CB. When an OS transistor is used as the transistor M 2 , the leakage current of the transistor M 2  can be extremely low. Consequently, with the use of the transistor M 2 , written data can be retained for a long time, and thus the frequency of the refresh operation for the memory cell can be decreased. Alternatively, refresh operation for the memory cell can be unnecessary. In addition, since the transistor M 2  has an extremely low leakage current, multi-level data or analog data can be retained in the memory cell  1474 . The same applies to the memory cell  1475  to the memory cell  1477 . 
     Note that the transistor M 3  may be a transistor containing silicon in a channel formation region (hereinafter, sometimes referred to as a Si transistor). The Si transistor may be either an n-channel transistor or a p-channel transistor. A Si transistor has higher field-effect mobility than an OS transistor in some cases. Therefore, a Si transistor may be used as the transistor M 3  functioning as a reading transistor. Furthermore, the transistor M 2  can be stacked over the transistor M 3  when a Si transistor is used as the transistor M 3 , in which case the area occupied by the memory cell can be reduced, leading to high integration of the storage device. 
     Alternatively, the transistor M 3  may be an OS transistor. When an OS transistor is used as each of the transistor M 2  and the transistor M 3 , the circuit of the memory cell array  1470  can be formed using only n-channel transistors. 
       FIG.  30 H  illustrates an example of a gain-cell memory cell including three transistors and one capacitor. A memory cell  1478  illustrated in  FIG.  30 H  includes a transistor M 4  to a transistor M 6  and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell  1478  is electrically connected to the wiring BIL, a wiring RWL, a wiring WWL, the wiring BGL, and a wiring GNDL. The wiring GNDL is a wiring for supplying a low-level potential. Note that the memory cell  1478  may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL. 
     The transistor M 4  is an OS transistor with a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M 4  may be electrically connected to each other. Alternatively, the transistor M 4  does not necessarily include the back gate. 
     Note that each of the transistor M 5  and the transistor M 6  may be an n-channel Si transistor or a p-channel Si transistor. Alternatively, the transistor M 4  to the transistor M 6  may be OS transistors. In that case, the circuit of the memory cell array  1470  can be formed using only n-channel transistors. 
     In the case where the semiconductor device described in any of the above embodiments is used in the memory cell  1478 , the transistor  200  can be used as the transistor M 4 , the transistors  300  can be used as the transistor M 5  and the transistor M 6 , and the capacitor  100  can be used as the capacitor CC. When an OS transistor is used as the transistor M 4 , the leakage current of the transistor M 4  can be extremely low. 
     Note that the structures of the peripheral circuit  1411 , the memory cell array  1470 , and the like described in this embodiment are not limited to the above. The arrangement and functions of these circuits and the wirings, circuit components, and the like connected to the circuits can be changed, removed, or added as needed. 
     The storage device of one embodiment of the present invention operates fast and can retain data for a long time. 
     The structure, method, and the like described in this embodiment can be used in an appropriate combination with any of other structures, methods, and the like described in this embodiment or the other embodiments. 
     Embodiment 4 
     In this embodiment, an example of a chip  1200  on which the semiconductor device of the present invention is mounted is described with reference to  FIG.  31 A  and  FIG.  31 B . A plurality of circuits (systems) are mounted on the chip  1200 . A technique for integrating a plurality of circuits (systems) into one chip is referred to as system on chip (SoC) in some cases. 
     As shown in  FIG.  31 A , the chip  1200  includes a CPU  1211 , a GPU  1212 , one or more analog arithmetic units  1213 , one or more memory controllers  1214 , one or more interfaces  1215 , one or more network circuits  1216 , and the like. 
     A bump (not illustrated) is provided on the chip  1200 , and as illustrated in  FIG.  31 B , the chip  1200  is connected to a first surface of a package board  1201 . In addition, a plurality of bumps  1202  are provided on a rear side of the first surface of the package board  1201 , and the package board  1201  is connected to a motherboard  1203 . 
     Storage devices such as DRAMs  1221  and a flash memory  1222  may be provided over the motherboard  1203 . For example, the DOSRAM described in the above embodiment can be used as the DRAM  1221 . In addition, for example, the NOSRAM described in the above embodiment can be used as the flash memory  1222 . 
     The CPU  1211  preferably includes a plurality of CPU cores. In addition, the GPU  1212  preferably includes a plurality of GPU cores. Furthermore, the CPU  1211  and the GPU  1212  may each include a memory for temporarily storing data. Alternatively, a common memory for the CPU  1211  and the GPU  1212  may be provided in the chip  1200 . The NOSRAM or the DOSRAM described above can be used as the memory. Moreover, the GPU  1212  is suitable for parallel computation of a number of data and thus can be used for image processing or product-sum operation. When an image processing circuit or a product-sum operation circuit using an oxide semiconductor of the present invention is provided in the GPU  1212 , image processing and product-sum operation can be performed with low power consumption. 
     In addition, since the CPU  1211  and the GPU  1212  are provided on the same chip, a wiring between the CPU  1211  and the GPU  1212  can be shortened, and the data transfer from the CPU  1211  to the GPU  1212 , the data transfer between memories included in the CPU  1211  and the GPU  1212 , and the transfer of arithmetic operation results from the GPU  1212  to the CPU  1211  after the arithmetic operation in the GPU  1212  can be performed at high speed. 
     The analog arithmetic unit  1213  includes one or both of an A/D (analog/digital) converter circuit and a D/A (digital/analog) converter circuit. Furthermore, the product-sum operation circuit may be provided in the analog arithmetic unit  1213 . 
     The memory controller  1214  includes a circuit functioning as a controller of the DRAM  1221  and a circuit functioning as an interface of the flash memory  1222 . 
     The interface  1215  includes an interface circuit for an external connection device such as a display device, a speaker, a microphone, a camera, or a controller. Examples of the controller include a mouse, a keyboard, and a game controller. As such an interface, a USB (Universal Serial Bus), an HDMI (registered trademark) (High-Definition Multimedia Interface), or the like can be used. 
     The network circuit  1216  includes a network circuit such as a LAN (Local Area Network). The network circuit  1216  may further include a circuit for network security. 
     The circuits (systems) can be formed in the chip  1200  through the same manufacturing process. Therefore, even when the number of circuits needed for the chip  1200  increases, there is no need to increase the number of steps in the manufacturing process; thus, the chip  1200  can be manufactured at low cost. 
     The motherboard  1203  provided with the package board  1201  on which the chip  1200  including the GPU  1212  is mounted, the DRAMs  1221 , and the flash memory  1222  can be referred to as a GPU module  1204 . 
     The GPU module  1204  includes the chip  1200  using SoC technology, and thus can have a small size. In addition, the GPU module  1204  is excellent in image processing, and thus is suitably used in a portable electronic device such as a smartphone, a tablet terminal, a laptop PC, or a portable (mobile) game machine. Furthermore, the product-sum operation circuit using the GPU  1212  can perform a method such as a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), or a deep belief network (DBN); hence, the chip  1200  can be used as an AI chip or the GPU module  1204  can be used as an AI system module. 
     At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with any of those in the other embodiments and the other examples described in this specification. 
     Embodiment 5 
     In this embodiment, examples of electronic components and electronic devices in which the storage device or the like described in the above embodiment is incorporated are described. 
     &lt;Electronic Component&gt; 
     First,  FIG.  32 A  and  FIG.  32 B  illustrate examples of an electronic component including a storage device  720 . 
       FIG.  32 A  is a perspective view of an electronic component  700  and a substrate (circuit board  704 ) on which the electronic component  700  is mounted. The electronic component  700  in  FIG.  32 A  includes the storage device  720  in a mold  711 .  FIG.  32 A  omits part of the electronic component to show the inside of the electronic component  700 . The electronic component  700  includes a land  712  outside the mold  711 . The land  712  is electrically connected to an electrode pad  713 , and the electrode pad  713  is electrically connected to the storage device  720  via a wire  714 . The electronic component  700  is mounted on a printed circuit board  702 , for example. A plurality of such electronic components are combined and electrically connected to each other on the printed circuit board  702 , which forms the circuit board  704 . 
     The storage device  720  includes a driver circuit layer  721  and a storage circuit layer  722 . 
       FIG.  32 B  is a perspective view of an electronic component  730 . The electronic component  730  is an example of a SiP (System in package) or an MCM (Multi Chip Module). In the electronic component  730 , an interposer  731  is provided over a package board  732  (printed circuit board) and a semiconductor device  735  and a plurality of storage devices  720  are provided over the interposer  731 . 
     The electronic component  730  using the storage device  720  as a high bandwidth memory (HBM) is illustrated as an example. An integrated circuit (a semiconductor device) such as a CPU, a GPU, or an FPGA can be used as the semiconductor device  735 . 
     As the package board  732 , a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used. As the interposer  731 , a silicon interposer, a resin interposer, or the like can be used. 
     The interposer  731  includes a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. The plurality of wirings have a single-layer structure or a layered structure. The interposer  731  has a function of electrically connecting an integrated circuit provided on the interposer  731  to an electrode provided on the package board  732 . Accordingly, the interposer is sometimes referred to as a “redistribution substrate” or an “intermediate substrate”. A through electrode may be provided in the interposer  731  to be used for electrically connecting the integrated circuit and the package board  732 . In the case of using a silicon interposer, a through-silicon via (TSV) can also be used as the through electrode. 
     A silicon interposer is preferably used as the interposer  731 . The silicon interposer can be manufactured at lower cost than an integrated circuit because it is not necessary to provide an active element. Moreover, since wirings of the silicon interposer can be formed through a semiconductor process, the formation of minute wirings, which is difficult for a resin interposer, is easily achieved. 
     An HBM needs to be connected to many wirings to achieve a wide memory bandwidth. Therefore, an interposer on which an HBM is mounted requires minute and densely formed wirings. For this reason, a silicon interposer is preferably used as the interposer on which an HBM is mounted. 
     In a SiP, an MCM, or the like using a silicon interposer, a decrease in reliability due to a difference in expansion coefficient between an integrated circuit and the interposer is less likely to occur. Furthermore, a surface of a silicon interposer has high planarity, and a poor connection between the silicon interposer and an integrated circuit provided thereon is less likely to occur. It is particularly preferable to use a silicon interposer for a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer. 
     A heat sink (radiator plate) may be provided to overlap the electronic component  730 . In the case of providing a heat sink, the heights of integrated circuits provided on the interposer  731  are preferably the same. In the electronic component  730  of this embodiment, the heights of the storage device  720  and the semiconductor device  735  are preferably the same, for example. 
     An electrode  733  may be provided on the bottom portion of the package board  732  to mount the electronic component  730  on another substrate.  FIG.  32 B  illustrates an example in which the electrode  733  is formed of a solder ball. Solder balls are provided in a matrix on the bottom portion of the package board  732 , whereby a BGA (Ball Grid Array) can be achieved. Alternatively, the electrode  733  may be formed of a conductive pin. When conductive pins are provided in a matrix on the bottom portion of the package board  732 , a PGA (Pin Grid Array) can be achieved. 
     The electronic component  730  can be mounted on another substrate by various mounting methods not limited to BGA and PGA. For example, a mounting method such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be employed. 
     The structure, method, and the like described in this embodiment can be used in an appropriate combination with any of other structures, methods, and the like described in this embodiment or the other embodiments. 
     Embodiment 6 
     In this embodiment, application examples of the storage device using the semiconductor device described in the above embodiment are described. The semiconductor device described in the above embodiment can be applied to, for example, storage devices of a variety of electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), video recording/reproducing devices, and navigation systems). Here, the computers refer not only to tablet computers, notebook computers, and desktop computers, but also to large computers such as server systems. Alternatively, the semiconductor device described in the above embodiment is applied to a variety of removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives).  FIG.  33 A  to  FIG.  33 E  schematically illustrate some structure examples of removable storage devices. The semiconductor device described in the above embodiment is processed into a packaged memory chip and used in a variety of storage devices and removable memories, for example. 
       FIG.  33 A  is a schematic view of a USB memory. A USB memory  1100  includes a housing  1101 , a cap  1102 , a USB connector  1103 , and a substrate  1104 . The substrate  1104  is held in the housing  1101 . The substrate  1104  is provided with a memory chip  1105  and a controller chip  1106 , for example. The semiconductor device described in the above embodiment can be incorporated in the memory chip  1105  or the like. 
       FIG.  33 B  is a schematic external view of an SD card, and  FIG.  33 C  is a schematic view of the internal structure of the SD card. An SD card  1110  includes a housing  1111 , a connector  1112 , and a substrate  1113 . The substrate  1113  is held in the housing  1111 . The substrate  1113  is provided with a memory chip  1114  and a controller chip  1115 , for example. When the memory chip  1114  is also provided on the back side of the substrate  1113 , the capacity of the SD card  1110  can be increased. In addition, a wireless chip with a radio communication function may be provided on the substrate  1113 . With this, data can be read from and written in the memory chip  1114  by radio communication between a host device and the SD card  1110 . The semiconductor device described in the above embodiment can be incorporated in the memory chip  1114  or the like. 
       FIG.  33 D  is a schematic external view of an SSD, and  FIG.  33 E  is a schematic view of the internal structure of the SSD. An SSD  1150  includes a housing  1151 , a connector  1152 , and a substrate  1153 . The substrate  1153  is held in the housing  1151 . The substrate  1153  is provided with a memory chip  1154 , a memory chip  1155 , and a controller chip  1156 , for example. The memory chip  1155  is a work memory of the controller chip  1156 , and a DOSRAM chip can be used, for example. When the memory chip  1154  is also provided on the back side of the substrate  1153 , the capacity of the SSD  1150  can be increased. The semiconductor device described in the above embodiment can be incorporated in the memory chip  1154  or the like. 
     At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with any of those in the other embodiments and the other examples described in this specification. 
     Embodiment 7 
     The semiconductor device of one embodiment of the present invention can be used as a processor such as a CPU and a GPU or a chip.  FIG.  34 A  to  FIG.  34 H  illustrate specific examples of electronic devices including a chip or a processor such as a CPU or a GPU of one embodiment of the present invention. 
     &lt;Electronic Device and System&gt; 
     The GPU or the chip of one embodiment of the present invention can be mounted on a variety of electronic devices. Examples of electronic devices include a digital camera, a digital video camera, a digital photo frame, an e-book reader, a mobile phone, a portable game machine, a portable information terminal, and an audio reproducing device in addition to electronic devices provided with a relatively large screen, such as a television device, a monitor for a desktop or notebook information terminal or the like, digital signage, and a large game machine like a pachinko machine. When the GPU or the chip of one embodiment of the present invention is provided in the electronic device, the electronic device can include artificial intelligence. 
     The electronic device of one embodiment of the present invention may include an antenna. When a signal is received by the antenna, the electronic device can display a video, data, or the like on a display portion. When the electronic device includes the antenna and a secondary battery, the antenna may be used for contactless power transmission. 
     The electronic device of one embodiment of the present invention may include a sensor (a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, a chemical substance, sound, time, hardness, an electric field, current, voltage, power, radioactive rays, flow rate, humidity, a gradient, oscillation, odor, or infrared rays). 
     The electronic device of one embodiment of the present invention can have a variety of functions. For example, the electronic device can have a function of displaying a variety of data (a still image, a moving image, a text image, and the like) on the display portion, a touch panel function, a function of displaying a calendar, date, time, and the like, a function of executing a variety of software (programs), a wireless communication function, and a function of reading out a program or data stored in a recording medium.  FIG.  34 A  to  FIG.  34 H  illustrate examples of electronic devices. 
     [Information Terminal] 
       FIG.  34 A  illustrates a mobile phone (smartphone), which is a type of information terminal. An information terminal  5100  includes a housing  5101  and a display portion  5102 . As input interfaces, a touch panel is provided in the display portion  5102  and a button is provided in the housing  5101 . 
     When the chip of one embodiment of the present invention is applied to the information terminal  5100 , the information terminal  5100  can execute an application utilizing artificial intelligence. Examples of the application utilizing artificial intelligence include an application for recognizing a conversation and displaying the content of the conversation on the display portion  5102 ; an application for recognizing letters, figures, and the like input to the touch panel of the display portion  5102  by a user and displaying them on the display portion  5102 ; and an application for performing biometric authentication using fingerprints, voice prints, or the like. 
       FIG.  34 B  illustrates a notebook information terminal  5200 . The notebook information terminal  5200  includes a main body  5201  of the information terminal, a display portion  5202 , and a keyboard  5203 . 
     Like the information terminal  5100  described above, when the chip of one embodiment of the present invention is applied to the notebook information terminal  5200 , the notebook information terminal  5200  can execute an application utilizing artificial intelligence. Examples of the application utilizing artificial intelligence include design-support software, text correction software, and software for automatic menu generation. Furthermore, with the use of the notebook information terminal  5200 , novel artificial intelligence can be developed. 
     Note that although  FIG.  34 A  and  FIG.  34 B  illustrate a smartphone and a notebook information terminal, respectively, as examples of the electronic device in the above description, an information terminal other than a smartphone and a notebook information terminal can be used. Examples of information terminals other than a smartphone and a notebook information terminal include a PDA (Personal Digital Assistant), a desktop information terminal, and a workstation. 
     [Game Machines] 
       FIG.  34 C  illustrates a portable game machine  5300  as an example of a game machine. The portable game machine  5300  includes a housing  5301 , a housing  5302 , a housing  5303 , a display portion  5304 , a connection portion  5305 , an operation key  5306 , and the like. The housing  5302  and the housing  5303  can be detached from the housing  5301 . When the connection portion  5305  provided in the housing  5301  is attached to another housing (not illustrated), an image to be output to the display portion  5304  can be output to another video device (not illustrated). In that case, the housing  5302  and the housing  5303  can each function as an operating unit. Thus, a plurality of players can play a game at the same time. The chip described in the above embodiment can be incorporated into the chip provided on a substrate in the housing  5301 , the housing  5302  and the housing  5303 . 
       FIG.  34 D  illustrates a stationary game machine  5400  as an example of a game machine. A controller  5402  is wired or connected wirelessly to the stationary game machine  5400 . 
     Using the GPU or the chip of one embodiment of the present invention in a game machine such as the portable game machine  5300  and the stationary game machine  5400  achieves a low-power-consumption game machine. Moreover, heat generation from a circuit can be reduced owing to low power consumption; thus, the influence of heat generation on the circuit, a peripheral circuit, and a module can be reduced. 
     Furthermore, when the GPU or the chip of one embodiment of the present invention is applied to the portable game machine  5300 , the portable game machine  5300  including AI can be achieved. 
     In general, the progress of a game, the actions and words of game characters, and expressions of an event and the like occurring in the game are determined by the program in the game; however, the use of artificial intelligence in the portable game machine  5300  enables expressions not limited by the game program. For example, it becomes possible to change expressions such as questions posed by the player, the progress of the game, time, and actions and words of game characters. 
     In addition, when a game requiring a plurality of players is played on the portable game machine  5300 , the artificial intelligence can create a virtual game player; thus, the game can be played alone with the game player created by the artificial intelligence as an opponent. 
     Although the portable game machine and the stationary game machine are illustrated as examples of game machines in  FIG.  34 C  and  FIG.  34 D , the game machine using the GPU or the chip of one embodiment of the present invention is not limited thereto. Examples of the game machine to which the GPU or the chip of one embodiment of the present invention is applied include an arcade game machine installed in entertainment facilities (a game center, an amusement park, and the like), and a throwing machine for batting practice installed in sports facilities. 
     [Large Computer] 
     The GPU or the chip of one embodiment of the present invention can be used in a large computer. 
       FIG.  34 E  illustrates a supercomputer  5500  as an example of a large computer.  FIG.  34 F  illustrates a rack-mount computer  5502  included in the supercomputer  5500 . 
     The supercomputer  5500  includes a rack  5501  and a plurality of rack-mount computers  5502 . The plurality of computers  5502  are stored in the rack  5501 . The computer  5502  includes a plurality of substrates  5504  on which the GPU or the chip shown in the above embodiment can be mounted. 
     The supercomputer  5500  is a large computer mainly used for scientific computation. In scientific computation, an enormous amount of arithmetic operation needs to be processed at a high speed; hence, power consumption is large and chips generate a large amount of heat. Using the GPU or the chip of one embodiment of the present invention in the supercomputer  5500  achieves a low-power-consumption supercomputer. Moreover, heat generation from a circuit can be reduced owing to low power consumption; thus, the influence of heat generation on the circuit, a peripheral circuit, and a module can be reduced. 
     Although a supercomputer is illustrated as an example of a large computer in  FIG.  34 E  and  FIG.  34 F , a large computer using the GPU or the chip of one embodiment of the present invention is not limited thereto. Other examples of large computers in which the GPU or the chip of one embodiment of the present invention is usable include a computer that provides service (a server) and a large general-purpose computer (a mainframe). 
     [Moving Vehicle] 
     The GPU or the chip of one embodiment of the present invention can be applied to an automobile, which is a moving vehicle, and the periphery of a driver&#39;s seat in the automobile. 
       FIG.  34 G  illustrates an area around a windshield inside an automobile, which is an example of a moving vehicle.  FIG.  34 G  illustrates a display panel  5701 , a display panel  5702 , and a display panel  5703  that are attached to a dashboard and a display panel  5704  that is attached to a pillar. 
     The display panel  5701  to the display panel  5703  can provide a variety of kinds of information by displaying a speedometer, a tachometer, mileage, a fuel gauge, a gear state, air-condition setting, and the like. In addition, the content, layout, or the like of the display on the display panels can be changed as appropriate to suit the user&#39;s preference, so that the design quality can be increased. The display panel  5701  to the display panel  5703  can also be used as lighting devices. 
     The display panel  5704  can compensate for view obstructed by the pillar (a blind spot) by showing an image taken by an imaging device (not illustrated) provided for the automobile. That is, displaying an image taken by the imaging device provided outside the automobile leads to compensation for the blind spot and an increase in safety. In addition, displaying an image to compensate for a portion that cannot be seen makes it possible for the driver to confirm the safety more naturally and comfortably. The display panel  5704  can also be used as a lighting device. 
     Since the GPU or the chip of one embodiment of the present invention can be applied to a component of artificial intelligence, the chip can be used for an automatic driving system of the automobile, for example. The chip can also be used for a system for navigation, risk prediction, or the like. A structure may be employed in which the display panel  5701  to the display panel  5704  display navigation information, risk prediction information, or the like. 
     Note that although an automobile is described above as an example of a moving vehicle, the moving vehicle is not limited to an automobile. Examples of the moving vehicle include a train, a monorail train, a ship, and a flying vehicle (a helicopter, an unmanned aircraft (a drone), an airplane, and a rocket), and these moving vehicles can each include a system utilizing artificial intelligence when the chip of one embodiment of the present invention is applied to each of these moving vehicles. 
     [Household Appliance] 
       FIG.  34 H  illustrates an electric refrigerator-freezer  5800  as an example of a household appliance. The electric refrigerator-freezer  5800  includes a housing  5801 , a refrigerator door  5802 , a freezer door  5803 , and the like. 
     When the chip of one embodiment of the present invention is applied to the electric refrigerator-freezer  5800 , the electric refrigerator-freezer  5800  including artificial intelligence can be achieved. Utilizing the artificial intelligence enables the electric refrigerator-freezer  5800  to have a function of automatically making a menu based on foods stored in the electric refrigerator-freezer  5800 , expiration dates of the foods, or the like, a function of automatically adjusting temperature to be appropriate for the foods stored in the electric refrigerator-freezer  5800 , and the like. 
     Although the electric refrigerator-freezer is described in this example as a household appliance, examples of other household appliances include a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, a heating-cooling combination appliance such as an air conditioner, a washing machine, a drying machine, and an audio visual appliance. 
     The electronic devices, the functions of the electronic devices, the application examples of artificial intelligence, their effects, and the like described in this embodiment can be combined as appropriate with the description of another electronic device. 
     At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with any of those in the other embodiments and the other examples described in this specification. 
     Example 1 
     In this example, Sample 1A to Sample 1C having a structure illustrated in  FIG.  35    were fabricated and analyzed by SIMS. 
     A structure  910  illustrated in  FIG.  35    includes a substrate  911 , an insulator  912  over the substrate  911 , and an insulator  914  over the insulator  912 . 
     Next, a method for fabricating the samples will be described. First, a silicon wafer was prepared as the substrate  911 . Then, a 100-nm-thick silicon oxide film was formed by a thermal oxidation method as the insulator  912  over the substrate  911 . 
     Next, silicon oxide was deposited as the insulator  914  over the insulator  912 . For Samples 1A to 1C, the silicon oxide was deposited under different conditions. In Sample 1A, a 30-nm-thick silicon oxide film was formed by a PECVD method using SiH 4  and N 2 O at a substrate temperature of 350° C. Here, the ratio between the flow rate of SiH 4  and the flow rate of N 2 O (SiH 4 :N 2 O) was 1:800. In addition, in Sample 1B, a 20-nm-thick silicon oxide film was formed by a PEALD method using SiH 4  as a precursor and N 2 O as an oxidizing gas film at a substrate temperature of 350° C. Here, the ratio between the flow rate of SiH 4  and the flow rate of N 2 O (SiH 4 :N 2 O) was 1:400. In Sample 1C, a 20-nm-thick silicon oxide film was formed by a PEALD method using SiH 4  as a precursor, N 2 O as an oxidizing gas, and N 2  as a dilution gas at a substrate temperature of 350° C. The deposition was performed in accordance with the flow illustrated in  FIG.  5    and the sequence illustrated in  FIG.  6 B . Here, the ratio between the flow rate of SiH 4  and the total flow rate of N 2 O and N 2  were (SiH 4 :(N 2 O+N 2 )) 1:400. The ratio between the flow rate of N 2 O and the flow rate of N 2  flow rate (N 2 O:N 2 ) was 1:4. 
     Hydrogen concentrations and nitrogen concentrations of Sample 1A to Sample 1C were evaluated with use of a SIMS analysis apparatus. With the insulator  914  as the quantified layer, analysis was performed from the surface of the insulator  914  toward the substrate  911 . 
     SIMS analysis results of Sample 1A to Sample 1C are shown below. The hydrogen concentrations of Sample 1A, Sample 1B, and Sample 1C are shown in  FIG.  36 A ,  FIG.  36 B , and  FIG.  36 C , respectively. The nitrogen concentrations of Sample 1A, Sample 1B, and Sample 1C are shown in  FIG.  37 A ,  FIG.  37 B , and  FIG.  37 C , respectively. Note that in each graph, a background (BG) level is indicated by a solid line. 
     As shown in  FIG.  36 A , the hydrogen concentration in the insulator  914  of Sample 1A formed by a PECVD method falls in the range of from approximately 7.0×10 19  atoms/cm 3  to 4.5×10 20  atoms/cm 3 , inclusive. As shown in  FIG.  36 B , the hydrogen concentration in the insulator  914  of Sample 1B formed by a PEALD method using SiH 4  as a precursor and N 2 O as an oxidizing gas falls in the range of from approximately 2.5×10 19  atoms/cm 3  to 2.0×10 20  atoms/cm 3 , inclusive. As shown in  FIG.  36 C , the hydrogen concentration in the insulator  914  of Sample 1C formed by a PEALD method using SiH 4  as a precursor, N 2 O as an oxidizing gas, and N 2  as a dilution gas falls in the range of from approximately 2.0×10 19  atoms/cm 3  to 7.0×10 19  atoms/cm 3 , inclusive. 
     The nitrogen concentration in the insulator  914  of Sample 1A formed by PECVD method, the nitrogen concentration in the insulator  914  of Sample 1B formed by a PEALD method using SiH 4  as a precursor and N 2 O as an oxidizing gas, and the nitrogen concentration in the insulator  914  of Sample 1C formed by a PEALD method using SiH 4  as a precursor, N 2 O as an oxidizing gas, and N 2  as a dilution gas fall in the range of from approximately 2.0×10 20  atoms/cm 3  to 5.0×10 20  atoms/cm 3 , inclusive. There was no difference of the nitrogen concentrations depending on the deposition methods (see  FIG.  37 A  to  FIG.  37 C ). 
     Thus, it is found that the hydrogen concentration in the silicon oxide film formed by a PEALD method using SiH 4  as a precursor and N 2 O as an oxidizing gas is lower than the hydrogen concentration in the silicon oxide film formed by a PECVD method. Furthermore, it is found that the hydrogen concentration in the silicon oxide film formed by a PEALD method using SiH 4  as a precursor, N 2 O as an oxidizing gas, and N 2  as the dilution gas is lower than the hydrogen concentration in the silicon oxide film formed by a PEALD method using SiH 4  as a precursor and N 2 O as an oxidizing gas. Accordingly, the deposition method of one embodiment of the present invention that is a PEALD method using SiH 4  as a precursor, N 2 O as an oxidizing gas, and N 2  as the dilution gas can provide a good-quality silicon oxide film with a low hydrogen concentration. Furthermore, the nitrogen concentration in the silicon oxide film was approximately the same as the nitrogen concentration in the silicon oxide film formed by a PECVD method. 
     At least part of the structure, method, and the like described in this example can be implemented in appropriate combination with any of those in the other embodiments and the other examples described in this specification. 
     Example 2 
     In this example, for evaluation of oxidation capability in the plasma application step, corresponding to Step S 03  in th process flow illustrated in  FIG.  5   , a receipt for the plasma step illustrated in  FIG.  38    was formed, oxidation is caused directly on a silicon wafer and oxidation capabilities were compared. In  FIG.  38   , an introduction period of N 2 O (N 2 O ON), an introduction period of N 2  (N 2  ON), and an application period of a radio frequency power (RF ON) are shown. In this example, the plasma treatment time (the application period of a radio frequency power) was fixed to 180 sec, and the total flow rate of N 2 O and N 2  was 4000 sccm, and the flow rate ratio between the flow rate of N 2 O and the flow rate of N 2  (N 2 O:N 2 ) was changed for each sample for evaluation. For Sample 2A, only N 2 O and no N 2  dilution were used; for Sample 2B, the flow rate ratio between the flow rate of N 2 O and the flow rate of N 2  was (N 2 O:N 2 ) 3:1; for Sample 2C, the flow rate ratio between the flow rate of N 2 O and the flow rate of N 2  (N 2 O:N 2 ) was 1:1; and for Sample 2D, the flow rate ratio between the flow rate of N 2 O and the flow rate of N 2  was (N 2 O:N 2 ) 1:4. The thicknesses of oxide films on the silicon wafer were measured using a spectroscopic ellipsometer. 
     The results are shown in  FIG.  39   . As a result, it was found that as the flow rate ratio between the flow rate of N 2 O and the flow rate of N 2  (N 2 O:N 2 ) was smaller, that is, as the proportion of the flow rate of N 2  was larger than the proportion of the flow rate of N 2 O, the thickness of the oxide film on the silicon wafer was larger. In the comparison of the thicknesses of the oxide films between Sample 2A using only N 2 O and Sample 2D at (N 2 O:N 2 )=1:4, the thickness of the oxide film of Sample 2D at (N 2 O:N 2 )=1:4 was about 1.15 times that of Sample 2A. Thus, it is considered that the oxidation capability in the plasma application step was strengthened by adding N 2  to N 2 O to be diluted. This result indicates that adding N 2  to N 2 O to be diluted increased radical species such as an O radical. 
     At least part of the structure, method, and the like described in this example can be implemented in appropriate combination with any of those in the other embodiments and the other examples described in this specification. 
     Example 3 
     In this example, calculation was performed on how often an O radical takes hydrogen (H) bonded to silicon (Si). For the calculation, quantum chemical calculation software (Gaussian) was used. The main conditions are listed in Table 1. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
             
            
               
                   
                 Software 
                 Gaussian09 
               
               
                   
                 Calculation method 
                 Density functional theory 
               
               
                   
                 Functional 
                 uHSEH1PBE 
               
               
                   
                 Spin state 
                 Triplet 
               
               
                   
                 Basis function 
                 6-31 + G(d) 
               
               
                   
                 Calculation 
                 Reaction path analysis (Structure 
               
               
                   
                   
                 optimization, IRC, vibration analysis) 
               
               
                   
                   
               
            
           
         
       
     
     In the calculation, the distance between an O atom and one H atom of SiH 4  is changed to obtain energies and structure optimization was performed on the transition state with the highest energy as a starting point. To verify whether the transition state was right, vibration calculation was performed to confirm that there is only one imaginary frequency. Next, Intrinsic Reaction Coordinate (IRC) calculation was performed, and a structure optimization was performed from the structure obtained by the IRC calculation, and energies of a reactant, a transition state, and a product were calculated.  FIG.  40 A  shows a structure of the reactant (Reactant),  FIG.  40 B  shows a structure of the transition state (Transition State), and  FIG.  40 C  shows a structure of a product (Product).  FIG.  41    shows the energy of each state in which zero-point motion was considered. 
     As shown in  FIG.  41   , the energy of the transition state is lower than the energy of the reactant, and the energy of the product is lower that the energy of the transition state, and thus when O takes H from SiH 4 , no activation barrier is considered. Probably, this reaction can easily occur. Thus, since release of H often occurs in the environment having a large number of O radicals, it is suggested that the film formed by a PEALD method using N 2 O diluted with added N 2  contained hydrogen at a lower concentration. 
     At least part of the structure, method, and the like described in this example can be implemented in appropriate combination with any of those in the other embodiments and the other examples described in this specification. 
     REFERENCE NUMERALS 
     M 1 : transistor, M 2 : transistor, M 3 : transistor, M 4 : transistor, M 5 : transistor, M 6 : transistor,  100 : capacitor,  110 : conductor,  112 : conductor,  115 : conductor,  120 : conductor,  125 : conductor,  130 : insulator,  140 : conductor,  142 : insulator,  145 : insulator,  150 : insulator,  152 : insulator,  153 : conductor,  154 : insulator,  156 : insulator,  200 : transistor,  200   a : transistor,  200   b : transistor,  205 : conductor,  205   a : conductor,  205   b : conductor,  210 : insulator,  212 : insulator,  214 : insulator,  216 : insulator,  217 : insulator,  218 : conductor,  222 : insulator,  224 : insulator,  224 A: insulating film,  230 : oxide,  230   a : oxide,  230 A: oxide film,  230   b : oxide,  230 B: oxide film,  230   ba : region,  230   bb : region,  230   bc : region,  240 : conductor,  240   a : conductor,  240   b : conductor,  241 : insulator,  241   a : insulator,  241   b : insulator,  242 : conductor,  242   a : conductor,  242 A: conductive film,  242   b : conductor,  242 B: conductive layer,  242   c : conductor,  246 : conductor,  246   a : conductor,  246   b : conductor,  250 : insulator,  250   a : insulator,  250 A: insulating film,  250   b : insulator,  250 B: insulating film,  250   c : insulator,  252 : insulator,  252 A: insulating film,  260 : conductor,  260   a : conductor,  260   b : conductor,  265 : sealing portion,  271 : insulator,  271   a : insulator,  271 A: insulating film,  271   b : insulator,  271 B: insulating layer,  271   c : insulator,  274 : insulator,  275 : insulator,  280 : insulator,  282 : insulator,  283 : insulator,  285 : insulator,  290 : memory device,  292 : capacitor device,  292   a : capacitor device,  292   b : capacitor device,  294 : conductor,  294   a : conductor,  294   b : conductor,  300 : transistor,  311 : substrate,  313 : semiconductor region,  314   a : low-resistance region,  314   b : low-resistance region,  315 : insulator,  316 : conductor,  320 : insulator,  322 : insulator,  324 : insulator,  326 : insulator,  328 : conductor,  330 : conductor,  350 : insulator,  352 : insulator,  354 : insulator,  356 : conductor,  400 : opening region,  401 : gas,  402 : oxidizing gas,  403 : high-frequency power,  405 : dilution gas,  500 : semiconductor device,  600 : semiconductor device,  601 : semiconductor device,  610 : cell array,  610 _ n : cell array,  610 _ 1 : cell array,  700 : electronic component,  702 : printed circuit board,  704 : circuit substrate,  711 : mold,  712 : land,  713 : electrode pad,  714 : wire,  720 : storage device,  721 : driver circuit layer,  722 : storage circuit layer,  730 : electronic component,  731 : interposer,  732 : package board,  733 : electrode,  735 : semiconductor device,  910 : structure,  911 : substrate,  912 : insulator,  914 : insulator,  1001 : wiring,  1002 : wiring,  1003 : wiring,  1004 : wiring,  1005 : wiring,  1006 : wiring,  1100 : USB memory,  1101 : housing,  1102 : cap,  1103 : USB connector,  1104 : substrate,  1105 : memory chip,  1106 : controller chip,  1110 : SD card,  1111 : housing,  1112 : connector,  1113 : substrate,  1114 : memory chip,  1115 : controller chip,  1150 : SSD,  1151 : housing,  1152 : connector,  1153 : substrate,  1154 : memory chip,  1155 : memory chip,  1156 : controller chip,  1200 : chip,  1201 : package board,  1202 : bump,  1203 : motherboard,  1204 : GPU module,  1211 : CPU,  1212 : GPU,  1213 : analog arithmetic unit,  1214 : memory controller,  1215 : interface,  1216 : network circuit,  1221 : DRAM,  1222 : flash memory,  1400 : storage device,  1411 : peripheral circuit,  1420 : row circuit,  1430 : column circuit,  1440 : output circuit,  1460 : control logic circuit,  1470 : memory cell array,  1471 : memory cell,  1472 : memory cell,  1473 : memory cell,  1474 : memory cell,  1475 : memory cell,  1476 : memory cell,  1477 : memory cell,  1478 : memory cell,  2700 : manufacturing apparatus,  2701 : atmosphere-side substrate supply chamber,  2702 : atmosphere-side substrate transfer chamber,  2703   a : load lock chamber,  2703   b : unload lock chamber,  2704 : transfer chamber,  2706   a : chamber,  2706   b : chamber,  2706   c : chamber,  2706   d : chamber,  2761 : cassette port,  2762 : alignment port,  2763   a : transfer robot,  2763   b : transfer robot,  2801 : gas supply source,  2802 : valve,  2803 : high-frequency generator,  2804 : waveguide,  2805 : mode converter,  2806 : gas pipe,  2807 : waveguide,  2808 : slot antenna plate,  2809 : dielectric plate,  2810 : high-density plasma,  2811 : substrate,  2811 _ n : substrate,  2811 _ n −1: substrate,  2811 _ n −2: substrate,  2811 _ 1 : substrate,  2811 _ 2 : substrate,  2811 _ 3 : substrate,  2812 : substrate holder,  2813 : heating mechanism,  2815 : matching box,  2816 : high-frequency power source,  2817 : vacuum pump,  2818 : valve,  2819 : exhaust port,  2820 : lamp,  2821 : gas supply source,  2822 : valve,  2823 : gas inlet,  2824 : substrate,  2825 : substrate holder,  2826 : heating mechanism,  2828 : vacuum pump,  2829 : valve,  2830 : exhaust port,  2900 : microwave treatment apparatus,  2901 : quartz tube,  2902 : substrate holder,  2903 : heating means,  5100 : information terminal,  5101 : housing,  5102 : display portion,  5200 : notebook information terminal,  5201 : main body,  5202 : display portion,  5203 : keyboard,  5300 : portable game machine,  5301 : housing,  5302 : housing,  5303 : housing,  5304 : display portion,  5305 : connection portion,  5306 : operation key,  5400 : type game machine,  5402 : controller,  5500 : supercomputer,  5501 : rack,  5502 : computer,  5504 : substrate,  5701 : display panel,  5702 : display panel,  5703 : display panel,  5704 : display panel,  5800 : electric refrigerator-freezer,  5801 : housing,  5802 : refrigerator door,  5803 : freezer door