Patent Publication Number: US-RE29962-E

Title: Collector-up semiconductor circuit structure for binary logic

Description:
BACKGROUND OF THE INVENTION 
     This invention relates generally to a bipolar semiconductor switching structure including the combination of a plurality of switching transistors. More particularly, this invention relates to a bipolar semiconductor switching structure suitable for collector-up or integrated injection logic circuitry and the interconnection of a plurality of active devices as a binary circuit. 
     Although binary semiconductor switching structures have heretofore been provided, such structures have generally required excessive semiconductor area, have consumed excessive power, do not successfully combine integrated injection logic and conventional transistor circuitry and have slow operating speeds. Thus there is a need for a high performance collector-up binary structure for interconnection as a binary circuit to perform logic functions. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     Accordingly, it is a general object of the present invention to provide an improved performance, collector-up logic semiconductor structure which performs binary circuit functions. 
     It is a particular object of the present invention to provide an improved semiconductor collector-up injection logic structure which may be formed in relatively high density arrays and which is capable of greatly improved switching speeds. 
     The foregoing and other objects of the invention are achieved in a collector-up binary structure of the type having spaced semiconductor regions forming a plurality of active devices suitable for interconnection as a binary circuit. The structure includes a semiconductor body of one conductivity having a planar surface and spaced first, second, third and fourth transistors formed in said body. Fifth, sixth, seventh and eighth transistors are included said fifth and sixth transistors being formed in the base region of said second transistor. The seventh and eighth transistors are formed in the base region of said fourth transistor. Lead means is provided for ohmic contact to the respective regions of each of the respective transistors. Interconnection means is provided to connect the respective regions as a binary circuit. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of the semiconductor structure interconnected as a binary circuit. 
     FIG. 2 is a top view of a semiconductor structure showing the respective device regions interconnected as a binary circuit. 
     FIG. 3 is a cross-sectional view of the FIG. 2 semiconductor structure. 
     FIG. 4 is a schematic diagram of the semiconductor structure interconnected as a binary circuit and including additional source transistors. 
     FIG. 5 is a top view of the semiconductor structure interconnected to form a binary circuit. 
     FIG. 6 is a cross-sectional view of the FIG. 5 semiconductor structure. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A plurality of collector-up binary structures are shown in the accompanying FIGS. 1-6. Briefly, the binary structure includes integrated injection or collector-up semiconductor structures uniquely combined in an integrated circuit structure. Collector-up structures are disclosed in co-pending applications COLLECTOR-UP SEMICONDUCTOR STRUCTURE AND METHOD, Ser. No. 454,789, filed Mar. 26, 1974, invented by Lewis K. Russell and assigned to the present assignee. The collector-up structure uniquely integrates a switching transistor in combination with a source transistor which injects carriers into the switching transistor. The collector-up structure utilizes the uppermost regions formed in the semiconductor body as collector regions, hence the designation &#34;collector-up&#34; structures. 
     Collector-up binary structures have been disclosed in co-pending application COLLECTOR-UP LOGIC TRANSMISSION GATES, Ser. No. 487,756, filed July 11, 1974, invented by Lewis K. Russell and assigned to a common assignee. The binary circuit therein disclosed when implemented in a semiconductor structure occupies a substantial portion of the semiconductor body. In the present invention the binary circuit has been uniquely implemented in a semiconductor structure with a significant reduction in the required active regions and thus a reduction in the semiconductor area required. 
     Collector-up structures are preferred in the present invention because they may be formed in relatively high density arrays which operate at greatly reduced power levels. In a collector-up structure a relatively high gain source transistor is provided capable of efficiently injecting carriers into the base region of the switching transistor. For example, an NPN switching transistor may have an associated PNP source transistor. The source transistor may be vertically configured and provide betas from 40 to 250. A supply voltage of 0.8 volts provides logic levels of approximately 0.7 volts and 0.02 volts. Collector-up structures may be uniquely combined to form a binary semiconductor structure as will now be seen. 
     Referring to FIG. 1, a schematic diagram of the collector-up binary circuit is shown. Control input terminal 13 is connected to bases 17 and 28 of transistors 16 and 26 respectively, and input terminal 14 is connected to bases 24 and 32 of transistors 21 and .[.29.]. .Iadd.30 .Iaddend.respectively. The collectors 19 and 22 of transistors 16 and 21 are connected to the input of the collector-up device 36. The connection is shown as a heavy line to indicate that the connection is physically accomplished by use of a single semiconductor region as will be seen. Collector-up device 36 is shown symbolically as a transistor having an open circle at base 39 indicating a source of injection via an associated source transistor. The emitter of the collector-up device is shown using an unshaded NPN transistor symbol, thereby indicating the conductivity of the switching transistor included in said collector-up device and further indicating that the emitter 38 is connected to the common semiconductor body or substrate. Collector-up device 36 has an equivalent circuit discussed in the previously referenced co-pending application COLLECTOR-UP SEMICONDUCTOR STRUCTURE AND METHOD, Ser. No. 454,789, filed Mar. 26, 1974. The equivalent circuit of device 36 may thus be viewed as an NPN switching transistor having a base terminal 39, an emitter 38 connected to the body and a collector 37. An additional associated source transistor may be a P-N-P transistor having an emitter connected to voltage supply means, a base connected to the semiconductor body and a collector connected to base 39 of the NPN switching transistor. Collector-up device 36 has a collector 37 connected to a base 43 of collector-up device 41. Device 41 has an emitter 44 connected to said body and a collector 42. Emitter 18 of transistor 16 and emitter 27 of transistor 26 are connected to collector 42. Collectors .[.29.]. .Iadd.30 .Iaddend.and 31 .[.are.]. .Iadd.of .Iaddend.respective transistors 26 and 29 are connected to the base terminal 48 of collector-up device 46, said connection being via a common semiconductor structural region as will be seen. Collector-up device 46 includes an equivalent circuit as was previously discussed in conjunction with device 36, and has an emitter 49 connected to said body and a collector 47 connected to the base 53 of collector-up device 51. Collector 47 is also connected to emitter 23 of transistor 21 and to output terminal 71. Collector-up device 51 has an emitter 54 connected to said body and a collector 52 connected to output terminal 72. Emitter 33 of device .[.29.]. .Iadd.30 .Iaddend.is connected to output terminal 72. 
     Referring to FIGS. 2 and 3, the top and cross-sectional views of the semiconductor binary structures are shown. The prime reference numbers correspond to the reference numbers of the FIG. 1 schematic diagram. Starting with a N conductivity body 11&#39; plural P spaced regions 53&#39; and the combination region including region 22&#39;, region 19&#39; and region 39&#39; are formed, said region 53&#39; said combination region being formed in said body 11&#39; extending to surface 12&#39;. Simultaneously P region 43&#39; and the P type combination region of regions 48&#39;, 31&#39; and 29&#39; are formed in body 11&#39; extending to surface 12&#39;. 
     Next N spaced regions 24&#39;, 17&#39; and 37&#39; are formed entirely within the first combination region including regions 22&#39;, 19&#39; and 39&#39; extending to surface 12&#39;. Simultaneously N regions 32&#39;, 28&#39; and 47&#39; are formed in the second combination region including regions 48&#39;, 31&#39; and 29&#39; extending to surface 12&#39;. At the same time, spaced substantially parallel N-type stripe regions 63&#39; and 68&#39; are formed in body 11&#39; extending to substantially planar surface 12&#39;. The regions extend laterally to overlap respective portions of regions 53&#39; and 43&#39;, and the combination regions of (22&#39;, 19&#39;, 39&#39;) and (48&#39;, 31&#39;, 29&#39;). Simultaneously N-type regions 52&#39; and 42&#39; are formed entirely within respective P-type regions 53&#39; and 43&#39; extending to surface 12&#39;. Next P-type regions 23&#39; and 18&#39; are formed within respective regions 24&#39; and 17&#39; extending to surface 12&#39;. Simultaneously P-type regions 33&#39; and 27&#39; are formed within regions 32&#39; and 28&#39; extending to surface 12&#39;. At the same time P-type stripe source regions 62&#39; and 67&#39; are formed entirely within respective N-type regions 63&#39; and 68&#39; extending to surface 12&#39;. P regions 62&#39; and 67&#39; extend laterally within the portions of respective stripe regions 63&#39; and 68&#39; which overlap portions of regions 53&#39;, 43&#39;, (22&#39;, 19&#39;, 39&#39;), and (48&#39;, 31&#39;, 29&#39;). 
     Lead means and interconnect means is provided to contact and interconnect the various respective regions. Lead means may comprise ohmic metal contacts such as the formation of aluminum contacts with each of the respective regions, and interconnect means may comprise a patterned aluminum layer. The aluminum  layer may be formed to simultaneously contact the respective regions and subsequently patterned to provide interconnection. Electrical interconnection is as previously described in conjunction with the FIG. 1 schematic diagram. 
     Turning to operation, an input signal having a first period T and having input C and complement C is provided at terminal 13 and 14 respectively. The signal is caused to propagate with time via the respective transistor pairs 16 and 26 and alternately 21 and 29, passing via collector-up structures 36 and 41 and alternately collector-up structures 46 and 51 to thereby provide an output signal at terminals 71 and 72 having a period 2T. Suitable voltage means for operation of the circuit may be provided by connecting first terminal of a voltage supply to stripe regions 62&#39; and 67&#39; and the second voltage supply terminal to the semiconductor body 11&#39;. 
     Referring to FIGS. 4, 5, and 6, an additional embodiment of the binary structure is shown wherein the source transistors previously associated with collector-up structures 36 and 46 may be omitted and additional PNP devices 61 and 66 are provided. PNP device 61 includes emitter 62, connected to voltage supply terminal 58, base region 63 connected to the common ground or semiconductor body, and collector 64 connected to collector 42 of collector-up device 41. Similarly, device 66 has an emitter 67 connected to voltage supply terminal 58, a base 68 connected to the common ground or semiconductor body and a collector 69 connected to a collector 52 of collector-up device 51. It is to be noted in operation that the respective devices 61 and 66 are source transistors providing current for the respective collector-up devices for improved switching operation. 
     Referring to FIGS. 5 and 6, it is to be noted that the first P type combination region including regions 48&#39;, 31&#39; and 29&#39; and the P type second combination region including regions 22&#39; and 19&#39; and 39&#39; have been spaced from the respective N type regions 63&#39; and 68&#39;. Moreover, additional P type regions 64&#39; and 69&#39;, formed simultaneously with the previously described combination regions and regions 43&#39; and 53&#39; have been added to the structure. P regions 69&#39; is formed in body 11&#39; and extends to surface 12&#39;. The combination of regions 67&#39; and 68&#39; extends laterally to overlap a portion of region 69&#39;. Similarly, P type region 64&#39; is formed in body 11&#39; extending to surface 12&#39;. The combination of regions 62&#39; and 63&#39; extends laterally to overlap a portion of regions 64&#39;. The respective PNP devices 61 and 66 thus formed have lead means and interconnecting means connected to the respective regions thereof to interpose respective transistors 61&#39; and 66&#39; as previously discussed in conjunction with the schematic diagram of FIG. 4. 
     Thus it is apparent that there has been provided an improved performance, collector-up logic semiconductor structure for performing binary circuit functions. It is further apparent that the present invention provides an improved semiconductor collector-up logic structure which may be formed in relatively high density arrays and which is capable of greatly improved switching speeds.