Patent Publication Number: US-10770411-B2

Title: Device comprising a stack of electronic chips

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional application of U.S. patent application Ser. No. 15/609,783 filed May 31, 2017, which claims the priority benefit of French patent application number 16/60568, filed on Oct. 31, 2016, all of which are incorporated herein by reference in their entirety. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to the field of electronic chips and, in particular embodiments, to a device comprising a stack of interconnected electronic chips. 
     BACKGROUND 
     Certain electronic chips, such as bank card chips, may contain confidential data which may be coveted by pirates. Such confidential data may be contained in circuits located on the front surface side of the chip. To obtain the data, a pirate may carry out an attack from the back side of the chip. 
     In a type of attack, called etch attack, the pirate etches a portion of the back side of the chip. From this etched portion, the pirate makes cavities having a width of a few micrometers, for example, by using an ion beam, which extend towards the front side until the circuits have been reached. Electric contacts with circuit elements are then created in the cavities, and the pirate uses these contacts to analyze the chip in operation. 
     In another type of attack, the pirate for example scans the back side of the chip with laser pulses. The impact of the laser disturbs the chip operation. The observation of the consequences of such disturbances on the activity of the circuits enables the pirate to successfully complete the attack. To disturb the chip operation, the pirate may also apply positive or negative potentials by means of a probe in contact with the back side, or induce currents or voltages in elements of the circuits by means of a coil arranged close to the back side. 
     This type of attack is called fault injection attack. 
     Such a chip comprising confidential data may be comprised in a stack of interconnected chips. 
     SUMMARY 
     The protection against attacks and, in particular against back side attacks, of a chip contained in a stack of interconnected chip is here considered. 
     Thus, an embodiment provides a device comprising a first chip having a front side and a back side. A second chip is stacked with the first chip and located on the back side of the first chip. A first loop comprises first and second through vias located in the first chip. Each through via has a first end on the front side of the first chip and a second end on the back side of the first chip. A first track that connects the first ends of the first and second through vias is located in the first chip on the front side thereof and a second track that connects the second ends of the first and second through vias is located in the second chip. The first chip comprises a first circuit for detecting an electrical characteristic of the first loop. 
     According to an embodiment, the first chip comprises on its back side first and second connection pads respectively connected to the first and second through vias and the second chip comprises third and fourth connection pads connected to the second track, the first and second pads being respectively soldered to the third and fourth pads of the second chip. 
     According to an embodiment, the detection circuit is capable of detecting at least one of the following electrical characteristics of the first loop a lack of electric continuity of the first loop; a difference between the value of the electric resistance of the first loop and a reference value, and a difference between the time taken by an electric pulse to flow through the first loop and a reference duration. 
     According to an embodiment, the first loop further comprises at least third and fourth through vias located in the first chip, the first loop alternately running through the first chip and through the second chip. 
     According to an embodiment, the first track has a serpentine pattern. 
     According to an embodiment, the second track has a serpentine pattern. 
     According to an embodiment, the second chip has a front side and has a back side facing the first chip, the second track being located on the front side of the second chip, the second chip comprising: fifth and sixth through vias connecting the second track to the first and second through vias; and a second circuit for detecting an electrical characteristic of the first loop. 
     According to an embodiment, the device further comprises at least one second loop comprising seventh and eighth through vias, located in the first chip and each having a first end on the front side of the first chip and a second end on the back side of the first chip; and a third track, connecting the first ends of the seventh and eighth through vias and located in the first chip on the front side thereof; and a fourth track, connecting the second ends of the seventh and eighth through vias and located in the second chip. 
     According to an embodiment, the second chip comprises a third circuit for detecting an electrical characteristic of the second loop. 
     According to an embodiment, the first circuit is capable of detecting an electrical characteristic of the first and second loops. 
     According to an embodiment, the first circuit is capable of detecting at least one of the following electrical characteristics of the first and second loops: an electric continuity between the first loop and the second loop; and a difference between the electric resistance of the first loop and that of the second loop. 
     According to an embodiment, the first circuit is capable of triggering the implementation of countermeasures intended to stop an attack of the first chip when said electrical characteristic is detected. 
     The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a simplified cross-section view of an example of a device comprising a stack of electronic chips; 
         FIG. 2  is a simplified cross-section view of an embodiment of a device comprising a stack of electronic chips; 
         FIG. 3  is a perspective diagram illustrating protection elements of a device comprising a stack of electronic chips according to an embodiment; 
         FIG. 4  is a simplified cross-section view of an alternative embodiment of a device comprising a stack of electronic chips; 
         FIG. 5  is a simplified cross-section view of another alternative embodiment of a device comprising a stack of electronic chips; 
         FIG. 6  is a simplified cross-section view of another alternative embodiment of a device comprising a stack of electronic chips; 
         FIG. 7  is a simplified cross-section view of another alternative embodiment of a device comprising a stack of electronic chips; and 
         FIG. 8  is a diagram illustrating an example of an embodiment of a method of controlling a device comprising a stack of electronic chips. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     The same elements have been designated with the same reference numerals in the various drawings and, further, the various drawings are not to scale. For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, the circuits comprised in the chips of the described devices, particularly circuits capable of containing confidential data to be protected, have not been detailed. Further, the described devices comprise detection circuits, the forming of which has not been detailed. The forming of such detection circuits is indeed within the abilities of those skilled in the art based on the functional indications of the present description. 
     In the following description, when reference is made to terms qualifying absolute position, such as terms “high”, “low”, etc. or relative position, such as terms “above”, “under”, “upper”, “lower”, etc., reference is made to the orientation of the concerned element in the concerned drawings, it being understood that, in practice, the described devices may be oriented differently. 
       FIG. 1  is a simplified cross-section view illustrating an example of a device  1  comprising a stack of electronic chips. Device  1  comprises a chip  3 , and a chip  5  located above chip  3 . Chips  3  and  5  each have a front side in the upper portion and a back side in the lower portion. Chip  3  is thus located on the back side of chip  5 . 
     Chip  3  comprises a semiconductor substrate  7 . Substrate  7  comprises, on its upper surface side (or front side), semiconductor elements of components such as transistors or diodes of circuits not shown. Chip  3  further comprises an interconnection layer  8  covering substrate  7  on the upper surface side thereof. Interconnection layer  8  contains, within insulating layers, conductive tracks, not shown, which connect the components of the circuits of chip  3 . Further, chip  3  comprises, on the upper surface of interconnection layer  8 , connection pads  9  electrically connected to the circuits of chip  3  by tracks of layer  8 . 
     Chip  5  comprises a semiconductor substrate  13 . Chip  5  comprises circuits located on its front side, these circuits comprising components formed inside and on top of substrate  13  on the upper surface side of substrate  13 . Chip  5  comprises an interconnection layer  14  covering substrate  13  on its upper surface side (or front side). Interconnection layer  14  contains, within insulating layers, conductive tracks, not shown, which connect the components of the circuits of chip  5 . Chip  5  further comprises through vias  15 . “Through via” here means a conductive through via thoroughly crossing substrate  13 , from the upper surface of the substrate to the lower surface (or back side) of the substrate. Vias  15  each have, on the front side, an end connected to the circuits of chip  5  by tracks of layer  14  and, on the back side, an end connected to a connection pad  17  located on the back side of upper chip  5 . Each connection pad  17  of upper chip  5  is soldered to a connection pad  9  of lower chip  3 . A filler material  18  may be provided between pads  9  and  17  to perform the soldering. Connections between the circuits of chip  3  and those of chip  5  are thus obtained. 
     The case where the circuits of upper chip  5  contain confidential data coveted by a pirate is here considered. In the presence of chip  3  on the back side of chip  5 , the pirate cannot attack the back side of chip  5 . To obtain the coveted data, the pirate should thus first separate pads  9  and  17  to remove chip  3  and access the back side of chip  5 . The pirate can then carry out the attack from the back side of chip  5 . During the attack, the pirate connects chips  5  to a power source to set it to an operating mode. The pirate may further electrically reconnect pads  9  and  17  with conductive wires, to restore the electric connection between the two chips while keeping an access to the back side of chip  5 . 
     It is here desired, in a device comprising a chip stack, to protect a chip against attacks from its back side when the chip has its back side facing another chip of the stack. 
       FIG. 2  is a simplified cross-section view of an embodiment of a device comprising a stack of electronic chips. The device of  FIG. 2  comprises the same elements as device  1  of  FIG. 1 , arranged substantially in the same way. The elements common to the two devices will not be detailed again hereafter. 
     Upper chip  5  of device  20  comprises two additional conductive through vias  30 A and  30 B. Each of vias  30 A and  30 B has an end, respectively  32 A,  32 B, located on the front side of chip  5 , and another end, respectively  34 A,  34 B, located on the back side of chip  5 . Upper ends  32 A and  32 B of vias  30 A and  30 B are electrically connected together by a conductive track  36  located in interconnection layer  14  of chip  5 . Lower ends  34 A and  34 B of vias  30 A and  30 B are electrically connected together by a conductive track  38  located in interconnection layer  8  of lower chip  3 . In the shown example, upper chip  5  comprises two additional connection pads  17 A and  17 B located on the back side of upper chip  5  and respectively connected to ends  34 A and  34 B of vias  30 A and  30 B. Further, lower chip  3  comprises two additional connection pads  9 A and  9 B located on the front side of chip  3  and respectively connected to a first and to a second end of track  38 , pads  17 A and  17 B being respectively soldered to pads  9 A and  9 B. The device thus comprises a conductive loop  39  comprising through vias  30 A and  30 B series-connected by tracks  36  and  38 . 
     Upper chip  5  further comprises a detection circuit  40  configured to monitor an electrical characteristic of loop  39 , for example, a lack of electric continuity of loop  39 . 
     In normal operation, the presence of lower chip  3  on the back side of upper chip  5  prevents the pirate from accessing the back side of chip  5  to carry out an attack. Loop  39  is intact, and circuit  40  detects no attack. 
     During an attack attempt aiming at obtaining confidential data from upper chip  5 , the pirate removes lower chip  3  to access the back side of chip  5 . To achieve this, the pirate separates connection pads  17 ,  17 A,  17 B of chip  5  from connection pads  9 ,  9 A,  9 B of chip  3 . Due to the fact that part of loop  39  is comprised within lower chip  3 , loop  39  is broken. When chip  5  is set back to the operating mode by the pirate to analyze its operation, the interruption of loop  39  is detected by circuit  40 , which then emits an alert signal A. After the generation of the alert signal in chip  5 , countermeasures are taken to stop the attack, for example, by destroying the confidential data or by stopping the operation of the circuits of chip  5 . 
     Chip  5  of device  20  is thus protected against attacks from its back side. 
     As an example, lower chip  3  has lateral dimensions greater than or equal to those of upper chip  5  and the entire back side of chip  5  faces chip  3 . As a variation, chip  3  is located opposite a portion only of the back side of chip  5 , corresponding to the critical circuits to be protected of chip  5 . 
     As an example, to be able to detect a discontinuity of loop  39 , detection circuit  40  is placed in series with a conductive portion of loop  39  for which an electrical characteristic is desired to be detected. In other words, circuit  40  is comprised within loop  39 . As an example, detection circuit  40  is located between nodes  42  and  44  located on track  36  to interrupt track  36 . As a variation, the detection circuit is located between track  36  and end  32 A of via  30 A or between track  36  and end  32 B of via  30 B. 
     Detection circuit  40  is then configured to detect an electrical characteristic of the conductive portion of loop  39  located outside of detection circuit  40 . As a variation, rather than monitoring the electric continuity of loop  39 , detection circuit  40  may be capable of monitoring one or a plurality of other electrical characteristics of the loop  39 , for example, of comparing the value of the electric resistance of loop  39  between nodes  42  and  44  with a reference value, or also of comparing with a reference duration the time taken by an electric pulse emitted by circuit  40  to flow through the loop. An advantage of such variations is that they enable to detect that chips  3  and  5  have been reconnected by conductive wires after having been separated, which cannot be detected by a simple verification of the electric continuity of loop  39 . 
       FIG. 3  is a perspective diagram illustrating in further detail an embodiment of loop  39  of the device of  FIG. 2 . Only tracks  36  and  38 , vias  30 A and  30 B, and circuit  40  have been shown in  FIG. 3 . Interconnection layers  8  and  14  have been schematized by two parallel planes. 
     As an example, track  36  of upper layer  5  has in top view the shape of a serpentine arranged in a plane substantially parallel to the upper surface of the chip. The serpentine may be arranged at a metallization level of the chip located above that of the chip circuit interconnection tracks. As an example, the critical circuits to be protected of chip  5  are partly or totally arranged in an area of the chip having the serpentine pattern extending therein, in top view. As an example, the critical circuits are partly or totally arranged in an area of the chip where each point is located in top view between two portions of track  36  separated by a distance shorter than 5 μm, preferably shorter than 2 μm. 
     An advantage of this layout of track  36  is that it enables to further protect chip  5  against a possible attack from its front side. Indeed, if a pirate intended to access the components of the critical circuits of chip  5  through interconnection layer  14 , this would inevitably interrupt track  36 , and circuit  40  would detect the attack. Upper chip  5  is thus advantageously protected by a single circuit  40  both against attacks from its front side and against attacks from its back side. The protection of upper chip  5  is thus obtained with a particularly small number of components. 
     In the example of  FIG. 3 , track  38  of lower chip  3  also has in top view the shape of a serpentine, for example, identical or similar to the serpentine shape of track  36 . 
     This enables to protect chip  5 , still by means of the same circuit  40 , against an attack where the pirate would attempt to remove a portion only of lower chip  3 , for example, by etching a through opening into lower chip  3 , to access a portion of the back side of chip  5  without separating the two chips. Due to the serpentine pattern of track  38 , during such an attack attempt, the pirate would inevitably interrupt track  38 , and the attack would thus be detected by circuit  40 . 
     As an example, the critical circuits to be protected of chip  5  are partly or totally arranged opposite an area of chip  3  having the serpentine pattern of track  38  extending therein in top view. To access the components of the critical circuits of chip  5  through the back side thereof, the pirate should remove from chip  3  a portion having lateral dimensions greater than those of the accesses to the components that the pirate would form if he/she intended to attack chip  5  from its front side. Thus, the serpentine pattern of track  38  may be looser than the serpentine pattern of track  36 , of example, the critical circuits of chip  5  are partly or totally arranged in an area having each point located in top view between two portions of track  38  separated by a distance shorter than 50 μm, preferably shorter than 20 μm. As a variation, the serpentine patterns of tracks  38  and  36  are similar, the critical circuits of chip  5  being partly or totally arranged in an area having each point located in top view between two portions of track  38  separated by a distance shorter than 5 μm, preferably shorter than 2 μm. 
       FIG. 4  is a simplified cross-section view of an alternative embodiment of device  20  of  FIG. 2 .  FIG. 4  more particularly illustrates a device  20 A comprising elements similar to those of device  20  of  FIG. 2 , arranged similarly. The elements common to the two devices will not be described again hereafter. In the following, only the differences between devices  20 A and  20  will be highlighted. 
     In device  20 A, loop  39  comprises additional conductive through vias  30 C and  30 D located in chip  5 . Vias  30 C and  30 D each have an end, respectively  32 C and  32 D, on the front side of chip  5 , and the other end, respectively  34 C and  34 D, on the back side of chip  5 . Ends  32 C and  32 D of vias  30 C and  30 D are connected by an additional track  36 A located in interconnection layer  14  of chip  5 . Ends  34 C and  34 D are connected to additional connection pads, respectively  17 C and  17 D, located on the back side of chip  5 . 
     Track  38  of chip  3  has been replaced with tracks  38 A and  38 B located in interconnection layer  8 . Further, chip  3  comprises additional connection pads  9 C and  9 D located on the front side of chip  3 . Track  38 A connects connection pad  9 A to connection pad  9 C, and track  38 B connects connection pad  9 B to connection pad  9 D. Pads  9 C and  9 D are respectively soldered to pads  17 C and  17 D. 
     Loop  39  of device  20 A thus comprises the four vias  30 A,  30 B,  30 C,  30 D series-connected by tracks  36 ,  36 A,  38 A,  38 B. Throughout loop  39 , tracks  36 ,  36 A,  38 A,  38 B are alternately located in upper chip  5  and in lower chip  3 . In other words, the portion of loop  39  for which an electrical characteristic is desired to be monitored alternatively crosses chip  5  and chip  3  a plurality of times. 
     Although, in the shown example, chip  5  comprises four through vias  30 A,  30 B,  30 C,  30 D arranged in chip  5 , other examples are possible where loop  39  comprises an even number greater than four of vias series-connected by tracks alternately located in upper chip  5  and in lower chip  3 . 
     An advantage of the embodiment of  FIG. 4  is that it enables to reinforce the protection of chip  5  against attacks. Indeed, as indicated above, a pirate coveting the confidential data of upper chip  5  might, after having separated chips  3  and  5 , attempt to reconnect them, for example, with conductive wires, to keep the electric connection between the two chips while preserving an access to the back side of upper chip  5 . Thereby, the electric continuity of loop  39  would be restored, which would prevent the detection of the attack by circuit  40 . However, such a reconnection is all the more difficult to perform as the number of vias to be reconnected is high. Device  20 A of  FIG. 4  thus has a reinforced protection level as compared with device  20  of  FIG. 2 . 
       FIG. 5  is a simplified cross-section view of another alternative embodiment of device  20  of  FIG. 2 .  FIG. 5  more particularly illustrates a device  20 B comprising elements similar to those of device  20  of  FIG. 2 , arranged similarly. The elements common to devices  20  and  20 B will not be described again hereafter. In the following, only the differences between devices  20  and  20 B will be highlighted. 
     Device  20 B comprises an additional loop  39 A comprising two additional conductive through vias  30 E and  30 F comprised in upper chip  5 . Vias  30 E and  30 F have, on the front side, respective ends  32 E and  32 F and, on the back side, respective ends  34 E and  34 F. Ends  34 E and  34 F are connected to additional connection pads, respectively  17 E and  17 F, located on the back side of chip  5 . Loop  39 A further comprises an additional track  36 B, located in interconnection layer  14  of upper chip  5  and connecting ends  32 E and  32 F of vias  30 E and  30 F. Loop  39 A further comprises a track  38 C comprised in interconnection layer  8  of lower chip  3 . Track  38 C interconnects additional connection pads  9 E and  9 F arranged on the front side of chip  3  and respectively soldered to pads  17 E and  17 F. 
     Loop  39 A of device  20 B thus comprises, series-connected and in the following order, in upper chip  5 , via  30 E, track  36 B, and via  30 F and, in lower chip  3 , track  38 C. 
     In this example, detection circuit  40  is placed not only in series with a conductive portion of loop  39 , as previously described, but also in series with a conductive portion of loop  39 A. In other words, circuit  40  is comprised within loop  39 A. As an example, detection circuit  40  is located between nodes  42 A and  44 A located on track  36 B so as to interrupt track  36 B. As a variation, the detection circuit is located between track  36 B and end  32 E of via  30 E or between track  36 B and end  32 F of via  30 F. 
     Detection circuit  40  is then configured to detect an electrical characteristic of the conductive portion of loop  39 A located outside of detection circuit  40 . As an example, detection circuit  40  of device  20 B is configured to detect an electrical characteristic of the assembly of the two loops  39  and  39 A, for example, the presence of an electric connection between loops  39  and  39 A or, for example, a difference between the electric resistance of loop  39  between nodes  42  and  44  and the electric resistance of loop  39 A between nodes  42 A and  44 B. 
     An advantage of the embodiment of  FIG. 5  is that it enables to reinforce the protection of chip  5  against attacks. Indeed, if a pirate coveting the confidential data of upper chip  5 , after having separated chips  3  and  5 , attempts to reconnect them, for example with conductive wires, he/she may end up creating an electric connection between the loops, such as a short-circuit, or creating a difference between the electric resistances of the loops. This is detected by circuit  40  when the pirate sets chip  5  back in operation to carry on the attack. 
       FIG. 6  is a simplified cross-section view of another alternative embodiment of device  20  of  FIG. 2 .  FIG. 6  more particularly illustrates a device  20 C comprising elements similar to those of device  20  of  FIG. 2 . The elements common to the two devices will not be described again hereafter. In the following, only the differences between devices  20 C and  20  will be highlighted. 
     Device  20 C differs from device  20  of  FIG. 2  essentially in that, in device  20 C, lower chip  3  has its back side facing the back side of upper chip  5 . In other words, in device  20 C, the front side of chip  3  corresponds to its lower surface, and the back side of chip  3  corresponds to its upper surface. 
     Connection pads  9  of chip  3  have been replaced with connection pads  17 ′ located on its back side. Pads  17 ′ are connected to the circuits of lower chip  3  by conductive through vias  15 ′. The connection pads  17 ′ of lower chip  3  are soldered to the connection pads  17  of upper chip  5 . 
     Chip  3  further comprises two conductive through vias  30 A′ and  30 B′. Through vias  30 A′ and  30 B′ thoroughly cross substrate  7  between the upper surface and the lower surface thereof. 
     Through vias  30 A′ and  30 B′ have, on the front side of chip  3 , respective ends  32 A′ and  32 B′ and, on the back side of chip  3 , respective ends  34 A′ and  34 B′. 
     Ends  32 A′ and  32 B′ are interconnected by an additional track  38 D located in interconnection layer  8  of lower chip  3 . Ends  34 A′ and  34 B′ of vias  30 A′ and  30 B′ are connected to additional connection pads  17 A′ and  17 B′ located on the back side of lower chip  3 . Pads  17 A′ and  17 B′ of lower chip  3  are respectively soldered to pads  17 A and  17 B of upper chip  5 . Device  20 C thus comprises a loop  39  comprising, in series and in the following order, in chip  5 , via  30 A, track  36 , and via  30 B, and, in chip  3 , via  30 B′, track  38 D, and via  30 A′. 
     Lower chip  3  further comprises an additional detection circuit  60  capable of monitoring an electrical characteristic of loop  39 . Circuit  60  is for example identical or similar to circuit  40 . As an example, to detect a discontinuity of loop  39 , detection circuit  60  is placed in series with a conductive portion of loop  39  for which an electrical characteristic is desired to be detected. In other words, circuit  60  is comprised within loop  39 . As an example, detection circuit  60  is located between nodes  62  and  64  located on track  38 D so as to interrupt track  38 D. As a variation, the detection circuit is located between track  38 D and end  32 A′ of via  30 A′ or between track  38 D and end  32 B′ of via  30 B′. 
     As an example, detection circuit  40  comprises a bypass switch  66  coupling nodes  42  and  44 , enabling to connect nodes  42  and  44  to ensure the electric continuity of loop  39  within circuit  40 . Similarly, detection circuit  60  may comprise a bypass switch  68  coupling nodes  62  and  64 , enabling to connect nodes  62  and  64  to ensure the electric continuity of loop  39  within circuit  60 . Each of detection circuits  40  and  60  may have a detection phase during which the detection circuit controls to the non-conductive state its bypass switch, respectively  66  and  68  and monitors an electrical characteristic of the portion of loop  39  located outside of the detection circuit. Circuits  40  and  60  are then configured so that bypass switch  66  of circuit  40  is on during the detection phase of circuit  60 , and so that bypass switch  68  of circuit  60  is on during the detection phase of circuit  40 , the detection phases of circuits  40  and  60  being separate. 
     The case where the circuits of lower chip  3  and those of upper chip  5  contain confidential data is here more particularly considered. 
     In normal operation, the presence of upper chip  5  on the back side of lower chip  3  prevents a pirate from accessing the back side of chip  3  to carry out an attack on chip  3 , and the presence of lower chip  3  on the back side of upper chip  5  prevents a pirate from accessing the back side of chip  5  to carry out an attack on chip  5 . Loop  39  is intact, and none of detection circuits  40  and  60  detects an attack. 
     In an attack attempt aiming at obtaining confidential data present in lower chip  3 , the pirate removes lower chip  5  to access the back side of lower chip  3 . The pirate then attempts operating chip  3 . Loop  39  being interrupted or modified, detection circuit  60  generates an alert signal A1 which triggers countermeasures intended to defeat the attack of lower chip  3 . 
     Similarly, if the pirate attempts to operate chip  5  to analyze the operation thereof, circuit  40  detects the interruption or the modification of loop  39  and triggers countermeasures intended to defeat the attack of chip  5 . 
     Thus, in device  20 C, each of chips  5  and  3  is protected against attacks from its back side. 
       FIG. 7  is a simplified cross-section view of an alternative embodiment of device  20 C of  FIG. 6 .  FIG. 7  more particularly illustrates a device  20 D comprising elements similar to those of device  20 C of  FIG. 6 , arranged similarly. The elements common to the two devices will not be described again hereafter. In the following, only the differences between devices  20 D and  20 C will be highlighted. 
     Device  20 D comprises an additional loop  39 A and a circuit  60 A for detecting an electrical characteristic of loop  39 A. Detection circuit  60 A is for example identical or similar to detection circuit  40 . In the shown example, detection circuit  60  of device  20 C of  FIG. 6  has been omitted. 
     Loop  39 A has a portion located in chip  5 . This portion is similar to the portion of loop  39 A located in chip  5  of device  20 B of  FIG. 5 , that is, loop  39 A comprises two additional through vias  30 E and  30 F, and a track  36 B comprised in interconnection layer  14  connecting ends  32 E and  32 F of vias  30 E and  30 F to respective pads  17 E and  17 F located on the back side of chip  5 . 
     Loop  39 A further comprises two additional through vias  30 E′ and  30 F′ comprised in lower chip  3 . Vias  30 E′ and  30 F′ have, on their front side, respective ends  32 E′ and  32 F′ and, on their back side, ends  34 E′ and  34 F′. Ends  34 E′ and  34 F′ are connected to additional connection pads, respectively  17 E′ and  17 F′, located on the back side of chip  3 . Loop  39 A further comprises an additional track  38 E, located in interconnection layer  8  of upper chip  3  and connecting ends  32 E′ and  32 F′ of vias  30 E′ and  30 F′. Connection pads  17 E′ and  17 F′ are respectively soldered to connection pads  17 E and  17 F. 
     Loop  39 A of device  20 D thus comprises, series-connected and in this order, in chip  5 , via  30 E, track  36 B, and via  30 F and, in chip  3 , via  30 F′, track  38 E, and via  30 E′. 
     In the device  20 D thus obtained, upper chip  5  is protected by loop  39  and by detection circuit  40  against attacks from its back side, and lower chip  3  is protected by loop  39 A and by detection circuit  60 A against attacks from its back side. 
       FIG. 8  is a diagram illustrating an example of an embodiment of a method of controlling a device comprising a stack of electronic chips. This method may be implemented by a detection circuit, such as one of previously-described detection circuits  40 ,  60 , or  60 A, to detect a possible attack of a chip of the device by monitoring the electrical characteristics of a loop such as previously-described loops  39  and  39 A. 
     The method starts at a step  80  (START), which for example corresponds to the connection of the chip comprising the detection circuit to a power source. The method ends either with a step  82  (INIT), or with a step  84  (ERR). Step  82  corresponds to the normal starting of the chip circuits, to perform the functions provided for the chip, for example, by using the confidential data of the chip. Step  82  is only implemented if no attack has been detected. Step  84  corresponds to the implementation of countermeasures intended to counter an attack. 
     After step  8   o , the method comprises a step  86  (CONT) at which the electric continuity of the monitored loop is tested for the detection circuit. If a discontinuity is detected, countermeasure step  84  is implemented. Otherwise, the method carries on with a step  88  (RES). 
     At step  88 , the electric resistance of the monitored loop is compared with a reference value by the detection circuit. The reference value for example corresponds to the resistance of the loop in the absence of an attack. The reference value may correspond to the resistance of another loop, for example, in the embodiment of  FIG. 5 , the monitored loop is loop  39  and the reference value is that of additional loop  39 A. If the difference between the resistance of the loop and the reference value exceeds, in absolute value, a threshold, a countermeasure step  84  is implemented. Otherwise, the method carries on with a step  90  (TIME). 
     At step  9   o , the detection circuit emits an electric pulse in the monitored loop. For example, the detection circuit applies to the monitored loop a rising potential edge between low and high potential values. The detection circuit compares with a reference duration the time taken by the pulse to flow through the monitored loop. The reference duration for example corresponds to the travel time in the absence of an attack. The reference duration may correspond to the time taken by a pulse to flow through another loop, for example, in the embodiment of  FIG. 5 , the monitored loop is loop  39  and the reference duration is that taken by a pulse to flow through additional loop  39 A. If the difference between the travel time and the reference duration is greater, in absolute value, than a threshold, the method proceeds to countermeasure step  84 . Otherwise, the chip starts normally at step  82 . 
     Step  86  enables to detect an attack by a pirate having separated the chips. The pirate may they want to restore the connections between the chips, while maintaining an access to the back side which is desired to be attacked. The new connections modify the loop resistance and/or the time taken by a pulse to flow through the loop. The attack is then detected at step  88  or  90 , and is then countered. An advantage of monitoring a plurality of electrical characteristics of the loop is that a particularly high protection level is thus obtained. 
     As a variation, the number of successively verified electrical characteristics may be different from  3 . Further, the order of the successive verifications of the loop characteristics may be different from what has been described in the example of  FIG. 8 . 
     Specific embodiments have been described. Various alterations, modifications, and improvements will readily occur to those skilled in the art. In particular, although tracks  36  and  38  described in relation with  FIG. 3  have serpentine shapes arranged in a plane located above the level of the circuit interconnection tracks, the serpentine may be partly or entirely located between interconnection tracks. Further, although serpentine shapes have been described, any other adapted track shape is possible. 
     Further, although the described embodiments comprise one or two loops, it is possible to provide more than two loops. 
     Further, although the described embodiments comprise two chips, devices comprising stacks of more than two chips may be provided. 
     Various embodiments with different variations have been described above. It should be noted that those skilled in the art may combine various elements of these various embodiments without showing any inventive step. In particular, tracks  36 A,  36 B,  38 A,  38 B,  38 C,  38 D of loops  39 ,  39 A described in relation with  FIGS. 4 to 7  may have serpentine shapes such as the serpentine shapes of tracks  36  and  38  described in relation with  FIG. 3 . 
     Further, the loops  39 ,  39 A described in relation with  FIGS. 5, 6, and 7  may each comprise more than two pairs of additional vias series-connected by tracks alternately arranged in lower chip  3  and in upper chip  5 , as described in relation with  FIG. 4 . 
     Further, a device comprising a stack of two chips, each having its back side facing the other chip, comprising two loops  39  and  39 A such as described in relation with  FIG. 7 , each of the two chips comprising a circuit for detecting an electrical characteristic of the two loops such as detection circuit  40  described in relation with  FIG. 5 , the two loops being common to the two detection circuits as described in relation with  FIG. 6  for a single common loop, may be provided. 
     Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.