Patent Publication Number: US-4368532-A

Title: Memory checking method

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a method of checking a memory, and more particularly to a method of checking a memory such as a read-only memory (ROM) or a memory for both read and write operations which is used primarily for reading only. 
     It is general practice, in systems that require high reliability to perform a check of read-out information, as by a parity check procedure, in order to prevent the erroneous system operation which can occur if false information is read out of a memory because of a malfunctioning memory element or some other problem. Generally the parity check method proceeds in the following manner. It should first be noted that a parity bit generating circuit and a parity check circuit are required, and that these are provided for in the computer processor. When data is written, the parity generating circuit forms a parity bit for each word which is to be stored in the memory, and causes the parity bit to be stored in the prescribed region of the memory. When the data is read out from the memory, the parity check circuit executes a parity check. Thus when data from the processor is written in the memory, the parity bit generating circuit forms a parity bit in accordance with odd or oven parity, and writes the parity bit in the prescribed region of the memory, which shares the same address as the data. Then, when the processor designates the address and the data is read out, the parity check circuit checks the data and issues an alarm if an error is detected. When this occurs the processor is interrupted by a well known method. In general, instruction words handled by a general micro-processor are composed of eight bits. This means that the number of bits which construct one word is increased to nine, since one bit must be added for the parity bit in the aforesaid parity check. On the other hand, in numerical control apparatus a read-only memory is used to store permanent data, such as a program for numerical control, and the read-only memory is almost always constructed of eight bits. That is to say, the read-only memory is composed of 8×n bits. 
     As is apparent from above-mentioned description, it is necessary to use the read-only memory (8×n bits) and a memory element constructed of 1×n bits, wherein the read-only memory is used for storing the instruction words and the memory element is used for storing the parity bits. However, there is no memory element constructed of 1×n bits available. For this reason, it is inevitable to substitute the read-only memory for the memory element (1×n bits), thereby substantially increasing the amount of hardware required. 
     It is also apparent that only 1/8 of the memory capacity is employed for the parity check, a fact which does not allow the memory to be used to the fullest possible extent. Moreover, in a comparatively small-scale system, the hardware for generating the parity bits and for checking them occupies a significant part of the overall hardware. 
     BRIEF SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a memory checking method capable of affording a great reduction in the memory region which is necessary for the inspection of the memory in the data processing unit which uses the read-only memory as main storage and hence, a method which permits the effective utilization of memory capacity. 
     It is another object of the present invention to provide a memory checking method which does not require a parity bit generating circuit, a parity check circuit and hardware for substituting a read-only memory for a memory constructed of 1×n bits, thereby reducing the amount of hardware required for inspection of the memory. 
     It is still another object of the present invention to provide a memory checking method which enables a memory check through the steps of incorporating, as required, operational control words in a logical block consisting of a plurality of words, executing a predetermined operation in connection with each word in the logical block, and deciding whether or not the result of the operation is the same as a predetermined value. 
     It is a further object of the present invention to provide a memory checking method which enables a memory check through the steps of determining an operational control word in such a manner that the result of an operation attains a specified value, such as all &#34;0&#34;s, when a predetermined operation is executed in connection with each word in a logical block, and then inserting the operational control word into the logical block. 
     Other features and advantages of the invention will be apparent form the following description taken in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a memory checking method by means of the conventional parity check operation; 
     FIG. 2 is a simplified block diagram for illustrating the execution of a memory checking method in accordance with the present invention; 
     FIG. 3A is a diagram illustrating a case in which one block consists of five words, and shows the content of each of the words W 1  through W 4  and the content of an operational control word; 
     FIG. 3B is a diagram illustrating the corresponding relationships between operational steps and the contents of operational register 3c of FIG. 2 at the time of a memory check; 
     FIG. 4A is a diagram illustrating the contents of words W 1  through W 4  in a logical block which consists of five words; 
     FIG. 4B is a diagram illustrating the corresponding relationships between operational steps and the contents of operational register 3c of FIG. 2 when an operational control word is generated; and 
     FIG. 5 is a block diagram of a processor. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The conventional parity check method can be understood from FIG. 1. Illustrated in the Figure are a central processing unit CPU, a parity bit generating circuit PG, a memory MEM, a parity bit memory region PB, and a parity check circuit PC. In this system the central processing unit CPU is provided with the parity bit generating circuit PG and parity check circuit PC. When data is to be written in the memory MEM, the parity bit generating circuit PG generates a parity bit for each word to be stored in the memory MEM, and causes the parity bit to be stored in the parity bit memory region PB. The parity check circuit executes a parity check when data is read out from the memory MEM. More specifically, when data from the central processing unit CPU is written in the memory MEM, the parity bit generating circuit PG generates a parity bit in accordance with odd or even parity, and writes the parity bit in the parity bit memory region PB having the same address as the data. When data is read out from a region of the memory MEM whose address has been designated by the central processing unit CPU, the parity check circuit checks this data and issues an alarm if the data is erroneous. An interrupt signal is then sent to the central processing unit by known means. 
     For even parity in the conventional method, a parity bit is generated and added to one word of data so as to make the total number of &#34;1&#34; bits an even number in that one word of data. Thus, if the number of &#34;1&#34; bits is odd, a parity bit of &#34;1&#34; is generated and added to the word, and if the number of &#34;1&#34; bits is even, a parity bit of &#34;0&#34; is generated and added to the word. Conversely, for odd parity, a parity bit is generated, and added to one word of data, so as to make the total number of &#34;1&#34;  bits an odd number in that word. If the number of &#34;1&#34; bits is odd, a parity of &#34;0&#34; is generated and added to the word, and if the number of &#34;1&#34; bits is even, a parity bit of &#34;1&#34; is generated and added to the word. 
     In contrast, the method of checking a memory in accordance with the present invention is illustrated simply in FIG. 2. The illustrated system includes a read-only memory (ROM) 1 for storing a control program or the like, a random access memory (RAM) 2 which stores data such as machining data for numerical control and which is used primarily for a read-only operation, a processor 3, and a common bus line 4. The read-only memory 1 and random access memory 2 each store at least one logical block made up of a plurality of words. In this case the read-only memory 1 stores logical blocks BL 1  through BL j , and the random access memory 2 stores logical blocks BL i  through BL n . OCW 1  through OCW n  denote operational control words for adjusting the results of operations, as will be described later. These words are inserted in the appropriate logical blocks as necessary. The processor 3 includes an operational unit 3a, operational registers 3b, 3c, and a control unit 3d, and is adapted to execute a predetermined operation on each word that comprises the logical block. Each word is read out from the read-only memory 1 and random access memory 2, and processor 3 checks the memory by determining whether or not the result of an operation is equivalent to a predetermined specified value. The operation referred to above can be an arithmethical operation such as addition or subtraction, a logical operation such as an AND, OR or exclusive-OR operation, or any suitable combination of these operations. The specified value mentioned above can be, for example, all &#34;0&#34;s or all &#34;1&#34;s. Accordingly, if operational control words are not present, the result of the operations applied successively to each word in the logical block will not be equivalent to the specified value, such as all &#34;0&#34;s. In such a case, the operational control words OCW 1  through OCW n  would be determined so as to make the result of the operations all &#34;0&#34;s, and the operational control words so determined would then be written in the read-only memory 1 and the random access memory 2 at the same time as the other information. 
     Before a memory checking operation in accordance with the invention is described, it will be assumed that m 8-bit words are stored in each logical block BL 1  through BL n , that the specified value mentioned above is all &#34;0&#34;s for the eight bits, and that the operation performed by the central processing unit on each read-out word is a logical operation, namely an exclusive-OR operation performed sequentially on the words which constitute each logical block. 
     The processor 3, making use of idle time, first reads out sequentially from the read-only memory 1 each word that forms the logical block BL 1 , and performs a prescribed operation. Thus the first word W 1  is read out from the logical block BL 1  and set in the operational register 3b. Next, the operational unit 3a takes the exclusive OR between corresponding ones of the bits forming the contents of the operational registers 3b, 3c (the content of operational register 3c initially being all &#34;0&#34;s), and the result of this operation is stored in operational register 3c. In this way the first word W 1  is set in the operational register 3c. Next, the second word W 2  is read out and set in operational register 3b in the manner described above, the operational unit 3a takes the exclusive OR between corresponding ones of the bits in the contents of the operational registers 3b, 3c, and the result of the operation is again stored in the operational register 3c. Thereafter, and in the same fashion, the third word W 3 , fourth word W 4  . . . m-th word W m  are read out sequentially, the exclusive-OR operation is executed for corresponding ones of the bits in the operational registers 3b, 3c and the results of the operations are set in the operational register 3c. After the m-th word W m  has been operated upon, a determination is made as to whether the content of operational register 3c is all &#34;0&#34;s; if it is, the content of the register is cleared, the words comprising the next logical block BL 2  are read out sequentially, and each word is processed as described above. If the result of a series of operations is not all &#34;0&#34;s, however, this is determined to represent an error. 
     It should be noted that when the exclusive-OR operation is applied successively to each bit in the words that constitute the logical blocks, as in the above case, the number of corresponding &#34;1&#34; bits in all words W 1  through W m  will be either odd or even in number. If even, the corresponding bit in the result of the operation will be a &#34;0&#34;; if odd, the corresponding bit in the result will be a &#34;1&#34;. 
     The memory checking method of the present invention will be understood more clearly from the drawings of FIG. 3. FIG. 3A is an example in which a block comprises five words, and shows the content of words W 1  through W 4 , and the content of an operational control word OCW i . FIG. 3B illustrates the corresponding relationships between operational steps and the contents of the operational register 3c when an exclusive-OR operation is executed. 
     When the first word W 1  (01001010) is read out and then set in the operational register 3b of FIG. 2, the operational unit 3a takes the exclusive OR between corresponding ones of the bits in the content of operational register 3b and in the content (initially all &#34;0&#34;s) of operational register 3c, and sets the result of the operation i.e., (01001010), in the operational register 3c. This completes Step 1 in FIG. 3B. Next, and in identical fashion, the second word W 2  (10101010) is read out and set in operational register 3b, after which the operational unit 3a takes the exclusive OR between corresponding ones of the bits in the contents of operational registers 3b, 3c (the content of the latter register being the result 01001010 of the preceding operation), and then sets the result of the operation i.e., (11100000), in the operational register 3c. This completes Step 2 in FIG. 3B. This process continues until each word has been read out and each bit of each word has been subjected to the exclusive-OR operation. If the memory is free of errors, the content of the operational register 3c will be all &#34;0&#34;s, as shown in Step 5 of FIG. 3B, after the last word in the logical block has been processed. The memory is erroneous if the content of operational register 3c is not all &#34;0&#34;s. 
     The foregoing description relates to the memory check procedure, but exactly how the operational control words are generated and written takes place as follows. To simplify the description, however, it will be assumed that one logical block consists of m words. 
     When the words W 1 , W 2  . . . constituting each of the logical blocks BL i , BL i+1  . . . BL n  are written in the random access memory 2, the processor 3 takes the exclusive OR between corresponding ones of each bits in each word sequentially. Thus, the first word W 1 , at the same time that it is written in the random access memory, is set in operational register 3b. The processor takes the exclusive-OR between corresponding ones of the bits of the word W 1  in the content of operational register 3b and in the content of operational register 3c (whose content is initially all &#34;0&#34;s), and sets the result in operational register 3c. The second word W 2 , when it is written in the random access memory, is likewise set in the operational register 3b, the processor takes the exclusive-OR between corresponding ones of the bits in this operational register and in operational register 3c, and the result is again set in operational register 3c.  The processing continues in exactly the same manner up to the word W m-1 . After this word has been written in the random access memory and subjected to the exclusive-OR operation with the result of the immediately preceding operation, the writing of data in the logical block BL i  will be complete if the content of the operational register 3c at this time is written in logical block BL i  as the operational control word OCW i . Thereafter, processing each logical block in exactly the same manner sets an operational control word at the end of each block, all of such blocks being written in the random access memory 2. 
     FIG. 4 is useful in describing the generation of operational control words in accordance with the present invention. FIG. 4A shows the contents of four words W 1  through W 4  in a block of five words. FIG. 4B illustrates the corresponding relationships between operational steps and the contents of the operational register 3c when an exclusive-OR operation is executed. 
     The first word W 1  (01001010), at the same time that it is written in the random access memory 2 of FIG. 2, is set in operational register 3b. The processor takes the exclusive-OR between corresponding ones of the bits of the word W 1  in the content of operational register 3b and in the content (initially 00000000, i.e., all &#34;0&#34;s) of operational register 3c, and sets the result, which is 01001010, in the operational register 3c. This completes step 1 in FIG. 4B. Next, and in the same manner, the second word W 2  (10101010) is set in register 3b at the same time that it is written in the random access memory, the processor takes the exclusive-OR between corresponding ones of the bits of the word W 2  in the content of operational register 3b and in the content (now 01001010, i.e., the result of the immediately preceding operation) of operational register 3c, and sets the result, which is 11100000, in the operational register 3c. This completes Step 2 in FIG. 4B. Thereafter, if each word is operated upon in the above manner as it is written into the random access memory, the content of the operational register 3c will be 00111000 after the fourth word W 4  has been processed (Step 4 of FIG. 4B). It is this 8-bit content of the operational register 4B that is written into the random access memory 2 as the operational control word OCW i . 
     A block diagram of a processor for practicing the memory checking method of the present invention is shown in FIG. 5. In addition to the processor, designated at numeral 3, the diagram shows the read-only memory ROM 1, and the random access memory RAM 2. 
     In the processor 3, GREG denotes a general purpose register composed of registers #1 through #n for storing the results of operations, indices and the like. An operational unit ART, corresponding to the operational unit 3a in FIG. 2, executes operations such as addition or subtraction or an exclusive-OR operation on corresponding ones of bits that make up words. ACC is an accumulator for temporarily storing the results of operations. ADR is an address register for storing an address in memory from which data is read out or in which data is written and for delivering the address to the address bus ABUS. PRC is a program counter which stores the address of the next instruction word and ADD is an adder. The adder ADD increments the content of the program counter PRC by one step each time an instruction is executed. The content of the program counter PRC is capable of being changed by the instruction word, such as by a jump instruction. ISR denotes an instruction register which is set by an instruction word read out from ROM 1 or RAM 2, the instruction word arriving on the data bus DBUS. DEC is a decoder which decodes the instruction word and delivers the decoded result to a control circuit COT. The latter circuit produces a control signal CS i  (where i=1 to N) in accordance with the instruction word on the basis of the decoded result from the decoder DEC, and causes a unit, such as the operational unit ART, to execute an operation in accordance with the instruction word. 
     When the computer power source is turned on, the processor 3 is placed under the control of the memory check program being stored in the read-only memory 1 and excecutes a memory check. Specifically, when the power is turned on, the first address in the ROM 1 is set in the program counter PRC. As a result, the data stored at the first address of ROM is read out from the memory and stored temporarily in register #1, which corresponds to the operational register 3b of FIG. 2. Next, operational unit ART takes the exclusive-OR between respective ones of the bits in the content of register #1 and in the content of register #2 (initially all &#34;0&#34;s) which corresponds to the operational register 3c in FIG. 2. The result of this operation is set in register #2, and the content of register #3 (initially all &#34;0&#34;s) is advanced by one. The content of register #3 is then compared with the value m to determine whether or not they are the same. The content of the program counter PRC also is incremented by one by the adder ADD. Thereafter, and in similar fashion, the data at the second, third . . . mth addresses is read out under the control of the memory check program, corresponding ones of the bits are subjected to the exclusive-OR operation, the content of register #3 is incremented by one, and its content is compared with m to determine if they are identical. When they are identical, a determination is made as to whether the content of register #2 is all &#34;0&#34;s). If it is, the content of register #3 is cleared and the abovesaid memory check operation is executed in identical fashion for the next logical block. If the content of register #2 is not all &#34;0&#34;s, an alarm is issued immediately. 
     The entire memory of ROM 1 is checked for errors in the manner described above and, when the check is completed, RAM 2 is subjected to the memory check in the same fashion. The process is completed when each block in ROM 1 and RAM 2 has been checked. 
     The operational control words are generated by starting the operational control word generating program at the time that the data is written in the particular memory. Since the operational control words are incorporated beforehand in the control program of ROM 1, the operational control words are generated only when machining program data is written in RAM 2. In such case the operational control word generating program is stored in ROM 1. 
     In the case described above the memory check was initiated when the power source was turned on, but it is also possible to utilize the idle time of the processor to effect the memory check. If the amount of such idle time is short, then the idle time would be utilized to check the memory block by block in order; a greater amount of idle time would permit the memory to be checked for all the blocks at once. It should be noted, however, that the most preferable method is to confirm the correctness of the memory by performing the memory check at the time that the power source is turned on. 
     It should be apparent from the foregoing that the present invention enables a memory check through a method including the steps of incorporating operational control words as necessary in logical blocks composed of a plurality of words, executing a prescribed operation in connection with each word of the logical blocks, and determining whether or not the result of the operation is the same as a predetermined value. Thus, in accordance with the characterizing feature of the present invention, it is not necessary to add a check bit to each word in a logical block; instead, it suffices merely to prepare a single operational control word for each single logical block, thereby minimizing the regions of the memory that are used exclusively for the memory check, the result being more effective utilization of memory capacity. A separate processor exclusively for the memory check is not necessary. Hence a single processor can be employed for both the memory check and for any other operation, such as a numerical control operation, and the memory check can be conducted using idle time, or just after the power source has been turned on. This results in greater economy without an increase in hardware. 
     While the present invention has been described and illustrated for a case in which each logical block is composed of m words, the number of words in each block need not be the same. Moreover, while the words in each logical block were described as being physically interconnected, this need not always be the case. However, such interconnection is preferable since it is generally required to know the location of the defective memory device whenever a defect in the memory is discovered. In addition, it is advantageous if the size of a logical block is made to agree with the length of address region of the memory device. For example, as a 16K bit (8 bit×2 kW) ROM, a single operational control word will suffice, if the size of the logical block is equal to 2K bytes. 
     It should also be noted that the present invention is not limited to the case described above where it was described that an operational control word is incorporated in each block. It is not necessary to insert a logical control word in a logical block that provides a specified operational result even if the block has not been furnished with an operational control word. Moreover, the present invention is not limited to the above described case where only one operational control word was inserted in each logical block, for example two operational control words may be inserted if desired. 
     As many apparently widely different embodiments of the present invention may be made without departing from the spirit and scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.