Patent Publication Number: US-9405485-B2

Title: Method and apparatus for writing data to a flash memory

Description:
RELATED APPLICATIONS 
     This application is a Continuation Application of U.S. application Ser. No. 13/948,613 filed on Jul. 23, 2013, now U.S. Pat. No. 8,769,218 with an issue date of Jul. 1, 2014, which is a Continuation Application of Ser. No. 13/443,342 filed on Apr. 10, 2012, now U.S. Pat. No. 8,521,971, which is a Continuation Application of U.S. application Ser. No. 13/069,937 filed on Mar. 23, 2011, now U.S. Pat. No. 8,219,764, which is a Continuation Application of U.S. application Ser. No. 11/699,372 filed on Jan. 30, 2007, now U.S. Pat. No. 7,937,522 which claims the right of priority based on Taiwan Application Serial Number 95142873, filed Nov. 20, 2006, the entireties of which are incorporated herein. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The invention relates to memory data management and, in particular, to a data writing method for managing flash memory data. 
     2. Related Art 
     Flash memory is a kind of storage system with the advantages of high access speed and high stability. It is non-volatile memory. That is, once data are stored in the flash memory, it no longer needs power to maintain the data. 
     The structure of the flash memory is in units of blocks. Each block is further divided into pages or sections. If data need to be written into the flash memory, a data writing command is executed to write data in an external buffer into the buffer of the flash memory before writing it into the flash memory. Under the condition that NOP is 1, the data in the memory page can be only written once. In practice, it is likely to occur that data cannot fully occupy a flash memory block or the data storage is not continuous. In these cases, the storage efficiency of the flash memory is reduced. Data defragmentation is employed to solve this problem. However, it requires a lot of time to reorganize data in the flash memory. In particular, once a destination address of the external buffer is assigned to the data, the current structure does not allow one to change the destination address of the data already stored in the flash memory buffer or read the data out of the flash memory buffer. Moreover, such a structure is not suitable for speeding up the data defragmentation. 
     It is therefore desirable to provide a new method for flash memory data management to prevent from spending a lot of time re-organizing data therein because of loose or discontinuous data distribution. The data storage ability of the flash memory is better optimized by reducing the dependence on the external buffer. 
     SUMMARY OF THE INVENTION 
     An objective of the invention is to provide a method for flash memory data management to reduce the amount of time for re-organizing data therein because of loose or discontinuous data distribution, thereby increasing the data storage efficiency thereof. 
     In accord with the above-mentioned objective, the invention provides a method for flash memory data management comprising the steps of: (a) writing data in an external buffer to a flash memory buffer, wherein the data in the flash memory buffer has a destination address; and (b) checking the data stored in the flash memory buffer and using an address changing command to assign a temporary address to the data stored in the flash memory buffer and to write the data into the temporary block when the flash memory buffer is not full. 
     In accord with the above-mentioned objective, the invention provides a method for flash memory data management comprising the steps of: (a) writing data in an external buffer to a flash memory buffer, wherein the data in the flash memory buffer has a destination address; and (b) checking the data stored in the flash memory buffer and using an address changing command when the flash memory buffer is not full, wherein the writing command deletes the data in the flash memory buffer and re-assigns an temporary address to the data; (c) writing the data in the external buffer to the flash memory buffer, wherein the data in the flash memory buffer has a temporary address; and (d) writing the data to a temporary block according to the temporary address. 
     In accord with the above-mentioned objective, the invention provides a method for flash memory data management comprising the steps of: (a) determining an address for transmitting data by a host, wherein the address is an original destination address; (b) waiting for the host to transmit the data to an external buffer; (c) determining whether the data in the external buffer have a first time transmission trait and, when they have the first time transmission trait, determining whether the address assigned by the host is a temporary address and, when the assigned address is a temporary address, reading temporary data in the temporary address to the external buffer, and executing a writing command to re-assign a new destination address; (d) writing the temporary data in the external buffer to a flash memory buffer; and (e) writing the data transmitted from the host in the external buffer to the flash memory buffer, wherein the data in the flash memory buffer have the original or new destination address. 
     If the data in the external buffer do not have the first time transmission trait, then step (e) is executed directly. When the data in the external buffer have the first time transmission trait and the host assigned data transmission address is not the temporary address, an algorithm is executed, followed by step (e). The algorithm includes organizing the data in the external buffer so that they become continuous. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features, aspects and advantages of the invention will become apparent by reference to the following description and accompanying drawings which are given by way of illustration only, and thus are not limitative of the invention, and wherein: 
         FIG. 1  is a schematic view showing the flowchart of an embodiment of the invention; 
         FIG. 2  is a schematic view showing the flowchart of another embodiment of the invention; 
         FIG. 3  is a schematic view showing the flowchart of yet another embodiment of the invention; and 
         FIG. 4  is a schematic view showing the application of the invention according to the flowchart of  FIG. 1  or  FIG. 2 . 
         FIG. 5  is a block diagram of a flash memory system, which may be employed to implement the methods depicted in the flowcharts of  FIGS. 1 and 2 , according to the invention. 
         FIG. 5A  is a block diagram of a flash memory system, which may be employed to implement the method depicted in the flowcharts of  FIG. 3 , according to the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention will be apparent from the following detailed description, which proceeds with reference to the accompanying drawings, wherein the same references relate to the same elements. 
     The disclosed method for flash memory data management writes data into a destination block when a flash memory buffer is full and into a temporary block when it is not full. Another method for flash memory data management according to the invention is for the case when data transmitted from a host have a first time transmission trait and the writing address of the data is a temporary address. In this case, temporary data are read to the external buffer and a writing command is executed to write the temporary data with a destination address to the flash memory buffer. Therefore, the invention can reduce the loose or discontinuous data distribution and the amount of time for re-organizing flash memory data. Moreover, it reduces the dependence on the external buffer to increase the data storage ability thereof. 
     The procedure of an embodiment of the invention is depicted in  FIG. 1 . Steps  102  and  104  takes a data writing command and a data address (e.g., using 5 cycles to transmit data with a destination address), respectively. They are used to write data in an external buffer to a flash memory buffer (step  106 ). The written data has a destination address. Step  108  checks the data stored in the flash memory buffer. When the flash memory buffer is not fill, an address changing command is used (step  110 ) to assign a temporary address to the data in the flash memory buffer (step  112 ). The data are then written to a temporary block of the flash memory (step  114 ). Steps  116  and  118  complete writing the data. 
     With reference to  FIG. 2 , steps  202  and  204  take a data writing command and a data address (e.g., using 5 cycles to transmit data with a destination address), respectively. They are used to write data in an external buffer to a flash memory buffer (step  206 ). The written data has a destination address. Step  208  checks the data stored in the flash memory buffer. When the flash memory buffer is not full, step  210  executes a writing command. The writing command deletes the data inside the flash memory buffer and re-assigns a temporary address to the data in the flash memory buffer (step  212 ). Step  214  re-writes the data in the external buffer to the flash memory buffer. The data in the flash memory buffer has the temporary address. Step  216  writes the data to a temporary block of the flash memory according to the temporary address. Steps  218  and  220  complete writing the data. 
     Please refer to  FIG. 3 . In step  304 , a host determines a location for transmitting data. The location is an original destination address. Step  306  waits for the host to transmit the data to an external buffer. Step  308  determines whether the data in the external buffer has the first time transmission trait. A first time transmission trait means transmission of “new” data, i.e., it is transmitted for the “first time.” That is, a controller determines whether the data transmitted from the host is new or not. If the address corresponding to the data is not the same as other addresses corresponding to data stored in the external buffer, or is not located in the address range of the data stored in the external buffer, the controller determines that the data has a first time transmission trait, i.e., the data is new. Step  310  determines whether the location assigned by the host for transmitting the data is pointed to a temporary address. In step  314 , when the location assigned by the host for transmitting data points to the temporary address, then temporary data in the temporary address are read to the external buffer. Afterwards, steps  316  and  318  execute a writing command for re-assigning an address as a new destination address. Step  320  writes the temporary data in the external buffer to a flash memory buffer. Step  322  writes the data in the external buffer transmitted from the host into the flash memory buffer. The data in the flash memory buffer has the original destination address or the new destination address. 
     More explicitly, in step  308 , when the data in the external buffer do not have the first time transmission trait, step  322  is executed directly to write the data in the external buffer transmitted from the host into the flash memory buffer. Alternatively, if in step  308  the data of the external buffer have the first time transmission trait and the location assigned by the host for data transmission in step  310  does not point to a temporary address, then step  312  executes algorithm to organize the data in the external buffer so that they become continuous. Afterwards, step  322  is performed to write the data in the external buffer transmitted from the host to the flash memory buffer. 
     After the data transmitted from the host to the external buffer are written into the flash memory buffer, step  324  checks whether the action of writing host data to the external buffer has stopped. After it is stopped, step  326  checks whether the flash memory buffer is full. When it is full, step  330  is performed to write data with a destination address to a destination block. The destination address is either the original destination address or the new destination address. If the flash memory buffer is found to be not full in step  326 , step  328  assigns a temporary block to the data. Step  329  writes the data to the temporary block. Step  332  completes writing data to the flash memory. Step  334  finishes the data writing to the flash memory. 
     Step  328  involves the disclosed method of moving data in the yet full flash memory buffer to the temporary block. As shown in  FIG. 1 , when the flash memory buffer is not full, an address changing command is used to assign a temporary address to the data in the flash memory buffer, writing the data to the temporary block. Alternatively, as shown in  FIG. 2 , if the flash memory buffer is not full, a writing command is executed. The writing command deletes the data inside the flash memory buffer and re-assigns a temporary address. The data in the external buffer are then written into the flash memory buffer. The data inside the flash memory buffer have a temporary address and are written into the temporary block accordingly. 
     After writing the data transmitted from the host to the external buffer into the flash memory buffer, step  324  checks whether the action of writing the host data to the external buffer has been stopped. If the writing is not over yet, step  336  checks the data stored in the flash memory buffer. If the flash memory buffer is full, then step  338  writes the data according to their destination address to a destination block. Step  340  completes writing the data to the destination block. In step  342 , the flash memory executes a writing command. Step  344  accumulates the destination address (e.g., accumulating the previous writing address). Afterwards, the procedure goes to step  306 , followed by the above-mentioned steps. The destination address is either the original destination address of the new destination address. 
     When the data are still being transmitted from the host to the external buffer, step  336  checks the data stored in the flash memory buffer. If the flash memory buffer is not full, the procedure goes to step  322  to write the data transmitted from the host to the external buffer into the flash memory buffer. 
     As shown in flowchart  400  of  FIG. 4 , a host determines a location for transmitting data (e.g. a continuous series of data) in step  404 . The location is a destination address. Step  406  waits for the host to transmit the data to an external buffer. Step  408  determines whether the data in the external buffer have a first time transmission trait. If the data have the first time transmission trait, step  410  executes a head data process to simplify subsequent data accesses. Step  412  writes the data of the external buffer to a flash memory buffer. The data in the flash memory buffer has a destination address. 
     After the host transmits the data to the external buffer, the procedure determines whether the data have the first time transmission trait. If the data do not have the first time transmission trait, step  412  is directly performed to write the data in the external buffer into the flash memory buffer. 
     Step  414  checks whether the action of writing the host data to the external buffer is over. If it is not over, then step  426  checks the data stored in the flash memory buffer. Once the flash memory buffer is full, step  428  writes the data according to the destination address to a destination block. Step  430  completes writing the data to the destination block. In step  432 , the flash memory executes a writing command. Step  434  accumulates the destination address (e.g., accumulating the previous writing address). Afterwards, the procedure goes back to step  406 , followed by the above-mentioned steps. 
     When the data are still being written to the external buffer and the flash memory buffer is not full in step  426 , the procedure goes back to step  406  to continue the above-mentioned steps. 
     Step  414  checks whether the action of writing the host data to the external buffer is over. When it is over, step  416  checks the data stored in the flash memory buffer. Once the flash memory buffer is full, step  420  is executed to write the data with the destination address into a destination block. 
     Once the action of writing the host data into the external buffer is over and the flash memory buffer is found to be not full in step  416 , then step  418  assigns a temporary block to the data. The data are written into the temporary block in step  419 . Step  422  completes writing the data into the flash memory. Step  424  finishes the action of writing the data to the flash memory. 
     Step  418  involves the disclosed method of moving the data in the yet full flash memory buffer into the temporary block. As illustrated in  FIG. 1 , when the flash memory buffer is not full, an address changing command is used to assign a temporary address to the data in the flash memory buffer for writing the data to the temporary block. Alternatively, as shown in  FIG. 2 , when the flash memory buffer is not full, a writing command is executed. The writing command deletes the data stored in the flash memory buffer and re-assigns a temporary address. The data in the external buffer are then written to the flash memory buffer. The data in the flash memory buffer has a temporary address and are written into the temporary buffer accordingly. 
       FIG. 5  shows a block diagram of flash memory system  54  of the invention, which is coupled to a host  52 . The flash memory system  54  comprises a controller  542  and a flash memory  544 . The controller  542  comprises an external buffer  5422 , the external buffer  5422  being external to flash memory  544 . The flash memory  544  comprises a buffer  5442  and two blocks called destination block  5444  and temporary block  5446 . Each block comprises a plurality of pages and each page includes four sectors (512 byte/sector). In addition, the destination block  5444  stores four sectors of data L0-L3. 
       FIG. 5  is a block diagram descriptively depicting structure to perform the methods depicted in the flow diagrams of  FIGS. 1 and 2 . The host would like to write 2 sectors of data from logical address 4 to logical address 5 (L4˜L5). The controller  542  receives a write command and data from the host  52  (step  102  and step  104 ), then keeps the data in the external buffer  5422 . When the write command is interpreted, the controller  542  transmits/moves/writes data in the external buffer  5422  to buffer of flash memory  5442  (step  106 ), the written data (L4-L5) has a destination address corresponding to the destination block  5444 . The controller  542  checks the buffer of flash memory  5442  is not full (step  108 ), the controller  542  uses an address changing command (step  110 ) to assign a temporary address to the data in the buffer of flash memory  544  (step  112 ). The data L4-L5 are then written to a temporary block  5446  of the flash memory  544  (step  114 ). Steps  116  and  118  complete writing the data. 
     According to another embodiment of this invention, wherein the structure of  FIG. 5  may be used to implement the method depicted in the flowchart of  FIG. 2 , the host would like to write two sectors of data from logical address 4 to logical address 5 (L4-L5). The controller  542  receives a write command and data from the host  52  (step  202  and step  204 ), then keeps the data in the external buffer  5422 . When the write command is interpreted, the controller  542  transmits/moves/writes data in the external buffer  5422  to buffer of flash memory  5442  (step  206 ), the written data (L4-L5) has a destination address corresponding to the destination block  5444 . The controller  542  checks that the buffer of flash memory  5442  is not full (step  208 ) and, if that is the case, the controller  542  resends a writing command (step  210 ). The writing command deletes the data in the buffer of flash memory  5442  and re-assigns a temporary address corresponding to the temporary block  5446  (step  212 ). Then, the controller re-writes the data L4-L5 in the external buffer  5422  to the buffer of the flash memory  5442  (step  214 ). The data L4-L5 are then written to a temporary block  5446  of the flash memory  544  (step  216 ). Steps  218  and  220  complete writing the data. 
       FIG. 5A  shows a block diagram of flash memory system  54 A of this invention, which is coupled to a host  52 A. The flash memory system  54 A comprises a controller  542 A and a flash memory  544 A. The controller  542 A comprises an external buffer  5422 A, external to flash memory  544 A. The flash memory  544 A comprises a buffer  5442 A and two blocks called destination block  5444 A and temporary block  5446 A. In addition, the destination block  5444 A stores four sectors of data L0-L3 and the temporary block  5446 A stores two sectors of data L4-L5. 
       FIG. 5A  is a block diagram descriptively depicting structure to perform the method depicted in the flow diagram of  FIG. 3 . The host now would like to write two sectors of data from logical address 6 to logical address 7 (L6-L7) (step  302 ). The controller  542 A receives a write command and data from the host  52 A (step  304  and step  306 ), then keeps the data in the external buffer  5422 A. The controller  542 A determines the sector of data L6-L7 is first transmitted (step  308 ) and also the address of data sector L6-L7 is pointed to the temporary block  5446 A (step  310 ). Then, the controller  542 A reads data sector L4-L5 from the temporary block  5446 A to the external buffer  5422 A (step  314 ). Afterwards, the controller  542 A executes a writing command for re-assigning a new destination address corresponding to the destination block  5444 A (steps  316  and  318 ). The controller  542 A transmits/writes/moves the data sector L4-L7 from the external buffer  5422 A to the buffer of flash memory  5442 A (step  320  and step  322 ). After the data sector L6-L7 transmitted from the host  52 A to the external buffer  5422 A are written into the buffer of flash memory  5442 A, the controller  542 A checks whether the action of host  52 A has stopped (step  324 ). After it is stopped, the controller  542 A checks whether the buffer of flash memory  5442 A is full (step  326 ). When it is full, the controller  542 A would instruct the flash memory  544 A to program data L4-L7 to the destination address of the destination block  5444 A (step  330 ). When the flash memory  544 A completes programming, it informs the controller  542 A (step  332 ) and then the controller  542 A informs the host  52  that the process is finished. 
     The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.