Patent Publication Number: US-2005128019-A1

Title: Refresh oscillator

Description:
BACKGROUND OF THE INVENTION  
      1. Field of the Invention  
      The present invention relates to a refresh oscillator, and more particularly to a refresh oscillator which can always generate a constant period of signals regardless of variations of a power supply voltage during a self refresh operation for periodically performing a refresh operation in a DRAM.  
      2. Description of the Background Art  
      A self refresh oscillator is used to guarantee a self refresh operation period for repeating a refresh operation in a DRAM after a predetermined time. The self refresh oscillator generates a constant period of signals and determines a self refresh period using the signals.  
       FIG. 1  is a circuit diagram illustrating a conventional refresh oscillator, including a biasing circuit  10  for determining levels of first and second biases BIAS 1  and BIAS 2  by controlling resistance of resisters R 11  to R 15  between diode-coupled PMOS transistor P 11  and NMOS transistor N 11  by using fuses F 11  to F 13 , and an oscillator  20  for controlling an oscillation period by using the first and second biases BIAS 1  and BIAS 2 .  
      In the biasing circuit  10 , the first PMOS transistor P 11  driven according to a potential of a first node Q 11  is diode-coupled between a power supply terminal VDD and the first node Q 11 , the plurality of resisters R 11  to R 15  are coupled in series between the first node Q 11  and a second node Q 12 , and the first NMOS transistor N 11  driven according to a potential of the second node Q 12  is coupled between the second node Q 12  and a ground terminal VSS. Each fuse F 11  to F 13  are coupled in parallel to the respective resisters R 12  to R 14 , and thus the resistance between the first and second nodes Q 11  and Q 12  are determined by cutting the fuses F 11  to F 13 . The potential of the first node Q 11  becomes the first bias BIAS 1  and the potential of the second node Q 12  becomes the second bias BIAS 2 .  
      In addition, the oscillator  20  includes a plurality of inverters I 11  to I 15 . PMOS transistors P 12  to P 16  driven according to the first bias BIAS 1  are coupled between the power supply terminal VDD and pull-up devices of the inverters I 11  to I 15 , respectively, and NMOS transistors N 12  to N 16  driven according to the second bias BIAS 2  are coupled between pull-down devices of the inverters I 11  to  115  and the ground terminal VSS, respectively. The oscillator  20  adjusts an oscillation period by controlling a current necessary for the operations of the inverters I 11  to  115  by using the PMOS transistors P 12  to P 16  and the NMOS transistors N 12  to N 16 . On the other hand, in the inverters I 11  to  115  composing the oscillator  20 , the output of the preceding inverter become the input of the succeeding inverter, and the output of the final inverter becomes both the output of the oscillator  20  and the input of the first inverter.  
      In the conventional refresh oscillator, operation points of the PMOS transistors P 12  to P 16  and the NMOS transistors N 12  to N 16  operated as loads of each inverter I 11  to I 15  are determined according to the levels of the first and second biases BIAS 1  and BIAS 2 . The first and second biases BIAS 1  and BIAS 2  are determined according to drain voltages of the diode-coupled PMOS transistor P 11  and NMOS transistor N 11 . When the resistance is controlled by cutting the fuses F 11  to F 13  to operate the PMOS transistor P 11  and the NMOS transistor N 11  in a linear region, the levels of the first and second biases BIAS 1  and BIAS 2  are controlled. Therefore, the current flowing through the PMOS transistors P 12  to P 16  and the NMOS transistors N 12  to N 16  is controlled, to change the oscillation period. That is, the oscillation period can be trimmed by cutting the fuses F 11  to F 13  coupled in parallel to the resisters R 12  to R 14 .  
      However, when the conventional refresh oscillator is operated in a low power of about 1.6V, such as a DDR 2  or low power DDR, voltage margins excluding operation voltages of the inverters I 11  to I 15  are not greater than threshold voltages of the PMOS transistors P 12  to P 16  and the NMOS transistors N 12  to N 16 . As a result, the PMOS transistors P 12  to P 16  and the NMOS transistors N 12  to N 16  are operated in a cut off region, and thus the existing current is very different from a value of the linear region, to considerably change the oscillation period.  
      In addition, the biasing circuit  10  determines the levels of the first and second biases BIAS 1  and BIAS 2  by controlling the resisters R 11  to R 15  between the diode-coupled PMOS transistor P 11  and NMOS transistor N 11  by using the fuses F 11  to F 13 . In case that a level of the power supply voltage VDD is varied, namely, levels of sources in PMOS transistors P 12  to P 16  are varied, due to an operation requiring large power consumption, the levels of the biases are also changed. The resulting levels of the biases change the oscillation period, which causes problems in the operation. Currents flowing to the NMOS transistors and the PMOS transistors are increased or decreased exponentially in accordance with the variation of bias levels due to the variation of power supply voltage, because the PMOS transistors P 12  to P 16  and the NMOS transistors N 12  to N 16  operate linearly. Therefore, the oscillation period varies rapidly.  
     SUMMARY OF THE INVENTION  
      The present invention is achieved to solve the above problems. Accordingly, it is a primary object of the present invention to provide a refresh oscillator which can always generate a constant period of signals by supplying constant biases to an oscillator by applying a constant current by using current mirrors, regardless of power supply voltage variation.  
      Another object of the present invention is to provide a refresh oscillator which can always generate a constant period of signals even in a low power supply voltage.  
      In accordance with an embodiment of the present invention, there is provided a refresh oscillator, comprising: a biasing circuit for generating constant first and second biases regardless of variations of a power supply voltage; and an oscillator for generating refresh signals having a constant period according to the first and second biases.  
      In accordance with another embodiment of the present invention, there is provided a refresh oscillator, comprising: a biasing circuit for generating constant first and second biases regardless of variations of a power supply voltage; a start-up circuit for stabilizing the initial operation of the biasing circuit by applying a predetermined voltage to the biasing circuit; and an oscillator for generating a constant period of refresh signals according to the first and second biases.  
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
      The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein:  
       FIG. 1  is a circuit diagram illustrating a conventional refresh oscillator; and  
       FIG. 2  is a circuit diagram illustrating a refresh oscillator in accordance with a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
      A refresh oscillator in accordance with a preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.  
       FIG. 2  is a circuit diagram illustrating the refresh oscillator in accordance with the present invention.  
      A biasing circuit  100  includes first and second current mirrors  110  and  120 , and determines levels of first and second biases BIAS 1  and BIAS 2 . The first current mirror  110  includes four diode connected PMOS transistors P 201  to P 204 , therefore, the four PMOS transistors P 201  to  204  are operated in saturation region if a voltage between a drain and a source of each PMOS transistor P 201  to P 204  is higher than a threshold voltage.  
      The second current mirror  120  includes first and second NMOS transistors N 201  and N 202  that are operated in a saturation region. Accordingly, the first and second biases BIAS 1  and BIASI 2  maintain a constant level regardless of variations of a power supply voltage VDD. The first and third PMOS transistors P 201  and P 203  are coupled in series between a power supply terminal VDD and a first node Q 201 , and the second and fourth PMOS transistors P 202  and P 204  are coupled in series between the power supply terminal VDD and a second node Q 202 . Gates of the first to fourth PMOS transistors P 201  to P 204  are connected to the first node Q 201 . The first to fourth PMOS transistors P 201  to P 204  are driven according to a potential of the first node Q 201 . The first NMOS transistor N 201  is coupled between the first node Q 201  and a third node Q 203 , and the second NMOS transistor N 202  is coupled between the second node Q 202  and a ground terminal VSS. The first and second NMOS transistors N 201  and N 202  are driven according to a potential of the second node Q 202 . A plurality of resisters R 201  to R 204  are coupled in series between the third node Q 203  and the ground terminal VSS, and each fuse F 201  to F 203  are coupled in parallel to the respective resisters R 201  to R 203 , respectively. The potential of the first node Q 201  is controlled by adjusting the resistance of the resisters R 201  to R 204  by cutting the fuses F 201  to F 203 . In other words, the first bias BIAS 1  level and the second bias BIAS 2  level can be controlled by adjusting resistance between the third node Q 203  and the ground terminal Vss. Here, the potential of the first node Q 201  becomes the first bias BIAS 1 , and the potential of the second node Q 202  becomes the second bias BIAS 2 .  
      A start-up circuit  200  stabilizes the initial operation of the biasing circuit  100 , and includes a fifth PMOS transistor P 205  coupled between the power supply terminal VDD and a fourth node Q 204 , a fourth NMOS transistor N 204  coupled between the fourth node Q 204  and the ground terminal VSS, and a third NMOS transistor N 203  coupled between the power supply terminal VDD and the first node Q 201 . Here, the fifth PMOS transistor P 205 , the third NMOS transistor N 203  and the fourth NMOS transistor N 204  are driven according to a potential of the fourth node Q 204 .  
      An oscillator  300  includes an odd number of inverters  1201  to  1205  driven according to the first and second biases BIAS 1  and BIAS 2 , for outputting consecutive pulses. A plurality of PMOS transistors P 206  to P 210  driven according to the first bias BIAS 1  are coupled between the power supply terminal VDD and pull-up devices of the inverters I 201  to I 205 , respectively, and a plurality of NMOS transistors N 205  to N 209  driven according to the second bias BIAS 2  are coupled between pull-down devices of the inverters I 201  to I 205  and the ground terminal VSS, respectively. The oscillator  300  controls a current necessary for the operations of the inverters  1201  to  1205  by using the PMOS transistors P 206  to P 210  and the NMOS transistors N 205  to N 209 . On the other hand, in the inverters  1201  to  1205  composing the oscillator  300 , the output of the preceding inverter become the input of the succeeding inverter, and the output of the final inverter becomes both the output of the oscillator  300  and the input of the first inverter.  
      In accordance with the present invention, the refresh oscillator generates the first and second biases BIAS 1  and BIAS 2  by using the first and second current mirrors  110  and  120  of the biasing circuit  100 . The first and second PMOS transistors P 201  and P 202  and the third and fourth PMOS transistors P 203  and P 204  which compose the first current mirror  110  are driven in pairs according to the potential of the first node Q 201 . That is, the two PMOS transistors form one pair, to output the constant first bias BIAS 1  regardless of variations of the power supply voltage VDD. In addition, the first and second NMOS transistors N 201  and N 202  composing the second current mirror  120  are driven in a pair according to the potential of the second node Q 202 . On the other hand, the first bias BIAS 1  can be controlled by adjusting the values of the plurality of resisters R 201  to R 204  by cutting the fuses F 201  to F 203 .  
      In regard to variations of the power supply voltage VDD, the levels of the first and second biases BIAS 1  and BIAS 2  are determined to operate the PMOS transistors P 201  to P 204  and the NMOS transistors N 201  and N 202  in the saturation region. The inverters  1201  to  1205  of the oscillator  300  are operated by the same current by the first and second biases BIAS 1  and BIAS 2 , regardless of variations of the power supply voltage VDD. The gate levels are biased through the current mirrors in order to flow constant currents to the PMOS transistors P 206  to P 210  and the NMOS transistors N 205  to N 209 , therefore, an output driving current and an inversion speed of each inverter become constant, and a constant period can be obtained.  
      Because the first and second biases BIAS 1  and BIAS 2  are operated not in the linear region but the saturation region, the refresh oscillator can be operated in a power supply level over a sum of threshold voltages of the PMOS transistors P 206  to P 210  and the NMOS transistors N 205  to N 209 , about 1.4V of low power supply voltage VDD.  
      On the other hand, the operation of the start-up circuit  200  for stabilizing the initial operation of the biasing circuit  100  will now be explained. When the power supply voltage VDD is low and the first bias BIAS 1  is approximate to 0V, if the potential of the fourth node Q 204  is low, the fifth PMOS transistor P 205  is turned on to rise the potential of the fourth node Q 204 . When the potential of the fourth node Q 204  rises, the third and fourth NMOS transistors N 203  and N 204  are turned on to rise the first bias BIAS 2 . However, because the fourth NMOS transistor N 204  is turned on, the potential of the fourth node Q 204  falls. Therefore, the fifth PMOS transistor P 205  is turned on and the third NMOS transistor N 203  is turned off, to drop the first bias BIAS 1 . It is thus possible for the first bias BIAS 1  to maintain a constant potential. Such a constant potential turns on the first to fourth PMOS transistors P 201  to P 204  of the first current mirror  110 .  
      As discussed earlier, in accordance with the present invention, the refresh oscillator generates constant biases by using the current mirrors, regardless of variations of the power supply voltage, and supplies the constant biases to the oscillator by using the start-up circuit for stabilizing the biasing circuit, thereby outputting a constant period of signals. As a result, the refresh oscillator can be applied to the design of all DRAM circuits requiring the self refresh operation.  
      As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalences of such metes and bounds are therefore intended to be embraced by the appended claims.