Patent Publication Number: US-10770964-B1

Title: Overshoot reduction circuit for buck converter

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION 
     This application claims the benefit of priority to Taiwan Patent Application No. 108115439, filed on May 3, 2019. The entire content of the above identified application is incorporated herein by reference. 
     Some references, which may include patents, patent applications and various publications, may be cited and discussed in the description of this disclosure. The citation and/or discussion of such references is provided merely to clarify the description of the present disclosure and is not an admission that any such reference is “prior art” to the disclosure described herein. All references cited and discussed in this specification are incorporated herein by reference in their entireties and to the same extent as if each reference was individually incorporated by reference. 
     FIELD OF THE DISCLOSURE 
     The present disclosure relates to a buck converter, and more particularly to an overshoot reduction circuit for the buck converter. 
     BACKGROUND OF THE DISCLOSURE 
     An electronic device generally includes various components requiring different operating voltages. Therefore, a DC-DC voltage converter is essential for voltage adjustment and stabilization of the electronic device. Based upon different power requirements, various types of DC-DC voltage converters such as a buck converter and a boost converter have been developed. The buck converter can decrease an input DC voltage to a default voltage, and the boost converter can increase an input DC voltage. With advances in circuit technologies, both the buck and boost converters have been adjusted for different system architectures and requirements. 
     SUMMARY OF THE DISCLOSURE 
     In response to the above-referenced technical inadequacies, the present disclosure provides an overshoot reduction circuit for a buck converter. The buck converter includes an upper bridge switch, a lower bridge switch and an operational transconductance amplifier. A first terminal of the upper bridge switch is connected to an input voltage source. A second terminal of the upper bridge switch is connected to a first terminal of the lower bridge switch. A second terminal of the lower bridge switch is grounded. A first input terminal of the operational transconductance amplifier is connected to a first reference voltage source. A second input terminal of the operational transconductance amplifier is connected to a node between the second terminal of the upper bridge switch and the first terminal of the lower bridge switch. The overshoot reduction circuit includes an operational amplifier, a first sampler circuit, a pulse generator circuit, a pulse calculator circuit, a second sampler circuit, a first comparator, a second comparator and a switch driver circuit. The operational amplifier has a first amplification input terminal and a second amplification input terminal. The first amplification input terminal of the operational amplifier is connected to a node between the first terminal of the upper bridge switch and the second terminal of the lower bridge switch to obtain a buck converted signal. An output terminal of the operational amplifier is grounded through a voltage divider circuit. The voltage divider circuit includes a first resistor and a second resistor. The second amplification input terminal of the operational amplifier is connected to a node between the first resistor and the second resistor to obtain a voltage feedback signal. The operational amplifier is configured to output an operation amplified signal according to the buck converted signal and the voltage feedback signal. The first sampler circuit is grounded through a first capacitor and configured to sample a first capacitor voltage signal of the first capacitor according to a lower bridge conducted signal of the lower bridge switch from the buck converter. The pulse generator circuit is configured to output a pulse signal according to the lower bridge conducted signal from the buck converter. The pulse calculator circuit is connected to the first sampler circuit and the pulse generator circuit. The pulse calculator circuit is configured to store and output a first sample compared signal according to the first capacitor voltage signal and the pulse signal. The second sampler circuit is grounded through a second capacitor. The second sampler circuit is configured to sample a second capacitor voltage signal of the second capacitor according to the lower bridge conducted signal of the lower bridge switch from the buck converter. The first comparator has a first comparison input terminal connected to the second sampler circuit and a second comparison input terminal connected to the pulse generator circuit. The first comparator is configured to compare the second capacitor voltage signal received through the first comparison input terminal with the first sample compared signal received through the second comparison input terminal to output a first comparing signal. The second comparator has a third comparison input terminal connected to a second reference voltage source and a fourth comparison input terminal connected to an output terminal of the operational transconductance amplifier. The second comparator receives a reference voltage from the second reference voltage source through the third comparison input terminal and receives an error amplified signal from the operational transconductance amplifier through the fourth comparison input terminal. The second comparator is configured to compare the error amplified signal with the reference voltage to output a second comparing signal. The switch driver circuit is connected to the first comparator, the second comparator, and a control terminal of the lower bridge switch. The switch driver circuit is configured to output a lower bridge switching signal to the lower bridge to control the lower bridge according to the first comparing signal and the second comparing signal. 
     In one aspect, the pulse generator circuit is configured to calculate an average voltage of a voltage of the first capacitor voltage signal and a voltage of the pulse signal, and accordingly output the first sample compared signal to the first comparator. 
     In one aspect, the first comparison input terminal of the first comparator is a non-inverting input terminal, the second comparison input terminal is an inverting input terminal, the third comparison input terminal of the third comparator is a non-inverting input terminal, and the fourth comparison input terminal is an inverting input terminal. When a voltage of the first sample compared signal is higher than a voltage of the second capacitor voltage signal, the first comparator outputs the first comparing signal at a high level to the switch driver circuit. When a voltage of the error amplified signal is higher than a voltage of the second reference voltage source, the second comparator outputs the second comparing signal at a high level to the switch driver circuit. The switch driver circuit turns off the lower bridge according to the first comparing signal at the high level and the second comparing signal at the high level. 
     In one aspect, the overshoot reduction circuit further includes a first switch. The first switch has a control terminal connected to the output terminal of the operational amplifier, a first terminal connected to a common voltage source, and a second terminal connected to the first resistor. 
     In one aspect, the overshoot reduction circuit further includes a second switch. The second switch has a control terminal connected to the output terminal of the operational amplifier, a first terminal connected to a common voltage source, and a second terminal connected to the first capacitor through the first sampler circuit. 
     In one aspect, the overshoot reduction circuit further includes a third switch. The third switch has a control terminal connected to an output terminal of the pulse generator circuit, a first terminal connected to a node between the first sampler circuit and the first capacitor, and a second terminal grounded. 
     In one aspect, the overshoot reduction circuit further includes a fourth switch. The fourth switch has a control terminal connected to the output terminal of the operational amplifier, a first terminal connected to a common voltage source, and a second terminal connected to the second capacitor through the second sampler circuit. 
     In one aspect, the overshoot reduction circuit further includes a fifth switch. The fifth switch has a control terminal connected to an output terminal of the pulse generator circuit, a first terminal connected to a node between the second sampler circuit and the second capacitor, and a second terminal grounded. 
     It should be understood that, when a heavy load unloads to a light load, the common buck converter outputs an overshoot voltage. Under this condition, a conduction time of the lower bridge switch is longer than a time that operates in a normal mode. Therefore, the present disclosure provides the overshoot reduction circuit for the buck converter, which can turn on or off the lower bridge switch of the buck converter, according to a conduction state of the lower bridge switch. It is worth noting that the lower bridge switch of the buck converter is turned off before the output voltage of the buck converter reaches a voltage threshold and the output current reaches a current threshold. As a result, the current flows from the source terminal of the lower bridge switch through the internal diode of the lower bridge switch to the inductor and the capacitor at the output terminal of the buck converter. Therefore, it can effectively prevent the overshoot voltage and the overshoot current from being generated by the buck converter. 
     These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their captions, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure will become more fully understood from the following detailed description and accompanying drawings. 
         FIG. 1  is a circuit layout diagram of an overshoot reduction circuit for a buck converter according to an embodiment of the present disclosure. 
         FIG. 2A  is a circuit layout diagram of a buck converter according to an embodiment of the present disclosure. 
         FIG. 2B  is a circuit layout diagram of an overshoot reduction circuit for a buck converter according to an embodiment of the present disclosure. 
         FIG. 3A  is a signal waveform diagram of an output current and an inductor current of the buck converter under condition of a constant output current according to an embodiment of the present disclosure. 
         FIG. 3B  is a signal waveform diagram of an upper bridge switching signal and a lower bridge switching signal of the buck converter under conditions of a constant output current and a constant conduction time according to the embodiment of the present disclosure. 
         FIG. 3C  is a signal waveform diagram of an output current, an inductor current, an upper bridge switching signal, a lower bridge switching signal and an output voltage of the buck converter during a transition from a heavy load to a light load according to the embodiment of the present disclosure. 
         FIG. 4A  is a signal waveform diagram of an inductor current of the buck converter according to an embodiment of the present disclosure. 
         FIG. 4B  is a signal waveform diagram of an output voltage of the buck converter according to the embodiment of the present disclosure. 
         FIG. 4C  is a signal waveform diagram of a lower bridge switching signal of the buck converter according to the embodiment of the present disclosure. 
         FIG. 4D  is a signal waveform diagram of a first pulse signal of a pulse generator circuit of the overshoot reduction circuit for the buck converter according to the embodiment of the present disclosure. 
         FIG. 4E  is a signal waveform diagram of a first capacitor voltage signal of a first sampler circuit of the overshoot reduction circuit for the buck converter according to the embodiment of the present disclosure. 
         FIG. 4F  is a signal waveform diagram of a second capacitor voltage signal of a second sampler circuit, a first sample compared signal of a pulse generator circuit and a second pulse signal of the pulse generator circuit of the overshoot reduction circuit for the buck converter according to the embodiment of the present disclosure. 
         FIG. 5A  is a signal waveform diagram of the inductor current of the buck converter according to the embodiment of the present disclosure. 
         FIG. 5B  is a signal waveform diagram of the output voltage of the buck converter according to the embodiment of the present disclosure. 
         FIG. 5C  is a signal waveform diagram of the lower bridge switching signal of the buck converter according to the embodiment of the present disclosure. 
         FIG. 5D  is a signal waveform diagram of the first pulse signal of the pulse generator circuit of the overshoot reduction circuit for the buck converter according to the embodiment of the present disclosure. 
         FIG. 5E  is a signal waveform diagram of the first capacitor voltage signal of the first sampler circuit of the overshoot reduction circuit for the buck converter according to the embodiment of the present disclosure. 
         FIG. 5F  is a signal waveform diagram of the second capacitor voltage signal of the second sampler circuit, the first sample compared signal of the pulse generator circuit and the second pulse signal of the pulse generator circuit of the overshoot reduction circuit for the buck converter according to the embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS 
     The present disclosure is more particularly described in the following examples that are intended as illustrative only since numerous modifications and variations therein will be apparent to those skilled in the art. Like numbers in the drawings indicate like components throughout the views. As used in the description herein and throughout the claims that follow, unless the context clearly dictates otherwise, the meaning of “a”, “an”, and “the” includes plural reference, and the meaning of “in” includes “in” and “on”. Titles or subtitles can be used herein for the convenience of a reader, which shall have no influence on the scope of the present disclosure. 
     The terms used herein generally have their ordinary meanings in the art. In the case of conflict, the present document, including any definitions given herein, will prevail. The same thing can be expressed in more than one way. Alternative language and synonyms can be used for any term(s) discussed herein, and no special significance is to be placed upon whether a term is elaborated or discussed herein. A recital of one or more synonyms does not exclude the use of other synonyms. The use of examples anywhere in this specification including examples of any terms is illustrative only, and in no way limits the scope and meaning of the present disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given herein. Numbering terms such as “first”, “second” or “third” can be used to describe various components, signals or the like, which are for distinguishing one component/signal from another one only, and are not intended to, nor should be construed to impose any substantive limitations on the components, signals or the like. 
     Reference is made to  FIGS. 1 and 2A , wherein  FIG. 1  is a circuit layout diagram of an overshoot reduction circuit for a buck converter according to an embodiment of the present disclosure, and  FIG. 2A  is a circuit layout diagram of a buck converter according to an embodiment of the present disclosure. 
     As shown in  FIG. 1 , an overshoot reduction circuit  1000  for the buck converter includes an operational amplifier OPA, a first sampler circuit SAM 1 , a pulse generator circuit PUG, a pulse calculator circuit HDV, a second sampler circuit SAM 2 , a first comparator COM 1 , a first switch M 1 , a second switch M 2 , a third switch M 3 , a fourth switch M 4 , a fifth switch M 5 , a second comparator COM 2 , and a switch driver circuit LD. The overshoot reduction circuit  1000  shown in  FIG. 1  is configured to turn on or off a lower bridge switch LG of a buck converter  2000  shown in  FIG. 2A . 
     The operational amplifier OPA has a first amplification input terminal and a second amplification input terminal. The first amplification input terminal such as a non-inverting input terminal of the operational amplifier OPA shown in  FIG. 1  is connected to the buck converter  2000  shown in  FIG. 2A . 
     As shown in  FIG. 2A , the buck converter  2000  includes an upper bridge switch HG and the lower bridge switch LG The upper bridge switch HG and the lower bridge switch LG are n-channel depletion mode MOSFETs, but the present disclosure is not limited thereto. The upper bridge switch HG is connected to the lower bridge switch LG 
     The second amplification input terminal of the operational amplifier OPA of the overshoot reduction circuit  1000  is connected to a node between the upper bridge switch HG and the lower bridge switch LG of the buck converter  2000 . That is, the second amplification input terminal of the operational amplifier OPA is connected to an output terminal of the buck converter  2000 . 
     More specifically, the buck converter  2000  further includes an inductor L 1  and a third capacitor C 3 . A first terminal such as a drain terminal of the upper bridge switch HG of the buck converter  2000  is connected to an input voltage source VIN. A second terminal such as a source terminal of the upper bridge switch HG is connected to a first terminal such as a drain terminal of the lower bridge switch LG A second terminal of the lower bridge switch LG is grounded. One terminal of the inductor L 1  is connected to the node between the upper bridge switch HG and the lower bridge switch LG The other terminal of the inductor L 1  is grounded through the third capacitor C 3 . The second amplification input terminal of the operational amplifier OPA is connected to a node between the inductor L 1  and the third capacitor C 3  of the buck converter  2000 . 
     As shown in  FIG. 1 , the second amplification input terminal such as an inverting input terminal of the operational amplifier OPA of the overshoot reduction circuit  1000  is connected to an output terminal of the operational amplifier OPA through a voltage divider circuit. The voltage divider circuit includes a first resistor R 1  and a second resistor R 2 . One terminal of the first resistor R 1  is connected to the output terminal of the operational amplifier OPA. The other terminal of the first resistor R 1  is connected to one terminal of the second resistor R 2 . The other terminal of the second resistor R 2  is grounded. The second amplification input terminal of the operational amplifier OPA is connected to a node between the first resistor R 1  and the second resistor R 2 . 
     A first switch M 1  may be disposed between the output terminal of the operational amplifier OPA and the voltage divider circuit. The first switch M 1  may be a P-channel enhancement mode MOSFET or any other type of transistors, but the present disclosure is not limited thereto. A control terminal such as a gate terminal of the first switch M 1  is connected to the output terminal of the operational amplifier OPA. A first terminal such as a source terminal of the first switch M 1  is connected to a common voltage source VCC. A second terminal such as a drain terminal of the first switch M 1  is connected to the one terminal of the first resistor R 1  of the voltage divider circuit. 
     The first amplification input terminal of the operational amplifier OPA receives a buck converted signal from the node between the upper bridge switch HG and the lower bridge switch LG of the buck converter  2000 . More precisely, the first amplification input terminal of the operational amplifier OPA obtains the buck converted signal from the node between the inductor L 1  and the third capacitor C 3  of the buck converter  2000 . The second amplification input terminal of the operational amplifier OPA obtains a voltage feedback signal from the node between the first resistor R 1  and the second resistor R 2 . The operational amplifier OPA is configured to output an operation amplified signal to the control terminal of the first switch M 1  to control the first switch M 1  according to the buck converted signal and the voltage feedback signal. 
     The operational amplifier OPA generates the operation amplified signal for controlling the first switch M 1  to generate a current, which is calculated by the following equation: I 1 =Vout/R 2 , wherein I 1  represents the current of the first switch M 1 , Vout represents an output voltage VOUT of the buck converter  2000 , and R 2  represents the second resistor R 2  shown in  FIG. 1 . As shown in  FIG. 1 , a current mirror circuit includes the first switch M 1 , the second switch M 2  and the fourth switch M 4 . A current of the second switch M 2  is equal to a current of the first switch M 1 , and a current of the fourth switch M 4  is equal to the current of the first switch M 1 . A first capacitor C 1  is charged by the current of the second switch M 2  within a constant time to obtain a voltage, which is calculated by the following equation: I 2 *T=C 1 V, wherein I 1  represents the current of the first switch M 1 , Vout represents an output voltage of the buck converter  2000 ,  12  represents the current flowing from the second switch M 2  to the first capacitor C 1 , T represents a time within which the first capacitor C 1  is charged by the current of the second switch M 2 , C 1  represents a capacitance of the first capacitor C 1 , and V represents the voltage of the first capacitor C 1 . In addition, a second capacitor C 2  is charged by the current of the fourth switch M 4  within a constant time to obtain a voltage, which is calculated by the following equation: I 4 *T=C 2 V, wherein I 4  represents a current flowing from the fourth switch M 4  to the second capacitor C 2 , T represents a time within which the second capacitor C 2  is charged by the current of the fourth switch M 4 , C 2  represents a capacitance of the second capacitor C 2 , and V represents the voltage of the second capacitor C 2 . 
     The second switch M 2  and the fourth switch M 4  may be P-channel enhancement mode MOSFETs or other types of transistors, but the present disclosure is not limited thereto. A first terminal such as a source terminal of the second switch M 2  and a first terminal such as a source terminal of the fourth switch M 4  are connected to the common voltage source VCC. A control terminal such as a gate terminal of the second switch M 2  and a control terminal such as a gate terminal of the fourth switch M 4  are connected to the output terminal of the operational amplifier OPA. A second terminal such as a drain terminal of the second switch M 2  is connected to an input terminal of the first sampler circuit SAM 1 . A second terminal such as a drain terminal of the fourth switch M 4  is connected to an input terminal of the second sampler circuit SAM 2 . 
     The third switch M 3  may be an N-channel enhancement mode MOSFET or any other type of transistors, but the present disclosure is not limited thereto. A first terminal of the third switch M 3  is connected to a non-ground terminal of the first capacitor C 1 . A control terminal such as a gate terminal of the third switch M 3  may be connected to an output terminal of the pulse generator circuit PUG The pulse generator circuit PUG may control the third switch M 3 . The first terminal such as a drain terminal of the third switch M 3  is connected to a node between the first sampler circuit SAM 1  and the first capacitor C 1 . A second terminal such as a source terminal of the third switch M 3  is grounded. 
     The first capacitor C 1  is charged by the current flowing through the second switch M 2  to the first capacitor C 1 . The first sampler circuit SAM 1  is grounded through the first capacitor C 1 . The first sampler circuit SAM 1  may be connected to the lower bridge switch LG of the buck converter  2000 . For example, when the lower bridge switch LG is turned on, the first sampler circuit SAM 1  is configured to sample the voltage of the first capacitor C 1  to output a first capacitor voltage signal, according to a lower bridge conducted signal LGON of the lower bridge switch LG from the buck converter  2000 . 
     The pulse generator circuit PUG may be connected to the lower bridge switch LG of the buck converter  2000 . For example, when the lower bridge switch LG is turned off, the pulse generator circuit PUG is configured to output a pulse signal, according to the lower bridge conducted signal LGON from the buck converter  2000 . 
     The pulse calculator circuit HDV is connected to the first sampler circuit SAM 1  and the pulse generator circuit PUG The pulse calculator circuit HDV is configured to store the first capacitor voltage signal from the first sampler circuit SAM 1  and the pulse signal from the pulse generator circuit PUG When the pulse calculator circuit HDV receives the first capacitor voltage signal, the lower bridge switch LG is turned off. Under this condition, the pulse calculator circuit HDV outputs and stores a first sample compared signal Toffavg, according to the first capacitor voltage signal of the first sampler circuit SAM 1  and the pulse signal of the pulse generator circuit PUG For example, the pulse calculator circuit HDV calculates an average voltage of a voltage of the first capacitor voltage signal and a voltage of the pulse signal to output the first sample compared signal Toffavg. After the pulse calculator circuit HDV stores the first sample compared signal Toffavg, the third switch SW 3  is turned on and the first capacitor C 1  discharges. 
     The second sampler circuit SAM 2  is grounded through the second capacitor C 2 . A capacitance of the second capacitor C 2  is N times a capacitance of the first capacitor C 1 , wherein N may be a positive value larger than 1, but the present disclosure is not limited thereto. A first terminal of the fifth switch M 5  is connected to a non-ground terminal of the second capacitor C 2 . 
     The fifth switch M 5  may be an N-channel enhancement mode MOSFET or any other type of transistors, but the present disclosure is not limited thereto. A control terminal such as a gate terminal of the fifth switch M 5  is connected to the output terminal of the pulse generator circuit PUG The pulse generator circuit PUG controls the fifth switch M 5 . A first terminal such as a drain terminal of the fifth switch M 5  is connected to a node between the second sampler circuit SAM 2  and the second capacitor C 2 . A second terminal such as a source terminal of the fifth switch M 5  is grounded. 
     The second sampler circuit SAM 2  is connected to the lower bridge switch LG of the buck converter  2000 . For example, after the first capacitor Cl discharges, the lower bridge switch LG is turned on again to allow the current of the fourth switch M 4  to flow through the second sampler circuit SAM 2  to charge the second capacitor C 2 . Then, the second sampler circuit SAM 2  is configured to sample a voltage of the charged second capacitor C 2  to output a second capacitor voltage signal Toff, according to the lower bridge conducted signal LGON of the lower bridge switch LG from the buck converter  2000 . 
     The first comparator COM 1  has a first comparison input terminal and a second comparison input terminal. The first comparison input terminal such as a non-inverting terminal of the first comparator COM 1  is connected to the second sampler circuit SAM 2 . The second comparison input terminal such as an inverting terminal of the first comparator COM 1  is connected to the pulse calculator circuit HDV. 
     The first comparator COM 1  is configured to compare the second capacitor voltage signal Toff received through the first comparison input terminal with the first sample compared signal Toffavg received through the second comparison input terminal to output a first comparing signal to the lower bridge switch LG from the buck converter  2000  to control the lower bridge switch LG 
     On the other hand, the second comparator COM 2  has a third comparison input terminal and a fourth comparison input terminal. The third comparison input terminal such as a non-inverting terminal of the second comparator COM 2  is connected to a reference voltage source Vth. The fourth comparison input terminal such as an inverting terminal of the second comparator COM 2  is connected to an output terminal of the operational transconductance amplifier of the buck converter  2000 . For example, one input terminal of the operational transconductance amplifier may be connected to the output terminal of the buck converter  2000  and a non-ground terminal of the third capacitor C 3  through a voltage divider circuit. Another input terminal of the operational transconductance amplifier may be connected to the reference voltage source Vth. The operational transconductance amplifier is configured to output an error amplified signal EAO, according to a voltage difference between a divided output voltage of the buck converter  2000  from the voltage divider circuit and a reference voltage of the reference voltage source Vth. 
     The second comparator COM 2  is configured to compare the reference voltage of the reference voltage source Vth received through the third comparison input terminal with the error amplified signal EAO received through the fourth comparison input terminal to output a second comparing signal to the switch driver circuit LD. 
     The switch driver circuit LD may be disposed between the first comparator COM 1  and the buck converter  2000 , and between the second comparator COM 2  and the buck converter  2000 . An input terminal of the switch driver circuit LD is connected to output terminals of the first comparator COM 1  and the second comparator COM 2 . An output terminal of the switch driver circuit LD is connected to a control terminal such as a gate terminal of the lower bridge switch LG of the buck converter  2000 . 
     The switch driver circuit LD may output a lower bridge switching signal LGONF to the control terminal of the lower bridge switch LG to control the lower bridge switch LG, according to the first comparing signal from the first comparator COM 1  and the second comparing signal from the second comparator COM 2 . 
     Reference is made to  FIGS. 1 and 2B , wherein  FIG. 1  is the circuit layout diagram of an overshoot reduction circuit for the buck converter according to the embodiment of the present disclosure, and  FIG. 2B  is a circuit layout diagram of an overshoot reduction circuit for a buck converter according to an embodiment of the present disclosure. 
     As shown in  FIG. 2B , the buck converter includes a control circuit COL, a logic circuit LGC, a driver circuit DRV, a switch circuit including an upper bridge switch UG and the lower bridge switch LG, a capacitor CBOOT, an inductor L, a resistor RESR, a capacitor COUT, the voltage driver circuit including a resistor RFB 1  and a resistor RFB 2 , a current source for providing an output current IOUT, an operational transconductance amplifier OTA and a comparator CMP. 
     As shown in  FIGS. 1 and 2B , the overshoot reduction circuit  1000  is connected to the logic circuit LGC of the buck converter through the switch driver circuit LD. The logic circuit LGC is connected to the driver circuit DRV and the control circuit COL. The driver circuit DRV is connected to control terminals of the upper bridge switch UG and the lower bridge switch LG of the switch circuit. For example, the upper bridge switch UG of the buck converter is a P-channel enhancement mode MOSFET and the lower bridge switch LG is an N-channel enhancement mode MOSFET. The driver circuit DRV of the buck converter is connected to gate terminals of the upper bridge switch UG and the lower bridge switch LG A first terminal such as a drain terminal of the upper bridge switch UG is connected to the input voltage source VIN. A second terminal such as a source terminal of the upper bridge switch UG is connected to the first terminal of such as the drain terminal of the lower bridge switch LG The second terminal such as a source terminal of the lower bridge switch LG is grounded. 
     One terminal of the inductor L is connected to a node between the second terminal of the upper bridge switch UG and the first terminal of the lower bridge switch LG The other terminal of the inductor L is connected to a series circuit of the resistor RESR and the capacitor COUT. One terminal of the resistor RFB 1  of the voltage driver circuit is connected to a node between the inductor L and the series circuit of the resistor RESR and the capacitor COUT. The other terminal of the resistor RFB 1  is connected to one terminal of the resistor RFB 2  of the voltage driver circuit. The other terminal of the resistor RFB 2  is grounded. In addition, the current source for providing the output current IOUT is connected to a node between the other terminal of the inductor L and the one terminal of the resistor RFB 1  of the voltage driver circuit. 
     A first terminal such as a non-inverting terminal of the operational transconductance amplifier OTA of the buck converter is connected to a reference voltage source VREF and receives a reference voltage from the reference voltage source VREF. A second input terminal such as an inverting terminal of the operational transconductance amplifier OTA is connected to a node between the resistor RFB 1  and the resistor RFB 2  of the voltage driver circuit. The output voltage VOUT of the buck converter  2000  at the node between the inductor L and the series circuit of the resistor RESR and the capacitor COUT is divided by the voltage driver circuit to output a feedback voltage VFB to the second terminal of the operational transconductance amplifier OTA. The operational transconductance amplifier OTA is configured to output the error amplified signal EAO according to the reference voltage of the reference voltage source VREF and the feedback voltage VFB. 
     A first comparison input terminal such as an inverting terminal of the comparator CMP of the buck converter is connected to an output terminal of the operational transconductance amplifier OTA, and receives the error amplified signal EAO from the operational transconductance amplifier OTA. A second comparison input terminal such as a non-inverting terminal of the comparator CMP is connected to a ramp circuit and receives a ramp signal VRAMP from the ramp circuit. The comparator CMP is configured to compare the error amplified signal EAO and the ramp signal VRAMP to output a comparing signal to the control circuit COL. The control circuit COL of the voltage converter is connected to an output terminal of the comparator CMP and an input terminal of the logic circuit LGC. The control circuit COL is configured to output a control signal to the logic circuit LGC according to the comparing signal of the comparator CMP. 
     The overshoot reduction circuit  1000  may be connected to the output terminal of the buck converter through the switch driver circuit LD. That is, the overshoot reduction circuit  1000  may be connected to the node between the inductor L and the series circuit of the resistor RESR and the capacitor COUT. The overshoot reduction circuit  1000  may receive the output voltage VOUT of the buck converter. The overshoot reduction circuit  1000  may be connected to the output terminal of the operational transconductance amplifier OTA of the buck converter through the fourth comparison input terminal such as the inverting terminal of the second comparator COM 2 . The overshoot reduction circuit  1000  may receive the error amplified signal EAO from the operational transconductance amplifier OTA. 
     The overshoot reduction circuit  1000  receives the lower bridge conducted signal LGON indicating an operational state of the lower bridge switch LG of the buck converter. The overshoot reduction circuit  1000  may output the lower bridge switching signal LGONF to the logic circuit LGC of the buck converter, according to the lower bridge conducted signal LGON, the error amplified signal EAO and the output voltage VOUT of the buck converter. 
     The logic circuit LGC may output a logic signal to the driver circuit DRV to control the driver circuit DRV to drive the upper bridge switch UG and the lower bridge switch LG of the switch circuit, according to the lower bridge conducted signal LGON from the overshoot reduction circuit  1000  and the control signal from the control circuit COL of the buck converter. It is worth noting that, before the buck converter outputs an overshoot voltage or an overshoot current, the driver circuit DRV turns off the lower bridge switch LG of the buck converter. As a result, a current flows to the output terminal of the buck converter through an internal diode of the lower bridge switch LG, thereby preventing the overshoot voltage or the overshoot current from being output by the buck converter. 
     More specifically, when a load of the buck converter releases energy, the second capacitor voltage signal Toff outputted by the pulse calculator circuit HDV of the overshoot reduction circuit  1000  is higher than the first sample compared signal Toffavg outputted by the second sampler circuit SAM 2 . For example, the second capacitor voltage signal Toff is larger than or equal to N times of the first sample compared signal Toffavg, which is calculated by the following equation: C 2 =C 1 ×N, wherein N depends on a ratio of the capacitance of the first capacitor C 1  and the capacitance of the second capacitor C 2  as shown in  FIG. 1 . As a result, the first comparator COM 1  outputs the first comparing signal at a high level to the switch driver circuit LD. 
     In addition, when the load of the buck converter releases energy, the output voltage VOUT of the buck converter increases such that the error amplified signal EAO outputted by the operational transconductance amplifier OTA is lower than the reference voltage of the reference voltage source Vth. As a result, the second comparator COM 2  outputs the second comparing signal at a high level to the switch driver circuit LD. 
     The switch driver circuit LD of the overshoot reduction circuit  1000  outputs the lower bridge switching signal LGONF at a high level to the logic circuit LGC, according to the first comparing signal at a high level from the first comparator COM 1  and the second comparing signal at a high level from the second comparator COM 2 . The logic circuit LGC outputs the logic signal at a high level to the driver circuit DRV to control the driver circuit DRV to turn off the lower bridge switch LG, according to the lower bridge switching signal LGONF at the high level. 
     Reference is made to  FIGS. 3A, 3B and 3C , wherein  FIG. 3A  is a signal waveform diagram of an output current and an inductor current of the buck converter under condition of a constant output current according to an embodiment of the present disclosure,  FIG. 3B  is a signal waveform diagram of an upper bridge switching signal and a lower bridge switching signal of the buck converter under conditions of a constant output current and a constant conduction time according to the embodiment of the present disclosure, and  FIG. 3C  is a signal waveform diagram of an output current, an inductor current, an upper bridge switching signal, a lower bridge switching signal and an output voltage of the buck converter during a transition from a heavy load to a light load according to the embodiment of the present disclosure. 
     As shown in  FIGS. 3A to 3C , IOUT represents an output current of the buck converter  2000  shown in  FIG. 2A  or the buck converter shown in  FIG. 2B . IL represents a current flowing through the inductor L 1  of the buck converter  2000  shown in  FIG. 2A  or through the inductor L of the buck converter shown in  FIG. 2B . HGS represents the upper bridge switching signal for controlling the upper bridge switch HG of the buck converter  2000  shown in  FIG. 2A  or controlling the upper bridge switch UG of the buck converter shown in  FIG. 2B . LGS represents the lower bridge switching signal for controlling the lower bridge switch LG of the buck converter  2000  shown in  FIG. 2A  or the buck converter shown in  FIG. 2B . VOUT represents the output voltage of the buck converter  2000  shown in  FIG. 2A  or the buck converter shown in  FIG. 2B . 
     When the lower bridge switch LG of the buck converter  2000  is not turned off timely, the inductor current IL is generated as shown by a dotted line in  FIG. 3C . In contrast, when the lower bridge switch LG of the buck converter  2000  is turned off timely, the inductor current IL overshoot as shown by the dotted line can be effectively reduced to generate the inductor current IL as shown by a solid line in  FIG. 3C . 
     When the output voltage VOUT of the buck converter  2000  shown in  FIG. 2A  or the buck converter shown in  FIG. 2B  is higher than a voltage at the node between the first resistor R 1  and the second resistor R 2  of the voltage driver circuit shown in  FIG. 1 , the overshoot reduction circuit  1000  turns off the lower bridge switch LG of the buck converter  2000 . 
     After the lower bridge switch LG of the buck converter  2000  is turned off, a system at the output terminal of the buck converter  2000  unloads. At this time, as shown in  FIG. 2A , the inductor current IL flows through an internal diode D 1  of the lower bridge switch LG to the first terminal such as the drain terminal of the lower bridge switch LG, and then flows to the inductor L 1 . As a result, the output voltage VOUT of the buck converter  2000  does not has an overshoot voltage as shown by the solid line in  FIG. 3C . Conversely, when the lower bridge switch LG is not turned off, the output voltage VOUT of the buck converter  2000  has the overshoot voltage as shown by the dotted line in  FIG. 3C . Therefore, an effect of reducing the overshoot of the output voltage can be effectively achieved by the above processes. 
     Reference is made to  FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 5A, 5B, 5C, 5D, 5E and 5F , wherein  FIGS. 4A and 5A  are signal waveform diagrams of an inductor current of the buck converter according to an embodiment of the present disclosure;  FIGS. 4B and 5B  are signal waveform diagrams of an output voltage of the buck converter according to the embodiment of the present disclosure;  FIGS. 4C and 5C  are signal waveform diagrams of a lower bridge switching signal of the buck converter according to the embodiment of the present disclosure ;  FIGS. 4D and 5D  are signal waveform diagrams of a first pulse signal of a pulse generator circuit of the overshoot reduction circuit for the buck converter according to the embodiment of the present disclosure;  FIGS. 4E and 5E  are signal waveform diagrams of a first capacitor voltage signal of a first sampler circuit of the overshoot reduction circuit for the buck converter according to the embodiment of the present disclosure; and  FIGS. 4F and 5F  are signal waveform diagrams of a second capacitor voltage signal of a second sampler circuit, a first sample compared signal of a pulse generator circuit and a second pulse signal of the pulse generator circuit of the overshoot reduction circuit for the buck converter according to the embodiment of the present disclosure.  FIGS. 4A, 4B, 4C, 4D, 4E and 4F  are partial enlarged diagrams of the signal waveforms of  FIGS. 5A, 5B, 5C, 5D, 5E and 5F , respectively. 
     As shown in  FIGS. 4A and 5A , IL represents the inductor current of the buck converter  2000  shown in  FIG. 2A  or the buck converter shown in  FIG. 2B . As shown in  FIG. 5A , when the buck converter  2000  shown in  FIG. 2A  or the buck converter shown in  FIG. 2B  is turned off by the overshoot reduction circuit  1000  shown in  FIG. 1 , a current of the last wave of the inductor current IL of the inductor L 1  of the buck converter  2000  shown in  FIG. 2A  or the inductor L of the buck converter shown in  FIG. 2B  decreases to almost zero. 
     As shown in  FIGS. 4A and 5B , VOUT represents the output voltage of the buck converter  2000  shown in  FIG. 2A  or the buck converter shown in  FIG. 2B . As shown in  FIG. 5B , when the buck converter  2000  shown in  FIG. 2A  or the buck converter shown in  FIG. 2B  is turned off by the overshoot reduction circuit  1000  shown in  FIG. 1 , the output voltage VOUT of the buck converter  2000  shown in  FIG. 2A  or the buck converter shown in  FIG. 2B  gradually increases such that a constant output current is generated. For example, the constant output current has a current value of about 1.2 amps, which is lower than a current threshold. That is, an overshoot current is not generated. 
     As shown in  FIGS. 4A and 5C , LGON represents the lower bridge conducted signal of the lower bridge switch LG of the buck converter  2000  shown in  FIG. 2A  or the buck converter shown in  FIG. 2B . More specifically, when a waveform of the lower bridge conducted signal LGON reaches a high level, the lower bridge switch LG of the buck converter  2000  shown in  FIG. 2A  or the buck converter shown in  FIG. 2B  is turned on. Conversely, when the waveform of the lower bridge conducted signal LGON falls to a low level from a high level, the lower bridge switch LG of the buck converter  2000  shown in  FIG. 2A  or the buck converter shown in  FIG. 2B  is turned off. 
     When the lower bridge conducted signal LGON shown in  FIGS. 4C and 5C  indicates that the lower bridge switch LG of the buck converter  2000  is turned off, the pulse generator circuit PUG of the overshoot reduction circuit  1000  shown in  FIG. 1  generates a pulse signal PS shown in  FIGS. 4D and 5D . At this time, as shown in  FIGS. 4E and 5E , the first sampler circuit SAM 1  of the overshoot reduction circuit  1000  samples a first capacitor voltage signal NETF of the first capacitor C 1 . 
     The pulse calculator circuit HDV of the overshoot reduction circuit  1000  shown in  FIG. 1  stores the pulse signal PS of the pulse generator circuit PUG and the first capacitor voltage signal NETF of the overshoot reduction circuit  1000 . The pulse calculator circuit HDV then calculates an average value such as a time average of the pulse signal PS and the first capacitor voltage signal NETF, and accordingly outputs the first sample compared signal Toffavg as shown in  FIGS. 4F and 5F . 
     As shown in  FIGS. 4F and 5F , Toff represents the second capacitor voltage signal Toff of the second capacitor C 2  that is sampled by the second sampler circuit SAM 2  of the overshoot reduction circuit  1000 . The first comparator COM 1  of the overshoot reduction circuit  1000  shown in  FIG. 1  compares the first sample compared signal Toffavg with the second capacitor voltage signal Toff to output the lower bridge switching signal LGONF to the lower bridge switch LG of the buck converter  2000  to control the lower bridge switch LG It is worth noting that, the lower bridge switch LG is turned off timely, thereby preventing an overshoot voltage and an overshoot current from being generated by the buck converter  2000 . 
     In summary, the present disclosure provides the overshoot reduction circuit for the buck converter, which can turn on or off the lower bridge switch of the buck converter, according to a conduction state of the lower bridge switch. It is worth noting that the lower bridge switch of the buck converter is turned off before the output voltage of the buck converter reaches a voltage threshold and the output current reaches a current threshold. As a result, the current flows from the source terminal of the lower bridge switch through the internal diode of the lower bridge switch to the inductor and the capacitor at the output terminal of the buck converter. Therefore, it can effectively prevent the overshoot voltage and the overshoot current from being generated by the buck converter. 
     The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. 
     The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others skilled in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present disclosure pertains without departing from its spirit and scope.