Patent Publication Number: US-10311962-B2

Title: Differential sampling circuit

Description:
This application claims the benefit of U.S. provisional application Ser. No. 62/462,405, filed Feb. 23, 2017, the disclosure of which is incorporated by reference herein in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a sampling circuit, and more particularly to a differential sampling circuit. 
     BACKGROUND OF THE INVENTION 
     As known, sampling circuits are applied to many circuitry systems.  FIG. 1  schematically illustrates a conventional analog-to-digital conversion system. As shown in  FIG. 1 , the analog-to-digital conversion system  100  comprises a buffering circuit  110  and an analog-to-digital converter (ADC)  120 . 
     The buffering circuit  110  is a differential buffering circuit. Moreover, the buffering circuit  110  generates a differential signal pair (vip, vin) to two input terminals of the analog-to-digital converter  120 . The signals vip and vin of the differential signal pair are complementary analog signals. The amplitudes of the signals vip and vin are equal. Moreover, the signals vip and vin have different signs. For example, in case that the first signal vip is +1, the second signal vin is −1. 
     The analog-to-digital converter  120  comprises a differential sampling circuit  122 . The differential sampling circuit  122  comprises switching elements sw 1 , sw 2  and sampling capacitors Ca 1 , Cb 1 . The capacitance values of the sampling capacitors Ca 1  and Cb 1  are equal. 
     A first terminal of the switching element sw 1  is connected with a first input terminal of the analog-to-digital converter  120  so as to receive the first signal vip of the differential signal pair. The sampling capacitor Ca 1  is connected between a second terminal of the switching element sw 1  and a ground terminal. A first terminal of the switching element sw 2  is connected with a second input terminal of the analog-to-digital converter  120  so as to receive the second signal vin of the differential signal pair. The sampling capacitor Cb 1  is connected between a second terminal of the switching element sw 2  and the ground terminal. 
       FIG. 2A  schematically illustrates the operations of the differential sampling circuit of  FIG. 1  during a sampling cycle.  FIG. 2B  schematically illustrates the operations of the differential sampling circuit of  FIG. 1  during a holding cycle. The sampling cycle and the holding cycle are alternate cycles. 
     During the sampling cycle, the switching elements sw 1  and sw 2  are in a close state. Meanwhile, the two input terminals of the analog-to-digital converter  120  are connected with the sampling capacitors Ca 1  and Cb 1 , respectively. Consequently, the voltage +v 1  of the first signal vp 1  and the voltage −v 1  of the second signal vin are stored in the sampling capacitors Ca 1  and Cb 1 , respectively. 
     During the holding cycle, the switching elements sw 1  and sw 2  are in an open state. Meanwhile, the two input terminals of the analog-to-digital converter  120  are disconnected from the sampling capacitors Ca 1  and Cb 1 . Meanwhile, the voltages +v 1  and −v 1  are still stored in the sampling capacitors Ca 1  and Cb 1 , respectively. According to the stored voltages of the sampling capacitors Ca 1  and Cb 1 , a processing circuit of the analog-to-digital converter  120  acquires a difference voltage Δv between the voltages +v 1  and −v 1 . The difference voltage Δv is 2v 1 , i.e., v 1 −(−v 1 )=2v 1 . 
     According to the difference voltage Δv, the processing circuit calculates a digital code. The digital code is used as an output digital code of the analog-to-digital converter  120 . 
     SUMMARY OF THE INVENTION 
     An embodiment of the present invention provides a differential sampling circuit. The differential sampling circuit includes a first switching element, a second switching element, a third switching element, a first sampling capacitor, a fourth switching element, a fifth switching element, a sixth switching element and a second sampling capacitor. A first terminal of the first switching element receives a first signal of a differential signal pair. A first terminal of the second switching element receives a second signal of the differential signal pair. A first terminal of the third switching element is connected with a second terminal of the second switching element. A second terminal of the third switching element is connected with a reference voltage terminal. A first terminal of the first sampling capacitor is connected with a second terminal of the first switching element. A second terminal of the first sampling capacitor is connected with the second terminal of the second switching element. A first terminal of the fourth switching element receives the second signal of the differential signal pair. A first terminal of the fifth switching element receives the first signal of the differential signal pair. A first terminal of the sixth switching element is connected with a second terminal of the fifth switching element. A second terminal of the sixth switching element is connected with the reference voltage terminal. A first terminal of the second sampling capacitor is connected with a second terminal of the fourth switching element. A second terminal of the second sampling capacitor is connected with the second terminal of the fifth switching element. 
     Another embodiment of the present invention provides a differential sampling circuit. The differential sampling circuit includes a first switching element, a second switching element, a third switching element, a first sampling capacitor, a second sampling capacitor, a fourth switching element, a fifth switching element, a sixth switching element, a third sampling capacitor and a fourth sampling capacitor. A first terminal of the first switching element receives a first signal of a differential signal pair. A first terminal of the second switching element receives a second signal of the differential signal pair. A first terminal of the third switching element is connected with a second terminal of the second switching element. A second terminal of the third switching element is connected with a reference voltage terminal. A first terminal of the first sampling capacitor is connected with a second terminal of the first switching element. A second terminal of the first sampling capacitor is connected with the second terminal of the second switching element. A first terminal of the second sampling capacitor is connected with the second terminal of the first switching element. A second terminal of the second sampling capacitor is connected with the reference voltage terminal. A first terminal of the fourth switching element receives the second signal of the differential signal pair. A first terminal of the fifth switching element receives the first signal of the differential signal pair. A first terminal of the sixth switching element is connected with a second terminal of the fifth switching element. A second terminal of the sixth switching element is connected with the reference voltage terminal. A first terminal of the third sampling capacitor is connected with a second terminal of the fourth switching element. A second terminal of the third sampling capacitor is connected with the second terminal of the fifth switching element. A first terminal of the fourth sampling capacitor is connected with a second terminal of the fourth switching element. A second terminal of the fourth sampling capacitor is connected with the reference voltage terminal. 
     Numerous objects, features and advantages of the present invention will be readily apparent upon a reading of the following detailed description of embodiments of the present invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
         FIG. 1  (prior art) schematically illustrates a conventional analog-to-digital conversion system; 
         FIG. 2A  (prior art) schematically illustrates the operations of the differential sampling circuit during a sampling cycle; 
         FIG. 2B  (prior art) schematically illustrates the operations of the differential sampling circuit of  FIG. 1  during a holding cycle; 
         FIG. 3  schematically illustrates the circuitry of a differential sampling circuit according to an embodiment of the present invention; 
         FIG. 4A  schematically illustrates the operations of the differential sampling circuit of  FIG. 3  during a sampling cycle; 
         FIG. 4B  schematically illustrates the operations of the differential sampling circuit of  FIG. 3  during a holding cycle; 
         FIG. 5  schematically illustrates the circuitry of a differential sampling circuit according to another embodiment of the present invention; 
         FIG. 6A  schematically illustrates the operations of the differential sampling circuit of  FIG. 5  during a sampling cycle; and 
         FIG. 6B  schematically illustrates the operations of the differential sampling circuit of  FIG. 5  during a holding cycle. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       FIG. 3  schematically illustrates the circuitry of a differential sampling circuit according to an embodiment of the present invention. As shown in  FIG. 3 , the differential sampling circuit  222  comprises switching elements sw 1 -sw 6  and sampling capacitors Ca 1 , Cb 1 . The capacitance values of the sampling capacitors Ca 1  and Cb 1  are equal. 
     A first terminal of the switching element sw 1  receives a first signal vip of a differential signal pair. A first terminal of the switching element sw 2  receives a second signal vin of the differential signal pair. A first terminal of the sampling capacitor Ca 1  is connected with a second terminal of the switching element sw 1 . A second terminal of the sampling capacitor Ca 1  is connected with a second terminal of the switching element sw 2 . A first terminal of the switching element sw 3  is connected with the second terminal of the switching element sw 2 . A second terminal of the switching element sw 3  is connected with a ground terminal. 
     A first terminal of the switching element sw 4  receives the second signal vin of the differential signal pair. A first terminal of the switching element sw 5  receives the first signal vip of the differential signal pair. A first terminal of the sampling capacitor Cb 1  is connected with a second terminal of the switching element sw 4 . A second terminal of the sampling capacitor Cb 1  is connected with a second terminal of the switching element sw 5 . A first terminal of the switching element sw 6  is connected with the second terminal of the switching element sw 5 . A second terminal of the switching element sw 6  is connected with the ground terminal. 
       FIG. 4A  schematically illustrates the operations of the differential sampling circuit of  FIG. 3  during a sampling cycle.  FIG. 4B  schematically illustrates the operations of the differential sampling circuit of  FIG. 3  during a holding cycle. The sampling cycle and the holding cycle are alternate cycles. 
     During the sampling cycle, the switching elements sw 1 , sw 2 , sw 4  and sw 5  are in a close state, but the switching elements sw 3  and sw 6  are in an open state. Consequently, the voltage 2v 1  is stored in the sampling capacitor Ca 1 . The potential at the first terminal of the sampling capacitor Ca 1  is higher than the potential at the second terminal of the sampling capacitor Ca 1 . Similarly, the voltage 2v 1  is stored in the sampling capacitor Cb 1 . The potential at the second terminal of the sampling capacitor Cb 1  is higher than the potential at the first terminal of the sampling capacitor Cb 1 . 
     During the holding cycle, the switching elements sw 1 , sw 2 , sw 4  and sw 5  are in the open state, but the switching elements sw 3  and sw 6  are in the close state. According to the stored voltages of the sampling capacitors Ca 1  and Cb 1 , a processing circuit (not shown) acquires a difference voltage Δv. The difference voltage Δv is 4v 1 , i.e., 2v 1 −(−2v 1 )=4v 1 . 
     The difference voltage Δv obtained by the differential sampling circuit  222  of the present invention is 4v 1 . This difference voltage Δv is two times the difference voltage of the conventional differential sampling circuit. When the differential sampling circuit  222  is applied to the analog-to-digital converter, the signal to noise ratio is improved since the signal is amplified and the noise of converter is keep the same. 
     In some embodiments, the differential sampling circuit  222  is further modified. Consequently, the difference voltage Δv is adjustable. 
       FIG. 5  schematically illustrates the circuitry of a differential sampling circuit according to another embodiment of the present invention. As shown in  FIG. 5 , the differential sampling circuit  322  comprises switching elements sw 1 ˜sw 6  and sampling capacitors Ca 1 , Ca 2 , Cb 1  and Cb 2 . The capacitance values of the sampling capacitors Ca 1  and Cb 1  are equal. The capacitance values of the sampling capacitors Ca 2  and Cb 2  are equal. 
     A first terminal of the switching element sw 1  receives a first signal vip of a differential signal pair. A first terminal of the switching element sw 2  receives a second signal vin of the differential signal pair. A first terminal of the sampling capacitor Ca 1  is connected with a second terminal of the switching element sw 1 . A second terminal of the sampling capacitor Ca 1  is connected with a second terminal of the switching element sw 2 . A first terminal of the sampling capacitor Ca 2  is connected with the second terminal of the switching element sw 1 . A second terminal of the sampling capacitor Ca 2  is connected with a ground terminal. A first terminal of the switching element sw 3  is connected with the second terminal of the switching element sw 2 . A second terminal of the switching element sw 3  is connected with the ground terminal. 
     A first terminal of the switching element sw 4  receives the second signal vin of the differential signal pair. A first terminal of the switching element sw 5  receives the first signal vip of the differential signal pair. A first terminal of the sampling capacitor Cb 1  is connected with a second terminal of the switching element sw 4 . A second terminal of the sampling capacitor Cb 1  is connected with a second terminal of the switching element sw 5 . A first terminal of the sampling capacitor Cb 2  is connected with the second terminal of the switching element sw 4 . A second terminal of the sampling capacitor Cb 2  is connected with the ground terminal. A first terminal of the switching element sw 6  is connected with the second terminal of the switching element sw 5 . A second terminal of the switching element sw 6  is connected with the ground terminal. 
       FIG. 6A  schematically illustrates the operations of the differential sampling circuit of  FIG. 5  during a sampling cycle.  FIG. 6B  schematically illustrates the operations of the differential sampling circuit of  FIG. 5  during a holding cycle. The sampling cycle and the holding cycle are alternate cycles. 
     During the sampling cycle, the switching elements sw 1 , sw 2 , sw 4  and sw 5  are in a close state, but the switching elements sw 3  and sw 6  are in an open state. Consequently, the voltage 2v 1  is stored in the sampling capacitor Ca 1 . The potential at the first terminal of the sampling capacitor Ca 1  is higher than the potential at the second terminal of the sampling capacitor Ca 1 . The voltage v 1  is stored in the sampling capacitor Ca 2 . The potential at the first terminal of the sampling capacitor Ca 2  is higher than the potential at the second terminal of the sampling capacitor Ca 2 . Similarly, the voltage 2v 1  is stored in the sampling capacitor Cb 1 . The potential at the second terminal of the sampling capacitor Cb 1  is higher than the potential at the first terminal of the sampling capacitor Cb 1 . The voltage v 1  is stored in the sampling capacitor Cb 2 . The potential at the second terminal of the sampling capacitor Cb 2  is higher than the potential at the first terminal of the sampling capacitor Cb 2 . 
     During the holding cycle, the switching elements sw 1 , sw 2 , sw 4  and sw 5  are in the open state, but the switching elements sw 3  and sw 6  are in the close state. Since the sampling capacitors Ca 1  and Ca 2  are in parallel with each other, the stored voltage is changed to 
             v   ⁢           ⁢     1   ·       (     1   +       Ca   ⁢           ⁢   1         Ca   ⁢           ⁢   1     +     Ca   ⁢           ⁢   2           )     .             
Similarly, since the sampling capacitors Cb 1  and Cb 2  are in parallel with each other, the stored voltage is changed to
 
     
       
         
           
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     As mentioned above, the capacitance values of the sampling capacitors Ca 1  and Cb 1  are equal, and the capacitance values of the sampling capacitors Ca 2  and Cb 2  are equal. Consequently, the difference voltage Δv is equal to 
     
       
         
           
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     In this embodiment, the ratio of the difference voltage Δv obtained by the differential sampling circuit  322  to the difference voltage Δv obtained by the conventional differential sampling circuit  122  is equal to 
               (     1   +       Cb   ⁢           ⁢   1         Cb   ⁢           ⁢   1     +     Cb   ⁢           ⁢   2           )     ,         
which is defined as an amplifying ratio of the sampled signal of the differential sampling circuit  322 . By adjusting the capacitance values of the sampling capacitors Ca 1  and Ca 2 , the amplifying ratio of the sampled signal is correspondingly changed.
 
     When the differential sampling circuit  322  is applied to an analog-to-digital conversion system, the amplifying ratio of the sampled signal is adjustable according to the capacitance values of the sampling capacitors Ca 1  and Ca 2 . In other words, the gain requirement of the buffering circuit can be reduced. 
     While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.