Patent Publication Number: US-7710807-B2

Title: Sense amplifiers having MOS transistors therein with different threshold voltages and/or that support different threshold voltage biasing

Description:
CROSS-REFERENCE TO PRIORITY APPLICATION AND RELATED APPLICATION 
   This application is a divisional of U.S. application Ser. No. 11/185,351; filed Jul. 20, 2005 now U.S. Pat. No. 7,345,939, which claims priority to Korean Application No. 2004-60977, filed Aug. 2, 2004. The disclosure of U.S. application Ser. No. 11/082,069 is hereby incorporated herein by reference. 

   FIELD OF THE INVENTION 
   The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device, which performs refresh operation and a method of sensing a bit line thereof. 
   BACKGROUND OF THE INVENTION 
   In general, a dynamic memory cell of a dynamic semiconductor memory device includes one transistor and one capacitor to store 1 bit of data. Data of a high level stored in the capacitor may vanish as time goes by. Therefore, in order to keep data, refresh operations should be performed periodically before data of a high level stored in the capacitor is vanished. 
   In the refresh operation of the dynamic semiconductor memory device, if word lines are selected in response to a refresh address, a charge sharing operation is performed between data of a high level stored in a memory cell connected between the selected word lines and a charge of a bit line of the memory cell connected to the selected word line, i.e., a precharge level. Thereafter, a bit line sense amplifier operates to sense and amplify a bit line pair to a power voltage level and a ground voltage level. 
     FIG. 1  is a block diagram illustrating configuration of a conventional semiconductor memory device. A memory cell array  100  includes a conjunction region CJ, a sense amplifier region SA, a sub word line driver region SWD, and a sub memory cell array block SMCA. The sub word line driver region SWD is arranged above and below the sub memory cell array block SMCA, the sense amplifier region SA is arranged on both sides of the sub memory cell array block SMCA, and the conjunction region CJ is arranged at a cross region of the sub word line driver region SWD and the sense amplifier SA.  FIG. 1  shows just a partial configuration of the memory cell array  100 . 
   Word line selecting signals PX 1  and PX 2  are arranged on a left side of the sub memory cell array block SMCA in a direction of crossing the conjunction region CJ and the sense amplifier region SA, and word line selecting signals PX 3  and PX 4  are arranged on a right side of the sub memory cell array block SMCA in a direction of crossing the conjunction region CJ and the sense amplifier region SA. Main word line selecting signals NWE 1 , . . . are arranged in a direction of crossing the sub word line driver region SWD and the sub memory cell array block SMCA, and sub word lines SWD 1  to SWD 4  are arranged in the same direction as the main word line selecting signal NWE 1 , in the sub memory cell array block SMCA. Array bit line pairs (e.g., ABL 1 ,ABL 1 B), are arranged in a perpendicular direction to the sub word lines SWL 1  to SWL 4 , and sense bit line pairs (e.g., SBL 1 ,SBL 1 B), are located between left and right array bit line pairs. 
   A bit line isolation gate ISOG 1  is arranged between each of the left array bit line pairs (e.g., ABL 1 ,ABL 1 B), and each of the sense bit line pairs (e.g., SBL 1 ,SBL 1 B), a bit line isolation gate ISOG 2  is arranged between each of the right array bit line pairs (e.g., ABL 1 ,ABL 1 B), and each of the sense bit line pairs (e.g., SBL 1 ,SBL 1 B), and a precharge circuit PRE 1  is arranged between each of the left array bit line pairs (e.g., ABL 1 ,ABL 1 B). A precharge circuit PRE 2  is arranged between each of the right array bit line pairs (e.g., ABL 1 ,ABL 1 B), a PMOS sense amplifier PSA and an NMOS sense amplifier NSA are arranged between each of the sense amplifier bit line pairs (e.g., SBL 1 ,SBL 1 B), and an I/O gate IOG is arranged between each of the sense amplifier bit line pairs (e.g., SBL 1 ,SBL 1 B), and each of I/O line pair IO 1 ,IO 1 B. Each of the bit line isolation gates ISOG 1  and ISOG 2  includes NMOS transistors N 3  and N 4 , the PMOS sense amplifier includes PMOS transistors P 1  and P 2 , and an NMOS sense amplifier includes NMOS transistors N 1  and N 2 . 
   In  FIG. 1 , a row address of 2-bit least significant bit (“LSB”) is decoded to generate word line selecting signals PX 1  to PX 4 , a row address of the rest bits except the 2-bit LSB is decoded to generate the main word line selecting signals (e.g., NWE 1 ), and each of the word line selecting signals PX 1  to PX 4  and the main word line selecting signals NWE 1  are combined to select the sub word lines SWL 1  to SWL 4 . In the same way, each of the word line selecting signals PX 1  to PX 4  and each of the rest word line selecting signals (not shown) are combined to select corresponding four (4) sub word lines. 
   The memory cells of the sub memory cell array block SMCA includes a memory cell MC 1  to MC 4  which has one transistor N and one capacitor C and the memory cell MC 1  is connected between the sub word line SWL 1  and the inverted bit line BL 1 B, the memory cell MC 2  which is connected between the sub word line SWL 2  and the bit line BL 1 , the memory cell MC 3  which is connected between the sub word line SWL 3  and the bit line BL 1 , and the memory cell MC 4  which is connected between the sub word line SWL 4  and the inverted bit line BL 1 B. The memory cells, which are not shown, are connected and arranged in the same way described above. 
   Functions of the components of the semiconductor memory device of  FIG. 1  are explained below. Each of the precharge circuits PRE 1  and PRE 2  precharge the array bit line pair ABL 1 ,ABL 1 B to a precharge voltage VBL level during precharge operation. Each of the bit line isolation gates ISOG 1  and ISOG 2  is turned on to connect the array bit line pair ABL 1 ,ABL 1 B and the sense bit line pair SBL 1 ,SBL 1 B if the bit line isolation control signals ISO 1  and ISO 2  are applied during the precharge operation, and connects the left array bit line pair ABL 1 ,ABL 1 B and the sense bit line pair SBL 1 ,SBL 1 B if the left sub memory cell array block SMCA is selected and so the bit line isolation control signal ISO 1  of a high voltage level is applied and connects the right array bit line pair ABL 1 ,ABL 1 B and the sense bit line pair SBL 1 ,SBL 1 B if the right sub memory cell array block SMCA is selected and so the bit line isolation control signal ISO 2  of a high voltage level is applied, during read operation, write operation, and refresh operation. The PMOS sense amplifier PSA detects a signal of a low level of the sense bit line SBL 1  or the inverted sense bit line SBL 1 B if a signal LA of a power voltage VCC level is applied and amplifies it to a power voltage VCC level, and the NMOS sense amplifier NSA detects a signal of a high level of the sense bit line SBL 1  or the inverted sense bit line SBL 1 B if a signal LAB of a ground voltage level is applied and amplifies it to a ground voltage level. The I/O gate IOG is turned on in response to a column selecting signal (not shown) to transmit data between the sense bit line pair SBL 1 ,SBL 1 B and the I/ 0  line pair IO 1 ,IO 1 B. 
     FIG. 2  is a view illustrating configuration of a circuit, which generates the signals LA,LAB. The circuit of  FIG. 2  includes a controller  10 , a PMOS transistor P 3 , and an NMOS transistor N 5 . Functions of the components of  FIG. 3  are explained below. The controller  10  generates first and second bit line sense amplifier enable control signals LAPG,LANG of a low level and a high level if an active command ACT or a refresh command REF is applied. The PMOS transistor P 3  generates a signal LA of a power voltage VCC level in response to the first bit line sense amplifier enable control signal LAPG of a low level. The NMOS transistor N 5  generates a signal LAB of a ground voltage VSS level in response to the second bit line sense amplifier enable signal LANG of a high level. 
     FIG. 3  is a timing diagram illustrating the refresh operation of the semiconductor memory device of  FIG. 1 .  FIG. 3  shows operation in case that in state that data of a high level is stored in the memory cell MC 1  and the array bit line pair ABL 1 ,ABL 1 B and the sense bit line pair SBL 1 ,SBL 1 B are precharged to a precharge voltage VBL level, a refresh command REF is applied and so the sub word line SWL 1  is selected. 
   If the sub word line SWL 1  is selected, a level of the sub word line SWL 1  is gradually increased, as predetermined time lapses after the sub word line SWL 1  is selected, the NMOS transistor N of the memory cell MC 1  is turned on, so that a charge sharing operation is performed between a charge of the capacitor C and a precharge level of the inverted array bit line ABL 1 B. At this time, since the bit line isolation gate ISOG 1  is perfectly turned on, the inverted array bit line ABL 1 B and the inverted sense bit line SBL 1 B are changed to the same level. If voltages of the inverted array bit line ABL 1 B and the inverted sense bit line SBL 1 B are increased by a voltage ΔV by the charge sharing operation during a charge sharing operation period T, the first and second bit line sense amplifier enable control signals LA,LAB of a power voltage VCC level and a ground voltage VSS level are generated. Thus, a voltage between a gate and a source of the NMOS transistor N 1  becomes greater than a threshold voltage of the NMOS transistor N 1 , so that the NMOS transistor N 1  is turned on to thereby reduce a voltage of the sense bit line SBL 1 . As a result, a voltage between a gate and a source of the PMOS transistor P 2  becomes greater than a threshold voltage of the PMOS transistor P 2 , so that the PMOS transistor P 2  is turned on to thereby increase a voltage of the inverted sense bit line SBL 1 B. So, the sense bit line SBL 1  is amplified to a ground voltage VSS level, and the inverted sense bit line SBL 1 B is amplified to a power voltage VCC level. 
   Even though not shown, in case that data of a low level is stored in the memory cell MC 1  and the sub word line SWL 1  is selected, the charge sharing operation is performed to reduce a voltage of the inverted sense bit line SBL 1 B by a voltage ΔV. Thereafter, if a signal LA of a power voltage VCC level and a signal LAB of a ground voltage VSS are applied, the PMOS transistor P 1  and the NMOS transistor N 2  are turned on to amplify a voltage of the inverted sense bit line SBL 1 B to a ground voltage level and to amplify a voltage of the sense bit line SBL 1  to a power voltage VCC level. 
   In the bit line sense amplifier of the conventional semiconductor memory device described above, since threshold voltages of the PMOS transistors P 1  and P 2  are identically designed and threshold voltage of the NMOS transistors N 1  and N 2  are identically designed, ability of the PMOS transistor P 1  of sensing data of a low level of the inverted sense bit line SBL 1  is identical to ability of the PMOS transistor P 2  of sensing data of a low level of the sense bit line SBL 1 , and ability of the NMOS transistor N 1  of sensing data of a high level of the inverted sense bit line SBL 1 B is identical to ability of the NMOS transistor N 2  of sensing data of a high level of the sense bit line SBL 1 . 
   In general, a refresh cycle of the refresh operation depends on sensing ability of the bit line sense amplifier and discharging time of data of a high level stored in the memory cell. That is, in order for the bit line sense amplifier to perform the sensing operation, the charge sharing operation is performed during the charge sharing operation period T before data of a high level stored in the memory cell is completely discharged, so that a voltage of the sense bit line (or inverted sense bit line) should be increased by a voltage ΔV from a precharge voltage VBL. The refresh operation for the same word line is performed at an interval of a refresh cycle, and as the refresh cycle is short, power consumption is more increased. The refresh cycle has close correlation with ability of sensing data of a high level of the bit line sense amplifier. If the memory cell is excellent in maintaining data of a high level, the refresh cycle can be set to be long. However, the memory cell has limitations to ability of maintaining data of a high level, and since the refresh cycle is set by assuming a case that ability of the memory cell of maintaining data of a high level is worst when the semiconductor memory device is designed, there is a limitation to increasing the refresh cycle. 
   However, if the bit line sense amplifier of the semiconductor memory device has excellent sensing ability for data of a high level, that is, the bit line sense amplifier is designed to sense very small level variation of a voltage of the sense bit line (or inverted sense bit line), the refresh cycle can be set to be long. 
   SUMMARY OF THE INVENTION 
   Embodiments of the invention include sense amplifiers configured to sense and amplify relatively small differential signals established across a pair of differential sense bit lines. According to these embodiments, a sense amplifier is provided with multiple MOS sense amplifiers therein. These MOS sense amplifiers include a first MOS sense amplifier having a first pair of MOS transistors of first conductivity type therein electrically coupled across a pair of sense bit lines. This first pair of MOS transistors of first conductivity type can be configured to have different threshold voltages so that enhanced sensing of relatively small differential voltages on the sense bit lines can be achieved. Alternatively, the first pair of MOS transistors may support different threshold voltage biasing. This different threshold voltage biasing may be achieved by independently controlling the level at which the substrate terminals of the MOS transistors are biased during a sense and amplify operation. These MOS sense amplifiers may also include a second MOS sense amplifier having a first pair of MOS transistors of second conductivity type therein electrically coupled across the pair of sense bit lines. In some of these embodiments, the first MOS sense amplifier is an AMOS sense amplifier and the second MOS sense amplifier is a PMOS sense amplifier or vice versa. 
   According to still further embodiments of the invention, the first MOS sense amplifier also includes a second pair of MOS transistors of first conductivity type electrically coupled across the pair of sense bit lines. This second pair of MOS transistors is configured to have different threshold voltages as well. Similarly, the first pair of MOS transistors of second conductivity type can be configured to have different threshold voltages or support different threshold voltage biasing. 
   Additional embodiments of the invention include a first MOS sense amplifier having a pair of MOS transistors of first conductivity type therein electrically coupled across a pair of sense bit lines. First, second and third sense amplifier enable lines are also provided. The first sense amplifier enable line is electrically coupled to source terminals of the pair of MOS transistors of first conductivity type. However, to support different threshold voltage biasing, the second sense amplifier enable line is electrically coupled to a substrate terminal of a first one of the pair of MOS transistors of first conductivity type and a third sense amplifier enable line is electrically coupled to a substrate terminal of a second one of the pair of MOS transistors of first conductivity type. A controller/driver is also provided. This controller is configured to independently drive the first, second and third sense amplifier enable lines during an operation to amplify a differential voltage established across the pair of sense bit lines. 
   Additional embodiments of the invention include a first MOS sense amplifier having first and second MOS transistors of first conductivity type therein. The first MOS transistor has a first threshold voltage, a drain terminal electrically connected to a first one of a pair of sense bit lines and a gate terminal electrically connected to a second one of the pair of sense bit lines. The second MOS transistor has a second threshold voltage unequal to the first threshold voltage, a drain terminal electrically connected to the second one of the pair of sense bit lines and a gate terminal electrically connected to a first one of the pair of sense bit lines. A second MOS sense amplifier may also be provided. The second MOS sense amplifier has third and fourth MOS transistors of first conductivity type therein. The third MOS transistor has the second threshold voltage, a drain terminal electrically connected to a first one of the pair of sense bit lines and a gate terminal electrically connected to a second one of the pair of sense bit lines. The fourth MOS transistor has the first threshold voltage, a drain terminal electrically connected to the second one of the pair of sense bit lines and a gate terminal electrically connected to a first one of the pair of sense bit lines. 
   Still further embodiments of the invention include a semiconductor memory device. This memory devices includes a first memory cell connected between a first word line accessed by a first address and an inverted bit line; a second memory cell connected between a second word line accessed by a second address and a bit line; a first type sense amplifier serially connected between the bit line and the inverted bit line and having a first type first MOS transistor sensing the inverted bit line and a first type second MOS transistor sensing the bit line if a first enable signal of a first voltage is applied; a second type first sense amplifier serially connected between the bit line and the inverted bit line and having a second type first MOS transistor sensing the inverted bit line and a second type second MOS transistor sensing the bit line if a second enable signal of a second voltage is applied, wherein the second type first MOS transistor has a better sensing ability than the second type second MOS transistor; and a second type second sense amplifier serially connected between the bit line and the inverted bit line and having a second type third MOS transistor sensing the inverted bit line and a second type fourth MOS transistor sensing the bit line if a third enable signal of the second voltage is applied, wherein the second type fourth MOS transistor has a better sensing ability than the second type third MOS transistor. 
   The first type transistor is a PMOS transistor, and the second type transistor is an NMOS transistor. A threshold voltage of the second type first MOS transistor is lower than a threshold voltage of the second type second MOS transistor, and a threshold voltage of the second type fourth MOS transistor is lower than a threshold voltage of the second type third MOS transistor. The first type sense amplifier and the second type first sense amplifier operate before the second type second sense amplifier operates if the first word line is selected, and the first type sense amplifier and the second type second sense amplifier operate before the second type first sense amplifier operates if the second word line is selected. The first type sense amplifier and the second type first sense amplifier operate if the first word line is selected, and the first type sense amplifier and the second type second sense amplifier operate if the second word line is selected. The first voltage may be a power voltage, and the second voltage may be ground voltage. 
   A memory device according to another embodiment includes a first memory cell connected between a first word line accessed by a first address and an inverted bit line; a second memory cell connected between a second word line accessed by a second address and a bit line; a first type first sense amplifier serially connected between the bit line and the inverted bit line and having a first type first MOS transistor sensing the inverted bit line and a first type second MOS transistor sensing the bit line if a first enable signal of a first voltage is applied, wherein the first type second MOS transistor has a better sensing ability than the first type first MOS transistor; a first type second sense amplifier serially connected between the bit line and the inverted bit line and having a first type third MOS transistor sensing the inverted bit line and a first type fourth MOS transistor sensing the bit line if a second enable signal of the first voltage is applied, wherein the first type third MOS transistor has a better sensing ability than the first type fourth MOS transistor; and a second type sense amplifier serially connected between the bit line and the inverted bit line and having a second type first MOS transistor sensing the inverted bit line and a second type second MOS transistor sensing the bit line if a third enable signal of a second voltage is applied. The first type transistor may be a PMOS transistor, and the second type transistor may be an NMOS transistor A threshold voltage of the first type first MOS transistor is higher than a threshold voltage of the first type second MOS transistor, and a threshold voltage of the first type fourth MOS transistor is higher than a threshold voltage of the first type third MOS transistor. The first type first sense amplifier and the second type sense amplifier operate before the first type second sense amplifier operates if the first word line is selected, and the first type second sense amplifier and the second type sense amplifier operate before the first type first sense amplifier operates if the second word line is selected. The first type first sense amplifier and the second type sense amplifier operate if the first word line is selected, and the first type second sense amplifier and the second type sense amplifier operate if the second word line is selected. The first voltage may be a power voltage, and the second voltage may be ground voltage. 
   A memory device according to another embodiment of the invention includes a first memory cell connected between a first word line accessed by a first address and an inverted bit line; a second memory cell connected between a second word line accessed by a second address and a bit line; a first type first sense amplifier serially connected between the bit line and the inverted bit line and having a first type first MOS transistor sensing the inverted bit line and a first type second MOS transistor sensing the bit line if a first enable signal of a first voltage is applied, wherein the first type second MOS transistor has a better sensing ability than the first type first MOS transistor; a first type second sense amplifier serially connected between the bit line and the inverted bit line and having a first type third MOS transistor sensing the inverted bit line and a first type fourth MOS transistor sensing the bit line if a second enable signal of a second voltage is applied, wherein the first type third MOS transistor has a better sensing ability than the first type fourth MOS transistor; a second type first sense amplifier serially connected between the bit line and the inverted bit line and having a second type first MOS transistor sensing the inverted bit line and a second type second MOS transistor sensing the bit line if a third enable signal of the first voltage is applied, wherein the second type first MOS transistor has a better sensing ability than the second type second MOS transistor; and a second type second sense amplifier serially connected between the bit line and the inverted bit line and having a second type third MOS transistor sensing the inverted bit line and a second type fourth MOS transistor sensing the bit line if a fourth enable signal of the second voltage is applied, wherein the second type fourth MOS transistor has a better sensing ability than the second type third MOS transistor. The first type transistor may be a PMOS transistor, and the second type transistor may be an NMOS transistor. 
   A threshold voltage of the first type first MOS transistor is lower than a threshold voltage of the second type second MOS transistor, a threshold voltage of the first type fourth MOS transistor is lower than a threshold voltage of the first type third MOS transistor, a threshold voltage of the second type first MOS transistor is higher than a threshold voltage of the second type second MOS transistor, and a threshold voltage of the second type fourth MOS transistor is higher than a threshold voltage of the second type third MOS transistor. 
   The first type first sense amplifier and the second type first sense amplifier operate before the first type second sense amplifier and the second type second sense amplifier operate if the first word line is selected, and the first type second sense amplifier and the second type second sense amplifier operate before the first type first sense amplifier and the first type first sense amplifier and the second type first sense amplifier operate if the second word line is selected. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram illustrating configuration of a conventional semiconductor memory device; 
       FIG. 2  is a view illustrating configuration of a circuit, which generates signals LA,LAB; 
       FIG. 3  is a timing diagram illustrating refresh operation of the semiconductor memory device of  FIG. 1 ; 
       FIG. 4  is a block diagram illustrating configuration of a semiconductor memory device according to a first embodiment of the present invention; 
       FIG. 5  is a view illustrating a circuit of generating signals LA and LAB of  FIG. 4 ; 
       FIG. 6  is a timing diagram illustrating the refresh operation of the semiconductor memory device of  FIG. 4 ; 
       FIG. 7  is a block diagram illustrating a semiconductor memory device according to a second embodiment of the present invention; 
       FIG. 8  is a view illustrating a circuit of generating signals LAi, LAj and LAB of  FIG. 7 ; 
       FIG. 9  is a timing diagram illustrating the refresh operation of the semiconductor memory device of  FIG. 7 ; 
       FIG. 10  is a block diagram illustrating a semiconductor memory device according to a third embodiment of the present invention; 
       FIG. 11  is a view illustrating a circuit of generating signals Lai, LAj, LABi, and LABj of  FIG. 10 ; 
       FIG. 12  is a timing diagram illustrating the refresh operation of the semiconductor memory device of  FIG. 10 ; 
       FIG. 13  is a block diagram illustrating configuration of a semiconductor memory device according to a fourth embodiment of the present invention; 
       FIG. 14  is a view illustrating a circuit of generating signals LA, LAB, LAB 1 , and LAB 2  of  FIG. 13 ; 
       FIG. 15  is a timing diagram illustrating the refresh operation of the semiconductor memory device of  FIG. 13 ; 
       FIG. 16  is a block diagram illustrating configuration of a semiconductor memory device according to a fifth embodiment of the present invention; 
       FIG. 17  is a view illustrating a circuit of generating signals LA, LAB, LA 1 , and LA 2  of  FIG. 16 ; 
       FIG. 18  is a timing diagram illustrating the refresh operation of the semiconductor memory device of  FIG. 16 ; 
       FIG. 19  is a block diagram illustrating configuration of a semiconductor memory device according to a sixth embodiment of the present invention; 
       FIG. 20  is a view illustrating a circuit of generating signals LA, LAB, LA 1 , LA 2 , LAB 1 , and LAB 2  of  FIG. 19 ; and 
       FIG. 21  is a timing diagram illustrating the refresh operation of the semiconductor memory device of  FIG. 19 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Moreover, the terms “first conductivity type” and “second conductivity type” refer to opposite conductivity types such as N or P-type, however, each embodiment described and illustrated herein includes its complementary embodiment as well 
   Like reference numbers refer to like elements throughout and signal lines and signals thereon may be referred to by the same reference characters. Signals may also be synchronized and/or undergo minor Boolean operations (e.g., inversion) without being considered different signals. 
     FIG. 4  is a block diagram illustrating configuration of a semiconductor memory device according to a first embodiment of the present invention. The NMOS sense amplifier NSA is replaced with a first NMOS sense amplifier NSAi and a second NMOS sense amplifier NSAj. The first NMOS sense amplifier NSAi includes NMOS transistors N 6  and N 7 , and the second sense amplifier NSAj includes NMOS transistors N 8  and N 9 . The NMOS transistor N 6  is relatively lower in threshold voltage than the NMOS transistor N 7 , and the NMOS transistor N 9  is relatively lower in threshold voltage than the NMOS transistor N 8 , whereas the PMOS transistors P 1  and P 2  are designed to have the same threshold voltage. Like reference numerals of  FIGS. 1 and 4  denote like parts and like functions, and thus description on those is omitted. 
   The memory cells MC 1  and MC 4  store data of a high level and the sub word line SWL 1  or the sub word line SWL 4  is selected during the refresh operation, the charge sharing operation is performed. Then, if a signal LA of a power voltage VCC level and a signal LABi of a ground voltage VSS level are applied, since the NMOS transistor N 6  is lower in threshold voltage than the NMOS transistor N 7 , even if a voltage of the inverted sense bit line SBL 1 B is raised a little, a voltage difference between a gate and a source of the NMOS transistor N 6  becomes greater than a threshold voltage of the NMOS transistor N 6 , so that the NMOS transistor N 6  is turned on to reduce a voltage of the sense bit line SBL 1 . In response, a voltage difference between a gate and a source of the PMOS transistor P 2  becomes greater than a threshold voltage of the PMOS transistor P 2 , so that the PMOS transistor P 2  is turned on to increase a voltage of the inverted sense bit line SBL 1 B. Thereafter, if a signal LABj of a ground voltage VSS level is applied, the NMOS transistor N 8  of the NMOS sense amplifier NSAj is turned on, so that the NMOS transistors N 6  and N 8  amplify the sense bit line SBL 1  to a ground voltage VSS level together. The PMOS transistor P 2  amplifies the inverted sense bit line SBL 1 B to a power voltage VCC level. 
   On the other hand, if the memory cells MC 2  and MC 3  store data of a high level and the sub word line SWL 2  or the sub word line SWL 3  is selected during the refresh operation, the charge sharing operation is performed. Then, if a signal LA of a power voltage VCC level and a signal LABj of a ground voltage VSS level are applied, since the NMOS transistor N 9  is lower in threshold voltage than the NMOS transistor N 8 , even if a voltage of the sense bit line SBL 1  is raised a little, a voltage difference between a gate and a source of the NMOS transistor N 9  becomes greater than a threshold voltage of the NMOS transistor N 9 , so that the NMOS transistor N 9  is turned on to reduce a voltage of the inverted sense bit line SBL 1 B. Thus, a voltage difference between a gate and a source of the PMOS transistor P 1  becomes greater than a threshold voltage of the PMOS transistor P 1 , so that the PMOS transistor P 1  is turned on to increase a voltage of the sense bit line SBL 1 . Thereafter, if a signal LABi of a ground voltage VSS level is applied, the NMOS transistor N 7  is turned on, so that the NMOS transistors N 7  and N 9  pull the sense bit line SBL 1  to a ground voltage VSS level together. The PMOS transistor P 1  makes the inverted sense bit line SBL 1 B be a power voltage VCC level. 
     FIG. 5  is a view illustrating a circuit of generating signals LA and LAB of  FIG. 4 . The circuit of  FIG. 5  includes a controller  20 , a PMOS transistor P 3 , and NMOS transistors N 10  and N 11 . The controller  20  generates first and second bit line sense amplifier enable control signals LAPG and LANGi of a low level and a high level if an active command ACT or a refresh command REF is applied and a 2-bit least significant bit (“LSB”) of row address A 0  and A 1  is applied and so the 2-bit LSB of row address A 0 ,A 1  are “00” or “11”. The PMOS transistor P 3  generates a signal LA of a power voltage VCC level in response to the first bit line sense amplifier enable control signal LAPG of a low level. The NMOS transistor N 10  generates a signal LABi of a ground voltage VSS level in response to the second bit line sense amplifier enable signal LANGi of a high level. Thereafter, a third bit line sense amplifier enable control signal LANGj of a high level is generated. The NMOS transistor N 11  generates a signal LABj of a ground voltage VSS level in response to the third bit line sense amplifier enable control signal LANGj of a high level. 
   On the other hand, the controller  20  generates the first and third bit line sense amplifier enable control signals LAPG and LANGj of a low level and a high level if an active command ACT or a refresh command REF is applied and a 2-bit least significant bit (“LSB”) of row address A 0  and A 1  is applied and so the 2-bit LSB of row address A 0 A 1  are “01” or “10”. The PMOS transistor P 3  generates a signal LA of a power voltage VCC level in response to the first bit line sense amplifier enable control signal LAPG of a low level. The NMOS transistor N 11  generates a signal LABj of a ground voltage VSS level in response to the third bit line sense amplifier enable signal LANGj of a high level. Thereafter, the second bit line sense amplifier enable control signal LANGi of a high level is generated. The NMOS transistor N 10  generates a signal LABi of a ground voltage VSS level in response to the second bit line sense amplifier enable control signal LANGi of a high level. 
     FIG. 6  is a timing diagram illustrating the refresh operation of the semiconductor memory device of  FIG. 4 . The refresh operation is performed under the same condition as that of  FIG. 3 . Operation during the charge sharing operation period T is the same as the timing diagram of  FIG. 3 . Here, since the refresh cycle is set to be long, levels of the inverted array bit line ABL 1 B and the inverted sense bit line SBL 1 B during the charge sharing operation period T are raised by a voltage Δv. The voltage Δv of  FIG. 6  is lower in level than the voltage ΔV of  FIG. 3 . 
   If the levels of the inverted array bit line ABL 1 B and the inverted sense bit line SBL 1 B are raised by a voltage Δv by the charge sharing operation during the charge sharing operation period T, the first and second bit line sense amplifier enable control signals LA and LABi of a power voltage VCC level and a ground voltage VSS level are generated. The NMOS transistor N 6  is turned on in response to a voltage of the inverted sense bit line SBL 1 B to reduce a level of the sense bit line SBL 1 , and the PMOS transistor P 2  is turned on in response to a voltage of the sense bit line SBL 1  to increase a level of the inverted sense bit line SBL 1 B. Thereafter, the third bit line sense amplifier enable control signal LABj of a ground voltage VSS level is generated. The PMOS sense amplifier PSA and the NMOS sense amplifiers NSAi and NSAj perform the sensing operation to amplify voltages of the inverted array bit line ABL 1 B and the inverted sense bit line SBL 1 B to a power voltage VCC level and to amplify voltages of the array bit line ABL 1  and the sense bit line SBL 1  to a ground voltage VSS level. 
   Even though not shown, if in state that the memory cell MC 2  stores data of a high level and the array bit line pair ABL 1 ,ABL 1 B and the sense bit line pair SBL 1 ,SBL 1 B are precharged to a precharge voltage VBL level, the refresh command REF is applied so that the sub word line SWL 2  is selected, the signals LA and LABj are generated, and then the signal LABi is generated. 
   As described above, the bit line sense amplifier of the semiconductor memory device according to the first embodiment of the present invention can perform the sensing operation even if a level of the inverted sense bit line SBL 1 B is varied by a small Δv since the NMOS transistor N 6  is lower in threshold voltage than the NMOS transistor N 7  in case that the memory cells MC 1  and MC 4  are selected. In case that the memory cells MC 2  and MC 3  are selected, it is possible to perform the sensing operation even if a level of the sense bit line SBL 1  is varied by a small Δv since the NMOS transistor N 9  is lower in threshold voltage than the NMOS transistor N 8 . That is, by having the NMOS transistor N 6  for data of a high level to have greater sensing ability than the NMOS transistor N 7  and having the NMOS transistor N 9  for data of a high level to have greater sensing ability than the NMOS transistor N 8 , the sensing ability of the bit line sense amplifier for data of a high level is improved, thereby lengthening the refresh cycle. 
   Operation of the semiconductor memory device according to the first embodiment of the present invention has been explained with a case that a signal LABj/LABi of a ground voltage VSS level is applied after a signal LABi/LABj of a ground voltage level is applied. But, a signal LABj/LABi of a floating state can be applied after a signal LABi/LABj of a ground voltage VSS level is applied. Thus, it is not absolutely in all embodiments to operate both NMOS sense amplifiers NSAi and NSAj. 
     FIG. 7  is a block diagram illustrating a semiconductor memory device according to a second embodiment of the present invention. The PMOS sense amplifier PSA is replaced with a first PMOS sense amplifier PSAi and a second PMOS sense amplifier PSAj. The first PMOS sense amplifier PSAi includes PMOS transistors P 6  and P 7 , and the second sense amplifier PSAj includes PMOS transistors P 4  and P 5 . This second embodiment is the dual of the first embodiment with respect to the NMOS and PMOS sense amplifiers. The PMOS transistor P 5  has a greater threshold voltage than the PMOS transistor P 4 , and the PMOS transistor P 6  has a greater threshold voltage than the PMOS transistor P 7 , and the NMOS transistors N 1  and N 2  are designed to have the same threshold voltage. 
   Like reference numerals of  FIGS. 1 and 7  denote like parts and like functions, and thus description on those is omitted. If the memory cells MC 1  and MC 4  store data of a high level and the sub word line SWL 1  or the sub word line SWL 4  is selected during the refresh operation, the charge sharing operation is performed. Then, if a signal LAi of a power voltage VCC level and a signal LAB of a ground voltage VSS level are applied, since the PMOS transistor P 6  is greater in threshold voltage than the PMOS transistor P 7 , if a signal LAi of a power voltage VCC level is applied, a voltage difference between a gate and a source of the PMOS transistor P 7  becomes greater than a threshold voltage of the PMOS transistor P 7 , so that the PMOS transistor P 7  is turned on to amplify a voltage of the inverted sense bit line SBL 1 B to a power voltage VCC level. Thus, a voltage difference between a gate and a source of the NMOS transistor N 1  becomes greater than a threshold voltage of the NMOS transistor N 1 , so that the NMOS transistor N 1  is turned on to amplify a voltage of the sense bit line SBL 1  to a ground voltage VSS level. Thereafter, if a signal LAj of a power voltage VCC level is applied, the PMOS transistor P 5  is turned on, so that the PMOS transistors P 5  and P 7  amplify the inverted sense bit line SBL 1 B to a power voltage VCC level together. 
   On the other hand, if the memory cells MC 2  and MC 3  store data of a high level and the sub word line SWL 2  or the sub word line SWL 3  is selected during the refresh operation, the charge sharing operation is performed. Then, if a signal LAj of a power voltage VCC level and a signal LAB of a ground voltage VSS level are applied, the PMOS transistor P 4  is turned on to amplify a voltage of the inverted sense bit line SBL 1 B to a power voltage VCC level. The NMOS transistor N 2  is turned on to amplify a voltage of the sense bit line SBL 1  to a ground voltage VSS level. Thereafter, if a signal LAi of a power voltage VCC level is applied, the PMOS transistor P 6  is turned on, so that the PMOS transistors P 4  and P 6  amplify the inverted sense bit line SBL 1 B to a power voltage VCC level together. 
     FIG. 8  is a view illustrating a circuit of generating signals LAi, LAj and LAB of  FIG. 7 . The circuit of  FIG. 8  includes a controller  30 , PMOS transistors P 8  and P 9 , and an NMOS transistor N 5 . The controller  30  generates first and second bit line sense amplifier enable control signals LAPGi and LANG of a low level and a high level if an active command ACT or a refresh command REF is applied and a 2-bit LSB of row address A 0  and A 1  is applied and so the 2-bit LSB of row address A 0 ,A 1  are “00” or “11”. The PMOS transistor P 8  generates a signal LAi of a power voltage VCC level in response to the first bit line sense amplifier enable control signal LAPGi of a low level. The NMOS transistor N 5  generates a signal LAB of a ground voltage VSS level in response to the second bit line sense amplifier enable signal LANG of a high level. Thereafter, a third bit line sense amplifier enable control signal LAPGj of a low level is generated. The PMOS transistor P 9  generates a signal LAj of a power voltage VCC level in response to the third bit line sense amplifier enable control signal LAPGj of a low level. 
   On the other hand, the controller  30  generates the second and third bit line sense amplifier enable control signals LANG and LAPGj of a low level and a high level if an active command ACT or a refresh command REF is applied and a 2-bit LSB of row address A 0  and A 1  is applied and so the 2-bit LSB of row address A 0 A 1  are “01” or “10”. The PMOS transistor P 9  generates a signal LAj of a power voltage VCC level in response to the third bit line sense amplifier enable control signal LAPGj of a low level. The NMOS transistor N 5  generates a signal LAB of a ground voltage VSS level in response to the second bit line sense amplifier enable signal LANG of a high level. Thereafter, the first bit line sense amplifier enable control signal LAPGi of a low level is generated. The PMOS transistor P 8  generates a signal LAi of a power voltage VCC level in response to the first bit line sense amplifier enable control signal LAPGi of a low level. 
     FIG. 9  is a timing diagram illustrating the refresh operation of the semiconductor memory device of  FIG. 7 . The refresh operation is performed tinder the same condition as that of  FIG. 3 . Operation during the charge sharing operation period T is the same as the timing diagram of  FIG. 6 . If the voltages of the inverted array bit line ABL 1 B and the inverted sense bit line SBL 1 B are increased by a voltage Δv by the charge sharing operation during the charge sharing operation period T, the first and second bit line sense amplifier enable control signals LAi and LAB of a power voltage VCC level and a ground voltage VSS level are generated. The PMOS transistor P 7  is turned on by sensing a voltage of the sense bit line SBL 1  to increase a level of the inverted sense bit line SBL 1 B, and the NMOS transistor N 1  is turned on by sensing a voltage of the inverted sense bit line SBL 1 B to reduce a level of the sense bit line SBL 1 . Thereafter, the third bit line sense amplifier enable control signal LAj of a power voltage VCC level is generated. The PMOS sense amplifiers PSAi and PSAj and the NMOS sense amplifier NSA perform the sensing operation to amplify voltages of the inverted array bit line ABL 1 B and the inverted sense bit line SBL 1 B to a power voltage VCC level and to amplify voltages of the array bit line ABL 1  and the sense bit line SBL 1  to a ground voltage VSS level. That is, since the PMOS transistor P 7  is designed to be lower in threshold voltage than the PMOS transistor P 6 , if a signal LAi of a power voltage VCC level is applied, a voltage difference between a gate and a source of the PMOS transistor P 7  becomes greater than a threshold voltage of the PMOS transistor P 7 , so that the PMOS transistor P 7  is turned on to raise a level of the inverted sense bit line SBL 1 B. 
   Even though not shown, if in state that the memory cell MC 2  stores data of a high level and the array bit line pair ABL 1 ,ABL 1 B and the sense bit line pair SBL 1 ,SBL 1 B are precharged to a precharge voltage VBL level, the refresh command REF is applied so that the sub word line SWL 2  is selected, the signals LAj and LAB are generated, and then the signal LABi is generated. 
   As described above, in the bit line sense amplifier of the semiconductor memory device according to the second embodiment of the present invention, it is possible for the PMOS transistor P 7  to perform the sensing operation even if a level of the inverted sense bit line SBL 1 B is varied by Δv since the PMOS transistor P 7  is lower in threshold voltage than the PMOS transistor P 6  in case of the refresh operation for the memory cells MC 1  and MC 4 . In case of the refresh operation for the memory cells MC 2  and MC 3 , it is possible for the PMOS transistor P 4  to perform the sensing operation even if a level of the sense bit line SBL 1  is varied by Δv since the PMOS transistor P 4  is lower in threshold voltage than the PMOS transistor P 5 . Thus, the sensing ability of the bit line sense amplifier for data of a high level is improved, thereby lengthening the refresh cycle. 
   Operation of the semiconductor memory device according to the second embodiment of the present invention has been explained with a case that a signal LAj/LAi of a power voltage VCC level is applied after a signal LAi/LAj of a power voltage VCC level is applied. But, in alternative embodiments, a signal LAj/LAi of a floating state can be applied after a signal LAi/LAj of a power voltage VSCC level is applied. Thus, it is not necessary to operate two PMOS sense amplifiers PSAi and PSAj. 
     FIG. 10  is a block diagram illustrating a semiconductor memory device according to a third embodiment of the present invention. The NMOS sense amplifier NSA of  FIG. 1  is replaced with NMOS sense amplifiers NSAi and NSAj, and the PMOS sense amplifier PSA is replaced with PMOS sense amplifiers PSAi and PSAj. The NMOS sense amplifier NSAi includes NMOS transistors N 6  and N 7 , and the NMOS sense amplifier NSAj includes NMOS transistors N 8  and N 9 , and the PMOS sense amplifier PSAj includes PMOS transistors P 4  and P 5 , and the PMOS sense amplifier PSAi includes NMOS transistors P 6  and P 7 . In  FIG. 10 , the PMOS transistor P 5  is relatively greater in threshold voltage than the PMOS transistor P 4 , the PMOS transistor P 6  is relatively greater in threshold voltage than the PMOS transistor P 7 , the NMOS transistor N 6  is relatively lower in threshold voltage than the NMOS transistor N 7 , and the NMOS transistor N 9  is relatively lower in threshold voltage than the NMOS transistor N 8 . Like reference numerals of  FIGS. 1 and 7  denote like parts and like functions, and thus description on those is omitted. 
   If the memory cells MC 1  and MC 4  store data of a high level and the sub word line SWL 1  or the sub word line SWL 4  is selected during the refresh operation, the charge sharing operation is performed. Then, if a signal LAi of a power voltage VCC level and a signal LABi of a ground voltage VSS level are applied, a voltage difference between a gate and a source of the PMOS transistor P 7  becomes greater than a threshold voltage of the PMOS transistor P 7 , and a voltage difference between a gate and a source of the NMOS transistor N 6  becomes greater than a threshold voltage of the NMOS transistor N 6 . The PMOS transistor P 7  is turned on to amplify a voltage of the inverted sense bit line SBL 1 B to a power voltage VCC level, and the NMOS transistor N 6  is turned on to amplify a voltage of the sense bit line SBL 1  to a ground voltage VSS level. Thereafter, if a signal LAj of a power voltage VCC level and a signal LABj of a ground voltage VSS level are applied, the PMOS sense amplifiers PSAi and PSAj and the NMOS sense amplifiers NSAi and NSAj perform the sensing operation together to make a voltage of the sense bit line SBL 1  be a ground voltage VSS level and a voltage of the inverted sense bit line SBL 1 B be a power voltage VCC level. 
   On the other hand, if the memory cells MC 2  and MC 3  store data of a high level and the sub word line SWL 2  or the sub word line SWL 3  is selected during the refresh operation, the charge sharing operation is performed. Then, if a signal LAj of a power voltage VCC level and a signal LABj of a ground voltage VSS level are applied, a voltage difference between a gate and a source of the PMOS transistor P 4  becomes greater than a threshold voltage of the PMOS transistor P 4 , and a voltage difference between a gate and a source of the NMOS transistor N 9  becomes greater than a threshold voltage of the NMOS transistor N 9 . The PMOS transistor P 4  is turned on to amplify a voltage of the sense bit line SBL 1  to a power voltage VCC level, and the NMOS transistor N 9  is turned on to amplify a voltage of the inverted sense bit line SBL 1 B to a ground voltage VSS level. 
   Thereafter, if a signal LAi of a power voltage VCC level and a signal LABi of a ground voltage VSS level are applied, the PMOS sense amplifiers PSAi and PSAj and the NMOS sense amplifiers NSAi and NSAj perform the sensing operation make a voltage of the inverted sense bit line SBL 1 B be a power voltage VCC level and a voltage of the sense bit line SBL 1  be a ground voltage VSS level. 
     FIG. 11  is a view illustrating a circuit of generating signals LAi, LAj, LABi, and LABj of  FIG. 10 . The circuit of  FIG. 11  includes a controller  40 , PMOS transistors P 8  and P 9 , and NMOS transistors N 10  and N 11 . The controller  40  generates first and second bit line sense amplifier enable control signals LAPGi and LANGi of a low level and a high level if an active command ACT or a refresh command REF is applied and a 2-bit LSB of row address A 0  and A 1  is applied and so the 2-bit LSB of row address A 0 ,A 1  are “00” or “11”. The PMOS transistor P 8  generates a signal LAi of a power voltage VCC level in response to the first bit line sense amplifier enable control signal LAPGi of a low level, and the NMOS transistor N 10  generates a signal LABi of a ground voltage VSS level in response to the second bit line sense amplifier enable signal LANGi of a high level. Thereafter, a third bit line sense amplifier enable control signal LAPGj of a low level and a fourth bit line sense amplifier enable control signal LANGj of a high level are generated. The PMOS transistor P 9  generates a signal LAj of a power voltage VCC level in response to the third bit line sense amplifier enable control signal LAPGj of a low level, and the NMOS transistor N 11  generates a signal LABj of a ground voltage VSS level in response to the fourth bit line sense amplifier enable control signal LANGj of a high level. 
   On the other hand, the controller  40  generates the third and fourth bit line sense amplifier enable control signals LAPGj and LANGj of a low level and a high level if an active command ACT or a refresh command REF is applied and a 2-bit LSB of row address A 0  and A 1  is applied and so the 2-bit LSB of row address A 0 A 1  are “01” or “10”. The PMOS transistor P 9  generates a signal LAj of a power voltage VCC level in response to the third bit line sense amplifier enable control signal LAPGj of a low level, and the NMOS transistor N 11  generates a signal LABj of a ground voltage VSS level in response to the fourth bit line sense amplifier enable signal LANGj of a high level. 
   Thereafter, the first bit line sense amplifier enable control signal LAPGi of a low level and the second bit line sense amplifier enable control signal LANGi of a high level are generated. The PMOS transistor PS generates a signal LAi of a power voltage VCC level in response to the first bit line sense amplifier enable control signal LAPGi of a low level, and the NMOS transistor N 10  generates a signal LABi of a ground voltage VSS level in response to the second bit line sense amplifier enable control signal LANGi of a high level. 
     FIG. 12  is a timing diagram illustrating the refresh operation of the semiconductor memory device of  FIG. 10 . The refresh operation is performed under the same condition as that of  FIG. 3 . Operation during the charge sharing operation period T is the same as the timing diagram of  FIG. 6 . If the levels of the inverted array bit line ABL 1 B and the inverted sense bit line SBL 1 B are raised by a voltage Δv by the charge sharing operation during the charge sharing operation period T, the first and second bit line sense amplifier enable control signals LAi and LABi of a power voltage VCC level and a ground voltage VSS level are generated. The PMOS transistor P 7  senses a voltage of the sense bit line SBL 1 , to increase a level of the inverted sense bit line SBL 1 B, and the NMOS transistor N 6  senses a voltage of the inverted sense bit line SBL 1 B to reduce a level of the sense bit line SBL 1 . Thereafter, the third bit lines sense amplifier enable control signal LAj of a power voltage VCC level and the fourth bit line sense amplifier enable control signal LABj of a ground voltage VSS level are generated. The PMOS sense amplifiers PSAi and PSAj and the NMOS sense amplifiers NSAi and NSAj perform the sensing operation together to amplify the inverted sense bit line SBL 1 B to a power voltage VCC level and the sense bit line SBL 1  to a ground voltage VSS level. 
   Even though not shown, if in state that the memory cell MC 2  stores data of a high level and the array bit line pair ABL 1 ,ABL 1 B and the sense bit line pair SBL 1 ,SBL 1 B are precharged to a precharge voltage VBL level, the refresh command REF is applied so that the sub word line SWL 2  is selected, the signals LAj and LABj are generated, and then the signals LAi and LABi is generated. 
   In the bit line sense amplifier of the semiconductor memory device according to the first embodiment of the present invention, during the refresh operation for the memory cells MC 1  and MC 4 , it is possible for the PMOS transistor P 7  to perform the sensing operation even if a level of the inverted sense bit line SBL 1 B is varied by Δv since the PMOS transistor P 7  is lower in threshold voltage than the PMOS transistor P 6 , and it is possible for the NMOS transistor N 6  to perform the sensing operation even if a level of the inverted sense bit line SBL 1 B is increased by Δv since the NMOS transistor N 6  is lower in threshold voltage than the NMOS transistor N 7 . During the refresh operation for the memory cells MC 2  and MC 3 , it is possible for the PMOS transistor P 4  to perform the sensing operation even if a level of the sense bit line SBL 1  is varied by Δv since the PMOS transistor P 4  is lower in threshold voltage than the PMOS transistor P 5 , and it is possible for the NMOS transistor N 9  to perform the sensing operation even if a level of the sense bit line SBL 1  is increased by Δv since the NMOS transistor N 9  is lower in threshold voltage than the NMOS transistor N 8 . 
   Operation of the semiconductor memory device according to the third embodiment of the present invention has been explained with a case where a signal LAj/LAi of a power voltage VCC level and a signal LABj/LABi of a ground voltage VSS level are applied after a signal LAi/LAj of a power voltage VCC level and a signal LABi/LABj of a ground voltage level are applied. But, signals LAj/LAi and LABj/LABi of a floating state can be applied after a signal LAi and LAj of a power voltage VCC level and a signal LABi/LABj of a ground voltage VSS level are applied. Thus, it is not necessary to operate two NMOS sense amplifiers NSAi and NSAj and two PMOS sense amplifiers PSAi and PSAj. 
     FIG. 13  is a block diagram illustrating configuration of a semiconductor memory device according to a fourth embodiment of the present invention. The semiconductor memory device of  FIG. 13  has the same configuration as that of  FIG. 1  except that signals LAB 1  and LAB 2  are respectively applied to respective substrates of the NMOS transistors N 1  and N 2 . 
   Like reference numerals of  FIGS. 1 and 13  denote like parts and like functions. Thus, operation when the signals LAB 1  and LAB 2  are applied will be explained below. If the memory cells MC 1  and MC 4  store data of a high level and the sub word line SWL 1  or the sub word line SWL 4  is selected during the refresh operation, the charge sharing operation is performed. Then, if a signal LAB 1  having a level higher than a substrate voltage VBB and a signal LAB 2  of a substrate voltage VBB level are applied, a threshold voltage of the NMOS transistor N 1  becomes lower than a threshold voltage of the NMOS transistor N 2 . Then, if a signal LA of a power voltage VCC level and a signal LAB of a ground voltage VSS level are applied, the same operation as the bit line sense amplifier of  FIG. 4  is performed. 
   On the other hand, if the memory cells MC 2  and MC 3  store data of a high level and the sub word line SWL 2  or the sub word line SWL 3  is selected during the refresh operation, the charge sharing operation is performed. Then, if a signal LAB 2  having a level higher than a substrate voltage VBB and a signal LAB 1  of a substrate voltage VBB level are applied, a threshold voltage of the NMOS transistor N 2  becomes lower than a threshold voltage of the NMOS transistor N 1 . Then, if a signal LA of a power voltage VCC level and a signal LAB of a ground voltage VSS level are applied, the same operation as the bit line sense amplifier of  FIG. 4  is performed. 
     FIG. 14  is a view illustrating a circuit of generating signals LA, LAB, LAB 1 . and LAB 2  of  FIG. 13 . The circuit of  FIG. 14  includes a controller  50 , a PMOS transistor P 3 , and NMOS transistors N 5  and N 12  to N 15 . 
   Functions of the components of  FIG. 14  are explained below. 
   The controller  50  generates first and fourth substrate voltage control signals CON 1  and CON 4  of a high level and second and third substrate voltage control signals CON 2  and CON 3  of a low level if an active command ACT or a refresh command REF is applied and a 2-bit LSB of row address A 0  and A 1  is applied and so the 2-bit LSB of row address A 0 ,A 1  are “00” or “11”. Here, a low level applied to the NMOS transistor N 13  is a substrate voltage VBB level. The NMOS transistors N 13  and N 14  are turned off and the NMOS transistors N 12  and N 15  are turned on, so that a signal LAB 1  of a higher voltage VBB+α than a substrate voltage VBB and a signal LAB 2  of a substrate voltage VBB level are generated. 
   On the other hand, first and fourth substrate voltage control signals CON 1  and CON 4  of a low level and second and third substrate voltage control signals CON 2  and CON 3  of a high level are generated if an active command ACT or a refresh command REF is applied and a 2-bit LSB of row address A 0  and A 1  is applied and so the 2-bit LSB of row address A 0 ,A 1  are “01” or “10”. Here, a low level applied to the NMOS transistor N 15  is a substrate voltage VBB level. The NMOS transistors N 12  and N 15  are turned off and the NMOS transistors N 13  and N 14  are turned on, so that a signal LAB 1  of a substrate voltage VBB and a signal LAB 2  of a higher voltage VBB+α than a substrate voltage VBB level are generated. 
   Thereafter, first and second bit line sense amplifier enable control signals LAPG and LANG of a low level and a high level are generated. Therefore, the PMOS transistor P 3  generates a signal LA of a power voltage VCC level in response to the first bit line sense amplifier enable control signal LAPG of a low level, and the NMOS transistor N 5  generates a signal LAB of a ground voltage VSS level in response to the second bit line sense amplifier enable control signal LANG of a high level 
     FIG. 15  is a timing diagram illustrating the refresh operation of the semiconductor memory device of  FIG. 13 . The refresh operation is performed under the same condition as that of  FIG. 6 . 
   Operation during the charge sharing operation period T is the same as the timing diagram of  FIG. 6 . 
   Thereafter, if a signal LAB 1  of a higher voltage VBB+α than a substrate voltage VBB and a signal LAB 2  of a substrate voltage VBB level are applied, a threshold voltage of the NMOS transistor N 1  becomes lower than a threshold voltage of the NMOS transistor N 2 . If a signal LA of a power voltage VCC level and a signal LAB of a ground voltage VSS level are applied, the same operation as in the timing diagram of  FIG. 6  is performed. 
   Even though not shown, if in state that the memory cell MC 2  stores data of a high level and the array bit line pair ABL 1 ,ABL 1 B and the sense bit line pair SBL 1 ,SBL 1 B are precharged to a precharge voltage VBL level, the refresh command REF is applied so that the sub word line SWL 2  is selected, a signal LAB 1  of a substrate voltage VBB and a signal LAB 2  of a higher voltage VBB+α than a substrate voltage VBB level are generated. Then, a signal LA of a power voltage VCC level and a signal LAB of a ground voltage VSS level are applied. 
   The semiconductor memory device of  FIG. 13  has a different configuration but performs the same operation as that of  FIG. 4 . 
     FIG. 16  is a block diagram illustrating configuration of a semiconductor memory device according to a fifth embodiment of the present invention. The semiconductor memory device of  FIG. 16  has the same configuration as that of  FIG. 1  except that signals LA 1  and LA 2  are respectively applied to respective substrates of the PMOS transistors P 1  and P 2 . 
   Like reference numerals of  FIGS. 1 and 16  denote like parts and like functions. Thus, operation when the signals LA 1  and LA 2  are applied will be explained below. 
   If the memory cells MC 1  and MC 4  store data of a high level and the sub word line SWL 1  or the sub word line SWL 4  is selected during the refresh operation, the charge sharing operation is performed. Then, if a signal LA 1  having a level lower than a power voltage VCC level and a signal LA 2  of a power voltage VCC level are applied, a threshold voltage of the PMOS transistor P 2  becomes lower than a threshold voltage of the PMOS transistor P 1 . Then, if a signal LA of a power voltage VCC level and a signal LAB of a ground voltage VSS level are applied, the same operation as the bit line sense amplifier of  FIG. 7  is performed. 
   On the other hand, if the memory cells MC 2  and MC 3  store data of a high level and the sub word line SWL 2  or the sub word line SWL 3  is selected during the refresh operation, the charge sharing operation is performed. Then, if a signal LA 2  having a level lower than a power voltage VCC level and a signal LA 1  of a power voltage VCC level are applied, a threshold voltage of the PMOS transistor P 1  becomes lower than a threshold voltage of the PMOS transistor P 2 . Then, if a signal LA of a power voltage VCC level and a signal LAB of a ground voltage VSS level are applied, the same operation as the bit line sense amplifier of  FIG. 7  is performed. 
     FIG. 17  is a view illustrating a circuit of generating signals LA, LAB, LA 1 , and LA 2  of  FIG. 16 . The circuit of  FIG. 17  includes a controller  60 , PMOS transistors P 3  and P 10  to P 13 , and an NMOS transistor N 5 . 
   Functions of the components of  FIG. 17  are explained below. 
   The controller  60  generates first and fourth substrate voltage control signals CON 5  and CON 8  of a low level and second and third substrate voltage control signals CON 6  and CON 7  of a high level if an active command ACT or a refresh command REF is applied and the 2-bit LSB of row address A 0 ,A 1  are “00” or “11”. The PMOS transistors P 10  and P 13  are turned on and the PMOS transistors P 11  and P 12  are turned off, so that a signal LA 2  of a power voltage VCC level and a signal LA 1  of a lower voltage VCC-β level than a power voltage VCC level are generated. 
   On the other hand, first and fourth substrate voltage control signals CON 5  and CON 8  of a high level and second and third substrate voltage control signals CON 6  and CON 7  of a low level are generated if an active command ACT or a refresh command REF is applied and a 2-bit LSB of row address A 0  and A 1  is applied and so the 2-bit LSB of row address A 0 ,A 1  are “01” or “10”. The PMOS transistors P 10  and P 13  are turned off and the PMOS transistors P 11  and P 12  are turned on, so that a signal LA 1  of a power voltage VCC level and a signal LA 2  of a lower voltage VCC-β level than a power voltage VCC level are generated. 
   Thereafter, first and second bit line sense amplifier enable control signals LAPG and LANG of a low level and a high level are generated. Therefore, the PMOS transistor P 3  generates a signal LA of a power voltage VCC level in response to the first bit line sense amplifier enable control signal LAPG of a low level, and the NMOS transistor N 5  generates a signal LAB of a ground voltage VSS level in response to the second bit line sense amplifier enable control signal LANG of a high level. 
     FIG. 18  is a timing diagram illustrating the refresh operation of the semiconductor memory device of  FIG. 16 . The refresh operation is performed under the same condition as that of  FIG. 3 . 
   Operation during the charge sharing operation period T is the same as the timing diagram of  FIG. 6 . 
   Thereafter, if a signal LA 1  of a lower voltage VCC-β than a power voltage VCC level and a signal LA 2  of a power voltage VCC level are applied and a signal LA of a power voltage VCC level and a signal LAB of a ground voltage VSS level are applied, the same operation as in the timing diagram of  FIG. 6  is performed. 
   Even though not shown, if in state that the memory cell MC 2  stores data of a high level and the array bit line pair ABL 1 ,ABL 1 B and the sense bit line pair SBL 1 ,SBL 1 B are precharged to a precharge voltage VBL level, the refresh command REF is applied so that the sub word line SWL 2  is selected, a signal LA 1  of a power voltage VCC level and a signal LA 2  of a lower voltage than a power voltage VCC level are generated, and a signal LA of a power voltage VCC level and a signal LAB of a ground voltage VSS level are applied. 
   The semiconductor memory device of  FIG. 16  has a different configuration but performs the same operation as that of  FIG. 7 . 
     FIG. 19  is a block diagram illustrating configuration of a semiconductor memory device according to a sixth embodiment of the present invention. The semiconductor memory device of  FIG. 19  has the same configuration as that of  FIG. 10  except that signals LA 1  and LA 2  are respectively applied to respective substrates of the PMOS transistors P 1  and P 2  and signals LAB 1  and LAB 2  are respectively applied to respective substrates of the NMOS transistors N 1  and N 2 . 
   Like reference numerals of  FIGS. 1 and 19  denote like parts and like functions. Thus, operation when the signals LA 1 , LA 2 , LAB 1  and LAB 2  are applied will be explained below. 
   If the memory cells MC 1  and MC 4  store data of a high level and the sub word line SWL 1  or the sub word line SWL 4  is selected during the refresh operation, the charge sharing operation is performed. Then, if a signal LA 2  of a power voltage VCC level, a signal LAB 1  having a level higher than a substrate voltage VBB, a signal LA 1  of a lower voltage level than a power voltage VCC level, and a signal LAB 2  of a substrate voltage VBB level are applied, a threshold voltage of the PMOS transistor P 1  becomes higher than a threshold voltage of the PMOS transistor P 2 , and a threshold voltage of the NMOS transistor N 1  becomes lower than a threshold voltage of the NMOS transistor N 2 . Then, if a signal LA of a power voltage VCC level and a signal LAB of a ground voltage VSS level are applied, the same operation as the bit line sense amplifier of  FIG. 10  is performed. 
   On the other hand, if the memory cells MC 2  and MC 3  store data of a high level and the sub word line SWL 2  or the sub word line SWL 3  is selected during the refresh operation, the charge sharing operation is performed. Then, if a signal LA 1  of a power voltage VCC level, a signal LAB 2  having a level higher than a substrate voltage VBB, a signal LA 2  of a lower voltage level than a power voltage VCC level, and a signal LAB 1  of a substrate voltage VBB level are applied, a threshold voltage of the PMOS transistor P 2  becomes higher than a threshold voltage of the PMOS transistor P 1 , and a threshold voltage of the NMOS transistor N 2  becomes lower than a threshold voltage of the NMOS transistor N 1 . Then, if a signal LA of a power voltage VCC level and a signal LAB of a ground voltage VSS level are applied, the same operation as the bit line sense amplifier of  FIG. 10  is performed. 
     FIG. 20  is a view illustrating a circuit of generating signals LA, LAB, LA 1 , LA 2 , LAB 1 , and LAB 2  of  FIG. 19 . The circuit of  FIG. 20  includes a controller  70 , PMOS transistors P 3  and P 10  to P 13 , and NMOS transistors N 5  and N 12  to N 15 . 
   Functions of the components of  FIG. 20  are explained below. 
   The controller  70  generates first and fourth substrate voltage control signals CON 1  and CON 4  of a high level, second and third substrate voltage control signals CON 2  and CON 3  of a low level, fifth and eighth substrate voltage control signals CON 5  and CON 8  of a low level, and sixth and seventh substrate voltage control signals CON 6  and CON 7  of a high level if an active command ACT or a refresh command REF is applied and a 2-bit LSB of row address A 0  and A 1  is applied and so the 2-bit LSB of row address A 0 ,A 1  are “00” or “11”. Here, a low level applied to the NMOS transistor N 13  is a substrate voltage VBB level. The NMOS transistors N 13  and N 14  are turned off and the NMOS transistors N 12  and N 15  are turned on, so that a signal LAB 1  of a higher voltage VBB+α than a substrate voltage VBB and a signal LAB 2  of a substrate voltage VBB level are generated, and the PMOS transistors P 10  and P 13  are turned on and the PMOS transistors P 11  and P 12  are turned off, so that a signal LA 2  of a power voltage VCC level and a signal LA 1  of a lower voltage VCC-β than a power voltage VCC level are generated. 
   On the other hand, the controller  70  generates first and fourth substrate voltage control signals CON 1  and CON 4  of a low level, second and third substrate voltage control signals CON 2  and CON 3  of a high level, fifth and eighth substrate voltage control signals CON 5  and CON 8  of a high level, and sixth and seventh substrate voltage control signals CON 6  and CON 7  of a low level if an active command ACT or a refresh command REF is applied and a 2-bit LSB of row address A 0  and A 1  is applied and so the 2-bit LSB of row address A 0 ,A 1  are “01” or “10”. Here, a low level applied to the NMOS transistor N 15  is a substrate voltage VBB level. The NMOS transistors N 12  and N 15  are turned off and the NMOS transistors N 13  and N 14  are turned on, so that a signal LAB 2  of a higher voltage VBB+α than a substrate voltage VBB and a signal LAB 1  of a substrate voltage VBB level are generated, and the PMOS transistors P 10  and P 13  are turned off and the PMOS transistors P 11  and P 12  are turned on, so that a signal LA 1  of a power voltage VCC level and a signal LA 2  of a lower voltage VCC-β than a power voltage VCC level are generated. 
   Thereafter, first and second bit line sense amplifier enable control signals LAPG and LANG of a low level and a high level are generated. Therefore, the PMOS transistor P 3  generates a signal LA of a power voltage VCC level in response to the first bit line sense amplifier enable control signal LAPG of a low level, and the NMOS transistor N 5  generates a signal LAB of a ground voltage VSS level in response to the second bit line sense amplifier enable control signal LANG of a high level. 
     FIG. 21  is a timing diagram illustrating the refresh operation of the semiconductor memory device of  FIG. 19 . The refresh operation is performed under the same condition as that of  FIG. 3 . 
   Operation during the charge sharing operation period T is the same as the timing diagram of  FIG. 6 . 
   Thereafter, if a signal LA 2  of a power voltage VCC level, a signal LA 1  of a lower voltage VCC-β level than a power voltage VCC level, a signal LAB 1  of a higher voltage VBB+α than a substrate voltage VBB, and a signal LAB 2  of a substrate voltage VBB level are generated and a signal LA of a power voltage VCC level and a signal LAB of a ground voltage VSS level are applied, the same operation as in the timing diagram of  FIG. 12  is performed. 
   Even though not shown, if in state that the memory cell MC 2  stores data of a high level and the array bit line pair ABL 1 ,ABL 1 B and the sense bit line pair SBL 1 ,SBL 1 B are precharged to a precharge voltage VBL level, the refresh command REF is applied so that the sub word line SWL 2  is selected, a signal LA 1  of a power voltage VCC level, a signal LA 2  of a lower voltage VCC-β level than a power voltage VCC level, a signal LAB 1  of a substrate voltage VBB, and a signal LAB 2  of a higher voltage VBB+α than a substrate voltage VBB level are generated, and a signal LA of a power voltage VCC level and a signal LAB of a ground voltage VSS level are applied. 
   The semiconductor memory device of  FIG. 19  has a different configuration but performs the same operation as that of  FIG. 10 . 
   The semiconductor memory device of the present invention described above improves the sensing ability for data of a high level by differentiating the sensing ability of the PMOS transistors which constitute the PMOS sense amplifier and/or the sensing ability of the NMOS transistors which constitute the NMOS sense amplifier. Therefore, it is possible to lengthen a refresh cycle of the semiconductor memory device. 
   The bit line sense amplifier of the semiconductor memory device of the present invention described above improves the sensing ability for data of a high level during the refresh operation and the read operation. 
   Accordingly, as described above, embodiments of the invention include sense amplifiers configured to sense and amplify relatively small differential signals established across a pair of differential sense bit lines. According to one these embodiments, a sense amplifier is provided with multiple MOS sense amplifiers therein. As illustrated by  FIG. 4 , these MOS sense amplifiers include a first NMOS sense amplifier (NSAi, NSAj) having a first pair of NMOS transistors N 6  and N 7  of first conductivity type therein electrically coupled across a pair of sense bit lines SBL 1  and SBL 1 B. This first pair of NMOS transistors N 6  and N 7  are configured to have different threshold voltages so that enhanced sensing of relatively small differential voltages on the sense bit lines can be achieved. Alternatively, as illustrated by  FIG. 13 , a first pair of NMOS transistors N 1  and N 2  may support different threshold voltage biasing. This different threshold voltage biasing may be achieved by independently controlling the level at which the substrate terminals of these NMOS transistors are biased during a sense and amplify operation. These MOS sense amplifiers may also include a second MOS sense amplifier PSA (PSAi in  FIG. 13 ) having a first pair of PMOS transistors P 1  and P 2  therein electrically coupled across the pair of sense bit lines SBL 1  and SBL 1 B. 
   Referring again to  FIG. 4 , the first MOS sense amplifier may also includes a second pair of NMOS transistors N 8  and N 9  electrically coupled across the pair of sense bit lines SBL 1  and SBL 1 B. This second pair of MOS transistors N 8  and N 9  is configured to have different threshold voltages as well. Similarly, as illustrated by  FIG. 7 , a first pair of PMOS transistors P 6  and P 7  can be configured to have different threshold voltages or, as illustrated by  FIG. 16 , the first pair of PMOS transistors P 1  and P 2  can support different threshold voltage biasing. 
   Referring again to  FIG. 13 , a first NMOS sense amplifier NSAi has a pair of NMOS transistors N 1  and N 2 . First, second and third sense amplifier enable lines LAB, LAB 1  and LAB 2  are also provided. The first sense amplifier enable line LAB is electrically coupled to source terminals of the pair of NMOS transistors N 1  and N 2 . However, to support different threshold voltage biasing, the second sense amplifier enable line LAB 1  is electrically coupled to a substrate terminal of NMOS transistor N 1  and the third sense amplifier enable line LAB 2  is electrically coupled to a substrate terminal of NMOS transistor N 2 . As illustrated by  FIGS. 14-15 , controller/driver is also provided. This controller is configured to independently drive the first, second and third sense amplifier enable lines during an operation to amplify a differential voltage established across the pair of sense bit lines. 
   As described herein before, the semiconductor memory device and the bit line sensing method according to the present invention can lengthen the refresh cycle by improving the sensing ability of data of a high level, thereby reducing power consumption of the refresh operation. 
   In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.