Patent Publication Number: US-2020302027-A1

Title: Simulation method and simulation device for semiconductor storage device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-050498, filed on Mar. 18, 2019; the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a simulation method and simulation device for a semiconductor storage device. 
     BACKGROUND 
     Conventionally, a test is performed to evaluate whether or not a controller that controls a semiconductor storage device operates according to the specification under actual use conditions at a stage of designing or manufacturing the controller. When a failure occurs in the controller in such a test, the controller is reformed, and then, confirmation on whether or not the failure has been resolved or the like is performed. At the time of confirming whether or not the failure has been resolved, it is required to reproduce a behavior when the failure has occurred by the semiconductor storage device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating an example when a simulation device of a first embodiment is used in a learning mode; 
         FIG. 2  is a diagram illustrating an example of a configuration of a memory chip in the first embodiment; 
         FIG. 3  is a circuit diagram illustrating a configuration example of one block included in a memory cell array in the first embodiment; 
         FIG. 4  is a diagram illustrating an example when the simulation device of the first embodiment is used in a simulation mode; 
         FIG. 5  is an exemplary and schematic diagram illustrating a specific configuration of the simulation device of the first embodiment; 
         FIG. 6  is an exemplary and schematic diagram illustrating an example of information stored in a storage device provided in the simulation device of the first embodiment; 
         FIG. 7  is a flowchart for explaining an example of a test method in the learning mode using the simulation device of the first embodiment; 
         FIG. 8  is a flowchart for explaining an example of a test method in the simulation mode using the simulation device of the first embodiment; 
         FIG. 9  is a diagram illustrating an example when a simulation device of a second embodiment is used in a learning mode; 
         FIG. 10  is an exemplary and schematic diagram illustrating information stored in a storage device provided in the simulation device of the second embodiment; 
         FIG. 11  is a diagram illustrating an example when the simulation device of the second embodiment is used in a simulation mode; 
         FIG. 12  is an exemplary and schematic diagram illustrating a specific configuration of the simulation device of the second embodiment; 
         FIG. 13  is a flowchart for explaining an example of a test method in the learning mode using the simulation device of the second embodiment; and 
         FIG. 14  is a flowchart for explaining an example of a test method in the simulation mode using the simulation device of the second embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     According to the present embodiment, a simulation method is a simulation method of a simulation device that simulates a semiconductor storage device connected to a first controller via a first communication channel. The simulation method includes: receiving first data from a portion of the first communication channel; receiving second data from the portion; and simulating a response of the semiconductor storage device based on first information. The first data is data which has been transferred from the first controller to the semiconductor storage device and of which writing is requested from the first controller. The second data is data which has been stored in the semiconductor storage device, and transferred from the semiconductor storage device to the first controller, and of which reading is requested from the first controller. The first information indicates a feature of the semiconductor storage device obtained based on comparison between the first data and the second data. 
     Hereinafter, the simulation method and the simulation device for the semiconductor storage device according to embodiments will be described in detail with reference to the attached drawings. Incidentally, the present invention is not limited to these embodiments. 
     First Embodiment 
     A simulation device according to a first embodiment can operate in two modes of a learning mode of learning a feature of a semiconductor storage device and a simulation mode of simulating a behavior of the semiconductor storage device based on the learned feature. 
       FIG. 1  is a diagram illustrating an example when a simulation device of a first embodiment is used in a learning mode. As illustrated in  FIG. 1 , a host  210   a , a controller  220   a , and a memory chip  230   a  constitute a test device  200   a  configured to evaluate whether or not the controller  220   a  operates according to the specification even under actual use conditions. 
     Here, the memory chip  230   a  is assumed to be a memory chip of a NAND flash memory as an example. Incidentally, the memory chip  230   a  is an example of the semiconductor storage device. 
     The controller  220   a  and the memory chip  230   a  are connected by a communication channel  240   a . The communication channel  240   a  is an example of a first communication channel. 
     The communication channel  240   a  comprises a wiring group including an IO signal line and a control signal line. The  10  signal line is a signal line configured to transmit and receive data, an address, and a command. The control signal line is, for example, a signal line configured to transmit and receive a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, a command latch enable (CLE) signal, an address latch enable (ALE) signal, a write protect (WP) signal, a data strobe (DQS) signal, a ready/busy (Ry/By) signal, and the like. 
     The controller  220   a  is an electronic component that can constitute a memory system together with the memory chip  230   a . The controller  220   a  may be configured using a hardware circuit or may include a processor that executes a program such as firmware. Further, the controller  220   a  may also include a storage device such as a register, a flip-flop, and a memory. The controller  220   a  can execute access to the memory chip  230   a  in the memory system based on a request from an external device of the memory system. Examples of the external device include a server computer, a personal computer, a central processing unit (CPU), a portable information terminal, and the like. Examples of the request include a request for storing data, a request for reading data, and a request for erasing data. Incidentally, the controller  220   a  is an example of a first controller. 
     The host  210   a  operates as the external device. That is, the host  210   a  can transmit various requests to the controller  220   a . Here, the host  210   a  sequentially transmits the requests to the controller  220   a  according to a procedure prepared in advance to test the operation of the controller  220   a . The procedure is described in, for example, a program. The host  210   a  is, for example, a processor, and transmits the requests to the controller  220   a  according to the procedure described in the program. Incidentally, the host  210   a  may be configured using a hardware circuit that does not require a program. 
     The controller  220   a  executes access to the memory chip  230   a  based on a request from the host  210   a  or the like. Specifically, the access by the controller  220   a  includes transmission of a write command for writing data to the memory chip  230   a  together with the data, transmission of a read command for reading data from the memory chip  230   a , and reception of data output in response to the read command from the memory chip  230   a . The write command and the read command include an address (physical address) indicating an access destination. 
     Hereinafter, data transferred from the controller  220   a  to the memory chip  230   a  will be referred to as write data in some cases. Further, data transferred from the memory chip  230   a  to the controller  220   a  will be referred to as read data in some cases. 
       FIG. 2  is a diagram illustrating an example of a configuration of the memory chip  230   a  in the first embodiment. The memory chip  230   a  includes a control circuit  231  and a memory cell array  232 . The control circuit  231  executes access to memory cell array  232  based on a command from controller  220   a . The access to the memory cell array  232  includes a program process of programming data into a memory cell MT, a read process of reading the data programmed in the memory cell MT, and an erase process of erasing the data programmed in the memory cell MT. 
     The memory cell array  232  includes a plurality of blocks. Pieces of data stored in the respective blocks are collectively erased. Each of the blocks includes a plurality of pages. Each of the pages is the minimum unit in which the program process or the read process is performed. 
       FIG. 3  is a circuit diagram illustrating a configuration example of one block included in the memory cell array  232  in the first embodiment. As illustrated in  FIG. 3 , each block includes (p+1) NAND strings arrayed in order along the X direction (p≥0). Select transistors ST 1  included in the (p+1) NAND strings have drains connected to the bit lines BL 0  to BLp, respectively, and gates commonly connected to a select gate line SGD. Further, selection transistors ST 2  have sources commonly connected to a source line SL, and gates commonly connected to a select gate line SGS. 
     Each of the memory cells MT is configured using a metal oxide semiconductor field effect transistor (MOSFET) having a stacked gate structure formed on a semiconductor substrate. The stacked gate structure includes a floating gate formed on the semiconductor substrate with a tunnel oxide film interposed therebetween, and a control gate electrode formed above the floating gate with an inter-gate insulating film interposed therebetween. A threshold voltage changes depending on the number of electrons stored in the floating gate. The memory cell MT stores data depending on a difference in threshold voltage. That is, the memory cell MT holds electric charges, the number of which corresponds to the data, in the floating gate. 
     In each NAND string, (q+1) memory cells MT are arranged such that current paths thereof are connected in series between the source of the select transistor ST 1  and the drain of the select transistor ST 2 . Then, the control gate electrodes are connected to word lines WL 0  to WLq in order from the memory cell MT positioned closest to the drain side. Therefore, a drain of the memory cell MT connected to the word line WL 0  is connected to the source of the select transistor ST 1 , and a source of the memory cell MT connected to the word line WLq is connected to the drain of the select transistor ST 2 . 
     Each of the word lines WL 0  to WLq connect the control gate electrodes of the memory cells MT in common between the NAND strings inside the block. That is, the control gate electrodes of the memory cells MT in the same row inside the block are connected to the same word line WL. When each of the memory cells MT is configured to be capable of holding a 1-bit value, (p+1) memory cells MT connected to the same word line WL are handled as one page, and the program process and the read process are performed for each of the pages. 
     Incidentally, each of the memory cells MT can store data of a plurality of bits. For example, when each of the memory cells MT can store data of n (n≥2) bits, a storage capacity per word line is equal to the size of n pages. 
     The control circuit  231  sets a threshold voltage of the memory cell MT of a page to be programmed to a level corresponding to data in the program process. Further, in the read process, the control circuit  231  compares the threshold voltage of the memory cell MT of the page to be read with a predetermined determination voltage to decode the level of the threshold voltage to data. Further, in the erase process, the control circuit  231  sets threshold voltages of all the memory cells MT included in a block to be erased to a predetermined level corresponding to an erased state. 
     The description will be given with reference to  FIG. 1  again. The threshold voltage of each of the memory cells MT may vary due to various factors. Therefore, there may occur an error in which a data value, different from a data value programmed in a memory cell MT, is read from the memory cell MT. The data value garbled by the error is detected in the controller  220   a , and corrected to a correct data value. 
     That is, the controller  220   a  has an error detection and correction function of detecting and correcting an error included in read data. The controller  220   a  performs encoding for error correction on data, and transmits the encoded data as write data to the memory chip  230   a . Further, when the controller  220   a  receives read data, the controller  220   a  decodes the read data to execute detection and correction of an error included in the read data. If the error correction is successful, the controller  220   a  can acquire data in the same state as that of the data before being subjected to encoding. 
     Incidentally, the controller  220   a  can execute a refresh process, a wear leveling process, or a garbage collection process in addition to the operation in response to the request from the host  210   a  although the detailed description thereof is omitted here. The controller  220   a  autonomously executes these processes without the request from the host  210   a . Even in these processes, the controller  220   a  can execute access to the memory chip  230   a.    
     In the first embodiment, the communication channel  240   a  is provided with a branch portion  250  that divides the communication channel  240   a . A branch destination generated by the branch portion  250  is connected to a simulation device  100 . Accordingly, the simulation device  100  can receive various signals, transferred between the controller  220   a  and the memory chip  230   a , via the branch portion  250 . In the learning mode, the simulation device  100  can learn features of the memory chip  230   a  based on the various signals transferred between the controller  220   a  and the memory chip  230   a.    
     The features include a feature relating to an error. In the first embodiment, an error rate and an error pattern are regarded as the features as an example. 
     The error rate is a ratio between the number of pieces of normal bit data or the number of pieces of bit data constituting unit data and the number of pieces of bit data garbled by an error. The unit data is, for example, data of a page size. Incidentally, the definition of the error rate is not limited thereto. Any quantity may be defined as the error rate as long as the quantity corresponds to a ratio or the amount of bit data garbled by an error included in data of a predetermined size. 
     The error pattern is information indicating an appearance tendency of an error. In one example, the error pattern indicates a portion of a word line where an error is likely to occur. 
     The learned feature is recorded as feature information (see  FIG. 6 ). After the feature information is obtained, the simulation device  100  may be used in the simulation mode. 
       FIG. 4  is a diagram illustrating an example when the simulation device  100  of the first embodiment is used in the simulation mode. As illustrated in  FIG. 4 , a host  210   b , a controller  220   b , and the simulation device  100  constitute a test device  200   b  configured to evaluate whether or not the controller  220   b  operates according to the specification even under actual use conditions. 
     The host  210   b  performs the same operation as that of the host  210   a . The controller  220   b  may be the same as the controller  220   a  or may be a controller different from the controller  220   a . The controller  220   b  may be a controller that has been reformed to cope with a failure that has occurred. The controller  220   b  is an example of a second controller. 
     The controller  220   b  and the simulation device  100  are connected by a communication channel  240   b . The communication channel  240   b  is an example of a second communication channel. 
     The communication channel  240   b  is configured using the same wiring group as that of the communication channel  240   a . That is, for example, the communication channel  240   b  includes an IC signal line and a control signal line. The control signal line is, for example, a signal line configured to transmit and receive a CE signal, a WE signal, a RE signal, a CLE signal, an ALE signal, a WP signal, a DQS signal, a Ry/By signal, and the like. 
     In the simulation mode, the simulation device  100  performs an operation simulating a behavior of the memory chip  230   a  according to the feature information. For example, when receiving a write command from the controller  220   b , the simulation device  100  stores write data, which has been transmitted together with the write command, in a storage device  106  provided therein. Thereafter, when receiving a read command, which requests reading of the write data already stored in the storage device  106 , from the controller  220   b , the simulation device  100  reads the write data from the storage device  106 , process the read write data based on the feature information, and transmits the processed write data to the controller  220   b  as read data. 
     Here, the processing is generating an error in data in one example. That is, the simulation device  100  generates an error in data, received as write data from the controller  220   b , and outputs the data including the error as read data. The error is generated in accordance with the learned feature of the memory chip  230   a . Thus, the simulation device  100  can operate as a pseudo memory chip having the same feature as that of the memory chip  230   a.    
     Incidentally, a method of the processing is not limited to the above method. The simulation device  100  can perform various types of processing on write data and transmit the processed write data as read data. 
     According to a technique to be compared with the embodiment, when a failure occurs in a controller during a test, a retest is executed to elucidate the failure or to confirm that the reformed controller has resolved the failure. Here, even in a case where a plurality of memory chips are manufactured in the same manufacturing process, features vary among the plurality of memory chips due to manufacturing variations and the like. In order to equalize conditions relating to the features of the memory chips between the case of a test where a failure has occurred and the case of a retest, the memory chip used in the test where the failure has occurs is used in the retest. Therefore, when it is desired to execute the retest a plurality of times, the total time required for the retests becomes longer according to the number of retests. Hereinafter, the technique to be compared with the embodiment will be referred to as a technique according to a comparative example. 
     In the first embodiment, the simulation device  100  learns the feature of the memory chip  230   a  in the learning mode, and operates as the pseudo memory chip having the same feature as that of the memory chip  230   a  in the simulation mode. Accordingly, if the simulation device  100  is used in the learning mode in the first test and the simulation device  100  is used in the simulation mode when a failure occurs in the controller  220   a , it is possible to eliminate the need for the memory chip  230   a  in the retest. 
     Further, for example, if a plurality of the simulation devices  100  are prepared and the same feature information is set to each of the plurality of simulation devices  100 , all of the plurality of simulation devices  100  operate as pseudo memory chips having the same feature as that of the memory chip  230   a . That is, when each of the plurality of simulation devices  100  is connected to each of a plurality of test devices  100   b  and used, it is possible to execute a plurality of retests in parallel. As a result, it is possible to significantly reduce the total time required for the retest as compared with the technique according to the comparative example. 
     Subsequently, a specific configuration of the simulation device  100  according to the first embodiment will be described.  FIG. 5  is an exemplary and schematic diagram illustrating a specific configuration of the simulation device  100  of the first embodiment. 
     The simulation device  100  includes an interface  101 , a command analysis device  102 , a response analysis device  103 , a response device  104 , an error analysis device  105 , and a storage device  106 . The response device  104  includes an error generation device  107 . The interface  101 , the command analysis device  102 , the response analysis device  103 , the response device  104 , and the error analysis device  105  are examples of a processing device. 
     Some or all of the command analysis device  102 , the response analysis device  103 , the response device  104 , and the error analysis device  105  may be configured using a hardware circuit that does not require a program or may be configured using a processor that operates based on a program. Further, some or all of the devices (the interface  101 , the command analysis device  102 , the response analysis device  103 , the response device  104 , the error analysis device  105 , and the storage device  106 ) provided in the simulation device  100  may be configured using a field-programmable gate array (FPGA) or an application specific integrated circuit (ASIC). 
     The interface  101  is hardware configured for connection to the communication channel  240   a  and the communication channel  240   b . The interface  101  may include a physical terminal and a buffer that receives a signal. 
     The command analysis device  102  is a device that analyzes signals output by the controller  220   a  and the controller  220   b . The command analysis device  102  can extract at least a write command, a read command, a physical address, and write data from the signals output by the controller  220   a  and the controller  220   b.    
     The response analysis device  103  is a device that analyzes a signal output from the memory chip  230   a  in the learning mode. The response analysis device  103  can extract at least read data from the signal output from the memory chip  230   a.    
     The response device  104  can generate a response to a command from the controller  220   b  and transmit the generated response to the controller  220   b  in the simulation mode. 
     When the response device  104  transmits data corresponding to read data to the controller  220   b , the error generation device  107  generates an error in the data. As a result, the response device  104  can transmit the data including the generated error to the controller  220   b  as the read data. 
     The error analysis device  105  receives feature information based on comparison between write data and read data in the learning mode. That is, the error analysis device  105  specifies a data bit different between the write data and the read data as an error, and calculates an error rate and an error pattern based on the number and a position of the specified error. Then, the error analysis device  105  records the calculated error rate and error pattern as the feature information. 
     The storage device  106  is configured using a register, a static random access memory (SRAM), a dynamic access memory (DRAM), a flash memory, a hard disk drive, or a combination thereof. The storage device  106  stores write data, feature information, and the like. 
       FIG. 6  is an exemplary and schematic diagram illustrating an example of information stored in the storage device  106  provided in the simulation device  100  of the first embodiment. The storage device  106  stores page information  10  corresponding to each of all the pages included in the memory cell array  232 . 
     One piece of the page information  10  includes write data written to the corresponding page and feature information regarding the corresponding page. That is, the feature information is calculated and recorded for each page according to this example. The feature information includes the error rate and the error pattern as described above. 
     Incidentally, the feature information may include arbitrary information in addition to the error rate and the error pattern. For example, the feature information may include voltage information, temperature information, a storage mode, time information, and the like. The voltage information is, for example, a voltage value used by the control circuit  231  during access (the program process or the read process) to the corresponding page, such as a determination voltage for determining the threshold voltage of the memory cell MT. The temperature information is temperature of peripheral environment of the memory chip  230   a  or the memory chip  230   a  during the access (the program process or the read process) to the corresponding page. The storage mode is information indicating the amount of data to be stored in one memory cell MT. The time information is information indicating the time when the access (the program process or the read process) to the corresponding page has been executed. 
     Further, a data configuration of a group of the page information  10  is not limited to a specific configuration. For example, the group of page information  10  may constitute one table or may constitute one list. Further, the page information  10  for all the pages is not necessarily stored in the storage device  106 . For example, the page information  10  regarding a page to which write data is not written is not necessarily stored in the storage device  106  in the learning mode. Further, the page information  10  regarding a page for which read has not been performed and thus acquisition of feature information has failed is not necessarily stored in the storage device  106  in the learning mode. 
     Further, in each of pieces of the page information  10 , write data may be recorded in an overwrite format or write data may be added in a log format whenever the program process is performed on the corresponding page. Similarly, the feature information may be recorded in overwrite format or may be added in a log format whenever access to the corresponding page is executed. 
     Subsequently, a series of operations using the simulation device  100  of the first embodiment will be described.  FIG. 7  is a flowchart for explaining an example of a test method in the learning mode using the simulation device  100  of the first embodiment. 
     When the simulation device  100  is used in the learning mode, the simulation device  100  is connected to the branch portion  250  provided in the communication channel  240   a  that connects the controller  220   a  and the memory chip  230   a  as illustrated in  FIG. 1 . 
     Then, when a test is started (S 101 ), the host  210   a  sends various requests to the controller  220   a  in a predetermined procedure, and the controller  220   a  accesses the memory chip  230   a  based on the request. Further, the controller  220   a  executes a refresh process, a wear leveling process, a garbage collection process, and the like, and autonomously accesses the memory chip  230   a  during these processes. 
     In the simulation device  100 , the interface  101  receives a signal transferred between the controller  220   a  and the memory chip  230   a  via the branch portion  250 . Then, the command analysis device  102  and the response analysis device  103  analyze a signal received by the interface  101 . 
     For example, when the write command has been transferred (S 102 : Yes), the command analysis device  102  detects the write command, and receives a physical address and write data transferred through the communication channel  240   a  together with the write command (S 103 ). Then, the command analysis device  102  records the received write data in the page information  10  corresponding to a page indicated by the received address (S 104 ). 
     The command analysis device  102  may record arbitrary information when recording the write data. For example, the command analysis device  102  may receive temperature information using a temperature sensor (not illustrated), and record the received temperature information as a part of feature information. Further, when recording the write data, the command analysis device  102  may receive time information from a timer (not illustrated) and record the received time information as a part of feature information. 
     Moreover, when not a write command but a read command has been transferred (S 102 : No, and S 105 : Yes), the command analysis device  102  detects the read command and receives a physical address transferred together with the read command (S 106 ). Further, the response analysis device  103  receives read data, transferred from the memory chip  230   a  to the controller  220   a , in response to the transferred read command (S 107 ). 
     Subsequently, the error analysis device  105  receives write data from the page information  10  regarding a page indicated by the address received by the process of S 106  (S 108 ). Then, the error analysis device  105  receives feature information based on comparison between the read data received by the process of S 107  and the write data received by the process of S 108  (S 109 ). That is, the error analysis device  105  calculates an error rate and an error pattern in S 109 . The error analysis device  105  records the feature information received by calculation in the page information  10  regarding the page indicated by the address received by the process of S 106  (S 110 ). 
     Incidentally, the error analysis device  105  may record arbitrary information at the time of acquiring the read data. For example, the error analysis device  105  may receive temperature information using a temperature sensor (not illustrated), and record the received temperature information as a part of the feature information. Further, when the read data has been received, the error analysis device  105  may receive time information from a timer (not illustrated) and record the received time information as a part of the feature information. 
     In this manner, when the write command has been transferred, the simulation device  100  operating in the learning mode receives the write data and stores the received write data into the storage device  106  during the test. Further, when the read command has been transferred, the simulation device  100  receives the read data, receives the feature information based on the comparison between the write data stored in the storage device  106  and the read data, and records the received feature information. As these operations are repeatedly executed, the write data is written, and then, feature information regarding all pages from which the data has been read is accumulated in the storage device  106 . That is, the features of the memory chip  230   a  are learned. 
     When a set feature command has been transferred instead of a write command and a read command (S 102 : No, S 105 : No, and S 111 : Yes), the command analysis device  102  detects the set feature command and receives a feature set by the set feature command (S 112 ). Then, the command analysis device  102  records the received feature into the storage device  106  (S 113 ). 
     The set feature command is a command to set various features to a memory chip. For example, a determination voltage can be set by the set feature command. 
     The read command includes a read command to perform read using a standard determination voltage, and a read command to perform read using the determination voltage set by the set feature command. In general, the read using the standard determination voltage is performed, but a search for a determination voltage to correctly read data is performed when an error rate of data inside a block BLK becomes low. A voltage value of the determination voltage obtained by the search is set by the set feature command, and read of data inside the corresponding block is executed using the determination voltage set by the set feature command. 
     When a set value of the determination voltage has been transferred by the set feature command, the command analysis device  102  records the set value into the storage device  106 . The set value of the determination voltage is recorded, for example, in association with the block BLK. 
     There is a case where a failure occurs in the controller  220   a  during the test. For example, after S 113  or after it is determined as No in the determination process of S 111 , it is determined whether or not a failure has occurred in the controller  220   a  (S 114 ). If the failure has occur in the controller  220   a  (S 114 : Yes), the test is stopped (S 115 ). Then, the test using the simulation device  100  in the learning mode ends. For example, when detecting that the controller  220   a  does not execute an intended operation, the host  210   a  can determine that a failure has occurred and stop the test. Incidentally, a method of detecting the occurrence of the failure and a method of stopping the test are not limited to the above methods. An arbitrary device can detect the occurrence of the failure and stop the test in an arbitrary method. 
     Further, when the host  210   a  finishes a series of procedures for the test without causing a failure in the controller  220   a  (S 114 : No, and S 116 : Yes), the test using the simulation device  100  in the learning mode ends. If there still remains a procedure (S 116 : No), the control shifts to S 102 . 
       FIG. 8  is a flowchart for explaining an example of a test method in the simulation mode using the simulation device  100  of the first embodiment. 
     When the simulation device  100  is used in the simulation mode, the simulation device  100  is connected to the controller  220   b  via the communication channel  240   b  as illustrated in  FIG. 4 . When a test is started (S 201 ), the host  210   b  sends various requests to the controller  220   b  according to a predetermined procedure similarly to the host  210   a  in the learning mode. The controller  220   b  regards the simulation device  100  as a memory chip and executes access to the simulation device  100 . That is, the controller  220   b  transmits various commands to the simulation device  100  and receives various responses from the simulation device  100 . Further, the controller  220   b  executes a refresh process, a wear leveling process, a garbage collection process, and the like, and autonomously accesses the simulation device  100  even in these processes. 
     In the simulation device  100 , the interface  101  receives a signal transmitted from the controller  220   b . Then, the command analysis device  102  and the response analysis device  103  analyze the signal received by the interface  101 . 
     For example, when the write command has been received (S 202 : Yes), the command analysis device  102  detects the write command, and receives a physical address and write data transferred through the communication channel  240   b  together with the write command (S 203 ). Then, the command analysis device  102  records the received write data into the page information  10  corresponding to a page indicated by the received address (S 204 ). 
     Moreover, when not a write command but a read command has been received (S 202 : No and S 205 : Yes), the command analysis device  102  detects the read command and receives a physical address transferred together with the read command (S 206 ). Then, the response device  104  receives the write data and feature information from the page information  10  regarding a page indicated by the address received by the process of S 206  (S 207 ). 
     The error generation device  107  generates an error in the write data based on the feature information (S 208 ). For example, the error generation device  107  bit-inverts the pieces of bit data, the number of which corresponds to an error rate out of a string of pieces of bit data of the write data. A position of bit data to be bit-inverted is set to a position based on an error pattern. As a result, data whose feature regarding an error is similar to the feature of the read data output from the memory chip  230   a  in the learning mode is generated. 
     The response device  104  transmits the write data including the error to the controller  220   b  as read data (S 209 ). As a result, a response simulating a behavior of the memory chip  230   a  is executed. Incidentally, the transmission of read data is executed via the interface  101 . 
     Further, when the set feature command is received instead of a write command and a read command (S 202 : No, S 205 : No, and S 210 : Yes), the command analysis device  102  detects the set feature command and receives a feature set by the set feature command, that is, a set value of a determination voltage (S 211 ). Then, the command analysis device  102  records the received feature, that is, the set value of the determination voltage into the storage device  106  (S 212 ). When responding to a read command received thereafter, read data corresponding to the determination voltage set by the set feature command is output. 
     For example, after S 212  or after it is determined as No in the determination process of S 210 , it is determined whether or not a failure has occurred in the controller  220   b  (S 213 ). If the failure has occur in the controller  220   b  (S 213 : Yes), the test is stopped (S 214 ). Then, the test using the simulation device  100  in the simulation mode ends. For example, when detecting that the controller  220   b  does not execute an intended operation, the host  210   b  can determine that a failure has occurred and stop the test. Incidentally, a method of detecting the occurrence of the failure and a method of stopping the test are not limited to the above methods. An arbitrary device can detect the occurrence of the failure and stop the test in an arbitrary method. 
     Further, when the host  210   b  finishes a series of procedures for the test without causing a failure in the controller  220   b  (S 213 : No, and S 215 : Yes), the test using the simulation device  100  in the simulation mode ends. If there still remains a procedure (S 215 : No), the control shifts, to S 202 , for example. 
     Incidentally, the description has been given regarding the example in which the simulation device  100  operates in the learning mode to receive the feature information and store the received feature information into the storage device  106 , and then, simulates the behavior of the memory chip  230   a  using the feature information stored in the storage device  106  at the time of operating in the simulation mode, in the description of  FIGS. 7 and 8 . The simulation device  100  operating in the simulation mode may be a device different from the simulation device  100  operating in the learning mode. For example, when a copy of the feature information received by the simulation device  100  operating in the learning mode is stored in the storage device  106  of the simulation device  100  operating in the simulation mode, the simulation device  100  operating in the simulation mode can simulate the behavior of the memory chip  230   a.    
     Further, a plurality of the simulation devices  100  operating in the simulation mode may be provided. The plurality of simulation devices  100  operating in the simulation mode can respectively simulate the behavior of the memory chip  230   a , and thus, can execute a plurality of tests in parallel. 
     Further, the simulation device  100  according to the first embodiment may be constituted by a first device operating only in the learning mode and a second device operating only in the simulation mode. In such a case, the first device can be configured such that the response device  104  is eliminated from the configuration of the simulation device  100  illustrated in  FIG. 5 . Further, the second device can be configured such that the response analysis device  103  is eliminated from the configuration of the simulation device  100  illustrated in  FIG. 5 . 
     Further, the description has been given assuming that the feature information is recorded for each page in the above description. The feature information may be recorded for each unit different from the page. For example, the feature information may be recorded for each block. 
     Incidentally, when the feature information is recorded for each block, for example, the feature information may be received in an arbitrary method. In one example, a representative page is set in advance for each block, and feature information regarding the representative page is regarded as feature information of a block including the representative page. In another example, for each block, feature information of a page for which read was executed last is regarded as feature information of a block including the page. 
     In this manner, the simulation device  100  receives the write data, which is transferred from the controller  220   a  to the memory chip  230   a  and of which writing is requested from the controller  220   a , from the branch portion  250  provided in the communication channel  240   a  that connects the controller  220   a  and the memory chip  230   a  according to the first embodiment. Thereafter, the simulation device  100  receives the read data that is write data which is transferred from the memory chip  230   a  to the controller  220   a  and of which reading is requested from the controller  220   a , from the branch portion  250 . Then, the simulation device  100  receives the feature information indicating the feature of the memory chip  230   a  based on the comparison between the write data and the read data. The simulation device  100  simulates the response of the memory chip  230   a  based on the feature information. With the above configuration, it is possible to simulate the behavior of the memory chip  230   a.    
     Further, the feature information includes the information on the error according to the first embodiment. With the above configuration, the simulation device  100  can respond to the read data having the same feature as that of the read data output from the memory chip  230   a  in terms of the error. 
     Further, the simulation device  100  receives the write data of which writing is requested from the controller  220   b  via the communication channel  240   b  that connects the controller  220   b  and the simulation device  100  according to the first embodiment. The simulation device  100  stores the received write data into the storage device  106 . Then, the simulation device  100  reads the write data from the storage device  106  in response to the command to read the write data, that is, the read command and processes the write data based on the feature information. Then, the simulation device  100  transmits the processed write data as the read data to the controller  220   b  via the communication channel  240   b . With the above configuration, it is possible to simulate the behavior of the memory chip  230   a.    
     Further, the feature information includes the information on the error according to the first embodiment. The simulation device  100  generates the error in the write data based on the information on the error recorded as the feature information. With the above configuration, the simulation device  100  can output data having the same feature as that of the read data output from the memory chip  230   a  in terms of the error in response to the read command. 
     Further, the memory chip  230   a  includes the plurality of pages, and the simulation device  100  receives the feature information for each page according to the first embodiment. 
     Incidentally, the simulation device  100  may be configured to receive the feature information for each unit different from the page. For example, the simulation device  100  may receive the feature information for each block. 
     Second Embodiment 
     When a procedure of a test executed by a host includes a plurality of processes, there is a case where an operator desires to re-execute the test from an arbitrary timing of the plurality of processes. In a second embodiment, the simulation device  100 , which enables re-execution of a test from an arbitrary timing, will be described. 
     Hereinafter, the simulation device  100  according to the second embodiment is referred to as a simulation device  100   a . The same components as those in the first embodiment among components included in the simulation device  100   a  will be denoted by the same names and reference signs as those of the first embodiment. Then, the same components as those of the first embodiment will not be described or will be briefly described. 
       FIG. 9  is a diagram illustrating an example when the simulation device  100   a  of the second embodiment is used in a learning mode. A host  210   c , a controller  220   c , and the memory chip  230   a  constitute a test device  200   c  configured to evaluate whether or not the controller  220   c  operates according to the specification even under actual use conditions. 
     The controller  220   c  is an electronic component that can constitute a memory system together with the memory chip  230   a . The controller  220   c  can perform, for example, the same operation as that of the controller  220   a . The controller  220   c  is another example of the first controller. 
     The controller  220   c  is connected to the memory chip  230   a  via the communication channel  240   a . The branch portion  250  that divides the communication channel  240   a  is provided. A branch destination generated by the branch portion  250  is connected to a simulation device  100   a . Accordingly, the simulation device  100   a  can receive various signals, transferred between the controller  220   c  and the memory chip  230   a , via the branch portion  250 . In the learning mode, the simulation device  100   a  can learn features of the memory chip  230   a  based on the various signals transferred between the controller  220   c  and the memory chip  230   a.    
     The simulation device  100   a  is further connected to the host  210   c  via a communication channel  300 . Further, the simulation device  100   a  is connected to the controller  220   c  via a communication channel  310 . The communication channel  300  is an example of a third communication channel. 
     The host  210   c  operates as an external device with respect to the memory system. That is, the host  210   c  can transmit various requests to the controller  220   c  similarly to the host  210   a . Here, the host  210   c  sequentially transmits the requests to the controller  220   c  according to a procedure set in advance to test the operation of the controller  220   c . The procedure is described using, for example, a program. The host  210   c  is, for example, a processor, and transmits the requests to the controller  220   c  according to the procedure described using the program. Incidentally, the host  210   c  may be configured using a hardware circuit that does not require a program. 
     Further, the host  210   c  can transmit a snapshot instruction to the simulation device  100   a  via the communication channel  300  once or more at different timings. For example, if the test procedure includes a plurality of processes to be executed consecutively, the host  210   c  can transmit the snapshot instruction to the simulation device  100   a  whenever each process is completed. Incidentally, the timing to transmit the snapshot instruction is not limited thereto. The snapshot instruction is an example of a first instruction. 
     When receiving the snapshot instruction, the simulation device  100   a  stores feature information and internal state information of the controller  220   c  in the storage device  106  provided therein. 
     Here, the internal state information of the controller  220   c  is information indicating a state of the storage device  221  provided in the controller  220   c . The storage device provided in the controller  220   c  includes a register, a flip-flop, and a memory. When the controller  220   c  includes a processor, the storage device provided in the controller  220   c  includes a register in the processor. The simulation device  100   a  receives content of the storage device  221  as the internal state information via the communication channel  310 , and stores the received internal state information into the storage device  106  in association with the feature information (feature information group) of all pages. Such a pair of the internal state information and the feature information group is referred to as snapshot information. 
       FIG. 10  is an exemplary and schematic diagram illustrating information stored in the storage device  106  provided in the simulation device  100   a  of the second embodiment. The storage device  106  stores the page information  10  corresponding to each of all the pages included in the memory cell array  232 , and one or more pieces of snapshot information  20 . 
     Each of the one or more pieces of snapshot information  20  is stored in response to the snapshot instruction, and is constituted by a pair of internal state information and a feature information group. The internal state information included in the snapshot information  20  is the internal state information received in response to the reception of the snapshot instruction. The feature information group is feature information for all pages collected from all pieces of the page information  10  in response to the reception of the snapshot instruction. 
     Incidentally, each of pieces of the snapshot information  20  may include information to specify each of pieces of the snapshot information  20  such as time information indicating a generated or stored time. Each of pieces of the snapshot information  20  may include an ID as the information to specify each of pieces of the snapshot information  20 . The ID may be designated from the host  210   c  by the snapshot instruction or may be generated by the simulation device  100   a . The ID may be a process number designated by the host  210   c . The process number is, for example, a unique number assigned to each of the plurality of processes included in the test procedure. 
       FIG. 11  is a diagram illustrating an example when the simulation device  100   a  of the second embodiment is used in a simulation mode. As illustrated in  FIG. 11 , a host  210   d , a controller  220   d , and the simulation device  100   a  constitute a test device  200   d  configured to evaluate whether or not the controller  220   d  operates according to the specification even under actual use conditions. 
     The host  210   d  performs the same operation as that of the host  210   c . The controller  220   d  may be the same as the controller  220   c  or may be a controller different from the controller  220   c . The controller  220   d  may be a controller that has been reformed to cope with a failure that has occurred. The controller  220   d  is an example of the second controller. 
     The controller  220   d  and the simulation device  100   a  are connected via the communication channel  240   b . The simulation device  100   a  is connected to the host  210   d  via the communication channel  300 . Further, the simulation device  100   a  is connected to the controller  220   d  via the communication channel  310 . 
     When operating in the simulation mode, the simulation device  100   a  can receive an instruction to specify one piece of the snapshot information  20  from the host  210   d . This instruction is referred to as a designation instruction. The designation instruction is an example of a second instruction. The simulation device  100   a  receives the designation instruction via the communication channel  300 . 
     Incidentally, a data structure of the designation instruction may be arbitrarily configured. Examples of the designation instruction may include an ID, time information, a process number, and the like. 
     The simulation device  100   a  loads a feature information group included in the designated snapshot information  20  among the one or more pieces of snapshot information  20  stored in the storage device  106 . That is, the simulation device  100   a  records each of pieces of the feature information of all the pages included in the feature information group into the corresponding page information  10 . As a result, the simulation device  100   a  can start an operation simulating the feature of the memory chip  230   a  at a time when the designated snapshot information  20  has been generated. 
     Further, the simulation device  100   a  sets the internal state information included in the designated snapshot information  20  in the controller  220   d . That is, the simulation device  100   a  overwrites a storage device  2221 , such as a register, a flip-flop, and a memory, provided in the controller  220   d  with the internal state information. As a result, the controller  220   d  can start the same operation as that of the controller  220   c  at the time when the designated snapshot information  20  has been generated. 
     As the feature information group is loaded and the internal state information is set, the controller  220   d  and the simulation device  100   a  can start the test from the time when the designated snapshot information  20  has been generated. The host  210   d  starts a test from the time when the designated snapshot information  20  has been generated in the test procedure. 
     When the test is started, the simulation device  100   a  performs an operation simulating the behavior of the memory chip  230   a  according to the feature information included in the page information  10 . For example, when receiving a write command from the controller  220   d , the simulation device  100   a  stores write data, which has been transmitted together with the write command, in a storage device  106  provided therein. Thereafter, when receiving a read command from the controller  220   d , the simulation device  100   a  reads write data stored in the storage device  106 , process the read write data based on the feature information included in the page information  10 , and transmits the processed write data to the controller  220   d  as read data. 
     In this manner, the simulation device  100   a  generates the snapshot information  20  at the instructed timing in the learning mode. The snapshot information  20  includes the feature information group in which pieces of the feature information of all the pages are collected and the internal state information of the controller  220   c . Then, the simulation device  100   a  is configured to be capable of designating any one out of the one or more pieces of snapshot information  20  generated at different timings in the simulation mode. As a result, if the host  210   c  transmits the snapshot instruction at a point when it is desired to execute a test again later, the simulation device  100   a  can start the test from such a point. That is, it is possible to execute the test again from an arbitrary timing. 
     Subsequently, a specific configuration of the simulation device  100   a  of the second embodiment will be described.  FIG. 12  is an exemplary and schematic diagram illustrating a specific configuration of the simulation device  100   a  of the second embodiment. 
     The simulation device  100   a  includes the interface  101 , the command analysis device  102 , the response analysis device  103 , the response device  104 , the error analysis device  105 , and the storage device  106 . The response device  104  includes an error generation device  107 . 
     The simulation device  100   a  further includes a second interface  108 , a third interface  109 , and a snapshot control device  110 . 
     The interface  101 , the command analysis device  102 , the response analysis device  103 , the response device  104 , the error analysis device  105 , the second interface  108 , the third interface  109 , and the snapshot control device  110  constitute another example of the processing device. 
     The second interface  108  is hardware configured for connection to the communication channel  300 . The second interface  108  may include a physical unit and a buffer that receives a signal. 
     The third interface  109  is hardware configured for connection to the communication channel  310 . The third interface  109  may include a physical unit and a buffer that receives a signal. 
     The snapshot control device  110  can generate the snapshot information  20  in response to a snapshot instruction and store the snapshot information  20  into the storage device  106 . Further, the snapshot control device  110  can receive internal state information and a feature information group from the snapshot information  20  designated by the designation instruction to set the internal state information in the controller  220   d  and load the feature information group. 
     Incidentally, the snapshot control device  110  may be configured using a hardware circuit that does not require a program or may be configured using a processor that operates based on a program, which is similar to the command analysis device  102 , the response analysis device  103 , the response device  104 , the error analysis device  105 , and the like. Further, the snapshot control device  110  may be configured using an FPGA or an ASIC. 
     Subsequently, a series of operations using the simulation device  100   a  of the second embodiment will be described.  FIG. 13  is a flowchart explaining an example of a test method in the learning mode using the simulation device  100   a  of the second embodiment. 
     When the simulation device  100   a  is used in the learning mode, the simulation device  100   a  is connected to the branch portion  250  provided in the communication channel  240   a  that connects the controller  220   c  and the memory chip  230   a  as illustrated in  FIG. 9 . Further, the simulation device  100   a  is connected to the host  210   c  via the communication channel  300 . Further, the simulation device  100   a  is connected to the controller  220   c  via the communication channel  310 . 
     Then, when a test is started (S 301 ), the same processes as those in S 102  to S 113  of  FIG. 7  are performed in S 302  to S 313 . 
     During the test, when the simulation device  100   a  receives a snapshot instruction (S 314 : Yes), the snapshot control device  110  receives internal state information of the controller  220   c  via the communication channel  310  (S 315 ). Further, the snapshot control device  110  receives feature information from the entire page information  10  (S 316 ). That is, the snapshot control device  110  receives the feature information of all the pages. 
     Then, the snapshot control device  110  records the internal state information received by the process of S 315  and the feature information of all the pages received by the process of S 316  as the snapshot information  20  (S 317 ). 
     Incidentally, when the snapshot instruction has not been received (S 314 : No), the processes of S 315  to S 317  are skipped. 
     Thereafter, the same processes as those in S 114  to S 116  of  FIG. 7  are performed in S 318  to S 320 . 
       FIG. 14  is a flowchart explaining an example of a test method in the simulation mode using the simulation device  100   a  of the second embodiment. 
     When the simulation device  100   a  is used in the simulation mode, the simulation device  100   a  is connected directly to the controller  220   d  via the communication channel  240   b  as illustrated in  FIG. 11 . Further, the simulation device  100   a  is connected to the host  210   d  via the communication channel  300 . Further, the simulation device  100   a  is connected to the controller  220   d  via the communication channel  310 . 
     Then, before starting a test, the simulation device  100   a  receives a designation instruction from the host  210   d  via the communication channel  300  (S 401 ). Then, the snapshot control device  110  sets internal state information included in the snapshot information  20  designated by the designation instruction in the controller  220   d  (S 402 ). Further, the snapshot control device  110  records a feature information group, included in the snapshot information  20  designated by the designation instruction, into the page information  10  (S 403 ). That is, the snapshot control device  110  records each of pieces of the feature information of all the pages included in the feature information group into the corresponding page information  10 . 
     Thereafter, when the test is started (S 404 ), the same processes as those in S 202  to S 215  of  FIG. 8  are performed in S 405  to S 418 . Incidentally, during the test, the host  210   d  can start the test from a point in the test procedure at which the designated snapshot information  20  has been generated. 
     In this manner, the controller  220   c  is connected to the host  210   c  and transmits a command to the memory chip  230   a  based on a request from the host  210   c  according to the second embodiment. The simulation device  100   a  receives the snapshot instruction from the host  210   c  via the communication channel  300  that connects the simulation device  100   a  and the host  210   c . The simulation device  100   a  receives the internal state information of controller  220   c  in response to the snapshot instruction and stores the snapshot information  20  including the internal state information and the feature information group into the storage device  106 . Further, the simulation device  100   a  sets the internal state information included in the snapshot information  20  in the controller  220   d  and loads the feature information group included in the snapshot information  20  before starting the test in the simulation mode. 
     With the above configuration, it is possible to execute the test again from an arbitrary point in a series of procedures of the test. 
     Further, the process of generating the snapshot information  20  and storing the generated snapshot information  20  in the storage device  106  can be executed a plurality of times according to the second embodiment. Then, the simulation device  100   a  can receive a designation instruction to designate one of the plurality of pieces of snapshot information  20  stored in the storage device  106  from the host  210   d.    
     With the above configuration, it is possible to execute the test again from an arbitrary point among a plurality of points in the series of procedures of the test. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.