Patent Publication Number: US-11394306-B2

Title: Flyback switching power supply, control system thereof and control method therefor

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a Continuation-in-Part of International Application No. PCT/CN2018/125484 filed on Dec. 29, 2018, which claims priority to Chinese patent application No. 201711474042.9, filed on Dec. 29, 2017. Both applications are incorporated herein by reference in their entireties. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to a switching power converter, and more particularly to a flyback switching power supply, a control system, and a method for controlling the flyback switching power supply. 
     BACKGROUND 
     Switching power supplies are generally used as power sources for various types of electric devices, converting an unregulated AC or DC input voltage into a regulated AC or DC output voltage. Since the switching power supplies need to adapt to different working conditions, there has been increasingly higher requirements for the dynamic response of the power supplies. A good dynamic response requires a small voltage change and a short voltage recovery time. 
     Primary-side regulated (PSR) flyback converters are widely used in switching power supplies because of its simple structure, low cost and flexible control. There is a significant imbalance between the dynamic response of the PSR flyback converters and the actual demand. The output voltage may fluctuate greatly, particularly in the case of large load switching. In order to improve the dynamic response, researchers in the field of PSR flyback converters have proposed many innovative methods. 
     A digital multi-modes control algorithm has been proposed, which uses different modes for different load ranges and combines PWM and PFM. A fast and smooth switching can be achieved when the loads are switched in a small range. However, the control modes based on the algorithm can only be switched in sequence, which results in a slow response, a long responding time and a large overshoot voltage when the loads are switched in a large range. 
     In order to improve the dynamic response performance in the full load range, Chong Wang et al. (Novel digital control method for improving dynamic responses of multimode primary-side regulation flyback converter, IEEE Transactions on Power Electronics, 2017, 32(2): 1457-1468) have proposed a hybrid control method, in which a dynamic process detection module is introduced to the system. In addition to the steady-state multi-modes, two dynamic modes, i.e. light to heavy (LTH) mode and heavy to light (HTL) mode, are provided. A fixed cycle and a fixed duty cycle are adopted for controlling in the LTH and HTL modes. When the output voltage approaches the ideal value, the slope of the output voltage is used to determine the load point, so as to make sure the system enters into a correct steady-state mode. This solution effectively reduces the overshoot voltage and response time under discontinuous conduction mode (DCM) and improves the dynamic performance of the converter. However, there are still shortcomings. The recovery time is very long up to 53 ms when switching from a full load to an extremely light load. 
     In addition, in order to speed up the dynamic response, PI parameters are increased to speed up the compensation and thus the dynamic performance is improved according to some control methods. However, it brings limited improvements on dynamic performance for the situations when a multi-modes control is used. 
     SUMMARY 
     According to one aspect of the present disclosure, a control system for a flyback switching power supply is provided. The switching power supply includes a primary-side winding, a primary-side switching transistor coupled to the primary-side winding, a secondary-side winding, a secondary-side synchronous rectification transistor for rectifying an output voltage of the flyback switching power supply, and an auxiliary winding for providing output voltage feedback. The control system includes a sampling module configured to sample a resistance divided voltage Vsense of the auxiliary winding, and obtain a sampled output voltage Vo_sample according to the signal Vsense and obtain an error signal err between the signal Vo_sample and a rated output voltage Vo_ REF ; a multi-modes judgment module configured to receive the signal Vo_sample output by the sampling module and outputs a mode judgment signal mode_dynamic, wherein the value of the signal mode_dynamic is equal to 1 if the signal Vo_sample is greater or equal to a predetermined upper limit of output voltage Vomax, and the value of the signal mode_dynamic is equal to 0 if the signal Vo_sample is smaller than the upper limit Vomax; a dynamic control module configured to receive the signal mode_dynamic and output a duty cycle control signal Duty_SR_dynamic of the secondary-side synchronous rectification transistor when the signal mode_dynamic is equal to 1; a load point judgment module configured to receive the signal Vo_sample output by the sampling module and the signal mode_dynamic, and output a state judgment signal state_judge and a switching cycle Ts_judge when the signal Vo_sample drops to the rated output voltage Vo_ REF , the multi-modes judgment module being configured to output a value of the state signal state corresponding to a steady-state mode upon receipt of the signal state_judge; a digital PID module configured to receive signals state and err and select a PID compensation algorithm according to the signal state, and calculate and output a control voltage compensation V PI  according to the signal err and predetermined PI parameters Kp and Ki, the multi-modes judgment module adjusting the value of state according to the control voltage compensation V PI ; and a PWM drive module configured to turn off the primary-side switching transistor and switch the secondary-side synchronous rectification transistor with a fixed cycle Ts_ HTL  and a fixed duty cycle D HTL  upon receipt of the signal Duty_SR_dynamic, the PWM drive module controlling the switching of the primary-side switching transistor in the steady-state mode by taking Ts_judge as a value of a first cycle when receiving the signal Ts_judge, the PWM drive module calculating a duty cycle of the secondary-side synchronous rectification transistor according to the signal Vo_sample to perform switching of the secondary-side synchronous rectification transistor with a same cycle as in the primary-side switching transistor, the PWM drive module performing controlling of the primary-side switching transistor by means of a peak current control method based on the signal state and the control voltage compensation V after the first cycle. 
     According to another aspect of the present disclosure, a flyback switching power supply is provided, which includes a primary-side winding, a primary-side switching transistor coupled to the primary-side winding, a secondary-side winding, a secondary-side synchronous rectification transistor for rectifying an output voltage of the flyback switching power supply, an auxiliary winding for providing output voltage feedback, and a control system. The control system includes a sampling module configured to sample a resistance divided voltage Vsense of the auxiliary winding, and obtain a sampled output voltage Vo_sample according to the signal Vsense and obtain an error signal err between the signal Vo_sample and a rated output voltage Vo_ REF ; a multi-modes judgment module configured to receive the signal Vo_sample output by the sampling module and outputs a mode judgment signal mode_dynamic, wherein the value of the signal mode_dynamic is equal to 1 if the signal Vo_sample is greater or equal to a predetermined upper limit of output voltage Vomax, and the value of the signal mode_dynamic is equal to 0 if the signal Vo_sample is smaller than the upper limit Vomax; a dynamic control module configured to receive the signal mode_dynamic and output a duty cycle control signal Duty_SR_dynamic of the secondary-side synchronous rectification transistor when the signal mode_dynamic is equal to 1; a load point judgment module configured to receive the signal Vo_sample output by the sampling module and the signal mode_dynamic, and output a state judgment signal state_judge and a switching cycle Ts_judge when the signal Vo_sample drops to the rated output voltage Vo_ REF , the multi-modes judgment module being configured to output a value of a state signal state corresponding to a steady-state mode upon receipt of the signal state_judge; a digital PID module configured to receive signals state and err and select a PID compensation algorithm according to the signal state, and calculate and output a control voltage compensation V PI  according to the signal err and predetermined PI parameters Kp and Ki, the multi-modes judgment module adjusting the value of state according to the control voltage compensation V PI ; and a PWM drive module configured to turn off the primary-side switching transistor and switch the secondary-side synchronous rectification transistor with a fixed cycle Ts_ HTL  and a fixed duty cycle D TL  upon receipt of the signal Duty_SR_dynamic, the PWM drive module controlling the switching of the primary-side switching transistor in the steady-state mode by taking Ts_judge as a value of a first cycle when receiving the signal Ts_judge, the PWM drive module calculating a duty cycle of the secondary-side synchronous rectification transistor according to the signal Vo_sample to perform switching of the secondary-side synchronous rectification transistor with a same cycle as in the primary-side switching transistor, the PWM drive module performing controlling of the primary-side switching transistor by means of a peak current control method based on the signal state and the control voltage compensation V PI  after the first cycle. 
     According to yet another aspect of the present disclosure, a method for controlling a flyback switching power supply is provided. The switching power supply includes a primary-side winding, a primary-side switching transistor coupled to the primary-side winding, a secondary-side winding, a secondary-side synchronous rectification transistor for rectifying an output voltage of the flyback switching power supply, and an auxiliary winding for providing output voltage feedback. The method includes: sampling a resistance divided voltage Vsense of the auxiliary winding; obtaining a sampled output voltage Vo_sample according to the signal Vsense and an error signal err between the signal Vo_sample and a rated output voltage Vo_ REF ; turning off a primary-side switching transistor and switching a secondary-side synchronous rectification transistor with a fixed cycle Ts_ HTL  and a fixed duty cycle D HTL  by a PWM drive module in a dynamic mode when Vo_sample≥Vomax, the system stepping out the dynamic mode and entering into a steady-state mode when the signal Vo_sample drops to Vo_ REF ; and obtaining a control voltage compensation V PI  by a digital PID module by means of a PID compensation algorithm according to the signal err and predetermined PI parameters Kp and Ki in the steady-state mode, the PWM drive module calculating the cycle of the primary-side switching transistor according to the control voltage compensation V PI  and calculating the duty cycle of the secondary-side synchronous rectification transistor according to the signal Vo_sample by means of a peak current control method, so as to perform switching of the primary-side switching transistor and the secondary-side synchronous rectification transistor with same cycles. 
     Details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and description below. Other features, objects, and advantages of the disclosure will become apparent from the description, the drawings, and the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In order to more clearly illustrate the technical solutions in the embodiments or the exemplary technologies of the present disclosure, the drawings to be used in the description of the embodiments or the exemplary technologies will be briefly described below. Obviously, the described drawings are only representations of the embodiments of the present disclosure, and those skilled in the art can obtain drawings for other embodiments based on these drawings without any creative work. 
         FIG. 1  is a diagram illustrating the structure of a switching power supply in accordance with an embodiment. 
         FIG. 2  is a diagram illustrating the structure of a sampling module in accordance with an embodiment. 
         FIG. 3  is a diagram illustrating the structure of a multi-modes judgment module in accordance with an embodiment. 
         FIG. 4  is a diagram illustrating the structure of a high dynamic control module in accordance with an embodiment. 
         FIG. 5  is a diagram illustrating the structure of a load point judgment module in accordance with an embodiment. 
         FIG. 6  is a diagram illustrating the structure of a digital PID module in accordance with an embodiment. 
         FIG. 7  is a diagram illustrating the structure of a PWM drive module in accordance with an embodiment. 
         FIG. 8  is a schematic diagram of an application of a heavy-to-light load switching mode in accordance with an embodiment. 
         FIG. 9  is a waveform diagram of an output voltage, a primary-side current and a secondary-side current in a heavy-to-light load switching mode in accordance with an embodiment. 
         FIG. 10  is a flowchart of a high dynamic control algorithm of the present disclosure in accordance with an embodiment. 
         FIG. 11  shows a dynamic result without a high dynamic control algorithm of the present disclosure adopted when the load is switched from 4Ω to 800Ω. 
         FIG. 12  shows a dynamic result with a high dynamic control algorithm of the present disclosure adopted when the load is switched from 4Ω to 800Ω. 
     
    
    
     DETAILED DESCRIPTION 
     The technical solutions of the present disclosure will be described clearly and thoroughly in combination with the drawings and embodiments. 
     In order to overcome the shortcomings and deficiencies of the prior art, the present disclosure proposes a flyback switching power supply, a control system for the flyback switching power supply, and a method for controlling the flyback switching power supply. When the load of the switching power supply is switched from a heavy load to a light load, the overshoot of the output voltage can be limited within a certain range, and the dynamic recovery time is significantly shortened, thereby improving the dynamic performance significantly. The method does not cause system instability in multi-modes control, and effectively reduces the overshoot of the voltage and dynamic recovery time, thereby leading to a better dynamic performance of the system. 
     One aspect of the present disclosure provides a flyback switching power supply.  FIG. 1  is a diagram showing the structure of a flyback switching power supply according to one embodiment of the present disclosure, in which a primary side of the flyback switching power supply has a main topology of primary-side regulation, and a secondary side of the flyback switching power supply has a synchronous rectification structure. Specifically, the primary side includes a primary-side winding and a primary-side switching transistor coupled to the primary-side winding, and the secondary side includes a secondary-side winding and a secondary-side synchronous rectification transistor (SR transistor) for rectifying an output voltage of the flyback switching power supply. The primary side may further include an auxiliary winding to provide output voltage feedback. 
     In the embodiment as shown in  FIG. 1 , the flyback switching power supply is an isolated type, i.e., the primary side and secondary side are coupled through windings to transmit energy between each other, but they are not electrically connected directly. 
     The flyback switching power supply further include a control system based on digital multi-modes control, which includes a sampling module, a multi-modes judgment module, a digital PID compensation module, a dynamic control module, a load point judgment module and a PWM drive module. These modules form a closed loop system with a controlled switching power supply. 
     The sampling module samples a resistance divided voltage Vsense of the auxiliary winding to obtain a current sampled output voltage Vo_sample. Feedback of the actual voltage output through the auxiliary winding is a prior art in the art, and will not be described in detail here. An error signal err (err=V O_REF −Vo_sample) of the sampled output voltage and a rated output voltage V O_REF  is then determined. The multi-modes judgment module receives the value of the sampled output voltage Vo_sample, and if Vo_sample is greater than or equal to a predetermined upper limit Vomax, the multi-modes judgment module outputs a dynamic mode judgment signal mode_dynamic with a value of 1, indicating that the system is in a heavy-to-light load switching state (HTL mode), and the dynamic mode judgment signal mode_dynamic is then input into the dynamic control module and the load point judgment module to perform high dynamic control. The dynamic control module receives the dynamic mode judgment signal mode_dynamic from the multi-modes judgment module. The dynamic control module turns off the primary-side switching transistor by the PWM driving module and output a duty cycle signal Duty_SR_dynamic of the SR transistor to the PWM drive module when the value of the signal mode_dynamic is 1. The output voltage drops rapidly by controlling the SR transistor to be switched with a fixed duty cycle. The load point judgment module receives the sampled output voltage Vo_sample from the sampling module in the HTL mode, and calculates a dropping slope Kdown of the output voltage. The current load is then determined according to the slope, based on which a steady-state mode that the system should be in after the dynamic process, as well as a switching cycle Ts_judge and a primary-side peak current of the steady-state mode are further determined. In an embodiment, the system enters into a DPFM steady-state mode after the dynamic process, in which the peak current is fixed. The load point judgment module outputs a step-out state judgment signal state_judge to the multi-modes judgment module, and outputs the current switching cycle Ts_judge to the PWM drive module. A steady state is then achieved which uses a conventional digital PID control. In the dynamic mode HTL, the PWM drive module turns off the primary-side switching transistor and receives the duty cycle signal Duty_SR_dynamic. Also, the PWM drive module controls the switching of the SR transistor with a fixed cycle and a fixed duty cycle, and obtains the PWM waveforms that regulate the primary-side switching transistor and the SR transistor. When the PWM drive module is in the steady state, a peak current control is adopted. 
       FIG. 2  shows an structure of the sampling module according to one embodiment. The sampling module samples the resistance divided voltage Vsense of the auxiliary winding. The sampling module includes two comparators COMP 1  and COMP 2 , a waveform real-time analysis module and a subtractor. The resistance divided voltage Vsense of the auxiliary winding is input into the positive terminal of COMP 1  and an internal sampling signal Vsample from the waveform real-time analysis module is input into the negative terminal of COMP 1 . The current value of the internal sampling signal Vsample is determined to be the inflection point value of the resistance divided voltage Vsense or not according to the output result of the comparator COMP. The sampled output voltage Vo_sample is assigned by the internal sampling signal Vsample, and then the internal sampling signal Vsample is dynamically adjusted according to the output result of the comparator COMP 1  for the next sampling. The resistance divided voltage Vsense is also input to the positive terminal of COMP 2  while the negative terminal of COMP 2  is coupled to zero level. The waveform real-time analysis module outputs the internal sampling signal Vsample and the value of the sampled output voltage Vo_sample according to the results of the two comparators. Vo_sample is input into the negative terminal of the subtractor, and the rated output voltage V O_REF  is input into the positive terminal of the subtractor, so that an error signal err (err=V O_REF −Vo_sample) is obtained. The voltage waveform of the resistance divided voltage Vsense is input into the sampling module and compared with the signal Vsample and 0 by two comparators COMP 1  and COMP 2 , respectively, and two signals comp_sample and comp_zero are then obtained. The waveform real-time analysis module analyzes the output signals of the two comparators to obtain the value of the current sampled output voltage Vo_sample, and adjusts the value of the internal sampling signal Vsample to prepare for the next sampling. The value of the error signal err is obtained by subtracting Vo_sample from the rated output voltage V O_REF  (a fixed Value). 
       FIG. 3  shows a structure of the multi-modes control module according to one embodiment. The multi-modes control module receives the sampled output voltage Vo_sample output by the sampling module. The multi-modes control module includes two comparators COMP 3  and COMP 4 , a dynamic mode judgment module, a steady-state mode judgment module, and a multi-modes state judgment module. The positive terminal of the comparator COMP 3  is coupled to a predetermined upper limit of output voltage Vomax, and the negative terminal of the comparator COMP 3  is coupled to the signal Vo_sample. The positive terminal of comparator COMP 4  is coupled to the signal Vo_sample, while the negative terminal of the comparator COMP 4  is coupled to a predetermined rated voltage V O_REF . The dynamic mode judgment module outputs the dynamic mode judgment signal mode_dynamic according to the results of the two comparators. A control voltage compensation V PI  and a state signal state are input into the steady-state mode judgment module, and the steady-state mode judgment module outputs a steady state signal state_steady. Specifically, the output voltage Vo_sample sampled by the sampling module is compared with the predetermined upper limit Vomax of the output voltage and the rated output voltage V O_REF  respectively by the comparators, and the comparison results are input into the dynamic mode judgment module for analysis. If Vo_sample≥Vomax, then mode_dynamic=1, indicating that the system enters into the dynamic mode and the current signal state=state_HTL. In the dynamic mode, when Vo_sample drops to V O_REF , the signal mode_dynamic becomes zero, and the system steps out the dynamic mode. The specific steady-state mode that the system is to enter into is determined according to the signal state_judge, and the current signal state=state_judge. In the steady-state mode, the signal mode_dynamic=0, and the steady-state mode judgment module performs mode judgment according to the current state signal state and the value of the digital compensation V PI  to output the signal state_steady of the next mode and assigns a value to the signal state. A control mode is determined according to a value of a state signal state output by the multi-modes state judgment module, and the control mode is selected from the CCM (continuous conduction mode), PWM (pulse width modulation), PFM (pulse frequency modulation), DPWM (digital pulse width modulation), or DPFM (digital pulse frequency modulation). 
       FIG. 4  shows a structure of the high dynamic control module according to one embodiment. The dynamic control module is a high dynamic control module, since the system enters into a dynamic mode when the dynamic mode judgment signal Mode_dynamic=1. The high dynamic control module receives the dynamic mode judgment signal Mode_dynamic output by the multi-modes judgment module. If Mode_dynamic=1, the system enters into the dynamic mode. In the dynamic mode, the primary-side switching transistor keeps off and no energy is input, so only the SR transistor of the secondary side needs to controlled with a fixed cycle Ts_ HTL  and a fixed duty cycle D HTL . Thus, the high dynamic control module only outputs the PWM signal Duty_SR_dynamic for the gate of the secondary-side SR transistor. 
       FIG. 5  shows a structure of a load point judgment module according to one embodiment, which includes a comparator COMP 5 , a parameter calculation module, a slope calculation module, and a step-out mode judgment module. The positive terminal of the comparator COMP 5  is coupled to Vo_sample, while the negative terminal is coupled to the rated output voltage Vo_ REF . The comparator COMP 5  outputs a reference voltage comparison signal Comp_V REF . In an embodiment, the comparator COMP 5  can be replaced by the comparator COMP 4  as described before. The input of the parameter calculation module is the dynamic mode judgment signal Mode_dynamic and the sampled output voltage Vo_sample, and the output is the value of the output voltage change ΔVo_sample and the corresponding time Δt. The input of the slope calculation module is ΔVo_sample, Δt and Comp_V REF , and the output is the voltage dropping slope Kdown. The input of the step-out mode judgment module is Kdown, and the output is the step-out state judgment signal state_judge and the current switching cycle Ts_judge. In the dynamic mode, state=HTL. The parameter calculation module performs a counting by a counter to obtain Δt, i.e., the time from entry into the dynamic mode to stepping out of the dynamic mode, and further obtains a change ΔVo_sample over Δt according to the input Vo_sample. The slope calculation module captures the time point when Vo_sample drops to Vo_ REF  by analyzing the output of the comparator Comp_V REF , and then calculates the slope Kdown of the output voltage. The step-out mode judgment module then determines the mode state_judge of the system after stepping out of the dynamic state and the switching cycle Ts_judge of the first cycle according to the value of Kdown. The step-out state judgment signal state_judge and the switching cycle signal Ts_judge after stepping-out are valid only when stepping out the dynamic mode. 
       FIG. 6  shows a structure of a digital PID compensation module according to an embodiment, which includes a PI parameter selection module and a digital PI compensation algorithm module. The input of the PI parameter selection module is the state signal state, and the output is PI parameters, i.e., proportional control factors Kp and integral control factors Ki. The input of the digital PI compensation algorithm module is Kp, Ki and the error signal err, and the output is the control voltage compensation V PI . The present disclosure uses the PID compensation algorithm, but only P adjustment and I adjustment are used, and D adjustment is not used. In the steady-state mode, different parameters Kp and Ki are selected depending on different modes, and are input into the subsequent digital PI compensation algorithm module together with the current output voltage error err to calculate the control voltage compensation V PI  for the next cycle. The digital PID compensation module is idle in the dynamic mode. 
       FIG. 7  shows a structure of the PWM drive module according to an embodiment, which includes a gating module, a primary-side switching transistor cycle Ts calculation module, a primary-side switching transistor duty cycle control module and a SR transistor duty cycle control module. The state signal state is input into the gating module, and two signals are obtained: a dynamic state signal State_HTL and a steady state signal State_steady. The gating module determines whether the current mode state should be a steady-state mode state_steady or a dynamic mode State_HTL. If the gating module outputs State_HTL, the input of the primary-side switching transistor duty cycle control module is State_HTL and 0, and the output is primary-side switching transistor dynamic duty cycle signal duty which is equal to Duty_dynamic. The input signals of the synchronous rectifier SR transistor duty cycle control module include State_HTL and Duty_SR_dynamic output by the high dynamic control module, and the output is the synchronous rectification SR transistor duty cycle signal Duty_SR which is equal to Duty_SR_dynamic. If the gating module outputs State_steady, the input signals of the primary switching transistor cycle Ts calculation module include V PI , State_steady and Ts_judge, and the output is the primary-side switching transistor cycle signal Ts. The signal Ts and primary-side peak current Ipeak are input to the primary-side switching transistor duty cycle control module which then outputs the primary-side switching transistor duty cycle signal duty which is equal to Duty_steady. State_steady and Vo_sample are input to the SR transistor duty cycle control module which thereby outputs a SR transistor duty cycle signal Duty_SR which is equal to Duty_SR_steady. 
     In the dynamic mode HTL, the primary-side switching transistor keeps off, and the PWM signal duty input into the gate of the primary-side switching transistor is equal to zero. The PWM signal Duty_SR that is input into the gate of the SR transistor is Duty_SR_dynamic which is provided by the high dynamic control module. 
     After the system steps out a dynamic state and enters into a steady state, the first switching cycle Ts of the primary-side switching transistor is Ts_judge which is provided by the load point judgment module. The calculation of the subsequent switching cycles Ts is same as in the steady-state mode. 
     The peak current control is adopted in the steady-state mode. The cycles Ts of the primary-side switching transistor in the PFM and DPFM mode are calculated according to the digital compensation V PI . The rest of the steady-state modes have fixed cycles. When the value of a cycle counter is 0, duty=1 and the primary-side switching transistor is turned on. When the primary-side current reaches the peak current, duty=0 and the primary-side switching transistor is turned off until the value of the cycle counter becomes zero again. This step is repeatedly performed as above. 
     In the steady state, the cycle of the secondary-side synchronous rectification transistor (SR transistor) is equal to the cycle of the primary-side switching transistor. When the primary-side switching transistor is turned off, Duty_SR=1 and the SR transistor is turned on. The SR transistor duty cycle control module calculates a time Ton_sr that the SR transistor keeps on according to the current output voltage Vo_sample. When the state of Duty_SR=1 lasts for this time, the SR transistor is turned off and Duty_SR=0. This step is repeatedly performed as above. 
     The advantages and effects of the present disclosure includes: 
     1. The dynamic control method proposed in this disclosure turns off the primary-side switching transistor when the output voltage exceeds an upper limit, and control the switching of the secondary-side synchronous rectification transistor with a fixed cycle and a fixed duty cycle. During the time that the synchronous rectification transistor is turned on, the energy of a load capacitor at the output end is extracted to the primary side, which causes the output voltage to drop rapidly and the overshoot voltage to decrease greatly, and also reduces the dynamic recovery time to 2.5 ms. 
     2. The dynamic control method proposed in this disclosure calculates the slope of the output voltage dropping from an upper limit to a rated value in the heavy-to-light load mode, and obtains the value of the load based on the monotonic correspondence between the slope and the load. The energy is not much different from the steady-state consumption of the load after the system steps out the HTL mode and enters into a steady state corresponding to the load point, thereby eliminating the potential voltage oscillations and reducing the dynamic recovery time. In addition, the value of the load after the stepping-out is determined by the slope, which avoids a large voltage resonance otherwise caused by the large difference between the energy and the steady-state consumption of the load after the stepping-out, and avoids a large oscillation otherwise caused by the HTL mode. Therefore, a more stable circuit is realized. 
     3. The present disclosure involves a heavy-to-light load mode, i.e. a HTL mode and a method of determining a load point based on a digital multi-modes control, which will not affect the stability of a common multi-modes control loop. 
     4. The present disclosure can be applied to a switching power supply circuit with synchronous rectification, and can be used widely and repeatedly. 
     The flyback power supply converter in one example has an input voltage range of 90˜265V and a constant output voltage of 20V. The maximum output current is 5 A. The transformer inductance is 417 μH, and the turn ratio of the transformer is 45 (primary-side windings): 8 (secondary-side windings): 4 (auxiliary windings). The clock frequency is 20 MHz. When judging the load point, the relationship between the output load, the voltage dropping slope Kdown and the corresponding working state are shown in Table 1. 
     
       
         
           
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                 Stepping-out Modes Corresponding to 
               
               
                 Different Slops Kdown in HTL Modes 
               
            
           
           
               
               
               
               
               
            
               
                 Kdown(mV/μs) 
                 Load(Ω) 
                 Mode 
                 Ts_judge/μs 
                 Ipeak/A 
               
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 ~2.65 
                 700~ 
                 DPFM 
                 543 
                 1.530 
               
               
                 2.65~3.18 
                 500~700 
                 DPFM 
                 409 
                 1.530 
               
               
                 3.18~4.25 
                 300~500 
                 DPFM 
                 335 
                 1.530 
               
               
                 4.25~5.32 
                 150~300 
                 DPFM 
                 196 
                 1.530 
               
               
                 5.32~ 
                 ~150      
                 DPFM 
                 121 
                 1.530 
               
               
                   
               
            
           
         
       
     
     The above are the specific parameters of the exemplary 20V/5 A primary-side regulated flyback power supply converter. 
     Referring to  FIG. 8 , when switching from a heavy load to a light load, it can be seen from the diagram that the HTL mode is used when the output voltage is greater than Vomax. If PID adjustment is used, as shown by the thick dashed line, the voltage will continue to increase after it rises to Vomax, and the dynamic recovery time is very long. The HTL mode if desired will be adopted immediately after the output voltage becomes greater than Vomax. In this mode, the primary-side switching transistor is turned off and the switching of the secondary-side synchronous rectification transistor is controlled with a fixed cycle and a fixed duty cycle. During the time when the synchronous rectification transistor is on, the energy of the load capacitor at the output end is extracted to the primary side, which causes the output voltage to drop rapidly. When the output voltage drops to a rated value, the output load can be obtained by the slope so as to make sure that the output energy in a steady state mode following the HTL mode is close to the consumption of the load, and the resonance otherwise caused by energy mismatch is therefore eliminated, as shown by the solid line. It can also be seen that if the output energy is too low due to improper conditions after stepping out the HTL mode, a voltage resonance may be introduced, as shown by the thin dotted line. 
       FIG. 9  shows key waveforms of the output voltage Vo, the primary-side current Ip, the secondary-side current Is and the resistance divided voltage Vsense of the auxiliary winding when switching from a heavy load to a light load. The system enters into the HTL mode with the primary-side switching transistor being turned off when the output voltage is greater than Vomax, and only the secondary-side synchronous rectification transistor is operated with a fixed cycle Ts_HTL and a fixed duty cycle D HTL . 
     The secondary-side current Is increases linearly inversely and forms a negative current when the synchronous rectification transistor is turned on. Is reaches a maximum value when the synchronous rectification transistor is turned off. During this process, the energy of the load capacitor at the output end is extracted and stored in an excitation inductor, which decreases the output voltage rapidly. Meanwhile, sampling is performed during the time when the synchronous rectification transistor is turned on. The waveform of Vsense of the auxiliary winding is also shown in the figure. 
     The energy stored in the excitation inductor is transmitted to the primary side when the synchronous rectification transistor is turned off, forming a negative current on the primary side. The energy is then returned to the input voltage network through the body diode of the primary-side switching transistor, making the negative current of the primary side decreases to zero gradually. The energy extracted from the secondary-side load capacitor is therefore released. 
     The above process can be repeated by controlling the switching of the secondary-side synchronous rectification transistor. The switching of the synchronous rectification transistor is performed with a fixed cycle Ts_HTL and a fixed duty cycle D HTL  to quickly reduce the stored energy in the load capacitor at the output end, which decreases the output voltage rapidly and further makes the system enter into a corresponding steady-state mode. 
     Another aspect of the present disclosure provides a method for controlling a flyback switching power supply.  FIG. 10  is a flowchart of the control method according to one embodiment of the present disclosure. As shown in the figure, the waveform of the voltage on the auxiliary winding is first sampled, and then mode judgment is performed to determine whether the system enters into the dynamic mode. If the system enters into the dynamic mode, the primary-side switching transistor is turned off, and the synchronous rectification transistor is operated with a fixed cycle Ts_HTL and a fixed duty cycle D HTL , which decreases the output voltage with a fixed slope (the voltage dropping slope keeps unchanged provided that the load does not change). At the same time, the output voltage is sampled with the help of the waveform of Vsense of the auxiliary winding during the time when the SR transistor is turned on and input into the load point judgment module when it drops to the rated voltage. According to the time Δt during which the output voltage drops, the slope Kdown of the drop is calculated, and the corresponding load point is thereby obtained. The system then enters into a corresponding steady-state mode based on the value of the load. The system quits the high dynamic control mode now, and enters into the steady-state mode with the output voltage being stabilized at the rated value. The digital PID compensation algorithm is subsequently used for conventional digital multi-modes control. For the connection relationship between the modules involved in the above steps and the corresponding working principles, reference may be made to the previous descriptions of the modules of the flyback switching power supply, which will not be repeated here. 
     The above is only a description of the steps of the control method of one embodiment, and is not used to limit the order of steps. Those skilled in the art can appropriately adjust the order of the corresponding steps according to the description of this application. 
       FIG. 11  shows the dynamic result when the load is switched from 4Ω to 800Ω in the case that the high dynamic algorithm of the present disclosure is not applied. It can be seen from the figure that, when a conventional digital multi-modes control algorithm is used, a large overshoot voltage of the output voltage of 3.150V is introduced, and a long dynamic recovery time of 64.32 ms is taken. Moreover, there will be voltage fluctuations when the output voltage drops to the rated value, thereby resulting in poor dynamic performance. 
       FIG. 12  shows the dynamic result when the load is switched from 4Ω to 800Ω using the high dynamic algorithm of the present disclosure. This is only an embodiment of the present disclosure. As can be seen from the figure, when using a high dynamic control algorithm, the overshoot voltage of the output voltage is 1.343V and the dynamic recovery time is 1.888 ms, which effectively reduces the overshoot voltage and greatly reduces the dynamic recovery time. In addition, there is no voltage fluctuation when the output voltage drops to the rated value and the load point can be accurately determined, which greatly improves the dynamic performance when switching from a heavy load to a light load.