Patent Publication Number: US-11646204-B2

Title: Method for forming a layer provided with silicon

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to U.S. Provisional Patent Application Ser. No. 63/043,398 filed Jun. 24, 2020 titled METHOD FOR FORMING A LAYER PROVIDED WITH SILICON, the disclosure of which is hereby incorporated by reference in its entirety. 
    
    
     FIELD 
     The present disclosure generally relates to a method for forming a layer provided with silicon on a substrate. The layer may be formed in a processing chamber by heating the substrate to a first temperature and introducing precursors into the processing chamber to deposit the layer. 
     BACKGROUND OF THE DISCLOSURE 
     Methods according to the present disclosure may be used in the manufacturing of integrated circuits, for example NAND devices. During manufacturing of 3D NAND devices, which are usable in applications such as flash memory, a substrate may be provided with a bilayer comprising a nitride layer and an oxide layer. The nitride layers and the oxide layers may undergo an etch process to form a gap in the bilayer. 
     The surface of the gap may be provided with multiple layers such as for example a blocking oxide, a trap silicon nitride, a tunnel oxide and a channel poly silicon layer for which the electrical properties may be very critical for the functioning of the integrated circuit. As a result, it may be desired to provide a method for forming a layer provided with silicon on a substrate to cover the gap of the bilayer. 
     SUMMARY OF THE DISCLOSURE 
     This summary is provided to introduce a selection of concepts in a simplified form. These concepts are described in further detail in the detailed description of example embodiments of the disclosure below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. 
     In accordance with at least one embodiment, an exemplary method may be disclosed for forming layers provided with silicon on a substrate comprising: positioning a substrate within a processing chamber; heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The method may comprise heating the substrate to a second temperature between 400 and 600° C. and introducing a second precursor into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor. 
     In accordance with a further embodiment an exemplary method may be disclosed for forming a layer provided with silicon comprising: positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 600° C. and introducing a trisilane precursor into the processing chamber to deposit a layer provided with silicon. The method may comprise heating the substrate to a third temperature between about 600 and 1200° C. to anneal the layer provided with silicon. The layer may comprise epitaxial grains after heating the processing chamber to the third temperature. 
     These and other embodiments will become readily apparent to those skilled in the art from the following detailed description of certain embodiments having reference to the attached figures; the invention not being limited to any particular embodiment(s) disclosed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       These and other features, aspects, and advantages of the invention disclosed herein are described below with reference to the drawings of certain embodiments, which are intended to illustrate and not to limit the invention. 
         FIG.  1    is cross-sectional illustrations of a NAND device during the manufacturing process. 
         FIG.  2    shows the hydrogen content of a deposited layer. 
         FIG.  3    shows grain formation in the deposited layers. 
         FIG.  4    shows the uniformity of the layers deposited in a gap after a top etch may be applied. 
     
    
    
     It will be appreciated that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of illustrated embodiments of the present disclosure. 
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     Although certain embodiments and examples are disclosed below, it will be understood by those in the art that the invention extends beyond the specifically disclosed embodiments and/or uses of the invention and obvious modifications and equivalents thereof. Thus, it is intended that the scope of the invention disclosed should not be limited by the particular disclosed embodiments described below. 
     The illustrations presented herein are not meant to be actual views of any particular material, structure, or device, but are merely idealized representations that are used to describe embodiments of the disclosure. 
     In some cases, the term “precursor” may refer to a compound that participates in the chemical reaction that produces another compound. In particular, it may relate to a compound that constitutes a film matrix or a main skeleton of a film. 
     As used herein, the term “substrate” may refer to any underlying material or materials that may be used to form, or upon which, a device, a circuit, or a film may be formed. A substrate may include a bulk material, such as silicon (e.g., single-crystal silicon), other Group IV materials, such as germanium, or other semiconductor materials, such as a Group II-VI or Group III-V semiconductor materials, and may include one or more layers overlying or underlying the bulk material. Further, the substrate may include various features, such as gaps, protrusions, and the like formed within or on at least a portion of a layer of the substrate. By way of examples, a substrate may include bulk semiconductor material and an insulating or dielectric material layer overlying at least a portion of the bulk semiconductor material. 
     As used herein, the term “film” and/or “layer” can refer to any continuous or non-continuous structure and material, such as material deposited by the methods disclosed herein. For example, film and/or layer can include two-dimensional materials, three-dimensional materials, nanoparticles or even partial or full molecular layers or partial or full atomic layers or clusters of atoms and/or molecules. A film or layer may comprise material or a layer with gaps, which may be at least partially continuous. 
     As used herein, a “structure” can be or include a substrate as described herein. Structures can include one or more layers overlying the substrate, such as one or more layers formed according to a method as described herein. 
     Three-dimensional (3-D) Not-AND (NAND) devices may be utilized in memory applications. The 3-D NAND devices may comprise structures comprising stacks of bilayers disposed on each other. The bilayers may comprise oxides and nitrides, for example. When disposing stacks of multiple bilayers on other stacks, alignment and stresses on the layers and different features may become critical. 
       FIG.  1    is cross-sectional illustrations of a NAND device during the manufacturing process in accordance with at least one embodiment of the invention. The device  1  under construction may comprise a substrate  3  and a first structure e.g. a first bilayer stack  220  comprising alternating nitride layers and oxide layers. The substrate  3  may comprise silicon, silicon oxide, or a metal oxide. The nitride layers may comprise at least one of: silicon nitride, germanium nitride, silicon germanium nitride (SiGeN), silicon oxynitride (SiON), germanium oxynitride (GeON), or combinations thereof. The oxide layers may comprise at least one of: silicon oxide, germanium oxide, silicon germanium oxide (SiGeOx), germanium oxynitride (GeON), silicon oxynitride (SiON), or combinations thereof. 
     The device  1  may go through a wet or dry etch process to create gaps  7  in the structure of the device  1 . The dry etch process may utilize a halide chemistry, for example fluorine or chlorine based. Fluorine etch processes may comprise NF3, CHF, SF6, CF4, and their mixtures, for example. The dry etch process may involve a remote plasma system, for example. The dry etch chemistry may involve oxygen or ozone in some cases. Providing the bilayers and etching the gaps in the bilayers may be repeated until a structure with sufficient height and a sufficient deep gap is manufactured. A halogen like dichlorine may be used as an etchant. 
     The surface of the gaps  7  may be provided with multiple layers  9  such as for example a blocking oxide  11 , a trap silicon nitride  13 , a tunnel oxide  15  e.g. silicon oxinitride (SiON) layer, and a channel poly silicon layer  17 . The electrical properties may be very critical for the functioning of the 3D NAND device. For example, for the channel poly silicon layer  17  it may be important to have a good conductivity. The poly silicon layer  19  may be covered with a siliconoxide (SiO) fill. 
     A good conductive layer for the channel poly silicon layer  17  may be provided by positioning the substrate  3  within a processing chamber. The substrate  3  may be heated to a first temperature between 300 and 500° C., preferable between 310 and 450° C., and even more preferable between 320 and 420° C. A first precursor may be introduced into the processing chamber to deposit a first layer. The temperature may be chosen lower than 370° C., for example 340° C. when the first precursor is trisilane (Si 3 H 8 ). The temperature may be chosen lower than 410° C., for example 400° C., when the first precursor is disilane (Si 2 H 6 ). 
     The precursor may be substantially carbon free. A carbon free first precursor may deposit a substantially carbon free silicon layer. A substantially carbon free silicon layer may help to get the required good electrical conductance. 
     The deposited first layer may have a thickness of 1 to 10 nanometer, preferably around 2 to 6 nanometer and most preferable around 4 nanometer. The deposited first layer may be amorphous. The deposited first layer may be substantially carbon free. 
       FIG.  2    shows the hydrogen content of the deposited layer as function of the deposition temperature using trisilane. The first layer may comprise more than 0.05 at % (atomic percentage) hydrogen when deposited at 520° C., more than 0.2 at % hydrogen when deposited at 450° C. and more than 0.5 at % hydrogen when deposited at 410° C. using trisilane. Hydrogen content may correlate with the temperature at which the layers may be deposited as shown. At temperatures lower than 370° C., for example 340° C. when the first precursor is trisilane (Si3H8) the hydrogen content may be larger than 1 at % or even larger than 2 at %. The first layer may be deposited using substantially carbon free precursors. The first layer may therefore be substantially carbon free. 
     The substrate may be heated subsequently to a second temperature between 400 and 600° C., preferable between 410 and 550° C. and even more preferable between 420 and 500° C. A second precursor may be introduced into the processing chamber to deposit a second layer. The second layer may be deposited on the first layer. The temperature may be chosen lower than 480° C., for example 460° C. or 430° C., when the second precursor is silane (SiH 4 ). 
     The second layer may have a thickness of 3 to 30 nanometer, preferably around 6 to 20 nanometer and most preferable around 12 nanometer. The deposited second layer may be amorphous. The deposited second layer may comprise 0.1 to 0.5% at % hydrogen for example 0.2 to 0.3 at % hydrogen. 
     Alternatively, the first and second layers may be deposited in one go forming a silicon layer with a single precursor. For example by a method for forming a silicon layer on a substrate, comprising: positioning a substrate within a processing chamber; heating the substrate to a temperature between 300 and 600° C. and introducing a trisilane precursor into the processing chamber to deposit the silicon layer. Trisilane deposits at a temperature between 300 and 600° C. silicon layers with a high hydrogen at %. 
     The substrate may then be heated to a third temperature between about 600 and 1200° C., preferably between 610 and 800° C., and most preferably between 620 and 700° C. to anneal the first and second layers. For example, the substrate may be heated to 650° C. to anneal the first and second layers. The anneal may be accomplished in the same process chamber as the deposition took place. The substrate may also be moved to a dedicated process chamber for the anneal or even to a different tool for the anneal. 
       FIG.  3    shows grain formation in the deposited layers. The first and/or second layer may comprise epitaxial grains  21  after heating the substrate to the third temperature. The grains  21  may have a length between 5 to 30 nm, preferable 10 to 20 nm. Grain formation may improve the electrical conductance of the layers. 
     The layers may function as an electrical channel in an integrated circuit. The electrical properties of the layers may be improved after the anneal at the third temperature. The electrical conductance of the layers may be improved. The layers may be used as the channel poly in a 3D NAND device for which the electrical conductance may be very critical for its functioning. The layers may be polycrystalline after heating the processing chamber to the third temperature. 
     The first and second precursor may comprise silicon atoms. Trisilane has three silicon atoms per molecule. Disilane has two silicon atoms per molecule. Silane has one silicon atom per molecule. The first precursor being trisilane or disilane may therefore have more silicon atoms per molecule than the second precursor being silane. 
     The substrate may be provided with a gap. For example, the gap  7  created in the first structure of the device  1  during a wet or dry etch process (see  FIG.  1   ). The gap may have a depth d between 1 to 100 micrometer and a width w between 0.01 to 1 micrometer. The first and second layers may be provided over the surface of the gap. The first and second layers may together form a conductive layer, for example for the poly channel of the 3D NAND device. 
     The method may comprise providing an etchant involving for example a halide chemistry to the processing chamber. When the uniformity of the gap is not sufficient, the etchant may improve the uniformity by etching more in the top of the gap then in the bottom of the gap. Also, when the gap was partially closed off in the top by the first and/or second layer and therefore hindering further processing the etchant may cause an etch back partially opening up the top of the gap. Also, the thickness of the first and second layer may be etched (e.g. trimmed) to the required thickness. 
     The etching may be accomplished with for example a batch reactor of a vertical furnace or a single wafer reactor. When a furnace is used the substrate  210  may be provided to a boat having space to accommodate 25 to 300 substrates. The boat with substrates may be moved into a reaction chamber of the reactor. The batch or alternatively a single wafer reactor may be constructed and arranged to provide a gaseous etchant to the reaction chamber for isotropic etching the first and second layers. For example, the reactor may be constructed to provide one or more gaseous etchants comprising a halide to the reaction chamber. 
     The halide may be selected from nitrogen trifluoride (NF 3 ), chloride (Cl 2 ), hydrogen chloride (HCl), hydrogen fluoride (HF), hydrobromic acid (HBr), boron chloride (BCl 3 ), or fluorine (F 2 ) for dry etching the first and/or second layer. The temperature in the reactor may be kept below 500° C., between 300 and 500° C. and preferably between 330 and 450° C. and the pressure in the reactor may be kept below 1 Torr. The reaction chamber may be kept substantially radical and/or ion free. A dry etch process may involve a remote plasma system, for example. 
     The etchant may be provided after introducing the first precursor into the processing chamber but before the second precursor is introduced in the processing chamber to deposit the second layer. In this way the relatively soft first layer may be etched before the relatively hard second layer is deposited improving the etch speed. 
     The etchant may also be provided in the processing chamber during deposition of the first layer. This may be done continuous so that the first precursor and the etchant are provided simultaneous or cyclic such that the first precursor and etchant are introduced alternatively into the processing chamber. 
     The etchant may be provided after introducing the second precursor into the processing chamber but before the anneal. In this way the second layer may be etched before the second layer is hardened by the anneal. 
     The etchant may also be provided in the processing chamber during deposition of the second layer as well. This may be done continuous so that the second precursor and the etchant are provided simultaneous or cyclic such that the second precursor and etchant are introduced alternatively into the processing chamber. 
     The dry etch of the first or second layer may, for example, be done with Cl2 at a temperature between 300 and 500° C. and preferably between 375 and 450° C. The etch rate of the first and/or second layer may be between 0.1 to 10 or around 1 nm/min at 410° C. with CL2. 
       FIG.  4    shows the uniformity of the layers deposited over the depth d of the gap  7  (in  FIG.  1   ) after a top etch may be applied. Dividing the thickness of the first and second layer in the bottom 10% (BTM) of the gap by the thickness of the first and second layer in the top 10% (TOP) of the gap may be a good indication of the deposition uniformity. In  FIG.  4    you may for example read out at bottom a layer thickness of 44.5 nm and in the top of 37.9 nm corresponding to a ratio of 1.17. If this ratio is between 0.7 and 1.3, preferably between 0.9 and 1.1 the deposition uniformity may be good. To have the same electrical properties over the length of the gap it may be important to have a good deposition uniformity. The electrical conductivity of the layers used as the channel poly in a 3D NAND device may then also be good. 
     The deposition step may include flow of a silicon precursor such as silane, disilane, trisilane, chlorosilane, dichlorosilane, trichlorosilane, tetrachlorosilane, methylsilane, dimethylsilane, trimethylsilane, tetramethylsilane, or a combination of the above, for example. The deposition step may also include a flow of a germanium precursor, such as germane, digermane, dichlorogermane, trichlorogermane, tetrachlorogermane, germanium alkoxide, or a combination of the above, for example. 
     Deposition of the first and/or second layers may also be done with multiple substrates simultaneously in batch in a reaction chamber of a vertical furnace. In batch a plurality of substrates may be provided to a wafer boat with a wafer handler and the wafer boat may be loaded with a lift into the processing chamber of a vertical furnace. The processing chamber may be heated to the first temperature. The processing chamber may be pumped down to a pressure between 0.01 and 1 Torr, and most preferably between 0.1 and 0.8 Torr. The first precursor may be introduced into the processing chamber to deposit the first layer on the substrate. Processing the substrates in batch with multiple, for example 25 to 300 substrates at the time has the advantage that one can take a long time for the processing while still having a good productivity for the tool. This may make it possible to lower the pressure during the deposition so that the uniformity improves of the layers when deposited in a gap. 
     Alternatively, the deposition of the first and/or second layers may be done with one substrate at the time in a single wafer reactor. In such a reactor only one substrate fits in the processing chamber at the time. The pressure in the processing chamber may be between 1 and 100 Torr to get sufficient productivity. 
     The first layer may also act as a seed layer for the second and subsequent layers. For example, the seed layer may be deposited by providing trisilane. The seed layer may help improving the quality and deposition of the subsequent layers, for example by keeping it amorphous before an anneal. 
     The first and/or second layer may be deposited via an Atomic Layer Deposition (ALD) process, a Chemical Vapor Deposition (CVD) process, or an epitaxial process, for example. The deposition step may occur by a thermal reaction, a plasma reaction, or a plasma enhanced reaction. 
     Optionally after the second layer is deposited but before the first and second layers are annealed the substrate may be heated to a fourth temperature between 300 and 500° C., preferable between 310 and 450° C. and even more preferable between 320 and 420° C.; and the first or a different precursor may be introduced into the processing chamber again to deposit a third layer. The third layer may have a thickness of 1 to 10 nanometer, preferably around 2 to 6 nanometer and most preferable around 3 nanometer. The first, second and third layer may thereafter be annealed at the third temperature. 
     The first and second layer may be doped with carbon. The carbon doping may be improving the formation of larger grains. The carbon doping may be improving the conductivity in the layers. The first and second layer may be doped with 0.1 to 4% preferably 0.2 to 3% and even more preferably 0.4 to 2% of carbon. The carbon dopant may be provided by co-flowing of a carbon comprising precursor during introducing the first and/or second precursor into the processing chamber. The carbon comprising precursor may for example be an alkane. The alkane may be ethylene (C 2 H 4 ). 
     The particular implementations shown and described are illustrative of the invention and its best mode and are not intended to otherwise limit the scope of the aspects and implementations in any way. Indeed, for the sake of brevity, conventional manufacturing, connection, preparation, and other functional aspects of the system may not be described in detail. Many alternative or additional functional relationship or physical connections may be present in the practical system, and/or may be absent in some embodiments. 
     It is to be understood that the configurations and/or approaches described herein are exemplary in nature, and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various acts illustrated may be performed in the sequence illustrated, in other sequences, or omitted in some cases. 
     The subject matter of the present disclosure includes all novel and nonobvious combinations and sub-combinations of the various processes, systems, and configurations, and other features, functions, acts, and/or properties disclosed herein, as well as any and all equivalents thereof.