Patent Publication Number: US-11050349-B2

Title: Coupled-inductor power-supply controller for operating a power supply in a reduced-power-dissipation mode

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a divisional of U.S. patent application Ser. No. 12/651,985, filed Jan. 4, 2010, now U.S. Pat. No. 9,755,520, which application is a continuation in-part of U.S. patent application Ser. No. 12/259,220, filed Oct. 27, 2008, now U.S. Pat. No. 7,786,711, which application is a continuation of U.S. patent application Ser. No. 11/519,516 filed Sep. 12, 2006, now U.S. Pat. No. 7,443,146, which claims the benefit of U.S. Provisional Patent Application Ser. No. 60/747,945, filed May 23, 2006. 
    
    
     BACKGROUND 
     A power supply may convert an input voltage having a first set of characteristics into an output voltage having another set of characteristics. For example, a power supply may convert 110 VAC from a power outlet into 9 VDC for powering or recharging the battery of a cell phone. 
     A DC-DC converter is a type of power supply that is widely used to supply DC power to electronic devices, such as computers, printers, and the like, and that is available in a variety of configurations for deriving a regulated DC output voltage from a DC source of input voltage. As a non-limiting example, a buck-mode or step-down DC-DC converter generates a regulated DC output voltage whose value is less than the value of the DC source voltage. A step-down DC-DC converter may include one or more power channels or phases, the outputs of which are combined at an output node for delivering a regulated stepped-down DC output voltage to a load. Each phase includes power switches and a current-flow path that includes a filter inductor. The power switches are, for example, controllably switched by a pulse-width modulation (PWM) signal produced by a PWM modulator to switchably connect a DC source voltage to one end of the filter inductor, a second end of which is connected to the output node. Alternatively, the power switches may be controllably switched by constant-on-time pulses, constant-off-time pulses, or other types of pulses. 
     In addition to regulator implementations which have no mutual magnetic coupling among the filter inductors, there are regulator configurations which provide magnetic coupling among the filter inductors. These ‘coupled-inductor’ DC-DC converters have become increasingly attractive for supplying power to portable electronic devices, such as, but not limited to, notebook computers, and the like, which may operate in a discontinuous current mode (DCM) during low or relatively light load (e.g., quiescent or ‘sleep’ mode) conditions to reduce power loss and preserve battery life. For DCM operation, the upper and lower MOSFETs of at least one respective power switching stage of the converter are turned off for part of the switching period, preventing polarity reversal of the inductor current, so that the inductor current is zero during part of the switching period, i.e. it is discontinuous, rather than a continuous, thereby reducing current to the output to accommodate the relatively light current demand during such low-load conditions. 
     A non-limiting example of a conventional dual-phase, coupled-inductor buck-mode regulator or DC-DC converter, in which the filter inductors of the respective phases are mutually coupled with one another, is diagrammatically illustrated in  FIG. 1 . The dual-phase regulator of  FIG. 1  comprises two phases that produce respective output currents i L1  and i L2 , which flow from phase nodes  115  and  215  of respective phases  110  and  210  through respective filter inductors L 1  and L 2 , which are mutually coupled with one another, such that a current magnetically induced in one phase by a switched or driven current flowing in the other stage flows in the same direction (from the phase node into the output node OUT) as the driven (inducing) current. These two currents are summed at an output node OUT to produce a composite or total output current I total . Output node OUT provides a regulated output voltage Vo for powering a device LOAD, such as the microprocessor of a notebook computer, through which a load current i o  flows. 
     In order to regulate the output voltage Vo, the voltage at the output node OUT is fed back to an error amplifier (EA)  310 , which is operative to compare the monitored output voltage Vo with a reference voltage VID. The voltage-difference output Comp of the error amplifier  310  is supplied to a power-supply controller  315 . For example, the controller  315  is operable to control the pulse widths of associated streams of pulse-width-modulation (PWM) waveforms that are applied by respective PWM generators within the controller to driver circuits, the outputs of which are coupled to the gates of, and control the on/off switching times of, the upper and lower switching devices (MOSFETs Q 11 /Q 21  and MOSFETs Q 12 /Q 22 ) of the phases  110  and  210 . In an example application, the PWM waveforms are sequenced and timed such that the interval between rising edges (or in some implementations, falling edges) thereof is constant to substantially equalize the output currents i L1  and i L2  of the two power channels. 
     In addition to monitoring the output voltage Vo, error amplifier  310  may also monitor the sum of the phase currents i L1 +i L2  via respective sense resistors Rsn 1  and Rsn 2 , which are coupled between the phase nodes  115  and  215  and a first, non-inverting (+) input  321  of a (K gain) transconductance amplifier  320 . Amplifier  320  has a second, inverting (−) input  322  coupled to the output node OUT, and a sense capacitor Csns connected across its inputs. The amplifier  320  allows the sum of the phase currents to be used to regulate the output resistance of the power supply according to a technique commonly known as droop regulation or load-line regulation. The voltage output Vdroop of the amplifier  320  is coupled to a first input  331  of a summer  330 , a second input  332  of which is coupled to the output node OUT. The Vdroop voltage output (which is typically negative) of amplifier  320  is added to the output voltage Vo to provide a difference voltage Vdiff that is coupled to a first, inverting (−) input  311  of error amplifier  310 . The second, non-inverting (+) input  312  of error amplifier  310  is coupled to receive the reference voltage VID. As described above, the output voltage Comp of error amplifier  310  is used by the controller  315  to control the pulse widths of the PWM waveforms that control the on/off switching of the upper and low MOSFETs of the phases  110  and  210 . 
     Examples of these PWM waveforms are shown in  FIG. 2  as including a first PWM waveform PH 1 , which is used to control the on/off switching of the upper MOSFET switch Q 11  of the first phase  110 , and a second PWM waveform PH 2 , which is used to control the on/off switching of the upper MOSFET switch Q 21  of the second phase  210 . For balanced-phase operation, the frequencies of the two PWM waveforms are substantially the same and the times of occurrence of the turn-on pulses Q 11 -ON of the first PWM waveform PH 1  are midway between the times of occurrence of the turn-on pulses Q 21 -ON of the second PWM waveform PH 2 , and vice versa. That is, the turn-on pulses Q 11 -ON are spaced approximately 360°/N=180° from the turn-on pulses Q 21 -ON, where N=2=the number of power-supply phases. During the intervals that the pulses of the waveforms PH 1  and PH 2  are high, MOSFETs Q 11  and Q 21  are turned on thereby, so that increasing or ramping up segments i L1-1  and i L2-1  of respective currents i L1  and i L2  flow therethrough and, via phase nodes  115  and  215 , through mutually coupled inductors L 1  and L 2  to the output node OUT. 
     As further shown in  FIG. 2 , when the turn-on pulse Q 11 -ON of the PWM waveform PH  1  goes low, a PWM waveform V GS_Q12 , which is used to control the on/off switching of the lower MOSFET switch Q 12  of the first phase  110 , transitions high for a prescribed period Q 12 -ON, corresponding to the pulse-width interval of PWM waveform V GS_Q12 . With MOSFET switch Q 12  turned on during this interval, the inductor current i L1  of the first channel gradually decreases or ramps down to zero from its peak value at the end of the duration of the turn-on pulse Q 11 -ON of PWM waveform PH 1 , as shown at i L1-2 . The ramping down portion i L1-2  of the output current i L1  is supplied by a portion i S12-1  of a current i S12  that flows from ground through the source-drain path of the active MOSFET Q 12  to phase node  115  and into the inductor L 1 . 
     In a like manner, when the turn-on pulse Q 21 -ON of the PWM waveform PH 2  goes low, a PWM waveform V GS_Q22 , which is used to control the on/off switching of the lower MOSFET switch Q 22  of the second phase  210 , transitions high for a prescribed period Q 22 -ON corresponding to the pulse-width interval of PWM waveform V GS_Q22 . With MOSFET switch Q 22  turned on during this interval, the inductor current i L2  of the second phase gradually ramps down to zero from its peak value at the end of the duration of the turn-on pulse Q 21 -ON of PWM waveform PH 2 , as shown at i L2-2 . The ramping down portion i L2-2  of the output current i L2  is supplied by a portion i S22-1  of a current i S22  that flows from ground through the source-drain path of the active MOSFET Q 22  to phase node  215  and into the inductor L 2 . 
     As pointed out above, because the inductor L 1  of the phase  110  is mutually coupled with the inductor L 2  of the phase  210 , the current i L1  driven through inductor L 1  as a result of the successive PWM-controlled turn on of the MOSFETs Q 11  and Q 12  magnetically induces a current in the inductor L 2  of the second phase, shown in the current waveform i L2  of  FIG. 2  as induced current i L2-3 . Because the upper MOSFET Q 21  of the second phase is off during this time (PH 2  is low), and the polarity of its inherent body-diode is oriented so as to inherently block the flow of current therethrough from the input voltage supply rail Vin to phase node  215 , no current is drawn through the upper MOSFET Q 21  to supply the induced current i L2-3 . MOSFET Q 22  of the second phase is also off at this time, since its switching PWM waveform V GS_Q22  is low. However, the orientation of its body-diode allows the flow of a current i S22-2  from ground and through this body-diode as a body-diode current i Q22  to phase node  215  and into inductor L 2  as the induced current i L2-3 . 
     In like manner, the current i L2  through inductor L 2  that results from the successive PWM-controlled turn on of the MOSFETs Q 21  and Q 22  magnetically induces a current in the inductor L 1  of the first phase, shown in the current waveform i L1  of  FIG. 2  as induced current i L1-3 . Because the upper MOSFET Q 11  of the first phase is off and the polarity of its inherent body-diode is oriented so as to inherently block the flow of current therethrough from the input voltage supply rail Vin, no current is drawn through the upper MOSFET Q 11  to provide the induced current i L1-3 . However, even though the lower MOSFET Q 12  of the first phase is off because its switching PWM waveform V GS_Q12  is low, the polarity orientation of its body-diode is such as to allow the flow of a current i S12-2  from ground and through the body-diode as a body-diode current i D12  to phase node  115  and into inductor L 1  as the induced current i L1-3 . 
     Unfortunately, because the two induced currents i L1-3  and i L2-3  are supplied by way of respective currents i Q12  and i Q22  through the body diodes of lower MOSFETs Q 12  and Q 22 , these induced currents may cause significant conduction losses in these MOSFETs. 
     SUMMARY 
     An embodiment of a power-supply controller includes first and second circuits. The first circuit is operable to cause a first current to flow through a first phase of a power supply. And the second circuit is operable to cause the second phase of the power supply to operate in a reduced-power-dissipation mode for at least a portion of a time period during which a second current magnetically induced by the first current flows through the second phase. For example, the second circuit may cause the second phase to operate in a reduced-power-dissipation mode by bypassing a diode (e.g., a standalone circulation diode or the inherent diode of a circulation transistor) of the second phase with a switch or other low-impedance path, or by activating the circulation transistor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  diagrammatically illustrates the overall circuit architecture of a non-limiting example of a conventional dual-phase, coupled inductor, buck-mode regulator, in which the filter inductors of the regulator&#39;s phases are mutually coupled with one another; 
         FIG. 2  shows waveform diagrams associated with DCM operation of the conventional dual-phase, buck-mode regulator of  FIG. 1 ; 
         FIG. 3  is a reduced complexity, diagrammatic illustration of a first embodiment of a buck-mode regulator for the case of dual-phase DCM operation; 
         FIG. 4  shows waveform diagrams associated with DCM operation of the dual-phase, buck-mode regulator of  FIG. 3 ; 
         FIG. 5  is a reduced complexity, diagrammatic illustration of a second embodiment of a buck-mode regulator for the case of single-phase DCM operation; 
         FIG. 6  shows waveform diagrams associated with the single-phase DCM operation of the buck-mode regulator of  FIG. 5 ; 
         FIG. 7  is a reduced complexity, diagrammatic illustration of a third embodiment of a buck-mode regulator for the case of a single-phase CCM (continuous mode) operation; 
         FIG. 8  shows waveform diagrams associated with the single-phase CCM operation of the buck-mode regulator of  FIG. 7 . 
         FIG. 9  is a reduced complexity, diagrammatic illustration of a fourth embodiment of a buck-mode regulator. 
         FIG. 10  is a reduced complexity, diagrammatic illustration of a fifth embodiment of a buck-mode regulator. 
     
    
    
     DETAILED DESCRIPTION 
     In general, in an embodiment, the functionality of a regulator&#39;s controller is augmented, such that the waveforms it produces to control the on/off switching of the low-side MOSFETs of the power-supply phases include auxiliary pulse signals having widths that at least partially coincide with the durations of the induced currents in the phases. As a result, rather than flowing as respective body-diode currents through the body-diodes of the low-side MOSFETs, the induced currents flow instead, at least part of the time, through the turned-on low-side MOSFETs, or through other lower-impedance bypass paths, thereby reducing or eliminating conduction losses in their body-diodes. 
     Attention is initially directed to  FIG. 3  which is a reduced complexity, diagrammatic illustration of a first embodiment for the case of a dual-phase, discontinuous conduction mode (DCM) operation of a buck-mode type of regulator, and to  FIG. 4 , which shows a set of waveform diagrams associated with the operation of  FIG. 3 . More particularly, the circuit architecture diagram of  FIG. 3  shows two phases that may be similar to the phases of the regulator architecture of  FIG. 1 , but omits an illustration of the feedback connections to the controller, to simplify the drawing. 
     Instead, the augmentation of the functionality of the supervisory controller is represented in  FIG. 3  by a pair of OR gate functions OR- 100  and OR- 200 , that are employed by the power-supply controller to insert additional or auxiliary on-time pulse-width portions into the respective switching waveforms V GS_Q12  and V GS_Q22  (PWM waveforms in this embodiment), and are effective to turn on the low-side MOSFETs Q 12  and Q 22  of respective phases  110  and  210  at times that at least partially coincide with the durations of the induced currents in the filter inductors L 1  and L 2 . Although shown as OR gates, the OR gate functions OR- 100  and OR- 200  may be implemented with any other suitable circuitry. 
     To this end, the OR gate function OR- 100  for phase  110  has a first input coupled to monitor the turning-off of the upper switching MOSFET Q 11 , which occurs at a high-to-low transition of the pulse Q 11 -ON of PWM waveform PH 1 , and a second input coupled to monitor the turning-on of the upper switching MOSFET Q 21  of the opposite phase  210 , which occurs at a low-to-high transition of the pulse Q 21 -ON of PWM waveform PH 2 . When either of these events occurs, the PWM waveform V GS_Q12 , which is used to control the on/off switching of lower switching MOSFET switch Q 12  of phase  110 , transitions from low-to-high. 
     In particular, in response to a high-to-low transition of the pulse Q 11 -ON of PWM waveform PH 1 , the PWM waveform V GS_Q12  transitions from low-to-high for a first pulse width interval Q 12 -ON- 1 ; in addition, in response to a low-to-high transition of the pulse Q 21 -ON of PWM waveform PH 2 , PWM waveform V GS_Q12  transitions from low-to-high for a second or auxiliary pulse width interval Q 12 -ON- 2 . As a consequence, both the ramping down portion i L1-2  of the driven, i.e., non-induced current (i L1-1 +i L1-2 ) through inductor L 1  and the entirety of the current i L1-3  induced therein by the non-induced current (i L2-1 +i L2-2 ) flowing through inductor L 2  will flow through the source-drain path of active lower MOSFET Q 12 . None of the induced current flowing through inductor L 1  will flow as a body-diode current iQ 12  through the body-diode of MOSFET Q 12 , so as to eliminate an associated conduction loss in the body-diode of MOSFET Q 12 . To control the turn-off of the lower MOSFET switch Q 12 , its source-drain current i S12  is monitored by conventional current monitoring circuitry, examples of which are disclosed in U.S. application Ser. No. 12/189,112, which is incorporated by reference. Whenever the source-drain current i S12  goes to zero, the PWM waveform V GS_Q 12  transitions from high-to-low, so that the lower MOSFET switch Q 12  is turned off. This prevents a reverse current from flowing from the LOAD or from the filter capacitors back through the first phase  110 . 
     In a similar manner, the OR gate function OR- 200  for phase  210  has a first input coupled to monitor the turning-off of the upper switching MOSFET Q 21 , which occurs at a high-to-low transition of the pulse Q 21 -ON of PWM waveform PH 2 , and a second input coupled to monitor the turning-on of the upper switching MOSFET Q 11  of the opposite power switching stage  110 , which occurs at a low-to-high transition of the pulse Q 11 -ON of PWM waveform PH 1 . When either of these events occurs, the PWM waveform V GS_Q22 , which is used to control the on/off switching of the lower switching MOSFET switch Q 22  of the phase  210 , transitions from low-to-high. 
     More particularly, in response to a high-to-low transition of the pulse Q 21 -ON of PWM waveform PH 2 , the PWM waveform V GS_Q22  transitions from low-to-high for a first pulse width interval Q 22 -ON- 1 ; in addition, in response to a low-to-high transition of the pulse Q 11 -ON of PWM waveform PH 1 , PWM waveform V GS_Q22  transitions from low-to-high for a second or auxiliary pulse width interval Q 22 -ON- 2 . As a consequence, both the ramping down portion i L2-2  of the non-induced current (i L2-1 +i L2-2 ) through inductor L 2  and the entirety of the current i L2-3  induced therein by the non-induced current (i L1-1 +i L1-2 ) flowing through inductor L 1  will flow through the source-drain path of active lower MOSFET Q 22 . None of the induced current flowing through inductor L 2  will flow as a body-diode current i D22  through the body-diode of MOSFET Q 22 , so as to eliminate an associated conduction loss in the body-diode of MOSFET Q 22 . To control the turn-off of the lower MOSFET switch Q 22 , its source-drain current i S22  is monitored by conventional monitoring circuitry. Whenever the source-drain current i S22  goes to zero, the PWM waveform V GS_Q22  transitions from high-to-low, so that the lower MOSFET switch Q 22  is turned off. 
     Still referring to  FIGS. 3 and 4 , alternate embodiments are contemplated. For example, the power-supply controller may not activate the low-side MOSFET Q 22  for the entire duration of the induced current I L2-3  through the inductor L 2 , thus reducing, but not eliminating, the time during which an induced current flows through the body diode of Q 22 . This may be due to an inherent or intentional circuit delay that prevents Q 22  from turning on until a delay time after Q 11  turns on. Or, this may be due to the power-supply controller inactivating Q 22  in response to I L2-2  being below a threshold voltage that is greater than zero, such that Q 22  is off for a period of time before I L2-3  becomes equal to zero. In another embodiment, the power supply controller may activate Q 22  for longer than the duration of I L2-3 . In yet another embodiment, the power supply controller may activate Q 22  before the start of the I L2-3  duration and inactivate Q 22  before the end of the I L2-3  duration, or may activate Q 22  after the start of the I L2-3  duration and inactivate Q 22  after the end of I L2-3  duration. In another embodiment, the power supply controller may only partially activate Q 22  such that is not full on, but is sufficiently on to bypass its body diode. Similar alternate embodiments are contemplated for the low-side MOSFET Q 12 , for example, such that the power-supply controller may not activate the low-side MOSFET Q 12  for the entire duration of the induced current I L1-3  through the inductor L 1 , thus reducing, but not eliminating, the time during which an induced current flows through the body diode of Q 12 . Consequently, in such alternate embodiments, the conduction losses in the body-diodes of the MOSFETS Q 12  and Q 22  may be reduced but not eliminated. Furthermore, although shown as a two-phase buck converter, the power supply of  FIG. 3  may have more than two phases and may be other than a buck converter. Moreover, where the power supply has more than two phases, then at least one of the phases may be magnetically uncoupled from the other phases, or the phases may be grouped such that each phase may be magnetically coupled to the other phases within its group but magnetically uncoupled from phases outside of its group. In addition, although shown coupled to ground, the low-side transistors Q 12  and Q 22  (and also the filter capacitors and the load) may be coupled to a negative input voltage. Furthermore, instead of sourcing current to the LOAD, one may modify the power supply to sink current from the LOAD, in which case the transistors Q 11  and Q 21  may be the circulation transistors, and at least some of the transistors Q 11 , Q 12 , Q 21 , and Q 22  may be replaced with PMOS transistors. Also, instead of being a PWM controller, the controller may be a constant-on-time, constant-off-time, or another type of controller. 
     The circuit architecture diagram of  FIG. 5  and its associated set of waveforms shown in  FIG. 6  correspond to the case of providing normal PWM switching signals for only one of the power-supply phases—phase  110  in this embodiment—of the dual-phase discontinuous conduction mode converter described above in conjunction with  FIGS. 3 and 4 . In this second embodiment, there is no PH 2  pulse for turning on the upper MOSFET switch Q 21  of the phase  210 . As such, the inputs to OR gate functions OR- 100  and OR- 200  associated with the turn-on and turn-off of MOSFET Q 21  are zero. Moreover, since there is no PH 2  pulse that initiates the flow of a non-induced current IL 2  through the inductor L 2 , the PWM waveform V GS_Q22  does not transition from low-to-high for a prescribed duration Q 22 -ON- 1  associated with the ramp down of a (non-existent) non-induced portion of current i L2  through the inductor L 2  at the end of the (non-existent) PH 2  pulse (since there is no non-induced current i L2  flowing through inductor L 2  to begin with). As a consequence, the PWM waveform V GS_Q12  for lower MOSFET switch Q 12  of the phase  110  does not require an auxiliary pulse-width portion (shown at Q 12 -ON- 2  in  FIG. 4 ), to turn on the lower MOSFET switch Q 12  of phase  210  to accommodate an (nonexistent) induced current through inductor L 1 . 
     However, in this second, single-active-phase DCM embodiment of  FIGS. 5 and 6 , there is an induced current i L2-3  that flows through the inductor L 2  of the power-supply phase  210 , as a result of the flow of the non-induced current i L1  through inductor L 1  during the normal operation of the upper and lower MOSFETS Q 11  and Q 12  of the phase  110 . To prevent this induced current i L2-3  from being supplied by way of the body-diode of the lower MOSFET Q 22  of the phase  210 , the pulse-width portion Q 22 -ON- 2  of the PWM waveform V GS_Q22  of the first, dual-active-phase DCM embodiment  FIGS. 3 and 4  is used in this second, single-active-phase DCM embodiment of  FIGS. 5 and 6  to turn on, and to provide for the flow of source-drain current i S22  through, the active lower MOSFET Q 22  while the induced current i L2-3  flows in the second phase  210 . The time of occurrence and duration of the pulse width Q 22 -ON- 2  of PWM waveform V GS_Q22  may be the same as the time of occurrence and duration of the induced current i L2-3 , as in the first embodiment of  FIGS. 3 and 4 . As a result, as in the first embodiment of  FIGS. 3 and 4 , all of the induced current (i L2-3 =i S22-2 ) flowing through inductor L 2  will flow through turned-on low side MOSFET Q 22 , rather than through its body-diode as a body-diode current iQ 22 , so as to eliminate an associated conduction loss in the body-diode of MOSFET Q 22 . 
     Alternate embodiments similar to at least some of those discussed above in conjunction with  FIGS. 3 and 4  are contemplated for the circuitry and techniques of  FIGS. 5 and 6 . For example, the power-supply controller may not activate the low-side MOSFET Q 22  for the entire duration of the induced current I L2-3  through the inductor L 2 , thus reducing, but not eliminating, the time during which an induced current flows through the body diode of Q 22 . Consequently, in such alternate embodiments, the conduction loss in the body-diode of MOSFET Q 22  may be reduced but not eliminated. 
       FIG. 7  is a reduced complexity, diagrammatic illustration of a third embodiment for the case of a single-active-phase CCM operation of the buck-mode regulator, while  FIG. 8  shows a set of waveform diagrams associated with the operation of the circuit architecture of  FIG. 7 . For CCM single-active-phase operation, the upper and lower MOSFETs Q 11  and Q 12  of the power-supply phase  110  are turned on and off in a complementary manner, so that a conductive path for current flow through the inductor L 1  and one or the other of the respective terminals (Vin and ground) of the input power supply will be continuously provided through one or the other of these MOSFETs. Thus, the inductor current i L1  through the filter inductor L 1  is repetitively ramped up and down between positive and negative peaks thereof, as the complementary PWM waveforms PH 1  and V GS_Q12  alternately turn MOSFETs Q 11  and Q 12  on and off, as shown in the waveform diagram of  FIG. 8 . 
     Similar to the diagrammatic illustrations of the respective dual-active-phase and single-active-phase DCM embodiments of  FIGS. 3 and 5 , the circuit architecture diagram of  FIG. 7  is substantially the same as the DCM buck-mode regulator of  FIGS. 3 and 5 , but lacks an illustration of the feedback connections (e.g.,  FIG. 1 ) to the power-supply controller to simplify the drawing. Instead, as in the circuit architecture diagrams of  FIGS. 3 and 5 ,  FIG. 7  shows a control diagram representative of the control function that is executed by the power-supply controller, to control the turn-on and turn-off times of the high-side MOSFET Q 11  and the low-side MOSFET Q 12  of the phase  110  by respective PWM complementary switching waveforms PH 1  and V GS_Q12 , as well as the OR gate function OR- 200  that is used to control auxiliary turn-on and turn-off times of the low side MOSFET Q 22  of the inactive phase  210 , in accordance with PWM waveform V GS_Q22 , at times that coincide with the durations of currents magnetically induced in the inductor L 2  of the phase  210 . 
     More particularly, as in the single-active-phase DCM regulator embodiment of  FIGS. 5 and 6 , in the single-active-phase CCM regulator embodiment of  FIGS. 7 and 8 , there is no PH 2  pulse for turning on the upper MOSFET switch Q 21  of the phase  210 . As such, the input to OR-gate function OR- 200  associated with the turn-off of MOSFET Q 21  is zero. Moreover, since there is no PH 2  pulse that initiates the flow of a non-induced current I L2  through the inductor L 2 , the PWM waveform V GS_Q22  does not transition from low-to-high for a prescribed duration Q 22 -ON- 1  associated with the ramp down of a (nonexistent) non-induced portion of current i L2  through the inductor L 2  at the end of the (non-existent) PH 2  pulse (since there is no non-induced current i L2  flowing through inductor L 2  to begin with). As a consequence, the PWM waveform V GS_Q12  for the lower MOSFET switch Q 12  of power switching stage  110  does not require an auxiliary pulse-width portion (shown at Q 12 -ON- 2  in  FIG. 4 ), to turn on the lower MOSFET switch Q 12  of the phase  210  to accommodate a (non-existent) induced current through inductor L 1 . 
     However, as in the single-active-phase DCM embodiment of  FIGS. 5 and 6 , there is an induced current i L2-3  that flows through the inductor L 2  as a result of the flow of the non-induced current i L1  through inductor L 1  during the normal operation of the upper and lower MOSFETS Q 11  and Q 12  of phase  110 . To prevent this induced current i L2-3  from being supplied by way of the body-diode of the lower MOS FET Q 22  of the phase  210 , the pulse-width portion Q 22 -ON- 2  of the PWM waveform V GS_Q22  of  FIG. 4  is again used to turn on and provide for the flow of source-drain current i S22  through the active lower MOSFET Q 22  for the duration of the induced current i L2-3 . The time of occurrence and duration of the pulse width Q 22 -ON- 2  of PWM waveform V GS_Q22  is substantially the same as the time of occurrence and duration of the induced current i L2-3 , as in the embodiments of  FIGS. 3-6 . As a result, as in the embodiments of  FIGS. 3-6 , all of the induced current (i L2-3 =i S22-2 ) flowing through inductor L 2  will flow through turned-on low side MOSFET Q 22 , rather than through its body-diode as a body-diode current iQ 22 , eliminating conduction loss in the body-diode of MOSFET Q 22 . 
     Alternate embodiments similar to at least some of those discussed above in conjunction with  FIGS. 3-6  are contemplated for the circuitry and techniques described in conjunction with  FIGS. 7 and 8 . For example, the power-supply controller may not activate the low-side MOSFET Q 22  for the entire duration of the induced current I L2-3  through the inductor L 2 , thus reducing, but not eliminating, the time during which an induced current flows through the body diode of Q 22 . Consequently, in such alternate embodiments, the conduction loss in the body-diode of MOSFET Q 22  may be reduced but not eliminated. 
       FIG. 9  is a diagrammatic illustration of another embodiment of a multistage coupled-inductor buck converter, where like numbers are used to reference like components relative to  FIGS. 1-8 . 
     In addition to the N phases  110 ,  210 , . . . , and N 10 , the buck converter includes a power-supply controller  400 , current sensors  402   1 - 402   N , and a filter capacitor  404 . The current sensors  402   1 - 402   N  may be conventional, such as disclosed in U.S. application Ser. No. 12/189,112, which is incorporated by reference. 
     A difference between the embodiments of  FIGS. 3-8  and the embodiment of  FIG. 9  is that the embodiment of  FIG. 9  uses current sensors  402  instead of or in addition to an OR logic function to determine when to switch on and off the low-side, i.e., circulating transistors Q 12 -ON 2 . 
     For example, the controller  400  may activate Q 12  for the entire time during which the sensor  402   1  senses a forward current (i.e., in this embodiment, a current flowing toward the load) flowing in the phase  110  while Q 11  is open, or for any portion of this time. This allows an induced or a decaying non-induced current to flow through the active transistor Q 12  instead of through the body diode of the inactive transistor Q 12 , and thus allows a reduction in the conduction losses in the transistor Q 12 . 
     Because a reverse phase current (i.e., in this embodiment, a current flowing away from the load) may be undesirable because it discharges the filter capacitor  404 , the controller  400  may turn off Q 12  in response to sensing a zero current, a reverse current, or a forward current below a predetermined threshold flowing through phase  110  while the transistor Q 11  is open. 
     In another embodiment, the controller  400  may turn off Q 12  in response to sensing a zero current, a reverse current, or a forward current below a predetermined threshold flowing through a phase other than the phase  110  while the transistor Q 11  is open. For example, the controller  400  may turn off Q 12  while Q 11  is open in response to sensing a zero current, a reverse current, or a forward current below a predetermined threshold in each of the other phases  210 -N 10 . The reasoning behind this is that when no forward currents are flowing through the other phases  210 -N 10 , then no current is magnetically induced in the phase  110 . 
     The controller  400  may control the circulation transistors Q 22 -QN 2  in a similar manner. 
     Alternate embodiments of the power supply of  FIG. 9  are contemplated. For example, embodiments similar to at least some of those discussed above in conjunction with  FIGS. 3-8  are contemplated. In addition, although described as being coupled to a negative supply Vss, the low-side transistors Q 12 -QN 2  may be coupled to ground, or to any other voltage lower than Vin. 
       FIG. 10  is a diagrammatic illustration of another embodiment of a multistage coupled-inductor buck converter, where like numbers are used to reference like components relative to  FIGS. 1-9 . 
     This embodiment is similar to that of  FIG. 9 , except that each phase  110 ,  210 , . . . , N 10  respectively includes a shunt transistor Q 13 -QN 3  that is coupled in parallel with a respective low-side transistor Q 12 -QN 2  but that receives a separate gate-drive signal from the controller  400 . 
     Therefore, to allow an induced or decaying current flowing in the phase  110  to bypass the body diode of the low-side transistor Q 12 , instead of activating Q 12 , the controller  400  may activate the transistor Q 13 . Or, the controller  400  may simultaneously activate both the transistors Q 12  and Q 13  to further lower the conduction losses caused by a decaying or induced current flowing in phase  110 —in this latter embodiment, the gates of the transistors Q 12  and Q 13  may receive the same drive signal from the controller  400 . Of course the controller  400  deactivates the transistor Q 13  while the high-side transistor Q 11  is closed. 
     The controller  400  may operate the shunt transistors Q 23 -QN 3  in a similar manner. 
     Shunt transistors similar to the shunt transistors Q 13 -QN 3  may also be included in the embodiments of  FIGS. 3-8 . 
     Still referring to  FIG. 10 , alternate embodiments are contemplated. For example, at least some of the alternate embodiments contemplated for the circuitry and techniques disclosed above in conjunction with  FIGS. 3-9  are also contemplated for the embodiment of  FIG. 10 . Furthermore, each phase may have more than one shunt transistor coupled in parallel with the low-side transistor, or may have one or more shunt transistors coupled in parallel with the high-side transistor (to lower the on resistances of the high-side transistors). Moreover, fewer than all of the phases may include a shunt transistor. 
     As will be appreciated from the foregoing description, the problem of body-diode conduction loss in a coupled-inductor DC-DC converter may be successfully reduced or eliminated, by incorporating into the MOSFET switching control waveforms, through which the regulator&#39;s controller controls on/off switching of the low-side (or shunt) MOSFETs of the multiple power stages, having auxiliary on-time pulse width portions that at least partially coincide with the durations of the induced currents in the power-supply phases. As a result, rather than being forced to flow as respective body-diode currents through the body-diodes of the MOSFETs for their entire duration, the induced currents (or at least portions thereof) will flow through the turned-on MOSFETS (or shunt MOSFETS) themselves for at least part of their durations, thereby reducing or eliminating conduction losses in the low-side-transistor body-diodes. 
     While several embodiments are described, it is to be understood that the disclosure is not limited thereto but is susceptible to numerous changes and modifications, and we therefore do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications.