Patent Publication Number: US-6992924-B2

Title: Magnetic memory and method for optimizing write current in a magnetic memory

Description:
DETAILED DESCRIPTION OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to methods for optimizing a write current in a magnetic memory device and to a magnetic memory device. More particularly, the present invention relates to methods for optimizing a write current in a magnetic random access memory (hereinafter referred to as MRAM) and to a magnetic memory device. 
   2. Background Art 
   Currently, an MRAM is receiving attention as a nonvolatile storage. The MRAM uses magnetic tunneling junction (hereinafter referred to as “MTJ”) device as its magnetic memory element. 
     FIG. 3  is a sectional view illustrating an exemplary structure of an MRAM memory cell. The memory cell shown in  FIG. 3  has an MTJ device  12  and a transistor  50 . The transistor  50  is formed on the main surface of a p-type semiconductor substrate  100  typically formed of silicon. On the main surface of the semiconductor substrate  100 , n-type diffusion regions  101  and  102  are formed with a predetermined gap provided there between. A read word line RWL is formed between the n-type diffusion regions  101  and  102  on the semiconductor substrate  100 . The read word line RWL corresponds to the gate of the transistor  50 . Device isolation regions  103  and  104  are formed between the transistor  50  and other adjoining transistors (not shown). 
   The n-type diffusion region  101  is connected to a metal wire  107  through a contact hole  105 . The metal wire  107  is connected to a ground potential node  130 . The write word line WWL is formed above the metal wire  107  with an insulating film (not shown) between them. The n-type diffuision region  102  is connected to a metal wire  108  through a contact hole  106 . The metal wire  108  is further connected to a metal wire  110  through a contact hole  109 . The metal wire  110  is connected to a pad metal  112  through a contact hole  111 . The pad metal  112  is a conductor for connecting the MTJ device  12  and the metal wire  110 . The MTJ device  12  is formed on the pad metal  112 . The MTJ device  12  includes a ferromagnetic free layer  120 , an insulating layer  121  and a ferromagnetic pinned layer  122 . The pinned layer  122  is designed to have a fixed magnetization direction so that the magnetization can not be reversed. The magnetization direction of the free layer  120  will be identical to or opposite from that of the pinned layer  122  according to data to be stored. A bit line BL is formed on the MTJ device  12 . 
   The read operation of the MRAM memory cell described above will now be explained. 
   In a read operation, the read word line RWL is selected, and the transistor  50  turned ON. This causes the MTJ device  12  to be connected to a ground potential node Vss. At this time, a sense current passes through the bit line BL. The resistance of the MTJ device  12  is low when the direction of the magnetic field of the free layer  120  is the same as that of the pinned layer  122 , while it is high when the direction of the magnetic field thereof is opposite from that of the pinned layer  122 . Thus, data stored in a memory cell can be read by detecting the current through the MTJ device  12  or the voltage drop across the MTJ device  12 . 
   The write operation of the MRAM will now be explained. 
   In a write operation, a write word line current I w  passes through a write word line WWL, and a write bit line current I B  passes through the bit line BL. The read word line RWL is not selected, so that the transistor  50  is OFF. 
     FIG. 4  illustrates the switching of the magnetization direction of the free layer  120 . Referring to  FIG. 4 , the write bit line current I B  generates a bit line magnetic field in the direction of an easy magnetization axis of the free layer  120 . The write word line current I W  generates a word line magnetic field in the direction of a hard magnetization axis of the free layer  120 . The word line magnetic field lowers the intensity of the bit line magnetic field required for changing the magnetization direction. 
     FIG. 5  shows an asteroid curve illustrating a critical magnetic field for switching the magnetization direction. Referring to  FIG. 5 , the axis of abscissa indicates a bit line magnetic field H x  generated by the write bit line current I B , while the axis of ordinate indicates a word line magnetic field H y  generated by the write word line current I W . If a magnetic field H x +H y  corresponding to the region inside the asteroid curve is generated, then the magnetization direction of the free layer  120  is not reversed, and the write operation is not performed. If a magnetic field H x +H y  corresponding to the region outside the asteroid curve is generated, then the magnetization direction of the free layer  120  is determined by the magnetic field, and the write operation is performed. 
   One of the challenges to developing MRAMs is a large current required for generating the magnetic field in the write operation. For instance, the power consumed for reading performed every 10 ns in an MRAM is typically 5 mW. The same MRAM consumes 40 mW for writing under the same condition, spending far more power than in the read operation. In this case, a power source voltage is 2.5 V. Hence, the averaged value of the write current (write bit line current I B  +write word line current I W ) in the write operation is 16 mA. In actual operations, the write current flows for 2.5 ns during a write operation, so that the actual write current is 64 mA. In the write operation, therefore, much power is consumed and noise is generated, due to a write current with a large peak, leading to a possibility of a circuit malfunction. 
     FIGS. 6 and 7  are functional block diagrams illustrating the constructions related to the write operation of a memory cell array in the MRAM. In the twin cell type MRAM shown in  FIG. 6 , bit lines BLT and BLC are connected to each write circuit WC. The bit lines BLT and BLC are interconnected outside the memory cell array. The twin cells are disposed at the intersections of the bit lines BLT, BLC and the write word lines WWL. In a one transistor and one MTJ device type MRAM shown in  FIG. 7 , a bit line BL is connected between a write circuit WC 1  and a write circuit WC 2  disposed opposite from the write circuit WC 1 . The memory cells are disposed, corresponding to the intersections of the write word lines WWL and the bit lines BL. The MRAM shown in  FIGS. 6 and 7  includes n bit lines per word. In response to a write address signal, one write word line and n bit lines are selected, and data is written to the memory cells located at the intersections of the write word line and the n bit lines. Thus, in the write operation, the write bit line current I B  passes through all the selected n bit lines as well as the write word line current I w  passing through the selected write word line. This means that the consumed power increases as the number of bit lines per word increases, and the probability of occurrence of noise increases accordingly. The write current should be preferably smaller to suppress power consumption and noise; however, an excessively small write current prevents a write operation from being accomplished. 
   SUMMARY OF THE INVENTION 
   According to one aspect of the present invention, there is provided a method for optimizing write current in a magnetic memory having a plurality of bit lines, a plurality of word lines crossing the bit lines, and a plurality of memory cells disposed at intersections of the bit lines and the word lines, each of the memory cells including a free layer with reversible magnetization and a pinned layer with fixed magnetization, the method including a step for determining a distance r B  from the bit lines to the free layers, a distance r W  from the word lines to the free layers, and a number n of the bit lines through which write bit line current I B  passes in a write operation, and a step for determining the write bit line current I B  and the write word line current I W  so as to minimize the write current I T  by using expression (1) representing an asteroid curve expressed by a bit line magnetic field H x  generated by the bit line current I B , a word line magnetic field H y  generated by the write word line current I W  passing through the word line in the write operation, and a predetermined constant H K , expression (2) representing write current I T  obtained by adding the write bit line current I B  and the write word line current I W , expression (3) representing the bit line magnetic field H x  generated by the bit line current I B  by using a predefined coefficient a, and expression (4) representing the word line magnetic field H y  generated by the word line current I W  by using the predefined coefficient a:
 
[Expression 3]
                 H   x     2   3       +     H   y     2   3         =     H   k     2   3               (   1   )                 I   T     =       n   ⁢           ⁢     I   B       +     I   W               (   2   )                 H   x     =     a   ⁢       I   B       r   B                 (   3   )                 H   y     =     a   ⁢       I   W       r   W                 (   4   )             
 
   According to the method for optimizing write current, the write bit line current I B  and the write word line current I W  are determined so as to generate the magnetic field on the asteroid curve given by expression (1) and to minimize the write current I T  that is given by expression (2). Hence, the magnetization direction of the free layers can be securely determined, that is, the magnetization direction can be switched, if necessary, by a minimum write current I T . Furthermore, since the write current I T  is minimized, occurrence of noise attributable to a change in the write current I T  can be suppressed. 
   According to another aspect of the present invention, there is provided a method for optimizing write current in a magnetic memory comprising a plurality of bit lines, a plurality of word lines crossing the bit lines, and a plurality of memory cells disposed at intersections of the bit lines and the word lines, each of the memory cells having a free layer with reversible magnetization and a pinned layer with fixed magnetization, the method including a step for determining a distance r B  from the bit lines to the free layers, a distance r W  from the word lines to the free layers, a number n of the bit lines through which write bit line current I B  passes in a write operation, a parasitic resistance R B  of the bit line, and a parasitic resistance R W  of the word line, and a step for determining the write bit line current I B  and the write word line current I W  so as to minimize write power P d  by using expression (5) representing an asteroid curve expressed by a bit line magnetic field H x  generated by the bit line current I B , a word line magnetic field H y  generated by the word line current I W  and a predetermined constant H K , expression (6) representing write power P d  consumed by the word lines and the bit lines by using the write bit line current I B  and the write word line current I W , expression (7) representing the bit line magnetic field H x  generated by the bit line current I B  by using a predetermined coefficient a, and expression (8) representing the word line magnetic field H y  generated by the word line current I W  by using the coefficient a.
 
[Expression 4]
                 H   x     2   3       +     H   y     2   3         =     H   k     2   3               (   5   )                 P   d     =       n   ⁢           ⁢     I   B   2     ⁢     R   B       +       I   W   2     ⁢     R   W                 (   6   )                 H   x     =     a   ⁢       I   B       r   B                 (   7   )                 H   y     =     a   ⁢       I   W       r   W                 (   8   )             
 
   According to the method for optimizing write current, the write bit line current I B  and the write word line current I W  are determined so as to generate the magnetic field on the asteroid curve given by expression (5) and to minimize the write power P d  that is given by expression (6). Hence, the magnetization direction of the free layers can be securely determined or the magnetization direction can be switched if necessary, by a minimum write power P d . Furthermore, since the write power P d  is minimized, excessive heat generation caused by write power can be restrained. 
   Preferably, the constant H K  is given by expression (9) using a predetermined design margin m 1  when the minimum bit line magnetic field that makes it possible to reverse the magnetization of the free layers in any one of the memory cells associated with the bit line through which the write bit line current I B  passes when H y =0 or the minimum word line magnetic field that makes it possible to reverse the magnetization of the free layers in any one of the memory cells associated with the word line through which the write word line current I W  passes when H x =0 is denoted by H U .
 
 H   K   =H   U   +m   1   (9)
 
   In this case, the asteroid curve given by expression (1) or (5) will be positioned outside a maximum asteroid curve among the asteroid curves that vary from a memory cell to another. Hence, the write bit line current I B  and the write word line current I W  are determined on the maximum asteroid curve, thereby making it possible to securely switch the magnetization direction of the free layers to be switched in any one of selected memory cells. 
   Preferably, the bit line magnetic field H x  and the word line magnetic field H y  are given by expressions (10) and (11) using predetermined design margins m 2  and m 3 , respectively, when the maximum bit line magnetic field that makes it impossible to reverse the magnetization of the free layers in any one of the memory cells when H y =0 or the maximum word line magnetic field that makes it impossible to reverse the magnetization of the free layers in any one of the memory cells when H x =0 is denoted by H L , where m 2 =m 3  or m 2 ≠m 3 .
 
| H   x   |≦H   1x   =H   L   −m   2   (10)
 
| H   y   |≦H   2Y   =H   L   −m   3   (11)
 
   In this case, the bit line magnetic field H x  and the word line magnetic field H y  are restricted by expressions (10) and (11), making it possible to prevent “multi-selection.” 
   According to yet another aspect of the present invention, there is provided a magnetic memory having a plurality of bit lines, a plurality of word lines crossing the bit lines, a plurality of magnetic memory elements disposed corresponding to intersections of the bit lines and the word lines, a reference potential generating means for generating a predetermined reference potential, a write bit line current controlling means for controlling write bit line current passing through the bit lines in a write operation on the basis of a reference potential generated by the reference potential generating means, and a write word line current controlling means for controlling write word line current passing through the word lines in the write operation on the basis of a reference potential generated by the reference potential generating means. 
   In this magnetic memory, a common reference potential is supplied to the write bit line current controlling means and the write word line current controlling means. The write bit line current controlling means controls a write bit line current on the basis of the reference potential, while the write word line current controlling means controls a write word line current on the basis of the same reference potential. Therefore, the write bit line current and the write word line current change in synchronization, so that their ratio can be always maintained to be constant. 
   Preferably, the write bit line current controlling means includes a first transistor having a gate for receiving a reference potential, and passing a write bit line current. The write word line current controlling means includes a second transistor having a gate for receiving a reference potential, and passing a write word line current. 
   Further preferably, the ratio of the channel width/channel length of the first transistor to the channel width/channel length of the second transistor is set to be substantially equal to the ratio of the write bit line current to the write word line current. 
   In this case, optimum write bit line current and write word line current can be set by appropriately setting the channel widths and channel lengths of the transistors. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows the characteristics of magnetic fields that can switch the magnetization of the free layer of an MTJ device used in MRAMs and the setting of the magnetic fields for designing the MRAM to explain the methods for optimizing the write current in the MRAM according to an embodiment of the present invention; 
       FIG. 2  is a functional block diagram showing a structure of the MRAM according to an embodiment of the present invention; 
       FIG. 3  is a sectional view showing an example of a construction of a memory cell of the MRAM (one transistor and one MTJ cell design); 
       FIG. 4  illustrates the relationship of the easy magnetization axis and the hard magnetization axis to the free layer, and the switching of magnetization direction, of the free layer of the MTJ device shown in  FIG. 3 ; 
       FIG. 5  illustrates the characteristics of the magnetic fields that can switch the magnetization direction of the free layer of the MTJ device shown in  FIG. 3 ; 
       FIG. 6  is a functional block diagram showing the configuration of a twin-cell type MRAM; and 
       FIG. 7  is a functional block diagram showing a configuration of an MRAM using one transistor and one MTJ device type cells. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   An embodiment according to the present invention will now be explained in detail with reference to the accompanying drawings. In the drawings, like or corresponding components are assigned like reference numerals to avoid repeating the same description. 
   1. Preparation First, the description will be given of a precondition for optimizing a bit line write current and a word line write current according to the embodiment. 
     FIG. 1  shows asteroid curves in the embodiment according to the present invention. Referring to  FIG. 1 , the axis of abscissa indicates the bit line magnetic field H x  generated by a write bit line current, while the axis of ordinate indicates a word line magnetic field H y  generated by a write word line current. 
   Although the asteroid curve will vary, depending upon the locations of memory cells in an MRAM and variations in manufacturing conditions, it will generally remain within the hatched region shown in  FIG. 1. A  maximum asteroid curve AC max  constituting the outer edge of the hatched region is given by expression (12) shown below, while a minimum asteroid curve AC min  constituting the inner edge of the hatched region is given by expression (13) shown below.
 
[Expression 5]
                     ⁢         H   x     2   3       +     H   y     2   3         =     H   U     2   3                 (   12   )                   H   x     2   3       +     H   y     2   3         =     H   L     2   3               (   13   )             
 
   H U  in expression (12) denotes the minimum bit line magnetic field that makes it possible to reverse the magnetization of a free layer  120  (refer to  FIG. 3 ) in any one of memory cells associated with selected bit lines BL in the MRAM when H y =0 or the minimum word line magnetic field that makes it possible to reverse the magnetization of the free layer  120  in any one of memory cells associated with a selected write word line WWL in the MRAM when H x =0. H L  in expression (13) denotes the maximum bit line magnetic field that makes it impossible to reverse the magnetization of the free layer  120  (see  FIG. 3 ) in any one of memory cells associated with selected bit lines BL in the MRAM when H y =0 or the maximum word line magnetic field that makes it impossible to reverse the magnetization of the free layer  120  in any one of memory cells associated with a selected write word line WWL in the MRAM when H x =0. 
   2. Setting design conditions An asteroid curve AC out  is defined with a predetermined design margin m 1  allowed between itself and a maximum asteroid curve AC max  outside the hatched region. In this embodiment, the outermost asteroid curve (hereinafter referred to as “the outer asteroid curve”) AC out  will be used. The outer asteroid curve AC out  is given by expression (14) shown below.
 
[Expression 6]
                     ⁢         H   x     2   3       +     H   y     2   3         =     H   k     2   3                 (   14   )             
 
   where H k  denotes a predetermined constant and is given by expression (15) shown below when the predetermined design margin m 1  is used:
 
 H   k   =H   U   +m   1   (15)
 
   It is necessary to restrict the bit line magnetic field H x  and the word line magnetic field H y  by expressions (16) and (17), respectively, shown below.
 
| H   x   |≦H   1x   (16)
 
| H   y   |≦H   2Y   (17)
 
   where H 1x  and H 2Y  are defined by expressions (18) and (19) shown below by using predetermined design margins m 2  and m 3 , respectively.
 
 H   1x   =H   L   −m   2   (18)
 
 H   2Y   =H   L   −m   3   (19)
 
   If a bit line magnetic field H x  that leads to H x &gt;H L  is generated, then the magnetization direction of the free layer  120  in some memory cells will be changed merely by the bit line magnetic field H x  regardless of the presence of the word line magnetic field H y . In this case, therefore, the data of memory cells that have not been selected by a write word line WWL will be also rewritten in addition to that of the memory cells selected by the write word line WWL. This is referred to as multi-selection. To prevent the multi-selection, the bit line magnetic field H x  and the word line magnetic field H y  are restricted as shown by expressions (16) and (17), respectively, taking the design margins m 2  and m 3  into account. 
   Referring back to  FIG. 1 , a point H 1  on the outer asteroid curve AC out  has its H x  component of H 1x  and its H Y  component of H 1Y . Similarly, a point H 2  has its H x  component of H 2x  and its H Y  component of H 2Y . Thus, a combination of an optimum write bit line current I B  and an optimum write word line current I W  are selected from among the combinations of the write bit line current I B  and the write word line current I W  for generating synthetic magnetic fields of the bit line magnetic field H x  and the word line magnetic field H y  lying on the curve between the point H 1  and the point H 2  on the outer asteroid curve AC out . 
   The bit line magnetic field H x  generated around a bit line BL when the write bit line current I B  is passed through the bit line BL is given by expression (20) shown below.
 
[Expression 7]
               H   x     =     a   ⁢       I   B       r   B                 (   20   )             
 
   where denotes a predefined coefficient, and r B  denotes the distance from the center of the cross-section of the bit line BL to the center of the cross-section of the free layer  120 . 
   Similarly, the word line magnetic field H Y  generated around a write word line WWL when the write word line current I W  is passed through the write word line WWL is given by expression (21) shown below.
 
[Expression 8]
               H   y     =     a   ⁢       I   W       r   W                 (   21   )             
 
   where r W  denotes the distance from the center of the cross-section of the write word line WWL to the center of the cross-section of the free layer  120 . 
   To optimize the write bit line current I B  and the write word line current I W , expressions (14), (16), (17), (20) and (21) are used to minimize the write current obtained by adding the write word line current I W  passing through a single selected write word line WWL and the write bit line currents I B  passing through a plurality of bit lines BL crossing the selected write word line WWL, or to minimize the power consumed by the write word line current I W  and the write bit line currents I B . 
   The outer asteroid curve AC out  is symmetrical with respect to the H X  axis and the H Y  axis; therefore, the minimum write current is calculated using the first quadrant thereof. 
   A constant k r  is defined by expression (22) shown below:
 
 k   r   ≡r   W   /r   B   (22)
 
   where k r , r W , r B ≧0 
   Expression (23) is derived from expression (14) and expressions (20) through (22).
 
[Expression 9]
                 I   B     2   3       +       (       I   W       k   r       )       2   3         =           (       r   B     a     )       2   3       ⁢     H   k     2   3         =       I   B0     2   3       =       (       I   W0       k   r       )       2   3                   (   23   )             
 
   I B0  denotes the write bit line current when I W =0 and is defined by expression (24) shown below:
 
 I   B0 =( r   B   /a ) H   k   (24)
 
   I W0  denotes the write word line current when I B =0 and is defined by expression (25) shown below:
 
 I   W0 =( r   W   /a ) H   k   (25)
 
   Therefore, expression (26) shown below applies to the relationship between I B0  and I W0 :
 
 I   WO   =k   r   I   B0   (26)
 
   Meanwhile, from expressions (16) and (17), the bit line magnetic field H x  and the word line magnetic field H y  are subjected to the restrictions given by expressions (27) and (28) shown below:
 
 H   2x   ≦H   x   ≦H   1x   (27)
 
 H   1y   ≦H   y   ≦H   2y   (2 8)
 
   If the write bit line current at H 1  in  FIG. 1  is denoted as I B1  and the write word line current at H 1  is denoted as I W1 , while the write word line current at H 2  in  FIG. 1  is denoted as I W2  and the write bit line current at H 2  is denoted as I B2 , then the currents I B1 , I W1 , I W2  and I B2  will be defined by expressions (29) through (32), respectively, as shown below:
 
[Expression 10]
               I   B1     ≡         r   B     a     ⁢     H     1   ⁢   x                 (   29   )                   I   W1     ≡         k   r     ⁡     (       I   B0     2   3       -     I   B1     2   3         )         2   3         =           r   W     a     ⁢       (       H   k     2   3       -     H     1   ⁢   x       2   3         )       2   3         =         r   W     a     ⁢     H     1   ⁢   y                   (   30   )                 I   W2     ≡         r   W     a     ⁢     H     2   ⁢   y                 (   31   )                   I   B2     ≡       {       I   B0     2   3       -       (       I   W2       k   r       )       2   3         }       2   3         =           r   B     a     ⁢       (       H   k     2   3       -     H     2   ⁢   y       2   3         )       2   3         =         r   B     a     ⁢     H     2   ⁢   x                   (   32   )             
 
   As is obvious from  FIG. 1 , relations expressed as 0&lt;I B2 &lt;I B1 &lt;I B0  and 0&lt;I W1 &lt;I W2 &lt;I W0  hold. 
   From expressions (27) through (32), the write bit line current I B  and the write word line current I W  are required to satisfy expressions (33) and (34) shown below:
 
 I   B2   ≦I   B   ≦I   B1   (33)
 
 I   W1   ≦I   W   ≦I   W2   (34)
 
   3. Method for Optimization by Minimizing Write Current 
   The description will now be given of a method for optimizing the write bit line current I B  and the write word line current I W  by minimizing the write current obtained by adding the write bit line currents I B  and the write word line current I W  under the precondition described above. 
   The write current I T  passing in the write operation is given by expression (35) shown below:
 
 I   T   =nI   B   +I   W   (35)
 
   Accordingly, a combination of the write bit line current I B  and the write word line current I W  that minimizes the write current I T  is selected from among the combinations of the write bit line current I B  and the write word line current I W  that satisfy both expressions (23) and (35). The selected combination indicates optimum write bit line current I B  and the write word line current I W . Expression (36) shown below is derived from expressions (23) and (35):
 
[Expression 11]
               I   T     =         n   ⁢           ⁢     I   B       +         k   r     ⁡     (       I   B0     2   3       -     I   B     2   3         )         2   3         =         n     k   r       ⁢       (       I   W0     2   3       -     I   W     2   3         )       3   2         +     I   W                 (   36   )             
 
   Based on expression (36), d 2 I T /dI 2   B &gt;0 in a region defined by 0&lt;I B &lt;I B0 ; therefore, the write current I T  is a convex function of the bit line current I B  in the above region. Accordingly, the write current I T  takes a local minimum value when dI T /dI B =0. Hereinafter, the write bit line current I B  that gives the local minimum value of I T  will be denoted by I BTmin . 
   3.1. Case Where I B2 &lt;I BTmin &lt;I B1    
   If I B2 &lt;I BTmin &lt;I B1 , then I BTmin  is given by expression (37) shown below.
 
[Expression 12]
               I     BT   ⁢           ⁢   min       =           k   r   3         (       n   2     +     k   r   2       )       3   2         ⁢     I   B0       =           r   W   3         (         n   2     ⁢     r   B   2       +     r   W   2       )       3   2         ⁢     I   B0       =           r   B     ⁢     r   W   3         a   ⁢           ⁢       (         n   2     ⁢     r   B   2       +     r   W   2       )       3   2           ⁢     H   k                   (   37   )             
 
   From expression (23), the write word line current I WTmin  that gives the local minimum value in this case is given by expression (38) shown below.
 
[Expression 13]
                     I     WT   ⁢           ⁢   min       =             n   3     ⁢     k   r           (       n   2     +     k   r   2       )       3   2         ⁢     I   B0       =           n   3     ⁢     r   B   2     ⁢     r   W           (         n   2     ⁢     r   B   2       +     r   W   2       )       3   2         ⁢     I   B0                     =           n   3         (       n   2     +     k   r   2       )       3   2         ⁢     I   W0       =           n   3     ⁢     r   B   3           (         n   2     ⁢     r   B   2       +     r   W   2       )       3   2         ⁢     I   W0                     =             n   3     ⁢     r   B   3       +     r   W         a   ⁢           ⁢       (         n   2     ⁢     r   B   2       +     r   W   2       )       3   2           ⁢     H   k                     (   38   )             
 
   Based on expressions (35), (37) and (38), the minimum write current I Tmin  in this case is given by expression (39) shown below.
 
[Expression 14]
                     I     T   ⁢           ⁢   min       =           n   ⁢           ⁢     k   r             n   2     +     k   r   2           ⁢     I   B0       =         n   ⁢           ⁢     r   W               n   2     ⁢     r   B   2       +     r   W   2           ⁢     I   B0                     =         n         n   2     +     k   r   2           ⁢     I   W0       =         n   ⁢           ⁢     r   B               n   2     ⁢     r   B   2       +     r   W   2           ⁢     I   W0                     =         n   ⁢           ⁢     r   B     ⁢     r   W         a   ⁢           n   2     ⁢     r   B   2       +     r   W   2             ⁢     H   k                     (   39   )             
 
   In this case, I BTmin  is determined as the optimum write bit line current, while I WTmin  is determined as the optimum write word line current. 
   3.2. Case Where I BTmin &gt;I B1    
   If I BTmin &gt;I B1 , then the write current I T  takes a minimum value in the region wherein the write bit line current I B  is larger than I B1 . Based on expression (33), the write bit line current I B  must be I B1  or less; therefore, the write bit line current I B  that minimizes the write current I T  is I B1 . Hence, the minimum write current I Tmin  in this case is given by expression (40) shown below. 
   [Expression 15]
 
 I   Tmin   =nI   B1   +I   W1 =1 /a ( nr   B   H   1x   +r   W   H   1y )  (40)
 
   In this case I B1  is determined as the optimum write bit line current, while I W1  is determined as the optimum write word line current. 
   3.3. Case Where I BTmin &lt;I B2    
   If I BTmin &lt;I B2 , then the write current I T  takes a minimum value in the region wherein the write bit line current I B  is smaller than I B2 . Based on expression (33), the write bit line current I B  must be I B2  or more. Therefore, the write bit line current I B  for minimizing the write current I T  in this case is I B2 . Hence, the minimum write current I Tmin  in this case is given by expression (41) shown below: 
   [Expression 16]
 
 I   Tmin   =nI   B2   +I   W2 =1 /a ( n r   B   H   2x   +r   W   H   2y )  (41)
 
   In this case, I B2  is determined as the optimum write bit line current, while I W2  is determined as the optimum write word line current. 
   Thus, according to this embodiment, if n, r B  and r W  are given, and H k , H 1x  and H 2y  are determined, then the optimum write bit line current I B  and optimum word line current I W  for minimizing the write current IT can be determined. 
   3.4. Example of Calculation 
   Table 1 shows an example in which the write bit line current and the write word line current are optimized for minimizing write current when n and k r (=r W /r B ) take different predetermined values. 
   
     
       
         
             
             
             
             
             
             
             
             
           
             
               TABLE 1 
             
             
                 
             
             
                 
                 
               I BTmin / 
               I WTmin / 
               I WTmin / 
               I Tmin / 
               I Tmin / 
               I Tmin / 
             
             
               n 
               k r   
               I B0   
               I B0   
               I W0   
               I B0   
               I W0   
               I W0   
             
             
                 
             
           
          
             
                 
             
          
         
         
             
             
             
             
             
             
             
             
          
             
               1 
               1.0 
               0.354 
               0.354 
               0.354 
               0.707 
               0.707 
               — 
             
             
               4 
               5.0 
               0.476 
               1.22 
               0.244 
               3.12 
               0.625 
               — 
             
             
               8 
               5.0 
               0.149 
               3.05 
               0.610 
               4.24 
               0.848 
               — 
             
          
         
         
             
             
             
             
             
             
             
             
             
          
             
               4 
               10.0 
               0.800 
               0.512 
               0.0512 
               3.71 
               0.371 
               0.385 
               (*1) 
             
          
         
         
             
             
             
             
             
             
             
             
          
             
               8 
               10.0 
               0.476 
               2.44 
               0.244 
               6.25 
               0.625 
               — 
             
             
               16 
               10.0 
               0.149 
               6.10 
               0.610 
               8.48 
               0.848 
               — 
             
          
         
         
             
             
             
             
             
             
             
             
             
          
             
               32 
               10.0 
               0.0265 
               8.70 
               0.870 
               9.54 
               0.954 
               1.05 
               (*2) 
             
             
               8 
               15.0 
               0.687 
               1.56 
               0.104 
               7.06 
               0.471 
               0.471 
               (*1) 
             
          
         
         
             
             
             
             
             
             
             
             
          
             
               16 
               15.0 
               0.320 
               5.82 
               0.388 
               10.9 
               0.730 
               — 
             
          
         
         
             
             
             
             
             
             
             
             
             
          
             
               32 
               15.0 
               0.0765 
               11.1 
               0.742 
               13.6 
               0.905 
               0.916 
               (*2) 
             
             
               8 
               20.0 
               0.800 
               1.02 
               0.0512 
               7.43 
               0.371 
               0.385 
               (*1) 
             
          
         
         
             
             
             
             
             
             
             
             
          
             
               16 
               20.0 
               0.476 
               4.88 
               0.244 
               12.5 
               0.625 
               — 
             
             
               32 
               20.0 
               0.149 
               12.2 
               0.610 
               17.0 
               0.848 
               — 
             
          
         
         
             
             
             
             
             
             
             
             
             
          
             
               64 
               20.0 
               0.0265 
               17.4 
               0.870 
               19.1 
               0.954 
               1.05 
               (*2) 
             
             
                 
             
          
         
       
     
   
   If r B  takes a fixed value, then I B0  also takes a fixed value. Thus, I BTmin , I WTmin  and I Tmin  can be calculated on the basis of comparison with I B0 . Similarly, if r W  takes a fixed value, the I W0  also takes a fixed value. Thus, I WTmin  and I Tmin  can be calculated on the basis of comparison with I W0 . 
   Referring to Table 1, I BTmin /I B0  is given by expression (37). I WTmin /I B0  and I WTmin /I W0  are given by expression (38). I Tmin /I B0  and I Tmin /I W0  are given by expression (39). I Tmin /I W0  in the rightmost column is given by expression (40) or (41). 
   In the rightmost column of Table 1, it is assumed that H 1x =H 2y =0.65×H k (I B1 =0.65×I B0 , I B2 =0.125×I B0 ). In the column, (*1) indicates the value of I Tmin /I W0  when I B =I B1 , because I BTmin &gt;I B1  for these rows. Furthermore, (*2) indicates the value of I Tmin /I W0  when I B =I B2 , because I BTmin &lt;I B2  for the rows. 
   4. Optimizing Method by Minimizing Write Power 
   As another alternative method, the write bit line current I B  and the write word line current I W  may be optimized by minimizing power consumption in write operations (hereinafter referred to as gwrite power h) in place of the above write current I T . 
   Write power P d  due to parasitic resistance of the write word line WWL L is given by expression (42) shown below: 
   [Expression 17]
 
 P   d   =nI   B   2   R   B   +I   W   2   R   W   (42)
 
   where R B  denotes a parasitic resistance of the bit line BL, and R W  denotes a parasitic resistance of the write word line WWL. 
   For the convenience of calculation, k R  is defined as k R =R W /R B , and R W  and P d  of expression (42) is normalized by R B . The normalized write power P is defined by expression (43) shown below:
 
[Expression 18]
               P   ≡       P   d       R   B         =       n   ⁢           ⁢     I   B   2       +       k   R     ⁢     I   W   2                 (   43   )             
 
   Deleting I W  from expression (43) by using expression (23) leads to expression (44) shown below;
 
[Expression 19]
                   P   =       ⁢       n   ⁢           ⁢     I   B   2       +       k   r   2     ⁢         k   R     ⁡     (       I   B0     2   3       -     I   B     2   3         )       3                     =       ⁢         (     n   -       k   r   2     ⁢     k   R         )     ⁢     I   B   2       +     3   ⁢     k   r   2     ⁢     k   R     ⁢     I   B0     2   3       ⁢     I   B     4   3         -     3   ⁢     k   r   2     ⁢     k   R     ⁢     I   B0     4   3       ⁢     I   B     2   3         +                     ⁢       k   r   2     ⁢     k   R     ⁢     I   B0   2                     (   44   )             
 
   The value of I B  that gives the local extreme values of P can be obtained by solving dP/dI B =0. The value of I B  is given by expression (45) when n−k r   2 k R   1 0:
 
[Expression 20]
               I   B     =         {       -       k   r     ⁡     (         k   r     ⁢     k   R       ±       n   ⁢           ⁢     k   R           )           n   -       k   r   2     ⁢     k   R           }       3   2       ⁢     I   B0               (   45   )             
 
   When n−k r   2 k R   1 0, P may be regarded as a cubic function of I B   2/3 .I B   2/3  is a monotone increasing function of I B  in the region of interest. In the vicinity of local extreme values, therefore, it may be said that the behavior of P as the function of I B  is similar to the behavior of P as the function of I B   2/3 . 
   In the vicinity of the values of I B  given by expression (45), P behaves as a cubic function of I B   2/3  as shown in expression (44). If n−k r   2 k R &lt;0, then k r k R −(nk R ) 1/2 &gt;0; therefore, the value I BPmin  that is the smaller value of I B  given by expression (45) is given by expression (46) shown below. This I BPmin  value is a candidate of the bit line current for minimizing the normalized write power P and eventually the write power P d .
 
[Expression 21]
                     I     BP   ⁢           ⁢   min       =         (         k   r     ⁢       k   R             n     +       k   r     ⁢       k   R             )       3   2       ⁢     I   B0                   =         (         r   W     ⁢       R   W               r   B     ⁢       n   ⁢           ⁢     R   B           +       r   W     ⁢       R   W             )       3   2       ⁢     I   B0                   =         (         r   W     ⁢       R   W               r   B     ⁢       n   ⁢           ⁢     R   B           +       r   W     ⁢       R   W             )       3   2       ⁢       r   B     a     ⁢     H   k                     (   46   )             
 
   If n−k r   2 k R &gt;0, then a value that is the larger value of I B  given by expression (45) provides a candidate of the write bit line current for minimizing the write power P d  and is also given by expression (46). 
   4.1. Case Where I B2 £I BPmin £I B1    
   Because d 2 P/dI B   2 &gt;0 in the region of 0&lt;I B &lt;I B0 , both P and P d  are convex functions in the region. Hence, if I B2 £I BPmin £I B1 , then P d  takes a minimum value at I BPmin  given by expression (46). The minimum power consumption P dmin  is given by expression (47) shown below by substituting (46) for I B  in expression (44).
 
[Expression 22]
                     P     d   ⁢           ⁢   min       =         R   B     ⁢     I   B0   2     ⁢       n   ⁢           ⁢     k   r   2     ⁢     k   R           (       n     +       k   r     ⁢       k   R           )     2         =         n   ⁢           ⁢     r   W   2     ⁢     R   B     ⁢     R   W           (         r   B     ⁢       n   ⁢           ⁢     R   B           +       r   W     ⁢       R   W           )     2       ⁢     I   B0   2                     =         R   W     ⁢     I   W0   2     ⁢     n       (       n     +       k   r     ⁢       k   R           )     2         =         n   ⁢           ⁢     r   B   2     ⁢     R   B     ⁢     R   W           (         r   B     ⁢       n   ⁢           ⁢     R   B           +       r   W     ⁢       R   W           )     2       ⁢     I   W0   2                     =         n   ⁢           ⁢     r   B   2     ⁢     r   W   2     ⁢     R   B     ⁢     R   W             a   2     ⁡     (         r   B     ⁢       n   ⁢           ⁢     R   B           +       r   W     ⁢       R   W           )       2       ⁢           ⁢     H   k   2                     (   47   )             
 
   The write word line current I WPmin  for the minimum power consumption P dmin  is given by expression (48) shown below from expressions (23) and (46):
 
[Expression 23]
                     I     WP   ⁢           ⁢   min       =             k   r     ⁡     (       n         n     +       k   r     ⁢       k   R             )         3   2       ⁢     I   B0       =         r   W       r   B       ⁢       (         r   B     ⁢       n   ⁢           ⁢     R   B                 r   B     ⁢       n   ⁢           ⁢     R   B           +       r   W     ⁢       R   W             )       3   2       ⁢     I   B0                     =           (       n         n     +       k   r     ⁢       k   R             )       3   2       ⁢     I   W0       =         (         r   B     ⁢       n   ⁢           ⁢     R   B                 r   B     ⁢       n   ⁢           ⁢     R   B           +       r   W     ⁢       R   W             )       3   2       ⁢     I   W0                     =         (         r   B     ⁢       n   ⁢           ⁢     R   B                 r   B     ⁢       n   ⁢           ⁢     R   B           +       r   W     ⁢       R   W             )       3   2       ⁢       r   W     a     ⁢     H   k                     (   48   )             
 
   If n−k r   2 k R =0, then P in expression (44) reduces to a quadratic function of I B   2/3 . This quadratic function is also a convex function, so that P d  takes a minimum value P dmin  at I BPmin  and I WPmin . P dmin , I BPmin  and I WPmin  are given by expressions (49) through (51), respectively, shown below: 
   In this case, I BPmin  is determined as the optimum write bit line current, while I WPmin  is determined as the optimum write word line current.
 
[Expression 24]
               P     d   ⁢           ⁢   min       =         n   4     ⁢     I   B0   2     ⁢     R   B       =       1   4     ⁢     I   W0   2     ⁢     R   W                 (   49   )                 I     BP   ⁢           ⁢   min       =       I   B0       2   ⁢     2                 (   50   )                 I     WP   ⁢           ⁢   min       =       I   W0       2   ⁢     2                 (   51   )             
 
   4.2. Case Where I BPmin &gt;I b1    
   Independently of the value of n−k r   2 k R , P d  is a convex function of I B  in the region defined by 0&lt;I B &lt;I B0 . If I BTmin &gt;I B1 , then the write power P d  takes a minimum local value P dmin  in the region wherein the write bit line current I B  is larger than I B1 . Based on expression (33), the write bit line current I B  must be I B1  or less; hence, the write bit line current I B  for minimizing the write power P d  in this case is I B1 . Thus, the minimum write power P dmin  in this case is given by expression (52) shown below: 
   [Expression 25]
 
 P   dmin   =nI   B1   2   R   B+   I   W1   2   R   W   (52)
 
   In this case, I B1  is determined as the optimum write bit line current, while I W1  is determined as the optimum write word line current. 
   4.3. Case Where I BPmin &lt;I B2    
   If I BPmin &lt;I B2 , then the write power P d  takes a local minimum value P dmin  in the region wherein the write bit line current I B  is smaller than I B2 . Based on expression (33), the write bit line current I B  must be I B2  or more. In this case, therefore, the write bit line current I B  for minimizing the write power P d  is I B2 . Hence, the minimum write power P dmin  in this case is given by expression (53) shown below: 
   [Expression 26]
 
 P   dmin   =nI   B2   2   R   B   +I   W2   2   R   W   (53)
 
   In this case, I B2  is determined as the optimum write bit line current, while I W2  is determined as the optimum write word line current. 
   4.4. Example of Calculation 
   Table 2 shows an example in which the write bit line current and the write word line current are optimized for minimizing write power when n, k R  and k r  respectively take different predetermined values. 
   
     
       
         
             
             
             
             
             
             
             
             
             
           
             
               TABLE 2 
             
             
                 
             
             
               n 
               k R   
               k r   
               I BPmin /I B0   
               I WPmin /I B0   
               I WPmin /I W0   
               P dmin /(I B0   2 R B ) 
               P dmin /(I W0   2 R W ) 
               P dmin /(I W0   2 R W ) 
             
             
                 
             
           
          
             
                 
             
          
         
         
             
             
             
             
             
             
             
             
             
          
             
               1 
               1 
               1 
               0.354 
               0.354 
               0.354 
               0.250 
               0.250 
               — 
             
             
               128 
               1 
               5 
               0.170 
               2.89 
               0.578 
               12.0 
               0.481 
               — 
             
          
         
         
             
             
             
             
             
             
             
             
             
             
          
             
               256 
               1 
               5 
               0.116 
               3.33 
               0.665 
               14.5 
               0.580 
               0.582 
               (*2) 
             
             
               8 
               1 
               10 
               0.688 
               1.04 
               0.104 
               4.86 
               0.0486 
               0.0494 
               (*1) 
             
          
         
         
             
             
             
             
             
             
             
             
             
          
             
               16 
               1 
               10 
               0.604 
               1.53 
               0.153 
               8.16 
               0.0816 
               — 
             
             
               64 
               1 
               10 
               0.414 
               2.96 
               0.296 
               19.8 
               0.198 
               — 
             
             
               256 
               1 
               10 
               0.239 
               4.83 
               0.483 
               37.9 
               0.379 
               — 
             
          
         
         
             
             
             
             
             
             
             
             
             
             
          
             
               32 
               2 
               15 
               0.701 
               1.45 
               0.0966 
               19.9 
               0.0443 
               0.0456 
               (*1) 
             
          
         
         
             
             
             
             
             
             
             
             
             
          
             
               64 
               2 
               15 
               0.619 
               2.15 
               0.143 
               33.7 
               0.0750 
               — 
             
             
               256 
               2 
               15 
               0.430 
               4.23 
               0.282 
               83.2 
               0.185 
               — 
             
             
               64 
               1 
               20 
               0.604 
               3.05 
               0.153 
               32.7 
               0.0816 
               — 
             
          
         
         
             
             
             
             
             
             
             
             
             
             
          
             
               128 
               4 
               20 
               0.688 
               2.07 
               0.104 
               77.8 
               0.0486 
               0.0494 
               (*1) 
             
          
         
         
             
             
             
             
             
             
             
             
             
          
             
               256 
               4 
               20 
               0.604 
               3.05 
               0.153 
               131 
               0.0816 
               — 
             
             
                 
             
          
         
       
     
   
   Referring to Table 2, I BPmin /I B0  is given by expression (46). I WPmin /I B0  and I WPmin /I W0  are given by expression (48). P dmin /(I B0   2 R B ) and P dmin /(I W0   2 R W ) are given by expression (47). P dmin /(I W0   2 R W ) in the rightmost column is given by expression (52) or (53). 
   In the rightmost column of Table 2, it is assumed that H 1x =H 2y =0.65×H k (I B1 =0.65×I B0 , I B2 =0.125×I B0 ), as in Table 1 above. In the column, (*1) indicates the value of P dmin /(I W0   2 R W ) when I B =I B1 , because I BTmin &gt;I B1  for these rows. Furthermore, (*2) indicates the value of P dmin /(I W0   2 R W ) when I B =I B2 , because I BTmin &lt;I B2  for the rows. 
   Thus, according to the embodiment, optimum write bit line current I BTmin  and write word line current I WTmin  can be determined on the basis of the asteroid curve. More specifically, to suppress the occurrence of noise or to minimize the load on a power circuit, optimum write bit line current I BTmin  and write word line current I WTmin  can be determined so as to minimize the write current I T . To restrain heat generation, optimum write bit line current I BPmin  and write word line current I WPmin  can be determined so as to minimize the write power P d . 
   5. Write Current Control Circuit 
     FIG. 2  is a functional block diagram showing the structure of an MRAM according to an embodiment of the present invention. Referring to  FIG. 2 , MRAM 1  includes a memory cell array  2 , a row decoder  3 , a column decoder  4  and a write current control circuit  5 . 
   A row decoder  3  receives a row address signal input from an outside source and selects a single write or read word line from a plurality of write or read word lines. A column decoder  4  receives a column address signal input from an outside source and selects one or more bit lines from a plurality of bit lines. The write current control circuit  4  controls the write word line current supplied to the word line selected by the row decoder  3  and also controls the write bit line current or currents supplied to the bit line or bit lines selected by the column decoder  4 . 
   The write current control circuit  4  includes a reference potential generating circuit  51 , a write bit line current control circuit  52  and a write word line current control circuit  53 . The reference potential generating circuit  51  includes a P-channel MOS transistor  54  and a constant-current source  55 . The P-channel MOS transistor  54  and the constant-current source  55  are connected in series between a power source potential (VDD) node  56  and a ground potential node  57 , the P-channel MOS transistor  54  being diode-connected. The reference potential generating circuit  51  generates a reference potential Vref and supplies the reference potential Vref to both the write bit line current control circuit  52  and the write word line current control circuit  53 . 
   The write bit line current control circuit  52  has a plurality of P-channel MOS transistors Tr 1  through Trn (n being a natural number). The sources of the P-channel MOS transistors Tr 1  through Trn are connected to the power source potential node  56 , and the drains thereof are connected to bit line current supply source lines BLCS 1  through BLCSn, respectively. The reference potential Vref is commonly supplied from the reference potential generating circuit  51  to the gates of the P-channel MOS transistors Tr 1  through Trn. 
   The write word line current control circuit  53  has a P-channel MOS transistor  531 . The source of the P-channel MOS transistor  531  is connected to the power source potential node  56 , and the drain thereof is connected to a write word line current supply source line WLCS. The reference potential Vref is supplied from the reference potential generating circuit  51  to the gate of the P-channel MOS transistor  531 . 
   Thus, the write bit line current control circuit  52  controls the write bit line currents according to the reference potential Vref, while the write word line current control circuit  53  controls the write word line current according to the same reference potential Vref. Thus, as the reference potential Vref increases, the write bit line current and the write word line current both decrease, whereas the write bit line current and the write word line current both increase as the reference potential Vref decreases. This means that the write bit line current and the write word line current change in the same direction and in a mutually interlocked manner. 
   Here, the channel width/channel length (W/L) of the P-channel MOS transistors Tr 1  through Trn in the write bit line current control circuit  52  and that of the P-channel MOS transistor  531  in the write word line current control circuit  53  are determined as described below. 
   The optimum write bit line current I B  and the optimum write word line current I W  that pass in the write operations are determined according to the write current optimizing method described before. Hence, the bit line write current control circuit  52  must supply the optimum write bit line current I B  to each bit line and also supply the optimum write word line current I W  to the selected word line. The same reference potential Vref is supplied to the write bit line current control circuit  52  and the write word line current control circuit  53 . Thus, the W/L values are set such that those of the P-channel MOS transistors Tr 1  through Trn are different from that of the P-channel MOS transistor  531 , thereby supplying optimum write bit line current I B  and the write word line current I W . 
   More specifically, the W/L ratio of the P-channel MOS transistors Tr 1  through Trn to the P-channel MOS transistor  531  is set to be substantially equal to the ratio of the optimum write bit line current I B  to the optimum write word line current I W . In Table 1, for example, if n=8 and k r =10.0, then I BTmin /I B0 =0.476 and I WTmin /I B0 =2.44. Hence, the W/L of the P-channel MOS transistors Tr 1  through Trn and the W/L of the P-channel MOS transistor  531  are set such that the aforesaid W/L ratio is 0.476/2.44. 
   As described above, the write current control circuit  5  according to the embodiment controls the write bit line current and the write word line current on the basis of the same reference potential Vref, permitting the ratio thereof to remain constant. 
   The reference potential Vref can be adjusted by adjusting the current value of the constant-current source  55 . This makes it possible to set the absolute values of the write bit line current and the write word line current at appropriate values. 
   While an embodiment of the present invention has been described, the aforesaid embodiment is merely an example for embodying the invention. It is to be understood, therefore, that the invention is not limited to the disclosed embodiment. On the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention.