Patent Publication Number: US-7902897-B2

Title: Variable delay circuit and delay correction method

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of priority from Japanese Patent Application No. 2007-211277 filed on Aug. 14, 2007, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This application relates to a variable delay circuit and a semiconductor integrated circuit. 
     2. Description of Related Art 
     Techniques related to variable delay circuits are disclosed in Japanese Laid-open Patent Publication No. 2006-92730, Japanese Laid-open Patent Publication No. H9-18305, and Japanese Laid-open Patent Publication No. 2003-46378. 
     SUMMARY 
     According to one aspect of an embodiment, a variable delay circuit having a plurality of delay elements is provided, which comprises a delay time correction circuit that individually corrects a delay time in each of the plurality of delay elements to compensate for a variation in transistor performance among the plurality of delay elements. 
     Additional advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become more apparent to those skilled in the art upon examination of the following or upon learning the various aspects of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a variable delay circuit; 
         FIG. 2  shows a variable delay circuit; 
         FIG. 3  shows a variable delay circuit; 
         FIG. 4  shows a first embodiment; 
         FIG. 5  shows a variable delay element in the first embodiment; 
         FIG. 6  shows a variable delay element according to the first embodiment; 
         FIG. 7  shows a variable delay element the first embodiment; 
         FIG. 8  shows a variable delay element the first embodiment; 
         FIG. 9  shows a variable delay element the first embodiment; 
         FIG. 10  shows a variable delay element the first embodiment; 
         FIG. 11  shows a variable delay element the first embodiment; 
         FIG. 12  shows a judgment circuit in the first embodiment; 
         FIG. 13  shows a delay correction operation in the first embodiment; 
         FIG. 14  shows operation timing of the delay correction operation in the first embodiment; 
         FIG. 15  shows a second embodiment; 
         FIG. 16  shows a judgment circuit in the second embodiment; 
         FIG. 17  shows a third embodiment; and 
         FIG. 18  shows a fourth embodiment. 
     
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
       FIG. 1  shows a variable delay circuit. A variable delay circuit VARDLYA includes delay elements BA 1  to BA 10  having a delay time τf, delay elements BB 1  to BB 9  having a delay time τs (τs&gt;τf), and switches SW 1  to SW 10 . The delay elements BA 1  to BA 9  are coupled in series with an input terminal IN of the variable delay circuit VARDLYA. The delay elements BB 1  to BB 9  and BA 10  are coupled in series to an output terminal OUT of the variable delay circuit VARDLYA. The switch SW 1  is coupled between the input terminal IN of the variable delay circuit VARDLYA and an input terminal of the delay element BB 1 . The switch SW 2  (SW 3  to SW 9 ) is coupled between an output terminal of the delay element BA 1  (BA 2  to BA 8 ) and an input terminal of the delay element BB 2  (BB 3  to BB 9 ). The switch SW 10  is coupled between an output terminal of the delay element BA 9  and an input terminal of the delay element BA 10 . The variable delay circuit VARDLYA controls the switches SW 1  to SW 10  so that one of the switches SW 1  to SW 10  is switched ON. 
     A minute difference in delay time (τs−τf) between the delay elements BA 1  to BA 10  and the delay elements BB 1  to BB 9 A is delay time resolution, in the variable delay circuit VARDLYA. For example, if the delay time τf of the delay elements BA 1  to BA 10  is 1.0 D (D is a unit time) and the delay time τs of the delay elements BB 1  to BB 9  is 1.1 D, the delay time of the variable delay circuit VARDLYA is adjusted within a range between 10.0 D to 10.9 D in increments of 0.1 D. 
       FIG. 2  shows another variable delay circuit. A variable delay circuit VARDLYB includes delay elements BC 1  to BC 9  and a selector SOUT. The delay elements BC 1  to BC 9  are coupled in series with an input terminal IN of the variable delay circuit VARDLYB. The delay elements BC 1  to BC 9  are voltage control delay elements, delay times of which vary depending on voltages supplied from a bias terminal BIAS of the variable delay circuit VARDLYB. If a signal supplied from a control terminal CTL[ 0 ] among control terminals CTL[ 9 : 0 ] of the variable delay circuit VARDLYB is 1, the selector SOUT selects one signal out of a plurality of signals supplied from the input terminal IN of the variable delay circuit VARDLYB and outputs the signal to an output terminal OUT of the variable delay circuit VARDLYB. If a signal supplied from the control terminal CTL[ 1 ] (CTL[ 2 ] to CTL[ 9 ]) among the control terminals CTL[ 9 : 0 ] is 1, the selector SOUT selects one signal out of a plurality of signals supplied from the delay elements BC 1  (BC 2  to BC 9 ) and outputs the signal to the output terminal OUT of the variable delay circuit VARDLYB. 
     The variable delay circuit VARDLYB in  FIG. 2 , roughly adjusts the delay time (a rough delay adjustment) by switching the signals supplied to the output terminal OUT by the selector SOUT based on the signal supplied from the control terminals CTL[ 9 : 0 ]. The variable delay circuit VARDLYB finely adjusts the delay time (a fine delay adjustment) by controlling the delay times of the delay elements BC 1  to BC 9  based on signals supplied from the bias terminal BIAS. Since the variable delay circuit VARDLYB adjusts the delay times of the delay elements BC 1  to BC 9  in a lump with the fine delay adjustment, delay time resolution of the variable delay circuit VARDLYB is rougher than the delay time resolution of the variable delay circuit VARDLYA in  FIG. 1 . 
     A delay time of a delay element intended by designers (an ideal delay time) may be set, in the variable delay circuit having a high resolution such as the variable delay circuit VARDLYA in  FIG. 1 . However, it may occur that the delay time of the delay element dose not coincide with the ideal delay time due to changes in operating environment (such as temperature and power supply voltage) of a semiconductor integrated circuit including the variable delay circuit or due to influences of manufacturing variations in transistor performance. For the above reasons, a function to correct the delay time of the delay element in the variable delay element is necessary. 
       FIG. 3  shows yet another variable delay circuit. The delay elements BA 1  to BA 10  and BB 1  to BB 9  in the variable delay circuit VARDLYA in  FIG. 1  are replaced with delay elements BA 1   a  to BA 10   a  and BB 1   a  to BB 9   a , respectively, in a variable delay circuit VARDLYC. Furthermore, the variable delay circuit VARDLYC includes delay time compensation circuits DLYCOMPA and DLYCOMPB. The delay elements BA 1   a  to BA 10   a  (BB 1   a  to BB 9   a ) are the voltage control delay elements, the delay times of which vary depending on voltages supplied from the delay time compensation circuit DLYCOMPA (DLYCOMPB). The delay time compensation circuit DLYCOMPA (DLYCOMPB) includes a delay circuit having the same voltage control delay element as the delay elements BA 1   a  to BA 10   a  (BB 1   a  to BB 9   a ). The delay time compensation circuit DLYCOMPA (DLYCOMPB) adjusts a bias voltage of the voltage control delay element of the delay circuit so that the delay times of the entire delay circuit coincides with a cycle of a reference clock signal. The delay time compensation circuit DLYCOMPA (DLYCOMPB) corrects the delay times of the delay elements BA 1   a  to BA 10   a  (BB 1   a  to BB 9   a ) by supplying the delay elements BA 1   a  to BA 10   a  (BB 1   a  to BB 9   a ) with the bias voltage of the voltage control delay element of the delay circuit. 
     The manufacturing variations in the transistor performance include manufacturing variations among chips and manufacturing variations in a chip. The manufacturing variations among chips are the variations in transistor performance among the semiconductor integrated circuits manufactured by using the same mask pattern. The manufacturing variations in the chip are the variations in transistor performance among transistors within a semiconductor integrated circuit made up of tens of millions of transistors. 
     The variable delay circuit having the high resolution adjusts the delay time of the high resolution by using a minute difference in delay time among the delay elements. The manufacturing variations in the chip for the transistor performance influence on the lengths of the delay times among the delay elements and this results in deterioration in delay time precision of the variable delay circuit. The variable delay circuit in  FIG. 3  uniformly adjusts the delay times of the plurality of delay elements within the variable delay circuit. Therefore, the variable delay circuit compensates for the manufacturing variations among chips, but does not compensate for the manufacturing variations in the chip. 
       FIG. 4  shows a first embodiment.  FIGS. 5 through 11  show the variable delay elements in  FIG. 4 .  FIG. 12  shows a judgment circuit in  FIG. 4 . A variable delay circuit VARDLY 1  provided on a very large scale integration (VLSI) according to the first embodiment includes selectors SB 0  to SBn, SE 0  to SEn, SH 0  to SHn and SINC, delay elements B 0  to Bn, E 0  to En and H 0  to Hn+1, a gate circuit NAND, a counter CNT, a judgment circuit JDG, a divider DIV, an increase/decrease value output circuit INCOUT, adders AB 0  to ABn, AE 0  to AEn and AH, registers RB 0  to RBn, RE 0  to REn and RH, and a control circuit CTR. 
     If any one of a selector control signals CM 0 [ 0 ] and CM 0 [ 2 ] among selector control signals CM 0 [ 2 : 0 ] supplied from the control circuit CTR is “1”, the selector SB 0  outputs a signal supplied from an input terminal of the variable delay circuit VARDLY 1 . If a selector control signal CM 0 [ 1 ] among the selector control signals CM 0 [ 2 : 0 ] is “1”, the selector SB 0  outputs an output signal of the delay element H 0 . If any one of selector control signals CM 1 [ 0 ] (CM 2 [ 0 ] to CMn[ 0 ]) and CM 1 [ 2 ] (CM 2 [ 2 ] to CMn[ 2 ]) among selector control signals CM 1 [ 2 : 0 ] (CM 2 [ 2 : 0 ] to CMn[ 2 : 0 ]) supplied from the control circuit CTR is “1”, the selector SB 1  (SB 2  to SBn) outputs an output signal of a delay element B 0  (B 1  to Bn−1). If a selector control signal CM 1 [ 1 ] (CM 2 [ 1 ] to CMn[ 1 ]) among the selector control signals CM 1 [ 2 : 0 ] (CM 2 [ 2 : 0 ] to CMn[ 2 : 0 ]) is “1”, the selector SB 1  (SB 2  to SBn) outputs an output signal of delay element H 1  (H 2  to Hn). The delay element B 0  (B 1  to Bn) outputs on receiving the output signal of the selector SB 0  (SB 1  to SBn). The delay element B 0  (B 1  to Bn) is a variable delay element, the delay time of which varies depending on values in the register RB 0  (RB 1  to RBn). 
     If any one of the selector control signals CM 0 [ 0 ] and CM 0 [ 1 ] among the selector control signals CM 0 [ 2 : 0 ] supplied from the control circuit CTR is “1”, the selector SE 0  outputs the signal supplied via a switch from an input terminal of the variable delay circuit VARDLY 1 . If the selector control signal CM 0 [ 2 ] among the selector control signals CM 0 [ 2 : 0 ] is “1”, the selector SE 0  outputs the output signal of the delay element H 0 . If any one of the selector control signals CM 1 [ 0 ] (CM 2 [ 0 ] to CMn[ 0 ]) and CM 1 [ 1 ] (CM 2 [ 1 ] to CMn[ 1 ]) among the selector control signals CM 1 [ 2 : 0 ] supplied from the control circuit CTR is “1”, the selector SE 1  (SE 2  to SEn) outputs an output signal of the delay element E 0  (E 1  to En−1). If the selector control signal CM 1 [ 2 ] (CM 2 [ 2 ] to CMn[ 2 ]) among the selector control signals CM 1 [ 2 : 0 ] is “1”, the selector SE 1  (SE 2  to SEn) outputs the output signal of the delay element H 1  (H 2  to Hn). The delay element E 0  (E 1  to En) outputs on receiving the output signal of the selector SE 0  (SE 1  to SEn). The delay element E 0  (E 1  to En) is the variable delay element, the delay time of which varies depending on values in the register RE 0  (RE 1  to REn). 
     If the selector control signal CM 0 [ 0 ] (CM 1 [ 0 ] to CMn[ 0 ]) among the selector control signals CM 0 [ 2 : 0 ] (CM 1 [ 2 : 0 ] to CMn[ 2 : 0 ]) supplied from the control circuit CTR is “1”, the selector SH 0  (SH 1  to SHn) outputs the output signal of the delay element H 0  (H 1  to Hn). If the selector control signal CM 0 [ 1 ] (CM 1 [ 1 ] to CMn[ 1 ]) among the selector control signals CM 0 [ 2 : 0 ] (CM 1 [ 2 : 0 ] to CMn[ 2 : 0 ]) is “1”, the selector SH 0  (SH 1  to SHn) outputs the output signal of the delay element B 0  (B 1  to Bn). If the selector control signal CM 0 [ 2 ] (CM 1 [ 2 ] to CMn[ 2 ] ) among the selector control signals CM 0 [ 2 : 0 ] (CM 1 [ 2 : 0 ] to CMn[ 2 : 0 ]) is “1”, the selector SH 0  (SH 1  to SHn) outputs the output signal of the delay element E 0  (E 1  to En). The delay element H 0  outputs on receiving an output signal of the gate circuit NAND. The delay element H 1  (H 2  to Hn+1) outputs on receiving the output signal of the selector SH 0  (SH 1  to SHn). The delay elements H 0  to Hn+1 are the variable delay elements, the delay times of which vary depending on values in register RH. If a ring oscillator control signal ROSCEN is “0”, the gate circuit NAND outputs an output signal “1”. If the ring oscillator control signal ROSCEN is “1”, the gate circuit NAND inverts an output signal of the delay element Hn+1 and outputs the output signal. 
     For example, any of variable delay elements DLY 1  to DLY 7  shown in  FIGS. 5 through 11  is used as the delay elements B 0  to Bn, E 0  to En and H 0  to Hn+1 of the variable delay circuit VARDLY 1 . The variable delay element DLY 1  shown in  FIG. 5A  includes PMOS transistors TP 10 , TP 11  and SP 10  to SP 1   p , NMOS transistors TN 10 , TN 11  and SN 10  to SN 1   p , and inverters INV 10  to INV 1   p . A source of the PMOS transistor TP 10  and a source of the PMOS transistor TP 11  are coupled with each other. A drain of the PMOS transistor TP 10  and a drain of the NMOS transistor TN 10  are coupled with each other. A drain of the PMOS transistor TP 11  and a drain of the NMOS transistor TN 11  are coupled with each other. A source of NMOS transistor TN 10  and a source of the NMOS transistor TN 11  are coupled with each other. A gate of the PMOS transistor TP 10  and a gate of the NMOS transistor TN 10  are coupled to an input terminal IN of the variable delay element DLY 1 . A gate of the PMOS transistor TP 11  and a gate of the NMOS transistor TN 11  are coupled to a connection node between the PMOS transistor TP 10  and the NMOS transistor TN 10 . A connection node between the PMOS transistor TP 11  and the NMOS transistor TN 11  is coupled to an output terminal OUT of the variable delay element DLY 1 . 
     Sources of the PMOS transistors SP 10  to SP 1   p  are coupled to a power supply line VDD. Drains of the PMOS transistors SP 10  to SP 1   p  are coupled to a connection node between the PMOS transistors TP 10  and TP 11 . Gates of the PMOS transistors SP 10  to SP 1   p  are coupled via inverters INV 10  to INV 1   p  to control terminals CTL[ 0 ] to CTL[p] of the variable delay element DLY 1 . Sources of the NMOS transistors SN 10  to SN 1   p  are coupled to a ground line VSS. Drains of the NMOS transistors SN 10  to SN 1   p  are coupled to a connection node between the NMOS transistors TN 10  and TN 11 . Gates of the NMOS transistors SN 10  to SN 1   p  are coupled to the control terminals CTL[ 0 ] to CTL[p] of the variable delay element DLY 1 . A delay time of the variable delay element DLY 1  in  FIG. 5  is adjusted by controlling the number of the PMOS transistors in their ON states among the PMOS transistors SP 10  to SP 1   p  and the number of the NMOS transistors in their ON states among the NMOS transistors SN 10  to SN 1   p.    
     The variable delay element DLY 1  makes use of a part where a delay time-current value characteristic line varies lineally as shown in  FIG. 5B . If the number of PMOS transistors in their ON states among the PMOS transistors SP 10  to SP 1   p  and the number of NMOS transistors in their ON states among the NMOS transistors SN 10  to SN 1   p  is 1, a current value of the variable delay element DLY 1  becomes Imin. If the number of PMOS transistors in their ON states among the PMOS transistors SP 10  to SP 1   p  and the number of NMOS transistors in their ON states among the NMOS transistors SN 10  to SN 1   p  is (p+1), the current value of the variable delay element DLY 1  becomes Imax. 
     A variable delay element DLY 2  shown in  FIG. 6  includes PMOS transistors TP 20 , TP 21  and SP 20  to SP 24 , NMOS transistors TN 20 , TN 21  and SN 20  to SN 24 , and inverters INV 20  to INV 23 . A source of the PMOS transistor TP 20  and a source of the PMOS transistor TP 21  are coupled with each other. A drain of the PMOS transistor TP 20  and a drain of the NMOS transistor TN 20  are coupled with each other. A drain of the PMOS transistor TP 21  and a drain of the NMOS transistor TN 21  are coupled with each other. A source of the NMOS transistor TN 20  and a source of the NMOS transistor TN 21  are coupled with each other. A gate of the PMOS transistor TP 20  and a gate of the NMOS transistor TN 20  are coupled to an input terminal IN of the variable delay element DLY 2 . A gate of the PMOS transistor TP 21  and a gate of the NMOS transistor TN 21  are coupled to a connection node between the PMOS transistor TP 20  and the NMOS transistor TN 20 . A connection node between the PMOS transistor TP 21  and NMOS transistor TN 21  is coupled to an output terminal OUT of the variable delay element DLY 2 . 
     Sources of the PMOS transistors SP 20  to SP 24  are coupled to the power supply line VDD. Drains of the PMOS transistors SP 20  to SP 24  are coupled to a connection node between the PMOS transistors TP 20  to TP 21 . Gates of the PMOS transistors SP 20  to SP 23  are coupled to control terminals CTL[ 0 ] to CTL[ 3 ] of the variable delay element DLY 2  via the inverters INV 20  to INV 23 . A gate of the PMOS transistor SP 24  is coupled to the ground line VSS. A transistor size of the PMOS transistor SP 21  is twice as large as that of the PMOS transistor SP 20 . Transistor sizes of the PMOS transistors SP 22  and SP 24  are four times as large as that of the PMOS transistor SP 20 . A transistor size of the PMOS transistor SP 23  is eight times as large as that of the PMOS transistor SP 20 . 
     Sources of the NMOS transistors SN 20  to SN 24  are coupled to the ground line VSS. Drains of the NMOS transistors SN 20  to SN 24  are coupled to a connection node between NMOS transistors TN 20  and TN 21 . Gates of the NMOS transistor SN 20  to SN 23  are coupled to the control terminals CTL[ 0 ] to CTL[ 3 ] of the variable delay element DLY 2 . A gate of the NMOS transistor SN 24  is coupled to the power supply line VDD. A transistor size of the NMOS transistor SN 21  is twice as large as that of the NMOS transistor SN 20 . Transistor sizes of the NMOS transistors SN 22  and SN 24  are four times as large as that of the NMOS transistor SN 20 . A transistor size of the NMOS transistor SN 23  is eight times as large as that of the NMOS transistor SN 20 . A delay time of the variable delay element DLY 2  in  FIG. 6  is adjusted by controlling the number of the PMOS transistors in their ON states among the PMOS transistors SP 20  to SP 23  and the number of the NMOS transistors in their ON states among NMOS transistors SN 20  to SN 23 . 
     A variable delay element DLY 3  in  FIG. 7A  includes drive capability variable inverters DVINV 30  and DVINV 31 . An input terminal IA of the drive capability variable inverter DVINV 30  is coupled to an input terminal IN of the variable delay element DLY 3 . An output terminal OA of the drive capability variable inverter DVINV  30  is coupled to an input terminal IA of the drive capability variable inverter DVINV  31 . An output terminal OA of the drive capability variable inverter DVINV 31  is coupled to an output terminal OUT of the variable delay element DLY 3 . Control terminals CA[ 4 : 0 ] of the derive capability variable inverters DVINV 30  and DVINV 31  are coupled to control terminals CTL[ 4 : 0 ] of the variable delay element DLY 3 . 
     As shown in  FIG. 7B , the drive capability variable inverter DVINV 30  (DVINV 31 ) includes an inverter INV 30  and inverters having a control terminal SWINV 30  to SWINV 34 . Input terminals IB of the inverter INV 30  and the inverters having the control terminals SWINV 30  to SWINV 34  are coupled to an input terminal IA of the drive capability variable inverter DVINV 30  (DVINV 31 ). Output terminals OB of the inverter  30  and the inverters having the control terminals SWINV 30  to SWINV 34  are coupled to an output terminal OA of the drive capability variable inverter DVINV 30  (DVINV 31 ). Control terminals CB of the inverters having the control terminals SWINV 30  to SWINV 34  are coupled to control terminals CA[ 0 ] to CA[ 4 ] of the drive capability variable inverter DVINV 30  (DVINV 31 ). A drive capability (the transistor sizes of the transistors forming the inverter) of the inverter having the control terminal SWINV 31  is twice as large as that of the inverter having the control terminal SWINV 30 . A drive capability of the inverter having the control terminal SWINV 32  is four times as large as that of the inverter having the control terminal SWINV 30 . A drive capability of the inverter having the control terminal SWINV 33  is eight times as large as that of the inverter having the control terminal SWINV 30 . A drive capability of the inverter having the control terminal SWINV 34  is sixteen times as large as that of the inverter having the control terminal SWINV 30 . A drive capability of the inverter INV 30  is twice as large as that of the inverter having the control terminal SWINV 30 . 
     As shown in  FIG. 7C , the inverter having the control terminal SWINV 30  (SWINV 31  to SWINV 34 ) includes PMOS transistors TP 30  and SP 30 , NMOS transistors TN 30  and SN 30 , and inverter INV 31 . A source of the PMOS transistor TP 30  is coupled to the power supply line VDD. A drain of the PMOS transistor TP 30  and a source of the PMOS transistor SP 30  are coupled with each other. A drain of the PMOS transistor SP 30  and a drain of the NMOS transistor SN 30  are coupled with each other. A source of the NMOS transistor SN 30  and a drain of the NMOS transistor TN 30  are coupled with each other. A source of the NMOS transistor TN 30  is coupled to the ground line VSS. A gate of the PMOS transistor TP 30  and a gate of the NMOS transistor TN 30  are coupled to an input terminal IB of the inverter having the control terminal SWINV 30  (SWINV 31  to SWINV 34 ). A gate of the PMOS transistor SP 30  is coupled via the inverter INV 31  to the control terminal CB of the inverter having the control terminal SWINV 30  (SWINV 31  to SWINV 34 ). A gate of the NMOS transistor TN 30  is coupled to the control terminal CB of the inverter having the control terminal SWINV 30  (SWINV 31  to SWINV 34 ). A connection node between the PMOS transistor SP 30  and the NMOS transistor SN 30  is coupled to the output terminal OB of the inverter having the control terminal SWINV 30  (SWINV 31  to SWINV 34 ). A delay time of the variable delay element DLY 3  in  FIG. 7A  is adjusted by controlling the number of the inverters having the control terminals in their ON states among the inverters having the control terminals SWINV 30  to SWINV 34  of the drive capability variable inverters DVINV 30  and DVINV 31 . 
     A variable delay element DLY 4  shown in  FIG. 8A  includes drive capability variable inverters DVINV 40  and DVINV 41 . An input terminal IA of the drive capability variable inverter DVINV  40  is coupled to an input terminal IN of the variable delay element DLY 4 . An output terminal OA of the drive capability variable inverter DVINV 40  is coupled to an input terminal IA of the drive capability variable inverter DVINV 41 . An output terminal OA of the drive capability variable inverter DVINV 41  is coupled to an output terminal OUT of the variable delay element DLY 3 . Control terminals CA[ 4 : 0 ] of the drive capability variable inverter DVINV 40  and DVINV 41  are coupled to the control terminals CTL[ 4 : 0 ] of the variable delay element DLY 4 . 
     As shown in  FIG. 8B , the drive capability variable inverter DVINV 40  (DVINV 41 ) includes an inverter INV 40  and an inverter having control terminals SWINV 40  to SWINV 44 . Input terminals IB of the inverter INV 40  and the inverters having the control terminals SWINV 40  to SWINV 44  are coupled to an input terminal IA of the drive capability variable inverter DVINV 40  (DVINV 41 ). Output terminals OB of the inverter  40  and the inverters having the control terminals SWINV 40  to SWINV 44  are coupled to an output terminal OA of the drive capability variable inverter DVINV 40  (DVINV 41 ). Control terminals CB of the inverters having the control terminals SWINV 40  to SWINV 44  are coupled to control terminals CA[ 0 ] to CA[ 4 ] of the drive capability variable inverter DVINV 40  (DVINV 44 ). A drive capability of the inverter having the control terminal SWINV 41  is twice as large as that of the inverter having the control terminal SWINV 40 . A drive capability of the inverter having the control terminal SWINV 42  is four times as large as that of the inverter having the control terminal SWINV 40 . A drive capability of the inverter having the control terminal SWINV 43  is eight times as large as that of the inverter having the control terminal SWINV 40 . A drive capability of the inverter having the control terminal SWINV 44  is sixteen times as large as that of the inverter having the control terminal SWINV 40 . A drive capability of the inverter INV 40  is twice as large as that of the inverter having the control terminal SWINV 40 . 
     As shown in  FIG. 8C , the inverter having the control terminal SWINV 40  (SWINV 41  to SWINV 44 ) includes a PMOS transistor TP 40 , an NMOS transistor TN 40 , a CMOS switch SPN 40 , and an inverter INV  41 . A drain of the PMOS transistor TP 40  is coupled to the power supply line VDD. A drain of the PMOS transistor TP 40  and a drain of the NMOS transistor TN 40  are coupled with each other. A gate of the PMOS transistor TP 40  and a gate of the NMOS transistor TN 40  are coupled to an input terminal IB of the inverter having the control terminal SWINV 40  (SWINV 41  to SWINV 44 ). The CMOS switch SPN 40  is coupled between a connection node of the PMOS transistor TP 40  and the NMOS transistor TN 40  and an output terminal OB of the inverter having the control terminal SWINV 40  (SWINV 41  to SWINV 44 ). A gate of a PMOS transistor of the CMOS switch SPN 40  is coupled via the inverter INV 41  to a control terminal CB of the inverter having the control terminal SWINV 40  (SWINV 41  to SWINV 44 ). A gate of an NMOS transistor of the CMOS switch SPN 40  is coupled to the control terminal CB of the inverter having the control terminal SWINV 40  (SWINV 41  to SWINV 44 ). Like the variable delay element DLY 3  shown in  FIG. 7A , a delay time of the variable delay element DLY 4  shown in  FIG. 8A  is adjusted by controlling the number of the inverters having the control terminals in their ON states among the inverters having the control terminals SWINV 40  to SWINV 44  of the drive capability variable inverters DVINV 40  and DVINV 41 . 
     A variable delay element DLY 5  shown in  FIG. 9A  includes inverters INV 50  and INV 51 , and capacitor circuits VARCAP 50  to VARCAP 54 . An input terminal I of the inverter INV 50  is coupled to an input terminal IN of the variable delay element DLY 5 . An output terminal O of the inverter INV 50  is coupled to an input terminal I of the inverter INV 51 . An output terminal O of the inverter INV 51  is coupled to an output terminal OUT of the variable delay element DLY 5 . Input terminals I of the capacitor circuits VARCAP 50  to VARCAP 54  are coupled to a connection node between the inverter INV 50  and the inverter INV 51 . The control terminals C of the capacitor circuits VARCAP  50  to VARCAP 54  are coupled to control terminals CTL[ 0 ] to CTL[ 4 ] of the variable delay element DLY 5 . A capacitance of the capacitor circuit VARCAP  51  is twice as large as that of the capacitor circuit VARCAP 50 . A capacitance of the capacitor circuit VARCAP  52  is four times as large as that of the capacitor circuit VARCAP 50 . A capacitance of the capacitor circuit VARCAP  53  is eight times as large as that of the capacitor circuit VARCAP 50 . A capacitance of the capacitor circuit VARCAP  54  is sixteen times as large as that of the capacitor circuit VARCAP 50 . 
     As shown in  FIG. 9B , the capacitor circuit VARCAP 50  (VARCAP 51  to VARCAP 54 ) includes a PMOS transistor TP 50 , an NMOS transistor TN 50 , a CMOS switch SPN 50 , and an inverter INV 52 . A source and a drain of the PMOS transistor TP 50  are coupled to the power supply line VDD. A source and a drain of the NMOS transistor TN 50  are coupled to the ground line VSS. A gate of the PMOS transistor TP 50  and a gate of the NMOS transistor TN 50  are coupled with each other. The CMOS switch SPN 50  is coupled between a connection node of the PMOS transistor TP 50  and the NMOS transistor TN 50  and the input terminal I of the capacitor circuit VARCAP 50  (VARCAP 51  to VARCAP 54 ). A gate of a PMOS transistor of the CMOS switch SPN 50  is coupled to the control terminal C of the capacitor circuit VARCAP 50  (VARCAP 51  to VARCAP 54 ). A gate of an NMOS transistor of the CMOS switch SPN 50  is coupled via the inverter INV 52  to the control terminal C of the capacitor VARCAP 50  (VARCAP 51  to VARCAP 54 ). A delay time of the variable delay element DLY 5  shown in  FIG. 9A  is adjusted by controlling the number of the capacitor circuits in their ON states (a load capacitance of the connection node between the inverters INV 50  and INV 51 ) among the capacitor circuits VARCAP 50  to VARCAP 54 . 
     A variable delay element DLY 6  shown in  FIG. 10  is a combination of the drive capability variable inverters DVINV 30  and DVINV 31  shown in  FIG. 7A  and the capacitor circuits VARCAP 50  to VARCAP 54  shown in  FIG. 9A . An input terminal IA of the drive capability variable inverter DVINV 30  is coupled to an input terminal IN of the variable delay element DLY 6 . An output terminal OA of the drive capability variable inverter DVINV 30  is coupled to an input terminal IA of the drive capability variable inverter DVINV 31 . An output terminal OA of the drive capability variable inverter DVINV 31  is coupled to an output terminal OUT of the variable delay element DLY 6 . Control terminals CA[ 4 : 0 ] of the drive capability variable inverters DVINV 30  and DVINV 31  are coupled to control terminals CTL[ 9 : 5 ] of the variable delay element DLY 6 . Input terminals I of the capacitor circuits VARCAP 50  to VARCAP 54  are coupled to a connection node between the drive capability variable inverter DVINV 30  and the drive capability variable inverter DVINV 31 . Control terminals C of the capacitor circuits VARCAP 50  to VARCAP 54  are coupled to control terminals CTL[ 0 ] to CTL[ 4 ] of the drive capability variable inverter DLY 6 . A delay time of the variable delay element DLY 6 , shown in  FIG. 10 , is adjusted by controlling the number of the inverters having control terminals in their ON states among the inverters having the control terminals SWINV 30  to SWINV 34  of the drive capability variable inverters DVINV 30  and DVINV 31  and by controlling the number of the capacitor circuits in their ON states among the capacitor circuits VARCAP 50  to VARCAP 54 . 
     A variable delay element DLY 7 , shown in  FIG. 11 , is a combination of the drive capability variable inverters DVINV 40  and DVINV 41 , shown in  FIG. 8A , and the capacitor circuits VARCAP 50  to VARCAP 54  shown in  FIG. 9A . An input terminal IA of the drive capability variable inverter DVINV 40  is coupled to an input terminal IN of the variable delay element DLY 7 . An output terminal OA of the drive capability variable inverter DVINV 40  is coupled to an input terminal IA of the drive capability variable inverter DVINV 41 . An output terminal OA of the drive capability variable inverter DVINV 41  is coupled to an output terminal OUT of the drive capability variable element DLY 7 . Control terminals CA[ 4 : 0 ] of the drive capability variable inverters DVINV 40  and DVINV 41  are coupled to control terminals CTL[ 9 : 5 ] of the variable delay element DLY 7 . Input terminals I of the capacitor circuit VARCAP 50  to VARCAP 54  are coupled to a connection node between the drive capability variable inverter DVINV 40  and the drive capability variable inverter DVINV 41 . Control terminals C of the capacitor circuits VARCAP 50  to VARCAP 54  are coupled to control terminals CTL[ 0 ] to CTL[ 4 ] of the drive capability variable inverter DLY 7 . A delay time of the variable delay element DLY 7 , shown in  FIG. 11 , is adjusted by controlling the number of the inverters having control terminals in their ON states among the inverters having the control terminals SWINV 40  to SWINV 44  of the drive capability variable inverters DVINV 40  and DVINV 41  and by controlling the number of the capacitor circuits in their ON states among the capacitor circuits VARCAP 50  to VARCAP 54 . 
     The counter CNT, shown in  FIG. 4 , receives the output signal of the delay element Hn+1, as a clock signal CLK. The counter CNT counts in synchronization with the clock signal CLK only when a counter control signal CNTEN supplied from the control circuit CTR shown in  FIG. 4  is set to “1”. The counter CNT initializes all the bits of the counted values to “0” after a predetermined period has elapsed after completion of the counting. The judgment circuit JDG shown in  FIG. 4  outputs a digital value Dinc based on the digital values Dtosc and Dh supplied from the control circuit CTR and on a digital value Dcnt supplied from the counter CNT, on completion of the counting by the counter CNT. The digital value Dtosc indicates a cycle of the clock signal CLK. The digital value Dh indicates delay time resolution of the delay elements B 0  to Bn, E 0  to En, and H 0  to Hn+1. The digital value Dcnt indicates the counted value by the counter CNT. The digital value Dinc indicates an increase/decrease value used to correct a delay time of a correction target delay element selected out of the delay elements B 0  to Bn, E 0  to En, and H 0  to Hn+1. An increase/decrease value INC generated by the judgment circuit JDG is represented by an equation (1), where a reference value Ntarg and a counted value N by the counter CNT are used. The reference value Ntarg is represented by an equation (2), where a cycle Tosc of the clock signal CLK and delay time resolution h of the delay elements B 0  to Bn, E 0  to En, and H 0  to Hn+1 are used. A time Ten in which the control circuit CTR sets the counter control signal CNTEN to “1” is represented by an equation (3), where the reference value Ntarg and the cycle Tosc of the clock signal CLK are used.
 
INC=( Ntarg−N )*{ Ntarg/ (2* N )}  Equation (1)
 
 Ntarg=Tosc/h   Equation (2)
 
Ten= Ntarg*Tosc   Equation (3)
 
As shown in  FIG. 12 , the judgment circuit JDG includes registers REG 0  to REG 4 , dividers DIV 0  to DIV 2 , a subtractor SUB 0 , and a multiplier MUL 0 . The register REG 0  latches the digital value Dtosc supplied from the control circuit CTR, shown in  FIG. 4 , at a predetermined cycle. The register  1  loads the digital signal Dh supplied from the control circuit CTR at the predetermined cycle. The divider DIV 0  divides a value in the register REG 0  by a value in the register REG 1 . The register REG 2  latches a result of the division by the divider DIV 0  at a predetermined cycle. The register REG 3  latches the digital value Dcnt supplied from the counter CNT, shown in  FIG. 4 , at a predetermined cycle. The subtractor SUB 0  subtracts a value in the register REG 3  from a value in the register REG 2 . The multiplier MUL 0  multiplies the value in the register REG 2  by a result of the subtraction by the subtractor SUB 0 . The divider DIV 1  divides a result of the multiplication of the multiplier MUL 0  by the value in the register REG 3 . The divider DIV 2  divides a result of the division of the divider DIV 1  by a digital value D 2 . The digital value D 2  could be, for example, “2”. The register REG 4  latches a result of the division by the divider DIV 2  based on completion of a counting operation by the counter CNT. A value of the register REG 4  is output as the digital value Dinc. Note that the register REG 4  initializes all the bits to “0” after a predetermined period has elapsed from when the register REG 4  latches a result of the division by the divider DIV 2 .
 
     The divider DIV in  FIG. 4  divides the digital value Dinc supplied from the judgment circuit JDG in  FIG. 4  by a digital value Dm. The digital value Dm indicates the number of the delay elements H 0  to Hn+1. If a selector control signal SELI[ 0 ] of the selector control signals SELI[ 1 : 0 ] supplied from the control circuit CTR in  FIG. 4  is “1”, the selector SINC outputs the digital value Dinc supplied from the judgment circuit JDG. If a selector control signal SELI[ 1 ] of the selector control signals SELI[ 1 : 0 ] is “1”, the selector SINC outputs a result of the division by the divider DIV. 
     If an output control signal OUTH (OUTB[ 0 ] to OUTB[n], OUTE[ 0 ] to OUTE[n]) supplied from the control circuit CTR in  FIG. 4  is “0”, the increase/decrease value output circuit INCOUT in  FIG. 4  outputs a digital value “0” to the adder AH (AB 0  to ABn and AE 0  to AEn). If the output control signal OUTH (OUTB[ 0 ] to OUTB[n], OUTE[ 0 ] to OUTE[n]) is “1”, the increase/decrease value output circuit INCOUT outputs the digital value supplied from the selector SINC in  FIG. 4  to the adder AH (AB 0  to Abn, AE 0  to AEn). The adder AH (AB 0  to Abn, AE 0  to AEn) adds the digital value supplied from the increase/decrease value output circuit INCOUT and a value in the register RH (RB 0  to RBn, RE 0  to REn). The register RH (RB 0  to RBn, RE 0  to REn) stores a result of the addition by the adder AH (AB 0  to ABn and AE 0  to AEn) at a predetermined cycle. The control circuit CTR controls each part of the variable delay circuit VARDLY 1  via the selector control signals CM 0 [ 2 : 0 ] to CMn[ 2 : 0 ], SELI[ 1 : 0 ], the ring oscillator control signal ROSCEN, the output control signals OUTH, OUTB[n: 0 ] and OUTE[n: 0 ], the counter control signal CNTEN, and the digital values Dtosc and Dh. 
       FIG. 13  shows a delay correction operation of the variable delay circuit VARDLY 1  in  FIG. 4 .  FIG. 14  shows operation timing in the delay correction operation by the variable delay circuit VARDLY 1  in  FIG. 4 . A reset operation starts when a reset signal changes from “0” to “1” and successively n start-up sequence successively starts when a reset signal changes from “1” to “0”, in the VLSI on which the variable delay circuit VARDLY 1  is provided. A normal operation starts after a predetermined period has elapsed from completion of the start-up sequence. A first delay correction operation is performed to compensate for the variations in transistor performance among the delay elements B 0  to Bn and among the delay elements E 0  to En during the start-up sequence of the VLSI, in the variable delay circuit VARDLY 1 . A second delay correction operation is performed to compensate for variation in transistor performance among the delay elements B 0  to Bn and E 0  to En due to changes in operating environment, during the normal operation of the VLSI. (The second delay correction operation may be performed at all time.) In the first delay correction operation of the variable delay circuit VARDLY 1 , delay correction operations are performed in such a sequence as the delay correction operation on the delay elements H 0  to Hn+1, the delay correction operation on the delay element B 0  to the delay correction operation on the delay element Bn, and the delay correction operation on the delay element E 0  to the delay correction operation on the delay element En. 
     The control circuit CTR in  FIG. 4  selects all the delay elements of H 0  to Hn+1 as the correction target delay element and sets the selector control signals CM 0 [ 0 ] to CMn[ 0 ] among the selector control signals CM 0 [ 2 : 0 ] to CMn[ 2 : 0 ] to “1”, in the delay correction operations of the delay elements H 0  to Hn+1. A ring oscillator including the gate circuit NAND and the delay elements H 0  to Hn+1 is formed based on the above setting. The control circuit CTR in  FIG. 4  outputs the digital value Dtosc indicating an oscillation cycle (the cycle of the clock signal CLK) of the ring oscillator including the gate circuit NAND and the delay elements H 0  to Hn+1. In addition, the control circuit CTR outputs the digital value Dh indicating the delay time resolution of the delay elements B 0  to Bn, E 0  to En, and H 0  to Hn+1. The control circuit CTR sets the selector control signal SELI[ 0 ] of the selector control signals SELI[ 1 : 0 ] to “1” and sets the output control signal OUTH among the output control signals OUTH, OUTB[n: 0 ], and OUTE[n: 0 ] to “1”. The control circuit CTR causes the ring oscillator, which includes the gate circuit NAND and the delay elements H 0  to Hn+1, to start an oscillating operation ( FIG. 14  ( 2 )) by setting the ring oscillator control signal ROSCEN to “1” ( FIG. 14  ( 1 )) and, in the above condition. Next, the control circuit CTR sets the counter control signal CNTEN to “1” in accordance with an oscillation stabilization period of the ring oscillator, which includes the gate circuit NAND and the delay elements H 0  to Hn+1, ( FIG. 14  ( 3 )) and causes the counter CNT in  FIG. 4  to start the counting operations ( FIG. 14  ( 4 )). The control circuit CTR sets the counter control signal CNTEN to “0” after a time Ten, which is calculated by use of the oscillation cycle of the ring oscillator including the gate circuit NAND and the delay elements H 0  to Hn+1 and of the delay time resolution of the delay circuits B 0  to Bn, E 0  to En, and H 0  to Hn+1, has elapsed ( FIG. 14  ( 5 )) and the control circuit CTR terminates the counting operation by the counter CNT ( FIG. 14  ( 6 )). Then the control circuit CTR sets the ring oscillator control signal ROSCEN to “0” ( FIG. 14  ( 7 )) and terminates the oscillating operation of the ring oscillator including the gate circuit NAND and the delay elements H 0  to Hn+1 ( FIG. 14  ( 8 )). The judgment circuit JDG in  FIG. 4  calculates the increase/decrease value INC based on the completion of the counting operation by the counter CNT ( FIG. 14  ( 9 )). By adding a result of division of the digital value Dinc, which indicates the increase/decrease value INC, and the digital value Dm, to the value in the register RH, the delay times of the delay elements H 0  to Hn+1 are corrected. The control circuit CTR repeats a series of such operations and terminates the series of operations at some point in which the increase/decrease value INC calculated by the judgment circuit JDG becomes “0” in a predetermined number of times. 
     The control circuit CTR in  FIG. 4  selects the delay element B 0  (B 1  to Bn) as the correction target delay element and sets the selector control signal CM 0 [ 1 ] (CM 1 [ 1 ] to CMn[ 1 ]) among the selector control signals CM 0 [ 2 : 0 ] (CM 1 [ 2 : 0 ] to CMn[ 2 : 0 ]) to “1”, in the delay correction operation of the delay element B 0  (B 1  to Bn). A ring oscillator that includes the gate circuit NAND and the delay elements H 0  to Hn+1 and B 0  (B 1  to Bn) is formed based on the above setting. The control circuit CTR outputs the digital value Dtosc which is an oscillation cycle (the cycle of the clock signal CLK) of the ring oscillator including the gate circuit NAND and the delay elements H 0  to Hn+1 and B 0  (B 1  to Bn). The control circuit CTR sets the selector control signal SELI[ 0 ] of the selector control signals SELI[ 1 : 0 ] to “0” and sets the output control signal OUTB[ 0 ] (OUTB[ 1 ] to OUTB[n]) among the output control signals OUTH, OUTB[n: 0 ], and OUTE[n: 0 ] to “1”. The control circuit CTR causes the ring oscillator, which includes the gate circuit NAND and the delay elements H 0  to Hn+1, and B 0  (B 1  to Bn), to start an oscillating operation by setting the ring oscillator control signal ROSCEN to “1”, in the above condition. Next, the control circuit CTR sets the counter control signal CNTEN to “1” in accordance with an oscillation stabilization period of the ring oscillator, which includes the gate circuit NAND and the delay elements H 0  to Hn+1 and B 0  (B 1  to Bn), and causes the counter CNT to start the counting operation. The control circuit CTR sets the counter control signal CNTEN to “0” after a time Ten, which is calculated by use of the oscillation cycle of the ring oscillator including the gate circuit NAND and the delay elements H 0  to Hn+1 and B 0  (B 1  to Bn) and the delay time resolution of the delay circuit B 0  to Bn, E 0  to En, and H 0  to Hn+1, has elapsed and the control circuit CTR terminates the counting operation by the counter CNT. Then the control circuit CTR sets the ring oscillator control signal ROSCEN to “0” and terminates the oscillating operation of the ring oscillator including the gate circuit NAND and the delay elements H 0  to Hn+1 and B 0  (B 1  to Bn). The judgment circuit JDG in  FIG. 4  calculates the increase/decrease value INC, based on the completion of the counting operation by the counter CNT. By adding the digital value Dinc, which indicates the increase/decrease value INC, to the value in the register RB 0  (RB 1  to RBn), the delay time of the delay element B 0  (B 1  to Bn) is corrected. The control circuit CTR repeats a series of such operations and terminates the series of operations at some point in which the increase/decrease value INC calculated by the judgment circuit JDG becomes “0” in a predetermined number of times. 
     The control circuit CTR in  FIG. 4  selects the delay element E 0  (E 1  to En) as the correction target delay element and sets the selector control signal CM 0 [ 2 ] (CM 1 [ 2 ] to CMn[ 2 ]) among the selector control signals CM 0 [ 2 : 0 ] (CM 1 [ 2 : 0 ] to CMn[ 2 : 0 ]) to “1”, in the delay correction operation of the delay element E 0  (E 1  to En). A ring oscillator that includes the gate circuit NAND and the delay elements H 0  to Hn+1 and E 0  (E 1  to En) is formed, based on the above setting. The control circuit CTR outputs the digital value Dtosc which is an oscillation cycle (the cycle of the clock signal CLK) of the ring oscillator including the gate circuit NAND and the delay elements H 0  to Hn+1 and E 0  (E 1  to En). The control circuit CTR sets the selector control signal SELI[ 0 ] of the selector control signals SELI[ 1 : 0 ] to “0” and sets the output control signal OUTE[ 0 ] (OUTE[ 1 ] to OUTE[n]) among the output control signals OUTH, OUTB[n: 0 ], and OUTE[n: 0 ] to “1”. The control circuit CTR causes the ring oscillator, which includes the gate circuit NAND and the delay elements H 0  to Hn+1, and E 0  (E 1  to En), to start an oscillating operation by setting the ring oscillator control signal ROSCEN to “1”, in the above condition. Next, the control circuit CTR sets the counter control signal CNTEN to “1” in accordance with an oscillation stabilization period of the ring oscillator, which includes the gate circuit NAND and the delay elements H 0  to Hn+1 and E 0  (E 1  to En), and causes the counter CNT to start the counting operation. The control circuit CTR sets the counter control signal CNTEN to “0” after a time Ten, which is calculated by use of the oscillation cycle of the ring oscillator including the gate circuit NAND and the delay elements H 0  to Hn+1 and E 0  (E 1  to En) and the delay time resolution of the delay circuit B 0  to Bn, E 0  to En and H 0  to Hn+1, has elapsed and the control circuit CTR terminates the counting operation by the counter CNT. Then the control circuit CTR sets the ring oscillator control signal ROSCEN to “0” and terminates the oscillating operation of the ring oscillator including the gate circuit NAND and the delay elements H 0  to Hn+1 and E 0  (E 1  to En). The judgment circuit JDG in  FIG. 4  calculates the increase/decrease value INC, based on the completion of the counting operation by the counter CNT. By adding the digital value Dinc, which indicates the increase/decrease value INC, to the value in the register RE 0  (RE 1  to REn), the delay time of the delay element E 0  (E 1  to En) is corrected. The control circuit CTR repeats a series of such operations and terminates the series of operations at some point in which the increase/decrease value INC calculated by the judgment circuit JDG becomes “0” in a predetermined number of times. 
     The correction operations of the delay elements H 0  to Hn+1 and update operations of the register RB 0  to RBn and RE 0  to REn are repeatedly performed, in the second delay correction operation of the variable delay circuit VARDLY 1  in  FIG. 4 . The control circuit CTR in  FIG. 4  sets the output signal OUTB[ 0 ] to OUTB[n] and OUTE[ 0 ] to OUTE[n] to “1”, in the update operations of the register RB 0  to RBn and RE 0  to REn. The digital value added to the value in the register RH is added to the values in the register RB 0  to RBn and RE 0  to REn, with the above setting, during the delay correction operations of the delay elements H 0  to Hn+1. By the above addition, the delay times of the delay elements B 0  to Bn and E 0  to En are corrected. 
     In the first embodiment, the first delay correction operation performed in the start-up sequence of the VLSI, on which the variable delay circuit VARDLY 1  in  FIG. 4  is provided, compensates for the variations in transistor performance among the delay elements B 0  to Bn and among the delay elements E 0  to En. The second delay correction operation performed in the normal operation of the VLSI, on which the variable delay circuit VARDLY 1  is provided (the second delay correction operation may be performed all the time), compensates for the variation in transistor performance of the delay elements B 0  to Bn and E 0  to En due to the changes in the operating environment of the VLSI (such as the temperature and the power supply voltage). The first delay compensation operation and the second delay compensation operation greatly improve the delay time precision of the variable delay circuit VARDLY 1 . 
     The variable delay circuit according to the first embodiment compensates for the variations in transistor performance among the plurality of delay elements and for the variation in transistor performance among the plurality of delay elements due to the changes in the operating environment. For the above reason, the first embodiment may greatly improve the delay time precision of the variable delay circuit. 
       FIG. 15  shows a second embodiment.  FIG. 16  shows a judgment circuit in  FIG. 15 . The same numerical references are given to the same elements as those shown in the first embodiment and their description will be reduced or omitted. A control circuit CTRa and a judgment circuit JDGa in the variable delay circuit VARDLY 2  provided on a VLSI in the second embodiment correspond to the control circuit CTR and the judgment circuit JDG in the variable delay circuit VARDLY 1  in the first embodiment. 
     The control circuit CTRa is the same as the control circuit CTR in the first embodiment other than that a time to set a counter control signal CNTEN to “1” is “k” times lengthened (the “k” is equal to or greater than 10000) and that the control circuit CTRa outputs a digital signal Dk which indicates the constant k. Upon completion of a counting operation by a counter CNT, the judgment circuit JDGa outputs a digital value Dinc based on digital values Dtosc, Dh, and Dk supplied from the control circuit CTRa and a digital signal Dcnt supplied from the counter CNT. An increase/decrease value INC calculated by the judgment circuit JDGa is represented by an equation (4), where a reference value Ntarg′, a counted value N′ by the counter CNT, and the constant k are used. The reference value Ntarg′ is represented by an equation (5), where a cycle Tosc of a clock signal CLK, delay time resolution h of delay elements B 0  to Bn, E 0  to En and H 0  to Hn+1, and the constant k are used. A time Ten′ in which the control circuit CTRa sets the counter control signal CNTEN to “1” is represented by an equation (6), where the reference value Ntarg′ and the cycle Tosc of the clock signal CLK are used.
 
INC=( Ntarg′−N ′)*{ Ntarg ′/(2* k*N ′)}  equation (4)
 
 Ntarg′=k*Tosc/h   equation (5)
 
Ten′= Ntarg′*Tosc   equation (6)
 
     As shown in  FIG. 16 , the judgment circuit JDGa has a configuration in which a register REG 5 , a multiplier MUL 1 , and a divider DIV 3  are added to the judgment circuit JDG in the first embodiment. The register REG 5  latches the digital value Dk supplied from the control circuit CTRa in  FIG. 15  at a predetermined cycle. The multiplier MUL 1  multiplies a result of division by divider DIV 0  by a value in the register REG 5 . A register REG 2  does not latch the result of the division by the divider DIV 0  but latches the result of the multiplication by the multiplier MUL 1  at the predetermined cycle. The divider DIV 3  divides the result of the division by divider DIV 1  by the value in the register REG 5 . Divider DIV 2  does not divide the result of the division by the divider DIV 1  but divides the result of the division by the divider DIV 3  by a digital value D 2 . 
     In the second embodiment, an error in time in which the control circuit CTRa sets the counter control signal CNTEN to “1” in accordance with variation in power supply voltage of the VLSI including the variable delay circuit VARDLY 2  may be observed. As disclosed above, in view of degradation in delay time precision of the variable delay circuit VARDLY 2  due to the error in the counted value by the counter CNT, the time in which the control circuit CRTa sets the counter signal CNTEN to “1” is “K” times lengthened. The setting corrects the error in the counted value by the counter CNT to an average. The delay time precision of the variable delay circuit VARDLY 2  may be improved. 
       FIG. 17  shows a third embodiment. The same numerical references are given to the same elements as those shown in the first embodiment and their description will be reduced or omitted. A variable delay circuit VARDLY 3  provided on a VLSI in a third embodiment includes selectors SB 0   a  to SBna, SH 0   a  to SHna and SINC, delay elements B 0  to Bn and H 0  to Hn+1, a gate circuit NAND, a counter CNT, a judgment circuit JDG, a divider DIV, an increase/decrease value output circuit INCOUTa, adders AB 0  to ABn and AH, registers RB 0  to RBn and RH, and a control circuit CTRb. The variable delay circuit VARDLY 3  includes delay elements B 0  to Bn which are coupled in series and whose start point is an input terminal, and selectors which select any of the output signals from the delay elements B 0  to Bn and supplies the output signal to an output terminal. 
     If a selector control signal CM 0 [ 0 ] of selector control signals CM 0 [ 1 : 0 ] is “1”, the selector SB 0   a  outputs a signal supplied from the input terminal of the variable delay circuit VERDLY 3 . If a selector control signal CM 0 [ 1 ] of the selector control signals CM 0 [ 1 : 0 ] is “1”, the selector SB 0   a  outputs an output signal of the delay element H 0 . If a selector control signal CM 1 [ 0 ] (CM 2 [ 0 ] to CMn[ 0 ]) of selector control signals CM 1 [ 1 : 0 ] (CM 2 [ 1 : 0 ] to CMn[ 1 : 0 ]) is “1”, the selector SB 1   a  (SB 2   a  to SBna) outputs an output signal of the delay element B 0  (B 1  to Bn−1). If a selector control signal CM 1 [ 1 ] (CM 2 [ 1 ] to CMn[ 1 ]) of the selector control signals CM 1 [ 1 : 0 ] (CM 2 [ 1 : 0 ] to CMn[ 1 : 0 ]) is “1”, the selector SB 1   a  (SB 2   a  to SBna) outputs an output signal of the delay element H 1  (H 2  to Hn). 
     If the selector control signal CM 0 [ 0 ] (CM 1 [ 0 ] to CMn[ 0 ]) of the selector control signals CM 0 [ 1 : 0 ] (CM 1 [ 1 : 0 ] to CMn[ 1 : 0 ]) is “ 1 ”, the selector SH 0   a  (SH 1   a  to SHna) outputs the output signal of the delay element H 0  (H 1  to Hn). If the selector control signal CM 0 [ 1 ] (CM 1 [ 1 ] to CMn[ 1 ]) of the selector control signals CM 0 [ 1 : 0 ] (CM 1 [ 1 : 0 ] to CMn[ 1 : 0 ]) is “1”, the selector SH 0   a  (SH 1   a  to SHna) outputs the output signal of the delay element B 0  (B 1  to Bn). 
     The increase/decrease value output circuit INCOUTa does not include a circuit which outputs a digital value to the adders AE 0  to AEn of the increase/decrease value output circuit INCOUT in  FIG. 4 . The control circuit CTRb does not include a circuit performing delay correction operations of the delay elements E 0  to En that is a first delay correction operation and a circuit performing update operations of the register RE 0  to REn that is a second delay correction operation, both of which are included in the control circuit CTR in  FIG. 4 . The third embodiment having the configuration disclosed above has the same advantages as that of the first embodiment. 
       FIG. 18  shows a fourth embodiment. The same numerical references are given to the same elements as those shown in the first to the third embodiments and their descriptions will be reduced or omitted. A control circuit CTRc and a judgment circuit JDGa in a variable delay circuit VARDLY 4  provided on a VLSI in the fourth embodiment correspond to the control circuit CTRb and the judgment circuit JDG in the variable delay circuit VARDLY 3  shown in  FIG. 17 . The control circuit CTRc is a modification of the control circuit CTRb, just as the control circuit CTRa, in  FIG. 15 , is a modification of the control circuit CTR in  FIG. 4 . The fourth embodiment has the same advantages as those of the first and the second embodiments. 
     Example embodiments of the present invention have now been described in accordance with the above advantages. It will be appreciated that these examples are merely illustrative of the invention. Many variations and modifications will be apparent to those skilled in the art.