Patent Publication Number: US-6909593-B2

Title: Multi-layer capacitor, wiring board, and high-frequency circuit

Description:
This application is a Divisional Application of U.S. patent application Ser. No. 10/443,092 filed May 22, 2003, now U.S. Pat. No. 6,711,484, currently pending; which is a Continuation Application of U.S. patent application Ser. No. 10/073,085 filed Feb. 12, 2002, now U.S. Pat. No. 6,594,136; which is a Continuation Application of U.S. patent application Ser. No. 09/511,557 filed Feb. 23, 2000, now U.S. Pat. No. 6,370,010. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a multi-layer capacitor, a wiring board, and a high-frequency circuit, and, more particularly, to a multi-layer capacitor useful in a high-frequency circuit, and a wiring board and a high-frequency circuit, both of which include the multi-layer capacitor. 
   2. Description of the Related Art 
   The most common multi-layer capacitor conventionally available is constructed of a ceramic dielectric material, for example, and includes a plurality of dielectric layers laminated with an internal electrode interposed therebetween. To construct a plurality of capacitors, a plurality of pairs of first and second internal electrodes are alternately laminated with particular dielectric layers sandwiched therebetween in the direction of lamination. A capacitor body is thus constructed. 
   First and second external terminal electrodes are respectively disposed on first and second end surfaces of the capacitor body. The first internal electrode has a lead extending to the first end surface of the capacitor body, and the lead is electrically connected to the first external terminal electrode. The second internal electrode has a lead extending to the second end surface, and the lead is electrically connected to the second external terminal electrode. 
   In the multi-layer capacitor, a current flows from the second external terminal electrode to the first external terminal electrode. More specifically, the current flows from the second external terminal electrode to the second internal electrode, and flows to the first internal electrode via a dielectric layer from the second internal electrode, and finally reaches the first external terminal electrode via the first internal electrode. 
   The equivalent circuit of the capacitor is a serial connection of C, L, and R, where C represents the capacitance of the capacitor, L represents an equivalent series inductance (ESL), and R represents an equivalent series resistance (ESR) which mainly consists of the resistance of the electrodes. 
   The equivalent circuit of the capacitor has a resonance frequency of f 0 =1/{2π(LC) 1/2 }, and cannot function as a capacitor in a frequency range above the resonance frequency. In other words, the smaller the inductance L, namely, ESL, is, the higher the resonance frequency f 0  becomes, and the capacitor accordingly can work on a higher frequency. Although making the internal electrode of copper to reduce ESR has been contemplated, a capacitor having a small ESL is required if it is intended for use in a microwave range. 
   A low ESL is also required of a capacitor which is used as a decoupling capacitor connected to a power supply circuit which feeds power to a microprocessing unit (MPU) chip for use in a work station or a personal computer. 
     FIG. 19  is a block diagram showing an example of the configuration of the above-referenced MPU  31  and a power supply  32 . 
   Referring to  FIG. 19 , MPU  31  includes an MPU chip  33  and a memory  34 . The power supply  32  feeds power to the MPU chip  33 . A decoupling capacitor  35  is connected along the power line that extends from the power supply  32  to the MPU chip  33 . Signal lines extend between the MPU chip  33  and the memory  34 . 
   Like an ordinary decoupling capacitor, the decoupling capacitor  35 , associated with MPU  31 , is used to absorb noise and smooth fluctuations in power supply voltage. The MPU chip  33  has an operating frequency of 500 MHz or higher, and some chips reaching an operating frequency of 1 GHz are currently under development. In high-speed applications keeping pace with such an MPU chip  33 , a quick power supply function is required of the capacitor. The quick power supply function feeds power from electricity stored in a capacitor within several nanoseconds when power is instantaneously needed, such as at startup. 
   The MPU  31  thus needs a decoupling capacitor  35  having an inductance as low as possible, for example, 10 pH or lower inductance. Thus, a capacitor having a low inductance is needed for functioning as the decoupling capacitor. 
   For instance, an MPU chip  33  having an operating clock frequency of 450 MHz is now supplied with 1.8 volts to 2.0 volts DC, and its power consumption is 23 W, i.e., with a current of 12 A being drawn. To reduce the power consumption, the MPU  31  is set to operate in a sleep mode at a power consumption of 1 W when not in use. When the MPU  31  is changed from sleep mode to an active mode, the MPU chip  33  needs to be supplied with power enough for the active mode to start within several clocks. At the operating clock frequency of 450 MHz, power must be supplied within 4 to 7 nanoseconds when the MPU  31  is changed from the sleep mode to the active mode. 
   Since the power feeding from the power supply  32  is not fast enough, the charge stored in the decoupling capacitor  35  in the vicinity of the MPU chip  33  is first discharged to feed power to the MPU chip  33  until the power feeding from the power supply  32  starts. 
   At an operating clock frequency of 1 GHz, the ESL value of the decoupling capacitor  35  in the vicinity of the MPU chip  33  needs to be 10 pH or smaller for the decoupling capacitor  35  to function in the manner described above. 
   The ESL of typical multi-layer capacitors ranges from 500 pH to 800 pH, which is far from the above-referenced value 10 pH. Such an inductance component is created in the multi-layer capacitor because a magnetic flux, the direction of which is determined by a current flowing through the multi-layer capacitor, is created, and a self inductance is created due to the magnetic flux. 
   Under these situations, the structures of multi-layer capacitors that can achieve a low ESL have been proposed in U.S. Pat. No. 5,880,925, Japanese Unexamined Patent Publication No. 2-159008, Japanese Unexamined Patent Publication No. 11-144996, and Japanese Unexamined Patent Publication No. 7-201651. 
   The above disclosed method of achieving a low ESL is primarily based on the cancellation of magnetic fluxes induced in the multi-layer capacitor. To cancel magnetic fluxes, the direction of a current flowing in the multi-layer is diversified. To diversify the direction of the current, the number of terminal electrodes disposed on the external surface of the capacitor body is increased so that the number of leads of internal electrodes electrically connected to the respective external terminal electrodes is increased. At the same time, the leads of the internal electrodes are aligned in several different directions. 
   The effectiveness of the proposed method of achieving a low ESL in the multi-layer capacitor is not sufficient. 
   For example, U.S. Pat. No. 5,880,925 and Japanese Unexamined Patent Publication No. 2-159008 disclose a structure in which the leads of internal electrodes extend to opposing sides of a capacitor body. It is estimated that such a structure achieves a low ESL of about 100 pH. 
   Japanese Unexamined Patent Publication No. 11-144996 discloses a structure in which the leads of internal electrodes extend to four sides of a capacitor body, and describes that the best ESL value is 40 pH. 
   Japanese Unexamined Patent Publication No. 7-201651 discloses a structure in which the leads of the internal electrodes extend to the top and bottom major surfaces of a capacitor body, and describes that the best ESL value is 50 pH. 
   For this reason, a plurality of multi-layer capacitors connected in parallel must be conventionally mounted on a wiring board to achieve an ESL value as low as 10 pH in a high-frequency circuit having a multi-layer capacitor for an MPU chip (including a power supply line). As a result, the mounting area required for the plurality of multi-layer capacitors increases, which prevents achievement of a compact design of an electronic device included in a high-frequency circuit. 
   SUMMARY OF THE INVENTION 
   To overcome the problems described above, preferred embodiments of the present invention provide an improved multi-layer capacitor which achieves a very low ESL value and provide a wiring board and a high-frequency circuit, both of which incorporate the multi-layer capacitor which achieves very low ESL. 
   A multi-layer capacitor of a preferred embodiment of the present invention includes a capacitor body having two opposing major surfaces and four side surfaces joining the two opposing major surfaces. The capacitor body includes a plurality of dielectric layers extending parallel to the major surfaces and at least one pair of first and second internal electrodes which are opposed to each other with a particular dielectric layer interposed therebetween to define a capacitor unit. 
   The multi-layer capacitor of the present invention is constructed to overcome the problems with conventional devices. More specifically, a first side-surface terminal electrode and a second side-surface terminal electrode are provided on at least one of the side surfaces of the capacitor body, while at least one major-surface terminal electrode is provided on at least one of the major surfaces of the capacitor body. 
   The first side-surface terminal and the second side-surface terminal are respectively electrically connected to the first internal electrode and the second internal electrode, while one of the first internal electrode and the second internal electrode is electrically connected to the major-surface terminal electrode through a via hole conductor penetrating the dielectric layer. 
   The first side-surface terminal electrode and the second side-surface terminal electrode are preferably provided on each of two side surfaces, and are more preferably provided on each of the four side surfaces. 
   The first side-surface terminal electrode and the second side-surface terminal electrode are preferably arranged adjacent to each other on each of the side surfaces, and are more preferably arranged adjacent to each other along each of the four side surfaces. 
   The major-surface terminal electrode may be provided on one of the two major surfaces or may be provided on each of the two major surfaces. 
   The via hole conductor may include a portion which penetrates the internal electrode in a manner such that the via hole conductor remains electrically isolated from the internal electrode which is not connected thereto. This arrangement is implemented when a plurality of internal electrodes, i.e., the first and second internal electrodes, are included. 
   The major-surface terminal electrodes preferably include a first major-surface terminal electrode and a second major-surface terminal electrode, which are respectively electrically connected to the first internal electrode and the second internal electrode. In this case, the first major-surface terminal electrode and the second major-surface terminal electrode may be provided on only one of the two major surfaces or may be provided on each of the two major surfaces. In each of the major surfaces, the one arranged closest to the first major-surface terminal electrode is preferably the second major-surface terminal electrode and the one arranged closest to the second major-surface terminal electrode is preferably the first major-surface terminal electrode. 
   When the first and second major-surface terminal electrodes are arranged, the first major-surface terminal electrode may be provided on one major surface while the second major-surface terminal electrode may be provided on the other major surface. 
   Preferably, the via hole conductors include a first via hole conductor which electrically connects the first internal electrode to the first major-surface terminal electrode such that the first via hole remains electrically isolated from the second internal electrode, and a second via hole conductor which electrically connects the second internal electrode to the second major-surface terminal electrode such that the second via hole remains electrically isolated from the first internal electrode. 
   The side-surface terminal electrodes may include an electrode which straddles two adjacent side surfaces. 
   Preferably, the major surface of the capacitor body of preferred embodiments of the present invention is generally square. 
   The multi-layer capacitor of preferred embodiments of the present invention is useful as a decoupling capacitor connected to an electrical circuit of a microprocessing unit chip in a microprocessing unit. 
   In addition, a multi-layer capacitor according to preferred embodiments of the present invention may be included in and mounted on a wiring board. A microprocessing unit chip may be mounted on a wiring board of this preferred embodiment of the present invention. 
   Preferably, the major-surface terminal electrode on the multi-layer capacitor is connected to the wiring board using a bump connecting electrode. The side-surface terminal electrode of the multi-layer capacitor may be connected to the wiring board. 
   Further, another preferred embodiment of the present invention may be a high-frequency circuit incorporating the multi-layer capacitor of various preferred embodiments of the present invention. 
   Other features, elements, characteristics and advantages of the present invention will be described in detail below with reference to the attached drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a plan view diagrammatically showing a multi-layer capacitor of a first preferred embodiment of the present invention; 
       FIG. 2  is a perspective view showing the external appearance of the multi-layer capacitor of  FIG. 1 ; 
     FIG.  3 A and  FIG. 3B  are sectional views showing the internal construction of the multi-layer capacitor of  FIG. 1 , wherein  FIG. 3A  shows a cross section along which a first internal electrode extends, and  FIG. 3B  shows a cross section along which a second internal electrode extends; 
       FIG. 4  is a cross-sectional view of the multi-layer capacitor of  FIG. 1 , taken along lines IV—IV in  FIGS. 3A and 3B ; 
       FIG. 5  is a cross-sectional view of a multi-layer capacitor of a second preferred embodiment of the present invention, corresponding to  FIG. 4 ; 
       FIG. 6  is a cross-sectional view of a multi-layer capacitor of a third preferred embodiment of the present invention, corresponding to  FIG. 4 ; 
       FIG. 7  is a plan view diagrammatically showing a multi-layer capacitor, as a first comparative example in comparison with the multi-layer capacitor shown in  FIG. 1 ; 
       FIG. 8  is a plan view diagrammatically showing a multi-layer capacitor, as a second comparative example in comparison with the multi-layer capacitor shown in  FIG. 1 ; 
       FIG. 9  is a plan view diagrammatically showing a multi-layer capacitor of a fourth preferred embodiment of the present invention; 
       FIG. 10  is a plan view diagrammatically showing a multi-layer capacitor of a fifth preferred embodiment of the present invention; 
       FIG. 11  is a plan view diagrammatically showing a multi-layer capacitor of a sixth preferred embodiment of the present invention; 
       FIG. 12  is a plan view diagrammatically showing a multi-layer capacitor of a seventh preferred embodiment of the present invention; 
       FIG. 13  is a plan view diagrammatically showing a multi-layer capacitor of an eighth preferred embodiment of the present invention; 
       FIG. 14  is a plan view diagrammatically showing a multi-layer capacitor of a ninth preferred embodiment of the present invention; 
       FIG. 15  is a plan view diagrammatically showing a multi-layer capacitor of a tenth preferred embodiment of the present invention; 
       FIG. 16  is a plan view diagrammatically showing a multi-layer capacitor of an eleventh preferred embodiment of the present invention; 
       FIG. 17  is a cross-sectional view diagrammatically showing the construction of a microprocessing unit which includes a multi-layer capacitor of preferred embodiments of the present invention which defines a decoupling capacitor; 
       FIG. 18  is a cross-sectional view diagrammatically showing the construction of a microprocessing unit which includes a multi-layer capacitor of preferred embodiments of the present invention which defines a decoupling capacitor, wherein the microprocessing unit has a construction different from that of the microprocessing unit shown in  FIG. 17 ; and 
       FIG. 19  is a block diagram diagrammatically showing the configuration of a microprocessing unit and a power supply, relating to the present invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   FIG.  1  through  FIG. 4  show a multi-layer capacitor  1  according to a first preferred embodiment of the present invention.  FIG. 1  is a plan view diagrammatically showing the layout of terminal electrodes of the multi-layer capacitor  1 .  FIG. 2  is a perspective view showing the external appearance of the multi-layer capacitor  1 .  FIGS. 3A and 3B  are sectional views showing the internal construction of the multi-layer capacitor  1 , illustrating different cross sections thereof.  FIG. 4  is a cross-sectional view of the multi-layer capacitor  1 , taken along lines IV—IV in  FIGS. 3A and 3B . 
   The multi-layer capacitor  1  includes a capacitor body  8  having two opposing major surfaces  2  and  3  and four side surfaces  4 ,  5 ,  6  and  7  joining the major surfaces  2  and  3 . In this preferred embodiment, the major surfaces  2  and  3  are preferably substantially square. 
   The capacitor body  8  includes a plurality of dielectric layers  9 , for example, made of ceramic dielectric, extending parallel to the major surfaces  2  and  3  and a plurality of pairs of a first internal electrode  10  and a second internal electrode  11  which are opposed to each other with a particular dielectric layer  9  interposed therebetween to define a capacitor unit. In this preferred embodiment, the first and second internal electrodes  10  and  11  have shapes which are preferably substantially identical to each other but are arranged so as to be rotated by about 90 degrees relative to each other. As for the internal electrode pattern, a single type pattern only is preferably used, thereby simplifying the manufacturing of the capacitor. 
   In this specification, the “capacitor unit” refers to a minimum unit that creates capacitance with a pair of internal electrodes. 
   A plurality of first and second side-surface terminal electrodes  12  and  13  in the form of bands extend along the side surfaces  4  through  7  of the capacitor body  8  and further extend to partly cover the major surfaces  2  and  3 . 
   More specifically, a total of three side-surface terminal electrodes are preferably provided on each of the side surfaces  4  through  7 . The first side-surface terminal electrodes  12  and the second side-surface terminal electrodes  13  are alternately arranged with one first side-surface terminal electrode  12  being adjacent to one second side-surface terminal electrode  13 , along the four side surfaces  4  through  7 . 
   A plurality of first and second major-surface terminal electrodes  14  and  15  preferably in the form of substantially circular members are provided on one major surface  2  of the capacitor body  8 . 
   In this preferred embodiment, two first major-surface terminal electrodes  14  and two second major-surface terminal electrodes  15  are preferably provided on the major surface  2  such that the one arranged closest to the first major-surface terminal electrode  14  is the second major-surface terminal electrode  15  and such that the one arranged closest to the second major-surface terminal electrode  15  is the first major-surface terminal electrode  14 . 
     FIG. 3A  shows a cross section along which the first internal electrode  10  extends, while  FIG. 3B  shows a cross section along which the second internal electrode  11  extends. 
   Referring to FIG.  3 A and  FIG. 4 , the first internal electrode  10  extends to each of the four side surfaces  4  through  7 , and is electrically connected at its ends to the first side-surface terminal electrodes  12 . 
   Referring to FIG.  3 B and  FIG. 4 , the second internal electrode  11  extends to each of the four side surfaces  4  through  7 , and is electrically connected at its ends to the second side-surface terminal electrodes  13 . 
   First via hole conductors  16 , penetrating particular dielectric layers  9 , are arranged within the capacitor body  8  to electrically connect the first internal electrodes  10  to the first major-surface terminal electrodes  14 . Second via hole conductors  17 , penetrating particular dielectric layers  9 , are arranged within the capacitor body  8  to electrically connect the second internal electrodes  11  to the second major-surface terminal electrodes  15 . 
   To create a large capacitance in this preferred embodiment, a plurality of the first internal electrodes  10  and the second internal electrodes  11  are alternately arranged in the direction of the lamination of the dielectric layers  9  and a plurality of pairs of opposing portions of the respective electrodes face each other, thereby defining a plurality of capacitor units. The plurality of capacitor units are connected in parallel through the first and second via hole conductors  16  and  17 . 
   With this arrangement, the first via hole conductor  16  penetrates and extends through the second internal electrodes  11 , while electrically connecting the plurality of first internal electrodes  10 . The second via hole conductor  17  penetrates and extends through the first internal electrodes  10 , while electrically connecting the plurality of second internal electrodes  11 . 
   The second internal electrode  11  has, around the first via hole conductor  16 , a gap  18  by which the first via hole conductor  16  is electrically isolated from the second internal electrode  11 . The first internal electrode  10  has, around the second via hole conductor  17 , a gap  19  by which the second via hole conductor  17  is electrically isolated from the first internal electrode  10 . 
     FIG. 1  shows the layout of the terminal electrodes  12  through  15  of the multi-layer capacitor  1  thus constructed. Referring to  FIG. 1 , the side-surface terminal electrodes  12  and  13  are shown to have a substantially rectangular shape but may have other shapes. To differentiate between the first side-surface terminal electrode  12  and the second side-surface terminal electrode  13 , the first side-surface terminal electrode  12  is shown in black. The first major-surface terminal electrodes  14  and the second major-surface terminal electrodes  15  are shown to have a substantially circular shape but may have other shapes. To differentiate between the first major-surface terminal electrode  14  and the second major-surface terminal electrode  15 , the first major-surface terminal electrode  14  is shown in black. 
   Typical currents flowing in this preferred embodiment of the multi-layer capacitor are shown by arrows in FIG.  1 . 
   Referring to  FIG. 1 , currents flow in a variety of directions in the approximate center portion of the major surface  2  and in the vicinity of the side surfaces  4  through  7  in the capacitor body  8  in the multi-layer capacitor  1 . Magnetic fluxes created by these currents are efficiently canceled, and the generation of the magnetic fluxes is thus controlled. The length of current-carrying path is accordingly shortened. As a result, the ESL value of the multi-layer capacitor  1  is greatly reduced so as to have a very low value. 
   Since the major surfaces  2  and  3  of the capacitor body  8  of the multi-layer capacitor  1  are generally square, the first and second side-surface terminal electrodes  12  and  13 , and the major-surface terminal electrodes  14  and  15  are easily arranged in a balanced layout to increase the cancellation effect of magnetic flux, compared with a capacitor body having a rectangular shape. This further decreases the ESL value. 
     FIG. 5  shows a second preferred embodiment of the present invention, and corresponds to  FIG. 4 , which shows the first preferred embodiment. Referring to  FIG. 5 , elements identical to those described with reference to  FIG. 4  are designated with the same reference numerals, and the description of these common elements is not repeated here. 
   In a multi-layer capacitor  1   a  shown in  FIG. 5 , a first major-surface terminal electrode  14  is disposed on one major surface  2 , while a second major-surface terminal electrode  15  is disposed on the other major surface  3 . 
     FIG. 6  shows a third preferred embodiment of the present invention, and corresponds to  FIG. 4 , which shows the first preferred embodiment. Referring to  FIG. 6 , elements identical to those described with reference to  FIG. 4  are designated with the same reference numerals, and the description about the common elements is not repeated here. 
   In a multi-layer capacitor  1   b  shown in  FIG. 6 , a first major-surface terminal electrode  14  and second major-surface terminal electrode  15  are provided on each of the two major surfaces  2  and  3 . 
   The layout of the terminal electrodes  12  through  15  in the multi-layer capacitor  1   a  shown in FIG.  5  and the multi-layer capacitor  1   b  shown in  FIG. 6  may be also shown as the layout of the multi-layer capacitor  1  is shown in FIG.  1 . 
   In the multi-layer capacitor  1  shown in FIG.  1  through  FIG. 4 , the directions of the currents flowing through the first and second via hole conductors  16  and  17  are opposite in the cross section shown in FIG.  4 . In the multi-layer capacitor  1   a  shown in FIG.  5  and the multi-layer capacitor  1   b  shown in  FIG. 6 , the directions of the currents flowing through the first and second via hole conductors  16  and  17  are the same. From this, the multi-layer capacitor  1  shown in  FIG. 1  outperforms the multi-layer capacitors  1   a  and  1   b  in the reduction of the ESL value. 
   To verify the effectiveness of the multi-layer capacitor  1  shown in FIG.  1  through  FIG. 4  in the reduction of the ESL value, a multi-layer capacitor  20  as a comparative example 1 shown in  FIG. 7 and a  multi-layer capacitor  21  as a comparative example 2 shown in  FIG. 8  are prepared. FIG.  7  and  FIG. 8  respectively show the multi-layer capacitor  20  and the multi-layer capacitor  21  in the same manner as  FIG. 1  shows the multi-layer capacitor  1 . For ease of comparison, like components are designated with like reference numerals. 
   The multi-layer capacitor  1  shown in  FIG. 1  preferably includes a total of sixteen terminal electrodes  12  through  15 , including the six first side-surface terminal electrodes  12 , the six second side-surface terminal electrodes  13 , the two first major-surface terminal electrodes  14 , and the two second major-surface terminal electrodes  15 . In the multi-layer capacitors  20  and  21  respectively shown in FIG.  7  and  FIG. 8 , sixteen electrodes  12  through  15  are also provided. 
   More specifically, the multi-layer capacitor  20  shown in  FIG. 7  has a total of sixteen electrodes, namely, eight first side-surface terminal electrodes  12  and eight second side-surface terminal electrodes  13 . The multi-layer capacitor  21  shown in  FIG. 8  has a total of sixteen electrodes, namely, eight first major-surface terminal electrodes  14  and eight second major-surface terminal electrodes  15 . 
   The multi-layer capacitors  1 ,  20 , and  21  have capacitor bodies  8  which are identical in shape and dimensions. The dimensions of the major surfaces of each capacitor body  8  is preferably, for example, about 2.5 mm by about 2.5 mm. 
   These multi-layer capacitors commonly include a total number of sixteen electrodes and a capacitor body  8  having identical shape and dimensions. The frequency characteristics of the multi-layer capacitors  1 ,  20 , and  21  are measured using a network analyzer to determine ESL values from self-resonance frequencies. The multi-layer capacitor  1  shown in  FIG. 1  achieves an ESL of 12 pH, the multi-layer capacitor  20  shown in  FIG. 7  has an ESL of 16 pH, and the multi-layer capacitor  21  shown in  FIG. 8  has an ESL of 24 pH. 
   From these results, given the same total number of electrodes  12  through  15 , forming the first and second side-surface terminal electrodes  12  and  13  and the first and second major-surface terminal electrodes  14  and  15  presents a lower ESL value as compared to forming the first and second side-surface terminal electrodes  12  and  13  only or forming the first and second major-surface terminal electrodes  14  and  15  only. 
   With the terminal electrodes provided on the side surfaces and the major surfaces at the same time, an interaction efficiently works to control the generation of magnetic fluxes, thereby providing a very low ESL capacitor, which is not achievable with the arrangement of the electrodes on the side surfaces only or on the major surfaces only. 
   FIG.  9  through  FIG. 16  show other preferred embodiments of the present invention. These figures show the respective preferred embodiments in a manner similar to FIG.  1 . Referring to FIG.  9  through  FIG. 16 , elements identical to those described with reference to  FIG. 1  are designated with the same reference numerals, and the description of common elements is not repeated here. 
   In a multi-layer capacitor  22  shown in  FIG. 9 , two of the first side-surface terminal electrodes  12  and two of the second side-surface terminal electrodes  13  respectively straddle two adjacent side surfaces, i.e., adjacent side surfaces  4  and  5 ,  5  and  6 ,  6  and  7 , and  7  and  4 . 
   The multi-layer capacitor  22  shown in  FIG. 9  achieves an even lower ESL value than the multi-layer capacitor  1  shown in FIG.  1 . More specifically, an ESL of 8 pH results when the multi-layer capacitor  22  having the capacitor body  8  identical to that in the preceding preferred embodiments is tested. 
   If the first major-surface terminal electrodes  14  and the second major-surface terminal electrodes  15  are provided on each of the two major surfaces  2  and  3  as shown in  FIG. 6  in the multi-layer capacitor  22  shown in  FIG. 9 , the ESL value slightly rises, becoming an ESL of 12 pH. 
   A multi-layer capacitor  23  shown in  FIG. 10 , a multi-layer capacitor  24  shown in  FIG. 11 , a multi-layer capacitor  25  shown in  FIG. 12 , a multi-layer capacitor  26  shown in  FIG. 13 , and a multi-layer capacitor  27  shown in  FIG. 14  all include a capacitor body  8  having substantially rectangular major surfaces  2  and  3 . 
   The multi-layer capacitors  23  through  25  include two first side-surface terminal electrodes  12  and two second side-surface terminal electrodes  13 , disposed on only one side surface  4  which joins the longer sides of the major surfaces  2  and  3 . The multi-layer capacitors  26  and  27  include two first side-surface terminal electrodes  12  and two second side-surface terminal electrodes  13 , disposed on one side surface  4  which joins the longer sides of the major surfaces  2  and  3 , and also two first side-surface terminal electrodes  12  and two second side-surface terminal electrodes  13 , disposed on the other side surface  6  opposed to the side surface  4 . 
   The multi-layer capacitors  23  and  26  have each a single major-surface terminal electrode  15 , the multi-layer capacitors  24  and  27  have each a total of three first and second major-surface terminal electrodes  14  and  15 , and the multi-layer capacitor  25  has a total of six first and second major-surface terminal electrodes  14  and  15 . 
   The ESL values of the multi-layer capacitors  23  through  27  with the major surfaces having dimensions of, for example, about 3.2 mm by about 1.6 mm are determined as follows. 
   The multi-layer capacitor  23  has an ESL of 152 pH, the multi-layer capacitor  24  has an ESL of 84 pH, and the multi-layer capacitor  25  has an ESL of 67 pH. The larger the number of the first and second major-surface terminal electrodes  14  and  15 , the smaller the ESL value. A multi-layer capacitor having no major-surface terminal electrodes, specifically, the multi-layer capacitor  23  having no second major-surface terminal electrodes  15 , has an ESL of 212 pH. 
   The multi-layer capacitor  26  has an ESL of 75 pH, and the multi-layer capacitor  27  has an ESL of 43 pH. A multi-layer capacitor having no major-surface terminal electrodes, specifically, the multi-layer capacitor  26  having no second major-surface terminal electrodes  15 , has an ESL of 102 pH. 
   The comparison of the multi-layer capacitor  26  to the multi-layer capacitor  27  also shows that the larger the number of the first and second major-surface terminal electrodes  14  and  15 , the smaller the ESL value. 
   By comparison of the multi-layer capacitor  23  to the multi-layer capacitor  26 , and the multi-layer capacitor  24  to the multi-layer capacitor  27 , increasing the number of side surfaces  4  through  7  including the first and second side-surface terminal electrodes  12  and  13  while increasing the number of the first and second side-surface terminal electrodes  12  and  13  proves to be effective in the reduction of the ESL value. 
   A multi-layer capacitor  28  shown in  FIG. 15  includes a total of sixteen side-surface terminal electrodes  12  and  13 , i.e., two first side-surface terminal electrodes  12  and two second side-surface terminal electrodes  13  provided on each of the four side surfaces  4  through  7 . 
   From the above preferred embodiments, the number of and locations of the first and second side-surface terminal electrodes  12  and  13  are modified as necessary. Similarly, the number and arrangement of the first and second major-surface terminal electrodes  14  and  15  are modified as necessary. 
   A multi-layer capacitor  29  shown in  FIG. 16  has a minimum number of elements which the multi-layer capacitor within the scope of the present invention requires in connection with the side-surface terminal electrode and the major-surface terminal electrode. More specifically, one first side-surface terminal electrode  12  and one second side-surface terminal electrode  13  are provided on the side surface  4  while one second major-surface terminal electrode  15  is provided on one major surface  2 . 
   The multi-layer capacitor of preferred embodiments of the present invention is useful as the decoupling capacitor  35  in the MPU  31  shown in FIG.  19 . The construction of the MPUs incorporating the multi-layer capacitor of preferred embodiments of the present invention as a decoupling capacitor are now described referring to FIG.  17  and FIG.  18 . 
   Referring to  FIG. 17 , an MPU  36  includes a multi-layer wring board  38  having a cavity  37  on its lower surface. An MPU chip  39  is surface-mounted on the wiring board  38 . A multi-layer capacitor  40  according to one of the preferred embodiments of the present invention described above which functions as a decoupling capacitor is housed in the cavity  37  of the wiring board  38 . The wiring board  38  is surface-mounted on a mother board  41 . 
   As diagrammatically shown, wiring conductors required for MPU  36  are provided on the surface of or inside the wiring board  38 . Through these wiring conductors, the connections shown in  FIG. 19  are established. 
   Now typical connections are discussed. A power supply hot electrode  42  and a ground electrode  43  are provided inside the wiring board  38 . 
   The power supply hot electrode  42  is electrically connected to a particular major-surface terminal electrode  45  and a particular side-surface terminal electrode  46  of the multi-layer capacitor  40  through a via hole conductor  44 , is electrically connected to a particular terminal  48  of the MPU chip  39  through a via hole conductor  47 , and is further electrically connected to a hot conductor land  50  of the mother board  41  through a via hole conductor  49 . 
   The ground electrode  43  is electrically connected to a particular major-surface terminal electrode  52  and a particular side-surface terminal electrode  53  of the multi-layer capacitor  40  through via hole conductors  51 , is electrically connected to a particular terminal  55  of the MPU chip  39  through a via hole conductor  54 , and is further electrically connected to a ground conductor land  57  of the mother board  41  through a via hole conductor  56 . 
   The major-surface terminal electrodes  45  and  52  of the multi-layer capacitor  40  are respectively connected to the via hole conductors  44  and  51  using bump, although they are not shown in FIG.  17 . 
   A memory corresponding to the memory  34  shown in  FIG. 19  is not shown in FIG.  17 . 
   The MPU  58  shown in FIG.  18  and the MPU  36  shown in  FIG. 17  share a number of elements in common. Like elements are designated with like reference numerals, and the discussion about the common elements is not repeated. 
   In the multi-layer capacitor  40  incorporated in MPU  36  shown in  FIG. 17 , all major-surface terminal electrodes  45  and  52  are preferably provided on the one major surface in the same manner as in the preferred embodiment shown in FIG.  4 . In a multi-layer capacitor  59  incorporated in MPU  58  shown in  FIG. 18 , the major-surface terminal electrodes  45  only are provided on the one major surface while the major-surface terminal electrodes  52  are provided on the other major surface, in the same manner as in the preferred embodiment shown in FIG.  5 . 
   With this arrangement, the major-surface terminal electrodes  45  are electrically connected to the power supply hot electrode  42  through the via hole conductor  44 , while the major-surface terminal electrodes  52  are electrically directly connected to a ground conductor land of the mother board  41 . 
   The major-surface terminal electrodes  45  and  52  of the above-referenced multi-layer capacitor  59  are also connected using bumps, although the bumps are not shown in detail in FIG.  18 . 
   A memory corresponding to the memory  34  shown in  FIG. 19  is not shown in FIG.  18 . 
   In the multi-layer capacitor of preferred embodiments of the present invention, the first and second side-surface terminal electrodes are provided on at least one of the side surfaces of the capacitor body, the major-surface terminal electrodes are disposed on at least one of the major surfaces of the capacitor body, the first and second internal electrodes are electrically connected at respective ends thereof to the first side-surface terminal electrodes which are opposed to each other with the dielectric layer interposed therebetween, and one of the first and second internal electrodes is connected to the major-surface terminal electrode via the via hole conductor penetrating the dielectric layer. The directions of the currents flowing within the multi-layer capacitor are thus diversified, the magnetic fluxes are effectively canceled, and the lengths of current-carrying paths are shortened. As a result, the ESL value is greatly reduced. 
   With this arrangement, the resonance frequency of the multi-layer capacitor is heightened. The frequency range in which the multi-layer capacitor functions as a capacitor is much higher. The multi-layer capacitor of various preferred embodiments of the present invention satisfies and even exceeds the high-frequency requirement imposed on electronic circuits. For instance, the multi-layer capacitor of preferred embodiments of the present invention is useful as a bypass capacitor or a decoupling capacitor in a high-frequency circuit. 
   A quick power supply function is required of a decoupling capacitor, if it is used with an MPU chip. Because of its low ESL value, the multi-layer capacitor of preferred embodiments of the present invention meets a high-speed operational requirement in this application. 
   When the multi-layer capacitor is mounted on the wiring board, the major-surface terminal electrodes on the multi-layer capacitor of preferred embodiments of the present invention are conveniently connected using bumps. Bump connections tend to be widely used as the operating frequency increases in a semiconductor chip, such as an MPU. The use of the major-surface terminal electrodes conveniently matches the bump connection. Furthermore, the use of the bump connection achieves a high density mounting, and controls the generation of an inductance component in the connection. 
   Through the features of the present invention as discussed below, each of the above preferred embodiments of the present invention effectively and greatly lowers the ESL value by promoting the cancellation of magnetic fluxes, and shortening the lengths of the current-carrying paths. 
   As compared to conventional construction of multi-layer capacitors, there are many structural and functional differences in the preferred embodiments of the present invention. For example, the number of the side surfaces having the first and second side-surface terminal electrodes is increased to two, and to four. Also, the first side-surface terminal electrodes and the second side-surface terminal electrodes are alternately arranged adjacent to each other on each side surface. The first side-surface terminal electrodes and the second side-surface terminal electrodes are alternately arranged adjacent to each other along each of the four side surfaces, and an even lower ESL value is obtained. Further, the first and second major-surface terminal electrodes as the major-surface terminal electrodes are respectively electrically connected to the first and second internal electrodes. If the first and second major-surface terminal electrodes are disposed on one major surface only, the ESL value is even more reduced. Further, when the first and second major-surface terminal electrodes are provided as the major-surface terminal electrodes on each of the major surfaces, the one arranged closest to the first major-surface terminal electrode is the second major-surface terminal electrode and the one arranged closest to the second major-surface terminal electrode is the first major-surface terminal electrode. In addition, some of the side-surface terminals straddle two adjacent side surfaces. Also, the major surface of the capacitor body is generally square. 
   It should be understood that the foregoing description is only illustrative of the preferred embodiments of the present invention. Various alternatives and modifications can be devised by those of skill in the art without departing from the present invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications and variances which fall within the scope of the appended claims.