Patent Publication Number: US-6657425-B2

Title: Power measurement circuit including harmonic filter

Description:
TECHNICAL FIELD 
     The present invention relates to monitoring circuitry, and more specifically, to an improved technique of monitoring power delivered by power amplifiers, transistors and the like, when used in specific applications such as wireless communications. 
     BACKGROUND OF THE INVENTION 
     Solid state power devices are utilized in a variety of applications including wireless signal generation. In such applications, it is necessary and/or desirable to ascertain the amount of power being output by the particular device. 
     FIG. 1 shows an exemplary prior art circuit arrangement for measuring power delivered to a load  101  by a radio frequency (RF) signal input through capacitor  102 . The actual chip is shown as enclosed by outline  103 , with capacitor  102 , circuitry  104 , and transistors Q 1  and Q 2  “on chip”. Bonding pads  110  through  112  represent the interface from the actual chip to the pin when transmitting the signal off chip. Inductor  114  represents a ground inductance, and inductors  115  and  116  represent inherent inductors such as inductance caused by the wire bond as well as the lead frame inductance of a chip package. 
     Typically, the load  101  is driven by the RF signal  130  through an off chip-matching network  132 . In order to measure the power being delivered to the load, several techniques are available. Some involve constructing a voltage divider circuit and then measuring a fraction of the signal applied to the load. Others utilize an off chip averaging circuit. Plural other techniques exist as well. 
     The arrangement of FIG. 1 describes one prior art technique for measuring the power delivered to the load. More specifically, transistor Q 2  is selected at a value much smaller than transistor Q 1 , such that the current through transistor Q 2  is only 1% or less of that through Q 1 . An averaging circuit includes resistor  140  and capacitor  142 . 
     FIG. 2 shows a graph of the voltage at the point V detect  in FIG. 1, as a function of the power delivered by the device. Notably, at approximately 1.8 watts, the slope of the curve in FIG. 2 becomes positive. This change in slope is due to several factors. One reason for the change in slope can be appreciated from a review of FIG. 3, a close up of transistor Q 2  showing the inherent base collector diode  301  and the substrate collector diode  302 . Both of these diodes are inherent in the device and are result of the physics of fabrication. However, at high power levels, these diodes become forward biased and introduce extra current paths into the collector of Q 2 . Accordingly, the current being measured and shown as i_sense in FIG. 1 is no longer an accurate measure of the power being delivered by the device. Instead, the measured signal is distorted because the high voltage variations at relatively high power cause additional current paths into the collector of Q 2 . Additionally, the coupling between inductors  115  and  116  causes further errors in the current i_sense. As a result, the measurement system shown in FIG. 1 only works for lower power signals, but does not operate properly at higher powers. 
     In view of the above, there exists a need in the art for an improved technique of providing current and power measurement in devices at high output power levels. This issue is particularly important in wireless communications devices, where circuitry similar to that shown in FIG. 1 is used. 
     It is an object of the invention to provide such power measurement in a manner that does not require the use of large components and bulky, lossy devices. 
     SUMMARY OF THE INVENTION 
     The above and other problems of the prior art are overcome in accordance with the present invention. A measurement transistor Q 2  is connected in parallel with the power transistor Q 1 . A shorting device is connected in parallel with the measurement transistor in order to short signals to ground, but only signals that are substantially the same as the frequency of an input RF signal. In a preferred embodiment, the shorting device is an inductor/capacitor (LC) resonant circuit. 
     In accordance with the invention, high frequency signals, which would vary greatly in voltage and cause the additional current paths discussed above are shorted to ground. By utilizing a resonant circuit, use of a large capacitor is avoided, yet the desired impedance in the shorting device is achieved. 
     In an additional preferred embodiment, the capacitor for the shorting device is constructed on chip, and the inductor portion of the LC resonant circuit comprises inherent inductance in a chip-bonding pad. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 depicts a prior art arrangement for measuring power delivered to a load; 
     FIG. 2 shows a voltage power curve for the arrangement of FIG. 1; 
     FIG. 3 shows the inherent diodes in a transistor device utilized in the arrangement of FIG. 1; 
     FIG. 4 shows an exemplary embodiment of the present invention; 
     FIG. 5 shows the power transfer curve of the arrangement of FIG. 4; and 
     FIG. 6 shows an alternative embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     FIG. 4 shows an exemplary embodiment of the present invention. In operation, an RF signal  420  is injected through capacitor  402  and transistor Q 1 . Bias circuitry  401  operates in a conventional fashion. The averaging circuit formed by resistor  409  and capacitor  410  provides a DC voltage at V detect , which is substantially proportional to the power being delivered to load resistor  411 . 
     However, the current caused by this V detect , and thus as measured through transistor Q 2 , is distorted by the effects previously described. Specifically, the coupling between inductors  408  and  404 , and the inherent diodes between the collector of transistor Q 2  and the substrate  2 , as well as the base collector diode, all cause current distortions which would lead to inaccurate measurements. 
     The presence of capacitor  406  and inductor  407  serves to minimize and/or eliminate high frequency components in the signal at the collector of Q 2 . These high frequency components are variations, which cause additional current components and thus distort the measure of the power delivered to the load  411 . 
     Preferably, capacitor  406  and inductor  407  are arranged with values to resonate at the desired operating frequency. As is well known, the series connection of an LC resonant circuit appears as a short circuit at the critical frequency, that at which the RF signal is delivered. Moreover, the capacitor may be added on chip with minimal cost, and the inductor  407  is a wire bond inductance, inherent in the system anyway. 
     In the preferred embodiment, further elimination of unwanted extraneous signals at the collector of Q 2  is achieved by increasing the resistance between the substrate level on which Q 1  is deposited, and a second substrate level on which Q 2  is deposited. One such technique involves placing a substrate tap around Q 2 , which is separate from the tap placed around Q 1 . Regardless of the technique used, the substrates are isolated with an increased resistance so as to effectively and substantially eliminate the cross inductance caused by the coupling of L 2  and L 3 . 
     A response curve showing V detect  as a function of the output power of the device with a modified circuit in FIG. 4 is shown in FIG.  5 . As can be appreciated from FIG. 5, there is no longer a positively sloped portion of the curve at higher output powers. This negatively sloped curve is important in feedback systems, which can become unstable when the slope of the curve turns positive as in the prior system depicted at FIG.  2 . 
     An alternative embodiment of the present invention is shown in FIG.  6 . Most of the components are substantially similar to those previous described with respect to FIG. 4, and thus, we will not repeat the description. 
     An averaging circuit  601  comprises a resistor  602  and capacitor  603 . Two series inductors  604  and  605  are utilized. Inductor  604  (which can also be a transmission line) provides a large inductance at RF. Inductor  608  and resistor  609  are parasitic components inherent in the installed capacitor  607 . The remainder of the operation of the circuit is as before. 
     Inductors  605  and  608  act in conjunction with capacitor  607  as a resonant circuit. The inductor  605  represents the inductance of the bonding pad  606 . Capacitor  607  and inductors  608  and  605  are chosen such that the resonant frequency of the circuit is at substantially the same frequency as the input RF signal. 
     At the desired frequency, the path into the collector of Q 2  becomes short, and thus, the distortion that disrupts the measurement is reduced. It is noted however, that the embodiment of FIG. 6 may be less preferable to that of FIG.  4 . This is due to the fact that the coupling K 23  shown in FIG. 6 is not significantly reduced by the use of a resonant circuit in the manner of FIG. 6, whereas in the embodiment of FIG. 4, such coupling is virtually eliminated. To minimize K 23  coupling, the wirebonds and pin-outs must be apart from each other. To further decrease the coupling, a ground wirebond/ground pin should separate them. 
     However, the embodiment of FIG. 6 eliminates the two sources of error discussed above with respect to FIG. 3, and has the potential advantage of not requiring any on chip fabrication of components, as would be required for the embodiment depicted in FIG.  4 . The choice between the two techniques, or other techniques of implementing a shorting circuit in parallel with the measurement transistor Q 2 , is a choice for the designer. 
     It is understood that while the foregoing describes the preferred embodiment of the invention, various other modifications and additions will be apparent to those of skill in the art.