Patent Publication Number: US-10324254-B2

Title: Method for the formation of nano-scale on-chip optical waveguide structures

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. application Ser. No. 14/933,095 filed Nov. 5, 2015, which is a continuation of U.S. application Ser. No. 13/901,298 filed May 23, 2013 (now U.S. Pat. No. 9,206,526), the disclosures of which are incorporated by reference. 
    
    
     TECHNICAL FIELD 
     The present invention relates to integrated optical circuits and, in particular, to optical waveguide structures formed in and supported by semiconductor substrates. 
     BACKGROUND 
     There is considerable interest in photonic integrated circuit technologies for both active and passive devices. 
     It is well known to transport electronic data between a data source and a data destination over an optical data path. The use of fiber-optic communications lines presents one well-known example of an optical data path. Indeed, with the continued development of optical communications technologies, functions previously performed in the electrical domain are now migrating into the optical domain. Optical channels are now replacing electric wires for the communication of electronic data, and optical signal processing is now replacing transistor signal processing for the manipulation of electronic data. 
     This migration towards optical solutions has even progressed down to the level of the integrated circuit. In this regard, the prior art teaches a number of optical waveguide structures implemented in semiconductor substrates. Compact on-chip optical waveguide structures are recognized to have extensive uses in semiconductor photonics. 
     As semiconductor integrated circuit process technology shrinks towards nano-scale features it is important for the optical waveguide structures formed in or supported by the integrated circuit substrate to also achieve nano-scale dimensions. However, it is difficult to make well-defined on-chip optical waveguide structures, especially in the nano-scale. In particular, there is a need to form densely populated hollow optical waveguides. 
     SUMMARY 
     In an embodiment, an optical waveguide comprises: a layer of semiconductor material having a bottom surface, said layer of semiconductor material including at least one hollow optical channel contained within the layer of semiconductor material and extending with a length parallel to the bottom surface, said layer of semiconductor material further having a non-planar top surface including first substantially planar top surface portions on either side of the at least one hollow optical channel and a second curved top surface extending over the at least one hollow optical channel, wherein a lowest portion of an inner surface of the at least one hollow optical channel is positioned below the first substantially planar top surface portions of said layer of semiconductor material. 
     In an embodiment, an optical waveguide comprises: a first layer of semiconductor material; a second layer of semiconductor material having a bottom surface in contact with the first layer of semiconductor material and further having a top surface; a hollow optical channel contained within the second layer of semiconductor material and extending with a length parallel to the bottom surface; wherein said top surface comprises first top surface portions on either side of the hollow optical channel and a second curved top surface portion extending over the hollow optical channel; wherein a lowest portion of an inner surface of the hollow optical channel is positioned below the first top surface portions; and wherein a highest portion of an inner surface of the hollow optical channel is positioned above the first top surface portions. 
     In an embodiment, an optical waveguide comprises: a supporting semiconductor substrate having a top surface; and a layer of semiconductor material having a bottom surface in contact with the top surface of the supporting semiconductor substrate, said layer of semiconductor material including at least one hollow optical channel contained within the layer of semiconductor material and extending with a length parallel to the top surface of the supporting semiconductor substrate, said layer of semiconductor material further having a non-planar top surface including first top surface portions on either side of the at least one hollow optical channel and a second top surface extending over the at least one hollow optical channel, wherein a lowest portion of an inner surface of the at least one hollow optical channel is positioned below the first top surface portions of said layer of semiconductor material. 
     In an embodiment, an optical waveguide comprises: a supporting semiconductor substrate having a top surface; and a layer of semiconductor material having a bottom surface in contact with the top surface of the supporting semiconductor substrate, said layer of semiconductor material including at least one hollow optical channel contained within the layer of semiconductor material and extending with a length parallel to the top surface of the supporting semiconductor substrate, said layer of semiconductor material further having a non-planar top surface including first top surface portions on either side of the at least one hollow optical channel and a second top surface extending over the at least one hollow optical channel, wherein a highest portion of the inner surface of the at least one hollow optical channel is positioned above the first top surface portions of said layer of semiconductor material. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which: 
         FIGS. 1-10  illustrates process steps in the formation of a nano-scale on-chip optical waveguide structure. 
     
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     Reference is now made to  FIGS. 1-10  which illustrate the process steps in the formation of a nano-scale on-chip optical waveguide structure. It will be understood that the drawings are not necessarily presented to scale. 
       FIG. 1  shows a conventional silicon-on-insulator (SOI) substrate  10  formed by insulator layer  100  of silicon dioxide formed on a first silicon (Si) layer  102 . A second silicon (Si) layer  104  is formed over the insulator layer  100 . In a preferred implementation, the SOI substrate  10  is of the partially-depleted (PD) type (i.e., the substrate  10  comprises PD SOI as known in the art). The first and second silicon layers  102  and  104  may be doped as needed for the integrated circuit application. The thickness of the first and second silicon layers  102  and  104  may be tuned (for example, through the use of a thinning operation) as needed for the integrated circuit application. Although a PD SOI is preferred, it will be understood that other types of SOI substrates, including fully depleted (FD), could instead be used. 
       FIG. 2  shows the deposit of a silicon dioxide (SiO 2 ) layer  106  over the second silicon (Si) layer  104 . 
       FIG. 3  shows the deposit of a silicon nitride (SiN) layer  108  over the silicon dioxide layer  106 . 
     A lithographic process as known in the art is then used to form an opening  110  in the silicon nitride layer  108  and silicon dioxide layer  106  (a SiN/SiO 2  hard mask) which extends down to reach at least the top surface of the second silicon (Si) layer  104 . The result of the lithographic process is shown in  FIG. 4 . The opening  110  may, in plan view, take on any desired shape governed by the dimensions of a waveguide area within which the nano-scale on-chip optical waveguide structures are to be produced. Exemplary shapes for the opening  110  include square and rectangular shapes. 
     An epitaxial growth process as known in the art is then performed to grow a silicon-germanium (SiGe) layer  112  on top of the second silicon (Si) layer  104  within the opening  110 . This silicon-germanium (SiGe) layer  112  is a sacrificial material layer as will be described in more detail below. The epitaxial growth process continues with the formation of a silicon layer (Si)  114  on top of the silicon-germanium (SiGe) layer  112  within the opening  110 . The result of the two step epitaxial growth process is shown in  FIG. 5 . 
     A lithographic process as known in the art is then used to form a plurality of trenches  116  which define at least one line  118  formed of a remaining portion of the second silicon (Si) layer  104 , a remaining portion of the silicon-germanium (SiGe) layer  112  and a remaining portion of the silicon layer  114  as a material strip interposed between adjacent parallel trenches  116 . The result of the lithographic process is shown in  FIG. 6 . Thus, a trench  116  is formed on either side of each line  118 . If multiple lines  118  are formed, the trenches  116  may be shared between the lines  118 . The trenches  116  extend completely through the silicon-germanium (SiGe) layer  112  and silicon layer (Si)  114  and in a preferred implementation further extend partially into the second silicon (Si) layer  104  of the SOI substrate  10 . Each included line  118  extends as a bi-layer material strip along the opening  110 , with multiple lines  118  in parallel with each other. Although two lines  118  are shown, it will be understood one fewer or more lines  118  could be provided within the opening  110  as dictated by the photonic needs of the integrated circuit application. Alternatively, the trenches  116  extend completely through the silicon-germanium (SiGe) layer  112  and silicon layer (Si)  114  to at least reach a top surface of the second silicon (Si) layer  104  of the SOI substrate  10  (it being important to remove the silicon-germanium (SiGe) layer  112  within each trench). 
     An epitaxial growth process as known in the art is then performed to grow a silicon layer (Si)  120  on top of the exposed surfaces of the second silicon (Si) layer  104 , the silicon-germanium (SiGe) layer  112  and the silicon layer (Si)  114 . The silicon layer (Si)  120  is a conformal layer covering the sides and top of the material strip. The result of the epitaxial growth process is shown in  FIG. 7 . 
       FIG. 8  shows that the SiN/SiO 2  hard mask has been removed. The effect of the removal of the SiN/SiO 2  hard mask is to expose the ends of the lines  118 . In other words, this will give the process access to the silicon-germanium (SiGe) layer  112  within each of the lines  118 . 
     In an exemplary implementation, the width w of the lines  118  may be of the range of 100 nm to hundreds of nm. The length of the lines  118  (extending perpendicular to the width w) may be of the range of several hundred nanometers to hundreds of microns. The etch selectivity between SiGe and Si can reach &gt;300, under HCl, so the maximum length of the line  118  is decided by the thickness of the Si layer  120  which should typically be several tens of nanometers to several hundred nanometers. A spacing z between adjacent lines  118  may be of the range of several tens of nanometers to tens of microns or more as defined by the photomask. 
     An etch process as known in the art is then performed to selectively remove the sacrificial material of the silicon-germanium (SiGe) layer  112  from within each of the lines  118 . In an embodiment, the etch may comprise an HCl dry etch which is selective to remove SiGe and leave the Si structures in place. The result of the selective etch process is shown in  FIG. 9 . As a result of the removal of the silicon-germanium (SiGe) layer  112 , each line  118  includes a hollow channel  122  which extends along the length of the line. The hollow channel  122  is surrounded on all sides by silicon structures in the form of silicon layer (Si)  120 , second silicon (Si) layer  104  and silicon layer (Si)  114 . 
     As an alternative, a wet clean such as hot SC1 (a mix of NH4OH and H2O2) can be used for the selective removal of SiGe, but this technique has significantly lower selectivity than HCl. 
     An anneal process as known in the art is then performed in order to effectuate a reflow of the silicon structures surrounding the hollow channels  122 . In an embodiment, the anneal may comprise an anneal in a hydrogen (H 2 ) atmosphere at a temperature of 700 degrees Celsius for a duration of about 30 minutes to achieve Si reflow. The result of the anneal process is shown in  FIG. 10 . The hollow channels  122  reform to have a generally circular cross-section surrounded by the Si structures of silicon layer (Si)  120 , second silicon (Si) layer  104  and silicon layer (Si)  114 . The diameter of the channels  122  may be selected by choosing the thickness of the epitaxially grown silicon-germanium (SiGe) layer  112 . Because accurate control can be exercised over epitaxial growth thicknesses, the process described can produce consistently sized hollow channels  122  for use as nano-scale on-chip optical waveguide structures  124 . 
     In a preferred implementation, as a result of the reflow the hollow channels  122  are produced in a manner wherein a lower portion of the channel  122  is positioned below an upper surface of the reflowed second silicon (Si) layer  104 . 
     In an exemplary implementation, the width x of the structures  124  may be of the range of 100 nm to hundreds of nanometers. In an exemplary implementation, the diameter y of the hollow channels  122  within the structures  124  may be of the range of 50 nanometers to hundreds of nanometers. A spacing z between adjacent structures  124  may be of the range of several tens of nanometers to tens of microns. 
     Although an SOI type substrate is preferred, it will be understood that a non-SOI type substrate including the second silicon (Si) layer  104  (alone or perhaps as an epitaxial growth over an underlying intrinsic or non-intrinsic semiconductor layer) could be used in place of the PD SOI substrate  10 . In such a case, the illustrated layers  100  and  102  would either be absent or replaced by the underlying intrinsic or non-intrinsic semiconductor layer. 
     The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.