Patent Publication Number: US-9892997-B2

Title: Adaptable molded leadframe package and related method

Description:
BACKGROUND 
     A leadframe assembly, often having a leadframe and one or more semiconductor dies can simplify circuit design, reduce costs, and provide greater efficiency and improved performance by keeping related and dependent circuit components in close proximity. Also, a leadframe assembly can facilitate application integration and greater electrical and thermal performance compared to using separate packaging for various circuit components. 
     Conventional leadframe assemblies can be configured either in a single-in-line package (SIP) where all of the leads protrude from one side of the package, or in a dual-in-line package (DIP) where all of the leads protrude from two sides of the package. When switching from a dual-in-line package to a single-in-line package, semiconductor components and electrical routing need to undergo a complete redesign, which requires reconfiguration of the entire package, thus increasing manufacturing cost, time and complexity. 
     Accordingly, there is a need to overcome the drawbacks and deficiencies in the art by providing a highly adaptable leadframe package that allows an easy conversion from a dual-in-line package to a single-in-line package. 
     SUMMARY 
     The present disclosure is directed to an adaptable molded leadframe package and related method, substantially as shown in and/or described in connection with at least one of the figures, and as set forth in the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  illustrates a top plan view of a portion of a semiconductor package processed in accordance with an initial processing action according to one implementation of the present application. 
         FIG. 1B  illustrates a top plan view of a portion of a semiconductor package processed in accordance with an intermediate processing action according to one implementation of the present application. 
         FIG. 1C  illustrates a top plan view of a portion of a semiconductor package processed in accordance with a final processing action according to one implementation of the present application. 
         FIG. 2A  illustrates a top plan view of a portion of a semiconductor package processed in accordance with an initial processing action according to one implementation of the present application. 
         FIG. 2B  illustrates a top plan view of a portion of a semiconductor package processed in accordance with an intermediate processing action according to one implementation of the present application. 
         FIG. 2C  illustrates a top plan view of a portion of a semiconductor package processed in accordance with an intermediate processing action according to one implementation of the present application. 
         FIG. 2D  illustrates a top plan view of a portion of a semiconductor package processed in accordance with a final processing action according to one implementation of the present application. 
         FIG. 2E  illustrates a top plan view of a portion of a semiconductor package processed in accordance with an optional processing action according to one implementation of the present application. 
         FIG. 3A  illustrates a cross sectional view of a portion of a dual-in-line semiconductor package according to one implementation of the present application. 
         FIG. 3B  illustrates a cross sectional view of a portion of a dual-in-line semiconductor package according to one implementation of the present application. 
         FIG. 3C  illustrates a cross sectional view of a portion of a dual-in-line semiconductor package according to one implementation of the present application. 
         FIG. 3D  illustrates a cross sectional view of a portion of a dual-in-line semiconductor package according to one implementation of the present application. 
         FIG. 4A  illustrates a cross sectional view of a portion of a single-in-line semiconductor package according to one implementation of the present application. 
         FIG. 4B  illustrates a cross sectional view of a portion of a single-in-line semiconductor package according to one implementation of the present application. 
         FIG. 4C  illustrates a cross sectional view of a portion of a single-in-line semiconductor package according to one implementation of the present application. 
         FIG. 4D  illustrates a cross sectional view of a portion of a single-in-line semiconductor package according to one implementation of the present application. 
         FIG. 5A  illustrates a cross sectional view of a portion of a dual-in-line semiconductor package according to one implementation of the present application. 
         FIG. 5B  illustrates a cross sectional view of a portion of a dual-in-line semiconductor package according to one implementation of the present application. 
         FIG. 5C  illustrates a cross sectional view of a portion of a dual-in-line semiconductor package according to one implementation of the present application. 
         FIG. 5D  illustrates a cross sectional view of a portion of a dual-in-line semiconductor package according to one implementation of the present application. 
         FIG. 6A  illustrates a cross sectional view of a portion of a single-in-line semiconductor package according to one implementation of the present application. 
         FIG. 6B  illustrates a cross sectional view of a portion of a single-in-line semiconductor package according to one implementation of the present application. 
         FIG. 6C  illustrates a cross sectional view of a portion of a single-in-line semiconductor package according to one implementation of the present application. 
         FIG. 6D  illustrates a cross sectional view of a portion of a single-in-line semiconductor package according to one implementation of the present application. 
         FIG. 7  illustrates a schematic diagram of an exemplary multi-phase inverter circuit of a semiconductor package according to one implementation of the present application. 
     
    
    
     DETAILED DESCRIPTION 
     The following description contains specific information pertaining to implementations in the present disclosure. The drawings in the present application and their accompanying detailed description are directed to merely exemplary implementations. Unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. Moreover, the drawings and illustrations in the present application are generally not to scale, and are not intended to correspond to actual relative dimensions. 
     Referring to  FIG. 1A ,  FIG. 1A  illustrates a top plan view of a portion of a semiconductor package processed in accordance with an initial processing action according to one implementation of the present application. For example, the initial processing action includes disposing at least one semiconductor device on a continuous conductive structure having a leadframe island coupled to a first lead and a second lead. 
     As illustrated in  FIG. 1A , structure  180  includes leadframe  130  having continuous conductive structures  110 ,  112 ,  114 ,  116 ,  120 ,  122  and  124 , and semiconductor devices  104   a ,  106   a  and  108   a  situated on continuous conductive structure  110 , semiconductor device  108   b  situated on continuous conductive structure  112 , semiconductor device  104   b  situated on continuous conductive structure  114 , and semiconductor device  106   b  situated on continuous conductive structure  116 . 
     As illustrated in  FIG. 1A , each of continuous conductive structures  110 ,  112 ,  114 ,  116 ,  120 ,  122  and  124  includes a leadframe island and a pair of leads coupled to the leadframe island on opposing sides thereof. For example, continuous conductive structure  110  includes leads  110   b  and  110   c  coupled to leadframe island  110   a , where leads  110   b  and  110   c  extend from opposing sides of leadframe island  110   a  to form a continuous conductive path for at least one of semiconductor devices  104   a ,  106   a  and  108   a . Continuous conductive structure  112  includes leads  112   b  and  112   c  coupled to leadframe island  112   a , where leads  112   b  and  112   c  extend from opposing sides of leadframe island  112   a  to form a continuous conductive path for semiconductor device  108   b . Continuous conductive structure  114  includes leads  114   b  and  114   c  coupled to leadframe island  114   a , where leads  114   b  and  114   c  extend from opposing sides of leadframe island  114   a  to form a continuous conductive path for semiconductor device  104   b . Continuous conductive structure  116  includes leads  116   b  and  116   c  coupled to leadframe island  116   a , where leads  116   b  and  116   c  extend from opposing sides of leadframe island  116   a  to form a continuous conductive path for semiconductor device  106   b . Similarly, continuous conductive structures  120 ,  122  and  124  each include a leadframe island (e.g., leadframe islands  120   a ,  122   a  and  124   a , respectively) and a pair of leads (e.g., leads  120   b  and  120   c , leads  122   b  and  122   c , and leads  124   b  and  124   c , respectively) extending from opposing sides of the leadframe island. In one implementation, continuous conductive structures  110 ,  112 ,  114 ,  116 ,  120 ,  122  and  124  of leadframe  130  each include conductive material, such as copper or copper alloy. 
     As illustrated in  FIG. 1A , semiconductor devices  104   a ,  106   a  and  108   a  are situated on leadframe island  110   a  of continuous conductive structure  110 . In one implementation, semiconductor devices  104   a ,  106   a  and  108   a  each include at least one terminal (not explicitly shown in  FIG. 1A ) on their respective top surfaces and at least one terminal (not explicitly shown in  FIG. 1A ) on their respective bottom surfaces. For example, the respective bottom terminals of semiconductor devices  104   a ,  106   a  and  108   a  are electrically coupled to leadframe island  110   a  of continuous conductive structure  110 , which provides a conductive path between lead  110   b , lead  110   c  and the bottom terminals through leadframe island  110   a . The construction of continuous conductive structure  110  allows semiconductor devices  104   a ,  106   a  and  108   a  to continue to function even when one of leads  110   b  and  110   c  is removed (e.g., trimmed) from continuous conductive structure  110 . 
     As illustrated in  FIG. 1A , semiconductor device  108   b  is situated on leadframe island  112   a  of continuous conductive structure  112 . Semiconductor device  108   b  includes at least one terminal on a bottom surface thereof and electrically coupled to leadframe island  112   a  of continuous conductive structure  112 , which provides a conductive path between lead  112   b , lead  112   c  and the bottom terminal through leadframe island  112   a . Semiconductor device  104   b  is situated on leadframe island  114   a  of continuous conductive structure  114 . Semiconductor device  104   b  includes at least one terminal on a bottom surface thereof and electrically coupled to leadframe island  114   a  of continuous conductive structure  114 , which provides a conductive path between lead  114   b , lead  114   c  and the bottom terminal through leadframe island  114   a . Semiconductor device  106   b  is situated on leadframe island  116   a  of continuous conductive structure  116 . Semiconductor device  106   b  includes at least one terminal on a bottom surface thereof and electrically coupled to leadframe island  116   a  of continuous conductive structure  116 , which provides a conductive path between lead  116   b , lead  116   c  and the bottom terminal through leadframe island  116   a . Similar to continuous conductive structure  110 , continuous conductive structures  112 ,  114  and  116  allow semiconductor devices  108   b ,  104   b  and  106   b , respectively, to continue to function even when one of their respective leads is removed (e.g., trimmed). 
     As illustrated in  FIG. 1A , the terminals of the respective top surfaces of semiconductor devices  104   a ,  106   a  and  108   a  are electrically coupled to lead  114   b , lead  116   b  and leadframe island  112   a , respectively, by bond wires. The terminals on the respective top surfaces of semiconductor devices  104   b ,  106   b  and  108   b  are electrically coupled to leadframe islands  122   a ,  124   a  and  120   a , respectively, by bond wires. In one implementation, at least one of semiconductor devices  104   a ,  104   b ,  106   a ,  106   b ,  108   a  and  108   b  is a power semiconductor switch, such as a power metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT) (e.g., a gallium nitride or silicon carbide HEMT) or a diode. 
     Referring to  FIG. 1B ,  FIG. 1B  illustrates a top plan view of a portion of a semiconductor package processed in accordance with an intermediate processing action according to one implementation of the present application. For example, the intermediate processing action includes encapsulating the at least one semiconductor device and the continuous conductive structure such that the first lead protrudes from one side of the semiconductor package and the second lead protrudes from another side of the semiconductor package. 
     As illustrated in  FIG. 1B , structure  182  includes encapsulant  150  covering semiconductor devices  104   a ,  104   b ,  106   a ,  106   b ,  108   a  and  108   b , and continuous conductive structures  110 ,  112 ,  114 ,  116 ,  120 ,  122  and  124 . For example, encapsulant  150  covers leadframe islands  110   a ,  112   a ,  114   a ,  116   a ,  120   a ,  122   a  and  124   a  of continuous conductive structures  110 ,  112 ,  114 ,  116 ,  120 ,  122  and  124 , respectively. Encapsulant  150  also covers portions of leads  110   b ,  112   b ,  114   b ,  116   b ,  120   b ,  122   b  and  124   b  on one side of leadframe  130 , and portions of leads  110   c ,  112   c ,  114   c ,  116   c ,  120   c ,  122   c  and  124   c  on another side of leadframe  130 . 
     In the present implementation, encapsulant  150  includes a mold compound, such as a plastic with a low flexural modulus. In one implementation, encapsulant  150  may include a high thermal conductive mold compound to achieve high voltage isolation. It should be noted that, during the molding process, leadframe  130  is suspended from both sides of structure  182 . Having leads suspended on both sides can improve the stability of leadframe  130  during the molding process, thereby allowing better control of the thickness of encapsulant  150 . 
     It is noted that after encapsulation, structure  182  is a dual-in-line semiconductor package, such as a molded dual-in-line leadframe package. As can be seen in  FIG. 1B , in structure  182 , each of continuous conductive structures  110 ,  112 ,  114 ,  116 ,  120 ,  122  and  124  traverses the entire width of the semiconductor package, and has leads protruding from opposing sides of the semiconductor package to provide electrical connections to corresponding semiconductor devices on both sides. For example, continuous conductive structure  110  has leads  110   b  and  110   c  protruding from opposing sides of encapsulant  150  of the dual-in-line semiconductor package. Lead  110   b  is configured to provide electrical connection to at least one of semiconductor devices  104   a ,  106   a  and  108   a  on one side of the dual-in-line semiconductor package. Lead  110   c  is configured to provide electrical connection to at least one of semiconductor devices  104   a ,  106   a  and  108   a  on another side of the dual-in-line semiconductor package. The construction of continuous conductive structure  110  allows at least one of semiconductor devices  104   a ,  106   a  and  108   a  on leadframe island  110   a  to continue to function even when one of leads  110   b  and  110   c  is removed (e.g., trimmed) from continuous conductive structure  110 . Similarly, each of continuous conductive structures  112 ,  114 ,  116 ,  120 ,  122  and  124  also has leads protruding from opposing sides of encapsulant  150  of the dual-in-line semiconductor package. Thus, continuous conductive structures  112 ,  114  and  116  allow semiconductor devices  108   b ,  104   b  and  106   b , respectively, to continue to function even when one of their respective leads is removed (e.g., trimmed). 
     Referring to  FIG. 1C ,  FIG. 1C  illustrates a top plan view of a portion of a semiconductor package processed in accordance with a final processing action according to one implementation of the present application. For example, the final processing action includes removing, for example, by trimming one of the first and second leads from the semiconductor package. 
     As illustrated in  FIG. 1C , portions of leads  110   c ,  112   c ,  114   c ,  116   c ,  120   c ,  122   c , and  124   c  protruding from one side of structure  182  in  FIG. 1B  are removed by, for example, trimming or cutting. Because continuous conductive structures  110 ,  112 ,  114 ,  116 ,  120 ,  122  and  124  each have two leads electrically coupled to and extending from a leadframe island to form a continuous electrical path for their corresponding semiconductor devices, after trimming the leads on one side of the semiconductor package, the semiconductor devices can continue to function by using the remaining leads on the opposite side of the semiconductor package for electrical connection. 
     As illustrated in  FIG. 1C , a portion of lead  110   c  of continuous conductive structure  110  protruding from encapsulant  150  is removed, and optionally insulated by insulation cap  148   a , such that no electrical connection may be made to lead  110   c  from outside of the semiconductor package. Since continuous conductive structure  110  still has lead  110   b  electrically coupled to and extending from leadframe island  110   a , semiconductor devices  104   a ,  106   a  and  108   a  can rely on leadframe island  110   a  and lead  110   b  for electrical connection and continue to function properly after trimming lead  110   c . Similarly, semiconductor device  104   b  can rely on leadframe island  114   a  and lead  114   b  of continuous conductive structure  114  for electrical connection and continue to function properly after trimming lead  114   c ; semiconductor device  106   b  can rely on leadframe island  116   a  and lead  116   b  of continuous conductive structure  116  for electrical connection and continue to function properly after trimming lead  116   c ; semiconductor device  108   b  can rely on leadframe island  112   a  and lead  112   b  of continuous conductive structure  112  for electrical connection and continue to function properly after trimming lead  112   c.    
     In one implementation, after trimming, the trimmed leads  110   c ,  112   c ,  114   c ,  116   c ,  120   c ,  122   c  and  124   c  each have an exposed surface. In another implementation, as illustrated in  FIG. 1C , after trimming portions of leads  110   c ,  112   c ,  114   c ,  116   c ,  120   c ,  122   c  and  124   c , insulation caps  148   a ,  148   b ,  148   c ,  148   d ,  148   e ,  148   f  and  148   g  are optionally disposed on the exposed surfaces of the trimmed leads  110   c ,  112   c ,  114   c ,  116   c ,  120   c ,  122   c  and  124   c , respectively, such that no electrical connection can be made to the trimmed leads from outside of the semiconductor package. 
     It is noted that, after trimming, structure  184  is converted from the dual-in-line semiconductor package shown in  FIG. 1B  to a single-in-line semiconductor package, such as a molded single-in-line leadframe package, with leads protruding only from one side of structure  184 . As can be seen in  FIG. 1C , in structure  184 , after trimming the portions of leads  110   c ,  112   c ,  114   c ,  116   c ,  120   c ,  122   c  and  124   c  protruding from encapsulant  150 , the remaining portions of leads  110   c ,  112   c ,  114   c ,  116   c ,  120   c ,  122   c  and  124   c  covered by encapsulant  150  stay intact in structure  184 , which would not be present in conventional SIP packages. The reason why the remaining portions of leads  110   c ,  112   c ,  114   c ,  116   c ,  120   c ,  122   c  and  124   c  would not be present in conventional SIP packages is that conventional SIP packages only require leads protruding from one side the package. Thus, only one lead would extend from a conductive structure and protrude from one side of the conventional SIP package, and would not traverse the entire width of the conventional SIP package. By contrast, in the present implementation, with the presence of the remaining portions of leads  110   c ,  112   c ,  114   c ,  116   c ,  120   c ,  122   c  and  124   c , each of respective continuous conductive structures  110 ,  112 ,  114 ,  116 ,  120 ,  122  and  124  traverses the entire width of the semiconductor package, and has leads protruding from one side of the semiconductor package for electrical connection. Among other advantages, continuous conductive structures  110 ,  112 ,  114 ,  116 ,  120 ,  122  and  124 , each having leads extending from two opposite sides of a leadframe island, allow for an easy conversion from a dual-in-line semiconductor package to a single-in-line semiconductor package without reconfiguring the internal structure (e.g., arrangements of the semiconductor components or related electrical routing paths) of the leadframe package, thereby substantially reduce manufacturing time, cost and complexity. 
     Although  FIG. 1C  shows trimming of portions of leads  110   c ,  112   c ,  114   c ,  116   c ,  120   c ,  122   c  and  124   c  protruding from one side of encapsulated leadframe  130 , it should be understood that, in another implementation, the trimming can be performed on the opposite side of structure  184  (e.g., by removing portions of leads  110   b ,  112   b ,  114   b ,  116   b ,  120   b ,  122   b  and  124   b  protruding from encapsulated leadframe  130 ), and still allows structure  184  to function as a SIP package by relying on untrimmed leads  110   c ,  112   c ,  114   c ,  116   c ,  120   c ,  122   c  and  124   c  for electrical connection. 
     Referring to  FIG. 2A ,  FIG. 2A  illustrates a top plan view of a portion of a semiconductor package processed in accordance with an initial processing action according to one implementation of the present application. For example, the initial processing action includes disposing a first high-side power switch of a multi-phase inverter on a first high-side portion of a leadframe, and disposing a first low-side power switch on a first low-side portion of the leadframe. 
     As illustrated in  FIG. 2A , structure  280  includes first high-side power switch  204   a , second high-side power switch  206   a  and third high-side power switch  208   a  situated on first high-side continuous conductive structure  210  of leadframe  230 , first low-side power switch  204   b  situated on first low-side continuous conductive structure  214  of leadframe  230 , second low-side power switch  206   b  situated on second low-side continuous conductive structure  216  of leadframe  230 , and third low-side power switch  208   b  situated on third low-side continuous conductive structure  212  of leadframe  230 . Structure  280  also includes driver integrated circuit (IC)  202  situated on driver IC continuous conductive structure  218  of leadframe  230 . In one implementation, structure  280  may be part of a high voltage (HV) multi-phase inverter. 
     In the present implementation, first high-side power switch  204   a  and first low-side power switch  204   b  (hereinafter collectively referred to as U-phase power switches  204 ), second high-side power switch  206   a  and second low-side power switch  206   b  (hereinafter collectively referred to as V-phase power switches  206 ), and third high-side power switch  208   a  and third low-side power switch  208   b  (hereinafter collectively referred to as W-phase power switches  208 ) are power semiconductor devices, which may correspond to semiconductor devices  104   a ,  104   b ,  106   a ,  106   b ,  108   a  and  108   b  in  FIGS. 1A-1C . In one implementation, at least one of U-phase power switches  204 , V-phase power switches  206  and W-phase power switches  208  is a power semiconductor switch, such as a power metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT) (e.g., a gallium nitride or silicon carbide HEMT) or a diode. In one implementation, at least one of U-phase power switches  204 , V-phase power switches  206  and W-phase power switches  208  may include group IV semiconductor material, such as silicon, or group III-V semiconductor material, such as gallium nitride (GaN). 
     In the present implementation, first high-side power switch  204   a  includes power terminal  238   a  (e.g., a source terminal) and control terminal  240   a  (e.g., a gate terminal) on a top surface thereof, and another power terminal (e.g., a drain terminal), not explicitly shown in  FIG. 2A , on a bottom surface thereof. Second high-side power switch  206   a  includes power terminal  238   b  (e.g., a source terminal) and control terminal  240   b  (e.g., a gate terminal) on a top surface thereof, and another power terminal (e.g., a drain terminal), not explicitly shown in  FIG. 2A , on a bottom surface thereof. Third high-side power switch  208   a  includes power terminal  238   c  (e.g., a source terminal) and control terminal  240   c  (e.g., a gate terminal) on a top surface thereof, and another power terminal (e.g., a drain terminal), not explicitly shown in  FIG. 2A , on a bottom surface thereof. 
     First low-side power switch  204   b  includes power terminal  238   d  (e.g., a source terminal) and control terminal  240   d  (e.g., a gate terminal) on a top surface thereof, and another power terminal (e.g., a drain terminal), not explicitly shown in  FIG. 2A , on a bottom surface thereof. Second low-side power switch  206   b  includes power terminal  238   e  (e.g., a source terminal) and control terminal  240   e  (e.g., a gate terminal) on a top surface thereof, and another power terminal (e.g., a drain terminal), not explicitly shown in  FIG. 2A , on a bottom surface thereof. Third low-side power switch  208   b  includes power terminal  238   f  (e.g., a source terminal) and control terminal  240   f  (e.g., a gate terminal) on a top surface thereof, and another power terminal (e.g., a drain terminal), not explicitly shown in  FIG. 2A , on a bottom surface thereof. 
     In the present implementation, driver IC  202  can be a high voltage IC (HVIC) for driving a high voltage (HV) multi-phase inverter, where the HV multi-phase inverter includes a U-phase having first high-side power switch  204   a  and first low-side power switch  204   b , a V-phase having second high-side power switch  206   a  and second low-side power switch  206   b , and a W-phase having third high-side power switch  208   a  and third low-side power switch  208   b . Driver IC  202  is configured to provide drive signals to the respective gates of U-phase power switches  204 , V-phase power switches  206 , and W-phase power switches  208 , for example. 
     As illustrated in  FIG. 2A , each of continuous conductive structures  210 ,  212 ,  214 ,  216 ,  218 ,  220 ,  222  and  224  includes a leadframe island and a pair of leads coupled to the leadframe island on opposing sides thereof. For example, first high-side continuous conductive structure  210  of leadframe  230  includes leadframe island  210   a  and leads  210   b  and  210   c  extending from opposing sides of leadframe island  210   a  to form a continuous conductive path for at least one of first high-side power switch  204   a , second high-side power switch  206   a  and third high-side power switch  208   a . First low-side continuous conductive structure  214  of leadframe  230  includes leadframe island  214   a  and leads  214   b  and  214   c  extending from opposing sides of leadframe island  214   a  to form a continuous conductive path for first low-side power switch  204   b . Second low-side continuous conductive structure  216  of leadframe  230  includes leadframe island  216   a  and leads  216   b  and  216   c  extending from opposing sides of leadframe island  216   a  to form a continuous conductive path for second low-side power switch  206   b . Third low-side continuous conductive structure  212  of leadframe  230  includes leadframe island  212   a  and leads  212   b  and  212   c  extending from opposing sides of leadframe island  212   a  to form a continuous conductive path for third low-side power switch  208   b . Driver IC continuous conductive structure  218  of leadframe  230  includes leadframe island  218   a  and leads  218   b  and  218   c  extending from opposing sides of leadframe island  218   a  to form a continuous conductive path for driver IC  202 . In addition, continuous conductive structure  220  includes leadframe island  220   a  and leads  220   b  and  220   c  extending from opposing sides of leadframe island  220   a . Continuous conductive structure  222  includes leadframe island  222   a  and leads  222   b  and  222   c  extending from opposing sides of leadframe island  222   a . Continuous conductive structure  224  includes leadframe island  224   a  and leads  224   b  and  224   c  extending from opposing sides of leadframe island  224   a . In one implementation, first high-side continuous conductive structure  210 , first low-side continuous conductive structure  214 , second low-side continuous conductive structure  216 , third low-side continuous conductive structure  212 , driver IC continuous conductive structure  218 , and continuous conductive structures  220 ,  222  and  224  of leadframe  230  each include conductive material, such as copper or copper alloy. 
     First high-side power switch  204   a , second high-side power switch  206   a , and third high-side power switch  208   a  are electrically and mechanically connected to leadframe island  210   a  of first high-side continuous conductive structure  210  by, for example, utilizing solder or conductive adhesive. First low-side power switch  204   b  is electrically and mechanically connected to leadframe island  214   a  of first low-side continuous conductive structure  214  by, for example, utilizing solder or conductive adhesive. Second low-side power switch  206   b  is electrically and mechanically connected to leadframe island  216   a  of second low-side continuous conductive structure  216  by, for example, utilizing solder or conductive adhesive. Third low-side power switch  208   b  is electrically and mechanically connected to leadframe island  212   a  of third low-side continuous conductive structure  212  by, for example, utilizing solder or conductive adhesive. 
     In the present implementation, first high-side power switch  204   a , second high-side power switch  206   a , and third high-side power switch  208   a  are situated on leadframe island  210   a  of first high-side continuous conductive structure  210 . In another implementation, first high-side power switch  204   a , second high-side power switch  206   a , and third high-side power switch  208   a  can be situated on separate continuous conductive structures (e.g., a first high-side continuous conductive structure, a second high-side continuous conductive structure and a third high-side continuous conductive structure) of leadframe  230 . 
     Because first high-side continuous conductive structure  210 , first low-side continuous conductive structure  214 , second low-side continuous conductive structure  216 , third low-side continuous conductive structure  212 , driver IC continuous conductive structure  218 , and continuous conductive structures  220 ,  222  and  224  each have a leadframe island and two leads extending from opposing sides of the leadframe island, electrically connections can be made on both sides of leadframe  230  for at least one terminal of each power switch and driver IC. For example, leads  210   b  and  210   c  of first high-side continuous conductive structure  210  can be coupled to a bus voltage, VBUS, to supply a bus voltage to the respective drains of first high-side power switch  204   a , second high-side power switch  206   a , and third high-side power switch  208   a . Leads  214   b  and  214   c  of first low-side continuous conductive structure  214  can be coupled to a switched node between first high-side power switch  204   a  and first low-side power switch  204   b . Leads  216   b  and  216   c  of second low-side continuous conductive structure  216  can be coupled to a switched node between second high-side power switch  206   a  and second low-side power switch  206   b . Leads  212   b  and  212   c  of third low-side continuous conductive structure  212  can be coupled to a switched node between third high-side power switch  208   a  and third low-side power switch  208   b . Leads  218   b  and  218   c  of driver IC continuous conductive structure  218  can be coupled to an input, INPUT, for driver IC  202 . Leads  220   b  and  220   c  of continuous conductive structure  220 , leads  222   b  and  222   c , of continuous conductive structure  222 , and leads  224   b  and  224   c  of continuous conductive structure  224  can be respectively coupled to corresponding source terminals of third high-side power switch  208   b , first low-side power switch  204   b , and second low-side power switch  206   b.    
     The construction of first high-side continuous conductive structure  210  allows at least one of high-side power switches  204   a ,  206   a  and  208   a  to continue to function even when one of leads  210   b  and  210   c  is removed (e.g., trimmed) from first high-side continuous conductive structure  210 . Similar, continuous conductive structures  212 ,  214 ,  216  and  218  allow low-side power switches  208   b ,  204   b  and  206   b  and driver IC  202 , respectively, to continue to function even when one of their respective leads is removed (e.g., trimmed). As will be discussed in detail below with reference to  FIGS. 2C and 2D , leadframe  230  can allow an easy conversion from a DIP to a SIP package. 
     Referring to  FIG. 2B , structure  282  illustrates a top plan view of a portion of a semiconductor package processed in accordance with an intermediate processing action according to one implementation of the present application. For example, the intermediate processing action includes coupling the first high-side power switch to the first low-side power switch. 
     As illustrated in  FIG. 2B , structure  282  includes first high-side power switch  204   a , second high-side power switch  206   a  and third high-side power switch  208   a  situated on first high-side continuous conductive structure  210  of leadframe  230 , first low-side power switch  204   b  situated on first low-side continuous conductive structure  214  of leadframe  230 , second low-side power switch  206   b  situated on second low-side continuous conductive structure  216  of leadframe  230 , and third low-side power switch  208   b  situated on third low-side continuous conductive structure  212  of leadframe  230 . Structure  282  also includes driver IC  202  situated on driver IC continuous conductive structure  218  of leadframe  230 . 
     As illustrated in  FIG. 2B , driver IC  202  is coupled to leadframe island  218   a  of driver IC continuous conductive structure  218  for receiving an input signal, for example. Driver IC  202  is also coupled to control terminals  240   a ,  240   b ,  240   c ,  240   d ,  240   e  and  240   f  of respective first high-side power switch  204   a , second high-side power switch  206   a , third high-side power switch  208   a , first low-side power switch  204   b , second low-side power switch  206   b  and third low-side power switch  208   b , though bond wires  244   a ,  244   b ,  244   c ,  244   d ,  244   e  and  244   f , respectively. 
     As illustrated in  FIG. 2B , power terminal  238   a  (e.g., a source terminal) of first high-side power switch  204   a  is electrically coupled to lead  214   b  of first low-side continuous conductive structure  214  through bond wire  246   a , where lead  214   b  is electrically and mechanically coupled to a power terminal (e.g., a drain terminal) of first low-side power switch  204   b . As a result, first high-side power switch  204   a  and first low-side power switch  204   b  are connected in a half-bridge configuration, and form one phase, (e.g., a U phase) of a multi-phase inverter. As illustrated in  FIG. 2B , power terminal  238   b  (e.g., a source terminal) of second high-side power switch  206   a  is electrically coupled to lead  216   b  of second low-side continuous conductive structure  216  through bond wire  246   b , where lead  216   b  is electrically and mechanically coupled to a power terminal (e.g., a drain terminal) of second low-side power switch  206   b . As a result, second high-side power switch  206   a  and second low-side power switch  206   b  are connected in a half-bridge configuration, and form one phase, (e.g., a V phase) of the multi-phase inverter. As illustrated in  FIG. 2B , power terminal  238   c  (e.g., a source terminal) of third high-side power switch  208   a  is electrically coupled to leadframe island  212   a  of third low-side continuous conductive structure  212  through bond wire  246   c , where leadframe island  212   a  is electrically and mechanically coupled to a power terminal (e.g., a drain terminal) of third low-side power switch  208   b . As a result, third high-side power switch  208   a  and third low-side power switch  208   b  are connected in a half-bridge configuration, and form one phase, (e.g., a W phase) of the multi-phase inverter. 
     As illustrated in  FIG. 2B , power terminal  238   d  (e.g., a source terminal) of first low-side power switch  204   b  is electrically coupled to leadframe island  222   a  of continuous conductive structure  222  through bond wire  246   e . Power terminal  238   e  (e.g., a source terminal) of second low-side power switch  206   b  is electrically coupled to leadframe island  224   a  of continuous conductive structure  224  through bond wire  246   f . Power terminal  238   f  (e.g., a source terminal) of third low-side power switch  208   b  is electrically coupled to leadframe island  220   a  of continuous conductive structure  220  through bond wire  246   d.    
     In the present implementation, bond wires  244   a - 244   f ,  246   a - 246   f  and  252  can include conductive material, such as aluminum, gold or copper. Bond wires  244   a - 244   f  and  252  may each have a diameter in a range between 1.3-2 mils (i.e., 10 −3  inches). Bond wires  246   a - 246   f  may each have a diameter in a range between 2-20 mils (i.e., 10 −3  inches). In another implementation, bond wires  244   a - 244   f ,  246   a - 246   f  and  252  can take forms of conductive ribbons for enhanced current carrying capacity. 
     Referring to  FIG. 2C , structure  284  illustrates a top plan view of a portion of a semiconductor package processed in accordance with an intermediate processing action according to one implementation of the present application. For example, the intermediate processing action covering the first high-side power switch and the first low-side power switch with an encapsulant. In the present implementation, structure  284  is a dual-in-line semiconductor package, such as a molded dual-in-line leadframe package with leads protruding from two opposing sides of structure  284 . As can be seen in  FIG. 2C , in structure  284 , each of continuous conductive structures  210 ,  212 ,  214 ,  216 ,  218 ,  220 ,  222  and  224  traverses the entire width of the semiconductor package, and has leads protruding from opposing sides of the semiconductor package for electrical connection. Thus, the dual-in-line semiconductor package offers access to various input and outputs on two sides of structure  284 . 
     As illustrated in  FIG. 2C , structure  284  includes encapsulant  250  covering first high-side power switch  204   a , second high-side power switch  206   a , third high-side power switch  208   a , first low-side power switch  204   b , second low-side power switch  206   b  and third low-side power switch  208   b . Encapsulant  250  covers leadframe islands  210   a ,  212   a ,  214   a ,  216   a ,  218   a ,  220   a ,  222   a  and  224   a  of leadframe  230 . Encapsulant  250  also covers portions of leads  210   b ,  212   b ,  214   b ,  216   b ,  218   b ,  220   b ,  222   b  and  224   b  on one side of leadframe  230 , and portions of leads  210   c ,  212   c ,  214   c ,  216   c ,  218   c ,  220   c ,  222   c  and  224   c  on another side of leadframe  230 . In addition, encapsulant  250  also covers bond wires  244   a - 244   f ,  246   a - 246   f  and  252 . In the present implementation, encapsulant  250  includes a mold compound, such as a plastic with a low flexural modulus. In one implementation, encapsulant  250  may include a high thermal conductive mold compound to achieve high voltage isolation. It should be noted that, during the molding process, leadframe  230  is suspended from both sides of structure  284 . Having leads suspended on both sides can improve the stability of leadframe  230  during the molding process, thereby allowing better control of the thickness of encapsulant  250 . 
     Referring to  FIG. 2D , structure  286  illustrates a top plan view of a portion of a semiconductor package processed in accordance with a final processing action according to one implementation of the present application. For example, the final processing action includes removing one or more leads protruding from one side of the semiconductor package. 
     As illustrated in  FIG. 2D , portions of leads  210   c ,  212   c ,  214   c ,  216   c ,  218   c ,  220   c ,  222   c  and  224   c  protruding from one side of encapsulated leadframe  230  in  FIG. 2C  are removed by, for example, trimming or cutting. As illustrated in  FIG. 2D , after trimming, structure  286  is converted from the dual-in-line semiconductor package shown in  FIG. 2C  to a single-in-line semiconductor package, such as a molded single-in-line leadframe package, with leads protruding only from one side of structure  286 . As can be seen in  FIG. 2D , in structure  286 , after trimming the portions of leads  210   c ,  212   c ,  214   c ,  216   c ,  218   c ,  220   c ,  222   c  and  224   c  protruding from encapsulant  250 , the remaining portions of leads  210   c ,  212   c ,  214   c ,  216   c ,  218   c ,  220   c ,  222   c  and  224   c  covered by encapsulant  250  stay intact in structure  286 , which would not be present in conventional SIP packages. The reason why the remaining portions of leads  210   c ,  212   c ,  214   c ,  216   c ,  218   c ,  220   c ,  222   c  and  224   c  would not be present in conventional SIP packages is that conventional SIP packages only require leads protruding from one side the package. Thus, only one lead would extend from a conductive structure and protrude from one side of the conventional SIP package, and would not traverse the entire width of the conventional SIP package. By contrast, in the present implementation, with the presence of the remaining portions of leads  210   c ,  212   c ,  214   c ,  216   c ,  218   c ,  220   c ,  222   c  and  224   c , each of respective continuous conductive structures  210 ,  212 ,  214 ,  216 ,  218 ,  220 ,  222  and  224  traverses the entire width of the semiconductor package, and has leads protruding from one side of the semiconductor package for electrical connection. Also, because continuous conductive structures  210 ,  212 ,  214 ,  216 ,  218 ,  220 ,  222  and  224  each have two leads electrically coupled to and extending from a leadframe island to form a continuous electrical path for their corresponding semiconductor devices, after trimming the leads on one side of the semiconductor package, the semiconductor devices can continue to function by replying on the remaining leads on the opposite side of the semiconductor package for electrical connection. As illustrated in  FIG. 2D , after trimming, each of continuous conductive structures  210 ,  212 ,  214 ,  216 ,  218 ,  220 ,  222  and  224  traverses the entire width of the semiconductor package, and has respective leads  210   b ,  212   b ,  214   b ,  216   b ,  218   b ,  220   b ,  222   b  and  224   b  protruding from one side of the semiconductor package for electrical connection. Among other advantages, continuous conductive structures  210 ,  212 ,  214 ,  216 ,  218 ,  220 ,  222  and  224 , each having leads extending from two opposite sides of a leadframe island, allow for an easy conversion from a dual-in-line semiconductor package to a single-in-line semiconductor package without reconfiguring the internal structure (e.g., arrangements of the semiconductor components or related electrical routing paths) of the leadframe package, thereby substantially reduce manufacturing time, cost and complexity. It is noted that the remaining portions of leads  210   c ,  212   c ,  214   c ,  216   c ,  218   c ,  220   c ,  222   c  and  224   c  in  FIG. 2D  are left exposed without electrical insulation. 
     Although  FIG. 2D  shows trimming of portions of leads  210   c ,  212   c ,  214   c ,  216   c ,  218   c ,  220   c ,  222   c  and  224   c  protruding from one side of encapsulated leadframe  230 , it should be understood that, in another implementation, the trimming can be performed on the opposite side of structure  286  (e.g., by removing portions of leads  210   b ,  212   b ,  214   b ,  216   b ,  218   b ,  220   b ,  222   b  and  224   b  protruding from encapsulated leadframe  230 ), and still allows structure  286  to function as a SIP package by relying on untrimmed leads  210   c ,  212   c ,  214   c ,  216   c ,  218   c ,  220   c ,  222   c  and  224   c  for electrical connection. 
     Referring to  FIG. 2E , structure  288  illustrates a top plan view of a portion of a semiconductor package processed in accordance with an optional processing action according to one implementation of the present application. For example, the optional processing action includes electrically insulating the one or more leads on the one side of the semiconductor package. 
     As illustrated in  FIG. 2E , the exposed portions of leads  210   c ,  212   c ,  214   c ,  216   c ,  218   c ,  220   c ,  222   c  and  224   c  on one side of molded leadframe  230  are electrically insulated by insulation caps  248   a ,  248   b ,  248   c ,  248   d ,  248   e ,  248   f ,  248   g  and  248   h , respectively. In one implementation, insulation caps  248   a ,  248   b ,  248   c ,  248   d ,  248   e ,  248   f ,  248   g  and  248   h  can include insulating material, such as dispensed epoxy, powder coating, or dielectric coating. As such, electrical connections can be made only through leads  210   b ,  212   b ,  214   b ,  216   b ,  218   b ,  220   b ,  222   b  and  224   b  on the opposing side of the semiconductor package. 
     Referring to  FIGS. 3A, 3B, 3C and 3D , each of  FIGS. 3A, 3B, 3C and 3D  illustrates a cross sectional view of a portion of a dual-in-line semiconductor package according to one implementation of the present application. For example, the cross sectional view in each of  FIGS. 3A, 3B, 3C and 3D  may correspond to the cross section of structure  182  along line  3 - 3  in  FIG. 1B  according to one implementation of the present application. In  FIGS. 3A, 3B, 3C and 3D , semiconductor device  304   a , continuous conductive structure  310  and continuous conductive structure  314  may correspond to semiconductor device  104   a , continuous conductive structure  110  of leadframe  130 , and continuous conductive structure  114  of leadframe  130 , respectively, in  FIG. 1B . 
     As illustrated in  FIGS. 3A, 3B, 3C and 3D , respective dual-in-line semiconductor packages  382 A,  382 B,  382 C and  382 D each include semiconductor device  304   a  situated on leadframe island  310   a  of continuous conductive structure  310 , and coupled to lead  314   b  of continuous conductive structure  314  through a bond wire. Semiconductor device  304   a  includes terminal  338   a  on a top surface thereof, and terminal  342   a  on a bottom surface thereof. Terminal  338   a  of semiconductor device  304   a  is electrically connected to lead  314   b  of continuous conductive structure  314  through a bond wire. Terminal  342   a  of semiconductor device  304   a  is electrically and mechanically connected to leadframe island  310   a  of continuous conductive structure  310  by, for example, utilizing solder or conductive adhesive. Encapsulant  350  covers semiconductor device  304   a , leadframe island  310   a  of continuous conductive structure  310 , and portions of leads  310   c  and  314   b , while the remaining portions of leads  310   c  and  314   b  protrude from opposing sides of the dual-in-line semiconductor package. 
     As illustrated in  FIG. 3A , each of continuous conductive structure  310  and continuous conductive structure  314  has a substantially uniform thickness throughout an entire length thereof. In one implementation, continuous conductive structure  310  and continuous conductive structure  314  may each have a substantially uniform thickness in a range between 0.2 to 2 mm (i.e., 10 −3  meters). 
     As illustrated in  FIG. 3B , lead  314   b  of continuous conductive structure  314  includes a down-set portion which is configured to reduce the thermal resistance of dual-in-line semiconductor packages  382 B, due to the reduced distance (e.g., 0.3 to 1 mm) between the bottom surface of the down-set portion of lead  314   b  and the bottom surface of encapsulant  350 . 
     As illustrated in  FIG. 3C , lead  314   b  of continuous conductive structure  314  includes a dual gauge portion, where a portion of lead  314   b  retains the full thickness of continuous conductive structure  314 , while the remaining portions of lead  314   b  retain a fraction (e.g., half-etched or quarter-etched) of the full thickness of continuous conductive structure  314  of the leadframe. The full thickness portion of lead  314   b  can reduce the thermal resistance, thereby improving the thermal performance, of dual-in-line semiconductor packages  382 C, due to the reduced distance between the bottom surface of the full thickness portion of lead  314   b  and the bottom surface of encapsulant  350 . 
     As illustrated in  FIG. 3D , lead  314   b  of continuous conductive structure  314  includes a dual gauge portion, where a portion of lead  314   b  retains the full thickness of continuous conductive structure  314 , while the remaining portions of lead  314   b  retain a fraction (e.g., half-etched or quarter-etched) of the full thickness of continuous conductive structure  314  of the leadframe. The full thickness portion of lead  314   b  can reduce the thermal resistance, thereby improving the thermal performance, of dual-in-line semiconductor packages  382 D, due to the reduced distance between the bottom surface of the full thickness portion of lead  314   b  and the bottom surface of encapsulant  350 . Also, as illustrated in  FIG. 3D , lead  314   b  of continuous conductive structure  314  includes a down-set portion, which can further reduce the thermal resistance of dual-in-line semiconductor packages  382 D, due to the further reduced distance between the bottom surface of the down-set portion of lead  314   b  and the bottom surface of encapsulant  350 . Although only continuous conductive structure  314  is shown to have a down-set portion and/or a dual gauge portion in  FIGS. 3B-3D , it should be understood that each of continuous conductive structures  110 ,  112 ,  114 ,  116 ,  120 ,  122  and  124  of leadframe  130  in  FIG. 1B  may have a down-set portion and/or a dual gauge portion. 
     In another implementation, leadframe island  310   a  of continuous conductive structure  310  in  FIGS. 3A-3D , on which semiconductor device  304   a  is situated, may also have a down-set portion and/or a dual gauge portion to improve thermal performance of semiconductor device  304   a . Similarly, each of leadframe islands  112   a ,  114   a  and  116   a  of respective continuous conductive structures  112 ,  114  and  116  in  FIG. 1B  may also have a down-set portion and/or a dual gauge portion to improve thermal performance of respective semiconductor devices  108   b ,  104   b  and  106   b  situated thereon. 
     Referring to  FIGS. 4A, 4B, 4C and 4D , each of  FIGS. 4A, 4B, 4C and 4D  illustrates a cross sectional view of a portion of a single-in-line semiconductor package according to one implementation of the present application. For example, the cross sectional view in each of  FIGS. 4A, 4B, 4C and 4D  may correspond to the cross section of structure  184  along line  4 - 4  in  FIG. 1C  according to one implementation of the present application. In  FIGS. 4A, 4B, 4C and 4D , semiconductor device  404   a , continuous conductive structure  410  and continuous conductive structure  414  may correspond to semiconductor device  104   a , continuous conductive structure  110  of leadframe  130 , and continuous conductive structure  114  of leadframe  130 , respectively, in  FIG. 1C . 
     As illustrated in  FIGS. 4A, 4B, 4C and 4D , respective single-in-line semiconductor packages  484 A,  484 B,  484 C and  484 D each include semiconductor device  404   a  situated on leadframe island  410   a  of continuous conductive structure  410 , and coupled to lead  414   b  of continuous conductive structure  414  through a bond wire. Semiconductor device  404   a  includes terminal  438   a  on a top surface thereof, and terminal  442   a  on a bottom surface thereof. Terminal  438   a  of semiconductor device  404   a  is electrically connected to lead  414   b  of continuous conductive structure  414  through a bond wire. Terminal  442   a  of semiconductor device  404   a  is electrically and mechanically connected to leadframe island  410   a  of continuous conductive structure  410  by, for example, utilizing solder or conductive adhesive. Encapsulant  450  covers semiconductor device  404   a , leadframe island  410   a  of continuous conductive structure  410 , and portions of leads  410   c  and  414   b , while the remaining portion of lead  414   b  protrudes from one side of the single-in-line semiconductor package. It is noted that a portion of lead  410   c  of continuous conductive structure  410  is removed from the single-in-line semiconductor package, and electrically insulated by optional insulation cap  448   a.    
     As illustrated in  FIG. 4A , each of continuous conductive structure  410  and continuous conductive structure  414  has a substantially uniform thickness throughout an entire length thereof. In one implementation, continuous conductive structures  410  and  414  may each have a substantially uniform thickness in a range between 0.2 to 2 mm (i.e., 10 −3  meters). 
     As illustrated in  FIG. 4B , lead  414   b  of continuous conductive structure  414  includes a down-set portion which is configured to reduce the thermal resistance of single-in-line semiconductor package  484 B, due to the reduced distance (e.g., 0.3 to 1 mm) between the bottom surface of the down-set portion of lead  414   b  and the bottom surface of encapsulant  450 . 
     As illustrated in  FIG. 4C , lead  414   b  of continuous conductive structure  414  includes a dual gauge portion, where a portion of lead  414   b  retains the full thickness of continuous conductive structure  414 , while the remaining portions of lead  414   b  retain a fraction (e.g., half-etched or quarter-etched) of the full thickness of continuous conductive structure  414  of the leadframe. The full thickness portion of lead  414   b  can reduce the thermal resistance, thereby improving the thermal performance, of dual-in-line semiconductor package  484 C, due to the reduced distance between the bottom surface of the full thickness portion of lead  414   b  and the bottom surface of encapsulant  450 . 
     As illustrated in  FIG. 4D , lead  414   b  of continuous conductive structure  414  includes a dual gauge portion, where a portion of lead  414   b  retains the full thickness of continuous conductive structure  414 , while the remaining portions of lead  414   b  retain a fraction (e.g., half-etched or quarter-etched) of the full thickness of continuous conductive structure  414  of the leadframe. The full thickness portion of lead  414   b  can reduce the thermal resistance, thereby improving the thermal performance, of single-in-line semiconductor package  484 D, due to the reduced distance between the bottom surface of the full thickness portion of lead  414   b  and the bottom surface of encapsulant  450 . Also, as illustrated in  FIG. 4D , lead  414   b  of continuous conductive structure  414  includes a down-set portion, which can further reduce the thermal resistance of single-in-line semiconductor package  484 D, due to the further reduced distance between the bottom surface of the down-set portion of lead  414   b  and the bottom surface of encapsulant  450 . Although only continuous conductive structure  414  is shown to have a down-set portion and/or a dual gauge portion in  FIGS. 4B-4D , it should be understood that each of continuous conductive structures  110 ,  112 ,  114 ,  116 ,  120 ,  122  and  124  of leadframe  130  in  FIG. 1C  may have a down-set portion and/or a dual gauge portion. 
     In another implementation, leadframe island  410   a  of continuous conductive structure  410  in  FIGS. 4A-4D , on which semiconductor device  404   a  is situated, may also have a down-set portion and/or a dual gauge portion to improve thermal performance of semiconductor device  404   a . Similarly, each of leadframe islands  112   a ,  114   a  and  116   a  of respective continuous conductive structures  112 ,  114  and  116  in  FIG. 1C  may also have a down-set portion and/or a dual gauge portion to improve thermal performance of respective semiconductor devices  108   b ,  104   b  and  106   b  situated thereon. 
     Referring to  FIGS. 5A, 5B, 5C and 5D , each of  FIGS. 5A, 5B, 5C and 5D  illustrates a cross sectional view of a portion of a dual-in-line semiconductor package according to one implementation of the present application. For example, the cross sectional view in each of  FIGS. 5A, 5B, 5C and 5D  may correspond to the cross section of structure  284  along line  5 - 5  in  FIG. 2C  according to one implementation of the present application. In  FIGS. 5A, 5B, 5C and 5D , first high-side power switch  504   a , first high-side continuous conductive structure  510 , driver IC  502  and driver IC continuous conductive structure  518  may correspond to first high-side power switch  204   a , first high-side continuous conductive structure  210  of leadframe  230 , driver IC  202  and driver IC continuous conductive structure  218  of leadframe  230 , respectively, in  FIG. 2C . 
     As illustrated in  FIGS. 5A, 5B, 5C and 5D , respective dual-in-line semiconductor packages  584 A,  584 B,  584 C and  584 D each include first high-side power switch  504   a  situated on leadframe island  510   a  of first high-side continuous conductive structure  510 , and driver IC  502  situated on leadframe island  518   a  of driver IC continuous conductive structure  518 . First high-side power switch  504   a  includes power terminal  538   a  (e.g., a source terminal) and control terminal  540   a  (e.g., a gate terminal) on a top surface thereof, and power terminal  542   a  (e.g., a drain terminal) on a bottom surface thereof. Control terminal  540   a  of first high-side power switch  504   a  is electrically connected to driver IC  502  through bond wire  544   a . Power terminal  542   a  of first high-side power switch  504   a  is electrically and mechanically connected to leadframe island  510   a  of first high-side continuous conductive structure  510  by, for example, utilizing solder or conductive adhesive. Although not explicitly shown in  FIG. 5A , power terminal  538   a  of first high-side power switch  504   a  is electrically connected to a power terminal (e.g., a drain terminal) of a first low-side power switch, such as first low-side power switch  204   b  through bond wire  246   a  and lead  214   b  as illustrated in  FIG. 2C . Encapsulant  550  covers first high-side power switch  504   a , driver IC  502 , leadframe island  510   a  of first high-side continuous conductive structure  510 , and leadframe island  518   a  of driver IC continuous conductive structure  518  of the leadframe. Encapsulant  550  also covers a portion of lead  510   c  of first high-side continuous conductive structure  510 , and a portion of lead  518   b  of driver IC continuous conductive structure  518  of the leadframe, while the remaining portions of lead  510   c  of first high-side continuous conductive structure  510  and lead  518   b  of driver IC continuous conductive structure  518  protrude from opposing sides of dual-in-line semiconductor package  584 A. 
     As illustrated in  FIG. 5A , each of first high-side continuous conductive structure  510  and driver IC continuous conductive structure  518  has a substantially uniform thickness throughout an entire length thereof. In one implementation, first high-side continuous conductive structure  510  and driver IC continuous conductive structure  518  may each have a substantially uniform thickness in a range between 0.2 to 2 mm (i.e., 10 −3  meters). 
     As illustrated in  FIG. 5B , driver IC continuous conductive structure  518  includes leadframe island  518   a  that is down set from lead  518   b  of driver IC continuous conductive structure  518 . The down-set portion under driver IC  502  can reduce the thermal resistance of dual-in-line semiconductor package  584 B, due to the reduced distance (e.g., 0.3 to 1 mm) between the bottom surface of the down-set portion of leadframe island  518   a  and the bottom surface of encapsulant  550 . 
     As illustrated in  FIG. 5C , leadframe island  518   a  of driver IC continuous conductive structure  518  includes a dual gauge portion, where a portion of leadframe island  518   a  directly under driver IC  502  retains the full thickness of driver IC continuous conductive structure  518  of the leadframe, while the remaining portions of leadframe island  518   a  retain a fraction (e.g., half-etched or quarter-etched) of the full thickness of driver IC continuous conductive structure  518  of the leadframe. The full thickness portion of driver IC continuous conductive structure  518  directly under driver IC  502  can reduce the thermal resistance, thereby improving the thermal performance, of dual-in-line semiconductor package  584 C, due to the reduced distance between the bottom surface of the full thickness portion of driver IC continuous conductive structure  518  and the bottom surface of encapsulant  550 . 
     As illustrated in  FIG. 5D , leadframe island  518   a  of driver IC continuous conductive structure  518  of the leadframe includes a dual gauge portion, where a portion of leadframe island  518   a  directly under driver IC  502  retains the full thickness of driver IC continuous conductive structure  518  of the leadframe, while the remaining portions of leadframe island  518   a  retain a fraction (e.g., half-etched or quarter-etched) of the full thickness of driver IC continuous conductive structure  518  of the leadframe. The full thickness portion of driver IC continuous conductive structure  518  directly under driver IC  502  can reduce the thermal resistance, thereby improving the thermal performance, of dual-in-line semiconductor package  584 D, due to the reduced distance between the bottom surface of the full thickness portion of driver IC continuous conductive structure  518  and the bottom surface of encapsulant  550 . Also, as illustrated in  FIG. 5D , leadframe island  518   a  of driver IC continuous conductive structure  518  is down set from lead  518   b  of driver IC continuous conductive structure  518 . The down-set portion under driver IC  502  can further reduce the thermal resistance of dual-in-line semiconductor package  584 D, due to the further reduced distance between the bottom surface of the down-set portion of leadframe island  518   a  and the bottom surface of encapsulant  550 . Although only driver IC continuous conductive structure  518  is shown to have a down-set portion and/or a dual gauge portion in  FIGS. 5B-5D , it should be understood that each of continuous conductive structures  210 ,  212 ,  214 ,  216 ,  218 ,  220 ,  222  and  224  of leadframe  230  in  FIG. 2C  may have a down-set portion and/or a dual gauge portion. 
     In another implementation, leadframe island  510   a  of first high-side continuous conductive structure  510  in  FIGS. 5A-5D , on which first high-side power switch  504   a  is situated, may also have a down-set portion and/or a dual gauge portion to improve thermal performance of first high-side power switch  504   a . Similarly, each of leadframe islands  212   a ,  214   a  and  216   a  of respective continuous conductive structures  212 ,  214  and  216  in  FIG. 2C  may also have a down-set portion and/or a dual gauge portion to improve thermal performance of respective low-side power switches  208   b ,  204   b  and  206   b  situated thereon. 
     Referring to  FIGS. 6A, 6B, 6C and 6D , each of  FIGS. 6A, 6B, 6C and 6D  illustrates a cross sectional view of a portion of a single-in-line semiconductor package according to one implementation of the present application. For example, the cross sectional view in each of  FIGS. 6A, 6B, 6C and 6D  may correspond to the cross section of structure  288  along line  6 - 6  in  FIG. 2E  according to one implementation of the present application. In  FIGS. 6A, 6B, 6C and 6D , first high-side power switch  604   a , first high-side continuous conductive structure  610 , driver IC  602  and driver IC continuous conductive structure  618  may correspond to first high-side power switch  204   a , first high-side continuous conductive structure  210  of leadframe  230 , driver IC  202  and driver IC continuous conductive structure  218  of leadframe  230 , respectively, in  FIG. 2E . 
     As illustrated in  FIGS. 6A, 6B, 6C and 6D , respective single-in-line semiconductor packages  688 A,  688 B,  688 C and  688 D each include first high-side power switch  604   a  situated on leadframe island  610   a  of first high-side continuous conductive structure  610 ; and driver IC  602  situated on leadframe island  618   a  of driver IC continuous conductive structure  618 . First high-side power switch  604   a  includes power terminal  638   a  (e.g., a source terminal) and control terminal  640   a  (e.g., a gate terminal) on a top surface thereof, and power terminal  642   a  (e.g., a drain terminal) on a bottom surface thereof. Control terminal  640   a  of first high-side power switch  604   a  is electrically connected to driver IC  602  through bond wire  644   a . Power terminal  642   a  of first high-side power switch  604   a  is electrically and mechanically connected to leadframe island  610   a  of first high-side continuous conductive structure  610  by, for example, utilizing solder or conductive adhesive. Although not explicitly shown in  FIG. 6A , power terminal  638   a  of first high-side power switch  604   a  is electrically mechanically connected to a control terminal (e.g., a drain terminal) of a first low-side power switch, such as first low-side power switch  204   b  through bond wire  246   a  and lead  214   b  as illustrated in  FIG. 2E . Encapsulant  650  covers first high-side power switch  604   a , driver IC  602 , and leadframe island  610   a  of first high-side continuous conductive structure  610 , leadframe island  618   a  of driver IC continuous conductive structure  618 . Encapsulant  650  also covers portions of leads  610   c  and  618   b , while the remaining portion of lead  618   b  protrudes from one side of the single-in-line semiconductor package. It is noted that a portion of lead  610   c  is removed from the single-in-line semiconductor package, and electrically insulated by optional insulation cap  648   a.    
     As illustrated in  FIG. 6A , each of first high-side continuous conductive structure  610  and driver IC continuous conductive structure  618  has a substantially uniform thickness throughout an entire length thereof. In one implementation, first high-side continuous conductive structure  610  and driver IC continuous conductive structure  618  may each have a substantially uniform thickness in a range between 0.2 to 2 mm (i.e., 10 −3  meters). 
     As illustrated in  FIG. 6B , driver IC continuous conductive structure  618  includes leadframe island  618   a  that is down set from lead  618   b  of driver IC continuous conductive structure  618 . The down-set portion under driver IC  602  can reduce the thermal resistance of single-in-line semiconductor package  688 B, due to the reduced distance between the bottom surface of the down-set portion of leadframe island  618   a  and the bottom surface of encapsulant  650 . 
     As illustrated in  FIG. 6C , leadframe island  618   a  of driver IC continuous conductive structure  618  includes a dual gauge portion, where a portion of leadframe island  618   a  directly under driver IC  602  retains the full thickness of driver IC continuous conductive structure  618  of the leadframe, while the remaining portions of leadframe island  618   a  retain a fraction (e.g., half-etched or quarter-etched) of the full thickness of driver IC continuous conductive structure  618  of the leadframe. The full thickness portion of driver IC continuous conductive structure  618  directly under driver IC  602  can reduce the thermal resistance, thereby improving the thermal performance, of single-in-line semiconductor package  688 C, due to the reduced distance between the bottom surface of the full thickness portion of driver IC continuous conductive structure  618  and the bottom surface of encapsulant  650 . 
     As illustrated in  FIG. 6D , leadframe island  618   a  of driver IC continuous conductive structure  618  of the leadframe includes a dual gauge portion, where a portion of leadframe island  618   a  directly under driver IC  602  retains the full thickness of driver IC continuous conductive structure  618  of the leadframe, while the remaining portions of leadframe island  618   a  retain a fraction (e.g., half-etched or quarter-etched) of the full thickness of driver IC continuous conductive structure  618  of the leadframe. The full thickness portion of driver IC continuous conductive structure  618  directly under driver IC  602  can reduce the thermal resistance of single-in-line semiconductor package  688 D due to the reduced distance between the bottom surface of the full thickness portion of driver IC continuous conductive structure  618  and the bottom surface of encapsulant  650 . Also, as illustrated in  FIG. 6D , leadframe island  618   a  of driver IC continuous conductive structure  618  is down set from lead  618   b  of driver IC continuous conductive structure  618 . The down-set portion under driver IC  602  can further reduce the thermal resistance of single-in-line semiconductor package  688 D, due to the further reduced distance between the bottom surface of the down-set portion of leadframe island  618   a  and the bottom surface of encapsulant  650 . Although only driver IC continuous conductive structure  618  is shown to have a down-set portion and/or a dual gauge portion in  FIGS. 6B-6D , it should be understood that each of continuous conductive structures  210 ,  212 ,  214 ,  216 ,  218 ,  220 ,  222  and  224  of leadframe  230  in  FIG. 2E  may have a down-set portion and/or a dual gauge portion. 
     In another implementation, leadframe island  610   a  of first high-side continuous conductive structure  610  in  FIGS. 6A-6D , on which first high-side power switch  604   a  is situated, may also have a down-set portion and/or a dual gauge portion to improve thermal performance of first high-side power switch  604   a . Similarly, each of leadframe islands  212   a ,  214   a  and  216   a  of respective continuous conductive structures  212 ,  214  and  216  in  FIG. 2E  may also have a down-set portion and/or a dual gauge portion to improve thermal performance of respective low-side power switches  208   b ,  204   b  and  206   b  situated thereon. 
     Referring to  FIG. 7 ,  FIG. 7  illustrates a schematic diagram of an exemplary multi-phase inverter circuit of a semiconductor package. In  FIG. 7 , with similar numerals representing similar features in  FIGS. 2A-2E , semiconductor package  700  includes driver integrated circuit (IC)  702  and multi-phase inverter  760 . Multi-phase inverter  760  includes a U-phase having first high-side power switch  704   a  and first low-side power switch  704   b , a V-phase having second high-side power switch  706   a  and second low-side power switch  706   b , and a W-phase having third high-side power switch  708   a  and third low-side power switch  708   b.    
     In the U-phase of multi-phase inverter  760 , first high-side power switch  704   a  and first low-side power switch  704   b  are connected in a half-bridge configuration. As illustrated in  FIG. 7 , the drain of first high-side power switch  704   a  is electrically coupled to a bus voltage, VBUS, at terminal  710 . The source of first high-side power switch  704   a  is electrically coupled to the drain of first low-side power switch  704   b  at switched node  714 . The source of first low-side power switch  704   b  is electrically coupled to terminal  722 . Driver IC  702  provides first high-side gate signal H 1  to the gate of first high-side power switch  704   a , and first low-side gate signal L 1  to the gate of first low-side power switch  704   b.    
     In the V-phase of multi-phase inverter  760 , second high-side power switch  706   a  and second low-side power switch  706   b  are connected in a half-bridge configuration. As illustrated in  FIG. 7 , the drain of second high-side power switch  706   a  is electrically coupled to the bus voltage, VBUS, at terminal  710 . The source of second high-side power switch  706   a  is electrically coupled to the drain of second low-side power switch  706   b  at switched node  716 . The source of second low-side power switch  706   b  is electrically coupled to terminal  724 . Driver IC  702  provides second high-side gate signal H 2  to the gate of second high-side power switch  706   a , and second low-side gate signal L 2  to the gate of second low-side power switch  706   b.    
     In the W-phase of multi-phase inverter  760 , third high-side power switch  708   a  and third low-side power switch  708   b  are connected in a half-bridge configuration. As illustrated in  FIG. 7 , the drain of third high-side power switch  708   a  is electrically coupled to the bus voltage, VBUS, at terminal  710 . The source of third high-side power switch  708   a  is electrically coupled to the drain of third low-side power switch  708   b  at switched node  712 . The source of third low-side power switch  708   b  is electrically coupled to terminal  720 . Driver IC  702  provides third high-side gate signal H 3  to the gate of third high-side power switch  708   a , and third low-side gate signal L 3  to the gate of third low-side power switch  708   b.    
     Driver IC  702  may include various circuit components, such as input logics, level shifters, overvoltage and undervoltage protection circuits, comparators, latches, high-side drivers, low-side drivers, capacitors, and bootstrap diodes, not explicitly shown in  FIG. 7 . Driver IC  702  is configured to receive one or more input signals, INPUT, from one or more input terminals  718 , and provide gate signals to the power switches in multi-phase inverter  760 , as described above. 
     It should be understood that although a semiconductor package having a multi-phase inverter and a driver IC has be shown as an implementation of the present application, other implementations of the present application may include a semiconductor package with a single phase inverter and with or without a driver IC. 
     Implementations of the present application offer multiple packaging options to customer with a highly adaptable leadframe (e.g., leadframe  130  in  FIGS. 1A-1C  and leadframe  230  in  FIGS. 2A-2E ) that can provide can be converted to multiple final package platforms, such as SIPs, DIPs and surface mount device (SMD) packages. The conversion process from one package platform to another can be done without reconfiguring the internal structure (e.g., arrangements of the semiconductor components or related electrical routing paths) of the leadframe package, thereby substantially reducing tooling costs as well as reducing production equipment conversion time. Moreover, implementations of the present application improve production line efficiency by avoiding multiple process set-up changes during production. 
     From the above description it is manifest that various techniques can be used for implementing the concepts described in the present application without departing from the scope of those concepts. Moreover, while the concepts have been described with specific reference to certain implementations, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the scope of those concepts. As such, the described implementations are to be considered in all respects as illustrative and not restrictive. It should also be understood that the present application is not limited to the particular implementations described herein, but many rearrangements, modifications, and substitutions are possible without departing from the scope of the present disclosure.