Patent Publication Number: US-9843285-B1

Title: Digital demodulator for pulse-width modulated (PWM) signals in a motor controller

Description:
BACKGROUND 
     Pulse-width modulated (PWM) signals are commonly used to control the current and/or voltage supplied to and, thus, the speed of, electric motors, such as brushless direct-current (BLDC) motors. Demodulating and digitizing PWM signals can be difficult, requiring complex and costly components (such as a digital signal processor (DSP) and/or analog-to-digital converter (ADC)), and/or components that may be physically large and difficult to implement in an integrated circuit (IC). Further, some PWM demodulation techniques may encounter difficulty generating a demodulated signal when the PWM signal has a duty cycle of 0% and/or 100%. Yet other solutions may require generating a local reference frequency to control a feedback network to demodulate the PWM signal. Further, in motor control systems, PWM control signals may be particularly noisy (e.g., have spurious signal spikes that could be, erroneously, included in a demodulated signal). Therefore, an improved technique for digital demodulation of PWM signals in a motor control system is needed. 
     SUMMARY 
     This Summary is provided to introduce a selection of concepts in a simplified form that are further described in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. 
     One aspect provides an electronic circuit for digitally demodulating a pulse-width modulated (PWM) signal in a motor control system. The electronic circuit includes an input to receive a speed demand signal that is a PWM signal having a duty cycle associated with a requested speed of a motor. A PWM demodulator demodulates the PWM signal and generates an N-bit digital speed value representative of the requested speed of the motor, where N is a positive integer. A motor driver generates, based at least in part upon the N-bit digital speed value, one or more control signals to operate the motor. 
     Another aspect provides a pulse-width modulated (PWM) signal demodulator. The PWM signal demodulator includes a multiplexer to select between a first digital value and a second digital value to provide a selected digital output value. The selection is based upon a logic level of a received PWM signal. The PWM signal demodulator also includes a digital low-pass filter to filter the selected digital output value to generate an N-bit digital value associated with a duty cycle of the received PWM signal. The low-pass filter includes a first input to receive the selected digital output value, a second input to receive a digital feedback value, an output to provide the N-bit digital value, and a feedback path to provide an adjusted N-bit digital value as the digital feedback value. 
     Another aspect provides a method for digitally demodulating a pulse-width modulated (PWM) signal in a motor control system. The method includes receiving a speed demand signal that is a PWM signal having a duty cycle associated with a requested speed of a motor coupled to the electronic circuit. The PWM signal is demodulated and an N-bit digital speed value representative of the requested speed of the motor is generated. N is a positive integer. Based at least in part upon the N-bit digital speed value, one or more control signals to operate the motor are generated. The PWM signal is demodulated by selecting between a first digital value and a second digital value to provide a selected digital output value, the selection based upon a logic level of the PWM signal. The selected digital output value is filtered to generate the N-bit digital speed value. 
     Another aspect provides a method for demodulating a pulse-width modulated (PWM) signal. The method includes selecting between a first digital value and a second digital value and providing a selected digital output value. The selection is based upon a logic level of a received PWM signal. The selected digital output value is filtered and an N-bit digital value associated with a duty cycle of the received PWM signal is generated. The N-bit digital value is generated based, at least in part, upon the selected digital output value and a digital feedback value. The digital feedback value is generated for a current sample of the selected digital output value by: subtracting the digital feedback value from the current selected digital output value to generate a first intermediate value; subtracting the digital feedback value from a previous N-bit digital speed value to generate a second intermediate value; subtracting the previous N-bit digital speed value from the digital feedback value to generate a third intermediate value and accumulate the third intermediate value for a window of X samples; adding the first intermediate value and the second intermediate value and accumulating the sums for a window of X samples as an accumulated sum value; multiplying the accumulated third intermediate values by a gain factor to generate an intermediate gain value; adding the intermediate gain value and the accumulated sum value to generate an intermediate feedback value; dividing the intermediate feedback value by a time factor to generate the digital feedback value; and dividing the accumulated third intermediate values by a time factor to generate the N-bit digital speed value. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       Other aspects, features, and advantages of the claimed subject matter will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements. Reference numerals that are introduced in the specification in association with a drawing figure might be repeated in one or more subsequent figures without additional description in the specification in order to provide context for other features. 
         FIG. 1  is a schematic diagram showing a motor driver with a pulse-width modulated (PWM) signal demodulator in accordance with illustrative embodiments; 
         FIG. 2  is a block diagram of the PWM signal demodulator of the motor driver of  FIG. 1  in accordance with illustrative embodiments; 
         FIG. 3  is a block diagram of the filter of the PWM signal demodulator of  FIG. 2  in accordance with illustrative embodiments; 
         FIG. 4  is another block diagram of the filter of the PWM signal demodulator of  FIG. 2  in accordance with illustrative embodiments; 
         FIGS. 5A and 5B  are timing diagrams showing illustrative signals of the PWM demodulator of  FIG. 2  in accordance with illustrative embodiments; 
         FIG. 6  is a flow diagram showing an illustrative process for operating a motor in accordance with illustrative embodiments; 
         FIG. 7  is a flow diagram showing an illustrative process for demodulating a PWM signal in accordance with illustrative embodiments; and 
         FIG. 8  is a flow diagram showing an illustrative process for low-pass filtering a digital signal in accordance with illustrative embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Described embodiments provide circuits, systems and methods for providing digital demodulation of a pulse-width modulated (PWM) signal to provide digital control of a motor. 
     Referring to  FIG. 1 , a schematic of illustrative motor system  100  is shown. Motor system  100  includes motor driver  102  to control operation of multi-phase motor  114 . Although shown in  FIG. 1  as being a three-phase motor, in some embodiments, motor  114  could employ other numbers of phases, as would be understood by one of ordinary skill in the art. In some embodiments, motor driver  102  is an integrated circuit (IC). In some embodiments, motor  114  may be a brushless direct-current (BLDC) motor. 
     Motor driver  102  is coupled to receive external speed demand signal  103   a  from an external device coupled to motor driver  102 . In general, external speed demand signal  103   a  is indicative of a requested speed of motor  114 . In some embodiments, external speed demand signal  103   a  is a pulse-width modulated (PWM) signal, although in some embodiments, external speed demand signal  103   a  may be provided in one of a variety of other formats, for example, a Single Edge Nibble Transmission (SENT) format, a Serial Peripheral Interface (SPI) format, a Local Interconnect Network (LIN) format, a CAN (Controller Area Network) format, an Inter-Integrated Circuit (I2C) format, or other similar signal formats, and converted to a PWM signal for provision to speed demand generator  104 . 
     Speed demand generator  104  receives external speed demand signal  103   a  and generates speed demand signal  107   a . In some embodiments, speed demand signal  107   a  is determined not only by external speed demand signal  103   a , but also motor current requirements measured or calculated by signal processor  122 . Further, speed demand signal  107   a  may also be adjusted based upon properties of motor driver  102  and/or motor  114 , such as an over current limit (OCL). For example, to protect against over current conditions, speed demand signal  107   a  may be clamped to a maximum value that may be less than requested by external speed demand signal  103   a.    
     As shown in  FIG. 1 , speed demand generator  104  may include PWM demodulator  106 . As described herein PWM demodulator  106  may demodulate a PWM signal (e.g., external speed demand signal  103   a ) and provide a digital output value (e.g., as speed demand signal  107   a ). 
     Pulse-width modulation (PWM) generator  108  is coupled to receive speed demand signal  107   a  and generate PWM signal  109   a , a duty cycle of which is based upon speed demand signal  107   a . PWM generator  108  is also coupled to receive modulation waveforms (e.g., signal  129   a ) from modulation signal generator  128 . In some embodiments, PWM generator  108  generates PWM signal  109   a  with a modulation characteristic (i.e., a relative time-varying duty cycle) in accordance with the modulation waveforms (e.g., signal  129   a ) provided by modulation signal generator  128 . 
     Gate driver  110  receives PWM signal  109   a  and generates PWM transistor drive signals  111   a ,  111   b ,  111   c ,  111   d ,  111   e  and  111   f  (collectively, transistor drive signals  111 ) to drive corresponding switching elements, shown as field effect transistors (FETs) Q 1 , Q 2 , Q 3 , Q 4 , Q 5 , and Q 6 . Together, transistors Q 1  and Q 2  form a half-bridge circuit that generates motor control signal OUTA corresponding to a first phase, A, of motor  114 . Similarly, transistors Q 3  and Q 4  form a half-bridge circuit that generates motor control signal OUTB corresponding to a second phase, B, of motor  114 , and transistors Q 5  and Q 6  form a half-bridge circuit that generates motor control signal OUTC corresponding to a third phase, C, of motor  114 . 
     Although shown in  FIG. 1  as employing motor  114  as a three-phase motor and motor driver  102  as including six corresponding switching elements, it is understood that any practical number of switching elements coupled in various suitable configurations can be used to provide signals to energize motor  114 . 
     Although transistors Q 1 , Q 2 , Q 3 , Q 4 , Q 5  and Q 6  are shown as being an N-channel metal oxide semiconductor field effect transistors (MOSFETs), other types of switching elements may be employed, such as P-channel MOSFETs, bipolar junction transistors (BJTs), Silicon-Controlled Rectifiers (SCRs), thyristors, triacs, or other similar switching elements. When MOSFETs are employed, each transistor has a corresponding intrinsic body diode as shown in  FIG. 1 . Each body diode is arranged from drain (cathode) to source (anode) of the MOSFET, making the MOSFET able to block current in only one direction. The body diodes are thus frequently utilized as freewheeling diodes for inductive loads, such as motor  114 , for example when the MOSFET is used as a switch in a half-bridge circuit. 
     The six transistors Q 1 , Q 2 , Q 3 , Q 4 , Q 5  and Q 6  are synchronized to operate in saturation to provide three motor drive signals OUTA, OUTB and OUTC to motor  114 . In some embodiments, such as shown in  FIG. 1 , transistors Q 1 , Q 2 , Q 3 , Q 4 , Q 5  and Q 6  may be internal to motor driver  102 . In other embodiments, transistors Q 1 , Q 2 , Q 3 , Q 4 , Q 5  and Q 6  may be external devices coupled to motor driver  102 . 
     Motor driver  102  includes signal processor  122  which is coupled to receive at least one of the motor drive signals (e.g., at least one of OUTA, OUTB, and OUTC). Signal processor  122  may include position and speed sensing circuit  124  to determine a speed and/or a rotational reference position of motor  114  (e.g., an angular position of a moving element (rotor) of motor  114  relative to a stationary element (stator) of motor  114 ). 
     In some embodiments, signal processor  122  may include zero crossing detector  126  that generates at least one signal indicative of a zero crossing of one or more of the windings of motor  114 . 
     When motor  114  is a three-phase motor, the motor includes three windings, shown as windings  118   a ,  118   b  and  118   c , each of which, as would be understood by one of skill in the art, can be depicted as an equivalent circuit having an inductor in series with a back electromotive force (EMF) voltage source (not shown). As shown in  FIG. 1 , each winding  118   a ,  118   b  and  118   c  is joined in a Y configuration at a common point shown as center tap  116 . The voltage of the back EMF voltage source is directly observable when the current through the associated motor winding is zero. Thus, zero crossing information might beneficially be employed to determine back EMF and, therefore, also a direction of motion and position of motor  114 . 
     The back EMF for each winding is a voltage opposing the voltage of the motor control signals (e.g., OUTA, OUTB, and OUTC) that is proportional to the speed of the motor. Knowing when back EMF zero crossing points occur is indicative of an angular position of motor  114  (e.g., of a position of a moving element (rotor) of motor  114  relative to a stationary element (stator) of motor  114 ). Some embodiments may alternatively or additionally employ optional Hall effect elements or other magnetic field sensing elements, shown as sensing elements  120   a ,  120   b  and  120   c , disposed within motor  114  to detect the rotational position of motor  114 . Signals from the sensing elements  120   a ,  120   b  and  120   c  may be provided to signal processor  122  as sensor signals  121   a . Some embodiments may alternatively or additionally employ an optional current sensor  130  to determine current through motor  114 . Signals from the current sensor may be provided to signal processor  122  and current sense signal  125   a.    
     Modulation signal generator  128  is coupled to receive a speed reference signal and/or a position reference signal  127   a  from signal processor  122 . In some embodiments, modulation signal generator  128  can modify modulation waveforms (e.g., signal  129   a ) to PWM generator  108  based, at least in part, upon speed reference signal and/or a position reference signal  127   a . Thus, in some embodiments, motor driver  102  can automatically adjust a timing (i.e., a phase) of the transistor drive signals  111  in relation to a sensed rotational position and sensed rotational frequency of motor  114  (e.g., signal  127   a ) and a requested speed of motor  114  (e.g., speed demand signal  107   a ). 
     Some embodiments of motor driver  102  might also provide for driving motor  114  in a phase advance mode to reduce a back electromotive force of the motor and align a phase of the current through motor  114  and a phase of a voltage applied to motor  114  (e.g., align a phase of the current of motor drive signals OUTA, OUTB and OUTC and a phase of the voltage of motor drive signals OUTA, OUTB and OUTC, respectively). 
     Motor driver  102  receives a power supply voltage VBB, which is also supplied to motor  114  through transistors Q 1 , Q 3  and Q 5  during times when transistors Q 1 , Q 3  and Q 5  are turned on. Motor driver  102  also receives a ground (or circuit common) supply voltage GND, which is supplied to motor  114  through transistors Q 2 , Q 4  and Q 6  during times when transistors Q 2 , Q 4  and Q 6  are turned on. It will be understood that there can be a small voltage drop (for example, 0.1 volts) through transistors Q 1 , Q 2 , Q 3 , Q 4 , Q 5  and Q 6  when they are turned on and supplying current to motor  114 . 
     Current is provided to motor  114  by turning on an upper transistor (e.g., one of transistors Q 1 , Q 3  and Q 5 ) in a given half-bridge circuit to couple supply voltage VBB though the upper transistor to motor  114 , and turning on a lower transistor (e.g., one of transistors Q 2 , Q 4  and Q 6 ) in another half-bridge circuit to couple ground voltage GND though the lower transistor to motor  114 , allowing current to flow through one or more corresponding windings of motor  114 . For example, if upper transistor Q 1  is turned on (e.g., control signal  111   a  is logic high), then one of lower transistors Q 4  and Q 6  could be turned on (e.g., one of control signals  111   d  or  111   f  is logic high) to allow a current to flow through associated windings of motor  114  (e.g., windings  118   a  and  118   b , or windings  118   a  and  118   c ). 
     To prevent short circuit (or “shoot through”) conditions, only one transistor in each half-bridge circuit can be turned on at a given time. As a precaution, gate driver circuit  110  might control transistor drive signals  111  such that for short periods of time after one of the transistors of a given half-bridge circuit turns off, the other transistor cannot turn on and, thus, both transistors are off. This time is commonly known as “dead time” of the half-bridge circuit. For the illustrative system shown in  FIG. 1 , during dead time for each half-bridge circuit, the upper transistor (e.g., transistors Q 1 , Q 3  and Q 5 ) and the lower transistor (e.g., transistors Q 2 , Q 4  and Q 6 ) are both off (e.g., transistor drive signals  111   a  and  111   b  are both logic low, transistor drive signals  111   c  and  111   d  are both logic low, and transistor drive signals  111   e  and  117   f  are both logic low). 
     Referring to  FIG. 2 , additional detail of PWM demodulator  106  is shown as PWM demodulator  106 ′. PWM demodulator  106 ′ receives external speed demand signal  103   a ′, which is a PWM signal, and generates speed demand signal  107   a ′ as an N-bit digital signal. As shown, PWM demodulator  106 ′ may include multiplexer (MUX)  206  and low-pass filter (LPF)  208 . MUX  206  has a first input,  202 , coupled to receive a first predetermined digital value, MAX. In some embodiments, the digital value of MAX may be a maximum digital value of PWM demodulator  106 ′. For example, if speed demand signal  107   a ′ is an N-bit digital signal, a maximum value of the N-bit signal is  2   N −1. For example, in an 8-bit system, MAX might be equal to 255. MUX  206  has a second input,  204 , coupled to receive a second predetermined digital value, MIN. In some embodiments, the digital value of MIN may be a minimum digital value of PWM demodulator  106 ′. For example, if speed demand signal  107   a ′ is an N-bit digital signal, a minimum value of the N-bit signal is 0. Thus, in digital values, a PWM duty cycle of 0% (e.g., of external speed demand signal  103   a ′) corresponds to MIN, and a PWM duty cycle of 100% corresponds to MAX. 
     MUX  206  selects between the MAX and MIN values based upon a logic level of external speed demand signal  103   a ′. For example, if external speed demand signal  103   a ′ is a logic high value, MUX  206  may provide the MAX value as signal U IN , and if external speed demand signal  103   a ′ is a logic low value, MUX  206  may provide the MIN value as signal U IN . The U IN  signal is an N-bit digital value that varies between the values of MAX and MIN based upon the input PWM signal (e.g., external speed demand signal  103   a ′). LPF  208  receives the UIN signal and filters it to provide the U OUT  signal as a filtered N-bit digital value, which is output from PWM demodulator  106 ′ as speed demand signal  107   a′.    
     In some embodiments, LPF  208  may be implemented as a digital voltage-controlled voltage-source (VCVS) low-pass filter. An analog VCVS filter uses a super-unity-gain voltage amplifier with high input impedance and low output impedance to implement a 2-pole (e.g., approximately 40 dB/decade) low-pass, high-pass, or bandpass response. Described embodiments may employ a digital circuit to implement LPF  208 . For example, in systems where N is equal to 8, described embodiments may set a zero band frequency of LPF  208  as the frequency where the input signal amplitude is attenuated by approximately 256 (−46 dB) so that the ripple of the output affected by input PWM frequency is less than 1 bit. LPF  208  is described in greater detail in regard to  FIGS. 3 and 4 . 
     Referring to  FIG. 3 , an illustrative embodiment of LPF  208  is shown as LPF  208 ′. As shown in  FIG. 3 , LPF  208 ′ may include subtractors  304 ,  310  and  312 , adders  306  and  322 , accumulators  308  and  314 , dividers  302  and  316 , and multiplier  320 . LPF  208 ′ receives the N-bit digital U IN  signal at subtractor  304 , and subtracts an N-bit digital feedback signal, U M , from U IN , to generate first intermediate value  304   a . Subtractor  310  subtracts feedback signal U M  from the filtered N-bit digital value, U OUT , to generate second intermediate value  310   a . Adder  306  adds first intermediate value  304   a  and second intermediate value  310   a  to generate summed value  306   a . The values of summed value  306   a  are accumulated by accumulator  308  for a determined number of samples (e.g., a determined number of summed values  306   a ) to generate accumulated value  308   a . Subtractor  312  subtracts the filtered N-bit digital value, U OUT , from feedback signal U M  to generate third intermediate value  312   a . The values of third intermediate value  312   a  are accumulated by accumulator  314  for a determined number of samples (e.g., a determined number of intermediate values  312   a ) to generate accumulated value  314   a . Multiplier  320  multiplies accumulated value  314   a  by a gain factor, K, to generate intermediate gain value  320   a . Adder  322  adds intermediate gain value  320   a  and accumulated value  308   a  to generate intermediate feedback signal  322   a . Divider  302  divides intermediate feedback signal  322   a  by a time constant, T, to generate feedback signal U M . Divider  316  divides accumulated value  314   a  by a time constant, T, to generate the filtered N-bit digital value, U OUT , which is output from PWM demodulator  106 ′ as speed demand signal  107   a′.    
     Referring to  FIG. 4 , another illustrative embodiment of LPF  208  is shown as LPF  208 ″. As shown in  FIG. 4 , LPF  208 ″ may implement dividers  402  and  416  as right shift modules, and may implement multiplier  420  as a left shift module. For example, division by 2 X  may be performed by right shifting the N-bit digital value by X bit positions. Similarly, multiplication by 2 Y  may be performed by left shifting the N-bit digital value by Y bit positions. 
     In the embodiment shown in  FIG. 4 , X determines the cutoff frequency and the zero band frequency of LPF  208 ″. The value of K may be selected to have fast response, avoid overshooting, and provide ease of implementation in a binary digital circuit. For example, in some embodiments, K may be equal to 1.25. 
       FIG. 5A  shows a plot of the PWM input signal (waveform  502 ) and the N-bit digital output signal, U OUT , (waveform  504 ) over time. As shown in  FIG. 5A , the PWM input signal starts with a 0% duty cycle, and increases to a 90% duty cycle. Correspondingly, U OUT  starts with a value of 0, and increases over time to a value of approximately 90% of 2 N −1. For example, for the illustrative operating conditions of  FIG. 5A , N is 8, 2 N −1 is 255, and U OUT  reaches a digital value of approximately 230. 
       FIG. 5B  shows a plot of the PWM input signal (waveform  506 ) and the N-bit digital output signal, U OUT , (waveform  508 ) over time. As shown in  FIG. 5B , the PWM input signal starts with a 100% duty cycle, and decreases to a 10% duty cycle. Correspondingly, U OUT  starts with a value of 2 N −1, and decreases over time to a value of approximately 10% of 2 N −1. For example, for the illustrative operating conditions of  FIG. 5B , N is 8, 2 N −1 is 255, and U OUT  reaches a digital value of approximately 25. In both  FIGS. 5A and 5B , the PWM input signal may have a frequency of 2.5 kHz. 
       FIG. 6  shows a flow diagram of process  600  to operate motor  114  by motor driver  102 . At block  602 , operation of motor  114  begins. At block  604 , a PWM speed demand signal is received (e.g., motor control  102  receives external speed demand signal  103   a ). At block  606 , the PWM signal is demodulated and digitized (e.g., by PWM demodulator  106 ) into an N-bit digital value. Block  606  is described in greater detail in regard to  FIG. 7 . At block  608 , the gate drive signals (e.g., transistor drive signals  111 ) associated with the N-bit digital value are determined. At block  610 , motor  114  is operated based on the gate drive signals determined at block  608  (e.g., switching elements Q 1 , Q 2 , Q 3 , Q 4 , Q 5 , and Q 6  are driven based upon transistor drive signals  111  to provide power to motor  114 ). Process  600  may return to block  604  to continue to receive a PWM speed demand signal, for example, until system  100  is powered off. 
       FIG. 7  shows additional detail of block  606  of  FIG. 6 , shown as process  606 ′. At block  702 , process  606 ′ begins. At block  704 , if the PWM signal is a logic high value (e.g., if external speed demand signal  103   a  is logic high), then at block  706 , the digital input value to the low-pass filter is set to a maximum digital value for the current sample of the PWM signal (e.g., MUX  206  of  FIG. 2  provides MAX as signal U IN  for a current sample of external speed demand signal  103   a ). At block  704 , if the PWM signal is a logic low value (e.g., if external speed demand signal  103   a  is logic low), then at block  708 , the digital input value to the low-pass filter is set to a minimum digital value for the current sample of the PWM signal (e.g., MUX  206  of  FIG. 2  provides MIN as signal U IN  for a current sample of external speed demand signal  103   a ). 
     At block  710 , signal U IN  is low-pass filtered (e.g., by LPF  208  of  FIG. 2 ). Block  710  is described in greater detail in regard to  FIG. 8 . At block  712 , the N-bit digital output value, U OUT , is generated for the current sample of the PWM signal (e.g., external speed demand signal  103   a ). At block  714 , process  606 ′ completes. 
       FIG. 8  shows additional detail of block  710  of  FIG. 7 , shown as process  710 ′. At block  802 , low-pass filtering begins (e.g., by LPF  208  of  FIG. 2 ). At block  804 , the low-pass filter subtracts an N-bit digital feedback signal, U M , from the N-bit digital input signal U IN  to generate a first intermediate value (e.g., intermediate value  304   a  of  FIG. 3 ). At block  806 , feedback signal U M  is subtracted from the filtered N-bit digital value, U OUT , to generate a second intermediate value (e.g., intermediate value  310   a ). At block  808 , the filtered N-bit digital value, U OUT , is subtracted from feedback signal U M  to generate a third intermediate value (e.g., intermediate value  312   a ). 
     At block  810 , the first intermediate value and the second intermediate value are added (e.g., summed value  306   a ). At block  812 , the summed values are accumulated for a determined number of samples (e.g., a window of samples) to generate an accumulated value (e.g., accumulated value  308   a ). At block  814 , the values of the third intermediate value are accumulated for a determined number of samples (e.g., a window of samples) to generate an accumulated value (e.g., accumulated value  314   a ). At block  816 , the accumulated value of the third intermediate value is divided by a time constant, T, to generate the filtered N-bit digital value, U OUT , which is output from PWM demodulator  106  as speed demand signal  107   a . At block  818 , the accumulated value of the third intermediate value is multiplied by a gain factor, K, to generate an intermediate gain value (e.g., intermediate gain value  320   a ). At block  820 , the intermediate gain value is added to the accumulated value  308   a  to generate an intermediate feedback signal (e.g., intermediate feedback signal  322   a ). At block  822 , the intermediate feedback signal is divided by a time constant, T, to generate feedback signal U M . At block  824 , low-pass filtering process  710 ′ completes. 
     In some embodiments, motor driver  102  may include a processor. As used herein, the term “processor” describes an electronic circuit that performs a function, an operation, or a sequence of operations. The function, operation, or sequence of operations can be hard coded into the electronic circuit or soft coded by way of instructions held in a memory device. A “processor” can perform the function, operation, or sequence of operations using digital values or using analog signals. In some embodiments, the “processor” can be embodied in an application specific integrated circuit (ASIC). In some embodiments, the “processor” can be embodied in a microprocessor with associated program memory. In some embodiments, the “processor” can be embodied in a discrete electronic circuit. The “processor” can be analog, digital or mixed-signal. 
     Various functions of circuit elements may also be implemented as processing blocks in a software program. Such software may be employed in, for example, a digital signal processor, microcontroller, or general purpose computer. Thus, described embodiments may be implemented in hardware, a combination of hardware and software, software, or software in execution by one or more processors. 
     Some embodiments may be implemented in the form of methods and apparatuses for practicing those methods. Described embodiments may also be implemented in the form of program code, for example, stored in a storage medium, loaded into and/or executed by a machine, or transmitted over some transmission medium or carrier, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation. A non-transitory machine-readable medium may include but is not limited to tangible media, such as magnetic recording media including hard drives, floppy diskettes, and magnetic tape media, optical recording media including compact discs (CDs) and digital versatile discs (DVDs), solid state memory such as flash memory, hybrid magnetic and solid state memory, non-volatile memory, volatile memory, and so forth, but does not include a transitory signal per se. When embodied in a non-transitory machine-readable medium, and the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the method. 
     When implemented on a processing device, the program code segments combine with the processor to provide a unique device that operates analogously to specific logic circuits. Such processing devices may include, for example, a general purpose microprocessor, a digital signal processor (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic array (PLA), a microcontroller, an embedded controller, a multi-core processor, and/or others, including combinations of the above. Described embodiments may also be implemented in the form of a bitstream or other sequence of signal values electrically or optically transmitted through a medium, stored magnetic-field variations in a magnetic recording medium, etc., generated using a method and/or an apparatus as recited in the claims. 
     Various elements, which are described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. It will be further understood that various changes in the details, materials, and arrangements of the parts that have been described and illustrated herein may be made by those skilled in the art without departing from the scope of the following claims.