Patent Publication Number: US-7902913-B2

Title: Reference voltage generation circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a divisional of U.S. application Ser. No. 11/934,970, filed Nov. 5, 2007, now U.S. Pat. No. 7,633,330, and is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-300535, filed on Nov. 6, 2006, the entire contents of both of which are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     An aspect of the present invention relates to a semiconductor integrated circuit and in particular to a reference voltage generation circuit for outputting a reference voltage. 
     2. Description of the Related Art 
     A band gap reference (BGR) circuit for outputting a given reference voltage if the ambient temperature fluctuates by using a band gap of a semiconductor is widely used with a semiconductor integrated circuit (LSI) of memory, etc. A BGR circuit that can operate on a low power supply voltage is demanded as the power supply voltage of an LSI lowers. Thus, a BGR circuit that can output a reference voltage on power supply voltage 1V or less is proposed (for example, refer to Hironori Banba et al. “A CMOS bandgap reference circuit with sub-1-v operation,” USA electronics and communications engineer association journal of solid-state circuits, vol. 34, number 5, May 1999). 
     The above proposed BGR circuit operates on a power supply voltage of 1V or less by lessening the threshold voltage of MOS transistors. However, the above proposed BGR circuit involves a problem of occurrence of variations in the reference voltage caused by the threshold voltage variations of PMOS transistors (p-channel MOS transistors). Especially, in an integrated circuit having a large variation in a threshold voltage of transistors, such as a ferroelectric memory, the BGR voltage varies with transistor manufacturing variations. 
     SUMMARY OF THE INVENTION 
     According to an aspect of the present invention, there is provided a reference voltage generation circuit including: a first transistor including: a first gate, a first source, and a first drain; a second transistor including: a second gate connected to the first gate, a second source connected to the first source, and a second drain; a first diode connected between a ground level and a V− node; a first resistor connected between the V− node and the first drain; a second diode connected between the ground level and a Vdio node; a second resistor connected between the Vdio node and a V+ node; a third resistor connected between the V+ node and the first drain; a first operational amplifier including: a first plus input port connected to the V+ node, a first minus input port connected to the V− node, and a first output port connected to the first gate and the second gate; a fourth resistor connected between the ground level and the second drain; and an output terminal disposed between the second drain and the fourth resistor. 
     According to another aspect of the present invention, there is provided a reference voltage generation circuit including: a reference current generation circuit including: an output terminal from which a temperature-independent current is output; a third transistor including: a third gate, a third source, and a third drain connected to the output terminal; a second operational amplifier including: a second plus input port connected to the output terminal, a second minus input port connected to a power supply voltage via a variable resistor that is disposed between the power supply voltage and a ground level, and a second output port connected to the third gate; and a fourth resistor connected between the output terminal and the ground level. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiment may be described in detail with reference to the accompanying drawings, in which: 
         FIG. 1  is a schematic drawing showing the configuration of a reference voltage generation circuit according to a first embodiment; 
         FIG. 2  is a schematic drawing showing a configuration example of a reference voltage generation circuit according to a first comparison example; 
         FIG. 3  is a schematic drawing showing a configuration example of a reference voltage generation circuit according to a second comparison example; 
         FIG. 4  is a schematic drawing showing a configuration example of a reference voltage generation circuit according to a third comparison example; 
         FIG. 5  is a schematic drawing showing the configuration of a reference voltage generation circuit according to a first modified example of the first embodiment; 
         FIG. 6  is a schematic drawing showing the configuration of a reference voltage generation circuit according to a second modified example of the first embodiment; 
         FIG. 7  is a schematic drawing showing the configuration of a reference voltage generation circuit according to a second embodiment; 
         FIG. 8  is a graph showing the relationship between the reference voltage output by the reference voltage generation circuit according to the second embodiment and power supply voltage; 
         FIG. 9  is a schematic drawing showing the configuration of a reference voltage generation circuit according to a third embodiment; 
         FIG. 10  is a schematic drawing showing a configuration example of a reference voltage generation circuit according to a fourth comparison example; and 
         FIG. 11  is a schematic drawing showing a configuration example of a reference voltage generation circuit according to a fifth comparison example. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     First and third embodiments will be discussed with reference to the accompanying drawings. The identical parts or similar parts described below with reference to the accompanying drawings are denoted by the same or similar reference numerals. The following first to third embodiments illustrate apparatus and methods for embodying the technical idea of the invention and the technical idea of the invention does not limit the structures, placement, etc., of components to those described below. Various changes can be added to the technical idea of the invention in the claims. 
     First Embodiment 
     A reference voltage generation circuit according to the first embodiment includes a first operational amplifier  30 , first and second PMOS transistors T 1  and T 2  with gate electrodes to which output of the first operational amplifier  30  is input, a circuit block  10  that sets the drain current of the first PMOS transistor T 1  to a current I 10  independent of the temperature, and an output resistor R out  connected between a drain electrode of the second PMOS transistor T 2  and a ground line  201 , and outputs the voltage of a connection node  103  of the drain electrode of the second PMOS transistor T 2  and the fourth resistor (output resistor) R out  as a reference voltage V BGR , as shown in  FIG. 1 . 
     The first PMOS transistor T 1  and the second PMOS transistor T 2  shown in  FIG. 1  are PMOS transistors of the same size. A power supply line  200  that supplies power supply voltage VDD is connected to source electrodes of the first PMOS transistor T 1  and the second PMOS transistor T 2 . An output terminal of the first operational amplifier  30  is connected to the gate electrodes. The circuit block  10  is connected to a drain electrode of the first PMOS transistor T 1 . 
     The circuit block  10  includes a first diode D 110  and a first resistor R 110  connected in series in a V− node between the ground level (ground line  201 ) and the drain electrode of the first PMOS transistor T 1 . The first resistor R 110  is connected at one end to the drain electrode of the first PMOS transistor T 1  and is connected at an opposite end to an anode of the first diode D 110  in the V− node. A cathode of the first diode D 110  is connected to the ground line  201 . The circuit block  10  sets the drain current of the first PMOS transistor T 1  to the current I 10  independent of the temperature. 
     The circuit block  10  also includes a circuit block  121  having a second diode D 120  and a second resistor R 121  connected in series and a third resistor R 120  connected in series in a V+ node between the ground line  201  and the drain electrode of the first PMOS transistor T 1 . The second diode D 120  has a plurality of diodes D 121  to D 12   n  connected in parallel (where n is an integer of two or more), each of the diodes D 121  to D 12   n  equaling the first diode D 110  in energization area. The third resistor R 120  is connected at one end to the drain electrode of the first PMOS transistor T 1  and is connected at an opposite end to one end of the second resistor R 121  in the V+ node. An opposite end of the second resistor R 121  is connected to anodes of the diodes D 121  to D 12   n . Cathodes of the diodes D 121  to D 12   n  are connected to the ground line  201 . The third resistor R 120  and the first resistor R 110  are equal in resistance value. 
     The circuit operation of the circuit block  10  is as follows: Let currents flowing from the drain electrode of the first PMOS transistor T 1  into a circuit block  11  and a circuit block  12  shown in  FIG. 1  be a current I 11  and a current I 12  respectively. The current I 10  is the sum of the current I 11  and the current I 12 . A voltage V− of the V− node is input to a minus input terminal  101  of the first operational amplifier  30  and a voltage V+ of the V+ node is input to a plus input terminal  102  of the first operational amplifier  30 . Since the gate voltage of the first PMOS transistor T 1  is controlled through the first operational amplifier  30  so that the voltages V− and V+ become equal, inevitably the current I 11  and the current I 12  also become equal when the resistance values of the first resistor R 110  and the third resistor R 120  are same. That is, the current I 10  is controlled so that the voltage V− of the V− node and the voltage V+ of the V+ node become equal. 
     The current I 11  and the current I 12  are represented by expressions (1) and (2) using a forward voltage Vf 1  of the first diode D 110 , backward saturation current Is of the first diode D 110 , a forward voltage Vf 2  of the second diode D 120  (the diodes D 121 , D 122 , . . . , D 12   n ), Boltzmann&#39;s constant k, absolute temperature T, and electric charge q:
 
 I   11   =Is ×exp{ q×Vf 1/( k×T )}  (1)
 
 I   12   =n×Is ×exp{ q×Vf 2/( k×T )}  (2)
 
     Here, VT is defined as in expression (3):
 
 VT =( k×T )/ q   (3)
 
     Since the current I 10  is controlled so that the voltage V− of the V− node and the voltage V+ of the V+ node become equal, the voltage occurring across the first resistor R 110  and the voltage occurring across the third resistor R 120  are the same. Thus, expression (4) holds true:
 
 I   11   ×R   110   =I   12   ×R   120   (4)
 
     In expression (4), R 110  and R 120  are the resistance values of the first resistor R 110  and the third resistor R 120 . From expressions (1) to (4), the forward voltages Vf 1  and Vf 2  are represented by expressions (5) and (6): 
     
       
         
           
             
               
                 
                   
                     Vf 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   = 
                   
                     VT 
                     × 
                     
                       ln 
                       ⁡ 
                       
                         ( 
                         
                           
                             I 
                             11 
                           
                           ⁢ 
                           
                             / 
                           
                           ⁢ 
                           Is 
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
             
               
                 
                   
                     Vf 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   = 
                   
                     
                       VT 
                       × 
                       ln 
                       ⁢ 
                       
                         { 
                         
                           
                             I 
                             12 
                           
                           ⁢ 
                           
                             / 
                           
                           ⁢ 
                           
                             ( 
                             
                               n 
                               × 
                               Is 
                             
                             ) 
                           
                         
                         } 
                       
                     
                     ⁢ 
                     
                       
 
                     
                     ⁢ 
                     
                         
                     
                     = 
                     
                       VT 
                       × 
                       
                         ln 
                         ⁡ 
                         
                           [ 
                           
                             
                               { 
                               
                                 
                                   I 
                                   11 
                                 
                                 ⁢ 
                                 
                                   / 
                                 
                                 ⁢ 
                                 
                                   ( 
                                   
                                     n 
                                     × 
                                     Is 
                                   
                                   ) 
                                 
                               
                               } 
                             
                             × 
                             
                               ( 
                               
                                 
                                   R 
                                   110 
                                 
                                 ⁢ 
                                 
                                   / 
                                 
                                 ⁢ 
                                 
                                   R 
                                   120 
                                 
                               
                               ) 
                             
                           
                           ] 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     From expressions (5) and (6), difference dVf between the forward voltage Vf 1  and the forward voltage Vf 2  is represented by expression (7):
 
 dVf=Vf 1 −Vf 2 =VT× 1 n ( n×R   120   /R   110 )  (7)
 
     The difference dVf is the voltage occurring across the second resistor R 121 . This means that expression (8) holds true:
 
 dVf=I   12   ×R   121   (8)
 
     In expression (8), R 121  is the resistance value of the second resistor R 121 . From expressions (4) and (8), expression (9) is found:
 
 I   11   ×R   110   =I   12   ×R   120   =R   120   /R   121   ×dVf   (9)
 
     From the forward voltage Vf 1  of the first diode D 110  and expression (9), voltage Vref of the drain electrode of the first PMOS transistor T 1  is represented by expression (10): 
     
       
         
           
             
               
                 
                   
                     V 
                     ref 
                   
                   = 
                   
                     
                       
                         Vf 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       + 
                       
                         
                           R 
                           120 
                         
                         ⁢ 
                         
                           / 
                         
                         ⁢ 
                         
                           R 
                           121 
                         
                         × 
                         dVf 
                       
                     
                     ⁢ 
                     
                       
 
                     
                     ⁢ 
                     
                         
                     
                     = 
                     
                       
                         Vf 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       + 
                       
                         
                           R 
                           120 
                         
                         ⁢ 
                         
                           / 
                         
                         ⁢ 
                         
                           R 
                           121 
                         
                         × 
                         VT 
                         × 
                         ln 
                         ⁢ 
                         
                           { 
                           
                             ( 
                             
                               n 
                               × 
                               
                                 R 
                                 120 
                               
                               ⁢ 
                               
                                 / 
                               
                               ⁢ 
                               
                                 R 
                                 110 
                               
                             
                             ) 
                           
                           } 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
     Generally, the forward voltage of a diode has negative dependence on the ambient temperature. For example, the dependence of the forward voltage Vf 1  on the ambient temperature is about −2 mV/° C. On the other hand, VT has positive dependence on the ambient temperature. The dependence of VT on the ambient temperature is about +0.086 mV/° C. Thus, the resistance values of the first resistor R 110 , the third resistor R 120 , and the second resistor R 121  and the integer flare appropriately selected based on expression (10), whereby the voltage Vref of the drain electrode of the first PMOS transistor T 1  can be set so that it does not depend on the ambient temperature. If the voltage Vref does not depend on the ambient temperature, the current I 10  independent of the ambient temperature flows into the first PMOS transistor T 1 . Since the resistance values of the first resistor R 110  and the third resistor R 120  are the same, the current I 11  and the current I 12  are the same. 
     The resistance values of the first resistor R 110  and the third resistor R 120  are set to large values to such an extent that the resistance value variations do not affect the reference voltage V BGR . However, to set the reference voltage generation circuit shown in  FIG. 1  to low power supply voltage, the range in which the voltage of the power supply line  200  is lowered is limited as much as the voltage drop in the first resistor R 110  and the third resistor R 120 . 
     In the reference voltage generation circuit according to the first embodiment shown in  FIG. 1 , the V− node is connected to the minus input terminal  101  of the first operational amplifier  30 , the V+ node is connected to the plus input terminal  102  of the first operational amplifier  30 , and the current I 10  is controlled so that the voltages of the V− node and the V+ node become equal. Consequently, the current I 10  independent of the ambient temperature flows into the first PMOS transistor T 1  as previously described. The voltages of the gate electrodes of the first PMOS transistor T 1  and the second PMOS transistor T 2  are equal and the voltages of the source electrodes of the first PMOS transistor T 1  and the second PMOS transistor T 2  are equal. Thus, a drain current equal to the current I 10  of the drain current of the first PMOS transistor T 1  flows into the second PMOS transistor T 2 . This means that the drain current of the second PMOS transistor T 2  independent of the ambient temperature flows from the second PMOS transistor T 2  into the output resistor R out . The output resistor R out  has a resistance value of, for example, several mega ohms. Consequently, the reference voltage V BGR  that is independent of the ambient temperature is output from the connection node  103 . 
     A comparison is made between the reference voltage generation circuit according to the first embodiment and reference voltage generation circuits according to first and second comparison example illustrated in  FIGS. 2 and 3  as follows: 
     The reference voltage generation circuit according to the first comparison example shown in  FIG. 2  has an operational amplifier  30   a , a PMOS transistor Ta 1 , a diode Da 1 , and diodes Da 21  to Da 2   m  (where m is an integer of two or more). The energization area of each of the diodes Da 21  to Da 2   m  is the same as that of the diode Da 1 . 
     Cathodes of the diodes Da 21  to Da 2   m  are connected to a ground line  201   a  and anodes are connected to one end of a resistor Ra 12 . One end of a resistor Ra 11  is connected to an opposite end of the resistor Ra 12  and wiring  202   a  is connected to an opposite end of the resistor Ra 11 . A cathode of the diode Da 1  is connected to the ground line  201   a  and a resistor Ra 2  is connected between an anode of the diode Da 1  and the wiring  202   a . A plus input terminal of the operational amplifier  30   a  is connected to a connection part of the resistors Ra 11  and Ra 12  and a minus input terminal is connected to a connection part of the anode of the diode Da 1  and the resistor Ra 2 . An output terminal of the operational amplifier  30   a  is connected to a gate electrode of the PMOS transistor Ta 1  and a power supply line  200   a  is connected to a source electrode. The wiring  202   a  is connected to a drain electrode of the PMOS transistor Ta 1  and reference voltage V BGR  is output as the voltage of the drain electrode of the PMOS transistor Ta 1 . 
     By using the fact that the forward voltages of the diode Da 1  and the diodes Da 21  to Da 2   m  have negative dependence on the ambient temperature and that a diffusion current has positive dependence on the ambient temperature, and by adjusting the resistance values of the resistors Ra 11 , Ra 12 , and Ra 2  appropriately, the reference voltage V BGR  with temperature compensated is output from the reference voltage generation circuit shown in  FIG. 2 . 
     In the reference voltage generation circuit shown in  FIG. 2 , since only one PMOS transistor Ta 1  is used, the reference voltage V BGR  is hard to be affected by the threshold voltage variations of the PMOS transistors. However, the voltage difference between the anodes of the diodes Da 21  to Da 2   m  and the wiring  202   a  is divided by the resistors Ra 11  and Ra 12  for setting the voltage of the plus input terminal of the operational amplifier  30   a . The reference voltage V BGR  output using the resistor dividing is, for example, about 1.25 V. This means that the voltage of the power supply line  200   a  cannot be lowered beyond 1.25 V. That is, the reference voltage generation circuit shown in  FIG. 2  has the disadvantage in that it is not suited to low-voltage operation. 
     The reference voltage generation circuit according to the second comparison example shown in  FIG. 3  has an operational amplifier  30   b , PMOS transistors Tb 1  to Tb 3 , a diode Db 1 , and diodes Db 21  to Db 2   m . The energization area of each of the diodes Db 21  to Db 2   m  is the same as that of the diode Db 1 . 
     Source electrodes of the PMOS transistors Tb 1  to Tb 3  are connected to a power supply line  200   b  and gate electrodes are connected to an output terminal of the operational amplifier  30   b . An anode of the diode Db 1  is connected to a drain electrode of the PMOS transistor Tb 1 . A cathode of the diode Db 1  is connected to a ground line  201   b . A drain electrode of the PMOS transistor Tb 2  is connected to one end of a resistor Rb 3 . An opposite end of the resistor Rb 3  is connected to anodes of the diodes Db 21  to Db 2   m . Cathodes of the diodes Db 21  to Db 2   m  are connected to the ground line  201   b . A drain electrode of the PMOS transistor Tb 3  is connected to one end of a resistor Rb 4  and an opposite end of the resistor Rb 4  is connected to the ground line  201   b.    
     By using the fact that the forward voltages of the diode Db 1  and the diodes Db 21  to Db 2   m  have negative dependence on the ambient temperature and that a diffusion current has positive dependence on the ambient temperature, and by adjusting the resistance value of the resistor Rb 3  appropriately, constant reference voltage V BGR  independent of temperature is output from the reference voltage generation circuit shown in  FIG. 3 . In the reference voltage generation circuit shown in  FIG. 3 , the voltage of the drain electrode of the PMOS transistor Tb 1  and the voltage of the drain electrode of the PMOS transistor Tb 2  are input to a minus input terminal and a plus input terminal of the operational amplifier  30   b . The voltages of the minus input terminal and the plus input terminal of the operational amplifier  30   b  are made equal, whereby the reference voltage V BGR  is output from the connection part of the drain electrode of the PMOS transistor Tb 3  and the resistor Rb 4 . 
     The reference voltage generation circuit according to the second comparison example shown in  FIG. 3  does not adopt the configuration of two stages of resistors as in the reference voltage generation circuit according to the first comparison example shown in  FIG. 2 , and uses the PMOS transistors Tb 1  to Tb 3  to set the reference voltage V BGR . Thus, the reference voltage generation circuit shown in  FIG. 3  has the advantage that the voltage of the power supply line  200   b  can be set lower than the voltage of the power supply line  200   a  in the reference voltage generation circuit shown in  FIG. 2 , for example, can be set to about 0.84 V. However, the reference voltage generation circuit shown in  FIG. 3  has the disadvantage in that the reference voltage V BGR  is easily affected by the threshold voltage variations of the PMOS transistors because three PMOS transistors are used. 
     A reference voltage generation circuit in  FIG. 4  according to a third compassion example is also possible as a configuration similar to that in  FIG. 3 . The reference voltage generation circuit shown in  FIG. 4  differs from the reference voltage generation circuit shown in  FIG. 3  in that it further includes resistors Rb 1  and Rb 2 . The resistor Rb 1  is connected at one end to a drain electrode of a PMOS transistor Tb 1  and is connected at an opposite end to a ground line  201 . The resistor Rb 2  is connected at one end to a drain electrode of a PMOS transistor Tb 2  and is connected at an opposite end to a ground line  201   b . By adjusting the resistance values of the resistors Rb 1  to Rb 3  appropriately, reference voltage V BGR  with temperature compensated is output from the reference voltage generation circuit shown in  FIG. 4 . 
     As compared with the reference voltage generation circuit according to the second comparison example shown in  FIG. 3 , the reference voltage generation circuit shown in  FIG. 1  has the advantage that the number of the used PMOS transistors is smaller by one than that in the reference voltage generation circuit shown in  FIG. 3 . Thus, the reference voltage generation circuit shown in  FIG. 1  has the advantage that the reference voltage V BGR  output by the reference voltage generation circuit shown in  FIG. 1  is hard to be affected by the threshold voltage variations of the PMOS transistors as compared with the reference voltage generation circuit shown in  FIG. 3 . 
     As compared with the reference voltage generation circuit according to the first comparison example shown in  FIG. 2 , the reference voltage generation circuit shown in  FIG. 1  has the advantage that the voltage drop in the first resistor R 110  and the third resistor R 120  can be made smaller than the voltage drop in the resistor Ra 11  in  FIG. 2 , whereby the reference voltage V BGR  can be set to be low (for example, can be set to about 1 V). 
     As described above, the reference voltage generation circuit according to the first embodiment can operate on low power supply voltage and can output the reference voltage V BGR  less affected by the threshold voltage variations of the PMOS transistors. 
     First Modified Example 
       FIG. 5  shows a reference voltage generation circuit according to a first modified example of the first embodiment. The reference voltage generation circuit shown in  FIG. 5  differs from the reference voltage generation circuit shown in  FIG. 1  in that it further includes a fifth resistor R 111  connected to the first diode D 110  in parallel and a sixth resistor R 122  connected between the ground line and the V+ node and having a resistance value equal to that of the fifth resistor R 111 . 
     In the first modified example of the first embodiment, in addition to the design parameters of the first embodiment shown in  FIG. 1 , the resistance values of the fifth resistor R 111  and the sixth resistor R 122  can be adjusted as a design parameter. 
     Second Modified Example 
       FIG. 6  shows a reference voltage generation circuit according to a second modified example of the first embodiment. In the reference voltage generation circuit shown in  FIG. 6 , a first diode D 110  and a first resistor R 110  are connected in the above mentioned order between a drain electrode of a second PMOS transistor T 2  and a ground line  201 . This means that the first diode D 110  has an anode connected to a drain electrode of a first PMOS transistor T 1  and a cathode connected to one end of the first resistor R 110 . An opposite end of the first resistor R 110  is connected to the ground line  201 . 
     Also, in the reference voltage generation circuit shown in  FIG. 6 , a circuit block  121  and a third resistor R 120  are connected in the above mentioned order between the drain electrode of the second PMOS transistor T 2  and the ground line  201 . This means that diodes D 121  to D 12   n  have anodes connected to the drain electrode and cathodes connected to one end of the second resistor R 121 . An opposite end of the second resistor R 121  is connected to one end of the third resistor R 120  and an opposite end of the third resistor R 120  is connected to the ground line  201 . 
     In the reference voltage generation circuit shown in  FIG. 6 , voltage V− and voltage V+ are made equal by a first operational amplifier  30 , whereby the sum of current I 11  and current I 12  becomes current I 10  independent of the ambient temperature. Thus, a drain current equal to the current I 10  and independent of the ambient temperature flows into the second PMOS transistor T 2 . Consequently, reference voltage V BGR  independent of the ambient temperature is output from a connection node  103  of the reference voltage generation circuit shown in  FIG. 6 . 
     Second Embodiment 
     A reference voltage generation circuit according to a second embodiment differs from the reference voltage generation circuit of the first embodiment in that it further includes a second operational amplifier  60  and a third PMOS transistor T 3 , as shown in  FIG. 7 . To the second operational amplifier  60 , a voltage V REFBI  provided by dividing power supply voltage VDD by a resistor and a reference voltage V BGR  are input. A gate electrode of the third PMOS transistor T 3  is connected to an output terminal of the second operational amplifier  60 . The reference voltage generation circuit shown in  FIG. 7  outputs a voltage V REF  and a voltage V REFDC  based on the reference voltage V BGR  output from the reference voltage generation circuit shown in  FIG. 4 . 
     The voltage V REFBI  is provided as the voltage difference between a power supply line  200   b  and aground line  201   b  is divided by a variable resistor Rvar shown in  FIG. 7 . The voltage V REFBI  can be changed by changing the resistance division ratio. The second operational amplifier  60  makes a comparison between the voltage V REFBI  and the reference voltage V BGR . And, the second operational amplifier  60  controls a third PMOS transistor T 3  based on the comparison result, as described later. 
     As shown in  FIG. 7 , a drain electrode of the third PMOS transistor T 3  and a plus input terminal of the second operational amplifier  60  are connected to a connection node  103 . The voltage of the connection node  103  is input to the plus input terminal of the second operational amplifier  60  and the voltage V REFBI  is input to a minus input terminal of the second operational amplifier  60 . 
     If the voltage of the minus input terminal of the second operational amplifier  60  is lower than the voltage of the plus input terminal, the second operational amplifier  60  outputs high. If the voltage of the minus input terminal is higher than the voltage of the plus input terminal, the second operational amplifier  60  outputs low. When the second operational amplifier  60  outputs high, the third PMOS transistor T 3  is turned off; when the second operational amplifier  60  outputs low, the third PMOS transistor T 3  is turned on. This means that the third PMOS transistor T 3  is turned off when the voltage V REFBI  is lower than the voltage of the connection node  103 , and that the third PMOS transistor T 3  is turned on when the voltage V REFBI  is higher than the voltage of the connection node  103 . That is, when V REFBI &lt;V BGR , V REF =V BGR  is output as the reference voltage; when V REFBI &gt;V BGR , V REF =V REFBI  is output as the reference voltage. 
     A source electrode of the third PMOS transistor T 3  is connected to the power supply line  200   b  and a resistor Rb 4  is connected to the drain electrode. When the third PMOS transistor T 3  is turned on, an electric current is supplied from the power supply line  200   b  through the third PMOS transistor T 3  to the resistor Rb 4 . This means that the third PMOS transistor T 3  supplies an electric current to the resistor Rb 4  under the control of the second operational amplifier  60 . As shown in  FIG. 7 , the resistor Rb 4  connected between the connection node  103  and the ground line  201   b  is divided and the voltage V REFDC  is set. The resistor Rb 4  is divided into resistors Rb 41  to Rb 43  to make the voltage V REFDC  from the voltage V REF , and functioning as an output adjusting section. 
       FIG. 8  shows dependence of the voltage V REF  and the voltage V REFDC  on the power supply voltage VDD supplied from the power supply line  200   b . As the power supply voltage VDD rises from 0 V, the voltage of the connection node  103  rises and the voltage V REF  and the voltage V REFDC  rise. When the power supply voltage VDD reaches a voltage Vdd 1 , the voltage of the connection node  103  becomes constant at the reference voltage V BGR  and the voltage V REF  and the voltage V REFDC  become constant at the voltage V BGR  and voltage V BGR ×Rb 43 /Rb 4  respectively. The voltage Vdd 1  is the voltage of the power supply line  200   b  at which the voltage of the connection node  103  reaches the reference voltage V BGR . Then, the voltage V REF  and the voltage V REFDC  are maintained at constant values regardless of rise in the power supply voltage VDD until the power supply voltage VDD reaches a voltage Vdd 2 . The voltage Vdd 2  is the voltage of the power supply line  200   b  at which the voltage V REFBI  becomes equal to the reference voltage V BGR . 
     When the power supply voltage VDD becomes the voltage Vdd 2  or more, the voltage V REFBI  becomes equal to or larger than the reference voltage V BGR , and the voltage V REF  and the voltage V REFDC  rise with the rise in the power supply voltage VDD, as shown in  FIG. 8 . 
     For example, in a burn-in test of a semiconductor integrated circuit, the voltage V REF  and the voltage V REFDC  can be used as the reference voltage of the semiconductor integrated circuit to be subjected to the burn-in test. Thus, the voltage V REFBI  is set based on the test condition, etc., of the burn-in test of a semiconductor integrated circuit. As the voltage V REFBI  is adjusted, the reference voltage generation circuit shown in  FIG. 7  can output any desired voltage V REF  and voltage V REFDC . 
     Third Embodiment 
     A reference voltage generation circuit according to a third embodiment differs from the reference voltage generation circuit according to the first embodiment shown in  FIG. 5  in that it further includes a second operational amplifier  60  and a third PMOS transistor T 3 , as shown in  FIG. 9 . To the second operational amplifier  60 , a voltage V REFBI  provided by dividing power supply voltage VDD by a resistor and a reference voltage V BGR  are input. The third PMOS transistor T 3  has a gate electrode connected to an output terminal of the second operational amplifier  60  and a drain electrode connected to a connection node  103 . The reference voltage generation circuit shown in  FIG. 9  outputs a voltage V REF  and a voltage V REFDC  based on a reference voltage V BGR . 
     A plus input terminal of the second operational amplifier  60  is connected to the connection node  103 , a voltage V REFBI  is connected to a minus input terminal, and output of the second operational amplifier  60  is input of a gate electrode of a third PMOS transistor T 3 . 
     In the reference voltage generation circuit shown in  FIG. 9 , the second operational amplifier  60  makes a comparison between the voltage V REFBI  and the reference voltage V BGR  and controls the third PMOS transistor T 3  based on the comparison result as in the reference voltage generation circuit shown in  FIG. 7 . 
     A source electrode of the third PMOS transistor T 3  is connected to a power supply line  200  and an output resistor R outb  is connected to the drain electrode. When the third PMOS transistor T 3  is turned on, an electric current is supplied from the power supply line  200  through the third PMOS transistor T 3  to the output resistor R outb . This means that the third PMOS transistor T 3  supplies an electric current to the output resistor R outb  under the control of the second operational amplifier  60 . 
     As shown in  FIG. 9 , the output resistor R outb  is divided and the voltage V REFDC  is set. The resistor R outb  is divided into resistors R out1  to R out3  to make the voltage V REFDC  from the voltage V REF , and functioning as an output adjusting section. 
     For comparison,  FIGS. 10 and 11  show reference voltage generation circuits according to fourth and fifth comparison examples for outputting voltage V REF  and voltage V REFDC  using third PMOS transistor T 3 , variable resistor Rvar, and second operational amplifier  60 . 
     The reference voltage generation circuit shown in  FIG. 10  includes an operational amplifier  31   a  and a PMOS transistor Ta 2  and outputs voltage V REF  and voltage V REFDC  based on the reference voltage V BGR  shown in  FIG. 2 . The reference voltage V BGR  is output to a minus input terminal of the operational amplifier  31   a . A plus input terminal of the operational amplifier  31   a , a drain electrode of the transistor Ta 2 , a drain electrode of the third PMOS transistor T 3 , and a plus input terminal of the second operational amplifier  60  are connected to one end of a resistor Ra out . An opposite end of the resistor Ra out  is connected to a ground line  201   a . A power supply line  200   a  is connected to a source electrode of the PMOS transistor Ta 2  and output of the operational amplifier  31   a  is input to a gate electrode of the PMOS transistor Ta 2 . In the reference voltage generation circuit shown in  FIG. 10 , the voltage V REFDC  is set by dividing the resistor Ra out . 
     In the reference voltage generation circuits according to the second and third embodiments shown in  FIGS. 7 and 9 , the number of the operational amplifiers is reduced as compared with the reference voltage generation circuit according to the fourth comparison example shown in  FIG. 10 . Generally, the operational amplifier uses, for example, 5 or more transistors. Since the number of the operational amplifier is reduced, the number of the circuit elements (transistors) of the reference voltage generation circuits according to the second and third embodiments can be reduced. 
     The reference voltage generation circuit shown in  FIG. 11  includes an operational amplifier  31   b  and a PMOS transistor Tb 4  and outputs voltage V REF  and voltage V REFDC  based on the reference voltage V BGR  shown in  FIG. 3 . The reference voltage V BGR  is output to a minus input terminal of the operational amplifier  31   b . A plus input terminal of the operational amplifier  31   b , a drain electrode of the PMOS transistor Tb 4 , a drain electrode of the third PMOS transistor T 3 , and a plus input terminal of the second operational amplifier  60  are connected to one end of a resistor Rb out . An opposite end of the resistor Rb out  is connected to a ground line  201   b . A power supply line  200   b  is connected to a source electrode of the PMOS transistor Tb 4  and output of the operational amplifier  31   b  is input to a gate electrode of the PMOS transistor Tb 4 . In the reference voltage generation circuit shown in  FIG. 11 , the voltage V REFDC  is set by dividing the resistor Rb out . 
     The number of the circuit elements (transistors) of reference voltage generation circuits according to the second and third embodiments shown in  FIGS. 7 and 9  can be reduced as compared with the reference voltage generation circuit according to the fifth comparison example shown in  FIG. 11 . 
     As described above, according to the reference voltage generation circuits according to the second and third embodiments, as the voltage V REFBI  is adjusted, any desired voltage V REF  and voltage V REFDC  can be generated based on the reference voltage V BGR . Also, according to the reference voltage generation circuits according to the second and third embodiments, the number of the elements is decreased, so that the voltage V REF  and the voltage V REFDC  less affected by the threshold voltage variations of the transistors can be output. Others are substantially similar to those of the first embodiment and duplicate description will not be given. 
     Other Embodiments 
     Although the invention has been described with the first to third embodiments, it is to be understood that the description and the drawings forming parts of the disclosure do not limit the invention. From the disclosure, various alternative embodiments, examples, and operational arts will be apparent to those skilled in the art. 
     In the first to third embodiments described above, the diodes D 121  to D 12   n  each equaling the first diode D 110  in energization area are connected in parallel to make up the second diode D 120  by way of example. However, the second diode D 120  may be a diode whose energization area is n times that of the first diode D 110 . 
     Thus, the invention contains various embodiments, etc., not described herein, of course. Therefore, the technical scope of the invention is to be determined solely by the inventive concepts which are delineated by the claims adequate from the description given above. 
     According to an aspect of the present invention, there is provided a reference voltage generation circuit that outputs a reference voltage less affected by the threshold voltage variations of transistors and that operates on a low power supply voltage.