Patent Publication Number: US-2023143543-A1

Title: Semiconductor device and method of manufacturing the semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application claims priority under 35 USC 119(a) to Korean Patent Application No. 10-2021-0151325 filed on Nov. 5, 2021 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. 
     TECHNICAL FIELD 
     The present inventive concept relates to a semiconductor device and a method of manufacturing the semiconductor device. 
     DISCUSSION OF THE RELATED ART 
     Field effect transistors (FET) have been developed to be more highly integrated. For example, a FinFET having a three-dimensional structure has been developed. 
     The FinFET device has a structure capable of reducing the short channel effect that may be experienced in other FETs. The FinFET device includes an active region having a fin shape. Since the channel region is formed in the fin-shaped active region, the FinFET device may have a suitable channel having its width bound within a relatively small horizontal region, as compared to the related art planar transistor. Therefore, the FinFET device may be scalable and capable of achieving a high performance, as compared to the related art planar transistor of a similar size, and thus, FinFET devices have been applied to various low-power/high-performance applications. 
     SUMMARY 
     A semiconductor device includes an active fin protruding from a substrate and extending in a first direction. A device isolation layer defines the active fin in the substrate and covers a portion of a side surface of the active fin. A plurality of gate structures intersect the active fin and extend in a second direction, perpendicular to the first direction. Each of the plurality of gate structures includes a gate and gate spacers on side surfaces of the gate. A plurality of epitaxial layers is disposed on the active fin, on opposite sides of the gate structure and includes a first epitaxial layer providing a drain region and a second epitaxial layer providing a source region. The gate spacers include a first spacer disposed between the first epitaxial layer and the gate. The first spacer includes a first region extending in a third direction, perpendicular to an upper surface of the substrate, along a side surface of the gate, and a second region extending from a lower portion of the first region in a direction away from the gate. 
     A semiconductor device includes an active fin protruding from a substrate and extending in a first direction. A device isolation layer defines the active fin in the substrate and covers a portion of a side surface of the active fin. A plurality of gate structures intersect the active fin and extend in a second direction, perpendicular to the first direction. A first epitaxial layer is disposed on a first recess region of the active fin, outside of a first gate structure, among the plurality of gate structures. A second epitaxial layer is disposed on a second recess region of the active fin, outside of a second gate structure, among the plurality of gate structures. One or more third epitaxial layers are disposed on one or more third recess regions on the active fin, between the first gate structure and the second gate structure. Each of the plurality of gate structures includes a gate and gate spacers on side surfaces of the gate. Among the gate spacers, a first gate spacer in contact with the first epitaxial layer includes a first region extending in a third direction, perpendicular to an upper surface of the substrate, and a second region bent from a lower portion of the first region and extending toward the first epitaxial layer. A length of the first epitaxial layer in the first direction is shorter than a length of the one or the plurality of third epitaxial layers in the first direction. 
     A semiconductor device includes an active fin protruding from a substrate and extending in a first direction. A device isolation layer defines the active fin in the substrate and covers a portion of a side surface of the active fin. A first gate structure intersects the active fin and extends in a second direction, perpendicular to the first direction. A first dummy gate structure extends in the second direction and is adjacent to the first gate structure. A first epitaxial layer is disposed on a first recess region of the active fin, between the first gate structure and the first dummy gate structure. The first gate structure includes a first gate, and a first gate spacer disposed on one side surface adjacent to the first dummy gate structure, among side surfaces of the first gate. The first gate spacer includes a first region extending in a third direction, perpendicular to an upper surface of the substrate, and a second region extending from a lower portion of the first region toward the first dummy gate structure. The first epitaxial layer is disposed between the dummy gate structure and the second region. 
     A method of manufacturing a semiconductor device includes forming an active fin on a substrate. A sacrificial gate structure including a sacrificial gate pattern and gate spacers, intersecting the active fin, is formed. Recess regions are formed in the active fin, on opposite sides of the sacrificial gate structure. Epitaxial layers are formed on the recess regions of the active fin. An opening is formed by removing the sacrificial gate pattern. A gate structure is formed by depositing a gate dielectric layer and a gate electrode in the opening. Contacts connected to the epitaxial layers are formed. The forming of the sacrificial gate structure includes forming the sacrificial gate pattern on the active fin, forming an insulating spacer on the sacrificial gate pattern on the active fin, forming a photoresist on the insulating spacer, removing the photoresist, while leaving a region in which an offset is to be formed in the insulating spacer, and etching the insulating spacer to form the gate spacers. 
     A method of manufacturing a semiconductor device includes forming a first active fin on a low voltage region and a second active fin on a high voltage region. A first sacrificial gate pattern intersecting the first active fin is formed. A second sacrificial gate pattern intersecting the second active fin is formed. A first insulating spacer is formed on opposite sides of the first sacrificial gate pattern. A second insulating spacer is formed on opposite sides of the second sacrificial gate pattern. A photoresist is formed on the first and second insulating spacers. After leaving the photoresist on a portion of the second insulating spacer, the first and second insulating spacers are etched and the second insulating spacer is formed as a gate spacer having an offset region on at least one side of the second sacrificial gate pattern in the high voltage region. First recess regions are formed by etching the first active fin from opposite sides of the first sacrificial gate pattern and second recess regions by etching the second active fin from opposite sides of the second sacrificial gate pattern. First epitaxial layers are formed on the first recess regions and second epitaxial layers are formed on the second recess regions by performing an epitaxial growth process and an in-situ doping process of doping an impurity element. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The above and other aspects and features of the present inventive concept will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: 
         FIG.  1    is a schematic plan view of a semiconductor device according to example embodiments; 
         FIG.  2 A  is a schematic cross-sectional view of a semiconductor device according to example embodiments; 
         FIG.  2 B  is a schematic cross-sectional view of a semiconductor device according to example embodiments; 
         FIG.  3    is a partially enlarged view of a semiconductor device according to example embodiments; 
         FIGS.  4  to  6    are schematic cross-sectional views of semiconductor devices according to example embodiments; 
         FIGS.  7 A and  7 B  are schematic cross-sectional views of a semiconductor device according to example embodiments; 
         FIGS.  8 A to  8 C  are schematic cross-sectional views of semiconductor devices according to example embodiments; 
         FIGS.  9 A and  9 B  are flowcharts illustrating a method of manufacturing a semiconductor device according to a process sequence according to example embodiments; 
         FIGS.  10 A,  10 B,  11 ,  12 ,  13 A,  13 B,  14 A,  14 B,  15 A,  15 B, and  16    are diagrams illustrating a process sequence to illustrate a method of manufacturing a semiconductor device according to example embodiments; 
         FIG.  17    is an exploded perspective view illustrating a CMOS image sensor including transistors of a semiconductor device according to example embodiments; 
         FIG.  18    is a diagram schematically illustrating a substrate structure in which transistors of a semiconductor device are formed, according to example embodiments; and 
         FIG.  19    is a flowchart illustrating a process sequence to illustrate a method of manufacturing a semiconductor device according to example embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, example embodiments will be described with reference to the accompanying drawings. 
       FIG.  1    is a schematic plan view of a semiconductor device according to example embodiments. 
       FIGS.  2 A and  2 B  are schematic cross-sectional views of a semiconductor device according to example embodiments.  FIG.  2 A  illustrates a cross section of the semiconductor device of  FIG.  1    taken along line I-I′, and  FIG.  2 B  illustrates cross sections of the semiconductor device of  FIG.  1    taken along lines II-IT and 
       FIG.  3    is a partially enlarged view of a semiconductor device according to example embodiments.  FIG.  3    illustrates an enlarged view of area ‘A’ of  FIG.  2 A . 
     Referring to  FIGS.  1  to  3   , a semiconductor device  100  may include a substrate  101 , an active fin  105  extending in the first direction X on the substrate  101 , gate structures  130 G extending in the second direction Y to intersect the active fin  105 , and epitaxial layers  150  disposed on the active fin  105 , on opposite sides of the gate structures  130 G. The semiconductor device  100  may further include a device isolation layer  110  defining the active fin  105  in the substrate  101 , dummy gate structures  130 D disposed side by side with the gate structures  130 G, contacts  161  and  162  connected to at least some of the epitaxial layers  150 , and interlayer insulating layers  172  and  174 . 
     The semiconductor device  100  may include FinFET devices which are transistors in which the active fin  105  has a fin-shaped structure. The FinFET devices may include transistors disposed around the active fin  105  and the gate structure  130 G that intersect each other. For example, the semiconductor device  100  may include NMOS transistors and/or PMOS transistors. 
     The substrate  101  may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon (Si) and/or germanium (Ge), for example, silicon-germanium (SiGe). The substrate  101  may be provided as a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, or the like. 
     The device isolation layer  110  may define the active fin  105  on the substrate  101 . The device isolation layer  110  may be formed by, for example, a shallow trench isolation (STI) process. In some embodiments, the device isolation layer  110  may also include a region extending deeper into a lower portion of the substrate  101  than in comparative arrangements. The device isolation layer  110  may have a curved upper surface having a higher level as it approaches the active fin  105 , but the shape of the upper surface of the device isolation layer  110  is not necessarily limited thereto. The device isolation layer  110  may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, and/or silicon oxycarbide. 
     The active fins  105  are defined by the device isolation layer  110  in the substrate  101  and may extend in a first direction (e.g., the X-direction). The active fin  105  may have a structure protruding from the substrate  101 . The upper end of the active fin  105  may protrude to a predetermined height from the upper surface of the device isolation layer  110 . The active fin  105  may be formed as a portion of the substrate  101  or may include an epitaxial layer grown from the substrate  101 . However, on opposite sides of the gate structure  130 G, the active fin  105  on the substrate  101  may be partially recessed, and epitaxial layers  150  may be disposed on the recessed active fin  105 . In some embodiments, the active fins  105  may be disposed in plurality and the active fins of the plurality of active fins  105  may be spaced apart from each other in the second direction (e.g., Y direction). 
     The gate structure  130 G may intersect the active fin  105  and may extend in the second direction Y. A channel region of a transistor may be formed in the active fin  105  intersecting the gate structure  130 G. The gate structure  130 G may include a gate  135 G, gate spacers  134  on opposite sides of the gate  135 G, and a gate capping layer  138 G on the gate  135 G. The gate  135 G may include a gate dielectric layer  131 G disposed on the active fin  105  and a gate electrode  133 G disposed on the gate dielectric layer  131 G. 
     The gate dielectric layer  131 G may be disposed between the active fin  105  and the gate electrode  133 G. The gate dielectric layer  131 G may cover at least a portion of the surfaces of the gate electrode  133 G, and for example, the gate dielectric layer  131 G may surround all surfaces except for an uppermost surface of the gate electrode  133 G. The gate dielectric layer  131 G may include silicon oxide, silicon nitride, or a high-k material. The high-k material may refer to a dielectric material having a higher dielectric constant than silicon oxide. The high-k material may be, for example, aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), and/or praseodymium oxide (Pr 2 O 3 ). In an illustrative embodiment, the thickness of the gate dielectric layer  131 G may range from about 1.5 nm to about 10 nm, and the semiconductor device  100  may include a transistor having a relatively thick oxide layer. 
     The gate electrode  133 G may be spaced apart from the active fin  105  with the gate dielectric layer  131 G interposed therebetween. The gate electrode  133 G may include a plurality of metal layers. The gate electrode  133 G may include a conductive material, for example, W, Ti, Ta, Mo, TiN, TaN, WN, TiON, TiAlC, TiAlN, and/or TaAlC. The gate electrode  133 G may include a semiconductor material such as doped polysilicon. 
     The gate spacers  134  may be disposed on opposite sides of the gate  135 G. The gate spacers  134  may include portions having a curved outer surface such that the width of the upper portion is smaller than the width of the lower portion, but the configuration is not necessarily limited thereto. The gate spacers  134  may electrically insulate the epitaxial layers  150  from the gate  135 G. Each of the gate spacers  134  may have a multilayer structure. The gate spacers  134  may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, and/or silicon oxycarbide. 
     The gate spacers  134  may include drain spacers  134   a _D and  134   b _D and source spacers  134   a _S and  134   b _S. The drain spacers  134   a _D and  134   b _D may be disposed on opposite sides of one first gate  135 G and may be provided as a pair, and the source spacers  134   a _S and  134   b _S may be disposed on opposite sides of one second gate  135 G and may be provided as a pair. The pair of drain spacers  134   a _D and  134   b _D may form an asymmetrical structure, and the pair of source spacers  134   a _S and  134   b _S may also form an asymmetrical structure, but the present inventive concept is not necessarily limited thereto. 
     The pair of drain spacers  134   a _D and  134   b _D may include a first spacer  134   a _D and a second spacer  134   b _D disposed on opposite sides of the first gate  135 G, and the first spacer  134   a _D may have a shape different from that of the second spacer  134   b _D. The first spacer  134   a _D may be disposed between a first epitaxial layer  150 (D) serving as the drain region  150 (D) and the first gate  135 G. The second spacer  134   b _D may be disposed on a second side opposite to a first side of the first gate  135 G in contact with the first spacer  134   a _D. The first spacer  134   a _D may include a first region  134   a   1  extending in a third direction Z perpendicular to the upper surface of the substrate  101  along a side surface of the first gate  135 G, and a second region  134   a   2  extending from a lower portion of the first region  134   a   1  in a direction away from the first gate  135 G. The first spacer  134   a _D may include a bent portion between the first region  134   a   1  and the second region  134   a   2 . The second region  134   a   2  may extend toward the first epitaxial layer  150 (D). The second region  134   a   2  may be disposed at a lower level (relative to the substrate  101  which may be considered the lowest level) than the first region  134   a   1 . A length d 1  of the second region  134   a   2  in the first direction X may range from about 1 nm to about 50 nm, for example, from about 25 nm to about 35 nm. The first region  134   a   1  may have a predetermined thickness ds in the first direction X, and the thickness ds may be substantially equal to or similar to the length d 1  of the second region  134   a   2 . 
     The pair of source spacers  134   a _S and  134   b _S may include a third spacer  134   a _S and a fourth spacer  134   b _S disposed on opposite sides of the second gate  135 G. The pair of drain spacers  134   a _D and  134   b _D may have mirror symmetry with the pair of source spacers  134   a _S and  134   b _S. Accordingly, the pair of source spacers  134   a _S and  134   b _S may have a structure similar to that of the pair of drain spacers  134   a _D and  134   b _D. For example, the third spacer  134   a _S may have a shape different from that of the fourth spacer  134   b _S. The third spacer  134   a _S may include a third region  134   a   3  extending in the third direction Z along a side surface of the second gate  135 G, and a fourth region  134   a   4  extending from a lower portion of the third region  134   a   3  in a direction away from the second gate  135 G. The third spacer  134   a _D may be disposed between a second epitaxial layer  150 (S) serving as the source region  150 (S) and the second gate  135 G. 
     Commercially available FinFET devices may have a relatively low operating voltage of 0.7V to 1V. Analog devices such as Input/Output (I/O) devices are driven by a high voltage such as 3.3V. In the case in which the high voltage as described above is applied to the FinFET device, deterioration of hot carrier properties due to a high electric field in the drain region, and an increase in leakage current such as Gate Induced Drain Leakage (GIDL) may be caused. 
     Gate Induced Drain Leakage (GIDL) may occur when a voltage difference between the gate and drain regions of the FET in the off state is relatively large. When the channel length is reduced, a maximum electric field applied to the carriers in the drain region overlapping the gate increases, and as carriers move from the source region to the drain region, a kinetic energy large enough to cause impact ionization in the high electric field region of the drain junction is obtained. Some of these carriers may cross the barrier of the Si—SiO 2  interface and enter the oxide film. Carriers with energy greater than this high thermal energy might no longer be in thermal equilibrium with the lattice, and such carriers are referred to as hot carriers, and such hot carriers and GIDL are closely related to the magnitude of the maximum E-field. 
     In the case of the FinFET structure of the related art, since the distance between the drain region and the source region is relatively short, the magnitude of the electric field (E-field) applied between the source region and the drain region may increase, and as the electric field in the horizontal direction increases, tunneling occurs in which electrons pass to the other band, and thus, there may be a problem with hot carrier and GIDL occurring. 
     According to an example embodiment of the present inventive concept, in a FinFET device to which a relatively high voltage is applied, by providing an offset between the drain region  150 (D) and the gate  135 G, for example, the second region  134   a   2  of the first spacer  134   a , the drain region  150 (D) and the gate  135 G may be further spaced apart from each other by an offset distance d 1 . Therefore, the overlap region in which the drain region  150 (D) and the gate  135 G overlap may be reduced, and a maximum electric field of the channel may be reduced. In detail, GIDL and hot carrier generation by the maximum electric field in a transistor to which a high voltage is applied is higher than the generation by the maximum electric field in the transistor to which the low voltage is applied, and thus, the magnitude of the maximum electric field in a transistor to which a high voltage is applied is reduced. Since the maximum electric field of the channel in the transistor to which a high voltage is applied may be reduced, the tunneling probability may be reduced, and thus, GIDL current and hot carrier generation may be reduced or significantly decreased. Accordingly, in a semiconductor device in which an analog device such as an Input/Output (I/O) device to which a relatively high voltage is applied is implemented as a FinFET device, the transistor may more effectively be turned-off and reliability of the transistor may be increased. 
     The gate capping layer  138 G may be disposed on the gate  135 G, and a lower surface and side surfaces thereof may be surrounded by the gate  135 G and the gate spacers  134 , respectively. The gate capping layer  138 G may include, for example, silicon nitride, and/or silicon oxynitride. In an example embodiment, the gate capping layer  138 G may fill a region in which the gate  135 G and the gate spacers  134  have been partially removed from the upper portion. 
     The dummy gate structures  130 D may cover an end of the active fin  105  in the first direction X and may be disposed in parallel with the gate structures  130 G. The dummy gate structures  130 D may include a dummy gate  135 D including a dummy gate dielectric layer  131 D and a dummy gate electrode  133 D, a dummy gate capping layer  138 D on the dummy gate  135 D, and gate spacers  134 . Components constituting the dummy gate structures  130 D may be at least similar to components constituting the gate structures  130 G. 
     The epitaxial layers  150  may be disposed on opposite sides of the channel region of the active fin  105  intersecting the gate structure  130 G. The epitaxial layers  150  may be disposed by partially recessing the upper portion of the active fin  105  on opposite sides of the gate structure  130 G. However, in example embodiments, the presence or absence of the recess and the depth of the recess may be variously changed. The epitaxial layers  150  may serve as a source region or a drain region of the transistors. The epitaxial layers  150  may have a mutually connected and merged shape on a plurality of active fins  105  adjacent in the second direction Y, but the configuration is not necessarily limited thereto. The epitaxial layers  150  may have angled side surfaces in a cross-section in the second direction Y. However, in example embodiments, the epitaxial layers  150  may have various shapes, for example, polygonal, circular, oval, and/or rectangular shapes. 
     The epitaxial layers  150  may include silicon (Si), for example, silicon germanium (SiGe), or silicon carbide (SiC). The epitaxial layers  150  may be formed of a plurality of layers including different concentrations of elements and/or doping elements. The epitaxial layers  150  may include silicon (Si) doped with a pentavalent N-type impurity element including phosphorus (P), arsenic (As), bismuth (Bi), and/or antimony (Sb). The epitaxial layers  150  may also include silicon germanium (SiGe) doped with a trivalent P-type impurity element including boron (B), indium (In), and/or gallium (Ga). 
     For example, to provide a channel region having a relatively longer channel length, the semiconductor device  100  may include a transistor in which the first epitaxial layer  150 (D) is a drain region and the second epitaxial layer  150 (S) is a source region. The epitaxial layers  150  may include a first epitaxial layer  150 (D) disposed on the first recess region of the active fin  105  outside the first gate structure  130 G, a second epitaxial layer  150 (S) disposed on the second recess region of the active fin  105  outside the second gate structure  130 G, and one or a plurality of third epitaxial layers  150  disposed on one or a plurality of third recess regions of the active fin  105 , between the first and second gate structures  130 G. The first epitaxial layer  150 (D) may be in contact with the first spacer  134   a _D, and may be disposed between the first dummy gate structure  130 D, adjacent to the first gate structure  130 G, and the first gate structure  130 G. The second epitaxial layer  150 (S) may be in contact with the third spacer  134   a _S, and may be disposed between the second dummy gate structure  130 D adjacent to the second gate structure  130 G and the second gate structure  130 G. 
     The pitch of the gate pattern structures including the gate structures  130 G and the dummy gate structures  130 D in the first direction X may be constant. The gate pattern structures have a constant pitch, but include a region in which a portion  134   a _D or  134   a _S of the gate spacers  134  is offset, and thus, a portion  150 (D) or  150 (S) of the epitaxial layers  150  may have a smaller length in the first direction X than other epitaxial layers  150 . For example, at least one of the one or the plurality of third epitaxial layers  150  between the gate structures  130 G may have a first length L 1  in a first direction X, and the first epitaxial layer  150 (D) may have a second length L 2  that is shorter than the first length L 1  in the first direction X. The second epitaxial layer  150 (S) may also have a third length L 3  shorter than the first length L 1  in the first direction X. The second length L 2  and the third length L 3  may be substantially the same as each other, but are not necessarily limited thereto. The first epitaxial layer  150 (D) and the second epitaxial layer  150 (S) may have a mirror-symmetric structure with respect to the center of one or the plurality of third epitaxial layers  150 , but the present inventive concept is not necessarily limited thereto. 
     The contacts  161  and  162  may pass through the interlayer insulating layers  172  and  174  and an insulating liner to be connected to the epitaxial layers  150 . The contacts  161  and  162  may apply an electrical signal to the epitaxial layers  150 . Each of the contacts  161  and  162  may include barrier layers  161   a  and  162   a  and metal layers  161   b  and  162   b . The barrier layers  161   a  and  162   a  may surround lower surfaces and side surfaces of the metal layers  161   b  and  162   b . The barrier layers  161   a  and  162   a  may include a metal nitride, for example, titanium nitride (TiN), tantalum nitride (TaN), and/or tungsten nitride (WN). The metal layers  161   b  and  162   b  may include a metal material, for example, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), and/or molybdenum (Mo). According to an example embodiment, the barrier layers  161   a  and  162   a  may be omitted. 
     A metal-semiconductor compound layer may be further disposed between the contacts  161  and  162  and the epitaxial layers  150 . The metal-semiconductor compound layer may include, for example, metal silicide, metal germanide, or metal silicide-germanide. In the metal-semiconductor compound layer, the metal may be titanium (Ti), nickel (Ni), tantalum (Ta), cobalt (Co), or tungsten (W), and the semiconductor is silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, the metal-semiconductor compound layer may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), and/or tungsten silicide (WSi). 
     The contacts  161  and  162  may include a first contact  161  connected to the first epitaxial layer  150 (D) serving as the drain region  150 (D), and a second contact  162  connected to the second epitaxial layer  150 (S) serving as the source region  150 (S). A driving voltage VDD in a range of about 1.2 V to about 50 V may be applied to the first contact  161 . In an illustrative embodiment, a driving voltage VDD in the range of about 3.3 V or about 3.1 V to about 3.5 V may be applied to the first contact  161 . 
     The interlayer insulating layers  172  and  174  may be disposed on the epitaxial layers  150  and the gate structure  130 G. The interlayer insulating layers  172  and  174  may include a first interlayer insulating layer  172  and a second interlayer insulating layer  174  on the first interlayer insulating layer  172 . The first interlayer insulating layer  172  may be disposed on side surfaces of the gate structures  130 G, and the second interlayer insulating layer  174  may be disposed on the gate structures  130 G and the dummy structures  130 D. The first interlayer insulating layer  172  may also be disposed on the upper surface of the device isolation layer  110  not covered by the gate structure  130 G. The interlayer insulating layers  172  and  174  may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and/or silicon oxycarbide. The interlayer insulating layers  172  and  174  may also include a plurality of insulating layers. 
     An insulating liner may be further disposed below the interlayer insulating layers  172  and  174 . The insulating liner covers the upper surface of the device isolation layer  110  that does not overlap the gate structure  130 G, and may extend onto the epitaxial layers  150 . An insulating liner may extend over the sides of the gate structure  130 G. The insulating liner may include, for example, silicon oxide, silicon nitride, and/or silicon oxynitride. 
       FIGS.  4  to  6    are schematic cross-sectional views of semiconductor devices according to example embodiments.  FIGS.  4  to  6    illustrate regions corresponding to  FIG.  2 A . In the example embodiments of  FIGS.  4  to  6   , to the extent that a description of an element has been omitted, that element may be understood to be at least similar to a corresponding element of  FIG.  2 A . 
     Referring to  FIG.  4   , in a semiconductor device  100 A, the first spacer  134   a _D in contact with the first epitaxial layer  150 (D) is offset to include a second region  134   a   2 , and the third spacer  134   a _S in contact with the second epitaxial layer  150 (S) might not be offset. In this case, the drain spacers  134   a _D and  134   b _D form an asymmetrical structure with each other, and the drain spacers  134   a _D and  134   b _D may form a symmetric structure with the source spacers  134   a _S and  134   b _S. 
     Referring to  FIG.  5   , in a semiconductor device  100 B, the offset distance of the first spacer  134   a _D in contact with the first epitaxial layer  150 (D) may be different from the offset distance of the third spacer  134   a _S in contact with the second epitaxial layer  150 (S). For example, an offset distance d 1  of the second region  134   a   2  of the first spacer  134   a _D in the first direction X may be greater than an offset distance d 2   a  of the fourth region  134   a   4  of the third spacer  134   a _S in the first direction X. Accordingly, a length L 2  of the first epitaxial layer  150 (D) in the first direction X may be shorter than a length L 3   a  of the second epitaxial layer  150 (S) in the first direction X. 
     Referring to  FIG.  6   , in a semiconductor device  100 C, both the first spacer  134   a _D and the second spacer  134   b _D forming a pair on opposite sides of the first gate  135 G are offset to have a bent lower shape, and both the third spacer  134   a _S and the fourth spacer  134   b _S forming a pair on opposite sides of the second gate  135 G may be offset to have a bent lower shape. In this case, the epitaxial layers  150  disposed on opposite sides of each of the first and second gates  135 G may have relatively reduced lengths L 1 ′ and L 2  in the X direction. 
       FIGS.  7 A and  7 B  are schematic cross-sectional views of a semiconductor device according to example embodiments.  FIG.  7 A  illustrates the region corresponding to  FIG.  2 A , and  FIG.  7 B  illustrates the region corresponding to  FIG.  2 B . 
     Referring to  FIGS.  7 A and  7 B , a semiconductor device  200  may further include a plurality of channel layers  240  disposed to be vertically spaced apart from each other on an active fin  205 , and inner spacers  220  disposed in parallel with a gate  235 G, between the plurality of channel layers  240 . The semiconductor device  200  may include a gate-all-around type of transistors in which the gate  235 G is disposed between the active fin  205  and the channel layers  240  and between the plurality of channel layers  240  having a nano-sheet shape. For example, the semiconductor device  200  may include transistors of a Multi Bridge Channel FET (MBCFET™) structure formed by channel layers  240 , epitaxial layers  250 , and a gate  235 G. 
     The plurality of channel layers  240  may be disposed as two or more, for example, a plurality of channel layers on the active fin  205  to be spaced apart from each other in a direction (Z direction) perpendicular to the upper surface of the active fin  205 . The channel layers  240  may be spaced apart from the upper surface of the active fin  205 , while being connected to the epitaxial layers  250 . The channel layers  240  may have the same or similar width as the active fin  205  in the second direction Y, and may have the same width as or similar width to that of the gate  235 G in the first direction X. However, in some embodiments, the channel layers  240  may have a reduced width such that side surfaces are positioned below the gate  235 G in the first direction X. 
     The plurality of channel layers  240  may be formed of a semiconductor material, and may include, for example, silicon (Si), silicon germanium (SiGe), and/or germanium (Ge). The channel layers  240  may be formed of, for example, the same material as the substrate  101 . The number and shape of the channel layers  240  constituting one channel structure may be variously changed in example embodiments. 
     The gate structure  230 G may be disposed on the active fin  205  and the plurality of channel layers  240  to extend while intersecting the active fin  205  and the plurality of channel layers  240 . Channel regions of transistors may be formed in the active fin  205  and the plurality of channel layers  240  intersecting the gate structure  230 G. In this embodiment, a gate dielectric layer  231 G may be disposed not only between the active fin  205  and the gate electrode  233 G, but also between the plurality of channel layers  240  and the gate electrode  233 G. The gate electrode  233 G may be disposed on the active fin  205  to fill a space between the plurality of channel layers  240  and to extend over the plurality of channel layers  240 . The gate electrode  233 G may be spaced apart from the plurality of channel layers  240  with the gate dielectric layer  231 G interposed therebetween. 
     The inner spacers  220  may be disposed in parallel with the gate  235 G, between the plurality of channel layers  240 . The gate  235 G may be spaced apart from the epitaxial layers  250  with the inner spacers  220  disposed therebetween, to electrically separate the gate  235 F from the epitaxial layers  250 . The inner spacers  220  may have a flat side surface facing the gate  235 G or may have an inwardly convexly rounded shape that is inwardly convex toward the gate  235 G. The inner spacers  220  may include silicon oxide, silicon nitride, and/or silicon oxynitride. The inner spacers  220  may be omitted in some embodiments. 
       FIGS.  8 A to  8 C  are schematic cross-sectional views of semiconductor devices according to example embodiments. 
     Referring to  FIG.  8 A , a semiconductor device  300 A may include a first spacer  334   a  and a second spacer  334   b  disposed on opposite sides of one gate  335 G and offset in a direction away from the gate  335 G. One of the epitaxial layers  350  disposed on opposite sides of one gate  335 G may serve as the source region  350 (S), and the other may serve as the drain region  350 (D). The first spacer  334   a  may include a first region  334   a   1 , and a second region  334   a   2  extending from a lower portion of the first region  334   a   1  in a direction away from the gate  335 G. The second spacer  334   b  may include a third region  334   b   1 , and a fourth region  334   b   2  extending from a lower portion of the third region  334   b   1  in a direction away from the gate  335 G. An offset distance D 1  of the second region  334   a   2  in the first direction X may be substantially the same as an offset distance D 2  of the fourth region  334   b   2  in the first direction X. 
     Referring to  FIG.  8 B , a semiconductor device  300 B is similar to the semiconductor device  600 A of  FIG.  7 A , but the offset distance D 1  of the second region  334   a   2  may be greater than the offset distance D 2   a  of the fourth region  334   b   2 . The first spacer  334   a  and the second spacer  334   b  may provide an asymmetrical structure. 
     Referring to  FIG.  8 C , a semiconductor device  300 C is similar to the semiconductor device  300 A of  FIG.  7 A , but the second spacer  334   b  does not provide an offset, and only the first spacer  334   a  might provide an offset second region  334   a   2 . 
       FIGS.  9 A and  9 B  are flowcharts illustrating a method of manufacturing a semiconductor device according to an example embodiment according to a process sequence. 
       FIGS.  10 A to  16    are diagrams illustrating a process sequence to illustrate a method of manufacturing a semiconductor device according to example embodiments. 
     Referring to  FIGS.  9 A to  13 B , an active fin  105  is formed on a substrate  101  (S 10 ), and a sacrificial gate structure including a sacrificial gate pattern  115  and gate spacers  134 , intersecting the active fin  105 , may be formed (S 20 ). 
     Forming the sacrificial gate structure (S 20 ) may include forming a sacrificial gate pattern  115  (S 21 ), forming an insulating spacer ( 134 P) (S 22 ), forming a photoresist  118  on the insulating spacer  134 P (S 23 ), removing the photoresist  118  while leaving a region OS in which an offset is to be formed in the insulating spacer  134 P (S 24 ), and forming gate spacers  134  by etching the insulating spacer  134 P (S 25 ). 
     First, the substrate  101  is patterned to form a trench defining the active fin  105 , and an insulating material fills the region from which a portion of the substrate  101  has been removed, to then be recessed such that the active fin  105  protrudes, thereby forming the device isolation layer  110 . The upper surface of the device isolation layer may be lower than the upper surface of the active fin  105 . The active fins  105  may have a form protruding further than the upper surface of the device isolation layer  110 . 
     Next, as illustrated in  FIGS.  10 A and  10 B , the sacrificial gate pattern  115  may be formed on the active fin  105  (S 21 ). The sacrificial gate pattern  115  may be a sacrificial structure formed in a region in which the gate electrode  133 G is disposed on the active fin  105  as illustrated in  FIG.  2    through a subsequent process. The sacrificial gate pattern  115  may intersect the active fin  105  and extend in the second direction (e.g., the Y direction). The sacrificial gate pattern  115  may include first and second sacrificial gate layers  111  and  112  and a mask pattern layer  113  sequentially stacked on the substrate  101 . The first and second sacrificial gate layers  111  and  112  may be patterned using the mask pattern layer  113 . The first and second sacrificial gate layers  111  and  112  may be an insulating layer and a conductive layer, respectively, but are not necessarily limited thereto, and the first and second sacrificial gate layers  111  and  112  may be formed together as a single layer. For example, the first sacrificial gate layer  111  may include silicon oxide, and the second sacrificial gate layer  112  may include polysilicon. The mask pattern layer  113  may include silicon oxide, silicon nitride, and/or silicon oxynitride. 
     Next, as illustrated in  FIG.  11   , an insulating spacer  134 P may be formed on the active fin  105  and the sacrificial gate pattern  115  (S 22 ). The insulating spacer  134 P may be formed by depositing a film having a uniform thickness along the upper and side surfaces of the active fin  105  and the upper and side surfaces of the sacrificial gate pattern  115 . 
     Next, as illustrated in  FIG.  12   , the photoresist  118  may be formed on the insulating spacer  134 P (S 23 ). 
     Next, as illustrated in  FIG.  13 A , an exposure process may be performed using a separate photomask to leave an offset region OS on the insulating spacer  134 P and to remove the photoresist  118  (S 24 ). The photoresist  118  may be removed from the area other than the offset region OS by performing an exposure process on the area other than the offset region OS. Alternatively, an exposure process may be performed on the offset region OS, and the photoresist  118  may be removed from a region other than the offset region OS. In  FIG.  13 A , the remaining photoresist  118  may be offset and disposed on one side of the sacrificial gate pattern  115 , and may partially overlap the sacrificial gate pattern  115  on the upper portion of the sacrificial gate pattern  115 . In  FIG.  13 B , an offset region OS&#39; may be formed relatively large, and the remaining photoresist  118  may be disposed on opposite sides of the sacrificial gate pattern  115  and may overlap the sacrificial gate pattern  115  in a vertical direction. 
     Thereafter, with reference to  FIG.  14 A  below together, as illustrated in  FIG.  14 A , the insulating spacer  134 P may be formed as the gate spacers  134  by performing an anisotropic etching process (S 25 ). When performing the anisotropic etching process, the photoresist  118  on the offset region OS serves as a mask, and thus, an offset bent from a lower portion in a direction away from the sacrificial gate pattern  115  may be formed on the first spacer  134   a _D and the third spacer  134   a _S. Each of the first spacers  134   a _D and the third spacers  134   a _S may partially remain on the upper surface of the sacrificial gate pattern  115 , but may be removed in a subsequent process. 
     Referring to  FIGS.  9 A,  14 A, and  14 B , recess regions RS may be formed in the active fin  105  on opposite sides of the sacrificial gate structure (S 30 ). 
     The active fin  105  may be partially etched on opposite sides of the sacrificial gate structure to form the recess regions RS. An etching process may be performed using the spacers  134   a _D and  134   a _S as an etch mask together with the sacrificial gate pattern  115 . Due to the offset region OS, some recess regions RS may have a shorter length in the first direction X than other recess regions RS. The recess regions RS may be formed by removing a predetermined depth downwardly from the upper end of the active fin  105 . The etch depth of the recess regions RS and the shape of the lower end of the recess regions RS are not necessarily limited to the illustration in the drawings, and may be variously changed according to example embodiments. 
     Referring to  FIGS.  9 A,  15 A, and  15 B , epitaxial layers  150  including source/drain regions may be formed on the recess regions RS of the active fin  105  (S 40 ). 
     The epitaxial layers  150  may be formed by performing an epitaxial growth process on the recess regions RS. The epitaxial layers  150  may include impurities by in-situ doping, and may also include a plurality of layers having different doping elements and/or doping concentrations. 
     Referring to  FIGS.  9 A and  16   , a first interlayer insulating layer  172  may be formed, and an opening OP may be formed by removing the sacrificial gate pattern  115  (S 50 ). 
     First, an insulating film may be formed on the sacrificial gate structure and the epitaxial layers  150 , and the first interlayer insulating layer  172  may be formed by performing a planarization process so that the upper surface of the mask pattern layer  113  is exposed. Before forming the first interlayer insulating layer  172 , an insulating liner may be conformally formed. 
     Next, the opening OP may be formed by removing the first and second sacrificial gate layers  111  and  112  and the mask pattern layer  113 . The first and second sacrificial gate layers  111  and  112  and the mask pattern layer  113  may be selectively removed with respect to the gate spacers  134  and the first interlayer insulating layer  172 . 
     Referring to  FIGS.  9 A,  2 A, and  2 B , a gate structure  130  may be formed by depositing a gate dielectric layer  131  and a gate electrode  133  in the opening OP (S 60 ), and contacts  161  and  162  connected to epitaxial layers including source/drain regions may be formed (S 70 ). 
     The gate dielectric layer  131  may conformally cover the upper surface of the active fin  105  and the gate spacers  134  in the opening OP. Forming the gate electrode  133  may include sequentially forming a plurality of metal layers on the gate dielectric layer  131 . Accordingly, the gate structure  130  including the gate electrode  133 , the gate dielectric layer  131 , and the gate spacers  134  may be formed. In this operation, a dummy gate structure  130 D may be formed together with the gate structure  130 . 
     The contacts may be formed by forming a contact opening exposing the epitaxial layers  150  by penetrating through the interlayer insulating layer  172  and then depositing a conductive material in the contact opening. 
       FIG.  17    is an exploded perspective view illustrating a CMOS image sensor including transistors of a semiconductor device according to example embodiments. 
     Referring to  FIG.  17   , an image sensor  1000  may be a stacked image sensor including a first substrate SUB 1  and a second substrate SUB 2  stacked in a vertical direction. The first substrate SUB 1  may include a sensing area SA and a first pad area PA 1 , and the second substrate SUB 2  may include a circuit area CA and a second pad area PA 2 . The sensing area SA may include a plurality of pixels PX arranged in a plurality of row lines and a plurality of column lines. The first pad area PA 1  includes a plurality of first pads PAD 1 , and the plurality of first pads PAD 1  may be configured to transmit and receive electrical signals with the circuit area CA of the second substrate SUB 2  and the second pad area PA 2 . The circuit area CA may include a logic circuit block LC, and may include a plurality of circuit elements constituting a row driver, a read-out circuit, a column driver, and the like. The circuit area CA may provide a plurality of control signals to the sensing area SA to control outputs from the plurality of pixels PX. 
     The first pads PAD in the first pad area PA 1  may be electrically connected to the second pads PAD 2  in the second pad area PA 2  by a connection portion CV. The structure of the image sensor  1000  is not necessarily limited to that illustrated in  FIG.  16    and may be variously modified according to example embodiments. For example, the image sensor  1000  may further include at least one substrate provided below the second substrate SUB 2  and including a memory chip such as DRAM or SRAM. 
     According to an example, a transistor of a semiconductor device manufactured according to an example embodiment of the present inventive concept may be applied to the plurality of circuit elements in the circuit area CA included in the second substrate SUB 2  of the image sensor  1000 . According to an example, the semiconductor device manufactured according to the present inventive concept may be applied to an ADC converter, an RF device, an I/O device, and the like. However, application examples of the semiconductor device manufactured according to the present inventive concept are not necessarily limited thereto. 
       FIG.  18    is a diagram schematically illustrating a substrate structure in which transistors of a semiconductor device are formed, according to example embodiments. 
     Referring to  FIG.  18   , a substrate structure  2000  in which transistors of a semiconductor device according to example embodiments are formed may be a lower plate of a CMOS image sensor. The substrate structure  2000  may include, for example, a plurality of voltage regions  2100 ,  2200 ,  2300 , and  2400  to which different driving voltages are provided. Accordingly, the driving voltage applied to any one of the plurality of voltage regions  2100 ,  2200 ,  2300 , and  2400  may be higher or lower than the driving voltage applied to the other voltage region. The plurality of voltage regions  2100 ,  2200 ,  2300 , and  2400  may include a first voltage region  2100 , a second voltage region  2200 , a third voltage region  2300 , and a fourth voltage region  2400 . Each of the plurality of voltage regions  2100 ,  2200 ,  2300 , and  2400  may include a plurality of transistors. 
     In an example embodiment, the driving voltage of the plurality of first transistors disposed in the first voltage region  2100  may be about 0.8 V, or may range from about 0.6 V to about 1.0 V. The driving voltage of the plurality of second transistors disposed in the second voltage region  2200  may be about 1.8 V, or may have a range of about 1.6 V to about 2.0 V. The driving voltage of the plurality of third transistors disposed in the third voltage region  2300  may be about 2.2 V, or may have a range of about 2.0 V to about 2.4 V. The driving voltage of the plurality of fourth transistors disposed in the fourth voltage region  2400  may be about 3.3 V, or may have a range of about 3.1 V to about 3.5 V. However, a detailed numerical range of the driving voltage is only an example, and the driving voltage in each of the plurality of voltage regions  2100 ,  2200 ,  2300 , and  2400  may be provided as a value different from the above example. 
     In an example embodiment, the plurality of transistors included in each of the plurality of voltage regions  2100 ,  2200 ,  2300 , and  2400  may have different driving voltages for respective voltage regions. The plurality of transistors included in any one voltage region may be transistors capable of being driven by a driving voltage in the corresponding voltage region. 
       FIG.  19    is a flowchart illustrating a process sequence to illustrate a method of manufacturing a semiconductor device according to example embodiments. Similar to the substrate structure  2000  of  FIG.  17   ,  FIG.  18    illustrates an example of a process of forming a transistor on a low voltage region and a transistor on a high voltage region together, in the plurality of voltage regions  2100 ,  2200 ,  2300 , and  2400  driven by different driving voltages. 
     Referring to  FIG.  19   , a first active fin on a low voltage region and a second active fin on a high voltage region may be formed (S 100 ). The high voltage region may correspond to, for example, the fourth voltage region  2400  of  FIG.  18   , and the low voltage region may correspond to, for example, the first voltage region  2100  of  FIG.  18   . The first active fin and the second active fin may extend in the first direction by patterning the substrate. The first active fin and the second active fin may be formed in the same process operation, for example, at the same time, but the present inventive concept is not necessarily limited thereto. 
     A first sacrificial gate pattern intersecting the first active fin and a second sacrificial gate pattern intersecting the second active fin may be formed (S 200 ). The first sacrificial gate pattern and the second sacrificial gate pattern may extend in a second direction perpendicular to the first direction. The first sacrificial gate pattern and the second sacrificial gate pattern may be formed together in a single process operation, for example, at the same time, but the present inventive concept is not necessarily limited thereto. 
     First insulating spacers may be formed on opposite sides of the first sacrificial gate pattern and second insulating spacers may be formed on opposite sides of the second sacrificial gate pattern (S 300 ). The first and second insulating spacers may be formed by depositing a film having a uniform thickness covering the first and second active fins and the first and second sacrificial gate patterns. 
     A photoresist is formed on a substrate, and the photoresist is left on a portion of the second insulating spacer while removing the photoresist, and then, a gate spacer having an offset may be formed on at least one side of the second sacrificial gate pattern, on the high voltage region, by etching the first and second insulating spacers (S 400 ). To reduce occurrence of GIDL and hot carriers by reducing a maximum electric field in the transistor to which the high voltage is applied, the photoresist may remain on a portion in which the second insulating spacer horizontally extends along the upper surface of the second active fin, on one side of the second sacrificial gate pattern in the high voltage region. In an anisotropic etching process to form gate spacers, the remaining photoresist may be formed as a gate spacer (see  134   a _D in  FIG.  2 A ) having a region in which the second insulating spacer has been offset. 
     First recess regions may be formed by etching the first active fins on opposite sides of the first sacrificial gate pattern, and second recess regions may be formed by etching the second active fins on opposite sides of the second sacrificial gate pattern (S 500 ). The first recess regions may be formed by partially etching the first active fins and removing the first active fins by a predetermined depth downwardly from the upper ends of the first active fins. The second recess regions may be formed as the second active fins are partially etched and removed by a predetermined depth downwardly from the upper ends of the second active fins. The first recess regions and the second recess regions may be formed in the same process operation, e.g., at the same time, but the present inventive concept is not necessarily limited thereto. 
     By performing an epitaxial growth process and an in-situ doping process of doping an impurity element, the first epitaxial layers on the first recess regions and second epitaxial layers on the second recess regions may be formed (S 600 ). The first epitaxial layers and the second epitaxial layers may be formed as epitaxial layers by performing an epitaxial growth process from the first recess regions and the second recess regions. The first epitaxial layers and the second epitaxial layers may be formed in the same process operation, for example, at the same time, but the present inventive concept is not necessarily limited thereto. 
     Thereafter, referring to  FIG.  9 A  together, openings are formed by removing the first and second sacrificial gate patterns, and a gate structure is formed by depositing a gate dielectric layer and a gate electrode in the openings, and contacts connected to the first and second epitaxial layers may be formed. 
     As set forth above, by forming an offset in the spacer between the epitaxial layer and the gate in a transistor to which a high voltage is applied as a driving voltage, a semiconductor device having desirable electrical characteristics and greater reliability by reducing or significantly decreasing a Gate Induced Drain Leakage (GIDL) phenomenon and occurrence of hot carriers of a transistor may be provided. 
     While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept.