Patent Publication Number: US-2019198429-A1

Title: Fan-out semiconductor package

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application claims benefit of priority to Korean Patent Application No. 10-2017-0177399 filed on Dec. 21, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. 
     TECHNICAL FIELD 
     The present disclosure relates to a semiconductor package, and more particularly, to a fan-out semiconductor package in which electrical connection structures may extend outwardly of a region in which a semiconductor chip is disposed. 
     BACKGROUND 
     A significant recent trend in the development of technology related to semiconductor chips has been reductions in the size of semiconductor chips. Therefore, in the field of package technology, in accordance with a rapid increase in demand for small-sized semiconductor chips, or the like, the implementation of a semiconductor package, having a compact size while including a plurality of pins, has been demanded. 
     One type of semiconductor package technology suggested to satisfy the technical demand, described above, is a fan-out semiconductor package. Such a fan-out package has a compact size and may allow a plurality of pins to be implemented by redistributing connection terminals outwardly of a region in which a semiconductor chip is disposed. 
     In the semiconductor package, when electromagnetic waves may have an influence on the semiconductor chip, and the like, a problem may occur. Therefore, an effective electromagnetic wave blocking structure is required in the semiconductor package. 
     SUMMARY 
     An aspect of the present disclosure may provide a fan-out semiconductor package including an effective electromagnetic wave blocking structure and having improved heat dissipation performance. 
     According to an aspect of the present disclosure, a fan-out semiconductor package may include: a frame including a plurality of insulating layers, a plurality of wiring layers disposed on the plurality of insulating layers, and a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and disposed on the stopper layer; first metal bumps disposed on the connection pads of the semiconductor chip; an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first metal bumps and filling at least portions of the recess portion; a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other; and a first blocking structure disposed on walls of the recess portion to surround side surfaces of the semiconductor chip. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a schematic block diagram illustrating an example of an electronic device system; 
         FIG. 2  is a schematic perspective view illustrating an example of an electronic device; 
         FIGS. 3A and 3B  are schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged; 
         FIG. 4  is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package; 
         FIG. 5  is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is ultimately mounted on a mainboard of an electronic device; 
         FIG. 6  is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is ultimately mounted on a mainboard of an electronic device; 
         FIG. 7  is a schematic cross-sectional view illustrating a fan-out semiconductor package; 
         FIG. 8  is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a mainboard of an electronic device; 
         FIG. 9  is a schematic cross-sectional view illustrating an example of a fan-out semiconductor package; 
         FIG. 10  is a schematic plan view illustrating a semiconductor chip and a blocking structure in the fan-out semiconductor package of  FIG. 9 ; 
         FIGS. 11 and 12  are schematic cross-sectional views illustrating fan-out semiconductor packages according to modified exemplary embodiments; and 
         FIGS. 13 through 17  are schematic views illustrating processes of manufacturing a fan-out semiconductor package according to an exemplary embodiment in the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, shapes, sizes, and the like, of components may be exaggerated or shortened for clarity. 
     Herein, a lower side, a lower portion, a lower surface, and the like, are used to refer to a direction toward a mounting surface of the fan-out semiconductor package in relation to cross sections of the drawings, while an upper side, an upper portion, an upper surface, and the like, are used to refer to an opposite direction to the direction. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined as described above. 
     The meaning of a “connection” of a component to another component in the description includes an indirect connection through an adhesive layer as well as a direct connection between two components. In addition, “electrically connected” conceptually includes a physical connection and a physical disconnection. It can be understood that when an element is referred to with terms such as “first” and “second”, the element is not limited thereby. They may be used only for a purpose of distinguishing the element from the other elements, and may not limit the sequence or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element. 
     The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with one another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein. 
     Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. In this case, singular forms include plural forms unless interpreted otherwise in context. 
     Electronic Device 
       FIG. 1  is a schematic block diagram illustrating an example of an electronic device system. 
     Referring to  FIG. 1 , an electronic device  1000  may accommodate a mainboard  1010  therein. The mainboard  1010  may include chip related components  1020 , network related components  1030 , other components  1040 , and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines  1090 . 
     The chip related components  1020  may include a memory chip such as a volatile memory (for example, a dynamic random access memory (DRAM)), a non-volatile memory (for example, a read only memory (ROM)), a flash memory, or the like; an application processor chip such as a central processor (for example, a central processing unit (CPU)), a graphics processor (for example, a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and a logic chip such as an analog-to-digital (ADC) converter, an application-specific integrated circuit (ASIC), or the like. However, the chip related components  1020  are not limited thereto, but may also include other types of chip related components. In addition, the chip related components  1020  may be combined with each other. 
     The network related components  1030  may include protocols such as wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, or the like), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, or the like), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access+ (HSPA+), high speed downlink packet access+ (HSDPA+), high speed uplink packet access+ (HSUPA+), enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, and 5G protocols, and any other wireless and wired protocols, designated after the abovementioned protocols. However, the network related components  1030  are not limited thereto, but may also include a variety of other wireless or wired standards or protocols. In addition, the network related components  1030  may be combined with each other, together with the chip related components  1020  described above. 
     Other components  1040  may include a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, a low temperature co-fired ceramic (LTCC), an electromagnetic interference (EMI) filter, a multilayer ceramic capacitor (MLCC), or the like. However, other components  1040  are not limited thereto, but may also include passive components used for various other purposes, or the like. In addition, other components  1040  may be combined with each other, together with the chip related components  1020  or the network related components  1030  described above. 
     Depending on a type of the electronic device  1000 , the electronic device  1000  may include other components that may or may not be physically or electrically connected to the mainboard  1010 . These other components may include, for example, a camera module  1050 , an antenna  1060 , a display device  1070 , a battery  1080 , an audio codec (not illustrated), a video codec (not illustrated), a power amplifier (not illustrated), a compass (not illustrated), an accelerometer (not illustrated), a gyroscope (not illustrated), a speaker (not illustrated), a mass storage unit (for example, a hard disk drive) (not illustrated), a compact disk (CD) drive (not illustrated), a digital versatile disk (DVD) drive (not illustrated), or the like. However, these other components are not limited thereto, but may also include other components used for various purposes depending on a type of electronic device  1000 , or the like. 
     The electronic device  1000  may be a smartphone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game machine, a smartwatch, an automotive component, or the like. However, the electronic device  1000  is not limited thereto, but may be any other electronic device processing data. 
       FIG. 2  is a schematic perspective view illustrating an example of an electronic device. 
     Referring to  FIG. 2 , a semiconductor package may be used for various purposes in the various electronic devices  1000  as described above. For example, a motherboard  1110  may be accommodated in a body  1101  of a smartphone  1100 , and various electronic components  1120  may be physically or electrically connected to the motherboard  1110 . In addition, other components that may or may not be physically or electrically connected to the mainboard  1010 , such as a camera module  1130 , may be accommodated in the body  1101 . Some of the electronic components  1120  may be the chip related components, and the semiconductor package  100  may be, for example, an application processor among the chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smartphone  1100 , but may be other electronic devices as described above. 
     Semiconductor Package 
     Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a finished semiconductor product in itself, and may be damaged due to external physical or chemical impacts. Therefore, the semiconductor chip itself may not be used, but may be packaged and used in an electronic device, or the like, in a packaged state. 
     Here, semiconductor packaging is required due to the existence of a difference in a circuit width between the semiconductor chip and a mainboard of the electronic device in terms of electrical connections. In detail, a size of connection pads of the semiconductor chip and an interval between the connection pads of the semiconductor chip are very fine, but a size of component mounting pads of the mainboard used in the electronic device and an interval between the component mounting pads of the mainboard are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and packaging technology for buffering a difference in a circuit width between the semiconductor chip and the mainboard is required. 
     A semiconductor package manufactured by the packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof. 
     The fan-in semiconductor package and the fan-out semiconductor package will hereinafter be described in more detail with reference to the drawings. 
     Fan-In Semiconductor Package 
       FIGS. 3A and 3B  are schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged. 
       FIG. 4  is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package. 
     Referring to  FIGS. 3A to 4 , a semiconductor chip  2220  may be, for example, an integrated circuit (IC) in a bare state, including a body  2221  including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads  2222  formed on one surface of the body  2221  and including a conductive material such as aluminum (Al), or the like, and a passivation layer  2223  such as an oxide film, a nitride film, or the like, formed on one surface of the body  2221  and covering at least portions of the connection pads  2222 . In this case, since the connection pads  2222  may be significantly small, it may be difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the mainboard of the electronic device, or the like. 
     Therefore, a connection member  2240  may be formed depending on a size of the semiconductor chip  2220  on the semiconductor chip  2220  in order to redistribute the connection pads  2222 . The connection member  2240  may be formed by forming an insulating layer  2241  on the semiconductor chip  2220  using an insulating material such as a photoimagable dielectric (PID) resin, forming via holes  2243   h  opening the connection pads  2222 , and then forming wiring patterns  2242  and vias  2243 . Then, a passivation layer  2250  protecting the connection member  2240  may be formed, an opening  2251  may be formed, and an underbump metal layer  2260 , or the like, may be formed. That is, a fan-in semiconductor package  2200  including, for example, the semiconductor chip  2220 , the connection member  2240 , the passivation layer  2250 , and the underbump metal layer  2260  may be manufactured through a series of processes. 
     As described above, the fan-in semiconductor package may have a package form in which all of the connection pads, for example, input/output (I/O) terminals, of the semiconductor chip are disposed inside the semiconductor chip, and may have excellent electrical characteristics and be produced at a low cost. Therefore, many elements mounted in smartphones have been manufactured in a fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to implement a rapid signal transfer while having a compact size. 
     However, since all I/O terminals need to be disposed inside the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has significant spatial limitations. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a compact size. In addition, due to the disadvantage described above, the fan-in semiconductor package may not be directly mounted and used on the mainboard of the electronic device. The reason is that even in a case in which a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in semiconductor package on the mainboard of the electronic device. 
       FIG. 5  is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is ultimately mounted on a mainboard of an electronic device. 
       FIG. 6  is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is ultimately mounted on a mainboard of an electronic device. 
     Referring to  FIGS. 5 and 6 , in a fan-in semiconductor package  2200 , connection pads  2222 , that is, I/O terminals, of a semiconductor chip  2220  may be redistributed through an interposer substrate  2301 , and the fan-in semiconductor package  2200  may be ultimately mounted on a mainboard  2500  of an electronic device in a state in which it is mounted on the interposer substrate  2301 . In this case, solder balls  2270 , and the like, may be fixed by an underfill resin  2280 , or the like, and an outer side of the semiconductor chip  2220  may be covered with a molding material  2290 , or the like. Alternatively, a fan-in semiconductor package  2200  may be embedded in a separate interposer substrate  2302 , connection pads  2222 , that is, I/O terminals, of the semiconductor chip  2220  may be redistributed by the interposer substrate  2302  in a state in which the fan-in semiconductor package  2200  is embedded in the interposer substrate  2302 , and the fan-in semiconductor package  2200  may be ultimately mounted on a mainboard  2500  of an electronic device. 
     As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the mainboard of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate interposer substrate and be then mounted on the mainboard of the electronic device through a packaging process or may be mounted and used on the mainboard of the electronic device in a state in which it is embedded in the interposer substrate. 
     Fan-Out Semiconductor Package 
       FIG. 7  is a schematic cross-sectional view illustrating a fan-out semiconductor package. 
     Referring to  FIG. 7 , in a fan-out semiconductor package  2100 , for example, an outer side of a semiconductor chip  2120  may be protected by an encapsulant  2130 , and connection pads  2122  of the semiconductor chip  2120  may be redistributed outwardly of the semiconductor chip  2120  by a connection member  2140 . In this case, a passivation layer  2150  may further be formed on the connection member  2140 , and an underbump metal layer  2160  may further be formed in openings of the passivation layer  2150 . Solder balls  2170  may further be formed on the underbump metal layer  2160 . The semiconductor chip  2120  may be an integrated circuit (IC) including a body  2121 , the connection pads  2122 , a passivation layer (not illustrated), and the like. The connection member  2140  may include an insulating layer  2141 , redistribution layers  2142  formed on the insulating layer  2141 , and vias  2143  electrically connecting the connection pads  2122  and the redistribution layers  2142  to each other. 
     As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip need to be disposed inside the semiconductor chip. Therefore, when a size of the semiconductor chip is decreased, a size and a pitch of balls need to be decreased, such that a standardized ball layout may not be used in the fan-in semiconductor package. On the other hand, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip as described above. Therefore, even in a case that a size of the semiconductor chip is decreased, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using a separate interposer substrate, as described below. 
       FIG. 8  is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a mainboard of an electronic device. 
     Referring to  FIG. 8 , a fan-out semiconductor package  2100  may be mounted on a mainboard  2500  of an electronic device through solder balls  2170 , or the like. That is, as described above, the fan-out semiconductor package  2100  includes the connection member  2140  formed on the semiconductor chip  2120  and capable of redistributing the connection pads  2122  to a fan-out region that is outside of a size of the semiconductor chip  2120 , such that the standardized ball layout may be used in the fan-out semiconductor package  2100  as it is. As a result, the fan-out semiconductor package  2100  may be mounted on the mainboard  2500  of the electronic device without using a separate interposer substrate, or the like. 
     As described above, since the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using the separate interposer substrate, the fan-out semiconductor package may be implemented at a thickness lower than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out semiconductor package may be implemented in a form more compact than that of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve a problem due to the occurrence of a warpage phenomenon. 
     Meanwhile, the fan-out semiconductor package refers to package technology for mounting the semiconductor chip on the mainboard of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts, and is a concept different from that of a printed circuit board (PCB) such as an interposer substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein. 
     Fan-out semiconductor packages according to exemplary embodiments in the present disclosure will hereinafter be described with reference to the drawings. 
       FIG. 9  is a schematic cross-sectional view illustrating an example of a fan-out semiconductor package.  FIG. 10  is a schematic plan view illustrating a semiconductor chip and a blocking structure in the fan-out semiconductor package of  FIG. 9 .  FIGS. 11 and 12  are schematic cross-sectional views illustrating fan-out semiconductor packages according to modified exemplary embodiments. 
     Referring to the drawings, a fan-out semiconductor package  100  according to an exemplary embodiment in the present disclosure may include a frame  110 , a semiconductor chip  121 , an encapsulant  131 , and a connection member  140 . The frame  110  may have a recess portion  110 H. In addition, the fan-out semiconductor package  100  according to the exemplary embodiment may include a first blocking structure  127  formed on sidewalls of the recess portion  110 H and a second blocking structure  128  formed on the recess portion  110 H as electromagnetic wave blocking structures. The first blocking structure  127  may be electrically connected to the ground. Therefore, the fan-out semiconductor package  100  according to the exemplary embodiment may further include a third blocking structure  129  connecting the first and second blocking structures  127  and  128  to each other. 
     In addition, the fan-out semiconductor package  100  according to the exemplary embodiment may further include a first passivation layer  151  disposed on the connection member  140  and having openings exposing at least portions of a redistribution layer  142  of the connection member  140 , a second passivation layer  152  disposed on the frame  110  and having openings exposing at least portions of a wiring layer  112   c  of the frame  110 , underbump metal layers  160  disposed in the openings of the first passivation layer  151  and electrically connected to the exposed redistribution layer  142 , and electrical connection structures  170  disposed on the underbump metal layers  160  and electrically connected to the exposed redistribution layer  142  through the underbump metal layers  160 , if necessary. 
     The frame  110  may improve rigidity of the fan-out semiconductor package  100  depending on certain materials, and serve to secure uniformity of a thickness of an encapsulant  131 . In addition, the frame  110  may include wiring layers  112   a,    112   b,    112   c,  and  112   d,  and connection via layers  113   a,    113   b,  and  113   c,  and thus serve as a connection member. The frame  110  may include the wiring layer  112   c  disposed on an inactive surface of the semiconductor chip  121  and provided as a backside wiring layer for the semiconductor chip  121  without performing a process of forming a separate backside wiring layer. 
     A metal layer  126  may be disposed below of the recess portion  110 H. The metal layer may be electrically connected to the ground. The semiconductor chip  121  may be disposed on the metal layer  126 . In addition, the metal layer  126  may serve as an etch stop layer for forming the recess portion  110 H. In addition, the inactive surface of the semiconductor chip  121  may be attached to the metal layer  126  through any known adhesive member  125  such as a die attach film (DAF), or the like. The recess portion  110 H may be formed by a sandblasting process. In this case, the recess portion  110 H may have a tapered shape. That is, walls of the recess portion  110 H may have a predetermined gradient in relation to the metal layer  126 . The metal layer  126  may have a planar area greater than that of the inactive surface of the semiconductor chip  121 . The bottom surface of the recess portion  110 H has a planar area greater than that of the inactive surface of the semiconductor chip  121 . In this case, a process of aligning the semiconductor chip  121  may be easier, and a yield of the semiconductor chip  121  may thus be improved. 
     The semiconductor chip  121  may be an integrated circuit (IC) provided in an amount of several hundred to several million or more elements integrated in a single chip. The semiconductor chip  121  may be, for example, a processor chip (more specifically, an application processor (AP)) such as a central processor (for example, a CPU), a graphic processor (for example, a GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a micro processor, a micro controller, or the like, but is not limited thereto. 
     The semiconductor chip  121  may be formed on the basis of an active wafer. In this case, a base material of a body of the semiconductor chip  121  may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body. Connection pads  121 P may electrically connect the semiconductor chip  121  to other components. A material of each of the connection pads  121 P may be a conductive material such as aluminum (Al), or the like. A passivation layer exposing the connection pads  121 P may be formed on the body, and may be an oxide film, a nitride film, or the like, or a double layer of an oxide layer and a nitride layer. An insulating layer, and the like, may also be further disposed in required positions. The semiconductor chip  121  may be a bare die, but may further include a redistribution layer formed on an active surface thereof, if necessary. 
     The semiconductor chip  121  may include metal bumps  121 B disposed on the connection pads  121 P and connected to the connection pads  121 P. Each of the metal bumps  121 B may be formed of a metal such as copper (Cu) or may be formed of a solder. As seen from a process to be described below, the fan-out semiconductor package  100  according to the exemplary embodiment may be subjected to a grinding process. In this case, a surface of a fourth wiring layer  112   d  of the frame  110  connected to the redistribution layer  142  may be disposed on the same level as or be coplanar with that of a surface of each of the metal bumps  121 B of the semiconductor chip  121  connected to the redistribution layer  142 . The same level or being coplanar may conceptually include a fine difference due to a process error. Therefore, a height of a connection via  143  connecting the metal bump  121 B to the redistribution layer  142  and a height of a connection via  143  connecting the fourth wiring layer  112   d  to the redistribution layer  142  may be the same as each other. The same height may conceptually include a fine difference due to a process error. When a surface on which the connection member  140  is formed is flat as described above, insulating layers  141  may be flatly formed, and the redistribution layers  142 , the connection vias  143 , or the like, may thus be more finely formed. Meanwhile, a structure in which one semiconductor chip  121  is included in the fan-out semiconductor package  100  is described in the present exemplary embodiment, but a plurality of semiconductor chips  121  may also be used, if necessary. 
     The frame  110  may include a first insulating layer  111   a,  first and second wiring layers  112   a  and  112   b  disposed, respectively, on first and second surfaces of the first insulating layer  111   a  opposing each other, a second insulating layer  111   b  disposed on the first surface of the first insulating layer  111   a  and covering the first wiring layer  112   a,  a third wiring layer  112   c  disposed on the second insulating layer  111   b,  a third insulating layer  111   c  disposed on the second surface of the first insulating layer  111   a  and covering the second wiring layer  112   b,  and a fourth wiring layer  112   d  disposed on the third insulating layer  111   c.  In addition, the frame  110  may include first connection via layers  113   a  penetrating through the first insulating layer  111   a  and electrically connecting the first and second wiring layers  112   a  and  112   b  to each other, second connection via layers  113   b  penetrating through the second insulating layer  111   b  and electrically connecting the first and third wiring layers  112   a  and  112   c  to each other, and third connection via layers  113   c  penetrating through the third insulating layer  111   c  and electrically connecting the second and fourth wiring layers  112   b  and  112   d  to each other. The first to fourth wiring layers  112   a,    112   b,    112   c,  and  112   d  may be electrically connected to each other, and may be electrically connected to the semiconductor chip  121 . The recess portion  110 H may penetrate through the first and third insulating layers  111   a  and  111   c,  but may not penetrate through the second insulating layer  111   b,  and the metal layer  126  may be disposed on the first surface of the first insulating layer  111   a  and be covered with the second insulating layer  111   b.  However, according to another exemplary embodiment, the recess portion  110 H may penetrate through another insulating layer, for example, the second insulating layer  111   b.    
     A material of each of the insulating layers  111   a,    111   b,  and  111   c  may be an insulating material. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. When a material having high rigidity, such as prepreg including a glass fiber, or the like, is used as the material of each of the insulating layers  111   a,    111   b,  and  111   c,  the frame  110  may be utilized as a support member for controlling warpage of the fan-out semiconductor package  100 . 
     The first insulating layer  111   a  may have a thickness greater than those of the second insulating layer  111   b  and the third insulating layer  111   c.  The first insulating layer  111   a  may be basically relatively thick in order to maintain rigidity, and the second insulating layer  111   b  and the third insulating layer  111   c  may be introduced in order to form a larger number of wiring layers  112   c  and  112   d.  The first insulating layer  111   a  may include an insulating material different from those of the second insulating layer  111   b  and the third insulating layer  111   c.  For example, the first insulating layer  111   a  may be, for example, prepreg in which an insulating resin is impregnated together with an inorganic filler in a glass fiber, and the second insulating layer  111   b  and the third insulating layer  111   c  may be an ABF or a PID film including an inorganic filler and an insulating resin. However, the materials of the first insulating layer  111   a  and the second and third insulating layers  111   b  and  111   c  are not limited thereto. Similarly, the first connection via layer  113   a  penetrating through the first insulating layer  111   a  may have a diameter greater than those of the second and third connection via layers  113   b  and  113   c  respectively penetrating through the second and third insulating layers  111   b  and  111   c.    
     The wiring layers  112   a,    112   b,    112   c,  and  112   d  may redistribute the connection pads  121 P of the semiconductor chip  121 , and may electrically connect the semiconductor chip  121  and another chip to each other together with the redistribution layers  142 . A material of each of the wiring layers  112   a,    112   b,    112   c,  and  112   d  may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring layers  112   a,    112   b,    112   c,  and  112   d  may perform various functions depending on designs of corresponding layers. For example, the wiring layers  112   a,    112   b,    112   c,  and  112   d  may include ground patterns, power patterns, signal patterns, and the like. Here, the signal patterns may include various signals except for the ground patterns, the power patterns, and the like, such as data signals, and the like. In addition, the wiring layers  112   a,    112   b,    112   c,  and  112   d  may include via pads, wire pads, electrical connection structure pads, and the like. 
     Thicknesses of the wiring layers  112   a,    112   b,    112   c,  and  112   d  may be greater than those of the redistribution layers  142  of the connection member  140 . Since the frame  110  may have a thickness equal to or greater than that of the semiconductor chip  121 , the wiring layers  112   a,    112   b,    112   c,  and  112   d  may also be formed to have large sizes. On the other hand, the redistribution layers  142  of the connection member  140  may be formed to have relatively small sizes for thinness. 
     The connection via layers  113   a,    113   b,  and  113   c  may electrically connect the wiring layers  112   a,    112   b,    112   c,  and  112   d  formed on different layers to each other, resulting in an electrical path in the frame  110 . A material of each of the connection via layers  113   a,    113   b,  and  113   c  may be a conductive material. Each of the connection via layers  113   a,    113   b,  and  113   c  may be completely filled with the conductive material, or the conductive material may also be formed along a wall of each of via holes. The first connection via layer  113   a  may have a cylindrical shape or a hourglass shape, and the second and third connection via layers  113   b  and  113   c  may have tapered shapes. In this case, the second and third connection via layers  113   b  and  113   c  may have tapered shapes of which directions are opposite to each other in relation to the first insulating layer  111   a.    
     The first blocking structure  127  may be formed on the sidewalls of the recess portion  110 H to surround side surfaces of the semiconductor chip  121 , and may be formed of a material such as a metal, or the like, able to block electromagnetic waves. For example, the first blocking structure  127  may be implemented using the same material as that of the redistribution layers  142 , the wiring layers  112   a,    112   b,    112   c,  and  112   d,  or the like. The first blocking structure  127  formed to surround the side surfaces of the semiconductor chip  121  may be used, such that the electromagnetic waves may be effectively blocked. As illustrated in  FIG. 9 , the first blocking structure  127  may extend from the sidewalls of the recess portion  110 H to an upper surface of the frame  110 . 
     The second blocking structure  128  may be formed on the recess portion  110 H and cover the active surface of the semiconductor chip. The second blocking structure  128  may be formed of the same material as that of the first blocking structure  127 , the redistribution layer  142 , the wiring layers  112   a,    112   b,    112   c,  and  112 , or the like, and may be manufactured together with the redistribution layer  142  by, for example, a process of manufacturing the redistribution layer  142 . As illustrated in  FIG. 10 , the second blocking structure  128  may have a plate shape, and an effective blocking structure may be implemented on the semiconductor chip  121 . In this case, the second blocking structure  128  may have through-holes formed in regions corresponding to the connection pads  121 P of the semiconductor chip  121 . In addition, some of the connection vias  143  included in the connection member  140  may be formed in the through-holes h to electrically connect the connection pads  121 P and the redistribution layer  142  to each other. In addition, as in an illustrated form, portions of the active surface of the semiconductor chip  121  between adjacent metal bumps  121 B may be covered by the second blocking structure  128 . The second blocking structure  128  may extend from a region covering the third insulating layer  111   c  to cover edge portions of the recess portion  110 H not occupied by the semiconductor chip  121  and edge portions of the semiconductor chip  121 . The second blocking structure  128  may extend from the region covering the third insulating layer  111   c  to cover the entire active surface of the semiconductor chip  121  except those regions corresponding to the connection pads  121 P or those regions corresponding to the metal bumps  121 B to allow electrical connections made of, for example, connection vias  143 , to pass through and also be electrically isolated from the second blocking structure  128 . In this case, the second blocking structure  128  may be an integral element. If necessary, one of the through-hole h corresponding to a metal bump  121 B connected to the ground may be omitted, and as such, the second blocking structure  128  may be electrically connected to the ground, by contacting the corresponding metal bump  121 B connected to the ground and/or a corresponding connection via connected to the ground. 
     The third blocking structure  129  may connect the first and second blocking structures  127  and  128  to each other, and may be formed of the same material as that of the first and second blocking structures  127  and  128 , such as a metal. The third blocking structure  129  may penetrate through the encapsulant  131 , and may be physically connected to the first and second blocking structures  127  and  128 . The third blocking structure  129  may be disposed on the same level as upper portions of the metal bumps  121 B disposed on the connection pads  121 P of the semiconductor chip  121 , in a case in which the connection pads  121 P are disposed on a level below the fourth wiring layer  112   d.  The third blocking structure  129  may be disposed on the same level as that of the metal bumps  121 B disposed on the connection pads  121 P of the semiconductor chip  121 , in a case in which the connection pads  121 P are disposed on the same level as the fourth wiring layer  112   d.  In order to implement the effective blocking structure, the third blocking structure  129  may have a ring shape configuring a closed loop unlike the connection vias performing an electrical connection function, as illustrated in  FIG. 10 . Therefore, a region in which electromagnetic waves may be leaked in the vicinity of the third blocking structure  129  may be decreased to improve overall blocking performance together with the first and second blocking structures  127  and  128 . 
     Substantially, all regions around the semiconductor chip  121  may be surrounded with electromagnetic wave blocking materials by the first to third blocking structures  127 ,  128 , and  129  described above, and electromagnetic wave blocking performance of the fan-out semiconductor package  100  may thus be improved. Further, the first to third blocking structures  127 ,  128 , and  129  may have excellent heat dissipation efficiency to contribute to improvement of heat dissipation performance of the fan-out semiconductor package  100 . 
     The encapsulant  131  may be filled in the recess portion  110 H to protect the frame  110 , the semiconductor chip  121 , and the like. An encapsulation form of the encapsulant  131  is not particularly limited, but may be a form in which the encapsulant  131  surrounds at least portions of the frame  110 , the semiconductor chip  121 , and the like. For example, the encapsulant  131  may cover the frame  110  and the active surface of the semiconductor chip  121 , and fill spaces between the walls of the recess portion  110 H and the side surfaces of the semiconductor chip  121 . The encapsulant  131  may fill the recess portion  110 H to thus serve as an adhesive and reduce buckling of the semiconductor chip  121  depending on certain materials. 
     A material of the encapsulant  131  is not particularly limited. For example, an insulating material may be used as the material of the encapsulant  131 . In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, a photoimagable encapsulant (PIE) resin may also be used as the insulating material. 
     The connection member  140  may be disposed on one surface of the frame  110 , may be electrically connected to the semiconductor chip  121 , and may include the redistribution layers  142 . For example, the connection member  140  may redistribute the connection pads  121 P of the semiconductor chip  121 , and may electrically connect the wiring layers  112   a,    112   b,    112   c,  and  112   d  of the frame  110  to the connection pads  121 P of the semiconductor chip  121 . Several tens to several millions of connection pads  121 P of the semiconductor chip  121  having various functions may be redistributed by the connection member  140 , and may be physically or electrically externally connected through the electrical connection structures  170  depending on the functions. The connection member  140  may include the insulating layers  141  disposed on the frame  110  and the active surface of the semiconductor chip  121 , the redistribution layers  142  disposed on the insulating layers  141 , and the connection vias  143  penetrating through the insulating layers  141  and connecting the connection pads  121 P, the fourth wiring layer  112   d,  and each of the redistribution layers  142  to each other. The numbers of insulating layers, redistribution layers, via layers of the connection member  140  may be more than or less than those illustrated in the drawing. 
     A material of each of the insulating layers  141  may be an insulating material. In this case, a photosensitive insulating material such as a PID resin may also be used as the insulating material. That is, each of the insulating layers  141  may be a photosensitive insulating layer. When the insulating layer  141  has photosensitive properties, the insulating layer  141  may be formed to have a smaller thickness, and a fine pitch of the connection via  143  may be achieved more easily. Each of the insulating layers  141  may be a photosensitive insulating layer including an insulating resin and an inorganic filler. When the insulating layers  141  are multiple layers, materials of the insulating layers  141  may be the same as each other, and may also be different from each other, if necessary. When the insulating layers  141  are the multiple layers, the insulating layers  141  may be integrated with each other depending on a process, such that a boundary therebetween may also not be apparent. 
     The redistribution layers  142  may serve to substantially redistribute the connection pads  121 P. A material of each of the redistribution layers  142  may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers  142  may perform various functions depending on designs of corresponding layers. For example, the redistribution layers  142  may include ground patterns, power patterns, signal patterns, and the like. Here, the signal patterns may include various signals except for the ground patterns, the power patterns, and the like, such as data signals, and the like. In addition, the redistribution layers  142  may include various pad patterns, and the like. 
     The connection vias  143  may electrically connect the redistribution layers  142 , the connection pads  121 P, and the fourth wiring layer  112   d,  and the like, formed on different layers to each other, resulting in an electrical path in the fan-out semiconductor package  100 . A material of each of the connection vias  143  maybe a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the connection vias  143  may be completely filled with the conductive material, or the conductive material may also be formed along a wall of each of the connection vias. In addition, each of the connection vias  143  may have a tapered shape, or the like. 
     The first passivation layer  151  may protect the connection member  140  from external physical or chemical damage. The first passivation layer  151  may have the openings exposing at least portions of the redistribution layer  142  of the connection member  140 . The number of openings formed in the first passivation layer  151  may be several tens to several millions. A material of the first passivation layer  151  is not particularly limited. For example, an insulating material may be used as the material of the first passivation layer  151 . In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, a solder resist may also be used. 
     The second passivation layer  152  may protect the frame  110  from external physical or chemical damage. The second passivation layer  152  may have the openings exposing at least portions of the third wiring layer  112   c  of the frame  110 . The number of openings formed in the second passivation layer  152  may be several tens to several millions. A material of the second passivation layer  152  is not particularly limited. For example, an insulating material may be used as the material of the second passivation layer  152 . In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, a solder resist may also be used. 
     The underbump metal layers  160  may improve connection reliability of the electrical connection structures  170  to improve board level reliability of the fan-out semiconductor package  100 . The underbump metal layers  160  may be connected to the redistribution layer  142  of the connection member  140  exposed through the openings of the passivation layer  151 . The underbump metal layers  160  may be formed in the openings of the passivation layer  151  by any known metallization method using any known conductive material such as a metal, but are not limited thereto. 
     The electrical connection structures  170  may physically or electrically externally connect the fan-out semiconductor package  100 . For example, the fan-out semiconductor package  100  may be mounted on the mainboard of the electronic device through the electrical connection structures  170 . Each of the electrical connection structures  170  may be formed of a conductive material, for example, a solder, or the like. However, this is only an example, and a material of each of the electrical connection structures  170  is not particularly limited thereto. Each of the electrical connection structures  170  may be a land, a ball, a pin, or the like. The electrical connection structures  170  may be formed as a multilayer or single layer structure. When the electrical connection structures  170  are formed as a multilayer structure, the electrical connection structures  170  may include a copper (Cu) pillar and a solder. When the electrical connection structures  170  are formed as a single layer structure, the electrical connection structures  170  may include a tin-silver solder or copper (Cu). However, this is only an example, and the electrical connection structures  170  are not limited thereto. 
     The number, an interval, a disposition form, and the like, of electrical connection structures  170  are not particularly limited, but may be sufficiently modified depending on design particulars by those skilled in the art. For example, the electrical connection structures  170  may be provided in an amount of several tens to several thousands according to the number of connection pads  121 P, or may be provided in an amount of several tens to several thousands or more or several tens to several thousands or less. When the electrical connection structures  170  are solder balls, the electrical connection structures  170  may cover side surfaces of the underbump metal layers  160  extending onto one surface of the first passivation layer  151 , and connection reliability may be more excellent. 
     At least one of the electrical connection structures  170  may be disposed in a fan-out region. The fan-out region refers to a region except for a region in which the semiconductor chip  121  is disposed. The fan-out package may have excellent reliability as compared to a fan-in package, may implement a plurality of input/output (I/O) terminals, and may facilitate a 3D interconnection. In addition, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be manufactured to have a small thickness, and may have price competitiveness. 
     Fan-out semiconductor packages according to modified examples will be described with reference to  FIGS. 11 and 12 . First, in a modified example of  FIG. 11 , shapes of a first blocking structure  127  and a metal layer  126  may be modified so that heat dissipation characteristics are further improved, as compared to the abovementioned exemplary embodiment. In detail, the first blocking structure  127  may include heat dissipation portions  127   d  extending from sidewalls of a recess portion  110 H inwardly of a frame  110 . The heat dissipation portions  127   d  may have a ring shape in a form such as a closed loop form and surrounding the semiconductor chip  121 . The number of layers of heat dissipation portions  127   d  may be increased depending on desired heat dissipation performance, a size of the fan-out semiconductor package, and the like. In addition or optionally, the metal layer  126  may also extend from a lower surface of the recess portion  110 H inwardly of the frame  110  in a lateral direction. Since heat generated by the semiconductor chip  121 , and the like, may be effectively dissipated in the lateral direction by extension structures of the heat dissipation portions  127   d  and the metal layer  126  in the lateral direction, performance and stability of the fan-out semiconductor package may be improved. 
     Next, in another modified example of  FIG. 12 , grooves T may be formed in a surface of a metal layer  126  adjacent the semiconductor chip  121 . An adhesive member  125 , or the like, may be filled in the grooves T. The grooves T of the metal layer  126  may be formed by removing portions of the metal layer  126  by a sandblasting process, or the like, at the time of processing the recess portion  110 H. The semiconductor chip  121  may have higher structural stability by the grooves T. 
       FIGS. 13 through 17  are schematic views illustrating processes of manufacturing a fan-out semiconductor package according to an exemplary embodiment in the present disclosure. Structural features of the fan-out semiconductor package having the structure described above may be more clearly understood from a description for processes of manufacturing a fan-out semiconductor package. 
     First, referring to  FIG. 13 , the first insulating layer  111   a  may be prepared using a copper clad laminate (CCL), or the like, and the first and second wiring layers  112   a  and  112   b,  the first metal layer  126 , and the first connection via layers  113   a  may be formed on and in the first insulating layer  111   a  by any known plating process. Via holes for the first connection via layers  113   a  may be formed using a mechanical drill, a laser drill, or the like. Then, the second and third insulating layers  111   b  and  111   c  may be formed on opposite surfaces of the first insulating layer  111   a,  respectively. The second and third insulating layers  111   b  and  111   c  may be formed by laminating and then hardening an ABF, or the like. Then, the third and fourth wiring layers  112   c  and  112   d  and the second and third connection via layers  113   b  and  113   c  may be formed on and in the second and third insulating layers  111   b  and  111   c,  respectively, by any known plating process. Via holes for the second and third connection via layers  113   b  and  113   c  may also be formed using a mechanical drill, a laser drill, or the like. 
     Then, as illustrated in  FIG. 14 , the second passivation layer  152  may be attached to a first surface of the frame  110  prepared by the process described above, and a carrier film  200  such as a DCF, including an insulating layer  201  and a metal layer  202  may be attached to the second passivation layer  152 . Then, a dry film  250  such as a DFR may be attached to the other surface of the frame  110 , and the recess portion  110 H penetrating through the first and third insulating layers  111   a  and  111   c  may be formed by a sandblasting process. In this case, the metal layer  126  may serve as an etch stop layer. The formed recess portions  110 H may have the tapered shape. Then, the dry film  250  may be removed. 
     Then, as illustrated in  FIG. 15 , the first blocking structure  127  maybe formed on the sidewalls of the recess portion  110 H by sputtering, a plating process, or the like. Then, the third blocking structure  129  may be formed on the first blocking structure  127  in a form such as a closed loop form, or the like. In this case, the third blocking structure  129  and the conduction vias  143  may be formed together with each other. Then, the semiconductor chip  121  may be disposed in the recess portion  110 H so that the inactive surface is attached to the metal layer  126 . Any known adhesive member  125  such as a DAF may be used to attach the inactive surface to the metal layer  126 . Meanwhile, the semiconductor chip  121  may be attached in a state in which the metal bumps  121 B such as copper (Cu) pillars are formed on the connection pads  121 P. 
     Then, as illustrated in  FIG. 16 , at least portions of the frame  110  and the semiconductor chip  121  maybe encapsulated using the encapsulant  131 . The encapsulant  131  may be formed by laminating and then hardening an ABF, or the like. Then, the encapsulant  131  may be grinded so that a surface of the fourth wiring layer  112   d  and surfaces of the metal bumps  121 B are exposed. An upper surface of the encapsulant  131  may become flat by the grinding, and the upper surfaces of the metal bumps  121 B, upper surfaces of the third blocking structure  129 , and the like, may be exposed from the encapsulant  131  and coplanar with each other. 
     Then, as illustrated in  FIG. 17 , the second blocking structure  128  having the plate shape may be formed on the encapsulant  131 . In this process, the redistribution layer  142  may also be formed. Then, a photosensitive material, or the like, may be applied and be then hardened to form the insulating layer  141 , and the redistribution layer  142  and the connection vias  143  may be formed on and in the insulating layer  141  by a plating process. The connection member  140  may be formed by such a process. Then, the first passivation layer  151  may be formed on the connection member  140  by laminating and then hardening an ABF, or the like, and the carrier film  200  may be removed. Then, the underbump metal layers  160  may be formed by any known metallization method, and the electrical connection structures  170  may be formed by a reflow process, or the like, using solder balls, or the like, to obtain the fan-out semiconductor package  100  as illustrated in  FIG. 9 . In a case in which grooves T of the metal layer  126  are formed by removing portions of the metal layer  126  by a sandblasting process, or the like, at the time of processing the recess portion  110 H, the fan-out semiconductor package as illustrated in  FIG. 12  may be obtained. 
     As set forth above, according to the exemplary embodiments in the present disclosure, a fan-out semiconductor package including an effective electromagnetic wave blocking structure and having improved heat dissipation performance may be implemented. 
     While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims.