Patent Publication Number: US-2005132363-A1

Title: Method, apparatus and system for optimizing context switching between virtual machines

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
      The present application is related to co-pending U.S. patent application Ser. No. ______, entitled “Method, Apparatus and System for Optimizing Context Switching Between Virtual Machines,” Attorney Docket Number P18449, assigned to the assignee of the present invention (and filed concurrently herewith). 
    
    
     FIELD  
      The present invention relates to the field of virtualization, and, more particularly to a method, apparatus and system for optimizing context switching between virtual machines.  
     BACKGROUND  
      Virtualization technology enables a single host running a virtual machine monitor (“VMM”) to present multiple abstractions of the host, such that the underlying hardware of the host appears as one or more independently operating virtual machines (“VMs”). Each VM may therefore function as a self-contained platform, running its own operating system (“OS”), or a copy of the OS, and/or a software application. The operating system and application software executing within a VM is collectively referred to as “guest software.” The VMM performs “context switching” as necessary to multiplex between various virtual machines according to a “round-robin” or some other predetermined scheme. To perform a context switch, the VMM may suspend execution of a first VM, optionally save the current state of the first VM, extract state information for a second VM and then execute the second VM.  
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
      The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements, and in which:  
       FIG. 1  illustrates conceptually an example multi-core processor according to embodiments of the present invention;  
       FIG. 2  illustrates conceptually the various threads in a hyperthreaded processor according to an embodiment of the present invention; and  
       FIG. 3  is a flowchart illustrating an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION  
      Embodiments of the present invention provide a method, apparatus and system for optimizing context switching between VMs. Reference in the specification to “one embodiment” or “an embodiment” of the present invention means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment,” “according to one embodiment” or the like appearing in various places throughout the specification are not necessarily all referring to the same embodiment.  
      The VMM on a virtual machine host has ultimate control over the host&#39;s physical resources and, as previously described, the VMM allocates these resources to guest software according to a round-robin or some other scheduling scheme. Current VMM&#39;s rely on the same execution thread (e.g., a hardware thread, a processor core and/or a central processing unit) to perform context switching (i.e., to save/restore the state of virtual machines) and to run the virtual machines. Currently, when the VMM schedules another VM for execution, it suspends execution of the active VM, and restores the state of a previously suspended VM from memory and/or disk into the processor cache, then resumes execution of the newly restored VM. It may also save the execution state of the suspended VM from the processor cache into memory and/or disk. The VMM typically uses the same execution thread to save the execution state (i.e., the internal state of the processor cache when the current VM was context switched out, including the paging data structure, device state, program counters, stack pointers, etc.) of the current VM from the host&#39;s processor cache to a main storage location, such as memory and/or disk. The previously suspended state of a second virtual machine from main memory and/or disk is brought into the host&#39;s processor cache and the second virtual machine is allowed to execute. Storing and retrieving state information to and from memory and/or disk, and use of the same execution thread to perform all such tasks is a virtualization overhead that may result in delays that significantly degrade the host&#39;s overall performance and the performance of the virtual machines.  
      Embodiments of the present invention include an optimized method, apparatus and system for context switching between VMs. More specifically, embodiments of the present invention optimize the context switching between virtual machines by using a separate execution thread to restore the state of a new VM in parallel while the VMM is running the previous VM (i.e., using a different execution thread). As used herein, an execution thread may include a separate process on a host, a separate thread and/or a separate processor core on a multi-core processor. “Multi-core processors” are well known to those of ordinary skill in the art and include a chip that contains more than one processor core. Embodiments of the present invention may be implemented as software, hardware, firmware and/or as a combination thereof. For example, the VMM may be implemented as a software application, or device driver, or as part of the operating system, or as part of or embedded in a chipset or microprocessor, or as a combination thereof.  
       FIG. 1  and  FIG. 2  illustrate various embodiments of the present invention. In one embodiment, a hardware solution may include the use of a multi-core processor.  FIG. 2  illustrates an example multi-core processor according to embodiments of the present invention. In this example, Host  100  may include Processor  110  which includes Main Cache  120 , Processor Core  160  and Processor Core  165 , and Main Memory  115 . Although only two processor cores are illustrated, it will be readily apparent to those of ordinary skill in the art that multi-core processors may include additional cores. Host  100  may also be executing various virtual machines (“VM  150 ”-“VM  165 ”) managed by Enhanced VMM  175 . In this embodiment, while Processor Core  160  executes VM  150 , Enhanced VMM  175  may activate Processor Core  165  to take appropriate action to restore the state of VM  155 , including appropriately inserting data into Main Cache  120 . Thus, while Processor Core  160  continues to access Main Cache  120  for information pertaining to VM  150 , Processor Core  165  may be loading VM  155  state information into the same cache. The process of managing the information in Main Cache  120  from various processors is well known to those of ordinary skill in the art and further description thereof is omitted herein. When Enhanced VMM  175  performs the context switch, Processor Core  160  may immediately begin running VM  155  because Main Cache  120  already includes at least some state information necessary to run VM  155 .  
      In yet another embodiment, a hyperthreaded processor may be used to optimize context switching between virtual machines. Hyperthreaded processors (e.g., (Intel Corporation&#39;s Pentium® 4 Processor with Hyper-Threading Technology) are well known to those of ordinary skill in the art and include a single physical processor with multiple logical processors, each sharing the physical resources of the host.  FIG. 2  illustrates conceptually the various threads in a hyperthreaded processor according to an embodiment of the present invention. According to this embodiment, the threads on the hyperthreaded processor essentially represent virtual processors that enable separate execution threads to run the various virtual machines, and to store and/or restore the state information pertaining to various virtual machines. As illustrated, Host  200  may include hyperthreaded processor  205 , capable of multiple execution threads (illustrated as “Virtual Processor  210 ” and “Virtual Processor  215 ”), Main Memory  220  and Main Cache  225 . Although only two threads (i.e., virtual processors) are illustrated, it will be apparent to those of ordinary skill in the art that hyperthreaded processors may include additional threads. Host  200  may additionally include multiple virtual machines (illustrated as “VM  250 ” and “VM  255 ”), managed by Enhanced VMM  275 .  
      According to one embodiment, each thread on Host  200  may be assigned to a virtual machine. Thus, for example, Thread  205  may execute VM  250  while Thread  210  may execute VM  255 . In this embodiment, when Enhanced VMM  275  determines that it needs to perform a context switch from VM  250  to VM  255 , it may activate Thread  210  to begin retrieving state information for VM  255  into Main Cache  225 . Upon the context switch, Thread  205  may save the state information for VM  250  while Thread  210  begins execution of VM  255  using the state information already loaded into Main Cache  225 .  
      Although specific embodiments have been described in detail above, any of the above-described embodiments may be practiced separately or in combination, to achieve the same result. It will be readily apparent to those of ordinary skill in the art that these combinations of features may be practiced in various embodiments to further optimize context switching between VMs.  
       FIG. 3  is a flow chart of an embodiment of the present invention. Although the following operations may be described as a sequential process, many of the operations may in fact be performed in parallel and/or concurrently. In addition, the order of the operations may be re-arranged without departing from the spirit of embodiments of the invention. In  301 , a VMM may execute on a virtual machine host and start up a first VM. The state of the first VM may be saved when the VMM executes a second VM on the host in  302 . In  303 , the VMM may determine to context switch from the second VM back to the first VM and therefore activate a separate process to restore the state of the first VM. In  304 , the separate process may restore the state of the first VM, including inserting appropriate data in the host&#39;s processor cache. In  305 , the VMM may perform a context switch from the second VM to the first VM, and the state information of the second VM may then be saved concurrently while the first VM is running in  306 .  
      The hosts according to embodiments of the present invention may be implemented on a variety of computing devices. According to an embodiment of the present invention, computing devices may include various components capable of executing instructions to accomplish an embodiment of the present invention. For example, the computing devices may include and/or be coupled to at least one machine-accessible medium. As used in this specification, a “machine” includes, but is not limited to, any computing device with one or more processors. As used in this specification, a machine-accessible medium includes any mechanism that stores and/or transmits information in any form accessible by a computing device, the machine-accessible medium including but not limited to, recordable/non-recordable media (such as read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media and flash memory devices), as well as electrical, optical, acoustical or other form of propagated signals (such as carrier waves, infrared signals and digital signals).  
      According to an embodiment, a computing device may include various other well-known components such as one or more processors. As previously described, these computing devices may include multi-core processors and/or hyperthreaded processors. The processor(s) and machine-accessible media may be communicatively coupled using a bridge/memory controller, and the processor may be capable of executing instructions stored in the machine-accessible media. The bridge/memory controller may be coupled to a graphics controller, and the graphics controller may control the output of display data on a display device. The bridge/memory controller may be coupled to one or more buses. A host bus controller such as a Universal Serial Bus (“USB”) host controller may be coupled to the bus(es) and a plurality of devices may be coupled to the USB. For example, user input devices such as a keyboard and mouse may be included in the computing device for providing input data.  
      In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be appreciated that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.