Patent Publication Number: US-8969882-B1

Title: Transistor having an ohmic contact by screen layer and method of making the same

Description:
RELATED APPLICATIONS 
     The instant application is related to the following U.S. Patent Applications:
     U.S. Patent Application titled “TRANSISTOR HAVING PARTIALLY OR WHOLLY REPLACED SUBSTRATE AND METHOD OF MAKING THE SAME,” U.S application Ser. No. 13/944,779;   U.S. Patent Application titled “TRANSISTOR HAVING HIGH BREAKDOWN VOLTAGE AND METHOD OF MAKING THE SAME,” U.S application Ser. No. 13/944,713;   U.S. Patent Application titled “SEMICONDUCTOR DEVICE, HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) AND METHOD OF MANUFACTURING,” U.S application Ser. No. 13/944,625;   U.S. Patent Application titled “TRANSISTOR HAVING BACK-BARRIER LAYER AND METHOD OF MAKING THE SAME,” U.S application Ser. No. 13/944,584;   U.S. Patent Application titled “TRANSISTOR HAVING DOPED SUBSTRATE AND METHOD OF MAKING THE SAME,” U.S application Ser. No. 13/944,494;   U.S. Patent Application titled “TRANSISTOR HAVING A BACK-BARRIER LAYER AND METHOD OF MAKING THE SAME,” U.S application Ser. No. 13/944,672; and   U.S. Patent Application titled “TRANSISTOR HAVING OHMIC CONTACT BY AND METHOD OF MAKING THE SAME,” U.S application Ser. No. 14/010,268.   

     The entire contents of the above-referenced applications are incorporated by reference herein. 
     BACKGROUND 
     In semiconductor technology, Group III-Group V (or III-V) semiconductor compounds are used to form various integrated circuit devices, such as high power field-effect transistors, high frequency transistors, high electron mobility transistors (HEMTs), or metal-insulator-semiconductor field-effect transistors (MISFETs). A HEMT is a field effect transistor incorporating a junction between two materials with different band gaps (i.e., a heterojunction) as the channel instead of a doped region, as is generally the case for metal oxide semiconductor field effect transistors (MOSFETs). In contrast with MOSFETs, HEMTs have a number of attractive properties including high electron mobility and the ability to transmit signals at high frequencies, etc. However, consistently forming low resistance, ohmic contacts with HEMTs is often difficult. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       One or more embodiments are illustrated by way of example, and not by limitation, in the figures of the accompanying drawings, wherein elements having the same reference numeral designations represent like elements throughout. It is emphasized that, in accordance with standard practice in the industry various features may not be drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features in the drawings may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  is a cross-sectional view of a high electron mobility transistor (HEMT) having an active layer including a screen layer in accordance with one or more embodiments; 
         FIG. 2  is a flow chart of a method of making an HEMT having an active layer including a screen layer in accordance with one or more embodiments; and 
         FIGS. 3A-3C  are cross-sectional views of an HEMT having an active layer including a screen layer at various stages of production in accordance with one or more embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are examples and are not intended to be limiting. 
     High electron mobility transistor (HEMT) devices include one or more contact metals, such as titanium, for electrically coupling HEMTs. If, during fabrication, the metal contact is not diffused far enough (too shallow) into an HEMT structure, the metal and semiconductor will not form an acceptable ohmic contact. If the metal is diffused too far (too deep) into the HEMT structure, the metalcauses charge carrier leakage and therefore will not form an acceptable ohmic contact. Unfortunately, fabrication process variations both within and between semiconductor devices using HEMTs cause metal to be diffused too shallow or too deep in some circumstances. In other cases, fabrication processes result in non-uniform metal diffusion. As described herein, a screen layer makes it possible to reduce an effect of process variation on the depth of metal diffusion to more accurately and reliably achieve a more uniform metal diffusion depth, resulting in improved ohmic contacts in HEMT devices having metal-semiconductor junctions. 
       FIG. 1  is a cross-sectional view of a high electron mobility transistor (HEMT)  100  having an active layer  112  including a screen layer  124  in accordance with one or more embodiments. HEMT  100  includes a substrate  102 . A nucleation layer  104  is over substrate  102 . In some embodiments, nucleation layer  104  includes multiple layers, such as one or more seed layers. A buffer layer  106  is over nucleation layer  104 . A channel layer  108  is over buffer layer  106 . An active layer  112  is over the channel layer  108 . The active layer  112  includes a first portion  120  over channel layer  108 . In some embodiments, an interface layer  122 , such as an n-type GaN (n-GaN) layer, is over the screen layer  124 . Due to a band gap discontinuity between the channel layer  108  and the active layer  112 , a two dimension electron gas (2-DEG)  114  is formed in the channel layer  108  near an interface with the active layer  112 . A metal layer  115  includes electrodes  116  over the channel layer  108  and a gate  118  over active layer  112  between the electrodes  116 . 
     As explained below, screen layer  124  reduces the risk of diffusion of metal from one or more electrodes  116  into the channel layer  108 . In some embodiments the screen layer  124  includes aluminum nitride (AlN). 
     Substrate  102  acts as a support for HEMT  100 . In some embodiments, substrate  102  is a silicon substrate. In some embodiments, substrate  102  includes silicon carbide (SiC), sapphire, or another suitable substrate material. In some embodiments, substrate  102  is a silicon substrate having a (111) lattice structure. 
     Nucleation layer  104  helps to compensate for a mismatch in lattice structures between substrate  102  and buffer layer  106 . In some embodiments, nucleation layer  104  includes multiple layers. In some embodiments, nucleation layer  104  includes a same material or different materials formed at different temperatures. In some embodiments, nucleation layer  104  includes a step-wise change in lattice structure. In some embodiments, nucleation layer  104  includes a continuous change in lattice structure. In some embodiments, nucleation layer  104  is formed by epitaxially growing the nucleation layer on substrate  102 . 
     In at least one example, nucleation layer  104  comprises a first layer of aluminum nitride (AlN), a second layer of AlN over the first layer of AlN. The first layer of AlN, e.g., is formed at a low temperature, ranging from about 900° C. to about 1000° C., and has a thickness ranging from about 10 nanometers (nm) to about 50 nm. If the thickness of the first layer of AlN is too small, subsequent layers formed on the first layer of AlN will experience a high stress at the interface with the first AlN layer due to lattice mismatch increasing a risk of layer separation. If the thickness of the first layer of AlN is too great, the material is wasted and production costs increase. The second layer of AlN is formed, e.g., at a high temperature, ranging from about 1000° C. to about 1300° C., and has a thickness ranging from about 50 nm to about 200 nm. The higher temperature provides a different lattice structure in the second AlN layer in comparison with the first AlN layer. The lattice structure in the second AlN layer is more different from a lattice structure of substrate  102  than the first AlN layer. If the thickness of the second layer of AlN is too small, subsequent layers formed on the second layer of AlN will experience a high stress at the interface with the second layer of AlN due to lattice mismatch increasing the risk of layer separation. If the thickness of the second layer of AlN is too great, the material is wasted and production costs increase. 
     In some embodiments, nucleation layer  104  is omitted, and thus buffer layer  106  is directly on substrate  102 . 
     In at least one example, buffer layer  106  includes three graded layers. A first graded layer adjoins nucleation layer  104 . The first graded layer includes Al x Ga 1-x N, where x ranges from about 0.7 to about 0.9. A thickness of the first graded layer ranges from about 50 nm to about 200 nm. A second graded layer is on the first graded layer. The second graded layer includes Al x Ga 1-x N, where x ranges from about 0.4 to about 0.6. A thickness of the second graded layer ranges from about 150 nm to about 300 nm. A third graded layer is on the second graded layer. The third graded layer includes Al x Ga 1-x N, where x ranges from about 0.15 to about 0.3. A thickness of the third graded layer ranges from about 300 nm to about 500 nm. 
     If the buffer layer  106  is too thin, channel layer  108  will have a high stress at an interface with buffer layer  106  and increase the risk of separation between the buffer layer and the channel layer. If the buffer layer  106  is too thick, material is wasted and production costs increase. In some embodiments, the buffer layer  106  is formed at a temperature ranging from about 1000° C. to about 1200° C. 
     In some embodiments, buffer layer  106  provides a p-type doped layer to reduce electron injection from substrate  102 . Electron injection occurs when electrons from substrate  102  diffuse into the channel layer  108 . By including p-type dopants in buffer layer  106 , the electrons are trapped by the buffer layer and do not negatively impact performance of 2-DEG  114  in the channel layer. In some embodiments, the p-type dopants include carbon, iron, magnesium, zinc or other suitable p-type dopants. In some embodiments, a concentration of the p-type dopant is greater than or equal to about 1×10 19  ions/cm 3 . If the p-type dopant concentration is too low, buffer layer  106  will not be able to effectively prevent electron injection from substrate  102 . If the p-type dopant concentration is too high, p-type dopants will diffuse into the channel layer and negatively impact 2-DEG  114 . In some embodiments, buffer layer  106  is formed using an epitaxial process. In some embodiments, buffer layer  106  is formed at a temperature ranging from about 1000° C. to about 1200° C. 
     Channel layer  108  is used to help form a conductive path for selectively connecting electrodes  116 . In some embodiments, the channel layer  108  includes GaN. In some embodiments, the channel layer  108  has a p-type dopant concentration of equal to or less than 1×10 17  ions/cm 3 . In some embodiments, the channel layer  108  is an undoped layer or an unintentionally doped layer. In some embodiments, the channel layer  108  has a thickness ranging from about 0.5 μm to about 2.0 μm. In at least one example, the channel layer  108  has a thickness greater than 1.25 μm. If a thickness of the channel layer  108  is too thin, the channel layer will not provide sufficient charge carriers to allow HEMT  100  to function properly. If the thickness of the channel layer  108  is too great, material is wasted and production costs increase. In some embodiments, the channel layer  108  is formed by an epitaxial process. In some embodiments, the channel layer  108  is formed at a temperature ranging from about 1000° C. to about 1200° C. 
     Active layer  112  is used to provide the band gap discontinuity with the channel layer  108  to form 2-DEG  114 . In some embodiments, active layer  112  includes the first portion  120  over the channel layer  108  and a screen layer  124  over the first portion  120  and, in some embodiments, the active layer  112  further includes an interface layer  122  over the screen layer. 
     In some embodiments, the first portion  120  includes aluminum gallium nitride (Al y Ga (1-y) N), where y ranges from 0.25 to 1 and represents an aluminum content ratio. The first portion  120  is over and in contact with the channel layer  108 . In some embodiments, y is between about 0.25 and about 0.40. Having an aluminum concentration in these ranges enables an improved 2-DEG layer  114 . In some embodiments, the first portion  120  is between 10 nm and 30 nm thick. 
     In some embodiments, first portion  120  includes one or more ternary compound semiconductors other than Al y Ga (1-y) N, such as indium aluminum nitride (In z Al (1-z) N). In some embodiments, z ranges from about 0.25 to about 0.9. In some embodiments, first portion  120  includes a complex structure including multiple layers some having one continuous aluminum concentration or a gradient aluminum concentration. 
     Screen layer  124  is used to improve ohmic contact between one or more metal electrodes  116  and the active layer  112 . Screen layer  124 , in some embodiments, reduces fabrication costs and/or reduces the size of the resultant transistor. In some embodiments, screen layer  124  results in a more uniform ohmic contact (ρc), i.e., a more uniform distribution of metal particles, in an individual transistor as well as separate transistors located at various points on a wafer, when compared to devices lacking a screen layer  124 , and increase a yield of quality ohmic contacts. In some embodiments, screen layer  124  is over the first portion  120 . In some embodiments, screen layer  124  is under interface layer  122 . In some embodiments, screen layer  124  is under interface layer  122  and over first portion  120 . 
     In some embodiments, screen layer  124  is under a second portion (not shown) and over first portion  120 . The second portion is between the screen layer  124 , and when present, the interface layer  122 . In some embodiments, the second portion has the attributes of the first portion  124 . In some embodiments, the second portion has the same or different materials as that of the first portion  124 , and in some embodiments, the second portion has the same or different thickness as that of the first portion  124 . 
     In some embodiments, screen layer  124  includes AlN, SiO, Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , or a wide band gap material. In some embodiments, the wide band gap material has a band gap greater than 3.0 eV. In some embodiments, the screen layer  124  is chosen from V 2 O 3 , La 2 O 3 , ZrSiO 4 , and HfSiO 4 . In some embodiments, the screen layer  124  has a thickness less than or equal to 30 {acute over (Å)}. The presence of the screen layer improves ohmic contact between one or more metal electrodes  116  and the active layer  112  by controlling diffusion of metal particles from electrodes  116  through the active layer. A screen layer that is too thick impedes sufficient diffusion to facilitate ohmic contact. A screen layer that is too thin does not provide sufficient control over diffusion of the metal particles through active layer  112 . 
     The interface layer  122  is used to form a conductive path for selectively electrically coupling electrodes  116  and gate  118 . The interface layer  122 , in some embodiments, is a GaN or an n-GaN layer. In some embodiments, the n-type dopants include silicon, oxygen or other suitable n-type dopants. In some embodiments, the interface layer  122  is about 2 nm to about 5 nm thick. In some embodiments, the interface layer  122  is formed by performing an epitaxial process. In some embodiments, the epitaxial process includes a MOCVD process, a MBE process, an HVPE process or another suitable epitaxial process. 
     2-DEG  114  acts as the channel for providing conductivity between electrodes  116 . Electrons from a piezoelectric effect in active layer  112  drop into the channel layer, and thus create a thin layer of highly mobile conducting electrons in the channel layer. 
     Electrodes  116  act as a source and a drain for HEMT  100  for transferring a signal into or out of the HEMT. Gate  118  helps to modulate conductivity of 2-DEG  114  for transferring the signal between electrodes  116 . 
     HEMT  100  is normally conductive meaning that a positive voltage applied to gate  118  will reduce the conductivity between electrodes  116  along 2-DEG  114 . 
       FIG. 2  is a flow chart of a method  200  of making an HEMT having an active layer including a screen layer  124  in accordance with one or more embodiments. Method  200  begins with operation  202  in which a low temperature (LT) seed layer and a high temperature (HT) seed layer are formed on a substrate, e.g., substrate  102 . The LT seed layer is formed on the substrate and the HT seed layer is formed on the LT seed layer. 
     In some embodiments, LT seed layer and HT seed layer include AlN. In some embodiments, the formation of LT seed layer and HT seed layer are performed by an epitaxial growth process. In some embodiments, the epitaxial growth process includes a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, a hydride vapor phase epitaxy (HVPE) process or another suitable epitaxial process. In some embodiments, the MOCVD process is performed using aluminum-containing precursor and nitrogen-containing precursor. In some embodiments, the aluminum-containing precursor includes trimethylaluminium (TMA), triethylaluminium (TEA), or other suitable chemical. In some embodiments, the nitrogen-containing precursor includes ammonia, tertiarybutylamine (TBAm), phenyl hydrazine, or other suitable chemical. In some embodiments, the LT seed layer and/or the HT seed layer includes a material other than AlN. In some embodiments, the HT seed layer has a thickness ranging from about 50 nm to about 200 nm. In some embodiments, the HT seed layer is formed at a temperature ranging from about 1000° C. to about 1300° C. In some embodiments, the LT seed layer had a thickness ranging from about 10 nm to about 50 nm. In some embodiments, the LT seed layer is formed at a temperature ranging from about 900° C. to about 1000° C. 
     Method  200  continues with operation  204  in which a buffer layer is formed on the HT seed layer. In some embodiments, the buffer layer includes an aluminum-gallium nitride (Al x Ga (1-x) N) layer. In some embodiments, the aluminum gallium nitride layer has two or more aluminum-gallium nitride layers each having a different ratio x decreased from the bottom to the top. In some embodiments, each of the two or more aluminum-gallium nitride layers is formed by performing an epitaxial process. In some embodiments, the epitaxial process includes a MOCVD process, a MBE process, an HVPE process or another suitable epitaxial process. In some embodiments, the MOCVD process uses an aluminum-containing precursor, a gallium-containing precursor, and a nitrogen-containing precursor. In some embodiments, the aluminum-containing precursor includes TMA, TEA, or other suitable chemical. In some embodiments, the gallium-containing precursor includes trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemical. In some embodiments, the nitrogen-containing precursor includes ammonia, TBAm, phenyl hydrazine, or other suitable chemical. In some embodiments, the graded layer is formed at a temperature ranging from about 1000° C. to about 1200° C. 
     In at least one example, the buffer layer includes a first layer including Al x Ga 1-x N, where x ranges from about 0.7 to about 0.9. A thickness of the first layer ranges from about 50 nm to about 200 nm. A second layer is on the first layer. The second layer includes Al x Ga 1-x N, where x ranges from about 0.4 to about 0.6. A thickness of the second layer ranges from about 150 nm to about 300 nm. A third layer is on the second layer. The third layer includes Al x Ga 1-x N, where x ranges from about 0.15 to about 0.3. A thickness of the third layer ranges from about 300 nm to about 550 nm. 
       FIG. 3A  is a cross-sectional view of a HEMT following operation  204  in accordance with one or more embodiments. The HEMT includes substrate  102  and nucleation layer  104  on the substrate. Nucleation layer  104  includes an LT seed layer  104   a  on substrate  102 , a HT seed layer  104   b  on the LT seed layer. Buffer layer  106  is on HT seed layer  104   b . For the sake of simplicity, nucleation layer  104  is depicted as a single layer in the following cross-sectional views. 
     Returning to  FIG. 2 , in operation  206   a  channel layer is formed on the buffer layer. In some embodiments, the channel layer is formed by performing an epitaxial process. In some embodiments, the epitaxial process includes a MOCVD process, a MBE process, an HVPE process or another suitable epitaxial process. In some embodiments, the first portion of the channel layer has a thickness ranging from about 0.5 μm to about 2.0 μm. In some embodiments, the dopant concentration in the first portion of the channel layer is equal to or less than about 1×10 17  ions/cm 3 . In some embodiments, the first portion of the channel layer is formed at a temperature ranging from about 1000° C. to about 1200° C. 
       FIG. 3B  is a cross-sectional view of a HEMT following operation  206  in accordance with one or more embodiments. The HEMT includes channel layer  108  over buffer layer  106 . 
     Returning to  FIG. 2 , in operation  208  an active layer is formed on the channel layer. In some embodiments, the active layer includes a first portion. The first portion includes Al y Ga (1-y) N, where y is a decimal representing an aluminum content ratio. In some embodiments, y is between about 0.25 and about 1In some embodiments, y is between about 0.25 and about 0.40. The first portion is formable by performing an epitaxial process. In some embodiments, the epitaxial process includes a MOCVD process, a MBE process, HVPE process or another suitable epitaxial process. In some embodiments, the first portion has a thickness ranging from about 10 nm to about 30 nm. In some embodiments, the first portion is formed at a temperature ranging from about 1000° C. to about 1200° C. 
     In operation  209 , a screen layer is formed in the active layer. The screen layer is formed over the first portion. In some embodiments, the formation of the screen layer is performed by an epitaxial growth process. In some embodiments, the screen layer includes AlN. In some embodiments, the epitaxial growth process includes a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process, a hydride vapor phase epitaxy (HVPE) process or another suitable epitaxial process. In some embodiments, the MOCVD process is performed using aluminum-containing precursor and nitrogen-containing precursor. In some embodiments, the aluminum-containing precursor includes trimethylaluminium (TMA), triethylaluminium (TEA), or other suitable chemical. In some embodiments, the nitrogen-containing precursor includes ammonia, tertiarybutylamine (TBAm), phenyl hydrazine, or other suitable chemical. In some embodiments, the screen layer includes AlN formed at a temperature ranging from about 900° C. to about 1300° C., and has a thickness less than or equal to 30 {acute over (Å)}. In some embodiments, the screen layer is chosen from AlN, SiO, Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , or a wide band gap material. In some embodiments, the wide band gap material has a band gap greater than 3.0 eV. In some embodiments, the screen layer is chosen from V 2 O 3 , La 2 O 3 , ZrSiO 4 , and HfSiO 4 . 
       FIG. 3C  is a cross-sectional view of a HEMT following operation  208  in accordance with one or more embodiments. The HEMT includes active layer  112  on the channel layer  108 . The active layer  112  includes the first portion  120  and the screen layer  124 . 2-DEG  114  is formed in of the channel layer  108  due to the band gap discontinuity between the first portion  120  in the active layer  112  and the channel layer  108 . 
     Returning to  FIG. 2 , in operation  210  an interface layer is formed over the screen layer. In some embodiments, the interface layer includes an n-type GaN layer. The interface layer, in some embodiments, is an n-GaN layer. In some embodiments, the n-type dopants include silicon, oxygen or other suitable n-type dopants. In some embodiments, the interface layer is about 2 nm to about 5 nm thick. In some embodiments, the interface layer is formed by performing an epitaxial process. In some embodiments, the epitaxial process includes a MOCVD process, a MBE process, an HVPE process or another suitable epitaxial process. In some embodiments, operation  210  is omitted. 
     In operation  212 , electrodes and a gate are formed on the first portion. In some embodiments which include operation  210 , the electrodes and the gate are formed on the interface layer. In some embodiments, the electrodes and the gate include copper, aluminum, titanium or another suitable metallic material. The electrodes are formed over the first portion, and the gate is formed over the active layer. A metal layer is deposited over the first portion. A patterned photoresist layer is formed over the metal layer, and the metal layer is etched to form the electrodes over the openings and the gate over the upper surface of the active layer. In some embodiments, the metal layer for forming the electrodes or the gate includes one or more metallic materials. In some embodiments, the electrodes or the gate include one or more layers of metallic materials. In at least one embodiment, the electrodes or the gate include at least one barrier layer contacting the other portion of the channel layer and/or the active layer. 
     Following operation  212  the HEMT has a similar structure to HEMT  100  in  FIG. 1 . 
     One aspect of this description relates to a transistor. The transistor includes a substrate, a channel layer over the substrate and an active layer over the channel layer. The active layer includes a first portion and a screen layer over the first portion. The transistor includes a metal layer over the screen layer. 
     Another aspect of this description relates to a transistor. The transistor includes a substrate, an aluminum nitride (AlN) nucleation layer over the substrate, and an aluminum gallium nitride (Al y Ga (1-y) N) buffer layer over the AlN nucleation layer. The transistor further includes a GaN channel layer over the Al y Ga (1-y) N buffer layer and an active layer over the GaN channel layer, The active layer includes a first portion including aluminum gallium nitride (Al x Ga (1-x) N), a screen layer including AlN over the first portion and an n-type gallium nitride (n-GaN) layer over the screen layer. The transistor further includes a metal layer over the n-GaN buffer layer and a two dimensional electron gas (2-DEG) in the channel layer adjacent an interface between the channel layer and the first portion. 
     Still another aspect of this description relates to a method of making a transistor. The method includes forming a channel layer over a substrate. The method includes forming an active layer comprising a first portion over the channel layer and a screen layer over the first portion. 
     It will be readily seen by one of ordinary skill in the art that the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.