Patent Publication Number: US-8111217-B2

Title: Driving circuit for an OLED (organic light emission diode), in particular for a display of the AM-OLED type

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to a driving circuit of an OLED diode (organic light emission diode), and more particularly, but not exclusively, relates to a driving circuit for display applications of the AM-OLED type, and the following description is made with reference to this field of application by way of illustration only. 
     2. Description of the Related Art 
     As is known, visualization devices or displays using organic light emission diodes, also indicated as OLED display, acronym from the English: “Organic Light Emitting Diode”, have found greater use in recent years. 
     These OLED displays are generally used in place of the displays with liquid crystals, differently from those that do not require additional components for being illuminated. It is in fact known that the displays with liquid crystals do not produce light, but are illuminated by an external light source, while the OLED devices produce their own light due to the presence of at least one layer of organic material enclosed by suitable metallic layers with the functions of cathode and anode. In particular, due to the monopolar nature of this layer of organic material, the OLED devices conduct current only in one direction, thus behaving similarly to a diode; herefrom the name of O-LED, by way of similitude with LED (acronym from the English: “Light Emitting Diode”, i.e., light emission diode). 
     It is thus possible, by using these OLED diodes, to realize much thinner displays, even flexible and rollable, and requiring smaller amounts of energy to operate. 
     In its most general form, an OLED display is made of several overlapped layers. In particular, on a first transparent layer, which has protective functions, a transparent conductive layer is deposited serving as an anode; subsequently at least three organic layers are generally added: one for the injection of the holes, one for the transport of electrons, and, between them, the three electroluminescent materials (red, green and blue), arranged to form a single layer made of many elements, each of them being substantially realized by three colored microdisplays. Finally, a reflecting layer is deposited that serves as a cathode. 
     In spite of the multiple layers, the total thickness, without considering the transparent layer, is of about 300 nanometers, making these OLED displays particularly useful in miniaturized applications. 
     In general, to form a display, the OLED diodes are organized in a matrix of pixels and are connected to a driving circuit suitable for supplying each OLED diode of this matrix with a current value necessary to obtain the luminescence of the diode itself according to a suitable addressing scheme. 
     Driving circuits realized in TFT technology (acronym from the English “Thin Film Transistor”, i.e., a thin film transistor) are widely used. In this case they are OLED displays with active matrix or AM-OLED, acronym from the English: “Active Matrix—Organic Light Emitting Diode”. 
     In such a driving circuit, a TFT transistor is connected to each OLED diode of the matrix so that, by driving with a suitable voltage the control or gate terminal of this TFT transistor, it is possible to modulate the current supplying the OLED diode, thus obtaining colors of different gradation (generally indicated with the English words grey-level scale or several color scale). 
     In its most simple form, a driving circuit for an OLED diode is schematically shown in  FIG. 1 , globally indicated with 1. 
     This driving circuit  1  has an input terminal IN 1  receiving an input voltage signal Vdata and an output terminal OUT 1  connected to an OLED diode, indicated as OL, in turn connected to a first voltage reference, in particular a supply voltage reference VDD. 
     The driving circuit  1  essentially includes a first TFT driver transistor T 1 , inserted between the output terminal OUT 1  and a second voltage reference, in particular a ground GND, and a second TFT selection transistor T 2 , inserted between a control terminal or gate of the first TFT driver transistor T 1  and the input terminal IN 1  and having in turn a control or gate terminal receiving a select voltage signal Vsel. 
     The driving circuit  1  finally includes a storage capacitor Cs inserted between the gate terminal of the first TFT driver transistor T 1  and the ground GND. 
     Essentially, the first TFT driver transistor T 1  serves for driving the OLED diode OL, enabled by the second TFT selection transistor T 2 , which is essentially a switch driven by the select voltage signal Vsel. Moreover, the storage capacitor Cs preserves a piece of electric information (under the form of charge) for the gate terminal of the first TFT driver transistor T 1 , during the scanning of the other rows of the matrix of pixels, i.e., the so called frame time where the refresh of the whole image occurs. 
     In the embodiment shown in  FIG. 1 , the TFT transistors T 1  and T 2  are N-channel transistors or nTFT. 
     When the select voltage signal Vsel enables the transmission of the datum, i.e., of the input voltage signal Vdata, through the second TFT selection transistor T 2 , this input voltage signal Vdata is transferred to the gate terminal of the first TFT driver transistor T 1 , thus imposing that the current flowing to the OLED diode OL is given by the relation: 
                     I   DS     =       μ   0     ⁢     C   ox     ⁢       W   L     ·         (       V     GS   ⁢           ⁢   1       -     V     t   ⁢           ⁢   1         )     2     2                 (   1   )               
being
 
     I DS  the drain current value of the first TFT driver transistor T 1  transferred to the OLED diode OL; and 
     V GS1 , V t1 , COX, μ 0 , W and L are, respectively, the voltage value between the gate and source terminals, the threshold voltage value, the capacity by surface unit, the mobility of the charge carriers, the gate width and length of the first TFT driver transistor T 1 . 
     At the end of the so called timing diagram, i.e., of the temporal window wherein the driving signals of the single pixel are applied, the select voltage signal Vsel disables the transfer through the second TFT selection transistor T 2 , and the datum is maintained between the electrodes of the storage capacitor Cs. 
     From the equation (1), it is noted how the current I DS  that the OLED diode OL is supplied with quadratically depends on the threshold voltage value V t1  of the first TFT driver transistor T 1 . 
     Unfortunately, it is well known that in the TFT transistors a considerable variation of the threshold voltage can be registered, which is strongly correlated and sensitive to certain process parameters that are to be controlled in an accurate way. With the input voltage signal Vdata identical, a non uniformity follows of the luminosity of the pixels of the matrix of a same AM-OLED display, the driving circuit  1  not succeeding in supplying the OLED diodes of the matrix of pixels with a stable current value. 
       FIG. 2  shows the simulated progress of the current I DS  flowing through the OLED diode OL for three topologically identical circuits, but different as regards the threshold voltage value V t1  of the TFT driver transistor T 1  comprised therein. The simulations have been carried out with the software AIM-Spice 3.2, using, for the TFT transistors, the level  12 . 
     Moreover, a form ratio (W/L) of the two TFT transistors, T 1  and T 2 , has been considered, fixed at a value equal to (W/L) 1 =(10 μm)/(5 μm), and (W/L) 2 =(2 μm)/(2 μm), respectively, with values of the parameters μ 0  and V t1 , relative to the surface mobility of the carriers and to e threshold voltage, respectively fixed equal to 100 cm 2 /(Vs) and 2.0 V, with a value of the storage capacitor Cs equal to 1 pF. 
     From the simulations carried out, it has been verified that, by a variation of ±10% of the threshold voltage value V t1  of the first TFT driver transistor T 1 , a considerable difference is revealed in the values of the current I DS  that the OLED diode OL is supplied with. In particular, in correspondence with a variation of +10% (V t1 =2.2 V, curve F−), a current difference is revealed equal to 10.4% (indicated in the figure as DI−); in correspondence with a variation of −10% (V t1 =1.8 V, curve F+), it occurs instead that the current has a variation equal to 10.2% (indicated in the figure as DI+). 
     To overcome the above discussed problem of the luminosity variation between the pixels, different circuit solutions have been proposed using a greater number of devices, in particular TFT transistors. 
     A first known solution, proposed by S. H. Jung, W. J. Nam, and M. K. Han in the article entitled: “A New Voltage Modulated AMOLED Pixel Design Compensating Threshold Voltage Variation of Poly-Si TFTs”, School of Electrical Engineering, Seoul National University, Seoul, KOREA ISSN/0002-0966X/02/3 622•SID 02 DIGEST 301-0622-$1.00+0.00© 2002 SID, is a driving circuit realized with four TFT transistors with p channel or p-TFT and a storage capacitor, schematically shown in  FIG. 3  and globally indicated with 3. 
     This driving circuit  3  has an input terminal IN 3  receiving an input voltage signal Vdata and an output terminal OUT 3  connected to an OLED diode, always indicated as OL, in turn connected to a first voltage reference, in particular a ground GND. 
     As previously seen, the driving circuit  3  comprises a first TFT driver transistor T 1 , inserted between the output terminal OUT 3  and a second voltage reference, in particular a supply voltage reference VDD, and a second TFT selection transistor T 2  connected to the input terminal IN 3  and having in turn a control or gate terminal receiving a select voltage signal Vsel. 
     The driving circuit  3  also comprises first and second TFT discharge transistors, respectively T 3  and T 4 , diode-wise connected and inserted, in parallel to each other, between the second TFT selection transistor T 2  and the gate terminal of the first TFT driver transistor T 1 . 
     The driving circuit  3  further includes a storage capacitor Cs inserted between the supply voltage reference VDD and the gate terminal of the first TFT driver transistor T 1 . 
     As previously, the TFT transistors T 1  and T 2  operate, respectively, as driver and as switch, while the block formed by the transistors T 3  and T 4  allows to discharge the storage capacitor Cs for the refresh of the information and enhance the voltage value at the gate terminal of the first TFT driver transistor T 1  by an amount equal to the threshold voltage V t3  of the second TFT discharge transistor T 3 . 
     In fact, when the select voltage signal Vsel turns on the second TFT selection transistor T 2 , the datum is transferred to the gate terminal of the first TFT driver transistor T 1  through the second TFT discharge transistor T 3  which is diode-wise connected. The current transferred to the OLED diode OL is given, therefore, by the relation: 
                                I   DS          =       μ   0     ⁢     C   ox     ⁢       W   L     ·         (            V     GS   ⁢           ⁢   1            -          V     t   ⁢           ⁢   1              )     2     2                     =       μ   0     ⁢     C   ox     ⁢       W   L     ·         (       V   DD     -     V   data     +          V     t   ⁢           ⁢   3            -          V     t   ⁢           ⁢   1              )     2     2                       (   2   )               
wherein:
 
     I DS  is the drain current value of the first TFT driver transistor T 1  transferred to the OLED diode OL; 
     Vdata is the input voltage signal or datum; and 
     V GS1 , V t1 , COX, μ 0 , W and L are, respectively, the voltage value between the gate and source terminals, the threshold voltage values, the capacity by surface unit, the mobility of the charge carriers, the gate width and length of the first TFT driver transistor T 1 ; and 
     V t3  is the threshold voltage value of the second TFT discharge transistor T 3 . 
     If the electric characteristics of the first TFT driver transistor T 1  and of the second TFT discharge transistor T 3  are rather similar, |V t1 |≈|V t3 | can be supposed; the drain current I DS  will thus have the form: 
     
       
         
           
             
               
                 
                   
                      
                     
                       I 
                       DS 
                     
                      
                   
                   = 
                   
                     
                       μ 
                       0 
                     
                     ⁢ 
                     
                       C 
                       ox 
                     
                     ⁢ 
                     
                       
                         W 
                         L 
                       
                       · 
                       
                         
                           
                             ( 
                             
                               
                                 V 
                                 DD 
                               
                               - 
                               
                                 V 
                                 data 
                               
                             
                             ) 
                           
                           2 
                         
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     From the equation (3) it thus emerges that the driving circuit  3  allows to obtain a drain current value I DS  independent from the threshold voltage V t1  of the first TFT driver transistor T 1 . 
     However, the correct operation of the circuit is based on the assumption that the transistors T 1  and T 3  have the same threshold voltage, condition, which can be hardly obtained in the practice. 
     J. C. Goh, H. J. Chung, J. Jang and C. H. Han in the article entitled: “A New Pixel Circuit for Active Matrix Organic Light Emitting Diodes”, IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 9, September 2002 thus have proposed a further driving circuit able to solve this problem. This driving circuit is schematically shown in  FIG. 4 , globally indicated with 4, using four TFT N-channel transistors, or n-TFT and two capacitors. 
     The driving circuit  4  has an input terminal IN 4  receiving an input voltage signal Vdata and an output terminal OUT 4  connected to a OLED diode, always indicated as OL, in turn connected to a first voltage reference, in particular a ground GND. 
     As previously seen, the driving circuit  4  comprises a first TFT driver transistor T 1 , inserted between the output terminal OUT 4  and a second voltage reference, in particular a supply voltage reference VDD, and a second TFT selection transistor T 2 , inserted between a control or gate terminal of the first TFT driver transistor T 1  and the input terminal IN 4  and having in turn a control or gate terminal receiving a first select voltage signal Vsel 1 . 
     The driving circuit  4  also includes a third TFT selection transistor and a fourth TFT selection transistor, respectively T 3  and T 4 , inserted, in series with each other, between the output terminal OUT 4  and the input terminal IN 4  and having respective control or gate terminals, the first receiving a signal Vsel 1  and the second receiving a select voltage signal Vsel 2 . 
     The driving circuit  4  further includes a storage capacitor Cs inserted between an inner circuit node X 4  of interconnection between the third and fourth TFT selection transistors, T 3  and T 4 , and the supply voltage reference VDD, as well as a bootstrap capacitor Cb, inserted between the gate terminal of the first TFT driver transistor T 1  and the inner circuit node X 4 . 
     The driving circuit  4  provides a Timing diagram divided into three periods: 
     (1) a first initialization period; 
     (2) a second compensation period, and 
     (3) a third data-input period. 
     The waveforms relative to this Timing diagram are shown in  FIG. 5 . 
     In the initialization period, the first and the second select voltage signals, Vsel  1  and Vsel 2 , are led to a first voltage value or high value, enabling all the three TFT selection transistors T 2 , T 3  and T 4  and thus realizing the discharge of the bootstrap capacitor Cb. 
     In the compensation period, while the first select voltage signal Vsel 1  is maintained at the high level, the second select voltage signal Vsel 2  is led to a second value or low value causing the opening of the fourth TFT selection transistor T 4 . Moreover, thanks to the modulation of the input voltage signal Vdata which is led to an intermediate value, next to the value of the threshold voltage of the first TFT driver transistor T 1 , the operation of the first TFT driver transistor T 1  is forced to the underthreshold region. In this way, the voltage value between the gate and source terminals of this first TFT driver transistor T 1 , equal to V t1 , is applied to the electrodes of the bootstrap capacitor Cb and preserved for the last fraction of the frame time, i.e., the data-input period. 
     In particular, in this data-input period, the first select voltage signal Vsel 1  is led to the low value, while the second select voltage signal Vsel 2  is led to the high value, causing the opening of the second and third TFT selection transistors, T 2  and T 3  and the closing of the fourth TFT selection transistor T 4 . Moreover, the electric information is applied to the input voltage signal Vdata on the basis of the changes introduced. 
     In this way, the voltage at the gate terminal of the first TFT driver transistor T 1  is equal to Vdata+V t1 , and the drain current I DS  is given by the relation: 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           I 
                           DS 
                         
                         = 
                         
                           
                             μ 
                             0 
                           
                           ⁢ 
                           
                             C 
                             ox 
                           
                           ⁢ 
                           
                             
                               W 
                               L 
                             
                             · 
                             
                               
                                 
                                   ( 
                                   
                                     
                                       V 
                                       
                                         GS 
                                         ⁢ 
                                         
                                             
                                         
                                         ⁢ 
                                         1 
                                       
                                     
                                     - 
                                     
                                       V 
                                       
                                         t 
                                         ⁢ 
                                         
                                             
                                         
                                         ⁢ 
                                         1 
                                       
                                     
                                   
                                   ) 
                                 
                                 2 
                               
                               2 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             μ 
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                           ⁢ 
                           
                             C 
                             ox 
                           
                           ⁢ 
                           
                             
                               W 
                               L 
                             
                             · 
                             
                               
                                 
                                   ( 
                                   
                                     
                                       V 
                                       data 
                                     
                                     + 
                                     
                                       V 
                                       
                                         t 
                                         ⁢ 
                                         
                                             
                                         
                                         ⁢ 
                                         1 
                                       
                                     
                                     - 
                                     
                                       V 
                                       
                                         t 
                                         ⁢ 
                                         
                                             
                                         
                                         ⁢ 
                                         1 
                                       
                                     
                                   
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                                 2 
                               
                               2 
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                         
                           
                             μ 
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                           ⁢ 
                           
                             C 
                             ox 
                           
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                               W 
                               L 
                             
                             · 
                             
                               
                                 V 
                                 data 
                                 2 
                               
                               2 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     From the equation (4), it occurs that the driving circuit  4  obtains a drain current value I DS  independent from the threshold voltage V t1  of the first TFT driver transistor T 1 . 
     This solution, however, shows an important limit, due to the fact that its correct operation is tied to the application, during the second compensation period, of such a voltage intermediate value as to put the first TFT driver transistor T 1  in the underthreshold region. Given the impossibility to realize all the TFT transistors present in the driving circuit of a matrix of pixels with the same electric characteristics, it is thus difficult that the voltage intermediate value applied in this period can ensure, for all the driver transistors, a correct operation under the underthreshold condition. 
     The technical problem underlying the present disclosure is that of devising a driving circuit for a display of the AM-OLED type, having such structural and functional characteristics as to obtain a driving current value independent from the threshold voltage variations of the TFT transistors contained therein, overcoming the limits and the drawbacks still affecting the circuits realized according to the prior solutions. 
     BRIEF SUMMARY 
     The present disclosure provides a self-regulation of the circuit leading to the automatic identification of the threshold voltage of the driver transistors contained therein, such voltage being stored across a bootstrap capacitor. 
     On the basis of this disclosure, the technical problem is solved by the driving circuit of an OLED diode inserted between a first voltage reference and a second voltage reference and having at least one input terminal receiving an input voltage signal and an output terminal for the generation of a driving current of this OLED diode, the circuit including at least one driver transistor having a first conduction terminal connected to this first voltage reference, a second conduction terminal connected to this output terminal and a control terminal connected to at least one first capacitor and one second capacitor. 
     Advantageously according to the disclosure, the first capacitor is inserted between the control terminal and an inner circuit node and the second capacitor is inserted between this inner circuit node (X 2 ) and the second voltage reference. 
     Further advantageously, the driving circuit also includes:
         a first switch driven by a first select voltage signal and inserted between the input terminal and the inner circuit node;   a second and a third switch driven by a second select voltage signal, this second switch inserted between the first conduction terminal and the control terminal of the driver transistor, and the third switch inserted between the inner circuit node and the second voltage reference, in parallel with the second capacitor; and   a fourth switch driven by a third select voltage signal and inserted between the first voltage reference and the first conduction terminal of the driver transistor.       

     Advantageously, the first select voltage signal enables the opening of the first switch, the second select voltage signal enables the conduction of the second and third switches and the third select voltage signal enables the conduction of the fourth switch, triggering a charge step of the first capacitor with the function of a bootstrap at a voltage value higher than a threshold voltage value of the driver transistor. 
     Further advantageously, a switch of the third select voltage signal enables the opening of the fourth switch, triggering a discharge step of the first bootstrap capacitor, a voltage value across it being led to a value equal to the threshold voltage of the driver transistor. 
     Moreover, a switch of the first, second and third select voltage signal enables the opening of the second and third switch and the closing of the first and fourth switch, respectively, thus applying to the control terminal of the driver transistor a voltage equal to the sum of the input voltage signal and of the voltage value stored in the first bootstrap capacitor, equal to the threshold voltage value of the driver transistor and generating the driving current according to the following relation: 
                     I   DS     =       μ   0     ⁢     C   ox     ⁢       W   L     ·         (       V     GS   ⁢           ⁢   1       -     V     t   ⁢           ⁢   f   ⁢           ⁢   1         )     2     2                     =       μ   0     ⁢     C   ox     ⁢       W   L     ·         (       V   data     +     V     t   ⁢           ⁢   f   ⁢           ⁢   1       -     V     t   ⁢           ⁢   f   ⁢           ⁢   1         )     2     2                     =       μ   0     ⁢     C   ox     ⁢       W   L     ·       V   data   2     2                     
wherein:
 
     V GS1 , V tf1 , COX, μ 0 , W and L are, respectively, the voltage value between the gate and source terminals, the threshold voltage value, the capacity by surface unit, the mobility of the charge carriers, the gate width and length of said driver transistor. 
     Finally, the switch of the first, second and third select enable signal enables the storage in the second capacitor of the charge supplied to the control terminal of the driver transistor until a new input voltage signal comes. 
     Further advantageously, the driver transistor and the switches are realized by respective thin film N-channel transistors. 
     The problem is also solved by a method for generating a driving current of an OLED diode by means of a driving circuit thus made, the method including, in sequence, the steps of:
         initialization, wherein the first select voltage signal is at a first level enabling the opening of the first switch, the second select voltage signal is led to a second level, enabling the closing of the second switch and of the third switch and the third select voltage signal is at this second level, enabling the closing of the fourth switch, triggering a charge step of the first capacitor with the function of a bootstrap at a voltage value higher than a threshold voltage value of the driver transistor;   compensation, wherein the first and the second select voltage signals, are maintained at the same level as in the previous initialization step, respectively the first level and second level, while the third select voltage signal is led to the first level, enabling the opening of the fourth switch, the first switch keeping open, thus triggering a discharge step of the first bootstrap capacitor, a voltage value across this capacitor being led to a value equal to the threshold voltage of the driver transistor; and   data-input, wherein the first and the third select voltage signals are led to the second level and the second select voltage signal is led to the first level, enabling the opening of the second and third switches and the closing of the first and fourth switches, respectively, thus applying to the control terminal of the driver transistor a voltage equal to the sum of the input voltage signal and of the voltage value stored in the first bootstrap capacitor, equal to the threshold voltage value of the driver transistor and generating the driving current according to the following relation:       

                           I   DS     =       μ   0     ⁢     C   ox     ⁢       W   L     ·         (       V     GS   ⁢           ⁢   1       -     V     t   ⁢           ⁢   f   ⁢           ⁢   1         )     2     2                     =       μ   0     ⁢     C   ox     ⁢       W   L     ·         (       V   data     +     V     t   ⁢           ⁢   f   ⁢           ⁢   1       -     V     tf   ⁢           ⁢   1         )     2     2                     =       μ   0     ⁢     C   ox     ⁢       W   L     ·       V   data   2     2                       (   5   )               
wherein:
 
     V GS1 , V tf1 , COX, μ 0 , W and L are, respectively, the voltage value between the gate and source terminals, the threshold voltage value, the capacity by surface unit, the mobility of the charge carriers, the gate width and length of the driver transistor. 
     In accordance with another embodiment of the present disclosure, a circuit is provided that includes a driver transistor having a first terminal coupled to a first voltage reference, a second terminal coupled to an output that is coupled to a second voltage reference, and a control terminal; a first capacitor coupled to a first node and to the control terminal of the driver transistor; a second capacitor coupled to the first node and to the second voltage reference; a first switch coupled between an input terminal and the first node; a second switch coupled between the first terminal of the driver transistor and the control terminal of the driver transistor; a third switch coupled between the second capacitor and the second voltage reference; and a fourth switch coupled between the first voltage reference and the first terminal of the driver transistor. 
     In accordance with another aspect of the foregoing embodiment, the driving circuit generates a driving current on an output at the second terminal of the driver transistor in accordance with the following relationship: 
                     I   DS     =       μ   0     ⁢     C   ox     ⁢       W   L     ·         (       V     GS   ⁢           ⁢   1       -     V     t   ⁢           ⁢   f   ⁢           ⁢   1         )     2     2                     =       μ   0     ⁢     C   ox     ⁢       W   L     ·         (       V   data     +     V     t   ⁢           ⁢   f   ⁢           ⁢   1       -     V     tf   ⁢           ⁢   1         )     2     2                     =       μ   0     ⁢     C   ox     ⁢       W   L     ·       V   data   2     2                     
wherein: V GS1 , V tf1 , COX, μ 0 , W and L are, respectively, the voltage value between the gate and source terminals, the threshold voltage value, the capacity by surface unit, the mobility of the charge carriers, the gate width and length of said driver transistor.
 
     In accordance with another aspect of the foregoing embodiment, the first capacitor is adapted to be charged to a higher voltage than the threshold voltage value of the driver transistor. Ideally, when the first capacitor is adapted to be charged, the first switch is open, and the second, third, and fourth switches are closed. 
     Accordance with another embodiment of the present disclosure, a display device is provided that includes a plurality of organic light emission diodes (OLEDs); and a circuit for driving each OLED, the circuit including: a driver transistor having a first terminal coupled to a first voltage reference, a second terminal coupled to an output that is coupled to a second voltage reference, and a control terminal; a first capacitor coupled to a first node and to the control terminal of the driver transistor; a second capacitor coupled to the first node and to the second voltage reference; a first switch coupled between an input terminal and the first node; a second switch coupled between the first terminal of the driver transistor and the control terminal of the driver transistor; a third switch coupled between the second capacitor and the second voltage reference; and a fourth switch coupled between the first voltage reference and the first terminal of the driver transistor. 
     In accordance with another aspect of the foregoing embodiment, the driving circuit generates a driving current on an output at the second terminal in accordance with the following relationship: 
                     I   DS     =       μ   0     ⁢     C   ox     ⁢       W   L     ·         (       V     GS   ⁢           ⁢   1       -     V     t   ⁢           ⁢   f1         )     2     2                     =       μ   0     ⁢     C   ox     ⁢       W   L     ·         (       V   data     +     V     t   ⁢           ⁢   f1       -     V     tf   ⁢           ⁢   1         )     2     2                     =       μ   0     ⁢     C   ox     ⁢       W   L     ·       V   data   2     2                     
wherein: V GS1 , V tf1 , COX, μ 0 , W and L are, respectively, the voltage value between the gate and source terminals, the threshold voltage value, the capacity by surface unit, the mobility of the charge carriers, the gate width and length of said driver transistor.
 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The characteristics and the advantages of the driving circuit according to the disclosure will be apparent from the following description of an embodiment thereof given by way of indicative and non limiting example with reference to the annexed drawings. 
       In these drawings: 
         FIG. 1  schematically shows a first embodiment of a driving circuit according to a prior solution; 
         FIG. 2  schematically shows the progress of a current signal obtained by the driving circuit of  FIG. 1 ; 
         FIG. 3  schematically shows a second embodiment of a driving circuit according to a prior solution; 
         FIG. 4  schematically shows a third embodiment of a driving circuit according to the a prior solution; 
         FIG. 5  schematically shows the progress of control signals of the driving circuit of  FIG. 4 ; 
         FIG. 6A  schematically shows a driving circuit realized according to the present disclosure; 
         FIG. 6B  shows a simplified schematization of the driving circuit of  FIG. 6A ; 
         FIG. 7  schematically shows the progress of control signals of the driving circuit of  FIG. 6A ; 
         FIG. 8  schematically shows a circuit equivalent of the driving circuit of  FIG. 6A  under a first operation condition; 
         FIG. 9  schematically shows the progress of a voltage signal obtained by the driving circuit of  FIG. 6A  under the first operation condition; 
         FIG. 10  schematically shows a circuit equivalent of the driving circuit of  FIG. 6A  under a second operation condition; 
         FIG. 11  schematically shows the progress of a voltage signal obtained by the driving circuit of  FIG. 6A  under the second operation condition; 
         FIG. 12  schematically shows a circuit equivalent of the driving circuit of  FIG. 6A  under a third operation condition; 
         FIG. 13  schematically shows the progress of a current signal obtained by the driving circuit of  FIG. 6A ; 
         FIG. 14  schematically shows an enlarged view of the progress of a portion of the current signal of  FIG. 13 ; 
         FIG. 15  schematically shows the luminosity characteristic curve as a function of the current of an OLED diode for mobile phone applications; and 
         FIG. 16  schematically shows a portion of an AM-OLED display. 
     
    
    
     DETAILED DESCRIPTION 
     With reference to these figures, and in particular to  FIGS. 6A and 6B , reference numeral  10  globally and schematically indicates a driving circuit for an AM-OLED display realized according to the present disclosure. 
     The driving circuit  10  includes five active devices, in particular TFT N-channel transistors or n-TFT, and two passive devices, in particular two capacitors. 
     More in detail, the driving circuit  10  has an input terminal IN receiving an input voltage signal Vdata or datum and an output terminal OUT connected to an OLED diode, indicated with OL, in turn connected to a first voltage reference, in particular a ground GND. The output terminal OUT supplies the OLED diode OL with a driving current IDS. 
     The driving circuit  10  includes a TFT driver transistor TF 1  connected between a second voltage reference, in particular a supply voltage reference VDD via internal circuit node X 3 , and the output terminal OUT and a first TFT selection transistor TF 2 , in turn connected to the input terminal IN and having a control or gate terminal receiving a first select voltage signal Vsel_ 1 . In particular, the first TFT selection transistor TF 2  realizes a switch controlled by the first select voltage signal Vsel_ 1 . 
     Advantageously, the driving circuit  10  also includes at least one second and one third TFT selection transistor, respectively TF 3  and TF 4 , inserted, in series with each other, between the supply voltage reference VDD via internal circuit node X 3  and the ground GND and having a respective control or gate terminal receiving a second select voltage signal Vsel_ 2 . Similarly, the second and third TFT selection transistors, TF 3  and TF 4 , realize respective switches controlled by the second select voltage signal Vsel_ 2 . 
     The driving circuit  10  further includes a storage capacitor Cst inserted between the first TFT selection transistor TF 2  and the ground GND, as well as a bootstrap capacitor Cbs inserted between the second TF 3  and the third TFT selection transistors TF 4 . 
     More in detail, the second TFT transistor TF 3  is inserted between the supply voltage reference VDD and a control or gate terminal of the TFT driver transistor TF 1 , indicated as first inner circuit diode X 1 , the bootstrap capacitor Cbs is inserted between the first inner circuit node X 1  and the conduction terminal of the first TFT selection transistor TF 2 , indicated as second inner circuit node X 2 , the third TFT selection transistor TF 4  is inserted between the second inner circuit node X 2  and the ground GND, and the storage capacitor Cst is inserted, in parallel with the third TFT selection transistor TF 4 , between the second inner circuit node X 2  and the ground GND. 
     Further advantageously, the driving circuit  10  includes a fourth TFT selection transistor TF 5 , inserted between the supply voltage reference VDD and the TFT driver transistor TF 1  and having a control or gate terminal receiving a third select voltage signal Vsel_ 3 . In this case, the fourth TFT selection transistor TF 5  realizes a switch controlled by the third select voltage signal Vsel_ 3 . More in particular, the fourth TFT selection transistor TF 5  is inserted between the supply voltage reference VDD and a conduction terminal of the TFT driver transistor TF 1 , indicated as a third inner circuit node X 3 , in turn connected to the second TFT selection transistor TF 3 . 
     In substance, in its most simple form, the driving circuit  10  according to the disclosure includes at least one driver transistor suitably connected to the supply voltage references and ground as well as to two capacitors through four driven switches. A schematization of the driving circuit  10  is reported in  FIG. 6B . 
     The driving circuit  10  includes at least one driver transistor TP connected to the output terminal OUT for the generation of the driving current IDS of the OLED diode OL. As previously seen, the driver transistor TP is realized by the transistor TFT TF 1 . 
     Advantageously, the driving circuit  10  also includes a bootstrap capacitor Cbs inserted between a control terminal X 1  of the driver transistor TP and a second inner circuit node X 2  and a storage capacitor Cst inserted between the second inner circuit node X 2  and the ground GND. 
     The second inner circuit node X 2  is also connected to the input terminal IN of the driving circuit  10  through a first switch SW 1  driven by the first select voltage signal Vsel_ 1 . The first switch SW 1  is realized by the first TFT selection transistor TF 2 . 
     Further advantageously, the driving circuit  10  also has second and third switches, SW 2  and SW 3 , driven by the second select voltage signal Vsel_ 2 . In particular, the second switch SW 2  is inserted between a conduction terminal, corresponding to a third inner circuit node X 3 , and the control terminal X 1  of the driver transistor TP, while the third switch SW 3  is inserted between the second inner circuit node X 2  and the ground GND, in parallel to the storage capacitor Cst. The second and third switches, SW 2  and SW 3 , are realized by the second and third TFT selection transistors, TF 3  and TF 4 , respectively. 
     Finally, the driving circuit  10  includes a fourth switch SW 4  driven by the third select voltage signal Vsel_ 3  and inserted between the supply voltage reference VDD and the third inner circuit node X 3 . The fourth switch SW 4  is realized by the fourth TFT selection transistor TF 5 . 
     Described in more detail below is the operation of the driving circuit  10  according to the disclosure. 
     Advantageously, the select voltage signals, Vsel_ 1 , Vsel_ 2 . and Vsel_ 3  divide the Timing diagram into three periods: 
     (1) a first initialization period P 1 ; 
     (2) a second compensation period P 2 ; and 
     (3) a third data-input period P 3 . 
     The waveforms taken by the select voltage signals, Vsel_ 1 , Vsel_ 2 , and Vsel_ 3  relative to a Timing diagram are shown in  FIG. 7 . 
     An initial condition is considered in which the first and the second select voltage signals, Vsel_ 1  and Vsel_ 2 , are at a first level, in particular low, while the third select voltage signal, Vsel_ 3 , is at a second level, in particular high. 
     In the first initialization period P 1 , the second select voltage signal, Vsel_ 2 , is led to a high level, enabling the second and the third TFT selection transistors, TF 3  and TF 4 . Similarly, the third select voltage signal, Vsel_ 3 , is led to a high level enabling the fourth TFT selection transistor TF 5 . 
     In this way a charge step of the bootstrap capacitor Cbs is triggered at a voltage value higher than the threshold voltage value Vtf 1  of the TFT driver transistor TF 1 . 
     In the second compensation period P 2 , the first and second select voltage signals, Vsel_ 1  and Vsel_ 2 , are maintained at the same level, respectively low and high, while the third select voltage signal Vsel_ 3  is led to a low value, opening the fourth TFT selection transistor TF 5 , with the first TFT selection transistor TF 2  keeping open. 
     In this way a discharge step of the bootstrap capacitor Cbs is triggered and the voltage across it is led to a value equal exactly to the threshold voltage Vtf 1  of the TFT driver transistor TF 1 . 
     In the third data-input period P 3 , all the select voltage signals change level. In particular, the first select voltage signal Vsel_ 1  and the third select voltage signal Vsel_ 3  are led to the high level and the second select voltage signal Vsel_ 2  is led to the low level, opening the second and the third TFT selection transistors, TF 3  and TF 4 , and closing the first and the fourth TFT selection transistors, TF 2  and TF 5 . It is thus possible to apply to the input voltage signal Vdata the electric information, i.e., a voltage corresponding to the luminosity value that is to be taken by the corresponding pixel, as indicated by its enhancement to the high level. 
     In this third data-input period P 3 , the voltage value applied to the gate terminal of the TFT driver transistor TF 1  is thus equal to Vdata+Vtf 1 , and its drain current I DS  is given by the following relation: 
                           I   DS     =       μ   0     ⁢     C   ox     ⁢       W   L     ·         (       V     GS   ⁢           ⁢   1       -     V     t   ⁢           ⁢   f   ⁢           ⁢   1         )     2     2                     =       μ   0     ⁢     C   ox     ⁢       W   L     ·         (       V   data     +     V     t   ⁢           ⁢   f   ⁢           ⁢   1       -     V     tf   ⁢           ⁢   1         )     2     2                     =       μ   0     ⁢     C   ox     ⁢       W   L     ·       V   data   2     2                       (   5   )               
corresponding to the equation (4) seen with reference to the prior solution, also in this case being:
 
     I DS  is the value of the drain current of the first TFT driver transistor T 1  transferred to the OLED diode OL; 
     Vdata is the input voltage signal or datum; and 
     V GS1 , V tf1 , COX, μ 0 , W and L are, respectively, the voltage value between the gate and source terminals, the threshold voltage value, the capacity by surface unit, the mobility of the charge carriers, the gate width and length of the TFT driver transistor TF 1 . 
     The storage capacitor Cst stores the charge supplied to the gate terminal of the TFT driver transistor TF 1 , i.e., to the first inner circuit node X 1 , until a new input voltage signal Vdata comes. 
     In substance, advantageously according to this disclosure, the first select voltage signal Vsel_ 1  enables the opening of the first switch SW 1 , the second select voltage signal Vsel_ 2  enables the conduction of the second and of the third switches, SW 2  and SW 3 , and the third select voltage signal Vsel_ 3  enables the fourth switch SW 4 , triggering a charge step of the bootstrap capacitor Cbs at a voltage value higher than the threshold voltage value Vtf 1  of the driver transistor TP. 
     Moreover, the switch of the third select voltage signal Vsel_ 3  enables the opening of the fifth switch SW 4 , triggering a discharge step of the bootstrap capacitor Cbs, thereby the voltage across it is led to a value equal to the threshold voltage Vtf 1 . 
     Finally, a switch of the first, second and third select voltage signals, Vsel_ 1 , Vsel_ 2 , and Vsel_ 3 , enables the opening of the second and of the third switches, SW 2  and SW 3 , and the closing of the first and of the fourth switches, SW 1  and SW 4 , respectively, thus applying to the control terminal X 1  of the driver transistor TP a voltage equal to the sum of the input voltage signal Vdata and of the voltage value stored in the bootstrap capacitor Cbs, equal to the threshold voltage value Vtf 1  of the driver transistor TP and generating the driving current IDS according to the above indicated relation (5). 
     To better understand the operation of the driving circuit  10 , it is possible to refer to its circuit equivalents in the different operative steps, i.e., in the different periods in the Timing diagram, as hereafter described. 
     First Initialization Period P 1   
     The driving circuit  10 , taking into account the sole transistors at stake, is reduced to its equivalent  10   P1  of  FIG. 8 . 
     In this first initialization period P 1 , the charge of the bootstrap capacitor Cbs is determined at a value higher than the threshold voltage Vtf 1  of the TFT driver transistor TF 1 . 
     The progress of the voltage VX 1  in the first inner circuit node X 1  is reported in  FIG. 9 , where the value of the threshold voltage Vtf 1  of the TFT driver transistor TF 1  has been indicated with a dotted line. 
     It is then observed, as already previously introduced, that the value of the voltage VX 1  of the first inner circuit node X 1  at the end of the first initialization period P 1  exceeds the value of the threshold value Vtf 1  of the TFT driver transistor TF 1 . 
     Second compensation period P 2   
     With the opening of the fourth TFT selection transistor TF 5  and with the first TFT selection transistor TF 2  kept open, the driving circuit  10  is reduced to its equivalent  10   P2  of  FIG. 10 . 
     Across the bootstrap capacitor Cbs a voltage value equal to the threshold voltage Vtf 1  of the TFT driver transistor TF 1  is automatically stored, without the need of any external intervention. The driving circuit  10  according to the disclosure is thus self-regulated and enables storing in the bootstrap capacitor Cbs the exact value of the threshold voltage Vtf 1  of the TFT driver transistor TF 1 , a value necessary for the compensation of the drain current IDS supplied on the output terminal OUT of the driving circuit  10  itself. 
     In fact, advantageously according to the disclosure, the bootstrap capacitor Cbs, when the voltage across it is higher than the threshold voltage value Vtf 1  of the TFT driver transistor TF 1 , determines the conduction of this transistor, which in turn triggers the discharge step of the bootstrap capacitor Cbs. This discharge step goes on until the voltage value across the bootstrap capacitor Cbs reaches exactly the desired value of the threshold voltage Vtf 1  of the TFT driver transistor TF 1 . 
     At this point, the TFT driver transistor TF 1  is disabled and the bootstrap capacitor Cbs maintains the voltage value attained, i.e., the value of the threshold voltage Vtf 1  of the TFT driver transistor TF 1 , as schematically shown in  FIG. 11  where the progress of the voltage in the first inner circuit node X 1 , connected to the bootstrap capacitor Cbs, is shown. 
     In this way, to overcome the drawbacks highlighted in connection with the known driving circuits, independently from the value of the threshold voltage Vtf 1  of the TFT driver transistor TF 1 , a self-regulation occurs of the driving circuit  10  that leads to the storage, always, of this value of threshold voltage Vtf 1  across the bootstrap capacitor Cbs. 
     Third Data-Input Period P 3   
     With the opening of the second and of the third TFT selection transistors, TF 3  and TF 4 , and the closing of the first and fourth selection transistors, TF 2  and TF 5 , the driving circuit  10  is reduced to its equivalent  10   P3  of  FIG. 12 . 
     In this period the driving in voltage of the OLED diode OL occurs with a current IDS having the expression defined in the above reported equation (5). 
     In particular, since in the bootstrap capacitor Cbs a voltage value equal to the threshold voltage value Vtf 1  of the TFT driver transistor TF 1  is stored, when one acts with the input voltage signal Vdata, the voltage value in the first inner circuit node X 1  is equal to Vdata+Vtf 1 . 
     The present disclosure thus relates to a method for generating a driving current IDS of an OLED diode OL in a matrix of pixels of an AM-OLED display by means of a driving circuit of the illustrated type, the method including, in sequence, the steps of:
         initialization, in which the first select voltage signal Vsel_ 1  is at a first level, in particular a low level, determining the opening of the first switch SW 1 , the second select voltage signal Vsel_ 2  is led to a second level, in particular a high level, enabling the second and the third switches, SW 2  and SW 3 , and the third select voltage signal Vsel_ 3  is at the high level, enabling the fourth switch SW 4  triggering a charge step of the bootstrap capacitor Cbs at a voltage value higher than the threshold voltage value Vtf 1  of the driver transistor TP;   compensation, in which the first and second select voltage signals, Vsel_ 1  and Vsel_ 2 , are maintained at the same level, respectively low and high, while the third select voltage signal Vsel_ 3  is led to the low level, opening the fourth switch SW 4 , the first switch SW 1  keeping open, thus triggering a discharge step of the bootstrap capacitor Cbs and the voltage across it is led to a value exactly equal to the threshold voltage Vtf 1  of the driver transistor TP; and   data-input, in which the first select voltage signal Vsel_ 1  and the third select voltage signal Vsel_ 3  are led to the high level and the second select voltage signal Vsel_ 2  is led to the low level, opening the second and the third switches, SW 2  and SW 3 , and closing the first and the fourth switches, SW 1  and SW 4 , respectively, applying to the gate terminal of the driver transistor TP a voltage equal to the sum of the input voltage signal Vdata and of the voltage value stored in the bootstrap capacitor Cbs, equal to the value of threshold voltage Vtf 1  of the driver transistor TP, and generating a driving current I DS  given by the above reported relation (5).       

     In particular, in the data-input step, the storage capacitor Cst stores the charge supplied to the gate terminal of the driver transistor TP, i.e., to the first inner circuit node X 1 , until a new input voltage signal Vdata is received. 
     Moreover, in the compensation step, the bootstrap capacitor Cbs, when the voltage across it is higher than the value of the threshold voltage Vtf 1  of the driver transistor TP, determines the conduction of this transistor, which, in turn, triggers the discharge step of the bootstrap capacitor Cbs, which goes on until the voltage value across the bootstrap capacitor Cbs reaches exactly the desired value of the threshold value Vtf 1  of the driver transistor TP when the driver transistor TP is disabled and the bootstrap capacitor Cbs maintains the voltage value attained, i.e., the value of the threshold voltage Vtf 1  of the driver transistor TP, as previously explained. 
     It is to be emphasized that the driving circuit  10  according to the disclosure is rather strong against the possible variations of the threshold voltage values of the TFT transistors contained therein for the driving of the OLED diodes. In this way, the problems connected to the lightning uniformity of a display of the AM-OLED type are overcome, i.e., of a display having a matrix of pixels including a plurality of these OLED diodes, driven by means of a driving circuit of the type described. 
     In particular, simulations carried out by the applicant with a driving circuit  10  including TFT transistors with the following form factors or dimensional relations:
         W/L=(10 μm)/(2 μm) for the TFT driver transistor TF 1  and for the fourth TFT selection transistor TF 5 ; and   W/L=(2 μm)/(2 μm) for the TFT selection transistors, TF 2 , TF 3  and TF 4 ,       

     and with values of the storage Cst and bootstrap Cbs capacitors equal to 1 pF, have revealed negligible variations of the driving drain current IDS of the OLED diode OL when the threshold voltage Vtf 1  of the TFT driver transistor TF 1  varies, as shown in  FIG. 13 . 
     In particular, it is immediately verified that, when the threshold voltage Vtf 1  varies of ±10% (Vtf1=2.0±0.2 V), the current IDS supplied to the OLED diode OL suffers from this variation in a negligible way. 
     To appreciate this infinitesimal variation, an enlargement of the portion A of  FIG. 13  is shown in  FIG. 14 , the curves f 1 , f 2  and f 3  corresponding to values of Vtf 1  equal to 2.0, 1.8 and 2.2, respectively. In correspondence with a variation of ±10% of the threshold voltage Vtf 1  of the TFT driver transistor TF 1 , there occurs then a relative variation equal to 0.2% in the current IDS flowing through the OLED diode OL. 
     Reminding that the specifications in terms of the luminosity of an OLED diode is requested depend on the type of application for which the diode is intended, the resulted luminosity uniformity has been obtained thanks to the driving circuit  10  for applications to the mobile telephony, where the luminosity varies in the range [140÷160] cd/m 2 . 
     These specifications derive from that for applications such as cell phones, the display is placed at a few tens of centimeters from the eyes, and thus a range of luminosity centered on 150 cd/m 2  is more than acceptable. 
     To obtain a luminosity of 150 cd/m 2  it is necessary to supply the OLED diode with a current density (J) of 4 mA/cm 2 . Considering that the area occupied by the OLED is of 19677.38 μm 2  (mean value of the range of areas previously indicated), it is deduced that the luminosity of 150 cd/m 2  is obtained for a current equal to 0.78 μA. 
     Supposing the above, the luminosity characteristic as a function of the current takes then the form shown in  FIG. 15 , indicated as LvC. 
     For a current flowing in the OLED diode OL of the value of 0.78 μA, at a variation of the threshold voltage of T 1  of ±10%, in the case of the driving circuit  10  according to the disclosure, there is a relative variation of the current of about 4.5%. 
     The luminosity values in relation to the above exposed variations are indicated in the following table: 
     
       
         
           
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                   
                 Current (μA) 
                 Luminosity (cd/m 2 ) 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                   
                 0.78 
                 150 
               
               
                   
                 0.8151 (+4.5%) 
                 156.75 
               
               
                   
                 0.7449 (−4.5%) 
                 143.25 
               
               
                   
               
            
           
         
       
     
     Considering that the uniformity of luminosity is the value of how the luminosity differs on a display, a level of non uniformity equal to 5-8% is acceptable for video applications. It is however of same importance that this uniformity does not change too much in width on small areas of the display, since the human eye is sensitive to these differences. 
     For a correct measurement of the luminosity uniformity of an AM-OLED display driven by the driving circuit  10  according to the disclosure, a portion  20  of the same constituted by nine OLED diodes OL, as shown in  FIG. 16 , has then been considered. 
     For each diode, it is also assumed that the minimum and maximum variation of luminosity is contained within the values defined in the above indicated Table 1. 
     The minimum (or negative) and maximum (or positive) luminosity variations are then given by the following relations: 
     
       
         
           
             
               Non 
               ⁢ 
               
                   
               
               ⁢ 
               
                 Uniformita 
                 ′ 
               
               ⁢ 
               
                   
               
               ⁢ 
               Positiva 
             
             = 
             
               100 
               ⁢ 
               
                   
               
               ⁢ 
               % 
               ⁢ 
               
                   
               
               ⁢ 
               
                 
                   
                     L 
                     Max 
                   
                   - 
                   
                     L 
                     Media 
                   
                 
                 
                   L 
                   Media 
                 
               
             
           
         
       
       
         
           
             
               Non 
               ⁢ 
               
                   
               
               ⁢ 
               
                 Uniformita 
                 ′ 
               
               ⁢ 
               
                   
               
               ⁢ 
               Negativa 
             
             = 
             
               100 
               ⁢ 
               
                   
               
               ⁢ 
               % 
               ⁢ 
               
                   
               
               ⁢ 
               
                 
                   
                     L 
                     Min 
                   
                   - 
                   
                     L 
                     Media 
                   
                 
                 
                   L 
                   Media 
                 
               
             
           
         
       
     
     Positive/Negative Non Uniformity 
     Mean 
     From these relations, it is understood that, by using the driving circuit  10  according to the disclosure, these values of positive and negative non uniformity (in absolute value) are equal to 4.5%, thus falling within the limits allowed for the application considered. 
     In the case of applications where OLED diodes are used with greater areas (for example, in the displays for television sets), the increase in driving current is to be taken into account, the increase implying a reduction of the current variation as a function of the threshold voltage variation with consequent decrease of the positive and negative non uniformity. 
     It is also suitable to remark that the increased sizes of the driving circuit  10  according to the disclosure with respect to the known circuits are negligible in most applications. In particular, the areas occupied by the single components of the driving circuit  10  are reported in the following table: 
     
       
         
           
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                   
                 Component 
                 Area (μm 2 ) 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                   
                 TFT 1 
                 96 
               
               
                   
                 TFT 2 
                 96 
               
               
                   
                 TFT 3 
                 72 
               
               
                   
                 TFT 4 
                 72 
               
               
                   
                 TFT 5 
                 72 
               
               
                   
                 Cb 
                 3900 
               
               
                   
                 Cs 
                 3900 
               
               
                   
               
            
           
         
       
     
     The total area of the driving circuit  10  is thus 8208 μm 2 . It is however known that the OLED diodes, used for example in the field of the mobile telephony, have an area occupation that varies in the range [16129÷23225.76]μm 2 , therefrom it is deduced that the area occupied by the OLED diode OL is at least 1.9 times that of the driving circuit  10 . 
     Finally, the power dissipated by the driving circuit  10  according to the disclosure has been evaluated for an AM-OLED display, obtained as sum of the power supplied by the voltage generators which take care of the opening and of the closing of the selection transistors during the three periods or steps for the generation of the IDS current, by the generator of the input voltage signal Vdata, and of the power supplied by the supply voltage reference VDD. Moreover, both the static power dissipated by the driving circuit  10 , evaluated when the signals constituting the Timing diagram take determined configurations, and the dynamic power rising during the switches of these signals have been determined. 
     In the following tables, the cumulative power values for the above defined three periods are reported: 
     
       
         
           
               
             
               
                 TABLE 3 
               
             
            
               
                   
               
               
                 static power 
               
            
           
           
               
               
               
               
            
               
                   
                 STATIC 
                   
                 STATIC 
               
               
                   
                 POW. (Watt) 
                 STATIC POW. (Watt) 
                 POW. (Watt) 
               
               
                   
                 first initialization 
                 Second compensation 
                 third data-input 
               
               
                 SIGNAL 
                 period P1 
                 period P2 
                 period P3 
               
               
                   
               
               
                 V sel _1 
                 0 
                 0 
                 0 
               
               
                 V sel _2 
                  0.11e −6   
                 0 
                 0 
               
               
                 V sel _3 
                 0 
                 0 
                 0 
               
               
                 V data   
                 0 
                 0 
                 0 
               
               
                 V DD   
                   15e −6   
                 0.06e −6   
                 5e −6   
               
               
                 Total 
                 15.11e −6   
                 0.06e −6   
                 5e −6   
               
               
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                 TABLE 4 
               
             
            
               
                   
               
               
                 dynamic power 
               
            
           
           
               
               
               
               
            
               
                   
                 DYNAMIC POW. 
                 DYNAMIC POW. 
                 DYNAMIC 
               
               
                   
                 (Watt) first 
                 (Watt) second 
                 POW. 
               
               
                   
                 initialization 
                 compensation 
                 (Watt) third data- 
               
               
                 SIGNAL 
                 period P1 
                 period P2 
                 input period P3 
               
               
                   
               
               
                 V sel _1 
                 0 
                 0 
                   49e −6   
               
               
                 V sel2   
                  21.5e −6   
                   37e −6   
                 69.5e −6   
               
               
                 V sel3   
                 0 
                 0 
                 0 
               
               
                 V data   
                 0 
                 0 
                 1.72e −6   
               
               
                 V DD   
                   330e −6   
                 38.5e −6   
                 35.5e −6   
               
               
                 Total 
                 351.5e −6   
                 75.5e −6   
                 155.72e −6   
               
               
                   
               
            
           
         
       
     
     From these tables it is thus derived that, for the driving circuit  10 :
         TOTAL STATIC POWER=20.17e −6  W   TOTAL DYNAMIC POWER=582.72e −6 W
 
extremely acceptable values in most applications, in particular in the case of application to the mobile telephony.
       

     In conclusion, the driving circuit according to the disclosed embodiments allows to obtain a self-regulated compensation of the threshold voltage variations of the TFT driver transistors contained therein. 
     The driving circuit  10  proposed thus provides for a correct driving of a matrix of OLED diodes, ensuring a lightning uniformity of a display of the AM-OLED type, with limited increase of the occupation area of the circuit itself and reasonable dissipated power values. 
     The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
     These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.