Patent Publication Number: US-6222413-B1

Title: Receiver assisted net driver circuit

Description:
FIELD OF THE INVENTION 
     The present invention relates to integrated circuit chips and to integrated circuit devices, and more particularly, relates to a receiver assisted net driver circuit. 
     DESCRIPTION OF THE RELATED ART 
     As used in the following description and claims, the term net means a connection or wire between a number of integrated circuit chips or between transistors in a circuit. 
     Chip-to-chip nets that are unterminated, multi-drop and long as compared to the transition time of the driving chip are difficult to switch fast. When the driver transition rate and the driver output impedance are selected to switch the net quickly, a lot of energy is left in the net after all of the receiving nodes have crossed the switching threshold. This remnant energy must dissipate in the driver; otherwise the remnant energy will disturb subsequent data transitions. 
     A need exists for an improved net driver circuit. It is desirable to provide such net drive circuit that enables faster transitions. It is desirable to provide such net drive circuit that effectively dissipates switching energy after all of the receiving nodes have switched. It is desirable to provide such net drive circuit that minimizes noise for the transitions. 
     SUMMARY OF THE INVENTION 
     A principal object of the present invention is to provide an improved net driver circuit. Other objects are to provide such net driver circuit substantially without negative effects and that overcomes many of the disadvantages of prior art arrangements. 
     In brief, an improved net driver circuit is provided. The net driver circuit includes a control circuit. A bidirectional input/output (I/O) circuit is coupled to the control circuit. The bidirectional input/output (I/O) circuit includes a receiver and a driver. The control circuit monitors the net and responsive to a new changed state of the net being identified, the control circuit enables the driver to drive the net to the new changed state. 
     In accordance with features of the invention, the receiver senses the current state of the net and the control circuit remembers the previous state of the net. When the net state is the same as the previous state, the control circuit causes the driver to be in a high impedance state. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein: 
     FIG. 1 is a schematic and block diagram representation of a receiver assisted net driver circuit of the preferred embodiment; 
     FIG. 2 is a schematic and block diagram representation of a control circuit of the preferred embodiment of the receiver assisted net driver circuit of FIG. 1; 
     FIG. 3 is a schematic and block diagram representation of a transition assist logic circuit of the preferred embodiment of the control circuit of FIG. 2; 
     FIG. 4 is a schematic and block diagram representation of a sense compare circuit of the preferred embodiment of the control circuit of FIG. 2; 
     FIG. 5 is a schematic and block diagram representation of an alternative control circuit of the preferred embodiment of the receiver assisted net driver circuit of FIG. 1; 
     FIG. 6 is a schematic and block diagram representation of a sense compare circuit of the preferred embodiment of the control circuit of FIG. 5; 
     FIG. 7 is a truth table for a logic block of the preferred embodiment included in the transition assist logic circuit of FIG.  3  and the sense compare circuits of FIGS. 4 and 5; 
     FIGS. 8A,  8 B, and  8 C are truth tables for a drive mode, a transition assist mode, and a receive mode of the transition assist logic circuit of FIG. 3; 
     FIG. 9A is a schematic diagram for a bi-directional input/output (I/O) circuit of the receiver assisted net driver circuit of FIG. 1; 
     FIGS. 9B and 9C are respective truth tables for a driver portion and a receiver portion of the bi-directional input/output (I/O) circuit of FIG. 9A; 
     FIG. 10 is a timing diagram for the sense compare circuit of the preferred embodiment of FIG. 4; and 
     FIG. 11 is a timing diagram for the sense compare circuit of the preferred embodiment of FIG.  6 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Having reference now to the drawings, in FIG. 1, there is shown a receiver assisted net driver circuit of the preferred embodiment generally designated by the reference character  100 . Receiver assisted net driver circuit  100  includes a control circuit  102  interconnected with a bi-directional input/output I/O circuit  104 . Control circuit  102  receives control signals from on-chip logic. FIG. 9 illustrates the bi-directional input/output I/O circuit  104 . As shown, bi-directional input/output I/O circuit  104  includes a combination of a driver  902  and a receiver  904 . Control circuit  102  is connected to the input of the driver  902  of the bi-directional input/output I/O circuit  104 , so that the driver  902  assists to speed up incoming transitions. Control circuit  102  receives the NREC_OUT signal from receiver  904 . DATA, ENABLE, TA_IN signals and an optional net sample clock are applied to the control circuit  102 . The TA_IN signal is used to enable a transition assist function of the preferred embodiment of the control circuit  102 . BIDI_DATA, BIDI_ENABLE, and TA_OUT signals provided by the control circuit  102  are applied to the bi-directional input/output I/O circuit  104 . 
     Control circuit  102  illustrated in FIGS. 2,  3  and  4  is clocked and uses a latch to store the state of the net for the previous state. An alternative control circuit  102 A illustrated in FIGS. 5 and 6, includes a time delay RC to store the state of the net for the previous state. 
     In accordance with features of the invention, a receiver portion of the bi-directional input/output I/O circuit  104 , control circuit  102  and the driver portion of the bi-directional input/output I/O circuit  104  are used to assist the switching transition of the net at each receiving chip. Inactive drivers at the receiving chips are used to help the net switch faster, and to help dissipate the switching energy after all of the receiving nodes have switched. Normally a chip sets the driver portion of its I/O bi-directional circuit to the high impedance state when it is receiving data from the net, and sets the driver portion to either drive low or drive high when it is sending data on the net. 
     In accordance with features of the invention, a receiver of the bi-directional input/output I/O circuit  104  senses the current state of the net and the control circuit  102  or  102 A remembers the previous state of the net. When the chip  100  is receiving, and this function is enabled by the control signal TA_IN, the control circuit  102  or  102 A monitors the net. When it senses that the net has a new state that is different from the old state, control circuit  102  or  102 A cause the driver  902  to drive the net to the new state of the net. When the net state is the same as the old state, the control circuit  102  or  102 A causes the driver  902  to be in the high impedance state. 
     Previous solutions have not controlled the assisting circuit to force it to be at a high impedance state before and during the net transition. The assisting circuit was always active and it was necessary to overdrive the current state of the assisting circuit to initiate the net transition while the assisting circuit held the net at the old state. In accordance with the preferred embodiment, control circuit  102  or  102 A does not hold the net at the old state. Once the transition is completed the assisting circuit releases the net, and does not need to be overdriven like the other implementations. 
     Referring to FIGS. 2,  3 , and  4  control circuit  102  includes a transition assist logic  200  and a sense compare circuit  202  that uses a clock and a latch to store the state of the net as the previous state. Transition assist logic  200  shown in more detail in FIG. 3 includes a pair of logic blocks  300  formed by a pair of two input AND gates  302  and  304  connected at the output to a two input NOR gate  306 . Transition assist logic  200  includes a plurality of inverters  308 ,  310 ,  312 ,  314 ,  316 , and  318 . ENABLE and DATA inputs are applied to AND gate  302  of a first logic block  300 . Inverter  308  receives the ENABLE input and provides an ENABLE_NOT output. Inverter  310  receives the NEC_OUT input and provides an NEC_OUT_NOT output. ENABLE_NOT and NEC_OUT_NOT inputs are applied to AND gate  304  of the first logic block  300 . As shown in a truth table for the logic block  300  in FIG. 7, the output (BIDI_DATA_NOT) of NOR gate  306  of the first logic block  300  is high unless either both ENABLE and DATA inputs to AND gate  302  are one or ENABLE_NOT and NEC_OUT_NOT inputs to AND gate  304  are one. The BIDI_DATA_NOT output of NOR gate  306  is inverted by inverter  312  providing the BIDI_DATA output of the transition assist logic  200 . 
     In the transition assist logic  200 , the ENABLE signal is applied to both inputs of AND gate  302  of a second logic block  300 . The transition signal from the sense compare circuit  102  is applied to a first input of AND gate  304  of the second logic block  300 . The TA_IN control signal is inverted by inverter  314 . The TA_IN_NOT output of inverter  314  is applied to the second input of AND gate  304  of the second logic block  300 . The TA_IN_NOT output of inverter  314  is applied to inverter  316  providing output TA_OUT. The output (BIDI_ENABLE_NOT) of NOR gate  306  of the second logic block  300  is inverted by inverter  318  providing the BIDI_ENABLE output of the transition assist logic  200 . 
     The transition assist logic circuit  200  has modes of operation including the drive mode, TA mode and receive mode. In the TA mode and receive mode, the BIDI_DATA output of the transition assist logic  200  must settle before the BIDI_ENABLE output of the transition assist logic  200  becomes active. In the drive mode, BIDI_DATA and BIDI_ENABLE outputs of the transition assist logic  200  must have the same delay. FIGS. 8A,  8 B and  8 C illustrate respective transition assist logic truth tables for the drive mode, transition assist (TA) mode and receive mode. 
     In FIG. 4, the sense compare circuit  202  that uses a sample clock and a latch  402  to store the state of the net as the previous state is shown. The NREC_OUT_NOT input is applied to an inverter  410  and an output NET_PREVIOUS_CYCLE signal of latch  402  is applied to a second inverter  412 . The NREC_OUT_NOT input, the NET_PREVIOUS_CYCLE_NOT signal of inverter  412 , the NET_PREVIOUS_CYCLE signal of latch  402 , and the inverted NREC_OUT output of inverter  410  are applied to respective AND gate inputs of a combination logic block  300  of the sense compare circuit  202 . An inverted transition signal TRANSITION_NOT is provided at the output of NOR gate  306  of the logic block  300 . The inverted transition signal TRANSITION_NOT is inverted by an inverter  414  providing the transition signal TRANSITION output of the sense compare circuit  202 . The NET_SAMPLE_CLOCK and TA_signal are applied to a NOR gate  418 . The output of NOR gate  418  provides an inverted latch clock input CP to latch  402 . The inverted latch clock output of NOR gate  418  is inverted by an inverter  420  and provides a latch clock input CN to latch  402 . The latch  402  samples on the rising edge of the inverted latch clock input CP. The latch clock input CN and the inverted latch clock input CP need to be complements. 
     Referring to FIGS. 5 and 6, control circuit  102 A includes the transition assist logic  200  and a sense compare circuit  502  that uses an RC filter to delay the state of the net for the previous state. FIG. 6 illustrates an RC delaying control circuit  102 A including a RC filter  614  formed by a resistor  616  and capacitor  618  coupled between the NREC_OUT_NOT input and ground. The same reference numbers used in sense compare circuit  202  are used for similar or identical components of the sense compare circuit  502 . Sense compare circuit  502  similarly includes a pair of inverters  410  providing outputs NREC_OUT_NOT_DELAYED_NOT and NREC_OUT applied to respective AND gates  302  and  304  of logic block  300 . The NREC_OUT_NOT_DELAYED output of RC filter  614  and the NREC_OUT_NOT input are applied to respective AND gates  302  and  304  of logic block  300 . The TRANSITION_NOT output of NOR gate  306  is inverted by inverter  414  to provide the TRANSITION output of sense compare circuit  502 . 
     Referring now to FIG.  7  and the following Truth Table, two inputs for AND gates  302  and  304  and NOR gate  306  of logic block  300  are shown. 
     
       
         
           
               
               
               
               
               
               
               
               
               
             
               
                   
               
               
                 a0 
                 a1 
                 A 
                 B0 
                 b1 
                 B 
                 A 
                 B 
                 C 
               
               
                   
               
             
            
               
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
               
               
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
               
               
                 1 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
               
               
                 1 
                 1 
                 1 
                 0 
                 0 
                 0 
                 1 
                 0 
                 o 
               
               
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 1 
               
               
                 0 
                 0 
                 0 
                 0 
                 1 
                 0 
                 0 
                 0 
                 1 
               
               
                 0 
                 0 
                 0 
                 1 
                 0 
                 0 
                 0 
                 0 
                 1 
               
               
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 0 
                 1 
                 0 
               
               
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 1 
                 0 
               
               
                   
               
            
           
         
       
     
     Referring to FIGS. 8A,  8 B,  8 C, and  9 , truth tables for transition assist logic  200  and the bi-directional I/O circuit  104  are shown. In the drive mode shown in FIG. 8A, a driver  902  in the bi-directional I/O circuit  104  is controlling the state of the net. The ENABLE=1 sets the drive mode of the transition assist logic  200 . The following truth table illustrates the drive mode: 
     
       
         
           
               
               
               
               
               
               
             
               
                   
               
             
            
               
                 DA- 
                 EN- 
                 NREC- 
                   
                   
                   
               
               
                 TA 
                 ABLE 
                 OUT 
                 TA_IN 
                 NREC_OUT_NOT 
                 TRANSITION 
               
               
                   
               
               
                 0 
                 1 
                 X 
                 X 
                 NREC OUT NOT 
                 X 
               
               
                 1 
                 1 
                 X 
                 X 
                 NREC OUT NOT 
                 X 
               
               
                   
               
            
           
           
               
               
               
            
               
                   
                 BIDI_DATA 
                 BIDI_ENABLE 
               
               
                   
                   
               
               
                   
                 0 
                 1 
               
               
                   
                 1 
                 1 
               
               
                   
                   
               
            
           
         
       
     
     The following truth table and FIG. 8B illustrate the receive mode of the transition assist logic  200 . The driver  902  is turned off and the transition assist is disabled. The ENABLE=0 and TA_IN=1 sets the receive mode. 
     
       
         
           
               
               
               
               
               
               
             
               
                   
               
               
                 DA- 
                 ENA- 
                   
                   
                   
                 TRANSI- 
               
               
                 TA 
                 BLE 
                 NREC_OUT 
                 TA_IN 
                 NREC_OUT_NOT 
                 TION 
               
               
                   
               
             
            
               
                 X 
                 0 
                 0 
                 1 
                 1 
                 X 
               
               
                 X 
                 0 
                 1 
                 1 
                 0 
                 X 
               
               
                   
               
            
           
         
       
     
     Data is unimportant and BIDI-DATA is unimportant because BIDI_ENABLE=0. 
     
       
         
           
               
               
               
             
               
                   
                   
               
               
                   
                 BIDI_DATA 
                 BIDI_ENABLE 
               
               
                   
                   
               
             
            
               
                   
                 (1)NREC_OUT NOT 
                 0 
               
               
                   
                 (0)NREC_OUT NOT 
                 0 
               
               
                   
                   
               
            
           
         
       
     
     FIG.  8 C and the following truth table illustrate the TA mode of the transition assist logic  200 . The driver  902  is controlled by the control circuit  102 ,  102 A. An output (NREC_OUT) of a receiver  904  is used by the control circuit  102 ,  102 A to determine how to control the driver. NREC_OUT controls BIDI_DATA; transition controls BIDI_ENABLE. 
     
       
         
           
               
               
               
               
               
               
             
               
                   
               
             
            
               
                 DA- 
                 ENA- 
                   
                   
                   
                 TRANSI- 
               
               
                 TA 
                 BLE 
                 NREC_OUT 
                 TA_IN 
                 NREC_OUT_NOT 
                 TION 
               
               
                   
               
               
                 X 
                 0 
                 0 
                 0 
                 1 
                 ˜ 
               
               
                 X 
                 0 
                 1 
                 0 
                 0 
                 ˜ 
               
               
                 X 
                 0 
                 ˜ 
                 0 
                 ˜ 
                 0 
               
               
                 X 
                 0 
                 ˜ 
                 0 
                 ˜ 
                 1 
               
               
                   
               
            
           
           
               
               
               
            
               
                   
                 BIDI_ENDATA 
                 BIDI_ENABLE 
               
               
                   
                   
               
               
                   
                 (1)NREC_OUT NOT 
                 ˜ 
               
               
                   
                 (0)NREC_OUT NOT 
                 ˜ 
               
               
                   
                 ˜ 
                 0 
               
               
                   
                 ˜ 
                 1 
               
               
                   
                   
               
            
           
         
       
     
     ENABLE=0 and TA_IN=0 sets the TA mode. With BIDI_ENABLE=0, no transition on C 4  detected so the driver is tri-stated and does not influence the voltage on the C 4 . When BIDI_ENABLE=1, with a voltage transition on the net detected so the driver is enabled, the data that the driver drives onto the changing net is set by the value of NREC_OUT. 
     Referring to FIGS. 9A,  9 B, and  9 C, truth tables are shown for the bi-directional I/O circuit  104  including the driver  902  and receiver  904  combination, as follows. As shown in the following truth table and in FIG. 9A, the driver  902  receives the BIDI_ENABLE and BIDI_DATA inputs and provides an output C 4  applied to the receiver  904 . 
     
       
         
           
               
               
               
               
             
               
                   
                   
               
               
                   
                 BIDI_ENABLE 
                 BIDI_DATA 
                 C4 
               
               
                   
                   
               
             
            
               
                   
                 O 
                 X 
                 HI Z 
               
               
                   
                 1 
                 0 
                 0 
               
               
                   
                 1 
                 1 
                 1 
               
               
                   
                   
               
            
           
         
       
     
     With the high impedance output, C 4 =HI Z, the enable input turns off the driver  902  and the value of data is not important. Driver  902  is tri-stated and does not control the voltage on the net other drivers on other chips attached to this net may control the voltage or the net may be completely uncontrolled. For the zero and one outputs C 4 =0,1, the enable input is high. During these states, the driver  902  controls the voltage on the net. 
     
       
         
           
               
               
               
             
               
                   
                   
               
               
                   
                 C4 
                 NREC_OUT 
               
               
                   
                   
               
             
            
               
                   
                 O 
                 1 
               
               
                   
                 1 
                 0 
               
               
                   
                   
               
            
           
         
       
     
     Even when the net is not controlled by any driver it has a voltage value. The output receiver  904  is 1 if the C 4  voltage is less than the receiver threshold voltage. The receiver output is 0 if the C 4  voltage is greater than threshold voltage. 
     While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawings, these details are not intended to limit the scope of the invention as claimed in the appended claims.