Patent Publication Number: US-2002000612-A1

Title: Power-mos transistor

Description:
BACKGROUND OF THE INVENTION  
       [0001] Solid state devices used to provide power for motors and RF devices are often implemented using field effect transistors. These power transistors comprise relatively large gate bodies that are interdigitated between source and drain regions. The power transistor structure must provide for high current switching capability. A power transistor structure also requires large voltage drops between the drain and the source and between the drain and the gate when the transistor is off and the gate is at source potential.  
       [0002] Present systems have provided power transistors with adequate current carrying capability at adequate voltage ranges. Isolation of the power transistor from neighboring electronic devices is traditionally provided for by the addition of a moat module that includes the growth of a field oxide and channel stop implants to prevent the formation of surface parasitic MOS devices. The moat module involves considerable processing time and procedures to complete.  
       [0003] Present power transistor devices also utilize three layers of metallization with the outermost layer having a low resistivity to minimize the metal bus resistance. A first layer of metallization is provided to form conductive interconnects to the source and drain regions of the device. A second layer of metallization is provided to form both a source bus and a drain bus and to contact the source and drain interconnects. However, the second layer of metallization alone is inadequate as a drain bus or a source bus to provide the high current switching capability necessary for power transistor devices. An outermost level of conductive material, copper for example, is therefore provided to increase the effective thickness of drain and source bus layers, thereby decreasing the bus resistance and minimizing IR drops along the bus.  
       [0004] The processing of the isolation moat module combined with the necessity for three layers of metallization increase processing time, difficulty and expense associated with the production of power transistor devices.  
       SUMMARY OF THE INVENTION  
       [0005] Accordingly, a need has arisen for a field effect device that can provide the traditionally necessary high current-carrying capability with relatively high breakdown voltages, but which does not require the additional processing time and expense needed to create field oxide structures in most isolation schemes or require the introduction of an intermediate level of metallization.  
       [0006] In accordance with the teachings of the present invention, a semiconductor device is provided that comprises a substrate having a first conductivity type. An epitaxial layer of a second conductivity type is formed outwardly from the substrate. An isolation region is formed in the epitaxial layer and the substrate. A guard ring is formed in portions of the substrate and portions of the epitaxial layer. An active region of the second conductivity type is defined in the epitaxial layer by the isolation region and the guard ring. A gate body is insulatively disposed outwardly from the active region. An insulative structure having a plurality of contact openings is disposed outwardly from the gate body and the epitaxial layer. A conductive interconnect layer is disposed outwardly from the insulative structure and fills the contact openings. The conductive interconnect layer is etched to form source and drain interconnects. A planarization layer is formed outwardly from the conductive interconnect layer and has an planarization contact opening. A passivation layer is formed outwardly from the planarization layer and has a passivation contact opening. A conductive layer is formed outwardly from the passivation layer. The conductive layer contacts the conductive interconnect layer through the passivation contact opening and planarization contact opening. The conductive layer is electrically isolated from the conductive interconnect layer by the planarization layer and the passivation layer.  
       [0007] The disclosed invention offers many technical advantages. For example, the invention provides an electronic device that is isolated from neighboring devices without the need for complex field oxide isolation structures and channel stop implants, saving time and processing steps. In addition, the invention optimizes the process of fabricating an electronic device by eliminating the use of an intermediate metal interconnect layer. In particular, the disclosed invention allows the construction of high voltage power transistors using copper without the need for three separate layers of metallization within a single device. Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.  
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0008] A more complete understanding of the invention may be acquired by referring to the accompanying figures in which like reference numbers indicate like features and wherein:  
     [0009] The FIGURE is a schematic cross-sectional diagram of one embodiment of a power transistor according to the teachings of the present invention.  
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
     [0010] The preferred embodiments of the present invention and its advantages are best understood by referring to the FIGURE of the drawings, like numerals being used for like and corresponding parts of the drawings.  
     [0011] The FIGURE illustrates an embodiment of the structure of a power field effect transistor according to the teachings of the present invention. Semiconductor device  10  includes a P− substrate  12 . In one embodiment, substrate  12  is a wafer formed from a single crystalline silicon material. It will be understood that substrate  12  may comprise other materials and/or layers within the scope of the present invention. For example, substrate  12  may comprise an epitaxial material, a recrystallized semiconductor material, a polycrystalline semiconductor material, or other suitable materials. In one embodiment, substrate  12  is a P-type substrate comprising, for example, boron.  
     [0012] The outer surface of substrate  12  is provided with N+ diffused regions (not shown), using implanted dopants of antimony, and P+ diffused regions (not shown), using implanted dopants of Boron, prior to the growth of an N-epitaxial layer  14  of approximately 15 microns in thickness. N− epitaxial layer  14  is comprised of, for example, phosphorus. After the growth of N− epitaxial layer  14 , the buried N+ diffused regions migrate upwards into epitaxial layer  14 , approximately 8 microns, for example. The N+ and P+ diffused regions are then augmented by diffusions from the outer surface of epitaxial layer  14 , to provide for a P+ isolation region  16 , comprising boron, and an N+ guard ring  18 , comprising antimony.  
     [0013] Isolation region  16  and guard ring  18  isolate and define an active region  20  of about 6 microns in thickness in which the power transistor of the present invention is formed.  
     [0014] A gate insulator layer  22  is grown outwardly from surface of substrate  12 . Gate insulator layer  22  may be on the order of 525 angstroms in thickness. Gate insulator layer  22  comprises, for example, silicon dioxide. It will be understood that gate insulator layer  22  may comprise another type of material capable of insulating semiconductor elements.  
     [0015] Gate bodies  24  and  26  are disposed outwardly from gate insulator layer  22  over active region  20 . Gate bodies  24  and  26  may be, for example, on the order of 5000 Angstroms in thickness. Gate bodies  24  and  26  may be disposed with a distance of 3.5 microns between them, for example. Gate bodies  24  and  26  may be approximately 2.5 microns in width. Gate bodies  24  and  26  comprise polycrystalline silicon, or other suitable material including single crystalline silicon or gallium arsenide.  
     [0016] Following the formation of gate bodies  24  and  26 , a P− well  21  is formed by implanting boron dopants between gate bodies  24  and  26  and then diffusing the dopants until P-well  21  reaches a width of approximately 7.5 microns. P-well  21  does not extend beyond the far outside walls of gate bodies  24  and  26 .  
     [0017] Gate sidewalls  27  may then be formed, for example, by depositing one or more conformal layers of TEOS (tetra-ethyl-ortho-silicate) oxide over the transistor utilizing a chemical vapor deposition (CVD) process. The conformal layer or layers of TEOS oxide may then be anisotropically etched, leaving gate sidewalls  27  formed at a width of 3,000 Angstroms, for example.  
     [0018] Within active region  20 , highly-diffusible dopants may be implanted and diffused into a conductive source region  28 , within P− well  21 , and a conductive drain region  30 , outside of P− well  21 . Conductive source region  28  and conductive drain region  30  may be spaced opposite one another and apart from gate body  24  to define a channel region in active region  20 .  
     [0019] Plate shielding (not explicitly shown) is used, instead of the channel stop implants and field isolation structures normally used to isolate MOS devices, to prevent the formation of parasitic MOS devices. Plate shielding results from gate bodies  24  and  26  completely surrounding all P diffusions present in active region  20 . For example, gate bodies  24  and  26  completely surround P− well  21  and source region  28 .  
     [0020] Other parasitic devices are prevented by isolation region  16  and guard ring  18 . The power transistor formed in active region  20  is isolated from other devices formed on substrate  12  and epitaxial layer  14  by the isolation effects of isolation region  16  and the junction between epitaxial layer  14  and substrate  12 . Guard ring  18  prevents the injection of holes into substrate  12  during particular loading and transient conditions for the power transistor. Guard ring  18  generally prevents the formation of vertical PNP current flow from source region  28  to substrate  12 , thereby preventing potential latch-up with neighboring devices.  
     [0021] An interlevel dielectric layer  32  is deposited as an insulative structure outwardly from gate insulator layer  22  and gate bodies  24  and  26 . Interlevel dielectric layer  32  is approximately 1 micron in thickness. In one embodiment interlevel dielectric layer  32  comprises a silane-based borophosphosilicate glass (BPSG). BPSG films are deposited at low temperatures such as, for example, 400-450° C. and are then immediately densified at approximately 800° C. for one hour. The purpose of this step is to completely stabilize the BPSG films, which would otherwise be prone to blistering during subsequent processing.  
     [0022] Contact openings  34  and  36  may be formed through interlevel dielectric layer  32  and gate insulator layer  22  over source region  28  and drain region  30 , respectively. Contact openings  34  and  36  may be formed using a dry etch process.  
     [0023] A reflow process of contact openings  34  and  36  is conducted by exposing device  10  to a high temperature step after the contact openings have been formed. This causes the interlevel dielectric layer  32  to flow slightly, producing rounded corners and sloped sidewalls in openings  34  and  36 . For example, BPSG used to comprise interlevel dielectric layer  32  flows at low temperatures (800-850° C. at atmospheric pressures), resulting in rounded corners. Thus, contact openings  34  and  36  are formed from outer surface of inner level dielectric layer  32  down to outer surface of substrate  12  and defined by the rounded corners of interlevel dielectric layer  32 .  
     [0024] A conductive interconnect layer  38  is deposited outwardly from interlevel dielectric layer  32 . Conductive interconnect layer  38  is approximately 0.75 microns in thickness. Conductive interconnect layer  38  comprises, for example, aluminum or other suitable material. Conductive interconnect layer  38  may also include additional barrier layers or adhesion layers. Conductive interconnect layer  38  is deposited in such a way that it fills contact openings  34  and  36 .  
     [0025] An etch process, such as a high energy plasma etch, is preferably used to etch conductive interconnect layer  38  such that source interconnect  40  is formed, contacting source region  28  through contact opening  34 , and such that drain interconnect  42  is formed, contacting drain regions  30  through contact opening  36 .  
     [0026] A planarization layer  44  is disposed outwardly from conductive interconnect layer  38  forming a planar surface. Planarization layer  44  may be on the order of 1 micron in thickness. Planarization layer  44  may comprise, for example, a deposited oxide. Alternatively, planarization layer  20  may be formed through the process of spin on glass (SOG) planarization. The SOG process combines spin-on glass with a deposited oxide which is deposited through a plasma process. Planarization layer  44  is operable to insulate source interconnect  40  from drain interconnect  42  and all of interconnect layer  38  from subsequent layers of metallization.  
     [0027] A passivation layer  46  is then deposited over the entire top surface of device  10 . Passivation layer  46  may be on the order of 1 micron in thickness. Passivation layer  46  prevents mechanical and chemical damage during assembly and packaging. Passivation layer  46  comprises, for example, plasma deposited silicon nitride (Si 3 N 4 ). Silicon nitride is desirable as a material for the formation of passivation layer  46  because it provides an impermeable barrier to moisture and mobile impurities and also forms a tough coat that protects device  10  against scratching. Both passivation layer  46  and planarization layer  44  may be slightly thinner over conductive interconnect layer  38 .  
     [0028] The combination of planarization layer  44  and passivation layer  46  provides a relatively defect free means of isolating conductive interconnect layer  38  from subsequent conductive layers such as a drain bus layer  50  disposed over passivation layer  46 . For example, the material used in planarization layer  44  and passivation layer  46  can combine to form an insulative structure with excellent thermal stability, low stress, good crack resistance, and high resistance to the penetration of moisture and charged particles. Ideally, these two layers should be thin to allow for adequate heat dissipation. However, counterbalancing this concern is the need to have sufficient insulative thickness to prevent the formation of parasitic capacitances.  
     [0029] A contact opening  48  is formed through passivation layer  46  and planarization layer  44  to drain interconnect  42 . Contact opening  48  is aligned/positioned above contact opening  36  and drain region  30 . Contact opening  48  may be formed using one or more dry etch processes preferably highly selective to passivation layer  46  and planarization layer  44 . Similarly, a contact opening (not shown) is made to source interconnect  40  and bond pad openings (not shown) are made to both source interconnect  40  and drain interconnect  42 .  
     [0030] Drain bus layer  50  is formed outwardly from passivation layer  46 . Drain bus layer  50  comprises, for example, a conductive metal with low resistivity that can be electrolytically grown, such as copper. Drain bus layer  50  may also comprise additional layers such as titanium tungsten (TiW) adhesion layers.  
     [0031] Drain bus layer  50  may be formed by depositing conductive material so that conductive material fills contact opening  48 , contacting drain interconnect  42 , and forms a thin layer (not shown) of conductive material overlying passivation layer  46 . The thin layer of conductive material is then etched as needed. Following etch, the remainder of the conductive material comprising drain bus layer  50  is then electrolytically grown from the etched initial thin layer of material. A similar source bus layer (not shown) may be formed using similar methods and contacting source interconnect  40  through a similar contact opening (not shown).  
     [0032] In one embodiment, drain bus layer  50  eventually comprises copper of approximately 15 microns in thickness. Copper is highly desirable as a drain bus material because of its very low resistivity. Copper is also a preferred material for bus construction used in power transistors, primarily because of its high current-carrying capability and high thermal conductivity, the latter allowing for enhanced heat dissipation. Copper is desirable over aluminum as a drain bus material because, to obtain the same current carrying capacity, the thickness of the aluminum required makes it difficult to be patterned or etched easily. Copper, on the other hand, can be grown through an electrolytic process as described above, eliminating the need to etch through a full thickness of copper.  
     [0033] The combination of planarization layer  44  and passivation layer  46  effectively isolates drain bus layer  50  from source interconnect  40 . It will be understood that drain bus layer  50  may be isolated from source interconnect  40  using only a passivation layer. However, combining planarization layer  44  with passivation layer  46  forms a heterogeneous planarization layer which is relatively defect free, as described above, and retains the properties of isolating drain bus layer  50  from other layers of metallization, and in particular, source interconnect  40 .  
     [0034] Although the device of the present invention has been described with reference to the formation of a power MOS transistor device, it should be understood that the use of the isolation technique described herein is equally applicable to the formation of other semiconductor devices. In addition, the combination of a copper interconnect or bus with dielectric isolation can be used to eliminate the necessity for an intermediate conductive layer as described herein. Furthermore, the structure and techniques described above, and more specifically their isolative properties, may be used to simplify a process utilized in the formation of a semiconductor device to more effectively isolate adjacent structures. In particular, it should be noted that the above structure and techniques provides a means for streamlining manufacturing processes by removing the necessity of adding a field oxide layer to isolate a semiconductor structure from a neighboring structure.  
     [0035] Although the present invention has been described in detail, it should be understood that various changes, alterations, substitutions and modifications to the descriptions contained herein may be made without departing from the scope and spirit of the present invention which is solely defined by the appended claims.