Patent Publication Number: US-9899333-B2

Title: Method for forming crack-stopping structures

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. application Ser. No. 14/220,140, filed 20 Mar. 2014, the disclosure of which is hereby incorporated herein by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a crack-stopping structure and method for forming the same, and more particularly, to a wafer crack-stopping hollow structure and method for forming the same. 
     2. Description of the Prior Art 
     In the field of semiconductor device fabrication, semiconductor devices and interconnections are formed to construct integrated circuits (ICs) on a semiconductor wafer. The fabrication of ICs may be completed through different methods and steps, but generally involves depositing layers of conductive, semiconductor, and insulating materials in precise patterns on a substrate or wafer to form the desired circuit or array patterns. Once formed, the ICs then need to be separated into individual piece-parts, so called dies or chips. The dies, which are isolated or separated from each other by scribe lines, are then separated by sawing along the scribe lines and are individually packaged. 
     When processing the semiconductor wafer to form multi-layer structures, alignment marks are typically disposed in the scribe lines for aligning the wafer with the mask. The alignment marks usually include metal or polysilicon that are formed on and beneath an uppermost surface of the semiconductor wafer. On the other hand, testing circuits are often simultaneously fabricated on the wafer along with the actual devices. The testing circuits include a plurality of metal test pads, which are electrically connected to an external terminal through probe needles, located on the scribe lines. 
     It is found that when the semiconductor wafer is diced, the dicing tool such as a dicing saw usually cuts across the alignment marks and the test pads. A major consideration is that the stress resulted from the sawing process causes serious peeling at where the large metal, that is the alignment marks and test pads occupied. This results in delamination and/or cracking at the interface between the multiple layers and it extends into neighboring dies. Consequently, delamination and/or cracking impact the reliability of the ICs and hence a reduction in IC yield from a given semiconductor wafer. 
     SUMMARY OF THE INVENTION 
     According to an aspect of the present invention, a crack-stopping structure is provided. The crack-stopping structure includes a semiconductor wafer comprising a plurality of dies defined by a plurality of scribe line regions, a plurality of metal patterns formed in the scribe line regions, and a plurality of groups of through silicon holes (hereinafter abbreviated as TSHs) formed in the scribe line regions. The wafer further includes a front side and a back side, and the TSHs respectively include at least a bottom opening formed in the bottom side of the wafer. Furthermore, the groups of TSHs are formed between the metal patterns and the dies. 
     According to another aspect of the present invention, a method for forming a crack-stopping structure is provided. The method for forming the crack-stopping structure includes following steps. A wafer including a plurality of dies defined by a plurality of scribe line regions is provided, a plurality of groups of TSHs are formed in the scribe line regions, and a plurality of through silicon vias (hereinafter abbreviated as TSVs) are formed in the dies. More important, the groups of TSHs are not filled up with metal. 
     According to the crack-stopping structure and the method for forming the same provided by the present invention, the TSHs are formed in the scribe line regions and particularly formed between the metal patterns and the dies. More important, the TSHs are hollow structure having no metal or conductive material formed therein. When the semiconductor wafer is diced, stress resulted from the sawing process causes serious peeling at where the metal patterns occupied. However, the peeling or cracking is obstructed and stopped by the hollow TSHs formed between the metal patterns and the dies, and thus the neighboring dies are protected from cracking. Consequently, delamination and/or cracking, which adversely impact the reliability and yield are prevented. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a flow chart illustrating a method for forming a crack-stopping structure provided by a first preferred embodiment of the present invention. 
         FIG. 2  is a plan view showing an overall configuration of a semiconductor wafer according to a first and a second preferred embodiment of the present invention. 
         FIG. 3  is a partially enlarged view of Circle A of  FIG. 2 . 
         FIG. 4  is a cross-sectional view taken along a Line B-B′ of  FIG. 3 . 
         FIG. 5  is a partially enlarged view of Circle A of  FIG. 2  and a schematic drawing in a step subsequent to  FIG. 3 . 
         FIGS. 6-7  are cross-sectional views taken along a Line B-B′ of  FIG. 5 , wherein  FIG. 7  is a schematic drawing in a step subsequent to  FIG. 6 . 
         FIG. 8  is a top view of a modification to the crack-stopping structure provided by the present invention. 
         FIG. 9  is a flow chart illustrating a method for forming a crack-stopping structure provided by a second preferred embodiment of the present invention. 
         FIG. 10  is a cross-sectional view taken along a Line B-B′ of  FIG. 3  and illustrating the method for forming the crack-stopping structure according to the second preferred embodiment. 
         FIG. 11  is a top view of another modification to the crack-stopping structure provided by the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIGS. 1-7 .  FIG. 1  is a flow chart illustrating a method for forming a crack-stopping structure provided by a first preferred embodiment of the present invention.  FIGS. 2-7  are schematic drawings illustrating a method for forming a crack-stopping structure provided by the first preferred embodiment, wherein  FIG. 2  is a plan view showing an overall configuration of a semiconductor wafer,  FIG. 3  is a partially enlarged view of Circle A of  FIG. 2 ,  FIG. 4  is a cross-sectional view taken along a Line B-B′ of  FIG. 3 ,  FIG. 5  is a partially enlarged view of Circle A of  FIG. 2  and in a step subsequent to  FIG. 3 , and  FIGS. 6-7  are cross-sectional views taken along a Line B-B′ of  FIG. 5 . As shown in  FIG. 1 , the method for forming a crack-stopping structure first provides a Step  10 : 
     STEP  10 : Providing a Semiconductor Wafer Comprising a Plurality of Dies Defined by a Plurality of Scribe Line Regions. 
     In order to clearly describe the structure of the present invention,  FIGS. 2-4  should be referred together. As shown in  FIGS. 2-4 , the semiconductor wafer  1  includes a plurality of dies  3  that are defined and divided by a plurality of scribe line regions  5 . As shown in  FIG. 4 , each die  3  includes a plurality of semiconductor devices  30  formed therein, and a plurality of interconnections  32  are formed on the semiconductor devices  30 . The interconnections  23  can be formed by Al-wiring process or Cu-damascene process, but not limited to this. Additionally, a distribution layer and a contact pad (both not shown) are selectively formed in the dies  3  for constructing an external electrical connection, but not limited to this. More important, a die seal ring  38  is formed simultaneously with forming the interconnections  32  and the distribution layer  34 . Accordingly, a plurality of die seal rings  38  are formed in the semiconductor wafer  1  for encompassing and surrounding the dies  3 , respectively. 
     Please still refer to  FIGS. 3-4 . In the scribe line region  5 , a plurality of metal patterns  50  are formed therein. The metal patterns  50  can include alignment marks, which serve for aligning the wafer  1  with the mask. Or, the metal patterns  50  can include a test pad electrically connected to testing circuits, which are often simultaneously fabricated on the wafer along with the actual semiconductor devices  30  and interconnections  32 . It is well-known to those skilled in the art that the semiconductor devices  30 , the interconnections  32 , the die seal ring  38 , and the metal patterns  50  are fabricated by the front-end-of-line (FEOL) process. 
     Please refer to  FIG. 1 . Next, a Step  12  is performed: 
     STEP  12 : Simultaneously Forming a Plurality of Groups of Through Silicon Holes in the Scribe Line Regions and a Plurality of Through Silicon Holes in the Die. 
     Please refer to  FIGS. 5-6 . It is also noteworthy that the semiconductor wafer  1  includes a front side  1   a  and a back side  1   b . Next, a plurality of groups of TSHs  7  are formed in the scribe line regions  5  and a plurality of TSHs  70  are formed in the dies  3 , simultaneously. According to the preferred embodiment, the TSHs  7  and TSHs  70  are preferably formed from the back side  1   b  of the semiconductor wafer  1  after completion of the semiconductor devices  30  and the interconnections  32 . However, the TSHs  7  and the TSHs  70  can be formed from the front side  1   a  of the semiconductor wafer  1  after completion of the semiconductor devices  30  and the interconnections  32  if required. 
     Please refer to  FIG. 1  again. After forming the TSHs  7  and the TSH  70 , a Step  14  is performed: 
     STEP  14 : Filling the Through Silicon Holes in the Dies with a Metal Material to Form a Plurality of Through Silicon Vias in the Dies, While the Groups of TSHs are not Filled up with the Metal Material 
     Please refer to  FIG. 7 . After forming the TSHs  7  in the scribe line regions  5  and the TSHs  70  in the dies  3 , a barrier layer (not shown) and a buffer layer (not shown) can be formed in the TSHs  7  and the TSHs  70 . The barrier layer may include Ti/TiN or Ta/TaN, but not limited to this. The buffer layer may include tungsten (W), but not limited to this. Next, a protecting layer (not shown) is formed on the TSHs  7  in the scribe line regions  5  and followed by filling up the TSHs  70  in the dies  3  with a metal material to form a plurality of through silicon vias (TSVs)  7   v . Since the TSHs  7  in the scribe line regions  5  are protected by the protecting layer, the TSHs  7  in the scribe line regions  5  are not filled with the metal material and thus remained hollow as shown in  FIG. 8 . Additionally, the protecting layer can be formed on the TSHs  7  before forming the barrier layer and the buffer layer if required. 
     Please refer to  FIGS. 5 and 7  again. The groups of TSHs  7  in the scribe line regions  5  are formed between the metal patterns  50  and the dies  3 , more particularly, between the metal patterns  50  and the die seal rings  38 . A diameter of the TSHs  7  is equal to a diameter of the TSVs  7   v , but the diameter of the TSHs  7  is larger than a width of the die seal rings  38 . Furthermore, it is well-known that the interconnections  32  includes trenches  32   t  and vias  32   v  filled with conductive material, and the diameter of the TSHs  7  is larger than a width of the vias  32   v  of the interconnections  32 . Furthermore, each group of TSHs  7  is formed corresponding to the metal patterns  50 , respectively. Therefore, each group of TSHs  7  is spaced apart from each other as shown in  FIG. 5 . 
     Additionally, each of the TSHs  7  provided by the preferred embodiment includes a bottom opening formed in the bottom side  1   b  of the semiconductor wafer  1  and a top opening formed in the front side  1   a  of the semiconductor wafer  1 . However, since the TSVs  7   v  and the TSHs  7  are formed by back side via-last process according to the preferred embodiment, each of the TSHs  7  can include only a bottom opening formed in the bottom side  1   b  of the semiconductor wafer  1 . 
     Please refer to  FIG. 8 , which is a modification to the crack-stopping structure of the present invention. According to the modification, the groups of TSHs  7  are arranged to form a continuous pattern along the die seal rings  38 , as shown in  FIG. 8 . 
     According to the crack-stopping structure and the method for forming the same provided by the first preferred embodiment, the TSHs  7  in the scribe line regions  5  and the TSHs  70  in the dies  3  are simultaneously formed. But only the TSHs  70  in the dies  3  are filled up with the metal material to form the TSV  7   v  while the TSHs  7  in the scribe line regions  5  are remained as hollow structures. Therefore, no extra process is required. More important, when the semiconductor wafer  1  is diced, the dicing tool may cut across the metal patterns  50 , and the stress resulted from the sawing process causes serious peeling at where the metal patterns  50  occupied. However, the peeling or cracking is obstructed and stopped by the hollow TSHs  7  formed between the metal patterns  50  and the dies  3 , and thus the neighboring dies  3  are protected from cracking. Consequently, delamination and/or cracking, which adversely impact the reliability and yield are prevented. 
     Please refer to  FIG. 9-10 ,  FIGS. 2-5 and 7  in the same time.  FIG. 9  is a flow chart illustrating a method for forming a crack-stopping structure provided by a second preferred embodiment of the present invention.  FIGS. 2-5, 7, and 10  are schematic drawings illustrating a method for forming a crack-stopping structure provided by the second preferred embodiment, wherein  FIG. 2  is a plan view showing an overall configuration of a semiconductor wafer according to the second preferred embodiment of the present invention,  FIG. 3  is a partially enlarged view of Circle A of  FIG. 2 , and  FIG. 10  is a cross-sectional view taken along a Line B-B′ of  FIG. 3 . Please note that elements the same in both of the first and second preferred embodiments are designated by the same numerals. As shown in  FIG. 9 , the method for forming a crack-stopping structure first provides a Step  20 : 
     STEP  20 : Providing a Semiconductor Wafer Comprising a Plurality of Dies Defined by a Plurality of Scribe Line Regions. 
     Please refer to  FIGS. 2-4 . The semiconductor wafer  1  includes a plurality of dies  3  that are defined and divided by a plurality of scribe line regions  5 . Each die  3  includes a plurality of semiconductor devices  30  formed therein, and a plurality of interconnections  32  are formed on the semiconductor devices  30  as shown in  FIG. 4 . As mentioned above, the interconnection  32  can be formed by Al-wiring process or Cu-damascene process, but not limited to this. Additionally, a distribution layer and a contact pad (both not shown) are selectively formed in the dies  3  for constructing an external electrical connection, but not limited to this. More important, a die seal ring  38  is formed simultaneously with forming the interconnections  32  and the distribution layer  34 . Accordingly, a plurality of die seal rings  38  are formed in the semiconductor wafer  1  for encompassing and surrounding the dies  3 , respectively. Please still refer to  FIGS. 4-5 . In the scribe line region  5 , a plurality of metal patterns  50  are formed therein. The metal patterns  50  can include alignment marks and/or test pads. 
     Please refer to  FIG. 9 . Next, a Step  22  is performed: 
     STEP  22 : Forming a Plurality of Through Silicon Vias in the Dies. 
     Please refer to  FIG. 10 . It is also noteworthy that the semiconductor wafer  1  includes a front side  1   a  and a back side  1   b . Next, a plurality of TSHs (not shown) are formed in the dies  3 . After forming the TSHs in the dies  3 , a barrier layer (not shown) and a buffer layer (not shown) can be formed in the TSHs in the dies  3  and followed by filling the TSHs in the dies  3  with a metal material to form a plurality of through silicon vias (TSVs)  7   v.    
     Please refer to  FIG. 9  again. Next, a Step  24  is performed: 
     STEP  24 : Forming a Plurality of Groups of Through Silicon Holes in the Scribe Line Regions. 
     Please refer to  FIG. 7 . After forming the TSVs  7   v  in the dies  3 , a plurality of groups of TSHs  7  are formed in the scribe line regions  5 . The groups of TSHs  7  are preferably formed in a single process performed in a single machine after forming the TSVs  7   v . According to the preferred embodiment, the TSHs  7  are preferably formed from the back side  1   b  of the semiconductor wafer  1  after completion of the semiconductor devices  30  and the interconnections  32 . However, the TSHs  7  can be formed from the front side  1   a  of the semiconductor wafer  1  after completion of the semiconductor devices  30  and the interconnections  32 . 
     It is noteworthy that the spatial relationship between the TSHs  7 , the metal patterns  50 , the die seal rings  38 , and the dies  3  are the same with those described in the first preferred embodiment, and thus those details are omitted in the interest of brevity. 
     According to the crack-stopping structure and the method for forming the same provided by the second preferred embodiment, the TSVs  7   v  in the dies  3  and the TSHs  7  in the scribe line regions  5  are sequentially formed. In other words, the TSVs  7   v  in the dies  3  and the TSHs  7  in the scribe line regions  5  are independently formed. More important, when the semiconductor wafer  1  is diced, the dicing tool may cut across the metal patterns  50 , and the stress resulted from the sawing process causes serious peeling at where the metal patterns  50  occupied. However, the peeling or cracking is obstructed and stopped by the hollow TSHs  7  formed between the metal patterns  50  and the dies  3 , and thus the neighboring dies  3  are protected from cracking. Consequently, delamination and/or cracking, which adversely impact the reliability and yield are prevented. 
     Additionally, please refer to  FIG. 11 , which is a top view of another modification to the crack-stopping structure provided by the present invention. According to the modification provided by the present invention, a plurality of groups of TSHs  7   r  are formed in the scribe line regions  5 . More important, the TSHs in the scribe line regions  5  can include not only a round shape as shown in  FIGS. 5 and 8 , but also a rectangular shape as shown in  FIG. 11 . According to the modification, a length the TSHs  7   r  is smaller than a width of the metal patterns  50 , but can be two to three times to a diameter of the TSVs  7   v  in the dies  3 . The groups of TSHs  7   r  are arranged correspondingly to the metal patterns  50 . Furthermore, the groups of TSHs  7   r  can be spaced apart from each other as shown in  FIG. 11 , but it is not limited that the groups of TSHs  7   r  can be arranged to form a continuous pattern along the die seal rings  38 . 
     Still additionally, after forming the hollow TSHs  7 / 7   r  in the scribe line regions  5  simultaneously with or after forming the TSVs  7   v  in the dies  3 , a packaging process can be performed. In the packaging process, the hollow TSHs  7  can be partially filled with a polymer, for example but not limited to, Benzocyclobutene (BCB). 
     It is well-known that TSV is a vertical electrical connection passing completely through the semiconductor wafer or a die so that they occupy less space. In other words, TSVs provide connections through the body of the dies leading smaller stack. And the present invention is able to be integrated with the TSV technology without complicating the processes. According to the crack-stopping structure and the method for forming the same provided by the present invention, the TSHs are formed simultaneously with or after forming the TSVs by the same methodology. The TSHs are formed in the scribe line regions and particularly formed between the metal patterns and the dies. More important, the TSHs are hollow structures having no metal or conductive material formed therein. When the semiconductor wafer is diced, the dicing tool may cut across the metal patterns, and the stress resulted from the sawing process causes serious peeling at where the metal patterns occupied. However, the peeling or cracking is obstructed and stopped by the hollow TSHs formed between the metal patterns and the dies, and thus the neighboring dies are protected from cracking. Consequently, delamination and/or cracking, which adversely impact the reliability and yield are prevented. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.