Patent Publication Number: US-2023162804-A1

Title: Memory including a plurality of portions and used for reducing program disturbance and program method thereof

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 17/498,400, filed on Oct. 11, 2021, entitled “MEMORY INCLUDING A PLURALITY OF PORTIONS AND USED FOR REDUCING PROGRAM DISTURBANCE AND PROGRAM METHOD THEREOF,” which is a continuation of U.S. application Ser. No. 16/827,734, filed on Mar. 24, 2020, entitled “MEMORY INCLUDING A PLURALITY OF PORTIONS AND USED FOR REDUCING PROGRAM DISTURBANCE AND PROGRAM METHOD THEREOF,” which is a continuation of International Application No. PCT/CN2020/074580, filed on Feb. 10, 2020, all contents of which are incorporated herein by reference in their entireties. 
    
    
     BACKGROUND 
     The disclosure is related to a memory and a program method, and more particularly, a memory including a plurality of portions and used for reducing program disturbance and a program method thereof. 
     In order to increase the capacity of a memory, a memory with a three-dimensional structure has been developed. For example, a three-dimensional stack NAND flash memory can be available presently. 
     A three-dimensional structure of a memory can include a plurality of layers so as to store more data on a same area. This structure has been proved to be effective for increasing capacity of memory. 
     However, program disturbance will become more significant when the number of layers is increased. Program disturbance will lead to a higher failure rate of programming a memory. In addition, pass voltage disturbance also occurs when using a memory with a plurality of layers. 
     Hence, a solution for reducing program disturbance and pass voltage disturbance when operating a three-dimensional memory is in need in the field. 
     SUMMARY 
     An embodiment provides a memory including a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line from bottom to top. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line from bottom to top. The controller is used to apply a first voltage to the first word line to an (x−2)th word line, a second voltage to an (x−1)th word line, and a third voltage to an (x+1)th word line when an xth word line is used to perform a program operation. x, k and m are positive integers. 
     An embodiment provides a memory including a first portion, a second portion and a controller. The first portion includes an (m+1)th word line to an nth word line from bottom to top. The second portion is formed below the first portion and includes a (k+1)th word line to an mth word line from bottom to top. The controller is used to apply a first voltage to an (x+2)th word line to the nth word line, a second voltage to an (x+1)th word line, a third voltage to an (x−1)th word line, a fourth voltage to the (m+1)th word line to an (x−2)th word line, and a fifth voltage to the (k+1)th word line to the mth word line when an xth word line is used to perform a program operation. x, k and m are integers. The fifth voltage is lower than the fourth voltage. 
     An embodiment provides a program method used for operating a memory. The memory includes a first portion and a second portion. The first portion includes a first word line to a kth word line from bottom to top. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line from bottom to top. The program method includes applying a first voltage to the to the first word line to an (x−2)th word line when an xth word line is used to perform a program operation; applying a second voltage to an (x−1)th word line; and applying a third voltage to an (x+1)th word line. 
     An embodiment provides a program method used for operating a memory. The memory includes a first portion and a second portion formed below the first portion. The first portion includes an (m+1)th word line to an nth word line from bottom to top. The second portion includes a (k+1)th word line to an mth word line from bottom to top. The program method includes applying a first voltage to an (x+2)th word line to the nth word line when an xth word line is used to perform a program operation; applying a second voltage to an (x+1)th word line; applying a third voltage to an (x−1)th word line; applying a fourth voltage to the (m+1)th word line to an (x−2)th word line; and applying a fifth voltage to the (k+1)th word line to the mth word line. x, k and m are integers. The fifth voltage is lower than the fourth voltage. 
     These and other objectives of the present disclosure will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    illustrates a memory according to an embodiment. 
         FIG.  2    illustrates the memory of  FIG.  1    operated in another condition. 
         FIG.  3    illustrates a memory according to another embodiment. 
         FIG.  4    and  FIG.  5    illustrate the memory of  FIG.  3    operated in other conditions. 
         FIG.  6    illustrates a memory according to another embodiment. 
         FIG.  7    illustrates a memory according to another embodiment. 
         FIG.  8    illustrates the memory of  FIG.  7    operated in another condition. 
         FIG.  9    illustrates a memory according to another embodiment. 
         FIG.  10    illustrates the memory of  FIG.  9    operated in another condition. 
         FIG.  11    illustrates a memory according to another embodiment. 
         FIG.  12    illustrates a flowchart of an program method according to an embodiment 
         FIG.  13    illustrates a flowchart of an program method according to another embodiment 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1    illustrates a memory  100  according to an embodiment. The memory  100  may include a first portion  110 , a second portion  120  and a controller  190 . The first portion  110  may include a first word line WL 1  to a kth word line WLk from bottom to top. The second portion  120  may be formed above the first portion  110  and includes a (k+1)th word line WL(k+1) to an mth word line WLm from bottom to top. 
     In the text, when a word line is said to be programmed, it may mean the word line is used to perform a program operation. A program operation said in the text may be an operation for programming a memory cell formed using, for example, a set of transistors. 
     When an xth word line WLx is used to perform a program operation, the controller  190  may apply a program voltage Vpgm to the xth word line WLx; the controller  190  may apply a first voltage V 1  to the first word line WL 1  to an (x−2)th word line WL(x−2); the controller  190  may apply a second voltage V 2  to an (x−1)th word line WL(x−1); and the controller  190  may apply third voltage V 3  is applied to an (x+1)th word line WL(x+1). x, k and m are positive integers, 1&lt;k&lt;m and 3≤x. 
     As shown in  FIG.  1   , the controller  190  may apply a fourth voltage V 4  to an (x+2)th word line WL(x+2) to the mth word line WLm when the xth word line WLx is used to perform the program operation, and x&lt;m−1. 
     In  FIG.  1   , the xth word line WLx is located in the first portion  110  as an example; however, the xth word line WLx may be located in the second portion  120  in another condition. 
       FIG.  2    illustrates the memory  100  of  FIG.  1    operated in another condition. In  FIG.  2   , the xth word line WLx is located in the second portion  120 . Regarding voltages applied,  FIG.  2    may be similar to  FIG.  1   , and it is not repeatedly described. 
       FIG.  1    and  FIG.  2    are merely examples, and each of the word lines WL(x−2), WL(x−1), WL(x+1) and WL(x+2) mentioned above is allowed to be located in the first portion  110  or the second portion  120 . 
     Regarding the memory  100 , the first voltage V 1  may have a first level if the xth word line WLx is in the first portion  110  and a second level if the xth word line WLx is in the second portion  120 , where the first level may be lower than the second level. For example, the first voltage V 1  in  FIG.  1    may have a lower value than the first voltage V 1  in  FIG.  2   . 
       FIG.  3    illustrates a memory  300  according to another embodiment. Regarding the memories  100  and  300 , the memory  300  may include a third portion  130  in addition to the first portion  110  and the second portion  120 . 
     The third portion  130  may be formed above the second portion  120  and includes an (m+1)th word line WL(m+1) to an nth word line WLn from bottom to top. As shown in  FIG.  3   , the controller  190  may apply a fourth voltage V 4  to the (x+2)th word line WL(x+2) to the nth word line WLn when the xth word line WLx is used to perform the program operation, m&lt;n, and x&lt;(n−1). 
       FIG.  4    and  FIG.  5    illustrate the memory  300  of  FIG.  3    operated in other conditions. In  FIG.  3   , the xth word line WLx used to perform a program operation is in the first portion  110 . In  FIG.  4    and  FIG.  5   , the xth word line WLx is in the second portion  120  and the third portion  130  respectively. 
       FIG.  3    to  FIG.  5    are merely examples, and each of the word lines WL(x−2), WL(x−1), WL(x+1) and WL(x+2) mentioned above is allowed to be located in the first portion  110 , the second portion  120  or third portion  130 . 
     Regarding the memory  300 , the first voltage V 1  may have a first level if the xth word line WLx is in the first portion  110 , a second level if the xth word line WLx is in the second portion  120 , and a third level if the xth word line WLx is in the third portion  130 , where the first level may be lower than the second level, and the second level may be lower than the third level. For example, the first voltage V 1  in  FIG.  3    may have a lower value than the first voltage V 1  in  FIG.  4   , and the first voltage V 1  in  FIG.  4    may have a lower value than the first voltage V 1  in  FIG.  5   . 
       FIG.  6    illustrates a memory  600  according to another embodiment. The memory  600  may be similar to the memory  100  of  FIG.  1    and  FIG.  2   . However, the structure of  FIG.  1    and  FIG.  2    may include merely one deck, and the memory  600  may have a structure of two decks. In other word, the memory  100  may have a one-deck structure, and the memory  600  may have a two-deck structure. As shown in  FIG.  6   , the first portion  110  is of a deck DECK 1 , and the second portion  120  is of a deck DECK 2 . The two decks DECK 1  and DECK 2  may be separated by a joint oxide layer OL. The memory  600  may include a lower dummy word line DL, an upper dummy word line DU and the joint oxide layer OL. The lower dummy word line DL may be formed above the first portion  110 . The upper dummy word line DU may be formed below the second portion  120 . The joint oxide layer OL may be formed between the lower dummy word line DL and the upper dummy word line DU. The voltages applied to a one-deck structure may be like the voltages applied to a two-deck structure according to embodiments. For example, the voltages applied to the word lines of the memory  600  may be like the voltages applied to the word lines of the memory  100  of  FIG.  1    and  FIG.  2   , and it is not repeatedly described. 
       FIG.  7    and  FIG.  8    illustrate a memory  700  operated in two conditions according to another embodiment. The memory  700  may include a first portion  710 , a second portion  720  and a controller  190 . The first portion  710  may include an (m+1)th word line WL(m+1) to an nth word line WLn from bottom to top. The second portion  720  may be formed below the first portion  710  and include a (k+1)th word line WL(k+1) to an mth word line WLm from bottom to top. 
     When an xth word line is used to perform a program operation, the controller  190  may apply a first voltage V 71  to an (x+2)th word line WL(x+2) to the nth word line WLn; the controller  190  may apply a second voltage V 72  to an (x+1)th word line WL(x+1); and the controller  190  may apply a third voltage V 73  to an (x−1)th word line WL(x−1). 
     If the word line WLx is located in the second portion  720  as shown in  FIG.  7   , when the xth word line is used to perform the program operation, the controller  190  may apply a fifth voltage V 75  to the (k+1)th word line WL(k+1) to an (x−2)th word line WL(x−2). In  FIG.  7   , x, k and m are integers, (k+2)&lt;x&lt;(m+1). The condition of  FIG.  7    may be substantially similar to the condition of  FIG.  1   ; however,  FIG.  7    is provided to introduce  FIG.  8    to  FIG.  11   . 
     If the word line WLx used to perform a program operation is located in the first portion  710  as shown in  FIG.  8   , the first voltage V 71 , the second voltage V 72  and the third voltage V 73  may be applied by the controller  190  as shown in  FIG.  7   ; however, the controller  190  may apply a fourth voltage V 74  to the (m+1)th word line WL(m+1) to an (x−2)th word line WL(x−2). The controller  190  may apply the fifth voltage V 75  to the (k+1)th word line WL(k+1) to the mth word line WLm. In  FIG.  8   , x, k and m are integers, 0&lt;k&lt;m, (m+2)&lt;x&lt;(n- 1 ). The fifth voltage V 75  may be lower than the fourth voltage V 74 . 
     According to another embodiment, as shown in  FIG.  6   , the first portion  710  and the second portion  720  shown in  FIG.  7    and  FIG.  8    may be of two decks respectively, and the two decks may be separated by a joint oxide layer. As shown in  FIG.  6   , the two decks may have an upper dummy word line and a lower dummy word line respectively. 
       FIG.  9    illustrates a memory  900  according to another embodiment.  FIG.  10    illustrates the memory  900  of  FIG.  9    operated in another condition. 
     As shown in  FIG.  9   , the memory  900  may have three portions  910 ,  920  and  930 . The first portion  910  and the second portion  920  may be similar to the portions  710  and  720  shown in  FIG.  7   . The third portion  930  may be formed above the first portion  910  and include a plurality of word lines WL(n+1) to WLq from bottom to top. The condition of  FIG.  9    may be similar to  FIG.  7    where the word line WLx used to perform a program operation is located in the lowermost portion  920 . The controller  190  may apply the first voltage V 71  to the plurality of word lines WL(n+1) to WLq of  FIG.  9   . The variable q is an integer, and q&gt;(n+1). 
     The memory  900  of  FIG.  10    may have the same structure as shown in  FIG.  9   . The condition of  FIG.  10    may be similar to  FIG.  8    where the word line WLx used to perform a program operation is located in the portion  910  above the lowermost portion  920 . The voltages applied to the portions  910  and  920  may be like the voltages applied to the portions  710  and  720  of  FIG.  8   . As shown in  FIG.  9   , the controller  190  may apply the first voltage V 71  to the plurality of word lines WL(n+1) to WLq of the portion  930 . 
       FIG.  11    illustrates a memory  1100  according to another embodiment. The first portion  1110  and the second portion  1120  of the memory  1100  may be like the portions  710  and  720  of  FIG.  8   , and the memory  1100  may further include a third portion  1130  formed below the second portion  1120 . Similarly, the xth word line WLx may be used to perform a program operation. Hence, the memory  1100  may include three portions and have a structure like the memory  900  of  FIG.  9    and  FIG.  10   . As shown in  FIG.  11   , the third portion  1130  may include a first word line WL 1  to a kth word line WLk from bottom to top. The controller  190  may apply a six voltage V 76  to the first word line WL 1  to the kth word line WLk. 0&lt;k, and the sixth voltage V 76  is lower than the fifth voltage V 75 . 
     Although the numberings of the portions and word lines are not the same, the memories  900  and  1100  shown in  FIG.  9    to  FIG.  11    may be regarded as a same memory operated in different conditions. 
     In  FIG.  9   , the word line (e.g., WLx) used to perform a program operation is located in a lowermost portion of the three portions. 
     In  FIG.  10   , the word line (e.g., WLx) used to perform a program operation is located in a second lowermost portion of the three portions. 
     In  FIG.  11   , the word line (e.g., WLx) used to perform a program operation is located in an uppermost portion of the three portions. 
     As shown in  FIG.  9    to  FIG.  11   , when the word line WLx used to perform a program operation is located in the different portions, different voltages may be applied to the word lines below the word line WLx according to the corresponding portion(s). 
     In the example of  FIG.  9    to  FIG.  11   , the relationship among voltages may be V76&lt;V75&lt;V74. In other words, a same voltage may be applied to word lines of a same portion located below the portion corresponding to the word line (e.g., WLx) used to perform a program operation, and a lower voltage may be applied to word lines of a portion located lower. 
       FIG.  12    illustrates a flowchart of a program method  1200  according to an embodiment. The program method  1200  may be used to operate the memory  100  of  FIG.  1    and  FIG.  2    and the memory  300  of  FIG.  3    to  FIG.  5   . The method  1200  may include following steps. 
     Step  1210 : apply a first voltage V 1  to the to the first word line WL 1  to an (x−2)th word line WL(x−2) when an xth word line WLx is used to perform a program operation; 
     Step  1220 : apply a second voltage V 2  to an (x−1)th word line WL(x−1); and 
     Step  1230 : apply a third voltage V 3  to an (x+1)th word line WL(x+1). 
     Step  1210  to Step  1230  may be performed when the xth word line WLx is used to perform the program operation. In addition, when the xth word line WLx is used to perform the program operation, a fourth voltage V 4  may be applied as show in  FIG.  1    to  FIG.  5    and as described above. The relationships among the voltages (e.g., V 1 , V 2 , V 3  and V 4 ) shown in  FIG.  1    to  FIG.  5    may be as described above. 
       FIG.  13    illustrates a flowchart of a program method  1300  according to an embodiment. The program method  1300  may be used to operate the memory  700  of  FIG.  8   , the memory  900  of  FIG.  9    and  FIG.  10   , and the memory  1100  of  FIG.  11   . The method  1300  may include the following steps. 
     Step  1310 : apply a first voltage V 71  to an (x+2)th word line WL(x+2) to the nth word line WLn when an xth word line WLx is used to perform a program operation; 
     Step  1320 : apply a second voltage V 72  to an (x+1)th word line WL(x+1); 
     Step  1330 : apply a third voltage V 73  to an (x−1)th word line WL(x−1); 
     Step  1340 : apply a fourth voltage V 74  to the (m+1)th word line WL(m+1) to an (x−2)th word line WL(x−2); and 
     Step  1350 : apply a fifth voltage V 75  to the (k+1)th word line WL(k+1) to the mth word line WLm. 
     Step  1310  to Step  1350  may be performed when the xth word line WLx is used to perform the program operation. In addition, when the xth word line WLx is used to perform the program operation, a six voltage V 76  may be applied as shown in  FIG.  11    and as described above. The relationships among the voltages (e.g., V 71 , V 72 , V 73 , V 74 , V 75  and V 76 ) shown in  FIG.  7    to  FIG.  11    may be as described above. 
     In summary, by using a memory sectioned to have a plurality of portions and applying voltages to the word lines of the memory according to the portions, program disturbance and pass voltage disturbance may be reduced according to simulations and experiments. In addition, by using a same voltage source to apply a voltage to word lines of a same portion or word lines of different portions, less voltage sources may be required, and the area of system may be smaller. Hence, problems of the field can be reduced. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the present disclosure. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.