Patent Publication Number: US-9432036-B1

Title: Radio frequency current steering digital to analog converter

Description:
TECHNICAL FIELD 
     Examples of the present disclosure generally relate to electronic circuits and, in particular, to a radio frequency (RF) current steering digital-to-analog converter (DAC). 
     BACKGROUND 
     Digital-to-analog conversion is the process of converting digital (binary) codes into a continuous range of analog signal levels. Digital codes can be converted into analog voltage, analog current, or analog charge signals using a digital-to-analog converter (DAC). Some wireless applications require conversion of digital codes into an analog signal modulating a radio frequency (RF) carrier. In some systems, the analog output of a DAC is low-pass filtered to remove aliased components in the second and third Nyquist zones. The analog signal is then translated to a carrier frequency using a mixer. The output of the mixer can be filtered to remove one of the side bands. A power amplifier amplifies the remaining side band for transmission. 
     One type of DAC includes a plurality of current steering cells, where each current steering cell includes a number of switches coupled to a current source. One current steering cell architecture includes four switches so that there is constant switching activity on the drain of the current source regardless of the digital input code, resulting in code independent dynamic performance. However, such additional switches come at the expense of increased area and power. 
     SUMMARY 
     An RF current steering DAC is described. In an example, a current steering circuit for a digital-to-analog converter (DAC) includes a source-coupled transistor pair responsive to a differential gate voltage; a current source coupled to the source-coupled transistor pair operable to source a bias current; a load circuit coupled to the source-coupled transistor pair operable to provide a differential output voltage; a driver having a first input, a second input, and a differential output, the differential output providing the differential gate voltage; and combinatorial logic having a data input, a clock input, a true output, and a complement output, the true output and the complement output respectively coupled to the first input and the second input of the driver, the combinatorial logic operable to exclusively OR a data signal on the data input and a clock signal on the clock input. 
     In another example, a digital-to-analog converter (DAC) includes a decoder operable to output a data signal in response to binary input codes, and a plurality of output cells coupled between the decoder and a load circuit to provide an analog output signal centered at a carrier frequency. Each of the plurality of output cells includes a switch circuit coupled to the load circuit; a driver having an input and an output, the output operable to control the switch; and combinatorial logic having a data input operable to receive a respective bit of the data signal, a clock input operable to receive a clock signal, and an output, coupled to the input of the driver, the combinatorial logic operable to exclusively OR the data input and the clock input. 
     In another example, a method of digital-to-analog conversion includes generating a data signal in response to binary input codes; operating a plurality of output cells to provide an analog output signal centered at a carrier frequency, where each of the plurality of output cells is operated by: exclusively ORing a respective bit of the data signal and a clock signal to generate a control signal; and selectively driving a load circuit based on the control signal. 
     These and other aspects may be understood with reference to the following detailed description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope. 
         FIG. 1  is a block diagram depicting an example of a digital-to-analog converter (DAC). 
         FIG. 2  is a block diagram depicting an example of the output network that can be used in a DAC, such as the DAC shown in  FIG. 1 . 
         FIG. 3  is a block diagram depicting an example of an output cell. 
         FIG. 4  is a graph depicting an output spectrum of the DAC of  FIG. 1 . 
         FIG. 5  is a schematic diagram depicting a more detailed example of an output cell. 
         FIG. 6  is a flow diagram depicting an example of a method of digital-to-analog conversion. 
         FIG. 7  illustrates an example architecture of an FPGA. 
     
    
    
     To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples. 
     DETAILED DESCRIPTION 
     Various features are described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. They are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. In addition, an illustrated embodiment need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular embodiment is not necessarily limited to that embodiment and can be practiced in any other embodiments even if not so illustrated, or if not so explicitly described. 
     An RF current steering DAC is described. In an example, a current steering cell in a DAC includes a source-coupled transistor pair responsive to a differential gate voltage. A current source is coupled to the source-coupled transistor pair and is operable to source a bias current. A driver is coupled to the source-coupled transistor pair to provide a differential gate voltage. Combinatorial logic is coupled to the driver. In a regular baseband mode of operation, the data passes through combinatorial logic to the driver without modification. In an RF mode of operation, the combinatorial logic is enabled to perform an exclusive OR of the data and the clock and the output is coupled to the driver. As such, an RF DAC can be implemented without the need for a mixer in the signal chain. Further, only a pair of transistor switches are needed for each current steering cell, which provides for less parasitic capacitance on the current source and an improvement in settling time as opposed to current steering cells having more than two switches. The switches, drivers, and combinatorial logic can all remain in the thin oxide domain, resulting in power and area savings. These and other aspects can be understood with reference to the following figures. 
       FIG. 1  is a block diagram depicting an example of a digital-to-analog converter (DAC)  100 . The DAC  100  includes a decoder  102 , an output network  106 , and a load circuit  112 . The decoder  102  includes an input  101  for receiving binary codes to be converted (“binary input”). The input  101  has a width of N bits for receiving N-bit binary codes. A clock port of the decoder  102  receives a clock signal “CLK”. The decoder  102  includes an output  104  operable to provide a data signal as output. The decoder  102  outputs control codes to control the output network  106  based on the respective binary input. The decoder  102  generates an output for an N-bit binary code for each cycle of the clock signal CLK 1 . 
     The output  104  has a width of M bits for providing M-bit control codes to the output network  106 . As described herein, the output  104  drives transistor switches in the output network  106 . In an example, the output network  106  includes current-mode logic (CML) transistor switches, and the output  104  comprises a differential output. In another example, the output network  106  includes complementary metal oxide semiconductor (CMOS) transistor switches, and the output  104  comprises a single ended output. 
     The output network  106  is coupled to the output  104  of the decoder  102 . The output network  106  also includes a clock port  110  configured to receive a clock signal (CLK 2 ). The output network  106  includes output cells  108   1  through  108   M  (collectively referred to as “output cells  108 ”). Each of the output cells  108  includes a clock port configured to receive the clock signal CLK 2 . Each of the output cells  108  receives a respective bit slice of the output  104 . Each of the output cells  108  further includes a data modulator  109 . The data modulator  109  is operable to modulate the input data at the frequency of CLK 2  to shift the data into higher Nyquist zones. By selecting the rate of CLK 2 , the DAC  100  can directly transition from digital to RF, obviating the need for additional components, such as mixers. The output network  106  includes an analog output  114 , which comprises the sum of the outputs of the output cells  108 . 
     In operation, each of the output cells  108  drives the load circuit  112  based on the control codes output by the decoder  102 . The level of the analog output varies based on the number of output cells  108  driving the load circuit  112 , which in turn is controlled by the control codes output by the decoder  102 . Through operation of the data modulator  109  in each of the output cells  108 , the analog output of the output network  106  includes sum and difference components centered at a carrier frequency. An exemplary spectrum of the analog output is described below. 
     The load circuit  112  is coupled to the analog output  114 . The load circuit  112  can include various types of circuits for sourcing or sinking the analog output. For example, the load circuit  112  can include resistor loads that convert analog output current to an analog output voltage. In another example, the load circuit  112  can include active circuit(s), such as current amplifier(s) for amplifying the analog output current or trans-resistance amplifier(s) for amplifying and converting the analog output current to an analog output voltage. 
     The DAC  100  is one example DAC in which the output cells  108  described herein can be used. The decoder  102  can employ various decoding schemes, including binary weighted coding, thermometer coding (unary weighted), or a combination thereof (e.g., a segmented DAC). Regardless of the input and particular coding used, the decoder  102  generally outputs a data signal used to drive the output cells  108  in the output network  106 . 
       FIG. 2  is a block diagram depicting an example of the output network  106  that can be used in a DAC, such as the DAC  100  shown in  FIG. 1 . As described above, the output network  106  comprises the output cells  108   1  through  108   M . The output cell  108   1  receives the first bit slice of each of the output  104  (referred to as “D[ 1 ]” for the first bit). In general, the kth output cell  108   k  receives the kth bit slice of the output  104 . Each of the output cells  108  also receives the clock signal (CLK 2 ). 
     Each of the output cells  108  is switched to steer current to either a positive end  114 P or negative end  114 N of the analog output  114 . The switching is based on the control code input (D[k]) and the clock input (CLK 2 ). In the example, the load circuit  112  comprises a resistor R P  coupled to the positive end  114 P, and a resistor R N  coupled to the negative end  114 N. In the example shown, the resistors R P  and R N  are coupled to a supply voltage (Vsup) and the output network  106  sinks a current I_sum_n on the negative end  114 N and a current I_sum_p on the positive end  114 P of the analog output  114 . In another example, the resistors R P  and R N  can be coupled to a reference voltage (e.g., electrical ground) and the output network  106  can supply the current I_sum_n and the current I_sum_p. 
       FIG. 3  is a block diagram depicting an example of an output cell  108   k  used in the output network  106  shown in  FIG. 2  (where kε{1 . . . M}). The output cell  108   k  comprises an output cascode  302 , a switch  306 , a current source  308 , and the data modulator  109 . The output cascode  302  and the current source  308  receive bias voltage from a voltage bias generator  310 . The switch  306  selectively couples the output cascode  302  and the current source  208  based on an output  318  of the data modulator  109 . The output cascode  302  drives an output  320 , which in the present example sinks a current I_out. The output cascode  302  is optional and can be used to shield the analog output  114  from parasitic capacitance of the output cell  108 . 
     The data modulator  109  includes a driver  312  and exclusive OR (XOR) logic  314 . The XOR logic  314  includes a pair of inputs coupled to receive a data bit slice D[k] and the clock signal CLK 2 . The XOR logic  314  also includes a control input coupled to receive an enable signal. The enables signal determines whether the XOR logic  314  performs an XOR&#39;s D[k] and CLK 2 , or whether the XOR logic  314  passes D[k]. An output  322  of the XOR logic  314  provides the XOR of D[k] and CLK 2  or D[k], depending on the state of the enable signal. The output  318  of the driver  312  is coupled to control the switch  306 . In an example, the XOR logic  314  includes an XOR gate having an enable input. In general, the XOR logic  314  comprises combinatorial logic operable to perform an XOR operation based on state of the enable signal. 
     In operation, XORing the clock signal CLK 2  with the data D[k] modulates the data D[k] into the higher Nyquist zones.  FIG. 4  is a graph  400  depicting an output spectrum of the DAC  100 . The graph  400  includes an axis  402  representing frequency in Hertz (Hz), and an axis  404  representing amplitude in arbitrary units. The graph  400  shows a first Nyquist zone  406 , a second Nyquist zone  408 , and a third Nyquist zone  410 . The bandwidth of the first Nyquist zone  406  is between 0 and F s /2. The bandwidth of the second Nyquist zone  408  is between F s /2 and F s . The bandwidth of the third Nyquist zone  410  is between F s  and 2F s . 
     As shown by  412 , the baseband signal is located in the first Nyquist zone  406  centered at a frequency F 0 . As shown by  414 , a lower side band of the RF signal is located in the second Nyquist zone  408  centered at a frequency F s -F 0 . A shown by  416 , an upper side band of the RF signal is located in the third Nyquist zone  410  centered at a frequency F s +F 0 . Thus, the DAC  100  transfers the power of the baseband signal in the first Nyquist zone  406  into the second and third Nyquist zones  408  and  410 . Power can also be transferred to higher Nyquist zones, but the dominant transfer is to the second and third Nyquist zones. 
     As shown in  FIG. 3 , the output cell  108   k  can be implemented using combinatorial logic upstream of the current steering switches. Compared to previous current steering cell architectures, the output cell  108   k  requires fewer drivers/switches and requires lower power and smaller implementation area. The modulation scheme inherently self-synchronizes the data with the clock. The scheme is compatible with deed sub-micron processes. Further, the output cell  108   k  removes the need for a mixer in the signal chain. 
       FIG. 5  is a schematic diagram depicting a more detailed example of the output cell  108   k . In general, the output cell  108   k  comprises a plurality of n-channel field effect transistors (FETs), such as n-type metal oxide semiconductor FETs (n-type MOSFETS, also referred to as NMOS transistors) or the like. The switch  306  comprises a source-coupled transistor pair that includes the transistor M 1  and the transistor M 2 . The sources of the transistors M 1  and M 2  are coupled to the node N 1 , which is in turn coupled to the current source  308 . The drain of the transistor M 1  is coupled to a source of a transistor M 3 , and the drain of the transistor M 2  is coupled to a source of a transistor M 4 . A gate of the transistor M 1  is coupled to an output  318 P of the driver  312 , and the gate of the transistor M 2  is coupled to an output  318 N of the driver  312 . The output  318 P is a positive end of a differential output of the driver  312 , and the output  318 N is a negative end of the differential output of the driver  312 . The transistors M 3  and M 4  are part of the output cascode  302 . Gates of the transistors M 3  and M 4  receive a bias voltage (Vbias). The drain current of the transistor M 3  is the output current I_out_p, and the drain current of the transistor M 4  is the output current I_out_n. The output cell  108  operates as described above with respect to  FIG. 3 . 
     Although the output cell  108   k  has been described as include a switch with n-type MOSFETS (current sink implementation), other examples of the output cell  108   k  can include a switch implemented using p-channel FETs, such as p-type MOSFETS (current source implementation). Further, the output cell  108   k  has been described as being responsive to a differential input (e.g., a current-mode logic (CML) implementation). It is to be understood that the output cell  108   k  can also be implemented with a single-ended input such as in a pure CMOS implementation. 
       FIG. 6  is a flow diagram depicting an example of a method  600  of digital-to-analog conversion. The method  600  may be understood with reference to  FIGS. 1 through 5  above. The method  600  begins at block  602 , where the decoder  102  generates a data signal response to binary input codes. At block  603 , a determination is made whether the output cells  108  operate in baseband or RF mode. If in baseband mode, the method  600  proceeds to block  610 . At block  610 , output cells  108  provide an analog output signal at baseband (i.e., without a carrier frequency). The block  610  can include a block  612 , where the XOR logic  314  is disabled in the baseband mode. 
     If in RF mode at block  603 , the method  600  proceeds to block  604 . At block  604 , output cells  108  provide an analog output signal centered at a carrier frequency. The block  604  can include blocks  606  through  608 . At block  606 , for each output cell  108 , the output cell  108  XOR&#39;s a bit of the data signal with a clock signal to generate a control signal. At block  608 , the output cell  108  selectively drives the load circuit  112  based on the control signal. 
     The output cells  108  described herein can be used in various DAC applications, including in DACs on various types of integrated circuits. For example, the output cells  108  can be used in a DAC on a programmable integrated circuit, such as a field programmable gate array (FPGA).  FIG. 7  illustrates an example architecture of an FPGA  700  that includes a large number of different programmable tiles including multi-gigabit transceivers (“MGTs”)  701 , configurable logic blocks (“CLBs”)  702 , random access memory blocks (“BRAMs”)  703 , input/output blocks (“IOBs”)  704 , configuration and clocking logic (“CONFIG/CLOCKS”)  705 , digital signal processing blocks (“DSPs”)  706 , specialized input/output blocks (“I/O”)  707  (e.g., configuration ports and clock ports), and other programmable logic  708  such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (“PROC”)  710 . 
     In some FPGAs, each programmable tile can include at least one programmable interconnect element (“INT”)  711  having connections to input and output terminals  720  of a programmable logic element within the same tile, as shown by examples included at the top of  FIG. 7 . Each programmable interconnect element  711  can also include connections to interconnect segments  722  of adjacent programmable interconnect element(s) in the same tile or other tile(s). Each programmable interconnect element  711  can also include connections to interconnect segments  724  of general routing resources between logic blocks (not shown). The general routing resources can include routing channels between logic blocks (not shown) comprising tracks of interconnect segments (e.g., interconnect segments  724 ) and switch blocks (not shown) for connecting interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments  724 ) can span one or more logic blocks. The programmable interconnect elements  711  taken together with the general routing resources implement a programmable interconnect structure (“programmable interconnect”) for the illustrated FPGA. 
     In an example implementation, a CLB  702  can include a configurable logic element (“CLE”)  712  that can be programmed to implement user logic plus a single programmable interconnect element (“INT”)  711 . A BRAM  703  can include a BRAM logic element (“BRL”)  713  in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile  706  can include a DSP logic element (“DSPL”)  714  in addition to an appropriate number of programmable interconnect elements. An IOB  704  can include, for example, two instances of an input/output logic element (“IOL”)  715  in addition to one instance of the programmable interconnect element  711 . As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element  715  typically are not confined to the area of the input/output logic element  715 . 
     In the pictured example, a horizontal area near the center of the die (shown in  FIG. 7 ) is used for configuration, clock, and other control logic. Vertical columns  709  extending from this horizontal area or column are used to distribute the clocks and configuration signals across the breadth of the FPGA. 
     Some FPGAs utilizing the architecture illustrated in  FIG. 7  include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, processor block  710  spans several columns of CLBs and BRAMs. 
     The processor block  710  can include various components ranging from a single microprocessor to a complete programmable processing system of microprocessor(s), memory controllers, peripherals, and the like. 
     Note that  FIG. 7  is intended to illustrate only an exemplary FPGA architecture. For example, the numbers of logic blocks in a row, the relative width of the rows, the number and order of rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top of  FIG. 7  are purely exemplary. For example, in an actual FPGA more than one adjacent row of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the FPGA. Moreover, the FPGA of  FIG. 7  illustrates one example of a programmable IC that can employ examples of the interconnect circuits described herein. The interconnect circuits described herein can be used in other types of programmable ICs, such as complex programmable logic devices (CPLDs) or any type of programmable IC having a programmable interconnect structure for selectively coupling logic elements. The FPGA  700  can include a DAC  750  having output cells  108 . 
     While the foregoing is directed to specific examples, other and further examples may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.