Patent Publication Number: US-2002003743-A1

Title: Memory device

Description:
BACKGROUND OF THE INVENTION  
       [0001] 1. Field of the Invention  
       [0002] The present invention relates to a multi port SRAM (Static Random Access Memory) including MISFETs (Metal Insulator Semiconductor Field Effect Transistors) and, more particularly, to a technique for reading and writing data from and into memory cells of the SRAM.  
       [0003] 2. Description of the Background Art  
       [0004] In an integrated circuit, an SRAM is used to cache data or instructions, i.e., to function to temporarily hold data therein for transmission of data to a CPU (Central Processing Unit) in timed relation to the CPU and to store the state of a sequential circuit therein. In recent years, emphasis has been placed on the rate at which data is written into and read from the memory. To increase a memory bandwidth, there has been proposed a technique in which a plurality of I/O ports are provided to the memory cells of the SRAM. Examples of this technique include a dual port static memory cell having one read port and one write port, and a multi port static memory cell having a multiplicity of read ports and a multiplicity of write ports.  
       [0005]FIG. 34 conceptually illustrates a configuration of a background art SRAM including a memory cell array and its peripheral components. Memory cells in the array are disposed in a matrix having m rows and n columns, and a memory cell in the i-th row, j-th column is designated by MC 1j . In FIG. 34 is shown the reference character MC 13  designating a memory cell disposed in the first row, the third column.  
       [0006] The SRAM shown in FIG. 34 is configured to have word lines extending along the rows and bit lines extending along the columns. A word line decoder  3  is connected to word line groups  30   1  (i=1, 2, 3, . . . , m-1, m), and selectively activates a word line group  301  corresponding to a row address RA inputted thereto. A bit line decoder  4  is connected to bit line groups  40   j  (j=1, 2, 3, . . . , n-1, n), and selectively activates a bit line group  40   j  corresponding to a column address CA inputted thereto.  
       [0007] The word line groups  30   i  and the bit line groups  40   j  intersect each other at the memory cells MC ij . In ether words, a common word line group is provided in corresponding relation to a plurality of memory cells arranged along each row, and a common bit line group is provided in corresponding relation to a plurality of memory cells arranged along each column.  
       [0008] Each of the word line groups  30   1  includes a write word line  31   1 , a read word line  33   1 , and a read complement word line  32   i . The read word line  33   1 , and the read complement word line  32   1  constitute a read word line pair. Each of the bit line groups  40   j  includes a write data bit line  41   j , a write data complement bit line  42   j , and a read data bit line  43   j . The write data bit line  4 l j  and the write data complement bit line  42   j  constitute a write data bit line pair.  
       [0009]FIG. 35 is a circuit diagram illustrating a common structure of every memory cell MC. Since the structure of the memory cells MC is not dependent basically upon the row and column locations (i, j), the subscripts denoting the row and column locations are omitted in FIG. 35.  
       [0010] The memory cell MC shown in FIG. 35 comprises a storage part (referred to hereinafter as a “storage cell”) SC having a pair of inverters L 1  and L 2  comprising a cross-coupled latch circuit, a read circuit RK, and access transistors QN 3  and QN 4 .  
       [0011] In the storage cell SC, the inverter L 1  has transistors QP 1  and QN 4  connected in series, and the inverter L 2  has transistors QP 2  and QN 2  connected in series. The read circuit RK comprises a tristate inverter having transistors QP 3 , QP 4 , QN 5 , QN 6  connected in series.  
       [0012] N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used as the transistors QN 1  to QN 6 , and P-type MOSFETs are used as the transistors QP 1  to QP 4 . For example, the N-type MOSFETs are of a surface-channel type, and the P-type MOSFETs are of a surface-channel or buried-channel type.  
       [0013] The storage cell SC further comprises a pair of nodes N 1  and N 2  which have a pair of storage states: the nodes N 1  and N 2  are “high” and “low” respectively, and vice versa. A “high” means a logic corresponding to a potential higher than (V DD +V ss )/2, and a “low” means a logic corresponding to a potential lower than (V DD +V SS )/2 where a ground is often selected as the potential Vss. A “high” and a “low” mean not only the logics but also potentials corresponding to the respective logics. Which of the “high” and “low” states represents a “1” as a bit of the SRAM and which represents a “0” is a matter of design choice.  
       [0014] The N-type MOSFET turns on when a “high” is applied to the gate thereof, and turns off when a “low” is applied thereto. The P-type MOSFET turns on when a “low” is applied to the gate thereof, and turns off when a “high” is applied thereto. In an “on” state, current flows between the source and the drain of the MOSFET to provide electrical conduction therebetween. In an “off” state, there is electrical disconnection between the source and the drain of the MOSFET and almost no current flows therebetween.  
       [0015] The node N 1  is the input of the inverter L 2 , and a potential corresponding to a logic complementary to the logic corresponding to the potential at the node N 1  is outputted to the node N 2 . The node N 2  is the input of the inverter L 1 , and the inverted bit of a logic complementary to the logic corresponding to the potential at the node N 2  is outputted to the node N 1 . Thus, there are a pair of storage states corresponding to complementary logics.  
       [0016] The access transistor QN 3  is connected at nodes N 1  and N 4  to the storage cell SC and the write data bit line  41 , respectively. The access transistor QN 4  is connected at nodes N 2  and N 5  to the storage cell SC and the write data complement bit line  42 , respectively. The gates of the respective access transistors QN 3  and QN 4  are connected commonly to the write word line  31 .  
       [0017] In the read circuit RK, the drains of the respective transistors QP 4  and QN 5  are connected commonly to a node N 3 . The gates of the respective transistors QP 3  and QN 6  are connected commonly to the node N 1 . The gates of the transistors QP 4  and QN 5  are connected to the read complement word line  32  and the read word line  33 , respectively. As described above, a dual port static memory cell is used as the memory cell MC.  
       [0018] For reading data from the memory cell MC, complementary logics are placed on the read word line  33  and the read complement word line  32 . The read word line  33  and the read complement word line  32  corresponding to a row including the memory cell MC to be read are driven high and low, respectively, whereas the read word lines  33  and the read complement word lines  32  corresponding to the other rows are driven low and high, respectively.  
       [0019] Thus, both of the transistors QP 4  and QN 5  of the read circuit RK in the memory cell MC to be read turn on. This causes an inverter comprised of the transistors QP 3  and QN 6  to apply a value complementary to the value at the node N 1  through the node N 3  to the read data bit line  43 . On the other hand, the transistors QP 4  and QN 5  of the read circuit RK in each of the memory cells MC which are not to be read turn off. This disconnects the read data bit line  43  from the storage cell SC in each of the memory cells MC which are not to be read.  
       [0020] For writing data into the memory cell MC, the write word line  31  corresponding to a row including the memory cell MC to be written is driven high, whereas the write word lines  31  corresponding to the other rows are driven low.  
       [0021] Thus, both of the access transistors QN 3  and QN 4  in the memory cell MC to be written turn on. This connects the nodes N 1  and N 2  of the storage cell SC through the nodes N 4  and N 5  to the write data bit line  41  and the write data complement bit line  42 , respectively. On the other hand, the access transistors QN 3  and QN 4  in each of the memory cells MC which are not to be written turn off. This disconnects the nodes N 1  and N 2  of the storage cell SC from the write data bit line  41  and the write data complement bit line  42  in each of the memory cells MC which are not to be written.  
       [0022] As described above, since the logics on the nodes N 1  and N 2  of the storage cell SC are in complementary relation, complementary logics are placed on the write data bit line  41  and the write data complement bit line  42  corresponding to a column including the memory cell MC to be written. Then, the logics placed on the write data bit line  41  and the write data complement bit line  42  are written into the nodes N 1  and N 2 , respectively.  
       [0023] After the write operation, the write word line  31  is driven low to turn off the access transistors QN 3  and QN 4 . This disconnects the storage cell SC from the write data bit line pair. Thus, the data held in the storage cell SC is not rewritten, and the storage cell SC is placed into a stand-by state.  
       [0024] In the above construction, when the write word line  31  is driven high during a write operation, the access transistors QN 3  and QN 4  in all of the memory cells MC disposed in the same row as the memory cell MC to be written turn on. Thus, in the memory cells MC which are disposed in the same row as the memory cell MC to be written but are not to be written, the nodes N 1  and N 2  are connected through the access transistors QN 3  and QN 4  to the write data bit line  41  and the write data complement bit line  42 , respectively, during the write operation.  
       [0025] On the other hand, the write data bit lines  41  and the write data complement bit lines  42  corresponding to the columns including the memory cells MC which are not to be written are normally precharged to an equal potential. This precharge potential is, for example, V DD , (V DD +V SS )/2, or V ss . Therefore, depending on the potentials at the nodes N 1  and N 2  in each of these memory cells MC, one of the write data bit line  41  and the write data complement bit line  42  is pulled to V ss  and the other is pulled to (V DD −V thn ) (assuming that the potential V DD  is applied to the write word line  31  and the threshold voltage V thn  of the transistors QN 3  and QN 4  is greater than zero). The potential application through the nodes N 1  and N 2  to such precharged write data bit line pair gives rise to unwanted electric power consumption.  
       [0026] Additionally, the bit line pair to which the potential is applied by the storage cell SC in the above-mentioned manner is subjected to another precharge operation to prepare for the next write operation. This precharge operation also consumes unwanted electric power.  
       [0027]FIG. 36 is a circuit diagram showing a configuration of a memory cell MC proposed for preventing the above-mentioned power consumption and disclosed, for example, in U.S. Pat. No. 6,005,794.  
       [0028] NMOS transistors QN 9  and QN 10  are connected in series between the node N 1  and a potential point providing the potential V ss  (also referred to hereinafter as a “potential point V ss ”), e.g., a ground. The gate of the NMOS transistor QN 9  is connected at the node N 4  to the write data bit line  41 , and the gate of the NMOS transistor QN 10  is connected to the write word line  31 . Similarly, NMOS transistors QN 11  and QN 12  are connected in series between the node N 2  and the potential point V ss . The gate of the NMOS transistor QN 11  is connected at the node N 5  to the write data complement bit line  42 , and the gate of the NMOS transistor QN 12  is connected to the write word line  31 .  
       [0029] The write word line  31  corresponding to the memory cell MC to be written (i.e., in a selected row) is driven high to turn on the transistors QN 10  and QN 12  during a write operation. Complementary logics are applied to the write data bit line  41  and the read data bit line  43  corresponding to the memory cell MC (i.e., in a selected column) to turn on one of the transistors QN 9  and QN 11 . When the write data bit line  41  and the write data complement bit line  42  are high and low respectively, a logic “low” is placed on the node N 1 . This forces the node N 2  high. Conversely, when the write data bit line  41  and the write data complement bit line  42  are low and high respectively, a logic “low” is placed on the node N 2 . This forces the node N 1  high.  
       [0030] In such a write operation, all of the unselected write data bit line pairs are driven to the potential V ss . The transistors QN 9  and QN 11  are off in the memory cells MC which are not to be written. Therefore, in the memory cells MC disposed in the row corresponding to the selected write word line  31  which is high, the nodes N 1  and N 2  are not forced to any potential from externally of the storage cell SC. In other words, this is advantageous in preventing the above-mentioned unwanted power consumption.  
       [0031] However, this circuit presents a problem in that a write operation which changes the stored content of the storage cell SC requires much time. Specifically, this circuit forces one of the nodes N 1  and N 2  low from externally of the storage cell SC, but does not have the function of forcing the other node high from externally of the storage cell SC. For example, when inverting the nodes N 1  and N 2  which are high and low respectively into their complementary states, the transistors QN 9  and QN 10  turn on to attempt to discharge the node N 1 . However, since the node N 2  is originally low and is not forced high from externally of the storage cell SC, the inverter L 1  attempts to hold the node N 1  high. The storage cell SC is designed to have a high static noise margin in order to hold data in a stable fashion. Therefore, this circuit is not capable of rapidly inverting the stored content of the storage cell SC only by discharging the node N 1 .  
       SUMMARY OF THE INVENTION  
       [0032] According to a first aspect of the present invention, a memory device comprises: (a) a plurality of word line groups each including (a-1) a write word line; (b) a plurality of bit line groups each including (b-1) a write data bit line, and (b-2) a write control line provided in corresponding relation to the write data bit line; and (c) a plurality of memory cells each provided in corresponding relation to one of the word line groups and one of the bit line groups, each of the memory cells including (c-1) a storage cell including a first storage node, and (c-2) a first switch connected between the write data bit line of the one of the bit line groups corresponding thereto and the first storage node, the first switch being conducting only when both of the write word line of the one of the word line groups corresponding thereto and the write control line are active, wherein the write control line is active when an associated one of the bit line groups which includes the write control line is selected, and is inactive when the associated one of the bit line groups is not selected.  
       [0033] Preferably, according to a second aspect of the present invention, in the memory device of the first aspect, each of the bit line groups further includes (b-3) a write data complement bit line provided in corresponding relation to the write data bit line. The storage cell each includes (c-1-1) a second storage node receiving a logic complementary to a logic on the first storage node. Each of the memory cells further includes (c-3) a second switch connected between the write data complement bit line of the one of the bit line groups corresponding thereto and the second storage node, the second switch being conducting only when both of the write word line of the one of the word line groups corresponding thereto and the write control line are active. The write data bit line and the write data complement bit line have logics complementary to each other when an associated one of the bit line groups which includes the write data bit line and the write data complement bit line is selected, and have the same logic when the associated one of the bit line groups is not selected. The write control line has the exclusive OR of the write data bit line and the write data complement bit line in the one of the bit line groups.  
       [0034] Preferably, according to a third aspect of the present invention, in the memory device of the second aspect, potentials on the write data bit line and the write data complement bit lines are non-invertingly amplified and then exclusive-ORed.  
       [0035] Preferably, according to a fourth aspect of the present invention, in the memory device of the first aspect, the first switch includes: (c-2-1) a first transistor having a control electrode connected to the write control line, and first and second current electrodes; and (c-2-2) a second transistor having a control electrode connected to the write word line, and first and second current electrodes. The first and second current electrodes of the first transistor and the first and second current electrodes of the second transistor are connected in series between the first storage node and the write data bit line.  
       [0036] Preferably, according to a fifth aspect of the present invention, in the memory device of the fourth aspect, the first switch further includes: (c-2-3) a third transistor having a control electrode receiving a logic complementary to a logic on the write control line, a first current electrode connected to the second current electrode of the first transistor, and a second current electrode connected to the first current electrode of the first transistor, the third transistor being different in conductivity type from the first transistor; and (c-2-4) a fourth transistor having a control electrode receiving a logic complementary to a logic on the write word line, a first current electrode connected to the second current electrode of the second transistor, and a second current electrode connected to the first current electrode of the second transistor, the fourth transistor being different in conductivity type from the second transistor.  
       [0037] Preferably, according to a sixth aspect of the present invention, in the memory device of the fourth or fifth aspect, the first current electrode of the first transistor and the second current electrode of the second transistor share one region with each other.  
       [0038] Preferably, according to a seventh aspect of the present invention, in the memory device of the first aspect, the first switch includes: (c-2-1) a first transistor having a control electrode, a first current electrode connected to the write data bit line, and a second current electrode connected to the first storage node; and (c-2-2) a second transistor having a control electrode connected to the write control line, a first current electrode connected to the control electrode of the first transistor, and a second current electrode connected to the write word line.  
       [0039] Preferably, according to an eighth aspect of the present invention, in the memory device of the first aspect, the first switch includes: (c-2-1) a first transistor having a control electrode connected to the write word line, a first current electrode, and a second current electrode connected to the write control line; and (c-2-2) a second transistor having a control electrode connected to the first current electrode of the first transistor, a first current electrode connected to the write data bit line, and a second current electrode connected to the first storage node.  
       [0040] According to a ninth aspect of the present invention, a memory device comprises: (a) a plurality of word line groups each including (a-1) a write word line; (b) a plurality of bit line groups each including (b-1) a write data bit line, and (b-2) a write control line provided in corresponding relation to the write data bit line; and (c) a plurality of memory cells each provided in corresponding relation to one of the word line groups and one of the bit line groups, each of the memory cells including (c-1) a storage cell including a first storage node, and (c-2) a first potential setting section for providing a logic complementary to a logic on the write data bit line of the one of the bit line groups corresponding thereto to the first storage node only when both of the write word line of the one of the word line groups corresponding thereto and the write control line are active, wherein the write control line is active when an associated one of the bit line groups which includes the write control line is selected, and is inactive when the associated one of the bit line groups is not selected.  
       [0041] Preferably, according to a tenth aspect of the present invention, in the memory device of the ninth aspect, the first potential setting section includes: (c-2-1) a first potential point for supplying a potential corresponding to a first logic; (c-2-2) a first switch for controlling electrical conduction between the first storage node and a first connection point, depending on a logic on the write control line; and (c-2-3) a second switch for controlling electrical conduction between the first connection point and the first potential point, depending on both of the logic on the write data bit line and a logic on the write word line.  
       [0042] Preferably, according to an eleventh aspect of the present invention, in the memory device of the tenth aspect, the first potential setting section further includes: (c-24) a second potential point for supplying a potential corresponding to a second logic complementary to the first logic; and (c-2-5) a third switch for controlling electrical conduction between the first connection point and the second potential point, depending on both of the logic on the write data bit line and a logic complementary to the logic on the write word line.  
       [0043] Preferably, according to a twelfth aspect of the present invention, in the memory device of the ninth aspect, the first potential setting section includes: (c-2-1) a first potential point for supplying a potential corresponding to a first logic; (c-2-2) a first switch for controlling electrical conduction between the first storage node and a first connection point, depending on a logic on the write word line; and (c-2-3) a second switch for controlling electrical conduction between the first connection point and the first potential point, depending on a logic on the write control line and the logic on the write data bit line.  
       [0044] Preferably, according to a thirteenth aspect of the present invention, in the memory device of the twelfth aspect, the first potential setting section further includes: (c2-4) a second potential point for supplying a potential corresponding to a second logic complementary to the first logic; and (c-2-5) a third switch for controlling electrical conduction between the first connection point and the second potential point, depending on both of a logic complementary to the logic on the write control line and the logic on the write data bit line.  
       [0045] Preferably, according to a fourteenth aspect of the present invention, in the memory device of the fourth or seventh aspect, the first transistor is an NMOS transistor formed on an SOI substrate; and a potential for alleviating a forward bias on the first current electrode of the first transistor and a body is applied to the write word line which is inactive.  
       [0046] According to a fifteenth aspect of the present invention, a memory device comprises: (a) a plurality of word line groups each including (a-1) a write word line; (b) a plurality of bit line groups each including (b-1) a write data bit line; and (c) a plurality of memory cells each provided in corresponding relation to one of the word line groups and one of the bit line groups, each of the memory cells including (c-1) a storage cell including a first storage node, (c-2) a switch connected between the first storage node and a first potential point supplying a first potential corresponding to a first logic, and (c-3) a control device for permitting open/close control of the switch, depending on a logic on the write data bit line of the one of the bit line groups corresponding thereto when the write word line of the one of the word line groups corresponding thereto is active.  
       [0047] Preferably, according to a sixteenth aspect of the present invention, in the memory device of the fifteenth aspect, the switch includes (c-2-1) a first transistor having a first current electrode connected to the first storage node, a second current electrode connected to the first potential point, and a control electrode. The control device includes (c-3-1) a second transistor having a first current electrode connected to the control electrode of the first transistor, a second current electrode connected to the write data bit line, and a control electrode connected to the write word line.  
       [0048] Preferably, according to a seventeenth aspect of the present invention, in the memory device of the sixteenth aspect, the control device further includes (c-3-2) a third transistor having a first current electrode connected to the second current electrode of the second transistor, a second current electrode connected to the first current electrode of the second transistor, and a control electrode receiving a potential corresponding to a logic complementary to a logic or the write word line.  
       [0049] In the memory device according to the first aspect of the present invention, both of the write word line and the write control line are active in a memory cell to be written during a write operation, to connect the first storage node through the first switch to the write data bit line. Thus, it takes short time to invert the logic to be stored at the first storage node, independently of the logic placed on the write data bit line. On the other hand, the write control line is inactive in each of the memory cells which are not to be written. Then, the first switch does not connect the first storage node to the write data bit line. This reduces unwanted power consumption in the memory cells which are not to be written.  
       [0050] In the memory device according to the second aspect of the present invention, the write data bit line and the write data complement bit line are precharged in each of the unselected bit line groups. This precharge operation normally drives the write data bit line and the write data complement bit line to the same potential. Therefore, exclusive-ORing the write data bit line and the write data complement bit line inactivates the write control line.  
       [0051] In the memory device according to the third aspect of the present invention, the exclusive-OR is correctly provided even when the potential to be applied to the write data bit line and the write data complement bit line during the precharge operation is intermediate between two potentials corresponding to complementary logics.  
       [0052] In the memory device according to the fourth, seventh or eighth aspect of the present invention, the first switch is implemented by the use of the first and second transistors.  
       [0053] The memory device according to the fifth aspect of the present invention can avoid the reduction in the potential to be applied to the first storage node by the amount of the threshold voltage of the first and second transistors below the potential to be applied to the write data bit line. This eliminates the need to provide a circuit for increasing the potential on the write word line.  
       [0054] In the memory device according to the sixth aspect of the present invention, the first switch having a smaller area is implemented.  
       [0055] In the memory device according to any one of the ninth to thirteenth aspects of the present invention, both of the write word line and the write control line are active in a memory cell to be written during a write operation. In this case, the logic complementary to the logic on the write data bit line is provided to the first storage node. On the other hand, the write control line is inactive in each of the memory cells which are not to be written. Then, the first potential setting section does not place any logic on the first storage node. This reduces the unwanted power consumption in the memory cells.  
       [0056] The memory device according to the fourteenth aspect of the present invention can suppress an effective base current flowing between the first current electrode and the body of the second transistor when the write word line is inactive, even if the second transistor is formed on the SOI substrate, to thereby eliminate so-called “half-select write disturb.” 
       [0057] In the memory device according to the fifteenth or sixteenth aspect of the present invention, when the write word line is active, the switch is open/close controlled depending on the logic on the write data bit line to control the electrical conduction/non-conduction between the first storage node and the first potential point. There is no path through which electric charges directly move between the first storage node and the write data bit line. Thus, the storage cell neither charges nor discharges the write data bit line in the memory cell to be written or in the memory cells connected to the same write word line as the memory cell to be written, thereby to avoid the unwanted power consumption. Additionally, the read operation from the memory cells connected to the same write word line as the memory cell to be written is performed rapidly.  
       [0058] The memory device according to the seventeenth aspect of the present invention can achieve on/off control of the first transistor with precision.  
       [0059] It is therefore an object of the present invention to provide a technique for reducing unwanted power consumption while rapidly performing a write operation which inverts a stored content.  
       [0060] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0061]FIG. 1 conceptually shows an SRAM according to a first preferred embodiment of the present invention;  
     [0062]FIG. 2 is a circuit diagram illustrating a single memory cell according to the first preferred embodiment of the present invention;  
     [0063]FIG. 3 is a circuit diagram illustrating a tristate inverter;  
     [0064]FIGS. 4 through 9 are circuit diagrams illustrating XOR circuits;  
     [0065]FIG. 10 is a circuit diagram of a modification of the first preferred embodiment of the present invention;  
     [0066]FIG. 11 schematically illustrates the first preferred embodiment of the present invention;  
     [0067]FIG. 12 conceptually shows an SRAM according to a second preferred embodiment of the present invention;  
     [0068]FIG. 13 is a circuit diagram showing a single memory cell according to the second preferred embodiment of the present invention;  
     [0069]FIG. 14 is a circuit diagram of a modification of the second preferred embodiment of the present invention;  
     [0070]FIG. 15 is a circuit diagram of another modification of the second preferred embodiment of the present invention;  
     [0071]FIG. 16 is a circuit diagram illustrating a single memory cell according to a third preferred embodiment of the present invention;  
     [0072]FIG. 17 is a circuit diagram of a modification of the third preferred embodiment of the present invention;  
     [0073]FIG. 18 is a circuit diagram illustrating a single memory cell according to a fourth preferred embodiment of the present invention;  
     [0074]FIG. 19 is a circuit diagram of a modification of the fourth preferred embodiment of the present invention;  
     [0075]FIG. 20 is a circuit diagram illustrating a single memory cell according to a fifth preferred embodiment of the present invention;  
     [0076]FIG. 21 is a circuit diagram of a memory cell according to a first modification of the fifth preferred embodiment of the present invention;  
     [0077]FIG. 22 is a circuit diagram of a memory cell according to a second modification of the fifth preferred embodiment of the present invention;  
     [0078]FIG. 23 is a circuit diagram of a memory cell according to a third modification of the fifth preferred embodiment of the present invention;  
     [0079]FIG. 24 is a circuit diagram of a memory cell according to a fourth modification of the fifth preferred embodiment of the present invention;  
     [0080]FIG. 25 is a circuit diagram of a memory cell according to a fifth modification of the fifth preferred embodiment of the present invention;  
     [0081]FIG. 26 is a circuit diagram of a memory cell according to a sixth modification of the fifth preferred embodiment of the present invention;  
     [0082]FIG. 27 is a circuit diagram of a plurality of memory cell s according to th e sixth modification of the fifth preferred embodiment of the present invention;  
     [0083]FIG. 28 is a cross-sectional view illustrating a background art access transistor;  
     [0084]FIG. 29 is a circuit diagram illustrating a memory cell employable in a dual port SRAM;  
     [0085]FIG. 30 conceptually shows an SRAM according to a seventh preferred embodiment of the present invention;  
     [0086]FIG. 31 is a circuit diagram illustrating a single memory cell according to the seventh preferred embodiment of the present invention;  
     [0087]FIG. 32 is a circuit diagram of a memory cell according to a modification of the seventh preferred embodiment of the present invention;  
     [0088]FIG. 33 is a circuit diagram of a memory cell according to another modification of the seventh preferred embodiment of the present invention;  
     [0089]FIG. 34 conceptually shows a background art SRAM;  
     [0090]FIGS. 35 and 36 are circuit diagrams illustrating background art memory cells; and  
     [0091]FIG. 37 is a block diagram showing connection between a dual port SRAM and a device for controlling the operation thereof. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     [0092] Preferred embodiments of the present invention will now be discussed wherein a logic “high” and a logic “low” are described as corresponding to a state in which a word line is active or selected and a state in which a word line is inactive or unselected, respectively, unless otherwise specified. The following description applies to the inverse corresponding relationship between these states if the conductivity types of transistors to be used are changed as required.  
     [0093] First Preferred Embodiment  
     [0094]FIG. 1 conceptually shows a configuration of an SRAM including a memory cell array and its peripheral components according to a first preferred embodiment of the present invention. The SPAM of FIG. 1 has a characteristic structure in that a write control line  44   j  is added to each bit line group  40   j  of the background art SRAM configuration. The bit line decoder  4  also places a potential (or logic) on the write control line  44   j . More specifically, a logic corresponding to the exclusive-OR (also referred to hereinafter as “XOR”) of the logic to be provided to the write data bit line  41   j , and the logic to be provided to the write data complement bit line  42   j  is placed on the write control line  44   j . For purposes of simplicity, it is assumed in the following description that one of the potentials V DD  and V ss  is applied to the write data bit line  41   j  and the write data complement bit line  42   j  during a precharge period.  
     [0095]FIG. 2 is a circuit diagram illustrating a configuration of a single memory cell MC shown in FIG. 1. As in the background art, the subscripts denoting the row and column locations are omitted in FIG. 2. The memory cell MC comprises a storage cell SC, a read circuit RK, and pass transistors MN 9 , MN 1 O, MN 11  and MN 12  which are NMOS transistors. There are provided a write data bit line  41 , a write data complement bit line  42 , a read data bit line  43 , a write word line  31 , a read complement word line  32 , and a read word line  33 .  
     [0096] The storage cell SC comprises a pair of cross-coupled inverters L 1  and L 2 . Nodes N 1  and N 2  serve as the outputs of the respective inverters L 1  and L 2 . The inverter L 1  includes a PMOS transistor QP 1  having a source receiving the potential V DD , a drain connected to the node N 1 , and a gate connected to the node N 2 ; and an NMOS transistor QN 1  having a source receiving the potential V ss , a drain connected to the node N 1 , and a gate connected to the node N 2 . Likewise, the inverter L 2  includes a PMOS transistor QP 2  having a source receiving the potential V DD , a drain connected to the node N 2 , and a gate connected to the node N 1 ; and an NMOS transistor QN 2  having a source receiving the potential V ss , a drain connected to the node N 2 , and a gate connected to the node N 1 .  
     [0097] The read circuit RK is a tristate inverter including: a PMOS transistor QP 3  having a source receiving the potential V DD , and a gate connected to the node N 1 ; a PMOS transistor QP 4  having a drain connected at a node N 3  to the read data bit line  43 , and a gate connected to the read complement word line  32 ; an NMOS transistor QN 6  having a source receiving the potential V ss , and a gate connected to the node N 1 ; and an NMOS transistor QN 5  having a drain connected at the node N 3  to the read data bit line  43 , and a gate connected to the read word line  33 . The drain of the transistor QP 3  and the source of the transistor QP 4 . are connected to each other, and the drain of the transistor QN 6  and the source of the transistor QN 5  are connected to each other.  
     [0098]FIG. 3 is a circuit diagram illustrating a configuration of the tristate inverter, and substantially shows the configuration of the read circuit RK. A logic A is provided commonly to the gate of one of the pair of NMOS transistors and to the gate of one of the pair of PMOS transistors. A logic B is provided to the gate of the other of the pair of NMOS transistors, and a logic {overscore (B)} (a logic complementary to the logic B and indicated with the line over B; this applies to other logics) is provided to the gate of the other of the pair of PMOS transistors. When the logic B is low, the output logic Z is not determined by the tristate inverter (in a tristate condition). When the logic B is high, the output logic Z is the inverse of the logic A.  
     [0099] Referring again to FIG. 2, the pass transistors MN 9  and MN 10  are connected in series between a node N 4  on the write data bit line  41  and the node N 1  of the storage cell SC, and function as a switch for transmitting the logic on the write data bit line  41  to the node N 1  when both of the write control line  44  and the write word line  31  are high. More specifically, one of the pair of current electrodes (the source-drain pair) of the pass transistor MN 9  is connected to the node N 1 , and one of the pair of current electrodes of the pass transistor MN 10  is connected to the node N 4 . The other of the pair of current electrodes of the pass transistor MN 9  and the other of the pair of current electrodes of the pass transistor MN 10  are connected to each other. The gate of the pass transistor MN 9  is connected at a node N 6  to the write control line  44 , and the gate of the pass transistor MN 10  is connected at the node N 4  to the write data bit line  41 .  
     [0100] Similarly, the pass transistors MN 11  and MN 12  are connected in series between a node N 5  on the write data complement bit line  42  and the node N 2  of the storage cell SC, and function as a switch for transmitting the logic on the write data complement bit line  42  to the node N 2  when both of the write control line  44  and the write word line  31  are high. More specifically, one of the pair of current electrodes of the pass transistor MN 11  is connected to the node N 2 , and one of the pair of current electrodes of the pass transistor MN 12  is connected to the node N 5 . The other of the pair of current electrodes of the pass transistor MN 11  and the other of the pair of current electrodes of the pass transistor MN 12  are connected to each other. The gate of the pass transistor MN 11  is connected at the node N 6  to the write control line  44 , and the gate of the pass transistor MN 12  is connected at the node N 4  to the write data bit line  41 .  
     [0101] The pass transistors MN 10  and MN 12  are similar to the transistors QN 10  and QN 12  shown in FIG. 36 in that the operation thereof is dependent upon the logic on the write word line  31 , but differ therefrom in that the sources thereof are not connected to the potential point V ss  but to the write data bit line  41  and the write data complement bit line  42 , respectively. The pass transistors MN 9  and MN 11  are similar to the transistors QN 9  and QN 11  shown in FIG. 36 in being connected between the pass transistor MN 10  and the node N 1  and between the transistor MN 12  and the node N 2 , respectively, but differ therefrom in that the electrical conduction thereof is dependent upon the logic on the write control line  44 .  
     [0102] A write operation into the memory cell having such a configuration is described below. A selected write word line  31  goes high to turn on the pass transistors MN 10  and MN 12 . One of the write data bit line  41  and the write data complement bit line  42  which constitute the write data bit line pair goes high, and the other goes low. In response to these transitions, the write control line  44  goes high to turn on the pass transistors MN 9  and MN 11 .  
     [0103] Thus, the node N 1  of the storage cell SC is connected at the node N 4  to the write data bit line  41  through the pass transistors MN 9  and MN 10 , and the node N 2  is connected at the node N 5  to the write data complement bit line  42  through the pass transistors MN 11  and MN 12 . The logics placed on the write data bit line  41  and the write data complement bit Line  42  are written into the nodes N 1  and N 2 , respectively. Therefore, the circuit shown in FIG. 2 requires less time to invert the data stored in the storage cell SC than the circuit shown in FIG. 36.  
     [0104] For consideration of the magnitude of potentials, it is assumed that the threshold voltage of the pass transistors MN 9  and MN 10  is a potential V thn  and the potential V DD  which is high is applied to the write word line  31  and the write data bit line  41 . Because of the substrate effect of the two pass transistors MN 9  and MN 10  between the nodes N 4  and N 1 , a potential (V DD −2V thn ) is applied to the node N 1 .  
     [0105] When the potential difference (V DD −V ss ) is not greater than 1 V, there is a likelihood that the inverters L 1  and L 2  of the storage cell SC recognize the potential (V DD  −2V thn ) as being low, rather than as being high. To prevent such a false recognition, the potential to be applied as being high to the write word line  31  may be set at, for example, (V DD +2V thn ) which is higher than the potential V DD . The potentials to be applied as being high to the write word line  31  and the write control line  44  may be set at (V DD +V thn ) to produce a similar effect.  
     [0106] The operation of each of the memory cells MC disposed in a row corresponding to the selected write word line  31  and in columns corresponding to the unselected write data bit line pairs will be described. In such a memory cell MC, both of the write data bit line  41  and the write data complement bit line  42  are precharged either high or low. In response to the precharged level, the write control line  44  is driven low. In other words, the write control line  44  corresponding to each unselected column is low. Thus, even when the write word line  31  is high to maintain the transistors MN 10  and MN 12  in an on state, the transistors MN 9  and MN 11  are off to prevent the storage cell SC from influencing the potentials on the write data bit line  41  and the write data complement bit line  42 . Therefore, the memory cell MC can reduce unwanted power consumption while rapidly performing a write operation which inverts the stored content thereof.  
     [0107]FIGS. 4 through 9 are circuit diagrams illustrating XOR circuits for exclusive-ORing the logics A and B to provide the logic Z. These XOR circuits may be used to provide the exclusive-OR of the logic on the write data bit line  41  and the logic on the write data complement bit line  42  to the write control line  44 . Although XOR circuits are shown as incorporated in the bit line decoder  4  in the configuration of FIG. 1, the XOR circuits may be provided separately from the bit line decoder  4 .  
     [0108] As an example, the operation of the XOR circuit shown in FIG. 7 is described below. When the logic A is high, an inverter comprised of a PMOS transistor TP 1  and an NMOS transistor TN 1  provides a logic “low” to a node J 1 . On the other hand, the logic A, i.e. a high, is provided to a node J 2 . A PMOS transistor TP 2  and an NMOS transistor TN 2  are connected in series between the nodes J 2  and J 1  and serve as an inverter. This inverter receives the logic B to output the logic Z which is the logic {overscore (B)} to a node J 3 . At this time, no conflict between the logic B and the logic {overscore (B)} occurs at the node J 3  since a transmission gate comprised of a PMOS transistor TP 3  and an NMOS transistor TN 3  is off.  
     [0109] When the logic A is low, the nodes J 1  and J 2  are high and low, respectively. Thus, both of the transistors TP 3  and TN 3  turn on to provide the logic B as the logic Z to the node J 3 . On the other hand, when the logic B is high, the NMOS transistor TN 2  transmits the logic “high” at the node J 1  to the node J 3 . When the logic B is low, the PMOS transistor TP 2  transmits the logic “low” at the node J 2  to the node J 3 . In either case, the logic B is provided as the logic Z to the node J 3 .  
     [0110] The circuit of FIG. 7 which performs the above-mentioned operation provides the XOR of the logics A and B. To obtain a value complementary to the exclusive-OR (XNOR or exclusive-NOR), the output from the XOR circuit may be inverted or the XOR circuit may receive the logics A and B one of which is inverted.  
     [0111]FIG. 10 is a circuit diagram showing a modification of the first preferred embodiment. The configuration of FIG. 10 is similar to that of FIG. 2 in that the transistor MN 9  the switching of which is controlled by the logic on the write control line  44  and the transistor MN 10  the switching of which is controlled by the logic on the write word line  31  are connected in series between the nodes N 1  and N 4 , but differs in that the transistors MN 9  and MN 10  are interchanged in position. Likewise, the configuration of FIG. 10 further differs from that of FIG. 2 in that the transistors MN 11  and MN 12  are interchanged in position between the nodes N 2  and N 5 . Such a configuration can, of course, provide effects similar to those of the configuration shown in FIG. 2.  
     [0112]FIG. 11 schematically illustrates an arrangement of the pass transistors MN 9 , MN 10 , MN 11  and MN 12 . The inverters L 1  and L 2  of the storage cell SC are symbolically shown for simplicity of illustration, while the arrangement of the pass transistors MN 9 , MN 10 , MN 11  and MN 12  is shown in plan as well as the write data bit line  41 , the write data complement bit line  42 , the write control line  44  and the write word line  31 . In FIG. 11, the reference characters inside round brackets correspond to the configuration shown in FIG. 10, and the reference characters to the left of the parenthesized reference characters correspond to the configuration shown in FIG. 2.  
     [0113] The arrangement of FIG. 11 will be described in conformity with the configuration shown in FIG. 2. The pass transistors MN 9  and MN 10  are formed in an active region R 1 . One of the pair of current electrodes of the pass transistor MN 9  is connected to the node N 1 , and one of the pair of current electrodes of the pass transistor MN 10  is connected to the write data bit line  41 . The other of the pair of current electrodes of the pass transistor MN 9  and the other of the pair of current electrodes of the pass transistor MN 10  share a source/drain region SD 1  with each other. Likewise, the pass transistors MN 11  and MN  12  are formed in an active region R 2 . One of the pair of current electrodes of the pass transistor MN 11  is connected to the node N 2 , and one of the pair of current electrodes of the pass transistor MN 12  is connected to the write data complement bit line  42 . The other of the pair of current electrodes of the pass transistor MN 11  and the other of the pair of current electrodes of the pass transistor MN 12  share a source/drain region SD 2  with each other.  
     [0114] A gate interconnect line G 1  serving as the gates of the pass transistors MN 9  and MN 11  and a gate interconnect line G 2  serving as the gates of the pass transistors MN 10  and MN 12  are provided over the active regions R 1  and R 2  (on the side of the viewer with respect to the plane of the figure), with a gate insulation film not shown therebetween. The write control line  44  and the write word line  31  is provided over the gate interconnect lines GI and G 2 . The write control line  44  and the write word line  31  are connected to the gate interconnect lines G 1  and G 2  through via contacts VI and V 2 , respectively.  
     [0115] As stated above, the pass transistors MN 9  and MN 10  share the source/drain region SD 1  with each other, and the pass transistor MN 11  and MN 12  share the source/drain region SD 2  with each other. This reduces the area of the pass transistors MN 9 , MN 10 , MN 11  and MN 12  when arranged.  
     [0116] A potential (V DD +V SS )/2 may be applied to the write data bit line  41   j  and the write data complement bit line  42   j  during the precharge period. In this case, a circuit for non-invertingly amplifying the potentials on the write data bit line  41   j  and the write data complement bit line  42   j  should be provided in the preceding stage of the XOR circuit. For example, when V ss =0 V and the input margin of the XOR circuit is great enough to allow the input of a potential 2V DD , the amplification factor of the non-inverting amplifier circuit should be doubled. This allows the pair of inputs to the XOR circuit to be both high even when the precharge potential is either V DD /2 or V DD . Further, when the precharge potential is V ss , the pair of inputs to the XOR circuit are both low. Therefore, this circuit configuration can enjoy the effects of the first preferred embodiment.  
     [0117] Second Preferred Embodiment  
     [0118]FIG. 12 conceptually shows a configuration of an SRAM including a memory cell array and its peripheral components according to a second preferred embodiment of the present invention. The SRAM of FIG. 12 has a characteristic structure in that a write complement control line  45   j  and a write complement word line  34   1  are added respectively to each bit line group  40   j  and each word line group  30   1  of the SRAM configuration of the first preferred embodiment.  
     [0119] The bit line decoder  4  and the word line decoder  3  place potentials (or logics) on the write complement control line  45   j  and the write complement word line  34   1 , respectively. More specifically, logics complementary to the logics on the write control line  44   j  and the write word line  31   1  are placed on the write complement control line  45   j  and the write complement word line  34   1 , respectively.  
     [0120]FIG. 13 is a circuit diagram illustrating a configuration of a single memory cell MC shown in FIG. 12. As in the background art, the subscripts denoting the row and column locations are omitted in FIG. 13. The memory cell MC of FIG. 13 comprises pass transistors MP 9 , MP 10 , MP 11  and MP 12  which are PMOS transistors in addition to the components of the memory cell MC of FIG. 2. The write complement control line  45  and the write complement word line  34  are additionally provided.  
     [0121] The pass transistors MP 9 , MP 10 , MP 10  and MP 12  are connected in parallel with the pass transistors MN 9 , MN 10 , MN 11  and MN 12 , respectively. The logics to be provided to the gates of the pass transistors MP 9 , MP 10 , MP 11  and MP 12  are complementary to the logics to be provided to the gates of the pass transistors MN 9 , MN 10 , MN 11  and MN 12 , respectively. That is, the gates of the pass transistors MP 9  and MP 11  are connected at a node N 7  to the write complement control line  45 , and the gates of the pass transistors MP 10  and MP 12  are connected to the write complement word line  34 .  
     [0122] Thus, the pass trainsistors MP 9 , MP 10 , MP 11  and MP 12  and the pass transistors MN 9 , MN 10 , MN 11  and MN 12  constitute respective transmission gates. Therefore, the potential reduction by the amount of the threshold voltage V thn  due to the substrate effect, which is mentioned with reference to FIG. 2, does not occur when the logic “high” is transmitted from the write data bit line  41  to the node N 1  (or when the logic “high” is transmitted from the write data complement bit line  42  to the node N 2 ). This is advantageous in eliminating the need to provide a booster circuit for increasing the potential to be applied to the write word line  31 .  
     [0123]FIG. 14 is a circuit diagram showing a modification of the second preferred embodiment of the present invention, and corresponds to FIG. 10 as seen in accordance with the first preferred embodiment. The configuration of FIG. 14 differs from that of FIG. 13 in that the transmission gate comprised of the pass transistors MN 9  and MP 9  and the transmission gate comprised of the pass transistors MN 10  and MP 10  are interchanged in position between the nodes N 1  and N 4 , and in that the transmission gate comprised of the pass transistors MN 11  and MP 11  and the transmission gate comprised of the pass transistors MN 12  and MP 12  are interchanged in position between the nodes N 2  and N 5 . Such a configuration can, of course, provide the effects of the second preferred embodiment.  
     [0124] The pass transistors MP 9  and MP 10 , like the pass transistors MN 9  and MN 10 , may share a source/drain region with each other to reduce the required area thereof. The same holds true for the pass transistors MP 11  and MP 12 .  
     [0125] Transmission gates may be used in place of the access transistors to avoid the potential reduction by the amount of the threshold voltage V thn  due to the substrate effect. FIG. 15 is a circuit diagram in which: the write complement word line  34  is added to the circuit of FIG. 35; the access transistor QN 3  of FIG. 35 is replaced with a transmission gate comprised of the PMOS transistor MP 10  and the NMOS transistor MN 10 ; and the access transistor QN 4  of FIG. 35 is replaced with a transmission gate comprised of the PMOS transistor MP 12  and the NMOS transistor MN 12 .  
     [0126] The electrical conduction of the transistors MN 10  and MN 12  is controlled by the logic on the write word line  31 , and the electrical conduction of the transistors MP 10  and MP 12  is controlled by the logic on the write complement word line  34 , as in the configuration of FIG. 14. This also avoids the potential reduction by the amount of the threshold voltage V thn  due to the substrate effect, to eliminate the need to increase the potential to be applied to the write word line  31 . The configuration of FIG. 15 has advantages over those of FIGS. 13 and 14 in that the reduction in the number of transmission gates by one in each branch transmitting write data accordingly shortens the time required to access the storage cell SC and reduces an area penalty and in that there is no need to provide the write control line  44  and, hence, the XOR circuit. Unlike the second preferred embodiment, however, the modification shown in FIG. 15 has a poorer function to avoid the potential conflict between the storage cell SC and the write data bit line pair in each of the memory cells MC disposed in unselected columns.  
     [0127] Third Preferred Embodiment  
     [0128]FIG. 16 is a circuit diagram illustrating a configuration of a single memory cell MC according to a third preferred embodiment of the present invention. As in the background art, the subscripts denoting the row and column locations are omitted in FIG. 16. The memory cell MC shown in FIG. 16 may be used as each of the memory cells MC 1j  shown in FIG. 1.  
     [0129] The memory cell MC comprises access transistors MN 2  and MN 4  and control transistors MN 1  and MN 3  all of which are NMOS transistors in place of the access transistors QN 3  and QN 4  of the configuration of FIG. 35.  
     [0130] The access transistor MN 2 , like the access transistor QN 3 , controls the electrical conduction between the nodes N 1  and N 4 . The access transistor MN 2  is similar to the access transistor QN 3  in having a gate connected to the write word line  31 , but there is a difference in that the control transistor MN 1  is connected between the write word line  31  and the access transistor MN 2 . Likewise, the access transistor MN 4  controls the electrical conduction between the nodes N 2  and N 5 . The access transistor MN 4  is similar to the access transistor QN 4  in having a gate connected to the write word line  31 , but there is a difference in that the control transistor MN 3  is connected between the write word line  31  and the access transistor MN 4 .  
     [0131] Since the gates of the control transistors MN 1  and MN 3  are connected through the node N 6  to the write control line  44 , the electrical conduction between the node N 1  and N 4  and the electrical conduction between the nodes N 2  and N 5  are effected only when both of the write word line  31  and the write control line  44  are high, as in the first preferred embodiment. Therefore, the memory cell MC of FIG. 16 can reduce unwanted power consumption while rapidly performing a write operation which inverts the stored content thereof, as in the first preferred embodiment.  
     [0132] The above-mentioned configuration is disadvantageous in that it is impossible to share a source/drain region between the control transistor MN 1  and the access transistor MN 2  or between the control transistor MN 3  and the access transistor MN 4 , as compared with the configuration of the first preferred embodiment.  
     [0133] However, the control transistors MN 1  and MN 3  conduct depending on the logic on the write control line  44 , thereby to transmit the logic on the write word line  31  to the gates of the access transistors MN 2  and MN 4 , respectively. Therefore, the circuit configuration of FIG. 16 may be modified in such a manner that the control transistor MN 3  is merged with the control transistor MN 1 , as shown in FIG. 17, to reduce the required area thereof.  
     [0134] Fourth Preferred Embodiment  
     [0135]FIG. 18 is a circuit diagram illustrating a configuration of a single memory cell MC according to a fourth preferred embodiment of the present invention. As in the background art, the subscripts denoting the row and column locations are omitted in FIG. 18. The memory cell MC shown in FIG. 18 may be used as each of the memory cells MC ij , shown in FIG. 1. The memory cell MC of FIG. 18 comprises control transistors MN 5  and MN 6  in place of the control transistors MN 1  and MN 3  of the memory cell MC of FIG. 16.  
     [0136] The gates of the control transistors MN 5  and MN 6  are connected commonly to the write word line  31 . The control transistor MN 5  is connected between the write data bit line  41  and the gate of the access transistor MN 2 , and the control transistor MN 6  is connected between the write data complement bit line  42  and the gate of the access transistor MN 4 . Therefore, the electrical conduction between the node N 1  and N 4  and the electrical conduction between the nodes N 2  and N 5  are effected only when both of the write word line  31  and the write control line  44  are high, as in the first preferred embodiment. Therefore, the memory cell MC of FIG. 18 can reduce unwanted power consumption while rapidly performing a write operation which inverts the stored content thereof, as in the first preferred embodiment.  
     [0137] The above-mentioned configuration is disadvantageous in that it is impossible to share a source/drain region between the control transistor MN 5  and the access transistor MN 2  or between the control transistor MN 6  and the access transistor MN 4 , as compared with the configuration of the first preferred embodiment.  
     [0138] However, the control transistors MN 5  and MN 6  conduct depending on the logic on the write word line  31 , thereby to transmit the logic on the write control line  44  to the gates of the access transistors MN 2  and MN 4 , respectively. Therefore, the circuit configuration of FIG. 18 may be modified in such a manner that the control transistor MN 6  is merged with the control transistor MN 5 , as shown in FIG. 19, to reduce the required area thereof.  
     [0139] Fifth Preferred Embodiment  
     [0140]FIG. 20 is a circuit diagram illustrating a configuration of a single memory cell MC according to a fifth preferred embodiment of the present invention. As in the background art, the subscripts denoting the row and column locations are omitted in FIG. 20. The memory cell MC shown in FIG. 20 may be used as each of the memory cells MC iJ  shown in FIG. 12, but does not require the write complement control line  45 . The memory cell MC of FIG. 20 has two major differences from that of FIG. 36.  
     [0141] A first difference is that the transistor QN 9  is not directly connected to the node N 1 , but the pass transistor MN 9  is connected between the transistor QN 9  and the node N 1 . Similarly, the transistor QN 1  is not directly connected to the node N 2 , but the pass transistor MN 11  is connected between the transistor QN 11  and the node N 2 . As in the first preferred embodiment, the gates of the pass transistors MN 9  and MN 11  are connected at the node N 6  to the write control line  44 . The point of connection between the transistors QN 9  and MN 9  is indicated as a node N 8 , and the point of connection between the transistors QN 11  and MN 11  is indicated as a node N 9 .  
     [0142] A second difference is that PMOS transistors MP 3  and MP 4  are connected in series between a potential point providing the potential V DD  (also referred to hereinafter as a “potential point V DD ”) and the node N 8 . Likewise, PMOS transistors MP 5  and MP 6  are connected in series between the potential point V DD  and the node N 9 . One of the pair of current electrodes of each of the transistors MP 4  and MP 6  receives the potential V DD , and the gate of each of the transistors MP 4  and MP 6  is connected to the write complement word line  34 . One of the pair of current electrodes of the transistor MP 3  is connected to the node N 8 , and one of the pair of current electrodes of the transistor MP 5  is connected to the node N 9 . The other of the pair of current electrodes of the transistor MP 3  and the other of the pair of current electrodes of the transistor MP 4  are connected to each other. The other of the pair of current electrodes of the transistor MP 5  and the other of the pair of current electrodes of the transistor MP 6  are connected to each other. The gates of the transistors MP 3  and MP 5  are connected to the write data bit line  41  and the write data complement bit line  42 , respectively.  
     [0143] With this arrangement, the provision of the transistors MP 3  and MP 4  capable of forcing the node N 1  high from externally of the storage cell SC and the transistors MP 5  and MP 6  capable of forcing the node N 2  high allows a rapid write operation which inverts the content stored in the memory cell MC. Additionally, the electrical conduction between the nodes N 1  and N 8  and the electrical conduction between the nodes N 2  and N 9  are effected by the pass transistors MN 9  and MN 19 , respectively, depending on the logic on the write control line  44 . This reduces the unwanted power consumption resulting from the potential conflict between the node N 1  and the write data bit line  41  and between the node N 2  and the write data complement bit line  42 .  
     [0144] Transistors MP 3 , MP 4 , QN 9  and QN 4 O and transistors MP 5 , MP 6 , QN 11  and QN 12  constitute a pair of tristate inverters having outputs at the nodes N 8  and N 9 , respectively. The operation of the memory cell MC of the fifth preferred embodiment will be described from the viewpoint of the operation of these tristate inverters.  
     [0145] These tristate inverters function as inverters only when the write word line  31  is high and, accordingly, the write complement word line  34  is low. That is, the logic complementary to the logic on the write data bit line  41  is provided to the node N 8 , and the logic complementary to the logic on the write data complement bit line  42  is provided to the node N 9 . With the write word line  31  held low and, accordingly, the write complement word line  34  held high, the potential at the node N 8  is not placed by the corresponding tristate inverter (in the tristate condition) even if the transistors MP 3  and QN 9  turn on, and the potential at the node N 9  is not placed by the corresponding tristate inverter even if the transistors MP 5  and QN 11  turn on.  
     [0146] In the word line group  30  corresponding to the row including the memory cell MC to be written or the selected word line group  30 , a high potential and a low potential are applied to the write word line  31  and the write complement word line  34  respectively, and the logics complementary to the logics on the write data bit line  41  and the write data complement bit line  42  are applied to the nodes N 8  and N 9  respectively. In the bit line group  40  corresponding to the column including the memory cell MC to be written or the selected bit line group  40 , logics complementary to each other are applied to the write data bit line  41  and the write data complement bit line  42 . Then, the logic on the write control line  44  goes high to turn on the pass transistors MN 9  and MN 11 . Therefore, the logics complementary to the logics on the write data bit line  41  and the write data complement bit line  42  are rapidly stored in the nodes N 1  and N 2  respectively, even in the case of inverting the stored content of the storage cell SC.  
     [0147] In each of the memory cells MC disposed in the row corresponding to the selected word line group  30 , the tristate inverters function as inverters. On the other hand, in each of the memory cells MC disposed in the rows corresponding to the unselected bit line groups  40 , since the write data bit line  41  and the write data complement bit line  42  are precharged to approximately equal potentials, the logic on the write control line  44  is low which places the pass transistors MN 9  and MN 11  in a nonconducting state. This provides disconnection between the node N 1  and the write data bit line  41  and between the node N 2  and the write data complement bit line  42  to reduce the unwanted power consumption resulting from the potential conflict.  
     [0148] The pass transistors MN 9  and MN 10  may be replaced with transmission gates in order to avoid the voltage reduction by the amount of the threshold voltage of the pass transistors MN 9  and MN 10  due to the substrate effect. Alternatively, the potential on the write word line  31  may be increased by the amount of the threshold voltage in order to compensate for the substrate effect of the pass transistors MN 9  and MN 10 .  
     [0149]FIG. 21 is a circuit diagram illustrating a configuration of a memory cell MC according to a first modification of the fifth preferred embodiment of the present invention. The memory cell configuration of FIG. 21 is such that the sequence of the inseries connected transistors QN 9  and QN 10  of the configuration of FIG. 20 is changed and the sequence of the in-series connected transistors QN 11  and QN 12  of the configuration of FIG. 20 is changed. The first modification can, of course, produce the effects of the fifth preferred embodiment.  
     [0150]FIG. 22 is a circuit diagram illustrating a configuration of a memory cell MC according to a second modification of the fifth preferred embodiment of the present invention. The memory cell configuration of FIG. 22 is such that the transistors MP 3 , MP 4 , MP 5  and MP 6  for providing the logic “high” to the storage cell SC are eliminated from the configuration of FIG. 21, and such that the sequence of the in-series connected pass transistor MN 9  and transistor QN 10  of the configuration of FIG. 21 is changed and the sequence of the in-series connected pass transistor MN 11  and transistor QN 12  of the configuration of FIG. 21 is changed.  
     [0151] As compared with the circuit shown in FIG. 36, the sequence of the in-series connected transistors QN 9  and QN 10  is changed between the node N 1  and the potential point V ss , and the pass transistor MN 9  the electrical conduction of which is controlled by the logic on the write control line  44  is connected between the transistors QN 9  and QN 10 . Likewise, the sequence of the in-series connected transistors QN 11  and QN 12  is changed between the node N 2  and the potential point V ss , and the pass transistor MN 11  the electrical conduction of which is controlled by the logic on the write control line  44  is connected between the transistors QN 11  and QN 12 .  
     [0152] With this arrangement, it is impossible to externally force the storage cell SC high. This is disadvantageous in being incapable of rapidly performing the write operation which inverts the content stored in the storage cell SC. However, the configuration of FIG. 22 has advantages over the configurations shown in FIGS. 20 and 21 in eliminating the need to provide the write complement word line  34  and in being usable as each of the SRAM memory cells MC shown in FIG. 1. Further, the configuration of FIG. 22 has an advantage over the configuration shown in FIG. 36 in that the write data bit line  41  and the write data complement bit line  42  in each of the unselected bit line groups  40  may be precharged either low or high.  
     [0153] Of course, there are six possible sequences of in-series connection of the transistors QN 10 , MN 9  and QN 9 , and any one of the sequences may be used to produce the above-mentioned effects. The same is true for the sequences of in-series connection of the transistors QN 12 , MN 11  and QN 11 .  
     [0154]FIG. 23 is a circuit diagram of a dual write port static memory cell according to a third modification of the fifth preferred embodiment of the present invention. The memory cell of FIG. 23 comprises two word line groups (except for the read complement word line  32  and the read word line  33 ), two bit line groups (except for the read data bit line  43 ) and two tristate inverters corresponding to the two bit line groups. A first word line group, a first bit line group and a first tristate inverter are designated by the respective reference characters of FIG. 21 with the character “a” added thereto, and a second word line group, a second bit line group and a second tristate inverter are designated by the respective reference characters of FIG. 21 with the character “b” added thereto.  
     [0155] Such a dual write port static memory cell can, of course, rapidly perform the storing operation when inverting the stored content of the storage cell SC and reduce the unwanted power consumption resulting from the potential conflict.  
     [0156]FIG. 24 is a circuit diagram showing a configuration of a memory cell MC according to a fourth modification of the fifth preferred embodiment of the present invention. The configuration of FIG. 24 differs from that of FIG. 21 in that devices between the node N 8  serving as the output of one of the pair of tristate inverters and the transistor MP 3 , between the node N 8  and the transistor QN 9  and between the node N 8  and the node N 1  are changed and in that devices between the node N 9  serving as the output of the other of the pair of tristate inverters and the transistor MP 5 , between the node N 9  and the transistor QN 11  and between the node N 9  and the node N 2  are changed.  
     [0157] The node N 8  is connected through the transistor MP 9  to the transistor MP 3 , is connected through the NMOS transistor MN 9  to the transistor QN 9 , and is connected through the NMOS transistor QN 10  to the storage node N 1 . The node N 9  is connected through the PMOS transistor MP 11  to the transistor MP 5 , is connected through the NMOS transistor MN 11  to the transistor QN 11 , and is connected through the NMOS transistor QN 12  to the storage node N 2 .  
     [0158] The fourth modification of the fifth preferred embodiment does not employ the write complement word line  34  but comprises the write complement control line  45  instead. The gates of the transistors MP 9  and MP 11  are connected at the node N 7  to the write complement control line  45 , and the gates of the transistors MN 9  and NM 11  are connected at the node N 6  to the write control line  44 . The gates of the transistors QN 10  and QN 12  are connected to the write word line  31 .  
     [0159] The write word line  31  corresponding to the selected row is activated to turn on the transistors QN 10  and QN 12 . This provides electrical conduction between the nodes N 1  and N 8  and between the nodes N 2  and N 9 . The write control line  44  and the write complement control line  45  corresponding to the selected column go high and low, respectively, to turn on the transistors MP 9 , MP 11 , MN 9  and MN 11 . Thus, to-bewritten data which are the inverses of the logics on the write data bit line  41  and the write data complement bit line  42  are provided through the nodes N 8  and N 9  to the nodes N 1  and N 2 , respectively, of the memory cell MC to be written. This operation is rapidly performed even when inverting the data to be stored in the storage cell SC.  
     [0160] In each of the memory cells MC which are disposed in the selected row but are not to be written (or disposed in unselected columns), the write control line  44  and the write complement control line  45  go low and high, respectively, to turn off the transistors MP 9 , MP 11 , MN 9  and MN 11 . The nodes N 8  and N 9  are placed in the tristate condition. Thus, the nodes N 1  and N 2  are not forced to any logics from externally of the storage cell SC, and the unwanted power consumption resulting from the potential conflict is prevented.  
     [0161]FIG. 25 is a circuit diagram showing a configuration of a memory cell MC according to a fifth modification of the fifth preferred embodiment of the present invention. The configuration of FIG. 25 differs from that of FIG. 24 in that the sequence of the in-series connected transistors MP 3  and MP 9  between the node N 8  and the potential point V DD  is changed, that the sequence of the in-series connected transistors MN 9  and QN 9  between the node N 8  and the potential point V ss  is changed, that the sequence of the in-series connected transistors MP 5  and MP 11  between the node N 9  and Athe potential point V DD  is changed, and that the sequence of the in-series connected transistors MN 11  and QN 11  between the node N 9  and the potential point V ss  is changed. Therefore, the configuration shown in FIG. 25 produces the effects of rapidly writing data and reducing the unwanted power consumption.  
     [0162]FIG. 26 is a circuit diagram showing a configuration of a memory cell MC according to a sixth modification of the fifth preferred embodiment of the present invention. The configuration of FIG. 26 differs from that of FIG. 21 in that the sequence of the in-series connected transistors MP 3  and MP 4  between the node N 8  and the potential point V DD  is changed, that the sequence of the in-series connected transistors MP 5  and NP 6  between the node N 9  and the potential point V DD  is changed, and that the transistors MP 4  and MP 6  are merged into a single transistor. Likewise, the sequence of the in-series connected transistors QN 9  and QN 10  between the node N 8  and the potential point V ss  is changed; the sequence of the in-series connected transistors QN 11  and QN 12  between the node N 9  and the potential point V ss  is changed; and the transistors QN 10  and QN 12  are merged into a single transistor. Therefore, the configuration shown in FIG. 26 can reduce the number of transistors to reduce the area required to produce the effects of the fifth preferred embodiment, as compared with the circuit shown in FIG. 21.  
     [0163] The nodes N 8  and N 9  are connected to the potential point V ss  in similar connecting relationship with the nodes N 1  and N 2  of FIG. 36. However, the electrical conduction between the nodes N 8  and N 1  and the electrical conduction between the node N 9  and N 2  are provided by the transistors MN 9  and MN 11 , respectively, only when the write control line  44  is high. This is true when the write data bit line  41  and the write data complement bit line  42  of each unselected bit line group  40  are precharged either low or high. Therefore, the configuration of FIG. 26 can produce effects similar to those of FIG. 21.  
     [0164]FIG. 27 is a circuit diagram showing an application of the configuration shown in FIG. 26 to memory cells MC i1  to MC in  in the i-th row. The plurality of memory cells MC 1j  disposed in the same row commonly use the write word line  31  and the write complement word line  34 . The transistors MP 4  (or the transistors MP 6 ) of the n respective memory cells MC i1  to MC in  may be merged into a PMOS transistor MP 400 , and the transistors QN 10  (or the transistors QN 12 ) thereof may be merged into an NMOS transistor QN 100 . Such merge firther reduces the number of transistors.  
     [0165] Sixth Preferred Embodiment  
     [0166] A sixth preferred embodiment of the present invention is similar to the first to fifth preferred embodiments in configuration shown in circuit diagram. A feature of the sixth preferred embodiment lies in that the MOSFETs constituting the memory cell MC are formed on an SOI (Semiconductor On Insulator or Silicon On Insulator) substrate.  
     [0167] First, a problem with a MOSFET constituting a background art memory cell MC and formed on the SOI substrate will be described. FIG. 28 is a cross-sectional view illustrating a construction of the access transistor QN 4  of FIG. 35 formed as a MOS transistor on the SOI substrate.  
     [0168] A semiconductor substrate  91 , a buried oxide film  92  and an SOI substrate  93  are arranged in vertically stacked relation in the order named. An insulative isolator  94  is selectively buried in the SOI substrate  93 . The SOI substrate  93  is divided into an n-type drain  93   a  connected to the node N 2 , an n-type source  93   b  connected to the node N 5 , and a P-type channel region  93   c  between the drain  93   a  and the source  93   b.  A pn junction J 11  is formed between the source  93   b  and the channel region  93   c,  and a pn junction J 12  is formed between the drain  93   a  and the channel region  93   c.  A gate electrode  98  is opposed to the channel region  93   c,  with a gate insulation film  95  therebetween, and has top and side surfaces covered with an insulation film  96 . Sidewalls  97  are opposed to the side surfaces of the gate electrode  98 , with the gate insulation film  96  therebetween. The gate electrode  98  comprises doped polysilicon  98   a,  a tungsten nitride film  98   b  and tungsten  98   c  arranged in vertically stacked relation in the order named from bottom to top. In this construction, since the insulative isolator  94  insulates the SOI substrate  93  from its surroundings, the access transistor QN 4  is normally in a so-called floating body condition unless a mechanism for fixing the potential of the channel region  93   c  is additionally provided.  
     [0169] A pair of memory cells MC xj  and MC yj  disposed in the j-th column and each having the configuration shown in FIG. 35 are assumed. Consideration will be given to so-called “half-select write disturb” when writing a “high” and a “low” into the nodes N 1  and N 2 , respectively, of the memory cell MC YJ  after a “low” and a “high” are written into the nodes N 1  and N 2 , respectively, of the memory cell MC XJ .  
     [0170] The write word line  31   x  is low after the write operation to the memory cell MC xj , and remains low during the write operation to the memory cell MC Yj . Thus, the source  93   b,  the channel region  93   c  and the drain  93   a  constitute a parasitic lateral bipolar transistor in the access transistor QN 4 , and function as the emitter, base and collector, respectively, of the bipolar transistor.  
     [0171] After the write operation to the memory cell MC Xj , the write data bit line  41   j  and the write data complement bit line  42   j  are both precharged high. Then, the access transistor QN 4  of the memory cell MC xj  does not turn on, and the source  93   b  and the drain  93   a  of the transistor QN 4  is held high. Since the P-type channel region  93   c  is floating, holes (schematically indicated by “+” in FIG. 28) are thermally accumulated in the channel region  93   c.    
     [0172] In this condition, when the write data bit line  41   j  is precharged high and the write data complement bit line  42   J  is precharged low for the write operation to the memory cell MC YJ , the pn junction J 11  of the access transistor QN 4  of the memory cell MC xj  is forward biased. Electrons are injected from the source  93   b  into the channel region  93   c  to discharge the holes accumulated in the channel region  93   c.  In this process, current I 1  flowing through the pn junction J 11  functions as an effective base current for the above-mentioned parasitic bipolar transistor. This induces spike-shaped current I 2  flowing from the drain  93   a  into the channel region  93   c.  In particular, longer time before the write operation to the memory cell MC Yj , causes more holes to be thermally accumulated, resulting in the greater current I 2 . In this case, the potential at the node N 2  is sometimes lowered from a “high” to a “low” by discharging the electric charges accumulated at the node N 2  to invert the stored content of the memory cell MC Xj .  
     [0173] The use of the circuit configuration according to the present invention, however, avoids the above-mentioned problem. For example, in the configuration shown in FIG. 2, the logic on the write data complement bit line  42  is written into the node N 2  through the transistors MN 11  and MN 12 . In general, an interconnect line between the transistors MN 11  and MN 12  is much shorter than the write data complement bit line  42 . Thus, as compared with the access transistor QN 4  of the memory cell MC having the structure of FIG. 35, the transistor MN 11  has a lower parasitic capacitance connected to one of the pair of current electrodes thereof which is closer to the write data complement bit line  42  (e.g., source), particularly if the impurity region is shared as shown in FIG. 11. As a result, the parasitic bipolar transistor does not sufficiently operate even when the transistor MN 11  is the SOI FET shown in FIG. 28. Therefore, the use of the circuit configuration according to the sixth preferred embodiment reduces the probability of occurrence of half-select write disturb.  
     [0174] It is desirable that the potential corresponding to the logic “low” on the unselected write word lines  31  is lower than the potential corresponding to the logic “low” on the write data complement bit lines  42  and, for example, ranges from about V ss   -0.3  Vb to about V ss -Vb where Vb is the built-in voltage developed by the drain  93   a  and the channel region  93   c.  Applying such a potential to the unselected write word lines  31  alleviates the forward bias at the pn junction J 11  while the accumulation of holes in the channel region  93   c  is avoided. Such potential setting on the write word lines  31  is particularly effective in the circuit configuration shown in FIG. 16 since the transistor MN 4  has the pair of current electrodes connected to the nodes N 2  and N 5  and is similar to the transistor QN 4  shown in FIG. 35 in terms of parasitic capacitance.  
     [0175] Of course, the transistor may be configured to fix the potential of the channel region  93   c  to avoid the half-select write disturb.  
     [0176] Although the dual port static memory cell is taken as an example in the first to sixth preferred embodiments, it is needless to say that these preferred embodiments are applicable to a multi port static memory cell.  
     [0177] Seventh Preferred Embodiment  
     [0178] The first to sixth preferred embodiments enable a write operation by activating not only the write word line  31  but also the write control line  44  to produce predetermined effects. However, the determination of the logic on the write control line  44  requires the determination of the potentials on the write data bit line  41  and the write data complement bit line  42  by precharge, independently of whether the potentials are V ss , V DD  or (V DD +V ss )/2. In other words, if the write data bit line  41  and the write data complement bit line  42  are allowed to be floating, there is apprehension that the potential on the write control line  44  is not determined. Further, when the write data bit line  41  and the write data complement bit line  42  are floating, there is a likelihood that power consumption results from the charging and discharging of the write data bit line  41  and the write data complement bit line  42  by the storage cell SC in each of the memory cells disposed in the same row as, the memory cell to be written but in different columns therefrom.  
     [0179] In particular, in some multi port SRAMs, e.g. dual port SRAMs, having a plurality of read and write paths for each cell and capable of independently and asynchronously reading and writing binary information, the storage cell SC can drive not only the write data bit line  41  and the write data complement bit line  42  but also the read data bit line  43  in parallel.  
     [0180]FIG. 37 is a block diagram showing a dual port SRAM  80  having first and second ports one of which serves as a write port and the other as a read port, and connections with devices for controlling the operation of the dual port SRAM  80 . A first microprocessor  81  performs read and write operations using the first port of the dual port SRAM  80  through a first read/write control circuit  82 . A second microprocessor  84  performs read and write operations using the second port of the dual port SRAM  80  through a second read/write control circuit  83 .  
     [0181]FIG. 29 is a circuit diagram illustrating a configuration of a memory cell MC usable in the dual port SRAM  80 . The memory cell MC of FIG. 29 comprises access transistors QN 13  and QN 14  which are NMOS transistors in place of the read circuit RK of the configuration shown in FIG. 35. The access transistor QN 13  is connected between the node N 1  and the read data bit line  43 , and has a gate connected to the read word line  33 . The access transistor QN 14  is connected between the node N 2  and a read data complement bit line  46 , and has a gate connected to the read word line  33 .  
     [0182] The configuration shown in FIG. 29 has an advantage over that of FIG. 35 in that the number of transistors is reduced by two per memory cell MC. However, at the nodes N 3  and N 10 , the storage cell SC charges and discharges the read data bit line  43  and the read data complement bit line  46  having greater electrostatic capacitances than do the gates of the transistors QP 3  and QN 6  of the read circuit RK, respectively, when the transistors QN 13  and QN 14  turn on. This produces a time period during which both the write word line  31   i  and the read word line  33   i  are high, when the write operation of the first read/write control circuit  82  and the read operation of the second read/write control circuit  83  are performed in parallel upon memory cells MC 1x  and MC 1y  (x#y) both disposed in the i-th row. During this time period, the storage cell SC of the memory cell MC 1y  drives not only the read data bit line  43  and the read data complement bit line  46  but also the write data bit line  41  and the write data complement bit line  42 , which might slow the read operation.  
     [0183]FIG. 30 conceptually shows an SRAM including a memory cell array and its peripheral components according to a seventh preferred embodiment of the present invention. The SRAM shown in FIG. 30 is constructed such that the write control lines  44  of the configuration shown in FIG. 1 are replaced with the read data complement bit lines  46 , and the read complement word lines  32  of the configuration shown in FIG. 1 are eliminated.  
     [0184]FIG. 31 is a circuit diagram illustrating a configuration of a single memory cell MC shown in FIG. 30. As in the background art, the subscripts denoting the row and column locations are omitted in FIG. 31. The memory cell MC shown in FIG. 31 comprises NMOS transistors QN 15 , QN 16 , QN 17  and QN 18  in place of the transistors QN 3  and QN 4  of the memory cell MC of FIG. 29. Of course, the read complement word line  32  may also be used, and the read circuit RK may be used in place of the transistors QN 13  and QN 14  in the memory cell MC. However, the seventh preferred embodiment is particularly effective when the memory cell MC includes a read mechanism having the possibility that the nodes N 1  and N 2  charge and discharge the read data bit line  43  and the read data complement bit line  46 , rather than the transistor gates, as above described.  
     [0185] The potential V ss  is supplied to one of the pair of current electrodes, e.g. the source, of the transistor QN 17 , and the node N 2  is connected to the other of the pair of current electrodes, e.g. the drain, thereof. The potential V ss  is supplied to one of the pair of current electrodes, e.g. the source, of the transistor QN 18 , and the node N 1  is connected to the other of the pair of current electrodes, e.g. the drain, thereof.  
     [0186] The write data bit line  41  is connected at the node N 4  to one of the pair of current electrodes, e.g. the source, of the transistor QN 15 , and the gate of the transistor QN 17  is connected to the other of the pair of current electrodes, e.g. the drain, thereof. The write data complement bit line  42  is connected to one of the pair of current electrodes, e.g. the source, of the transistor QN 16 , and the gate of the transistor QN 18  is connected to the other of the pair of current electrodes, e.g. the drain, thereof. The gates of the transistors QN 15  and QN 16  are connected to the write word line  31 .  
     [0187] With this arrangement, a write operation is performed to be described below. The write data bit line  41  and the write data complement bit line  42  are precharged to potentials corresponding to logics to be provided to the nodes N 1  and N 2 , respectively. For example, the potentials V DD  and V ss  corresponding to a “high” and a “low” are placed on the write data bit line  41  and the write data complement bit line  42 , respectively. Thereafter, the write word line  31  is activated to turn on the transistors QN 15  and QN 16 , thereby applying potentials (V DD −V thn ) and V ss  to the gates of the transistors QN 17  and QN 18 , respectively (where the threshold voltage V thn  of the transistor QN 15  is greater than zero). This places the transistors QN 17  and QN 18  into the on- and off-states, respectively. Since the transistor QN 17  is on, the potential V ss  is transmitted to the node N 2 . Then, the inverter L 1  functions to store the logic “high” in the node N 1 .  
     [0188] Thereafter, the potential V ss  is placed on both of the write data bit line  41  and the write data complement bit line  42  to drive the gates of the transistors QN 17  and QN 18  low, thereby turning off the transistors QN 17  and QN 18 . Subsequently, the write word line  31  is inactivated to go low. This turns off the transistors QN 15  and QN 16  to place the gates of the transistors QN 17  and QN 18  into a floating condition.  
     [0189] In a read operation, the read word line  33  is activated to turn on the transistors QN 13  and QN 14 . Thus, the logics stored in the nodes N 1  and N 2  are transmitted at the nodes N 3  and N 10  to the read data bit line  43  and the read data complement bit line  46 , respectively. To increase the rate of reading, it is desirable to precharge the read word line  33  prior to the activation thereof.  
     [0190] With this arrangement, electrical charges are not supplied from the write data bit line  41  and the write data complement bit line  42  to the storage cell SC but the potential V ss  is applied to one of the nodes N 1  and N 2  during the write operation. In other words, there is no path through which the electrical charges directly move between the bit lines  41 ,  42  and the nodes N 1 , N 2 . Thus, when the write word line  31  is active and the write data bit line  41  and the write data complement bit line  42  are floating, these lines are neither charged nor discharged by the storage cell SC to avoid the unwanted power consumption. Therefore, the read operation is not slowed if there is a time period during which both the write word line  31  and the read word line  33  are high.  
     [0191] At the end of the above-mentioned write operation, the procedure is discussed such that turning off the transistors QN 17  and QN 18  is followed by turning off the transistors QN 15  and QN 16 . The procedure may be reversed so that turning off the transistors QN 15  and QN 16  is followed by turning off the transistors QN 17  and QN 18 . This produces the effect of backing up the information in the storage cell SC since the gates of the transistors QN 17  and QN 18  are placed into the floating condition while one of the transistors QN 17  and QN 18  remains on. There is a possible soft error such that the content stored in the storage cell SC is inverted, for example, resulting from irradiation with a cosmic ray, such as a neutron beam. Backing up the information in the storage cell SC increases the critical amount of charge required to cause a soft error, that is, makes a soft error difficult to occur.  
     [0192]FIG. 32 is a circuit diagram showing a modification of the seventh preferred embodiment of the present invention. The memory cell MC of FIG. 32 comprises the write complement word line  34  substituted for the write word line  31 , and PMOS transistors QP 15  and QP 16  substituted for the transistors QN 15  and QN 16 .  
     [0193] The configuration shown in FIG. 32 produces effects similar in logic propagation to those of the configuration shown in FIG. 31. However, the configuration shown in FIG. 32 can avoid the reduction in potential by the amount of the threshold voltage V thn  (&gt; 0 ) when placing a “high” on the gates of the transistors QN 17  and QN 18 .  
     [0194] On the other hand, when placing a “low” on the gates of the transistors QN 17  and QN 18 , the potentials thereof increase to V ss −V thp  where V thp  is the threshold voltage of the PMOS transistors QP 15  and QP 16  and is less than zero. Therefore, the configuration of FIG. 31 is advantageous over that of FIG. 32 in ensuring the turning off of the transistors QN 17  and QN 18  to suppress the leakage current from the nodes N 1  and N 2  to the potential point V ss .  
     [0195]FIG. 33 is a circuit diagram showing another modification of the seventh preferred embodiment of the present invention. Both of the write word line  31  and the write complement word line  34  are used. A transmission gate comprised of the transistors QP 15  and QN 15  connected in parallel is connected between the node N 4  and the gate of the transistor QN 17 . A transmission gate comprised of the transistors QP 16  and QN 16  connected in parallel is connected between the node N 5  and the gate of the ax transistor QN 18 . The gates of the PMOS transistors QP 15  and QP 16  are connected to the write complement word line  34 , and the gates of the NMOS transistors QN 15  and QN 16  are connected to the write word line  31 .  
     [0196] Such a construction allows the on/off control of the transistors QN 17  and QN 18  with precision.  
     [0197] While the invention has been described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is understood that numerous other modifications and variations can be devised without departing from the scope of the invention.