Patent Publication Number: US-7724592-B2

Title: Internal data comparison for memory testing

Description:
RELATED APPLICATION 
   This Application is a Divisional of U.S. application Ser. No. 11/126,747, titled “INTERNAL DATA COMPARISON FOR MEMORY TESTING,” filed May 11, 2005 now U.S. Pat. No. 7,480,195 (Allowed) which is commonly assigned and incorporated herein by reference. 

   TECHNICAL FIELD OF THE INVENTION 
   The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to test methods for semiconductor memory devices as well as circuits and apparatus for implementing such methods. 
   BACKGROUND OF THE INVENTION 
   Electronic information handling or computer systems, whether large machines, microcomputers or small and simple digital processing devices, require memory for storing data and program instructions. Various memory systems have been developed over the years to address the evolving needs of information handling systems. One such memory system includes semiconductor memory devices. 
   Semiconductor memory devices are rapidly-accessible memory devices. In a semiconductor memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Semiconductor memory devices typically store information in a large array of cells. 
   Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. One important form of semiconductor memory device includes a non-volatile memory made up of floating-gate memory cells called flash memory. Flash memory is often used where regular access to the data stored in the memory device is desired, but where such data is seldom changed. Computer applications use flash memory to store BIOS firmware. Peripheral devices such as printers store fonts and forms on flash memory. Digital cellular and wireless applications consume large quantities of flash memory and are continually pushing for lower voltages and higher densities. Portable applications such as digital cameras, audio recorders, personal digital assistants (PDAs) and test equipment also use flash memory as a medium to store data. 
   Another important form of semiconductor memory device includes a volatile memory called dynamic random access memory (DRAM). DRAM is often used where rapid access to the memory array is desired for both data input and data output. DRAM has faster access times than flash memory, but requires periodic refresh to avoid losing its data values. Computer applications typically use DRAM to store program instructions and other temporary data. 
   Prior to shipping, a manufacturer may test its semiconductor memory devices as part of a quality program to improve end-use reliability. It is generally common to test the devices for defective columns or rows of memory cells, and to replace those defective elements with redundant elements. By writing a known pattern to a memory array, reading data values from the array and comparing those data values to the expected data values, defective elements can be identified. Such testing is generally performed by specialized external tester devices during the fabrication process and often prior to packaging the devices. Post-packaging failures are typically impracticable to detect as the specialized tester devices are generally unavailable. 
   For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative methods of testing memory devices, circuits for implementing such test methods, and memory devices making use of such circuits and test methods. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a simplified block diagram of a memory system, according to an embodiment of the invention. 
       FIG. 2  is a schematic of a NAND memory array, according to another embodiment of the invention. 
       FIG. 3  is a schematic of a data path proceeding from the memory array through the column access circuitry to the I/O circuitry in accordance with an embodiment the invention. 
       FIG. 4  is a schematic of a data path proceeding from the memory array through the column access circuitry to the I/O circuitry in accordance with a further embodiment the invention. 
       FIG. 5  is a schematic of a portion of a data path in accordance with a still further embodiment the invention showing one example of the relationship between decoding circuitry and a compare circuit. 
       FIG. 6  is a schematic of compare circuits in accordance with one embodiment of the invention. 
       FIG. 7  is a schematic of a portion of the data path showing the relationship between a final compare circuit and an output latch in accordance with one embodiment of the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   In the following detailed description of the present embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that process, electrical or mechanical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof. 
   Although the testing methods and data comparison circuits described herein are applicable to a variety of memory device types, including various forms of volatile and non-volatile memory devices known in the art, such methods and comparison circuits will be described in relation to a flash memory device. Those skilled in the art will readily recognize their applicability to other memory devices. 
     FIG. 1  is a simplified block diagram of a memory system  100 , according to an embodiment of the invention. Memory system  100  includes an integrated circuit flash memory device  102 , e.g., a NAND memory device, that includes an array of memory cells  104 , an address decoder  106 , row access circuitry  108 , column access circuitry  110 , control circuitry  112 , Input/Output (I/O) circuitry  114 , and an address buffer  116 . Memory system  100  includes an external microprocessor  120 , or memory controller, electrically connected to memory device  102  for memory accessing as part of an electronic system. The memory device  102  receives control signals from the processor  120  over a control link  122 . The memory cells are used to store data that are accessed via a data (DQ) link  124 . Address signals are received via an address link  126  that are decoded at address decoder  106  to access the memory array  104 . Address buffer circuit  116  latches the address signals. The memory cells are accessed in response to the control signals and the address signals. The control circuitry  112  is adapted to perform test methods in accordance with embodiments of the invention. Furthermore, column access circuitry  110  includes data comparison logic in accordance with embodiments of the invention. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device of  FIG. 1  has been simplified to help focus on the invention. 
     FIG. 2  is a schematic of a NAND memory array  200  as a portion of memory array  104  in accordance with another embodiment of the invention. As shown in  FIG. 2 , the memory array  200  includes word lines  202   1  to  202   N  and intersecting bit lines  204   1  to  204   M . For ease of addressing in the digital environment, the number of word lines  202  and the number of bit lines  204  are each some power of two, e.g., 256 word lines  202  by 4,096 bit lines  204 . 
   Memory array  200  includes NAND strings  206   1  to  206   M . Each NAND string includes floating-gate transistors  208   1  to  208   N , each located at an intersection of a word line  202  and a bit line  204 . The floating-gate transistors  208  represent non-volatile memory cells for storage of data. The floating-gate transistors  208  of each NAND string  206  are connected in series source to drain between a source select line  214  and a drain select line  215 . Source select line  214  includes a source select gate  210 , e.g., a field-effect transistor (FET), at each intersection between a NAND string  206  and source select line  214 , and drain select line  215  includes a drain select gate  212 , e.g., a field-effect transistor (FET), at each intersection between a NAND string  206  and drain select line  215 . In this way, the floating-gate transistors  208  of each NAND string  206  are connected between a source select gate  210  and a drain select gate  212 . 
   A source of each source select gate  210  is connected to a common source line  216 . The drain of each source select gate  210  is connected to the source of the first floating-gate transistor  208  of the corresponding NAND string  206 . For example, the drain of source select gate  210   1  is connected to the source of floating-gate transistor  208   1  of the corresponding NAND string  206   1 . Each source select gate  210  includes a control gate  220 . 
   The drain of each drain select gate  212  is connected to the bit line  204  for the corresponding NAND string at a drain contact  228 . For example, the drain of drain select gate  212   1  is connected to the bit line  204   1  for the corresponding NAND string  206   1  at drain contact  228   1 . The source of each drain select gate  212  is connected to the drain of the last floating-gate transistor  208   N  of the corresponding NAND string  206 . For example, the source of drain select gate  212   1  is connected to the drain of floating-gate transistor  208   N  of the corresponding NAND string  206   1 . 
   Typical construction of floating-gate transistors  208  includes a source  230  and a drain  232 , a floating gate  234 , and a control gate  236 , as shown in  FIG. 2 . Floating-gate transistors  208  have their control gates  236  coupled to a word line  202 . A column of memory array  200  includes a NAND string  206  and the source and drain select gates connected thereto. A row of the floating-gate transistors  208  are those transistors commonly coupled to a given word line  202 . 
     FIG. 3  is a schematic of a data path proceeding from the memory array through the column access circuitry to the I/O circuitry in accordance with an embodiment the invention. Because memory devices typically contain millions, if not billions, of memory cells, it is common to have multiple levels of multiplexing in coupling a memory cell to a DQ line of the memory device. 
   As shown in  FIG. 3 , a target memory cell  208  as part of a memory array  200  selectively coupled to a first multiplexer  302  through its associated bit line  204 , along with bit lines  204  from a number of other memory cells (not shown in  FIG. 3 ). As one example, for a memory array  200  of the type depicted in  FIG. 2 , a target memory cell  208  might be selectively coupled to the first multiplexer  302  upon activation of its word line  202  and an associated drain select gate (not shown in  FIG. 3 ). The first multiplexer  302  may be configured to select one of every two or more bit lines in response to an address decoder (not shown in  FIG. 3 ) and couple it to an output  304 . It will be apparent that other memory array configurations, such as NOR configurations, are also suitable for use with the invention. 
   The output  304  is provided to sensing and latching circuitry  306 . The sensing and latching circuitry  306  senses the data value of the target memory cell  208  and provides a signal indicative of its data value on its output  308 . The output  308  of sensing and latching circuitry  306  is then provided to column decode circuitry  310  along with other outputs  308  from other sensing devices (not shown in  FIG. 3 ). The column decode circuitry  310  is configured to select one of a plurality of outputs  308  in response to an address decoder (not shown in  FIG. 3 ) and couple it to an output latch  312  to place the data signal on the node  314 , such as a DQ line, of the memory device. Note that the data path is generally bidirectional, and the output latch  312  generally also receives data values from the node  314  during a write operation to the memory device. Often, the data path includes two data signal legs, i.e., for carrying complementary logic levels. The column decode circuitry  310  includes comparison circuitry in accordance with an embodiment of the invention. 
     FIG. 4  is a schematic of a data path proceeding from the memory array through the column access circuitry to the I/O circuitry in accordance with a further embodiment the invention. A sensing device  405  senses a data value from a target memory cell (not shown in  FIG. 4 ). The sensing device  405  then passes the data value to one or more latches, such as a data latch and/or cache latch  407 . Two latches are typically used in a flash memory device. In such configurations, the cache latch can hold data for passing to the output latch while the sensing device senses a data value from a subsequent memory cell for latching in a data latch. However, the various embodiments are not dependent upon a specific number of latches. 
   As noted previously, multiple levels of multiplexing may be used to determine whether a sensed data value is coupled to the output latch  413  in normal operation. For the embodiment depicted in  FIG. 4 , three levels of multiplexing, or decoding, are involved. These levels of decoding include a first level of decoding, such as provided by Y decoder  408 , a second level of decoding, such as Z decoder  409 , and a third level of decoding, such as R decoder  410 , provide levels of selection, or predecoding. Although the first level of decoding for this embodiment is shown to occur between the sensing devices and the output latches  413 , the first level of decoding for comparison of data could occur prior to the sensing devices, such as the multiplexer  302  of  FIG. 3 . The decoders  408 ,  409  and  410  are essentially switches that selectively couple or isolate the data path from the output latch  413  in response to control signals, and may be referred to herein generally as switches. The data path further includes a switch  411 , whose use will be described later. Output latch  413  is coupled to an I/O node  314  of the memory device. 
   In practice, a first level of decoding downstream from the sensing devices selects a first subset of columns for coupling to the output latches  413 . Additional levels of decoding select further subsets of the first subset of sensed data values for coupling to the output latches  413 . As an example, in normal operation, a first decoder might be responsive to 4 bits of the column address and select 1 of every 16 columns for sensing. A second decoder might be responsive to 3 bits of the column address and select 1 of every 8 data values for coupling to the output latch  413 . And a third decoder might be responsive to 3 bits of the column address and select 1 of every 8 data values selected by the second decoder for coupling. 
   Switches  409 ,  410  and  411  are each associated with a compare circuit  419 ,  420  and  421 , respectively. In each data path, there is a compare circuit for each level of decoding, with a compare circuit for a given level of decoding placed between its respective decoder and the output latches. The compare circuits  419 ,  420  and  421  each have a first input on one side of its associated switch and a second input on the other side of its associated switch. The compare circuits  419 ,  420  and  421  generate an output signal on their outputs  450 ,  455  and  460 , respectively, indicative of whether their first and second inputs are receiving the same data value. As an example, compare circuits  419 ,  420  and  421  could include logic, such as XOR or XNOR, that output a first logic level if each input is the same and a second logic level if the inputs have complementary logic levels. 
     FIG. 5  is a schematic of a portion of a data path in accordance with a still further embodiment the invention showing one example of the relationship between decoding circuitry and a compare circuit. In  FIG. 5 , a cache latch  507  and an output latch  513  are on opposing sides of a switch, e.g., n-type field effect transistor (nFET)  510 . The nFET  510  may be part of a decode circuit for selectively coupling the cache latch  507  to the output latch  513  in response to a control signal at node  535 . Compare circuit  520  has a first input coupled to a first source/drain region of the nFET  510  and a second input coupled to a second source/drain region of the nFET  510 . Compare circuit  520  is further shown to receive an enable signal from node  570 ; during normal operation, there is no need for the compare circuit  520 . By loading a data value in the cache latch  507  and an expected data value in the output latch  513 , while the cache latch  507  and output latch  513  are isolated from each other, e.g., by deactivating the nFET  510 , compare circuit  520  may compare their respective values, if enabled, and output a signal indicative of a match or mismatch at node  555 . Note, however, that compare circuit  520  will not compare a data value selected by nFET  510 , but a data value selected by a higher level of decoding. For example, if nFET  510  is a part of the Z decoder  409  of  FIG. 4 , compare circuit  520  would compare a data value selected by the Y decoder  408  of  FIG. 4 . 
   To locate a defective column of a memory device, a series of data comparisons are made within the memory device. This discussion will refer back to  FIG. 4 . A known pattern is first written to the memory array. The input pattern is preferably a repeating pattern, with each word of the input page having the same pattern. For example, for a page containing two 8-bit words, the pattern may be all zeros “0000000000000000,” all ones “1111111111111111”, checkerboard “0101010101010101” or reverse checkerboard “1010101010101010.” In general terms, in a repeating pattern for a page having two or more words, every bit of a first word has the same data value as its corresponding bit of each remaining word such that each word has the same data pattern. Stated alternatively, for a page having M words of N bits each, bit n =bit mN+n  for each value of m and n, where m is some integer value from 0 to M−1 and n is some integer value from 0 to N−1. 
   A read operation is then performed on the memory device, such that sensing device  405  senses the data value of a target memory cell and loads the sensed data value into the data/cache latch  407 . In read operations, many memory cells are generally read in parallel, such that multiple data/cache latches  407  will hold data values concurrently, each representative of a different memory cell. As an example, if an address value of the multiplexer  302  of  FIG. 3  selects  512  columns for sensing, data will be latched for each of the columns. 
   Contemporaneously, the expected data values are loaded into the output latches  413 . The data/cache latches  407  should be isolated from the output latches  413  such that they each independently hold their respective data values. Loading each output latch  413  with its expected data value is made easier by utilizing a repeating pattern in the array. 
   Note that loading the same data value in the output latch  413  as is contained in the data/cache latches  407  may result in a complementary value appearing on the data path. For example, if a memory cell contains a data value having a first logic level, such as a logic high or 1, an output of the data/cache latch  407  may be the first logic level. However, if a data value having the first logic level is loaded into the output latch  413  for comparing to the sensed data value, that output of the output latch  413  may be a second logic level, such as a logic low or 0. Thus, the comparison logic may need to compensate to provide an indication of a mismatch only if the logic levels of the data values differ and not merely if the logic levels on the data path differ. 
   After loading the sensed and expected data values into latches at both ends of the data path, a comparison of the sensed and expected data values is made at a first level of decoding using a first compare circuit. To perform the comparison at the first level of decoding, such as provided by Y decoder  408 , the inputs of the first compare circuit, e.g., compare circuit  419 , must be isolated from each other. In the embodiment depicted in  FIG. 4 , this can be accomplished by deactivating the switches of the Z decoder  409 . Remaining switches in the path to the output latch  413 , e.g., switches of R decoder  410  and switches  411 , would be activated to allow coupling of the cache latch  407  to the Z decoder  409  and to allow coupling of the output latch  413  to the Z decoder  409 . In this manner, compare circuit  419  receives the sensed data value at a first input and the expected data value at a second input. The compare circuit  419  then provides a signal at its output  450  having a first logic level if both the sensed data value and the expected data value are the same and having a second logic level if the sensed data value and the expected data value have complementary logic levels. This process can be repeated for each address value of the Y decoder, e.g., 16 cycles if the Y decoder is responsive to 4 bits of the column address. If no mismatch is indicated, each of the columns is deemed to be good. 
   If the compare circuit  419  indicates a mismatch between the sensed and expected data values, at least one column selected by the Y decoder  408  is deemed to be defective and the address value of the Y decoder  408  is stored for use in redundancy selection. Upon detecting a defective column at the first level of decoding, further comparisons are made at higher levels of decoding. 
   To perform the comparison at a second level of decoding, such as provided by Z decoder  409 , the inputs of the second compare circuit, e.g., compare circuit  420 , must be isolated from each other. In the embodiment depicted in  FIG. 4 , this can be accomplished by deactivating the switches of the R decoder  410 . Remaining switches in the path to the output latch  413 , e.g., switches  411 , would be activated to allow coupling of the output latch  413  to the R decoder  410  and to allow coupling of the cache latch  407  to the R decoder  410  if the Z decoder  409  is set to allow coupling, i.e., its address value matches its respective portion of the column address. 
   In this manner, for selected columns, compare circuit  420  receives the sensed data value at a first input and the expected data value at a second input. The compare circuit  420  then provides a signal at its output  455  having a first logic level if both the sensed data value and the expected data value are the same and having a second logic level if the sensed data value and the expected data value have complementary logic levels. Note that if the column is not selected by higher levels of decoding, one input of the compare circuit  420  could be floating. For one embodiment, the compare circuits  420  do not indicate a mismatch if one input is floating, i.e., they provide their first logic level. For a further embodiment, they present a high impedance if one input is floating. The compare process can be repeated for each address value of the Z decoder, e.g., 8 cycles if the Z decoder is responsive to 3 bits of the column address. 
   If the compare circuit  420  indicates a mismatch between the sensed and expected data values, at least one column selected by the Z decoder  409  is deemed to be defective and the address value of the Z decoder  409  is stored for use in redundancy selection. Upon detecting a defective column at the second level of decoding, further comparisons may be made at higher levels of decoding. Note that if the second level of decoding is capable of identifying an individual column, no further comparisons would be necessary. 
   To perform the comparison at a third level of decoding, such as provided by R decoder  410 , the inputs of the third compare circuit, e.g., compare circuit  421 , must be isolated from each other. In the embodiment depicted in  FIG. 4 , this can be accomplished by deactivating the switches  411 . Remaining switches in the path to the output latch  413 , if any, would be activated to allow coupling of the output latch  413  to the switch  411  and to allow coupling of the cache latch  407  to the switch  411  if the Z decoder  409  and R decoder  410  are set to allow coupling, i.e., their address values match their respective portions of the column address. In this manner, for selected columns, compare circuit  421  receives the sensed data value at a first input and the expected data value at a second input. The compare circuit  421  then provides a signal at its output  460  having a first logic level if both the sensed data value and the expected data value are the same and having a second logic level if the sensed data value and the expected data value have complementary logic levels. Note that if the column is not selected by higher levels of decoding, one input of the compare circuit  421  could be floating. For one embodiment, the compare circuits  421  do not indicate a mismatch if one input is floating, i.e., they provide the first logic level. For a further embodiment, they present a high impedance if one input is floating. This process can be repeated for each address value of the R decoder, e.g., 8 cycles if the R decoder is responsive to 3 bits of the column address. 
   If the compare circuit  421  indicates a mismatch between the sensed and expected data values, the column corresponding to that column address, i.e., the address represented by the address values of the Y decoder  408 , Z decoder  409  and R decoder  410 , is deemed to be defective and the address value of the R decoder  410  is further stored for use in redundancy selection. With the address values for each level of decoding identified in relation to the defective column, the stored address may be used by redundancy selection circuitry, which is generally part of the control circuitry of the memory device, to apply a repair solution to the defective columns. Redundancy selection is well understood in the art and need not be detailed herein. However, in general, known defective addresses are stored in a register. When a target address is received by the memory device, it is compared to the known defective addresses. If a match occurs, the access request for the defective portion of the memory device is routed to a redundant portion of the memory device in a manner that is transparent to the external device. In this manner, certain levels of defects can be tolerated, provided there are sufficient redundant elements to replace the defective elements. 
     FIG. 6  is a schematic of compare circuits  620   a  and  620   b  in accordance with one embodiment of the invention. The compare circuits  620   a  or  620   b  could be used, for example, as compare circuits  419 ,  420 ,  421  and  520  in cases where the data path has complementary legs. Other forms of combinatorial logic capable of generating a signal indicative of a mismatch may also be used with various embodiments of the invention. 
   Often, columns of a memory array are paired, either physically or logically, such that when one is selected for sensing, the other is not.  FIG. 6  not only provides detail of one implementation of the compare circuitry, but also demonstrates how the data path of one of the paired columns can be used to selectively disable the compare circuitry of the other column. Disabling is useful if the other column is a known bad column prior to testing as it may be desirable to avoid comparing data for a known bad column. 
   The compare circuit  620   a  is coupled to a first data path including a first leg  672   a  for a data value and a second leg  674   a  for the complement of the data value. The compare circuit  620   a  includes a first nFET  680   a  having a drain coupled to the output node  655  and a gate coupled to a first source/drain region of nFET  610   1  in path  672   a , and a second nFET  682   a  having a drain coupled to the output node  655  and a gate coupled to a first source/drain region of nFET  610   2  in path  674   a . The compare circuit  620   a  further includes a third nFET  684   a  having a drain coupled to a source of nFET  680   a  and a gate coupled to a second source/drain region of nFET  610   1  in path  672   a , and a fourth nFET  686   a  having a drain coupled to a source of nFET  682   a  and a gate coupled to a second source/drain region of nFET  610   2  in path  674   a.    
   The compare circuit  620   a  further includes an optional fifth nFET  688   a  having a drain coupled to the sources of nFETs  684   a  and  686   a  and a gate coupled to receive a control signal at node  670 , and an optional sixth nFET  690   a  having a drain coupled to the sources of nFETs  684   a  and  686   a  and a gate coupled to the path  674   b . In this configuration, the nFET  690   a  can act as a local enable device, with nFET  688   a  permitting an override of any deactivation of nFET  690   a . To locally disable the compare circuit  620   a , the data/cache latch associated with path  674   b  could be loaded with a data value to deactivate nFET  690   a . Thus, for example, if path  674   a  was associated with a known bad column, the data/cache latch associated with path  674   b  would be loaded with a data value necessary to place path  674   b  in a logic low state, thus deactivating nFET  690   a . In this case, assuming nFET  688   a  is deactivated, the compare circuit  620   a  would be disabled. Otherwise, the data/cache latch associated with path  674   b  would be loaded with a data value necessary to place path  674   b  in a logic high state, thus activating nFET  690   a . By activating nFET  688   a , however, the compare circuit  620   a  is locally enabled regardless of a state of nFET  690   a.    
   The compare circuit  620   a  further includes an optional seventh nFET  692   a  having a drain coupled to the sources of nFETs  688   a  and  690   a , a source coupled to receive a ground potential at node  694   a , and a gate coupled to receive a control signal at node  678   a . The nFET  692   a  can act as a global enable device. 
   The compare circuit  620   b  is coupled to a second data path including a first leg  672   b  for a data value and a second leg  674   b  for the complement of the data value. The compare circuit  620   b  includes a first nFET  680   b  having a drain coupled to the output node  655  and a gate coupled to a first source/drain region of nFET  610   3  in path  672   b , and a second nFET  682   b  having a drain coupled to the output node  655  and a gate coupled to a first source/drain region of nFET  610   4  in path  674   b . The compare circuit  620   b  further includes a third nFET  684   b  having a drain coupled to a source of nFET  680   b  and a gate coupled to a second source/drain region of nFET  610   3  in path  672   b , and a fourth nFET  686   b  having a drain coupled to a source of nFET  682   b  and a gate coupled to a second source/drain region of nFET  610   4  in path  674   b.    
   The compare circuit  620   b  further includes an optional fifth nFET  688   b  having a drain coupled to the sources of nFETs  684   b  and  686   b  and a gate coupled to receive a control signal at node  670 , and an optional sixth nFET  690   b  having a drain coupled to the sources of nFETs  684   b  and  686   b  and a gate coupled to the path  674   a . In this configuration, the nFET  690   b  can act as a local enable device, with nFET  688   b  permitting an override of any deactivation of nFET  690   b . To locally disable the compare circuit  620   b , the data/cache latch associated with path  674   a  could be loaded with a data value to deactivate nFET  690   b . Thus, for example, if path  674   b  was associated with a known bad column, the data/cache latch associated with path  674   a  would be loaded with a data value necessary to place path  674   a  in a logic low state, thus deactivating nFET  690   b . In this case, assuming nFET  688   b  is deactivated, the compare circuit  620   b  would be disabled. Otherwise, the data/cache latch associated with path  674   a  would be loaded with a data value necessary to place path  674   a  in a logic high state, thus activating nFET  690   b . By activating nFET  688   b , however, the compare circuit  620   b  is locally enabled regardless of a state of nFET  690   b.    
   The compare circuit  620   b  further includes an optional seventh nFET  692   b  having a drain coupled to the sources of nFETs  688   b  and  690   b , a source coupled to receive a ground potential at node  694   b , and a gate coupled to receive a control signal at node  678   b . The nFET  692   b  can act as a global enable device. It is noted that while nFET devices were used in this embodiment, other switch types, such as p-channel field effect transistors (pFETs) could be used with appropriate changes in logic levels. Also, for the embodiment depicted in  FIG. 6 , logic levels placed on the data path by the data/cache latch and the output latch are presumed to be complementary, such that the output of the compare circuits  620  indicate a mismatch of data values only if the logic levels on each side of the switches  610  are the same. If the data values placed on the data path by the data/cache latch and the output latch are not complementary, appropriate output of the compare circuits  620  could be achieved by replacing nFETs  684  and  686  with pFET devices. 
   As can be seen in  FIG. 6 , a mismatch of data values would be indicated by node  655  being pulled to the ground potential, e.g., a logic low. If no mismatch occurred, the output of node  655  would be a high impedance state. If a logic high signal is desired for indicating all good columns, the node  655  could be pulled up to the logic high level, e.g., Vcc, provided that the pull-up device would be overcome if at least one of the compare circuits  620  indicated a mismatch. 
     FIG. 7  is a schematic of a portion of the data path showing the relationship between a final compare circuit  721  and an output latch  713  in accordance with one embodiment of the invention. As shown in  FIG. 7 , the compare circuit  721  has inputs coupled to legs  772  and  774  of a data path, with the inputs  780  and  784  on leg  772  coupled on opposing sides of nFET  711   a , and with the inputs  782  and  786  on leg  774  coupled on opposing sides of nFET  711   b . nFETs  711   a  and  711   b  each receive a control signal  740  for selectively isolating the inputs  780 / 784  and  782 / 786 , respectively. Operation of the compare circuit  721  may occur substantially as described with reference to  FIG. 6 . However, details of the compare circuit  721  are left out to focus on the relationship with the output latch  713 . 
   For a normal read operation, compare circuit  721  would be disabled and nFETs  711   a / 711   b  would be deactivated in response to control signal  740 . In addition, nFETs  708   a / 708   b  would be activated in response to control signal  712  while nFETs  702   a / 702   b ,  722 ,  726  and  730  would be deactivated in response to control signals  706 ,  720 ,  724  and  728 , respectively. In this manner, the data value and its complement on legs  772 / 774  would latch into the cross-coupled inverters  714 / 715  of output latch  713 . The data value in output latch  713  is then available for output to I/O node  314 . The data value may be buffered by one or more inverters  716 ,  738 ,  744  and  742 . 
   For a normal write operation, compare circuit  721  would be disabled and nFETs  711   a / 711   b  would be deactivated in response to control signal  740 . In addition, nFETs  702   a / 702   b  would be activated in response to control signal  706  while nFETs  708   a / 708   b ,  722 ,  726  and  730  would be deactivated in response to control signals  712 ,  720 ,  724  and  728 , respectively. In this manner, the data value from I/O node  314  and its complement are placed on legs  772  and  774 , respectively, for latching into the data/cache latches (not shown in  FIG. 7 ). 
   To load the output latch  713  with a data value for comparison in accordance with embodiments of the invention, compare circuit  721  would be disabled and nFETs  711   a / 711   b  would be deactivated in response to control signal  740 . In addition, nFETs  702   a / 702   b  and  708   a / 708   b  would be activated in response to control signals  706  and  712 , respectively, while nFETs  722 ,  726  and  730  would be deactivated in response to control signals  720 ,  724  and  728 , respectively. It would also be preferable that the legs  772  and  774  be isolated from the data/cache latches (not shown in  FIG. 7 ), such as by deactivating one or more of the upstream decoder circuits (not shown in  FIG. 7 ). In this manner, the data value is latched into the output latch  713 . 
   Note that in the embodiment depicted in  FIG. 7 , if a logic high data value is sensed and placed on leg  772 , it would be provided to the I/O node  314  as a logic high value. However, if a logic high value is received from the I/O node  314  for latching in the output latch  713 , it will produce a logic low value at the output of the inverter  716 . Thus, during comparison of a sensed data value and its expected data value, the inputs  780  and  786  will see a first logic level and the inputs  784  and  782  will see a second logic level if the sensed and expected data values match. Accordingly, the logic of the compare circuit  721  would need to compensate for the differing logic levels presented to the inputs of the compare circuit  721  for each leg  772 / 774  as described with reference to  FIG. 6 . 
   During a comparison of the data value in the output latch  713  to a sensed data value, compare circuit  721  would be enabled and nFETs  711   a / 711   b  would be deactivated in response to control signal  740 . In addition, nFETs  702   a / 702   b ,  708   a / 708   b ,  722 ,  726  and  730  would be deactivated in response to control signals  706 ,  712 ,  720 ,  724  and  728 , respectively. It is noted that inverter  716 , which drives the input  784  of the compare circuit  721 , is a normal part of the read path. However, inverter  718 , which is coupled to the opposite side of the output latch  713  and drives the input  786  of the compare circuit  721 , is not required for normal operation of a memory device as only one side of the output latch  713  need be driven during a read operation and the output latch  713  is typically not used for a write operation. This inverter  718  is added to buffer the signal to the input  786  as the cross-coupled inverters  714 / 715  of the output latch  713  are typically weak devices. 
   The nFETs  722 ,  726  and  730  are optionally provided in order to set or reset the output latch  713  without need to drive a data value from the I/O node  314 . For example, there would be no need to accept an external data value if it were desired to set all output latches  713  to the same data value. To set the output latch  713  to a first data value, the nFETs  722  and  730  would be activated and the nFET  726  would be deactivated, thus pulling a first side of the output latch  713  to the ground potential node  732 . To set the output latch  713  to a second data value, the nFETs  726  and  730  would be activated and the nFET  722  would be deactivated, thus pulling a second side of the output latch  713  to the ground potential node  732 . 
   CONCLUSION 
   Compare logic and methods have been described for use in memory devices. The circuits and methods allow a normal mode of operation and a test mode of operation are useful in quality programs that can be performed without the need for specialized external testing equipment. The test mode of operation includes a data comparison test mode. The data comparison test mode systematically searches for addresses of defective columns by comparing a sensed data value to an expected data value at various levels of decoding. Upon detection of a defective column, the address value for each level of decoding is stored and can be used in redundancy selection to replace the defective columns with redundant columns. The comparison is internal to the memory device such that the test mode can be run after fabrication, even by an end user, thus allowing repair after fabrication and installation. The comparisons are facilitated by compare logic inserted into the data path. 
   Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.