Patent Publication Number: US-3970951-A

Title: Differential amplifier with constant gain

Description:
Differential amplifiers using field effect transistors (FET&#39;s) in a depletion-enhancement type of transistor technology have been known and used for the amplification of analog signals. However, such known amplifiers have not been suitable for precision or linear amplification since the amplification factor of the circuit changes as the input signal voltage varies. Consequently, the output is not a true amplified copy of the input and cannot be used for measurement or control purposes without some compensating circuits. 
     It is then an object of this invention to devise a circuit of the FET type which will provide a constant amplification factor over an operating range of input signal voltages. 
     It is also an object to provide such an amplifier circuit which can be incorporated on a semi-conductor chip with other active circuitry. 
     A further object is to provide a linear circuit of the differential amplifier type which can be incorporated on a semi-conductor chip with other circuits and which will provide a uniform gain characteristic for input signals. 
     Other objects will be apparent in the following description of appended drawings showing a preferred embodiment of the circuit of my invention and in the claims which follow. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of the prior art differential amplifier. 
     FIG. 2 is a circuit diagram of the circuit of the preferred embodiment of my invention. 
     FIG. 3 is a composite chart showing the effect of the parameters to be considered in the design of a circuit as in FIG. 2. 
     Differential amplifiers can be used for amplification of low level analog type signals and provide a relatively satisfactory circuit. However, the differential amplifier when constructed in the enhanced-depleted transistor logic type of circuits on a semi-conductive chip does not maintain a constant relation between the input and output voltage signals and has not been appropriate in applications where linearity is essential for measurement or control purposes. 
    
    
     In FIG. 1, a differential amplifier circuit of a known type is shown. The circuit is conventionally fabricated on a chip having its substrate connected to a negative voltage supply to provide isolation of the circuit elements and will comprise both enhanced and depleted technology transistors. An enhanced FET has the characteristic that it will not normally conduct a current and a positive gate voltage with respect to its source is required to cause conduction whereas the depleted type FET is normally conductive and is rendered non-conductive by a gate voltage which is negative with respect to its source. 
     In FIG. 1, a depleted FET 10 has its drain connected to a terminal 11 of a drain voltage source and its gate and source electrodes are connected to the drain of an enhancement type FET 12. The gate of FET 12 is connected to a terminal 13 to receive a voltage V in  to be amplified. A second depletion FET 15 has its drain connected to voltage source 11 and its source and gate are connected to a terminal 16 where the amplified output of the circuit is available. The output terminal 16 is also connected to the drain of a second enhanced FET 17 having its gate connected to a zero reference voltage, i.e., a ground level. The sources of both FET&#39;s 12 and 17 are connected together and are supplied current by a current source 19. Current source 19 may be any substantially constant current device such as a saturated transistor or a more complex circuit. 
     The uppermost curve G 1  of the chart of FIG. 3 indicates a representative variation of the input voltage to output gain of the FIG. 1 circuit over the operating range +0.15V to -0.15V of the input voltage. It is evident that the gain varies over this range so that the amplitude of an output signal will depend upon the average level of the input signal and that the positive and negative excursions of the output will not have the same amplitude relation as in the input signal. 
     The circuit of FIG. 2 is a modified version of that of FIG. 1 and has a uniform though slightly lower gain characteristic. In this circuit, the FET&#39;s 10, 12, 15 and 17 are retained in the same configuration with current source 19, input 13 and output 16 as in FIG. 1. An additional enhancement FET 20 is provided with both its drain and its gate connected to the junction of transistors 10 and 12 and a second additional enhancement FET 21 is similarly connected to the output junction 16. The sources of FET&#39;s 20 and 21 are each connected to the reference or ground level. These additional transistors modify the reaction of the circuits to voltage variations so that the gain is non-uniformly reduced as shown by graph G 2  of FIG. 3. It may be seen that the resulting gain does not change to any appreciable extent over the usable range of input signal voltages. 
     By operating the FET devices in the saturation region (i.e., V DS  &gt; V GS  -- V T ) the terminal voltage - current relationship is given by ##EQU1## where V DS  = Drain to source voltage 
     V GS  = Gate to source voltage 
     C = Gate capacitance per unit area 
     μ = Effective carrier mobility 
     W/L = channel width to length ratio 
     Using this equation, it can be shown that the basic differential amplifier of FIG. 1 has a gain characteristic Av given by ##EQU2## in which the A subscript refers to FETs 12 and 17 the L subscript refers to FETs 10 and 15 
     
         α = 0.5K (V.sub.o - V.sub.sub + ψ).sup.-.sup.1/2 
    
     V t15  is the threshold turn-on voltage of FET 15 
     
         V.sub.t15 = K.sub.1 + K (V.sub.o - V.sub.sub + ψ).sup.1/2 = K.sub.1 + K.sup.2 /2α 
    
     k and K 1  are process dependent parameters, 
     V o  is the output voltage signal (source voltage of FET 15) 
     V sub  is the substrate to ground voltage and 
     ψ is two times the Fermi level. 
     The following specific values of these parameters were used to generate curve G 1  of FIG. 3. 
     
         λa = 27/2 (5.2) = 70.2 μv/v 
    
     
         λl = 27/2 (4.28) = 57.8 μv/v 
    
     ψ = 0.75v 
     k 1  (enhanced) = -0.84V 
     k 1  (depleted) = -4.06V 
     k = 0.919v 1/2   
     v sub  = -5V 
     i = 203μa 
     the same parameters are used to generate graph G 2  for the circuit of FIG. 2 with the additional parameter 
     
         λ.sub.20 = λ.sub.21 = 2.16μV/V. 
    
     In order to compute the voltage gain for the circuit of FIG. 2, we can consider it in two parts. ##EQU3## 
     To compute δI 17  /δV in   
     
         I.sub.19 = I.sub.12 + I.sub.17 
    
     Identifying the voltage at the common source node of FET&#39;s 12 and 17 as V s   
     
         I.sub.12 = λ.sub.A (V.sub.in - V.sub.s - V.sub.TA).sup.2 
    
     
         I.sub.17 = λ.sub.A (-V.sub.s - V.sub.TA).sup.2 
    
     Solving for (-V s  -V TA ) and substituting 
     
         I.sub.12 = λ.sub.A (V.sub.in + {I.sub.17 /λ.sub.A }.sup..5).sup.2 
    
     
         I.sub.19 = λ.sub.A (V.sub.in + { I.sub.17 /λ.sub.A }.sup..5).sup.2 + I.sub.17 
    
     I 19  is constant, and taking a partial derivative with respect to V in  ##EQU4## 
     Next, multiply both numerator and denominator of the term inside braces by λ A  /λ L ).sup..5 and also multiply the quantity outside braces by (λ L  /λ L ).sup..5. This gives ##EQU5## 
     Under the condition that 
     I 17  ≈ I 15  &gt;&gt; I 21   
     i 17  ≈ λ l  (-v t15 ).sup. 2 
     and 
     λ L  = 1/2μC (W/L) 15  for FET 15 
     Therefore -V t15  = (I 17  /λ L ).sup.. 5 and ##EQU6## To compute δV o  /δI 16  start by noting 
     
         I.sub.15 - I.sub.21 = I.sub.17 
    
     
         I.sub.17 = λ.sub.15 (-K.sub.1 -K {V.sub.o -V.sub.sub +ψ}.sup..5).sup.2 - λ.sub.21 (V.sub.o -V.sub.T21).sup.2 
    
     Taking partial derivatives and solving ##EQU7## where α 15  =  0.5K (V o  - V sub  + ψ) - .sup..5. Using ##EQU8## which factored and rearranged is ##EQU9## the voltage gain of the FIG. 3 circuit. This can be simplified as ##EQU10## where the notation implies that α 15 , Y, and X are functions of V in . 
     The behavior of these factors with respect to V in  is plotted in the lower three graphs where it may be seen that for X and α 15 , the Av increases with increasing V in  but a change in Y is a direction to compensate for changes in V in  due to X and α 15 . The slope of Y may be determined by a selection of the ratio λ 21  /λ 15  so that a desired variation (normally zero) of the circuit gain with respect to the input voltage signal may be achieved. 
     The following approximation may be used to select the λ 21  /λ 15  ratio. ##EQU11## and where the second numerator term is smaller than α 15  ##EQU12## 
     It can therefor be seen that by an appropriate selection of the characteristics of the two shunting FETs 20 and 21 as compared to the characteristics of FETs 10 and 15, the gain of the circuit may be controlled to be uniform over the operating range of the amplifier. 
     The above embodiment is intended to be illustrative of the best embodiment of the invention and is not to be taken as limiting the scope of the invention as set out in the following claims.