Patent Publication Number: US-11024552-B2

Title: Device arrangement structure assembly having adhesive tape layer

Description:
RELATED APPLICATIONS 
     This application is a divisional application of U.S. application Ser. No. 15/193,542, filed on Jun. 27, 2016, which claims the priority of U.S. Provisional Application No. 62/323,007, filed Apr. 15, 2016, which are incorporated herein by reference in their entireties. 
    
    
     BACKGROUND 
     Because semiconductor devices are commonly manufactured on circular wafers having industry standard diameters, automated test systems capable of efficient collection of large quantities of test data are typically configured to handle circular wafers having those diameters. 
     In a number of applications, including light emitting diode (LED) display technology, devices are arranged in structures that do not conform to an industry standard, circular wafer. These devices are commonly tested using manual or semi-automated methods that are less efficient than fully automated testing of standard sized circular wafers. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description, drawings, and claims. 
         FIGS. 1A and 1B  are diagrams of an assembly, in accordance with some embodiments. 
         FIGS. 2A and 2B  are diagrams of an assembly, in accordance with some embodiments. 
         FIG. 3  is a flow chart of a method of testing a test assembly, in accordance with some embodiments. 
     
    
    
     Like reference symbols in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
     The following disclosure provides different embodiments, or examples, for implementing features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     In various embodiments, a test assembly includes a device arrangement structure, a wafer having a top wafer surface and a wafer diameter, and an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by a wafer circumference in a plan view. 
     The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The array of devices is thereby electrically accessible at the first surface and capable of being tested using a test system configured for fully automated testing of wafers having the wafer diameter. 
       FIGS. 1A and 1B  are diagrams of an assembly  100 , in accordance with some embodiments.  FIG. 1A  depicts a plan view of assembly  100  and  FIG. 1B  depicts a cross-sectional view of assembly  100  through cut line A-A′. Assembly  100  includes a wafer  110 , a device arrangement structure  120 , and an adhesive layer  130  (adhesive element) between wafer  110  and device arrangement structure  120 . 
     Wafer  110  has a top wafer surface  111 , a circumference  112 , a bottom wafer surface  113 , a diameter  114 , and a thickness  115 . In some embodiments, wafer  110  comprises silicon. In various embodiments, wafer  110  comprises materials such as compound semiconductor materials or insulating materials such as glass that are capable of having a rigid structure. 
     In some embodiments, wafer  110  is an unprocessed wafer. In some embodiments, wafer  110  is a wafer that has undergone one or more manufacturing processes. In some embodiments, wafer  110  comprises one or more of a dopant, a metal, or an oxide. 
     Top wafer surface  111  is one of two flat surfaces of wafer  110 , and bottom wafer surface  113  is the other one of the two flat surfaces of wafer  110 . In some embodiments, one or both of top wafer surface  111  and bottom wafer surface  113  is a substantially planar surface. 
     Circumference  112  is a substantially circular shape. In some embodiments, circumference  112  is a circle having a notch (not shown) that, in use, is recognized by an automated test system for orientation during wafer handling. In some embodiments, circumference  112  is a circle having a flat segment (not shown) that, in use, is recognized by an automated test system for orientation during wafer handling. In some embodiments, circumference  112  is a circle having any irregular segment that, in use, is recognized by an automated test system for orientation during wafer handling. In some embodiments, circumference  112  is an uninterrupted circle. 
     Diameter  114  is the maximum distance between two opposite points of the circular portion or entirety of circumference  112 . In some embodiments, diameter  114  is 200 millimeters (mm). In some embodiments, diameter  114  is 300 mm. In some embodiments, diameter  114  is a distance corresponding to an industry standard for wafer manufacturing, handling, and testing. 
     Thickness  115  is the distance between top wafer surface  111  and bottom wafer surface  113 . In some embodiments, thickness  115  ranges from 500 micrometers (μm) to 1000 μm. In some embodiments, thickness  115  ranges from 700 μm to 800 μm. In some embodiments, thickness  115  is less than 500 μm. In some embodiments, thickness  115  is greater than 1000 μm. In some embodiments, thickness  115  is a distance corresponding to an industry standard for wafer manufacturing, handling, and testing. 
     Device arrangement structure  120  has a first surface  121  having a perimeter  122 , and a second surface  123  separated from first surface  121  by a thickness  124 . In some embodiments, perimeter  122  is a rectangle having a width  125  and a height  126 . In some embodiments, width  125  and height  126  have the same value and perimeter  122  is a square. In some embodiments, width  125  and height  126  have different values. 
     In some embodiments, perimeter  122  is a non-rectangular shape and width  125  and height  126  represent maximum distances between points in perimeter  122  in respective horizontal and vertical directions. In some embodiments, perimeter  122  is a circle having a diameter that does not correspond to an industry standard, and width  125  and height  126  represent the non-standard diameter. 
     First surface  121  and second surface  123  are substantially flat and parallel to each other such that thickness  124  is substantially uniform across at least a portion of device arrangement structure  120 . First surface  121  and second surface  123  are parallel to top wafer surface  111 . In some embodiments, thickness  124  ranges from 1 mm to 10 mm. In some embodiments, thickness  124  ranges from 2 mm to 5 mm. In some embodiments, thickness  124  is less than 1 mm. In some embodiments, thickness  124  is greater than 10 mm. 
     In some embodiments, one or both of width  125  and height  126  ranges from 50 mm to 200 mm. In some embodiments, one or both of width  125  and height  126  is approximately 100 mm. In some embodiments, one or both of width  125  and height  126  is less than 50 mm. In some embodiments, one or both of width  125  and height  126  is greater than 200 mm. 
     The largest dimension of a width, height, diagonal, or diameter of perimeter  122  is smaller than diameter  114 . Device arrangement structure  120  is positioned relative to wafer  110  such that, in a plan view, wafer circumference  112  encircles perimeter  122 . 
     Device arrangement structure  120  includes an array of devices  127 . Device arrangement structure  120  is a solid configured to hold each device  128  of the array of devices  127  in a fixed position. In some embodiments, device arrangement structure  120  comprises glass. In some embodiments, device arrangement structure  120  is an LED device structure for an LED display and the array of devices  127  is a plurality of LED devices. In some embodiments, device arrangement structure  120  includes one or more circuits and/or devices in addition to the array of devices  127 . 
     Each device  128  of the array of devices  127  has an electrical contact  129  on first surface  121 . In some embodiments, each device  128  of the array of devices  127  has a plurality of electrical contacts  129  on first surface  121 . In some embodiments, more than one device  128  shares an electrical contact  129 . In some embodiments, a device  128  has an electrical contact (not shown) in addition to electrical contact  129 , a non-limiting example being an electrical contact on second surface  123 . 
     In some embodiments, electrical contact  129  comprises a metal pad. In some embodiments, electrical contact  129  comprises a pad comprising aluminum. In some embodiments, electrical contact  129  comprises a transparent conductive material, non-limiting examples of which include zinc oxide (ZnO), indium-tin mixed oxide (ITO), antimony-tin mixed oxide (ATO), fluorine-doped tin oxide (FTO), and aluminum-doped zinc oxide (AlZO). 
     By having an electrical contact  129  on first surface  121 , each device  128  is electrically accessible at first surface  121  such that device  128  is capable of being electrically tested through the electrical contact  129 . 
     Device  128  is an electrical circuit or a combination of an electrical circuit and another component. In some embodiments, an electrical circuit is a semiconductor circuit. In some embodiments, the array of devices  127  comprises a number of devices  128  that ranges from 1,000 to 100,000. In some embodiments, the array of devices  127  comprises a number of devices  128  less than 1,000. In some embodiments, the array of devices  127  comprises a number of devices  128  greater than 100,000. 
     In some embodiments, at least one device  128  of the array of devices  127  comprises a first component  128 A and a second component  128 B. In some embodiments, each device  128  of the array of devices  127  comprises a first component  128 A and a second component  128 B. In some embodiments, first component  128 A comprises an LED. In some embodiments, first component  128 A comprises a plurality of LEDs. In some embodiments, second component  128 B comprises a control circuit for an LED. In some embodiments, second component  128 B comprises a control circuit for a plurality of LEDs. In some embodiments, first component  128 B does not have an electrical contact  129  on first surface  121  and second component  128 B has an electrical contact  129  on first surface  121 . 
     In some embodiments, device arrangement structure  120  includes a first layer  120 A and a second layer  120 B. In various embodiments, first layer  120 A comprises a transparent conductive material, non-limiting examples of which include ZnO, ITO, ATO, FTO, and AlZO. 
     In some embodiments, second layer  120 B comprises a glass material such as silicon dioxide (SiO 2 ). In some embodiments, second layer  120 B comprises the array of devices  127 . 
     In some embodiments, adhesive layer  130  comprises a glue or other adhesive material capable of maintaining device arrangement structure  120  in a stationary position relative to wafer  110 . Adhesive layer  130  contacts wafer  110  at top wafer surface  111  and contacts device arrangement structure  120  at second surface  123 . In some embodiments, adhesive layer  130  contacts one or both of wafer  110  and device arrangement structure  120  at one or more additional surfaces. 
     In some embodiments, adhesive layer  130  comprises an adhesive material having adhesive properties responsive to temperature changes such that, in operation, device arrangement structure  120  is mounted to wafer  110  and/or dismounted from wafer  110  at an elevated temperature with respect to a temperature of a test or manufacturing environment. 
     In some embodiments, adhesive layer  130  comprises an adhesive material capable of being cured such that, in operation, the adhesive material is applied to top wafer surface  111  and/or second surface  123  as a liquid or paste and cured to be configured to maintain the position of device arrangement structure  120  relative to wafer  110 . 
     In some embodiments, adhesive layer  130  comprises an adhesive material capable of being dissolved such that device arrangement structure  120  is capable of being dismounted from wafer  110  by a solvent. 
     In some embodiments, adhesive layer  130  comprises one or more sections of a tape having a top adhesive surface in contact with second surface  123  and a bottom adhesive surface in contact with top wafer surface  111 . 
     In some embodiments, adhesive layer  130  contacts an entirety of top wafer surface  111 . In some embodiments, adhesive layer  130  contacts a portion of top wafer surface  111 . In some embodiments, adhesive layer  130  contacts multiple portions of top wafer surface  111 . 
     In some embodiments, adhesive layer  130  contacts an entirety of second surface  123 . In some embodiments, adhesive layer  130  contacts a portion of second surface  123 . In some embodiments, adhesive layer  130  contacts multiple portions of second surface  123 . 
       FIGS. 2A and 2B  are diagrams of an assembly  200 , in accordance with some embodiments.  FIG. 2A  depicts a plan view of assembly  200  and  FIG. 2B  depicts a cross-sectional view of assembly  200  through cut line B-B′. Assembly  200  includes wafer  110  and device arrangement structure  120 , discussed above with respect to assembly  100 . Although a number of features of wafer  110  and device arrangement structure  120  are not depicted in  FIGS. 2A and 2B , assembly  200  is understood to include the features of wafer  110  and device arrangement structure  120  discussed above with respect to assembly  100 . 
     In some embodiments, such as those depicted in  FIG. 2B , assembly  200  does not include adhesive layer  130 . In some embodiments, assembly  200  includes adhesive layer  130 . 
     Assembly  200  includes a tape layer  230  (adhesive element). Tape layer  230  is one or more sections of a tape having an adhesive surface. The adhesive surface of tape layer  230  contacts a portion of top wafer surface  111  and a portion of first surface  121 . In some embodiments, the adhesive surface of tape layer  230  contacts one or both of wafer  110  and device arrangement structure  120  at one or more additional surfaces. 
     In some embodiments, tape layer  230  has mechanical and adhesive strength such that tape layer  230  is capable of maintaining device arrangement structure  120  in a stationary position relative to wafer  110 . In some embodiments in which assembly  200  includes adhesive layer  130 , the combination of adhesive layer  130  and tape layer  230  has mechanical and adhesive strength such that the combination of adhesive layer  130  and tape layer  230  is capable of maintaining device arrangement structure  120  in a stationary position relative to wafer  110 . 
     In some embodiments, first surface  121  has a rectangular perimeter  122  and tape layer  230  comprises four tape layers, each tape layer corresponding to a corner of perimeter  122 . In some embodiments, tape layer  230  comprises fewer than four tape layers. In some embodiments, tape layer  230  comprises more than four tape layers. 
       FIG. 3  is a flow chart of a method  300  of testing a test assembly. Method  300  is capable of being performed with an assembly  100  or an assembly  200 , described above with respect to  FIGS. 1A and 1B and 2A and 2B , respectively. 
     In some embodiments, method  300  includes operation  305 , at which devices are arranged in a device arrangement structure. In some embodiments, arranging the devices includes arranging devices  127  in device arrangement structure  120 . In some embodiments, arranging the devices includes arranging LED devices on an LED device structure that is part of an LED display. 
     At operation  310 , the device structure is mounted on a wafer having a diameter that corresponds to an industry standard. Mounting the device structure on a wafer includes using an adhesive element to form a test assembly. In some embodiments, using the adhesive element includes applying an adhesive layer between the device structure and the wafer. In some embodiments, using the adhesive element includes applying adhesive layer  130  between second surface  123  of device arrangement structure  120  and top wafer surface  111  of wafer  110 . In some embodiments, using the adhesive element includes applying adhesive layer  130  to one or both of second surface  123  of device arrangement structure  120  and top wafer surface  111  of wafer  110 . In some embodiments, applying an adhesive layer includes using an elevated temperature relative to a temperature of a test or manufacturing environment. In some embodiments, applying an adhesive layer includes curing the adhesive layer. 
     In some embodiments, using the adhesive element includes applying a tape layer to a top surface of the device arrangement structure and to a surface of the wafer. In some embodiments, using the adhesive element includes applying tape layer  230  to top surface  121  of device arrangement structure  120  and to top wafer surface  111  of wafer  110 . 
     Mounting the device structure to the wafer includes mounting the device structure including the array of devices being electrically accessible at the top surface of the device arrangement structure. 
     At operation  315 , an automated test sequence is performed on the array of devices. Performing the automated test sequence includes controlling movement of the test assembly using an automated test system configured to test wafers having the wafer diameter. Performing the automated test sequence also includes electrically accessing the array of devices at the top surface of the device arrangement structure. 
     In some embodiments, performing the automated test sequence includes executing a functional test on a device. In some embodiments, performing the automated test sequence includes executing an electrical test to measure an electrical property of a device, non-limiting examples of which include resistance, conductance, capacitance, leakage current, and threshold voltage. 
     In some embodiments, performing the automated test sequence includes executing software routines on the test system. In some embodiments, executing the software routines on the test system includes executing software routines that are designed to be executed on wafers having the wafer diameter. In some embodiments, performing the automated test sequence includes executing a wafer acceptance test (WAT) routine. In some embodiments, performing the automated test sequence includes executing a circuit probe (CP) routine. 
     In some embodiments, at least one device of the array of devices comprises an LED and a control circuit, and performing the automated test sequence comprises performing an electrical test of at least one control circuit of the at least one device. 
     In some embodiments, controlling movement of the test assembly using the automated test system includes automatically positioning a device of the array of devices under a test fixture. In some embodiments, the test fixture includes a probe pin configured make an electrical connection with an electrical contact on the top surface of the device arrangement structure. In some embodiments, the test fixture includes an array of probe pins configured to have a given probe pin make an electrical connection with a corresponding electrical contact on the top surface of the device arrangement structure. 
     In some embodiments, the test assembly is one test assembly of a plurality of test assemblies numbering from 20 to 30. In some embodiments, the test assembly is one test assembly of a plurality of test assemblies numbering fewer than 20. In some embodiments, the test assembly is one test assembly of a plurality of test assemblies numbering greater than 30. 
     In some embodiments, the test assembly is one test assembly of a plurality of test assemblies and controlling movement of the test assembly using the automated test system includes automatically loading each test assembly of the plurality of test assemblies onto a moveable test platform in contact with a bottom surface of the wafer. In some embodiments, controlling movement of the test assembly using the automated test system includes automatically retrieving each test assembly of the plurality of test assemblies from a wafer container configured to store wafers having the wafer diameter. In some embodiments, controlling movement of the test assembly using the automated test system includes automatically storing each test assembly of the plurality of test assemblies in a wafer container configured to store wafers having the wafer diameter. 
     In some embodiments, the test assembly is one test assembly of a plurality of test assemblies and performing the automated test sequence on the array of devices includes storing test data for each assembly of the plurality of test assemblies. In some embodiments, storing test data for each assembly of the plurality of test assemblies includes storing an identifier for each assembly of the plurality of test assemblies. In some embodiments, storing test data for each assembly of the plurality of test assemblies includes storing location data for one or more devices of the array of devices. In some embodiments, storing test data for each assembly of the plurality of test assemblies includes storing test outcome data for one or more devices of the array of devices, non-limiting examples of test outcomes including pass-fail status and comparison to a threshold value. 
     In some embodiments, electrically accessing the array of devices at the top surface of the device arrangement structure includes electrically accessing an entirety of the array of devices. In some embodiments, electrically accessing the array of devices at the top surface of the device arrangement structure includes electrically accessing a subset of the array of devices. 
     In some embodiments, a device has a plurality of electrical contacts at the top surface of the device arrangement structure and electrically accessing the array of devices at the top surface of the device arrangement structure includes accessing each electrical contact of the plurality of electrical contacts. In some embodiments, a device has a plurality of electrical contacts at the top surface of the device arrangement structure and electrically accessing the array of devices at the top surface of the device arrangement structure includes accessing a subset of the plurality of electrical contacts. 
     In some embodiments, method  300  includes operation  320 , at which the device arrangement structure is dismounted from the wafer. In some embodiments, dismounting the device arrangement structure from the wafer includes applying heat to the test assembly. In some embodiments, dismounting the device arrangement structure from the wafer includes applying a solvent to the test assembly. 
     By mounting device arrangement structures on wafers to form test assemblies, devices electrically accessible at top surfaces of the device arrangement structures can be tested using automated test systems configured for the wafers. For multiple test assemblies, efficiency is thereby improved by as much as 90% in comparison to manual or semi-automated testing. Automatically obtaining and linking test data to specific devices also facilitates data analysis. 
     An aspect of this description relates to an assembly. The assembly includes a wafer having a top wafer surface and a wafer circumference. The assembly further includes a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view; and an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly further includes an adhesive element configured to affix the device arrangement structure in a stationary position relative to the wafer, wherein the adhesive element includes a tape layer having an adhesive surface attached to the top surface of the device arrangement structure and attached to a surface of the wafer. In some embodiments, the adhesive element includes an adhesive layer between the top wafer surface and the device arrangement structure. In some embodiments, the perimeter is a rectangle; and the adhesive element includes four tape layers, each tape layer of the four tape layers contacting the top wafer surface and the first surface at a corner of the rectangle. In some embodiments, at least one device of the array of devices is a semiconductor circuit including a light emitting diode (LED). 
     An aspect of this description relates to an assembly. The assembly includes a wafer having a top wafer surface and a circular wafer circumference. The assembly further includes a light emitting diode (LED) device structure. The LED device structure includes a first surface having a perimeter, the perimeter being a rectangle having dimensions smaller than a diameter of the wafer circumference; a second surface parallel to the first surface and the top wafer surface and between the first surface and the top wafer surface; and a plurality of LED devices, at least one LED device of the plurality of LED devices having an electrical contact on the first surface. The assembly further includes an adhesive element configured to affix the LED device structure in a stationary position relative to the wafer, wherein the adhesive element comprises a tape layer having an adhesive surface attached to the top surface of the LED device structure and attached to a surface of the wafer. In some embodiments, the at least one LED device of the plurality of LED devices includes an LED and a control circuit; and the electrical contact on the first surface is an electrical contact to the control circuit. In some embodiments, the LED device structure includes a first layer comprising a transparent conductive material and having the first surface; and a second layer comprising a glass material and having the second surface. In some embodiments, the second layer includes the plurality of LED devices. In some embodiments, the adhesive element includes an adhesive layer between the top wafer surface and the second surface. 
     An aspect of this disclosure relates to an assembly. The assembly includes a wafer having a top wafer surface. The assembly includes a device arrangement structure. The device arrangement structure includes a first surface, wherein the first surface is a farthest surface of the device arrangement structure from the wafer; and an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly further includes a plurality of adhesive elements configured to affix the device arrangement structure in a stationary position relative to the wafer, wherein a first adhesive element of the plurality of adhesive elements includes a tape layer having an adhesive surface attached to the first surface and attached to the top wafer surface. In some embodiments, a second adhesive element of the plurality of adhesive elements is between the wafer and the device arrangement structure. In some embodiments, the second adhesive element covers an entirety of the top wafer surface. In some embodiments, the first adhesive element is over a first edge of the device arrangement structure, and a second adhesive element of the plurality of adhesive elements is over a second edge, different from the first edge, of the device arrangement structure. In some embodiments, the device arrangement structure includes a first layer and a second layer, and the second layer is between the wafer and the first layer. In some embodiments, the first layer includes a transparent conductive material. In some embodiments, the transparent conductive material includes at least one of ZnO, ITO, ATO, FTO or AlZO. In some embodiments, the second layer includes a glass material. In some embodiments, the array of devices is in the second layer, and the contact is on the first layer. In some embodiments, a device of the array of devices includes a light emitting diode (LED); and a control circuit electrically connected to the LED. In some embodiments, the plurality of adhesive elements includes an adhesive element over each corner of the device arrangement structure. 
     Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.