Patent Publication Number: US-7218082-B2

Title: Compensation technique providing stability over broad range of output capacitor values

Description:
TECHNICAL FIELD 
   The present subject matter relates to amplifier and buffer circuitry, for example for linear voltage regulators, stable over a broad range of output capacitor values. 
   BACKGROUND 
   Circuits comprising an amplifier and buffer find many applications in modern electronic devices. For example, voltage regulators based on such circuitry are used to supply a constant voltage source from an unregulated or regulated higher voltage supply. Low dropout (LDO) linear regulators are designed to allow a small voltage drop between the input supply and the regulated output voltage. LDOs thus decrease the headroom requirement and also increase power efficiency compared to linear regulators with high dropout architectures. 
     FIG. 7  shows a typical architecture for a low dropout linear regulator  10 . The input stage is a differential gain stage consisting of a transconductance (gm) amplifier  11  driving a high impedance node (V G ) with a resistance R O  in parallel with a capacitance C 1 . The V G  node is where the majority of the regulator&#39;s gain is established. Following the input gain stage is a buffer amplifier  13  to drive the high capacitive node of a pass element. For this architecture, a PMOS transistor  15  is used as the pass element to deliver current from the input supply to the regulator output. A resistor divider, R F1  and R F2 , feeds back a divided voltage of the output to the non-inverting input terminal of the gm amplifier  11 . This feedback regulates the output voltage to some multiple of V REF  depending on the ratio of the feedback resistors. The LDO output (V OUT ) is bypassed by an output capacitor C OUT . 
   Some of the specific challenges regarding the design of LDOs relate to its compensation. The frequency of the output pole (P OUT ) directly depends on the load current and is equal to 1/(2π*R O,PMOS *C O ). R O,PMOS  is the drain output resistance of the PMOS transistor pass device  15  and equals V A /I LOAD , where V A  is the transistor Early voltage, and I LOAD  is the output load current. Thus, P OUT  can swing several decades depending on the load current swing, making the placement of the pole at V G  (P G ) critical. If the frequencies of P G  and P OUT  lie too close together below crossover frequency, instability can occur. 
   One compensation strategy is to make P OUT  the dominant pole. The non-dominant pole P G , therefore, must lie beyond the maximum frequency of P OUT  by at least the gain of the regulator for ample phase margin. This can lead to high operating currents, and often low loop gain to ensure P G  is beyond crossover. Increasing the output capacitor value to guarantee that P OUT  is at low enough frequencies for all load currents also can be unattractive due to increased cost and solution size. 
   Another strategy is to make P G  the dominant pole by adding a compensating capacitor at V G . P OUT , therefore, must either lie beyond the crossover frequency, or a zero must be inserted (usually in the form of capacitor ESR) to counter the pole before crossover. The first case defines a minimum frequency requirement for P OUT , placing constraints on the minimum load current and maximum output capacitor value. These constraints can be undesirable as they generally require significant quiescent load current and typically have poor transient response. The second case puts specific constraints on the type of output capacitor, and again requires a broadband P G  pole beyond the output zero. These constraints can be undesirable for size, power consumption, cost, and transient response reasons. 
   SUMMARY 
   An amplifier-buffer circuit, such as used in a linear voltage regulator which is responsive to an input voltage to supply a regulated voltage to a load, implements an output stage configured with a compensation scheme providing stability of operations over a wide range of output capacitor values. The present teachings may be applied to amplifier and buffer circuits intended for a variety of applications, although discussion of examples will focus mainly on voltage regulators. 
   Hence, in several aspects, a circuit comprises an amplifier and an output stage, which may be a buffer. The amplifier monitors a voltage proportional to a signal output of the circuit to a load. In response, the amplifier generates an error signal indicative of a difference from a reference voltage. The output stage or the buffer is responsive to the error signal from the amplifier for processing an input signal to provide the signal output to the load. The output stage includes a metal oxide semiconductor (MOS) pass transistor having a source and a drain coupled between the input signal and the load. The gate of this transistor controls the voltage drop across the MOS pass transistor to provide the output signal to the load. The buffer or output stage also includes an input transistor circuit. 
   An example of this circuit, to implement a voltage regulator, which is operative over a range of capacitances at the output. The regulator comprises a control circuit, for monitoring a voltage proportional to voltage at the load to generate an error signal indicative of a difference from a reference voltage, and an output stage responsive to the error signal from the control circuit for providing the regulated voltage to the load. The output stage includes a metal oxide semiconductor (MOS) pass transistor having a source and a drain coupled between the input voltage and the load and a gate for controlling the voltage drop across the MOS pass transistor to provide the regulated voltage at the load. The output stage also includes an input transistor circuit responsive to the error signal coupled to control operation of the MOS pass transistor. This transistor circuit presents a shunt impedance to the error signal for values of the output capacitance within a portion of the range, so as to stabilize the closed loop gain of the voltage regulator over that portion of the range. 
   In the examples, the output stage is configured to have high bandwidth and a low output resistance. Several examples of the output stage use two MOS current mirrors, where the transistor serving as the pass element for the voltage regulator is an element of the second MOS current mirror. Other examples of the output stage use one or more resistor-transistor circuits. The high bandwidth and low output resistance of the output stage provide stability for low to moderate capacitance by pushing the output pole to high frequencies while an internal pole is dominant and rolls off the gain at lower frequencies. For high output capacitance, the shunt impedance couples the internal pole and output pole, such that the output pole becomes dominant while the internal pole gets pushed to higher frequencies, maintaining stability. 
   Two different examples of the transistor circuit of the output stage are described below. In one example, this circuit includes a bipolar junction transistor (BJT) having a base receiving the error signal. In this implementation, the base-emitter resistance of the BJT forms the shunt providing resistive shunting for higher values of output capacitance. The other example of the transistor circuit of the output stage uses an MOS transistor, with its gate receiving the error signal. In this second implementation, the transistor circuit of the output stage further comprises a series resistance and capacitance forming the shunt, connected to the gate of the MOS transistor. 
   In another aspect, a circuit may comprise an amplifier, an integration circuit and an output stage buffer. The amplifier has gain greater than unity and is coupled to the output signal. The integration circuit is coupled to the output of the amplifier. The output stage buffer processes an input signal in response to a signal from the integration circuit, to produce the output signal supplied to the load. The integrator and the output stage buffer are configured to stabilize the closed loop gain of the circuit over respective portions of a specified range of capacitance appearing at a connection of the output stage buffer to the load. 
   An example of such a circuit may serve as a voltage regulator, which comprises a high impedance amplifier responsive to a voltage supplied to the load for outputting an error signal, an integration circuit coupled to the error signal output of the amplifier, and a unity gain output stage. The unity gain output stage is coupled to the input voltage and supplies the regulated voltage to the load in response to the error signal received via the integration circuit. The integrator and the unity gain output stage stabilize the regulated voltage over respective portions of the range of output capacitance. 
   In the examples, the unity gain output stage has a high bandwidth and a low output resistance, so as to stabilize operation for low to moderate capacitance by pushing the output pole to high frequencies while an internal pole is dominant and rolls off the gain at lower frequencies. For high output capacitance, an input impedance of the output stage couples the internal pole and output pole, such that the output pole becomes dominant while the internal pole gets pushed to higher frequencies, maintaining stability. 
   Additional objects, advantages and novel features of the examples will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and the accompanying drawings or may be learned by production or operation of the examples. The objects and advantages of the present teachings may be realized and attained by practice or use of the methodologies, instrumentalities and combinations particularly pointed out in the appended claims. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The drawing figures depict one or more implementations in accord with the present teachings, by way of example only, not by way of limitations. In the figures, like reference numerals refer to the same or similar elements. 
       FIG. 1  is a schematic diagram of an example of a linear voltage regulator. 
       FIG. 2  is a functional block diagram useful in explaining the small-signal characteristics of the output stage of the regulator of  FIG. 1 . 
       FIG. 3  is a Bode plot for the regulator of  FIG. 1 , with low and high C OUT  values. 
       FIGS. 4–6  are schematic diagrams of several other examples of a linear voltage regulator. 
       FIG. 7  is a schematic diagram of a prior art low dropout linear voltage regulator. 
   

   DETAILED DESCRIPTION 
   In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. However, it should be apparent to those skilled in the art that the present teachings may be practiced without such details. In other instances, well known methods, procedures, components, and circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings. 
   The present teachings are applicable to circuitry combining an amplifier and a buffer. Although there are many other applications for such circuits, for convenience, discussion of the examples below will focus on examples intended for use as voltage regulators, particularly linear voltage regulators. 
     FIG. 1  is a schematic of a low dropout (LDO) linear voltage regulator  30 . The regulator  30  comprises an input stage and an output stage. The input stage serves as a high gain amplifier, e.g. for uses as a control circuit for generating an error signal to control the output stage as a function of a voltage proportional to the load voltage. The output stage has unity gain and serves as a buffer. 
   The input gain stage includes a differential gm amplifier  31  feeding into a high impedance integrating node (V INT ) with output resistance R O . A compensating capacitor and resistor (R C  and C C ) are added to V INT  as part of the compensation scheme. The input stage provides all the open-loop DC gain for the LDO  30 , which equals gm IN *R O  with respect to gm amplifier  31 &#39;s differential input. A resistor divider, R F1  and R F2 , feeds back a divided voltage of the output to the non-inverting input terminal of the gm amplifier  31 . This feedback regulates the output voltage to some multiple of V REF  depending on the ratio of the feedback resistors. The LDO output (V OUT ) is bypassed by an output capacitor C OUT . 
   The output stage  35  comprises a pass transistor N 2  and stabilizing circuitry. The stage  35  essentially is a unity-gain amplifier (buffer) that includes the pass transistor element N 2  inside the loop and is responsive to the integrated error signal as it appears at node V INT . 
   A bipolar junction transistor (BJT) Q 1  provides the connection between the input gain stage and output stage and serves as the input circuit for the stage  35 . The base emitter resistance of the BJT contributes to the compensation scheme, which will be illustrated later. A later embodiment ( FIG. 4 ) utilizes a MOS device for this input coupling transistor, but to provide the compensation, the input circuit there utilizes an additional shunt impedance. 
   As shown in  FIG. 1 , the output stage  35  utilizes two current mirror circuits  37  and  39 . The first current mirror circuit  37  uses two P-type metal oxide semiconductor (PMOS) transistors P 1  and P 2 . The second current mirror circuit  39  uses two N-type metal oxide semiconductor (NMOS) transistors N 1  and N 2 . The base of Q 1  connects to the error signal output of the gain stage, and its collector current is mirrored by P 1  and P 2  with a mirror gain of M. The output of the PMOS mirror feeds into the second mirror  39  comprised of N 1  and N 2  with mirror gain N−1. NMOS transistor N 2  serves as the pass device for the LDO  30 , with its source as V OUT . The loop of the output stage is closed by tying V OUT  back to the emitter of Q 1 . 
   The high bandwidth and low output resistance of the output stage provide stability for low to moderate capacitance by pushing the output pole to high frequencies while an internal pole is dominant and rolls off the gain at lower frequencies. For high output capacitance, the shunt impedance couples the internal pole and output pole, such that the output pole becomes dominant while the internal pole gets pushed to higher frequencies, maintaining stability. 
   The LDO architecture of  FIG. 1  includes an NMOS pass transistor N 2  in a source-follower configuration. To achieve low drop out operation (i.e. small V IN −V OUT ), the gate of the pass device N 2  should be driven to a voltage higher than V IN . Therefore, a separate but higher voltage supply V BIAS  is needed to provide the appropriate NMOS gate voltage for low drop out operation. In the example of  FIG. 1 , for correct operation at full rated load current (I OUT ), V BIAS  should be greater than V IN  by at least: (V BIAS −V IN )≧(V SAT (P 2 )+V GS (N 1 )−V DROPOUT ) 
   There are various methods for generating the V BIAS  supply voltage. In a first example, the user of the LDO regulator  30  could provide both V IN  and V BIAS  supplies through separate external power sources. Second, a DC to DC boost converter could be used to generate V BIAS  from V IN . Optimally the boost converter could be integrated on the same integrated circuit as the LDO regulator  30 . The design of DC to DC boost converters is well documented and understood by those skilled in the art and is beyond the scope of this detailed description. As another example, the user may supply V BAIS  and use a DC to DC buck converter to generate V IN . Again the buck converter could optimally be included on the same integrated circuit as the LDO regulator  30 . The benefit of such a configuration is that high efficiency power conversion is maintained from V BIAS  to V IN  while the LDO output will provide rejection from V IN  ripple inherent in the DC to DC switching conversion process. 
   The current source I BIAS  shown in the example of  FIG. 1  may be included, to always have some collector current flowing in Q 1  even under no load conditions. When I OUT  is zero, Q 1  is biased up with a collector current of I BIAS /M. This ensures that Q 1  always has a finite base resistance for the compensation scheme to work, even under very low output current levels. 
   The entire output stage can be imagined as its own feedback amplifier configured in unity-gain feedback, as shown by the small-signal block diagram in  FIG. 2 . Transistor Q 1  serves as the gm amplifier  41 , with its base as the non-inverting input, its emitter as the inverting input, and its collector as the gm output. The small-signal collector current is multiplied by gains M and N, which represent the two mirror stages  37  and  39 . Thus the total closed-loop transconductance gain of the output stage (GM OS ) from V INT  to I OUT  is equal to gm Q1 (1+M*N). The closed-loop voltage gain, however, from V INT  to V OUT  is unity. 
   For small to moderate output capacitor values, the integrating node serves as the dominant pole and is equal to P INT =1/(2π*R O *C C ). The non-dominant pole at V OUT  is at much higher frequencies compared to conventional PMOS LDO architectures because of the smaller output resistance (R OUT ) at the source of N 2 . This output resistance equals the inverse of the closed-loop transconductance of the output stage, which is equal to R OUT =1/GM OS . Therefore, the output pole is pushed to a value of GM OS /(2π*C OUT ), where GM OS  equals gm Q1 (1+M*N). Thus the output stage provides a very low output resistance R OUT , allowing the use of greater valued output capacitors at C OUT  while maintaining adequate phase margin. 
   The implementation of the NPN bipolar junction transistor Q 1  helps sustain LDO stability, as the output capacitor value further increases towards infinity. Q 1 &#39;s base resistance r π1  plays a role in the compensation, as C OUT  increases from moderate to very high capacitor values. For small to moderate-valued capacitors, the input resistance of the output stage (R IN  in  FIGS. 1–3 ) looks very high impedance, since the output stage acts like a voltage follower to V OUT . However, as C OUT  increases towards infinity, the impedance at the output node decreases and V OUT  begins to behave as an incremental ground. Thus, the resistance R IN  looking into the base of Q 1  no longer looks high impedance, but instead this resistance looks like the base resistance r π1  of transistor Q 1  providing a shunt connection to ground through C OUT . 
   This base resistance shunting of the high resistance of the V INT  node reduces the impedance of the internal node and pushes out the internal pole P INT  to higher frequencies. Meanwhile, the output pole continues to travel to lower frequencies as C OUT  increases. Eventually, the two poles swap roles. P OUT  becomes the dominant pole while P INT  is pushed out to a higher frequency equal to 1/(2π*r π1 *C C ), where r π1  is equal to Beta Q1 /gm Q1 .  FIG. 3  illustrates this change in compensation between low and high C OUT  values. 
   This use of a BJT for Q 1  contributes to the compensation scheme because of the base resistance provided by that type of transistor. If a MOS device were used in place of Q 1 , P INT  and P OUT  would be completely isolated from each other, since the gate resistance of a MOS device is virtually infinite. Thus, as C OUT  increases, P INT  stays fixed at 1/(2π*R O *C C ) while P OUT  travels to lower frequencies. Eventually, the stability of the regulator becomes compromised when C OUT  reaches a value when P OUT  and P INT  are at the same vicinity. 
   Note that even with a BJT for Q 1 , the above scenario can still occur resulting in marginal stability. This happens for intermediate C OUT  values where P OUT  and P INT  cross over each other. The region where this occurs, however, is at much higher frequencies compared to the MOS case, because P INT  moves out towards higher frequencies as C OUT  increases for the BJT case. Because this region is at a higher frequency, a reasonable sized compensating resistor (R C ) can advantageously be inserted in series with the compensating capacitor C C  at V INT . This creates a zero in the frequency response that can easily be tuned to frequencies above the crossover region, creating additional phase margin. 
   An element of the compensation strategy in the example of  FIG. 1  is the shunting of V INT  by the intrinsic base resistance of Q 1 . In that embodiment, Q 1  is a BJT type transistor. However, the compensation scheme may be implemented using other transistor types, but a different shunting is provided to implement the compensation scheme.  FIG. 4  shows another embodiment  40  of an LDO, which is generally similar to the embodiment of  FIG. 1 , but substitutes a metal oxide semiconductor—field effect transistor (MOSFET), specifically NMOS transistor N 3  in the output stage  45 , in place of the BJT input transistor Q 1 . Otherwise, the LDO  40  is the same as the LDO  30 , and like components are identified by the same reference characters. 
   As outlined above, a bare replacement of Q 1  with an MOS transistor would disrupt the compensation method, since a MOSFET has virtually infinite resistance looking into its gate. However, a shunting resistor that mimics the base resistance of Q 1  can be explicitly added around the MOS transistor N 3  so that the compensation scheme can work. 
   In the illustrated example, a series resistor-capacitor network is connected between V INT  and V OUT . R X  resembles the shunting resistor for this case. The addition of series capacitor C X  insures that the DC biasing of the output stage is not disrupted by R X . For frequencies above DC, C X  can be considered as a short circuit. Thus, the small signal model of the output stage  45  would look exactly like that of the output stage  35  in  FIG. 2 , and the compensation strategy would still apply. The disadvantage of this method over that of  FIG. 1  is that C X  could be substantially large for it to act like a short circuit for frequencies of interest. 
   However, the output stage  45  does provide substantially the same stability. Again the high bandwidth and low output resistance of the output stage provide stability for low to moderate capacitance by pushing the output pole to high frequencies while an internal pole is dominant and rolls off the gain at lower frequencies. For high output capacitance, the shunt impedance couples the internal pole and output pole, such that the output pole becomes dominant while the internal pole gets pushed to higher frequencies, maintaining stability. 
     FIG. 5  shows another embodiment  50  of an LDO, which is generally similar to the embodiment  30  of  FIG. 1 , but does not utilize current mirrors in the output stage  55 . Essentially, in circuit  57 , a resistor R P  has been substituted for the transistor P 1 ; and in circuit  59 , a resistor R N  has been substituted for the transistor N 1 . Current mirrors as in  FIGS. 1 and 4  are preferred, as the use of current mirrors creates a constant open loop gain in the output stage and is easy to set up and prove stability. The circuit using resistors can produce substantially similar results, however, adding the resistors means that current gain is not constant, so more effort must be expended to ensure stability of the output stage loop. Otherwise, the LDO  50  is the same as the LDO  30 , and like components are identified by the same reference characters. 
     FIG. 6  shows another embodiment  60  of an LDO, which is generally similar to the embodiment  50  of  FIG. 5 , and like components are identified by the same reference characters. For example, like the LDO  50 , the LDO  60  does not utilize current mirrors, and instead uses resistors in the circuits  67 ,  69 . The LDO design  60 , however, goes a step further by providing a low impedance follower in the circuit  69  to drive the high capacitance load of the large output NMOS (N 2 ). The bias current through the follower driving N 2  is selected to push the pole of gate of N 2  out beyond cross over. In both resistor circuit cases ( FIGS. 5 and 6 ), the I bias  of  FIGS. 1 and 4  is not needed as a fixed amount of current is required to turn on P 2  and N 2  (namely V gs (P 2 )/R p ). 
   While the foregoing has described what are considered to be the best mode and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.