Patent Publication Number: US-11394379-B2

Title: Switch device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims priority benefit of Japanese Patent Application No. JP 2019-199617 filed in the Japan Patent Office on Oct. 31, 2019. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety. 
     BACKGROUND 
     The disclosure in the present specification relates to a switch device. 
     The inventor of the present application has been proposing a large number of new technologies for switch devices such as an in-vehicle intelligent power device (IPD) since before (see, for example, PCT Patent Publication No. WO2017/187785). 
     SUMMARY 
     For such related-art switch devices, however, there is room for further improvement in determining which of output abnormal conditions is occurring (particularly, distinguishing, during a switch-on period of a high-side switch large-scale integration (LSI), which of a load-open condition and a short-to-power-supply-voltage condition is occurring). 
     Accordingly, it is desirable to provide a switch device capable of properly determining which of output abnormal conditions is occurring. 
     A switch device according to an embodiment of the present disclosure includes a switch element coupled between a power supply terminal and an output terminal, and an output abnormality detection circuit that, when an output current flowing during a turn-on period of the switch element is smaller than a threshold value, detects an occurrence of an output abnormal condition, and increases a turn-on resistance of the switch element to determine which of a load-open condition and a short-to-power-supply-voltage condition is occurring at the output terminal on the basis of an output voltage at the output terminal (first configuration). 
     Here, in the switch device configured according to the first configuration, the output abnormality detection circuit preferably increases the turn-on resistance so as to cause the output voltage to coincide with a first voltage (second configuration). 
     Further, in the switch device configured according to the second configuration, the output abnormality detection circuit preferably compares the output voltage with a second voltage higher than the first voltage to determine which of the load-open condition and the short-to-power-supply-voltage condition is occurring at the output terminal (third configuration). 
     Further, in the switch device configured according to the third configuration, the output abnormality detection circuit preferably determines that the load-open condition is occurring at the output terminal when the output voltage is lower than the second voltage, and that the short-to-power-supply-voltage condition is occurring at the output terminal when the output voltage is higher than the second voltage (fourth configuration). 
     Further, in the switch device according to the fourth configuration, the output abnormality detection circuit preferably includes a first comparator that compares an output current detection signal according to the output current or a sense voltage according to the output current with a predetermined threshold voltage to generate an output abnormality detection signal, a second comparator that compares the output voltage with the first voltage to generate a turn-on resistance control signal, and a third comparator that compares the output voltage with the second voltage to generate a determination signal (fifth configuration). 
     Further, in the switch device configured according to the fifth configuration, the second comparator and the third comparator are preferably enable-controlled according to the output abnormality detection signal (sixth configuration). 
     Further, in the switch device according to the fifth configuration or the sixth configuration, the output abnormality detection circuit preferably further includes a first resistor coupled between the power supply terminal and an application node of the first voltage, a second resistor coupled between the power supply terminal and an application node of the second voltage, a first current source coupled between the application node of the first voltage and a constant electric potential node, and a second current source coupled between the application node of the second voltage and the constant electric potential node (seventh configuration). 
     Further, an electronic device according to another embodiment of the present disclosure includes the switch device configured according to any one of the above first to seventh configurations, and a load coupled to the switch device (eighth configuration). 
     Here, in the electronic device configured to according to the eighth configuration, the load is preferably a valve lamp, a relay coil, a solenoid, a light emitting diode, or a motor (ninth configuration). 
     Further, a vehicle according to a further embodiment of the present disclosure includes the electronic device according to the eighth configuration or the ninth configuration (tenth configuration). 
     According to the embodiments of the present disclosure, a switch device capable of properly determining which of output abnormal conditions is occurring can be provided. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating an entire configuration example of a semiconductor integrated circuit device; 
         FIG. 2  is a diagram illustrating a configuration example of a gate control section; 
         FIG. 3  is a diagram illustrating a configuration example of an output current detection section; 
         FIG. 4  is a diagram that describes a short-to-ground condition during a switch-on period; 
         FIG. 5  is a diagram that describes a load-open condition during a switch-on period; 
         FIG. 6  is a diagram that describes a short-to-power-supply-voltage condition during a switch-on period; 
         FIG. 7  is a diagram illustrating a configuration example of an output abnormality detection circuit; 
         FIG. 8  is a diagram illustrating a configuration example of a gate driver; 
         FIG. 9  is a diagram illustrating an example of a load-open condition detection operation; 
         FIG. 10  is a diagram illustrating an example of a short-to-power-supply-voltage condition detection operation; and 
         FIG. 11  is an external view of a vehicle illustrating a configuration example of the vehicle. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     &lt;Semiconductor Integrated Circuit Device&gt; 
       FIG. 1  is a diagram illustrating an entire configuration example of a semiconductor integrated circuit device. A semiconductor integrated circuit device  1  in this configuration example is a high-side switch LSI (a kind of in-vehicle IPD) that conducts/cuts off between a load  3  and an application node of a power supply voltage VBB according to an instruction from an electronic control unit (ECU)  2 . 
     Here, the semiconductor integrated circuit device  1  includes external terminals T 1  to T 5  as sections for establishing electric coupling to an outside of the device. The external terminal T 1  is a power supply terminal (VBB pin) for receiving a supply of the power supply voltage VBB (for example, 12 V) from an unillustrated battery. The external terminal T 2  is a load couple terminal or an output terminal (OUT pin) for being externally coupled to the load  3  (a valve lamp, a relay coil, a solenoid, a light emitting diode, a motor, or the like). The external terminal T 3  is a signal input terminal (IN pin) for receiving an external input of an external control signal Si from the ECU  2 . The external terminal T 4  is a signal output terminal (FAIL pin) for externally outputting an output abnormality report signal FAIL to the ECU  2 . The external terminal T 5  is a signal output terminal (SENSE pin) for externally outputting an output current detection signal SENSE to the ECU  2 . In addition, an external sense resistor  4  is coupled between the external terminal T 5  and a ground node at the outside of the device. 
     Further, the semiconductor integrated circuit device  1  includes an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET)  10 , an output current monitoring section  20 , a gate control section  30 , a control logic section  40 , a signal input section  50 , an internal power supply section  60 , an abnormality protection section  70 , and an output current detection section  80 , these sections being integrated in the semiconductor integrated circuit device  1 . 
     The NMOSFET  10  is a high voltage tolerance power transistor (its voltage tolerance being, for example, 42 V) with its drain node coupled to the external terminal T 1  and its source node coupled to the external terminal T 2 . The NMOSFET  10  coupled in this way functions as a switch element (high-side switch) for conducting/cutting off a current path extending from the application node of the power supply voltage VBB to the ground node via the load  3 . In addition, the NMOSFET  10  is turned on when a gate drive signal G 1  is at a high level and is turned off when the gate drive signal G 1  is at a low level. 
     Further, for the NMOSFET  10 , its elements may be designed such that its turn-on resistance Ron is equal to several tens of mΩ. In this regard, however, the lower the turn-on resistance Ron is, the more likely to flow an overcurrent is and the more likely to occur an abnormal heat generation is when a short-to-ground condition (an abnormal condition in which a short circuit to a ground node or a low electric potential node equivalent thereto is occurring) is occurring at the external terminal T 2 . Thus, the further the turn-on resistance Ron of the NMOSFET  10  is decreased, the higher the importance of each of an overcurrent protection circuit  71  and a temperature protection circuit  73 , which will be described later, is. 
     The output current monitoring section  20  includes NMOSFETs  21  and  22  and a sense resistor  23  and generates a sense voltage Vs (corresponding to the sense signal) according to an output current Io flowing through the NMOSFET  10 . 
     The NMOSFETs  21  and  22  are mirror transistors coupled in parallel to the NMOSFET  10  and generate sense currents Is and Is 2  according to the output current Io. A ratio of the size of the NMOSFET  10  relative to the size of each of the NMOSFETs  21  and  22  is represented by m:1 (m&gt;1). Thus, each of the sense currents Is and Is 2  has a decreased magnitude equal to 1/m of the magnitude of the output current Io. In addition, just like the NMOSFET  10 , the NMOSFETs  21  and  22  are turned on when the gate drive signal G 1  is at the high level and are turned off when the gate drive signal G 1  is at the low level. 
     The sense resistor  23  (its resistance value: Rs) is coupled between a source node of the NMOSFET  21  and the external terminal T 2  and is a current-to-voltage conversion element for generating the sense voltage Vs according to the sense current Is (Vs=Is×Rs+Vo, Vo being an output voltage that appears at the external terminal T 2 ). 
     The gate control section  30  generates the gate drive signal G 1  resulting from enhancing the electric current ability of a gate control signal S 1  and outputs the gate drive signal G 1  to the gate node of the NMOSFET  10  (further to gate nodes of the NMOSFETs  21  and  22 ), to thereby perform turn-on/off control of the NMOSFET  10 . Here, the gate control section  30  includes a function of controlling the NMOSFET  10  so as to cause the output current Io to be limited according to an overcurrent protection signal S 71 . Further, the gate control section  30  also includes a function of controlling the turn-on resistance Ron of the NMOSFET  10  (involving its drain-source voltage Vds) according to an output abnormality detection signal S 72  (specifically, a turn-on resistance control signal S 72   b  described later). 
     The control logic section  40  receives supply of an internal power supply voltage Vreg and generates the gate control signal S 1 . When the external control signal Si is, for example, at a high level (logical level when the NMOSFET  10  is turned on), the internal power supply voltage Vreg is supplied from the internal power supply section  60  to the control logic section  40 , and thus, the control logic section  40  is in an operation state, thereby causing the gate control signal S 1  to be at a high level (=Vreg). On the other hand, when the external control signal Si is at a low level (logical level when the NMOSFET  10  is turned off), the internal power supply voltage Vreg is not supplied from the internal power supply section  60  to the control logic section  40 , and thus, the control logic section  40  is in a non-operation state, thereby causing the gate control signal S 1  to be at a low level (=GND). Further, the control logic section  40  monitors various output signals of the abnormality protection section  70 . Particularly, the control logic section  40  also includes a function of generating the output abnormality report signal FAIL according to the result of the monitoring of the output abnormality detection signal S 72  (specifically, an output abnormality detection signal S 72   a  and a determination signal S 72   c , which will be described later). 
     The signal input section  50  is a Schmitt trigger for receiving the input of the external control signal Si from the external terminal T 3  and transmitting a resultant signal to the control logic section  40  and the internal power supply section  60 . Here, the external control signal Si is set to, for example, a high level when the NMOSFET  10  is turned on and a low level when the NMOSFET  10  is turned off. 
     The internal power supply section  60  generates a predetermined internal power supply voltage Vreg from the power supply voltage VBB and supplies the internal power supply voltage Vreg to individual portions of the semiconductor integrated circuit device  1 . Here, the operation state/non-operation state of the internal power supply section  60  is controlled according to the external control signal Si. More specifically, the internal power supply section  60  is in the operation state when the external control signal Si is at a high level and is in the non-operation state when the external control signal Si is at a low level. 
     The abnormality protection section  70  is a circuit block for detecting various abnormal conditions of the semiconductor integrated circuit device  1  and includes the overcurrent protection circuit  71 , an output abnormality detection circuit  72 , the temperature protection circuit  73 , and a voltage lowering protection circuit  74 . 
     The overcurrent protection circuit  71  generates an overcurrent protection signal S 71  according to the result of monitoring of the sense voltage Vs (namely, monitoring as to whether or not an overcurrent abnormal condition of the output current Io is occurring). Here, the overcurrent protection signal S 71  is set to, for example, a low level when the abnormal condition is not detected and a high level when the abnormal condition is detected. 
     The output abnormality detection circuit  72  monitors the output voltage Vo and the output current detection signal SENSE to detect whether or not a load-open condition or a short-to-power-supply-voltage condition is occurring at the output terminal T 2 . Here, the short-to-power-supply-voltage condition is an abnormal condition in which a short circuit to an application node of the power supply voltage VBB or a high electric potential node equivalent thereto is occurring. Further, the output abnormality detection circuit  72  generates the output abnormality detection signal S 72  according to the result of the detection. Here, the output abnormality detection signal S 72  includes the output abnormality detection signal S 72   a , the turn-on resistance control signal S 72   b , and the determination signal S 72   c , the details of these signals being described later. In addition, the output abnormality detection signal S 72   a  is set to, for example, a low level when the abnormal condition is not detected and a high level when the abnormal condition is detected. 
     The temperature protection circuit  73  includes a temperature detection element (not illustrated) for detecting an abnormal heat generation condition in the semiconductor integrated circuit device  1  (particularly, in the vicinity of the NMOSFET  10 ) and generates a temperature protection signal S 73  according to the result of the detection (namely, according to whether or not the abnormal heat generation condition is occurring). Here, the temperature protection signal S 73  is set to, for example, a low level when the abnormal condition is not detected and a high level when the abnormal condition is detected. 
     The voltage lowering protection circuit  74  generates a voltage lowering protection signal S 74  according to the result of monitoring of the power supply voltage VBB or the internal power supply voltage Vreg (namely, according to whether or not an abnormal voltage lowering condition is occurring). Here, the voltage lowering protection signal S 74  is set to, for example, a low level when the abnormal condition is not detected and a high level when the abnormal condition is detected. 
     The output current detection section  80  generates the sense current Is 2  (=Io/m) according to the output current Io by causing the source voltage of the NMOSFET  22  to coincide with the output voltage Vo using an unillustrated bias section, and outputs the sense current Is 2  to the external terminal T 5 . Thus, the output current detection signal SENSE resulting from a current-to-voltage conversion of the sense current Is 2  using the external sense resistor  4  (its resistance value: R 4 ) is transmitted to the ECU  2 . At this time, the output current detection signal SENSE is represented by Is 2 ×R 4 . The larger the output current Io is, the higher the output current detection signal SENSE is, and the smaller the output current Io is, the lower the output current detection signal SENSE is. Here, in the case where an electric current value of the output current Io is to be read from the output current detection signal SENSE, it is sufficient if an analog-to-digital (A/D) conversion of the output current detection signal SENSE is implemented in the ECU  2 . 
     &lt;Gate Control Section&gt; 
       FIG. 2  is a diagram illustrating a configuration example of the gate control section  30 . The gate control section  30  of  FIG. 2  includes a gate driver  31 , an oscillator  32 , a charge pump  33 , a clamper  34 , an NMOSFET  35 , a resistor  36  (its resistance value: R 36 ), a capacitor  37  (its capacitance value: C 37 ), and a Zennor diode  38 . 
     The gate driver  31  is coupled between an output node of the charge pump  33  (application node of a boosted voltage VG) and the external terminal T 2  (application node of the output voltage Vo) and generates the gate drive signal G 1  resulting from the enhancement of the electric current ability of the gate control signal S 1 . Here, the gate drive signal G 1  is set to, for example, a high level (=VG) when the gate control signal S 1  is at a high level, and a low level (=Vo) when the gate control signal S 1  is at a low level. 
     Further, the gate driver  31  also includes a function of controlling the gate drive signal G 1  so as to cause the turn-on resistance Ron of the NMOSFET  10  (involving the drain-source voltage Vds) to vary according to the output abnormality protection signal S 72  (particularly, the turn-on resistance control signal S 72   b ). 
     The oscillator  32  generates a clock signal CLK having a predetermined frequency and outputs the clock signal CLK to the charge pump  33 . Here, the operation/non-operation of the oscillator  32  is controlled according to an enable signal Sa from the control logic section  40 . 
     The charge pump  33  is an example of a voltage booster that generates a boosted voltage VG higher than the power supply voltage VBB by driving a flying capacitor using the clock signal CLK and supplies the boosted voltage VG to the gate driver  31 . Here, the operation/non-operation of the charge pump  33  is controlled according to an enable signal Sb from the control logic section  40 . 
     The clamper  34  is coupled between the external terminal T 1  (application node of the power supply voltage VBB) and the gate node of the NMOSFET  10 . In an application in which a load  3  having inductivity is coupled to the external terminal T 2 , when the NMOSFET  10  is switched from its on-state to its off-state, the output voltage Vo may be caused to fall to a negative voltage (&lt;GND) by a back electromotive force of the load  3 . For this reason, the clamper  34  (what is called an active clamp circuit) is provided for absorbing the energy of the back electromotive force. 
     A drain node of the NMOSFET  35  is coupled to the gate node of the NMOSFET  10 . A source node of the NMOSFET  35  is coupled to the external terminal T 2 . A gate node of the NMOSFET  35  is coupled to an application node of the overcurrent protection signal S 71 . Further, the resistor  36  and the capacitor  37  are coupled in series between the drain node and the gate node of the NMOSFET  35 . 
     A cathode of the Zennor diode  38  is coupled to the gate node of the NMOSFET  10 . An anode of the Zennor diode  38  is coupled to the source node of the NMOSFET  10 . The Zennor diode  38  coupled in this way functions as a clamp element that limits a gate-source voltage (=VG−Vo) of the NMOSFET  10  to a predetermined value or less. 
     In the gate control section  30  in the present configuration example, when the overcurrent protection signal S 71  is set to a high level, the gate drive signal G 1  is caused to fall with a predetermined time constant τ (=R 36 ×C 37 ) from a stationary state high level (=VG). As a result, the conductivity of the NMOSFET  10  is gradually decreased, and thus, a limitation applied to the output current Io is gradually increased. On the other hand, when the overcurrent protection signal S 71  is set to a low level, the gate drive signal G 1  is caused to rise with the predetermined time constant τ. As a result, the conductivity of the NMOSFET  10  is gradually increased, and thus, the limitation applied to the output current Io is gradually decreased. 
     In this way, the gate control section  30  in the present configuration example includes the function of controlling the gate drive signal G 1  so as to cause the output current Io to be limited according to the overcurrent protection signal S 71 . 
     &lt;Output Current Detection Section&gt; 
       FIG. 3  is a diagram illustrating a configuration example of the output current detection section  80 . The output current detection section  80  in this configuration example includes an amplifier  81  and a p-type MOSFET (PMOSFET)  82 . 
     An inversion input node (−) of the amplifier  81  is coupled to the source node of the NMOSFET  10  (further to the external terminal T 2 ). A non-inversion input node (+) of the amplifier  81  and a source node of the PMOSFET  82  are coupled to the source node of the NMOSFET  22 . An output node of the amplifier  81  is coupled to a gate node of the PMOSFET  82 . A drain node of the PMOSFET  82  is coupled to the external sense resistor  4  via the external terminal T 5 . 
     The amplifier  81  and the PMOSFET  82  coupled in this way function as a bias section that causes the source voltage of the NMOSFET  22  to coincide with the output voltage Vo. Thus, the output current detection section  80  is capable of accurately generating the sense current Is 2  (=Io/m) according to the output current Io. 
     &lt;Further Study Regarding Output Abnormal Conditions&gt; 
       FIGS. 4, 5, and 6  are diagrams that respectively describe a short-to-ground condition, a load-open condition, and a short-to-power-supply-voltage condition, during a switch-on period (turn-on period of the NMOSFET  10 ). 
     When the short-to-ground condition occurs at the output terminal T 2  during the turn-on period of the NMOSFET  10 , as illustrated in  FIG. 4 , the output voltage Vo becomes substantially equal to the ground electric potential GND, and an extremely large amount of the output current Io flows through the NMOSFET  10 . That is, the output current Io is brought to an overcurrent state. Thus, satisfaction of conditions represented by Vo≈GND and S 71 =H (logical level when the overcurrent is detected) makes it possible to determine that the short-to-ground condition is occurring at the output terminal T 2 . 
     On the other hand, when the load-open condition occurs at the output terminal T 2  during the turn-on period of the NMOSFET  10 , as illustrated in  FIG. 5 , a current path from the NMOSFET  10  to the load  3  is cut off. Thus, only a slight amount of the output current Io flows through the NMOSFET  10 . At this time, the slight amount of output current Io is determined by a resistance element Rx (&gt;&gt;Ron) of internal circuits coupled to the source node of the NMOSFET  10 , and is represented by VBB/(Ron+Rx). As a result, the output voltage Vo (=VBB−Ron×Io) becomes substantially equal to the power supply voltage VBB. 
     Further, when the short-to-power-supply-voltage condition occurs at the output terminal T 2  during the turn-on period of the NMOSFET  10 , as illustrated in  FIG. 6 , a short-circuit path directly coupled between an application node of the power supply voltage VBB and the load  3  is formed. At this time, a resistance element Ry of the short-circuit path is significantly small (Ry=several mΩ to several tens of mΩ). Thus, most of a current flowing from the application node of the power supply voltage VBB to the load  3  flows through the above short-circuit path as a short-to-power-supply-voltage current Ivbbs, and thus, almost no output current Io flows through the NMOSFET  10 . As a result, the output voltage Vo (=VBB−Ry×Ivbbs) becomes substantially equal to the power supply voltage VBB. 
     As described above, when the load-open condition or the short-to-power-supply-voltage condition is occurring at the output terminal T 2  during the turn-on period of the NMOSFET  10 , in both cases, the output voltage Vo becomes substantially equal to the power supply voltage VBB (namely, Vo≈VBB). For this reason, simple monitoring of the output voltage Vo does not make it possible to determine which of the load-open condition and the short-to-power-supply-voltage condition the abnormal condition occurring at the external terminal T 2  is. 
     In view of the result of the above further study, in the following, the output abnormality detection circuit  72  is proposed which detects an output abnormal condition during the turn-on period of the NMOSFET  10  and is capable of determining which of the load-open condition and the short-to-power-supply-voltage condition the output abnormal condition is. 
     &lt;Output Abnormality Detection Circuit&gt; 
       FIG. 7  is a diagram illustrating a configuration example of the output abnormality detection circuit  72 . The output abnormality detection circuit  72  in this configuration example includes comparators  72   a  to  72   c , resistors  72   d  and  72   e , and current sources  72   f  and  72   g . Note that already-described components will be denoted by reference signs similar to those of the components, and thereby, duplicate descriptions thereof will be omitted. 
     The comparator  72   a  (corresponding to the first comparator) compares the output current detection signal SENSE that is input to its inversion input node (−) with a threshold voltage VTH that is input to its non-inversion input node (+) to generate the output abnormality detection signal S 72   a . The output abnormality detection signal S 72   a  is set to a low level (logical level when the output abnormality is not detected) when a condition represented by SENSE&gt;VTH is satisfied, and a high level (logical level when the output abnormality is detected) when a condition represented by SENSE&lt;VTH is satisfied. 
     Specifically, when the load-open condition or the short-to-power-supply-voltage condition is occurring at the external terminal T 2 , almost no output current Io flows through the NMOSFET  10  (see  FIG. 5  or  FIG. 6  described above). Thus, the condition represented by SENSE&lt;VTH is satisfied, and the output abnormality detection signal S 72   a  is set to a high level (S 72   a =H). In this regard, however, merely monitoring the output abnormality detection signal S 72   a  does not make it possible to distinguish which of the load-open condition and the short-to-power-supply-voltage condition is occurring. 
     Here, the threshold value VTH may be a fixed value or a variable value. In the case where the threshold value VTH is a variable value, for example, an external terminal is preferably prepared, to which an appropriately predetermined analog voltage is externally input as the threshold voltage VTH. 
     Further,  FIG. 7  illustrates an example in which the output current detection signal SENSE is input to the comparator  72   a , but the sense voltage Vs may be input thereto instead of the output current detection signal SENSE. 
     The comparator  72   b  (corresponding to the second comparator) operates upon receipt of the application of the power supply voltage VBB and a reference voltage VBBM 5  (=VBB−5 V), and compares the output voltage Vo that is input to the inversion input node (−) with a first voltage VBB−V 1  that is input to the non-inversion input node (+) to generate the turn-on resistance control signal S 72   b . The turn-on resistance control signal S 72   b  is set to a low level (logical level when the turn-on resistance Ron is increased) when a condition represented by Vo&gt;VBB−V 1  is satisfied, and to a high level (logical level when the turn-on resistance Ron is not increased) when a condition represented by Vo&lt;VBB−V 1  is satisfied. 
     Further, the comparator  72   b  is enable-controlled according to the output abnormality detection signal S 72   a . More specifically, the comparator  72   b  is in a disabled state (non-operation state) when the output abnormality detection signal S 72   a  is at a low level (S 72   a =L), and is in an enabled state (operation state) when the output abnormality detection signal S 72   a  is at a high level (S 72   a =H). 
     Here, the gate driver  31  controls the gate drive signal G 1  so as to cause the turn-on resistance Ron of the NMOSFET  10  (involving the drain-source voltage Vds) to vary according to the turn-on resistance control signal S 72   b.    
       FIG. 8  is a diagram illustrating a configuration example of the gate driver  31 . The gate driver  31  in this configuration example includes a source-current source  311  and a sink-current source  312  that form an output stage of the gate driver  31 , and a controller  313  that controls these current sources. 
     The source-current source  311  is coupled between an application node of the booted voltage VG and an application node of the gate drive signal G 1 . When the gate drive signal G 1  is set to a high level (=VG), the source-current source  311  is turned on to cause a source current IH (upper-side gate drive current) to flow into the application node of the gate drive signal G 1 . 
     The sink-current source  312  is coupled between the application node of the gate drive signal G 1  and the external terminal T 2  (application node of the output voltage Vo). When the gate drive signal G 1  is set to a low level (=Vo), the sink-current source  312  is turned on to draw a sink current IL (lower-side gate drive current) from the application node of the gate drive signal G 1 . 
     The controller  313  performs control of turning on/off each of the source current IH and the sink current IL by controlling the source-current source  311  and the sink-current source  312  according to the gate control signal S 1 . For example, when the gate control signal S 1  is at a high level, the controller  313  sets the gate drive signal G 1  to a high level (=VG) by turning on the source current IH and turning off the sink current IL. On the other hand, when the gate control signal S 1  is at a low level, the controller  313  sets the gate drive signal G 1  to a low level (=Vo) by turning off the source current IH and turning on the sink current IL. 
     Moreover, the sink current IL is turned on/off according to the turn-on resistance control signal S 72   b . More specifically, when the turn-on resistance control signal S 72   b  is at a high level (S 72   b =H), the sink current IL is turned on even during the turn-on period of the NMOSFET  10  (which normally is a period during which the sink current IL is to be turned off). As a result, the gate drive signal G 1  is decreased from the high level (=VG), and thus, the turn-on resistance Ron of the NMOSFET  10  is increased from its normal value. On the other hand, when the turn-on resistance control signal S 72   b  is at a low level (S 72   b =L), the sink current IL is turned off, and thus, the turn-on resistance Ron is returned to its normal value. 
     As described above, when the comparator  72   b  is in the enabled state (S 72   a =H), the turn-on/off control of the sink current IL according to the turn-on resistance control signal S 72   b  is performed. As a result, during the turn-on period of the NMOSFET  10 , the turn-on resistance Ron of the NMOSFET  10  is controlled so as to cause the output voltage Vo to coincide with the first voltage VBB−V 1 . 
     Returning to  FIG. 7 , the detail description of the configuration and operation of the output abnormality detection circuit  72  will be continued. 
     The comparator  72   c  (corresponding to the third comparator) operates upon receipt of the application of the power supply voltage VBB and the reference voltage VBBM 5  (=VBB−5 V), and compares the output voltage Vo that is input to the non-inversion input node (+) with a second voltage VBB−V 2  (&gt;VBB−V 1 ) that is input to the inversion input node (−) to generate the determination signal S 72   c . The determination signal S 72   c  is set to a low level (logical level when the load-open condition is occurring) when a condition represented by Vo&lt;VBB−V 2  is satisfied, and to a high level (logical level when the short-to-power-supply-voltage condition is occurring) when a condition represented by Vo&gt;VBB−V 2  is satisfied. 
     Further, the comparator  72   c  is enable-controlled according to the output abnormality detection signal S 72   a , just like the above-described comparator  72   b . More specifically, the comparator  72   c  is in a disabled state (non-operation state) when the output abnormality detection signal S 72   a  is at a low level (S 72   a =L), and is in an enabled state (operation state) when the output abnormality detection signal S 72   a  is at a high level (S 72   a =H). 
     The resistor  72   d  (corresponding to the first resistor) is coupled between the external terminal T 1  and an application node of the first voltage VBB−V 1 . The current source  72   f  (corresponding to the first current source) is coupled between the application node of the first voltage VBB−V 1  and a node of a constant electric potential (=VBBM 5 ). The resistor  72   d  (its resistance value: Rd) and the current source  72   f  (its current value: If), coupled in such a way as described above, generate, at a node therebetween, the first voltage VBB−V 1 , which is lower than the power supply voltage VBB by a predetermined voltage V 1  (=Rd×If). 
     The resistor  72   e  (corresponding to the second resistor) is coupled between the external terminal T 1  and an application node of the second voltage VBB−V 2 . The current source  72   g  (corresponding to the second current source) is coupled between the application node of the second voltage VBB−V 2  and the node of the constant electric potential (=VBBM 5 ). The resistor  72   e  (its resistance value: Re) and the current source  72   g  (its current value: Ig), coupled in such a away as described above, generate, at a node therebetween, the second voltage VBB−V 2 , which is lower than the power supply voltage VBB by a predetermined voltage V 2  (=Re×Ig, V 2 &lt;V 1 ). 
     Note that  FIG. 7  illustrates an example in which the first current source  72   f  and the second current source  72   g  constantly operate, but a configuration may be employed in which, just like the comparators  72   b  and  72   c , the first current source  72   f  and the second current source  72   g  are enable-controlled according to the output abnormality detection signal S 72   a . In this case, the first current source  72   f  and the second current source  72   g  each may be in a disabled state (non-operation state) when the output abnormality detection signal S 72   a  is at a low level (S 72   a =L), and be in an enabled state (operation state) when the output abnormality detection signal S 72   a  is at a high level (S 72   a =H). 
     The output abnormality detection circuit  72  in the present configuration example makes it possible to, when the output current Io flowing during the turn-on period of the NMOSFET  10  is smaller than a threshold value (SENSE&lt;VTH), detect an occurrence of an output abnormal condition, and increase the turn-on resistance Ron of the NMOSFET  10  to determine which of the load-open condition and the short-to-power-supply-voltage condition is occurring at the external terminal T 2  on the basis of the output voltage Vo. 
     More specifically, the output abnormality detection circuit  72  compares the output voltage Vo with the second voltage VBB−V 2 , and is capable of determining that the load-open condition is occurring when a condition represented by Vo&lt;VBB−V 2  is satisfied, and of determining that the short-to-power-supply-voltage condition is occurring when a condition represented by Vo&gt;VBB−V 2  is satisfied. 
     In the following, an output abnormality detection operation (a determination operation for each of the load-open condition and the short-to-power-supply-voltage condition) will be described in detail referring to  FIGS. 9 and 10 . 
     &lt;Output Abnormality Detection Operation (Determination Operation for Load-Open Condition and Short-to-Power-Supply-Voltage Condition)&gt; 
       FIG. 9  is a diagram illustrating an example of a load-open condition detection operation.  FIG. 9  depicts, in order from its top side, the output current detection signal SENSE, the output voltage Vo, the output abnormality detection signal S 72   a , the turn-on resistance control signal S 72   b , and the determination signal S 72   c.    
     Before time t 1 , the load-open condition is not occurring at the external terminal T 2 , and the output current Io is appropriately flowing through the fully turned-on NMOSFET  10 . Thus, the output current detection signal SENSE is higher than the threshold voltage VTH. Further, the output voltage Vo is equal to a voltage VBB−V 0 , which is lower than the power supply voltage VBB by a drain-source voltage V 0  of the NMOSFET  10  (V 0 =Io×Ron 0 , Ron 0  being a turn-on resistance of the fully turned-on NMOSFET  10 ). 
     Further, before the time t 1 , a condition represented by SENSE&gt;VTH is satisfied, and thus, a condition represented by S 72   a =L (logical level when the output abnormality is not detected) is satisfied. Thus, each of the turn-on resistance control signal S 72   b  and the determination signal S 72   c  is in a disabled state (for example, a high impedance state). 
     Upon occurrence of a load-open condition at the external terminal T 2  at the time t 1 , a situation in which almost no output current Io flows through the NMOSFET  10  (see  FIG. 5  described above) arises. Thus, the output current detection signal SENSE becomes lower than the threshold voltage VTH. 
     At this time, a condition represented by S 72   a =H (logical level when the output abnormality is detected) is satisfied, and thus, the comparator  72   b  is brought to the enabled state. Accordingly, after the time t 1 , the turn-on resistance Ron of the NMOSFET  10  (involving the drain-source voltage Vds) is controlled according to the turn-on resistance control signal S 72   b.    
     Note that in the case where the load-open condition is occurring at the external terminal T 2 , the output voltage Vo (=VBB−Ron×Io) can be changed to any target voltage by controlling the turn-on resistance Ron of the NMOSFET  10 . For example, in  FIG. 9 , the output voltage Vo is adjusted so as to coincide with the first voltage VBB−V 1  (&lt;VBB−V 0 ) by increasing the turn-on resistance Ron of the NMOSFET  10  from the turn-on resistance Ron 0 , which is the turn-on resistance of the fully turned-on NMOSFET  10 . 
     Further, upon satisfaction of the condition represented by S 72   a =H (logical level when the output abnormality is detected), the comparator  72   c  is also brought to the enabled state. Thus, after the time t 1 , the determination signal S 72   c  according to the result of the comparison of the output voltage Vo with the second voltage VBB−V 2  is output. According to  FIG. 9 , a condition represented by Vo (=VBB−V 1 )&lt;VBB−V 2  is satisfied, and thus, the determination signal S 72   c  is set to a low level. 
     In this way, when conditions represented by S 72   a =H and S 72   c =L are satisfied, a determination that the load-open condition is occurring at the external terminal T 2  can be made. 
       FIG. 10  is a diagram illustrating an example of a short-to-power-supply-voltage condition detection operation.  FIG. 10  depicts, in order from its top side, the output current detection signal SENSE, the output voltage Vo, the output abnormality detection signal S 72   a , the turn-on resistance control signal S 72   b , and the determination signal S 72   c , just like in  FIG. 9  described above. 
     Before time t 2 , the short-to-power-supply-voltage condition is not occurring at the external terminal T 2  and the output current Io is appropriately flowing through the fully turned-on NMOSFET  10 . Thus, the output current detection signal SENSE is higher than the threshold voltage VTH. Further, the output voltage Vo is equal to the voltage VBB−V 0 , which is lower than the power supply voltage VBB by the drain-source voltage V 0  of the NMOSFET  10 . 
     Further, before the time t 2 , the condition represented by SENSE&gt;VTH is satisfied, and thus, the condition represented by S 72 =L (logical level when the output abnormality is not detected) is satisfied. Accordingly, each of the turn-on resistance control signal S 72   b  and the determination signal S 72   c  is in the disabled state (for example, the high impedance state). As described above, as a matter of course, the behavior before the time t 2  is exactly the same as that before the time t 1  in  FIG. 9 . 
     Upon occurrence of the short-to-power-supply-voltage condition at the external terminal T 2  at the time t 2 , a situation in which almost no output current Io flows through the NMOSFET  10  (see  FIG. 6  described above) arises. Thus, the output current detection signal SENSE becomes lower than the threshold voltage VTH. 
     At this time, the condition represented by S 72   a =H (logical level when the output abnormality is detected) is satisfied, and thus, the comparator  72   b  is brought to the enabled state. Accordingly, after the time t 2 , the turn-on resistance Ron of the NMOSFET  10  (involving the drain-source voltage Vds) is controlled according to the turn-on resistance control signal S 72   b.    
     In this regard, however, in the case in which the short-to-power-supply-voltage condition is occurring at the external terminal T 2 , the output voltage Vo does not depend on the turn-on resistance Ron of the NMOSFET  10  and is determined by external factors (refer to the resistance element Ry of the short-circuit path and the short-to-power-supply-voltage current Ivbbs in  FIG. 6 ). Specifically, the output voltage Vo becomes substantially equal to the power supply voltage VBB. At this time, the turn-on resistance control signal S 72   b  remains fixed to a low level (logical level when the turn-on resistance Ron is increased). 
     Further, upon satisfaction of the condition represented by S 72   a =H (logical level when the output abnormality is detected), the comparator  72   c  is also brought to an enabled state. Thus, after the time t 2 , the determination signal S 72   c  according to the result of the comparison of the output voltage Vo with the second voltage VBB−V 2  is output. According to  FIG. 10 , a condition represented by Vo (≈VBB)&gt;VBB−V 2  is satisfied, and thus, the determination signal S 72   c  becomes a high level. 
     In this way, when conditions represented by S 72   a =H and S 72   c =H are satisfied, a determination that the short-to-power-supply-voltage condition is occurring at the external terminal T 2  can be made. 
     Note that, if the NMOSFET  10  is in its turn-off period, the determination as to which of the load-open condition and the short-to-power-supply-voltage condition is occurring can be easily made on the basis of the output voltage Vo. However, when such a sequence is employed that, upon receipt of rising of the output abnormality detection signal S 72   a  to the high level (logical level when the output abnormality is detected), the NMOSFET  10  is fully turned off and then the determination as to which of the load-open condition and the short-to-power-supply-voltage condition is occurring is started anew, it takes a long time (for example, several hundreds of μs) to obtain the result of the determination. 
     In contrast, employing the above-described output abnormality detection circuit  72  makes it possible to, after the detection of the output abnormal condition (S 72   a =H), promptly determine which of the load-open condition and the short-to-power-supply-voltage condition is occurring, without waiting for the completion of the full turn-off of the NMOSFET  10 . Accordingly, the safety of an electronic device (in-vehicle device) in which the semiconductor integrated circuit device  1  is mounted can be enhanced. 
     In addition, the control logic section  40  is capable of reporting, to the ECU  2 , a current condition determined from among conditions, namely, a normal condition, the short-to-ground condition, the load-open condition, and the short-to-power-supply-voltage condition, using, for example, a prepared output abnormality report signal FAIL including two bits indicating “00,” “01,” “10,” and “11” corresponding to the respective conditions. 
     &lt;Application to Vehicle&gt; 
       FIG. 11  is an external view of a vehicle illustrating a configuration example of the vehicle. A vehicle X in this configuration example mounts a battery (not illustrated in  FIG. 11 ) and various kinds of electronic devices X 11  to X 18  that operate by receiving supply of electric power from the battery. Note that mounted positions of the electronic devices X 11  to X 18  in  FIG. 11  may be different from actual positions for convenience of illustration. 
     The electronic device X 11  is an engine control unit that performs various kinds of control in relation to an engine, such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto cruise control. 
     The electronic device X 12  is a lamp control unit that performs turn-on/off control of each of lamps, such as a high intensity discharged lamp (HID) and a daytime running lamp (DRL). 
     The electronic device X 13  is a transmission control unit that performs control in relation to a transmission. 
     The electronic device X 14  is a body control unit that performs various kinds of control in relation to travel of the vehicle X, such as anti-lock brake system (ABS) control, electric power steering (EPS) control, and electronic suspension control. 
     The electronic device X 15  is a security control unit that performs drive control of each of a door lock, a burglar alarm, and the like. 
     The electronic device X 16  is an electronic device that is mounted into the vehicle X as standard equipment or a manufacturer&#39;s option product at the stage of factory shipping, and examples of this electronic device X 16  include, but are not limited to, a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat. 
     The electric device X 17  is an electric device that is optionally mounted in the vehicle X as a user&#39;s option product, and examples of this electronic device X 17  include, but are not limited to, in-vehicle audio/visual (A/V) equipment, a car navigation system, an electronic toll collection system (ETC). 
     The electronic device X 18  is an electronic device including a high voltage tolerance motor, and examples of this electronic device X 18  include, but are not limited to, an in-vehicle blower, an oil pump, a water pump, a battery cooling fan. 
     Note that the semiconductor integrated circuit device  1 , the ECU  2 , and the load  3 , which have been described above, can be mounted in any one of the electronic devices X 11  to X 18 . 
     &lt;Other Modification Examples&gt; 
     In the above embodiment, the in-vehicle high-side switch LSI has been described as an example, but application targets of the disclosure in the present specification is not limited to the in-vehicle high-side switch LSI, and the disclosure can widely be applied to high-side switch LSIs other than the in-vehicle high-side switch LSI. 
     Further, not only the above-described embodiment but also the various technical features disclosed in the present specification can be modified in various ways within the scope not departing from the gist of the technical creation thereof. That is, it should be considered that the above-described embodiment is just an example and is not restrictive in all respects. Further, the technical scope of the present disclosure is indicated not by the description of the above embodiment but by the claims, and is to be understood as including meanings equivalent to the claims, and all modifications belonging within the claims. 
     The disclosure in the present specification can be used in an in-vehicle IPD and the like.