Patent Publication Number: US-6906477-B2

Title: Linear control device for controlling a resistive and/or an inductive and/or a capacitive load

Description:
BACKGROUND OF THE INVENTION 
   A. Field of the Invention 
   The invention relates to an energy savings device or method that can be applied to a resistive, an inductive, or a capacitive load regardless of the respective impedance or inductance or capacitance of the load. More particularly, the invention relates to a linear control dimming device that is mounted in series with a resistive, an inductive or a capacitive load and that has access for power and operation to one side of an electrical line supplied to the load. A fluorescent light fixture or a motor for a fan or other device, for example, can be controlled by way of the linear control device or method according to the invention. 
   B. Description of the Related Art 
   The ability to control illumination levels is strongly desired, especially due to the rising energy costs. Such ability to control illumination levels is very important for establishments that require a great deal of lighting, such as restaurants and offices. 
   Lighting levels that are higher than necessary not only result in a higher energy costs associated with the lighting, but also can increase air conditioning costs due to the excess heat provided by the lighting fixtures. Fluorescent light fixtures output less heat than incandescent light fixtures for equivalent illumination, and thus they are becoming more popular with offices or other commercial establishments. 
   There currently exist various types of dimmer devices that can be used in order to control the amount of light output by fluorescent lights. One type utilizes a complex electronic ballast which first converts the applied AC line voltage to DC, then switches the applied tube voltage at high frequency. The resulting power-to-light output efficiency is hampered by this additional manipulation. This type requires an expensive fixture replacement and rewiring to the wall switch. Simplistic phase control devices will not provide satisfactory results when controlling a magnetic ballast fluorescent fixture. 
     FIG. 1A  shows the connections of a conventional fluorescent dimmer device or controller  100 , which is provided between a line and a load. The load is shown as a light fixture  110 , which may be a fluorescent tube and associated ballast, for example. As shown in  FIG. 1A , the conventional controller  100  needs access to both sides (line  102  and neutral  104 ) of an AC power input, in addition to the load. Since connectivity to the neutral line  104  is not always available at a light switch box, conventional fluorescent controllers may require expensive re-wiring to be installed. 
   The problem with using such a conventional dimmer circuit for a fluorescent lighting fixture is that the conventional dimmer circuit cannot modulate reactive loads. Reactive loads react with the controller, thereby producing oscillations that then cause surges of voltage and current, which are both unpredictable and uncontrollable. With such control being applied to a fluorescent light fixture, the typical result is a non-harmonic type of flickering, which frequently takes the light from zero output to maximum output and to values in between. Such flickering is visually (and also audibly) discomforting, and may even be unhealthful to people who are near the flickering fluorescent light (for example, it may cause headaches due to having to view the undesirable light flickering). 
   As explained earlier, a controller such as the one shown in  FIG. 1A  can be used to control a fluorescent light without causing significant flickering, but such a controller requires fairly substantial installation costs, since they cannot be installed at a light switch box (where a neutral line is not typically provided), but rather have to be installed very close to the ballast (e.g., in the ceiling of a room, where a neutral line is provided). 
   U.S. Pat. No. 5,043,635 to Talbott et al. describes a two-line power control device for dimming fluorescent lights, which does not require to be coupled to a neutral line. Accordingly, the Talbott et al. device can in theory be installed at a light switch box. However, due to the analog structure and the various components described in the Talbott et al. device, such a device is very difficult to manufacture, and also such a device is very difficult to manufacture in a small size. Thus, it is not feasible to install such a device in a light switch box, given the bulkiness as well as the transformer configuration of the Talbott et al. device. 
   SUMMARY OF THE INVENTION 
   The present invention is directed to an apparatus and a method for controlling an amount of power supplied to a resistive, inductive or capacitive load by modulating a period of time that current flows through the load: 
   According to one aspect of the invention, there is provided an energy savings device for an inductive, resistive or capacitive load that is powered by an input AC voltage waveform. The device includes a setting unit configured to allow a user to set a desired power operating level for the load, and that outputs a setting signal as a result thereof. The device also includes a processor configured to receive the setting signal from the setting unit, and that determines a phase delay to be performed on an output AC voltage waveform that is to be provided to the load, wherein the processor outputs a control signal as a result thereof. The device further includes a switching linear control element that receives the control signal output from the processor, and that turns off and on at predetermined times in accordance with the control signal, so as to create the output AC voltage waveform as a chopped voltage wavefrom from the input AC voltage waveform. The device still further includes a bridge rectifier connected to the switching linear control element and disposed in a series connection between the load and a line that provides the input AC voltage waveform, wherein the bridge rectifier converts an AC current waveform from a bi-directional waveform to a unidirectional waveform for inputting to the switching linear control element. The output voltage waveform is provided to the load by way of the bridge rectifier. 
   According to another aspect of the invention, there is provided an energy savings method for an inductive, resistive, or capacitive load that is powered by an input AC voltage waveform. The method includes setting a desired power operating level for the load. The method also includes receiving, by a processor, a signal indicative of the desired power operating level for the load, and determining a phase delay to be performed on an output AC voltage waveform that is to be provided to the load, and to output a control signal as a result thereof. The method further includes, in response to the control signal, turning a switching linear control element off and on at predetermined times in accordance with the control signal, so as to create the output AC voltage waveform from the input AC voltage waveform. The method still further includes converting, by way of a bridge rectifier connected to the switching linear control element and disposed in a series connection between the load and a line that provides the input AC voltage waveform, an AC current waveform received on the line from a bi-directional waveform to a unidirectional waveform for inputting to the switching linear control element. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing advantages and features of the invention will become apparent upon reference to the following detailed description and the accompanying drawings, of which: 
       FIG. 1A  shows a hookup of a related energy savings device that is provided between an input voltage line and a load; 
       FIG. 1B  shows a hookup of a related energy savings device that is provided between an input voltage line and a load; 
       FIG. 2  shows an alternative hookup of a related energy savings device that provides neutral side control; 
       FIG. 3  is a block diagram of a first related energy savings device; 
       FIG. 4  is a schematic circuit diagram of the first related energy savings device; 
       FIG. 5  shows phase control waveforms according to the first related energy savings device; 
       FIG. 6  is a software flow diagram of microprocessor firmware that operates the first related energy savings device; 
       FIG. 7  is a block diagram of a second related energy savings device; 
       FIG. 8  is a schematic circuit diagram of the second related energy savings device; 
       FIG. 9  is a schematic circuit diagram of a master unit used in a related energy savings device; 
       FIG. 10  is a schematic circuit diagram of a follower unit used in a related energy savings device; 
       FIG. 11  is a block diagram of an energy savings device according to a first embodiment of the invention; 
       FIGS. 12A ,  12 B and  12 C show phase control waveforms according to the first embodiment of the invention; and 
       FIG. 13  is a schematic circuit diagram of an energy savings device according to the first embodiment of the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Preferred embodiments of the invention will be described in detail below, with reference to the accompanying drawings. 
   The invention is directed to an apparatus and method for controlling power to a resistive, an inductive or a capacitive load, such as a fluorescent light fixture, a halogen light fixture, or a motor for a fan. In a preferred configuration, the energy controlling apparatus is configured to be installed in a light switch box typically located on an interior wall of a building, behind a wall switch plate. Since most light switches are mounted within a switch box that is easily accessible through the wall (e.g., behind a switch plate), the line to the switch is dropped from the fixture to the switch, and the other side of the line (e.g., neutral) is not conveniently present. The invention provides a true switch replacement and operates in series with an inductive or resistive load, in a two-wire configuration, plus safety ground wire. 
   Before describing the invention, also referred to below as a linear control device or LCD, a related device referred to as a universal control device or UCD, which is described in U.S. patent application Ser. Nos. 10/454,840, filed Jun. 5, 2003, and Ser. No. 10/205,031, filed Jul. 26, 2002, which are assigned to the same entity as this application and which are incorporated in their entirety herein by reference, will be explained below. 
     FIG. 1B  shows a hookup of a Universal Control Device (UCD) energy savings device  150 , which is provided between the input AC line voltage  102  and a reactive load  110 , whereby hookup to the neutral line  104  is not required by the energy savings device  150  in order to provide an energy control function for the load  110 . 
   Additionally, referring now to  FIG. 2 , some installations will wire the line  102  directly to the light fixture  110 , leaving the load return  103  for fixture control. In this case, there is no line  102  connection in the switch box, again disallowing integration of a conventional fluorescent dimmer device. The UCD controller  150  is fully compatible with neutral  104  side control, in the manner as shown in FIG.  2 . In summary, the UCD controller is installed in series with the load, on either side of the load, without regard to wiring polarity, identically to a dry contact switch installation. 
   With regards to fluorescent light fixtures, the UCD energy savings device regulates a voltage output to gaseous discharge lamps of the fluorescent light fixture from the secondary coils of a ballast element of the fluorescent light fixture. 
   A block diagram of the UCD is shown in  FIG. 3 , and a schematic circuit diagram of the UCD is shown in FIG.  4 . 
   The UCD includes a “push” On/Off switch and potentiometer unit  310  that is coupled to a line input (AC input voltage)  305 , a solid state switch unit  320 , a driver  330  for driving the solid state switch unit  320 , a power supply  340 , a microprocessor  350 , and a line synchronization detector  360 . The solid state switch unit  320  is provided between the line input  305  and the load  365 . The switch and potentiometer unit  310  includes a “push” On/Off switch SW 1  and a potentiometer POT. The line synchronization detector  360  provides an interrupt signal to the microprocessor  350 , which corresponds to “rising” zero crossing of a load current waveform, to be explained in more detail below. 
   The UCD is a two wire dimmer unit, and can be utilized to control standard magnetic fluorescent fixtures. The UCD may also be used to control other resistive, inductive or capacitive (e.g., standard electronic fluorescent fixtures) loads. The UCD functions similar to incandescent dimmers, but it also implements line synchronization functions and timing functions (not done by incandescent dimmers) to allow it to control fluorescent fixtures and/or other types of reactive or capacitive loads. In a preferred configuration, the UCD is wired in series with the fluorescent load without observance of wiring polarity, in either the hot or return side of the load, in a manner that is identical to a standard single pole wall switch. In fact, the UCD is configured so as to replace any existing wall switch to provide a dimming functionality. 
   In a preferred implementation, the UCD implements an 8-bit digital microprocessor  350  (of course, other types of microprocessors, such as 16-bit, 32-bit, etc., may be utilized instead of an 8-bit microprocessor, while remaining within the scope of the invention) with embedded firmware control algorithms for minimum parts count, and highly stable operation. The UCD is compatible with any configuration of magnetic ballast or electronic ballast fluorescent and/or incandescent loads. In a preferred construction, unit size, costs, producibility, performance and stability are optimized through the use of advanced digital and mass production techniques. Other possible constructions of the UCD to be described later include occupancy sensing, ambient light correction, and AC line modem for communication with a remote Energy Management System. All of these constructions of the UCD to be described herein are “in series”, two wire devices (see  FIG. 1B  or FIG.  2 ). 
   Table 1 provides line specifications of the UCD. One of ordinary skill in the art will recognize that other line specification ranges may be handled by the UCD. 
   
     
       
         
             
           
             
               TABLE 1 
             
             
                 
             
             
               Line Specifications 
             
             
                 
             
           
          
             
                 
             
          
         
         
             
             
             
             
          
             
                 
               Voltage 
               110/277 
               Vac 
             
             
                 
               Frequency 
               50/60 
               Hz 
             
             
                 
               Load Current 
               6.3 
               Amps Maximum 
             
             
                 
               Load/Watts 
               750 
               Watts Maximum 
             
             
                 
               Power Factor 
               0.87-0.90 
               (full power) 
             
             
                 
               THD 
               &lt;35% 
               (full power) 
             
          
         
         
             
             
             
             
          
             
                 
               EMI/RFI 
               FCC Part 18 
             
             
                 
                 
             
          
         
       
     
   
   The UCD provides AC line synchronization and timing firmware algorithms used to provide stable dimming control of an inductive and/or resistive and/or capacitive load without regard to applied line voltage, frequency, and without requiring a specific connection to the AC Line Return or Safety Ground. The UCD implements phase control of the load, and also strategically controls the switching element turn-on timing for stable (non-flickering) control of inductive or resistive loads. The UCD synchronizes on the load current zero crossing, which causes a turning off of the series switching elements making up the solid state switch unit  320 . 
   Highly inductive or resistive loads, such as magnetic fluorescent ballasts, cause a significant phase shift (delay) of the load current waveform relative to the applied voltage waveform, greatly complicating stable synchronization. This phase shift varies depending on the specific installation (number of fixtures and specific ballast specifications) as well as the selected dimming level. As the dimming level is varied, or fluorescent tube temperature changes, the current zero crossing synchronization signal to the microprocessor will move significantly in real time, causing a shift in phase timing for the next cycle. Unless a suitable phase timing algorithm is implemented, the light fixture will flicker in an oscillatory way, resulting in unstable (highly unsatisfactory) dimming. It was determined by the inventors of the UCD (the same inventors as the LCD to be described later) that standard incandescent dimmers will not reliably function with fluorescent or other types of reactive loads due to their simplistic line synchronization methods. The timing correction algorithms utilized in for the UCD are an important aspect of the UCD design, and are described in detail below. Also, the UCD performs well as a dimmer control with little or no flickering, for an electronic fluorescent ballast, which is a capacitive load. 
     FIG. 5  shows the applied line voltage waveform, the dimmed fluorescent load current waveform, and the microprocessor synchronization waveform as implemented by the UCD. Also shown in  FIG. 5  are seven (7) time points in a single cycle of the applied line voltage waveform (60 Hz or 16.67 msec time period for one cycle), each of which is discussed in detail below. The highly inductive nature of a fluorescent magnetic ballast causes the load current to lag the applied line voltage, as seen in the comparison of the AC line voltage waveform  510  with the load current waveform  520 . The amount of lag depends on the circuit inductance, specific ballast design factors, tube striking voltage which is affected by tube temperature, and the amount of dimming phase delay being applied by the UCD. A point by point discussion of the seven labeled time points in  FIG. 5  follows, with reference to the circuit elements shown in FIG.  4 . 
   Time point  1  corresponds to the rising zero crossing of the applied line voltage waveform  510 . 
   Time point  2  corresponds to the turn off point of Silicon Controlled Rectifier (SCR) Q 2  from the previous dim cycle. An SCR turns off when the applied current through it reaches zero. Once the SCR turns off, the voltage across the SCR rises sharply. 
   At time point  3 , the turning off of SCR Q 2  causes the synchronization signal on pin  5  of the microprocessor U 2  to go low, which interrupts the microprocessor U 2 . In the preferred construction of the UCD, microprocessor firmware is initialized to only respond to the falling edge of the interrupt, and is used to derive all phase control timing for an entire line cycle. As the UCD dimmer potentiometer R 7  is rotated clockwise, the period of phase delay time between time point  3  and time point  4  of  FIG. 5  is increased, causing the fluorescent light fixture being controlled by the UCD to dim. Conversely, counterclockwise rotation of the UCD dimmer potentiometer R 7  decreases this phase delay time, thereby causing the fluorescent light fixture light output amount to intensify. 
   The inventors of the UCD have found through experimentation that a typical fluorescent tube with magnetic ballast goes off (no light output by it) at approximately 120 degrees (about 5.5 mseconds) of phase delay. This is due to insufficient tube ionization caused by insufficient tube heater output. Without adequate tube ionization, the tube strike voltage exceeds that available from the AC line. The inventors of the UCD have also found that they were not able to visibly discern a change in light output until the phase delay reached about 15 degrees (about 0.7 mseconds) of phase delay. The half-intensity point was about 90 degrees of phase delay (about 4.17 mseconds). 
   Microprocessor control of the phase delay controls the dim level of the fluorescent fixture (the load). In response to the falling edge of the synchronization interrupt, the microprocessor U 2  resets a free-running internal hardware timer (not shown in the figures) to zero, then waits for the timer to reach the phase delay value corresponding to the current position of the UCD dimmer potentiometer R 7 . In a preferred implementation, the UCD dimmer potentiometer R 7  is coupled to a rotatable dial that is disposed on a wall of a building, whereby, when a user rotates the dial, the resistance of potentiometer R 7  changes accordingly. The change in the resistance of potentiometer R 7  is discerned by the microprocessor U 2 , which then computes a different phase delay value for a next AC voltage waveform cycle based on the new dimmer setting. 
   After the calculated phase delay time corresponding to time point  4  is reached, the microprocessor U 2  triggers the SCR Q 1  on by bringing pin  2  of the microprocessor U 2  low for a short period of time. In the preferred construction, an opto-isolated triac U 1  is used to trigger the SCR on while isolating the microprocessor U 2  from possible damaging transients. Once the SCR Q 1  is triggered on and current begins to flow, SCR Q 1  will latch itself on until current reaches zero during the next half cycle. Current flow through the load continues whenever the SCR Q 1  or the SCR Q 2  is triggered on. When the SCR triggers on, the synchronization signal  530  goes high again. The rising edge of the synchronization signal  530  is ignored by the microprocessor U 2 , which only reacts to a falling edge of the synchronization signal  530  (due to microprocessor firmware that allows interrupts only on the falling edge of a signal provided to its interrupt port). 
   Time point  5  corresponds to the next zero crossing of the load current waveform  520 . At this point, the SCR Q 1  turns off. Unlike the occurrence at time point  2 , no synchronization signal occurs at time point  5 . This is because the microprocessor 5V supply voltage (input line voltage)  340  is negative (it is a floating supply), and the open fluorescent circuit (that is, the load) is roughly ground. The synchronization signal  530  actually rises slightly (few tenths of a volt) after time point  5 , because the “grounded” fluorescent circuit is actually higher in voltage than the microprocessor negative 5V power supply  340 . Microprocessor firmware is provided such that no microprocessor interrupt is generated from this slight perturbation of the synchronization signal  530  (and also since it does not correspond to a voltage drop but rather a voltage rise). 
   Phase control for the latter half-cycle of the AC line voltage waveform  510  is derived from the previous earlier half-cycle interrupt. The microprocessor U 2  measures the applied line frequency and computes the number of internal free-running hardware timer counts that it has to wait for before triggering the SCR on for this latter half-cycle. The timer counts for a time period corresponding between the time between time point  5  and time point  6 . 
   At time point  6 , the SCR Q 2  is triggered on. At time point  6 , the voltage of the synchronization signal  530  drops slightly (a few tenths of a volt). No microprocessor interrupt is generated here either, due to the microprocessor firmware being configured to not cause an interrupt fQr such a small voltage drop. Again, the SCR Q 2  remains on during the negative half cycle, until the circuit current reaches zero. 
   At time point  7 , the rising load current waveform  520  again reaches zero. Again the synchronization signal  530  goes to zero, which causes a microprocessor interrupt (since it is a falling edge of the synchronization signal  530 ). This also causes a resynchronization of an internal free-running timer of the microprocessor U 2 , and results in another phase delay cycle similar to the one that was described above with respect to the time point  2  and time point  3 . 
   The UCD hardware design according to a preferred construction includes the components illustrated in the  FIG. 4  schematic diagram. A brief description of each hardware component, and its applied function, is provided below. 
   The microprocessor U 2  (which corresponds to microprocessor  350  of  FIG. 3 ) provides the control functions and algorithms for the UCD based on an internally stored firmware program. By way of example and not by way of limitation, in a preferred implementation, a MICROCHIP™ 12C672 eight bit microprocessor incorporates 2 kilobytes programmable read only memory (PROM) for program storage, 128 bytes random access memory (RAM), an eight bit timer, 4 channel 8 bit Analog to Digital (A/D) converter, 4 MHz oscillator, and reset circuit in a very space efficient  8  pin package. More details on this microprocessor can be found at the Internet web site www.microchip.com. Of course, one of ordinary skill in the art will understand that other types and sizes of microprocessors may be utilized for the microprocessor to be used to control the UCD. 
   Since the functionality of the microprocessor U 2  exists internally, in a preferred implementation, six I/O pins may be allocated to either digital inputs and outputs or analog inputs. Two pins are reserved for +5 volt power and ground. By way of example and not by way of limitation, an Analog to Digital input impedance is approximately 10K ohms. 
   By way of example and not by way of limitation, the “push” on/off potentiometer switch SW 1  is rated for the 6.3 ampere maximum dimming capacity. When turned off, the dimmer/load is entirely open circuited, resulting in no current flow to the load. Rotating potentiometer R 7  and switch SW 1  are preferably integrated into a single unit. Pushing the adjustment shaft of potentiometer R 7  will cycle switch SW 1  on and off. Potentiometer R 7  is wired as an adjustable voltage divider, whereby rotating the shaft of potentiometer R 7  adjusts the voltage at pin  7  of microprocessor U 2 . The microprocessor U 2  reads the voltage at its pin  7  once every AC line cycle, and uses this voltage to derive the amount of phase delay (dim level) for the load. Resistor R 8  is wired between the potentiometer wiper and ground, and is used to provide a more linear relationship between the potentiometer position and resulting dim level. By way of example and not by way of limitation, resistor R 8  has a resistance of 4.7 kohms. 
   In the preferred implementation of the UCD, two SCRs Q 1 , Q 2  are connected back to back to provide an active switching element for the UCD, and correspond to the solid state switch  320  of FIG.  3 . The inventors of the UCD found that TRIAC devices do not trigger as accurately as back-to-back SCRs when switching a highly inductive resistive load. Consistent and accurate switching element turn-OFF at the current zero crossing is very important to line synchronization. The use of a TRIAC as the active element may result in occasional flickering, which may be due to an unstable holding current level. As a result, the inventors found that an active element that includes back-to-back SCRs functions much better than one having a TRIAC in the energy savings device according to the invention, whereby using two SCRs provides an increase in switching current capability and better heat distribution to a heat sink. 
   By way of example and not by way of limitation, the SCRs utilized in a preferred implementation of the UCD are 600V, 15 ampere devices. The SCRs Q 1 , Q 2  are designed to run very cool at maximum specified loads. The choice of which type of SCRs to use in the UCD may also be made based on a low holding current parameter for the SCRs. When a signal of either polarity triggers the opto-isolated triac U 1 , positive pulses from pin  4  and from pin  6  of the opto-isolated triac U 1  are transmitted to gates (G) of the SCRs Q 1 , Q 2 , respectively. Opto-isolated triac U 1  of  FIG. 4  corresponds to solid state driver unit  330  shown in FIG.  3 . 
   SCRs conduct current in one direction (from anode to cathode), with back-to-back SCRs having the capability to conduct in both directions. SCRs are latching devices, meaning that once they are trigger on, they will continue conducting until the anode-to-cathode current through them reaches zero (or reverses direction). An SCR is triggered on by pulling current out of its Gate pin, or bringing the Gate voltage a few volts lower than its anode pin. The holding current specification for an SCR specifies the minimum SCR current necessary for the SCR to latch on, and to remain latched on. A holding current on the order to 20 milliamperes is needed for proper operation of a typical SCR. Once the SCR current drops below the specified holding current, it will turn off until retriggered again. Only the SCR with its anode voltage positive relative to its cathode voltage is capable of being triggered on. This means that SCR Q 1  controls the load during the positive half of the AC voltage waveform cycle, and SCR Q 2  controls the load during the negative half of the AC voltage waveform cycle. 
   As shown best in  FIG. 4 , the opto-isolated triac U 1  is used to trigger the SCRs Q 1 , Q 2 . The microprocessor U 2  triggers opto-isolated triac&#39;s U 1  internal triac, and subsequently one or the other SCR Q 1 , Q 2 , by illuminating the opto-isolated triac&#39;s U 1  internal light emitting diode (LED). LED illumination occurs when the microprocessor U 2  pulls its output pin  2  low, resulting in LED forward current. The opto-isolated triac U 1  is capable of conducting current in either direction, depending on the relative voltages of pins  4  and pin  6  of the opto-isolated triac U 1 . For example, if pin  6  is higher than pin  4  of the opto-isolated triac U 1 , current will flow from pin  6  to pin  4 . Connecting the opto-isolated triac U 1  between the gates of the two SCRs Q 1 , Q 2  provides a convenient method of triggering back-to-back SCRs. 
   Current flows into pin  6  of the opto-isolated triac U 1  and out pin  4  in response to the positive half of the AC sine wave voltage waveform  510  (see  FIG. 5 ) and vice versa in response to the negative half of the AC sine wave voltage waveform  510 . Pulling current out of the associated SCR gate turns the device on. The internal structure of the SCR allows current to flow into the gate of the opposite device without triggering the device. Therefore, SCR Q 1  will remain latched through the positive half of the sine wave current, whereupon at approximately zero crossing, the latching current will be insufficient and SCR Q 1  will switch off. Similarly, the gate of SCR Q 2  will source current into pin  4  of the triac U 1  and out pin  6  of the triac U 1  during negative half of the AC cycle, and remains latched again until approximately zero crossing. This switching sequence repeats for each cycle of the AC sine wave voltage waveform  510 , providing full power of sine wave current to the (fluorescent) load. Accurate and stable triggering of the SCRs Q 1  and Q 2  are very important to the suppression of flickering. 
   Back-to-back SCRs are used to form an active element of an energy savings device according to a preferred implementation of the UCD since they were found by the inventors of the UCD to be somewhat more stable in their turn OFF characteristics than a TRIAC. In order for an SCR to latch on, the anode/cathode current must exceed the latching current requirement. Once it is latched on, an SCR will remain on until it is turned off when anode/cathode current drops below holding current requirement. With such features, SCRs are ideal devices to be utilized for the active element that corresponds to the solid state switch  320  (see  FIG. 3 ) of the UCD. One of ordinary skill in the art will recognize that other types of solid state switches may be utilized, as well as switch drivers, beyond the ones described herein. 
   In the preferred implementation of the UCD, the opto-isolated triac U 1  is utilized to provide driving signals to the SCRs Q 1 , Q 2 . By way of example and not by way of limitation, the opto-isolated triac U 1  may be a MOC3022 opto-isolated triac, which drives the Q 1  and Q 2  gates and provides line transient protection to the microprocessor U 2 . A LED drive current of approximately 5 milliamps (via resistor R 6 , which is a 620 ohm resistor in the preferred implementation) is sufficient to reliably trigger the opto-isolated triac U 1 . The GP5 pin of microprocessor U 2 , which corresponds to pin  2  of the microprocessor U 2 , is configured for output and is capable of sinking up to 20 milliamps. 
   Referring to  FIG. 5 , the opto-isolated triac U 1  outputs a drive signal starting at time point  6 , whereby the drive signal is turned off well before the load current zero crossing at time point  7 . Also, the opto-isolated triac U 1  outputs a drive signal starting at time point  4 , whereby the drive signal is turned off well before the load current zero crossing at time point  5 . 
   Referring to  FIG. 4 , resistor R 2  is a current limiting resistor, and is provided so as to limit the series current of the opto-isolated triac U 1  to be less than one ampere under all circumstances. For 277 VAC installations, the value of resistor R 2  should preferably be increased to 470 ohms due to the increase in the AC waveform voltage level. 
   In a preferred implementation of the UCD, the SCR trigger signal output by the optoisolated triac U 1  stays on for approximately 1.2 milliseconds. The actual SCR trigger signal on time is not critical, since an SCR triggers on within a few microseconds of receiving a trigger signal to its gate. In a preferred implementation of the UCD, and as explained above, the SCR trigger signal turns off before the next zero crossing of the load current waveform, in order to enforce some SCR off time (e.g., 0.25 milliseconds). This off time is provided in order to recharge the 5 volt power supply  340  (see  FIG. 3 ) for the next cycle. 
   Resistor R 1 , capacitors C 1 , C 2 , diodes D 1  and D 2 , and the 5 volt power supply of  FIG. 4  are all utilized for a power supply control for the UCD, and together form the power supply unit  340  shown in FIG.  3 . In a preferred implementation of the UCD, the 5 Volt power supply  340  provides up to 20 millamps of power to the microprocessor U 2 , opto-isolated triac U 1 , and the potentiometer R 7  at all times in which the UCD is powered. The 5 Volt power supply  340  floats with the AC line input. Voltage is derived by the widely varying voltage across SCRs Q 1  and Q 2 . Power is available to the circuit only when SCRs Q 1  and Q 2  are switched OFF. When SCRs Q 1  and Q 2  are turned on, the 5 Volt supply  340  is maintained by capacitor C 1  and is stabilized by zener diode D 1 . Silicon Diode D 2  provides a discharge path for capacitor C 1 . Resistor R 1  and capacitor C 2  provide an AC coupled voltage drop to limit silicon diode D 1  and zener diode D 2  current and dissipation. By way of example and not by way of limitation, the microprocessor U 2  remains entirely functional with any supply voltage over 3.3 Volts at a current of 3 milliamps. In a preferred implementation of the UCD, supply regulation is not critical as long as the supply voltage maintains the 3.3V minimum. 
   Resistors R 3 , R 2 , R 4 , R 5 , and diode D 3  of  FIG. 4  are elements making up the Line sync unit  360  shown in FIG.  3 . The falling half of the AC line output (when SCRs Q 1  and Q 2  turn off) is used for line synchronization. SCRs Q 1  and Q 2  turn off at the line current zero crossing. Zener diode D 3  protects the microprocessor interrupt input (port  5  of the microprocessor U 2 ) against unforeseen line and switching transient spikes. Resistor R 5  limits current input to the microprocessor U 2  and allows the internal microprocessor protection or clamp diodes to function while preventing any possible burnout. Resistors R 2 , R 3  and R 4  also provide a current limiting and line synchronization function for the UCD. 
   The inventors of the UCD have realized that stable AC line synchronization is very important to non-flickering operation when controlling inductive and/or resistive loads (especially conventional Magnetic Ballast Fluorescent Fixtures), and even for controlling capacitive loads (such as Electronic Ballast Fluorescent Fixtures). These synchronization methods are implemented in the firmware of the microprocessor U 2  used in the UCD. 
   The microprocessor firmware provides a Line Sync Edge Detection function. In detail, the microprocessor U 2  is interrupted on the falling edge of Line Syncronization signal  530  (see  FIG. 5 ) which occurs once every AC cycle as the switching element turns off at the current zero crossing. SCRs have a characteristic in that they latch themselves on until the current through them reaches zero. The point where they turn off is used as the line synchronization. An internal timer of microprocessor U 2  is initialized at this interrupt, and timing parameters for the next entire AC cycle calculated in firmware. Using a single current zero crossing per AC cycle cancels any non-uniformity of the positive and negative halves of the current waveform, as well as eliminates interrupt input threshold hysteresis effects. 
   The firmware of microprocessor U 2  also provides an AC Line Period Determination function. In detail, at initial power up, the microprocessor performs a timing analysis of the AC line with the load switched off so that specific timer counts for each half phase may be calculated. Leaving the load off during this period provides a very accurate measurement of the AC line voltage, without inductive load phase shift influence. At the first interrupt after initial power up, the microprocessor timer is initialized to zero. At the next interrupt the timer value is stored, representing the number of timer counts for a full AC cycle. Subsequent phase timing parameters are derived from this number. Intra-interrupt timing functions are driven by waiting for specific timer counts. 
   The microprocessor firmware also performs a Phase Timing Calculation function. In detail, once the line period has been determined, the firmware of microprocessor U 2  performs phase timing calculations. Since synchronization is performed only once per AC cycle, a determination of the cycle half time is made by dividing the period by two (shift right one time). Next, a calculation of when the cycle is completed (cyclendtime) in anticipation of the next interrupt is made. 
   The firmware of microprocessor U 2  further performs a Dead Time Implementation function. In detail, circuit power is only available when the series switching elements (SCRs) are turned off, therefore microprocessor firmware guarantees a minimum off time (deadtime) for each AC line half cycle to restore the 5 volt supply. 
   The firmware of microprocessor U 2  also performs a Fixture Warmup function. In detail, fluorescent tubes should be fully warmed up before they can be reliably dimmed. This feature may not be desirable for other types of inductive or resistive loads, and may be easily deleted from the control device, without departing from the scope of the invention. To address this requirement, the fixture is set to full intensity for a first time period after initial power up. By way of example and not by way of limitation, the first time period is set to 12 seconds. Upon completion of the 12 second period, the intensity is returned to the dim level corresponding to the position of potentiometer R 7  (see FIG.  4 ). 
   The firmware of microprocessor U 2  further provides a Sync Window Implementation function. In detail, in order to reject spurious line transients which could possibly upset dimmer timing, a sync window algorithm is utilized in the first embodiment. At the end of each full AC cycle, the microprocessor U 2  waits until cyclendtime which occurs a few timer counts before the next line interrupt, before re-enabling interrupts. If a spurious interrupt occurred between the last sync edge and cyclendtime, it is effectively ignored. 
   The firmware of microprocessor U 2  also provides a Slow Phase Timing (Dim Level) Changes function. In detail, when using a current zero crossing sync with an inductive magnetic ballast, any phase timing (dim level) change causes a slight synchronization variance which could cause instability (flickering) if not greatly damped out. To greatly lessen this possibility, phase timing changes are limited to one timer count per AC cycle, thereby minimizing this effect. 
   The firmware of microprocessor U 2  further provides a function for pulsing the SCRs ON at the correct time. In detail, the SCRs Q 1 , Q 2  are pulsed on, instead of just turned on and left on at the proper time, to reduce the drain on the 5 Volt power supply  340  (see FIG.  3 ). 
   More details of the microprocessor firmware implementation according to a preferred implementation of the UCD is provided in detail below. In the preferred implementation of the UCD, the firmware of microprocessor U 2  is written using a Microchip assembler language specific to the 12C672 eight bit microprocessor. Of course, based on the type of microprocessor utilized in the first embodiment, the choice of software language used to write the microprocessor firmware will be utilized accordingly. 
   A detailed flow chart of the preferred implementation of microprocessor firmware to be utilized by a microprocessor U 2  provided in the UCD is illustrated in FIG.  6 . Major flow chart function descriptions are provided below. 
   For UCD implementation, a Reset occurs only during initial power up. At this time, microprocessor memory and register contents are random, and are thereby initialized before they can be used. In the preferred implementation of the UCD, the microprocessor U 2  has an internal reset circuit which recognizes when power is initially applied. Upon Reset, the microprocessor U 2  begins execution at address  0000 , which is where the initialization firmware starts. Once this initialization executes, it is not re-executed unless another power up sequence occurs. 
   Two interrupts are enabled for the UCD according to a preferred construction. First, the external synchronization falling edge interrupt, from which all phase delay calculations are derived, is enabled. Second, the internal hardware free-running timer overflow interrupt is enabled. In the preferred implementation of the first embodiment, the timer is an 8 bit timer which is incremented once every 64 microseconds. The timer overflows every 16.384 milliseconds ( 256  counts), which is slightly less than a full 16.667 millisecond line cycle. During an interrupt, the microprocessor U 2  stops executing where it is, saves it&#39;s state (e.g., processor status word and program counter), and executes interrupt code. Initial line parameter calculations, hardware timer maintenance, and Analog to Digital Converter (ADC) maintenance occurs during the interrupt firmware. 
   Referring to  FIG. 6 , “Main” is the start of the primary UCD software program run by the microprocessor U 2 . It is entered after initial power up initialization and once per complete line cycle. “Main” keeps track of the current line half cycle, and performs all phase timing calculations based on the free-running hardware timer. Phase timing is implemented by waiting for the appropriate free-running timer count to occur, then calling the TrigScr subroutine which implements the SCR trigger timing. Specific free-running timer values to wait for are calculated based on the following factors: 
   a) Dimpot position: As indicated by the converted ADC value. Rotating the dimpot potentiometer clockwise will reduce phase delay, and increase florescent intensity. 
   b) FullOnMode: During the first 12 seconds after initial power up, the UCD is in FullOnMode. During this time, the florescent load is forced into full intensity to warm the tubes. During FullOnMode, phase delay is fixed at the constant value fulltime. When not in FullOnMode, phase delay is calculated based on dimpot position, and results of the softdim calculation. The softdim calculation prevents large cycle to cycle phase delays from occurring. This provides a stabilizing effect on florescent intensity. 
   c) Cycle Half: After completion of the first half of the line cycle, firmware waits for the pre-calculated half period free-running hardware timer value, resets the timer, and jumps back to Main. This causes the second half cycle phase delay timing to be identical to the first half cycle. At the end of the second half cycle, firmware will wait for the free-running hardware timer to reach the pre-calculated cyclendtime, then re-enable interrupts in anticipation of the next full line cycle. 
   After the appropriate phase delay has be determined, a call to TrigScr is executed whereby the SCRs Q 1 , Q 2  are turned on at the appropriate times. 
   The TrigSCR sub-routine toggles the SCRs Q 1 , Q 2  on and off for a period of time to minimize drain on the 5V power supply. Once the SCR current is greater than the SCR specified holding current, it will latch on for the duration of the half cycle, until the current reaches zero again. Relative free-running hardware timer values are used to accomplish this pulse ON, pulse OFF, and pulse duration timing. 
   The following are descriptions of each section of the dimmer firmware utilized by the microprocessor U 2  according to a preferred implementation of the UCD, whereby each section is identified by line number, then label and references to the flow chart of FIG.  6 . Of course, other firmware may be utilized as would be recognized by one of ordinary skill in the art. 
   Line  1 : Defines the microprocessor as the target for the assembler 
   Line  2 : This include file defines the microprocessor register names and memory mapped register addresses. 
   Line  5 : A list of defined memory mapped addresses follows:
         dimpot: Storage of the dim potentiometer analog value   timerstat: Mode Flags specific to dimming mode   tmrovflcntr: Used as an overflow counter to the internal 8 bit counter TMR0   intovflcntr; LSB of counter used for 12 sec full ON   fullintcntr: MSB of counter used for 12 sec full ON   timereg: Temp Storage of TMR0 Count   periodmsb: Measured MSB of Full wave TMR0 Count   periodlsb: Measured LSB of Full wave TMR0 Count   halftime: Calculated TMR0 Count for Half Wave   trigtime: Calculated TMR0 Count to Trigger SCR   SCRofftime: Temp Storage where time to turn off SCR is stored each cycle   SCRlstime: Temp Storage for Last SCR time . . . subse quent SCR ON/OFF functions key off of this stored TMR0 value   cycendtime: Re-Enable Edge Interrupt time   softlast: Temp Storage of last dim time count is stored. Used for Soft Dim       

   Line  23  ;GPIO Bit Defs
         potanal 12C672 GPIO Pin Allocated to Potentiometer Analog Input   gp1 12C672 GPIO Pin Not Used   acint 12C672 GPIO Pin Allocated for AC Interrupt Input   gp3 12C672 GPIO Pin Not Used   gp4 12C672 GPIO Pin Not Used   SCRdrv 12C672 GPIO Pin GPIO SCR Drive Output       

   Line  31  ;TimerStat Bit Defs
         firstedg Flag: First Interrupt Edge Occured   secedge Flag: Second Interrupt Edge Occured   fullonmode Flag: Full on mode   newedge Flag: New Edge Flag   cycsechalf Flag: Second Half of Period   oddedge Not Used in this Version       

   Line  39  ;Value Defs
         intovflow=d‘3’ ;FullOnMode Int Overflows  − 4Secs per inc   dimofst=h‘4’ ;ADC Offset, Higher Numbers go Dimmer   maxofst=h‘7f’ ;Maxdim Offset   maxdima=h‘fe’ ;Maxdim Level   maxdimlyl=h‘d0’ ;Maxdim   intwindow=d‘3’ ;Interrupt Window   SCRpulsetime=h‘37’ ;Time SCR is Pulsed ON and Off   deadtime=d‘8’ ;Dead time past zero crossing   fulltime=d‘8’ ;Full On time past zero crossing       

   Line  54  rstvec The microprocessor starts execution at address  0  after Reset, Interrupts are disabled, then memory initialized 
   Line  58  intvec The microprocessor interrupt vector for enabled interrupts is at address  4   
   Line  59  intsvc TMR0 is cleared at each falling edge of the AC interrupt. After a Reset, a wait for the zeroth edge is executed. Upon occurrence of the zeroth edge, TMR0 overflow interrupt is enabled so that the AC edge to edge period can be calculated. Upon occurrence of the first edge interrupt, AC parameters are calculated and used in subsequent phase calculations. 
   Line  61  Jump table based on edge occurrences 
   Line  65  notfirst Zeroth edge interrupt has occurred, enable TMR0 overflow Interrupts 
   Line  72  firsthap First interrupt has happened, count number of TMR0 overflows, enable Next TMR0 overflow interrupt 
   Line  78  notmrint If it&#39;s a second edge interrupt, then disable subsequent TMR0 overflow Interrupts, and then calculate AC timing parameters 
   Line  81  caltime AC parameters such as period, halftime, and cyclendtime, are calculated once. Flag secedge is then set, and further edge interrupts enabled. From now on, each edge interrupt constitutes an AC line synchronization signal used for phase control of the SCRs 
   Line  100  sechap Once the second edge interrupt has occurred, then 12 seconds of full on is executed to fully warm the tube heaters. Fullintcntr, and intovflcntr form a 16 bit counter which count 16.667 mS edge interrupts. A total of 768 edge interrupts provides a net 12.8 seconds of fluorescent tube full on time. 
   Line  112  fulldun Upon conclusion of the full on mode, the fullonmode flag is cleared in timerstat. 
   Line  113  notfull Each edge interrupt, the A/D converter is checked for conversion complete. If it has completed the dimpot value is inverted by exclusive Oring the input value and stored in the memory location dimpot. 
   Line  121  nocvrt A/D conversion has completed, another conversion is started. The newedge flag is set and the cycsechalf flag cleared, indicating to the main program code that an interrupt had occurred, and that it is now the first half of the AC cycle. 
   Line  123  glitint TMR0 is cleared, Edge interrupts are re-enabled, and a return from interrupt executed 
   Line  129  initmem Microprocessor hardware registers are initialized, program defined registers are cleared, and finally edge interrupts are enabled. 
   Line  173  main Main part of the program. Wait for second edge interrupt. At this time, all AC line parameters have been calculated, and normal phase control can commence. 
   Line  175  main1 Wait for each new edge. Newedge is a handshake flag with intsvc which is used to wait for a new edge at the completion of each AC cycle. 
   Line  178  main2 Entered at the start of each AC cycle. Potentiometer scaling to actual TMR0 counts are performed once per AC cycle. Edge Interrupts are disabled, dimpot contains the commanded dim value. The memory location softlast is used to calculate the desired dim value time. 
   Line  189  sechalf This is the entry point for the second half of the AC cycle. If NOT in Fullonmode, then go to dimtrig. Else, it is fullonmode at sechala. 
   Line  191  secala A wait until TMR0=deadtime is executed. Deadtime defines the earliest time (in TMR0 counts) the SCR may be triggered ON after an AC line voltage zero crossing. A call to trigSCR turns the SCR on for a period of time. After returning, the first cycle half is complete. 
   Line  198  dimtrig Fullonmode has completed, enforce minimum deadtime limit, by waiting for TMR0 to reach deadtime value. 
   Line  202  dimwait Past deadtime, now wait for the calculated TMR0 value corresponding to the calculated phase delay for the indicated dim level. The memory location trigtime is incremented or decremented once each time, effectively “chasing” the desired dim level stored in softlast. 
   Line  217  hafcycl Halfcycle parameters are checked. If already in the second half, a wait for next edge interrupt (jump to rstcycle) is executed. If Not already in second half, a wait until the previously calculated Halftime TMR0 value is executed. Once past halftime, TMR0 is cleared, and the cycsechalf flag is set. Then a jump to sechalf occurs, duplicating timing parameters for the second half of the AC cycle. 
   Line  229  rstcycle Once timing for the second half of the AC cycle has been executed, a wait until cyclendtime is executed before edge interrupts are Re-enabled. This provides a window which rejects AC line transients which occur outside of the window. Upon passage of the window, Interrupts are re-enabled, and a jump to main1 is executed, causing a Wait for the next edge interrupt. 
   Line  240  trigSCR TrigSCR is a routine that is called when it&#39;s time to turn on the SCR. When called, the SCR is triggered on (SCRdrv is brought low), then the SCRofftime is calculated based on addition of the constant SCRpulsetime, and the current TMR0 value. A wait until SCRofftime is executed, whereupon the SCR is turned off (SCRdrv is brought high). If cycendtime occurs during the time trigSCR executes, drive to the SCR is deasserted, and a return to the calling code is executed. 
   Line  265  end End of the program. 
     FIG. 7  shows a block diagram of an energy savings device UCD- 2  according to a different construction, and  FIG. 8  shows a schematic circuit diagram of the energy savings device UCD- 2  according to that different construction. The energy savings device UCD- 2  provides all of the functions of the UCD described previously, along with extra functions. The UCD- 2  includes an occupancy sensor, an ambient light sensor, and an AC line modem for remote communications to a central energy management system, for example. The UCD- 2  provides a more robust energy savings function than the UCD described previously. 
   As shown in  FIG. 7 , an ambient light sensor unit  710  of the UCD- 2  provides the capability to adjust the dimming level for constant level illumination during day/night ambient illumination variances. Referring also to  FIG. 8 , the ambient light sensor unit  710  includes a photo-resistor R 19  with amplifier  720 , which provides a stable indication of the total ambient illumination via a signal AMBLITE provided to port  1  of the microprocessor U 2 . The microprocessor U 2  adjusts the dimming level to maintain this total ambient illumination level. For example, during a cloudy day, if the clouds break during the afternoon and thus the light through windows of an office increases, this results in an increase in the illumination level picked up by the ambient light sensor unit  710 . Accordingly, the microprocessor U 2  will adjust the load current waveform to provide a slightly dimmer signal than what was previously provided (during the cloudy period), so as to maintain a stable ambient illumination for the office. 
   Referring to  FIG. 7 , the occupancy sensor unit  730  of the UCD- 2  provides the capability to sense movement within an illumination area. The occupancy sensor unit  730  is configured to provide a signal indicative of no movement to the microprocessor U 2  if no movement is sensed after an extended interval of time (e.g., 15 minutes or more). Upon receipt of the “no movement” signal from the occupancy sensor unit  730 , the microprocessor U 2  turns the light fixture off, in order to save energy. Similarly, illumination to a preset level is restored if movement occurs, such as when a person walks into a room. Referring to  FIG. 8 , the occupancy sensor unit  730  according to a preferred implementation includes a passive infrared sensor  750  with a multifaceted (Fresnel) lens  740  in front of a pyroelectric transducer. For example, a Murata IRA-E710ST0 may be utilized as the motion detector for the occupancy sensor unit  730 . The lens  740  focuses infrared energy from a multitude of narrow, discrete beams or cones. As a warm body moves across the field of view of the detector, the transducer output has peaks and valleys which are amplified, thereby providing an indication that movement is occurring. This results in a signal MOTDET that is indicative of movement being provided to the microprocessor U 2 . 
   Referring to  FIG. 7 , the AC line modem  760  of the UCD- 2  enables bi-directional communications with an energy management unit, such as with a centralized energy management system (EMS). In one implementation shown in  FIG. 8 , the AC line modem is implemented as a line modem TDA5051 component. The EMS has the capability to remotely control some or all dimming functions and modes including turn off illumination (via signal PWRDWN provided to microprocessor U 2 ), set dimming level, and verify occupancy sensor status (possible burglar alarm function). The EMS is preferably a standard personal computer with external AC line modem connected to a serial port. Software running under an operating system, such as the Windows™ operating system, maintains the status of all units within a local area. The AC line modem  760  functions by modulating a 200 KHz signal onto the AC power line via a filter network  770  that includes an inductor L 1  and a capacitor C 4  (see FIG.  8 ), in one possible implementation of the UCD- 2 . The EMS can communicate with a wide area of dimming units that are on a common AC line step down transformer, for example. Each dimming unit carries a unique address to facilitate a multi-drop communications network via the power lines. 
   In a third possible construction of the UCD, unlike the “loaded” UCD- 2 , only the ambient light sensor unit of the UCD- 2  is provided along with the features of the UCD. 
   In a fourth possible construction of the UCD, only the occupancy sensor unit of the UCD- 2  is provided along with the features of the UCD. 
   In a fifth possible construction of the UCD, only the AC line modem of the UCD- 2  is provided along with the features of the UCD. In another possible implementation, both the occupancy sensor unit and the AC line modem (but not the ambient light sensor) of the UCD- 2  are utilized along with the features of the UCD. In yet another possible implementation, both the AC line modem and the ambient light sensor (but not the occupancy sensor unit) are utilized along with the features of the UCD. In still yet another possible implementation, both the occupancy sensor unit and the ambient light sensor (but not the AC line modem) are utilized along with the features of the UCD. 
   A sixth possible implementation includes all of the features described above with respect to the UCD- 2 , as well as a remote control function. The remote control function allows a user to set a light level by a remote control unit, without having to go to a switch box on a wall. By pointing the remote control unit in a direction of the switch box, and by enabling a button on the remote control unit, a signal is picked up by an element (e.g., infrared sensor, IR sensor) on the switch box, similar to a television remote control unit, whereby a room light level is either increased or decreased depending on the user&#39;s selection on the remote control unit. The remote control function can also be used with any of the other implementations (or constructions) described above. 
   A seventh possible implementation of the UCD is described herein with respect to  FIGS. 9 and 10 . The seventh construction of the UCD is directed to a master/follower control system, whereby a master unit controls one or more reactive loads, and whereby at least one follower unit coupled to the master unit responds exactly the same as the master unit to control loads coupled to each follower unit. The master/follower control system provides for modular flexibility for different sizes of facilities.  FIG. 9  shows a schematic circuit diagram of a master unit  900 .  FIG. 10  shows a schematic circuit diagram of a follower unit  1000  that is controlled by the master unit  900  of FIG.  9 . 
   The seventh possible construction of the UCD includes a conduction angle phase switching circuit connected in parallel with a reactive load, an AC power source for switching power across the load, and a line switching circuit for enabling the application of AC power to the load through the phase switching circuit. 
   In the seventh construction of the UCD, an ambient light sensor  910  is provided for generating a light control signal indicative of the amount of ambient light present in a particular location. Coupled to the light sensing circuit is a phase angle conduction control circuit, which generates and applies to a control is terminal of the phase switching circuit a phase control signal to control the phase angle conduction time of the phase switching circuit, based on the amount of ambient light measured by the light sensing circuit, in order to maintain a substantially constant lighting level. In  FIG. 9 , the microprocessor U 3  functions as the phase angle conduction control circuit. 
   Integrated with the phase angle conduction control circuit is an RC filter circuit which gradually increases the phase angle conduction time switching circuit from zero, or from a predetermined minimum value, to a steady state phase angle conduction time based on the ambient light conditions sensed by the light sensing circuit, after power enabling by the line switching circuit. 
   Referring to  FIG. 9 , the master unit includes a line switch SW 1  connected in series with an AC power source between a hot (black) and a neutral (white) power line. Connected in series between the hot and neutral power lines is an reactive load (e.g., fluorescent lamp), and a phase angle control switching device that includes SCRs Q 1  and Q 2  and an opto-isolated triac U 1  for driving the SCRs (see discussion with respect to the first embodiment). 
   Also shown in  FIG. 9  is the microprocessor U 3 , which receives a line sync signal from a bridge circuit D 1  that is coupled to the hot and neutral lines. Based on the line sync signal, and based on the setting of the potentiometer and switch SW 1 , the microprocessor U 3  provides control signals to the opto-isolated triac U 1 , as well as to follower units coupled to the master unit via pulse width modulated (PWM) signaling. 
     FIG. 10  shows the elements of a follower unit  1000 , which receives the PWM control signals from the master unit, and which controls one or more loads connected to the follower unit based on on/off switching of its active element (SCRs Q 1 , Q 2 , and opto-isolated triac U 1 ) via those control signals. 
   A first embodiment of the invention will be described below, which utilizes a linear control device (LCD) to control a load such as a fluorescent light fixture, with reference to  FIGS. 11 ,  12 A,  12 B,  12 C, and  13 . The LCD is an improvement on the various constructions of the UCD described previously. 
   The LCD encompasses both center switched phase control and closed loop linear current control dimming.  FIG. 11  illustrates a preferred implementation of the LCD according to the first embodiment. The LCD  1100  includes a bridge rectifier  1110  on the output that allows the use of a single switching/linear control element  1120  to control current flow during both halves of the AC cycle of an AC voltage waveform. By way of example and not by way of limitation, the switching/linear control element  1120  may be a MOSFET, an IGBT, or a BJT. Without the bridge rectifier  1110 , two control elements with a relatively complex biasing arrangement would be required, as described above with respect to the first and second constructions of the UCD described previously. 
   For the purposes of description of the operation of the LCD, assume the use of a MOSFET as the switching linear control element  1120 , although an IGBT or BJT device can be utilized as described above with only minor circuit changes. Selection of a particular device for the switching linear control element  1120  could be based, for example, on cost, available device specifications (primarily RdsON for MOSFETs and VceSat for IGBT and BJT), load characteristics and resulting thermal considerations. Any of these devices allow switching fully On or OFF at any time during the AC cycle or linearly controlling load current. 
   As shown in  FIG. 11 , the LCD  1100  also includes a processor  1130 , a dim level setting element  1140 , a low pass filter  1150 , an operational amplifier  1160 , and a floating power supply  1170 . The bridge rectifier  1110  is disposed between the line  1175  (that provides the AC input voltage waveform) and the load  1185 . The processor  1130  provides control of the MOSFET  1120 , whereby a 5V switch control output voltage on line  1188  turns the MOSFET  1120  OFF, a 0 V switch control output voltage on line  1188  turns the MOSFET  11200 N, and a tristate output on the line  1188  corresponds to a linear current control mode. 
   The pulse width modulated (PWM) output on line  1192  of the processor  1130  is either a 0% duty cycle corresponding to a 0V output on line  1192 , a 100% duty cycle corresponding to a 5V output on line  1192 , or a 50% duty cycle corresponding to a 2.5V output on line  1192 . 
   A voltage line synchronization signal on line  1194  is input to a Timer Reset input of the processor  1130 , where the digital voltage line synchronization waveform  1196  and the Applied AC Voltage waveform  1198  (input by way of the line  1175 ) are shown. The commanded dim level that a user sets by way of the dim level setting element is inputted to an analog input  1177  of the processor  1130 . 
   Note that, as shown in  FIG. 11 , the LCD  1100  is connected in series with the load  1185 , with no neural or ground wire connection to the LCD  1100 . 
     FIG. 12A  illustrates the LCD center switching concept. In  FIG. 12A , progressively narrower load current pulses  1220 A,  1220 B,  1220 C,  1220 D,  1220 E corresponding to increased dimming levels are applied to the MOSFET  1120 , whereby each pulse is centered at a peak of the Applied AC voltage waveform  1198 . The times when the pulses  1220 A,  1220 B,  1220 C,  1220 D and  1220 E are provided correspond to ON periods of the output AC voltage waveform, and all other times correspond to OFF periods of the output AC voltage waveform. 
   By center-switching the MOSFET  1120  around the peak of the applied AC voltage waveform  1198 , inductive load current will increase quicker, reach higher magnitudes, and minimize the resulting voltage to load current phase shift (lower power factor). Additionally, center switching of the applied AC voltage waveform  1198  maximizes magnetic ballast secondary voltages, increasing the probability of firing the fluorescent tube. Also, instantaneous fluorescent tube heater current (and instantaneous temperature) is maximized during this center switched ON period when the applied voltage and resulting current is highest. MOSFET gate-source voltage (Vgs) is positive (e.g., 10 volts or more) to turn the MOSFET  1120  fully ON, zero volts to turn the MOSFET  1120  fully OFF, and somewhere in between to cause it to become a linear (resistive) control element. 
     FIG. 12B  illustrates the linear current control mode of the LCD  1100 . When biased fully ON, the RdsON specification of the MOSFET  1120  determines it&#39;s effective series resistance. Current MOSFET technology has developed inexpensive 600 Volt devices with RdsON specifications of less than 0.2 ohms, suitable for controlling 500 Watt or more inductive loads when placed in a standard Wall Switch electrical enclosure. Lower voltage devices can be made with lower. RdsON specifications. Typically, half the voltage rating results in a device with one fourth the RdsON specification. Heat generated within the MOSFET  1120  obeys Ohm&#39;s I 2 R law for the duration of time it&#39;s conducting power. Low dimming levels are achieved by controlling the period of time the MOSFET  1120  is fully ON, centered around the peak of the applied AC voltage waveform  1198 . 
   Current through an inductive load builds/decays slowly, and if the conduction width is too constrained (narrow), very little current will develop before the switch is turned OFF. Referring now to  FIG. 12B , which shows progressively narrower load current pulses  1240 A,  1240 B,  1240 C,  1240 D, and  1240 E, whereby linear load current limiting is performed at some point while the dimming level is increased, if linear current control was not performed, the center switched load current width would become too narrow for adequate load current to develop through an inductive load, thereby resulting in the fluorescent light extinguishing. Before this point occurs, the LCD  1100  will maintain the adequate center switched load current width (in  FIG. 12B , the pulses  1240 C,  1240 D and  1240 E are maintained at a minimum allowed current width even though the dimming level is increased), then revert to closed loop Linear Current control to achieve the additional stable dimming. 
   When switched ON or OFF, the resulting heat generated within the MOSFET  1120  is relatively low (determined by the load current and RdsON of the device), while when being used as a linear control device, the heat generated will be significantly increased (Vdrain-Vsource times the load current). However, since the LCD  1100  uses high efficiency ON/OFF switching for the majority of the dimming, and linear current control mode only for the remaining very short period of time at high dimming levels, MOSFET linear mode heat is minimized. Thus, by using both timed center switched phase control, augmented with a linear current control technique at high dimming levels, very stable, effective and thermally efficient dimming of fluorescent light fixtures is achieved. 
   As compared to the UCD or the UCD- 2  or the other constructions of the UCD described previously, the use of a Triac or back-to-back Thyristors for the solid state switching element allows switching ON at any time during the AC cycle, relying on the Load Current zero crossing to turn off the Triac. Because of this, the UCD relies on the Load current waveform for synchronization. 
   Inductive loads cause the current waveform to shift in real time as dimming levels are adjusted. Advanced line synchronization and triggering techniques implemented in software minimizes this phase shift for stable dimming, however not completely. Without center switching, the average current waveform delays further and further relative to the applied voltage waveform as dimming levels are increased, resulting in a low power factor which wastes available power. Linear current control is possible with a Triac. At high dimming levels, load current doesn&#39;t even begin to flow until substantially after the peak applied voltage is reached, significantly reducing the magnitude and remaining available time for current to flow through the load. Since current does not flow during the peak applied AC voltage, this limits the maximum firing voltage available on the secondary of a magnetic ballast and significantly limits maximum realizeable dimming levels. 
     FIG. 12C  shows the Applied AC voltage waveform  1198 , the load current through the Triac  1255 , and the phase-shifted (delayed) current waveform  1265  that results in a power factor that is not as good as achieved by way of the LCD  1100  of the first embodiment. 
     FIG. 13  shows a schematic diagram of a preferred construction for implementing the LCD  1100 . For convenience, a Microchip PIC processor  1310  provides the timing and logic functions for the LCD  1100 . Other devices, configurations, or technologies could be considered for providing such functions for the LCD  1100  while remaining within the scope of this invention. An Operational Amplifier U 3  is used to drive the gate of the MOSFET Q 1  (whereby the MOSFET Q 1  corresponds to the MOSFET  1120  shown in FIG.  11 ). In the Linear mode, the OP amp U 3  senses the load current via the voltage developed across the current sense resistor R 12  and linearly controls the gate voltage of the MOSFET Q 1  to maintain the specified current indicated by the Digital to Analog converter output of the Processor PIC. When in the Center Switching mode, the Processor PIC offsets the OP amp U 3  via a tri-stateable digital output to turn the MOSFET Q 1  completely ON or OFF. The high slew rate of the OP amp U 3  facilitates fast Gate control of the MOSFET Q 1 . Preferably, a rail to rail OP Amp device is selected to eliminate the requirement for a negative supply voltage. 
   The bridge rectifier D 8  is in series with the Load, whereby it converts the bi-directional AC load current into a uni-directional current flow, compatible with a single MOSFET switching element, which greatly simplifies the gate biasing network. The 8 bit PWM output of the Processor PIC is used as a Digital to Analog (D/A) output for linear current control of the MOSFET Q 1 . A simple 2-pole RC low pass filter (resistor R 6  and capacitor C 6 ) converts the PWM output to a microprocessor-commanded stable DC voltage level. A voltage divider (resistor R 13  and resistor R 9 ) matches the D/A output to the sensed current. The +12V and +5V supply voltages are derived from voltage across the Bridge rectifier D 8  (corresponding to bridge rectifier  1110  in  FIG. 11 ) during times when the MOSFET Q 1  is turned OFF. A large capacitor (C 2 , C 5 ) is charged and Zener regulator diodes D 1 , D 3  provide stable supply voltages. 
   In the preferred construction of the first embodiment, only 7 milliamps of 5V supply and 3 milliamps of +12V supply are required for powering the LCD  1100 . In the preferred construction, the processor PIC is a PIC 16C772 device made by Microchip. The PIC 16C772 includes an internal 4 MHz clock oscillator, one 16 Bit timer, one 8 bit Pulse Width Modulated (PWM) Output, 5 twelve bit Analog to Digital conversion channels, 4 Kilobytes of Flash program storage memory, and 256 bytes of Random Access Memory. Other processor devices can be considered for the LCD without impacting circuit functionality, while remaining within the scope of the invention. 
   The 16 bit timer is used for MOSFET control timing within the 16.67 millisecond AC waveform period. The use of a 16 bit timer facilitates quite accurate center switching timing control (500 nanosecond timing resolution). Accurate timing is required so that symmetrical switching of the MOSFET can occur, resulting in flickerless dimming. This timer is reset at each AC voltage waveform zero crossing and free-run counts up from that point. A high valued resistor R 3  protects the synchronization input pin of Processor PIC from excessive input voltages. Software run by the Processor PIC calculates the proper timer count to switch ON or OFF the MOSFET Q 1  based on the commanded dim level potentiometer (for example, see the description with respect to the different constructions of the UCD described previously). Once the proper timer value is reached (determined by software sampling of the timer), software places the tri-state digital output into it&#39;s proper state. This output is driven Low (zero volts) to force the OP Amp output to slew to it&#39;s positive rail (to turn the MOSFET Q 1  fully ON), driven High (5 Volts) to slew to it&#39;s negative rail (0 Volts to turn the MOSFET Q 1  completely OFF), or go tri-state (or high impedance) to linearly control the gate voltage of the MOSFET Q 1  for current control). Using this method, the PWM D/A output of the Processor PIC remains static and only changes when the Dim Level changes, resulting in very accurate timing. 
   Like the other described constructions of the UCD, the two-wire nature of the LCD device, whereby the LCD device wires in series with the load, is maintained, whereby it requires no specific connection to the neutral or safety ground. Accordingly, replacement of a SPST wall switch with the LCD can be easily performed. 
   The software written for the Linear Dimmer is preferably written in “C”, using Microchip PIC software development tools. See the description of earlier embodiments of the invention for software that may be utilized for the Processor of the LCD. This dimmer configuration works by maintaining a constant load current in accordance with the D/A converter voltage output from the PIC. 
   Since the local supply voltages for the microprocessor, OP Amp, and MOSFET drive is derived from the MOSFET “OFF” time, periods where the MOSFET Q 1  is off (or has significant voltage across it) are maintained so that the supply voltage does not drop too low. Since only a few milliamps of supply voltages are required, this required OFF time can be quite short. For brief periods (on the order of 0.5 msec) bracketing the voltage zero crossings, the MOSFET Q 1  remains OFF. Leaving the MOSFET Q 1  OFF for this very short period of time during the Voltage zero crossing does not affect the full intensity level of the lamp. Since the positive voltage pulses occur at 120 Hz (60 Hz with the UCD and UCD- 2  configurations), capacitive coupling of the supply voltages using a small value capacitor (C 8  and C 9  in  FIG. 13 ) minimizes power dissipation in the power supply circuit. 
   In a preferred implementation of the LCD, light output is controlled based on the position of the operator controlled Dim Level potentiometer, in conjunction with sensed ambient light indicated by the Optional Photo Conductive Cell (PCC). Varying ambient light causes the PCC to change resistance, forming a voltage divider with R 6 , as seen in FIG.  13 . If the PCC is not to be used, a 1K ohm resistor may be substituted instead. The Dim Level potentiometer voltage is read in software by the A/D converter function of the Processor PIC, and scaled to a value corresponding to a “reasonable” PCC voltage divider A/D conversion reading. The software encoded for the Processor PIC incrementally adjusts the pulse width and D/A converter output voltage so that the ambient light (as indicated by the PCC voltage divider conversion) matches the Dim Level voltage reading. Using this procedure, ambient light is power efficiently controlled, using only that lamp power required to maintain the operator desired ambient light level. 
   At initial power on, the fluorescent lamp should be fully heated at full intensity before it is dimmed. The period of time required is approximately 15 to 30 seconds. After this initial warm up time has transpired, the LCD incrementally adjusts the Lamp intensity level corresponding to the Dim level potentiometer position. 
   Depending on the specific installation (Number of fixtures, and Commanded Dim levels), it is possible for the MOSFET Q 1  to get excessively hot. As a safety feature, a thermistor RT 1  is thermally coupled to the MOSFET Q 1 , whereby a thermistor changes its resistance in accordance with its temperature. The thermistor RT 1  is placed into a voltage divider circuit with resistor R 1 , causing a varying voltage (Readable by the A/D converter of the Processor PIC), corresponding to the temperature of the MOSFET Q 1 . At a MOSFET temperature of approximately 50 degrees C., software being run by the PIC will begin incrementally increasing Lamp intensity so that MOSFET power dissapation and temperature is reduced. Accordingly, a protection mode is provided for the LCD  1100 . 
   Note also that the ground symbol shown in  FIG. 13  is a local ground return and does not imply a connection to the line neutral or safety ground. Accordingly, the LCD  1100  truly is a two-wire device. Also, a photoconductive cell PC 1  is shown in  FIG. 13 , to provide an optional feature of automatic dimmer control based on the amount of light sensed by a light sensor S 1 . The photoconductive cell PC 1  senses the amount of light received by the light sensor S 1 , and provide an input signal to the processor PIC, which the processor PIC uses to set the amount of dimming to be performed by way of the LCD  1100 . 
   A preferred embodiment of the present invention has been described according to the present invention. Many modifications and variations may be made to the techniques and structures described and illustrated herein without departing from the spirit and scope of the invention. Accordingly, it should be understood that the apparatuses described herein are illustrative only and are not limiting upon the scope of the invention. With the use of an energy savings device according to an embodiment of the invention, it is possible to achieve up to a 60% or more energy savings, while not adversely affecting the perceived amount of light by users. 
   Also, the above-described embodiment of the present invention is capable of providing dimming for electronic ballast fluorescent fixtures, using the same electronics and software as those described earlier with respect to magnetic ballast fluorescent fixtures. Tests performed by the inventors showed a dimming capability for several different types of electronic ballast fluorescent fixtures, without any noticeable flickering. Therefore, an apparatus and method according to different embodiments of the present invention can be used to control resistive, inductive, and/or capacitive loads, and even to control dimming of fluorescent light fixtures that are configured to screw into incandescent light sockets.