Patent Publication Number: US-10784791-B2

Title: Driving circuit allowing efficient turning-off of synchronous rectifiers

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of CN application No. 201810641012.0, filed on Jun. 21, 2018, and incorporated herein by reference. 
     FIELD OF THE INVENTION 
     The present invention relates generally to electronic circuits, more specifically but not exclusively to synchronous rectification. 
     BACKGROUND OF THE INVENTION 
     In a synchronous rectifying switching power supply, there is a synchronous rectifier which can be equivalent to an ideal transistor and a parasitic inductor that are serially coupled. The real drain-source voltage V DS  between the drain terminal and the source terminal of the ideal transistor is needed to be sampled and further regulated by a driving circuit to a preset value so that the output voltage of the synchronous rectifying switching power supply is regulated to a desired target value. In addition, the real drain-source voltage V DS  is compared with a reverse voltage threshold and when the drain-source voltage reaches the reverse voltage threshold, the ideal transistor is turned off to avoid a reverse current. 
     As it is difficult to sample the real drain-source voltage V DS  between the drain terminal and the source terminal of the ideal transistor. A regular way is to sample the drain-source detecting voltage V DSS  between the drain terminal and the source terminal of the synchronous rectifier which practically comprises the voltage drop V LP  across the parasitic inductor of the synchronous rectifier in addition to the real drain-source voltage V DS  of the ideal transistor. Especially, when the current flowing through the parasitic inductor is relatively large and/or the inductance of the parasitic inductor is relatively large, the voltage drop V LP  can be large, resulting a large difference between the drain-source detecting voltage V DSS  and the real drain-source voltage V DS . 
     As a result, if the synchronous rectifier is turned off when the drain-source detecting voltage V DSS  reaches the reverse voltage threshold, the efficiency will be low as this turn-off moment is actually ahead of the moment at which the real drain-source voltage V DS  reaches the reverse voltage threshold. 
     A traditional way to prevent false triggering is to decrease the driving voltage applied at the gate terminal of the synchronous rectifier so as to regulate the drain-source detecting voltage V DSS  at the preset value when the drain-source detecting voltage V DSS  reaches the preset value. Accordingly, the on-resistance of the synchronous rectifier SR is increased, which in turn reduces or eliminates the increase of the drain-source detecting voltage VDSS due to the decrease of the current flowing through the synchronous rectifier SR. As a result, the moment at which the synchronous rectifier SR is turned off when the drain-source detecting voltage VDSS reaches the reverse threshold voltage is closer to the ideal turn-off moment. However, the traditional way is inefficient. 
     Thus, there&#39;s a need to address at least the above mentioned or other issues. 
     SUMMARY 
     Embodiments of the present invention are directed to a driving circuit for driving a synchronous rectifier, wherein the synchronous rectifier is configured to comprise a drain terminal, a source terminal and a gate terminal, and a drain-source detecting voltage exists between the drain terminal and the source terminal, and wherein the driving circuit is configured to regulate the drain-source detecting voltage at a first reference voltage when the drain-source detecting voltage reaches a second reference voltage, wherein the first reference voltage is lower than the second reference voltage. 
     Embodiments of the present invention are also directed to a synchronous rectifying switching power supply, comprising: a primary circuit configured to receive an input signal and to provide an primary signal; a transformer having a primary winding and a secondary winding, wherein the primary winding is electrically coupled to the primary circuit to receive the primary signal; a synchronous rectifier electrically coupled between the secondary winding and a load, wherein the synchronous rectifier is configured to comprise a drain terminal, a source terminal and a gate terminal, and a drain-source detecting voltage exists between the drain terminal and the source terminal; and a driving circuit for driving the synchronous rectifier, wherein the driving circuit is configured to regulate the drain-source detecting voltage at a first reference voltage when the drain-source detecting voltage reaches a second reference voltage, wherein the first reference voltage is lower than the second reference voltage. 
     Embodiments of the present invention are further directed to a driving method for driving a synchronous rectifier, wherein the synchronous rectifier is configured to comprise a drain terminal, a source terminal and a gate terminal, and a drain-source detecting voltage exists between the drain terminal and the source terminal, and wherein the driving method comprises regulating the drain-source detecting voltage at a first reference voltage when the drain-source detecting voltage reaches a second reference voltage, wherein the first reference voltage is lower than the second reference voltage. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
       The present invention can be further understood with reference to the following detailed description and the appended drawings, wherein like elements are provided with like reference numerals. 
         FIG. 1  illustrates a synchronous rectifying switching power supply  100  in accordance with an embodiment of the present invention. 
         FIG. 2  illustrates a driving circuit  200  used as the driving circuit DR of the synchronous rectifying switching power supply  100  in accordance with an embodiment of the present invention. 
         FIG. 3  illustrates the relationship between the real drain-source voltage V DS  and the drain-source detecting voltage V DSS  of the synchronous rectifier SR. 
         FIG. 4  illustrates the waveforms of the drain-source detecting voltage V DSS  and the real drain-source voltage V DS  when the drain-source detecting voltage V DSS  is respectively regulated at the first reference voltage V REF1  and the second reference voltage V REF2  since the drain-source detecting voltage V DSS  reaches the second reference voltage V REF2 . 
         FIG. 5  illustrates a driving circuit  500  used as the driving circuit DR of the synchronous rectifying switching power supply  100  of  FIG. 1  in accordance with an embodiment of the present invention. 
         FIG. 6  illustrates a driving method  600  in accordance with an embodiment of the present invention. 
     
    
    
     DESCRIPTION 
     The present invention is now described. While it is disclosed in its preferred form, the specific embodiments of the invention as disclosed herein and illustrated in the drawings are not to be considered in a limiting sense. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Indeed, it should be readily apparent in view of the present description that the invention may be modified in numerous ways. Among other things, the present invention may be embodied as devices, methods, software, and so on. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or one embodiment combining software and hardware aspects. The following detailed description is, therefore, not to be taken in a limiting sense. 
     Throughout the specification, the meaning of “a,” “an,” and “the” may also include plural references. 
       FIG. 1  illustrates a synchronous rectifying switching power supply  100  in accordance with an embodiment of the present invention. As shown in  FIG. 1 , the synchronous rectifying switching power supply  100  is illustrated to comprise a primary circuit PR, a transformer T, a synchronous rectifier SR and a driving circuit DR. Specifically, the primary circuit PR is configured to receive an input signal VIN and then to convert the input signal VIN into a primary signal V P . The transformer T is configured to comprise a primary winding TP and a secondary winding TS, wherein the primary winding TP is electrically coupled to the primary circuit PR to receive the primary signal V P . The primary signal V P  can be a DC signal or an AC signal. The synchronous rectifier SR is electrically coupled between the secondary winding TS and a load RL. As shown in  FIG. 1 , the synchronous rectifier SR comprises a drain terminal D, a source terminal S and a gate terminal G, wherein the drain terminal D is electrically coupled to a first terminal of the secondary winding TS, and the source terminal S is electrically coupled to a first terminal of the load RL and a reference ground. Persons of ordinary skill in the art will recognize that, in another embodiment, the source terminal S of the synchronous rectifier SR may be coupled to the first terminal of the secondary winding TS, the drain terminal D may be coupled to the first terminal of the load RL. The driving circuit DR is electrically coupled to the gate terminal G of the synchronous rectifier SR so as to provide a gate voltage V GS  to control the turn-on, turn-off and/or the value of the on-resistance of the synchronous rectifier SR. As shown in  FIG. 1 , a secondary current I SEC  flows through the synchronous rectifier SR, which in turn results in a drain-source detecting voltage V DSS  between the drain terminal D and the source terminal S of the synchronous rectifier SR. In an embodiment, the synchronous rectifying switching power supply  100  may be an LLC resonant switching power supply, a flyback switching power supply or any other suitable type of switching power supply. Yet in another embodiment, the synchronous rectifier SR may be an N-type metal-oxide-semiconductor field effect transistor (NMOSFET). 
       FIG. 2  illustrates a driving circuit  200  used as the driving circuit DR of the synchronous rectifying switching power supply  100  in accordance with an embodiment of the present invention. 
     As shown in  FIG. 2 , the driving circuit  200  is configured to comprise an amplifying circuit EAO and a comparison circuit CMP. The amplifying circuit EAO comprises a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the amplifying circuit EAO is configured to receive the drain-source detecting voltage V DSS , the second input terminal of the amplifying circuit EAO is configured to receive a first reference voltage V REF1 , the output terminal of the amplifying circuit EAO is electrically coupled to the gate terminal G of the synchronous rectifier SR. The amplifying circuit EAO operates to output an amplifying signal S EAO  at the output terminal of the amplifying circuit EAO based on amplifying the difference between the first reference voltage V REF1  and the drain-source detecting voltage V DSS  and. In an embodiment, the first input terminal and the second input terminal of the amplifying circuit EAO are respectively an inverting input terminal (−) and a non-inverting input terminal (+). 
     The comparison circuit CMP comprises a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the comparison circuit CMP is configured to receive the drain-source detecting voltage V DSS , the second input terminal of the comparison circuit CMP is configured to receive a second reference voltage V REF2 , and the comparison circuit CMP is configured to output a comparison signal S CMP  at the output terminal of the comparison circuit CMP based on comparing the drain-source detecting voltage V DSS  with the second reference voltage V REF2  so as to control whether the amplifying signal S EAO  is provided to the gate terminal G of the synchronous rectifier SR or not, and wherein the second reference voltage V REF2  is larger than the first reference voltage V REF1 . More specifically, the amplifying signal S EAO  is provided to the gate terminal G of the synchronous rectifier SR when the drain-source detecting voltage V DSS  is larger than the second reference voltage V REF2 , and the amplifying signal S EAO  is not provided to the gate terminal G of the synchronous rectifier SR when the drain-source detecting voltage V DSS  is lower than the second reference voltage V REF2 . In an embodiment, the first input terminal and the second input terminal of the comparison circuit CMP are respectively a non-inverting input terminal (+) and an inverting input terminal (−). 
     Continue referring to  FIG. 2 , the driving circuit  200  may further comprise an off comparison circuit OFF which comprises a first input terminal, a second input terminal and an output terminal. The first input terminal of the off comparison circuit OFF is configured to receive the drain-source detecting voltage V DSS , the second input terminal of the off comparison circuit OFF is configured to receive an off reference voltage V ROFF , and the off comparison circuit OFF operates to output an off signal S OFF  at the output terminal of the off comparison circuit OFF based on comparing the drain-source detecting voltage V DSS  with the off reference voltage V ROFF  and so as to control the turn-off of the synchronous rectifier SR. More specifically, the synchronous rectifier SR is turned off when the off signal S OFF  is in an activated state; and the synchronous rectifier SR is not controlled by the off signal S OFF  when the off signal S OFF  is in a non-activated state. The off reference voltage V ROFF  is larger than the second reference voltage V REF2 . In more detail, when the drain-source detecting voltage V DSS  is larger than the off reference voltage V ROFF , the off signal S OFF  is in the activated state, and the synchronous rectifier SR is thus turned off. When the drain-source detecting voltage V DSS  is lower than the off reference voltage V ROFF , the off signal S OFF  is in the non-activated state, and the synchronous rectifier SR is thus not controlled by the off signal S OFF . In an embodiment, the first input terminal and the second input terminal of the off comparison circuit OFF are respectively a non-inverting input terminal (+) and an inverting input terminal (−). 
     Still refer to  FIG. 2 , the driving circuit  200  may further comprise an on comparison circuit ON. The on comparison circuit ON is configured to comprise a first input terminal, a second input terminal and an output terminal, wherein the first terminal of the on comparison circuit ON is configured to receive the drain-source detecting voltage V DSS , the second input terminal of the on comparison circuit ON is configured to receive an on reference voltage V RON , the on comparison circuit ON operates to output an on signal S ON  at the output terminal of the on comparison circuit ON based on comparing the drain-source detecting voltage V DSS  with the on reference voltage V RON  so as to control the turn-on of the synchronous rectifier SR. In more detail, the synchronous rectifier SR is turned on when the on signal S ON  is in an activated state, and the synchronous rectifier SR is not controlled by the on signal S ON  when the on signal S ON  is in a non-activated state. The on reference voltage V RON  is lower than the first reference voltage V REF1 . More specifically, when the drain-source detecting voltage V DSS  is lower than the on reference voltage V RON , the on signal S ON  in in its activated state, and the synchronous rectifier SR is thus turned on; when the drain-source detecting voltage V DSS  is larger than the on reference voltage V RON , the on signal S ON  is in its non-activated state, and the synchronous rectifier SR is thus not controlled by the on signal S ON . In an embodiment, the first terminal and the second terminal of the on comparison circuit ON are respectively an inverting input terminal (−) and a non-inverting input terminal (+). 
     In the embodiment in which the off comparison circuit OFF and the on comparison circuit ON are comprised, the driving circuit  200  may further comprise a RS flip-flop FF, a driver DRV, a first switch S 1 , a second switch S 2  and a logic circuit LOG. As shown in  FIG. 2 , the RS flip-flop FF comprises a set terminal S, a reset terminal R and an output terminal Q, wherein the set terminal S is electrically coupled to the output terminal of the on comparison circuit ON to receive the on signal S ON , and the reset terminal R is electrically coupled to the output terminal of the off comparison circuit OFF to receive the off signal S OFF . The driver DRV comprises an input terminal and an output terminal, wherein the input terminal of driver DRV is electrically coupled to the output terminal Q of the RS flip-flop FF to receive the signal output by the RS flip-flop FF. The first switch S 1  comprises a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch S 1  is electrically coupled to the output terminal of the driver DRV to receive the signal output by the driver DRV, and the second terminal of the driver DRV is electrically coupled to the gate terminal G of the synchronous rectifier SR. The second switch S 2  comprises a first terminal, a second terminal and a control terminal, wherein the first terminal of the second switch S 2  is electrically coupled to the output terminal of the amplifying circuit EAO to receive the amplifying signal S EAO , and the second terminal of the second switch S 2  is electrically coupled to the gate terminal G of the synchronous rectifier SR. The logic circuit LOG comprises a first input terminal I 1 , a second input terminal I 2 , a third input terminal I 3 , a first output terminal O 1  and a second output terminal O 2 . The first input terminal I 1  is electrically coupled to the on comparison circuit ON to receive the on signal S ON , the second input terminal I 2  is electrically coupled to the off comparison circuit OFF to receive the off signal S OFF , the third input terminal I 3  is electrically coupled to the comparison circuit CMP to receive the comparison signal S CMP , the first output terminal O 1  is configured to provide a first control signal S S1  to the control terminal of the first switch S 1  to control the turn-on or turn-off of the first switch S 1 , the second output terminal O 2  is configured to provide a second control signal S S2  to the control terminal of the second switch S 2  to control the turn-on or turn-off of the second switch S 2 , wherein the first control signal S S1  and the second control signal S S2  are complementary, namely, the second control signal S S2  is the inverting signal of the first control signal S S1 . The first control signal S S1  is in an activated state and the second control signal S S2  is in a non-activated state when the off signal S OFF  is in its activated state, namely, when the drain-source detecting voltage V DSS  is larger than the off reference voltage V ROFF . As a result, on one hand, the first control signal S S1  turns on the first switch S 1  and the second control signal S S2  turns off the second switch S 2 , and the gate terminal G of the synchronous rectifier the synchronous rectifier SR thus receives the output signal of the driver DRV and the synchronous rectifier SR is controlled by the output signal of the driver DRV. On the other hand, as the off signal S OFF  is in its activated state, the RS flip-flop FF is reset and provides a logic low signal (0) to the driver, and the driver DRV accordingly provides a logic low signal (0) to the gate terminal G of the synchronous rectifier SR to turn off the synchronous rectifier SR. 
     Persons of ordinary skill in the art will recognize that, when the off signal S OFF  is in its activated state, the drain-source detecting voltage V DSS  is larger than the off reference voltage V ROFF , thus accordingly, the comparison signal S CMP  is in its activated state and the on signal S ON  is in its non-activated state as the drain-source detecting voltage V DSS  is certainly larger than the second reference voltage V REF2  and the on reference voltage V RON . However, under this situation, the comparison signal S CMP  and the on signal S ON  will be override by the activated off signal S OFF . When the comparison signal S CMP  is in its activated state and the off signal S OFF  is in its non-activated state, the second control signal S S2  is in its activated state and the first control signal S S1  is in its non-activated state. Under this situation, on one hand, the second switch S 2  is turned on by the second control signal S S2  and the first switch S 1  is turned off by the first control signal S S1 , the gate terminal G of the synchronous rectifier SR receives the amplifying signal S EAO  output by the amplifying circuit EAO and the synchronous rectifier SR is thus controlled by the amplifying signal S EAO . More specifically, the amplifying signal S EAO  operates to regulate the value of the on-resistance of the synchronous rectifier SR, thus to regulate the drain-source detecting voltage V DSS  so that the drain-source detecting voltage V DSS  is maintained regulated at the first reference voltage V REF1 . Persons of ordinary skill in the art will recognize that, when the comparison signal S CMP  is in its activated state and the off signal S OFF  is in its non-activated state, the drain-source detecting voltage V DSS  is certainly larger than the on reference voltage V RON , namely, the on signal S ON  is in its non-activated state, as the drain-source detecting voltage V DSS  is larger than the second reference voltage V REF2 . However, under this situation, the on signal S ON  is override by the activated comparison signal S CMP  and the non-activated off signal S OFF , that is, the first control signal S S1  and the second control signal S S2  are relevant to the activated comparison signal S CMP  and the non-activated off signal S OFF  other than the on signal S ON . In an embodiment, the activated state refers to a logic high state (1) and the non-activated state refers to a logic low state (0). 
       FIG. 3  illustrates the relationship between the real drain-source voltage V DS  and the drain-source detecting voltage V DSS  of the synchronous rectifier SR. As shown in  FIG. 3 , in operation, the synchronous rectifier SR can be equivalent to an ideal transistor SR′ and a parasitic inductor LP which are serially coupled. Ideally, when the real drain-source voltage V DS  reaches the off reference voltage V ROFF , the synchronous rectifier SR is turned off. But in operation, it is the drain-source detecting voltage V DSS  that is compared with the off reference voltage V ROFF , and the synchronous rectifier SR is turned off when the drain-source detecting voltage V DSS  reaches the off reference voltage V ROFF . And the drain-source detecting voltage V DSS  between the drain terminal D and the source terminal S of the synchronous rectifier SR is the sum of the real drain-source voltage V DS  between the drain terminal DI and the source terminal SI of the ideal transistor SR′ and the parasitic voltage V LP  across the parasitic inductor LP, as shown in equation (1):
 
 V   DSS   =V   DS   +V   LP   (1)
 
wherein the parasitic voltage V LP  can be expressed as below in equation (2):
 
 V   LP   =L   LP   *di/dt   (2)
 
wherein L LP  represents the inductance of the parasitic inductor LP, di/dt represents the change rate of the current flowing through the parasitic inductor LP.
 
     As a result, as the drain-source detecting voltage V DSS  is larger than the real drain-source voltage V DS , especially when di/dt is large, the synchronous rectifier SR cannot be regulated promptly and is turned off ahead of the ideal turn-off moment. 
       FIG. 4  illustrates the waveforms of the drain-source detecting voltage V DSS  and the real drain-source voltage V DS  when the drain-source detecting voltage V DSS  is respectively regulated at the first reference voltage V REF1  and the second reference voltage V REF2  since the drain-source detecting voltage V DSS  reaches the second reference voltage V REF2 . Curve  1  represents the real drain-source detecting voltage V DSS  when it is regulated at the second reference voltage V REF2  since the moment t 0  at which the drain-source detecting voltage V DSS  reaches the second reference voltage V REF2 . Curve  2  represents the ideal drain-source voltage V DSS  when the drain-source detecting voltage V DSS  is regulated at the second reference voltage V REF2  since the moment t 0  at which the drain-source detecting voltage V DSS  reaches the second reference voltage V REF2 . Curve  3  represents the real drain-source detecting voltage V DSS  when it is regulated at the first reference voltage V REF1  since the moment t 0  at which the drain-source detecting voltage V DSS  reaches the second reference voltage V REF2 . Curve  4  represents the ideal drain-source voltage V DSS  when the drain-source detecting voltage V DSS  is regulated at the first reference voltage V REF1  since the moment t 0  at which the drain-source detecting voltage V DSS  reaches the second reference voltage V REF2 . 
     The operation of the driving circuit  200  will now be set forth with reference to  FIG. 2  and  FIG. 4 . As shown in  FIG. 2  and  FIG. 4 , as the secondary current I SEC  reduces, the drain-source detecting voltage V DSS  increases gradually, and at moment t 0 , the drain-source detecting voltage V DSS  increases to the second reference voltage V REF2 , thus, the comparison signal S CMP  transits to the activated state (logic high 1). On the other hand, as the drain-source detecting voltage V DSS  is still lower than the off reference voltage V ROFF , the off signal S OFF  is in its non-activated state (logic low 0), thus, the second control signal S S2  is in its activated state (logic high 1) and the first control signal S S1  is in its non-activated state (logic low 0). As a result, the second switch S 2  is turned on by the second control signal S S2  and the first switch S 1  is turned off by the first control signal S S1 , and the gate terminal G of the synchronous rectifier SR receives the amplifying signal S EAO  output by the amplifying circuit EAO and the synchronous rectifier SR is controlled by the amplifying signal S EAO . 
     More specifically, as the drain-source detecting voltage V DSS  increases, the difference between the first reference voltage V REF1  and the drain-source detecting voltage V DSS  becomes lower, and accordingly the amplifying signal S EAO  becomes lower and the on-resistance of the synchronous rectifier SR increases. Thus, the increase of the drain-source detecting voltage V DSS  due to the reduction of the secondary current I SEC  is reduced or eliminated, regulating the drain-source detecting voltage V DSS  at the first reference voltage V REF1 . The driving voltage applied at the gate terminal G of the synchronous rectifier SR is lowered to a relatively low level before the synchronous rectifier SR is turned off, which in turn helps to improve the speed of the turn-off of the synchronous rectifier SR. As shown by curve  3 , as the drain-source detecting voltage V DSS  increases, at moment t 2 , the drain-source detecting voltage V DSS  reaches the off reference voltage V ROFF , and consequently, the off signal S OFF  transits to the activated state (logic high 1), and in turn, the first control signal S S1  transits to its activated state (logic high 1) and the second control signal S S2  transits to its non-activated state (logic low 0). As a result, on one hand, the first switch S 1  is turned on by the first control signal S S1  and the second switch S 2  is turned off by the second control signal S S2 , thus, the gate terminal G of the synchronous rectifier SR receives the signal output by the driver DRV so that the synchronous rectifier SR is controlled by the output signal output by the driver DRV. On the other hand, the activated state of the off signal S OFF  resets the RS flip-flop FF and the RS flip-flop FF thus outputs a logic low signal (0) to the driver DRV which in turn outputs a logic low signal (0) to the gate terminal G of the synchronous rectifier SR. Consequently, the synchronous rectifier SR is turned off. 
       FIG. 5  illustrates a driving circuit  500  used as the driving circuit DR of the synchronous rectifying switching power supply  100  of  FIG. 1  in accordance with an embodiment of the present invention. The driving circuit  500  of  FIG. 5  has a similar configuration as that of the driving circuit  200  of  FIG. 2 , except that the RS flip-flop FF, the driver DRV, the first switch S 1 , the second switch S 2  and the logic circuit LOG in  FIG. 2  are all replaced by the driving stage DRSTG of  FIG. 5 , wherein the driving stage DRSTG comprises a high-side switch M 1  and a low-side switch M 2 . The high-side switch M 1  comprises a first terminal, a second terminal and a control terminal, wherein the first terminal of the high-side switch M 1  is electrically coupled to a power supply VCC, the control terminal of the high-side switch M 1  is electrically coupled to the output terminal of the on comparison circuit ON to receive the on signal S ON . The low-side switch M 2  comprises a first terminal, a second terminal and a control terminal, wherein the first terminal of the low-side switch M 2  is electrically coupled to the second terminal of the high-side switch M 1 , the second terminal of the low-side switch M 2  is electrically coupled to the reference ground, and the control terminal of the low-side switch M 2  is electrically coupled to the output terminal of the off comparison circuit OFF to receive the off signal S OFF . The gate terminal G of the synchronous rectifier SR is electrically coupled to the second terminal of the high-side switch M 1 , the first terminal of the low-side switch M 2  and the output terminal of the amplifying circuit EAO. In addition, in the driving circuit  500  in  FIG. 5 , the amplifying circuit EAO comprises a control terminal which is electrically coupled to the output terminal of the comparison circuit CMP to receive the comparison signal S CMP , and the amplifying circuit EAO is allowed to provide the amplifying signal S EAO  when the comparison signal S CMP  is in its activated state, and the amplifying circuit EAO is not allowed to provide the amplifying signal S EAO  when the comparison signal S CMP  is in its non-activated state. 
     In operation, when the drain-source detecting voltage V DSS  is lower than the on reference voltage V RON , the on signal S ON  is in its activated state and the high-side switch M 1  is turned on. Meanwhile, when the drain-source detecting voltage V DSS  is lower than the on reference voltage V RON , the drain-source detecting voltage V DSS  is certainly lower than the off reference voltage V ROFF , the off signal S OFF  is in its non-activated state, the low-side switch M 2  is turned off, as a result, the gate terminal G of the synchronous rectifier SR is electrically coupled to the power supply VCC, and the synchronous rectifier SR is turned on. When the drain-source detecting voltage V DSS  is larger than the off reference voltage V ROFF , the off signal S OFF  is in its activated state, the low-side switch M 2  is turned on. Meanwhile, when the drain-source detecting voltage V DSS  is larger than the off reference voltage V ROFF , the drain-source detecting voltage V DSS  is certainly larger than the on reference voltage V RON , the on signal S ON  is in its non-activated state, and the high-side switch M 1  is turned off, and the gate terminal G of the synchronous rectifier SR is electrically coupled to the reference ground and the synchronous rectifier SR is turned off. When the drain-source detecting voltage V DSS  is larger than the second reference voltage V REF2  and lower than the off reference voltage V ROFF , on one hand, the comparison signal S CMP  is in its activated state, which in turn enables the amplifying circuit EAO so that the amplifying circuit EAO outputs the amplifying signal S EAO , on the other hand, when the drain-source detecting voltage V DSS  is larger than the second reference voltage V REF2  and lower than the off reference voltage V ROFF , the drain-source detecting voltage V DSS  is certainly larger than the on reference voltage V RON , thus, the on signal S ON  and the off signal S OFF  are both in the non-activated state, and the driving stage DRSTG is in a high-z state, the gate terminal G of the synchronous rectifier SR is electrically coupled to the output terminal of the amplifying circuit EAO to receive the amplifying signal S EAO , and the on-resistance of the synchronous rectifier SR is regulated by the amplifying signal S EAO . 
     The operation of the driving circuit  500  will now be set forth with reference to  FIG. 4  and  FIG. 5 . As shown in  FIG. 4  and  FIG. 5 , as the secondary current I SEC  reduces, the drain-source detecting voltage V DSS  increases gradually. At moment t 0 , the drain-source detecting voltage V DSS  increase to the second reference voltage V REF2 , the comparison signal S CMP  transits to the activated state (logic high 1) which in turn enables the amplifying circuit EAO and the amplifying circuit EAO outputs the amplifying signal S EAO . At this moment, as the drain-source detecting voltage V DSS  is lower than the off reference voltage V ROFF , the off signal S OFF  is in its non-activated state (logic low 0), the low-side switch M 2  is turned off; and as the drain-source detecting voltage V DSS  is larger than the on reference voltage V RON , the on signal S ON  is in its non-activated state (logic low 0), the high-side switch M 1  is turned off, thus, the gate terminal G of the synchronous rectifier SR receives the amplifying signal S EAO  output by the amplifying circuit EAO and the synchronous rectifier SR is controlled by the amplifying signal S EAO . More specifically, as the drain-source detecting voltage V DSS  increases, the difference between the first reference voltage V REF1  and the drain-source detecting voltage V DSS  reduces, the amplifying signal S EAO  becomes lower, causing the on-resistance of the synchronous rectifier SR to increase, which in turn reduces or eliminates the increase of the drain-source detecting voltage V DSS  due to the reduction of the secondary current I SEC , regulating the drain-source detecting voltage V DSS  at the first reference voltage V REF1 . The driving voltage applied at the gate terminal G of the synchronous rectifier SR is lowered to a relatively low level before the synchronous rectifier SR is turned off, which in turn helps to improve the speed of the turn-off of the synchronous rectifier SR. This is because that before the drain-source detecting voltage V DSS  reaches the second reference voltage V REF2 , the gate terminal G of the synchronous rectifier SR is electrically coupled to the high level power supply VCC, which helps to improve the system efficiency. As the drain-source detecting voltage V DSS  increase slowly anyway, as shown by curve  3 , at moment t 2 , the drain-source detecting voltage V DSS  reaches the off reference voltage V ROFF , the off signal S OFF  transits to the activated state (logic high 1), the low-side switch M 2  is turned on, and the gate terminal G of the synchronous rectifier SR is electrically coupled to the reference ground and the synchronous rectifier SR is turned off. 
     As shown in  FIG. 4 , moment t 1  represents the moment at which the drain-source detecting voltage V DSS  reaches the off reference voltage V ROFF  in the traditional scheme where the drain-source detecting voltage V DSS  is regulated at the second reference voltage V REF2  when the drain-source detecting voltage V DSS  reaches the second reference voltage V REF2 ; moment t 2  represents the moment at which the drain-source detecting voltage V DSS  reaches the off reference voltage V ROFF  in the embodiments of the present invention where the drain-source detecting voltage V DSS  is regulated at the first reference voltage V REF1  when the drain-source detecting voltage V DSS  reaches the second reference voltage V REF2 ; and moment t 3  represents the ideal turn-off moment. As can be observed from  FIG. 4 , the moment t 2  is closer to the ideal turn-off moment t 3  than the moment t 1  is. That is, compared with the traditional scheme when the drain-source detecting voltage V DSS  is regulated at the second reference voltage V REF2 , in the embodiments in accordance with the present invention, the real turn-off moment is closer to the ideal turn-off moment, which helps to prevent the synchronous rectifier SR from being falsely turned off more efficiently. In another word, at the same moment, such as at the moment t 4  shown in  FIG. 4 , the drain-source detecting voltage V DSS2  obtained with the embodiments in accordance with the present invention is lower than the drain-source detecting voltage V DSS1  obtained using the prior-art technology, as a result of which, it is more efficient to prevent the synchronous rectifier SR from being turned off ahead of the ideal turn-off moment because of that the drain-source detecting voltage V DSS  reaches the off reference voltage V ROFF , and thus, when the synchronous rectifier SR is turned off, the secondary current I SEC  approaches more closely to zero. 
       FIG. 6  illustrates a driving method  600  in accordance with an embodiment of the present invention. Similarly to the embodiment of  FIG. 1 , in the embodiment of  FIG. 6 , a synchronous rectifier SR comprises a drain terminal D, a source terminal S and a gate terminal G, and there exists a drain-source detecting voltage V DSS  between the drain terminal D and the source terminal S of the synchronous rectifier SR, the gate terminal G is driven by a gate voltage V GS . The driving method  600  comprises steps  601  and  602 . In step  601 , judge if the drain-source detecting voltage V DSS  reaches a second reference voltage V REF2  or not, if yes, step  602  is performed. In step  602 , the gate voltage V GS  of the synchronous rectifier SR is lowered down so as to regulate the drain-source detecting voltage V DSS  at a first reference voltage V REF1 , wherein the first reference voltage V REF1  is lower than the second reference voltage V REF2 . 
     In an embodiment, the driving method  600  may further comprise a step of turning off the synchronous rectifier SR when the drain-source detecting voltage V DSS  reaches an off reference voltage V ROFF , wherein the off reference voltage V ROFF  is larger than the second reference voltage V REF2 . In another embodiment, the driving method  600  may further comprise a step of turning on the synchronous rectifier SR when the drain-source detecting voltage V DSS  reaches the on reference voltage V RON , wherein the on reference voltage V RON  is lower than the first reference voltage V REF1 . 
     It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described herein above. Rather the scope of the present invention is defined by the claims and includes both combinations and sub-combinations of the various features described hereinabove as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not in the prior art.