Patent Publication Number: US-10777651-B2

Title: Gate stacks

Description:
PRIORITY APPLICATION 
     This application is a continuation of U.S. application Ser. No. 14/688,337, filed Apr. 16, 2015, which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     Gate stacks including a tungsten silicide (WSix) material tier with topography may suffer from WSix cracking, which may affect gate functional reliability. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document. 
         FIG. 1A  is a cross-sectional view illustrating an example of a gate stack according to a first embodiment. 
         FIG. 1B  is a cross-sectional view illustrating a cracked gate stack according to the first embodiment. 
         FIG. 2  is a cross-sectional view illustrating an example of a gate stack according to a second embodiment. 
         FIG. 3  is a cross-sectional view illustrating an example of a gate stack according to a third embodiment. 
         FIG. 4  is a process flow diagram illustrating a process of fabricating a gate stack according to an embodiment. 
         FIG. 5  is a process flow diagram illustrating a process of fabricating a gate stack according to another embodiment. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     The following detailed description refers to the accompanying drawings which show, by way of illustration, specific aspects and embodiments in which the present subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present subject matter. 
     The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer, such as a substrate, regardless of the actual orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side”, “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the actual orientation of the wafer or substrate. 
     The terms “wafer” and “substrate” are used herein to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. 
       FIG. 1A  is a cross-sectional view illustrating an example of a gate stack  100  according to a first embodiment. The gate stack  100  may include an NAND complementary metal-oxide semiconductor (CMOS) gate. In some embodiments, the gate stack  100  may include a gate  10  formed horizontally between shallow trench isolations (STIs)  20  (e.g., silicon oxide), and a WSix material  30  formed over the gate  10  and the STIs  20 . In many situations, the height of the gate  10  is generally different from the height of the STIs  20 . As shown in  FIG. 1A , for example, the gate  10  is higher than the STIs  20 , and thus a top surface of the gate  10  and top surfaces of the STIs  20  are not on a same level. In some embodiments, the gate  10  may include a polysilicon (poly) material. Weak spots  30 A may be formed at low material density regions as deposited due to topography, and may cause integration issues within the gate stack  100 . In some embodiments, the gate stack  100  may further include a gate oxide  40  (e.g., silicon oxide), which is formed vertically between the gate  10  and a channel  50 . The channel  50  may include a single crystalline silicon active area. 
       FIG. 1B  is a cross-sectional view illustrating a cracked gate stack  100  according to the first embodiment. Over some processing steps during a fabrication of the gate stack  100  with topography, WSix grains may grow, and may thus introduce volume shrinkage and large tensile stress, which may cause some open cracks  30 B at low density areas (such as weak spots  30 A as shown in  FIG. 1A ). For example, during the fabrication of the gate stack  100 , after receiving a thermal treatment with a thermal budget, cracks  30 B may be formed at the weak spots  30 A of the WSix material  30 . Such cracks  30 B may result in broken gate reliability, and thus may yield concerns to the gate stack  100 . 
       FIG. 2  is a cross-sectional view illustrating an example of a gate stack  200  according to a second embodiment. In some embodiments, the gate stack  200  may include a gate  10  formed between STIs  20 , a WSix material  30  formed on a top surface of the poly material  10  and top surfaces of the STIs  20 , and a tungsten silicon nitride (WSiN) material  60  as a cap on a top surface of the WSix material  30 . In some embodiments, the WSiN material  60  has a thickness in a range from 50 A to 200 A. Weak spots  30 A (as shown in  FIG. 1A ) may be formed at low material density regions due to topography. 
     Compared with the WSix material  30 , the WSiN material  60  may have a higher resistance to grain growth under a thermal treatment, may experience smaller volume shrinkage and stress build-up, and thus may be more stable than the WSix material  30  during the thermal treatment. The WSiN material  60  in the gate stack  200  may function as both a stress stabilization layer and a crack propagation barrier to limit the crack formation and propagation. Such a hybrid WSix/WSiN stack structure may mitigate possible WSix cracking of the WSix material deposited on the gate stack with topography. A crack-free gate stack may thus be achieved with such a hybrid WSix/WSiN stack. 
     In some embodiments, the gate stack  200  may further include a dielectric material (e.g., tetraethyl orthosilicate (TEOS))  70  formed on a top surface of the WSiN material  60 . In some embodiments, the gate stack  200  may further include a gate oxide  40  fainted between the poly material  10  and a channel  50 . The channel  50  may include a single crystalline silicon active area. The gate stack  200  may include a source and a drain (not shown in the figures). The gate stack  200  may be used in a peripheral transistor of a three dimension (3D) NAND flash memory or other memories such as a planar nonvolatile memory or a volatile memory. 
       FIG. 3  is a cross-sectional view illustrating an example of a gate stack  300  according to a third embodiment. 
     In some embodiments, the gate stack  300  may include a gate  10  formed between STIs  20 , a first WSix material  30  formed on a top surface of the gate  10  and top surfaces of the STIs  20 , a WSiN interlayer material  60  on a top surface of the first WSix material  30 , and a second WSix material  80  on a top surface of the WSiN interlayer material  60 . In some embodiments, a thickness of the WSiN interlayer material  60  is approximately of 50 A to 200 A. Weak spots  30 A may be formed at low material density regions as deposited due to topography. 
     Compared with a WSix material (such as the first WSix material  30  and the second WSix material  80 ), the WSiN interlayer material  60  may have a higher resistance to grain growth under a thermal treatment, may experience smaller volume shrinkage and stress build-up, and thus may be more stable than the WSix material during the thermal treatment. The WSiN interlayer material  60  in the gate stack  300  may function as both a stress stabilization layer and a crack propagation barrier to limit the crack formation and propagation. For example, even when cracks are formed in the first WSix material  30 , the WSiN interlayer  60  may block the cracks to prevent the cracks from propagating through the whole stack. Therefore, such a hybrid WSix/WSiN/WSix stack structure may mitigate possible WSix cracking of the WSix material deposited on the gate stack with topography. A crack-free gate stack may thus be achieved with such a hybrid WSix/WSiN/WSix stack. The gate stack  300  may be used in a peripheral transistor of a 3D NAND flash memory or other memories such as a planar nonvolatile memory or a volatile memory. 
     In some embodiments, the gate stack  300  may further include a TEOS material formed over the second WSix material  80 . In some embodiments, the gate stack  300  may further include a gate oxide  40  formed between the poly material  10  and a channel  50 . The gate stack  300  may include a source and a drain (not shown in the figures). 
       FIG. 4  is a process flow diagram illustrating a process  400  of fabricating a gate stack  200  as shown in  FIG. 2  according to an embodiment. 
     At  402 , a gate structure may be formed on a substrate (such as a silicon material). The gate structure may include a gate  10  (such as a poly material) horizontally between STIs  20  (e.g., silicon oxide) as shown in  FIG. 2 . In some embodiments, the gate structure may further include a gate oxide  40  formed vertically between the poly material  10  and a channel  50 . The channel  50  may include a single crystalline silicon active area. The gate structure may include a source and a drain (not shown in the figures). 
     At  404 , a WSix tier  30  may be formed over the gate  10  and the STIs  20 . In some embodiments, in a Physical Vapor Deposition (PVD) chamber, WSix may be deposited on the top surface of the gate  10  and the top surfaces of the STIs  20  to form the WSix tier  30 . 
     At  406 , a WSiN tier  60  may be formed on a top surface of the WSix tier  30  as a cap. In some embodiments, in the chamber (e.g., the PVD chamber used to form the WSix tier  30 ), a WSix material may be sputtered on the top surface of the WSix tier  30 , while adding nitrogen gas into the chamber, to incorporate nitrogen into the sputtered WSix material to form the WSiN tier  60 . In some embodiments, in the chamber used to form the WSix tier  30 , a WSiN material may be directly sputtered on the top surface of the WSix tier  30  to form the WSiN tier  60 . 
     These methods of fabricating a gate stack are flexible, and the whole fabrication process can be done in the same PVD chamber for example. In this way, it can be easier to control the location and thickness of the WSix tier  30  and the WSiN tier  60  individually in the hybrid WSix/WSiN stack. Additionally, these methods of fabricating a gate stack are integration-friendly. The WSix tier  30  in the hybrid WSix/WSiN stack may act as an interface layer, and the WSiN tier  60  (with nitrogen up to e.g., 13%) may not provide any dry etch concerns due to the small amount of nitrogen. 
     In some embodiments, in an implant chamber, nitrogen may be implanted into an upper portion of the WSix tier  30  to transform the upper portion of the WSix material into a WSiN material to form the WSiN tier  60 . 
     In some embodiments, a dielectric material (e.g., TEOS) tier  70  may be formed on a top surface of the WSiN tier  60 . 
       FIG. 5  is a process flow diagram illustrating a process  500  of fabricating a gate stack  300  according to another embodiment. 
     At  502 , a gate structure may be formed on another material, such as a substrate. The gate structure may include a gate  10  (such as a poly material) horizontally between STIs  20  (e.g., silicon oxide) as shown in  FIG. 3 . In some embodiments, the gate structure may further include a gate oxide  40  formed vertically between the gate  10  and a channel  50 . The channel  50  may include a single crystalline silicon active area. 
     At  504 , a first WSix tier  30  may be formed over the gate  10  and the STIs  20 . In some embodiments, in a chamber (e.g., a PVD chamber), WSix may be deposited on the top surface of the gate  10  and the top surfaces of the STIs  20  to form the first WSix tier  30 . 
     At  506 , a WSiN interlayer tier  60  may be formed on a top surface of the first WSix tier  30 . 
     In some embodiments, in the PVD chamber used to form the first WSix tier  30 , while adding nitrogen gas into the chamber, a WSix material may be sputtered on the top surface of the first WSix tier  30  to incorporate nitrogen into the sputtered WSix to form the WSiN interlayer tier  60 . In some embodiments, in the PVD chamber used to form the first WSix tier  30 , a WSiN material may be directly sputtered on the top surface of the first WSix tier  30  to form the WSiN interlayer tier  60 . In some embodiments, in an implant chamber, nitrogen may be implanted into an upper portion of the first WSix tier  30  to transform the upper portion of the WSix material into a WSiN material to form the WSIN interlayer tier  60 . 
     At  508 , a second WSix tier  80  may be formed on a top surface of the WSiN interlayer tier  60 . In some embodiments, in the same PVD chamber used to form the first WSix tier  30  and the WSiN interlayer tier  60 , a WSix material may be directly deposited to form the second WSix tier  80  on the top surface of the WSiN interlayer tier  60 . 
     In some embodiments, a dielectric material (e.g., TEOS) tier  70  may be formed over the second WSix tier  80 . 
     The above description and the drawings illustrate some embodiments of the invention to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of others. Many other embodiments will be apparent to those of ordinary skill in the art upon reading and understanding the above description.