Patent Publication Number: US-8527928-B1

Title: Optimizing circuit layouts by configuring rooms for placing devices

Description:
This application is a divisional application of U.S. patent application Ser. No. 11/231,055, filed on Sep. 19, 2005, and issued Feb. 16, 2010, as U.S. Pat. No. 7,665,054, the contents of which are hereby incorporated by reference as if set forth in their entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates generally to circuit layouts and more particularly to optimizing circuit layouts for analog and RF (radio frequency) circuits. 
     Circuit design for analog and RF circuits poses a number of unique challenges. In order for a circuit to perform correctly when manufactured using a semi-conductor process, several techniques have been employed when positioning devices (i.e., analog and RF devices) in the layout. 
     For example, a common technique involves matching the ratios of sizes, orientations and other properties between one or more devices in order to achieve electrical equivalence between these devices when manufactured. Additionally, in order to minimize the influence of process variations, certain groups of devices are placed in close proximity to each other. Another common matching technique involves positioning devices “symmetrically” by mirroring their orientations and usually aligning them in one dimension an equal distance from a specified symmetry line. 
     Analog and RF circuits often have several groups of devices, where each group must be individually arranged in proximity to one another as described above and where each group often requires local symmetry lines to position devices in symmetric arrangements within that group. Grouping of devices is also performed to isolate certain devices from other groups by surrounding them with a guard-ringed structure in the layout, or inserting them into a certain type of well in the semiconductor process. Once these devices are grouped, an additional requirement involves matching variations across these groups. This is accomplished by aligning the symmetry lines of these groups with respect to each other or by aligning the group boundaries with respect to each other. Sometimes, two or more devices that need to be matched very strongly may be combined into a single layout instance, often referred to as a “compound device.” These devices may be combined using user specified patterns to ensure perfect matching. 
     An additional objective when arranging these devices is to minimize the lengths of various connections between the devices in the circuit. These connections are often implemented using metal wires, and minimizing their lengths reduces the amount of space and material needed for implementation. Further, the resistances and capacitances introduced by these wires can adversely affect the electrical behavior of the circuit, and these effects need to be minimized as well. Certain connections in the circuit sometimes have more impact on the performance than other connections. It is therefore desirable to reduce lengths of specific paths or connections depending on the flow of currents and signals through the circuit. These signal and current paths are often identified by circuit designers who perform simulations of the electrical behavior of the circuit. This information is then either conveyed to a layout designer, who arranges the devices in the layout, or is used by the circuit designers themselves if they implement the layout on their own. An example involves identifying DC current paths through the circuit from the current source (often the positive voltage source, VDD) to the current sinks (often the negative voltage source, VSS, or the ground connection, GND). The devices in the layout are then arranged to minimize the lengths of wires connecting from the current sources to various devices and then to the current sinks. 
     While accounting for these various considerations, it is also necessary to meet several process design rule criteria for successful fabrication. An example is the restriction imposed on the minimum spacing between geometry on a given mask layer. This further imposes restrictions on the distances between various devices in the layout. Another objective is to minimize the total area occupied by all the devices, in order to minimize the mask costs during fabrication. 
     In some contexts, circuit layout design is discussed in terms of cell layout design, where a cell is a device arrangement that can be used as a building block for larger circuits. Then the area of a given cell may also be constrained by how this cell is packaged along with other cells when finishing the block-level layout. These constraints may be captured as restrictions on the height and/or width of the cell layout. Sometimes, the shape of the cell area may also be restricted to a certain rectilinear arrangement to fit with other cells. For example, the cell may be L-shaped instead of rectangular. Certain regions in the cell layout may also be designated as “keep-out” regions where one may not place any other devices. This latter construct is useful to reserve space for inserting other devices and/or geometry at a later point in the design cycle. 
     Currently most designers implement their semiconductor layouts manually for analog and RF circuits. Positioning the devices for matching, symmetry, grouping, minimizing area, wire-length, lengths of signal paths, etc., is performed by hand. Information regarding matching requirements, symmetry, critical signal and DC paths, observed from electrical simulations, is often annotated as text or graphics on the schematic by the designers. The layout designer then uses this information as a guideline when positioning these devices. At other times, for simplicity, the layout designer may position the devices as they are observed on the schematic, assuming that the positions of these devices on the schematic are an indication of the proximity of devices and optimal with regard to minimum lengths of critical signal or current paths. Another simple approach involves looking at previous implementations of the circuit, for example, a layout performed for a similar schematic, or a layout performed for a different set of device parameters for the same schematic, or a circuit implemented in a different semiconductor technology for the same or similar schematic. The layout designer then arranges the layout to look similar to the previous layout, with regard to the positioning of certain devices and/or groups of devices. 
     Some constraints like matching, symmetry and design rules, however, are very difficult to precisely implement by hand. Further, since there are a large number of possible arrangements of devices in a layout, it can be very difficult to analyze the impact of multiple tradeoffs between objectives like wire-length, area and lengths of signal paths manually. To address this, some conventional tools automate the generation of Analog and RF layouts by capturing these requirements as analytical constraints, possibly represented on a discrete grid for placing devices. Some of these approaches are described, for example, in analog design articles. (A. Shah, S Dugalleix and F Lemery, “High-performance CMOS-amplifier design uses front-to-back analog flow”, EDN design feature, Oct. 31, 2002.) However, these tools are typically limited in their ability to optimize performance features while imposing design constraints such as symmetry, matching and grouping. For example, a grid formulation may limit placement options such as the orientation of devices. Further, these tools are also typically limited in their ability to support “layout migration”, where a previously determined layout is taken as a starting point for a modified set of constraints or optimization criteria. 
     Thus, there is a need for improved methods and systems for optimizing circuit layouts, especially in applications involving analog and RF circuits. 
     SUMMARY OF THE INVENTION 
     In one embodiment of the present invention, a computer-readable medium stores a specification for a circuit layout. The specification includes: a configuration of rooms for placing devices, one or more room constraints for the configuration of rooms, one or more groups of devices for the rooms, and one or more device constraints for devices in a same room. 
     According to one aspect of this embodiment, the configuration of rooms may include a tree-structure for the rooms. According to another aspect, the room constraints may include a common symmetry line for a first room and a second room. According to another aspect, the device constraints may include a self-symmetry constraint for a first device about a symmetry line in a first room. According to another aspect, the device constraints may include a symmetry constraint for a first device and a second device about a symmetry line in a first room. According to another aspect, the devices may be analog or RP (radio frequency) devices. 
     In another embodiment of the present invention, a system for determining a specification for a circuit layout includes a user interface and a computer-readable medium. The user interface receives input from a user for determining a configuration of rooms for placing devices, one or more room constraints for the configuration of rooms, one or more groups of devices for the rooms, and one or more device constraints for devices in a same room. The computer-readable medium stores the specification for the circuit layout, where the specification includes the configuration of rooms, the one or more room constraints, the one or more groups of devices, and the one or more device constraints. 
     This embodiment may include aspects described above. According to another aspect, the user interface may include a graphical user interface that displays a tree-structure for the configuration of rooms. Further, the graphical user interface may display a reference circuit layout and the input from the user may determine at least some of the tree-structure from the reference circuit layout. Further, the graphical user interface may display a reference circuit schematic, and the input from the user may determine at least some of the tree-structure from the reference circuit schematic. 
     In another embodiment of the present invention, a method of determining a circuit layout includes: determining a configuration of rooms for placing devices, determining one or more room constraints for the configuration of rooms, determining one or more groups of devices for the rooms, and determining one or more device constraints for devices in a same room. 
     This embodiment may include aspects described above. According to another aspect, the method may further include determining, from the configuration of rooms, the one or more room constraints, the one or more groups of devices, and the one or more device constraints, a first placement of devices and a first positioning of rooms. The first placement of devices includes first spatial coordinates for the devices in the rooms, and the first positioning of rooms includes first spatial coordinates for boundaries of the rooms. 
     Further, the configuration of rooms may include a tree-structure for the rooms, and determining the first placement of devices and the first positioning of rooms may include searching the tree structure to determine the placement of the devices in each room and the positioning of said each room. 
     Further, the method may include: determining, from the first placement of devices and the first positioning of rooms, a first cost value; determining, from the first placement of devices, a second placement of devices, wherein the second placement of devices includes second spatial coordinates for the devices in the rooms; determining, from the first positioning of rooms and the second placement of devices, a second positioning of rooms, wherein the second positioning of rooms includes second spatial coordinates for the boundaries of the rooms; and determining, from the second placement of devices and the second positioning of rooms, a second cost value. Further, determining the second placement of devices may include perturbing the first placement of devices. 
     Additional embodiments relate to an apparatus that carries out the method and a computer-readable medium that stores (e.g., tangibly embodies) a computer program that carries out the method. 
     In this way the present invention enables improved methods and systems for optimizing circuit layouts, especially in applications involving analog and RF circuits. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows an exemplary method for optimizing a circuit layout. 
         FIG. 2  shows an exemplary method for creating a cell-plan. 
         FIG. 3  shows an exemplary cell-plan design with symmetry constraints. 
         FIG. 4  shows an exemplary cell-plan design with a keep-out region. 
         FIG. 5  shows an exemplary string format for a cell-plan tree. 
         FIG. 6  shows an exemplary binary-tree representation of a cell-plan. 
         FIG. 7  shows an exemplary cell-plan string related to the embodiment shown in  FIG. 6 . 
         FIG. 8  shows an exemplary binary-tree representation of a cell-plan. 
         FIG. 9  shows an exemplary cell-plan string related to the embodiment shown in  FIG. 8 . 
         FIG. 10  shows an exemplary circuit schematic. 
         FIG. 11  shows an exemplary cell plan and corresponding layout related to the embodiment shown in  FIG. 10 . 
         FIG. 12  shows an exemplary method for making a slicing-tree representation for a configuration of rooms. 
         FIG. 13  shows an exemplary augmentation of a slicing-tree representation to include constrained-component-trees. 
         FIG. 14  shows an exemplary placement method where members of a constrained-component-tree are placed within a room. 
         FIG. 15  shows an exemplary slicing-tree representation, including constrained-component-trees, together with a focus on the sizing of a specific node. 
         FIG. 16  shows exemplary alignments of boundary lines and symmetry lines within rooms in a cell-plan. 
         FIG. 17  shows an exemplary representation of a keep-out region in a cell-plan. 
         FIG. 18  shows an exemplary method for optimizing a circuit layout. 
     
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     An embodiment of the present invention is shown in  FIG. 1 . A method  102  for optimizing a circuit layout includes determining a first layout specification  104  that includes a configuration of rooms for placing devices, one or more room constraints for the configuration of rooms, one or more groups of devices for the rooms, and one or more device constraints for devices in the same room. More specific examples of a specification  104  are discussed below to illustrate arrangements that include constraints on rooms and devices for a circuit layout with particular focus on analog and RF (radio frequency) layouts although other applications are possible. A first cost value  106  measures one or more optimization criteria such a path length, area, or gain. Next a second specification  108  is determined possibly by some adjustment or perturbation of the first specification  104  and a corresponding second cost value  110  is determined for comparison with the first cost value  106 . This process can be terminated at this stage if either the first specification  104  or the second specification  108  is satisfactory (e.g., as measured by the corresponding cost values  106 ,  110 ), or alternatively the process may be continued by generating additional specifications and cost values. 
     The following sections present further details related to various embodiments of the present invention as illustrated in  FIG. 1 . 
     Section 1 presents details related to using specifications  104 ,  108  to specify the relative locations and relationships between devices or groups of devices in a circuit. The structures described herein are generally applicable to circuit layouts but are especially advantageous for the types of constraints encountered in analog and RF circuit layouts including matching, symmetry and grouping constraints. Additional constraints may, for example, include constraints for relative locations of devices or groups of devices, alignment of symmetry lines and group boundaries, and defining keep-out regions in a cell relative to certain devices or groups of devices. 
     In some contexts the focus will be on a cell-plan that includes elements of the specification other than same-room device constraints. That is, a cell-plan typically includes a configuration of rooms for placing devices, one or more room constraints for the configuration of rooms, and one or more groups of devices for the rooms. This focus may be desirable when the cell-plan portion of a specification is most likely to be usable for future designs. For the case where the specification does not include same-room constraints, the cell-plan is the specification. 
     In general, the specification or cell-plan can be technology and device parameter independent, in that it does not change when device sizes vary, the design goals change or the process technology changes. 
     Section 2 presents details related to using specifications (and cell-plans) to optimize the circuit performance and layout according to some cost function  106 ,  110 . A designer can create a cell-plan by observing the flow of signals or currents in a circuit. This information may be gathered from the electrical behavior of the circuit, for example, via the electrical simulations, or from prior knowledge of the working of the circuit. A designer may also create the cell-plan by observing the locations of device symbols on the schematic to produce a layout similar to the arrangement on a schematic. A designer may also create a cell-plan by looking at a previous layout implementation of the circuit. The cell-plan can be conveyed in a written or graphic form by a circuit designer to a layout designer, who can then either generate a layout that adheres to a cell-plan constraint or further optimize the circuit layout generated using a cell-plan constraint. 
     Section 3 presents details related to software architectures for implementing the specifications  104 ,  108  and related methods  102  that maintain the constraints in the layout design. In an assisted interactive environment, the software may provide automated techniques to enforce some or all of the constraints (e.g., room constraints and device constraints). This can ensure that in addition to meeting typical requirements for symmetry, matching and grouping, the design result will also meet other requirements for devices and groups of device that may be critical, for example, to minimize lengths of signal and current paths in the circuit. 
     1. Creating Cell-Plans and Specifications 
       FIG. 2  shows an exemplary method  202  for creating a cell-plan for specifying a circuit layout. In a first step  204 , a cell rectangle is introduced. In a second step  206  the cell rectangle is split horizontally (at line a) into a top portion and a bottom portion. In a third step  208  the bottom portion is split vertically (at line b) into a left and right portion. In a fourth step  210  devices (or groups of devices) are inserted into the separated portions, which are called rooms. In  FIG. 2 , the devices include a resistor R 1  and transistors M 1 , M 2 , M 3 , M 4 , M 5 , and M 6 . 
     In general, the cell area is divided into rooms by recursively partitioning it using horizontal and/or vertical partition lines. Devices and/or groups of devices are then inserted as members of rooms.  FIG. 2  shows how an exemplary cell-plan is created by recursively partitioning the cell area into rooms using horizontal and vertical partition lines so that devices can be inserted into the rooms. 
     In this way topological relationships can be specified between devices and groups of devices. These relationships are implied by the partitions used to create these rooms and the insertion of devices and/or groups of devices into these rooms. For example, for the cell-plan described in  FIG. 2 , the group of devices M 1 , M 2 , and M 3  are constrained to be topologically to the left of the group of devices M 4 , M 5 , and M 6 . This topological relationship applies to the geometric bounding box of the groups of devices and not to the individual devices themselves. This relationship is specified by the vertical partition-line b. Similarly, the partition-line a specifies that all devices and/or groups in the sub-partition/rooms below it are topologically to the bottom of all devices and/or groups in the sub-partition/rooms above it. In this example, this implies that the bounding box of all devices M 1 , M 2 , M 3 , M 4 , M 5 , and M 6  must be topologically below the bounding box of device R 1 . 
     Optional relationships can be specified between devices and/or groups within a room. That is, a cell-plan can be augmented by same-room constraints. For example, devices inside a room can be specified to have symmetry, matching and grouping constraints. The room may possess a symmetry line to which, the devices within the room can be constrained to be locally symmetric.  FIG. 3  shows an exemplary cell-plan  302  where devices M 2  and M 3  are constrained to be symmetric with each other with respect to the local symmetry line. Device M 1  is also constrained to be self-symmetric with respect to the local symmetry line. The groups may further be constrained as “free-form” or “grid-form” groups depending on whether coordinates must be specified on a grid. 
     Optional relationships can be specified between various rooms. For example, the symmetry lines belonging to adjacent rooms can be constrained to be aligned with each other as shown in  FIG. 3 . The boundaries of two groups in adjacent rooms may also be specified to be aligned to each other. Certain adjacent rooms may be specified to share certain geometry, for example, well geometry. Multiple adjacent rooms may be enclosed within the same guard-ring. 
     Optional properties can be specified on rooms and the dimensions of the rooms. For example, certain rooms can be marked as keep-out regions with a certain height/width associated with the keep-out region.  FIG. 4  shows an exemplary cell-plan design  402  where a room is marked as a keep-out region. Note that specifying a corner room to be a keep-out region in the original cell  404  results in a final L-shaped cell  406 . Certain rooms may also be specified to be enclosed within an isolation ring, like a guard-ring. 
     Optional relationships can be specified between objects outside a room with respect to the room itself. For example, I/O (input/output) pins that belong to the cell may be constrained to be symmetric with respect to a room&#39;s symmetry line. 
     In some embodiments the cell-plan can be augmented with additional same-room constraints for symmetry, matching and grouping constraints necessary for Analog &amp; RF circuit layouts. 
     For example, when specifying a cell-plan constraint, both devices that are part of a symmetry constraint can be inserted into the same room. When a device is inserted into a room, the user-interface may automatically insert its symmetric partner into the same room or provide the user with an error message when the partner is inserted into a different room. When the devices are inside the same room, their symmetry constraints are interpreted as local symmetry constraints, with respect to the local symmetry line of the room they belong to. This is consistent with desired behavior for grouped devices to be placed symmetrically around a local symmetry line. 
     Relationships between devices that belong to different rooms can be achieved by specifying relationships between the symmetry lines of the different rooms and/or the boundaries of groups within different rooms and then specifying a relationship between the devices inside the rooms to their local symmetry lines. For example, a device A can be placed self-symmetrically (aligned to the local symmetry line) inside Room-A. A device B can be placed self-symmetrically inside Room-B. If the symmetry lines of Room-A and Room-B are aligned to each other, the devices A and B are automatically aligned to each other. Those skilled in the art may extend this specification to allow symmetric partners to exist in neighboring rooms with additional restrictions on the legal topological relationships that work in combination with such a specification. 
     Other constraints can also be incorporated into this framework. All devices that exist in a “Proximity Matching” constraint can be inserted into the same room. This is consistent with the desired behavior of these devices to be placed in close proximity to each other. Devices that are part of other “Orientation Matching” and “Device Matching” constraints may exist in the same or different rooms. “Group” constraints may be automatically generated when devices are inserted into a room. Groups that are explicitly created independently of the cell-plan specification can co-exist with a cell-plan specification since the user can simply insert these groups along with devices into a room in the cell-plan. Such a group of devices can be further constrained into a grid-like arrangement such as a “grid-form” in order to further constrain the relative locations of the individual devices. All devices that are part of a “Compound Device” can be inserted into the same room since this is consistent with the desired characteristic that these devices should be placed together. 
     In some embodiments cell-plan constraints can be created by the user using a graphical interface. Some of these steps are illustrated using the example in  FIG. 2 . For example, the graphical interface starts with a single rectangle  204  representing the cell area. The user can then sub-divide the cell-area into partitions. For this purpose, the user may choose to “Split Horizontally” or “Split Vertically”. When the user chooses to “Split Horizontally” and clicks inside the cell area, the cell area is then divided into two partitions, one above the other, separated by a horizontal partition line. Each of these partitions can further be split either horizontally or vertically to create further sub-partitions, as illustrated in the second step  206  and the third step  208 . 
     Once the desired partitions are created, the user can add devices and/or groups of devices into these rooms. The list of members in each room can be generated by selecting the components on the schematic and/or by typing their names in by hand as illustrated in the fourth step  210 . 
     The user can specify properties on rooms by selecting those rooms and specifying the appropriate property. For example, rooms can be designated as keep-out regions or isolated using guard-rings. Multiple rooms can be specified to be surrounded by a common isolation ring, like a guard-ring. 
     The user can specify relationships between adjacent rooms. For example, one can specify the symmetry lines and/or group boundaries of adjacent rooms to be aligned. One can also automatically create these constraints for adjacent rooms that are created recursively, using the same direction for splitting, consecutively (i.e., one immediately following the other). 
     The cell-plan constraint can then be saved to a text-based constraint representation, which can then be read back for editing purposes. A text-based representation of the Cell-Plan is useful to save this information in a user-editable form. We now describe one way in which the user can represent this information in a textual form. 
     The topological relationship represented by the cell-plan can be expressed in a binary tree format, which enumerates the relative locations between the devices and/or groups. This can then be captured using a string-based representation of the binary tree.  FIG. 5  shows an exemplary recursive keyword-based string format  502  for a cell-plan tree. The keywords “|” and “-” are used to represent the vertical and horizontal cut-lines, respectively. The keyword “children” points to the left/right or bottom/top children of each node in the tree. The left or bottom children are always listed first. The keyword “Collection” represents a list of physical layout device names or group names. This keyword is used for listing devices and groups that are all placed within the same cell room. The keyword “NamedGroup” represents a single group name, which is the only group occupying that particular cell room. This keyword is used only if a cell room is solely occupied by a single group. The structure of this tree and thereby this string-based representation  502 , is very similar to the way the cell-plan is drawn as illustrated in the following examples. 
       FIG. 6  shows the binary-tree representation  602  of a corresponding cell-plan  604 . A corresponding cell-plan string  702  is shown in  FIG. 7 . The first horizontal cut line a on the tree structure  602  is represented by one child (i.e., the left branch of the tree, which in this case represents the “bottom” in the cell-plan  604 ), and a collection with member R 1 , which represents the right branch or “top” of the cut line in the cell-plan  604 . The bottom branch of the tree  602  is then cut vertically at line b) split into one collection, the “Left” group of devices (i.e., M 1 , M 2 , M 3 ), and the second collection, the “Right” group of devices, (i.e., M 4 , M 5 , M 6 ). 
       FIG. 8  shows another example for a binary tree representation  802  of a cell-plan  804 , where each room in the cell-plan  804  contains a group. A corresponding cell-plan string  902  is shown in  FIG. 9 . 
     The use of cell-plans or specifications provides the ability to capture relative locations of devices and/or groups of devices in the presence of symmetry, matching and grouping constraints that are necessary for Analog/RF circuits. In the context of circuit design, this allows devices within groups/rooms to re-orient and re-position themselves to consider alternate placement arrangements, while at the same time maintaining the topological arrangements between groups/rooms. 
     2. Using a Cell-Plan or Specification to Optimize a Circuit Layout 
     This section describes how a cell-plan (or specification) can be used within a design flow to optimize the performance of the circuit and/or the layout. There are several ways in which this can be accomplished. These include various combinations of: (a) how a cell-plan is created before and/or after creating a layout; (b) how a cell-plan is communicated before and/or after creating a layout; and (c) how a cell-plan is followed when creating and/or adjusting a layout. 
     In creating a cell-plan from a circuit schematic, a circuit designer might first identify the critical signal paths and/or DC current paths in the circuit. Reducing the lengths of critical signal paths takes precedence over reducing length of other connections. The designer may obtain this information from prior experience or from measurements based on results from the electrical stimulation of the circuit. 
       FIG. 10  shows a circuit schematic  1002  that represents a video circuit driver. The schematic includes transistor devices M 0 , M 1 , M 2 , M 4 , M 5 , M 8 , M 9 , M 15 , M 17 , M 18 , and M 19 , capacitors C 0 , and C 1 , and I/O pins, Vsig, Vref, and Vout. Critical signal paths  1004  are indicated with dotted circles, and large capacitors  1006  are indicated by dotted squares. 
     In this example, the designer has identified the transistors that are part of the critical signal path  1004 . For example, in  FIG. 10  the signal flows from input I/O pins, Vsig &amp; Vref, through the transistors M 0 , M 1 , M 2 , M 8 , M 19 , M 17 , M 15 , and M 18 , to the output I/O pin Vout. Further, the designer knows that these transistors that make up the critical signal path must be positioned far away from the clocked circuitry in the circuit, namely the mixed-signal transistors and the large capacitors  1006  (i.e., capacitors C 0  and C 1 ). 
     In order to capture this information, a cell-plan  1102  can be created as shown in  FIG. 11 . Note that the cell-plan  1102  has been created such that the transistors that are part of the critical signal path are positioned to the left, far away from the transistors that are part of the mixed-signal circuitry and the large capacitors. The rest of the transistors and capacitors that belong to the regular analog circuitry are positioned in between them. Also note that the designer has specified that the input I/O pins Vsig and Vref are to be positioned symmetrically with respect to the local symmetry line of the room containing the critical signal path. 
     This cell-plan specification  1102  can now be followed when creating a layout  1104 . Note that the topological relationship specified by the cell-plan constraint  1102  has been enforced in this layout  1104 . As a result, the transistors belonging to the critical signal path in the layout  1104  are positioned to the left of the analog circuitry which is further positioned to the left of the mixed-signal circuit and the large capacitors. Further, the I/O pins Vsig and Vref are also positioned symmetrically with respect to the local symmetry line of the critical signal path. 
     As shown in  FIG. 11 , the critical signal path in the layout  1104  includes devices M 0 , M 1 , M 2 , M 8 , M 15 , M 17 , M 18 , and M 19 . The Analog devices include capacitors C 2  and C 3  and devices M 4 , M 5 , M 6 , M 9 , M 10 , M 11 , M 12 , M 13 , M 14 , and M 16 . The mixed-signal devices include M 3 , M 7 , M 20 , M 21 , and M 22 . The large capacitors include C 0  and C 1 . 
     In other cases, a designer may identify the DC current paths through the circuit. These are the connections from the current source (often the positive voltage source, VDD) to the current sinks (often the negative voltage source, VSS or the ground connection, GND). Once these are identified, the transistors connecting these current paths can be positioned in adjacent rooms in the cell-plan, so as to minimize the lengths of these connections. 
     A cell-plan can also be created by observing the position of the device symbols on the schematic. This assumes that the person drawing the schematic already positioned these symbols in the schematic correctly. Such a cell-plan can be used to generate a layout that resembles, in part, the position of the device symbols on the schematic. 
     A cell-plan may also be created from a pre-existing layout. Such a layout may exist from previous implementations of the circuit in a different technology, previous implementations of similar circuits or previous implementation of the same circuit using a different set of device parameters. Once a previous layout exists, the circuit designer and/or the layout designer can draw a cell-plan to closely follow the positions of the devices in the existing layout. Such a cell-plan can then be used to generate a layout that resembles, in part, the existing layout. 
     Once a cell-plan has been created, it can be saved along with the schematic in a graphical form and/or a textual representation. Such information can then be conveyed to a layout designer who can follow that information when creating a layout. Such information may also be reused by the same designer, who created it, at a later time in the design cycle. Capturing the cell-plan in a reusable form also provides the capability to correct parts of it, in case more information is available at a later point in the design cycle, for example, from electrical simulations after extracting the parasitic resistances and capacitors in the layout. 
     Once a cell-plan is available, a layout designer can use the cell-plan to create a layout. The cell-plan can also be used by automatic and/or assisted interactive software that adheres to the cell-plan&#39;s constraints. 
     The layout designer may also choose to follow most of the relationships specified by the cell-plan, but violate parts of it. For example, the boundaries of the rooms need not be straight lines, in case the layout can be packed more tightly. However, following most of the cell-plan specification ensures that the devices are positioned in a fashion as intended by the designer, for example, to minimize the lengths of certain connections in the circuit. 
     The layout designer may choose to further optimize a layout after creating an initial layout using the cell-plan. In cases where major changes are then made, the layout designer may choose to record this information in a new cell-plan by editing the previous cell-plan. Such information is very useful in further re-tuning the layout at a later point in the design cycle in case the technology, the device parameters, the design goals and/or the circuit itself changes. 
     As illustrated by the embodiments discussed above, the present invention enables a designer to formally capture the requirements for physical adjacency, separation and topological relationships that are useful for optimizing the performance of a circuit layout. For example, one can use the cell-plan constraint to minimize the lengths of critical signal paths and/or DC current paths in the circuit. Since this constraint can be captured in a graphical and textual manner, it can be formally communicated from one designer to another. It can also be stored in a way that is substantially independent of related technologies and parameter values, thereby making it easy to reuse when device parameters, design goals, and/or technologies change. 
     3. Software Architecture that Enforces Constraints for a Cell-Plan or Specification 
     According to another embodiment of the present invention, a software architecture can be implemented to enforce a cell-plan constraint (or more generally a specification constraint) in the context of circuit layout design. As discussed below, a slicing-tree can be used to represent the configuration of rooms, which can then be augmented to support one or more device constraints for devices in a same room and also to support one or more room constraints. 
     A slicing-tree characterization has been used conventionally to represent floorplans for block-level digital circuits. As described in conventional slicing-tree references, a slicing-style layout is one that can be derived by recursively “slicing” a rectangle into rooms. The process stops when each component to be placed can be assigned to a single room in the rectangle. (D. F. Wong, C. L. Liu, “A new algorithm for floorplan design,” Proceedings of the 23rd ACM/IEEE Design Automation Conference, p. 101-107, July 1986; L van Ginneken, R Otten, “Optimal slicing of plane point placements,” Proceedings of the European Design Automation Conference, 1990. EDAC, 322-326.) 
       FIG. 12  shows an exemplary slicing-tree representation for a configuration of rooms. In this example, the rectangle represents the layout surface and the component refers to all members of a room. The slicing-tree method  1202  is shown in four steps including a slicing decomposition of a layout surface  1204 , the resulting configuration with six rooms  1206 , an assignment  1208  of six components (i.e., devices or groups of devices) to the rooms, and a slicing tree  1210  for the configuration of six rooms. 
     While the slicing-tree based approach has been previously used for representing floorplans for block-level digital circuits, this approach can be augmented according to the present invention to include constrained optimization for analog and RF circuit designs, as discussed below. 
     The slicing tree configuration for rooms can be augmented to support one or more device constraints between members of devices in the same room using technology disclosed in U.S. patent application Ser. No. 10/674,085, filed Sep. 29, 2003, entitled “Method for Generating Constrained Component Placement for Integrated Circuits and Packages,” and issued Aug. 15, 2006, as U.S. Pat. No. 7,093,220. This application is incorporated herein by reference in its entirety. This technology employs a tree structure, hereafter referred to as constrained-component-tree, to represent devices and groups of devices with one or more device constraints between them. 
     While the constrained-component-tree has been used in the above-cited application to represent and place devices in an overall cell layout, this technology can be adapted according to the present invention to augment the slicing tree configuration of rooms so as to represent and place devices within the same room with one or more same-room constraints. 
       FIG. 13  shows an exemplary augmentation  1302  where a slicing tree  1304  representing a configuration of six rooms is augmented to provide a slicing tree  1306  with constrained-component-trees  1308  to represent member devices within each of the six rooms. 
     Each of the constrained-component-trees  1308  uses a structured search to determine the spatial coordinates of individual devices in the presence of one or more device constraints like symmetry, matching and grouping. This can be used to determine device placement within each of the rooms.  FIG. 14  shows an exemplary placement method  1402  where members of the constrained-component-tree  1404  corresponding to room number one (1) are placed within the room  1406  by determining the spatial coordinates for each of the individual devices M 0 , M 1 , M 2 , M 8 , M 15 , M 17 , M 18  and M 19 . 
     Once the devices within the rooms are placed, the overall cell dimensions are determined by positioning each of the rooms, which includes determining the spatial coordinates for the boundaries the rooms. This is done by using a Depth-First Search (DFS) walk of the slicing tree. For example,  FIG. 15  shows a slicing-tree representation  1502 , including constrained-component-trees  1504 , together with a focus  1506  on the sizing of node “b” given the placement of member devices within rooms “2” and “1.” In the slicing-tree representation  1502 , the DFS walk of the tree would traverse the nodes in the order: “2, 1, b, 3, 6, 5, e, d, 4, c, a”. While doing so, the dimensions of the components (1, 2, 3, 4, 5, 6) are determined by the placement of the devices within each of those rooms. The positions of any other node (a, b, c, d, e) are determined by stacking the node&#39;s children, in a non-overlapping fashion, horizontally in the case of a horizontal cut (or vertically in the case of a vertical cut) next to each other and computing the bounding box. When stacking the children next to each other, the order of the children is determined by the topological relationship specified by the cell-plan. For example, in  FIG. 15 , component “1” is specified by the slicing tree  1502  to be above component “2”, as represented by the horizontal slice “b”. The process is repeated until we compute the position of the node represented by “a” to give the overall positioning of all rooms in the layout. During this process, the first component (“2” in this case) can be positioned with coordinates, x=0, y=0. This can be used to locate the positions of each of the other components. 
     The representation discussed so far, including a slicing tree  1306  for the configuration of rooms and constrained-component-trees  1308  for the members of each of the rooms, can be further augmented to support constraints between rooms, like alignment of symmetry lines between rooms, alignment of group boundaries between rooms and designation of rooms as keep-out regions. 
       FIG. 16  shows an exemplary embodiment  1602  of the present invention for aligning symmetry lines at node b, during the DFS walk described above, when stacking components “1” and “2.”  FIG. 16  also shows an embodiment  1604  of the present invention for aligning group boundary lines at node e, during the DFS walk, when stacking components “5” and “6.” 
       FIG. 17  shows an exemplary representation of a keep-out region according to an embodiment of the present invention. The cell-plan  1702  has a keep-out region at the fourth room so that the cell-plan has an L-shaped configuration. If certain rooms in an initial cell-plan  1702  are designated as keep-out rooms, dimensions of the component in the slicing tree representing that room can be forced to the dimensions needed by such a keep-out region. This forces the result to reserve white-space in the layout at the location of the keep-out region. By specifying such a keep-out region in a corner of a cell, one can generate a desired shape for a cell, for example, an L-shaped cell-plan  1702 . 
       FIG. 18  shows an exemplary method  1802  for optimizing a layout design according to the present invention. The method  1802  employs a software architecture using the representation, described above, to optimize the cell layout, while enforcing the specification  1804 . This specification  1804  includes the configuration of rooms, one or more room constraints for the configuration of rooms, one or more groups of devices in rooms and one or more device constraints for devices in the same room. This is used to determine an initial placement representation  1806  that includes a slicing tree for the configuration of rooms and constrained-component-trees for the members of rooms with one or more same-room constraints. The overall cell layout is determined by placing the devices within each of the rooms using a structured search of the constrained-component-tree and positioning the boundaries of the rooms through a DFS-walk of the slicing tree in  1808 . This step  1808  also includes adjustment of the locations of room components (i.e., devices and/or groups of devices in rooms) to account for room constraints. A cost metric is evaluated  1810  to determine whether the overall quality of the layout is optimal, in which case the process is terminated  1812 . Otherwise, the constrained-component-trees for the devices in the rooms are perturbed  1814  to generate modified constrained-component-trees for the devices in those rooms. Step  1808  is then repeated to generate a modified placement of member devices within rooms and modified positions for each of the rooms, creating a new overall cell layout. The entire process is repeated until we find an optimal cost  1810 . The result is an optimal specification-enforced cell layout  1816 . Note that the devices in the rooms can be perturbed  1814  by a variety of means including swapping device positions within a constrained-component-tree or changing the structure of the constrained-component-tree itself for devices within a room. Additionally, the steps of perturbing devices within rooms  1814 , generating a new overall cell layout  1808 , evaluating a cost metric  1810 , and evaluating the termination criterion  1812  may be executed as a simulated annealing process. Note that while devices within the rooms are perturbed, the slicing tree representing the configuration of rooms remains unchanged, thereby ensuring that the cell-plan constraints are observed. 
     4. Alternative Embodiments of the Invention 
     While the above-described embodiments are directed towards software architectures using slicing trees augmented with constrained-component-trees for members within rooms and adjustments for room constraints, one can extend this approach to other representations for members within rooms that also support same-room device constraints. For example, symmetry, matching and grouping constraints may be formulated using linear equations involving the variable coordinates of devices. Then, for example, the constrained-component-trees in the representation  1806  can be augmented or replaced by linear equations (e.g. Ax=b, Ax≦b) where the placement of devices  1808  can then be determined by solving the system of equations (e.g., solving for x). In the absence of constrained-component-trees, the placement of member devices within rooms can be perturbed  1814  by randomly relocating devices or by swapping locations of devices, and creating a new set of equations for the members within the rooms. Other steps in the above-described method  1802  may remain unchanged. 
     Although only certain exemplary embodiments of this invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. For example, aspects of embodiments disclosed above can be combined in other combinations to form additional embodiments. Accordingly, all such modifications are intended to be included within the scope of this invention.