Patent Publication Number: US-11658202-B2

Title: Dual row select pixel for fast pixel binning

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 63/025,883, filed May 15, 2020, the contents of which are incorporated herein by reference. 
     This application is related to U.S. patent application Ser. No. 17/066,277, titled “Layout Design of Dual Row Select Structure” and concurrently filed Oct. 8, 2020. 
    
    
     BACKGROUND INFORMATION 
     Field of the Disclosure 
     This disclosure relates generally to image sensors, and in particular but not exclusively, relates to complementary metal oxide semiconductor (CMOS) image sensors with pixel binning. 
     Background 
     Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, as well as, medical, automobile, and other applications. As image sensors are integrated into a broader range of electronic devices, it is desirable to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design as well as image acquisition processing. 
     A typical image sensor operates in response to image light from an external scene being incident upon the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge upon absorption of the image light. The image charge photogenerated by the pixels may be measured as analog output image signals on column bitlines that vary as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as analog image signals from the column bitlines and converted to digital values to produce digital images (i.e., image data) representing the external scene. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. 
         FIG.  1    illustrates one example of an imaging system including an array of pixel cells organized in a variety of different color patterns in accordance with the teachings of the present invention. 
         FIG.  2 A  illustrates one example of a 2×4 shared pixel cell with a dual conversion gain configuration included in a pixel array of an imaging system. 
         FIG.  2 B  illustrates a top view of a 16C color filter pattern utilized with 2×4 shared pixel cells included in a pixel array. 
         FIG.  3 A  illustrates an example arrangement of two 2×4 shared pixel cells included in a pixel array with binning provided at one of the column ADCs. 
         FIG.  3 B  illustrates various examples of pixel arrays of shared pixel cells with various binning configurations. 
         FIG.  4 A  shows another example illustrating an arrangement of shared pixel cells included in pixel arrays with binning implemented with in-pixel charge sharing provided with transistors coupling the floating diffusions. 
         FIG.  4 B  illustrates various additional examples of pixel arrays of shared pixel cells with various binning configurations. 
         FIG.  5    shows still another example illustrating an arrangement of shared pixel cells included in a pixel array with binning implemented with a metal line coupling the floating diffusions of the shared pixel cells. 
         FIG.  6    shows an example illustrating an arrangement of shared pixel cells included in a pixel array with binning implemented with a second row select transistor coupling a source follower from one of the pixel cells to a bitline of another pixel cell in accordance with the teachings of the present invention. 
         FIG.  7    shows another example illustrating an arrangement of several rows of shared pixel cells included in a pixel array with binning implemented with second row select transistors coupling source followers from pixel cells to bitlines of other pixel cells to provide binning in accordance with the teachings of the present invention. 
         FIG.  8    shows an example horizontal layout of row select transistors included in shared pixel cells included in a pixel array in accordance with the teachings of the present invention. 
         FIG.  9    shows a top view of an example layout of an arrangement of shared pixel cells including a left 2×4 shared pixel cell and a right shared pixel cell included in a pixel array with binning implemented with dual row select transistors in accordance with the teachings of the present invention. 
         FIG.  10    shows a top view of another example layout of an arrangement of shared pixel cells including a left 2×4 shared pixel cell and a right shared pixel cell included in a pixel array with binning implemented with dual row select transistors in accordance with the teachings of the present invention. 
         FIG.  11    shows yet another example illustrating an arrangement of several rows of shared pixel cells included in a pixel array with binning implemented with second row select transistors coupling source followers from pixel cells to a bitline of other pixel cells to provide binning in accordance with the teachings of the present invention. 
         FIG.  12    shows another example illustrating an arrangement of shared pixel cells included in a pixel array with binning implemented with second row select transistors coupling the shared pixel cells to bitlines of other pixel cells in accordance with the teachings of the present invention. 
         FIG.  13    shows still another example illustrating an arrangement of shared pixel cells included in a pixel array with binning implemented with second row select transistors coupling the shared pixel cells to bitlines of other pixel cells in accordance with the teachings of the present invention. 
     
    
    
     Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. In addition, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention. 
     DETAILED DESCRIPTION 
     Various examples directed to an imaging system with pixel cells including pixel cells with dual row select transistors that provide fast pixel binning are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring certain aspects. 
     Reference throughout this specification to “one example” or “one embodiment” means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases “in one example” or “in one embodiment” in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples. 
     Spatially relative terms, such as “beneath,” “below,” “over,” “under,” “above,” “upper,” “top,” “bottom,” “left,” “right,” “center,” “middle,” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship relative to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is rotated or turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated ninety degrees or at other orientations) and the spatially relative descriptors used herein are interpreted accordingly. In addition, it will also be understood that when an element is referred to as being “between” two other elements, it can be the only element between the two other elements, or one or more intervening elements may also be present. 
     Throughout this specification, several terms of art are used. These terms are to take on their ordinary meaning in the art from which they come, unless specifically defined herein or the context of their use would clearly suggest otherwise. It should be noted that element names and symbols may be used interchangeably through this document (e.g., Si vs. silicon); however, both have identical meaning. 
     As will be discussed, various examples of an imaging system with an array of pixel cells with dual row select pixels for fast pixel binning to support both high resolution image capture as well as high speed high definition (HD) video are disclosed. In various examples, 16C pixel cell arrangements are provided that utilize multiple shared pixel cell units with dual conversion gain, which therefore can provide improved lower noise performance. By limiting the number of photodiodes sharing the same floating diffusion (FD) within a shared pixel cell unit to up to 8 photodiodes, the shared pixel cell&#39;s conversion gain is higher while the FD capacitance kept lower. In various examples, the 16C pixel cell arrangements may be read out in 16C mode, which may be utilized for example for high speed HD video acquisition, or in 1C mode, which may be utilized for example for high resolution still image capture. 
     As will be shown in one example, in 16C mode, a left 2×4 shared pixel cell unit and a right 2×4 shared pixel cell unit of the same color are binned together to output a single image data signal for the same color (e.g., red, green, blue). In various examples, the left and right 2×4 shared pixel cell units are binned inside the pixel array with dual row select transistors for fast pixel binning to achieve a fast 16× frame rate relative to a 1C mode or full size pixel cells in accordance with the teachings of the present invention. 
     As the pixel sizes in image sensors have been decreasing, and as image sensor resolutions have been increasing, arrangements of color filter array patterns have been changing accordingly. For instance, pixel binning has become one approach to increase image sensor sensitivity by adding or combining image charges from multiple pixels as pixel sizes have decreased. With pixel binning, color filter array patterns can be grouped accordingly to accommodate for example 1C, 4C (e.g., 2×2), 9C (e.g., 3×3), 16C (e.g., 4×4), etc., configurations. With a 16C pixel cell arrangement in accordance with the teachings of the present invention, an image sensor can have the flexibility to provide different modes to support both high resolution still image capture, as well as high speed high definition (HD) video acquisition. 
     For small sub-micron pixels, a shared pixel structure may be utilized to account for limited pixel area. In some examples, multiple 2×2 or 2×4 unit shared pixel cell arrangements may be used in combination to form a 16C (e.g., 4×4) color filter pattern. Furthermore, the pixel cells can be single conversion gain (CG) pixel cells for normal dynamic range or the pixel cells can be dual conversion gain (DCG) pixel cells to provide high dynamic range acquisition. DCG pixel cells can be configured to provide both high conversion gain (HCG) for dim lighting conditions and low conversion gain (LCG) for bright lighting conditions. It is appreciated that one of the tradeoffs when choosing between high conversion gain for dim lighting conditions and low conversion gain for bright lighting conditions is that pixel cells that are configured for high conversion gain generally have less readout noise compared to pixel cells that are configured for low conversion gain. Thus, when given the option, one reason not to choose a 4×4 (e.g., 16C) shared pixel cell configuration over a smaller 2×2 (e.g., 4C) shared pixel cell configuration or a full size (e.g., 1C) mode configuration is to take advantage of the lower noise performance of the 1C or 4C configurations. 
     To illustrate,  FIG.  1    illustrates generally one example of a complementary metal oxide semiconductor (CMOS) imaging system  100  including a color pixel array  102  with an array of pixel cells with dual row select pixels for fast pixel binning in accordance with an embodiment of the present disclosure. As shown in the depicted example, the imaging system  100  includes an image sensor with pixel array  102 , a control circuit  110 , a readout circuit  106 , and function logic  108 . In one example, pixel array  102  is a two-dimensional (2D) array of pixel cells. 
     For explanation purposes, the example depicted in  FIG.  1    illustrates generally that an array of pixel cells may be organized in one of a variety of different color patterns. For instance, the array of color pixel cells  104 A illustrates an example of a 1C Bayer (RGB) color filter pattern, which may be utilized for high resolution still image capture. Similarly, the array of color pixel cells  104 B illustrates an example of a 4C (2×2) Bayer color filter pattern of red (R), green (G), and blue (B) color filters as shown. The array of color pixel cells  104 C illustrates an example of a 9C (3×3) Bayer (RGB) color filter pattern. The array of color pixel cells  104 D illustrates an example of a 16C (4×4) Bayer (RGB) color filter pattern, which may be utilized for example for high speed HD video capture. As will be described in greater detail, it is noted that with a 16C shared pixel cell  104 D, imaging system  100  can provide different modes to support both high resolution still image capture, as well as high speed HD (high definition) video in accordance with the teachings of the present invention. 
     In shown in the depicted example, the pixel cells included pixel array  102  are arranged into rows and columns to acquire image data of a person, place, object, etc., which can then be used to render an image of a person, place, object, etc. After the photodiodes in the pixel cells of pixel array  102  have acquired their image charge, the corresponding analog image signals are read out by readout circuit  106  through column bitlines  112 . In the various examples, readout circuit  106  includes an analog-to-digital conversion (ADC) circuits, which are coupled to convert the analog image signals received from the pixel cells  104  through bitlines  112  into digital image signals, which may be then transferred to function logic  108 . Function logic  108  may simply store the image data or even manipulate the image data by applying post image processing or effects. Such image processing may, for example, include image processing, image filtering, image extraction and manipulation, determination of light intensity, crop, rotate, remove red eye, adjust brightness, adjust contrast, etc. 
     In one example, a control circuit  110  is coupled to pixel array  102  to control operational characteristics of pixel array  102 . For instance, in one example, control circuit  110  generates the transfer gate signals and other control signals to control the transfer and readout of image data from the photodiodes included in the pixel cells of pixel array  102 . In addition, control circuit  110  may generate a shutter signal for controlling image acquisition. In one example, the shutter signal may be a rolling shutter signal such that each row of the pixel array  102  is read out sequentially row by row during consecutive acquisition windows. In another example, the shutter signal may also establish an exposure time, which is the length of time that the shutter remains open. In one embodiment, the exposure time is set to be the same for each of the frames. 
       FIG.  2 A  illustrates one example of a 2×4 shared pixel cell  204  with a dual conversion gain configuration included in a pixel array of an imaging system. It is appreciated that the pixel cell  204  of  FIG.  2 A  may be an example implementation of pixel cells that are included in the pixel array  102  of the image sensor  100  as shown in  FIG.  1   , including for example color pixel cells  104 D, and that similarly named and numbered elements described above are coupled and function similarly below. 
     In the example depicted in  FIG.  2 A , pixel cell  204  includes a photodiode P 1  coupled to a transfer transistor  214 - 1 , a photodiode P 2  coupled to a transfer transistor  214 - 2 , a photodiode P 3  coupled to a transfer transistor  214 - 3 , a photodiode P 4  coupled to a transfer transistor  214 - 4 , a photodiode P 5  coupled to a transfer transistor  214 - 5 , a photodiode P 6  coupled to a transfer transistor  214 - 6 , a photodiode P 7  coupled to a transfer transistor  214 - 7 , and a photodiode P 8  coupled to a transfer transistor  214 - 8 . A floating diffusion FD  216  is coupled to transfer transistor  214 - 1 , transfer transistor  214 - 2 , transfer transistor  214 - 3 , transfer transistor  214 - 4 , transfer transistor  214 - 5 , transfer transistor  214 - 6 , transfer transistor  214 - 7 , and transfer transistor  214 - 8 . 
     Transfer transistor  214 - 1  is coupled to be controlled in response to a transfer control signal TX 1 , transfer transistor  214 - 2  is coupled to be controlled in response to a transfer control signal TX 2 , transfer transistor  214 - 3  is coupled to be controlled in response to a transfer control signal TX 3 , transfer transistor  214 - 4  is coupled to be controlled in response to a transfer control signal TX 4 , transfer transistor  214 - 5  is coupled to be controlled in response to a transfer control signal TX 5 , transfer transistor  214 - 6  is coupled to be controlled in response to a transfer control signal TX 6 , transfer transistor  214 - 7  is coupled to be controlled in response to a transfer control signal TX 7 , and transfer transistor  214 - 8  is coupled to be controlled in response to a transfer control signal TX 8 . As such, charge photogenerated in photodiode P 1  in response to incident light is transferred to floating diffusion FD  216  in response to transfer control signal TX 1 , charge photogenerated in photodiode P 2  in response to incident light is transferred to floating diffusion FD  216  in response to transfer control signal TX 2 , charge photogenerated in photodiode P 3  in response to incident light is transferred to floating diffusion FD  216  in response to transfer control signal TX 3 , charge photogenerated in photodiode P 4  in response to incident light is transferred to floating diffusion FD  216  in response to transfer control signal TX 4 , charge photogenerated in photodiode P 5  in response to incident light is transferred to floating diffusion FD  216  in response to transfer control signal TX 5 , charge photogenerated in photodiode P 6  in response to incident light is transferred to floating diffusion FD  216  in response to transfer control signal TX 6 , charge photogenerated in photodiode P 7  in response to incident light is transferred to floating diffusion FD  216  in response to transfer control signal TX 7 , and charge photogenerated in photodiode P 8  in response to incident light is transferred to floating diffusion FD  216  in response to transfer control signal TX 8 . 
     As illustrated in the depicted example, a reset transistor  224  and a dual conversion gain transistor  222  are coupled between a voltage supply (e.g., AVDD) and the floating diffusion FD  216 . In the example, a second floating diffusion FD 2   226  is coupled to the node between reset transistor  224  and dual conversion gain transistor  222 . A gate of a source follower transistor SF  218  is coupled to the floating diffusion FD  216 . The drain of the source follower transistor SF  218  is coupled to a voltage supply (e.g., AVDD). A row select transistor  220  is coupled to a source of the source follower transistor SF  218 . In operation, the row select transistor  220  is coupled to output a data signal (e.g., image data) from the source follower transistor SF  218  of pixel cell  204  to a bitline  212  in response to a row select signal RS. 
     In one example, pixel cell  204  is configured for high conversion gain (HCG) when the dual conversion gain transistor  222  is deactivated or off, such that the floating diffusion FD  216  stores the image charge photogenerated in the photodiode(s) in response to incident light. In the example, pixel cell  204  is configured for low conversion gain (LCG) when the dual conversion gain transistor  222  is activated or on, such that both the floating diffusion FD  216  and the second floating diffusion FD  226  store the image charge photogenerated in the photodiode(s) in response to incident light. 
     In various examples, the photodiodes of the pixel array are binned, including photodiodes P 1 , P 2 , P 3 , P 4 , P 5 , P 6 , P 7 , P 8 . In other words, the image charge information generated from each photodiode is summed with image charge information generated from one or more other photodiodes to generate combined information, and therefore sum the performance of each individual photodiode to improve the performance of the pixel array. For instance, in various examples, 2×2 or 2×4 groupings of photodiodes may be configured to be binned such that the plurality of photodiodes included in each binned grouping all share the same color. As such, in a 2×4 shared pixel example, the 8 photodiodes are arranged in the pixel array such that each 2×4 grouping of image sensing photodiodes is either red, green, or blue. In one example, the 2×4 groupings of binned photodiodes may all be adjacent or neighboring photodiodes in the pixel array and share the same color filter. In a 2×2 example, the 2×2 groupings of the 4 binned photodiodes may all share the same color. 
       FIG.  2 B  shows a top view of an example 16C color filter pattern utilized with arrangements of two 2×4 shared pixel cells side-by-side included in a pixel array. It is appreciated that the 16C color filter example illustrated in  FIG.  2 B  may be utilized with a plurality of 2×4 shared pixel cells  204  as illustrated in  FIG.  2 A . As shown in the example depicted in  FIG.  2 B , the 16C color filter pattern is a 16C Bayer color filter pattern with 16C groupings of red (R), green (G), and blue (B) color filters. In the depicted example, each 16C grouping may include a left 2×4 shared pixel cell and a right 2×4 shared pixel cell that are similar to the pixel cell  204  illustrated in  FIG.  2 A . As such, the blue (B) 16C grouping includes a left 2×4 grouping  204 BL and a right 2×4 grouping  204 BR. The green (G) 16C grouping in the same row as the blue (B) 16C grouping includes a left 2×4 grouping  204 GBL and a right 2×4 grouping  204 GBR. The red (R) 16C grouping includes a left 2×4 grouping  204 RL and a right 2×4 grouping  204 RR. The green (G) 16C grouping in the same row as the red (R) 16C grouping includes a left 2×4 grouping  204 GRL and a right 2×4 grouping  204 GRR. As shown, each 2×4 grouping includes 8 color filters numbered 1-8, which correspond to underlying photodiodes P 1 -P 8 . In 16C mode, the left 2×4 shared pixel cell and the right 2×4 shared pixel cell of the same color (e.g., red, green, blue) are binned together to output a single image data signal for the same color. 
       FIG.  3 A  shows an example of a 16C arrangement of shared pixel cells included in a pixel array with horizontal analog binning implemented inside a column analog to digital converter (ADC) through capacitor charge sharing. As shown in the depicted example, the 16C arrangement includes a left 2×4 shared pixel cell  304 L and a right 2×4 shared pixel cell  304 R that are each coupled to a respective bitline BL 0   312 L and BL 1   312 R. It is appreciated that the pixel cells  304 L and  304 R may be examples of pixel cell  204 , which is described in detail above in connection with  FIG.  2 A , and that similarly named and numbered elements described above are coupled and function similarly below. Further, it is appreciated therefore that the coupling and operation of shared pixel cells  304 L and  304 R are not be described again in detail for the sake of brevity. 
     In full size (1C) or 4C readout mode, the image data signal from the left and right 2×4 shared pixel cells  304 L and  304 R are read out at the same time or simultaneously through respective bitlines BL 0   312 L, BL 1   312 R, which are coupled to two column ADC circuits  306 L,  306 R, respectively. In the various examples, the column ADC circuits may be included in a readout circuit (e.g., readout circuit  106 ) to convert the image signals in the respective bitlines BL 0   312 L, BL 1   312 R to digital image signals. However, in a 16C readout mode, column ADC  306 L is coupled to both bitline BL 0   312 L and bitline BL 1   312 R to implement horizontal analog binning inside column ADC  306 L through capacitor charge sharing. As a result, column ADC  306 R is inactive during this 16C readout mode, as shown with inactive column ADC  306 R illustrated with dashed lines  FIG.  3 A . 
     In a 16C readout mode, each 2×4 shared pixel cell  304 L and  304 R has the charge binned image data signal from its 8 photodiodes P 1 -P 8  at its floating diffusion (FD), and this signal is read out through its bitline BL 0   312 L and BL 1   312 R. The two signals from left shared pixel cell  304 L and right shared pixel cell  304 R on bitlines BL 0   312 L and BL 1   312 R are then averaged through charge sharing in the column ADC  306 L. For every ADC in this example, two bitlines are needed for analog binning in 16C mode as shown in  FIG.  3 A . The other ADC (e.g., ADC  306 R to the right in  FIG.  3 A ) that is active in full size (1C) or 4C mode is now inactive in 16C mode. As a consequence, the image sensor&#39;s output data rate in 16C mode is only half of output data rate of the full size (1C) or 4C mode. To fully utilize all ADCs, and keep the frame rate of 16C mode 16 times of full size, the number of bitlines should be doubled. Similarly, in a 16C mode configuration that utilizes 2×2 shared pixel cells (e.g., four 2×2 shared pixel cells for 16C) for binning, in order to fully utilize the ADCs and keep frame rate 64 times of full size, the number of active bitlines should therefore be 4 times that of full size (1C), or one bitline for each of the four shared 2×2 shared pixel cells. 
     In an example of a 200 megapixel sensor having an image resolution of 16384×12288, for a whole row (e.g., 16384 pixels) of column ADCs, 16384 bitlines are needed. To support 16C mode and 16C 2×2 binning mode with same data rate as full size (1C), 65536 bitlines in total are needed, or 4 bitlines per pixel pitch. For small pixels (such as for example 0.61 um), this requires extra metal layer(s), which increase the cost. The reduced metal spacing between bitlines and their neighboring metal traces also increase the bitline capacitance, which slows down the sensor readout performance. 
     In another example of a 3 megapixel sensor configured in 1080p mode or 720p mode with ⅛ down sampling, it is noted that only 4 multiples of rows can be readout together with 4 bitlines per 2×4 shared pixel cell. In addition, only 2 multiples of rows can be readout together with 2 bitlines per 2×4 shared pixel cell.  FIG.  3 B  further illustrates an example of pixel arrays  302 A,  302 B,  302 C with 16C mode and 2×2 shared pixel cell configurations. As shown with pixel array  302 A with binning performed at the source followers and 2×2 shared pixel cells, the equivalent source follower size is 8×, the metal capacitance Cm is 4×, and the metal resistance Rm is ¼. Pixel array  302 B with some source follower binning and some analog binning and 2×2 shared pixel cells, the equivalent source follower size is 4×, the metal capacitance Cm is 2×, and the metal resistance Rm is ½. Similarly, pixel array  302 C with analog binning and 2×2 shared pixel cells, the equivalent source follower size is 2×, the metal capacitance Cm is 1×, and the metal resistance Rm is 1×. Therefore, it is appreciated that there is no meaningful difference in speed because the RC time constants regarding pixel arrays  302 A,  302 B,  302 C are substantially equal (i.e., (4)·(¼)=(2)·(½)=(1)·(1)). 
       FIG.  4 A  shows another example illustrating a 16C arrangement of shared pixel cells including a left 2×4 shared pixel cell  404 L and a right 2×4 shared pixel cell  404 R included in a pixel array with binning implemented with in-pixel charge sharing provided with transistors coupling together the floating diffusions of the shared pixel cells  404 L and  404 R. It is appreciated that the pixel cells  404 L and  404 R may also be examples of pixel cell  204 , which is described in detail above in connection with  FIG.  2 A , and that similarly named and numbered elements described above are coupled and function similarly below. Further, it is appreciated therefore that the coupling and operation of shared pixel cells  404 L and  404 R are not be described again in detail for the sake of brevity. 
     As shown in the depicted example, pixel cells  404 L and  404 R are dual conversion gain (DCG) configurations as they both include DCG transistors. Thus, for a DCG pixel, there are two floating diffusions, FD for HCG and FD+FD 2  for LCG. The charge binning is through an extra transistor  428  that is coupled between the FD of the two pixel cells  404 L and  404 R, or an extra transistor  430  that is coupled between the second floating diffusion FD 2  of the two pixel cells  404 L and  404 R. With FD charge binning, the binned signal can be readout through a single bitline. For every column ADC, one bitline is needed. In the example depicted in  FIG.  4 A , the left 2×4 shared pixel cell  404 L and the right 2×4 shared pixel cell  404 R should each have separate row select controls, as depicted with row select signal RS 0  for the left pixel cell  404 L and row select signal RS 1  for the right pixel cell  404 R, so that each bitline can separately be used to simultaneously to read another row to achieve the frame rate in 16C mode. 
     As shown, extra transistor(s)  428 ,  430  and the extra row control wires that provide row select signal RS 0  and RS 1  are needed, which may be difficult to realize in small pixels. Furthermore, the coupling between the two shared pixels  404 L and  404 R at the two floating diffusions results in lower conversion gain when connected in 16C mode, which will harm the readout noise performance. 
     In yet another example of a 3 megapixel sensor configured in 1080p mode or 720p mode with ⅛ down sampling, it is noted that 8 multiples of rows can be readout together with 4 bitlines per 2×4 shared pixel cell. In addition, 4 multiples of rows can be readout together with 2 bitlines per 2×4 shared pixel cell.  FIG.  4 B  further illustrates another example of pixel arrays  402 A,  402 B with 16C mode connected floating diffusion provided binning configurations. As shown with pixel array  402 A with 16C mode binning performed with connected floating diffusions and 2×2 shared pixel cell source followers, the equivalent source follower size is 4×, the metal capacitance Cm is 2×, and the metal resistance Rm is ½. Pixel array  402 B with 16C mode binning performed with connected floating diffusions and 2×2 shared pixel cell analog binning provided with capacitor charge sharing at the ADC  406 B, the equivalent source follower size is 2×, the metal capacitance Cm is 1×, and the metal resistance Rm is 1×. Therefore, it is appreciated that there is no meaningful difference in speed because the RC time constants regarding pixel arrays  402 A,  402 B are substantially equal (i.e., (2)·(½)=(1)·(1)). 
       FIG.  5    shows yet another example illustrating a 16C arrangement of shared pixel cells including a left 2×4 shared pixel cell  504 L and a right 2×4 shared pixel cell  504 R included in a pixel array with binning implemented with in-pixel charge sharing provided with a metal connection that couples together the floating diffusions of pixel cells  504 L,  504 R to each other. It is appreciated that the pixel cells  504 L and  504 R may also be examples of pixel cell  204 , which is described in detail above in connection with  FIG.  2 A , and that similarly named and numbered elements described above are coupled and function similarly below. Further, it is appreciated therefore that the coupling and operation of shared pixel cells  504 L and  504 R are not be described again in detail for the sake of brevity. 
     As shown,  FIG.  5    illustrates the second floating diffusion FD 2  binning is provided by removing the transistors  428  and  430  shown in  FIG.  4 A . Instead,  FIG.  5    shows that the floating diffusions FD 2  of pixel cells  504 L and  504 R are directly electrically coupled together with a metal line or metal connection  532 . Although the extra binning transistor is removed compared to the example depicted in  FIG.  4 A , the example shown in  FIG.  5    illustrates that binning is provided for dual conversion gain pixels and that the lower conversion gain is lower than single 2×4 dual conversion gain pixel&#39;s LCG readout due to the shared two floating diffusions FD 2  through the metal connection  532 . 
     As shown in the example depicted in  FIG.  5   , the bitline BL 0   512 L of the left pixel cell  504 L is used to readout row n in response to row select signal RS 0 , and the bitline BL 1   512 R of the right pixel cell  504 R is used to simultaneously readout another different row n+2 m . Readout speed can be therefore doubled compared to analog binning. However, in addition to the extra row select control wire (e.g., row select signal RS 1  in addition to row select signal RS 0 ), there is also a coupling capacitance between floating diffusion FD and the respective bitline in the configuration illustrated in  FIG.  5   . As a consequence, the voltage on bitline BL 1   512 R may be capacitively coupled (through the capacitance of the row select transistor coupled to receive row select signal RS 1 ) to the FD, and result in unwanted crosstalk, which affects the voltage on bitline BL 0   512 L through metal connection  532 . Thus, performance will be deteriorated. 
     Therefore, in order to reduce crosstalk and improve performance,  FIG.  6    is an illustration of another configuration illustrating a 16C arrangement of shared pixel cells including a left 2×4 shared pixel cell  604 L and a right 2×4 shared pixel cell  604 R included in a pixel array with binning implemented with dual row select transistors in accordance with the teachings of the present invention. It is noted that the example depicted in  FIG.  6    describes 2×4 arrangements of photodiodes for explanation purposes, but that in other examples, different arrangements of photodiodes, such as a 2×2 arrangements of photodiodes, etc., may be included in the shared pixel cells in accordance with the teachings of the present invention. It is also appreciated that the pixel cells  604 L and  604 R illustrated in the example of  FIG.  6    share some similarities with pixel cell  204 , which is described in detail above in connection with  FIG.  2 A , and that the similarly named and numbered elements described above are coupled and function similarly below. Further, it is appreciated therefore that the coupling and operation of shared pixel cells  604 L and  604 R are not be described again in complete detail for the sake of brevity. 
     In the example depicted in  FIG.  6   , the crosstalk between bitline BL 0   612 L of the left shared pixel cell  604 L and bitline BL 1   612 R of the right shared pixel cell  604 R is significantly reduced or eliminated when compared to the example depicted in  FIG.  5   . In particular, the example shows that metal connection  632  that directly couples together the floating diffusions of shared pixel cells  604 L,  604 R is no longer required and is instead optional, as indicated with a dashed line in  FIG.  6   . When metal connection  632  is removed, the crosstalk discussed above is significantly reduced or eliminated, and performance is improved compared to the example described in  FIG.  5   . Instead, binning is provided in the example depicted in  FIG.  6    with the inclusion a second row select transistor  634 R in addition to the first row select transistor  620 R in the pixel cell  604 R. Without the metal connection  632 , both the HCG and the LCG mode readouts are binned through the two source followers  618 L,  618 R. As shown in the depicted example, a second row select transistor  634 R is coupled between source follower SF  618 R of pixel cell  604 R and the bitline BL 0   612 L of pixel cell  604 L. As such, the drain regions of first row select transistor  620 L and second row select transistor  634 R are both coupled to the source region of source follower SF  618 R. As will be discussed in greater detail below, in one example, the source region of the source follower SF  618 R is a split source junction region that is split into the drains regions of first row select transistor  620 R and second row select transistor  634 R. Stated in another way, the drain regions of the first row select transistor  620 R and second row select transistor  634 R are shared a common junction in the semiconductor material with the split source junction region of the source follower SF  618 R. In another example, the drains of first row select transistor  620 R and second row select transistor  634 R may be coupled together with a metal connection. 
     In another example in which optional metal connection  632  is included, which couples together the two second floating diffusions FD 2 , true binning of the second floating diffusions FD 2  of the 16 photodiodes is provided for an LCG mode readout when the dual conversion gain transistors  622 L,  622 R are turned on. In the LCG mode, which is when the dual conversion gain transistors  622 L,  622 R are turned on, the effective source follower size doubles and bitline settles faster when compared to a single source follower transistor. 
     When the dual conversion gain transistors  622 L,  622 R are turned off, an HCG mode readout can be achieved with binning with the second row select transistor  620 R turned on, which enables binning through the two source follower transistors  618 L,  618 R to provide a binning signal of the 8 respective photodiodes from both 2×4 shared pixel cells  604 L,  604 R in accordance with the teachings of the present invention. 
     When metal connection  632  is not included and when reading out row n through bitline BL 0   612 L, bitline BL 1   612 R of pixel cell  604 R and the floating diffusion FD  616 L of pixel cell  604 L are isolated from one another as the row select transistor  620 R is turned off in response to row select signal RS 1 , which eliminates the crosstalk issue suffered by the example shown in  FIG.  5   . When the second row select transistor  634 R turned on in response to the row select signal RS 2  to provide binning, the metal line  632  is not needed to provide binning. In other words, the left pixel cell  604 L and the right pixel cell  604 R are binned through their source follower transistors  618 L,  618 R and through the second row select transistor  634 R when turned on in response to the row select signal RS 2 . In addition, it is further appreciated that by not including metal connection  632 , the gain of the LCG readout mode is not further reduced by the direct coupling together of the two floating diffusions, which therefore provides improved readout performance. It is noted that in another example, the inclusion of a second row select transistor  634 R as discussed can also be implemented in a single conversion gain pixel cell implementation, without dual conversion gain transistors  622 L and  622 R, to provide binning in accordance with the teachings of the present invention. 
       FIG.  7    is an illustration of yet another configuration illustrating a 16C arrangement of several rows of shared pixel cells including left 2×4 shared pixel cells  704 AL,  704 BL and right 2×4 shared pixel cells  704 AR,  704 BR included in a pixel array with binning implemented with dual row select transistors in accordance with the teachings of the present invention. It is noted that the example depicted in  FIG.  7    describes 2×4 arrangements of photodiodes for explanation purposes, but that in other examples, different arrangements of photodiodes, such as a 2×2 arrangements of photodiodes, etc., may be included in the shared pixel cells in accordance with the teachings of the present invention. It is also appreciated that the pixel cells  704 AL,  704 AR,  704 BL,  704 BR share some similarities with pixel cell  204 , which is described in detail above in connection with  FIG.  2 A , and that the similarly named and numbered elements described above are coupled and function similarly below. Further, it is appreciated therefore that the coupling and operation of shared pixel cells  704 AL,  704 AR,  704 BL,  704 BR are not be described again in complete detail for the sake of brevity. 
     It is also appreciated that the arrangement illustrated in  FIG.  7    also shares some similarities with the example illustrated in  FIG.  6   . However, in order to keep left shared pixel cells  704 AL,  704 BL and right shared pixel cells  704 AR,  704 BR layouts symmetric compared to the shared pixel cells illustrated in  FIG.  6   , each of the shared pixel cells  704 AL,  704 AR,  704 BL,  704 BR illustrated in  FIG.  7    includes a respective first row select transistor  720 AL,  720 AR,  720 BL,  720 BR and a respective second row select transistor  734 AL,  734 AR,  734 BL,  734 BR. As shown in the example, the drain regions of both of the first and second row select transistors  720 AL/ 734 AL,  720 AR/ 734 AR,  720 BL/ 734 BL,  720 BR/ 734 BR for each respective 2×4 shared pixel cells  704 AL,  704 AR,  704 BL,  704 BR are coupled to the respective source regions of respective source follower transistors  718 AL,  718 AR,  718 BL,  718 BR of the respective pixel cell. As will be described in greater detail below, in one example, the first and second row select transistors  720 AL/ 734 AL,  720 AR/ 734 AR,  720 BL/ 734 BL,  720 BR/ 734 BR share a drain region that is coupled to the respective split source junction regions of respective source follower transistors  718 AL,  718 AR,  718 BL,  718 BR of the respective pixel cell. In another example, the drain regions of the first and second row select transistors  720 AL/ 734 AL,  720 AR/ 734 AR,  720 BL/ 734 BL,  720 BR/ 734 BR may be coupled together with metal lines. 
     As shown in the depicted example, there are two variations of the 2×4 shared pixel cells  704 AL,  704 AR,  704 BL,  704 BR. In particular, shared pixel cells  704 AL and  704 AR are included in an A-cell layout and pixel cells  704 BL and  704 BR are included in a B-cell layout in the example depicted in  FIG.  7   . In the A-cell, the binning row select transistors  734 AL,  734 AR are coupled to the left bitline BL 0   712 L in response to row select signal RS 1 . In the B-cell, the binning row select transistors  734 BL,  734 BR are coupled to the right bitline BL 1   712 R in response to row select signal RS 1 . In various examples, the pixel cells alternate between A-cells and B-cells for each consecutive row in a column. In other words, the pixel cells are organized in a repeating pattern of A-cell, B-cell, A-cell, B-cell, . . . , etc., for each column. 
     Stated in another way, in various examples, each column of pixel cells may be organized into two subgroups of pixel cells. In one example, the first subgroup includes every other row of pixel cells, and the second subgroup includes the remaining every other row of pixel cells that are not included in the first subgroup. Thus, the A-cells may be included in the first subgroup of pixel cells, and the B-cells may be included in the remaining second subgroup of pixel cells. 
     The example illustrated in  FIG.  7    shows that each of the shared pixel cells  704 AL,  704 AR,  704 BL,  704 BR includes two row select transistors  720 AL/ 734 AL,  720 AR/ 734 AR,  720 BL/ 734 BL,  720 BR/ 734 AR, which are coupled to be controlled with separate row select signals of RS 0  and RS 1 . When read out in full-sized (1C) or 4C mode, the first row select signal RS 0  is activated for both left  704 AL,  704 BL and right  704 AR,  704 BR shared pixels, and their respective image signals at the floating diffusions FD are readout separately through two bitlines BL 0   712 L, BL 1   712 R at the same time or simultaneously. 
     When read out in 16C mode with 2×4 shared pixel cells, or in another example in 16C mode with 2×2 shared pixel cells (e.g., four 2×2 shared pixel cells in a 16C arrangement) binning mode, the second row select signal RS 1  is activated for both left  704 AL,  704 BL and right  704 AR,  704 BR shared pixels so that the second row select transistors  734 AL/ 734 AR for the A-cell and  734 BL/ 734 BR for the B-cell connect to the same respective bitline  712 L/ 712 R. To illustrate, in the top row in  FIG.  7   , which shows the A-cell, the row select signal RS 1  couples the pixel cells  704 AL,  704 AR to the left bitline BL 0   712 L. For another row, such as in the bottom row in  FIG.  7   , which shows the B-cell, the row select signal RS 1  couples the pixel cells  704 BL,  704 BR to the right bitline BL 1   712 R, such that the loading on both bitlines BL 0   712 L, BL 1   712 R is the same. Therefore, two 16C binned signals are read out simultaneously through the two separate bitlines BL 0   712 L, BL 1   712 R and the two column ADCs  706 L,  706 R so the data rate in 16C mode is 16 times that of a full size (1C) readout, without increasing the number of the bitlines in accordance with the teachings of the present invention. 
     In another example when reading out in 16C binning mode with 2×2 shared pixel cells (e.g., four 2×2 shared pixel cells per 16C arrangement), the number of bitlines can be doubled from 2 to 4 to fully utilize all of the column ADCs. Thus, in a 200 megapixel example, only 32768 bitlines are needed, or 2 bitlines per the pitch of the pixel cell (e.g., 0.61 um), which doesn&#39;t require extra metal layers. 
     As mentioned above, in one example, the first and second row select transistors of each shared pixel cell  704 AL,  704 AR,  704 BL,  704 BR share a drain region in a common junction. In other words, in the example, first and second row select transistors  720 AL and  734 AL, first and second row select transistors  720 AR and  734 AR, first and second row select transistors  720 BL and  734 BL, and first and second row select transistors  720 BR and  734 BR share drain regions in common junctions. To illustrate,  FIG.  8    is a diagram that shows an example of a horizontal row select transistor arrangement that the shared drain regions of the first and second row select transistors of each shared pixel cell  704 AL,  704 AR,  704 BL,  704 BR included in a pixel array in accordance with the teachings of the present invention. Thus, it is appreciated that the row select transistors illustrated in  FIG.  8    may be examples of the row select transistors illustrated in  FIG.  7   , and that the similarly named and numbered elements described above are coupled and function similarly below. 
     As shown in the example depicted in  FIG.  8   , the A-cell layout includes a first row select transistor  820 AL disposed proximate to a second row select transistor  834 AL. The A-cell also includes a first row select transistor  820 AR disposed proximate to a second row select transistor  834 AR. As discussed above, the drain regions of first row select transistors  820 AL/ 820 AR and second row select transistors  834 AL/ 834 AR are coupled to respective source regions of respective source follower transistors of the pixel cell. In the example, if it is assumed that the column bitlines (e.g., BL 0   812 L, BL 1   812 R) are aligned along a vertical axis, it is noted that first and second row select transistors  820 AL and  834 AL and that first and second row select transistors  820 AR and  834 AR are horizontally arranged relative to the column bitlines (e.g., perpendicular to the column bitlines), such that the respective drain regions of the row select transistors are adjacent to or overlapping with one another in the semiconductor material. In one example, these adjacent drain regions are shared regions included in a common junction and are therefore directly coupled together by sharing the drain with the silicon junction in common with split source junction regions of the respective source followers of the pixel cell. By sharing the common drain in the semiconductor (e.g., silicon) junction, no metal interconnection and no isolation structure are required. In another example, these adjacent drain regions may be coupled together via a short metal line. In either example, it is appreciated that this horizontal arrangement minimizes capacitance. As shown in the example A-cell, the source region of first row select transistor  820 AR is coupled to bitline BL 1   812 R, while the source regions of first row select transistor  820 AL, second row select transistor  834 AL, and second row select transistor  834 AR are coupled to bitline BL 0   812 L. 
     Similarly, the B-cell layout includes a first row select transistor  820 BL disposed proximate to a second row select transistor  834 BL. As mentioned, in various examples, the pixel cells alternate in a repeating pattern between A-cell and B-cell layouts for each consecutive row in a column as shown. The B-cell also includes a first row select transistor  820 BR disposed proximate to a second row select transistor  834 BR. In the example, it is noted that first and second row select transistors  820 BL and  834 BL and that first and second row select transistors  820 BR and  834 BR are horizontally arranged such that their respective drain regions are adjacent to or overlapping with one another in the semiconductor material. Similar to the A-cell, these adjacent drain regions in the B-cell are also shared regions included in a common junction and are therefore directly coupled together by sharing the drain with the silicon junction in common with split source junction regions of the respective source followers of the pixel cell. By sharing the common drain in the semiconductor (e.g., silicon) junction, no metal interconnection and no isolation structure are required. In another example, these adjacent drain regions are coupled together via a short metal line. In either example, it is appreciated that this horizontal arrangement minimizes capacitance. As shown in the example B-cell, the source region of first row select transistor  820 BL is coupled to bitline BL 0   812 L, while the source regions of first row select transistor  820 BR, second row select transistor  834 BL, and second row select transistor  834 BR are coupled to bitline BL 1   812 R. 
     As can be appreciated, the layout illustrated in  FIG.  8    is designed that there is no significant difference in the semiconductor patterning between the A-cells and the B-cells. The differences between the A-cells and the B-cells are that the relative physical locations of the pairs of first and second row select transistors  820 AL/ 834 AL,  820 AR/ 834 AR,  820 BL/ 834 BL,  820 BR/ 834 BR, are switched horizontally relative to one another from left-to-right or from right-to-left as shown. As can be observed in the depicted example, the second row select transistors  834 AL,  834 AR,  834 BL,  834 BR are disposed or physically located in the semiconductor material closer to the column bitline BL 0   812 L or column BL 1   812 R that they are coupled to when compared to the corresponding first row select transistors  820 AL,  820 AR,  820 BL,  820 BR of same shared pixel cell. 
     To illustrate, the example depicted in  FIG.  8    shows that for the A-cells in the top row, the second row select transistors  834 AL,  834 AR that are responsive to the second row select signal RS 1  are both coupled to the first column bitline BL 0   812 L on the left side  838 L of the illustrated arrangement. Thus, the second row select transistors  834 AL,  834 AR are disposed or physically located in the semiconductor material closer to the first column bitline BL 0   812 L when compared to the corresponding first row select transistors  820 AL,  820 AR. Similarly, in the B-cells in the next row, the second row select transistors  834 BL,  834 BR that are responsive to the second row select signal RS 1  are both coupled to the second column bitline BL 1   812 R on the right side  838 R of the illustrated arrangement. Thus, the second row select transistors  834 BL,  834 BR are disposed or physically located in the semiconductor material closer to the second column bitline BL 1   812 R on the right side  838 R when compared to the corresponding first row select transistors  820 AL,  820 AR. As mentioned, in the various examples, this alternating layout pattern repeats for down the rows for each column in accordance with the teachings of the present invention. 
     It is further appreciated that the physical locations of the first column bitline BL 0   812 L and the second column bitline BL 1   812 R are the same for the A-cells in the top row and the B-cells in the next row. As such, only the metal connections and vias differ only slightly between the A-cells in the top row and the B-cells in the next row in the depicted layout in order to couple the row select transistors to the column bitlines. As such, the bitline metal capacitance is minimized in this layout example in accordance with the teachings of the present invention. 
       FIG.  9    shows generally a top view of an example layout an arrangement of shared pixel cells including a left 2×4 shared pixel cell and a right shared pixel cell included in a pixel array with binning implemented with dual row select transistors in accordance with the teachings of the present invention. It is appreciated that the 16C arrangement of shared pixel cells illustrated in  FIG.  9    may be an example of one of the 16C arrangements of shared pixel cells discussed above, and the similarly named and numbered elements described above are coupled and function similarly below. It is also noted that the example depicted in  FIG.  9    describes 2×4 arrangements of photodiodes for explanation purposes, but that in other examples, different arrangements of photodiodes, such as 2×2 arrangements of photodiodes, etc., may be included in the shared pixel cells in accordance with the teachings of the present invention. 
     As shown in the example depicted in  FIG.  9   , the left shared pixel cell includes the photodiodes P 1 -P 8  disposed in semiconductor material  936  (e.g., silicon), which are coupled to generate image charge in response to incident light. In the example, the photodiodes P 1 -P 8  are coupled to transfer their photogenerated image charge to a floating diffusion FD, which is coupled to dual source followers  918 L- 1 / 918 L- 2 . In the specific example depicted in  FIG.  9   , it is noted that there is a floating diffusion FD disposed in semiconductor material  936  in a central location relative to photodiodes P 1 -P 4  and a floating diffusion FD disposed in semiconductor material  936  in a central location relative to photodiodes P 5 -P 8 . In the example, these floating diffusions FD may be coupled together and to the gate terminals of the two source followers  918 L- 1 / 918 L- 2  with a metal line in a metal layer that is out of view in the illustration. In the example, the dual source follower transistors  918 L- 1 / 918 L- 2  are implemented with the common junction sharing design technique by sharing source regions of the two source followers  918 L- 1 / 918 L- 2 , as illustrated with the common junction including the shared region between the gates of the source follower transistors  918 L- 1 / 918 L- 2 . The reset transistor  924 L is coupled to reset the pixel cell, and the dual conversion gain transistor  922 L is coupled to enable an LCG mode when turned on and an HCG mode when turned off. It is appreciated that the corresponding photodiodes P 1 -P 8 , floating diffusions FD, dual source followers  918 R- 1 / 918 R- 2 , reset transistor  924 R, and dual conversion gain transistor  922 R of the right shared pixel cell are coupled and function similarly as their left shared pixel cell counterparts. 
     Similar to the example described above in  FIG.  8   , the 16C arrangement of left and right shared pixel cells also includes a first row select transistor  920 L disposed proximate to a second row select transistor  934 L. In addition, a first row select transistor  920 R is disposed proximate to a second row select transistor  934 R. As shown in the example, the first and second row select transistors  920 L and  934 L and the first and second row select transistors  920 R and  934 R are horizontally arranged such that their respective drain regions are adjacent to or overlapping with one another in the semiconductor material  936 . In one example, these adjacent drain regions are shared regions and are therefore coupled together by sharing the drain with the silicon junction in common with split source junction regions of the respective source followers  918 L- 1 / 918 L- 2 ,  918 R- 1 / 918 R- 2 . By sharing the common drain in the semiconductor (e.g., silicon) junction, no metal interconnection and no isolation structure are required. As such, with the common junction sharing design technique utilized in one example for the dual source followers  918 L- 1 / 918 L- 2 , a split source junction region of the dual source followers  918 -L 1 / 918 L- 2  into the shared drain region of the two row select transistors  920 L,  934 L in the common junction provide improved direct coupling through the semiconductor material (e.g., silicon) with no additional metal and no isolation required. However, in another example, it is appreciated that these adjacent regions may be coupled together via a short metal line. In either example, it is appreciated that this horizontal adjacent drain arrangement illustrated in the example of  FIG.  9    minimizes capacitance. 
     Similarly, the drain regions of first row select transistor  920 R and second row select transistor  934 R are coupled to the source regions of dual source followers  918 R- 1 / 918 R- 2 . As mentioned, in one example, the dual source followers  918 R- 1 / 918 R- 2  are also implemented with the common junction sharing, as also illustrated with the shared regions between the gates of the source follower transistors  918 R- 1 / 918 R- 2 . Thus, in the example, there is a common shared junction region between the gates of the dual source followers and between the gates of the two row select transistors of each shared pixel cell in accordance with the teachings of the present invention. In one example, the source region of first row select transistor  920 L is coupled to bitline BL 0  (not shown), while the source regions of first row select transistor  920 R, second row select transistor  934 L, and second row select transistor  934 R are coupled to bitline BL 1  (not shown). 
     In one example, it is appreciated that the layout pattern of the 16C arrangement of left and right shared pixel cells illustrated in  FIG.  9    can substantially replicated or for repeated for a layout of 16C arrangement in a neighboring row, with the exception of switching or alternating the relative horizontal positions of the first and second row select transistors  920 L/ 934 L and  920 R/ 934 R, as discussed above in  FIG.  8   . As such, only the metal connections and vias differ slightly, and the bitline metal capacitance is minimized in this layout style. 
     Therefore, assuming that the layout illustrated in  FIG.  9    is an example of a B-cell as discussed above for instance in  FIGS.  7 - 8   , it is noted that an example layout of an A-cell compared to the example layout shown in  FIG.  9    is also designed so that there is no significant difference in the semiconductor patterning between the A-cells and the B-cells. Similar to the example described above in  FIG.  8   , the differences between the A-cells and the B-cells shown in  FIG.  9    are that the relative physical locations of the pairs of first and second row select transistors  920 AL/ 934 AL,  920 AR/ 934 AR, are switched horizontally relative to one another from left-to-right or from right-to-left. 
     To illustrate, assuming that  FIG.  9    shows an example layout of a B-cell, the depicted example the second row select transistors  934 L,  934 R that are responsive to the second row select signal RS 1  are disposed or physically located in the semiconductor material closer  936  to the right side  938 R of the illustrated arrangement, which is closer to the physical location of the column bitline that the second row select transistors  934 L,  934 R are coupled to, when compared to the corresponding first row select transistors  920 L,  920 R that are responsive to the first row select signal RS 0 . In an example layout of an A-cell, which would be in the next row, it is appreciated that the second row select transistors that are responsive to the second row select signal RS 1  are disposed or physically located in the semiconductor material  936  closer to the left side  938 L of the illustrated arrangement when compared to the corresponding first row select transistors that are responsive to the first row select signal RS 0 . Similar to the example described in  FIG.  8    above, it is also appreciated that the physical locations of the first column bitline BL 0  the second column bitline BL 1  are the same for the A-cells and the B-cells in the next row for the example depicted in  FIG.  9   . As such, only the metal connections and vias differ slightly between the A-cells of one row and the B-cells of a next row in the depicted layout in order to couple the row select transistors to the column bitlines. As such, the bitline metal capacitance is minimized in this layout example in accordance with the teachings of the present invention. 
       FIG.  10    shows generally a top view of another example layout an arrangement of shared pixel cells including a left 2×4 shared pixel cell and a right shared pixel cell included in a pixel array with binning implemented with dual row select transistors in accordance with the teachings of the present invention. It is appreciated that the 16C arrangement of shared pixel cells illustrated in  FIG.  10    may be another example of one of the 16C arrangements of shared pixel cells discussed above, and the similarly named and numbered elements described above are coupled and function similarly below. It is also noted that the example depicted in  FIG.  10    describes 2×4 arrangements of photodiodes for explanation purposes, but that in other examples, different arrangements of photodiodes, such as 2×2 arrangements of photodiodes, etc., may be included in the shared pixel cells in accordance with the teachings of the present invention. 
     It is also appreciated that the example layout illustrated in  FIG.  10    shares many similarities with the example layout illustrated in  FIG.  9   . For instance, as shown in the example depicted in  FIG.  10   , the left shared pixel cell includes the photodiodes P 1 -P 8  disposed in semiconductor material  1036  (e.g., silicon), which are coupled to generate image charge in response to incident light. In the example, the photodiodes P 1 -P 8  are coupled to transfer their photogenerated image charge to a floating diffusion FD, which is coupled to dual source followers  1018 L- 1 / 1018 L- 2 . In the specific example depicted in  FIG.  10   , it is noted that there is a floating diffusion FD disposed in semiconductor material  1036  in a central location relative to photodiodes P 1 -P 4  and a floating diffusion FD disposed in semiconductor material  1036  in a central location relative to photodiodes P 5 -P 8 . In the example, these floating diffusions FD may be coupled together and to the gate terminals of the two source followers  1018 L- 1 / 1018 L- 2  with a metal line in a metal layer that is out of view in the illustration. In the depicted example, the dual source follower transistors  1018 L- 1 / 1018 L- 2  are implemented with the common junction sharing design technique by sharing source regions of the two source followers  1018 L- 1 / 1018 L- 2 , as illustrated with the shared region between the gates of the source follower transistors  1018 L- 1 / 1018 L- 2 . The reset transistor  1024 L is coupled to reset the pixel cell, and the dual conversion gain transistor  1022 L is coupled to enable an LCG mode when turned on and an HCG mode when turned off. It is appreciated that the corresponding photodiodes P 1 -P 8 , floating diffusions FD, dual source followers  1018 R- 1 / 1018 R- 2 , reset transistor  1024 R, and dual conversion gain transistor  1022 R of the right shared pixel cell are coupled and function similarly as their left shared pixel cell counterparts. 
     One of the differences between the example layout illustrated in  FIG.  10    and the example layout illustrated in  FIG.  9    is that in the example illustrated in  FIG.  10   , the row select transistors are placed in a vertical arrangement instead of a horizontal arrangement. To illustrate, if it is assumed that the column bitlines are aligned along a vertical axis on the page (e.g., as also illustrated in previous examples described above), a first row select transistor  1020 L is disposed proximate to a second row select transistor  1034 L in a relative vertical location (on the page) parallel to the column bitlines. In addition, a first row select transistor  1020 R is disposed proximate to a second row select transistor  1034 R in a relative vertical location (on the page) parallel to the column bitlines. As such, each of the pair of first and second row select transistors  1020 L/ 1034 L has the same lateral distance to the left side  1038 L and/or right side  1038 R of the illustrated arrangement. Similarly, each of the pair of first and second row select transistors  1020 R/ 1034 R is the same lateral distance to the left side  1038 L and/or right side  1038 R of the illustrated arrangement. Thus, as shown in the example, the first and second row select transistors  1020 L and  1034 L and the first and second row select transistors  1020 R and  1034 R are vertically arranged (e.g., parallel to the column bitlines). Further, with the depicted layout, the respective drain regions of the pairs of rows select transistors  1020 L/ 1034 L,  1020 R/ 1034 R are also adjacent to or overlapping with one another in the semiconductor material  1036 . In one example, these adjacent drain regions are shared regions and are therefore coupled together by sharing the drain with the silicon junction in common with split source junction regions of the respective source followers  1018 L- 1 / 1018 L- 2 ,  1018 R- 1 / 1918 R- 2 . By sharing the common drain in the semiconductor (e.g., silicon) junction, no metal interconnection and no isolation structure are required. As such, with the common junction sharing design technique utilized in one example for the dual source followers  1018 -L 1 / 1018 L- 2 , a split source junction region of the dual source followers  1018 -L 1 / 1018 L- 2  into the shared drain region of the two row select transistors  1020 -L,  1034 L in the common junction provide improved direct coupling through the semiconductor material (e.g., silicon) with no additional metal and no isolation required. However, in another example, it is appreciated that these adjacent regions may be coupled together via a short metal line. In either example, it is appreciated that this adjacent drain arrangement illustrated in the example of  FIG.  10    also minimizes capacitance. 
     Similarly, the drain regions of first row select transistor  1020 R and second row select transistor  1034 R are coupled to the source regions of dual source followers  1018 R- 1 / 1018 R- 2 . In one example, the dual source followers  1018 R- 1 / 1018 R- 2  are also implemented with the common junction sharing, as also illustrated with the shared regions between the gates of the source follower transistors  1018 R- 1 / 1018 R- 2 . Thus, in the example, there is a common shared junction region between the gates of the dual source followers and between the gates of the two row select transistors of each shared pixel cell in accordance with the teachings of the present invention. 
       FIG.  11    shows yet another example illustrating an arrangement of several rows of shared pixel cells included in a pixel array with binning implemented with second row select transistors coupling source followers from pixel cells to a bitline of other pixel cells in accordance with the teachings of the present invention. It is noted that the example depicted in  FIG.  11    describes 2×4 arrangements of photodiodes for explanation purposes, but that in other examples, different arrangements of photodiodes, such as a 2×2 arrangements of photodiodes, etc., may be included in the shared pixel cells in accordance with the teachings of the present invention. It is also appreciated that the pixel cells illustrated in  FIG.  11    share some similarities with pixel cell  204 , which is described in detail above in connection with  FIG.  2 A , and that the similarly named and numbered elements described above are coupled and function similarly below. Further, it is appreciated therefore that the coupling and operation of shared pixel cells are not be described again in complete detail for the sake of brevity. 
     It is also appreciated that the example layout illustrated in  FIG.  11    shares some similarities with the example layout illustrated in  FIG.  7   . For instance,  FIG.  11    shows an arrangement of shared pixel cells, which include shared pixel cells  1104 A,  1104 B,  1104 C,  1104 D in a first row in  FIG.  11   , and shared pixel cells  1104 E,  1104 F,  1104 G,  1104 H in a second row. In the example, shared pixel cells  1104 A and  1104 E are coupled to bitline BL 0   1112 A, which is coupled to column ADC  1106 A, shared pixel cells  1104 B and  1104 F are coupled to bitline BL 1   1112 B, which is coupled to column ADC  1106 B, shared pixel cells  1104 C and  1104 G are coupled to bitline BL 2   1112 C, which is coupled to column ADC  1106 C, and shared pixel cells  1104 D and  1104 H are coupled to bitline BL 3   1112 D, which is coupled to column ADC  1106 D. 
     In the example depicted in  FIG.  11   , each shared pixel cell includes eight photodiodes P 1 -P 8 , which share a respective floating diffusion FD. In the example, photodiodes P 5 -P 8  of shared pixel cells  1104 A,  1104 C,  1104 E,  1104 G are configured to detect red (R) light, photodiodes P 1 -P 4  of shared pixel cells  1104 A,  1104 C,  1104 E,  1104 G and photodiodes P 5 -P 8  of shared pixel cells  1104 B,  1104 D,  1104 F,  1104 H are configured to detect green (G) light, and photodiodes P 1 -P 4  of shared pixel cells  1104 B,  1104 D,  1104 F,  1104 H are configured to detect blue (B) light. 
     It is appreciated that the arrangement of shared pixel cells  1104 A,  1104 B,  1104 C,  1104 D,  1104 E,  1104 F,  1104 G,  1104 H shown in  FIG.  11    can be applied to 2×2 or 2×4 or other shared pixel structures. Although the depicted example illustrates dual conversion gain (DCG) pixel cells with the inclusion of dual conversion gain transistors and second floating diffusions FD 2 , the arrangement can also be applied single conversion gain (SCG) pixel cell configurations. It is also noted that the example depicted in  FIG.  11    also includes metal interconnects  1132 A,  1132 C,  1132 E,  1132 G connecting two second floating diffusions FD 2  between shared pixel cells, it is appreciated that the metal interconnects  1132 A,  1132 C,  1132 E,  1132 G are optional as discussed above and can be removed with binning that can also be provided with second row select transistors RS 1  as discussed above. 
     It is noted that one difference between the arrangement illustrated in  FIG.  11    and previously described arrangements is that there are intervening columns of pixel cells between columns of pixel cells that are coupled together through the second row select transistors. For instance, as shown in the example depicted in  FIG.  11   , a first column may include shared pixel cells  1104 A and  1104 E, which are coupled to column bitline BL 0   1112 A through respective first and second row select transistors. A second column may include shared pixel cells  1104 C and  1104 G, which are coupled to column bitline BL 2   1112 C through respective first row select transistors. The second column pixel cells includes second row select transistors that are also coupled to the column bitline BL 0   1112 A. 
     However, the example depicted in  FIG.  11    also illustrates that there is a third column of pixel cells  1104 B,  1104 F coupled to column bitline BL 1   1112 B. As shown in the depicted example, the third column of pixel cells  1104 B,  1104 F and column bitline BL 1   1112 B are disposed between the first column of pixel cells  1104 A,  1104 E and the second column of pixel cells  1104 C,  1104 G. Similarly, the second column of pixel cells  1104 C,  1104 G and column bitline BL 2   1112 C are disposed between the third column of pixel cells  1104 B,  1104 G and a fourth column of pixel cells  1104 D,  1104 H, as shown. 
     With the metal interconnects  1132 A,  1132 C,  1132 E,  1132 G connecting two second floating diffusions FD 2  as shown, LCG mode readouts are provided with true FD binning of the 16 photodiodes of the two connected shared pixel cells, while HCG mode readouts are provided with bitline binning through two source followers, with each source follower coupled to generate the FD binning signal of the 8 photo diodes from same 2×4 shared pixel. In LCG mode readouts, it is appreciated that the effective source follower size is doubled, which results in faster bitline settling time when compared to single source follower configurations. Without the metal interconnects  1132 A,  1132 C,  1132 E,  1132 G connecting two second floating diffusions FD 2 , both HCG and LCG mode readouts may still be binned through the two source followers via the respective second row select RS 1  transistors. 
     The arrangement of shared pixel cells shown in  FIG.  11    can also be applied when horizontal binning (for 4Cs of the same color, for instance) is required. An example of the 4C color pattern arrangement is illustrated in  FIG.  11    with the 2×2 groupings of red (R), green (G), and blue (B) color filters over the photodiodes as shown. 
       FIG.  12    shows another example illustrating an arrangement of shared pixel cells included in a pixel array with binning implemented with second row select transistors coupling the shared pixel cells to bitlines of other pixel cells in accordance with the teachings of the present invention. It is appreciated that the shared pixel cells illustrated in  FIG.  12    share similarities with the example shared pixel cells discussed above, and that the similarly named and numbered elements described above are coupled and function similarly below. Further, it is appreciated therefore that the coupling and operation of shared pixel cells are not be described again in complete detail for the sake of brevity. It is also noted that the example depicted in  FIG.  12    describes 2×4 arrangements of photodiodes for explanation purposes, but that in other examples, different arrangements of photodiodes, such as 2×2 arrangements of photodiodes, etc., may be included in the shared pixel cells in accordance with the teachings of the present invention. 
     As shown, the example arrangement depicted in  FIG.  12    illustrates that the dual row select transistor configurations in accordance with the teachings of the present invention may also be applied to RGB Bayer pattern color filter arrangements for full resolution as well as binning (e.g., 2×2, 2×4, etc.) modes. As shown in the example, a shared pixel cell  1204 A coupled to a bitline BL 0   1212 A and a shared pixel cell  1204 E coupled to a bitline BL 4   1212 E. Each shared pixel cell  1204 A,  1204 E illustrated in  FIG.  12    includes photodiodes P 1 -P 8 , which are coupled to floating diffusions that are coupled to respective source follower transistors  1218 A,  1218 E, as shown. In the depicted example, shared pixel cell  1204 A includes a first row select transistor  1220 A coupled between the source region of source follower transistor  1218 A and bitline BL 0   1212 A. Shared pixel cell  1204 A also includes a second row select transistor  1234 A coupled between the source region of source follower transistor  1218 A and bitline BL 0   1212 A. As mentioned in previous examples, the drain regions of the dual row select transistors  1220 A,  1234 A may be shared in one example, or may be coupled together through a short metal connection in another example. Continuing with the example depicted in  FIG.  12   , shared pixel cell  1204 E includes a first row select transistor  1220 E coupled between the source region of source follower transistor  1218 E and bitline BL 4   1212 E. Shared pixel cell  1204 E also includes a second row select transistor  1234 E coupled between the source region of source follower transistor  1218 E and bitline BL 4   1212 E. As mentioned in previous examples, the drain regions of the dual row select transistors  1220 B,  1234 B may be shared in one example, or may be coupled together through a short metal connection in another example. 
     The example arrangement depicted in  FIG.  12    has the flexibility to be operated in a variety of modes. For example, with the second row select transistors  1234 A,  1234 B turned off in response to row select signal RS 1 , the first row select transistors  1220 A,  1220 E can be turned on to readout individual photodiodes, such for instance the blue (B) photodiode P 1  of shared pixel cells  1204 A,  1204 E, through bitline BL 0   1212 A and through bitline BL 4   1212 E, respectively, for a full resolution mode (1C) readout. 
     In another example, with the first row select transistors  1220 A,  1220 E turned off in response to row select signal RS 0 , the second row select transistors  1234 A,  1234 E can be turned on in response to row select signal RS 1  to readout binned photodiodes, such for instance the blue (B) photodiode P 1  binned with the blue (B) photodiode P 5  of shared pixel cells  1204 A,  1204 E, through bitline BL 0   1212 A for a 2×2 binning mode (4C) readout. In this example, the blue (B) photodiodes P 1  and P 5  image signals are charge binned at the floating diffusion from each shared pixel cell  1204 A,  1204 E, and the signals are then averaged through the outputs of source follower transistors  1218 A,  1218 E, which is then read out through it bitline BL 0   1212 A for a 4C binned readout. 
     It is appreciated of course the readouts of the blue (B) photodiodes P 1 , P 5  are described above for explanation purposes and that the red (R) photodiodes P 4 , P 8  and/or green (G) photodiodes P 2 , P 6  or P 3 , P 7  can be read out similarly. 
       FIG.  13    shows still another example illustrating an arrangement of shared pixel cells included in a pixel array with binning implemented with second row select transistors coupling the shared pixel cells to bitlines of other pixel cells to provide binning without crosstalk in accordance with the teachings of the present invention. It is appreciated that the shared pixel cell arrangement as illustrated in  FIG.  13    share many similarities with the example shared pixel cell arrangement as illustrated in  FIG.  12    discussed above, and that the similarly named and numbered elements described above are coupled and function similarly below. Further, it is appreciated therefore that the coupling and operation of shared pixel cells are not be described again in complete detail for the sake of brevity. It is also noted that the example depicted in  FIG.  13    describes 2×4 arrangements of photodiodes for explanation purposes, but that in other examples, different arrangements of photodiodes, such as 2×2 arrangements of photodiodes, etc., may be included in the shared pixel cells in accordance with the teachings of the present invention. 
     As shown, the example arrangement depicted in  FIG.  13    illustrates a 32 row period of shared pixel cells that are arranged similar to the dual row select transistor RGB pattern color filter arrangement illustrated in  FIG.  12   . In the example, the row select signal RS 0  is configured to turn on the first row select transistors for a full resolution (1C) readout while the row select signal RS 1  is configured to turn off the second row select transistor. These examples are depicted in  FIG.  13    with the solid line coupled between the bitlines and the shared pixel cells. 
     In the example, the row select signal RS 1  is configured to turn on the second row select transistors for a 2×2 binning mode (4C) readout while the row select signal RS 0  is configured to turn off the first row select transistor. These examples are depicted in  FIG.  13    with the dashed-line coupled between the bitlines and the shared pixel cells. 
     As shown, shared pixel cell  1304 - 1 A is coupled to bitline BL 0   1312 A and shared pixel cell  1304 - 1 E is coupled to bitline BL 4   1312 E in response to row select signal RS 0  for full resolution (1C) readout mode. Shared pixel cell  1304 - 1 A and shared pixel cell  1304 - 1 E are both coupled to bitline BL 0   1312 A in response to row select signal RS 1  for 2×2 binning (4C) readout mode. 
     Shared pixel cell  1304 - 2 A is coupled to bitline BL 1   1312 B and shared pixel cell  1304 - 2 E is coupled to bitline BL 5   1312 F in response to row select signal RS 0  for full resolution (1C) readout mode. Shared pixel cell  1304 - 2 A and shared pixel cell  1304 - 2 E are both coupled to bitline BL 1   1312 B in response to row select signal RS 1  for 2×2 binning (4C) readout mode. 
     Shared pixel cell  1304 - 3 A is coupled to bitline BL 2   1312 C and shared pixel cell  1304 - 3 E is coupled to bitline BL 6   1312 G in response to row select signal RS 0  for full resolution (1C) readout mode. Shared pixel cell  1304 - 3 A and shared pixel cell  1304 - 3 E are both coupled to bitline BL 2   1312 C in response to row select signal RS 1  for 2×2 binning (4C) readout mode. 
     Shared pixel cell  1304 - 4 A is coupled to bitline BL 3   1312 D and shared pixel cell  1304 - 4 E is coupled to bitline BL 7   1312 H in response to row select signal RS 0  for full resolution (1C) readout mode. Shared pixel cell  1304 - 4 A and shared pixel cell  1304 - 4 E are both coupled to bitline BL 3   1312 D in response to row select signal RS 1  for 2×2 binning (4C) readout mode. 
     Shared pixel cell  1304 - 5 A is coupled to bitline BL 0   1312 A and shared pixel cell  1304 - 5 E is coupled to bitline BL 4   1312 E in response to row select signal RS 0  for full resolution (1C) readout mode. Shared pixel cell  1304 - 5 A and shared pixel cell  1304 - 5 E are both coupled to bitline BL 4   1312 E in response to row select signal RS 1  for 2×2 binning (4C) readout mode. 
     Shared pixel cell  1304 - 6 A is coupled to bitline BL 1   1312 B and shared pixel cell  1304 - 6 E is coupled to bitline BL 5   1312 F in response to row select signal RS 0  for full resolution (1C) readout mode. Shared pixel cell  1304 - 6 A and shared pixel cell  1304 - 6 E are both coupled to bitline BL 5   1312 F in response to row select signal RS 1  for 2×2 binning (4C) readout mode. 
     Shared pixel cell  1304 - 7 A is coupled to bitline BL 2   1312 C and shared pixel cell  1304 - 7 E is coupled to bitline BL 6   1312 G in response to row select signal RS 0  for full resolution (1C) readout mode. Shared pixel cell  1304 - 7 A and shared pixel cell  1304 - 7 E are both coupled to bitline BL 6   1312 G in response to row select signal RS 1  for 2×2 binning (4C) readout mode. 
     Shared pixel cell  1304 - 8 A is coupled to bitline BL 3   1312 D and shared pixel cell  1304 - 8 E is coupled to bitline BL 7   1312 H in response to row select signal RS 0  for full resolution (1C) readout mode. Shared pixel cell  1304 - 8 A and shared pixel cell  1304 - 8 E are both coupled to bitline BL 7   1312 H in response to row select signal RS 1  for 2×2 binning (4C) readout mode. 
     The above description of illustrated examples of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. 
     These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.