Patent Publication Number: US-9424970-B2

Title: High-k transformers extending into multiple dielectric layers

Description:
BACKGROUND 
     Transformers are widely used in the wireless communication, such as chip-to-chip wireless communication, in which signals are transmitted from one chip to a neighboring chip wirelessly. One application of the chip-to-chip wireless communication is the signal transmission between a memory (for example, a dynamic random access memory (DRAM)) and a graphics processing unit (GPU). Due to the big number of transformers that may be used in the chip-to-chip wireless communication, the coupling-coefficients (k) of the transformers became a very important factor for reducing power consumption, for increasing communication distances, and for increasing signal-to-noise ratios. 
     Conventionally, to improve the k values of transformers that include two inductors formed on different chips, various approaches have been taken, which include reducing the thickness of chips so that the distances between the inductors may be reduced. This requires the chips to be ground to a very small thickness, and hence the process complexity in the handling of the respective wafers and chips is increased, and a higher cost may be involved. The improvement in the k values of the transformers may also be achieved by increasing areas of the transformers, and increasing magnetic flux density in the transformers. These methods, however, cause the chip area occupied by the transformers to be increased. For applications in which many transformers are involved, the increase in the chip area may be significant. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  illustrates a cross-sectional view of metal bridge portions of an inductor formed in a chip; 
         FIGS. 2 and 3  are top views of an upper portion and a lower portion of an inductor, respectively; 
         FIG. 4  illustrates a combined top view of the structures shown in  FIGS. 2 and 3 ; 
         FIG. 5  illustrates semi-turn portions of the inductor shown in  FIGS. 2 through 4 ; and 
         FIG. 6  illustrates a cross-sectional view of a portion of a transformer formed of two inductors, each in one of two chips, with the two chips bonded together. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure. 
     A novel transformer and the method of forming the same are provided in accordance with an embodiment. The variations and the operation of the embodiment are then discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. In the subsequent discussion, an inductor may be referred to as a transformer, since it may be a part of a transformer that includes two inductors formed on two chips. 
       FIG. 1  illustrates a cross-sectional view of a portion of a wafer or a chip (referred to as wafer/chip hereinafter)  100 , in which inductor  22  is formed. Wafer/chip  100  includes substrate  110 , which may be an organic substrate, a ceramic substrate, or a semiconductor substrate such as a silicon crystalline substrate. Active devices such as transistors (not shown) may be formed at top surface  110 A of semiconductor substrate  110 . Inductor  22  may be used to form a primary or secondary part (winding) of transformer  222  (not shown in  FIG. 1 , please refer to  FIG. 6 ). Interconnect structure  122 , which includes metal lines  124  and vias  126  formed therein and electrically coupled to the semiconductor devices, is formed over substrate  110 . Metal lines  124  and vias  126  may be formed of copper or copper alloys, and may be formed using damascene processes. Interconnect structure  122  may include inter-layer dielectric (ILD)  128  and inter-metal dielectrics (IMDs)  132 . 
     IMDs  132  may include a plurality of dielectric layers. The metal layers in IMDs  132  are referred to as metal layers M 1  through Mtop, with the metal layers including metal lines  124  and vias  126 . Metal layer M 1  is the bottom metal layer over substrate  110 , with no additional metal layer under metal layer M 1  and over substrate  110 . Metal layer Mtop is the top metal layer formed in low-k dielectric layer. Metal layers M 1  through Mtop may be formed of copper or copper alloys. In an exemplary embodiment, metal layer M 9  is metal layer Mtop. However, depending on the number of IMD layers  132 , the integer “top” may represent an integer greater or smaller than 9. IMDs  132  may be low-k dielectric layers having k values lower than about 3.0 or 2.5, for example. Redistribution line (RDL) layer(s), which may comprise one or more layers, may be formed over IMDs  132 . The RDL layers may include metal line portions and via portions, which are referred to as RDLs  136 . RDLs  136  may be formed of aluminum, aluminum copper, or the like. Dielectric layer(s)  138 , in which RDLs  136  are formed, may be formed of non-low-k dielectric materials (which have dielectric constants greater than 3.8), such as un-doped silicate glass (USG), silicon oxide, silicon nitride, or multi-layers thereof. 
       FIG. 1  also illustrates a cross-sectional view of a portion of inductor  22 , which comprises metal lines  124 , vias  126 , and optionally RDLs  136  that are electrically coupled to each other. It is appreciated that chip/wafer  100  may include a plurality of inductors  22 , although  FIG. 1  only illustrates one inductor  22 . The cross-sectional view as shown in  FIG. 1  may be obtained from the planes crossing lines  1 - 1  in  FIG. 4 . 
       FIGS. 2 and 3  illustrate top views of inductor  22 , wherein the top view shown in  FIG. 2  represents upper portion  22 A (also see  FIG. 1 ) of inductor  22 . Upper portion  22 A is located in upper ones of metal layers M 1  through Mtop and RDLs. The top view shown in  FIG. 3  represents lower portion  22 B of inductor  22 , wherein the lower portion  22 B is located in lower ones of metal layers M 1  through Mtop, and possibly RDLs (also refer to  FIG. 1 ). Portions of upper portion  22 A of inductor  22  may be directly over and overlapping portions of lower portion  22 B. 
     Referring back to  FIG. 1 , in an embodiment, upper portion  22 A extends from the top layer of the RDLs to one of the metal layers M 1  through M 9 . For example, upper portion  22 A may include portions in each of the RDLs and M 9 . Correspondingly, lower portion  22 B extends into each of metal layers M 1  through M 8 . In alternative embodiments, the bottom metal layer of lower portion  22 B may be any of the metal layers over, and not including, metal layer M 1 . For example, the lower portion  22 B may include metal layers M 2  through M 8 , M 3  through M 8 , or the like. In the embodiments M 9  belongs to upper portion  22 A, and M 8  belongs to lower portion  22 B, the via layer V 89 , which is between metal layers M 8  and M 9 , is the dividing via layer that divides upper portion  22 A from lower portion  22 B. Alternatively, the dividing layer may be via layers V 78 , V 67 , or the like. In each of upper portion  22 A and lower portion  22 B, metal lines  124  and vias  126  are formed in each of the corresponding metal layers and via layers, so that from the top layer to the bottom layer of each of upper portion  22 A and lower portion  22 B, metal lines  124  and vias  126  are connected to form an integrated and continuous metal feature. 
     Referring again to  FIG. 1 , the total thickness T 1  of upper portion  22 A may be close to the total thickness T 2  of lower portion  22 B, wherein thicknesses T 1  and T 2  are measured in the direction perpendicular to major surface  110 A of substrate  110 . Accordingly, the selection of the dividing layer that separates upper portion  22 A from lower portion  22 B is related to the thicknesses of metal layers M 1  through RDL. Since the upper ones of metal layers M 1  through M 9  may be thicker than the lower ones, upper portion  22 A may include fewer layers than lower portion  22 B. In an embodiment, a value |(T 1 −T 2 )/(T 1 +T 2 )| may be calculated to determine which dividing layer is the optimal layer, which means that if this dividing layer is used, thickness T 1  of upper portion  22 A is closest to thickness T 2  of lower portion  22 B. Alternatively stating, the optimal dividing scheme has an effect that if one more layer in upper portion  22 A is re-divided into lower portion  22 B, or one more layer in lower portion  22 B is re-divided into upper portion  22 A, the value |(T 1 −T 2 )/(T 1 +T 2 )| will increase. 
     Referring again to  FIG. 2 , the illustrated upper portion  22 A includes a plurality of semi-turns, wherein two of the semi-turns  22 A in combination may form a ring-like structure (such as ring 1 , ring 2 , or ring 3 ), which is close to a ring, except the ring-like structure has at least one break, and possibly two breaks therein. Throughout the description, the term “semi-turn” is used to refer to a shape close to a half (a 180-degree turn) of a ring, and two semi-turns in combination may form a ring-like structure (a 360 degree turn). In the exemplary embodiment as shown in  FIG. 2 , each of the semi-turns  22 A 1  and  22 A 2  includes three sections, with the middle section connected between, and perpendicular to, the other two sections. Semi-turns  22 A 1  and  22 A 2  form three ring-like structures ring 1 , ring 2 , and ring 3 , with breaks  26 A in each of ring-like structures. Furthermore, ring-like structures ring 1 , ring 2 , and ring 3  may form a concentric pattern, with outer ones of the ring-like structures ring 1 , ring 2 , and ring 3  surrounding/encircling the inner ones. Bridges  22 A 3  may be formed to interconnect the semi-turns that belong to different ring-like structures ring 1 , ring 2 , and ring 3 . 
     Similarly, in  FIG. 3 , the illustrated lower portion  22 B also includes a plurality of semi-turns  22 B 1  and  22 B 2  that are vertically overlapping the corresponding semi-turns of upper portion  22 A, wherein two of the semi-turns of lower portion  22 B in combination may form a ring-like structure. For example, semi-turns  22 B 1  and  22 B 2  form a ring-like structure, with breaks  26 B therein. In addition, the ring-like structures in lower part  22 B may form a concentric pattern, with outer ones of the ring-like structures surrounding the inner ones. Bridges  22 B 3  may be formed to interconnect the semi-turns that belong to different ring-like structures. In the exemplary embodiment as shown in  FIG. 3 , each of the semi-turns  22 B 1  and  22 B 2  includes three sections, with the middle section connected between, and perpendicular to, the other two sections. 
       FIG. 4  illustrates a top view of inductor  22 , with both upper portion  22 A and lower portion  22 B shown in  FIG. 4 . The cross-sectional view shown in  FIG. 1  may be obtained from the planes crossing lines  1 - 1  in  FIG. 4 . Metal bridges  22 A 3  and  22 B 3  cross each other in the top view. Semi-turns  22 A 1  ( FIG. 2 ) and the corresponding underlying semi-turns  22 B 1  ( FIG. 3 ) include portions vertically overlap each other, and semi-turns  22 A 2  ( FIG. 2 ) and the corresponding semi-turns  22 B 2  ( FIG. 3 ) include portions vertically overlap each other, wherein the overlapped portions are marked as  22 A/ 22 B in  FIG. 4 . Semi-turns  22 A and  22 B are further connected to ports  28 A and  28 B, at which points the transformer also extend from M 1  through RDL. 
       FIG. 5  illustrates a cross-sectional view of a semi-turn portion of inductor  22 , wherein the cross-sectional view is obtained along planes crossing lines  5 - 5  in  FIG. 4 . It is observed that the semi-turns such as  22 A 1  of upper portion  22 A and the respective underlying semi-turns  22 B 1  of lower portion  22 B are integrated as a single integrated semi-turn through metal via(s) in the dividing layer (via layer V 89  in the illustrated example) that separates upper portion  22 A from lower portion  22 B. Accordingly, in the semi-turn portions, metal lines  124  and vias  126  are formed in each of the corresponding metal layers and via layers, so that metal lines  124  and vias  126 , and RDLs  136  are connected to form an integrated metal feature extending all the way from metal layer M 1  to RDL. 
     Combining  FIGS. 1 through 5 , it is observed that inductor  22  may include first portions (semi-turns, for example) that extends through a plurality of metal layers, which may be metal layers M 1  through the top layer of the RDLs. Metal bridges  22 A 3 , on the other hand, extends through the upper ones, but not into the lower ones, of the plurality of metal layers, while metal bridges  22 B 3  extends through the lower ones, but not into the upper ones, of the plurality of metal layers. As shown in  FIG. 1 , which illustrates metal bridge portions of inductor  22 , metal bridges  22 A 3  and  22 B 3  are physically separated from each other by a dividing layer (for example, via layer V 89 ), although different dividing layers such as via layers V 67  or V 56  may be used. Further, the dividing layer may include more than one via layer. For example, the dividing layer may include via layer V 78  and additional layers such as M 8 , and may include a plurality of layers such as via layer V 67  and V 78  and metal layer M 8 . 
     In  FIGS. 2 through 4 , semi-turns  22 A 1 ,  22 A 2 ,  22 B 1 , and  22 B 2 , and the respective ring-like structures ring 1 , ring 2 , and ring 3  are shown as having a square or a squares-like shape with breaks therein. In alternative embodiments, other shapes may be adopted by semi-turns  22 A 1 ,  22 A 2 ,  22 B 1 , and  22 B 2  to form ring-like structures, which shapes include, but are not limited to, circles, ellipses, and the like. Furthermore, each of inductors  22  may include a plurality of ring-like structures, such as two, four, five, or more, with the outer ring-like structures encircling/surrounding the inner ring-like structures. 
     Further through  FIGS. 1 through 5 , it is observed that if a trace is made to trace the metal connection from port  28 A to port  28 B ( FIG. 4 ), most portions (including semi-turns  22 A 1 ,  22 A 2 ,  22 B 1 , and  22 B 2 ) of the metal trace extend from metal layers M 1  all the way into redistribution layer RDLs. Accordingly, the resistances of these portions of inductor  22  are very low. The metal bridge portions  22 A 3  and  22 B 3  have the thicknesses close to a half of the thicknesses of the semi-turn portions, and hence the respective resistances are also low. Furthermore, evenly dividing upper portion  22 A and the lower portion  22 B of inductor  22  in thickness help make the resistances of metal bridges  22 A 3  and  22 B 3  more uniform. As a result, the Q value of inductor  22  may be improved, and the k value of the respective transformer (not shown in  FIGS. 1 through 5 , please refer to  FIG. 6 ) comprising inductor  22  is also improved. 
       FIG. 6  illustrates the two portions of transmitter  222  formed in chips  100  and  200 . Inductor  22 , which is in chip  100  and forms a portion of transformer  222 , is essentially the same as shown in  FIGS. 1 through 5 . In chip  200 , inductor  23  is formed, and may also have essentially the same structure as shown in  FIGS. 1 through 5 . Chips  100  and  200  may be stacked to each other through bonding, gluing, or other methods. Inductors  22  and  23  in combination form transmitter  222 , wherein signals may be coupled between inductors  22  and  23 . In an embodiment, the semi-turns in inductor  22  may vertically overlap the semi-turns (not shown) in inductor  23  after chips  100  and  200  are bonded. 
     The transformers formed according to embodiments have improved k values. Compared to conventional transformers formed in only metal layers M 8  and M 9  of chips, the k values of the transformers in accordance with embodiments may be as high as about 0.77, which is about 15 percent improvement over the k values 0.67 of conventional transformers. In experiments, the embodiments were used to form dynamic random access memory (DRAM) transceivers and graphic processing unit (GPU) transceivers, with inductor(s)  22  in  FIG. 6  forming the transceivers of the DRAM, and inductor(s)  23  forming the transceivers of the GPU. The experiment results indicated that the total power consumptions of 1024 transceivers may be reduced to about 7 watts from 8 watts consumed by transceivers adopting conventional structures. 
     In accordance with embodiments, a device includes a first plurality of dielectric layers over a substrate and a second plurality of dielectric layers over the first plurality of dielectric layers. A metal inductor includes a first metal portion, a second metal portion, a third metal portion, and a fourth metal portion, wherein each of the first, the second, the third, and the fourth metal portions extends into the first and the second plurality of dielectric layers. A first metal bridge connects the first metal portion to the second metal portion, wherein the first metal bridge extends into the first plurality of dielectric layers and not into the second plurality of dielectric layers. A second metal bridge connects the third metal portion to the fourth metal portion, wherein the second metal bridge extends into the second plurality of dielectric layers and not into the first plurality of dielectric layers. 
     In accordance with other embodiments, a device includes a plurality of metal layers over a substrate, wherein the plurality of metal layers is formed of a first metallic material including copper; and at least one redistribution metal layer over the plurality of metal layers. The at least one redistribution metal layer is formed of a second metallic material including aluminum. A metal inductor includes a plurality of semi-turns forming ring-like structures, with outer ones of the ring-like structures encircling inner ones of the ring-like structures. Each of the plurality of semi-turns extends into each of the plurality of metal layers and the at least one redistribution metal layer. The metal inductor further includes a first plurality of metal bridges, each connecting two of the plurality of semi-turns in different one of the ring-like structures. Each of the first plurality of metal bridges extends into lower ones of the plurality of metal layers, and not into the at least one redistribution metal layer. The metal inductor further includes a second plurality of metal bridges, each connecting additional two of the plurality of semi-turns in different ring-like structures. Each of the second plurality of metal bridges extends into a top one of the plurality of metal layers and the at least one redistribution metal layer, and not into the lower ones of the plurality of metal layers. 
     In accordance with yet other embodiments, a device includes a first chip including a plurality of metal layers over a substrate. The plurality of metal layers is formed of a first metallic material including copper, and includes a bottom metal layer, a top metal layer, and metal layers between the bottom metal layer and the top metal layer. A first metal inductor is formed in the first chip and includes a top inductor layer not lower than the top metal layer, and a bottom inductor layer in the bottom metal layer. The first metal inductor includes a portion in each of the plurality of metal layers. The metal inductor further includes a first plurality of metal bridges, each extending into the bottom metal layer, and a second plurality of metal bridges over the first plurality of metal bridges. Each of the second plurality of metal bridges includes a portion level with the top inductor layer. A second chip is bonded to the first chip, with a second metal inductor formed in the second chip. The first and the second metal inductors overlap each other. 
     Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.