Patent Publication Number: US-2023164006-A1

Title: Horizontal centering of sampling point using multiple vertical voltage measurements

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 17/224,985, filed Apr. 7, 2021, entitled “HORIZONTAL CENTERING OF SAMPLING POINT USING MULTIPLE VERTICAL VOLTAGE MEASUREMENTS”, naming Ali Hormati, which is hereby incorporated herein by reference in its entirety for all purposes. 
    
    
     REFERENCES 
     The following prior applications are herein incorporated by reference in their entirety for all purposes:
     U.S. Pat. No. 9,100,232, filed Feb. 2, 2105 as application Ser. No. 14/612,241 and issued Aug. 4, 2015, naming Amin Shokrollahi, Ali Hormati, and Roger Ulrich, entitled “Method and Apparatus for Low Power Chip-to-Chip Communications with Constrained ISI Ratio”, hereinafter identified as [Shokrollahi].   U.S. Pat. No. 10,193,716, filed Apr. 28, 2017, as application Ser. No. 15/582,545 and granted Jan. 29, 2019, naming Ali Hormati and Richard Simpson, entitled “Clock Data Recovery Utilizing Decision Feedback Equalization”, hereinafter identified as [Hormati I].   U.S. Pat. No. 10,848,351, filed Feb. 25, 2020, as application Ser. No. 16/800,892 and granted Nov. 24, 2020, naming Ali Hormati, entitled “Sampler Offset Calibration during Operation”, hereinafter identified as [Hormati II].   U.S. Pat. No. 10,904,046, filed Mar. 27, 2020 as application Ser. No. 16/833,362 and granted Jan. 26, 2021, naming Ali Hormati, entitled “Variable Gain Amplifier and Sampler Offset Calibration without Clock Recovery”, hereinafter identified as [Hormati III].   

     BACKGROUND 
     In modern digital systems, digital information has to be processed in a reliable and efficient way. In this context, digital information is to be understood as information available in discrete, i.e., discontinuous values. Bits, collection of bits, but also numbers from a finite set can be used to represent digital information. 
     In most chip-to-chip, or device-to-device communication systems, communication takes place over a plurality of wires to increase the aggregate bandwidth. A single or pair of these wires may be referred to as a channel or link and multiple channels create a communication bus between the electronic components. At the physical circuitry level, in chip-to-chip communication systems, buses are typically made of electrical conductors in the package between chips and motherboards, on printed circuit boards (“PCBs”) boards or in cables and connectors between PCBs. In high frequency applications, microstrip or stripline PCB traces may be used. 
     Common methods for transmitting signals over bus wires include single-ended and differential signaling methods. In applications requiring high speed communications, those methods can be further optimized in terms of power consumption and pin-efficiency, especially in high-speed communications. More recently, vector signaling methods such as described in [Shokrollahi] have been proposed to further optimize the trade-offs between power consumption, pin efficiency and noise robustness of chip-to-chip communication systems. In those vector signaling systems, digital information at the transmitter is transformed into a different representation space in the form of a vector codeword that is chosen in order to optimize the power consumption, pin-efficiency and speed trade-offs based on the transmission channel properties and communication system design constraints. Herein, this process is referred to as “encoding”. The encoded codeword is communicated as a group of signals from the transmitter to one or more receivers. At a receiver, the received signals corresponding to the codeword are transformed back into the original digital information representation space. Herein, this process is referred to as “decoding”. 
     Regardless of the encoding method used, the received signals presented to the receiving device are sampled (or their signal value otherwise recorded) at intervals best representing the original transmitted values, regardless of transmission channel delays, interference, and noise. This Clock and Data Recovery (CDR) not only must determine the appropriate sample timing, but must continue to do so continuously, providing dynamic compensation for varying signal propagation conditions. It is common for communications receivers to extract a receive clock signal from the received data stream. Some communications protocols facilitate such Clock Data Recovery or CDR operation by constraining the communications signaling so as to distinguish between clock-related and data-related signal components. Similarly, some communications receivers process the received signals beyond the minimum necessary to detect data, so as to provide the additional information to facilitate clock recovery. As one example, a so-called double-baud-rate receive sampler may measure received signal levels at twice the expected data reception rate, to allow independent detection of the received signal level corresponding to the data component, and the chronologically offset received signal transition related to the signal clock component. 
     However, the introduction of extraneous communications protocol transitions is known to limit achievable data communication rate. Similarly, receive sampling at higher than transmitted data rate is known to substantially increase receiver power utilization. 
     Real-world communications channels are imperfect, degrading transmitted signals in both amplitude (e.g. attenuation) and timing (e.g. delay and pulse smearing) which may be addressed via transmitter pre-compensation and/or receive equalization. Continuous time linear equalization (CTLE) is one known approach to frequency domain equalization, in one example providing compensation for increased channel attenuation at high frequencies. Time-domain-oriented equalization methods are also used to compensate for the effects of inter-symbol-interference or ISI on the received signal. Such ISI is caused by the residual electrical effects of a previously transmitted signal persisting in the communications transmission medium, so as to affect the amplitude or timing of the current symbol interval. As one example, a transmission line medium having one or more impedance anomalies may introduce signal reflections. Thus, a transmitted signal will propagate over the medium and be partially reflected by one or more such anomalies, with such reflections appearing at the receiver at a later time in superposition with signals propagating directly. 
     One method of data-dependent receive equalization is Decision Feedback Equalization or DFE. Here, the time-domain oriented equalization is performed by maintaining a history of previously-received data values at the receiver, which are processed by a transmission line model to predict the expected influence that each of the historical data values would have on the present receive signal. Such a transmission line model may be pre-calculated, derived by measurement, or generated heuristically, and may encompass the effects of one or more than one previous data interval. The predicted influence of these one or more previous data intervals is collectively called the DFE compensation. At low to moderate data rates, the DFE compensation may be calculated in time to be applied before the next data sample is detected, as example by being explicitly subtracted from the received data signal prior to receive sampling, or implicitly subtracted by modifying the reference level to which the received data signal is compared in the receive data sampler or comparator. However, at higher data rates the detection of previous data bits and computation of the DFE compensation may not be complete in time for the next data sample, requiring use of so-called “unrolled” DFE computations performed on speculative or potential data values rather than known previous data values. As one example, an unrolled DFE stage may predict two different compensation values depending on whether the determining data bit will resolve to a one or a zero, with the receive detector performing sampling or slicing operations based on each of those predictions, the multiple results being maintained until the DFE decision is resolved. 
     BRIEF DESCRIPTION 
     A digital receiver system samples received signals in both amplitude and time, obtaining sufficient information to permit accurate detection and decoding of the transmitted data regardless of signal degradations induced by the communications medium. Addressing the particular characteristics of the communications medium may require signal amplification, frequency- and time-domain filtering, as well as accurate adjustment of both the time and amplitude at which sampling occurs. 
     Accurate setting of data sampler timing to maximize receive data integrity requires accurate measurement of the overall receive eye opening. However, in some system embodiments a determination of the overall extent of the eye opening may not be made directly, due to limitations in the adjustment range of sampler timing, threshold, or both. 
     A method is described for indirect measurement of eye extent, including the steps of sampling a data stream at a locked sampling point using data samplers having vertical decision thresholds associated with speculative decision feedback equalization (DFE) terms to detect a predetermined transitional data pattern, varying a sampling offset and a vertical threshold of a spare sampler to measure a signal amplitude trajectory of a pattern-verified signal according to detection of the predetermined transitional data pattern, and adjusting the locked sampling point based on the measured signal amplitude trajectory by adjusting the speculative DFE terms. 
    
    
     
       BRIEF DESCRIPTION OF FIGURES 
         FIG.  1    is a block diagram of a receiver, in accordance with some embodiments. 
         FIGS.  2 A and  2 B  shows an example receive signal as an eye diagram. 
         FIGS.  3 A and  3 B  show measurements of eye opening. 
         FIG.  4    is a flowchart of a method  400 , in accordance with some embodiments. 
         FIG.  5    is a block diagram of a receiver clock system, in accordance with some embodiments. 
         FIG.  6    is a block diagram of a measurement controller, in accordance with some embodiments 
     
    
    
     DETAILED DESCRIPTION 
     In recent years, the signaling rate of high-speed communications systems have reached speeds of tens of gigabits per second, with individual data unit intervals measured in picoseconds. One example of such a system is given by [Shokrollahi], which describes use of vector signaling codes over extremely high bandwidth multiwire data communications links, such as between two integrated circuit devices in a system. Depending on the particular coding scheme used, the number of channels comprising such a communications link may range from two to eight or more, and may also communicate one or more clock signals, either within data channels or on separate communications channels. 
     In one embodiment utilizing a vector signaling code, multiple bits of data are encoded at the transmitter into a vector signaling “codeword”, i.e. a set of symbols to be transmitted essentially simultaneously over the multiple wires or channels of the communication medium. As each such wire or channel may take on more than two possible values, each symbol of the codeword is drawn from an alphabet of allowable signal values; in examples of [Shokrollahi], alphabets of four and ten values are used in encodings of five data bits into six symbol codewords. In the receiver, the multilevel wire signals are detected to determine the received codeword, which is then decoded (e.g. by a mapping table lookup) into received data. 
     In an alternative embodiment, it is noted that each vector signaling codeword is a superposition of “subchannel” components, each such subchannel being an orthogonal mode or pattern of modulation of the wires or channels. Thus, in the example of [Shokrollahi], five subchannels may be summed to produce the transmitted signals, each subchannel modulated by one of the five transmitted data bits. Similarly, a vector signaling code receiver may directly detect the combination of received wire signals corresponding to a particular subchannel, as one example by using a multi-input comparator (MIC) performing a weighted summation of two or more wire signals correlated with the orthogonal mode of that subchannel, and directly producing one bit of received data. In the example of [Shokrollahi], full decoding of five data bits is shown using a set of MICs combining from two to six wire signals. As codeword and subchannel processing models are fully equivalent, interoperation is assured regardless of the particular encoding and decoding model used, e.g. allowing combination of a codeword transmitter with a MIC-based subchannel receiver based on the same orthogonal vector signaling code. 
     As previously mentioned, wire signals in an orthogonal vector signaling code system may take on multiple distinct values, while detected subchannel results (as one example, the results of weighted summation as at the output of a MIC) are typically binary, thus receive processing functions such as ISI reduction and skew correction may be performed more efficiently on the simpler subchannel signals rather than on the more complex wire signals. 
     Conventional practice for a high-speed integrated circuit receiver terminates each received signal channel, subchannel, or wire signal in a signal detector. This signal detector performs a measurement constrained in both time and amplitude dimensions; in one example embodiment, it may be composed of a sample-and-hold circuit that constrains the time interval being measured, followed by a threshold detector or digital comparator that determines whether the signal within that interval falls above or below (or in some embodiments, within bounds set by) a reference value. Alternatively, a digital comparator may determine the signal amplitude followed by a clocked digital flip-flop capturing the result at a selected time. In other embodiments, a combined time- and amplitude-detection circuit is used, measuring the amplitude state of its input in response to the specified timing of a clock transition. 
     For descriptive convenience, this document will use the term sampling device, or more simply “sampler” to describe the receiver component that obtains an input measurement, as it implies both the time and amplitude measurement constraints, rather than the equivalent but less descriptive term “slicer” also used in the art. Similarly, the sampler input will simply be described as the “received signal”, whether it is derived from a wire signal, a MIC subchannel output, or other received information value. No limitation is implied by these descriptive conveniences, with all embodiments described herein being applicable to all signal sources and encodings. 
     In some embodiments, the time at which a sample is captured may be adjusted in some or all of the receiver samplers; in some embodiments, the threshold level to which a sample is compared may be adjusted in some or all of the receiver samplers. As one example, the well-known receiver “eye plot” diagram is typically obtained by iterative adjustment of these parameters, with the results plotted graphically as signal amplitudes over time. 
     Clock Data Recovery 
     Clock Data Recovery or Clock Data Alignment (CDR or CDA) circuits as in [Hormati I] extract timing information, either from the received signal(s) themselves or from dedicated clock signal inputs, and utilizing that extracted information to generate clock signals to control the time interval used by received signal sampling device. The actual clock extraction may be performed using well known circuits such as a Phase Locked Loop (PLL) or Delay Locked Loop (DLL), which in their operation may also generate higher frequency internal clocks, multiple clock phases, etc. in support of receiver operation. Implementation distinctions between CDR and CDA embodiments as described in the art are irrelevant to the present descriptions, thus the term CDA will subsequently be used herein as a generic identifier, without implying limitation. 
     In one common CDA embodiment, a first sample time is configured to optimally obtain the data sample, and a second sample time is configured to optimally determine whether the phase of the internal clock remains aligned with incoming signal transitions, which may be as much as ½ of a received signal unit interval (UI) offset in time from the optimum data sampling time. As sampling in such embodiments occurs twice per received unit interval, such systems are described as utilizing a double baud rate CDA. Such systems are very common in low speed communications system or where the received signal exhibits very sharp transitions, i.e. where there is significant displacement in time between observation of a signal transition and optimum sampling of data. 
     So-called single baud rate CDA embodiments are also known, in which the same sample time is used to obtain the data sample, and to determine whether the phase of the internal clock remains aligned with incoming signal transitions. In one such embodiment, inter-symbol interference (ISI) within the transmission medium, combined with group delay within the receive input processing, can result in detectable signal transitions which can inform CDA alignment at one sampling amplitude, while simultaneously detecting a stable data value at a second sampling amplitude. 
     CDA embodiments produce a single or primary sampling clock that provides a phase-locked sampling point for one or more data samplers. In some embodiments, the CDA generates early and late measurements and responsively adjusts the sampling instant to find a locked sampling instant representative of a desired ratio of early and late measurements. A CDA embodiment may also produce secondary clocks having predetermined phase relationships to the primary clock, as one example having ninety degree or quadrature offsets. In some embodiments, two such clocks may be input to phase interpolation (PI) circuits, allowing creation of additional phase-locked sampling points having a configurable phase relationship to the primary sampling clock and its associated data samplers. 
     Receive Signal Equalization 
     At high data rates, even relatively short and high-quality communications channels exhibit considerable frequency-dependent signal loss, thus it is common for data receivers to incorporate receive signal equalization. Continuous-time Linear Equalization (CTLE) is commonly used to provide increased high frequency gain in the receive signal path, in compensation for the increased high frequency attenuation of the channel. 
     It has also become common practice for data communications receivers to incorporate Decision Feedback Equalization (DFE) to compensate for signal propagation anomalies in the communications medium, including ISI. The DFE system performs non-linear time-domain equalization on the received signal by maintaining a history of previously-received data values at the receiver, and processing those historic data values with a transmission line model to predict the expected influence each of the historical data values would have on the present receive signal. Such a transmission line model may be pre-calculated, derived by measurement, or generated heuristically, and may encompass the effects of one or more than one previous data interval. 
     In a typical receiver design, this computed DFE compensation value will be subtracted from the current receive signal input to produce a corrected signal more accurately representing the received data value. Those familiar with the art will recognize that the DFE compensation value produced as described above cannot be calculated until the previous unit interval&#39;s data value has been detected. Thus, as data rates increase, a point will be reached at which the information to produce the DFE compensation value is not available in time to be applied to the next unit interval sampling. Indeed, at the highest data rates currently used in practice, this situation may exist for multiple previous unit intervals, as the detection time for a single data value may represent multiple unit interval durations, requiring the receiver to pipeline or parallelize the detection operation. Thus, it is common for embodiments to forgo such “closed loop” DFE methods for one or more of the most recent unit intervals, instead relying on an “open loop” or “unrolled loop” generation of one or more elements of the DFE compensation value for these most recent unit intervals. 
     In an effort to accelerate such DFE operation, some embodiments speculatively produce DFE compensation values corresponding to each of the possible detected data values for a given unit interval. One embodiment incorporates multiple data detection samplers, each provided with a distinct value of DFE compensation associated with the possible detected data values for one or more previous unit intervals. The result of each sampler is stored until the previous data value is known, at which time the corresponding stored result is selected for data detection. 
     The set of DFE compensation values speculatively created to represent the constellation of potential detected data results over the previous transmit unit interval or intervals represent a set of measurement levels spanning some portion of the receive signal amplitude range. As an example, previous transmission of consecutive “zero” signals might lead to a predicted lower threshold level for a subsequent receiver data measurement incorporating speculative DFE compensation, while previous transmission of consecutive “one” signals might lead to a predicted higher threshold level for the same data measurement. Thus, for any data measurement used to detect an actual data value, the described multiple-sampler receiver will potentially perform measurement operations using thresholds either too high or too low for the actual signal during that interval. 
     CDA Combined with DFE 
     In high speed communications systems operating over channels with significant frequency-dependent attenuation, received signals often have significantly sloped rise and fall times, even after receive signal equalization. Thus, a signal sampler timed to trigger at “center of eye” may under some circumstances still intersect with a signal transition still transitioning from one data value to the next, especially if that received signal is significantly perturbed by ISI. One such example may be seen in  FIG.  2 B , where the sampling point marked by “+” intersects with the signal trajectory identified as [0,1,1]. A receiver incorporating DFE will compensate for this behavior by having its effective data sampling threshold adjusted to be further away from the signal trajectory, while a fixed-threshold sampler (i.e. one not obtaining the benefit of DFE) might detect an incorrect value. 
     In such environments, it is possible to utilize a single sample time per received unit interval to determine both data value and clock phase. These baud-rate CDA embodiments rely on the observation that certain combinations of received ISI and detection sampling threshold have sub-optimal data sampling characteristics; that is, they have a high probability of intersecting with a changing input signal having a slow rise and fall time. Thus, by controlling the receive equalization to constrain transition rates, and then restricting observation of clock timing to only those sampling thresholds and received data patterns (which correlate to particular ISI levels) that provide such intersections, a single sampling time may be utilized for both clock and data sampling. 
     One embodiment described in [Hormati I] takes advantage of this effect to utilize measurement operations from multiple samplers or comparators performing speculative DFE operations. In that embodiment, a stored speculative result not used for determining the received data value (that is, measured at a signal offset above or below the appropriate DFE correction for that interval, but at the same time as the valid data sample) provides information relating to clock recovery. 
     Example Embodiment 
     For purposes of description and without implying limitation, a serial data receiver as shown in  FIG.  1    will be used as an example. This example receiver includes at least one stage of speculative DFE  150  supported by a first phase  120  of data samplers  121 / 122  performing concurrent time-sampling operations at two different amplitude thresholds, and a receiver clock system  170  to produce a sampling clock, the phase of which may be adjusted by a CDR correction to optimize data sampling timing. As shown, the data samplers  121  and  122  have vertical decision thresholds that are determined in part by speculative DFE terms provided by DFE circuit  150 . The data samplers generate outputs by slicing the data signal received from CTLE  110  according to their respective vertical decision thresholds and sampling the decision according to the sampling clock. Before sampling, the received data signal may be amplified and/or equalized by CTLE  110 . In some embodiments, the receiver system of  FIG.  1    may include additional processing phases similar to that of  120 , however for simplicity only one is shown. Additionally,  FIG.  1    includes data history  140  which may be, for example, a shift register-type buffer, and a pattern detection circuit  155  configured to detect one or more predetermined transitional data patterns. 
       FIG.  5    is a block diagram of one receiver clock system  170 , in accordance with some embodiments. As shown, early-late votes selected by multiplexer  160  are accumulated in a least-significant bit (LSB) portion of a multi-bit register  505 . The value of the CDR sample selected via multiplexor  160  may be combined with the data pattern identified by pattern detection circuit  155  to generate an early-late vote. Each early-late votes may adjust the value of the multi-bit register  505  in directions as determined by the value of the early-late vote, or provide no change if there is no valid early-late vote for a given signaling interval. For example, an early-late vote having a value associated with “early” may increment the LSB while early-late votes having values associated with “late” may decrement the LSB, or vice-versa depending on the implementation. Each CDR sample may be validated by the pattern detection circuit  155  to determine that the CDR sample was taken during a valid transitional data pattern, thus qualifying the early-late vote generated by E/L logic as a valid early-late vote. In some embodiments, pattern detection circuit  155  may provide an enable signal to the receiver clock system  170  to enable updating of the LSB of multi-bit register  505 . The multi-bit register  505  further includes a most-significant bit (MSB) portion (bolded) that may correspond to a multi-bit digital control signal for the local oscillator  515 . As shown, the MSB portion is separated from the LSB portion by a number of positions to provide filtering. Furthermore,  FIG.  5    includes a digital-to-analog converter (DAC)  510  configured to convert the multi-bit digital control signals to e.g., analog oscillator element control signals. Such analog control signals may control e.g., the operating currents of cascaded transistor elements in a ring oscillator. Other implementations known to those of skill in the art may be used as well. Outputs of ring oscillator  515  may be provided to data samplers  121 / 122 , and additionally may be provided to one or more phase interpolators (not shown), one of which may be included in measurement controller  190  for generating a variable-phase adjusted clock for spare sampler  180 . The receiver clock system  170  shown in  FIG.  5    illustrates only one possible embodiment, and other alternative embodiments may be utilized as well. 
       FIG.  1    further includes a spare sampler  180  configured to provide additional measurement capability that is non-intrusive with respect to generation and processing of data and CDR samples gathered by data samplers  121  and  122 . While  FIG.  1    includes two spare samplers  180 , it should be noted that such an embodiment should not be considered as limiting, and spare samplers  180  might include a single spare sampler, or more than two spare samplers. In one such embodiment, one or more spare samplers  180  may be configured to gather eye scope data, using Amplitude threshold(s) and/or a variable-phase adjusted clock. Such a variable-phase adjusted clock may be generated using e.g., a phase interpolator within measurement controller  190  that is configurable to receive phase(s) of the sampling clock from receiver clock system  170  and to generate a variable-phase adjusted clock that moves horizontally around the sampling interval. Alternatively, spare samplers may be configured to receive the sampling clock provided to data samplers  121 / 122  that corresponds to the center-of-eye sampling instant. A clock selection circuit (not shown) may be used to select between two such clocks. Measurement controller  190  may be further configured to adjust a vertical threshold of the spare sampler. As will be described in more detail below, such adjustments may be made to perform non-intrusive measurements of signal amplitude trajectory of a pattern-verified signal to adjust the locked sampling point of the data samplers  121 / 122 . 
       FIG.  2 A  is an example of a typical receive signal “eye”, produced by a time-overlay of the receive signal over multiple unit intervals. Thus, each individual line comprising the eye represents the receive signal “trajectory”, as it spans two or more unit intervals. 
     In  FIG.  2 B , subsets of signal trajectories comprising the eye of  FIG.  2 A  are labeled using a triplet notation of [previous data value, current data value, subsequent data value]. For descriptive convenience, this notation may be extended to incorporate additional previous and/or subsequent unit intervals, collectively described as the transitional data pattern associated with a particular measurement or action. 
     As would be expected, the [1, 1, 1] trajectories in  FIG.  2 B  are clustered along the top of the graph, the [1, 1, 0] trajectories transition downward at the right of the graph, [0, 0, 1] transition upward at the right of the graph, etc. Trajectories corresponding to a previous received data value of “1” (thus, optimally detected by the upper DFE sampling location) are shown as bold lines, while those trajectories corresponding to a previous received data value of “0” (and thus optimally detected by the lower DFE sampling location) are shown as pale lines. 
     The upper DFE sampler location selected by a DFE system to detect the current data value if the previous data value was “1” is shown with the black symbol + labeled “+VH1”. It may be noted that this sampler location is well positioned in the center of the upper data eye, but also is directly over the trajectory of a [0,1,1] received signal (the current data value of which will be detected by the lower sampler location, as determined by the previous data value of “0”.) Thus, the sampler having the decision threshold set to “−VH1” (indicated by the white + symbol), effectively corresponds to an edge sample that may be utilized by the CDR system to determine whether the sampler timing is early or late relative to that signal transition. Use of sampler outputs as early-late indications causes the sampling clock to have a lock point associated with the DFE correction factors ±VH1, as the CDR will adjust the phase of the sampling clock until the early-late indications selected from the data samplers responsive to the transition data patterns are approximately a 1:1 ratio. 
     Dynamic Data Sampler Decision Threshold Adjustment 
     As previously mentioned, reliable and error-free detection of received data signals may include accurate adjustment of a data sampler threshold at a predetermined time and amplitude position within the receive signal “eye”. Drift of that predetermined sampler vs. signal relationship over time, temperature, or supply voltage can lead to an increased receive bit error rate, and ultimately detection failure. 
     One known solution calibrates and adjusts a spare sampler offline (i.e. in a nonintrusive manner) and then exchanges that preconfigured unit with the active data sampler, freeing it to be calibrated and adjusted. In such a system, switching circuitry must be provided to all signals entering, controlling, and output by the samplers so that they may be directed as required to either data path or calibration functions. 
     To avoid use of such switching circuitry, one embodiment performs measurements using a spare sampler operating outside of a data signal processing path, and then uses information obtained through such measurements to adjust operation of the data samplers operating in the data signal processing path in a nonintrusive manner, as described in [Hormati II]. As the spare sampler is not part of the active data signal processing path, threshold levels and clock timing may be adjusted without impacting received data, allowing identification of both the extremes of normal operation (i.e. the boundaries of the received “eye” opening). In some embodiments, such adjustments to the spare sampler are comparable to those used to obtain the statistical data required to plot an eye diagram, and thus that spare sampler may subsequently be referred to as an eye sampler hereinafter, without implying limitation. 
     Ideally, the locked sampling point for the data samplers is set to the mid-point of the maximum horizontal eye opening, which may correspond to a known signaling interval duration. (In embodiments using predictive or speculative DFE, as in these examples, the eye openings being measured are those associated with the anticipated data value detected by each sampler, e.g. the extent of a valid data “1” for the upper sampler or a valid data “0” for the lower sampler.) In one representative embodiment, this point is determined by first advancing then retarding the sample timing of a sampler (as one example, by adjusting a phase interpolator (PI) producing a secondary or phase-adjustable clock controlling the sample time of a spare sampler,) to determine the extent of the eye opening, then calculating the mid-point of those timing extremes. However, due to the unavoidable adjustment nonlinearities of an uncalibrated clock interpolator, simply averaging the two setting values is not sufficient. Thus, in the illustration of  FIG.  3 A , measurement of interval AC may be performed at a threshold level appropriate for the upper sampler, but the correct value for configuration of the clock interpolator to center B within that range is not easily determined without some means to linearize the incremental timing adjustments. In one such embodiment, a predetermined look-up table of PI setting values and their associated time offsets is used to linearize or normalize the PI setting values. Alternatively, equivalent correction may be obtained using a best-fit function whose parameters have been configured or adjusted so as to correspond to the actual PI behavior. Calibration of a phase interpolator to obtain such a correction table or function may require a lengthy series of measurements, which may be difficult to obtain in some environments, especially if the phase interpolator settings change with time, temperature, or other process variations. Functionality described above in regard to processing the data points shown in  FIG.  3 B  such as the best-fit functions and look-up tables may be implemented within processor  630  as described below and shown in  FIG.  6   , either in hardware or software embodiments. 
     Beyond the adjustment nonlinearity of the clock interpolator, in some embodiments sampler measurements at the left (e.g. “early”) edge of the eye may themselves be inaccurate, due to variations in sampler sensitivity due to the shorter time between the sampler being reset or initialized and when it is triggered. 
     In an alternative embodiment, the slope of the signal amplitude trajectory forming the left edge of the eye is measured, allowing first the effective eye edge at the desired vertical decision threshold, then the optimum sampling point of the data sampler to be determined computationally rather than by direct measurement. As shown in  FIG.  3 B , the vertical threshold voltage of e.g., a spare sampler configured to trigger at an initial data sampling time D is incrementally adjusted while gathering a statistically valid set of measurements associated with particular transitional data patterns, allowing e.g., the voltage difference AV′ from the decision threshold of the data sampler to be measured. In one embodiment in accordance with the teachings of [Hormati II], this measurement is performed by repeated sampling at a given threshold value, discarding all measurements in which the captured result was not part of a predetermined transitional data pattern, e.g. the data sequence [0, 0, 1, 0], and determining that the result is a “1” if the ratio of sampled 1&#39;s to sampled 0&#39;s resulting from said measurements exceeds a predetermined threshold. In the example illustrated as  FIG.  3 B , the sampling offset for the sampler is adjusted downward from its original setting D after each measurement procedure, until the bounding amplitude trajectory of the eye being measured is found. In another embodiment, D represents the presumed or original locked data sampling point of a data sampler, in both threshold and timing, with any resulting correction obtained by these procedures representing an improvement in timing margin, amplitude margin, or both. As described above, results taken from the “other” data sampler (i.e., the results that do not correspond to the data decision as determined by resolution of the previous bit) are pattern-verified to generate phase-error signals, and thus the locked sampling point is tied to the value of the vertical decision thresholds of the data samplers. It may be further noted that the locked sampling point is determined in part by the speculative DFE factors provided to the data samplers  121 / 122 , and thus any changes in the speculative DFE factors provided to data samplers  121 / 122  will thus have an effect on moving the locked sampling point horizontally within the signaling interval. 
     For a one-stage speculative DFE as used in these examples, it may be noted that the first term of the DFE correction series H 1  corresponds to approximately ½ΔV 1  from the vertical center of the eye in this example. This implies that a spare pair of samplers such as  180  of  FIG.  1    may be used either simultaneously or sequentially to perform “1” and “0” measurements as described above, assuming that the individual sampler results are each qualified by the appropriate data sequences, i.e. [0, 0, 1, 0] for the upper sampler and [1, 1, 0, 1] for the lower sampler, by adjustment of the vertical decision thresholds applied to the spare samplers. One embodiment chooses a qualifying data pattern from the set [0, 0, 1, 1], [0, 0, 1, 0], [1, 1, 0, 1], [1, 1, 0, 0], [0, 1, 0, 1], [0, 1, 0, 1]. In some embodiments, the predetermined data patterns used to qualify measurements are triplet values, while in others quadruplet data patterns are used. Shorter or longer data patterns may be used in other embodiments. Similarly, an embodiment may be configured to detect a single data pattern and use it to qualify measurements, or may be configured to qualify a series of measurements against a multiplicity of data patterns. 
     The vertical threshold voltage and the phase interpolator (PI) control values of the spare sampler determining the timing of each measurement may be configured by a dedicated measurement controller or processor, as in  190  of  FIG.  1   . In various embodiments, this measurement controller/processor  190  may be implemented as a finite state machine controlled by hardware logic, a sequence of discrete commands executed by a programmable controller, or as a software program executing on an embedded or general-purpose processor. Thus, in various embodiments the configuration, information gathering, and analysis components these measurements may be performed using different combinations of on-chip hardware, embedded software, and host-based software resources, without limitation. 
     Given at least two measurements ΔV 1  and ΔV 2  with respect to the speculative H1 DFE term (or alternatively, finite voltage measurements) at corresponding distinct sampling offsets as in  FIG.  3 B , the slope of the left eye edge may be calculated using geometric principals, allowing the intercept point E (e.g., a ΔV=0 with respect to H1) to be predicted without the previously-described issues associated with directly measuring that extent. In this computation, each measured signal amplitude (typically recorded in absolute or relative units of DAC steps) and sampling offset (typically measured in units of PI setting steps) represents a two-dimensional point in eye diagram space, through which the statistically determined signal amplitude trajectory passes. In some embodiments, such a two-dimensional point may take the form of (x=horizontal offset, y=vertical offset). In some embodiments, the horizontal offset may correspond to an absolute timing offset from e.g., the locked sampling instant, or alternatively a PI code associated with known timing offsets. The vertical offset may correspond to differences between the speculative DFE decision threshold of the data samplers and the determined value of the variable decision threshold of the spare samplers (the ΔV 1  and ΔV 2  described above), or alternatively may correspond only to the determined value of the variable decision threshold. In some embodiments, the slope of the eye edge may be known to be fairly constant in the region of interest, allowing a simple linear or first-order extrapolation to be used to extend the predicted trajectory to intercept point E (dotted line of  FIGS.  3 A and  3 B .) In other embodiments, additional measurements may be made, allowing use of a second- or higher-order curve fitting function to extrapolate the three or more two-dimensional measurement points to the predicted intercept point (solid line of  FIG.  3 A ). In some embodiments, a verification is performed on the predicted intercept result, in one particular embodiment confirming that the predicted result is approximately ½ of a known signaling interval away from the current locked sampling point. 
     In some embodiments, the locked sampling point for the data samplers is adjusted to be approximately a half unit interval away from the left predicted intercept point at the desired vertical decision threshold. In another embodiment, a comparable measurement of two or more two-dimensional points followed by an extrapolation is used to find a rightmost predicted intercept point, and the locked sample point for the data samplers is adjusted to be half way between the leftmost and rightmost predicted intercept point at the desired vertical decision threshold. As described above, the locked sampling point may be moved horizontally throughout the signaling interval by means of adjusting the values of the speculative DFE decision thresholds provided to the data samplers. Based on the analysis of the predicted intercept point, the DFE circuit  150  may increase or decrease the magnitude of the H1 values provided to the data samplers, and the process may repeat until it is determined that the predicted intercept point is within a threshold of a known distance from the locked sampling point. 
       FIG.  4    is a flowchart of a method  400 , in accordance with some embodiments. As shown, method  400  includes sampling  402  a data stream at a locked sampling point using data samplers having vertical decision thresholds associated with speculative decision feedback equalization (DFE) terms to detect a predetermined transitional data pattern. The method further includes varying  404  a sampling offset and a vertical threshold of a spare sampler to measure a signal amplitude trajectory of a pattern-verified signal according to detection of the predetermined transitional data pattern. The method further includes adjusting  406  the locked sampling point  406  based on the measured signal amplitude trajectory by adjusting the speculative DFE terms+/−H1, as such an adjustment will automatically re-lock to a new sampling instant. 
     In some embodiments, measuring the signal amplitude trajectory of the pattern-verified signal comprises generating at least two signal amplitudes of the pattern-verified signal, each signal amplitude generated at respective sampling point. Two such points are shown in  FIG.  3 B , one of which is generated at the locked sampling instant ΔV1 from the vertical threshold of the data sampler, and the other of which is generated at a sampling instant offset from the locked sampling point that is ΔV2 from the vertical threshold of the data sampler. Each of these points may correspond to two dimensional points identified e.g., by a PI code associated with a horizontal offset and a voltage amplitude associated with a vertical offset. The voltage amplitude may correspond to the control setting of the vertical threshold of the spare sampler. As one particular embodiment offered without implying limitation, a vertical threshold of a sampler is varied at a first sampling time and at a second sampling time to measure a first and a second intersection with the signal trajectory for the predetermined transitional data pattern. The signal amplitude trajectory then may be measured based on the observation that it passes through the first and the second intersections, each corresponding to a measured vertical threshold and sampling instant offset. In some embodiments, measurement controller  190  operates on the first and second intersections to estimate a first order shape, e.g., a straight line. In more advanced embodiments, additional points may be gathered for estimating a second order or higher shape, such as a curved line that is more akin to a signal “eye” trace in a signaling interval. Two such signal shapes are illustrated in  FIG.  3 A , with the solid straight line corresponding to an exemplary first order shape and the dashed curved line corresponding to an exemplary second order shape. 
     The first and second intersections may be provided to measurement controller  190 , which may include a processor for estimating a horizontal offset (e.g., a PI code) that would be associated with a signal amplitude on the measured signal amplitude trajectory corresponding to one of the speculative DFE terms. In the pattern verified signal [1, 0, 0] of  FIG.  3 B , the processor may estimate a horizontal offset from the locked sampling instant associated with the +H1 speculative term. The measurement controller  190  subsequently determines whether or not this estimated horizontal offset is within a threshold of e.g., ½ of a known unit interval. In the scenario for which the horizontal offset is associated with a PI code, the controller may check the estimated PI code against a lookup table having PI codes with known timing offsets that may account for non-linearities in the PI. 
       FIG.  6    is a block diagram of a measurement controller  190 , in accordance with some embodiments. As shown, measurement controller  190  includes two multi-bit registers  605  and  610 . The least-significant bit (LSB) of each multi-bit register is incremented or decremented according to each pattern-verified early-late vote generated by spare samplers  180 . A most-significant bit (MSB) portion of each multi-bit register  605  and  610  may correspond to multi-bit digital control signals used to control the variable decision threshold for a corresponding spare sampler associated with the transitional data pattern. As  FIG.  6    includes two multi-bit registers, the variable decision threshold for at least two transitional data patterns may be maintained. Alternatively, each spare sampler may be operating at a different sampling instant from e.g., a variable-phase eye measurement clock generated e.g., by phase interpolator  615  operating on the sampling clocks received from the receiver clock system  170 . In such embodiments, multi-bit registers  605  and  610  may accumulate pattern-verified (e.g., using pattern detection logic  155 ) generated by spare samplers  180  and converted using logic (not shown) to pattern-verified early-late votes for the same transitional data pattern to measure signal amplitudes of a signal amplitude trajectory at two different sampling points. In some embodiments, the pattern-verified early-late votes are accumulated in the LSB, and enough changes in one direction or the other will influence the MSBs to adjust, thus adjusting the vertical decision threshold of the corresponding spare sampler. As shown, measurement controller  190  includes digital-to-analog converters (DACs)  620  and  625 , which may be configured to generate an analog voltage value for the slicing threshold of spare samplers  180  based on the multi-bit digital control signals stored in the MSBs of registers  605  and  610 . Once the spare sampler begins generating pattern-verified early-late votes at an approximate 50-50 ratio, then the measured signal amplitude at a given sampling offset and associated with the transitional data pattern may be provided to processor  630 . Processor  630  is configured to gather at least two data points as previously described that include a measured signal amplitude component and a corresponding sampling offset. The processor  630  is configured to measure the signal amplitude trajectory based on the at least two data points by estimating a first order (or higher) curve. Based on the signal amplitude trajectory, the intercept point E as shown in  FIG.  3 B  is estimated and analyzed to determine if the horizontal offset from the locked sampling instant to the offset associated with intercept point E is greater than or less than e.g., ½ of a known signaling interval duration. Processor  630  may output a control signal to DFE circuit  150  to adjust the speculative H1 DFE terms for the data samplers, which as described above will adjust the locked sampling instant. The previous measurements may then be made again until it is determined that the sampling instant is within a predetermined threshold of the ½ known signaling interval duration. In some embodiments, one or more of the components shown in the measurement controller  190  of  FIG.  6    such as but not limited to processor  630  may be included in other portions of the system of  FIG.  1   . Furthermore, measurement controller  190  may include additional components not shown in  FIG.  6   . 
     In some embodiments this adjustment is made by adjusting the speculative DFE term corresponding to the vertical sampling thresholds of one stage of unrolled or speculative DFE samplers. This adjustment influences the point on the signal trajectory captured for purposes of clock adjustment, moving the CDA lock phase. An alternative embodiment may adjust the sampling lock point phase directly, as with adjustment of a phase interpolator for the sampling clock.