Patent Publication Number: US-2016240464-A1

Title: Hybrid circuit board and method for making the same, and semiconductor package structure

Description:
FIELD 
     The subject matter herein generally relates to a package substrate structure. 
     BACKGROUND 
     In the field of integrated circuit (IC) substrate packages, the package structure generally includes a substrate and a semiconductor chip electrically connected to the substrate. However, the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the conventional substrate are different resulting in a warpage of the package structure and a low package yield rate. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Implementations of the present technology will now be described, by way of example only, with reference to the attached figures. 
         FIG. 1  is a cross sectional view of a hybrid circuit board according to the first embodiment of the present disclosure. 
         FIG. 2  is a cross sectional view of a hybrid circuit board according to the second embodiment of the present disclosure. 
         FIG. 3  is a cross sectional view of a semiconductor package structure according to the present disclosure. 
         FIG. 4A  to  FIG. 4F  are cross sectional views of a method of making a hybrid circuit board in  FIG. 1  according to the present disclosure. 
         FIG. 5A  to  FIG. 5C  are cross sectional views of a method of making a hybrid circuit board in  FIG. 2  based on the method of  FIG. 4  according to the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein may be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure. 
     The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like. 
       FIG. 1  illustrates a hybrid circuit board  100  including an insulated molding layer  10 , a solder mask layer  20 , a conductive patterned layer  30 , a plurality of conductive pillars  40 , and a supporting plate  50 . The insulated molding layer  10  includes a first surface  11  and a second surface  12  opposite to the first surface  11 . The solder mask layer  20  is formed on the first surface  11  of the insulated molding layer  10 . The conductive patterned layer  30  is formed on a first surface  11  of the insulated molding layer  10  and is embedded in the solder mask layer  20 . The thickness of the conductive patterned layer  30  is substantially equal to the thickness of the solder mask layer  20 . The plurality of conductive pillars  40  are embedded in the insulated molding layer  10 . Each of the conductive pillars  40  has a first end  41  electrically connected to the conductive patterned layer  30 , and a second end  42  which is opposite to the first end  41  and is exposed to the second surface  12  of the insulated molding layer  10 . The supporting plate  50  defines an opening  51  formed on the solder mask layer  20  and the conductive patterned layer  30  to partially expose the solder mask layer  20  and the conductive patterned layer  30 . The second end  42  for each of the conductive pillars  40  is flush with the second surface  12  of the insulated molding layer  10 , or is projecting from the second surface  12  of the insulated molding layer  10 . 
     The solder mask layer  20  is formed by using conventional soldering resist inks The insulated molding layer  10  can be made by epoxy resin or hybrid epoxy. In this embodiment, the insulated molding layer  10  is made by epoxy resin. The thermal expansion coefficient of the insulated molding layer  10  is in a range of 3 ppm/° C.-6 ppm/° C. The thermal expansion coefficient of the insulated molding layer  10  is equivalent to the thermal expansion coefficient of semiconductor chips, which have a thermal expansion coefficient around 3 ppm/° C.-4 ppm/° C. . Using the insulated molding layer  10  in the hybrid circuit board  100  can effectively reduce the warpage of the semiconductor package structure. The cost of the epoxy resin used in the insulated molding layer  10  is much cheaper than the cost of conventional copper clad laminates (CCL) or polypropylene (PP). 
     The conductive materials used in the conductive patterned layer  30  and the conductive pillars  40  can be the conventional conductive metals, including copper, tin, nickel, chromium, titanium, and combined metal alloy of above. Copper is used in the illustrated embodiment. 
     The supporting plate  50  has sufficient stiffness and strength to prevent bending deformation damage to the hybrid circuit board  100  during transportation making the hybrid circuit board  100  easy to transport. In the illustrated embodiment, the supporting plate  50  may be a polymer sheet covered with the copper layers. 
     The portions of the solder mask layer  20  and the conductive patterned layer  30 , corresponding to the opening  51  of the supporting plate  50 , are exposed and formed as a chip bonding region (not shown). 
       FIG. 2  illustrates a second embodiment of the hybrid circuit board  200 , which has an additional second solder mask layer  21  and a second conductive patterned layer  31  based on the structure of the hybrid circuit board  100 . The second conductive patterned layer  31  is formed on the second surface  12  of the insulated molding layer  10 , and the second solder mask layer  21  is formed on the second surface  12  of the insulated molding layer  10  and a portion of the second conductive patterned layer  31 . A partial surface of the second conductive patterned layer  31  is exposed to the second solder mask layer  21 . The second conductive patterned layer  31  is electrically connected with the second ends  42  of the conductive pillars  40 . 
       FIG. 3  illustrates a semiconductor package structure  300 , which includes the hybrid circuit board  200  and a semiconductor chip  60 . The semiconductor chip  60  is electrically connected with the conductive patterned layer  30  by solder  70 . In this embodiment, the semiconductor chip  60  can be a flip-chip or a wire-bond chip. 
     It is necessary to fill in underfills (not shown) when using a flip-chip at the junction between the hybrid circuit board  200  and the flip-chip  60 . The underfills can be wrapped around the solder  70  to protect the solder  70  and can be used to enhance the bonding force between the flip-chip  60  and the hybrid circuit board  200 . 
     In other embodiments, the hybrid circuit board  200  of the semiconductor package structure  300  can be replaced by the hybrid circuit board  100 . 
       FIG. 4A  to  FIG. 4F  illustrates a method of making the hybrid circuit board  100 . 
     Referring to  FIGS. 4A to 4F , a process flow is presented in accordance with an example embodiment. The example method shown in  FIGS. 4A to 4F  is provided by way of example, as there are a variety of ways to carry out the method. The method described below can be carried out using the configurations illustrated in  FIGS. 4A to 4F , for example, and various elements of these figures are referenced in explaining example method. Each of  FIGS. 4A to 4F  represents one or more processes, methods or subroutines, carried out in the example method. Furthermore, the illustrated order of  FIGS. 4A to 4F  is illustrative only and the order of  FIG. 4A to 4F  can change according to the present disclosure. Additional processes can be added or fewer processes may be utilized, without departing from this disclosure. 
       FIG. 4A  illustrates a supporting plate  50 , which has sufficient stiffness and strength for using as a carrier of the hybrid circuit board  100 . In this embodiment, the supporting plate  50  is a polymer sheet covered with the copper metal layers as shown in  FIG. 4A . 
       FIG. 4B  illustrates the supporting plate  50  in  FIG. 4A  to open a through hole  52  and to form a solder mask layer  20 . The solder mask layer  20  is formed on part of an end surface of the supporting plate  50 . The process details for forming the sold mask layer are described as below. Firstly, one end surface of the supporting plate  50  is fully coated with the photosensitive solder resist ink, and then the photosensitive solder resist ink is exposed and developed to remove part of the photosensitive solder resist ink, and finally, the solder mask layer  20  is formed on part of the surface of the supporting plate  50 . 
     Before coating the photosensitive solder resist ink, the supporting plate  50  can define a through hole  52 . The through hole  52  shown in  FIG. 4B  is an example for illustration only and is not an actual position. After the through hole  52  is defined, the supporting plate  50  is coated with the photosensitive solder resist ink. After coating the photosensitive solder resist ink, the photosensitive solder resist ink positioned on the supporting plate  50  is exposed and developed to form the solder mask layer  20  on part of an end surface of the supporting plate  50 . The light used for exposure can be an ultraviolet light. 
       FIG. 4C  illustrates a conductive patterned layer  30  to be formed on the supporting plate  50  shown in  FIG. 4B . The conductive patterned layer  30  is formed on the end surface of the supporting plate  50  with the solder mask layer  20 , in addition, the conductive patterned layer  30  is formed on the end surface of the supporting plate  50  without covering the solder mask layer  20 . 
     In the illustrated embodiment, the conductive patterned layer  30  can be formed by electro-plating. The conductive patterned layer  30  is embedded in the solder mask layer  20 . The thickness of the conductive patterned layer  30  is equivalent to the thickness of the solder mask layer  20  as shown in  FIG. 4C . The circuit pattern of the hybrid circuit board  100  can be well defined by the conductive patterned layer  30  and the solder mask layer  20  with a fine line circuit pattern. Therefore, the method of the present disclosure can be used to realize the preparation of the fine line circuit pattern. 
       FIG. 4D  and  FIG. 4E  illustrate a plurality of conductive pillars  40  to be formed on the surface of the conductive patterned layer  30  shown in  FIG. 4C . Each of the conductive pillars  40  has a first end  41  electrically connected with the conductive patterned layer  30 , and a second end  42  opposite to the first end  41 . 
       FIG. 4D  illustrates that a dry film layer  80  is formed on the surface of the supporting plate  50  with the solder mask layer  20  and the conductive patterned layers  30 , and another dry film layer  80  is formed on the surface of the supporting plate  50  away from the conductive patterned layer  30 . The dry film layer  80 , which is positioned on the surface of the supporting plate  50  with the solder mask layer  20  and the conductive patterned layer  30 , is exposed and is developed to remove a portion of the dry film layer  80 . After developing, the surface of the conductive patterned layer  30  is partially exposed. And then, a plurality of conductive pillars  40  are formed on the exposed surface of the conductive patterned layer  30 , and are electrically connected with the conductive patterned layer  30 . The method for making the conductive pillars  40  can be electroplating. And finally, the residual dry film layers  80  are removed and shown as  FIG. 4E . In the illustrated embodiment, the electroplating method used for forming the conductive pillars replaces the traditional mechanical drilling method. 
       FIG. 4F  illustrates an insulated molding layer  10  to be formed on the surface of the supporting plate  50  with the solder mask layer  20  and the conductive patterned layer  30  shown in  FIG. 4E . The conductive pillars  40  are embedded in the insulated molding layer  10 , and the second ends  42  of the conductive pillars  40  related to the insulated molding layer  10  are exposed. 
     To manufacture the insulated molding layer  10 , the supporting plate  50  with the conductive patterned layer  30  electrically connected with a plurality of conductive pillars shown in  FIG. 4E  is first placed into a mold (not shown), the molten resin is injected to the surface of the supporting plate  50  with the solder mask layer  20  and the conductive patterned layer  30 , to form the insulated molding layer  10  on the surface of the solder mask layer  20  and the conductive patterned layer  30 . A plurality of the conductive pillars  40  are embedded in the insulated molding layer  10  as shown in  FIG. 4F . After molding the insulated molding layer  10 , it can further include a polishing process for polishing the mold surface of the insulated molding layer  10 . After polishing, the second ends  42  of the conductive pillars  40  embedded in the insulated molding layer  10  are exposed. 
     Before manufacturing the insulated molding layer  10 , the conductive pillars  40  can be micro-etched to produce rough surfaces on the conductive pillars  40 . The rough surfaces of the conductive pillars  40  can enhance the bonding force between the conductive pillars  40  and the insulated molding layer  10 . 
     The method for making the hybrid circuit board  100  further comprises a process that the supporting plate  50  is partially etched to form an opening  51  which exposes the solder mask layer  20  and the conductive patterned layer  30 . As mentioned above, the partial etching process can use the dry film layer  80  for patterning to expose part of the supporting plate  50 , and then, the exposed part of the supporting plate  50  is etched by the conventional chemical solutions to define the opening  51 . The method for making a hybrid circuit board is easy to produce a thin hybrid circuit board, thereby reducing the overall thickness of the semiconductor package structure. 
     To produce a hybrid circuit board  200 , it needs to perform additional procedures based on the structure of  FIG. 4F .  FIG. 5A  to  FIG. 5C  illustrate the additional processes to form the second solder mask layer  21  and the second conductive patterned layer  31 . 
       FIG. 5A  illustrates a second conductive patterned layer  31  to be formed on the surface of the insulated molding layer  10  shown in  FIG. 4F  for electrical connection with the second ends  42  of the conductive pillars  40 . The second conductive patterned layer  31  is partially etched to remove a portion of the second conductive patterned layer  31  and expose a portion of the insulated molding layer  10 . The method of forming a second conductive patterned layer  31  can be selected from one of electro-plating, chemical deposition, or physical deposition. 
       FIG. 5B  illustrates a second solder mask layer  21  to be formed on part of the second conductive patterned layer  31  and the exposed insulated molding layer  10  shown in  FIG. 5A . The process details are described as follow. The exposed portion of the insulated molding layer  10  mentioned in  FIG. 5A  is coated with the photosensitive solder resist ink to form the second solder mask layer  21  after patterning. 
     The detailed method for partially etching the second conductive patterned layer  31  is described as below. The second conductive patterned layer  31  is fully covered with a dry film layer  80 . The surface of the supporting plate  50  away from the conductive patterned layer  30  is also covered with a dry film layer  80  for protection. Next, the dry film layer  80  positioned on the second conductive patterned layer  31  is exposed and developed to remove part of the dry film layer  80  and to expose a portion of the second conductive patterned layer  31 . The exposed portion of the second conductive patterned layer  31  is etched and removed. The etching method is a chemical etching by using the conventional etching solutions. 
     The method for making the hybrid circuit board  200  further comprises a process that the supporting plate  50  is partially etched to form an opening  51  which exposes the solder mask layer  20  and the conductive patterned layer  30  as shown in  FIG. 5C . As mentioned above, the partial etching process can use the dry film layer  80  for patterning to expose part of the supporting plate  50 , and then, the exposed part of the supporting plate  50  is etched by the conventional chemical solutions to define the opening  51 . 
     An organic solderability preservative (OSP) is used to cover the surface of the conductive patterned layer  30  of the hybrid circuit board  100 , or to cover the surfaces of the conductive patterned layer  30  and the second conductive patterned layer  31  of the hybrid circuit board  200 , to protect the surface of the conductive patterned layer  30  and/or the second conductive patterned layer  31 . In addition, a multi-metal layer of Ni/Pt/Au can be formed on the surface of the conductive patterned layer  30 , or formed on the surfaces of the conductive patterned layer  30  and the second conductive patterned layer  31 , to avoid the surface oxidation of the exposed portion of the conductive patterned layer  30  and the second conductive patterned layer  31 . 
     With the present disclosure, a hybrid circuit board for semiconductor package structures and materials are an optimized design, which can include the introduction of an insulated molding layer  10  in the package substrate structure, and the design of the materials by matching the thermal expansion coefficient of the insulated molding layer  10  and the thermal expansion coefficient of the semiconductor chips  60 . It is not only effective to reduce cost, but also effective to avoid warping of the package of the semiconductor package structure in the subsequent processes. In addition, the manufacturing method is simple to form a hybrid circuit board with a plurality of conductive pillars by using the electroplating process instead of the traditional mechanical drilling process, and achieve a fine line circuit pattern on a thinner hybrid circuit board, thereby reducing the overall thickness of the semiconductor package structure. 
     The embodiments shown and described above are only examples. Many details are often found in the art such as the other features of a hybrid circuit board. Therefore, many such details are neither shown nor described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, especially in matters of shape, size, and arrangement of the parts within the principles of the present disclosure, up to and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiments described above may be modified within the scope of the claims.