Patent Publication Number: US-7903746-B2

Title: Calibrating parameters in a storage subsystem with wide ports

Description:
BACKGROUND 
     1. Technical Field 
     The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to a method and procedure for detecting cable length in a storage subsystem with wide ports. 
     2. Description of Related Art 
     In storage network systems, high speed serial differential interfaces are used to interconnect multiple storage components. For example, in BladeCenter® products from IBM Corporation, a serially attached SCSI (SAS) switch may be used to interconnect the server blades to external storage, such as a typical storage enclosure. The server blades may be directly connected to the SAS switch via an internal high speed fabric. The SAS switch is connected to the external storage via external SAS cables. 
     Generally, multiple cable lengths are required for attaching storage at different distances from the SAS switch. The initial release of the first BladeCenter® storage product may require a “short” cable, such as three meters, and a “long” cable, such as eleven meters. Soon thereafter, the storage product may require longer cables, such as twenty meters. 
     As the high speed interfaces increase in data rate speed, it becomes necessary to selectively adjust the transmitter/receiver characteristics, such as pre-emphasis and de-emphasis. With significantly disparate cable lengths, it is difficult to optimize the high speed interface for both short and long cables. Therefore, it becomes necessary to determine the cable length attached to each port of the SAS switch. Furthermore, some scenarios may occur in which a short cable is inadvertently, or possibly deliberately, replaced with a long cable. 
     To accommodate the different cable lengths, created either by statically preplanned cabling procedures or by dynamically swapping cables in a customer location, it becomes necessary to dynamically determine cable lengths between a SAS switch and external storage. Several methods have been proposed and implemented in the prior art. For example, some fiber channel cables implement an embedded VPD (vital product data) circuit that includes cable length information. This has only been implemented with cables using small form factor pluggable (SFP) connections. Whether the cables are optical or copper, it remains that the necessary cable length information is implemented with some type of cable VPD, which is only accessible via some sort of out-of-band interface embedded within the high speed cable. 
     Furthermore, very recent SAS cabling technology employs the notion of a “wide” port. A wide port consists of multiple lanes or physical transceiver elements (PHYs). Today, SFPs are designed for a single port. It is quite impractical to provide a wide SFP for optical ports. For example, a four-wide port would require four laser transmitters and four receivers. Using a wide SFP for copper cabling would be more likely, but a significant cost adder would be required. It should be noted that SFPs, whether optical or copper, require an out-of-band interface, something that is heretofore not standardized or implemented. 
     A generally accepted bit error rate (BER) for high speed serial interfaces is 1×10 −12  (one error occurrence for every 10 12  bits that are transferred). Some things that can affect high speed signaling include impedance variation caused by unexpected electrical discontinuities along the transmission path, high speed driver/receiver circuit defects, improper mating contacts caused by bent or damaged connector pins, incomplete connector mating caused by mechanical or installation problems, and signal coupling between adjacent signal paths. Individual components are tested to a performance range, but tolerance buildup can cause attenuation beyond nominal design targets. Often, performance parameters are guaranteed by the manufacturing process controls and not 100% tested. Therefore, there is an exposure to maverick defects. 
     Ideally, all the above problems are tested and verified by interconnect and subsystem manufacturers. However, often this is not the case, and such defects are introduced into the final system integration process. All the low speed circuitry (&lt;1 GHz) can be adequately tested. The high speed circuitry must be carefully verified. A common technique is to wrap the high speed interfaces using a cable or wrap paths external to the subsystem; however, this does not cover the actual interface connections at the time of system integration. 
     As subsystem components are integrated into a system, the parametric variance from the nominal case may cause a communication failure across the high speed interface. Aggravating factors may include customer data pattern, printed circuit variations and parasitics, connector parasitics, cable length or cable discontinuities, and system environment. When a communication failure is detected, the system may try to retransmit the data or may employ error correction schemes. The price for transmission recovery may be realized in lost performance. Performance degradation may be measured in bit error rate (BER). 
     SUMMARY 
     In one illustrative embodiment, a computer program product comprises a non-transitory computer useable medium having a computer readable program. The computer readable program, when executed on a computing device, causes the computing device to set at least one transmitter parameter and at least one receiver parameter in the computing device and record error rate, adjust the at least one transmitter parameter and the at least one receiver parameter and record the error rate until the at least one transmitter parameter and the at least one receiver parameter are margined from a minimum to a maximum, and calibrate the at least one transmit parameter and the at least one receiver parameter. Adjusting the at least one transmitter parameter and the at least one receiver parameter comprises repeatedly adjusting the at least one transmitter parameter and the at least one receiver parameter for a next transmitter/receiver pair until the at least one transmitter parameter and the at least one receiver parameter for all transmitter/receiver pairs within the plurality of transmitter/receiver pairs are margined from a minimum to a maximum. 
     In another illustrative embodiment, a computing device comprises at least one transmitter/receiver pair and a processor. The processor is configured to set at least one transmitter parameter and at least one receiver parameter in the computing device and recording error rate, adjust the at least one transmitter parameter and the at least one receiver parameter and record the error rate until the at least one transmitter parameter and the at least one receiver parameter are margined from a minimum to a maximum, and calibrate the at least one transmit parameter and the at least one receiver parameter. Adjusting the at least one transmitter parameter and the at least one receiver parameter comprises repeatedly adjusting the at least one transmitter parameter and the at least one receiver parameter for a next transmitter/receiver pair until the at least one transmitter parameter and the at least one receiver parameter for all transmitter/receiver pairs within the plurality of transmitter/receiver pairs are margined from a mimum to a maximum. 
     In one illustrative embodiment, a method for point-to-point calibration in a computing device comprises setting at least one transmitter parameter and at least one receiver parameter in the computing device and recording error rate, adjusting the at least one transmitter parameter and the at least one receiver parameter and recording the error rate until the at least one transmitter parameter and the at least one receiver parameter are margined from a minimum to a maximum, and calibrating the at least one transmit parameter and the at least one receiver parameter. Adjusting the at least one transmitter parameter and the at least one receiver parameter comprises repeatedly adjusting the at least one transmitter parameter and the at least one receiver parameter for a next transmitter/receiver pair until the at least one transmitter parameter and the at least one receiver parameter for all transmitter/receiver pairs within the plurality of transmitter/receiver pairs are margined from a minimum to a maximum. 
     These and other features and advantages of the present invention will be described in, or will become apparent to those of ordinary skill in the art in view of, the following detailed description of the exemplary embodiments of the present invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention, as well as a preferred mode of use and further objectives and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein: 
         FIGS. 1A-1C  are block diagrams of a narrow port in a storage network in accordance with one illustrative embodiment; 
         FIGS. 2A-2C  are block diagrams of a wide port in a storage network in accordance with one illustrative embodiment; 
         FIG. 3  is a flowchart illustrating operation of a mechanism for detecting cable length in a storage subsystem with wide ports in accordance with an illustrative embodiment; 
         FIG. 4  is a block diagram illustrating an example system environment in which aspects of the illustrative embodiments may be implemented; 
         FIG. 5  is a block diagram illustrating a subsystem interface environment in which aspects of the illustrative embodiments may be implemented; 
         FIG. 6  is a block diagram that illustrates a high speed point-to-point calibration procedure in accordance with an illustrative embodiment; 
         FIG. 7  is a flowchart illustrating operation of a point-to-point calibration mechanism in accordance with an illustrative embodiment; and 
         FIG. 8  is a flowchart illustrating system calibration in accordance with an illustrative embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE ILLUSTRATIVE EMBODIMENTS 
     Referring to the figures,  FIGS. 1A-1C  are block diagrams of a narrow port in a storage network in accordance with one illustrative embodiment. More particularly with reference to  FIG. 1A , switch module  110  has processor  112  and switch application specific integrated circuit (ASIC)  114 . Switch ASIC  114  has physical transceiver element (PHY)  116 . A PHY includes a transmitter and receiver pair. End device  120  has processor  122  and end device ASIC  124 . End device ASIC  124  has PHY  126 . PHY  116  is connected to PHY  126  via an external cable for normal data transfer. In one exemplary embodiment, switch module  110  may be a serial attached SCSI (SAS) switch module and end device  120  may be a SAS end device. 
     With reference now to  FIG. 1B , PHY  116  in switch ASIC  114  and PHY  126  in end device ASIC  124  are configured for diagnostic internal loopback at each end. In accordance with the illustrative embodiment, PHY  116  and PHY  126  have the capability to connect the transmitter to the receiver to form an internal loopback.  FIG. 1B  illustrates how the SAS network is configured during diagnostic verification of the external interface. The SAS devices at each end of the cabled interface perform an internal wrap to test out the narrow port of each respective device. 
     Turning to  FIG. 1C , PHY  126  in end device ASIC  124  is configured for diagnostic loopback at the end device. PHY  126  has the capability to connect the transmitter to the receiver to form an external loopback.  FIG. 1C  illustrates a configuration that provides the basis for the cable length detection mechanism and procedure for a narrow port to be described in further detail below. 
       FIGS. 2A-2C  are block diagrams of a wide port in a storage network in accordance with one illustrative embodiment. More particularly with reference to  FIG. 2A , switch module  210  includes switch ASIC  220 , which has switch processor  222 , data processor  224 , switch  226 , and PHYs  0 -N  212 - 216 . Each PHY includes a transmitter and receiver pair. Data processor  224  comprises at least one of a cyclical redundancy check module, a pattern generator/check module, a data buffer, a packet controller, or a protocol controller. End device  230  includes end device ASIC  240 , which has target processor  242 , data processor  244 , switch  246 , and PHYs  0 -N  232 - 236 . PHYs  212 - 216  are connected to respective ones of PHYs  232 - 236  via a wide port external cable for normal data transfer. In one exemplary embodiment, switch module  210  may be a serial attached SCSI (SAS) switch module and end device  230  may be a SAS end device. 
     With reference now to  FIG. 2B , PHYs  212 - 216  in switch ASIC  220  and PHYs  232 - 236  in end device ASIC  240  are configured for diagnostic internal loopback at each end. In accordance with the illustrative embodiment, PHYs  212 - 216  and PHYs  232 - 236  have the capability to connect the transmitter to the receiver to form an internal loopback.  FIG. 2B  illustrates how the wide port SAS network is configured during diagnostic verification of the external interface. The SAS devices at each end of the cabled interface perform an internal wrap to test out the narrow port of each respective device. 
     Turning to  FIG. 2C , PHY  212  in switch ASIC  220  and PHY  232  in end device ASIC  240  are configured for normal data transfer. In the depicted example, PHY  0   212  is a command PHY. PHYs  1 -N  234 - 236  in end device ASIC  240  are configured for diagnostic loopback at the end device.  FIG. 2C  illustrates a configuration that provides the basis for the cable length detection mechanism and procedure for a wide port of the illustrative embodiments to be described in further detail below. 
     Those of ordinary skill in the art will appreciate that the hardware depicted in  FIGS. 1A-1C  and  FIGS. 2A-2C  may vary. For example, switch module  110  in  FIGS. 1A-1C  may include more than one narrow port, and switch module  210  in  FIGS. 2A-2C  may include more than one wide port. Other modifications to the storage area network configurations may be made within the spirit and scope of the present invention. The depicted examples are not meant to state or imply any architectural limitations with respect to the present invention. 
     In accordance with an illustrative embodiment, a mechanism and procedure are provided for detecting cable length in a storage subsystem with wide ports. The mechanism may use in-situ bidirectional cable wrapping for determining different cable lengths. Note that high speed differential interfaces generally implement transmitter and receiver circuits, also known as serializer/deserializer (SERDES) circuits, which allow for adjustment of the transmitter amplitude as well as receiver equalization. A mechanism and procedure for adjusting transmitter amplitude and receiver equalization will be described in further detail below with reference to  FIGS. 4-8 . During normal operation, it is desired to optimally tune these parameters to provide for the most robust system electrical performance. 
     To determine the length of any attached cables, a diagnostic procedure is defined that under-margins the transmitter output and detunes the receiver input to the point that the interface fails, for each external port and even for each PHY within a wide port. Based on the transition point from “successful” wrap to “failed” wrap, the cable length can be determined. This assumes that there are a fixed number of predetermined cable lengths, such as “long” cable and “short” cable. The transition point may identify the cable as long or short, at which point the optimum tuning parameters can accordingly be determined and programmed during normal operation. 
       FIG. 3  is a flowchart illustrating operation of a mechanism for detecting cable length in a storage subsystem with wide ports in accordance with an illustrative embodiment. It will be understood that each block of the flowchart illustrations, and combinations of blocks in the flowchart illustrations, can be implemented by computer program instructions. These computer program instructions may be provided to a processor or other programmable data processing apparatus to produce a machine, such that the instructions which execute on the processor or other programmable data processing apparatus create means for implementing the functions specified in the flowchart block or blocks. These computer program instructions may also be stored in a computer-readable memory or storage medium that can direct a processor or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory or storage medium produce an article of manufacture including instruction means which implement the functions specified in the flowchart block or blocks. 
     Accordingly, blocks of the flowchart illustrations support combinations of means for performing the specified functions, combinations of steps for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that each block of the flowchart illustrations, and combinations of blocks in the flowchart illustrations, can be implemented by special purpose hardware-based computer systems which perform the specified functions or steps, or by combinations of special purpose hardware and computer instructions. 
     Furthermore, the flowcharts are provided to demonstrate the operations performed within the illustrative embodiments. The flowcharts are not meant to state or imply limitations with regard to the specific operations or, more particularly, the order of the operations. The operations of the flowcharts may be modified to suit a particular implementation without departing from the spirit and scope of the present invention. 
     With reference now to  FIG. 3 , operation begins when the cable length connected to a wide port is unknown. The mechanism invokes the diagnostic cable wrap routine to configure the PHYs on each end for cable length detection (block  302 ). Then, the mechanism establishes a command PHY for communication across the wide port (block  304 ). 
     The mechanism wraps the next PHY in the wide port by configuring the PHY to connect the transmitter to the receiver to form an external loopback (block  306 ). The mechanism adjusts transmitter and receive parameters to minimum and records the error rate (block  308 ). The mechanism then adjusts transmitter and receiver parameters to a next step and records the error rate (block  310 ). The mechanism determines whether all adjustments are completed (block  312 ). If all adjustments are not completed, operation returns to block  310  to adjust transmitter and receiver parameters to a next step and record the error rate. 
     If all adjustments are completed for the PHY in block  312 , the mechanism determines whether the last PHY has been tested (block  314 ). If the last PHY has not been tested, operation returns to block  306  to wrap the next PHY in the wide port. 
     If, however, the last PHY has been tested in block  314 , the mechanism compares the recorded data for each PHY to determine a table of values (block  316 ). The mechanism averages the data for the wrapped PHYs (block  318 ). The mechanism then determines the cable length based on the average of the wrapped PHYs (block  320 ). Thereafter, operation ends. 
     During product testing, multiple cable lengths may be attached, whereby each specific cable length is characterized by collecting a set of data points as the wrap is detuned to failure.  FIG. 3  illustrates how the characterization data reflects the range of data points with respect to optimum performance and failure. A table of these characterization values may be used during the wrap testing to identify whether a long cable or short cable, or other predetermined lengths, is attached. In other words, error rates may be recorded for known lengths. The mechanism may then compare the recorded values from blocks  308  and  310 , or the average data from block  318 , to the recorded error rates for known lengths. When characterizing wide ports, there are multiple link wraps that are tested. This provides multiple data points for more granular length determination of the attached cable. Note that the flowchart of  FIG. 3  may operate for a single PHY for a narrow port cable. 
     In accordance with one illustrative embodiment, high speed serial interfaces used in high frequency applications may be dynamically margined beyond normal limits to determine optimum performance settings. The acquired setting represents a system calibration point for each physical path. Each system may store the calibration data for the respective point-to-point nodes of the serial interface connection. 
     A high speed differential interface may consist of four wires. Two wires are used differentially to represent a single signal, such as a transmit signal. Similarly, two wires are used differentially to represent a second signal, such as a receive signal. In this fashion, transmit and receive signals are implemented. In accordance with an illustrative embodiment, a mechanism is provided to optimize the performance of the data transmission between subsystems across the high speed interface. 
     The mechanism may vary the parameters of the stimulus and response mechanisms in such a manner as to stress the communication interface transfer function. The mechanism may then determine the design/guard band margin of the specific hardware under test. The resulting information may then be used as calibration factors for the specific hardware configuration. 
     For high speed SAS switches, the mechanism may use pre-emphasis/input compensation to test for margins. In this case, focus is across a communication interface, point-to-point communication from transmitter to receiver. This may cover blade slots, internal high speed fabric, and external cabling, for example. 
     In the past, a single calibration factor would be used for the system or for a limited set of cable lengths. The mechanism of the illustrative embodiment covers an unlimited number of cable lengths and paths (cables of variable width) as a result of the individual point-to-point calibration. Note that the mechanism of the illustrative embodiment may also be applied to internalized high speed fabrics as opposed to cabled interfaces. Instead of a nominal set of parameters, the system can be optimized for every path. Many times, the electrical length of a cable or path may not closely correlate to the physical length due to parasitics across the connection. This calibration mechanism may optimize the system for both physical and electrical differences. 
     The calibration may be applied for each point-to-point connection, such as a consistent set of subsystems cabled together. As another example, the calibration may be applied to a changing set of subsystems, such as system reconfiguration, addition or reduction of cabled subsystems, or subsystem degradation due to time or environment. Performance calibration may be initiated by power on reset, notification of a hardware change or reconfiguration, or increased error correction rate above a set limit. 
       FIG. 4  is a block diagram illustrating an example system environment in which aspects of the illustrative embodiments may be implemented. High speed subsystem  410  is connected to high speed subsystem  430  via subsystem external cabling. High speed subsystem  410  includes PHY and link layers  412 , which is connected to a transmitter/receiver pair through serialization/de-serialization (SERDES) circuit  416 . High speed subsystem  410  also includes PHY and link layers  414 , which is connected to a transmitter/receiver pair through serialization/de-serialization (SERDES) circuit  418 . The transmitter/receiver pairs are connected to the subsystem external cabling through connector  420 . High speed subsystem  430  includes PHY and link layers  432 , which is connected to a transmitter/receiver pair through serialization/de-serialization (SERDES) circuit  436 . High speed subsystem  430  also includes PHY and link layers  434 , which is connected to a transmitter/receiver pair through serialization/de-serialization (SERDES) circuit  438 . The transmitter/receiver pairs in high speed subsystem  430  are connected to the subsystem external cabling through connector  440 . 
     In the example depicted in  FIG. 4 , the PHY and link layers  412 ,  414  and SERDES circuits  416 ,  418  in high speed subsystem  410  represent stimulus (transmitter)  452 . The PHY and link layers  432 ,  434  and SERDES circuits  436 ,  438  in high speed subsystem  430  represent response (receiver)  456 . The transceiver pairs, connectors  420 ,  440 , and subsystem external cabling represent a complex interface transfer function  454 . In accordance with the illustrative embodiment, the mechanism varies stimulus and response parameters. The range of functionality determines a performance margin for a given set of externally cabled subsystems. 
       FIG. 5  is a block diagram illustrating a subsystem interface environment in which aspects of the illustrative embodiments may be implemented. Host system  510  includes internal application processors  512 - 516 , which are connected to SAS switch  518  at internal ports. Storage subsystems  522 - 526  are connected to SAS switch  518  via high speed SAS cables at external ports. The mechanism of the illustrative embodiment may margin each point-to-point connection to find the optimum performance setting. The mechanism may then calibrate data stored for each point-to-point connection. 
       FIG. 6  is a block diagram that illustrates a high speed point-to-point calibration procedure in accordance with an illustrative embodiment. Subsystem  610  includes PHY and link layers  612 , which are connected to a transmit/receiver pair via SERDES  616 . Subsystem  630  includes PHY and link layers  632 , which are connected to a transmit/receiver pair via SERDES  636 . The transmit/receiver pair of subsystem  610  is connected to the transmit/receiver pair of subsystem  630  by external cable  650 . 
     A node-to-node connection includes the output transmitter, printed circuit board paths, connectors, internal high speed fabric, external cables, and the input receiver. The calibration mechanism of the illustrative embodiment sets transmit and receiver parameters to nominal design value. 
     The mechanism then determines the transmit set point for one end of the point-to-point external connection (Node A). The mechanism generates self test patterns at the source switch and monitors expected data at the receive switch at the other end of the external connection (Node B). The parameter the mechanism measures is bit error rate (BER). In one exemplary embodiment, a unit of BER is one error per megabit of data received. The calibration mechanism then margins the transmit settings within a minimum (min) to maximum (max) range. The transmit set point for Node A corresponds to the transmit set point that achieved the highest BER at the receiver, Node B. 
     The calibration mechanism then determines the receiver set point for the other end of the point-to-point external connection (Node B). The mechanism generates self test patterns at the source switch and monitors expected data at the receive switch, Node B of the external connection. The calibration mechanism margins the receiver settings from min to max range. The receiver set point of Node B corresponds to the receiver set point that achieved the highest BER at the receiver. 
     The calibration mechanism then repeats the above calibration sequence for external cable Node C and Node D. 
       FIG. 7  is a flowchart illustrating operation of a point-to-point calibration mechanism in accordance with an illustrative embodiment. Operation begins and the calibration mechanism sets self test patterns at the transmit side (block  702 ). The calibration mechanism sets the transmit SAS parameters to minimum (block  704 ) and sets receive SAS parameters to nominal (block  706 ). 
     The calibration mechanism calculates bit error rate (BER) (block  708 ). The mechanism then determines whether the transmit parameter is equal to the maximum (block  710 ). If the transmit parameter is not equal to the maximum, then the calibration mechanism increments the transmit SAS parameter (block  712 ), and operation returns to block  708  to calculate the BER for the incremented transmit parameter. As the calibration mechanism margins the transmit SAS parameter from minimum to maximum, the mechanism logs BER for each parameter value, as seen in block  714 . 
     If the transmit parameter is equal to the maximum in block  710 , then the calibration mechanism calculates the transmit calculation value (block  716 ). Next, the calibration mechanism sets the receive SAS parameter to minimum (block  718 ) and sets the transmit SAS parameter to nominal (block  720 ). 
     The calibration mechanism calculates BER (block  722 ). The mechanism then determines whether the receive parameter is equal to the maximum (block  724 ). If the receive parameter is not equal to the maximum, then the calibration mechanism increments the receive SAS parameter (block  726 ), and operation returns to block  722  to calculate the BER for the incremented receive parameter. As the calibration mechanism margins the receive SAS parameter from minimum to maximum, the mechanism logs BER for each parameter value, as seen in block  728 . 
     If the receive parameter is equal to the maximum in block  724 , then the calibration mechanism calculates the receive calibration value (block  730 ). Thereafter, operation ends. 
       FIG. 8  is a flowchart illustrating system calibration in accordance with an illustrative embodiment. Operation begins responsive to one of a plurality of initiating conditions, including power on reset (block  802 ), system reconfiguration (block  804 ), added or reduced cabled subsystems (block  806 ), or SAS bit error rate interface degrading (block  808 ). The calibration mechanism, in response to an initiating condition, performs point-to-point calibration for the affected high speed interface (block  810 ). Then, the calibration mechanism updates calibration parameters in the system firmware (block  812 ). Thereafter, system calibration is complete (block  814 ), and operation ends. 
     Thus, the illustrative embodiments solve the disadvantages of the prior art by providing a mechanism and procedure for detecting cable length in a storage subsystem with wide ports. The mechanism may use in-situ bidirectional cable wrapping for determining different cable lengths. The mechanism under-margins transmitter output to failure for each external port and even for each PHY within a wide port. Based on the transition point from “good” wrap to “bad” wrap, the cable length may be determined. This assumes that there are a fixed number of predetermined cable lengths, such as “long” and “short.” The transition point identifies if the cable is long or short, at which point the optimum tuning parameters can accordingly be set. 
     The illustrative embodiments further provide a mechanism to calibrate the high speed transmitter/receiver pair characteristics, and, thus, to optimize the transmission performance between subsystems. The mechanism mitigates the need for frequent error correction and does not incur the performance degradation associated with error correction techniques. 
     It should be appreciated that the illustrative embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. In one exemplary embodiment, the mechanisms of the illustrative embodiments are implemented in software, which includes but is not limited to firmware, resident software, microcode, etc. 
     Furthermore, the illustrative embodiments may take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer-readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. 
     The medium may be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk—read-only memory (CD-ROM), compact disk—read/write (CD-R/W) and DVD. 
     A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. 
     Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems and Ethernet cards are just a few of the currently available types of network adapters. 
     The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.