Patent Publication Number: US-11380686-B2

Title: Semiconductor devices including work function layers

Description:
CROSS-REFERENCE TO THE RELATED APPLICATION 
     This U.S. non-provisional patent application claims priority from Korean Patent Application No. 10-2020-0074713, filed on Jun. 19, 2020, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Field 
     Example embodiments of the disclosure relate to semiconductor devices having work function layers and/or formation methods thereof. 
     2. Description of Related Art 
     In accordance with high integration of a semiconductor device, research on technology for disposing a plurality of transistors having different threshold voltages on a substrate is being conducted. Use of a plurality of processes executed in a sequential manner for embodiment of a plurality of transistors having different threshold voltages is very disadvantageous in terms of mass production efficiency. An increase in the number of processes may increase scattering of electrical characteristics of transistors. 
     SUMMARY 
     Example embodiments of the disclosure provide semiconductor devices having superior electrical characteristics while being advantageous in terms of mass production efficiency and/or formation methods thereof. 
     A semiconductor device according to example embodiments of the disclosure includes a substrate, a first transistor on the substrate, and a second transistor on the substrate. The first transistor has a first threshold voltage. The first transistor includes a first N-type active region defined on the substrate, a first gate electrode extending across the first N-type active region, and a first gate dielectric layer between the first N-type active region and the first gate electrode. The first gate electrode has a first work function layer. The first gate dielectric layer has high-k dielectrics containing La. The first work function layer includes a first layer on the first gate dielectric layer and having TiON, a second layer on the first layer and having TiN or TiON, a third layer on the second layer and having TiON, a fourth layer on the third layer and having TiN, and a fifth layer on the fourth layer and having TiAlC. The second transistor has a second threshold voltage different from the first threshold voltage. The second transistor includes a first P-type active region defined on the substrate, a second gate electrode extending across the first P-type active region, and a second gate dielectric layer between the first P-type active region and the second gate electrode. The second gate electrode has a second work function layer. The second gate dielectric layer has high-k dielectrics. The second work function layer includes the fifth layer directly contacting the second gate dielectric layer. 
     A semiconductor device according to example embodiments of the disclosure includes a substrate, a first transistor on the substrate, and a second transistor on the substrate. The first transistor has a first threshold voltage. The first transistor includes a first N-type active region having a plurality of first N-type active patterns vertically aligned on the substrate, a first gate electrode extending across the first N-type active region, and a first gate dielectric layer between the first N-type active region and the first gate electrode. The first gate electrode has a first work function layer. The first gate dielectric layer has high-k dielectrics containing La. The first work function layer includes a first layer on the first gate dielectric layer and having TiON, a second layer on the first layer and having TiN or TiON, a third layer on the second layer and having TiON, a fourth layer on the third layer and having TiN, and a fifth layer on the fourth layer and having TiAlC. The second transistor has a second threshold voltage different from the first threshold voltage. The second transistor includes a first P-type active region having a plurality of first P-type active patterns vertically aligned on the substrate, a second gate electrode extending across the first P-type active region, and a second gate dielectric layer between the first P-type active region and the second gate electrode. The second gate electrode has a second work function layer. The second gate dielectric layer has high-k dielectrics. The second work function layer includes the fifth layer directly contacting the second gate dielectric layer. 
     A semiconductor device according to example embodiments of the disclosure includes a substrate, first to third N-type active regions and first to third P-type active regions on the substrate, first to sixth gate electrodes, a first gate dielectric layer, a second gate dielectric layer, and first to fifth layers on the substrate. The first to third N-type active regions and first to third P-type active regions are spaced apart from one another. The first gate electrode extends across the first N-type active region and has a first work function layer. The second gate electrode extends across the first P-type active region and has a second work function layer. The third gate electrode extends across the second N-type active region and has a third work function layer. The fourth gate electrode extends across the third N-type active region and has a fourth work function layer. The fifth gate electrode extends across the second P-type active region and has a fifth work function layer. The sixth gate electrode extends across the third P-type active region and has a sixth work function layer. The first gate dielectric layer has high-k dielectrics containing La. The first gate dielectric layer is provided between the first N-type active region and the first gate electrode. The first gate dielectric layer is provided between the third N-type active region and the fourth gate electrode. The first gate dielectric layer is provided between the second P-type active region and the fifth gate electrode. The first gate dielectric layer is provided between the third P-type active region and the sixth gate electrode. The second gate dielectric layer has high-k dielectrics. The second gate dielectric layer is provided between the first P-type active region and the second gate electrode and between the second N-type active region and the third gate electrode. The first layer includes TiON. The second layer includes TiN or TiON. The third layer includes TiON. The fourth layer includes TiN. The fifth layer includes TiAlC. The first work function layer includes the first layer on the first gate dielectric layer, the second layer on the first layer, the third layer on the second layer, the fourth layer on the third layer, and the fifth layer on the fourth layer. The second work function layer includes the fifth layer directly contacting the second gate dielectric layer. The third work function layer includes first layer on the second gate dielectric layer, the second layer on the first layer, the third layer on the second layer, the fourth layer on the third layer, and the fifth layer on the fourth layer. The fourth work function layer includes the third layer on the first gate dielectric layer, the fourth layer on the third layer, and the fifth layer on the fourth layer. The fifth work function layer includes the fourth layer on the first gate dielectric layer and the fifth layer on the fourth layer. The sixth work function layer includes the fifth layer directly contacting the first gate dielectric layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is sectional views explaining semiconductor devices according to example embodiments of the disclosure. 
         FIG. 2  is a layout explaining semiconductor devices according to example embodiments of the disclosure. 
         FIGS. 3 to 27  are sectional views explaining semiconductor devices according to example embodiments of the disclosure. 
         FIGS. 28 to 43  are sectional views explaining formation methods of semiconductor devices according to example embodiments of the disclosure. 
     
    
    
     DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS 
       FIG. 1  is sectional views explaining semiconductor devices according to example embodiments of the disclosure.  FIG. 2  is a layout explaining semiconductor devices according to example embodiments of the disclosure.  FIG. 3  is cross-sectional views taken along lines  1 - 1 ′,  2 - 2 ′,  3 - 3 ′,  4 - 4 ′,  5 - 5 ′ and  6 - 6 ′ in  FIG. 2 .  FIG. 4  is cross-sectional views taken along lines  11 - 11 ′,  12 - 12 ′,  13 - 13 ′,  14 - 14 ′,  15 - 15 ′ and  16 - 16 ′ in  FIG. 2 .  FIG. 5  is cross-sectional views taken along lines  1 - 1 ′ and  11 - 11 ′ in  FIG. 2 .  FIG. 6  is cross-sectional views taken along lines  2 - 2 ′ and  12 - 12 ′ in  FIG. 2 .  FIG. 7  is cross-sectional views taken along lines  3 - 3 ′ and  13 - 13 ′ in  FIG. 2 .  FIG. 8  is cross-sectional views taken along lines  4 - 4 ′ and  14 - 14 ′ in  FIG. 2 .  FIG. 9  is cross-sectional views taken along lines  5 - 5 ′ and  15 - 15 ′ in  FIG. 2 .  FIG. 10  is cross-sectional views taken along lines  6 - 6 ′ and  16 - 16 ′ in  FIG. 2 .  FIG. 1  may correspond to an enlarged view showing a first portion  31  of  FIG. 5 , a second portion  32  of  FIG. 6 , a third portion  33  of  FIG. 7 , a fourth portion  34  of  FIG. 8 , a fifth portion  35  of  FIG. 9 , and a sixth portion  36  of  FIG. 10 . 
     Referring to  FIG. 1 , the semiconductor devices according to example embodiments of the disclosure may include first to sixth active regions  41  to  46 , an interface dielectric layer  47 , a plurality of first and second gate dielectric layers  48  and  49 , first to sixth gate electrodes G 1  to G 6 , and a gate capping layer  76 . 
     The interface dielectric layer  47 , the second gate dielectric layer  49 , the first gate electrode G 1 , and the gate capping layer  76  may be sequentially stacked on the first active region  41 . The interface dielectric layer  47 , the first gate dielectric layer  48 , the second gate electrode G 2 , and the gate capping layer  76  may be sequentially stacked on the second active region  42 . The interface dielectric layer  47 , the second gate dielectric layer  49 , the third gate electrode G 3 , and the gate capping layer  76  may be sequentially stacked on the third active region  43 . 
     The interface dielectric layer  47 , the second gate dielectric layer  49 , the fourth gate electrode G 4 , and the gate capping layer  76  may be sequentially stacked on the fourth active region  44 . The interface dielectric layer  47 , the second gate dielectric layer  49 , the fifth gate electrode G 5 , and the gate capping layer  76  may be sequentially stacked on the fifth active region  45 . The interface dielectric layer  47 , the first gate dielectric layer  48 , the sixth gate electrode G 6 , and the gate capping layer  76  may be sequentially stacked on the sixth active region  46 . 
     The first gate electrode G 1  may include a first work function layer WF 1 , a first gate conductive layer  72  and a second gate conductive layer  74  which are sequentially stacked. The first work function layer WF 1  may include a first layer  61 , a second layer  62 , a third layer  63 , a fourth layer  64  and a fifth layer  65  which are sequentially stacked. The first layer  61  may directly contact the second gate dielectric layer  49 . 
     The second gate electrode G 2  may include a second work function layer WF 2 , the first gate conductive layer  72  and the second gate conductive layer  74  which are sequentially stacked. The second work function layer WF 2  may include the first layer  61 , the second layer  62 , the third layer  63 , the fourth layer  64  and the fifth layer  65  which are sequentially stacked. The first layer  61  may directly contact the first gate dielectric layer  48 . 
     The third gate electrode G 3  may include a third work function layer WF 3 , the first gate conductive layer  72  and the second gate conductive layer  74  which are sequentially stacked. The third work function layer WF 3  may include the third layer  63 , the fourth layer  64  and the fifth layer  65  which are sequentially stacked. The third layer  63  may directly contact the second gate dielectric layer  49 . 
     The fourth gate electrode G 4  may include a fourth work function layer WF 4 , the first gate conductive layer  72  and the second gate conductive layer  74  which are sequentially stacked. The fourth work function layer WF 4  may include the fourth layer  64  and the fifth layer  65  which are sequentially stacked. The fourth layer  64  may directly contact the second gate dielectric layer  49 . 
     The fifth gate electrode G 5  may include a fifth work function layer WF 5 , the first gate conductive layer  72  and the second gate conductive layer  74  which are sequentially stacked. The fifth work function layer WF 5  may include the fifth layer  65 . The fifth layer  65  may directly contact the second gate dielectric layer  49 . 
     The sixth gate electrode G 6  may include a sixth work function layer WF 6 , the first gate conductive layer  72  and the second conductive layer  74  which are sequentially stacked. The sixth work function layer WF 6  may include the fifth layer  65 . The fifth layer  65  may directly contact the first gate dielectric layer  48 . 
     Each of the first to third active regions  41  to  43  may include a semiconductor layer having N-type impurities. Each of the first to third active regions  41  to  43  may include a semiconductor layer having P-type impurities. Each of the fourth to sixth active regions  44  to  46  may be referred to as a “P-type active region”. In an embodiment, each of the first to third active regions  41  to  43  may include a monocrystalline silicon layer having N-type impurities. Each of the fourth to sixth active regions  44  to  46  may include a monocrystalline silicon layer having P-type impurities. 
     The interface dielectric layer  47  may include a silicon oxide formed using a thermal oxidation process or a cleaning process. The interface dielectric layer  47  may be omitted. The first gate dielectric layer  48  may include high-k dielectrics. The first gate dielectric layer  48  may include Hf, O, and N. The first gate dielectric layer  48  may include HfON. The second gate dielectric layer  49  may include high-k dielectrics containing La. The second gate dielectric layer  49  may include Hf, La, O, and N. The second gate dielectric layer  49  may include HfLaON. In an embodiment, the second gate dielectric layer  49  may be referred to as a “first gate dielectric layer”, and the first gate dielectric layer  48  may be referred to as a “second gate dielectric layer”. 
     The first layer  61  may include TiON. The second layer  62  may include TiN or TiON. The third layer  63  may include TiON. The fourth layer  64  may include TiN. The fifth layer  65  may include TiAlC. The first gate conductive layer  72  may include TiN. The second gate conductive layer  74  may include W. 
     Referring to  FIG. 2 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21  having a first area LP, a second area SP, a third area RP, a fourth area RN, a fifth area SN, and a sixth area LN. 
     A plurality of first transistors TR 1  may be disposed within the first area LP. For example, a first active region  41  may be defined in the substrate  21  within the first area LP. A plurality of first gate electrodes G 1  may be disposed across the first active region  41 . The first active region  41  and the plurality of first gate electrodes G 1  may constitute the plurality of first transistors TR 1 . A plurality of second transistors TR 2  may be disposed within the second area SP. For example, a second active region  42  may be defined in the substrate  21  within the second area SP. A plurality of second gate electrodes G 2  may be disposed across the second active region  42 . The second active region  42  and the plurality of second gate electrodes G 2  may constitute the plurality of second transistors TR 2 . A plurality of third transistors TR 3  may be disposed within the third area RP. For example, a third active region  43  may be defined in the substrate  21  within the third area RP. A plurality of third gate electrodes G 3  may be disposed across the third active region  43 . The third active region  43  and the plurality of third gate electrodes G 3  may constitute the plurality of third transistors TR 3 . 
     A plurality of fourth transistors TR 4  may be disposed within the fourth area RN. For example, a fourth active region  44  may be defined in the substrate  21  within the fourth area RN. A plurality of fourth gate electrodes G 4  may be disposed across the fourth active region  44 . The fourth active region  44  and the plurality of fourth gate electrodes G 4  may constitute the plurality of fourth transistors TR 4 . A plurality of fifth transistors TR 5  may be disposed within the fifth area SN. For example, a fifth active region  45  may be defined in the substrate  21  within the fifth area SN. A plurality of fifth gate electrodes G 5  may be disposed across the fifth active region  45 . The fifth active region  45  and the plurality of fifth gate electrodes G 5  may constitute the plurality of fifth transistors TR 5 . A plurality of sixth transistors TR 6  may be disposed within the sixth area LN. For example, a sixth active region  46  may be defined in the substrate  21  within the sixth area LN. A plurality of sixth gate electrodes G 6  may be disposed across the sixth active region  46 . The sixth active region  46  and the plurality of sixth gate electrodes G 6  may constitute the plurality of sixth transistors TR 6 . 
     Each of the plurality of first to sixth transistors TR 1 , TR 2 , TR 3 , TR 4 , TR 5  and TR 6  may include a fin field effect transistor (finFET), a multi-bridge channel transistor such as MBCFET®, a nano-wire transistor, a vertical transistor, a recess channel transistor, a 3-D transistor, a planar transistor, or a combination thereof. In an embodiment, each of the plurality of first to third transistors TR 1 , TR 2  and TR 3  may be a PMOS transistor. In an embodiment, each of the plurality of fourth to sixth transistors TR 4 , TR 5  and TR 6  may be an NMOS transistor. 
     Each of the plurality of first transistors TR 1  may have a first threshold voltage. Each of the plurality of second transistors TR 2  may have a second threshold voltage different from the first threshold voltage. Each of the plurality of third transistors TR 3  may have a third threshold voltage different from the first threshold voltage. An absolute value of the second threshold voltage may be smaller than an absolute value of the first threshold voltage. An absolute value of the third threshold voltage may be greater than the absolute value of the first threshold voltage. For example, the first threshold voltage may be about −220 mV. The second threshold voltage may be about −150 mV. The third threshold voltage may be about −300 mV. 
     Each of the plurality of fourth transistors TR 4  may have a fourth threshold voltage different from the first threshold voltage. Each of the plurality of fifth transistors TR 5  may have a fifth threshold voltage different from the fourth threshold voltage. Each of the plurality of sixth transistors TR 6  may have a sixth threshold voltage different from the fourth threshold voltage. The fourth threshold voltage may be higher than the sixth threshold voltage. The fifth threshold voltage may be lower than the sixth threshold voltage. For example, the fourth threshold voltage may be about 320 mV. The fifth threshold voltage may be about 180 mV. The sixth threshold voltage may be about 250 mV. 
     Again referring to  FIGS. 1 and 2 , in an embodiment, the plurality of sixth transistors TR 6  may be referred to as a “plurality of second transistors”. The plurality of second transistors TR 2  may be referred to as a “plurality of third transistors”. The plurality of third transistors TR 3  may be referred to as a “plurality of fourth transistors”. The plurality of fourth transistors TR 4  may be referred to as a “plurality of fifth transistors”. The plurality of fifth transistors TR 5  may be referred to as a “plurality of sixth transistors”. The plurality of sixth gate electrodes G 6  may be referred to as a “plurality of second gate electrodes”. The plurality of second gate electrodes G 2  may be referred to as a “plurality of third gate electrodes”. The plurality of third gate electrodes G 3  may be referred to as a “plurality of fourth gate electrodes”. The plurality of fourth gate electrodes G 4  may be referred to as a “plurality of fifth gate electrodes”. The plurality of fifth gate electrodes G 5  may be referred to as a “plurality of sixth gate electrodes”. 
     The first active region  41  may be referred to as a “first N-type active region”. The second active region  42  may be referred to as a “second N-type active region”. The third active region  43  may be referred to as a “third N-type active region”. The sixth active region  46  may be referred to as a “first P-type active region”. The fourth active region  44  may be referred to as a “second P-type active region”. The fifth active region  45  may be referred to as a “third P-type active region”. The sixth work function layer WF 6  may be referred to as a “second work function layer”. The second work function layer WF 2  may be referred to as a “third work function layer”. The third work function layer WF 3  may be referred to as a “fourth work function layer”. The fourth work function layer WF 4  may be referred to as a “fifth work function layer”. The fifth work function layer WF 5  may be referred to as a “sixth work function layer”. 
     Referring to  FIG. 3 , a pair of first source/drain regions  55  may be disposed within the first active region  41  adjacent to opposite sides of the first gate electrode G 1 . The pair of first source/drain regions  55  may be disposed within the second active region  42  adjacent to opposite sides of the second gate electrode G 2 . The pair of first source/drain regions  55  may be disposed within the third active region  43  adjacent to opposite sides of the third gate electrode G 3 . A pair of second source/drain regions  59  may be disposed within the fourth active region  44  adjacent to opposite sides of the fourth gate electrode G 4 . The pair of second source/drain regions  59  may be disposed within the fifth active region  45  adjacent to opposite sides of the fifth gate electrode G 5 . The pair of second source/drain regions  59  may be disposed within the sixth active region  46  adjacent to opposite sides of the sixth gate electrode G 6 . In an embodiment, each of the first to sixth gate electrodes G 1  to G 6  may correspond to a replacement metal gate electrode. 
     Referring to  FIG. 4 , an element isolation layer  23  may be disposed on the substrate  21  to define the first to sixth active regions  41  to  46 . Each of the first to sixth active regions  41  to  46  may protrude to a level higher than an upper surface of the element isolation layer  23 . The first gate electrode G 1  may cover an upper surface and side surfaces of the first active region  41 . The second gate electrode G 2  may cover an upper surface and side surfaces of the second active region  42 . The third gate electrode G 3  may cover an upper surface and side surfaces of the third active region  43 . The fourth gate electrode G 4  may cover an upper surface and side surfaces of the fourth active region  44 . The fifth gate electrode G 5  may cover an upper surface and side surfaces of the fifth active region  45 . The sixth gate electrode G 6  may cover an upper surface and side surfaces of the sixth active region  46 . Each of the first to sixth gate electrodes G 1  to G 6  may extend on the element isolation layer  23 . 
     The substrate  21  may include a semiconductor substrate such as a silicon wafer. The element isolation layer  23  may include an insulating layer formed using a shallow trench isolation (STI) method. The element isolation layer  23  may include a silicon oxide, a silicon nitride, a silicon oxynitride, a silicon boron nitride (SiBN), a silicon carbon nitride (SiCN), low-k dielectrics, high-k dielectrics, or a combination thereof. 
     Referring to  FIG. 5 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a first active region  41 , an interface dielectric layer  47 , a second gate dielectric layer  49 , a pair of first source/drain regions  55 , a first gate electrode G 1 , a gate capping layer  76 , a gate spacer  78 , and an interlayer insulating layer  79 . 
     An upper surface of the element isolation layer  23  may be formed at a level lower than an uppermost end of the first active region  41 . The first active region  41  may protrude to a level higher than the upper surface of the element isolation layer  23 . The first active region  41  may include monocrystalline silicon having N-type impurities. The N-type impurities may include P, As, or a combination thereof. The first active region  41  may be referred to as a “first N-type active region”. 
     The pair of first source/drain regions  55  may be disposed within the first active region  41  adjacent to opposite sides of the first gate electrode G 1 . Uppermost ends of the pair of first source/drain regions  55  may protrude to a level higher than the uppermost end of the first active region  41 . Each of the pair of first source/drain regions  55  may include a semiconductor layer having P-type impurities. The P-type impurities may include B, BF, or a combination thereof. Each of the pair of first source/drain regions  55  may include an SiGe layer formed using a selective epitaxial growth (SEG) method. Each of the pair of first source/drain regions  55  may include a first lower drain  51 , a first intermediate drain  52 , and a first upper drain  53 . 
     The first lower drain  51  may directly contact the first active region  41 . The first intermediate drain  52  may be disposed on the first lower drain  51 . The first upper drain  53  may be disposed on the first intermediate drain  52 . The weight ratio of Ge of the first lower drain  51  may be smaller than that of the first intermediate drain  52 . In an embodiment, the first lower drain  51  may be an Si layer. The weight ratio of Ge of the first intermediate drain  52  may be greater than those of the first lower drain  51  and the first upper drain  53 . The weight ratio of Ge of the first upper drain  53  may be smaller than that of the first intermediate drain  52 . In an embodiment, the first upper drain  53  may be an Si layer. 
     The first gate electrode G 1  may include a first work function layer WF 1 , a first gate conductive layer  72  and a second gate conductive layer  74  which are sequentially stacked. The first work function layer WF 1  may include a first layer  61 , a second layer  62 , a third layer  63 , a fourth layer  64  and a fifth layer  65  which are sequentially stacked. The first layer  61  may directly contact the second gate dielectric layer  49 . 
     The first work function layer WF 1  may cover an upper surface and side surfaces of the first active region  41 . The first work function layer WF 1  may extend on the element isolation layer  23 . A lowermost end of the first work function layer WF 1  may be disposed at a level lower than an uppermost end of the first active region  41 . The lowermost end of the first work function layer WF 1  may be disposed nearer to a lower surface of the substrate than to the uppermost end of the first active region  41 . 
     The interface dielectric layer  47  may be formed on the upper surface and the side surfaces of the first active region  41 . The interface dielectric layer  47  may be interposed between the first work function layer WF 1  and the first active region  41 . The second gate dielectric layer  49  may be disposed between the first work function layer WF 1  and the interface dielectric layer  47 . The second gate dielectric layer  49  may extend between the first work function layer WF 1  and the element isolation layer  23 . 
     The gate capping layer  76  may cover the first gate electrode G 1 . The gate spacer  78  may be disposed on side walls of the gate capping layer  76  and the first gate electrode G 1 . The interlayer insulating layer  79  may be disposed on the pair of first source/drain regions  55 . Each of the gate spacer  78  and the interlayer insulating layer  79  may include a silicon oxide, a silicon nitride, a silicon oxynitride, a silicon boron nitride (SiBN), a silicon carbon nitride (SiCN), low-k dielectrics, high-k dielectrics, or a combination thereof. For example, the gate spacer  78  may include a silicon nitride. The interlayer insulating layer  79  may include a silicon oxide or low-k dielectrics. 
     The second gate dielectric layer  49  may extend between the first gate electrode G 1  and the gate spacer  78 . The second gate dielectric layer  49  may extend on side surfaces of the first work function layer WF 1 . 
     Referring to  FIG. 6 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a second active region  42 , an interface dielectric layer  47 , a first gate dielectric layer  48 , a pair of first source/drain regions  55 , a second gate electrode G 2 , a gate capping layer  76 , a gate spacer  78 , and an interlayer insulating layer  79 . In the following description, only differences will be briefly described. 
     The second active region  42  may be referred to as a “second N-type active region”. A first lower drain  51  may directly contact the second active region  42 . The second gate electrode G 2  may include a second work function layer WF 2 , a first gate conductive layer  72  and a second gate conductive layer  74  which are sequentially stacked. The second work function layer WF 2  may include a first layer  61 , a second layer  62 , a third layer  63 , a fourth layer  64 , and a fifth layer  65 . The first layer  61  may directly contact the first gate dielectric layer  48 . 
     Referring to  FIG. 7 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a third active region  43 , an interface dielectric layer  47 , a second gate dielectric layer  49 , a pair of first source/drain regions  55 , a third gate electrode G 3 , a gate capping layer  76 , a gate spacer  78 , and an interlayer insulating layer  79 . 
     The third active region  43  may be referred to as a “third N-type active region”. A first lower drain  51  may directly contact the third active region  43 . The third gate electrode G 3  may include a third work function layer WF 3 , a first gate conductive layer  72  and a second gate conductive layer  74  which are sequentially stacked. The third work function layer WF 3  may include a third layer  63 , a fourth layer  64  and a fifth layer  65  which are sequentially stacked. The third layer  63  may directly contact the second gate dielectric layer  49 . 
     Referring to  FIG. 8 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a fourth active region  44 , an interface dielectric layer  47 , a second gate dielectric layer  49 , a pair of second source/drain regions  59 , a fourth gate electrode G 4 , a gate capping layer  76 , a gate spacer  78 , and an interlayer insulating layer  79 . 
     The fourth active region  44  may include monocrystalline silicon having P-type impurities. The fourth active region  44  may be referred to as a “second P-type active region”. Each of the pair of second source/drain regions  59  may include a semiconductor layer having N-type impurities. Each of the pair of second source/drain regions  59  may include an Si layer or an SiC layer formed using a selective epitaxial growth (SEG) method. Each of the pair of second source/drain regions  59  may include a second lower drain  56 , a second intermediate drain  57 , and a second upper drain  58 . 
     The second lower drain  56  may directly contact the fourth active region  44 . The fourth gate electrode G 4  may include a fourth work function layer WF 4 , a first gate conductive layer  72  and a second gate conductive layer  74  which are sequentially stacked. The fourth work function layer WF 4  may include a fourth layer  64  and a fifth layer  65  which are sequentially stacked. The fourth layer  64  may directly contact the second gate dielectric layer  49 . 
     Referring to  FIG. 9 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a fifth active region  45 , an interface dielectric layer  47 , a second gate dielectric layer  49 , a pair of second source/drain regions  59 , a fifth gate electrode G 5 , a gate capping layer  76 , a gate spacer  78 , and an interlayer insulating layer  79 . 
     The fifth active region  45  may be referred to as a “third P-type active region”. Each of the pair of second source/drain regions  59  may include a semiconductor layer having N-type impurities. The second lower drain  56  may directly contact the fifth active region  45 . The fifth gate electrode G 5  may include a fifth work function layer WF 5 , a first gate conductive layer  72  and a second gate conductive layer  74  which are sequentially stacked. The fifth work function layer WF 5  may include a fifth layer  65 . The fifth layer  65  may directly contact the second gate dielectric layer  49 . 
     Referring to  FIG. 10 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a fifth active region  45 , an interface dielectric layer  47 , a first gate dielectric layer  48 , a pair of second source/drain regions  59 , a sixth gate electrode G 6 , a gate capping layer  76 , a gate spacer  78 , and an interlayer insulating layer  79 . 
     The sixth active region  46  may be referred to as a “first P-type active region”. Each of the pair of second source/drain regions  59  may include a semiconductor layer having N-type impurities. The second lower drain  56  may directly contact the sixth active region  46 . The sixth gate electrode G 6  may include a sixth work function layer WF 6 , a first gate conductive layer  72  and a second gate conductive layer  74  which are sequentially stacked. The sixth work function layer WF 6  may include a fifth layer  65 . The fifth layer  65  may directly contact the first gate dielectric layer  48 . 
     The sixth work function layer WF 6  may cover an upper surface and side surfaces of the sixth active region  46 . The sixth work function layer WF 6  may extend on the element isolation layer  23 . The first gate dielectric layer  48  may be disposed between the sixth work function layer WF 6  and the interface dielectric layer  47 . The first gate dielectric layer  48  may extend between the sixth work function layer WF 6  and the element isolation layer  23 . The first gate dielectric layer  48  may extend between the sixth gate electrode G 6  and the gate spacer  78 . The first gate dielectric layer  48  may extend on side surfaces of the sixth work function layer WF 6 . 
       FIG. 11  is cross-sectional views taken along lines  1 - 1 ′,  2 - 2 ′,  3 - 3 ′,  4 - 4 ′,  5 - 5 ′ and  6 - 6 ′ in  FIG. 2 .  FIG. 12  is cross-sectional views taken along lines  11 - 11 ′,  12 - 12 ′,  13 - 13 ′,  14 - 14 ′,  15 - 15 ′ and  16 - 16 ′ in  FIG. 2 .  FIG. 13  is cross-sectional views taken along lines  1 - 1 ′ and  11 - 11 ′ in  FIG. 2 .  FIG. 14  is cross-sectional views taken along lines  2 - 2 ′ and  12 - 12 ′ in  FIG. 2 .  FIG. 15  is cross-sectional views taken along lines  3 - 3 ′ and  13 - 13 ′ in  FIG. 2 .  FIG. 16  is cross-sectional views taken along lines  4 - 4 ′ and  14 - 14 ′ in  FIG. 2 .  FIG. 17  is cross-sectional views taken along lines  5 - 5 ′ and  15 - 15 ′ in  FIG. 2 .  FIG. 18  is cross-sectional views taken along lines  6 - 6 ′ and  16 - 16 ′ in  FIG. 2 . 
     Referring to  FIG. 11 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , first to sixth active regions  41  to  46 , a plurality of first and second source/drain regions  55  and  59 , and first to sixth gate electrodes G 1  to G 6 . In an embodiment, each of the first to sixth gate electrodes G 1  to G 6  may correspond to a replacement metal gate electrode. 
     Referring to  FIG. 12 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , first to sixth active regions  41  to  46 , and first to sixth gate electrodes G 1  to G 6 . 
     Referring to  FIG. 13 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a first active region  41 , an interface dielectric layer  47 , a second gate dielectric layer  49 , a pair of first source/drain regions  55 , a first gate electrode G 1 , a gate capping layer  76 , a gate spacer  78 , an interlayer insulating layer  79 , and an inner spacer  88 . 
     The first active region  41  may include a plurality of first active patterns  41 A,  41 B,  41 C and  41 D. The plurality of first active patterns  41 A,  41 B,  41 C and  41 D may be vertically aligned on the substrate  21 . One of the plurality of first active patterns  41 A,  41 B,  41 C and  41 D, which is disposed at a lowermost side, that is, the first active pattern  41 A, may be defined within the substrate  21  by the element isolation layer  23 . The plurality of first active patterns  41 A,  41 B,  41 C and  41 D may be spaced apart from one another. The first active region  41  may be referred to as a “first N-type active region”. The plurality of first active patterns  41 A,  41 B,  41 C and  41 D may be referred to as a “plurality of first N-type active patterns”. 
     The pair of first source/drain regions  55  may be disposed within the first active region  41  adjacent to opposite sides of the first gate electrode G 1 . The first gate electrode G 1  may include a first work function layer WF 1 , a first gate conductive layer  72 , and a second gate conductive layer  74 . The first gate electrode G 1  may cover an upper surface and side surfaces of the first active pattern  41 A disposed at the lowermost side from among the plurality of first active patterns  41 A,  41 B,  41 C and  41 D. The first gate electrode G 1  may surround upper surfaces, lower surfaces and side surfaces of the remaining first active patterns  41 B,  41 C and  41 D, except for the first active pattern  41 A disposed at the lowermost side from among the plurality of first active patterns  41 A,  41 B,  41 C and  41 D. 
     The inner spacer  88  may be interposed between first gate electrode G 1  and the pair of first source/drain regions  55 . The inner spacer  88  may include a silicon oxide, a silicon nitride, a silicon oxynitride, low-k dielectrics, high-k dielectrics, or a combination thereof. For example, the inner spacer  88  may include a silicon nitride. The inner spacer  88  may be omitted. 
     The first work function layer WF 1  may include a first layer  61 , a second layer  62 , a third layer  63 , a fourth layer  64  and a fifth layer  65  which are sequentially stacked. The first layer  61  may directly contact the second gate dielectric layer  49 . The first work function layer WF 1  may cover the upper surface and the side surfaces of the first active pattern  41 A disposed at the lowermost side from among the plurality of first active patterns  41 A,  41 B,  41 C and  41 D. The first work function layer WF 1  may surround the upper surfaces, the lower surfaces and the side surfaces of the remaining first active patterns  41 B,  41 C and  41 D, except for the first active pattern  41 A disposed at the lowermost side from among the plurality of first active patterns  41 A,  41 B,  41 C and  41 D. 
     The interface dielectric layer  47  may be formed on the first active region  41 . The interface dielectric layer  47  may be interposed between the first work function layer WF 1  and the first active region  41 . The second gate dielectric layer  49  may be disposed between the first work function layer WF 1  and the interface dielectric layer  47 . The second gate dielectric layer  49  may extend between the first work function layer WF 1  and the element isolation layer  23 . The second gate dielectric layer  49  may extend between the first work function layer WF 1  and the inner spacer  88 . 
     Referring to  FIG. 14 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a second active region  42 , an interface dielectric layer  47 , a first gate dielectric layer  48 , a pair of first source/drain regions  55 , a second gate electrode G 2 , a gate capping layer  76 , a gate spacer  78 , an interlayer insulating layer  79 , and an inner spacer  88 . 
     The second active region  42  may include a plurality of second active patterns  42 A,  42 B,  42 C and  42 D. The second active region  42  may be referred to as a “second N-type active region”. The plurality of second active patterns  42 A,  42 B,  42 C and  42 D may be referred to as a “plurality of second N-type active patterns”. The second gate electrode G 2  may include a second work function layer WF 2 , a first gate conductive layer  72  and a second gate conductive layer  74  which are sequentially stacked. The second work function layer WF 2  may include a first layer  61 , a second layer  62 , a third layer  63 , a fourth layer  64  and a fifth layer  65  which are sequentially stacked. The first layer  61  may directly contact the first gate dielectric layer  48 . 
     Referring to  FIG. 15 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a third active region  43 , an interface dielectric layer  47 , a second gate dielectric layer  49 , a pair of first source/drain regions  55 , a third gate electrode G 3 , a gate capping layer  76 , a gate spacer  78 , an interlayer insulating layer  79 , and an inner spacer  88 . 
     The third active region  43  may include a plurality of third active patterns  43 A,  43 B,  43 C and  43 D. The third active region  43  may be referred to as a “third N-type active region”. The plurality of third active patterns  43 A,  43 B,  43 C and  43 D may be referred to as a “plurality of third N-type active patterns”. The third gate electrode G 3  may include a third work function layer WF 3 , a first gate conductive layer  72  and a second gate conductive layer  74  which are sequentially stacked. The third work function layer WF 3  may include a third layer  63 , a fourth layer  64  and a fifth layer  65  which are sequentially stacked. The third layer  63  may directly contact the second gate dielectric layer  49 . 
     Referring to  FIG. 16 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a fourth active region  44 , an interface dielectric layer  47 , a second gate dielectric layer  49 , a pair of second source/drain regions  59 , a fourth gate electrode G 4 , a gate capping layer  76 , a gate spacer  78 , an interlayer insulating layer  79 , and an inner spacer  88 . 
     The fourth active region  44  may include a plurality of fourth active patterns  44 A,  44 B,  44 C and  44 D. The fourth active region  44  may be referred to as a “second P-type active region”. The plurality of fourth active patterns  44 A,  44 B,  44 C and  44 D may be referred to as a “plurality of second P-type active patterns”. The fourth gate electrode G 4  may include a fourth work function layer WF 4 , a first gate conductive layer  72  and a second gate conductive layer  74  which are sequentially stacked. The fourth work function layer WF 4  may include a fourth layer  64  and a fifth layer  65  which are sequentially stacked. The fourth layer  64  may directly contact the second gate dielectric layer  49 . 
     Referring to  FIG. 17 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a fifth active region  45 , an interface dielectric layer  47 , a second gate dielectric layer  49 , a pair of second source/drain regions  59 , a fifth gate electrode G 5 , a gate capping layer  76 , a gate spacer  78 , an interlayer insulating layer  79 , and an inner spacer  88 . 
     The fifth active region  45  may include a plurality of fifth active patterns  45 A,  45 B,  45 C and  45 D. The fifth active region  45  may be referred to as a “third P-type active region”. The plurality of fifth active patterns  45 A,  45 B,  45 C and  45 D may be referred to as a “plurality of third P-type active patterns”. The fifth gate electrode G 5  may include a fifth work function layer WF 5 , a first gate conductive layer  72  and a second gate conductive layer  74  which are sequentially stacked. The fifth work function layer WF 5  may include a fifth layer  65 . The fifth layer  65  may directly contact the second gate dielectric layer  49 . 
     Referring to  FIG. 18 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a sixth active region  46 , an interface dielectric layer  47 , a first gate dielectric layer  48 , a pair of second source/drain regions  59 , a sixth gate electrode G 6 , a gate capping layer  76 , a gate spacer  78 , an interlayer insulating layer  79 , and an inner spacer  88 . 
     The sixth active region  46  may include a plurality of sixth active patterns  46 A,  46 B,  46 C and  46 D. The sixth active region  46  may be referred to as a “first P-type active region”. The plurality of sixth active patterns  46 A,  46 B,  46 C and  46 D may be referred to as a “plurality of first P-type active patterns”. The sixth gate electrode G 6  may include a sixth work function layer WF 6 , a first gate conductive layer  72  and a second gate conductive layer  74  which are sequentially stacked. The sixth work function layer WF 6  may include a fifth layer  65 . The fifth layer  65  may directly contact the first gate dielectric layer  48 . 
       FIG. 19  is sectional views explaining semiconductor devices according to example embodiments of the disclosure.  FIG. 20  is cross-sectional views taken along lines  1 - 1 ′,  2 - 2 ′,  3 - 3 ′,  4 - 4 ′,  5 - 5 ′ and  6 - 6 ′ in  FIG. 2 .  FIG. 21  is cross-sectional views taken along lines  11 - 11 ′,  12 - 12 ′,  13 - 13 ′,  14 - 14 ′,  15 - 15 ′ and  16 - 16 ′ in  FIG. 2 .  FIG. 22  is cross-sectional views taken along lines  1 - 1 ′ and  11 - 11 ′ in  FIG. 2 .  FIG. 23  is cross-sectional views taken along lines  2 - 2 ′ and  12 - 12 ′ in  FIG. 2 .  FIG. 24  is cross-sectional views taken along lines  3 - 3 ′ and  13 - 13 ′ in  FIG. 2 .  FIG. 25  is cross-sectional views taken along lines  4 - 4 ′ and  14 - 14 ′ in  FIG. 2 .  FIG. 26  is cross-sectional views taken along lines  5 - 5 ′ and  15 - 15 ′ in  FIG. 2 .  FIG. 27  is cross-sectional views taken along lines  6 - 6 ′ and  16 - 16 ′ in  FIG. 2 .  FIG. 19  may correspond to an enlarged view showing a first portion  531  of  FIG. 22 , a second portion  532  of  FIG. 23 , a third portion  533  of  FIG. 24 , a fourth portion  534  of  FIG. 25 , a fifth portion  535  of  FIG. 26 , and a sixth portion  536  of  FIG. 27 . 
     Referring to  FIG. 19 , the semiconductor devices according to example embodiments of the disclosure may include first to sixth active regions  41  to  46 , an interface dielectric layer  47 , a plurality of first and second gate dielectric layers  48  and  49 , first to sixth gate electrodes G 1  to G 6 , and a gate capping layer  76 . 
     A first work function layer WF 1  may include a first layer  161 , a second layer  162 , a third layer  163 , a fourth layer  164  and a fifth layer  165  which are sequentially stacked. The first layer  161  may directly contact the second gate dielectric layer  49 . 
     A second work function layer WF 2  may include the first layer  161 , the second layer  162 , the third layer  163 , the fourth layer  164  and the fifth layer  165  which are sequentially stacked. The first layer  161  may directly contact the first gate dielectric layer  48 . 
     A third work function layer WF 3  may include the second layer  162 , the third layer  163 , the fourth layer  164  and the fifth layer  165  which are sequentially stacked. The second layer  162  may directly contact the first gate dielectric layer  48 . 
     A fourth work function layer WF 4  may include the third layer  163 , the fourth layer  164  and the fifth layer  165  which are sequentially stacked. The third layer  163  may directly contact the second gate dielectric layer  49 . 
     A fifth work function layer WF 5  may include the fourth layer  164  and the fifth layer  165  which are sequentially stacked. The fourth layer  164  may directly contact the second gate dielectric layer  49 . 
     A sixth work function layer WF 6  may include the fourth layer  164  and the fifth layer  165 . The fourth layer  164  may directly contact the first gate dielectric layer  48 . 
     The first layer  161  may include TiN. The second layer  162  may include TiN. The third layer  163  may include TiN. The fourth layer  164  may include TiN. The fifth layer  165  may include TiAlC. 
     Referring to  FIG. 20 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , first to sixth active regions  41  to  46 , a plurality of first and second source/drain regions  55  and  59 , and first to sixth gate electrodes G 1  to G 6 . In an embodiment, each of the first to sixth gate electrodes G 1  to G 6  may correspond to a replacement metal gate electrode. 
     Referring to  FIG. 21 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , first to sixth active regions  41  to  46 , and first to sixth gate electrodes G 1  to G 6 . 
     Referring to  FIG. 22 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a first active region  41 , an interface dielectric layer  47 , a second gate dielectric layer  49 , a pair of first source/drain regions  55 , a first gate electrode G 1 , a gate capping layer  76 , a gate spacer  78 , and an interlayer insulating layer  79 . A first layer  161  may directly contact the second gate dielectric layer  49 . 
     Referring to  FIG. 23 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a second active region  42 , an interface dielectric layer  47 , a first gate dielectric layer  48 , a pair of first source/drain regions  55 , a second gate electrode G 2 , a gate capping layer  76 , a gate spacer  78 , and an interlayer insulating layer  79 . A first layer  161  may directly contact the first gate dielectric layer  48 . 
     Referring to  FIG. 24 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a third active region  43 , an interface dielectric layer  47 , a first gate dielectric layer  48 , a pair of first source/drain regions  55 , a third gate electrode G 3 , a gate capping layer  76 , a gate spacer  78 , and an interlayer insulating layer  79 . A second layer  162  may directly contact the first gate dielectric layer  48 . 
     Referring to  FIG. 25 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a fourth active region  44 , an interface dielectric layer  47 , a second gate dielectric layer  49 , a pair of second source/drain regions  59 , a fourth gate electrode G 4 , a gate capping layer  76 , a gate spacer  78 , and an interlayer insulating layer  79 . A third layer  163  may directly contact the second gate dielectric layer  49 . 
     Referring to  FIG. 26 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a fifth active region  45 , an interface dielectric layer  47 , a second gate dielectric layer  49 , a pair of second source/drain regions  59 , a fifth gate electrode G 5 , a gate capping layer  76 , a gate spacer  78 , and an interlayer insulating layer  79 . A fourth layer  164  may directly contact the second gate dielectric layer  49 . 
     Referring to  FIG. 27 , the semiconductor devices according to example embodiments of the disclosure may include a substrate  21 , an element isolation layer  23 , a fifth active region  45 , an interface dielectric layer  47 , a first gate dielectric layer  48 , a pair of second source/drain regions  59 , a sixth gate electrode G 6 , a gate capping layer  76 , a gate spacer  78 , and an interlayer insulating layer  79 . A fourth layer  164  may directly contact the first gate dielectric layer  48 . 
       FIGS. 28 to 43  are sectional views explaining formation methods of semiconductor devices according to example embodiments of the disclosure. Each of  FIGS. 28 to 43  may correspond to an enlarged view showing the first portion  31  of  FIG. 5 , the second portion  32  of  FIG. 6 , the third portion  33  of  FIG. 7 , the fourth portion  34  of  FIG. 8 , the fifth portion  35  of  FIG. 9 , and the sixth portion  36  of  FIG. 10 . 
     Referring to  FIG. 28 , an interface dielectric layer  47  may be formed on first to sixth active regions  41  to  46 . The interface dielectric layer  47  may include a silicon oxide formed using a thermal oxidation process or a cleaning process. The interface dielectric layer  47  may directly contact the first to sixth active regions  41  to  46 . 
     Referring to  FIG. 29 , a first gate dielectric layer  48  may be formed on the interface dielectric layer  47 . The first gate dielectric layer  48  may include high-k dielectrics. In an embodiment, the first gate dielectric layer  48  may include HfO. 
     Referring to  FIG. 30 , an additive layer  49 A may be formed on the first gate dielectric layer  48 . In an embodiment, the additive layer  49 A may include La or LaO. 
     Referring to  FIG. 31 , a first mask pattern  49 M may be formed to cover the additive layer  49 A within a first area LP, a third area RP, a fourth area RN and a fifth area SN. Using the first mask pattern  49 M as an etch mask, the additive layer  49 A may be etched, thereby exposing the first gate dielectric layer  48  within a second area SP and a sixth area LN. 
     Referring to  FIG. 32 , the first mask pattern  49 M may be removed. A second gate dielectric layer  49  may be formed by injecting a metal material in the additive layer  49 A into the first gate dielectric layer  48  using an annealing process. In an embodiment, the second gate dielectric layer  49  may include HfLaO. 
     The second gate dielectric layer  49  may be formed on the interface dielectric layer  47  within the first area LP, the third area RP, the fourth area RN and the fifth area SN. The first gate dielectric layer  48  may remain on the interface dielectric layer  47  within the second area SP and the sixth area LN. 
     Referring to  FIG. 33 , nitrogen may be injected into the first gate dielectric layer  48  and the second gate dielectric layer  49  using a nitrogen injection process. The first gate dielectric layer  48  may include Hf, O, and N. The second gate dielectric layer  49  may include Hf, La, O, and N. In an embodiment, the first gate dielectric layer  48  may include HfON. 
     The second dielectric layer  49  may include HfLaON. 
     Referring to  FIG. 34 , a first layer  61  may be formed on the first gate dielectric layer  48  and the second gate dielectric layer  49 . The first layer  61  may include Ti, O, and N. In an embodiment, the first layer  61  may include TiON. The first layer  61  may have a thickness of 0.7 to 2 nm. 
     Referring to  FIG. 35 , a second layer  62  may be formed on the first layer  61 . The second layer  62  may include Ti and N. In an embodiment, the second layer  62  may include TiN. The second layer  62  may have a thickness of 0.7 to 2 nm. 
     Referring to  FIG. 36 , a second mask pattern  62 M may be formed to cover the second layer  62  within the first area LP and the second area SP. Using the second mask pattern  62 M as an etch mask, the second layer  62  and the first layer  61  may be etched, thereby exposing the second gate dielectric layer  49  within the third area RP, the fourth area RN and the fifth area SN while exposing the first gate dielectric layer  48  within the sixth area LN. The first layer  61  and the second layer  62  may remain within the first area LP and the second area SP. 
     Referring to  FIG. 37 , the second mask pattern  62 M may be removed. A third layer  63  may be formed on the second layer  62 , the second gate dielectric layer  49  and the first gate dielectric layer  48 . The third layer  63  may include Ti and N. In an embodiment, the third layer  63  may include TiN. The third layer  63  may have a thickness of 0.7 to 2 nm. 
     Referring to  FIG. 38 , oxygen may be injected into the third layer  63  using an oxygen injection process. The third layer  63  may include Ti, O, and N. In an embodiment, the third layer  63  may include TiON. 
     During execution of the oxygen injection process, oxygen may be injected into the second layer  62 . The second layer  62  may include Ti, O, and N. In an embodiment, the second layer  62  may include TiON. 
     Referring to  FIG. 39 , a third mask  63 M may be formed to cover the third layer  63  within the first area LP, the second area SP, the third area RP, the fifth area SN and the sixth area LN. Using the third mask pattern  63 M as an etch mask, the third layer  63  may be etched, thereby exposing the second gate dielectric layer  49  within the fourth area RN. 
     Referring to  FIG. 40 , the third mask pattern  63 M may be removed. A fourth layer  64  may be formed on the third layer  63  and the second gate dielectric layer  49 . The fourth layer  64  may include Ti and N. In an embodiment, the fourth layer  64  may include TiN. The fourth layer  64  may have a thickness of 0.7 to 2 nm. 
     Referring to  FIG. 41 , a fourth mask pattern  64 M may be formed to cover the fourth layer  64  within the first area LP, the second area SP, the third area RP and the fourth area RN. Using the fourth mask pattern  64 M as an etch mask, the fourth layer  64  and the third layer  63  may be etched, thereby exposing the second gate dielectric layer  49  within the fifth area SN while exposing the first gate dielectric layer  48  within the sixth area LN. 
     Referring to  FIG. 42 , the fourth mask pattern  64 M may be removed, thereby exposing the fourth layer  64 . A fifth layer  65  may be formed on the fourth layer  64 , the second gate dielectric layer  49  and the first gate dielectric layer  48 . The fifth layer  65  may include TiAlC. The fifth layer  65  may have a thickness of 0.7 to 2 nm. 
     Referring to  FIG. 43 , a first gate conductive layer  72  may be formed on the fifth layer  65 . The first gate conductive layer  72  may include TiN. The thickness of the first gate conductive layer  72  may be greater than that of the fifth layer  65  by 2 to 1,000 times. 
     Again referring to  FIG. 1 , a second gate conductive layer  74  may be formed on the first gate conductive layer  72 . The second gate conductive layer  74  may include a metal, a metal nitride, a metal oxide, a metal silicide, conductive carbon, polysilicon, or a combination thereof. For example, the second gate conductive layer  74  may include a W layer. A gate capping layer  76  may be formed on the second gate conductive layer  74 . The gate capping layer  76  may include a silicon oxide, a silicon nitride, a silicon oxynitride, a silicon boron nitride (SiBN), a silicon carbon nitride (SiCN), low-k dielectrics, high-k dielectrics, or a combination thereof. For example, the gate capping layer  76  may include a silicon nitride. 
     In accordance with example embodiments of the disclosure, a first gate dielectric layer having high-k dielectrics containing La, a second gate dielectric layer having high-k dielectrics, and first to sixth work function layers having combinations of first to fifth layers may be provided. A combination of the first and second gate dielectric layers and the first to sixth work functions may constitute a plurality of transistors having different threshold voltages. Semiconductor devices having superior electrical characteristics while being advantageous in terms of mass production efficiency may be embodied. 
     While the embodiments of the disclosure have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the disclosure and without changing essential features thereof. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.