Patent Publication Number: US-9836075-B2

Title: Method and apparatus for generating a direct current bias

Description:
PRIORITY CLAIM 
     This application claims priority from Chinese Application for Patent No. 201310521075.X filed Oct. 25, 2013, the disclosure of which is incorporated by reference. 
     TECHNICAL FIELD 
     Embodiments of the present disclosure relate to the field of automobile engines, and more specifically, relate to an apparatus and method for generating a direct current (DC) bias. 
     BACKGROUND 
     Start-stop technology of an automobile engine is a new type of environmental friendly automobile technology that has been developed in recent years. According to this technology, when an idle speed condition is satisfied during the travelling of an automobile, the automobile engine will automatically stall so as not to operate. Conversely, when it is required to continue advancing, the automobile will quickly respond to a start command to quickly re-start the engine, thereby realizing an instant transition. Since the automobile engine does not work during each temporary stall, there is a reduction in fuel consumption and exhaust emission. 
     Generally, when the automobile engine is restarted after stalling, the power supply voltage of the system will drop to a lower value from a normal voltage within a short time, and then gradually rise to the normal voltage after a start condition is satisfied. This is shown in  FIG. 1 . As shown in  FIG. 1 , a normal power supply voltage of an automobile signal processor is usually 12V, for example, while during the start/stop operation of the automobile engine, the power supply voltage of the automobile signal processor will drop to a lowest voltage, e.g., 4.5V. In order to provide an automobile engine start/stop functionality, the automobile signal processor needs to work in a broad voltage range from the lowest voltage to the normal power supply voltage. Therefore, a DC voltage of a device will be biased to a lower value so as to support the broad operation range. However, a lower bias voltage will restrict swing of internal signals of the system, which means a signal to noise ratio will be lowered; in this way, signal quality during the normal operation will be degraded. 
     Therefore, there is a need in the art for an improved solution with respect to the automobile engine start/stop technology. 
     SUMMARY 
     In view of the above, the present disclosure provides a solution of generating a DC bias so as to overcome or alleviate at least a part of defects existing in the automobile engine start/stop operation in the prior art. 
     According to one aspect of the present disclosure, there is provided an apparatus for generating a DC bias. The apparatus may comprise: a voltage detector configured to detect a system power supply voltage and generate a trigger signal at an output end; a control signal generator configured to receive the trigger signal and generate a control signal for controlling generation of a DC bias; and a DC bias generator configured to receive the control signal at a control input end, and generate a DC bias based on the control signal, such that the DC bias with a first value is generated when the power supply voltage is a first voltage, while the DC bias with a second value is generated when the power supply voltage is a second voltage different from the first voltage, wherein the first value is different from the second value. 
     According to a second aspect of the present disclosure, there is provided a method for generating a direct current DC bias. The method may comprise: detecting a system power supply voltage and generating a trigger signal; generating a control signal for controlling generation of a DC bias based on the trigger signal; and generating the DC bias based on the control signal, such that the DC bias having a first value is generated when the power supply voltage is a first voltage, while the DC bias having a second value is generated when the power supply voltage is a second voltage different from the first voltage, wherein the first value is different from the second value. 
     With embodiments of the present disclosure, a dynamic DC bias may be realized, which may not only support a larger voltage range, but also significantly improve the signal to noise ratio of signals during normal operation. Moreover, in preferred embodiments, a smooth transition of DC bias may be implemented in a simple and cost-effective manner. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features, advantages, and other aspects of various embodiments of the present disclosure will become more apparent with reference to the detailed description in conjunction with the accompanying drawings, throughout which same reference numerals indicate same or like elements or components and wherein: 
         FIG. 1  schematically shows an exemplary diagram of a battery cranking curve in the worst case during automobile engine start/stop operations; 
         FIG. 2  schematically shows a diagram of a dynamic DC bias as provided in the present disclosure; 
         FIG. 3  schematically shows a block diagram of an apparatus for generating a DC bias according to an embodiment of the present disclosure; 
         FIG. 4  schematically shows a circuit diagram of an apparatus for generating a DC bias according to an embodiment of the present disclosure; 
         FIG. 5  schematically shows a circuit diagram of an apparatus for generating a DC bias according to another embodiment of the present disclosure; 
         FIG. 6  schematically shows a circuit diagram of an apparatus for generating a DC bias according to a further embodiment of the present disclosure; 
         FIG. 7  schematically shows a circuit diagram of an apparatus for generating a DC bias according to a still further embodiment of the present disclosure; 
         FIG. 8  schematically shows a circuit diagram of an alternative capacitance multiplier that may be used in an apparatus for generating a DC bias according to the present disclosure; 
         FIG. 9  schematically shows a signal timing diagram during start/stop operation of an automobile engine; 
         FIG. 10  schematically shows curve diagrams of a DC bias when adopting a single resistor and adopting a resistance multiplier; and 
         FIG. 11  schematically shows a flow chart of a method for generating a DC bias according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE DRAWINGS 
     Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be appreciated that these figures and description only relate to exemplary preferred embodiments. It should be noted that based on the following description, those skilled in the art will readily conceive alternative embodiments of the structures and methods disclosed herein, and these alternative embodiments may be used without departing from the idea of the disclosure as claimed. 
     It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and in turn practice the present disclosure, not intended for limiting the scope of the present disclosure in any manner. 
     Next,  FIGS. 2 to 11  will be referenced to describe a technical solution of generating a DC bias according to embodiments of the present disclosure. 
     First, reference is made to  FIG. 2 , in which a schematic diagram of a dynamic DC bias according to an embodiment of the present disclosure is schematically presented. As mentioned above, in order to support a broad work range, the device DC voltage is biased to a lower value, which causes a restriction on swing of internal signals of the system and in turn degrades the signal to noise ratio. In order to solve the above problem, the inventors envisage adopting a solution of dynamic DC bias, i.e., dynamically changing the DC bias for different power supply voltages. As shown in  FIG. 2 , according to this solution, under a normal operation state, i.e., when the power supply voltage of the vehicle signal processor is relatively high (e.g., 12V), the DC bias may be maintained at a higher value (e.g., 3.3V); while during the start/stop operation of the automobile engine, when the power supply voltage drops to a lower value (e.g., 4.5V), the DC bias is caused to have a lower value (e.g., 2.5V). Preferably, the switch process has a smooth transition, i.e., realizing a soft handover, which may reduce or eliminate potential sharp noise during switch and reduce the impact on the signal quality. In this manner, it not only supports a broad work range of the signal processor of an automobile, and meanwhile reduces the limit to swing of internal signals of the signal during the normal operation period as much as possible, thereby enhancing the signal to noise ratio and improving the signal quality. 
     To this end, there is provided a technical solution for generating DC bias for an automobile engine start/stop application.  FIG. 3  schematically shows a block diagram of an apparatus  300  for generating a DC bias according to an embodiment of the present disclosure. 
     As shown in  FIG. 3 , the apparatus  300  comprises a voltage detector  310 , a control signal generator  320 , and a DC bias generator  330 . The voltage detector  310  detects a system power supply voltage to detect an automobile start/stop operation and generate a trigger signal Vtrig. The detecting, for example, may be implemented by detecting change of a power supply voltage Vcc. The power supply voltage Vcc here is a power supply voltage provided by a battery of the automobile to the signal processor chip. During the normal operation, the power supply voltage Vcc is generally at a higher value 12V, while during the automobile engine start/stop operation, Vcc will drop to a lower value 4.5V. Therefore, by detecting change of Vcc, the automobile engine start/stop operation may be detected. Preferably, when Vcc drops from 12V to a predetermined threshold (e.g., 8V), it may be believed that the automobile engine start/stop operation is being performed. When detecting the automobile engine start/stop operation, the voltage detector may generate the trigger signal Vtrig. As will be detailed hereinafter, the Vtrig signal may be a voltage signal; however, for different circuit implementations, the values of the Vtrig signal during the start/stop operation might be somewhat different, which will be detailed infra. Besides, it may be understood that a certain amplitude relationship exists between the power supply voltage directly provided to the power supply voltage of the signal processor chip and an output voltage of the automobile battery; therefore, it is also possible to detect, for example, the start/stop operation by detecting an output voltage of the automobile battery. 
     The control signal generator  320  receives the trigger signal Vtrig, and generates a control signal for DC bias generation based on the trigger signal Vtrig, which control signal is for example a current control signal I 1 . The DC bias generator  330  receives control signal I 1  and generates the DC bias based on the control signal I 1 , such that a DC bias having a first value is generated when the power supply voltage is the first voltage, while a DC bias having a second value is generated when the power supply voltage is a second voltage lower than the first voltage, wherein the first value is greater than the second value. Wherein the first voltage, for example, is a power supply voltage under a normal operation state, e.g., 12V, while the second voltage, for example, is the lowest power supply voltage 4.5V during the automobile engine start/stop operation. The first value, for example, is 3.3V, and the second value, for example, is 2.5V. 
       FIG. 4  schematically illustrates a circuit diagram of an apparatus for generating a DC bias according to an embodiment of the present disclosure. As shown in  FIG. 4 , the power supply voltage Vcc is input into the voltage detector  310 . The voltage detector  310  generates a trigger signal Vtrig based on the power supply voltage signal Vcc. For example, during the automobile engine start/stop operation, a Vtrig signal of high voltage, for example, is generated, while during the normal operation of the automobile engine, the Vtrig signal is kept low. The voltage detector  310  may comprise various circuit structures such as a threshold comparator or a mean value detector, and the like, which may be implemented by those skilled in the art in a plurality of manners based on the description herein, which will not be detailed. The detector  310  may be powered from a supply voltage Vdd. 
     Since the Vtrig signal is changed to a high voltage, a voltage drop exists at two ends of an inductor L; therefore, the current will flow through the inductor L; besides, the current gradually rises to the maximum current from zero within the coil transition time. Namely, the inductor L will smoothly increase the current flowing therethrough to the maximum current value. The current flowing through the inductor L may be mirrored into the DC bias generation circuit  330  through a mirror circuit, for using as the control signal I 1  for controlling generation of the DC bias. 
     As shown in  FIG. 4 , the DC bias generator  330  comprises an amplifier A 2 , a resistor R 1 , and a resistor R 2 , wherein the resistor R 1  and the resistor R 2  are connected in series between the ground and an output end of the amplifier A 2 , while the middle node between the resistor R 1  and the resistor R 2  is connected to a negative input end of the amplifier A 2 . The negative input end further receives the control signal I 1  from the control signal generator  320 ′. Besides, the positive input end of the amplifier receives an input signal Vbg. The input signal Vbg is a band gap voltage inside the signal processor. 
     Vcc is a high voltage when the engine works normally, while the Vtrig is kept at a low voltage. Therefore, no current flows through the inductor L. At this point, the control current I 1  injected into the DC bias generator is also 0. Therefore, the DC bias at the output end of the amplifier A 2  may be expressed as:
 
 Vdc=Vbg *(1+ R 2/ R 1)
 
wherein Vdc indicates a voltage value of a DC bias, Vbg indicates the voltage value of the band gap voltage inputted at the positive input end of the amplifier, R 1  indicates a resistance value of the resistor R 1 , and R 2  indicates the resistance value of the resistor R 2 .
 
     During the automobile engine start/stop operation, when the Vcc changes to a low voltage, Vtrig changes to a high voltage. Hence, the current flows through the inductor L, which means the mirror current I 1  is injected into the amplifier A 2 . Therefore, at this point, the DC bias Vdc at the output end of the amplifier may be represented as:
 
 Vdc=Vbg *(1+ R 2/ R 1)− I 1* R 2
 
     Therefore, during the automobile engine start/stop operation, a trigger signal that is a high voltage signal is generated when the power supply voltage drops, and a control signal I 1  is generated based on the high voltage signal, such that the DC bias during the start/stop operation drops to a value lower than the DC bias during normal operation. In this way, when the power supply voltage resumes the normal operation, the Vtrig signal will become a low voltage signal; thus, the control current I 1  gradually decreases to zero, and finally, the DC bias is caused to resume a higher DC bias. Accordingly, a dynamic DC bias may be realized. Besides, use of the inductor L will cause the switch of the DC bias between a higher value and a lower value much smoother, thereby realizing a better audio effect. 
     The dynamic DC bias may also be implemented based on an equivalent inductive circuit. Reference is made to  FIG. 5 , which schematically illustrates a circuit diagram of an apparatus for generating a DC bias for automobile engine operations according to another embodiment of the present disclosure. In the circuit of  FIG. 5 , the voltage detector  310  and the DC bias generator  330  are identical to those in  FIG. 4 , which will not be detailed herein. Different from the inductor-based implementation as shown in  FIG. 4 , the control signal generator  320 ″ comprises an equivalent inductor L comprising a resistor Ro, a capacitor C 1 , a NMOS transistor M 1 .  FIG. 5  further shows a current mirror circuit. As shown in  FIG. 5 , an output end of the voltage detector  310  is connected to one end of the resistor Ro, and the other end of the resistor Ro is connected to the capacitor C 1 , while the other end of the capacitor C 1  is grounded. The end of the resistor Ro connected to the capacitor C 1  is connected to a gate of the transistor M 1 . A source of the transistor M 1  is grounded, and its drain is connected to a current input end of the current mirror, and the mirror output end of the current mirror is connected to a negative input end of the amplifier A 2 . In the circuit shown in  FIG. 5 , the resistor Ro, the capacitor C 1 , and the transistor M 1  form an equivalent inductive circuit, and the current flowing through M 1  is mirrored into I 1  by means of a current mirror. The current signal I 1 , as a control signal, is injected into a negative input end of the amplifier A 2 . During normal operation, the Vcc is a high-voltage signal, the Vtrig is a low-voltage signal (e.g., 0V); at this point, the transistor M 1  is turned off, and no current flows through the transistor M 1 . Therefore, the control signal I 1  is also 0. However, when Vcc is changed to a low voltage, the Vtrig signal changes to a high voltage signal (e.g., Vdd, 4.2V). At this point, C 1  is electrically charged and thus the voltage Vx at node X rises gradually, which will cause turn-on of the transistor M 1 . In this way, due to the fact the drain of the transistor M 1  is connected to the current input of the current mirror current, the current flowing through the transistor M 1  will be mirrored into current I 1  at the mirror current output end, which current I 1  is then injected to the amplifier A 2 . 
     However, in order to realize a current switch within a time of milliseconds (e.g., 2 ms), a larger inductor is usually required. This means a larger capacitor and resistor are also needed in the RC-based implementation. However, use of larger resistor and larger capacitor will occupy a larger area on the circuit. Besides, whether current I 1  is accurate also depends on the Vtrig signal and the transistor M 1 . 
     To this end,  FIG. 6  further provides a circuit diagram of an apparatus for generating a DC bias according to a further embodiment of the present disclosure. As shown in  FIG. 6 , in the control signal generator  320 ′″ as shown, both a resistance-multiplier-circuit and a source couple pair structure are employed. In  FIG. 6 , the resistance multiplier circuit comprises a resistor Ro and an NMOS transistor M 3  and a PMOS transistor M 4 . One end of the resistor Ro is connected to the output end of the voltage detector  310 ; the other end thereof is connected to sources the transistor M 3  and of the transistor M 4 ; the transistor M 3  is connected to the drain of the transistor M 4  and is further connected to the capacitor C 1 . The other end of the capacitor C 1  is connected to a tail current source Iss. The other end of the tail current source Iss is grounded. Therefore, in the circuit diagram of  FIG. 6 , the resistor Ro and the transistor M 3  constitute an N-type common source stage with source degeneration, while the resistor Ro and the transistor M 4  form a P-type common source stage with source degeneration. 
     The circuit of  FIG. 6  also comprises an NMOS transistor M 1 , a gate of which is connected to a middle node between the capacitor and the multiplication resistor circuit. However, the drain of the transistor is connected to the internal power supply voltage VDD of the automobile signal processor, and its source is connected to the tail current source Iss. In addition to the transistor M 1 , there further comprises a NMOS transistor M 2 . The sources of the transistor M 2  and the transistor M 1  are connected together. The gate and drain of the transistor M 2  are connected together and connected to an input end of the current mirror through the diode D 1 . The gates of the transistors M 3  and M 4  are commonly connected to the gate of the transistor M 2 . Therefore, in the circuit diagram of  FIG. 6 , transistors M 1  and M 2  jointly form a source couple pair. Such circuit structure as shown in  FIG. 6  can ensure that with the change of voltage difference at points X, Y, the current of the tail current source Iss finally flows through M 1  or M 2  in an alternative manner. 
       FIG. 7  further schematically shows a circuit diagram of an apparatus for generating a DC bias according to a further embodiment of the present disclosure. Compared with the circuit shown in  FIG. 6 , the control signal generator  320 ″″ comprises a capacitance multiplier circuit, rather than a single capacitor. As shown in  FIG. 7 , the capacitance multiplier circuit comprises a resistor Rx, a resistor N*Rx, A 1 , and C 1 . One end of the resistor Rx is connected to the drains of the transistors M 3  and M 4 , while the other end is connected to the output end of the amplifier A 1  (e.g., OTA). Similarly, one end of the resistor N*Rx is also connected to the drains of the transistors M 3  and M 4  and the other end is connected to the capacitor C 1  and the input end of the amplifier A 1 . The resistor Rx, resistor N*Rx, A 1  and C 1  forms an equivalent capacitive circuit with an equivalent capacitance value of (N+1)*C 1 . 
     Besides the capacitance multiplier circuit used in  FIG. 7 , another type of capacitance multiplier circuit may also be adopted. For example,  FIG. 8  further schematically shows a circuit diagram of an alternative capacitance multiplier that may be used by the apparatus for generating DC bias. As illustrated, different from  FIG. 7 , the capacitance multiplier circuit is a transistor-based current type capacitance multiplier. The capacitance multiplier circuit comprises a capacitor C 1 , a circuit source Is and two NMOS transistors Mc and Mc′, wherein the transistors Mc and Mc′ have width-length ratios of w/l and N*w/l, respectively. The gate and source of the transistor Mc are connected to the gate and source of the transistor Mc′, respectively. The drain and source of the transistor Mc are also connected together and are connected to the current source Is. The other end of the current source Is is connected to the power supply voltage VDD inside the system. The gate and drain of the transistor Mc′ are connected to two ends of the capacitor C 1 . Through such a capacitive equivalent circuit, an equivalent capacitance value of (N+1)*C 1  may also be provided. In this way, a smaller capacitance may be utilized to realize a larger transition time. However, it should be noted that those skilled in the art, based on the description here, may also envisage several capacitance multiplier circuits in other structures, and the present invention is not limited to the embodiments as shown. 
     Next,  FIG. 9  will be referenced to describe in detail the work principles of the circuits of  FIGS. 6 and 7 . As shown in  FIG. 9 , when the automobile start/stop operation starts, the power supply voltage Vcc shifts from a high voltage (12V) to a low voltage (4.5V), which will trigger a threshold window. This window, for example, may be defined through a predetermined voltage threshold (such as 8V) or a predetermined percentage value. Once the threshold window is triggered, it will generate a trigger signal, i.e., the Vtrig signal will change from a high voltage (e.g., VDD) to a low voltage (e.g., 0V). At this point, in the circuit diagram as shown in  FIGS. 6 and 7 , the transistor M 4  will be turned off, and the transistor M 3  will be turned on. Thus, the voltage Vx at the connection point (i.e., X point) of drains of the transistors M 3  and M 4  will flow through the transistor M 3 . 
     The resistor Ro and the equivalent capacitance circuit are discharged. The transition time constant τ1 is equal to:
 
τ1=( gm 3* ro 3* Ro )*(( N+ 1)* C 1)
 
wherein gm 3  indicates the transcondutance of the transistor M 3 , and ro 3  indicates the conductive resistance of the transistor M 3 .
 
     In the circuit diagram as shown in  FIG. 7 , since the transcondutance multiplier circuit and the capacitance multiplier circuit prolong the transition time, such that even a smaller resistor Ro and a smaller capacitor C 1  are used, it can also realize a greater transition time constant, thereby realizing smooth transition. 
     Therefore, Vx will be smoothly discharged to a lower value within the transition time. Meanwhile, with gradual discharge of Vx, the current of the tail current source Iss will gradually flow through the transistor M 2 , and the voltage V Y  at the drain (point Y) of the transistor M 2  will gradually drop. In this way, the voltage difference between V Y  and Vtrig will gradually decrease, which will be advantageous to prolong the discharge time. Finally, since the final voltage value of the Vx after discharging is low, the transistor M 1  is turned off, and the tail current Iss will not flow through the transistor M 1 . In this way, the current of the tail current source Iss will completely flow through the transistor M 2 , and then flow through the diode D 1 . Meanwhile, the current mirror circuit will mirror the current flowing through the diode D 1  into I 1 , and inject I 1  into the negative input end of the amplifier A 2 . Therefore, the output Vdc of the amplifier A 2  may be represented as Vdc=Vbg*(1+R 2 /R 1 )−I 1 *R 2 . Thus, the DC bias may change from a higher value to a lower value, as shown in  FIG. 9 . 
     On the other hand, upon the end of the start/stop operation, the Vcc will rise and in turn trigger the threshold window. This means Vtrig will change from a low voltage (e.g., 0V) to a high voltage (e.g., V DD ). Since Vtrig is a high voltage, the transistor M 3  will be turned off, and the transistor M 4  will be turned on. Therefore, Vtrig will charge point X through the transistor M 4 , resistor Ro, and capacitance multiplier, which means the voltage Vx at point X will rise gradually. At this point, the transition time constant is:
 
τ2=( gm 4* ro 4* Ro )*(( N+ 1)* C 1)
 
     wherein gm 4  denotes transconductance of the transistor M 4 , ro 4  denotes the conductive resistance of the transistor M 4 . Likewise, because the resistance multiplier circuit and capacitance multiplier circuit are used to prolong time, even if a smaller resistor Ro and the capacitor C 1  are used, it may also achieve a larger transition time constant, thereby realizing a smooth transition. 
     Meanwhile, with gradual charge of Vx, the current of the tail current source Iss will gradually flow out of the transistor M 2 , and the voltage V Y  at the drain (point Y) of the transistor M 2  will rise gradually. In this way, the voltage difference between Vtrig and V Y  will decrease gradually, which will be advantageous to prolong the charge time. When the Vx is charged to the final value V DD , due to use of the diode D 1 , it may be ensured that Vx voltage is greater than VY. Therefore, all tail currents will flow through M 1 , and no current will flow through M 2 . Since no tail current flows through the diode D 1 , the current I 1  mirrored by the current mirror will be 0, i.e., no current is injected into a negative input end of the comparison amplifier A 2 . Meanwhile, the voltage V Y  at Y will rise. In this way, the output Vdc of the comparison amplifier turns again to Vdc=Vbg*(1+R 2 /R 1 ), as shown in  FIG. 9 . 
     Therefore, in the present invention, alternative turn-on and turn-off of M 3  and M 4  enables the tail current to alternatively flow through M 1  and M 2 , such that the DC bias may be dynamically adjusted at the start of start/stop and at the end of start/stop. 
       FIG. 10  further schematically shows the transition time of a DC bias in the case of employing a single resistor Ro and employing a resistance multiplier. As shown in  FIG. 10 , a circuit employing the resistance multiplier can effectively prolong the transition time, such that the transition of the DC bias voltage will become smoother, rather than a steep change like using a single resistor Ro. 
     Based on the present disclosure, a dynamic DC bias may be realized, which may not only support a larger voltage range but also significantly improve the signal to noise ratio of the signal during normal operation. According to referred embodiments of the present invention, smooth transition upon DC bias adjustment may also be realized. Additionally, it provides a simple and cost-effective implementation manner. 
     A method for generating a direct current DC bias will now be described with reference to  FIG. 11 . As shown in  FIG. 11 , first, at step S 1101 , a system power supply voltage is measured and a trigger signal at an output end is generated. Next, at step S 1102 , a control signal for controlling generation of the DC bias is generated based on the trigger signal. Then, at step S 1103 , the DC bias is dynamically generated based on the control signal, namely, when the power supply voltage is a first voltage, the DC bias having a first value is generated; while when the power supply voltage is a second voltage different from the first voltage, the DC bias having a second value is generated, wherein the first value is different from the second value. Preferably, the DC bias transits smoothly between the first value and the second value. 
     According to one embodiment of the present disclosure, the generating a control signal for controlling generation of the DC bias may comprise: generating a current signal through an inductive circuit based on the trigger signal, and generating a mirror signal of the current signal by means of a mirror circuit as the control signal. The inductive circuit may comprise an inductor or an equivalent inductive circuit. The equivalent inductive circuit may comprise a resistive circuit and a capacitive circuit. The resistive circuit may comprise a resistance multiplier for achieving equivalent multiplication resistance. The capacitive circuit may also comprise a capacitance multiplier for achieving equivalent multiplication capacitance. 
     It should be noted that the specific operations of the method are substantially similar to the operations of the circuits as mentioned above. Therefore, for specific details about the method, reference is made to the description of the apparatus with reference to  FIGS. 2 to 10 , which will not be detailed here. 
     It should be noted that the embodiments have been described above with reference to specific numerical values. However, the embodiments are not limited thereto. In fact, the numerical values as quoted in relevant description would change in different applications. 
     Besides, it should be noted that the embodiments have been described in detail with regard to generation of the DC bias during the automobile engine start/stop operation. However, the disclosure is not limited thereto. Instead, the embodiments may be applied to any other similar applications in which a fixed DC bias might cause degradation of signal quality or other issues. 
     Besides, it should be noted that the embodiments are directed to a flexible solution for generating a DC bias. Although it is described that a higher DC bias is set when the power supply voltage is of a higher value and a lower DC bias is set when the power supply voltage is relatively low, in different applications, there might exist different situations, i.e., a lower bias is set for a higher power supply voltage, and a higher bias is set for a lower power supply voltage. 
     It should also be noted that the exemplary circuit diagram as schematically shown hereinabove describes the structure and operation of various circuit diagrams. However, the embodiments are not limited thereto. Without departing from the true spirit of the present disclosure, those skilled in the art may make various kinds of additions, deletions and improvements to the circuit structure. 
     Besides, those skilled in the art should understand, the descriptions in the present description are only illustrative, and should not be construed as limitative. The scope of the present disclosure is only limited by the appended claims.