Patent Publication Number: US-11641734-B2

Title: Method of forming a semiconductor structure having a gate structure electrically connected to a word line

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a Divisional application of the U.S. application Ser. No. 16/673,975, filed on Nov. 5, 2019, the entirety of which is incorporated by reference herein in their entireties. 
    
    
     BACKGROUND 
     Technical Field 
     The present disclosure relates to a method of forming a semiconductor structure. 
     Description of Related Art 
     With the rapid growth of electronic industry, the development of semiconductor devices has achieved high performance and miniaturization. Generally, a transistor of a semiconductor structure may use an oxide semiconductor layer as a channel because of its off-state leakage current characteristics. However, a high-resistance metal-oxide layer is formed between the oxide semiconductor layer and a metal structure, which may cause an increase in the contact resistance. Thus, the performance of the semiconductor structure may be affected. 
     SUMMARY 
     According to one embodiment of the present disclosure, a method of forming a semiconductor structure includes the following steps. A capacitor is formed on a substrate. A recess is formed in the capacitor. A drain region is formed in the recess. A word line is formed on the drain region. A gate structure is formed on the drain region, and the gate structure is electrically connected to the word line. A first bit line is formed on the gate structure, such that the first bit line servers as a source region. 
     In some embodiments of the present disclosure, the method further includes the following steps. A second bit line is formed when forming the first bit line. A first metal structure and a second metal structure are formed respectively on the word line and the second bit line. 
     In some embodiments of the present disclosure, the method further includes forming a first metal contact on the substrate before forming the word line. 
     In some embodiments of the present disclosure, forming the first metal contact is such that a top surface of the first metal contact is at same horizontal level as a top surface of the drain region. 
     In some embodiments of the present disclosure, forming a second metal contact on the first metal contact after forming the first and second bit lines. 
     In some embodiments of the present disclosure, forming the second metal contact and forming the first metal structure and the second metal structure are performed by using one deposition process. 
     In the aforementioned embodiments, since the gate structure is disposed on the drain region and has the portion in the word line and the first bit line is disposed on the gate structure to serve as the source region, low-resistance of the semiconductor structure can be achieved. As a result, the performance of the semiconductor structure can be improved. 
     It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows: 
         FIG.  1    is a cross-sectional view of a semiconductor structure in accordance with one embodiment of the present disclosure; and 
         FIG.  2    to  FIG.  10    are cross-sectional views of a method of forming a semiconductor structure at various stages in accordance with one embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
       FIG.  1    is a cross-sectional view of a semiconductor structure  100  in accordance with one embodiment of the present disclosure. Referring to  FIG.  1   , a semiconductor structure  100  includes a substrate  110 , a drain region  120 , a word line  130 , a gate structure  140 , and a first bit line  150 . The drain region  120  is disposed on the substrate  110 . The word line  130  is disposed on the drain region  120 . The gate structure  140  is disposed on the drain region  120  and has a portion in the word line  130 . The first bit line  150  is disposed on the gate structure  140  to serve as a source region. 
     In greater detail, the semiconductor structure  100  includes a gate dielectric layer  141  disposed on the drain region  120 . The gate dielectric layer  141  surrounds the gate structure  140 . The gate structure  140  is in contact with the drain region  120 . The word line  130  has a portion between the drain region  120  and the first bit line  150 . 
     In the present embodiments, the drain region  120 , the gate structure  140 , and the first bit line (source region)  150  may serve as a vertical transistor. In greater details, a lengthwise direction of the first bit line (source region)  150  and a lengthwise direction of the drain region  120  are perpendicular to a lengthwise direction of the gate structure  140 . In other words, the lengthwise direction of the gate structure  140  is perpendicular to a lengthwise direction of the substrate  110 . 
     In some embodiments, the semiconductor structure  100  further includes a metal layer  160 , a first isolation layer  162 , and a capacitor  170  disposed on the substrate  110 . The metal layer  160  is disposed between the capacitor  170  and the substrate  110 . The first isolation layer  162  is in contact with the metal layer  160  and the capacitor  170 . The drain region  120  is embedded in the capacitor  170 . In greater details, the capacitor  170  includes a semiconductor material  172  and a nitride-oxide-nitride structure  174  surrounding the semiconductor material  172 . The drain region  120  is aligned with the semiconductor material  172  of the capacitor  170 . In some embodiments, a top surface  170   t  of the capacitor  170  is at same horizontal level as a top surface  120   t  of the drain region  120 . 
     In some embodiments, the metal layer  160  may be made of tungsten (W). In some embodiments, the semiconductor material  172  may include silicon. The nitride-oxide-nitride structure  174  may include a titanium nitride layer  175 , zirconium oxide layer  176 , and titanium nitride layer  177 . 
     In some embodiments, the semiconductor structure  100  further includes a first metal structure  180 , a second bit line  152 , and a second metal structure  182 . The first metal structure  180  disposed on the word line  130 . The first metal structure  180  is disposed between the first bit line  150  and the second bit line  152 . The second metal structure  182  is disposed on the second bit line  152 . In greater details, an adhesion layer  181  is disposed between the first metal structure  180  and the word line  130 , and another adhesion layer  183  is disposed between the second metal structure  182  and the second bit line  152 . In other words, the adhesion layers  181  and  183  are in contact with the word line  130  and the second bit line  152 , respectively. The adhesion layers  181  and  183  can adhere the first metal structure  180  and the second metal structure  182 , respectively. 
     In some embodiments, a top surface  180   t  of the first metal structure  180  is at same horizontal level as a top surface  182   t  of the second metal structure  182 . In some embodiments, a bottom surface  180   b  of the first metal structure  180  is below a bottom surface  182   b  of the second metal structure  182 . 
     In some embodiments, the first metal structure  180  and the second metal structure  182  may be made of same materials. For example, the first metal structure  180  and the second metal structure  182  may be made of copper (Cu). 
     In some embodiments, the semiconductor structure  100  further includes a first metal contact  190  and the second metal contact  192 . The first metal contact  190  is disposed on the substrate  110 , and the second metal contact  192  is disposed on the first metal contact  190 . In greater details, an adhesion layer  191  is disposed between the first metal contact  190  and the metal layer  160 , and another adhesion layer  193  is disposed between the second metal contact  192  and the first metal contact  190 . In other words, the adhesion layers  191  and  193  are in contact with the metal layer  160  and the first metal contact  190 , respectively. The adhesion layers  191  and  193  can adhere the first metal contact  190  and the second metal contact  192 , respectively. 
     In some embodiments, the second metal contact  192  has a top portion  194  and the bottom portion  196  connected to the top portion  194 . A width of the top portion  194  is larger than a width of the bottom portion  196 . In some embodiments, the width of the bottom portion  196  of the second metal contact  192  is larger than a width of the first metal contact  190 . 
     In some embodiments, a top surface  190   t  of the first metal contact  190  is at same horizontal level as the top surface  120   t  of the drain region  120 . In greater details, the top surface  190   t  of the first metal contact  190 , the top surface  120   t  of the drain region  120 , and the top surface  170   t  of the capacitor  170  are at same horizontal level. 
     In some embodiments, a top surface  192   t  of the second metal contact  192  is at same horizontal level as the top surface  180   t  of the first metal structure  180 . In greater details, the top surface  192   t  of the second metal contact  192 , the top surface  180   t  of the first metal structure  180 , and the top surface  182   t  of the second metal structure  182  are at same horizontal level. 
     In some embodiments, the first metal contact  190  and the second metal contact  192  may be made of different materials. For example, the first metal contact  190  may be made of tungsten (W), while the second metal contact  192  may be made of copper (Cu). Since the first metal contact  190  and the second metal contact  192  are made of different materials, the resistance of the semiconductor structure  100  can be decreased. 
     In some embodiments, the semiconductor structure  100  further includes a first dielectric structure  200  and a second dielectric structure  210 . The first dielectric structure  200  is disposed on the substrate  110  and surrounds the drain region  120 . The second dielectric structure  210  is disposed on the first dielectric structure  200  and surrounds the first bit line  150 . In greater details, the first dielectric structure  200  further surrounds the capacitor  170  and the first metal contact  190 . The second dielectric structure  210  further surrounds the word line  130 , the gate structure  140 , the second bit line  152 , the first metal structure  180 , the second metal structure  182 , and the second metal contact  192 . 
     In some embodiments, the first dielectric structure  200  and the second dielectric structure  210  may be made of same materials. For example, the first dielectric structure  200  and the second dielectric structure  210  may be made of oxide. 
     In some embodiments, the semiconductor structure  100  further includes a second isolation layer  202  and a third isolation layer  204  disposed on the first isolation layer  162 . The first dielectric structure  200  and the second dielectric structure  210  are separated apart by the second isolation layer  202 . The third isolation layer  204  is disposed on the first metal structure  180 , the second metal structure  182 , and the second metal contact  192 . In some embodiments, the third isolation layer  204  is in contact with the first metal structure  180 , the second metal structure  182 , and the second metal contact  192 . 
     In some embodiments, the first isolation layer  162 , the second isolation layer  202 , and the third isolation layer  204  may be made of same material. For example, the first isolation layer  162 , the second isolation layer  202 , and the third isolation layer  204  may be made of silicon oxide, silicon nitride or silicon oxynitride, or other suitable materials. 
       FIG.  2    to  FIG.  10    are cross-sectional views of a method of forming a semiconductor structure at various stages in accordance with one embodiment of the present disclosure. 
     Referring to  FIG.  2   , the capacitor  170  is formed on the substrate  110 . In greater details, the metal layer  160 , the first isolation layer  162 , the first dielectric structure  200 , and the second isolation layer  202  are formed in sequence on the substrate  110 . Then, an etching process may be performed to form an opening in the metal layer  160 , the first isolation layer  162 , the first dielectric structure  200 , and the second isolation layer  202 , and the semiconductor material  172  and the nitride-oxide-nitride structure  174  may be filled in the opening to form the capacitor  170 . In some embodiments, a top surface of the semiconductor material  172  is at same horizontal level of a top surface of the nitride-oxide-nitride structure  174 . 
     In some embodiments, the first dielectric structure  200  may be made of oxide or other suitable dielectric materials. In some embodiments, the first dielectric structure  200  may be formed by chemical vapor deposition (CVD), ALD, or other suitable process. 
     In some embodiments, the first isolation layer  162  and the second isolation layer  202  may be made of same material. For example, the first isolation layer  162  and the second isolation layer  202  may be made of silicon nitride. In some embodiments, the first isolation layer  162  and the second isolation layer  202  may be formed by chemical vapor deposition (CVD), ALD, or other suitable process. 
     Referring to  FIG.  3   , after the capacitor  170  is formed on the substrate  110 , a recess R 1  is formed in the capacitor  170 . In greater details, the semiconductor material  172  is etched to form the recess R 1 , such that the top surface of the semiconductor material  172  is below the top surface of the nitride-oxide-nitride structure  174 . 
     Referring to  FIG.  3    and  FIG.  4   , after the recess R 1  is formed in the capacitor  170 , the drain region  120  is formed in the recess R 1 . Since the recess R 1  is formed by etching semiconductor material  172  of the capacitor  170 , the drain region  120  is formed in self-aligned in the recess R 1 . The drain region  120  is embedded in the capacitor  170 . In some embodiments, the drain region  120  may made of an indium tin oxide (ITO), or other suitable conductive materials. 
     Referring to  FIG.  5   , after the drain region  120  is formed, a recess R 2  is formed in the metal layer  160 , the first isolation layer  162 , the first dielectric structure  200 , and the second isolation layer  202 . In greater details, the metal layer  160 , the first isolation layer  162 , the first dielectric structure  200 , and the second isolation layer  202  are etched, such that the metal layer  160  is exposed. 
     After the recess R 2  is formed, the adhesive layer  191  is formed on a sidewall and a bottom surface of the recess R 2 . The adhesive layer  191  further covers the second isolation layer  202  and the drain region  120 . In some embodiments, a bottom surface of the adhesive layer  191  is at same horizontal level as a bottom surface of the capacitor  170 . In some embodiments, the adhesive layer  191  may made of titanium nitride. 
     Referring to  FIG.  5    and  FIG.  6   , after the adhesive layer  191  is formed, the first metal contact  190  is formed on the adhesive layer  191 . After the first metal contact  190  is formed, a planarization operation is performed, such as a chemical mechanical polishing (CMP) operation, to remove a portion of the adhesive layer  191 . As a result, the top surface  190   t  of the first metal contact  190  is at same horizontal level as the top surface  120   t  of the drain region  120 . 
     In some embodiments, the adhesion layer  191  is in contact with the metal layer  160  and the first metal contact  190 . The adhesion layer  191  can adhere the first metal contact  190 . In greater details, the adhesion layer  191  enables the first metal contact  190  to have improved filling characteristics in the recess R 2 , and therefore results in forming the first metal contact  190  without leaving unfilled voids therein. 
     Referring to  FIG.  7   , after the first metal contact  190  is formed, the second dielectric structure  210  is formed on the drain region  120  and the first metal contact  190 . In other words, the second dielectric structure  210  covers the drain region  120 , the first metal contact  190 , and the second isolation layer  202 . In some embodiments, the second dielectric structure  210  is made of oxide or other suitable dielectric materials. In some embodiments, the second dielectric structure  210  is formed by chemical vapor deposition (CVD), ALD, or other suitable process. 
     Referring to  FIG.  8   , after the second dielectric structure  210  is formed, the word line  130  is formed on the drain region  120 . After the word line  130  is formed, the gate structure  140  is formed on the drain region  120 . The gate structure  140  is electrically connected to the word line  130 . 
     In some embodiments, after the word line  130  and the gate structure  140  formed, a planarization operation is performed, such as a chemical mechanical polishing (CMP) operation, to remove a portion of the second dielectric structure  210 . As a result, the gate structure  140  and the gate dielectric layer  141  are exposed. 
     In some embodiments, the gate structure  140  may be made of indium gallium zinc oxide (IGZO), or other suitable conductive metals. For example, the gate structure  140  is an IGZO film which is beneficial to decrease the rate of leakage. In some embodiments, the gate dielectric layer  141  may be made of silicon oxide, or other suitable dielectric materials. 
     Referring to  FIG.  9   , after the gate structure  140  is formed on the drain region  120 , the first bit line  150  is formed on the gate structure  140 , such that the first bit line  150  serve as the source region. In greater details, the second bit line  152  is formed when the first bit line  150  is formed. The method of forming the first bit line  150  and the second bit line  152  may include forming a conductive material layer and then patterning the conductive material layer with a photolithography process. 
     In some embodiments, the first bit line  150  and the second bit line  152  may made of an indium tin oxide (ITO), or other suitable conductive materials. In some embodiments, the drain region  120 , the first bit line  150 , and the second bit line  152  may made of same materials. 
     Referring to  FIG.  9    and  FIG.  10   , after the first bit line  150  and the second bit line  152  are formed, another second dielectric structure  210  is formed on the second dielectric structure  210  of  FIG.  9   . The second dielectric structure  210  of  FIG.  10    and the second dielectric structure  210  of  FIG.  9    may be the same. In other words, the second dielectric structure  210  of  FIG.  10    and the second dielectric structure  210  of  FIG.  9    may be made of same materials. For clarify, a dash line in  FIG.  10    is to illustrate that there is no interface in the second dielectric structure  210 . 
     As shown in  FIG.  10   , openings O 1 , O 2 , and O 3  are formed in the second dielectric structure  210 . In greater details, the opening O 1  expose the word line  130 , the opening O 2  expose the second bit line  152 , and the opening O 3  exposes the first metal contact  190 . 
     After the openings O 1 , O 2 , and O 3  are formed in the second dielectric structure  210 , the first metal structure  180 , the second metal structure  182  and the second metal contact  192  are formed in openings O 1 , O 2 , and O 3 , respectively. In greater details, the adhesive layer  181  is formed on a sidewall and a bottom surface of the opening O 1 , and then the first metal structure  180  is formed on the adhesive layer  181 . The adhesive layer  183  is formed on a sidewall and a bottom surface of the opening O 2 , and then the second metal structure  182  is formed on the adhesive layer  183 . The adhesive layer  193  is formed on a sidewall and a bottom surface of the opening O 3 , and then the second metal contact  192  is formed on the adhesive layer  193 . As a result, the semiconductor structure  100  as shown in  FIG.  1    can be obtained. 
     In some embodiments, forming the second metal contact  192  and forming the first metal structure  180  and the second metal structure  182  are performed by using one deposition process. In some embodiments, forming first metal contact  190  and forming the second metal contact  192  are performed by using different deposition processes, thermal budget can be reduced after the gate structure  140  is formed. 
     In some embodiments, the adhesive layers  181 ,  183 , and  193  may made of same materials, such as tantalum (Ta). In some embodiments, the first metal structure  180 , the second metal structure  182 , and the second metal contact  192  may made of same materials, such as copper (Cu). 
     In summary, the semiconductor structure includes the substrate, the drain region, the word line, the gate structure, and the first bit line. The gate structure is disposed on the drain region and has the portion in the word line, and the first bit line is disposed on the gate structure to serve as the source region. By using the semiconductor structure, low-resistance of the semiconductor structure can be achieved, and the performance of the semiconductor structure can be improved. 
     Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.