Patent Publication Number: US-11640976-B2

Title: Semiconductor memory device having a channel layer

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2020-0122210 filed on Sep. 22, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein. 
     BACKGROUND 
     1. Technical Field 
     Various embodiments of the invention relate generally to an electronic device, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device. 
     2. Related Art 
     The increase in integration density of two-dimensional memory devices in which memory cells are formed in a single layer over a substrate has recently been limited. Thus, three-dimensional memory devices have been proposed in which memory cells are stacked in a vertical direction over a substrate. In addition, various structures and manufacturing methods have been developed to improve the operational reliability of three-dimensional memory devices. 
     SUMMARY 
     According to an embodiment, a semiconductor device may include a stacked structure with first conductive layers and insulating layers that are stacked alternately with each other, second conductive layers located on the stacked structure, first openings passing through the second conductive layers and the stacked structure and having a first width, second conductive patterns formed in the first openings and located on the stacked structure to be electrically coupled to the second conductive layers, data storage patterns formed in the first openings and located under the second conductive patterns, and channel layers formed in the data storage patterns and the second conductive patterns. 
     According to an embodiment, a semiconductor device may include a stacked structure including word lines and insulating layers stacked alternately with each other, wherein the word lines include first openings having a first width, select lines located on the stacked structure and including second openings having a second width less than the first width, an isolation insulating pattern located on the stacked structure and insulating the select lines from each other, data storage patterns formed in the first openings and located under the select lines, and channel layers formed in the data storage patterns and extending to the second openings. 
     According to an embodiment, a method of manufacturing a semiconductor device may include forming a stacked structure including first material layers and second material layers stacked alternately with each other, forming a conductive layer on the stacked structure, forming a sacrificial layer on the conductive layer, forming a first opening through the sacrificial layer, the conductive layer and the stacked structure, forming a data storage layer in the first opening, forming a channel structure in the data storage layer, removing the sacrificial layer so as to protrude the channel structure above the conductive layer, forming a second opening between the channel structure and the conductive layer by etching the data storage layer, forming a conductive pattern in the second opening, and forming an isolation insulating pattern through the conductive pattern. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS.  1 A to  1 E  are diagrams illustrating the structure of a semiconductor device according to an embodiment of the present disclosure; 
         FIGS.  2 A to  2 F ,  FIGS.  3 A to  3 C , and  FIGS.  4 A to  4 D ,  FIGS.  5 A to  5 C ,  FIGS.  6 A to  6 C ,  FIGS.  7 A to  7 D , and  FIGS.  8 A to  8 D  are diagrams illustrating a manufacturing method of a semiconductor device according to an embodiment of the present disclosure; 
         FIG.  9    is a block diagram illustrating a memory system according to an embodiment of the present disclosure; 
         FIG.  10    is a block diagram illustrating a memory system according to an embodiment of the present disclosure; 
         FIG.  11    is a block diagram illustrating a memory system according to an embodiment of the present disclosure; 
         FIG.  12    is a block diagram illustrating a memory system according to an embodiment of the present disclosure; and 
         FIG.  13    is a block diagram illustrating a memory system according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Specific structural or functional descriptions of examples of embodiments in accordance with concepts which are disclosed in this specification are illustrated only to describe the examples of embodiments in accordance with the concepts and the examples of embodiments in accordance with the concepts may be carried out by various forms but the descriptions are not limited to the examples of embodiments described in this specification. 
     Various embodiments are directed to a semiconductor device having a stabilized structure and improved characteristics, and a method of manufacturing the semiconductor device. 
       FIGS.  1 A to  1 E  are diagrams illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.  FIG.  1 A  is an A-A′ cross-sectional view of  FIGS.  1 D and  1 E ,  FIG.  1 D  is a plan view of a first level LV 1  of  FIG.  1 A , and  FIG.  1 E  is a plan view of a second level LV 2  of  FIG.  1 A .  FIG.  1 B  is an enlarged view of a portion B of  FIG.  1 A  and  FIG.  1 C  is an enlarged view of a portion C of  FIG.  1 A . 
     Referring to  FIGS.  1 A to  1 C , a semiconductor device may include a stacked structure ST, a conductive structure  21 , data storage patterns  14  and channel layers  16 . The semiconductor device may further include blocking patterns  13 , tunnel insulating layers  15 , insulating cores  17 , channel pads  18 , an insulating protective layer  19 , an isolation insulating pattern  22 , an interlayer insulating layer  23 , a slit structure SLS, or a combination thereof. 
     The stacked structure ST may include first conductive layers  11  and insulating layers  12  that are stacked on each other. The first conductive layers  11  may be gate electrodes of memory cells, or word lines. The first conductive layers  11  may include a conductive material such as polysilicon, tungsten, molybdenum, or metal. The insulating layers  12  may insulate the stacked first conductive layers  11  from each other. The insulating layers  12  may include insulating materials such as oxides, nitrides, or air gaps. 
     The conductive structure  21  may be stacked on the stacked structure ST. The conductive structure  21  may be a gate electrode of a select transistor, or a select line. According to an embodiment, the conductive structure  21  may include a drain select line. 
     The conductive structure  21  may include second conductive layers  21 A and second conductive patterns  21 B. The second conductive layers  21 A may be located over the stacked structure ST. Each of the second conductive layers  21 A may commonly surround sidewalls of the plurality of channel layers  16 . Each of the second conductive patterns  21 B may surround the sidewall of each of the channel layers  16 . The second conductive pattern  21 B may be interposed between the channel layers  16  and the second conductive layers  21 A. According to an embodiment, a plurality of second conductive patterns  21 B may be electrically connected to one second conductive layer  21 A. The second conductive layer  21 A and the second conductive patterns  21 B may be formed into a single layer. Alternatively, an interface may exist between the second conductive layer  21 A and the second conductive patterns  21 B. 
     The second conductive pattern  21 B may have an uneven upper surface. Referring to  FIG.  1 C , the second conductive pattern  21 B may include either or both of a protruding portion and a depressed portion. The upper surface of the second conductive pattern  21 B may include a first portion P 1  adjacent to the tunnel insulating layer  15  and a second portion P 2  adjacent to the second conductive layer  21 A. The second portion P 2  may have a different level with respect to the first portion P 1 . According to an embodiment, the first portion P 1  may have a higher level than the second portion P 2 . According to an embodiment, the first portion P 1  may have a higher level than the upper surface of the second conductive layer  21 A. The second portion P 2  may have substantially the same level as the upper surface of the second conductive layer  21 A, or may have a lower level than the upper surface of the second conductive layer  21 A. 
     The second conductive layers  21 A may include a conductive material such as polysilicon, tungsten, molybdenum, or metal. The second conductive patterns  21 B may have materials that are the same or different from the second conductive layers  21 A. The specific resistance of the second conductive patterns  21 B may be equal to or less than that of the second conductive layers  21 A. The second conductive patterns  21 B may include polysilicon, metal, metal nitride, metal silicide, or the like. According to an embodiment, the second conductive patterns  21 B may include tungsten, tungsten nitride, tungsten silicide, molybdenum, molybdenum nitride, molybdenum silicide, titanium, titanium nitride, titanium silicide, or a combination thereof. 
     The channel layers  16  may pass through the stacked structure ST and the conductive structure  21  in a third direction III. The third direction III may refer to a stacking direction of the first conductive layers  11  and the insulating layers  12 . The channel layers  16  may protrude above the upper surface of the conductive structure  21 . The channel pads  18  may be disposed over the conductive structure  21  and protrude above the upper surface of the conductive structure  21 . 
     Each of the channel pads  18  may be coupled to each of the channel layers  16 . Referring to  FIG.  1 C , the channel layer  16  may protrude into the channel pad  18 . Since the channel pad  18  contacts the upper surface and the sidewall of the channel layer  16 , a contact area may be increased. The channel pad  18  may be formed on the insulating core  17 , the channel layer  16  and the tunnel insulating layer  15 . 
     Each of the channel layers  16  may have a central region filled up, or an open central region. The open central region of each of the channel layers  16  may be filled with the insulating core  17 . The insulating cores  17  may include an insulating material such as an oxide, a nitride, or air gaps. The channel layer  16 , the insulating core  17  formed in the channel layer  16 , and the channel pad  18  coupled to the channel layer  16  may form a single channel structure CH. 
     The tunnel insulating layers  15 , the data storage patterns  14  and the blocking patterns  13  may be interposed between the channel layers  16  and the blocking patterns  13 . The data storage patterns  14  may include a floating gate, a charge trapping material, polysilicon, a nitride, a variable resistance material, a phase change material, a nanostructure, or the like. 
     The tunnel insulating layers  15 , the data storage patterns  14  and the blocking patterns  13  may surround the channel layers  16 . The data storage patterns  14  and the blocking patterns  13  may be located under the conductive structure  21 . According to an embodiment, the data storage patterns  14  and the blocking patterns  13  may be located under the second conductive patterns  21 B. In a cross-sectional view, the thickness of each second conductive pattern  21 B in a first direction I may be substantially the same as the sum of the thickness of the data storage pattern  14  in the first direction I and the thickness of the blocking pattern  13  in the first direction I. The first direction I may cross the third direction III. 
     Upper surfaces of the data storage patterns  14  and upper surfaces of the blocking patterns  13  may be located at substantially the same or different levels from each other. The upper surfaces of the data storage patterns  14  and the upper surfaces of the blocking patterns  13  may be located at a higher level than the upper surface of the uppermost first conductive layer  11 . The upper surfaces of the data storage patterns  14  and the upper surfaces of the blocking patterns  13  may be located between the upper surface of the conductive structure  21  and the lower surface of the conductive structure  21 , or between the lower surface of the conductive structure  21  and the upper surface of the uppermost first conductive layer  11 . The distance between the second conductive patterns  21 B and the uppermost first conductive layer  11  may be ensured by ensuring the distance between the upper surfaces of the data storage patterns  14  and the uppermost first conductive layer  11 . Alternately, the distance between the second conductive patterns  21 B and the uppermost first conductive layer  11  may be ensured by ensuring the distance between the upper surfaces of the blocking patterns  13  and the uppermost first conductive layer  11 . Therefore, a breakdown voltage may be ensured. 
     The tunnel insulating layers  15  may extend between the channel layers  16  and the second conductive patterns  21 B. According to an embodiment, each of the tunnel insulating layers  15  may be interposed between the channel layer  16  and the data storage pattern  14  and between the channel layer  16  and the second conductive pattern  21 B. The tunnel insulating layers  15  may protrude above the upper surface of the conductive structure  21 . 
     The insulating protective layer  19  may surround the channel pads  18 . The insulating protective layer  19  may surround the channel pads  18  and the tunnel insulating layers  15  and may extend along the upper surface of the conductive structure  21 . The insulating protective layer  19  may be interposed between the channel pads  18  and the interlayer insulating layer  23 , between the tunnel insulating layers  15  and the interlayer insulating layer  23 , and between the conductive structure  21  and the interlayer insulating layer  23 . The insulating protective layer  19  may include an insulating material such as an oxide or a nitride. 
     An insulating layer IL may be located on the conductive structure  21 . The insulating layer IL may include the isolation insulating pattern  22  and the interlayer insulating layer  23 . The insulating layer IL may have a single-layer or multilayer structure. 
     The isolation insulating pattern  22  may be stacked on the stacked structure ST. The isolation insulating pattern  22  may pass through the conductive structure  21  in the third direction III and extend to the interlayer insulating layer  23 . The isolation insulating pattern  22  may be interposed between the second conductive layers  21 A and insulate the second conductive layers from each other. The isolation insulating pattern  22  may contact the second conductive layers  21 A at both sides thereof. At least one of the second conductive patterns  21 B may contact the isolation insulating pattern  22 . The isolation insulating pattern  22  may include an insulating material such as an oxide, a nitride, or air gaps. The interlayer insulating layer  23  may be located on the conductive structure  21 . The interlayer insulating layer  23  may include an insulating material such as oxide or nitride. 
     According to an embodiment, the interlayer insulating layer  23  and the isolation insulating pattern  22  may be coupled into a single layer. Referring to  FIG.  1 A , a portion of the insulating layer IL that passes through the conductive structure  21  may be the isolation insulating pattern  22 , and a portion of the insulating layer IL that is formed above the conductive structure  21  may be the interlayer insulating layer  23 . 
     According to an embodiment, the insulating layer IL may have a multilayer structure. Referring to  FIG.  1 B , the insulating layer IL may include an isolation insulating pattern  22 ′ and an interlayer insulating layer  23 ′. An interface may be defined between the isolation insulating pattern  22 ′ and the interlayer insulating layer  23 ′. The isolation insulating pattern  22 ′ and the interlayer insulating layer  23 ′ may include different materials. The isolation insulating pattern  22 ′ may include an insulating material such as an oxide and a nitride. The interlayer insulating layer  23 ′ may include an amorphous carbon layer. The isolation insulating pattern  22 ′ may pass through the conductive structure  21  to extend between the channel pads  18 . The isolation insulating pattern  22 ′ may pass through the interlayer insulating layer  23 ′. 
     The slit structure SLS may pass through the interlayer insulating layer  23 , the conductive structure  21  and the stacked structure ST. The slit structure SLS may be located between the channel layers  16  adjacent to each other in the first direction I. The slit structure SLS may extend between the second conductive layers  21 A and between the channel pads  18 . The slit structure SLS may pass through the interlayer insulating layer  23 . 
     The slit structure SLS may include a source contact structure  24  and an insulating spacer  25  and may further include a barrier layer  26 . The source contact structure  24  may include a conductive material such as polysilicon, tungsten, molybdenum, or a metal. The source contact structure  24  may have a single layer structure or a multi-layer structure. According to an embodiment, the source contact structure  24  may include a polysilicon single layer. According to an embodiment, the source contact structure  24  may include a first contact structure  24 A and a second contact structure  24 B having a lower specific resistance than the first contact structure  24 A. The first contact structure  24 A may include polysilicon and the second contact structure  24 B may include a metal. The second contact structure  24 B may be separated from the uppermost first conductive layer  11  of the first conductive layers  11 . The lower surface of the second contact structure  24 B may be located in a higher level than the upper surface of the uppermost first conductive layer  11 . 
     The barrier layer  26  may surround the source contact structure  24 . The barrier layer  26  may be interposed between the source contact structure  24  and the insulating spacer  25 . The barrier layer  26  may be interposed between the first contact structure  24 A and the second contact structure  24 B. The barrier layer  26  may include tungsten nitride, molybdenum nitride, tungsten nitride, tantalum nitride, or the like. 
     The insulating spacer  25  may be interposed between the source contact structure  24  and the first conductive layers  11  and between the source contact structure  24  and the conductive structure  21 . The insulating spacer  25  may surround the sidewall of the source contact structure  24  and may include an insulating material such as an oxide, a nitride, or air gaps. 
     According to the above-described structure, memory cells may be located at intersections between the channel structure CH and the first conductive layers  11 . Select transistors may be located at an intersection between the channel structure CH and the conductive structure  21 . The memory cells may be located in the third direction III, and at least one select transistor may be stacked on the memory cells. The memory cells and at least one select transistor that are stacked on top of each other may share the channel layer  16  and the tunnel insulating layer  15 . While a select transistor has a similar structure to a memory cell, the select transistor may include the second conductive pattern  21 B instead of the data storage pattern  14  and the blocking pattern  13 . 
     Referring to  FIGS.  1 A and  1 D , each of the first conductive layers  11  may include first openings OP 1 . The first openings OP 1  may be arranged in the first direction I and in a second direction II crossing the first direction I. Each of the first openings OP 1  may have a circular cross-section, an elliptical cross-section, a polygonal cross-section, or the like. The channel layer  16 , the tunnel insulating layer  15  and the data storage pattern  14  may be located in each of the first openings OP 1 . In addition, the blocking pattern  13  and the insulating core  17  may be located in each of the first openings OP 1 . 
     Referring to  FIGS.  1 A and  1 E , the conductive structure  21  may include second openings OP 2 . The second openings OP 2  may be arranged in the first direction I and the second direction II. The second openings OP 2  may be located at positions corresponding to the first openings OP 1 . Each of the second openings OP 2  may have a circular cross-section, an elliptical cross-section, a polygonal cross-section, or the like. The channel layer  16  and the tunnel insulating layer  15  may be located in each of the second openings OP 2 . In other words, the data storage pattern  14  and the blocking pattern  13  may not be located in the second openings OP 2 . 
     In a plan view, the second openings OP 2  may have a smaller width than the first openings OP 1 . According to an embodiment, each of the first openings OP 1  may have a first width W 1  in the first direction I and each of the second openings OP 2  may have a second width W 2  in the first direction I. The second width W 2  may be less than the first width W 1 . 
     In a plan view, the distance between the second openings OP 2  may be greater than the distance between the first openings OP 1 . According to an embodiment, the first openings OP 1  may be spaced apart from each other at a first distance D 1  in the first direction I, and the second openings OP 2  may be spaced apart from each other at a second distance D 2  in the first direction I. The second distance D 2  may be greater than the first distance D 1 . 
     The isolation insulating pattern  22  may pass through the conductive structure  21  between the second openings OP 2 . The second conductive layers  21 A at both sides may be insulated from each other by the isolation insulating pattern  22 . The isolation insulating pattern  22  may extend in the second direction II. The isolation insulating pattern  22  may contact the second conductive patterns  21 B at both sides thereof. The tunnel insulating layers  15  and the second conductive patterns  21 B may be interposed between the isolation insulating pattern  22  and the channel layers  16 . 
     According to the above-described structure, since the second openings OP 2  have a smaller width than the first openings OP 1 , the distance between the second openings OP 2  may be selectively increased. In the first level LV 1  where the isolation insulating pattern  22  is not formed, the first distance D 1  may be maintained between the first openings OP 1 . In the second level LV 2  where the isolation insulating pattern  22  is formed, the second distance D 2  may be sufficiently maintained between the second openings OP 2 . Therefore, in the second level LV 2 , it may be possible to ensure a space where the isolation insulating pattern  22  is formed between the channel structures CH. 
     In addition, the sidewalls of the channel layers  16  located adjacent to the isolation insulating pattern  22  may be entirely surrounded by the second conductive patterns  21 B. Therefore, the channel layers  16  located adjacent to the isolation insulating pattern  22  may serve as real channel layers, not dummy channel layers. In addition, since the select transistors have a gate all around (GAA) structure, they may have uniform characteristics. 
       FIGS.  2 A to  2 F ,  FIGS.  3 A to  3 C , and  FIGS.  4 A to  4 D ,  FIGS.  5 A to  5 C ,  FIGS.  6 A to  6 C ,  FIGS.  7 A to  7 D , and  FIGS.  8 A to  8 D  are diagrams illustrating a manufacturing method of a semiconductor device according to an embodiment of the present disclosure.  FIGS.  2 A,  3 A,  4 A,  5 A,  6 A,  7 A, and  8 A  and  FIGS.  2 B,  3 B,  4 B,  5 B,  6 B,  7 B, and  8 B  are plan views, and  FIGS.  2 C,  3 C,  4 C,  5 C,  6 C,  7 C, and  8 C  and  FIGS.  2 D,  4 D,  7 D , and  8 D are cross-sectional views. Hereinafter, any repetitive detailed description of components having already been mentioned above will be omitted. 
     Referring to  FIGS.  2 A to  2 F , the stacked structure ST, a conductive layer  33 , a sacrificial layer  34 , the first openings OP 1 , the channel structures CH and memory layers M may be formed. First, referring to  FIGS.  2 A to  2 C , the stacked structure ST may be formed on a substrate (not shown) that includes a lower structure. The lower structure may include a peripheral circuit, an interconnection structure, a source structure or the like. 
     The stacked structure ST may include first material layers  31  and second material layers  32  that are stacked alternately with each other. The first material layers  31  may include a material having a high etch selectivity with respect to the second material layers  32 . For example, the first material layers  31  may include a sacrificial material, such as nitride, and the second material layers  32  may include an insulating material, such as oxide. For example, the first material layers  31  may include a conductive material such as polysilicon, tungsten, or molybdenum, and the second material layers  32  may include an insulating material such as an oxide. The first material layers  31  may have the same or different thicknesses from each other. According to an embodiment, at least one lowermost first material layer  31  may have a greater thickness than the other first material layers  31 . Each of the second material layers  32  may have the same or different thicknesses in comparison with each other. According to an embodiment, at least one uppermost second material layer  32  may have a greater thickness than the other second material layers  32 . 
     The conductive layer  33  may be formed on the stacked structure ST. The conductive layer  33  may be a gate electrode of a select transistor, or a select line. The conductive layer  33  may include a conductive material such as polysilicon, tungsten, or molybdenum. The sacrificial layer  34  may be formed on the conductive layer  33 . The sacrificial layer  34  may include a nitride layer, a carbon layer, an amorphous carbon layer, or the like. The sacrificial layer  34  may serve as a hard mask during subsequent processes. 
     The first openings OP 1  may be formed through the sacrificial layer  34 , the conductive layer  33  and the stacked structure ST. The first openings OP 1  may be arranged in the first direction I and in the second direction II crossing the first direction I. 
     Referring to  FIGS.  2 A,  2 B and  2 D , a memory layer M may be formed in the first openings OP 1 . The memory layer M may include at least one of a blocking layer  35 , a data storage layer  36  and a tunnel insulating layer  37 . The memory layer M may be formed along inner surfaces of the first openings OP 1  and may be formed on the upper surface of the stacked structure ST. According to an embodiment, the blocking layer  35 , the data storage layer  36  and the tunnel insulating layer  37  may be formed in a sequential manner. A buffer layer (not shown) may be formed before the memory layer M is formed. The buffer layer may serve to protect the memory layer M when removing the first material layers  31  during subsequent processes. The buffer layer may include nitride. 
     Subsequently, a channel layer  38  may be formed in the first openings OP 1 . The channel layer  38  may include a semiconductor material such as silicon or germanium, or may include a nanostructure. The channel layer  38  may be formed along the surface of the memory layer M. Subsequently, an insulating core  39  may be formed in the first openings OP 1 . The insulating core  39  may include an insulating material such as an oxide, a nitride, or air gaps. 
     Subsequently, referring to  FIGS.  2 A,  2 B and  2 E , a recess region may be formed by etching the insulating core  39 . The recessed region may be provided to form a channel pad. An upper surface of an etched insulating core  39 A may be located at a higher level than an upper surface of the conductive layer  33 . An upper portion of the channel layer  38  may be exposed by the etched insulating core  39 A. Subsequently, channel layers  38 A may be formed by etching the channel layer  38 . Tunnel insulating layers  37 A may then be formed by etching the tunnel insulating layer  37 . Upper surfaces of the tunnel insulating layers  37 A may be located at substantially a same level as that of the insulating core  39 . Upper surfaces of the channel layers  38 A may protrude above the upper surface of the insulating core  39  or the upper surfaces of the tunnel insulating layers  37 A. 
     Subsequently, channel pads  41  may be coupled to the channel layers  38 A, respectively. According to an embodiment, after a conductive layer is formed, the channel pads  41  may be formed by planarizing the conductive layer until the upper surface of the sacrificial layer  34  is exposed. The planarization may be performed using a chemical mechanical polishing (CMP) process. When the conductive layer is planarized, portions of the blocking layer  35  and the data storage layer  36  that are formed on the upper surface of the stacked structure ST may also be planarized. As a result, blocking layers  35 A and data storage layers  36 A may be formed in the first openings OP 1 , respectively. The channel structure CH including the channel layer  38 A and the channel pad  41  may be formed. The channel structure CH may further include the insulating core  39 A. The channel layers  38 A may protrude into the channel pads  41 . The channel pads  41  may include a conductive material such as polysilicon, tungsten, or molybdenum. 
     The upper surfaces of the channel pads  41 , the data storage layers  36 A and the blocking layers  35 A may be located at substantially the same or different levels in comparison with each other. Depending on etch rates of the channel pads  41 , the data storage layers  36 A and the blocking layers  35 A, the upper surfaces thereof may be located at different levels in comparison with each other. A layer or a pad having a material with a lower etch rate may be less etched during planarization, such that an upper surface thereof may be located at a higher level. According to an embodiment, the upper surfaces of the channel pads  41  may be located at a higher level than those of the data storage layers  36 A. The upper surfaces of the data storage layers  36 A may be located at a higher level than those of the blocking layers  35 A. 
     Subsequently, referring to  FIGS.  2 A,  2 B and  2 F , the sacrificial layer  34  may be removed. The sacrificial layer  34  may be removed using a dip-out process. As a result, the channel structure CH may protrude above the upper surface of the conductive layer  33 , and the channel pads  41  may protrude above the upper surface of the conductive layer  33 . In addition, the memory layer M surrounding the channel structure CH may be exposed. 
     Referring to  FIGS.  3 A to  3 C , the second openings OP 2  may be formed between the channel structure CH and the conductive layer  33 . The second openings OP 2  may be formed by etching the memory layer M. Each of the second openings OP 2  may have a ring shape surrounding each of the channel structures CH. According to an embodiment, blocking patterns  35 B may be formed by selectively etching the blocking layers  35 A. The blocking layers  35 A may be etched using a dry cleaning process. Subsequently, data storage patterns  36 B may be formed by selectively etching the data storage layers  36 A. The data storage layers  36 A may be etched using a dry cleaning process. The second openings OP 2  may be formed at portions from which the blocking layers  35 A and the data storage layers  36 A are etched. 
     The data storage layers  36 A and the blocking layers  35 A may be etched to a depth to expose the uppermost second material layer  32 . The data storage layers  36 A and the blocking layers  35 A may be etched to a depth wherein the uppermost first material layer  31  is not exposed. When the uppermost second material layer  32  has a greater thickness than the other second material layers  32 , the uppermost second material layer  32  may prevent the uppermost first material layer  31  from being exposed when the data storage layers  36 A and the blocking layers  35 A are etched. 
     Referring to  FIGS.  4 A to  4 D , conductive patterns  42 A may be formed in the second openings OP 2 . First, referring to  FIGS.  4 A to  4 C , a conductive material layer  42  may be formed on the conductive pads  41  and the upper surface of conductive material layer  33 . The conductive material layer  42  may have the same or different materials than the materials of the conductive layer  33 . The conductive material layer  42  may include a material having a lower specific resistance than that of the conductive layer  33 . The conductive material layer  42  may include a conductive material such as polysilicon, doped polysilicon, a metal, a metal nitride, or a metal silicide. According to an embodiment, the conductive material layer  42  may include tungsten, tungsten nitride, tungsten silicide, titanium, titanium nitride, titanium silicide, tantalum, tantalum nitride, tantalum silicide, molybdenum, molybdenum nitride, molybdenum silicide, or a combination thereof. 
     The conductive material layer  42  may fill the second openings OP 2  and surround the channel pads  41 . The conductive material layer  42  may include a first portion P 1  and a second portion P 2 . The first portion P 1  may be formed in the second openings OP 2 . The second portion P 2  may surround protruding portions of the channel structures CH. In addition, the conductive material layer  42  may include a third portion P 3  that may be formed on the upper surface of the conductive layer  33 . The conductive material layer  42  may be formed using a deposition process. During the deposition process, a seam may be formed in the conductive material layer  42 . According to an embodiment, the seam may be formed at a position corresponding to the second portion P 2 , or at a position where the first portion P 1  and the second portion P 2  are coupled to each other. 
     Subsequently, an additional process may be performed with respect to materials of the conductive layer  33  and the conductive material layer  42 . According to an embodiment, when the conductive layer  33  includes polysilicon and the conductive material layer  42  includes a metal, the conductive layer  33  may be silicided by performing heat treatment thereon. 
     Referring to  FIGS.  4 A,  4 B and  4 D , the conductive material layer  42  may be etched to form the conductive patterns  42 A. By etching the second portion P 2  of the conductive material layer  42 , the conductive patterns  42 A may be formed. The third portion P 3  may also be etched when the second portion P 2  is etched. The conductive material layer  42  may be formed using a dry cleaning process. As a result, the channel pads  41  and the conductive patterns  42 A may be separated from each other. When a seam is exposed during the etching process of the conductive material layer  42 , an etch rate of the corresponding portion may be increased compared to the other portions. As a result, the conductive patterns  42 A may have irregular upper surfaces. For example, protrusions or recesses may be formed in the upper surfaces of the conductive patterns  42 A. 
     The conductive patterns  42 A may be interposed between the tunnel insulating layers  37 A and the conductive layer  33 , respectively. Each of the conductive patterns  42 A may have a ring shape including a third opening OP 3 . The conductive patterns  42 A may be electrically coupled to the conductive layer  33 . 
     Referring to  FIGS.  5 A to  5 C , an insulating protective layer  43  may be formed. The insulating protective layer  43  may surround the protruding portions of the channel structures CH. The insulating protective layer  43  may surround the exposed channel pads  41  and tunnel insulating layer  37 A. The insulating protective layer  43  may surround the upper surface of the conductive layer  33 . The insulating protective layer  43  may include an insulating material such as an oxide or a nitride. The insulating protective layer  43  may be formed using a deposition process and may be conformally formed along the profile of the channel pads  41 . 
     Subsequently, a spacer material layer  44  may be formed over the insulating protective layer  43 . The spacer material layer  44  may serve as an etch barrier during subsequent processes and include a material having a greater etch selectivity than the conductive layer  33 . The spacer material layer  44  may include a carbon layer, an amorphous carbon layer, or the like. 
     The spacer material layer  44  may include first portions P 1  surrounding the channel structures CH and a second portion P 2  coupling the first portions P 1 . A space SP that is deposited with no spacer material may exist between the first portions P 1 . The first portions P 1  may have a greater thickness than the second portion P 2 . Each of the first portions P 1  may have an overhang structure so that an upper part thereof may be thicker than a lower part thereof. The spacer material layer  44  may be formed using a deposition process with poor step coverage. According to an embodiment, the spacer material layer  44  may be formed using Plasma Enhanced Chemical Vapor Deposition (PE-CVD), Physical Vapor Deposition (PVD), or the like. 
     Referring to  FIGS.  6 A to  6 C , a mask pattern  45  may be formed on the spacer material layer  44 . The mask pattern  45  may include line patterns extending in the second direction II. The mask pattern  45  may cover the channel structures CH and expose a first region R 1  where an isolation insulating pattern is formed and a second region R 2  where a slit structure is formed. 
     By etching the spacer material layer  44  using the mask pattern  45  as an etch barrier, spacers  44 A may be formed on the sidewalls of the channel structures CH. The second portion P 2  of the spacer material layer  44  may be etched. An area of the first portion P 1  that is thicker than the other areas may be etched from the upper part of the channel structure CH. As a result, the insulating protective layer  43  may be exposed. 
     Referring to  FIGS.  7 A to  7 D , fourth openings OP 4  may be formed through the conductive layer  33  and isolation insulating patterns  46 A may be formed in the fourth openings OP 4 . First, referring to  FIGS.  7 A to  7 C , the insulating protective layer  43  and the conductive layer  33  may be etched using the mask pattern  45  and the spacers  44 A as an etch barrier. According to an embodiment, under the condition that the conductive layer  33  has a high etch selectivity with respect to the spacers  44 A, the conductive layer  33  may be selectively etched. As a result, the fourth opening OP 4  and a fifth opening OP 5  may be formed. The fourth opening OP 4  and the fifth opening OP 5  may pass through the conductive layer  33  and extend between the spacers  44 A. 
     The fourth opening OP 4  and the fifth opening OP 5  may pass through the conductive layer  33  and have a depth which does not expose the uppermost first material layer  31 . The fourth opening OP 4  may be located at a portion corresponding to the first region R 1 . The fifth opening OP 5  may be located at a portion corresponding to the second region R 2 . The fourth opening OP 4  may have a smaller width than the fifth opening OP 5 . 
     The conductive patterns  42 A may be exposed when the conductive layer  33  is etched. However, the conductive patterns  42 A may be etched when the conductive layer  33  is etched. At least one of the conductive patterns  42 A located adjacent to the first region R 1  may be etched or exposed. As a result, conductive structures CS extending in the second direction II may be formed. Each of the conductive structures CS may include a conductive layer  33 A and the conductive patterns  42 A. Subsequently, the mask pattern  45  and the spacers  44 A may be removed and a cleaning process may be performed. 
     Subsequently, referring to  FIGS.  7 A,  7 B and  7 D , an isolation insulating pattern  46 A may be formed in the fourth opening OP 4 . When the isolation insulating pattern  46 A is formed, a sacrificial pattern  46 B may also be formed in the fifth opening OP 5 . When the isolation insulating pattern  46 A is formed, an interlayer insulating layer  46 C may also be formed. The isolation insulating pattern  46 A, the sacrificial pattern  46 B and the interlayer insulating layer  46 C may be coupled into a single layer. 
     According to an embodiment, an insulating material layer may be formed on the conductive structure CS. The insulating material layer may be formed in the fourth opening OP 4  and the fifth opening OP 5  and may be formed on the insulating protective layer  43 . After the insulating material layer is formed, a planarizing process may be performed thereon to thereby form an insulating layer  46 . The insulating layer  46  may include the isolation insulating pattern  46 A, the sacrificial pattern  46 B and the interlayer insulating layer  46 C. 
     However, the insulating layer  46  may be formed without removing the spacers  44 A. The remaining spacers  44 A may serve, together with the insulating layer  46 , as an interlayer insulating layer. 
     Referring to  FIGS.  8 A to  8 D , the slit structure SLS may pass through the conductive structure CS and the stacked structure ST. 
     First, referring to  FIGS.  8 A to  8 C , a mask pattern  47  may be formed on the insulating layer  46 . The mask pattern  47  may be formed to expose the second region R 2 . Subsequently, the insulating layer  46  and the stacked structure ST may be etched using the mask pattern  47  as an etch barrier. As a result, a sixth opening OP 6  may pass through the insulating layer  46 , the conductive structure CS and the stacked structure ST. According to an embodiment, the sixth opening OP 6  may have a depth such that the source structure located under the stacked structure ST is exposed. 
     Subsequently, seventh openings OP 7  may be formed by removing the first material layers  31  through the sixth opening OP 6 . Third material layers  51  may be formed in the seventh openings OP 7 . According to an embodiment, the third material layers  51  may include a conductive material such as polysilicon, tungsten, molybdenum, or a metal. At least one lowermost third material layer  51 , among the third material layers  51 , may be a source select line, and the other third material layers  51  may be word lines. 
     Referring to  FIGS.  8 A,  8 B and  8 D , the slit structure SLS may be formed in the sixth opening OP 6 . After an insulating spacer  48  is formed in the sixth opening OP 6 , a source contact structure  50  may be formed in the insulating spacer  48 . According to an embodiment, the source contact structure  50  may be formed in a single layer by filling the insulating spacer  48  with a conductive material layer. The single layer may include polysilicon. According to an embodiment, a first contact structure  50 A, a barrier layer  49 , and a second contact structure  50 B may be formed in a sequential manner in the sixth opening OP 6 . The second contact structure  50 B may include a material having a lower specific resistance than the first contact structure  50 A. 
     According to the above-described manufacturing method, the spacers  44 A be formed using the step difference between the upper surface of the conductive layer  33  and the upper surface of the channel structure CH. In addition, the conductive layer  33  may be etched using the spacers  44 A and the mask pattern  45  as an etch barrier. Accordingly, by etching the conductive layer  33  by self-alignment, a region where the isolation insulating pattern  46 A is formed may be defined. In addition, by replacing the data storage layer and the blocking layer with the conductive pattern  42 A in a level corresponding to the conductive structure CS, a region where the isolation insulating pattern  46 A is formed may be ensured, and a select transistor having a GAA structure may be formed. 
       FIG.  9    is a block diagram illustrating a memory system  1000  according to an embodiment of the present disclosure. 
     Referring to  FIG.  9   , the memory system  1000  may include a memory device  1200  configured to store data and a controller  1100  configured to perform communications between the memory device  1200  and a host  2000 . 
     The host  2000  may be a device or system configured to store data in the memory system  1000  or retrieve data from the memory system  1000 . The host  2000  may generate requests for various operations and output the generated requests to the memory system  1000 . The requests may include a program request for a program operation, a read request for a read operation, and an erase request for an erase operation. The host  2000  may communicate with the memory system  1000  by using at least one interface protocol among, for example, Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory express (NVMe), Universal Serial Bus (USB), Multi-Media Card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE). 
     The host  2000  may include at least one of a computer, a portable digital device, a tablet, a digital camera, a digital audio player, a television, a wireless communication device, or a cellular phone. However, embodiments of the disclosed technology are not limited thereto. 
     The controller  1100  may control overall operations of the memory system  1000 . The controller  1100  may control the memory device  1200  in response to the requests of the host  2000 . The controller  1100  may control the memory device  1200  to perform a program operation, a read operation and an erase operation at the request of the host  2000 . Alternatively, the controller  1100  may perform a background operation for performance improvement of the memory system  1000  in the absence of the request from the host  2000 . 
     To control the operations of the memory device  1200 , the controller  1100  may transfer a control signal and a data signal to the memory device  1200 . The control signal and the data signal may be transferred to the memory device  1200  through different input/output lines. The data signal may include a command, an address, or data. The control signal may be used to differentiate periods wherein the data signal is input. 
     The memory device  1200  may perform a program operation, a read operation and an erase operation in response to control of the controller  1100 . The memory device  1200  may be a volatile memory that loses data when a power supply is blocked, or a non-volatile memory that retains data in the absence of power supply. The memory device  1200  may have the structure as described above with reference to  FIGS.  1 A to  1 E . In addition, the memory device  1200  may be the semiconductor device manufactured by the method as described above with reference to  FIGS.  2 A to  8 D . According to an embodiment, the semiconductor memory device may include a stacked structure that includes first conductive layers and insulating layers stacked alternately with each other; second conductive layers located on the stacked structure, first openings passing through the second conductive layers and the stacked structure and having a first width; second conductive patterns formed in the first openings and located on the stacked structure to be electrically coupled to the second conductive layers; data storage patterns formed in the first openings and located under the second conductive patterns; and channel layers formed in the data storage patterns and the second conductive patterns. 
       FIG.  10    is a block diagram illustrating a memory system  30000  according to an embodiment of the present disclosure. 
     Referring to  FIG.  10   , the memory system  30000  may be incorporated into a cellular phone, a smart phone, a tablet, a personal computer (PC), a personal digital assistant (PDA), or a wireless communication device. The memory system  30000  may include a memory device  2200  and a memory controller  2100  controlling the operations of the memory device  2200 . 
     The memory controller  2100  may control a data access operation of the memory device  2200 , for example, a program operation, an erase operation or a read operation of the memory device  2200  in response to control of a processor  3100 . 
     The data programmed into the memory device  2200  may be output through a display  3200  in response to control of the memory controller  2100 . 
     A radio transceiver  3300  may exchange a radio signal through an antenna ANT. For example, the radio transceiver  3300  may change the radio signal received through the antenna ANT into a signal which may be processed by the processor  3100 . Therefore, the processor  3100  may process the signal output from the radio transceiver  3300  and transfer the processed signal to the memory controller  2100  or the display  3200 . The memory controller  2100  may transfer the signal processed by the processor  3100  into the memory device  2200 . In addition, the radio transceiver  3300  may change a signal output from the processor  3100  into a radio signal and output the radio signal to an external device through the antenna ANT. A control signal for controlling the operations of the host or data to be processed by the processor  3100  may be input by an input device  3400 , and the input device  3400  may include a pointing device, such as a touch pad and a computer mouse, a keypad, or a keyboard. The processor  3100  may control the operations of the display  3200  so that data output from the memory controller  2100 , data output from the radio transceiver  3300 , or data output from an input device  3400  may be output through the display  3200 . 
     According to an embodiment, the memory controller  2100  capable of controlling the operations of the memory device  2200  may be realized as a portion of the processor  3100 , or as a separate chip from the processor  3100 . 
       FIG.  11    is a block diagram illustrating a memory system  40000  according to an embodiment of the present disclosure. 
     Referring to  FIG.  11   , the memory system  40000  may be incorporated into a personal computer (PC), a tablet PC, a net-book, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player. 
     The memory system  40000  may include the memory device  2200  and the memory controller  2100  that controls a data processing operation of the memory device  2200 . 
     A processor  4100  may output data stored in the memory device  2200  through a display  4300  according to data input through an input device  4200 . Examples of the input device  4200  may include a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard. 
     The processor  4100  may control overall operations of the memory system  40000  and control operations of the memory controller  2100 . According to an embodiment, the memory controller  2100  capable of controlling the operations of the memory device  2200  may be realized as a portion of the processor  4100 , or as a separate chip from the processor  4100 . 
       FIG.  12    is a block diagram illustrating a memory system  50000  according to an embodiment of the present disclosure. 
     Referring to  FIG.  12   , the memory system  50000  may be incorporated into an image processor, for example, a digital camera, a cellular phone with a digital camera attached thereto, a smart phone with a digital camera attached thereto, or a table PC with a digital camera attached thereto. 
     The memory system  50000  may include the memory device  2200  and the memory controller  2100  that controls a data processing operation of the memory device  2200 , for example, a program operation, an erase operation, or a read operation. 
     An image sensor  5200  of the memory system  50000  may convert an optical image into digital signals. The converted digital signals may be transferred to a processor  5100  or the memory controller  2100 . In response to control of the processor  5100 , the converted digital signals may be output through a display  5300  or stored in the memory device  2200  through the memory controller  2100 . In addition, the data stored in the memory device  2200  may be output through the display  5300  in response to control of the processor  5100  or the memory controller  2100 . 
     According to an embodiment, the memory controller  2100  capable of controlling the operations of the memory device  2200  may be formed as a part of the processor  5100 , or a separate chip from the processor  5100 . 
       FIG.  13    is a block diagram illustrating a memory system  70000  according to an embodiment of the present disclosure. 
     Referring to  FIG.  13   , the memory system  70000  may include a memory card or a smart card. The memory system  70000  may include the memory device  2200 , the memory controller  2100 , and a card interface  7100 . 
     The memory controller  2100  may control data exchange between the memory device  2200  and the card interface  7100 . According to an embodiment, the card interface  7100  may be, but is not limited thereto, a secure digital (SD) card interface or a multi-media card (MMC) interface. 
     The card interface  7100  may interface data exchange between a host  60000  and the memory controller  2100  according to a protocol of the host  60000 . According to an embodiment, the card interface  7100  may support a Universal Serial Bus (USB) protocol and an InterChip (IC)-USB protocol. The card interface  7100  may refer to hardware capable of supporting a protocol which is used by the host  60000 , software installed in the hardware, or a signal transmission method. 
     When the memory system  70000  is connected to a host interface  6200  of the host  60000  such as a PC, a tablet PC, a digital camera, a digital audio player, a cellular phone, a console video game hardware, or a digital set-top box, the host interface  6200  may perform data communication with the memory device  2200  through the card interface  7100  and the memory controller  2100  in response to control of a microprocessor  6100 . 
     A semiconductor device with a stabilized structure and improved reliability may be provided. In addition, a method of manufacturing a semiconductor device may be simplified at low cost.