Patent Publication Number: US-2021193230-A1

Title: Sense amplifier for bidirectional sensing of memory cells of a non-volatile memory

Description:
BACKGROUND 
     Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Like-numbered elements refer to common components in the different figures. 
         FIG. 1A  is a functional block diagram of a memory device. 
         FIG. 1B  is a block diagram depicting one example of a memory structure. 
         FIG. 2  is a block diagram depicting one embodiment of a memory system. 
         FIG. 3  is a perspective view of a portion of one embodiment of a monolithic three-dimensional memory structure. 
         FIG. 4  is a schematic of a plurality of NAND strings. 
         FIG. 5  depicts various embodiments of a portion of a three-dimensional memory array with a vertical cross-point structure. 
         FIG. 6  depicts threshold voltage distributions in a three bit per cell embodiment. 
         FIG. 7A  is a flowchart describing one embodiment of a process for programming/writing. 
         FIG. 7B  is a flowchart describing one embodiment of a process for programming/writing data into memory cells connected to a common word line. 
         FIG. 7C  depicts a word line voltage during programming/writing and verify operations. 
         FIG. 8  is a flowchart describing one embodiment of a process for reading data from non-volatile memory cells. 
         FIGS. 9A and 9B  illustrate a window of threshold values to which memory cells can be programmed, including negative threshold values. 
         FIGS. 10A-10C  illustrate several techniques for sensing memory cells with negative threshold voltage values. 
         FIG. 11  illustrates some elements of an embodiment of a sense amplifier that can be used to perform a sensing operation using the techniques illustrated in  FIG. 10C . 
         FIG. 12  is a more detailed representation of an embodiment for the sense amplifier of  FIG. 11 . 
         FIG. 13  illustrates one embodiment for some of the control waveforms for a sensing operation using the embodiment of  FIG. 12 . 
         FIG. 14  is a flowchart describing one embodiment of a process for a sensing operation for the sense amplifier of  FIG. 12  using the waveforms of  FIG. 13 . 
         FIG. 15  is a circuit diagram of an additional embodiment of a sense amplifier operable in a first mode and a second mode. 
         FIG. 16  is a flowchart presenting an embodiment for a sensing operation in which the sensing node in the sense amplifier circuit of  FIG. 15  is discharged through a selected memory cell. 
         FIG. 17  illustrates an embodiment for the discharge of a sensing node in the sense amplifier circuit of  FIG. 15  through a selected memory cell. 
         FIG. 18  illustrates a pre-charge phase for a sensing operation of the embodiment of  FIG. 15  in a sensing mode where the current from a selected memory cell flows into the sense amplifier. 
         FIG. 19  illustrates a settling phase, in which the voltage levels on the sense amplifier circuit are stabilized for a sensing operation of the embodiment of  FIG. 15  in a sensing mode where the current from a selected memory cell flows into the sense amplifier. 
         FIG. 20  illustrates the charging of the sensing node charging phase for a sensing operation of the embodiment of  FIG. 15  in a sensing mode where the current from a selected memory cell flows into the sense amplifier. 
         FIG. 21  illustrates the strobe phase for a sensing operation of the embodiment of  FIG. 15  in a sensing mode where the current from a selected memory cell flows into the sense amplifier. 
         FIG. 22  is a circuit diagram of an alternate embodiment of a sense amplifier operable in a first mode and a second mode. 
         FIG. 23  is a diagram of an embodiment of a bias-voltage generation circuit that can provide control gate voltages for some of the PMOS elements of the sense amplifier embodiments in  FIGS. 15 and 22 . 
         FIG. 24  is a diagram of an embodiment of a bias-voltage generation circuit that can provide the bias level used in discharging the sensing node of the sense amplifier embodiments in  FIGS. 15 and 22 . 
         FIG. 25  is a flowchart describing one embodiment of a process for a sensing operation for the sense amplifier of  FIG. 15  in the first sensing mode, in which current flows into the sense amplifier. 
     
    
    
     DETAILED DESCRIPTION 
     To increase the amount of data stored on a non-volatile memory device, data can be stored in a multi-level cell (MLC) format, where an individual memory cell can be programmed to multiple different states, where each memory cell can hold more than one bit of data. In memory cells where different data states correspond to different threshold voltage (Vt) values, this involves splitting up the range, or window, of available Vt values into a number of ranges corresponding to the different data states. To store more states per cell, the Vt range allotted to each state needs to be made smaller, the size of the window increased, or both. The size of the Vt window can be increased by extending the window further into negative Vt values and having multiple states with negative, or non-positive, Vt values. However, for this to be useful, the memory device must be able to distinguish between different non-positive Vt states. 
     Sensing negative Vt states by most standard sensing techniques and sense amplifier structures has a number of limitations. In a typical sensing arrangement, the control gate of a memory cell is biased by a read voltage and a bit line connected to sense amplifier is discharged through the memory cell to a source line, where the amount of discharge depends on the value of the read voltage relative to the memory cell&#39;s Vt. Under this usual arrangement, reading of negative Vt states uses negative read voltages; however, negative voltages are typically not available on a memory die and their introduction involves complications. Alternately, negative Vt states can be read by raising the source voltage for the memory cell, but this approach can usually only extend to a fairly shallow negative Vt range. To allow for sensing more deeply into the negative Vt range, the following introduces sense amplifier structures and techniques in which the source is discharged through a selected memory cell into the bit line and sense amplifier, reversing the usual direction of current flow through the selected memory cell in a sensing operation. 
     More specifically, a first set of embodiments for a sense amplifier structure and sensing techniques are described where, in a first phase, the source line is discharged through a selected memory to the corresponding bit line and on into the sense amp. The amount of current discharged in this phase will depend on the conductivity of the memory cell, which in turn depends on the word line voltage supplied to the control gate of the selected memory cell relative to its threshold voltage. A discharge transistor has its control gate connected to the memory cell&#39;s discharge path during the first phase, so that the conductivity of the discharge transistor will reflect the conductivity of the selected memory cell. The control gate of the discharge transistor is then set to float at this level. In a second phase, a sense node is then discharged through the discharge transistor: as the conductivity of the discharge transistor reflects the conductivity of the selected memory cell, the rate at which the sense node discharges reflects the conductivity of the memory cell. After discharging the sense node for a sensing period, the level on the sense node is latched for the read result. 
     To improve accuracy of the sensing operation for the first set of embodiments, elements can be included in the sense amp to reduce noise levels. To reduce noise on the control gate of the discharge transistor when transitioning between phases, a decoupling capacitor can be connected to the control gate. The capacitor can also be biased to adjust for operating conditions, such as temperature, and device processing variations. To reduce noise on the source node of the discharge transistor, an auxiliary keeper current can be supplied through the discharge transistor during the transition between phases and on into the sense node discharge phase. 
     In another set of embodiments for a sense amplifier, the sense amplifier is operable in a first sensing mode, in which current flows from a selected memory through its corresponding bit line and into the sense amplifier, with the charge from the current accumulating on a sensing node and capacitor. The amount of charge accumulated on the sensing node depends on the state of the selected memory cell. In a second sensing mode, charge is discharged from the sensing node and sensing capacitor through the selected memory cell, where the amount of charge remaining on sensing node depends on the state of the selected memory cell. In either sensing mode, the state of the selected memory is then determined based on the amount of charge on the sensing node after the charging (in the first sensing mode) or discharging (in the second sensing mode) of the sensing node. In the second sensing mode, the sensing node discharges to the selected memory cell&#39;s bit line through a path of series connected NMOS transistors. For the first sensing mode, a current path from the selected memory cell to the sensing node includes cascaded PMOS transistors, where the cascaded PMOS transistors are connected in parallel with the series connected NMOS transistors used for the second sensing mode. 
       FIGS. 1A-5  describe examples of memory systems that can be used to implement the technology proposed herein.  FIG. 1A  is a functional block diagram of an example memory system  100 . In one embodiment, the components depicted in  FIG. 1A  are electrical circuits. Memory system  100  includes one or more memory dies  108 . The one or more memory dies  108  can be complete memory dies or partial memory dies. In one embodiment, each memory die  108  includes a memory structure  126 , control circuitry  110 , and read/write circuits  128 . Memory structure  126  is addressable by word lines via a row decoder  124  and by bit lines via a column decoder  132 . The row decoder  124  can include the drivers and other elements to bias the word lines for the different memory operations. The read/write circuits  128  include multiple sense blocks  150  including SB 1 , SB 2 , . . . , SBp (sensing circuitry) and allow a page of memory cells to be read or programmed in parallel, where a page is the unit in which data is written and/or read. A physical page is the physical unit of a number of cells into which data can be concurrently written and/or read, and a logical page a corresponding logical unit of data written into a physical page. More detail on sense amplifier circuits that can be used in the sense blocks  150  including SB 1 , SB 2 , . . . , SBp is given below with respect to  FIGS. 11-14 . 
     In some systems, a controller  122  is included in the same package (e.g., a removable storage card) as the one or more memory die  108 . However, in other systems, the controller can be separated from the memory die  108 . In some embodiments the controller will be on a different die than the memory die  108 . In some embodiments, one controller  122  will communicate with multiple memory die  108 . In other embodiments, each memory die  108  has its own controller. Commands and data are transferred between a host  140  and controller  122  via a data bus  120 , and between controller  122  and the one or more memory die  108  via lines  118 . In one embodiment, memory die  108  includes a set of input and/or output (I/O) pins that connect to lines  118 . 
     Control circuitry  110  cooperates with the read/write circuits  128  to perform memory operations (e.g., write, read, and others) on memory structure  126 , and includes a state machine  112 , an on-chip address decoder  114 , and a power control circuit  116 . The state machine  112  provides die-level control of memory operations. In one embodiment, state machine  112  is programmable by software. In other embodiments, state machine  112  does not use software and is completely implemented in hardware (e.g., electrical circuits). In other embodiments, state machine  112  can be replaced by a programmable microcontroller. Control circuitry  110  also includes buffers such as registers, ROM fuses and other storage devices for storing default values such as base voltages and other parameters. 
     The on-chip address decoder  114  provides an address interface between addresses used by host  140  or controller  122  to the hardware address used by the decoders  124  and  132 . Power control module  116  controls the power and voltages supplied to the word lines and bit lines during memory operations. Power control module  116  may include charge pumps for creating voltages. The sense blocks include bit line drivers. 
     State machine  112  and/or controller  122  (or equivalently functioned circuits), in combination with all or a subset of the other circuits depicted in  FIG. 2 , can be considered a control circuit that performs the functions described herein. The control circuit can include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor, FGA, ASIC, integrated circuit or other type of circuit. 
     The (on-chip or off-chip) controller  122  (which in one embodiment is an electrical circuit) may comprise one or more processors  122   c , ROM  122   a , RAM  122   b , a memory interface (MI)  122   d  and a host interface (HI)  122   e , all of which are interconnected. The storage devices (ROM  122   a , RAM  122   b ) store code (software) such as a set of instructions (including firmware), and one or more processors  122   c  is/are operable to execute the set of instructions to provide the functionality described herein. Alternatively, or additionally, one or more processors  122   c  can access code from a storage device in the memory structure, such as a reserved area of memory cells connected to one or more word lines. RAM  122   b  can be to store data for controller  122 , including caching program data (discussed below). Memory interface  122   d , in communication with ROM  122   a , RAM  122   b  and processor  122   c , is an electrical circuit that provides an electrical interface between controller  122  and one or more memory die  108 . For example, memory interface  122   d  can change the format or timing of signals, provide a buffer, isolate from surges, latch I/O, etc. One or more processors  122   c  can issue commands to control circuitry  110  (or another component of memory die  108 ) via Memory Interface  122   d . Host interface  122   e  provides an electrical interface with host  140  data bus  120  in order to receive commands, addresses and/or data from host  140  to provide data and/or status to host  140 . 
     In one embodiment, memory structure  126  comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping material such as described, for example, in U.S. Pat. No. 9,721,662, incorporated herein by reference in its entirety. 
     In another embodiment, memory structure  126  comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates such as described, for example, in U.S. Pat. No. 9,082,502, incorporated herein by reference in its entirety. Other types of memory cells (e.g., NOR-type flash memory) can also be used. 
     The exact type of memory array architecture or memory cell included in memory structure  126  is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure  126 . No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure  126  include ReRAM memories, magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architectures of the memory structure  126  include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like. 
     One example of a ReRAM, or PCMRAM, cross point memory includes reversible resistance-switching elements arranged in cross point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature. 
     Magnetoresistive memory (MRAM) stores data by magnetic storage elements. The elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the other plate&#39;s magnetization can be changed to match that of an external field to store memory. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created. 
     Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe—Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. In other embodiments, the memory cells of a PCM memory can have their data state set or reset through use of current pulses. Note that the use of “pulse” in this document does not require a square pulse, but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light, or other wave. 
     A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art. 
       FIG. 1B  depicts an example of memory structure  126 . In one embodiment, an array of memory cells is divided into multiple planes. In the example of  FIG. 1B , memory structure  126  is divided into two planes: plane  141  and plane  142 . In other embodiments, more or less than two planes can be used. In some embodiments, each plane is divided into a number of memory erase blocks (e.g., blocks  0 - 1023 , or another amount). In certain memory technologies (e.g. 2D/3D NAND and other types of flash memory), a memory erase block is the smallest unit of memory cells for an erase operation. That is, each erase block contains the minimum number of memory cells that are erased together in a single erase operation. Other units of erase can also be used. In other memory technologies (e.g. MRAM, PCM, etc.) used in other embodiments implementing the solution claimed herein, memory cells may be overwritten without an erase operation and so erase blocks may not exist. 
     Each memory erase block includes many memory cells. The design, size, and organization of a memory erase block depends on the architecture and design for the memory structure  126 . As used herein, a memory erase block is a contiguous set of memory cells that share word lines and bit lines; for example, erase block i of  FIG. 1B  includes memory cells that share word lines WL 0 _ i , WL 1 _ i , WL 2 _ i  and WL 3 _ i  and share bit lines BL 0 -BL 69 , 623 . 
     In one embodiment, a memory erase block (see block i) contains a set of NAND strings which are accessed via bit lines (e.g., bit lines BL 0 -BL 69 , 623 ) and word lines (WL 0 , WL 1 , WL 2 , WL 3 ).  FIG. 1B  shows four memory cells connected in series to form a NAND string. Although four cells are depicted to be included in each NAND string, more or less than four can be used (e.g., 16, 32, 64, 128, 256 or another number or memory cells can be on a NAND string). One terminal of the NAND string is connected to a corresponding bit line via a drain select gate, and another terminal is connected to the source line via a source select gate. Although  FIG. 1B  shows 69,624 bit lines, a different number of bit lines can also be used. 
     Each memory erase block and/or each memory storage unit is typically divided into a number of pages. In one embodiment, a page is a unit of programming/writing and a unit of reading. Other units of programming can also be used. One or more pages of data are typically stored in one row of memory cells. For example, one or more pages of data may be stored in memory cells connected to a common word line. A page includes user data and overhead data (also called system data). Overhead data typically includes header information and Error Correction Codes (ECC) that have been calculated from the user data of the sector. The controller (or other component) calculates the ECC when data is being written into the array, and also checks it when data is being read from the array. In one embodiment, a page includes data stored in all memory cells connected to a common word line. 
     In the example discussed above, the unit of erase is a memory erase block and the unit of programming and reading is a page. Other units of operation can also be used. Data can be stored/written/programmed, read or erased a byte at a time, 1K bytes, 512K bytes, etc. No particular unit of operation is required for the claimed solutions described herein. In some examples, the system programs, erases, and reads at the same unit of operation. In other embodiments, the system programs, erases, and reads at different units of operation. In some examples, the system programs/writes and erases, while in other examples the system only needs to program/write, without the need to erase, because the system can program/write zeros and ones (or other data values) and can thus overwrite previously stored information. 
     As used herein, a memory storage unit is the set of memory cells representing the smallest storage unit of operation for the memory technology to store/write/program data into the memory structure  126 . For example, in one embodiment, the memory storage unit is a page sized to hold 4 KB of data. In certain embodiments, a complete memory storage unit is sized to match the number of physical memory cells across a row of the memory structure  126 . In one embodiment, an incomplete memory storage unit has fewer physical memory cells than a complete memory storage unit. 
       FIG. 2  is a block diagram of example memory system  100 , depicting more details of one embodiment of controller  122 . As used herein, a flash memory controller is a device that manages data stored on flash memory and communicates with a host, such as a computer or electronic device. A flash memory controller can have various functionality in addition to the specific functionality described herein. For example, the flash memory controller can format the flash memory to ensure the memory is operating properly, map out bad flash memory cells, and allocate spare memory cells to be substituted for future failed cells. Some part of the spare cells can be used to hold firmware to operate the flash memory controller and implement other features. In operation, when a host needs to read data from or write data to the flash memory, it will communicate with the flash memory controller. If the host provides a logical address to which data is to be read/written, the flash memory controller can convert the logical address received from the host to a physical address in the flash memory. (Alternatively, the host can provide the physical address). The flash memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid pages of data to a new block, so the full block can be erased and reused). 
     The interface between controller  122  and non-volatile memory die  108  may be any suitable flash interface, such as Toggle Mode  200 ,  400 , or  800 . In one embodiment, memory system  100  may be a card-based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternate embodiment, memory system  100  may be part of an embedded memory system. For example, the flash memory may be embedded within the host. In other example, memory system  100  can be in the form of a solid-state drive (SSD). 
     In some embodiments, non-volatile memory system  100  includes a single channel between controller  122  and non-volatile memory die  108 , the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures, 2, 4, 8 or more channels may exist between the controller and the memory die, depending on controller capabilities. In any of the embodiments described herein, more than a single channel may exist between the controller and the memory die, even if a single channel is shown in the drawings. 
     As depicted in  FIG. 2 , controller  122  includes a front-end module  208  that interfaces with a host, a back-end module  210  that interfaces with the one or more non-volatile memory die  108 , and various other modules that perform functions which will now be described in detail. 
     The components of controller  122  depicted in  FIG. 2  may take the form of a packaged functional hardware unit (e.g., an electrical circuit) designed for use with other components, a portion of a program code (e.g., software or firmware) executable by a (micro) processor or processing circuitry that usually performs a particular function of related functions, or a self-contained hardware or software component that interfaces with a larger system, for example. For example, each module may include an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware or combination thereof. Alternatively, or in addition, each module may include software stored in a processor readable device (e.g., memory) to program a processor for controller  122  to perform the functions described herein. The architecture depicted in  FIG. 2  is one example implementation that may (or may not) use the components of controller  122  depicted in  FIG. 1A  (i.e. RAM, ROM, processor, interface). 
     Referring again to modules of the controller  122 , a buffer manager/bus control  214  manages buffers in random access memory (RAM)  216  and controls the internal bus arbitration of controller  122 . A read only memory (ROM)  218  stores system boot code. Although illustrated in  FIG. 2  as located separately from the controller  122 , in other embodiments one or both of the RAM  216  and ROM  218  may be located within the controller. In yet other embodiments, portions of RAM and ROM may be located both within the controller  122  and outside the controller. Further, in some implementations, the controller  122 , RAM  216 , and ROM  218  may be located on separate semiconductor die. 
     Front end module  208  includes a host interface  220  and a physical layer interface (PHY)  222  that provide the electrical interface with the host or next level storage controller. The choice of the type of host interface  220  can depend on the type of memory being used. Examples of host interfaces  220  include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface  220  typically facilitates transfer for data, control signals, and timing signals. 
     Back end module  210  includes an error correction code (ECC) engine  224  that encodes the data bytes received from the host, and decodes and error corrects the data bytes read from the non-volatile memory. A command sequencer  226  generates command sequences, such as program and erase command sequences, to be transmitted to non-volatile memory die  108 . A RAID (Redundant Array of Independent Dies) module  228  manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the non-volatile memory system  100 . In some cases, the RAID module  228  may be a part of the ECC engine  224 . Note that the RAID parity may be added as an extra die or dies as implied by the common name, but it may also be added within the existing die, e.g. as an extra plane, or extra block, or extra WLs within a block. A memory interface  230  provides the command sequences to non-volatile memory die  108  and receives status information from non-volatile memory die  108 . In one embodiment, memory interface  230  may be a double data rate (DDR) interface, such as a Toggle Mode  200 ,  400 , or  800  interface. A flash control layer  232  controls the overall operation of back end module  210 . 
     One embodiment includes a writing/reading manager  236 , which can be used to manage (in conjunction with the circuits on the memory die) the writing and reading of memory cells. In some embodiments, writing/reading manager  236  performs the processes depicted in the flowcharts described below. 
     Additional components of system  100  illustrated in  FIG. 2  include media management layer  238 , which performs wear leveling of memory cells of non-volatile memory die  108 . System  100  also includes other discrete components  240 , such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with controller  122 . In alternative embodiments, one or more of the physical layer interface  222 , RAID module  228 , media management layer  238  and buffer management/bus controller  214  are optional components that are not necessary in the controller  122 . 
     The Flash Translation Layer (FTL) or Media Management Layer (MML)  238  may be integrated as part of the flash management that may handle flash errors and interfacing with the host. In particular, MML may be a module in flash management and may be responsible for the internals of NAND management. In particular, the MML  238  may include an algorithm in the memory device firmware which translates writes from the host into writes to the memory structure  126  of die  108 . The MML  238  may be needed because: 1) the memory may have limited endurance; 2) the memory structure  126  may only be written in multiples of pages; and/or 3) the memory structure  126  may not be written unless it is erased as a block. The MML  238  understands these potential limitations of the memory structure  126  which may not be visible to the host. Accordingly, the MML  238  attempts to translate the writes from host into writes into the memory structure  126 . As described below, erratic bits may be identified and recorded using the MML  238 . This recording of erratic bits can be used for evaluating the health of blocks and/or word lines (the memory cells on the word lines). 
     Controller  122  may interface with one or more memory dies  108 . In one embodiment, controller  122  and multiple memory dies (together comprising non-volatile storage system  100 ) implement a solid-state drive (SSD), which can emulate, replace or be used instead of a hard disk drive inside a host, as a NAS device, in a laptop, in a tablet, in a server, etc. Additionally, the SSD need not be made to work as a hard drive. 
     Some embodiments of a non-volatile storage system will include one memory die  108  connected to one controller  122 . However, other embodiments may include multiple memory die  108  in communication with one or more controllers  122 . In one example, the multiple memory die can be grouped into a set of memory packages. Each memory package includes one or more memory die in communication with controller  122 . In one embodiment, a memory package includes a printed circuit board (or similar structure) with one or more memory die mounted thereon. In some embodiments, a memory package can include molding material to encase the memory dies of the memory package. In some embodiments, controller  122  is physically separate from any of the memory packages. 
       FIG. 3  is a perspective view of a portion of one example embodiment of a monolithic three-dimensional memory structure  126 , which includes a plurality memory cells. For example,  FIG. 3  shows a portion of one block of memory. The structure depicted includes a set of bit lines BL positioned above a stack of alternating dielectric layers and conductive layers. For example, purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. One set of embodiments includes between 108-216 alternating dielectric layers and conductive layers, for example, 96 data word line layers, 8 select layers, 4 dummy word line layers and 108 dielectric layers. More or less than 108-216 layers can also be used. As will be explained below, the alternating dielectric layers and conductive layers are divided into four “fingers” by local interconnects LI (isolation areas).  FIG. 3  only shows two fingers and two local interconnects LI. Below and the alternating dielectric layers and word line layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that in  FIG. 3 , the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the memory hole with materials including a charge-trapping layer to create a vertical column of memory cells. Each memory cell can store one or more bits of data. More details of the three-dimensional monolithic memory structure  126  is provided with respect to  FIG. 4 . 
       FIG. 4  depicts an example 3D NAND structure and shows physical word lines WLL 0 -WLL 47  running across the entire block. The structure of  FIG. 4  can correspond to a portion of one of the blocks of  FIG. 1B , including bit lines  311 ,  312 ,  313 ,  314 , . . . ,  319 . Within the block, each bit line is connected to four NAND strings. Drain side selection lines SGD 0 , SGD 1 , SGD 2  and SGD 3  are used to determine which of the four NAND strings connect to the associated bit line. The block can also be thought of as being divided into four sub-blocks SB 0 , SB 1 , SB 2  and SB 3 . Sub-block SB 0  corresponds to those vertical NAND strings controlled by SGD 0  and SGS 0 , sub-block SB 1  corresponds to those vertical NAND strings controlled by SGD 1  and SGS 1 , sub-block SB 2  corresponds to those vertical NAND strings controlled by SGD 2  and SGS 2 , and sub-block SB 3  corresponds to those vertical NAND strings controlled by SGD 3  and SGS 3 . 
       FIG. 5  illustrates another memory structure that can be used for the structure  126  of  FIG. 1A .  FIG. 5  illustrates a three-dimensional vertical cross-point structure, the word lines still run horizontally, with the bit lines oriented to run in a vertical direction. 
       FIG. 5  depicts one embodiment of a portion of a monolithic three-dimensional memory array structure  126  that includes a first memory level  412  positioned below a second memory level  410 . As depicted, the local bit lines LBL 11 -LBL 33  are arranged in a first direction (i.e., a vertical direction) and the word lines WL 10 -WL 23  are arranged in a second direction perpendicular to the first direction. This arrangement of vertical bit lines in a monolithic three-dimensional memory array is one embodiment of a vertical bit line memory array. As depicted, disposed between the intersection of each local bit line and each word line is a particular memory cell (e.g., memory cell Min is disposed between local bit line LBL 11  and word line WL 10 ). This structure can be used with a number of different memory cell structures. In one example, the particular memory cell may include a floating gate device or a charge trap device (e.g., using a silicon nitride material). In another example, the particular memory cell may include a reversible resistance-switching material, a metal oxide, a phase change memory (PCM) material, or a ReRAM material. The global bit lines GBL 1 -GBL 3  are arranged in a third direction that is perpendicular to both the first direction and the second direction. A set of bit line select devices (e.g., Q 11 -Q 31 ), such as a vertical thin film transistor (VTFT), may be used to select a set of local bit lines (e.g., LBL 11 -LBL 31 ). As depicted, bit line select devices Q 11 -Q 31  are used to select the local bit lines LBL 11 -LBL 31  and to connect the local bit lines LBL 11 -LBL 31  to the global bit lines GBL 1 -GBL 3  using row select line SG 1 . Similarly, bit line select devices Q 12 -Q 32  are used to selectively connect the local bit lines LBL 12 -LBL 32  to the global bit lines GBL 1 -GBL 3  using row select line SG 2  and bit line select devices Q 13 -Q 33  are used to selectively connect the local bit lines LBL 13 -LBL 33  to the global bit lines GBL 1 -GBL 3  using row select line SG 3 . 
     Referring to  FIG. 5 , as only a single bit line select device is used per local bit line, only the voltage of a particular global bit line may be applied to a corresponding local bit line. Therefore, when a first set of local bit lines (e.g., LBL 11 -LBL 31 ) is biased to the global bit lines GBL 1 -GBL 3 , the other local bit lines (e.g., LBL 12 -LBL 32  and LBL 13 -LBL 33 ) must either also be driven to the same global bit lines GBL 1 -GBL 3  or be floated. In one embodiment, during a memory operation, all local bit lines within the memory array are first biased to an unselected bit line voltage by connecting each of the global bit lines to one or more local bit lines. After the local bit lines are biased to the unselected bit line voltage, then only a first set of local bit lines LBL 11 -LBL 31  are biased to one or more selected bit line voltages via the global bit lines GBL 1 -GBL 3 , while the other local bit lines (e.g., LBL 12 -LBL 32  and LBL 13 -LBL 33 ) are floated. The one or more selected bit line voltages may correspond with, for example, one or more read voltages during a read operation or one or more programming voltages during a programming operation. 
     The memory systems discussed above can be erased, programmed/written and read. At the end of a successful programming process, the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages (Vts) for erased memory cells, as appropriate.  FIG. 6  illustrates example threshold voltage distributions for the memory cell array when each memory cell stores more than one bit of data in a multi-level cell (MLC) format, in this case three bits of data. Other embodiments, however, may use other data capacities per memory cell (e.g., such as one, two, four, or five bits of data per memory cell).  FIG. 6  shows eight threshold voltage distributions, corresponding to eight data states. The first threshold voltage distribution (data state) S 0  represents memory cells that are erased. The other seven threshold voltage distributions (data states) S 1 -S 17  represent memory cells that are programmed and, therefore, are also called programmed states. Each threshold voltage distribution (data state) corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. In one embodiment, data values are assigned to the threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a memory erroneously shifts to its neighboring physical state, only one bit will be affected. 
       FIG. 6  also shows seven read reference voltages, Vr 1 , Vr 2 , Vr 3 , Vr 4 , Vr 5 , Vr 6 , and Vr 7 , for reading data from memory cells. By testing (e.g., performing sense operations) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine what data state (i.e., S 0 , S 1 , S 2 , S 3 , . . . ) a memory cell is in. 
       FIG. 6  also shows seven verify reference voltages, Vv 1 , Vv 2 , Vv 3 , Vv 4 , Vv 5 , Vv 6 , and Vv 7 . When programming memory cells to data state S 1 , the system will test whether those memory cells have a threshold voltage greater than or equal to Vv 1 . When programming memory cells to data state S 2 , the system will test whether the memory cells have threshold voltages greater than or equal to Vv 2 . When programming memory cells to data state S 3 , the system will determine whether memory cells have their threshold voltage greater than or equal to Vv 3 . When programming memory cells to data state S 4 , the system will test whether those memory cells have a threshold voltage greater than or equal to Vv 4 . When programming memory cells to data state S 5 , the system will test whether those memory cells have a threshold voltage greater than or equal to Vv 5 . When programming memory cells to data state S 6 , the system will test whether those memory cells have a threshold voltage greater than or equal to Vv 6 . When programming memory cells to data state S 7 , the system will test whether those memory cells have a threshold voltage greater than or equal to Vv 7 . 
     In one embodiment, known as full sequence programming, memory cells can be programmed from the erased data state S 0  directly to any of the programmed data states S 1 -S 7 . For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state S 0 . Then, a programming process is used to program memory cells directly into data states S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , and/or S 7 . For example, while some memory cells are being programmed from data state S 0  to data state S 1 , other memory cells are being programmed from data state S 0  to data state S 2  and/or from data state S 0  to data state S 3 , and so on. The arrows of  FIG. 6  represent the full sequence programming. The technology described herein can also be used with other types of programming in addition to full sequence programming (including, but not limited to, multiple stage/phase programming). In some embodiments, data states S 1 -S 7  can overlap, with controller  122  relying on ECC to identify the correct data being stored. 
       FIG. 7A  is a flowchart describing one embodiment of a process for programming that is performed by controller  122 . In some embodiments, rather than have a dedicated controller, the host can perform the functions of the controller. In step  702 , controller  122  sends instructions to one or more memory die  108  to program data. In step  704 , controller  122  sends one or more addresses to one or more memory die  108 . The one or more logical addresses indicate where to program the data. In step  706 , controller  122  sends the data to be programmed to the one or more memory die  108 . In step  708 , controller  122  receives a result of the programming from the one or more memory die  108 . Example results include that the data was programmed successfully, an indication that the programming operation failed, and indication that the data was programmed but at a different location, or other result. In step  710 , in response to the result received in step  708 , controller  122  updates the system information that it maintains. In one embodiment, the system maintains tables of data that indicate status information for each block. This information may include a mapping of logical addresses to physical addresses, which blocks/word lines are open/closed (or partially opened/closed), which blocks/word lines are bad, etc. 
     In some embodiments, before step  702 , controller  122  would receive host data and an instruction to program from the host, and the controller would run the ECC engine  224  to create code words from the host data, as known in the art and described in more detail below. These code words are the data transmitted in step  706 . Controller  122  (e.g., writing/reading manager  236 ) can also scramble the data prior to programming the data in the memory. 
       FIG. 7B  is a flowchart describing one embodiment of a process for programming. The process of  FIG. 7B  is performed by the memory die in response to the steps of  FIG. 7A  (i.e., in response to the instructions, data and addresses from controller  122 ). In one example embodiment, the process of  FIG. 7B  is performed on memory die  108  using the one or more control circuits discussed above (see  FIG. 1 ), at the direction of state machine  112 . The process of  FIG. 7B  can also be used to implement the full sequence programming discussed above. The process of  FIG. 7B  can also be used to implement each phase of a multi-phase programming process. 
     Typically, the program voltage applied to the control gates (via a selected word line) during a program operation is applied as a series of program pulses. Between programming pulses are a set of verify pulses to perform verification. In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step  770  of  FIG. 7B , the programming voltage (Vpgm) is initialized to the starting magnitude (e.g., ˜12-16V or another suitable level) and a program counter PC maintained by state machine  112  is initialized at  1 . In step  772 , a program pulse of the program signal Vpgm is applied to the selected word line (the word line selected for programming). In one embodiment, the group of memory cells being programmed concurrently are all connected to the same word line (the selected word line). The unselected word lines receive one or more boosting voltages (e.g., ˜7-11 volts) to perform boosting schemes known in the art. If a memory cell should be programmed, then the corresponding bit line is grounded. On the other hand, if the memory cell should remain at its current threshold voltage, then the corresponding bit line is connected to Vdd to inhibit programming. In step  772 , the program pulse is concurrently applied to all memory cells connected to the selected word line so that all of the memory cells connected to the selected word line are programmed concurrently. That is, they are programmed at the same time or during overlapping times (both of which are considered concurrent). In this manner all of the memory cells connected to the selected word line will concurrently have their threshold voltage change, unless they have been locked out from programming. 
     In step  774 , the appropriate memory cells are verified using the appropriate set of verify reference voltages to perform one or more verify operations. In one embodiment, the verification process is performed by applying the testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltage. 
     In step  776 , it is determined whether all the memory cells have reached their target threshold voltages (pass). If so, the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step  778 . If, in  776 , it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step  780 . 
     In step  780 , the system counts the number of memory cells that have not yet reached their respective target threshold voltage distribution. That is, the system counts the number of memory cells that have, so far, failed the verify process. This counting can be done by the state machine, the controller, or other logic. In one implementation, each of the sense blocks will store the status (pass/fail) of their respective cells. In one embodiment, there is one total count, which reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, separate counts are kept for each data state. 
     In step  782 , it is determined whether the count from step  780  is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during a read process for the page of memory cells. If the number of failed memory cells is less than or equal to the predetermined limit, than the programming process can stop and a status of “PASS” is reported in step  778 . In this situation, enough memory cells programmed correctly such that the few remaining memory cells that have not been completely programmed can be corrected using ECC during the read process. In some embodiments, step  780  will count the number of failed cells for each sector, each target data state or other unit, and those counts will individually or collectively be compared to a threshold in step  782 . 
     In another embodiment, the predetermined limit can be less than the number of bits that can be corrected by ECC during a read process to allow for future errors. When programming less than all of the memory cells for a page, or comparing a count for only one data state (or less than all states), than the predetermined limit can be a portion (pro-rata or not pro-rata) of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed or other criteria. 
     If number of failed memory cells is not less than the predetermined limit, than the programming process continues at step  784  and the program counter PC is checked against the program limit value (PL). Examples of program limit values include 12, 20 and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step  788 . This is one example of a program fault. If the program counter PC is less than the program limit value PL, then the process continues at step  786  during which time the Program Counter PC is incremented by 1 and the program voltage Vpgm is stepped up to the next magnitude. For example, the next pulse will have a magnitude greater than the previous pulse by a step size (e.g., a step size of 0.1-0.5 volts). After step  786 , the process loops back to step  772  and another program pulse is applied to the selected word line so that another iteration (steps  772 - 786 ) of the programming process of  FIG. 7B  is performed. 
     In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation (e.g., see read reference voltages Vr 1 , Vr 2 , Vr 3 , Vr 4 , Vr 5 , Vr 6 , and Vr 7 , of  FIG. 6 ) or verify operation (e.g. see verify reference voltages Vv 1 , Vv 2 , Vv 3 , Vv 4 , Vv 5 , Vv 6 , and Vv 7  of  FIG. 6 ) in order to determine whether a threshold voltage of the concerned memory cell has reached such level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the certain value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased). 
     There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. Other read and verify techniques known in the art can also be used. 
     In some embodiments, controller  122  receives a request from the host (or a client, user, etc.) to program host data (data received from the host) into the memory system. In some embodiments, controller  122  arranges the host data to be programmed into units of data. For example, controller  122  can arrange the host data into pages, partial pages (a subset of a page), word line units, blocks, jumbo blocks, or other units. 
     Step  772  of  FIG. 7B  includes applying a program voltage pulse on the selected word line. Step  774  of  FIG. 7B  includes verification, which in some embodiments comprises applying the verify reference voltages on the selected word line. As steps  772  and  774  are part of an iterative loop, the program voltage is applied as a series of voltage pulses that step up in magnitude. Between voltage pulses, verify reference voltages are applied. This is depicted in  FIG. 7C , which shows program voltage pulses  792 ,  794  and  796 , applied during three successive iterations of step  772 . Between program voltage pulses  792 ,  794  and  796 , the system tests the memory cells to determine whether threshold voltages of the memory cells are greater than the respective verify reference voltages by applying the verify references voltages as verify pulses. 
       FIG. 8  is a flowchart describing a sensing operation performed in order to read data from the memory cells. In step  800 , a pass voltage is applied to unselected word lines so that unselected memory cells on a NAND string are conducting, which enables the system to test whether the selected memory cell conducts in response to the read reference voltage. This pass voltage is often referred to as Vread. In step  802 , the appropriate read reference voltage, also referred to as Vcgr, is applied to the selected word line. In one example of a system that stores one bit per memory cell, Vcgr=0 v, or a small voltage near v. In step  804 , all of the bit lines are pre-charged. In one example embodiment, the bit lines are pre-charged by charging a capacitor in the sense amplifier and then putting the bit line in communication with the charged capacitor so that the bit line charges up. In step  806 , the bit line is allowed to discharge, for example, by discharging the capacitor. After a predetermined time period, referred to as the “integration time” or “strobe time” the voltage of the capacitor is sampled to see whether the respective memory cell(s) conducted in step  810 . If the memory cell conducts in response to Vcgr, then the threshold voltage of the memory cell is less than Vcgr. If Vcgr=0 v and the memory cell turns on, then the memory cell is in the erased state and the data stored is 1. If Vcgr=0V and the memory cell does not turn on, then the memory cell is in the programmed state and the data stored is 0. 
     The storage density of a memory circuit such as in  FIG. 1B, 3, 4 , or  5  can be increased by storing more data states in each of the cells. For instance,  FIG. 6  shows a 3-bit per cell example, where each memory cell can store one of 8 different data states. Storing 8 or even more states per cell presents a number of difficulties, as either the different state distributions need to be stored closer together, a larger range of threshold voltages (or “Vt window”) needs to be used, or both. However, programming memory cell states more closely together becomes increasingly complicated, as obtaining sufficiently tight, well-separated distributions can significantly lower performance; and accurate data retention is harder as a smaller amount of threshold voltage drift can make reading the data difficult or even impossible. With respect to increasing the Vt window, going to higher threshold voltages allows for more states to be added at the high Vt end, but at the cost of increased operating voltages, increasing power consumption and possibly shortening device life. Alternately, the Vt window can be increased by extending it further into negative threshold voltages. 
     In the example of  FIG. 6 , only the distribution of the lowest, or erased, data state of S 0  has a threshold voltage below 0V. Storing more states with negative threshold values can increase the Vt window. This is illustrated in  FIGS. 9A and 9B . 
       FIG. 9A  is similar to  FIG. 6 , but only shows the lowest threshold state S 0  and the highest of threshold state SN. The effective Vt window in this example is from around −1V or a few tenths of a volt less on the low side to several volts on the high side (in the 4-6V range, for example, such as 5V), with the other state distributions falling in between these two values. If S 0  is the only state whose Vt is below 0V, this can be read by setting the control gate of the memory cell to ground at step  802  in the flow of  FIG. 8 .  FIG. 9B  illustrates lowering the bottom end of the Vt window deeper into negative Vt values. In this example, the S 0  distribution is at or below Vt=−2.5V to −1.5V (e.g., around −2V or so), adding around 1V to the Vt window and providing additional room for more data states, such as illustrated by S 1 . However, distinguishing between different data states with negative thresholds has historically been difficult. Therefore,  FIGS. 10A-10C  present some techniques for sensing negative Vt values. 
       FIGS. 10A-10C  are simplified representations showing a NAND string having only one memory cell connected in series between a source side select gate SGS and a drain side select gate SGD. To simplify the figures, other, non-selected memory cells of the NAND string are not shown but would be biased at a read pass voltage allowing them to conduct for any stored data states. The NAND string is connected on the source end to a source line SRC and on the drain side to a bit line, which is in turn connected to a sense amplifier. 
       FIG. 10A  illustrates a sensing operation for the memory cell using a negative word line voltage CGRV to sense a negative threshold. Aside from the negative word line voltage, the NAND string is biased as is common for reading positive threshold voltage values. The drain and source select gates are set to an on state by applying a sufficiently high voltage along the control lines to their gates, SGD=H and SGD=H, and the source line voltage VSRC is set to ground, VSRC=0V, or other low voltage. The bit line is pre-charged to positive voltage higher than VSRC; for example, VBL can be in the 0.2-1.0V range, such as 0.5V or somewhat lower. The bit line is then discharged by the current Icell, where the rate of discharge is based on the threshold voltage of the memory cell and the word line voltage CGRV on its control gate. After an integration time, the sense amp connected to bit line latches the result. Although this approach can be used for negative Vt states, it requires the use of negative voltages, such as the CGRV=−1.5V illustrated in  FIG. 10A . However, negative voltages are typically not used on a memory device as they require additional circuitry to generate and are often difficult to maintain. Additionally, negative voltage levels near or below the −1.5V range are difficult to produce, limiting how deeply the Vt window can be extended downward. 
     Another approach to sensing negative Vt states, but without negative voltages, is illustrated in  FIG. 10B . In  FIG. 10B , the biasing of the NAND string is changed to allow a non-negative voltage, such as CGRV=0V, to be used to sense negative Vt states. The select gates (and any non-selected memory cells) of the NAND string are again biased to be on, but now the source line is raised above ground; for example, VSRC can be in the 0.8-1.5V range, such as about 1V or a little higher. This places the source of the selected memory cell at VSRC and allows for negative Vt sensing with a non-negative word line voltage. To discharge the bit line by Icell through the selected memory cell, the bit line is then pre-charged to a level above the source line; for example, VBL can be in the 1.2-1.8V range, such as around 1.5V, placing it a few tenths of a volt above VSRC. After discharging the bit line for a sensing interval, the result is then latched by the corresponding sense amp for the read result. Although this technique allows for negative Vt sensing without negative voltages, it cannot go much deeper into negative Vt values than about −1.1V. 
       FIG. 10C  illustrates another approach that can extend sensing into deeper negative Vt values while only using non-negative voltages. In the sensing arrangement of  FIG. 10C , the source line is raised to a voltage level above the bit line voltage level, VSRC&gt;VBL&gt;0V. Rather than determining whether a selected memory cell is conducting by discharging the bit line through the memory cell into the source line, the source line is now discharged through the memory cell into the bit line and sense amp.  FIG. 10C  illustrates this by the current Icell running upwards towards the bit line, rather than downwards toward the source line as in  FIGS. 10A and 10B . For example, the source line can be set in the range VSRC=2.0-2.5V, such as low as 2V, and the bit line voltage, VBL, set a few tenths (e.g., 0.2-0.4V) of a volt less than VSRC. With CGRV=0V, this allows for sensing of a Vt down to about, for example, −1.8V or even further depending on the VSRC and VBL levels. The approach of  FIG. 10C  is utilized in the following sense amplifier embodiments that can be used for deep negative threshold voltage sensing and techniques for reducing the noise that can occur in such sensing operations. 
       FIG. 11  illustrates an embodiment of a sense amplifier  1110  that can be used to perform a sensing operation using the approach of  FIG. 10C . The sense amplifier  1110  can correspond to one of the sense blocks SB 1 , SB 2 , . . . , SBp  150  in  FIG. 1A . A selected memory cell  1101  is connected between a source line SRC  1103  and a bit line BL  1105 . Other memory cells (e.g. of same NAND string) are also connected between source line SRC  1103  and bit line BL  1105 ; however, those other memory cells are not depicted in  FIG. 11 . The sense amplifier  1110  is typically selectively connectable to multiple bit lines through a column decoding circuit not shown in  FIG. 11 . The selected bit line BL  1105  can be discharged on the path labelled “BL path” through the series connected switches BLC 2   1111  and BLC  1113  to the discharge transistor DT  1115 , and then on through the discharge transistor DT  1115  to the discharge node SRCGND. The control gate of the discharge transistor DT  1115  is connected in a diode type arrangement to the internal (to the sense amp) bit line node BLI between BLC 2   1111  and BLC  1113 . When both of BLC 2   1111  and BLC  1113  are on, the current flowing to the bit line BL  1105  from the memory cell  1101  can discharge along the BL path to the discharge node SRCGND; and when both of BLC 2   1111  and BLC  1113  are turned off, the discharge BL path is cut off and the control gate of DT  1115  is left to float at the level on the node BLI between BLC 2   1111  and BLC  1113 . 
     To the right in  FIG. 11 , a second discharge path labelled “SEN path” allows for the sensing node SEN to also discharge through the switch XXL  1121  to the discharge transistor DT  1115 . When XXL  1121  is on, any charge stored on the capacitor Csen  1123  will discharge at a rate determined by the control gate voltage on discharge transistor DT  1115 . After discharging over a sensing period, a sensing result based on the level on the node SEN can then be set in the latch  1125  and the shifted out over the data bus DBUS. The SEN node can be pre-charge by the latch  1125 . 
     The voltage levels and timing for the switches in  FIG. 11  are controlled by the elements on the memory array such as the read/write circuits  128  and sense blocks SB 1 , SB 2 , SBp  150  in  FIG. 1A , here represented by the bias circuitry of control block  1131 . A sensing operation, such as a read or verify, is done in two stages. After the initial biasing of the source line SRC, bit line BL, the selected memory and other elements (such as select gates and non-selected memory cells in a NAND embodiment), the switches BLC 2   1111  and BLC  1113  are turned on. The bit line is then discharged along the BL path through the discharge transistor. The degree of discharge, or whether there is any current discharged at all, will depend on the word line voltage CGRV on the selected memory cell&#39;s control gate and the selected memory cell&#39;s threshold voltage Vt. Consequently, the voltage on the node BLI will depend on the memory cell&#39;s data state and how this data state corresponds to the read level CGRV biasing the selected memory cell. After the voltage level on the node BLI is sufficiently stabilized, the switches BLC 2   1111  and BLC  1113  are turned off, leaving the node BLI, and consequently the control gate of the discharge transistor DT  1115 , to float at the level set during the bit line discharge phase. 
     Once the switches BLC 2   1111  and BLC  1113  are turned off and the gate of the discharge transistor DT  1115  is floating at the level set during the bit line discharge phase, the conductivity of the transistor DT  1115  is based on the conductivity of the selected memory cell. In the sense node discharging phase, the switch XXL  1121  is turned on so that the previously charged sense node SEN and the sense node capacitor Csen  1123  can discharge through discharge transistor DT  1115  along the SEN path. After a discharge time, the value at the SEN node can then be captured by latch  1125 . As the discharge rate along the SEN path depends on the gate voltage on the discharge transistor DT  1115 , which in turn depends on the state of the selected memory cell, the latched value corresponds to the data state. For a memory cell biased as illustrated in  FIG. 10C , VCGR=0V is used for sensing the lowest (i.e., most negative) data state, with the VCGR value increased to sense higher Vg states, both less negative Vt states and positive Vt states. 
     A number of variations in  FIG. 11  are possible. For example, rather than having switches BLC 2   1111  and BLC  1113  connected in series between BL  1105  and the central SCOM node as shown, one of these can be moved to between the node BLI and the gate of the discharge transistor DT  1115 . This arrangement will also allow the level on the control gate of discharge transistor DT  1115  to be set by the voltage level on the BLI node when both switches are on; and close off the BL path and leave the control gate on discharge transistor DT  1115  to float when both are turned off. In another variation, the BL path and the SEN path could discharge through different transistors, but where the gates on the different transistors are tied together. These and other variations can be incorporated in the embodiment of  FIG. 11  and other embodiments described below. 
     To more accurately sense data values, noise during the sensing process should be minimized to the extent practical, particularly when larger number of states are to be stored with the available Vt window. To this end, several techniques can be applied to the sense amp embodiments illustrated in  FIG. 11  to provide improved product reliability and performance. Two sources of noise relate to the discharge transistor DT  1115  of  FIG. 11 , where noise on either the gate of the transistor, or, equivalently node BLI, and noise along the current paths through the transistor can throw off the sensing process. 
     To reduce noise on the current path through discharge transistor DT  1115 , a clamp device and an auxiliary current source, or “keeper current,” can be introduced into the sense amp circuit to clamp the drain voltage of the discharge transistor DT  1115  during sensing. This can help block the possible noise through discharge transistor DT  1115  and provide a current flow through discharge transistor DT  1115  to the node SRCGND. The node SRCGND will typically be a node on a commonly regulated SRCGND line to which the sense amp and other sense amps are connected, so that during a sensing operation all of the connected sense amps may be discharging current into the SRCGND line. The introduction of the auxiliary keeper current helps to remove the critical noise at SRCGND node during sensing. 
     To reduce noise at the control gate of the discharge transistor DT  1115 , a de-coupling capacitor can be introduced to compensate and correct the possible coupling when the switches BLC 2   1111  and BLC  1113  switch off to prepare for discharge of sense node. This solution will help to correct the possibly unwanted coupling to the gate of the discharge transistor DT  1115  and provides a more accurate sensing result. The de-coupling capacitor can track operating conditions, such as the temperature, and device corners in order to obtain more accurate sensing results. This can be useful to provide accurate sensing results with temperature dependence and device corners, since the level of how negative a Vt can be sensed may depend on the temperature and device corners. 
       FIG. 12  includes these immediately above-described elements to reduce noise, as well as other elements that can be incorporated into various embodiments for a sense amp circuit, such as can be incorporated in the sense blocks SB 1 , SB 2 , . . . , SBp  150  of  FIG. 1A . In  FIG. 12 , the elements of  FIG. 11  are repeated along with a decoupling capacitor Cdecop  1212  connected to the node BLI and a supplemental current source NLO  1218  to help stabilize the SRCGND node during transition to the sensing phase. 
     More explicitly,  FIG. 12  illustrates a memory cell  1201  connected between a source line SRC  1203  and a bit line BL  1205 . The memory cell  1201  can be part of a NAND string of charge storing memory cells, such as described with respect to  FIGS. 3 and 4 , a memory cell based on a phase change memory material (PCM), such as described above with respect to  FIG. 5 , or of other memory technology. The bit line BL  1205  is connected to the sense amplifier through the decoding circuitry, here represented by the bit line select (BLS) switch  1206 . (In this discussion, the switches are generally named according to their control signals from the bias control circuit, such that, for example, the control signal BLS for switch  1206  is also used for its name.) 
     After the bit line select switch BLS  1206 , the bit line BL  1205  is connected to the internal bit line BLI through switch BLC 2   1211 , and then through switch BLC  1213  to the central comment sensing node SCOM. The node SCOM is connected through the discharge transistor DT  1215  to allow the node SCOM to discharge to SRCGND. Similar to  FIG. 11 , this provides the discharge path labelled BL path from SRC  1203  through the selected memory cell  1201  to the selected bit line, on through the series connected switches BLC 2   1211  and BLC  1213  to the discharge transistor DT  1215 , and finally on to SRCGND. The control gate of DT  1215  is again connected to the node at BLI, so that when the switches BLC 2   1211  and BLC  1213  are turned off, the control gate of DT  1215  will be left floating at the level on BLI. 
     To the right on  FIG. 12 , the SEN node with the capacitor Csen  1223  is connected to the SCOM node through the switch XXL  1221 , and then on to discharge transistor DT  1215  to provide the second discharge path (SEN path) from the SEN node to SRCGND for the second of the sensing operations. The SEN node is also connected to the latch  1225  to latch the result of the sensing operation, which is turn connected to the data bus DBUS. Depending on the embodiment, the latch  1225  can include a number of individual latches for use in multi-state reading and writing or for other data operations. The elements of  FIG. 12  described so far are largely as described above with respect  FIG. 11 , except that to simplify  FIG. 12  the bias control block ( 1131  of  FIG. 11 ) to provide the control signals for the various switches is not shown (but is to be included in the device). Some of the waveforms provided to the elements in  FIG. 12  are shown in  FIG. 13 , as described below. 
       FIG. 12  explicitly shows a number of elements not shown in  FIG. 11 , but which can be added in various embodiments. A switch NLO 2   1207  is connected between SRCGND and a node between BLS  1206  and BLC 2   1211 , allowing for BL  1205  or BLI to be pre-charged or set to various voltage levels from SRCGND. A switch INV  1216  is connected between the discharge transistor DT  1215 , allowing for the sense amp to be selectively isolated from SRCGND, as the SRCGND node may be connected to a line commonly shared by a large number of other sense amps. A switch GRS  1217  is connected in parallel with DT  1215 , allowing DT  1215  to be bypassed if, for example, the level on BLI is low so that DT  1215  is off, and the sense amp needs to discharge the DCOM node above DT  1215  to SRCGND. These and various other switches can be added to the sense amp circuit to improve operation and versatility. 
     The embodiment of  FIG. 12  also includes some additional elements that do not directly enter into the main sensing operations described here, but can also add to its versatility. A switch BIAS  1204  can connect the bit line to a level BLBIAS that can be used in biasing a selected bit line for various memory operations. Also, another path to the central SCOM node is provided through a switch BLX  1241  (and possibly additional switches) to a high sense amp voltage VHSA. Although not used in the sensing operations mainly described here (where all data states are sensed by discharging the SRC line  1203  through the memory cell  1201  into the sense amp), more standard sensing operations as illustrated in  FIG. 10A  (where the sense amp/bit line discharge through the memory cell  1201  into SRC  1203 ) could use the switch BLX  1241 . For example, rather than sense all states as illustrated by  FIG. 10C , successively raising CGRV from 0V through the various read valued, the approach of  FIG. 10C  could be used for negative Vt states and then switch to the approach of  FIG. 10A  for the non-negative Vt states that do not require a negative CGRV value when using the approach of  FIG. 10A . 
     As described above with respect to  FIG. 11 , the sense amplifier arrangement of  FIG. 12  can be used to perform a sensing operation on a selected memory cell by a first phase using the first discharge path “BL path” to discharge the source line  1203  through the selected memory cell  1201  and on through the discharge transistor DT  1215  to SRCGND. This will set the node at BLI, and the control gate on DT  1215 , to a voltage level dependent on the data state of the memory relative to the voltage level CGRV on the corresponding word line. Once the level on BLI node is stabilized, the switches BLC 2   1211  and BLC  1213  are turned off, leaving the control gate of DT  1215  to float, and the conductivity of DT  1215  to be determined by the conductivity of the selected memory cell  1201 . In the second phase, the switch XXL  1221  is turned on to discharge the pre-charged node SEN through DT  1215  to SRCGND at a rate based on the conductivity of DT  1215 , which is in turn based on the conductivity of the memory cell  1201 . After a discharge period, the level on SEN is captured by the latch  1225  to give the sensing result. 
     To reduce noise on the BLI node, and the gate of discharge transistor DT  1215 , when the switches BLC 2   1211  and BLC  1213  are turned off during the transition, the de-coupling capacitor Cdecop  1212  is introduced. This capacitor helps to compensate and correct for the possibly of unwanted coupling to the gate of the discharge transistor DT  1215  and provide a more accurate sensing result. The lower plate of Cdecop  1212  is connected to the BLI node, with the upper plate connected to a level BLI_BST that can allow the de-coupling capacitor Cdecop  1212  to track the operating conditions, such as temperature, and device corners in order to obtain a more accurate sensing result. In some embodiments, Cdecop  1212  can be implemented as a transistor with both its source and drain connected to the BLI node and its control gate connected to the level BLI_BST. 
     Another source of noise during the transition between phases and the subsequent discharging of the SEN node can come from noise in the SRCGND level, where the SRCGND line will typically be shared by a large number of sense amps that will concurrently be dumping current into the SRCGND line. A supplemental current source through the switch NLO  1218  is connected to a sense amp voltage LVSA to provide a keeper current through the discharge transistor  1215 . A clamp device DCL  1219  clamps the drain voltage (at node DCOM) of discharge transistor DT  1215  during the sensing. These devices help block the possible noise through discharge transistor DT  1215  and keep a constant current through to the commonly regulated node SRCGND. This can help remove the detrimental noise at SRCGND node during sensing. 
       FIG. 13  illustrates waveforms for the control signals from the biasing circuitry for some of the control signals for  FIG. 12  in one embodiment for a sensing operation. The waveforms are marked at times t 0 -t 10 , where: t 0 -t 3  is preparatory period; t 3 -t 6  is the first phase where the source line SRC  1203  is discharged into the sense amp and the level on the control gate of the discharge transistor DT  1215  set; t 6 -t 8  is the transition between phases; t 8 -t 9  is the second phase when the SEN node is discharged along the second discharge, or SEN, path; and t 9 -t 10  is the strobe period when the value on the SEN node is latched. 
     The control signals for some of the devices in  FIG. 12  are not included in the waveforms of  FIG. 13 . INV  1216  in on, and GRS  1217  is off during the all of the shown period. The bit line select switch BLS  1206  is on for the whole period, or at least until the first phase concludes at t 6 . As discussed above, the switches BIAS  1204  and BLX  1241  are not active in the sensing operation described with respect to  FIG. 13  and would both be off DCL  1219  acts as a voltage clamp for the node DCOM and has its gate set for this purpose. 
     Starting at t 0  for  FIG. 13 , BL  1205 , the nodes BLI, SCOM, SEN and SRCGND are all low, as are the control signals on NLO 2   1207 , BLC 2   1211 , BLC  1213 , XXL  1221 , the CLK signal to the plate of Csen  1223 , and NLO. Between t 0  and t 1 , the array is biased. This can include setting the SRC line  1203 , the selected and unselected word lines, select gates, or other levels needed to bias a selected memory cell  1201 , depending on the architecture of the array. 
     Between t 1  and t 2 , the initial levels for the sense amp are set. The SRCGND line is raised to an initial high value and NLO 2   1207  is turned on, as is BLC 2   1211 . This sets the values on BL  1205  and the node at BLI high. Once the bit line and internal bit line are set, between t 2  and t 3 , NLO 2  is turned off and SRCGND is lowered to the level used during the following discharge phases. 
     The first discharge phase along the first discharge path labelled BL path in  FIGS. 11 and 12 , when the source line SRC  1203  discharges through the selected memory cell  1201  into the sense amp, begins at t 3  when BLC  1213  is turned on, connecting the central common sense node SCOM to BLI. The bit line BL  1205  and BLI begin to discharge between t 3  and t 4 , while SCOM charges up. The level on all these three top traces will depend on the conductivity of the selected memory cell, where HC is a highly conductive cell, MC a cell of middle conductivity, and NC a non-conducting cell. As shown, BL, BLI and SCOM will stabilize at t 4  with the high conductively cell highest, the non-conducting cell lowest, and the intermediate state in the middle. To prepare for the next phase, at t 4  the SEN node is pre-charged, which can be done from the latch  1225 , followed by raising the CLK signal to Csen  1223  at t 5 , which further raises the level on SEN. By t 6 , the level on BLI (and the control gate of DT  1215 ) is stabilized at a level based on the conductivity of the selected memory cell and the SEN node is pre-charged, setting the conditions for the second discharge phase. 
     At t 6 , BLC 2   1211  and BLC  1213  are turned off, isolating the BLI node, so that from t 7  on, BLI is floating (represented by the broken lines) at a level based the memory cell&#39;s conductivity. This cuts off the discharge path from the source line SRC  1203  and causes the bit line  1205  to go high, where it will stay for the rest of the process, and SCOM to discharge through the discharge transistor DT  1215  and bounce about. This also results in coupling noise on BLI and the gate of DT  1215 , as illustrated in  FIG. 13  by the jagged outlining of the BLI levels between t 6  and t 8 . The decoupling capacitor Cdecop  1212  is used to help correct for this noise, where the level BLI_BST on the upper plate of Cdecop  1212  can track temperature and device corners to provide a more accurate sensing result. 
     The fluctuations on the SCOM node and the BLI node also introduce noise on SRCGND, which can be very sensitive to noise, as shown by the jagged outline of SRCGNE between t 6  and t 7 . To help remove this noise, the supplemental current from NLO  1218  and the clamp DCL  1219  to keep the level at DCOM help to stabilize the SRCGND node and the SCOM node. As shown on the bottom trace, NLO  1218  is turned on to provide the supplemental keeper current at t 7 . 
     At t 6 , the SEN node has been pre-charged and the control gate of DT  1215  and SRCGND have be stabilized. XXL  1221  is then turned on to discharge the SEN node. The transition in XXL  1221  can again introduce noise for SRCGND, which the keeper current from NLO  1218  will also help stabilize. When XXL  1221  turns on at t 8 , SCOM and SEN begin to discharge at a rate determine by the gate voltage on DT  1215 , which was in turn set by the conductivity of the memory cell. As shown, between t 8  and t 9  the HC state discharges most rapidly and the NC state shows almost no discharge, while the MC state falls in the middle. At  9 -t 10 , the level on SEN is latched, after which the sensing operation is complete. 
       FIG. 14  is a flowchart describing one embodiment of a process for a sensing operation for the sense amplifier of  FIG. 12  using the waveforms of  FIG. 13 . Beginning at step  1401 , the selected memory cell  1201 , source line  1203 , and any other array elements (select gates, non-selected memory cell on the same NAND string, etc.) are biased in preparation for the sensing operation. This corresponds the t 0 - t  section of  FIG. 13 . In step  1403 , the bit line BL  1205  and internal bit line BLI are charged up, corresponding to the period of t 1 -t 3  of  FIG. 13 . The first discharge phase then begins in step  1405 . 
     In step  1405 , the switch BLC  1213  is turned on and the source SRC  1203  begins the first discharging phase through the selected memory cell  1201  along the first discharge path (BL path), eventually stabilizing at a level depending on the conductivity of the selected memory cell  1201 . The level on BLI during this process is also the level on the control gate of the discharge transistor DT  1215 , corresponding to step  1407 . Steps  1405  and  1407  are during the period t 3 -t 6  of  FIG. 13 . 
     The SEN node is pre-charged at step  1409 . In the embodiment of  FIG. 13 , this occurs during the period t 4 -t 6 , during the first discharge phase along the BL path. Other embodiments can have this step earlier or later, as long as the SEN node is prepared for subsequent discharge along the SEN path at step  1415 . 
     Steps  1411  and  1413  are part of the transition between the two phases, corresponding to the period t 6 - 8  in the embodiment of  FIG. 13 . At step  1411 , the BL path for discharge is cut off and the control gate of DT  1215  is set to float at the level on BLI by turning off of the switches BLC 2   1211  and BLC  1213 . The capacitor Cdecop  1212  helps to reduce the noise on BLI, where having the upper plate connected to the level BLI_BST can help with variations due to operating conditions or process corners. At step  1413 , the auxiliary keeper current from NLO  1218  begins, helping to stabilize SRCGND. 
     The second discharge phase for the second discharge path, the SEN path, corresponding to the period t 8 - 9 , begins at step  1415 . The switch XXL  1221  is turned on and the SEN node discharges through DT  1215 , whose control gate was set based on the conductivity of the selected memory cell  1201  at step  1407 . For the embodiment of  FIG. 13 , the keeper current is kept running during this period to keep SRCGND noise down. At step  1417 , the level on SEN is latched to provide the sensing result and concluding the sense operation. 
     The discussion now considers an additional set of embodiments for a sense amplifier circuit, such as can be used for determining the data states of non-volatile memory cells. These additional embodiments can include many of the components of the embodiments described above, but can also include additional elements. More specifically, these additional embodiments include a first path and a second path between a selected bit line and the SEN node to which the sensing capacitor, CSEN, is attached. The first path is used for performing sensing operations in a first mode, in which current conducted through a selected memory cell flows into the sense amplifier and is conducted along the first path to the SEN node to charge up the sensing capacitor. The second path is used for conventional sensing operation in which charge on the sensing capacitor is conducted along the second path and discharged through a selected memory cell. In both modes, the voltage level on the SEN node can then be used to determine the data state of the selected memory cell. 
     The first current path, used when the sensing is based on currently flowing into the sense amplifier, uses PMOS transistors for conducting current from the bit line to the sensing node. The second current path, used when the sensing is based on currently flowing out of sense amplifier, uses NMOS transistors for conducting current from the sensing node to the bit line. The PMOS devices of the first path are in parallel with the NMOS devices of the second current path. Both sensing directions can be achieved by use of a different set of control signals to bias the sense amplifier, so that the sense amplifier is capable to handle the current of a selected memory cell in both directions. 
       FIG. 15  is a circuit diagram of an additional embodiment of a sense amplifier operable in a first mode and a second mode. Relative to  FIGS. 11 and 12 ,  FIG. 15  repeats a number of sense amplifier elements and includes a number of elements that can be included in the embodiments of  FIGS. 11 and 12 , but where not shown there in order to simplify the discussion given above.  FIG. 15  adds several elements, providing the first current path that can used to charge the SEN node when operating in the first sensing mode in which the SEN node and sensing capacitor are charged from a selected memory cell. A number of the elements (e.g., NLO 2   1207 , BLC 2   1211 , BLI_BST  1212 , DCL  1219 , DT  1215 , GRS  1217 , INV  1216 ) illustrated in  FIG. 12  are not included in  FIG. 15  and following figures, but alternate embodiments can also include some or all of these elements into the embodiments described with respect to  FIG. 15  and subsequent figures. 
     More specifically, starting on the left hand side,  FIG. 15  illustrates a memory cell  1501  with its source side connected to a source line CELSRC  1503  and with its drain side connected to a bit line that connects to the sense amplifier at the bit line node BL  1505 . The node BL  1505  can be biased by a level BLBIAS through a switch BIAS  1504 , here implemented as an NMOS device. The bit line node BL  1505  can be connected to an internal bit line BLI by way of a bit line select switch BLS  1506 , again implemented as an NMOS device. Depending on the embodiment, internal bit line BLI can be connected to one or multiple bit lines BL  1505  and the bit line select switch BLS  1506  can used to connect the sense amp to a selected memory cell on a selected bit line for sensing operations, for both data read and program verify and to also set the bias level along the bit line to programming bias levels, such as program inhibit and program enable. Depending on the embodiment, the memory cell  1501  can be an individual memory cell or one or a number of memory cells connected between CELSRC  1503  and BL  1505 , such as in a NAND string. A single word line  1502  is shown in  FIG. 15  and would use to bias the memory cell, such as to a sensing voltage for a read or verify operation or to apply a programming voltage to a selected memory cell, where, in the case of a NAND string for example, WL  1502  is representative of the set of word lines and selected gate lines used to bias NAND string. 
     BLI is connected to the common node SCOM of the sense amplifier through a bit line clamp switch BLC  1513 , again implemented as an NMOS device, and the SCOM node is in turn connected to the sense node SEN though the NMOS device of switch XXL  1521 . The sensing capacitor Csen  1523  is connected to the SEN on its top (as represented here) plate and to the control signal CLKSA on its bottom plate. The sensing node SEN is connected to the data latch  1525 . Depending on the embodiment, each sense amplifier can be connected to a number of different data latches, such as can be used for different bits stored on a memory cell when used with a multi-level cells (MLC) memory. The common node SCOM is also connectable to the level VHSA though the NMOS device of switch XXL  1541  and to the level SRCGND thought the NMOS device of switch NLO  1518 . 
     Other elements in  FIG. 15 , not represented in  FIGS. 11 and 12 , can include the PMOS device of switch  1563 , through which BLX  1241  is connectable to VHSA, and NMOS device of switch  1561 , though which BLX  1241  is connectable to level SRCGND. As shown in  FIG. 15 , both of switches  1563  and  1561  have their control gates connected to the control signal INV_S so that when INV_S is high the NMOS of  1561  will be on and the PMOS of  1563  will be off, and when INV_S is low the NMOS of  1561  will be off and the PMOS of  1563  will be on. The devices  1561  and  1563  can be used to set the bit line BL  1505  to a program inhibit or a program enable level during a programming operation, for example. 
     Between the sensing node SEN and the latch  1525  is an NMOS device switch BLQ  1571 , where the internal sensing bus line between BLQ  1571  and latch  1525  is labelled SBUS. The internal sensing bus line SBUS is also connectable to the level VHLB by NMOS device switch LPC  1573  that can be used to pre-charge the line SBUS. SBUS is also connected to the level VLOP through the series connected NMOS devices of switch STB  1567  and  1565 , whose gate is connected to the SEN node. The NMOS devices  1565  and STB  1567  can be used to discharge the SBUS mode during a sensing operation.  FIG. 15  also includes a control block  1531  that includes the bias circuitry configured to provide the control signals used by the sense amplifier during its operation. 
     The elements of  FIG. 15  described so far are all either used in the second sensing mode, in which the SEN node is discharged through a selected memory cell, or shared between the second mode and the first mode, in which the SEN node is charged through the selected memory cell. As described in more detail below, in the second, traditional sensing mode, the SEN node is discharged through selected memory cell to BL  1505  through the NMOS devices BLC  1513  and XXL  1521 , which operate as series connected source follower devices. To provide a first current path between BL  1505  and SEN for use in the first sensing mode, in which the SEN node is charged through the selected memory cell  1501  from CELSRC  1503 , several PMOS devices are added in parallel with the NMOS devices of the second current path. These additional PMOS devices are configured to be source follower devices when current flows in the reverse direction from BL  1505  to SEN. 
     More specifically, in parallel with the NMOS device BLC  1513  between BLI and SCOM is the PMOS device PBLC  1514 . Between SCOM and SEN, a PMOS PXXL  1522  is connected in parallel with the NMOS XXL  1521 . A PMOS switch PBLX  1542  is also connected in parallel with NMOS BLX  1541  for use in the first sensing mode. Before describing the operation of the circuit of  FIG. 15  in the first sensing mode, a brief description of the second sensing mode is given. 
     In a traditional sensing operation (second sensing mode) of a sense amplifier, a selected memory cell  1501  is biased by setting the word line WL  1502  to a read voltage. The read voltage is applied to the word line  1502  of the selected memory cell and, in the case of a NAND string, would also include biasing the non-selected memory cells and select gates to be conducting. The degree to which the selected memory cell  1501  conducts depends on the level of the read voltage applied to the word line of the selected memory cell relative the threshold voltage of the memory cell, which in turn depends on the data state programmed to the memory cell. 
     To perform a sensing operation, either a data read or a program verify in the second mode, the SEN node and sensing capacitor Csen  1523  are pre-charged. The SEN node is pre-charged and then discharged along the path from SEN to BL  1505  through XXL  1521  and BLC  1513  at a rate dependent on the conductivity of the memory cell  1501 , which in turn depends on the read voltage applied to WL  1502  relative to the threshold voltage of the memory cell  1501 . The voltage level on SEN and Csen  1523  determines the level on the gate of  1565 , which determines the conductivity of  1565 . The voltage on SBUS can also be pre-charged through LPC  1573 . After allowing the SEN node to discharge for some interval of time, the strobe transistor STB  1567  is turned on for a sensing, or strobe, interval to allow SBUS to discharge at a rate dependent of the SENS voltage level. Depending on the level on the internal bus line SBUS at the end of the strobing interval, either a 0 or a 1 sensing result is latched into the latch  1525  based on whether the SBUS voltage level is above or below a reference level. 
       FIG. 16  is a flowchart presenting an embodiment for a second mode sensing operation in which the sensing node in a sense amplifier circuit is discharged through a selected memory cell. At step  1601  the SEN node is pre-charged. For example, SEN can be pre-charged though BLQ  1571  and LPC  1573  from the VHLS level, after which BLQ  1571  and LPC  1573  can be turned off. The SBUS line can then be pre-charged through LPC  1573  from the VHLS level at step  1603 . The memory cell (or, in the case of NAND memory, the NAND string) is biased for a sensing operation at step  1605 , where, depending on the embodiment, step  1605  can be performed before, after, or currently with steps  1601  and  1603 . 
     Once the sense amplifier is biased to its pre-charge levels at steps  1601  and  1603  and the selected memory cell  1501  (or NAND string) is biased at step  1605 , the SEN node is discharged along the second current path through XXL  1521  and BLC  1513  to BL  1505  at step  1607 . The rate at which the SEN discharges will depend on the conductivity of memory cell  1501 , which, in the case of a NAND memory cell, in turn depends on the level of the read voltage applied to word line  1502  relative to the threshold voltage of the memory cell  1501 . For example, if the read voltage is less than the memory cell&#39;s threshold voltage memory cell  1501  will not conduct and SEN will not discharge. As the gate of  1565  is connected to the SEN node, the voltage on SEN will determine the conductivity of  1565 . After allowing an interval for SEN to discharge, at step  1609  a strobe signal of the control signal to STB  1567  is asserted for a strobe interval allowing SBUS to discharge an amount determined by the voltage level on SEN. At the end of the strobe interval, the level on SBUS relative to a reference level is latched into the latch  1525  as either a 0 or 1 to determine the result of the sensing operation. 
       FIG. 17  illustrates the discharge of the SEN node through a selected memory cell  1501  to CELSRC of step  1607  of  FIG. 16  and the strobe on STB  1567  of step  1609  of  FIG. 16 . To pre-charge the SEN node at step  1601  in the second sensing mode, the switches XXL  1521 , PXXL  1522 , and STB  1567  are all turned off and switch BLQ  1571  and LPC  1573  are turned on. This provides a path from VHLB to SEN, allowing the SEN node and the sensing capacitor Csen  1523  to be pre-charged from the VHLB level. (This pre-charge of the SEN node can be performed as illustrated in  FIG. 18 , where it is also included in the first sensing node.) To pre-charge the SBUS line at step  1603 , the switch BLQ  1571  is turned off, the switch STB  1567  is off, and the switch LPC  1573  is on, allowing the SBUS line to charge from the level on VHLB. (The pre-charge of SBUS can be performed as illustrated below in  FIG. 20 , where it is also included in phase  3  of the first sensing node.) 
     Once the SEN node and SBUS are pre-charged, the SEN node is discharged through the selected memory cell  1501 . The selected memory cell  1501  is biased by setting a read voltage on the word line  1502  and setting the source line CELSRC  1503  to low voltage level. In the case of a NAND string, the non-selected memory cells and selected gates are biased to be conductive. The degree to which the selected memory cell  15011  will conduct will depend on the threshold voltage of the selected memory cell  1501  and the level of the read voltage along word line WL  1502  relative to this threshold value. The series connected, cascaded NMOS switches XXL  1521  and BLC  1513  are on, along with the bit line select switch BLS  1506 , with the parallel connected PMOS devices PXXL  1522  and PBLC  1514  of first current path turned off, and the other switches out SCOM (NLO  1518 , BLX  1541 , PBLX  1542 ) turned off. This provides the second current path through the source followers of XXL  1521  and BLC  1513  for the SEN node, and the sensing capacitor Csen  1523  to discharge at step  1607  through the selected memory cell  1501  to CELSRC  1503 . This is as illustrated by the arrow, where the amount of discharge (or lack of discharge) will depend on the level of the read voltage on WL  1502  relative to the threshold voltage of the selected memory cell  1501 . 
     After a sensing interval for the discharge time, a strobe pulse is applied at STB  1567 , corresponding to step  1609 . The voltage level on NMOS  1565  is determined by the voltage level on SEN, so that the degree to which SBUS will (or will not) discharge (as represented the arrow to VLOP) will reflect the relationship of the read voltage to the selected memory cells data state as reflected in its threshold voltage. The latching of the level on SBUS at step  1611  can then be performed. 
       FIGS. 18-21  illustrate an embodiment for a sensing operation for the sense amplifier circuit of  FIG. 15  when operating in the first sensing mode, when the sensing node SEN and sensing capacitor Csen  1523  are charged though the selected memory cell  1501  along the first current path from BLI to SEN.  FIG. 21  is a flowchart corresponding to the phases illustrated in  FIGS. 17-20 . 
       FIG. 18  illustrates a pre-charge phase, or phase  1 , for a sensing operation in the first sensing mode. In the pre-charge phase the bit line BL  1505  and source line CELSRC  1503  are pre-charged to a target voltage V(CELSRC). For a NAND based embodiment, this will also raise the channel of the NAND string to V(CELSRC). As shown on the left of  FIG. 17 , this can be accomplished by setting BLBIAS to V(CELSRC) and turning on the switch BIAS  1504  to set BL  1505  to V(CELSRC) and setting CELSRC  1503  to V(CELSRC). To limit this pre-charging to these elements and the selected memory cell  1501 , the switches BLC  1513 , NLO  1518 , XXL  1521 , PXXL  1522 , BLX  1541  and PBLX  1542  are all turned off (as indicated by the X through these devices) by their biasing control signals from control block  1531 . The INV_S level can also betaken high at this point (or other point prior to phase  2 ) to turn off PMOS  1563  and turn on  1563 . 
     As shown on the right hand side of  FIG. 18 , the sensing node SEN and sensing capacitor Csen  1523  are pre-charged from VHLS by turning on LPC  1573  and BLQ  1571 . As STB  1567 , XXL  1521  and PXXL  1522  are all off, the charge from VHLS accumulates on SEN and sensing capacitor Csen  1523 . 
       FIG. 19  illustrates a settling phase, or phase  2 , in which the voltage levels on the sense amplifier circuit are stabilized for a sensing operation in the first sensing mode. As illustrated by the arrow on the left hand side of  FIG. 18 , the bit line is settled by use of the cascaded PMOS devices PBLC  1514  and PBLX  1542 . In more detail, the level on CELSRC  1503  is maintained at the first mode sensing level of  2   v , but, relative to  FIG. 18 , the switch BIAS  1504  is now turned off. As in  FIG. 18 , BLC  1513 , NLO  1518 , and the parallel pair of XXL  1521  and PXXL  1522  are all off. Also, as in  FIG. 18 , BLX  1541  is off and INV_S is high, so that NMOS  1561  is on and PMOS  1563  is off PBLX  1542  is now on, providing a path from SCOM to SRCGND. As PBLC  1514  is also on, this provides a current path as indicated by the arrow from BL  1505  through the cascaded source follower PMOS devices PBLC  1514  and PBLX  1542  to SRCGND, allowing BL to settle down. 
     With respect to the SEN node, in the stabilization phase (phase  2 ) the SEN node is discharged to ˜1V, with the local threshold voltage variation of NMOS  1565  compensated for in the result of the discharge. As in  FIG. 18 , the SEN node remains cut off from the SCOM node by having both XXL  1521  and PXXL  1522  off. The SEN node having been pre-charged as in  FIG. 18 , LPC  1573  is now off while BLQ  1571  remains on. To discharge the SEN node, STB  1567  is on. As SEN is connected to the gate of NMOS  1565 , and both of BLQ  1571  and STB  1567  are biased to be on, NMOS  1565  is basically a diode connected transistor with the SEN being applied to the gate of NMOS  1565 . This will allow SEN to discharge to a level determined by the threshold voltage Vth of NMOS  1565 . If the lower plate of the sensing capacitor is at ˜1V, this results in the sense node SEN will discharge to VLOP+Vth=−1V, cancelling or compensating the local Vt variations between the different sense amplifies on the die. 
       FIG. 20  illustrates a SEN node charging phase, or phase  3 , of an embodiment for the first sensing mode. Relative to phase  2  in  FIG. 19 , PXXL  1522  is now turned on and BLQ  1571  is turned off. The level of CLKSA is stepped down from ˜1V to V. As the source line CELSRC  1503  is at a relative high sensing level ( 2   v ), current will flow from the source lines and through the selected memory cell  1501  to BL  1505  at a rate dependent on the read voltage applied to the word line WL  1502  relative to the threshold voltage level of the selected memory cell  1501 . (As before, in the case of a NAND embodiment, the non-selected memory cells and select gates of the selected NAND string will be biased to be on.) The first current path of the cascaded PMOSs PBLC  1514  and PXXL  1522  (as illustrated by the arrow from the selected memory cell  1501 ), where the transistors act as source followers and let the SEN node and the upper plate of the sensing capacitor Csen  1523  accumulate charge at a rate based on the conductance of the selected memory cell  1501 . Depending on the level of current Icell through the selected memory cell, SEN may stay at ground (0V), rise from ground slowly, or rise rapidly. After an accumulation sensing interval, PXXL  1522  can be turned off to trap the accumulated charge on SEN. 
     In phase  3 , the SBUS line is also pre-charged. With BLQ  1571  and STB  1567  off, LPC  1573  is turned on. This allows for SBUS to be pre-charged form VHLB. Once SBUS is pre-charged, LPC  1573  can be turned off. 
       FIG. 21  illustrates the strobe phase (phase  4 ) of the first sensing mode, in which the result is stored in the latch  1525 . As illustrated in  FIG. 20 , charge is accumulated on the SEN node over the sensing interval during phase  3 , where the amount of accumulated charge is based on the conductivity of the selected memory cell  1501  in response to the applied read voltage. As the sensing node SEN is connected to the gate of the NMOS  1565 , the amount of accumulated charge on SEN will determine the conductivity of NMOS  1565 . The process of discharging the SEN node in phase  2  ( FIG. 19 ) cancels the threshold voltage Vth of NMOS  1565  so that the voltage level accumulated on SEN will have the Vth variation removed. By applying a strobe (briefly asserting a control signal for a sensing interval) to turn on STB  1567 , SBUS will discharge at a rate based on the voltage level V(SEN) on SEN, which is in turn based on the data state stored in the selected memory cell  1501  relative to the read voltage applied to the word line  1502 . If V(SEN)=(Icell*tSense)/C, where C is capacitance of Csen  1523 , is greater than a reference value (such as 1V for the process described here), SBUS is discharged. The result of the sensing can then be latched into latch  1525 . 
     Referring back to  FIG. 19  and the settling phase, or phase  2 , in which the voltage levels on the sense amplifier circuit are stabilized for a sensing operation in the first sensing mode, this phase included settling the bit line BL  1505  by use of a path through SCOM, PBLX  1542  and the switch of NMOS  1561  to SRCGND. The gate of NMOS  1561  is controlled by the signal INV_S. In  FIG. 19 , INV_S is high so that the NMOS  1561  is on. In a program operation, the value of INV_S can be set based on the result of a preceding program verify operation. When INV_S=high, this indicates that the selected memory cell failed the preceding program verify and that a subsequent verify operation will need to be performed, so that the bit line BL  1505  will be discharged as part of this subsequent verify by setting INV_S high. 
     When INV_S=low, this indicates that the selected memory cell has passed a preceding program verify and that a subsequent verify operation need not be performed. The memory cell can be locked out from further verify, in which case the bit line BL  1505  need not be discharged for a subsequent verify, saving on power. If INV_S is low, the NMOS  1561  will be off, cutting off the path from bit line BL  1505  through SCOM, PBLX  1542  and the switch of NMOS  1561  to SRCGND. In some modes of operation, such as “no lock-out”, it can be useful to still be able the discharge BL  1505  to SRCGND. To able be able to discharge BL  1505  independently of the INV_S level and without using the PBLX  1542  path, an additional PMOS path between SCOM and SRCGND can be added in parallel with NLO  1518 .  FIG. 22  illustrates such an alternate embodiment. 
       FIG. 22  is a circuit diagram of an alternate embodiment of a sense amplifier operable in a first mode and a second mode. Relative to  FIG. 15 ,  FIG. 22  adds the PMOS PNLO  1519  in parallel with the NMOS NLO  1518  between SCOM and SRCGND. This provides a path between BLI and SRCGND through the series connected PMOS devices PBLC  1514  and PNLO  1519  operating as source follower devices. This provides a path through which BL  1505  can be discharged to SRCGND regardless of the level on INV_S. 
       FIG. 22  is also marked to illustrate an alternate embodiment for the process illustrated in  FIG. 19  for the settling phase, or phase  2 , in which the voltage levels on the sense amplifier circuit are stabilized for a sensing operation in the first sensing mode. On the right had side, the SEN node is again discharged to VLOP+Vth=−1V as described above with respect to  FIG. 19 . To settle down BL  1505 , PBLC  1514  is now cascaded with PNLO  1519  so that from SCOM the current path is now though PNLO  1519  to SRCGND. 
     The control signals for biasing the elements of the sense amplifier circuit of  FIGS. 15 and 22  are provided by the control block  1531 . These control signals can include both the gate voltages for the various transistors and also the values applied at lines such as INV_S and VLOP.  FIGS. 23 and 24  illustrate embodiments for some elements of the bias-voltage generation circuitry of the control block  1531 . 
       FIG. 23  is a diagram of an embodiment of a bias-voltage generation circuit that can provide control gate voltages for some of the PMOS elements of the sense amplifier embodiments in  FIGS. 15 and 22 . More specifically, the circuit of  FIG. 23  can provide bias levels for the PMOS devices of PBLC  1514 , PXXL  1522 , and PBLX  1542  also a CELSRC level for use in the first sensing mode described with respect to  FIGS. 18-22 . In the first sensing mode of  FIGS. 18-22 , as the current from a selected NAND string or memory cell flows into the sense amplifier (such as is illustrated with respect to  FIG. 10C ), the usual roles of the source and drain are reversed and the bit line serves the role normally filled by source line. Because of this, the biasing circuit of  FIG. 22  references the bias levels relative to a target bit line level, VBL_TARGET. Other voltages, such as the read voltage applied to the word line of a selected memory cell, can similarly be biased relative to this target bit line level, much the way in which the levels of a traditional sensing operation (in which current flows from the bit lines) are referenced relative to the source line&#39;s level. 
     The target bit line voltage VBL_TARGET for BL  1505  is received at the node  2301 . The value of VBL_TARGET will vary depending on the embodiment, but a typical value can be around 2V, such as some tenths of a volt less to perhaps a volt higher. Relative to VBL_TARGET, the target level of CELSRC for  FIGS. 18-22  will somewhat higher to reflect a voltage drop across the selected memory cell and the bit line and other elements (such as non-selected memory cells and select gates of a NAND string) between source line CELSRC  1503  and BL  1505 . The target voltage for CELSRC is provided from a node  2303 , where the voltage drop across the selected memory cell is emulated by the voltage source  2305  and the voltage drop along the bit line is emulated by the voltage source  2307 . 
     The target voltage levels of PBLC, PBLX, and PXXL are all lower than VBL_TARGET and are supplied from nodes between  2301  and the low voltage level on the sense amplifier of VSSSA. (As noted above, switches and their control signals are similarly named, so that PBLC, for example, is used for both the PMOS transistor PBLC  1514  and the control signal applied to its control gate.) A diode connected PMOS  2311  connected the VBL_TARGET node  2301  and, though current source  2323 , VSSSA provides a first drop down in the voltage of VBL_TARGET. The target voltage for PBLC is provided at node  2313  below the diode connected PMOS  2311 . A resistor R 1   2315  provides an additional voltage drop for providing the target voltage for PBLX at node  2317 , with a second additional voltage drop provided by resistor R 2   2319  for the target voltage of PXXL at node  2321 . 
       FIG. 24  is a diagram of an embodiment of a bias-voltage generation circuit that can provide the bias level used in discharging the sensing node SEN of the sense amplifier embodiments in  FIGS. 15 and 22 . More specifically, the circuit of  FIG. 24  provides the VLOP level below the transistor  1565  of  FIGS. 15 and 22  to level that compensates for the threshold voltage Vth of the NMOS transistor  1565  during the discharging of the SEN node in the stabilizing of the sense amplifier in phase  2  as represented in  FIGS. 19 and 22 . 
     The input to the circuit of  FIG. 24  is the same CLKSA value as applied to the lower plate of the sensing capacitor Csen  1523 . During phase  2 , when the SEN node and top plate of the are discharged, CLKSA is at its high level of around 1V, for example, before being dropped to its low value of VSSSA at phase  3 . To discharge SEN to VLOP+Vth=1V, VLOP is biased to 1V-Vth. Connected between the CLKSA input and VSSSA,  FIG. 24  includes series connected NMOS transistor  2401  and NMOS transistor  2403 . The transistor  2401  can receive a high sense amplifier voltage level VDDSA at its gate so that it is on and the voltage across the transistor corresponds to any drop across BLQ  1571  and STB  1567  when these are on, as in phase  2 . NMOS  2403  is diode connected across NMOS  2401 , having its gate connected to the CLKSA input. As this mimics the connection of NMOS  1565  to the SEN node, by sizing NMOS  2403  similarly to NMOS  1565  so that they have the same Vth, this can provide the wanted Vth offset from CLKSA in the VLOP. The target VLOP level can be provided from node  2405  between NMOS  2403  and the current source  2407 . When CLKSA is subsequently stepped down to 0V in phase  3 , this will bring the voltage level on SEN also to 0V. 
       FIG. 25  is a flowchart describing one embodiment of a process for a sensing operation for the sense amplifier of  FIG. 15  in the first sensing mode, in which current flows into the sense amplifier. The flow of  FIG. 25  corresponds to the phase  1  of  FIG. 18 , phase  2  of  FIG. 19  or alternate embodiment  FIG. 22 , phase  3  of  FIG. 20 , and phase  4  of  FIG. 21 . 
     Steps  2501  and  2503  are part of the pre-charge phase, or phase  1 , as illustrated in  FIG. 18 . At step  2501  the selected bit line BL  1505 , including the selected NAND string or memory cell  1501 , and source line CELSRC  1503  are pre-charged to the target level of for CELSRC, where the bit line BL  1505  can be pre-charged through BIAS  1504  from the BLBIAS line. The target value for the voltage level on CELSRC can be provided from the circuit of  FIG. 23 , which can be part of the control block  1531 . At step  2503  the SEN node and top plate of the sensing capacitor Csen  1523  are pre-charged from VHLB though LPC  1573  and BLQ  1571 . Steps  2501  and  2503  can be performed concurrently or sequentially in either order, depending on the embodiment. 
     Steps  2505  and  2507  are part of the settling or stabilization phase, or phase  2 , as illustrated in  FIG. 19  or  FIG. 22 . In step  2505  the switch BIAS  1504  is turned off while the source line CELSRC  1503  is maintained at the target level for CELSRC, so that BL  1505  is allowed to settle by discharging through the bit line select switch BLS  1506  and through PBLC  1514  to the low level of SRCGND. In the embodiment of  FIG. 19 , INV_S is high and PBLC  1514  is cascaded with PBLX  1542  and the path continues through  1561  to SRCGND. In the embodiment of  FIG. 22 , INV_S can be either high or low and PBLC  1514  is cascaded with PNLO  15419  to SRCGND. At step  2507 , the SEN node is discharged though BLQ  1571 , STB  1567 , and  1565  to VLOP while CLKSA is at ˜1V. The value on VLOP can be set to a target level by the circuit of  FIG. 24 , which can be part of the control block  1531 . As described above, this allows for local variations of the threshold voltage Vth of NMOS  1565  from sense amplifier to sense amplifier across the memory die to be cancelled. Steps  2505  and  2507  can be performed concurrently or sequentially in either order, depending on the embodiment. 
     Once the sense amplifier has been pre-charged and settled in phases  1  and  2 , in phase  3  the selected memory cell  1501  and elements of the sense amplifier are biased to determine the data state stored on the selected memory cell  1501  as illustrated in  FIG. 20 . At step  2509  the CLKSA level is stepped down from −1V to VSSSA (i.e., ground or 0V). As illustrated in embodiment of  FIG. 24 , the level on VLOP is based on CLKSA so that when CLKSA goes to ground, so will VLOP. At step  2511 , the selected memory cell  1501  is biased to conduct current into the sense amplifier at a rate dependent on the data stored in the memory cell. Biasing the selected memory cell  1501  can include maintaining CELSRC  1503  at its target level and applying a sensing voltage to the word line WL  1502 . This process can be used for both verify and data read operations and sensing voltage will depend on the operation and, in multi-level cell (MLC) embodiments, the state being sensed. Depending on the embodiment, the biasing of a selected memory cell can also include applying other bias levels. For example, in the case of a NAND memory embodiment, the non-selected memory cells and select gates of the NAND string of the selected memory cell  1501  will be biased to be on. 
     The sense amplifier is also biased to accumulate charge on the SEN node and top plate of sensing capacitor Csen  1523  at step  2513 , where the amount of charge stored on the SEN node and sensing capacitor Csen  1523  will depend on the data state of the selected memory cell  1501 , such as its threshold voltage relative to the sensing voltage applied to the word line WL  1502 . In addition to stepping down CLKSA in step  2509  to allow charge to accumulate on the SEN node, PBLC  1514  and PXXL  1522  are turned on, where the voltage levels for the control signals of these devices can be the target values provided from the biasing circuit of  FIG. 23 . The cascaded PMOSs of PBLC  1514  and PXXL  1522  operate as source followers and allow SEN to charge up based on the current from the selected memory cell  1501  at step  2515  based on the biasing of steps  2511  and  2513 . 
     Along with accumulating charge on the SEN node, the SBUS line is also pre-charged in phase  3  at step  2517 . By turning LPC  1573  on, and BLQ  1571  and STB  1567  off, SBUS can be pre-charged from VHLB. 
     Steps  2519 ,  2521 , and  2523  are part of the strobe phase, or phase  4 , as illustrated in  FIG. 21 . After accumulating the current through the selected memory cell  1501  for an interval in phase  3 , at step  2519  the path from BL  1505  to SEN is cut off, such as by turning off PXXL  1522 . The level on SEN will determine the amount of current NMOS  1565  will conduct. At step  2521 , a strobe is applied to the control gate of STB  1567  so that SBUS will discharge by an amount dependent on the amount of current through NMOS  1565 , which is in turn based on the level on SEN, and interval of the duration of the strobe pulse. After the strobe at step  2521 , the sensing result is latched into latch  1525 . 
     According to a first set of aspects, a non-volatile memory circuit includes a plurality of memory cells, a bit line connected to one or more of the memory cells, a sense amplifier connectable to the bit line, and one or more control circuits connected to the memory cells and the sense amplifier. The sense amplifier includes a sensing capacitor and a data latch. The one or more control circuits are configured, in a first sensing mode, to: bias a selected one of the memory cells to conduct current into the sense amplifier at a level dependent on a data state stored in the selected memory cell; bias the sense amplifier accumulate charge on the sensing capacitor to an amount dependent on the level of current conducted into the sense amplifier; and latch a first sensing result into the data latch based on the amount of change accumulated on the sensing capacitor. 
     Other aspects include a method that includes: biasing a selected memory cell to conduct current into a sense amplifier at a level dependent on a data state stored in the selected memory cell; biasing the sense amplifier accumulate charge on a sensing capacitor of the sense amplifier to an amount dependent on the level of current conducted into the sense amplifier; and latching a sensing result into a data latch based on the amount of charge accumulated on the sensing capacitor. 
     Yet more aspects include a system that includes a sense amplifier having: a first node connectable to a selected memory cell; a sensing capacitor; a sense node connected to the sensing capacitor; a first path between the first node and the sense node; a second path between the first node and sense node; and one or more biasing circuits. The one or more biasing circuits are configured to: sense the selected memory cell in a first sensing mode by charging the sensing capacitor from current conducted along the first path from the selected memory cell; and sense the selected memory cell in a second sensing mode by discharging the sensing capacitor by current conducted along the second path and through the selected memory cell. 
     For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment. 
     For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them. 
     For purposes of this document, the term “based on” may be read as “based at least in part on.” 
     For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects. 
     For purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects. 
     The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.