Patent Publication Number: US-11652186-B2

Title: Avalanche photo-transistor

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 16/405,153, entitled “Avalanche Photo-Transistor,” filed May 7, 2019, which claims the benefit under 35 U.S.C. § 119(e) of U.S. Patent Application No. 62/667,640, entitled “Avalanche Photo-Transistor,” filed May 7, 2018, both of which are incorporated herein by reference in their entirety. 
    
    
     BACKGROUND 
     Light propagates in free space or through an optical medium. The light can be coupled to a transducer that coverts an optical signal to an electrical signal for processing. However, transducers can be inefficient or leaky resulting in a loss of optical energy. 
     SUMMARY 
     This specification describes technologies relating to an avalanche photo-transistor (APT) for sensing applications. The technology utilizes a three-terminal solution with an interim doping region (e.g., a &gt;10 18  cm −3  dopant concentration heavily-doped p+ layer) between a detection region (e.g., Ge layer) and a multiplication region (e.g., a Si layer). The interim doping region can be separately biased from the detection region and multiplication region using a separate terminal to sweep the generated carriers from the detection region to the multiplication region and amplify the generated carriers in the multiplication region. 
     In general, one innovative aspect of the subject matter described in this specification can be embodied in a device including a detection region configured to absorb light incident on a first surface of the detection region and generate one or more charge carriers in response to absorbing the incident light, a first terminal in electrical contact with the detection region and configured to bias the detection region, an interim doping region, having a doping concentration of a first type dopant that is greater than a threshold doping concentration, where the one or more charge carriers flow toward the interim doping region, a second terminal in electrical contact with the interim doping region and configured to bias the interim doping region, a multiplication region configured to receive the one or more charge carriers flowing from the interim doping region and generate one or more additional charge carriers in response to receiving the one or more charge carriers, and a third terminal in electrical contact with the multiplication region and configured to bias the multiplication region, where the interim doping region is located in between the detection region and the multiplication region. 
     Other embodiments of this aspect include corresponding systems, apparatus, and computer programs, configured to perform the actions of the methods, encoded on computer storage devices. 
     These and other embodiments can each optionally include one or more of the following features. In some implementations, the detection region can be a crystalline germanium layer, and the multiplication region can be a crystalline silicon layer. The detection region can be operated under non-avalanche mode and the multiplication region can be operated under avalanche mode. The first type of dopant of the interim doping region can be a p-type dopant, where a threshold doping concentration is at least 10 18  cm −3  of p-type dopant in a crystalline silicon layer. 
     In some implementations, the interim doping region is adjacent to the detection region, and where a second surface of the interim doping region is co-planar with the first surface of the detection region. In some implementations, the interim doping region surrounds the detection region. 
     In some implementations, a bias voltage different across the multiplication region can be less than 7 volts. A bias voltage difference across the detection region can be less than 3 volts. 
     In general, another aspect of the subject matter described in this specification can be embodied in methods that include the actions of applying a first voltage to a first terminal of an avalanche photo-transistor device, where the first terminal is in electrical contact with a detection region of the avalanche photo-transistor device, applying a second voltage to a second terminal of the avalanche photo-transistor device, where the second terminal is in electrical contact with an interim doping region of the avalanche photo-transistor device, applying a third voltage to a third terminal in electrical contact with a multiplication region of the avalanche photo-transistor device, generating, within the detection region, one or more charge carriers from incident light on a surface of the detection region, providing, through the interim doping region, the one or more charge carriers from the detection region to the multiplication region, generating, within the multiplication region, one or more additional charge carriers from the one or more charge carriers, and providing, using the avalanche photo-transistor device, a detection measurement based in part on the one or more additional charge carriers. 
     These and other embodiments can each optionally include one or more of the following features. In some implementations, the incident light includes one or more pulses of light traveling in a medium and reflected by an object, and the detection measurement includes identifying a direct time or an indirect phase or an indirect frequency delay due to a time-of-flight of the one or more pulses of light traveling in a medium and reflected by an object. 
     In some implementations, the detection measurement is a current value corresponding to the additional charge carriers generated by the multiplication region. 
     In some implementations, applying the second voltage and applying the third voltage includes applying a bias voltage difference between the respective second terminal and third terminal of less than 7 volts. Applying the first voltage and applying the second voltage includes applying a bias voltage difference between the respective first terminal and second terminal of less than 3 volts. 
     In some implementations, a flow of charge carriers and additional charge carriers is normal to the light incident on the surface of the detection region. A flow of charge carriers and additional charge carriers can be lateral to the light incident on the surface of the detection region. 
     Particular embodiments of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages. An advantage of this technology is that the required biasing voltages to achieve an avalanche breakdown of the device can be less than 7V, e.g., 6V. Biasing voltages below 7V can allow for improved power budget requirements for incorporating the device in a larger system, e.g., in consumer applications, as well as allowing off-the-shelf components to be used to supply the voltage to the device (e.g., commercially-available CMOS-compatible power supplies). Utilizing a heavily-doped (e.g., &gt;10 18  cm −3  dopant concentration) p+ layer as an interim doping region between the detection layer and the multiplication layer reduces a sensitivity to doping fluctuations over a region of the device which can arise due to fabrication control issues, thereby reducing punch-through voltage fluctuations, avalanche breakdown voltage fluctuations, etc., that can arise from inconsistent doping across the device, which can cause premature punch-through, avalanche breakdown and/or excessive dark current in the device. 
     The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1 A  is a block diagram of an example avalanche photo-transistor device. 
         FIG.  1 B- 1 C  are block diagrams of example geometries for doping regions. 
         FIG.  2    is a flow diagram of an example process for avalanche photo-transistor. 
         FIG.  3    is a schematic of an example band diagram for an avalanche photo-transistor device under operating conditions. 
         FIG.  4    is a schematic of an effective device circuitry for an avalanche photo-transistor under operating conditions. 
         FIGS.  5 A- 5 B  are block diagrams of another example avalanche photo-transistor device. 
         FIGS.  6 A- 6 B  are block diagrams of another example avalanche photo-transistor device. 
     
    
    
     DETAILED DESCRIPTION 
     This specification describes technologies related to an avalanche photo-transistor (APT) device for detecting and converting an optical signal to an electrical signal, and amplifying the electrical signal for processing. The APT device includes three terminals which can be used to separately bias a detection region, a multiplication region, and an interim doping region that is located between the detection region and multiplication region. 
     In one embodiment, a bias of a few volts, e.g., less than 3V, can be applied to the Ge detection region. An unintentional background doping level for the Ge detection region (e.g., crystalline germanium layer) may be &lt;10 16  cm −3 . As such, the Ge detection region relies on the voltage difference between a first doping region in the Ge detection region and the interim doping region to separate electron-hole pairs and sweep the charge carriers from the detection region to the multiplication region. 
     In one embodiment, the interim doping region between a Ge detection region and a Si multiplication region is heavily-doped with p-type dopants, e.g., 10 18 -10 20  cm −3  of p-type dopant in the interim doping region and is biased to lower and stabilize a breakdown voltage of the reversely-biased P-I-N (PIN) structure formed in the Si multiplication region, for example, to less than 7V. The biased heavily-doped interim doping region functions to lower a barrier height at the interface between the Ge detection region and Si multiplication region to allow for charge carriers generated in the Ge detection region to flow more easily to the Si multiplication region. The Si multiplication region relies on the voltage difference between a second doping region in the Si multiplication region and the interim doping region to sweep and amplify the photo-carriers. 
     The APT device can include a first doping region (e.g., a &gt;10 18  cm −3  heavily-doped p+ region) that is buried within the Ge detection region and in electrical and physical contact with a first terminal, and a second doping region (e.g., a &gt;10 18  cm −3  heavily-doped n+ region) that is buried within the Si multiplication region and in electrical and physical contact with a second terminal. Doping profiles for the respective first doping region and second doping region can be selected in part such that the first doping region forms an Ohmic contact with the first terminal and the second doping region forms an Ohmic contact with the second terminal. 
     Doping profiles, e.g., a concentration of dopant vs depth into the layer, for the interim doping region and second doping region can be selected in part to form a P-I-N (PIN) structure between the p+-doped interim doping region and n+-doped second doping region. An intrinsic region of the PIN structure between the p+ region and n+ region is formed from the silicon multiplication region located between the interim doping region and the second doping region, where the intrinsic region has a low doping level, e.g., is unintentionally doped at concentrations of &lt;10 16  cm −3  of dopants. 
     In some implementations, the APT device can be configured to be a vertically-integrated device, e.g., such that light is absorbed starting at a top surface of the device and the charge flow proceeds vertically downward through the device.  FIG.  1 A  is a block diagram of an example avalanche photo-transistor (APT) device  100 . As depicted in  FIG.  1 A , the APT device  100  is a vertically-integrated device, including a substrate  102 , a multiplication region  104  on top of the substrate  102 , and a detection region  106  on top of the multiplication region  104 . The APT device  100  additionally includes an interim doping region  108  located between the multiplication region  104  and detection region  106 . 
     The detection region  106  is configured to absorb light that is incident on a first surface  107  of the detection region  106  and generate one or more charge carriers within the detection region  106  from the incident light. The detection layer  106  can be crystalline germanium (Ge), germanium silicon (GeSi), or another material that is suitable for optical absorption and process integration. At least one surface of the detection region  106  is exposed to the incident light, e.g., a top surface of the detection region  106 . As depicted in  FIG.  1 A , the detection region  106  is a top layer of a vertically-integrated APT device  100 . 
     The detection region  106  has a thickness  120  that is normal to the first surface  107  and that is sufficient to allow for absorption of the incident light  101 , e.g., near-infrared light, such that the incident light  101  is absorbed within the detection region  106  and where at least one charge carrier pair is generated from the incident light  101  within the detection region  106 . Thickness  120  of the detection region  106  can range, for example, between 0.5-5 microns (μm). 
     The multiplication region  104  is configured to receive the one or more charge carriers from the interim doping region  108  and generate one or more additional charge carriers. The multiplication region  104  can be crystalline silicon, or another material that is suitable for multiplication and vertical integration. The multiplication region  104  is adjacent to the detection region  106  along an interface  105 . As depicted in  FIG.  1 A , the multiplication region  104  is a layer supported by the substrate  102  and supportive of the detection region  106 , where the interim doping region  108  is located at an interface between the multiplication region  104  and detection region  106 . 
     The multiplication region  104  has a thickness  122  that is normal to the first surface  107  and that is sufficient for the generation of one or more additional charge carriers from the one or more carriers that are generated in the detection region  106 . Thickness  122  of the multiplication region  104  can range, for example, between 100-500 nanometers (nm). The thickness  122  may determine the breakdown voltage of the multiplication region  104 . For example, a thickness  122  of 100 nm corresponds to ˜5-7 Volts required to achieve avalanche breakdown in the multiplication region  104 . In another example, a thickness  122  of 300 nm corresponds to ˜15-21 Volts required to achieve avalanche breakdown in the multiplication region  104 . 
     A first doping region  110  is located adjacent to a surface of the detection region  106 . The first doping region  110  can range a depth  111  from the surface of the detection region  106 . The first doping region  110  includes a p-type dopant, e.g., boron, aluminum, gallium, or indium. A doping profile for the first doping region  110  can be, for example, at least a threshold amount (e.g. 10 16  cm −3 ) of constant doping concentration along the depth  111  to maintain a constant voltage throughout the first doping region  110 . In one example, the first doping region  110  includes a dopant concentration of at least 10 18  cm −3  of boron for a depth  111  adjacent to a first surface  107  of the germanium detection region  106 . 
     A second doping region  112  is located adjacent to a surface of the substrate  102 . The second doping region  112  can range a depth  113  from the surface of the substrate  102 . The second doping region  112  includes an n-type dopant, e.g., phosphorus, arsenic, antimony, or the like. A doping profile for the second doping region  112  can be, for example, at least a threshold amount (e.g. 10 16  cm −3 ) of constant doping concentration along the depth  113  to maintain a constant voltage throughout the second doping region  112 . In one example, the second doping region  112  includes a dopant concentration of 10 18  cm −3  of phosphorous for a depth  113  adjacent to a surface of the substrate  102 . 
     The interim doping region  108  is located between the multiplication region  104  and the detection region  106 . As depicted in  FIG.  1 A , the interim doping region  108  is buried at a surface of the multiplication region  104  that is adjacent to a surface of the detection region  106 . The interim doping region  108  can range a depth  109  from the surface of the multiplication region  104 . A selected depth  109  of the interim doping region  108  may slightly adjust the breakdown voltage of multiplication region  104 . Additionally, a depth  109  of the interim doping region  108  can be selected to be sufficiently thin to prevent Auger recombination and slowdown of charge carriers, as will be discussed in further detail with reference to  FIG.  3    below. 
     The interim doping region  108  can be defined by a region of a threshold concentration of doping material, e.g., p-type dopant, within a crystalline silicon layer. The p-type dopant can be, for example, boron, aluminum, gallium, or indium. The interim doping region  108  has a doping concentration that is greater than a threshold doping concentration. A threshold doping concentration is a minimum number of dopants (e.g., p-type dopants) that are present within the interim doping region  108 , which maintains a constant voltage throughout the interim doping region  108 . In some embodiments, the threshold doping concentration within the interim doping region  108  can be 10 16  cm′. Furthermore, providing a bias voltage on the interim doping region  108  and a bias voltage on the second doping region  112 , which generates a voltage difference across the multiplication region  104 , may to lower and stabilize the breakdown voltage of a reversely-biased P-I-N (PIN) diode formed in the multiplication region  104 , for example, to set the voltage difference less than 7 V. In one example, the interim doping region  108 , can be defined as a volume within a crystalline silicon layer where there is a concentration of 10 18 -10 20  cm −3  of boron atoms in a silicon layer. 
     A doping profile for the interim doping region  108  can be, for example, at least a threshold amount of constant doping concentration along the depth  109 . In one example, the interim doping region  108  includes a dopant concentration of &gt;10 18  cm −3  of boron buried a depth  109  adjacent to an interface  105  between the multiplication region  104  and detection region  106 . 
     Each of the multiplication region  104 , detection region  106 , and interim doping region  108  are in electrical and physical contact with one or more terminals, respectively. Terminals can be metal or metal-alloy contacts that are in physical and electrical contact with a respective region. For example, the terminals can be composed of aluminum, copper, tungsten, tantalum, metal nitride, or silicide. A minimum contact area of the terminal can be selected to minimize its blockage of optical signal, but at the same time allow for physical and electrical contact with a probe sustaining an applied voltage from the probe with minimal degradation of the terminal. As depicted in  FIG.  1 A , the multiplication region  104 , detection region  106 , and interim doping region  108  are in electrical and physical contact with at least two terminals each, respectively. Although not shown in  FIG.  1   , the at least two terminals for each respective region are eventually in physical and electrical contact with each other. 
     A first terminal  114  is in electrical contact with the first doping region  110  and is configured to bias the detection region  106 . More particularly, the first terminal  114  is in electrical and physical contact with the first doping region  110 . The doping concentration of the first doping region  110  can be selected in part to result in a small contact resistance between the first terminal  114  and the first doping region  110  for efficient biasing, and at the same time decreases the RC time constant to increases the device operation speed. 
     A second terminal  116  is in electrical contact with the interim doping region  108  and is configured to bias the interim doping region  108 , so that a voltage difference and an electric field is generated between the first doping region and the interim doping region. The second terminal  116  is in electrical and physical contact with the interim doping region  108 . The doping concentration of the interim doping region  108  can be selected in part to result in a small contact resistance between the second terminal  116  and the interim doping region  108  for efficient biasing. 
     A third terminal  118  is in electrical contact with the second doping region  112  and is configured to bias the multiplication region  104 , so that a voltage difference and an electric field is generated between the interim doping and the second doping region. The third terminal  118  is in electrical and physical contact with the second doping region  112 . The doping concentration of the second doping region  112  can be selected in part to result in a small contact resistance between the third terminal  118  and the second doping region  112  for efficient biasing, and at the same time decreases the RC time constant to increases the device operation speed. 
     In some example embodiments, a total series resistance due to contact resistance and doping resistance of the respective terminals and doping layers is less than a few Ohms for APT devices operating at &gt;Gigahertz (GHz) operation, e.g., for optical communication applications. In other example embodiments, a total series resistance due to contact resistance and doping resistance of the respective terminals and doping layer is less than a few tens of Ohms for APT devices operating at Megahertz (MHz) to GHz operation, e.g., for time-of-flight applications. 
     Respective applied bias voltages to the first terminal  114 , second terminal  116 , and third terminal  118  are described below in further detail with respect to  FIGS.  2 ,  3 , and  6   . 
     The interim doping region  108 , the first doping region  110 , and the second doping region  112  can each have a respective in-plane geometry to form less than a complete layer in a plane that is parallel to the first surface  107 .  FIG.  1 B- 1 C  are block diagrams of example geometries of doping regions. 
       FIG.  1 B  is a block diagram  140  of an example in-plane geometry of a doping region, e.g., a first doping region  110 , a second doping region  112 , or an interim doping region  108 . As depicted in  FIG.  1 B , the in-plane geometry is a finger-like structure including multiple “fingers”  142  and a base  144 , where each finger  142  has a width  146  and a length  148 . A gap  150  between adjacent fingers  142  has a width  152 . 
       FIG.  1 C  is a block diagram  160  of another example in-plane geometry of a doping region  162 , e.g., a first doping region  110 , a second doping region  112 , or an interim doping region  108 . As depicted in  FIG.  1 C , the in-plane geometry is a mesh-like structure including gaps  164  in the doping region having a width  168  and length  166  Though depicted in  FIG.  1 C  as square gaps  164  in the doping region  162 , other geometries for the gap are conceivable, e.g., circular, rectangular, polygonal, or the like. 
     Though depicted in  FIGS.  1 B and  1 C  as in-plane geometries forming less than complete layers, one or more of the doping layers, e.g., a first doping region  110 , a second doping region  112 , or an interim doping region  108  of the APT device  100  can be a complete layer. 
     Referring now to  FIG.  1 A , under illumination conditions, the APT device  100  is illuminated by a light source  101 . Light source  101  can be a near-infrared (NIR) light source, emitting wavelengths of light ranging between, for example, 750 nm to 1.65 microns. For example, a NIR light source can emit light with a peak intensity at a wavelength of 850 nm, 1.31 microns, 1.55 microns or the like. In one example, a NIR light source  101  is direct or reflected light from a NIR laser, light emitting diodes (LEDs), or another NIR light source used in optical communications and/or optical sensing applications. The light source  101  is incident on at least a first surface  107  of the detection region  106  such that the detection region  106  absorbs light from the light source  101  and generates one or more carriers from the light of the light source  101  within the detection region  106 . In a vertically-integrated device, as depicted in  FIG.  1 A , a flow of charge carriers and additional charge carriers is normal to the light incident on the surface of the detection region. Operation of the APT device  100  under illumination conditions will be described in further detail with reference to  FIGS.  2 ,  3 , and  6    below. 
     Fabrication of an Avalanche Photo-Transistor 
     The various aspects of the APT device  100  as depicted in  FIG.  1 A  can be fabricated on the substrate  102 , for example, using complementary metal-oxide-semiconductor (CMOS) microfabrication techniques, e.g., photolithography processes, etching processes, deposition processes, and the like. In some embodiments, fabrication of the APT device  100  can include forming a second doping region  112  embedded in a silicon substrate  102  using, for example, ion implantation, diffusion, rapid thermal processing, or other similar processes. 
     A silicon multiplication layer  104  can be grown on the silicon substrate  102  using various vacuum techniques, e.g., chemical-vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), or the like. In some implementations, the second doping region  112  is buried within a silicon substrate  102 , e.g., using ion implantation, where an undoped layer of silicon above the buried second doping region forms a silicon multiplication layer  104 . 
     An interim doping region  108  can be embedded adjacent to an interface  105  of the silicon multiplication layer  104  during the growth process of the silicon multiplication region  104 , e.g., by using in-situ dopants during the growth process of the silicon material. In some implementations, the interim doping region  108  can be formed using implantation or diffusion techniques. 
     A germanium detection region  106  can be formed on top of the silicon multiplication region  104 , for example, using CVD, MOCVD, MBE, ALD, or the like. The first doping region  110  can be embedded adjacent to a first surface  107  of the germanium detection region  106  during the growth process of the germanium detection region  106 , e.g., by using in-situ dopants during the growth process of the germanium material. In some implementations, the first doping region  110  can be formed using implantation or diffusion techniques. 
     Terminals  114 ,  116 , and  118  can be fabricated on the APT device  100  in contact with respective first doping region  110 , interim doping region  108 , and second doping region  112 , using, for example a process including a deposition step, a lift-off step, or an etch step. 
     Example Operation of the Avalanche Photo-Transistor 
       FIG.  2    is a flow diagram of an example process  200  for avalanche photo-transistor under operating conditions. Operating conditions of the APT device, as described here, include applying one or more voltages on the respective terminals of the APT device, e.g., the first terminal  114 , the second terminal  116 , and the third terminal  118 . Operating conditions can additionally include exposing at least a surface of the APT device, e.g., a first surface  107 , to illumination of a light source. 
     A first voltage is applied to a first terminal in electrical contact with a detection region ( 202 ). With reference to  FIG.  1 A , a first voltage V U  is applied to a first terminal  114  in electrical contact with a detection region  106 . In one example, a first voltage V U  applied to the first terminal  114  is 0 Volts. 
     Referring back to  FIG.  2   , a second voltage is applied to a second terminal in electrical contact with an interim doping region ( 204 ). With reference to  FIG.  2   , a second voltage V M  is applied to a second terminal  116  in electrical contact with an interim doping region  108 . Second voltage V M  can be selected in part to sweep the charge carriers from the detection region  106  to the multiplication region  104 . Below a threshold second voltage, the interim doping layer  108  can act as a gate between the detection region  106  and the multiplication region  104 , such that a voltage above the threshold second voltage is needed at the second terminal to facilitate the movement of charge carriers from detection region  106  to the multiplication region  104 , in other words, to bias the gate. For example, when the first voltage V U  applied to the first terminal  114  is 0 Volts, a second voltage V M  applied to the second terminal  116  is less than or equal to 5 Volts, e.g., 3 Volts. 
     In some implementations, applying the first voltage V U  and applying the second voltage V M  includes applying a bias voltage difference and an electric field between the respective first terminal  114  and second terminal  116  of less than 5 volts. The bias voltage difference between the respective first terminal  114  and the second terminal  116  can be selected to be sufficient to sweep the generated one or more charge carriers from the detection region  106 , e.g., the Ge layer, to the interim doping region  108  at a desired transit time. In one example, the bias voltage difference between the first terminal  114  and the second terminal  116  is ˜1-2 Volts for a detection region  106  that is composed of germanium. 
     Referring back to  FIG.  2   , a third voltage is applied to a third terminal in electrical contact with a multiplication region ( 206 ). With reference to  FIG.  1 A , a third voltage V L  is applied to a third terminal  118  in electrical contact with a multiplication region  104 . For example, when the first voltage V U  applied to the first terminal  114  is 0 Volts and the second voltage V M  applied to the second terminal  116  is 3 Volts, a third voltage V L  applied to the third terminal  118  is less than or equal to 12 Volts, e.g., 10 Volts. 
     In some implementations, applying the second voltage V M  and applying the third voltage V L  includes applying a bias voltage difference and an electric field between the respective second terminal  116  and third terminal  118  of less than 9 volts. The bias voltage difference between the respective second terminal  116  and the third terminal  118  can be selected to be sufficient to sweep and amplify the generated one or more charge carriers from the interim doping region  108  to the multiplication region  104 , e.g., the Si layer, at a desired transit time and multiplication gain. In one example, the bias voltage difference between the second terminal  116  and the third terminal  118  is ˜5-6 Volts for a detection region  106  that is composed of silicon. 
     Referring now to  FIG.  3   , which is a schematic of an example band diagram  300  for an avalanche photo-transistor (APT) device (e.g., APT device  100 ) under operating conditions. Band diagram  300  depicts an APT device including a multiplication region  304 , a detection region  306 , and an interim doping region  308  between the multiplication region  304  and detection region  306 . In accordance with some embodiments, the detection region  306  includes a first doping region  310  where the first doping region is a heavily-doped p+ region with a charged concentration &gt;10 18  cm −3 . The multiplication region  304  includes a second doping region  312  where the second doping region is a heavily-doped n+ region with a charge concentration of &gt;10 18  cm −3 . The interim doping region  308  is a heavily-doped layer with a charge concentration &gt;10 18  cm −3 . 
     As described above with reference to  FIG.  2    in steps  202 - 206 , a set of voltages V U , V M , and V L , are applied to the APT device at respective terminals to result in a band diagram as depicted in  FIG.  3   . For example, a bias voltage difference is applied between a first terminal (e.g., first terminal  114 ) in electrical contact with the first doping region  310  and a second terminal (e.g., second terminal  116 ) in electrical contact with the interim doping region  308  that is less than 3 Volts, and a bias voltage difference is applied between the second terminal and a third terminal (e.g., third terminal  118 ) in electrical contact with the second doping region  312  that is less than 7 Volts. If the first doping region, the interim doping region, and the second doping region are p+, p+, and n+ doped, respectively, the PIN junction formed in the multiplication region  104  can be characterized as a reverse-biased PIN junction. 
     Referring back to  FIG.  2   , one or more charge carriers are generated within the detection region using incident light on a surface of the detection region ( 208 ). The photocurrent associated with the charge carriers generated within the detection region is in accordance with the electric field formed between the first doping region and interim doping region. With reference to  FIG.  3   , incident light from a light source  301  is exposed to a surface of the detection region  306 , e.g., NIR light from a NIR light source  301 . Light from the light source  301  is absorbed within the detection region  306 , e.g., within the layer of crystalline germanium, and one or more charge carriers, e.g., electron  318  and hole  319  pairs, are generated from the absorbed light. 
     Referring back to  FIG.  2   , one or more charge carriers are provided from the detection region to the multiplication region using the interim doping region ( 210 ). For a sufficient first voltage V U  and second voltage V M  applied to the first doping region and the interim doping region, respectively, the charge carriers are swept from the detection region to the multiplication region. As depicted in  FIG.  3   , the one or more charge carriers, e.g., electrons  318 , are swept from the detection region  306  to the multiplication region  304  over a barrier  320  with little or no electric field depicted in the band diagram  300 . Charge separation between electrons  318  and holes  319  can be facilitated by a barrier  322  to holes  319  generated by a band alignment of the germanium layer and silicon layer at the interface between the detection region  306  and interim doping region  308 . The bias voltage difference that is applied between the second terminal and a third terminal can result in a strong electric field achieving an avalanche process in the multiplication region  304 , which facilitates the flow of electrons  318  to the multiplication region  304  and amplifies the numbers of electrons within the multiplication region  304 . 
     One or more additional charge carriers are generated, as described in  FIG.  2   , using the one or more charge carriers within the multiplication region ( 212 ). Once the one or more electrons  318  of  FIG.  3    are swept into the multiplication region  304 , a process of charge multiplication can occur, generating additional electron  324  and hole  325  pairs in the multiplication region  304 . For a sufficient applied bias voltage difference between the second terminal (e.g., second terminal  116 ) and the third terminal (e.g., third terminal  118 ), e.g., at least 7 Volts, the multiplication region  304  operates under avalanche process conditions, producing an amplification of the one or more carriers by generating one or more additional carriers. The generated one or more additional holes  325  move towards the heavily p+ doped first doping region  310  and are collected at the first terminal, while the one or more additional electrons  324  flow towards the heavily n+ doped second doping region  312  and are collected at the third terminal. 
     Referring back to  FIG.  2   , a detection measurement is provided based in part on the one or more additional charge carriers ( 214 ). In some implementations, the detection measurement is a current value corresponding to the additional charge carriers generated by the multiplication region  304  that are collected by the n+ second doping region  312  by the third terminal. Further details of the collected current values are discussed below with reference to  FIG.  4   . 
     In some implementations, the incident light from light source  301  includes one or more pulses of light traveling in a medium (e.g., air, liquid, stone, brick, etc.) and reflected by an object. The object can be, for example, a person (e.g., hand, face, fingers, etc.), a vehicle (e.g., car, plane, etc.), a building, or another type of object. The pulses of light traveling in the medium can be from a NIR laser source, where the pulses are reflected off of the object and then incident on the APT device. The detection measurement includes identifying a direct time or an indirect phase or an indirect frequency delay due to a time-of-flight of the one or more pulses of light traveling in the medium and reflected by the object. In some implementations, the incident light from light source  301  includes one or more pulses of light traveling in a confined medium (e.g., optical fiber, optical waveguide) and transmitted through. The pulses of light traveling in the medium can be from a NIR laser source, where the pulses are incident on the APT device. The detection measurement includes identifying a “zero” state or a “one” state or a state from the total 2 n  states of digital optical communication using one or more pulses of light traveling in the medium. 
       FIG.  4    is an equivalent circuitry  400  for an avalanche photo-transistor (APT) device under operating conditions. As described above with reference to  FIG.  1 A , the APT device  402  depicted in  FIG.  4    includes a silicon multiplication region  404 , a germanium detection region  406 , and an interim doping region  408  located between the multiplication region  404  and detection region  406 . A first terminal  410  is in electrical contact with the germanium detection region  406 , at a first doping region buried in the germanium detection region  406 . A second terminal  412  is in electrical contact with the interim doping region  408 . A third terminal  414  is in electrical contact with the silicon multiplication region  404  at a second doping region that is adjacent to the multiplication region  404 . 
     Under operating conditions, a first voltage V U  is applied to the first terminal  410 , e.g., 0 Volts. A second voltage V M  is applied to the second terminal  412 , e.g., 3 Volts. A third voltage V L  is applied to the third terminal  414 , e.g., 10 Volts. The voltage bias difference applied between the first terminal  410  and second terminal  412  (i.e., 3V bias voltage difference given the aforementioned V U  and V M ) functions to bias the germanium detection region  406  and in return generate a dark current I d   Ge    416  flowing towards the first terminal  410  from the detection region  406 . 
     The voltage bias difference between the second terminal  412  and the third terminal  414  (i.e., 3V bias voltage difference given the aforementioned V M  and V L ) functions to bias the silicon multiplication region  404 , causing the silicon multiplication region  404  to operate under avalanche process conditions. A multiplication factor M*  418  due to the avalanche process by electron injection of charge carriers that are present in the biased multiplication region  404  operating under avalanche process conditions results in multiplication gain of the APT device  402 . The second voltage V M  applied to the second terminal  412  generates a leaking current I c   Ge    420  from the second terminal  412  flowing towards the first terminal  410 , and measurable at the first terminal  410 . 
     Under dark conditions, e.g., no illumination of the APT device  402 , the multiplication factor M*  418  augments the dark current I d   Ge    416 . A current measurement at the first terminal  410  under dark conditions I u (D) is equal to:
 
 I   u ( D )= M *( I   d   Ge )+ I   c   Ge   (1)
 
     Under illumination conditions, e.g., light is exposed to the APT device, the APT device  402  is exposed to incident light from a light source  422 , e.g., a NIR laser. Photocurrent I p   Ge    424  is generated from the conversion of light energy incident on the germanium detection region  406  to one or more charge carriers, e.g., electron-hole pairs, which are separated such that electrons  426  flow towards the silicon multiplication region  404  and third terminal  414  (and holes  427  flow towards the first terminal  410 ). The electrons  426  are amplified and generate one or more additional charge carriers in the multiplication region  404 . A current measurement at the first terminal  410  under illumination conditions I u (L) is equal to:
 
 I   u ( L )= M *( I   d   Ge   +I   p   Ge )+ I   c   Ge   (2)
 
     An amplified photocurrent measurement can be determined, for example, by subtracting out the dark-condition current measurement I u (D) from the illumination-condition current measurement I u (L), where the result is a current value corresponding to the additional charge carriers generated by the multiplication region  404 . 
     In some implementations, the detection measurement includes identifying a direct time or an indirect phase or an indirect frequency delay due to a time-of-flight of the one or more pulses of light traveling in the medium and reflected by the object. A direct time delay, indirect phase delay, or indirect frequency delay, etc., of a light pulse can be determined between a time of the pulse of the light source  422  and a measurement I u (D) of the photocurrent by the APT device  402 . For example, a time-to-digital converter is used to measure the direct time delay between firing an NIR laser pulse and detecting the reflected NIR laser pulse. For example, a local oscillator having the same waveform of an amplitude-modulated continuous-wave NIR laser or a frequency-modulated continuous-wave NIR laser is used to mix with the reflected NIR laser and obtain an indirect phase delay or indirect frequency delay. 
     Other Embodiments of the Avalanche Photo-Transistor 
     In some embodiments, an avalanche photo-transistor (APT) device can be configured to be a laterally-integrated device, e.g., such that light is absorbed at a top surface of the device and the charge flow proceeds laterally through a width of the device. In other words, a flow of charge carriers and additional charge carriers is lateral to the light incident on the surface of the detection region. A laterally-integrated device may have a heavily-doped p+ region laterally spaced apart from a Ge detection region, e.g., adjacent to or surrounding the Ge detection region.  FIGS.  5 A-B  and  6 A-B are two example embodiments of laterally-integrated device structures for the APT device.  FIGS.  5 A- 5 B  are block diagrams of another example avalanche photo-transistor device, where the interim doping region is laterally spaced apart from the detection region.  FIG.  5 A  is a cross-sectional view of a unilateral APT device  500 , where the flow of charge carriers and additional charge carriers is lateral with respect to a top surface of the APT device  500 . Unilateral APT device  500  includes a substrate  502 , e.g., a silicon substrate. The substrate  502  may additionally include a silicon layer grown epitaxially on top of the substrate  502 . A detection region  504 , e.g., germanium detection region, is embedded within the silicon layer grown epitaxially and/or the silicon substrate  502 . The embedded germanium detection region is fabricated in part by etching the silicon layer grown epitaxially and/or the silicon substrate  502  to form a recess, and then selectively grow a germanium in the recess. The germanium detection region  504  can include a thickness  508  ranging from 0.5 μm-5 μm and width  510  ranging 0.5 μm-50 um. 
     A first doping region  506  is embedded within the detection region  504  adjacent to a surface  507  of the detection region  504 , where the surface  507  is a top surface where light is incident on the APT device from a light source  501 . The first doping region  506  includes a doping profile that is constant doping concentration above a threshold (e.g. 10 16  cm −3 ) for a thickness  512  into the detection region  504 . Thickness  512  can be, for example, at least 10 18  cm −3 p+ doping concentration along the thickness  512 . In some example embodiments, a doping layer thickness  512  of the first doping region  506  can be between 20 nm and 500 nm. In other embodiments, the doping layer thickness  512  has other values. 
     A second doping region  514  is adjacent to the detection region  504  and partially or fully embedded within a multiplication region  516 , e.g., the silicon layer grown epitaxially, and adjacent to the surface  507 . The second doping region  514  includes a doping profile that is a constant doping concentration above a threshold (e.g. 10 16  cm −3 ) for a thickness  518  into the multiplication region  516 . Thickness  518  can be, for example, at least 10 18  cm −3 n+ doping concentration along the thickness  518 . In some example embodiments, a doping layer thickness  518  of the second doping region  514  can be between 20 nm and 1500 nm. In other embodiments, the doping layer thickness  518  has other values. 
     An interim doping region  520  is located between the first doping region  506  and second doping region  514  and embedded in the silicon material, e.g., the silicon substrate  502  that is between the first doping region  506  and second doping region  514 . The interim doping region  520  includes a doping profile having at least a threshold concentration (e.g. 10 16  cm −3 ) of carriers along a thickness  522  of the interim doping region. Thickness  522  can include, for example, at least 10 18  cm −3 p+ doping concentration along the thickness  522 . In some example embodiments, interim doping region thickness  522  of the interim doping layer  52  can be between 20 nm and 500 nm. In other embodiments, the doping layer thickness  522  has other values. 
     A distance  524  between the interim doping region  520  and the second doping region  514  defines the multiplication region  516  of the APT device  500 , similar to the multiplication region  104  of the vertically-integrated device in  FIG.  1 A . As depicted in  FIG.  5 A , one or more charge carriers generated in the detection region  504  flow along direction  528  laterally towards the multiplication region  516 , where one or more additional charge carriers are generated by an avalanche process. 
     Each of the first doping region  506 , interim doping region  520 , and second doping region  514  is in electrical and physical contact with a respective terminal. The first doping region  506  is in electrical contact with a first terminal  530 , which can be used to apply a first voltage V U  to the first terminal  530 . The interim doping region  520  is in electrical contact with a second terminal  532 , which can be used to apply a second voltage V M  to the second terminal  532 . The second doping region  514  is in electrical contact with a third terminal  534 , which can be used to apply a third voltage V L  to the third terminal  534 . 
       FIG.  5 B  is a top-down view of the unilateral APT device  500 . As depicted in  FIG.  5 B , the detection region  504  surrounds the first doping region  506 , and the interim doping region  520  is in-between the first doping region  506  and the second doping region  514 . 
     Benefits of the laterally-integrated device, e.g., shown in  FIG.  5 A , compared to the vertically integrated device, e.g., shown in  FIG.  1 A , is the flat surface topography. It facilitates the back-end metal process by reducing in-plane stresses and better-controlling chemical-mechanical polishing. 
     In another embodiment, the interim doping region of the APT device surrounds the detection region.  FIGS.  6 A- 6 B  are block diagrams of another example avalanche photo-transistor device, where the interim doping region  620  of the bilateral APT device surround the detection region. In contrast to the single direction of flow  528  of the unilateral APT device  500  described in  FIGS.  5 A-B , the bilateral APT device  600  described in  FIGS.  6 A-B  includes multiple directions of flow for the generated charge carriers.  FIG.  6 A  depicts a cross-sectional view of the bilateral APT device  600 . Bilateral APT device  600  includes a substrate  602 , e.g., a silicon substrate. The substrate  602  may additionally include a silicon layer grown epitaxially on top of the substrate  602 . A detection region  604 , e.g., germanium detection region, is embedded within the silicon layer grown epitaxially and/or the silicon substrate  602 . Similar to APT device  500 , the embedded germanium detection region is fabricated in part by etching the silicon layer grown epitaxially and/or the silicon substrate  602  to form a recess, and then selectively grow a germanium in the recess. The germanium detection region  604  can include a thickness  608  ranging from 0.5 μm-5 μm and a width  610  ranging from 0.5 μm-50 μm. 
     A first doping region  606  is embedded within the detection region  604  adjacent to a surface  607  of the detection region  604 , where a surface  607  is a top surface where light is incident on the APT device from a light source  601 . The first doping region  606  includes a doping profile that is constant doping concentration above a threshold (e.g. 10 16  cm −3 ) for a thickness  612  into the detection region  604 . Thickness  612  can include, for example, at least 10 18  cm −3 p+ doping concentration along the thickness  612 . 
     As depicted in  FIG.  6 B , a second doping region  614  surrounds the detection region  604  and partially or fully embedded within a multiplication region  616 , e.g., the silicon layer grown epitaxially, and adjacent to the surface  607 . The second doping region  614  includes a doping profile that is a constant doping concentration above a threshold (e.g. 10 16  cm −3 ) for a thickness  618  into the multiplication region  616 . Thickness  618  can be, for example, at least 10 18  cm −3 n+ doping concentration along the thickness  618 . 
     As depicted in  FIG.  6 B , the interim doping region  620  is located between the detection region  604  and the second doping region  614  and surrounds the detection region  604 . The interim doping region  620  is embedded within the silicon material, e.g., the silicon substrate  602 . The interim doping region  620  includes a doping profile having at least a threshold concentration of carriers along a thickness  622  of the interim doping region. Thickness  622  can be, for example, at least 10 18  cm −3  p+ doping concentration along the thickness  622 . 
     A distance  624  between the interim doping region  620  and the second doping region  614  defines the multiplication region  616  of the bilateral APT device  600 , similar to the multiplication region  104  of the vertically-integrated device in  FIG.  1 A . As depicted in  FIG.  6 A , one or more charge carriers generated in the detection region  504  flow laterally towards the multiplication region  616  that surrounds the detection region, where one or more additional charge carriers are generated by an avalanche process. 
     Each of the first doping region  606 , interim doping region  620 , and second doping region  614  is in electrical and physical contact with a respective terminal. The first doping region  606  is in electrical contact with a first terminal  630 , which can be used to apply a first voltage V U  to the first terminal  630 . The interim doping region  620  is in electrical contact with a second terminal  632 , which can be used to apply a second voltage V M  to the second terminal  632 . The second doping region  614  is in electrical contact with a third terminal  634 , which can be used to apply a third voltage V L  to the third terminal  634 . 
     In some embodiments, light incident on the first surface of the detection region of the APT device is coupled to the first surface of the APT device via free space. The incident light can be, for example, normal to the first surface of the detection region, as depicted by incident light  101  incident on surface  107  in  FIG.  1 A . In some embodiments, light incident on the detection region of the APT device can be coupled to the detection region of the APT device via evanescent coupling through a waveguide. The APT device can be integrated with a waveguide, e.g., a Si rib waveguide, where light propagates through the passive waveguide and then evanescently couples to the detection region of the APT device, e.g., the Ge absorption region. The evanescent coupling of light can be in-plane, e.g., in a direction parallel to a first surface of the detection region. 
     In accordance with aforementioned descriptions and corresponding figures, it is understood that the present application disclose the embodiments of APT device including detection region and multiplication region to generate the photocurrent, where the detection region is operated under a non-avalanche mode and configured to detect and generate the charge carriers, and the multiplication region is operated under an avalanche mode and configured to amplify the charge carriers. Operation under avalanche mode is when operating conditions include a multiplication gain that is greater than 1 (M&gt;1), and operation under “non-avalanche” mode includes a multiplication gain that is equal to 1 (M=1). 
     Specifically, the APT device applies three constant bias voltages on a first doping region, interim doping region, and second doping region respectively. The bias voltage on interim doping region can be properly designed to stabilize the operations of the detection region and multiplication region. In another aspect, the material of the detection region (e.g., germanium) and the material of the multiplication region (e.g., silicon) are different. The utilizations of the material difference may improve the detection and multiplication individually. 
     While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any features or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination. 
     Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. 
     Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.