Patent Publication Number: US-8987768-B2

Title: Semiconductor light emitting device having roughness layer

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation of copending application Ser. No. 12/883,554 filed on Sep. 16, 2010, which claims priority to copending Continuation application Ser. No. 12/340,354 filed on Dec. 19, 2008 (now U.S. Pat. No. 7,821,024 issued Oct. 26, 2014), which claims priority under 35 U.S.C. 119(a) to Korean Patent Application No. 10-2007-0133919 filed on Dec. 20, 2007. The contents of all these applications are hereby incorporated by reference in their entirety. 
    
    
     BACKGROUND 
     The present disclosure relates to a semiconductor light emitting device. 
     Group III-V nitride semiconductors have been variously applied to an optical device such as blue and green light emitting diodes (LED), a high speed switching device, such as a MOSFET (Metal Semiconductor Field Effect Transistor) and an HEMT (Hetero junction Field Effect Transistors), and a light source of a lighting device or a display device. 
     The nitride semiconductor is mainly used for the LED (Light Emitting Diode) or an LD (laser diode), and studies have been continuously conducted to improve the fabrication process or light efficiency of the nitride semiconductor. 
     SUMMARY 
     Embodiments provide a semiconductor light emitting device comprising a second conductive semiconductor layer with a dual roughness structure. 
     Embodiments provide a semiconductor light emitting device comprising a second conductive semiconductor layer with a horn-shaped dual roughness structure. 
     Embodiments provide a semiconductor light emitting device, which is capable of enhancing external quantum efficiency by forming a horn-shaped dual roughness structure in a second conductive semiconductor layer. 
     An embodiment provides a semiconductor light emitting device comprising: a first conductive semiconductor layer; an active layer on the first conductive semiconductor layer; and a second conductive semiconductor layer comprising a dual roughness structure on the active layer. 
     An embodiment provides a semiconductor light emitting device comprising: a first conductive semiconductor layer; an active layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer, wherein the second conductive semiconductor layer comprises: a first semiconductor layer comprising a shape of multiple horns; and a roughness layer ohmic-contacted on the first semiconductor layer. 
     An embodiment provides a semiconductor light emitting device comprising: a substrate; a first conductive semiconductor layer on the substrate; an active layer on the first conductive semiconductor layer; and a second conductive semiconductor layer comprising a dual roughness structure of a shape a multiple horns on the active layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a side sectional view of a semiconductor light emitting device according to a first embodiment, while  FIG. 1A  is a side sectional view of a semiconductor light emitting device according to an embodiment related to the first embodiment. 
         FIGS. 2 through 7  are sectional views illustrating a method for fabricating a semiconductor light emitting device according to a first embodiment. 
         FIG. 8  is a side sectional view of a semiconductor light emitting device according to a second embodiment. 
         FIG. 9  is a side sectional view of a semiconductor light emitting device according to a third embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Hereinafter, a semiconductor light emitting device according to the embodiment will be described with reference to the accompanying drawings. In the description of the embodiment, it will be understood that, when a layer (or film), a region, a pattern, or a structure is referred to as being “on(above/over/upper)” or “under(below/down/lower)” another substrate, another layer (or film), another region, another pad, or another pattern, it can be directly on the other substrate, layer (or film), region, pad or pattern, or intervening layers may also be present. Furthermore, it will be understood that, when a layer (or film), a region, a pattern, a pad, or a structure is referred to as being “between” two layers (or films), regions, pads, or patterns, it can be the only layer between the two layers (or films), regions, pads, or patterns or one or more intervening layers may also be present. Thus, it should be determined by technical idea of the invention. 
       FIG. 1  is a side sectional view of a semiconductor light emitting device according to a first embodiment. 
     Referring to  FIG. 1 , a semiconductor light emitting device  100  comprises a substrate  110 , a buffer layer  120 , a first conductive semiconductor layer  130 , an active layer  140 , a second conductive semiconductor layer  150  having dual roughness  152  and  156 , a first electrode  171 , and a second electrode  173 . 
     The substrate  110  may be formed of a material selected from the group consisting of sapphire (Al 2 O 3 ), GaN, SiC, ZnO, Si, GaP, and GaAs. Concave-convex patterns may be formed on the substrate  110 , but the present invention is not limited thereto. 
     The buffer layer  120  is formed on the substrate  110 . The buffer layer  120  is a layer for reducing a lattice constant difference from the substrate  110 . The buffer layer  120  may be formed to a predetermined thickness (for example, about 140 Å to about 1,000 Å) by selectively using GaN, AlN, AlGaN, InGaN, or AlInGaN. 
     An undoped semiconductor layer (not shown) may be formed on the buffer layer  120  or the substrate  110 . The undoped semiconductor layer (not shown) may comprise an undoped GaN-based layer. Neither of the buffer layer  120  and the undoped semiconductor layer (not shown) may be formed on the substrate  110 , or at least one of them may be formed on the substrate  110 . 
     At least one first conductive semiconductor layer  130  is formed on the buffer layer  120 . The first conductive semiconductor layer  130  is a semiconductor layer doped with a first conductive dopant. The first conductive semiconductor layer  130  may be formed of a semiconductor material having a composition formula of In x Al y Ga 1−x−y N (0≦x≦1, 0≦y≦1, 0≦x+y≦1), for example, InAlGaN, GaN, AlGaN, InGaN, AlN, or InN. When the first conductive semiconductor layer  130  is an N-type semiconductor layer, the first conductive dopant is an N-type dopant, such as Si, Ge, or Sn. 
     The active layer  140  is formed on the first conductive semiconductor layer  130 . The active layer  140  may have a single quantum well structure or a multiple quantum well structure. The active layer  140  may be formed of InGaN/GaN or AlGaN/GaN by using group III-V compound semiconductors. 
     The active layer  140  is formed of a material having a bandgap energy according to a light wavelength at which light is emitted. For example, in the case of a blue light emission having a wavelength range from 460 nm to 470 nm, the active layer  140  may be formed in a single or multiple quantum well structure at a period of an InGaN well layer/GaN barrier layer. The active layer  140  may comprise a material emitting a colored light such as a blue wavelength light, a red wavelength light, and a green wavelength light. A conductive clad layer  140 A and/or  140 B may be formed over and/or under the active layer  140  as shown in  FIG. 1A , and the conductive clad layer  140 A and/or  140 B comprises an AlGaN-based layer. 
     The second conductive semiconductor layer  150  is formed on the active layer  140 . The second conductive semiconductor layer  150  is a semiconductor layer doped with a second conductive dopant. The second conductive semiconductor layer  150  may be formed of a semiconductor material having a composition formula of In x Al y Ga 1−x−y N (0≦x≦1, 0≦y≦1, 0≦x+y≦1), for example, InAlGaN, GaN, AlGaN, InGaN, AlN, or InN. When the second conductive semiconductor layer  150  is a P-type semiconductor layer, the second conductive dopant is a P-type dopant, such as Mg, Zn, Ca, Sr, or Ba. 
     The first conductive semiconductor layer  130 , the active layer  140 , and the second conductive semiconductor layer  150  serve as a light emitting structure. The light emitting structure may be formed in one of an N-P junction structure, a P-N junction structure, an N-P-N junction structure, and a P-N-P junction structure. 
     The second conductive semiconductor layer  150  comprises a first semiconductor layer  151  and a roughness layer  155 . 
     The first semiconductor layer  151  is a P-type semiconductor layer doped with a second conductive dopant and may be formed of InAlGaN, GaN, AlGaN, InGaN, AlN, or InN. The first semiconductor layer  151  has a first roughness  152  on the top surface thereof, and the first roughness  152  may be formed in a shape of multiple horns. 
     The first roughness  152  may have a structure in which horn-shaped apex patterns and inverse-horn-shaped valley patterns are alternately arranged. 
     The first roughness  152  may have a height (H) of about 0.5 μm to about 1.2 μm and a diameter (D) of about 0.3 μm to about 1.0 μm. The height (H) of the first roughness  152  may be that of the horn-shaped apex pattern, and the diameter (D) of the first roughness  152  may be length between two the apexes or between two valleys. The first roughness  152  may have a horn shape, a polygonal horn shape, or a random horn shape, and may be formed at irregular intervals. 
     The roughness layer  155  is formed on the first semiconductor layer  151 . The roughness layer  155  is a P-type semiconductor layer doped with a second conductive dopant and may be formed of InAlGaN, GaN, AlGaN, InGaN, AlN, or InN. 
     The roughness layer  155  is ohmic-contacted with the first semiconductor layer  151  and may be formed to a predetermined thickness of about 1,000 Å to about 2,000 Å. 
     The roughness layer  155  is formed with a second roughness  156 . The second roughness  156  may be formed in the same shape as the first roughness  152 . The second roughness  156  may have a structure in which horn-shaped apex patterns and inverse-horn-shaped valley patterns are arranged regularly or irregularly. 
     The first semiconductor layer  151  and the roughness layer  155  may be formed of the same semiconductor materials or the different semiconductor materials. 
     The second electrode  173  is formed on the roughness layer  155  of the second conductive semiconductor layer  150 , and the second electrode  173  may have predetermined patterns. The first electrode  171  may be formed on or electrically connected to the first conductive semiconductor layer  130 . 
     By forming the first roughness and the second roughness having a shape of multiple horns in the second conductive semiconductor layer  150 , external quantum efficiency can be enhanced. That is, the horn-shaped first rough  152  and the horn-shaped second roughness  156  change the incident angle of light emitted from the active layer  140 , thereby enhancing light emission efficiency. 
       FIGS. 2 through 7  are sectional views illustrating a method for manufacturing a semiconductor light emitting device according to a first embodiment. 
     Referring to  FIG. 2 , a buffer layer  120 , a first conductive semiconductor layer  130 , an active layer  140 , and a first semiconductor layer  151 A of a second conductive semiconductor layer are formed on a substrate  110 . 
     The substrate  110  may be formed of a material selected from the group consisting of sapphire (Al 2 O 3 ), GaN, SiC, ZnO, Si, GaP, and GaAs. The buffer layer  120  is formed on the substrate  110  and may be formed of GaN, AlN, AlGaN, InGaN, or AlInGaN. An undoped semiconductor layer (not shown) may be formed on the buffer layer  120  or the substrate  110 . The undoped semiconductor layer (not shown) may comprise an undoped GaN-based layer. Neither of the buffer layer  120  and the undoped semiconductor layer (not shown) may be formed on the substrate  110 , or at least one of them may be formed. 
     At least one first conductive semiconductor layer  130  is formed on the buffer layer  120 . The first conductive semiconductor layer  130  may comprise an N-type semiconductor layer. The first conductive semiconductor layer  130  may be formed of a semiconductor material having a composition formula of In x Al y Ga 1−x−y N (0≦x≦1, 0≦y≦1, 0≦x+y≦1), for example, InAlGaN, GaN, AlGaN, InGaN, AlN, or InN. The first conductive semiconductor layer  130  comprises an N-type dopant, such as Si, Ge, or Sn. 
     The active layer  140  is formed on the first conductive semiconductor layer  130 . The active layer  140  may have a single quantum well structure or a multiple quantum well structure. The active layer  140  may be formed of InGaN/GaN or AlGaN/GaN by using group III-V compound semiconductors. The active layer  140  may comprise a material emitting a colored light such as a blue wavelength light, a red wavelength light, and a green wavelength light. 
     A conductive clad layer (not shown) may be formed over and/or under the active layer  140 . The conductive clad layer (not shown) comprises an AlGaN-based layer. 
     The first semiconductor layer  151 A of the second conductive semiconductor layer is formed on the active layer  140 . The first semiconductor layer  151 A may comprise a P-type semiconductor layer. The first semiconductor layer  151 A may be formed of a semiconductor material having a composition formula of In x Al y Ga 1−x−y N (0≦x≦1, 0≦y≦1, 0≦x+y≦1), such as InAlGaN, GaN, AlGaN, InGaN, AlN, or InN. The first semiconductor layer  151 A may comprise a P-type dopant such as Mg, Zn, Ca, Sr, or Ba. The first semiconductor layer  151 A may be formed to a predetermined thickness of about 0.7 μm to about 1.5 μm. 
     Referring to  FIGS. 3 and 4 , a removal layer  160  is formed on the first semiconductor layer  151 A. The removal layer  160  is formed in a thin film type by selectively using indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), silver (Ag), and aluminum (Al). 
     A first etching process is performed on the removal layer  160 . The first etching process uses a wet etchant (for example, HCl solution). The removal layer  160  is formed in a shape of multiple island patterns  162  by a wet etching process. 
     The island patterns  162  may have an embossing shape, a semispherical shape, or a convex lens shape, or may be formed regularly or irregularly with an irregular size and a random shape. The shape and size of the island patterns  162  may be different according to a material of the removal layer  160  or an etching degree. 
     Referring to  FIGS. 4 and 5 , a second etching process is performed on the island patterns  162 . The second etching process may be performed by a dry etching process. 
     The second etching process may be performed from the multiple island patterns  162  to a predetermined portion of the first semiconductor layer  151 A. 
     The dry etching process may be performed by selectively using an Inductively Coupled Plasma (ICP) apparatus, a Reactive Ion Etching (RIE) apparatus, a Capacitively Coupled Plasma (CCP) apparatus, and an Electron Cyclotron Resonance (ECR) apparatus. 
     An etching depth of the first semiconductor layer  151 A is changed according to a material difference (strength difference) and a thickness difference of the island patterns  162 . Accordingly, the first semiconductor layer  151  has a first roughness  152  having a shape of multiple horns on the top surface thereof. 
     The first roughness  152  of the first semiconductor layer  151  is formed in an apex/valley patterns. The valley patterns are formed by a relatively thin island pattern region, and the apex patterns are formed by a relatively thick island pattern region. 
     The first roughness  152  of the first semiconductor layer  151  may be formed in a horn shape, a polygonal horn shape, or a random horn shape, and may be formed at dense intervals. 
     The first roughness  152  may have a height (H) of about 0.5 μm to about 1.2 μm and a diameter (D) of about 0.3 μm to about 1.0 μm. 
     Referring to  FIG. 6 , a roughness layer  155  is formed on the first semiconductor layer  151 . The first semiconductor layer  151  and the roughness layer  155  define a second conductive semiconductor layer  150 . 
     The roughness layer  155  may be a P-type semiconductor layer. The roughness layer  155  may be formed of a semiconductor material having a composition formula of In x Al y Ga 1−x−y N (0≦x≦1, 0≦y≦1, 0≦x+y≦1), for example, InAlGaN, GaN, AlGaN, InGaN, AlN, or InN. The roughness layer  155  may comprise a P-type dopant such as Mg, Zn, Ca, Sr, or Ba. 
     The roughness layer  155  may be formed to a predetermined thickness of about 1,000 Å to about 2,000 Å and is ohmic-contacted with the first semiconductor layer  151 . A second roughness  156  having the same shape as the first roughness  152  is formed in the roughness layer  155 . 
     The second conductive semiconductor layer  150  may have a structure in which a dual structure of the first roughness  152  and the second roughness  156  is formed in a horn shape. 
     Referring to  FIG. 7 , a mesh etching process is performed to expose a portion of the first conductive semiconductor layer  130 . 
     A first electrode  171  is formed on the first conductive semiconductor layer  130 , and a second electrode  173  is formed on the second conductive semiconductor layer  150 . 
     In the semiconductor light emitting device  100  according to the current embodiment, the dual structure of the horn-shaped roughness  152  and  156  is formed in the second conductive semiconductor layer  150 . Thus, the incident angle of light emitted from the active layer  140  can be changed, thereby enhancing external quantum efficiency. 
       FIG. 8  is a side sectional view of a semiconductor light emitting device according to a second embodiment. In the first and second embodiments, like reference numerals refer to like elements and duplicate description will be omitted. 
     Referring to  FIG. 8 , the semiconductor light emitting device  100 A comprises a substrate  110 , a buffer layer  120 , a first conductive semiconductor layer  130 , an active layer  140 , a second conductive semiconductor layer  150  having dual roughness  152  and  156 , a transparent electrode layer  170 , a first electrode  171 , and a second electrode  173 . 
     The transparent electrode layer  170  is formed on the second conductive semiconductor layer  150  and may have a roughness structure. 
     The transparent electrode layer  170  may have a roughness with a shape of multiple horns along the roughness layer  155  of the second conductive semiconductor layer  150 . Accordingly, a triple structure of horn-shaped roughness may be formed on the active layer  140 . 
     The transparent electrode layer  170  may comprise at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), ZnO, RuOx, TiOx, IrOx, and SnO 2 . 
     The second electrode  173  may be formed on the roughness layer  155  of the second conductive semiconductor layer  150 , or may be formed on the transparent electrode layer  170  and/or the roughness layer  155 . 
       FIG. 9  is a side sectional view of a semiconductor light emitting device according to a third embodiment. In the first and third embodiments, like reference numerals refer to like elements and duplicate description will be omitted. 
     Referring to  FIG. 9 , the semiconductor light emitting device  100 B comprises a substrate  110 , a buffer layer  120 , a first conductive semiconductor layer  130 , an active layer  140 , a second conductive semiconductor layer  150  having dual roughness  152  and  156 , a third conductive semiconductor layer  170 , a first electrode  171 , and a second electrode  173 . 
     The third conductive semiconductor layer  175  may comprise an N-type semiconductor layer or a P-type semiconductor layer. For example, when the first conductive semiconductor layer  130  is an N-type semiconductor layer, the third conductive semiconductor layer  175  may be an N-type semiconductor layer. When the first conductive semiconductor layer  130  is a P-type semiconductor layer, the third conductive semiconductor layer  175  may be a P-type semiconductor layer. 
     The third conductive semiconductor layer  175  may have a roughness with a shape of multiple horns along the roughness layer  155  of the second conductive semiconductor layer  150 . Accordingly, a triple structure of horn-shaped roughness may be formed on the active layer  140 . 
     Furthermore, a transparent electrode layer (not shown) may be formed on the third conductive semiconductor layer  175 , and the transparent electrode layer (not shown) can diffuse a current to a whole region. 
     The second electrode  173  may be formed on the third conductive semiconductor layer  175 , but the present invention is not limited thereto. 
     The semiconductor light emitting device according to the current embodiment may be formed in a P-N structure, an N-P structure, an N-P-N structure, and a P-N-P structure. Accordingly, the second conductive semiconductor layer  150  may be implemented with an N-type semiconductor layer or a P-type semiconductor layer. 
     Any reference in this specification to “one embodiment,” “an embodiment,” “example embodiment,” etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is comprised in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments. 
     Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.