Patent Publication Number: US-10776076-B2

Title: Neural network engine

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 15/955,426 filed Apr. 17, 2018, which application relates to International PCT Application No. PCT/EP2016/081776 (Ref: FN-481-PCT), the disclosures of which are incorporated herein by reference in their entireties. 
    
    
     FIELD 
     The present invention relates to a neural network engine. 
     BACKGROUND 
     A processing flow for typical Convolutional Neural Network (CNN) is presented in  FIG. 1 . Typically, the input to the CNN is at least one 2D image/map  10  corresponding to a region of interest (ROI) from an image. The image/map(s) can comprise image intensity values only, for example, the Y plane from a YCC image; or the image/map(s) can comprise any combination of colour planes from an image; or alternatively or in addition, the image/map(s) can contain values derived from the image such as a Histogram of Gradients (HOG) map as described in PCT Application No. PCT/EP2015/073058 (Ref: FN-398), the disclosure of which is incorporated by reference, or an Integral Image map. 
     CNN processing comprises two stages:
         Feature Extraction ( 12 )—the convolutional part; and   Feature classification ( 14 ).       

     CNN feature extraction  12  typically comprises a number of processing layers 1 . . . N, where:
         Each layer comprises a convolution followed by optional subsampling (pooling);   Each layer produces one or (typically) more maps (sometimes referred to as channels);   The size of the maps after each convolution layer is typically reduced by subsampling (examples of which are average pooling or max-pooling);   A first convolution layer typically performs 2D convolution of an original 2D image/map to produce its output maps, while subsequent convolution layers perform 3D convolution using the output maps produced by the previous layer as inputs. Nonetheless, if the input comprises say a number of maps previously derived from an image; or multiple color planes, for example, RGB or YCC for an image; or multiple versions of an image, then the first convolution layer can operate in exactly the same way as successive layers, performing a 3D convolution on the input images/maps.       

       FIG. 2  shows an example 3D convolution with a 3×3×3 kernel performed by a subsequent feature extraction convolution layer of  FIG. 1 . The 3×3×3 means that three input maps A, B, C are used and so, a 3×3 block of pixels from each input map is needed in order to calculate one pixel within an output map. 
     A convolution kernel also has 3×3×3=27 values or weights pre-calculated during a training phase of the CNN. The cube  16  of input map pixel values is combined with the convolution kernel values  18  using a dot product function  20 . After the dot product is calculated, an activation function  22  is applied to provide the output pixel value. The activation function  22  can comprise a simple division, as normally done for convolution, or a more complex function such as sigmoid function or a rectified linear unit (ReLU) activation function of the form: y j =h(x j )=max (0,x j ) as typically used in neural networks. 
     In this case, for 2D convolution, where a single input image/map is being used, the input image/map would be scanned with a 3×3 kernel to produce the pixels of a corresponding output map. 
     Within a CNN Engine such as disclosed in PCT Application No. PCT/EP2016/081776 (Ref: FN-481-PCT) a processor needs to efficiently implement the logic required to perform the processing of different layers such as convolution layers and pooling layers. 
     SUMMARY 
     According to the present invention there is provided a neural network engine according to claim  1 . 
     Embodiments of the present invention incorporate a module for outputting floating point results for pooling or convolution layer operations in a neural network processor. 
     By sharing the resources needed for both layer types, the processing pipeline within the neural network engine can be kept simple with the number of logic gates as low as possible. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: 
         FIG. 1  shows a typical Convolutional Neural Network (CNN); 
         FIG. 2  shows an exemplary 3D Convolution with a 3×3×3 kernel; 
         FIG. 3  shows a typical floating point adder; 
         FIG. 4  shows a tree for implementing 3×3 convolution kernel; 
         FIGS. 5( a ) and ( b )  show trees for 3×3 average and maximum pooling respectively; 
         FIG. 6  shows processing logic configured for implementing a convolutional network layer according to an embodiment of the present invention; 
         FIG. 7  shows the processing logic of  FIG. 6  configured for implementing an average pooling layer; 
         FIG. 8  shows the processing logic of  FIG. 6  configured for implementing a max pooling layer; 
         FIG. 9  illustrates a conventional ReLU activation function; 
         FIG. 10  illustrates a PReLU activation function implemented by an embodiment of the present invention; 
         FIG. 11  shows the output module of  FIGS. 6-8  with an interface for implementing the PReLU activation function of  FIG. 10  in more detail; 
         FIG. 12  illustrates a conventional PEAK operation; and 
         FIG. 13  shows a variant of the processing logic of  FIGS. 6-8  for additionally implementing either a PEAK operation or two parallel 2×2 Max pooling operations. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     A floating point (FP) representation is usually employed for both the convolution kernel weights and image/map values processed by a CNN engine. A typical format suited for a hardware CNN engine implementation is 16 bit, half precision floating point (IEEE 754-2008). However, 8-bit FP representations can also be used and PCT Application No. PCT/EP2016/081776 (Ref: FN-481-PCT) discloses how a default FP exponent bias can changed to a custom value to avoid needing to use higher precision FP formats. 
       FIG. 3  shows an exemplary conventional 16 bit FP (IEEE 754-2008) floating point adder—clearly this structure is similar for any precision. As is known, such an adder must know which of two operands comprising s1/exp1/m1 and s2/exp2/m2 respectively is larger in order to align the mantissa of the operands. Thus, the adder shown includes a comparator  40  producing a binary output (O/P) indicating which of the floating point operands is larger. 
     The sign bits s1,s2 of these operands are in turn used through multiplexer  42  to select between a version of m1 shifted according to the difference between exp2 and exp1 subtracted from m2; or the shifted version of m1 added to m2; and through multiplexer  44  to select between a version of m2 shifted according to the difference between exp2 and exp1 subtracted from m1; or the shifted version of m2 added to m1. Now using multiplexers  46 ,  48  and  50  depending on the output O/P of the comparator  40 , the output of either multiplexer  42  or  44  is chosen to generate the mantissa for the output of the adder, the value of the mantissa is also used to adjust whichever of exp1 or exp2 are selected by multiplexer  48  to generate the exponent for the output of the adder, while the sign for the output of the adder is chosen as either s1 or s2. 
     Note that this adder is shown for exemplary purposes only and the present invention is equally applicable to any equivalent floating point adder. 
     Referring now to  FIG. 4 , it will be seen that convolution layers need: logic implementing floating point multipliers ( 30 ) and adder logic ( 32 ) to implement the dot product function ( 20 ) shown in  FIG. 2  as well as logic for the activation function ( 22 ). Note that any 3D convolution layers can be broken into a longer chain of multipliers whose products are then added in a deeper tree than shown. Thus, the 3×3×3 convolution shown in  FIG. 2  might require 27 multipliers. The logic shown in  FIG. 4  can therefore be expanded to deal with the largest form of convolution to be performed by a given CNN engine and where smaller or simpler 2D convolutions are to be performed, then for example, selected non-active weights within the kernel can be zeroed. 
     Separately,  FIG. 5( a )  shows that average pooling layers need: adders ( 34 ) as well as logic ( 36 ) for implementing a multiplication by 1/kernel size; while  FIG. 5( b )  shows that maximum pooling layers need comparators ( 38 ). 
     Looking at the trees of  FIGS. 4 and 5 , it will be seen that the adder ( 32 ,  34 ) and comparator ( 38 ) trees have similar structures with each node in a tree either producing a sum of its inputs or a maximum of its inputs respectively. 
     It will also been seen that any floating point adder such as the adder of  FIG. 3  already comprises comparator circuitry  40  for determining which of its operands is larger. Thus, with little additional configuration circuitry, any such adder can be converted to either select the sum of its input operands (as normal) or the larger of the operands fed to the comparator based on a single control input. The logic paths producing these results are separate and so this functionality can be implemented without effecting the timing of the adder. 
     Referring now to  FIG. 6 , there is shown circuitry  70  for enabling a CNN engine to process either a convolutional, max pooling or average pooling layer of a neural network according to an embodiment of the present invention. The circuitry  70  comprises a first layer of conventional floating point multipliers  30  such as are shown in  FIG. 4 . Now instead of a tree of floating point adder nodes  32  as shown in  FIG. 4 , there is provided a tree  32 ′ of configurable nodes which can be set to either produce a sum of their inputs or a maximum of their inputs according to the value of an Op_sel control input. 
     In the embodiment, the output of the final node in the tree  32 ′ and an output of one of the multipliers  32  are fed to an output module  60  as In0 and In1 respectively. 
     The circuitry  70  is configured to operate in a number of different modes: 
     In  FIG. 6 , the tree  32 ′ is configured for 3×3 2D convolution by having the nodes perform addition i.e. Op_sel is set to indicate addition and fed to each node. Now trained weight values  18  for a kernel are combined with input image/map values  16  typically surrounding a given pixel corresponding to in11 in the multipliers  30  as required, before being fed through the tree  32 ′ to the output module  60 . An activation function enable signal is fed to the output module  60  and this will cause the output module  60  to apply a required activation function to the result of an operation on In0 and In1 determined according to the value of Op_sel, in this case addition, as will be explained in more detail below, before providing the convolution output for the given pixel of the input image/map. 
       FIG. 7  shows that the same tree  32 ′ can configured for average pooling by setting the weight values  18  in the kernel to 1/9, where 9 is the number of (active) cells in the kernel, and having the nodes in the tree  32 ′ configured to perform addition. In this case, the output module  60  simply needs to add In0 and In1 to provide its output according to the value of Op_sel. Thus, no activation function (or a simple identity function) need only be applied to the operational result of In0, In1. 
     Finally,  FIG. 8  shows that the same tree  32 ′ can be configured for max pooling by setting the (active) weight values  18  in the kernel to 1 and having the nodes in the tree  32 ′ configured as comparators only to produce a maximum of their operands. In this case, the output module  60  simply needs to select the larger of In0 and In1 as its output according to the value of Op_sel. Again, no activation function (or a simple identity function) need only be applied to the operational result of In0, In1. 
     Again, the trees presented here are just an example for 3×3 kernels. Other kernel sizes can be easily implemented. 
     As indicated, convolution needs an activation function  22  to be applied to the dot product  20  of the input image/map values  16  and weight kernel values  18 . Currently, the most used activation function are Identity function i.e. no activation function is applied, ReLU and PReLU. 
     As shown in  FIG. 9 , ReLU (Rectified Linear Unit), a very simple function, is defined as follows:
 
ReLU( x )= x  for  x&gt; 0
 
ReLU( x )=0 for  x&lt;= 0
 
     PReLU (Parametric ReLU), a more general form of ReLU function, is defined as follows:
 
 p ReLU( x )= x  for  x&gt; 0
 
 p ReLU( x )= x /slope_coef for  x&lt;= 0
 
     Some embodiments of the present invention do not employ a precise slope and instead only use a slope with values that are a power of two. Although such slopes can be used as an approximation of a specified slope, this approach works best, if the network is trained with the approximated PReLU function, rather than approximating the PReLU function after training. 
     In any case, such an approximation needs two inputs:
         Coef—The logarithm of the slope coefficient   PSlope—Flag that indicates if the slope is negative or positive.       

     Thus, referring to  FIG. 10 , the PReLU function becomes:
 
 p ReLU( x )= x  for  x&gt; 0
 
 p ReLU( x )= x /(2{circumflex over ( )}Coef) for  x&lt;= 0 and  P Slope=0
 
 p ReLU( x )=− x /(2{circumflex over ( )}Coef) for  x&lt;= 0 and  P Slope=1
 
     Looking at the approximated PReLU activation function, it will be seen that it only needs to modify the exponent of the input. 
     Referring now to  FIG. 11  and based on the observations and approximations discussed above, the output module  60  can implement the addition, maximum, ReLU and PReLU functions as required. The Op_sel input is used to select between the addition or maximum of the two operands In0 and In1. 
     The activation input can have two bits and can select between three types of activation as shown in Table 1. It will therefore be appreciated that one or more activation functions can be added, especially by increasing the number of control bits. 
     
       
         
           
               
               
               
               
               
             
               
                   
                 TABLE 1 
               
               
                   
                   
               
             
            
               
                   
                 Activation 
                 0 
                 0 
                 No Activation 
               
               
                   
                   
                 0 
                 1 
                 ReLU 
               
               
                   
                   
                 1 
                 0 
                 PReLU 
               
               
                   
                   
                 1 
                 1 
                 Not Supported 
               
               
                   
                   
               
            
           
         
       
     
     For PReLU, the coefficients can be coded with 4 bits, representing the logarithm of the coefficient: 
     
       
         
           
               
               
               
             
               
                   
                   
               
               
                   
                 4 bit PReLU Coef 
                 PReLU slope coefficient 
               
               
                   
                   
               
             
            
               
                   
                 0000 
                 1 
               
               
                   
                 0001 
                 2 
               
               
                   
                 0010 
                 4 
               
               
                   
                 . . . 
                 . . . 
               
               
                   
                 1111 
                 2{circumflex over ( )}15 
               
               
                   
                   
               
            
           
         
       
     
     The output module  60  can take advantage of the floating point number pipeline with division by the power of two coefficient being done by subtracting the 4 bit PReLU coefficient instruction field value from the FP16 exponent value of the sum of In0 and In1 (or possibly the larger of the two, as will be explained below). 
     Using this scheme, an identity activation function can be implemented as a form of PReLU with PSlope=0 and Coef=0000, thus enabling the activation input to be defined with a single binary activation input with settings ReLU=0 or PReLU=1, so that the PReLU function shown in  FIG. 10  could be modified as follows:
 
 p ReLU( x )= x  for  x&gt; 0
 
 p ReLU( x )=( x /(2{circumflex over ( )}Coef) for  x&lt;= 0 and  P Slope=0)*Activation Input
 
 p ReLU( x )=(− x /(2{circumflex over ( )}Coef) for  x&lt;= 0 and  P Slope=1)*Activation Input,
 
so enabling the function to be implemented in a single pipeline.
 
     The special cases for subnormal/infinite can treated by the logic implementing the PReLU activation function in the following way:
         If the input is a negative, NaN or infinite, the input value is passed to the output unchanged;   If the result is a subnormal, the result is clamped to 0.       

     It will be appreciated that normally, an activation function other than the identity function would only be used when processing convolution layers. However, using an output module  60  with configuration controls such as shown in  FIG. 11 , it would also be possible to apply a non-linear activation function to a pooling result. Although not common, this option could be useful in some situations. 
     Referring now to  FIG. 12 , a further form of layer which can be incorporated within a network can involve detecting peaks within an image/map. A PEAK operation scans a source image/map with an M×N window, 4×4 in  FIG. 12 , in raster order with a given step size, for example, 1, and produces a map containing a list of the peaks found—a peak being an image/map element that is strictly greater in value than any of the surrounding elements in a window. 
     Referring to  FIG. 13 , implementing a PEAK operation again requires the nodes of the tree  32 ′ to be configured as comparators, as in the case of max pooling. The only condition is to have the middle element of the M×N window, corresponding to the pixel location of the image/map being processed, connected to the multiplier whose output is fed directly to In1 of the output module  60 ′ i.e. in the example shown in  FIG. 13 , in11 and in22 are swapped. The output module  60 ′ now produces two outputs, one indicating the peak value (as for max pooling) and a second output indicating if In1 is greater than In0 i.e. that In1 is a valid peak. 
     One way to provide this second output is for the second output to comprise a binary value indicating the maximum operand e.g. 0 for In0 or 1 for In0. Such an output could also find application for functions other than PEAK. 
     In a still further variant, it is also possible for the tree  32 ′ to simultaneously provide a result of two pooling operations. In the example of  FIG. 13 , the tree  32 ′ produces two 2×2 max pooling operations in parallel. In this case, the outputs are drawn from the two adders  32 ( 1 ),  32 ( 2 ) in the penultimate stage of the tree. These outputs could also be fed through an activation function, if required, but in any case, this can enable the step size for a pooling operation to be increased, so reducing processing time for an image/map. Again, this may require a re-organisation of the input image/map values so that the desired 2×2 sub-windows from the image values  16  are fed via the multipliers  30  to the appropriate nodes of the tree  32 ′. 
     It will also be seen that the 2×2 pooling approach shown in  FIG. 13  can be adapted to provide average pooling by setting the weight values  18  to ¼ and configuring the nodes of the tree  32 ′ for summation. 
     It will be appreciated that where only particular sized windows for 2D or 3D convolution or pooling were to be processed, the connections from input image/map and kernel values  16 ,  18  to the multipliers  30  could hardwired. However, where window sizes can vary, then especially for peak layer processing and sub-window pooling, multiplexer circuitry (not shown) would need to be interposed between the inputs  16 ,  18  for the engine and the multipliers  30 . 
     The above described embodiments can be implemented with a number of variants of a basic floating point adder:
         Normal FP adder used within the output module  60 ,  60 ′;   FP adder with activation function used within the output module  60 ,  60 ′;   Combined adder and max used within the tree  32 ′; and   Combined adder and max with activation function used within the output module  60 ,  60 ′.       

     Using these variants of adder, a common engine such as the CNN engine disclosed in PCT Application No. PCT/EP2016/081776 (Ref: FN-481-PCT) can be reconfigured for convolution, pooling or peak operations with minimal extra logic by comparison to implementing any given layer independently.