Patent Publication Number: US-9412728-B2

Title: Post-CMOS processing and 3D integration based on dry-film lithography

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a national stage application under 35 U.S.C. 371 and claims the benefit of PCT Application No. PCT/IB2013/055946 having an international filing date of Jul. 19, 2013, which designated the United States, which PCT application claimed the benefit of European Patent Application No. 12179308.7 filed Aug. 3, 2012, the disclosures of both the above-identified applications are incorporated herein by reference. 
     TECHNICAL FIELD 
     The present invention is in the field of chip fabrication. 
     BACKGROUND 
     The continuing demand for faster and smaller ICs has led to aggressive downscaling in transistor sizes, as predicted by Moore&#39;s Law [1]. Today&#39;s state of the art IC technology offers fascinating levels of performance and functionality, while introducing new barriers and challenges for further downscaling. As conventional planar IC de-signs have almost reached the limits, an emerging technology called three-dimensional integrated circuit (3D-IC) promises new possibilities to achieve higher volumetric transistor density. This technology enables the integration of multiple layers with vertical interconnections, providing potential performance improvements even in the absence of device scaling. Extensive studies by numerous research groups have already verified the potential of this technology for better electrical performance, lower power consumption, lower noise, smaller form factor, and more functionality [2]. 
     In the earlier system implementation approaches, chips with different functionalities were manufactured independently and assembled by wire bonds and global interconnects. This resulted in systems with significant signal transmission delays leading to limited operation frequency, which eventually could not meet the demands of the electronics market. Later, system-on-chip (SoC) integration approach was introduced, wherein different functional blocks, such as analog, digital, memory etc. . . . are merged in a single substrate. Although this scheme is very promising at first glance, it leads to a larger die area, which eventually reduces the manufacturing yield. Moreover, a particular choice of technology that is good for one circuit type is not always good for the others. Therefore, optimizing the system in favor of all elements has become an additional design and fabrication challenge. Moreover, gradually lengthening on-chip interconnects due to higher system complexity and larger die area have led to increase in the communication latency, and therefore, limited the operation speed once again after the era of hybrid technologies. Power consumption has also increased by the higher number of signal repeaters along the lines. In order to address the limitations of SoC, vertical packaging technologies have been developed, such as system-in-a-package (SiP) employing die stacking with wire bonds, and package-on-package (PoP). Nevertheless, the absolute benefits of “going vertical” has only been achieved by thinned chip stacking and use of TSVs, which allow significantly higher interconnection densities compared to the off-chip connections. This technology has enabled the integration of identical layers (homogeneous integration) or disparate layers with different functionality, size, and technology (heterogeneous integration), as illustrated in  FIG. 1 . 
     In view of the prior art, the present invention aims to develop a generic platform for the stacking of chips fabricated through multi-project-wafer (MPW) runs. Therefore, all the layers in the stack are already diced chips and the subsequent process steps are CMOS-compatible. We consider heterogeneous integration for sensing applications [3] and 3D multiprocessor systems [4] as the target applications for the proposed technology; however, the techniques can be applied to many other applications, which require post-CMOS processing in general, such as CMOS-MEMS cofabrication [5]. The inventors previously presented chip-level post-CMOS processing techniques based on stencil lithography [6] and 3D integration techniques based on template alignment [7]. In the context of the present invention, on the other hand, we employ dry-film resist as an alternative to traditional photolithography methods. After the post-processing steps, chip-to-chip alignment is achieved by surface-tension-driven self-alignment. Furthermore, a new parylene deposition technique is proposed for via sidewall passivation without the need of bottom dielectric etching. 
     SUMMARY OF THE INVENTION 
     The invention presented herein concerns a chip-level post-CMOS processing technique for 3D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple alternative to spin-coated resist. Unlike conventional photolithography methods, the inventive technique allows resist patterning on very high topography, thereby chip-level photolithography can be done without using any wafer reconstitution approach. 
     Moreover, the invention proposes a via sidewall passivation method which eliminates dielectric etching at the bottom of the via. 
     Accordingly, in line with a first aspect, the invention provides a method for performing a post processing pattern on a diced chip having a footprint, comprising the steps of: providing a support wafer; applying a first dry film photoresist to the support wafer; positioning a mask corresponding to the footprint of the diced chip on the first dry film photoresist; expose the mask and the first dry film photoresist to UV radiation; remove the mask; photoresist develop the exposed first dry film photoresist to obtain a cavity corresponding to the diced chip; positioning the diced chip inside the cavity; applying a second dry film photoresist to the first film photoresist and the diced chip; and expose and develop the second dry film photoresist applied to the diced chip in accordance with the post processing pattern. 
     In a second aspect the invention provides a method for obtaining a stack of two semiconductor layers in a back to face configuration, whereby at least one of the semiconductor layer comprises a through silicon via (TSV), comprising the steps of: provide a first semiconductor layer; provide a second semiconductor layer; making a hole through the second semiconductor layer from a face side to a back side; apply the face side of second semiconductor layer on a release tape; depositing parylene on the assembly of the second semiconductor layer and the release tape, thereby obtaining a sidewall passivation in the hole and a bonding layer on the back side of the second semiconductor; releasing the release tape, thereby obtaining a membrane of parylene covering an opening of the hole on the front side; position the back side of the second semiconductor layer relative to a face side of the first semiconductor layer; bonding the second semiconductor layer to the first semiconductor by applying pressure and heat; removing the membrane of parylene by directional etching; and electrically connecting the face side of the second semiconductor to the face side of the first semiconductor by depositing a conductor inside the hole, thereby obtaining the TSV. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       The invention will be better understood through the description of example embodiments and in reference to the figures, whereby 
         FIG. 1  contains illustrations of conventional 2D, homogeneous 3D, and heterogeneous 3D integration concepts; 
         FIG. 1A  summarizes the major 3D integration techniques, highlighting the ones used in this study; 
         FIG. 2  illustrates the complete process flow used for post-CMOS processing and C2C stacking; 
         FIG. 3  contains camera photos of the diced and thinned wafer, where each chip measures 3.5 mm by 3.5 mm and the final thickness is 50 μm (The UV-tape is transferred to the backside after grinding for frontside inspection); 
         FIG. 4  contains a camera photo of the carrier wafer with the diced chips and patterned dry-film (left), and the microscope image showing the via openings on the dry-film and the Al pads on the chip (right); 
         FIG. 5  shows a SEM photo of the chip after releasing the UV tape, leaving a 2 μm-thick parylene membrane on the frontside of the chip; 
         FIG. 6  shows (a) Microscope image of the cross-section of two 50 μm-thick chips bonded with parylene intermediate layer. (b) SEM photo of the top chip frontside after bonding; 
         FIG. 7  shows (a) SEM photos showing the parylene residuals after the etching step. (b) SEM photo of the vias after parylene etching and washing steps; 
         FIG. 8  shows a SEM photo showing the dry-film mask and the electroplated Cu inside the via openings; 
         FIG. 9  shows a SEM photo of the vias after maskless seed layer etching; 
         FIG. 10  shows a Cross section view of the TSVs after polishing, showing the 60 μm-diameter TSV opening and 100 μm-diameter electroplated Cu with 15 μm thickness on the surface; 
         FIG. 11  shows (a) Resistance measurement results of 5 chip stacks fabricated through the same processing steps. (Inset: Layout of the top chip, showing 16 rows and 256 pads. Chain starts from top left corner and ends at bottom left corner). (b) Average TSV resistance extracted from first two and last two rows before and after heat treatment; 
         FIG. 12  shows pad-to-edge distance along all directions for the chips manufactured in UMC 90 nm process. Mean and standard deviation values are calculated as 37 μm and 1.1 μm, respectively. (Each chip in the box is labeled with a letter and a number (C 1 , C 2 , C 3  . . . ), where letters represent the rows and numbers represent the columns); 
         FIG. 13  shows (a) SEM image of the CMOS pad after via etching and parylene passivation by frontside UV-tape protection. (b) SEM image of the via opening after bonding and parylene etching, showing the sidewall parylene passivation and the RDL layer on the bottom chip; and 
         FIG. 14  shows SEM images of the bonded chips after anisotropic parylene etching. (An already broken chip is used as the top chip to inspect the alignment accuracy). 
     
    
    
     DESCRIPTION OF EXAMPLE EMBODIMENTS OF THE INVENTION 
     Overview of 3D Integration Fabrication 
     The 3D integration fabrication involves three major processing steps: (i) TSV fabrication, (ii) thinning, and (iii) wafer or chip bonding after alignment, where the order of these process steps may vary depending on the integration strategy [2]. The core element of the 3D-IC technology is the TSV, which can be categorized as via-first, via-middle, and via-last according to the sequence of the TSV fabrication steps relative to the CMOS fabrication process. In the via-first (or FEOL TSV) approach, TSVs are fabricated prior to the transistor fabrication and usually doped polysilicon is used as the conductive material [8,9,10]. Via-middle type TSV (or BEOL TSV) is fabricated in between FEOL and BEOL steps, and tungsten (W) and copper (Cu) deposited by CVD are usually employed for high-aspect-ratio via filling [11,12]. These via approaches offer several advantages such as higher TSV density and aspect-ratio; however, they may only be fabricated in a CMOS foundry. In the via-last (or post-BEOL TSV) method, on the other hand, TSV fabrication is done after the completion of CMOS foundry processes. This method enables the heterogeneous integration by stacking chips/wafers from different technologies. However, the materials and processes used during the post-processing have to be compatible with the CMOS, particularly the thermal processes. 
     In the via-last TSV, the vias can be introduced either before or after aligned bonding. In via-before-bonding approach, for instance, TSVs are fabricated prior to the bonding, and then metal-metal bonding is performed to electrically connect two (or more) device layers. In the via-after-bonding approach, on the other hand, the layers are first aligned and bonded, then the TSVs are fabricated. Other varieties of these techniques can be generated depending on the sequence of the thinning step and the orientation of the bonding, face-to-face (F2F), and back-to-face (B2F). In F2F bonding, two layers are bonded as the FEOL layers are facing each other; while in B2F bonding, the wafer is usually bonded to a handle wafer, the substrate is thinned by backgrinding, and the handle wafer is released after two device wafers are bonded. Various bonding techniques have been studied extensively for 3D integration [13,14], such as direct oxide/oxide bonding, metal thermo-compression bonding, metal eutectic bonding, and polymer bonding, to mention a few. In the context of the present invention polymer bonding is considered as an effective method for the bonding since it allows bonding at lower temperatures and the bonding quality is not as sensitive to the surface topography [15]. 
     Depending on whether the integration is performed in wafer or die-level, three major chip stacking approaches can be listed as: (i) wafer-to-wafer (W2W), (ii) chip-to-wafer (C2W), and (iii) chip-to-chip (C2C). Undoubtedly, W2W integration offers the highest throughput and the alignment accuracy. However, W2W is only possible when the chip sizes are the same, substrate materials are compatible, and both wafers have very good yield. The impact of the IC chip yield on the overall TSV manufacturing cost is given with more detail in [16]. In addition, since the CMOS fabricants do not usually disclose their yield values, the estimation of the final yield would be difficult in case the integration is done in another facility. Another important difficulty for the wafer-level post-CMOS processing is that the CMOS wafer size is not always compatible to the tools available in research/university cleanrooms. For example, typical diameters of CMOS wafers are ranging from 200 mm to 300 mm, but the micromachining tools are, in general, compatible to 100 mm to 150 mm wafers. Moreover, full-wafer CMOS runs are very costly especially for research purposes and prototype development. Due to these technical limitations, die-level processing is employed here. Detailed reviews on W2W alignment and bonding can be found in [17,18, &#39;9]. 
     In die-level processing, on the other hand, it is possible to perform a pre-testing and to process only the working chips (Known-Good-Die or KGD), which in turn may lead to a higher yield and lower cost for a 3D chip stack. Furthermore, chips from a broad range of process, size and functionality can be integrated in principle. Nevertheless, a typical 3D integration process requires chip thinning, bonding, etching, via sidewall passivation, via metallization, and several photolithography steps, as explained before. Accomplishing all these tasks in die-level is very demanding and gives very low throughput considering the very small dimensions of the chips. To overcome the chip handling problems and to increase the throughput, C2W bonding techniques have been developed. In such integration, the KGDs can be aligned and bonded to a carrier or a CMOS wafer by pick-and-place tools [20]. Another very promising approach for C2C or C2W integration is surface-tension-driven self-assembly, where an aqueous solution is used in between the layers to be aligned [21]. Other alignment and assembly approaches, such as self-assembly with electrostatic attraction [22] and magnetically-assisted assembly [23], were previously presented. Using the etched silicon wafer as the template for C2W bonding and KGD stacking has also been demonstrated with good alignment accuracy [7,24,25]. A similar C2W alignment approach was proposed with a patterned BCB layer as the alignment template [26]. Such template alignment techniques eliminate the requirement of C2W bonding tools, and they promise comparable alignment accuracy by manual die insertion into the cavity. 
       FIG. 1A  summarizes the major 3D integration techniques, highlighting the ones used in this study. Combinations of these individual methods and introduction of new materials and processes bring numerous strategies, and it is difficult to pick the best solution based on the current state of the technology. Compatibility and availability of the materials and tools, targeted applications, interconnection densities, throughput, fabrication cost, and homogeneity of the layers are some of the parameters that should be considered to select the most appropriate method. What follows is a brief summary of the motivation why those particular methods have been preferred in this study. Firstly, via-first and via-middle type TSVs can only be fabricated in a CMOS foundry. Secondly, C2C integration is employed due to the technological limitations and the difficulties of wafer-level processing for heterogeneous integration, as well as due to the compatibility issue of the MEMS tools with the CMOS wafers. TSVs are fabricated after dielectric bonding in order to eliminate the reliability problems related to the metal-metal bonding. Finally, B2F orientation is preferred in order to allow stacking of multiple layers in a modular manner. Compared to the blind-via fabrication techniques where the TSV is etched from the backside till the landing metal, the proposed strategy is much simpler since it eliminates several fabrication steps, such as metal-metal bonding and passivation layer patterning. On the other hand, main drawback is that the frontside vias block the BEOL layers; thus, an exclusion zone is required for each TSV. 
     3D Integration Based on Dry-Film Lithography 
     Dry-film resist is a thick photo-definable polymer film, which has been widely used in printed circuit board manufacturing. The film can be applied by lamination regardless of the substrate shape and dimension, and it does not require any clean room facility and expensive processing tools. Thickness uniformity, fast and simple processing, excellent adhesion, almost vertical sidewalls can be listed among the benefits of dry-film, which make it attractive in MEMS applications. It has been demonstrated that the dry-film can be used as the electroplating mold in LIGA-type processes as an alternative to SU-8 [27]. Vulto et al. proposed that the film can be employed in microfluidic channel fabrication by bonding two substrates with the patterned dry-film, where the biocompatibility and liquid sealing capability were also demonstrated [28,29]. More recently, three-dimensional microfluidic structures were fabricated through multilayer lamination and direct projection lithography [30]. Particularly for the 3D integration technology, CSEM (Switzerland) researchers presented a CMOS-compatible TSV fabrication process based on dry-film lithography [31]. Later, Jacquet et al. employed the dry-film to etch the dielectric passivation only at the bottom of the via by using the tenting property of the dry-film lamination [32]. In the present invention, we employ dry-film for chip embedding, via etching (top chip), surface passivation etching (bottom chip), redistribution layer (RDL) patterning (bottom chip), and via filling by Cu electroplating (bonded stack). 
       FIG. 2  illustrates the complete process flow used for post-CMOS processing and C2C stacking. For the first verification tests, dummy silicon chips with a thermal oxide layer (1 μm) and Ti/Al (20/200 nm) test patterns are fabricated. The top chip and the bottom chip comprise complementary patterns to form the daisy-chain connections after bonding and TSV fabrication. Having diced the wafers with an automatic dicing tool, the chips are transferred to the UV grinding tape. Then, the top chip and the bottom chip are thinned down to 50 μm by using Disco DAG810 automatic grinder. The chips are then released from the grinding tape after exposing the tape to the UV light (365 nm) by Powatec U-200 UV curing tool.  FIG. 3  shows the camera photos of the wafer after dicing and grinding steps. 
     Chip Embedding 
     The proposed technique allows the processing of diced chips without the need of a carrier wafer having through openings for chip embedding. The photolithography process starts with the lamination of the dry-film on a single-side polished Si wafer (Step 1). Prior to the lamination, the wafer is exposed to O 2  plasma to clean and dehydrate the surface. ORDYL ALPHA940 (from ELGA EUROPE SRL) dry-film resist (40 μm thick) is laminated at 110° C. by using an office laminator. In this film, a negative-tone photosensitive layer is sandwiched between two polyester protective films, where the bottom protective film is removed before the lamination, and the top one is removed after exposure in order to prevent adhesion to the mask. For the exposure, two approaches can be followed: (i) exposure through the mask, and (ii) exposure by using the chip itself as the mask since dry-film is a negative-tone resist (Step 2). The first approach allows higher throughput as many chip openings can be patterned at the same time. However, this requires prior chip dimension measurement so that the mask can be designed accordingly. In the latter approach, on the other hand, the chip is placed on the dry-film and the exact chip area is transferred to the film by exposure. The disadvantage of this technique is that chips should be pre-aligned manually. After the exposure step, the unexposed regions are etched in Na 2 CO 3  1% solution. A short O 2  plasma cleaning follows the development and rinsing to remove the dry-film residuals. In this study, it is tested that 1 min (500 W) plasma cleaning is usually sufficient. Additional 1 min can be followed after inspection if there is still dry-film left at the patterned edges. However, long exposure to O 2  plasma may burn and destroy the film. 
     Photolithography and Post-Processing 
     The chips are placed into the openings in the following step (Step 3). Depending on the thickness of the chip, Si wafer with the dry-film openings can be etched by DRIE to have a deeper opening for thicker chips (Step 3.a). A second dry-film lamination step is then employed for patterning (Step 4). It is experimentally verified that the 40 μm-thick dry-film lamination can tolerate up to 100 μm of surface topography. Embedded and laminated chips are exposed to UV-light through a Cr mask for the patterning. In case the chip openings have been patterned by a mask with multiple chip opening layout, then whole wafer can be exposed with single exposure in the second photolithography step. Otherwise, if the chip itself has been used as the mask by manual placement, then each chip should be aligned and exposed one by one by using a shadow mask allowing exposure of only one chip at a time.  FIG. 4  shows the carrier wafer after chip placement and dry-film lithography, and the microscope image of the dry-film patterns for via etching. Based on the photolithography test patterns, it is concluded that the circular openings having diameters less than 40 μm cannot be defined precisely due to the resolution limit of the dry-film employed. In order to clean the dry-film residues especially left at the edges of the smaller openings, the wafer is exposed to 500 W O 2  plasma for 2 minutes. 
     Following the second dry-film patterning for the via openings (top chip), the Al pad, dielectric layers, and the Si substrate are etched by anisotropic dry etching (Step 5.a). Here, two approaches are possible. If thick chips are used (Step 3.a), a blind via is created by partial etching, and then the chip backside is grinded till the via opening is reached. In the alternative approach, chips are thinned prior to the etching and embedded into the carrier wafer (Step 3.b), and then vias are formed by through etching. Following the etching process, the via sidewalls are passivated by parylene deposition. The use of polymer liner for TSV passivation has been previously demonstrated [7,33,34]. For the present invention, however, a novel technique is employed to eliminate the dielectric etching at the bottom of the via. The through-etched chips are placed on a UV-sensitive tape as the chip frontside is facing to the tape. Then, a pinhole-free and very conformal parylene layer is deposited at room temperature (Step 6.a). This deposition passivates the sidewalls and forms a parylene layer at the chip backside, which is used as the adhesive layer during C2C bonding. After exposing the tape to UV light, the tape is released, leaving a parylene membrane on the frontside, as shown in  FIG. 5 . 
     Chip-to-Chip Bonding 
     After the post-processing, the chips are aligned and bonded (Step 7). Here, both the template alignment technique [7] and surface-tension-driven self-alignment [21] can be employed. In the latter technique, top and bottom chips are exposed to a short O 2  plasma to turn the parylene surface to hydrophilic. The bottom chip is placed on a hydrophobic surface and two chips are aligned by a water droplet. Next, aligned chips are bonded by using a low-cost thermal nanoimprinter tool (Step 8). In the test vehicle, the adhesive bonding is performed at 200° C. for 30 min in EHN-3250 Thermal Nanoimprinter (ESCO, Japan).  FIG. 6( a )  shows the cross-section of two 50 μm-thick chips bonded by parylene intermediate layer. The SEM photo of the top chip surface is given in  FIG. 6 b   ), which shows some deformation on the parylene membrane; however, this is not critical since the membrane will be etched in the next step, leaving the parylene only on the sidewalls. 
     Following the bonding, the chip stack is temporarily attached to a Si carrier wafer by using a thermoplastic polymer wax, QUICKSTICK™135. The parylene membrane is then etched by maskless anisotropic parylene etching in O 2  plasma generated by STS Multiplex ICP (Step 9). In other TSV fabrication techniques, the dielectric passivation has to be etched at the bottom of the via. This requires either photolithography steps to protect the dielectric layer elsewhere, or a well-controlled etching process to properly clean the dielectric on the landing pad. This is usually difficult knowing the fact that etch rate decreases as the aspect-ratio of the via increases. The proposed approach, on the other hand, allows parylene etching only on the surface, which is much easier and controllable. Moreover, the technique allows both sidewall passivation and backside adhesive layer deposition steps in single parylene run.  FIG. 7( a )  shows the SEM images of the etched and passivated vias just after anisotropic parylene etching, showing the parylene residuals at the via edges. Thereby, the wafer with the mounted chip stacks is rinsed in DI water and dried with the N 2 .  FIG. 7( b )  shows the chip stack after the washing and drying steps, showing no visible parylene residual. 
     Cu Electroplating 
     In order to finalize the TSV, a conductive layer connecting the bottom pad to the top is required. Cu lining electro-deposition process is preferred since it allows less electro-deposition time compared to fully filling the openings [35]. In addition, more complex electroplating bath chemistries and techniques for void-free superconformal filling are avoided. In the present context, Cu lining is electroplated with INTERVIA Cu 8510 bath by using sputtered Cu film as the seed layer. Prior to the deposition, the chip surface, particularly the oxide layer on the Al pads, is cleaned by Ar ion bombardment in BAS450 sputtering tool. Then, without breaking the vacuum, 500 nm of Cu is sputtered by DC magnetron sputtering (Step 10). Similar to the aforementioned photolithography steps, dry-film resist is laminated and patterned in order to inhibit the electroplating in the areas other than the TSV openings (Step 11). After the dry-film lithography, the wafer is exposed to 1 min of O 2  plasma to clean the dry-film residuals inside the openings and to increase the surface wettability. Electroplating is performed by applying a DC current controlled by a general-purpose potentiostat (from AMEL instruments).  FIG. 8  shows the electroplated Cu grown inside the dry-film mask. 
     Following the electroplating, rinsing and drying steps, the dry-film resist is stripped in NaOH 2.5% solution. Alternatively, it is verified that metal-ion-free positive-resist strippers can be employed with the help of elevated temperature (around 65° C.) and ultrasonic agitation. Cu seed layer is etched in (NH 4 ) 2 S 2 O 8 +H 2 SO 4  (96%) solution for 3 minutes with an etch rate of 200 nm/min. This etchant also etches the electroplated Cu, however, the etched thickness is negligible compared to the initial thickness of the electrodeposited Cu. The compatibility of the temporary mounting wax to this etchant is also verified in this step. The chip stack after the maskless seed layer etching is shown in  FIG. 9 , which clearly demonstrates the precision of the alignment and uniformity of the electroplating. Some roughness on Cu is observed and it is believed to be related to poor composition of the electroplating bath. 
     For the cross-section inspection, the chips are released from the carrier wafer by placing the wafer on a hot plate around 100° C., at which the wax softens. The wax residuals at the chip backside are cleaned by acetone followed by isopropyl alcohol (IPA) cleaning. Then, the chip surface is covered by a special resin, and one edge of the stack is polished till the middle of the via.  FIG. 10  shows the cross-section of the TSVs after the polishing step. The continuous Cu line from bottom pad to the top and the parylene between the chips and on the sidewalls are clearly visible. The off-centered plating at the top of the via is related to the misalignment of the final dry-film lithography. It is also seen that the Cu thickness decreases at the bottom of the via. This phenomenon is related to the higher electroplating rate at the chip surface, which can be controlled by optimizing the concentrations of the organic additives (accelerator, suppressor, and leveler), and by using reverse pulse electroplating techniques. 
     Daisy-Chain Measurements 
     After the fabrication is finalized, the resistance measurements are performed for the TSVs connected in daisy-chain pattern. The series resistance is measured by HP4155B Semiconductor Parameter Analyzer connected to Karl Suss PM8 manual probe station. In order to have a statistical distribution of the TSV resistance and to demonstrate the reliability of the process, row resistance from 5 different chip stacks (each stack is composed of two 50 μm-thick chips having 16 rows, 16 columns, thus 256 TSVs.) is measured.  FIG. 11( a )  shows the row resistances (16 TSVs in series) including the interconnection resistance and off-chip cables. Among 1280 TSVs measured, just 10 open-circuit defects are detected, resulting in more than 99% yield. Moreover, the average row resistance is calculated as 33.8Ω with 3.3Ω standard deviation. The total contribution of the interconnections is then subtracted from the measured value and the resistance of single TSV is calculated as 0.5Ω, in average. Moreover, the chip is placed on a hot plate at 200° C. for 5 min and the resistance of the same rows are measured again.  FIG. 11( b )  gives the average resistance values before and after heat treatment, demonstrating no significant change. 
     CMOS Post-Processing and 3D Integration 
     Having verified the reliability of the proposed fabrication process with the dummy Si chips, the method is tested on real CMOS chips. Here, a multiprocessor chip is used as the test vehicle. The platform is aimed to be composed of completely identical stacked dies connected by TSVs, where each die features four 32-bit embedded processors and associated memory modules. The chip is manufactured in 10-metal UMC 90 nm process and measures 4×4 mm 2 . The details of the processor architecture and the modular 3D multiprocessor approach can be found in [4]. 
     Prior to the post-processing, the dimensions of CMOS chips are measured.  FIG. 12  shows the pad-to-edge distance along all directions, where the mean and standard deviation values are calculated as 37 μm and 1.1 μm, respectively. This result shows that mask and C2C alignment steps can be done in good precision based on the physical dimensions. Firstly, 40 μm diameter via openings are etched on 60×60 μm 2  CMOS pads on the top chip by using AI RIE (1.2 μm), dielectric RIE (10 μm), and Si DRIE (40 μm), respectively. It is verified that 40 μm-thick dry-film is thick enough to survive till the end of all dry etching steps, especially the dielectric etching which has lower selectivity to the organic resists. 1 μm-thick parylene film is deposited to isolate the via sidewalls and the chip backside, where it will be used as the adhesive layer for bonding.  FIG. 13( a )  shows the parylene membrane after releasing the UV tape. 
     Since the two chips are targeted to be identical to reduce the non-recurring engineering costs, the surface of the bottom chip is passivated and RDL is patterned to reroute the signal to the upper tier. After the parylene passivation and patterning steps by dry-film lithography, RDL is patterned by lift-off process using the dry-film as the sacrificial layer. Alignment and bonding are done as explained for the dummy chips. Finally, parylene membrane on the top chip is etched by anisotropic O 2  plasma etching, as shown in  FIG. 13( b ) .  FIG. 14  shows the SEM images of the 50 μm- and 280 μm-thick CMOS chips post-processed, aligned and bonded in die-level. Currently, the impact of individual steps to the CMOS performance is being tested by the test setup explained in [4]. 
     CONCLUSION 
     A C2C 3D integration platform based on post-CMOS processing and dry-film lithography is presented. Proposed techniques are applied to diced and thinned Si chips emulating real CMOS chips. Although the technology is demonstrated in die-level, some of the process steps are compatible to wafer-level processing as well. Two 50 μm-thick chips are successfully bonded, and then 60 μm-diameter TSVs with parylene sidewall passivation and electroplated Cu metallization are fabricated. It is believed that the TSV aspect-ratio can be increased by using MOCVD instead of PVD for the seed layer deposition, and by an electroplating setup enabling high-aspect-ratio deposition. A method eliminating the requirement of dielectric etching at the bottom of the via is demonstrated. Daisy-chain measurements show 0.5Ω TSV resistance in average, with a yield of more than 99% for 1280 TSVs from 5 different chip stacks. Then, the techniques are applied to CMOS microprocessor chips. For the bottom chip, the surface is passivated by parylene, which is patterned by dry-film lithography and RDL is fabricated by the Al lift-off process. For the top chip, Al, dielectric, and Si etching steps are performed by using a dry-film mask. Two chips are aligned by surface-tension-driven alignment and bonded at 200° C. by using a low-cost nanoimprinter tool. According to the invention the 3D integration technology, which is considered to be a very challenging process, can be accomplished in a MEMS clean room without using any expensive tool developed for this purpose. We believe that this chip-level post-processing technique can be used not only for chip stacking but also for applications where the CMOS layers have to be modified by surface or bulk micromachining, in case full CMOS wafer is not available or compatible, or very expensive for research purposes. 
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