Patent Publication Number: US-2023134201-A1

Title: Semiconductor package

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2021-0145562, filed on Oct. 28, 2021 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. 
     TECHNICAL FIELD 
     Embodiments of the present disclosure relate to a semiconductor package. 
     DISCUSSION OF RELATED ART 
     As advances are made in the implementation of high-performance elements, sizes of semiconductor chips have increased, and as a result, sizes of semiconductor packages have also increased. Meanwhile, the thickness of semiconductor packages has been decreasing in light of the demand for thin electronic devices. 
     Semiconductor packages are being developed to satisfy the demands for multi-functionality, high capacity, and miniaturization. For this reason, by incorporating a plurality of semiconductor chips into a single semiconductor package, it has become possible to implement high capacity and multi-functional devices, while significantly reducing the size of semiconductor packages used in such devices. 
     SUMMARY 
     Embodiments of the present disclosure provide a semiconductor package in which a structural stability between a wiring post and a wiring pad is increased, by disposing at least a part of the wiring post inside a recess formed in the wiring pad, inside a redistribution layer. 
     According to embodiments of the present disclosure, a semiconductor package includes a first wiring pattern, and a first redistribution layer disposed on an upper surface of the substrate. The first redistribution layer includes a first wiring pad, a first recess formed on an upper surface of the first wiring pad, a first metal seed layer disposed on sidewalls and a bottom surface of the first recess, and a first wiring post at least partially disposed on the first metal seed layer inside the first recess. The semiconductor package further includes a first solder resist layer disposed on an upper surface of the first redistribution layer and including a second recess formed inside the first solder resist layer, a first conductive terminal disposed on sidewalls and a bottom surface of the second recess, a first solder ball disposed on the first conductive terminal, and a first semiconductor chip disposed on the first solder resist layer and electrically directly connected to the first redistribution layer through the first solder ball. 
     According to embodiments of the present disclosure, a semiconductor package includes a substrate including a first wiring pattern, a wiring pad disposed on an upper surface of the substrate, a first recess recessed from an upper surface of the wiring pad toward the upper surface of the substrate, a metal seed layer disposed on sidewalls and a bottom surface of the first recess, and a wiring post at least partially disposed on the metal seed layer inside the first recess. The wiring post is in contact with the metal seed layer disposed on the sidewalls of the first recess, and the wiring post extends in a vertical direction. The semiconductor package further includes a second wiring pattern disposed on an upper surface of the wiring post. The second wiring pattern is in contact with the wiring post. The semiconductor package further includes a solder resist layer disposed on the second wiring pattern. The upper surface of the wiring post is higher than the upper surface of the wiring pad, and the upper surface of the wiring post is lower than a lower surface of the solder resist layer. 
     According to embodiments of the present disclosure, a semiconductor package includes a substrate including a first wiring pattern, a wiring pad disposed on an upper surface of the substrate, a first recess recessed from an upper surface of the wiring pad toward the upper surface of the substrate, a metal seed layer disposed along two sidewalls and a bottom surface of the first recess, and a wiring post at least partially disposed on the metal seed layer inside the first recess. The wiring post is in contact with the metal seed layer disposed on the two sidewalls of the first recess, and the wiring post extends in a vertical direction. The semiconductor package further includes a second wiring pattern disposed on an upper surface of the wiring post and in contact with the wiring post, a solder resist layer disposed on the second wiring pattern, a second recess formed inside the solder resist layer, a conductive terminal disposed along sidewalls and a bottom surface of the second recess, a first solder ball disposed on a lower surface of the substrate, a second solder ball disposed on the conductive terminal, and a semiconductor chip disposed on the solder resist layer and electrically directly connected to the second wiring pattern through the second solder ball. The upper surface of the wiring post is higher than the upper surface of the wiring pad, and the upper surface of the wiring post is lower than a lower surface of the solder resist layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features of the present disclosure will become more apparent by describing in detail embodiments thereof with reference to the accompanying drawings, in which: 
         FIG.  1    is a diagram illustrating a semiconductor package according to embodiments of the present disclosure; 
         FIG.  2    is an enlarged view of a region A of  FIG.  1    according to embodiments of the present disclosure; 
         FIGS.  3  to  16    are intermediate process diagrams illustrating a method of fabricating a semiconductor package according to embodiments of the present disclosure; 
         FIG.  17    is an enlarged view of a semiconductor package according to embodiments of the present disclosure; 
         FIG.  18    is an enlarged view illustrating a semiconductor package according to embodiments of the present disclosure; 
         FIG.  19    is an enlarged view illustrating a semiconductor package according to embodiments of the present disclosure; 
         FIG.  20    is an enlarged view illustrating a semiconductor package according to embodiments of the present disclosure; 
         FIG.  21    is a diagram illustrating a semiconductor package according to embodiments of the present disclosure; and 
         FIG.  22    is an enlarged view of a region B of  FIG.  21    according to embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the accompanying drawings. 
     It will be understood that the terms “first,” “second,” “third,” etc. are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a “first” element in an embodiment may be described as a “second” element in another embodiment. 
     It should be understood that descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, unless the context clearly indicates otherwise. 
     As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. 
     Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper”, etc., may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. 
     It will be understood that when a component such as a film, a region, a layer, or an element, is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another component, it can be directly on, connected, coupled, or adjacent to the other component, or intervening components may be present. It will also be understood that when a component is referred to as being “between” two components, it can be the only component between the two components, or one or more intervening components may also be present. It will also be understood that when a component is referred to as “covering” another component, it can be the only component covering the other component, or one or more intervening components may also be covering the other component. Other words used to describe the relationships between components should be interpreted in a like fashion. 
     Herein, when one value is described as being about equal to another value or being substantially the same as or equal to another value, it is to be understood that the values are identical, the values are equal to each other within a measurement error, or if measurably unequal, are close enough in value to be functionally equal to each other as would be understood by a person having ordinary skill in the art. For example, the term “about” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations as understood by one of the ordinary skill in the art. Further, it is to be understood that while parameters may be described herein as having “about” a certain value, according to embodiments, the parameter may be exactly the certain value or approximately the certain value within a measurement error as would be understood by a person having ordinary skill in the art. 
     Hereinafter, a semiconductor package according to embodiments of the present disclosure will be described with reference to  FIGS.  1  and  2   . 
       FIG.  1    is a diagram illustrating a semiconductor package according to embodiments of the present disclosure.  FIG.  2    is an enlarged view of a region A of  FIG.  1    according to embodiments of the present disclosure. 
     Referring to  FIGS.  1  and  2   , the semiconductor package according to embodiments of the present disclosure includes a substrate  100 , a first wiring pattern  105 , a first redistribution layer  110 , a first solder resist layer  120 , a first conductive terminal  130 , a first semiconductor chip  140 , a first solder ball  151 , a second solder ball  152 , a first underfill material  160 , and a first mold layer  170 . 
     The substrate  100  may be, for example, a printed circuit board (PCB) or a ceramic substrate. However, embodiments of the present disclosure are not limited thereto. 
     When the substrate  100  is a printed circuit board, the substrate  100  may be made of at least one of, for example, phenol resin, epoxy resin, and polyimide. For example, the substrate  100  may include at least one of FR4, tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, BT (bismaleimide triazine), thermount, cyanate ester, polyimide, and liquid crystal polymer. 
     The first wiring pattern  105  may be disposed inside the substrate  100 . The first wiring pattern  105  may include a plurality of wirings spaced apart from each other in a horizontal direction DR 1 . Further, the first wiring pattern  105  may include a plurality of wirings spaced apart from each other in a vertical direction DR 2 . The first wiring pattern  105  may include a conductive material. 
     The first solder ball  151  may be disposed on a lower surface  100   b  of the substrate  100 . The first solder ball  151  may be in contact with the first wiring pattern  105  disposed on the lower surface  100   b  of the substrate  100 . The first solder ball  151  may protrude convexly from the lower surface  100   b  of the substrate  100 . The first solder ball  151  may be a portion by which the substrate  100  is electrically connected to another external element. 
     The first solder ball  151  may include, for example, at least one of tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), and combinations thereof. However, embodiments of the present disclosure are not limited thereto. 
     The first redistribution layer  110  may be disposed on an upper surface  100   a  of the substrate  100 . A lower surface  110   b  of the first redistribution layer  110  may be in contact with the upper surface  100   a  of the substrate  100 . The first redistribution layer  110  may include a first wiring pad  111 , a first metal seed layer  112 , a first wiring post  113 , a second wiring pattern  114 , and a first interlayer insulating film  115 . 
     The first wiring pad  111  may be disposed on the upper surface  100   a  of the substrate  100 . The first wiring pad  111  may be in contact with the first wiring pattern  105 . For example, the first wiring pad  111  may be directly electrically connected to the first wiring pattern  105 . However, embodiments of the present disclosure are not limited thereto. For example, in embodiments, a metal seed layer may be disposed between the upper surface  100   a  of the substrate  100  and the first wiring pad  111 . The first wiring pad  111  may include a plurality of pads spaced apart from each other in the horizontal direction DR 1 . 
     A width W 2  of the first wiring pad  111  in the horizontal direction DR 1  may have a range of about 35 µm to about 130 µm. The first wiring pad  111  may include, for example, copper (Cu). In embodiments, the first wiring pad  111  may include, for example, at least one of tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), and combinations thereof. 
     A first recess R 1  may be formed inside the first wiring pad  111 . The first recess R 1  may be recessed from an upper surface  111   a  of the first wiring pad  111  toward the upper surface  100   a  of the substrate  100 . A bottom surface of the first recess R 1  may be formed inside the first wiring pad  111 . 
     The first recess R 1  may include a first sidewall R 1 _ s   1 , and a second sidewall R 1 _ s   2  disposed opposite to the first sidewall R 1 _ s   1  in the horizontal direction DR 1 . For example, a width W 1  of the first recess R 1  in the horizontal direction DR 1  may have a range of about 20 µm to about 100 µm. Here, the width W 1  of the first recess R 1  in the horizontal direction DR 1  may be defined as a width in the horizontal direction DR 1  between the first sidewall R 1 _ s   1  of the first recess R 1  and the second sidewall R 1 _ s   2  of the first recess R 1 . For example, the width W 1  of the first recess R 1  in the horizontal direction DR 1  may be formed to be about 80% or less of the width W 2  of the first wiring pad  111  in the horizontal direction DR 1 . 
     For example, a depth d of the first recess R 1  in the vertical direction DR 2  may have a range of about 0.5 µm to about 3 µm. The depth d of the first recess R 1  in the vertical direction DR 2  may be defined as a depth in the vertical direction DR 2  from the upper surface  111   a  of the first wiring pad  111  to a bottom surface of the first recess R 1 . 
     The first metal seed layer  112  may be disposed along the first sidewall R 1 _ s   1 , the second sidewall R 1 _ s   2 , and the bottom surface of the first recess R 1 . For example, the first metal seed layer  112  may be conformally formed along the first sidewall R 1 _ s   1 , the second sidewall R 1 _ s   2 , and the bottom surface of the first recess R 1 . For example, an uppermost surface of the first metal seed layer  112  may be formed on the same plane as the upper surface  111   a  of the first wiring pad  111 . For example, a thickness t of the first metal seed layer  112  may have a range of about 0.3 µm to about 3 µm. 
     The first metal seed layer  112  may include, for example, copper (Cu). In embodiments, the first metal seed layer  112  may include, for example, at least one of tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), and combinations thereof. 
     For example, the first metal seed layer  112  may include the same material as the first wiring pad  111 . For example, each of the first metal seed layer  112  and the first wiring pad  111  may include copper (Cu). In this case, the copper (Cu) included in the first metal seed layer  112  may have a finer structure than the copper (Cu) included in the first wiring pad  111 . 
     The first wiring post  113  may be disposed on the first metal seed layer  112 . At least a part of the first wiring post  113  may be disposed inside the first recess R 1 . The first wiring post  113  may extend in the vertical direction DR 2 . For example, the first wiring post  113  may extend lengthwise in the vertical direction DR 2 . 
     The first wiring post  113  may be in contact with the first metal seed layer  112  disposed on the first sidewall R 1 _ s   1  of the first recess R 1 . Further, the first wiring post  113  may be in contact with the first metal seed layer  112  disposed on the second sidewall R 1 _ s   2  of the first recess R 1 . The first wiring post  113  may be in contact with the first metal seed layer  112  disposed on the bottom surface of the first recess R 1 . The first recess R 1  may be completely filled by the first metal seed layer  112  and the first wiring post  113 . 
     An upper surface  113   a  of the first wiring post  113  may be formed to be higher than the upper surface  111   a  of the first wiring pad  111 . The upper surface  113   a  of the first wiring post  113  may be formed to be lower than the upper surface  110   a  of the first redistribution layer  110 . The upper surface  113   a  of the first wiring post  113  may be formed to be lower than the lower surface of the first solder resist layer  120 . 
     A width W 3  of the first wiring post  113  in the horizontal direction DR 1  may be smaller than the width W 2  of the first wiring pad  111  in the horizontal direction DR 1 . The width W 3  of the first wiring post  113  in the horizontal direction DR 1  may be smaller than the width W 1  of the first recess R 1  in the horizontal direction DR 1 . 
     The first wiring post  113  may include, for example, copper (Cu). In embodiments, the first wiring post  113  may include, for example, at least one of tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), and combinations thereof. 
     For example, the first wiring post  113  may include the same material as the first metal seed layer  112 . For example, each of the first wiring post  113  and the first metal seed layer  112  may include copper (Cu). In this case, the copper (Cu) included in the first metal seed layer  112  may have a finer structure than the copper (Cu) included in the first wiring post  113 . 
     The second wiring pattern  114  may be disposed on the upper surface of the first wiring post  113 . The second wiring pattern  114  may include a plurality of wirings spaced apart from each other in the horizontal direction DR 1 . Further, the second wiring pattern  114  may include a plurality of wirings spaced apart from each other in the vertical direction DR 2 . The second wiring pattern  114  may include a conductive material. 
     The first interlayer insulating film  115  may be disposed on the upper surface  100   a  of the substrate  100 . The first interlayer insulating film  115  may surround the first wiring pad  111 , the first metal seed layer  112 , the first wiring post  113 , and the second wiring pattern  114 . For example, the upper surface of the first interlayer insulating film  115  may form the upper surface  110   a  of the first redistribution layer  110 . For example, the upper surface of the first interlayer insulating film  115  may be formed on the same plane as the uppermost surface of the second wiring pattern  114 . The first interlayer insulating film  115  may include an insulating material. 
     The first solder resist layer  120  may be disposed on the upper surface  110   a  of the first redistribution layer  110 . The first solder resist layer  120  may be in contact with each of the upper surface  110   a  of the first redistribution layer  110  and the uppermost surface of the second wiring pattern  114 . The first solder resist layer  120  may include, for example, photo solder resist (PSR) ink. 
     A second recess R 2  may be formed inside the first solder resist layer  120 . The second recess R 2  may extend in the vertical direction DR 2  from the upper surface of the first solder resist layer  120  to the lower surface of the first solder resist layer  120 . The second wiring pattern  114  may be exposed by the second recess R 2 . 
     The first conductive terminal  130  may be disposed along the sidewalls and the bottom surface of the second recess R 2 . Further, at least a part of the first conductive terminal  130  may be disposed on the upper surface of the first solder resist layer  120  adjacent to both sidewalls of the second recess R 2 . The first conductive terminal  130  may include a conductive material. 
     The second solder ball  152  may be disposed on the first conductive terminal  130 . The second solder ball  152  may protrude from the first conductive terminal  130  in the vertical direction DR 2 . The second solder ball  152  may include, for example, at least one of tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), and combinations thereof. However, embodiments of the present disclosure are not limited thereto. 
     The first semiconductor chip  140  may be disposed on the upper surface of the first solder resist layer  120 . The first semiconductor chip  140  may be electrically connected to the second solder ball  152 . The first semiconductor chip  140  may be electrically directly connected to the first redistribution layer  110  through the second solder ball  152 . 
     The first underfill material  160  may surround the sidewalls of the second solder ball  152  between the upper surface of the first solder resist layer  120  and the first semiconductor chip  140 . The first underfill material  160  may be formed to further protrude laterally from the sidewalls of the first semiconductor chip  140 . However, embodiments of the present disclosure are not limited thereto. 
     The first mold layer  170  may surround the sidewalls of the first underfill material  160 , and the sidewalls and the upper surface of the first semiconductor chip  140 , on the upper surface of the first solder resist layer  120 . However, embodiments of the present disclosure are not limited thereto. For example, in embodiments, the upper surface of the first mold layer  170  may be formed on the same plane as the upper surface of the first semiconductor chip  140 . The first mold layer  170  may include, for example, an epoxy molding compound (EMC) or two or more types of silicone hybrid materials. However, embodiments of the present disclosure are not limited thereto. 
     In the semiconductor package according to embodiments of the present disclosure, because at least a part of the first wiring post  113  is disposed inside the first recess R 1  formed in the first wiring pad  111 , the structural stability between the first wiring post  113  and the first wiring pad  111  can be increased. 
     Hereinafter, a method of fabricating a semiconductor package according to embodiments of the present disclosure will be described with reference to  FIGS.  1  to  16   . 
       FIGS.  3  to  16    are intermediate process diagrams illustrating a method of fabricating a semiconductor package according to embodiments of the present disclosure. 
     Referring to  FIG.  3   , the substrate  100  may be provided. The first wiring pattern  105  may be formed inside the substrate  100 . The uppermost surface of the first wiring pattern  105  may be exposed on the upper surface  100   a  of the substrate  100 . Further, the lowermost surface of the first wiring pattern  105  may be exposed on the lower surface  100   b  of the substrate  100 . 
     Referring to  FIG.  4   , the first wiring pad  111  may be formed on the upper surface  100   a  of the substrate  100 . The first wiring pad  111  may be formed to be in contact with the first wiring pattern  105  exposed on the upper surface  100   a  of the substrate  100 . However, embodiments of the present disclosure are not limited thereto. For example, in embodiments, the first wiring pad  111  may be grown using a metal seed layer formed on the upper surface  100   a  of the substrate  100  as a seed. In this case, a metal seed layer may be formed between the upper surface  100   a  of the substrate  100  and the first wiring pad  111 . 
     Referring to  FIGS.  5  and  6   , a first mask pattern M 1  may be formed on the upper surface  100   a  of the substrate  100  and the first wiring pad  111 . Subsequently, by etching a part of the first wiring pad  111  using the first mask pattern M 1  as a mask, the first recess R 1  may be formed. A bottom surface of the first recess R 1  may be formed inside the first wiring pad  111 . That is, the bottom surface of the first recess R 1  may be formed between the upper surface  100   a  of the substrate  100  and the upper surface  111   a  of the first wiring pad  111 . 
     Referring to  FIGS.  7  and  8   , the first mask pattern M 1  may be removed. 
     Referring to  FIG.  9   , the first metal seed layer  112  may be formed on the upper surface  100   a  of the substrate  100 , and the sidewalls and the upper surface  111   a  of the first wiring pad  111 . Further, the first metal seed layer  112  may be formed on the first sidewall R 1 _ s   1 , the second sidewall R 1 _ s   2 , and the bottom surface of the first recess R 1 . The first metal seed layer  112  may be formed, for example, conformally. For example, the first metal seed layer  112  may be formed conformally on the first sidewall R 1 _ s   1 , the second sidewall R 1 _ s   2 , and the bottom surface of the first recess R 1 . 
     Referring to  FIGS.  10  and  11   , a second mask pattern M 2  may be formed on the first metal seed layer  112 . The second mask pattern M 2  may expose the first metal seed layer  112  formed on the bottom surface of the first recess R 1 . The second mask pattern M 2  may overlap the first metal seed layer  112  formed on the first sidewall R 1 _ s   1  of the first recess R 1  in the vertical direction DR 2 . Further, the second mask pattern M 2  may overlap the first metal seed layer  112  formed on the second sidewall R 1 _ s   2  of the first recess R 1  in the vertical direction DR 2 . 
     Referring to  FIGS.  12  and  13   , the first wiring post  113  may be formed on the first metal seed layer  112  inside the first recess R 1 . The interior of the first recess R 1  may be completely filled with the first metal seed layer  112  and the first wiring post  113 . 
     Referring to  FIGS.  14  and  15   , the second mask pattern M 2  may be removed. Therefore, the sidewalls and the upper surface  111   a  of the first wiring pad  111 , the uppermost surface of the first metal seed layer  112 , and a part of the sidewalls and the upper surface of the first wiring post  113  may be exposed. 
     Referring to  FIG.  16   , the first interlayer insulating film  115  may be formed on the upper surface  100   a  of the substrate  100 . The first interlayer insulating film  115  may cover the sidewalls and the upper surface  111   a  of the first wiring pad  111 , the uppermost surface of the first metal seed layer  112 , and a part of the sidewalls and the upper surface of the first wiring post  113 . 
     Subsequently, the second wiring pattern  114  may be formed on the upper surface  113   a  of the first wiring post  113  inside the first interlayer insulating film  115 . The sidewalls of the second wiring pattern  114  may be surrounded by the first interlayer insulating film  115 . Through such a fabrication process, the first redistribution layer  110  may be formed on the upper surface  100   a  of the substrate  100 . 
     Subsequently, the first solder resist layer  120  may be formed on the upper surface  110   a  of the first redistribution layer  110 . The first solder resist layer  120  may be formed conformally. However, embodiments of the present disclosure are not limited thereto. 
     Subsequently, the second recess R 2  may be formed inside the first solder resist layer  120 . The second recess R 2  may penetrate the first solder resist layer  120  in the vertical direction DR 2 . At least a part of the second wiring pattern  114  may be exposed on the bottom surface of the second recess R 2 . 
     Referring back to  FIG.  1   , the first conductive terminal  130  may be formed on the sidewalls and the bottom surface of the second recess R 2 . Further, at least a part of the first conductive terminal  130  may also be formed on the upper surface of the first solder resist layer  120  adjacent to both sidewalls of the second recess R 2 . 
     Subsequently, the first semiconductor chip  140  may be formed on the upper surface of the first solder resist layer  120 . The first semiconductor chip  140  may be attached to the first conductive terminal  130  through the second solder ball  152 . Next, the first underfill material  160  may be formed to surround the sidewalls of the second solder ball  152  between the upper surface of the first solder resist layer  120  and the first semiconductor chip  140 . Subsequently, the first mold layer  170  may be formed on the upper surface of the first solder resist layer  120  to surround the sidewalls of the first underfill material  160 , and the sidewalls and the upper surface of the first semiconductor chip  140 . The semiconductor package shown in  FIG.  1    may be fabricated through such a fabrication process. 
     Hereinafter, a semiconductor package according to embodiments of the present disclosure will be described with reference to  FIG.  17   . For convenience of explanation, a further description of components and technical aspects previously described may be omitted, and differences from the semiconductor device shown in  FIGS.  1  and  2    will be mainly described. 
       FIG.  17    is an enlarged view illustrating a semiconductor package according to embodiments of the present disclosure. 
     Referring to  FIG.  17   , in the semiconductor package according to embodiments of the present disclosure, each of a first wiring post  213  and a first metal seed layer  212  is not disposed on a part of the bottom surface of the first recess R 1 . 
     For example, each of the first wiring post  213  and the first metal seed layer  212  may be spaced apart from the second sidewall R 1 _ s   2  of the first recess R 1 . In an embodiment according to  FIG.  17   , the first metal seed layer  212  is not disposed on the second sidewall R 1 _ s   2  of the first recess R 1  and the bottom surface of the first recess R 1  adjacent to the second sidewall R 1 _ s   2  of the first recess R 1 . The first interlayer insulating film  115  may be disposed between the second sidewall R 1 _ s   2  of the first recess R 1  and the first wiring post  213 . Further, the first interlayer insulating film  115  may be disposed between the second sidewall R 1 _ s   2  of the first recess R 1  and the first metal seed layer  212 . 
     A width W 4  of the first wiring post  213  in the horizontal direction DR 1  may be smaller than the width W 2  of the first wiring pad  111  in the horizontal direction DR 1 . The width W 4  of the first wiring post  213  in the horizontal direction DR 1  may be smaller than the width W 1  (see  FIG.  2   ) of the first recess R 1  in the horizontal direction DR 1 . 
     Hereinafter, a semiconductor package according to embodiments of the present disclosure will be described with reference to  FIG.  18   . Differences from the semiconductor device shown in  FIGS.  1  and  2    will be mainly described. 
       FIG.  18    is an enlarged view illustrating a semiconductor package according to embodiments of the present disclosure. 
     Referring to  FIG.  18   , in the semiconductor package according to embodiments of the present disclosure, each of at least a part of the first metal seed layer  312  and at least a part of the first wiring post  313  may be disposed on the upper surface  111   a  of the first wiring pad  111 . 
     For example, each of at least a part of the first metal seed layer  312  and at least a part of the first wiring post  313  may be disposed on the upper surface  111   a  of the first wiring pad  111  adjacent to the first sidewall R 1 _ s   1  of the first recess R 1 . Further, each of at least a part of the first metal seed layer  312  and at least a part of the first wiring post  313  may be disposed on the upper surface  111   a  of the first wiring pad  111  adjacent to the second sidewall R 1 _ s   2  of the first recess R 1 . 
     A width W 5  of the first wiring post  313  in the horizontal direction DR 1  may be smaller than the width W 2  of the first wiring pad  111  in the horizontal direction DR 1 . The width W 5  of the first wiring post  313  in the horizontal direction DR 1  may be larger than the width W 1  (see  FIG.  2   ) of the first recess R 1  in the horizontal direction DR 1 . 
     Hereinafter, a semiconductor package according to embodiments of the present disclosure will be described with reference to  FIG.  19   . For convenience of explanation, a further description of components and technical aspects previously described may be omitted, and differences from the semiconductor device shown in  FIGS.  1  and  2    will be mainly described. 
       FIG.  19    is an enlarged view illustrating a semiconductor package according to embodiments of the present disclosure. 
     Referring to  FIG.  19   , in the semiconductor package according to embodiments of the present disclosure, each of at least a part of a first metal seed layer  412  and at least a part of a first wiring post  413  may be disposed on the upper surface  111   a  of the first wiring pad  111 . 
     For example, at least a part of the first metal seed layer  412  and at least a part of the first wiring post  413  may each be disposed on the upper surface  111   a  of the first wiring pad  111  adjacent to the first sidewall R 1 _ s   1  of the first recess R 1 . An upper surface of the first metal seed layer  412  disposed on the second sidewall R 1 _ s   2  of the first recess R 1  may be in contact with the first interlayer insulating film  115 . 
     A width W6 of the first wiring post  413  in the horizontal direction DR 1  may be smaller than the width W 2  of the first wiring pad  111  in the horizontal direction DR 1 . The width W6 of the first wiring post  413  in the horizontal direction DR 1  may be larger than the width W 1  (see  FIG.  2   ) of the first recess R 1  in the horizontal direction DR 1 . However, embodiments of the present disclosure are not limited thereto. For example, in embodiments, the width W6 of the first wiring post  413  in the horizontal direction DR 1  may be smaller than the width W 1  (see  FIG.  2   ) of the first recess R 1  in the horizontal direction DR 1 . 
     Hereinafter, a semiconductor package according to embodiments of the present disclosure will be described with reference to  FIG.  20   . For convenience of explanation, a further description of components and technical aspects previously described may be omitted, and differences from the semiconductor devices shown in  FIGS.  1  and  2    will be mainly described. 
       FIG.  20    is an enlarged view illustrating a semiconductor package according to embodiments of the present disclosure. 
     Referring to  FIG.  20   , in the semiconductor package according to embodiments of the present disclosure, each of a first wiring post  513  and a first metal seed layer  512  is not disposed on a part of the bottom surface of the first recess R 1 . Further, each of at least a part of the first metal seed layer  512  and at least a part of the first wiring post  513  is not disposed on the upper surface  111   a  of the first wiring pad  111 . 
     For example, each of the first wiring post  513  and the first metal seed layer  512  may be spaced apart from the second sidewall R 1 _ s   2  of the first recess R 1 . In an embodiment according to  FIG.  20   , the first metal seed layer  512  is not disposed on the second sidewall R 1 _ s   2  of the first recess R 1  and the bottom surface of the first recess R 1  adjacent to the second sidewall R 1 _ s   2  of the first recess R 1 . The first interlayer insulating film  115  may be disposed between the second sidewall R 1 _ s   2  of the first recess R 1  and the first wiring post  513 . Further, the first interlayer insulating film  115  may be disposed between the second sidewall R 1 _ s   2  of the first recess R 1  and the first metal seed layer  512 . 
     For example, at least a part of the first metal seed layer  512  and at least a part of the first wiring post  513  may each be disposed on the upper surface  111   a  of the first wiring pad  111  that is adjacent to the first sidewall R 1 _ s   1  of the first recess R 1 . A width W 7  of the first wiring post  513  in the horizontal direction DR 1  may be smaller than the width W 2  of the first wiring pad  111  in the horizontal direction DR 1 . 
     Hereinafter, a semiconductor package according to embodiments of the present disclosure will be described with reference to  FIGS.  21  and  22   . For convenience of explanation, a further description of components and technical aspects previously described may be omitted, and differences from the semiconductor device shown in  FIGS.  1  and  2    will be mainly described. 
       FIG.  21    is a diagram illustrating a semiconductor package according to embodiments of the present disclosure.  FIG.  22    is an enlarged view of a region B of  FIG.  21    according to embodiments of the present disclosure. 
     Referring to  FIGS.  21  and  22   , a semiconductor package according to embodiments of the present disclosure further includes an interposer  600 , a third wiring pattern  605 , a second redistribution layer  610 , a second solder resist layer  620 , a second conductive terminal  630 , a second semiconductor chip  640 , a third solder ball  653 , a second underfill material  660 , a second mold layer  670 , and a connecting via  680 . 
     The interposer  600  may be disposed on the first semiconductor chip  140 . For example, the interposer  600  may be disposed on the upper surface of the first mold layer  170 . The third wiring pattern  605  may be disposed inside the interposer  600 . The third wiring pattern  605  may include a plurality of wirings spaced apart from each other in the horizontal direction DR 1 . Further, the third wiring pattern  605  may include a plurality of wirings spaced apart from each other in the vertical direction DR 2 . The third wiring pattern  605  may include a conductive material. 
     The connecting via  680  may be disposed on the sidewalls of the first semiconductor chip  140 . The connecting via  680  may penetrate the first mold layer  170 , the first solder resist layer  120 , and the first redistribution layer  110  in the vertical direction DR 2 . The connecting via  680  may be electrically directly connected between the first wiring pattern  105  and the third wiring pattern  605 . The substrate  100  and the interposer  600  may be electrically connected directly through the connecting via  680 . The connecting via  680  may include a conductive material. 
     The second redistribution layer  610  may be disposed on an upper surface  600   a  of the interposer  600 . The second redistribution layer  610  may include a second wiring pad  611 , a second metal seed layer  612 , a second wiring post  613 , a fourth wiring pattern  614 , and a second interlayer insulating film  615 . The second redistribution layer  610  may have a structure similar to that of the first redistribution layer  110 . 
     For example, the second wiring pad  611  may be disposed on the upper surface  600   a  of the interposer  600 . The second wiring pad  611  may be in contact with the third wiring pattern  605 . The first recess R 1  may be formed inside the first wiring pad  111 . The third recess R 3  may be recessed from an upper surface  611   a  of the second wiring pad  611  toward the upper surface  600   a  of the interposer  600 . A bottom surface of the third recess R 3  may be formed inside the second wiring pad  611 . 
     The second metal seed layer  612  may be disposed along both sidewalls and the bottom surface of the third recess R 3 . The second wiring post  613  may be disposed on the second metal seed layer  612 . At least a part of the second wiring post  613  may be disposed inside the third recess R 3 . The second wiring post  613  may extend in the vertical direction DR 2 . The second wiring post  613  may be in contact with the second metal seed layer  612  inside the third recess R 3 . 
     An upper surface of the second wiring post  613  may be formed to be higher than the upper surface  611   a  of the second wiring pad  611 . The upper surface of the second wiring post  613  may be formed to be lower than the upper surface of the second redistribution layer  610 . The upper surface of the second wiring post  613  may be formed to be lower than the lower surface of the second solder resist layer  620 . 
     A width of the second wiring post  613  in the horizontal direction DR 1  may be smaller than a width of the second wiring pad  611  in the horizontal direction DR 1 . The width of the second wiring post  613  in the horizontal direction DR 1  may be smaller than the width of the third recess R 3  in the horizontal direction DR 1 . 
     Each of the second wiring pad  611 , the second metal seed layer  612 , and the second wiring post  613  may include, for example, copper (Cu). In embodiments, each of the second wiring pad  611 , the second metal seed layer  612 , and the second wiring post  613  may include, for example, at least one of tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), and combinations thereof. 
     For example, the second wiring pad  611 , the second metal seed layer  612 , and the second wiring post  613  may each include the same material. For example, each of the second wiring pad  611 , the second metal seed layer  612 , and the second wiring post  613  may include copper (Cu). In this case, copper (Cu) included in the second metal seed layer  612  may have a finer structure than that of copper (Cu) included in each of the second wiring pad  611  and the second wiring post  613 . 
     The fourth wiring pattern  614  may be disposed on the upper surface of the second wiring post  613 . The fourth wiring pattern  614  may include a plurality of wirings spaced apart from each other in the horizontal direction DR 1 . Further, the fourth wiring pattern  614  may include a plurality of wirings spaced apart from each other in the vertical direction DR 2 . The fourth wiring pattern  614  may include a conductive material. The second interlayer insulating film  615  may be disposed on the upper surface  600   a  of the interposer  600 . The second interlayer insulating film  615  may surround the second wiring pad  611 , the second metal seed layer  612 , the second wiring post  613 , and the fourth wiring pattern  614 . The second interlayer insulating film  615  may include an insulating material. 
     The second solder resist layer  620  may be disposed on the upper surface of the second redistribution layer  610 . The second solder resist layer  620  may include, for example, photo solder resist (PSR) ink. The fourth recess R 4  may be formed inside the second solder resist layer  620 . The second conductive terminal  630  may be disposed along the sidewalls and a bottom surface of the fourth recess R 4 . Further, at least a part of the second conductive terminal  630  may also be disposed on the upper surface of the second solder resist layer  620  that is adjacent to both sidewalls of the fourth recess R 4 . The second conductive terminal  630  may include a conductive material. 
     The third solder ball  653  may be disposed on the second conductive terminal  630 . The second semiconductor chip  640  may be disposed on the upper surface of the second solder resist layer  620 . The second semiconductor chip  640  may be electrically directly connected to the second redistribution layer  610  through the third solder ball  653 . The second underfill material  660  may surround the sidewalls of the third solder ball  653  between the upper surface of the second solder resist layer  620  and the second semiconductor chip  640 . The second mold layer  670  may surround the sidewalls of the second underfill material  660 , and the sidewalls and the upper surface of the second semiconductor chip  640 , on the upper surface of the second solder resist layer  620 . 
     While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.