Patent Publication Number: US-2019190505-A1

Title: Delay control circuits

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0174953, filed on Dec. 19, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein. 
     BACKGROUND 
     1. Field 
     Example embodiments provided herein relate to a delay control circuit, and more specifically, to a delay control circuit in which sensitivity to process, voltage and temperature (PVT) variation is low and a duty ratio is maintained. 
     2. Description of the Related Art 
     Precision of a clock is very important in many fields of digital systems. Especially, a clock received from the outside and an internal clock need to be synchronized. Also, the performance of the digital system may be influenced by how accurately the duty ratio is controlled. However, since a quantization error occurs due to the characteristics of the digital system, an improvement in accuracy of the clock becomes increasingly difficult. 
     A delay line may be used to synchronize the clock received from the outside and the internal clock. The clock received from the outside passes through the delay line and has a predetermined delay time. The delay line may change a driving strength or change a an output capacitance seen by a driving stage to generate the delay time. Specifically, the delay time may be adjusted by changing the slope of the signal passing through the delay line. 
     However, when a PVT variation occurs due to an external factor, a delay error may be produced by the delay line circuit. As a delay time generated by the delay line becomes longer, the delay error may increase exponentially. Additionally, when the signal passes through the delay line at a skewed corner, the duty ratio may change. A skewed corner, in some technologies, is associated with NMOS and PMOS devices which are coupled in a circuit. 
     SUMMARY 
     One or more example embodiments provide a delay control circuit having low sensitivity to PVT variation. 
     Further, one or more example embodiments provide a delay control circuit in which a duty ratio of a signal is maintained before and after passing through the delay control circuit. 
     According to an aspect of an example embodiment, there is provided a delay control circuit including: a first step delay cell including a first switch having a first end connected to a first node, and a first capacitor connected to a second end of the first switch; a second step delay cell including a second switch having a first end connected to a second node, and a second capacitor connected to a second end of the second switch; and an inverter configured to couple an output signal of the first step delay cell to an input of the second step delay cell, wherein the first and the second switches are turned on and off by a control signal. 
     According to an aspect of another example embodiment, there is provided a delay control circuit including a first step delay cell which is configured to receive a first signal and includes a first node; a second step delay cell which is configured to provide a second signal and includes a second node; a control signal input configured to receive a control signal, wherein the control signal input is coupled to the first step delay cell and to the second step delay cell; and a first inverter which is configured to receive a third signal from the first step delay cell and to output a fourth signal to the second step delay cell, wherein when the first signal is enabled and the control signal indicates a minimum delay value, a first voltage level of the first node decreases with a first slope, and a second voltage level of the second node increases with a second slope. 
     According to an aspect of an example embodiment, there is provided a delay control circuit configured to receive a first signal as an input and to delay the first signal, the delay control circuit including: k step delay cells including first and second step delay cells, wherein k is an even integer greater than zero; a first inverter disposed between the first step delay cell and the second step delay cell; and a second inverter coupled to an output of the second step delay cell, wherein the first step delay cell is configured to provide a second signal in response to the first signal, the first inverter is configured to provide a third signal in response to the second signal, the second step delay cell is configured to provide a fourth signal in response to the third signal, the second inverter is configured to provide a fifth signal in response to the fourth signal, a second duty ratio of the second signal is greater than a first duty ratio of the first signal, a third duty ratio of the fifth signal is less than the second duty ratio, and the third duty ratio approximately matches the first duty ratio. 
     The aspects of the present inventive concept are not limited to those mentioned above and another aspect which is not mentioned can be clearly understood by those skilled in the art from the description below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and/or other aspects will become apparent and more readily appreciated from the following description of exemplary embodiments, taken in conjunction with the accompanying drawings in which: 
         FIGS. 1A and 1B  are example circuit diagrams for explaining a step delay cell; 
         FIG. 2  is an example timing diagram for explaining the voltage for each node of the step delay cell when a power supply noise is relatively small; 
         FIG. 3  is an example timing diagram for explaining the voltage for each node of the step delay cell when the power supply noise is relatively large; 
         FIG. 4  is a graph illustrating the magnitude of the delay error to an average value of a slope of a second signal P 2 ; 
         FIGS. 5 and 6  are example circuit diagrams for describing a delay control circuit according to some embodiments; 
         FIG. 7  is an example circuit diagram for describing the configuration of the delay control circuit according to some embodiments; 
         FIGS. 8A and 8B  are example circuit diagrams for explaining capacitors and switches of the delay control circuit according to some embodiments; 
         FIGS. 9A, 9B, and 9C  are example timing diagrams for explaining the voltage for each node of the delay control circuit according to some embodiments; 
         FIGS. 10A and 10B  are example tables for describing the code of the control signal according to some embodiments; 
         FIG. 11  is an example diagram for explaining occurrence of a duty error at a skewed corner; 
         FIG. 12A  is an example view for illustrating a change in the duty ratio of the signal having passed through the delay control circuit according to some embodiments at the SF corner (slow-fast corner); 
         FIG. 12B  is an example view for illustrating a change in duty ratio of the signal having passed through the delay control circuit according to some embodiments at the FS corner (fast-slow corner); and 
         FIG. 13  is an example block diagram illustrating the structure of the memory which utilizes the delay control circuit according to some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 1A and 1B  are example circuit diagrams for explaining a step delay cell.  FIG. 2  is an example timing diagram for explaining the voltage for each node of the step delay cell when a power supply noise is relatively small.  FIG. 3  is an example timing diagram for explaining the voltage for each node of the step delay cell when the power supply noise is relatively large.  FIG. 4  is a graph illustrating the magnitude of the delay error to an average value of a slope of a second signal P 2 . 
     Referring to  FIGS. 1A and 1B , a step delay cell  100  may include an input inverter  110 , an output inverter  120 , and a variable capacitor CC. 
     An input stage of the input inverter  110  may be connected to an input node I. An output stage of the input inverter  110  may be connected to a delay node S. An input stage of the output inverter  120  may be connected to the delay node S. An output stage of the output inverter  120  may be connected to an output node O. 
     The input inverter  110  may invert a first signal P 1  provided to the input node I. The input inverter  110  may invert the first signal P 1  and provide the first signal P 1  to the delay node S in the form of a second signal P 2 . The output inverter  120  receives the second signal P 2 , inverts the second signal P 2 , and may provide the inverted second signal P 2  to the output node O in the form of a third signal P 3 . 
     One end of the variable capacitor CC may be connected to the delay node S. The other end of the variable capacitor CC, for example, may be grounded. The capacitance of the variable capacitor CC may be controlled by a control signal STR. STR generally represents a control signal which may be a scalar or a vector. That is, STR may be composed of a single binary signal or may be composed of two or more constituent control signals. 
     As illustrated in  FIG. 1A , in some embodiments, the variable capacitor CC may include switches SW 1  and SW 2 , and two capacitors C, connected to the switches SW 1  and SW 2 . A control signal STR[ 1 : 0 ] may control turning on/off of the switches SW 1  and SW 2 . Depending on the switch positions, each of the capacitors C may be coupled to or decoupled from the delay node S, in accordance with the turning on/off of the switches SW 1  and SW 2 . In other words, the control signal STR[ 1 : 0 ] may control the switches SW 1  and SW 2  to adjust the capacitance of the variable capacitor CC. For example, if both switches SW 1  and SW 2  are turned off, the capacitance of the variable capacitor CC may be zero. For example, if one of the switches SW 1  and SW 2 ) is turned on and the other one is turned off, the capacitance of the variable capacitor CC may be the capacitance of C. On the other hand, if both switches SW 1  and SW 2  are turned on, the capacitance of the variable capacitor CC may be twice the capacitance of C. Therefore, the control signal STR[ 1 : 0 ] may control the capacitance of the variable capacitor CC by controlling the turning on/off of the switches SW 1  and SW 2 . 
     Throughout the disclosure, coupling or connecting a capacitor to a node internal to a step delay cell may be referred to as “shorting” (closing the switch, the switch is on) and decoupling or disconnecting the capacitor from the node may be referred to as “open” (the switch is open, cut, or off). 
     Although  FIG. 1A  illustrates a configuration in which the variable capacitor CC includes two switches SW 1  and SW 2  and two capacitors C, the embodiments provided herein are not limited thereto. For example, the variable capacitor CC may include a plurality of capacitors, and a plurality of switches capable of adjusting short/opening thereof. 
     As illustrated in  FIG. 1B , in some embodiments, the control signal STR may adjust the distance between pole plates of the variable capacitor CC. For example, when the distance between the pole plates of the variable capacitor CC increases by the control signal STR, the capacitance of the variable capacitor CC may be reduced. For example, when the distance between the pole plates of the variable capacitor CC decreases by the control signal STR, the capacitance of the variable capacitor CC may increase. 
     Those having ordinary skill in the technical field of this disclosure may achieve a variable capacitor CC in which capacitance is adjusted by the control signal STR in various ways. Hereinafter, for the convenience of explanation, a case where the variable capacitor CC includes a switch, and a capacitor connected to the switch will be described. 
       FIGS. 1A, 1B, 2, and 3  illustrate a case where the control signal STR has a low value or a high value. In some embodiments, the low value is expressed as 0 (logic low level), and the high value is expressed as 1 (logic high level) for convenience of explanation. 
     In some example embodiments, the inverted first signal P 1 , and the second signal P 2  may be the same or different from each other. 
     For example, when the control signal STR is 0 in  FIGS. 1A, 1B and 3 , the capacitor C and the delay node S may be opened. The value STR=0 may be said to indicate a minimum delay value. In other words, when the control signal STR is 0, the switch SW connected to the capacitor C is opened, and the connection between the capacitor C and the delay node S may be cut. At this time, the inverted first signal P 1 , and the second signal P 2  may be the same. 
     For example, when the control signal STR is 1, the capacitor C and the delay node S may be short. In other words, when the control signal STR is 1, the switch SW connected to the capacitor C is short, and the capacitor C and the delay node S may be connected to each other. At this time, the capacitor C may be charged with the inverted first signal P 1 . Also, because the capacitor C provides a capacitive load at the delay node S, the capacitor C will tend to charge or discharge depending on the state of the output connected to C. In such a case, the inverted first signal P 1 , and the second signal P 2  may be different from each other while the capacitor C is charging or discharging. 
     Specifically, when the voltage level of the inverted first signal P 1  increases, the capacitor C may be charged with the inverted first signal P 1 . Since the capacitor C is charged with the inverted first signal P 1 , the voltage level of the inverted first signal P 1  may ramp up more slowly than the case where the capacitor C and the delay node S are opened (decoupled). In a simplified scenario, the capacitor C integrates the current from an inverter output. For a constant current, the resulting integral of the constant current is a ramp voltage function. 
     Further, when the voltage level of the inverted first signal P 1  decreases, the capacitor C may discharge the charged electric charge to the delay node S. Since the electric charge is discharged from the capacitor C to the delay node S, the voltage level of the inverted first signal P 1  may ramp down more slowly than the case where the capacitor C and the delay node S are opened (decoupled). 
     That is, the capacitor C may control the increasing and decreasing speed of the voltage level of the first signal P 1  inverted through charging and discharging. Therefore, the control signal STR may control the opening/short (coupling/decoupling) of the capacitor C to control the increasing and decreasing speed of the voltage level of the inverted first signal P 1 . That is, since the control signal STR may control the increasing and decreasing slope of the inverted first signal P 1  provided to the delay node S, it is possible to delay the increasing and decreasing speed of the inverted first signal P 1 . Therefore, the second signal P 2  is a signal may be the inverted first signal P 1  (without slope controlled) or may be a signal in which the slope of the inverted first signal P 1  is controlled. 
     To facilitate the description and to aid in the understanding of the technical idea of the example embodiments provided herein, some characteristics of an inverter to be described below will be assumed. First, in the delay control circuit according to some example embodiments, a propagation delay may occur when the signal passes through the inverter. However, it is assumed that the propagation delay is much smaller than the delay due to the capacitor. Even though the propagation delay is illustrated in the drawings to be large enough to compare with the delay due to the capacitor, this is for ease of explanation, and the examples are not limited to the illustrated matters 
     In addition, the inverter according to some embodiments is assumed to have a threshold voltage of ½ point of the maximum voltage of the input and the minimum voltage of the input. The case where the input voltage is 0V to 10V will be described as an example. When the input of the inverter is less than 5V, the output of the inverter may be enabled. When the input of the inverter is 5V or more, the output of the inverter may be disabled. However, the embodiments are not limited to some characteristics of the inverter. Such an assumption is for facilitating the explanation and for helping understanding of those having ordinary skill in the technical field of the disclosure provided herein. The inverter achieved according to some embodiments may also have different characteristics. For example, the threshold voltage of an inverter may be higher or lower than a half of the maximum value of the input and the minimum value of the input of the inverter. 
     Referring to  FIG. 2 ,  FIG. 2  is a diagram illustrating a case where the noise of the power supply voltage VDD is relatively small. That is,  FIG. 2  is a diagram illustrating a state in which the power supply voltage VDD is stably supplied. 
     First, the case where the control signal STR is 0, that is, the case where the capacitor C and the delay node S are opened (decoupled from each other) will be described. The first signal P 1  may be provided to the input node I. The first signal P 1  may be provided to the input stage of the input inverter  110 . The input inverter  110  may invert the first signal P 1  and provide it to the delay node S as the second signal P 2 . The voltage level of the first signal P 1  may start to rise at time t 1 . 
     The second signal P 2  may be provided to the delay node S. The voltage level of the second signal P 2  may start to fall at time t 2 . The time t 2  may be the time subsequent to the time t 1  as illustrated in the drawings. That is, the falling time of the voltage level of the second signal P 2  may be later than the rising time of the voltage level of the first signal P 1 . The time t 2  may be subsequent to the time t 1  due to the propagation delay of the input inverter  110 . The second signal P 2  may be reduced from the time t 2  at the first slope g 1 . 
     If the output inverter  120  inverts the second signal P 2  and provides it to the output node O, a third signal P 3  may be provided to the output node O. The voltage level of the third signal P 3  may start to rise at time t 3 . The time t 3  may be a time subsequent to the time t 2 . That is, the rising time of the voltage level of the third signal P 3  may be later than the falling time of the voltage level of the second signal P 2 . The time t 3  may be subsequent to the time t 2  due to the propagation delay of the output inverter  120 . 
     At the input node I, the initial rising time of the voltage level of the first signal P 1  may be t 1  (an upward ramp transition begins). On the other hand, at the output node O, the initial rising time of the voltage level of the third signal P 3  may be t 3 . When the control signal STR is 0, the total delay time may be t 3 -t 1 . Since the capacitor C is opened to (decoupled from) the delay node S when the control signal STR is 0, the total delay time may be caused by the input inverter  110  and the output inverter  120 . That is, the propagation delay time tS 1  due to the input inverter  110  and the output inverter  120  may be t 3 -t 1 . 
     Next, the case where the control signal STR is 1, that is, the case where the capacitor C and the delay node S are short (coupled) will be described. The first signal P 1  may be provided to the input node I. The first signal P 1  may be provided to the input stage of the input inverter  110 . The input inverter  110  may invert the first signal P 1  and provide it to the delay node S. The voltage level of the first signal P 1  may start to rise at the time t 1 . 
     The second signal P 2  may be provided to the delay node S. The voltage level of the second signal P 2  may start to fall at the time t 2 . The time t 2  may be the time subsequent to the time t 1  as illustrated in the drawings. That is, the initial falling time of the voltage level of the second signal P 2  may occur at a time later than the initial increasing time of the voltage level of the first signal P 1 . The time t 2  may be subsequent to the time t 1  due to the propagation delay of the input inverter  110 . 
     The second signal P 2  may be reduced at the time t 2  with the second slope g 2 . The absolute value of the second slope g 2  may be smaller than the absolute value of the first slope g 1 . That is, the falling speed of the second signal P 2  when the control signal STR is 1 may be smaller than the falling speed of the second signal P 2  when the control signal STR is 0. In other words, when the control signal STR is 1, the second signal P 2  may ramp down at a slower rate than the case where the control signal STR is 0. 
     If the output inverter  120  inverts the second signal P 2  and provides it to the output node O, the third signal P 3  may be provided to the output node O. The voltage level of the third signal P 3  may start to rise at the time t 4 . The time t 4  may be subsequent to the time t 3 . The initial rising time of the voltage level of the third signal P 3  when the control signal STR is 1 may be later than the initial rising time of the voltage level of the third signal P 3  when the control signal STR is 0. The time t 4  may be subsequent to the instant t 3  because the charge charged in the capacitor C is discharged to the delay node S. 
     At the input node I, the initial increasing time of the voltage level of the first signal P 1  may be t 1 . On the other hand, at the output node O, the initial increasing time of the voltage level of the third signal P 3  may be t 4 . When the control signal STR is 1, the total delay time (tS 1 +ΔS 1 ) may be t 4 -t 1 . As described above, the propagation delay time tS 1  due to the input inverter  110  and the output inverter  120  may be t 3 -t 1 . Therefore, the delay time ΔS 1  due to the capacitor C may be t 4 -t 3 . 
     In  FIG. 2 , the propagation delay time tS 1  is illustrated to be large enough to compare with the delay time ΔS 1 , but in actual implementation, the propagation delay time tS 1  may be much smaller than the delay time ΔS 1 . That is, the propagation delay time tS 1  may be a negligibly small value. 
     Referring to  FIG. 3 ,  FIG. 3  is a diagram illustrating a case where the noise of the power supply voltage VDD is relatively large. That is,  FIG. 3  is a diagram illustrating a state in which the power supply voltage VDD is not stably supplied; the voltage is not a simple clean constant. For the sake of convenience of explanation, repeated or same description of the contents described above will be omitted or briefly explained. 
     When the power supply voltage VDD is unstable, the total delay time may become uncertain (delay uncertainty). That is, when the power supply voltage VDD is unstable, the slope of the second signal P 2  of the delay node S may be varied (slope variation). When the slope of the second signal P 2  of the delay node S is varied, the initial rising time of the third signal P 3  of the output node O may be varied. That is, the third signal P 3  may have a delay error. The error may be positive or negative and of uncertain magnitude. 
     The delay error ΔE 1  generated when the control signal STR is 0 may be smaller than the delay error ΔE 2  generated when the control signal STR is 1. In other words, the delay error ΔE 1  when the second signal P 2  decreases according to a first slope g 1  may be smaller than the delay time ΔE 2  when the second signal P 2  decreases according to a second slope g 2 . Refer to  FIG. 4 . 
     As illustrated in the graph  400  of  FIG. 4 , the x-axis is the magnitude of the delay time ΔS and the y-axis is the magnitude of the delay error ΔE. As the delay time ΔS increases, the delay error ΔE may increase exponentially. An exponential function has the form f(x)=a x . 
     In conclusion, as the delay time ΔS increases, that is, as the absolute value of the slope of the second signal P 2  is small, the delay error due to the fluctuation of the power supply voltage VDD may be relatively large. That is, as the absolute value of the slope of the second signal P 2  is small, the delay error may be greatly influenced by external factors. 
     Although  FIG. 3  illustrates that a delay error occurs in accordance with the voltage variation, the embodiments are not limited thereto. For example, the delay error may be generated in accordance with PVT variation (Process, Voltage, and Temperature variation). Generally, PVI variation refers to a process by which a chip is manufactured, a voltage under which it is operating and a temperature under which it is operating. 
       FIGS. 5 and 6  are circuit diagrams for describing a delay control circuit according to some example embodiments. 
     Referring to  FIG. 5 , a delay control circuit  500  according to some embodiments may include k step delay cells (VBUF 1  to VBUFk) and k inverters (INTb 1  to INTbk). Here, k may be an integer greater than 1 in some embodiments. In some other embodiments, k may be an even number greater than 1. 
     The outputs of the k step delay cells (VBUF 1  to VBUFk) may be connected to the inputs of the k inverters (INTb 1  to INTbk), respectively. For example, the output of the first step delay cell VBUF 1  may be connected to the input of the first inverter INTb 1 . The output stage of the first inverter INTb 1  may be connected to the input of the second step delay cell VBUF 2 . 
     The same n control signals (STR[n- 1 : 0 ]) may be provided to each of the k step delay cells (VBUF 1  to VBUFk). For example, n control signals (STR[n- 1 ] to STR[ 0 ]) may be provided to the first step delay cell VBUF 1 . Also, the same n control signals (STR[n- 1 ] to STR[ 0 ]) may be provided to the second step delay cell VBUF 2 . 
       FIG. 6  illustrates a case where k=2 and n=3 in the delay control circuit  500  of  FIG. 5 . For convenience of explanation, in some embodiments, the case where the delay control circuit  500  has k=2 and n=3, that is, the delay control circuit is the delay control circuit  600  of  FIG. 6  is illustrated, but the embodiments are not limited thereto. 
     Referring to  FIG. 6 , the delay control circuit  600  according to some example embodiments may include first and second step delay cells VBUF 1  and VBUF 2  and first and second inverters INTb 1  and INTb 2 . 
     First and second control signals STR[ 2 : 0 ] may be provided to the first and second step delay cells VBUF 1  and VBUF 2 , respectively. In other words, the first, second, and third control signals STR[ 2 ], STR[ 1 ], and STR[ 0 ] may be provided to the first step delay cell VBUF 1 . Further, the first, second, and third control signals STR[ 2 ], STR[ 1 ], and STR[ 0 ] may be provided to the second step delay cell VBUF 2 . 
     In  FIGS. 6 to 10B , each of the control signals STR[ 2 ], STR[ 1 ], and STR[ 0 ] may have low or high value. In some embodiments, for convenience of explanation, the low value is expressed as 0 (logic low level) and the high value is expressed as 1 (logic high level). For example, when the first control signal STR[ 2 ] is high, the second control signal STR[ 1 ] is low, and the third control signal STR[ 0 ] is low, the control signal may be expressed as [100]. 
     The input stage of the first step delay cell VBUF 1  may be connected to the first input node IN. The output stage of the first step delay cell VBUF 1  may be connected to the first output node O 1 . The input stage of the first inverter INTb 1  may be connected to the first output node O 1 . The output stage of the first inverter INTb 1  may be connected to the second input node I 1 . The input stage of the second step delay cell VBUF 2  may be connected to the second input node I 1 . The output stage of the second step delay cell VBUF 2  may be connected to the second output node O 2 . The input stage of the second inverter INTb 2  may be connected to the second output node O 2 . The output stage of the second inverter INTb 2  may be connected to the third output node OUT. The description will be made in more detail referring to  FIG. 7 . 
       FIG. 7  is a circuit diagram for describing the configuration of the delay control circuit according to some example embodiments. 
     Referring to  FIG. 7 , the first step delay cell VBUF 1  may include a third inverter INT 1 , a fourth inverter INT 2 , first, second, and third switches S 1 , S 2 , and S 3 , and first, second, and third capacitors C 1 , C 2 , and C 3 ). 
     The input stage of the third inverter INT 1  may be connected to the first input node IN. The output stage of the third inverter INT 1  may be connected to the first node N 1 . One end of the first switch S 1  may be connected to the first node N 1 . The other end of the first switch S 1  may be connected to one end of the first capacitor C 1 . The other end of the first capacitor C 1 , for example, may be grounded. One end of the second switch S 2  may be connected to the first node N 1 . The other end of the second switch S 2  may be connected to one end of the second capacitor C 2 . The other end of the second capacitor C 2 , for example, may be grounded. One end of the third switch S 3  may be connected to the first node N 1 . The other end of the third switch S 3  may be connected to one end of the third capacitor C 3 . The other end of the third capacitor C 3 , for example, may be grounded. The input stage of the fourth inverter INT 2  may be connected to the first node N 1 . The output stage of the fourth inverter INT 2  may be connected to the first output node O 1 . 
     The first, second, and third control signals STR[ 2 ], STR[ 1 ], and STR[ 0 ] may control turning on-off of the first, second, and third switches S  1 , S 2 , and S 3 , respectively. For example, if the first control signal STR[ 2 ] is 1, the first switch S 1  may be turned on. If the first switch S 1  is turned on, the first capacitor C 1  and the first node N 1  may be short (coupled). If the first control signal STR[ 2 ] is 0, the first switch S 1  may be turned off. If the first switch S 1  is turned off, the first capacitor C 1  and the first node N 1  may be opened (decoupled). 
     The second step delay cell VBUF 2  may include a fifth inverter INT 3 , a sixth inverter INT 4 , fourth, fifth, and sixth switches S 4 , S 5 , and S 6 , and fourth, fifth, and sixth capacitors C 4 , C 5 , and to C 6 . 
     The input stage of the fifth inverter INT 3  may be connected to the second input node I 1 . The output stage of the fifth inverter INT 3  may be connected to the second node N 2 . One end of the fourth switch S 4  may be connected to the second node N 2 . The other end of the fourth switch S 4  may be connected to one end of the fourth capacitor C 4 . The other end of the fourth capacitor C 4 , for example, may be grounded. One end of the fifth switch S 5  may be connected to the second node N 2 . The other end of the fifth switch S 5  may be connected to one end of the fifth capacitor C 5 . The other end of the fifth capacitor C 5 , for example, may be grounded. One end of the sixth switch S 6  may be connected to the second node N 2 . The other end of the sixth switch S 6  may be connected to one end of the sixth capacitor C 6 . The other end of the sixth capacitor C 6 , for example, may be grounded. The input stage of the sixth inverter INT 4  may be connected to the second node N 2 . The output stage of the sixth inverter INT 4  may be connected to the second output node O 2 . 
     The first, second, and third control signals STR[ 2 ], STR[ 1 ], and STR[ 0 ] may control the turning on-off of the fourth, fifth, and sixth switches S 4 , S 5 , and S 6 , respectively. In other words, the first control signal STR[ 2 ] may control the turning on/off of the first and fourth switches S 1  and S 4 . The second control signal STR[ 1 ] may control the turning on/off of the second and fifth switches S 2  and S 5 . The third control signal (STR[ 0 ]) may control the turning on/off of the third and sixth switches S 3  and S 6 . For example, if the first control signal STR[ 2 ] is 1, the first and fourth switches S 1  and S 4  may be turned on. If the first control signal STR[ 2 ] is 0, the first and fourth switches S 1  and S 4  may be turned off. 
     The capacitance of the first capacitor C 1  and the capacitance of the fourth capacitor C 4  may be the same. The capacitance of the second capacitor C 2  and the capacitance of the fifth capacitor C 5  may be the same. The capacitance of the third capacitor C 3  and the capacitance of the sixth capacitor C 6  may be the same. 
       FIGS. 8A and 8B  are example circuit diagrams for explaining capacitors and switches of the delay control circuit according to some embodiments. 
     Referring to  FIG. 8A , in some embodiments, the first to sixth switches (S 1  to S 6 ) may be MOS transistors. The first, second, and third control signals STR[ 2 ], STR[ 1 ], and STR[ 0 ] may be provided to the gate of the MOS transistor. Although the first, second, third, fourth, fifth, and sixth switches S 1 , S 2 , S 3 , S 4 , S 5  and S 6  are illustrated as the NMOS transistors in  FIG. 8A , the embodiments provided herein are not limited thereto. For example, the first, second, third, fourth, fifth, and sixth switches S 1 , S 2 , S 3 , S 4 , S 5  and S 6  may be PMOS transistors. Alternatively, for example, the first, second, third, fourth, fifth, and sixth switches S 1 , S 2 , S 3 , S 4 , S 5  and S 6  may be a combination of an NMOS transistor and a PMOS transistor. 
     Referring to  FIG. 8B , in some embodiments, the first, second, third, fourth, fifth, and sixth switches S 1 , S 2 , S 3 , S 4 , S 5  and S 6  may be transmission gates. Also, in some embodiments, the first, second, third, fourth, fifth, and sixth capacitors C 1 , C 2 , C 3 , C 4 , C 5 , and C 6  may be MOS capacitors. 
     Although  FIGS. 8A and 8B  describe examples of switches and capacitors of the delay control circuit according to some embodiments, the embodiments provided herein are not limited thereto. For example, the delay control circuit according to some embodiments may be achieved by the combination of  FIGS. 8A and 8B . Those having ordinary skill in the technical field of this disclosure will be able to implement switches and capacitors in various ways. 
       FIGS. 9A, 9B, and 9C  are example timing diagrams for explaining the voltage for each node of the delay control circuit according to some embodiments. 
     For convenience of explanation, the signals provided to each node illustrated in  FIGS. 7, 8A and 8B  are defined. The signal of the first input node IN is defined as a fourth signal P 4 . The signal of the first node N 1  is defined as a fifth signal P 5 . The signal of the first output node O 1  is defined as a sixth signal P 6 . The signal of the second input node I 1  is defined as a seventh signal P 7 . The signal of the second node N 2  is defined as an eighth signal P 8 . The signal of the second output node O 2  is defined as a ninth signal P 9 . The signal of the third output node OUT is defined as a tenth signal P 10 . 
       FIG. 9A  is a diagram illustrating the voltage level for each node when the control signal STR[ 2 : 0 ] is [000], that is, when the values of the first, second, and third control signals STR[ 2 ], STR[ 1 ], and STR[ 0 ] are 0, respectively. The value [000] may be said to indicate a minimum delay value. That is to say, the timing chart of  FIG. 9A  illustrates the change in the voltage level of each node when the first to sixth switches S 1 , S 2 , S 3 , S 4 , S 5  and S 6  are opened. 
     The fourth signal P 4  may be provided to the first input node IN. The fourth signal P 4  may be provided to the input stage of the third inverter INT 1 . The voltage level of the fourth signal P 4  may start to rise from the time T 1 . The third inverter INT 1  may invert the fourth signal P 4  and provide it to the first node N 1 . 
     The fifth signal P 5  may be provided to the first node N 1 . The voltage level of the fifth signal P 5  may start to fall at the time T 2 . The falling time of the voltage level of the fifth signal P 5  may be later than the increasing time of the voltage level of the fourth signal P 4 . Time T 2  may be subsequent to the time T 1  due to the propagation delay of the third inverter INT 1 . The voltage level of the fifth signal P 5  may be reduced from the time T 2  according to a third slope g 3 . 
     The fourth inverter INT 2  may invert the fifth signal P 5  and provide it to the first output node O 1 , resulting in the sixth signal P 6 . The voltage level of the sixth signal P 6  may start to rise at time T 3 . The rising time of the voltage level of the sixth signal P 6  may be later than the falling time of the voltage level of the fifth signal P 5 . Time T 3  may be subsequent to the time T 2  due to the propagation delay of the fourth inverter INT 2 . 
     The first inverter INTb 1  may invert the sixth signal P 6  and provide it to the second input node I 1  resulting in the seventh signal P 7 . The voltage level of the seventh signal P 7  may start to fall at time T 4 . The time t 4  may be a time subsequent to the time t 3 . That is, the falling time of the voltage level of the seventh signal P 7  may be later than the rising time of the voltage level of the sixth signal P 6 . The time T 4  may be subsequent to the time T 3 , due to the propagation delay of the first inverter INTb 1 . 
     The eighth signal P 8  may be provided to the second node N 2 . The voltage level of the eighth signal P 8  may start to rise at time T 5  due to the signal P 7 . The rising time of the voltage level of the eighth signal P 8  may be later than the falling time of the voltage level of the seventh signal P 7 . Time T 5  may be subsequent to the time T 4  due to the propagation delay of the fifth inverter INT 3 . The voltage level of the eighth signal P 8  may increase from the time T 5  according to a fourth slope g 4 . The absolute value of the third slope g 3  and the absolute value of the fourth slope g 4  may be the same. For example, the third slope g 3  and the fourth slope g 4  may have values with the same magnitude but with different signs. 
     The ninth signal P 9  may be provided to the second output node O 2  in response to the signal P 8 . The voltage level of the ninth signal P 9  may start to fall at time T 6 . The falling time of the voltage level of the ninth signal P 9  may be later than the rising time of the voltage level of the eighth signal P 8 . Time T 6  may be subsequent to the time T 5  due to the propagation delay of the sixth inverter INT 4 . 
     The tenth signal P 10  may be provided to the third output node OUT in response to the signal P 9 . The voltage level of the tenth signal P 10  may start to rise at time T 7 . The time T 7  may be the time subsequent to the time T 6 . That is, the rising time of the voltage level of the tenth signal P 10  may be later than the falling time of the voltage level of the ninth signal P 9 . Time T 7  may be subsequent to the time T 6  due to the propagation delay of the second inverter INTb 2 . 
     At the first input node IN, the increasing time of the voltage level of the fourth signal P 4  may be T 1 . On the other hand, at the third output node OUT, the rising time of the voltage level of the tenth signal P 10  may be T 7 . When the control signal STR[ 2 : 0 ] is [000], the total delay time may be T 7 -T 1 . That is, the propagation delay time tS due to the first, second, third, fourth, fifth, and sixth inverters INTb 1 , INTb 2 , INT 1 , INT 2 , INT 3 , and INT 4  may be T 7 -T 1 . 
     The case where the control signal STR[ 2 : 0 ] is [001] will be described referring to  FIG. 9B . For the sake of convenience of explanation, the repeated or same contents will be omitted or briefly explained. 
     When STR=[001] and a signal at the input terminal IN is enabled, the fifth signal P 5  may ramp down according to a fifth slope g 5 . The absolute value of the fifth slope g 5  may be smaller than the absolute value of the third slope g 3 . That is, the falling speed of the fifth signal P 5  when the control signal STR[ 2 : 0 ] is [001] may be smaller than the falling speed of the fifth signal P 5  when the control signal STR[ 2 : 0 ] is [000]. In other words, when the control signal STR[ 2 : 0 ] is [001] (an example indicating a non-minimum delay value, because some additional capacitive load is added), the fifth signal P 5  may decay at a slower rate when the control signal STR[ 2 : 0 ] is [000] (indicating a minimum delay value because no additional capacitive load is added). 
     The eighth signal P 8  may ramp up with a sixth slope g 6 . The absolute value of the sixth slope g 6  may be smaller than the absolute value of the fourth slope g 4 . That is, the rising speed of the eighth signal P 8  when the control signal STR[ 2 : 0 ] is [001] may be smaller than the rising speed of the eighth signal P 8  when the control signal STR[ 2 : 0 ] is [000]. In other words, when the control signal STR[ 2 : 0 ] is [001], the eighth signal P 8  may ramp up more slowly than when the control signal STR[ 2 : 0  is [000]. 
     The absolute value of the fifth slope g 5  and the absolute value of the sixth slope g 6  may be the same. That is, the fifth slope g 5  and the sixth slope g 6  may have values with the same magnitude but with different signs. 
     At the first input node IN, the initial start time of the voltage level ramp up of the first signal P 1  may be T 1 . On the other hand, at the third output node OUT, the initial start time of the voltage level ramp of the tenth signal P 10  may be T 8 . When the control signal STR[ 2 : 0 ] is [001], the total delay time (tS+ΔS 2 ) may be T 8 -T 1 . As described above, the propagation delay time tS due to the first, second, third, fourth, fifth, and sixth inverters INTb 1 , INTb 2 , INT 1 , INT 2 , INT 3 , and INT 4  may be T 7 -T 1 . Therefore, the delay time ΔS 2  due to the first, second, third, fourth, fifth, and sixth capacitors C 1 , C 2 , C 3 , C 4 , C 5 , and C 6  may be T 8 -T 7 . 
     The case where the control signal STR[ 2 : 0 ] is [011] will be described referring to  FIG. 9C . For the sake of convenience of explanation, repeated or same contents will be omitted or briefly explained. 
     When the signal at IN transitions to a high value, the fifth signal P 5  may ramp down according to a seventh slope g 7 . The absolute value of the seventh slope g 7  may be smaller than the absolute value of the fifth slope g 5 . That is, the falling speed of the fifth signal P 5  when the control signal STR[ 2 : 0 ] is [011] may be smaller than the falling speed of the fifth signal P 5  when the control signal STR[ 2 : 0 ] is [001]. In other words, when the control signal STR[ 2 : 0 ] is [011], the fifth signal P 5  may ramp down more slowly than when the control signal STR[ 2 : 0 ] is [001]. This is consistent with STR=[011] indicating a greater delay than STR =[001]. 
     The eighth signal P 8  may be increased with the eighth slope g 8 . The absolute value of the eighth slope g 8  may be smaller than the absolute value of the sixth slope g 6 . That is, the rising speed of the eighth signal P 8  when the control signal STR[ 2 : 0 ] is [011] may be smaller than the rising speed of the eighth signal P 8  when the control signal STR[ 2 : 0 ] is [001]. In other words, when the control signal STR[ 2 : 0 ] is [011], the eighth signal P 8  may be increased to be slower than the case where the control signal STR[ 2 : 0 ] is [001]. 
     The absolute value of the seventh slope g 7  and the absolute value of the eighth slope g 8  may be the same. That is, the seventh slope g 7  and the eighth slope g 8  may have values with the same magnitude but with different signs. 
     At the first input node IN, the increasing start time of the voltage level of the first signal P 1  may be T 1 . On the other hand, at the third output node OUT, the increasing start time of the voltage level of the tenth signal P 10  may be T 9 . When the control signal STR[ 2 : 0 ] is [011], the total delay time (tS+ΔS 3 ) may be T 9 -T 1 . As described above, the propagation delay time tS due to the first, second, third, fourth, fifth, and sixth inverters INTb 1 , INTb 2 , INT 1 , INT 2 , INT 3 , and INT 4  may be T 7 -T 1 . Therefore, the delay time ΔS 3  due to the first to sixth capacitors C 1 , C 2 , C 3 , C 4 , C 5 , and C 6  may be T 9 -T 7 . 
     In  FIGS. 9A, 9B and 9C , the propagation delay time tS is illustrated to be large enough to compare with the delay times ΔS 2  and ΔS 3 , but in the actual implementation, the propagation delay time tS may be the value that is much smaller than the delay times ΔS 2  and ΔS 3 . That is, the propagation delay time tS may be negligibly small. 
     The description will be given with reference to  FIGS. 1, 2, and 6 to 9C . In some embodiments, the propagation delay times tS 1  and tS may be much smaller than the delay times ΔS 1 , ΔS 2 , and ΔS 3 . Therefore, it is assumed that the propagation delay times tS 1  and tS are negligible. 
     The delay control circuit ( 500  of  FIG. 5, and 600  of  FIG. 6 ) according to some embodiments may include a plurality of step delay cells  100 , and a plurality of inverters. When a target delay time is ΔS, in some embodiments, each of the k step delay cells VBUF 1  to VBUFk included in the delay control circuit  500  may delay the input signal by ΔS/k. 
     In some embodiments, when the target delay time is ΔS, each of the first and second step delay cells VBUF 1  and VBUF 2  included in the delay control circuit  600  may delay the input signal by ΔS/2. That is to say, in  FIG. 9B , each of the first and second step delay cells VBUF 1  and VBUF 2  may delay the fourth signal P 4  by (ΔS 2 )/2. In  FIG. 9C , each of the first and second step delay cells VBUF 1  and VBUF 2  may delay the fourth signal P 4  by (ΔS 3 )/2. 
     Referring to  FIG. 4 , as the magnitude of the delay time ΔS increases, the delay error ΔE may increase exponentially. Therefore, since the delay control circuit  500  delays ΔS by ΔS/k for k times, the delay error ΔE may be reduced. That is, the delay control circuit  500  may be a circuit with small sensitivity to PVT variation. This improved accuracy due to using the factor 1/k is due to the properties of exponential functions. Similarly, since the delay control circuit  600  delays ΔS by ΔS/2 twice (k=2, for example), the delay error ΔE may be reduced. 
     Referring to  FIGS. 9B and 9C , in some embodiments, there may be a relation of ΔS 3 =2(ΔS 2 ). Alternatively, in some other embodiments, there may be a relation of ΔS 3 =3(ΔS 2 ). For specific explanation, reference is made to  FIGS. 10A and 10B . 
       FIGS. 10A and 10B  are example tables for describing the code of the control signal according to some embodiments. 
     Referring to  FIGS. 6 and 10A , in some embodiments, the control signal STR[ 2 : 0 ] may follow a binary code. In other words, the control signal STR[ 2 : 0 ] may have the values of [000], [001], [010], [011], [100], [101], [110], and [111]. When the control signal STR[ 2 : 0 ] has the above respective values, the delay times (Delay) of the input signal may be 0, ΔS,  2 ΔS,  3 ΔS,  4 ΔS,  5 ΔS,  6 ΔS, and  7 ΔS, respectively. That is, each time the binary code of the control signal STR[ 2 : 0 ] increases by 1, the delay time (Delay) of the input signal may be increased by ΔS. In some embodiments, the control signal is applied to an ordered sequence of m capacitors in the step delay cell. A ratio between any two neighboring capacitors in the ordered sequence is ½. The ratio between a first capacitor in the sequence and the m th  capacitor is thus 2 −(m−1) . It is assumed that the propagation delay time tS due to the inverter is ignored. As an example, the capacitance ratio or proportions of the first capacitor C 1 , the second capacitor C 2 , and the third capacitor C 3  may be 4:2:1. Further, the capacitance ratio of the fourth capacitor C 4 , the fifth capacitor C 5 , and the sixth capacitor C 6  may be 4:2:1. 
     Therefore, in some embodiments, if the control signal STR[ 2 : 0 ] follows the binary code, there may be a relation of ΔS 3 =3(ΔS 2 ). 
     Referring to  FIGS. 6 and 10B , in some embodiments, the control signals STR[ 2 : 0 ] may follow a unary code or thermometer code. In other words, the control signals STR[ 2 : 0 ] may have values of [000], [001], [011], and [111]. A unary code is generally of the form 0 followed by zero or more 1s. When the control signal STR[ 2 : 0 ] has each of the above values, the delay time (Delay) of the input signal may be 0, ΔS,  2 ΔS, and  3 ΔS, respectively. That is, each time the unary code of the control signal STR[ 2 : 0 ] increases by 1, the delay time (Delay) of the input signal may be increased by ΔS. However, it is assumed that the propagation delay time tS due to the inverter is ignored. The capacitances of the first, second, third, fourth, fifth, and sixth capacitors C 1 , C 2 , C 3 , C 4 , C 5 , and C 6  may be the same. 
     Therefore, in some embodiments, if the control signal STR[ 2 : 0 ] follows the unary code, there may be a relation of ΔS 3 =2(ΔS 2 ). 
     In some embodiments, only the case where the voltage level of the input signal provided to the delay control circuit ( 500  in  FIG. 5, and 600  in  FIG. 6 ) increases is described, but the embodiments provided herein are not limited thereto. When the input signal decreases, a reverse operation of the operation described in some embodiments may be performed. For example, when the voltage level decreases at the first input node IN, the voltage of the first node N 1  may increase. Also, when the voltage level decreases in the first input node IN, the voltage of the second node N 2  may increase. 
       FIG. 11  is an example diagram for explaining occurrence of a duty error at a skewed corner. 
     Referring to  FIG. 11 , a typical signal (Typical) and signals (SF, FS) of the skewed corner are illustrated. 
     An SF corner (slow-fast corner) will be described on the basis of a typical signal (Typical). At the SF corner, the operation of the NMOS transistor may be slow, and the operation of the PMOS transistor may be fast. In other words, at the SF corner, the falling time of the signal level may be later than the falling time of the typical signal (Typical) level. Also, at the SF corner, the rising time of the signal level may be faster than the rising time of the typical signal (Typical) level. As a result, the duty ratio of the signal may increase at the SF corner. 
     An FS corner (fast-slow corner) will be described on the basis of the typical signal (Typical). At the FS corner, the operation of the NMOS transistor may be fast, and the operation of the PMOS transistor may be slow. In other words, at the FS corner, the falling time of the signal level may be faster than the falling time of the typical signal (Typical) level. Also, at the FS corner, the rising time of the signal level may be slower than the rising time of the typical signal (Typical) level. As a result, the duty ratio of the signal may be reduced at the FS corner. 
     In other words, the duty ratio of the signal may increase at the corner of SF, and the duty ratio of the signal may decrease at the FS corner. A change in the duty ratio of the signal having passed through the delay control circuit according to some embodiments will be described referring to  FIGS. 12A and 12B  at the skewed corner. 
       FIG. 12A  is an example view for illustrating a change in the duty ratio of the signal having passed through the delay control circuit according to some embodiments at the SF corner (slow-fast corner). 
       FIG. 12B  is an example view for illustrating a change in duty ratio of the signal having passed through the delay control circuit according to some embodiments at the FS corner (fast-slow corner). 
       FIGS. 12A and 12B  will be explained only from the viewpoint of the duty ratio, without considering the delay time of the signal passing through the delay control circuit according to some embodiments. Further, for the sake of convenience of explanation, it is assumed that the change in the duty ratio occurs only in the first and second step delay cells (VBUF 1 , VBUF 2 ). 
     Referring to  FIGS. 6 and 12A , an eleventh signal may be provided to the first input node IN. A width of the high level (e.g., 1) of the eleventh signal may be D 1 . 
     The fourth signal P 4  may be provided to the first output node O 1  through the first step delay cell VBUF 1 . At this time, a width of high level of the sixth signal P 6  may be D 2 . Here, the width D 2  of high level may be larger than the width D 1  of high level. 
     At the SF corner, since the rising time becomes faster and the falling time becomes slower, the width of the high level may increase. In other words, when the fourth signal P 4  passes through the first step delay cell VBUF 1 , the duty ratio may increase. 
     The sixth signal P 6  may be provided to the second input node I 1  through the first inverter INTb 1 . At this time, the width of the low level (e.g., 0) of the seventh signal P 7  may be D 2 . 
     The seventh signal P 7  may be provided to the second output node O 2  through the second step delay cell VBUF 2 . At this time, the width of low level of the ninth signal P 9  may be D 1 . At the SF corner, since the rising time becomes faster and the falling time becomes slower, the width of the low level may be reduced. In other words, when the seventh signal P 7  passes through the second step delay cell VBUF 2 , the duty ratio may decrease. 
     The ninth signal P 9  may be provided to the third output node OUT through the second inverter INTb 2 . The signal provided to the third output node OUT may have a high level width of D 1 . 
     As a result, the duty ratio of the signal provided to the first input node IN may be substantially the same as the duty ratio of the signal which is output to the third output node OUT. In other words, the duty ratio increased by passing through the first step delay cell VBUF 1  may be cancelled with the duty ratio reduced by passing through the second step delay cell VBUF 2 . Therefore, at the SF corner, the duty ratio of the signal passing through the delay control circuit  600  according to some embodiments may be maintained. In this way the duty ratio of the final waveform emerging from the delay control circuit approximately matches the duty ratio of the initial waveform input to the delay control circuit. 
     The description will be made with reference to  FIGS. 6 and 12B . For the sake of convenience of explanation, differences from the contents described above will be mainly described. 
     In the case of the FS corner, when the fourth signal P 4  passes through the first step delay cell VBUF 1 , the duty ratio of the sixth signal P 6  may decrease. When the seventh signal P 7  passes through the second step delay cell VBUF 2 , the duty ratio of the ninth signal P 9  may increase. That is, the duty ratio reduced by passing through the first step delay cell VBUF 1  may be canceled with the duty ratio increased by passing through the second step delay cell VBUF 2 . Therefore, at the FS corner, the duty ratio of the signal passing through the delay control circuit  600  according to some embodiments may be maintained. 
     The description will be made with reference to  FIGS. 5, 12A and 12B . For the sake of convenience of explanation, differences from the contents described above will be mainly described. 
     The delay control circuit  500  according to some embodiments may include an even number of step delay cells. In other words, k may be an even number. 
     At the FS corner, the duty ratio of the signal passed through the odd-numbered step delay cells (VBUF 1 , VBUF 3 , . . . , VBUFk−1) may increase. The duty ratio of the signal passed through the even-numbered step delay cells (VBUF 2 , VBUF 4 , . . . , VBUFk) may decrease. That is, the duty ratio increased by passing through the odd-numbered step delay cells (VBUF 1 , VBUF 3 , . . . , VBUFk−1) may be canceled with the duty ratio reduced by passing through the even-numbered step delay cells (VBUF 2 , VBUF 4 , . . . , VBUFk). Therefore, at the FS corner, the duty ratio of the signal passing through the delay control circuit  600  according to some embodiments may be maintained. In some situations, the various step delay cells of a delay circuit are all fabricated by the same process and experience the same voltage and temperature events during operation. Thus, the various step delay cells and exhibit the same PVT variations, if any. In the event that a particular fabricated delay circuit exhibits a skewed corner under given voltage and temperature conditions, embodiments provided herein compensate to provide an output clock waveform with a duty ratio that approximately matches a duty ratio of the clock waveform input to the delay circuit. 
     At the SF corner, the duty ratio of the signal passing through the odd-numbered step delay cells (VBUF 1 , VBUF 3 , . . . , VBUFk−1) may decrease. The duty ratio of the signal passing through the even-numbered step delay cells (VBUF 2 , VBUF 4 , . . . , VBUFk) may increase. That is, the duty ratio reduced by passing through the odd-numbered step delay cells (VBUF 1 , VBUF 3 , . . . , VBUFk−1) may be cancelled with the duty ratio increased by passing through the even-numbered step delay cells (VBUF 2 , VBUF 4 , . . . , VBUFk). Therefore, at the FS corner, the duty ratio of the signal passing through the delay control circuit  600  according to some embodiments may be maintained. 
       FIG. 13  is an example block diagram illustrating the structure of the memory which utilizes the delay control circuit according to some embodiments. 
     Referring to  FIG. 13 , the memory system  1300  may include a delay control circuit ( 500  of  FIG. 5, and 600  of  FIG. 6 ), a phase detection unit  1310 , a control unit  1320 , an input/output circuit  1330 , and a memory cell array  1340 . 
     The delay control circuit ( 500  of  FIG. 5, and 600  of  FIG. 6 ) may perform the same functions as those of the aforementioned contents. The input clock CLK_IN may be provided to the delay control circuit ( 500  of  FIG. 5, and 600  of  FIG. 6 ). The delay control circuit ( 500  of  FIG. 5, and 600  of  FIG. 6 ) may delay the input clock CLK_IN by a specific time and provide it to the output clock CLK_OUT. 
     The phase detection unit  1310  may compare the input clock CLK_IN with the output clock CLK_OUT. The phase detection unit  1310  may provide comparison data of the input clock CLK_IN and the output clock CLK_OUT to the control unit  1320 . 
     The control unit  1320  may adjust the delay time of the delay control circuit ( 500  of  FIG. 5, and 600  of  FIG. 6 ), using the comparison data provided from the phase detection unit  1310 . 
     The input/output circuit  1330  may receive the output clock CLK_OUT to read the value stored in the memory cell array  1340  or write the value on the memory cell array  1340 . For example, in some embodiments, the output clock CLK_OUT is used to access the contents of the memory cell array  1340 . The input clock CLK_IN may be an external clock waveform. The output clock CLK_OUT may be an internal clock waveform. The system  1300  synchronizes the output clock CLK_OUT with the input clock CLK_IN while limiting waveform distortion effects such as delay variation or duty cycle variation. 
     In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the example embodiments without substantially departing from the principles of the present disclosure. Therefore, the example embodiments are used in a generic and descriptive sense only and not for purposes of limitation.