Patent Publication Number: US-10783848-B2

Title: Display device subpixel activation patterns

Description:
BACKGROUND 
     This application claims the priority benefit of Korean Patent Application No. 10-2016-0160285 filed on Nov. 29, 2016, which is hereby incorporated herein by reference for all purposes as if fully set forth herein. 
     TECHNICAL FIELD 
     The present disclosure relates to a display device consuming less power and having enhanced display quality. 
     DESCRIPTION OF THE RELATED ART 
     A flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting display device, and the like. In a flat panel display device, data lines and gate lines are disposed to intersect with each other, and regions in which a data line and the gate line intersect with each other is defined as a single subpixel. A plurality of subpixels is formed in a panel. In order to drive each subpixel, a video data signal desired to be displayed is supplied to the data lines and a gate pulse is sequentially supplied to the gate lines. The video data signal is supplied to subpixels of a display line to which the gate pulse is supplied, and as all the data lines are sequentially scanned by the gate pulse, video data is displayed. 
     The video data signal provided to the data lines is generated by a data driver, and the data driver outputs a data voltage through a source channel connected to the data line. In order to reduce the number of source channels, a structure in which a plurality of data lines are connected to one source channel and a data voltage output to the source channel is supplied to the data lines in a time division manner using a multiplexer is used. The multiplexer includes switches selectively connecting the source channel and the plurality of data lines, and the switches are turned on in response to a control signal to connect the source channel and one data line. 
     As resolution of a display panel is increased, a time period during which a data voltage is supplied to one horizontal line is shortened, and accordingly, an output period of control signals for controlling switches is also shortened. Specifically, a period during which control signals from the multiplexer are reversed from a gate ON voltage to a gate OFF voltage or from a gate OFF voltage to a gate ON voltage is shortened. When reversing of a voltage level of control signals (e.g., transition) very frequently over a short period of time, a circuit section generating the control signal consumes a large amount of power. 
     BRIEF SUMMARY 
     According to an aspect of the present disclosure, a display device may include a display panel, a data driver, a multiplexer, and a multiplexer controller. First to fourth color subpixels may be disposed on the display panel. The data driver may output a data voltage to be supplied to the first to fourth color subpixels, through output buffers. The multiplexer may distribute each of data voltages output by the output buffers to four data lines in a time division manner in response to first to fourth control signals. The multiplexer controller may sequentially output a first control signal to an nth control signal during a first horizontal period, and sequentially output the nth control signal to the first control signal during a second horizontal period. The first and second horizontal periods may include first to fourth scan periods which are continuous and uniform, and a subpixel receiving a data voltage output during the first scan period of the first horizontal period and a subpixel receiving a data voltage output during the first scan period of the second horizontal period may be subpixels of the same color. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a view illustrating a display device according to an embodiment of the present disclosure. 
         FIG. 2  is a view illustrating an example of a subpixel illustrated in  FIG. 1 . 
         FIG. 3  is a view illustrating an example of a data driver. 
         FIG. 4  is a view illustrating a structure of multiplexers and subpixel arrays according to a first embodiment of the present disclosure. 
         FIG. 5  is a view illustrating a timing of control signals according to the first embodiment of the present disclosure. 
         FIG. 6  is a view illustrating a structure of multiplexers and subpixel arrays according to a second embodiment of the present disclosure. 
         FIG. 7  is a view illustrating a timing of control signals according to the second embodiment of the present disclosure. 
         FIG. 8  is a view illustrating a structure of multiplexers and subpixel arrays according to a third embodiment of the present disclosure. 
         FIG. 9  is a view illustrating a timing of control signals according to the third embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, one skilled in the art will understand that the disclosure may be practiced without these specific details. In other instances, well known structures associated with electronic components and fabrication techniques have not been described in detail to avoid unnecessarily obscuring the descriptions of the embodiments of the present disclosure. 
     Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising,” are to be construed in an open, inclusive sense; that is, as “including, but not limited to.” 
     Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. 
     As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise. 
     As used in the specification and the appended claims, the use of “correspond,” “corresponds,” and “corresponding” is intended to describe a ratio of or a similarity between referenced objects. The use of “correspond” or one of its forms should not be construed to mean the exact shape or size. 
     The present disclosure is directed to a display device with a set control signal timing. The display device includes color subpixels that are driven according to a set of control signals from a multiplexer. The multiplexer can provide various patterns of control signals, and in one embodiment provides gate control signals in a first sequence and then in a second sequence opposite the first sequence. This may result in reduced switching time and power as no gate signal switching is done at the beginning and end of the sequence. 
     In a gate driver of the present disclosure, switches may be implemented as transistors having a structure of n-type or p-type metal oxide semiconductor field effect transistors (MOSFETs). In the embodiments described hereinafter, an n-type transistor will be described, but the present disclosure is not limited thereto. For example, other types of transistors (e.g. P-type MOSFETs, BJTs, and TFETs) or other types of switches may also be used. In the present disclosure, outputting control signals refers to a state in which the corresponding control signals are in a gate ON voltage state. That is, gate ON voltage of the switches as n type transistors correspond to a high potential voltage and outputting or applying control signals refers to a state in which corresponding control signals are in a high potential voltage state. 
       FIG. 1  is a view illustrating a display device according to an embodiment of the present disclosure, and  FIG. 2  is a view illustrating an example of a subpixel illustrated in  FIG. 1 . 
     Referring to  FIGS. 1 and 2 , the display device of the present disclosure includes a display panel  100 , a timing controller  200 , a gate driver  300 , a data driver  400 , a multiplexer  500 , and a multiplexer controller  600 . 
     The display panel  100 , including a subpixel array in which subpixels are disposed in a matrix form, displays input image data. As illustrated in  FIG. 2  the subpixel array includes a thin film transistor (TFT) array formed on a lower substrate, a color filter array formed on an upper substrate, and liquid crystal cells Clc. The TFT array includes a data line DL and a gate line GL crossing the data line DL, a TFT formed at a crossing between the data line DL and the gate line GL, a subpixel electrode  1  connected to the TFT, a storage capacitor Cst, and the like. The color filter array includes a black matrix and a color filter. A common electrode  2  may be formed on the lower substrate or upper substrate. Liquid crystal cells Clc are driven by an electric field between the subpixel electrode  1  to which a data voltage is supplied and the common electrode  2  to which a common voltage Vcom is supplied. 
     The timing controller  200  may receive digital video data RGB from an external host and receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a main clock CLK, and the like. The timing controller  200  transmits the digital video signal RGB to the data driver  400 . The timing controller  200  generates a source timing control signal for controlling an operation timing of the data driver  400  using the timing signals Vsync, Hsync, DE, and CLK and gate timing control signals ST, GCLK, and MCLK for controlling an operation timing of a level shifter and a shift register of the gate driver  300 . 
     The gate driver  300  outputs a gate pulse Gout using a gate timing control signal. The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE). The gate start pulse (GSP) indicates a starting line for the gate driver  300  to output a first gate pulse Gout. The gate shift clock (GSC) is a clock for shifting the gate start pulse (GSP). The gate output enable (GOE) sets an output period of the gate pulse Gout. The gate driver  300  may be implemented in the form of a gate-in-panel (GIP) including a combination of TFTs on the display panel  100 . 
     The data driver  400  converts image data provided from the timing controller  200  into a data voltage. 
       FIG. 3  is a view illustrating a configuration of a data driver. Referring to  FIG. 3 , the data driver  400  includes a register unit  410 , a first latch  420 , a second latch  430 , a digital-to-analog converter (DAC)  440 , and an output unit  450 . The register unit  410  samples RGB digital video data bits of the input image using data control signals SSC and SSP provided from the timing controller  200 , and provides the sampled digital video data bits to the first latch  420 . The first latch  420  samples and latches the digital video data bits according to clocks sequentially provided from the register unit  410 , and simultaneously outputs the latched data. The second latch  430  latches data provided from the first latch  420  and simultaneously outputs latched data in response to a source output enable signal SOE. The DAC  440  converts video data input from the second latch unit  430  into a gamma compensation voltage GMA to generate an analog video data voltage. The output unit  450  provides an analog type data voltage ADATA output from the DAC  440  to the data lines DL during a low logical period of the source output enable signal SOE. The output unit  450  may be implemented as an output buffer outputting a data voltage using a low potential voltage GND and a voltage received through a high potential input terminal, as driving voltages. 
     The multiplexer  500  distributes data voltages output from output buffers to the plurality of data lines DL in a time division manner. In  FIG. 1 , an embodiment is depicted in which 3m number of data lines DL are connected to each output buffer. However, the number of data lines connected to the output buffers is not limited thereto. In some embodiments, the multiplexer is any switching device capable of selecting coupling an input to one or more of a plurality of outputs. In one embodiment the switching device is a switch having an input contact, an output contact, and a gate or state controller. 
       FIG. 4  is a view illustrating a structure of multiplexers and subpixel arrays according to a first embodiment of the present disclosure, and  FIG. 5  is a view illustrating a timing of control signals and a gate pulse according to the first embodiment of the present disclosure. 
     Referring to  FIGS. 4 and 5 , the display panel  100  includes red subpixels R, green subpixels G, and blue subpixels B disposed in parallel in each pixel line HL. The subpixels disposed in each pixel line receive a gate pulse GS 1  through the gate line GL. For example, subpixels P disposed in a first pixel line HL 1  receive a first gate pulse GS 1  through a first gate lines GL 1 . Also, subpixels P disposed in a second pixel line HL 2  receive a second gate pulse GS 2  through a second gate line GL 2 , and subpixels P disposed in a third pixel line HL 3  receive a third gate pulse GS 3  through a third gate line GL 3 . 
     In some embodiments, the different color subpixels R, G, and B are disposed in a repeating pattern. For example, in the last sequence, the red subpixels R are disposed in a (3m−2)th column line (CL[3m−2]), the green pixels G are disposed in a (3m−1)th column line (CL [3m−1]), and the blue subpixels B are disposed in a 3mth column line (CL 3   m ). In this example, red subpixels R are disposed in a first column line CL 1  and a fourth column line CL 4 . Green pixels G are disposed in a second column line CL 2  and a fifth column line CL 5 . Also, blue subpixels B are disposed in a third column line CL 3  and a sixth column line CL 6 . 
     The data driver  400  outputs a data voltage to three subpixels positioned in one pixel line HL during every horizontal period H. For example, a first output buffer BUF 1  of the data driver  400  sequentially outputs a data voltage applied to R 11 , G 12 , and G 13  during a first scan period t 1  of the first horizontal period 1 st  H. In this embodiment, R (or B or B)xy represents a color and a position of a subpixel. That is, Rab refers to a red subpixel positioned in a horizontal line a and a column line b. Thus, R 11  refers to a red subpixel positioned in a first column line CL 1  in the first pixel line HL 1 . Also, in  FIG. 5 , Data 1  illustrates subpixels to which a data voltage output by the first output buffer BUF 1  is applied. Also, the first horizontal period  1 H may be defined as a period during which a data voltage is supplied to the subpixels P disposed in one pixel line HL. The data driver  400  supplies the data voltage to three subpixels during the first horizontal period  1 H in a time division manner. Each of the first to third scan periods t 1  to t 3  of each horizontal period is defined as a period during which a data voltage applied to one subpixel P is output. 
     The multiplexer  500  distributes data voltages, which are output by the output buffers BUF, to a plurality of data lines. The multiplexer  500  according to the first embodiment distributes a data voltage output by the first output buffer BUF 1  to first to third data lines DL 1  to DL 3  in a time division manner. To this end, the multiplexer  500  includes first to third switches M 1 , M 2 , and M 3 . The first switch M 1  is turned on in response to a first control signal Mux 1  to connect the first output buffer BUF 1  and the first data line DL 1 . The second switch M 2  is turned on in response to a second control signal Mux 2  to connect the first output buffer and the second data line DL 2 , and the third switch M 3  is turned on in response to a third control signal Mux 3  to connect the first output buffer BUF 1  and the third data line DL 3 . 
     The multiplexer controller  600  outputs the first to third control signals in a time division manner during one horizontal period H. The multiplexer controller  600  may sequentially output the first, second, and third control signals Mux 1 , Mux 2 , and Mux 3  or sequentially output the third, second, and first control signals Mux 3 , Mux 2 , and Mux 1 , during one horizontal period. For example, the multiplexer controller  600  sequentially outputs the first to third control signals Mux 1  to Mux 3  during the first horizontal period 1 st  H and sequentially outputs the third to first control signals Mux 3  to Mux 1  during a second horizontal period 2 nd  H. 
     The first to third control signals Mux 1  to Mux 3  are sequentially output during each horizontal period H in which the gate pulse GS maintains a gate ON voltage. For example, during the first horizontal period  1 H, the first gate pulse GS 1  maintains the gate ON voltage and the first to third control signals Mux 1  to Mux 3  are sequentially output. 
     As a result, the subpixel R 11  is charged during the first scan period t 1  of the first horizontal period 1 st  H, the subpixel G 12  is charged during the second scan period t 2  of the first horizontal period 1 st  H, and the subpixel B 13  is charged during the third scan period t 3  of the first horizontal period 1 st  H. 
     Also, the subpixel B 23  is charged during a first scan period t 1  of a second horizontal period 2 nd  H, the subpixel G 22  is charged during a second scan period t 2  of the second horizontal period 2 nd  H, and the subpixel R 21  is charged during a third scan period t 3  of the second horizontal period 2 nd  H. 
     In this manner, in the first embodiment, the third control signal Mux 3  is output during the final period of the first horizontal period 1 st  H and the first period of the second horizontal period 2 nd  H. That is, the number of times the third control signal Mux 3  is reversed to a gate ON voltage and the number of times the third control signal Mux 3  is reversed to a gate OFF voltage from the first horizontal period 1 st  H to the second horizontal period 2 nd  H are one time, respectively. Similarly, the number of times the first control signal Mux 1  is reversed to a gate ON voltage and the number of times the first control signal Mux 1  is reversed to a gate OFF voltage from the second horizontal period 2 nd  H to the third horizontal period 3 rd  H are one time, respectively. 
     As a result, overall transition number of the control signals Mux 1  to Mux 3  output by the multiplexer controller  600  is reduced, and thus, power consumption of the multiplexer controller  600  is reduced. 
       FIG. 6  is a view illustrating a structure of pixel arrays and multiplexers according to a second embodiment of the present disclosure, and  FIG. 7  is a timing diagram of control signals and gate pulses according to the second embodiment of the present disclosure. 
     Referring to  FIGS. 6 and 7 , subpixels include a white subpixel W, a red subpixel R, a green subpixel G, and a blue subpixel B. 
     In odd-numbered pixel lines HL 1  and HL 3 , W, R, G, and B subpixels are sequentially disposed, and in even-numbered pixel lines HL 2  and HL 4 , G, B, W, and R subpixels are sequentially disposed. Thus, the W, R, G, and B subpixels disposed in parallel in each pixel line may form a unit pixel. Alternately, W, R, G, and B subpixels disposed in 2×2 unit may form a unit pixel. In image rendering of the display panel, one unit pixel may be used as a reference or two adjacent subpixels may be used as a reference. 
     The multiplexer  500  distributes data voltages, which are output by the output buffers BUFs, to a plurality of data lines. The multiplexer  500  distributes a positive (+) polarity data voltage, which is output by the first output buffer BUF 1 , to a first data line DL 1 , a third data line DL 3 , a sixth data line DL 6 , and an eight data line DL 8  in a time division manner. Also, the multiplexer  500  distributes a negative (−) polarity data voltage, which is output by the second output buffer BUF 2 , to a second data line DL 2 , a fourth data line DL 4 , a fifth data line DL 5 , and a seventh data line DL 7  in a time division manner. To this end, the multiplexer  500  includes first to eighth switches M 1  to M 8 . 
     The first switch M 1  is turned on in response to the first control signal Mux 1  to connect the first output buffer BUF 1  to the first data line DL 1 . The third switch M 3  is turned on in response to the third control signal Mux 3  to connect the first output buffer BUF 1  to the third data line DL 3 . The sixth switch M 6  is turned on in response to the second control signal Mux 2  to connect the first output buffer BUF 1  to the sixth data line DL 6 . The eighth switch M 8  is turned on in response to the fourth control signal Mux 4  to connect the first output buffer BUF 1  to the eighth data line DL 8 . 
     The second switch M 2  is turned on in response to the second control signal Mux 2  to connect the second output buffer BUF 2  to the second data line DL 2 . The fourth switch M 4  is turned on in response to the fourth control signal Mux 4  to connect the second output buffer BUF 2  to the fourth data line DL 4 . The fifth switch M 5  is turned on in response to the first control signal Mux 1  to connect the second output buffer BUF 2  to the fifth data line DL 5 . The seventh switch M 7  is turned on in response to the third control signal Mux 3  to connect the second output buffer BUF 2  to the seventh data line DL 7 . 
     The multiplexer controller  600  outputs the first to fourth control signals Mux 1  to Mux 4  in a time division manner during one horizontal period  1 H. The multiplexer controller  600  may sequentially output the first control signal Mux 1  to the fourth control signal Mux 4  or sequentially output the fourth control signal Mux 4  to the first control signal Mux 1  during one horizontal period. For example, the multiplexer controller  600  may sequentially output the first control signal Mux 1  to the fourth control signal Mux 4  during a first horizontal period 1 st  H and sequentially output the fourth control signal Mux 4  to the first control signal Mux 1  during a second horizontal period 2 nd  H. 
     Within one horizontal period  1 H, the first control signal Mux 1  to the fourth control signal Mux 4  are output during one scan period  1   t . Within each horizontal period H, each of first to fourth scan periods t 1  to t 4  is defined as a period during which a data voltage applied to one subpixel P is output. 
     The data driver  400  outputs data voltages having the opposite polarities through mutually adjacent output buffers. For example, the data driver  400  may output a positive (+) polarity data voltage to the output buffer BUF 1  and output a negative (−) polarity data voltage to the second output buffer BUF 2 . 
     The data driver  400  outputs a data voltage to one pixel line HL during each horizontal period H. In  FIG. 7 , Data 1  represents subpixels to which a data voltage output by the first output buffer BUF 1  is applied, and Data 2  represents subpixels to which a data voltage output by the second output buffer BUF 2  is applied. That is, the first output buffer BUF 1  of the data driver  400  sequentially outputs a data voltage supplied to subpixels positioned in a first column line CL 1 , a sixth column line CL 6 , a third column line CL 3 , and an eighth column line CL 8  during each horizontal period H. The second output buffer BUF 2  sequentially outputs a data voltage supplied to subpixels positioned in a fifth column line CL 5 , a second column line CL 2 , a seventh column line CL 7 , and a fourth column line CL 4  during each horizontal period H. 
     As a result, a subpixel W 11  and a subpixel W 15  are charged during a first scan period t 1  of the first horizontal period 1 st  H. A subpixel R 16  and a subpixel R 12  are charted during a second scan period t 2  of the first horizontal period 1 st  H. A subpixel G 13  and a subpixel G 17  are charged during a third scan period t 3  of the first horizontal period 1 st  H. A subpixel B 18  and a subpixel B 14  are charged during a fourth scan period t 4  of the first horizontal period 1 st  H. 
     Since the same control signal is maintained at the gate ON voltage during the fourth scan period t 4  of the first horizontal period 1 st  H and during the first scan period t 1  of the second horizontal period 2 nd  H, power consumption of the multiplexer controller  600  may be reduced. 
     In the second embodiment having the RGBW structure, since subpixels of different colors are disposed in the same column line of adjacent pixel lines, a data voltage of a different color may be introduced in a section in which a gate pulse is reversed to a gate OFF voltage. For example, as illustrated in  FIG. 7 , the first output buffer BUF 1  outputs a data voltage supplied to a subpixel B 18  during a fourth scan period t 4  of the first horizontal period 1 st  H and outputs a data voltage supplied to a subpixel R 28  during a first scan period t 1  of the second horizontal period 2 nd  H. Since the first gate pulse GS 1  is reversed to a gate OFF voltage at a timing when the first horizontal period 1 st  H expires, the subpixel B 18  does not receive a data voltage during the second horizontal period 2 nd  H. However, the first gate pulse GS 1  may maintain the gate ON voltage even at an initial stage of the second horizontal period 2 nd  H due to RC delay, and, as a result, the data voltage supplied to the subpixel R 28  is mixed in the subpixel B 18 . Due to this, the subpixel B 18  may not represent an intended gray level. 
     A third embodiment described hereinafter is to improve a degradation of display quality of an image caused as the data voltage is mixed due to RC delay of the gate pulse GS.  FIG. 8  is a view illustrating a structure of pixel arrays and multiplexers according to a third embodiment of the present disclosure, and  FIG. 9  is a view illustrating a timing of control signals and gate pulses according to the third embodiment of the present disclosure. 
     Referring to  FIGS. 8 and 9 , subpixels include a white subpixel W, a red subpixel R, a green subpixel G, and a blue subpixel B. In odd-numbered pixel lines HL 1  and HL 3 , W, R, G, and B subpixels are sequentially disposed, and in even-numbered pixel lines HL 2  and HL 4 , G, B, W, and R subpixels are sequentially disposed. Thus, the W, R, G, and B subpixels disposed in parallel in each pixel line may form a unit pixel. Alternately, W, R, G, and B subpixels disposed in 2×2 unit may form a unit pixel. In image rendering of the display panel, one unit pixel may be used as a reference or two adjacent subpixels may be used as a reference. 
     The multiplexer  500  distributes data voltages, which are output by the output buffers BUFs, to a plurality of data lines. The multiplexer  500  distributes a positive (+) polarity data voltage, which is output by the first output buffer BUF 1 , to a first data line DL 1 , a sixth data line DL 6 , a third data line DL 3 , and an eight data line DL 8  in a time division manner. Also, the multiplexer  500  distributes a negative (−) polarity data voltage, which is output by the second output buffer BUF 2 , to a fifth data line DL 5 , a second data line DL 2 , a seventh data line DL 7 , and a fourth data line DL 4  in a time division manner. To this end, the multiplexer  500  includes first to eighth switches M 1  to M 8 . 
     The first switch M 1  is turned on in response to the first control signal Mux 1  to connect the first output buffer BUF 1  to the first data line DL 1 . The sixth switch M 6  is turned on in response to the second control signal Mux 2  to connect the first output buffer BUF 1  to the sixth data line DL 6 . The third switch M 3  is turned on in response to the third control signal Mux 3  to connect the first output buffer BUF 1  to the third data line DL 3 . The eighth switch M 8  is turned in response to the fourth control signal Mux 4  to connect the first output buffer BUF 1  to the eighth data line DL 8 . 
     The fifth switch M 5  is turned on in response to the first control signal Mux 1  to connect the second output buffer BUF 2  to the fifth data line DL 5 . The second switch M 2  is turned on in response to the second control signal Mux 2  to connect the second output buffer BUF 2  to the second data line DL 2 . The seventh switch M 7  is turned in response to the third control signal Mux 3  to connect the second output buffer BUF 2  to the seventh data line DL 7 . The fourth switch M 4  is turned on in response to the fourth control signal Mux 4  to connect the second output buffer BUF 2  to the fourth data line DL 4 . 
     The multiplexer controller  600  outputs the first to fourth control signals Mux 1  to Mux 4  in a time division manner during one horizontal period  1 H. The multiplexer controller  600  may sequentially output the first control signal Mux 1  to the fourth control signal Mux 4  or sequentially output the fourth control signal Mux 4  to the first control signal Mux 1  during one horizontal period. For example, the multiplexer controller  600  may sequentially output the first control signal Mux 1  to the fourth control signal Mux 4  during a first horizontal period 1 st  H and sequentially output the fourth control signal Mux 4  to the first control signal Mux 1  during a second horizontal period 2 nd  H. 
     Within one horizontal period  1 H, the first control signal Mux 1  to the fourth control signal Mux 4  are output during one scan period  1   t . Within each horizontal period H, each of first to fourth scan periods t 1  to t 4  is defined as a period during which a data voltage applied to one subpixel P is output. 
     The data driver  400  outputs data voltages having the opposite polarities through mutually adjacent output buffers. For example, the data driver  400  may output a positive (+) polarity data voltage to the output buffer BUF 1  and output a negative (−) polarity data voltage to the second output buffer BUF 2 . 
     The data driver  400  outputs a data voltage to one pixel line HL during each horizontal period H. In  FIG. 9 , Data 1  represents subpixels to which a data voltage output by the first output buffer BUF 1  is applied, and Data 2  represents subpixels to which a data voltage output by the second output buffer BUF 2  is applied. That is, the first output buffer BUF 1  of the data driver  400  sequentially outputs a data voltage supplied to subpixels positioned in a first column line CL 1 , a sixth column line CL 6 , a third column line CL 3 , and an eighth column line CL 8  during each horizontal period H. The second output buffer BUF 2  sequentially outputs a data voltage supplied to subpixels positioned in a fifth column line CL 5 , a second column line CL 2 , a seventh column line CL 7 , and a fourth column line CL 4  during each horizontal period H. 
     A connection relation between the subpixels and the data lines disposed on the display panel  100  according to the third embodiment is as follows. A subpixel W positioned in the first pixel line HL 1  is connected to any one of the data lines DL applying a data voltage to a subpixel W positioned in the second pixel line HL 2 . A subpixel R positioned in the first pixel line HL 1  is connected to any one of the data lines DL applying a data voltage to a subpixel R positioned in the second pixel line HL 2 . A subpixel G positioned in the first pixel line HL 1  is connected to any one of the data lines DL applying a data voltage to a subpixel G positioned in the second pixel line HL 2 . A subpixel B positioned in the first pixel line HL 1  is connected to any one of the data lines DL applying a data voltage to a subpixel B positioned in the second pixel line HL 2 . 
     In detail, in the odd-numbered pixel lines HL 1  and HL 3 , the subpixel W is disposed in a (4k−3)th (k is a natural number of 2 or greater) column line CL(4k−3), the subpixel R is disposed in a (4k−2)th column line CL(4k−2), the subpixel G is disposed in a (4k−1)th column line CL(4k−1), and the subpixel B is disposed in the (4k)th column line 4k. 
     In the even-numbered pixels lines HL 2  and HL 4 , the subpixel G is disposed in a (4k−3)th column line CL(4k−3), the subpixel B is disposed in a (4k−2)th column line CL(4k−2), the subpixel W is disposed in a (4k−1)th column line CL(4k−1), and the subpixel R is disposed in the (4k)th column line 4k. In  FIG. 8 , a structure of a transistor of subpixels disposed in the even-numbered pixel lines HL 2  and HL 4  is omitted. As illustrated in  FIG. 2 , ith subpixels disposed in the even-numbered pixel lines HL 2  and HL 4  may include a drain electrode connected to an ith data line, a gate electrode connected to a gate line, and a source electrode connected to a pixel electrode. 
     In the odd-numbered pixel lines HL 1  and HL 3 , ith subpixels are connected to a (i−2)th data line. That is, ith subpixels include a transistor including a gate electrode connected to a gate line GL, a drain electrode connected to a (i−2)th data line, and a source electrode connected to a pixel electrode  1 . As a result, the ith subpixels receive a data voltage through the (i−2)th data line in the odd-numbered pixel lines HL 1  and HL 3 . For example, in the first pixel line HL 1 , a subpixel G 13  positioned in the third column line CL 3  receives a data voltage through the first data line DL 1  and a subpixel B 14  positioned in the fourth column line CL 4  receives a data voltage through the second data line DL 2 . 
     Also, in  FIG. 8 , in the odd-numbered pixel lines HL 1  and HL 3 , first and second subpixels may be regarded as dummy subpixels. For example, a subpixel W 11  and a subpixel R 12  of the first pixel line HL 1  and a subpixel W 31  and a subpixel R 32  of the third pixel line HL 3  may be regarded as dummy subpixels. Since the dummy subpixels W 11 , R 12 , W 31 , and R 32  are not connected to data lines, the dummy subpixels are blind spots. Thus, the first and second column lines CL 1  and CL 2  in which the dummy subpixels W 11 , R 12 , W 31 , and R 32  are disposed may be covered by a black matrix. 
     As a result, subpixels to which the first data voltage Data 1 , which is output by the first output buffer BUF 1 , is supplied are as follows. 
     During the first scan period t 1  of the first horizontal period 1 st  H, the first switch M 1  connects the first output buffer BUF 1  to the first data line DL 1  in response to the first control signal Mux 1 . As a result, a data voltage supplied by the first output buffer BUF 1  is applied to the subpixel G 13  by way of the first data line DL 1 . 
     During the second scan period t 2  of the first horizontal period 1 st  H, the sixth switch M 6  connects the first output buffer BUF 1  to the sixth data line DL 6  in response to the second control signal Mux 2 . As a result, the data voltage supplied by the first output buffer BUF 1  is applied to the subpixel B 18  by way of the sixth data line DL 6 . 
     During the third scan period t 3  of the first horizontal period 1 st  H, the third switch M 3  connects the first output buffer BUF 1  to the third data line DL 3  in response to the third control signal Mux 3 . As a result, the data voltage supplied by the first output buffer BUF 1  is applied to the subpixel W 15  by way of the third data line DL 3 . 
     During the fourth scan period t 4  of the first horizontal period 1 st  H, the eighth switch M 8  connects the first output buffer BUF 1  to the eighth data line DL 8  in response to the fourth control signal Mux 4 . As a result, the data voltage supplied by the first output buffer BUF 1  is applied to the subpixel R 10  by way of the eighth data line DL 8  (not shown). 
     During the first scan period t 1  of the second horizontal period 2 nd  H, the eighth switch M 8  connects the first output buffer BUF 1  to the eighth data line DL 8  in response to the fourth control signal Mux 4 . As a result, the data voltage supplied by the first output buffer BUF 1  is applied to the subpixel R 28  by way of the eighth data line DL 8 . 
     Subpixels to which the second data voltage Data 2 , which is output by the second output buffer BUF 2 , is supplied are as follows. 
     During the first scan period t 1  of the first horizontal period 1 st  H, the fifth switch M 5  connects the second output buffer BUF 2  to the fifth data line DL 5  in response to the first control signal Mux 1 . As a result, a data voltage supplied by the second output buffer BUF 2  is applied to the subpixel G 17  by way of the fifth data line DL 5 . 
     During the second scan period t 2  of the first horizontal period 1 st  H, the second switch M 2  connects the second output buffer BUF 2  to the second data line DL 2  in response to the second control signal Mux 2 . As a result, the data voltage supplied by the second output buffer BUF 2  is applied to the subpixel B 14  by way of the second data line DL 2 . 
     During the third scan period t 3  of the first horizontal period 1 st  H, the seventh switch M 7  connects the second output buffer BUF 2  to the seventh data line DL 7  in response to the third control signal Mux 3 . As a result, the data voltage supplied by the second output buffer BUF 2  is applied to the subpixel W 19  by way of the seventh data line DL 7 . 
     During the fourth scan period t 4  of the first horizontal period 1 st  H, the fourth switch M 4  connects the second output buffer BUF 2  to the fourth data line DL 4  in response to the fourth control signal Mux 4 . As a result, the data voltage supplied by the second output buffer BUF 2  is applied to the subpixel R 16  by way of the fourth data line DL 4 . 
     During the first scan period t 1  of the second horizontal period 2 nd  H, the fourth switch M 4  connects the second output buffer BUF 2  to the fourth data line DL 4  in response to the fourth control signal Mux 4 . As a result, the data voltage supplied by the second output buffer BUF 2  is applied to the subpixel R 24  by way of the fourth data line DL 4 . 
     As described above, in the display device according to the third embodiment, the subpixels of the same color are connected to each data line. For example, during the fourth scan period r 4  of the first horizontal period 1 st  H and during the first scan period t 1  of the second horizontal period 2 nd  H, the first output buffer BUF 1  supplies a data voltage to the subpixel R. Thus, although the data voltage applied to the subpixel R 10  and the subpixel R 28  is supplied during the first scan period t 1  of the second horizontal period 2 nd  H due to delay of the first gate pulse GS 1 , the data voltage written to the subpixel R 10  is rarely changed. This is because, since the subpixel R 10  and the subpixel R 28  are positioned to be very close to each other, there is a high possibility that the same or very similar data voltage is supplied to the subpixel R 10  and the subpixel R 28 . 
     In this manner, when one control signal maintains the gate ON voltage in a continuous scan period, although a different data voltage is mixed in a subpixel due to delay of the gate pulse GS, a degradation of display quality may be improved. 
     Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art. 
     The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
     These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.