Patent Publication Number: US-7584304-B2

Title: Non-volatile memory storage device including an interface select switch and associated method

Description:
BACKGROUND OF THE INVENTION 
   This application claims priority from Korean patent application No. 10-2004-0076914, filed on Sep. 24, 2004, which we incorporate by reference. 
   1. Field of the Invention 
   The field of the invention relates to a non-volatile memory storage device and, more particularly, to a non-volatile memory storage device including a switch to select between one or more interfaces. 
   2. Description of the Related Art 
   A non-volatile memory storage device is a small device that can store a large amount of data without requiring a continuous power supply. Thus, the non-volatile memory storage device is frequently used as a portable storage device. 
   Conventional non-volatile memory storage devices typically support only one interface, either the Advanced Technology Attachment (ATA) specification or the Serial Advanced Technology Attachment (SATA) specification. Accordingly, there is a need for a non-volatile semiconductor memory storage device that can support both the SATA and ATA interfaces. 
   SUMMARY OF THE INVENTION 
   The present invention provides a non-volatile semiconductor memory storage device capable of supporting a plurality of storage interfaces. The device comprises a non-volatile memory and an interface unit including a plurality of storage interfaces. The interface unit is adapted to select a storage interface from the plurality of storage interfaces responsive to a selection signal. The non-volatile memory is adapted to exchange data with a host external to the device via the selected storage interface. In an embodiment, the selected storage interface is an ATA storage interface to convert the exchanged data in accordance with an ATA protocol when selected responsive to the selection signal. In another embodiment, the selected storage interface is a SATA storage interface to convert the exchanged data in accordance with a SATA protocol when selected responsive to the selection signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The aspects and advantages of the present invention will become more apparent with the detailed description of the exemplary embodiments with reference to the attached drawings. 
       FIG. 1  is a block diagram of a non-volatile memory storage device according to an embodiment of the present invention. 
       FIG. 2  is a block diagram of the interface unit in  FIG. 1 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Embodiments of the present invention will now be described in detail with reference the accompanying drawings. Like reference numerals are used to designate like or equivalent elements throughout this description. 
     FIG. 1  is a block diagram of a non-volatile memory storage device  100  according to an embodiment of the present invention. The non-volatile memory storage device  100  includes a non-volatile memory  101 , a memory controller  103 , an interface unit  105 , a memory buffer  107 , a central processing unit (CPU) interface unit  109 , and a CPU  111 . 
   The non-volatile memory  101  stores data from an external host. As shown in  FIG. 1 , the non-volatile memory  101  may comprise a plurality of non-volatile memory chips. The non-volatile memory  101  may be flash memory. 
   The memory controller  103  controls access to the non-volatile memory  101 . The memory controller  103  may detect and correct errors in the data stored to or retrieved from the non-volatile memory  101 . Although not shown in the drawings, the memory controller  103  may include a scrambler to map an input digital signal stream to a signal stream with different statistical characteristics, and an arbiter to allow access to non-volatile memory  101  according to priority. 
   The interface unit  105  selects either an ATA interface or an SATA interface in response to an external ATA/SATA selection signal I/F_SEL, and allows the exchange of data between the external host and the non-volatile memory storage device  100  via the selected ATA or SATA interface. The interface unit  105  may allow the exchange of data or signals between the external host and the CPU  111 . The ATA/SATA selection signal I/F_SEL may be generated using an external selection switch (not shown). The external selection switch may be a jumper switch. In other words, the interface unit  105  may select either the ATA interface or the SATA interface using the external selection switch. When the ATA interface is selected, the interface unit  105  converts data exchanged between the external host and the non-volatile memory  101  according to the ATA specification. When the SATA interface is selected, the interface unit  105  converts data exchanged between the external host and the non-volatile memory  101  according to the SATA specification. Since the SATA interface is backward compatible with respect to the ATA interface, e.g., implementing E-IDE (Extended-Integrated Drive Electronics), the ATA interface may be executed using the SATA interface. 
   The memory buffer  107  temporarily stores data retrieved from or to be stored to non-volatile memory  101 . The memory buffer  107  may store a program(s) to be executed by the CPU  111 . The memory buffer  107  may be a static random access memory (SRAM). The CPU interface unit  109  couples the interface unit  105 , the memory controller  103 , with the CPU  111 , so the CPU  111  may provide signals to the interface unit  105  and the memory controller  103 . The CPU  111  may control the overall operation of the non-volatile memory storage device  100  by executing the program stored in the memory buffer  107 . 
   Accordingly, non-volatile memory storage device  100  supports both the ATA interface and the SATA interface without installing different software. 
     FIG. 2  is a detailed block diagram of the interface unit  105 . Referring to  FIG. 2 , the interface unit  105  includes an ATA interface logic unit  201 , a SATA interface logic unit  203 , and a multiplexer  205 . The ATA interface logic unit  201  supports the ATA interface. Specifically, the ATA interface logic unit  201  converts data from the non-volatile memory  101 , or signals from the other elements of the non-volatile memory storage device  100 , into data that satisfies the ATA protocol, and provides the converted data to an external host. The ATA interface logic unit  201  receives data from an external host, converts the data in accordance to the ATA specification, and provides the converted data to the non-volatile memory  101  or the other elements within device  100 . 
   The SATA interface logic unit  203  supports the SATA interface. Specifically, the SATA interface logic unit  203  converts data from the non-volatile memory  101 , or signals from the other elements of device  100 , into data that satisfies the SATA protocol, and provides the converted data to an external host. The SATA interface logic unit  203  receives data from an external host, converts the data in accordance to the SATA specification, and provides the converted data to the non-volatile memory  101  or the other elements within device  100 . 
   In response to the ATA/SATA selection signal I/F_SEL, the multiplexer  205  provides data from the non-volatile memory  101  to either the ATA interface logic unit  201  or the SATA interface logic unit  203 . The multiplexer  205  provides data from either the ATA interface logic unit  201  or the SATA interface logic unit  203  to the non-volatile memory  101 , via the memory controller  103 . 
   As described above, a non-volatile memory storage device  100  according to an embodiment of the present invention is capable of supporting both the SATA and the ATA specifications without an additional interface. Therefore, the non-volatile memory storage device  100  implements both interfaces with the same software. 
   While this invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.