Patent Publication Number: US-10777888-B2

Title: Beamforming integrated circuit with RF grounded material ring

Description:
PRIORITY 
     This patent application claims priority from provisional U.S. patent application No. 62/412,122, filed Oct. 24, 2016, entitled, “HIGH PERFORMANCE PACKAGED MICROCHIP,” and naming Vipul Jain, Noyan Kinayman, Robert McMorrow, Kristian Madsen, Shamsun Nahar, and Nitin Jain as inventors, the disclosure of which is incorporated herein, in its entirety, by reference. 
    
    
     FIELD OF THE INVENTION 
     Various embodiments of the invention generally relate to high-frequency microchips and, more particularly, various embodiments of the invention relate to managing the signal-to-noise ratios of beamforming microchips for use with phased arrays. 
     BACKGROUND OF THE INVENTION 
     Active electronically steered antenna systems (“AESA systems,” a type of “phased array system”) or active antenna systems form electronically steerable beams for a wide variety of radar and communications systems. To that end, AESA systems typically have a plurality of beam-forming elements (e.g., antennas) that transmit and/or receive energy so that such energy can be coherently combined (i.e., in-phase and amplitude). This process is referred to in the art as “beam forming” or “beam steering.” Specifically, for transmission, many AESA systems implement beam steering by providing various RF phase shift and gain settings. The phase settings and gain weights together constitute a complex beam weight between each beam-forming element. For a signal receiving mode, many AESA systems use a beamforming or summation point. 
     To achieve beam-forming using an antenna array, each antenna element is connected to a semiconductor integrated circuit generally referred to as a “beam-forming IC.” This microchip/integrated circuit may have a number of sub-circuit components implementing various functions. For example, those components may implement phase shifters, amplitude control modules or a variable gain amplifier (VGA), a power amplifier, a power combiner, a digital control, and other electronic functions. Such an integrated circuit is packaged to permit input and output radio frequency (RF) connections. 
     Undesirably, some interfaces to the integrated circuit can interfere with other local interfaces or metal in its body (e.g., a seal ring), causing phase and amplitude modulation. In addition, due to inefficient packaging configurations, the integrated circuit often operates at higher than preferred temperatures. 
     SUMMARY OF VARIOUS EMBODIMENTS 
     In accordance with one embodiment of the invention, a beamforming integrated circuit system for use in a phased array has a microchip with RF circuitry, and a plurality of (on chip) interfaces electrically connected with the RF circuitry. The plurality of interfaces includes a signal interface, a first ground interface, and a second ground interface. The signal interface is configured to communicate an RF signal, and both the first and second ground interfaces are adjacent to the signal interface. The system also has a material ring circumscribing the plurality of interfaces, and at least one RF ground path coupled with the material ring. 
     The RF circuitry preferably operates at high frequencies, such as between about 5 GHz and 300 GHz. For mounting, the plurality of interfaces may be configured to be flip-chip mounted on a substrate. To that end, the system also may include a printed circuit board, and the microchip may be flip-chip mounted to the printed circuit board. In addition, the RF ground path may include a via extending through the printed circuit board, a metal layer on the microchip, and a fifth ground interface. In this case, the metal layer physically connects the fifth ground interface with the material ring. 
     The at least one RF ground path may include a plurality of RF ground paths coupled about the material ring. Those paths may be coupled at points along the material ring using a spacing on the order of magnitude of anticipated wavelengths of RF signals operated on by the microchip. For example, the integrated circuit may be configured to operate on an RF signal having a given wavelength, and the plurality of ground paths each electrically connect with the material ring at prescribed points. These prescribed points are space apart a prescribed distance from each other. This prescribed distance may be between 0.1*given wavelength and 2.0*given wavelength. 
     Rather than using a die level package, some embodiments may use a package level package with a plurality of package interfaces. To electrically communicate the microchip with the package, the system also may have wirebonds coupling each of the first ground interface, the second ground interface, and the signal interface to at least one of the plurality of package interfaces. 
     The signal interface may be considered to have a first side and a second, opposite side. To improve performance, the first ground interface is adjacent to the first side, and the second ground interface is adjacent to the second side. Indeed, many embodiments may have more interfaces. For example, the plurality of interfaces may have a second signal interface, a third ground interface and a fourth ground interface. In a manner similar to the first and second ground interfaces, the third ground interface and fourth ground interface may be adjacent to the second signal interface. 
     The material ring protects the microchip. To that end, the material ring may include one or both of a crackstop ring and a seal ring. In that case, the material ring may include metal. Moreover, despite being referred to as a “ring,” the material ring may have discontinuities. 
     In accordance with another embodiment, a beamforming integrated circuit system for use in a phased array has a microchip with both RF circuitry and a bottom side, and a plurality of interfaces electrically connected with the RF circuitry. The plurality of interfaces includes a signal interface, a first ground interface, and a second ground interface. As with various other embodiments, the signal interface is configured to communicate an RF signal, while the first and second ground interfaces are adjacent to the signal interface. The system also has a material ring (at least one of a crackstop ring and a seal ring) circumscribing the plurality of interfaces, a ground path, and metal on the bottom side of the microchip and configured to electrically connect the material ring with the ground path. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Those skilled in the art should more fully appreciate advantages of various embodiments of the invention from the following “Description of Illustrative Embodiments,” discussed with reference to the drawings summarized immediately below. 
         FIG. 1  schematically shows an active electronically steered antenna system (“AESA system”) that can implement an AESA microchip configured accordance with illustrative embodiments of the invention. 
         FIG. 2  schematically shows a plan view of an AESA microchip having a wafer level package, as well as a cross-sectional view of the same microchip flip-chip mounted on a printed circuit board, in accordance with illustrative embodiments of the invention. 
         FIG. 3A  schematically shows a plan view of another AESA microchip having wafer level package, as well as a cross-sectional view of the same microchip flip-chip mounted on a printed circuit board, in accordance with yet another embodiment of the invention. 
         FIG. 3B  schematically shows a plan view of the top of an AESA microchip system having a package level package (e.g., using a surface mount package) and implementing illustrative embodiments of the invention. 
         FIG. 4  schematically shows a plan view of an alternative AESA microchip having a wafer level package, as well as a cross-sectional view of the same microchip flip-chip mounted on a printed circuit board, in accordance with yet another embodiment of the invention 
         FIG. 5  schematically shows several transmission line structures that may be used with various embodiments of the invention. 
         FIG. 6  graphically shows simulation data of the projected performance of various embodiments that RF ground the seal ring and crackstop ring. This performance is compared with systems that do not RF ground those rings. 
     
    
    
     DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     In illustrative embodiments, a high-frequency microchip system positions interface pads on a flip-chip mounted microchip to optimize thermal performance. To that end, selected interface pads of the microchip may be grouped away from the periphery of the microchip to thermally communicate with a heat sink on a printed circuit board to which the microchip is flip-chip mounted. Those interface pads may include ground pads, or power pads (e.g., receiving input voltage, such as Vdd). 
     In addition or alternatively, the microchip also configures its seal ring and/or crackstop ring to minimize RF interference with its signal pads. To that end, the rings both preferably are RF grounded in multiple locations as a function of anticipated wavelengths of signals processed by the microchip. More specifically, one or both of the rings preferably are grounded in multiple locations about their peripheries in a manner that effectively RF grounds the ring(s) for anticipated signal wavelengths. To further mitigate noise, the high frequency signal pads preferably have a ground pad adjacent to two of its sides. 
     In either case, the microchip may use a wafer level chip-scale package to flip-chip bond with the noted printed circuit board. Other embodiments, however, may use a package level package, such as a quad flat no-leads package. Details of illustrative embodiments are discussed below. 
       FIG. 1  schematically shows an active electronically steered antenna system (“AESA system  10 ”) configured in accordance with illustrative embodiments of the invention and communicating with an orbiting satellite  12 . A phased array implements the primary functionality of the AESA system  10 . Specifically, as known by those skilled in the art, the phased array forms one or more of a plurality of electronically steerable beams that can be used for a wide variety of applications. As a satellite communication system, for example, the AESA system  10  preferably is configured operate at one or more satellite frequencies. Among others, those frequencies may include the Ka-band, Ku-band, and/or X-band. 
     The satellite communication system may be part of a cellular network operating under a known cellular protocol, such as the 3G, 4G, or 5G protocols. Accordingly, in addition to communicating with satellites  12 , the AESA system  10  may communicate with earth-bound devices, such as smartphones or other mobile devices, using any of the 3G, 4G, or 5G protocols. As another example, the satellite communication system may transmit/receive information between aircraft and air traffic control systems. Of course, those skilled in the art may use the AESA system  10  (implementing the noted phased array) in a wide variety of other applications, such as broadcasting, optics, radar, etc. Some embodiments may be configured for non-satellite communications and instead communicate with other devices, such as smartphones (e.g., using 4G or 5G protocols). Accordingly, discussion of communication with orbiting satellites  12  is not intended to limit all embodiments of the invention. 
     For additional information regarding various embodiments of the AESA system  10 , see co-pending U.S. patent application Ser. No. 15/267,689, filed Sep. 16, 2016, and assigned to Anokiwave, Inc. of San Diego, Calif., the disclosure of which is incorporated herein, in its entirety, by reference. 
     The AESA system  10  of  FIG. 1  uses beamforming microchips to control, transmit, and/or receive RF signals.  FIG. 2  schematically shows upper and lower views of a microchip system  14  implemented in an AESA system  10  and configured in accordance with one embodiment of the invention. Specifically, the upper view shows the bottom surface of a microchip  16  having RF circuitry (not shown). This view is considered to be the bottom surface because when it is mounted to a printed circuit board  18  (lower view), it faces downwardly. Reference to that surface as a top or bottom surface is for convenience only and not intended to limit various embodiments. 
     In addition to showing features of the top surface of the microchip  16 , however, this upper view also shows features of the printed circuit board  18  (e.g., metal  22 ) as well as solder balls  20 . The lower view shows a cross-sectional view of the microchip  16  flip-chip mounted on the prior noted printed circuit board  18 , which has top-side metal  22  and a bottom side heat sink or heat spreader (collectively referred to as a “heat sink  24 ”). The heat sink  24  can be any of a variety of heat sinks known in the art. Some embodiments may augment the cooling effect by using a fan (not shown) to convectively cool the heat sink  24 . 
     The drawings have text calling out various features of the microchip  16  and the printed circuit board  18 . Specifically, the printed circuit board  18  has a plurality of metal lines/ports on its top surface for communicating signals with the microchip  16 . Among others, those lines include digital communication lines D 1  and D 2 , and RF lines, shown as Ports A, B, C 1 , C 2 , C 3 , and C 4 . Ports A, B, C 1 -C 4 , for example, may carry high frequency signals to communicate with the satellite  12  of  FIG. 1 . Those signals may include microwave-wave frequencies (300 MHz and 30 GHz) and/or millimeter-wave (30 GHz to 300 GHz) frequencies. Each of these lines couples with microchip pads (generally referred to using reference number “26”) through the solder balls  20  (or other conductor, such as copper pillars) between the microchip pads  26  and those lines. Those microchip pads  26  that communicate RF signals, shown in the lower view because they are blocked in the figures by the PCB metal  22 , may be referred to as “signal pads  26 B.” 
     The printed circuit board  18  has a plurality of vias  28  extending through its body to thermally and electrically couple between the noted heat sink  24  on the bottom PCB surface, and a large metal pad  22  (or, alternatively, a plurality metal pads  22 ) on the top PCB surface.  FIG. 2  shows the vias  28  in the upper view as circles with several interior hatched angled lines. The upper view also shows those vias  28  as within larger circles having a dotted pattern—solder balls  20 . Of course, as shown in the lower view, the solder balls  20  are physically above the vias  28  from the perspective of the figures. 
     In accordance with illustrative embodiments of the invention, a set of static pads  26 A (i.e., pads that transmit a static signal or no signal, such as a DC power signal or ground—they do not transmit RF signals) are concentrated in an inner region of the top microchip surface. In illustrative embodiments, those static pads  26 A are ground pads, which also will be referred to using reference number “ 26 A.”  FIG. 2 , for example, shows a 4×3 array/set of 12 ground pads  26 A in that inner region. Indeed, various embodiments may have more or fewer than 12 ground pads  26 A. Accordingly, like other features shown in this figure, specific locations and numbers of certain elements are illustrative and not intended to limit all embodiments. 
     This inner set of ground pads  26 A is circumscribed by a plurality of other interface pads  26  on the microchip  16 . These other interface pads  26  may include one or both signal pads  26 B (e.g., for communicating RF signals) and/or additional ground pads  26 A. Accordingly, some or all of the signal pads  26  on the microchip  16  preferably have no other pads  26 A or  26 B between it and at least one edge of the microchip  16  and thus, are considered to be “adjacent” to the edge of the microchip  16 . It should be pointed out that, as shown in the figures, circumscribing does not imply that there is a continuous barrier of interface pads  26  around the inner set of pads  26 A. 
     The inner ground pads  26 A preferably do not electrically connect with other, more peripheral/radially outwardly positioned ground pads  26 A and  26 B through the top surface metal  22  of the printed circuit board  18 . In a similar manner, the inner ground pads  26 A may not electrically connect to the RF circuitry. Instead, as discussed below, these ground pads  26 A simply conduct heat away from the region near the RF circuitry or the RF circuitry itself. They do not ground a circuit. Other embodiments, however, couple these ground pads  26 A with the RF circuitry. 
     Some or all of the RF signal pads  26 B preferably have a ground pad  26 A adjacent to two of its opposing sides. For example, Port C 2  has a ground pad  26 A adjacent to its right side, and another ground pad  26 A adjacent to its left side. No other pads  26 A or  26 B are between Port C 2  and those two ground pads  26 A. The inventors recognized that using a configuration such as this further mitigates noise and cross-talk between RF interfaces/pads  26 B at high frequencies, such as in the microwave and millimeter-wave frequencies. 
     Other embodiments may position a third ground pad adjacent to another side of the signal pad, or position two ground pads  26 A at a different angular position relative to the other ground pad. For example, rather than being 180 spaced apart (e.g., like the ground pads  26 A around Port C 2 ), some embodiments may angularly space the two ground ports to be 120 degrees apart or 90 degrees apart. These configurations of signal pads  26 B and ground pads  26 A may be generally referred to as a “GSG pad arrangement.” 
     High frequency RF circuitry undesirably generates a lot of waste heat. If not properly managed, this waste heat can affect performance, and even damage the microchip  16 . The inventors recognized that heat generated by the functional elements of the microchip  16  (e.g., the RF circuitry) may be routed through the printed circuit board  18  and to the heat sink  24  through the vias  28 . Moreover, rather than spreading them out across the printed circuit board  18 , these thermal management ground vias  28  can be clustered, as shown in  FIG. 2 , to produce a relatively large thermal mass that more readily cools the microchip circuitry. These vias  28  can be filled or unfilled. 
     When coupled with the printed circuit board  18 , the microchip ground pads  26 A contact the solder balls  20 , which in turn contact top surface, exposed PCB metal  22  on the printed circuit board  18 . This top surface PCB metal  22  may be a single mass, or a single interrupted, discontinuous mass of surface metal  22 . Accordingly, the inventors clustered the top surface PCB metal  22  and vias  28  in a central location and in a relatively large volume to more easily route the heat away from the functional elements. This cluster produces the noted large thermal mass that more readily conducts heat to the heat sink  24 . Two or more adjacent ground vias  28  in the interior of the printed circuit board  18  may be considered to be a “cluster.” In a similar manner, two or more adjacent ground pads  26 A on the interior of the microchip  16  also may be considered to be a cluster. These clusters may have 3, 4, 5, 6 or some other number of elements and preferably is in the form of a two-dimensional array (e.g., as shown in  FIG. 2 ). 
     Simulations of various embodiments implementing similar designs have shown a significantly lower temperature rise that those of prior art microchip systems without such a cluster. One simulation, for example, showed a 10 degree temperature rise in a microchip system  14  implementing an embodiment of the invention, while a prior art microchip system showed a 60-70 degree temperature rise. Indeed, these results are preliminary and could change depending on the situation and implementation. 
     The microchip  16  also has a plurality of rings  32  that both (i.e., together) protect the functional elements of the microchip  16  and minimize cracking during the fabrication process. Specifically, the microchip  16  has a seal ring  32  circumscribing the microchip pads  26 , and a crackstop ring  32  radially outward of the seal ring. Both rings  32  preferably are formed from metal and extend from the surface into the microchip  16 . Although referred to as “rings,” they are not necessarily circular or elliptical. For example,  FIG. 2  shows the rings  32  as being rectangular. Other embodiments may be square, pentagonal, irregularly shaped, or some other shape. Some embodiments may have a break in one or both of the rings  32 . As such, the rings  32  would be discontinuous but still circumscribe pads  26  and the RF circuitry. 
     More particularly, as known by those skilled in the art, during the wafer dicing process, the microchip  16  can develop a crack that can degrade and possibly render the microchip  16  nonfunctional. The crackstop ring  32  therefore acts as a barrier to mitigate such a crack from permeating into the microchip  16 . Preferably, the crackstop ring  32  acts as a physical block to prevent a crack from extending radially inwardly into the microchip  16  (i.e., beyond the crackstop ring). 
     In addition, as also known by those skilled in the art, contaminants also can adversely affect the functional elements of the microchip  16 . Accordingly, the seal ring  32  acts as a substantial barrier to mitigate or prevent contaminants, such as ions and moisture, from reaching the functional blocks of the microchip  16  (e.g., to protect the RF circuitry). 
     One or both of the two rings  32  may be DC grounded, but often, in the prior art, they may not be RF grounded (i.e., grounded with regard to RF signals). Accordingly, one or both of the prior art rings may be considered to be RF floating. This is particularly problematic with an AESA microchip  16  (e.g., a microchip  16  used in the AESA system  10  of  FIG. 1 ) because one or both floating rings can interfere with the incoming or outgoing high-frequency RF signals in the lines of the PCB and the RF pads  26 B of the microchip  16 . Among other frequencies, the rings undesirably can produce resonances at microwave and millimeter-wave frequencies—the very wavelengths commonly used for AESA systems. For example, such an undesired resonance can occur when the rings have a length of more than about half the order of the wavelength of RF signals transmitted and/or received by the microchip  16 . Although such resonance typically has a low quality factor, it may couple paths between RF lines/pins/interfaces. The inventors overcame this problem by appropriately RF grounding the two rings  32 . 
       FIG. 3A  schematically shows one embodiment in which the seal ring  32  and the crackstop ring  32  both are RF grounded. To that end, a plurality of the ground pads  26 A of the microchip  16  are electrically connected directly to the two rings  32 . In illustrative embodiments, metal  34  on the bottom surface of the microchip  16  makes that electrical connection.  FIG. 3A  shows some of those connections at various locations using reference number  34 . One skilled in the art can select the appropriate locations for grounding each of the rings  32  to ensure that in addition to being DC grounded, each of the rings  32  is RF grounded. In this example, each of the rings  32  is RF grounded on one or more points along each of its sides (assuming the ring  32  is rectangular in shape). For example, the locations can be spaced apart from each other in equidistant and non-equidistant points from between 0.1 times and 2.0 times the wavelength of the RF signals of the microchip  16 . As noted, this preferably eliminates or mitigates parasitic resonances caused by the rings  32 . 
     Rather than using the direct RF grounding of  FIG. 3A , other embodiments may RF ground the rings  32  with other techniques. For example, some embodiments may capacitively couple the ring(s) to one or more of the lines, such as the digital lines D 1 , D 2 . 
     It should be noted that  FIG. 3A  shows the microchip system  14  as having both the thermal benefits of  FIG. 2 , as well as the interference mitigation benefits immediately discussed above. Various embodiments, however, may implement the microchip system  14  with just one of those improvements. For example, the microchip system  14  may have just the improvement for mitigating interference (e.g., an appropriate RF grounding with a GSG pad arrangement). As another example, the microchip system  14  may have just the improvement for improving thermal performance. Accordingly, while the microchip system  14  of  FIG. 3A  may have an improved overall performance because it implements the two noted improvements, those skilled in the art can select one of those improvements. 
     Various embodiments also apply to microchip systems  14  that are not packaged at the wafer level.  FIG. 3B , for example, shows another embodiment that RF grounds the ring(s) using a package level package having package pads  37 . In this example, the package is a quad flat no-leads package (“QFN package  36 ”). As known by those in the art, a QFN package  36  is a surface mountable package in which the microchip  16  is coupled with a conductive leadframe. 
     Specifically,  FIG. 3B  schematically shows a top view of a packaged microchip  16  (microchip system  14 ) with a portion of package encapsulation material removed to better view the microchip  16 . As with the microchip  16  of  FIG. 3A , this microchip  16  also has one or more seal rings  32  and/or crackstop rings  32 , a plurality of ground pads  26 A, and a plurality of signal pads  26 B. In a corresponding manner, the package has a leadframe forming ground pads  26 A and signal pads  26 B. Bond wires  27  electrically connect 1) the ground pads  26 A of the microchip  16  to the ground pads  26 A of the package, and 2) the signal pads  26 B of the microchip  16  to the signal pads of the package. The microchip system  14  has a plurality of other elements (some labeled in the drawing), such as through silicon vias  28 , a molded body, and a die paddle/ground paddle  39  to which the microchip  16  may be coupled. 
     In accordance with illustrative embodiments, and as with the embodiment of  FIG. 3A , select ground pads  26 A are extended radially outwardly (e.g., using metal  34  on the microchip  16 ) to electrically and physically contact one or both of the rings  32 .  FIG. 3B  shows some of those metal connection locations at reference number  34 . One skilled in the art can select the appropriate locations to provide the RF ground. As suggested above, the connections preferably are spaced apart at much smaller intervals than about half the wavelength of anticipated signals to be transmitted and/or received. Bond wires  27  electrically connect each of those selected ground pads  26 A with a ground source, such as the die paddle of the package and/or one of the ground pads  26 A of the package. 
     Structure other than or in addition to the microchip ground pads  26 A can also RF ground one or both of the rings  32 .  FIG. 3B , for example, also shows a through-silicon via (“TSV  38 ”), on the microchip  16 , coupled with ground (e.g., though the die paddle) that connects one or both of the rings  32  to ground. Although only one such TSV  38  connection is shown, those skilled in the art can use two or more as required by the application. 
     Indeed, although QFN packages  36  are discussed above, various embodiments apply to other types of packages used to protect microchips on the package level. For example, in addition to flat packages, illustrative embodiments also may apply to microchip systems  14  using through-hole packages and chip carriers. Accordingly, discussion of QFN packages  36  is merely an example and not intended to limit all embodiments. 
       FIG. 4  schematically shows another embodiment using another type of static interface/pad to manage the thermal profile of the microchip  16 . More specifically, the inner ground pads  26 A circumscribe a plurality of other static interface pads  26 A that also provide the noted thermal benefit. This arrangement thus uses two separate thermal paths that each leads to two separate heat spreading planes on the PCB. In addition, this arrangement also enables some pads used as ground pads  26 A in  FIG. 3A  now to be used as input voltage pads  26 A. Accordingly, such an arrangement should enable a pin count reduction and enable use of a smaller microchip/package. 
     As shown, this plurality of other interface pads  26 A may be considered to form an island of/another set of other pads  26 A. Specifically, in this embodiment, the other plurality of interface pads  26 A are input voltage pads  26 A (e.g., Vdd). Indeed, these two sets of pads  26 A are electrically isolated from each other, and preferably are positioned as close to each other as possible to minimize the footprint of the microchip  16  while increasing the number of pads  26 A used to provide the noted thermal benefit. 
     As shown in the lower view of  FIG. 4 , vias  28  thermally extend from the PCB input voltage pads  26 A to the heat sink  24 . The inner ground pads  26 A (i.e., radially outward of the input voltage pads  26 A), however, connect to another metal sheet  22 A within the printed circuit board  18  that ultimately also acts as a heat sink or heat spreader. Accordingly, as with the embodiment of  FIG. 2 , both the inner ground pads  26 A and input voltage pads  26 A effectively conduct heat away from the functional elements of the microchip  16 . 
     Other embodiments may orient the two sets of pads  26 A of  FIG. 4 —the inner ground pads  26 A and the input voltage pads  26 A—in an opposite manner. Specifically, other embodiments may have a plurality of inner input voltage pads  26 A that circumscribe a plurality of inner ground pads  26 A. In other words, the arrangement of  FIG. 4  may simply substitute the inner ground pads  26 A with input voltage pads  26 A, and substitute the inner voltage pads  26 A with inner ground pads  26 A. 
     Those skilled in the art may use any of a variety of different transmission structures with the microchip system  14 .  FIG. 5 , For example, schematically shows several transmission line structures that may be used with various embodiments of the invention. Specifically, those different transmission line structures may include a micros trip  40 , a strip line  42 , and/or a coplanar waveguide  44  (CPW). Of course, those in the art may select transmission line structures other than those shown. 
     The inventors simulated an embodiment of the invention that RF grounded the rings  32  to determine the RF isolation between the ports identified in  FIG. 3A  as “Port A” and “Port B.” This was compared with a similar microchip device that did not RF ground the rings  32 .  FIG. 6  shows the output of that simulation. Specifically,  FIG. 6  shows the amount of isolation between the ports as a function of frequency for the two compared microchips. In this graph, −70 dB is the most favorable isolation, while zero dB is the least favorable isolation. As shown, the simulated RF grounded microchip  16  with RF grounded ring(s) appears to have an isolation of less than about −40.0 dB across all frequencies of between zero and 40 GHz. In contrast, the simulated microchip without the RF grounded ring(s) is effectively unusable at about 40 GHz, and appears to have significantly more interference at frequencies greater than about 8 to 10 GHz. 
     To form the system, a fabrication method may simply flip-chip mount the microchip  16  on the printed circuit board  18  using conventional flip-chip techniques. This may include forming the solder balls  20  over the vias  28  on the printed circuit board  18 , adding under-fill material  46 , placing the microchip  16  on the solder balls  20 , and then placing the printed circuit board  18  in a re-flow oven. In illustrative embodiments, when secured together, the flip-chip mounting forms a conductive thermal connection extending from:
         the RF circuitry, through the static pads  26 A/interfaces (e.g., the centrally located static pads  26 A/interfaces of the microchip  16 , such as the power pads  26 A or ground pads  26 A),   the solder balls  20 ,   the vias  28  in the printed circuit board  18 , and   ultimately to the heat sink  24  or spreader.       

     Accordingly, illustrative embodiments position static pads  26 A on the microchip  16  and printed circuit board metal  22  to better thermally manage a flip-chip microchip system  14 . In addition or alternatively, other embodiments may RF ground the seal ring  32  and/or crackstop ring  32  and employ a GSG pad arrangement to mitigate cross-talk and interference between high-speed RF microchips  16  having multiple signal interfaces. 
     Although the above discussion discloses various exemplary embodiments of the invention, it should be apparent that those skilled in the art can make various modifications that will achieve some of the advantages of the invention without departing from the true scope of the invention.