Patent Publication Number: US-2012026807-A1

Title: Semiconductor memory chip and integrated circuit

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2010-0028716, filed on Mar. 30, 2010, in the Korean intellectual property Office, which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     A semiconductor package refers generally to a packaged semiconductor memory chip with fine circuits sealed with a mold resin or ceramic for protection from external environments and mounting on an integrated circuit. Additional emphases were also put on the semiconductor packaging design to improve the performance and quality of the integrated circuit through compactness, slimness, and multi-functionality. 
     Achieving all of compactness, slimness, and multi-functionality of electronic devices requires reducing the size while increasing the capacity of a semiconductor chip. One suitable technique is known as a chip scale packaging, which requires that the package must have a size no greater than 1.2 times the size of the semiconductor memory chip. Other areas of interest in the semiconductor packaging focus on increasing capacity and processing speed of a semiconductor package. 
       FIG. 1  shows a conventional integrated circuit including a semiconductor memory chip formed in a semiconductor package. 
     In the conventional integrated circuit of  FIG. 1 , data outputted from the semiconductor memory chip in a semiconductor package are transferred to a first transmission line TL 1  and a second transmission line TL 2  through a first package data line PDL 1  and a second package data line PDL 2  formed in the package area. Since the first and second transmission lines TL 1 , TL 2  have equivalent inductances, a mutual inductance ML occurs between the first and second transmission lines TL 1 , TL 2 . The mutual inductance ML causes signal noise due to crosstalk in the data signal transferred through the first and second transmission lines TL 1 , TL 2 . 
     To solve this problem, the conventional integrated circuit utilizes a coupling capacitor CP between the first and second package data lines PDL 1 , PDL 2  in order to offset the mutual inductance ML between the first and second transmission lines TL 1 , TL 2 . However, the coupling capacitor CP has an equivalent series inductance ESL, which serves as a limiting factor of the integrated circuit operating in a wide bandwidth. 
     SUMMARY 
     An embodiment of the present invention provides a semiconductor memory chip and an integrated circuit, which are capable of operating in a wide bandwidth by providing a coupling capacitor implemented with a MOS transistor within the semiconductor memory chip. 
     In an embodiment, a semiconductor memory chip includes: a driving voltage reception unit configured to receive a power supply voltage and a ground voltage; a first data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive first data to output the driven first data through a first data line; a second data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive second data to output the driven second data through a second data line; and a MOS transistor coupled between the first data line and the second data line. 
     In another embodiment, an integrated circuit includes: a semiconductor memory chip in which a MOS transistor operating as a coupling capacitor is coupled between first and second data lines through which first and second data are outputted; and first and second package data lines provided in a package area of the semiconductor memory chip and configured to transfer data from the first and second data lines to first and second transmission lines which are coupled to a memory control unit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects, features and other advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  shows a conventional integrated circuit including a semiconductor memory chip in which a semiconductor package is formed; 
         FIG. 2  shows an integrated circuit according to an embodiment of the present invention; 
         FIG. 3  is a circuit diagram of the integrated circuit shown in  FIG. 2 ; and 
         FIG. 4  is a waveform diagram for explaining signal noise attenuation effect of the integrated circuit shown in  FIG. 2 . 
     
    
    
     DESCRIPTION OF SPECIFIC EMBODIMENTS 
     Hereinafter, embodiments of the present invention will be described with reference to accompanying drawings. However, the embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. 
       FIG. 2  illustrates a structure of an integrated circuit according to an embodiment of the present invention, and  FIG. 3  is a circuit diagram of the integrated circuit illustrated in  FIG. 2 . 
     Referring to  FIG. 2 , the integrated circuit according to an embodiment of the present invention includes a semiconductor memory chip  1 , first and second package data lines PDL 1 , PDL 2  in a package area, and first and second transmission lines TL 1 , TL 2  outside the package area. Data are transferred from the semiconductor memory chip  1  to a memory control unit  2  through the first and second package data lines PDL 1 , PDL 2  and the first and second transmission lines TL 1 , TL 2 , respectively. 
     The semiconductor memory chip  1  includes a driving voltage reception unit  10 , a data driving unit  11 , and a coupling capacitor  12  coupled between first and second data lines DL 1 , DL 2 . 
     The driving voltage reception unit  10  is configured to receive a power supply voltage VDD and a ground voltage VSS through a first power line PL 1  and a second power line PL 2 , respectively, in the package area. The driving voltage reception unit  10  is also configured to provide the received voltages VDD and VSS to the data driving unit  11 . The first and second power lines PL 1 , PL 2  have inductances in the lines, and their equivalent inductances are represented as L 10 , L 11 , respectively, in  FIG. 3 . 
     Referring back to  FIG. 2 , the power supply voltage VDD is supplied to the data driving unit  2  from the first power line PL 1  and correspondingly through a first internal power line IPL 1 . Likewise, the ground voltage VSS is supplied to the data driving unit  2  from the second power line PL 2  and through a second internal power line IPL 2 . As shown in  FIGS. 2-3 , the data driving unit  11  drives first and second data DATA 1 , DATA 2  to output through the first and second data lines DL 1 , DL 2 , respectively. More specifically, referring to  FIG. 3 , the data driving unit  11  includes first and second data drivers DRV 1 , DRV 2 . The first data driver DRV 1  is configured to receive a first pull-up signal PU 1  and a first pull-down signal PD 1  and drive the first data DATA 1 , and the second data driver DRV 2  is configured to receive a second pull-up signal PU 2  and a second pull-down signal PD 2  and drive the second data DATA 1 . The equivalent resistances in the first and second internal power lines IPL 1  and IPL 2  are represented as first and second resistors R 10 , R 11 , respectively. 
     The coupling capacitor  12  is implemented with an NMOS transistor with its source and drain coupled to the first data line DL 1  and its gate coupled to the second data line DL 2 . Alternatively, the coupling capacitor  12  may be formed by coupling the source and drain of the NMOS transistor to the second data line DL 2  and the gate to the first data line DL 1 . 
     Since the coupling capacitor  12  is implemented with the NMOS transistor, an equivalent series inductance (ESL) does not occur as opposed to the conventional coupling capacitor formed in the package area. Consequently, the integrated circuit to which the coupling capacitor  12  is applied according to an embodiment of the present invention may be stably operated in a wide bandwidth. 
     The equivalent resistances of the first and second package data lines PDL 1 , PDL 2  are represented with third and fourth resistors R 12 , R 13 , respectively. The equivalent inductances of the first and second package data lines PDL 1 , PDL 2  are represented with third and fourth inductors L 12 , L 13 . 
     The coupling capacitor  12  having the NMOS transistor in the integrated circuit according to an embodiment of the present invention may control the capacitance in units of several pF by adjusting the width and length of the gate. Therefore, by adjusting the capacitance of the coupling capacitor  12 , it is possible to attenuate signal noise generated by crosstalk between the data signals transferred through the first and second transmission lines TL 1 , TL 2 . 
     As shown in  FIG. 4 , in the case X when the coupling capacitor  12  is not implemented, overshooting occurs in the waveform of the data signals transferred through the first and second transmission lines TL 1 , TL 2 . On the contrary, in the case Y when the coupling capacitor  12  is implemented in the integrated circuit according to an embodiment of the present invention, overshooting of X is quite improved. 
     The embodiments of the present invention have been disclosed above for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.