Patent Publication Number: US-7904667-B2

Title: Systems and methods for monitoring and controlling binary state devices using a memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation-in-part of U.S. patent application Ser. No. 10/992,428, filed Nov. 17, 2004, which is hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     Generally, the invention relates to static random access memories (SRAMs). More specifically, the invention relates to multi-port SRAMs that include input read registers and output drive registers for controlling and monitoring binary state devices. 
     2. Description of the Related Art 
     Microprocessors and microcontrollers have become a ubiquitous part of everyday life. They can be found in virtually all types of products available today: from transportation and manufacturing equipment, to consumer electronics, household appliances and children&#39;s toys. Processors control and monitor all or part of the functionality of these products using their general-purpose input/output (GPI/O) connections. This control can typically include such things as turning binary devices on and off for functional signaling to an end-user (e.g., toggling light emitting diode power to indicate whether a product is on or off, etc.) and monitoring the state of binary devices for system oversight (e.g., checking switch state to see whether a certain product function has been selected). 
     However, the number of GPI/O connections available for any given microprocessor or microcontroller is limited by, among other factors, the physical size of the processor. As the system demands on the GPI/O connections increase in number, a system designer is forced to choose between competing demands, selecting some at the expense of others. If the system designer desires to facilitate more demands than a processor&#39;s GPI/O connections can accommodate, the system designer must include external circuitry or use external input/output (I/O) processors to handle the overflow or excess demands. Both of these I/O overflow solutions are time, space, power and cost inefficient. 
     Also used within the typical microcontroller system of today is a random access memory (RAM), particularly a static RAM, or SRAM. An SRAM is a type of read/write memory that holds its data, without external refresh, for as long as power is supplied to it. An SRAM is typically used as external cache memory for processors and controllers. Cache memory is commonly used to store and retrieve commands, instructions and/or data that are frequently needed or used by the processor. In some applications, an SRAM can also be used as the main memory of a processor. An SRAM capable of interfacing with multiple processors, for example as cache memory and/or main memory, is commonly known as a multi-port SRAM (e.g., a dual-port device interfaces with two processors, etc.). 
       FIG. 1  illustrates a typical block diagram for a system  100  with multiple processors that control and/or monitor binary state devices  190 , among other functions, and that access a multi-port SRAM  150 . As shown in  FIG. 1 , N processors  111 - 113  are each connected to N ports  121 - 123 , respectively, of the multi-port SRAM  150 . Each of the N processors  111 - 113  is further connected to a variety of binary state devices  190  using the processors&#39; GPI/O connections (not shown). The typical command within a processor to control a binary state device is a read/write to the GPI/O port that is coupled to that device. As an example of a limitation of the system in  FIG. 1 , assume that there are nine binary state devices  190 . Further assume that N equals 3 and that each of three processors  111 - 113  has three GPI/O connections. In this case, all nine of the binary state devices  190  can be controlled or monitored by the processors  111 - 113  (i.e., each of the three processors  111 - 113  can be connected to three of the nine binary state devices  190 ). 
     However, with continued reference to  FIG. 1 , consider a further example where the number of binary state devices  190  in the system  100  exceeds the cumulative number of GPI/O connections for all of the N processors  111 - 113  (e.g., N equals one, total number of GPI/O equals three and the number of devices equals four). In this example, either additional, external means for controlling and/or monitoring the excess device(s) must be added to system  100 , or the excess device(s) must be eliminated from the system  100 . As previously discussed, adding external circuitry, such as external input/output (I/O) processors, to system  100  for handling the excess device(s) is time, space, power and cost inefficient. Likewise, excluding a binary state device  190  from control by the processors  111 - 113  may not be an option based on customer demands and system requirements. 
     Thus, what is needed is an external means for one or more processors to control and/or monitor binary state devices without adding additional circuit elements to the processor-based system, thus freeing up or expanding the functionality of the processors&#39; GPI/O connections. 
     SUMMARY OF THE INVENTION 
     A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to ground. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations. The memory device may also include one or more settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR. 
     A method according to aspects of the invention can be used for controlling states of external binary devices coupled to a memory device. This exemplary method can include a step for coupling one or more processors to the memory device. Another step can read, using the processors, to a first memory location of the memory device, wherein the first memory location includes at least one bit that reflects a first state of a first external binary device. A further step can read, using the processors, to a second memory location of the memory device, wherein the second memory location includes at least one bit that reflects a second state of a second external binary device. The method can include an additional step for writing, using the processors, to the second memory location of the memory device, wherein the bit of the second memory location controls the change of the second state to a third state of the second external binary device. The method may include setting one or more controlling bits and determining, based on the controlling bits, which controlled register bits will reflect the state of a first external binary devices. 
     A further method according to aspects of the invention can be used for controlling states of external binary devices coupled to a memory device. This exemplary method includes a means for coupling processors to the memory device, a means for monitoring a first state of a first external binary device, and a means for manipulating a second state of a second external binary device. This method may include determining, based on the one or more controlling bits, which bits from a set of controlled register bits will be used to control the states of external binary devices coupled to the memory device. 
     A system for controlling and monitoring one or more binary state devices can include a multi-port memory device and a plurality of processors. The multi-port memory device can include a memory array coupled to a plurality of ports, the memory array having a plurality of memory locations, each memory location associate with a memory address. The multi-port memory device can include one or more input read registers and one or more output drive registers. The memory device may further include settable controlling bits and a set of controlled register bits. Setting the controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR. Each input read register can be associated with a first memory address and can be coupled to a first set of binary state devices and can have a corresponding first set of input read register bits, such that each first set bit is capable of reflecting a state of each corresponding first set device. Each output drive register can be associated with a second memory address and can be coupled to a second set of the binary state devices and can have a corresponding second set of output drive register bits, such that each second set bit is capable of reflecting a state of each corresponding second set device and is further capable of controlling the state of each corresponding second set device. Additionally, the plurality of processors can be coupled to the plurality of ports, wherein each processor is capable of executing an instruction that reads to the first memory address, and reads and writes to the second memory address. 
     Additional aspects of the invention will be set forth in part in the detailed description which follows, and in part will be apparent from this disclosure, or may be learned by practice of the invention. The aspects of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other aspects and features of the invention will become apparent to those ordinarily skilled in the art upon review of the following detailed description of specific embodiments of the invention in conjunction with the accompanying figures, wherein: 
         FIG. 1  illustrates a typical block diagram for multiple processors that control and/or monitor binary devices, and that each access a multi-port SRAM; 
         FIG. 2  illustrates a generalized multi-port static random access memory (SRAM) according to some embodiments of the invention; 
         FIG. 3  illustrates a dual-port SRAM according to some embodiments of the invention; 
         FIG. 4  illustrates a two-device Input Read Register (IRR) of a dual-port SRAM according to some embodiments of the invention; 
         FIG. 5  illustrates a five-device Output Drive Register (ODR) of a dual-port SRAM according to some embodiments of the invention; and 
         FIG. 6  illustrates a functional block diagram with signal routing for a dual-port SRAM according 
         FIG. 7  illustrates a block diagram of a module of a memory device that specifies which bits are associated with input read registers and output drive registers. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The invention will now be described in detail with reference to the drawings, which are provided as illustrative examples of the invention so as to enable those skilled in the art to practice the invention and are not meant to limit the scope of the invention. Where certain elements of the invention can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the invention will be described, while detailed descriptions of other portions of such known components will be omitted so as to not obscure the invention. Further, the invention encompasses present and future known equivalents to the components referred to herein by way of illustration. 
       FIG. 2  illustrates a generalized multi-port static random access memory (SRAM) according to some embodiments of the invention. As shown in  FIG. 2 , the multi-port SRAM  250  includes N ports  121 - 123  that are coupled to N processors  111 - 113 , respectively. As used herein, the terms processor, controller, microprocessor and microcontroller generally indicate any type of computing device or combination of devices (e.g., electronic, optical, organic, discrete, highly-integrated, etc.) capable of executing an instruction set (e.g., reduced instruction set, complex instruction set, etc.) that at least includes a read instruction and a write instruction to a memory device. Each term, whether used in the singular or plural form, is meant to indicate one or more of such computing devices or combinations of devices. 
     The exemplary multi-port SRAM  250  also includes one or more input read registers  230  and one or more output drive registers  260 . Input read registers  230  and output drive registers  260  allow for monitoring and controlling binary state devices  190  by any of the N processors  111 - 113  through the standard interface between processors  111 - 113  and ports  121 - 123  of the multi-port SRAM  250 . Any of the N processors  111 - 113  can access input read registers  230  and output drive registers  260  by simply reading or writing to the memory address associated with the register. Once a read or write request is detected to one of these registers and the appropriate read enable or write enable signal is set (discussed in further detail below), the requesting processor will be allowed to read or write to the appropriate register, thereby monitoring or controlling the binary state devices  190 . When not set to control or monitor binary state devices  190 , the addresses used for the input read registers  230  and output drive registers  260  of the present invention can be used by the SRAM main memory array for standard memory operations. The inclusion of the input read register (IRR)  230  and the output drive register (ODR)  260  frees up the processor general-purpose input/output (GPI/O) connections, or pins, for other or additional tasks, and does so without forcing the system designer to include additional I/O-handling circuitry in the design; an SRAM can be there anyway. 
     Some embodiments of the invention utilize the dual-port SRAM.  FIG. 3  illustrates a dual-port SRAM according to some embodiments of the invention. As shown in  FIG. 3 , two processors  111 , 112  can simultaneously utilize the dual-port SRAM  350 . The embodiments illustrated include an input read register (IRR)  330  that can capture the state of external binary state devices  340 , for example two external devices, and make their states available to either processor  111 , 112 . The illustrated embodiments further include an output drive register (ODR)  360  that can control and monitor the state of external binary state devices  370 , for example five external devices, and make this control and status available to either processor  111 , 112 . In some embodiments, for example, the two sets of external binary state devices  340  and  370  can include one or more of the same external binary devices; while in other embodiments, the two sets can be mutually exclusive. It will be evident to those skilled in the art after review of this disclosure that these embodiments can be readily modified for more or less than two processors, more or less than one IRR and/or one ODR, and a varying number of external binary state devices. Such modifications are intended to be within the scope of the present invention. 
     In some embodiments, IRR  330  of the invention can capture the status, or states, of external binary state devices  340  (e.g., switches, etc.) that are connected to the input read pins of dual-port SRAM  350 . IRR  330  can be given memory address x 0000 , although other addresses can be assigned without deviating from the scope of the invention. The contents of IRR  330  can be read as a standard memory access to address x 0000  from any of the processors  111 , 112  (of which, for example only, two are shown in  FIG. 3 ) and the data can be output via standard inputs and outputs (I/Os) of SRAM  350 . For example,  FIG. 4  illustrates an example of a two-device IRR  330  of the dual-port SRAM  350  according to some embodiments of the invention. 
     The embodiment of dual-port SRAM  350  shown in  FIG. 4  includes IRR  330 , which can be a 16-bit memory location at memory address x 0000 . However, embodiments of the invention are equally applicable to memories of any bit-size. The SRAM  350  can utilize bit  0  (IRR 0 ) and bit  1  (IRR 1 ) of IRR  330  to monitor the status of, for example, two external binary state devices: device  1   441  and device  2   442 , respectively. The address used by IRR  330  (i.e., x 0000 ) can also be set for use by the SRAM  350  main memory array  451  for standard memory operations. Any of the processors  111 , 112  can access IRR  330 , and thus the status of devices  441 , 442 . However, it is not necessary to some embodiments of the present invention that every processor  111 , 112  be couple to IRR  330 . 
     For example, processor  1   111  can execute a read command to SRAM address x 0000  using address lines A 0L -A 12L . The states of devices  441  and  442  can be read from IRR  330  to input/output lines I/O 0L -I/O 15L  via the address and I/O control  455  of SRAM  350 . In the example shown in  FIG. 4 , device  1   441  is on, which is reflected in bit IRR 0  as being high or “1”. Likewise, device  2   442  is off, which is reflected in bit IRR 1  as being low or “0”. Processor  2   112 , can also access the states of the two devices  441 , 442  in a similar manner. 
     Table 1, below, defines the operation of embodiments of a dual-port SRAM  350  that includes an IRR  330  in accordance with the invention. As shown in Table 1, when  SFEN =V 1L , IRR  330  is active (i.e., IRR read mode is available to the processors) and address x 0000  is not available for standard memory operations. During IRR read mode of address x 0000 , I/O 0  and I/O 1  are valid bits and I/O 2  through I/O 15  are “don&#39;t care” bits. As will now be apparent to those skilled in the art, the invention can include a varying number of valid and “don&#39;t care” IRR bits. Writes to address x 0000  are not allowed from either processor port during IRR read mode because SRAM  350  mirrors the on/off status of devices  441  and  442  to IRR  330 . When SRAM  350  special function enable input (  SFEN )=V 1H , IRR  330  is inactive (i.e., standard memory mode is available to the processors) and address x 0000  can be used with the SRAM main memory array  451  for standard memory operations. This exemplary IRR  330  can support inputs up to approximately 3.5V (e.g., V 1L &lt;=˜0.4 V, V 1H &gt;=˜1.4 V). However, as will be evident to those skilled in the art upon review of this disclosure, varying input levels and alternative logic schemes for IRR  330  can also be used with aspects of some embodiments of the present invention. Such variations and alternatives are intended to be within the scope of the present invention. 
     
       
         
           
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                 Input Read Register (IRR) Operation 
               
            
           
           
               
               
               
               
               
               
               
               
               
               
            
               
                 
                   SFEN 
                 
                 
                   CE 
                 
                 R/  W   
                 
                   OE 
                 
                 
                   UB 
                 
                 
                   LB 
                 
                 ADDR 
                 I/O 0 -I/O 1   
                 I/O 2 -I/O 15   
                 Mode 
               
               
                   
               
               
                 H 
                 L 
                 H 
                 L 
                 L 
                 L 
                 x0000-Max 
                 Valid 
                 Valid 
                 Standard Memory 
               
               
                 L 
                 L 
                 H 
                 L 
                 X 
                 L 
                 x0000 
                 Valid 
                 X 
                 IRR Read 
               
               
                   
               
            
           
         
       
     
     In some embodiments, referring again to  FIG. 3 , ODR  360  of the invention can determine and manipulate the status, or states, of external binary state devices  370  (e.g., LEDs) by providing a path to V SS  and/or ground for the circuit of the external devices  370 . The status of ODR  360 , and thus external devices  370 , can be set using standard write access from any of the processors  111 , 112  to address x 0001  of SRAM  350 , with a “1” corresponding to “on” for the associated device and a “0” corresponding to “off”. The status of the ODR can also be read (without changing the status of the bits) via a standard read to address x 0001  of the SRAM  350 . For example,  FIG. 5  illustrates a five-device output drive register (ODR)  360  of a dual-port SRAM  350  according to some embodiments of the invention. 
     The embodiment of dual-port SRAM  350  shown in  FIG. 5  includes ODR  360 , which can be a 16-bit memory location at memory address x 0001 . However, embodiments of the invention are equally applicable to memories of any bit-size. SRAM  350  can utilize bit  0  (ODR 0 ) through bit  4  (ODR 4 ) of ODR  360  to control and monitor the status of, for example, five external binary state devices: device  1   571  through device  5   575 , respectively. ODR  360  can also be used as part of the regular memory array  451  of SRAM  350 . Any of the processors  111 , 112  can access ODR  330 , and thus control and monitor the state of the devices  571 - 575 . However, it is not necessary to some embodiments of the present invention that every processor  111 , 112  be couple to ODR  360 . 
     For example, processor  1   111  can execute a write command to SRAM address x 0001  using address lines A 0L -A 12L  and input/output lines I/O 0L -I/O 15L . Since, in this embodiment of dual-port SRAM  350  there are five external binary devices  571 - 575 , bits  0 - 4  of the ODR  360  (i.e., ODR 0  through ODR 4 ) can be used to control and monitor the exemplary five devices, respectively. To turn on one of the devices, the processor writes a “1” to the corresponding bit of the ODR  360  for that device. When a bit of ODR  360  is set to “1”, ODR  360  can provide a path to the SRAM  350  supply voltage(s) and/or ground (not shown) via one of two output voltages, OV SS1 , and OV SS2    581 , 581 . The number and amplitude of output supply voltage(s) can vary by application. For example, the drive voltage for this exemplary ODR  360  might be between approximately 1.5 volts and about 3.5 volts, which can limit the total current draw of all attached devices to, for example, approximately 40 milliamps (mA) total. Likewise, to turn off one of the devices, the processor writes a “0” to that device&#39;s corresponding bit of the ODR  360 , which opens the output supply voltage path for that device. 
     The status of devices  571  through  575  can also be read from the ODR  360  to any of the processors  111  or  112  without affecting the state or operation of the devices. This read operation is performed in a similar manner as with IRR  330 . In the example shown in  FIG. 5 , device  1   571  is on, which is reflected in bit ODR 0  as being high or “1”. Likewise, device  5   575  is off, which is reflected in bit ODR 1  as being low or “0”. Further, a processor could change the on/off status of devices  1  and  5   571 , 575  by executing a write to address x 0001  of the SRAM  350  that changes the state of ODR 0  to low or “0” and the state of ODR 1  to high or “1”. Processor  2   112 , can also control and monitor the states of devices  571  through  575  in a similar manner. 
     Table 2, below, defines the operation of embodiments of a dual-port SRAM  350  that includes an ODR  360  in accordance with the invention. As shown in Table 2, when  SFEN =V 1L , ODR  360  is active (i.e., ODR read/write mode is available to the processors) and address x 0001  is not available for standard memory operations. During ODR read/write mode of address x 0001 , I/O 0  through I/O 4  are valid bits and I/O 5  through I/O 15  are “don&#39;t care” bits. As will now be apparent to those skilled in the art, the invention can include a varying number of valid and “don&#39;t care” ODR bits. In this mode, writes to address x 0001  are allowed from any of the processors  111  or  112  when R/  W =“L”, and reads are allowed when R/  W =“H”. When  SFEN =V 1H , ODR  360  is inactive (i.e., standard memory mode is available to the processors) and address x 0001  can be used with the SRAM main memory array  451  for standard memory operations. However, as will be evident to those skilled in the art upon review of this disclosure, varying input/output levels and alternative logic schemes for ODR  360  can also be used with aspects of some embodiments of the present invention. Such variations and alternatives are intended to be within the scope of the present invention. 
     
       
         
           
               
             
               
                 TABLE 2 
               
             
            
               
                   
               
               
                 Output Drive Register (ODR) Operation 
               
            
           
           
               
               
               
               
               
               
               
               
               
               
            
               
                 
                   SFEN 
                 
                 
                   CE 
                 
                 R/  W   
                 
                   OE 
                 
                 
                   UB 
                 
                 
                   LB 
                 
                 ADDR 
                 I/O 0 -I/O 4   
                 I/O 5 -I/O 15   
                 Mode 
               
               
                   
               
               
                 H 
                 L 
                 H 
                 X 
                 L 
                 L 
                 x0000-Max 
                 Valid 
                 Valid 
                 Standard Memory 
               
               
                 L 
                 L 
                 L 
                 X 
                 X 
                 L 
                 x0001 
                 Valid 
                 X 
                 ODR Write 
               
               
                 L 
                 L 
                 H 
                 L 
                 X 
                 L 
                 x0001 
                 Valid 
                 X 
                 ODR Read 
               
               
                   
               
            
           
         
       
     
       FIG. 6  illustrates a functional block diagram  600  with signal routing for a dual-port SRAM according to some embodiments of the invention. As shown in exemplary  FIG. 6 , the block diagram  600  of the exemplary dual-port SRAM can include some blocks of the typical dual-port SRAM, for example: memory array  651 ; address decoders  652 L/R; I/O control  653 L/R; I/O logic  654 L/R; and arbitration, interrupt and semaphore logic  658 . Further, the signal pins of this exemplary SRAM can include some typical signal, for example:  CE   L/R ;  OE   L/R ; and R/  W   L/R . However, an SRAM according to the present invention can also include the IRR/ODR functional block  330 / 360 , which uses the signals  SFEN , IRR 0-1  and ODR 0-4 . 
       FIG. 7  illustrates a block diagram of a module  700  of a memory device  350  that specifies which bits are associated with input read registers and output drive registers. In some embodiments, module  700  may comprise at least one IRR  330 , at least one ODR  360 , and at least one special function decode module  730 . Special function decode module  730  may be coupled to IRR  330  and ODR  360 . IRR  330  and ODR  360  may be coupled to other elements of a memory device or to external binary devices via links  752 ,  753 ,  754 ,  755 ,  756 , and  757 . Links  752 ,  753 ,  754 ,  755 ,  756 , and  757  may be connected to external connectors, such as pins, on a memory device. 
     Special function decode module  730  may take as input one or more controlling bits  771 ,  772 , and  773 . The controlling bits  771 ,  772 , and  773  may be set by an internal memory device, such as a flash ROM (not pictured), or may be set via pins external to a memory device. In some embodiments, controlling bits  771 ,  772 , and  773  may be special function register bits  771 ,  772 , and  773 . Special function register bits  771 ,  772 , and  773  may be set at power-up of a memory device  350  or may be set dynamically during device operation. Special function decode module  730  may determine which controlled bits  762 ,  763 ,  764 ,  765 ,  766 , and  767  are coupled to IRR  330  and which are coupled to ODR  360  based on controlling bits  771 ,  772 , and  773 . For example, the controlling bits  771 ,  772 , and  773  may define which controlled bits  762 ,  763 ,  764 ,  765 ,  766 , and  767  are coupled to IRR  330  and ODR  360  based on Table 3. In the example of Table 3, if all three controlling bits are set to zero, then all of the controlled bits  762 ,  763 ,  764 ,  765 ,  766 , and  767  may be coupled to ODR  360 . On the other hand, if the controlling bits are set in another manner, then a different mixture of controlled bits are coupled to IRR  330  and ODR  360 . In some embodiments, there may be a disabling setting (depicted in Table 3 as occurring then controlling bits  771 ,  772 , and  773  are each set to one) in which no controlled bit  762 ,  763 ,  764 ,  765 ,  766 , or  767  is coupled to either IRR  330  or ODR  360 . 
     
       
         
           
               
             
               
                 TABLE 3 
               
               
                   
               
               
                 Programmable IRR &amp; ODR 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
               
               
               
            
               
                 771 
                 0 
                 0 
                 0 
                 0 
                 1 
                 1 
                 1 
                 1 
               
               
                 772 
                 0 
                 0 
                 1 
                 1 
                 0 
                 0 
                 1 
                 1 
               
               
                 773 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
                 0 
                 1 
               
               
                 Send to 
                 N/A 
                 762 
                 762-763 
                 762-764 
                 762-765 
                 762-766 
                 762-767 
                 N/A 
               
               
                 IRR 330 
               
               
                 Send to 
                 762-767 
                 763-767 
                 764-767 
                 765-767 
                 766-767 
                 767 
                 N/A 
                 N/A 
               
               
                 ODR 360 
               
               
                   
               
            
           
         
       
     
     In some embodiments, both IRR  330  and ODR  360  are coupled to each link  752 ,  753 ,  754 ,  755 ,  756 , and  757 . IRR  330  and ODR  360  may couple particular signals from the special function decode module  730  to link  752 ,  753 ,  754 ,  755 ,  756 , and  757 . Therefore, in some embodiments, when special function decode module  730  couples particular controlled bits, for example, controlled bits  762  and  763  to IRR  330 , and IRR  330  couples those particular controlled bits  762  and  763  to corresponding links  752  and  753 , then controlled bits  762  and  763  may effectively act as part of IRR  330 , and the memory device may be able to represent the state of binary devices connected to links  752  and  753  at controlled bits  762  and  763 , respectively. 
     Similarly, if special function decode module  730  couples particular controlled bits, for example, controlled bits  766  and  767 , to ODR  360 , and ODR  360  couples its inputs from special function decode module  730  to corresponding links  756  and  757 , then controlled bits  766  and  767  may effectively act as part of ODR  360 , and the memory device may be able to represent and modify the state of binary devices connected to links  756  and  757  via controlled bits  766  and  767 , respectively. 
     In some embodiments, bits  761  and  768  may be coupled directly to links  751  and  758 , respectively, thereby bypassing the assignment mechanism of special function decode module  730 . Bits  761  and  768  may each be associated with input read register  330  and/or an output drive register  360 . 
     In some embodiments, each controlling bit  771 ,  772 , and  773  may correspond to one or more controlled bits  762 ,  763 ,  764 ,  765 ,  766 , and  767 . For example, if there were one controlling bit  771 ,  772 , and  773  for each controlled bit  762 ,  763 ,  764 , then each controlling bit  771 ,  772 , and  773  could be used by special function decode module  730  to determine whether to associate the corresponding controlled bit  762 ,  763 , or  764 , respectively, with IRR  330  or ODR  360 . In other embodiments, such as those associated with Table 3, the controlling bits  771 ,  772 , and  773 , taken together may define states that indicate which of the controlled bits  762 ,  763 ,  764 ,  765 ,  766 , and  767  are coupled to each of IRR  330  and ODR  360 . 
     As would be appreciated by those skilled in the art, in some embodiments (not pictured), the features discussed with respect to  FIG. 7  may be performed using more than one IRR  330 , ODR  360 , and/or special function decode module  730 . Additionally, different numbers of bits  761  and  768 ; controlling bits  771 ,  772 , and  773 ; and controlled bits  762 ,  763 ,  764 ,  765 ,  766 , and  767  may be used. 
     Although embodiments of the present invention have been particularly described with reference to embodiments thereof, it should be readily apparent to those of ordinary skill in the art that various changes, modifications and substitutes can be made without departing from the spirit and scope of the invention. Such changes, modifications and substitutes are intended to be within the scope of the claimed invention. Accordingly, it will be appreciated that in numerous instances, some features of the invention will be employed without a corresponding use of other features. Further, those skilled in the art will understand that variations can be made in the number and arrangement of components illustrated in the above figures. For example, while specific reference is made to a static random access memory device, other memory types can also employ embodiments of the invention described herein. Additionally, while the processors used in the above examples are impliedly external to the memory device, those skilled in the art will recognize that a single integrated circuit chip might contain multiple processor cores as well as the memory device of the present invention (i.e., a system-on-a-chip). Further, some simple controllers that do not include GPI/O pins can now be given that I/O functionality by implementing embodiments of the invention. It is intended that the scope of the appended claims include such changes, modifications and substitutions.