Patent Publication Number: US-2018040358-A1

Title: Nonvolatile memory

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2016-155106, filed Aug. 5, 2016, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a nonvolatile memory. 
     BACKGROUND 
     Currently, cash memories and main memories used in various systems are mainly volatile memories such as a static random access memory (SRAM) and a dynamic random access memory (DRAM). However, they have a problem that power consumption is large. Thus, an attempt of replacing the volatile memories used in various systems and, furthermore, storage memories with high-speed and low-power nonvolatile RAM has been reviewed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram showing an example of a memory system. 
         FIG. 2  is a diagram showing an example of the memory system. 
         FIG. 3  is a diagram showing an example of the memory system. 
         FIG. 4  is a diagram showing a summary of sequential access and random access. 
         FIG. 5  is a table showing a status of a nonvolatile RAM at sequential/random access. 
         FIG. 6  is a diagram showing an example of an I/O width (bit width) inside the nonvolatile RAM. 
         FIG. 7  is a diagram showing an example of SOT-MRAM. 
         FIG. 8  is a diagram showing an example of an equivalent circuit of a sub-array. 
         FIG. 9  is an illustration showing an example of a device structure of a cell unit. 
         FIG. 10  is an illustration showing an example of the device structure of the cell unit. 
         FIG. 11  is an illustration showing an example of the device structure of the cell unit. 
         FIG. 12  is an illustration showing an example of a device structure of a memory cell. 
         FIG. 13  is an illustration showing an example of the device structure of the memory cell. 
         FIG. 14  is an illustration showing an example of the device structure of the memory cell. 
         FIG. 15  is a diagram showing an example of a word line decoder/driver. 
         FIG. 16A  is a diagram showing an example of a read/write circuit. 
         FIG. 16B  is a diagram showing an example of the read/write circuit. 
         FIG. 17  is a diagram showing an example of a sense circuit. 
         FIG. 18A  is an illustration showing an example of a (first) write operation of multi-bit access. 
         FIG. 18B  is an illustration showing an example of a (first) write operation of the multi-bit access. 
         FIG. 19A  is an illustration showing an example of a (second) write operation of the multi-bit access. 
         FIG. 19B  is an illustration showing an example of a (second) write operation of the multi-bit access. 
         FIG. 20A  is an illustration showing an example of a (first) write operation of single-bit access. 
         FIG. 20B  is an illustration showing an example of a (first) write operation of the single-bit access. 
         FIG. 21A  is an illustration showing an example of a (second) write operation of the single-bit access. 
         FIG. 21B  is an illustration showing an example of a (second) write operation of the single-bit access. 
         FIG. 22  is an illustration showing an example of a read operation of the multi-bit access. 
         FIG. 23  is an illustration showing an example of a read operation of the single-bit access. 
         FIG. 24  is a diagram simply showing SOT-MRAM of  FIG. 7 . 
         FIG. 25  is a diagram showing a modified example of SOT-MRAM of  FIG. 24 . 
         FIG. 26  is a diagram showing a modified example of SOT-MRAM of  FIG. 24 . 
         FIG. 27  is a diagram showing a modified example of SOT-MRAM of  FIG. 24 . 
         FIG. 28  is a diagram showing a modified example of SOT-MRAM of  FIG. 24 . 
         FIG. 29  is a diagram showing an example of a D/S_A driver of  FIGS. 27 and 28 . 
         FIG. 30  is a diagram showing an example of a D/S_B driver of  FIGS. 27 and 28 . 
         FIG. 31  is a diagram showing an example of a D/S_A sinker of  FIGS. 27 and 28 . 
         FIG. 32  is a diagram showing an example of a D/S_B driver of  FIGS. 27 and 28 . 
         FIG. 33  is a diagram showing an example of SOT-MRAM. 
         FIG. 34A  is a diagram showing an example of an equivalent circuit of a sub-array. 
         FIG. 34B  is a diagram showing an example of an equivalent circuit of a sub-array. 
         FIG. 35  is an illustration showing an example of a device structure of a cell unit. 
         FIG. 36  is an illustration showing an example of the device structure of the cell unit. 
         FIG. 37  is an illustration showing an example of the device structure of the cell unit. 
         FIG. 38  is a diagram showing an example of the word line decoder/driver. 
         FIG. 39  is a diagram showing an example of the read/write circuit. 
         FIG. 40  is an illustration showing an example of a (first) write operation of the multi-bit access. 
         FIG. 41  is an illustration showing an example of a (second) write operation of the multi-bit access. 
         FIG. 42  is an illustration showing an example of a (first) write operation of the single-bit access. 
         FIG. 43  is an illustration showing an example of a (second) write operation of the single-bit access. 
         FIG. 44  is an illustration showing an example of a read operation of the multi-bit access. 
         FIG. 45  is an illustration showing an example of a read operation of the single-bit access. 
         FIG. 46  is a diagram showing an example of SOT-MRAM. 
         FIG. 47  is a diagram showing an example of the word line decoder/driver. 
         FIG. 48  is a diagram showing an example of the sub-decoder/driver. 
         FIG. 49  is an illustration for comparison of the examples in  FIGS. 7, 33 and 46 . 
         FIG. 50  is a diagram simply showing SOT-MRAM of  FIG. 33 . 
         FIG. 51  is a diagram showing a modified example of SOT-MRAM of  FIG. 50 . 
         FIG. 52  is a diagram showing a modified example of SOT-MRAM of  FIG. 50 . 
         FIG. 53  is a diagram showing a modified example of SOT-MRAM of  FIG. 50 . 
         FIG. 54  is a diagram showing a modified example of SOT-MRAM of  FIG. 50 . 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, a nonvolatile memory comprising: a first conductive line extending in a first direction, and including a first portion, a second portion, a third portion provided between the first and second portions, and a fourth portion provided between the second and third portions; a first storage element including a first terminal and a second terminal, the first terminal being connected to the third portion; a first transistor including a third terminal, a fourth terminal, and a first electrode controlling a first current path between the third and fourth terminals, the third terminal being connected to the second terminal; a second storage element including a fifth terminal and a sixth terminal, the fifth terminal being connected to the fourth portion; a second transistor including a seventh terminal, an eighth terminal, and a second electrode controlling a second current path between the seventh and eighth terminals, the seventh terminal being connected to the sixth terminal; a second conductive line extending in the first direction and connected to the first and second electrodes; a third conductive line extending in a second direction crossing to the first direction and connected to the fourth terminal; and a fourth conductive line extending in the second direction and connected to the eighth terminal. 
     Embodiments will be described hereinafter with reference to the accompanying drawings. 
     (Memory System) 
       FIGS. 1 to 3  show examples of a memory system. 
     The memory system to which the embodiments are applied comprises a CPU (host)  11 , a memory controller  12  and a nonvolatile RAM  13 . 
     This memory system is employed in, for example, personal computers, electronic devices including cellular telephone terminals, image pickup devices including digital still cameras and video cameras, tablet computers, smartphones, game consoles, car navigation systems, printer devices, scanner devices, server systems and the like. 
     In the example of  FIG. 1 , a processor  10  comprises the CPU  11 , the memory controller  12 , and the nonvolatile RAM  13 . In other words, the memory controller  12  and the nonvolatile RAM  13  are embedded in the processor (chip)  10 . 
     In contrast, in the example of  FIG. 2 , the processor  10  comprises the CPU  11  and the memory controller  12 . In other words, the nonvolatile RAM  13  is provided independently of the processor (chip)  10 , as a general chip. In addition, in the example of  FIG. 3 , the memory controller  12  and the nonvolatile RAM  13  are provided independently of the processor (chip)  10 , as general chips. In this case, the memory controller  12  and the nonvolatile RAM  13  are, for example, mounted in a memory module  14 . 
     The CPU  11  comprises, for example, CPU cores. The CPU cores are the elements which can execute different data processing parallel to each other. The memory controller  12  mainly controls a read operation and a write operation for the nonvolatile RAM  13 . 
     The nonvolatile RAM  13  is a memory which can switch a multi-bit access (first mode) and a single-bit access (second mode). 
     The multi-bit access indicates accessing memory cells in a memory cell array in parallel and the single-bit access indicates accessing one memory cell in the memory cell array. 
     For example, a spin orbit torque (SOT)-magnetic random access memory (MRAM) is one of memories that can switch the multi-bit access and the single-bit access. The SOT-MRAM will be explained later. 
       FIG. 4  shows a summary of a sequential access and a random access. 
     In the memory system shown in  FIGS. 1 to 3 , the memory controller  12  can issue the first command to execute the sequential access and the second command to execute the random access. 
     The sequential access is a mode of sequentially accessing (multi-bit) memory cells. For example, burst transfer employed in DRAM, a storage class memory (SCM) and the like is a type of the sequential access. 
     In the burst transfer, the memory controller  12  can omit, for example, transfer of a column address to the nonvolatile RAM (embodiments)  13  or transfer of a column address to the DRAM (comparative example)  13 ′ by issuing the first command (burst transfer command). A band width (data amount which can be transferred in a certain period) between the CPU and the memory (nonvolatile RAM or DRAM) can be therefore improved. 
     The random access is a mode of accessing one (single-bit) memory cell. In the random access, the memory controller  12  issues the second command (random access command) and transfers a row address and a column address to the nonvolatile RAM (embodiments)  13  or the DRAM (comparative example)  13 ′. 
     In the random access, latency (i.e., a period from the time when the CPU requests a certain amount of data to the time when the CPU receives the data) is reduced as compared with the sequential access since the data required by the CPU alone is accessed. 
     Thus, the memory controller  12  issues the first command to instruct the sequential access when the band width is considered with a higher priority or the second command to instruct the random access when the latency is considered with a higher priority. 
     In the embodiments, the nonvolatile RAM  13  can switch the first mode to execute the multi-bit access and the second mode to execute the single-bit access, in response to the first command and the second command. 
     For example, when the memory controller  12  issues the first command, the first command is transferred to an internal controller  13 - 2  via an interface  13 - 1 . When the internal controller  13 - 2  confirms the first command, the internal controller  13 - 2  executes the multi-bit access to a memory cell array  13 - 3 . 
     In addition, when the memory controller  12  issues the second command, the second command is transferred to the internal controller  13 - 2  via the interface  13 - 1 . When the internal controller  13 - 2  confirms the second command, the internal controller  13 - 2  executes the single-bit access to a memory cell array  13 - 3 . 
     Thus, the multi-bit access is executed inside the nonvolatile RAM  13  when the sequential access is instructed, and the single-bit access is executed inside the nonvolatile RAM  13  when the random access is instructed. An access efficiency inside the nonvolatile RAM  13  can be thereby increased. 
     In other words, increase in the band width (increase in the data transfer efficiency) can be first obtained as an effect of the sequential access by making the multi-bit access correspond to the sequential access. In addition to this, the time required for the read operation or the write operation is reduced and the access efficiency inside the nonvolatile RAM  13  is increased by executing the multi-bit access inside the nonvolatile RAM  13 , in the embodiments. 
     In contrast, in the comparative example, the DRAM  13 ′ comprises an interface  13 ′- 1  corresponding to the first command and the second command but an internal controller  13 ′- 2  can only execute the single-bit access. 
     Therefore, even when the memory controller  12  issues the first command, the internal controller  13 ′- 2  executes the single-bit access to the memory cell array  13 ′- 3 . In other words, when the sequential access (access to memory cells) is instructed, the internal controller  13 ′- 2  must repeat access operations (operations of generating the column address and accessing the memory in response to the burst length). 
     If the sequential access is thus instructed in the comparative example, the time required for the read operation or the write operation is long and the access efficiency inside the DRAM  13 ′ is degraded since the access operations are executed inside the DRAM  13 ′. 
       FIG. 5  shows a status of the nonvolatile RAM at sequential/random access. 
     When the first command to instruct the sequential access is issued, the nonvolatile RAM executes the multi-bit access. The multi-bit access is N-bit access to access N bits (N memory cells) parallel. N is a natural number of 2 or larger. When N is eight, the N-bit access is a byte access. 
     The I/O width at the N-bit access is, for example, n×N. n is the number of blocks (memory cores) in which the read operation or the write operation can be executed parallel. n is, for example, 64, 128, 256, and the like. The I/O width indicates the data amount which can be transferred between the interface  13 - 1  and the memory cell array  13 - 3  within a certain period, inside the nonvolatile RAM. 
     As shown in  FIG. 6 , for example, if the memory cell array  13 - 3  includes n blocks (memory cores) BK_ 1 , . . . BK_n, the interface (data buffer)  13 - 1  in the nonvolatile RAM  13 - 1  can latch n×N bits in the read operation at the N-bit access. 
     In this case, n×N bits are transferred from the memory cell array  13 - 3  to the interface  13 - 1  via the internal bus (I/O width=n×N bits) in the read operation. The access efficiency in the nonvolatile RAM  13  is therefore improved in the read operation at the N-bit access. 
     However, the read operation in each of blocks BK_k (k is one of 1 to n) is executed in, for example, N cycles (N-time read operations). This is because one block BK_k includes one sense amplifier for convenience of layout. Since only one sense amplifier is included in each block BK_k, N cycles are required to read N bits from each block BK_k. This will be explained later. 
     However, each block BK_k includes, for example, a register and N bits read in N cycles are temporarily stored in the register. For this reason, n×N bits are transferred from the memory cell array  13 - 3  to the interface  13 - 1  via the internal bus (I/O width=n×N bits) in the read operation at the N-bit access as explained above. 
     Latency of the read operation at the N-bit access is t read ×N. t read  represents the latency in one cycle of the read operation (latency in reading one bit). 
     In addition, energy generated in the read operation at the N-bit access includes E WL , E col , and E sensing ×N. However, E WL  represents energy for activating the row (word line), E col  represents energy for activating the column (column select line), and E sensing  represents energy required to read the data by the sense amplifier. 
     In addition, as shown in  FIG. 6 , for example, if the memory cell array  13 - 3  includes n blocks (memory cores) BK_ 1 , . . . BK_n, the interface (data buffer)  13 - 1  in the nonvolatile RAM  13 - 1  can latch n×N bits in the write operation at the N-bit access, too. 
     In this case, n×N bits are transferred from the interface  13 - 1  to the memory cell array  13 - 3  via the internal bus (I/O width=n×N bits) in the write operation. In addition, in each block BK_k (k is one of 1 to n) of the memory cell array  13 - 3 , N bits transferred from the interface  13 - 1  are temporarily stored in the register. Therefore, in the write operation at the N-bit access, too, the access efficiency in the nonvolatile RAM  13  is improved, similarly to the read operation. 
     However, the write operation in each of the blocks BK_k is executed in, for example, two cycles (two write operations). This corresponds to a case where the nonvolatile RAM  13  is, for example, an SOT-MRAM. 
     In SOT-MRAM, for example, the same data (for example, 0) is written to N bits (N memory cells) in each block BK_k, in the first write operation. After this, N bits (N memory cells) in each block BK_k are held or changed as data (0 or 1) corresponding to the write data (N bits transferred from the interface  13 - 1 ), in the second write operation. This will be explained later. 
     The write operation in each block BK_k is executed in two cycles in, for example, SOT-MRAM but, if a nonvolatile memory capable of executing the operation in one cycle or the other cycles exists, the embodiments can also be implemented by using it. 
     An example of latency and energy of the write operation at the N-bit access will be explained. In this example, the nonvolatile RAM  13  is SOT-MRAM shown in  FIG. 7  which will be explained later, and the write operation is completed in two cycles. 
     The latency of the write operation at the N-bit access is t write ×2. However, t write  is the latency in one cycle of the write operation. 
     In addition, the energy generated in the write operation at the N-bit access includes E WL , E col , E BL ×N, and E SOT ×2. However, E WL  represents energy for activating the row (word line), E col  represents energy for activating the column (column select line), E BL  represents energy required for the voltage assist in SOT-MRAM, and E SOT  represents energy required to generate a write current in SOT-MRAM. 
     The voltage assist and generation of the write current in SOT-MRAM will be explained later. 
     The important matter is that the I/O width (n×N bits) in the read operation and the I/O width (n×N bits) in the write operation are the same as each other at the N-bit access. Since both the I/O widths are the same as each other, an algorithm in the read operation and an algorithm in the write operation can be partially made common, and control of the read operation and the write operation using the controller in the nonvolatile RAM can be simplified. 
     In contrast, when the second command to instruct the random access is issued, the nonvolatile RAM executes the single-bit access. The I/O width at the single-bit access is, for example, n. 
     As shown in  FIG. 6 , for example, if the memory cell array  13 - 3  includes n blocks (memory cores) BK_ 1 , . . . BK_n, the interface (data buffer)  13 - 1  in the nonvolatile RAM  13 - 1  can latch n bits in the read operation at the single-bit access. 
     In this case, n bits are transferred from the memory cell array  13 - 3  to the interface  13 - 1  via the internal bus (I/O width=n bits) in the read operation. The access efficiency in the nonvolatile RAM  13  is therefore improved in the read operation at the single-bit access. 
     The latency of the read operation at the single-bit access is t read . In addition, the energy generated in the read operation at the single-bit access includes E WL , E col , and E sensing . 
     As shown in  FIG. 6 , for example, if the memory cell array  13 - 3  includes n blocks (memory cores) BK_ 1 , . . . BK_n, the interface (data buffer)  13 - 1  in the nonvolatile RAM  13 - 1  can latch n bits in the write operation at the single-bit access. 
     In this case, n bits are transferred from the interface  13 - 1  to the memory cell array  13 - 3  via the internal bus (I/O width=n bits) in the write operation. In addition, in each block BK_k (k is one of 1 to n) of the memory cell array  13 - 3 , 1 bit transferred from the interface  13 - 1  is temporarily stored in the register. Therefore, in the write operation at the single-bit access, too, the access efficiency in the nonvolatile RAM  13  is improved, similarly to the read operation. 
     However, the write operation in each block BK_k is executed in, for example, two cycles (two write operations), similarly to the case of the N-bit access. This corresponds to a case where the nonvolatile RAM  13  is, for example, an SOT-MRAM. 
     In SOT-MRAM, for example, predetermined data (for example, 0) is written to 1 bit (one memory cell) which is an interest of write, in each block BK_k, in the first write operation. After this, 1 bit (one memory cell) which is the interest of write in each block BK_k, is held or changed as data (0 or 1) corresponding to the write data (1 bit transferred from the interface  13 - 1 ), in the second write operation. 
     N−1 bits other than 1 bit which is an interest of write are masked so as not to be the interest of write in both the first and second write operations. At the single-bit access, for example, 1 bit which is the interest of write and N−1 bits which is to be masked are determined based on the data stored in the register. This will be explained later. 
     An example of latency and energy of the write operation at the single-bit access in the embodiments will be explained. In this example, the nonvolatile RAM  13  is SOT-MRAM and the write operation is completed in two cycles. 
     The latency and energy of the write operation at the single-bit access are the same as the latency and energy of the write operation at the N-bit access. The latency of the write operation at the single-bit access is t write ×2. In addition, the energy generated in the write operation at the single-bit access includes E WL , E col , E BL ×N, and E SOT ×2. 
     The important matter is that the I/O width (n bits) in the read operation and the I/O width (n bits) in the write operation are the same as each other at the single-bit access, too. Since both the I/O widths are the same as each other, an algorithm in the read operation and an algorithm in the write operation can be partially made common, and control of the read operation and the write operation using the controller in the nonvolatile RAM can be simplified. 
     (SOT-MRAM) 
     The SOT-MRAM will be explained as a nonvolatile RAM to which the embodiments can be applied. 
     First Example 
       FIG. 7  shows a first example of the SOT-MRAM. 
     The SOT-MRAM  13   SOT  comprises an interface  13 - 1 , an internal controller  13 - 2 , a memory cell array  13 - 3  and a word line decoder/driver  17 . The memory cell array  13 - 3  comprises n blocks (memory cores) BK_ 1  to BK_n. n is a natural number of 2 or larger. 
     A command CMD is transferred to the internal controller  13 - 2  via the interface  13 - 1 . The command CMD includes, for example, a first command to instruct the sequential access and a second command to instruct the random access. 
     When the internal controller  13 - 2  receives the command CMD, the internal controller  13 - 2  outputs, for example, control signals WE l , to WE n , RE l  to RE n , WE1/2, W sel   _   1  to W sel   _   n , R sel   _   1  to R sel   _   n , and SE 1  to SE n , to execute the command CMD. The meaning and roles of the control signals will be explained later. 
     An address signal Addr is transferred to the internal controller  13 - 2  via the interface  13 - 1 . The address signal Addr is divided into a row address A row  and column addresses A col   _   1  to A col   _   n  in the interface  13 - 1 . The row address A row  is transferred to the word line decoder/driver  17 . The column addresses A col   _   1  to A col   _   n  are transferred to n blocks BK_ 1  to BK_n. 
     DA 1  to DA n  are read data or write data transmitted or received in the read operation or the write operation. The I/O width (bit width) between the interface  13 - 1  and each of the blocks BK_k (k is one of 1 to n) is N bits at the N-bit access or 1 bit at the single-bit access as explained above. 
     Each of the blocks BK_k includes a sub-array A sub   _   k , a read/write circuit  15 , and a column selector  16 . 
     The column selector  16  selects one of j columns (j is a natural number of 2 or larger) CoL 1  to CoL j  and connects the selected column CoL p  (p is one of 1 of j) to the read/write circuit  15 . If the selected column CoL p  is CoL 1 , for example, conductive lines LBL 1  to LBL 8 , SBL 1  and WBL 1  are electrically connected to the read/write circuit  15  via the column selector  16 , as conductive lines LBL 1  to LBL 8 , SBL and WBL. 
     The sub-array A sub   _   k  comprises, for example, memory cells M 11  (MC 1  to MC 8 ) to M 1j  (MC 1  to MC 8 ), and M i1  (MC 1  to MC 8 ) to M ij  (MC 1  to MC 8 ). 
     An example of the sub-array A sub   _   k  will be explained with an equivalent circuit of a sub-array A sub   _   1  shown in  FIG. 8 . 
     M 11  (MC 1  to MC 8 ) to M 1j  (MC 1  to MC 8 ), M i1  (MC 1  to MC 8 ) to M ij  (MC 1  to MC 8 ), WL 1  to WL i , SWL 1  to SWL i , SBL 1  to SBL j , WBL 1  to WBL j , LBL 1  to LBL 8 , Q W , and Q S  shown in  FIG. 8  correspond to M 11  (MC 1  to MC 8 ) to M 1j  (MC 1  to MC 8 ), M i1  (MC 1  to MC 8 ) to M ij  (MC 1  to MC 8 ), WL 1  to WL i , SWL 1  to SWL i , SBL 1  to SBL j , WBL 1  to WBL j , LBL 1  to LBL 8 , Q W , and Q S  shown in  FIG. 7 , respectively. 
     Conductive lines L SOT  extend in the first direction. The cell unit M ij  corresponds to the conductive line L SOT  and comprises the memory cells MC 1  to MC 8 . The number of memory cells MC 1  to MC 8  corresponds to N of the N-bit access. The number of memory cells MC 1  to MC 8  is eight in the present example but is not limited to this. For example, the number of memory cells MC 1  to MC 8  may be two or larger. 
     The memory cells MC 1  to MC 8  comprise storage elements MTJ 1  to MTJ 8  and transistors T 1  to T 8 , respectively. 
     Each of the storage elements MTJ 1  to MTJ 8  is a magnetoresistive element. For example, each of the storage elements MTJ 1  to MTJ 8  comprises a first magnetic layer (storage layer) having a variable magnetization direction, a second magnetic layer (reference layer) having an invariable magnetization direction, and a nonmagnetic layer (tunnel barrier layer) between the first and second magnetic layers, and the first magnetic layer is in contact with the conductive line L SOT . 
     In this case, the conductive line L SOT  desirably has the material and the thickness which enable the magnetization direction of the first magnetic layers of the storage elements MTJ 1  to MTJ 8  to be controlled by spin orbit coupling or the Rashba effect. For example, the conductive line L SOT  contains tantalum (Ta), tungsten (W), platinum (Pt) and the like and has a thickness in a range of 5 to 20 mm (for example, approximately 10 nm). The conductive line L SOT  may be formed in a multilayer structure of two or more layers including a layer of metals such as hafnium (Hf), magnesium (Mg), titanium (Ti) and the like in addition to a layer of the metals such as tantalum (Ta), tungsten (W), platinum (Pt) and the like. Furthermore, the conductive line L SOT  may be formed in a multilayer structure of two or more layers including layers formed of single metallic elements of the above but different in crystal structure or a layer in which a single metallic element of the above is oxidized or nitrided. 
     Each of transistors T 1  to T 8  is, for example, an N-channel field effect transistor (FET). The transistors T 1  to T 8  are desirably so called vertical transistors which are disposed above the semiconductor substrate and in which channels (current paths) intersect the surface of the semiconductor substrate in the vertical direction. 
     The storage element MTJ d  (d is one of 1 to 8) comprises a first terminal (storage layer) and a second terminal (reference layer), and the first terminal is connected to the conductive line L SOT . The transistor Td comprises a third terminal (source/drain), a fourth terminal (source/drain), a channel (current path) between the third and fourth terminals, and a control electrode (gate) which controls occurrence of a channel, and the third terminal is connected to a second terminal. 
     The conductive lines WL 1  to WL i  extend in the first direction and are connected to the control electrodes of the transistors T 1  to T 8 . The conductive lines LBL 1  to LBL 8  extend in the second direction intersecting the first direction and are connected to the fourth terminals of the transistors T 1  to T 8 , respectively. 
     Each of the conductive lines L SOT  has first and second end portions. 
     Each of the transistors Q S  comprises a channel (current path) connected between the first end portion of the conductive line L SOT  and the conductive lines SBL 1  to SBL j , and a control terminal (gate) which controls generation of the channel. Each of the transistors Q W  comprises a channel (current path) connected between the second end portion of the conductive line L SOT  and the conductive lines SBL 1  to SBL j , and a control terminal (gate) which controls generation of the channel. 
     The conductive lines SWL 1  to SWL i  extend in the first direction and are connected to the control electrodes of the transistors Q S  and Q W . The conductive lines SBL 1  to SBL j  and WBL 1  to WBL j  extend in the second direction. 
     In the present embodiments, the transistor Q S  is connected to the first end portion of the conductive line L SOT  and the transistor Q W  is connected to the second end portion of the conductive line L SOT , but one of them may be omitted. 
     According to the present embodiments, the architecture or the layout for putting SOT-MRAM to practical use is implemented. The nonvolatile MRAM which can be used in various systems can be thereby implemented. 
       FIGS. 9 to 14  show examples of a device structure of SOT-MRAM. 
     In these figures, M ij  (MC 1  to MC 8 , MTJ 1  to MTJ 8 , T 1  to T 8 ), WL i , SWL i , SBL j , WBL j , LBL 1  to LBL 8 , Q W , and Q S  correspond to M 1   j  (MC 1  to MC 8 , MTJ 1  to MTJ 8 , T 1  to T 8 ), WL i , SWL i , SBL j , WBL j , LBL 1  to LBL 8 , Q W , and Q S  shown in  FIGS. 7 and 8 , respectively. 
     In the example shown in  FIG. 9 , the conductive line L SOT  is disposed above the semiconductor substrate  21 , and each of the transistors Q S  and Q W  is disposed as what is called a horizontal transistor (FET) in the surface area of the semiconductor substrate  21 . The horizontal transistor is a transistor having a channel (current path) extending along the surface of the semiconductor substrate  11 . 
     The storage elements MTJ 1  to MTJ 8  are disposed on the conductive line L SOT  and the transistors T 1  to T 8  are disposed on the storage elements MTJ 1  to MTJ 8 , respectively. The transistors T 1  to T 8  are so called vertical transistors. The conductive lines LBL 1  to LBL 8 , SBL j  and WBL j  are disposed on the transistors T 1  to T 8 . 
     In the example shown in  FIG. 10 , the conductive line L SOT  is disposed above the semiconductor substrate  21 , and the transistors Q S  and Q W  and the storage elements MTJ 1  to MTJ 8  are disposed on the conductive line L SOT . The transistors T 1  to T 8  are disposed on the storage elements MTJ 1  to MTJ 8 , respectively. The transistors Q S , Q W , and T 1  to T 8  are so called vertical transistors. 
     In addition, the conductive lines LBL 1  to LBL 8  are disposed on the transistors T 1  to T 8 , and the conductive lines SBL j  and WBL j  are disposed on the transistors Q S  and Q W . 
     In the example shown in  FIG. 11 , the conductive lines LBL 1  to LBL 8 , SBL j  and WBL j  are disposed above a semiconductor substrate  21 . The transistors T 1  to T 8  are disposed on the conductive lines LBL 1  to LBL 8 , and the transistors Q S  and Q W  are disposed on the conductive lines SBL j  and WBL j . The storage elements MTJ 1  to MTJ 8  are disposed on the transistors T 1  to T 8 , respectively. 
     The conductive line L SOT  is disposed on the transistors T 1  to T 8 , Q S  and Q W . The transistors Q S , Q W , and T 1  to T 8  are so called vertical transistors. 
     In the examples of  FIGS. 9 to 11 , each of the storage elements MTJ 1  to MTJ 8  comprises a first magnetic layer (storage layer)  22  having a variable magnetization direction, a second magnetic layer (reference layer)  23  having an invariable magnetization direction, and a nonmagnetic layer (tunnel barrier layer)  24  between the first magnetic layer  22  and the second magnetic layer  23 , and the first magnetic layer  22  is in contact with the conductive line L SOT . 
     In addition, each of the first magnetic layer  22  and the second magnetic layer  23  has an easy-axis of magnetization in an in-plane direction along the surface of the semiconductor substrate  21  and in the second direction intersecting the first direction in which the conductive line L SOT  extends. 
     For example,  FIG. 12  shows an example of the device structure of the memory cell MC 1  shown in  FIGS. 9 and 10 . In this example, the transistor T 1  comprises a semiconductor pillar (for example, a silicon pillar)  25  extending in the third direction intersecting the first and second directions, i.e., the direction intersecting the surface of the semiconductor substrate  21 , a gate insulating layer (for example, silicon oxide)  26  covering a side surface of the semiconductor pillar  25 , and the conductive line WL i  covering the semiconductor pillar  25  and the gate insulating layer  26 . 
     The easy-axis of magnetization of each of the first magnetic layer  22  and the second magnetic layer  23  is the second direction in the example shown in  FIG. 12  but may be the first direction as indicated in the example shown in  FIG. 13  or the third direction as indicated in the example shown in  FIG. 14 . The storage element MTJ 1  shown in  FIGS. 12 and 13  is called a magnetoresistive element of an in-plane magnetization type, and the storage element MTJ 1  shown in  FIG. 14  is called a magnetoresistive element of a vertical magnetization type. 
     The device structure shown in  FIGS. 12 to 14  may be turned upside down to obtain the memory cell MC 1  shown in  FIG. 11 . 
     A characteristic of the memory cell MC 1  shown in  FIGS. 12 to 14  is that a current path of a read current I read  used in the read operation is different from a current path of a write current I write  used in the write operation. 
     For example, the read current I read  flows from the conductive line LBL 1  to the conductive line L SOT  or from the conductive line L SOT  to the conductive line LBL 1  in the read operation. In contrast, the write current I write  flows from the right side to the left side or from the left side to the right side inside the conductive line L SOT  in the write operation. 
     In the spin-transfer-torque (STT)-MRAM, the current path of the read current I read  used in the read operation is the same as the current path of the write current I write  used in the write operation. In this case, margin of the read current I read  and the write current I write  must be sufficiently secured in consideration of thermal stability Δ and the like to prevent occurrence of the write phenomenon in the read operation. 
     However, both the read current I read  and the write current I write  become small due to microminiaturization of a memory cell or the like, and the margin of both the currents can hardly be sufficiently secured. 
     According to the SOT-MRAM of the present example, since the current path of the read current I read  is different from the current path of the write current I write , the margin of both the currents can be sufficiently secured in consideration of thermal stability Δ and the like even if the read current I read  and the write current I write  become small due to microminiaturization of a memory cell or the like. 
       FIG. 15  shows an example of the word line decoder/driver shown in  FIG. 7 . 
     The word line decoder/driver  17  has a function of activating or deactivating the conductive lines WL 1  to WL i  and SWL 1  to SWL i  in the read operation or the write operation. 
     Activation of the conductive lines WL 1  to WL i  indicates applying an ON potential to turn on (i.e., to urge the current paths to be generated in) the transistors T 1  to T 8  to the conductive lines WL 1  to WL i . Activation of the conductive lines SWL 1  to SWL i  indicates applying an ON potential to turn on (i.e., to urge the current paths to be generated in) the transistors Q S  and Q W  to the conductive lines SWL 1  to SWL i . 
     Deactivation of the conductive lines WL 1  to WL i  indicates applying an OFF potential to turn off (i.e., to urge no current paths to be generated in) the transistors T 1  to T 8  to the conductive lines WL 1  to WL i . Deactivation of the conductive lines SWL 1  to SWL i  indicates applying an OFF potential to turn off (i.e., to urge no current paths to be generated in) the transistors Q S  and Q W  to the conductive lines SWL 1  to SWL i . 
     An OR circuit  31  and AND circuits  321  to  32   i  are decoder circuits. 
     In the read operation, for example, a read enable signal RE from the internal controller  13 - 2  shown in  FIG. 7  becomes active (1). In the write operation, a write enable signal WE from the internal controller  13 -shown in  FIG. 7  becomes active (1). 
     The row address signal A row  has, for example, R bits (R is a natural number of 2 or more) and has a relationship i (number of rows)=2 R . 
     In the read operation or the write operation, an output signal of one of the AND circuits  32   1  to  32   i  becomes active (1) when the row address signal A row  is input to the word line decoder/driver  17 . For example, if the row address signal A row  is 00 . . . 00 (all 0), the output signal of the AND circuit  32   1  becomes active. If the row address signal A row  is 11 . . . 11 (all 1), the output signal of the AND circuit  32   i  becomes active. 
     Drive circuits  33   1  to  33   i  and drive circuits  34   1  to  34   i  correspond to the AND circuits  32   1  to  32   i , respectively. 
     If the output signal of the AND circuit  32   1  is active (1), the drive circuit  33   1  outputs the ON potential to the conductive line WL 1  and the drive circuit  34   1  outputs the ON potential to the conductive line SWL 1 . If the output signal of the AND circuit  32   1  is nonactive (0), the drive circuit  33   1  outputs the OFF potential to the conductive line WL 1  and the drive circuit  34   1  outputs the OFF potential to the conductive line SWL 1 . 
     Similarly to this, if the output signal of the AND circuit  32   i  is active (1), the drive circuit  33   i  outputs the ON potential to the conductive line WL i  and the drive circuit  34   i  outputs the ON potential to the conductive line SWL i . If the output signal of the AND circuit  32   i  is nonactive (0), the drive circuit  33   i  outputs the OFF potential to the conductive line WL i  and the drive circuit  34   i  outputs the OFF potential to the conductive line SWL i . 
       FIG. 16A  shows an example of the read/write circuit shown in  FIG. 7 . 
     In the read operation or the write operation, the read/write circuit  15  selects one of the multi-bit access and the single-bit access, based on an instruction from the internal controller  13 - 2  shown in  FIG. 7 . 
     The read/write circuit  15  comprises a read circuit and a write circuit. 
     The write circuit comprises ROMs  35  and  37 , selectors (multiplexers)  36  and  39 , write drivers/sinkers D/S_A and D/S_B, a transfer gate TG, a data register  38 , a mask register  40 , AND circuits  41   1  to  41   8 , and voltage assist drivers  42   1  to  42   8 . 
     The write drivers/sinkers D/S_A and D/S_B have a function of urging one of a first write current and a second write current in mutually opposite directions to be generated in, for example, the conductive line L SOT  shown in  FIGS. 9 to 11 . 
     The first write current is a current for, for example, writing 0 to the storage elements MTJ 1  to MTJ 8  shown in  FIGS. 9 to 11 , i.e., setting a relationship between the magnetization directions of the first magnetic layer  22  and the second magnetic layer  23  of the storage elements MTJ 1  to MTJ 8  shown in  FIGS. 9 to 11  to be in a parallel state, by the spin orbit coupling or the Rashba effect. 
     The second write current is a current for, for example, writing 1 to the storage elements MTJ 1  to MTJ 8  shown in  FIGS. 9 to 11 , i.e., setting the relationship between the magnetization directions of the first magnetic layer  22  and the second magnetic layer  23  of the storage elements MTJ 1  to MTJ 8  shown in  FIGS. 9 to 11  to be in an antiparallel state, by the spin orbit coupling or the Rashba effect. 
     The voltage assist drivers  42   1  to  42   8  have a function of permitting/inhibiting the 0/1-write operation using the first and second write currents. 
     For example, when the voltage assist drivers  42   1  to  42   8  permit the 0/1-write operation, the voltage assist drivers  42   1  to  42   8  selectively apply an assist potential V dd   _   W2  for facilitating the 0/1-write operation to, for example, the conductive lines LBL 1  to LBL 8  shown in  FIGS. 9 to 11 . In this case, since a voltage for destabilizing the magnetization direction of the first magnetic layer (storage layer)  22  shown in  FIGS. 9 to 11  is generated in the storage elements MTJ 1  to MTJ 8 , the magnetization direction of the first magnetic layer  22  can easily be inversed. 
     When the voltage assist drivers  42   1  to  42   8  permit the 0/1-write operation as shown in  FIG. 16B , the voltage assist drivers  42   1  to  42   8  may selectively apply assist potentials V dd   _   W2  to V dd   _   W9  for facilitating the 0/1-write operation to, for example, the conductive lines LBL 1  to LBL 8  shown in  FIGS. 9 to 11 , respectively. In other words, the assist potentials applied to the conductive lines LBL 1  to LBL 8  shown in  FIGS. 9 to 11  may be different from each other. 
     When the voltage assist drivers  42   1  to  42   8  inhibit the 0/1-write operation, the voltage assist drivers  42   1  to  42   8  selectively apply an inhibit potential V inhibit   _   W  for urging the 0/1-write operation to be hardly executed to, for example, the conductive lines LBL 1  to LBL 8  shown in  FIGS. 9 to 11 . In this case, since a voltage for destabilizing the magnetization direction of the first magnetic layer (storage layer)  22  shown in  FIGS. 9 to 11  is not generated in the storage elements MTJ 1  to MTJ 8  or since a voltage for stabilizing the magnetization direction of the first magnetic layer  22  is generated in the storage elements MTJ 1  to MTJ 8 , the magnetization direction of the first magnetic layer  22  can hardly be inversed. 
     When the voltage assist drivers  42   1  to  42   8  inhibit the 0/1-write operation, the voltage assist drivers  42   1  to  42   8  may set the conductive lines LBL 1  to LBL 8  to be in a floating state instead of applying the inhibit potential V inhibit   _   W  to the conductive lines LBL 1  to LBL 8 . 
     The read circuit comprises shift registers  43  and  46 , read drivers  44   1  to  44   8  and a sense circuit  45 . 
     The read drivers  44   1  to  44   8  have a function of selectively applying, for example, a select potential V dd   _   r  for urging the read current to be generated to the conductive lines LBL 1  to LBL 8  shown in  FIGS. 9 to 11 . In this case, since the read current flows from one conductive line LBL d  (d is one of 1 to 8) to which the select potential V dd   _   r  is applied to the conductive line L SOT  shown in  FIGS. 9 to 11 , data is read from the storage element MTJ d  which is to be read. 
     The read drivers  44   1  to  44   8  may apply a nonselect potential V inhibit   _   r  which does not urge the read current to be generated, to remaining seven conductive lines other than the conductive line LBL d , of the conductive lines LBL 1  to LBL 8  or may set seven conductive lines to be in a floating state instead. 
     One sense circuit  45  is provided in, for example, one read/write circuit  15 . In other words, only one sense circuit  45  is provided in one block (memory core) BK_k. 
     The sense circuit  45  comprises, for example, a sense amplifier SA n , a clamp transistor (for example, N-channel FET) Q clamp , an equalizing transistor (for example, N-channel FET) Q equ , and a reset transistor (for example, N-channel FET) Q rst  as shown in  FIG. 17 . 
     When the control signal RE n  from the internal controller  13 - 2  shown in  FIG. 7  is active (high level), the clamp transistor Q clamp  is turned on. In addition, when the control signal RE n  from the internal controller  13 - 2  shown in  FIG. 7  is active (high level), i.e., when the control signal bSE n  is active (low level), the sense amplifier SA n  becomes in an operated state. 
     The sense amplifier SA n  is a current sense type of comparing a cell current (read current) I mc  flowing from the memory cell which is to be read to the conductive line SBL with a reference current I rc  flowing to the reference cell, in the present example, but is not limited to this. The sense amplifier SA n  may adopt, for example, a sense amplifier circuit of a voltage sense type or a self-reference type. 
     In addition, when the control l signal φ eau  is active (high level), the equalizing transistor Q equ  is turned on and, for example, potentials of two input/output nodes N mc  and N rc  of the sense amplifier SA n  are equalized. In addition, when the control signal φ rst  is active (high level), the reset transistor Q rst  is turned on. 
     Next, an example of the read operation and an example of the write operation using the word line decoder/driver  17  shown in  FIG. 15  and the read/write circuit  15  shown in  FIG. 16  will be explained. 
     *Write Operation 
     [Multi-Bit Access] 
     When the internal controller  13 - 2  shown in  FIG. 7  receives, for example, the write command CMD of the sequential access, the internal controller  13 - 2  controls the write operation using the multi-bit access. The internal controller  13 - 2  executes the write operation using the multi-bit access by the first write operation and the second write operation. 
     The first write operation is an operation of writing the same data (for example, 0) at multi-bits (for example, 8 bits) which are the interests of write. 
     First, the write enable signal WE becomes 1 and the output signal of the OR circuit  31  becomes 1 in the word line decoder/driver  17  shown in  FIG. 15 . For example, if all the bits of the row address signal A row  are 1 (11 . . . 11), the output signal of the AND circuit  32   i  becomes 1. The conductive lines WL i  and SWL i  are therefore activated by the drivers  33   i  and  34   1 . 
     Next, the internal controller  13 - 2  shown in  FIG. 7  sets, for example, the control signal WE1/2 at 0. The control signal WE1/2 is a signal for selecting one of the first write operation and the second write operation and, for example, when the control signal WE1/2 is 0, the first write operation is selected. 
     In this case, the selector  36  selects and outputs 0 from the ROM  35  as the ROM data, in the read/write circuit  15  shown in  FIG. 16A . Therefore, the write driver/sinker D/S_A outputs, for example, the drive potential V dd   _   W1  as the write pulse signal and the write driver/sinker D/S_B outputs, for example, the ground potential V ss . 
     In addition, in the write operation, the transfer gate TG is on since the control signal WE n  becomes active (high level). 
     Therefore, the write pulse signal is applied to the conductive line WBL via the transfer gate TG and the ground potential V ss  is applied to the conductive line SBL via the transfer gate TG. At this time, if the column selected by the column selector  16  shown in  FIG. 7  is assumed to be CoL j , the write current (first write current) I write  flows from the conductive line WBL j  to the conductive line SBL j , i.e., from the right side to the left side in the conductive line L SOT , as shown in, for example,  FIG. 18A . 
     In addition, the selector  39  selects and outputs all 1 (11111111) from the ROM  37  as the ROM data, in the read/write circuit  15  shown in  FIG. 16A . In addition, the internal controller  13 - 2  shown in  FIG. 7  sets the value of the mask register  40  at all 1 (11111111) by using, for example, the control signal W sel   _   1 . at the multi-bit access. 
     All the AND circuits  41   1  to  41   8  therefore output 1 as the output signals. At this time, all the high-voltage assist drivers  42   1  to  42   8  output, for example, the assist potential V dd   _   W2  to the conductive lines LBL 1  to LBL 8 . 
     In other words, for example, the write current (first write current) I write  flows from the conductive line WBL j  to the conductive line SBL j  in a state in which the assist potential V dd   _   W2  is applied to all the conductive lines LBL 1  to LBL 8 , as shown in  FIG. 18A . 
     As a result, the same data is written at all the multi-bits (for example, 8 bits) that are the interests of write, in the first write operation. However, it is assumed that 0 is written, i.e., all the storage elements MTJ 1  to MTJ 8  become in a parallel state in the first write operation. 
     In addition, the assist potentials applied to the respective conductive lines LBL 1  to LBL 8  may be mutually different potentials V dd   _   W2  to V dd   _   W9  by preparing a plurality of (for example, eight) power lines as shown in  FIG. 16B  and  FIG. 18B . 
     The second write operation is an operation of urging the same data (for example, 0) written at multi-bits (for example, 8 bits) which are the interests of write, to be held (for example, if the write data is 0) or to be changed from 0 to 1 (for example, if the write data is 1) in accordance with the write data. 
     First, the conductive lines WL i  and SWL i  are held in the activated state in the word line decoder/driver  17  shown in  FIG. 15 . 
     Next, the internal controller  13 - 2  shown in  FIG. 7  sets, for example, the control signal WE1/2 at 1. For example, when the control signal WE1/2 is 1, the second write operation is selected. 
     In this case, the selector  36  selects and outputs 1 from the ROM  35  as the ROM data, in the read/write circuit  15  shown in  FIG. 16A . Therefore, the write driver/sinker D/S_B outputs, for example, the drive potential V dd   _   W1  as the write pulse signal and the write driver/sinker D/S_A outputs, for example, the ground potential V ss . 
     The drive potential of the write pulse signal output from the write driver/sinker D/S_A circuit in the first write operation and the drive potential of the write pulse signal output from the write driver/sinker D/S_B in the second write operation may be different drive potentials. In addition, the ground potential of the write pulse signal output from the write driver/sinker D/S_B circuit in the first write operation and the ground potential of the write pulse signal output from the write driver/sinker D/S_B in the second write operation may be different ground potentials. 
     The write pulse signal is applied to the conductive line SBL via the transfer gate TG and the ground potential V ss  is applied to the conductive line WBL via the transfer gate TG. At this time, if the column selected by the column selector  16  shown in  FIG. 7  is assumed to be CoL j , the write current (second write current) I write  flows from the conductive line SBL j  to the conductive line WBL j , i.e., from the right side to the left side in the conductive line L SOT , as shown in, for example,  FIG. 19A . 
     In addition, the selector  39  selects and outputs the write data (for example, 01011100) stored in the data register  38 , in the read/write circuit  15  shown in  FIG. 16A . The write data is preliminarily stored in the data register  38  before the second write operation is executed. In addition, the internal controller  13 - 2  shown in  FIG. 7  sets the value of the mask register  40  at all 1 (11111111) by using, for example, the control signal W sel   _   1 , at the multi-bit access. 
     The AND circuits  41   1  to  41   8  therefore output the output signal (for example, 01011100) corresponding to the write data. At this time, for example, each of the voltage assist drivers  42   1  to  42   8  outputs the assist potential V dd   _   W2  when the write data is 1 or outputs the inhibit potential V inhibit   _   W  when the write data is 0. 
     In other words, for example, if the write data is 01011100, the write current (second write current) I write  flows from the conductive line SBL j  to the conductive line WBL j  in a state in which the inhibit potential V inhibit   _   W  is applied to the conductive lines LBL 1 , LBL 3 , LBL 7  and LBL 8  and the assist potential V dd   _   W2  is applied to the conductive lines LBL 2 , LBL 4 , LBL 5  LBL 6 , as shown in  FIG. 19A . 
     As a result, 0 is held, i.e., 0 is written as the data of the storage elements MTJ 1 , MTJ 3 , MTJ 7  and MTJ 8 , of the multi-bits (for example, 8 bits) which are the interests of write, in the second write operation. In addition, 0 is changed to 1, i.e., 1 is written as the data of the storage elements MTJ 2 , MTJ 4 , MTJ 5  and MTJ 6 , of the multi-bits (for example, 8 bits) which are the interests of write. 
     In addition, the assist potentials applied to the conductive lines LBL 2 , LBL 4 , LBL 5  and LBL 6  may be V dd   _   W3 , V dd   _   W5 , V dd   _   W6  and V dd   _   W7 , respectively, as shown in  FIG. 16B  and  FIG. 19B . The inhibit potentials V inhibit   _   W  applied to the conductive lines LBL 1 , LBL 3 , LBL 7  and LBL 8  may also be mutually different potentials. In addition, if the efficiency of the voltage effect of the voltage assist is adequately high, the inhibit potential V inhibit  can be replaced with a floating potential. 
     However, it is assumed that 1 is selectively written to the storage elements MTJ 1  to MTJ 8 , i.e., the state of the storage elements MTJ 1  to MTJ 8  is selectively changed from the parallel state to the antiparallel state, in the second write operation. 
     [Single-Bit Access] 
     When the internal controller  13 - 2  shown in  FIG. 7  receives, for example, the write command CMD of the random access, the internal controller  13 - 2  controls the write operation using the single-bit access. The internal controller  13 - 2  executes the write operation using the single-bit access by the first write operation and the second write operation. 
     The first write operation is an operation of writing predetermined data (for example, 0) at the single bit which is the interest of write. 
     First, the output signal of the OR circuit  31  becomes 1 in the word line decoder/driver  17  shown in  FIG. 15 . For example, if all the bits of the row address signal A row  are 1 (11 . . . 11), the output signal of the AND circuit  32   i  becomes 1. The conductive lines WL i  and SWL i  are therefore activated by the drivers  33   i  and  34   i . 
     Next, the internal controller  13 - 2  shown in  FIG. 7  sets, for example, the control signal WE1/2 at 0. For example, when the control signal WE1/2 is 0, the first write operation is selected. 
     In this case, the selector  36  selects and outputs 0 from the ROM  35  as the ROM data, in the read/write circuit  15  shown in  FIG. 16A . Therefore, the write driver/sinker D/S_A outputs, for example, the drive potential V dd   _   W1  as the write pulse signal and the write driver/sinker D/S_B outputs, for example, the ground potential V ss . 
     The write pulse signal is applied to the conductive line WBL via the transfer gate TG and the ground potential V ss  is applied to the conductive line SBL via the transfer gate TG. At this time, if the column selected by the column selector  16  shown in  FIG. 7  is assumed to be CoL j , the write current (first write current) I write  flows from the conductive line WBL j  to the conductive line SBL j , i.e., from the right side to the left side in the conductive line L SOT , as shown in, for example,  FIG. 20A . 
     In addition, the selector  39  selects and outputs all 1 (11111111) from the ROM  37  as the ROM data, in the read/write circuit  15  shown in  FIG. 16A . In addition, the internal controller  13 - 2  shown in  FIG. 7  sets selected one bit, of eight bits stored in the mask register  40 , at 1 by using, for example, the control signal W sel   _   1 , at the single-bit access. 
     For example, when the storage element MTJ 4  is an interest of write, 1 bit corresponding to the conductive line LBL 4  connected to the storage element MTJ 4 , of 8 bits stored in the mask register  40 , is set at 1. In this case, 8 bits stored in the mask register  40  becomes, for example, 00010000. 
     Therefore, the AND circuit  41   4 , of the AND circuits  41   1  to  41   8 , outputs 1 as the output signal and the remaining AND circuits  41   1  to  41   3  and  41   5  to  41   8  output 0 as the output signals. At this time, the voltage assist driver  42   4 , of the high-voltage assist drivers  42   1  to  42   8  outputs the assist potential V dd   _   W2  to the conductive line LBL 4 , and the remaining voltage assist drivers  42   1  to  42   3  and  42   5  to  42   8  output the inhibit potential V inhibit   _   W  to the conductive lines LBL 1  to LBL 3  and LBL 5  to LBL 8 . 
     In other words, for example, the write current (first write current) I write  flows from the conductive line WBL j  to the conductive line SBL 1  in a state in which the assist potential V dd   _   W2  is applied to the conductive line LBL 4  and the inhibit potential V inhibit   _   W  is applied to the conductive lines LBL 1  to LBL 3  and LBL 5  to LBL 8 , as shown in  FIG. 20A . 
     As a result, the single bit which is the interest of write, for example, predetermined data (for example, 0) is written to the storage element MTJ 4 , in the first write operation. 
     In addition, the already written data is held in remaining seven bits that are not the interests of write, for example, the storage elements MTJ 1  to MTJ 3  and MTJ 5  to MTJ 8 , by the above mask processing. In other words, the data in the storage elements MTJ 1  to MTJ 3  and MTJ 5  to MTJ 8  is not changed to 0, but the data in the storage elements MTJ 1  to MTJ 3  and MTJ 5  to MTJ 8  is protected, in the first write operation. 
     As shown in  FIG. 16B  and  FIG. 20B , the write current (first write current) I write  may flow from the conductive line WBL j  to the conductive line SBL j  in a state in which the assist potential V dd   _   W5  is applied to the conductive line LBL 4 , by preparing the mutually different potentials V dd   _   W2  to V dd   _   W9  as the assist potentials applied to the conductive lines LBL 1  to LBL 8 . The inhibit potentials V inhibit   _   W  applied to the conductive lines LBL 1  to LBL 3  and LBL 5  to LBL 8  may also be mutually different potentials. In addition, if the efficiency of the voltage effect of the voltage assist is adequately high, the inhibit potential V inhibit  can be replaced with a floating potential. 
     The second write operation is an operation of urging the predetermined data (for example, 0) written at the single bit which is the interest of write, to be held (for example, if the write data is 0) or to be changed from 0 to 1 (for example, if the write data is 1) in accordance with the write data. 
     First, the conductive lines WL i  and SWL i  are held in the activated state in the word line decoder/driver  17  shown in  FIG. 15 . 
     Next, the internal controller  13 - 2  shown in  FIG. 7  sets, for example, the control signal WE1/2 at 1. For example, when the control signal WE1/2 is 1, the second write operation is selected. 
     In this case, the selector  36  selects and outputs 1 from the ROM  35  as the ROM data, in the read/write circuit  15  shown in  FIG. 16A . Therefore, the write driver/sinker D/S_B outputs, for example, the drive potential V dd   _   W1  as the write pulse signal and the write driver/sinker D/S_A outputs, for example, the ground potential V ss . 
     The drive potential of the write pulse signal output from the write driver/sinker D/S_A circuit in the first write operation and the drive potential of the write pulse signal output from the write driver/sinker D/S_B in the second write operation may be different drive potentials. In addition, the ground potential of the write pulse signal output from the write driver/sinker D/S_B circuit in the first write operation and the ground potential of the write pulse signal output from the write driver/sinker D/S_B in the second write operation may be different ground potentials. 
     The write pulse signal is applied to the conductive line SBL via the transfer gate TG and the ground potential V ss  is applied to the conductive line WBL via the transfer gate TG. At this time, if the column selected by the column selector  16  shown in  FIG. 7  is assumed to be CoL j , the write current (second write current) I write  flows from the conductive line SBL j  to the conductive line WBL j , i.e., from the left side to the right side in the conductive line L SOT , as shown in, for example,  FIG. 21A . 
     In addition, the selector  39  selects and outputs the write data (for example, xxx1xxxx) stored in the data register  38 , in the read/write circuit  15  shown in  FIG. 16A . In this example, x represents invalid data. The write data is preliminarily stored in the data register  38  before the second write operation is executed. In addition, the internal controller  13 - 2  shown in  FIG. 7  sets selected one bit, of eight bits stored in the mask register  40 , at 1 by using, for example, the control signal W sel   _   1 , at the single-bit access. 
     For example, when the storage element MTJ 4  is an interest of write in the first write operation, 1 bit corresponding to the conductive line LBL 4  connected to the storage element MTJ 4 , of 8 bits stored in the mask register  40 , is set at 1 in the second write operation, too. In other words, 8 bits stored in the mask register  40  becomes, for example, 00010000. 
     The AND circuit  41   4 , of the AND circuits  41   1  to  41   8 , therefore outputs the output signal (for example, 1) corresponding to the write data. At this time, for example, the voltage assist driver  42   4  outputs the assist potential V dd   _   W2  when the write data is 1 or outputs the inhibit potential V inhibit   _   W  when the write data is 0. 
     In addition, the AND circuits  41   1  to  41   3  and  41   5  to  41   8 , of the AND circuits  41   1  to  41   8 , output 0. At this time, the voltage assist drivers  42   1  to  42   3  and  42   5  to  42   8  output, for example, the inhibit potential V inhibit   _   W . 
     In other words, for example, if the write data is xxx1xxxx and the mask data is 00010000, the write current (second write current) I write  flows from the conductive line SBL j  to the conductive line WBL j  in a state in which the inhibit potential V inhibit   _   W  is applied to the conductive lines LBL 1  to LBL 3  and LBL 5  to LBL 8  and the assist potential V dd   _   W2  is applied to the conductive lines LBL 4 , as shown in  FIG. 21A . 
     As a result, the predetermined data (for example, 0) is changed to 1, i.e., 1 is written as the single bit which is the interest of write, for example, the data of the storage element MTJ 4 , in the second write operation. In contrast, when the write data is 0, the predetermined data (for example, 0) is held, i.e., 0 is written as the data of the storage elements MTJ 4 . 
     In addition, the already written data is held in remaining seven bits that are not the interests of write, for example, the storage elements MTJ 1  to MTJ 3  and MTJ 5  to MTJ 8 , by the above mask processing. In other words, the data in the storage elements MTJ 1  to MTJ 3  and MTJ 5  to MTJ 8  is not changed to 1, but the data in the storage elements MTJ 1  to MTJ 3  and MTJ 5  to MTJ 8  is protected, in the second write operation, too. 
     As shown in  FIG. 16B  and  FIG. 21B , the write current (second write current) I write  may flow from the conductive line SBL j  to the conductive line WBL j  in a state in which the assist potential V dd   _   W5  is applied to the conductive line LBL 4 , by preparing the mutually different potentials V dd   _   W2  to V dd   _   W9  as the assist potentials applied to the conductive lines LBL 1  to LBL 8 . The inhibit potentials V inhibit   _   W  applied to the conductive lines LBL 1  to LBL 3  and LBL 5  to LBL 8  may also be mutually different potentials. In addition, if the efficiency of the voltage effect of the voltage assist is adequately high, the inhibit potential V inhibit  can be replaced with a floating potential. 
     A single voltage assist driver may be provided instead of the voltage assist drivers and a destination of its output may be changed to one of the conductive lines LBL 1  to LBL 8  sequentially. In this case, the multi-bit access can be executed in the write type close to a single-bit access type which will be explained later. 
     *Read Operation 
     [Multi-Bit Access] 
     When the internal controller  13 - 2  shown in  FIG. 7  receives, for example, the read command CMD of the sequential access, the internal controller  13 - 2  controls the read operation using the multi-bit access. 
     First, the read enable signal RE becomes 1 and the output signal of the OR circuit  31  becomes 1 in the word line decoder/driver  17  shown in  FIG. 15 . For example, if all the bits of the row address signal A row  are 1 (11 . . . 11), the output signal of the AND circuit  32   i  becomes 1. The conductive lines WL i  and SWL i  are therefore activated by the drivers  33   i  and  34   i . 
     Next, the internal controller  13 - 2  shown in  FIG. 7  sets selected one bit of eight bits stored in the shift register  43  to be 1 sequentially by using, for example, the control signal R sel   _   1 . In this case, the read drivers  44   1  to  44   8  sequentially output the select potential V dd   _   r . 
     For example, the conductive lines LBL 1  to LBL 8  are selected one by one at the select potential V dd   _   r  and seven conductive lines other than the conductive line LBL d  (d is one of 1 to 8) set at the select potential V dd   _   r  are set at the nonselect potential V inhibit   _   r . In addition, φ rst  in  FIG. 17  becomes active and the conductive line SBL is set at the ground potential V ss . 
     In this case, for example, if the conductive line LBL 1  is set at the select potential V dd   _   r , the read current I read  flows from the conductive line LBL 1  to the conductive line L SOT  via the storage element MTJ 1 , as shown in  FIG. 22 . The data of the storage element MTJ 1  is thereby stored in the shift register  46  via the sense circuit  45  shown in  FIG. 16A or 16B . 
     Similarly to this, the data of the storage elements MTJ 2  to MTJ 8  is sequentially stored in the shift register  46  via the sense circuit  45  shown in  FIG. 16A or 16B  by sequentially setting the conductive lines LBL 2  to LBL 8  at the select potential V dd   _   r . 
     As a result, the multi-bits (for example, 8 bits) that are the interests of sequential access are stored in the shift register  46  as the read data (for example, 01011100), by eight read operations. The multi-bits are wholly transferred to the interface  13 - 2  shown in  FIG. 7  as the read data DA 1 . 
     The select potentials sequentially applied to the conductive lines LBL 1  to LBL 8  can be different potentials by preparing a plurality of (for example, eight) power lines. In this case, the influence that the parasitic resistance differs in accordance with the location of the selected storage element on the conductive line L SOT  can be canceled. 
     If the efficiency of the voltage effect of the voltage assist is adequately high, the floating potential can also be used as the nonselect potential. In this case, a plurality of read drivers do not need to be mounted, and the select potential V dd   _   r  can be output to the predetermined conductive line and the read operation can be executed by changing one of the conductive lines LBL 1  to LBL 8  sequentially as the destination of the output of the single read driver. 
     [Single-Bit Access] 
     When the internal controller  13 - 2  shown in  FIG. 7  receives, for example, the read command CMD of the random access, the internal controller  13 - 2  controls the read operation using the single-bit access. 
     First, the read enable signal RE becomes 1 and the output signal of the OR circuit  31  becomes 1 in the word line decoder/driver  17  shown in  FIG. 15 . For example, if all the bits of the row address signal A row  are 1 (11 . . . 11), the output signal of the AND circuit  32   i  becomes 1. The conductive lines WL i  and SWL i  are therefore activated by the drivers  33   i  and  34   i . 
     Next, the internal controller  13 - 2  shown in  FIG. 7  sets one bit of eight bits stored in the shift register  43  to be 1 by using, for example, the control signal R sel   _   1 . For example, if the storage element which is the interest of read is MTJ 4 , the internal controller  13 - 2  shown in  FIG. 7  controls the shift register  43  such that eights stored in the shift register  43  become 00010000. 
     In this case, the read driver  44   4 , of the read drivers  44   1  to  44   8 , outputs the select potential V dd   _   r  and remaining seven read drivers  44   1  to  44   3  and  44   5  to  44   8  output the nonselect potential V inhibit  r. In addition, φ rst  in  FIG. 17  becomes active and the conductive line SBL is set at the ground potential V ss . 
     Therefore, for example, the read current I read  flows from the conductive line LBL 4  to the conductive line L SOT  via the storage element MTJ 4 , as shown in  FIG. 23 . The data of the storage element MTJ 4  is thereby stored in the shift register  46  via the sense circuit  45  shown in  FIG. 16A or 16B . As a result, the shift register  46  stores, for example, xxx1xxxx as the read data. 
     The valid data (read data) stored in the shift register  46  is transferred to the interface  13 - 1  shown in  FIG. 7  as the read data DA 1 . 
     The select potentials sequentially applied to the conductive lines LBL 1  to LBL 8  may be different potentials by preparing a plurality of (for example, eight) power lines. In this case, the influence that the parasitic resistance differs in accordance with the location of the selected storage element on the conductive line L SOT  can be canceled. 
     If the efficiency of the voltage effect of the voltage assist is adequately high, the floating potential can also be used as the nonselect potential. In this case, a plurality of read drivers do not need to be mounted, and the select potential V dd   _   r  can be output to the predetermined conductive line and the read operation can be executed by changing one of the conductive lines LBL 1  to LBL 8  sequentially as the destination of the output of the single read driver. 
     (Layout) 
       FIG. 24  is a diagram simply showing the SOT-MRAM explained with reference to  FIGS. 7 to 23 .  FIGS. 25 to 28  show a modified example of the SOT-MRAM shown in  FIG. 24 . An example of the layout of the write drivers/sinkers D/S_A and D/S_B will be explained here. 
     The same elements as those shown in, for example,  FIG. 7  are denoted by the same referential numbers in  FIGS. 24 to 28  and their detailed explanations are omitted. 
     The SOT-MRAM shown in  FIG. 24  has, for example, what is called a shared word line architecture in which the memory cells MC 1  to MC 8  accessed parallel at the multi-bit access share one conductive line (word line) WL 1  selecting the memory cells MC′ to MC 8 . 
     In addition, the SOT-MRAM shown in  FIG. 24  has what is called a column direction extending architecture in which the conductive lines WBL 1  to WBL j  and SBL 1  to SBL j  for urging the write current to flow to the conductive line L SOT  shared by the memory cells MC 1  to MC 8  extend in the second direction intersecting the first direction. 
     In this case, the write drivers/sinkers D/S_A and D/S_B are disposed in the read/write circuit  15  in each block (memory core) BK_k (k is one of 1 to n). The write drivers/sinkers D/S_A and D/S_B are shared by the columns CoL 1  to CoL j . 
     In addition, the power lines PSL for supplying, for example, the drive potential V dd   _   W1  and the ground potential V ss  to the write drivers/sinkers D/S_A and D/S_B are disposed above the read/write circuit  15  and extend in the first direction. 
     The SOT-MRAM shown in  FIG. 25  has the shared word line architecture and the column direction extending architecture, similarly to the SOT-MRAM shown in  FIG. 24 . 
     However, the write drivers/sinkers D/S_A and D/S_B are provided for each column CoL p  (p is one of 1 to j) in the block BK_k (k is one of 1 to n). In this case, the write drivers/sinkers D/S_A and D/S_B are laid out between sub-arrays A sub   _   1  to A sub   _   n  and the column selector  16 . 
     In addition, the power lines PSL for supplying, for example, the drive potential V dd   _   W1 and the ground potential V ss  to the write drivers/sinkers D/S_A and D/S_B are disposed above the write drivers/sinkers D/S_A and D/S_B and extend in the first direction. 
     The SOT-MRAM shown in  FIG. 26  has the shared word line architecture and the column direction extending architecture, similarly to the SOT-MRAM shown in  FIG. 25 . 
     However, the example shown in  FIG. 26  is different from the example shown in  FIG. 25  with respect to features that the write drivers/sinkers D/S_A are laid out at one of ends (i.e., the end portion on the side where the column selectors  16  do not exist) of the sub-arrays A sub   _   1  to A sub   _   n  and that the write drivers/sinkers D/S_B are laid out at the other end (i.e., the end portion on the side where the column selectors  16  exist) of the sub-arrays A sub   _   1  to A sub   _   n . 
     In addition, the power lines PSL for supplying, for example, the drive potential V dd   _   W1  and the ground potential V ss  to the write drivers/sinkers D/S_A are disposed above the write drivers/sinkers D/S_A and extend in the first direction. The power lines PSL for supplying, for example, the drive potential V dd   _   W1  and the ground potential V ss  to the write drivers/sinkers D/S_B are disposed above the write drivers/sinkers D/S_B and extend in the first direction. 
     The SOT-MRAM shown in  FIG. 27  has the shared word line architecture and the column direction extending architecture, similarly to the SOT-MRAM shown in  FIG. 26 . 
     However, the example shown in  FIG. 27  is different from the example shown in  FIG. 26  with respect to features that the write drivers/sinkers D/S_A are divided into D/S_A drivers and D/S_A sinkers and that the write drivers/sinkers D/S_B are divided into D/S_B drivers and D/S_B sinkers. 
     In addition, the D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the end portion on the side where the column selectors  16  do not exist) of the sub-arrays A sub   _   1  to A sub   _   n , and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the end portion on the side where the column selectors  16  exist) of the sub-arrays A sub   _   1  to A sub   _   n . 
     The power lines PSL for supplying, for example, the ground potential V ss  to the D/S_A sinkers and the D/S_B sinkers are disposed above the D/S_A sinkers and the D/S_B sinkers and extend in the first direction. The power lines PSL for supplying, for example, the drive potential V dd   _   W1  to the D/S_A drivers and the D/S_B drivers are disposed above the D/S_A drivers and the D/S_B drivers and extend in the first direction. 
     The SOT-MRAM shown in  FIG. 28  has the shared word line architecture, similarly to the SOT-MRAM shown in  FIG. 27 . 
     However, the SOT-MRAM shown in  FIG. 28  has what is called a row direction extending architecture in which the conductive lines WBL 1  to WBL j  and SBL 1  to SBL j  for urging the write current to flow to the conductive line L SOT  shared by the memory cells MC 1  to MC 8  extend in the first direction in which the conductive line WL 1  extends, as compared with the example shown in  FIG. 27 . 
     In this case, the D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the end portion in the first direction) of the sub-arrays A sub   _   1  to A sub   _   n , and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the end portion in the first direction) of the sub-arrays A sub   _   1  to A sub   _   n . 
     As shown in this figure, for example, the D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the left end portion) of the sub-arrays A sub   _   1  to A sub   _   n , and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the right end portion) of the sub-arrays A sub   _   1  to A sub   _   n , in the odd-numbered block BK_k (k is 1, 3, 5, . . . ) 
     The D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the right end portion) of the sub-arrays A sub   _   1  to A sub   _   n , and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the left end portion) of the sub-arrays A sub   _   1  to A sub   _   n , in the even-numbered block BK_k (k is 2, 4, 6, . . . ) 
     The power lines PSL for supplying, for example, the ground potential V ss  to the D/S_A sinkers and the D/S_B sinkers are disposed above the D/S_A sinkers and the D/S_B sinkers and extend in the second direction. The power lines PSL for supplying, for example, the drive potential V dd   _   W1  to the D/S_A drivers and the D/S_B drivers are disposed above the D/S_A drivers and the D/S_B drivers and extend in the second direction. 
       FIGS. 29 to 32  show examples of the D/SA driver, the D/S_B driver, the D/S_A sinker, and the D/S_B sinker shown in  FIGS. 27 and 28 . 
     The D/S_A driver comprises, for example, a P-channel FET controlled by a control signal φ IN , and the D/S_B driver comprises, for example, a P-channel FET controlled by a control signal bφ IN . The D/S_A sinker comprises, for example, an N-channel FET controlled by a control signal φ IN , and the D/S_B sinker comprises, for example, an N-channel FET controlled by a control signal bφ IN . 
     The control signal φ IN  corresponds to the control signal φ IN  output from the selector  36  in  FIG. 16 . The control signal bφ IN  is an inverted signal of the control signal φ IN . 
     In the example shown in  FIG. 27 , of the examples shown in  FIGS. 24 to 28 , the write drivers/sinkers (the D/S_A driver, the D/S_B driver, the D/S_A sinker, and the D/S_B sinker) are provided for each column CoLp. In addition, the power line PSL for supplying V ss  and the power line PSL for supplying V dd   _   W1  are disposed separately from each other. The example shown in  FIG. 27  is therefore considered most desirable. 
     Second Example 
       FIG. 33  shows a second example of the SOT-MRAM. 
     The SOT-MRAM  13   SOT  comprises an interface  13 - 1 , an internal controller  13 - 2 , a memory cell array  13 - 3  and a word line decoder/driver  17 . The memory cell array  13 - 3  comprises n blocks (memory cores) BK_ 1  to BK_n. n is a natural number of 2 or larger. 
     A command CMD is transferred to the internal controller  13 - 2  via the interface  13 - 1 . The command CMD includes, for example, a first command to instruct the sequential access and a second command to instruct the random access. 
     For example, when the internal controller  13 - 2  receives the command CMD, the internal controller  13 - 2  outputs, for example, control signals WE, RE, WE1/2, W sel , R sel , RE 1  to RE n , and SE 1  to SE n , to execute the command CMD. The meaning and roles of the control signals will be explained later. 
     An address signal Addr is transferred to the internal controller  13 - 2  via the interface  13 - 1 . The address signal Addr is divided into a row address A row  and column addresses A col   _   1  to A col   _   n  in the interface  13 - 1 . The row address A row  is transferred to the word line decoder/driver  17 . The column addresses A col   _   1  to A col   _   n  are transferred to n blocks BK_ 1  to BK_n. 
     DA is read data or write data transmitted or received in the read operation or the write operation. The I/O width (bit width) between the interface  13 - 1  and each of the blocks BK_k (k is one of 1 to n) is N bits at the N-bit access or 1 bit at the single-bit access as explained above. 
     Each of the blocks BK_k includes a sub-array A sub   _   k , a read/write circuit  15 , and a column selector  16 . 
     The column selector  16  selects one of j columns (j is a natural number of 2 or larger) CoL 1  to CoL j  and connects the selected column CoL p  (p is one of 1 of j) to the read/write circuit  15 . For example, if the selected column CoL p  is CoL 1 , conductive lines LBL 1 , SBL 1  and WBL 1  are electrically connected to the read/write circuit  15  via the column selector  16 , as conductive lines LBL, SBL and WBL. 
     The sub-array A sub   _   k  comprises, for example, memory cells M 11  (MC 1  to MC 8 ) to M 1   j  (MC 1  to MC 8 ), and M i1  (MC 1  to MC 8 ) to M ij  (MC 1  to MC 8 ). 
     An example of the sub-array A sub   _   k  will be explained with an equivalent circuit of a sub-array A sub   _   1  shown in  FIG. 34A . 
     M 11  (MC 1  to MC 8 ) to M 1j  (MC 1  to MC 8 ), M i1  (MC 1  to MC 8 ) to M ij  (MC 1  to MC 8 ), WL 11  to WL 18 , WL i1  to WL i8 , SWL 1  to SWL i , SBL 1  to SBL j , WBL j  to WBL j , LBL 1  to LBL 8 , Q W , and Q S  shown in  FIG. 34A  correspond to M 11  (MC 1  to MC 8 ) to M 1j  (MC 1  to MC 8 ), M i1  (MC 1  to MC 8 ) to M ij  (MC 1  to MC 8 ), WL 11  to WL 18 , WL i1  to WL i8 , SWL 1  to SWL i , SBL 1  to SBL j , WBL 1  to WBL j , LBL 1  to LBL j , Q W , and Q S  shown in  FIG. 33 , respectively. 
     Conductive lines L SOT  extend in the first direction. The cell unit M ij  corresponds to the conductive line L SOT  and comprises the memory cells MC 1  to MC 8 . The number of memory cells MC 1  to MC 8  corresponds to N of the N-bit access. The number of memory cells MC 1  to MC 8  is eight in the present example but is not limited to this. For example, the number of memory cells MC 1  to MC 8  may be two or larger. 
     The memory cells MC 1  to MC 8  comprise storage elements MTJ 1  to MTJ 8  and transistors T 1  to T 8 , respectively. 
     Each of the storage elements MTJ 1  to MTJ 8  is a magnetoresistive element. For example, each of the storage elements MTJ 1  to MTJ 8  comprises a first magnetic layer (storage layer) having a variable magnetization direction, a second magnetic layer (reference layer) having an invariable magnetization direction, and a nonmagnetic layer (tunnel barrier layer) between the first and second magnetic layers, and the first magnetic layer is in contact with the conductive line L SOT . 
     In this case, the conductive line L SOT  desirably has the material and the thickness which enable the magnetization direction of the first magnetic layers of the storage elements MTJ 1  to MTJ 8  to be controlled by spin orbit coupling or the Rashba effect. For example, the conductive line L SOT  contains tantalum (Ta), tungsten (W), platinum (Pt) and the like and has a thickness in a range of 5 to 20 mm (for example, approximately 10 nm). The conductive line L SOT  may be formed in a multilayer structure of two or more layers including a layer of metals such as hafnium (Hf), magnesium (Mg), titanium (Ti) and the like in addition to a layer of the metals such as tantalum (Ta), tungsten (W), platinum (Pt) and the like. Furthermore, the conductive line L SOT  may be formed in a multilayer structure of two or more layers including layers formed of single metallic elements of the above but different in crystal structure or a layer in which a single metallic element of the above is oxidized or nitrided. 
     Each of transistors T 1  to T 8  is, for example, an N-channel FET. The transistors T 1  to T 8  are desirably so called vertical transistors which are disposed above the semiconductor substrate and in which channels (current paths) intersect the surface of the semiconductor substrate in the vertical direction. 
     The storage element MTJ d  (d is one of 1 to 8) comprises a first terminal (storage layer) and a second terminal (reference layer), and the first terminal is connected to the conductive line L SOT . The transistor Td comprises a third terminal (source/drain), a fourth terminal (source/drain), a channel (current path) between the third and fourth terminals, and a control electrode (gate) which controls occurrence of a channel, and the third terminal is connected to a second terminal. 
     The conductive lines WL 11  to WL 18  and WL i1  to WL i8  extend in the second direction intersecting the first direction and are connected to the control electrodes of the transistors T 1  to T 8 . The conductive lines LBL 1  to LBL j  extend in the first direction and are connected to the fourth terminals of the transistors T 1  to T 8 , respectively. 
     Each of the conductive lines L SOT  has first and second end portions. 
     Each of the transistors Q S  comprises a channel (current path) connected between the first end portion of the conductive line L SOT  and the conductive lines SBL 1  to SBL j , and a control terminal (gate) which controls generation of the channel. Each of the transistors Q W  comprises a channel (current path) connected between the second end portion of the conductive line L SOT  and the conductive lines SBL 1  to SBL j , and a control terminal (gate) which controls generation of the channel. 
     The conductive lines SWL 1  to SWL i  extend in the second direction and are connected to the control electrodes of the transistors Q S  and Q W . The conductive lines SBL 1  to SBL j  and WBL 1  to WBL j  extend in the first direction. 
     In the present embodiments, the transistor Q S  is connected to the first end portion of the conductive line L SOT  and the transistor Q W  is connected to the second end portion of the conductive line L SOT , but one of them may be omitted. 
     In addition, the transistors T 1  to T 8  can be replaced with diodes D 1  to D 8  as shown in  FIG. 34B . 
     According to the present embodiments, the architecture or the layout for putting SOT-MRAM to practical use is implemented. The nonvolatile MRAM which can be used in various systems can be thereby implemented. 
       FIGS. 35 to 37  show examples of a device structure of the SOT-MRAM. 
     In these figures, M ij  (MC 1  to MC 8 , MTJ 1  to MTJ 8 , T 1  to T 8 ), WL i1  to WL i8 , SWL i , SBL j , LBL j , Q W , and Q S  correspond to M ij  (MC 1  to MC 8 , MTJ 1  to MTJ 8 , T 1  to T 8 ), WL i1  to WL i8 , SWL i , SBL j , WBL j , LBL j , Q W , and Q S  shown in  FIG. 33  and  FIG. 34A , respectively. 
     In the example shown in  FIG. 35 , the conductive line L SOT  is disposed above the semiconductor substrate  21 , and each of the transistors Q S  and Q W  is disposed as what is called a horizontal transistor (FET) in the surface area of the semiconductor substrate  21 . 
     The storage elements MTJ 1  to MTJ 8  are disposed on the conductive line L SOT  and the transistors T 1  to T 8  are disposed on the storage elements MTJ 1  to MTJ 8 , respectively. The transistors T 1  to T 8  are so called vertical transistors. In addition, the conductive lines LBL j , SBL j  and WBL j  are disposed on the transistors T 1  to T 8 . 
     In the example shown in  FIG. 36 , the conductive line L SOT  is disposed above the semiconductor substrate  21 , and the transistors Q S  and Q W  and the storage elements MTJ 1  to MTJ 8  are disposed on the conductive line L SOT . The transistors T 1  to T 8  are disposed on the storage elements MTJ 1  to MTJ 8 , respectively. The transistors Q S , Q W , and T 1  to T 8  are so called vertical transistors. 
     In addition, the conductive line LBL j  is disposed on the transistors T 1  to T 8 , and the conductive lines SBL j  and WBL j  are disposed on the transistors Q S  and Q W . 
     In the example shown in  FIG. 37 , the conductive lines LBL j , SBL j  and WBL j  are disposed above the semiconductor substrate  21 . The transistors T 1  to T 8  are disposed on the conductive line LBL j , and the transistors Q S  and Q W  are disposed on the conductive lines SBL j  and WBL j . The storage elements MTJ 1  to MTJ 8  are disposed on the transistors T 1  to T 8 , respectively. 
     The conductive line L SOT  is disposed on the transistors T 1  to T 8 , Q S  and Q W . The transistors Q S , Q W , and T 1  to T 8  are so called vertical transistors. 
     In the examples of  FIGS. 35 to 37 , each of the storage elements MTJ 1  to MTJ 8  comprises a first magnetic layer (storage layer)  22  having a variable magnetization direction, a second magnetic layer (reference layer)  23  having an invariable magnetization direction, and a nonmagnetic layer (tunnel barrier layer)  24  between the first magnetic layer  22  and the second magnetic layer  23 , and the first magnetic layer  22  is in contact with the conductive line L SOT . 
     In addition, each of the first magnetic layer  22  and the second magnetic layer  23  has an easy-axis of magnetization in an in-plane direction along the surface of the semiconductor substrate  21  and in the second direction intersecting the first direction in which the conductive line L SOT  extends. 
     The structure explained with reference to  FIGS. 12 to 14  can be employed as an example of the device structure of each memory cell shown in  FIG. 35  and  FIG. 36 . In addition, the structure shown in  FIGS. 12 to 14  may be turned upside down to obtain the device structure of each memory cell shown in  FIG. 37 . 
     The characteristic of the memory cell shown in  FIGS. 12 to 14  is that the current path of the read current I read  used in the read operation is different from the current path of the write current I write  used in the write operation. As explained in the first example, even if both the read current I read  and the write current I write  become small due to microminiaturization of the memory cell or the like, the margin of both the currents can be sufficiently secured in consideration of the thermal stability Δ. 
       FIG. 38  shows an example of the word line decoder/driver shown in  FIG. 33 . 
     The word line decoder/driver  17  has a function of activating or deactivating the conductive lines WL 11  to WL 18 , WL i1  to WL i8  and SWL 1  to SWL i  in the read operation or the write operation. 
     An OR circuit  31  and AND circuits  32   1  to  32   i ,  32   11  to  32   18 ,  32   i1  to  32   i8 ,  32 ′ 11  to  32 ′ 18 , and  32 ′ i1  to  32 ′ i8  are decoder circuits. 
     In the read operation, for example, a read enable signal RE from the internal controller  13 - 2  shown in  FIG. 33  becomes active (1). In the write operation, a write enable signal WE from the internal controller  13 - 2  shown in  FIG. 33  becomes active (1). 
     The row address signal A row  has, for example, R bits (R is a natural number of 2 or more) and has a relationship i (number of rows)=2 R . 
     In the read operation or the write operation, all bits (R bits) of one of the row address signals A row1  to A rowi  become 1 when the row address signal A row  is input to the word line decoder/driver  17 . 
     For example, if the row address signal A row  is 00 . . . 00 (all 0), the output signal of the AND circuit  32   1  becomes 1 since all the bits of the row address signal A row1  become 1. In this case, the drive circuit  34   1  sets the conductive line SWL 1  to be active. In addition, if the row address signal A row  is 11 . . . 11 (all 1), the output signal of the AND circuit  32   i  becomes 1 since all the bits of the row address signal A rowi  become 1. In this case, the drive circuit  34   i  sets the conductive line SWL i  to be active. 
     A ROM  37 , a data register  38 , a selector (multiplexer)  39  and a mask register  40  are elements used in the write operation. The ROM  37 , the data register  38 , the selector (multiplexer)  39  and the mask register  40  control setting the conductive lines WL 11  to WL 18  and WL i1  to WL i8  to be active/nonactive, in the row selected by the row address signal A row . This will be explained later. 
     A shift register  43  is an element used in the read operation. The shift register  43  controls setting the conductive lines WL 11  to WL 18  and WL i1  to WL i8  to be active/nonactive, in the row selected by the row address signal A row . This will also be explained later. 
     Drive circuits  33   11  to  33   18 ,  33   i1  to  33   i8 ,  33 ′ 11  to  33 ′ 18 , and  33 ′ i1  to  33 ′ i8  correspond to AND circuits  32   11  to  32   18 ,  32   i1  to  32   i8 ,  32 ′ 11  to  32 ′ 18 , and  32 ′ i1  to  32 ′ i8 , respectively. 
     When an output signal of the AND circuit  32   1  is active (1), output signals of the AND circuits  32   11  to  32   18  and  32 ′ 11  to  32 ′ 18  can be active. In addition, when an output signal of the AND circuit  32   i  is active (1), output signals of the AND circuits  32   i1  to  32   i8  and  32 ′ i1  to  32 ′ i8  can be active. 
       FIG. 39  shows an example of the read/write circuit shown in  FIG. 33 . 
     In the read operation or the write operation, the read/write circuit  15  selects one of the multi-bit access and the single-bit access and executes the read operation or the write operation, based on an instruction from the internal controller  13 - 2  shown in  FIG. 33 . 
     The read/write circuit  15  comprises a read circuit and a write circuit. 
     The write circuit comprises a ROM  35 , a selector (multiplexer)  36 , write drivers/sinkers D/SA and D/S_B, a transfer gate TG, and a voltage assist driver  42 . 
     The write drivers/sinkers D/S_A and D/S_B have a function of urging one of a first write current and a second write current in mutually opposite directions to be generated in, for example, the conductive line L SOT  shown in  FIGS. 35 to 37 . 
     The first write current is a current for, for example, writing 0 to the storage elements MTJ 1  to MTJ 8  shown in  FIGS. 35 to 37 , i.e., setting a relationship between the magnetization directions of the first magnetic layer  22  and the second magnetic layer  23  of the storage elements MTJ 1  to MTJ 8  shown in  FIGS. 35 to 37  to be in a parallel state, by the spin orbit coupling or the Rashba effect. 
     The second write current is a current for, for example, writing 1 to the storage elements MTJ 1  to MTJ 8  shown in  FIGS. 35 to 37 , i.e., setting the relationship between the magnetization directions of the first magnetic layer  22  and the second magnetic layer  23  of the storage elements MTJ 1  to MTJ 8  shown in  FIGS. 35 to 37  to be in an antiparallel state, by the spin orbit coupling or the Rashba effect. 
     The voltage assist driver  42  has a function of applying a voltage for facilitating the write operation to the storage elements MTJ 1  to MTJ 8  in the 0/1-write operation using the first and second write currents. 
     For example, when the voltage assist driver  42  applies an assist potential V dd   _   W2  to, for example, LBL j  shown in  FIGS. 35 to 37 , a voltage which destabilizes the magnetization direction of the first magnetic layer (storage layer)  22  is selectively generated depending on turning on/off the transistors T 1  to T 8 . 
     The read circuit comprises a sense circuit  45  and a shift register  46 . 
     The read driver  44  has a function of applying a select potential V dd   _   r  for urging the read current to be generated to, for example, the conductive line LBL j  shown in  FIGS. 35 to 37 . 
     For example, when the read driver  44  applies the select potential V dd   _   r  to, for example, LBL j  shown in  FIGS. 35 to 37 , the read driver  44  can urge the read current to selectively flow to the storage elements MTJ 1  to MTJ 8  depending on turning on/off the transistors T 1  to T 8 . 
     One sense circuit  45  is disposed in, for example, one read/write circuit  15 . In other words, only one sense circuit  45  is disposed in one block (memory core) BK_k. 
     The sense circuit  45  comprises, for example, a sense amplifier SA n , a clamp transistor (for example, N-channel FET) Q clamp , an equalizing transistor (for example, N-channel FET) Q equ , and a reset transistor (for example, N-channel FET) Q rst  as shown in  FIG. 17 . 
     The sense circuit  45  is not explained here since the circuit has been explained in the first example of the SOT MRAM. 
     Next, an example of the read operation and an example of the write operation using the word line decoder/driver  17  shown in  FIG. 38  and the read/write circuit  15  shown in  FIG. 39  will be explained. 
     *Write Operation 
     [Multi-Bit Access] 
     When the internal controller  13 - 2  shown in  FIG. 33  receives, for example, the write command CMD of the sequential access, the internal controller  13 - 2  controls the write operation using the multi-bit access. The internal controller  13 - 2  executes the write operation using the multi-bit access by the first write operation and the second write operation. 
     The first write operation is an operation of writing the same data (for example, 0) at multi-bits (for example, 8 bits) which are the interests of write. 
     First, the write enable signal WE becomes 1 and the output signal of the OR circuit  31  becomes 1 in the word line decoder/driver  17  shown in  FIG. 38 . For example, if all the bits of the row address signal A row  are 1 (11 . . . 11), all the bits of the row address signal A rowi  become 1 and the output signal of the AND circuit  32   i  becomes 1. In this case, the drive circuit  34   i  activates the conductive line SWL i . 
     In addition, the internal controller  13 - 2  shown in  FIG. 33  sets, for example, the control signal WE1/2 at 0. The control signal WE1/2 is a signal for selecting one of the first write operation and the second write operation and, for example, when the control signal WE1/2 is 0, the first write operation is selected. 
     In other words, the selector  39  selects the ROM  37  and outputs all 1 (11111111) as the ROM data. In addition, the internal controller  13 - 2  shown in  FIG. 33  sets the value of the mask register  40  at all 1 (11111111) by using, for example, the control signal W sel , at the multi-bit access. 
     Therefore, when an output signal of the AND circuit  32   i  is 1, all the AND circuits  32   i1  to  32   i8  output 1 as the output signals. In this case, the drivers  33   i1  to  33   i8  activate the conductive lines WL i1  to WL i8 . 
     In contrast, the selector  36  selects and outputs 0 from the ROM  35  as the ROM data, in the read/write circuit  15  shown in  FIG. 39 . Therefore, the write driver/sinker D/S_A outputs, for example, the drive potential V dd   _   W1  as the write pulse signal and the write driver/sinker D/S_B outputs, for example, the ground potential V ss . 
     In addition, in the write operation, the transfer gate TG is on since the control signal WE n  becomes active (high level). 
     Therefore, the write pulse signal is applied to the conductive line WBL via the transfer gate TG and the ground potential V 55  is applied to the conductive line SBL via the transfer gate TG. At this time, if the column selected by the column selector  16  shown in  FIG. 33  is assumed to be CoL j , the write current (first write current) I write  flows from the conductive line WBL j  to the conductive line SBL j , i.e., from the right side to the left side in the conductive line L SOT , as shown in, for example,  FIG. 40 . 
     In addition, in the read/write circuit  15  shown in  FIG. 39 , the driver  42  applies the assist potential V dd   _   W2  to the conductive line LBL since the control signal φWE becomes active (1). 
     In the first write operation, all the transistors T 1  to T 8  are on since all the conductive lines WL i1  to WL i8  are activated as shown in, for example,  FIG. 40 . This means that the write current (first write current) I write  flows in a state in which the assist potential V dd   _   W2  is applied to all the storage elements MTJ 1  to MTJ 8 . 
     As a result, the same data is written at all the multi-bits (for example, 8 bits) that are the interests of write, in the first write operation. However, it is assumed that 0 is written, i.e., all the storage elements MTJ 1  to MTJ 8  become in a parallel state in the first write operation. 
     The second write operation is an operation of urging the same data (for example, 0) written at multi-bits (for example, 8 bits) which are the interests of write, to be held (for example, if the write data is 0) or to be changed from 0 to 1 (for example, if the write data is 1) in accordance with the write data. 
     First, the internal controller  13 - 2  shown in  FIG. 33  sets, for example, the control signal WE1/2 at 1. For example, when the control signal WE1/2 is 1, the second write operation is selected. 
     In this case, the selector  39  selects the data register  38  and outputs the write data (for example, 01011100) stored in the data register  38 , in the word line decoder/driver  17  shown in  FIG. 38 . The write data is preliminarily stored in the data register  38  before the second write operation is executed. In addition, the internal controller  13 - 2  shown in  FIG. 33  sets the value of the mask register  40  at all 1 (11111111) by using, for example, the control signal W sel , at the multi-bit access. 
     The AND circuits  32   i1  to  32   i8  therefore output the output signal (for example, 01011100) corresponding to the write data. At this time, for example, the drivers  33   i1  to  33   18  activate the corresponding conductive lines WL i1  to WL i8  when the write data is 1 or deactivate the corresponding conductive lines WL i1  to WL i8  when the write data is 0. 
     In addition, the selector  36  selects and outputs 1 from the ROM  35  as the ROM data, in the read/write circuit  15  shown in  FIG. 39 . Therefore, the write driver/sinker D/S_B outputs, for example, the drive potential V dd   _   W1  as the write pulse signal and the write driver/sinker D/S_A outputs, for example, the ground potential V ss . 
     The write pulse signal is applied to the conductive line SBL via the transfer gate TG and the ground potential V ss  is applied to the conductive line WBL via the transfer gate TG. In addition, the driver  42  applies the assist potential V dd   _   W2  to the conductive line LBL since the control signal φ WE  becomes active (1). 
     At this time, if the column selected by the column selector  16  shown in  FIG. 33  is assumed to be CoL j , the write current (second write current) I write  flows from the conductive line SBL j  to the conductive line WBL j , i.e., from the left side to the right side in the conductive line L SOT , as shown in, for example,  FIG. 41 . 
     In other words, for example, if the write data is 01011100, the transistors T 1 , T 3 , T 7 , and T 8  become OFF and the transistors T 2 , T 4 , T 5 , and T 6  become ON, as shown in  FIG. 41 . In addition, the write current (second write current) I write  flows from the conductive line SBL j  to the conductive line WBL j  in a state in which the assist potential V dd   _   W2  is applied to the storage elements MTJ 2 , MTJ 4 , MTJ 5 , and MTJ 6 . 
     As a result, 0 is held, i.e., 0 is written as the data of the storage elements MTJ 1 , MTJ 3 , MTJ 7  and MTJ 8 , of the multi-bits (for example, 8 bits) which are the interests of write, in the second write operation. In addition, 0 is changed to 1, i.e., 1 is written as the data of the storage elements MTJ 2 , MTJ 4 , MTJ 5  and MTJ 6 , of the multi-bits (for example, 8 bits) which are the interests of write. 
     However, it is assumed that 1 is selectively written to the storage elements MTJ 1  to MTJ 8 , i.e., the state of the storage elements MTJ 1  to MTJ 8  is selectively changed from the parallel state to the antiparallel state, in the second write operation. 
     [Single-Bit Access] 
     When the internal controller  13 - 2  shown in  FIG. 33  receives, for example, the write command CMD of the random access, the internal controller  13 - 2  controls the write operation using the single-bit access. The internal controller  13 - 2  executes the write operation using the single-bit access by the first write operation and the second write operation. 
     The first write operation is an operation of writing predetermined data (for example, 0) at the single bit which is the interest of write. 
     First, the output signal of the OR circuit  31  becomes 1 in the word line decoder/driver  17  shown in  FIG. 38 . For example, if all the bits of the row address signal A row  are 1 (11 . . . 11), the output signal of the AND circuit  32   i  becomes 1. The conductive lines SWL i  is therefore activated by the driver  34   i . 
     Next, the internal controller  13 - 2  shown in  FIG. 33  sets, for example, the control signal WE1/2 at 0. For example, when the control signal WE1/2 is 0, the first write operation is selected. 
     In this case, the selector  39  selects the ROM  37  and outputs all 1 (11111111) as the ROM data, in the word line decoder/driver  17  shown in  FIG. 38 . In addition, the internal controller  13 - 2  shown in  FIG. 33  sets selected one bit, of eight bits stored in the mask register  40 , at 1 by using, for example, the control signal W sel , at the single-bit access. 
     For example, when the storage element MTJ 4  is an interest of write, 1 bit corresponding to the storage element MTJ 4 , of 8 bits stored in the mask register  40 , is set at 1. In this case, 8 bits stored in the mask register  40  becomes, for example, 00010000. 
     Therefore, the AND circuit  32   i4 , of the AND circuits  32   i1  to  32   i8 , outputs 1 as the output signal and the remaining AND circuits  32   i1  to  32   i3  and  32   i5  to  32   i8  output 0 as the output signals. At this time, the driver  33   i4 , of the drivers  33   i1  to  33   i8 , activate the conductive line WL i4  and the remaining drivers  33   11  to  33   i3  and  33   i5  to  33   i8  deactivate the conductive lines WL i1  to WL i3  and WL i5  to WL i8 . 
     In addition, the selector  36  selects and outputs 0 from the ROM  35  as the ROM data, in the read/write circuit  15  shown in  FIG. 39 . Therefore, the write driver/sinker D/S_A outputs, for example, the drive potential V dd   _   W1  as the write pulse signal and the write driver/sinker D/S_B outputs, for example, the ground potential V ss . 
     The write pulse signal is applied to the conductive line WBL via the transfer gate TG and the ground potential V ss  is applied to the conductive line SBL via the transfer gate TG. In addition, the driver  42  applies the assist potential V dd   _   W2  to the conductive line LBL since the control signal φ WE  becomes active (1). 
     At this time, if the column selected by the column selector  16  shown in  FIG. 33  is assumed to be CoL j , the write current (first write current) I write  flows from the conductive line WBL j  to the conductive line SBL j , i.e., from the right side to the left side in the conductive line L SOT , as shown in, for example,  FIG. 42 . 
     In other words, for example, the write current (first write current) I write  flows from the conductive line WBL j  to the conductive line SBL j  in a state in which the assist potential V dd   _   W2  is applied to the storage element MTJ 4  and the assist potential V dd   _   W2  is not applied to the storage elements MTJ 1  to MTJ 3  and MTJ 5  to MTJ 8 , as shown in  FIG. 42 . 
     As a result, the single bit which is the interest of write, for example, predetermined data (for example, 0) is written to the storage element MTJ 4 , in the first write operation. 
     In addition, the already written data is held in remaining seven bits that are not the interests of write, for example, the storage elements MTJ 1  to MTJ 3  and MTJ 5  to MTJ 8 , by the above mask processing. In other words, the data in the storage elements MTJ 1  to MTJ 3  and MTJ 5  to MTJ 8  is not changed to 0, but the data in the storage elements MTJ 1  to MTJ 3  and MTJ 5  to MTJ 8  is protected, in the first write operation. 
     The second write operation is an operation of urging the predetermined data (for example, 0) written at the single bit which is the interest of write, to be held (for example, if the write data is 0) or to be changed from 0 to 1 (for example, if the write data is 1) in accordance with the write data. 
     First, the conductive lines WL i4  and SWL i  are held in the activated state in the word line decoder/driver  17  shown in  FIG. 38 . 
     Next, the internal controller  13 - 2  shown in  FIG. 33  sets, for example, the control signal WE1/2 at 1. For example, when the control signal WE1/2 is 1, the second write operation is selected. 
     In this case, the selector  36  selects and outputs 1 from the ROM  35  as the ROM data, in the read/write circuit  15  shown in  FIG. 39 . Therefore, the write driver/sinker D/S_B outputs, for example, the drive potential V dd   _   w1  as the write pulse signal and the write driver/sinker D/S_A outputs, for example, the ground potential V ss . 
     The write pulse signal is applied to the conductive line SBL via the transfer gate TG and the ground potential V ss  is applied to the conductive line WBL via the transfer gate TG. In addition, the driver  42  applies the assist potential V dd   _   W2  to the conductive line LBL since the control signal φ WE  becomes active (1). 
     At this time, if the column selected by the column selector  16  shown in  FIG. 33  is assumed to be CoL j , the write current (second write current) I write  flows from the conductive line SBL j  to the conductive line WBL j , i.e., from the left side to the right side in the conductive line L SOT , as shown in, for example,  FIG. 43 . 
     In addition, the selector  39  outputs the write data (for example, xxx1xxxx) stored in the data register  38 , in the word line decoder/driver  17  shown in  FIG. 38 . In this example, x represents invalid data. The write data is preliminarily stored in the data register  38  before the second write operation is executed. In addition, the internal controller  13 - 2  shown in  FIG. 33  sets selected one bit, of eight bits stored in the mask register  40 , at 1 by using, for example, the control signal W sel , at the single-bit access. 
     For example, when the storage element MTJ 4  is an interest of write in the first write operation, 1 bit corresponding to the storage element MTJ 4 , of 8 bits stored in the mask register  40 , is set at 1 in the second write operation, too. In other words, 8 bits stored in the mask register  40  becomes, for example, 00010000. 
     The AND circuit  32   i4 , of the AND circuits  32   i1  to  32   i8 , therefore outputs the output signal (for example, 1) corresponding to the write data. At this time, for example, the driver  33   i4  activates the conductive line WL i4  when the write data is 1 or deactivates the conductive line WL i4  when the write data is 0. 
     In addition, the AND circuits  32   i1  to  32   i3  and  32   i5  to  32   i8 , of the AND circuits  32   i1  to  32   i8 , output, for example, 0. At this time, the drivers  33   i1  to  33   13  and  33   15  to  33   i8  deactivate, for example, the conductive lines WL i1  to WL i3  and WL i5  to WL i8 . 
     In other words, for example, when the write data is xxx1xxxx and the mask data is 00010000, the write current (second write current) I write  flows from the conductive line SBL j  to the conductive line WBL j  in a state in which the assist potential V dd   _   W2  is applied to the storage element MTJ 4  and the assist potential V dd   _   W2  is not applied to the storage elements MTJ 1  to MTJ 3  and MTJ 5  to MTJ 8 , as shown in  FIG. 43 . 
     As a result, the predetermined data (for example, 0) is changed to 1, i.e., 1 is written as the single bit which is the interest of write, for example, the data of the storage element MTJ 4 , in the second write operation. In contrast, when the write data is 0, the predetermined data (for example, 0) is held, i.e., 0 is written as the data of the storage elements MTJ 4 . 
     In addition, the already written data is held in remaining seven bits that are not the interests of write, for example, the storage elements MTJ 1  to MTJ 3  and MTJ 5  to MTJ 8 , by the above mask processing. In other words, the data in the storage elements MTJ 1  to MTJ 3  and MTJ 5  to MTJ 8  is not changed to 1, but the data in the storage elements MTJ 1  to MTJ 3  and MTJ 5  to MTJ 8  is protected, in the second write operation, too. 
     *Read Operation 
     [Multi-Bit Access] 
     When the internal controller  13 - 2  shown in  FIG. 7  receives, for example, the read command CMD of the sequential access, the internal controller  13 - 2  controls the read operation using the multi-bit access. 
     First, the read enable signal RE becomes 1 and the output signal of the OR circuit  31  becomes 1 in the word line decoder/driver  17  shown in  FIG. 38 . For example, if all the bits of the row address signal A row  are 1 (11 . . . 11), the output signal of the AND circuit  32   i  becomes 1. The conductive lines SWL i  is therefore activated by the driver  34   i . 
     Next, the internal controller  13 - 2  shown in  FIG. 7  sets one bit of eight bits stored in the shift register  43  to be 1 sequentially by using, for example, the control signal R sel . In this case, the drivers  33 ′ i1  to  33 ′ i8  sequentially activate the conductive lines WL i1  to WL i8 . 
     For example, the conductive lines WL i1  to WL i8  are activated one by one and seven conductive lines other than the activated conductive line WL id  (d is one of 1 to 8) are deactivated. In addition, φ rst  in  FIG. 17  becomes active and the conductive line SBL is set at the ground potential V ss . 
     In addition, in the read/write circuit  15  shown in  FIG. 39 , the driver  44  applies the select potential V dd   _   r  to the conductive line LBL since the control signal φ RE  becomes active (1). 
     In this case, for example, if the transistor T 1  in the memory cell MC 1  is turned on, the read current I read  flows from the conductive line LBL j  to the conductive line L SOT  via the storage element MTJ 1 , as shown in  FIG. 44 . The data of the storage element MTJ 1  is thereby stored in the shift register  46  via the sense circuit  45  shown in  FIG. 39 . 
     Similarly to this, the data of the storage elements MTJ 2  to MTJ 8  is sequentially stored in the shift register  46  via the sense circuit  45  shown in  FIG. 39  by sequentially setting the transistors T 2  to T 8  to be turned on. 
     As a result, the multi-bits (for example, 8 bits) that are the interests of sequential access are stored in the shift register  46  as the read data (for example, 01011100), by eight read operations. The multi-bits are wholly transferred to the interface  13 - 2  shown in  FIG. 33  as the read data DA. 
     [Single-Bit Access] 
     When the internal controller  13 - 2  shown in  FIG. 7  receives, for example, the read command CMD of the random access, the internal controller  13 - 2  controls the read operation using the single-bit access. 
     First, the read enable signal RE becomes 1 and the output signal of the OR circuit  31  becomes 1 in the word line decoder/driver  17  shown in  FIG. 38 . For example, if all the bits of the row address signal A row  are 1 (11 . . . 11), the output signal of the AND circuit  32   i  becomes 1. The conductive lines SWL i  is therefore activated by the driver  34   i . 
     Next, the internal controller  13 - 2  shown in  FIG. 7  sets one bit which is the interest of read, of eight bits stored in the shift register  43  to be 1 by using, for example, the control signal R sel . For example, if the storage element which is the interest of read is MTJ 4 , the internal controller  13 - 2  shown in  FIG. 7  controls the shift register  43  such that eights stored in the shift register  43  become 00010000. 
     In this case, the driver  33 ′ i4 , of the drivers  33 ′ i1  to  33 ′ 1-8 , activate the conductive line WL i4  and the remaining seven drivers  33 ′ i1  to  33 ′ i3  and  33 ′ i5  to  33 ′ i8  deactivate the conductive lines WL i1  to WL i8  and WL i5  to WL i8 . In addition, φ rst  in  FIG. 17  becomes active and the conductive line SBL is set at the ground potential V ss . 
     Therefore, for example, the read current I read  flows from the conductive line LBL j  to the conductive line L SOT  via the transistor T 4  and the storage element MTJ 4 , as shown in  FIG. 45 . The data of the storage element MTJ 4  is thereby stored in the shift register  46  via the sense circuit  45  shown in  FIG. 39 . As a result, the shift register  46  stores, for example, xxx1xxxx as the read data. 
     The valid data (read data) stored in the shift register  46  is transferred to the interface  13 - 1  shown in  FIG. 33  as the read data DA. 
     Third Example 
       FIGS. 46 to 48  show SOT-MRAM of a third example. 
     This modified example is characterized by employing so called a divided word line structure in the second example, i.e., the SOT-MRAM shown in  FIGS. 33 to 45 . 
       FIG. 46  shows a third example of the SOT-MRAM. 
     The SOT-MRAM  13   SOT  comprises an interface  13 - 1 , an internal controller  13 - 2 , a memory cell array  13 - 3 , a word line decoder/driver  17  and sub-decoders/drivers SD 11  to SD 1n  and SD i1  to SD in . The memory cell array  13 - 3  comprises n blocks (memory cores) BK_ 1  to BK_n. n is a natural number of 2 or larger. 
     A command CMD is transferred to the internal controller  13 - 2  via the interface  13 - 1 . The command CMD includes, for example, a first command to instruct the sequential access and a second command to instruct the random access. 
     When the internal controller  13 - 2  receives the command CMD, the internal controller  13 - 2  outputs, for example, control signals WE, RE, WE1/2, W sel   _   1  to W sel   _   n , R sel   _   1  to R sel   _   n , RE 1  to RE n , and SE 1  to SE n , to execute the command CMD. 
     An address signal Addr is transferred to the internal controller  13 - 2  via the interface  13 - 1 . The address signal Addr is divided into a row address A row  and column addresses A col   _   1  to A col   _   n  in the interface  13 - 1 . The row address A row  is transferred to the word line decoder/driver  17 . The column addresses A col   _   1  to A col   _   n  are transferred to n blocks BK_ 1  to BK_n. 
     DA 1  to DA n  are read data or write data transmitted or received in the read operation or the write operation. The I/O width (bit width) between the interface  13 - 1  and each of the blocks BK_k (k is one of 1 to n) is N bits at the N-bit access or 1 bit at the single-bit access as explained above. 
     Each of the blocks BK_k includes a sub-array A sub   _   k , a read/write circuit  15 , and a column selector  16 . 
     The column selector  16  selects one of j columns (j is a natural number of 2 or larger) CoL 1  to CoL j  and connects the selected column CoL p  (p is one of 1 of j) to the read/write circuit  15 . For example, if the selected column CoL p  is CoL 1 , conductive lines LBL 1 , SBL 1  and WBL j  are electrically connected to the read/write circuit  15  via the column selector  16 , as conductive lines LBL, SBL and WBL. 
     The sub-array A sub   _   k  comprises, for example, memory cells M 11  (MC 1  to MC 8 ) to M 1j  (MC 1  to MC 8 ), and M i1  (MC 1  to MC 8 ) to M ij  (MC 1  to MC 8 ). The sub-array A sub   _   k  is not explained here since the sub-array is the same as the sub-array A sub   _   1  in the second example, for example,  FIG. 34A or 34B . 
       FIG. 47  shows an example of the word line decoder/driver shown in  FIG. 46 . 
     The word line decoder/driver  17  has a function of activating or deactivating conductive lines SWL 1  to SWL i  and global conductive lines GWL 1  to GWL i  in the read operation or the write operation. 
     An OR circuit  31  and AND circuits  32   1  to  32   i  are decoder circuits. 
     In the read operation, for example, a read enable signal RE from the internal controller  13 - 2  shown in  FIG. 46  becomes active (1). In the write operation, a write enable signal WE from the internal controller  13 - 2  shown in  FIG. 46  becomes active (1). 
     The row address signal A row  has, for example, R bits (R is a natural number of 2 or more) and has a relationship i (number of rows)=2 R . 
     In the read operation or the write operation, all bits (R bits) of one of the row address signals A row1  to A rowi  become 1 when the row address signal A row  is input to the word line decoder/driver  17 . 
     For example, if the row address signal A row  is 00 . . . 00 (all 0), the output signal of the AND circuit  321  becomes 1 since all the bits of the row address signal A row1  become 1. In this case, the drive circuit  331  sets the global conductive line GWL 1  to be active and the drive circuit  34   1  sets the conductive line SWL 1  to be active. 
     In addition, if the row address signal A row  is 11 . . . 11 (all 1), the output signal of the AND circuit  32   i  becomes 1 since all the bits of the row address signal A rowi  become 1. In this case, the drive circuit  33   i  sets the global conductive line GWL i  to be active and the drive circuit  34   i  sets the conductive line SWL i  to be active. 
       FIG. 48  shows an example of the sub-decoder/driver shown in  FIG. 46 . 
     The sub-decoder/driver SD 11  has a function of activating or deactivating the conductive lines WL 11  to WL 18  and WL i1  to WL i8  in the read operation or the write operation. 
     A ROM  37 , a data register  38 , a selector (multiplexer)  39  and a mask register  40  are elements used in the write operation. The ROM  37 , the data register  38 , the selector (multiplexer)  39  and the mask register  40  control setting the conductive lines WL 11  to WL 18  and WL i1  to WL i8  to be active/nonactive, in the row selected by the row address signal A row . 
     A shift register  43  is an element used in the read operation. The shift register  43  controls setting the conductive lines WL 11  to WL 18  and WL i1  to WL i8  to be active/nonactive, in the row selected by the row address signal A row . 
     Drive circuits  33   11  to  33   18 ,  33   11  to  33   i8 ,  33 ′ 11  to  33 ′ 18 , and  33 ′ i1  to  33 ′ i8  correspond to AND circuits  32   11  to  32   18 ,  32   i1  to  32   i8 ,  32 ′ 11  to  32 ′ 18 , and  32 ′ i1  to  32 ′ i8 , respectively. 
     When an output signal of the AND circuit  32   1  shown in  FIG. 47  is active (1) and the global conductive line GWL 1  is activated, output signals of the AND circuits  32   11  to  32   18  and  32 ′ 11  to  32 ′ 18  can be active. In addition, when an output signal of the AND circuit  32   i  shown in  FIG. 47  is active (1) and the global conductive line GWL i  is activated, output signals of the AND circuits  32   i1  to  32   i8  and  32 ′ i1  to  32 ′ i8  can be active. 
     The read/write circuit  15  shown in  FIG. 46  is not explained here since the circuit is the same as the read/write circuit  15  shown in  FIG. 39  explained in the second example. 
     In addition, an example of the read operation and an example of the write operation using the word line decoder/driver  17  shown in  FIG. 47 , the sub-decoder/driver SD 11  shown in  FIG. 48  and the read/write circuit  15  shown in  FIG. 39  are not explained here since the examples are the same as the example of the read operation and the example of the write operation explained in the second example. 
     In the second example (shared bit line architecture), the write data cannot be written parallel to the sub-arrays A sub   _   1  to A sub   _   n . In contrast, in the third example (shared bit line architecture and divided word line structure), the write data can be written parallel for the sub-arrays A sub   _   1  to A sub   _   n . 
       FIG. 49  shows a comparison among the first example ( FIG. 7 ), the second example ( FIG. 33 ) and the third example ( FIG. 46 ). 
     In the first example (shared word line architecture) shown in  FIG. 7 , the write data is written to the memory cells MC 1  to MC 8  by, for example, controlling the electric potentials of the conductive lines LBL 1  to LBL 8  from the column side. In the first example shown in  FIG. 7 , the write data can be therefore written parallel to the sub-arrays A sub   _   1  to A sub   _   n . 
     In the sub-arrays A sub   _   1  to A sub   _   n , however, the memory cells MC 1  to MC 8  which are the interests of write are limited in the same row selected by the word line decoder/driver  17 . 
     In contrast, in the second example (shared word line architecture) shown in  FIG. 33 , the write data is written to the memory cells MC 1  to MC 8  by, for example, controlling the electric potentials of the conductive lines WL i1  to WL i8  from the row side. In the second example shown in  FIG. 33 , the write data cannot be therefore written parallel to the sub-arrays A sub   _   1  to A sub   _   n . 
     It is the third example which solves the problem of the second example. 
     In the third example (shared bit line architecture and divided word line structure) shown in  FIG. 46 , the write data is written to the memory cells MC 1  to MC 8  by, for example, controlling the electric potentials of the conductive lines WL i1  to WL i8  from the row side. In the third example unlike the second example, however, for example, the sub-decoders/drivers SD 11  to SD 1n  are provided to correspond to the sub-arrays A sub   _   1  to A sub   _   n , respectively. 
     Therefore, the write data is written to the memory cells MC 1  to MC 8  by, for example, controlling the electric potentials of the conductive lines WL i1  to WL i8  for each of the sub-arrays A sub   _   1  to A sub   _   n  by using the sub-arrays A sub   _   1  to A sub   _   n . 
     In other words, the write data can be written parallel to the sub-arrays A sub   _   1  to A sub   _   n  in the third example shown in  FIG. 46 . 
     In the sub-arrays A sub   _   1  to A sub   _   n , however, the memory cells MC 1  to MC 8  which are the interests of write are limited in the same row selected by the word line decoder/driver  17 . 
     (Layout) 
       FIG. 50  is a diagram simply showing the SOT-MRAM explained with reference to  FIGS. 33 to 49 .  FIGS. 51 to 54  show a modified example of the SOT-MRAM shown in  FIG. 50 . An example of the layout of the write drivers/sinkers D/S_A and D/S_B will be explained here. 
     The same elements as those shown in, for example,  FIG. 33  or  FIG. 46  are denoted by the same referential numbers in  FIGS. 50 to 54  and their detailed explanations are omitted. 
     The SOT-MRAM shown in  FIG. 50  has, for example, what is called a shared bit line architecture in which the memory cells MC 1  to MC 8  accessed parallel at the multi-bit access share one conductive line (bit line) LBL selecting the memory cells MC 1  to MC 8 . 
     In addition, the SOT-MRAM shown in  FIG. 50  has what is called a column direction extending architecture in which the conductive lines WBL 1  to WBL j  and SBL 1  to SBL j  for urging the write current to flow to the conductive line L SOT  shared by the memory cells MC 1  to MC 8  extend in the first direction in which the conductive line LBL 1  extends. 
     In this case, the write drivers/sinkers D/S_A and D/S_B are disposed in the read/write circuit  15  in each block (memory core) BK_k (k is one of 1 to n). The write drivers/sinkers D/S_A and D/S_B are shared by the columns CoL 1  to CoL j . 
     In addition, the power lines PSL for supplying, for example, the drive potential V dd   _   W1  and the ground potential V ss  to the write drivers/sinkers D/S_A and D/S_B are disposed above the read/write circuit  15  and extend in the second direction intersecting the first direction. 
     The SOT-MRAM shown in  FIG. 51  has the shared bit line architecture and the column direction extending architecture, similarly to the SOT-MRAM shown in  FIG. 50 . 
     However, the write drivers/sinkers D/S_A and D/S_B are provided for each column CoL p  (p is one of 1 to j) in the block BK_k (k is one of 1 to n). In this case, the write drivers/sinkers D/S_A and D/S_B are laid out between sub-arrays A sub   _   1  to A sub   _   n  and the column selector  16 . 
     In addition, the power lines PSL for supplying, for example, the drive potential V dd   _   W1  and the ground potential V ss  to the write drivers/sinkers D/S_A and D/S_B are disposed above the write drivers/sinkers D/S_A and D/S_B and extend in the second direction. 
     The SOT-MRAM shown in  FIG. 52  has the shared bit line architecture and the column direction extending architecture, similarly to the SOT-MRAM shown in  FIG. 51 . 
     However, the example shown in  FIG. 52  is different from the example shown in  FIG. 51  with respect to features that the write drivers/sinkers D/S_A are laid out at one of ends (i.e., the end portion on the side where the column selectors  16  do not exist) of the sub-arrays A sub   _   1  to A sub   _   n  and that the write drivers/sinkers D/S_B are laid out at the other end (i.e., the end portion on the side where the column selectors  16  exist) of the sub-arrays A sub   _   1  to A sub   _   n . 
     In addition, the power lines PSL for supplying, for example, the drive potential V dd   _   W1  and the ground potential V ss  to the write drivers/sinkers D/S_A are disposed above the write drivers/sinkers D/S_A and extend in the second direction. The power lines PSL for supplying, for example, the drive potential V dd   _   W1  and the ground potential V ss  to the write drivers/sinkers D/S_B are disposed above the write drivers/sinkers D/S_B and extend in the second direction. 
     The SOT-MRAM shown in  FIG. 53  has the shared bit line architecture and the column direction extending architecture, similarly to the SOT-MRAM shown in  FIG. 52 . 
     However, the example shown in  FIG. 53  is different from the example shown in  FIG. 52  with respect to features that the write drivers/sinkers D/S_A are divided into D/S_A drivers and D/S_A sinkers and that the write drivers/sinkers D/S_B are divided into D/S_B drivers and D/S_B sinkers. 
     In addition, the D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the end portion on the side where the column selectors  16  do not exist) of the sub-arrays A sub   _   1  to A sub   _   n , and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the end portion on the side where the column selectors  16  exist) of the sub-arrays A sub   _   1  to A sub   _   n . 
     The power line PSL for supplying, for example, the ground potential V ss  to the D/S_A sinkers and the D/S_B sinkers is disposed above the D/S_A sinkers and the D/S_B sinkers and extend in the second direction. The power line PSL for supplying, for example, the drive potential V dd   _   W1  to the D/S_A drivers and the D/S_B drivers is disposed above the D/S_A drivers and the D/S_B drivers and extend in the second direction. 
     The SOT-MRAM shown in  FIG. 54  has the shared bit line architecture, similarly to the SOT-MRAM shown in  FIG. 53 . 
     However, the SOT-MRAM shown in  FIG. 54  has what is called a row direction extending architecture in which the conductive lines WBL 1  to WBL j  and SBL 1  to SBL j  for urging the write current to flow to the conductive line L SOT  shared by the memory cells MC 1  to MC 8  extend in the second direction intersecting the first direction in which the conductive lines LBL 1  to LBL j  extend, as compared with the example shown in  FIG. 53 . 
     In this case, the D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the end portion in the second direction) of the sub-arrays A sub   _   1  to A sub   _   n , and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the end portion in the second direction) of the sub-arrays A sub   _   1  to A sub   _   n . 
     As shown in this figure, for example, the D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the left end portion) of the sub-arrays A sub   _   1  to A sub   _   n , and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the right end portion) of the sub-arrays A sub   _   1  to A sub   _   n , in the odd-numbered block BK_k (k is 1, 3, 5, . . . ) 
     The D/S_A sinkers and the D/S_B sinkers are laid out at one of ends (i.e., the right end portion) of the sub-arrays A sub   _   1  to A sub   _   n , and the D/S_A drivers and the D/S_B drivers are laid out at the other end (i.e., the left end portion) of the sub-arrays A sub   _   1  to A sub   _   n , in the even-numbered block BK_k (k is 2, 4, 6, . . . ) 
     The power lines PSL for supplying, for example, the ground potential V ss  to the D/S_A sinkers and the D/S_B sinkers are disposed above the D/S_A sinkers and the D/S_B sinkers and extend in the second direction. The power lines PSL for supplying, for example, the drive potential V dd   _   W1  to the D/S_A drivers and the D/S_B drivers are disposed above the D/S_A drivers and the D/S_B drivers and extend in the first direction. 
     The D/S_A drivers, the D/S_B drivers, the D/S_A sinkers, and the D/S_B sinkers shown in  FIGS. 53 and 54  are not explained here since the drivers and the sinkers are the same as, for example, the D/S_A drivers, the D/S_B drivers, the D/S_A sinkers, and the D/S_B sinkers in the first example, i.e.,  FIGS. 29 to 32 . 
     In the example shown in  FIG. 53 , of the examples shown in  FIGS. 50 to 54 , the write drivers/sinkers (the D/S_A driver, the D/S_B driver, the D/S_A sinker, and the D/S_B sinker) are provided for each column CoL p . In addition, the power line PSL for supplying V ss  and the power line PSL for supplying V dd   _   W1  are disposed separately from each other. The example shown in  FIG. 53  is therefore considered most desirable. 
     CONCLUSION 
     According to the above embodiments, the nonvolatile MRAM which can be used in various systems can be thereby implemented. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.