Patent Publication Number: US-2022221891-A1

Title: Semiconductor devices and in-vehicle electronic control devices

Description:
TECHNICAL FIELD 
     The present invention relates to a structure of a semiconductor device configured using a multilayer wiring technique, and particularly relates to an effective technique for application to the semiconductor device in which variation in a pairing property of elements is small and high reliability is required. 
     BACKGROUND ART 
     A current mirror circuit that is frequently used in an analog integrated circuit converts an input current into a desired magnification (mirror ratio) and outputs the input current having the desired magnification depending on sizes of MOS transistors on an input side and an output side. In order to operate the semiconductor integrated circuit device including the current mirror circuit with high accuracy, it is required that the variation in the pairing property of the transistors constituting the current mirror circuit is reduce and that aging variation in the pairing property is suppressed. 
     In the semiconductor integrated circuit device, a metal wiring that connects elements such as transistors, diodes, resistors, and capacitances is usually formed on these elements through an interlayer insulating film (interlayer oxide film). The metal wiring (wiring pattern) is formed by repeating formation of a metal film and an insulating film and pattern formation by lithography. 
     In general, in the case of forming a multilayer metal wiring, an upper wiring layer far from a transistor is used for connection of a long distance in a chip, a power supply main line, or the like, and a wiring thicker than a lower wiring close to the transistor or a wide wiring is often used in order to reduce impedance. In recent years, in a semiconductor device or the like on which a power transistor controlling a large current is mounted, sometimes a wider and thicker copper redistribution is used as an upper layer of a passivation film of the semiconductor device. 
     Meanwhile, because the metal film and the insulating film that are formed on the semiconductor substrate have different linear expansion coefficients from the semiconductor substrate, thermal strain is generated in the semiconductor element due to an environmental temperature around the semiconductor element or a temperature change due to self-heating. The thermal strain of the wiring pattern disposed around elements such as transistors and resistors causes dispersion and the variation in an electric characteristic of these elements. 
     For example, PTL 1 discloses a technique for reducing a change with time of the element caused by the wiring pattern. PTL 1 discloses a technique for reducing an influence of a dummy wiring on the MOS transistor by defining disposition of a dummy wiring on the upper layer of the MOS transistor constituting a pair. 
     PTL 1 discloses that “a semiconductor device including a mechanical chemical polishing dummy wiring disposed on an upper layer of a transistor, wherein the dummy wiring does not overlap any of the pairing transistors in a plan view, or a portion overlapping a first transistor and a second transistor is disposed so as to be equivalent between the first transistor and the second transistor”. 
     CITATION LIST 
     Patent Literature 
     PTL 1: JP 2003-100899 A 
     SUMMARY OF INVENTION 
     Technical Problem 
     As described above, in the upper wiring layer far from the transistor, sometimes the wide wiring is used. These wiring widths are wider than the transistor sizes of the transistors constituting the pair, and sometimes are narrower than an entire arrangement of the pair transistors. When such wide wirings are disposed around the pair transistors, in order to make the wiring patterns equivalent seen from each transistor, the wide wirings is required to bypass the transistor arrangement, and there is a problem in that a chip size increases. 
     In particular, the influence on the chip size is large because the number of transistors included in the current mirror circuit used in an analog-to-digital converter or the like is large. 
     An object of the present invention is to provide a highly reliable semiconductor device capable of reducing the variation in a mirror ratio of the current mirror circuit and suppressing the change with time of the pairing property of the elements in the semiconductor device including the current mirror circuit. 
     Solution to Problem 
     In order to solve the above problems, a semiconductor device includes: a first semiconductor element group in which a plurality of semiconductor elements are connected in parallel; a second semiconductor element group disposed in a layer identical to the first semiconductor element group and in which a plurality of semiconductor elements are connected in parallel; and a plurality of wirings disposed in an upper layer of the first semiconductor element group and the second semiconductor element group, the plurality of wirings having a width greater than a width of each semiconductor element of the first semiconductor element group and the second semiconductor element group. The first semiconductor element group and the second semiconductor element group form a pair to constitute a circuit having predetermined pair accuracy, and the plurality of wirings are disposed such that a combination of distances in a planar direction from each semiconductor element of the first semiconductor element group to a wiring at a position closest in the planar direction is equal to a combination of distances in the planar direction from each semiconductor element of the second semiconductor element group to a wiring at a position closest in the planar direction. 
     Advantageous Effects of Invention 
     According to the present invention, in the semiconductor device including the current mirror circuit, the highly reliable semiconductor device capable of reducing the variation in the mirror ratio of the current mirror circuit and suppressing the change with time of the pairing property of the elements can be implemented. 
     Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a plan view illustrating a semiconductor device according to a first embodiment of the present invention. 
         FIG. 2  is a circuit diagram illustrating the semiconductor device of the first embodiment of the present invention. 
         FIG. 3A  is a view illustrating a simulation model of thermal strain of a wiring. 
         FIG. 3B  is a view illustrating a simulation result of a thermal strain by the model in  FIG. 3A . 
         FIG. 4  is a partially enlarged view illustrating the semiconductor device in  FIG. 1 . 
         FIG. 5  is a sectional view taken along a line A-A′ of  FIG. 4 . 
         FIG. 6  is a plan view illustrating a semiconductor device of a conventional example. 
         FIG. 7  is a circuit diagram illustrating the semiconductor device of the conventional example. 
         FIG. 8  is a plan view illustrating a semiconductor device according to a second embodiment of the present invention. 
         FIG. 9  is a sectional view taken along a line B-B′ of  FIG. 8 . 
         FIG. 10  is a partially enlarged view illustrating the semiconductor device in  FIG. 8 . 
         FIG. 11  is a sectional view taken along a line C-C′ of  FIG. 10 . 
         FIG. 12  is a plan view illustrating a semiconductor device according to a third embodiment of the present invention. 
         FIG. 13  is a sectional view taken along a line D-D′ of  FIG. 12 . 
         FIG. 14  is a partially enlarged view illustrating the semiconductor device in  FIG. 12 . 
         FIG. 15  is a sectional view taken along a line E-E′ of  FIG. 14 . 
         FIG. 16  is a plan view illustrating a semiconductor device according to a fourth embodiment of the present invention. 
         FIG. 17  is a circuit diagram illustrating the semiconductor device of the fourth embodiment of the present invention. 
         FIG. 18  is a partially enlarged view illustrating the semiconductor device in  FIG. 16 . 
         FIG. 19  is a plan view illustrating a semiconductor device according to a fifth embodiment of the present invention. 
         FIG. 20  is a plan view illustrating a semiconductor device according to a sixth embodiment of the present invention. 
         FIG. 21  is a circuit diagram illustrating the semiconductor device of the sixth embodiment of the present invention. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same component is denoted by the same reference numeral, and the detailed description of overlapping parts is omitted. 
     First Embodiment 
     A semiconductor device according to a first embodiment of the present invention will be described with reference to  FIGS. 1 to 7 .  FIGS. 6 and 7  are a plan view and a circuit diagram illustrating a conventional semiconductor device illustrated as a comparative example in order to facilitate understanding of the present invention. 
       FIG. 1  is an example illustrating a planar positional relationship between MOS transistors M 01  to M 74  constituting a current mirror circuit and wide wirings  20  in a semiconductor device of the first embodiment. As illustrated in  FIG. 1 , the plurality of MOS transistors M 01  to M 74  are arranged in an X-direction, and each of the plurality of wide wirings  20  is disposed to extend in a Y-direction perpendicular to the MOS transistors M 01  to M 74 . A width W 2  of one wide wiring  20  is about 4 times a width W 1  of one MOS transistor. 
       FIG. 2  is a circuit diagram illustrating the semiconductor device in  FIG. 1 . A mirror source of a mirror circuit in  FIG. 2  is configured by connecting four MOS transistors M 01  to M 04  in parallel to a mirror terminal  100 . A mirror destination is also configured such that four MOS transistors M 11  to M 14 , M 21  to M 24 , and the like are connected in parallel to each of mirror terminals  101  to  107 . However, the arrangement order of the MOS transistors in  FIG. 1  may be different from that in  FIG. 2 . 
     In  FIG. 1 , the MOS transistors are arranged in parallel in a distributed manner as M 01  to M 71 , M 02  to M 72 , M 03  to M 73 , M 04  to M 74  from the left. 
     Furthermore, M 01  to M 31  are arranged in the order of M 01 , M 11 , M 21 , M 31  from the left, and M 02  to M 32  are changed one by one like M 12 , M 22 , M 32 , M 02  from the left. Similarly, M 03  to M 43  and M 04  to M 44  are arranged while the order is changed. Similarly, M 41  to M 71 , M 42  to M 72 , M 43  to M 73 , M 44  to M 74  are arranged while the order is changed one by one. 
     At this point, an influence of stress of a wiring pattern on the MOS transistor will be described with reference to  FIGS. 3A and 3B .  FIG. 3A  is a sectional view illustrating a thermal stress simulation model in which a silicon oxide film  400  that is of an interlayer oxide film, a polyimide film  500 , and a copper wiring  200  are disposed on an SOI substrate including a silicon substrate (semiconductor substrate)  300 , a silicon oxide film  401 , and a silicon (Si) layer  301 .  FIG. 3B  illustrates a simulation result of a strain amount at an interface  302  between the silicon layer  301  and the silicon oxide film  401  in  FIG. 3A . 
     As illustrated in  FIG. 3B , the thermal strain of the silicon interface  302  is affected by an upper layer wiring (copper wiring  200 ), and changes depending on a planar distance from a wiring end. In addition, mobility of electrons and holes in silicon depends on the strain amount of silicon. As described above, because the electric characteristic of the semiconductor element changes depending on the positional relationship with the wiring pattern, it is necessary to consider the disposition, shape, and the like of the upper layer wiring pattern of each element in the semiconductor element in which the pairing property is required. 
     A detailed positional relationship between the MOS transistor and the wide wiring  20 , which are constituents in the first embodiment, will be described below.  FIG. 4  is an enlarged plan view illustrating regions of the eight MOS transistors M 01  to M 71  from the left in  FIG. 1 .  FIG. 5  is a sectional view taken along a line A-A′ of  FIG. 4 . In  FIGS. 4 and 5 , patterns of wiring layers  10  of an upper layer close to the MOS transistors are laid out so as to be identical as viewed from the respective MOS transistors with respect to the MOS transistors M 01  to M 71 , and the strain given to the MOS transistors by the wiring layers  10  is identical in the respective MOS transistors. 
     The planar distances from the MOS transistors M 01 , M 11 , M 21 , M 31  to the wiring ends of the wide wirings  20  are defined as D 2 , D 1 , E 1 , E 2 , respectively. The distances in the planar direction from M 41  to M 71  to the wiring ends of the wide wirings  20  are similar. In M 01  to M 71 , the presence or absence of the upper wide wiring  20  is different from the distance in the planar direction from the wiring end, so that the influence of thermal strain by the wide wiring  20  is different and the pairing property of the MOS transistors is degraded. 
     However, in the circuit of  FIG. 2 , when the MOS transistor and the wide wiring  20  are arranged as illustrated in  FIG. 1 , in a set of the MOS transistors for each mirror terminal  101  to  107  of  FIG. 2 , a combination of the distances in the planar direction from the MOS transistor to the closest wide wiring  20  is, for example, as follows. 
     &lt;&lt;Mirror Terminal  100 &gt;&gt; (Mirror Source) 
     Transistors M 01  to M 04 : distances D 2 , E 2 , E 1 , D 1  to wide wiring  20   
     &lt;&lt;Mirror Terminal  101 &gt;&gt; (Mirror Destination) 
     Transistors M 11  to M 14 : distances D 1 , D 2 , E 2 , E 1  to wide wiring  20   
     &lt;&lt;Mirror Terminal  102 &gt;&gt; (Mirror Destination) 
     Transistors M 21  to M 24 : distances E 1 , D 1 , D 2 , E 2  to wide wiring  20   
     &lt;&lt;Mirror Terminal  103 &gt;&gt; (Mirror Destination) 
     Transistors M 31  to M 34 : distances E 2 , E 1 , D 1 , D 2  to wide wiring  20   
     The same applies to the mirror terminals  104  to  107 , and the electric characteristic of the MOS for each mirror terminal in  FIG. 2  is the same because the mirror terminals  104  to  107  become a combination of (D 1 , D 2 , E 1 , E 2 ). Accordingly, the pairing property between the mirror source and each mirror destination can be secured as the current mirror circuit. 
     The first embodiment includes: a circuit that includes at least a first semiconductor element group (the group of mirror terminal  100 ) in which the plurality of semiconductor elements (the MOS transistors M 01  to M 04 ) are connected in parallel and a second semiconductor element group (group of mirror terminals  101 ) in which the plurality of semiconductor elements (MOS transistors M 11  to M 14 ) are connected in parallel, the pairing property being required in the circuit; and a plurality of wirings formed above each semiconductor element group ( 100 ,  101 ) and having a width greater than one width of the semiconductor element M 01 . The plurality of wide wirings  20  are disposed such that the combination of distances (D 2 , E 2 , E 1 , D 1 ) in the planar direction from each semiconductor element (M 01  to M 04 ) constituting the first semiconductor element group ( 100 ) to the wide wiring  20  at the position closest in the planar direction is equal to the combination of the distances (D 1 , D 2 , E 2 , E 1 ) in the planar direction from each semiconductor elements (M 11  to M 14 ) constituting the second semiconductor element group ( 101 ) to the wide wiring  20  at the position closest to the planar direction. Thus, the influence of the stress applied from the wide wiring  20  on the first semiconductor element group (the group of the mirror terminals  100 ) and the influence of the stress applied from the wide wiring  20  on the second semiconductor element group (the group of the mirror terminals  101 ) can be equalized to each other. 
     Because a degree of degradation due to the stress can be equalized, the pairing property between the first semiconductor element group (group of mirror terminals  100 ) and the second semiconductor element group (group of mirror terminals  101 ) can be maintained, and aging degradation (change with time) can be suppressed. 
     In the first embodiment, the current mirror circuit has been described as an example of the circuit in which the pairing property is required. However, the present invention is not limited to the current mirror circuit, but can be widely applied to other circuits in which the pairing property (pair accuracy) is required. 
     In addition, the configuration in which the number of MOS transistors (semiconductor elements) constituting each semiconductor element group is four has been described as an example, but the present invention is not limited thereto. Similarly, the number of semiconductor element groups constituting a circuit in which the pairing property is required is not limited to seven. 
     On the other hand, in the conventional semiconductor device of  FIGS. 6 and 7 , the MOS transistors constituting the current mirror circuit are arranged without being dispersed, and in this case, because the influence of the wide wiring  20  varies among the MOS transistors MO to M 7 , the pairing property of the MOS transistors decreases, and a mirror ratio of the current mirror circuit also varies for each mirror destination. 
     As described above, the semiconductor device of the first embodiment includes: the first semiconductor element group (the group of the mirror terminal  100 ) in which the plurality of semiconductor elements (the MOS transistors M 01  to M 04 ) are connected in parallel; the second semiconductor element group (the group of the mirror terminal  101 ) disposed in a layer identical to the first semiconductor element group (the group of the mirror terminal  100 ) and in which the plurality of semiconductor elements (the MOS transistors M 11  to M 14 ) are connected in parallel; and the plurality of wide wirings  20  disposed on an upper layer of the first semiconductor element group (the group of the mirror terminals  100 ) and the second semiconductor element group (the group of the mirror terminals  101 ), the wide wiring  20  having the width W 2  greater than the width W 1  of each semiconductor element of the first semiconductor element group (the group of the mirror terminals  100 ) and the second semiconductor element group (the group of the mirror terminals  101 ). The first semiconductor element group (the group of the mirror terminals  100 ) and the second semiconductor element group (group of mirror terminals  101 ) form a pair to constitute a circuit having predetermined pair accuracy, and the plurality of wide wirings  20  are disposed such that the combination of distances in the planar direction from each semiconductor element (the MOS transistor M 01  to M 04 ) of the first semiconductor element group (the group of the mirror terminal  100 ) to the wide wiring  20  at the position closest in the planar direction is equal to the combination of distances in the planar direction from each semiconductor element (the MOS transistors M 11  to M 14 ) of the second semiconductor element group the (group of the mirror terminal  101 ) to the wide wiring  20  at the position closest in the planar direction. 
     Furthermore, the above-described circuit is the current mirror circuit, the first semiconductor element group (group of mirror terminals  100 ) is the mirror source of the current mirror circuit, and the second semiconductor element group (group of mirror terminals  101 ) is the mirror destination of the current mirror circuit. 
     Thus, in the semiconductor device including the current mirror circuit, the highly reliable semiconductor device that reduces the variation in the mirror ratio of the current mirror circuit and prevents the change with time in the pairing property of the elements can be implemented. 
     Furthermore, the reliability of the in-vehicle electronic control device can be improved by mounting the semiconductor device of the first embodiment on the in-vehicle electronic control device. 
     Second Embodiment 
     A semiconductor device according to a second embodiment of the present invention will be described with reference to  FIGS. 8 to 11 .  FIG. 8  is an example illustrating a planar positional relationship among MOS transistors M 01  to M 74  constituting a current mirror circuit in the semiconductor device of the second embodiment, a wide wiring  20 , and a wide wiring  30  in a wiring layer different from the wide wiring  20 . In  FIG. 8 , the MOS transistors M 01  to M 74  and the wide wiring  20  are the same as those in  FIG. 1 . The current mirror circuit of the second embodiment is the same as that in  FIG. 2 .  FIG. 9  illustrates a sectional view taken along a line B-B′ of  FIG. 8 . 
     The detailed arrangement of the MOS transistor, the wide wiring  20 , and the wide wiring  30  of the second embodiment will be described below.  FIG. 10  is an enlarged plan view illustrating regions of the eight MOS transistors M 01  to M 71  from the left of  FIG. 8 , and  FIG. 11  is a sectional view taken along a line C-C′ of  FIG. 10 . In  FIGS. 10 and 11 , distances D 1 , D 2 , E 1 , E 2  in the planar direction between the MOS transistors M 01  to M 71  and the wide wiring  20  are the same as those in  FIGS. 4 and 5  of the first embodiment. 
     As illustrated in  FIGS. 10 and 11 , the distances in the planar direction between the wide wiring  30  and the MOS transistors M 01 , M 11 , M 21 , M 31  are set to G 1 , F 1 , F 2 , F 3 , respectively. The same applies to M 41 , M 51 , M 61 , M 71 . 
     By disposing the MOS transistor constituting the current mirror circuit in  FIG. 9 , the wide wiring  20  of the upper layer, and the wide wiring  30  of the wiring layer different from the wide wiring  20  as illustrated in  FIG. 8 , in each set of the MOS transistors connected to each of the terminal mirror  101  to  107  in the circuit diagram of  FIG. 2 , the distance in the planar direction from the MOS transistor to the wide wiring  30  becomes, for example, as follows, and all become the combination of F 1 , F 2 , F 3 , G 1 . 
     &lt;&lt;Mirror Terminal  100 &gt;&gt; (Mirror Source) 
     Transistors M 01  to M 04 : distances G 1 , F 3 , F 2 , F 1  to wide wiring  30   
     &lt;&lt;Mirror Terminal  101 &gt;&gt; (Mirror Destination) 
     Transistors M 11  to M 14 : distances F 1 , G 1 , F 3 , F 2  to wide wiring  30   
     &lt;&lt;Mirror Terminal  102 &gt;&gt; (Mirror Destination) 
     Transistors M 21  to M 24 : distances F 2 , F 1 , G 1 , F 3  to wide wiring  30   
     &lt;&lt;Mirror Terminal  103 &gt;&gt; (Mirror Destination) 
     Transistors M 31  to M 34 : distance F 3 , F 2 , F 1 , G 1  to wide wiring  30   
     As described above, the combination of the distances in the planar direction from the MOS transistor to the wide wiring  20  and the wide wiring  30  is the same between the terminals of the mirror source ( 100 ) and the mirror destination ( 101  to  107 ) of the current mirror circuit, and the influence of the stress of the wide wiring can be equalized between the terminals of the mirror source and the mirror destination, so that initial variation in the mirror ratio of the current mirror circuit can be reduced and aged degradation (change with time) can be suppressed. 
     As described above, in the semiconductor device of the second embodiment, the plurality of wirings include the plurality of wide wirings  20  disposed in the first wiring layer and the plurality of wide wirings  30  disposed in the second wiring layer different from the first wiring layer, the plurality of wide wirings  20  of the first wiring layer are disposed such that the combination of distances in the planar direction from each semiconductor element (MOS transistors M 01 , M 11 , M 21 , M 31 ) of the first semiconductor element group (the group of the mirror terminal  100 ) to the wide wiring  20  disposed in the first wiring layer at the position closest in the planar direction is equal to the combination of distances in the planar direction from each semiconductor element (MOS transistors M 41 , M 51 , M 61 , M 71 ) of the second semiconductor element group (the group of the mirror terminal  101 ) to the wide wiring  20  disposed in the first wiring layer at the closest position in the planar direction, and the plurality of wide wirings  30  of the second wiring layer are disposed such that the combination of distances in the planar direction from each semiconductor element (MOS transistors M 01 , M 11 , M 21 , M 31 ) of the first semiconductor element group (the group of the mirror terminal  100 ) to the wide wiring  30  disposed in the second wiring layer at the position closest in the planar direction is equal to the combination of distances in the planar direction from each semiconductor element (MOS transistors M 41 , M 51 , M 61 , M 71 ) of the second semiconductor element group (the group of the mirror terminal  101 ) to the wide wiring  30  disposed in the second wiring layer at the position closest in the planar direction. 
     Third Embodiment 
     A semiconductor device according to a third embodiment of the present invention will be described with reference to  FIGS. 12 to 15 .  FIG. 12  is an example illustrating a planar positional relationship among MOS transistors M 01  to M 74  constituting a current mirror circuit in the semiconductor device of the third embodiment, a wide wiring  20 , and a wide wiring  31  of a wiring layer different from the wide wiring  20 . In  FIG. 12 , the MOS transistors M 01  to M 74  and the wide wiring  20  are the same as those in  FIG. 1 . The current mirror circuit of the second embodiment is the same as that in  FIG. 2 .  FIG. 13  is a sectional view taken along a line D-D′ of  FIG. 12 . 
     In the third embodiment, as illustrated in  FIG. 13 , the wide wiring  31  is disposed closer to the MOS transistor side (lower layer side) than the wide wiring  20 . 
     Hereinafter, the detailed disposition of the MOS transistor, the wide wiring  20 , and the wide wiring  31  of the third embodiment will be described below.  FIG. 14  is an enlarged plan view illustrating regions of the eight MOS transistors M 01  to M 71  from the left of  FIG. 12 , and  FIG. 15  is a sectional view taken along a line E-E′ of  FIG. 14 . In  FIGS. 14 and 15 , distances D 1 , D 2 , E 1 , E 2  in the planar direction between the MOS transistors M 01  to M 71  and the wide wiring  20  are the same as those in  FIGS. 4 and 5  of the first embodiment. 
     In addition, distances in the planar direction between the region where the wide wiring  20  and the wide wiring  31  planarly overlap each other and the MOS transistors M 01 , M 11 , M 21 , M 31  are set to H 3 , H 2 , H 1 , J 1 , respectively. When the MOS transistor constituting the current mirror circuit, the wide wiring  20  of the upper layer, and the wide wiring  31  are disposed as illustrated in  FIGS. 12 and 13 , in the set of MOS transistors connected to each mirror terminal  101  to  107  of the circuit diagram of  FIG. 2 , the distance in the planar direction from the MOS transistor to the overlapping region of the wide wiring  20  and the wide wiring  31  is, for example, as follows, and all become a combination of H 1 , H 2 , H 3 , J 1 . 
     &lt;&lt;Mirror Terminal  100 &gt;&gt; (Mirror Source) 
     Transistors M 01  to M 04 : distances H 3 , J 1 , H 1 , H 2  to wide wiring  31   
     &lt;&lt;Mirror Terminal  101 &gt;&gt; (Mirror Destination) 
     Transistors M 11  to M 14 : distances H 2 , H 3 , J 1 , H 1  to wide wiring  31   
     &lt;&lt;Mirror Terminal  102 &gt;&gt; (Mirror Destination) 
     Transistors M 21  to M 24 : distances H 1 , H 2 , H 3 , J 1  to wide wiring  31   
     &lt;&lt;Mirror Terminal  103 &gt;&gt; (Mirror Destination) 
     Transistors M 31  to M 34 : Distances J 1 , H 1 , H 2 , H 3  to the wide wiring  31   
     As described above, the combination of the distances in the planar direction from the MOS transistor to the wide wiring  20  and the wide wiring  31  and the combination of the distances in the planar direction from the MOS transistor to the overlapping of the wide wiring  20  and the wide wiring  31  are made the same for each combination of the mirror source of the current mirror circuit and the MOS transistor of the terminal of each mirror destination, whereby the influence of the stress of the wide wiring can be made equal between the mirror source and the mirror destination, and the initial variation reduction and the aging degradation (change with time) of the mirror ratio of the current mirror circuit can be suppressed. 
     As described above, in the semiconductor device of the third embodiment, the plurality of wirings include the plurality of wide wirings  20  disposed in the first wiring layer and the plurality of wide wirings  31  disposed in the second wiring layer different from the first wiring layer, the wide wiring  20  disposed in the first wiring layer and the wide wiring  31  disposed in the second wiring layer are disposed so as to overlap each other, and the wide wiring  20  disposed in the first wiring layer and the wide wiring  31  disposed in the second wiring layer are disposed such that the combination of distances in the planar direction from each semiconductor element (the MOS transistors M 01 , M 11 , M 21 , M 31 ) of the first semiconductor element group (the group of the mirror terminal  100 ) to the position where the wide wiring  20  disposed in the first wiring layer closest to each semiconductor element in the planar direction overlaps the wide wiring  31  disposed in the second wiring layer is equal to the combination of distances in the planar direction from each semiconductor element (the MOS transistors M 41 , M 51 , M 61 , M 71 ) of the second semiconductor element group (the group of the mirror terminal  101 ) to the position where the wide wiring  20  disposed in the first wiring layer closest in the planar direction overlaps the wide wiring  31  disposed in the second wiring layer. 
     Fourth Embodiment 
     A semiconductor device according to a fourth embodiment of the present invention will be described with reference to  FIGS. 16 to 18 .  FIG. 16  is an example illustrating a planar positional relationship between MOS transistors M 01  to M 84  constituting a current mirror circuit in the semiconductor device of the fourth embodiment and the wide wiring  21 .  FIG. 17  is a circuit diagram illustrating the current mirror circuit of  FIG. 16 . In  FIG. 16 , similarly to  FIG. 1 , the plurality of MOS transistors M 01  to M 84  are arranged in the X-direction, and the plurality of wide wirings  21  are disposed to extend in the Y-direction perpendicular to the MOS transistors M 01  to M 84 . However, in the fourth embodiment, a width W 3  of one wide wiring  21  is about 5 times the width W 1  of one MOS transistor. 
     All the MOS transistors M 01  to M 04  connected to a mirror terminal  120  of the mirror source of  FIG. 17  are disposed in a center of the wiring  21  in  FIG. 16 . On the other hand, similarly to the first embodiment ( FIG. 1 ), the MOS transistors M 11  to M 84  of the mirror destinations are arranged while the order is changed one by one. In the arrangement of  FIG. 17 , the combination of distances in the planar direction from each mirror destination to the nearest mirror source is the same between the mirror terminals of the mirror destinations. For this reason, the variation depending on the distance from the mirror source can be reduced. 
       FIG. 18  is an enlarged plan view illustrating regions of the nine transistors M 11  to M 81  from the left of  FIG. 16 . The distances in the planar direction from the MOS transistors M 11 , M 21 , M 31 , M 41  to the wiring ends of the wide wirings  21  are defined as D 4 , D 3 , E 3 , E 4 , respectively. 
     The same applies to M 51  to M 81 . 
     In each of mirror terminal  121  to  128  of the mirror destination of  FIG. 17 , by arranging the MOS transistor and the wide wiring  21  as illustrated in  FIG. 16 , the combinations of the distances in the planar direction from the MOS transistor to the wide wiring  21  become D 3 , D 4 , E 3 , E 4 . Thus, the variation in the mirror ratio between the mirror destinations is reduced because the influence of the wide wiring of each mirror destination becomes equal. 
     However, the mirror source is different from the mirror destination in the influence of wiring stress. For this reason, in the case of the fourth embodiment, sizes of the MOS transistors of the mirror source and the mirror destination are adjusted so as to obtain a required mirror ratio, and the mirror ratio is corrected by calibration after the semiconductor integrated circuit device is manufactured. 
     Furthermore, the correction is required when there is the variation in the mirror ratio over a long period of time. However, because the influence of the strain due to the wide wiring between the mirror destinations is the same, the correct of the mirror ratio is not required for each mirror destination, and the correction can be simplified. 
     As described above, in the semiconductor device of the fourth embodiment, the circuit is the current mirror circuit, the semiconductor device further includes the third semiconductor element group (the group of the mirror terminal  120 ) in which the plurality of semiconductor elements (the MOS transistors M 01  to M 04 ) are connected in parallel, the first semiconductor element group (the group of the mirror terminal  121 ) and the second semiconductor element group (the group of the mirror terminal  122 ) are the mirror destination of the current mirror circuit, and the third semiconductor element group (the group of the mirror terminal  120 ) is the mirror source of the current mirror circuit. 
     In addition, the plurality of semiconductor element groups are included as the mirror destination (the groups of the mirror terminals  121  to  128 ), and each combination of distances in the planar direction from each semiconductor element in the plurality of semiconductor element groups (the groups of the mirror terminals  121  to  128 ) to the wide wiring  21  at the position closest in the planar direction is equal to the combination of distances in the planar direction in the first semiconductor element group (the group of the mirror terminal  121 ). 
     Fifth Embodiment 
     A semiconductor device according to a fifth embodiment of the present invention will be described with reference to  FIG. 19 .  FIG. 19  is an example illustrating a planar positional relationship between MOS transistors M 01  to M 74  constituting a current mirror circuit in the semiconductor device of the fifth embodiment, a wide wiring  20 , and a dummy wiring  22  in the same wiring layer as the wide wiring  20 . The current mirror circuit of the fifth embodiment is the same as that in  FIG. 2 . 
     In the fifth embodiment, only two wide wirings  20  are disposed with respect to the arrangement of the MOS transistors M 01  to M 74  constituting the current mirror circuit. The dummy wiring  22  having the same width as the wide wiring  20  is disposed in the same wiring layer at a part of the position where the wide wiring  20  is disposed in  FIG. 1 . For the same reason as in the fifth embodiment, the dummy wiring  22  has an effect of equalizing the influence of the stress applied to the MOS transistor from the wide wiring  20  between the terminals of the mirror destination and the mirror source. 
     As illustrated in the stress simulation result of  FIG. 3B , because the stress applied to the silicon is different between the wiring end and the wiring center, the dummy wiring  22  in  FIG. 19  needs to be extended in the Y-direction from the MOS transistor arrangement. 
     Sixth Embodiment 
     A semiconductor device according to a sixth embodiment of the present invention will be described with reference to  FIGS. 20 and 21 .  FIG. 20  is an example illustrating a planar positional relationship between MOS transistors M 01  to M 64  constituting a current mirror circuit in the semiconductor device of the sixth embodiment and a wide wiring  20 . Similarly to the first embodiment ( FIG. 1 ), the MOS transistors M 01  to M 64  are arranged in the X-direction, and the wide wiring  20  is disposed to extend in the Y-direction perpendicular to the MOS transistors M 01  to M 64 . A width W 2  of one wide wiring  20  is about 4 times a width W 1  of one MOS transistor.  FIG. 21  is a circuit diagram illustrating the current mirror circuit of  FIG. 20 . 
     In  FIG. 20 , dummy transistors DM 1  to DM 4  that are dummy semiconductor elements are disposed in the MOS transistor array in order to adjust the positions of the MOS transistors M 01  to M 64  and the wide wiring  20 . Thus, similarly to the first embodiment ( FIG. 1 ), in the set of MOS transistors for the mirror terminal  130  to  136  in  FIG. 21 , the combination of the distances in the planar direction from the MOS transistor to the width wiring  20  closest to the MOS transistor is the same, so that the influence of the stress of the width wiring  20  can be equalized between the mirror source and the mirror destination, and the initial variation reduction and the aging degradation (aging) of the mirror ratio of the current mirror circuit can be suppressed. 
     The first to sixth embodiments are the arrangement examples of the MOS transistor set connected in parallel to the mirror terminal of the current mirror circuit and the upper layer wiring. However, in addition to the MOS transistor, for example, a semiconductor element such as a bipolar transistor or a semiconductor resistance element and the upper layer wiring thereof may be disposed. 
     The present invention is not limited to the above embodiments, but includes various modifications. 
     For example, the above embodiments are described in detail in order to explain the present invention in an easy-to-understand manner, and the above embodiments are not necessarily limited to a case including all the described configurations. Furthermore, some components in one example can be replaced with the components in another example, and the configuration of another example can be added to the configuration of one example. Furthermore, regarding some components in the examples, other components can be added, deleted, and replaced. 
     REFERENCE SIGNS LIST 
     
         
         MO to M 7  MOS transistor 
         M 01  to M 84  MOS transistor 
         DM 1  to DM 4  dummy transistor 
           10  (metal) wiring layer 
           20 ,  21  wide (metal) wiring 
           22  dummy wiring (of same wiring layer as metal wiring  20 ) 
           30 ,  31  wide (metal) wiring (of wiring layer different from metal wiring  20 ) 
         W 1  to W 3  transistor size or metal wiring width 
           100  to  107  mirror terminal (of current mirror circuit) 
           110  to  117  mirror terminal (of current mirror circuit) 
           120  to  128  mirror terminal (of current mirror circuit) 
           130  to  136  mirror terminal (of current mirror circuit) 
         D 1  to D 4  distance (in planar direction from MOS transistor to wide metal wiring) 
         E 1  to E 5  distance (in planar direction from MOS transistor to wide metal wiring) 
         F 1  to F 3  distance (in planar direction from MOS transistor to wide metal wiring) 
         G 1  distance (in planar direction from MOS transistor to wide metal wiring) 
         H 1  to H 3  distance (in planar direction from MOS transistor to overlap of wide metal wiring) 
         J 1  distance (in planar direction from MOS transistor to overlap of wide metal wiring) 
           200  copper wiring 
           300  silicon substrate (semiconductor substrate) 
           301  silicon (Si) layer 
           302  interface between silicon layer  301  and silicon oxide film  401   
           400  silicon oxide film 
           401  silicon oxide film (interlayer oxide film) 
           500  polyimide film