Patent Publication Number: US-2022239307-A1

Title: Analog to digital converter with current mode stage

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of application Ser. No. 17/120,438, filed Dec. 14, 2020, which is a continuation of application Ser. No. 16/359,495, filed Mar. 20, 2019, which issued as U.S. Pat. No. 10,868,557, which application claims the benefit of provisional application Ser. No. 62/650,536, filed Mar. 30, 2018, which applications are incorporated herein by reference in their entirety. 
    
    
     BACKGROUND 
     Analog-to-digital converters (ADC or A/D) are used in a variety of applications in order to convert a sampled analog signal into a digital signal. There are a variety of ADC architectures, such as pipelined, flash, Sigma-Delta, successive approximation register (SAR), etc. A pipelined, or sub-ranging, ADC uses two or more steps of sub-ranging. A coarse conversion of an analog input voltage to a coarse digital value is done, then the coarse digital value is converted back to an analog signal with a digital-to-analog converter (DAC). The coarse analog value is compared to the input voltage with an analog comparator, and the difference, or residue, is then converted into a finer digital representation and the results are combined. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1A  is a block diagram illustrating aspects of an analog-to-digital converter (ADC) system in accordance with some embodiments. 
         FIG. 1B  is a circuit diagram illustrating further aspects of an analog-to-digital converter (ADC) in accordance with some embodiments. 
         FIG. 2  is a phase diagram illustrating the ADC clock signals in accordance with some embodiments. 
         FIG. 3  is a circuit diagram illustrating aspects of a current steering digital-to-analog conversion (DAC) and transconductance (Gm) stage of an ADC in accordance with some embodiments. 
         FIGS. 4  A and B are circuit diagrams depicting aspects of a residue amplifier of an ADC in accordance with some embodiments. 
         FIG. 5  is a circuit diagram illustrating aspects of a successive approximation register (SAR) stage of an ADC in accordance with some embodiments. 
         FIG. 6  is a phase diagram illustrating the SAR clock signals in accordance with some embodiments. 
         FIG. 7  depicts an analog-to-digital conversion method in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Analog-to-digital converters (ADC) convert an analog voltage signal into a digital signal. For example, a pipelined, or sub-ranging, ADC uses two or more steps of sub-ranging. A coarse conversion of an analog input voltage to a coarse digital value is done, then the coarse digital value is converted back to an analog signal with a digital-to-analog converter (DAC). The coarse value is compared to the input voltage with an analog comparator, and the difference, or residue, is then converted finer and the results are combined. 
     A successive-approximation ADC uses a comparator to successively narrow a range that contains the input voltage. At each successive step, the converter compares the input voltage to the output of a DAC that might represent the midpoint of a selected voltage range. At each step in this process, the approximation is stored in a successive approximation register (SAR). The steps are continued until the desired resolution is reached. With some ADC methods, it can be difficult to attain a sufficiently high signal to noise ratio (SNR) and conversion bandwidth in low voltage deep submicron processes. 
     Some pipelined ADC methods use a switched capacitor Multiplying DAC (MDAC) which tends to be limited in conversion bandwidth. While pipelined ADCs can provide high resolution and high bandwidth conversion, they also tend to be power hungry because they use several switched capacitor MDACs. Similarly, while SAR ADCs provide a relatively low power architecture, they also use a traditional switched capacitor MDAC. Such ADC methods may not be readily scalable to deep sub-micron process technologies while attaining good power efficiency. 
     The present disclosure includes examples of a multi-stage pipelined ADC with a current steering first stage and a cascaded SAR second stage. As discussed in further detail below, disclosed examples employ both current domain and voltage domain signal processing to attain high sampling rates and low power consumption. In some disclosed examples, this is achieved by the use of a low power current steering DAC approach, where a combined current steering DAC and a transconductance amplifier cell are employed. A high conversion rate is achievable because the proposed current steering DAC is inherently faster than a switched capacitor method for the same power consumption by essentially replacing the switched capacitor network of a conventional switched capacitor MDAC with feedback resistors to convert the residue current signals to a voltage signal. 
       FIG. 1A  generally illustrates an example of an ADC system  100  in accordance with some disclosed embodiments. In general, the ADC system  100  includes a first MDAC stage  10  coupled to an input terminal  102  that receives an analog input voltage signal V IP /V IM . The first MDAC stage  10  includes a first sub-ADC stage  30  configured to output a first digital value corresponding to the analog input voltage. In some examples, the first digital value output by the first MDAC stage  10  is the most significant bits (MSB) of the ADC digital output signal. The first MDAC stage  10  further includes a current steering DAC stage  40  that is connected to the input terminal  102  and receives the output of the first sub-ADC stage  30 . The current steering DAC stage  40  converts the analog input voltage and the first digital value to respective first and second current signals, determines a residue current signal representing a difference between the first current signal and the second current signal in the current domain, and converts the residue current signal to an analog residual voltage output signal Vres. 
     A second ADC stage  20  is coupled to the first MDAC stage  10  to receive the analog residual voltage signal Vres, and convert the analog residue voltage signal Vres to a second digital value, which in the illustrated example is the least significant bits (LSB) of the ADC digital output signal. An alignment and digital error correction stage  50  is configured to combine the first and the second digital values MSB, LSB and output a digital value D out  representing the analog input signals at an output terminal  104 . 
       FIG. 1B  depicts further aspects of the ADC system  100  shown in  FIG. 1A . In  FIG. 1B , the first sub ADC stage  30  of the first MDAC stage  10  includes a flash sub-ADC  125 , while the second ADC stage  20  includes a cascaded successive approximation register (SAR)  135  ADC. 
     The input terminal  102  is configured to receive differential analog input signals V IP  and V IM , which are sampled by a switched capacitor network  185 . As discussed further below, various control signals ( 170 ,  175 ,  180 ) are provided to control the operation of a plurality of switches  101  as well as the flash ADC  125  and the current steering digital-to-analog converter (IDAC)  130 . 
     The illustrated first sub-ADC stage  30  includes a flash sub-ADC  125  to generate the first digital value MSB of the digital output signal V out . The flash sub-ADC  125  receives the differential analog input signals V IP , V IM  and converts this analog signal to the first digital value at an output terminal that is connected to the alignment and digital error correction stage  50  and the current steering DAC stage  40 . The current steering DAC stage  40  is comprised of a transconductance amplifier (Gm)  115  to perform a voltage-to-current conversion of the sampled input signal. In the illustrated example, the Gm  115  does not receive a current feedback signal and thus operates open loop. Examples of the current steering DAC stage  40  also have a current steering IDAC  130  configured to receive and convert the first digital value received from the flash sub-ADC  125  back to an analog representation in the current domain. The Gm  115  and IDAC  130  output currents are combined to generate a residue current representing the difference between the first digital value and the input voltage, which is then converted to the voltage residue signal Vres and output to the second ADC stage  20 . As discussed further below, in some examples, the operations of the Gm cell  115  and the IDAC  130  are merged or combined into a common circuit, thus simplifying the actual circuit implementation. Additionally, the Gain-Bandwidth requirements of the residue amplifier may be significantly reduced since the Gain-Bandwidth is inversely proportional to the residue amplifier feedback factor and the disclosed amplifier has a feedback factor close to unity. This in turn reduces the power consumption of the circuit compared to conventional switched capacitor MDAC methods. 
     The residue amplifier  120  is configured to receive the residue current Ires,p/Ires,m from the Gm  115  and IDAC  130 , and convert the residue current Ires,p/Ires,m into the residue voltage signal Vres based on the feedback resistors  190 . The residue voltage Vres represents the difference between the analog input voltage and the first digital representation of the analog input voltage signal output by the Flash sub-ADC  125 . As discussed further herein below, the residue amplifier may include two stages, the first stage employing a wideband self-biased amplifier and the second stage having a common mode feedback circuit. The residue voltage is then passed to the second ADC stage  20  of the ADC system  100 . Employing a current mode processing of the residue, rather than a switched-capacitor device reduces influences of capacitor loading on the residue amplifier to improve performance. 
     In the illustrated example, the second ADC stage  20  is coupled to receive the residue voltage output by the current steering DAC stage  40 . Additionally, second ADC stage  20  is configured to convert the residue voltage into the second digital value representing the least significant bits (LSBs) of the digital output signal. The MSBs and LSBs are received and combined in the alignment and digital error correction stage  50 , which outputs the digital representation D out  of the analog input voltage at the output terminal  104 . In the illustrated example, the first ADC stage  10  provides 4 bit MSBs, and the second ADC stage  20  provides 9 bit LSBs to the alignment and digital error correction stage  50 , which provides a 12 bit digital output signal (one bit is redundant and is used to accomplish the digital error correction function). 
     Using current steering instead of switch capacitors in the first MDAC stage  10  reduces the gain-bandwidth (GBW) requirements of the amplifier for a given settling accuracy. Referring to Equations 1 and 2 shown below, generally, the gain bandwidth is required to be greater than or equal to two times the sampling frequency (F S ) times the natural log of two times the number of bits converted after the first MDAC stage  10 , or “backend bits” (N BACKEND ) all over the feedback factor (β) (see Equation 1). In Equations 1 and 2, β is defined as R GM  (or R DAC ) divided by R GM  (or R DAC ) plus RF, see Equation 2. The feedback factor β is close to unity in the current steering DAC since the resistance of RF 190 is small compared to the resistance of the IDAC  130  and GM  115 . A switched capacitor MDAC has a β much less than unity, which indicates a larger GBW is required for the same settling accuracy vis-à-vis the current steering approach. 
     
       
         
           
             
               
                 
                   GBW 
                   ≥ 
                   
                     
                       2 
                       * 
                       
                         F 
                         s 
                       
                       * 
                       
                         Ln 
                         ⁡ 
                         
                           ( 
                           2 
                           ) 
                         
                       
                       * 
                       
                         N 
                         backend 
                       
                     
                     β 
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
             
               
                 
                   β 
                   = 
                   
                     
                       
                         
                           R 
                           GM 
                         
                         || 
                         
                           R 
                           DAC 
                         
                       
                       
                         
                           R 
                           GM 
                         
                         || 
                         
                           
                             R 
                             DAC 
                           
                           + 
                           
                             R 
                             F 
                           
                         
                       
                     
                     ≈ 
                     1 
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     Thus, the Gain-Bandwidth requirements of the disclosed residue amplifier are significantly reduced, since the Gain-Bandwidth is inversely proportional to the feedback factor, β, and the example residue amplifier arrangement has a feedback factor close to unity. As an example, GBW requirements for a 12 bit/500 MSPS ADC using current steering would be less than 10 GHz, while an ADC of the same specifications using switched capacitors instead of current steering would have a GBW requirement of greater than 100 GHz. 
       FIG. 2  depicts an example of the control signals  170 ,  175  for the switches  101 , the Gm  115 , the flash ADC  125 , the IDAC  130 , the residue amplifier  120 , and the SAR  135 . The switches  101  turn on when the first phase control signal  170  goes high at a time  230 , resulting in the sampling capacitors  185  charging based on the analog input signals V IP , V IM . When the first phase signal  170  goes low at time  232 , the switches  170  open and the Gm  115  and the flash ADC  125  sample the analog input signals V IP , V IM . The flash ADC  125  and the IDAC  130  complete the respective conversions and latches the output based on the second phase control signal  175  going high at a time  220 . Additionally, when the first phase control signal  170  is high, the residue current signals from the Gm  115  and IDAC  130  are not output to the residue amplifier  120  while the input signals V IP , V IM  are sampled, allowing the residue amplifier  120  to be reset. 
       FIG. 3  is a circuit diagram  300  illustrating aspects of an example of the IDAC  130  and transconductance amplifier (Gm)  115  of the ADC  100 . In some examples, the IDAC  130  is comprised of a plurality of DAC unit cells  130 , and the Gm  115  may also include a plurality of Gm cells  115 . 
     Each of the IDAC  130  cells includes transistors  340  and  342 . The transistor  340  is controlled by bias voltage V b1  and is connected between a voltage terminal VDD and the transistor  342 , which receives a bias voltage V b2  at its gate terminal. The transistors  340  and  342  are configured to provide a current source representing the least significant digits I LSb1  to transistors  344  and  346  based on the MSB digital output signal. Control signals D and DZ are received at respective gate terminals to control the operation of the transistors  344  and  346  to output the residual current signals I res,p , I res,m  representing the analog residual voltage signal. The control signals D and DZ are provided by the first stage flash ADC  125  outputs. 
     The Gm cell  115  converts the analog input voltage signals V IP  and V IM  from the voltage domain into a representation of the voltage in the current domain. The GM cell  115  includes current sources  355  and resistors R S    360 . The transistors  348 ,  350  are connected to the current sources  355 , with the analog input voltage signals V IP  and V IM  coupled to the respective gate terminals of the transistors  348 ,  350 . The Gm cell  115  thus provides current signals Igm,p/Igm,m representing the sampled analog input voltage signals V IP  and V IM . As noted above, the IDAC unit cell  130  outputs a current signal Idac,p/Idac,m representing the analog input signals. The IDAC  130  and Gm  115  output the residue current signals Ires,p/Ires,m, which represents the difference between the current signals Igm,p/Igm,m output by the Gm unit cell  115  and the current signals Idac,p/Idac,m output by the IDAC cells  130 . The residue current signal Idac,p/Idac,m is received by the residue amplifier  120 , which outputs the voltage residue signals that represents the difference between the sample input voltage and the first digital signal output by the sub ADC  125 . 
     Thus, the operations of the Gm  115  and the IDAC  130  may be merged into a common circuit as shown in  FIG. 3 , which may simplify the circuit implementation. More particularly, in some disclosed examples the incoming voltage signals are converted into current, a voltage-to-current converter (Gm cell  115 ) may be used to perform the transformation between the voltage and current domains. The Gm cell  115  yields a current given by the Equation 3 shown below. 
     
       
         
           
             
               
                 
                   
                     
                       I 
                       resp 
                     
                     - 
                     
                       I 
                       resm 
                     
                   
                   = 
                   
                     
                       1 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         I 
                         LSB 
                       
                     
                     - 
                     
                       
                         ( 
                         
                           
                             V 
                             IP 
                           
                           - 
                           
                             V 
                             IM 
                           
                         
                         ) 
                       
                       
                         2 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           R 
                           S 
                         
                       
                     
                     - 
                     
                       ( 
                       
                         
                           2 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             I 
                             B 
                           
                         
                         + 
                         
                           I 
                           C 
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     As seen from Equation 3, the output current (I res,p −I res,m ) of the combined circuit yields a current containing the IDAC  130  current (1I LSB ), the Gm  115  current (V IP −V IM  divided by 2R S ) and bias currents (2I B +I C ), and therefore represents a “merged” current comprising the Gm and DAC currents. 
       FIGS. 4A and 4B  illustrate aspects of an example of the residue amplifier  120 , which may be a transimpedance amplifier configured to convert the residue current signal to an analog voltage signal output to the second ADC stage  20 . In some examples, the residue amplifier  120  is a two-stage residue amplifier with feed forward compensation. 
     The residue amplifier  120  illustrated in  FIG. 4A  may be a fully differential amplifier that comprises a first stage  402  and a second stage  404 . The first stage  402  contains input pair transistors  440   b  and  440   c  having gate terminals coupled to the differential input voltage signals V IP /V IM , with a load that may include a resistor pair  420 , and transistors  415   b  and  415   c . The bias current is set by a current source  445  including the residue current Ires output by the combined Gm  115  and IDAC  130 . The differential outputs Vres,p/Vres,m of the first stage  402  represent the residue signal output by the first MDAC stage  10 , and are coupled to the inputs of the second stage  404  via transistors  415   d  and  415   a . The second stage  404  includes transistors  440   d ,  415   d ,  440   a  and  415   a . The resistors  190  feedback the residue voltage signals Vres,p and Vres,m from the second stage  404  output back to the first stage inputs V IM  and V IP . The amplifier is compensated by capacitors  435  and  430 . 
     The resultant currents provided by the Gm  115  and IDAC  130  are amplified and converted back into the voltage domain for later use by the SAR  135  to produce the LSBs of the digital output signal Dout. The differential input voltages V IM  and V IP , are coupled to the current signals Igm and Idac via the transistors  350  and  348  as shown in  FIG. 3 . In addition, the residue voltage signals Vres,p/Vres,m output by the amplifier are connected to the input voltages V IM  and V IP  in a negative feedback configuration through the feedback resistors  190 . 
       FIG. 4B  shows an example of a common-mode feedback circuit  410  that provides a common mode feedback voltage signal V CMFB  to the amplifier  120  shown in  FIG. 4A . The residue voltage signals Vres,p/Vres,m output by the amplifier  400  are sampled by a common mode detector circuit  472 . The common mode detector  472  is comprised of capacitors  480  and resistors  475 . The common mode detector  472  takes an average of the residue voltage signals Vres,p, Vres,m and that average is sent to the positive terminal of an error amplifier  490 . The error amplifier  490  compares the averaged voltage to the common mode voltage V CM  and outputs the common mode feedback voltage V CMFB  to the first stage of the residue amplifier  400  via the resistors  465 . 
       FIG. 5  depicts an example of the second ADC stage  20 , which includes a SAR ADC  135  in some examples. The SAR ADC  135  includes a sample and hold circuit  501 , a comparator  560  and SAR logic  140 . The SAR logic  140  receives a clock signal CLKS and provides an output signal ϕ SAR  to the sample and hold circuit  501 . The output signal ϕ SAR  controls the operation of a plurality of switches  510  to selectively connect one side of a plurality of capacitors. In the illustrated example, there are two sets of capacitors  520   a ,  520   b  corresponding respectively to the differential residue voltage inputs Vres,p and Vres,m. Each of the sets of capacitors  520   a ,  520   b  includes a plurality of capacitors C 0 -C N , where N may correspond to the number of bits to be converted, such as the LSB bits shown in  FIG. 1B . In some examples, the capacitors are binary weighted, with the minimum capacitor size C being about 2 fF in some embodiments. The control signal  170  controls various SPDT switches  505  used to connect the sample and hold circuit  501  to the input residue voltages Vres,p and Vres,m, and to a reference signal V ref  as well as switches  101  connecting the common mode voltage signal V CM  to the sample and hold circuit  501  and the comparator  560 . 
     Referring to  FIG. 2 , when the control signal ϕ 1    170  is high, switches  505  connect the analog residue input signals Vres,p and Vres,m to the top plates of the capacitors C 0 -C N  of the sets of capacitors  520   a ,  520   b . At the same time, the bottom plates of the capacitors C 0 -C N  and the inputs of the comparator  560  are coupled to the common mode voltage V CM  due to switches  101  closing. During the next phase the output signal ϕ SAR  pulses are asserted to control the binary search algorithm implemented by the SAR logic  135  to generate the second digital output representing the LSBs of the analog input voltage. 
       FIG. 6  illustrates an example phase diagram for the control signal ϕ 1    170  and the output signal ϕ SAR . The control signal ϕ 1    170  is used for tracking and holding the signal in the SAR ADC  135  of the second ADC stage  20  of the ADC  100  while the output signal ϕ SAR  is used to control the operation of the switches  510  shown in  FIG. 5 . When the input control signal ϕ 1    170  goes low as shown at a time  602 , the output signal ϕ SAR  starts cycling and provides a plurality of output pulses  604  to control the switches  510  and sample the differential input signals V IP  and V IM  via the sets of capacitors  520   a ,  520   b . When the control signal ϕ 1    170  goes high such as at the time  606 , the output signal ϕ SAR  stops cycling and the output pulses  604  cease. 
       FIG. 7  shows an example of an ADC method  700  implemented by the ADC  100 . The method  700  starts at block  702  where an analog input voltage V IP , V IM  is received, for example, at the input terminals  102  shown in  FIG. 1B . At block  704  the analog input voltage is converted to a first digital value, which may be the MSBs for the digital output signal, and at block  706  the analog input voltage is converted into a first current I gm,p , I gm,m . At block  708  the first digital value is converted to a second current I dac,p , I dac,m . The first and second current signals are combined into a residue current signal I res,p , I res,m  in block  710 . At block  712 , and analog residue voltage is generated from the residue current. This residue voltage is then used in the generation of a second digital value in block  714 , which may be the LSBs of the digital output signal. In block  716  the first digital value and the second digital value are combined to create the digital output signal representing the analog input signal. 
     Accordingly, the various embodiments disclosed herein provide an ADC method and system that can achieve a high conversion rate and high accuracy with good power efficiency. Disclosed embodiments include a first ADC stage with a first sub-ADC stage configured to output a first digital value corresponding to an analog input voltage. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first current signal and the second current signal in the current domain, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values into a digital output voltage. 
     In accordance with additional embodiments, an ADC conversion method includes receiving an analog input voltage signal, converting the analog input voltage signal to a first digital signal, and converting the analog input voltage to a first current signal. The first digital value is converted to a second current signal, and the first and second currents are combined into a residue current signal. The residue current signal is converted to an analog residue voltage signal, and the analog residue voltage signal is converted to a second digital signal. The first and second digital signals are combined into a digital output signal representing the analog input voltage signal. 
     In accordance with still further examples, an ADC has an input terminal configured to receive an analog input voltage. A sub ADC is configured to sample the received analog input voltage signal and output a first digital signal representing the analog input voltage signal. A transconductance amplifier is configured to sample the received analog input voltage signal and output a first current signal. A DAC converter is configured to receive the first digital signal and output a second current signal representing the first digital signal, and a residual amplifier is configured to receive the first and second current signals and output an analog residual voltage signal based on the first and second current signals. A residue ADC is configured to receive the analog residue voltage signal and output a second digital signal representing the analog residue voltage signal. An alignment and error correction circuit is configured to combine the first and second digital signals. 
     This disclosure outlines various embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.