Patent Publication Number: US-2023144740-A1

Title: Semiconductor device

Description:
TECHNICAL FIELD 
     The present technology (the technology according to the present disclosure) relates to a semiconductor device, and particularly relates to a technology effective by being applied to a semiconductor device using a memory cell array unit as a product-sum calculation circuit. 
     BACKGROUND ART 
     A complementary MOS (CMOS) circuit including an re-channel conductive metal oxide semiconductor field effect transistor (MOSFET) (hereinafter, referred to as an n-type MOSFET) and a p-channel conductive MOSFET (Hereinafter, referred to as a p-type MOSFET) on the same substrate has low power consumption, is easily miniaturized and highly integrated, and can operate at a high speed, and thus is widely used as many LSI constituent devices. In particular, an LSI having multiple functions mounted on one chip together with an analog circuit and a memory is commercialized as a system on chip (SoC). 
     Here, a static random access memory (SRAM), which is one of the volatile memories, is mixed in many system on chips from the viewpoint of process affinity with a CMOS with less process addition. 
     The SRAM performs arithmetic processing in combination with a central processing unit (CPU) as a cache memory, but there is a problem of delay and power consumption between the memory and the CPU. In recent years, a neural network circuit has been put into practical use as an application for authentication of images or patterns. By using a memory array for a product-sum calculation of the neural network circuit, it can be expected to solve the delay and power consumption between a memory and a CPU, which are problems of the Neumann type computing. 
     Patent Document 1 discloses a product-sum calculation device including a product-sum calculation circuit in which a plurality of synapses in which a nonvolatile variable resistance element and a fixed resistance element are connected in series is arranged in a matrix. 
     CITATION LIST 
     Patent Document 
     Patent Document 1: Japanese Patent Application Laid-Open No. 2019-179499 
     Patent Document 2: Japanese Patent Application Laid-Open No. 2004-335535 A 
     Patent Document 3: Japanese Patent Application Laid-Open No. 2011-035398 
     SUMMARY OF THE INVENTION 
     Problems to be Solved by the Invention 
     Incidentally, as an example of product-sum calculation, for example, product-sum computation is performed according to a method of using a resistance (R) as load data, using a voltage (V) as an input, and adding the product (V×1/R)=I current (charge amount). As a memory, an SRAM may be applied, but it is necessary to use the SRAM as a resistor corresponding to load data. 
     As a method of using an SRAM and a resistor, an FET may be connected to an SRAM cell having a normal six-transistor configuration (six MOSFETs), and a channel of the connected FET may be used as a resistor. A circuit in which a plurality of FETs is connected to an SRAM cell having a six-transistor configuration is used as a multi-port SRAM capable of performing parallel reading and simultaneous writing/reading. 
     In Patent Document 2, two FETs are connected to an SRAM cell having a six-transistor configuration, and in Patent Document 3, four FETs are connected to an SRAM cell having a six-transistor configuration, and parallel reading and simultaneous writing/reading are performed by a plurality of word lines and bit lines. In any circuit configuration, a cell current of 100 μA level is required to increase a speed. 
     In a case where a MOSFET having a channel resistance of a cell current (Icell) of, for example, the above-described 100 μA level is applied as the resistance (R) in product-sum calculation, a channel resistance of about 1 k to 100 kΩ (kilo-ohm) is obtained by V/Icell (where V is assumed to be about 0.5 V to 3 V). For example, in a case where the product (V×1/R)=I current (charge amount) of the resistance (R) and the input voltage (V) in the product-sum calculation is output as a signal, the signal is output as a charge amount stored in load capacitance. In this case, a response speed is output as a time constant (T) of approximately CR, and assuming that load capacitance of cell array is, for example, about 100 fF, T=1 ns is obtained at R=10 kΩ. It is difficult to process a change at a response speed of about 1 ns in a subsequent circuit, for example, a DA converter, and a resistance of about GΩ (giga-ohm) is required to control the response speed to a level that can be processed by the circuit, for example, to about 1 μs. 
     Furthermore, in a case where a dendrite line as a summation line is charged with product-sum charge of multiple bits (for example, 1024), a low resistance state (LRS) needs to be sufficiently larger than the dendrite line, and for example, a resistance of 1 MΩ (megaohm) or more is required. 
     However, in order to achieve such resistance with a MOSFET, it is necessary to set a channel width (W) to 1/1000 or to set a channel length (L) to 1000 times, and an occupied area of a memory cell greatly increases, and thus manufacturing cost is increased. 
     An object of the present technology is to provide a semiconductor device capable of performing a product-sum calculation with high power efficiency while maintaining a small area of a memory cell. 
     Solutions to Problems 
     (1) According to an aspect of the present technology, there is provided a semiconductor device including a memory cell array in which a plurality of memory cells is arranged in a matrix. Then, each memory cell of the plurality of memory cells includes a flip-flop circuit including two inverter circuits in each of which a load field effect transistor and a drive field effect transistor are connected in series, input portions and output portions of the two inverter circuits being cross-joined to each other, two transfer field effect transistors each having a gate electrode connected to a word line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the output portions of the two inverter circuits, and two resistance elements of which one end sides are respectively connected to the second main electrode regions of the two transfer field effect transistors and other end sides are respectively connected to a bit line and a bit line bar. 
     (2) According to another aspect of the present technology, there is provided a semiconductor device including a memory cell array in which a plurality of memory cells is arranged in a matrix. Then, each memory cell of the plurality of memory cells includes a flip-flop circuit including two inverter circuits in each of which a load field effect transistor and a first drive field effect transistor are connected in series, input portions and output portions of the two inverter circuits being cross-joined to each other, two first transfer field effect transistors each having a gate electrode connected to a word line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the output portions of the two inverter circuits, and the second main electrode regions being respectively connected to a bit line and a bit line bar, two second drive field effect transistors each having a gate electrode and a pair of first and second main electrode regions, the gate electrodes being respectively connected to the input portions of the two inverter circuits, and the first main electrode regions being connected to each other, two second transfer field effect transistors each having a gate electrode connected to the word line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the second main electrode regions of the two second drive field effect transistors, and two resistance elements of which one end sides are respectively connected to the second main electrode regions of the two second transfer field effect transistors and other end sides are respectively connected to a dendrite line and a dendrite line bar. 
     (3) According to still another aspect of the present technology, there is provided a semiconductor device including a memory cell array in which a plurality of memory cells is arranged in a matrix. Then, each memory cell of the plurality of memory cells includes a flip-flop circuit including two inverter circuits in each of which a load field effect transistor and a first drive field effect transistor are connected in series, input portions and output portions of the two inverter circuits being cross-joined to each other, a first transfer field effect transistor having a gate electrode connected to a word line, and a pair of first and second main electrode regions, the first main electrode region being connected to the output portion of the other inverter circuit of the two inverter circuits, and the second main electrode region being connected to a bit line bar, two second drive field effect transistors each having a gate electrode and a pair of first and second main electrode regions, the gate electrodes being respectively connected to the input portions of the two inverter circuits, and the first main electrode regions being connected to each other, two second transfer field effect transistors each having a gate electrode connected to an axon line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the second main electrode regions of the two second drive field effect transistors, and two resistance elements of which one end sides are respectively connected to the second main electrode regions of the two second transfer field effect transistors and other end sides are respectively connected to a dendrite line and a dendrite line bar. 
     (4) According to still another aspect of the present technology, there is provided a semiconductor device including a memory cell array in which a plurality of memory cells is arranged in a matrix. Then, each memory cell of the plurality of memory cells includes a flip-flop circuit including two inverter circuits in which a load field effect transistor and a first drive field effect transistor are connected in series, input portions and output portions of the two inverter circuits being cross-joined to each other, two first transfer field effect transistors each having a gate electrode connected to a word line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the output portions of the two inverter circuits, and the second main electrode regions being respectively connected to a bit line and a bit line bar, two second drive tunnel field effect transistors each having a gate electrode and a pair of n-type first main electrode region and p-type second main electrode region, the gate electrodes being respectively connected to the input portions of the two inverter circuits, and the n-type first main electrode region being connected to an axon line, and two second transfer tunnel field effect transistors each having a gate electrode connected to the word line, and a pair of n-type first main electrode region and p-type second main electrode region, the p-type second main electrode regions being respectively connected to the p-type second main electrode regions of the two second drive tunnel field effect transistors, and the n-type first main electrode regions being respectively connected to a dendrite line and a dendrite line bar. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1    is a diagram illustrating a schematic configuration of a memory cell array unit of a semiconductor device according to a first embodiment of the present technology. 
         FIG.  2    is an equivalent circuit diagram of the memory cell in  FIG.  1   . 
         FIG.  3    is a schematic plan view illustrating a planar pattern of the memory cell in  FIG.  1   . 
         FIG.  4 A  is a schematic sectional view illustrating a sectional structure taken along the line a 3 -a 3  in  FIG.  3   . 
         FIG.  4 B  is a schematic sectional view illustrating a sectional structure taken along the line b 3 -b 3  in  FIG.  3   . 
         FIG.  5    is a diagram illustrating a schematic configuration of a memory cell array unit of a semiconductor device according to a second embodiment of the present technology. 
         FIG.  6    is an equivalent circuit diagram of the memory cell in  FIG.  5   . 
         FIG.  7    is a diagram illustrating a schematic configuration of a memory cell array unit of a semiconductor device according to a third embodiment of the present technology. 
         FIG.  8    is an equivalent circuit diagram of the memory cell in  FIG.  7   . 
         FIG.  9    is a diagram illustrating a schematic configuration of a memory cell array unit of a semiconductor device according to a fourth embodiment of the present technology. 
         FIG.  10    is an equivalent circuit diagram of the memory cell in  FIG.  9   . 
         FIG.  11    is a transmissive circuit diagram illustrating a modification example of the memory cell according to the fourth embodiment. 
         FIG.  12    is a transmissive circuit diagram illustrating a modification example of the memory cell according to the fourth embodiment. 
     
    
    
     MODE FOR CARRYING OUT THE INVENTION 
     Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. 
     Note that, in all the drawings for describing the embodiments of the present technology, constituents having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. 
     Furthermore, each drawing is schematic and may be different from an actual one. Furthermore, the following embodiments exemplify a device or a method for embodying the technical idea of the present technology, and do not specify the configuration as follows. That is, various modifications can be applied to the technical idea of the present technology within the technical scope described in the claims. 
     Furthermore, in the following embodiments, in three directions orthogonal to each other in a space, a first direction and a second direction orthogonal to each other in the same plane are defined as an X direction and a Y direction, respectively, and a third direction orthogonal to the first direction and the second direction is defined as a Z direction. In the following embodiments, a thickness direction of a semiconductor layer (semiconductor substrate) will be described as the Z direction. 
     First Embodiment 
     In a first embodiment, an SRAM type memory cell including six field effect transistors and two resistance elements will be described. 
     &lt;&lt;Configuration of Memory Cell Array Unit&gt;&gt; 
     A semiconductor device  1  according to the first embodiment of the present technology includes a memory cell array unit  2  illustrated in  FIG.  1   . As illustrated in  FIG.  1   , in the memory cell array unit  2 , a plurality of memory cells  3  are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. Furthermore, in the memory cell array unit  2 , word lines WL extending in the X direction are arranged for each of the memory cells  3  arranged in the Y direction. Furthermore, in the memory cell array unit  2 , complementary bit lines (a bit line BL 1  and a bit line bar BL 2  (BL-)) extending in the Y direction are arranged for each of the memory cells  3  arranged in the X direction. Then, each memory cell  3  of the plurality of memory cells  3  is disposed at an intersection between the corresponding word line WL and the complementary bits (BL 1  and BL 2 ). 
     Here, during a product-sum calculation process (inference in a neural network), the memory cell array unit  2  functions as a product-sum calculation circuit, the word line WL functions as an axon, and the bit line BL 1  and the bit line bar BL 2  function as a dendrite and a dendrite bar (dendrite-). 
     &lt;&lt;Configuration of memory cell&gt;&gt; 
     As illustrated in  FIG.  2   , each of the plurality of memory cells  3  includes a flip-flop circuit  5 , two transfer field effect transistors (transfer gate transistors) Qt 1  and Qt 2 , and two resistance elements  6 A and  6 B. 
     The flip-flop circuit  5  includes two inverter circuits  4   a  and  4   b , and has a configuration in which input portions  4   a   1  and  4   b   1  and the output portions (storage node portions)  4   a   2  and  4   b   2  of two inverter circuits  4   a  and  4   b  are alternately cross-joined. 
     One inverter circuit  4   a  of the two inverter circuits  4   a  and  4   b  has a configuration in which a load field effect transistor (pull-up transistor) Qp 1  and a drive field effect transistor (pull-down transistor) Qd 1  are connected in series. The other inverter circuit  4   b  has a configuration in which a load field effect transistor Qp 2  and a drive field effect transistor Qd 2  are connected in series. 
     The two load field effect transistors Qp 1  and Qp 2 , the two drive field effect transistors Qd 1  and Qd 2 , and the two transfer field effect transistors Qt 1  and Qt 2  each have a gate insulating film, a gate electrode (control electrode), and a pair of first main electrode region and second main electrode region functioning as a source region and a drain region, and electrical conduction between the first main electrode region and the second main electrode region is controlled by a gate signal input to the gate electrode. Although the field effect transistors Qp 1 , Qp 2 , Qd 1 , Qd 2 , Qt 1 , and Qt 2  are not limited thereto, for example, the field effect transistors Qp 1 , Qp 2 , Qd 1 , and Qd 2  are configured by MOSFETs in which a gate insulating film is a silicon oxide (SiO 2 ) film. Furthermore, as the field effect transistors Qp 1 , Qp 2 , Qd 1 , Qd 2 , Qt 1 , and Qt 2 , a metal insulator semiconductor FET (MISFET) in which a gate insulating film is a silicon nitride (Si 3 N 4 ) film or a laminated film such as a silicon nitride film and a silicon oxide film may be used. Hereinafter, the load field effect transistor may be simply referred to as a load FET, the drive field effect transistor may be simply referred to as a drive FET, and the transfer field effect transistor may be simply referred to as a transfer FET. 
     The two load FETs Qp 1  and Qp 2  are configured by p-channel conductivity type MOSFETs. On the other hand, the two drive FETs Qd 1  and Qd 2  and the two transfer FETs Qt 1  and Qt 2  are configured by n-channel conductivity type MOSFTETs. That is, the memory cell  3  includes a CMOS circuit. 
     As illustrated in  FIG.  2   , in the one inverter circuit  4   a , the gate electrodes of the load FET Qp 1  and the drive FET Qd 1  are electrically connected to each other to configure an input portion  4   a   1 . Furthermore, the respective first main electrode regions (drain regions) of the load FET Qp 1  and the drive FET Qd 1  are electrically connected to each other to configure an output portion  4   a   2 . Furthermore, the second main electrode region (source region) of the drive FET Qd 1  is electrically connected to a ground line  28   c   1  (refer to  FIG.  3   ) to which a Vss potential (for example, 0 V) as a first reference potential is applied. Furthermore, the second main electrode region (source region) of the load FET Qp 1  is electrically connected to a power supply line  28   d  (refer to  FIG.  3   ) to which a Vdd potential (for example, 0.5 V to 1.2 V) as a second reference potential higher than the Vss potential as the first reference potential is applied. 
     As illustrated in  FIG.  2   , in the other inverter circuit  4   b , the gate electrodes of the load FET Qp 2  and the drive FET Qd 2  are electrically connected to each other to configure an input portion  4   b   1 . The first main electrode regions (drain regions) of the load FET Qp 2  and the drive FET Qd 2  are electrically connected to each other to configure an output portion  4   b   2 . Then, the second main electrode region (source region) of the drive FET Qd 2  is also electrically connected to a ground line  28   c   2  (refer to  FIG.  3   ) to which the Vss potential is applied similarly to the drive FET Qd 1 , and the second main electrode region (source region) of the load FET Qp 2  is also electrically connected to the power supply line  18   d  (refer to  FIG.  3   ) to which the Vdd potential is applied similarly to the load FET Qp 1 . 
     As illustrated in  FIG.  2   , in the two inverter circuits  4   a  and  4   b , the output portion  4   a   2  of one inverter circuit  4   a  is electrically connected to the input portion  4   b   1  of the other inverter circuit  4   b . That is, the first main electrode region (drain region) of each of the load FET Qp 1  and the drive FET Qd 1  configuring one inverter circuit  4   a  is electrically connected to the gate electrode of each of the load FET Qp 2  and the drive FET Qd 2  configuring the other inverter circuit  4   b.    
     Furthermore, the output portion  4   b   2  of the other inverter circuit  4   b  is electrically connected to the input portion  4   a   1  of the one inverter circuit  4   a . That is, the first main electrode region (drain region) of each of the load FET Qp 2  and the drive FET Qd 2  configuring the other inverter circuit  4   b  is electrically connected to the gate electrode of each of the load FET Qp 1  and the drive FET Qd 1  configuring the one inverter circuit  4   a.    
     Note that the respective output portions  4   a   2  and  4   b   2  of the two inverter circuits  4   a  and  4   b  configure a storage node portion of the memory cell  3 . 
     In the two transfer FETs Qt 1  and Qt 2 , in one transfer FET Qt 1 , the gate electrode is electrically connected to the word line WL, and the first main electrode region of the pair of first and second main electrode regions is electrically connected to the output portion  4   a   2  of one inverter circuit  4   a . In the other transfer FET Qt 2 , the gate electrode is electrically connected to the word line WL, and the first main electrode region of the pair of first and second main electrode regions is electrically connected to the output portion  4   b   2  of the other inverter circuit  4   b.    
     As illustrated in  FIG.  2   , in the two resistance elements  6 A and  6 B, one resistance element  6 A has one end side electrically connected to the second main electrode region of one transfer FET Qt 1  and the other end side electrically connected to the bit line BL 1 . In the other resistance element  6 B, one end side is electrically connected to the second main electrode region of the other transfer FET Qt 2 , and the other end side is electrically connected to the bit line bar BL 2 . 
     &lt;&lt;Specific Configuration of Memory Cell&gt;&gt; 
     Next, a specific configuration of the memory cell  3  will be described in detail with reference to  FIGS.  3 ,  4 A , and  4 B. 
     &lt;Configuration of FFT&gt; 
     In the one inverter circuit  4   a , as illustrated in  FIGS.  3  and  4 A , the load FET Qp 1  is configured in an n-type well region  12   a  corresponding to an n-type semiconductor region in an active region partitioned by an isolation region  11  on the main surface of the semiconductor layer  10 . The isolation region  11  is not limited thereto, but is configured by, for example, a shallow trench isolation (STI) structure constructed by forming a groove extending in the depth direction from the main surface of the semiconductor layer  10  and selectively burying an insulating film in the groove. 
     The load FET Qp 1  mainly includes a gate insulating film  15  provided on the main surface of the semiconductor layer  10 , a gate electrode  16   p  provided on the gate insulating film  15 , and a pair of first main electrode regions  17   p   1  and second main electrode regions  17   p   2 provided in the semiconductor layer  10  to be separated from each other in the channel length direction with a channel formation region immediately below the gate electrode  16   p  interposed therebetween and functioning as a source region and a drain region. The pair of first and second main electrode regions  17   p   1  and  17   p   2  is provided in the n-type well region  12   a.    
     In the inverter circuit  4   a , as illustrated in  FIGS.  3  and  4 B , the drive FET Qd 1  is configured in a p-type well region  12   b  from a p-type semiconductor region in an active region partitioned by the isolation region  11  on the main surface of the semiconductor layer  10 . The drive FET Qd 1  mainly includes a gate insulating film  15  provided on the main surface of the semiconductor layer  10 , a gate electrode  16   d  provided on the gate insulating film  15 , and a pair of first main electrode region  17   d   1  and second main electrode region  17   d   2  provided in the semiconductor layer  10  to be separated from each other in the channel length direction with a channel formation region immediately below the gate electrode  16   d  interposed therebetween and functioning as a source region and a drain region. The pair of first and second main electrode regions  17   d   1  and  17   d   2  is provided in the p-type well region  12   b.    
     As illustrated in  FIGS.  3  and  4 B , one transfer FET Qt 1  is configured in a p-type well region  12   b  in an active region defined by the isolation region  11  on the main surface of the semiconductor layer  10 . One transfer FET Qt 1  mainly includes a gate insulating film  15  provided on the main surface of the semiconductor layer  10 , a gate electrode  16   t  provided on the gate insulating film  15 , and a pair of first main electrode region  17   t   1  and second main electrode region  17   t   2  provided in the semiconductor layer  10  to be separated from each other in the channel length direction with a channel formation region immediately below the gate electrode  16   t  interposed therebetween and functioning as a source region and a drain region. The pair of first and second main electrode regions  17   t   1  and  17   t   2  is provided in the p-type well region  12   b . The transfer FET Qt 1  and the drive FET Qd 1  have a structure in which the respective first main electrode regions  17   t   1  and  17   d   1  are made common (shared). 
     The semiconductor layer  10  is configured with, for example, a p-type semiconductor substrate including single crystal silicon. The gate insulating film  15  is configured with, for example, a silicon oxide (SiO 2 ) film. The gate electrodes  16   p ,  16   d , and  16   t  are configured with, for example, a composite film in which a silicide film is laminated on a polycrystalline silicon film into which an impurity for reducing a resistance value is introduced. 
     The pair of first and second main electrode regions  17   p   1  and  17   p   2  includes, for example, an extension region including a p-type semiconductor region, a contact region including a p-type semiconductor region having a higher impurity concentration than that of the extension region, and a silicide film provided on the contact region. The pair of first and second main electrode regions  17   d   1  and  17   d    2  and the pair of first and second main electrode regions  17   t   1  and  15   t   2  include, for example, an extension region including an n-type semiconductor region, a contact region including an n-type semiconductor region having a higher impurity concentration than that of the extension region, and a silicide film provided on the contact region. 
     As illustrated in  FIGS.  4 A and  4 B , each of the load FET Qp 1 , the drive FET Qd 1 , and the transfer FET Qt 1  is covered with an interlayer insulating film  21  provided on the semiconductor layer  10 . 
     In the other inverter circuit  4   b , the transfer FET Qt 2  has a configuration similar to that of the above-described transfer FET Qt 1 , and the drive FET Qd 2  has a configuration similar to that of the above-described drive FET Qd 1 . Then, the other transfer FET Qt 2  has a configuration similar to that of the above-described transfer FET Qt 1 . Therefore, a description of specific configurations of the load FET Qt 2 , the drive FET Qd 2 , and the transfer FET Qt 2  will be omitted. 
     Furthermore, each of the load FETs Qp 1  and Qp 2 , the drive FETs Qd 1  and Qd 2 , and the transfer FETs Qt 1  and Qt 2  is configured by, for example, a lightly doped drain (LDD) structure and a self-aligned silicide (SALICIDE) structure, but a description of a specific configuration thereof will also be omitted. 
     Note that the load FET Qp 2 , the drive FET Qd 2 , and the transfer FET Q 2  are also covered with the interlayer insulating film  21 . 
     &lt;Configuration of Resistance Element&gt; 
     As illustrated in  FIG.  4 B , one resistance element  6 A is buried in an interlayer insulating film  24  provided on the interlayer insulating film  21 . The resistance element  6 A has, not limited to, a metal insulator metal (MIM) structure in which, for example, a first electrode  23   a  on one end side, an insulating film  23   b , and a second electrode  23   c  on the other end side are laminated in this order from the semiconductor layer  10  side. As each of the first electrode  23   a  and the second electrode  23   c , for example, a high melting point metal compound film such as a titanium nitride (TiN) film or a tantalum nitride (TaN) film may be used. As the insulating film  23   b , for example, a silicon oxide (SiO 2 ) film, an aluminum oxide (AlO 2 ) film, a magnesium oxide (MgO 2 ) film, a hafnium oxide (HfO 2 ) film, or a zirconium oxide (ZrO 2 ) film having a film thickness of about 1 to 3 nm can be used. 
     The other resistance element  6 B has a configuration similar to that of the above-described resistance element  6 A. Therefore, a description of a specific configuration of the other resistance element  6 B will be omitted. 
     The two resistance elements  6 A and  6 B can obtain a desired resistance value with a small area. For example, the resistance elements  6 A and  6 B can form a resistance value of 1 MΩ or more, which is necessary in a case where a bit line as a summation line is charged with product-sum charge for multiple bits (for example, 1024), within an occupied area of the memory cell  3  during a product-sum calculation process. Moreover, since the resistance elements  6 A and  6 B are disposed on the transfer FETs Qt 1  and Qt 2  , in other words, disposed to overlap the transfer FETs Qt 1  and Qt 2  in a plan view (refer to  FIGS.  3  and  4 B ), an increase in the planar size of the memory cell  3  can be suppressed. That is, the memory cell  3  of the first embodiment includes the two resistance elements  6 A and  6 B while maintaining a small area necessary for arrangement of six FETs (Q 1 , Qp 2 , Qd 1 , Qd 2 , Qt 1 , and Qt 2 ). 
     A resistance value of each of the two resistance elements  6 A and  6 B is preferably larger than a channel resistance value of the transfer FETs Qt 1  and Qt 2 , and more preferably 1 MΩ or more. 
     &lt;Configuration of One Inverter Circuit&gt; 
     As illustrated in  FIG.  3   , the gate electrodes  16   p  and  16   d  of the load FET Qp 1  and the drive FET Qd 1  configuring one inverter circuit  4   a  are integrally molded and electrically connected to each other. That is, the respective gate electrodes  16   p  and  16   d  of the load FET Qp 1  and the drive FET Qd 1  are connected to each other to configure the input portion  4   a   1  (refer to  FIG.  2   ). 
     As illustrated in  FIGS.  3  and  4 A , the first main electrode region  17   p   1  of the load FET Qp 1  is electrically connected to a relay wiring  25   a   1  formed in a first wiring layer on the interlayer insulating film  21  via a conductive plug  22   a  buried in the interlayer insulating film  21  on the semiconductor layer  10 . On the other hand, as illustrated in  FIGS.  3  and  4 B , the respective first main electrode regions  17   d   1  and  17   t   1  of the drive FET Qd 1  and the transfer FET Qt 1  are electrically connected to the relay wiring  25   a   1  via a conductive plug  22   b  buried in the interlayer insulating film  21  on the semiconductor layer  10 . That is, the respective first main electrode regions  17   p   1 ,  17   d   1  , and  17   t   1  of the load FET Qp 1 , the drive FET Qd 1 , and the transfer FET Qt 1  are electrically connected to each other to configure the output portion  4   a   2  (refer to  FIG.  2   ). The relay wiring  25   a   1  and relay wirings  25   c   1  to  25   e   1  that will be described later are buried in an interlayer insulating film  24  on the interlayer insulating film  21 . 
     As illustrated in  FIGS.  3  and  4 B , the second main electrode region  17   d   2  of the drive FET Qd 1  is electrically connected to the relay wiring  25   c   1  formed in the first wiring layer via a conductive plug  22   c  buried in the interlayer insulating film  21 . Then, the relay wiring  25   c   1  is electrically connected to a ground wiring  28   c   1  formed in a second wiring layer on the interlayer insulating film  26  and extending in the Y direction via a conductive plug  27   c  buried in the interlayer insulating film  26  on the interlayer insulating film  24 . The Vss potential as the above-described first reference potential is applied to the ground wiring  28   c   1 . That is, Vss potential is supplied from the ground wire  28   c   1  to the second main electrode region  17   d   2  of the drive FET Qd 1 . 
     As illustrated in  FIGS.  3  and  4 A , the second main electrode region  17   p   2  of the transfer FET Qp 1  is electrically connected to the relay wiring  25   d   1  formed in the first wiring layer via a conductive plug  22   d  buried in the interlayer insulating film  21 . Then, although not illustrated in detail, the relay wiring  25   d   1  is electrically connected to the power supply line  28   d  formed in the second wiring layer on the interlayer insulating film  26  and extending in the Y direction via the conductive plug buried in the interlayer insulating film  26 . The Vdd potential as the above-described second reference potential is applied to the power supply line  28   d . That is, the Vdd potential is supplied from the power supply line  28   d  to the second main electrode region  17   p   2  of the load FET Qp 1 . 
     As illustrated in  FIGS.  3  and  4 B , the second main electrode region  17   t   2  of the transfer FET Qt 1  is electrically connected to the first electrode  23   a  of the resistance element  6 A via a conductive plug  22   e  buried in the interlayer insulating film  21 . Then, the second electrode  23   c  of the resistance element  6 A is electrically and mechanically connected to the relay wiring  25   e   1  formed in the first wiring layer. Then, although not illustrated in detail, the relay wiring  25   e   1  is electrically connected to the bit line BL 1  (dendrite) formed in the second wiring layer on the interlayer insulating film  26  and extending in the Y direction via the conductive plug buried in the interlayer insulating film  26 . 
     &lt;Other Inverter Circuit&gt; 
     As illustrated in  FIG.  3   , the respective gate electrodes  16   p  and  16   d  of the load FET Qp 2  and the drive FET Qd 2  configuring the other inverter circuit  4   b  are integrally molded and electrically connected to each other. That is, the respective gate electrodes  16   p  and  16   d  of the load FET Qp 2  and the drive FET Qd 2  are connected to each other to configure the input portion  4   b   1  (refer to  FIG.  2   ). 
     As illustrated in  FIG.  3   , although not illustrated in detail, the first main electrode region  17   p   2  of the load FET Qp 2  is electrically connected to the relay wiring  25   a   2  formed in the first wiring layer on the interlayer insulating film  21  via the conductive plug buried in the interlayer insulating film  21  on the semiconductor layer  10 , similarly to that of the above-described load FET Qp 1 . On the other hand, although not illustrated in detail, the respective first main electrode regions  17   d   1  and  17   t   1  of the drive FET Qd 2  and the transfer FET Qt 2  are electrically connected to the relay wiring  25   a   2  via the conductive plug buried in the interlayer insulating film  21  on the semiconductor layer  10 , similarly to those of the drive FET Qd 1  and the transfer FET Qt 1  described above. That is, the respective first main electrode regions  17   p   1 ,  17   d   1 , and  17   t   1  of the load FET Qp 2 , the drive FET Qd 2 , and the transfer FET Qt 2  are electrically connected to each other to configure the output portion  4   b   2  (refer to  FIG.  2   ). The relay wiring  25   a   2  and the relay wiring  25   c   2  to  25   e   2  that will be described later are buried in the interlayer insulating film  24  on the interlayer insulating film  21 . 
     As illustrated in  FIG.  3   , although not illustrated in detail, the second main electrode region  17   d   2  of the drive FET Qd 2  is electrically connected to the relay wiring  25   c   2  formed in the first wiring layer via the conductive plug buried in the interlayer insulating film  21 , similarly to that of the above-described drive FET Qd 1 . Then, the relay wiring  25   c   2  is electrically connected to the ground wiring  28   c   2  formed in the second wiring layer on the interlayer insulating film  26  and extending in the Y direction via the conductive plug buried in the interlayer insulating film  26  on the interlayer insulating film  24 . The Vss potential (for example, 0 V) as the above-described first reference potential is applied to the ground wiring  28   c   2 . That is, the Vss potential is supplied from the ground wire  28   c   2  to the second main electrode region  17   d   2  of the drive FET Qd 2 . 
     As illustrated in  FIG.  3   , although not illustrated in detail, the second main electrode region  17   p   2  of the load FET Qp 2  is electrically connected to the relay wiring  25   d   2  formed in the first wiring layer via the conductive plug buried in the interlayer insulating film  21 , similarly to that of the above-described load field effect transistor Qp 1 . Then, the relay wiring  25   d   2  is electrically connected to the power supply line  28   d  formed in the second wiring layer on the interlayer insulating film  26  and extending in the Y direction via the conductive plug buried in the interlayer insulating film  26 . That is, the Vdd potential is supplied from the power supply line  28   d  to the second main electrode region  17   p   2  of the load FET Qp 2 . 
     As illustrated in  FIG.  3   , although not illustrated in detail, the second main electrode region  17   t   2  of the transfer FET Qt 2  is electrically connected to the first electrode  23   a  of the resistance element  6 B via the conductive plug buried in the interlayer insulating film  21 , similarly to that of the above-described transfer FET Qt 1 . Then, the second electrode  23   c  of the resistance element  6 B is electrically and mechanically connected to the relay wiring  25   e   2  formed in the first wiring layer. Then, the relay wiring  25   e   2  is electrically connected to the bit line bar BL 2  (dendrite-) formed in the second wiring layer on the interlayer insulating film  26  and extending in the Y direction via the conductive plug buried in the interlayer insulating film  26 . 
     &lt;Two Inverter Circuits&gt; 
     As illustrated in  FIG.  3   , although not illustrated in detail, the gate electrode  16   p  of the load FET Qp 1  is electrically connected to the relay wiring  25   a   2  via the conductive plug buried in the interlayer insulating film  21 . That is, the respective gate electrodes  16   p  and  16   d  of the load FET Qp 1  and the drive FET Qd 1  configuring the one inverter circuit  4   a  are electrically connected to the respective first main electrode regions  17   p   1  and  17   d   1  of the load FET Qp 2  and the drive FET Qd 2  configuring the other inverter circuit  4   b  and the first main electrode region  17   t   1  of the other transfer FET Qt 2 . 
     As illustrated in  FIG.  3   , although not illustrated in detail, the gate electrode  16   p  of the load FET Qp 2  is electrically connected to the relay wiring  25   a   1  via the conductive plug buried in the interlayer insulating film  21 . That is, the respective gate electrodes  16   p  and  16   d  of the load FET Qp 2  and the drive FET Qd 2  configuring the other inverter circuit  4   b  are electrically connected to the respective first main electrode regions  17   p   1  and  17   d   1  of the load FET Qp 1  and the drive FET Qd 1  configuring the one inverter circuit  4   a  and the first main electrode region  17   t   1  of the one transfer FET Qt 1 . 
     Note that, although not illustrated in  FIG.  3   , the respective gate electrodes  16   p  and  16   d  of the two transfer FETs Qt 1  and Qt 2  are electrically connected to the word line WL extending in the X direction. The word line WL is formed, for example, in a third wiring layer provided on the second wiring layer via the interlayer insulating film. 
     &lt;&lt;Write Operation and Product-Sum Calculation&gt;&gt; 
     Next, an operation of writing data to the memory cell  3  and a product-sum calculation will be described. 
     As a write operation to the memory cell  3 , by applying the Vcc potential (for example, 1 V) to the word line WL to turn on the two transfer FETs Qt 1  and Qt 2 , and setting the bit line BL 1  to the Vdd potential and the bit line bar BL 2  to the Vss potential, the output portion (storage node portion)  4   a   2  of one inverter circuit  4   a  is set to the Vcc potential and the output portion (storage node portion)  4   b   2  of the other inverter circuit  4   b  is set to the Vss potential. Even if the word line WL is set to the Vss potential, the flip-flop circuit  5  including the two inverter circuits  4   a  and  4   b  is stabilized. 
     On the other hand, at the time of a product-sum calculation (inference) using the memory cell array unit  2  as a product-sum calculation circuit, the bit line BL 1  as a dendrite and the bit line bar BL 2  as a dendrite bar (dendrite-) are precharged to the Vcc potential (for example, 1 V) in a state in which the flip-flop circuit  5  of the memory cell  3  stores data. Subsequently, a signal (for example, a pulse voltage) is sequentially input to the word line WL as an axon or to the plurality of word lines WL. When the signal reaches the Vcc potential, the respective transfer FETs Qt 1  and Qt 2  of the two inverter circuits  4   a  and  4   b  are turned on, and the drive FET Qd 2  of the other inverter circuit  4   b  having the gate electrode  16   d  connected to the output portion (storage node portion)  4   a   2  of the one inverter circuit  4   a  is turned on. Therefore, the charge of the bit line bar BL 2  is released toward the Vss potential, and the potential decreases. On the other hand, since the drive FET Qd 1  of one inverter circuit  4   a  in which the gate electrode  16   d  is connected to the output portion  4   b   2  of the other inverter circuit  4   b  is in an OFF state, the charge of the bit line BL 1  is not released, and the potential does not change. 
     Here, the potential of the bit line bar BL 2  (dendrite-) changes with the CR time constant of the resistance value R of the resistance element  6 B and the parasitic capacitance C parasitic on the bit line bar BL 2 . Therefore, by outputting or AD-converting a potential difference between the bit line BL 1  (dendrite) and the bit line bar BL 2  (dendrite-) in response to the CR time constant, the sum-product calculation with high power efficiency can be performed. 
     Note that the input potential to the word line WL, that is, the axon at the time of the sum-product calculation can be freely set separately from the Vcc potential or a write potential applied to the word WL at the time of writing data to the memory cell  3 . In a case where the conductance of the load FETs Qp 1  and Qp 2  is greater than the conductance of the resistance elements  6 A and  6 B, writing of data to the memory cell  3  is performed by cutting off the Vcc potential or the Vss potential. 
     &lt;&lt;Main Effects of First Embodiment&gt;&gt; 
     As described above, the memory cell  3  of the semiconductor device  1  according to the first embodiment includes the flip-flop circuit  5 , and the two transfer FETs Qt 1  and Qt 2 , and further includes the two resistance elements  6 A and  6 B. Then, each of the two resistance elements  6 A and  6 B has a resistance value of 1 MΩ or more, which is necessary in a case where a bit line as a summation line is charged with product-sum charge for multiple bits (for example, 1024), during the product-sum calculation process, and is disposed within an occupied area of the memory cell  3 . Therefore, according to the semiconductor device  1  of the first embodiment, it is possible to perform a product-sum calculation with high power efficiency while maintaining a small area of the memory cell  3 . 
     Second Embodiment 
     In a second embodiment, an SRAM-type memory cell including ten field effect transistors and two resistance elements will be described. 
     &lt;&lt;Configuration of Memory Cell Array Unit&gt;&gt; 
     A semiconductor device  1 A according to the second embodiment includes a memory cell array unit  2 A illustrated in  FIG.  5   . As illustrated in  FIG.  5   , in the memory cell array unit  2 A, a plurality of memory cells  3 A are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. Furthermore, in the memory cell array unit  2 A, word lines WL extending in the X direction are arranged for each of memory cells  3 A arranged in the Y direction. Furthermore, in the memory cell array unit  2 A, complementary bit lines (a bit line BL 1  and a bit line bar BL 2  (BL-)) extending in the Y direction are arranged for each of the memory cells  3 A arranged in the X direction. Furthermore, in the memory cell array unit  2 A, complementary dendrite lines (dendrite line DL 1  and dendrite line bar (dendrite line-) DL 2 ) extending in the Y direction are arranged for each of the memory cells  3 A arranged in the X direction. Then, each memory cell  3 A of the plurality of memory cells  3 A is disposed at an intersection between the corresponding word line WL and the complementary bit lines (BL 1  and BL 2 ) and complementary dendrite lines (DL 1  and DL 2 ). 
     Here, during a product-sum calculation process (inference in a neural network), the memory cell array unit  2 A functions as a product-sum calculation circuit, the word line WL functions as an axon, and the dendrite line DL 1  and the dendrite line bar DL 2  function as a dendrite and a dendrite bar (dendrite-). 
     &lt;&lt;Configuration of Memory Cell&gt;&gt;As illustrated in  FIG.  6   , each memory cell  3 A of the plurality of memory cells  3 A includes a flip-flop circuit  5 , two transfer FETs Qt 1  and Qt 2  as first transfer field effect transistors, two transfer FETs Qt 3  and Qt 4  as second transfer field effect transistors, two drive FETs Qd 3  and Qd 4  as second drive field effect transistors, and two resistance elements  6 A and  6 B. 
     The flip-flop circuit  5  includes two inverter circuits  4   a  and  4   b , and has a configuration in which input portions  4   a   1  and  4   b   1  and the output portions (storage node portions)  4   a   2  and  4   b   2  of two inverter circuits  4   a  and  4   b  are alternately cross-joined. 
     One inverter circuit  4   a  of the two inverter circuits  4   a  and  4   b  has a configuration in which a load FET (pull-up transistor) Qp 1  and a drive FET (pull-down transistor) Qd 1  as a first drive field effect transistor are connected in series. Furthermore, the other inverter circuit  4   b  has a configuration in which a load FET Qp 2  and a drive FET Qd 2  as a first drive field effect transistor are connected in series. 
     Similarly to the two drive FETs Qd 1  and Qd 2  and the two transfer FETs Qt 1  and Qt 2 , the two drive FETs Qd 3  and Qd 4  and the two transfer FETs Qt 3  and Qt 4  include a gate insulating film, a gate electrode (control electrode), and a pair of first main electrode region and second main electrode region functioning as a source region and a drain region, and electrical conduction between the first main electrode region and the second main electrode region is controlled by a gate signal input to the gate electrode. Then, the FETs Qd 3 , Qd 4 , Qt 3 , and Qt 4  are also configured by n-channel conductivity type MOSFETs, for example. 
     As illustrated in  FIG.  6   , in one transfer FET Qt 1  of the two transfer FETs Qt 1  and Qt 2 , similarly to the transfer FET Qt 1  of the first embodiment described above, the gate electrode is electrically connected to the word line WL, and the first main electrode region of the pair of first and second main electrode regions is electrically connected to the output portion  4   a   2  of one inverter circuit  4   a . Then, unlike the transfer FET Qt 1  of the first embodiment described above, the second main electrode region of one transfer FET Qt 1  is electrically connected to the bit line BL 1  without passing through the resistance element  6 A. 
     As illustrated in  FIG.  6   , in the other transfer FET Qt 2  of the two transfer FETs Qt 1  and Qt 2 , similarly to the transfer FET Qt 2  of the first embodiment described above, the gate electrode is electrically connected to the word line WL, and the first main electrode region of the pair of first and second main electrode regions is electrically connected to the output portion  4   b   2  of the other inverter circuit  4   b . Then, in the other transfer FET Qt 2 , unlike the transfer FET Qt 2  of the first embodiment described above, the second main electrode region is electrically connected to the bit line bar BL 2 without passing through the resistance element  6 B. 
     As illustrated in  FIG.  6   , one drive FET Qd 3  of the two drive FETs Qd 3  and Qd 4  has a gate electrode electrically connected to the gate electrode of each of the load FET Qp 1  and the drive FET Qd 1  configuring one inverter circuit  4   a . That is, the gate electrode of the one drive FET Qd 3  is electrically connected to the input portion  4   a   1  of the one inverter circuit  4   a.    
     As illustrated in  FIG.  6   , the other drive FET Qd 4  of the two drive FETs Qd 3  and Qd 4  has a gate electrode electrically connected to the gate electrode of each of the load FET Qp 2  and the drive FET Qd 2  configuring the other inverter circuit  4   b . That is, the gate electrode of the other drive FET Qd 4  is electrically connected to the input portion  4   b   1  of the other inverter circuit  4   b.    
     As illustrated in  FIG.  6   , the first main electrode region of each of the two drive FETs Qd 3  and Qd 4  is electrically connected to the ground wiring to which the Vss potential as a first reference potential is applied. 
     As illustrated in  FIG.  6   , in one transfer FET Qt 3  of the two transfer FETs Qt 3  and Qt 4 , the gate electrode is electrically connected to the word line WL, and the first main electrode region of the pair of first and second main electrode regions is electrically connected to the second main electrode region of the drive FET Qd 3 . Then, in the one transfer FET Qt 3 , the second main electrode region is electrically connected to the first electrode on one end side of the resistance element  6 A. Then, the second main electrode on the other end side of the resistance element  6 A is electrically connected to the dendrite line DL 1 . 
     As illustrated in  FIG.  6   , in the other transfer FET Qt 4  of the two transfer FETs Qt 3  and Qt 4 , the gate electrode is electrically connected to the word line WL, and the first main electrode region of the pair of first and second main electrode regions is electrically connected to the second main electrode region of the drive FET Qd 4 . Then, in the other transfer FET Qt 4 , the second main electrode region is electrically connected to the first electrode on one end side of the resistance element  6 B. Then, the second main electrode on the other end side of the resistance element  6 B is electrically connected to the dendrite line bar (dendrite line-) DL 2 . 
     Although not illustrated, the dendrite line DL 1  and the dendrite line bar DL 2  are formed in the second wiring layer and extend in the Y direction, for example, similarly to the bit line BL 1  and the bit line bar BL 2 . 
     The two resistance elements  6 A and  6 B of the second embodiment also have an MIM structure similarly to the resistance elements  6 A and  6 B of the first embodiment described above, can obtain a desired resistance value with a small area, and are arranged within an occupied area of the memory cell. Then, a resistance value of each of the two resistance elements  6 A and  6 B is preferably larger than a channel resistance value of the transfer FETs Qt 3  and Qt 4 , and more preferably 1 MΩ or more. 
     &lt;&lt;Write Operation and Product-Sum Calculation&gt;&gt; 
     Next, an operation of writing data to the memory cell  3 A and a product-sum calculation will be described. 
     As a write operation to the memory cell  3 A, by applying the Vcc potential (for example, 1 V) to the word line WL to turn on the two transfer FETs Qt 1  and Qt 2  and setting the bit line BL 1  to the Vcc potential and the bit line bar BL 2  to the Vss potential, the output portion (storage node portion)  4   a   2  of one inverter circuit  4   a  is set to the Vcc potential and the output portion (storage node portion)  4   b   2  of the other inverter circuit  4   b  is set to the Vss potential. Even if the word line WL is set to the Vss potential, the flip-flop circuit  5  including the two inverter circuits  4   a  and  4   b  is stabilized. 
     On the other hand, at the time of a product-sum calculation (inference) using the memory cell array unit  2 A as a product-sum calculation circuit, the dendrite line DL 1  and the dendrite line bar DL 2  are precharged to the Vcc potential (for example, 1 V) in a state in which the flip-flop circuit  5  of the memory cell  3 A stores data. Subsequently, a signal (for example, a pulse voltage) is sequentially input to the word line WL as an axon or to the plurality of word lines WL. When the signal reaches the Vcc potential, the two transfer FETs Qt 3  and Qt 4  are turned on, and the other drive FET Qd 4  having the gate electrode connected to the output portion (storage node portion)  4   a   2  of the one inverter circuit  4   a  is turned on. Therefore, the charge of the dendrite line bar DL 2  is released toward the Vss potential, and the potential decreases. On the other hand, since one drive FET Qd 3  having the gate electrode connected to the output portion  4   b   2  of the other inverter circuit  4   b  is in an OFF state, the charge of the dendrite line DL 1  is not released, and the potential does not change. 
     Here, the potential of the dendrite line bar DL 2  (dendrite line-) changes with the CR time constant of the resistance value R of the resistance element  6 B and the parasitic capacitance C parasitic on the dendrite line bar DL 2 . Therefore, by outputting or AD-converting a potential difference between the dendrite line DL 1  and the dendrite line bar DL 2  (dendrite line-) in response to the CR time constant, the sum-product calculation with high power efficiency can be performed. 
     Note that the input potential to the word line WL, that is, the axon at the time of the sum-product calculation can be freely set separately from the Vcc potential or a write potential applied to the word WL at the time of writing data to the memory cell  3 A. Writing of data into the flip-flop circuit  5  of the memory cell  3 A is usually performed at a high speed through an SRAM operation. The current consumption can be reduced by reducing the Vcc potential during the SRAM operation and increasing a threshold voltage Vth of each of the load FETs Qp 1  and Qp 2  and the drive FTEs Qd 1  and Qd 2 . 
     &lt;&lt;Main Effects of Second Embodiment&gt;&gt; 
     As described above, the memory cell  3 A of the semiconductor device  1 A according to the second embodiment includes the flip-flop circuit  5 , the four transfer FETs Qt 1 , Qt 2 , Qt 3 , and Qt 4 , and the two drive FETs Qd 3  and Qd 4 , and further includes the two resistance elements  6 A and  6 B. Then, each of the two resistance elements  6 A and  6 B has a resistance value of 1 MΩ or more, which is necessary in a case where a bit line as a summation line is charged with product-sum charge for multiple bits (for example, 1024), during the product-sum calculation process, and is disposed within an occupied area of the memory cell  3 A. Therefore, according to the semiconductor device  1 A of the first embodiment, similarly to the semiconductor device  1  of the first embodiment described above, it is possible to perform a product-sum calculation with high power efficiency while maintaining a small area of the memory cell  3 A. 
     Third Embodiment 
     In a third embodiment, an SRAM-type memory cell including nine field effect transistors and two resistance elements will be described. 
     &lt;&lt;Configuration of Memory Cell Array Unit&gt;&gt; 
     The semiconductor device  1 B according to the third embodiment includes a memory cell array unit  2 B illustrated in  FIG.  7   . As illustrated in  FIG.  7   , in the memory cell array unit  2 B, a plurality of memory cells  3 B is arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. Furthermore, in the memory cell array unit  2 B, a word line WL and an axon line AL extending in the X direction are arranged for each of memory cells  3 B arranged in the Y direction. Furthermore, in the memory cell array unit  2 B, bit line bars BL 2  (BL-) extending in the Y direction are arranged for the memory cells  3 B arranged in the X direction. In the memory cell array unit  2 B, complementary dendrite lines (a dendrite line DL 1  and a dendrite line bar (dendrite line-) DL 2 ) extending in the Y direction are arranged for each of the memory cells  3 B arranged in the X direction. Then, each memory cell  3 B of the plurality of memory cells  3 B is disposed at an intersection between the corresponding word line WL, the complementary bit lines (BL 1  and BL 2 ), and the dendrite line DL 2 . 
     In the memory cell array unit  2 B, the bit line BL 1  of the second embodiment described above is eliminated, and the dendrite line DL 1  is used as a bit line when writing data to the memory cell  3 B. 
     Here, during a product-sum calculation process (inference in a neural network), the memory cell array unit  2 B functions as a product-sum calculation circuit, the axon line AL functions as an axon, and the dendrite line DL 1  and the dendrite line bar DL 2  function as a dendrite and a dendrite bar (dendrite-). On the other hand, when data is written to the memory cell  3 B, the dendrite line DL 1  functions as a bit line. 
     &lt;&lt;Configuration of Memory Cell&gt;&gt; 
     As illustrated in  FIG.  8   , each memory cell  3 B of the plurality of memory cells  3 B includes a flip-flop circuit  5 , a transfer FET Qt 2  as a first transfer field effect transistor, two transfer FETs Qt 3  and Qt 4  as second transfer field effect transistors, two drive FETs Qd 3  and Qd 4  as second drive field effect transistors, and two resistance elements  6 A and  6 B. The memory cell  3 B has a configuration basically similar to that of the memory cell  3 A of the second embodiment described above, and is different in that one transfer FET Qt 1  is eliminated and the gate electrode of each of the two transfer FETs Qt 3  and Qt 4  is electrically connected to the axon line AL. Other configurations are similar to those of the memory cell  3 A of the second embodiment described above. However, similarly to the second embodiment, the transfer FET Qt 2  may be added. 
     The two resistance elements  6 A and  6 B of the third embodiment also have an MIM structure similarly to the resistance elements  6 A and  6 B of the first embodiment described above, can obtain a desired resistance value with a small area, and are arranged within an occupied area of the memory cell. Then, a resistance value of each of the two resistance elements  6 A and  6 B is preferably larger than a channel resistance value of the transfer FETs Qt 3  and Qt 4 , and more preferably 1 MΩ or more. 
     &lt;Write Operation and Product-Sum Calculation&gt; 
     Next, an operation of writing data to the memory cell  3 B and a product-sum calculation will be described. 
     As the write operation of data to the memory cell  3 B, by applying the Vcc potential (for example, 1 V) to the word line WL to turn on the transfer FET Qt 2  and setting the bit line bar BL 2  to the Vss potential, the output portion (storage node portion)  4   a   2  of one inverter circuit  4   a  is set to the Vcc potential, the output portion (storage node portion)  4   b   2  of the other inverter circuit  4   b  is set to the Vss potential. Even if the word line WL is set to the Vss potential, the flip-flop circuit  5  including the two inverter circuits  4   a  and  4   b  is stabilized. By setting the bit line bar BL 2  to the Vcc potential, the output portion (storage node portion)  4   a   2  of one inverter circuit  4   a  is set to the Vss potential, the output portion (storage node portion)  4   b   2  of the other inverter circuit  4   b  is set to the Vcc potential. Even if the word line WL is set to the Vss potential, the flip-flop circuit  5  including the two inverter circuits  4   a  and  4   b  is stabilized. 
     On the other hand, during a product-sum calculation (inference) using the memory cell array unit  2 B as a product-sum calculation circuit, the dendrite line DL 1  and the dendrite line bar DL 2  are precharged to the Vcc potential (for example, 1 V) in a state in which the flip-flop circuit  5  of the memory cell  3 B stores data. Subsequently, a signal (for example, a pulse voltage) is input sequentially to the axon line AL as an axon or to the plurality of axon lines AL. When the signal reaches the Vcc potential, the two transfer FETs Qt 3  and Qt 4  are turned on, and the other drive FET Qd 4  having the gate electrode  16   d  connected to the output portion (storage node portion)  4   a   2  of the one inverter circuit  4   a  is turned on. Therefore, the charge of the dendrite line bar DL 2  is released toward the Vss potential, and the potential decreases. On the other hand, since one drive FET Qd 3  having the gate electrode  16   d  connected to the output portion  4   b   2  of the other inverter circuit  4   b  is in an OFF state, the charge of the dendrite line DL 1  is not released, and the potential does not change. 
     Here, the potential of the dendrite line bar DL 2  (dendrite line-) changes with the CR time constant of the resistance value R of the resistance element  6 B and the parasitic capacitance C parasitic on the dendrite line bar DL 2 . The resistance elements  6 A and  6 B are connected to the drive FETs Qd 3  and Qd 4  for product-sum calculation, and thus do not affect writing of data to the memory cell  3 B. Therefore, by outputting or AD-converting a potential difference between the dendrite line DL 1  and the dendrite line bar DL 2  (dendrite line-) in response to the CR time constant, the sum-product calculation with high power efficiency can be performed. 
     In the memory cell  3 B of the third embodiment, since the word line WL is in an OFF state in which the potential is not supplied even in an ON state in which the Vcc potential is supplied to the axon line AL, the transfer FET Qt 2  of the memory cell can be turned off even during the product-sum calculation, and the low power consumption and the stabilization of the memory operation can be achieved. 
     Note that the input potential to the word line WL, that is, the axon at the time of the sum-product calculation can be freely set separately from the Vcc potential or a write potential applied to the word WL at the time of writing data to the memory cell  3 A. Writing of data into the flip-flop circuit  5  of the memory cell  3 A is usually performed at a high speed through an SRAM operation. By reducing the Vcc potential during the SRAM operation and increasing the threshold voltage Vth of each of the transfer FETs Qp 1  and Qp 2  and the drive FTEs Qd 1  and Qd 2 , the current consumption can be reduced. 
     &lt;&lt;Main Effects of Third Embodiment&gt;&gt; 
     As described above, the memory cell  3 B of the semiconductor device  1 B according to the third embodiment includes the flip-flop circuit  5 , the three transfer FETs Qt 2 , Qt 3 , and Qt 4 , the two drive FETs Qd 3  and Qd 4 , and further includes the two resistance elements  6 A and  6 B. Then, each of the two resistance elements  6 A and  6 B has a resistance value of 1 MΩ or more, which is necessary in a case where a bit line as a summation line is charged with product-sum charge for multiple bits (for example, 1024), during a product-sum calculation process, and is disposed within an occupied area of the memory cell  3 B. Therefore, also in the semiconductor device  1 B according to the third embodiment, similarly to the semiconductor device  1  according to the first embodiment described above, it is possible to perform a product-sum calculation with high power efficiency while maintaining a small area of the memory cell  3 B. 
     Fourth Embodiment 
     In a fourth embodiment, an SRAM-type memory cell including six field effect transistors and four tunnel field effect transistors will be described. 
     &lt;&lt;Configuration of Memory Cell Array Unit&gt;&gt; 
     A semiconductor device  1 C according to the second embodiment includes a memory cell array unit  2 C illustrated in  FIG.  9   . As illustrated in  FIG.  9   , in the memory cell array unit  2 C, a plurality of memory cells  3 C is arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. Furthermore, in the memory cell array unit  2 A, similarly to the memory cell array unit  2 A of the second embodiment described above, word lines WL extending in the X direction are arranged for each of memory cells  3 C arranged in the Y direction, complementary bit lines (a bit line BL 1  and a bit line bar BL 2  (BL 2 -)) extending in the Y direction are arranged for each of the memory cells  3 C arranged in the X direction, and complementary dendrite lines (dendrite line DL 1  and dendrite line bar (dendrite line-) DL 2 ) extending in the Y direction are arranged for each of the memory cells  3 C arranged in the X direction. Then, each memory cell  3 B of the plurality of memory cells  3 B is disposed at an intersection between the corresponding word line WL and the complementary bit lines (BL 1  and BL 2 ) and complementary dendrite lines (DL 1  and DL 2 ). 
     Here, during a product-sum calculation process (inference in the neural network), the memory cell array unit  2 C functions as a product-sum calculation circuit, the axon line AL illustrated in  FIG.  10    functions as an axon, and the dendrite line DL 1  and the dendrite line bar DL 2  function as a dendrite and a dendrite bar (dendrite-). 
     &lt;&lt;Configuration of Memory Cell&gt;&gt; 
     As illustrated in  FIG.  10   , each memory cell  3 C of the plurality of memory cells  3 C includes a flip-flop circuit  5 , two transfer FETs Qt 1  and Qt 2  as first transfer field effect transistors, two transfer tunnel FETs Qt 5  and Qt 6  as second transfer tunnel field effect transistors, and two drive tunnel FETs Qd 5  and Qd 6  as second drive tunnel field effect transistors. The memory cell  3 C has a configuration basically similar to that of the memory cell  3 A of the second embodiment described above, and includes drive tunnel FETs Qd 5  and Qd 6  and transfer tunnel FETs Qt 5  and Qt 6  instead of the resistance elements  6 A and  6 B, the drive FTEs Qd 3  and Qd 4 , and the transfer FETs Qt 3  and Qt 4  of the second embodiment described above. 
     The two drive tunnel FETs Q 5  and Qd 6  each have a gate electrode (control electrode) and a pair of n-type first main electrode region and p-type second main electrode region functioning as a source region and a drain region, and electrical conduction between the n-type first main electrode region and the p-type main electrode separation region is controlled by a gate signal input to the gate electrode. 
     As illustrated in  FIG.  10   , the gate electrode of one drive tunnel FET Q 5  of the two drive tunnel FETs Qd 5  and Qd 6  is electrically connected to the gate electrode of each of the load FET Qp 1  and the drive FET Qd 5  configuring one inverter circuit  4   a . That is, the gate electrode of the one drive tunnel FET Qd 5  is electrically connected to the input portion  4   a   1  of the one inverter circuit  4   a.    
     As illustrated in  FIG.  10   , in the other drive tunnel FET Qd 6  of the two drive tunnel FETs Qd 5  and Qd 6 , the gate electrode is electrically connected to the gate electrode of each of the load FET Qp 2  and the drive FET Qd 2  configuring the other inverter circuit  4   b . That is, the gate electrode of the other drive tunnel FET Qd 6  is electrically connected to the input portion  4   b   1  of the other inverter circuit  4   b.    
     As illustrated in  FIG.  10   , the n-type first main electrode region of each of the two drive tunnel FETs Qd 5  and Qd 6  is electrically connected to the axon line AL. 
     As illustrated in  FIG.  10   , in one transfer FET Qt 5  of the two transfer tunnel FETs Qt 5  and Qt 6 , the gate electrode is electrically connected to the word line WL, and the p-type second main electrode region is electrically connected to the p-type second main electrode region of one drive tunnel FET Qd 5 . Then, in the one transfer tunnel FET Qt 5 , the n-type first main electrode region is electrically connected to the dendrite line DL 1 . 
     As illustrated in  FIG.  10   , in the other transfer tunnel FET Qt 6  of the two transfer tunnel FETs Qt 5  and Qt 6 , the gate electrode is electrically connected to the word line WL, and the p-type second main electrode region is electrically connected to the p-type second main electrode region of the other drive tunnel FET Qd 6 . Then, in the other transfer tunnel FET Qt 6 , the n-type first main electrode region is electrically connected to the dendrite line bar (dendrite line) DL 2 . 
     As illustrated in  FIG.  10   , in the two drive tunnel FETs Qd 5  and Qd 6  and the two transfer tunnel FETs Qt 5  and Qt 6 , a pair of main electrode regions functioning as a source region and a drain region includes the n-type first main electrode region and the p-type second main electrode region. Therefore, a pn-type parasitic diode PD 1  is formed in an equivalent circuit on a conductive path connecting the one transfer tunnel FET Qt 5  to the dendrite line DL 1 . Furthermore, a pn-type parasitic diode PD 2  is formed in an equivalent circuit on a conductive path connecting the other transfer tunnel FET Qt 6  to the dendrite line bar DL 2 . 
     &lt;&lt;Write Operation and Product-Sum Calculation&gt;&gt; 
     Next, an operation of writing data to the memory cell  3 C and a product-sum calculation will be described. 
     As a write operation to the memory cell  3 C, by applying the Vcc potential (for example, 1 V) to the word line WL to turn on the two transfer FETs Qt 1  and Qt 2  and setting the bit line BL 1  to the Vcc potential and the bit line bar BL 2  to the Vss potential, the output portion (storage node portion)  4   a   2  of one inverter circuit  4   a  is set to the Vcc potential and the output portion (storage node portion)  4   b   2  of the other inverter circuit  4   b  is set to the Vss potential. Even if the word line WL is set to the Vss potential, the flip-flop circuit  5  including the two inverter circuits  4   a  and  4   b  is stabilized. 
     On the other hand, at the time of a product-sum calculation (inference) using the memory cell array unit  2 C as a product-sum calculation circuit, the dendrite line DL 1  and the dendrite line bar DL 2  are precharged to the Vss potential (for example, 0 V) in a state in which the flip-flop circuit  5  of the memory cell  3 C stores data. Subsequently, a signal (for example, a pulse voltage) is input to the axon line AL. When the signal reaches the Vcc potential, since the other drive tunnel FET Qd 6  having the gate electrode connected to the output portion (storage node portion)  4   a   2  of the one inverter circuit  4   a  is in an ON state, the dendrite line bar DL 2  is charged by being supplied with electric charge from the axon line AL. In this case, even when the word line WL has the Vss potential and the other transfer tunnel FET Qt 6  is in an OFF state, since the source region (second main electrode region) side of the transfer tunnel FET Qt 6  has a high potential, the parasitic diode PD 2  operates in the forward direction, and the charging of the dendrite line bar DL 2  is not inhibited. 
     On the other hand, since one drive tunnel FET Qd 5  electrically connected to the output portion (storage node portion)  4   b   2  of the other inverter circuit  4   b  is in an OFF state, the dendrite line DL 1  is not charged with the electric charge from the axon line AL and the potential is maintained. 
     The potential of the dendrite line bar DL 2  changes with the CR time constant of the channel resistance value R of each of the drive tunnel FET Qd 6  and the transfer tunnel FET Qt 6  and the parasitic capacitance C of the dendrite line bar DL 2 . The transfer FET connected to the storage node portion of the flip-flop circuit is a normal MOSFET, and thus does not affect writing of data to the memory cell. Furthermore, even if the signal of the axon line AL becomes the Vss potential (ground potential) and the dendrite line bar DL 2  has a high potential, the transfer tunnel FET Qt 6  is in an OFF state, and the parasitic diode PD 2  is in an opposite direction, so that the electric charge does not flow back from the dendrite line bar DL 2  to the axon line AL. Therefore, by outputting or AD-converting a potential difference between the dendrite line DL 1  and the dendrite line bar DL 2  (dendrite line-) in response to the CR time constant, the sum-product calculation with high power efficiency can be performed. 
     The two drive tunnel FETs Q 5  and Qd 6  and the two transfer tunnel FETs Qt 5  and Qt 6  can increase the channel resistance value with a small area compared with a normal MOSFET. That is, during the product-sum calculation process, it is possible to obtain a resistance value of 1 MΩ or more, which is necessary in a case where a bit line as a summation line is charged with product-sum charge for multiple bits (for example, 1024) with a small area compared with the MOSFET. Therefore, also in the semiconductor device  1 A according to the fourth embodiment, similarly to the semiconductor device  1  according to the first embodiment described above, it is possible to perform a product-sum calculation with high power efficiency while maintaining a small area of the memory cell  3 C. 
     Note that a channel resistance value of the two drive tunnel FETs Q 5  and Qd 6  and the two transfer tunnel FETs Qt 5  and Qt 6  is preferably larger than a channel resistance value of the transfer FETs Qt 3  and Qt 4 , and more preferably 1 MΩ or more. 
     MODIFICATION EXAMPLES 
     First Modification Example 
       FIG.  11    is an equivalent circuit diagram of a memory cell according to a first modification example of the fourth embodiment. 
     As illustrated in  FIG.  11   , a memory cell  3 C 1  basically has a configuration similar to that of the memory cell of the fourth embodiment described above, and has a configuration in which the two transfer tunnel FETs Qt 5  and Qt 6  illustrated in  FIG.  10    are omitted compared with the memory cell of the fourth embodiment. 
     That is, as illustrated in  FIG.  11   , the memory cell  3 C 1  of the first modification example includes the flip-flop circuit  5 , the two transfer FETs Qt 1  and Qt 2 , and the two drive tunnel FETs Q 5  and Qd 6 , and does not include the two transfer tunnel FETs Qt 5  and Qt 6  illustrated in  FIG.  10   . Therefore, the p-type second main electrode region of one drive tunnel FET Q 5  is electrically connected to the dendrite line DL 1  without passing through the transfer tunnel FET, and the p-type second main electrode region of the other drive tunnel FET Qd 6  is electrically connected to the dendrite line bar DL 2  without passing through the transfer tunnel FET. 
     Also in the memory cell  3 C 1  of the first modification example configured as described above, effects similar to those of the above-described fourth embodiment can be achieved. 
     Second Modification Example 
       FIG.  12    is an equivalent circuit diagram of a memory cell according to a second modification example of the fourth embodiment. 
     As illustrated in  FIG.  12   , a memory cell  3 C 2  basically has a configuration similar to that of the memory cell  3 C of the above-described fourth embodiment, and has a configuration in which the drive tunnel FET Qd 6  and the transfer tunnel FET Qt 6  on the other inverter circuit  4   b  side illustrated in  FIG.  10    are omitted compared with the memory cell  3 C of the fourth embodiment. 
     That is, as illustrated in  FIG.  12   , the memory cell  3 C 2  of the second modification example includes the flip-flop circuit  5 , the two transfer FETs Qt 1  and Qt 2 , and further includes one drive tunnel FET Q 5  and one transfer tunnel FET Qt 6 . Then, in the memory cell array unit, the dendrite line bar DL 2  illustrated in  FIG.  10    is omitted. 
     Also in the memory cell  3 C 2  of the second modification example configured as described above, effects similar to those of the above-described fourth embodiment can be achieved. 
     Note that the present technology may have the following configurations. 
     (1) 
     A semiconductor device including: 
     a memory cell array in which a plurality of memory cells is arranged in a matrix, in which 
     each memory cell of the plurality of memory cells includes 
     a flip-flop circuit including two inverter circuits in each of which a load field effect transistor and a drive field effect transistor are connected in series, input portions and output portions of the two inverter circuits being cross-joined to each other, 
     two transfer field effect transistors each having a gate electrode connected to a word line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the output portions of the two inverter circuits, and 
     two resistance elements of which one end sides are respectively connected to the second main electrode regions of the two transfer field effect transistors and other end sides are respectively connected to a bit line and a bit line bar. 
     (2) 
     The semiconductor device according to (1), in which a resistance value of the resistance elements is greater than a channel resistance value of the transfer field effect transistors. 
     (3) 
     The semiconductor device according to (1), in which a resistance value of the resistance elements is 1 MΩ or more. 
     (4) 
     The semiconductor device according to (1) or (2), in which when a product-sum calculation is performed, the word line functions as an axon, the bit line functions as a dendrite, and the bit line bar functions as a dendrite bar. 
     (5) 
     A semiconductor device including: 
     a memory cell array in which a plurality of memory cells is arranged in a matrix, in which 
     each memory cell of the plurality of memory cells includes 
     a flip-flop circuit including two inverter circuits in each of which a load field effect transistor and a first drive field effect transistor are connected in series, input portions and output portions of the two inverter circuits being cross-joined to each other, 
     two first transfer field effect transistors each having a gate electrode connected to a word line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the output portions of the two inverter circuits, and the second main electrode regions being respectively connected to a bit line and a bit line bar, 
     two second drive field effect transistors each having a gate electrode and a pair of first and second main electrode regions, the gate electrodes being respectively connected to the input portions of the two inverter circuits, and the first main electrode regions being connected to each other, 
     two second transfer field effect transistors each having a gate electrode connected to the word line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the second main electrode regions of the two second drive field effect transistors, and 
     two resistance elements of which one end sides are respectively connected to the second main electrode regions of the two second transfer field effect transistors and other end sides are respectively connected to a dendrite line and a dendrite line bar. 
     (6) 
     The semiconductor device according to (5), in which a resistance value of the resistance elements is greater than a channel resistance value of the transfer field effect transistors. 
     (7) 
     The semiconductor device according to (5), in which a resistance value of the resistance elements is 1 MΩ or more. 
     (8) 
     The semiconductor device according to any one of (5) to (7), in which when a product-sum calculation is performed, the word line functions as an axon. 
     (9) 
     A semiconductor device including: 
     a memory cell array in which a plurality of memory cells is arranged in a matrix, in which 
     each memory cell of the plurality of memory cells includes 
     a flip-flop circuit including two inverter circuits in each of which a load field effect transistor and a first drive field effect transistor are connected in series, input portions and output portions of the two inverter circuits being cross-joined to each other, 
     a first transfer field effect transistor having a gate electrode connected to a word line, and a pair of first and second main electrode regions, the first main electrode region being connected to the output portion of the other inverter circuit of the two inverter circuits, and the second main electrode region being connected to a bit line bar, 
     two second drive field effect transistors each having a gate electrode and a pair of first and second main electrode regions, the gate electrodes being respectively connected to the input portions of the two inverter circuits, and the first main electrode regions being connected to each other, 
     two second transfer field effect transistors each having a gate electrode connected to an axon line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the second main electrode regions of the two second drive field effect transistors, and 
     two resistance elements of which one end sides are respectively connected to the second main electrode regions of the two second transfer field effect transistors and other end sides are respectively connected to a dendrite line and a dendrite line bar. 
     (10) 
     The semiconductor device according to (9), in which a resistance value of the resistance elements is greater than a channel resistance value of the transfer field effect transistors. 
     (11) 
     The semiconductor device according to (9), in which a resistance value of the resistance elements is 1 MΩ or more. 
     (12) 
     A semiconductor device including: 
     a memory cell array in which a plurality of memory cells is arranged in a matrix, in which 
     each memory cell of the plurality of memory cells includes 
     a flip-flop circuit including two inverter circuits in which a load field effect transistor and a first drive field effect transistor are connected in series, input portions and output portions of the two inverter circuits being cross-joined to each other, 
     two first transfer field effect transistors each having a gate electrode connected to a word line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the output portions of the two inverter circuits, and the second main electrode regions being respectively connected to a bit line and a bit line bar, 
     two second drive tunnel field effect transistors each having a gate electrode and a pair of n-type first main electrode region and p-type second main electrode region, the gate electrodes being respectively connected to the input portions of the two inverter circuits, and the n-type first main electrode region being connected to an axon line, and 
     two second transfer tunnel field effect transistors each having a gate electrode connected to the word line, and a pair of n-type first main electrode region and p-type second main electrode region, the p-type second main electrode regions being respectively connected to the p-type second main electrode regions of the two second drive tunnel field effect transistors, and the n-type first main electrode regions being respectively connected to a dendrite line and a dendrite line bar. 
     The scope of the present technology is not limited to the illustrated and described exemplary embodiments, but also includes all embodiments that provide equivalent effects to those for which the present technology is intended. Moreover, the scope of the present technology is not limited to the combinations of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the disclosed respective features. 
     REFERENCE SIGNS LIST 
     
         
           1  Semiconductor device 
           2  Memory cell array unit 
           3  Memory cell 
           4   a ,  4   b  Inverter circuit 
           4   a   1 ,  4   b   1  Input portion 
           4   a   2 ,  4   b   2  Output portion (storage node portion) 
           5  Flip-flop circuit 
           6 A,  6 B Resistance element 
         Qd 1 , Qd 2 , Qd 3 , Qd 4  Drive field effect transistor (pull-down transistor) 
         Qp 1 , Qp 2  Load field effect transistor (pull-up transistor) 
         Qt 1 , Qt 2 , Qt 3 , Qt 4  Transfer field effect transistor (pass gate transistor) 
           10  Semiconductor layer 
           11  Isolation region 
           12   a  n-type well region 
           12   b  p-type well region 
           15  Gate insulating film 
           16   d ,  16   p ,  16   t  Gate electrode 
           17   d   1 ,  17   p   1 ,  17   t   1  First main electrode region 
           17   d   2 ,  17   p   2 ,  17   t   2  Second main electrode region 
           21  Interlayer insulating film 
           22   a ,  22   b ,  22   c ,  22   d ,  22   e  Conductive plug 
           23   a  First electrode 
           23   b  Insulating film 
           23   c  Second electrode 
           24  Interlayer insulating film 
           25   a   1 ,  25   a   2 ,  25   c   1 ,  25   c   2 ,  25   d   1 ,  25   d   2 ,  25   e   1 ,  25   e   2  Relay wiring 
           26  Interlayer insulating film 
           27  Conductive plug 
           28   c   1 ,  28   c   2  Ground wiring 
           28   d  Power supply line 
         AL Axon line 
         BL 1  Bit line 
         BL 2  Bit line bar 
         DL 1  Dendrite line 
         DL 2  Dendrite line bar 
         WL Word line 
         Qd 1 , Qd 2 , Qd 3 , Qd 4  Drive field effect transistor (drive FET) 
         Qp 1 , Qp 2  Load field effect transistor (drive FET) 
         Qt 1 , Qt 2 , Qt 3 , Qt 4  Transfer field effect transistor (transfer FET) 
         Qd 5 , Qd 6  Drive tunnel field effect transistor (drive tunnel FET) 
         Qt 5 , Qt 6  Transfer tunnel field effect transistor (transfer tunnel FET) 
         PD 1 , PD 2  Parasitic diode