Patent Publication Number: US-8996926-B2

Title: DMA integrity checker

Description:
BACKGROUND 
     Direct memory access (DMA) controllers allow certain hardware subsystems within a computing system to access system memory somewhat independent of a central, microprocessor unit. To illustrate general DMA functionality, consider the example of  FIG. 1 , which illustrates a digital system  100  including a microprocessor  102 , memory  104 , DMA controller  106  and input/output block  108 , all of which are operably coupled via a system bus  110 . Without the DMA controller  106 , when the microprocessor  102  is required to transfer large amounts of data in memory  104  or is required to write data to or read data from I/O block  108  or another system peripheral, the microprocessor  102  is typically fully occupied for the entire duration of read or write operations during the transfer. With the DMA controller  106 , however, the microprocessor  102  programs the DMA controller  106  to handle the data transfer and, after programming the DMA controller  106 , the microprocessor  102  can go about other tasks. After being programmed, the DMA controller  106  transfers the data in a somewhat autonomous fashion, and asserts an interrupt request (IRQ) to notify the microprocessor  102  that the data transfer is complete. In this way, the microprocessor  102  can off-load large data transfers to the DMA controller  106  and use its own resources for more suitable tasks. Hence, DMA controllers may be useful any time a microprocessor struggles to efficiently transfer data, where the microprocessor needs to perform useful work while waiting for a relatively slow I/O data transfer, or in other suitable instances. 
     While DMAs can improve the efficiency of data transfers for digital processing systems, DMAs also have the potential to wreak havoc on these systems if there are any bits in memory that have been corrupted and which the DMA acts upon. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a block diagram of a digital system that makes use of a direct memory access (DMA) controller. 
         FIG. 2  shows a block diagram of digital system that makes use a DMA controller having an integrity checker in accordance with some embodiments. 
         FIGS. 3A-3D  collectively illustrates an example where a DMA controller in accordance with some embodiments performs a data transfer with integrity checking. 
     
    
    
     DETAILED DESCRIPTION 
     The description herein is made with reference to the drawings, wherein like reference numerals are generally utilized to refer to like elements throughout, and wherein the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to facilitate understanding. It may be evident, however, to one of ordinary skill in the art, that one or more aspects described herein may be practiced with a lesser degree of these specific details. In other instances, known structures and devices are shown in block diagram form to facilitate understanding. 
     As mentioned above, absent adequate safeguards, DMA controllers can wreak havoc in digital systems if they inadvertently act on corrupted data stored in memory. To remedy this issue and also limit the amount of resources spent by the microprocessor in managing the DMA, the present disclosure provides improved DMA integrity checking techniques. In these integrity checking techniques, a DMA controller can be programmed with a sequence of transaction control sets (e.g., which point to descriptors and/or links in memory) along with corresponding expected error detection coding information. When transferring data as specified by a first transaction control set, the DMA controller incrementally updates an actual error detection code with each and every move transaction included during execution of the first TCS. If the DMA is to autonomously continue after completion of the move sequence specified by the first TCS, a second TCS is needed, and it is at the point of loading the second TCS that the actual error detection code (which had been accumulated over previous transactions) is checked against an expected error detection code contained in the second TCS. So long as the actual error detection code is the same as the expected error detection code, the DMA controller can continue with processing of the second TCS transfer without flagging an interrupt and without needing management from the microprocessor  202 . Hence, the DMA integrity checking techniques disclosed herein check that a previously executed TCS (e.g., first TCS) has left the DMA system in an expected state after execution of the previous TCS (so as to detect any faults during execution). By providing this improved integrity checking, the DMA controller is more reliable and can be trusted to operate more autonomously, thereby freeing up the microprocessor for other tasks. 
     It will be appreciated that “error detection code” as referred to herein can be used to detect a data error present in bits, words, or other sizes of data. Error detection codes can include, but are not limited to cyclic redundancy checks, parity bit(s), and hash values, among others. In some instances, an error detection code can be implemented as an error correction code, wherein the information in the error correction code not only detects whether an error is present but also helps to correct the error. 
       FIG. 2  shows one example of a digital system  200  that makes use of a DMA controller in accordance with some embodiments. The system  200  includes a microprocessor  202 , memory  204 , DMA controller  206 , and input/output module  208 , all of which are operably coupled via a system bus  210 . An interrupt controller  212 , which receives interrupts from multiple respective peripherals and prioritizes them, may also be present in some implementations. Alternatively, the DMA may include its own trigger unit and arbiter, rather than using an interrupt as a trigger. 
     The DMA controller  206  includes an integrity checking module  214 , bus controller  216 , and transaction control set (TCS) registers  218 . As will be appreciated in greater detail herein, a DMA operation can start when the microprocessor  202  load TCS registers  218  with a first transaction control set (TCS). This first TCS specifies a source address, destination address, size, and control information for one or more blocks of data to be transferred within memory  204 . 
     After the TCS has been written to the TCS registers  218 , the bus controller  216  then carries out the data transfer specified by the first TCS, for example, by transferring one or more source data blocks (e.g., src data block  232 ) to one or more corresponding destination address blocks (e.g., dest. data block  236 ). As each word is transferred in memory  204 , the integrity checking module  214  calculates an actual error detection code. This actual error detection code can take the form of an actual address error detection code (stored in actual address EDC register  229 ), which is based on the memory addresses actually accessed by the DMA controller while executing the first transaction control set. The actual error detection code can also take the form of an actual data error detection code (stored in actual data EDC register  231 ), which is based on the data actually transferred by the DMA controller  206  while executing the first transaction control set. 
     After data of the first TCS has been transferred, logic  227  can then compare these actual error detection code(s) stored in  229 / 231  to corresponding expected error detection code(s) stored in  228 / 230 , respectively. The expected error detection code(s) stored in  228 / 230  are often read from a second TCS by the DMA controller. For example, the second TCS can follow the first TCS in the sequence of transaction control sets. If the actual error detection code(s) stored in  229 / 231  is different from the expected error detection code(s) in  228 / 230 , the DMA controller  206  halts data transfers and flags an error (e.g., an interrupt IRQ) to limit damage to data stored in memory  204 . If no error is detected, the DMA continues with another data transfer specified by the next TCS in the sequence without flagging an interrupt so the microprocessor  202  can continue with other tasks un-interrupted. Thus, by comparing the actual and expected error codes and putting adequate safeguards in place, the DMA controller helps to ensure data has been moved accurately. 
     It will be appreciated that that actual data error detection codes stored in  231  can be calculated independently of the actual src./dest. address error detection codes stored in  229 . Thus, some implementations may employ only data error detection codes, while other implementations may employ only error detection codes calculated over source and/or destination addresses. Still other implementations can use both data error detection codes and error detection codes calculated over source and destination addresses. 
     In some applications, such as shown in  FIG. 2  for example, source data is “scattered” over a number of non-contiguous blocks across physical memory  204 . For example in  FIG. 2 , a first data block  232  having a first data size starts at a first base address (src addr  1 ), wherein consecutive bytes of the first data block are stored at consecutively incremented addresses from the first base address until all of the data is stored up to the first data size. A second data block  234  having a second data size can be stored starting at a second base address (src addr  2 ), which is non-contiguous with regards to the addresses of the first data block  232  in physical memory  204 . Any number of other data blocks can also be stored in this fashion. Destination addresses, to which the source data blocks are to be moved or copied, can also be similarly scattered across physical memory  204 . For example, in  FIG. 2 , first destination block  236  is where first source data block  232  is to be moved, and second destination block  238  is where second source data block  234  is to be moved. 
     With reference to  FIG. 2 , there is also a possibility to configure the DMA controller to skip addresses or even not modify the addresses in a source and/or destination block ( 232 ,  236 ). For example, the DMA can be set to read a single byte at a time from constant source address (such as a serial channel receive register) and write the data to a destination buffer on a 8 bit, 16 bit, 32 bit or 64 bit increment of the destination address. This way, the DMA can expand, contract, and/or interleave data in buffers as the DMA moves it around to make it more suitable for further processing (for instance for FFT filtering that needs specific data alignments). 
     An example of DMA controller functionality is now described in more detail with regards to  FIGS. 3A-3D . Like the previously described systems, the system  300  in  FIGS. 3A-3D  includes a microprocessor  302 , memory  304 , and DMA controller  306 , which are operably coupled by a system bus. 
       FIG. 3A  provides an illustrative example where the processor  302  desires to transfer 3 kilobytes of source data, which is scattered across three non-contiguous memory blocks ( 308 ,  310 ,  312 ), to three non-contiguous destination blocks ( 314 ,  316 ,  318 ). Although this example transfers three blocks of non-contiguous source data, each of which is one kilobyte in size, to three equally sized destination addresses, it will be appreciated that any number of blocks of data and data block of any size can be used. The blocks can have the same size, or can be different sizes. Further, the source data and/or destination data can be arranged in a continuous block in some implementations, rather than being non-contiguous as illustrated. 
     To effectuate this desired data transfer, microprocessor  302  builds a linked list of link structures ( 320 ,  322 ,  324 ) in memory  304 . The link structures  320 ,  322 ,  324  include DMA control information and pointers to the respective data blocks spread over memory. For example, link structure  1  ( 320 ) has a source address field  326  that points to base address of first source data block  308 , and also has a destination address field  328  that points to base address of first destination block  314 . Link structure  1   320  also includes a control field  330  that specifies the size of the source data block  308 . The control field  330  also specifies link structure  1  is a link that is followed by another link (here link structure  2   322 ), while link field  332  provides a base address/pointer for this other link (here, base address of link structure  2   322 ). Because the linked structures in this example act as transaction control sets, the link structures, when viewed as a collective, can “gather” source data scattered across non-contiguous memory locations and/or can “scatter” data across non-contiguous destination addresses in one continuous DMA operation. 
     Referring to  FIG. 3B , to effectuate the desired data transfer, the processor  302  writes the first transaction control set  320  to the TCS registers  218  in the DMA controller  306  (see line  334 ). In particular, the processor  302  writes a base address of the first data block  308  to source register  220 , writes a destination address of a base address of the first destination block  314  to destination register  222 , and writes a size of the first data block  308  to count register  224 . The microprocessor also writes control bit(s) to control register  226  to indicate whether the TCS 1   320  represents a link that is followed by another transaction control set. 
     The DMA controller, acting through its bus controller  216 , then moves or copies first source data block  308  to first destination block  314  (see line  336 ). Typically, the DMA moves the data on a word by word basis, incrementing its count value  224  by one word and incrementing its source and destination address registers  220 ,  222  by one word as each word is transferred, until the specified data size has been transferred. The DMA can compute an actual address error detection code for the base source and base destination addresses, and stores this actual address EDC in actual address EDC register  229 . The DMA can also compute an actual data EDC over the transferred data, for example by updating the actual data EDC  231  on a word by word basis, or by calculating the EDC code on larger chunks of the data. 
     In  FIG. 3C , the DMA grabs the second TCS 2  link  322 , whose base address was contained in link field  332  of TSC 1   320 , without requiring guidance from microprocessor  302 . Because the second link structure  322  includes expected error checking codes pertaining to the first link structure  320 , upon grabbing the second link structure  322 , the DMA compares the expected error checking codes with the actual error checking codes stored in  229 / 231  (which were based on processing of the first link structure  320 ). If the DMA detects an error in EDCs, it can flag an interrupt, but otherwise can continue with the data transfer. Assuming no errors are detected, the logic  227  in DMA controller decodes the remaining fields in the TCS 2  link  322 , and based on these fields, transfers 1 Kb of data from the second source data block  310  to the second destination block  316  (see line  338 ). Logic  227  then updates the actual address EDC using Source/Destination Addresses in TCS 2   322  and/or over transferred data for TCS 2   322 , and updates  229 / 231 . This actual EDC is a “running total” with the actual EDC from TCS 1  calculated in  FIG. 3B , and thus the actual EDC values in  229 / 231  in  FIG. 3C  depend on addresses and/or data transferred in  FIG. 3B . 
     In  FIG. 3D , the DMA grabs the third TCS 3  link  324 , whose base address was contained in link field  340  of TSC 2   322 , without requiring guidance from microprocessor  302 . Because the third link structure  324  includes expected error checking codes pertaining to the second link structure  322 , upon grabbing the third link structure  324 , the DMA compares the expected error checking codes with the actual error checking codes stored in  229 / 231  (which were based on processing of the second link structure  322 ). Logic  227  decodes the fields in the TCS 3  link  324 , and based on these fields, transfers 1 Kb of data from Src. 3   312  to Dest. 3   318  (see line  342 ). Logic  227  then computes actual EDC for SRC/Destination Address in TCS 3   322  and/or over transferred data for TCS 3 . This EDC is a “running total” with the EDC from TCS 2  calculated in  FIG. 3C  (and EDC from TCS 1  calculated in  FIG. 3B  for that matter). The control field  344  in TCS 3  indicates TCS 3   324  is the end of the chain of links, so DMA can set its status registers accordingly to be polled by the microprocessor at a suitable time. If errors are detected, the DMA can flag an interrupt. While a plurality of different embodiments has been described with reference to the figures, the present invention is not limited to these embodiments, as a plurality of modifications is possible without departing from the scope of the present invention. Some examples for such modifications will be described below. In some implementations, the data blocks are scattered over physical memory due to mapping between virtual memory addresses used by applications and physical memory addresses used by the operating system. Alternatively, the data blocks can be scattered over static, predetermined positions in memory (e.g., in flash or ROM used to store boot code). Further, although some embodiments described above are based on linked lists, the description is not limited in any way to linked lists. Other stack based or circular arrangements of TCS descriptors in memory are also possible. 
     Thus, it will be appreciated that some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a transaction control set that describes a data transfer to be processed as a linked list by the DMA. A bus controller reads and writes to memory to accomplish the data transfer described in the transaction control set. An integrity checker determines an actual error detection code based on information in successive links of the linked list and selectively flags an error based on whether the actual error detection code is the same as an expected error detection code. 
     Another embodiment relates to a system. The system includes a memory to store a linked list data structure describing data to be transferred. A microcontroller is coupled to the memory via a bus structure, and is configured to access the linked list data structure and determine respective expected error detection codes for successive links in the linked list data structure. A direct memory access (DMA) controller actually transfers data in the memory according to the linked list data structure via the bus structure. The DMA controller includes an integrity checker to selectively flag an error based on whether the respective expected error detection codes are the same as actual error detection codes determined by the DMA when the DMA actually transfers the data according to the linked list data structure. 
     Still another embodiment relates to a method. In this method, a first transaction control set is stored in memory starting at a first base address. The first transaction control set includes a first source address of first source data to be transferred and a first destination address where the first source data is to be transferred. A second transaction control set, which is stored in memory starting at a second base address that is non-contiguous in memory with the first transaction control set, is also accessed. The second transaction control set includes a second source address of second source data to be transferred and a second destination address where the second source data is to be transferred. A first error detection code is determined based on the first transaction control set or the first source data. A second error detection code is determined based on the second transaction control set or the second source data. The second error detection depends on the first transaction control set or the first source data. 
     It is to be understood that in the description of embodiments contained herein any direct connection or coupling between functional blocks, devices, components, circuit elements or other physical or functional units shown in the drawings or described herein could also be implemented by an indirect connection or coupling, i.e., a connection or coupling comprising one or more intervening elements. Furthermore, it should be appreciated that functional blocks or units shown in the drawings may be implemented as separate circuits in some embodiments, but may also be fully or partially implemented in a common circuit or common integrated circuit in other embodiments, or in some cases may also be implemented jointly by programming a processor accordingly. 
     It should be noted that the drawings are provided to give an illustration of some aspects and features of embodiments of the present invention and are to be regarded as schematic only. In particular, the elements shown in the drawings are not necessarily to scale with each other, and the placement of various elements in the drawings is chosen to provide a clear understanding of the respective embodiment and is not to be construed as necessarily being a representation of the actual relative location of the various components and elements shown. The features of the various embodiments described herein may be combined with each other. On the other hand, describing an embodiment with a plurality of features is not to be construed as indicating that all those features are necessary for practicing the present invention, as other embodiments may comprise less features and/or alternative features.