Patent Publication Number: US-10326584-B2

Title: Carrier synchronization device

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application is a continuation of U.S. application Ser. No. 14/938,356, filed Nov. 11, 2015, which is herein incorporated by reference. 
    
    
     BACKGROUND 
     In a communication carrier system, a baseband signal is modulated with a carrier wave, and information in the baseband signal is extracted from the modulated wave received by the receiver. During the transmission progress, random offsets or noises are introduced to the carrier wave. As a result, the frequency of the carrier wave received by the transmitter and that received by the receiver are different from each other. If the difference between the carrier wave at the transmitter and that at the receiver is too large, such extraction is failed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  is a schematic diagram of a device in accordance with various embodiments of the present disclosure. 
         FIG. 2  is a flow chart of a method illustrating operations of the device in  FIG. 1  in accordance with various embodiments of the present disclosure. 
         FIG. 3  is a schematic diagram of an analog to digital converter in  FIG. 1  in accordance with various embodiments of the present disclosure. 
         FIG. 4A  is a schematic diagram of a digital to time converter in  FIG. 1  in accordance with various embodiments of the present disclosure. 
         FIG. 4B  is a waveform illustrating the first reference signal and the second reference signal in  FIG. 4A  in accordance with various embodiments of the present disclosure. 
         FIG. 5  is a schematic diagram of a phase-locked loop circuit in  FIG. 1  in accordance with various embodiments of the present disclosure. 
         FIG. 6  is a schematic diagram of a device in accordance with various embodiments of the present disclosure. 
         FIG. 7  is a flow chart of a method illustrating operations of the device in  FIG. 6  in accordance with various embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     The terms used in this specification generally have their ordinary meanings in the art and in the specific context where each term is used. The use of examples in this specification, including examples of any terms discussed herein, is illustrative only, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given in this specification. 
     Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     In this document, the term “coupled” may also be termed as “electrically coupled”, and the term “connected” may be termed as “electrically connected”. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other. 
       FIG. 1  is a schematic diagram of a device  100  in accordance with various embodiments of the present disclosure. In some embodiments, the device  100  is implemented in or implemented as a demodulation device. 
     In some embodiments, the device  100  is configured to generate a local oscillating signal LO 1 , and demodulate a modulated signal Y(T) according to the local oscillating signal LO 1 , in order to output an output signal I(T) and an output signal Q(T). In some embodiments, the device  100  is applied to a receiver or a transceiver. In some embodiments, the device  100  is configured to estimate the frequency and phase variations between a transmitter (not shown) and the receiver by using information in the received modulated signal Y(T) to reproduce or recover the carrier signal for the modulated signal Y(T) at the receiver, in order to permit coherent demodulation. In further embodiments, the transceiver is a radio frequency interconnect (RFI) transceiver. 
     As illustratively shown in  FIG. 1 , the device  100  includes a data receiving circuit  120  and an oscillating signal generator  140 . In some embodiments, the device  100  is applied to transceivers employing Binary Phase Shift Keying (BPSK) modulation. 
     In various embodiments, the data receiving circuit  120  operates as a demodulator of the device  100 . The data receiving circuit  120  is configured to output the output signal I(T), the output signal Q(T), and a phase error signal ERR according to the oscillating signal LO 1  and the modulated signal Y(T). In some embodiments, the phase error signal ERR indicates a phase difference between the oscillating signal LO 1  and the modulated signal Y(T). The oscillating signal generator  140  is configured to delay a phase of a reference signal REF 1  according to the phase error signal ERR, in order to generate the oscillating signal LO 1 . In some embodiments, the oscillating signal generator  140  includes an analog to digital converter  142 , a digital to time converter  144 , and a phase-locked loop  146 . An input terminal of the analog to digital converter  142  is electrically coupled to the data receiving circuit  120  to receive the phase error signal ERR. An input terminal of the digital to time converter  144  is electrically coupled to an output terminal of the analog to digital converter  142  to receive a digital signal DOUT. An input terminal of the phase-locked loop  146  is electrically coupled to an output terminal of the digital to time converter  144  to receive a reference signal REF 2 . The analog to digital converter  142  is configured to receive the phase error signal ERR and convert the phase error signal ERR to the digital signal DOUT. The digital to time converter  144  is configured to delay the reference signal REF 1  according to the digital signal DOUT, in order to generate the reference signal REF 2 . The phase-locked loop  146  is configured to generate the oscillating signal LO 1  according to the reference signal REF 2 . 
     In some embodiments, as illustratively shown in  FIG. 1 , the data receiving circuit  120  includes a demodulator  130 , filters  124 A and  124 B, and a mixer  126 . The demodulator  130  is configured to demodulate the modulated signal Y(T) according to the oscillating signal LO 1 . In some embodiments, the demodulator  130  includes mixers  122 A and  122 B, and a phase shifter  128 . A first input terminal of the mixer  122 A and a first input terminal of the mixer  122 B are configured to receive the modulated signal Y(T). A second input terminal of the mixer  122 A is electrically coupled to an output terminal of the phase-locked loop  146  to receive the oscillating signal LO 1 . A second input terminal of the mixer  122 B is electrically coupled to an output terminal of the phase shifter  128  to receive a shifted oscillating signal LO 2 . An input terminal of the filter  124 A is electrically coupled to an output terminal of the mixer  122 A to receive a data signal DS 1 . An input terminal of the filter  124 B is electrically coupled to an output terminal of the mixer  122 B to receive a data signal DS 2 . A first input terminal and a second input terminal of the mixer  126  are electrically coupled to an output terminal of the filter  124 A and an output terminal of the filter  124 B respectively to receive the output signal I(T) and the output signal Q(T). An output terminal of the mixer  126  is electrically coupled to the input terminal of the analog to digital converter  142 . An input terminal of the phase shifter  128  is electrically coupled to the output terminal of the phase-locked loop  146  to receive the oscillating signal LO 1 . 
     The mixer  122 A is configured to demodulate the modulated signal Y(T) according to the oscillating signal LO 1 , in order to generate the data signal DS 1 . The mixer  122 B is configured to demodulate the modulated signal Y(T) according to the shifted oscillating signal LO 2 , in order to generate the data signal DS 2 . 
     In some embodiments, the oscillating signal LO 1  and the shifted oscillating signal LO 2  are different in phase by about 90 degrees. The phase shifter  128  is configured to receive the oscillating signal LO 1  and generate the shifted oscillating signal LO 2  according to the oscillating signal LO 1 . Alternatively stated, in some embodiments, a phase shift of about 90 degrees is introduced to the oscillating signal LO 1  by the phase shifter  128 , to generate the shifted oscillating signal LO 2 . 
     The filter  124 A is configured to generate the output signal I(T) according to the data signal DS 1 . The filter  124 B is configured to generate the output signal Q(T) according to the data signal DS 2 . The mixer  126  is configured to generate the phase error signal ERR according to the output signal I(T) and the output signal Q(T). The phase error signal ERR indicates the phase difference between the oscillating signal LO 1  and the modulated signal Y(T). In some embodiments, since the oscillating signal LO 1  and the shifted oscillating signal LO 2  are different in phase by about 90 degrees, the phase error signal ERR also indicates the phase difference between the shifted oscillating signal LO 2  and the modulated signal Y(T). In some embodiments, the mixer  126  operates as a phase detector of the device  100 . 
     In some approaches without using the oscillating signal generator  140 , a phase offset is randomly introduced to the modulated signal Y(T) during the transmission progress. As a result, the output signals I(T) and Q(T) are different from the data carried in the modulated signal Y(T). Compared with the aforementioned approaches, the device  100  utilizes the analog to digital converter  142  to convert the phase error signal ERR, which is sufficient to indicate the phase offset introduced during the transmission progress, to the digital signal DOUT. The digital to time converter  144  then determines a delay time for the reference signal REF 1  according to the digital signal DOUT, and accordingly generates the reference signal REF 2 . Thus, the phase-locked loop  146  is able to generate the oscillating signal LO 1 , which is utilized for demodulating the modulated signal Y(T), according to the reference signal REF 2 . Effectively, the oscillating signal LO 1  is able to be synchronized with the carrier signal for the modulated signal Y(T). As a result, the output signals I(T) and Q(T) are correctly received. 
     In some embodiments, the analog to digital converter  142  and the digital to time converter  144  operate as a digital control circuit of the oscillating signal generator  140 . Compared with some approaches using a passive filter to control a voltage-controlled oscillator, variations on the digital control circuit in the device  100  are limited. Moreover, the analog to digital converter  142 , the digital to time converter  144 , and the phase-locked loop  146  together operate as a digital calibration mechanism for the oscillating signal LO 1 , i.e., the carrier signal of the modulated signal Y(T). In some embodiments, the digital calibration mechanism is implemented with various types of active circuits. Compared with the aforementioned approaches using the passive filter, a circuit area of the device  100  is reduced. 
       FIG. 2  is a flow chart of a method  200  illustrating operations of the device  100  in  FIG. 1 , in accordance with some embodiments of the present disclosure. The operations of the device  100  in  FIG. 1  are also described below by the method  200  illustrated in  FIG. 2 . For better understanding of the present disclosure, the method  200  is discussed in relation to the device  100  shown in  FIG. 1 , but is not limited thereto. 
     As illustratively shown in  FIG. 2 , the method  200  includes operation S 210 , S 220 , S 230 , S 240 , S 250  and S 260 . In operation S 210 , the mixer  122 A demodulates the modulated signal Y(T) according to the oscillating signal LO 1  to generate the data signal DS 1 , and the filter  124 A generates the output signal I(T) according to the data signal DS 1 . In operation S 220 , the mixer  122 B demodulates the modulated signal Y(T) according to the shifted oscillating signal LO 2  to generates the data signal DS 2 , and the filter  124 B generates the output signal Q(T) according to the data signal DS 2 , in which the shifted oscillating signal LO 2  is generated by the phase shifter  128  according to the oscillating signal LO 1 . In operation S 230 , the mixer  126  generates the phase error signal ERR according to the output signal I(T) and the output signal Q(T). In operation S 240 , the analog to digital converter  142  converts the phase error signal ERR to the digital signal DOUT. In operation S 250 , the digital to time converter  144  delays the reference signal REF 1  according to the digital signal DOUT, to generate the reference signal REF 2 . In operation S 260 , the phase-locked loop  146  generates the oscillating signal LO 1  according to the reference signal REF 2 . After operation S 260  is performed, in a steady state, the oscillating signal LO 1  is effectively calibrated. Thus, the mixer  122 A and the mixer  122 B are able to demodulate the modulated signal Y(T) according to the calibrated oscillating signal LO 1 . As a result, the coherent demodulation for the modulated signal Y(T) is permitted. 
     The above description includes exemplary operations, but the operations are not necessarily performed in the order described. The order of the operations disclosed in the present disclosure are able to be changed, or the operations are able to be executed simultaneously or partially simultaneously as appropriate, in accordance with the spirit and scope of various embodiments of the present disclosure. 
     Reference is made to  FIG. 3 .  FIG. 3  is a schematic diagram of the analog to digital converter  142  in  FIG. 1 , in accordance with various embodiments of the present disclosure. In some embodiments, the analog to digital converter  142  includes a voltage divider  320 , comparators OP 1 -OP 5 , and an encoder  340 . 
     In some embodiments, the voltage divider  320  is configured to generate at least one reference voltage according to at least one predetermined voltage. For illustration, the voltage divider is configured to generate reference voltages VR 1 -VR 5  according to the predetermined voltages VREF+ and VREF−. As illustratively shown in  FIG. 3 , in some embodiments the voltage divider  320  includes resistors R 1 -R 6  coupled in series. One end of the series-connected resistors R 1 -R 6  is configured to receive the predetermined voltage VREF+, and another end of the series-connected resistors R 1 -R 6  is configured to receive the predetermined voltage VREF−. With such arrangements, a voltage difference between the reference voltages VREF+ and VREF− is divided by the resistors R 1 -R 6  to generate the reference voltages VR 1 -VR 5 . 
     Furthermore, the comparators OP 1 -OP 5  are coupled to different nodes of the voltage divider  320  to receive reference voltages VR 1 -VR 5  respectively. The comparators OP 1 -OP 5  are configured to compare the phase error signal ERR with the reference voltages VR 1 -VR 5 , respectively, to generate bit signals Q 1 -Q 5 . Positive input terminals of the comparators OP 1 -OP 5  are configured to receive the phase error signal ERR. Negative input terminals of the comparators OP 1 -OP 5  are electrically coupled to different nodes between two of the resistors R 1 -R 6 , respectively. With such arrangements, the bit signals Q 1 -Q 5  are able to present the voltage level of the phase error signal ERR in a digital form. For example, if the voltage level of the phase error signal ERR is between the reference voltages VR 3  and VR 4 , the bit signals Q 4  and Q 5  are logic zero which indicates logic low level. Alternatively stated, as the reference voltages VR 4  and VR 5  are higher than the phase error signal ERR, the compactors OP 4  and OP 5  accordingly output the bit signals Q 4  and Q 5  being logic zero. On the other hand, as the reference voltages VR 1 -VR 3  are lower than the voltage level of the phase error signal ERR, the bit signals Q 1 -Q 3  are logic one which indicates logic high level. 
     In some embodiments, the bit signals Q 1 -Q 5  are 2 N-1 -bit thermometer codes, and are able to be converted to N-bit binary codes, in which N is an integer. As illustratively shown in  FIG. 3 , the encoder  340  is coupled to the output terminals of the comparators OP 1 -OP 5  to receive the bit signals Q 1 -Q 5 . The encoder  340  then converts the bit signals Q 1 -Q 5  to the digital signal DOUT. In some embodiments, the encoder  340  is a thermometer to binary encoder, and configured to output the digital signal DOUT with N-bit binary codes. 
     The arrangement of the analog to digital converter  142  in  FIG. 3  is given for illustrative purposes. Various arrangements of the analog to digital converter  142  are within the contemplated scope of the present disclosure. 
     Reference is made to  FIG. 4A .  FIG. 4A  is a schematic diagram of a digital to time converter  144  in  FIG. 1 , in accordance with various embodiments of the present disclosure. 
     In some embodiment, as illustratively shown in  FIG. 4A , the digital to time converter  142  includes an inverter chain  420 , capacitive units C 1 -C 5 , and switching units S 1 -S 5 . The inverter chain  420  is configured to generate the reference signal REF 2  according to the reference signal REF 1 . The switching units S 1 -S 5  are configured to be turned on or off according to the digital signal DOUT, in order to connect or disconnect the corresponding capacitive units C 1 -C 5  to the inverter chain  420 . 
     In some embodiments, the inverter chain  420  includes inverter units  422  and  424 . An input terminal of the inverter unit  422  is configured to receive the reference signal REF 1 . An input terminal of the inverter unit  424  is coupled to an output terminal of the inverter unit  422  at a node  426 , and an output terminal of the inverter unit  424  is configured to output the reference signal REF 2 . In some embodiments, the switching units S 1 -S 5  are configured to be turned on or off according to a corresponding bit of the digital signal DOUT. For illustration, the switching unit S 1  is turned on or off by a first bit of the digital signal DOUT, the switching unit S 2  is turned on or off by a second bit of the digital signal DOUT, and so on. Alternatively stated, for the digital signal DOUT with N-bits, the X-th bit of the digital signal DOUT is configured to turn the X-th switching unit of N switching units on or off. 
     As illustratively shown in  FIG. 4A , the capacitive units C 1 -C 5  are coupled to the node  426  via the switching units S 1 -S 5 , and are coupled in parallel with each other. Effectively, the output loading of the inverter unit  422  is varied with the connections of the switching units S 1 -S 5 . The delay time between the reference signal REF 1  and the reference signal REF 2  are varied with the output loading of the inverter unit  422 . In other words, the delay time is able to be determined by controlling the switching units S 1 -S 5 . The switching units S 1 -S 5  and the capacitive units C 1 -C 5  form an equivalent RC circuit, and the equivalent capacitance is determined according to the capacitive units C 1 -C 5  connected to the node  426 . For illustration, if the first bit of the digital signal DOUT is logic one, and the second bit to the fifth bit of the digital signal DOUT are logic zero, the switching unit S 1  is turned on, and the switching units S 2 -S 5  are thus turned off. As a result, the capacitive unit C 1  is connected to the node  426  via the switching unit S 1 , and the capacitive units C 2 -C 5  are disconnected to the node  426 . Thus, the output loading of the inverter  422  is adjusted, and the delay time is accordingly varied. 
     Reference is made to  FIG. 4B .  FIG. 4B  is a waveform illustrating the reference signal REF 1  and the reference signal REF 2  in  FIG. 4A  in accordance with various embodiments of the present disclosure. As illustratively shown in  FIG. 4B , a controllable and variable phase is present between the reference signal REF 2  and the reference signal REF 1 . Alternatively stated, the delay time DT between the reference signal REF 1  and the reference signal REF 2  is able to be adjusted according to the digital signal DOUT. In some embodiments, the capacitive units C 1 -C 5  are configured to have the same capacitance value. Alternatively, in some other embodiments, the capacitive units C 1 -C 5  are configured to have different capacitance values. For different applications, the capacitance values of the capacitive units C 1 -C 5  are properly adjusted according to practical needs. 
     As described above, based on the analog to digital converter  142  in  FIG. 3  and the digital to time converter  144  in  FIG. 4A , the phase of the reference signal REF 2  are adjusted, via the digital signal DOUT, according to different voltage levels of the phase error signal ERR. 
     The arrangement of the digital to time converter  144  in  FIG. 4A  is given for illustrative purposes. Various arrangements of the digital to time converter  144  are within the contemplated scope of the present disclosure. Furthermore, various proper electrical components are chosen to implement the functional units in the aforementioned embodiments. For example, in some embodiments, the switching units and the capacitive units are implemented with various types of transistors or other semiconductor components, and the comparators are implemented with operational amplifiers. 
     Reference is made to  FIG. 5 .  FIG. 5  is a schematic diagram of a phase-locked loop  146  in  FIG. 1 , in accordance with various embodiments of the present disclosure. As mentioned in the above paragraphs, the phase-locked loop  146  is configured to generate the oscillating signal LO 1  according to the reference signal REF 2 . Since the phase of the reference signal REF 2  is adjusted according to the phase error signal ERR, and the reference signal REF 2  is configured as the reference clock signal to generate the oscillating signal LO 1 , the phase of the oscillating signal LO 1  generated by the phase-locked loop  146  is thus controlled by the phase error signal ERR. 
     In some embodiments, the phase-locked loop  146  includes a phase detecting unit  520 , a filter unit  540 , an oscillator unit  560 , and a frequency divider unit  580 . The phase detecting unit  520  is configured to output an error signal ES according to the reference signal REF 2  and a feedback signal FS sent from the frequency divider unit  580 . The filter unit  540  includes a low-pass filter coupled to the phase detecting unit  520  and configured to filter the error signal ES and output a control signal CS. Then, the control signal CS is sent to the oscillator unit  560 , such that the oscillator unit  560  outputs the oscillating signal LO 1  according to the control signal CS. The frequency divider unit  580  is arranged in the feedback path and coupled between the oscillator unit  560  and the phase detecting unit  520 . 
     In some embodiments, the frequency divider unit  580  is configured to divide the frequency of the oscillating signal LO 1  by N and output the feedback signal FS to the phase detecting unit  520 . Alternatively stated, the frequency of the oscillating signal LO 1  is N times of the frequency of the reference signal REF 2 . In some embodiments, in a steady state, when the phase of the reference signal REF 2  is φ, the phase of the oscillating signal LO 1  is Nφ. In some embodiments, N is an integer number. 
     The arrangement of the phase-locked loop  146  illustrated in  FIG. 5  is given for illustrative purposes. Various arrangements of the phase-locked loop  146  are within the contemplated scope of the present disclosure. For example, in various embodiments, the phase-locked loop  146  further includes a reference input divider unit (not shown) configured to multiply the frequency of the reference signal REF 2  by a fractional number N/M. 
     Reference is now made to  FIG. 6 .  FIG. 6  is a schematic diagram of a device  600  in accordance with various embodiments of the present disclosure. With respect to the embodiments of  FIG. 1 , like elements in  FIG. 6  are designated with the same reference numbers for ease of understanding. 
     In some embodiments, the device  600  illustrated in  FIG. 6  is applied to transceivers employing Quadrature Phase Shift Keying (QPSK) modulation or Quadrature Amplitude Modulation (QAM). 
     For illustration, compared with the device  100 , the data receiving circuit  620  of the device  600  includes mixers  622 A- 622 D, filters  624 A and  624 B, limiters  624 C and  624 D, a subtractor  626 , and a phase shifter  628 . The filter  624 A is electrically coupled to the mixer  622 A. 
     A first input terminal of the mixer  622 A and a first input terminal of the mixer  622 B are configured to receive the modulated signal Y(T). A second input terminal of the mixer  622 A is electrically coupled to the output terminal of the phase-locked loop  146  to receive the oscillating signal LO 1 . A second input terminal of the mixer  622 B is electrically coupled to an output terminal of the phase shifter  628  to receive a shifted oscillating signal LO 2 . An input terminal of the filter  624 A is electrically coupled to an output terminal of the mixer  622 A to receive the data signal DS 1 . An input terminal of the filter  624 B is electrically coupled to an output terminal of the mixer  622 B to receive the data signal DS 2 . An input terminal of the limiter  624 C is electrically coupled to an output terminal of the filter  624 A to receive estimated data EST 1 . An input terminal of the limiter  624 D is electrically coupled to an output terminal of the filter  624 B to receive estimated data EST 2 . A first input terminal of the mixer  622 C is electrically coupled to an output terminal of the limiter  624 C to receive estimated data EST 3 , and a second input terminal of the mixer  622 C is electrically coupled to the output terminal of the filter  624 B to receive the estimated data EST 2 . A first input terminal of the mixer  622 D is electrically coupled to an output terminal of the limiter  624 D to receive estimated data EST 4 , and a second input terminal of the mixer  622 D is electrically coupled to the output terminal of the filter  624 A to receive the estimated data EST 1 . 
     A first input terminal and a second input terminal of the subtractor  626  are electrically coupled to an output terminal of the mixer  622 C and an output terminal of the filter mixer  622 D respectively to receive the output signal I(T) and Q(T). An output terminal of the subtractor  626  is electrically coupled to the input terminal of the analog to digital converter  142 . An input terminal of the phase shifter  628  is electrically coupled to the output terminal of the phase-locked loop  146  to receive the oscillating signal LO 1 . 
     In some embodiments for transceivers employing QPSK or QAM modulations, the limiter  624 C is configured to produce the estimated data EST 3  to indicate the sign of the estimated data EST 1 , and the limiter  624 D is configured to produce the estimated data EST 4  to indicate the sign of the estimated data EST 2 . The estimated data EST 3  and the estimated data EST 4  are then mixed with the estimated data EST 2  and the estimated data EST 1 , respectively. 
     Compared with the device  100 , the device  600  includes the subtractor  626 , instead of the mixer  126 . In some embodiments, the subtractor  626  is configured to subtract the output signal Q(T) from the output signal I(T) to generate the phase error signal ERR. 
       FIG. 7  is a flow chart of a method  700  illustrating operations of the device  600  in  FIG. 6 , in accordance with some embodiments of the present disclosure. The operations of the device  600  in  FIG. 6  are also described below by the method  700  illustrated in  FIG. 7 . For better understanding of the present disclosure, the method  700  is discussed in relation to the device  600  shown in  FIG. 6 , but is not limited thereto. With respect to the embodiments of  FIG. 2 , like elements in  FIG. 7  are designated with the same reference numbers for ease of understanding. 
     As illustratively shown in  FIG. 7 , the method  700  includes operation S 710 , S 720 , S 730 , S 740 , S 750 , S 240 , S 250  and S 260 . Compared with the method  200  illustrated in  FIG. 2 , in some embodiments illustrated in  FIGS. 6-7 , the operations of generating the phase error signal ERR in  FIG. 6 , i.e., operations S 710 -S 750 , are different from the operations S 210 -S 230  illustrated in  FIG. 2 . 
     In operation S 710 , the mixer  622 A demodulates the modulated signal Y(T) according to the oscillating signal LO 1  in order to generate the data signal DS 1 , and the filter  624 A generates the estimated data EST 1  according to the data signal DS 1 . In operation S 720 , the mixer  622 B demodulates the modulated signal Y(T) according to the shifted oscillating signal LO 2  to generate the data signal DS 2 , and the filter  624 B generates the estimated data EST 2  according to the data signal DS 2 , in which the shifted oscillating signal LO 2  is generated by the phase shifter  628  according to the oscillating signal LO 1 . 
     In operation S 730 , the limiter  624 C generates the estimated data EST 3  according to the estimated data EST 1 , and the mixer  622 C generates the output signal I(T) according to the estimated data EST 3  and the estimated data EST 2 . In operation S 740 , the limiter  624 D generates the estimated data EST 4  according to the estimated data EST 2 , and the mixer  622 D generates the output signal Q(T) according to the estimated data EST 4  and the estimated data EST 1 . 
     In operation S 750 , the subtractor  626  generates the phase error signal ERR according to the output signal I(T) and the output signal Q(T). 
     In some embodiments, the subtractor  626  operates as the phase detector of device  600  in  FIG. 6 . For illustration, in operations S 710 -S 750 , the subtractor  626  subtracts the output signal Q(T) from the output signal I(T) to generate the phase error signal ERR. Effectively, the phase error signal ERR indicates a difference between the oscillating signal LO 1  and the modulated signal Y(T). After operation S 750  is performed, the phase error signal ERR is then send to the oscillating signal generator  140 , in order to perform operations S 240 -S 260  as discussed above. After operation S 260  is performed, in a steady state, the oscillating signal LO 1  is effectively calibrated. Thus, the data receiving circuit  120  is able to demodulate the modulated signal Y(T) according to the calibrated oscillating signal LO 1 . As a result, the coherent demodulation for the modulated signal Y(T) is permitted. 
     The above description includes exemplary operations, but the operations are not necessarily performed in the order described. The order of the operations disclosed in the present disclosure are able to be changed, or the operations are able to be executed simultaneously or partially simultaneously as appropriate, in accordance with the spirit and scope of various embodiments of the present disclosure. 
     As described above, in the embodiments disclosed in the present disclosure, the phase of the reference signal sent to the phase-locked loop and the oscillator unit is tunable by a delay time controlled by the digital signal, such that the frequency and the phase of the local oscillation signal is adjusted by the loop circuit and therefore the modulated signal is properly demodulated according to the local oscillation signal. The carrier recovery method is applied in communication modulation systems employing various modulations including, for example, BPSK, QPSK, or QAM modulations as discussed in the aforementioned embodiments. 
     In some embodiments, a device is disclosed that includes an oscillating signal generator is configured to generate an oscillating signal according to a first reference signal and a phase error signal indicating a phase difference between the oscillating signal and a modulated signal. The oscillating signal generator includes a digital to time converter and a phase-locked loop. The digital to time converter is configured to generate a second reference signal by delaying the first reference signal according to a digital signal that is converted from the phase error signal. The phase-locked loop is configured to generate the oscillating signal in response to the second reference signal. 
     Also disclosed is a device that includes a first mixer, an analog to digital converter, and a digital to time converter. The first mixer is configured to generate a phase error signal that indicates a phase difference between an oscillating signal and a modulated signal. The analog to digital converter is configured to convert the phase error signal to a digital signal. The digital to time converter is configured to delay a first reference signal according to the digital signal, to generate a second reference signal for a phase-locked loop that is configured to generate the oscillating signal. 
     Also disclosed is a method that includes: converting a phase error signal to a digital signal by an analog to digital converter, adjusting a phase of a first reference signal by a digital to time converter, in response to the digital signal, to generate a second reference signal, and in response to the second reference signal, generating an oscillating signal by a phase-lock loop, for demodulation of a modulated signal. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.