Patent Publication Number: US-2022230674-A1

Title: Read operation method for non-volatile memory device to reduce disturbance

Description:
TECHNICAL FIELD 
     The disclosure relates in general to an operation method for a memory device, and more particularly to a read operation method for a memory device. 
     BACKGROUND 
     For three-dimension (3D) memory devices, after heavy read cycles, e.g. 100K read cycles on a selected word line, adjacent word lines adjacent to the selected word line may suffer read disturbance. 
     Analysis reveals that when the pre-turn on period of the selected word line is closed, if the pass voltage (Vpass) of the selected word line is lower than the threshold voltages of the selected word line, then the down-coupling effect occurs. This may cause large channel potential difference between the selected word line and adjacent word lines; and has a high vertical electronic field at the adjacent word lines. Hot carrier injection is likely to occur and then read disturbance occurs. 
     SUMMARY 
     According to one embodiment, an operation method for a memory device is provided. The operation method includes: increasing an adjacent word line voltage to a first adjacent word line voltage during a pre-turn on period; and increasing the adjacent word line voltage from the first adjacent word line voltage to a second adjacent word line voltage after the pre-turn on period is finished; wherein the first adjacent word line voltage is lower than the second adjacent word line voltage; the adjacent word line voltage is applied to at least one adjacent word line, and the at least one adjacent word line is adjacent to a selected word line. 
     According to another embodiment, provided is an operation method for a memory device. The operation method includes: increasing a selected word line voltage to a first adjacent word line voltage during a pre-turn on period; and lowering the selected word line voltage in multi-step lowering voltages from the first adjacent word line voltage to a reference voltage; wherein in lowering the selected word line voltage in the multi-step lowering voltages, voltage steps are at least more than two steps. 
     According to an alternative embodiment, provided is an operation method for a memory device. The operation method includes: increasing a selected word line voltage to a first selected word line voltage during a pre-turn on period; and lowering the selected word line voltage from first selected word line voltage in a smooth curve between a first timing and a second timing. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a functional block diagram of a memory device according to one embodiment of the application. 
         FIG. 2  shows a 3D circuit diagram of a memory array according to one embodiment of the application. 
         FIG. 3  shows a read operation waveform diagram of a memory device according to a first embodiment of the application. 
         FIG. 4  shows comparison of the horizontal electronic field and the vertical electronic field in the prior art and in the first embodiment of the application. 
         FIG. 5  shows a relationship curve of Vt (threshold voltage) variation to the read counts in the prior art and in the first embodiment of the application. 
         FIG. 6A  and  FIG. 6B  shows two read operation waveform diagrams of a memory device according to a second embodiment of the application. 
         FIG. 7  shows comparison of the horizontal electronic field and the vertical electronic field in the prior art and in the second embodiment of the application. 
         FIG. 8  shows a relationship curve of Vt (threshold voltage) variation to the read counts in the prior art and in the second embodiment of the application. 
         FIG. 9  shows a read operation waveform diagram of a memory device according to a third embodiment of the application. 
         FIG. 10  shows comparison of the horizontal electronic field and the vertical electronic field in the prior art and in the third embodiment of the application. 
         FIG. 11  shows a relationship curve of Vt (threshold voltage) variation to the read counts in the prior art and in the third embodiment of the application. 
     
    
    
     In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing. 
     DESCRIPTION OF THE EMBODIMENTS 
     Technical terms of the disclosure are based on general definition in the technical field of the disclosure. If the disclosure describes or explains one or some terms, definition of the terms is based on the description or explanation of the disclosure. Each of the disclosed embodiments has one or more technical features. In possible implementation, one skilled person in the art would selectively implement part or all technical features of any embodiment of the disclosure or selectively combine part or all technical features of the embodiments of the disclosure. 
       FIG. 1  shows a functional block diagram of a memory device according to one embodiment of the application. The memory device  100  includes: a controller  110  and a memory array  120 . The controller  110  is coupled to the memory array  120 . The controller  110  controls operations (for example the read operations) of the memory array  120 . 
       FIG. 2  shows a 3D circuit diagram of a memory array according to one embodiment of the application. The memory array  120  includes a plurality of string select lines (SSLs) SSL 0 _ 0  to SSL 2 _ 3 , a plurality of dummy word lines DWLT 1 , DWLT 0 , DWLB 1  and DWLB 0 , a plurality of word lines WL 0  to WLN−1 (N being a positive integer), a plurality of bit lines BL 0  to BL 3 , a plurality of global select lines (GSLs) GSL 0  to GSL 3  and a plurality of memory cells.  FIG. 2  is an example, and the application is not limited by this. 
     Usually, the memory array  120  includes a plurality of memory block each including for example but not limited by four sub-blocks. As shown in  FIG. 2 , the sub-blocks SB 0  to SB 3  are independently selected by the SSLs SSL 0 _ 0  to SSL 2 _ 3  and the GSLs GSL 0  to GSL 3 . 
       FIG. 3  shows a read operation waveform diagram of a memory device according to a first embodiment of the application. VBL refers to the bit line voltage, VSWL refers to the selected word line voltage, VUWL refers to the unselected word line voltage, VAWL refers to the adjacent word line voltage, VSSL refers to the SSL voltage and VGSL refers to the GSL voltage. In the following, the word line WLn (n being an integer between 0 and N−1) is referred as a selected word line (or a target word line), and the word lines WLn+1 and WLn−1 adjacent to the selected word line WLn are referred as adjacent word lines. The selected word line voltage VSWL is applied to the selected word line and the adjacent word line voltage VAWL is applied to the adjacent word lines. 
     In the first embodiment of the application, during the pre-turn on period, the bit line voltage VBL is at the low voltage (or said, a reference voltage) (for example but not limited by 0V). In the read period, the bit line voltage VBL is transited to the high voltage (T 34 ). When the read period finishes (T 37 ), the bit line voltage VBL is transited to the low voltage. 
     In the first embodiment of the application, during the pre-turn on period, the selected word line voltage VSWL is rising to a first selected word line voltage VSWL 1  at the timing T 31  and is lowering at the timing T 32 . During the read period, the selected word line voltage VSWL has multi-step voltages (or said, multi-step increasing voltages): a first step voltage (i.e. a second selected word line voltage VSWL 2 ) which is increased from the low voltage at the timing T 34 , and a second step voltage (i.e, a third selected word line voltage VSWL 3 ) which is increased from the first step voltage (i.e. the second selected word line voltage VSWL 2 ) at the timing T 35 . At timing  36 , the selected word line voltage VSWL is increased from the third selected word line voltage VSWL 3  to the first selected word line voltage VSWL 1 . When the read period is finished (T 3 ), the selected word line voltage VSWL is transited to the low voltage. The second selected word line voltage VSWL 2  and the third selected word line voltage VSWL 3  are read voltages. 
     In the first embodiment of the application, during the pre-turn on period, the unselected word line voltage VUWL is rising at the timing T 31 . When the read period is finished, the unselected word line voltage VUWL is transited to the low voltage. 
     In the first embodiment of the application, during the pre-turn on period, the adjacent word line voltage VAWL is rising to a first adjacent word line voltage VAWL 1  at the timing T 31 . After the pre-turn on period is finished, the adjacent word line voltage VAWL is rising from the first adjacent word line voltage VAWL 1  to a second adjacent word line voltage VAWL 2  at the timing T 33 . When the read period is finished, the adjacent word line voltage VAWL is transited to the low voltage. The first adjacent word line voltage VAWL 1  is lower than the second adjacent word line voltage VAWL 2 ; and the second adjacent word line voltage VAWL 2  is equal to the unselected word line voltage VUWL. 
     In the first embodiment of the application, during the pre-turn on period, the adjacent word line voltage VAWL of the adjacent word lines is lower than the selected word line voltage VSWL; and the vertical electronic field on the adjacent word lines during the pre-turn on period is reduced. 
     In the first embodiment of the application, the rising of the adjacent word line voltage VAWL to the second adjacent word line voltage VAWL 2  is later than the end of the pre-turn on period; and thus, the horizontal electronic field on the adjacent word lines is reduced. 
     In the first embodiment of the application, the first adjacent word line voltage VAWL 1  is for example but not limited by, higher than the threshold voltage of the memory cells of the adjacent word lines. For example, the first adjacent word line voltage VAWL 1  is between 2V and 5V. 
     In the first embodiment of the application, the second adjacent word line voltage VAWL 2  is corresponding to the pass voltage Vpass. For example, the second adjacent word line voltage VAWL 2 , which is a sufficient high pass voltage Vpass, is between 6V and 9V (or between 6V and 10V). 
     In the first embodiment of the application, during the pre-turn on period, the string select line voltage VSSL (labeled by “L 31 ”) of the selected sub-blocks and the string select line voltage VSSL (labeled by “L 32 ”) of the unselected sub-blocks are rising at the timing T 31 . When the pre-turn on period is finished, the string select line voltage VSSL (labeled by “L 32 ”) of the unselected sub-blocks is lowered at the timing T 32 . When the read period is finished, the string select line voltage VSSL (labeled by “L 31 ”) of the selected sub-blocks is lowered. During the read period, the string select line voltage VSSL (labeled by “L 32 ”) of the unselected sub-blocks is kept at the low voltage. 
     In the first embodiment of the application, during the pre-turn on period, the global select line voltage VGSL (labeled by “L 33 ”) of the selected sub-blocks and the global select line voltage VGSL (labeled by “L 34 ”) of the unselected sub-blocks are rising at the timing T 31 . When the pre-turn on period is finished, the global select line voltage VGSL (labeled by “L 34 ”) of the unselected sub-blocks is lowered at the timing T 32 . When the read period is finished, the global select line voltage VGSL (labeled by “L 33 ”) of the selected sub-blocks is lowered. During the read period, the global select line voltage VGSL (labeled by “L 34 ”) of the unselected sub-blocks is kept at the low voltage. 
       FIG. 4  shows comparison of the horizontal electronic field and the vertical electronic field in the prior art and in the first embodiment of the application. The curve L 41  refers to a horizontal electrical field between the channel and ONO (oxide-nitride-oxide) at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the prior memory device (not applying the read operations of the first embodiment of the application) when the pre-turn on period is finished. The curve L 42  refers to a horizontal electrical field between the channel and ONO at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the prior memory device (not applying the read operations of the first embodiment of the application) when the adjacent word line voltage VAWL is increased to the second adjacent word line voltage VAWL 2  (at the timing T 33 ). 
     The curve L 43  refers to a vertical electrical field between ONO and the gate at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the prior memory device (not applying the read operations of the first embodiment of the application) when the pre-turn on period is finished. The curve L 44  refers to a vertical electrical field between ONO and the gate at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the prior memory device (not applying the read operations of the first embodiment of the application) when the adjacent word line voltage VAWL is increased to the second adjacent word line voltage VAWL 2  (at the timing T 33 ). 
     The curve L 45  refers to a horizontal electrical field between the channel and ONO at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the first embodiment of the application when the pre-turn on period is finished. The curve L 46  refers to a horizontal electrical field between the channel and ONO at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the first embodiment of the application when the adjacent word line voltage VAWL is increased to the second adjacent word line voltage VAWL 2  (at the timing T 33 ). 
     The curve L 47  refers to a vertical electrical field between ONO and the gate at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the first embodiment of the application when the pre-turn on period is finished. The curve L 48  refers to a vertical electrical field between ONO and the gate at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the first embodiment of the application when the adjacent word line voltage VAWL is increased to the second adjacent word line voltage VAWL 2  (at the timing T 33 ). 
     By comparing the curves L 43  and L 47 , the read operations of the first embodiment of the application may effectively reduce the vertical electronic field at the adjacent word lines and further reduce the read disturbance. 
       FIG. 5  shows a relationship curve of Vt (threshold voltage) variation to the read counts in the prior art and in the first embodiment of the application. As shown in  FIG. 5 , the first embodiment of the application may reduce the Vt (threshold voltage) variation and further reduce the read disturbance. 
       FIG. 6A  and  FIG. 6B  show two read operation waveform diagrams of a memory device according to a second embodiment of the application. In  FIG. 6A  and  FIG. 6B , the bit line voltage VBL, the unselected word line VUWL, the string select line voltage VSSL and the global select line VGSL have waveforms the same or similar to that of the bit line voltage VBL, the unselected word line VUWL, the string select line voltage VSSL and the global select line VGSL in  FIG. 3 , and thus the details thereof are omitted. 
     Refer to  FIG. 6A . In the second embodiment of the application, during the pre-turn on period, the selected word line voltage VSWL is rising to a first selected word line voltage VSWL 601  at the timing T 601  and is lowering in multi-step lowering voltages at the timing T 602 . The selected word line voltage VSWL is lowered from the first selected word line voltage VSWL 601  to a second selected word line voltage VSWL 602  at the timing T 602 . The selected word line voltage VSWL is lowered from the second selected word line voltage VSWL 602  to a third selected word line voltage VSWL 603  at the timing T 603 . The selected word line voltage VSWL is lowered from the third selected word line voltage VSWL 603  to the low voltage at the timing T 604 . The selected word line voltage VSWL is increased from the low voltage to the first selected word line voltage VSWL 601  at the timing T 605 . The timing T 603 , T 604  and T 605  are within the read period. When the read period is finished (T 606 ), the selected word line voltage VSWL is transited to the low voltage. The second selected word line voltage VSWL 602  and the third selected word line voltage VSWL 603  are read voltages. 
     Refer to  FIG. 6A . In the second embodiment of the application, at beginning of the pre-turn on period, the adjacent word line voltage VAWL is rising; and the adjacent word line voltage VAWL is lowering at the end of the read period. 
     Refer to  FIG. 6B . In the second embodiment of the application, during the pre-turn on period, the selected word line voltage VSWL is rising to a first selected word line voltage VSWL 611  at the timing T 611  and is lowering in multi-step voltages at the timing T 612 . The selected word line voltage VSWL is lowered from the first selected word line voltage VSWL 611  to a second selected word line voltage VSWL 612  at the timing T 612 . The selected word line voltage VSWL is lowered from the second selected word line voltage VSWL 612  to a third selected word line voltage VSWL 613  at the timing T 613 . The selected word line voltage VSWL is lowered from the third selected word line voltage VSWL 613  to the low voltage at the timing T 614 . The multi-step voltage lowering of the selected word line voltage VSWL in  FIG. 6B  is similar to the multi-step voltage lowering of the selected word line voltage VSWL in  FIG. 6A . 
     The selected word line voltage VSWL is increased from the low voltage to the fourth selected word line voltage VSWL 614  at the timing T 615 . The selected word line voltage VSWL is increased from the fourth selected word line voltage VSWL 614  to the fifth selected word line voltage VSWL 615  at the timing T 616 . The selected word line voltage VSWL is increased from the fifth selected word line voltage VSWL 615  to the first selected word line voltage VSWL 611  at the timing T 617 . The multi-step voltage increase (during the read period) of the selected word line voltage VSWL in  FIG. 6B  is similar to the multi-step voltage increase (during the read period) of the selected word line voltage VSWL in  FIG. 3 . 
     When the read period is finished (T 618 ), the selected word line voltage VSWL is transited to the low voltage. The second selected word line voltage VSWL 612 , the third selected word line voltage VSWL 613 , the fourth selected word line voltage VSWL 614  and the fifth selected word line voltage VSWL 615  are read voltages. 
     The adjacent word line voltage VAWL in  FIG. 6B  has similar waveforms with the adjacent word line voltage VAWL in  FIG. 6A  and thus the details are omitted. 
     In the second embodiment of the application, the first selected word line voltage VSWL 601 /VSWL 611  is for example but not limited by, higher than the highest threshold voltage of the memory cells of the selected word line WLn. For example, the first selected word line voltage VSWL 601 /VSWL 611  is between 6V and 10V. 
     In the second embodiment of the application, in multi-step voltage lowering of the selected word line voltage VSWL, the second selected word line voltage VSWL 602 /VSWL 612  is lower than the first selected word line voltage VSWL 601 /VSWL 611 ; the third selected word line voltage VSWL 603 /VSWL 613  is lower than the second selected word line voltage VSWL 602 NSWL 612  and so on. 
     In the second embodiment of the application, in multi-step voltage lowering of the selected word line voltage VSWL, the voltage steps are at least more than two steps. 
       FIG. 7  shows comparison of the horizontal electronic field and the vertical electronic field in the prior art and in the second embodiment of the application. The curve L 71  refers to a horizontal electrical field between the channel and ONO at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the prior memory device (not applying the read operations of the second embodiment of the application) when the pre-turn on period is finished. The curve L 72  refers to a horizontal electrical field between the channel and ONO at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the prior memory device (not applying the read operations of the second embodiment of the application) at the timing T 605 /T 615 . The curve L 73  refers to a vertical electrical field between ONO and the gate at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the prior memory device (not applying the read operations of the second embodiment of the application) when the pre-turn on period is finished. The curve L 74  refers to a vertical electrical field between ONO and the gate at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the prior memory device (not applying the read operations of the second embodiment of the application) at the timing T 605 /T 615 . The curve L 75  refers to a horizontal electrical field between the channel and ONO at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the second embodiment of the application when the pre-turn on period is finished. The curve L 76  refers to a horizontal electrical field between the channel and ONO at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the second embodiment of the application at the timing T 605 /T 615 . The curve L 77  refers to a vertical electrical field between ONO and the gate at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the second embodiment of the application when the pre-turn on period is finished. The curve L 78  refers to a vertical electrical field between ONO and the gate at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the second embodiment of the application at the timing T 605 /T 615 . 
     By comparing the curves L 71  and L 75 , the read operations of the second embodiment of the application may effectively reduce the horizontal electronic field at the selected word line WLn and thus reduce the read disturbance. By comparing the curves L 73  and L 77 , the read operations of the second embodiment of the application may effectively reduce the vertical electronic field at the selected word line WLn and thus reduce the read disturbance. 
       FIG. 8  shows a relationship curve of Vt (threshold voltage) variation to the read counts in the prior art and in the second embodiment of the application. As shown in  FIG. 8 , the second embodiment of the application may reduce the Vt (threshold voltage) variation and further reduce the read disturbance. 
       FIG. 9  shows a read operation waveform diagram of a memory device according to a third embodiment of the application. In  FIG. 9 , the bit line voltage VBL, the unselected word line VUWL, the adjacent word line VAWL, the string select line voltage VSSL and the global select line VGSL have waveforms the same or similar to that of the bit line voltage VBL, the unselected word line VUWL, the adjacent word line VAWL, the string select line voltage VSSL and the global select line VGSL in  FIG. 6A  and  FIG. 6B , and thus the details thereof are omitted. 
     In the third embodiment of the application, during the pre-turn on period, the selected word line voltage VSWL is rising to a first selected word line voltage VSWL 91  at the timing T 91 . From the timing T 92  to the timing T 93 , the selected word line voltage VSWL is lowered from the first selected word line voltage VSWL 91  to the low voltage in a smooth curve. In one possible embodiment of the application, the smooth curve refers to, for example but not limited by, a straight line. 
     In the third embodiment of the application, the time length between the timing T 92  and the timing T 93  is longer than 1 μs, for example but not limited by, between 1 μs to 10 μs. 
     In the third embodiment of the application, during the read period, the selected word line voltage VSWL has multi-step voltages: a first step voltage (i.e. a second selected word line voltage VSWL 92 ) which is increased from the low voltage at the timing T 94 , and a second step voltage (i.e. a third selected word line voltage VSWL 93 ) which is increased from the first step voltage (i.e. the second selected word line voltage VSWL 92 ) at the timing T 95 . At timing  36 , the selected word line voltage VSWL is increased from the third selected word line voltage VSWL 93  to the first selected word line voltage VSWL 91 . When the read period is finished (T 97 ), the selected word line voltage VSWL is transited to the low voltage. The second selected word line voltage VSWL 92  and the third selected word line voltage VSWL 93  are read voltages. 
       FIG. 10  shows comparison of the horizontal electronic field and the vertical electronic field in the prior art and in the second embodiment of the application. The curve L 101  refers to a horizontal electrical field between the channel and ONO at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the prior memory device (not applying the read operations of the third embodiment of the application) when the pre-turn on period is finished. The curve L 102  refers to a vertical electrical field between ONO and the gate at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the prior memory device (not applying the read operations of the third embodiment of the application) when the pre-turn on period is finished. The curve L 103  refers to a horizontal electrical field between the channel and ONO at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the third embodiment of the application at the timing T 93 . The curve L 104  refers to a vertical electrical field between ONO and the gate at the selected word line WLn, the adjacent word lines WLn−1, WLn+1 in the third embodiment of the application at the timing T 93 . 
     By comparing the curves L 101 , L 102 , L 103  and L 104 , the read operations of the third embodiment of the application may effectively reduce the horizontal electronic field and the vertical electronic field at the selected word line WLn for reducing the read disturbance. 
       FIG. 11  shows a relationship curve of Vt (threshold voltage) variation to the read counts in the prior art and in the third embodiment of the application, As shown in  FIG. 11 , the third embodiment of the application may reduce the Vt (threshold voltage) variation and further reduce the read disturbance. 
     The first embodiment, the second embodiment and the third embodiment may be independently implemented or may be implemented in combination. For example, the first embodiment and the second embodiment may be implemented in combination. Alternatively, the first embodiment and the third embodiment may be implemented in combination. These are within the spirit and the scope of the application. 
     From the above description, the above embodiments of the application may effectively reduce abnormal read disturbance on the selected word line. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.