Patent Publication Number: US-8525498-B2

Title: Average input current limit method and apparatus thereof

Description:
TECHNICAL FIELD 
     The present invention generally relates to an input current limit method, and more particularly, relates to a method and apparatus for limiting the average value of the input current. 
     BACKGROUND 
     USB powered devices have become ubiquitous because of the popularity of computers. However, the voltage supplied by a USB connection has a characteristic that limits the use of USB powered devices. Specifically, the output voltage of the USB port will decrease when the output current from the USB port is larger than some value, for example, 500 mA. So there is a need to limit the current supplied by the USB port in order to allow proper use of USB powered devices. 
       FIG. 1  illustrates one prior art peak current limiting method for current limit. The current (known also as input current in  FIG. 1 ) flowing through the switch Sin is sensed and compared with a threshold VCLM. The switch Sin is turned off when the sensed current is larger than the threshold VCLM, thus limiting the peak value of the input current. However, the duty cycle of the switch Sin varies with different outputs and the actual input current supplied by the power source is the average value of the current flowing through the switch Sin because of the large input capacitor Cin. Therefore, the peak value of the input current does not mean the same current supplied by the power source. When the output voltage is low, a large input current range is wasted. 
     In order to limit the input current, the peak current limit could also be used to directly limit the peak value of the current supplied by the power source. A disadvantage of this method is that the current supplied by the power source cannot follow the input current flowing rapidly through the switch Sin. Therefore, it cannot be used directly to control the input current, which is a critical parameter on a per cycle basis. 
       FIG. 2  illustrates another prior art circuit for current limiting. A resistor R and a switch S are coupled between the power source and the power device. The resistor R is used to sense the current supplied by the power source. The “on” resistance of the switch S is regulated according to the sensed current so as to limit the current. In this method, the resistor R cannot be integrated in the same IC with the switch S and other control circuits because it is used to sense and must be very accurate. So the complexity and cost of the whole circuit are increased. The switch S will also increase the power loss and may cause thermal issues. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention can be further understood with reference to the following detailed description and the appended drawings, wherein like elements are provided with like reference numerals. 
         FIG. 1  illustrates a prior art circuit for input current limiting. 
         FIG. 2  illustrates another prior art circuit of input current limiting. 
         FIG. 3  illustrates a block diagram of a voltage regulator with average input current limit, in accordance with one embodiment of the present disclosure. 
         FIG. 4  illustrates a Buck circuit with average input current limit, in accordance with another embodiment of the present disclosure. 
         FIG. 5  is the waveform of the circuit shown in  FIG. 4  in operation. 
         FIG. 6  is the flow chart of the average input current limit method in accordance with still another embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Disclosed in this description is an input current limit method and apparatus that limits the average value of the input current. DC-input voltage regulators generally have large input capacitors so that the average value of the input current after the input capacitor is absolutely equal to the current actually supplied by the power source. The current supplied by the power source is limited through limiting the average value of the input current. 
       FIG. 3  illustrates a block diagram of the voltage regulator with average input current limit in accordance with one embodiment of the present disclosure. It comprises a switching circuit  301 , a current average circuit  302  and a current limit circuit  303 . The switching circuit  301  comprises an input current Iin and an input capacitance Cin. The current average circuit  302  is coupled to the switching circuit  301  to sense the input current Iin and generate a signal VITG that represents the average value of the input current Iin. The current limit circuit  303  is coupled to the switching circuit  301  and current average circuit  302  to limit the signal VITG to a threshold voltage VCLM, so as to limit the average value of the input current Iin to some value. 
     The switching circuit  301  comprises a large input capacitor Cin and an input switch Sin through which the input current Iin flows. When the average value of the input current Iin is limited, the actual current supplied by the power source is limited because of the large input capacitor Cin. The switching circuit  301  may be any topology that comprises an input switch, such as Buck, Buck-Boost, flyback and so on. In one embodiment, the switching circuit  301  is a Buck circuit. 
     The current average circuit  302  comprises a current sensing circuit  304 , a capacitor Citg and a switch Sitg. The current sensing circuit  304  is coupled to the switching circuit  301  to sense the input current Iin and generate a sensed current Isense. The current sensing circuit  304  may be a resistor sensing circuit or a circuit that works like a current mirror. One terminal of the capacitor Citg is coupled to the current sensing circuit  304  to receive the sensed current Isense. The other terminal of the capacitor Citg is grounded. The switch Sitg is coupled across the capacitor Citg and is turned on and off complementarily with the input switch Sin. When the input switch Sin is on, the switch Sitg is off, the capacitor Citg is charged by the sensed current Isense, and the voltage VITG across the capacitor Citg is increased. When the input switch Sin is off, the switch Sitg is on, then the capacitor Citg is quickly discharged, and the voltage VITG is quickly decreased to zero. So in each switching cycle, the peak value of the voltage VITG represents the integration value of the input current Iin and also the average value of the input current Iin. 
     The current limit circuit  303  comprises a comparing circuit  305  and a control circuit  306 . The comparing circuit  305  is coupled to the current average circuit  302  to receive the signal VITG, which is representative of the average value of the input current Iin, and compare it with a threshold voltage VCLM to generate a signal OAC. If the signal VITG is larger than the threshold voltage VCLM, the signal OAC is valid, otherwise it is invalid. The control circuit  306  is coupled to the comparing circuit  305  and the switching circuit  301  to receive the signal OAC and control the on and off function of the switches in the switching circuit  301 . If the signal OAC is valid, the control circuit  306  will turn off the input switch Sin to limit the voltage VITG, so as to limit the average value of the input current Iin. The comparing circuit  305  may be any circuit that can realize comparison. In one embodiment, it only comprises a comparator. The control circuit  306  may sense one or more parameters of the switching circuit  301 , including current, voltage and power, and use any control method such as PFM or PWM to control the on and off function of the switches in the switching circuit  301 . 
       FIG. 4  illustrates a Buck circuit with average input current limit in accordance with another embodiment. The switching circuit  301  is a non-synchronous Buck circuit comprising an input capacitor Cin, an input switch Sin, a diode D, an inductor L and an output capacitor Cout. The input switch Sin may be MOSFET or any other kind of semiconductor device, and it may be N-type or P-type. In this embodiment, the input switch Sin is a P-type MOSFET. The diode D may also be substituted by a synchronous rectifier to form a synchronous Buck circuit. 
     The current average circuit  302  comprises a current sensing circuit  304 , a capacitor Citg and a switch Sitg. The current sensing circuit  304  is coupled to the switching circuit  301  to sense the input current Iin and generate a sensed current Isense. One terminal of the capacitor Citg is coupled to the current sensing circuit  304  to receive the sensed current Isense. The other terminal of the capacitor Citg is grounded. The switch Sitg is coupled across the capacitor Citg and turned on and off complementarily with the input switch Sin. The peak value of the voltage VITG across the capacitor Citg represents the average value of the input current Iin. 
     The comparing circuit  305  comprises a comparator COM 1 . The non-inverting input terminal of the comparator COM 1  is coupled to the current average circuit  302  to receive the voltage VITG. The inverting input terminal of the comparator COM 1  is coupled to a threshold voltage VCLM. The output terminal of the comparator COM 1  is coupled to the control circuit  306  to output the signal OAC. When the voltage VITG is larger than the threshold voltage VCLM, the signal OAC is valid, i.e., high level, otherwise it is invalid, i.e., low level. 
     The control circuit  306  is coupled to the comparing circuit  305  and the switching circuit  301 , and turns off the input switch Sin when the signal OAC is valid. In this embodiment, the control circuit  306  further senses the output voltage VOUT of the switching circuit  301  and combines it with the signal VITG to control the on and off function of the switches in the switching circuit  301 . The control circuit  306  comprises resistors Rd 1 , Rd 2 , R 1 , R 2 , comparators COM 2  and COM 3 , a capacitor C 1  and a flip-flop Qff. The resistors Rd 1  and Rd 2  form a voltage sensing circuit, i.e., a voltage divider, to sense the output voltage VOUT. This voltage sensing circuit may also be realized by capacitors. The sensed output voltage signal is coupled to the inverting input of the comparator COM 3  and the capacitor C 1 . The other terminal of capacitor C 1  is coupled to the resistor R 1  of which another terminal is coupled to the output terminal of comparator COM 3  and the resistor R 2 . The other terminal of resistor R 2  is coupled to the inverting input of comparator COM 2 . The non-inverting input of the comparator COM 3  is coupled to a voltage reference VREF, which represents the required output voltage. The non-inverting terminal of comparator COM 2  is coupled to the voltage VITG. The flip-flop Qff comprises two reset terminals. One is coupled to the comparing circuit  305  to receive the signal OAC, the other is coupled to the output terminal of comparator COM 2 . The not output Q of the flip-flop Qff is coupled to the drive circuit and the switch Sitg to control the on and off function of the input switch Sin and switch Sitg. The set terminal of the flip-flop Qff is coupled to a clock signal CLK. 
     The current average circuit  302  may either be external or integrated into the IC together with the current limit circuit  303 . If it is integrated, it may be difficult to maintain the capacitance of the capacitor Citg at a constant value. The capacitor Citg may vary with the die temperature. So in situations with the same average input current, the voltage VITG across the capacitor Citg may be different. The result of the comparison between the voltage VITG and the threshold voltage VCLM also may not be accurate. As a result, a threshold correction circuit is needed to adjust the threshold voltage VCLM along with the capacitor Citg. 
     In one embodiment, a threshold correction circuit  401  is used to adjust the threshold voltage VCLM along with the capacitor Citg. When the integration capacitor Citg becomes larger because of the die temperature, the integration voltage VITG will become lower under the same average input switch current condition. The threshold correction circuit  401  will lower the threshold voltage VCLM along with the voltage VITG to make sure the output of the comparing circuit  305  accurate. 
     In  FIG. 4 , the threshold correction circuit  401  comprises a charge current supply circuit  402 , a capacitor Citg 1 , a switch Sitg 1 , and a sample and hold circuit S/H. The charge current supply circuit  402  is coupled to one terminal of the capacitor Citg 1  to provide a constant charge current Icharge for the capacitor Citg 1 . The other terminal of the capacitor Citg 1  is grounded. The switch Sitg 1  is parallel with the capacitor Citg 1 . The sample and hold circuit S/H is coupled to the capacitor Citg 1  to sample and hold the voltage VR across the capacitor Citg 1 . A clock signal is used to control the switch Sitg 1  and the sampled and hold circuit S/H. In one embodiment, the threshold correction circuit  401  and the control circuit  306  share the same clock signal CLK. The S/H circuit may sample and hold the voltage VR at the rising edge of the CLK signal or earlier. The sampled and held value is used as the threshold voltage VCLM. The current average circuit  302  and threshold correction circuit  401  are integrated. So the capacitor Citg 1  as well as the threshold voltage VCLM will be changed also if the capacitor Citg is changed because of the die temperature. 
     The charge current supply circuit  402  may be any circuit that can supply constant current. In one embodiment, the charge current supply circuit  402  comprises a comparator COM 2 , a resistor R 11 , switch S 11 , S 12  and S 13 . The non-inverting terminal of the comparator COM 2  is coupled to a reference VREF 1 , and the inverting terminal is coupled to the resistor R 11  and the source of the switch S 11 . The other terminal of the resistor R 11  is grounded. The output terminal of the comparator COM 2  is coupled to the gate of the switch S 11  whose drain is coupled to the gate and drain of the switch S 12 . The sources of switch S 12  and S 13  are coupled to the input terminal. The gate of switch S 12  and S 13  are coupled together. The drain of the switch S 13  is coupled to the capacitor Citg 1 , switch Sitg 1  and the sample and hold circuit S/H. Switches S 12  and S 13  form a current mirror. The charge current Icharge is determined by the reference VREF 1 , resistor R 11  and the width-length rate of switches S 12  and S 13 . 
       FIG. 5  is the waveform of the circuit shown in  FIG. 4  in operation. When the CLK signal is high, the flip-flop Qff is set, the not output  Q  of the flip-flop Qff becomes low. The input switch Sin is turned on and the switch Sitg is turned off. The capacitor Citg is charged by the sensed current Isense, the voltage VITG across the capacitor Citg is increased. The switch Sitg 1  is turned on and the capacitor Citg 1  is quickly discharged, the voltage VR across the capacitor Citg 1  is quickly decreased. In this embodiment, the S/H circuit samples and holds the voltage VR a little bit earlier than the rising edge of the CLK signal. The sampled and held value is used as the threshold voltage VCLM. When the CLK signal is low, the switch Sitg 1  is turned off and the capacitor Citg 1  is charged by the constant current Icharge supplied by the charge current supply circuit  402 . The voltage VR is increased. When the voltage VITG becomes larger than the feedback signal COMP or the threshold voltage VCLM, the flip-flop Qff is reset, the not output  Q  of the flip-flop Qff becomes high. The input switch Sin is turned off and the switch Sitg is turned on. The capacitor Citg is quickly discharged, the voltage VITG across the capacitor Citg is quickly decreased to zero. 
     When the input switch Sin is on, the switch Sitg is off. The relationship between VITG and ISENSE is 
                 C   itg     ⁢       ⅆ     V   ITG         ⅆ   t         =       I   sense     .           
When the input switch Sin is off, the switch Sitg is on, I sense =I in =0, V ITG =0. Provided the current sampling ratio is n, so
 
               I   sense     =       1   n     ⁢       I     i   ⁢           ⁢   n       .             
The average value of the input current Iin in each cycle is
 
     
       
         
           
             
               
                 
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     wherein f N  is the switching frequency of the input switch Sin, i.e., the frequency of the CLK signal, and D is the duty cycle of the input switch Sin. The average value of the input current Iin is limited if the voltage VITG is limited. If we want to limit the average value of the input current Iin to a value limit, then the threshold voltage VCLM should be 
               V   CLM     =         I   limit       n   *     C   itg     *     f   s         .           
Through the threshold voltage VCLM and the charge current Icharge and when the sample and hold circuit S/H samples and holds the voltage, the capacitance of the capacitor Citg 1  can be decided.
 
     The description also discloses an average input current limit method in a voltage regulator, which can limit the average value of the input current.  FIG. 6  is the flow chart of the average input current limit method. 
     Step A, sensing the input current that flows or “is flowing” through the input switch Sin. 
     Step B, determining whether the input switch Sin is on. If the input switch Sin is on, go to step C, otherwise go to step D. 
     Step C, using the sensed current to charge a capacitor Citg, then go to step E. 
     Step D, quickly discharging the capacitor Citg, then go to step B. 
     Step E, determining whether the voltage Vitg across the capacitor Citg is larger than a threshold voltage Vclm. If yes, go to step F, else go to step B. 
     Step F, turn off the input switch Sin. 
     In one embodiment, the method further comprises a step to adjust the threshold voltage Vclm with the capacitor Citg. 
     In one embodiment, the method further comprises using the voltage Vitg across the capacitor Citg in controlling the on and off function of the switches in the voltage regulator. 
     From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.