Patent Publication Number: US-2020294609-A1

Title: Semiconductor storage device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-047705, filed on Mar. 14, 2019; the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a semiconductor storage device. 
     BACKGROUND 
     In a semiconductor storage device including a fuse element, a resistive state of the fuse element varies depending on existence/non-existence of writing of bit information into the fuse element. Here, it is desired to appropriately read the bit information from the fuse element. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram illustrating a configuration of a semiconductor storage device according to an embodiment; 
         FIG. 2  is a circuit diagram illustrating a configuration of a semiconductor storage device according to a first modification example of the embodiment; 
         FIG. 3  is a circuit diagram illustrating a configuration of a semiconductor storage device according to a second modification embodiment of the embodiment; 
         FIG. 4  is a circuit diagram illustrating a configuration of a semiconductor storage device according to a third modification example of the embodiment; 
         FIG. 5  is a circuit diagram illustrating a configuration of a semiconductor storage device according to a fourth modification example of the embodiment; 
         FIG. 6  is a circuit diagram illustrating a configuration of a semiconductor storage device according to a fifth modification example of the embodiment; 
         FIG. 7  is a circuit diagram illustrating a configuration of a semiconductor storage device according to a sixth modification example of the embodiment; 
         FIG. 8  is a circuit diagram illustrating a configuration of a semiconductor storage device according to a seventh modification example of the embodiment; and 
         FIG. 9  is a circuit diagram illustrating a configuration of a semiconductor storage device according to an eighth modification example of the embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, there is provided a semiconductor storage device including a latch circuit, a connection circuit, a first fuse element, and a writing circuit. The latch circuit is arranged across a first current path and a second current path. The connection circuit is arranged across the first current path and the second current path. The first fuse element is arranged in the first current path. The writing circuit is electrically connected to one end of the first fuse element. At least one of the latch circuit and the connection circuit has higher current driving capability with respect to the first current path than current driving capability with respect to the second current path. 
     Exemplary embodiments of a semiconductor storage device will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments. 
     Embodiment 
     A semiconductor storage device according to the embodiment is, for example, a one-time programmable (OTP) memory and includes one or more memory circuits including a fuse element. In the semiconductor storage device, a resistive state of the fuse element varies depending on existence/non-existence of writing of bit information into the fuse element. Here, it is desired to appropriately read the bit information from the fuse element. 
     For example, in a case where a fusing type (poly-fusing type) fuse element is used, it is possible to make a circuit area of the fuse element small compared to a case where a gate breakdown-type fuse element is used since programming in low voltage is possible and high voltage is not necessary. In this case, in order to read existence/non-existence of writing of bit information into a fuse element, it is considered to provide a current path in which a magnitude relationship of resistance is reversed according to existence/non-existence of writing into the fuse element (second current path) in parallel with a current path including the fuse element that is an object of writing (first current path). 
     Here, when a resistance element that requires a large circuit area is arranged in the second current path as an element to reverse a magnitude relationship of a resistance value in a current path according to existence/non-existence of writing of bit information, there is a tendency that a circuit area of a semiconductor storage device is increased. 
     For example, there is a possibility that a circuit area of a semiconductor storage device becomes larger than a circuit area required by a specification of a case where the semiconductor storage device has a single-bit configuration. Also, in a case where a semiconductor storage device includes a storage capacity of a several bits for a purpose of trimming (that is, case of including a plurality of memory circuits), when a resistance element is arranged in a second current path in each memory circuit, there is a possibility that a circuit area of the semiconductor storage device further becomes larger than a circuit area required by a specification. Accordingly, there is a possibility that it becomes difficult to mount a semiconductor storage device (such as OTP memory) in a semiconductor device without a logic region and/or a semiconductor device of a small analog product or the like. 
     Thus, in the present embodiment, a memory circuit is configured in such a manner that current driving capability with respect to a first current path becomes higher than current driving capability with respect to a second current path in a semiconductor storage device, whereby appropriate reading of bit information from a fuse element is made possible without an arrangement of a resistance element in the second current path. 
     Specifically, a semiconductor storage device  1  may be configured in a manner illustrated in  FIG. 1 .  FIG. 1  is a circuit diagram illustrating a configuration of the semiconductor storage device  1 . The semiconductor storage device  1  includes one or more memory circuits  2 . Each memory circuit  2  includes a latch circuit  10 , a connection circuit  20 , a fuse element FE 1 , a fuse element FE 2 , a fuse element FE 3 , a writing circuit  30 , a driving circuit  40 , a control circuit  50 , a signal generating circuit  60 , and an output circuit  70 . 
     Two current paths CP 1  and CP 2  are provided in the memory circuit  2 . The current path CP 1  and the current path CP 2  are current paths from power potential to reference potential VBP through a common current path CP 3 , and are electrically connected to each other in parallel between the power potential and a common node Nc. The common current path CP 3  is electrically connected between the common node Nc and the reference potential VBP. 
     The latch circuit  10  is placed on a power potential side compared to the connection circuit  20  and the fuse elements FE 1  to FE 3 , and is arranged across the current path CP 1  and the current path CP 2 . The connection circuit  20  is placed between the latch circuit  10  and the fuse elements FE 1  to FE 3 , and is arranged across the current path CP 1  and the current path CP 2 . The fuse element FE 1  is placed on a reference potential side compared to the latch circuit  10  and the connection circuit  20 , and is arranged in the current path CP 1 . Each of the fuse elements FE 2  and FE 3  is placed on the reference potential side compared to the latch circuit  10  and the connection circuit  20 , and is arranged in the current path CP 2 . An input side of the writing circuit  30  is electrically connected to the signal generating circuit  60 , and an output side thereof is electrically connected to one end of the fuse element FE 1 . An input side of the control circuit is electrically connected to the signal generating circuit  60 , and an output side thereof is electrically connected to the latch circuit  10  and the connection circuit  20 . An input side of the output circuit  70  is electrically connected to the latch circuit  10 , and an output side thereof is electrically connected to an output node Nout. 
     The latch circuit  10  includes an NMOS transistor NT 1 , a PMOS transistor PT 1 , an NMOS transistor NT 2 , and a PMOS transistor PT 2 . 
     The NMOS transistor NT 1  and the PMOS transistor PT 1  are arranged in the current path CP 1  and are connected to each other in series in the current path CP 1 . A gate of each of the NMOS transistor NT 1  and the PMOS transistor PT 1  is connected to the current path CP 2 . The NMOS transistor NT 2  and the PMOS transistor PT 2  are arranged in the current path CP 2  and are connected to each other in series in the current path CP 2 . A gate of each of the NMOS transistor NT 2  and the PMOS transistor PT 2  is connected to the current path CP 1 . 
     A source of the NMOS transistor NT 1  is electrically connected to the connection circuit  20 , a drain thereof is electrically connected to a node N 1 , and a gate thereof is electrically connected to a node N 2 . The node N 1  is a node between the MOS transistor NT 1  and the PMOS transistor PT 1  in the current path CP 1 . The node N 2  is a node between the MOS transistor NT 2  and the PMOS transistor PT 2  in the current path CP 2 . A source of a PMOS transistor NT 1  is electrically connected to power potential, a drain thereof is electrically connected to the node N 1 , and a gate thereof is electrically connected to the node N 2 . A source of the NMOS transistor NT 2  is electrically connected to the connection circuit  20 , a drain thereof is electrically connected to the node N 2 , and a gate thereof is electrically connected to the node N 1 . A source of a PMOS transistor NT 2  is electrically connected to the power potential, a drain thereof is electrically connected to the node N 2 , and a gate thereof is electrically connected to the node N 1 . 
     The connection circuit  20  includes an NMOS transistor NT 3  and an NMOS transistor NT 4 . 
     The NMOS transistor NT 3  is electrically connected to the NMOS transistor NT 1  and the PMOS transistor PT 1  in series in the current path CP 1 . A source of the NMOS transistor NT 3  is electrically connected to the fuse element FE 1 , a drain thereof is electrically connected to the source of the NMOS transistor NT 1 , and a gate thereof is electrically connected to the control circuit. The NMOS transistor NT 3  receives a control signal from the control circuit at the gate. 
     The NMOS transistor NT 4  is electrically connected to the NMOS transistor NT 2  and the PMOS transistor PT 2  in series in the current path CP 2 . A source of the NMOS transistor NT 4  is electrically connected to the fuse element FE 2 , a drain thereof is electrically connected to the source of the NMOS transistor NT 2 , and a gate thereof is electrically connected to the control circuit. The NMOS transistor NT 3  receives a control signal from the control circuit at the gate. 
     The signal generating circuit  60  includes an NMOS transistor NT 11 , a PMOS transistor PT 11 , an NMOS transistor NT 12 , and a PMOS transistor PT 12 . 
     The NMOS transistor NT 11  and the PMOS transistor PT 11  are connected as an inverter, a common gate being electrically connected to an input node  60   a  and a common drain being electrically connected to an intermediate node  60   b . The NMOS transistor NT 12  and the PMOS transistor PT 12  are connected as an inverter, a common gate being electrically connected to the intermediate node  60   b  and a common drain being electrically connected to an output node  60   c.    
     The NMOS transistor NT 11  and the PMOS transistor PT 11  generate an inverted control signal PRGb that is a control signal PRG inverted logically, and supply the generated signal to the intermediate node  60   b  and to the control circuit  50  from the intermediate node  60   b . The NMOS transistor NT 12  and the PMOS transistor PT 12  generate a control signal PRGt that is the inverted control signal PRGb further inverted logically, and supply the generated signal from the output node  60   c  to the writing circuit  30 . 
     The writing circuit  30  includes an NMOS transistor NT 21 , a PMOS transistor PT 21 , an NMOS transistor NT 22 , a PMOS transistor PT 22 , an NMOS transistor NT 23 , a PMOS transistor PT 23 , and an NMOS transistor (writing transistor) NT 24 . 
     The NMOS transistor NT 21  and the PMOS transistor PT 21  are connected as an inverter, a common gate being electrically connected to an input node  30   a  for a clock signal WCLK and a common drain being electrically connected to an intermediate node  30   c . The NMOS transistor NT 23  and the PMOS transistor PT 23  are connected as an inverter, a common gate being electrically connected to the intermediate node  30   c  and a common drain being electrically connected to an intermediate node  30   d . The NMOS transistor NT 22  and the PMOS transistor PT 22  are connected in a cascade, a common gate being electrically connected to an input node  30   b  for the control signal PRGt. A source of the NMOS transistor NT 22  is electrically connected to ground potential, and a drain thereof is electrically connected to a source of the NMOS transistor NT 21 . A source of the PMOS transistor PT 22  is electrically connected to the power potential, and a drain thereof is electrically connected to the intermediate node  30   c . A gate of the NMOS transistor NT 24  (writing transistor) is electrically connected to the intermediate node  30   d , a source thereof is electrically connected to the ground potential, and a drain thereof is electrically connected to an output node  30   e.    
     The driving circuit  40  includes a PMOS transistor PT 3  and a PMOS transistor PT 4 . A source of the PMOS transistor PT 3  is connected to the power potential, a gate thereof is connected to the control circuit  50 , and drain thereof is connected to the node N 1 . A source of the PMOS transistor PT 4  is connected to the power potential, a gate thereof is connected to the control circuit  50 , and a drain thereof is connected to the node N 2 . 
     The control circuit  50  includes an NMOS transistor NT 31 , a PMOS transistor PT 31 , an NMOS transistor NT 32 , a PMOS transistor PT 32 , an NMOS transistor NT 33 , and a PMOS transistor PT 33 . 
     The NMOS transistor NT 31  and the PMOS transistor PT 31  are connected as an inverter, a common gate being electrically connected to an input node  50   a  for a control signal POR and a common drain being electrically connected to an intermediate node  50   c . The NMOS transistor NT 33  and the PMOS transistor PT 33  are connected as an inverter, a common gate being electrically connected to the intermediate node  50   c  and a common drain being electrically connected to an output node  50   d . The NMOS transistor NT 32  and the PMOS transistor PT 32  are connected in a cascade, a common gate being electrically connected to an input node  50   b  for the inverted control signal PRGb. A source of the NMOS transistor NT 32  is electrically connected to the ground potential, and a drain thereof is electrically connected to a source of the NMOS transistor NT 31 . A source of the PMOS transistor PT 32  is electrically connected to the power potential, and a drain thereof is electrically connected to the intermediate node  50   c.    
     The output circuit  70  includes an NMOS transistor NT 41 , a PMOS transistor PT 41 , an NMOS transistor NT 42 , a PMOS transistor PT 42 , an NMOS transistor NT 43 , and a PMOS transistor PT 43 . 
     The NMOS transistor NT 41  and the PMOS transistor PT 41  are connected as an inverter, a common gate being electrically connected to an input node  70   a  and a common drain being electrically connected to an intermediate node  70   b . The NMOS transistor NT 42  and the PMOS transistor PT 42  are connected as an inverter, a common gate being electrically connected to the intermediate node  70   b  and a common drain being electrically connected to an intermediate node  70   c . The NMOS transistor NT 43  and the PMOS transistor PT 43  are connected as an inverter, a common gate being electrically connected to the intermediate node  70   c  and a common drain being electrically connected to an output node Nout. With this configuration, the output circuit  70  outputs, from the output node Nout, a signal in which bit information read from the fuse element FE 1  through the latch circuit  10  is logically inverted. 
     The memory circuit  2  is configured in such a manner that current driving capability with respect to the current path CP 1  becomes higher than current driving capability with respect to the current path CP 2 . 
     For example, current driving capability of the NMOS transistor NT 1  may be higher than current driving capability of the NMOS transistor NT 2  in the latch circuit  10 . A dimension (=(gate width)/(gate length)) of the NMOS transistor NT 1  is larger than a dimension of the NMOS transistor NT 2 . A threshold voltage of the NMOS transistor NT 1  is lower than a threshold voltage of the NMOS transistor NT 2 . The NMOS transistor NT 1  has a larger dimension than the NMOS transistor NT 2  and a lower threshold voltage than the NMOS transistor NT 2 . Here, current driving capability of the PMOS transistor PT 1  may be substantially equal to current driving capability of the PMOS transistor PT 2 , and current driving capability of the NMOS transistor NT 3  may be substantially equal to current driving capability of the NMOS transistor NT 4 . 
     Alternatively, current driving capability of the PMOS transistor PT 1  may be lower than current driving capability of the PMOS transistor PT 2  in the latch circuit  10 . A dimension (=(gate width)/(gate length)) of the PMOS transistor PT 1  is smaller than a dimension of the PMOS transistor PT 2 . A threshold voltage of the PMOS transistor PT 1  is higher than a threshold voltage of the PMOS transistor PT 2 . The PMOS transistor PT 1  has a smaller dimension than the PMOS transistor PT 2  and a higher threshold voltage than the PMOS transistor PT 2 . Here, current driving capability of the NMOS transistor NT 1  may be substantially equal to current driving capability of the NMOS transistor NT 2 , and current driving capability of the NMOS transistor NT 3  may be substantially equal to current driving capability of the NMOS transistor NT 4 . 
     Alternatively, current driving capability of the NMOS transistor NT 1  may be higher than current driving capability of the NMOS transistor NT 2 , and current driving capability of the PMOS transistor PT 1  may be lower than current driving capability of the PMOS transistor PT 2  in the latch circuit  10 . Here, current driving capability of the NMOS transistor NT 3  may be substantially equal to current driving capability of the NMOS transistor NT 4 . 
     Alternatively, current driving capability of the NMOS transistor NT 3  may be higher than current driving capability of the NMOS transistor NT 4  in the connection circuit  20 . A dimension (=(gate width)/(gate length)) of the NMOS transistor NT 3  is larger than a dimension of the NMOS transistor NT 4 . A threshold voltage of the NMOS transistor NT 3  is lower than a threshold voltage of the NMOS transistor NT 4 . The NMOS transistor NT 3  has a larger dimension than the NMOS transistor NT 4  and a lower threshold voltage than the NMOS transistor NT 4 . Here, current driving capability of the NMOS transistor NT 1  may be substantially equal to current driving capability of the NMOS transistor NT 2 , and current driving capability of the PMOS transistor PT 1  may be substantially equal to current driving capability of the PMOS transistor PT 2 . 
     Alternatively, current driving capability of the NMOS transistor NT 1  may be higher than current driving capability of the NMOS transistor NT 2  in the latch circuit  10 , and current driving capability of the NMOS transistor NT 3  may be higher than current driving capability of the NMOS transistor NT 4  in the connection circuit  20 . Here, current driving capability of the PMOS transistor PT 1  may be substantially equal to current driving capability of the PMOS transistor PT 2 . 
     Alternatively, current driving capability of the PMOS transistor PT 1  may be lower than current driving capability of the PMOS transistor PT 2  in the latch circuit  10 , and current driving capability of the NMOS transistor NT 3  may be higher than current driving capability of the NMOS transistor NT 4  in the connection circuit  20 . Here, current driving capability of the NMOS transistor NT 1  may be substantially equal to current driving capability of the NMOS transistor NT 2 . 
     Alternatively, current driving capability of the NMOS transistor NT 1  may be higher than current driving capability of the NMOS transistor NT 2  in the latch circuit  10 , current driving capability of the PMOS transistor PT 1  may be lower than current driving capability of the PMOS transistor PT 2  in the latch circuit  10 , and current driving capability of the NMOS transistor NT 3  may be higher than current driving capability of the NMOS transistor NT 4  in the connection circuit  20 . 
     That is, at least one of the latch circuit  10  and the connection circuit  20  is configured in such a manner that current driving capability with respect to the current path CP 1  becomes higher than current driving capability with respect to the current path CP 2 . Also, a plurality of fuse elements FE 2  and FE 3  (that is, fuse elements the number of which is larger than that in the current path CP 1 ) is arranged in the current path CP 2 . Accordingly, it is possible to reverse a magnitude relationship in resistance in the current path CP 1  and the current path CP 2  equivalently according to existence/non-existence of fusion of the fuse element FE 1  (existence/non-existence of writing of bit information) even when no resistance element is arranged in the current path CP 2 . Note that a layout area of the plurality of fuse elements FE 2  and FE 3  arranged in the current path CP 2  is much smaller than a layout area of a resistance element. 
     Accordingly, it is possible to make resistance of the current path CP 2  higher than resistance of the current path CP 1  equivalently according to the fuse element FE 1  not being fused (there being no writing of bit information). Also, it is possible to make resistance of the current path CP 1  higher than resistance of the current path CP 2  equivalently according to the fuse element FE 1  being fused (there being writing of bit information). As a result, it is possible to appropriately read bit information from the fuse element FE 1 . 
     For example, when the control signal POR becomes an active level (such as H level) and the control signal PRGb becomes an active level (such as H level) before the fuse element FE 1  is fused (low resistive state or bit state “0”), a control signal RD becomes an active level (such as H level) and the NMOS transistors NT 3  and NT 4  of the connection circuit  20  are turned on. Also, since the control signal PRGt logically inverted with respect to the control signal PRGb becomes a non-active level (such as L level), the NMOS transistor NT 24  (writing transistor) is kept in an off state. 
     In a period in which the control signal RD is the active level, current corresponding to a resistance value in a low resistive state of the fuse element FE 1  flows in the current path CP 1 , and current corresponding to a total resistance value of the plurality of fuse elements FE 2  and FE 3  flows in the current path CP 2 . Here, since current driving capability with respect to the current path CP 1  is higher than current driving capability with respect to the current path CP 2  in at least one of the latch circuit  10  and the connection circuit  20  and the plurality of fuse elements FE 2  and FE 3  is connected to the current path CP 2 , more current flows in the current path CP 1 . Accordingly, the output node N 2  of the latch circuit  10  holds a state of the “H” level, and the output circuit  70  outputs the “L” level corresponding to the bit state “0” to the output node Nout in response thereto. 
     When a clock WCLK becomes an active level (such as H level) and the control signal PRGt becomes an active level (such as H level), the NMOS transistor NT 24  (writing transistor) is kept in an on state. Also, since the control signal PRGb becomes a non-active level (such as L level), the control signal RD becomes a non-active level (such as L level) and the NMOS transistors NT 3  and NT 4  of the connection circuit  20  are turned on. 
     Since the NMOS transistor NT 24  (writing transistor) is kept in the on state, a large current flows in the fuse element FE 1  due to a potential difference between potential of the node Nc and the ground potential, the fuse element FE 1  is fused, and a bit value “1” is stored. 
     When the control signal POR becomes an active level (such as H level) and the control signal PRGb becomes an active level (such as H level) after the fuse element FE 1  is fused (high resistive state or bit state “1”), the control signal RD becomes an active level (such as H level) and the NMOS transistors NT 3  and NT 4  of the connection circuit  20  are turned on. Also, since the control signal PRGt logically inverted with respect to the control signal PRGb becomes a non-active level (such as L level), the NMOS transistor NT 24  (writing transistor) is kept in the off state. 
     In a period in which the control signal RD is the active level, current corresponding to a total resistance value of the plurality of fuse elements FE 2  and FE 3  flows in the current path CP 2 . Here, since the fuse element FE 1  is fused, current does not flow in the current path CP 1  substantially, and more current flows in the current path CP 2 . Accordingly, the output node N 2  of the latch circuit  10  holds a state of the “L” level, and the output circuit  70  outputs the “H” level corresponding to the bit state “1” to the output node Nout in response thereto. 
     As described above, in the embodiment, the memory circuit  2  is configured in such a manner that current driving capability with respect to the current path CP 1  becomes higher than current driving capability with respect to the current path CP 2  in the semiconductor storage device  1 . Accordingly, it becomes possible to appropriately read bit information from the fuse element FE 1  without arranging a resistance element in the current path CP 2 . As a result, it is possible to reduce a circuit area of the semiconductor storage device  1 , and it becomes possible to implement the semiconductor storage device  1  into a semiconductor device without a logic region and/or a semiconductor device of a small analog product or the like. 
     Note that when at least one of the latch circuit  10  and the connection circuit  20  is configured in such a manner that current driving capability with respect to the current path CP 1  becomes adequately higher than current driving capability with respect to the current path CP 2 , it is possible to reverse a magnitude relationship of resistance values in the current paths CP 1  and CP 2  according to existence/non-existence of writing of bit information into the fuse element FE 1  even when the number of fuse elements arranged in the current path CP 2  is reduced. 
     For example, as illustrated in  FIG. 2 , the number of fuse elements arranged in a current path CP 2  may be made identical to the number of fuse elements arranged in a current path CP 1  by omission of a fuse element FE 3  (see  FIG. 1 ) from the current path CP 2 .  FIG. 2  is a circuit diagram illustrating a configuration of a semiconductor storage device  1  according to a first modification example of the embodiment. In this configuration, it is also possible to realize an effect similar to that of the embodiment and to further reduce a circuit area. 
     For example, as illustrated in  FIG. 3 , the number of fuse elements arranged in a current path CP 2  may be made smaller than the number of fuse elements arranged in a current path CP 1  by omission of fuse elements FE 2  and FE 3  (see  FIG. 1 ) from the current path CP 2 .  FIG. 3  is a circuit diagram illustrating a configuration of a semiconductor storage device  1  according to a second modification example of the embodiment. In this configuration, it is also possible to realize an effect similar to that of the embodiment and to further reduce a circuit area. 
     Also, a change in consideration of a balance in a circuit may be added to a semiconductor storage device  1 . In a current path CP 1 , a drain of an NMOS transistor NT 24  (writing transistor) is connected between a fuse element FE 1  and an NMOS transistor NT 3  and it is possible to assume that capacity loads are connected equivalently. 
     With respect to that, a dummy writing circuit  180  is connected to a current path CP 2 , for example, as illustrated in  FIG. 4 .  FIG. 4  is a circuit diagram illustrating a configuration of a semiconductor storage device  1  according to a third modification example of the embodiment. The writing circuit  180  is connected to a node between a fuse element FE 2  and an NMOS transistor NT 4 . The writing circuit  180  includes an NMOS transistor NT 54 . A source of the NMOS transistor NT 54  is connected to ground potential, a gate thereof is connected to the ground potential, and a drain thereof is connected to the node between the fuse element FE 2  and the NMOS transistor NT 4 . A dimension (=W/L, W: channel width and L: channel length) of the NMOS transistor NT 54  may be substantially equal to a dimension of the NMOS transistor NT 24 . Accordingly, it is possible not only to realize an effect similar to that of the embodiment but also to make capacity loads the same between the current path CP 1  and the current path CP 2 . As a result, it is possible to increase a margin of a resistance value in a case of reversing a magnitude relationship of resistance values in the current paths CP 1  and CP 2  according to existence/non-existence of writing of bit information, that is, a bit information reading margin. 
     Also, in this configuration, when at least one of a latch circuit  10  and a connection circuit  20  is configured in such a manner that current driving capability with respect to the current path CP 1  becomes adequately higher than current driving capability with respect to the current path CP 2 , it is possible to reverse a magnitude relationship of resistance values in the current paths CP 1  and CP 2  according to existence/non-existence of writing of bit information into the fuse element FE 1  even when the number of fuse elements arranged in the current path CP 2  is reduced. 
     For example, as illustrated in  FIG. 5 , the number of fuse elements arranged in a current path CP 2  may be made identical to the number of fuse elements arranged in a current path CP 1  by omission of a fuse element FE 3  (see  FIG. 4 ) from the current path CP 2 .  FIG. 5  is a circuit diagram illustrating a configuration of a semiconductor storage device  1  according to a fourth modification example of the embodiment. In this configuration, it is also possible to realize an effect similar to that of the embodiment and to further reduce a circuit area. 
     Also, a writing circuit that performs writing may be connected to a current path CP 2  instead of a dummy writing circuit. For example, as illustrated in  FIG. 6 , a writing circuit  280  is connected to the current path CP 2 .  FIG. 6  is a circuit diagram illustrating a configuration of a semiconductor storage device  1  according to a fifth modification example of the embodiment. The writing circuit  280  is connected to a node between a fuse element FE 2  and a fuse element FE 3 . The writing circuit  280  includes an NMOS transistor NT 51 , a PMOS transistor PT 51 , an NMOS transistor NT 52 , a PMOS transistor PT 52 , an NMOS transistor NT 53 , a PMOS transistor PT 53 , and an NMOS transistor (writing transistor) NT 54 . The writing circuit  280  has a connection configuration similar to that of the writing circuit  30 , and performs an operation similar to that of the writing circuit  30 . 
     In this configuration, the writing circuit  30  receives data DATA in an input node  30   a , and the writing circuit  280  receives data DATA in a corresponding input node  280   a . Accordingly, when the writing circuit  30  writes bit information “1” into a fuse element FE 1 , the writing circuit  280  makes the fuse element FE 3  hold bit information “0” without performing writing. Also, when the writing circuit  280  writes the bit information “1” into the fuse element FE 3 , the writing circuit  30  makes the fuse element FE 1  hold the bit information “0” without performing writing. As a result, it is possible to make a memory circuit  2  hold the data DATA complementarily and to make the memory circuit  2  securely hold the bit information. 
     In this configuration, it is also possible not only to realize an effect similar to that of the embodiment but also to make capacity loads the same between a current path CP 1  and a current path CP 2 . As a result, it is possible to increase a margin of a resistance value in a case of reversing a magnitude relationship of resistance values in the current paths CP 1  and CP 2  according to existence/non-existence of writing of bit information, that is, a bit information reading margin. 
     Also, in this configuration, when at least one of a latch circuit  10  and a connection circuit  20  is configured in such a manner that current driving capability with respect to the current path CP 1  becomes adequately higher than current driving capability with respect to the current path CP 2 , it is possible to reverse a magnitude relationship of resistance values in the current paths CP 1  and CP 2  according to existence/non-existence of writing of bit information into the fuse element FE 1  even when the number of fuse elements arranged in the current path CP 2  is reduced. 
     For example, as illustrated in  FIG. 7 , the number of fuse elements arranged in a current path CP 2  may be made identical to the number of fuse elements arranged in a current path CP 1  by omission of a fuse element FE 2  (see  FIG. 6 ) from the current path CP 2 .  FIG. 7  is a circuit diagram illustrating a configuration of a semiconductor storage device  1  according to a sixth modification example of the embodiment. In this configuration, it is also possible to realize an effect similar to that of the embodiment and to further reduce a circuit area. 
     Also, it is possible to commonalize a partial configuration of a writing circuit  30  and a writing circuit  280  in a configuration illustrated in  FIG. 6 . For example, as illustrated in  FIG. 8 , a writing circuit  380  is configured by replacement of an NMOS transistor NT 51 , a PMOS transistor PT 51 , an NMOS transistor NT 52 , a PMOS transistor PT 52 , an NMOS transistor NT 53 , and a PMOS transistor PT 53  respectively with an NMOS transistor NT 21 , a PMOS transistor PT 21 , an NMOS transistor NT 22 , a PMOS transistor PT 22 , an NMOS transistor NT 23 , and a PMOS transistor PT 23  while a connection relationship in a writing circuit  280  is kept.  FIG. 8  is a circuit diagram illustrating a configuration of a semiconductor storage device  1  according to a seventh modification example of the embodiment. Here, a gate of an NMOS transistor (writing transistor) NT 54  is connected to an intermediate node  30   a  in a writing circuit  30 . Accordingly, the writing circuit  380  illustrated in  FIG. 8  can realize an operation similar to that of the writing circuit  280  illustrated in  FIG. 6 . In the configuration illustrated in  FIG. 8 , a circuit area can be reduced compared to a configuration illustrated in  FIG. 6 . 
     In this configuration, it is also possible not only to realize an effect similar to that of the embodiment but also to make capacity loads the same between a current path CP 1  and a current path CP 2 . As a result, it is possible to increase a margin of a resistance value in a case of reversing a magnitude relationship of resistance values in the current paths CP 1  and CP 2  according to existence/non-existence of writing of bit information, that is, a bit information reading margin. 
     Also, in this configuration, when at least one of a latch circuit  10  and a connection circuit  20  is configured in such a manner that current driving capability with respect to the current path CP 1  becomes adequately higher than current driving capability with respect to the current path CP 2 , it is possible to reverse a magnitude relationship of resistance values in the current paths CP 1  and CP 2  according to existence/non-existence of writing of bit information into the fuse element FE 1  even when the number of fuse elements arranged in the current path CP 2  is reduced. 
     For example, as illustrated in  FIG. 9 , the number of fuse elements arranged in a current path CP 2  may be made identical to the number of fuse elements arranged in a current path CP 1  by omission of a fuse element FE 2  (see  FIG. 6 ) from the current path CP 2 .  FIG. 9  is a circuit diagram illustrating a configuration of a semiconductor storage device  1  according to an eighth modification example of the embodiment. In this configuration, it is also possible to realize an effect similar to that of the embodiment and to further reduce a circuit area. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.