Patent Publication Number: US-2021193765-A1

Title: Transparent display device

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims priority from Korean Patent Application No. 10-2019-0175640, filed on Dec. 24, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. 
     BACKGROUND 
     Technical Field 
     The present disclosure relates to a transparent display device. 
     Description of the Related Art 
     With advancement in information-oriented societies, demands for display devices that display an image have increased in various forms. Recently, various types of display devices such as a liquid crystal display (LCD) device, a plasma display panel (PDP) device, and an organic light emitting display (OLED) device, a quantum dot light emitting display (QLED) device have been widely utilized. 
     Recent, studies for transparent display devices for allowing a user to look at objects or image arranged on an opposite side of a display device after transmitting the display device are actively ongoing. 
     A transparent display device includes a display area on which an image is displayed, and a non-display area, wherein the display area may include a transmissive area that may transmit external light, and a non-transmissive area. 
     BRIEF SUMMARY 
     The inventors of the present disclosure recognized the importance of the transparent display device having a high light transmittance in the transmissive area and also ensuring a maximum light emission area in the non-transmissive area. Accordingly, one or more embodiments of the present disclosure provides a transparent display device that may improve light transmittance in a transmissive area. 
     One or more embodiments of the present disclosure provides a transparent display device that may increase or maximize a light emission area in a non-transmissive area. 
     Further embodiments of the present disclosure provides a transparent display device that may prevent diffraction from occurring when external light passes through a transmissive area. 
     In addition to the technical benefits of the present disclosure as mentioned above, additional benefits and features of the present disclosure will be clearly understood by those skilled in the art from the following description of the present disclosure. 
     In accordance with an aspect of the present disclosure, the above and other benefits can be accomplished by the provision of a transparent display device comprising a substrate provided with a display area including a transmissive area and a non-transmissive area, in which a plurality of subpixels are disposed, and a non-display area surrounding the display area, at least one insulating layer provided over the substrate, anode electrodes provided in each of the plurality of subpixels over the at least one insulating layer, a bank provided among the anode electrodes, a light emitting layer provided over the anode electrodes, and a cathode electrode provided over the light emitting layer. The at least one insulating layer and the bank are provided in only the non-transmissive area. 
     In accordance with another aspect of the present disclosure, the above and other benefits can be accomplished by the provision of a transparent display device comprising a substrate provided with a display area including a transmissive area and a non-transmissive area, in which a plurality of subpixels are disposed, and a non-display area surrounding the display area, a common power line provided over the substrate and extended in the display area in a first direction, and a pixel power line provided over the substrate and extended in the display area in the first direction. The transmissive area is provided between the pixel power line and the common power line, and includes a plurality of second curved portions. 
     According to the present disclosure, an insulating layer having a high refractive index is removed from the transmissive area, whereby light transmittance of the transmissive area may be improved. 
     Also, according to the present disclosure, the bank is removed from the transmissive area, whereby a yellowish phenomenon may be prevented from occurring in the transmissive area. 
     Also, according to the present disclosure, common power lines and pixel power lines may alternately be disposed in the display area, and the transmissive area may be provided between the common power line and the pixel power line. Also, a first subpixel may be provided in an area where a gate line and the common power line cross each other, and a third subpixel may be provided in an area where the gate line and the pixel power line cross each other, and a second subpixel may be provided between the first subpixel and the third subpixel. Therefore, the present disclosure may improve transmittance by maximizing the transmissive area. 
     Also, according to the present disclosure, the anode electrode provided in each of the first and third subpixels may include a first portion, a second portion protruded from one side of the first portion, and a third portion protruded from the other side of the first portion. Here, the second portion and the third portion may prevent diffraction from occurring due to a plurality of metal lines by covering the metal lines provided therebelow. 
     Also, according to the present disclosure, the second portion and the third portion may be formed in the anode electrode provided in each of the first and third subpixels, whereby an area of a light emission area may be increased or maximized in the non-transmissive area. 
     Also, according to the present disclosure, a curved portion may be provided in the transmissive area, whereby light concentration on a specific direction due to diffraction may be reduced. 
     In addition to the effects of the present disclosure as mentioned above, additional advantages and features of the present disclosure will be clearly understood by those skilled in the art from the above description of the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The above and other features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a perspective view illustrating a transparent display device according to one embodiment of the present disclosure; 
         FIG. 2  is a schematic plane view illustrating a transparent display panel; 
         FIG. 3  is an enlarged view of an area A in  FIG. 2 ; 
         FIG. 4A  is a plane view illustrating an anode electrode, a first inter-layer insulating layer, a second inter-layer insulating layer and a bank; 
         FIG. 4B  is a plane view illustrating a color filter layer; 
         FIG. 5  is a cross-sectional view taken along line I-I of  FIG. 3 ; 
         FIG. 6  is a cross-sectional view taken along line II-II of  FIGS. 4A and 4B ; 
         FIG. 7  is a cross-sectional view taken along line of  FIGS. 4A and 4B ; 
         FIGS. 8A and 8B  are views illustrating shapes of first, second and third anode electrodes; 
         FIGS. 9A to 9E  are views illustrating shapes of a transmissive area and a non-transmissive area; 
         FIG. 10  is an enlarged view of an area B in  FIG. 2 ; 
         FIG. 11  is a cross-sectional view taken along line IV-IV of  FIG. 10 ; 
         FIG. 12  is a cross-sectional view taken along line V-V of  FIG. 10 ; and 
         FIG. 13  is a cross-sectional view taken along line VI-VI of  FIG. 10 . 
     
    
    
     DETAILED DESCRIPTION 
     Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. 
     Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. 
     A shape, a size, a ratio, an angle, and a number disclosed in the drawings for describing embodiments of the present disclosure are merely an example, and thus, the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout the specification. In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted. In a case where ‘comprise,’ have,&#39; and ‘include’ described in the present specification are used, another part may be added unless ‘only˜’ is used. The terms of a singular form may include plural forms unless referred to the contrary. 
     In construing an element, the element is construed as including an error range although there is no explicit description. 
     In describing a position relationship, for example, when the position relationship is described as ‘upon˜,’ ‘above˜’, ‘below˜,’ and ‘next to˜,’ one or more portions may be arranged between two other portions unless ‘just’ or ‘direct’ is used. 
     It will be understood that, although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. 
     In describing elements of the present disclosure, the terms “first,” “second,” etc., may be used. These terms are intended to identify the corresponding elements from the other elements, and basis, order, or number of the corresponding elements are not limited by these terms. The expression that an element is “connected” or “coupled” to another element should be understood that the element may directly be connected or coupled to another element but may directly be connected or coupled to another element unless specially mentioned, or a third element may be interposed between the corresponding elements. 
     Features of various embodiments of the present disclosure may be partially or overall coupled to or combined with each other, and may be variously inter-operated with each other and driven technically as those skilled in the art can sufficiently understand. The embodiments of the present disclosure may be carried out independently from each other, or may be carried out together in co-dependent relationship. 
     Hereinafter, an example of a transparent display device according to the present disclosure will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
       FIG. 1  is a perspective view illustrating a transparent display device according to one embodiment of the present disclosure. 
     Hereinafter, X axis indicates a line parallel with a gate line, Y axis indicates a line parallel with a data line, and Z axis indicates a height direction of a transparent display device  100 . 
     Although a description has been described based on that the transparent display device  100  according to one embodiment of the present disclosure is embodied as an organic light emitting display device, the transparent display device  100  may be embodied as a liquid crystal display device, a plasma display panel (PDP), a Quantum dot Light Emitting Display (QLED) or an Electrophoresis display device. 
     Referring to  FIG. 1 , the transparent display device  100  according to one embodiment of the present disclosure includes a transparent display panel  110 , a source drive integrated circuit (IC)  210 , a flexible film  220 , a circuit board  230 , and a timing controller  240 . 
     The transparent display panel  110  includes a first substrate  111  and a second substrate  112 , which face each other. The second substrate  112  may be an encapsulation substrate. The first substrate  111  may be a plastic film, a glass substrate, or a silicon wafer substrate formed using a semiconductor process. The second substrate  112  may be a plastic film, a glass substrate, or an encapsulation film. The first substrate  111  and the second substrate  112  may be made of a transparent material. 
     The gate driver supplies gate signals to the gate lines in accordance with a gate control signal which is provided from the timing controller  240 . The gate driver may be provided in one side of the display area of the transparent display panel  110 , or the non-display area of both peripheral sides of the transparent display panel  110  by a gate driver in panel (GIP) method. In another way, the gate driver may be manufactured in a driving chip, may be mounted on the flexible film, and may be attached to one side of the display area of the transparent display panel  110 , or the non-display area of both peripheral sides of the transparent display panel  110  by a tape automated bonding (TAB) method. 
     The source drive IC  210  receives digital video data and source control signals from the timing controller  240 . The source drive IC  210  converts the digital video data into analog data voltages in accordance with the source control signal, and supplies the analog data voltages to the data lines. If the source drive IC  210  is manufactured in a driving chip, the source drive IC  210  may be mounted on the flexible film  220  by a chip on film (COF) method or a chip on plastic (COP) method. 
     Pads, such as power pads and data pads, may be formed in a non-display area of the transparent display panel  110 . Lines connecting the pads with the source drive IC  210  and lines connecting the pads with lines of the circuit board  230  may be formed in the flexible film  220 . The flexible film  220  may be attached onto the pads using an anisotropic conducting film, whereby the pads may be connected with the lines of the flexible film  220 . 
       FIG. 2  is a schematic plane view illustrating a transparent display panel,  FIG. 3  is an enlarged view of an area A in  FIG. 2 ,  FIG. 4A  is a plane view illustrating an anode electrode, a first inter-layer insulating layer, a second inter-layer insulating layer and a bank,  FIG. 4B  is a plane view illustrating a color filter layer,  FIG. 5  is a cross-sectional view taken along line I-I of  FIG. 3 ,  FIG. 6  is a cross-sectional view taken along line II-II of  FIGS. 4A and 4B ,  FIG. 7  is a cross-sectional view taken along line of  FIGS. 4A and 4B ,  FIGS. 8A and 8B  are views illustrating shapes of first, second and third anode electrodes, and  FIGS. 9A to 9E  are views illustrating shapes of a transmissive area and a non-transmissive area. 
     The substrate  111  may include a display area DA where pixels P are formed to display an image, and a non-display area NDA that does not display an image. 
     The display area DA, as shown in  FIG. 3 , includes a transmissive area TA and a non-transmissive area NTA. The transmissive area TA is an area through which most of externally incident light passes, and the non-transmissive area NTA is an area through which most of externally incident light fails to transmit. For example, the transmissive area TA may be an area where light transmittance is greater than α%, for example, 90%, and the non-transmissive area NTA may be an area where light transmittance is smaller than (β%, for example, 50%. In some embodiments, α is greater than β. A user may view an object or background arranged on a rear surface of the transparent display panel  110  due to the transmissive area TA. 
     The non-transmissive area NTA may be provided with pixel power lines VDDL, common power lines VSSL, reference lines, data lines, gate lines GL, and pixels P. The transmissive area TA and the non-transmissive area NTA can be considered from different viewpoints. In a first viewpoint, the transmissive area TA can be considered as a single area TA that is the sum of the all areas on the display that are transmissive. In this respect, it is proper to label and discuss this area as the transmissive area TA. In a second view point, the transmissive area TA can be considered and viewed as a plurality of individual areas. In this respect, each individual area TA is one transmissive area and there are a plurality of transmissive areas TA that comprise the display. 
     In a similar fashion, in a first viewpoint, the non-transmissive area TA can be considered as a single area NTA that is the sum of the all areas on the display that are non-transmissive. In this respect, it is proper to label and discuss this area as the non-transmissive area NTA and refer to this area as a whole. In a second view point, the non-transmissive area NTA can be considered and viewed as a plurality of individual areas NTA. In this respect, each individual area NTA is one non-transmissive area and there are a plurality of non-transmissive areas NTA in the display. A non-transmissive area NTA can be considered running as a row and there are several individual rows. Further, a non-transmissive area NTA can be considered running as a column and there are several individual columns that intersect with the rows of the other NTAs. Or, one non-transmissive area NTA can be considered as the area that surrounds a single transmissive area TA and it can be viewed that the respective non-transmissive areas NTA abut each other. In this regard, there are a plurality of non-transmissive areas, for which is some embodiments, each of them abut, or in some instances, intersect with, another non-transmissive area NTA. 
     The gate lines GL may be extended in a first direction (X axis direction), and may cross the pixel power lines VDDL, the common power lines VSSL and the data lines in the display area DA. 
     The pixel power lines VDDL, the common power lines VSSL, the reference lines and the data lines may be extended in a second direction (Y axis direction). In some embodiments, the pixel power lines VDDL and the common power lines VSSL may alternately be disposed in the display area DA. The transmissive area TA may be disposed between the pixel power line VDDL and the common power line VSSL. 
     The pixels P emit predetermined light to display an image. An emission area EA may correspond to an area, from which light emits, in the pixel P. 
     Each of the pixels P may include a first subpixel P 1 , a second subpixel P 2 , and a third subpixel P 3 . The first subpixel P 1  may be provided to include a first emission area EA 1  emitting green light, the second subpixel P 2  may be provided to include a second emission area EA 2  emitting red light, and the third subpixel P 3  may be provided to include a third emission area EA 3  emitting blue light, but these subpixel are not limited thereto. Each of the pixels P may further include a subpixel emitting white light W. An arrangement sequence of the subpixel P 1 , P 2  and P 3  may be changed in various ways. 
     Hereinafter, for convenience of description, a description will be given based on that the first subpixel P 1  is a green subpixel emitting green light, the second subpixel P 2  is a red subpixel emitting red light, and the third subpixel P 3  is a blue subpixel emitting blue light. 
     Each of the first subpixel P 1  and the third subpixel P 3  may be disposed to overlap any one of a first overlapping area IA 1  where the common power line VSSL and the gate line GL cross each other and a second overlapping area IA 2  where the pixel power line VDDL and the gate line GL cross each other. 
     For example, the first subpixel P 1 , as shown in  FIG. 3 , may be disposed to overlap the first overlapping area IA 1  where the common power line VSSL and the gate line GL cross each other, but is not limited thereto. The third subpixel P 3  may be disposed to overlap the second overlapping area IA 2  where the pixel power line VDDL and the gate line GL cross each other, but is not limited thereto. The first subpixel P 1  may be disposed to overlap the second overlapping area IA 2 , and the third subpixel P 3  may be disposed to overlap the first overlapping area IA 1 . Also, the first subpixel P 1  and the s third subpixel 
     P 3  may be disposed alternately along the common power line VSSL, or may be disposed alternately along the pixel power line VDDL. 
     The second subpixel P 2  may be disposed between the first overlapping area IA 1  and the second overlapping area IA 2 . For example, the second subpixel P 2  may be disposed between the first subpixel P 1  and the third subpixel P 3 . In some embodiments, the second subpixel P 2  may be overlapped with the gate line GL. 
     Each of the first subpixel P 1 , the second subpixel P 2  and the third subpixel P 3 , as shown in  FIG. 5 , may include a circuit element that includes a capacitor, a thin film transistor, etc., and a light emitting diode. The thin film transistor may include a switching transistor, a sensing transistor, and a driving transistor T. 
     The switching transistor is switched in accordance with a gate signal supplied to the gate line GL and serves to supply a data voltage supplied from the data line to the driving transistor T. 
     The sensing transistor serves to sense a threshold voltage deviation of the driving transistor T, which is a cause of image quality degradation. 
     The driving transistor T is switched in accordance with the data voltage supplied from the switching transistor to generate a data current from a power source supplied from the pixel power line VDDL, and serves to supply the generated data current to the anode electrode  120  of the pixel. 
     The driving transistor T includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. 
     In detail, the active layer ACT may be provided over the first substrate  111 . The active layer ACT may be formed of a silicon based semiconductor material or an oxide based semiconductor material. A buffer layer (not shown) may be provided between the active layer ACT and the first substrate  111 . 
     A gate insulating layer GI may be provided over the active layer ACT. The gate insulating layer GI may be formed an inorganic film, for example, a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a multi-layered film of SiOx and SiNx. 
     A gate electrode GE may be provided over the gate insulating layer GI. The gate electrode GE may be formed of a single layer or a multi-layer made of any one of Mo, Al, Cr, Au, Ti, Ni, Nd and Cu or their alloy. 
     A first inter-layer insulating layer ILD 1  and a second inter-layer insulating layer ILD 2  may be provided over the gate electrode GE. The first inter-layer insulating layer ILD 1  and the second inter-layer insulating layer ILD 2  may be formed an inorganic layer, for example, a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multi-layered layer of SiOx and SiNx. 
     In the transparent display panel  110  according to one embodiment of the present disclosure, insulating layers provided between the first substrate  110  and the anode electrode  120 , particularly some of inorganic layers may be provided in only the non-transmissive area, and may not be provided in the transmissive area TA. 
     In detail, the insulating layers provided between the first substrate  110  and the anode electrode  120  may include a gate insulating layer GI, a first inter-layer insulating layer IDL 1 , and a second inter-layer insulating layer ILD 2 . 
     Each of the gate insulating layer GI, the first inter-layer insulating layer ILD 1  and the second inter-layer insulating layer ILD 2  may be made of an inorganic layer such as a silicon oxide (SiOx) layer having a refractive index of 1.4 to 1.5 or a silicon nitride (SiNx) layer having a refractive index of 1.8 to 1.9. If a high refractive layer such as SiNx is formed in the transmissive area TA, externally incident light may be reflected from the high refractive layer, whereby light loss may occur. As a result, transmittance of the transparent display panel  110  may be reduced in the transmissive area TA. 
     The transparent display panel  110  according to one embodiment of the present disclosure may remove high refractive layers from the transmissive area TA to improve transmittance in the transmissive area TA. 
     At least one of the gate insulating layer GI, the first inter-layer insulating layer ILD 1  and the second inter-layer insulating layer ILD 2  may be formed of a silicon nitride (SiNx) layer. For example, the gate insulating layer GI may be formed of a silicon oxide (SiOx) layer, and the first inter-layer insulating layer ILD 1  and the second inter-layer insulating layer ILD 2  may be formed of silicon nitride (SiNx) layers. In this case, the first inter-layer insulating layer ILD 1  and the second inter-layer insulating layer ILD 2  may be provided in only the non-transmissive area NTA, and may not be provided in the transmissive area TA. 
     For another example, all of the gate insulating layer GI, the first inter-layer insulating layer ILD 1  and the second inter-layer insulating layer ILD 2  may be formed of silicon nitride (SiNx) layers. In this case, the gate insulating layer GI, the first inter-layer insulating layer ILD 1  and the second inter-layer insulating layer ILD 2  may be provided in only the non-transmissive area NTA, and may not be provided in the transmissive area TA. 
     For other example, only the second inter-layer insulating layer ILD 2  may be formed of silicon nitride (SiNx) layers. In this case, the second inter-layer insulating layer ILD 2  may be provided in only the non-transmissive area NTA, and may not be provided in the transmissive area TA. 
     The transparent display panel  110  according to one embodiment of the present disclosure may prevent external light from being lost in the transmissive area TA, whereby transmittance in the transmissive area may be improved. 
     Source and drain electrodes SE and DE may be provided over the second inter-layer insulating layer ILD 2 . One of the source and drain electrodes SE and DE may be connected to the active layer ACT through a second contact hole CH 2  that passes through the gate insulating layer GI and the first and second inter-layer insulating layers ILD 1  and ILD 2 . For example, the drain electrode DE may be connected to the active layer ACT through the second contact hole CH 2  that passes through the gate insulating layer GI and the first and second inter-layer insulating layers ILD 1  and ILD 2 . 
     The source and drain electrodes SE and DE may be formed of a single layer or a multi-layer made of any one of Mo, Al, Cr, Au, Ti, Ni, Nd and Cu or their alloy. 
     A first planarization layer PLN 1  may be provided over the source and drain electrodes SE and DE to planarize a step difference caused by the driving transistor T. The first planarization layer PLN 1  may be formed of an organic layer, for example, acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. 
     An anode auxiliary electrode  115  may be provided over the first planarization layer PLN 1 . The anode auxiliary electrode  115  may be connected to one of the source and drain electrodes SE and DE through a third contact hole CH 3  that passes through the first planarization layer PLN 1 . For example, the anode auxiliary electrode  115  may be connected to the drain electrode DE through the third contact hole CH 3  that passes through the first planarization layer PLN 1 . 
     The anode auxiliary electrode  115  may be formed of a single layer or a multi-layer made of any one of Mo, Al, Cr, Au, Ti, Ni, Nd and Cu or their alloy. 
     A second planarization layer PLN 2  may be formed over the anode auxiliary electrode  115 . The second planarization layer PLN 2  may be formed of an organic layer, for example, acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. 
     Light emitting diodes, which are comprised of the anode electrode  120 , a light emitting layer  130 , and a cathode electrode  140 , and a bank  125  are provided over the second planarization layer PLN 2 . 
     The anode electrode  120  may be provided over the second planarization layer PLN 2 , and may be connected with the driving transistor T. In detail, the anode electrode  120  may be connected to the anode auxiliary electrode  115  through a first contact hole CH 1  that passes through the second planarization layer PLN 2 . Since the anode auxiliary electrode  115  is connected to the source electrode SE or the drain electrode DE of the driving transistor T through the third contact hole CH 3 , the anode electrode  120  may electrically be connected with the driving transistor T. 
     The anode electrode  120  may be provided for each of the subpixels P 1 , P 2  and P 3 . In detail, one anode electrode  120  may be formed in the first subpixel P 1 , another anode electrode  120  may be formed in the second subpixel P 2 , and other anode electrode  120  may be formed in the third subpixel P 3 . The anode electrode  120  is not provided in the transmissive area TA. 
     The anode electrode  120  according to one embodiment of the present disclosure may include a first anode electrode  121 , a second anode electrode  122  and a third anode electrode  123 . 
     The first anode electrode  121  may be disposed over the common power line VSSL. In detail, the first anode electrode  121  may be disposed to overlap the first overlapping area IA 1  where the common power line VSSL and the gate line GL cross each other. 
     The first anode electrode  121  may be provided over the common power line VSSL in a plural number along the common power line VSSL. The subpixels provided with the plurality of first anode electrodes  121  may be at least one of the first subpixel P 1  and the third subpixel P 3 . For example, the subpixels provided with the plurality of first anode electrodes  121  may be the first subpixels P 1 . For another example, the subpixels provided with the plurality of first anode electrodes  121  may be the third subpixels P 3 . For other example, the subpixels provided with the plurality of first anode electrodes  121  may be the first subpixels P 1  and the third subpixels P 3 . In some embodiments, the first subpixels P 1  and the third subpixels P 3  may alternately be disposed over the common power line VSSL. 
     The third anode electrode  123  may be disposed over the pixel power line VDDL. In detail, the third anode electrode  123  may be disposed to overlap the second overlapping area IA 2  where the pixel power line VDDL and the gate line GL cross each other. 
     The third anode electrode  123  may be provided over the pixel power line VDDL in a plural number along the pixel power line VDDL. The subpixels provided with the plurality of third anode electrodes  123  may be at least one of the first subpixel P 1  and the third subpixel P 3 . For example, the subpixels provided with the plurality of third anode electrodes  123  may be the first subpixels P 1 . For another example, the subpixels provided with the plurality of third anode electrodes  123  may be the third subpixels P 3 . For other example, the subpixels provided with the plurality of third anode electrodes  123  may be the first subpixels P 1  and the third subpixels P 3 . In some embodiments, the first subpixels P 1  and the third subpixels P 3  may alternately be disposed over the pixel power line VDDL. 
     The second anode electrode  122  may be disposed between the first anode electrode  121  and the third anode electrode  123 . In detail, the second anode electrode  122  may be disposed over the gate line GL provided between the first overlapping area IA 1  and the second overlapping area IA 2 . 
     The first anode electrode  121  and the third anode electrode  123  may have shapes different from a shape of the second anode electrode  122 . 
     In detail, the first anode electrode  121 , as shown in  FIG. 8A , may include a first portion  121   a  and a second portion  121   b . In one embodiment, the first anode electrode  121  may further include a third portion  121   c.    
     The first portion  121   a  of the first anode electrode  121  may be disposed to overlap the first overlapping area IA 1  where the common power line VSSL and the gate line GL cross (or overlap) each other. For example, the first portion  121   a  of the first anode electrode  121 , as shown in  FIG. 8A , may have a rectangular shape but is not limited thereto. The first portion  121   a  of the first anode electrode  121  may be formed in various shapes such as a circle, a semi-circle, and a polygonal shape. 
     The first portion  121   a  of the first anode electrode  121  may be provided with a thin film transistor, such as a switching transistor, a sensing transistor, and a driving transistor T, and a capacitor therebelow. The first portion  121   a  of the first anode electrode  121  may have a width WA 1  that may at least partially or entirely cover the thin film transistor and the capacitor, which are provided therebelow. 
     The second portion  121   b  of the first anode electrode  121  may be protruded from one side S 1 - 1  of the first portion  121   a.  In some embodiments, the second portion  121   b  of the first anode electrode  121  may be disposed over the common power line VSSL. 
     That is, one side S 1 - 1  of the first portion  121   a  may correspond to a side crossing the common power line VSSL. The second portion  121   b  of the first anode electrode  121  may be protruded toward a direction where the common power line VSSL is extended, that is, a second direction (Y axis direction). 
     The second portion  121   b  of the first anode electrode  121  may include a first side S 2 - 1  facing the first portion  121   a,  and second side S 2 - 2  and third side S 2 - 3  connecting the first side S 2 - 1  with the first portion  121   a.    
     The second portion  121   b  of the first anode electrode  121  may have a width WA 2  at the first side S 2 - 1 , which is smaller than the width WA 1  of the first portion  121   a  of the first anode electrode  121 . The second portion  121   b  of the first anode electrode  121 , as shown in  FIG. 7 , may be provided with a plurality of metal lines therebelow, for example, a common power line VSSL, data lines DL 1  and DL 2 , and reference lines VREFL 1  and VREFL 2 . In some embodiments, the common power line VSSL, the data lines DL 1  and DL 2  and the reference lines VREFL 1  and VREFL 2  may be disposed in parallel in the same direction, that is, a second direction (Y axis direction) as shown in  FIG. 3 . Therefore, the second portion  121   b  of the first anode electrode  121  may at least partially or entirely cover the plurality of metal lines by the width WA 2  smaller than the width WA 1  of the first portion  121   a  of the first anode electrode  121 . 
     Meanwhile, the second portion  121   b  of the first anode electrode  121 , as shown in  FIG. 8A , may be provided with a first curved part CV 1  between the first side S 2 - 1  and the first portion  121   a.  In detail, the second portion  121   b  of the first anode electrode  121  may include second and third sides S 2 - 2  and S 2 - 3  connecting the first side S 2 - 1  with the first portion  121   a.  The second side S 2 - 2  of the second portion  121   b  of the first anode electrode  121  may include one first curved part CV 1  connected from one point to the first portion  121   a  by a curve. Also, the third side S 2 - 3  of the second portion  121   b  of the first anode electrode  121  may include another one first curved part CV 1  connected from one point to the first portion  121   a  by a curve. In some embodiments, the first curved part CV 1  may be recessed toward an inward direction. 
     The third portion  121   c  of the first anode electrode  121  may be protruded from the other side S 1 - 2  of the first portion  121   a.  In some embodiments, the third portion  121   c  of the first anode electrode  121  may be disposed over the common power line VSSL. That is, the other side S 1 - 2  of the first portion  121   a  may correspond to a side crossing the common power line VSSL and facing one side S 1 - 1 . The third portion  121   c  of the first anode electrode  121  may be protruded toward a direction where the common power line VSSL is extended, that is, a second direction (Y axis direction). 
     The third portion  121   c  of the first anode electrode  121  may include a first side S 3 - 1  facing the first portion  121   a,  and second side S 3 - 2  and third side S 3 - 3  connecting the first side S 3 - 1  with the first portion  121   a.    
     The third portion  121   c  of the first anode electrode  121  may have a width WA 3  at the first side S 3 - 1 , which is smaller than the width WA 1  of the first portion  121   a  of the first anode electrode  121 . The third portion  121   c  of the first anode electrode  121 , as shown in  FIG. 7 , may be provided with a plurality of metal lines therebelow, for example, a common power line VSSL, data lines DL 1  and DL 2 , and reference lines VREFL 1  and VREFL 2 . In some embodiments, the common power line VSSL, the data lines DL 1  and DL 2  and the reference lines VREFL 1  and VREFL 2  may be disposed in parallel in the same direction, that is, a second direction (Y axis direction). Therefore, the third portion  121   c  of the first anode electrode  121  may at least partially or entirely cover the plurality of metal lines by the width WA 2  smaller than the width WA 1  of the first portion  121   a  of the first anode electrode  121 . 
     In the third portion  121   c  of the first anode electrode  121 , the width WA 3  at the first side S 3 - 1  may be equal (or substantially equal) to the width WA 2  of the second portion  121   b  of the first anode electrode  121 . The third portion  121   c  of the first anode electrode  121  and the second portion  121   b  of the first anode electrode  121  may have symmetric shapes by interposing the first portion  121   a  of the first anode electrode  121 . 
     Meanwhile, the third portion  121   c  of the first anode electrode  121 , as shown in  FIG. 8A , may be provided with a first curved part CV 1  between the first side S 3 - 1  and the first portion  121   a.  In detail, the third portion  121   c  of the first anode electrode  121  may include second and third sides S 3 - 2  and S 3 - 3  connecting the first side S 3 - 1  with the first portion  121   a.  The second side S 3 - 2  of the third portion  121   c  of the first anode electrode  121  may include one first curved part CV 1  connected from one point to the first portion  121   a  by a curve. Also, the third side S 3 - 3  of the third portion  121   c  of the first anode electrode  121  may include another one first curved part CV 1  connected from one point to the first portion  121   a  by a curve. In some embodiments, the curved part CV may be recessed toward an inward direction. 
     The third anode electrode  123 , as shown in  FIG. 8A , may include a first portion  123   a  and a second portion  123   b.  In one embodiment, the third anode electrode  123  may further include a third portion  123   c.    
     The first portion  123   a  of the third anode electrode  123  may be disposed to overlap the second overlapping area IA 2  where the pixel power line VDDL and the gate line GL cross (or overlap) each other. For example, the first portion  123   a  of the third anode electrode  123 , as shown in  FIG. 8A , may have a rectangular shape but is not limited thereto. The first portion  123   a  of the third anode electrode  123  may be formed in various shapes such as a circle, a semi-circle, and a polygonal shape. 
     The first portion  123   a  of the third anode electrode  123  may be provided with a thin film transistor, such as a switching transistor, a sensing transistor, and a driving transistor T, and a capacitor therebelow. The first portion  123   a  of the third anode electrode  123  may have a width WA 1  that may at least partially or entirely cover the thin film transistor and the capacitor, which are provided therebelow. 
     The second portion  123   b  of the third anode electrode  123  may be protruded from one side S 1 - 1  of the first portion  123   a.  In some embodiments, the second portion  123   b  of the third anode electrode  123  may be disposed over the pixel power line VDDL. 
     That is, one side S 1 - 1  of the first portion  123   a  may correspond to a side crossing the pixel power line VDDL. The second portion  123   b  of the third anode electrode  123  may be protruded toward a direction where the pixel power line VDDL is extended, that is, a second direction (Y axis direction). 
     The second portion  123   b  of the third anode electrode  123  may include a first side S 2 - 1  facing the first portion  123   a,  and second side S 2 - 2  and third side S 2 - 3  connecting the first side S 2 - 1  with the first portion  123   a.    
     The second portion  123   b  of the third anode electrode  123  may have a width WA 2  at the first side S 2 - 1 , which is smaller than the width WA 1  of the first portion  123   a  of the third anode electrode  123 . The second portion  123   b  of the third anode electrode  123  may be provided with a plurality of metal lines therebelow, for example, a pixel power line VDDL, data lines DL 1  and DL 2 , and reference lines VREFL 1  and VREFL 2 . In some embodiments, the pixel power line VDDL, the data lines DL 1  and DL 2  and the reference lines VREFL 1  and VREFL 2  may be disposed in parallel in the same direction, that is, a second direction (Y axis direction) as shown in  FIG. 3 . Therefore, the second portion  123   b  of the third anode electrode  123  may at least partially or entirely cover the plurality of metal lines by the width WA 2  smaller than the width WA 1  of the first portion  123   a  of the third anode electrode  123 . 
     Meanwhile, the second portion  123   b  of the third anode electrode  123 , as shown in  FIG. 8A , may be provided with a first curved part CV 1  between the first side S 2 - 1  and the first portion  123   a.  In detail, the second portion  123   b  of the third anode electrode  123  may include second and third sides S 2 - 2  and S 2 - 3  connecting the first side S 2 - 1  with the first portion  123   a.  The second side S 2 - 2  of the second portion  123   b  of the third anode electrode  123  may include one first curved part CV 1  connected from one point to the first portion  123   a  by a curve. Also, the third side S 2 - 3  of the second portion  123   b  of the third anode electrode  123  may include another one first curved part CV 1  connected from one point to the first portion  123   a  by a curve. In some embodiments, the curved part CV may be recessed toward an inward direction. 
     The third portion  123   c  of the third anode electrode  123  may be protruded from the other side S 1 - 2  of the first portion  123   a.  In some embodiments, the third portion  123   c  of the third anode electrode  123  may be disposed over the pixel power line VDDL. That is, the other side S 1 - 2  of the first portion  123   a  may correspond to a side crossing the pixel power line VDDL and facing one side S 1 - 1 . The third portion  123   c  of the third anode electrode  123  may be protruded toward a direction where the pixel power line VDDL is extended, that is, a second direction (Y axis direction). 
     The third portion  123   c  of the third anode electrode  123  may include a first side S 3 - 1  facing the first portion  123   a,  and second side S 3 - 2  and third side S 3 - 3  connecting the first side S 3 - 1  with the first portion  123   a.    
     The third portion  123   c  of the third anode electrode  123  may have a width 
     WA 3  at the first side S 3 - 1 , which is smaller than the width WA 1  of the first portion  123   a  of the third anode electrode  123 . The third portion  123   c  of the third anode electrode  123  may be provided with a plurality of metal lines therebelow, for example, a pixel power line VDDL, data lines DL 1  and DL 2 , and reference lines VREFL 1  and VREFL 2 . In some embodiments, the pixel power line VDDL, the data lines DL 1  and DL 2  and the reference lines VREFL 1  and VREFL 2  may be disposed in parallel in the same direction, that is, a second direction (Y axis direction). Therefore, the third portion  123   c  of the third anode electrode  123  may at least partially or entirely cover the plurality of metal lines by the width WA 2  smaller than the width WA 1  of the first portion  123   a  of the third anode electrode  123 . 
     In the third portion  123   c  of the third anode electrode  123 , the width WA 3  at the first side S 3 - 1  may be equal (or substantially equal) to the width WA 2  of the second portion  123   b  of the third anode electrode  123 . The third portion  123   c  of the third anode electrode  123  and the second portion  123   b  of the third anode electrode  123  may have symmetric shapes by interposing the first portion  123   a  of the third anode electrode  123 . 
     Meanwhile, the third portion  123   c  of the third anode electrode  123 , as shown in  FIG. 8A , may be provided with a first curved part CV 1  between the first side S 3 - 1  and the first portion  123   a.  In detail, the third portion  123   c  of the third anode electrode  123  may include second and third sides S 3 - 2  and S 3 - 3  connecting the first side S 3 - 1  with the first portion  123   a.  The second side S 3 - 2  of the third portion  123   c  of the third anode electrode  123  may include one first curved part CV 1  connected from one point to the first portion  123   a  by a curve. Also, the third side S 3 - 3  of the third portion  123   c  of the third anode electrode  123  may include another one first curved part CV 1  connected from one point to the first portion  123   a  by a curve. In some embodiments, the first curved part CV 1  may be recessed toward an inward direction. 
     Meanwhile, the second anode electrode  122 , as shown in  FIG. 8B , may be provided with the first portion  122   a  only. The first portion  122   a  of the second anode electrode  122 , as shown in  FIG. 8B , may have a rectangular shape but is not limited thereto. The first portion  122   a  of the second anode electrode  122  may be formed in various shapes such as a circle, a semi-circle, and a polygonal shape. 
     The first portion  122   a  of the second anode electrode  122  may be provided with a thin film transistor, such as a switching transistor, a sensing transistor and a driving transistor T, and a capacitor therebelow. The first portion  122   a  of the second anode electrode  122  may have a width WA 4  that may cover the thin film transistor and the capacitor, which are provided therebelow. The width WA 4  of the first portion  122   a  of the second anode electrode  122  may be smaller than the width WA 1  of the first portions  121   a  and  123   a  of the first and third anode electrodes  121  and  123  but is not limited thereto. The width WA 4  of the first portion  122   a  of the second anode electrode  122  may be equal to the width WA 1  of the first portions  121   a  and  123   a  of the first and third anode electrodes  121  and  123 . 
     Meanwhile, the second anode electrode  122  does not include a portion protruded from the first portion  122   a  unlike the first anode electrode  121  and the third anode electrode  123 . The second anode electrode  122  is overlapped with the gate line GL extended in the first direction (X axis direction), and is not overlapped with the common power line VSSL or the pixel power line VDDL extended in the second direction (Y axis direction). Therefore, if the portion protruded from the first portion  122   a  to the second direction (Y axis direction) is formed in the second anode electrode  122 , the non-transmissive area NTA is required, and an area of the transmissive area TA may be reduced. Therefore, the second anode electrode  122  may preferably be made of the first portion  122   a  only. 
     Consequently, the second anode electrode  122  may have an area smaller than those of the first anode electrode  121  and the third anode electrode  123 . Therefore, the second subpixel P 2  provided with the second anode electrode  122  may have a light emission area smaller than those of the first subpixel P 1  and the third subpixel P 3  provided with the first anode electrode  121  or the third anode electrode  123 . The second subpixel P 2  may be a red subpixel emitting red light. Generally, since the red subpixel has lifetime more excellent than a green subpixel and a blue subpixel, even though the red subpixel is formed with a small area, lifetime of the transparent display panel  110  may not be reduced. 
     In the transparent display panel  110  according to one embodiment of the present disclosure, the first anode electrode  121  and the third anode electrode  123  may include first portions  121   a  and  123   a,  and second portions  121   b  and  123   b  and third portions  121   c  and  123   c  protruded from the first portions  121   a  and  123   a  in the second direction (Y axis direction). 
     In some embodiments, the second portions  121   b  and  123   b  and the third portions  121   c  and  123   c  may cover the plurality of metal lines provided therebelow and extended in the second direction (Y axis direction). In some embodiments, the plurality of metal lines may include a power line PL such as the common power line VSSL or the pixel power line VDDL, data lines DL 1  and DL 2 , and reference lines VREFL 1  and VREFL 2 . The data lines DL 1  and DL 2  and the reference lines VREFL 1  and VREFL 2 , as shown in  FIG. 7 , may be disposed to be spaced apart from each other in the same layer. For example, the data lines DL 1  and DL 2  and the reference lines VREFL 1  and VREFL 2  may be disposed to be spaced apart from the source electrode SE and the drain electrode DE of the driving transistor T in the same layer. The common power line VSSL or the pixel power line VDDL may be disposed in the same layer as the anode auxiliary electrode  115 . 
     If these metal lines are disposed in parallel to be spaced apart from one another, a slit, specifically a linear or rectangular shape may be formed between the metal lines. If external light passes through the slit, diffraction may occur. 
     Diffraction may mean that interference occurs in spherical waves after plane waves are changed to the spherical waves as light passes through the slit. Therefore, as interpolation interference and destructive interference occur in the spherical waves, the external light that has passed through the slit may have irregular light intensity. As a result, definition of an object or image arranged at an opposite side of the transparent display panel  110  may be reduced. 
     In the transparent display panel  110  according to one embodiment of the present disclosure, the second portions  121   b  and  123   b  and the third portions  121   c  and  123   c  protruded from the first portions  121   a  and  123   a  in the second direction (Y axis direction) may be formed in the first anode electrode  121  and the third anode electrode  123  to cover the plurality of metal lines provided below the first anode electrode  121  and the third anode electrode  123  if possible. Therefore, the transparent display panel  110  according to one embodiment of the present disclosure may prevent diffraction from occurring due to the plurality of metal lines. 
     Moreover, the transparent display panel  110  according to one embodiment of the present disclosure may increase an area of an emission area EA by forming the second portions  121   b  and  123   b  and the third portions  121   c  and  123   c  in the first anode electrode  121  and the third anode electrode  123 . 
     Also, In the transparent display panel  110  according to one embodiment of the present disclosure, the second portions  121   b  and  123   b  and the third portions  121   c  and  123   c  of the first anode electrode  121  and the third anode electrode  123  may have minimum widths WA 2  and WA 3  that may cover the plurality of metal lines. 
     In one embodiment, the second portions  121   b  and  123   b  and the third portions  121   c  and  123   c  of the first anode electrode  121  and the third anode electrode  123 , as shown in  FIG. 7 , may have ends on a plane position, which are equal to an end of the outermost line of a plurality of signal lines provided therebelow. In some embodiments, the plurality of signal lines may include a power line PL such as the common power line VSSL or the pixel power line VDDL, data lines DL 1  and DL 2 , and reference lines VREFL 1  and VREFL 2 . 
     For example, the second portions  121   b  and  123   b  and the third portions  121   c  and  123   c  of the first anode electrode  121  and the third anode electrode  123 , as shown in  FIG. 7 , may have one ends on a plane position, which are equal to an end of the first data line DL 1  disposed at the outermost. Also, the second portions  121   b  and  123   b  and the third portions  121   c  and  123   c  of the first anode electrode  121  and the third anode electrode  123 , as shown in  FIG. 7 , may have the other ends on a plane position, which are equal to an end of the second data line DL 2  disposed at the outermost. 
     Also, the first portions  121   a,    122   a  and  123   a  of the first anode electrode  121 , the second anode electrode  122  and the third anode electrode  123  may have a minimum width that may cover the plurality of metal lines. 
     In detail, the first portions  121   a,    122   a  and  123   a  of the first anode electrode  121 , the second anode electrode  122  and the third anode electrode  123  may be provided with a plurality of circuit elements therebelow. Each of the plurality of circuit elements may include a plurality of signal lines SL extended from a layer the same as any one of the gate electrode GE, the source electrode SE, the drain electrode DE, and the anode auxiliary electrode  115  of the driving transistor T. The first portions  121   a,    122   a  and  123   a  of the first anode electrode  121 , the second anode electrode  122  and the third anode electrode  123 , as shown in  FIG. 6 , may have ends on a plane position, which are equal to an end of the outermost line of the plurality of signal lines provided therebelow. Therefore, the transparent display panel  110  according to one embodiment of the present disclosure may make sure of a maximum area of the transmissive area TA, and may improve transmittance. 
     The first anode electrode  121 , the second anode electrode  122  and the third anode electrode  123  may be formed of a metal material of high reflectivity such as a deposited structure (Ti /Al/Ti) of aluminum and titanium, a deposited structure (ITO/Al/ITO) of aluminum and ITO, an Ag alloy and a deposited structure (ITO/Ag alloy/ITO) of Ag alloy and ITO. The Ag alloy may be an alloy of silver (Ag), palladium (Pb), and Copper (Cu). 
     A bank  125  may be provided over a second planarization layer PLN 2 . Also, the bank  125  may be provided among the anode electrodes  120 . In detail, the bank  125  may be provided among the first anode electrode  121 , the second anode electrode  122  and the third anode electrode  123 , which are disposed to adjoin one another in the first direction (X axis direction). Also, the bank  125  may be provided among a plurality of first anode electrodes  121  disposed over the common power line VSSL along the second direction (Y axis direction). Also, the bank  125  may be provided among a plurality of third anode electrodes  123  disposed over the pixel power line VDDL along the second direction (Y axis direction). 
     The bank  125  may be formed to cover each edge of the first anode electrode  121 , the second anode electrode  122  and the third anode electrode  123  and partially expose each of the first anode electrode  121 , the second anode electrode  122  and the third anode electrode  123 . Therefore, the bank  125  may prevent light emitting efficiency from being deteriorated due to a current concentrated on the ends of the first anode electrode  121 , the second anode electrode  122  and the third anode electrode  123 . The bank  125  may be provided in only the non-transmissive area NTA, and may not be provided in the transmissive area TA. 
     The bank  125  may respectively define emission areas EA 1 , EA 2 , and EA 3  of the subpixels P 1 , P 2  and P 3 . Each of the emission areas EA 1 , EA 2  and EA 3  of the subpixels P 1 , P 2  and P 3  indicates an area where the anode electrode  120 , the light emitting layer  130  and the cathode electrode  140  are sequentially deposited and then holes from the anode electrode  120  and electrons from the cathode electrode  140  are combined with each other in the light emitting layer  130  to emit light. In this case, the area where the bank  125  is not formed and the anode electrode  120  is exposed may be an emission area EA, and the other area may be a non-emission area NEA. 
     The bank  125  may be provided in only the non-transmissive area NTA, and may not be provided in the transmissive area TA. The bank  125  may have a yellowish color due to its material characteristic. In the transparent display panel  110  according to one embodiment of the present disclosure, as the bank  125  is not formed in the transmissive area TA, yellowish phenomenon in the transmissive area TA may be prevented from occurring. 
     Meanwhile, the bank  125  may have an end different from that of at least one insulating layer provided between the anode electrode  120  and the first substrate  111 . In detail, in the transparent display panel  110  according to one embodiment of the present disclosure, the bank  125  may be provided in only the non-transmissive area NTA, and may not be provided in the transmissive area TA. Also, in the transparent display panel  110  according to one embodiment of the present disclosure, at least one of the insulating layers provided between the anode electrode  120  and the first substrate  111  may be formed in only the non-transmissive area NTA, and may not be provided in the transmissive area TA. At least one of the insulating layers may include a gate insulating layer GI, a first inter-layer insulating layer ILD 1  and a second inter-layer insulating layer ILD 2 . 
     A distance d 2  between the transmissive area TA and the end of the bank  125  may be longer than a distance d 1  between the transmissive area TA and at least one insulating layer, for example, an end of each the first inter-layer insulating layer ILD 1  and the second inter-layer insulating layer ILD 2 . That is, the end of at least one insulating layer may be formed to be closer to the transmissive area TA than the end of the bank  125 . 
     The bank  125  may partially be overlapped with the transmissive area TA due to a process error. Since the bank  125  has a yellowish color, the transparent display panel  110  may have a yellowish color in the transmissive area TA where the bank  125  is provided, and a user may recognize this. 
     In the transparent display panel  110  according to one embodiment of the present disclosure, even though a process error occurs, the distance d 2  between the transmissive area TA and the end of the bank  125  may be formed sufficiently such that the bank  125  may not be overlapped with the transmissive area TA. 
     Meanwhile, at least one insulating layer provided between the anode electrode  120  and the first substrate  111  may have a sufficient area to protect the circuit elements provided in the non-transmissive area NTA, for example, the driving transistor T. The at least one insulating layer may be formed to cover the area where the circuit elements are formed. Moreover, the at least one insulating layer may be formed at a position where its end is spaced apart from the area where the driving transistor T is formed at a sufficient distance, to improve reliability of the circuit elements. Therefore, the distance dl between the transmissive area TA and the end of the at least one insulating layer may be shorter than the distance d 2  between the transmissive area TA and the end of the bank  125 . 
     Meanwhile,  FIG. 7  shows that the distance dl between the transmissive area TA and the end of the at least one insulating layer is longer than  0 , but is not limited thereto. The distance dl between the transmissive area TA and the end of the at least one insulating layer may be  0 . 
     If at least one insulating layer provided between the anode electrode  120  and the first substrate  111  includes a plurality of insulating layers, the plurality of insulating layers, as shown in  FIG. 7 , may have the same ends but are not limited thereto. 
     The plurality of insulating layers may have ends different from one another. For example, the first inter-layer insulating layer ILD 1  and the second inter-layer insulating layer ILD 2  may not be provided in the transmissive area TA. In this case, a distance between the transmissive area TA and the end of the first inter-layer insulating layer ILD 1  may be shorter than a distance between the transmissive area TA and the end of the second inter-layer insulating layer ILD 2 . That is, the first inter-layer insulating layer ILD 1  and the second inter-layer insulating layer ILD 2  may have a stair type deposited structure. The stair type deposited structure may reduce a step difference, whereby a surface gap may be prevented from occurring in the first planarization layer PLN 1  formed above the insulating films. 
     The bank  125  may be formed of an organic layer, for example, acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. 
     The organic light emitting layer  130  may be provided over the anode electrode  120 . The organic light emitting layer  130  may include a hole transporting layer, a light emitting layer, and an electron transporting layer. In this case, if a voltage is applied to the anode electrode  120  and the cathode electrode  140 , holes and electrons move to the light emitting layer through the hole transporting layer and the electron transporting layer, respectively, and are combined with each other in the light emitting layer to emit light. 
     The organic light emitting layer  130 , as shown in  FIG. 5 , may include light emitting layers each of which is formed for each of the subpixels P 1 , P 2  and P 3 . For example, a green light emitting layer  131  emitting green light may be formed in the first subpixel P 1 , a red light emitting layer  132  emitting red light may be formed in the second subpixel P 2 , and a blue light emitting layer  133  emitting blue light may be formed in the third subpixel P 3 . In this case, the light emitting layers of the organic light emitting layer  130  are not formed in the transmissive area TA. 
     The cathode electrode  140  may be provided over the organic light emitting layer  130  and the bank  125 . The cathode electrode  140  may be provided in the transmissive area TA as well as the non-transmissive area NTA that includes the emission area EA, but is not limited thereto. The cathode electrode  140  may be provided in only the non-transmissive area NTA that includes the emission area EA, and may not be provided in the transmissive area TA to improve transmittance. 
     The cathode electrode  140  may be a common layer commonly formed for the subpixels P 1 , P 2  and P 3  to apply the same voltage to the subpixels P 1 , P 2  and P 3 . The cathode electrode  140  may be formed of a transparent conductive material (TCO) such as ITO and IZO, which can transmit light, or may be formed of a semi-transmissive conductive material such as Mg, Ag, or alloy of Mg and Ag. If the cathode electrode  140  is formed of a semi-transmissive conductive material, emission efficiency may be enhanced by micro cavity. 
     An encapsulation layer  150  may be provided over the light emitting diodes. The encapsulation layer  150  may be formed over the cathode electrode  140  to overlay the cathode electrode  140 . The encapsulation layer  150  serves to prevent oxygen or water from being permeated into the organic light emitting layer  130  and the cathode electrode  140 . Accordingly, in some embodiments, the encapsulation layer  150  may include at least one inorganic film and at least one organic film. 
     Meanwhile, although not shown in  FIG. 5 , a capping layer may additionally be formed between the cathode electrode  140  and the encapsulation layer  150 . 
     A color filter layer  170  may be provided over the encapsulation layer  150 . The color filter layer  170  may be provided over one surface of the second substrate  112  that faces the first substrate  111 . In this case, the first substrate  111  provided with the encapsulation layer  150  and the second substrate  112  provided with the color filter layer  170  may be bonded to each other by an adhesive layer  160 . In some embodiments, the adhesive layer  160  may be an optically clear resin (OCR) layer or an optically clear adhesive (OCA) film. 
     The color filter layer  170  may be formed to be patterned for each of the subpixels P 1 , P 2  and P 3 . In detail, the color filter layer  170  may include a first color filter CF 1 , a second color filter CF 2 , and a third color filter CF 3 . The first color filter CF 1  may be disposed to correspond to the emission area EA 1  of the first subpixel P 1 , and may be a green color filter that transmits green light. The second color filter CF 2  may be disposed to correspond to the emission area EA 2  of the second subpixel P 2 , and may be a red color filter that transmits red light. The third color filter CF 3  may be disposed to correspond to the emission area EA 3  of the third subpixel P 3 , and may be a blue color filter that transmits blue light. 
     The transparent display panel  110  according to one embodiment of the present disclosure is characterized in that a polarizer is not used, and the color filter layer  170  is formed in the second substrate  112 . If the polarizer is attached to the transparent display panel  110 , transmittance of the transparent display panel  110  is reduced by the polarizer. Meanwhile, if the polarizer is not attached to the transparent display panel  110 , a problem occurs in that externally incident light is reflected towards the electrodes. 
     Since a polarizer is not attached to the transparent display panel  110  according to one embodiment of the present disclosure, transmittance may be prevented from being reduced. Also, in the transparent display panel  110  according to one embodiment of the present disclosure, the color filter layer  170  may be formed in the second substrate  112  to partially absorb externally incident light, thereby preventing the incident light from being reflected toward the electrodes. That is, the transparent display panel  110  according to one embodiment of the present disclosure may reduce external light reflectivity without reducing transmittance. 
     Meanwhile, a black matrix BM may be provided among the color filters CF 1 , CF 2  and CF 3 . The black matrix BM may be provided among the subpixels P 1 , P 2  and P 3  to prevent color mixture among the adjacent subpixels P 1 , P 2  and P 3  from occurring. Also, the black matrix BM may prevent externally incident light from being reflected toward a plurality of lines provided among the subpixels P 1 , P 2  and P 3 , for example, the gate lines, the data lines, the pixel power lines, the common power lines, the reference lines, etc. 
     The black matrix BM may include a material that absorbs light, for example, a black dye that absorbs light of a visible light wavelength range. 
     A color filter layer  170  may define the non-transmissive area NTA in the display area DA. In detail, an area where color filters CF 1 , CF 2  and CF 3  and a black matrix BM are provided may be the non-transmissive area NTA, and the other area may be the transmissive area TA. 
     In the transparent display panel  110  according to one embodiment of the present disclosure, as shown in  FIGS. 9A to 9E , the transmissive area TA may have a rounded polygonal shape. In detail, the transmissive area TA may be provided with a plurality of second curved parts CV 2 . When considered in this regard, each transmissive area TA is as one of a plurality of transmissive areas. There are thus a plurality of transmissive areas TA, each of which is surrounded by a non-transmissive area NTA 
     Each of the plurality of second curved parts CV 2  provided in the each respective transmissive areas TA may have a shape corresponding to the plurality of first curved parts CV 1  provided in the first and third anode electrodes  121  and  123  but is not limited thereto. The shape of each of the plurality of second curved parts CV 2  may be determined by the color filter layer  170  and thus is not always the same as that of each of the plurality of first curved parts CV 1  provided in the first and third anode electrodes  121  and  123 . The plurality of second curved parts CV 2  provided in the transmissive area TA and the plurality of first curved parts CV 1  provided in the first and third anode electrodes  121  and  123  may have the same curvature, or may have their respective curvatures different from each other. 
     Meanwhile, the non-transmissive area NTA may have a linear or rectangular shape longitudinally extended in the first direction (X axis direction), or may have a linear or rectangular shape longitudinally extended in the second direction (Y axis direction). The plurality of non-transmissive areas NTA having a linear shape (or rectangular shape) may be disposed in parallel at a predetermined interval. The non-transmissive areas NTA can be considered as individual areas that abut each other. In this respect, there are a plurality of individual non-transmissive areas NTA. 
     The transmissive areas TA may be disposed among the plurality of non-transmissive areas NTA spaced apart from one another at a constant interval. In this case, the transmissive area TA may be a slit having periodicity among the non-transmissive areas NTA of a linear shape (or rectangular shape). If externally incident light passes through periodic slits, periodic diffraction may occur. 
     In detail, the transmissive area TA may be provided among the non-transmissive areas NTA having a linear shape (or rectangular shape) longitudinally extended in the first direction (X axis direction), or may be provided among the non-transmissive areas NTA having a linear shape (or rectangular shape) longitudinally extended in the second direction (Y axis direction). That is, the transmissive area TA may have a rectangular shape. 
     In this case, the externally incident light may cause periodic diffraction in each of the first direction (X axis direction) and the second direction (Y axis direction). Therefore, a diffractive pattern orthogonal in the first direction (X axis direction) and the second direction (Y axis direction) may be formed. The diffractive pattern may allow light to be concentrated on the first direction (X axis direction) and the second direction (Y axis direction) and may have irregular light intensity. As a result, definition of an object or image arranged at an opposite side of the transparent display panel  110  may be reduced. 
     In the transparent display panel  110  according to one embodiment of the present disclosure, the second curved part CV 2  may be formed in the transmissive area TA, whereby light concentration on a specific direction may be reduced. 
     The transmissive area, as shown in  FIG. 9A , may have a rectangular shape, and may be provided with a second curved part CV 2  at four corners. The transmissive area TA may be provided with the second curved part CV 2  of four corners, and may include four straight parts ST connecting the second curved parts CV 2 . The four straight parts ST may be disposed to be parallel with their facing straight part ST. If external light passes through the straight parts ST, light may be concentrated on specific directions, for example, the first direction (X axis direction) and the second direction (Y axis direction), whereby an orthogonal diffractive pattern may be formed. On the other hand, four second curved parts CV 2  are not parallel with their facing second curved part CV 2 . If external light passes through the second curved part CV 2 , light is not concentrated on a specific direction, and a diffractive pattern may be formed along the second curved part CV 2 . As a result, the transparent display panel  110  may reduce light concentration on a specific direction by using the second curved part CV 2 . 
     Meanwhile, the transmissive area, as shown in  FIG. 9B , may increase a ratio of the second curved parts CV 2  occupied at corners by reducing a length of each of the four straight parts ST and forming each of the four second curved parts CV 2  to have a long length. Alternatively, the transmissive area, as shown in  FIG. 9C , may increase a ratio of the second curved parts CV 2  occupied at corners by forming the second curved parts CV 2  more than 4. 
     The transmissive area TA shown in  FIGS. 9B and 9C  may more reduce diffraction than the transmissive area shown in  FIG. 9A , but has a problem in that an area of the transmissive area TA is reduced. The lengths of the second curved part CV 2  and the straight part ST may be determined considering transmittance of the transmissive area TA. 
     Meanwhile, the transmissive area TA, as shown in  FIG. 9D , may be disposed in an oblique direction. If the transmissive areas TA are disposed in parallel along the first direction or the second direction, a diffractive pattern of the first direction and a diffractive pattern of the second direction may be formed longitudinally. Also, as light of the transmissive area TA is overlapped with another light of another transmissive area TA, light intensity may be more enhanced. As the transmissive area TA is disposed in an oblique direction, a long and definite diffractive pattern may be prevented from being formed. 
     Also, the second curved part CV 2  of the transmissive area TA may be formed of a curve as shown in  FIGS. 9A to 9D , but is not limited thereto. The second curved part CV 2  of the transmissive area TA may be formed of a plurality of oblique lines as shown in  FIG. 9E . 
     Referring to  FIG. 2  again, the non-display area NDA may be provided with a pad area PA in which pads PAD are disposed, and at least one gate driver  205 . 
     In detail, the non-display area NDA may include a first non-display area NDA 1  in which the pads PAD are disposed, a second non-display area NDA 2  disposed in parallel with the first non-display area NDA 1  by interposing the display area DA, and third and fourth non-display areas NDA 3  and NDA 4  connecting the first non-display area NDA 1  with the second non-display area NDA 2 . 
     The gate driver  205  is connected to the gate lines GL and supplies gate signals to the gate lines GL. The gate driver  205  may be disposed in at least one of the fourth non-display area NDA 4  and the third non-display area NDA 3  in a gate drive in panel (GIP) type. For example, as shown in  FIG. 2 , the gate driver  205  may be formed in the fourth non-display area NDA 4 , and another gate driver  205  may be formed in the third non-display area NDA 3 , but is not limited thereto. The gate driver  205  may be formed in any one of the fourth non-display area NDA 4  and the third non-display area NDA 3 . 
     The pads PAD may include a first pad VDDP, a second pad VSSP, a third pad VREFP, and a fourth pad DP, and may be provided in the first non-display area NDA 1 . That is, the first non-display area NDA 1  may include a pad area PA. 
     In the transparent display panel  110  according to one embodiment of the present disclosure, a plurality of circuits and a plurality of metal lines may be disposed in the non-display area NDA, particularly the first non-display area NDA 1  and the second non-display area NDA 2 . The plurality of circuits may include electrostatic prevention circuits and multiplex circuits disposed in the first non-display area NDA 1 . 
     For example, the electrostatic prevention circuits may be circuits for preventing static electricity from entering the transparent display panel  110  or occurring in the transparent display panel  110 . The electrostatic prevention circuits may be provided in the first non-display area NDA 1 . In detail, the electrostatic prevention circuits, as shown in  FIG. 5 , may be disposed in an area ESDA between the reference line VREF 1  and the common power line VSS 1  provided in the first non-display area NDA 1 . 
     For example, each of the multiplex circuits may be a circuit for driving the plurality of data lines time-divisionally. The multiplex circuits may be disposed over the first non-display area NDA 1 . In detail, the multiplex circuits, may be disposed in an area MUXA between the display area DA and the common power line VSS 1  provided in the first non-display area NDA 1 . 
     The transparent display panel  110  according to one embodiment of the present disclosure may include a plurality of signal lines connected with the subpixels P 1 , P 2  and P 3  provided in the display area DA. For example, the transparent display panel  110  according to one embodiment of the present disclosure may include a pixel power line VDD, a common power line VSS and a reference line VREF. 
     The pixel power line VDD may supply a first power source to the driving transistor T of each of the subpixels P 1 , P 2  and P 3  provided in the display area DA. 
     Accordingly, in some embodiments, the pixel power line VDD may include a first pixel power line VDD 1  provided in a first non-display area NDA 1 , a second pixel power line VDD 2  provided in a second non-display area NDA 2 , and a plurality of third pixel power lines VDDL connecting the first pixel power line VDD 1  with the second pixel power line VDD 2 . 
     The common power line VSS may supply a second power source to the cathode electrode  140  of the subpixels P 1 , P 2  and P 3  provided in the display area DA. In some embodiments, the second power source may be a common power source commonly supplied to the subpixels P 1 , P 2  and P 3 . 
     Accordingly, in some embodiments, the common power line VSS may include a first common power line VSS 1  provided in the first non-display area NDA 1 , a second common power line VSS 2  provided in the second non-display area NDA 2 , and a plurality of third common power lines VSSL connecting the first common power line VSS 1  with the second common power line VSS 2 . 
     The reference line VREF may supply an initialization voltage (or sensing voltage) to the driving transistor T of each of the subpixels P 1 , P 2  and P 3  provided in the display area DA. 
     Accordingly, in some embodiments, the reference line VREF may include a first reference line VREF 1  provided in the first non-display area NDA 1 , and a plurality of second reference lines VREFL disposed in the display area DA. 
     Hereinafter, the first pixel power line VDD 1 , the first common power line VSS 1  and the first reference line VREF 1 , which are provided in a first non-display area NDA 1 , will be described in more detail with reference to  FIGS. 10 to 13 . 
       FIG. 10  is an enlarged view of an area B in  FIG. 2 ,  FIG. 11  is a cross-sectional view taken along line IV-IV of  FIG. 10 ,  FIG. 12  is a cross-sectional view taken along line V-V of  FIG. 10 , and  FIG. 13  is a cross-sectional view taken along line VI-VI of  FIG. 10 . 
     The pads PAD, a first pixel power line VDD 1 , a first common power line VSS 1 , a first reference line VREF 1 , a third pixel power line VDDL and a third common power line VSSL are provided in the first non-display area NDA 1 . 
     Referring to  FIGS. 2, 10 and 11 , the first pixel power line VDD 1  may be provided to be extended in the first non-display area NDA 1 , specifically between the pad area PA and the display area DA in a first direction (X axis direction). The first pixel power line VDD 1  may be connected with the first pad VDDP in the first non-display area NDA 1 , and may be supplied with a first power source from the first pad VDDP. The first pad VDDP may be extended in a second direction (Y axis direction), and may be connected with the first pixel power line VDD  1 . For example, the first pixel power line VDD 1  and the first pad VDDP may be provided in the same layer as shown in  FIG. 11 , and may be connected with each other without being spaced apart from each other. 
     Also, the first pixel power line VDD 1  may be connected with a plurality of third pixel power lines VDDL disposed in the display area DA, and may supply the first power source to the driving transistor T of each of the subpixels P 1 , P 2  and P 3  through the plurality of third pixel power lines VDDL. 
     The first pixel power line VDD 1  may be made of a plurality of metal layers. For example, the first pixel power line VDD 1 , as shown in  FIG. 11 , may include a first metal layer VDD 1 - 1  and a second metal layer VDD 1 - 2  provided over the first metal layer VDD 1 - 1 . The first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  may partially be overlapped with each other, and may be connected with each other through a fourth contact hole CH 4 . 
     In some embodiments, the first metal layer VDD 1 - 1  of the first pixel power line VDD 1  may be provided in the same layer as the source electrode SE and the drain electrode DE of the driving transistor T provided in the display area DA. The first metal layer VDD 1 - 1  may be made of the same material as that of the source electrode SE and the drain electrode DE of the driving transistor T and may be formed simultaneously with them. 
     The second metal layer VDD 1 - 2  of the first pixel power line VDD 1  may be provided in the same layer as the anode auxiliary electrode  115  provided in the display area DA. The second metal layer VDD 1 - 2  may be made of the same material as that of the anode auxiliary electrode  115  and may be formed simultaneously with the anode auxiliary electrode  115 . In this case, the second metal layer VDD 1 - 2  of the first pixel power line VDD 1  may be connected to the first metal layer VDD 1 - 1  through a plurality of fourth contact holes CH 4  that pass through the first planarization layer PLN 1 . 
     In the transparent display panel  110  according to one embodiment of the present disclosure, as the first pixel power line VDD 1  provided in the non-display area NDA is provided as a double layer, a total area of the first pixel power line VDD 1  may be increased, whereby resistance of the first pixel power line VDD 1  may be reduced. 
     Also, in the transparent display panel  110  according to one embodiment of the present disclosure, as the second metal layer VDD 1 - 2  of the first pixel power line VDD 1  may be connected to the first metal layer VDD 1 - 1  through the plurality of fourth contact holes CH 4 , the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  may stably be connected with each other. 
     Meanwhile, in the transparent display panel  110  according to one embodiment of the present disclosure, the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  of the first pixel power line VDD 1  are not in entire contact with each other. If the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  of the first pixel power line VDD 1  are in entire contact with each other, even though the second planarization layer PLN 2  is deposited over the second metal layer VDD 1 - 2 , an upper surface of the area where the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  are in contact with each other may be formed to be recessed toward the first substrate  111  without being planarized. For this reason, a problem may occur in that the layers formed over the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  of the first pixel power line VDD 1 , for example, a second common power connection electrode  185 , the cathode electrode  140 , the encapsulation layer  150  are not deposited stably. 
     In the transparent display panel  110  according to one embodiment of the present disclosure, the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  of the first pixel power line VDD 1  may be in contact with each other through the plurality of fourth contact holes CH 4  without entire contact. In the transparent display panel  110  according to one embodiment of the present disclosure, if the second planarization layer PLN 2  is formed over the second metal layer VDD 1 - 2 , a planarized upper surface may be provided even in the area where the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  are in contact with each other. Therefore, in the transparent display panel  110  according to one embodiment of the present disclosure, the layers formed over the first metal layer VDD 1 - 1  and the second metal layer VDD 1 - 2  of the first pixel power line VDD 1 , for example, the second common power connection electrode  185 , the cathode electrode  140 , the encapsulation layer  150  may be deposited stably. 
     The second pixel power line VDD 2  may be provided to be extended in the second non-display area NDA 2  in a first direction (X axis direction). The second pixel power line VDD 2  may electrically be connected with the first pixel power line VDD 1  through the third pixel power line VDDL. 
     The second pixel power line VDD 2  may be made of a plurality of metal layers like the first pixel power line VDD 1 . For example, the second pixel power line VDD 2  may include a first metal layer and a second metal layer provided over the first metal layer like the first pixel power line VDD 1 . 
     The third pixel power line VDDL may be provided between the transmissive areas TA in the display area DA, and thus may be connected with the driving transistor T of each of the subpixels P 1 , P 2  and P 3 . The third pixel power line VDDL may be extended in the display area DA in a second direction (Y axis direction), and thus its one end may be connected with the first pixel power line VDD 1  and its other end may be connected with the second pixel power line VDD 2 . 
     In some embodiments, the third pixel power line VDDL may be connected with the first pixel power line VDD 1  as one layer but may be connected with the first pixel power line VDD 1  as a plurality of layers as shown in  FIG. 11 . 
     For example, the third pixel power line VDDL may include a second metal layer VDDL- 2  and a third metal layer VDDL- 3  provided below the second metal layer VDDL- 2 . The second metal layer VDDL- 2  of the third pixel power line VDDL may be extended in the display area DA to the first non-display area NDA 1  in a second direction (Y axis direction). The second metal layer VDDL- 2  may be provided in the same layer as the anode auxiliary electrode  115  provided in the display area DA. The second metal layer VDDL- 2  may be made of the same material as that of the anode auxiliary electrode  115  and may be formed simultaneously with the anode auxiliary electrode  115 . 
     One end of the third metal layer VDDL- 3  of the third pixel power line VDDL may be connected to the second metal layer VDDL- 2  of the third pixel power line VDDL in the first non-display area NDA 1 , and the other end thereof may be connected to the first pixel power line VDD 1 . The third metal layer VDDL- 3  may be provided in the same layer as the gate electrode GE of the driving transistor T provided in the display area DA. The third metal layer VDDL- 3  may be made of the same material as that of the gate electrode GE of the driving transistor T and may be formed simultaneously with the gate electrode GE. 
     The third metal layer VDDL- 3  of the third pixel power line VDDL may be connected to the second metal layer VDDL- 2  of the third pixel power line VDDL at one end through the first metal layer VDDL- 1 . In this case, the third metal layer VDDL- 3  of the third pixel power line VDDL may be connected to the first metal layer VDDL- 1  through a fifth contact hole CH 5  that passes through the first and second inter-layer insulating layers ILD 1  and ILD 2 . The first metal layer VDDL- 1  may be connected to the second metal layer VDDL- 2  of the third pixel power line VDDL through a sixth contact hole CH 6  that passes through the first planarization layer PLN 1 . Therefore, the third metal layer VDDL- 3  of the third pixel power line VDDL may electrically be connected with the second metal layer VDDL- 2  of the third pixel power line VDDL. 
     Also, the third metal layer VDDL- 3  of the third pixel power line VDDL may be connected to the first metal layer VDD 1 - 1  of the first pixel power line VDD 1  at the other end through a seventh contact hole CH 7  that passes through the first and second inter-layer insulating layers ILD 1  and ILD 2 . 
     Meanwhile, the third metal layer VDDL- 3  of the third pixel power line VDDL may be formed as one line pattern between the second metal layer VDDL- 2  and the first pixel power line VDD but is not limited thereto. The third metal layer VDDL- 3  of the third pixel power line VDDL may include a plurality of line patterns provided between the second metal layer VDDL- 2  and the first pixel power line VDD  1 . In this case, the third metal layer VDDL- 3  of the third pixel power line VDDL may electrically be connected with the plurality of line patterns through the metal layer provided over another layer, for example, the first metal layer VDDL- 1 . 
     Referring to  FIGS. 2, 10 and 12 , the first common power line VSS 1  may be provided to be extended in the first non-display area NDA 1 , specifically between the first pixel power line VDD 1  and the display area DA in a first direction (X axis direction). The first common power line VSS 1  may be connected with the second pad VSSP in the first non-display area NDA 1 , and may be supplied with a second power source from the second pad VSSP. Also, the first common power line VSS 1  may be connected with the plurality of third common power lines VSSL disposed in the display area DA, and may supply the second power source to the cathode electrode  140  of the subpixels P 1 , P 2  and P 3  through the plurality of third common power lines VSSL. 
     The first common power line VSS 1  may be made of a plurality of metal layers. For example, the first common power line VSS 1 , as shown in  FIG. 12 , may include a first metal layer VSS 1 - 1  and a second metal layer VSS 1 - 2  provided over the first metal layer VSS 1 - 1 . The first metal layer VSS 1 - 1  and the second metal layer VSS 1 - 2  may partially be overlapped with each other, and may be connected with each other through a fifth contact part CTS. 
     In some embodiments, the first metal layer VSS 1 - 1  of the first common power line VSS 1  may be provided in the same layer as the source electrode SE and the drain electrode DE of the driving transistor T provided in the display area DA. The first metal layer VSS 1 - 1  may be made of the same material as that of the source electrode SE and the drain electrode DE of the driving transistor T and may be formed simultaneously with them. 
     The second metal layer VSS 1 - 2  of the first common power line VSS 1  may be provided in the same layer as the anode auxiliary electrode  115  provided in the display area DA. The second metal layer VSS 1 - 2  may be made of the same material as that of the anode auxiliary electrode  115  and may be formed simultaneously with the anode auxiliary electrode  115 . 
     In this case, the second metal layer VSS 1 - 2  of the first common power line VSS 1  may be connected to the first metal layer VSS 1 - 1  through the fifth contact part CT 5  that passes through the first planarization layer PLN 1 . The fifth contact part CT 5  may partially remove the first planarization layer PLN 1  and partially expose the upper surface of the first metal layer VSS 1 - 1  of the first common power line VSS 1 . In some embodiments, the fifth contact part CT 5  may expose the upper surface of the first metal layer VSS 1 - 1  of the first common power line VSS 1  along the first direction (X axis direction). The second metal layer VSS 1 - 2  of the first common power line VSS 1  may directly in contact with the exposed upper surface of the first metal layer VSS 1 - 1  of the first common power line VSS 1 . As a result, the second metal layer VSS 1 - 2  of the first common power line VSS 1  may have a wide contact area with the first metal layer VSS 1 - 1  of the first common power line VSS 1 , thereby being stably connected to the first metal layer VSS 1 - 1 . 
     In the transparent display panel  110  according to one embodiment of the present disclosure, as the first common power line VSS 1  provided in the non-display area NDA is provided as a double layer, a total area of the first common power line VSS 1  may be increased, whereby resistance of the first common power line VSS 1  may be reduced. 
     Meanwhile, the first common power line VSS 1  may electrically be connected with the second pad VSSP provided in the pad area PA. In some embodiments, the first pixel power line VDD 1  and the first reference line VREF 1  may be provided between the first common power line VSS 1  and the second pad VSSP. If the first common power line VSS 1  is formed in the same layer as the first pixel power line VDD 1  and the first reference line VREF 1 , the first common power line VSS 1  and the second pad VSSP cannot be formed in the same layer in a single body. 
     The transparent display panel  110  according to one embodiment of the present disclosure may electrically connect the first common power line VSS 1  with the second pad VSSP by using a plurality of connection electrodes disposed on different layers. 
     In detail, the transparent display panel  110  according to one embodiment of the present disclosure may electrically connect the first common power line VSS 1  with the second pad VSSP by using a first common power connection electrode  180  and a second common power connection electrode  185 , which are disposed on their respective layers different from each other. 
     The first common power connection electrode  180  is provided in the first non-display area NDA 1 . The first common power connection electrode  180  is provided between the first common power line VSS 1  and the first substrate  111 , and electrically connects the first common power line VSS 1  with the second pad VSSP. 
     For example, the first common power connection electrode  180  may be provided in the same layer as the gate electrode GE of the driving transistor T provided in the display area DA. Also, the first common power connection electrode  180  may be made of the same material as that of the gate electrode GE of the driving transistor T and may be formed simultaneously with the gate electrode GE. 
     One end of the first common power connection electrode  180  may be connected to the first common power line VSS 1  and the other end of the first common power connection electrode  180  may be connected to the second pad VSSP. In detail, the first common power connection electrode  180  may be connected to the first metal layer VSS 1 - 1  of the first common power line VSS 1  at one end through an eighth contact hole CH 8  that passes through the first and second inter-layer insulating layers ILD 1  and ILD 2 . Also, the first common power connection electrode  180  may be connected to the second pad VSSP at the other end through a ninth contact hole CH 9  that passes through the first and second inter-layer insulating layers ILD 1  and ILD 2 . 
     Meanwhile, the first common power connection electrode  180  may be formed between the second pad VSSP and the first common power line VSS 1  as one electrode but is not limited thereto. The first common power connection electrode  180  may include a plurality of electrodes. 
     For example, the first common power connection electrode  180 , as shown in  FIG. 12 , may include one first common power connection electrode  181 , another first common power connection electrode  182 , and other first common power connection electrode  183 . 
     One first common power connection electrode  181  may be connected to the first common power line VSS 1  through the eighth contact hole CH 8 , and another first common power connection electrode  182  may be connected to the second pad VSSP through the ninth contact hole CH 9 . One first common power connection electrode  181  and another first common power connection electrode  182  may be provided in the same layer as the gate electrode GE of the driving transistor T. 
     One end of the other first common power connection electrode  183  provided over a layer different from one first common power connection electrode  181  and another first common power connection electrode  182  may be connected to the first common power connection electrode  181  through a tenth contact hole CH 10 , and the other end thereof may be connected to the first common power connection electrode  182  through an eleventh contact hole CH 11 . In some embodiments, the other first common power connection electrode  183  may be provided in the same layer as the source electrode SE and the drain electrode DE of the driving transistor T. 
     The second common power connection electrode  185  may be provided in the first non-display area NDA 1 , and may partially be overlapped with the first common power connection electrode  180 . Also, the second common power connection electrode  185  is provided over the first common power line VSS 1 , and electrically connects the first common power line VSS 1  with the second pad VSSP. 
     For example, the second common power connection electrode  185  may be provided in the same layer as the anode electrode  120  of the light emitting diode provided in the display area DA. Also, the second common power connection electrode  185  may be made of the same material as that of the anode electrode  120  of the light emitting diode and may be formed simultaneously with the anode electrode  120 . 
     One end of the second common power connection electrode  185  may be connected to the first common power line VSS 1 , and the other end of the second common power connection electrode  185  may be connected to the second pad VSSP. In detail, the second common power connection electrode  185  may be connected to the second metal layer VSS 1 - 2  of the first common power line VSS 1  at one end through a first contact part CT 1 . The first contact part CT 1  may partially remove the second planarization layer PLN 2  and partially expose the upper surface of the second metal layer VSS 1 - 2  of the first common power line VSS 1 . In some embodiments, the first contact part CT 1  may expose the upper surface of the second metal layer VSS 1 - 2  of the first common power line VSS 1  along the first direction (X axis direction). The second common power connection electrode  185  may directly in contact with the exposed upper surface of the first common power line VSS 1 . As a result, the second common power connection electrode  185  may have a wide contact area with the first common power line VSS 1 , thereby being stably connected to the first common power line VSS 1 . Meanwhile, at least a part of the first contact part CT 1  may be formed to overlap the fifth contact part CTS. 
     The second common power connection electrode  185  may be connected to the second pad VSSP at the other end through a second contact part CT 2 . The second contact part CT 2  may partially remove the first planarization layer PLN 1  and partially expose the upper surface of the second pad VSSP. The second pad VSSP, as shown in  FIG. 2 , may include a plurality of pad parts. In some embodiments, two pad parts disposed to adjoin each other may be connected with each other through a pad connection electrode PC. The second contact part CT 2  may expose the upper surface of the second pad VSSP connected by the pad connection electrode PC along the first direction (X axis direction). The second common power connection electrode  185  may directly in contact with the exposed upper surface of the second pad VSSP. As a result, the second common power connection electrode  185  may have a wide contact area with the second pad VSSP, thereby being stably connected to the second pad VSSP. 
     Also, the second common power connection electrode  185  may electrically be connected with the cathode electrode  140  through a cathode contact part CCT in the first non-display area NDA 1 . The cathode contact part CCT may partially remove the bank  125  and partially expose the upper surface of the second common power connection electrode  185 . The cathode contact part CCT may expose the upper surface of the second common power connection electrode  185  along the first direction (X axis direction). As a result, the second common power connection electrode  185  may have a wide contact area with the cathode electrode  140 , thereby being stably connected to the cathode electrode  140 . 
     Consequently, the first common power line VSS 1  may electrically be connected with the cathode electrode  140  through the second common power connection electrode  185 . Therefore, the first common power line VSS 1  may supply the second power source forwarded from the second pad VSSP to the cathode electrode  140 . 
     The transparent display panel  110  according to one embodiment of the present disclosure may electrically connect the first common power line VSS 1  and the second pad VSSP, which are disposed in the first non-display area NDA 1 , with each other by using the first common power connection electrode  180  and the second common power connection electrode  185  disposed on their respective layers different from each other. In some embodiments, the first common power connection electrode may be provided below the first common power line VSS 1  and the second pad VSSP, and the second common power connection electrode may be provided over the first common power line VSS 1  and the second pad VSSP. 
     Therefore, the transparent display panel  110  according to one embodiment of the present disclosure may increase a total area of the common power line VSS, whereby resistance of the common power line VSS may be reduced. 
     Also, in the transparent display panel  110  according to one embodiment of the present disclosure, even though a defect occurs in any one of the first common power connection electrode  180  and the second common power connection electrode  185 , the first common power line VSS 1  and the second pad VSSP may be connected with each other by the other one. Therefore, since the transparent display panel  110  according to one embodiment of the present disclosure may stably supply the first power source to the subpixels P 1 , P 2  and P 3 , panel yield may be improved. 
     The second common power line VSS 2  may be extended in the second non-display area NDA 2  in a first direction (X axis direction). The second common power line VSS 2  may electrically be connected with the first common power line VSS 1  through the third common power line VSSL. 
     The second common power line VSS 2  may be made of a plurality of metal layers like the first common power line VSS 1 . For example, the second common power line VSS 2  may include a first metal layer and a second metal layer provided over the first metal layer like the first common power line VSS 1 . 
     The third common power line VSSL is provided between the transmissive areas TA in the display area DA. In some embodiments, the transparent display panel  110  according to one embodiment of the present disclosure may reduce or minimize the non-transmissive area NTA in the display area DA by alternately disposing the third common power line VSSL and the third pixel power line VDDL between the transmissive areas TA. Therefore, the transparent display panel  110  according to one embodiment of the present disclosure may enhance transmittance by increasing the transmissive area TA. 
     Meanwhile, the third common power line VSSL may be extended in the display area DA in a second direction (Y axis direction), and thus its one end may be connected with the first common power line VSS 1  and its other end may be connected with the second common power line VSS 2 . For example, the third common power line VSSL and the first common power line VSS 1 , as shown in  FIG. 12 , may be provided in the same layer, and may be connected with each other without being spaced apart from each other. 
     Referring to  FIGS. 2, 10 and 13 , the first reference line VREF 1  may be provided to be extended in the first non-display area NDA 1 , specifically between the first pixel power line VDD 1  and the first common power line VSS 1  in a first direction (X axis direction). The first reference line VREF 1  may be connected with the third pad VREFP in the first non-display area NDA 1 , and may be supplied with the initialization voltage (or sensing voltage) from the third pad VREFP. Also, the first reference line VREF 1  may be connected with the plurality of second reference lines VREFL disposed in the display area DA, and may supply the initialization voltage (or sensing voltage) to the transistor T of each of the subpixels P 1 , P 2  and P 3  through the plurality of second reference lines VREFL. 
     The first reference line VREF 1  may be made of a plurality of metal layers. For example, the first reference line VREF 1 , as shown in  FIG. 13 , may include a first metal layer VREF 1 - 1  and a second metal layer VREF 1 - 2  provided over the first metal layer VREF 1 - 1 . The first metal layer VREF 1 - 1  and the second metal layer VREF 1 - 2  may partially be overlapped with each other, and may be connected with each other through a twelfth contact hole CH 12 . 
     In some embodiments, the first metal layer VREF 1 - 1  of the first reference line VREF 1  may be provided in the same layer as the source electrode SE and the drain electrode DE of the driving transistor T provided in the display area DA. The first metal layer VREF 1 - 1  may be made of the same material as that of the source electrode SE and the drain electrode DE of the driving transistor T and may be formed simultaneously with them. 
     The second metal layer VREF 1 - 2  of the first reference line VREF 1  may be provided in the same layer as the anode auxiliary electrode  115  provided in the display area DA. The second metal layer VREF 1 - 2  may be made of the same material as the anode auxiliary electrode  115  and may be formed simultaneously with the anode auxiliary electrode  115 . In this case, the second metal layer VREF 1 - 2  of the first reference line VREF 1  may be connected to the first metal layer VREF 1 - 1  through the twelfth contact hole CH 12  that passes through the first planarization layer PLN 1 . 
     In the transparent display panel  110  according to one embodiment of the present disclosure, as the first reference line VREF 1  provided in the non-display area NDA is provided as a double layer, a total area of the first reference line VREF 1  may be increased, whereby resistance of the first reference line VREF 1  may be reduced. 
     Meanwhile, the first reference line VREF 1  may electrically be connected with the third pad VREFP provided in the pad area PA. In some embodiments, the first pixel power line VDD 1  may be provided between the first reference line VREF 1  and the third pad VREFP. If the first reference line VREF 1  is formed in the same layer as the first pixel power line VDD 1 , the first reference line VREF 1  and the third pad VREFP cannot be formed in the same layer in a single body. 
     The transparent display panel  110  according to one embodiment of the present disclosure may electrically connect the first reference line VREF 1  with the third pad VREFP by using a plurality of connection electrodes disposed over different layers. 
     In detail, the transparent display panel  110  according to one embodiment of the present disclosure may electrically connect the first reference line VREF 1  with the third pad VREFP by using a first reference connection electrode  190  and a second reference connection electrode  195 , which are disposed on their respective layers different from each other. 
     The first reference connection electrode  190  is provided in the first non-display area NDA 1 . The first reference connection electrode  190  is provided between the first reference line VREF 1  and the first substrate  111 , and electrically connects the first reference line VREF 1  with the third pad VREFP. 
     For example, the first reference connection electrode  190  may be provided in the same layer as the gate electrode GE of the driving transistor T provided in the display area DA. Also, the first reference connection electrode  190  may be made of the same material as that of the gate electrode GE of the driving transistor T and may be formed simultaneously with the gate electrode GE. 
     One end of the first reference connection electrode  190  may be connected to the first reference line VREF 1  and the other end of the first reference connection electrode  190  may be connected to the third pad VREFP. In detail, the first reference connection electrode  190  may be connected to the first metal layer VREF 1 - 1  of the first reference line VREF 1  at one end through a thirteenth contact hole CH 13  that passes through the first and second inter-layer insulating layers ILD 1  and ILD 2 . Also, the first reference connection electrode  190  may be connected to the third pad VREFP at the other end through a fourteenth contact hole CH 14  that passes through the first and second inter-layer insulating layers ILD 1  and ILD 2 . 
     Meanwhile, the first reference connection electrode  190  may be formed between the first reference line VREF 1  and the third pad VREFP as one electrode but is not limited thereto. The first reference connection electrode  190  may include a plurality of electrodes. 
     The second reference connection electrode  195  may be provided in the first non-display area NDA 1 . At least a part of the second reference connection electrode  195  may be overlapped with the first reference connection electrode  190 . The second reference connection electrode  195  is provided over the first reference line VREF 1 , and electrically connects the first reference line VREF 1  with the third pad VREFP. 
     For example, the second reference connection electrode  195  may be provided in the same layer as the anode electrode  120  of the light emitting diode provided in the display area DA. Also, the second reference connection electrode  195  may be made of the same material as that of the anode electrode  120  of the light emitting diode and may be formed simultaneously with the anode electrode  120 . 
     One end of the second reference connection electrode  195  may be connected to the first reference line VREF 1  and the other end thereof may be connected to the third pad VREFP. In detail, the second reference connection electrode  195  may be connected to the second metal layer VREF 1 - 2  of the first reference line VREF 1  at one end through a third contact part CT 3 . The third contact part CT 3  may partially remove the second planarization layer PLN 2  and partially expose the upper surface of the second metal layer VREF 1 - 2  of the first reference line VREF 1 . In some embodiments, the third contact part CT 3  may expose the upper surface of the second metal layer VREF 1 - 2  of the first reference line VREF 1  along the first direction (X axis direction). As a result, the second reference connection electrode  195  may have a wide contact area with the first reference line VREF 1 , thereby being stably connected to the first reference line VREF 1 . 
     The second reference connection electrode  195  may be connected to the third pad VREFP at the other end through a fourth contact part CT 4 . The fourth contact part CT 4  may partially remove the first planarization layer PLN 1  and partially expose the upper surface of the third pad VREFP. In some embodiments, the fourth contact portion CT 4  may expose the upper surface of the third pad VREFP along the first direction (X axis direction). The second reference connection electrode  195  may directly in contact with the exposed upper surface of the third pad VREFP. As a result, the second reference connection electrode  195  may have a wide contact area with the third pad VREFP, thereby being stably connected to the third pad VREFP. 
     The second reference connection electrode  195  is formed in the same layer as the second common power connection electrode  185  but is spaced apart from the second common power connection electrode  185 . Therefore, the second reference connection electrode  195  is not electrically connected with the second common power connection electrode  185 . 
     The transparent display panel  110  according to one embodiment of the present disclosure may connect the first reference line VREF 1  and the third pad VREFP, which are disposed in the first non-display area NDA 1 , with each other by using the first reference connection electrode  190  and the second reference connection electrode  195  disposed on their respective layers different from each other. In some embodiments, the first reference connection electrode  190  may be provided below the first reference line VREF 1  and the third pad VREFP, and the second reference connection electrode  195  may be provided over the first reference line VREF 1  and the third pad VREFP. 
     Therefore, the transparent display panel  110  according to one embodiment of the present disclosure may increase a total area of the first reference line VREF 1 , whereby resistance of the first reference line VREF 1  may be reduced. 
     Also, in the transparent display panel  110  according to one embodiment of the present disclosure, even though a defect occurs in any one of the first reference connection electrode  190  and the second reference connection electrode  195 , the first reference line VREF 1  and the third pad VREFP may be connected with each other by the other one. Therefore, since the transparent display panel  110  according to one embodiment of the present disclosure may stably supply the initialization voltage (or sensing voltage) to the subpixels P 1 , P 2  and P 3 , panel yield may be improved. 
     Also, the transparent display panel  110  according to one embodiment of the present disclosure may test a defect of the driving transistor T before the anode electrode  120  is deposited. 
     The transparent display panel  110  may connect the first common power line VSS 1  with the second pad VSSP by using only the second common power connection electrode  185  provided in the same layer as the anode electrode  120 . Also, the transparent display panel  110  may connect the first reference line VREF 1  with the third pad VREFP by using only the second reference connection electrode  195  provided in the same layer as the anode electrode  120 . 
     In this case, a process of testing a defect of the driving transistor T has no choice but to be performed after the anode electrode  120  is deposited. If a defect occurs in the driving transistor T, a repair process may be performed to repair a portion where the defect has occurred. In some embodiments, the layers deposited on the layer where the defect has occurred should be removed to perform the repair process. For example, if the defect occurs in the layer provided with the anode auxiliary electrode  115 , the second planarization layer PLN 2  and the anode electrode  120  should be removed for the repair process. In some embodiments, luminescence may not be performed in the corresponding area. 
     In this way, if the repair process is performed after the anode electrode  120  is formed, repair yield is reduced due to the anode electrode  120  and the organic layer PLN 2  provided over the anode auxiliary electrode  115 , and a tact time is increased. 
     The transparent display panel  110  according to one embodiment of the present disclosure may connect the first common power line VSS 1  with the second pad VSSP by using the first common power connection electrode  180  and the second common power connection electrode  185 . Also, the transparent display panel  110  according to one embodiment of the present disclosure may connect the first common power line VSS 1  with the second pad VSSP through the first common power connection electrode  180  even though the second common power connection electrode  185  is not formed. 
     The transparent display panel  110  according to one embodiment of the present disclosure may connect the first reference line VREF 1  with the third pad VREFP by using the first reference connection electrode  190  and the second reference connection electrode  195 . Also, the transparent display panel  110  according to one embodiment of the present disclosure may connect the first reference line VREF 1  with the third pad VREFP through the first reference connection electrode  190  even though the second reference connection electrode  195  is not formed. 
     Therefore, the transparent display panel  110  according to one embodiment of the present disclosure may test a defect of the driving transistor T before the anode electrode  120  is deposited. That is, since the repair process is performed before the second planarization layer PLN 2  and the anode electrode  120  are deposited, the transparent display panel  110  according to one embodiment of the present disclosure may prevent repair yield from being reduced due to the second planarization layer PLN 2  and the anode electrode  120 . In addition, the transparent display panel  110  according to one embodiment of the present disclosure may reduce a tact time. 
     Meanwhile, in the transparent display panel  110  according to one embodiment of the present disclosure, the pixel power line VDD, the common power line VSS and the first reference line VREF 1  may be provided in only the first non-display area NDA 1  and the second non-display area NDA 2  of the non-display area NDA. In the transparent display panel  110  according to one embodiment of the present disclosure, each of the pixel power line VDD, the common power line VSS and the first reference line VREF 1  may be formed in a double layered structure, and the common power line VSS and the first reference line VREF 1  may respectively be connected with the plurality of connection electrodes. Therefore, even though the pixel power line VDD, the common power line VSS and the first reference line VREF 1  are provided in only the first non-display area NDA 1  and the second non-display area NDA 2 , the transparent display panel  110  according to one embodiment of the present disclosure may make sure of a sufficient area of each of the pixel power line VDD, the common power line VSS and the first reference line VREF 1  and reduce or minimize resistance. 
     In the transparent display panel  110  according to one embodiment of the present disclosure, as the pixel power line VDD, the common power line VSS and the first reference line VREF 1  are not provided in the third non-display area NDA 3  and the fourth non-display area NDA 4 , transmittance in the third non-display area NDA 3  and the fourth non-display area NDA 4  may be improved. That is, the transparent display panel  110  according to one embodiment of the present disclosure may have transmittance even in the third non-display area NDA 3  and the fourth non-display area NDA 4 , which is similar to that of the display area DA. 
     It will be apparent to those skilled in the art that the present disclosure described above is not limited by the above-described embodiments and the accompanying drawings and that various substitutions, modifications, and variations can be made in the present disclosure without departing from the spirit or scope of the disclosures. Consequently, the scope of the present disclosure is intended to cover all variations or modifications derived from the meaning, scope, and equivalent concept of the present disclosure. 
     The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
     These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.