Patent Publication Number: US-9835908-B2

Title: Display apparatus

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2015-0026677 filed on Feb. 25, 2015, the contents of which are hereby incorporated by reference in their entirety. 
     BACKGROUND 
     1. Field of Disclosure 
     The present disclosure relates generally to flat panel displays. More particularly, the present disclosure relates to a flat panel display apparatus operated in an inversion driving scheme. 
     2. Description of the Related Art 
     A liquid crystal display forms an electric field in a liquid crystal layer disposed between two substrates, and this field changes an alignment of liquid crystal molecules of the liquid crystal layer to control a transmittance of light incident to the liquid crystal layer. In this manner, a desired image is displayed through the liquid crystal display. 
     Liquid crystal display driving methods are typically classified into line inversion methods, column inversion methods, and dot inversion methods according to a phase of a data voltage applied to data lines. The line inversion method inverts the phase of image data applied to data lines every pixel row, the column inversion method inverts the phase of the image applied to the data lines every pixel column, and the dot inversion method inverts the phase of the image data applied to the data lines every pixel row and every pixel column. 
     In general, a display apparatus displays colors using red, green, and blue colors as primary colors. Accordingly, the display apparatus includes pixels respectively corresponding to the red, green, and blue colors. In recent years, a display apparatus that displays images using red, green, blue, and white colors has been developed. 
     SUMMARY 
     The present disclosure provides a display apparatus capable of reducing or eliminating a horizontal crosstalk phenomenon and a moving line-stain phenomenon. 
     Embodiments of the inventive concept provide a display apparatus including a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction crossing the first direction, and a plurality of pixels connected to the gate lines and the data lines. The pixels include pixels arranged in a k-th column between a k-th data line and a (k+1)th data line. The pixels in the k-th are arranged in a plurality of groups and each of the groups includes 2i first pixels connected to the k-th data line and 2i second pixels connected to the (k+1)th data line. 
     Successive ones of the pixels in each group are connected to the k-th data line and the (k+1)th data line, and each pixel has a width in the first direction that is greater than a width in the second direction. 
     Embodiments of the inventive concept also provide a display apparatus including a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction crossing the first direction, and a plurality of pixels connected to the gate lines and the data lines, the plurality of pixels comprising at least first and second dots. The first dot includes first, second, and third pixels sequentially arranged in the first direction, and the second dot includes fourth, fifth, and sixth pixels sequentially arranged in the first direction. The pixels in a k-th column are arranged in groups of 4i pixels, the pixels of each group being connected to their two adjacent data lines in alternating manner. 
     According to the above, the horizontal crosstalk phenomenon and the moving line-stain phenomenon may be substantially improved. In addition, a flicker caused by brightness difference may be prevented from being perceived between frame periods. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other advantages of the present disclosure will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein: 
         FIG. 1  is a block diagram showing a liquid crystal display apparatus according to an exemplary embodiment of the present disclosure; 
         FIG. 2  is an equivalent circuit diagram for one pixel of  FIG. 1 ; 
         FIG. 3  is a plan view showing a portion of a liquid crystal panel according to an exemplary embodiment of the present disclosure; 
         FIG. 4A  is a plan view showing a state in which first and second red pixels of  FIG. 3  are turned on; 
         FIG. 4B  is a plan view showing a state in which first and second green pixels of  FIG. 3  are turned on; 
         FIG. 4C  is a plan view showing a state in which first and second blue pixels of  FIG. 3  are turned on; 
         FIG. 4D  is a plan view showing a state in which all pixels shown in  FIG. 3  are turned on; 
         FIG. 5  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure; 
         FIG. 6  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure; 
         FIG. 7  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure; 
         FIG. 8  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure; 
         FIG. 9  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure; 
         FIG. 10A  is a plan view showing a state in which red pixels of  FIG. 9  are turned on; 
         FIG. 10B  is a plan view showing a state in which green pixels of  FIG. 9  are turned on; 
         FIG. 10C  is a plan view showing a state in which blue pixels of  FIG. 9  are turned on; 
         FIG. 10D  is a plan view showing a state in which all pixels shown in  FIG. 9  are turned on; 
         FIG. 11  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure; 
         FIG. 12  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure; 
         FIG. 13  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure; 
         FIG. 14  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure; and 
         FIG. 15  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings, which are not necessarily to scale. All numerical values are approximate, and may vary. All examples of specific materials and compositions are to be taken as nonlimiting and exemplary only. Other suitable materials and compositions may be used instead. 
       FIG. 1  is a block diagram showing a liquid crystal display apparatus  1000  according to an exemplary embodiment of the present disclosure and  FIG. 2  is an equivalent circuit diagram showing one pixel of  FIG. 1 . 
     Referring to  FIG. 1 , the liquid crystal display apparatus  1000  includes a liquid crystal panel  100 , a controller  200 , a gate driver  300 , and a data driver  400 . 
     The liquid crystal panel  100  includes a lower substrate  110 , an upper substrate  120  facing the lower substrate  110 , and a liquid crystal layer  130  interposed between the lower and upper substrates  110  and  120 . 
     The liquid crystal panel  100  includes a plurality of gate lines G 1  to Gm extending in a first direction DR 1  and a plurality of data lines D 1  to Dn extending in a second direction DR 2  crossing the first direction DR 1 . The gate lines G 1  to Gm and the data lines D 1  to Dn define pixel areas, and pixels PX displaying an image are arranged in the pixel areas in a one-to-one correspondence.  FIG. 1  shows one pixel from among the pixels PX. This particular pixel is arranged in a first row and a first column and is connected to a first gate line G 1  among the gate lines G 1  to Gm and a first data line D 1  among the data lines D 1  to Dn, as a representative example. 
     Referring to  FIGS. 1 and 2 , the pixel PX includes a thin film transistor TR connected to the first gate line G 1  and the first data line D 1 , a liquid crystal capacitor Clc connected to the thin film transistor TR, and a storage capacitor Cst connected to the liquid crystal capacitor Clc in parallel. The storage capacitor Cst may be omitted if desired. The liquid crystal capacitor Clc includes a pixel electrode PE disposed on the lower substrate  110  and a common electrode CE disposed on the upper substrate  120  as its two terminals, and the liquid crystal layer  130  disposed between the pixel electrode PE and the common electrode CE serves as the dielectric of the liquid crystal capacitor Clc. 
     The thin film transistor TR may be disposed on the lower substrate  110 . The thin film transistor TR includes a gate electrode connected to the first gate line G 1 , a source electrode connected to the first data line D 1 , and a drain electrode connected to the pixel electrode PE. The common electrode CE is disposed over an entire surface of the upper substrate  120  and receives a common voltage. Unlike the configuration shown in  FIG. 2 , the common electrode CE may be disposed on the lower substrate  110 , and in this case, at least one of the pixel electrode PE and the reference electrode CE may include slits. 
     The storage capacitor Cst assists the liquid crystal capacitor Clc and includes the pixel electrode PE, a storage line (not shown), and an insulating layer disposed between the pixel electrode PE and the storage line (not shown). The storage line (not shown) is disposed on the lower substrate  110  to overlap a portion of the pixel electrode PE. The storage line (not shown) receives a constant voltage, such as a storage voltage. 
     Although not shown in  FIG. 2 , according to another embodiment, the display apparatus  1000  may have a structure in which each pixel PX is divided into two different grayscale areas. In this structure, each pixel PX includes at least two sub-pixels receiving data voltages based on differing gamma curves, and thus, the two sub-pixels display different grayscales with respect to the same input image data. 
     The pixels PX each display one of the primary colors. The primary colors include red, green, blue, and white colors. The pixels may however include any other primaries. For example, they may include yellow, cyan, and magenta colors. Each of the pixels may further include a color filter CF representing one of the primary colors. In  FIG. 2 , the color filter CF is disposed on the upper substrate  120 , but it should not be limited thereto or thereby. That is, the color filter CF may be disposed on the lower substrate  110 . 
     The controller  200  receives image data RGB and control signals from an external graphic controller (not shown). The control signals include a vertical synchronization signal Vsync as a frame distinction signal, a horizontal synchronization signal Hsync as a row distinction signal, a data enable signal maintained at a high level during a period in which data are output (so as to indicate a data input period), and a main clock signal MCLK. 
     The controller  200  converts the image data RGB to a format compatible with the data driver  400 , and applies the converted image data DATA to the data driver  400 . The controller  200  generates a gate control signal GS 1  and a data control signal DS 1 . The controller  200  applies the gate control signals GS 1  to the gate driver  300  and applies the data control signal DS 1  to the data driver  400 . 
     The gate control signal GS 1  is used to drive the gate driver  300  and the data control signal DS 1  is used to drive the data driver  400 . 
     The gate driver  300  generates gate signals in response to the gate control signal GS 1  and sequentially applies the gate signals to the gate lines G 1  to Gm. The gate control signal GS 1  includes a vertical start signal initiating scanning of the gate driver  300 , at least one clock signal controlling an output timing of a gate-on voltage, and an output enable signal determining a duration of the gate-on voltage. 
     The data driver  400  converts the image data DATA to corresponding grayscale voltages in response to the data control signal DS 1 , and applies the grayscale voltages to the data lines D 1  to Dn as the data voltages. The data voltages include a positive polarity (+) data voltage having a positive value with respect to the common voltage, and a negative polarity (−) data voltage having a negative value with respect to the common voltage. The data control signal DS 1  includes a horizontal start signal STH initiating transmission of the image data DATA to the data driver  400 , a load signal indicating application of the data voltages to the data lines D 1  to Dn, and an inversion signal inverting the polarity of the data voltages with respect to the reference voltage. 
     The polarity of the data voltages applied to the pixels PX is inverted after one frame is finished and before a next frame starts, to prevent liquid crystal molecules from deteriorating and burning. That is, the polarity of the data voltage is inverted every frame in response to the inversion signal applied to the data driver  400 . The liquid crystal panel  100  is operated in a manner in which data voltages having different polarities from each other are applied to the data lines D 1  to Dn in units of at least one data line while the image corresponding to the one frame is displayed, and thus a display quality of the image is improved. 
     Each of the controller  200 , the gate driver  300 , and the data driver  400  is directly mounted on the liquid crystal panel  100  in at least one integrated circuit chip. This chip is connected to the liquid crystal panel  100  in a tape carrier package (TCP) manner after being mounted on a flexible printed circuit board, or mounted on a separate printed circuit board. Alternatively, the gate driver  300  may be directly integrated on the liquid crystal panel  100  together with the gate lines G 1  to Gm, the data lines D 1  to Dn, and the thin film transistor TR. In addition, the controller  200 , the gate driver  300 , and the data driver  400  may be integrated in a single chip. 
       FIG. 3  is a plan view showing a portion of a liquid crystal panel according to an exemplary embodiment of the present disclosure. 
     Referring to  FIG. 3 , the pixels includes pixels arranged in a k-th column (k is an integer number equal to or greater than 1) positioned between a k-th data line and a (k+1)th data line among the data lines D 1  to Dn. 
     The pixels arranged in the k-th column are grouped into a plurality of groups consecutively arranged along the second direction DR 2 . Each group includes 2n first pixels PX 1  (n is an integer number equal to or greater than 1) connected to the k-th data line and 2n second pixels PX 2  connected to the (k+1)th data line. Each group includes an even number of pixels. Within each pixel group, the pixels arranged in the k-th column are alternately connected to the k-th data line and the (k+1)th data line, i.e. connected to both the k-th and (k+1)th data lines in a predetermined sequence. 
     Hereinafter, first, second, third, fourth, fifth, sixth, seventh, and eighth gate lines G 1 , G 2 , G 3 , G 4 , G 5 , G 6 , G 7 , and G 8 , first, second, third, fourth, fifth, sixth, seventh, and eighth data lines D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , D 7 , and D 8 , and pixels PX(8×8) arranged in eight rows by eight columns and defined by the lines G 1  to G 8  and D 1  to D 8  will be described in detail with reference to  FIGS. 3 and 5 to 8 . 
     The pixels arranged in the eight rows PR 1 , PR 2 , PR 3 , PR 4 , PR 5 , PR 6 , PR 7 , and PR 8  (hereinafter, referred to as first, second, third, fourth, fifth, sixth, seventh, and eighth pixel rows) are sequentially arranged along the second direction DR 2 , and the pixels arranged in the eight columns PC 1 , PC 2 , PC 3 , PC 4 , PC 5 , PC 6 , PC 7 , and PC 8  (hereinafter, referred to as first, second, third, fourth, fifth, sixth, seventh, and eighth pixel columns) are sequentially arranged along the first direction DR 1 . The first to eighth pixel rows PR 1  to PR 8  are connected to the first to eighth gate lines G 1  to G 8  in a one-to-one correspondence. 
     The first pixel column PC 1  is disposed between the first and second data lines D 1  and D 2 , the second pixel column PC 2  is disposed between the second and third data lines D 2  and D 3 , and the third pixel column PC 3  is disposed between the third and fourth data lines D 3  and D 4 . Since the first to eighth columns PC 1  to PC 8  have substantially the same structure and function, hereinafter a connection structure of the first pixel column PC 1  will be described in detail and detailed descriptions on the connection structures of the second to eighth pixel columns PC 2  to PC 8  will be omitted. 
     Each of the first to eighth pixel columns PC 1  to PC 8  includes groups PG 1  and PG 2  consecutively arranged along the second direction DR 2 . Each of the groups PG 1  and PG 2  of the first pixel column PC 1  includes 2i (i is an integer number equal to or greater than 1) first pixels PX 1  connected to the first data line D 1  and 2i second pixels PX 2  connected to the second data line D 2 .  FIG. 3  shows the case of i=1 as a representative example. Each group PG 1  and PG 2  includes two first pixels PX 1  and two second pixels PX 2 . Here, the first pixels PX 1  of the first pixel column PC 1  are connected to the first data line D 1  and the second pixels PX 2  of the first pixel column PC 1  are connected to the second data line D 2 . The two first pixels PX 1  included in each group may have different colors from each other, and the two second pixels PX 2  included in each group may have different colors from each other. 
     The pixels of the first pixel column PC 1  are alternately connected to the first and second data lines D 1  and D 2  within each group PG 1  and PG 2 . As an example, a first group PG 1  of the groups PG 1  and PG 2  includes two first pixels PX 1  respectively arranged in the first and third pixel rows PR 1  and PR 3  and respectively connected to the first and third gate lines G 1  and G 3 . The first group PG 1  includes two second pixels PX 2  respectively arranged in the second and fourth pixel rows PR 2  and PR 4  and respectively connected to the second and fourth gate lines G 2  and G 4 . The second group PG 2  of the groups PG 1  and PG 2  includes two first pixels PX 1  respectively arranged in the sixth and eighth pixel rows PR 6  and PR 8  and respectively connected to the sixth and eighth gate lines G 6  and G 8 . The second group PG 2  includes two second pixels PX 2  respectively arranged in the fifth and seventh pixel rows PR 5  and PR 7  and respectively connected to the fifth and seventh gate lines G 5  and G 7 . 
     The order of the first and second pixels PX 1  and PX 2  is reversed by pixel group. That is, when the first pixels PX 1  of the first group PG 1  are arranged in odd-numbered pixel rows and the second pixels PX 2  of the first group PG 1  are arranged in even-numbered pixel rows, the first pixels PX 1  of the second group PG 2  are arranged in even-numbered pixel rows and the second pixels PX 2  of the second group PG 2  are arranged in odd-numbered pixel rows. As an example, the pixels PX 1  and PX 2  of the first group PG 1  and the pixels PX 2  and PX 1  of the second group PG 2  are arranged symmetrically with respect to the fourth gate line G 4 . 
     Accordingly, the first pixels PX 1  are arranged in first, third, sixth, and eighth pixel rows PR 1 , PR 3 , PR 6 , and PR 8  of each of the first to eighth pixel columns PC 1  to PC 8  and are connected to a left data line of the two data lines adjacent to their respective pixel columns. The second pixels PX 2  are arranged in second, fourth, fifth, and seventh pixel rows PR 2 , PR 4 , PR 5 , and PR 7  of each of the first to eighth pixel columns PC 1  to PC 8 , and are connected to a right data line of the two data lines adjacent to their respective pixel columns. 
     First to eighth data voltages are applied to the first to eighth data lines D 1  to D 8 , and each of the first to eighth data voltages has a positive (+) or negative (−) polarity with respect to the common voltage applied to the common electrode CE (refer to  FIG. 2 ).  FIG. 3  shows the polarity of the data voltages applied to the pixels in a j-th (j is an integer number equal to or greater than 1) frame, and thus the polarity of the data voltages applied to the pixels in a (j+1)th frame is inverted. That is, the data driver  400  shown in  FIG. 1  inverts the polarity of the data voltages applied to the data lines D 1  to Dn every frame. 
     The polarity of the first to eighth data voltages is inverted in the unit of 2z data lines in the first direction DR 1 . In detail, when the z=2 in  FIG. 3 , the first to fourth data voltages respectively applied to the first to fourth data lines D 1  to D 4  have the polarities of +, −, +, and −, respectively, and the fifth to eighth data voltages respectively applied to the fifth to eighth data lines D 5  to D 8  have the polarities of −, +, −, and +, respectively. Therefore, the first, third, sixth, and eighth data lines D 1 , D 3 , D 6 , and D 8  receive a positive polarity (+) data voltage and the second, fourth, fifth, and seventh data lines D 2 , D 4 , D 5 , and D 7  receive a negative polarity (−) data voltage. 
     The pixels of each of the first to eighth pixel columns PC 1  to PC 8  are repeatedly arranged in groupings of four colors, along the second direction DR 2 . Thus, among the pixels of each of the first to eighth pixel columns PC 1  to PC 8 , the pixels of the first and fifth pixel rows PR 1  and PR 5  have the same color, the pixels of the second and sixth pixel rows PR 2  and PR 6  have the same color, the pixels of the third and seventh pixel rows PR 3  and PR 7  have the same color, and the pixels of the fourth and eighth pixel rows PR 4  and PR 8  have the same color. 
     As an example, the pixels in the first and fifth pixel rows PR 1  and PR 5  of the first, third, fifth, and seventh pixel columns PC 1 , PC 3 , PC 5 , and PC 7  have a red color (R), and the pixels in the second and sixth pixel rows PR 2  and PR 6  of the first, third, fifth, and seventh pixel columns PC 1 , PC 3 , PC 5 , and PC 7  have a green color (G). The pixels in the third and seventh pixel rows PR 3  and PR 7  of the first, third, fifth, and seventh pixel columns PC 1 , PC 3 , PC 5 , and PC 7  have a blue color (B), and the pixels in the fourth and eighth pixel rows PR 4  and PR 8  of the first, third, fifth, and seventh pixel columns PC 1 , PC 3 , PC 5 , and PC 7  have a white color (W). 
     The pixels in the first and fifth pixel rows PR 1  and PR 5  of the second, fourth, sixth, and eighth pixel columns PC 2 , PC 4 , PC 6 , and PC 8  have the blue color (B), and the pixels in the second and sixth pixel rows PR 2  and PR 6  of the second, fourth, sixth, and eighth pixel columns PC 2 , PC 4 , PC 6 , and PC 8  have the white color (W). The pixels in the third and seventh pixel rows PR 3  and PR 7  of the second, fourth, sixth, and eighth pixel columns PC 2 , PC 4 , PC 6 , and PC 8  have a red color (R), and the pixels in the fourth and eighth pixel rows PR 4  and PR 8  of the second, fourth, sixth, and eighth pixel columns PC 2 , PC 4 , PC 6 , and PC 8  have the green color (G). 
     In  FIG. 3 , the pixels having the red color, the pixels having the green color, the pixels having the blue color, and the pixels having the white color are represented by R, G, B, and W, respectively. In addition, the pixels receiving the positive polarity (+) data voltage are represented by R+, G+, B+, and W+, respectively, and the pixels receiving the negative polarity (−) data voltage are represented by R−, G−, B−, and W−, respectively. 
     The arrangement order of the pixels should not be limited to that shown in  FIG. 3 . That is, positions of the red, green, blue, and white pixels R, B, and W may vary in any manner. As an example, the pixels of each pixel row may be arranged in repeating pairs of the same color, or the pixels of each pixel column may be arranged in repeating groups of four pixels of the same color. 
     A first red pixel R+ of the first group PG 1  of the first pixel column PC 1  is connected to the first data line D 1 , and a second red pixel R− of the second group PG 2  of the first pixel column PC 1  is connected to the second data line D 2 . A first green pixel G− of the first group PG 1  of the first pixel column PC 1  is connected to the second data line D 2 , and a second green pixel G+ of the second group PG 2  of the first pixel column PC 1  is connected to the first data line D 1 . A first blue pixel B+ of the first group PG 1  of the first pixel column PC 1  is connected to the first data line D 1 , and a second blue pixel B− of the second group PG 2  of the first pixel column PC 1  is connected to the second data line D 2 . A first white pixel W− of the first group PG 1  of the first pixel column PC 1  is connected to the second data line D 2 , and a second white pixel W+ of the second group PG 2  of the first pixel column PC 1  is connected to the first data line D 1 . 
     Accordingly, the polarity of the data voltages applied to the pixels displaying a first color in the first group PG 1  of the first pixel column PC 1  is different from the polarity of the data voltages applied to the pixels displaying the first color in the second group PG 2  of the first pixel column PC 1 . The first color may be one of the red, green, blue, and white colors. In this embodiment, polarity is inverted every four data lines. That is, each group of four successive data lines has the opposite polarities as its adjacent groups. When pixels are also connected to the data lines as above, three columns of four pixel columns have same-color pixels receiving data voltages of both polarities, and one column of the four pixel columns has same color receiving data voltages of only one polarity. That is, within the four successive pixel columns, three of these columns apply data voltages of two polarities different to each color, while the fourth column only applies data voltages of a single polarity. 
     In the present exemplary embodiment, dummy pixels DPX may be disposed adjacent to the second pixels PX 2  of the first pixel column PC 1 . The dummy pixels DPX are connected to the first data line D 1 . The dummy pixels DPX are disposed adjacent to the second pixels PX 2  of the first pixel column PC 1  and adjacent to the first pixels PX 1  of the last pixel column. 
     Therefore, the dummy pixels DPX connected to the first data line D 1  are positioned in odd-numbered pixel rows, and the dummy pixels DPX connected to the last data line Dn are positioned in even-numbered pixel rows. 
     The red, green, blue, and white pixels R, G, B, and W are arranged in repeating order on the liquid crystal panel  110  along the second direction D 2 . Each of the red, green, blue, and white pixels R, G, B, and W has a horizontal pixel structure in which a width (hereinafter, referred to as a horizontal width) in the first direction D 1  is greater than a width (hereinafter, referred to as a vertical width) in the second direction D 2 . In the present exemplary embodiment, a ratio of the horizontal width to the vertical width is in a range of from 2:1 to 3:1. 
       FIG. 4A  is a plan view showing a state in which the first and second red pixels among the pixels shown in  FIG. 3  are turned on,  FIG. 4B  is a plan view showing a state in which the first and second green pixels among the pixels shown in  FIG. 3  are turned on,  FIG. 4C  is a plan view showing a state in which the first and second blue pixels among the pixels shown in  FIG. 3  are turned on, and  FIG. 4D  is a plan view showing a state in which all pixels shown in  FIG. 3  are turned on. 
     Referring to  FIG. 4A , the first and second red pixels R+ and R− receive data voltages having the same grayscale but different polarities. However, although the data voltages have the same grayscale, a difference in voltage between the positive polarity (+) data voltage and the negative polarity (−) data voltage occurs due to a kickback voltage. Due to this difference in voltage, a difference in brightness occurs between the first and second red pixels R+ and R−. For convenience in explanation, the first and second red pixels R+ and R− are represented by different hatchings in  FIG. 4A . 
     When a sum of polarities of the data voltages applied to the pixels arranged in the same pixel row is biased to the positive (+) polarity or the negative (−) polarity, a phenomenon, in which the common voltage ripples to a positive direction or a negative direction due to a coupling phenomenon between the common electrode and the data lines, occurs. 
     However, as shown in  FIG. 4A , the first and second red pixels R+ and R− are repeatedly arranged in the first direction DR 1 . That is, in a single pixel row, the number of first red pixels R+ receiving the positive polarity (+) data voltage is equal to the number of second red pixels R− receiving the negative polarity (−) data voltage. For pixels displaying other colors, e.g., green, blue, and white colors, the number of pixels receiving the positive polarity (+) data voltage is equal to the number of pixels receiving the negative polarity (−) data voltage in each pixel row. Accordingly, the common voltage is prevented from being rippled to the positive or negative direction with respect to the reference voltage, and thus horizontal crosstalk is prevented from occurring. 
     The first and second red pixels R+ and R− are arranged in repeating manner along the second direction DR 2 . That is, the number of the first red pixels R+ receiving the positive data voltage is equal to the number of the second red pixels R− receiving the negative data voltage in one pixel column. For pixels displaying other colors, e.g., green, blue, and white colors, the number of pixels receiving the positive polarity (+) data voltage is equal to the number of pixels receiving the negative polarity (−) data voltage in each pixel column. Accordingly, brightness difference is prevented from occurring between the pixel columns, and thus the moving line-stain, in which a vertical line is perceived when the i-th frame is changed to the (i−1)th frame, is prevented from occurring. 
     Similarly, the first and second green pixels G+ and G− are arranged in repeating manner along the first and second directions DR 1  and DR 2  and the first and second blue pixels B+ and B− are also arranged in repeating manner along the first and second directions DR 1  and DR 2  as shown in  FIGS. 4B and 4C . Therefore, brightness difference is prevented from occurring between different pixel rows and between different pixel columns, and thus horizontal crosstalk and moving line-stains are prevented from occurring. 
     As described above, the positive and negative pixels displaying the red, green, blue, and white pixels are arranged in repeating manner along the pixel rows and the pixel columns, and the number of positive pixels is equal to the number of negative pixels with respect to each of the red, green, blue, and white pixels. Thus, although all pixels are substantially and simultaneously operated as shown in  FIG. 4D , brightness difference does not occur between the pixel rows and the pixel columns. As a result, the horizontal crosstalk phenomenon and the moving line-stain phenomenon may be prevented from occurring. 
       FIG. 5  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure. 
     Referring to  FIG. 5 , the first to fourth data voltages respectively applied to the first to fourth data lines D 1  to D 4  have polarities of +, −, −, and +, respectively, and the fifth to eighth data voltages respectively applied to the fifth to eighth data lines D 5  to D 8  have polarities of −, +, +, and −, respectively. Therefore, the first, fourth, sixth, and seventh data lines D 1 , D 4 , D 6 , and D 7  receive a positive polarity (+) data voltage and the second, third, fifth, and eighth data lines D 2 , D 3 , D 5 , and D 8  receive a negative polarity (−) data voltage. 
     The pixels of each of the first to eighth pixel columns PC 1  to PC 8  are repeatedly arranged in groupings of four colors along the second direction DR 2 . These groupings are arranged so that the pixels of each of the pixel rows are arranged in repeating patterns of two colors. Accordingly, among the pixels of each of the first to eighth pixel columns PC 1  to PC 8 , the pixels of the first and fifth pixel rows PR 1  and PR 5  have the same colors, the pixels of the second and sixth pixel rows PR 2  and PR 6  have the same colors, the pixels of the third and seventh pixel rows PR 3  and PR 7  have the same colors, and the pixels of the fourth and eighth pixel rows PR 4  and PR 8  have the same colors. 
     As an example, the pixels arranged in the first and fifth pixel rows PR 1  and PR 5  of the first, third, fifth, and seventh pixel columns PC 1 , PC 3 , PC 5 , and PC 7  have a red color (R), and the pixels arranged in the second and sixth pixel rows PR 2  and PR 6  of the first, third, fifth, and seventh pixel columns PC 1 , PC 3 , PC 5 , and PC 7  have a green color (G). The pixels arranged in the third and seventh pixel rows PR 3  and PR 7  of the first, third, fifth, and seventh pixel columns PC 1 , PC 3 , PC 5 , and PC 7  have a blue color (B), and the pixels arranged in the fourth and eighth pixel rows PR 4  and PR 8  of the first, third, fifth, and seventh pixel columns PC 1 , PC 3 , PC 5 , and PC 7  have a white color (W). The pixels arranged in the first and fifth pixel rows PR 1  and PR 5  of the second, fourth, sixth, and eighth pixel columns PC 2 , PC 4 , PC 6 , and PC 8  have the blue color (B), and the pixels arranged in the second and sixth pixel rows PR 2  and PR 6  of the second, fourth, sixth, and eighth pixel columns PC 2 , PC 4 , PC 6 , and PC 8  have the white color (W). The pixels arranged in the third and seventh pixel rows PR 3  and PR 7  of the second, fourth, sixth, and eighth pixel columns PC 2 , PC 4 , PC 6 , and PC 8  have the red color (R), and the pixels arranged in the fourth and eighth pixel rows PR 4  and PR 8  of the second, fourth, sixth, and eighth pixel columns PC 2 , PC 4 , PC 6 , and PC 8  have the green color (G). 
     The first red pixel R+ of the first group PG 1  of the first pixel column PC 1  is connected to the first data line D 1 , and the second red pixel R− of the second group PG 2  of the first pixel column PC 1  is connected to the second data line D 2 . The first green pixel G+ of the first group PG 1  of the first pixel column PC 1  is connected to the second data line D 2 , and the second green pixel G+ of the second group PG 2  of the first pixel column PC 1  is connected to the first data line D 1 . The first blue pixel B+ of the first group PG 1  of the first pixel column PC 1  is connected to the first data line D 1 , and the second blue pixel B− of the second group PG 2  of the first pixel column PC 1  is connected to the second data line D 2 . The first white pixel W+ of the first group PG 1  of the first pixel column PC 1  is connected to the second data line D 2 , and the second white pixel W+ of the second group PG 2  of the first pixel column PC 1  is connected to the first data line D 1 . 
     Accordingly, the polarity of the data voltages applied to the pixels displaying a first color in the first group PG 1  of the first pixel column PC 1  is different from the polarity of the data voltages applied to the pixels displaying the first color in the second group PG 2  of the first pixel column PC 1 . Here, the first color may be one of red, green, blue, and white. In the configuration of the present embodiment, three columns of four pixel columns have same-color pixels receiving data voltages of both polarities, and one column of the four pixel columns has same color receiving data voltages of only one polarity. As shown in  FIG. 5 , among the first to fourth pixel columns PC 1  to PC 4 , the pixels arranged in the first, third, and fourth pixel columns PC 1 , PC 3 , and PC 4  receive data voltages of two different polarities, while the pixels of the second pixel column PC 2  all receive data voltages of a single polarity. 
       FIG. 6  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure. 
     Referring to  FIG. 6 , the first to fourth data voltages respectively applied to the first to fourth data lines D 1  to D 4  have polarities of +, +, −, and −, respectively, and the fifth to eighth data voltages respectively applied to the fifth to eighth data lines D 5  to D 8  also have polarities of +, +, −, and − respectively. Therefore, the first, second, fifth, and sixth data lines D 1 , D 2 , D 5 , and D 6  receive a positive polarity (+) data voltage and the third, fourth, seventh, and eighth data lines D 3 , D 4 , D 7 , and D 8  receive a negative polarity (−) data voltage. 
     The pixels are arranged in a repeating pattern of two colors in each pixel row and are arranged in a two-color repeating pattern in each pixel column, although the two patterns are different. 
     As an example, the pixels arranged in the first and fifth pixel rows PR 1  and PR 5  of the first, third, fifth, and seventh pixel columns PC 1 , PC 3 , PC 5 , and PC 7  have a red color (R), and the pixels arranged in the second and sixth pixel rows PR 2  and PR 6  of the first, third, fifth, and seventh pixel columns PC 1 , PC 3 , PC 5 , and PC 7  have a green color (G). The pixels arranged in the third and seventh pixel rows PR 3  and PR 7  of the first, third, fifth, and seventh pixel columns PC 1 , PC 3 , PC 5 , and PC 7  have a blue color (B), and the pixels arranged in the fourth and eighth pixel rows PR 4  and PR 8  of the first, third, fifth, and seventh pixel columns PC 1 , PC 3 , PC 5 , and PC 7  have a white color (W). The pixels arranged in the first and fifth pixel rows PR 1  and PR 5  of the second, fourth, sixth, and eighth pixel columns PC 2 , PC 4 , PC 6 , and PC 8  have the blue color (B), and the pixels arranged in the second and sixth pixel rows PR 2  and PR 6  of the second, fourth, sixth, and eighth pixel columns PC 2 , PC 4 , PC 6 , and PC 8  have the white color (W). The pixels arranged in the third and seventh pixel rows PR 3  and PR 7  of the second, fourth, sixth, and eighth pixel columns PC 2 , PC 4 , PC 6 , and PC 8  have the red color (R), and the pixels arranged in the fourth and eighth pixel rows PR 4  and PR 8  of the second, fourth, sixth, and eighth pixel columns PC 2 , PC 4 , PC 6 , and PC 8  have the green color (G). 
     The first red pixel R+ of the first group PG 1  of the second pixel column PC 2  is connected to the second data line D 2 , and the second red pixel R− of the second group PG 2  of the second pixel column PC 2  is connected to the third data line D 3 . The first green pixel G− of the first group PG 1  of the second pixel column PC 2  is connected to the third data line D 3 , and the second green pixel G+ of the second group PG 2  of the second pixel column PC 2  is connected to the second data line D 2 . The first blue pixel B+ of the first group PG 1  of the second pixel column PC 2  is connected to the second data line D 2 , and the second blue pixel B− of the second group PG 2  of the second pixel column PC 2  is connected to the third data line D 3 . The first white pixel W− of the first group PG 1  of the second pixel column PC 2  is connected to the third data line D 3 , and the second white pixel W+ of the second group PG 2  of the second pixel column PC 2  is connected to the second data line D 2 . 
     Accordingly, the polarity of the data voltages applied to the pixels displaying a first color in the first group PG 1  of the second pixel column PC 2  is different from the polarity of the data voltages applied to the pixels displaying the first color in the second group PG 2  of the second pixel column PC 2 . The first color may be red, green, blue, or white, for example. In the configuration of the present embodiment, two columns of four pixel columns have same-color pixels receiving data voltages of both polarities, and two columns of the four pixel columns have same color receiving data voltages of only one polarity. As shown in  FIG. 6 , among the first to fourth pixel columns PC 1  to PC 4 , the pixels arranged in the second and fourth pixel columns PC 2  and PC 4  receive data voltages of two different polarities, while the pixels of columns PC 1  and PC 3  receive data voltages of a single polarity. 
     In  FIGS. 3 to 6 , the polarity of the data voltages applied to the data lines is inverted in units of four data lines, i.e. data voltage polarity is inverted every four data lines, but it should not be limited thereto or thereby. As another example, the polarity of the data voltages applied to the data lines may be inverted every two data lines. 
       FIG. 7  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure. 
     Referring to  FIG. 7 , each of the first to eighth pixel columns PC 1  to PC 8  includes a plurality of groups consecutively arranged along the second direction DR 2 . Each of the groups of the first pixel column PC 1  includes 2i first pixels PX 1  connected to the first data line D 1  and 2i second pixels PX 2  connected to the second data line D 2 .  FIG. 7  shows the pixels when i=1 as a representative example. Each group includes two first pixels PX 1  and two second pixels PX 2 . 
     Within one group, the pixels of the first pixel column PC 1  are pairwise-alternately connected to the first and second data lines D 1  and D 2 . Among the pixel groups, a first group PG 1  includes the first pixels PX 1  respectively arranged in the first and second pixel rows PR 1  and PR 2  and the second pixels PX 2  respectively arranged in the third and fourth pixel rows PR 3  and PR 4 . A second group PG 2  includes the first pixels PX 1  respectively arranged in the seventh and eighth pixel rows PR 7  and PR 8  and the second pixels PX 2  respectively arranged in the fifth and sixth pixel rows PR 5  and PR 6 . The order of the first and second pixels PX 1  and PX 2  is reversed from one group to the next. As an example, the arrangement of connections between the pixels of the first group PG 1  and the first and second data lines D 1  and D 2  may be symmetric with the connections between the pixels of the second group PG 2  and the first and second data lines D 1  and D 2 , with respect to the gate line G 4 . 
       FIG. 7  shows the first pixel column PC 1  as a representative example, but other pixel columns PC 2  to PC 8  have the same structure as that of the first pixel column PC 1 . Accordingly, the pixels arranged in the first, second, seventh, and eighth pixel rows PR 1 , PR 2 , PR 7 , and PR 8  of each of the first to eighth pixel columns PC 1  to PC 8  are connected to the leftmost of their two respective adjacent data lines, and the pixels arranged in the third, fourth, fifth, and sixth pixel rows PR 3 , PR 4 , PR 5 , and PR 6  of each of the first to eighth pixel columns PC 1  to PC 8  are connected to the rightmost of their two respective adjacent data lines. 
     In the present exemplary embodiment, dummy pixels DPX may be disposed adjacent to the second pixels PX 2  of the third, fourth, fifth, and sixth pixel rows PR 3 , PR 4 , PR 5 , and PR 6  of the first pixel column PC 1 . The dummy pixels DPX are connected to the first data line D 1 . The dummy pixels DPX are disposed adjacent to the second pixels PX 2  of the first pixel column PC 1 , and may also be disposed adjacent to the first pixels PX 1  of the last pixel column. 
     Therefore, the dummy pixels DPX shown in  FIG. 7  are arranged in the third, fourth, fifth, and sixth pixel rows PR 3 , PR 4 , PR 5 , and PR 6 . 
     Since the color arrangements of the pixels shown in  FIG. 7  are substantially the same as the color arrangements of the pixels shown in  FIGS. 3, 5, and 6 , detailed descriptions of the color arrangements of the pixels shown in  FIG. 7  will be omitted. 
       FIG. 8  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure. 
     Referring to  FIG. 8 , each of the first to eighth pixel columns PC 1  to PC 8  includes a plurality of pixel groups consecutively arranged along the second direction DR 2 . Each of the groups of the first pixel column PC 1  includes two first pixels PX 1  connected to the first data line D 1  and two second pixels PX 2  connected to the second data line D 2 . 
     The pixels of the first pixel column PC 1  are organized into pixel groups. Within each group, pixels are alternately connected to the first and second data lines D 1  and D 2 . Within groups, a first group PG 1  includes the first pixels PX 1  respectively arranged in the first and fourth pixel rows PR 1  and PR 4  and the second pixels PX 2  respectively arranged in the second and third pixel rows PR 2  and PR 3 . A second pixel group PG 2  includes the first pixels PX 1  respectively arranged in the sixth and seventh pixel rows PR 6  and PR 7  and the second pixels PX 2  respectively arranged in the fifth and eighth pixel rows PR 5  and PR 8 . The order of second pixels PX 1  and PX 2  are inverted in successive groups. As an example, the connection structure between the pixels of the first group PG 1  and the first and second data lines D 1  and D 2  may be the inverse of the connection structure between the pixels of the second group PG 2  and the first and second data lines D 1  and D 2 , with respect to the fourth gate line G 4 . 
       FIG. 8  shows the first pixel column PC 1  as a representative example, but other pixel columns PC 2  to PC 8  have the same structure as that of the first pixel column PC 1 . Accordingly, the pixels arranged in the first, fourth, sixth, and seventh pixel rows PR 1 , PR 4 , PR 6 , and PR 7  of each of the first to eighth pixel columns PC 1  to PC 8  are connected to a left data line of their two respective adjacent data lines, and the pixels arranged in the second, third, fifth, and eighth pixel rows PR 2 , PR 3 , PR 5 , and PR 8  of each of the first to eighth pixel columns PC 1  to PC 8  are connected to a right data line of their two respective adjacent data lines. 
     In the present exemplary embodiment, dummy pixels DPX may be disposed adjacent to the second pixels PX 2  of the second, third, fifth, and eighth pixel rows PR 2 , PR 3 , PR 5 , and PR 8  of the first pixel column PC 1 . The dummy pixels DPX are connected to the first data line D 1 . The dummy pixels DPX are disposed adjacent to the second pixels PX 2  of the first pixel column PC 1 , and are also disposed adjacent to the first pixels PX 1  of the last pixel column without being disposed in any other pixel column. 
     Therefore, the dummy pixels DPX shown in  FIG. 8  may be arranged in the second, third, fifth, and eighth pixel rows PR 2 , PR 3 , PR 5 , and PR 8 . 
       FIG. 9  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure. 
     Referring to  FIG. 9 , a display apparatus according to the present exemplary embodiment includes first and second dots DOT 1  and DOT 2 . The first dot DOT 1  includes first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  and the second dot DOT 2  includes fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6 . The first and second dots DOT 1  and DOT 2  are alternately arranged along both of the first and second directions DR 1  and DR 2 . Each of the first and second dots DOT 1  and DOT 2  includes three pixels and displays color image information through the three pixels. 
     The first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  are sequentially arranged along the first direction DR 1  in the first dot DOT 1 . As an example, the first pixel SPX 1  displays a first color, e.g., a red color R, the second pixel SPX 2  displays a second color, e.g., a green color G, and the third pixel SPX 3  displays a third color, e.g., a blue color B. A ratio of the horizontal width to the vertical width of each of the first to third pixels SPX 1  to SPX 3  is approximately 1:3. 
     The fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6  are sequentially arranged along the first direction DR 1  in the second dot DOT 2 . As an example, the fourth pixel SPX 4  displays a fourth color, e.g., a red color R, the fifth pixel SPX 5  displays a fifth color, e.g., a green color G, and the sixth pixel SPX 6  displays a sixth color, e.g., a white color W. 
     In  FIG. 9 , the dots DOT(8×4) arranged in eight rows by four columns defined by first, second, third, fourth, fifth, sixth, seventh, and eighth gate lines G 1 , G 2 , G 3 , G 4 , G 5 , G 6 , G 7 , and G 8  and first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth data lines D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , D 7 , D 8 , D 9 , D 10 , D 11 , and D 12  will be described. 
     The dots DTR 1 , DTR 2 , DTR 3 , DTR 4 , DTR 5 , DTR 6 , DTR 7 , and DTR 8  arranged in the eight rows (hereinafter, referred to as first, second, third, fourth, fifth, sixth, seventh, and eighth dot rows) are sequentially arranged along the second direction DR 2 , and the dots DTC 1 , DTC 2 , DTC 3 , and DTC 4  arranged in the four columns (hereinafter, referred to as first, second, third, and fourth dot columns) are sequentially arranged along the first direction DR 1 . The first to eighth dot rows DTR 1  to DTR 8  are connected to the first to eighth gate lines G 1  to G 8  in a one-to-one correspondence. In odd-numbered dot columns DTC 1  and DTC 3 , the first dots DOT 1  are disposed in odd-numbered dot rows DTR 1 , DTR 3 , DTR 5 , and DTR 7  and the second dots DOT 2  are disposed in even-numbered dot rows DTR 2 , DTR 4 , DTR 6 , and DTR 8 . In even-numbered dot columns DTC 2  and DTC 4 , the first dots DOT 1  are disposed in the even-numbered dot rows DTR 2 , DTR 4 , DTR 6 , and DTR 8  and the second dots DOT 2  are disposed in the odd-numbered dot rows DTR 1 , DTR 3 , DTR 5 , and DTR 7 . 
     Each of the first to fourth dot columns DTC 1  to DTC 4  includes a plurality of first dot groups DTG 1  and a plurality of second dot groups DTG 2 , which are alternately arranged along the second direction DR 2 . Each of the first dot groups DTG 1  includes two first dots DOT 1  and two second dots DOT 2 , and each of the second dot groups DTG 2  includes two first dots DOT 1  and two second dots DOT 2 . 
     The first dot column DTC 1  includes a first pixel column SPC 1  in which the first and fourth pixels SPX 1  and SPX 4  are alternately arranged along the second direction DR 2 , a second pixel column SPC 2  in which the second and fifth pixels SPX 2  and SPX 5  are alternately arranged along the second direction DR 2 , and a third pixel column SPC 3  in which the third and sixth pixels SPX 3  and SPX 6  are alternately arranged along the second direction DR 2 . 
     In the first dot column DTC 1 , the first dot DOT 1  of the first dot group DTG 1  includes first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  respectively connected to the first, second, and third data lines D 1 , D 2 , and D 3 , and the second dot DOT 2  of the first dot group DTG 1  includes fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6  respectively connected to the second, third, and fourth data lines D 2 , D 3 , and D 4 . In the first dot column DTC 1 , the first dot DOT 1  of the second dot group DTG 2  includes first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  respectively connected to the second, third, and fourth data lines D 2 , D 3 , and D 4 , and the second dot DOT 2  of the second dot group DTG 2  includes fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6  respectively connected to the first, second, and third data lines D 1 , D 2 , and D 3 . 
     The second dot column DTC 2  includes a fourth pixel column SPC 4  in which the fourth and first pixels SPX 4  and SPX 1  are alternately arranged along the second direction DR 2 , a fifth pixel column SPC 5  in which the fifth and second pixels SPX 5  and SPX 2  are alternately arranged along the second direction DR 2 , and a sixth pixel column SPC 6  in which the sixth and third pixels SPX 6  and SPX 3  are alternately arranged along the second direction DR 2 . 
     In the second dot column DTC 2 , the first dot DOT 1  of the first dot group DTG 1  includes first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  respectively connected to the fifth, sixth, and seventh data lines D 5 , D 6 , and D 7 , and the second dot DOT 2  of the first dot group DTG 1  includes fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6  respectively connected to the fourth, fifth, and sixth data lines D 4 , D 5 , and D 6 . In the second dot column DTC 2 , the first dot DOT 1  of the second dot group DTG 2  includes first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  respectively connected to the fourth, fifth, and sixth data lines D 4 , D 5 , and D 6 , and the second dot DOT 2  of the second dot group DTG 2  includes fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6  respectively connected to the fifth, sixth, and seventh data lines D 5 , D 6 , and D 7 . 
     First to twelfth data voltages are respectively applied to the first to twelfth data lines D 1  to D 12  and each of the first to twelfth data voltages has a positive (+) or negative (−) polarity with respect to the reference voltage applied to the common electrode CE (refer to  FIG. 2 ).  FIG. 9  shows the polarity of the data voltages applied to the pixels in an i-th frame, and thus the polarity of the data voltages applied to the pixels in an (i+1)th frame is inverted. That is, the data driver  400  shown in  FIG. 1  inverts the polarity of the data voltages applied to the data lines D 1  to Dn every frame. 
     The polarity of the first to twelfth data voltages is inverted every 6j data lines in the first direction DR 1 . In detail, when j=1 in  FIG. 9 , the first to sixth data voltages respectively applied to the first to sixth data lines D 1  to D 6  have the polarities of +, −, +, −, +, and −, respectively, and the seventh to twelfth data voltages respectively applied to the seventh to twelfth data lines D 7  to D 12  have the polarities of −, +, −, +, −, and +, respectively. Therefore, the first, third, fifth, eighth, tenth, and twelfth data lines D 1 , D 3 , D 5 , D 8 , D 10 , and D 12  receive a positive polarity (+) data voltage and the second, fourth, sixth, seventh, ninth, and eleventh data lines D 2 , D 4 , D 6 , D 7 , D 9 , and D 11  receive a negative polarity (−) data voltage. 
     In  FIG. 9 , the positive polarity (+) data voltages are represented by R+, G+, B+, and W+ and the negative polarity (−) data voltages are represented by R−, G−, B−, and W−. The arrangement order of the pixels should not be limited to that shown in  FIG. 9 . 
     The pixels arranged in the first and fourth pixel columns SPC 1  and SPC 4  have the red color R, the pixels arranged in the second and fifth pixel columns SPC 2  and SPC 5  have the green color G, and the pixels arranged in the third and sixth pixel columns SPC 3  and SPC 6  have the blue or white color B or W. 
     The first pixels SPX 1  included in the first dot group DTG 1  and the first pixel column SPC 1  are connected to the first data line D 1  to receive the positive polarity red data voltage R+. The fourth pixels SPX 4  included in the first dot group DTG 1  and the first pixel column SPC 1  are connected to the second data line D 2  to receive the negative polarity red data voltage R−. The first pixels SPX 1  included in the second dot group DTG 2  and the first pixel column SPC 1  are connected to the second data line D 2  to receive the negative red data voltage R−. The fourth pixels SPX 4  included in the second dot group DTG 2  and the first pixel column SPC 1  are connected to the first data line D 1  to receive the positive polarity red data voltage R+. The second and third pixel columns SPC 2  and SPC 3  have a similar connection structure to that of the first pixel column SPC 1  except for the colors. 
     Accordingly, the polarity of the data voltages applied to the pixels displaying a first color in the first dot DOT 1  of the first dot group DTG 1  is different from the polarity of the data voltages applied to the pixels displaying the first color in the first dot DOT 1  of the second dot group DTG 2 . The polarity of the data voltages applied to the pixels displaying the second, third, and fourth colors becomes different in accordance with the dot groups in which the pixels displaying the second, third, and fourth colors are included. 
     In the present exemplary embodiment, dummy pixels DPX may be disposed adjacent to the second dots DOT 2  of the first dot group DTG 1  and the first dot column DTC 1 , and are also disposed adjacent to the first dots DOT 1  of the second dot group DTG 2  of the first dot column DTC 1 . The dummy pixels DPX are connected to the first data line D 1 . Although not shown in figures, the dummy pixels DPX may also be disposed adjacent to the first dots DOT 1  and/or the second dots DOT 2  of the last pixel column. 
       FIG. 10A  is a plan view showing a state in which the red pixels of  FIG. 9  are turned on,  FIG. 10B  is a plan view showing a state in which the green pixels of  FIG. 9  are turned on,  FIG. 10C  is a plan view showing a state in which the blue pixels of  FIG. 9  are turned on, and  FIG. 10D  is a plan view showing a state in which all pixels of  FIG. 9  are turned on. 
     Referring to  FIG. 10A , the first pixel SPX 1  receives a positive polarity red data voltage R+ and the fourth pixel SPX receives a negative polarity red data voltage R−. Although the positive red data voltage R+ and the negative red data voltage R− have the same grayscale, a difference in voltage occurs between the positive polarity (+) red data voltage R+ and the positive polarity (−) red data voltage R− due to a kickback voltage. Thus, a difference in brightness occurs between the first and fourth pixels SPX 1  and SPX 4 . For convenience of explanation, the first and second pixels SPX 1  and SPX 4  are represented by different hatchings in  FIG. 10A . 
     When a sum of polarities of the data voltages applied to the pixels arranged in the same pixel row is biased to the positive (+) polarity or the negative (−) polarity, the common voltage ripples to a positive direction or a negative direction due to a coupling phenomenon between the common electrode and the data lines. 
     However, as shown in  FIG. 10A , the first and fourth pixels SPX 1  and SPX 4  are arranged in repeating manner along the first direction DR 1 . That is, the number of the first pixels SPX 1  is equal to the number of the fourth pixels SPX 4  in one pixel row. Accordingly, the common voltage is prevented from being rippled to the positive or negative direction with respect to the reference voltage, and thus horizontal crosstalk is prevented from occurring. 
     The first and fourth pixels SPX 1  and SPX 4  are arranged in repeating manner along the second direction DR 2 , and the number of the first pixels SPX 1  is equal to the number of the fourth pixels SPX 4  in one dot column. Accordingly, brightness difference is prevented from occurring between the dot columns, and thus a moving line-stain, or a vertical line perceived when the i-th frame is changed to the (i−1)th frame, is prevented from occurring. 
     Similarly, the second and fifth pixels SPX 2  and SPX 5  are arranged in repeating manner along the first and second directions DR 1  and DR 2 , and the number of the second pixels SPX 2  is equal to the number of the fifth pixels SPX 5  in the same dot column and in the same dot row. The second pixel SPX 2  receives a positive polarity green data voltage G+ and the fifth pixel SPX 5  receives a negative polarity green data voltage G−. Therefore, brightness difference does not occur between dot rows and between dot columns, and thus horizontal crosstalk and moving line-stains are prevented from occurring. 
     Referring to  FIG. 10C , the third pixel SPX 3  of the first dot group DTG 1  receives a positive polarity blue data voltage B+ and the third pixel SPX 3  of the second dot group DTG 2  receives a negative polarity blue data voltage B−. The first and second dot groups DTG 1  and DTG 2  are alternately arranged along the second direction DR 2 . The third sub pixels SPX 3  are arranged in different dot rows in the first direction DR 1 . Accordingly, brightness difference does not occur between dot rows and between dot columns with respect to the blue color, and thus horizontal crosstalk and moving line-stains are prevented from occurring. 
     As described above, the positive and negative pixels displaying the red, green, blue, and white pixels are arranged in repeating manner along the dot rows and the dot columns, and the number of positive pixels is equal to the number of negative pixels with respect to each of the red, green, blue, and white pixels. Thus, although all pixels are substantially and simultaneously operated as shown in  FIG. 10D , brightness difference does not occur between the dot rows and the dot columns. As a result, the horizontal crosstalk phenomenon and the moving line-stain phenomenon may be prevented from occurring. 
       FIG. 11  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure. 
     Referring to  FIG. 11 , a display apparatus according to the present exemplary embodiment includes first and second dots DOT 1  and DOT 2 . The first dot DOT 1  includes first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  and the second dot DOT 2  includes fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6 . The first and second dots DOT 1  and DOT 2  are arranged in alternating manner along the first and second directions DR 1  and DR 2 . 
     In the first dot column DTC 1 , the first dots DOT 1  of first and seventh dot rows DTR 1  and DTR 7  each include first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  respectively connected to the first, second, and third data lines D 1 , D 2 , and D 3 , and the second dots DOT 2  of the second and eighth dot rows DTR 2  and DTR 8  each include fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6  respectively connected to the first, second, and third data lines D 1 , D 2 , and D 3 . In the first dot column DTC 1 , the first dots DOT 1  of the third and fifth dot rows DTR 3  and DTR 5  each include first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  respectively connected to the second, third, and fourth data lines D 2 , D 3 , and D 4 , and the second dots DOT 2  of the fourth and sixth dot rows DTR 4  and DTR 6  each include fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6  respectively connected to the second, third, and fourth data lines D 2 , D 3 , and D 4 . 
     In the second dot column DTC 2 , the first dots DOT 1  of the second and eighth dot rows DTR 2  and DTR 8  each include first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  respectively connected to the fourth, fifth, and sixth data lines D 4 , D 5 , and D 6 , and the second dots DOT 2  of the first and seventh dot rows DTR 1  and DTR 7  each include fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6  respectively connected to the fourth, fifth, and sixth data lines D 4 , D 5 , and D 6 . In the second dot column DTC 2 , the first dots DOT 1  of the fourth and sixth dot rows DTR 4  and DTR 6  each include first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  respectively connected to the fifth, sixth, and seventh data lines D 5 , D 6 , and D 7 , and the second dots DOT 2  of the third and fifth dot rows DTR 3  and DTR 5  each include fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6  respectively connected to the fifth, sixth, and seventh data lines D 5 , D 6 , and D 7 . 
     In the first pixel column SPC 1 , the first pixels SPX 1  receiving the positive polarity red data voltage R+ are disposed in the first and seventh dot rows DOT 1  and DOT 7 , and the first pixels SPX 1  receiving the negative polarity red data voltage R− are disposed in the third and fifth dot rows DTR 3  and DTR 5 . In the first pixel column SPC 1 , the second pixels SPX 2  receiving the positive polarity red data voltage R+ are disposed in the second and eighth dot rows DTR 2  and DTR 8 , and the second pixels SPX 2  receiving the negative red data voltage R− are disposed in the fourth and sixth dot rows DTR 4  and DTR 6 . Accordingly, the polarities of the data voltages of +, +, −, and − are inverted to the polarities of −, −, +, and + in the same pixel column along the second direction DR 2 . 
     The second pixel column SPC 2  has the similar structure as the first pixel column SPC 1  except with different colors. 
     In the third pixel column SPC 3 , the third pixels SPX 3  receiving the positive polarity blue data voltage B+ are disposed in the first and seventh dot rows DOT 1  and DOT 7 , and the third pixels SPX 3  receiving the negative polarity blue data voltage B− are disposed in the third and fifth dot rows DTR 3  and DTR 5 . In the third pixel column SPC 3 , the sixth pixels SPX 6  receiving the positive polarity white data voltage W+ are disposed in the second and eighth dot rows DTR 2  and DTR 8 , and the sixth pixels SPX 6  receiving the negative polarity white data voltage W− are disposed in the fourth and sixth dot rows DTR 4  and DTR 6 . 
     As described above, the positive and negative pixels displaying the red, green, blue, and white colors are repeatedly arranged in the dot rows and the dot columns. Thus, brightness difference does not occur between the dot rows and the dot columns. As a result, the horizontal crosstalk phenomenon and the moving line-stain phenomenon may be prevented from occurring. 
       FIG. 12  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure. 
     Referring to  FIG. 12 , a display apparatus according to the present exemplary embodiment includes first and second dots DOT 1  and DOT 2 . The first dot DOT 1  includes first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  and the second dot DOT 2  includes fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6 . The first and second dots DOT 1  and DOT 2  are alternately arranged in the first and second directions DR 1  and DR 2 . 
     In the first dot column DTC 1 , the first dot DOT 1  of first and seventh dot rows DTR 1  and DTR 7  includes first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  respectively connected to the first, second, and third data lines D 1 , D 2 , and D 3 , and the second dot DOT 2  of the second and eighth dot rows DTR 2  and DTR 8  includes fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6  respectively connected to the second, third, and fourth data lines D 2 , D 3 , and D 4 . In the first dot column DTC 1 , the first dot DOT 1  of the third and fifth dot rows DTR 3  and DTR 5  includes first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  respectively connected to the second, third, and fourth data lines D 2 , D 3 , and D 4 , and the second dot DOT 2  of the fourth and sixth dot rows DTR 4  and DTR 6  includes fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6  respectively connected to the first, second, and third data lines D 1 , D 2 , and D 3 . 
     In the second dot column DTC 2 , the first dot DOT 1  of the second and eighth dot rows DTR 2  and DTR 8  includes first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  respectively connected to the fifth, sixth, and seventh data lines D 5 , D 6 , and D 7 , and the second dot DOT 2  of the first and seventh dot rows DTR 1  and DTR 7  includes fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6  respectively connected to the fourth, fifth, and sixth data lines D 4 , D 5 , and D 6 . In the second dot column DTC 2 , the first dot DOT 1  of the fourth and sixth dot rows DTR 4  and DTR 6  includes first, second, and third pixels SPX 1 , SPX 2 , and SPX 3  respectively connected to the fourth, fifth, and sixth data lines D 4 , D 5 , and D 6  and the second dot DOT 2  of the third and fifth dot rows DTR 3  and DTR 5  includes fourth, fifth, and sixth pixels SPX 4 , SPX 5 , and SPX 6  respectively connected to the fifth, sixth, and seventh data lines D 5 , D 6 , and D 7 . 
     In the first pixel column SPC 1 , the first pixels SPX 1  receiving the positive polarity red data voltage R+ are disposed in the first and seventh dot rows DOT 1  and DOT 7 , and the first pixels SPX 1  receiving the negative polarity red data voltage R− are disposed in the third and fifth dot rows DTR 3  and DTR 5 . In the first pixel column SPC 1 , the fourth pixels SPX 4  receiving the positive polarity red data voltage R+ are disposed in the fourth and sixth dot rows DTR 4  and DTR 6 , and the fourth pixel SPX 4  receiving the negative polarity red data voltage R− is disposed in the second and eighth dot rows DTR 2  and DTR 8 . Accordingly, the pixels receiving the positive polarity red data voltage R+ and the pixels receiving the negative polarity red data voltage R− are reversed in order every four dot rows. That is, the polarities of the data voltages of +, −, −, and + are inverted to the polarities of −, +, +, and − in the same pixel column along the second direction DR 2 . 
     The second and third pixel columns SPC 2  and SPC 3  have a similar structure as the first pixel column SPC 1  but with different pixel colors. 
     As described above, the positive and negative pixels displaying the red, green, blue, and white pixels are arranged in repeating order along the dot rows and the dot columns. Thus, brightness difference does not occur between the dot rows and the dot columns. As a result, the horizontal crosstalk phenomenon and the moving line-stain phenomenon may be prevented from occurring. 
       FIG. 13  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure. 
     Referring to  FIG. 13 , pixels arranged in a first pixel column between the first and second data lines D 1  and D 2  are alternately connected to the first and second data lines D 1  and D 2  within each pixel group. More specifically, the connection structure between the pixels and the first and second data lines D 1  and D 2  changes every 4i pixels. When i=1, among the pixels arranged in the first to fourth pixel rows PR 1  to PR 4 , the pixels of the first and third pixel rows PR 1  and PR 3  are connected to the first data line D 1  and the pixels of the second and fourth pixel rows PR 2  and PR 4  are connected to the second data line D 2 . On the contrary, among the pixels arranged in the fifth to eighth pixel rows PR 5  to PR 8 , the pixels of the fifth and seventh pixel rows PR 5  and PR 7  are connected to the second data line D 2  and the pixels of the sixth and eighth pixel rows PR 6  and PR 8  are connected to the first data line D 1 . 
     Among the pixels in the first pixel column PC 1 , the red pixel R is disposed in odd-numbered pixel rows, i.e., the first, third, fifth, and seventh pixel rows PR 1 , PR 3 , PR 5 , and PR 7 , and the blue pixel B is disposed in even-numbered pixel rows, i.e., the second, fourth, sixth, and eighth pixel rows PR 2 , PR 4 , PR 6 , and PR 8 . Among the pixels arranged in the second pixel column PC 2 , the green pixel G is disposed in the odd-numbered pixel rows PR 1 , PR 3 , PR 5 , and PR 7 , and the white pixel W is disposed in the even-numbered pixel rows PR 2 , PR 4 , PR 6 , and PR 8 . Among the pixels arranged in the third pixel column PC 3 , the blue pixel B is disposed in the odd-numbered pixel rows PR 1 , PR 3 , PR 5 , and PR 7 , and the red pixel R is disposed in the even-numbered pixel rows PR 2 , PR 4 , PR 6 , and PR 8 . Among the pixels arranged in the fourth pixel column PC 4 , the white pixel W is disposed in the odd-numbered pixel rows PR 1 , PR 3 , PR 5 , and PR 7 , and the green pixel G is disposed in the even-numbered pixel rows PR 2 , PR 4 , PR 6 , and PR 8 . 
     The pixels forming one column are connected to the left and right data lines in groupings of 4i pixels. Accordingly, the red pixels R+ of the first and third pixel rows PR 1  and PR 3  of the first pixel column PC 1  are connected to the first data line D 1 , and the blue pixels B− of the second and fourth pixel rows PR 2  and PR 4  of the first pixel column PC 1  are connected to the second data line D 2 . In addition, the red pixels R− of the fifth and seventh pixel rows PR 5  and PR 7  of the first pixel column PC 1  are connected to the second data line D 2 , and the blue pixels B+ of the sixth and eighth pixel rows PR 6  and PR 8  of the first pixel column PC 1  are connected to the first data line D 1 . 
     Therefore, although the polarity of the data voltages applied to the first and second data lines D 1  and D 2  is not changed within one frame period, the positive pixels and the negative pixels are alternately arranged with each other within the one pixel column. In particular, the pixels having the same color are disposed to periodically have different polarities from each other within any given pixel column. As an example, the pixels having the same color may have different polarities every four pixel rows in at least three pixel columns of each grouping of four successive pixel columns. Each of the pixels has a ratio of a horizontal width to a vertical width of 1:3. 
       FIG. 14  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure. 
     Referring to  FIG. 14 , the connection structure between the pixels and their adjacent left/right data lines changes every 4i pixels in each pixel column. For instance, when i=1, among the pixels arranged in the first to fourth pixel rows PR 1  to PR 4  of the first pixel column PC 1 , the pixels arranged in the first and fourth pixel rows PR 1  and PR 4  are connected to the first data line D 1 , and the pixels arranged in the second and third pixel rows PR 2  and PR 3  are connected to the second data line D 2 . On the contrary, among the pixels arranged in the fifth to eighth pixel columns PR 5  to PR 8 , the pixels arranged in the fifth and eighth pixel rows PR 5  and PR 8  are connected to the second data line D 2 , and the pixels arranged in the sixth and seventh pixel rows PR 6  and PR 7  are connected to the first data line D 1 . 
     The color arrangement of the pixels shown in  FIG. 14  is the same as the color arrangement of the pixels shown in  FIG. 13 , and thus detailed descriptions of the color arrangement of the pixels shown in  FIG. 14  will be omitted. 
     The pixels forming one pixel column are connected to the left and right data lines in groupings of 4i pixels. Accordingly, the red pixels R+ of the first and seventh pixel rows PR 1  and PR 7  of the first pixel column are connected to the first data line D 1 , and the blue pixels B− of the second and eighth pixel rows PR 2  and PR 8  of the first pixel column are connected to the second data line D 2 . In addition, the red pixels R− of the third and fifth pixel rows PR 3  and PR 5  of the first pixel column PC 1  are connected to the second data line D 2 , and the blue pixels B+ of the fourth and sixth pixel rows PR 4  and PR 6  of the first pixel column PC 1  are connected to the first data line D 1 . 
     Therefore, although the polarity of the data voltages applied to the first and second data lines D 1  and D 2  is not changed within one frame period, the positive pixels and the negative pixels are alternately arranged within a given pixel column. In particular, the pixels having the same color are disposed to periodically have different polarities from each other within a given pixel column. As an example, the pixels having the same color may have different polarities every four pixel rows in at least three pixel columns of a four pixel column grouping. 
       FIG. 15  is a plan view showing a portion of a liquid crystal panel according to another exemplary embodiment of the present disclosure. 
     Referring to  FIG. 5 , the pixels forming one pixel column are connected to their adjacent left and right data lines in groupings of 4i pixels. Accordingly, the red pixels R+ of the first and seventh pixel rows PR 1  and PR 7  of the first pixel column PC 1  are connected to the first data line D 1 , and the blue pixels B+ of the second and eighth pixel rows PR 2  and PR 8  of the first pixel column PC 1  are connected to the first data line D 1 . In addition, the red pixels R− of the third and fifth pixel rows PR 3  and PR 5  of the first pixel column PC 1  are connected to the second data line D 2 , and the blue pixels B− of the fourth and sixth pixel rows PR 4  and PR 6  of the first pixel column PC 1  are connected to the second data line D 2 . 
     Therefore, although the polarity of the data voltages applied to the first and second data lines D 1  and D 2  is not changed within one frame period, the positive pixels and the negative pixels are alternately arranged within one pixel column. In particular, the pixels having the same color are disposed to periodically have different polarities from each other within one pixel column. As an example, the pixels having the same color may have different polarities every four pixel rows, for at least three of every four adjacent pixel columns. 
     As described above, positive and negative pixels displaying the red, green, blue, and white colors are repeatedly arranged within dot rows. Thus, brightness difference does not occur between different dot rows and different dot columns. As a result, the horizontal crosstalk phenomenon and the moving line-stain phenomenon may be prevented from occurring. 
     Although the exemplary embodiments of the present invention have been described, it is understood that the present invention should not be limited to these exemplary embodiments but various changes and modifications can be made by one ordinary skilled in the art within the spirit and scope of the present invention as hereinafter claimed. Various features of the above described and other embodiments can be mixed and matched in any manner, to produce further embodiments consistent with the invention.