Patent Publication Number: US-11035739-B2

Title: Integrated electronic device comprising a temperature sensor and sensing method

Description:
BACKGROUND 
     Technical Field 
     The present disclosure relates to an integrated electronic device comprising a temperature sensor and to the relevant sensing method. 
     Description of the Related Art 
     As is known, temperature sensors have a plurality of applications. For instance, they may be stand-alone components, which supply at output the temperature value of an environment. In addition, they may be a component of a more complex system, which includes other elements, the performance whereof varies with temperature. These variations are frequently undesirable so that it is useful to detect the existing temperature and compensate for the performance variations and make them independent of temperature. Also when the performance variation with temperature is the desired effect of the complex system, frequently it is in any case useful to have direct information on the local absolute temperature value. 
     Temperature sensors are built in very different ways, in particular according to the application and to whether they are of a stand-alone type or they are integrated in a more complex system. In the former case, in fact, frequently no problems of dimensions exist, and simpler but more cumbersome solutions may be used, whereas in the latter case the possibility of an integrated implementation with the other components of the system, in addition to the dimensions and consumption, may be important. 
     In case of temperature sensors integrated in an electronic circuit, it is known to exploit the variability with temperature of the base-emitter voltage of bipolar transistors. In fact, it is well known that this voltage has a variation of some millivolts per degree centigrade. By detecting the variation of voltage with a sensing circuit and amplifying it, with appropriate algorithms it is possible to determine the local temperature within the electronic circuit. This solution, albeit extremely widely adopted, is not free from disadvantages, due for example to the need of implementing bipolar components for MOS technology circuits and/or to the high consumption of the temperature sensor and the associated components, for example of conditioning and amplification stages associated to the temperature sensor. Furthermore, this solution has the disadvantage of giving rise to high noise, which may be disadvantageous in some applications. On the other hand, the known solutions have consumption levels that are the higher, the lower the level of maximum accepted noise. Not least, this solution does not always solve the problem since the base-emitter voltage read is generally compared with a reference value, generated through a different stage, such as a band-gap circuit, which in turn may vary with temperature. This behavior introduces an error in the output signal, so that the temperature value read may not have the desired precision. 
     In some known solutions, the sensing circuit comprises a resistive bridge for compensating for the temperature dependence in the reference element or circuit. However, also this solution is not free from disadvantages in so far as it introduces an undesirable consumption level. 
     More innovative solutions comprise, for example, the use of MEMS (Micro-Electrical-Mechanical System) technologies that enable creation of elements that may undergo mechanical deformation as the temperature varies (see, for example, “A Micromachined Silicon Capacitive Temperature Sensor for Radiosonde Applications” by Hong-Yu Ma, Qing-An Huang, Ming Qin, Tingting Lu, E-ISBN: 978-1-4244-5335-1/09, 2009 IEEE). Other known solutions are based upon the use of new materials (see, for example, “High-performance bulk silicon interdigital capacitive temperature sensor based on graphene oxide” by Chun-Hua Cai and Ming Qin, ELECTRONICS LETTERS, 28 Mar. 2013 Vol. 49 No. 7, ISSN: 0013-5194). 
     These solutions are, however, difficult to integrate in digital systems and thus not universally applicable. 
     BRIEF SUMMARY 
     One aim of the present disclosure is to provide a temperature sensor that overcomes the drawbacks of the prior art. 
     According to the present disclosure, an integrated electronic device exploits the fact that a reverse biased PN junction has an equivalent capacitance variable in a known way with temperature. This capacitance may be compared with a reference capacitance provided to have a negligible dependence upon temperature. A known sensing circuit, for example a switched capacitor operational amplifier, may then detect the capacitance variation with temperature and output a voltage that varies directly with the capacitance variation. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       For a better understanding of the present disclosure preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein: 
         FIG. 1  shows the plot of the junction capacitance C j  of a junction diode as a function of the voltage applied V d ; 
         FIG. 2  shows the variation of junction capacitance C j  of a junction diode as a function of temperature; 
         FIG. 3  shows a simplified circuit diagram of a present device according to a first embodiment of the present disclosure; 
         FIG. 4  shows the plot of electrical signals in the circuit of  FIG. 3 ; 
         FIG. 5  shows a simplified circuit diagram of a present device according to a second embodiment of the present disclosure; 
         FIG. 6  shows the plot of electrical signals in the circuit of  FIG. 5 ; 
         FIG. 7  shows the plot of the output voltage V o  of the circuit of  FIG. 5 ; and 
         FIG. 8  shows a possible implementation of a temperature sensor according to the embodiments of  FIGS. 3 and 5 . 
     
    
    
     DETAILED DESCRIPTION 
     Present sensors according to embodiments of the present disclosure exploit the dependence upon temperature of the capacitance of a reverse biased PN-junction diode. 
     In fact, as is known, the contact potential (or built-in voltage) V bi  of a reverse biased PN diode is given by: 
                       V   bi     ⁡     (   T   )       =         k   ·   T     q     ·     ln   ⁡     (         N   A     ·     N   D           n   i     ⁡     (   T   )         )                 (   1   )               
where K is Boltzmann&#39;s constant, T is the temperature in degrees Kelvin, q is the charge of the electron, N A  is the concentration of acceptor atoms, N D  is the concentration of donor atoms, and n i (t) is the concentration of the intrinsic carriers in the PN diode. In particular, the concentration n i  of the intrinsic carriers depends upon the temperature T on the basis of Eq. (2):
 
                     n   i   2     =     0.961   ·     10   33     ·     T   3     ·     e       -       E   Geff     ⁡     (   T   )           k   ·   T                   (   2   )               
where E Geff  is the energy gap of the material used for integration of the diode.
 
     In a PN diode, by applying a reverse voltage V d  thereto, a charge Q j  is stored on the junction: 
                       Q   j     ⁡     (   T   )       =         2   ·   q   ·     ɛ   s       ⁢           N   D     ·     N   A           N   D     +     N   A         ⁡     [         V     b   ⁢   i       ⁡     (   T   )       -     V   d       ]                   (   3   )               
where ε S  is the dielectric constant of the semiconductor. As may be noted, the accumulated charge Q j  depends upon the temperature through the contact potential V bi , as well as upon the reverse voltage V d .
 
     The junction capacitance C j  of the diode is thus: 
                       C   j     ⁡     (     T   ,     V   ⁢   d       )       =         A   D     ·       d   ⁢       Q   j     ⁡     (     T   ,   V     )           d   ⁢   V         =       A   D     ·           Q   j     ⁡     (     T   ,     V   ⁢   d       )       -       Q   j     ⁡     (     T   ,       V   ⁢   d     -     d   ⁢   V         )           d   ⁢   V                   (   4   )               
where A is the area of the PN junction.
 
     In practice, a PN diode formed in a silicon substrate has a junction capacitance depending both upon the biasing voltage and the temperature, as illustrated respectively in  FIG. 1  (with a solid line) and in  FIG. 2 , calculated respectively at constant temperature (T=25° C.) and at constant reverse biasing voltage (V r =0.625V).  FIG. 1  also shows with a dashed line the plot of the junction capacitance determined using more accurate calculations. 
     In particular, as may be noted from  FIG. 2 , in temperature ranges wherein integrated circuits normally operate, the junction capacitance C j  has an approximately linear plot as a function of temperature. Consequently, to a first approximation, the reading of the junction capacitance C j  of a reverse biased PN diode has a relation of direct proportionality with the local temperature, and reading of the junction capacitance and/or of its variation supplies direct information on the temperature or on the temperature variation. 
       FIG. 3  shows a temperature sensor  1  that exploits the principle explained above. 
     In detail, the temperature sensor  1  comprises a sensor input  2  supplied with a sensor excitation signal, i.e., the timed biasing voltage DRH. A sensing diode  3 , of a PN-junction type, has its cathode coupled to the sensor input  2  and its anode coupled to an inverting input  7  of an operational amplifier  4 . A reference capacitor  5 , having a reference capacitance C R , is coupled between the sensor input  2  and a non-inverting input  8  of the operational amplifier  4 . The reference capacitance C R  is chosen so as to have the same value as the junction capacitance C j  at room temperature. 
     The inputs  7 ,  8  of the operational amplifier  4  are both coupled to a first reference potential line  10 , set at a first common mode potential V CMin , through a respective input switch  11 . The input switches  11  are controlled by a same reset signal R. 
     The operational amplifier  4  is of a fully differential type, has a pair of outputs  15 ,  16  and has a capacitive feedback formed by a first and a second feedback capacitors  17 ,  18 , which have the same feedback capacitance C i . In detail, the first feedback capacitor  17  is coupled between the first output  15  and the inverting input  7 , and the second feedback capacitor  18  is coupled between the second output  16  and the non-inverting input  8  of the operational amplifier  4 . The outputs  15 ,  16  of the operational amplifier  4  are further coupled to a second reference potential line  20 , set at a second common mode potential V CMout , through a respective output switch  21 . The output switches  21  are controlled by the reset signal R. 
     A timed biasing voltage DRH is supplied on the input  2  and switches between a low value (for example, 0.625 V) and a high value V DRH  (for example, 1.25V). In particular, the low value is in any case positive for keeping the sensing diode  3  (which has its anode coupled to the virtual ground on the inverting input  7  of the operational amplifier  4 ) reverse biased in all the sensing phases, and the high value is chosen for generating a voltage step ΔV of a preset value, as explained in detail hereinafter. 
     In practice, in the temperature sensor  1  of  FIG. 3 , the sensing diode  3  and the reference capacitor  5  form a sensing element  25  and the operational amplifier  4 , with the capacitive feedback, forms a switched capacitor differential amplifier stage of a known type and widely used, for example, in reading of MEMS structures. 
     The operational amplifier  4  and the relevant feedback network  17 ,  18 ,  11 ,  21  may be incorporated in an ASIC (Application Specific Integrated Circuit)  28 . 
     The sensing diode  3  and the reference capacitor  5  may be formed in a semiconductor material chip, as described in greater detail with reference to  FIG. 8 . 
     The outputs  15  and  16  of the operational amplifier  4  are coupled to a processing stage  30 , generally external to the temperature sensor  1  but possibly also integrated in the ASIC. The processing stage  30  may comprise circuits for amplification of the output voltage V o  and for analog-to-digital conversion. 
     Finally, a timing stage  31  generates biasing/timing signals for the temperature sensor  1  and for the processing stage  30 , such as the reset signal R, the timed biasing voltage DRH, and a reading acquisition signal S for the processing stage  30 . 
     Sensing of the output voltage V o  of the operational amplifier  4  is obtained according to the timing, illustrated in  FIG. 4 , which includes the succession of a reset phase and a sensing phase that follow each other in an acquisition period T 1  equal to one half of a sensing period T 2 =2·T 1 , as described in detail hereinafter. In particular, the reset signal R and the reading acquisition signal S have the same period, but different duty cycle. For this reason, hereinafter the sensing period T 2  is considered as being divided into two half periods T 11  and T 12 , corresponding to two successive periods of the acquisition period T 1 . 
     Reset Phase—First Half Period T 11    
     At instant to the reset signal R switches to the high state, causing the input switches  11  and of the output switches  21  to switch off. Consequently, the inputs  7 ,  8  of the operational amplifier  4  are coupled to the first common mode potential V CMin  (for example, 0.625 V, i.e., to the low value of the timed biasing voltage DRH), and the outputs  15 ,  16  of the operational amplifier  4  are coupled to the second common mode potential V CMout  (for example, 1 V), thus resetting the operational amplifier  4 . 
     In this step, the timed biasing voltage DRH (for example, 0.625 V) is low, as likewise is the reading acquisition signal S. The output voltage V o  is thus not acquired by the signal processing stage  30 . 
     Next, at instant t 1 , the reset signal R switches to the low state, causing opening of the input and output switches  11 ,  21  and causing the input nodes  7 ,  8  and output nodes  15 ,  16  of the operational amplifier  4  to be independent. The timed biasing voltage DRH is low, as is the reading acquisition signal S. 
     The step t 1 -t 2  may be adopted in case of use of the correlated double sampling (CDS) technique. During this step, in fact, with the technique referred to, offset sampling is carried out, which may then be subtracted during the sensing phase. In this way, it is possible to reduce the offset. 
     Sensing Phase—First Half Period T 11    
     At the instant t 2 , the timed biasing voltage DRH has a rising edge and reaches a value that reverse biases the sensing diode  3 , for example, at 1.25 V. In this condition, neglecting possible losses, a reverse current flows in the sensing diode  3 . Further, a reference current flows in the reference capacitor  5 . There is thus a charge displacement Q 1  (according to the law in Eq. (3), where V d  is here the timed biasing voltage DRH) from the sensing diode  3  to the operational amplifier  4  and a charge displacement Q 2  (according to the law Q=C/ΔV, where ΔV is the step of the timed biasing voltage DRH) from the reference capacitor  5  to the operational amplifier  4 . As a result of the half bridge configuration of the sensing element  25  and of the feedback network of the amplifier  26 , the latter is traversed by a differential charge Q 2 −Q 1  that is a function of the amplitude of the step ΔV of the timed biasing voltage DRH, of the capacitance difference ΔC (difference between the junction capacitance C j  of the sensing diode, and the capacitance C R  of the reference capacitor  5 ), and of the capacitances C i  of the feedback capacitors  17 ,  18 . 
     Consequently, between the outputs  15  and  16  of the operational amplifier  4  there is an output voltage V o   
                       V   o     ⁡     (   t   )       ∝         Δ   ⁢   C       C   i       ⁢   Δ   ⁢   V             (   5   )               
which is acquired by the signal processing stage by virtue of the high value of reading acquisition signal S.
 
     In this connection, since the time plot of the output voltage V o  has a transient step, acquisition of the output voltage V o  is made during the subsequent steady state step regime, and the involved time is calculated taking into account the bandwidth of the operational amplifier  4 . 
     This step terminates at instant t 3 , where a new period T 1  of the reading acquisition signal S and of the reset signal R and the second half period T 12  of the sensing signal DRH start. 
     Reset Phase—Second Half Period T 12    
     At instant t 3 , the reset signal R switches to high, and the reading acquisition signal S switches to low. The operational amplifier  4  is thus reset again, in a way generally similar to what described for the reset phase of the first half period T 11 , with the only difference that, now, the timed biasing voltage DRH is high. This value does not, however, affect the reset phase since, as before, the operational amplifier  4  is reset, and the output voltage V o  is not acquired by the signal processing stage  30 . 
     At instant t 4 , the reset signal R switches again to low. 
     Sensing Phase—Second Half Period T 12    
     At the instant t 5 , the timed biasing voltage DRH has a falling edge, thus causing a charge displacement opposite to that of the sensing phase in the first half period. Consequently, the output voltage V o  has a value 
                       V   o     ⁡     (   t   )       ∝         Δ   ⁢   C       C   i       ⁢   Δ   ⁢   V             (   6   )               
with a opposite sign to Eq. (5), since in this half period T 12  the step ΔV of the timed biasing voltage DRH is a down step and is equal to −V DRH .
 
     Also in this step, the value of the output voltage V o  is acquired from the signal processing stage  30  thanks to the high value of the reading acquisition signal S. The signal processing stage  30  thus modifies the sign of the output voltage V o  in one of the two half periods T 11  and T 12 , in a way synchronized with the sensing period T 2 . 
     This step terminates at instant t 3 , where a new period T 1  of the reading acquisition signal S and of the reset signal R starts, as well as a new period T 2  of the sensing signal DRH. 
     The solution illustrated in  FIG. 3  thus enables detection of the absolute temperature in the area of the sensing diode  3  on the basis of the variation of its reverse junction capacitance, using a simple voltage biased capacitive bridge. This solution presents the advantage of having a zero current consumption and a very simple structure, which does not require use of MEMS capacitive structures. 
     However, the sensing diode  3  intrinsically presents a current leakage that, in some situations, may reduce reading precision in an undesirable way. 
     In fact, the aforesaid current leakage of the sensing diode  3  determines a variation of the charge Q 1 . In fact, during the sensing phase, the sensing diode  3  undergoes a displacement of charge equal to Q 1 −Q L , where Q L  is the charge due to the leakage current. A more precise approximation of the output voltage V o  is thus the following: 
                       V   o     ⁡     (   t   )       ∝           Δ   ⁢   C       C   i       ⁢   ΔV     +       I   L     ·     C   i     ·       T   1     2                 (   7   )               
where I L  is the leakage current of the sensing diode  3 .
 
       FIG. 5  shows an embodiment wherein the leakage current I L  of the sensing diode  3  is compensated. 
     In particular, the temperature sensor of  FIG. 5  has the same basic structure as the temperature sensor of  FIG. 3 , where a compensation diode  40  and a symmetry capacitor  41 , having a capacitance equal to the capacitance C R  of the reference capacitor  5 , have been added. The elements in common with those of  FIG. 3  are thus designated by the same reference numbers. 
     In detail, the compensation diode  40  has its anode coupled to the non-inverting input  8  of the operational amplifier  4  and its cathode coupled to a third reference potential line  43 , set at a non-constant biasing potential V STB , and the symmetry capacitor  41  is coupled between the inverting input  7  of the operational amplifier  4  and the third reference potential line  43 . 
     The biasing potential V STB  switches between two positive values, for example between 0 V and 2.5 V, to be surely higher than the potential on the inputs  7  and  8  of the operational amplifier  4  and keep the compensation diode  40  reverse biased. 
     Two current generators  45  are also illustrated in  FIG. 5  and represent the leakage currents I L  of the sensing diode  3  and of the compensation diode  40 . In practice, the sensing diode  3 , the reference capacitor  5 , the compensation diode  40 , and the symmetry capacitor  41  form a capacitive bridge  44 . 
     As illustrated in the timing diagram of  FIG. 6 , where the signals R, DRH, S have the same meaning as in  FIG. 4 , and the switching instants t 0 −t 5  correspond to the above, the biasing potential V STB  switches at the rising edge of the reset signal R, thus at frequency f 2 =1/T 2  equal to one half of the frequency (f 1 =1/T 1 ) of the reset signal R and equal to the frequency of the sensing signal DRH. It follows that the effects of switching of the biasing potential V STB  do not affect the operational amplifier  4  since, during the reset phase, the inputs  7 ,  8  of the latter are coupled to the first common mode potential V CMin . Furthermore, the biasing potential V STB  has the same sign as the timed biasing voltage DRH during the sensing phase; namely, it is positive with respect to the virtual ground on the inputs  7  and  8  of the operational amplifier  4  for keeping the compensation diode  40  reverse biased in all the sensing phases and to have a voltage step ΔV equal to the step of the sensing signal DHR in order to keep the compensation diode  40  in the same operating conditions as the sensing diode  3 . 
     In this way, during the sensing phase (both in the first half period T 11  and in the second half period T 12  of the sensing signal DRH), the feedback capacitors  17  and  18  are traversed by the following currents: 
     a current due to the differential charge generated by the switching edge of the timed biasing voltage DRH and depending on the difference of capacitance in the capacitive bridge  44 ; 
     a leakage current I L1  in the sensing diode  3 ; and 
     a leakage current I L2  in the compensation diode  40 . 
     Consequently, the output voltage V o  of the temperature sensor of  FIG. 5  may be expressed as follows: 
     
       
         
           
             
               
                 
                   
                     
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                     + 
                     
                       
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                           1 
                         
                       
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     By manufacturing the compensation diode  40  in the same way and with the same parameters as the sensing diode  3 , due also to the same reverse biasing of the diodes  3  and  40 , they generate leakage currents I L1  and I L2  that are the same so that in Eq. (8) the two contributions of the leakage currents I L1  and I L2  cancel out, and the output voltage V o  may be expressed again by Eq. (6). 
     The effect of cancelling out of the leakage currents in the sensing diode  3  is visible in the simulation of  FIG. 7 , which reproduces the voltages on the non-inverting output  15  and on the inverting output  16  of the operational amplifier  4  in case of compensation of the leakage current of the sensing diode  3  (solid lines) and in the case without compensation (dashed lines). 
     As may be noted, the output voltage V o  of the operational amplifier  4  without compensation has a reading error proportional both to the leakage current and to the integration time. Instead, the output voltage V o  with compensation, after a transient, is insensitive to the above parameters. 
       FIG. 8  shows a possible implementation of the compensation diode  40  and of the symmetry capacitor  41 . In the example illustrated, the temperature sensor  1  is formed in a chip  60  of semiconductor material, such as silicon, having a substrate  50  of a P type, accommodates a well  51  of an N type, which forms the cathode K of the compensation diode  40 . The well  51  in turn accommodates a tap  52 , of a P type, forming the anode A of the compensation diode  40 . 
     An insulating layer  55  extends over the substrate  50  and accommodates two metal regions  56 ,  57 , arranged on top of each other and formed, for example, in two different metallization levels of the chip  60 . The metal regions  56 ,  57  form, together with the portion of the insulating layer  55  arranged in between, the reference capacitor  5 . 
     The compensation diode  40  and the symmetry capacitor  41  may be formed in a similar way. 
     The described temperature sensor comprises only a few simple components of a capacitive type (sensing diode  3 , reference capacitor  5 , possibly a capacitive bridge  44 ) that may easily be integrated and require only a small area, which cooperate with a sensing network (operational amplifier  4  and corresponding feedback network) that may be manufactured using standard CMOS technology. The sensor has a zero d.c. biasing voltage, and thus a low current consumption. 
     The temperature sensor  1  may be compensated with respect to the current leakages by a few simple components (compensation diode  40 , symmetry capacitor  41 ), thus supplying a particularly precise output. 
     Finally, it is clear that modifications and variations may be made to the embodiments of a temperature sensor described and illustrated herein, without thereby departing from the scope of the present disclosure. In particular, the switched capacitor differential amplifier  26  may be replaced by another type of sensing circuit, and/or be formed in a different way from what illustrated, for example be formed as a non-fully differential amplifier. 
     The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
     These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.