Patent Publication Number: US-9887197-B2

Title: Structure containing first and second vertically stacked nanosheets having different crystallographic orientations

Description:
BACKGROUND 
     The present application relates to a method of forming a semiconductor structure containing vertically stacked and suspended nanosheets of a semiconductor channel material of a first crystallographic orientation in a first device region, and vertically stacked and suspended nanosheets of a semiconductor channel material of a second crystallographic orientation, different from the first crystallographic orientation, in a second device region. The present application also relates to the semiconductor structure that is provided by the method. 
     The use of new semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. One type of new semiconductor device that has been touted as a viable option beyond the 7 nm technology node is nanosheet containing devices. By “nanosheet containing devices” it is meant that the device channel contains one or more layers of nanosheets. Each nanosheet has a vertical thickness that is substantially less than the width of each nanosheet. Gate structures are formed above and below each nanosheet. One of the challenges facing the fabrication of nanosheet containing devices is to boost carrier mobility to improve device performance. 
     SUMMARY 
     In one aspect of the present application, a method of forming a semiconductor structure is provided. In one embodiment of the present application, the method includes providing a first substrate comprising a first semiconductor material having a first crystallographic orientation, wherein a second substrate portion comprising a second semiconductor material having a second crystallographic orientation that is different from the first crystallographic orientation is present on a portion of the first substrate. Next, a first nanosheet stack structure is formed on a portion of the first substrate and in a first device region, and a second nanosheet stack structure is formed on a portion of the second substrate portion and in a second device region. The first nanosheet stack structure comprises a first portion of a base sacrificial layer and alternating layers of semiconductor channel material and sacrificial semiconductor material, each of which has the first crystallographic orientation. The second nanosheet stack structure comprises a second portion of the base sacrificial layer, and alternating layers of semiconductor channel material and sacrificial semiconductor material, each of which has the second crystallographic orientation. A first sacrificial gate structure is formed straddling the first nanosheet stack structure and a second sacrificial gate structure is formed straddling the second nanosheet stack structure. Exposed portions of the first and second nanosheet stack structures are then removed and thereafter the first and second sacrificial gate structures are removed. Next, remaining portions of the base sacrificial layer and the layers of sacrificial semiconductor material are removed providing vertically stacked and suspended nanosheets of the semiconductor channel material in the first and second device regions, wherein the nanosheets of the semiconductor channel material in the first device region have the first crystallographic orientation and the nanosheets of the semiconductor channel material in the second device region have the second crystallographic orientation. 
     In another aspect of the present application, a semiconductor structure is provided. In one embodiment of the present application, the semiconductor structure includes a substrate comprising a first semiconductor material having a first crystallographic orientation and a first device region and a second device region. First vertically stacked and suspended nanosheets of semiconductor channel material of the first crystallographic orientation are located above the substrate and within the first device region. Second vertically stacked and suspended nanosheets of semiconductor channel material of a second crystallographic orientation are located above the substrate and within the second device region. In accordance with the present application, the second crystallographic orientation is different from the first crystallographic orientation. 
    
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1  is a cross sectional view of an exemplary semiconductor structure including a multilayered stack of, from bottom to top, a first substrate comprising a first semiconductor material having a first crystallographic orientation and a second substrate comprising a second semiconductor material having a second crystallographic orientation that is different from the first crystallographic orientation. 
         FIG. 2  is a cross sectional view of the exemplary semiconductor structure of  FIG. 1  after forming a mask over a second device region and removing the second substrate from a first device region. 
         FIG. 3  is a cross sectional view of the exemplary semiconductor structure of  FIG. 2  after removing the mask and epitaxially growing a base sacrificial layer of a third semiconductor material, wherein the portion of the base sacrificial layer located on the first substrate and in the first device region has the first crystallographic orientation and the portion of the base sacrificial layer located on a remaining portion of the second substrate and in the second device region has the second crystallographic orientation. 
         FIG. 4  is a cross sectional view of the exemplary semiconductor structure of  FIG. 3  after epitaxially growing a material stack comprising alternating layers of a semiconductor channel material and a sacrificial semiconductor material on the base sacrificial layer, wherein the portion of each layer of semiconductor channel material and each layer of sacrificial semiconductor material located in the first device region has the first crystallographic orientation and the portion of each layer of semiconductor channel material and each layer of sacrificial semiconductor material located in the second device region has the second crystallographic orientation. 
         FIG. 5  is a cross sectional view of the exemplary semiconductor structure of  FIG. 4  after forming a first nanosheet stack structure in the first device region and a second nanosheet stack structure in the second device region. 
         FIG. 6  is a cross sectional view of the exemplary semiconductor structure of  FIG. 5  after forming a first sacrificial gate structure and a first dielectric spacer straddling the first nanosheet stack structure and a second sacrificial gate structure and a second dielectric spacer straddling the second nanosheet stack structure. 
         FIG. 7  is a cross sectional view of the exemplary semiconductor structure of  FIG. 6  after removing exposed portions of the first and second nanosheet stack structures and forming a first epitaxial semiconductor S/D structure in the first device region and a second epitaxial semiconductor S/D structure in the second device region. 
         FIG. 8  is a cross sectional view of the exemplary semiconductor structure of  FIG. 7  after forming a middle-of-the-line (MOL) dielectric material structure having a topmost surface that is coplanar with a topmost surface of each of the first and second sacrificial gate structures. 
         FIG. 9  is a cross sectional view of the exemplary semiconductor structure of  FIG. 8  after removing the first and second sacrificial gate structures and thereafter selectively removing remaining portions of the base sacrificial layer and remaining portions of the layers of sacrificial semiconductor material within the first and second device regions to provide vertically stacked and suspended nanosheets of semiconductor channel material within the first and second device regions. 
         FIG. 10  is a cross sectional view of the exemplary semiconductor structure of  FIG. 9  after forming a first functional gate structure surrounding the vertically stacked and suspended nanosheets of the semiconductor channel material within the first device region, and a second functional gate structure surrounding the vertically stacked and suspended nanosheets of the semiconductor channel material within the second device region. 
         FIG. 11  is a cross sectional view of another exemplary semiconductor structure of the present application. 
         FIG. 12  is a cross sectional view of yet another exemplary semiconductor structure of the present application. 
     
    
    
     DETAILED DESCRIPTION 
     The present application will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals. 
     In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application. 
     It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present. 
     Referring first to  FIG. 1 , there is illustrated an exemplary semiconductor structure including a multilayered stack of, from bottom to top, a first substrate  10  comprising a first semiconductor material having a first crystallographic orientation and a second substrate  12  comprising a second semiconductor material having a second crystallographic orientation that is different from the first crystallographic orientation. The multilayered stack of the first substrate  10  and the second substrate  12  may be referred to herein as a hybrid orientation substrate. 
     In one embodiment of the present application, element  11  can be a bonding interface that is formed by the direct bonding of the first and second substrates ( 10 ,  12 ). In another embodiment of the present application, element  11  can be a dielectric layer such as, for example, an oxide. In such an embodiment, the dielectric layer may be present on at least one of the first and second substrates ( 10 ,  12 ) prior to bonding the first and second substrates ( 10 ,  12 ). 
     The first semiconductor material that provides the first substrate  10  may be any semiconductor material having semiconducting properties. Examples of semiconductor materials that may be used as the first semiconductor material and thus the first substrate  10  can include silicon (Si), germanium (Ge), silicon germanium alloys (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), III-V compound semiconductors and/or II-VI compound semiconductors. III-V compound semiconductors are materials that include at least one element from Group III of the Periodic Table of Elements and at least one element from Group V of the Periodic Table of Elements. II-VI compound semiconductors are materials that include at least one element from Group II of the Periodic Table of Elements and at least one element from Group VI of the Periodic Table of Elements. In one embodiment, the first semiconductor material that provides the first substrate  10  is silicon. 
     The first crystallographic orientation of the first semiconductor material that provides the first substrate  10  may be any of the well known crystallographic orientations. For example, the first crystallographic orientation of the first semiconductor material that provides the first substrate  10  may be {100}, {110}, or {111}. In one embodiment of the present application, the first substrate  10  is silicon having a {100} crystallographic orientation. In another embodiment of the present application, the first substrate  10  is silicon having a {110} crystallographic orientation. 
     The second semiconductor material that provides the second substrate  12  may include one of the semiconductor materials mentioned above for the first semiconductor material that provides the first substrate  10 . In one embodiment, the second semiconductor material may be the same as the first semiconductor material. For example, silicon may be used as the first and second semiconductor materials. In another embodiment, the second semiconductor material may be different than the first semiconductor material. For example, the first semiconductor material may be composed of silicon, while the second semiconductor material may be composed of germanium. 
     The second crystallographic orientation of the second semiconductor material that provides the second substrate  12  may also be any of the well known crystallographic orientations provided that the second crystallographic orientation differs from the first crystallographic orientation. In one example, the first crystallographic orientation of the first semiconductor material that provides the first substrate  10  may be {100}, while the second crystallographic orientation of the second semiconductor material that provides the second substrate  12  may be {110}. In another example, the first crystallographic orientation of the first semiconductor material that provides the first substrate  10  may be {110}, while the second crystallographic orientation of the second semiconductor material that provides the second substrate  12  may be {100}. In either example, the first and second semiconductor materials may both be composed of silicon. 
     In some embodiments of the present application, the first substrate  10  and the second substrate  12  are both relaxed substrates. In another embodiment, the first substrate  10  is a relaxed substrate, while the second substrate  12  is strained. 
     The exemplary semiconductor structure illustrated in  FIG. 1  can be formed utilizing any well known wafer bonding process. In some embodiments, wafer bonding may be performed at a temperature from 20° to 200° C. Other temperatures that are lesser than, or greater than, the aforementioned temperature range may also be employed in the present application to bond the first and second substrates ( 10 ,  12 ). In some embodiments of the present application, an external force may be applied to at least one of the two substrates during at least a portion of the bonding process. In some embodiments, at least one of the two substrates may be thinned after the bonding process. In one example, chemical mechanical polishing and/or grinding may be used to thin at least one of the two substrates after bonding. 
     Referring now to  FIG. 2 , there is illustrated the exemplary semiconductor structure of  FIG. 1  after forming a mask  15  over a second device region  102  and removing the second substrate  12  from a first device region  100 . As shown, a portion of the second substrate  12  that is present directly beneath the mask  15  remains in the second device region  102 . The portion of the second substrate  12  that remains in the second device region  102  can be referred to herein as a second substrate portion  12 R. 
     In accordance with the present application, the first device region  100  is an area in which a first conductivity type semiconductor device can be subsequently formed, while the second device region  102  is an area in which a second conductivity type semiconductor device, that is opposite from the first conductivity type, can be subsequently formed. In one example, the first device region  100  is an area in which an n-type semiconductor device (e.g., nFET) can be subsequently formed, while the second device region  102  is an area in which a p-type semiconductor device (e.g., pFET) can be subsequently formed. In another example, the first device region  100  is an area in which a p-type semiconductor device (e.g., pFET) can be subsequently formed, while the second device region  102  is an area in which an n-type semiconductor device (e.g., nFET) can be subsequently formed. 
     The exemplary semiconductor structure of  FIG. 2  can be formed by first providing a layer of at least one masking material over the entirety of the second substrate  12 . In one embodiment, the masking material may include a hard mask material such as, for example, a semiconductor oxide, semiconductor nitride and/or semiconductor oxynitride. In one specific example, silicon dioxide can be used as the masking material. 
     In some embodiments, the layer of at least one masking material may be formed by a deposition process such as, for example, chemical vapor deposition or plasma enhanced chemical vapor deposition. In another embodiment, the layer of at least one masking material may be formed by a thermal growth process such as, for example, thermal oxidation or thermal nitridation. In yet another embodiment, any combination of deposition processes and/or thermal growth processes may be used in providing the layer of at least one masking material. The layer of at least one masking material may have a thickness from 20 nm to 100 nm. Other thickness that are lesser than, or greater than, the aforementioned thickness range may be also employed. 
     After providing the layer of the at least one masking material, the layer of at least one masking material is then patterned to provide mask  15  shown in  FIG. 2 . In one embodiment, patterning may be achieved by lithography and etching. Lithography includes forming a photoresist material (not shown) atop a material or material stack to be patterned. The photoresist material may include a positive-tone photoresist composition, a negative-tone photoresist composition or a hybrid-tone photoresist composition. The photoresist material may be formed by a deposition process such as, for example, spin-on coating. After forming the photoresist material, the deposited photoresist material is subjected to a pattern of irradiation. Next, the exposed photoresist material is developed utilizing a conventional resist developer. This provides a patterned photoresist atop a portion of the material or material stack to be patterned. The pattern provided by the patterned photoresist material is thereafter transferred into the underlying material layer or material layers utilizing at least one pattern transfer etching process. Typically, the at least one pattern transfer etching process is an anisotropic etch. In one embodiment, a dry etching process such as, for example, reactive ion etching can be used. In another embodiment, a chemical etchant can be used. In still a further embodiment, a combination of dry etching and wet etching can be used. In the present application, the etch stops on a surface of the first substrate  10 . 
     Referring now to  FIG. 3 , there is illustrated the exemplary semiconductor structure of  FIG. 2  after removing the mask  15  and epitaxially growing a base sacrificial layer ( 14 L,  14 R) of a third semiconductor material. The base sacrificial layer includes a first portion  14 L and a second portion  14 R. In accordance with the present application, the first portion  14 L of the base sacrificial layer, which is located directly on the first substrate  10  and in the first device region  100 , has the first crystallographic orientation, and the second portion  14 R of the base sacrificial layer, which is located on the remaining portion of the second substrate (i.e., second substrate portion  12 R) and in the second device region  102 , has the second crystallographic orientation. 
     The third semiconductor material that provides the base sacrificial layer ( 14 L,  14 R) includes any of the semiconductor materials mentioned above for the first substrate  10  provided that the third semiconductor material is different (i.e., has a different etch selectivity) from either the first and second semiconductor materials. In one example, and when the first and second semiconductor materials are composed of silicon, the third semiconductor material may be composed of a silicon germanium alloy. 
     Mask  15  may be removed utilizing any mask removal process including, for example, planarization or etching. When an etch is used, the etch is selective in removing the mask  15  from the exemplary semiconductor structure. 
     The base sacrificial layer ( 14 L,  14 R) of the third semiconductor material is formed by an epitaxial growth (or deposition) process. The terms “epitaxially growing and/or depositing” and “epitaxially grown and/or deposited” mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material has the same crystalline characteristics as the deposition surface on which it is formed. Since an epitaxial growth process is used in providing the base sacrificial layer ( 14 L,  14 R), the first portion  14 L of the base sacrificial layer formed directly from the first substrate  10  has the first crystallographic orientation, while the second portion  14 R of the base sacrificial layer formed directly from the second substrate portion  12 R has the second crystallographic orientation. 
     Examples of various epitaxial growth process apparatuses that can be employed in the present application include, e.g., rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature for epitaxial deposition typically ranges from 550° C. to 900° C. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking. The epitaxial growth of the base sacrificial layer ( 14 L,  14 R), can be performed utilizing any well known precursor gas or gas mixture. Carrier gases like hydrogen, nitrogen, helium and argon can be used. 
     In some embodiments and as shown, the first portion  14 L of the base sacrificial layer that is present in the first device region  100  has a vertical thickness that is greater than a vertical thickness of the second portion  14 R of the base sacrificial layer in the second device region  102 , yet each portion  14 L,  14 R of the base sacrificial layer has a topmost surface that is coplanar with each other. In some embodiments, a planarization process such as chemical mechanical polishing and/or grinding can be used to provide the coplanarity to the base sacrificial layer ( 14 L,  14 R). 
     Referring now to  FIG. 4 , there is illustrated the exemplary semiconductor structure of  FIG. 3  after epitaxially growing a material stack comprising alternating layers of a semiconductor channel material (e.g.,  16 L,  16 R,  20 R,  20 L) and a sacrificial semiconductor material (e.g.,  18 L,  18 R,  22 L and  22 R) on the base sacrificial layer ( 14 L,  14 R). The number of layers of semiconductor channel material and the number of layers of sacrificial semiconductor material may vary as long as at least two layers of semiconductor channel material and at least two layers of sacrificial semiconductor material are present. Moreover, and as shown, each layer of semiconductor channel material (e.g.,  16 L,  16 R,  20 L,  20 R) is capped with a layer of sacrificial semiconductor material (e.g.,  18 L,  18 R,  22 L and  22 R). 
     In accordance with the present application, the portion of each layer of semiconductor channel material (e.g.,  16 L,  20 L) and each layer of sacrificial semiconductor material ( 18 L,  22 L) located atop the first portion  14 L of the base sacrificial layer and in the first device region  100  has the first crystallographic orientation and the portion of each layer of semiconductor channel material (e.g.,  16 R,  20 R) and each layer of sacrificial semiconductor material (e.g.,  18 R,  22 R) located atop the second portion  14 R of the base sacrificial layer and in the second device region  102  has the second crystallographic orientation. 
     Each layer of sacrificial semiconductor material (including, for example, portions  18 L,  18 R,  22 L,  22 R) is composed of the third semiconductor material as mentioned above for the base sacrificial layer ( 14 L,  14 R). In one example, each layer of sacrificial semiconductor material (including, for example, portions  18 L,  18 R,  22 L,  22 R) is composed of a silicon germanium alloy. 
     Each layer of semiconductor channel material (including for example, portions  16 L,  16 R,  20 L,  20 R) is composed of a semiconductor material. The semiconductor material that provides each layer of semiconductor channel material may be the same as, or different from, the first semiconductor material and/or the second semiconductor material with the proviso that the semiconductor material that provides each layer of semiconductor channel material has a different etch rate in a specific etchant as compared to the sacrificial semiconductor material and the base sacrificial layer. In one example, the first and second semiconductor materials and the semiconductor material that provides each layer of semiconductor channel material are each composed of silicon. In some embodiments, each layer of the semiconductor channel material comprises a same semiconductor material. In other embodiments, at least one layer of the semiconductor channel material comprises a different semiconductor material than at least one other layer of semiconductor channel material. 
     The material stack of alternating layers of semiconductor channel material (e.g.,  16 L,  16 R,  20 L,  20 R) and sacrificial semiconductor material (e.g.,  18 L,  18 R,  22 L,  22 R) can be formed utilizing an epitaxial growth (or deposition process) as mentioned above for forming the base sacrificial layer ( 14 L,  14 R). 
     The thickness of each layer of semiconductor channel material may be in a range from 3 nm to 10 nm, while the thickness of each layer of sacrificial semiconductor material may be in a range from 5 nm to 20 nm. Other thicknesses that are lesser than, or greater than, the aforementioned ranges may also be employed in the present application. In some embodiments, each layer of semiconductor channel material has a same thickness. In other embodiments, at least one layer of semiconductor channel material has a different thickness than another layer of semiconductor channel material. In some embodiments, each sacrificial semiconductor material has a same thickness. In other embodiments, at least one layer of sacrificial semiconductor material has a different thickness than another layer of sacrificial semiconductor material. 
     Referring now to  FIG. 5 , there is illustrated the exemplary semiconductor structure of  FIG. 4  after forming a first nanosheet stack structure  24 L in the first device region  100  and a second nanosheet stack structure  24 R in the second device region  102 . Although a single first nanosheet structure  24 L and a single second nanosheet structure  24 R are described and illustrated, the present application contemplates embodiments in which a plurality of first nanosheet structures  24 L and/or second nanosheet structures  24 R can be formed. 
     The first nanosheet stack structure  24 L includes a remaining portion of the first portion  14 L of the base sacrificial layer, and a remaining portion of the material stack including remaining portions of the alternating layers of semiconductor channel material (e.g.,  16 L,  20 L) and of sacrificial semiconductor material (e.g.,  18 L,  22 L). The remaining portion of the first portion  14 L of the base sacrificial layer in the first device region  100  is labeled as  14 L′, the remaining portion of each layer of semiconductor channel material within the first device region  100  is labeled as  16 L′,  20 L′ and the remaining portion of each layer of sacrificial semiconductor material within the first device region  100  is labeled as  18 L′,  22 L′. Each semiconductor material that constitutes the first nanosheet structure  24 L has the first crystallographic orientation. 
     The second nanosheet stack structure  24 R includes a remaining portion of the second portion  14 R of the base sacrificial layer, and a remaining portion of the material stack including remaining portions of the alternating layers of semiconductor channel material (e.g.,  16 R,  20 R) and of sacrificial semiconductor material (e.g.,  18 R,  22 R). The remaining portion of the second portion  14 R of the base sacrificial layer in the second device region  102  is labeled as  14 R′, the remaining portion of each layer of semiconductor channel material within the second device region  102  is labeled as  16 R′,  20 R′ and the remaining portion of each layer of sacrificial semiconductor material within the second device region  102  is labeled as  18 R′,  22 R′. Each semiconductor material that constitutes the second nanosheet structure  24 R has the second crystallographic orientation. 
     The first and second nanosheet stack structures  24 L,  24 R can be formed by patterning the exemplary semiconductor structure shown in  FIG. 4 . In one embodiment, the patterning process may include lithography and etching as defined above. In one embodiment, and in the first device region  100 , the etch removes a portion of the first substrate  10  to provide a first pedestal portion  10 L that extends above a remaining portion  10 B of the first substrate  10 . In one embodiment, and in the second device region  102 , the etch also removes a portion of the second substrate portion  12 R to provide a second substrate base portion  12 R′ and a portion of the first substrate  10  to provide a second pedestal portion  10 R of the first substrate  10 . In accordance with the present application, the first nanosheet stack structure  24 L sits on the first pedestal portion  10 L of the first substrate  10 , while the second nanosheet stack structure  24 R sits on the second substrate base portion  12 R′ and the second pedestal portion  10 R of the first substrate  10 . 
     As is shown, the sidewall surfaces of the first nano sheet stack structure  24 L are vertically aligned with the sidewall surfaces of the first pedestal portion  10 L formed in the first device region  100 , while the sidewalls of the second nanosheet stack structure  24 R are vertically aligned with the sidewall surfaces of both the second substrate base portion  12 R′ and the second pedestal portion  10 R of the first substrate  10  in the second device region  102 . As is further shown, the first nanosheet stack structure  24 L is spaced apart and is thus not in direct contact with any portion of the second nanosheet stack structure  24 R. 
     Referring now to  FIG. 6 , there is illustrated the exemplary semiconductor structure of  FIG. 5  after forming a first sacrificial gate structure  26 L and a first dielectric spacer  28 L straddling the first nanosheet stack structure  24 L and a second sacrificial gate structure  26 R and a second dielectric spacer  28 R straddling the second nanosheet stack structure  24 R. By “straddling” it is meant that a first portion of a first material is located on one side of a second material, and another portion of the first material is located on another side of the second material, and wherein yet a further portion of the first material is present above a topmost surface of the second material. Each sacrificial gate structure  26 L,  26 R protects a gate region of the exemplary semiconductor structure of the present application during the processing of the source/drain regions of the exemplary semiconductor structure. In the present application, a bottommost surface of the first sacrificial gate structure  26 L and a bottommost surface of the first dielectric spacer  28 L land on a surface of the remaining portion  10 B of the first substrate  10 , while a bottommost surface of the second sacrificial gate structure  26 R and a bottommost surface of the second dielectric spacer  28 R also land on a surface of the remaining portion  10 B of the first substrate  10 . 
     Each sacrificial structure  26 L,  26 R includes a single sacrificial material layer or a stack of two or more sacrificial materials (i.e., at least one sacrificial material portion). In one embodiment, the at least one sacrificial material portion comprises, from bottom to top, a sacrificial gate dielectric portion, a sacrificial gate portion and a sacrificial dielectric cap portion. In some embodiments, the sacrificial gate dielectric portion and/or the sacrificial dielectric cap portion can be omitted and only a sacrificial gate portion is formed. The at least one sacrificial material portion can be formed by forming a blanket layer (or layers) of a material (or various materials) and then patterning the material (or various materials) by lithography and an etch. In one embodiment, the at least one sacrificial material portion can be formed by first depositing a blanket layer of a sacrificial gate dielectric material. The sacrificial gate dielectric material can be an oxide, nitride, and/or oxynitride. In one example, the sacrificial gate dielectric material can be a high k material having a dielectric constant greater than silicon dioxide. In some embodiments, a multilayered dielectric structure comprising different dielectric materials, e.g., silicon dioxide, and a high k dielectric can be formed and used as the sacrificial gate portion. The sacrificial gate dielectric material can be formed by any deposition technique including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition. 
     After forming the blanket layer of sacrificial gate dielectric material, a blanket layer of a sacrificial gate material can be formed on the blanket layer of sacrificial gate dielectric material. The sacrificial gate material can include any material including, for example, polysilicon, amorphous silicon, an elemental metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium and platinum), an alloy of at least two elemental metals or multilayered combinations thereof. The sacrificial gate material can be formed utilizing a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD) or other like deposition processes. 
     After forming the blanket layer of sacrificial gate material, a blanket layer of a sacrificial gate cap material can be formed. The sacrificial gate cap material may include a hard mask material such as, for example, silicon dioxide and/or silicon nitride. The sacrificial gate cap material can be formed by any suitable deposition process such as, for example, chemical vapor deposition or plasma enhanced chemical vapor deposition. 
     After providing the above mentioned sacrificial material stack (or any subset of said sacrificial materials), lithography and etching can be used to pattern the sacrificial material stack (or any subset of said sacrificial materials) and to provide each sacrificial gate structure  26 L,  26 R. The remaining portions of the sacrificial gate dielectric material constitute a sacrificial gate dielectric portion, the remaining portions of the sacrificial gate material constitute a sacrificial gate portion, and the remaining portions of the sacrificial dielectric cap material constitute a sacrificial dielectric cap portion. 
     In some embodiments, the first sacrificial gate structure  26 L and the second sacrificial gate structure  26 R comprise a same sacrificial material or stack of sacrificial materials. In yet another embodiment, the first sacrificial gate structure  26 L comprises a different sacrificial material or stack of sacrificial materials from the second sacrificial gate structure  26 R. When different materials are used, block mask technology can be implemented during the fabrication of the first and second sacrificial gate structures  26 L,  26 R. 
     After providing the first and second sacrificial gate structures ( 26 L,  26 R), a dielectric spacer can be formed on exposed sidewall surfaces of the each sacrificial gate structure  26 L,  26 R. The dielectric spacer that is located on the first sacrificial gate structure  26 L is referred to herein a first dielectric spacer  28 L, while the dielectric spacer formed on the second sacrificial gate structure  26 R is referred to herein as a second dielectric spacer  28 R. Each dielectric spacer  28 L,  28 R can be formed by first providing a dielectric spacer material and then etching the dielectric spacer material. Examples of dielectric spacer materials that may be employed in the present application include dielectric oxides, dielectric nitrides and/or dielectric oxynitrides. In one embodiment, the dielectric spacer material used in providing each dielectric spacer  28 L,  28 R is composed of silicon dioxide or silicon nitride. The dielectric spacer material may be provided by a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVP). The etch used to provide the dielectric spacer may comprise a dry etching process such as, for example, reactive ion etching. 
     Referring now to  FIG. 7 , there is illustrated the exemplary semiconductor structure of  FIG. 6  after removing exposed portions of the first and second nanosheet stack structures  24 L,  24 R (not covered by either a sacrificial gate structure or a dielectric spacer) and forming a first epitaxial semiconductor S/D (“S/D” denotes source/drain) structure  30 L in the first device region  100  and a second epitaxial semiconductor S/D structure  30 R in the second device region  102 . 
     The exposed portions of the first and second nanosheet stack structures  24 L,  24 R can be removed utilizing an anisotropic etching process such as for example, a reactive ion etch, utilizing each sacrificial gate structure and each dielectric spacer as an etch mask. Although not shown, a portion of the first nanosheet stack structure  24 L remains beneath the first sacrificial gate structure  26 L and the first dielectric spacer  28 L, and a portion of the second nanosheet stack structure  24 R remains beneath the second sacrificial gate structure  26 R and the second dielectric spacer  28 L. 
     Each first epitaxial semiconductor S/D structure  30 L grows from an exposed sidewall surface of the remaining first nanosheet stack structure in the first device region  100 , while each second epitaxial semiconductor S/D structure  30 R grows from an exposed sidewall surface of the remaining second nanosheet stack structure in the second device region  102 . The forming of the first epitaxial semiconductor S/D structure  30 L in the first device region  100  and the second epitaxial semiconductor S/D structure  30 R in the second device region  102  includes an epitaxial growth process as defined above. 
     Each first epitaxial semiconductor S/D structure  30 L and each second epitaxial semiconductor S/D structure  30 R includes a semiconductor material and a dopant. The dopant within the each first epitaxial semiconductor S/D structure  30 L is of a different conductivity than the dopant within each second epitaxial semiconductor S/D structure  30 R. 
     The semiconductor material that provides each first epitaxial semiconductor S/D structure  30 L and each second epitaxial semiconductor S/D structure  30 R can be selected from one of the semiconductor materials mentioned above for the first substrate  10 . The dopant can be either a p-type dopant or an n-type dopant. The term “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing semiconductor material, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium and indium. “N-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing semiconductor material, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic and phosphorous. In one embodiment, the dopant that can be present in the each first epitaxial semiconductor S/D structure  30 L and each second epitaxial semiconductor S/D structure  30 R can be introduced into the precursor gas that provides the first epitaxial semiconductor S/D structure  30 L and each second epitaxial semiconductor S/D structure  30 R. In another embodiment, the dopant can be introduced into an intrinsic layer of each first epitaxial semiconductor S/D structure  30 L and each second epitaxial semiconductor S/D structure  30 R by utilizing one of ion implantation or gas phase doping. Block mask technology may be used to form each first epitaxial semiconductor S/D structure  30 L and each second epitaxial semiconductor S/D structure  30 R. 
     Each first epitaxial semiconductor S/D structure  30 L has a height that is less than the first sacrificial gate structure  26 L and each second epitaxial semiconductor S/D structure  30 R has a height that is less than the height of the second sacrificial gate structure  26 R. 
     Referring now to  FIG. 8 , there is illustrated the exemplary semiconductor structure of  FIG. 7  after forming a middle-of-the-line (MOL) dielectric material structure  32  having a topmost surface that is coplanar with a topmost surface of each of the first and second sacrificial gate structures  26 L,  26 R. 
     MOL dielectric material structure  32  may be composed of silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer or any combination thereof. The term “low-k” as used throughout the present application denotes a dielectric material that has a dielectric constant of less than silicon dioxide. In another embodiment, a self-planarizing material such as a spin-on glass (SOG) or a spin-on low-k dielectric material such as SiLK™ can be used as MOL dielectric material structure  32 . The use of a self-planarizing dielectric material as MOL dielectric material structure  32  may avoid the need to perform a subsequent planarizing step. 
     In one embodiment, the MOL dielectric material structure  32  can be formed utilizing a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation or spin-on coating. In some embodiments, particularly when non-self-planarizing dielectric materials are used as MOL dielectric material structure  32 , a planarization process or an etch back process follows the deposition of the dielectric material that provides the MOL dielectric material structure  32 . The thickness of the dielectric material that provides the MOL dielectric material structure  32  may vary depending on the type of dielectric material employed as well as the method that was employed in forming the same. In one embodiment, the dielectric material used to provide the MOL dielectric material structure  32  has a thickness from 80 nm to 500 nm. Other thicknesses that are greater or lesser than the range provided above can also be used for the dielectric material that provides the MOL dielectric material structure  32 . 
     Referring now to  FIG. 9 , there is illustrated the exemplary semiconductor structure of  FIG. 8  after removing the first and second sacrificial gate structures  26 L,  26 R and thereafter selectively removing remaining portions of the base sacrificial layer  14 L′,  14 R′ and remaining portions of the layers of sacrificial semiconductor material ( 18 L′,  18 R′,  22 L′ and  22 R′) within the first and second device regions  100 ,  102  to provide vertically stacked and suspended nanosheets (e.g.,  16 L″ and  20 L″, and  16 R″ and  20 R″) of semiconductor channel material within the first and second device regions  100 ,  102 . As is shown, a first gate cavity  34 L is formed in the first device region  100 , and a second gate cavity  34 R is formed in the second device region  102 . Although not shown (for clarity), a portion of the first dielectric spacer  28 L and a portion of the second dielectric spacer  28 L would be located in front of the vertically stacked and suspended nanosheets (e.g.,  16 L″ and  20 L″, and  16 R″ and  20 R″) of semiconductor channel material within the first and second device regions  100 ,  102 , respectively. Each nanosheet (e.g.,  16 L″ and  20 L″, and  16 R″ and  20 R″) of semiconductor channel material has a width from 10 nm to 60 nm. The vertical thickness of each nanosheet is less than the width of each nanosheet. 
     The removal of the first and second sacrificial gate structures  26 L,  26 R can be performed utilizing one or more anisotropic etching processes. The removal of remaining portions of the base sacrificial layer  14 L′,  14 R′ and remaining portions of the layers of sacrificial semiconductor material ( 18 L′,  18 R′,  22 L′ and  22 R′) within the first and second device regions  100 ,  102  can be performed utilizing a wet etch process that is selective in removing the sacrificial semiconductor material relative to the semiconductor channel material. 
     In the present embodiment, the vertically stacked and suspended nanosheets (e.g.,  16 L″ and  20 L″, and  16 R″ and  20 R″) of semiconductor channel material within the first and second device regions  100 ,  102  are located above the remaining portion  10 B of the first substrate  10 . 
     Notably,  FIG. 9  illustrates a semiconductor structure of the present application which includes a substrate (i.e., remaining portion  10 B of first substrate  10 ) comprising a first semiconductor material and having a first crystallographic orientation and a first device region  100  and a second device region  102 . First vertically stacked and suspended nanosheets of semiconductor channel material (i.e.,  16 L″,  20 L″, etc) of the first crystallographic orientation are located above the substrate (i.e.,  10 B) and within the first device region  100 . Second vertically stacked and suspended nanosheets of semiconductor channel material (i.e.,  16 R″,  20 R″, etc.) of a second crystallographic orientation are located above the substrate (i.e.,  10 B) and within the second device region  102 . In accordance with the present application, the second crystallographic orientation is different from the first crystallographic orientation. In one embodiment, the first vertically stacked and suspended nanosheets of semiconductor channel material (i.e.,  16 L″,  20 L″, etc) and the second vertically stacked and suspended nanosheets of semiconductor channel material (i.e.,  16 R″,  20 R″, etc) are each comprised of relaxed semiconductor materials. In other embodiments, the first vertically stacked and suspended nanosheets of semiconductor channel material (i.e.,  16 L″,  20 L″, etc) is comprised of a relaxed (or strained) semiconductor materials, while the second vertically stacked and suspended nanosheets of semiconductor channel material (i.e.,  16 R″,  20 R″, etc) is comprised of strained (or relaxed) semiconductor materials. 
     Referring now to  FIG. 10 , there is illustrated the exemplary semiconductor structure of  FIG. 9  after forming a first functional gate structure ( 36 L,  38 L) surrounding the first vertically stacked and suspended nanosheets ( 16 L″ and  20 L″) of the semiconductor channel material within the first device region  100 , and a second functional gate structure ( 36 R,  38 R) surrounding the second vertically stacked and suspended nanosheets ( 16 R″ and  20 R″) of the semiconductor channel material within the second device region  102 . By “functional gate structure” it is meant a permanent gate structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device through electrical or magnetic fields. 
     The first functional gate structure ( 36 L,  38 L) includes a first gate dielectric portion  36 L and a first gate conductor portion  38 L, while the second functional gate structure ( 36 R,  38 R) includes a second gate dielectric portion  36 R and a second gate conductor portion  38 R. In one embodiment, the first functional gate structure ( 36 L,  38 L) is a pFET device that is located on the first vertically stacked and suspended nanosheets ( 16 L″ and  20 L″) of the semiconductor channel material that have a {110} crystallographic orientation, while the second functional gate structure ( 36 R,  38 R) is an nFET device that is located on the second vertically stacked and suspended nanosheets ( 16 R″ and  20 R″) of the semiconductor channel material that have a {100} crystallographic orientation. In such an embodiment, each semiconductor channel material that has a {100} crystallographic orientation may be strained (e.g., strained Si). Also, each semiconductor channel material that has a {110} crystallographic orientation may be relaxed (e.g., relaxed Si). 
     Each gate dielectric portion ( 36 L,  36 R) may include a gate dielectric material. The gate dielectric material that provides each gate dielectric portion ( 36 L,  36 R) can be an oxide, nitride, and/or oxynitride. In one example, the gate dielectric material that provides each gate dielectric portion ( 36 L,  36 R) can be a high-k material having a dielectric constant greater than silicon dioxide. Exemplary high-k dielectrics include, but are not limited to, HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , SiON, SiN x , a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. In some embodiments, a multilayered gate dielectric structure comprising different gate dielectric materials, e.g., silicon dioxide, and a high-k gate dielectric, can be formed and used as each gate dielectric portion ( 36 L,  36 R). The first gate dielectric portion  36 L may be the same as, or different from, the second gate dielectric portion  36 R. 
     The gate dielectric material used in providing the gate dielectric portion ( 36 L,  36 R) can be formed by any deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition. In some embodiments and when different gate dielectric materials are used in providing the gate dielectric portions ( 36 L,  36 R), block mask technology can be used. In one embodiment of the present application, the gate dielectric material used in providing each gate dielectric portion ( 36 L,  36 R) can have a thickness in a range from 1 nm to 10 nm. Other thicknesses that are lesser than, or greater than, the aforementioned thickness range can also be employed for the gate dielectric material that may provide each gate dielectric portion ( 36 L,  36 R). 
     Each gate conductor portion ( 38 L,  38 R) can include a gate conductor material. The gate conductor material used in providing each gate conductor portion ( 38 L,  38 R) can include any conductive material including, for example, doped polysilicon, an elemental metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium and platinum), an alloy of at least two elemental metals, an elemental metal nitride (e.g., tungsten nitride, aluminum nitride, and titanium nitride), an elemental metal silicide (e.g., tungsten silicide, nickel silicide, and titanium silicide) or multilayered combinations thereof. The first gate conductor portion  38 L may be the same as, or different from, the second gate conductor portion  38 R. In one example, the first gate conductor portion  38 L may comprise an nFET gate metal, while the second gate conductor portion  38 R may comprise a pFET gate metal. In another example, the first gate conductor portion  38 L may comprise a pFET gate metal, while the second gate conductor portion  38 R may comprise an nFET gate metal. 
     The gate conductor material used in providing the gate conductor portion ( 38 L,  38 R) can be formed utilizing a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD) or other like deposition processes. When a metal silicide is formed, a conventional silicidation process is employed. When a different gate conductor material is used for gate conductor portions ( 38 L,  38 R), block mask technology can be used. In one embodiment, the gate conductor material used in providing each gate conductor portion ( 38 L,  38 R) has a thickness from 50 nm to 200 nm. Other thicknesses that are lesser than, or greater than, the aforementioned thickness range can also be employed for the gate conductor material used in providing each gate conductor portion ( 38 L,  38 R). 
     Each functional gate structure can be formed by providing a functional gate material stack of the gate dielectric material, and the gate conductor material. A planarization process may follow the formation of the functional gate material stack. Block mask technology may be used to selectively provide one of the functional gate structures prior to forming the other functional gate structure. As is shown, the middle-of-the-line (MOL) dielectric material  32  surrounds the first functional gate structure and the second functional gate structure, and a topmost surface of the MOL dielectric material  32  is coplanar with a topmost surface of the first and second functional gate structures. 
     Referring now to  FIG. 11 , there is illustrated another exemplary semiconductor structure of the present application. The exemplary semiconductor structure of  FIG. 11  can be formed utilizing the basic processing steps described and illustrated above with respect to  FIGS. 1-10  except that an undercut process is performed in the sacrificial base layer ( 14 L,  14 R) and filling the same with an insulator (e.g., an oxide) to provide an insulator layer  50 . 
     Referring now to  FIG. 12 , there is illustrated yet another exemplary semiconductor structure of the present application. The exemplary semiconductor structure of  FIG. 12  can be formed utilizing the basic processing steps described and illustrated above with respect to  FIGS. 1-10  except that an undercut process is performed in the sacrificial base layer ( 14 L,  14 R) between  FIGS. 5 and 6  of the present application, and thereafter filling the same with an insulator (e.g., oxide) to provide an insulator layer  50 . 
     While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.