Patent Publication Number: US-6671733-B1

Title: Internal parallel system channel

Description:
FIELD OF INVENTION 
     An apparatus and method for providing connectivity using physical and emulated links so as to allow for simultaneous connection of such nodes particularly in a parallel sysplex environment. 
     BACKGROUND OF THE INVENTION 
     Networks provide the means of exchanging information, whether it is data, voice or other medium. Most networks provide for a plurality of switching nodes connected to each other, and to other communication devices by links. Each link is further characterized by a bandwidth or link capacity. When information is to be exchanged between two communication devices, a path is established within the network connecting the origination nodes to destination nodes and their respective associated devices. In many networks, the specified origin and destination nodes are connected through physical paths. In other instances, wherein each path is characterized by a predetermined bandwidth, the origin-to-destination paths are referred to as “logical” or “virtual” paths. It is possible that several such virtual paths may co-exist along all or some part of a physical path within a network. An important element of logical network design is the process of selecting a set of physical paths through the network having sufficient capacity for carrying the estimated traffic of a communications system. This process may take into account various factors such as network topology and available network resources. 
     It should also be noted that logical paths and the grouping of such logical paths into one or more logical sub-networks can characterize both or a network having a set of logical sub-networks for serving various users, and often such sub-networks are re-dimensioned from time to time to serve changing traffic requirements. 
     In a parallel sysplex environment, transfer of commands, responses and data-necessitates the use of high bandwidth fiber-optic links. Furthermore, shared database software in the sysplex requires the use of transceivers for interchange of command and data between an operating system database and a control program, such as Coupling Facility. The control program resides within a logical partition on a CEC which may or may not be dedicated to it. In instances where the CEC is not dedicated, other logical partitions on that CEC may exist as operating system database nodes in the sysplex. 
     In current sysplex implementations, a database node which resides in the same CEC must use fiber-optic links and transceivers to establish connectivity. Nonetheless, the existing art does not provide for instances where virtual connections and physical connections, can co-exist between origin to destination nodes primarily when the operating system and the control program co-exist within the same CEC. The present invention provides connectivity using physical and emulated links so as to allow for simultaneous connection of such nodes. 
     SUMMARY OF THE INVENTION 
     The method and apparatus described by the present invention provide connectivity in a computer network environment that includes a plurality of nodes, interface links and at least one central electronic complex divided into one or more physical and or virtual sub-environments. A first control program is provided in the central electronic complex in order to establish a first command process layer and a first transfer process layer within this first control program for handling data. The first command process layer is then linked to the first transfer process layer in this control program. A second control program is also provided in the central electronic complex in order to establish a second command process layer and a second transfer process layer within this second control program for handling data. The second command process layer is also linked to the second transfer layer in said second control program. Ultimately a link is emulated between the first transfer process layer and the second transfer process layer; and a physical interface is provided between the first transfer process layer and the second transfer process layer without affecting any of the logical interface(s) between the transfer process layers. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of practice, together with further objects and advantages thereof, may best be understood by reference to the following description taken in connection with the accompanying drawings in which: 
     FIG. 1 is an illustration of the protocol layers that exist in a current parallel sysplex connection using link hardware as provided by one embodiment of the present invention; 
     FIG. 2 depicts a parallel sysplex connection as used by one embodiment of the present invention; 
     FIG. 3 is an illustration of a coupling system with links as per one embodiment of the present invention; and 
     FIG. 4 is an illustration of the protocol layers that exist in a current parallel sysplex connection using link hardware. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 illustrates the function and protocol layers ( 100 ,  102 ,  130 , and  140 ) that exist in a current parallel sysplex connection using link hardware. The arrows shown as  105  and  107  respectively, indicate a logical or functional relation between similar protocol layers. The arrows shown as  110  and  120  respectively, indicate the physical interfaces between different protocol layers, i.e. the actual signal path required in the current implementation to allow the similar protocol layers to communicate. 
     The invention as illustrated in FIG. 1, replaces the Link Transceiver Layers as illustrated in FIG. 4 by adding a direct connection, shown at  112 , between the Transfer Process Layers  130  and  140 . 
     FIG. 2 depicts a parallel sysplex connection using one embodiment of the present invention. One objective of this design is to replace the link transceiver layers and the interfaces between them by adding a physical interface between the transfer process layers  230  and  240 . The logical interface between the transfer process layers is unaffected by the invention and remains unchanged. 
     To accomplish this task, the Send Message Instruction in the transfer process layer is invoked with a subchannel as a parameter. This subchannel describes the CF node target and a subset of possible links that can be used to communicate between the OS node and the CF node. The transfer process layer selects among available non-busy links to initiate the communication. Each link, whether a physical link or an emulated link, is associated with a link control block located in the hardware system area. Hardware links use the link control block to store link status and interface information that is needed to communicate with the link transceiver layer. In the invention, the emulated link uses the link control block for a different purpose. The emulated link does not need a protocol description for communicating with the link transceiver layer because this layer is eliminated when an emulated link is present. However, the emulated link needs to replace the physical interface between the OS node and CF node link transceiver layers in FIG.  1 . The link control block of the emulated link provides this replacement in the invention. 
     In FIG. 3, the coupling system definition for a CEC with emulated links generate link control blocks in fixed pairs where one link control block of the pair belongs to OS node transfer process layer and the other link control block of the pair belongs to the CF node transfer process layer. 
     Certain CPU code has the ability to move information between logical partitions by translating the addresses within a partition to a common host absolute e address format. 
     A link control block that is used to manage the link transceiver interface is given an additional function when it is used to describe one of the emulated links. For emulated links, the link control blocks must be defined in pairs, one for the OS node  200  and one for the CF node  202 . 
     The present invention has the ability to take advantage of a number of existing elements in the current sysplex implementation and the I/O subsystem design. With the help of some modifications, the current implementation can be used. In an alternate embodiment some new elements have been added. 
     New Elements 
     Buffer Busy Indicators 
     A control block in the hardware system area includes an area to indicate that a new command has been placed in the CF partner link control for execution by the CF operating system. These Buffer Busy indicators are examined by the Locate Channel Buffer instruction and information on the location of the new command is returned to the CF operating system code. 
     Error State Pending Indicators 
     A control block in the hardware system area has an Error State Pending indicator for each Internal Channel in the system. The Error State Pending indicators are tested and manipulated by the Test Message Path State and Clear Message Path State instructions. 
     Message Responses 
     The response block of a primary message is stored directly to the OS partition by licensed internal code running in the CF partition. The exact location of the message response block (MRB) is determined from information located in the OS partner link control block. Completion status in the OS partner link control block is updated by licensed internal code running in the CF partition. Responses to operations that are completed asynchronously to the originating SMSG instruction are queued to an asynchronous message Processor and completion is indicated in the subchannel. 
     Data Mover (Scatter/Gather) 
     The data areas in the OS partition are addressed as link data buffer addresses by the SMSG instruction. However, the data areas in the CF partition are addressed according to different logical definitions. The internal channel data moving instruction in the CF partition moves data appropriately between these buffers which may have different numbers and lengths. 
     Secondary Command Handling 
     A processor or channel that receives the secondary message (i.e. at the OS partition side of the secondary command transfer) normally performs secondary commands that are sent from a CF partition to an OS partition. For internal channels, the secondary command is performed by the CF partition, which originates the secondary command. The command is interpreted as if it is already present at the OS partition channel. These secondary commands include cross invalidates, list notifications and fencing requests. 
     Use of Existing Elements 
     Subchannels 
     A S/390 subchannel is used to describe to Coupling Facility to the transport protocol layer. 
     Channel Path Ids 
     An Internal Channel is assigned a channel path ID in the range 0-255. 
     Path Selection Controls 
     The Internal Channel path is selected using the same controls as used to select the fiber optic channels. 
     Coupling Facility Link Buffer Operation Controls 
     The Internal Channel uses the same architected and internal facilities to represent the state of the channel as used by the fiber optic channels. 
     CPU Operand Access Control Registers/Zone Relocation 
     The Internal Channel uses the addressing and translation functions of the Operand Access Control Registers to effect the access of storage in multiple LPAR partitions (zones) by the licensed internal code that implements the Internal Channel function. 
     Modified Elements 
     Link Controls 
     The Link Control Block has several changes for the Internal Channel: 
     An indicator that this link is an Internal Channel 
     A pointer to the partner link control block at the other end of the emulated link. 
     LPAR partition (zone) addressing information for the current active operation. 
     Send Message Instruction 
     The modification of the Send Message Instruction includes: 
     A test to determine if the selected path is an Internal Channel. 
     Moving the Message Command Block (MCB) to the appropriate buffer control area in the Coupling Facility partition. 
     Formation of a list of addresses within the OS logical partition which identify either 1) the origin of data to be written to the Coupling Facility or 2) the location of data to be read from the Coupling Facility. 
     Setting the emulated busy bit associated with this Internal Channel buffer. 
     Locate Channel Buffer Instruction 
     The modification of the Locate Channel Buffer instruction includes: 
     Additional controls for searching and recording the emulated busy vectors. 
     Additional controls for selecting the Channel Operation Block. 
     Signal Channel Buffer Instruction 
     The modification of the Signal Channel Buffer instruction includes: 
     A test to determine if the selected path is an Internal Channel. 
     Calculation of the address of the MRB associated with the MCB launched from the OS partner link control block. 
     Storing the MRB to the zone address within the OS logical partition. 
     Setting completion indication in the partner OS link control block. 
     Setting the,control mechanisms necessary for completing the message asynchronously. 
     Move Channel Buffer Data Multiple Instruction 
     The modification of the Move Channel Buffer Data Multiple instruction includes: 
     A test to determine if the selected path is an Internal Channel. 
     A test to determine if data must be written to or read from the CF. 
     Translation of data area addresses in the OS partition and the CF partition necessary to move the data between the partitions. 
     Move the data and set an indication that the data move is complete. 
     Test Message Path State Instruction 
     The modification of the Test Message Path State instruction includes: 
     A test to determine if the selected path is an 
     Internal Channel Testing of the emulated Error State Pending indicators. 
     Clear Message Path State Instruction 
     The modification of the Clear Message Path State instruction includes: 
     A test to determine if the selected path is an Internal Channel Manipulation of the emulated Error State Pending indicators. 
     While the invention has been described in detail herein in accordance with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit and scope of the invention.