Patent Publication Number: US-11652096-B2

Title: Memory cell array and method of manufacturing same

Description:
PRIORITY CLAIM 
     This application is a continuation of U.S. application Ser. No. 16/587,601, filed Sep. 30, 2019, now U.S. Pat. No. 10,950,595, issued Mar. 16, 2021, which is a continuation of U.S. application Ser. No. 15/964,492, filed Apr. 27, 2018, now U.S. Pat. No. 10,431,576, issued Oct. 1, 2019, which claims the benefit of U.S. Provisional Application No. 62/660,834, filed Apr. 20, 2018, which are herein incorporated by reference in their entireties. 
    
    
     BACKGROUND 
     The semiconductor integrated circuit (IC) industry has produced a wide variety of digital devices to address issues in a number of different areas. Some of these digital devices, such as memory macros, are configured for the storage of data. For example, in some applications, a cache is a particular memory macro that can be used on an IC chip. Furthermore, in some applications, cache can be configured to store recently used data such that subsequent accesses of recent data can be implemented by accessing the cache as opposed to accessing memory located off of the IC chip (e.g., off-chip). In general, a larger cache allows more recent data to be stored on-chip resulting in less off-chip memory data access. The design of smaller memory cells enables denser ICs and speeds up overall IC performance. Therefore, alternatives to 6-transistor (6T) synchronous random access memory (SRAM) are desired. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    is a circuit diagram of a memory cell, in accordance with some embodiments. 
         FIG.  2 A  is a block diagram of a memory cell array having a plurality of memory cells in  FIG.  1   , in accordance with some embodiments. 
         FIG.  2 B  is a circuit diagram of a memory cell array having a plurality of memory cells in  FIG.  1   , in accordance with some embodiments. 
         FIG.  3 A  is a diagram of a layout design, in accordance with some embodiments. 
         FIG.  3 B  is a diagram of a layout design, in accordance with some embodiments. 
         FIG.  4 A  is a diagram of a layout design, in accordance with some embodiments. 
         FIG.  4 B  is a diagram of a layout design, in accordance with some embodiments. 
         FIGS.  5 A,  5 B,  5 C,  5 D,  5 E,  5 F,  5 G and  5 H  are diagrams of at least one integrated circuit, in accordance with some embodiments. 
         FIG.  6    is a diagram of a layout design of a memory cell array, in accordance with some embodiments. 
         FIG.  7    is a diagram of a layout design of a memory cell array, in accordance with some embodiments. 
         FIG.  8    is a diagram of a layout design of a memory cell array, in accordance with some embodiments. 
         FIG.  9    is a flowchart of a method of forming or manufacturing a memory cell array, in accordance with some embodiments. 
         FIGS.  10 A- 10 B  are flowcharts of a method of generating a layout design of a memory cell array, in accordance with some embodiments. 
         FIG.  11    is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith, in accordance with some embodiments. 
         FIG.  12    is a block diagram of a system for designing an IC layout design, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides different embodiments, or examples, for implementing features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not limiting. Other components, materials, values, steps, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     In accordance with some embodiments, a method of forming a memory cell array includes generating a first set of tiles extending in a first direction and generating a second set of tiles extending in the first direction. In some embodiments, each tile of the first set of tiles corresponds to a first layout design of a first set of memory cells. In some embodiments, each tile of the second set of tiles corresponds to a second layout design of a second set of memory cells. 
     In some embodiments, each memory cell of the first set of memory cells comprises a five transistor (5T) synchronous random access memory (SRAM) memory cell. In some embodiments, each memory cell of the second set of memory cells comprises a 5T SRAM memory cell. 
     In some embodiments, the first set of memory cells are arranged in at least a first row and a second row of the memory cell array. In some embodiments, the second set of memory cells are arranged in at least a third row and a fourth row of the memory cell array. 
     In some embodiments, a shape of the first set of tiles or a shape of the second set of tiles is non-rectangular which results in smaller standard cells than other designs. In some embodiments, by having smaller standard cells, the first set of tiles or the second set of tiles can be utilized to manufacture integrated circuits that are smaller than other integrated circuits. 
     The first set of tiles and the second set of tiles alternate with each other in the second direction. In some embodiments, the second set of tiles is separated from the first set of tiles in the second direction. 
     In some embodiments, each tile of the first set of tiles is offset from an adjacent tile of the first set of tiles in a second direction different from the first direction. In some embodiments, each tile of the second set of tiles is offset from an adjacent tile of the second set of tiles in the second direction. 
     In some embodiments, generating the first set of tiles includes generating the first layout design of the first set of memory cells. In some embodiments, generating the second set of tiles includes generating the second layout design of the second set of memory cells. 
     In some embodiments, each tile of the first set of tiles and each tile of the second set of tiles extends in a third direction different from the first direction and the second direction. 
       FIG.  1    is a circuit diagram of a memory cell  100 , in accordance with some embodiments. 
     Memory cell  100  is a five transistor (5T) single port (SP) static random access memory (SRAM) memory cell used for illustration. In some embodiments, memory cell  100  employs a number of transistors other than five. Other types of memory are within the scope of various embodiments. 
     Memory cell  100  comprises three P-type metal oxide semiconductor (PMOS) transistors P 1 , P 2  and P 3 , and two N-type metal oxide semiconductor (NMOS) transistors N 1  and N 2 . Transistors P 1 , P 2 , N 1 , and N 2  form a cross-latch or a pair of cross-coupled inverters. For example, PMOS transistor P 1  and NMOS transistor N 1  form a first inverter while PMOS transistor P 2  and NMOS transistor N 2  form a second inverter. 
     A source terminal of each of PMOS transistors P 1  and P 2  are configured as a voltage supply node NODE_ 1 . Each voltage supply node NODE_ 1  is coupled to a first voltage source VDDI. A drain terminal of PMOS transistor P 1  is coupled with a drain terminal of NMOS transistor N 1 , a gate terminal of PMOS transistor P 2 , a gate terminal of NMOS transistor N 2 , and is configured as a storage node NDB. 
     A drain terminal of PMOS transistor P 2  is coupled with a drain terminal of NMOS transistor N 2 , a gate terminal of PMOS transistor P 1 , a gate terminal of NMOS transistor N 1 , a source terminal of PMOS transistor P 3 , and is configured as a storage node ND. A source terminal of each of NMOS transistors N 1  and N 2  is configured as a supply reference voltage node (not labelled) having a supply reference voltage VSS. The source terminal of each of NMOS transistors N 1  and N 2  is also coupled to supply reference voltage VSS. 
     A word line WL 1  is coupled with a gate terminal of PMOS transistor P 3 . Word line WL 1  is also called a write control line because PMOS transistor P 3  is configured to be controlled by a signal on word line WL 1  in order to transfer data between bit line BL 1  and node ND. 
     A drain terminal of PMOS transistor P 3  is coupled to a bit line BL 1 . Bit line BL 1  is configured as both data input and output for memory cell  100 . In some embodiments, in a write operation, applying a logical value to a bit line BL 1  enables writing the logical value on the bit line BL 1  to memory cell  100 . Bit line BL 1  is called a data line because the data carried on bit line BL 1  is written to and read from node ND. In some embodiments, the source terminal of PMOS transistor P 3  is coupled to the bit line BL 1 , and the drain terminal of PMOS transistor P 3  is coupled to the storage node ND. 
       FIG.  2 A  is a block diagram of a memory cell array  200 A having a plurality of memory cells in  FIG.  1   , in accordance with some embodiments. For example, memory cell  100  of  FIG.  1    is usable as one or more memory cells in memory cell array  200 A. 
     Memory cell array  200 A comprises an array of memory cells  202 [ 1 , 1 ],  202 [ 1 , 2 ], . . . ,  202 [ 2 , 2 ], . . . ,  202 [M,N] (collectively referred to as “array of memory cells  202 A”) having M rows and N columns, where N is a positive integer corresponding to the number of columns in array of memory cells  202 A and M is a positive integer corresponding to the number of rows in array of memory cells  202 A. The rows of cells in array of memory cells  202 A are arranged in a first direction X. The columns of cells in array of memory cells  202 A are arranged in a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. Memory cell  100  of  FIG.  1    is usable as one or more memory cells in array of memory cells  202 A. 
     Memory cell array  200 A further includes 2N bit lines BL[1], . . . BL[2N] (collectively referred to as “bit line BL”). Each column  1 , . . . , N in array of memory cells  202 A is overlapped by a pair of bit lines BL[1], . . . , BL[2N]. Each bit line BL extends in the second direction Y and is over a column of cells (e.g., column  1 , . . . , N). In some embodiments, memory cell array  200 A does not include one or more bit line bars BLB. Note that the term “bar” as used in this context indicates a logically inverted signal, for example, bit line bar BLB[1], . . . BLB[N] carries a signal logically inverted from a signal carried by bit line BL[1], . . . BL[N]. 
     A bit line of the set of bit lines BL in array of memory cells  202 A or array of memory cells  202 B of  FIG.  2 B  corresponds to bit line BL 1  of  FIG.  1   . 
     In some embodiments, a pair of memory cells of array of memory cells  202 A are positioned between a pair of bit lines of bit lines BL. For example, in row  1  and column  1  of memory cell array  200 A, memory cell  202 [1,1] and memory cell  202 [1,2] are each positioned between bit line BL[1] and BL[2]. Similarly, in row  1  and column  2  of memory cell array  200 A, memory cell  202 [1,3] and memory cell  202 [1,4] are each positioned between bit line BL[3] and BL[4]. 
     Memory cell array  200 A further includes 2M word lines WL[1], . . . WL[2M] (collectively referred to as “word line WL”). Each word line WL extends in the first direction X and is over a row of cells (e.g., row  1 , . . . , M). Each row  1 , . . . , M in array of memory cells  202 A is overlapped by a pair of word lines WL[1], . . . , WL[2M]. For example, word line WL[1] and WL[2] each overlap row  1  of array of memory cells  202 A. Similarly, word line WL[3] and WL[4] each overlap row  2  of array of memory cells  202 A and word line WL[7] and WL[2M] each overlap row M of array of memory cells  202 A. 
     A word line of the set of word lines WL in array of memory cells  202 A or array of memory cells  202 B of  FIG.  2 B  corresponds to word line WL 1  of  FIG.  1   . 
     In some embodiments, each row of memory cells of array of memory cells  202 A are positioned between a pair of word lines of word lines WL. For example, in row  1  of memory cell array  200 A, memory cells  202 [1,1],  202 [1,2], . . . ,  202 [1,N] are positioned between word line WL[1] and WL[2]. Similarly, in row  2  of memory cell array  200 A, memory cells  202 [2,1],  202 [2,2], . . . ,  202 [2,N] are positioned between word line WL[3] and WL[4]. 
     Each memory cell in the array of memory cells  202 A is coupled to a corresponding bit line of bit lines BL and a corresponding word line of word lines WL. For example, memory cell  202 [1,1] is coupled to bit line BL[1] and word line WL[1]. Similarly, memory cell  202 [1,2] is coupled to bit line BL[2] and word line WL[2], memory cell  202 [1,3] is coupled to bit line BL[3] and word line WL[2], memory cell  202 [2,1] is coupled to bit line BL[1] and word line WL[4], and memory cell  202 [2,2] is coupled to bit line BL[2] and word line WL[3]. 
     Memory cells of the array of memory cells  202 A are grouped into a first set of memory cells  204  and a second set of memory cells  206 . 
     The first set of memory cells  204  includes memory cells  204   a ,  204   b , . . . ,  204   i.    
     The second set of memory cells  206  includes memory cells  206   a ,  206   b ,  206   c  and  206   d.    
     In some embodiments, the memory cells of the first set of memory cells  204  correspond to memory cells of a first layout design type (e.g., layout designs  300 A- 300 B of  FIGS.  3 A- 3 B ), and the second set of memory cells  206  correspond to memory cells of a second layout design type (e.g., layout designs  400 A- 400 B of  FIGS.  4 A- 4 B ) different from the first layout design type. 
     In some embodiments, the memory cells of the first set of memory cells  204  correspond to memory cells of the second layout design type (e.g., layout designs  400 A- 400 B of  FIGS.  4 A- 4 B ), and the second set of memory cells  206  correspond to memory cells of the first layout design type (e.g., layout designs  300 A- 300 B of  FIGS.  3 A- 3 B ). 
       FIG.  2 B  is a circuit diagram of a memory cell array  200 B having a plurality of memory cells in  FIG.  1   , in accordance with some embodiments. Memory cell array  200 B is an embodiment of the block diagram of memory cell array  200 A of  FIG.  2 A  expressed in a circuit diagram. Memory cell  100  of  FIG.  1    is usable as one or more memory cells in memory cell array  200 B. 
     In comparison with memory cell array  200 A of  FIG.  2 A , array of memory cells  202 B of memory cell array  200 B replace array of memory cells  202 A of  FIG.  2 A . Array of memory cells  202 B is an embodiment of the array of memory cells  202 A of  FIG.  2 A . 
     Each memory cell in the array of memory cells  202 B comprises a corresponding PMOS transistor P 3 [1,1], P 3 [1,2] . . . , P[M,N] of a set of PMOS transistors  210  (not labelled) coupled to each of a corresponding inverter I 1 [1,1], I 1 [1,2], . . . , I 1 [M,N] of a first set of inverters  212  (not labelled) and a corresponding inverter I 2 [1,1], I 2 [1,2], . . . , I 2 [M,N] of a second set of inverters  214  (not labelled). The first set of inverters  212  and the second set of inverters  214  are part of a set of cross-coupled inverters  216  (not labelled). 
     One or more of PMOS transistors P 3 [1,1], P 3 [1,2], . . . , P 3 [M,N] of the set of PMOS transistors  210  in array of memory cells  202 B corresponds to PMOS transistor P 3  of  FIG.  1   . 
     One or more of inverters I 1 [1,1], I 1 [1,2], . . . , I 1 [M,N] of the first set of inverters  212  in array of memory cells  202 B corresponds to PMOS transistor P 2  and NMOS transistor N 2  of  FIG.  1   . 
     One or more of inverters I 2 [1,1], I 2 [1,2], . . . , I 2 [M,N] of the second set of inverters  214  in array of memory cells  202 B corresponds to PMOS transistor P 1  and NMOS transistor N 1  of  FIG.  1   . 
     In some embodiments, one or more memory cells of memory cell array  200 A or  200 B includes one or more single port (SP) SRAM cells. In some embodiments, one or more memory cells of memory cell array  200 A or  200 B includes one or more dual port (DP) SRAM cells. Different types of memory cells in memory cell array  200 A or  200 B are within the contemplated scope of the present disclosure. Different configurations of array of memory cells  202 A or  202 B are within the contemplated scope of the present disclosure. Different configurations of bit lines BL or word lines WL in array of memory cells  202 A or  202 B are within the contemplated scope of the present disclosure. 
     In some embodiments, memory cell array  200 A- 200 B includes an array of 5T SRAM cells ( FIG.  1   ) causing memory cell array  200 A- 200 B to include less transistors than other memory cell arrays. In some embodiments, by memory cell array  200 A- 200 B including less transistors, memory cell array  200 A- 200 B occupies less area than other memory cell arrays. In some embodiments, by occupying less area than other memory cell arrays, memory cell array  200 A- 200 B is denser and has a larger memory capacity compared with other approaches. 
       FIG.  3 A  is a diagram of a layout design  300 A, in accordance with some embodiments. Layout design  300 A corresponds to a layout diagram of a portion of memory cell array  200 A- 200 B of  FIGS.  2 A- 2 B . For example, layout design  300 A corresponds to a layout design of one or more memory cells  206   a ,  206   b ,  206   c  or  206   d  of the second set of memory cells  206  of  FIGS.  2 A- 2 B . 
     Components that are the same or similar to those in one or more of  FIGS.  3 B,  4 A- 4 B and  6 - 8    (shown below) are given the same reference numbers, and detailed description thereof is thus omitted. 
     Structural relationships including alignment, lengths and widths, as well as configurations of layout design  400 A- 400 B ( FIGS.  4 A- 4 B ), layout design  600  ( FIG.  6   ), layout design  700  ( FIG.  7   ) or layout design  800  ( FIG.  8   ) are similar to the structural relationships and configurations of layout design  300 A or  300 B of  FIGS.  3 A- 3 B , and will not be described in  FIGS.  4 A- 4 B, and  6 - 8    for brevity. 
     Layout design  300 A is usable to manufacture integrated circuit  500 A ( FIGS.  5 A- 5 H ). 
     Layout design  300 A corresponds to a layout design of memory cells  202 [1,2],  202 [1,3],  202 [2,2] and  202 [2,3] of  FIGS.  2 A- 2 B . In some embodiments, layout design  300 A corresponds to a layout design of memory cells  202 [1,6],  202 [1,7],  202 [2,6] and  202 [2,7] of  FIGS.  2 A- 2 B . In some embodiments, layout design  300 A corresponds to a layout design of memory cells  202 [3,2],  202 [3,3],  202 [4,2] and  202 [4,3] of  FIGS.  2 A- 2 B . In some embodiments, layout design  300 A corresponds to a layout design of memory cells  202 [3,6],  202 [3,7],  202 [4,6] and  202 [4,7] of  FIGS.  2 A- 2 B . In some embodiments, layout design  300 A corresponds to a layout design of one or more memory cells  204   a ,  204   b , . . . ,  204   i  of the first set of memory cells  204  of  FIGS.  2 A- 2 B . 
     Layout design  300 A includes a first portion  302   a , a second portion  302   b , a third portion  302   c  and a fourth portion  302   d . A center of layout design  300 A corresponds to a boundary between each of the first portion  302   a , second portion  302   b , third portion  302   c  and fourth portion  302   d . In some embodiments, the first portion  302   a  corresponds to the layout design of memory cell  202 [1,2], the second portion  302   b  corresponds to the layout design of memory cell  202 [2,2], the third portion  302   c  corresponds to the layout design of memory cell  202 [1,3], and the fourth portion  302   d  corresponds to the layout design of memory cell  202 [2,3]. First portion  302   a , second portion  302   b , third portion  302   c  and fourth portion  302   d  have corresponding corner notches  390   a ,  390   b ,  390   c  and  390   d  (see  FIG.  3 B ). Other configurations of the first portion  302   a , second portion  302   b , third portion  302   c  and fourth portion  302   d  are within the scope of the present disclosure. 
     The first portion  302   a  includes active region layout patterns  304   a ,  306   a ,  308   a  and  310   a  (collectively referred to as “set of active region layout patterns  312   a ”). Active region layout patterns  304   a ,  306   a ,  308   a  and  310   a  are useable to manufacture corresponding active regions  504   a   1 ,  506   a   1 ,  508   a   1 , and  510   a   1  of integrated circuit  500 A or  500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, the set of active region layout patterns  312   a  is referred to as an oxide definition (OD) layout pattern which defines source or drain diffusion layout patterns of layout design  300 A- 300 B. For example, in some embodiments, active region layout pattern  304   a  is useable to manufacture the drain and source regions of a PMOS transistor P 1   a  of  FIGS.  3 A- 3 B , active region layout pattern  306   a  is useable to manufacture the drain and source regions of an NMOS transistor N 1   a  of  FIGS.  3 A- 3 B , active region layout pattern  308   a  is useable to manufacture the drain and source regions of an NMOS transistor N 2   a  of  FIGS.  3 A- 3 B , and active region layout pattern  310   a  is useable to manufacture the drain and source regions of PMOS transistors P 2   a  and PG 1   a  of  FIGS.  3 A- 3 B . In some embodiments, PMOS transistor P 1   a  corresponds to PMOS transistor P 1  ( FIG.  1   ), PMOS transistor P 2   a  corresponds to PMOS transistor P 2  ( FIG.  1   ), PMOS transistor PG 1   a  corresponds to PMOS transistor P 3  ( FIG.  1   ), NMOS transistor N 1   a  corresponds to NMOS transistor N 1  ( FIG.  1   ), and NMOS transistor N 2   a  corresponds to NMOS transistor N 2  ( FIG.  1   ). 
     Each of the layout patterns of the set of active region layout patterns  312   a  is separated from an adjacent layout pattern of the set of active region layout patterns  312   a  in a first direction X by a first pitch (not labelled). In some embodiments, an adjacent element is directly next to another element. Each of the layout patterns of the set of active region layout patterns  312   a  extend in a second direction Y different from the first direction X and is located on a first layout level. In some embodiments, the first layout level corresponds to the active region of layout design  300 A- 300 B or  400 A- 400 B ( FIGS.  4 A- 4 B ). 
     Active region layout pattern  304   a  is adjacent or directly next to a first side of the first portion  302   a  of layout design  300 A and a corner notch  390   a . Active region layout pattern  310   a  is adjacent or directly next to a second side of the first portion  302   a  of layout design  300 A. The second side of the first portion  302   a  of layout design  300 A is opposite from the first side of the first portion  302   a  of layout design  300 A. In some embodiments, active region layout pattern  306   a  is adjacent to corner notch  390   a . In some embodiments, the active region layout pattern  304   a  extends from a side of layout design  300 A to the corner notch  390   a  of the layout design. In some embodiments, the active region layout pattern  304   a  and  304   b  extends from notch  390   a  to notch  390   b . In some embodiments, the active region layout pattern  304   b  extends from the side of layout design  300 A to the corner notch  390   b  of the layout design. In some embodiments, the active region layout pattern  304   c  extends from a side of layout design  300 A to the corner notch  390   c  of the layout design. In some embodiments, the active region layout pattern  304   c  and  304   d  extends from notch  390   c  to notch  390   d . In some embodiments, the active region layout pattern  304   d  extends from the side of layout design  300 A to the corner notch  390   d  of the layout design. 
     In some embodiments, a length of active region layout pattern  304   a  in the second direction Y is different from a length of active region layout pattern  310   a  in the second direction Y. In some embodiments, a length of active region layout pattern  306   a  in the second direction Y is different from a length of active region layout pattern  308   a  in the second direction Y. In some embodiments, a length of active region layout pattern  306   a  in the second direction Y is the same as the length of active region layout pattern  308   a  in the second direction Y. Other quantities or configurations of the set of active region layout patterns  312   a  are within the scope of the present disclosure. 
     The first portion  302   a  further includes gate layout patterns  320   a ,  322   a  and  324   a  (collectively referred to as “set of gate layout patterns  326   a ”). In some embodiments, gate layout patterns  320   a ,  322   a  and  324   a  are usable to manufacture corresponding gate structures  520   a ,  522   a  and  524   a  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). In some embodiments, gate layout pattern  320   a  is useable to manufacture gate regions of PMOS transistor P 1   a  and NMOS transistor N 1   a , gate layout pattern  322   a  is useable to manufacture gate regions of NMOS transistor N 2   a  and PMOS transistor P 2   a , and gate layout pattern  324   a  is useable to manufacture a gate region of PMOS transistor PG 1   a . In some embodiments, gate layout pattern  322   a  is adjacent to corner notch  390   a.    
     In some embodiments, each gate layout pattern of the set of gate layout patterns  326   a  extends in the first direction X and overlaps the set of active region layout patterns  312   a . The set of gate layout patterns  326   a  is positioned on a second layout level different from the first layout level. In some embodiments, the second layout level corresponds to the POLY level of layout design  300 A- 300 B or  400 A- 400 B ( FIGS.  4 A- 4 B ). The set of active region layout patterns  312   a  is below the set of gate layout patterns  326   a . Other quantities or configurations of the set of gate layout patterns  326   a  are within the scope of the present disclosure. 
     The first portion  302   a  further includes conductive feature layout patterns  330   a ,  332   a ,  334   a  and  336   a  (collectively referred to as “set of conductive feature layout patterns  338   a ”). In some embodiments, conductive feature layout patterns  330   a ,  332   a ,  334   a  and  336   a  are usable to manufacture corresponding conductive structures  530   a ,  532   a ,  534   a  and  536   a  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, the set of conductive feature layout patterns  338   a  extends in the first direction X, and is over at least the set of active region layout patterns  312   a  or the set of gate layout patterns  326   a . Conductive feature layout pattern  330   a  overlaps active region layout patterns  304   a  and  306   a . Conductive feature layout pattern  334   a  overlaps active region layout patterns  308   a  and  310   a . Conductive feature layout patterns  332   a ,  336   a  are over corresponding active region layout patterns  308   a ,  310   a . In some embodiments, conductive feature layout pattern  330   a  is adjacent to corner notch  390   a.    
     In some embodiments, each conductive feature layout pattern of the set of conductive feature layout patterns  338   a  is separated from an adjacent layout pattern of the set of conductive feature layout patterns  338   a  in at least the first direction X or the second direction Y. The set of conductive feature layout patterns  338   a  is on a third layout level different from the first layout level and the second layout level. In some embodiments, the third layout level corresponds to the metal one (M 1 ) level of layout design  300 A- 300 B or  400 A- 400 B ( FIGS.  4 A- 4 B ). Other quantities or configurations of the set of conductive feature layout patterns  338   a  are within the scope of the present disclosure. 
     The first portion  302   a  further includes via layout patterns  360   a ,  362   a ,  364   a ,  366   a ,  368   a ,  370   a  (collectively referred to as “set of via layout patterns  358   a ”). In some embodiments, via layout patterns  360   a ,  362   a ,  364   a ,  366   a ,  368   a ,  370   a  are usable to manufacture corresponding vias  560   a ,  562   a ,  564   a ,  566   a ,  568   a ,  570   a  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, each via layout pattern of the set of via layout patterns  358   a  is located where each conductive feature layout pattern of the set of conductive feature layout patterns  338   a  overlaps each active region layout pattern of the set of active region layout patterns  312   a . The set of via layout patterns  358   a  are between the set of conductive feature layout patterns  338   a  and the set of active region layout patterns  312   a . In some embodiments, the set of via layout patterns  358   a  are on at least the via zero (V 0 ) level of layout design  300 A- 300 B or  400 A- 400 B ( FIGS.  4 A- 4 B ). In some embodiments, the V 0  level is between the third layout level and the first or second layout level of layout design  300 A- 300 B or  400 A- 400 B ( FIGS.  4 A- 4 B ). In some embodiments, the first portion  302   a  of layout design  300 A is usable to fabricate memory cell  202 [1,2],  202 [1,6],  202 [3,2] or  202 [3,6] of the second set of memory cells  206  of memory cell array  200 A or  200 B. Other quantities or configurations of the set of via layout patterns  358   a  are within the scope of the present disclosure. 
     The second portion  302   b  includes active region layout patterns  304   b ,  306   b ,  308   b  and  310   b  (collectively referred to as “set of active region layout patterns  312   b ”), gate layout patterns  320   b ,  322   b  and  324   b  (collectively referred to as “set of gate layout patterns  326   b ”), conductive feature layout patterns  330   b ,  332   b ,  334   b  and  336   b  (collectively referred to as “set of conductive feature layout patterns  338   b ”) and via layout patterns  360   b ,  362   b ,  364   b ,  366   b ,  368   b ,  370   b  (collectively referred to as “set of via layout patterns  358   b ”). 
     In some embodiments, the first portion  302   a  and the second portion  302   b  of layout design  300 A- 300 B are mirror images of each other with respect to the second direction Y, and similar detailed description is therefore omitted. 
     In some embodiments, active region layout patterns  304   b ,  306   b ,  308   b  and  310   b  are useable to manufacture active regions similar to corresponding active regions  504   a   1 ,  506   a   1 ,  508   a   1 , and  510   a   1  of integrated circuit  500 A or  500 B ( FIGS.  5 A- 5 H ). In some embodiments, gate layout patterns  320   b ,  322   b  and  324   b  are usable to manufacture gate structures similar to corresponding gate structures  520   a ,  522   a  and  524   a  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). In some embodiments, conductive feature layout patterns  330   b ,  332   b ,  334   b  and  336   b  are usable to manufacture conductive structures similar to corresponding conductive structures  530   a ,  532   a ,  534   a  and  536   a  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). In some embodiments, via layout patterns  360   b ,  362   b ,  364   b ,  366   b ,  368   b ,  370   b  are usable to manufacture vias similar to corresponding vias  560   a ,  562   a ,  564   a ,  566   a ,  568   a ,  570   a  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, active region layout patterns  304   a  and  304   b  are part of a same continuous active region layout pattern. In some embodiments, active region layout patterns  308   a  and  308   b  are part of a same continuous active region layout pattern. In some embodiments, active region layout patterns  310   a  and  310   b  are part of a same continuous active region layout pattern. 
     In some embodiments, the second portion  302   b  of layout design  300 A is usable to fabricate memory cell  202 [2,2],  202 [2,6],  202 [M,2] or  202 [M,6] of the second set of memory cells  206  of memory cell array  200 A or  200 B. 
     The third portion  302   c  includes active region layout patterns  304   c ,  306   c ,  308   c  and  310   c  (collectively referred to as “set of active region layout patterns  312   c ”), gate layout patterns  320   c ,  322   c  and  324   c  (collectively referred to as “set of gate layout patterns  326   c ”), conductive feature layout patterns  330   c ,  332   c ,  334   c  and  336   c  (collectively referred to as “set of conductive feature layout patterns  338   c ”) and via layout patterns  360   c ,  362   c ,  364   c ,  366   c ,  368   c ,  370   c  (collectively referred to as “set of via layout patterns  358   c ”). 
     In some embodiments, the first portion  302   a  and the third portion  302   c  of layout design  300 A- 300 B are mirror images of each other with respect to the first direction X, and similar detailed description is therefore omitted. 
     In some embodiments, active region layout patterns  304   c ,  306   c ,  308   c  and  310   c  are useable to manufacture active regions similar to corresponding active regions  504   a   1 ,  506   a   1 ,  508   a   1 , and  510   a   1  of integrated circuit  500 A or  500 B ( FIGS.  5 A- 5 H ). In some embodiments, gate layout patterns  320   c ,  322   c  and  324   c  are usable to manufacture gate structures similar to corresponding gate structures  520   a ,  522   a  and  524   a  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). In some embodiments, conductive feature layout patterns  330   c ,  332   c ,  334   c  and  336   c  are usable to manufacture conductive structures similar to corresponding conductive structures  530   a ,  532   a ,  534   a  and  536   a  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). In some embodiments, via layout patterns  360   c ,  362   c ,  364   c ,  366   c ,  368   c ,  370   c  are usable to manufacture vias similar to corresponding vias  560   a ,  562   a ,  564   a ,  566   a ,  568   a ,  570   a  of integrated circuit  500 A- 500 B (FIGS.  5 A- 5 H). In some embodiments, gate layout patterns  324   a  and  324   c  are part of a same continuous gate layout pattern. 
     In some embodiments, the third portion  302   c  of layout design  300 A is usable to fabricate memory cell  202 [1,3],  202 [1,7],  202 [3,3] or  202 [3,7] of the second set of memory cells  206  of memory cell array  200 A or  200 B. 
     The fourth portion  302   d  includes active region layout patterns  304   d ,  306   d ,  308   d  and  310   d  (collectively referred to as “set of active region layout patterns  312   d ”), gate layout patterns  320   d ,  322   d  and  324   d  (collectively referred to as “set of gate layout patterns  326   d ”), conductive feature layout patterns  330   d ,  332   d ,  334   d  and  336   d  (collectively referred to as “set of conductive feature layout patterns  338   d ”) and via layout patterns  360   d ,  362   d ,  364   d ,  366   d ,  368   d ,  370   d  (collectively referred to as “set of via layout patterns  358   d ”). 
     In some embodiments, the third portion  302   c  and the fourth portion  302   d  of layout design  300 A- 300 B are mirror images of each other with respect to the second direction Y, and similar detailed description is therefore omitted. In some embodiments, the second portion  302   b  and the fourth portion  302   d  of layout design  300 A- 300 B are mirror images of each other with respect to the first direction X, and similar detailed description is therefore omitted. 
     In some embodiments, active region layout patterns  304   d ,  306   d ,  308   d  and  310   d  are useable to manufacture active regions similar to corresponding active regions  504   a   1 ,  506   a   1 ,  508   a   1 , and  510   a   1  of integrated circuit  500 A or  500 B ( FIGS.  5 A- 5 H ). In some embodiments, active region layout patterns  304   b ,  304   c  and  304   d  are useable to manufacture the drain and source regions of corresponding PMOS transistors P 1   b , P 1   c  and P 1   d , active region layout patterns  306   b ,  306   c  and  306   d  are useable to manufacture the drain and source regions of corresponding NMOS transistors N 1   b , N 1   c  and N 1   d , active region layout patterns  308   b ,  308   c  and  308   d  are useable to manufacture the drain and source regions of corresponding NMOS transistors N 2   b , N 2   c  and N 2   d , active region layout pattern  310   b  is useable to manufacture the drain and source regions of PMOS transistors P 2   b  and PG 1   b , active region layout pattern  310   c  is useable to manufacture the drain and source regions of PMOS transistors P 2   c  and PG 1   c , and active region layout pattern  310   d  is useable to manufacture the drain and source regions of PMOS transistors P 2   d  and PG 1   d.    
     In some embodiments, PMOS transistor P 1   b , P 1   c  or P 1   d  is similar to PMOS transistor P 1  ( FIG.  1   ), PMOS transistor P 2   b , P 2   c  or P 2   d  is similar to PMOS transistor P 2  ( FIG.  1   ), PMOS transistor PG 1   b , PG 1   c  or PG 1   d  is similar to PMOS transistor P 3  ( FIG.  1   ), NMOS transistor N 1   b , N 1   c  or N 1   d  is similar to NMOS transistor N 1  ( FIG.  1   ), and NMOS transistor N 2   b , N 2   c  or N 2   d  is similar to NMOS transistor N 2  ( FIG.  1   ). 
     In some embodiments, gate layout patterns  320   d ,  322   d  and  324   d  are usable to manufacture gate structures similar to corresponding gate structures  520   a ,  522   a  and  524   a  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). In some embodiments, gate layout pattern  320   b  is useable to manufacture gate regions of PMOS transistor P 1   b  and NMOS transistor N 1   b , gate layout pattern  322   b  is useable to manufacture gate regions of NMOS transistor N 2   b  and PMOS transistor P 2   b , gate layout pattern  320   c  is useable to manufacture gate regions of PMOS transistor P 1   c  and NMOS transistor N 1   c , gate layout pattern  322   c  is useable to manufacture gate regions of NMOS transistor N 2   c  and PMOS transistor P 2   c , gate layout pattern  320   d  is useable to manufacture gate regions of PMOS transistor P 1   d  and NMOS transistor N 1   d , gate layout pattern  322   d  is useable to manufacture gate regions of NMOS transistor N 2   d  and PMOS transistor P 2   d , and gate layout patterns  324   b ,  324   c  and  324   d  are useable to manufacture corresponding gate regions of PMOS transistors PG 1   b , PG 1   c  and PG 1   d.    
     In some embodiments, conductive feature layout patterns  330   d ,  332   d ,  334   d  and  336   d  are usable to manufacture conductive structures similar to corresponding conductive structures  530   a ,  532   a ,  534   a  and  536   a  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). In some embodiments, via layout patterns  360   d ,  362   d ,  364   d ,  366   d ,  368   d ,  370   d  are usable to manufacture vias similar to corresponding vias  560   a ,  562   a ,  564   a ,  566   a ,  568   a ,  570   a  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, active region layout patterns  304   c  and  304   d  are part of a same continuous active region layout pattern. In some embodiments, active region layout patterns  308   c  and  308   d  are part of a same continuous active region layout pattern. In some embodiments, active region layout patterns  310   c  and  310   d  are part of a same continuous active region layout pattern. 
     Each of the set of active region layout patterns  312   b ,  312   c  and  312   d  is similar to the set of active region layout patterns  312   a , and similar detailed description is therefore omitted. Each of the set of gate layout patterns  326   b ,  326   c  and  326   d  is similar to the set of gate layout patterns  326   a , and similar detailed description is therefore omitted. Each of the set of conductive feature layout patterns  338   b ,  338   c  and  338   d  is similar to the set of conductive feature layout patterns  338   a , and similar detailed description is therefore omitted. Each of the set of via layout patterns  358   b ,  358   c  and  358   d  is similar to the set of via layout patterns  358   a , and similar detailed description is therefore omitted. In some embodiments, gate layout patterns  324   b  and  324   d  are part of a same continuous gate layout pattern. 
     In some embodiments, the fourth portion  302   d  of layout design  300 A is usable to fabricate memory cell  202 [2,3],  202 [2,7],  202 [M,3] or  202 [M,7] of the second set of memory cells  206  of memory cell array  200 A or  200 B. 
     Other quantities or configurations of the set of active region layout patterns  312   b ,  312   c ,  312   d , the set of gate layout patterns  326   b ,  326   c ,  326   d , the set of conductive feature layout patterns  338   b ,  338   c ,  338   d , or the set of via layout patterns  358   b ,  358   c  and  358   d  are within the scope of the present disclosure. 
     Layout design  300 A further includes conductive feature layout patterns  340   a ,  340   b  (collectively referred to as “set of conductive feature layout patterns  340 ”). In some embodiments, conductive feature layout patterns  340   a  and  340   b  are usable to manufacture conductive structure  540   a  or similar conductive structures of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, the set of conductive feature layout patterns  340  extends in the first direction X, and is over gate layout patterns  324   a  and  324   b . Conductive feature layout pattern  340   a  is over gate layout pattern  324   a . Conductive feature layout pattern  340   b  is over gate layout pattern  324   b.    
     In some embodiments, each conductive feature layout pattern of the set of conductive feature layout patterns  340  is separated from an adjacent layout pattern of the set of conductive feature layout patterns  340  in at least the second direction Y. The set of conductive feature layout patterns  340  is on the third layout level. 
     Layout design  300 A further includes conductive feature layout patterns  342   a ,  342   b  (collectively referred to as “set of conductive feature layout patterns  342 ”). In some embodiments, conductive feature layout patterns  342   a  and  342   b  are usable to manufacture corresponding conductive structures  542   a  and  542   b  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). In some embodiments, the set of conductive feature layout patterns  342  extends in the first direction X. Conductive feature layout pattern  342   a  is over active region layout patterns  304   a  and  304   b . Conductive feature layout pattern  342   b  is over active region layout patterns  306   a  and  306   b . In some embodiments, each conductive feature layout pattern of the set of conductive feature layout patterns  342  is separated from an adjacent layout pattern of the set of conductive feature layout patterns  342  in at least the first direction X. The set of conductive feature layout patterns  342  is on the third layout level. 
     Layout design  300 A further includes conductive feature layout patterns  344   a ,  344   b  (collectively referred to as “set of conductive feature layout patterns  344 ”). In some embodiments, conductive feature layout patterns  344   a  and  344   b  are usable to manufacture conductive structures similar to corresponding conductive structures  542   a  and  542   b  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). In some embodiments, the set of conductive feature layout patterns  344  extends in the first direction X. Conductive feature layout pattern  344   a  is over active region layout patterns  304   c  and  304   d . Conductive feature layout pattern  344   b  is over active region layout patterns  306   c  and  306   d . In some embodiments, each conductive feature layout pattern of the set of conductive feature layout patterns  344  is separated from an adjacent layout pattern of the set of conductive feature layout patterns  344  in at least the first direction X. The set of conductive feature layout patterns  344  is on the third layout level. 
     Layout design  300 A further includes at least conductive feature layout pattern  350   a  (collectively referred to as “set of conductive feature layout patterns  350 ”). In some embodiments, conductive feature layout pattern  350   a  is usable to manufacture conductive structure  550   a  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, conductive feature layout pattern  350   a  extends in the first direction X, and is over at least active region layout patterns  310   a ,  310   b ,  310   c  and  310   d.    
     In some embodiments, each conductive feature layout pattern  350   a  of the set of conductive feature layout patterns (not labelled) is separated from an adjacent layout pattern of the set of conductive feature layout patterns (not labelled) in at least the first direction X or the second direction Y. The conductive feature layout pattern  350   a  is on a fourth layout level different from the first layout level, the second layout level and the third layout level. In some embodiments, the fourth layout level corresponds to the metal two (M 2 ) level of layout design  300 A- 300 B or  400 A- 400 B ( FIGS.  4 A- 4 B ). 
     Layout design  300 A further includes via layout patterns  374   a ,  374   b  (collectively referred to as “set of via layout patterns  374 ”). In some embodiments, via layout patterns  374   a ,  374   b  are usable to manufacture corresponding vias  574   a ,  574   b  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). In some embodiments, each via layout pattern of the set of via layout patterns  374  is located where conductive feature layout pattern  342   a  overlaps active region layout patterns  304   a  and  304   b , or where conductive feature layout pattern  342   b  overlaps active region layout patterns  306   a  and  306   b . Via layout pattern  374   a  is between conductive feature layout pattern  342   a  and active region layout patterns  304   a  and  304   b . Via layout pattern  374   b  is between conductive feature layout pattern  342   b  and active region layout patterns  306   a  and  306   b . In some embodiments, the set of via layout patterns  374  are on at least the V 0  level of layout design  300 A- 300 B or  400 A- 400 B ( FIGS.  4 A- 4 B ). 
     Layout design  300 A further includes via layout patterns  376   a ,  376   b  (collectively referred to as “set of via layout patterns  376 ”). In some embodiments, via layout patterns  376   a ,  376   b  are usable to manufacture vias similar to corresponding vias  574   a ,  574   b  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). In some embodiments, each via layout pattern of the set of via layout patterns  376  is located where conductive feature layout pattern  344   a  overlaps active region layout patterns  304   c  and  304   d , or where conductive feature layout pattern  344   b  overlaps active region layout patterns  306   c  and  306   d . Via layout pattern  376   a  is between conductive feature layout pattern  344   a  and active region layout patterns  304   c  and  304   d . Via layout pattern  376   b  is between conductive feature layout pattern  344   b  and active region layout patterns  306   c  and  306   d . In some embodiments, the set of via layout patterns  376  are on at least the V 0  level of layout design  300 A- 300 B or  400 A- 400 B ( FIGS.  4 A- 4 B ). 
     Layout design  300 A further includes via layout patterns  378   a ,  378   b  (collectively referred to as “set of via layout patterns  378 ”). In some embodiments, via layout patterns  378   a ,  378   b  are usable to manufacture via  578   a  or similar to via  578   a  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). In some embodiments, the set of via layout patterns  378  is located where conductive feature layout pattern  350   a  overlaps active region layout patterns  310   a ,  310   b ,  310   c  and  310   d . Via layout pattern  378   a  is between conductive feature layout pattern  350   a  and active region layout patterns  310   a  and  310   b . Via layout pattern  378   b  is between conductive feature layout pattern  350   a  and active region layout patterns  310   c  and  310   d . In some embodiments, the set of via layout patterns  378  are on at least the via one (V 1 ) level of layout design  300 A- 300 B or  400 A- 400 B ( FIGS.  4 A- 4 B ). In some embodiments, the V 1  level is between the third layout level and the fourth layout level of layout design  300 A- 300 B or  400 A- 400 B ( FIGS.  4 A- 4 B ). 
     Layout design  300 A further includes via layout patterns  380   a ,  380   b  (collectively referred to as “set of via layout patterns  380 ”). In some embodiments, via layout patterns  380   a ,  380   b  are usable to manufacture via  580   a  or vias similar to via  580   a  of integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). In some embodiments, via layout pattern  380   a  is located where conductive feature layout pattern  340   a  overlaps gate layout patterns  324   a  and  324   c . In some embodiments, via layout pattern  380   b  is located where conductive feature layout pattern  340   b  overlaps gate layout patterns  324   b  and  324   d . Via layout pattern  380   a  is between conductive feature layout pattern  340   a  and gate layout patterns  324   a  and  324   c . Via layout pattern  380   b  is between conductive feature layout pattern  340   b  and gate layout patterns  324   b  and  324   d . In some embodiments, the set of via layout patterns  380  are on at least the via over gate (VG) level of layout design  300 A- 300 B or  400 A- 400 B ( FIGS.  4 A- 4 B ). In some embodiments, the VG level is between the third layout level and the second layout level of layout design  300 A- 300 B or  400 A- 400 B ( FIGS.  4 A- 4 B ). 
     Other quantities or configurations of conductive feature layout patterns  340   a ,  340   b ,  342   a ,  342   b ,  344   a ,  344   b  or  350   a , or via layout patterns  374   a ,  374   b ,  376   a ,  376   b ,  378   a ,  378   b ,  380   a  or  380   b  are within the scope of the present disclosure. 
     In some embodiments, layout design  300 A- 300 B has a non-rectangular shape which results in a smaller standard cell than other designs. In some embodiments, by having a smaller standard cell, layout design  300 A- 300 B can be utilized to manufacture integrated circuits that are smaller than other integrated circuits. 
       FIG.  3 B  is a diagram of a layout design  300 B, in accordance with some embodiments. 
     Layout design  300 B is usable to manufacture integrated circuit  500 A ( FIGS.  5 A- 5 H ). Layout design  300 B is a variation of layout design  300 A of  FIG.  3 A . In comparison with layout design  300 A of  FIG.  3 A , layout design  300 B further includes a first well layout pattern  314  and a second well layout pattern  316 . 
     First well layout pattern  314  extends in the second direction Y, and is located on a fifth layout level. First well layout pattern  314  is useable to manufacture a first well  501  (e.g., at least portions  501   a ,  501   b ) of integrated circuit  500 A ( FIGS.  5 A- 5 H ). In some embodiments, the fifth layout level is different from the first layout level, the second layout level, the third layout level and the fourth layout level. In some embodiments, the fifth layout level corresponds to the well level of layout design  300 A- 300 B or  400 A- 400 B ( FIGS.  4 A- 4 B ). In some embodiments, a portion of the fifth layout level includes the first layout level. First well layout pattern  314  includes layout patterns  354   a ,  354   b  and  354   c.    
     Layout pattern  354   a  extends in the second direction Y and is below active region layout patterns  304   a  and  304   b . Layout pattern  354   a  is adjacent to a side  352   a  of the first portion  302   a  or the second portion  302   b  of layout design  300 B, and corner notches  390   a  and  390   b . Layout pattern  354   a  is useable to manufacture portion  501   a  of first well  501  of integrated circuit  500 A ( FIGS.  5 A- 5 H ). Layout pattern  354   a  has a width W 1  (not labelled) in the first direction X. 
     Layout pattern  354   b  extends in the second direction Y and is below active region layout patterns  310   a ,  310   b ,  310   c  and  310   d . Layout pattern  354   b  is positioned over centerlines  352   b   1  and  352   b   2  of layout design  300 B. In some embodiments, a center of layout pattern  354   b  is aligned with the centerlines  352   b   1  and  352   b   2  of layout design  300 B. Layout pattern  354   b  is useable to manufacture at least portion  501   b  of the first well  501  of integrated circuit  500 A ( FIGS.  5 A- 5 H ). Layout pattern  354   b  has a width W 2  (not labelled) in the first direction X. 
     Layout pattern  354   c  extends in the second direction Y and is below active region layout patterns  304   c  and  304   d . Layout pattern  354   c  is adjacent to a side  352   c  of the third portion  302   c  or the fourth portion  302   d  of layout design  300 B, and corner notches  390   c  and  390   d . Layout pattern  354   c  is useable to manufacture a portion of first well  501  similar to portion  501   a . Layout pattern  354   c  has width W 1  (not labelled) in the first direction X. 
     Second well layout pattern  316  extends in the second direction Y, and is located on the fifth layout level. Second well layout pattern  316  is useable to manufacture a second well  501 ′ (e.g., at least portion  501   c ) of integrated circuit  500 A ( FIGS.  5 A- 5 H ). 
     Second well layout pattern  316  includes layout patterns  356   a  and  356   b.    
     Layout pattern  356   a  extends in the second direction Y and is below active region layout patterns  306   a ,  306   b ,  308   a  and  308   b . Layout pattern  356   a  is between layout patterns  354   a  and  354   b . Layout pattern  356   a  is useable to manufacture portion  501   c  of second well  501 ′ of integrated circuit  500 A ( FIGS.  5 A- 5 H ). Layout pattern  356   a  has a width W 3  (not labelled) in the first direction X. 
     Layout pattern  356   b  extends in the second direction Y and is below active region layout patterns  306   c ,  306   d ,  308   c  and  308   d . Layout pattern  356   b  is between layout patterns  354   b  and  354   c . Layout pattern  356   b  is useable to manufacture a portion of second well  501 ′ similar to portion  501   c  of integrated circuit  500 A ( FIGS.  5 A- 5 H ). Layout pattern  356   b  has width W 3  (not labelled) in the first direction X. 
     In some embodiments, width W 1 , W 2  or W 3  is the same as another width of width W 1 , W 2  or W 3 . In some embodiments, width W 1 , W 2  or W 3  is different from another width of width W 1 , W 2  or W 3 . 
     Other configurations or quantities of first well layout pattern  314  or second well layout pattern  316  are within the scope of the present disclosure. Other configurations or quantities of layout patterns  354   a ,  354   b ,  354   c ,  356   a  or  356   b  are within the scope of the present disclosure. 
       FIG.  4 A  is a diagram of a layout design  400 A, in accordance with some embodiments. Layout design  400 A corresponds to a layout diagram of a portion of memory cell array  200 A- 200 B of  FIGS.  2 A- 2 B . For example, layout design  400 A corresponds to a layout design of one or more memory cells  204   a ,  204   b , . . . ,  204   i  of the first set of memory cells  204  of  FIGS.  2 A- 2 B . 
     Layout design  400 A is similar to layout design  300 A ( FIG.  3 A ). Similar elements have a same reference number increased by 100. 
     Layout design  400 A is usable to manufacture integrated circuit  500 B ( FIGS.  5 A- 5 H ). 
     Layout design  400 A corresponds to a layout design of memory cells  202 [2,4],  202 [2,5],  202 [3,4] and  202 [3,5] of  FIGS.  2 A- 2 B . For example, in some embodiments, the first portion  402   a  corresponds to the layout design of memory cell  202 [2,4] of  FIGS.  2 A- 2 B , the second portion  402   b  corresponds to the layout design of memory cell  202 [3,4] of  FIGS.  2 A- 2 B , the third portion  402   c  corresponds to the layout design of memory cell  202 [2,5] of  FIGS.  2 A- 2 B , and the fourth portion  402   d  corresponds to the layout design of memory cell  202 [3,5] of  FIGS.  2 A- 2 B . First portion  402   a , second portion  402   b , third portion  402   c  and fourth portion  402   d  have corresponding corner notches  490   a ,  490   b ,  490   c  and  490   d  (see  FIG.  4 B ). Corner notches  490   a ,  490   b ,  490   c  and  490   d  are similar to corresponding corner notches  390   a ,  390   b ,  390   c  and  390   d , and similar detailed description is therefore omitted. In some embodiments, layout design  400 A corresponds to a layout design of memory cells  206   a ,  206   b ,  206   c  or  206   d  of the second set of memory cells  206  of  FIGS.  2 A- 2 B . 
     In some embodiments, the first portion  402   a  of layout design  400 A is usable to fabricate memory cell  202 [2,4],  202 [2,N],  202 [M,4] or  202 [M,N] of the first set of memory cells  204  of memory cell array  200 A or  200 B. 
     In some embodiments, the second portion  402   b  of layout design  400 A is usable to fabricate memory cell  202 [1,4],  202 [1,N],  202 [3,4] or  202 [3,N] of the first set of memory cells  204  of memory cell array  200 A or  200 B. 
     In some embodiments, the third portion  402   c  of layout design  400 A is usable to fabricate memory cell  202 [2,1],  202 [2,5],  202 [M,1] or  202 [M,5] of the first set of memory cells  204  of memory cell array  200 A or  200 B. 
     In some embodiments, the fourth portion  402   d  of layout design  400 A is usable to fabricate memory cell  202 [1,1],  202 [1,5],  202 [3,1] or  202 [3,5] of the first set of memory cells  204  of memory cell array  200 A or  200 B. 
     Active region layout patterns  404   a ,  406   a ,  408   a  and  410   a  (collectively referred to as “set of active region layout patterns  412   a ”) are useable to manufacture corresponding active regions  504   a   2 ,  506   a   2 ,  508   a   2 ,  510   e  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). In some embodiments, set of active region layout patterns  412   a  is referred to as OD layout patterns which define source or drain diffusion layout patterns of layout design  400 A- 400 B. For example, in some embodiments, active region layout pattern  404   a  is useable to manufacture the drain and source regions of NMOS transistor N 1   a ′ of  FIGS.  4 A- 4 B , active region layout pattern  406   a  is useable to manufacture the drain and source regions of PMOS transistor P 1   a ′ of  FIGS.  4 A- 4 B , active region layout pattern  408   a  is useable to manufacture the drain and source regions of PMOS transistor P 2   a ′ of  FIGS.  4 A- 4 B , and active region layout pattern  410   a  is useable to manufacture the drain and source regions of NMOS transistor N 2   a ′ and the drain and source regions of PMOS transistor PG 1   a ′ of  FIGS.  4 A- 4 B . 
     In some embodiments, active region layout patterns  404   b ,  406   b ,  408   b  and  410   b  (collectively referred to as “set of active region layout patterns  412   b ”) are useable to manufacture active regions similar to corresponding active regions  504   a   2 ,  506   a   2 ,  508   a   2 , and  510   e  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). In some embodiments, active region layout patterns  404   c ,  406   c ,  408   c  and  410   c  (collectively referred to as “set of active region layout patterns  412   c ”) are useable to manufacture active regions similar to corresponding active regions  504   a   2 ,  506   a   2 ,  508   a   2 , and  510   e  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). In some embodiments, active region layout patterns  404   d ,  406   d ,  408   d  and  410   d  (collectively referred to as “set of active region layout patterns  412   d ”) are useable to manufacture active regions similar to corresponding active regions  504   a   2 ,  506   a   2 ,  508   a   2 , and  510   e  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, active region layout patterns  404   b ,  404   c  and  404   d  are useable to manufacture the drain and source regions of corresponding NMOS transistors N 1   b ′, N 1   c ′ and N 1   d ′, active region layout patterns  406   b ,  406   c  and  406   d  are useable to manufacture the drain and source regions of corresponding PMOS transistors P 1   b ′, P 1   c ′ and P 1   d ′, active region layout patterns  408   b ,  408   c  and  408   d  are useable to manufacture the drain and source regions of corresponding PMOS transistors P 2   b ′, P 2   c ′ and P 2   d ′, active region layout pattern  410   b  is useable to manufacture the drain and source regions of NMOS transistors N 2   b ′ and the drain and source regions of PMOS transistor PG 1   b ′, active region layout pattern  410   c  is useable to manufacture the drain and source regions of NMOS transistors N 2   c ′ and the drain and source regions of PMOS transistor PG 1   c ′, and active region layout pattern  410   d  is useable to manufacture the drain and source regions of NMOS transistors N 2   d ′ and the drain and source regions of PMOS transistor PG 1   d′.    
     In some embodiments, gate layout patterns  420   a ,  422   a  and  424   a  (collectively referred to as “set of gate layout patterns  426   a ”) are usable to manufacture corresponding gate structures  520   a ,  522   a  and  524   a  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). In some embodiments, gate layout pattern  420   a  is useable to manufacture gate regions of NMOS transistor N 1   a ′ and PMOS transistor P 1   a ′, gate layout pattern  422   a  is useable to manufacture gate regions of NMOS transistor N 2   a ′ and PMOS transistor P 2   a ′, and gate layout pattern  424   a  is useable to manufacture a gate region of PMOS transistor PG 1   a′.    
     In some embodiments, gate layout patterns  420   b ,  422   b  and  424   b  (collectively referred to as “set of gate layout patterns  426   b ”) are usable to manufacture gate structures similar to corresponding gate structures  520   a ,  522   a  and  524   a  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). In some embodiments, gate layout patterns  420   c ,  422   c  and  424   c  (collectively referred to as “set of gate layout patterns  426   c ”) are usable to manufacture gate structures similar to corresponding gate structures  520   a ,  522   a  and  524   a  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). In some embodiments, gate layout patterns  420   d ,  422   d  and  424   d  (collectively referred to as “set of gate layout patterns  426   d ”) are usable to manufacture gate structures similar to corresponding gate structures  520   a ,  522   a  and  524   a  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, gate layout pattern  420   b  is useable to manufacture gate regions of PMOS transistor P 1   b ′ and NMOS transistor N 1   b ′, gate layout pattern  422   b  is useable to manufacture gate regions of NMOS transistor N 2   b ′ and PMOS transistor P 2   b ′, gate layout pattern  420   c  is useable to manufacture gate regions of PMOS transistor P 1   c ′ and NMOS transistor N 1   c ′, gate layout pattern  422   c  is useable to manufacture gate regions of NMOS transistor N 2   c ′ and PMOS transistor P 2   c ′, gate layout pattern  420   d  is useable to manufacture gate regions of PMOS transistor P 1   d ′ and NMOS transistor N 1   d ′, gate layout pattern  422   d  is useable to manufacture gate regions of NMOS transistor N 2   d ′ and PMOS transistor P 2   d ′, and gate layout patterns  424   b ,  424   c  and  424   d  are useable to manufacture corresponding gate regions of PMOS transistors PG 1   b ′, PG 1   c ′ and PG 1   d′.    
     In some embodiments, conductive feature layout patterns  430   a ,  432   a ,  434   a  and  436   a  (collectively referred to as “set of conductive feature layout patterns  438   a ”) are usable to manufacture corresponding conductive structures  530   a ,  532   a ,  534   b  and  536   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). In some embodiments, conductive feature layout patterns  430   b ,  432   b ,  434   b  and  436   b  (collectively referred to as “set of conductive feature layout patterns  438   b ”) are usable to manufacture conductive structures similar to corresponding conductive structures  530   a ,  532   a ,  534   b  and  536   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). In some embodiments, conductive feature layout patterns  430   c ,  432   c ,  434   c  and  436   c  (collectively referred to as “set of conductive feature layout patterns  438   c ”) are usable to manufacture conductive structures similar to corresponding conductive structures  530   a ,  532   a ,  534   b  and  536   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). In some embodiments, conductive feature layout patterns  430   d ,  432   d ,  434   d  and  436   d  (collectively referred to as “set of conductive feature layout patterns  438   d ”) are usable to manufacture conductive structures similar to corresponding conductive structures  530   a ,  532   a ,  534   b  and  536   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, via layout patterns  460   a ,  462   a ,  464   a ,  466   a ,  468   a ,  470   a  (collectively referred to as “set of via layout patterns  458   a ”) are usable to manufacture corresponding vias  560   a ,  562   a ,  564   a ,  566   b ,  568   b ,  570   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). In some embodiments, via layout patterns  460   b ,  462   b ,  464   b ,  466   b ,  468   b ,  470   b  (collectively referred to as “set of via layout patterns  458   b ”) are usable to manufacture vias similar to corresponding vias  560   a ,  562   a ,  564   a ,  566   b ,  568   b ,  570   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). In some embodiments, via layout patterns  460   c ,  462   c ,  464   c ,  466   c ,  468   c ,  470   c  (collectively referred to as “set of via layout patterns  458   c ”) are usable to manufacture vias similar to corresponding vias  560   a ,  562   a ,  564   a ,  566   b ,  568   b ,  570   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). In some embodiments, via layout patterns  460   d ,  462   d ,  464   d ,  466   d ,  468   d ,  470   d  (collectively referred to as “set of via layout patterns  458   d ”) are usable to manufacture vias similar to corresponding vias  560   a ,  562   a ,  564   a ,  566   b ,  568   b ,  570   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, conductive feature layout patterns  440   a  and  440   b  (collectively referred to as “set of conductive feature layout patterns  440 ”) are usable to manufacture conductive structure  540   a  or similar conductive structures of integrated circuit  500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, conductive feature layout patterns  442   a  and  442   b  (collectively referred to as “set of conductive feature layout patterns  442 ”) are usable to manufacture corresponding conductive structures  542   a  and  542   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, conductive feature layout patterns  444   a  and  444   b  (collectively referred to as “set of conductive feature layout patterns  444 ”) are usable to manufacture conductive structures similar to corresponding conductive structures  542   a  and  542   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, conductive feature layout pattern  450   a  (collectively referred to as “set of conductive feature layout patterns  450 ”) is usable to manufacture conductive structure  550   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, via layout patterns  474   a ,  474   b  (collectively referred to as “set of via layout patterns  474 ”) are usable to manufacture corresponding vias  574   a ,  574   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, via layout patterns  476   a ,  476   b  (collectively referred to as “set of via layout patterns  476 ”) are usable to manufacture vias similar to corresponding vias  574   a ,  574   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, via layout patterns  478   a ,  478   b  (collectively referred to as “set of via layout patterns  478 ”) are usable to manufacture via  578   b  or vias similar to  578   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, via layout patterns  480   a ,  480   b  (collectively referred to as “set of via layout patterns  480 ”) are usable to manufacture via  580   a  or vias similar to via  580   a  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). 
     In some embodiments, layout design  400 A- 400 B has a non-rectangular shape which results in a smaller standard cell than other designs. In some embodiments, by having a smaller standard cell, layout design  400 A- 400 B can be utilized to manufacture integrated circuits that are smaller than other integrated circuits. 
       FIG.  4 B  is a diagram of a layout design  400 B, in accordance with some embodiments. 
     Layout design  400 B is usable to manufacture integrated circuit  500 B ( FIGS.  5 A- 5 H ). Layout design  400 B is a variation of layout design  400 A of  FIG.  4 A . In comparison with layout design  400 A of  FIG.  4 A , layout design  400 B further includes a first well layout pattern  416  and a second well layout pattern  414 . 
     First well layout pattern  416  extends in the second direction Y, and is located on the fifth layout level. First well layout pattern  416  is useable to manufacture a first well  502  (e.g., at least portions  502   a ,  502   b ) of integrated circuit  500 B ( FIGS.  5 A- 5 H ). 
     First well layout pattern  416  includes layout patterns  456   a ,  456   b ,  456   c  and  456   d.    
     Layout pattern  456   a  extends in the second direction Y and is below active region layout patterns  404   a  and  404   b . Layout pattern  456   a  is adjacent to a side  452   a  of the first portion  402   a  or the second portion  402   b  of layout design  400 B. Layout pattern  456   a  is useable to manufacture portion  502   a  of first well  502  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). Layout pattern  456   a  has width W 1  (not labelled) in the first direction X. 
     Layout pattern  456   b  extends in the second direction Y and is below active region layout patterns  404   c  and  404   d . Layout pattern  456   b  is adjacent to a side  452   c  of the third portion  402   c  or the fourth portion  402   d  of layout design  400 B. Layout pattern  456   b  is useable to manufacture a portion of first well  502  similar to portion  502   a  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). Layout pattern  456   b  has width W 1  (not labelled) in the first direction X. 
     Layout pattern  456   c  extends in the first direction X and is below a portion of active region layout patterns  410   a  and  410   c . In some embodiments, a side of layout pattern  456   c  is aligned with a first side of layout pattern  454   b  along line  452   d   1  in the first direction X. Layout pattern  456   c  is useable to manufacture portion  502   b  of first well  502  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). Layout pattern  456   c  has width W 2  (not labelled) in the first direction X. 
     Layout pattern  456   d  extends in the first direction X and is below a portion of active region layout patterns  410   b  and  410   d . In some embodiments, a side of layout pattern  456   d  is aligned with a second side of layout pattern  454   b  along line  452   d   2  in the first direction X. Layout pattern  456   d  is useable to manufacture a portion of first well  502  similar to portion  502   b  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). Layout pattern  456   d  has width W 2  (not labelled) in the first direction X. 
     Second well layout pattern  414  extends in the second direction Y, and is located on the fifth layout level. Second well layout pattern  414  is useable to manufacture a second well  502 ′ (e.g., at least portions  502   c ,  502   d ) of integrated circuit  500 B ( FIGS.  5 A- 5 H ). Second well layout pattern  414  includes layout patterns  454   a ,  454   b  and  454   c.    
     Layout pattern  454   a  extends in the second direction Y and is below active region layout patterns  406   a ,  406   b ,  408   a  and  408   b . Layout pattern  454   a  is useable to manufacture portion  502   c  of second well  502 ′ of integrated circuit  500 B ( FIGS.  5 A- 5 H ). Layout pattern  454   a  has width W 3  (not labelled) in the first direction X. 
     Layout pattern  454   b  extends in the first direction X and is below a portion of active region layout patterns  410   a ,  410   b ,  410   c  and  410   d . Layout pattern  454   b  is positioned over center lines  452   b   1 ,  452   b   2  of layout design  400 B. In some embodiments, a center of layout pattern  454   b  is aligned with center lines  452   b   1  and  452   b   2  of layout design  400 B. In some embodiments, the first side of layout pattern  454   b  is aligned with line  452   d   1  in the first direction X. In some embodiments, the second side of layout pattern  454   b  is aligned with line  452   d   2  in the first direction X. Layout pattern  454   b  is useable to manufacture at least portion  502   d  of the second well  502 ′ of integrated circuit  500 B ( FIGS.  5 A- 5 H ). In some embodiments, layout pattern  454   b  is useable to manufacture portions similar to portion  502   d  of the second well  502 ′ of integrated circuit  500 B ( FIGS.  5 A- 5 H ). Layout pattern  454   b  has width W 2  (not labelled) in the first direction X. 
     Layout pattern  454   c  extends in the second direction Y and is below active region layout patterns  406   c ,  406   d ,  408   c  and  408   d . Layout pattern  454   c  is useable to manufacture a portion of second well  502 ′ similar to portion  502   c  of integrated circuit  500 B ( FIGS.  5 A- 5 H ). Layout pattern  454   c  has width W 3  (not labelled) in the first direction X. 
     In some embodiments, layout patterns  454   a ,  454   b  and  454   c  are part of a same continuous layout pattern (e.g., second well layout pattern  414 ). 
     Layout pattern  454   a  is between layout patterns  456   a  and each of layout patterns  454   b ,  456   c  and  456   d . Layout pattern  454   c  is between layout patterns  456   b  and each of layout patterns  454   b ,  456   c  and  456   d . Layout pattern  454   b  is between layout patterns  456   c  and  456   d . Layout pattern  454   b  is between layout patterns  454   a  and  454   c.    
     In some embodiments, width W 1 , W 2  or W 3  is the same as another width of width W 1 , W 2  or W 3 . In some embodiments, width W 1 , W 2  or W 3  is different from another width of width W 1 , W 2  or W 3 . 
     Other configurations or quantities of first well layout pattern  416  or second well layout pattern  414  are within the scope of the present disclosure. Other configurations or quantities of layout patterns  454   a ,  454   b ,  454   c ,  456   a ,  456   b ,  456   c  or  456   d  are within the scope of the present disclosure. 
       FIGS.  5 A,  5 B,  5 C,  5 D,  5 E,  5 F,  5 G and  5 H  are diagrams of an integrated circuit  500 A or  500 B, in accordance with some embodiments. 
       FIG.  5 A  is a cross-sectional view of an integrated circuit  500 A or  500 B corresponding to layout design  300 B or  400 B as intersected by plane A-A′, respectively. 
       FIG.  5 B  is a cross-sectional view of an integrated circuit  500 A or  500 B corresponding to layout design  300 B or  400 B as intersected by plane B-B′, respectively. 
       FIG.  5 C  is a cross-sectional view of an integrated circuit  500 A or  500 B corresponding to layout design  300 B or  400 B as intersected by plane C-C′, respectively. 
       FIG.  5 D  is a cross-sectional view of an integrated circuit  500 A corresponding to layout design  300 B as intersected by plane D-D′, and  FIG.  5 E  is a cross-sectional view of an integrated circuit  500 B corresponding to layout design  400 B as intersected by plane E-E′. 
       FIG.  5 F  is a cross-sectional view of an integrated circuit  500 A or  500 B corresponding to layout design  300 B or  400 B as intersected by plane F-F′, respectively. 
       FIG.  5 G  is a cross-sectional view of an integrated circuit  500 A corresponding to layout design  300 B as intersected by plane G-G′, and  FIG.  5 H  is a cross-sectional view of an integrated circuit  500 A corresponding to layout design  400 B as intersected by plane H-H′. 
     Integrated circuit  500 A is manufactured by the first portion  302   a  of layout design  300 B, and integrated circuit  500 B is manufactured by the first portion  402   a  of layout design  400 B. In some embodiments, second portion  302   b , third portion  302   c  and fourth portion  302   d  of layout design  300 B are usable to manufacture an integrated circuit similar to integrated circuit  500 A. In some embodiments, second portion  402   b , third portion  402   c  and fourth portion  402   d  of layout design  400 B are usable to manufacture an integrated circuit similar to integrated circuit  500 B. 
     Structural relationships including alignment, lengths and widths, as well as configurations of integrated circuit  500 A- 500 B are similar to the structural relationships and configurations of layout design  300 A- 300 B of  FIGS.  3 A- 3 B  and layout design  400 A- 400 B of  FIGS.  4 A- 4 B , and will not be described in  FIGS.  5 A- 5 H  for brevity. 
     For brevity, integrated circuits  500 A and  500 B are described below as they pertain to  FIGS.  5 A- 5 H . For brevity, elements with the same reference numeral in integrated circuits  500 A and  500 B are described with reference to either integrated circuit  500 A or  500 B, and similar detailed description is omitted. 
     Integrated circuit  500 B is a variation of integrated circuit  500 A. In comparison with integrated circuit  500 A, integrated circuit  500 B does not include first well  501  and second well  501 ′. In comparison with integrated circuit  500 A, first well  502  of integrated circuit  500 B replaces first well  501 , and second well  502 ′ of integrated circuit  500 B replaces second well  501 . 
     Integrated circuit  500 A includes a first well  501  and a second well  501 ′. Each of the first well  501  and the second well  501 ′ is located on at least the first level of integrated circuit  500 A, and extends in the second direction Y. 
     The first well  501  of integrated circuit  500 A includes dopants of a first type. The second well  501 ′ of integrated circuit  500 A includes dopants of a second type different from the first type. In some embodiments, the first type is an N-type dopant, the second type is a P-type dopant, and the first well  501  of integrated circuit  500 A is an N-well, and the second well  501 ′ of integrated circuit  500 A is a P-well. In some embodiments, the first type is a P-type dopant, the second type is an N-type dopant, and the first well  501  of integrated circuit  500 A is a P-well, and the second well  501 ′ of integrated circuit  500 A is an N-well. 
     The first well  501  of integrated circuit  500 A includes a first portion  501   a  and a second portion  501   b.    
     The first portion  501   a  of the first well  501  extends in the second direction Y and is adjacent to a first side  590   a  of integrated circuit  500 A. In some embodiments, the first side  590   a  of integrated circuit  500 A corresponds to line  352   a  of layout design  300 B. The first portion  501   a  of the first well  501  is located on at least the first level of integrated circuit  500 A. 
     The second portion  501   b  of the first well  501  extends in the second direction Y and is adjacent to a second side  590   b  of integrated circuit  500 A. In some embodiments, the second side  590   b  of integrated circuit  500 A corresponds to line  352   b   1  of layout design  300 B. The second portion of the first well  501  is located on at least the first level of integrated circuit  500 A. 
     The second well  501 ′ of integrated circuit  500 A includes a portion  501   c . The second well  501 ′ is between the first portion  501   a  of the first well  501  and the second portion  501   b  of the first well  501 . 
     Portion  501   c  of the second well  501 ′ extends in the second direction Y and is between the first portion  501   a  of the first well  501  and the second portion  501   b  of the first well  501 . Portion  501   c  of the second well  501 ′ is located on at least the first level of integrated circuit  500 A. Other quantities or configurations of the first well  501  or the second well  501 ′ are within the scope of the present disclosure. 
     Integrated circuit  500 A or  500 B includes a set of active regions  504  extending in the second direction Y. The set of active regions  504  is located on a first level of integrated circuit  500 A or  500 B. 
     The set of active regions  504  includes one or more of active regions  504   a   1 ,  506   a   1 ,  508   a   1  or  510   a   1 . Each of the active regions  504   a   1 ,  506   a   1 ,  508   a   1 ,  510   a   1  of the set of active regions  504  is separated from an adjacent active region of the set of active regions  504  in the first direction X by a first pitch (not labelled). 
     Active region  504   a   1  is adjacent to the first side  590   a  of integrated circuit  500 A. Active region  510   a   1  is adjacent to the second side  590   b  of integrated circuit  500 A. The second side  590   b  of integrated circuit  500 A is opposite from the first side  590   a  of integrated circuit  500 A. 
     Active region  504   a   1  of the set of active regions  504  is embedded in the first portion  501   a  of the first well  501  of integrated circuit  500 A. 
     Active region  510   a   1  of the set of active regions  504  is embedded in the second portion  501   b  of the first well  501  of integrated circuit  500 A. 
     Active region  506   a   1  or  508   a   1  of the set of active regions  504  is embedded in portion  501   c  of the second well  501 ′ of integrated circuit  500 A. 
     Active regions  506   a   1  and  508   a   1  includes dopants of the first type. Active regions  504   a   1  and  510   a   1  includes dopants of the second type. In some embodiments, the first type is an N-type dopant, the second type is a P-type dopant, and therefore active regions  504   a   1  and  510   a   1  are each P-type active regions embedded in first well  501  (which is an N-well), and active regions  506   a   1  and  508   a   1  are each N-type active regions embedded in second well  501 ′ (which is a P-well). In some embodiments, the first type is a P-type dopant, the second type is an N-type dopant, and therefore active regions  504   a   1  and  510   a   1  are each N-type active regions embedded in first well  501  (which is a P-well), and active regions  506   a   1  and  508   a   1  are each P-type active regions embedded in second well  501 ′ (which is an N-well). 
     In some embodiments, a length of at least one of active region  504   a   1 ,  506   a   1 ,  508   a   1  or  510   a   1  in the second direction Y is different from a length of another of active region  504   a   1 ,  506   a   1 ,  508   a   1  or  510   a   1  in the second direction Y. In some embodiments, a length of at least one of active region  504   a   1 ,  506   a   1 ,  508   a   1  or  510   a   1  in the second direction Y is the same as a length of another of active region  504   a   1 ,  506   a   1 ,  508   a   1  or  510   a   1  in the second direction Y. Other quantities or configurations of the set of active regions  504  are within the scope of the present disclosure. 
     Integrated circuit  500 A or  500 B includes a set of gates  527  extending in the first direction X. The set of gates  527  overlaps the set of active regions  504  of integrated circuit  500 A or the set of active regions  505  of integrated circuit  500 B. The set of gates  527  is located on a second level of integrated circuit  500 A or  500 B. The second level is different from the first level of integrated circuit  500 A or  500 B. In some embodiments, the second level of integrated circuit  500 A or  500 B is referred to as the POLY level. 
     The set of gates  527  includes one or more of gate structures  520   a ,  522   a  or  524   a . Each of gate structures  520   a  and  524   a  are separated from gate structure  522   a  in the second direction Y by a gate pitch (not labelled). Gate structures  520   a  and  524   a  are separated from each other in the first direction X. Other quantities or configurations of the set of gates  527  are within the scope of the present disclosure. 
     Integrated circuit  500 A or  500 B includes conductive structures  504   b ,  504   c ,  504   d ,  504   e ,  504   f ,  510   b ,  510   c ,  510   d ,  510   e ,  510   f ,  516   e ,  516   f  and  520   f  (collectively referred to as a “set of contacts  521 ”). 
     Set of contacts  521  extends in the first direction X or the second direction Y. The set of contacts  521  is over the set of active regions  504  of integrated circuit  500 A or the set of active regions  505  of integrated circuit  500 B. The set of contacts  521  is located on the second level of integrated circuit  500 A or  500 B. In some embodiments, the second level of integrated circuit  500 A or  500 B is referred to as the metal diffusion (MD) level. 
     The set of contacts  521  electrically couples the set of active regions  504  of integrated circuit  500 A or the set of active regions  505  of integrated circuit  500 B to upper levels (e.g., M 0 , M 1  or M 2 ) of corresponding integrated circuit  500 A or  500 B. Conductive structures  504   b ,  510   b  electrically couple corresponding vias  506   b ,  512   b  to active region  504   a   1  or  504   a   2  (part of integrated circuit  500 B). Conductive structures  504   c ,  510   c  electrically couple corresponding vias  506   c ,  512   c  to active region  506   a   1  or  506   a   2  (part of integrated circuit  500 B). Conductive structures  504   d ,  510   d  electrically couple corresponding vias  506   d ,  512   d  to active region  508   a   1  or  508   a   2  (part of integrated circuit  500 B). Conductive structures  504   e ,  510   e ,  516   e  electrically couple corresponding vias  506   e ,  512   e ,  518   e  to active region  510   a   1 . Conductive structures  504   f ,  510   f  electrically couple corresponding vias  506   f ,  512   f  to active region  510   b . Conductive structures  516   f ,  520   f  electrically couple corresponding vias  518   f ,  522   f  to active region  510   c . Other quantities or configurations of the set of contacts  521  are within the scope of the present disclosure. 
     Integrated circuit  500 A or  500 B includes conductive structures  508   b ,  508   c ,  508   d ,  508   e ,  508   f ,  514   b ,  514   e ,  514   f ,  516   c ,  516   d ,  520   e ,  524   f  (collectively referred to as a “set of conductive structures  529 ”). Set of conductive structures  529  extends in the first direction X or the second direction Y. The set of conductive structures  529  is over the set of active regions  504  of integrated circuit  500 A or the set of active regions  505  of integrated circuit  500 B. The set of conductive structures  529  is over at least the set of contacts  521  or the set of gates  527 . The set of conductive structures  529  is located on a third level of integrated circuit  500 A or  500 B. The third level of integrated circuit  500 A or  500 B is different from the first level of integrated circuit  500 A or  500 B and the second level of integrated circuit  500 A or  500 B. In some embodiments, the third level of integrated circuit  500 A or  500 B is referred to as the metal zero (M 0 ) level. 
     The set of conductive structures  529  electrically couples the set of active regions  504  of integrated circuit  500 A or the set of active regions  505  of integrated circuit  500 B to upper levels (e.g., M 1  or M 2 ) of corresponding integrated circuit  500 A or  500 B. In some embodiments, the set of conductive structures  529  electrically couples the set of gates  527  to upper levels (e.g., M 1  or M 2 ) of integrated circuit  500 A or  500 B. Other quantities or configurations of the set of conductive structures  529  are within the scope of the present disclosure. 
     Integrated circuit  500 A or  500 B includes vias  504   g ,  506   b ,  506   c ,  506   d ,  506   e ,  506   f ,  512   b ,  512   c ,  512   d ,  512   e ,  512   f ,  514   c ,  514   d ,  518   e ,  518   f  and  522   f  (collectively referred to as a “set of vias  523 ”) between the set of conductive structures  529  and the set of active regions  504  of integrated circuit  500 A or the set of active regions  505  of integrated circuit  500 B. The set of vias  523  electrically couple the set of conductive structures  529  to the set of active regions  504  of integrated circuit  500 A or the set of active regions  505  of integrated circuit  500 B. In some embodiments, one or more vias of the set of vias  523  is located where one or more conductive structures of the set of conductive structures  529  is over one or more active regions of the set of active regions  504  of integrated circuit  500 A or one or more active regions of the set of active regions  505  of integrated circuit  500 B. 
     Vias  506   b ,  512   b  electrically couple corresponding conductive structures  508   b ,  514   b  to corresponding conductive structures  504   b ,  510   b . Vias  506   c ,  512   c  electrically couple corresponding conductive structures  508   c ,  516   c  to corresponding conductive structures  504   c ,  510   c . Vias  506   d ,  512   d  electrically couple corresponding conductive structures  508   d ,  516   d  to corresponding conductive structures  504   d ,  510   d . Vias  506   e ,  512   e ,  518   e  electrically couple corresponding conductive structures  508   e ,  514   e ,  520   e  to corresponding conductive structures  504   e ,  510   e ,  516   e . Vias  506   f ,  522   f  electrically couple corresponding conductive structures  508   f ,  524   f  to corresponding conductive structures  504   f ,  520   f . Vias  512   f ,  518   f  electrically couple conductive structure  514   f  to corresponding conductive structures  510   f ,  516   f.    
     Each of vias  514   c ,  514   d ,  504   g  is above corresponding gate structures  522   a ,  520   a ,  524   a . Vias  514   c ,  514   d ,  504   g  electrically couple corresponding conductive structures  516   c ,  516   d ,  506   g  to corresponding gate structures  522   a ,  520   a ,  524   a . Vias  514   c ,  514   d ,  504   g  are above corresponding gate structures  522   a ,  520   a ,  524   a . In some embodiments, the set of vias  523  is between the first set of conductive structures  538  and the set of gates  527 . Via  504   g  of the set of vias  523  is located where conductive structure  540   a  of the first set of conductive structures  538  is over gate structure  524   a  of the set of gates  527 . 
     Set of vias  523  is in the via over diffusion (VD) level or the via over gate (VG) level of integrated circuit  500 A or  500 B. The VG or VD level of integrated circuit  500 A or  500 B is between the second level and the third level. In some embodiments, vias  514   c ,  514   d ,  504   g  are in the VG level of integrated circuit  500 A or  500 B. In some embodiments, vias  506   b ,  506   c ,  506   d ,  506   e ,  506   f ,  512   b ,  512   c ,  512   d ,  512   e ,  512   f ,  518   e ,  518   f  and  522   f  are in the VD level of integrated circuit  500 A or  500 B. Other quantities or configurations of the set of vias  523  are within the scope of the present disclosure. 
     Integrated circuit  500 A or  500 B includes conductive structures  524   e ,  528   f ,  530   a ,  532   a ,  534   a ,  534   b ,  536   a ,  536   b ,  540   a ,  542   a  and  542   b  (collectively referred to as a “first set of conductive structures  538 ”). The first set of conductive structures  538  extends in the first direction X. Each conductive structure of the first set of conductive structures  538  is separated from an adjacent conductive structure of the first set of conductive structures  538  feature in at least the first direction X or the second direction Y. The first set of conductive structures  538  is over at least the set of active regions  504  of integrated circuit  500 A, the set of active regions  505  of integrated circuit  500 B, the set of gates  527 , or the set of contacts  521 . The first set of conductive structures  538  is located on a fourth level of integrated circuit  500 A or  500 B. The fourth level of integrated circuit  500 A or  500 B is different from the first level of integrated circuit  500 A or  500 B, the second level of integrated circuit  500 A or  500 B and the third level of integrated circuit  500 A or  500 B. In some embodiments, the fourth level of integrated circuit  500 A or  500 B is referred to as the metal one (M 1 ) level. 
     In some embodiments, conductive structure  540   a  corresponds to the word line WL 1  of memory cell  100  of  FIG.  1    or word lines WL[1], . . . , WL[2M] of memory cell array  200 A- 200 B of  FIGS.  2 A- 2 B . 
     The first set of conductive structures  538  is electrically coupled to the set of active regions  504  of integrated circuit  500 A or the set of active regions  505  of integrated circuit  500 B. In some embodiments, the first set of conductive structures  538  is electrically coupled to the set of gates  527 . Other quantities or configurations of the first set of conductive structures  538  are within the scope of the present disclosure. 
     Integrated circuit  500 A or  500 B includes vias  522   e ,  526   f ,  560   a ,  562   a ,  564   a ,  566   a ,  566   b ,  568   a ,  568   b ,  570   a ,  570   b ,  574   a ,  574   b  and  580   a  (collectively referred to as a “first set of vias  572 ”) between the first set of conductive structures  538  and the set of active regions  504  of integrated circuit  500 A or the set of active regions  505  of integrated circuit  500 B. The first set of vias  572  electrically couple the first set of conductive structures  538  to the set of active regions  504  of integrated circuit  500 A or the set of active regions  505  of integrated circuit  500 B. In some embodiments, one or more vias of the first set of vias  572  is located where one or more conductive structures of the first set of conductive structures  538  overlaps one or more active regions of the set of active regions  504  of integrated circuit  500 A or one or more active regions of the set of active regions  505  of integrated circuit  500 B. 
     Vias  560   a ,  574   a  electrically couple corresponding conductive structures  530   a ,  542   a  to corresponding conductive structures  508   b ,  514   b . Vias  562   a ,  574   b  electrically couple corresponding conductive structures  530   a ,  542   b  to corresponding conductive structures  516   c ,  508   c . Via  564   a  electrically couples conductive structure  532   a  to conductive structure  508   d . Vias  566   a ,  566   b  electrically couple corresponding conductive structures  534   a ,  534   b  to conductive structures  516   d . Vias  568   a ,  570   a ,  522   e  electrically couple corresponding conductive structures  536   a ,  534   a ,  524   e  to corresponding conductive structures  508   e ,  514   e ,  520   e . Vias  568   b ,  570   b ,  526   f  electrically couple corresponding conductive structures  536   b ,  534   b ,  528   f  to corresponding conductive structures  508   f ,  514   f ,  524   f . Via  580   a  electrically couples conductive structure  540   a  to conductive structure  506   g.    
     First set of vias  572  is in the via zero (V 0 ) level of integrated circuit  500 A or  500 B. The V 0  level of integrated circuit  500 A or  500 B is between the third level and the fourth level. In some embodiments, the V 0  level of integrated circuit  500 A or  500 B is between the M 1  level and the M 0  level. Other quantities or configurations of the first set of vias  572  are within the scope of the present disclosure. 
     Integrated circuit  500 A or  500 B includes conductive structures  550   a  and  550   b  (collectively referred to as a “second set of conductive structures  552 ”). The second set of conductive structures  552  extends in the first direction X. Each conductive structure of the second set of conductive structures  552  is separated from an adjacent conductive structure of the second set of conductive structures  552  in at least the first direction X or the second direction Y. In some embodiments, the second set of conductive structures  552  is over one or more of the set of active regions  504  of integrated circuit  500 A, the set of active regions  505  of integrated circuit  500 B or the set of contacts  521 . 
     The second set of conductive structures  552  is located on a fifth level of integrated circuit  500 A or  500 B. The fifth level of integrated circuit  500 A or  500 B is different from the first level of integrated circuit  500 A or  500 B, the second level of integrated circuit  500 A or  500 B, the third level of integrated circuit  500 A or  500 B and the fourth level of integrated circuit  500 A or  500 B. In some embodiments, the fifth level of integrated circuit  500 A or  500 B is referred to as the metal two (M 2 ) level. 
     In some embodiments, the second set of conductive structure  552  overlaps the set of active regions  504  of integrated circuit  500 A or the set of active regions  505  of integrated circuit  500 B. Conductive structure  550   a  overlaps active region  510   a  of the set of active regions  504  of integrated circuit  500 A and the second side  590   b  of integrated circuit  500 A. Conductive structure  550   b  overlaps active region  510   c  of the set of active regions  505  of integrated circuit  500 B and the second side  590   b  of integrated circuit  500 B. In some embodiments, conductive structure  550   a  or  550   b  corresponds to the bit line BL 1  of memory cell  100  of  FIG.  1    or bit lines BL[1], . . . , BL[2N] of memory cell array  200 A- 200 B of  FIGS.  2 A- 2 B . 
     In some embodiments, the second set of conductive structures  552  is electrically coupled to the set of active regions  504  of integrated circuit  500 A or the set of active regions  505  of integrated circuit  500 B. Conductive structure  550   a  is electrically coupled to active region  510   a  of integrated circuit  500 A. Conductive structure  550   b  is electrically coupled to active region  510   c  of integrated circuit  500 B. Other quantities or configurations of the second set of conductive structures  552  are within the scope of the present disclosure. 
     Integrated circuit  500 A or  500 B includes vias  578   a  and  578   b  (collectively referred to as a “set of vias  576 ”) between the second set of conductive structures  552  and the first set of conductive structures  538 . The set of vias  576  electrically couple the second set of conductive structures  552  to the first set of conductive structures  538 . Vias  578   a ,  578   b  electrically couple corresponding conductive structures  550   a ,  550   b  to corresponding conductive structures  524   e ,  528   f . In some embodiments, the set of vias  576  electrically couple the second set of conductive structures  552  to the set of active regions  504  of integrated circuit  500 A or the set of active regions  505  of integrated circuit  500 B. 
     In some embodiments, one or more vias of the set of vias  576  is located where one or more conductive structures of the second set of conductive structures  538  overlaps one or more active regions of the set of active regions  504  of integrated circuit  500 A or one or more active regions of the set of active regions  505  of integrated circuit  500 B. 
     First set of vias  572  is in the via one (V 1 ) level of integrated circuit  500 A or  500 B. The V 1  level of integrated circuit  500 A or  500 B is between the fourth level and the fifth level. In some embodiments, the V 1  level of integrated circuit  500 A or  500 B is between the M 2  level and the M 1  level. Other quantities or configurations of the set of vias  572  are within the scope of the present disclosure. 
     Integrated circuit  500 B is a variation of integrated circuit  500 A. In comparison with integrated circuit  500 A, a first well  502  of integrated circuit  500 B replaces first well  501 , a second well  502 ′ of integrated circuit  500 B replaces second well  501 , and a set of active regions  505  of integrated circuit  500 B replaces the set of active regions  504 . 
     Integrated circuit  500 B includes first well  502  and second well  502 ′. Each of the first well  502  and the second well  502 ′ is located on at least the first level of integrated circuit  500 B, and extends in at least the second direction Y. 
     The first well  502  of integrated circuit  500 B includes dopants of the second type. The second well  502 ′ of integrated circuit  500 B includes dopants of the first type. In some embodiments, the first type is an N-type dopant, the second type is a P-type dopant, and the first well  502  of integrated circuit  500 B is a P-well, and the second well  502 ′ of integrated circuit  500 B is an N-well. In some embodiments, the first type is a P-type dopant, the second type is an N-type dopant, and the first well  502  of integrated circuit  500 B is an N-well, and the second well  502 ′ of integrated circuit  500 B is a P-well. 
     The first well  502  of integrated circuit  500 B includes a first portion  502   a  and a second portion  502   b.    
     The first portion  502   a  of the first well  502  extends in the second direction Y and is adjacent to the first side  590   a  of integrated circuit  500 B. In some embodiments, the first side  590   a  of integrated circuit  500 B corresponds to line  352   a  of layout design  400 B. The first portion  502   a  of the first well  502  is located on at least the first level of integrated circuit  500 B. 
     The second portion  502   b  of the first well  502  extends in the second direction Y and is adjacent to the second side  590   b  of integrated circuit  500 B. In some embodiments, the second side  590   b  of integrated circuit  500 B corresponds to line  352   b   1  of layout design  400 B. The second portion of the first well  502  is located on at least the first level of integrated circuit  500 B. Other quantities or configurations of the first well  502 , the first portion  502   a  of the first well  502  or the second portion  502   b  of the first well  502  are within the scope of the present disclosure. 
     The second well  502 ′ of integrated circuit  500 B includes a first portion  502   c  and a second portion  502   d.    
     The first portion  502   c  of the second well  502 ′ extends in the second direction Y and is adjacent to the first portion  502   a  of the first well  502 . The first portion  502   c  of the second well  502 ′ is located on at least the first level of integrated circuit  500 B. 
     The second portion  502   d  of the second well  502 ′ extends in at least the first direction X or the second direction Y. The second portion  502   d  of the second well  502 ′ is adjacent to each of the second side  590   b  of integrated circuit  500 B, the second portion  502   b  of the first well  502  and the first portion  502   c  of the second well  502 ′. The second portion  502   d  of the second well  502 ′ is located on at least the first level of integrated circuit  500 B. 
     The first portion  502   c  of the second well  502 ′ is between the first portion  502   a  of the first well  502  and each of the second portion  502   b  of the first well  502  and the second portion  502   d  of the second well  502 ′. Other quantities or configurations of the second well  502 ′, the first portion  502   c  of the second well  502 ′ or the second portion  502   d  of the second well  502 ′ are within the scope of the present disclosure. 
     Integrated circuit  500 B includes a set of active regions  505  extending in the second direction Y. The set of active regions  505  is located on the first level of integrated circuit  500 B. 
     The set of active regions  505  includes one or more of active regions  504   a   2 ,  506   a   2 ,  508   a   2  or  510   e . Each of the active regions  504   a   2 ,  506   a   2 ,  508   a   2  or  510   e  of the set of active regions  505  is separated from an adjacent active region of the set of active regions  505  in the first direction X by the first pitch (not labelled). 
     Active region  510   e  includes an active region  510   b  and an active region  510   c . Active region  510   b  and active region  510   c  are separated from each other in the second direction Y. 
     Active region  504   a   2  is adjacent to the first side  590   a  of integrated circuit  500 B. Active region  510   e  is adjacent to the second side  590   b  of integrated circuit  500 B. 
     Active region  504   a   2  of the set of active regions  505  is embedded in the first portion  502   a  of the first well  502  of integrated circuit  500 B. 
     Active region  510   e  of the set of active regions  505  is embedded in each of the second portion  502   b  of the first well  502  of integrated circuit  500 B and the second portion  502   d  of the second well  502 ′ of integrated circuit  500 B. Active region  510   b  is embedded in the second portion  502   b  of the first well  502  of integrated circuit  500 B. Active region  510   c  is embedded in the second portion  502   d  of the second well  502 ′ of integrated circuit  500 B. 
     Active region  506   a   2  or  508   a   2  of the set of active regions  505  is embedded in the first portion  502   c  of the second well  502 ′ of integrated circuit  500 B. 
     Active regions  504   a   2  and  510   b  includes dopants of the first type. Active regions  506   a   2 ,  508   a   2  and  510   c  includes dopants of the second type. 
     In some embodiments, the first type is an N-type dopant, the second type is a P-type dopant, and therefore active regions  504   a   2  and  510   b  are each N-type active regions embedded in the first well  502  (which is a P-well), and active regions  506   a   2 ,  508   a   2  and  510   c  are each P-type active regions embedded in the second well  502 ′ (which is an N-well). In some embodiments, the first type is a P-type dopant, the second type is an N-type dopant, and therefore active regions  504   a   2  and  510   b  are each P-type active regions embedded in the first well  502  (which is an N-well), and active regions  506   a   2 ,  508   a   2  and  510   c  are each N-type active regions embedded in the second well  502 ′ (which is a P-well). 
     In some embodiments, a length of at least one of active region  504   a   2 ,  506   a   2 ,  508   a   2 ,  510   b ,  510   c , or  510   e  in the second direction Y is different from a length of another of active region  504   a   2 ,  506   a   2 ,  508   a   2 ,  510   b ,  510   c , or  510   e  in the second direction Y. In some embodiments, a length of at least one of active region  504   a   2 ,  506   a   2 ,  508   a   2 ,  510   b ,  510   c , or  510   e  in the second direction Y is the same as a length of another of active region  504   a   2 ,  506   a   2 ,  508   a   2 ,  510   b ,  510   c , or  510   e  in the second direction Y. Other quantities or configurations of the set of active regions  505  are within the scope of the present disclosure. 
     In some embodiments, integrated circuit  500 A- 500 B occupies less area than other integrated circuits. In some embodiments, by occupying less area than other integrated circuits, integrated circuit  500 A- 500 B is utilized as part of a memory cell array  200 A- 200 B that is denser compared with other approaches. In some embodiments, by being utilized as part of a denser memory cell array  200 A- 200 B, memory cell array  200 A- 200 B has a larger memory capacity than other approaches. 
       FIG.  6    is a diagram of a layout design  600 , in accordance with some embodiments. 
     A portion of layout design  600  is usable to manufacture integrated circuit  500 A or  500 B ( FIGS.  5 A- 5 H ). 
     Layout design  600  comprises a first set of tiles  602  and a second set of tiles  604  arranged as an array of tiles. In some embodiments, at least one tile of the first set of tiles  602  corresponds to layout design  300 A or  300 B, and at least one tile of the second set of tiles  604  corresponds to layout design  400 A or  400 B. In some embodiments, at least one tile of the first set of tiles  602  corresponds to layout design  400 A or  400 B, and at least one tile of the second set of tiles  604  corresponds to layout design  300 A or  300 B. In some embodiments, a shape of the first set of tiles  602  and a shape of the second set of tiles  604  are non-rectangular, and therefore the shape of layout design  600  can also be a non-rectangular shape. 
     The first set of tiles  602  extends in a third direction S. The third direction S relates to the first direction X and the second direction Y. For example, in some embodiments, the third direction S is rotated from the first direction X towards the second direction Y by an angle α. In some embodiments, the angle α ranges from about 0 degrees to about 180 degrees. The angle α is expressed by formula 2 (described below). In some embodiments, the third direction S is equal to the first direction X or the second direction Y. In some embodiments, the third direction S is different from the first direction X or the second direction Y. The first set of tiles  602  comprises one or more of tiles  608 [1,1],  608 [2,1], . . . ,  608 [P, 1 ],  608 [1,3],  608 [2,3], . . . ,  608 [P, 3 ],  608 [1,Q−1],  608 [2,Q−1], . . . ,  608 [P−1,Q−1], where P is a positive integer corresponding to the number of columns in the array of tiles and Q is a positive integer corresponding to the number of rows in the array of tiles. 
     Each tile of the first set of tiles  602  extends in the first direction X. Each tile of the first set of tiles  602  has four notches (not labelled for ease of illustration). In some embodiments, the four notches (not labelled for ease of illustration) of each tile of the first set of tiles  602  corresponds to corner notches  390   a ,  390   b ,  390   c  and  390   d  of the set of corner notches  390  of  FIGS.  3 A- 3 B . For example, tile  608 [P,Q−1] has notches  630   a ,  630   b ,  630   c  and  630   d . In some embodiments, notches  630   a ,  630   b ,  630   c  and  630   d  are corresponding corner notches  390   a ,  390   b ,  390   c  and  390   d  of  FIGS.  3 A- 3 B . Each notch  630   a ,  630   b ,  630   c  and  630   d  is located in a corresponding corner of tile  608 [P,Q−1]. In some embodiments, each notch (not labelled for ease of illustration) of each tile of the first set of tiles  602  is located in a corresponding corner of the tile of the first set of tiles  602 . A center of each tile of the first set of tiles  602  is offset from a center of an adjacent tile of the first set of tiles  602  in the second direction Y by a distance D 1 . For example, the center of tile  608 [1,1] is separated from the center of tile  608 [2,1] in the second direction Y by the distance D 1 . 
     A center of each tile of the first set of tiles  602  is separated from a center of an adjacent tile of the first set of tiles  602  in the third direction S by a distance D 2 . For example, a center of tile  608 [1,1] is separated from a center of tile  608 [2,1] in the third direction S by the distance D 2 . 
     A center of each tile of the first set of tiles  602  is separated from a center of an adjacent tile of the first set of tiles  602  in the first direction X by a distance D 3 . For example, the center of tile  608 [1,1] is separated from the center of tile  608 [2,1] in the first direction X by the distance D 3 . 
     A relationship between distances D 1 , D 2  and D 3  is expressed by formula 1.
 
 D 2=( D 1 2   +D 3 2 ) 0.5   (1)
 
     The second set of tiles  604  extends in the third direction S. A relationship between angle α and distances D 2  and D 3  is expressed by formula 2.
 
α=ArcCos( D 3/ D 2)  (2)
 
     The second set of tiles  604  comprises one or more of tiles  608 [1,2],  608 [2,2], . . . ,  608 [P, 2 ],  608 [1,4],  608 [2,4], . . . ,  608 [P, 4 ],  608 [1,Q],  608 [2,Q], . . . ,  608 [P,Q]. The second set of tiles  604  is separated from the first set of tiles  602  in the second direction Y. 
     The first set of tiles  602  and the second set of tiles  604  alternate with each other in the second direction Y. Each tile of the second set of tiles  604  extends in the first direction X. Each tile of the second set of tiles  604  has four notches (not labelled for ease of illustration). In some embodiments, the four notches (not labelled for ease of illustration) of each tile of the second set of tiles  604  corresponds to corner notches  490   a ,  490   b ,  490   c  and  490   d  of the set of corner notches  490  of  FIGS.  4 A- 4 B . For example, tile  608 [P,Q] has notches  640   a ,  640   b ,  640   c  and  640   d . In some embodiments, notches  640   a ,  640   b ,  640   c  and  640   d  are corresponding corner notches  490   a ,  490   b ,  490   c  and  490   d  of  FIGS.  4 A- 4 B . Each notch  640   a ,  640   b ,  640   c  and  640   d  is located in a corresponding corner of tile  608 [P,Q]. In some embodiments, each notch (not labelled for ease of illustration) of each tile of the second set of tiles  604  is located in a corresponding corner of the tile of the second set of tile  604 . A center of each tile of the second set of tiles  604  is offset from a center of an adjacent tile of the second set of tiles  604  in the second direction Y by a distance D 1 ′. For example, the center of tile  608 [1,2] is separated from the center of tile  608 [2,2] in the second direction Y by the distance D 1 ′. 
     A center of each tile of the second set of tiles  604  is separated from a center of an adjacent tile of the second set of tiles  604  in the third direction S by a distance D 2 ′. For example, a center of tile  608 [1,2] is separated from a center of tile  608 [2,2] in the third direction S by the distance D 2 ′. 
     A center of each tile of the second set of tiles  604  is separated from a center of an adjacent tile of the second set of tiles  604  in the first direction X by a distance D 3 ′. For example, the center of tile  608 [1,2] is separated from the center of tile  608 [2,2] in the first direction X by the distance D 3 ′. 
     A relationship between distances D 1 ′, D 2 ′ and D 3 ′ is expressed by formula 3.
 
 D 2′=( D 1′ 2   +D 3′ 2 ) 0.5   (3)
 
     A relationship between angle α and distances D 2 ′ and D 3 ′ is expressed by formula 4.
 
α=ArcCos( D 3′/ D 2′)  (4)
 
     A center of a tile of the second set of tiles  604  is separated from a center of an adjacent tile of the first set of tiles  604  in a fourth direction T by a distance D 4 . For example, the center of tile  608 [1,1] is separated from the center of tile  608 [1,2] in the fourth direction T by the distance D 4 . The fourth direction T relates to the first direction X and the second direction Y. For example, the fourth direction T is rotated from the first direction X towards the second direction Y by an angle β. In some embodiments, the angle β ranges from about 0 degrees to about 180 degrees. The angle β relates to distances D 5  and D 4  by formula 5.
 
β=ArcCos( D 5 /D 4)  (5)
 
     In some embodiments, the fourth direction T is equal to the first direction X or the second direction Y. In some embodiments, the fourth direction T is different from the first direction X or the second direction Y. A center of a tile of the second set of tiles  604  is separated from a center of an adjacent tile of the first set of tiles  604  in the first direction X by a distance D 5 . For example, the center of tile  608 [P, 1 ] is separated from the center of tile  608 [P, 2 ] in the first direction X by the distance D 5 . 
     In some embodiments, two notches (not labelled) of a tile in the second set of tiles  604  are flush with tiles in the first set of tiles  602 , and the other two notches (not labelled) are not flush with adjacent tiles in the first set of tiles  602  or the second set of tiles  604  creating a corresponding space (not labelled) between adjacent tiles. In some embodiments, one or more spaces (not labelled) between adjacent tiles can be utilized for well contacts (not shown) or substrate contacts (not shown). In some embodiments, additional well contacts (not shown) or substrate contacts (not shown) can be utilized to improve latch-up prevention. In some embodiments, latch-up is a short circuit between one or more wells and the substrate. In some embodiments, two notches (not labelled) of a tile in the second set of tiles  604  are flush with corresponding notches (not labelled) of two different tiles in the first set of tiles  602 . For example, notch  610   a  of tile  608 [2,4] of the second set of tiles  604  is flush with a corresponding notch  612   a  of tile  608 [1,Q−1] of the first set of tiles  602 , and notch  610   b  of tile  608 [2,4] of the second set of tiles  604  is flush with a corresponding notch  612   b  of tile  608 [2,3] of the first set of tiles  602 . 
     In some embodiments, two notches (not labelled for ease of illustration) of a tile in the first set of tiles  602  are flush with corresponding notches (not labelled for ease of illustration) of two different tiles in the second set of tiles  604 . For example, notch  612   b  of tile  608 [2,3] of the first set of tiles  602  is flush with a corresponding notch  610   b  of tile  608 [2,4] of the second set of tiles  604 , and notch  614   a  of tile  608 [2,3] of the first set of tiles  602  is flush with a corresponding notch  614   b  of tile  608 [P, 2 ] of the second set of tiles  604 . In some embodiments, two notches (not labelled for ease of illustration) of a tile in the second set of tiles  604  are not flush with portions of adjacent tiles in the first set of tiles  602  or the second set of tiles  604  creating a space (not labelled for ease of illustration) that can be utilized for well contacts (not shown) or substrate contacts (not shown). For example, in some embodiments, a notch  650   a  of tile  608 [2, 4] is not flush with adjacent tiles  608 [1,4] and  608 [1, 3] resulting in space  622   a . Similarly, in some embodiments, a notch  650   b  of tile  608 [2, 4] is not flush with adjacent tiles  608 [2,Q−1] and  608 [P,  4 ] resulting in space  622   b . For example, in some embodiments, as shown in  FIG.  6   , space  620   a  is between tile  608 [2, Q−1] and tile  608 [1, Q−1] of the first set of tiles  602 , and space  620   b  is between tile  608 [2, Q−1] and  608 [P, Q−1] of the first set of tiles  602 . In these embodiments, space  622   a  and space  622   b  can be utilized for well contacts (not shown) or substrate contacts (not shown). In some embodiments, two notches (not labelled for ease of illustration) of a tile in the first set of tiles  602  are not flush with portions of adjacent tiles in the second set of tiles  604  or the first set of tiles  602 . For example, in some embodiments, a notch  652   a  of tile  608 [2, Q−1] is not flush with adjacent tiles  608 [2, 4] and  608 [1, Q−1] resulting in space  620   a . Similarly, in some embodiments, a notch  652   b  of tile  608 [2, Q−1] is not flush with adjacent tiles  608 [P,Q−1] and  608 [2, Q] resulting in space  620   b . In these embodiments, space  620   a  and space  620   b  can be utilized for well contacts (not shown) or substrate contacts (not shown). In some embodiments, at least space  620   a ,  620   b ,  622   a  or  622   b  is 12.5% of the area of a tile in the first set of tiles  602  or the second set of tiles  604 . 
     In some embodiments, at least one of distances D 1 , D 1 ′, D 2 , D 2 ′, D 3 , D 3 ′, D 4  or D 5  is different from another of distances D 1 , D 1 ′, D 2 , D 2 ′, D 3 , D 3 ′, D 4  or D 5 . In some embodiments, at least one of distances D 1 , D 1 ′, D 2 , D 2 ′, D 3 , D 3 ′, D 4  or D 5  is the same as another of distances D 1 , D 1 ′, D 2 , D 2 ′, D 3 , D 3 ′, D 4  or D 5 . Other quantities or configurations of the first set of tiles  602  or the second set of tiles  604  are within the scope of the present disclosure. In some embodiments, each of the notches of at least one tile of the first set of tiles  602  or the second set of tiles  604  is a right-angled notch. In some embodiments, each of the notches of at least one tile of the first set of tiles  602  or the second set of tiles  604  is referred to as a corner notch. In some embodiments, each of the notches of at least one tile of the first set of tiles  602  or the second set of tiles  604  is a quirk. Other shapes or configurations of the notches in the first set of tiles  602  or the second set of tiles  604  are within the scope of the present disclosure. 
     In some embodiments, a shape of the first set of tiles  602  and a shape of the second set of tiles  604  are non-rectangular, and therefore can be placed as standard cells in layout design  600  closer to each other than other designs. In some embodiments, by placing the first set of tiles  602  and the second set of tiles  604  closer to each other than other cells, the first set of tiles or the second set of tiles can be utilized to manufacture corresponding integrated circuits that are closer to each other than other integrated circuits. In some embodiments, by manufacturing integrated circuits that are closer to each other than other integrated circuits, the area of the manufactured integrated circuits are also smaller than other integrated circuits. 
       FIG.  7    is a diagram of a layout design  700 , in accordance with some embodiments. 
     Layout design  700  is a variation of layout design  600  ( FIG.  6   ). Similar elements have a same reference number increased by 100. Layout design  700  combines features of layout design  300 A of  FIG.  3 A , layout design  400 A of  FIG.  4 A  and layout design  600  of  FIG.  6   . 
     Layout design  700  includes tile  708 [1,2], tile  708 [2,2], tile  708 [1,3] and tile  708 [2,3]. Tiles  708 [1,2],  708 [2,2],  708 [1,3] and  708 [2,3] are a variation of corresponding tiles  608 [1,2],  608 [2,2],  608 [1,3] and  608 [2,3] of  FIG.  6   . 
     Each of tiles  708 [1,2] and  708 [2,2] corresponds to layout design  300 A of  FIG.  3 A , and each of tiles  708 [1,3] and  708 [2,3] corresponds to layout design  400 A of  FIG.  4 A . In some embodiments, each of tiles  708 [1,2] and  708 [2,2] corresponds to layout design  400 A of  FIG.  4 A , and each of tiles  708 [1,3] and  708 [2,3] corresponds to layout design  300 A of  FIG.  3 A . For ease of illustration, each of the elements within tiles  708 [1,2],  708 [2,2],  708 [1,3] and  708 [2,3] are not labeled. 
     Tiles  708 [1,2],  708 [2,2],  708 [1,3] and  708 [2,3] include corresponding set of active region layout patterns  702 ,  704 ,  712  and  714 . 
     The set of active region  702  or  704  corresponds to the set of active region layout patterns  412   a ,  412   b ,  412   c  and  412   d  of layout design  400 A. The set of active region  712  or  714  corresponds to the set of active region layout patterns  312   a ,  312   b ,  312   c  and  312   d  of layout design  300 A. 
     The set of active region  702  includes active region layout patterns  702   a ,  702   b ,  702   c ,  702   d ,  702   e ,  702   f ,  702   g  and  702   h . Active region layout pattern  702   a  corresponds to active region layout patterns  404   a  and  404   b , active region layout pattern  702   b  corresponds to active region layout patterns  406   a  and  406   b , active region layout pattern  702   c  corresponds to active region layout patterns  408   a  and  408   b , active region layout pattern  702   d  corresponds to active region layout patterns  410   a  and  410   b , active region layout pattern  702   e  corresponds to active region layout patterns  410   c  and  410   d , active region layout pattern  702   f  corresponds to active region layout patterns  408   c  and  408   d , active region layout pattern  702   g  corresponds to active region layout patterns  406   c  and  406   d , active region layout pattern  702   h  corresponds to active region layout patterns  404   c  and  404   d.    
     The set of active region  702  includes active region layout patterns  704   a ,  704   b ,  704   c ,  704   d ,  704   e ,  704   f ,  704   g  and  704   h . Active region layout patterns  704   a ,  704   b ,  704   c ,  704   d ,  704   e ,  704   f ,  704   g  and  704   h  are similar to corresponding active region layout patterns  702   a ,  702   b ,  702   c ,  702   d ,  702   e ,  702   f ,  702   g  and  702   h , and similar detailed description is therefore omitted. 
     The set of active region  712  includes active region layout patterns  712   a ,  712   b ,  712   c ,  712   d ,  712   e ,  712   f ,  712   g  and  712   h . Active region layout pattern  712   a  corresponds to active region layout patterns  304   a  and  304   b , active region layout pattern  712   b  corresponds to active region layout patterns  306   a  and  306   b , active region layout pattern  712   c  corresponds to active region layout patterns  308   a  and  308   b , active region layout pattern  712   d  corresponds to active region layout patterns  310   a  and  310   b , active region layout pattern  712   e  corresponds to active region layout patterns  310   c  and  310   d , active region layout pattern  712   f  corresponds to active region layout patterns  308   c  and  308   d , active region layout pattern  712   g  corresponds to active region layout patterns  306   c  and  306   d , active region layout pattern  712   h  corresponds to active region layout patterns  304   c  and  304   d.    
     The set of active region  714  includes active region layout patterns  714   a ,  714   b ,  714   c ,  714   d ,  714   e ,  714   f ,  714   g  and  714   h . Active region layout patterns  714   a ,  714   b ,  714   c ,  714   d ,  714   e ,  714   f ,  714   g  and  714   h  are similar to corresponding active region layout patterns  712   a ,  712   b ,  712   c ,  712   d ,  712   e ,  712   f ,  712   g  and  712   h , and similar detailed description is therefore omitted. 
     The n-type layout patterns of the set of active region layout pattern  702  or  704  of corresponding tile  708 [1,2] or  708 [2,2] are aligned in the second direction Y with corresponding n-type layout patterns of the set of active region layout patterns  712  or  714  of corresponding tile  708 [1,3] or  708 [2,3]. For example, n-type active region layout patterns  702   d ,  702   e ,  702   h ,  704   a ,  704   d ,  704   e  and  704   h  are aligned in the second direction Y with corresponding n-type active region layout patterns  712   b ,  712   c ,  712   f ,  712   g ,  714   b ,  714   c  and  714   f.    
     The p-type layout patterns of the set of active region layout pattern  712  or  714  of corresponding tile  708 [1,2] or  708 [2,2] are aligned in the second direction Y with corresponding p-type layout patterns of the set of active region layout patterns  712  or  714  of corresponding tile  708 [1,3] or  708 [2,3]. For example, p-type active region layout patterns  702   c ,  702   f ,  702   g ,  704   b ,  704   c ,  704   f  and  704   g  are aligned in the second direction Y with corresponding p-type active region layout patterns  712   a ,  712   d ,  712   e ,  712   h ,  714   a ,  714   d  and  714   e . Other quantities or configurations of tiles  708 [1,2],  708 [2,2],  708 [1,3] and  708 [2,3] are within the scope of the present disclosure. 
     In some embodiments, layout design  700  has a non-rectangular shape which results in a smaller standard cell than other designs. In some embodiments, by having a smaller standard cell, layout design  700  can be utilized to manufacture integrated circuits that are smaller than other integrated circuits. 
       FIG.  8    is a diagram of a layout design  800 , in accordance with some embodiments. 
     Layout design  800  is a variation of layout design  600  of  FIG.  6    and layout design  700  of  FIG.  7   . Similar elements have a same reference number increased by 200. Layout design  800  combines features of layout design  300 B of  FIG.  3 B , layout design  400 B of  FIG.  4 B  and layout design  600  of  FIG.  6   . 
     In comparison with layout design  700  of  FIG.  7   , layout design  800  further includes a first well layout pattern  802 , a second well layout pattern  804 , a third well layout pattern  806 , a fourth well layout pattern  808 , a fifth well layout pattern  812 , a sixth well layout pattern  814 , a seventh well layout pattern  816 , an eighth well layout pattern  818 , and well layout patterns  822   a ,  824   a  and  828   a.    
     First well layout pattern  802  and fifth well layout pattern  812  are similar to second well layout pattern  414  of layout design  400 B of  FIG.  4 B , and similar detailed description is therefore omitted. Second well layout pattern  804  and sixth well layout pattern  814  are similar to the first well layout pattern  416  of layout design  400 B of  FIG.  4 B , and similar detailed description is therefore omitted. Third well layout pattern  806  and seventh well layout pattern  816  are similar to first well layout pattern  314  of layout design  300 B of  FIG.  3 B , and similar detailed description is therefore omitted. Fourth well layout pattern  808  and eighth well layout pattern  818  are similar to second well layout pattern  316  of layout design  300 B of  FIG.  3 B , and similar detailed description is therefore omitted. 
     First well layout pattern  802  includes well layout patterns  802   a ,  802   b  and  802   c . Well layout patterns  802   a ,  802   b  and  802   c  are similar to corresponding well layout patterns  454   a ,  454   b  and  454   c  of layout design  400 B of  FIG.  4 B , and similar detailed description is therefore omitted. 
     Second well layout pattern  804  includes well layout patterns  804   a ,  804   b ,  804   c  and  804   d . Well layout patterns  804   a ,  804   b ,  804   c  and  804   d  are similar to corresponding well layout patterns  456   a ,  456   b ,  456   c  and  456   d  of layout design  400 B of  FIG.  4 B , and similar detailed description is therefore omitted. 
     Third well layout pattern  806  includes well layout patterns  806   a ,  806   b  and  806   c . Well layout patterns  806   a ,  806   b  and  806   c  are similar to corresponding well layout patterns  354   a ,  354   b  and  354   c  of layout design  300 B of  FIG.  3 B , and similar detailed description is therefore omitted. 
     Fourth well layout pattern  808  includes well layout patterns  808   a  and  808   b . Well layout patterns  808   a  and  808   b  are similar to corresponding well layout patterns  356   a  and  356   b  of layout design  300 B of  FIG.  3 B , and similar detailed description is therefore omitted. 
     Fifth well layout pattern  812  includes well layout patterns  812   a ,  812   b  and  812   c . Well layout patterns  812   a ,  812   b  and  812   c  are similar to corresponding well layout patterns  454   a ,  454   b  and  454   c  of layout design  400 B of  FIG.  4 B , and similar detailed description is therefore omitted. 
     Sixth well layout pattern  814  includes well layout patterns  814   a ,  814   b ,  814   c  and  814   d . Well layout patterns  814   a ,  814   b ,  814   c  and  814   d  are similar to corresponding well layout patterns  456   a ,  456   b ,  456   c  and  456   d  of layout design  400 B of  FIG.  4 B , and similar detailed description is therefore omitted. 
     Seventh well layout pattern  816  includes well layout patterns  816   a ,  816   b  and  816   c . Well layout patterns  816   a ,  816   b  and  816   c  are similar to corresponding well layout patterns  354   a ,  354   b  and  354   c  of layout design  300 B of  FIG.  3 B , and similar detailed description is therefore omitted. 
     Eighth well layout pattern  818  includes well layout patterns  818   a  and  818   b . Well layout patterns  818   a  and  818   b  are similar to corresponding well layout patterns  356   a  and  356   b  of layout design  300 B of  FIG.  3 B , and similar detailed description is therefore omitted. 
     Well layout pattern  822   a  is similar to well layout pattern  456   a  of layout design  400 B of  FIG.  4 B , and similar detailed description is therefore omitted. Well layout pattern  824   a  is similar to well layout pattern  454   a  of layout design  400 B of  FIG.  4 B , and similar detailed description is therefore omitted. Well layout pattern  828   a  is similar to well layout pattern  356   a  of layout design  300 B of  FIG.  3 B , and similar detailed description is therefore omitted. 
     In some embodiments, well layout patterns  804   a  and  828   a  are part of a same continuous well layout pattern. In some embodiments, at least two of well layout patterns  802   a ,  802   b ,  802   c ,  806   a  and  806   b  are part of a same continuous well layout pattern. In some embodiments, well layout patterns  804   c  and  808   a  are part of a same continuous well layout pattern. In some embodiments, well layout patterns  802   c  and  806   b  are part of a same continuous well layout pattern. In some embodiments, at least two of well layout patterns  804   b ,  814   a  and  808   b  are part of a same continuous well layout pattern. 
     In some embodiments, at least two of well layout patterns  812   a ,  812   b ,  812   c ,  816   a  and  816   b  are part of a same continuous well layout pattern. In some embodiments, well layout patterns  814   c  and  818   a  are part of a same continuous well layout pattern. In some embodiments, well layout patterns  812   c  and  816   b  are part of a same continuous well layout pattern. In some embodiments, at least two of well layout patterns  822   a ,  814   b  and  818   b  are part of a same continuous well layout pattern. In some embodiments, well layout patterns  816   c  and  824   a  are part of a same continuous well layout pattern. 
     Other quantities or configurations of one or more of first well layout pattern  802 , second well layout pattern  804 , third well layout pattern  806 , fourth well layout pattern  808 , fifth well layout pattern  812 , sixth well layout pattern  814 , seventh well layout pattern  816 , eighth well layout pattern  818  or well layout patterns  822   a ,  824   a  and  828   a  are within the scope of the present disclosure. 
     In some embodiments, layout design  800  has a non-rectangular shape which results in a smaller standard cell than other designs. In some embodiments, by having a smaller standard cell, layout design  800  can be utilized to manufacture integrated circuits that are smaller than other integrated circuits. 
       FIG.  9    is a flowchart of a method  900  of forming or manufacturing a memory cell array in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method  900  depicted in  FIG.  9   , and that some other processes may only be briefly described herein. In some embodiments, the method  900  is usable to form one or more memory cells, such as memory cell  100  ( FIG.  1   ), one or more memory cell arrays, such as memory cell array  200 A- 200 B ( FIGS.  2 A- 2 B ) or one or more integrated circuits such as integrated circuit  500 A- 500 H ( FIGS.  5 A- 5 H ). In some embodiments, the method  900  is usable to form memory cell arrays or integrated circuits having similar structural relationships as one or more of layout designs  300 A- 300 B,  400 A- 400 B or  600 - 800  ( FIGS.  3 A- 3 B,  4 A- 4 B or  6 - 8   ). 
     In operation  902  of method  900 , a first set of tiles  602  extending in a first direction (e.g., third direction S) is generated. In some embodiments, generating the first set of tiles  602  of operation  902  includes operation  902   a.    
     In some embodiments, operation  902   a  includes generating a first layout design (e.g., layout design  300 A- 300 B) of a first set of memory cells  204 . In some embodiments, at least one tile of the first set of tiles  602  corresponds to layout design  300 A or  300 B. In some embodiments, each tile of the first set of tiles  602  corresponds to layout design  300 A or  300 B of the first set of memory cells  204 . In some embodiments, each tile of the first set of tiles  602  is offset from an adjacent tile of the first set of tiles in the second direction Y different from the first direction ((e.g., third direction S). 
     In some embodiments, generating the first layout design (e.g., layout design  300 A- 300 B) of the first set of memory cells  204  of operation  902   a  includes generating a first portion  302   a  of the first layout design (e.g., layout design  300 A- 300 B), generating a second portion  302   b  of the first layout design, generating a third portion  302   c  of the first layout design and generating a fourth portion  302   d  of the first layout design. 
     In some embodiments, the first portion  302   a  of the first layout design (e.g., layout design  300 A- 300 B) corresponds to fabricating a first memory cell  202 [1,2] of the first set of memory cells  204  of memory cell array  200 A- 200 B. In some embodiments, the second portion  302   b  of the first layout design (e.g., layout design  300 A- 300 B) corresponds to fabricating a second memory cell  202 [2,2] of the first set of memory cells  204  of memory cell array  200 A- 200 B. In some embodiments, the third portion  302   c  of the first layout design (e.g., layout design  300 A- 300 B) corresponds to fabricating a third memory cell  202 [1,3] of the first set of memory cells  204  of memory cell array  200 A- 200 B. In some embodiments, the fourth portion  302   d  of the first layout design (e.g., layout design  300 A- 300 B) corresponds to fabricating a fourth memory cell  202 [2,3] of the first set of memory cells  204  of memory cell array  200 A- 200 B. 
     In some embodiments, the first portion  302   a  of the first layout design (e.g., layout design  300 A- 300 B) and the second portion  302   b  of the first layout design are mirror images of each other with respect to the second direction Y. In some embodiments, the third portion  302   c  of the first layout design (e.g., layout design  300 A- 300 B) and the fourth portion  302   d  of the first layout design are mirror images of each other with respect to the second direction Y. 
     In operation  904  of method  900 , a second set of tiles  604  extending in the first direction (e.g., third direction S) is generated. In some embodiments, the second set of tiles  604  is separated from the first set of tiles  602  in at least the second direction Y. In some embodiments, generating the second set of tiles  604  of operation  904  includes operation  904   a.    
     In some embodiments, operation  904   a  includes generating a second layout design (e.g., layout design  400 A- 400 B) of a second set of memory cells  206 . In some embodiments, at least one tile of the second set of tiles  604  corresponds to layout design  400 A or  400 B. In some embodiments, each tile of the second set of tiles  604  corresponds to the second layout design (e.g., layout design  400 A- 400 B) of the second set of memory cells  206 . In some embodiments, each tile of the second set of tiles  604  is offset from an adjacent tile of the second set of tiles  604  in the second direction Y. 
     In some embodiments, generating the second layout design (e.g., layout design  400 A- 400 B) of the second set of memory cells  206  of operation  904   a  includes generating a first portion  402   a  of the second layout design (e.g., layout design  400 A- 400 B), generating a second portion  402   b  of the first layout design, generating a third portion  402   c  of the first layout design and generating a fourth portion  402   d  of the first layout design. 
     In some embodiments, the first portion  402   a  of the second layout design (e.g., layout design  400 A- 400 B) corresponds to fabricating a first memory cell  202 [2,4] of the second set of memory cells  206  of memory cell array  200 A- 200 B. In some embodiments, the second portion  402   b  of the second layout design (e.g., layout design  400 A- 400 B) corresponds to fabricating a second memory cell  202 [3,4] of the second set of memory cells  206  of memory cell array  200 A- 200 B. In some embodiments, the third portion  402   c  of the second layout design (e.g., layout design  400 A- 400 B) corresponds to fabricating a third memory cell  202 [2,5] of the second set of memory cells  206  of memory cell array  200 A- 200 B. In some embodiments, the fourth portion  402   d  of the second layout design (e.g., layout design  400 A- 400 B) corresponds to fabricating a fourth memory cell  202 [3,5] of the second set of memory cells  206  of memory cell array  200 A- 200 B. 
     In some embodiments, the first portion  402   a  of the second layout design (e.g., layout design  400 A- 400 B) and the third portion  402   c  of the second layout design are mirror images of each other with respect to the third direction (e.g., first direction X). In some embodiments, the second portion  402   b  of the second layout design (e.g., layout design  400 A- 400 B) and the fourth portion  402   d  of the second layout design are mirror images of each other with respect to the third direction (e.g., first direction X). 
     In some embodiments, the first set of tiles  602  and the second set of tiles  604  alternate with each other in the second direction X. In some embodiments, each tile of the first set of tiles  602  and each tile of the second set of tiles  604  extends in a third direction (e.g., first direction X) different from the first direction and the second direction. 
     In some embodiments, at least operation  902  or  904  is performed by a processing device (e.g., processor  1202  ( FIG.  12   )) configured to execute instructions for generating the first set of tiles  602  or the second set of tiles  604 . In some embodiments, the first set of tiles  602  or the second set of tiles  604  are stored in a memory (e.g., a non-transitory computer-readable medium  1204  ( FIG.  12   )) as layout design  1216 . 
     In some embodiments, at least layout design  300 A- 300 B,  400 A- 400 B or  600 - 800  is a graphic database system (GDSII) file format. 
     In operation  906  of method  900 , a memory cell array  200 A or  200 B or an integrated circuit  500 A or  500 B is manufactured based on at least the first layout design (layout design  300 A or  300 B), the second layout design (second layout design  400 A or  400 B) or layout designs  600 - 800 . In some embodiments, operation  906  of method  900  includes manufacturing memory cell array  200 A or  200 B or integrated circuit  500 A or  500 B based on at least the first set of tiles  602  or the second set of tiles  604 . In some embodiments, operation  906  includes manufacturing memory cell  100  based on at least the first layout design  300 A or  300 B or second layout design  400 A or  400 B. In some embodiments, operation  906  includes manufacturing memory cell array  200 A or  200 B or integrated circuit  500 A or  500 B based on at least the first set of tiles  602  or the second set of tiles  604 . 
     In some embodiments, operation  906  of method  900  comprises manufacturing at least one mask based on at least layout design  300 A- 300 B,  400 A- 400 B or  600 - 800 , and manufacturing the memory cell array (e.g., memory cell,  100 , memory cell array  200 A- 200 B) or integrated circuit (e.g., integrated circuit  500 A or  500 B) based on the at least one mask. 
     In some embodiments, one or more of operations  902 ,  904  or  906  is not performed. 
     In some embodiments, method  900  generates one or more layout designs (e.g., first layout design  300 A- 300 B, second layout design  400 A- 400 B or layout design  600 - 800 ) that occupy less area than other approaches. In some embodiments, method  900  is used to manufacture a memory cell array (e.g., memory cell  100 , memory cell array  200 A- 200 B or integrated circuit  500 A- 500 B) that occupies less area than other memory cell arrays. 
       FIGS.  10 A- 10 B  are a flowchart of a method  1000  of generating a layout design of a memory cell array in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method  1000  depicted in  FIGS.  10 A- 10 B , and that some other processes may only be briefly described herein. Method  1000  is an embodiment of at least operation  902   a  or  904   a . In some embodiments, the method  1000  is usable to generate one or more of layout designs  300 A- 300 B ( FIGS.  3 A- 3 B ) or  400 A- 400 B ( FIGS.  4 A- 4 B ) or  600 - 700  ( FIGS.  600 - 700   ) of memory cell  100  ( FIG.  1   ), memory cell array  200 A- 200 B ( FIGS.  2 A- 2 B ) or integrated circuit  500 A- 500 B ( FIGS.  5 A- 5 H ). 
     In operation  1002  of method  1000 , a set of active region layout patterns  312   a  or  412   a  is generated. In some embodiments, generating the set of active region layout patterns  312   a ,  412   a  corresponds to fabricating a set of active regions  504  or  505  of memory cell array  200 A- 200 B. In some embodiments, each of the layout patterns of the set of active region layout patterns  312   a ,  412   a  is separated from an adjacent layout pattern of the set of active region layout patterns  312   a ,  412   a  in the first direction X by a first pitch. In some embodiments, the set of active region layout patterns  312   a ,  412   a  extend in the second direction Y different from the first direction and being located on a first layout level (e.g., active region or well). 
     In some embodiments, the set of active region layout patterns of method  1000  includes one or more of set of active region layout patterns  312   b ,  312   c ,  312   d ,  412   a ,  412   b  or  412   c.    
     In some embodiments, generating the set of active region layout patterns  312   a ,  412   a  of operation  1002  includes generating a first active region layout pattern  304   a ,  404   a  adjacent to a first side  352   a ,  452   a  of the layout design  300 A- 300 B or  400 A- 400 B of memory cell  100 , and generating a second active region layout pattern  310   a ,  410   a  adjacent to a second side  352   b   1 ,  452   b   1  of memory cell  100  opposite from the first side  352   a ,  452   a  of the memory cell  100 . In some embodiments, a length of the first active region layout pattern  304   a ,  404   a  in the second direction Y is different from a length of the second active region layout pattern  310   a ,  410   a  in the second direction Y. 
     In operation  1004 , a set of active region layout patterns  312   a ,  412   a  is placed on a first layout level. In some embodiments, the first layout level corresponds to the active region of layout design  300 A- 300 B or  400 A- 400 B ( FIGS.  4 A- 4 B ). 
     In operation  1006 , a set of gate layout patterns  326   a  or  426   a  is generated. In some embodiments, the set of gate layout patterns  326   a ,  426   a  corresponds to fabricating a set of gate structures  527  of memory cell array  200 A- 200 B or integrated circuit  500 A- 500 B. In some embodiments, the set of gate layout patterns  326   a ,  426   a  extends in the first direction X and overlaps the set of active region layout patterns  312   a ,  412   a.    
     In some embodiments, the set of gate layout patterns of method  1000  includes one or more of set of gate layout patterns  326   b ,  326   c ,  326   d ,  426   b ,  426   c  or  426   d.    
     In operation  1008 , the set of gate layout patterns  326   a ,  426   a  is placed on a second layout level (e.g., POLY) different from the first layout level. 
     In operation  1010 , a first set of conductive feature layout patterns  338   a  or  438   a  is generated. In some embodiments, the first set of conductive feature layout patterns  338   a ,  438   a  corresponds to fabricating a first set of conductive structures  538  of memory cell array  200 A- 200 B or integrated circuit  500 A- 500 B. In some embodiments, the first set of conductive feature layout patterns  338   a ,  438   a  extends in the first direction X, and is over at least the set of active region layout patterns  312   a ,  412   a  or the set of gate layout patterns  326   a ,  426   a . In some embodiments, each conductive feature layout pattern of the first set of conductive feature layout patterns  338   a ,  438   a  is separated from an adjacent layout pattern of the first set of conductive feature layout patterns  338   a ,  438   a  in at least the first direction X or the second direction Y. 
     In some embodiments, the first set of conductive feature layout patterns of method  1000  includes one or more of set of conductive feature layout patterns  338   b ,  338   c ,  338   d ,  340 ,  342 ,  344 ,  438   b ,  438   c ,  438   d ,  440 ,  442  or  444 . 
     In operation  1012 , the first set of conductive feature layout patterns  338   a ,  438   a  is placed on a third layout level (e.g., M 1 ) different from the first layout level and the second layout level. 
     In operation  1014 , a second set of conductive feature layout patterns  350  or  450  is generated. In some embodiments, the second set of conductive feature layout patterns  350 ,  450  corresponds to fabricating a second set of conductive structures  552  of memory cell array  200 A- 200 B or integrated circuit  500 A- 500 B. In some embodiments, the second set of conductive feature layout patterns  350 ,  450  extends in the first direction X and overlaps at least the second active region layout pattern  310   a ,  310   b ,  310   c ,  310   d ,  410   a ,  410   b ,  410   c  or  410   d  and the second side  352   b   1 ,  452   b   1  of layout design  300 A- 300   b ,  400 A- 400 B of memory cell  100 . In some embodiments, each conductive feature layout pattern of the second set of conductive feature layout patterns  350 ,  450  is separated from an adjacent layout pattern of the second set of conductive feature layout patterns  350 ,  450  in at least the first direction X or the second direction Y. 
     In operation  1016 , the second set of conductive feature layout patterns  350 ,  450  is placed on a fourth layout level (e.g., M 2 ) different from the first layout level, the second layout level and the third layout level. 
     In operation  1018 , a first set of via layout patterns  358   a  or  458   a  is generated. In some embodiments, the first set of via layout patterns  358   a ,  458   a  corresponds to fabricating a first set of vias  572 . In some embodiments, the first set of vias  572  couple the first set of conductive structures  538  to the set of active regions  504 ,  505 . In some embodiments, each via layout pattern of the first set of via layout patterns  358   a ,  458   a  is located where each conductive feature layout pattern of the first set of conductive feature layout patterns  338   a ,  438   a  overlaps each active region layout pattern of the set of active region layout patterns  312   a ,  412   a.    
     In some embodiments, the first set of via layout patterns of method  1000  includes one or more of via layout patterns  358   b ,  358   c ,  358   d ,  458   b ,  458   c ,  458   d ,  374 ,  376 ,  378 ,  380 ,  474 ,  476 ,  478  or  480 . 
     In operation  1020 , the first set of via layout patterns  358   a ,  458   a  is placed between the first set of conductive feature layout patterns  338   a ,  438   a  and the set of active region layout patterns  312   a ,  412   a . In some embodiments, the first set of via layout patterns  358   a ,  458   a  are on at least the V 0  level of layout design  300 A- 300 B,  400 A- 400 B. 
     In operation  1022 , a second set of via layout patterns  380  or  480  is generated. In some embodiments, the second set of via layout patterns  380 ,  480  corresponds to fabricating a second set of vias  523 . In some embodiments, the second set of vias  523  couple the first set of conductive structures  338   a ,  438   a  to the set of gates  527 . In some embodiments, a first via layout pattern  380   a ,  480   a  of the second set of via layout patterns  380 ,  480  is located where a first conductive feature layout pattern  340   a ,  440   a  of the set of conductive feature layout patterns  340 ,  440  overlaps a first gate layout pattern  324   a ,  324   c ,  424   a ,  424   c  of the set of gate layout patterns  326   a ,  426   a.    
     In some embodiments, the second set of via layout patterns of method  1000  includes one or more of via layout patterns  358   a ,  358   b ,  358   c ,  358   d ,  458   a ,  458   b ,  458   c ,  458   d ,  374 ,  376 ,  378 ,  474 ,  476  or  478 . 
     In operation  1024 , the second set of via layout patterns  380 ,  480  is placed between the first set of conductive feature layout patterns  340 ,  440  and the set of gate layout patterns  326   a ,  426   a . In some embodiments, the second set of via layout patterns  380 ,  480  are on at least the VG level of layout design  300 A- 300 B,  400 A- 400 B 
     Method  1000  includes either operations  1026 - 1032  or operations  1026 ′- 1032 ′. 
     Operations  1026 - 1032  are discussed with reference to layout design  300 A- 300 B. For example, first well layout pattern  314  corresponds to the first well layout pattern of operations  1026 - 1032 , and the second well layout pattern  316  corresponds to the second well layout pattern of operations  1026 - 1032  of layout design  300 A- 300 B. 
     Operations  1026 ′- 1032 ′ are discussed with reference to layout design  400 A- 400 B, such that first well layout pattern  416  corresponds to the first well layout pattern of operations  1026 ′- 1032 ′, and the second well layout pattern  414  corresponds to the second well layout pattern of operations  1026 ′- 1032 ′. 
     For simplicity, operations  1026 ′- 1032 ′ are discussed after the discussion of operations  1026 - 1032 . 
     In operation  1026 , a first well layout pattern  314  is generated. In some embodiments, the first well layout pattern  314  corresponds to fabricating a first well  501  of memory cell array  200 A- 200 B or integrated circuit  500 A. In some embodiments, the first well  501  has a first dopant type. In some embodiments, the first dopant type is an N-dopant type. In some embodiments, the first dopant type is a P-dopant type. 
     In some embodiments, operation  1026  includes one or more of operations  1026   a  or  1026   b.    
     In some embodiments, operation  1026   a  includes generating a first layout pattern (e.g., layout pattern  354   a  or  354   c ). In some embodiments, the first layout pattern  354   a  corresponds to fabricating a first portion  501   a  of the first well  501 . In some embodiments, the first layout pattern  354   a  extends in the second direction Y and is adjacent to the first side  352   a  of the layout design  300 B of memory cell  100 . 
     In some embodiments, operation  1026   b  includes generating a second layout pattern (e.g., layout pattern  354   b ). In some embodiments, the second layout pattern  354   b  corresponds to fabricating a second portion  501   b  of the first well  501 . In some embodiments, the second layout pattern extends in the second direction and is adjacent to the second side of the memory cell  100 . 
     In operation  1028 , the first well layout pattern  314  is placed on a fourth layout level (e.g., well level) different from the first layout level, the second layout level and the third layout level. In some embodiments, a portion of the fourth layout level includes the first layout level. In some embodiments, a portion of the fourth layout level is the same as the first layout level. 
     In some embodiments, operation  1028  includes one or more of operations  1028   a  or  1028   b.    
     In some embodiments, operation  1028   a  includes placing the first layout pattern  354   a  below the first active region layout pattern  304   a.    
     In some embodiments, operation  1028   b  includes placing the second layout pattern  354   b  below the second active region layout pattern  310   a.    
     In operation  1030 , a second well layout pattern  316  is generated. In some embodiments, the second well layout pattern  316  corresponds to fabricating a second well  501 ′ of memory cell array  200 A- 200 B or integrated circuit  500 A. In some embodiments, the second well  501 ′ has a second dopant type different from the first dopant type. In some embodiments, the second dopant type is a P-dopant type. In some embodiments, the second dopant type is an N-dopant type. 
     In some embodiments, operation  1030  includes one or more of operations  1030   a  or  1030   b.    
     In some embodiments, operation  1030   a  includes generating a third layout pattern (e.g., layout pattern  356   a ). In some embodiments, the third layout pattern  356   a  corresponds to fabricating a portion  501   c  of the second well  501 ′. In some embodiments, the third layout pattern  356   a  extends in the second direction Y. In some embodiments, the third layout pattern  356   a  is between the first layout pattern and  354   a  the second layout pattern  354   b.    
     In some embodiments, operation  1030   b  includes generating a fourth layout pattern (e.g., layout pattern  356   b ). In some embodiments, the fourth layout pattern  356   b  corresponds to fabricating a portion of the second well  501 ′ similar to portion  501   c . In some embodiments, the fourth layout pattern  356   b  extends in the second direction Y. In some embodiments, the fourth layout pattern  356   b  is between the second layout pattern  354   b  and the third layout pattern  354   c.    
     In operation  1032 , the second well layout pattern  316  is placed on the fourth layout level. In some embodiments, operation  1032  further includes placing the second well layout pattern  316  between the first layout pattern  354   a  and the second layout pattern  354   b . In some embodiments, operation  1032  further includes placing the second well layout pattern  316  below a third active region layout pattern  306   a  of the set of active region layout patterns  312   a  and a fourth active region  308   a  of the set of active region layout patterns  312   a.    
     In some embodiments, operation  1032  includes one or more of operations  1032   a  or  1032   b.    
     In some embodiments, operation  1032   a  includes placing the third layout pattern  356   a  below each of a third active region layout pattern  306   a  of the set of active region layout patterns  312   a  and a fourth active region  308   a  of the set of active region layout patterns  312   a.    
     In some embodiments, operation  1032   b  includes placing the fourth layout pattern  356   b  below each of active region layout pattern  306   b  of the set of active region layout patterns  312   a  and active region  308   b  of the set of active region layout patterns  312   a.    
     For simplicity, operations  1026 ′- 1032 ′ are discussed after the discussion of operations  1026 - 1032 . 
     In operation  1026 ′, a first well layout pattern  416  is generated. In some embodiments, the first well layout pattern  416  corresponds to fabricating a first well  502  of memory cell array  200 A- 200 B or integrated circuit  500 B. In some embodiments, the first well  502  has a first dopant type. In some embodiments, the first dopant type is a P-dopant type. In some embodiments, the first dopant type is an N-dopant type. 
     In some embodiments, operation  1026 ′ includes one or more of operations  1026   a ′ or  1026   b′.    
     In some embodiments, operation  1026   a ′ includes generating a first layout pattern (e.g., layout pattern  456   a  or  456   b ). In some embodiments, the first layout pattern  456   a  corresponds to fabricating a first portion  502   a  of the first well  502 . In some embodiments, the first layout pattern  456   a  extends in the second direction Y and is adjacent to the first side  452   a  of the layout design  400 B of memory cell  100 . 
     In some embodiments, operation  1026   b ′ includes generating a second layout pattern (e.g., layout pattern  456   c  or  456   d ). In some embodiments, the second layout pattern  456   c  corresponds to fabricating a second portion  502   b  of the first well  501 . In some embodiments, the second layout pattern  456   c  extends in the second direction Y and is adjacent to the second side  452   b   1  of the layout design  400 B of memory cell  100 . 
     In operation  1028 ′, the first well layout pattern  416  is placed on the fourth layout level. In some embodiments, operation  1028 ′ includes one or more of operations  1028   a ′ or  1028   b′.    
     In some embodiments, operation  1028   a ′ includes placing the first layout pattern  456   a  below the first active region layout pattern  404   a.    
     In some embodiments, operation  1028   b ′ includes placing the second layout pattern  456   c  below a first portion  410   a   1  of the second active region layout pattern  410   a.    
     In operation  1030 ′, a second well layout pattern  414  is generated. In some embodiments, the second well layout pattern  414  corresponds to fabricating a second well  502 ′ of memory cell array  200 A- 200 B or integrated circuit  500 B. In some embodiments, the second well  502 ′ has a second dopant type different from the first dopant type. In some embodiments, the second dopant type is an N-dopant type. In some embodiments, the second dopant type is a P-dopant type. 
     In some embodiments, operation  1030 ′ includes one or more of operations  1030   a ′ or  1030   b′.    
     In some embodiments, operation  1030   a ′ includes generating a third layout pattern (e.g., layout pattern  454   a  or  454   c ). In some embodiments, the third layout pattern  454   a  corresponds to fabricating a first portion  502   c  of the second well  502 ′. In some embodiments, the third layout pattern  454   a  extends in the second direction Y. 
     In some embodiments, operation  1030   b ′ includes generating a fourth layout pattern (e.g., layout pattern  454   b ). In some embodiments, the fourth layout pattern  454   b  corresponds to fabricating a second portion  502   d  of the second well  502 ′. In some embodiments, the fourth layout pattern  454   b  extends in the second direction Y and is adjacent to the second side  452   b   1  of the layout design  400 B of memory cell  100 . 
     In operation  1032 ′, the second well layout pattern  414  is placed on the fourth layout level. 
     In some embodiments, operation  1032 ′ includes one or more of operations  1032   a ′ or  1032   b′.    
     In some embodiments, operation  1032   a ′ includes placing the third layout pattern  454   a  between the first layout pattern  456   a  and at least the second layout pattern  456   c  or the fourth layout pattern  456   d . In some embodiments, operation  1032   a ′ includes placing the third layout pattern  454   a  below a third active region layout pattern  406   a  of the set of active region layout patterns  412   a  and a fourth active region  408   a  of the set of active region layout patterns  412   a.    
     In some embodiments, operation  1032   b ′ includes placing the fourth layout pattern  454   b  below a second portion  410   a   2  of the second active region layout pattern  410   a.    
     In some embodiments, one or more of operations  1002 - 1024 ,  1026 - 1032  or  1026 ′- 1032 ′ is not performed. 
     One or more of the operations of methods  1000  is performed by a processing device (e.g., processor  1202  ( FIG.  12   )) configured to execute instructions for generating a layout design (e.g., first layout design  300 A- 300 B, second layout design  400 A- 400 B or layout design  600 - 800 ). In some embodiments, first layout design  300 A- 300 B, second layout design  400 A- 400 B or layout design  600 - 800  are stored in a memory (e.g., a non-transitory computer-readable medium  1204  ( FIG.  12   )) as layout design  1216 . In some embodiments, one or more operations of methods  900 - 1000  is performed using a same processing device as that used in a different one or more operations of methods  900 - 1000 . In some embodiments, a different processing device is used to perform one or more operations of methods  900 - 1000  from that used to perform a different one or more operations of methods  900 - 1000 . 
     In some embodiments, method  1000  generates one or more layout designs (e.g., first layout design  300 A- 300 B, second layout design  400 A- 400 B or layout design  600 - 800 ) that occupy less area than other approaches. 
       FIG.  11    is a block diagram of an integrated circuit (IC) manufacturing system  1100 , and an IC manufacturing flow associated therewith, in accordance with at least one embodiment of the present disclosure. 
     In  FIG.  11   , IC manufacturing system  1100  includes entities, such as a design house  1120 , a mask house  1130 , and an IC manufacturer/fabricator (“fab”)  1140 , that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device  1160 . The entities in system  1100  are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house  1120 , mask house  1130 , and IC fab  1140  is owned by a single larger company. In some embodiments, two or more of design house  1120 , mask house  1130 , and IC fab  1140  coexist in a common facility and use common resources. 
     Design house (or design team)  1120  generates an IC design layout  1122 . IC design layout  1122  includes various geometrical patterns designed for an IC device  1160 . The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device  1160  to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout  1122  includes various IC features, such as an active region, gate electrode, source electrode and drain electrode, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house  1120  implements a proper design procedure to form IC design layout  1122 . The design procedure includes one or more of logic design, physical design or place and route. IC design layout  1122  is presented in one or more data files having information of the geometrical patterns. For example, IC design layout  1122  can be expressed in a GDSII file format or DFII file format. 
     Mask house  1130  includes data preparation  1132  and mask fabrication  1134 . Mask house  1130  uses IC design layout  1122  to manufacture one or more masks to be used for fabricating the various layers of IC device  1160  according to IC design layout  1122 . Mask house  1130  performs mask data preparation  1132 , where IC design layout  1122  is translated into a representative data file (“RDF”). Mask data preparation  1132  provides the RDF to mask fabrication  1134 . Mask fabrication  1134  includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The IC design layout  1122  is manipulated by mask data preparation  1132  to comply with particular characteristics of the mask writer and/or requirements of IC fab  1140 . In  FIG.  11   , mask data preparation  1132  and mask fabrication  1134  are illustrated as separate elements. In some embodiments, mask data preparation  1132  and mask fabrication  1134  can be collectively referred to as mask data preparation. 
     In some embodiments, mask data preparation  1132  includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout  1122 . In some embodiments, mask data preparation  1132  includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem. 
     In some embodiments, mask data preparation  1132  includes a mask rule checker (MRC) that checks the IC design layout that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout  1122  to compensate for limitations during mask fabrication  1134 , which may undo part of the modifications performed by OPC in order to meet mask creation rules. 
     In some embodiments, mask data preparation  1132  includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab  1140  to fabricate IC device  1160 . LPC simulates this processing based on IC design layout  1122  to create a simulated manufactured device, such as IC device  1160 . The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout  1122 . 
     It should be understood that the above description of mask data preparation  1132  has been simplified for the purposes of clarity. In some embodiments, data preparation  1132  includes additional features such as a logic operation (LOP) to modify the IC design layout  1122  according to manufacturing rules. Additionally, the processes applied to IC design layout  1122  during data preparation  1132  may be executed in a variety of different orders. 
     After mask data preparation  1132  and during mask fabrication  1134 , a mask or a group of masks are fabricated based on the modified IC design layout. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout. The mask can be formed in various technologies. In some embodiments, the mask is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, the mask is formed using a phase shift technology. In the phase shift mask (PSM), various features in the pattern formed on the mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication  1134  is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in the semiconductor wafer, in an etching process to form various etching regions in the semiconductor wafer, and/or in other suitable processes. 
     IC fab  1140  is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab  1140  is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business. 
     IC fab  1140  uses the mask (or masks) fabricated by mask house  1130  to fabricate IC device  1160 . Thus, IC fab  1140  at least indirectly uses IC design layout  1122  to fabricate IC device  1160 . In some embodiments, a semiconductor wafer  1142  is fabricated by IC fab  1140  using the mask (or masks) to form IC device  1160 . Semiconductor wafer  1142  includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). 
     Details regarding an integrated circuit (IC) manufacturing system (e.g., system  1100  of  FIG.  11   ), and an IC manufacturing flow associated therewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 20150278429, published Oct. 1, 2015, U.S. Pre-Grant Publication No. 20140040838, published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entireties of each of which are hereby incorporated by reference. 
       FIG.  12    is a block diagram of a system  1200  for designing an IC layout design in accordance with some embodiments. In some embodiments, system  1200  generates or places one or more IC layout designs described herein. System  1200  includes a hardware processor  1202  and a non-transitory, computer readable storage medium  1204  encoded with, i.e., storing, the computer program code  1206 , i.e., a set of executable instructions. Computer readable storage medium  1204  is configured for interfacing with manufacturing machines for producing the integrated circuit (e.g., memory cell array). The processor  1202  is electrically coupled to the computer readable storage medium  1204  via a bus  1208 . The processor  1202  is also electrically coupled to an I/O interface  1210  by bus  1208 . A network interface  1212  is also electrically connected to the processor  1202  via bus  1208 . Network interface  1212  is connected to a network  1214 , so that processor  1202  and computer readable storage medium  1204  are capable of connecting to external elements via network  1214 . The processor  1202  is configured to execute the computer program code  1206  encoded in the computer readable storage medium  1204  in order to cause system  1200  to be usable for performing a portion or all of the operations as described in method  900  or  1000 . 
     In some embodiments, the processor  1202  is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. 
     In some embodiments, the computer readable storage medium  1204  is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, the computer readable storage medium  1204  includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In some embodiments using optical disks, the computer readable storage medium  1204  includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD). 
     In some embodiments, the storage medium  1204  stores the computer program code  1206  configured to cause system  1200  to perform method  900  or  1000 . In some embodiments, the storage medium  1204  also stores information needed for performing method  900  or  1000  as well as information generated during performing method  900  or  1000 , such as layout design  1216  and user interface  1218 , and/or a set of executable instructions to perform the operation of method  900  or  1000 . In some embodiments, layout design  1216  comprises one or more of layout designs  300 A,  300 B,  400 A,  400 B or  600 - 800 . 
     In some embodiments, the storage medium  1204  stores instructions (e.g., computer program code  1206 ) for interfacing with manufacturing machines. The instructions (e.g., computer program code  1206 ) enable processor  1202  to generate manufacturing instructions readable by the manufacturing machines to effectively implement method  900  or  1000  during a manufacturing process. 
     System  1200  includes I/O interface  1210 . I/O interface  1210  is coupled to external circuitry. In some embodiments, I/O interface  1210  includes a keyboard, keypad, mouse, trackball, trackpad, and/or cursor direction keys for communicating information and commands to processor  1202 . 
     System  1200  also includes network interface  1212  coupled to the processor  1202 . Network interface  1212  allows system  1200  to communicate with network  1214 , to which one or more other computer systems are connected. Network interface  1212  includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interface such as ETHERNET, USB, or IEEE-1394. In some embodiments, method  900  or  1000  is implemented in two or more systems  1200 , and information such as layout design, and user interface are exchanged between different systems  1200  by network  1214 . 
     System  1200  is configured to receive information related to a layout design through I/O interface  1210  or network interface  1212 . The information is transferred to processor  1202  by bus  1208  to determine a layout design for producing one or more of memory cell  100 , memory cell array  200 A or  200 B or memory cell array  500 A or  500 B. The layout design is then stored in computer readable medium  1204  as layout design  1216 . System  1200  is configured to receive information related to a user interface through I/O interface  1210  or network interface  1212 . The information is stored in computer readable medium  1204  as user interface  1218 . 
     In some embodiments, method  900  or  1000  is implemented as a standalone software application for execution by a processor. In some embodiments, method  900  or  1000  is implemented as a software application that is a part of an additional software application. In some embodiments, method  900  or  1000  is implemented as a plug-in to a software application. In some embodiments, method  900  or  1000  is implemented as a software application that is a portion of an EDA tool. In some embodiments, method  900  or  1000  is implemented as a software application that is used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of the integrated circuit device or memory cell array. In some embodiments, the layout is stored on a non-transitory computer readable medium. In some embodiments, the layout is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. In some embodiments, the layout is generated based on a netlist which is created based on the schematic design. In some embodiments, method  900  or  1000  is implemented by a manufacturing device to manufacture an integrated circuit (e.g., memory cell  100  or memory cell array  300 A- 300 B,  400 A- 400 B,  600 - 800  or  500 A- 500 H) using a set of masks manufactured based on one or more layout designs (e.g., layout design  300 A,  300 B,  400 A,  400 B or  600 - 800 ) generated by system  1200 . 
     System  1200  of  FIG.  12    generates layout designs (e.g., layout design  300 A,  300 B,  400 A,  400 B or  600 - 800 ) of memory cell  100 , memory cell array  200 A or  200 B or memory cell array  500 A or  500 B that occupy less area than other approaches. 
     One aspect of this description relates to a method of forming a memory cell array. In some embodiments, the method includes generating a first set of tiles extending in a first direction, generating a second set of tiles extending in the first direction, and manufacturing the memory cell array based on at least the first layout design. In some embodiments, the generating the first set of tiles includes generating a first layout design of a first set of memory cells, each tile of the first set of tiles corresponds to the first layout design of the first set of memory cells, each tile of the first set of tiles is offset from an adjacent tile of the first set of tiles in a second direction different from the first direction, and each tile of the first set of tiles includes at least a first corner notch. In some embodiments, the generating the second set of tiles includes generating a second layout design of a second set of memory cells, each tile of the second set of tiles corresponds to the second layout design of the second set of memory cells, each tile of the second set of tiles is offset from an adjacent tile of the second set of tiles in the second direction, and each tile of the second set of tiles includes at least a second corner notch. In some embodiments, each first corner notch is flush with each second corner notch, each tile of the first set of tiles extends in a third direction different from the first direction and the second direction, the first set of tiles and the second set of tiles alternate with each other in the second direction, and each tile of the second set of tiles extends in the third direction, and at least one of the above generating operations is performed by a hardware processor, and the first layout design is stored in a non-transitory computer-readable medium. 
     Another aspect of this description relates to a method of forming a memory cell array having a first set of memory cells. The method includes generating, by a processor, a layout design of the memory cell array, the layout design corresponding to a tile having a first corner notch and a second corner notch, and manufacturing the memory cell array based on the layout design. In some embodiments, the generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of the memory cell array, the first active region layout pattern extending between the first corner notch and the second corner notch, and being adjacent to a first side of a memory cell of the first set of memory cells; and generating a second active region layout pattern corresponding to fabricating a second active region of the memory cell array, the second active region layout pattern being adjacent to a second side of the memory cell opposite from the first side of the memory cell, the second active region layout pattern being separated from the first active region layout pattern in a first direction, the first active region layout pattern and the second active region layout pattern extending in a second direction and being located on a first layout level. In some embodiments, at least one of the above layout patterns is stored in a non-transitory computer-readable medium, and at least one of the above generating operations is performed by a hardware processor. 
     Still another aspect of this description relates to a memory cell array. In some embodiments, the memory cell array includes a first memory cell arranged in a first row in a first direction, a second memory cell arranged in a second row in the first direction, and being separated from the first memory cell in a second direction different from the first direction, a first word line extending in the first direction, and being coupled to the first memory cell, a second word line extending in the first direction, and being coupled to the second memory cell, and a first bit line extending in the second direction, and being coupled to the first memory cell and the second memory cell. In some embodiments, the first memory cell corresponds to a five transistor (5T) memory cell. In some embodiments, the first memory cell includes a first active region having a first length in the second direction, and a second active region having a second length in the second direction and being different from the first length. In some embodiments, the first active region and the second active region extending in the second direction, being located on a first level and being separated from each other in the first direction. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.