Patent Publication Number: US-2023155502-A1

Title: Multilevel self-balance control circuit, dc/dc conversion system and ac/dc conversion system

Description:
RELATED APPLICATIONS 
     This application claims the benefit of Chinese Patent Application No. 202111341819.0, filed on Nov. 12, 2021, which is incorporated herein by reference in its entirety. 
     FIELD OF THE INVENTION 
     The present invention generally relates to the field of power electronics, and more particularly to multilevel self-balance control circuits, and DC/DC and AC/DC conversion systems. 
     BACKGROUND 
     A switched-mode power supply (SMPS), or a “switching” power supply, can include a power stage circuit and a control circuit. When there is an input voltage, the control circuit can consider internal parameters and external load changes, and may regulate the on/off times of the switch system in the power stage circuit. Switching power supplies have a wide variety of applications in modern electronics. For example, switching power supplies can be used to drive light-emitting diode (LED) loads. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a schematic diagram of an example multilevel self-balance control circuit, in accordance with embodiments of the present invention. 
         FIG.  2    is another schematic diagram of the example multilevel self-balance control circuit, in accordance with embodiments of the present invention. 
         FIG.  3    is a schematic diagram of a first example implementation of a multilevel self-balance control circuit, in accordance with embodiments of the present invention. 
         FIG.  4    is a schematic diagram of an example control unit, in accordance with embodiments of the present invention. 
         FIG.  5    is a schematic diagram of an example self-balance voltage three-level flying capacitor architecture based on the BUCK topology, in accordance with embodiments of the present invention. 
         FIG.  6    is a waveform diagram of an example operation of a self-balance three-level flying capacitor architecture based on the BUCK topology under a condition that the rear-stage synchronizes the front stage once a cycle in the balanced state, in accordance with embodiments of the present invention. 
         FIG.  7    is a waveform diagram of an example operation of a self-balance three-level flying capacitor architecture based on the BUCK topology under a condition that the rear-stage synchronizes the front stage once a cycle in the unbalanced state, in accordance with embodiments of the present invention. 
         FIG.  8    is a schematic diagram of a second example implementation of a multilevel self-balance control circuit, in accordance with embodiments of the present invention. 
         FIG.  9    is a schematic diagram of another example implementation of the control unit, in accordance with embodiments of the present invention. 
         FIG.  10    is a schematic diagram of an example self-balance three-level flying capacitor architecture based on the BOOST topology, in accordance with embodiments of the present invention. 
         FIG.  11    is a schematic diagram of the example driving waveform of the self-balance three-level flying capacitor architecture based on the BOOST topology under a condition that the rear-stage synchronizes the front stage once a cycle in the balanced state, in accordance with embodiments of the present invention. 
         FIG.  12    is a schematic diagram of the example driving waveform of the self-balance three-level flying capacitor architecture based on the BOOST topology under a condition that the rear-stage synchronizes the front stage once a cycle in the unbalanced state, in accordance with embodiments of the present invention. 
         FIG.  13    is a schematic diagram of a third example implementation of a multilevel self-balance control circuit, in accordance with embodiments of the present invention. 
         FIG.  14    is a schematic diagram of an example self-balance three-level flying capacitor architecture based on the DCX(DC transformer)-LLC topology, in accordance with embodiments of the present invention. 
         FIG.  15    is a waveform diagram of example operation of the self-balance three-level flying capacitor architecture based on the DCX-LLC topology under a condition that the rear-stage synchronizes the front stage once a cycle in the unbalanced state, in accordance with embodiments of the present invention. 
         FIG.  16    is a waveform diagram of an example control of the N-level self-balance flying capacitor architecture, in accordance with embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Reference may now be made in detail to particular embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention may be described in conjunction with the preferred embodiments, it may be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it may be readily apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, processes, components, structures, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention. 
     DC/DC converters are widely used in rail transit, electric power, energy storage, high-power transmission, and other fields. Voltage divider units are indispensable parts of a DC/DC converter. In a voltage divider unit, in order to ensure normal circuit operations, it is necessary to meet balancing requirements. The balancing problems are often difficult to solve, which may require a significant number of samples in voltage signals or current signals, with implementations of control strategies in voltage/current balancing. As a result, the complexity and cost of the system can accordingly be increased. 
     In particular embodiments, the balancing problem of a voltage divider unit can be addressed by connecting an active load on the output side of the voltage divider unit, satisfying that the power flowing through the active load is positively correlated with the current power output by the front-stage circuit, and achieving the linkage control of the front-stage circuit and the rear-stage active load to achieve automatic balancing of the front-stage circuit. 
     As shown in  FIG.  1   , the front-stage circuit can be a voltage divider to be balanced, the rear-stage active load a controlled load network, and the rear-stage active load may present a negative feedback characteristic. This can automatically realize the voltage-balancing control of the front-stage circuit, and also realize the power change of the rear-stage active load. The front-stage circuit and the rear-stage active load can be under linkage control, and the control signal can be generated by the front-stage circuit and synchronized with switches of the rear-stage active load. Conversely, control signals may also be generated from the rear-stage active load, and synchronized with switches of the front-stage circuit. 
     As shown in  FIG.  2   , when the front-stage circuit is a voltage divider unit  11 , the rear-stage active load is a voltage-controlled charge source load  12 . In this particular example, voltage divider unit  11  can include switches and capacitors. Any suitable voltage divider circuit structure implemented by a combination of switches and capacitors can be utilized in certain embodiments. The front-stage circuit and the rear-stage active load may be controlled by control unit  13  to ensure that the total amount of charge flowing through the rear-stage active load is positively correlated with the output voltage of the current front-stage circuit within the period of each working state. That is, when the output voltage of the front-stage circuit increases, the total amount of charge flowing into the rear-stage active load can be increased. Conversely, when the output voltage of the front-stage circuit decreases, the total amount of charge flowing into the rear-stage active load may be decreased. 
     As shown in  FIGS.  2 - 7   , a multilevel self-balance control circuit is provided, and the multilevel self-balance control circuit can include voltage divider unit  11 , voltage-controlled charge source load  12 , and control unit  13 . As shown in  FIGS.  2  and  3   , voltage divider unit  11  may receive and divide input voltage Vin. As shown in  FIG.  3   , voltage divider unit  11  can be a flying capacitor converter. The flying capacitor converter can include N−1 stages of basic modules  111  cascaded sequentially. Each of the basic modules  111  can include a capacitor, a first switch, and a second switch. One terminal of the first switch in one of the stages can connect to the upper plate of a capacitor, and another terminal of the first switch can connect to the upper plate of a capacitor in the previous stage. The control terminal of the first switch can connect to a switch control signal. One terminal of the second switch of the present stage can connect to a lower plate of the present capacitor, and the other terminal of the second switch can connect to a lower plate of a capacitor in the previous stage. The control terminal of the second switch can connect to the switch control signal. 
     In particular embodiments, the first and second switches can be implemented by metal-oxide-semiconductor (MOS) transistors. Any devices that can be used as power switches may be selected for implementation in certain embodiments. The first and second switches in the same basic module can be complementarily conducted, and the basic modules at all stages are under phase-shifted control. That is, switch control signals for the first switches of all stages in the basic modules can be successively phase shifted with a preset angle, and switch control signals for the second switches of all stages in the basic modules can be in turn phase shifted with the preset angle. For example, N is an integer greater than or equal to 3. The voltages VC 1 −VC(N−1) across the capacitors in the first stage to the (N−1)th stage can respectively be Vin/(N−1), 2Vin/(N−1), . . . Vin. The withstand voltage of the switches in each stage of the basic module can be the voltage difference between the capacitors in the adjacent two modules; that is, Vin/(N−1). Therefore, the topology of the flying capacitor converter can reduce the voltage stress of the switches, such that low-voltage components can be used to meet the application requirements of high-voltage applications. The voltage balance effect of the flying capacitor converter may significantly affect the system performance. If the voltages are poorly balanced, the stress on the MOS transistors can be increased, which may cause damages and failures of the MOS transistors. Any suitable voltage divider circuit structure that requires balance control can be utilized in certain embodiments. 
     As shown in  FIGS.  2  and  3   , voltage-controlled charge source load  12  can connect to the output terminal of voltage divider unit  11 . The input charge amount of voltage-controlled charge source load  12  may be adjusted based on the output voltage of the voltage divider  11  adaptively, such that the total amount of charge flowing through voltage-controlled charge source load  12  within the period of each working state of voltage divider unit  11  is positively correlated with output voltage Vmid of voltage divider unit  11 . The balance control of voltage divider unit  11  can be achieved by negative feedback. 
     In the example of  FIG.  3   , voltage-controlled charge source load  12  may be a BUCK circuit. The BUCK circuit can include power transistor M 1 , power transistor M 2 , inductor L 1 , capacitor Co 1 , and load R 1 . In particular embodiments, each power transistor may be implemented by N-type metal oxide semiconductor (NMOS); however, other devices can alternatively be utilized in certain embodiments. The drain of power transistor M 1  can connect to the output of voltage divider unit  11 , with the gate receiving switch control signal SH. The source of power transistor M 1  can connect to the drain of power transistor M 2 . The gate of power transistor M 2  may receive switch control signal SL, with the source grounded. One terminal of inductor L 1  can connect to the source of power transistor M 1  (the drain of power transistor M 2 ), and the other terminal thereof can be coupled to the ground via capacitor Co 1 . The load R 1  can connect in parallel with capacitor Co 1 , and power transistors M 1  and M 2  may be complementarily conducted. 
     Any circuit structure capable of changing the amount of input charges based on the output voltage of voltage divider unit  11 , and thereby achieving negative feedback to meet the characteristics of the voltage-controlled charge source, can be utilized in certain embodiments. As shown in  FIGS.  3  and  4   , control unit  13  may generate control signals for voltage divider unit  11  and voltage-controlled charge source load  12 , thereby controlling voltage divider unit  11  and voltage-controlled charge source load  12  in linkage. 
     In particular embodiments, control unit  13  can control voltage-controlled charge source load  12  to operate in a critical conduction mode with a constant on-time (COT) control, and synchronously generate switch control signals to voltage divider unit  11  based on control signals for voltage-controlled charge source load  12 . For example, control unit  13  may utilize a dual closed-loop COT control under the critical conduction mode. Here, the critical conduction mode is a valley current mode. Control unit  13  can include zero-crossing detection module  131 , on-time control module  132 , trigger  133 , and voltage divider control module  134 . Zero-crossing detection module  131  can detect a zero-crossing point of the inductor (e.g., inductor L 1 ) current in voltage-controlled charge source load  12 , and may generate a turn-on signal for a main switch in voltage-controlled charge source load  12 . On-time control module  132  can connect to the output terminal of zero-crossing detection module  131  and may receive an on-time control signal generated based on the difference between output voltage Vo of voltage-controlled charge source load  12 , and reference voltage Vref. 
     In particular embodiments, output voltage Vo can be acquired by a voltage outer loop, and subtracted from reference voltage Vref to obtain an error signal. The error signal can be passed through a proportional integral (PI) compensation network to generate the on-time control signal, which may represent an expected value of the duration of the on-time. The duration of the on-time can be timed from the zero-crossing point of the inductor until reaching the time represented by the on-time control signal; thus, a turn-off signal for the main switch may be generated. The input terminal of trigger  133  can connect to the output terminals of zero-crossing detection module  131  and on-time control module  132  to receive the turn-on signal and turn-off signal to generate the control signal. When the inductor current crosses zero, the turn-on signal for a main switch (e.g., power transistor M 1 ) can be activated. When the main switch is on, the inductor can be in the energy storage state. 
     When the duration of on-time reaches the value represented by the on-time control signal, the turn-off signal for the main switch can be activated. In stable operation, the output voltage may be constant, so the on-time can be constant. For example, trigger  133  can include an RS flip-flop. The set terminal S of the RS flip-flop can connect to the output terminal of zero-crossing detection module  131 , reset terminal R can connect to the output terminal of on-time control module  132 , non-inverting output terminal Q can connect to the gate of power transistor M 1  to generate the switch control signal SH for power transistor M 1 , and inverting output terminal Q′ can connect to the gate of power transistor M 2  to generate switch control signal SL for power transistor M 2 . For example, the turn-on signal for the main switch in BUCK circuit may also be a driving signal for synchronizing the front-stage flying capacitor converter. Voltage divider control module  134  can connect to the output terminal of zero-crossing detection module  131 , synchronously generating the switch control signal for voltage divider unit  11  based on the zero-crossing detection signal. It should be understood that voltage divider control module  134  can also be coupled to one of the output terminals of trigger  133 . For example, voltage divider control module  134  can be implemented by a state machine. 
     In particular embodiments, control unit  13  may be disposed in the rear-stage active load, and the front-stage control signal synchronized by the rear-stage control signal. For example, control unit  13  can synchronously generate switch control signals to voltage divider unit  11  based on the control signal for voltage-controlled charge source load  12 . In some applications, control unit  13  may also be disposed in the front-stage circuit. In this case, control unit  13  in the front-stage circuit can detect the output of the rear-stage circuit to adjust the duration of the on-time, and may pass the signal to the rear-stage active load to control the on-time of the switch in the rear-stage active load. Since the valley current of the rear-stage active load can be required to be consistent, a turn-on signal for the rear-stage active load main switch may be generated by the rear-stage active load itself. The turn-on signal can be passed to the front-stage circuit for triggering the switching of the working state of the front-stage circuit, thereby forming switch control signals of the front-stage circuit. The control signals for the rear-stage active load (or front-stage circuit) can be synchronized with the control signals for the front-stage circuit (or the rear-stage active load) once per cycle, or periodically synchronized every M cycles, where M is an integer greater than 1. 
     A self-voltage-balancing three-level flying capacitor architecture based on the BUCK topology, is shown as an example to further illustrate the working principle of the multilevel self-balance control circuit of the present disclosure.  FIG.  5    shows a self-balance voltage three-level flying capacitor architecture based on the BUCK topology, in accordance with embodiments of the present invention.  FIG.  6    shows a schematic diagram of the driving waveform of the self-balance three-level flying capacitor architecture based on the BUCK topology under a condition that the rear-stage synchronizes the front stage once a cycle in the balanced state, in accordance with embodiments of the present invention. In the carrier phase-shifted control, switch control signals S 1   a  and S 1   b  can be mutually complementary, and switch control signals S 2   a  and S 2   b  may be mutually complementary. For example, switch control signal S 1   a  can be phase shifted from the switch control signal S 2   a  by 180°, and the duty cycles of all switches can be 0.5. 
     The switch control signals for the front-stage circuit may be synchronized with the turn-on signal for the main switch in the rear-stage BUCK circuit. Since the duty cycle of the flying capacitor converter is only 0.5, there can be N−1 working states in the flying capacitor converter including N−1 basic modules. In this example, there are two working states for the three-level flying capacitor converter (N=3). In the case of working state  1 , switch control signals S 1   a  and S 2   b  can be active, where capacitor C 1  is in a discharge mode. When in working state  2 , switch control signals S 1   b  and S 2   a  can be active, and capacitor C 1  may be in a charging mode. The BUCK circuit features as a voltage-controlled charge source when under both constant-on-time and valley current control. The duration of the on-time of the BUCK circuit can be determined by the outer loop voltage loop, and the turn-on signal decided by a zero-crossing detection (ZCD). When the inductor current crosses zero, the turn-on signal can be generated to turn on the main switch, and when the on-time reaches the expected value, a turn-off signal may be generated to turn off the main switch. The three-level flying capacitor converter can be synchronously triggered at the rising edge of the turn-on signal for the main switch to start the carrier phase-shifted control. That is, the three-level flying capacitor converter may complete the switching of the working states once within one switching cycle of the BUCK circuit. At every rising edge of the turn-on signal for the main switch, the working state of the three-level flying capacitor converter can be synchronously switched. 
     For example, when voltage VC 1  across capacitor C 1  is unbalanced (that is, VC 1 ≠½ Vin), such as when VC 1  is higher, the principle of the voltage-balancing is as follows. As shown in  FIG.  7   , when capacitor C 1  is in the discharge mode (State=1, the switch control signals S 2   b  and S 1   a  are active), voltage Vmid=VC 1 , which is higher than the balance point. Since the output voltage is constant, the on-time is constant, and thus the discharge amount of capacitor C 1  is increased (the area of the dotted triangle region is increased). On the other hand, when capacitor C 1  is in the charge mode (State=2, the switch control signals S 2   a  and S 1   b  are active), voltage Vmid=Vin−VC 1 , which is lower than the balance point. The charges provided into capacitor C 1  can be decreased (the area of the linear triangle region is decreased). That is, when the voltage of capacitor C 1  is higher than the balance point, the charging amount of capacitor C 1  may be less than the discharge amount. With gradually accumulation over time, the voltage of capacitor C 1  can be stabilized at the predetermined voltage level due to the negative feedback effect, thereby achieving voltage balancing. When the voltage of capacitor C 1  is lower than the balance point, the operations are likewise. 
     As shown in  FIGS.  2  and  8 - 12   , the present invention provides an embodiment of a multilevel self-balance control circuit comprising: voltage divider unit  11 , voltage-controlled charge source load  12 , and control unit  13 . As shown in  FIGS.  2  and  8   , voltage divider unit  11  may receive input voltage Vin, and divide input voltage Vin. For example, voltage divider unit  11  may utilize a flying capacitor converter. As shown in  FIGS.  2  and  8   , voltage-controlled charge source load  12  can connect to the output terminal of voltage divider unit  11 . The amount of input charges to voltage-controlled charge source load  12  may be adjusted based on the output voltage of the voltage divider  11 . Thus, the total amount of charges flowing through voltage-controlled charge source load  12  within the period of each working state of voltage divider unit  11  can be positively correlated with output voltage Vmid of voltage divider unit  11 , and a negative feedback loop may be formed to achieve balance control of voltage divider unit  11 . 
     In the example of  FIG.  8   , voltage-controlled charge source load  12  is a BOOST circuit. The BOOST circuit can include power transistor M 3 , power transistor M 4 , inductor L 2 , capacitor Co 2 , and load R 2 . For example, each power transistor may be implemented by NMOS. One terminal of inductor L 2  can connect to the output terminal of voltage divider unit  11 , and the other terminal of inductor L 2  can connect to the drain of power transistor M 3 . The gate of power transistor M 3  may receive switch control signal SL, whereas the source of power transistor M 3  is grounded. The source of power transistor M 4  can connect to the drain of power transistor M 3 , the gate of power transistor M 4  may receive switch control signal SH, and the drain of power transistor M 4  can be coupled to the ground through capacitor Co 2 . The load R 2  can connect in parallel with capacitor Co 2 , and power transistors M 3  and M 4  may be complementarily conducted. 
     Any circuit structure capable of changing the amount of input charges based on the output voltage of voltage divider unit  11 , and thereby achieving negative feedback to meet the characteristics of the voltage-controlled charge source can be utilized in certain embodiments. As shown in  FIGS.  8  and  9   , control unit  13  may respectively generate control signals for voltage divider unit  11  and voltage-controlled charge source load  12 , thereby controlling voltage divider unit  11  and voltage-controlled charge source load  12  in linkage. 
     In particular embodiments, control unit  13  can control voltage-controlled charge source load  12  to operate in a critical conduction mode, e.g., the peak current control mode, and may synchronously generate switch control signals to voltage divider unit  11  based on control signals for voltage-controlled charge source load  12 . For example, control unit  13  employs a dual closed-loop peak current control mode. Control unit  13  can include zero-crossing detection module  135 , comparison module  136 , trigger  137 , and voltage divider control module  138 . Zero-crossing detection module  135  can detect a zero-crossing point of the current of the inductor (e.g., inductor L 2 ) in voltage-controlled charge source load  12 , and may generate a turn-on signal for a main switch in voltage-controlled charge source load  12 . Comparison module  136  can compare internal loop peak reference current ipkref against inductor current iL to outputs a turn-off signal for the main switch. For example, output voltage Vo may be acquired by a voltage outer loop, an error signal is obtained by subtracting output voltage Vo from a reference voltage Vref, and the error signal passed through a proportional integral (PI) compensation network to generate the internal loop peak reference current. The input terminal of trigger  137  can connect to the output terminals of the zero-crossing detection module  135  and comparison module  136  to receive the turn-on signal and turn-off signal, in order to generate the control signal. 
     When the inductor current crosses zero, the turn-on signal for the main switch can be activated. When the inductor current reaches the internal loop peak reference current, the turn-off signal for the main switch (e.g., power transistor M 3 ) may be activated. When the main switch is on, the inductor is in the energy storage state. For example, trigger  137  is implemented by RS flip-flop. The set terminal S of the RS flip-flop can connect to the output terminal of the zero-crossing detection module  135 . Reset terminal R can connect to the output terminal of comparison module  136 . The non-inverting output terminal Q can connect to the gate of power transistor M 3  to generate switch control signal SL for power transistor M 3 , and inverting output terminal Q′ can connect to the gate of power transistor M 4  to generate switch control signal SH for power transistor M 4 . Voltage divider control module  138  can connect to the output terminal of trigger  137  (non-inverting output terminal or inverting output terminal), and may synchronously generate switch control signals to voltage divider unit  11  based on the output signals from trigger  137 . It should be understood that voltage divider control module  138  can also be coupled to the output terminal of the zero-crossing detection module  135 . In one example, voltage divider control module  138  is implemented by a state machine. 
     It is to be noted that the front-stage circuit may be synchronized by the rear-stage active load. On the other hand, the rear-stage active load can also be synchronized by the front-stage circuit. The synchronization may be performed once per cycle, or it can be synchronized every M cycles, where M is an integer greater than 1. A self-voltage-balancing three-level flying capacitor architecture based on the BOOST topology is served as an example to further illustrate the working principle of the multilevel self-balance control circuit of the present disclosure.  FIG.  10    shows a self-balance three-level flying capacitor architecture based on the BOOST topology, in accordance with embodiments of the present invention.  FIG.  11    shows a schematic diagram of the driving waveform of the self-balance three-level flying capacitor architecture based on the BOOST topology under a condition that the rear-stage synchronizes the front stage once a cycle in the balanced state, in accordance with embodiments of the present invention. When voltage VC 1  across capacitor C 1  is balanced (e.g., VC 1 =½ Vin), Vmid can be a constant voltage with a value of Vin/(N−1), and for a three-level flying capacitor circuit, Vmid=Vin/2. 
     When voltage VC 1  across capacitor C 1  is unbalanced (e.g., VC 1  ½ Vin), automatic voltage balancing can be achieved if Vmid&gt;½ Vo. As shown in  FIG.  13   , when VC 1  is higher than a balance point, the principle of the voltage-balancing is as follows. When capacitor C 1  is in the discharge mode (e.g., switch control signals S 2   b  and S 1   a  are active), voltage Vmid=VC 1  can be over the balance point. According to the volt-second equilibrium of Boost circuit, it can be deduced that when voltage Vmid&gt;½ Vo, the switching period of the Boost circuit increases. Since the peak current remains constant under the stable operation, the discharge amount of capacitor C 1  can be increased. That is, the area of the dotted triangle region is increased. On the other hand, when capacitor C 1  is in the charging mode (e.g., when switch control signals S 2   a  and S 1   b  are active), voltage Vmid=Vin−VC 1  may be below the balance point, resulting in a decrease in the charging amount of capacitor C 1 . That is, the area of the linear triangle region can be decreased. Therefore, when the voltage of capacitor C 1  exceeds the balance point, the voltage of capacitor C 1  eventually gets stabilized at the rated voltage due to the negative feedback effects, in order to achieve voltage balance. In the event that the voltage of capacitor C 1  is lower than the balance point, analogous operations can occur. 
     As shown in  FIGS.  2  and  13 - 15   , an example multilevel self-balance control circuit can include voltage divider unit  11 , voltage-controlled charge source load  12 , and control unit  13 . As shown in  FIGS.  2  and  13   , voltage divider unit  11  may receive an input voltage Vin and divides input voltage Vin. For example, voltage divider unit  11  may employ a flying capacitor converter as described above. As shown in  FIGS.  2  and  13   , voltage-controlled charge source load  12  can connect to the output terminal of voltage divider unit  11 . The amount of input charges to voltage-controlled charge source load  12  may be adaptively adjusted based on the output voltage of voltage divider unit  11 . Thus, the total amount of charges flowing through voltage-controlled charge source load  12  within the period of each working state of voltage divider unit  11  can be positively correlated with the output voltage of voltage divider unit  11 . Balance control of voltage divider unit  11  may thereby by achieved by a negative feedback loop. 
     As shown in the example of  FIG.  13   , voltage-controlled charge source load  12  is a DCX-LLC circuit (DC conversion circuit with a transformer based on LLC resonance). For example, the DCX-LLC circuit can include power transistor M 5 , power transistor M 6 , inductor L 3 , capacitor Co 3 , transformer, rectifier module  121 , capacitor C 4 , and load R 3 . In this particular example, each power transistor may be implemented using NMOS. The drain of power transistor M 5  can connect to the output terminal of voltage divider unit  11 . The gate of power transistor M 5  may receive switch control signal SH, and the source of power transistor M 5  can connect to the drain of power transistor M 6 . The gate of power transistor M 6  may receive switch control signal SL, whereas the source of power transistor M 6  may be grounded. One terminal of inductor L 3  can connect to the source of power transistor M 5 , and the other terminal can be coupled to the ground via the primary coil of the transformer and capacitor C 4 . The secondary coil of the transformer can connect to the input terminal of the rectifier module  121 . Capacitor Co 3  and load R 3  can connect in parallel between the two output terminals of the rectifier module  121 , and power transistors M 5  and M 6  may be complementarily operated. 
     Any circuit structure capable of changing the amount of input charges based on the output voltage of voltage divider unit  11 , and thereby achieving negative feedback to meet the characteristics of the voltage-controlled charge source can be utilized in certain embodiments. As shown in  FIGS.  2  and  13   , the control unit may generate control signals for voltage divider unit  11  and voltage-controlled charge source load  12 , and can control voltage divider unit  11 , and voltage-controlled charge source load  12  in linkage. In particular embodiments, control unit  13  can control voltage-controlled charge source load  12  under a constant frequency control mode, and may synchronously generate switch control signals to voltage divider unit  11  based on the control signals for voltage-controlled charge source load  12 . Any control circuit structure capable of achieving a fixed frequency control mode can be utilized in certain embodiments. It is to be noted that the front-stage circuit may be synchronized by the rear-stage active load. On the other hand, the rear-stage active load can also be synchronized by the front-stage circuit. The synchronization may be performed once per cycle, or it can be synchronized every M cycles, where M is an integer greater than 1. 
     A self-voltage-balancing three-level flying capacitor architecture based on the DCX-LLC topology is served as an example to further illustrate the working principle of the multilevel self-balance control circuit of particular embodiments.  FIG.  14    shows a self-balance three-level flying capacitor architecture based on the DCX-LLC topology. For example, voltage VC 1  across capacitor C 1  is higher, the balancing process can be shown in  FIG.  16   . When capacitor C 1  is in the discharge mode, voltage Vmid=VC 1  exceeds the balance point. Consequently, the rear-stage LLC resonant current increases, resulting in a higher discharge amount. That is, the area of the linear region may be increased. When capacitor C 1  is in the charging mode, voltage Vmid=Vin−VC 1  can go below the balance point. In this case, the rear-stage LLC resonant current can decrease, resulting in less charging amount. That is, the area of the dot-shaped region is reduced. Eventually, a negative feedback loop may be formed to achieve voltage balancing of the front-stage circuit. When the voltage of capacitor C 1  is below the balance point, same principle of operation is applicable as discussed. 
     In particular embodiments, circuitry is not limited to the BUCK circuit, the Boost circuit, or the DCX-LLC circuit, as shown. Further, the control strategy is not limited to the COT-controlled critical conduction mode, the peak-current controlled critical conduction mode, or the fixed-frequency control mode. The relationships between the topology circuits and the control strategies are not limited to the correspondences exemplified herein, and various suitable implementations can be supported in certain embodiments. Particular embodiments may not require a complex control algorithm to achieve automatic voltage balancing of the system. Rather, the amount of charges input to the rear-stage active load can be changed based on the output voltage Vmid of the front-stage circuit, thereby forming a negative feedback loop to balance the voltages of the capacitors in the front-stage circuit. Regarding a more general N-level self-voltage-balancing flying capacitor architecture, the control waveform can be as shown in  FIG.  16   . For example, the front-stage circuit has a total of N−1 different working states. The turn-on signal of the rear-stage BUCK circuit can synchronize the switching of the working states of the front-stage circuit. In another example, the turn-on signal of the rear-stage active load can be used to synchronize the front-stage circuit once every N cycles. 
     Particular embodiments may provide a DC/DC conversion system that can include a DC power supply and a multilevel self-balance control circuit, as described herein. The DC power supply can be coupled to the input of the multilevel self-balance control circuit. Particular embodiments may also provide an AC/DC conversion system that can include an AC power supply, a rectifier circuit, and a multilevel self-balance control circuit, as described herein. The input terminal of the rectifier circuit can be coupled to the AC power supply, and the output coupled to the input terminal of the multilevel self-balance control circuit. 
     In particular embodiments, a multilevel self-balance control circuit, a DC/DC conversion system, and an AC/DC conversion system, may be provided. The multilevel self-balance control circuit can include: a voltage divider unit, which may receive and divide an input voltage; a voltage-controlled charge source load coupled to the output terminal of the voltage divider unit, and adaptively adjusting the amount of charges input to the voltage-controlled charge source load based on the output voltage of the voltage divider unit. Thus, a total amount of charges flowing through the voltage-controlled charge source load during the period of each working state of the voltage divider unit may be positively correlated with the output voltage of the voltage divider unit, and the balance control of the voltage divider unit can thereby be realized by a negative feedback loop. The multilevel self-balance control circuit can also include the control unit, which can generate the control signals for the voltage divider unit and the voltage-controlled charge source load, and control the voltage divider unit and the voltage-controlled charge source load in linkage. In the multilevel self-balance control circuit, the DC/DC conversion system, and the AC/DC conversion system of particular embodiments, an active load can be coupled to the output side of the voltage divider unit, and the power flowing through the active load may be positively correlated with the output power of the current voltage divider unit. Thus, automatic balancing of the voltage divider unit may be realized by a negative feedback loop. The front-stage circuit and the rear-stage active load can be simultaneously controlled to reduce the need for current or voltage sampling and control, thereby saving system cost and reducing system complexity. 
     The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with modifications as are suited to particular use(s) contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.