Patent Publication Number: US-9412302-B2

Title: Pixel driving circuit, driving method, array substrate and display apparatus

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is the National Stage of PCT/CN2014/085823 filed on Sep. 3, 2014, which claims priority under 35 U.S.C. §119 of Chinese Application No. 201410184466.1 filed on May 4, 2014, the disclosure of which is incorporated by reference. 
     TECHNICAL FIELD 
     The present disclosure relates to a pixel driving circuit, a driving method, an array substrate and a display apparatus. 
     BACKGROUND 
     An organic light emitting display (AMOLED) is a hot topic in the present flat panel display research field. Compared with a liquid crystal display, the OLED has advantages of low power consumption, low production cost, self-luminescent, broad viewing angle, and fast response speed and so on. At present, in the display field of a mobile phone, a PDA and a digital camera and the like, OLED has started to replace a traditional LCD display screen. The pixel driving circuit design is a core technical content of the AMOLED display, and has important research significance. 
     Unlike a thin film transistor liquid crystal display (TFT-LCD) that utilizes a stable voltage to control luminance, OLED belongs to a current-driven display and needs a stable current to control light emitting. 
     SUMMARY 
     The technical problem to be solved by the present disclosure is how to keep the current flowing through OLED of each pixel consistent. 
     In order to solve the above technical problem, one aspect of the present disclosure provides a pixel driving circuit, comprising: a data line, a first scanning line, a second scanning line, an enabling control line, a power supply line, a light emitting device, a driving transistor, a storage capacitor, a resetting unit, a data writing unit and a light emitting control unit. 
     The resetting unit is connected to the enabling control line and a first terminal of the storage capacitor and configured to reset a voltage at the first terminal of the storage capacitor to low voltage under a control of the enabling control line. 
     The data writing unit is connected to a second terminal of the storage capacitor, the first scanning line and the driving transistor, and configured to write information including a threshold voltage of the driving transistor and a voltage of the data line into the second terminal of the storage capacitor under a control of the first scanning line. 
     The light emitting control unit is connected to the second scanning line, the data line, the power supply line, the first terminal of the storage capacitor, the driving transistor and the light emitting device. A gate of the driving transistor is connected to the second terminal of the storage capacitor, and a source and a drain thereof are connected to the light emitting control unit. The light emitting control unit is configured to make the first terminal of the storage capacitor be the voltage of the data line under a control of the second scanning line, make two terminals of the storage capacitor keep a voltage difference and make the driving transistor connected to the power supply line, so as to drive the light emitting device to emit light. 
     Alternatively, the resetting unit comprises a first transistor, whose gate is connected to the enabling control line, source is connected to the first terminal of the storage capacitor, and drain is connected to a ground. The first transistor is configured to make the first terminal of the storage capacitor connected to the ground under the control of the enabling control line, so as to set the first terminal of the storage capacitor to the low voltage. 
     Alternatively, the data writing unit comprises: a second transistor and a third transistor, wherein a gate of the second transistor is connected to the first scanning line, a source thereof is connected to the data line, and a drain thereof is connected to a source of the driving transistor; a gate of the third transistor is connected to the first scanning line, a source thereof is connected to a drain of the driving transistor, and a drain thereof is connected to the second terminal of the storage capacitor. The second transistor and the third transistor are configured to form an access under the control of the first scanning line, so as to write the information including the threshold voltage of the driving transistor and the voltage of the data line into the second terminal of the storage capacitor. 
     Alternatively, the light emitting control unit comprises: a fourth transistor, a fifth transistor and a sixth transistor, a gate of the fourth transistor is connected to the second scanning line, a source thereof is connected to the power supply line, and a drain thereof is connected to the source of the driving transistor; a gate of the fifth transistor is connected to the second scanning line, a source thereof is connected to the drain of the driving transistor, and a drain thereof is connected to the light emitting device; a gate of the sixth transistor is connected to the second scanning line, a source thereof is connected to the data line, and a drain thereof is connected o the first terminal of the storage capacitor. The sixth transistor is configured to write the voltage of the data line into the first terminal of the storage capacitor under the control of the second scanning line and make the two terminals of the storage capacitor keep the voltage difference. The fourth transistor and the fifth transistor are configured to form an access under the control of the second scanning line, so that the driving transistor is connected to the power supply line, so as to drive the light emitting device to emit light. 
     Alternatively, the light emitting device is an organic light emitting diode, whose anode is connected to the light emitting control unit and cathode is connected to the ground. 
     Another aspect of the present disclosure further provides a driving method of the pixel driving circuit described above, comprising following steps: applying an enable signal to the enabling control line, so that the resetting unit resets the first terminal of the storage capacitor to the low voltage; applying a first scanning effective signal to the first scanning line so that the data writing unit writes the information including the threshold voltage of the driving transistor and the voltage of the data line into the second terminal of the storage capacitor; and applying a second scanning effective signal to the second scanning line so that the light emitting control unit writes the voltage of the data line into the first terminal of the storage capacitor, makes the two terminals of the storage capacitor keep a voltage difference and makes the driving transistor connected to the power supply line so as to drive the light emitting device to emit light. 
     Alternatively, the step of applying a first scanning effective signal to the first scanning line so that the data writing unit writes the information including the threshold voltage of the driving transistor and the voltage of the data line into the second terminal of the storage capacitor comprises: 
     applying the first scanning effective signal to the first scanning line so that the second transistor and the third transistor are turned on to form an access, so as to write the information including the threshold voltage of the driving transistor and the voltage of the data line into the second terminal of the storage capacitor. 
     Alternatively, the step of applying a second scanning effective signal to the second scanning line so that the light emitting control unit writes the voltage of the data line into the first terminal of the storage capacitor, makes the two terminals of the storage capacitor keep a voltage difference and makes the driving transistor connected to the power supply line so as to drive the light emitting device to emit light comprises: 
     applying the second scanning effective signal to the second scanning line so that the sixth transistor is turned on to write the data voltage into the first terminal of the storage capacitor and make the two terminals of the storage capacitor keep a voltage difference and the fourth transistor and the fifth transistor are turned on to form an access, so that the driving transistor is connected to the power supply line, so as to drive the light emitting to emit light. 
     Another aspect of the present disclosure further provides an array substrate comprising the pixel driving circuit described above. 
     Another aspect of the present disclosure further provides a display apparatus comprising the array substrate described above. 
     In the pixel driving circuit and driving method thereof according to the embodiments of the present disclosure, the data writing unit writes the information of the threshold voltage of the driving transistor and the voltage of the data line into the storage capacitor. When the light emitting control unit controls light emitting, the information of the threshold voltage of the driving transistor written into the storage capacitor compensate for the threshold voltage of the driving transistor when the driving transistor emits light, which solves the problem of non-uniformity of the threshold voltage caused by the manufacturing process and long-time operation of the pixel point driving transistor, so that the current flowing through each pixel point light emitting device is not affected by the threshold voltage, thereby finally ensuring the uniformity of the image display. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a structure of a known 2T1C pixel driving circuit; 
         FIG. 2  is a schematic diagram of a structure of a pixel driving circuit of an embodiment of the present disclosure; 
         FIG. 3  is a schematic diagram of operation of the pixel driving circuit in  FIG. 2  in a resetting phase; 
         FIG. 4  is a timing diagram of the pixel driving circuit in  FIG. 2  in a resetting phase, corresponding to a timing phase  1 ; 
         FIG. 5  is a schematic diagram of operation of the pixel driving circuit in  FIG. 2  in a charging phase; 
         FIG. 6  is a timing diagram of the pixel driving circuit in  FIG. 2  in a charging phase, corresponding to a timing phase  2 ; 
         FIG. 7  is a schematic diagram of the pixel driving circuit in  FIG. 2  in a compensating and light emitting phase; 
         FIG. 8  is a timing diagram of the pixel driving circuit in  FIG. 2  in the compensating and light emitting phase, corresponding to a timing phase  3 . 
     
    
    
     DETAILED DESCRIPTION 
     Specific implementations of the present disclosure will be further described in detail by combining with accompanying figures and embodiments. 
       FIG. 1  is a known 2T1C pixel driving circuit. This circuit is constituted of only one driving TFT, one switch TFT and one storage capacitor Cs. When a scanning line selects one row, V scan  is low, T 1  is turned on, and a data voltage V data  is written into the storage capacitor Cs. After the scanning of this row ends, V scan  becomes high, T 1  is turned off, and a gate voltage stored on the Cs drives a T 2  transistor, so that the T 2  transistor generates current to drive OLED, thereby ensuring OLED to continuously emit light within one frame. The saturation current formula of TFT is I OLED =K(V GS −V th ) 2 . Due to process manufacturing and device aging and so on, the threshold voltage (V th ) of the driving TFT of respective pixel points will drift, which results in that the current flowing through OLED of each pixel point changes due to the change of V th , thereby influencing the display effect of the entire image. 
       FIG. 2  shows a circuit structure of a pixel driving circuit of the embodiment. As shown in  FIG. 2 , the circuit comprises: a data line Data, a first scanning line Scan[ 1 ], a second scanning line Scan[ 2 ], an enabling control line Em, a power supply line S, a light emitting device D, a driving transistor DTFT, a storage capacitor C, a resetting unit  1 , a data writing unit  2  and a light emitting control unit  3 . 
     The resetting unit  1  is connected to the enabling control line Em and a first terminal (i.e., node B) of the storage capacitor C, and is configured to reset a voltage at the first terminal of the storage capacitor C to a low voltage under a control of the enabling control line Em. 
     The data writing unit  2  is connected to a second terminal (node A) of the storage capacitor C, the first scanning line Scan[ 1 ], and the driving transistor DTFT, and is configured to write information including a threshold voltage V th  of the driving transistor DTFT and a voltage V data  of the data line Data into the second terminal of the storage capacitor C under a control of the first scanning line Scan[ 1 ]. At this time, the voltage at node A is V data −V th . 
     The light emitting control unit  3  is connected to the second scanning line Scan[ 2 ], the data line Data, the power supply S, the first terminal of the storage capacitor C, the driving transistor DTFT and the light emitting device D. A gate of the driving transistor DTFT is connected to the second terminal of the storage capacitor C, and a source and a drain thereof are connected to the light emitting control unit  3 . The light emitting control unit  3  is configured to make the first terminal of the storage capacitor C be the voltage V data  of the data line Data under a control of the second scanning line Scan[ 2 ], make two terminals of the storage capacitor C keep a voltage difference, and make the driving transistor DTFT connected to the power supply line S, so as to drive the light emitting device D to emit light. 
     In the pixel driving circuit of the present embodiment, the data writing unit  2  writes the information of the threshold voltage of the driving transistor and the voltage of the data line into the storage capacitor C. When the light emitting control unit  3  controls light emitting, the information of the threshold voltage of the driving transistor written into the storage capacitor C compensates for the threshold voltage of the driving transistor when the driving transistor emits light, which solves the problem of non-uniformity of the threshold voltage caused by the manufacturing process and long-time operation of the pixel point driving transistor, so that the current flowing through each pixel point light emitting device is not affected by the threshold voltage, thereby finally ensuring the uniformity of the image display. 
     In the present embodiment, the resetting unit  1  comprises: a first transistor T 1 . A gate of the first transistor T 1  is connected to the enabling control line Em, a source thereof is connected to the first terminal of the storage capacitor C, and a drain thereof is connected to a ground. The first transistor T 1  is configured to make the first terminal of the storage capacitor C connected to the ground under the control of the enabling control line Em, so as to set the first terminal of the storage capacitor C to the low voltage. That is, when Em is an active signal, the first terminal of C is connected to the ground by T 1 , and the voltage at node B is 0. 
     In the present embodiment, the data writing unit  2  comprises: a second transistor T 2  and a third transistor T 3 . A gate of the second transistor T 2  is connected to the first scanning line Scan[ 1 ], a source thereof is connected to the data line Data, and a drain thereof is connected to the source of the driving transistor DTFT. A gate of the third transistor T 3  is connected to the first scanning line Scan[ 1 ], a source thereof is connected to the drain of the driving transistor DTFT, and a drain thereof is connected to the second terminal of the storage capacitor C. The second transistor and the third transistor are configured to form an access under the control of the first scanning line Scan[ 1 ], so as to write the information including the threshold voltage of the driving transistor DTFT and the voltage of the data line into the second terminal of the storage capacitor C. 
     For example, as shown in  FIG. 2 , when the first scanning line Scan[ 1 ] is effective, T 2  and T 3  are turned on, so as to form an access T 2 →DTFT→T 3 , and the V data  signal starts to charge the node A through the access T 2 →DTFT→T 3  until the node A is charged to be V data −V th  (which satisfies that a voltage difference between the gate and the source of DTFT is V th ). At this time, the voltage at the two terminals of the storage capacitor C is also V data −V th . In addition, since T 5  is turned off, current in the access T 2 →DTFT→T 3  will not flow through the light emitting device, which indirectly reduces the loss of service time of the light emitting device. 
     In the present embodiment, the light emitting control unit  3  comprises: a fourth transistor T 4 , a fifth transistor T 5  and a sixth transistor T 6 . A gate of the fourth transistor T 4  is connected to the second scanning line Scan[ 2 ], a source thereof is connected o the power supply line S, and a drain thereof is connected to the source of the driving transistor DTFT. A gate of the fifth transistor T 5  is connected to the second scanning line Scan[ 2 ], a source thereof is connected the drain of the driving transistor DTFT, and a drain thereof is connected to the light emitting device D. A gate of the sixth transistor T 6  is connected to the second scanning line Scan[ 2 ], a source thereof is connected to the data line Data, and a drain thereof is connected to the first terminal of the storage capacitor C. The sixth transistor T 6  is configured to write the voltage of the data line into the first terminal of the storage capacitor C under the control of the second scanning line Scan[ 2 ] and make the two terminals of the storage capacitor C keep a voltage difference. The fourth transistor T 4  and the fifth transistor T 5  are configured to form an access under the control of the second scanning line Scan[ 2 ], so that the driving transistor DTFT is connected to the power supply lime S, so as to drive the light emitting device D to emit light. 
     As shown in  FIG. 2 , the light emitting control unit  3  comprises: a fourth transistor T 4 , a fifth transistor T 5  and a sixth transistor T 6 . A gate of the fourth transistor T 4  is connected to the second scanning line Scan[ 2 ], a source thereof is connected o the power supply line S, and a drain thereof is connected to the source of the driving transistor DTFT. A gate of the fifth transistor T 5  is connected to the second scanning line Scan[ 2 ], a source thereof is connected to the drain of the driving transistor DTFT, and a drain thereof is connected to the light emitting device D. A gate of the sixth transistor T 6  is connected to the second scanning line Scan[ 2 ], a source thereof is connected to the data line Data, and a drain thereof is connected to the first terminal of the storage capacitor C. When the second scanning line Scan[ 2 ] is effective, T 4 , T 5  and T 6  are turned on. At this time, the voltage at node B changes from the original 0V into V data , while the node A is in a floating state. Therefore, in order to maintain the original voltage difference (V data −V th ) between the nodes A and B, a constant voltage jump will occur to the voltage at the node A of the gate of the DTFT, and the voltage at the node A jumps to 2V data −V th . Moreover, at this time, T 4 , the driving transistor DTFT and T 5  form an access T 4 →DTFT→T 5 , the source of the driving transistor DTFT is connected to the power supply line S, the voltage is V dd , and current flows through the access T 4 →DTFT→T 5 , so that the light emitting device D starts to emit light. 
     It can be obtained from the saturation formula of the driving transistor DTFT the following: 
     
       
         
           
             
               I 
               D 
             
             = 
             
               
                 
                   K 
                   ⁡ 
                   
                     ( 
                     
                       
                         V 
                         GS 
                       
                       - 
                       
                         V 
                         th 
                       
                     
                     ) 
                   
                 
                 2 
               
               = 
               
                 
                   
                     K 
                     ⁡ 
                     
                       [ 
                       
                         
                           V 
                           dd 
                         
                         - 
                         
                           ( 
                           
                             
                               2 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 V 
                                 data 
                               
                             
                             - 
                             
                               V 
                               th 
                             
                           
                           ) 
                         
                         - 
                         
                           V 
                           th 
                         
                       
                       ] 
                     
                   
                   2 
                 
                 = 
                 
                   
                     K 
                     ⁡ 
                     
                       ( 
                       
                         
                           V 
                           dd 
                         
                         - 
                         
                           2 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             V 
                             data 
                           
                         
                       
                       ) 
                     
                   
                   2 
                 
               
             
           
         
       
       
         
           
             K 
             = 
             
               
                 μ 
                 · 
                 
                   C 
                   ox 
                 
               
               ⁢ 
               
                 W 
                 L 
               
             
           
         
       
     
     Herein, V GS  is a gate-source voltage of DTFT, μ is a carrier mobility, C ox  is a gate oxide layer capacitor, and W/L is a width-length ratio of the driving transistor. 
     It can be seen from the above formula that the operation current I D  has been not affected by V th , but is only related with V data , which solves thoroughly the problem of the threshold voltage (V th ) drift caused by the manufacturing process and long-time operation of the driving transistor DTFT, thereby eliminating its influence on the current I D  that drives the light emitting device and ensuring normal operation of the light emitting device. 
     The light emitting device D in the present embodiment can be an organic light emitting diode (OLED), whose anode is connected to the light emitting control unit, and connected to the drain of the fifth transistor T 5  in the example of  FIG. 2 , and cathode is connected to the ground. 
     The pixel driving circuit of the present embodiment overcomes the influence caused by the change of the threshold voltage V th  of the driving transistor by means of compensating mode. At the same time, this design guarantees that no current flows through the light emitting device (OLED) when the circuit is in the compensating phase and buffering phase, and also indirectly increases the service time of the OLED. 
     There further provides in an embodiment of the present disclosure a driving method of the pixel driving circuit described above, comprising following steps: 
     applying an enable signal to the enabling control line Em, so that the resetting unit  1  resets the first terminal of the storage capacitor C to the low voltage; 
     applying a first scanning effective signal to the first scanning line Scan[ 1 ] so that the data writing unit  2  writes the information including the threshold voltage of the driving transistor DTFT and the voltage of the data line into the second terminal of the storage capacitor C; and 
     applying a second scanning effective signal to the second scanning line Scan[ 2 ] so that the light emitting control unit  3  writes the voltage of the data line into the first terminal of the storage capacitor C, makes the two terminals of the storage capacitor C keep a voltage difference and makes the driving transistor DTFT connected to the power supply line so as to drive the light emitting device D to emit light. 
     In an exemplary embodiment, the step of applying a first scanning effective signal to the first scanning line Scan[ 1 ] so that the data writing unit  2  writes the information including the threshold voltage of the driving transistor DTFT and the voltage of the data line into the second terminal of the storage capacitor C may comprise: 
     applying the first scanning effective signal to the first scanning line Scan[ 1 ] so that the second transistor T 2  and the third transistor T 3  are turned on to form an access, so as to write the information including the threshold voltage of the driving transistor DTFT and the voltage of the data line into the second terminal of the storage capacitor C. 
     In an exemplary embodiment, the step of applying a second scanning effective signal to the second scanning line Scan[ 2 ] so that the light emitting control unit  3  writes the voltage of the data line into the first terminal of the storage capacitor C, makes the two terminals of the storage capacitor C keep a voltage difference and makes the driving transistor DTFT connected to the power supply line so as to drive the light emitting device D to emit light may comprise: 
     applying the second scanning effective signal to the second scanning line Scan[ 2 ] so that the sixth transistor T 6  is turned on to write the voltage of the data line into the first terminal of the storage capacitor C and make the two terminals of the storage capacitor C keep a voltage difference, and the fourth transistor T 4  and the fifth transistor T 5  are turned on to form an access, so that the driving transistor DTFT is connected to the power supply line S, so as to drive the light emitting D to emit light. 
     The above driving method will be described below in detail by taking all the transistors in the pixel driving circuit in  FIG. 2  being P-type transistors and the light emitting device being OLED as an example. The driving method includes three phases. 
       FIG. 3  schematically shows an equivalent circuit of the pixel driving circuit in  FIG. 2  operating in a resetting phase.  FIG. 4  shows a timing diagram of the pixel driving circuit in the resetting phase, corresponding to a timing phase  1 . As shown in  FIGS. 3 and 4 , the timing diagram phase  1  is the resetting phase. At this time, Em is valid, T 1  is turned on (as shown in the dashed line block in  FIG. 3 ), and T 2 , T 3 , T 4 , T 5  and T 6  are turned off. This process resets the node B to be connected to the ground, that is, the first terminal of the storage capacitor C is connected to the ground (the current access of the first terminal of the storage capacitor C and the ground is as shown in the dotted arrow in  FIG. 3 ). The voltage is 0V, and the previous voltage signal is reset. 
       FIG. 5  schematically shows an equivalent circuit of the pixel driving circuit in  FIG. 2  operating in a charging phase, corresponding to a timing phase  2 . As shown in  FIGS. 5 and 6 , the timing phase  2  is the charging phase. At this time, T 2  and T 3  are turned on (as shown in the dashed line block in  FIG. 5 ), and T 1 , T 4 , T 5 , and T 6  are turned off. The V data  signal of the data line Data starts to charge the node A through the current access T 2 →DTFT→T 3  (as shown in the dotted arrow in  FIG. 5 ) until the node A is charged to be V data −V th  (which satisfies the voltage difference between the gate and source of DTFT is V th ). In this process, since the node B is connected to the ground and its potential is always 0, the voltage at the node A will be always maintained at V data −V th  after the charging is finished. In addition, since T 5  is turned off, the current will not flow through OLED, thereby reducing indirectly the loss of the service time of OLED. 
       FIG. 7  schematically shows an equivalent circuit of the pixel driving circuit in  FIG. 2  in a compensating and light emitting phase.  FIG. 8  schematically shows a timing diagram of the pixel driving circuit in  FIG. 2  in the compensating and light emitting phase, corresponding to a timing phase  3 . As shown in  FIGS. 7 and 8 , the timing phase  3  is the compensating and light emitting phase of the OLED pixel driving circuit. At this time, T 4 , T 5  and T 6  are turned on (as shown in the dashed line block in  FIG. 7 ), and T 2 , T 3 , and T 1  are turned off. At this time, the voltage at the node B changes from the original 0V into V data , while the node A is in a floating state. Therefore, in order to maintain the original voltage difference (V data −V th ) between the nodes A and B, a constant voltage jump will occur to the voltage at the node A of the gate of the DTFT, and the voltage at the node A jumps to 2V data −V th . At this time, T 4 , the driving transistor DTFT and T 5  form an access T 4 →DTFT→T 5  (as shown in the dotted arrow in  FIG. 7 ), the source of the driving transistor DTFT is connected to the power supply line S, and the voltage connected to the power supply line is V dd , and current flows through the access T 4 →DTFT→T 5 , so that the light emitting device D starts to emit light. 
     It can be obtained from the saturation formula of the driving transistor DTFT the following: 
     
       
         
           
             
               I 
               D 
             
             = 
             
               
                 
                   K 
                   ⁡ 
                   
                     ( 
                     
                       
                         V 
                         GS 
                       
                       - 
                       
                         V 
                         th 
                       
                     
                     ) 
                   
                 
                 2 
               
               = 
               
                 
                   
                     K 
                     ⁡ 
                     
                       [ 
                       
                         
                           V 
                           dd 
                         
                         - 
                         
                           ( 
                           
                             
                               2 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 V 
                                 data 
                               
                             
                             - 
                             
                               V 
                               th 
                             
                           
                           ) 
                         
                         - 
                         
                           V 
                           th 
                         
                       
                       ] 
                     
                   
                   2 
                 
                 = 
                 
                   
                     K 
                     ⁡ 
                     
                       ( 
                       
                         
                           V 
                           dd 
                         
                         - 
                         
                           2 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             V 
                             data 
                           
                         
                       
                       ) 
                     
                   
                   2 
                 
               
             
           
         
       
       
         
           
             K 
             = 
             
               
                 μ 
                 · 
                 
                   C 
                   ox 
                 
               
               ⁢ 
               
                 W 
                 L 
               
             
           
         
       
     
     Herein, V GS  is a gate-source voltage of DTFT, μ is a carrier mobility, C ox  is a gate oxide layer capacitor, and W/L is a width-length ratio of the driving transistor. 
     It can be seen from the above formula that V th  in the final expression of the operation current I OLED  has been offset at this time. That is, in the phase  2 , the voltage at the node A will be always maintained at V data −V th , wherein V th  compensates for the V th  produced by the DTFT in the phase  3 , so that I OLED  is not affected by V th , but is only related with V data . Therefore, the problem of the threshold voltage (V th ) drift caused by the manufacturing process and long-time operation of the driving transistor DTFT is thoroughly solved, its influence on I OLED  is eliminated and normal operation of the light emitting device is ensured. 
     Another embodiment of the present disclosure further provides an array substrate comprising the pixel driving circuit described above. 
     There further provides in another embodiment of the present disclosure a display apparatus comprising the above array substrate. This display apparatus can be any product or means having a display function, such as an AOLED panel, a TV set, a digital photo frame, a mobile phone, a tablet computer and so on. 
     The above implementations are just used for describing the present disclosure, but not used for limiting the present disclosure. Those skilled in the art can make various improvements and modifications without departing from the spirit and scope of the present disclosure, and thus these improvements and modifications as well as equivalent technical solutions also belong to the scope of the present disclosure. The patent protection scope of the present disclosure shall be defined by the Claims. 
     The present application claims the priority of a Chinese patent application No. 201410184466.1 filed on May 4, 2015. Herein, the content disclosed by the Chinese patent application is incorporated in full by reference as a part of the present disclosure.