Patent Publication Number: US-5835773-A

Title: Method for achieving native performance across a set of incompatible architectures using a single binary file

Description:
FIELD OF THE INVENTION 
     The invention relates to the field of generating and executing programs for digital computer systems. 
     BACKGROUND OF THE INVENTION 
     In the past, software vendors have been limited to providing a software product that is only compatible with an operating system that runs on just one computer platform. However, now a wide range of computer platforms that provide various levels of computing performance can run a common operating system. Since lower cost platforms provide lower performance, while higher cost platforms provide higher performance, computer users advantageously scale what they pay for a particular computer platform in accordance with a desired level of computing performance. Software vendors now have an opportunity to provide a software product that runs on the common operating system on the wide range computer platforms. 
     Despite some compatibility provided by the common operating system, software vendors are still limited by incompatible computer architectures. Lower performance computer platforms include computer architectures that are incompatible with computer architectures of higher performance computer platforms. A simple example of such incompatibility is incompatible instructions set architectures of the computer platforms. However, even among platforms having the same instruction set architecture, there are further incompatibilities caused by significantly different performance characteristics of different micro-architectures. 
     Among various previously known strategies employed by software vendors for coping with such computer architecture incompatibilities, each includes an undesirable trade off. 
     A first strategy is for software vendors to distribute intermediate code, which requires end users to generate optimized binary files for execution on their particular computer platform. A disadvantage of this strategy is an undesirable increase in machine resources and in skill level required by the end users. 
     Another strategy is for software vendors to support only a subset architecture that is common to the otherwise incompatible computer architecture. A disadvantage of this strategy is that it gives up much of the performance that could be gained by exploiting all of the features of each computer architecture of the wide range of computer platforms. 
     Yet another strategy is using emulation of a single binary. While this provides good compatibility across a set of instruction set architectures, resulting performance is typically an order of magnitude lower than a native binary. 
     Yet another strategy is performing dynamic translation from one instruction set architecture to another instruction set architecture while performing local performance optimization. Unfortunately, overall performance is still limited, since more global optimizations such as cache padding, inlining, global code motion, and the like, may be very difficult to perform using dynamic translation. 
     Yet another strategy is for software vendors to distribute so called &#34;chubby&#34; binaries, which are very large files that include duplication in multiple versions of all code, so that each version performs well on at least one of the computer platforms. However, this results in computer platform resources being consumed by very large files. Since a large amount of this duplicated code is not performance critical, some of the increase in space usage does not provide a major advantage in performance. 
     What is needed is a method and article of manufacture for a balanced tradeoff between size of a single binary and performance of that binary on various computer architectures of a wide range of computer platforms. 
     SUMMARY OF THE INVENTION 
     The present invention provides a method and article of manufacture for a balanced tradeoff between size of a single binary file and performance of that binary on various computer architectures of a wide range of computer platforms. 
     In accordance with the teachings of the invention, a majority of execution time of most programs is spent executing a relatively small section of the binary. Only these sections need to be native compiled for full performance on a desired computer architecture. A complementary remainder of the program can be dynamically translated from a particular computer architecture, selected as a generic architecture, to the desired architecture with little loss in overall performance. Another advantage is the modular construction of the binary, which provides for end users to easily strip out of the binary any support for undesired computer architectures. 
     Briefly and in general terms the invention includes identifying performance critical source code and complementary source code having less performance criticality than the performance critical source code. The performance critical source code is compiled so as to generate performance critical object code for a first computer architecture, or an additional plurality of computer architectures as desired. The complementary source code is compiled so as to generate complementary object code for the so called generic computer architecture, which is different than at least one of the plurality of computer architectures. As will be discussed in greater detail subsequently herein, the complementary object code has less performance criticality than the performance critical object code so as to reduce overall performance effects of subsequent translation of the complementary code to any desired computer architecture. 
     For convenient distribution, computer readable program code is preferably embodied in a single architecture independent executable binary file that includes the performance critical object code for the plurality of computer architectures, as well as the complementary object code. Subsequent storage of the computer readable program code on a computer usable medium such as a floppy disk further aids in distribution. 
     In accordance with the principles of the invention, after such distribution the file is opened for execution on a computer having the desired computer architecture by loading the performance critical object code for the desired computer architecture from among the performance critical object code for the plurality of computer architectures. The complementary object code is loaded, and is translated to the desired computer architecture if the so called generic computer architecture is different than the desired computer architecture. 
     Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawing, illustrating by way of example the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a block diagram of a single architecture independent executable binary file of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the preferred embodiment of the invention, software performance analysis techniques are employed to identify performance critical source code and complementary source code having less performance criticality than the performance critical source code. Performance criticality is defined in terms of frequency of execution. Upon compilation and execution, analysis reveals that the performance critical source code is more frequently executed than the complementary source code. 
     The performance critical source code is compiled so as to generate performance critical object code for a first computer architecture, or an additional plurality of computer architectures as desired. The complementary source code is compiled so as to generate complementary object code for the so called generic computer architecture, which is different than at least one of the plurality of computer architectures. 
     FIG. 1 shows a block diagram of a single architecture independent executable binary file of the present invention. In the preferred embodiment, the performance critical object code for each one of the plurality of computer architectures includes performance critical absolute object code for the respective computer architecture and an address translation table for the performance critical absolute object code for the respective computer architecture. 
     For example, as shown in FIG. 1. within the file the performance critical object code for the first computer architecture includes performance critical absolute object code for the first computer architecture and an address translation table for the performance critical absolute object code for the first computer architecture. Similarly, the performance critical object code for the second computer architecture includes performance critical absolute object code for the second computer architecture and an address translation table for the performance critical absolute object code for the second computer architecture. 
     The complementary object code has less performance criticality than the performance critical object code so as to reduce overall performance effects of subsequent translation of the complementary code to any desired computer architecture. Preferably, all desired computer architectures are equipped with an appropriate dynamic translator for translating from the so called generic computer architecture to the desired computer architecture. Helpful discussions by William B. Buzby in U.S. patent application Ser. No. 08/616608 filed Mar. 15, 1996 and entitled &#34;Use of Dynamic Translation to Collect and Exploit Run-Time Information in an Optimizing Compilation System&#34; are incorporated herein by reference. While dynamic translation as described therein is preferred, it should be understood that use of various translation techniques in conjunction with the invention provide beneficial results. 
     In the preferred embodiment, the complementary object code is position independent object code, which is particularly advantageous for use in conjunction with dynamic translation. All addresses for program data and any code located in the performance critical section are stored in the address translation table for each specific architecture. This system advantageously provides for code and data symbols being placed differently on various computer architectures; only forcing the translation table to be of identical layout. This is advantageous since different architectures need different data layout for maximum performance, and some computer architectures will have larger code size for routines in the performance critical object code. 
     Preferably, the binary file includes performance critical object code for the so called generic computer architecture. Since in the preferred embodiment all computer platforms that can execute any of the performance critical object code will have a dynamic translator for the so called generic computer architecture, each computer platform can execute the binary file, even if not at native performance. 
     The binary file is preferably stored on a computer usable medium such as a floppy disk to provide for convenient distribution of computer readable program code. In accordance with the principles of the invention, after such distribution the file is opened for execution on a computer having the desired computer architecture by loading the performance critical object code for the desired computer architecture from among the performance critical object code for the plurality of computer architectures. The complementary object code is translated to the desired computer architecture if the so called generic computer architecture is different than the desired computer architecture, and is loaded. 
     When the dynamic translator converts an access to an address within the address translation table, the address is mapped to the actual address within the object code compiled for that computer architecture. This is similar to mapping done for code addresses in dynamic object code translation, except the address translation table contains the starting addresses for data symbols. This provides for the translator directly materializing the constant address in-line, rather than referencing the translation table. Since the native code for the performance critical object code contains the address translation table, there is no need to make the performance critical code position independent. 
     The present invention provides a method and article of manufacture for a balanced tradeoff between size of a single binary file and performance of that binary on various computer architectures of a wide range of computer platforms. Although specific embodiments of the invention have been described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated, and various modifications and changes can be made without departing from the scope and spirit of the invention. Within the scope of the appended claims, therefor, the invention may be practiced otherwise than as specifically described and illustrated.