Patent Publication Number: US-2020286738-A1

Title: Spacer Etching Process For Integrated Circuit Design

Description:
This is a divisional application of U.S. patent application Ser. No. 15/357,203, filed on Nov. 21, 2016, which is a continuation application of U.S. patent application Ser. No. 14/850,764, filed Sep. 10, 2015, which is a divisional application of U.S. patent application Ser. No. 14/081,345, filed Nov. 15, 2013, now issued U.S. Pat. No. 9,153,478, which claims the benefit of U.S. Provisional Application No. 61/791,138 entitled “Spacer Etching Process for Integrated Circuit Design” filed Mar. 15, 2013 each of which is herein incorporated by references in its entirety. This patent application also herein incorporates by reference U.S. patent application Ser. No. 13/892,945 entitled “A Method of Fabricating a FinFET Device” filed May 13, 2013, now issued U.S. Pat. No. 8,932,957. 
    
    
     BACKGROUND 
     The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. 
     For example, a spacer technique is often used to form mandrels, which are used in devices such as a fin field effect transistor (FinFET) device. Frequently, the spacer technique is used for doubling the exposed pattern in advanced lithography. That is, the pitch of a final pattern is reduced to only half compared with the first exposed pattern. Due to constraints from the lithography process, it is difficult to obtain small cut features. 
     Also in some occasions, it is desirable to have a large process window. The process window refers to a range of focus and exposure settings that will still produce the desired features into the photo-resist layer in the photolithographic process. 
     Accordingly, what is needed is an improvement in this area. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  is a flow chart of a method of forming a target pattern on a substrate for implementing one or more embodiments. 
         FIG. 2  shows a target pattern  200  with target features  202 ,  204 ,  206 ,  208 ,  210 , and  212 .  FIG. 2  also shows the target feature  208  being cut from the target feature  206  by a cut feature  214 . 
         FIGS. 3 a , 3 b , 3 c , 4 a , 4 b , 5 a , and 5 b    illustrate the operations of forming the target pattern  200  according to the method of  FIG. 1 , in accordance with an embodiment. 
         FIGS. 6 a , 6 b , 6 c , 6 d , 6 e , 7 a , 7 b , 7 c , 8 a , 8 b , 8 c   ,  9   a ,  9   b ,  9   c ,  9   d ,  9   e ,  10   a ,  10   b ,  10   c ,  10   d ,  10   e ,  11   a ,  11   b ,  11   c ,  11   d ,  11   e ,  11   f , and  11   g  are top and cross sectional views of forming a device according to the method of  FIG. 1 , in accordance with an embodiment. 
         FIGS. 12 a  and 12 b    illustrate the minimum cut feature with two embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the performance of a first process before a second process in the description that follows may include embodiments in which the second process is performed immediately after the first process, and may also include embodiments in which additional processes may be performed between the first and second processes. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity. Furthermore, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Referring now to  FIG. 1 , a flow chart of a method  100  for forming a target pattern is illustrated. Additional operations can be provided before, during, and after the method  100 , and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. The method  100  is an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. The method  100  will be further described below. 
       FIG. 2  is a diagram showing an example target pattern  200  including a number of target features  202 ,  204 ,  206 ,  208 ,  210 ,  212  and a cut feature  214 . The target features may be, for example, metal lines. This target pattern  200  will be further described with reference to the additional figures of the patent, as discussed below. 
     Referring to  FIGS. 1 and 3   a , the method  100  begins at operation  102  by providing a substrate  218 . The substrate  218  includes one or more material layers. In an embodiment, the substrate includes a semiconductor layer, a pad oxide layer, and a silicon nitride (SiN) layer. In an embodiment, the substrate includes a dielectric layer, an inter-layer dielectric layer such as an extreme low-k dielectric (ELK) layer, and an anti-reflection layer such as a nitrogen-free anti-reflection coating (NFARC) layer. In one example, the NFARC layer uses a material such as silicon oxide, silicon oxygen carbide, or plasma enhanced chemical vapor deposited silicon oxide. 
     The method  100  proceeds to operation  104  by forming a hard mask layer  220  on the substrate  218 . The hard mask layer  220  may include one or more material layers and is formed by a procedure such as deposition. In an embodiment, the hard mask layer  220  may include silicon oxide formed by thermal oxidation. In an embodiment, the hard mask layer  220  may include SiN formed by chemical vapor deposition (CVD). For example, the hard mask layer  220  may be formed by CVD using chemicals including Hexachlorodisilane (HCD or Si2Cl6), Dichlorosilane (DCS or SiH2Cl2), Bis(TertiaryButylAmino) Silane (BTBAS or C8H22N2Si) and Disilane (DS or Si2H6). 
     Referring to  FIGS. 1 and 3   b , the method  100  proceeds to operation  106  by performing a first patterning process to the hard mask layer  220  using a first layout, thereby forming a first plurality of trenches,  222   a ,  222   b ,  222   c , and  222   d , in the hard mask layer  220 , as illustrated in  FIG. 3 b   . The first patterning process includes a lithography process and an etching process. In an embodiment, a resist layer, patterned with the first layout, is formed on the hard mask layer  220  using a lithography process, such as resist coating, soft baking, exposing, post-exposure baking (PEB), developing, and hard baking in one example. Then, the hard mask layer  220  is etched through the openings of the patterned resist layer, forming a plurality of trenches,  222   a ,  222   b ,  222   c , and  222   d , in the hard mask layer  220  by the etching process. The patterned resist layer is removed thereafter using a suitable process, such as wet stripping or plasma ashing. In one example, the etching process includes applying a dry (or plasma) etch to remove the hard mask layer  220  within the openings of the patterned resist layer. 
     Referring to  FIGS. 1 and 3   c , the method  100  proceeds to operation  108  by performing a second patterning process to the hard mask layer  220  using a second layout, thereby forming a second plurality of trenches,  224   a ,  224   b ,  224   c , and  224   d , in the hard mask layer  220 , as illustrated in  FIG. 3   c.    
     In an embodiment, the second patterning process starts with forming a material layer over the hard mask layer  220  using one or more material different from the hard mask layer  220 . For example, while the hard mask layer  220  uses silicon oxide or silicon nitride, the material layer may use bottom anti-reflective coating (BARC) or spin-on glass (SOG). The second patterning process further includes a lithography process and an etching process thereby forming the second plurality of trenches in the hard mask layer  220 . In an embodiment, a resist layer, patterned with the second layout, is formed on the material layer using a lithography process. Then, the material layer and the hard mask layer  220  are etched through the openings of the patterned resist layer, forming a plurality of trenches in the hard mask layer  220  by the etching process. The patterned resist layer is removed thereafter using a suitable process, such as wet stripping or plasma ashing. The material layer is removed thereafter using a suitable process, such as an etching process tuned to selectively remove the material layer while the hard mask layer  220  remains. 
     Thus far, by performing operations  106  and  108  of the method  100 , both the first plurality of mandrel trenches and the second plurality of mandrel trenches are formed on the hard mask layer  220 , and portions of the first plurality of mandrel trenches and portions of the second plurality of mandrel trenches may merge. 
       FIG. 4 a    shows the merged mandrel trenches in the hard mask layer  220  including mandrel trenches  226   a ,  222   b ,  226   c , and  224   d . The mandrel trench  226   a  is formed by merging mandrel trench  222   a  formed in operation  106  of the method  100  and mandrel trench  224   a  formed in operation  108  of the method  100 . The mandrel trench  226   c  is formed by merging mandrel trenches  222   c  and  222   d  formed in operation  106  of the method  100  and mandrel trenches  224   b  and  224   c  are formed in operation  108  of the method  100 . 
     Referring to  FIGS. 1 and 4   b , after thus having formed the merged mandrel trenches in the hard mask layer, the method  100  proceeds to operation  110  by forming spacer features inside and on the sidewalls of the merged mandrel trenches, such as spacer features  228   a ,  228   b ,  228   c ,  228   d , and  228   e , as shown in  FIG. 4 b   . The spacer features have a thickness. The spacer features include one or more materials different from the hard mask layer  220 , such as titanium nitride (TiN). In addition or in the alternative, the spacer features may include a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. The spacer features can be formed by various processes, including a deposition process and an etching process. For example, the deposition process includes a CVD process or a physical vapor deposition (PVD) process. For example, the etching process includes an anisotropic etch such as plasma etch. Wherein width of the mandrel trenches is equal to or less than twice the thickness of the spacer features, spacer features merge inside the mandrel trenches. For example, referring to  FIG. 4 b   , within a dotted box  230 , spacer features  228   c  and  228   e  properly merge inside a mandrel trench. 
     The method  100  proceeds to operation  112  by removing the hard mask layer  220  through a suitable process, such as an etching process tuned to selectively remove the hard mask layer while the spacer features remain. 
     Referring to  FIGS. 1 and 5   a , the method  100  proceeds to operation  114  by forming a material layer  240  on the substrate and within openings defined by the spacer features  228   a - e , as illustrated in  FIG. 5 a   . In an embodiment, the material layer is deposited over the spacer features and is then partially removed such that the top surface of the spacer features is exposed by a procedure, such as chemical mechanical polishing (CMP) or etch back. In an embodiment, the material layer uses bottom anti-reflective coating (BARC) or spin-on glass (SOG). 
     The method  100  proceeds to operation  116  by removing the spacer features through a suitable process, such as an etching process tuned to selectively remove the spacer features while the material layer  240  remains. Wherein the width of the merged trenches is equal to or less than twice the thickness of the spacer features, a cut feature is formed after the spacer features are removed.  FIG. 5 b    shows the spacer features  228   a - e  being removed, leaving a desired pattern on the substrate with a cut feature  214 . 
       FIGS. 6 a -11 g    show a process flow for a lithographic-spacer process with cut features according to a second embodiment of the present disclosure. In each of  FIGS. 6 a -11 g   , the figure designated “a” (e.g.,  FIG. 6 a   ) includes a dotted line that defines cross sectional views for the figures designated “b,” “c,” and so on. 
     Referring to  FIGS. 6 a -6 e   , a first layout is formed in the hard mask layer  308  as mandrel trenches. In the present embodiment, a substrate includes a dielectric layer  302 , an inter-layer dielectric (ILD) layer  304 , and a nitrogen-free anti-reflection coating (NFARC) layer  306 . A hard mask layer  308  is formed on the NFARC layer  306 . A first bottom material layer  310 , a first middle material layer  312 , and a first resist layer  314  are formed for patterning the hard mask layer  308 . In an embodiment, the ILD layer  304  includes an extreme low-k dielectric (ELK) material, the NFARC layer  306  includes a material such as silicon oxide, silicon oxygen carbide, or plasma enhanced chemical vapor deposited silicon oxide, the hard mask layer  308  includes silicon nitride, the bottom material includes a bottom anti-reflection coating polymeric material, and the middle material includes silicon containing polymer. 
       FIGS. 6 b , 6 c    show the device with a patterned resist layer  314  according to the first layout as mandrel trenches.  FIGS. 6 d , 6 e    show the device after etching through the openings of the patterned resist layer  314  and thereafter removing the layers  314 ,  312 , and  310 , thereby forming a first plurality of trenches in the hard mask layer  308 . 
     Referring to  FIGS. 7 a -7 c   , a second bottom material layer  320  is deposited over the hard mask layer  308 , a second middle material layer  322  is deposited over the second bottom material layer  320 , and a second resist layer  324  is patterned according to a second layout as mandrel trenches. The layers  322 ,  320 , and  308  are to be etched through the openings of the patterned resist layer  324  to form a second plurality of trenches in the hard mask layer  308 . 
       FIGS. 8 a -8 c    show the merger of the first and second plurality of mandrel trenches in the hard mask layer  308  after etching the layers  322 ,  320 , and  308  through the openings of the patterned resist layer  324  in  FIGS. 7 b  and 7 c   , and removing the layers  324 ,  322 , and  320  thereafter. 
       FIGS. 9 a -9 e    show spacer features being formed inside and on sidewalls of the merged mandrel trenches.  FIGS. 9 b , 9 c    show a spacer material  330  being deposited over the hard mask layer  308  and on the NFARC layer  306 . In one example, the spacer material includes titanium nitride.  FIGS. 9 d , 9 e    show the spacer material  330  from the horizontal surfaces away from the mandrel sidewalls being removed, such as by an anisotropic etch process, thereby forming spacer features on the sidewalls of the mandrel trenches. 
       FIGS. 10 a -10 e    show the hard mask layer  308  being removed, as well as portions of the NFARC layer  306  and the ILD layer  304 , with the spacer features formed in  FIGS. 9 a -9 e    being used as a mask. This can be done by a suitable process, such as an anisotropic etch process. 
       FIGS. 11 a -11 g    show the desired final pattern being formed in the ILD layer  304  on the dielectric layer  302 .  FIGS. 11 b , 11 c    show the spacer features  330  and NFARC layer  306  being removed, leaving only the patterned ILD layer  304  on the dielectric layer  302 . This can be done by one or two etching processes, selective to the spacer material and the NFARC material.  FIGS. 11 d , 11 e    show a material  340  deposited over the patterned ILD layer  304 . For example, the material  340  can be copper, tungsten or silicide for forming metal lines.  FIGS. 11 f , 11 g    show the deposited material  340  being planarized to form the final device. This can be done with an etching or chemical mechanical polishing (CMP) process. 
     Accordingly, the present disclosure provides a method of forming a target pattern or device by performing a first and a second lithography processes to form mandrel trenches in a hard mask layer, and thereafter performing spacer and etching processes. 
     Although not intended to be limiting, an advantage of one or more embodiments of the present disclosure is that the second layout can be used as not only either a main feature or a cut feature of the target pattern, but also both of them after proper process scheme. That is, the second layout can be used as a new mandrel, a merged portion of the first layout, or a cut feature for the first layout so as to achieve a desirable uniformity in density for lithographic exposure. The desirable uniformity in pattern density improves lithography process window. Therefore, the present disclosure is lithography friendly for forming small cut features. Moreover, the second layout may be used either before or after the first layout in performing the method  100  to achieve same result. The new process can be referred to as LLSE (lithography, lithography, spacer, etch). This LLSE process has the advantage of the conventional LELE processes, and has the capability of making smaller cut features. 
       FIGS. 12 a , 12 b    illustrate one improvement achieved by the present disclosure over a LELE process. For simplicity purposes, a dimension of a feature in direction X is referred to as the width of the feature, and a dimension of a feature in direction Y is referred to as the length of the feature. 
     Referring now to  FIG. 12 a   , in a LELE process, a mandrel line within a spacer  256  is cut to two mandrel lines  250  and  252  by a cut feature  254 . A distance  255  between one end of mandrel line  250  and one end of mandrel line  252  is referred to as an End-to-End (EtE) feature which is limited by the length of cut feature  254 . Since the width of cut feature  254  is constrained by the width of the spacer  256 , the minimum length of cut feature  254  is limited by the lithography process. 
     Referring now to  FIG. 12 b   , in an embodiment of the present disclosure, a cut feature  264  is formed as a trench in a second lithography process over two mandrel trenches  266  and  268  formed in a first lithography process. A distance  265  between one end of a target feature  262  and one end of a target feature  260  is referred to as an End-to-End (EtE) feature, which is limited by the length of cut feature  264 . The width of cut feature  264  is constrained within two mandrel trenches  266  and  268 . Because the width of mandrel trenches  266  and  268  is substantially larger than the width of spacer  256  from  FIG. 12 a   , the width of cut feature  264  can be substantially larger than the width of cut feature  254  from  FIG. 12 a   . As a result, the length of cut feature  264  can be substantially smaller than the length of cut feature  254  for the same lithography process. Hence, a smaller EtE feature is achieved by an embodiment of the present disclosure. 
     Thus, the present disclosure provides an embodiment of a method of forming a target pattern. The method includes forming a first material layer on a substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness; removing the first material layer; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features. The target pattern is to be formed with the first layout and the second layout. 
     The present disclosure also provides another embodiment of a method of forming a target pattern on a substrate. The method includes forming a first material layer on the substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness; removing the first material layer; forming a second material layer on the substrate and within openings defined by the spacer features; and removing the spacer features. The target pattern is to be formed with the first layout and the second layout. 
     The present disclosure provides yet another embodiment of a method of forming a target pattern. The method includes depositing a first material layer on a substrate; performing a first lithography patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second lithography patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches using a process including deposition and etching, the spacer features having a thickness; removing the first material layer by an etching process; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features using one of: an etching process and a polishing process. The target pattern is to be formed with the first layout and the second layout; the first layout includes a first subset of the target pattern; the second layout includes a second subset of the target pattern and a cut pattern for the first subset; and the cut pattern corresponds to a portion of the second layout wherein width of the second layout is less than twice the thickness of the spacer features. 
     The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.