Patent Publication Number: US-2022216222-A1

Title: Structure and method for sram finfet device having an oxide feature

Description:
This application is a continuation application of U.S. patent application Ser. No. 16/913,061, filed Jun. 26, 2020, which is a continuation of U.S. patent application Ser. No. 15/664,315, filed Jul. 31, 2017, which is a divisional application of U.S. application Ser. No. 14/262,378, filed Apr. 25, 2014, each of which is herein incorporated by reference in its entirety. 
     This application is related to U.S. patent application Ser. No. 13/740,373 filed Jan. 14, 2013, now issued U.S. Pat. No. 8,901,607; Ser. No. 13/902,322 filed May 24, 2013, now issued U.S. Pat. No. 9,318,606; Ser. No. 13/934,992 filed Jul. 3, 2013, now issued U.S. Pat. No. 9,006,786; Ser. No. 14/155,793 filed Jan. 15, 2014, now issued U.S. Pat. No. 9,257,559; U.S. Ser. No. 14/254,072 filed Apr. 16, 2014, now issued U.S. Pat. No. 9,209,185; and U.S. Ser. No. 14/254,035 filed Apr. 16, 2014, as “FinFET Device With High-K Metal Gate Stack”, the entire disclosures of which are hereby incorporated by reference. 
    
    
     BACKGROUND 
     The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. 
     Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, a three dimensional transistor, such as a static random-access memory (SRAM) fin-like field-effect transistor (FinFET), has been introduced to replace a planar transistor. Although existing FinFET devices and methods of fabricating SARM FinFET devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read in association with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features in drawings are not drawn to scale. In fact, the dimensions of illustrated features may be arbitrarily increased or decreased for clarity of discussion. 
         FIG. 1  is a flow chart of an example method for fabricating a SRAM FinFET device in accordance with some embodiments. 
         FIG. 2A  is a diagrammatic perspective view of an example SRAM FinFET device undergoing processes in accordance with some embodiments. 
         FIG. 2B  is a cross-sectional view of an example FinFET device along the line A-A in  FIG. 2A  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIG. 3A  is a diagrammatic perspective view of an example SRAM FinFET device undergoing processes in accordance with some embodiments. 
         FIG. 3B  is a cross-sectional view of an example SRAM FinFET device alone the line A-A in  FIG. 3A  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIGS. 4A and 4B  are diagrammatic perspective views of a SRAM FinFET device undergoing processes in accordance with some embodiments. 
         FIG. 5  is a cross-sectional view of an example SRAM FinFET device along the line A-A in  FIG. 4A  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIG. 6A  is a cross-sectional view of an example SRAM FinFET device along the line A-A in  FIG. 4A  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIG. 6B  is a cross-sectional view of an example SRAM FinFET device along the line B-B in  FIG. 4B  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIGS. 7A and 7B  are diagrammatic perspective views of a SRAM FinFET device undergoing processes in accordance with some embodiments. 
         FIGS. 8A and 8B  are diagrammatic perspective views of a SRAM FinFET device undergoing processes in accordance with some embodiments. 
         FIG. 8C  is a cross-sectional view of an example SRAM FinFET device along the line A-A in  FIG. 8A  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIG. 8D  is a cross-sectional view of an example SRAM FinFET device along the line B-B in  FIG. 8B  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIG. 9A  is a cross-sectional view of an example SRAM FinFET device along the line AB-AB in  FIG. 8A  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIG. 9B  is a cross-sectional view of an example SRAM FinFET device along the line BB-BB in  FIG. 8B  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIGS. 10A and 10B  are diagrammatic perspective views of a SRAM FinFET device undergoing processes in accordance with some embodiments. 
         FIGS. 11A and 11B  are diagrammatic perspective views of a SRAM FinFET device undergoing processes in accordance with some embodiments. 
         FIGS. 12A and 12B  are diagrammatic perspective views of a SRAM FinFET device undergoing processes in accordance with some embodiments. 
         FIG. 13A  is a cross-sectional view of an example SRAM FinFET device along the line AB-AB in  FIG. 12A  at fabrication stages constructed according to the method of  FIG. 1 . 
         FIG. 13B  is a cross-sectional view of an example SRAM FinFET device along the line BB-BB in  FIG. 12B  at fabrication stages constructed according to the method of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     The present disclosure is directed to, but not otherwise limited to, a fin-like field-effect transistor (FinFET) device. The FinFET device, for example, may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure will continue with a FinFET example to illustrate various embodiments of the present invention. It is understood, however, that the application should not be limited to a particular type of device, except as specifically claimed. 
       FIG. 1  is a flowchart of a method  100  for fabricating a SRAM FinFET device  200  in accordance with some embodiments. It is understood that additional steps may be implemented before, during, and after the method, and some of the steps described may be replaced or eliminated for other embodiments of the method. The SRAM FinFET device  200  and the method  100  making the same are collectively described with reference to various figures. 
     Referring to  FIGS. 1 and 2A-2B , the method  100  begins at step  102  by providing a substrate  210 . The substrate  210  may include a bulk silicon substrate. Alternatively, the substrate  210  may include an elementary semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; or combinations thereof. 
     In another embodiment, the substrate  210  has a silicon-on-insulator (SOI) structure with an insulator layer in the substrate. An exemplary insulator layer may be a buried oxide layer (BOX). The SOI substrate may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. 
     In the present embodiment, the substrate  210  includes a first semiconductor material layer  212 , a second semiconductor material layer  214  disposed over the first semiconductor material layer  212  and a third semiconductor material layer  216  disposed over the second semiconductor material layer  214 . The second and third semiconductor material layers,  214  and  216 , are different from each other. The second semiconductor material layer  214  has a first lattice constant and the third semiconductor material layer  416  has a second lattice constant different from the first lattice constant. In the present embodiment, the second semiconductor material layer  214  includes silicon germanium (SiGe), and both of the first and the third semiconductor material layers,  212  and  216 , include silicon. In various examples, the first, the second and the third semiconductor material layers,  212 ,  214  and  216 , may include germanium (Ge), silicon (Si), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), or other suitable materials. In the present embodiment, the second and the third semiconductor material layers,  214  and  216 , are deposited by epitaxial growth, referred to as a blanket channel epi. In various examples, the epitaxial processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. 
     The substrate  210  may include various doped features depending on design requirements as known in the art. In some embodiment, the substrate  210  may include various doped regions depending on design requirements (e. g., p-type substrate or n-type substrate). In some embodiment, the doped regions may be doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF 2 ; n-type dopants, such as phosphorus or arsenic, and/or combination thereof. The doped regions may be configured for an n-type FinFET (NFET), or alternatively configured for a p-type FinFET (PFET). 
     Referring to  FIGS. 1 and 3A-3B , the method  100  proceeds to step  104  by forming first fins structure  220  and trenches  230  in the substrate  210 . The first fin structure  220  has a first width w 1  in a range of about 4 nm to about 10 nm. In one embodiment, a patterned fin hard mask (FHM) layer  222  is formed over the substrate  210 . The patterned FHM layer  222  includes silicon oxide, silicon nitride, silicon oxynitride, or any other suitable dielectric material. The patterned hard mask layer  222  may include a single material layer or multiple material layers. The patterned FHM layer  222  may be formed by depositing a material layer by thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other appropriate method, forming a patterned photoresist (resist) layer by a lithography process, and etching the material layer through the openings of the patterned photoresist layer to form the patterned FHM layer  222 . 
     An exemplary photolithography process may include forming a photoresist layer, exposing the resist by a lithography exposure process, performing a post-exposure bake process, and developing the photoresist layer to form the patterned photoresist layer. The lithography process may be alternatively replaced by other technique, such as e-beam writing, ion-beam writing, maskless patterning or molecular printing. 
     The substrate  210  is then etched through the patterned FHM layer  222  to form the first fins structure  220  and the trenches  230  in the substrate  210 . In another embodiment, the patterned photoresist layer is directly used the patterned FHM layer  222  as an etch mask of the etch process to form the first fins structure  220  and the trenches  230  in the substrate  210 . The etching process may include a wet etch or a dry etch. In one embodiment, the wet etching solution includes a tetramethylammonium hydroxide (TMAH), a HF/HNO3/CH3COOH solution, or other suitable solution. The respective etch process may be tuned with various etching parameters, such as etchant used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and/or other suitable parameters. For example, a wet etching solution may include NH 4 OH, KOH (potassium hydroxide), HF (hydrofluoric acid), TMAH (tetramethylammonium hydroxide), other suitable wet etching solutions, or combinations thereof. Dry etching processes include a biased plasma etching process that uses a chlorine-based chemistry. Other dry etchant gasses include CF 4 , NF 3 , SF 6 , and He. Dry etching may also be performed anisotropically using such mechanism as DRIE (deep reactive-ion etching). 
     In the present embodiment, the etching depth is controlled such that the third and the second semiconductor material layers,  216  and  214  are exposed but the first semiconductor material layer  212  is partially exposed in the trench  230 . Thus the first fin structure  220  is formed to have the third semiconductor material layer  216  as an upper portion, the second semiconductor material layer  214  as a middle portion and the first semiconductor material layer  212  as a bottom portion. 
     In some embodiment, the SRAM FinFET device  200  includes an n-type FinFET (NFET) device, designated with the reference numeral  200 A and referred to as the SRAM FinFET device  200 A. The SRAM FinFET device  200  also includes a PFET device, designated with the reference numeral  200 B and referred to as the SRAM FinFET device  200 B. 
     Referring to  FIGS. 1 and 4A-4B , the method  100  proceeds to step  106  by forming a patterned oxidation-hard-mask (OHM)  310  over the substrate  210 , including wrapping a portion of the first fin structures  220 . In the present embodiment, in the NFET  200 A, the patterned OHM  310  covers a first region  312  and exposes a second region  314  in the substrate  210 . In the PFET  200 B, the patterned OHM  310  wraps the whole first fins structure  220 . The patterned OHM layer  310  may include silicon oxide, silicon nitride, silicon oxynitride, or any other suitable dielectric material. The patterned OHM layer  310  may be formed by depositing a material layer by thermal oxidation, chemical CVD, ALD, or any other appropriate method, forming a patterned photoresist (resist) layer by a lithography process, and etching the material layer through the openings of the patterned photoresist layer to form the patterned OHM layer  310 . 
     Referring also to  FIGS. 1, 4A and 5 , the method  100  proceeds to step  108  by performing a thermal oxidation process to the SRAM FinFET device  200 . In one embodiment, the thermal oxidation process is conducted in oxygen ambient. In another embodiment, the thermal oxidation process is conducted in a combination of steam ambient and oxygen ambient. In the second region  314  of the NFET  200 A, during the thermal oxidation process, at least outer layers of the first, the second and the third semiconductor material layers,  212 ,  214  and  216 , convert to a first, second and a third semiconductor oxide features  322 ,  324  and  326 , respectively. While in the first region  312  of the NFET  200 A, as well as entire the PFET  200 B, the patterned OHM  310  prevents the first fin structure  220 , to be oxidized. Therefore, the thermal oxidation process is referred to as a selective oxidation. 
     After the thermal oxidation process, the first fin structure  220  in the second region  324  has a different structure than those in the first region  312 . For the sake of clarity to better description, the first fin structure  220  in the second region  314  (having the second semiconductor oxide feature  324 ) is referred to as a second fin structure  320 . Thus the second fin structure  320  has the third semiconductor material layer  216  as its upper portion, the second semiconductor material layer  214 , with the second semiconductor oxide feature  324  at its outer layer, as its middle portion and the first semiconductor material layer as its bottom portion. 
     In the present embodiment, the thermal oxidation process is controlled such that the second semiconductor material layer  214  oxidizes much faster that the first and third semiconductor material layers,  212  and  216 . In another words, comparing to the second semiconductor oxide feature  324 , the first and third semiconductor oxide features,  322  and  326 , are quite thin. As an example, the thermal oxidation process to the SRAM FinFET device  200  is performed in a H 2 O reaction gas with a temperature ranging from about 400° C. to about 600° C. and under a pressure ranging from about 1 atm. to about 20 atm. After the oxidation process, a cleaning process is performed to remove the first and the third semiconductor oxide features,  322  and  326 . The cleaning process may be performed using diluted hydrofluoric (DHF) acid. 
     In the present example, the second semiconductor oxide features  324  extends in the vertical direction with a horizontal dimension varying from the top surface to the bottom surface of the second semiconductor material layer  214 . In furtherance of the present example, the horizontal dimension of the second semiconductor oxide features  324  reaches its maximum, referred to as a second width w 2 , and decreases to close to zero when approaches to the top and bottom surfaces of the second semiconductor oxide features  324 , resulting in an olive shape in a cross-sectional view. By tuning of the thermal oxidation process, selecting a composition and thickness of the second semiconductor material layer  214  and tuning the oxidation temperature, it achieves a target second width w 2  of the second semiconductor oxide feature  324 , which applies an adequate stress to the third semiconductor material layer  216  in the first fin structure  220 , where a gate channel is to be defined underlying a gate region, which will be described later. 
     In one embodiment, the second semiconductor material layer  214  includes silicon germanium (SiGex 1 ) and both of the first and the third semiconductor material layers,  212  and  216 , include silicon (Si). The subscript x 1  is a first Ge composition in atomic percent and it may be adjusted to meet a predetermined volume expansion target. In one embodiment, x 1  is selected in a range from about 20% to about 85%. An outer layer of the SiGex 1  layer  214  is oxidized by the thermal oxidation process, thereby forming the silicon germanium oxide (SiGeO) feature  324 . The second width w 2  of the SiGeO feature  324  is in a range of about 3 nm to 10 nm. A center portion of the SiGex 1  layer  214  changes to a second Ge composition x 2 , which is much higher than x 1 . A size and shape of the center portion of SiGex 2  vary with process conditions, such as thermal oxidation temperature and time. Also the second Ge composition x 2  in the center portion is higher than other portions, such as a top portion, a bottom portion, a left side portion and a right side portion. 
     Referring to  FIGS. 1 and 6A-6B , the method  100  proceeds to step  110  by depositing a dielectric layer  410  over the substrate  210 , including filling in the trench  230 , in both of the NFET  200 A and the PFET  200 B. First, the patterned OHM layer  310  is removed by an etching process, such as a selective wet etch. The dielectric layer  410  may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. The dielectric layer  410  may be deposited by CVD, physical vapor deposition (PVD), ALD, thermal oxidation, other suitable techniques, or a combination thereof. 
     Referring to  FIGS. 1 and 7A-7B , the method  100  proceeds to step  112  by covering the NFET  200 A with a patterned hard mask (HM) layer  415 , forming a third fin structure  440  in the PFET device  200   b . The patterned HM layer  415  may include silicon nitride, silicon oxynitride, silicon carbide, or any other suitable dielectric material. The patterned HM layer  415  may be formed similarly to forming of the patterned OHM layer  310  in step  106 . In the present embodiment, the patterned HM layer  415  covers the NFET device  200 A and leave the PFET device  200 B be un-covered. 
     In the PFET device  200 B, the third semiconductor material layer  216  in the first fin structure  220  is recessed by a proper etching process, such as a selective wet etch, a selective dry etch, or a combination thereof. In present embodiment, the recessing process is controlled to leave the remaining third semiconductor material layer  216  have a first height hi for gaining process integration flexibility. The fourth semiconductor material layer  430  is then deposited over the recessed third semiconductor material layer to form a third fin structure  440 . The fourth semiconductor material layer  430  may be deposited by epitaxial growth. The epitaxial process may include CVD deposition techniques, molecular beam epitaxy, and/or other suitable processes. The fourth semiconductor material layer  430  may include germanium (Ge), silicon (Si), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), or other suitable materials. In the present embodiment, the fourth semiconductor material layer  430  is same as the second semiconductor material layer  214 , SiGe. Thus the third fin structure  440  is formed to have the fourth semiconductor material layer  430  as its upper portion, the third semiconductor material layer  216  as its upper middle portion, the second semiconductor material layer  214  as its lower middle portion and the first semiconductor material layer  212  as its bottom portion. 
     A CMP process may be performed thereafter to remove excessive the fourth semiconductor material layer  430  and planarize the top surface of the PFET device  200 B. The HM layer  415  in the NFET device  200 A is removed by a proper etching process, such as a wet etch, a dry etch, or a combination thereof. 
     Referring to  FIGS. 1 and 8A-8E , the method  100  proceeds to step  114  by recessing the dielectric layer  410  in both of the NFET device  200 A and the PFET device  200 B. First, the patterned HM layer  415  is removed from the NFET device  200 A by a proper etching process, such as a selective wet etch, or a selective dry etch. The dielectric layer  410  is then recessed in both of the NFET device  200 A and the PFET device  200 B to expose the upper portion of the first fin structure  220  (in the NFET device  200 A) and the upper portion of the third fin structure  440  (in the PFET device  200 B). In the present embodiment, the recessing processes are controlled to have a top surface of the remaining dielectric layer  410  above the second semiconductor material layer  214  with a first distance di for gaining process integration flexibility. In the present embodiment, the remaining dielectric layer  410  in the trench  230  forms shallow trench isolation (STI) features. 
     In some embodiments, the SRAM FinFET device  200  includes source/drain (S/D) regions and gate regions. In furtherance of the embodiment, one of the S/D regions is a source region, and another of the S/D regions is a drain region. The S/D regions are separated by the gate region. For the sake of clarity to better description, the S/D regions and the gate regions in the NFET device  200 A are referred to as a first S/D regions  450 A and a first gate regions  460 A; the S/D regions and the gate regions in the PFET device  200 B are referred to as a second S/D regions  450 B and a second gate regions  460 B. 
     Referring to  FIG. 9A , in the NFET device  200 A, the first S/D regions  450 A are separated by the first gate regions  460 A. In the present embodiment, the first S/D region  450 A includes a first subset of the first S/D regions  450 AA and a second subset of the first S/D regions  450 AB. The first subset of the first S/D regions  450 AA are formed in the second region  314  and the second subset of the first S/D regions  450 AB are formed in both of the first region  312  and the second region  314 , such that the first region  312  locates in the middle and the second region  314  locates symmetrically beside the first region  312 . The first gate regions  460 A are formed in the second region  314 . The second region  314  includes the second fin structure  320 . The first region  312  includes the first fin  220 . 
     In the present embodiment, the second semiconductor material layer  214  in the first region  312  is referred to as an anchor  470 . The second subset of the first S/D region  450 AB has a first space s 1 . A difference between a width of the anchor  470  and the first space s 1  is a second space s 2 . The second space s 2  is in a range of about 10% to about 25% of the first space s 1 . The anchor  470  is designed to be between two first gate regions  460 A in a periodic matter, such as every two first gate regions  460 A, or every three first gate regions  460 A, or every fourth first gate regions  460 A, and so on. 
     Referring to  FIG. 9B , in the PFET device  200 B, the second S/D regions  450 B are separated by the second gate regions  460 B. The second S/D regions  450 B and the second gate region  460 B are formed in the first region  312 . The first region  312  includes the first fin structure  220 . 
     Referring to  FIGS. 1 and 10A-10B , the method  100  proceeds to step  116  by forming a gate stack  510  and sidewall spacers  520  on sidewalls of the gate stack  510 , in the first and second gate regions,  460 A and  460 B. In one embodiment using a gate-last process, the gate stack  510  is a dummy gate and will be replaced by the final gate stack at a subsequent stage. Particularly, the dummy gate stacks  510  are to be replaced later by a high-k dielectric layer (HK) and metal gate electrode (MG) after high thermal temperature processes, such as thermal annealing for S/D activation during the sources/drains formation. The dummy gate stack  510  is formed on the substrate  210  and is partially disposed over the second fin structure  320  in the first gate region  460 A and the third fin structure  440  in the second gate region  460 B. In one embodiment, the dummy gate stack  510  includes a dielectric layer, an electrode layer  514  and a gate hard mask (GHM)  516 . The dummy gate stack  510  is formed by a suitable procedure including deposition and patterning. The patterning process further includes lithography and etching. In various examples, the deposition includes CVD, physical vapor deposition (PVD), ALD, thermal oxidation, other suitable techniques, or a combination thereof. The lithography process includes photoresist (or resist) coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, and/or combinations thereof. The etching process includes dry etching, wet etching, and/or other etching methods (e.g., reactive ion etching). 
     The dielectric layer includes silicon oxide. Alternatively or additionally, the dielectric layer may include silicon nitride, a high-k dielectric material or other suitable material. The electrode layer  514  may include polycrystalline silicon (polysilicon). The GHM  516  includes a suitable dielectric material, such as silicon nitride, silicon oxynitride or silicon carbide. The sidewall spacers  520  may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof. The sidewall spacers  520  may include a multiple layers. Typical formation methods for the sidewall spacers  520  include depositing a dielectric material over the gate stack  510  and then anisotropically etching back the dielectric material. The etching back process may include a multiple-step etching to gain etch selectivity, flexibility and desired overetch control. 
     Referring again to  FIGS. 1 and 10A-10B , the method  100  proceeds to step  118  by forming a first S/D features  610 A in the first S/D regions  450  A and a second S/D features  610 B in the second S/D regions  450 B. In one embodiment, the first S/D features  610 A is formed by recessing a portion of the upper portion of the first fin structures  220  in the first subset of the first S/D region  450 AA and the second fin structures  320  in the second subset of the first S/D region  450 AB. The second S/D features  610 B is formed by recessing a portion of the upper portion of the third fin structures  440  in the second S/D region  450 B. In one embodiment, the first fin structure  220 , the second fin structure  320  and the third fin structure  440  are recessed in one etching process. In another embodiment, the first fin structure  220 , the second fin structure  320  and the third fin structure  440  are recessed in different etching processes. In present embodiment, for gaining process integration flexibility. the recessing process is controlled to have a portion of the third semiconductor material layer  216  remain in the first fin structure  220  and the second fin structure  320  and have a portion of the fourth semiconductor material layer  430  remain in the third fin structure  440 . 
     The first S/D features  610 A and the second S/D features  610 B are then epitaxially grow on the recessed first fin structure  220  in the first subset of the first S/D region  450 AA, the recessed second fin structure  320  in the second subset of first S/D region  450 AB and the recessed third fin structure  440  in the second S/D region  450 B. The first and the second S/D features,  610 A and  610 B, include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, or other suitable material. The first and the second S/D features,  610 A and  610 B, may be formed by one or more epitaxy or epitaxial (epi) processes. The first and the second S/D features,  610 A and  610 B, may also be doped, such as being in-situ doped during the epi processes. Alternatively, the first and the second S/D features,  610 A and  610 B, are not in-situ doped and implantation processes (i.e., a junction implant process) are performed to dope the first and the second S/D features,  610 A and  610 B. 
     In one embodiment, the first S/D features  610 A is formed by the epitaxially grown Si layer doped with carbon to form Si:C z  as a lower portion of the first S/D features  610 A and the epitaxial grown Si layer doped with phosphorous to form Si:P as an upper portion of the first S/D features  610 A, where z is carbon composition in atomic percent. In one embodiment, z is in a range of about 0.5% to about 1.5%. The Si:C z  has a thickness, which is in a range of about 5 nm to about 15 nm. The Si:P has a thickness, which is in a range of about 20 nm to 35 nm. In another embodiment, the second S/D features  610 B is formed by the epitaxially grown SiGe layer doped with boron to form SiGe a B, where a is germanium composition in atomic percent. In one embodiment, a is in a range of about 60% to about 100%. 
     Referring to  FIGS. 1 and 11A-11B , the method  100  proceeds to step  120  by forming an interlayer dielectric (ILD) layer  720  on the substrate  210  between the gaps of the dummy gate stacks  510 . The ILD layer  720  includes silicon oxide, silicon oxynitride, low k dielectric material or other suitable dielectric materials. The ILD layer  720  may include a single layer or alternative multiple layers. The ILD layer  720  is formed by a suitable technique, such as CVD, ALD and spin-on (SOG). A chemical mechanical polishing (CMP) process may be performed thereafter to remove excessive ILD layer  720  and planarize the top surface of the SRAM FinFET device  200 . 
     Referring also to  FIGS. 1 and 11A-11B , the method  100  proceeds to step  122  by removing the dummy gate stacks  510  in the first gate region  460 A to form one or more first gate trench  810 A and in the second gate region  460 B to form one or more second gate trench  810 B. The upper portion of the second fin structure  320  is exposed in the first gate trench  810 A and the upper portion of the third fin structure  440  is exposed in the second gate trench  810 B. The dummy gate stacks  510  are removed by an etch process (such as selective wet etch or selective dry etch) designed to have an adequate etch selectivity with respect to the third semiconductor material layer  216  in the first gate trench  810 A and the fourth semiconductor material layer  430  in the second gate trench  810 B. The etch process may include one or more etch steps with respective etchants. The gate hard mask layer  516  and the spacers  520  are removed as well. Alternatively, the dummy gate stack  510  may be removed by a series of processes including photolithography patterning and etching process. 
     Referring to  FIGS. 1 and 12A-12B , the method  100  proceeds to step  124  by forming a first and a second high-k/metal gate (HK/MG) stacks,  910 A and  910 B, over the substrate  210 , including wrapping over a portion of the second fins structure  320  in the first gate trench  810 A and a portion of the third fin structure  440  in the second gate trench  810 B, respectively. The first and the second HK/MG stacks,  910 A and  910 B, include gate dielectric layer and gate electrode on the gate dielectric. In one embodiment, the gate dielectric layer includes a dielectric material layer having a high dielectric constant (HK dielectric layer-greater than that of the thermal silicon oxide in the present embodiment) and the gate electrode includes metal, metal alloy or metal silicide. The formation of the first and the second HK/MG stacks,  910 A and  910 B, includes depositions to form various gate materials and a CMP process to remove the excessive gate materials and planarize the top surface of the NFET device  200 A and the PFET device  200 B. 
     In one embodiment, the gate dielectric layer includes an interfacial layer (IL) deposited by a suitable method, such as atomic layer deposition (ALD), CVD, thermal oxidation or ozone oxidation. The IL includes oxide, HfSiO and oxynitride. A HK dielectric layer is deposited on the IL by a suitable technique, such as ALD, CVD, metal-organic CVD (MOCVD), physical vapor deposition (PVD), other suitable technique, or a combination thereof. The HK dielectric layer may include LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitrides (SiON), or other suitable materials. The gate dielectric layers wrap over the upper portion of the second fin structures  320  in the first gate region  460 A and the upper portion of the third fin structures  440  in the second gate region  460 B. 
     A metal gate (MG) electrode may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a work function to enhance the device performance (work function metal layer), liner layer, wetting layer, adhesion layer and a conductive layer of metal, metal alloy or metal silicide). The MG electrode may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, any suitable materials or a combination thereof. The MG electrode may be formed by ALD, PVD, CVD, or other suitable process. The MG electrode may be formed separately for the NFET  200 A and the PFET  200 B with different metal layers. A CMP process may be performed to remove excessive MG electrode. 
     Referring to  FIG. 13A , in the NFET device  200 A, the first gate region  460 A includes the first HM/MG  910 A, which wraps over the upper portion of the second fin structure  320 . The second fin structure  320  includes the semiconductor material layer  216  as its upper portion, the second semiconductor material layer  214  (with a semiconductor oxide feature  324  at its outer layer) as its middle portion, and the first semiconductor material layer  212  as its bottom portion. Therefore, during forming the second semiconductor oxide feature  324  in the second fin structure  320 , a proper strain is induced to the first gate region  460 A and it will increase mobility in a channel region in the first gate region  460 A. In the present embodiment, the second subset of the first S/D region  450 AB, equipped with the anchors  470  in a periodical matter, which will enhance strain induced to the first gate region  460 A and mobility in the channel region. The second space s 2  provides an adequate separation between the anchor  470  and the first gate region  460 A to avoid adverse impacts, such as induced interface states in the first HK/MG  910  by the anchor  470 . 
     Referring to  FIG. 13B , in the PFET device  200 B, the second S/D region  450 B are separated by the second gate region  460 B. The second gate region  460 B includes the second HK/MG  910 B wraps over the upper portion of the third fin structure  440 . The third fin structure  440  includes the fourth semiconductor material layer  430  as its upper portion, the third semiconductor material layer  216  as its upper middle portion, the second semiconductor material layer  214  as its lower middle portion, and the first semiconductor material layer  212  as its bottom portion. 
     The SRAM FinFET device  200  may undergo further CMOS or MOS technology processing to form various features and regions known in the art. For example, subsequent processing may form various contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate  210 , configured to connect the various features to form a functional circuit that includes one or more SRAM FinFET field-effect transistors. In furtherance of the example, a multilayer interconnection includes vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may implement various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. 
     Additional operations may be implemented before, during, and after the method  100 , and some operations described above may be replaced or eliminated for other embodiments of the method. 
     Based on the above, the present disclosure offers structures of a SRAM FinFET. The structures employ technique of volume expansion and periodic anchor structures in its NFET device to induce an efficient strain to the gate region to improve device performance. 
     The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having an n-type FinFET (NFET) region and a p-type FinFET (PFET) region. The device also includes a first fin structure over the substrate in the NFET region, a second fin structure over the substrate in the NFET region and a third fin structure over the substrate in the PFET region. The device also includes a first high-k (HK)/metal gate (MG) stack over the substrate in the NFET region, including wrapping over a portion of the first fin structure. The device also includes a first subset of source/drain (S/D) features, adjacent to the first HK/MG stack, over the recessed first fin structure m a second subset of S/D features partially over the recessed second fin structure and partially over the recessed first fin structure, which around the recessed second fin structure, adjacent to another first HK/MG stack. The device also includes a second HK/MG)stack over the substrate in the PFET region, including wrapping over a portion of the third fin structure and a second S/D features, adjacent to the second HK/MG stack, over the recessed third fin structure in the PFET region. 
     The present disclosure also provides another embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having an n-type fin-like field-effect transistor (NFET) region and a p-type fin-like field-effect transistor (PFET) region. The device also includes a first fin structure over the substrate in the NFET gate region. The first fin structure includes an epitaxial silicon (Si) layer as its upper portion and an epitaxial silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its lower portion. The device also includes a second fin structure over the substrate in the NFET region. The second fin structure includes an epitaxial silicon (Si) layer as its upper portion and an epitaxial silicon germanium (SiGe) as its lower portion. The device also includes a third fin structure over the substrate in the PFET region. The third fin structure includes an epitaxial SiGe layer as its upper portion, an epitaxial Si as its middle portion and another epitaxial SiGe layer as its bottom portion. The device also includes a first subset of source/drain (S/D) regions in a portion of the first fin structure, a second subset of S/D regions in a portion of the second fin structure, which is surrounded by the first fin structure and a second S/D regions in a portion of the third fin structures. 
     The present disclosure also provides a method for fabricating a FinFET. The method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and a p-type fin-like field-effect transistor (PFET) region. The method also includes forming first fin structures in the NFET region and the PFEN region. The first fin structure includes a first epitaxial semiconductor material layer as its upper portion, a second epitaxial semiconductor material layer, with a semiconductor oxide feature at its outer layer, as its middle portion and a third semiconductor material layer as its bottom portion. The method also includes forming a patterned oxidation-hard-mask (OHM) over the NFET region and PFEN region to expose the first fin structure in a first gate region of the NFET region, applying annealing to form a semiconductor oxide feature at out layer of the second semiconductor material layer in the first fin structure in the first gate region, depositing a dielectric layer between the first fins, forming a third fin structure in the PNFET device while covering the NFET device with a hard mask layer, recessing the dielectric layer in both of the NFET region and the PFET region, forming dummy gates in a first gate region and a second gate region in the second fin structure, forming a first source/drain (S/D) features in a first S/D region in the first fin structure and in the second fin structure in the NFET region and forming a second S/D feature in a second S/D region in the third fin structure in the PFET region. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.