Patent Publication Number: US-2012037924-A1

Title: Junction Field-Effect Transistor

Description:
TECHNICAL FIELD 
     The present invention relates to a junction field-effect transistor, and more specifically, it relates to a junction field-effect transistor capable of easily controlling the threshold voltage and capable of easily controlling a saturation current flowing in a channel region. 
     BACKGROUND ART 
     Silicon carbide (hereinafter abbreviated as SiC), having a wide band gap and a maximum insulation field larger by about one digit as compared with silicon (hereinafter abbreviated as Si), is a material expected for application to next-generation power semiconductor devices. SiC has heretofore been applied to various electronic devices through single-crystalline wafers referred to as 4H-SiC or 6H-SiC, and is regarded as suitable to high-temperature/high-power devices in particular. The aforementioned crystal is alpha-phase SiC formed by stacking zinc blende and wurtzite. Semiconductor devices have also been experimentally manufactured through a beta-phase SiC crystal referred to as 3C-SiC. A Schottky diode, a MOSFET (metal oxide semiconductor field-effect transistor), thyristor etc. serving as power devices or a CMOS (complementary mental-oxide semiconductor)-IC (integrated circuit), which is the most versatile semiconductor device, has recently been experimentally manufactured, and it has been confirmed from the characteristics thereof that the characteristics are extremely excellent as compared with conventional Si semiconductor devices.  FIG. 6  is a sectional view showing the structure of a conventional junction field-effect transistor. As shown in  FIG. 6 , the conventional junction field-effect transistor  120  comprises a p-type semiconductor layer  107 , an n-type semiconductor layer  101 , a p +  buried layer  105 , a p +  region  104 , n +  regions  108   a  and  108   b,  a gate electrode  111 , a source electrode  113  and a drain electrode  115 . 
     The n-type semiconductor layer  101  is formed on the p-type semiconductor layer  107  by epitaxy, and the p +  buried layer  105  is formed on a deep position around the boundary between the p-type semiconductor layer  107  and the n-type semiconductor layer  101 . The p +  region  104  and the n +  regions  108   a  and  108   b  are formed on the surface of the n-type semiconductor layer  101 . The gate electrode  111 , the source electrode  113  and the drain electrode  115  are formed on the surface of the n-type semiconductor layer  101 . The gate electrode  111  and the p +  region  104  are electrically connected with each other, the source electrode  113  and the n +  region  108   a  are electrically connected with each other, and the drain electrode  115  and the n +  region  108   b  are electrically connected with each other. 
     In the junction field-effect transistor  120 , the n-type semiconductor layer  101  located immediately under the p +  region  104  serves as a channel. In other words, a negative voltage is so applied to the gate electrode  111  that a depletion layer  117  spreads in the n-type semiconductor layer  101  from the boundary between the n-type semiconductor layer  101  and the p +  region  104  toward the boundary between the n-type semiconductor layer  101  and the p +  buried layer  105  and a current between the drain electrode  115  and the source electrode  113  is cut off in a case of a normally-on transistor. In a case of a normally-off transistor, a positive voltage is so applied to the gate electrode  111  that the depletion layer  117  shrinks in the n-type semiconductor layer  101  from the boundary between the n-type semiconductor layer  101  and the p +  buried layer  105  toward the boundary between the n-type semiconductor layer  101  and the p +  region  104  and a current flows between the drain electrode  115  and the source electrode  113 . For example, Patent No. 3216804 (Japanese Patent Laying-Open No. 11-195655 (Patent Literature 1)) discloses a junction field-effect transistor similar to the aforementioned structure. 
     Patent Document 1: Patent No. 3216804 (Japanese Patent Laying-Open No. 11-195655) 
     DISCLOSURE OF THE INVENTION 
     Problems to be Solved by the Invention 
     Referring to  FIG. 6 , an dopant diffusion rate in SiC is so extremely slow that it takes an extremely long time for diffusing dopants into the n-type semiconductor layer  101  in order to form the p +  region  104  and the p +  buried layer  105  by thermal diffusion, if the n-type semiconductor layer  101  is composed of SiC. Therefore, the p +  region  104  and the p +  buried layer  105  are generally formed by implanting dopant ions into the n-type semiconductor layer  101  (ion implantation). When ion implantation is employed, the implanted dopants have prescribed concentration profiles in the depth direction. Therefore, the number of electrons in the n-type semiconductor layer  101  is reduced due to action of the implanted dopant ions. This is now described. 
       FIG. 7  schematically illustrates concentration profiles along the line A 4 -A 4  in  FIG. 6 . Referring to  FIG. 7 , dopant ions implanted for forming the p +  region  104  have a concentration profile denoted by c 3  in the depth direction. Similarly, dopant ions implanted for forming the p +  buried layer  105  have a concentration profile denoted by d 3  in the depth direction. As obvious also from the concentration profile c 3  of the dopant ions, the dopant ions implanted for forming the p +  region  104  partially reach a region for forming the n-type semiconductor layer  101  without remaining in a region for forming the p +  region  104 . When the dopant ions reach the region for forming the n-type semiconductor layer  101 , minority carriers (holes) resulting from the dopants and majority carriers (electrons) present in the n-type semiconductor layer  101  recombine with each other, to reduce the number of the majority carriers present in the n-type semiconductor layer  101 . Similarly, the dopant ions implanted for forming the p +  buried layer  105  partially remain in the region for forming the n-type semiconductor layer  101  without reaching a region for forming the p +  buried layer  105 , as obvious also from the concentration profile d 3  of the dopant ions. Thus, the dopant ions reduce the number of electrons present in the n-type semiconductor layer  101 . When the concentration of electrons originally present in the n-type semiconductor layer  101  is expressed by a one-dot chain line b 3  in  FIG. 7 , the concentration of electrons actually present in the n-type semiconductor layer  101  is expressed by the difference between the concentration b 3  of the electrons originally present in the n-type semiconductor layer  101  and the concentration profiles c 3  and d 3  of the dopant ions, i.e., the area of a region e 3 . Since the axis of ordinates in  FIG. 7  is on a logarithmic scale, the concentration of the electrons actually present in the n-type semiconductor layer  101  is approximately expressed by the length f 3  of the uppermost portion in the region e 3 . 
     Ion implantation has such a disadvantage that it is difficult to control concentration profiles of dopant ions in the depth direction. Therefore, the concentration profile c 3  of the dopant ions is dispersable in the depth direction, as shown by dotted lines in  FIG. 7  (similarly, the concentration profile d 3  of the dopant ions is also dispersable in the depth direction, while this is not illustrated). When the concentration profile c 3  of the dopant ions is dispersed in the depth direction, the number of dopant ions reaching the n-type semiconductor layer  101  changes to influence the decrement of the electron concentration f 3  (e 3 ). 
     More specifically, the concentration profile c 3  slides to the left dotted line in the figure and the electron concentration f 3  (e 3 ) exceeds the design value when the dopant ions are implanted into a region shallower than the design value. When the dopant ions are implanted into a region deeper than the design value, on the other hand, the concentration profile c 3  slides to the right dotted line in the figure, and the electron concentration f 3  (e 3 ) falls below the design value. 
     Since the n-type semiconductor layer  101  is a portion serving as the channel of the junction field-effect transistor  120  as hereinabove described, the aforementioned change of the electron concentration f 3  (e 3 ) influences the threshold voltage of the transistor and the saturation current density of the channel. Therefore, there has been such a problem in the conventional junction field-effect transistor that the threshold voltage and the saturation current density of the channel are hard to control. 
     This problem is not a problem caused only in a junction field-effect transistor employing SiC but a problem caused in general junction field-effect transistors. In the case of SiC, however, the dopant concentration profile tends to increase (tends to tail) in a deep portion, and hence this problem is particularly important. 
     Accordingly, an object of the present invention is to provide a junction field-effect transistor capable of easily controlling the threshold voltage and capable of easily controlling saturation current density of a channel. 
     Means for Solving the Problems 
     The junction field-effect transistor according to the present invention comprises a first conductivity type semiconductor layer having a channel region, a buffer layer formed on the channel region and a second conductivity type doped region formed on the buffer layer. A first conductivity type carrier concentration in the buffer layer is lower than a first conductivity type carrier concentration in the first conductivity type semiconductor layer. 
     According to the inventive junction field-effect transistor, relatively high-concentration dopant ions are implanted into the buffer layer in formation of the second conductivity-type doped region. However, the number of first conductivity type carriers present in the buffer layer is originally small, whereby the number of the carriers hardly decreases in the buffer layer. Further, relatively low-concentration dopant ions are implanted into the first conductivity type semiconductor layer, whereby the number of first conductivity type carriers in the first conductivity type semiconductor layer hardly decreases. In other words, the concentration of the first conductivity type carriers present in the channel region is hardly influenced in formation of the second conductivity type doped region. Also when the concentration profile of second conductivity type dopant ions is dispersed in the depth direction in formation of the second conductivity type doped region, therefore, the concentration of the first conductivity type carriers present in the channel region is hardly influenced. Consequently, the threshold voltage can be easily controlled, and the saturation current of the channel can be easily controlled. 
     Preferably in the junction field-effect transistor according to the present invention, the first conductivity type carrier concentration in the buffer layer is not more than one tenth of the first conductivity type carrier concentration in the first conductivity type semiconductor layer. 
     Thus, the number of carriers present in the buffer layer is sufficiently reduced as compared with the number of carriers present in the first conductivity type semiconductor layer, whereby the number of carriers reduced by dopant implantation decreases to an ignorable extent. 
     Preferably in the junction field-effect transistor according to the present invention, the first conductivity type semiconductor layer is composed of SiC. 
     SiC, having a wide band gap and a maximum insulation field larger by about one digit as compared with Si, is suitable as the material for the junction field-effect transistor. In ion implantation into SiC, further, the quantity of dopant implantation is particularly dispersable in the depth direction. Therefore, the structure of the present invention is particularly effective. 
     Preferably, the junction field-effect transistor according to the present invention further comprises a second conductivity type semiconductor layer formed under the channel region. 
     Thus, it is possible to feed no current to the channel region by extending a depletion layer on the boundary between the first conductivity type semiconductor layer and the second conductivity type doped region toward the second conductivity type semiconductor layer. 
     Preferably in the junction field-effect transistor according to the present invention, the second conductivity type semiconductor layer is formed by implanting an dopant, and the junction field-effect transistor further comprises another buffer layer formed under the channel region on the second conductivity type semiconductor layer. A first conductivity type carrier concentration in another buffer layer is lower than the first conductivity type carrier concentration in the first conductivity type semiconductor layer. 
     Thus, relatively high-concentration dopant ions are implanted into another buffer layer in formation of the second conductivity type semiconductor layer. However, the number of first conductivity type carriers present in another buffer layer is originally small, whereby the number of carriers hardly decreases in another buffer layer. Further, relatively low-concentration dopant ions are implanted into the first conductivity type semiconductor layer, whereby the number of first conductivity type carriers in the first conductivity type semiconductor layer hardly decreases. In other words, the concentration of the first conductivity type carriers present in the channel region is hardly influenced in formation of the second conductivity type semiconductor layer. Also when the concentration profile of second conductivity type dopant ions is dispersed in the depth direction in formation of the second conductivity type semiconductor layer, therefore, the concentration of the first conductivity type carriers present in the first conductivity type semiconductor layer is hardly influenced. Consequently, control of the threshold voltage is simplified, and the saturation current of the channel can be controlled. 
     Preferably in the junction field-effect transistor according to the present invention, the first conductivity type carrier concentration in the aforementioned another buffer layer is not more than one tenth of the first conductivity type carrier concentration in the first conductivity type semiconductor layer. 
     Thus, the number of carriers present in another buffer layer is sufficiently reduced as compared with the number of carriers present in the first conductivity type semiconductor layer, whereby the number of carriers reduced by dopant implantation decreases to an ignorable extent. 
     Preferably, the junction field-effect transistor according to the present invention further comprises a semiconductor substrate composed of n-type SiC. The first conductivity type semiconductor layer is formed on one main surface of this semiconductor substrate. 
     A semiconductor substrate composed of n-type SiC has lower density of defects such as micropipes (through dislocations) as compared with a semiconductor substrate composed of p-type SiC. Therefore, the yield can be improved, and a leakage current can be reduced. 
     Preferably, the junction field-effect transistor according to the present invention further comprises a gate electrode formed on the surface of the second conductivity type doped region, an electrode, either a source electrode or a drain electrode, formed on the surface of the first conductivity type semiconductor layer and another electrode, either a drain electrode or a source electrode, formed on another main surface of the semiconductor substrate. 
     Thus, carriers move substantially perpendicularly to the semiconductor substrate, to form the so-called vertical field-effect transistor. 
     Preferably, the junction field-effect transistor according to the present invention further comprises a gate electrode formed on the surface of the second conductivity type doped region, and a source electrode and a drain electrode formed on the surface of the first conductivity type semiconductor layer. 
     Thus, carriers move substantially parallelly to the semiconductor substrate, to form the so-called horizontal field-effect transistor. 
     EFFECTS OF THE INVENTION 
     According to the inventive junction field-effect transistor, the threshold voltage can be easily controlled, and the saturation current density of the channel can be easily controlled. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a sectional view showing the structure of a junction field-effect transistor according to a first embodiment of the present invention. 
         FIG. 2  is a diagram schematically showing concentration profiles along the line A 1 -A 1  in  FIG. 1 . 
         FIG. 3  is a sectional view showing the structure of a junction field-effect transistor according to a second embodiment of the present invention. 
         FIG. 4  is a diagram schematically showing concentration profiles along the line A 2 -A 2  in  FIG. 3 . 
         FIG. 5  is a sectional view showing the structure of a junction field-effect transistor according to a third embodiment of the present invention. 
         FIG. 6  is a sectional view showing the structure of a conventional junction field-effect transistor. 
         FIG. 7  is a diagram schematically showing concentration profiles along the line A 4 -A 4  in  FIG. 6 . 
     
    
    
     DESCRIPTION OF THE REFERENCE SIGNS 
       1  semiconductor layer,  3 ,  18  buffer layer,  4   a,    4   b,    9   a,    9   b,    104  p +  region,  5   a ,  5   b,    105  p +  buried layer,  6  semiconductor substrate,  6   a,    6   b  substrate main surface,  7  n-type epitaxial layer,  8   a,    8   b,    108   a,    108   b  n +  region,  10  p-type epitaxial layer,  11 ,  11   a,    11  b,  111  gate electrode,  13 ,  13   a,    13   b,    113  source electrode,  15 ,  115  drain electrode,  17 ,  17   a,    17   b,    117  depletion layer,  19  p-type region,  20 ,  20   a,    21 ,  120  junction field-effect transistor,  101  n-type semiconductor layer,  107  p-type semiconductor layer. 
     BEST MODES FOR CARRYING OUT THE INVENTION 
     Embodiments of the present invention are now described with reference to the drawings. 
     First Embodiment 
       FIG. 1  is a sectional view showing the structure of a junction field-effect transistor according to a first embodiment of the present invention. As shown in  FIG. 1 , the junction field-effect transistor  20  according to this embodiment comprises a semiconductor substrate  6 , an n-type epitaxial layer  7 , an n-type semiconductor layer  1  as a first conductivity type semiconductor layer, a buffer layer  3 , p +  buried layers  5   a  and  5   b  as second conductivity type semiconductor layers, p +  regions  4   a  and  4   b  as second conductivity type doped regions, n +  regions  8   a  and  8   b,  p +  regions  9   a  and  9   b,  gate electrodes  11   a  and  11   b,  source electrodes  13   a  and  13   b  and a drain electrode  15 . 
     The n-type epitaxial layer  7  is formed on one main surface  6   a  of the semiconductor substrate  6  composed of n-type SiC, and the p +  buried layers  5   a  and  5   b  are formed on the surface of the n-type epitaxial layer  7 . The semiconductor layer  1  is formed on the n-type epitaxial layer  7  and the p +  buried layers  5   a  and  5   b.  The p +  regions  4   a  and  4   b,  the n + regions  8   a  and  8   b  and the p + regions  9   a  and  9   b  are formed on the surface of the semiconductor layer  1 . The n +  region  8   a  and the p +  region  9   a  are formed adjacently to each other, and the n +  region  8   b  and the p + region  9   b  are formed adjacently to each other. The respective ones of the p +  regions  4   a  and  4   b  are formed by implanting dopant ions. The respective ones of the p +  regions  9   a  and  9   b  extend downward in the figure, and reach the respective ones of the p +  buried layers  5   a  and  5   b.    
     The semiconductor layer  1  is composed of SiC. In the semiconductor layer  1 , regions around those located vertically immediately under the respective ones of the p +  regions  4   a  and  4   b  are channel regions of the junction field-effect transistor  120 . The channel regions are formed on the p +  buried layers  5   a  and  5   b    
     The buffer layer  3  is formed in the semiconductor layer  1 . The buffer layer  3  is formed on the channel regions under the p +  regions  4   a  and  4   b.  The electron concentration in the buffer layer  3  is lower than the electron concentration in the semiconductor layer  1 , and the electron concentration in the buffer layer  3  is not more than one tenth of the electron concentration in the semiconductor layer  1 . The buffer layer  3  may be an n −  region, may be an undoped layer, or may be a p −  region. 
     The gate electrodes  11   a  and  11   b  are formed on the surfaces of the respective ones of the p +  regions  4   a  and  4   b.  Further, the source electrode  13   a  is formed on the surfaces of the n +  region  8   a  and the p +  region  9   a,  and the source electrode  13   b  is formed on the surfaces of the n +  region  8   b  and the p +  region  9   b  (the surface of the semiconductor layer  1 ). The drain electrode  15  is formed on another main surface  6   b  (lower side in the figure) of the semiconductor substrate  6 . 
     When the junction field-effect transistor  20  is a normally-on transistor, a negative voltage is so applied to the gate electrodes  11   a  and  11   b  that the respective ones of depletion layers  17   a  and  17   b  spread in the channel regions, and currents between the drain electrode  15  and the respective ones of the source electrodes  13   a  and  13   b  are cut off. When the junction field-effect transistor  20  is a normally-off transistor, a positive voltage is so applied to the gate electrodes  11   a  and  11   b  that the respective ones of the depletion layers  17   a  and  17   b  disappear from the channel regions and currents flow between the drain electrode  15  and the source electrodes  13   a  and  13   b  through the channel regions. 
     According to the junction field-effect transistor  20  of this embodiment, the concentrations of electrons present in the channel regions are hardly influenced in formation of the p +  regions  4   a  and  4   b.  This is now described. 
       FIG. 2  is a diagram schematically showing concentration profiles along the line A 1 -A 1  in  FIG. 1 . Referring to  FIG. 2 , dopant ions implanted for forming the p +  region  4   a  have a concentration profile denoted by c 1  in the depth direction. A one-dot chain line b 1  denotes the concentration profile of carriers (electrons) originally present in the buffer layer  3  and the semiconductor layer  1 . The concentration of electrons actually present in the semiconductor layer  1  is expressed by the difference between the concentration b 1  of electrons originally present in the semiconductor layer  1  (present in the semiconductor layer  1  not yet formed with the doped region therein) and the concentration profile c 1  of the dopant ions, i.e., the area of a region e 1 . Since the axis of ordinates in  FIG. 2  is on a logarithmic scale, the concentration of the electrons actually present in the semiconductor layer  1  is approximately expressed by the length f 1  of the uppermost portion in the region e 1 . 
     According to the concentration profile c 1  of the dopant ions, the concentration of dopant ions present in the semiconductor layer  1  is extremely low as compared with the concentration b 1  of electrons originally present in the semiconductor layer  1 , and the concentration f 1  (el) of electrons actually present in the semiconductor layer  1  is substantially equivalent to the concentration b  1  of electrons originally present in the semiconductor layer  1 . Therefore, the concentrations of electrons present in the channel regions are hardly influenced in formation of the p +  region  4   a.  Since the number of electrons present in the buffer layer  3  is small as compared with the number of electrons present in the semiconductor layer  1 , fluctuation of the number of electrons present in the buffer layer  3  is also small. 
     Also when the concentration profile c 1  of p-type dopant ions is dispersed in the depth direction as shown by dotted lines in the figure in formation of the p +  regions  4   a  and  4   b,  therefore, the concentrations of electrons present in the channel regions are hardly influenced. Consequently, the threshold voltage can be easily controlled, and saturation currents of channels can be easily controlled. 
     In the junction field-effect transistor  20  according to this embodiment, the electron concentration in the buffer layer  3  is not more than one tenth of the electron concentration in the semiconductor layer  1 . 
     Thus, the number of electrons present in the buffer layer  3  is sufficiently reduced as compared with the number of electrons present in the semiconductor layer  1 , whereby the number of electrons reduced by dopant implantation decreases to an ignorable extent. 
     In the junction field-effect transistor  20  according to this embodiment, the semiconductor layer  1  is composed of SiC. 
     SiC, having a wide band gap and a maximum insulation field larger by about one digit as compared with Si, is suitable as the material for the junction field-effect transistor. In ion implantation into SiC, further, the quantity of dopant implantation is particularly dispersable in the depth direction. Therefore, the structure of the present invention is particularly effective. 
     The junction field-effect transistor  20  according to this embodiment further comprises the p +  buried layers  5   a  and  5   b  formed under the channel regions. 
     Thus, it is possible to feed no currents to the channel regions by extending the depletion layers  17   a  and  17   b  on the boundaries between the semiconductor layer  1  and the p +  regions  4   a  and  4   b  toward the p + buried layers  5   a  and  5   b.    
     The junction field-effect transistor  20  according to this embodiment further comprises the semiconductor substrate  6  composed of n-type SiC. The semiconductor layer  1  is formed on one main surface  6   a  of the semiconductor substrate  6 . 
     A semiconductor substrate composed of n-type SiC has lower density of defects such as micropipes (through dislocations) as compared with a semiconductor substrate composed of p-type SiC. Therefore, the yield can be improved, and a leakage current can be reduced. 
     The junction field-effect transistor  20  according to this embodiment further comprises the gate electrodes  11   a  and  11   b  formed on the surfaces of the respective ones of the p + regions  4   a  and  4   b,  the source electrodes  13   a  and  13   b  formed on the surface of the semiconductor layer  1 , and the drain electrode  15  formed on another main surface  6   b  of the semiconductor substrate  6 . 
     Thus, carriers move substantially perpendicularly to the semiconductor substrate  6 , to form the so-called vertical field-effect transistor. 
     Second Embodiment 
       FIG. 3  is a sectional view showing the structure of a junction field-effect transistor according to a second embodiment of the present invention. As shown in  FIG. 3 , the junction field-effect transistor  20   a  according to this embodiment further comprises a buffer layer  18  as another buffer layer. The buffer layer  18  is formed under channel regions of a semiconductor layer  1  on p +  buried layers  5   a  and  5   b.  The electron concentration in the buffer layer  18  is lower than the electron concentration in the semiconductor layer  1 . The electron concentration in the buffer layer  18  is not more than one tenth of the electron concentration in the semiconductor layer  1 . Further, the respective ones of the p +  buried layers  5   a  and  5   b  are formed by implanting dopant ions. 
     The remaining structure of the junction field-effect transistor  20   a  is substantially similar to the structure of the junction field-effect transistor  20  shown in the first embodiment, and hence identical members are denoted by identical reference numerals, and description thereof is skipped. 
     According to the junction field-effect transistor  20   a  of this embodiment, the concentrations of electrons present in the channel regions are hardly influenced in formation of the p +  buried layers  5   a  and  5   b.  This is now described. 
       FIG. 4  is a diagram schematically showing concentration profiles along the line A 2 -A 2  in  FIG. 3 . Referring to  FIG. 4 , dopant ions implanted for forming the p +  buried layer  5   a  have a concentration profile denoted by d 2  in the depth direction. A one-dot chain line b 2  denotes the concentration profile of electrons originally present in the buffer layer  18  and the semiconductor layer  1 . The concentration of electrons actually present in the semiconductor layer  1  is expressed by the difference between the concentration b 2  of electrons originally present in the semiconductor layer  1  and the concentration profile d 2  of the dopant ions, i.e., the area of a region e 2 . Since the axis of ordinates in  FIG. 4  is on a logarithmic scale, the concentration of the electrons actually present in the semiconductor layer  1  is approximately expressed by the length f 2  of the uppermost portion in the region e 2 . 
     According to the concentration profile d 2  of the dopant ions, the concentration of dopant ions present in the semiconductor layer  1  is extremely low as compared with the concentration b 2  of electrons originally present in the semiconductor layer  1 , and the concentration f 2  (e 2 ) of electrons actually present in the semiconductor layer  1  is substantially equivalent to the concentration b 2  of electrons originally present in the semiconductor layer  1 . Therefore, the concentrations of electrons present in the channel regions are hardly influenced in formation of the p +  buried layer  5   a.  Since the number of electrons present in the buffer layer  18  is small as compared with the number of electrons present in the semiconductor layer  1 , fluctuation of the number of electrons present in the buffer layer  18  is also small. 
     Also when the concentration profile d 2  of p-type dopant ions is dispersed in the depth direction as shown by dotted lines in the figure in formation of the p +  buried layers  5   a  and  5   b,  therefore, the concentrations of electrons present in the channel regions are hardly influenced. Consequently, the threshold voltage can be easily controlled, and saturation currents of channels can be easily controlled. 
     In the junction field-effect transistor  20   a  according to this embodiment, the electron concentration in the buffer layer  18  is not more than one tenth of the electron concentration in the semiconductor layer  1 . 
     Thus, the number of electrons present in the buffer layer  18  is sufficiently reduced as compared with the number of electrons present in the semiconductor layer  1 , whereby the number of electrons reduced by dopant implantation decreases to an ignorable extent. 
     Third Embodiment 
       FIG. 5  is a sectional view showing the structure of a junction field-effect transistor according to a third embodiment of the present invention. As shown in  FIG. 5 , the junction field-effect transistor  21  according to this embodiment has a RESURF (reduced surface) structure, and is different from the junction field-effect transistor  20  according to the first embodiment in the following points: 
     In other words, a p-type epitaxial layer  10  is formed on a semiconductor substrate  6 , and a semiconductor layer  1  is formed on the p-type epitaxial layer  10 . A p-type region  19  is formed on the surface of the semiconductor layer  1 , and a buffer layer  3  is formed in the semiconductor layer  1 . P 30   regions  4   a  and  9   a  and n + regions  8   a  and  8   b  are formed on the surface of the p-type region  19 . The p +  region  9   a  reaches the p-type epitaxial layer  10 . A gate electrode  11  is formed on the surface of the p +  region  4   a,  a source electrode  13  is formed on the surfaces of the p +  region  9   a  and the n + region  8   a  (the semiconductor layer  1 ), and a drain electrode  15  is formed on the surface of the n +  region  8   b.  Concentration profiles along the line A 3 -A 3  in  FIG. 5  are similar to the concentration profiles shown in  FIG. 2 . According to this embodiment, a region around that located vertically immediately under the p +  region  4   a  is a channel region of the junction field-effect transistor  21 . 
     When the junction field-effect transistor  21  is a normally-on transistor, a negative voltage is so applied to the gate electrode  11  that a depletion layer  17  spreads in the channel region, and a current between the drain electrode  15  and the source electrode  13  is cut off. When the junction field-effect transistor  21  is a normally-off transistor, a positive voltage is so applied to the gate electrode  11  that each of the depletion layer  17  disappears from the channel region and a current flows between the drain electrode  15  and the source electrode  13  through the channel region. 
     The remaining structure is substantially similar to the structure of the junction field-effect transistor  20  shown in the first embodiment, and hence identical members are denoted by identical reference numerals, and description thereof is skipped. Also in the junction field-effect transistor  21  according to this embodiment, effects similar to those of the junction field-effect transistor  20  shown in the first embodiment can be attained. 
     The junction field-effect transistor  21  according to this embodiment further comprises the gate electrode  11  formed on the surface of the p +  region  4   a  as well as the source electrode  13  and the drain electrode  15  formed on the surface of the semiconductor layer  1 . 
     Thus, carriers move substantially parallelly to the semiconductor substrate  6 , to form the so-called horizontal junction field-effect transistor. 
     It is possible to widen a depletion layer between a gate and a drain by forming the p-type region  19  on the semiconductor layer  1 , as in this embodiment. Thus, the withstand voltage between the gate and the drain can be improved. The p-type region  19  in this embodiment is not an essential component, but the p +  regions  4   a  and  9   a  and the n +  regions  8   a  and  8   b  may be formed on the surface of the semiconductor layer  1  without forming the p-type region  19 . 
     The embodiments disclosed in the above must be considered as illustrative in all points and not restricted. The scope of the present invention is shown not by the aforementioned embodiments but by the scope of claim for patent, and intended to include all corrections and modifications within the meaning and range equivalent to the scope of claim for patent.