Patent Publication Number: US-9424315-B2

Title: Methods and systems for run-time scheduling database operations that are executed in hardware

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is related to the following U.S. Patent Applications and Patents, which are herein incorporated by reference in their entirety: U.S. patent application Ser. No. 11/895,952, filed on Aug. 27, 2007, entitled “Methods and Systems for Hardware Acceleration of Database Operations and Queries,” by Joseph I. Chamdani et al.; U.S. patent application Ser. No. 11/895,998, filed on Aug. 27, 2007, entitled “Hardware Acceleration Reconfigurable Processor for Accelerating Database Operations and Queries,” by Jeremy Branscome et al.; U.S. patent application Ser. No. 11/895,997, filed on Aug. 27, 2007, entitled “Processing Elements of a Hardware Acceleration Reconfigurable Processor for Accelerating Database Operations and Queries,” by Jeremy Branscome et al.; U.S. patent application Ser. No. 12/168,821, filed on Jul. 7, 2008, entitled “Methods and Systems for Generating Query Plans that are Compatible for Execution in Hardware,” by Ravi Krishnamurthy et al.; U.S. patent application Ser. No. 12/144,486, filed on Jun. 23, 2008, entitled “Methods and Systems for Real-time Continuous Updates,” by Kapil Surlaker et al.; U.S. patent application Ser. No. 12/099,131, filed on Apr. 7, 2008, entitled “Accessing Data in a Column Store Database Based on Hardware Compatible Data Structures,” by U.S. patent application Ser. No. 12/099,133, filed on Apr. 7, 2008, entitled “Accessing Data in a Column Store Database Based on Hardware Compatible Indexing and Replicated Reordered Columns,” by Krishnan Meiyyappan et al.; and U.S. patent application Ser. No. 12/144,303, filed on Jun. 23, 2008, entitled “Fast Batch Loading and Incremental Loading of Data into a Database,” by James Shau et al. 
     BACKGROUND 
     Despite their different uses, applications, and workload characteristics, most systems run on a common Database Management System (DBMS) using a standard database programming language, such as Structured Query Language (SQL). Most modern DBMS implementations (Oracle, IBM DB2, Microsoft SQL, Sybase, MySQL, PostgreSQL, Ingress, etc.) are implemented on relational databases, which are well known to those skilled in the art. 
     Typically, a DBMS has a client side where applications or users submit their queries and a server side that executes the queries. On the server side, most enterprises employ one or more general purpose servers. However, although these platforms are flexible, general purpose servers are not optimized for many enterprise database applications. In a general purpose database server, all SQL queries and transactions are eventually mapped to low level software instructions called assembly instructions, which are then executed on a general purpose microprocessor (CPU). The CPU executes the instructions, and its logic is busy as long as the operand data are available, either in the register file or on-chip cache. To extract more parallelism from the assembly code and keep the CPU pipeline busy, known CPUs attempt to predict ahead the outcome of branch instructions and execute down the SQL code path speculatively. Execution time is reduced if the speculation is correct; the success of this speculation, however, is data dependent. Other state-of-the-art CPUs attempt to increase performance by employing simultaneous multithreading (SMT) and/or multi-core chip multiprocessing (CMP). To take advantage of these, changes have to be made at the application or DBMS source code to manually create the process/thread parallelism for the SMT or CMP CPUs. This is generally considered highly undesirable. 
     Unfortunately, general purpose CPUs are not efficient for database applications. Branch prediction is generally not accurate because database processing involves tree traversing and link list or pointer chasing that is very data dependent. Known CPUs employ the well known code-flow (or Von Neumann) architecture, which uses a highly pipelined instruction flow (rather than a data-flow where operand data is pipelined) to operate on data stored in the CPU&#39;s tiny register files. Real database workloads, however, typically require processing gigabytes to terabytes of data, which overwhelms these tiny registers with loads and reloads. On-chip cache of a general purpose CPU is not effective since it&#39;s relatively too small for real database workloads. This requires that the database server frequently retrieve data from its small memory or disk. Accordingly, known database servers rely heavily on squeezing the utilization of their small system memory size and disk input/output (I/O) bandwidth. Those skilled in the art recognize that these bottlenecks between storage I/O, the CPU, and memory are very significant performance factors. 
     However, overcoming these bottlenecks is a complex task because typical database systems consist of several layers of hardware, software, etc., that influence the overall performance of the system. These layers comprise, for example, the application software, the DBMS software, operating system (OS), server processor systems, such as its CPU, memory, and disk I/O and infrastructure. Traditionally, performance has been optimized in a database system horizontally, i.e., within a particular layer. For example, many solutions attempt to optimize various solutions for the DBMS query processing, caching, the disk I/O, etc. These solutions employ a generic, narrow approach that still fails to truly optimize the large performance potentials of the database system, especially for relational database systems having complex read-intensive applications. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. In the figures: 
         FIG. 1  illustrates an exemplary system that is consistent with the principles of the present invention; 
         FIG. 2  illustrates exemplary system topologies that are consistent with the principles of the present invention; 
         FIG. 3A  illustrates a prior art database system and  FIG. 3B  illustrates some of the optimizations of the present invention over the prior art; 
         FIG. 4  illustrates a functional architecture of the custom computing (C2) software of the present invention; 
         FIG. 5  illustrates a protocol stack employed by the C2 software and a Hardware Accelerated Reconfigurable Processor (HARP) of the present invention; 
         FIG. 6  illustrates an exemplary architecture of a HARP; 
         FIG. 7  illustrates a column store database and associated data structures employed by some embodiments of the present invention; 
         FIG. 8  illustrates a table column layout and associated data structures employed by some embodiments of the present invention; 
         FIG. 9  illustrates an exemplary machine code database instruction flow for a SQL query that is consistent with the principles of the present invention; 
         FIG. 10  illustrates an exemplary dataflow for a SQL query through processing elements in the HARP in accordance with the principles of the present invention; 
         FIG. 11  illustrates an exemplary logic flow of the addressing schemes employed in the present invention; 
         FIG. 12  illustrates a structure of the global database virtual address scheme of the present invention; 
         FIG. 13  illustrates an exemplary run-time scheduling by a task manager of database operations in both hardware and software in accordance with the present invention; and 
         FIGS. 14 and 15  illustrate examples of associative accumulation MOPs. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention provide a run-time scheduler that schedules tasks for database queries on one or more execution resources in a dataflow fashion. In some embodiments, the run-time scheduler may comprise a task manager, a memory manager, and a hardware resource manager. When a query is received by a host database management system, a query plan is created for that query. The query plan splits a query into various fragments. These fragments are further compiled into a directed acyclic graph of tasks. Unlike conventional scheduling, the dependency arc in the directed acyclic graph is based on page resources. Tasks may comprise machine code database instructions for execution in hardware to perform functions of the query. Tasks may also comprise software functions or may relate to I/O. 
     The run-time scheduler receives tasks and will identify database virtual address ranges affected by the tasks. The run-time scheduler may then request an intent lock on memory in the hardware resources that correspond to the affected database virtual address ranges. The run-time scheduler will queue the tasks for scheduling arbitration and allocate hardware processing slots based on task progress. The run-time scheduler will check with the hardware resources to determine if it can dispatch that task. If hardware resources are available, then the run-time scheduler dispatches the task, moves the task to a running queue, and waits for a signal from the hardware resources. As tasks are completed by the hardware resources, the run-time scheduler will unlock relevant pages in the task&#39;s workset. When all tasks of a query fragment are done, the run-time scheduler will then notify the host database management system. 
     In other instances, the run-time scheduler may elect to dispatch some of the tasks to a software execution resource, such as the host database management system. In addition, the run-time scheduler may dispatch some tasks to an I/O execution resource as in the case of fetching data from a disk or from a buffer. 
     As part of scheduling the tasks, the run-time schedule may also allocate memory resources as necessary. This may include page swapping from memory to storage, page replacement as well as prefetching on-demand or speculatively. 
     Due to the comprehensive nature of the present inventions in the C2 solution, the figures are presented generally from a high level of detail and progress to a low level of detail. For example,  FIGS. 1-3  illustrate exemplary systems and topologies enabled by the present invention.  FIGS. 4-5  illustrate the architecture of the C2 software.  FIG. 6  illustrates the architecture of a HARP module.  FIGS. 7-8  illustrate the database format and data structures employed by the C2 solution of the present invention.  FIGS. 9-10  illustrate an example execution of a SQL query by the C2 solution of the present invention.  FIG. 11  illustrates an exemplary logic flow of the addressing schemes employed and  FIG. 12  illustrates a structure of the global database virtual address scheme of the present invention.  FIG. 13  illustrates an example of the scheduling performed by a task manager of the present invention.  FIGS. 14-15  illustrate exemplary associative accumulation MOPs that may be used by embodiments of the present invention. 
     Reference will now be made in detail to the exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
       FIG. 13  An Exemplary C2 System 
     The present invention employs a custom computing (C2) solution that provides a significant gain in performance for enterprise database applications. In the C2 solution, a node or appliance may comprise the host (or base) system that is combined with hardware acceleration reconfigurable processors (HARP). These HARPs are specially designed to optimize the performance of database systems and its applications, especially relational database systems and read-intensive applications. 
     A host system may be any standard or pre-existing DBMS system. In general, such systems will comprise a standard general purpose CPU, a system memory, I/O interfaces, etc. 
     The HARPs are coupled to the host system and are designed to offload repetitive database operations from the DBMS running on the host system. The HARPs utilize dataflow architecture processing elements that execute machine code instructions that are defined for various database operations. The C2 solution may employ a node that is scalable to include one HARP, or multiple HARPs. In addition, the C2 solution may use a federated architecture comprising multiple nodes, i.e., multiple DBMS servers that are enhanced with the C2 solution. 
     In some embodiments, the C2 solution employs an open architecture and co-processor approach so that the C2 hardware can be easily integrated into existing database systems. Of note, the hardware acceleration of the C2 solution utilizes novel machine code database instructions to execute certain fragments of a query in a dataflow and using parallel, pipelined execution. 
     In the present invention, the C2 solution also comprises software that orchestrates the operations of the DBMS running on the host system and the HARPs. The C2 software is configured with a flexible, layered architecture to make it hardware and database system agnostic. Thus, the C2 software is capable of seamlessly working with existing DBMSs based on this open architecture. 
     In general, the C2 software receives the query from the DBMS and breaks the query down into query fragments. The C2 software then decides which of these query fragments can be appropriately handled in software (in the C2 software itself or back in the originating DBMS) or, ideally, with hardware acceleration in the HARPs. All or part of the query may be processed by the C2 software and HARPs. 
     In addition, in order to maximize the efficiency of the hardware acceleration, the C2 solution stores its databases in compressed, column-store format and utilizes various hardware-friendly data structures. The C2 solution may employ various compression techniques to minimize or reduce the storage footprint of its databases. The column-store format and hardware-friendly data structures allow the HARPs or C2 software to operate directly on the compressed data in the column-store database. The column-store database may employ columns and column groups that are arranged based on an implicit row identifier (RID) scheme and RID to primary key column mapping to allow for easy processing by the HARPs. The hardware-friendly data structures also allow for efficient indexing, data manipulation, etc. by the HARPs. 
     For example, the C2 solution utilizes a global virtual address space for the entire database to greatly simplify and maximize efficiency of create, read, update, and delete operations of data in a database. In some embodiments, the columns and column groups are configured with a fixed width to allow for arithmetic memory addressing and translation from a virtual address to a physical memory address. On-demand and speculative prefetching may also be utilized by the C2 solution to hide I/O bandwidth latency and maximize HARP utilization. 
     Referring now to  FIG. 1 , an exemplary system  100  of the C2 solution is illustrated. As shown, system  100  may comprise an application  102  that is running on a client  104 , such as a personal computer or other system. Application  102  interfaces a DBMS  106  across a network  108 , such as the Internet, local area network, etc. DBMS  106  may further interface one or more databases stored in storage infrastructure  112 . For purposes of explanation, DBMS  106  and its components may be collectively referred to in this disclosure as a node of system  100 . Although  FIG. 1  shows a single node, system  100  may of course comprise multiple nodes. The various components of  FIG. 1  will now be further described. 
     Application  102  may be any computer software that requests the services of DBMS  106 . Such applications are well known to those skilled in the art. For example, application  102  may be a web browser in which a user is submitting various search requests. Of course, application  102  may be another system or software that is consuming the services of DBMS  106  and submitting queries to DBMS  106 . 
     Client  104  represents the hardware and software that supports the execution of application  102 . Such clients are well known to those skilled in the art. For example, client  104  may be a personal computer or another server. 
     DBMS  106  is any computer software that manages databases. In general, DBMS  106  controls the organization, storage, management, and retrieval of data in a database. As is well known, these types of systems are common for supporting various SQL queries on relational databases (and thus may also be known as a RDBMS). Due to its open architecture, various DBMS systems may be employed by the present invention. Typical examples of DBMSs include Oracle, DB2, Microsoft Access, Microsoft SQL Server, PostgreSQL, and MySQL. 
     In some embodiments, and for purposes of explanation, DBMS  106  is shown comprising C2 software  110  interfacing MySQL software  114  via an API  116 . MySQL software  114  is open source software that is sponsored and provided by MySQL AB and is well known to those skilled in the art. Of course, any DBMS software, such as those noted above, may be employed in the present invention. 
     C2 software  110  orchestrates the execution of a query forwarded from DBMS  106 , and thus, operates in conjunction with MySQL software  114 . For example, in the C2 software  110 , SQL queries are broken down into query fragments and then routed to the most appropriate resource. A query fragment may be handled in C2 hardware, i.e., HARP module  204 . (HARP module  204  is further described with reference to  FIG. 2 .) The query fragment may also be processed in the C2 software itself, or returned for handling by MySQL software  114 . 
     In general, C2 software  110  utilizes a flexible, layered architecture to make it hardware and database system agnostic. For example, C2 software  110  may operate as a storage engine of MySQL software  114 . As is well known, MySQL software  114  may provide an API  116  for storage engines, which can interface with C2 software  110 . API  116  comprises the software that specifies how the C2 software  110  and MySQL software  114  will interact, how they will request services from each other, such as SQL queries and results. 
     As a storage engine, C2 software  110  may employ the MySQL API  116  to provide various storage mechanisms, indexing facilities, locking levels, and ultimately provide a range of different functions and capabilities that are transparent to MySQL software  114 . As noted above, this is one aspect of how the present invention overcomes the generic approach in known solutions without having to sacrifice performance for functionality, or fine tune the database. Of note, although  FIG. 1  shows a single storage engine, MySQL software  114  may be coupled to multiple storage engines (not shown) in addition to C2 software  110 . C2 software  110  is also described in further detail with reference to  FIGS. 4-5 . 
     Network  108  represents the communication infrastructure that couples application  102  and DBMS  106 . For example, network  108  may be the Internet. Of course, any network, such as a local area network, wide area network, etc., may be employed by the present invention. 
     Storage infrastructure  112  comprises the computer storage devices, such as disk arrays, tape libraries, and optical drives that serve as the storage for the databases of system  100 . Storage infrastructure  112  may employ various architectures, such as a storage area network, network attached storage, etc., which are known to those skilled in the art. 
     In some embodiments, the C2 solution stores its databases in storage infrastructure  112  in column-store format. Column-store format is where data is stored in columns or groups of columns. Column-store format is advantageous for data fetching, scanning, searching, and data compression. The column-store format may employ fixed width columns and column groups with implicit RIDs and a RID to primary key column to allow for arithmetic memory addressing and translation. This allows HARPs  204  to utilize hardware processing for database processing, such as column hopping, and to operate directly on the compressed data in the columns. 
     In contrast, in typical DBMS environments, data is stored in row-store format. Row-store format is sometimes considered by those skilled in the art for having better performance in data updates and record retrieval; thus, it is sometimes considered to have better functionality over column-store databases in most applications with a high ratio of updates over reads. In the present invention, however, the C2 solution achieves better performance by using hardware acceleration with a column-store database, yet it still delivers the functionality and benefits of row-store databases. The column store format used by the C2 solution of the present invention is further described with reference to  FIGS. 7-8 . 
       FIG. 2 —System Topologies 
       FIG. 2  illustrates exemplary system topologies that are consistent with the principles of the present invention. As shown,  FIG. 2  illustrates a basic C2 node topology, a scale up C2 node topology, and a scale out topology. These various topologies may be utilized to customize the C2 solution for various sizes of databases and desired performance. In addition, these topologies are provided to illustrate that the C2 solution can be easily scaled up to virtually any size of database or performance. 
     First, the basic C2 node will be explained, which comprises a single host system  202  and a single HARP module  204 . Variations of this basic node will then be explained to show how the basic node can be scaled up and how multiple nodes can be employed in a federated architecture. 
     The basic C2 node topology may comprise a host system  202  and a hardware acceleration reconfigurable processor (HARP) module  204 . Collectively, host  202  and HARP module  204  may be referred to as a node or appliance. In some embodiments, host system  202  and HARP module  204  are coupled together over a known communications interface, such as a PCIe or hypertransport (HT) interface. In terms of packaging, host system  202  and HARP module  204  may be built on one or more cards or blades that are bundled together in a common chassis or merely wired together. In the C2 solution, host system  202  and HARP module  204  may be flexibly packaged using a modular form factor for ease of installation and scaling. 
     The host system  202  may comprise a general purpose CPU, such as a Xeon x86 processor by the Intel Corporation, and a memory, such as a dynamic random access memory. Such types of host systems are well known to those skilled in the art. In general, in the C2 solution, host system  202  will be used to process parts of a query that are less time consuming (i.e., slow path portion), such as server-client connection, authentication, SQL parsing, logging, etc. However, in order to optimize performance, the bulk of query execution (i.e., the fast path portion) is offloaded to the HARP module  204 . 
     Host system  202  may run MySQL software  114  and also run C2 software  110  that orchestrates query processing between MySQL  114  and HARP  204 . In particular, C2 software  110  will decompose a query into a set of query fragments. Each fragment comprises various tasks, which may have certain dependencies. C2 software  110  will determine which fragments and tasks are part of the fast path portion and offload them to the HARP module  204 . Appropriate tasks for the selected query fragments are sent to HARP module  204  with information on the database operation dependency graph. Within the HARP module  204 , tasks are further broken down into parallel/pipelined machine code operations (known as MOPs) and executed in hardware. 
     HARP module  204  comprises processing logic (HARP logic  302 ) and a relatively large memory (HARP memory  304 ) for hardware accelerating database operations of the node. In some embodiments, HARP module  204  is configured to handle various repetitive database tasks, such as table scanning, indexing, etc. In the C2 solution, HARP module  204  can receive high-level database query tasks (not just low-level read/write or primitive computation tasks as is typical for a general purpose processor) in the form of machine code database instructions. 
     HARP logic  302  is the hardware that executes machine code database instructions for the database tasks being handled by HARP module  204 . To adapt to application requirement changes, the HARP logic  302  is designed to have hardware re-configurability. Accordingly, in some embodiments, HARP logic  302  is implemented using field programmable gate arrays (FPGAs). However, any type of custom integrated circuit, such as application specific integrated circuits (ASICs), may be implemented as HARP logic  302 . 
     HARP memory  304  serves as the memory of HARP module  204 . In order to maximize the efficiency of the HARP logic  302 , the HARP memory  304  may be implemented using relatively large amounts of memory. For example, in some embodiments, the HARP memory  304  in a HARP module  204  may comprise 256 gigabytes or more of RAM or DRAM. Of course, even larger amounts of memory may be installed in HARP module  204 . HARP logic  302  and HARP memory  304  are further described with reference to  FIG. 6 . 
     In addition to the basic C2 node, a scale up C2 node topology may be used as an extension of the basic C2 node. As shown, host system  202  may now be coupled to a plurality or array of 1-N HARP modules  204 . In this type of node, a PCIe switch or other suitable switching fabric may couple these components together with storage infrastructure  112 . Of course, other internal arrangements for a scale up C2 node may be utilized in the present invention. 
     Going further, a scale out topology can be used for multiple C2 nodes. As shown, the scale out topology may comprise various combinations of either the basic or scale up C2 nodes. For example, as shown, the scale out topology may comprise Nodes  1 -M, which are coupled to storage infrastructure  112 . In  FIG. 2 , Node  1  is shown as a basic C2 node, while Node M is shown as a scale up node. A control node  206  is also shown and manages the operations of Nodes  1 -M. Control node  206  is shown as a separate node; however, those skilled in the art will recognize the role of control node  206  by any of Nodes  1 -M. Other variations in node hierarchy and management are within the scope of the present invention. Of course, this topology may also comprise a variety of combinations of nodes. 
       FIGS. 3A and 3B —Some Advantages 
       FIG. 3A  illustrates a prior art database system and  FIG. 3B  illustrates an exemplary implementation of the C2 solution for the present invention. In  FIG. 3A , a typical prior art database system is shown. An SQL query is submitted to a DBMS (e.g., MySQL), which runs on top of a typical operating system. The CPU attempts to then execute the SQL query. However, because the CPU is a general purpose CPU it executes this query based on software, which has several limitations. 
     In contrast, as shown in  FIG. 3B , the SQL query may submitted to a C2 system having a DBMS that comprises a top layer DBMS software (i.e., MySQL)  114  and C2 software  110 . C2 software  110  interfaces with the DBMS software  114  to orchestrate and optimize processing of the SQL query. 
     In particular, C2 software  110  may identify portions of the query, i.e., the fast path portion, which is better handled in hardware, such as HARP module  204 . Such portions may be those fragments of the query that are repetitive in nature, such as scanning, indexing, etc. In the prior art system, the DBMS is limited by its own programming, the operating system, and the general purpose CPU. The present invention avoids these bottlenecks by offloading fast path portions of a query to HARP module  204 . 
     As shown, HARP module  204  comprises HARP logic  302  and a HARP memory  304  to accelerate the processing of SQL queries. In order to maximize the use of HARP module  204 , the present invention may also utilize column store databases. Whereas the prior art system is hindered by the limitations of a standard row store database. These features also allow the present invention to maximize the performance of the I/O between the operating system and storage. 
     For ease of implementation, C2 software  110  may be implemented on well known operating systems. The operating system will continue to be used to perform basic tasks such as controlling and allocating memory, prioritizing system requests, controlling input and output devices, facilitating networking, and managing files and data in storage infrastructure  112 . In some embodiments, various operating systems, such as Linux, UNIX, and Microsoft Windows, may be implemented. 
       FIGS. 3A and 3B  are provided to illustrate some of the differences between the present invention and the prior art and advantages of the present invention. Those skilled in the art will also recognize that other advantages and benefits may be achieved by the embodiments of the present invention. For purposes of explanation, the present disclosure will now describe the C2 software, hardware, data structures, and some operations in further detail. 
       FIG. 4 —C2 Software Architecture 
     As noted, C2 software  110  orchestrates the processing of a query between MySQL software  114  and HARP module  204 . In some embodiments, C2 software  110  runs as an application on host system  202  and as a storage engine of MySQL software  114 .  FIG. 4  illustrates an architecture of the C2 software  110 . As shown, C2 software  110  comprises a query and plan manager  402 , a query reduction/rewrite module  404 , an optimizer  406 , a post optimizer module  408 , a query plan generator  410 , an execution engine  412 , a buffer manager  414 , a task manager  416 , a memory manager  418 , a storage manager  420 , an answer manager  422 , an update manager  424 , shared utilities  426 , and a HARP manager  428 . Each of these components will now be briefly described. 
     Query and plan manager  402  analyzes and represents the query received from the MySQL software  114 , annotates the query, and provides a representation of the query plan. Query reduction/rewrite module  404  breaks the query into query fragments and rewrites the query fragments into tasks. Rewrites may be needed for compressed domain rewrites and machine code database instruction operator rewrites. Optimizer  406  performs cost-based optimization to be done using cost model of resources available to C2 software  110 , i.e., HARP module  204 , resources of C2 software  110  itself using software operations, or MySQL software  114 . 
     These modules interact with each other to determine how to execute a query, such as a SQL query from MySQL software  114 . The data structures output by the query plan generator  410  will be the same data structure that the optimizer  406  and the rewrite module  404  will operate on. Once a parsed SQL query has been represented in this data structure (converted, for example, from MySQL), manager  402  rewrites the query such that each fragment of the query can be done entirely in MySQL software  114 , in C2 software  110 , or in HARP module  204 . Once the final query representation is available, the rewrite module  404  goes through and breaks the graph into query fragments. 
     Post optimizer module  408  is an optional component that rewrites after the optimizer  406  for coalescing improvements found by optimizer  406 . Query plan generator  410  generates an annotations-based, template-driven plan generation for the query tasks. Execution engine  412  executes the query fragments that are to be handled by software or supervises the query execution in HARP module  204  via HARP manager  428 . 
     Buffer manager  414  manages the buffers of data held in the memory of host  202  and for the software execution tasks handled by host  202 . Task manager  416  orchestrates the execution of all the tasks in HARP module  204  and software, i.e., in execution engine  412  or MySQL software  114 . Task manager  416  is further described below. 
     Memory manager  418  manages the virtual address and physical address space employed by C2 software  110  and HARP module  204  in HARP memory  304 . In some embodiments, memory manager  418  utilizes a 50-bit VA addressing (i.e., in excess of 1 petabyte). This allows C2 software  110  to globally address an entire database and optimize hardware execution of the query tasks. An example of the addressing scheme that may be employed is further described below. 
     Storage manager  420  is responsible for managing transfers of data from HARP memory  304  to/from storage infrastructure  112 . Answer manager  422  is responsible for compiling the results of the query fragments and providing the result to MySQL software  114  via the API  116 . 
     Update manager  424  is responsible for updating any data in the database stored in storage infrastructure  112 . Shared utilities  426  provide various utilities for the components of C2 software  110 . For example, these shared utilities may include a performance monitor, a metadata manager, an exception handler, a compression library, a logging and recovery manager, and a data loader. 
     HARP manager  428  controls execution of the tasks in HARP module  204  by setting up the machine code database instructions and handles all interrupts from any of the hardware in HARP module  204 . In some embodiments, HARP manager  428  employs a function library known as a Hardware Acceleration Function Library (HAFL) in order to make its function calls to HARP module  204 . One of the functions of the HAFL is task pipelining and IMC extension and overflow. 
       FIG. 5 —Protocol Stack of C2 Software 
     As shown, a SQL query is received in the RDBMS layer, i.e., MySQL software  114 . MySQL software  114  then passes the SQL query via API  116  to C2 software  110 . In C2 software  110 , the SQL query is processed and executed. At this layer, C2 software  110  also manages retrieving data for the SQL query, if necessary, from storage infrastructure  112  or from host system  202 . 
     In order to communicate with HARP module  204 , HARP manager  428  employs the HAFL layer in order to make its function calls to HARP module  204 . In order to allow for variances in hardware that may exist in HARP module  204 , the protocol stack may also comprise a hardware abstraction layer. Information is then passed from C2 software  110  to HARP module  204  in the form of machine code database instructions via an interconnect layer. As noted, this interconnect layer may be in accordance with the well known PCIe or HT standards. 
     Within HARP module  204 , the machine code database instructions are parsed and forwarded to HARP logic  302 . These instructions may relate to a variety of tasks and operations. For example, as shown, the protocol stack provides for systems management, task coordination, and direct memory access to HARP memory  304 . In HARP logic  302 , machine code database instructions can be executed by the various types of processing elements (PE). HARP logic  302  may interface with HARP memory  304 , i.e., direct memory access by utilizing the memory management layer. 
       FIG. 6 —HARP Logic 
       FIG. 6  illustrates an exemplary architecture of the HARP logic  302 . As shown, HARP logic  302  may comprise a set of processing cores  602 ,  604 ,  606 , and  608 , and switching fabric  610 . Processing core  602  (as well as cores  604 ,  606 , and  608 ) may comprise a set of processing elements (PEs)  620 . In the embodiment shown, processing cores  602 ,  604 ,  606 , and  608  each comprise two PEs; of course, each processing core may comprise any number of PEs. 
     In addition to its PEs, processing core  602  may comprise a task processor  612 , a memory manager  614 , a buffer cache  616 , and an interconnect  618 . One or more of these components may be duplicated or removed from the other processing cores  604 ,  606 , and  608 . For example, as shown, core  602  may be the sole core that includes task processor  612  and an interconnect  618 . This architecture may be employed because cores  602 ,  604 ,  606 , and  608  are connected via switching fabric  610  and may operate logically as a single processor or processor core. Of course, one skilled in the art will recognize that various redundancies may be employed in these processing cores as desired. 
     Task processor  612  is the hardware that supervises the operations of the processing cores  602 ,  604 ,  606 , and  608 . Task Processor  612  is a master scheduling and control processing element, disconnected from the direct dataflow of the execution process for a query. Task processor  612  maintains a running schedule of machine code database instructions which have completed, are in progress, or are yet to execute, and their accompanying dependencies. The task processor  612  may also dispatch machine code database instructions for execution and monitor their progress. Dependencies can be implicit, or explicit in terms of strong intra- or inter-processor release criteria. Machine code database instructions stalled for software-assist can be context-switched by the Task Processor  612 , which can begin or continue execution of other independent query tasks, to optimize utilization of execution resources in HARP logic  302 . 
     Memory manager  614  is the hardware that interfaces HARP memory  304 . For example, memory manager  614  may employ well known memory addressing techniques, such as translation look-aside buffers to map the global database virtual address space to a physical address in HARP memory  304  to access data stored in HARP memory  304 . 
     Buffer cache  616  serves as a small cache for a processing core. For example, temporary results or other meta-data may be held in buffer cache  616 . 
     PCIe interconnect  618  is the hardware that interfaces with host system  202 . As noted, interconnect  618  may be a PCIe or HT interconnect. 
     PEs  620  represent units of the hardware and circuitry of HARP logic  302 . As noted, PEs  620  utilize a novel dataflow architecture to accomplish the query processing requested of HARP logic  302 . In particular, PEs  620  implement execution of an assortment of machine code database instructions that are known as Macro Ops (MOPs) and Micro Ops (UOPs). MOPs and UOPs are programmed and executed by the PEs  620  to realize some distinct phase of data processing needed to complete a query. MOPs and UOPs are just example embodiments of machine code database instructions; other types of instruction sets for high level database operations of course may be used by the C2 solution. 
     PEs  620  pass logical intermediate MOP results among one another through a variable-length dataflow of dataflow tokens, carried across an interconnect data structure (which is a physical data structure and not a software data structure) termed an Inter-Macro Op Communication (IMC) path. Of note, the IMC paths and self routing fabric  610  allow HARP module  204  to utilize a minimal amount of reads/writes to HARP memory  304  by keeping most intermediate results flowing through the IMCs in a pipelined, parallel fashion. Data passed in an IMC may be temporarily stored in buffer caches  616  and interconnect fabric  610 ; however, data in IMCs can also be dispatched out through interconnect  618  to other PEs  620  on another HARP module. 
     In the dataflow concept, each execution step, as implemented by a MOP and its accompanying UOP program, can apply symmetrically and independently to a prescribed tuple of input data to produce some tuple of result. Given the independence and symmetry, any number of these tuples may then be combined into a list, matrix, or more sophisticated structure to be propagated and executed in pipelined fashion, for optimal execution system throughput. These lists of tuples, comprised fundamentally of dataflow tokens, are the intermediate and final results passed dynamically among the MOPs via IMC. 
     Although the dataflow travels over physical links of potentially fixed dimension, the logical structure of the contents can be multi-dimensional, produced and interpreted in one of two different ways: either with or without inherent, internal formatting information. Carrying explicit internal formatting information allows compression of otherwise extensive join relationships into nested sub list structures which can require less link bandwidth from fabric  610  and intermediate storage in buffer cache  616 , at the cost of the extra formatting delimiters, increased interpretation complexity and the restriction of fixing the interpretation globally among all consumers. Without inherent formatting, a logical dataflow may be interpreted by the consumer as any n-dimensional structure having an arbitrary but consistent number of columns of arbitrary but consistent length and width. It should be noted that the non-formatted form can be beneficial not only in its structural simplicity, but in the freedom with which consumer MOPs may interpret, or reinterpret, its contents depending upon the purpose of the execution step a consumer is implementing. 
     The dataflow used in realizing a given query execution can be described by a directed acyclic graph (DAG) with one intervening MOP at each point of flow convergence and bifurcation, one MOP at each starting and ending point, as well as any point necessary in between (i.e. single input &amp; output MOP). The DAG must have at least one starting and one ending point, although any larger number may be necessary to realize a query. MOPs which serve as the starting point are designed to begin the dataflow by consuming and processing large amounts of data from local storage. Ending point MOPs may terminate the dataflow back into local storage, or to a link which deposits the collected dataflow (result table list) into host CPU memory. An example of a DAG for a well known TPC-H query is shown in  FIG. 9 . 
     As mentioned above, MOP DAGs can physically and logically converge or bifurcate, programmatically. The physical convergence is accomplished with a multi-input MOP, which relate inputs in some logical fashion to produce an output comprised of all inputs (e.g. composition, merge, etc.). The physical bifurcation is accomplished by means of multicast technology in the IMC fabric, which dynamically copies an intermediate result list to multiple consumer MOPs. These mechanisms work together to allow realization of any desired DAG of MOP execution flow. 
     In the present invention, each MOP is configured to operate directly on the compressed data in the column-store database and realizes some fundamental step in query processing. MOPs are physically implemented and executed by PEs  620  which, depending on specific type, will realize a distinct subset of all MOP types. MOPs work systematically on individual tuples extracted either from local database storage in HARP memory  304  or the IMC dataflow, producing output tuples which may be interpreted by one or more MOP processes downstream. 
     UOPs are the low-level data manipulators which may be combined into a MOP-specific UOP program accompanying a MOP, to perform analysis and/or transformation of each tuple the MOP extracts. MOPs which utilize UOP programs are aware of the dependency, distributing selected portions of each tuple to the underlying UOP engine, extant within all PEs  620  supporting such MOPs. For each set of inputs from each tuple, the UOP program produces a set of outputs, which the MOP may use in various ways to realize its function. 
     For example, one manner a MOP may use UOP output is to evaluate each tuple of a list of tuples for a set of predicating conditions, where the MOP decides either to retain or to drop each tuple based on the UOP result. Another manner is for the UOP to perform an arithmetic transformation of each input tuple, where the MOP either appends the UOP result to form a larger logical tuple, or replaces some portion of the input tuple to form the output tuple. 
     Given a finite number of execution resources in PEs  620 , the full MOP dataflow DAG needed to execute a query may be partitioned into segments of connected MOPs called tasks. These tasks are then scheduled by task processor  612  for execution in a sequential fashion, as MOP execution resources become available in PEs  620 . Significant in this process is the propagation of the execution dataflow among these tasks, such that the entire query result is accurately and consistently computed, regardless of how each task is apportioned and regardless of the latency between scheduling each task. 
     One method that may be employed in HARP logic  302  is to treat each task atomically and independently, terminating the dataflow back into local storage in HARP memory  304  at the end of each task and restarting that dataflow at the beginning of the subsequent task by reloading it from HARP memory  304 . In some embodiments, a more efficient method may be employed to pipeline tasks at their finer, constituent MOP granularity, where at least one MOP of a new task may begin execution before all MOPs of the previous task have finished. This fine-grained method is referred to as task pipelining. 
     Keeping the dataflow alive over task boundaries is a key to realizing the extra efficiency of task pipelining. To accomplish this in the C2 solution, IMCs may include the ability to dynamically spill, or send their dataflow to an elastic buffer backed by HARP memory  304 , pending the awakening of a consumer MOP which will continue the dataflow. On scheduling the consumer MOP, IMCs are able to fill dynamically, reading from the elastic buffer in HARP memory  304  as necessary to continue execution, pulling out any slack that may have built up in the dataflow while waiting for the scheduling opportunity. Task pipelining with these mechanisms then may provide a more efficient use of execution resources, down to the MOP granularity, such that a query may be processed as quickly as possible. 
     Due to the sheer volume of data involved, high-latency, low-bandwidth, non-volatile storage in storage infrastructure  112  often holds most of the data being queried. Because execution rates can outstrip the bandwidth available to read from such storage, tasks requiring latent data can shorten execution time by starting and progressing their dataflow execution at the rate the data arrives, instead of waiting for an entire prefetch to complete before beginning execution. This shortcut is referred to as prefetch pipelining. The C2 solution may employ both on-demand prefetching and speculative prefetching. On-demand prefetching is where data is prefetched based on the progress of the dataflow. Speculative prefetching is where data is prefetched based on an algorithm or heuristic that estimates the data is likely to be requested as part of a dataflow. 
     In the present invention, prefetch pipelining can be accomplished by having one or more MOPs, when beginning a task&#39;s dataflow, accept data progressively as it is read from slow storage in storage infrastructure  112 . IMCs are capable of filling progressively as data arrives, as are all MOPs already designed to read from local storage in HARP memory  304 . Given that support, MOPs can satisfy the requirement of executing progressively at the rate of the inbound dataflow and accomplish efficient prefetch pipelining. 
     As shown, processing core  602  may comprise scanning/indexing PE  622  and XCAM PE  624  as its set of PEs  620 . As noted, PEs  620  are the physical entities responsible for executing MOPs, with their underlying UOPs, and for realizing other sophisticated control mechanisms. Various incarnations of processing elements are described herein, where each incarnation supports a distinct subset of the MOP and control space, providing different and distinct functionality from the perspective of query execution. Each of the different PE forms is now addressed where those which support MOPs employing UOP programs implicitly contain a UOP processing engine. 
     Scanning/indexing PE  622  implements MOPs which analyze database column groups stored in local memory, performing parallel field extraction and comparison, to generate row pointers (row ids or RIDs) referencing those rows whose value(s) satisfy the applied predicate. For some MOP forms, a data value list (which is an abstract term for a logical tuple list flowing through an IMC) containing a column of potentially sparse row pointers may be given as input, in which case the scan occurs over a sparse subset of the database. For other forms, scanning occurs sequentially over a selected range of rows. 
     The selection predicate is stipulated through a micro-op (UOP) program of finite length and complexity. For conjunctive predicates which span columns in different column groups, scanning may be done either iteratively or concurrently in dataflow progression through multiple MOPs to produce the final, fully selected row pointer list. 
     In as much as the Scanning/Indexing PE  622  optimizes scanning parallelism and is capable of constructing and interpreting compacted bitmap bundles of row pointers (which are a compressed representation of row pointers, sparse or dense, that can be packed into logical tuples flowing through an IMC), it operates most efficiently for highly selective predicates, amplifying the benefits thereof. Regardless, its MOP support locates specific database content. 
     Scanning/Indexing PE  622  also implements MOPs which project database column groups from HARP memory  304 , search and join index structures, and manipulate in-flight data flows, composing, merging, reducing, and modifying multi-dimensional lists of intermediate and final results. Depending on the MOP, input can be one or more value lists whose content may be interpreted in a one- or two-dimensional manner, where two-dimensional lists may have an arbitrary number of columns (which may have arbitrary logical width). 
     In the context of list reduction, a UOP program of finite length and complexity is stipulated as a predicate function, to qualify one or more components of the input value list elements, eliminating tuples that do not qualify. List composition involves the combining of related lists into a single output format which explicitly relates the input elements by list locality, while list merging involves intermingling input tuples of like size in an unrelated order. Modification of lists involves a UOP program, which can generate data-dependent computations, to replace component(s) of each input tuple. 
     The Scanning/Indexing PE  622  may also be used for joins with indexes, like a Group Index, which involves the association of each input tuple with potentially many related data components, in a one-to-many mapping, as given by referencing the index via a row pointer component contained in each input tuple. MOPs implemented by the Scanning/Indexing PE  622  may thus relate elements of a relational database by query-specific criteria, which can be useful for any query of moderate to advanced complexity. 
     XCAM PE  624  implements MOPs which perform associative operations, like accumulation and aggregation, sieving, sorting and associative joins. Input is in the form of a two-dimensional data value list which can be interpreted as containing at least two columns related by list locality: key and associated value. 
     Accumulation occurs over all data of like keys (associatively), applying one of several possible aggregation functions, like summation or an atomic compare and exchange of the current accumulator value with the input value component. A direct map mode exists which maps the keys directly into HARP memory  304 , employing a small cache (not shown) to minimize memory access penalties. A local mode of accumulation exists, as well, to realize zero memory access penalties by opportunistically employing the cache, at the risk of incomplete aggregation. For purposes of explanation, examples of associative accumulation MOPs are illustrated with reference to  FIGS. 14 and 15 . 
     Sieving involves the progressive capture of keys qualifying as most extreme, according to a programmable sieving function, generating a result list of the original input keys and values such that the last N tuples&#39; keys are the most extreme of all keys in the original input. Iterative application of Sieve can converge on a sorted output, over groups of some small granularity. 
     Sorting can also be accomplished through construction and traversal of either hashes or B-Trees. These hashes or B-Trees can be constructed to relate each input key to its associated value with a structure that is efficient to search and with which to join. 
     Within each of PEs  620  thus may be a UOP Processing Engine (not shown). Whereas PEs  620  execute MOPs in a dataflow fashion at the higher levels, embedded UOP Processing Engines in PEs  620  realize the execution of UOPs, which embed within their logical MOP parent to serve its low-level data manipulation and analysis needs. In some embodiments, the UOP processing engine is code-flow logic, where a UOP program is executed repetitively by a parent Processing Element at MOP-imposed boundaries, given MOP-extracted input data, to produce results interpreted by the parent MOP. 
     Considering the code-flow nature, each UOP engine has its own program storage, persistent register set and execution resources. It is capable, through appropriate UOP instructions, to accept data selected from the parent MOP and to simultaneously execute specified data manipulation or analysis thereon, in combination with some stored register state. In this manner, this tiny code-flow processor is able to fit seamlessly into the dataflow as a variable-latency element which, at the cost of increased latency, is capable of performing any of the most complex low-level data manipulation and analysis functions on the dataflow pouring through. The capability of the MOP to select and present only those data required for UOP processing, at a fine granularity, minimizes the latency imposed by the UOP code flow, maximizing overall dataflow throughput. 
       FIG. 7 —C2 Data Structures 
     The C2 solution utilizes various hardware-friendly data structures to assist in hardware accelerating database operations by HARP modules  204 . In general, hot columns (i.e., columns having active or frequent access) stay in the HARP memory  304  so that they can be accessed randomly fast. Warm Columns (i.e., columns having less active access) also stay in the HARP memory  304 ; but occasionally, they may be evicted to a disk in storage infrastructure  112 . Cold columns usually be held in storage infrastructure  112 , but may be partially brought into HARP memory  304 , e.g., for one time usage. In some embodiments, date columns in the Sorted-Compressed format will be held in the memory of host system  202  and accessed by the software running on host  202 . 
     In general, there is a single entry point for HARP module  204  to identify all the database columns. In particular, as shown in  FIG. 7 , a root table  702  points to all the available table descriptors  704 . The table descriptors  704  in turn point to their respective table columns  706 . Each table stores multiple columns in the VA memory space. Each of these tables will now be further described. 
     As noted, root table  702  identifies all the tables accessed by HARP module  204 . In some embodiments, each entry in the table takes 8 bytes. When needed, multiple Root Table blocks can be chained by a next pointer. The Descriptor Pointers in the root table  702  points to the individual table descriptors. The indices of the Descriptor Pointers also serve as the table ID. To simplify the hardware design, a CSR (Control Status Register) may be employed to store the Root Table information as long as the hardware accessible Table IDs and Descriptors&#39; information is retained in HARP module  204 . 
     Each database defined table has a table descriptor  704 . All the table descriptors  704  may reside in the HARP memory  304 . A table descriptor  704  may comprise different groups of data. A group may contain one or more columns. Within a group, the data is organized as rows. A group of data resides in a memory plane which is allocated to it. A data element in a particular plane has direct reference to its corresponding element in another plane. The relationship of the addresses among all the element pairs is the same arithmetical computation. The table descriptor is portable because the present invention utilizes a global virtual address space. In other words, when copying the table descriptor from one virtual memory location to another, all the information in the table is still valid. 
     In the C2 solution, the data structures of the database are architected to optimize database data processing in HARP hardware. All table columns/column groups, indices and meta-data are defined in a global database virtual address space (DBVA). A reserved DBVA section is allocated for table descriptors  704  as part of the meta-data. Table descriptors  704  include information about a table, such as the table name, number of rows, number of columns/column groups, column names, width(s) within a column group, etc. In addition to the information of data layout and access information in the VA space, the table descriptors  704  also have information about the compression types/algorithms used for each individual column. In the present invention, hardware can directly use this information to accomplish database queries and table element insertion, update, and deletion. 
       FIG. 8 —Table Column Layout 
       FIG. 8  is now provided to provide further detail on the structure of a table in column-store format as employed by the C2 solution of the present invention. As shown, each database table is broken into multiple columns or column groups having a fixed width. Variable width columns are also supported by extending the basic columns to a column heap structure with linked lists. In the C2 solution, a column group can have one or more columns packed together. Because of the simple arithmetic mapping or the single indirection in the companion column, the hardware and software of the present invention can easily access rows across the columns without any degradation in performance; thus, the C2 solution can provide the same functionality and benefits as known row store databases. Table and column descriptors may also be embedded in the MOPs and query tasks. 
     Of note, in the present invention, the columns or column groups possess an implicit row id (RID). A RID is considered implicit because it is not materialized as a part of a column or column group. Instead, each column and column group is designated a starting RID, which corresponds to an address in the global database virtual address space, which is then mapped to a physical address in HARP memory  304 . Since each column and column group is a fixed width, the RID can provide the basis for arithmetically calculating the memory address of any data in the column or column group. 
     In some embodiments, all columns are packed together in the single DBVA. In addition, a meta-data structure may be employed to facilitate certain column accesses. For example, as shown, a row pointer primary key index may comprise a sorted list of primary keys and their associated row id (RID) in a column or column group. Of course, a B-tree index may be used as an alternative to this type of index. 
     In the present invention, two active sets of database regions are maintained, i.e., a main database region and an augment region for newly added data. Query processing operates on both regions and is accelerated by the HARP module  204 . The augment region is utilized to hold new inserted items. Optionally, the augment region may be rolled into the main region. For example, as shown in  FIG. 8 , RIDs 1−n are the main region, while RIDs n+1, etc. comprise the augment region. 
     Deletion updates may be committed into the main region right away. To alleviate the drastic changes across all the columns in a table, the present invention may allocate a valid or invalid bit. A row deletion in a table, therefore, becomes a trivial task of setting the appropriate bit in every column group in the table. 
       FIG. 9 —Example of a SQL Query 
       FIG. 9  shows one of the 22 TPC-H queries, query # 3 , and how it would be executed using the machine code database instructions. TPC-H queries are published by the Transaction Processing Performance Council (TPC), which is a non-profit organization to define benchmarks and to disseminate objective, verifiable TPC performance data to the industry. TPC benchmarks are widely used today in evaluating the performance of computer systems. This particular query is a shipping priority query to find the potential revenue and shipping priority of the orders having the largest revenue among those that had not been shipped of a given date. The market segment and date are randomly generated from the prescribed range, and BUILDING and 03/15/1995 are the example here. This query is a complex multiple table join of three tables, CUSTOMER, ORDERS, and LINEITEM tables. 
     C2 Software  110  will decompose this query into 24 MOPs to send to HARP module  204 , along with their dependency information, which establishes the topology of the dataflow from MOP to MOP. All MOPs are started and hardware processing begins in pipelined fashion, with each MOP&#39;s results being fed to one or more downstream consumers over one or more dedicated logical IMC connections. 
     The responsibility of the first MOP, ScanCol( 0 ), is to reference HARP memory  304  to find all the customers in the CUSTOMER table who belong to the ‘BUILDING’ market segment, producing into IMC 0  all matching CUSTOMER references in the form of one RID per qualified row. RevIndex( 1 ) then traverses a reverse index residing in  304 , pre-built to relate customers to their one or more orders residing in the ORDERS table, outputting references to all orders made by the given customers. Because the CUSTOMER references are no longer necessary and to boost performance by reducing utilization of IMC transmission resources over IMC 2 , the ListProject( 2 ) removes the original customer references after the reverse index join, leaving only the ORDER references. The ScanRPL( 3 ) MOP then scans these orders&#39; O_ORDERDATE column, retaining ORDER references only to those orders whose order date occurs before the date ‘1995-03-15’. 
     Progressing onward through IMC 3 , the dataflow entering RevIndex( 4 ) consists of ORDER table references (RIDs) which have satisfied all criteria mentioned thus far: each order was placed by a customer in the ‘BUILDING’ market segment before the date Mar. 15, 1995. To finish evaluating the WHERE clause of the illustrated SQL query statement, these orders must be qualified in terms of certain properties of their related line items. 
     The purpose of the RevIndex( 4 ) MOP is then to associate each of the qualifying orders to its one or more constituent line items from the LINEITEM table, returning appropriate references thereto. At this point, the flow contains a two-column tuple list relating ORDER references (RIDs) to LINEITEM RIDs, multicasting identical copies of these tuples into IMC 4  and IMC 5 . ListProject( 5 ) extracts only the LINEITEM RID column from the dataflow in preparation for ProjRpl( 6 ), which extracts each line item&#39;s L_SHIPDATE column value, feeding these ship dates to IMC 7 . ListCompose( 7 ) consumes IMC 7  along with IMC 5 , executing a composition of the input lists to create a three-column tuple list where each tuple contains an ORDER RID, an associated LINEITEM RID and its ship date. ListSelect( 8 ) consumes the composed list from IMC  8  and selects only those tuples having ship date older than ‘1995-03-15’, thus completing the WHERE clause requirements. 
     Again, at the output of ListSelect( 8 ), the dataflow still logically appears as a three-column tuple list where each tuple relates an ORDER RID to one of its associated LINEITEM RIDs and that line item&#39;s ship date. It should be noted in this flow that multiple distinct LINEITEM RIDs may appear (in different tuples) with an identical ORDER RID, a definite possibility here since a single order may be comprised of an arbitrary number of line items in the target database and this query specifically requests only those line items satisfying the ship date criteria. The redundancy of ORDER RIDs in the list suggests an aggregation step will be needed to realize the SUM of the SQL select statement, but before that, some more data must be gathered and calculations done. 
     IMC 9  and IMC 10  both carry the output of ListSelect( 8 ), identically. ListProject( 9 ) extracts only the LINEITEM RID column from IMC 9 , passing that on to both ProjRpl( 12 ) and ProjRpl( 11 ), which fetch each referenced LINEITEM&#39;s L_EXTENDEDPRICE and L_DISCOUNT, respectively. Those procured extended price and discount data are then composed together by ListCompose( 13 ) to form a two-column tuple to be carried via IMC 17 . ListTupleArith( 14 ) implements the arithmetic process of computing (L_EXTENDEDPRICE*(1−L_DISCOUNT)) on a per-tuple basis before sending this arithmetic result to ListCompose( 15 ). In the meantime, ListProject( 10 ) extracts the ORDER RID column from the output of ListSelect( 8 ), such that ListCompose( 15 ) can make a two-column composition relating, within each tuple, an ORDER RID to its line item&#39;s arithmetic product. 
     The final hardware step to complete the query involves fully evaluating the SELECT clause, including its SUM aggregation function. The remainder of the MOP flow of  FIG. 9 , beginning with the output of ListCompose( 15 ), is dedicated to this process. 
     AssocAccumSum( 16 ) receives from IMC 19  with each of the two-column tuples relating an ORDER RID to one of its line item&#39;s (L_EXTENDEDPRICE*(1−L_DISCOUNT)) product, computing a summation of these values independently for each distinct ORDER RID. For example, a given ORDER RID may appear twice in IMC 19  (once in two different tuples), having two distinct LINEITEMs which satisfied all criteria thus far. Each of these LINEITEMs would have generated its own product in ListTupleArith( 14 ), such that the aggregation process of AssocAccumSum( 16 ) must sum them together. The result is a distinct sum of products over each distinct ORDER RID, realizing the SQL SUM aggregation function, here named REVENUE within the query. 
     Once the aggregation has completed for a given ORDER RID, ListProject( 17 ) extracts the ORDER RID itself, passing it to ProjRpl( 18 ), ProjRpl( 19 ) and ProjRpl( 20 ). These MOPs gather in parallel the referenced orders&#39; O_ORDERDATE, O_SHIPPRIORITY, and O_ORDERKEY, respectively, while ListCompose( 21 ) forms a two-column tuple consisting of O_SHIPPRIORITY and O_ORDERKEY. ListCompose( 22 ) meanwhile forms a two-column tuple comprised of O_ORDERKEY and REVENUE. The final MOP, ListCompose( 23 ), composes the two two-column tuple lists into a final four-column tuple list which satisfies the SQL query and its SELECT statement. 
     It should be noted in this example that the SQL query SELECT actually stipulates L_ORDERKEY. But an optimization may be applied here, knowing that O_ORDERKEY is functionally equivalent when used in this manner, thus avoiding the need to carry any LINEITEM RIDs beyond IMC 11  or IMC 12 . 
       FIG. 10 —Example of a Dataflow through the HARP 
     In  FIG. 9  we have described how an SQL statement gets mapped into a logical MOP DAG (directed acyclic graph) which gets executed in a dataflow fashion with IMC chaining between MOPs.  FIG. 10  illustrates an exemplary dataflow through PEs  620  in HARP logic  302  for the same TPC-H SQL # 3  query shown in  FIG. 9 . As noted, C2 Software  110  will decompose this query task into 10 PE stages to send to HARP module  204 , along with their MOP and UOP instructions and dependency information. 
     Stage 1 is performed by Scanning PE  1002  is to find all the customers in CUSTOMER table that is in BUILDING market segment and passes the results (C_RIDs of matching customer records) in an IMC to Indexing PE  1004 . 
     Stage 2 is a join operation of C_CUSTKEY=O_CUSTKEY performed by Indexing PE  1004  using a reverse index method. Each C_RID of Stage 1&#39;s matching customer records corresponds to an O_RID hitlist of ORDER table records, given a customer may place multiple orders. The results (O_RIDs) are passed in an IMC to Scanning PE  1006 . 
     Stage 3 is performed by Scanning PE  1006  to read the O_ORDERDATE field of all the matching orders (O_RIDs) that Stage 2 outputs, compare for &lt;‘1995-03-15’, and passes the results (O_RIDs) in an IMC to Indexing PE  1008 . 
     Stage 4 is a join operation of O_ORDERKEY=L_ORDERKEY performed by Indexing PE  1008  using a reverse index method. Each O_RID of Stage 3&#39;s matching order records corresponds to an L_RID hitlist of LINEITEM table records, given an order may have multiple line items. The results (L_RIDs) are passed in an IMC to Scanning PE  1010 . 
     Stage 5 is performed by Scanning PE  1010  to read the L_SHIPDATE field of all matching line items (L_RIDs) that Stage 4 outputs, compare for &gt;‘1995-03-15’, and passes the results (L_RIDs) in 3 IMCs to Indexing PE  1012 ,  1014 , and  1016 . 
     Stage 6 is a column extraction/projection operation done by Indexing PE  1012 ,  1014 , and  1016  to get L_ORDERKEY, L_EXTENDEDPRICE, and L_DISCOUNT column. 
     Stage 7 is a list merge operation of 2 columns (L_EXTENDEDPRICE and L_DISCOUNT) done by Indexing PE  1018 . 
     Stage 8 is an aggregation operation of REVENUE of each L_ORDERKEY group, done by XCAM PE  1020  based on outputs of Indexing PE  1012  and  1018 . As the SQL statement defines, REVENUE is calculated as the sum of (L_EXTENDEDPRICE*(1−L_DISCOUNT)). Note that even though the GROUP BY defines the group key as concatenation of L_ORDERKEY, O_ORDERDATE, O_SHIPPRIORITY, the group key is simplified to L_ORDERKEY since it is already a unique identifier. The output of XCAM PE  1020  is a pair list of group key (L_ORDERKEY) with its REVENUE. 
     Stage 9, done by Indexing PE  1022  and  1024 , is a column extraction of O_ORDERDATE based on L_ORDERKEY output of XCAM PE  1020 . 
     Stage 10, done by XCAM PE  1026 , is a sieve (ORDER BY) operation of REVENUE, O_ORDERDATE to output top N groups with largest REVENUEs. These outputs are placed at a result buffer area in HARP memory  304 , ready to be retrieved by DBMS software  114 . 
     Exemplary Global Database Virtual Addressing Scheme 
     As noted, the C2 solution of the present invention can employ an arbitrarily large virtual address space (DBVA) to globally address an entire database. This addressing scheme is utilized to assist hardware acceleration, because it allows HARP module  204  and C2 software  110  to arithmetically calculate the location of any data in a database.  FIG. 11  illustrates an exemplary logic flow of the addressing schemes employed and  FIG. 12  illustrates a structure of the global database virtual address scheme of the present invention. 
     Referring now to  FIG. 11 , when a query is received from MySQL software  114 , it is eventually submitted to query execution engine  412  for processing. At this level, execution engine  412  operates on the database using what are known as logical addresses. A logical address utilizes the naming convention of the SQL query. For example, a logical address may consist of a database name, a table name, a column group name, and a column name which is then converted to a DBVA. Since it is a virtual address, the DBVA may be arbitrarily large, e.g., in excess of a petabyte. 
     The DBVA may then be converted to physical addresses of the data in storage  112  or in the memory of host system  202 . For example, as shown, a storage manager  420  may have a mapping that converts a DBVA to a storage physical address (SPA). This allows for retrieval of data from storage  112 . In addition, buffer manager  414  may convert the DBVA to a physical address in the memory of host system  202 , for example, using a standard memory manager in the operating system running on host system  202 . Such conversions are well known to those skilled in the art. 
     However, of note, the present invention may employ an extensible addressing scheme for one or more HARP modules  204 . As noted, HARP modules  204  may comprise a relatively large memory, i.e., in excess of 256 gigabytes or more. HARP modules  204  may also employ smaller memories, such as, about 32 gigabytes. In addition, the C2 solution may comprise nodes that have multiple HARP modules  204  and may also support multiple nodes. Accordingly, the present invention may comprise a novel, layered virtual addressing scheme. 
     In one embodiment, each HARP module  204  translates the DBVA to a physical address (HPA) of HARP memory  304 . For example, HARP module  204  may utilize a translation-lookaside buffer (TLB) for this translation. 
     Alternatively, especially in a multi-HARP module environment or federated system, each HARP module  204  may employ a secondary virtual address space (called an HVA) that underlies the DBVA. Referring now to  FIG. 12 , in this embodiment, memory manager  418  may thus include a DBVA-HVA service that maps a DBVA address into yet another virtual address in the HVA. Memory manager  418  may then translate the HVA into a HPA using, for example, a TLB for the respective HARP memory  304 . 
     This feature allows the present invention to continue utilizing a single global virtual address space for a database even where system  100  includes multiple HARP modules  204  or multiple nodes of HARP modules. Accordingly, systems of the C2 solution can continue to employ hardware-friendly addressing for hardware acceleration of the database operations regardless of the number of HARP modules  204  or the size of the database. 
       FIGS. 14-15 —Associative Accumulation MOPs 
     Another associative operation implemented by XCAM PE  624  can involve the writing of each input value, mapped by its associated key value, to a corresponding location in HARP memory  304  (vis-à-vis the direct map mode). As the input keys may vary arbitrarily in order and value, this process effects a surgical scattering of writes to desired portions of HARP memory  304  in a manner particularly useful for making anything from large, sweeping to small, incremental updates of database column contents. At least two approaches may be available, each with some advantages: full and selective replace. 
     In  FIG. 14 , a full replace function is shown. The full replace function may be considered a coalescing form. In general, this MOP may first collect writes to adjacent memory locations over a window of address space, before dispatching them to HARP memory  304 . While avoiding reads of original memory contents, coalescing takes advantage of the potential for spatial locality in the input key stream, thereby minimizing the write and nullifying the read bandwidth required, to provide a high performance solution for executing updates of memory  304 . Since reads are avoided and since the granularity of the update size can be much less than that of the coalescing window, any key location not addressed within the window may have its associated memory contents cleared to a constant value or assigned otherwise undefined data. A small cache may be utilized to perform the coalescing. 
     In  FIG. 15 , a selective replace function is shown, and may also be considered a non-coalescing form. This function may be more precise and selective in updating HARP memory  304 , by preserving data in adjacent locations at the expense of higher memory read and write bandwidth requirements. This approach can be especially useful for small update granularity (e.g. 1-bit) where spatial locality cannot be guaranteed among the updates requested in the input stream and preservation of surrounding data is necessary. Again, a small cache may be used to mitigate unnecessary memory accesses, in an opportunistic manner. 
     Task Management 
     As noted above, the task management and run-time scheduling that may be performed by the task manager  416  will now be further described. In review, in the C2 solution, a query is broken down into one or more Query Fragments (QFs). A QF is then executed either by C2 software  110 , by MySQL software  114 , or ideally, in hardware by HARP module  204 . 
     Going further, a QF may be considered to comprise one or more task dependencies described in a directed acyclic graph (DAG). A large task may be split into smaller tasks due to resource constraints (e.g., maximum prefetch size, number of MOPs/PEs available, etc.). In some embodiments, the C2 solution may employ four basic types of tasks: a MOP-type task; a SOP (software operation) type task; a prefetch-type task; and a SYNC-type task. Each of these task types will now be further described. 
     A MOP-type task relates to tasks that are executed in the hardware of HARP logic  302 . A MOP-type task may comprise one MOP or many MOPs in a DAG that is executed by HARP logic  302 . 
     A SOP-type task relates to tasks that are executed by execution engine  412  in the software of C2 software  110 . A SOP-type may comprise one SOP or many SOPs in a DAG that is executed by the CPU of host system  202  based on C2 software  110 . 
     A prefetch-type task relates to retrieving data from storage  112  to HARP module  204 , from storage  112  to host system  202 , or from HARP module  204  to host system  202 . A SYNC-type relates to a virtual address (VA) page&#39;s inserts/deletes/updates to synchronize data held in HARP memory  304 . 
     In general, an entire task set of a QF is submitted together to task manager  416  for scheduling. Task manager  416  may schedule a task out-of-order for optimal scheduling, to one of the execution units, i.e., HARP modules  1  . . . n, QEE  412 , SM  420 , or BM  414 . Task manager  416  scheduling can be primarily driven by a task&#39;s workset pages, DAG within its QF, estimated execution time, and dispatched queries. 
     In some embodiments, for MOP-type tasks, HARP manager  428  may do further scheduling optimization based on specific resources (such as, available PEs  620 , IMC ports, TLB entries, etc.) of HARP module  204 . For PREFETCH-type tasks, SM  420  and BM  414  may also do further scheduling optimization based on disk I/O and host system  202  cache resources, respectively. 
     Task manager  416  also supports multi-versioning database snapshots for fast continuous updates. Accordingly, task manager  416  may employ one SYNC task per page, with the entire SYNC taskset entered together. For each older task affected by any SYNC, an UNDO/REDO task wrapper will be created by task manager  416  with the help of QEE  412 . 
     Task manager  416  may utilize one logical central scheduling window consisting of four queues: a waiting queue, a paging queue, ready queue, and a running queue.  FIG. 13  illustrates an example of this window. 
     For purposes of explanation, the life cycle of a MOP-type task will be explained as an example of how task manager  416  performs its run-time scheduling. Then, the algorithm used by task manager  416  to schedule a task will be explained. 
     A MOP-type task is created by query plan generator  410  during MOP plan generation based on the best plan generated by optimizer  406 . Query plan generator  410  may split a QF/task into multiple smaller tasks, in which case the task dependency is described in a DAG. 
     Query plan generator  410  passes on the complete task set to QEE  412 , which then submits it to task manager  416 . For each new task, task manager  416  will translate the task&#39;s logical address ranges (schemaID, tableID, partitionID, columnID, RID range) into global database virtual address (DBVA) ranges. Then, task manager  416  will ask MM  418  to map with intent lock all the DBVA ranges. MM  418  will eventually reply with a list of mapped VA pages for the task&#39;s workset, available, and missing page list. Task manager  416  will then place the task in the waiting task queue to compete for scheduling arbitration. 
     Based on the task set&#39;s scheduling cost comparison (described later), eventually this task wins a scheduling slot, at which time, task manager  416  requests a real lock from MM  418  for all the task&#39;s workset pages. Of note, winning a scheduling slot does not mean that the task is dispatched for execution yet. 
     If all the task&#39;s workset pages are granted the lock by MM  418  and the data are physically present in HARP memory  304 , then task manager  416  will move the task to its ready queue, otherwise task manager  416  will move the task to the paging queue until data can be paged into HARP memory  304 . If the task is in the paging queue, task manager  416  may wait for subsequent page updates from MM  418  for lock grant and a notification that data is present. 
     When the task is in the ready queue and reaches the bottom, task manager  416  will check if it can dispatch the task to HARP manager  428  based on its task queue status. If HARP manager  428  is ready to dispatch the task to HARP module  204 , the task manager  416  moves the task to its running queue and awaits a done signal from HARP manager  428 . HARP manager  428  will eventually schedule the task, map the task to one of HARP modules  204 , loading missing TLB entries if necessary, and submit the task&#39;s MOP chain to HARP module  204  via, for example, the PCIe interface. 
     When HARP module  204  completes the entire task execution, it may send a PCIe task done interrupt to HARP manager  428 , which subsequently forwards this status to task manager  416 . Based on the taskID, HARP manager  428  updates the task status in the running queue. Task manager  416  will then call MM  418  to unlock all the workset pages. 
     As part of locking/unlocking workset pages, task manager  416  may be configured to work with memory manager  418  to detect deadlocks and/or resolve deadlocks of workset pages. Task manager  416  may also be configured to proactively avoid deadlocks when initially locking or requesting intents to lock various workset pages. 
     When all tasks of a QF are done, task manager  416  will notify QEE  412 . Answer manager  422  will further propagate the QF completion all the way to MySQL software  114  via API  116 . 
     Task Manager Run-time Scheduling 
     In general, task manager  416  will attempt to select as many tasks in the waiting queue in each of its scheduling windows. When a task has won a scheduling slot, task manager  416  will then move the state of that task from the waiting queue to the paging/ready queues. Selection is made based on the following priority order: 
     1. SYNC tasks are scheduled by task manager  416  without delay; 
     2. RED-mode tasks are scheduled according to the oldest first, then the next oldest one, and so forth; 
     3. YELLOW-mode root tasks; 
     4. GREEN-mode non-root tasks; and 
     5. GREEN-mode root tasks. 
     Root (or leader) tasks have no DAG dependency within a QF boundary, but a DAG has only one root task (i.e., critical path&#39;s leader task). A root task, leader tasks and trailing tasks of same DAG collectively form a QF&#39;s task set. Each of these priorities will now be further described. 
     SYNC-Type Tasks 
     When a SYNC task is submitted to task manager  416 , it will tag older tasks (i.e. all tasks currently in waiting, paging, or ready queues) as pre-sync and subsequent younger tasks as post-sync. Any pre-sync task having a page that overlaps a page with a SYNC task will have its workset pages unlocked. If this task is in the paging or ready queues, it is demoted back to the waiting queue. 
     For SOP-type sync tasks in the SYNC task, task manager  416  will still immediately schedule this task with highest priority. Task manager  416  will thus instruct MM  418  to lock the pages written by this sync task. With sync-ed pages locked, any post-sync or pre-sync tasks using any of these pages will be blocked until the corresponding SYNC task completes. Remaining tasks that operate on unchanged pages can continue to be scheduled as usual. 
     Sometimes a SYNC task is not immediately granted a lock by MM  418 , for example, if there are running task(s). In these instances, task manager  416  will hold this SYNC task until these running task(s) complete. However, other SYNC task(s) of the same task set may be granted the lock and executed. 
     For each pre-sync task having overlapping page(s) with the SYNC task set, task manager  416  will wrap around this pre-sync task an undo and redo SOP-type task. The undo and redo task pair may be created right away by calling a routine in QEE  412  to create the two wrapper tasks. Undo and redo are done based on the snapshot version of the database and what blocks within each synchronized page are modified. The undo-redo task pair may require getting write locks from MM  418  beforehand and then calling an unlock when the redo task is done. If a write lock is not granted immediately by MM  418 , then task manager  416  may hold the task in the waiting queue. 
     In the case of multiple SYNC tasks from different groups, task manager  416  may re-create an existing undo-redo task pair. There may also be more pages affected by an undo-redo task pair based on the pre-sync task&#39;s snapshot version of the database. 
     For a post-sync task, task manager  416  generally schedules it after the SYNC task, but it may be before or after a pre-sync task. If it is before a pre-sync task, then given the upgraded snapshot version, this task may be issued without blocking. If the post-sync task is scheduled after a pre-sync task having an overlapping page, then task manager  416  will block the post-sync task until the pre-sync task (with undo/redo wrapper) is completed. 
     RED-Mode Tasks 
     First, task manager  416  may sort waiting tasks oldest first based on their wait time numbers. If the highest wait time exceeds a threshold, then task manager  416  will designate that task as a RED-mode task and perform single step scheduling of these tasks. 
     For waiting tasks in a scheduling window, task manager  416  will first try to find all root tasks. As noted, root (or leader) tasks have no DAG dependency within a QF boundary, but a DAG has only one root task (i.e., critical path&#39;s leader task). A root task, leader tasks and trailing tasks of same DAG collectively form the QF&#39;s task set. 
     YELLOW-Mode Root Tasks 
     If a root task&#39;s wait time exceeds a threshold, such as a weighted percentage of critical path execution time for a task set, then task manager  416  will put this root task into YELLOW mode. Task manager  416  will prioritize scheduling of the YELLOW-mode root task. Task manager  416  will schedule as many root tasks in YELLOW mode as possible. 
     GREEN-Mode Non-Root Tasks 
     Task manager  416  will attempt to find trailing/leader tasks that are dependent on already-scheduled root task(s) and schedule them if possible. For remaining GREEN-mode root tasks in the scheduling window, task manager  416  may: determine the size of available pages already in HARP memory  304  for MOPs, or memory in host system  202  for SOPs; determine the size of missing pages to be prefetched or allocated if not done yet (e.g., for new temporary tables/area); estimate a duration for pages that have to be locked, including the prefetch time; and calculate a scheduling cost. 
     In some embodiments, task manager  416  may calculate scheduling cost according to the formula
 
sched_cost= f (workset_pagesize, available_pagesize, missing_pagesize, lock_duration)
 
=lock_duration*( c 1*workset_pagesize+ c 2*missing_pagesize− c 3*available_pagesize), where  c 1,  c 2, and  c 3 are programmable weight coefficients.
 
     Since missing pages may involve prefetching from disk I/O, the c1 coefficient can also include cost of I/O bandwidth. 
     Task manager  416  will compare costs of task sets, and select the task set with the least cost. Task manager  416  will then ask MM  418  to lock the workset pages of the selected task set. 
     In some embodiments, task manager  416  may fetch or prefetch various columns based on a ranking. Task manager  416  may rank columns, for example, based on one or more characteristics of the column and usage of the columns. In particular, task manager  416  may rank columns that contain index information, floating point numerical data, keys, data above a size threshold, date information, etc. Task manager  416  may also rank columns based on the number of predetermined characteristics present or on a weighted sum of predetermined characteristics. Task manager  416  may also update rankings of the columns over time based on their usage. 
     Task manager  416  may then selectively load columns into a HARP based on their ranking or speculatively prefetch columns based on their ranking. When loading or prefetching, task manager  416  may account for the capacity or unused input/output capacity of the relevant HARP. In addition, task manager  416  may speculatively prefetch columns based on free space available in the HARP&#39;s memory  304 . Conversely, task manager  416  may selectively discard columns from a HARP based on their ranking. 
     Task manager  416  may also employ various exceptions to its basic algorithms, for example, in the event of a task failure or other event in system  100  that requires attention. For example, task manager  416  may perform various tasks to recover from an error or disruption, such as identifying a cause of the disruption and resolving the disruption based on its cause. Various errors or disruptions may include a buffer overflow, and the like. As part of handling the disruption, task manager  416  may extend the virtual address and allocating additional physical address space in the memory  304  of the HARP to accommodate the overflow in the buffer. Task manager  416  may identify other errors, such as, a miss by a translation buffer, a task that exceeds a processing element capability, an arithmetic overflow, an uncorrectable error in a buffer, an uncorrectable physical link error in the HARP, a conditional task included in the dataflow execution of tasks, etc., as tasks that need to be resolved or corrected. 
     Task manager  416  may take various actions to resolve these disruptions or errors, such as, re-executing the disrupted task using a SOP, and/or requesting a new plan for continuing the dataflow execution of the query, for example, based on a conditional task. 
     Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.