Patent Publication Number: US-2022216193-A1

Title: Semiconductor package including processor chip and memory chip

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 16/051,926 filed Aug. 1, 2018, which is incorporated by reference herein in its entirety. 
     Korean Patent Application No. 10-2017-0150710, filed on Nov. 13, 2017, in the Korean Intellectual Property Office, and entitled: “Semiconductor Package,” is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     1. Field 
     Embodiments relate to semiconductor packages, and more particularly, to a system in package (SiP) including a processor chip and a memory chip. 
     2. Description of the Related Art 
     Recently, the market demand for mobile or portable devices has increased rapidly, and accordingly, miniaturization and weight reductions of electronic components mounted on such devices have been continuously required. For this purpose, many researches have been conducted to develop a semiconductor package that has a small volume and is able to process high-capacity data by highly integrating and incorporating many semiconductor chips into the semiconductor package. Thus, a system in package (SiP) has been developed to efficiently arrange semiconductor chips, e.g., a processor chip and a memory chip, within a limited space of a semiconductor package. 
     SUMMARY 
     Embodiments are directed a semiconductor package, including a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate, the second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads in an upper surface portion of the signal transmission device and connected to the plurality of first bonding wires, penetrating electrodes in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device. The lower pads are connected to the penetrating electrodes, and connected to the package substrate via bonding balls. 
     Embodiments are directed to a semiconductor package, including a package substrate including a plurality of internal traces, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate and stacked with adhesion members therebetween, the second region of the package substrate being spaced apart from the first region of the package substrate, the second region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The processor chip and the signal transmission device transmit a signal via the plurality of internal traces, and the plurality of memory chips and the signal transmission device transmits a signal via the plurality of first bonding wires. 
     Embodiments are directed to a semiconductor package, including a package substrate, a processor chip mounted on the package substrate, a plurality of memory chips mounted on the package substrate and to exchange data with each other, a signal transmission device mounted on the package substrate, a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device, and a molding member covering lateral surfaces of the processor chip, the plurality of memory chips, and the signal transmission device. The processor chip, the plurality of memory chips, and the signal transmission device are spaced apart from each other. The signal transmission device includes upper pads in an upper surface portion of the signal transmission device, the upper pads connected to the plurality of first bonding wires, penetrating electrodes in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device. The lower pads are connected to the penetrating electrodes and connected to the package substrate via bonding balls. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which: 
         FIGS. 1A-1D  illustrate a semiconductor package according to an embodiment; 
         FIGS. 2A and 2B  illustrate a semiconductor package according to an embodiment; 
         FIGS. 3A and 3B  illustrate a semiconductor package according to an embodiment; 
         FIGS. 4A and 4B  illustrate a semiconductor package according to an embodiment; 
         FIGS. 5A and 5B  illustrate a semiconductor package according to an embodiment; 
         FIGS. 6A and 6B  illustrate a semiconductor package according to an embodiment; and 
         FIG. 7  is a block diagram illustrating a structure of a semiconductor package according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Unless mentioned otherwise, a plane area refers to an area of a surface parallel to a main surface of a package substrate, and a thickness refers to a thickness in a vertical direction with respect to the main surface of the package substrate. In addition, unless mentioned otherwise, a vertical direction or a horizontal direction refers to a vertical direction or a horizontal direction with respect to the main surface of the package substrate. Moreover, unless mentioned otherwise, an upper surface of a stack of components on the package substrate refers to a surface opposite to the main surface of the package substrate, and a lower surface of the stack of the components on the package substrate refers to a surface facing the main surface of the package substrate. 
     Embodiments will now be described more fully hereafter with reference to the accompanying drawings. 
       FIGS. 1A-1D  illustrate a semiconductor package  10  according to an embodiment. 
       FIG. 1A  illustrates a vertical sectional view of the semiconductor package  10 , and  FIG. 1B  illustrates a plan view of the semiconductor package  10 . In  FIG. 1B , a molding member  510  is not shown for clearly showing an internal structure of the semiconductor package  20 . 
     Referring to  FIGS. 1A and 1B , the semiconductor package  10  may include a package substrate  100 , an external connection terminal  120 , a processor chip  200 , a plurality of memory chips  210 A,  220 A,  230 A, and  240 A, a signal transmission device  300 A, a plurality of first bonding wires  410 , and the molding member  510 . The package substrate  100  may have a lower surface and an upper surface including a first region  101 , a second region  102 , and a third region  103  between the first and second regions  101  and  102 . The external connection terminal  120  may be formed on the lower surface of the package substrate  100 . The processor chip  200  may be mounted on the first region  101  of the upper surface of the package substrate  100 . The plurality of memory chips  210 A,  220 A,  230 A, and  240 A may be mounted on the second region  102  of the upper surface of the package substrate  100 , e.g., in a stack. The signal transmission device  300 A may be mounted on the third region  103  of the upper surface of the package substrate  100 , e.g., by bonding balls  320 , and may be dispositioned between the processor chip  200  and at least one of the plurality of memory chips  210 A,  220 A,  203 A, and  240 A in a horizontal direction. The plurality of first bonding wires  410  may connect the plurality of memory chips  210 A,  220 A,  230 A, and  240 A to the signal transmission device  300 A, and may have difference lengths or the same length. 
     The package substrate  100  may have upper substrate pads  111  on the upper surface thereof, and may have lower substrate pads  112  on the lower surface thereof. The package substrate  100  may also have an internal trace  110  and a substrate connection via (not shown) that electrically connects the upper substrate pads  111  with the lower substrate pads  112 . The package substrate  100  may be, e.g., a printed circuit board (PCB). 
     The package substrate  100  may be formed of at least one material of phenol resin, epoxy resin, and polyimide. For example, the package substrate  100  may include at least one material of flame retardant 4 (FR4), tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, bismaleimide triazine (BT), thermount, cyanate ester, polyimide, and liquid crystal polymer. The upper substrate pads  111 , the lower substrate pads  112 , the internal trace  110 , and the substrate connection via may be formed at least one of, for example, copper (Cu), nickel (Ni), aluminum (Al), or beryllium copper (BeCu). 
     The processor chip  200  may be implemented using, e.g., a microprocessor, a graphics processor, a signal processor, a network processor, a chip set, an audio codec, a video codec, an application processor, or a System on Chip (SoC). The microprocessor may include, for example, a single core or multiple cores. 
     The plurality of memory chips  210 A,  220 A,  230 A, and  240 A may include, e.g., a high bandwidth memory. According to some embodiments, the plurality of memory chips  210 A,  220 A,  230 A, and  240 A may include, e.g., a volatile and/or nonvolatile memory. The volatile memory may include, for example, a dynamic random access memory (DRAM), a static RAM (SRAM), a thyristor RAM (TRAM), a zero capacitor RAM (ZRAM), or a twin transistor RAM (TTRAM), and memory circuits that are able to temporally store data while powered on. The nonvolatile memory may include, for example, a flash memory, a magnetic RAM (MRAM), a spin-transfer torque MRAM (STT-MRAM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM, polymer RAM, a nano floating gate memory, a holographic memory, a molecular electronics memory, or an insulator resistance change memory, and memory circuits that are able to maintain data while powered on and off. 
     Respective one of the plurality of memory chips  210 A,  220 A,  230 A, and  240 A may include a semiconductor substrate having an active surface (e.g., an upper surface) and an inactive surface (e.g., a lower surface) facing each other, memory devices on the active surfaces, and a plurality of upper memory bonding pads  211 ,  221 ,  231 , and  241  on the active surfaces. The plurality of upper memory bonding pads  211 ,  221 ,  231 , and  241  may be connected to first bonding wires  410 , respectively. 
     In some embodiments, the plurality of memory chips  210 A,  220 A,  230 A, and  240 A may be integrated into a single package in a System in Package (SiP), and the number of the plurality of memory chips  210 A,  220 A,  230 A, and  240 A may vary according to a purpose of the semiconductor package  10 . Embodiments are not restricted by the number of the plurality of memory chips  210 A,  220 A,  230 A, and  240 A.For example, more or less memory chips than the plurality of memory chips  210 A,  220 A,  230 A, and  240 A may be stacked, e.g., in a vertical direction. 
     The plurality of memory chips  210 A,  220 A,  230 A, and  240 A may be stacked on the package substrate  100 , and may adhere to each other via, e.g., a plurality of adhesion members  213 ,  223 ,  233 , and  243 . 
     The plurality of adhesion members  213 ,  223 ,  233 , and  243  may be, e.g., die attach films (DAFs). The DAFs may include, e.g., inorganic adhesives and polymer adhesives. The polymer adhesives may include a thermosetting resin and a thermoplastic resin. The thermosetting resin may have a three-dimensional (3D) cross-link structure after being heated and molded, and may not soften after being heated again. In contrast, the thermoplastic resin may have plasticity via heating, and may have a linear polymer structure. In some embodiments, the plurality of adhesion members  213 ,  223 ,  233 , and  243  may be hybrid polymer adhesives obtained by mixing the thermosetting resin and the thermoplastic resin. 
     The signal transmission device  300 A may include a base substrate  301 , and a conductive structure formed on the base substrate  301 . The base substrate  301  may be a silicon wafer including silicon (Si) (e.g., polycrystal Si, or amorphous Si). The conductive structure of the signal transmission device  300 A may include upper pads  311  in an upper surface portion of the base substrate  301 , penetrating electrodes  310  in a main body portion of the base substrate  301 , and lower pads  312  of  FIG. 1C  in a lower surface portion of the base substrate  301 . The upper pads  311  may be connected to the first bonding wires  410 . The penetrating electrodes  310  may be connected to the upper pads  311  and may penetrate the main body portion of the base substrate  301 , e.g., in the vertical direction. The lower pads  312  of  FIG. 1C  may be connected to the penetrating electrodes  310 , and may be connected to the package substrate  100  via the bonding balls  320 . 
     The signal transmission device  300 A may be mounted on the third region  103  of the upper surface of the package substrate  100  between the first region  101  and the second region  102  of the upper surface of the package substrate  100 . In other words, the signal transmission device  300 A may be arranged between the processor chip  200  in the first region  101  and the plurality of memory chips  210 A,  220 A,  230 A, and  240 A in the second region  102 , and may be spaced apart from the processor chip  200  and the plurality of memory chips  210 A,  220 A,  230 A, and  240 A, i.e., in a horizontal direction. 
     According to some embodiments, the signal transmission device  300 A may further include a circuit region  330  and a buffer circuit in the circuit region  330 . The buffer circuit may control a capacitance loading of the plurality of memory chips  210 A,  220 A,  230 A, and  240 A. According to other embodiments, a semiconductor integrated circuit including at least one of a transistor, a diode, a capacitor, and a resistor may be formed in the circuit region  330 . The circuit region  330  may overlap with the upper pads  311 . In some cases, the circuit region  330  may be omitted. 
     In a plan view, a plane area of the signal transmission device  300 A may be smaller than that of the processor chip  200  and that of each of the plurality of memory chips  210 A,  220 A,  230 A, and  240 A. 
     The plurality of first bonding wires  410  may electrically connect the plurality of memory chips  210 A,  220 A,  230 A, and  240 A to the signal transmission device  300 A. The plurality of first bonding wires  410  may connect the plurality of upper memory bonding pads  211 ,  221 ,  231 , and  241  of the plurality of memory chips  210 A,  220 A,  230 A, and  240 A to the upper pads  311  of the signal transmission device  300 A, respectively. For convenience of explanation, the accompanying drawings illustrate some of the plurality of first bonding wires  410 . 
     The first bonding wires  410  may include at least one of gold (Au), silver (Ag), copper (Cu), or aluminum (Al). According to some embodiments, the first bonding wires  410  may be connected to the plurality of upper memory bonding pads of the plurality of memory chips  210 A,  220 A,  230 A, and  240 A or the upper pads  311  of the signal transmission device  300 A by at least one of, e.g., thermo-compression bonding and a ultrasonic bonding, and a thermo-sonic bonding performed by mixing the thermo-compression bonding and the ultrasonic bonding. 
     The molding member  510  may seal or encapsulate the processor chip  200 , the plurality of memory chips  210 A,  220 A,  230 A, and  240 A, the signal transmission device  300 A, and the first bonding wires  410  with the upper surface of the package substrate  100  to thereby protect them from an external environment, e.g., moisture, an impact, a temperature, or static electricity. 
     The molding member  510  may be formed by injecting an appropriate amount (or a predetermined amount) of molding resin onto the package substrate  100  in an injection process and hardening the injected molding resin in a hardening process, thereby forming an outward appearance of the semiconductor package  10 . In a pressurization process, e.g., a pressing process, the outward appearance of the semiconductor package  10  may be formed by applying a pressure to the molding resin. Process conditions, e.g., a delay time between the injection process and the pressurization process on the molding resin, the amount of injected molding resin, a pressing pressure, and a pressing temperature, may be set in consideration of properties, e.g., a viscosity. According to some embodiments, the molding resin may include, e.g., epoxy-group molding resin or polyimide-group molding resin. 
     The molding member  510  may protect the processor chip  200  and the plurality of memory chips  210 A,  220 A,  230 A, and  240 A from an external influence, e.g., moisture, an impact, a temperature, or static electricity. For this protection, the molding member  510  may have a thickness  510 T for surrounding a lateral surface of at least the processor chip  200  and respective lateral surfaces of the plurality of memory chips  210 A,  220 A,  230 A, and  240 A. For example, the thickness  510 T of the molding member  510  may be greater than a thickness of the processor chip  200  or a total thickness of the plurality of memory chips  210 A,  220 A,  230 A, and  240 A. According to some embodiments, the molding member  510  may surround or cover an upper surface of the processor chip  200  and/or upper surfaces of the plurality of memory chips  210 A,  220 A,  230 A, and  240 A. According to other embodiments, the molding member  510  may expose the upper surface of the processor chip  200  and/or the upper surfaces of the plurality of memory chips  210 A,  220 A,  230 A, and  240 A. 
     In some embodiments, the molding member  510  may entirely/partially cover the package substrate  100 , and may have a width  510 W that may be substantially the same as a width of the package substrate  100  or the semiconductor package  10  in, e.g., the horizontal direction. 
     The plurality of memory chips  210 A,  220 A,  230 A, and  240 A may be stacked to overlap each other, and may have side walls aligned with each other vertically. At least one of the plurality of first bonding wires  410  may penetrate through e.g., a side wall of at least one of the adhesion members  223 ,  233 , and  243 . In this case, compared with semiconductor packages in which a plurality of memory chips are horizontally shifted by a certain distance from each other and vertically stacked, a plane area of the semiconductor package  10  may be relatively small, and accordingly, the width  510 W of the molding member  510  may decrease. 
     In general, a processor chip and a plurality of memory chips may be arranged adjacent to each other in a semiconductor package, and may transmit a signal to each other via an internal trace of a package substrate of the semiconductor package. In this case, a signal transmission between the plurality of memory chips and the internal trace of the package substrate may be performed through a through-silicon via (TSV), not through wire bonding. Use of the TSV for the signal transmission may increase a manufacturing cost of a semiconductor package and complicate a manufacturing process thereof, compared to use of the wire bonding for the signal transmission. 
     On the contrary, in the semiconductor package  10  according to an embodiment, signals of the plurality of memory chips  210 A,  220 A,  230 A, and  240 A may be transmitted to the signal transmission device  300 A via the plurality of first bonding wires  410  without passing through the package substrate  100  or without using any trace/wire of the package substrate  100 , and a signal of the processor chip  200  may be transmitted to the signal transmission device  300 A via the internal trace  110  of the package substrate  100  and then via the bonding balls  320 . 
     In other words, signal transmission paths between the processor chip  200  and the plurality of memory chips  210 A,  220 A,  230 A, and  240 A may be formed with, e.g., the plurality of first bonding wires  410 , the signal transmission device  300 , and the internal trace  110  of the package substrate  100 . As a result, the signal transmission paths between the processor chip  200  and the plurality of memory chips  210 A,  220 A,  230 A, and  240 A may be efficiently arranged in the semiconductor package  10  to reduce a size of the semiconductor package  10 , compared to when the signal transmission paths between the processor chip  200  and the plurality of memory chips  210 A,  220 A,  230 A, and  240 A may be formed with only the internal trace of the package substrate  100  or only the plurality of first bonding wires  410 . Further, the plurality of first bonding wires  410  and the internal trace  110  of the package substrate  100  may not be adjacent to each other in the horizontal direction, and thus the influence between the signal transmission paths between the processor chip  200  and the plurality of memory chips  210 A,  220 A,  230 A, and  240 A, e.g., crosstalk, may be reduced. Moreover, the signal transmission paths between the processor chip  200  and the plurality of memory chips  210 A,  220 A,  230 A, and  240 A may be distributed in different routes, e.g., the plurality of first bonding wires  410  and the internal trace  110  of the package substrate  100 , for efficient distribution of electrical resistances/impedances for signal transmission, for efficient distribution of electrical resistances/impedances for signal transmission and thus the semiconductor package  10  may have improved performance. 
     Signal transmission between the processor chip  200  and the signal transmission device  300 A and signal transmission between the plurality of memory chips  210 A,  220 A,  230 A, and  240 A and the signal transmission device  300 A will be described below. 
       FIG. 1C  illustrates a magnified view of a portion C of  FIG. 1A . 
     The processor chip  200  may include chip pads  202  on it lower surface. The chip pads  202  may be connected to a semiconductor device of the processor chip  200  via a wiring structure (not shown). The signal transmission device  300 A may include the lower pads  312  on its lower surface. The lower pads  312  may be electrically connected to the upper pads  311  in  FIG. 1D  via the penetrating electrodes  310  formed in the main body portion of the base substrate  301 . The chip pads  202  and the lower pads  312  may be used as terminals for the signal transmission between the processor chip  200  and the signal transmission device  300 A. The numbers of the chip pads  202  and the lower pads  312  and arrangements thereof are illustrated as an example, and may be appropriately selected or determined according to the type and capacity of the semiconductor package  10 . 
     The internal trace  110  of the package substrate  100  may electrically connect the processor chip  200  to the signal transmission device  300 A. For example, the chip pads  202  may be electrically connected to the internal trace  110  via bonding balls  204  and the upper substrate pads  111 , and the lower pads  312  may be electrically connected to the internal trace  110  via the bonding balls  320  and the upper substrate pads  111 . In other words, the processor chip  200  and the signal transmission device  300 A may transmit (e.g., send and receive) a signal via the internal trace  110  of the package substrate  100 . 
       FIG. 1D  illustrates a magnified view of a portion D of  FIG. 1A . 
     The memory chip  210 A may include the upper memory bonding pad  211  on it upper surface. The upper memory bonding pad  211  may be connected to a semiconductor device of the memory chip  210 A via a wiring structure (not shown). The signal transmission device  300 A may include the upper pads  311  on its upper surface. The upper pads  311  may be electrically connected to the lower pads  312  in  FIG. 1C  via the penetrating electrodes  310 . The upper memory bonding pads  211  and the upper pads  311  may be used as terminals for the signal transmission between the plurality of memory chips  210 A,  220 A,  230 A, and  240 A and the signal transmission device  300 A. The numbers of the upper memory bonding pads  211  and upper pads  311  and arrangements thereof are illustrated as an example, and may be appropriately selected or determined according to the type and capacity of the semiconductor package  10 . 
     The first bonding wires  410  may electrically connect the memory chip  210 A to the signal transmission device  300 A. For example, the first bonding wires  410  may electrically connect the upper memory bonding pads  211  to the upper pads  311 . In other words, the memory chip  210 A and the signal transmission device  300 A may transmit a signal via the first bonding wires  410 . 
     Referring to  FIGS. 1A-1D , in the semiconductor package  10  according to an embodiment, the signal transmission between the processor chip  200  and the signal transmission device  300 A may be performed via the internal trace  110  of the package substrate  100 , and the signal transmission between the plurality of memory chips  210 A,  220 A,  230 A, and  240 A and the signal transmission device  300 A may be performed via the first bonding wires  410 . Thus, in the semiconductor package  10 , the processor chip  200  and the plurality of memory chips  210 A,  220 A,  230 A, and  240 A may transmit a signal to each other via the signal transmission device  300 A. 
       FIGS. 2A and 2B  illustrate a semiconductor package  20  according to an embodiment. 
       FIG. 2A  illustrates a vertical sectional view of the semiconductor package  20 , and  FIG. 2B  illustrates a plan view of the semiconductor package  20 . In  FIG. 2B , a molding member  520  is not shown for clearly showing an internal structure of the semiconductor package  20 . 
     Referring to  FIGS. 2A and 2B , the semiconductor package  20  includes the package substrate  100 , the processor chip  200 , a plurality of memory chips  210 B,  220 B,  230 B, and  240 B, a signal transmission device  300 B, the plurality of first bonding wires  410 , and the molding member  520 . 
     Components that constitute the semiconductor package  20  and materials used to form the components are the same as or similar to those described above with reference to  FIGS. 1A and 1B , and thus differences therebetween will be described. 
     The plurality of memory chips  210 B,  220 B,  230 B, and  240 B may be sequentially stacked on the second region  102  of the package substrate  100  in a vertical direction (i.e., in a z direction). The plurality of memory chips  210 B,  220 B,  230 B, and  240 B are shifted by a certain distance from each memory chip in a horizontal direction (i.e., in an x direction) on the package substrate  100  such that the upper memory bonding pads  211 ,  221 , and  231  formed in respective portions of the upper surfaces of the plurality of memory chips  210 B,  220 B,  230 B, and  240 B do not overlap each other in the vertical direction and are not covered by the adhesion member  223 ,  233 , and  243 . As the plurality of memory chips  210 B,  220 B,  230 B, and  240 B are positioned farther from the package substrate  100  in the vertical direction, the plurality of memory chips  210 B,  220 B,  230 B, and  240 B may be dispositioned farther from the processor chip  200  in the horizontal direction. 
     As a result, the plurality of first bonding wires  410  may be connected to the upper memory bonding pads  211 ,  221 ,  231 , and  241  without penetrating through the adhesion member  223 ,  233 , and  243 . Thus, the plurality of first bonding wires  410  may electrically connect the upper memory bonding pads  211 ,  221 ,  231 , and  241  to the signal transmission device  300 B without penetrating through the adhesion member  223 ,  233 , and  243 . This may bring a difference in a manufacturing process. For example, after all of the plurality of memory chips  210 B,  220 B,  230 B, and  240 B are sequentially stacked, the plurality of first bonding wires  410  may be formed in batches. 
     Compared with semiconductor packages including a plurality of memory chips that are arranged and stacked vertically, a plane area of the semiconductor package  20  may increase, and accordingly, a width  520 W of the molding member  520  may increase. 
       FIGS. 3A and 3B  illustrate a semiconductor package  30  according to an embodiment. 
       FIG. 3A  illustrates a vertical sectional view of the semiconductor package  30 , and  FIG. 3B  illustrates a plan view of the semiconductor package  30 . In  FIG. 3B , a molding member  530  is not shown for clearly showing an internal structure. 
     Referring to  FIGS. 3A and 3B , the semiconductor package  30  includes the package substrate  100 , the processor chip  200 , a plurality of memory chips  210 C,  220 C,  230 C, and  240 C, a signal transmission device  300 C, the plurality of first bonding wires  410 , a second bonding wire  420 , and the molding member  530 . 
     Components that constitute the semiconductor package  30  and materials used to form the components are the same as or similar to those described above with reference to  FIGS. 1A and 1B , and thus differences therebetween will be described. 
     The plurality of memory chips  210 C,  220 C,  230 C, and  240 C may be sequentially stacked on the second region  102  of the package substrate  100  in a vertical direction (i.e., in a z direction). The plurality of memory chips  210 C,  220 C,  230 C, and  240 C are shifted by a certain distance from each memory chip in a horizontal direction (i.e., in an x direction) on the package substrate  100  such that the upper memory bonding pads  211 ,  221 , and  231  formed in respective portions of the upper surfaces of the plurality of memory chips do not overlap each other in the vertical direction and are not covered by the adhesion member  223 ,  233 , and  243 . As the plurality of memory chips  210 C,  220 C,  230 C, and  240 C are positioned farther from the package substrate  100  in the vertical direction, the plurality of memory chips  210 C,  220 C,  230 C, and  240 C may be dispositioned farther from the processor chip  200  in the horizontal direction. 
     The plurality of first bonding wires  410  may electrically connect the plurality of memory chips  210 C,  220 C,  230 C, and  240 C to the signal transmission device  300 C. The plurality of first bonding wires  410  may connect the plurality of upper memory bonding pads  211 ,  221 ,  231 , and  241  of the plurality of memory chips  210 C,  220 C,  230 C, and  240 C to the upper pads  311  of the signal transmission device  300 C, respectively. For convenience of explanation, the accompanying drawings illustrate some of the plurality of first bonding wires  410 . 
     The second bonding wire  420  may directly connect the plurality of memory chips  210 C,  220 C,  230 C, and  240 C to the upper substrate pad  111  of the package substrate  100  without via the signal transmission device  300 C. The second bonding wire  420  (instead of the first bonding wires  410 ) may connect a power/ground pad of the upper memory bonding pad  211 ,  221 ,  231 , and  241  of the plurality of memory chips  210 C,  220 C,  230 C, and  240 C to a power/ground pad of the upper substrate pads  111  of the package substrate  100 . 
     The second bonding wire  420  may be connected to a pad that provides a power/ground voltage to the plurality of memory chips  210 C,  220 C,  230 C, and  240 C, from among the upper memory bonding pads  211 ,  221 ,  231 , and  241 . According to some embodiments, the second bonding wire  420  may connect the memory chip  210 C at the lowest position among the plurality of memory chips  210 C,  220 C,  230 C, and  240 C to the package substrate  100  and connect the plurality of memory chips  210 C,  220 C,  230 C, and  240 C to each other. Thus, the second bonding wire  420  may serially and sequentially connect the pad for the power/ground voltage of the package substrate  100  and the upper memory bonding pads  211 ,  221 ,  231 , and  241  of the plurality of memory chips  210 C,  220 C,  230 C, and  240 C. 
     While input/output (I/O) signal transmission may be performed between the processor chip  200  and the plurality of memory chips  210 C,  220 C,  230 C, and  240 C via the signal transmission device  300 C in a bilateral direction, a supply of the power/ground voltage may be performed between the plurality of memory chips  210 C,  220 C,  230 C, and  240 C and the package substrate  100  in a unilateral direction via the second bonding wire  420 . In this case, the signal transmission device  300 C may perform the I/O signal transmission between the processor chip  200  and the plurality of memory chips  210 C,  220 C,  230 C, and  240 C without supplying the power/ground voltage, and thus interference of the I/O signal transmission, which may be caused by, e.g., the power/ground voltage, may be reduced. Moreover, the plurality of memory chips  210 C,  220 C,  230 C, and  240 C may minimize power loss and may stably receive the power/ground voltage, as the plurality of memory chips  210 C,  220 C,  230 C, and  240 C may be powered and grounded to the outside via the external connection terminals  120  without passing through the signal transmission device  300 C. 
       FIGS. 4A and 4B  illustrate a semiconductor package  40  according to an embodiment. 
       FIG. 4A  illustrates a vertical sectional view of the semiconductor package  40 , and  FIG. 4B  illustrates a plan view of the semiconductor package  40 . In  FIG. 4B , a molding member  540  is not shown for clearly showing an internal structure of the semiconductor package  40 . 
     Referring to  FIGS. 4A and 4B , the semiconductor package  40  includes the package substrate  100 , the processor chip  200 , a plurality of memory chips  210 D,  220 D,  230 D, and  240 D that may exchange data with each other, a signal transmission device  300 D, the plurality of first bonding wires  410 , and the molding member  540 . 
     Components that constitute the semiconductor package  40  and materials used to form the components are the same as or similar to those described above with reference to  FIGS. 1A and 1B , and thus differences therebetween will be described. 
     At least two neighboring memory chips of the plurality of memory chips  210 D,  220 D,  230 D, and  240 D may be connected to one of the upper pads  311  of the signal transmission device  300 D via corresponding first bonding wires  410  to which the at least two neighboring memory chips are connected. For example, corresponding first bonding wires  410  respectively connected to the memory chips  210 D and  220 D may be connected to a single first upper pad  311 , and corresponding first bonding wires  410  respectively connected to the other memory chips  230 D and  240 D may be connected to a single second upper pad  311 . According to other embodiments, all of the plurality of first bonding wires  410  connected to the plurality of memory chips  210 D,  220 D,  230 D, and  240 D may be connected to a single third upper pad  311 . Thus, at least two of the plurality of memory chips  210 D,  220 D,  230 D, and  240 D may be the same kind of memory chips that may perform data combination or data merge between each other. Accordingly, compared with semiconductor packages in which a plurality of memory chips are different kinds of memory chips that may not perform data combination or data merge therebetween, the number of upper pads  311  may decrease, and a width of the signal transmission device  300 D may be reduced. 
     The plurality of memory chips  210 D,  220 D,  230 D, and  240 D may be aligned with each other vertically, and at least one of the plurality of first bonding wires  410  may penetrate through at least one of the adhesion members  223 ,  233 , and  243 . Moreover, the width of the signal transmission device  300 D may be reduced such that a horizontal distance between the processor chip  200  and the plurality of memory chips  210 D,  220 D,  230 D, and  240 D may decrease. In this case, compared with the semiconductor packages in which the plurality of memory chips are different kinds of memory chips, an area of the semiconductor package  40  may decrease, and accordingly, a width  540 W of the molding member  540  may decrease. 
       FIGS. 5A and 5B  illustrate a semiconductor package  50  according to an embodiment. 
       FIG. 5A  illustrates a vertical sectional view of the semiconductor package  50 , and  FIG. 5B  illustrates a plan view of the semiconductor package  50 . In  FIG. 5B , a molding member  550  is not shown for clearly showing an internal structure. 
     Referring to  FIGS. 5A and 5B , the semiconductor package  50  includes the package substrate  100 , the processor chip  200 , a plurality of memory chips  210 E,  220 E,  230 E, and  240 E that may exchange data with each other, a signal transmission device  300 E, a plurality of first bonding wires  410 , and the molding member  550 . 
     Components that constitute the semiconductor package  50  and materials used to form the components are the same as or similar to those described above with reference to  FIGS. 1A and 1B , and thus differences therebetween will be described. 
     The plurality of memory chips  210 E,  220 E,  230 E, and  240 E may be stacked on the second region  102  of the package substrate  100 . The plurality of memory chips  210 E,  220 E,  230 E, and  240 E may be shifted by a certain distance from each memory chip in a horizontal direction on the package substrate  100  and may be sequentially stacked one on another such that the upper memory bonding pads  211 ,  221 , and  231  formed in respective portions of the upper surfaces of the plurality of memory chips  210 E,  220 E,  230 E, and  240 E may not be covered by the adhesion member  223 ,  233 , and  243 . As the plurality of memory chips  210 E,  220 E,  230 E, and  240 E may be positioned farther from the package substrate  100 , the plurality of memory chips  210 E,  220 E,  230 E, and  240 E may be stacked in a direction further away from the processor chip  200 . 
     The plurality of memory chips  210 E,  220 E,  230 E, and  240 E may be connected to one of the upper pads  311  of the signal transmission device  300 E via a plurality of first bonding wires  410  that may be connected to each other in series. For example, the plurality of first bonding wires  410  serially connected to the memory chips  210 E,  220 E,  230 E, and  240 E may be connected to a same first upper pad  311 . The plurality of first bonding wires  410  may connect the plurality of memory chips  210 E,  220 E,  230 E, and  240 E to each other. Thus, all of the plurality of memory chips  210 E,  220 E,  230 E, and  240 E may be the same kind of memory chips that may perform data combination or data merge between each other. Accordingly, compared with semiconductor packages in which a plurality of memory chips are different kinds of memory chips, the number of upper pads  311  may decrease, and accordingly a width of the signal transmission device  300 E may decrease. 
     In this case, compared with the semiconductor packages in which the plurality of memory chips are different kinds of memory chips, an area of the semiconductor package  50  may decrease, and accordingly, a width  550 W of the molding member  550  may decrease. 
       FIGS. 6A and 6B  illustrate a semiconductor package  60  according to an embodiment. 
       FIG. 6A  illustrates a vertical sectional view of the semiconductor package  60 , and  FIG. 6B  illustrates a plan view of the semiconductor package  60 . In  FIG. 6B , a molding member  560  is not shown for clearly showing an internal structure. 
     Referring to  FIGS. 6A and 6B , the semiconductor package  60  includes the package substrate  100 , the processor chip  200 , a plurality of memory chips  210 F,  220 F,  230 F, and  240 F that may exchange data with each other, a signal transmission device  300 F, the plurality of first bonding wires  410 , a third bonding wire  430 , and the molding member  560 . 
     Components that constitute the semiconductor package  60  and materials used to form the components are the same as or similar to those described above with reference to  FIGS. 1A and 1B , and thus differences therebetween will be described below. 
     The plurality of memory chips  210 F,  220 F,  230 F, and  240 F may be stacked on the second region  102  of the package substrate  100 . The plurality of memory chips  210 F,  220 F,  230 F, and  240 F may be shifted by a certain distance from each memory chip in a horizontal direction on the package substrate  100  and may be sequentially stacked one on another such that the upper memory bonding pads  211 ,  221 , and  231  formed in respective portions of the upper surfaces of the plurality of memory chips  210 F,  220 F,  230 F, and  240 F may not be covered by the adhesion member  223 ,  233 , and  243 . 
     As the plurality of memory chips  210 F,  220 F,  230 F, and  240 F may be positioned farther from the package substrate  100 , the plurality of memory chips  210 F,  220 F,  230 F, and  240 F may be stacked in a direction closer to the processor chip  200 . Accordingly, in a plan view, at least a portion of the signal transmission device  300 F may overlap the plurality of memory chips  210 F,  220 F,  230 F, and  240 F. 
     The plurality of memory chips  210 F,  220 F,  230 F, and  240 F may be connected to each other via the third bonding wire  430 . The plurality of first bonding wires  410  may connect redistribution pads  242  formed on an upper surface of the memory chip  240 F at the highest position among the plurality of memory chips  210 F,  220 F,  230 F, and  240 F to the upper pads  311  of the signal transmission device  300 F. Thus, all of the plurality of memory chips  210 F,  220 F,  230 F, and  240 F may be the same kind of memory chips that may perform data combination or data merge between each other. Accordingly, compared with semiconductor packages in which a plurality of memory chips are different kinds of memory chips, the number of upper pads  311  may decrease, and accordingly a width of the signal transmission device  300 F may decrease. 
     The memory chip  240 F at the highest position among the plurality of memory chips  210 F,  220 F,  230 F, and  240 F may further include the redistribution pads  242  and redistribution lines  245 . The redistribution line  245  may electrically connect the upper memory bonding pads  241  to the redistribution pads  242 . The redistribution lines  245  may extend from the upper memory bonding pads  241  to the redistribution pads  242  such that the upper memory bonding pads  241  and the redistribution pads  242  may be flexibly located on the memory chip  240 F. Thus, the redistribution pads  242  may be arranged adjacent to the signal transmission device  300 F. The first bonding wires  410  may electrically connect the redistribution pads  242  to the upper pads  311 . Accordingly, the redistribution pads  242  adjacent to the signal transmission device  300 F may simplify an arrangement of the first bonding wires  410 . For convenience of explanation,  FIG. 6B  illustrates that the redistribution lines  245  are exposed. However, the redistribution lines  245  may not be exposed. 
     The width of the signal transmission device  300 F may decrease. As the signal transmission device  300 F may be partially overlapped by the plurality of memory chips  210 F,  220 F,  230 F, and  240 F, an area independently occupied by the signal transmission device  300 F may be reduced. In this case, compared with semiconductor packages in which a plurality of memory chips are different kinds of memory chips and semiconductor packages in which, when a plurality of memory chips are positioned farther from a package substrate, the plurality of memory chips are shifted by a certain distance from each memory chip in a direction further away from a processor chip and are stacked, an area of the semiconductor package  60  may decrease, and accordingly, a width  560 W of the molding member  560  may decrease. 
       FIG. 7  illustrates a block diagram of a structure of a semiconductor package  1000  according to an embodiment. 
     Referring to  FIG. 7 , the semiconductor package  1000  may include a microprocessor unit (MPU)  1010 , a memory  1020 , an interface  1030 , a graphics processing unit (GPU)  1040 , function blocks  1050 , and a system bus  1060  via which these components may be connected to one another. The semiconductor package  1000  may include both the MPU  1010  and the GPU  1040  or may include either the MPU  1010  or the GPU  1040 . 
     The MPU  1010  may include a core and an L2 cache. For example, the MPU  1010  may include multiple cores. The multiple cores may preform identical functions or different functions. The multiple cores may be activated at the same time or at different time points. 
     The memory  1020  may store results of processes performed in the function blocks  1050 , under the control of the MPU  1010 . The interface  1030  may transmit or received information or signals with external devices. The GPU  1040  may perform graphic functions. For example, the GPU  1040  may perform a video codec or a 3D graphic process. The function blocks  1050  may perform various functions. For example, the semiconductor package  1000  may be an application processor (AP) for use in mobile devices, some of the function blocks  1050  may perform a communication function. The semiconductor package  1000  may include one of the semiconductor packages  10 ,  20 ,  30 ,  40 ,  50 , and  60  according to embodiments described above with reference to  FIGS. 1A-6B . 
     Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.