Patent Publication Number: US-7913012-B2

Title: System and method for connecting a master device with multiple groupings of slave devices via a LINBUS network

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is related to the following: U.S. patent application Ser. No. 11/618,581, filed Dec. 29, 2006 entitled “PRECISION OSCILLATOR HAVING LINBUS CAPABILITIES”; U.S. patent application Ser. No. 9/885,459, filed Jun. 19, 2001 and entitled “FIELD PROGRAMMABLE MIXED-SIGNAL INTEGRATED CIRCUIT”, issued Jan. 30, 2007 as U.S. Pat. No. 7,171,542; U.S. patent application Ser. No. 10/244,728, filed Sep. 16, 2002 entitled “CLOCK RECOVERY METHOD FOR BURSTY COMMUNICATIONS,”issued Jul. 12, 2005 as U.S. Pat. No. 6,917,658; U.S. patent application Ser. No. 10/244,344, filed Sep. 16, 2002, entitled “PRECISION OSCILLATOR FOR AN ASYNCRONOUS TRANSMISSION SYSTEM”; which is a Continuation in Part of U.S. patent application Ser. No. 11/395,378, filed Mar. 31, 2006 entitled “PRECISION OSCILLATOR HAVING IMPROVED TEMPERATURE COEFFICIENT CONTROL”, all of which are incorporated herein by reference. 
     TECHNICAL FIELD 
     The present invention relates to master slave LINBUS connections, and more particularly to a system and method for interconnecting a single LINBUS master with multiple groups of LINBUS slaves. 
     BACKGROUND 
     LINBUS devices have the ability to interconnect via a local interconnect network (LIN) bus. A LIN interface is an asynchronous serial communications interface used primarily in automobile networks. LIN compatible devices have the ability to provide a selectable master and slave modes, unique synchronization without a quartz crystal or ceramic resonator in both the master and slave modes, and has fully configurable transmission/reception characteristics via special function registers. In existing LINBUS configurations, a single master may be in connection with and communicating with up to twenty slave devices. Since the LINBUS networks are also used to provide interconnections with a plurality of sensors on an automobile, and since the number of sensors on automobiles is greatly increasing with the improved sensing and monitoring technologies available within the modem day automobile, there has arisen a need to have the ability to extend the capabilities of a LINBUS network beyond the twenty slave limit that presently associated with the master. Thus, some means for enabling the increased number of slaves within a particular LINBUS connection would be of great benefit. 
     SUMMARY OF THE INVENTION 
     The present invention, as disclosed and described herein, in one aspect thereof, comprises a LINBUS communications network including a microcontroller unit containing processing circuitry for performing predefined digital processing functions and a plurality of groups of slave devices. A LINBUS network communications hardware is located within the microcontroller unit for digitally communicating with an off-chip LINBUS device for transmitting data thereto and receiving data therefrom. A plurality of LINBUS communication network interfaces each selectively connect one of the plurality of groups of slave devices to the LINBUS network communications hardware. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying Drawings in which: 
         FIG. 1  illustrates an overall block diagram of a mixed-signal integrated circuit utilizing a UART in association with one of the communication ports; 
         FIG. 2  illustrates a more detailed diagram of the integrated circuit of  FIG. 1 ; 
         FIG. 3  illustrates a block diagram of the UART; 
         FIG. 3A  illustrates a block diagram of the baud rate generator; 
         FIG. 4  illustrates a block diagram of the precision oscillator; 
         FIG. 5  illustrates a more detailed diagram of the precision oscillator of  FIG. 4 ; 
         FIG. 6  illustrates an output waveform diagram of a precision oscillator; 
         FIG. 7  illustrates a schematic diagram of the temperature compensated reference voltage; 
         FIG. 8  illustrates a schematic diagram of one-half of the output wave shaping circuit; 
         FIG. 9  illustrates a schematic diagram/layout for one of the resistors illustrating the mask programmable feature thereof; 
         FIG. 10  illustrates a schematic diagram of the programmable capacitor; 
         FIG. 11  illustrates a schematic diagram of the comparator; 
         FIG. 12  illustrates a logic diagram for the S/R latch in combination with the comparator; 
         FIG. 13  illustrates a schematic diagram of the delay block; 
         FIG. 14  illustrates a schematic diagram for an offset circuit for the comparator; 
         FIG. 15  illustrates a block diagram of one instantiation of the oscillator; and 
         FIGS. 16 and 17  illustrate tables for the oscillator controls; 
         FIG. 18  illustrates a schematic diagram of the precision oscillator including a programmable resistor array; 
         FIGS. 19   a  and  19   b  depict a schematic diagram of a programmable resistor array implementing a funneling scheme to control leakage currents; 
         FIG. 20  is a flow diagram illustrating the process for controlling the programmable resistor area of  FIGS. 19   a  and  19   b;    
         FIGS. 21   a  and  21   b  illustrate a further embodiment of a programmable resistor array implemented utilizing low leakage switches; 
         FIG. 22  is a schematic diagram of an individual low leakage switch implemented within the programmable resistor array of  FIG. 21 ; and 
         FIG. 23  is a schematic diagram illustrating an implementation of a programmable resistor array for the top resistor of the resistor voltage divider providing a voltage input to the precision oscillator. 
         FIGS. 24   a  and 24 b  depict a schematic diagram of the SR latch of the precision oscillator; 
         FIG. 25  is a schematic diagram of the comparators used within the precision oscillator; 
         FIG. 26  is a flow diagram illustrating the operation of the source degeneration circuit of the comparator; 
         FIG. 27  illustrates the programmable offset voltage circuit provided by the comparator; 
         FIG. 28  illustrates utilizing the curvature of the temperature variation provided by transistors within the comparator to achieve a linear temperature variation for the oscillator; 
         FIG. 29  illustrates the use of a programmable transistor array to control the temperature variation curvature; 
         FIG. 30  illustrates the operation of a comparator having a digitally programmable temperature variation curve; 
         FIG. 31  illustrates a further embodiment of the band-gap generator enabling programmability of the temperature coefficients of the band-gap reference voltage; 
         FIGS. 32   a - 32   d  depict a schematic diagram of the band-gap generator; 
         FIG. 33  is a functional block diagram of the frequency trimming on-the-fly functionality of the oscillator; 
         FIG. 34  is a flow diagram illustrating the process for frequency trimming on-the-fly for the oscillator based upon temperature; 
         FIG. 35  illustrates the separate coarse and fine tune frequency trimming of the capacitor within the RC circuit of the oscillator; 
         FIG. 36  is an illustration of the coarse capacitor array; 
         FIG. 37  is a schematic diagram of the fine capacitor array; and 
         FIG. 38  is a schematic diagram of the temperature capacitor array. 
         FIG. 39  is an illustration of an implementation of a LINBUS network; 
         FIG. 40  is a block diagram of the LINBUS communications interface; 
         FIG. 41  is a flow diagram illustrating the manner in which data is transmitted through the LINBUS communications interface; 
         FIG. 42  illustrates the LINBUS address register; 
         FIG. 43  illustrates the LINBUS data register; 
         FIG. 44  illustrates the LINBUS control mode register; 
         FIG. 45  illustrates the remaining LINBUS registers; and 
         FIG. 46  illustrates an automotive network including a number of master devices interconnected via a CAN network each of the master devices having associated slave devices connected via a LINBUS; 
         FIG. 47  illustrates a plurality of master devices each interconnected to a single group of slaves via a LINBUS network; 
         FIG. 48  illustrates the manner in which a master device initiates a communication with a slave device over the LINBUS network; 
         FIG. 49  illustrates a method for connecting a single master device to a plurality of different groupings of slave devices via a LINBUS network; 
         FIG. 50   a  illustrates a P#MAT SFR register; 
         FIG. 50   b  illustrates a P#MASK SFR register; 
         FIG. 52  is a flow diagram illustrating the manner for interconnecting the master device with a plurality of slave devices via a LINBUS network; 
         FIG. 51  is a flow diagram illustrating a first manner for selecting the group of slave devices for connection to the master device; and 
         FIG. 53  is a flow diagram illustrating a further embodiment for selecting a group of slave devices for interconnection with the master device. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the drawings, wherein like reference numbers are used herein to designate like elements throughout the various views, embodiments of the present invention are illustrated and described, and other possible embodiments of the present invention are described. The figures are not necessarily drawn to scale, and in some instances the drawings have been exaggerated and/or simplified in places for illustrative purposes only. One of ordinary skill in the art will appreciate the many possible applications and variations of the present invention based on the following examples of possible embodiments of the present invention. 
     Referring now to  FIG. 1 , there is illustrated an integrated circuit that is comprised of a fully integrated mixed-signal System on a Chip with a true 12-bit multi-channel ADC  110  with a programmable gain pre-amplifier  112 , two 12-bit DACs  114  and  116 , two voltage comparators  118  and  120 , a voltage reference  122 , and an 8051-compatible microcontroller core  140  with 32 kbytes of FLASH memory  126 . There is also provided an I2C/SMBUS  128 , a UART  130 , and an SPI  132  serial interface implemented in hardware (not “bit-banged” in user software) as well as a Programmable Counter/Timer Array (PCA)  134  with five capture/compare modules. There are also 32 general purpose digital Port I/Os. The analog side further includes a multiplexer  113  as operable to interface eight analog inputs to the programmable amplifier  112  and to the ADC  110 . 
     With an on-board V DD  monitor  136 , WDT, and clock oscillator  137 , the integrated circuit is a stand-alone System on a Chip. The MCU effectively configures and manages the analog and digital peripherals. The FLASH memory  126  can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. The MCU can also individually shut down any or all of the peripherals to conserve power. 
     A JTAG interface  142  allows the user to interface with the integrated circuit through a conventional set of JTAG inputs  144 . On-board JTAG emulation support allows non-intrusive (uses no on-chip resources), full speed, in-circuit emulation using the production integrated circuit installed in the final application. This emulation system supports inspection and modification of memory and registers, setting breakpoints, watch points, single stepping, run and halt commands. All analog and digital peripherals are fully functional when emulating using JTAG. 
     The microcontroller  140  is fully compatible with the MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop software. The core has all the peripherals included with a standard 8052, including three 16-bit counter/timers, a full-duplex UART, 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and four byte-wide I/O Ports. 
     Referring further to  FIG. 1 , the core  141  is interfaced through an internal BUS  150  to the various input/output blocks. A cross-bar switch  152  provides an interface between the UART  130 , SPI BUS  132 , etc., and the digital I/O output this is a configurable interface. That can be associated with the V DD  monitor  136 . 
     The core  140  employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12 MHz. By contrast, the core  140  executes seventy percent (70%) of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. The core  140  has a total of 109 instructions. The number of instructions versus the system clock cycles to execute them is as follows: 
     
       
         
           
               
               
            
               
                   
                   
               
               
                   
                 Instructions 
               
            
           
           
               
               
               
               
               
               
               
               
               
               
            
               
                   
                 26 
                 50 
                 5 
                 14 
                 7 
                 3 
                 1 
                 2 
                 1 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
               
               
               
               
               
            
               
                 Clocks to Execute 
                 1 
                 2 
                 ⅔ 
                 3 
                 ¾ 
                 4 
                 ⅘ 
                 5 
                 8 
               
               
                   
               
            
           
         
       
     
     With the core  140 &#39;s maximum system clock at 20 MHz, it has a peak throughput of 20 MIPS. 
     As an overview to the system of  FIG. 1 , the cross-bar switch  152  can be configured to interface any of the ports of the I/O side thereof to any of the functional blocks  128 ,  130 ,  132 ,  134 ,  135  or  136  which an provide interface between the cross-bar switch  152  and the core  140 . Further, the cross-bar switch can also interface through these functional blocks  128 - 136  directly to the BUS  150 . 
     Referring now to  FIG. 2 , there is illustrated a more detailed block diagram of the integrated circuit of  FIG. 1 . In this embodiment, it can be seen that the cross-bar switch  152  actually interfaces to a system BUS  202  through the BUS  150 . The BUS  150  is a BUS as operable to allow core  140  to interface with the various functional blocks  128 - 135  in addition to a plurality of timers  204 ,  206 ,  208  and  210 , in addition to three latches  212 ,  214  and  216 . The cross-bar switch  152  is configured with a configuration block  220  that is configured by the core  140 . The other side of the cross-bar switch  152 , the I/O side, is interfaced with various port drivers  222 , which are controlled by a port latch  224  that interfaces with the BUS  150 . In addition, the core  140  is operable to configure the analog side with an analog interface configuration in control block  226 . 
     The core  140  is controlled by a clock on a line  232 . The clock is selected from, as illustrated, one of two locations with a multiplexer  234 . The first is external oscillator circuit  137  and the second is an internal oscillator  236 . The internal oscillator circuit  236  is a precision temperature and supply compensated oscillator, as will be described herein below. The core  140  is also controlled by a reset input on a reset line  154 . The reset signal is also generated by the watchdog timer (WDT) circuit  136 , the clock and reset circuitry all controlled by clock and reset configuration block  240 , which is controlled by the core  140 . Therefore, it can be seen that the user can configure the system to operate with an external crystal oscillator or an internal precision non-crystal non-stabilized oscillator that is basically “free-running.” This oscillator  236 , as will be described herein below, generates the timing for both the core  140  and for the UART  130  timing and is stable over temperature. 
     Referring now to  FIG. 3 , there is illustrated a block diagram of the UART  130 . A system clock is input to a baud rated generator  302  which provides a transmit clock on the line  304  and a receive clock on a line  306 . The transmit clock is input to a transmit control block  308  and the receive clock is input to a receive control block  310 . A serial control register (SCON 0 )  320  is provided that is operable to provide control signals to the control blocks  308  and  310 . The transmit data is received from a bus  322  and is input through a gate  324  to a serial data buffer (SBUF)  326 . The output of this data is input to a zero detector  328  and then to a control block  308 . The system is an asynchronous, full duplex serial port device and two associated special function registers, a serial control register (SCON 0 )  320  and a serial data buffer (SBUF 0 ) (not shown), are provided. Data is received on a line  312  and is input to an input shift register  314 . This is controlled by the control block  310  to output the shifted-in data to a latch  332  and then through a gate  334  to an SFR bus  322 . In transmit mode, data is received from an SFR bus  322  and input through a gate  324  to a transmit shift register  326  which is output to a transmit line  319  from the register  326  or from the control block  308  through an AND gate  358  which is input to one input of an OR gate  340  to the transmit line  319 . This is all controlled by the control block  308 . 
     Referring now to  FIG. 3A , there is illustrated a block diagram of the baud rate generator  302 . This baud rate is generated by a timer wherein a transmit clock is generated by a block TL 1  and the receive clock is generated by a copy of the TL 1  illustrated as an RX Timer, which copy of TL 1  is not user-accessible. Both the transmit and receive timer overflows are divided by two for the transmit clock and the receive clock baud rates. The receive timer runs when timer  1  is enabled, and uses the same TH 1  value, this being a reload value. However, an RX Timer reload is forced when Start Condition is detected on the receive pin. This allows a receipt to begin any time a Start is detected, independent of the state of the transmit timer. 
     Referring now to  FIG. 4 , there is illustrated a diagrammatic view of the precision internal oscillator  236  that is disposed on integrated circuit. The integrated circuit, as noted hereinabove, is a commercially available integrated circuit that incorporates the precision oscillator  236  in association therewith. The integrated circuit provides the capability of selecting a crystal oscillator wherein a crystal is disposed between two crystal ports, selecting an external clock signal or selecting an internal free-running oscillator. The free-running oscillator is illustrated in  FIG. 4  as the precision oscillator  236 . At the center of the oscillator are two comparators, a first comparator  402  and a second comparator  404 . A temperature compensated voltage reference circuit  406  is provided that provides a temperature compensated voltage reference (the trip voltage V TRIP ) to the negative inputs of the comparators  402 . The outputs of the comparators  402  and  404  are connected to the Set and Reset, respectively, inputs of an S/R latch  408 . The Q and Q-Bar outputs thereof are input to an output RC timing circuit  410  that is operable to define the period of the oscillator, the output of the S/R latch  408  providing the output clock signal. The output of this RC timing circuit  410  is fed back to the positive inputs of the comparators  402  and  404 . The output RC timing circuit  410  is also temperature compensated. As will be described herein below, the voltage reference block  406  provides a negative temperature coefficient, whereas the comparators  402  and S/R latch  408  combination provide a positive temperature coefficient and the output RC timing circuit  410  provide a positive temperature coefficient. The overall combined coefficient will be approximately zero, as will be described herein below. 
     Referring now to  FIG. 5 , there is illustrated a more detailed diagrammatic view of the precision oscillator of  FIG. 4 . The voltage reference circuit  406  is comprised of a voltage divider that divides the supply voltage V DD  to a voltage V TRIP  on a node  502 . The voltage divider is comprised of a top resistor  504  labeled R 3 . The bottom half of the voltage divider is comprised of two parallel resistors, a resistor  506  labeled R 2  and a resistor  508  labeled R 4 . For nomenclature purposes, the resistors will be referred as R 2 , R 3  and R 4 . 
     Resistors R 3  and R 4  are fabricated from the same material to provide a positive temperature coefficient. These are fabricated from the N-diffusion material, which has a positive temperature coefficient. By comparison, R 2  is manufactured from polycrystalline silicon in the first layer which is referred to as Poly1 material, and which also has a positive temperature coefficient, but which differs. It should be understood that different materials could be utilized, it only being necessary that there be two resistors having different temperature coefficients. Although not a part of this disclosure, Poly1 material is basically the first layer of polycrystalline silicon that is disposed on the substrate over a protective oxide layer, from which such structures as the gates of transistors are fabricated. With the positive temperature coefficients of the resistors, this will result in the voltage V TRIP  having a negative coefficient. As will be described herein below, the resistors being of different materials facilitates adjustments between the two resistors R 2  and R 4  to vary the temperature coefficient. This is primarily due to the fact that they are of differing materials. 
     The output RC timing circuit  410  is comprised of two RC circuits. The first RC circuit is comprised of a P-channel transistor  520  having the source/drain path thereof connected between V DD  and one side of a resistor  522  labeled R, the other end thereof connected to a node  524 . Node  524  is connected to one side of a capacitor  526 , the other side of the capacitor  526  connected to V SS . —channel transistor  528  has the source/drain path thereof connected across capacitor  526 , and the gate thereof connected to the gate of P-channel transistor  520  and also to the Q-output of the S/R latch  408 . Node  524  comprises the positive input of the comparator  402 . The second RC network is comprised of a P-channel transistor  530  having the source/drain path thereof connected between V DD  and one side of a resistor  532  (labeled R), the other side of resistor  532  connected to a node  534 . Node  534  is connected to one side of a capacitor  536 , the other side thereof connected to V SS . An N-channel transistor  538  has the source/drain path thereof connected between node  534  and V SS . The gate of transistor  538  is connected to the gate of transistor  530  and also to the Q-Bar output of S/R latch  408 . The node  534  comprises the positive input of the comparator  404 . The output waveform for the circuit of  FIG. 5  is illustrated in  FIG. 6 , wherein conventional RC rise and fall curves are illustrated for each of the RC circuits. The period of each output waveform is defined from the initial turn-on point where voltage is applied to the resistor R to the point where resistor R of the other of the RC circuits is turned on. There will be period T 1  and a period T 2  for each of the RC circuits, respectively. The sum of the two periods is equal to the period for the oscillator. Transistors  520 ,  530 ,  528  and  538  are sized such that their resistances are substantially less than the value of resistors  522  and  532 . The resistors  522  and  532  are fabricated from Poly1 material due to its low temperature coefficient. The period of the oscillator is the sum of the period T 1  and the period T 2 +2 times the delay of the comparators. 
     Referring now to  FIG. 7 , there is illustrated more detailed block diagram of the implementation of the voltage reference  406 . The resistor  504  which is illustrated in  FIG. 5  as being connected to V DD  is actually connected through the source/drain of the P-channel resistor  702  to V DD  with the gate thereof connected to a bias voltage. Similarly, the bottom end of resistor  506  is connected to V SS  through the source/drain path of a N-channel transistor  706  to V SS , the gates of both transistors  704  and  706  connected to a bias. Transistors  702 ,  704  and  706  are sized such that their resistances are substantially less than the value of resistors R 2 , R 3  and R 4 . Also, first order power supply independence comes from the fact that the trip voltage V Trip  is proportional to the supply voltage, i.e., V DD *(1−e(t/τ)). Therefore, in the time it takes to reach the trip voltage at the input of the comparator is supply independent to the first order. This is one reason that the RC timing circuits are utilized rather than a current source charging a capacitor, which does not provide the first order cancellation.
 
 V   Trip   =V   DD *ratio
 
 V   Trip   =V   DD *(1 −e (− T 1/τ))
 
 T 1=−τ*1 n (1 −V   Trip   /V   DD  
 
Thus: T 1=−τ*1 n (1−ratio)
 
     From a temperature compensation standpoint, there are a number of aspects of the voltage reference circuit  406  that can be utilized to provide temperature compensation. Commonly, the resistors have a set variation with respect to temperature. The Poly1 resistor R 2  has a temperature coefficient of 255 ppm whereas the N-diffused resistors R 3  and R 4  have a temperature coefficient of 800 ppm. In the present disclosure, it is desirable to have a negative coefficient of 462 ppm. 
     To analyze how a negative temperature coefficient is created with the resistors R 2 , R 3  and R 4 , consider that R 2  and R 4  are a parallel combination defined as REQ=R 2 //R 4 . If REQ and R 3  have different temperature coefficients with TCR 3 &gt;TCREQ, then the trip voltage will have a negative temperature coefficient. V TRIP  will be defined as follows: 
     
       
         
           
             
               
                 
                   
                     V 
                     TRIP 
                   
                   = 
                   
                     
                       REQ 
                       
                         
                           R 
                           3 
                         
                         + 
                         REQ 
                       
                     
                     ⁢ 
                     
                       V 
                       DD 
                     
                   
                 
               
             
             
               
                 
                   
                     
                       
                         
                           
                             1 
                             
                               V 
                               TRIP 
                             
                           
                           ⁢ 
                           
                             
                               ⅆ 
                               
                                 V 
                                 TRIP 
                               
                             
                             
                               ⅆ 
                               T 
                             
                           
                         
                         = 
                         
                           
                             
                               1 
                               REQ 
                             
                             ⁢ 
                             
                               
                                 ⅆ 
                                 REQ 
                               
                               
                                 ⅆ 
                                 T 
                               
                             
                           
                           - 
                           
                             
                               
                                 R 
                                 3 
                               
                               
                                 
                                   R 
                                   3 
                                 
                                 + 
                                 REQ 
                               
                             
                             ⁡ 
                             
                               [ 
                               
                                 
                                   1 
                                   REQ 
                                 
                                 ⁢ 
                                 
                                   
                                     ⅆ 
                                     REQ 
                                   
                                   
                                     ⅆ 
                                     T 
                                   
                                 
                               
                               ] 
                             
                           
                           - 
                         
                       
                     
                   
                   
                     
                       
                         
                           
                             R 
                             3 
                           
                           
                             
                               R 
                               3 
                             
                             + 
                             REQ 
                           
                         
                         ⁡ 
                         
                           [ 
                           
                             
                               1 
                               
                                 R 
                                 3 
                               
                             
                             ⁢ 
                             
                               
                                 ⅆ 
                                 
                                   R 
                                   3 
                                 
                               
                               
                                 ⅆ 
                                 T 
                               
                             
                           
                           ] 
                         
                       
                     
                   
                 
               
             
             
               
                 
                   
                     
                       1 
                       
                         V 
                         TRIP 
                       
                     
                     ⁢ 
                     
                       
                         ⅆ 
                         
                           V 
                           TRIP 
                         
                       
                       
                         ⅆ 
                         T 
                       
                     
                   
                   = 
                   
                     
                       
                         R 
                         2 
                       
                       
                         
                           R 
                           3 
                         
                         + 
                         REQ 
                       
                     
                     ⁡ 
                     
                       [ 
                       
                         TCREQ 
                         - 
                         
                           TCR 
                           3 
                         
                       
                       ] 
                     
                   
                 
               
             
           
         
       
     
     For REQ, is must be assumed that V TRIP  is a fixed value, such that R 2  and R 4  can be varied to target a specific temperature coefficient. This can be shown by the following equations: 
                             1   REQ     ⁢       ⅆ   REQ       ⅆ   T         =       [       1     R   2       ⁢       ⅆ     R   2         ⅆ   T         ]     +     [         1     R   4       ⁢       ⅆ     R   4         ⅆ   T         -     ]                           ⁢           R   2         R   2     +     R   4         ⁡     [       1     R   2       ⁢       ⅆ     R   2         ⅆ   T         ]       -         R   4         R   2     +     R   4         ⁡     [       1     R   4       ⁢       ⅆ     R   4         ⅆ   T         ]                           TREQ   =       TCR   2     +     TCR   4     -         R   2         R   2     +     R   4         ⁢     TCR   2       -         R   4         R   2     +     R   4         ⁢     TCR   4                     
The results of equation 5 can be utilized in equation 3 to set the final temperature coefficient of V TRIP .
 
     Referring now to  FIG. 8 , there is illustrated a detailed diagram of the implementation of one-half of the charging structure  410 . This, as with the case with respect to the voltage reference structure  406 , there is provided a P-channel transistor  802  for connecting the top end of the resistor  522  to V DD , with the gate thereof connected to a bias supply. This P-channel transistor introduces very little error in the temperature operation thereof. Capacitor  526  is a variable capacitor, such that the value thereof can be varied to set the period for the oscillator. The capacitor  526  is fabricated from an insulator disposed between the first layer poly, P 1 , and the second layer poly, P 2 , with a layer of oxide disposed there between. The resistor  522  is an N-diffusion resistor. 
     The resistors R 3 , R 2  and R 4  in the voltage reference circuit  406  are variable resistors that can be mask programmable resistors. Resistor R 3  is utilized to set the value of V TRIP  and resistors R 2  and R 4  are utilized to select a temperature coefficient, since they have dissimilar temperature coefficients. 
       FIG. 9  illustrates a layout for one of the resistors R 2 -R 4 . A plurality of series connected resistors is fabricated in either the substrate with an N-type diffusion or in the Poly1 layer. These resistors provide a mask programmable set of connections  904  to allow one or more resistors  902  to be added into the resistor string, they being initially shorted out. Although not shown, there is also provided the ability to short additional ones of the resistors to decrease the value. This is mask programmable and is utilized to “tweak” the design at the metal level. 
     Referring now to  FIG. 10 , there is illustrated a diagrammatic view of the capacitor  526 , which is a register programmable capacitor to allow for adjustment of the center frequency. There is provided a nominal capacitor  1002  which has a value of 380 fF, which is connected between node  24  and V SS . In parallel therewith, there is also provided a mask programmable capacitor  1004  that provides for eight steps of programming in increments of 39.5 fF. The register programmable capacitors are provided with a capacitor  1006  of value “C” that is connected between a node  524  and one side of the source/drain path of an N-channel transistor  1008 , the gate thereof connected to the LSB bit. The configuration of the capacitor  1006  disposed between the switching transistor  1008  and the node  524  is only used for LSB. This structure allows the use of the smaller unit capacitor, but there is some non-linear capacitance that is introduced from the source/drain of the transistor  1008  and, also, the wire bonds. The remaining selectable capacitors are each comprised of a capacitor  1010  which is connected between V SS  and one side of the source/drain path of an N-channel transistor  1012 , the other side thereof connected to node  524  and the gate thereof connected to the bits [ 1 ] through [ 6 ]. The value of the capacitor  1010  associated with bit &lt; 1 &gt;is a value of “C”, with the next selectable capacitor  1010  having the associated transistor gate connected to the bit value &lt; 2 &gt;and the last of the selectable capacitor  1010  having the gate of the associated transistor connected to the bit &lt; 6 &gt;and a value of 32 C. This is a binary tree, with the LSB providing an LSB of approximately C/2. 
     Referring now to  FIG. 11 , there is illustrated a diagrammatic view of the differential input structure for each of the comparators  402  and  404 . There are provided two differential P-channel transistors  1102  and  1104  having one side of the source/drain paths thereof connected to a node  1106 , node  1106  connected through a current source  1108  to V DD . The other side of the source/drain path of transistor  1102  is connected to a node  1110  and the other side of the source/drain path of transistor  1104  is connected to a node  1112 . The gate of transistor  1102  comprises the positive input and the gate of transistor  1104  comprises the negative input connected to V REF . Node  1110  is connected to one side of the source/drain path of an N-channel transistor  1114  and the gate thereof, the other side of the source/drain path of transistor  1114  connected to V SS . Node  1112  is connected to one side of the source/drain path of an N-channel transistor  1116 , the other side thereof connected to V SS  and the gate thereof connected to a node  1118 , node  1118  connected to one side of a resistor  1120 , the other side thereof connected to the gate of transistor  1114 . Node  1112  is also connected to the gate of an N-channel transistor  1122 , the source/drain path thereof connected between node  1118  and V SS . This structure is referred to as a modified Flynn-Lidholm latching comparator which provides a Set/Reset latch with dynamic logic, described in Flynn M. Lidholm S. U., “A 1.2 μm CMOS Current Controlled Oscillator, IEEE Journal of Solid state Circuits,” Vol. 27 No. 7 July 1992. 
     Referring now to  FIG. 12 , there is illustrated a diagrammatic view of the comparator  402  and one-half of the S/R latch  408  illustrating the Q-Bar output. The one-half of the S/R latch  408  has the Set input thereof connected to the output of comparator  402  and input to the gate of an N-channel transistor  1202 , the source/drain path thereof connected between a node  1204  and V SS . A P-channel transistor  1206  has the source/drain path thereof connected between node  1204  and V DD , the gate thereof connected to a node  1208 . Node  1204  is connected to the input of a conventional inverter  1210  and also to one side of the source/drain path of an N-channel transistor  1212 , the other side thereof connected to V DD  and the gate thereof connected to a node  1214 , which node  1214  is also connected to the output of inverter  1210 . Node  1214  is connected to the input of an inverter  1216 , the output thereof providing the Q-Bar output. Node  1214  also is connected through a delay block  1218  to the input of a NAND gate  1220  labeled “ND1.” NAND gate  1220  is comprised of a P-channel transistor  1222  having the source/drain path thereof connected between V SS  and the node  1208  and an N-channel transistor  1224  having the source/drain path thereof connected between the node  1204  and one side of the source/drain path of an N-channel transistor  1226 , the other side thereof connected to V SS . The gates of transistors  1222  and  1224  are connected to the output of the delay block  1218 . The gate of transistor  1226  is connected to the reset input “RST” from the other side of the S/R latch  408 . Node  1208  is connected to the input of an inverter  1230 , the output thereof driving the gate of an N-channel transistor  1232  having the source/drain path thereof connected between the output of the comparator  402 , the SET input of latch  408 , and the other side of the source/drain path of transistor  1232  connected to V SS . The parallel structure to that associated with the output of comparator  402  in  FIG. 12  is provided for the output of comparator  404  for the Reset input. 
     In operation, when the positive input of comparator  402 , FB 1 , charges up, SET starts to go high. As it reaches the threshold voltage V TH  of transistor  1202 , Q-Bar begins to go low and, at the same time, the other side of the latch, which has a NAND gate ND 2  similar to ND 1 , begins to go low and pulls down RST. When RST is pulled down, this then sets the Q-output. Initially, it is assumed that Q-Bar is set to a value of “1” and the Q-output is set to “0” with FB 1  equaling “0” on comparator  402  and FB 2  on the positive input of comparator  404  being initially set to “1” with SET=0 and RST=1. The delay block  1218  prevents ND 1  from pulling down the SET value before RST goes low. RST going low ensures that the pull down input is low (or ND 1  high) to result in a symmetric process for SET/RST. 
     Referring now to  FIG. 13 , there is illustrated a schematic diagram of the delay block  1218 . This delay block is comprised of a plurality of series connected invertors comprised of two series connected transistors, a P-channel transistor  1302  and an N-channel transistor  1304 , with the gates thereof connected together and one side of the source/drain path thereof connected to a node  1306 , transistor  1302  connected between V DD  and V SS . 
     Referring now to  FIG. 14 , there is illustrated a diagrammatic view of a simplified comparator illustrating how supply independence is enhanced. The comparator of  FIG. 14  is illustrated with a current source  1402  disposed between V DD  and a node  1404 , node  1404  connected to one side of two differential connected P-channel transistors  1406  and  1408 . The gate of transistor  1406  is connected to one input, whereas the gate of transistor  1408  is connected to the other V REF  input. The other side of the source/drain path of transistor  1406  is connected to a node  1410 , which is connected to one side of the source/drain path of an N-channel  1412 , the other side thereof connected to ground and the gate thereof connected to both the drain thereof on node  1410  and to the gate of an N-channel transistor  1414 . Transistor  1414  has the source/drain path thereof connected between the other side of transistor  1408  and V SS . Additionally, an offset transistor(s)  1416  of the P-channel type has the source/drain path thereof connected across the source/drain path of transistor  1408 , the gate thereof connected to V REF  and also to the gate of transistor  1408 . Transistor  1416  represents selectable transistors that are mask programmable to select a predetermined offset in the comparator. This offset at the input of the comparators aid in the supply independence. Without offset, the following would be true: 
     With offset:
 
 T   Period =2*(−τ*1 n (1 −V   TRIP   /V   DD )+ T   Delay(comp) )
 
 T   period −2*(−τ*1 n −ratio)+ T   Delay(comp)  
 
 V   TRIP =ratio* V   DD  
 
Without offset:
 
 V   TRIP   =V   TRIP   +V   OS  
 
 T   Period =2*(−τ1 n (1−ratio− V   OS   /V   DD )+ T   Delay(comp) )
 
From these equations, it can be seen that V DD  dependence has been added. Power supply dependence can be added or subtracted by varying the transistors  1416 , noting that there could be variable transistors across transistor  1406  also. This way, the offset can be made negative or positive. Again, this is a mask programmable system.
 
     Referring now to  FIG. 15 , there is illustrated a diagrammatic view of one instantiation of the precision oscillator. In the oscillator implemented on the integrated circuit, a programmable internal clock generator  2402  is provided that is controlled by a register  2406  and a register  2408 . The output of the internal clock generator is input to a divide circuit  2410 , which is also controlled by the register  2408 , the output thereof being input to one input of a multiplexer  2411 . This multiplexer  2411  is controlled by the register  2408 . Multiplexer  2411  outputs the system clock (SYSCLK), which is input to the baud rate generator  302 . In addition to an internal clock generator, there is also a provision for an external crystal controlled oscillator. A crystal controlled internal or on-chip oscillator  2412  is provided that is interfaced through an input circuit  2414  to terminals  2417  and  2418  to an external crystal  2416 . The output of the oscillator  2412  is input to one input of the multiplexer  2411 . Additionally, an external clock is provided on a terminal  2420  that is also input to one input of the multiplexer  2411 . The crystal controlled oscillator  2412  is controlled by a register  2422 . 
     The internal oscillator  2402  is provided such that it will be the default system clock after a system reset. The internal oscillator period can be programmed with the register  2406  by the following equation: 
               Δ   ⁢           ⁢   T     ≅     0.0025   ×     1     f   BASE       ×   Δ   ⁢           ⁢   OSCICL           
wherein f BASE  is a frequency of the internal oscillator followed by a reset, ΔT is the change in internal oscillator, and ΔOSCICL is a change to the value held in the register  2406 . Typically, the register  2406  will be factory calibrated to a defined frequency such as, in one example, 12.0 MHz.
 
     Referring now to  FIG. 16 , there is illustrated a table for register  2406  wherein it can be seen that bits  6 - 0  are associated with the calibration register of the oscillator and its value can be changed internally.  FIG. 17  illustrates the control register  2408  illustrating the controls provided therefore. 
     The use of digitally programmable resistor networks is proposed for the purpose of increasing the frequency stability of oscillators, in particular with respect to temperature drift and supply voltage variation, so that these oscillators may approach the frequency stability of crystals. In this way, the entire oscillator assembly may be integrated on-chip. The proposed programmable resistor networks are constructed in special topologies from integrated resistors of differing materials and from integrated transistors used as switches. Associated digital logic is also included to control the special switching sequence that is required. These programmable resistor arrays are used as one means to increase the frequency stability of a fully-integrated free-running oscillator beyond what is required simply for UART operation, and to instead achieve a much more precise frequency stability of ±0.5% in order to meet stricter CAN (Control Area Network) specifications—in the presence of variations in temperature from −40 C to 125 C, variations in supply voltage from 1.8V to 3.6V, and variations in component manufacturing of various types. 
     Referring now to  FIG. 18 , there is provided a further illustration of the precision oscillator  236  with an alternative and improved embodiment of the voltage reference circuit  406 . As before, there are two bottom resistors  1804  and  1805  designated R 2  and R 4  respectively, making up two independent arrays. In this implementation, however, there are also two top resistors in parallel, as opposed to just one, forming what will be considered a single resistor array  1802  designated R 3 =R 2 prime∥R 4 prime. R 2 prime is chosen to be the same material as R 2 , and R 4 prime is chosen to be the same material as R 4 . Also, R 2 prime and R 4 prime are chosen to be a factor of K times the value of R 2  and R 4  respectively on their nominal programmed settings, i.e. R 2 prime=K*R 2  and R 4 prime=K*R 4 , where the value of K is the same in both equations. As a result of these choices, process variations in R 2 prime∥R 4 prime will track and approximately cancel process variations in R 2 ∥R 4 , and thus the overall process variation of the voltage reference temperature coefficient is significantly reduced compared to the case where the top resistor consists of only a single resistive material. Also, in this implementation, each of the three resistor arrays R 3 =R 2 prime∥R 4 prime, R 2 , R 4 , is made digitally programmable in its resistance value. 
     As before, the voltage reference circuit  406  is connected to the negative inputs of comparators  402  and  404 . The outputs of comparators  402  and  404  are connected to the S and R inputs of an SR latch  408 . The Q and Q-Bar outputs of the SR latch  408  are connected to the RC timing block circuit  410 . The RC timing block circuit  410  consists of the transistors  802 ,  802 ′, resistor  522 ,  522 ′, variable capacitor  526 ,  526 ′ and transistor  528 ,  528 ′ as was described previously with respect to  FIG. 8 . 
     The digitally programmable resistor arrays, consisting of resistors R 3 =R 2 prime∥R 4 prime, R 2 , and R 4 , comprising the digitally programmable resistor divider network are configured to minimize the effects of end resistance, switch resistance, and sub-threshold leakage currents of switches on the overall temperature coefficient generated by the resistor divider network. These three effects add significant process variation and non linearity to what would otherwise be a very linear and well-controlled temperature coefficient of the resistor divider network, as well as making this temperature coefficient larger in value than it would otherwise be. Process variation and non linearity of the resistor voltage divider temperature coefficient directly translate into process variation and non linearity of the overall oscillator temperature coefficient. The overall accuracy of this particular implementation of the precision oscillator must go beyond what is required simply for UART operation, and instead achieve a much more precise frequency stability of +/−0.5 percent from −40 C to 125 C, in order to meet stricter CAN (Control Area Network) specifications. Since it is very expensive to trim the temperature coefficient of each part individually—because this requires heating and/or cooling the part in an accurate temperature-controlled environment—this +/−0.5% accuracy budget must also include the part-to-part variation of the overall oscillator temperature coefficient. 
     Switches connected to resistors must be implemented as MOS devices in the triode region of operation, which have high, nonlinear, poorly-controlled temperature coefficients that degrade the otherwise low, linear, well-controlled temperature coefficients of the programmable resistor array—making it difficult to compensate for the temperature coefficient of the overall oscillator in a PTAT/CTAT fashion. In order to control this, the topology of the resistor network is designed so that the ratio of total pure resistance to total end/switch resistance on any particular programmable setting is always kept large enough that the temperature coefficient contribution from the total end/switch is negligible in the weighted sum. The weighted-sum equation for a resistor temperature coefficient is given by:
 
 TCres=[ 2* R end/( R pure+2* R end)]* TC end+[ R pure/( R pure+2* R end)]* TC pure,
 
where the weighting is the respective fraction that end resistance and pure resistance contribute to the overall series combination. The factor of 2 occurs in the equation, because there is 1 parasitic end resistance on each side of the pure resistance, making a total of 2 end resistances per 1 pure resistance, for each resistor.
 
     For P+ non-silicided poly resistors in a typical 0.18 μm process, such as those used in the programmable R 4  array, pure resistances have tempcos of −75 ppm/C, while end resistances have tempcos of −1692 ppm/C. In this case, the pure resistance tempco is much smaller than the end resistance tempco, so end resistances have a major impact on the overall temperature coefficient of the P+ resistors used in the R 4  array. Moreover, the value of these end resistors can vary by as much as +/−50% from one chip to another, causing the overall temperature coefficients of the P+ poly resistors to vary significantly, as predicted by the previous weighted-sum equation. For this reason, all P+ poly resistors are implemented in parallel within the programmable R 4  resistor array, so that only one resistor in the parallel combination is connected for a given setting, while all other parallel resistors are disconnected from the array, as will be explained. In this way, the R 4  resistor array has only two end resistances and one pure resistance contributing to the overall resistance on any particular programmable setting. If each of the P+ poly resistors in the array are then made long enough and wide enough in the design, such that the value of the pure resistance is made orders of magnitude greater than the value of the two end resistances, then the overall resistor temperature coefficient will be very close to the well-controlled value of −75 ppm/C, as desired. 
     For N+ non-silicided poly resistors in a typical 0.18 μm process, such as those used in the programmable R 2  array, pure resistances have tempcos of −1184 ppm/C, while end resistances have tempcos of −1372 ppm/C. In this case, the pure resistance tempco is much closer in value to the end resistance tempco, so the end resistances have a less significant impact on the overall temperature coefficient of the N+ poly resistors in R 2  than they did in the case of the P+ poly resistors in R 4 . Although the +/−50% variation of the end resistor values still presents a problem, it is also to a lesser degree in this case, as again predicted by the weighted-sum equation. As a consequence of these facts, the N+ poly resistors do not need to be implemented in parallel, but can instead be implemented in series, where a certain number of N+ poly resistors are added and subtracted from the total series sum for any given setting. This approach saves area compared to the parallel approach and is therefore preferred when end and pure resistor values are relatively close in value. The parallel approach is preferred when extremely low and well-controlled resistor tempcos need be achieved at the expense of area, as in the case of the R 2  array. 
     Referring now to  FIGS. 19   a  and  19   b , there are illustrated a schematic diagram of the programmable resistor array making up the variable resistor R 2  illustrated in  FIG. 18 . This programmable resistor array consists of a plurality of resistors  1902 , implemented in this case with N+ non-silicided polysilicon material, which are connected in series between a first node  1904  and a second node  1906 . Note that other resistive materials may also be used to implement these resistors, depending on the details of the particular fabrication process. Each transistor  1908  acts as a switch to disconnect its associated resistor  1902  from the array, having its drain node attached to the top of each resistor  1902  and its source node attached to special circuitry which limits the sub-threshold leakage of the switch when it is turned off, as will be explained. When each transistor  1908  is turned on, the top node of the associated resistor  1902  is shorted to the bottom node  1906  of the series resistor array through the leakage funnel circuitry  1910 , effectively shorting out the associated resistor and all resistors succeeding it in the series array so that they do not contribute to the total series resistance. When each transistor  1908  is turned off, the associated resistor node is left free, so that the resistor  1902  can contribute to the overall series resistance of the variable resistor array, assuming all transistors preceding it in the array are also switched off. In this off state, the sub-threshold leakage of the switch  1908  is significantly reduced by the aforementioned special leakage funnel circuitry  1910 . Note that the bulk node of each transistor within the programmable resistor array is connected to ground. 
     The following describes the sequence of turning on/off switches in the R 2  array so as to program it to a particular resistance value. Assuming all switches are turned on to begin with, node  1904  is shorted to node  1906  through all of the switches and leakage circuitry, resulting in a resistance of zero. Next, the transistor switch closest to node  1904  is turned off. The top-most resistor in the series array, and only this particular resistor, is now connected between node  1904  and node  1906 . Next this switch remains off, and the switch directly succeeding this switch in the array is turned off. The top-most resistor and the resistor directly succeeding it are now both connected in series between node  1904  and node  1906 . Continuing this process, each time the next switch in sequence is turned off, an additional resistance is added to the series sum, until finally all resistors in the array are connected in series when all switches are turned off. Note that, at bare minimum for this scheme to work, only one switch really needs to be turned on for any given resistance setting, since it effectively shorts out all the switches succeeding it in sequence whether they are on or off. However, having all successive switches on in sequence, as described, results in a lower effective parasitic switch resistance to node  1906 , and therefore less degrading effect from the high, nonlinear, and poorly-controlled switch resistance on the very low, linear, and well-controlled temperature coefficient of the series polysilicon resistors. 
     The “leakage funnel”  1910  consists, in one particular implementation, of three transistors  1914 ,  1916 ,  1918  forming the top branch of a tree, and a fourth transistor  1920  forming the root branch of the tree. The top-branch transistors  1914 ,  1916 ,  1918  have their drain/source path connected between associated groupings of transistor switches attached to the resistor array, hereafter referred to as leaves, and an intermediate node  1912  inside the tree. The root transistor  1920  has its drain/source path connected between intermediate node  1912  and the bottom node  1906  of the series resistor array. One skilled in the art would appreciate that the leakage funnel may include more or less than 2 levels of branches, with any number of transistors on the various branch levels and any number of switches acting as leaves attached to the resistor array, so long as a tree topology is formed that funnels leakage from a larger number of leaf transistors on the top-most level to a smaller number of root transistors on the bottom-most level. 
     A first transistor  1914  of the top branch of the leakage funnel  1910  has its drain connected to the source of each of the leaf transistors  1908   a  within a first portion of the resistor array. A second transistor  1916  of the top branch of the funnel has its drain connected to the source of each of the leaf transistors  1908   b  within a second portion of the resistor array. And a third transistor  1918  of the top branch of the funnel has its drain connected to each of the sources of the leaf transistors  1908   c  within a third portion of the resistor array. 
     The previous paragraph described a leakage funnel that was implemented in an explicit fashion with branch transistors separate from the leaves of the resistor array. A leakage funnel can also be implemented in an implicit fashion within the array itself by generating the branches from leaves that will later be turned off in the previously described switching sequence. Such an implicit leakage funnel is implemented with transistor groupings  1908   d  and  1908   e  within a fourth and fifth portion of the resistor array. Leaf transistors  1908   d  have their sources connected to the drain node of leaf transistor  1908   f  within the array. When leaf transistor  1908   f  is turned off in the switching sequence, it acts as the root branch of a tree with leaves consisting of the three transistors  1908   d  which were turned off previously. As transistors succeeding  1908   f  are subsequently turned off in sequence, extra branch levels are added to this tree, with a single transistor being added per new branch level. At the end of the sequence, when every switch in the array is ultimately turned off, transistor  1908   g  becomes the final root of the tree. 
     Implicit leakage funnels can be profitably implemented at the end of the resistor array when the overall series poly resistance becomes very large, in which case the extra switch resistance introduced by the large number of extra branch levels can be tolerated with negligible effect on the very low, linear, and well-controlled temperature coefficient of the series poly resistance. Adding extra switch resistance towards the beginning of the array is problematic, because the total series resistance is very small and therefore easily affected by the high, nonlinear, and poorly controlled temperature coefficient of the switches. The advantage of implicit leakage trees is that they tend to do a better job of reducing leakage than explicit trees, as well as saving area and reducing the complexity of the required control logic. For these reasons, explicit leakage funnels are used at the beginning of the R 2  array, and implicit leakage funnels are used at the end of the R 2  array. 
     The control signals applied to the gates of the transistors within the R 2  resistor array are provided in a manner such that the leakage currents of the transistors are minimized via the leakage funnels, and thus the impact on the temperature coefficient of the programmable resistor array is minimized. The transistors forming the switches in the digitally programmable resistor array illustrated in  FIGS. 19   a  and 19 b  must be large enough (i.e. must be sized with big enough W/L) to keep their on-resistance relatively small, such that on any given setting, the on-resistance contributes negligibly compared to the pure part of the resistor. This on-resistance has a high nonlinear temperature coefficient, and varies greatly in value due to manufacturing. In modern submicron processes (e.g. a 0.18 μm process), when the transistors are turned off, they still draw a significant current since the sub-threshold leakage of the transistor is so large. Unfortunately, making the size of the transistor bigger to reduce on-resistance also has the adverse effect of increasing this leakage current. In a typical 0.18 um process, given a choice of W/L=20 um/0.18 um for each switch, which is the required W/L to keep on-resistance sufficiently low, we are forced to endure sub-threshold leakage currents on the order of a few nano-amps per switch at 85 C. 
     The uncompensated temperature coefficient of the oscillator is roughly −70 ppm/C, which requires a PTAT temperature coefficient from a programmable resistor array of approximately +70 ppm/C to cancel out. To keep the overall power consumption of the oscillator low, the bias current within the programmable resistor array is on the order of a few 10&#39;s of micro-amps. With such a small bias current, leakage on the order of a few nano-amps per switch, times ˜30 switches, will significantly perturb such a low temperature coefficient as +70 ppm/C. Additionally, these subthreshold leakage currents exhibit an exponential dependence on temperature and threshold voltage, adding significant non-linearity and process variation to the programmable resistor array&#39;s temperature coefficient. 
     The number of switches that are turned off at any particular time is controlled such that once a grouping of transistor switches has been turned off, one of the transistor switches associated with this grouping within the transistor funnel  1910  is also turned off. As a result, only the leakage current of a single transistor is affecting the temperature coefficient of the circuit for that particular grouping of switches, rather than the leakage current of every single transistor in the group. 
     This process is more fully illustrated in  FIG. 20 . Digital logic, implemented in Verilog code, controls the switching of the transistors in the trees and properly adjusts the funneling for different settings. The process begins at step  2002  wherein all of the switches are turned on and the programmable resistor array provides a resistance of zero. The first switch, closest to node  1904 , is turned off at step  2004 . Once this first switch has been turned off, a particular resistance associated with this first switch is provided by the programmable resistor array, and control passes to inquiry step  2010  where a determination is made if all switches within a particular group (i.e. a particular grouping of transistors connected to the same transistor of the funnel) are turned off. Thus, for example, a determination is made if all of the switches  1908   a  and/or all of the switches  1908   b  and/or all of the switches  1908   c  have been turned off. If inquiry step  2010  determines that no groups have all their transistors turned off, control passes to inquiry step  2006 . Inquiry step  2006  determines if the programmable resistor array is providing the desired resistance. If so, the process is completed at step  2008 . Otherwise, if the desired resistance is not yet high enough, the next switch (directly succeeding the previous switch) is turned off at step  2012  and control passes back to step  2010 . 
     If inquiry step  2010  determines that all of a particular group of switches have been turned off, then the associated funnel switch is turned off at step  2014 . Thus, for example, if all of the switches  1908   a  had been turned off, then switch  1914  would be turned off within the transistor funnel  1910 . This has the effect of having the leakage current associated with switch  1914  being the only leakage current affecting the temperature coefficient of the programmable resistor array for the particular grouping of transistors  1908   a , rather than having the cumulative effect of the leakage current of all of the switches in  1908   a  affecting the temperature coefficient. The process is similar for the switches  1908   b  associated with switch  1916  and the switches  1908   c  associated with switch  1918 . Inquiry step  2016  determines if all three of the funnel transistor switches  1914 ,  1916  and  1918  have been turned off. If not, control passes back to step  2006  to determine if the desired resistance has been achieved. However, if inquiry step  2016  determines that each of the funnel switches  1914  through  1918  have been turned off, then the main funnel switch  1920  is also turned off at step  2018 . This causes the leakage current provided by the entire group of switches consisting of transistors  1908   a ,  1908   b  and  1908   c  to have the effect of only the single transistor  1920 , rather than the cumulative effects of all of the transistors  1908   a ,  1908   b  and  1908   c . Control is then finally returned to inquiry step  2006  to determine if the desired resistance has been achieved. Note that no special control logic is required for the operation of the implicit leakage funnel implemented with transistors  1908   d  and  1908   f . So long as the proper switching sequence in  FIG. 20  is followed, the root branch transistors in  1908   f  take care of shutting themselves off properly on relevant settings. 
     The above described funneling approach works well in cases where larger leakages on the order of a few nano-amps may be tolerated, but the area of the programmable resistor array needs to be conserved. Larger leakages may be tolerated in the case of the N+ poly R 2  array because the tempco is a fairly large value of −1184 ppm/C. However, in the case of the P+ poly R 4  network, leakage must be kept on the order of pico-amps or less, because the tempco is a very small −75 ppm/C. A second scheme will now be explained that achieves femto-amp sub-threshold leakage in a typical 0.18 um process, and that works extremely well in the case of the R 4  array. The only drawback to this scheme is that it requires more area to implement. 
       FIGS. 21   a  and  21   b , depict the programmable resistor array forming the resistor R 4 . The programmable resistor array illustrated in  FIGS. 21   a  and  21   b  includes a plurality of P+ non-silicided polysilicon resistors  2102  all in parallel with one another. Note that other resistive materials may also be used to implement these resistors, depending on the details of the particular fabrication process. For any given setting, control logic ensures that only one resistor is switched in and that the remaining resistors are all switched out. The switching is accomplished using the circuitry included inside box  2200 , as will be described momentarily. Having one resistor switched in and 29 resistors switched out, on any given setting, creates a great deal of sub-threshold leakage current through the 29 switches that are off, assuming that the circuitry inside box  2200  were to be implemented with a single transistor switch. As already mentioned, for a 20 um/0.18 um regular VT transistor, this sub-threshold leakage is a few nano-amps per switch at 85 C in a typical 0.18 um process. Accounting for all 29 transistors that are off, total leakage current of around 100 nano-amps would be expected, which would significantly affect the required low +70 ppm/C temperature coefficient of the voltage reference, given that the bias current in the resistor divider is only 10&#39;s of micro-amps. 
     To solve this problem, a new circuit termed a “low-leakage switch” is proposed as a one-to-one replacement for the leaky single transistor switches which would otherwise have to be used to switch in and out the parallel P+ poly resistors in  FIGS. 21   a  and  21   b . This new low-leakage switch is illustrated in  FIG. 22 . A top node  2202  is connected to the drain of transistor  2204  and to the P+ resistor associated with the low leakage switch  2200 . The transistor  2204  has its drain/source path connected between node  2202  and node  2206 . A pair of transistors  2208  and  2210  is connected in series between the gate and source of transistor  2204  to create a negative gate-to-source voltage when transistor  2204  is turned off, and thereby reduce the sub-threshold leakage current. The source/drain path of transistor  2208  is connected between V DD  and node  2206 . The drain/source path of transistor  2210  is connected between node  2206  and node  2212 . The bulk of transistors  2204  and  2210  are connected to ground, and the bulk of transistor  2208  is connected to its drain. The gates of transistors  2204 ,  2208  and  2210  are connected to the output of NOR gate  2214 . NOR gate  2114  receives an input signal SWITCH and an input signal PDN. The low leakage switches operate by pulling the source of transistor  2204  above its gate by a few hundred milli-volts when either of the two input signals SWITCH or PDN goes high. This results in a negative gate-to-source voltage (VGS) for switch  2204 , which reduces the current leakage of  2204  from nano-amps to femto-amps in a typical 0.18 um process. 
       FIGS. 21   a  and  21   b , depict the programmable resistor array, including the low leakage switch  2200  described in  FIG. 22 . In this case, a parallel connection of a plurality of resistors  2102  has a first end connected to a top node  2304  of the programmable resistor array. The second end of resistors  2102  are each connected to node  2102  of a low leakage switch  2200  as illustrated in  FIG. 22 . The node  2212  of low leakage switch  2200  is the output of the programmable resistor array. The low leakage switch approach works well in cases where leakage needs to be extremely small, but larger areas may be tolerated for the bigger low leakage switches. The “leakage funnel” scheme described in the context of the programmable R 2  array and the “low leakage switch” scheme described above in the context of the programmable R 4  array both operate together to eliminate the disastrous effects of leakage current on the temperature coefficient of the voltage reference network, and therefore on the temperature coefficient of the overall oscillator. 
     Referring now to  FIG. 23 , there is illustrated the programmable resistor array used to provide the variable resistor  1802  designated R 3 =R 2 prime∥R 4 prime in the voltage reference circuit of  FIG. 18 . As already explained, it has been determined that using a parallel combination of R 2 prime∥R 4 prime resistors—where R 2 prime is the same material as R 2 , where R 4 prime is the same material as R 4 , and where R 2 prime=K*R 2  and R 4 prime=K*R 4  with K being the same factor for both equations, provides a situation wherein the process variations of the top resistor array R 2 prime∥R 4 prime and bottom resistor arrays R 2 ∥R 4  tend to cancel each other out. The top resistors R 3 =R 2 prime∥R 4 prime are made digitally programmable to allow coarse tuning of the programmable voltage reference temperature coefficient, while the bottom resistors R 2  and R 4  are also each made separately digitally programmable to allow a fine tuning of the programmable voltage reference temperature coefficient. The coarse tuning is implemented in such a way as to triple the tuning range of the programmable resistor array beyond what could have been achieved via the fine tuning alone, while adding very little additional area. 
     The resistors  2302  comprise P+ poly resistors similar to the P+ poly resistors utilized in the programmable resistor array for variable resistor R 4 . The resistors  2302  are connected in parallel with each other between a first node  2304  and second nodes  2306   a ,  2306   b  and  2306   c,  respectively. The second nodes  2306   a ,  2306   b  and  2306   c  are connected to the drains of a set of transistors  2308   a ,  2308   b  and  2308   c , respectively. The transistors  2308   a ,  2308   b  and  2308   c  have their drain/source path connected between nodes  2308   a ,  2308   b  and  2308   c , respectively, and node  2310 . The bulks of transistors  2308  are connected to ground. The gates of transistors  2308  are connected in such a way as to receive control bits from NOR gate  2312 . 
     In parallel with the P+ poly resistors  2308  are N+ poly resistors  2330 . The N+ poly resistors  2330  are in series with each other. A first transistor switch  2332  is used to turn on resistor  2330   a . Resistor  2330   a  is connected between node  2334  and node  2336 . Transistor  2332  has its source/drain path connected between node  2334  and node  2336 . The bulk of transistor  2332  is connected to VDD and the gate of transistor  2332  is connected so as to receive a control signal from NAND gate  2338 . Resistor  2330   b  is connected between node  2336  and node  2340 . Transistor  2342  is in series with resistor  2330   b  and has its drain/source path between node  2340  and node  2310 . The bulk of transistor  2342  is connected to ground, and the gate of transistor  2342  is connected to a control signal from NOR gate  2312 . Transistor  2344  has its drain/source path connected between node  2334  and node  2310 . The bulk of transistor  2344  is connected to ground, and the gate of transistor  2344  is connected to receive a control signal from NAND gate  2312 . On any one of the three possible coarse tune settings, a P+ poly resistance is switched in on the left side and an N+ poly resistance is switched in on the right side. 
     By applying the desired control signals to the transistors of the R 3  programmable resistor array, the R 3  value is coarse-tuned such that the R 4 prime P+and R 2 prime N+ top resistors are set to one of three possible K-factor multiples of the corresponding R 4  P+ and R 2  N+ bottom resistors. In this way, the process variations of the top and bottom resistors tend to cancel each other out, regardless of the coarse tune setting. 
     Although the preferred embodiment has been described in detail, it should be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims. 
     Referring now to  FIGS. 24   a  and  24   b , there are illustrated a schematic diagram of an additional embodiment of the SR latch  408 . As described previously with respect to the SR latch  408 , the inputs to the SR latch  408  comprise the SET input at node  2402  and the RESET input at node  2404 . The comparator  402  is connected to node  2402 , and the comparator  404  is connected to node  2404 . A transistor  2406  has its drain/source path connected between node  2402  and ground. The bulk of transistor  2406  is connected to the source, and the gate of the transistor  2406  is connected to receive an input signal pdn. A transistor  2408  has its gate connected to node  2402 . Transistor  2408  has its drain/source path connected between node  2410  and ground. The bulk of transistor  2408  is connected to its source. Transistor  2412  has its source/drain path connected between VDD and node  2410 . The gate of transistor  2412  is connected to node  2414  designated PDSET_bar. 
     Transistor  2420  has its drain/source path connected between node  2402  and ground. The bulk of transistor  2420  is connected to its source. The gate of transistor  2420  is connected to node  2422  designated PDSET. Transistor  2424  also has its gate connected to node  2422 . The source/drain path of transistor  2424  is connected between VDD and node  2414 . The bulk of transistor  2424  is connected to its source. A series connection of transistors  2426  and  2428  are connected between VDD and ground. Transistor  2426  has its source/drain path connected between VDD and node  2422 . Transistor  2428  has its drain/source path connected between node  2422  and ground. The bulk of transistor  2428  is connected to its source. The gates of transistors  2426  and  2428  are connected to node  2414 . A transistor  2430  has its source/drain path connected between VDD and node  2414 . Transistor  2432  has its source/drain path connected between VDD and node  2414 . The bulk of transistor  2432  is connected to its source. The gate of transistor  2432  is connected to node  2434 . Transistor  2436  is in series with transistor  2432  and has its drain/source path connected between node  2414  and node  2438 . The bulk of transistor  2436  is connected to ground and the gate of transistor  2436  is connected to node  2434 . Transistor  2440  is also in series with transistor  2436  and has its drain/source path connected between node  2438  and ground. The bulk of transistor  2440  is also connected to ground and its gate is connected to node  2442 . 
     A delay box  2444  is connected between node  2434  and  2446 . Transistors  2450  and  2452  have their drains connected to node  2446 . The source/drain path of transistor  2450  is connected between VDD and node  2446 . The drain/source of path transistor  2452  is connected between node  2446  and ground. The gates of transistors  2450  and  2452  are connected to node  2454 . Transistor  2458  has its source/drain path connected between VDD and node  2460 . Connected in series with transistor  2458  is transistor  2462  having its source/drain path connected between node  2460  and node  2454 . The gate of transistor  2462  is connected to ground. The bulk of transistors  2462  and  2458  are connected to VDD. A transistor  2464  has its source/drain path connected between VDD and node  2454 . The bulk of transistor  2464  is connected to VDD and the gate of transistor  2464  is connected to receive input pdnb. Node  2446  is connected to the gates of a series connection of transistors  2466  and  2468 . Transistor  2466  has its source/drain path connected between ground and node  2470 . Transistor  2468  has its drain/source path connected between node  2470  and node  2472 . A transistor  2474  has its drain/source path connected between node  2472  and ground. A transistor  2476  has its drain/source path connected between node  2470  and VDD. Node  2470  comprises the output of the SR latch Q Bar. 
     The remainder of the latch circuit  408  is the same configuration as that just described for the reset input  2404  and Q output  2488 . A transistor  2480  has its drain/source path connected between node  2404  and Vdd. The bulk of transistor  2480  is connected to the source, and the gate of the transistor  2480  is connected to receive an input signal pdnb. A transistor  2408 ′ has its gate connected to node  2404 . Transistor  2408 ′ has its drain/source path connected between node  2410 ′ and ground. The bulk of transistor  2408 ′ is connected to its source. Transistor  2412 ′ has its source/drain path connected between VDD and node  2410 ′. The gate of transistor  2412 ′ is connected to node  2414 ′ designated PDRST_bar. 
     Transistor  2420 ′ has its drain/source path connected between node  2404  and ground. The bulk of transistor  2420 ′ is connected to its source. The gate of transistor  2420 ′ is connected to node  2422 ′ designated PDRST. Transistor  2424 ′ also has its gate connected to node  2422 ′. The source/drain path of transistor  2424 ′ is connected between VDD and node  2414 ′. The bulk of transistor  2424 ′ is connected to its source. A series connection of transistors  2426 ′ and  2428 ′ are connected between VDD and ground. Transistor  2426 ′ has its source/drain path connected between VDD and node  2422 ′. Transistor  2428 ′ has its drain/source path connected between node  2422 ′ and ground. The bulk of transistor  2428 ′ is connected to its source. The gates of transistors  2426 ′ and  2428 ′ are connected to node  2414 ′. A transistor  2430 ′ has its source/drain path connected between VDD and node  2414 ′. Transistor  2432 ′ has its source/drain path connected between VDD and node  2414 ′. The bulk of transistor  2432 ′ is connected to its source. The gate of transistor  2432 ′ is connected to node  2434 ′. Transistor  2436 ′ is in series with transistor  2432 ′ and has its drain/source path connected between node  2414 ′ and node  2438 ′. The bulk of transistor  2436 ′ is connected to ground and the gate of transistor  2436 ′ is connected to node  2434 ′. Transistor  2440 ′ is also in series with transistor  2436 ′ and has its drain/source path connected between node  2438 ′ and ground. The bulk of transistor  2440 ′ is also connected to ground and its gate is connected to node  2442 ′. 
     A delay box  2444 ′ is connected between node  2434 ′ and  2446 ′. Transistors  2450 ′ and  2452 ′ have their drains connected to node  2446 ′. The source/drain path of transistor  2450 ′ is connected between VDD and node  2446 ′. The drain/source of path transistor  2452 ′ is connected between node  2446 ′ and ground. The gates of transistors  2450 ′ and  2452 ′ are connected to node  2454 ′. A capacitor  2456 ′ is connected between node  2454 ′ and ground. Transistor  2458 ′ has its source/drain path connected between VDD and node  2460 ′. Connected in series with transistor  2458 ′ is transistor  2462 ′ having its source/drain path connected between node  2460 ′ and node  2454 ′. The gate of transistor  2462 ′ is connected to ground. The bulk of transistors  2462 ′ and  2458 ′ are connected to VDD. A transistor  2482  has its source/drain path connected between node  2454 ′ and ground. The bulk of transistor  2482  is connected to ground and the gate of transistor  2482  is connected to receive input pdn. Node  2446 ′ is connected to the gates of a series connection of transistors  2490  and  2486 . Transistor  2490  has its source/drain path connected between node  2488  and node  2491 . Transistor  2486  has its drain/source path connected between node  2488  and Vdd. A transistor  2492  has its drain/source path connected between node  2491  and ground. A transistor  2484  has its drain/source path connected between node  2488  and VDD. Node  2488  comprises the output of the SR latch Q. 
     By connecting the gates of transistors  2440  and  2440 ′ to nodes  2446  and  2446 ′ respectively, the operating speed of the SR latch is greatly increased. In prior art SR latch configurations, the gates of transistors  2440  and  2440 ′ were connected to the set node  2402  and reset node  2404 , respectively. Connection of the gates of transistors  2440  and  2440 ′ to IQ and IQ Bar improves operation of the comparators  402  and  404  because this configuration cuts down on the load capacitance that the comparators must drive. IQ and IQ Bar are actually delayed versions of the SET and RESET signals. In order to account for the extra delay from SET to IQ and from RESET to IQ Bar, the delay boxes  2444  and  2444 ′ should be designed such that their delays are increased by at least a factor of 2. Only the delay through the nodes SET, SET-Bar, IQ and Q Bar on the left side and RESET, RESET-Bar, IQ Bar, Q on the right side actually enter into the period of an oscillation. This comprises a hidden form of memory bypass in the latch architecture. Thus, making the delay box longer has no adverse effect on the temperature coefficient of the oscillator, since it has no affect whatsoever on the frequency of oscillation. 
     By connecting an additional NMOS foot transistor to the transistor  2408  such that the source of  2408  connects to the drain of the foot transistor and the source of the foot transistor connects to ground, transistor  2408  may be turned on and off by the appropriate control signal to the gate of the foot transistor. Additional copies of this assembly of transistor  2408  and associated foot transistor may then be added in parallel such that all copies connect at node  2410  and node  2402  but are free from one another at all other nodes. By turning off different numbers of the copies via their respective foot switches, the curvature of the oscillator temperature coefficient can be digitally programmed. This is a mechanism by which curvature correction can be added to the oscillator. 
     Referring now to  FIG. 25 , there is a provided a schematic diagram of an alternative embodiment of the comparator circuits  402 ,  404 . The inputs to the comparator circuit are provided at the input node  2502  and the Vref node  2504 . The input node  2502  is connected to the gate of a transistor  2506 . Transistor  2506  has its source/drain path connected between node  2508  and node  2510 . A transistor  2512  has its source/drain path connected between node  2508  and node  2514 . The gate of transistor  2512  is connected to the reference voltage input node  2504 . Node  2514  also comprises the output node of the comparators  402 ,  404 . A series connection of transistors  2516  and  2518  are connected between VDD and node  2508 . Transistor  2516  has its source/drain path connected between VDD and node  2520 . Transistor  2518  has its source/drain path connected between node  2520  and node  2508 . The gates of transistors  2516  and  2518  are connected to receive signals ibias 1  and ibias 2 , respectively. Transistor  2522  has its drain/source path connected between node  2510  and node  2524 . The bulk of transistor  2522  is connected to ground. The gate of transistor  2522  is connected to node  2526 . Transistor  2528  has its gate connected to receive input signal pdn. The drain/source path of transistor  2528  is connected between node  2510  and ground. Transistor  2530  has its gate connected to node  2526 . The drain/source path of transistor  2530  is connected between node  2514  and node  2532 . The output node  2514  is also connected to the gate of transistor  2534 . Transistor  2534  has its drain/source path connected between node  2526  and node  2536 . Transistor  2538  is connected in series with transistor  2534  and has its drain/source path connected between node  2536  and ground. The gate of transistor  2538  is connected to receive signal latchb. 
     Circuit  2540  connected to nodes  2524  and  2532  enables the offset voltage of the comparator  408  to be digitally program responsive to a six bit input signal applied to the gates of transistors  2542  through  2552 . The circuit  2540  consists of a parallel combination of transistors  2542 ,  2544  and  2546 , connected between node  2524  and ground, and a second parallel combination of transistors  2548 ,  2550  and  2552 , connected between node  2532  and ground. The bulk of each of these transistors is connected to ground. The circuit  2540  provides programmable source degeneration to the current mirror, consisting of transistors  2522  and  2530 , of the comparator. All of the transistors in  2540  operate in the triode region, and as such act as resistors. The sizing of transistors  2542 - 2552  is chosen such that the resistances on each side of the mirror are weighted in a binary fashion. By changing the ratio of degeneration resistance between the left and right sides of the mirror via the act of turning some transistors in  2542 - 2552  on and others off, the current gain of the mirror is altered from 1:1 to some other ratio. Hence the offset voltage of the comparator is adjusted, either positively or negatively, around a nominal value of zero when the resistances on both sides are equal. 
     The operation of the source degeneration circuit  2540  is more fully illustrated in the flow diagram of  FIG. 26 . The process is initiated at step  2602  and a determination is made if a positive or negative voltage offset is needed by the comparator at step  2604 . If a positive voltage offset is to be applied to the comparator, the source degeneration resistance is increased on one side of the current mirror at step  2606  by turning off the associated transistors. The source degeneration resistance is decreased on the opposite side of the current mirror at step  2608  by turning on the associated transistors. The process is completed when the desired offset voltage is achieved at step  2609 . The increase and decrease of the source degeneration resistance on opposite sides of the current mirror is achieved by turning off some of the triode transistors to increase source degeneration resistance or turning on some of the triode transistors to decrease source degeneration resistance. By source degenerating one side more than the other, the transfer ratio of the current mirror comprised of transistors  2522  and  2530  is changed, and thus the voltage offset of the comparator is changed. If inquiry step  2604  determines that a negative offset voltage is to be applied, the source degeneration is decreased on the first side of the current mirror at step  2610  and increased on the opposite side at step  2612 . This is of course, the opposite of the process performed for a positive offset voltage increase. The process is completed at step  2609 . 
     Referring now to  FIG. 27 , it can be seen how the voltage offset  2702  introduced by the source degeneration circuit  2540  is provided responsive to a six bit input signal. The first three bits  2704  control the transistors  2548  through  2552  on a first side of the current mirror comprised of transistors  2522  and  2530 . A bit in a logical high state “1” turns on the associated transistor, and a bit in a logical low state “0” turns off the associated transistor. The second three bits  2706 , control transistors  2542  through  2546  on a second side of the current mirror. These bits turn on and off the associated transistors in a similar fashion. While the present description has been with respect to a source degeneration circuit  2540  controlled by a six bit input signal, it should, of course, be realized that any number of fewer or greater transistors may be used for the source degeneration circuit  2540  to achieve a desired voltage offset. 
     Referring now back to  FIG. 25 , the latching transistor  2534  which latches the output node  2514  of the SR latch  408  to a desired state may be used to compensate for small non-linearities within the temperature coefficient of the RC network  410  of the oscillator circuit. In the embodiment illustrated in  FIG. 25 , this feature is controlled by an on/off switch consisting of transistor  2538  responsive to the control signal “latchb.” The temperature variation of the RC network  410  in the oscillator has a small curvature associated with it, as illustrated at  2802  in  FIG. 28 . This curvature cannot be fully compensated for in a PTAT/CTAT fashion by the programmable resistor arrays described herein in the earlier sections on the voltage reference network. By introducing a temperature coefficient with an appropriate curvature in the opposite direction within the comparators, the overall uncompensated temperature coefficient of the oscillator can be made more linear, and therefore more compensatable by the programmable resistor arrays described earlier. This is implemented by intentionally oversizing the latching transistor  2534  inside the comparator so that it becomes a dominating factor in the temperature coefficient variation. The disable switch  2538  enables the feature to be turned off if the temperature coefficient curvature compensation does not work well within the actual device. Thus, as it is illustrated in  FIG. 28 , the temperature coefficient curvature  2802  provided by the RC circuit is compensated for by the temperature coefficient curvature  2804  induced by the latch transistor  2534 . This results in a temperature coefficient  2806  that is more linear since the curvature of the RC circuit  2802  and the curvature of the temperature coefficient  2804  of the transistor tend to cancel out each other. 
     Referring now to  FIG. 29 , this temperature coefficient current compensation feature may also be made digitally programmable to allow more precise control over the amount of curvature correction implemented by the latching switch. Thus, rather than using a single latching switch  2534  that is turned on and off by a switch  2538 , a programmable latching transistor circuit  2902  may be utilized. The programmable latching circuit  2902  would be responsive to a multi bit input signal provided on control lines  2906 . The multi bit control signal would select the latch transistor or transistors that most nearly provided the desired temperature coefficient curvature desired to cancel out the temperature coefficient curvature caused by the RC circuit. Thus, the programmable latching transistor circuit  2902  provides a variable temperature coefficient curvature responsive to the multi bit digital input. This would enable the situation illustrated in  FIG. 30  wherein the temperature variation curvature  3002 , provided by the RC circuit could be corrected by any number of selected temperature coefficient curvatures  3004  implemented by the programmable latching transistor circuit  2902  responsive to the input control signal. Therefore, if the amount of temperature coefficient curvature in the RC circuit should vary from one manufacturing lot to another, the programmable curvature correction can be used to adjust for each lot individually, so that all lots end up having linear temperature coefficients despite the variations. 
     One possible implementation of the programmable latching transistor circuit  2902  is now described. Connect additional copies in parallel of the assembly consisting of latching transistor  2534  and its associated foot transistor  2538  in  FIG. 25 , such that all copies short together at node  2526  and at node  2534  but are free from one another at all other nodes. By turning off different numbers of the copies via their respective foot switches (the gates of the foot switches would connect to the digital input lines  2906  in a one-to-one fashion), the curvature of the oscillator temperature coefficient can be digitally programmed. The addition and subtraction of these copies changes the effective drive strength of the latching transistor  2534 , and therefore changes the curvature of the temperature coefficient. 
     Referring now to  FIG. 31 , there is illustrated a further embodiment of the band-gap generator  122  illustrated in  FIG. 1 . The temperature coefficients of the comparators  3102  and the regulated supply voltage  3104  within the oscillator may be controlled by providing the ability to digitally program the temperature coefficient of the band-gap reference voltage provided from the band-gap generator  122 . The temperature coefficient of the band-gap reference voltage is programmed responsive to a digital control signal provided via input  3106 . Having the ability to program the temperature coefficient of the band-gap reference voltage allows for precise control of the temperature coefficient of the comparators  3102  used in the oscillator and over the temperature coefficient of the regulated voltage supply  3104 . By having control over the temperature coefficient of the comparators  3102  and regulated voltage  3104 , the temperature coefficient variation of the entire oscillator circuit may be more closely controlled since the temperature coefficient variation of the comparators  3102  and regulated voltage supply  3104  is a chief source of temperature coefficient variations in the oscillator. 
     Referring now to  FIGS. 32   a - 32   d , there are more fully illustrated a schematic diagram of the band-gap generator  122 . The band-gap generator  122  consists of start-up circuitry  3202 , a PTAT generator  3204 , a CTAT generator  3206  and the programmable temperature coefficient circuitry  3208 . The programmable temperature coefficient circuitry  3208  is connected to the band-gap generator circuitry at node  3210 . A gate of transistor  3212  is connected to node  3210  and its source/drain path is connected between VDD and node  3214 . Transistor  3216  is connected in series with transistor  3212  and has its source/drain path connected between node  3214  and the output node of the band-gap generator  3218 . A resistor array is connected to node  3218 . The first part of the resistor array consists of a parallel combination of resistor  3220  and  3222  in series with another parallel combination of resistors  3224  and  3226 . The resistor array next comprises a series connection of resistors  3228 ,  3230 ,  3232 ,  3234  and  3236 . Resistors  3238  and  3240  have a first side connected to the bottom of resistor  3226  and a second end is connected to the CTAT generator at node  3242 . A series combination of resistors  3244 ,  3246  and  3248  are connected between the end of resistor  3236  and node  3242 . The CTAT generator  3206  is connected to the resistor array at node  3242 . Note that all resistors in the bandgap are chosen to be the same unit size in order to achieve the best possible matching. To construct bigger resistors than the basic unit size, resistors of unit size must be placed in series. Similarly, to construct resistors of smaller size, resistors of unit size must be placed in parallel. It should therefore be understood that the exact configuration of resistors in the programmable tempco circuit can easily be changed if a different total resistance is required. 
     The gates of transistors  3212  are each connected to node  3210 . The source/drain path of transistors  3212  are connected between VDD and node  3214 . Transistors  3216  are connected in series with transistors  3212  and have their source/drain path connected between node  3214  and the output node  3218 . The gates of transistors  3216  are connected to receive the trim signals trim 0 bar through trim 4 bar. Transistors  3217  have their source/drain path connected between node  3214  and the tops of resistors  3226 ,  3228  and  3234 , respectively. Transistors  3217   a ,  3217   b  and  3217   c  are connected to the top of transistors  3226 ,  3228 ,  3230 . Transistors  3217   d  and  3217   e  are connected to the top of resistor  3234 . The gates of transistors  3217  are connected to receive digital control signals trim  0  through trim  4 , which are the inversed of 0 bar through 4 bar. 
     By controlling the digital signals applied to the inputs of transistors  3216  and  3217  (which are the inverses of one another), the user may digitally program the temperature coefficient of the band-gap reference voltage provided at the output node  3218 . Transistors  3212  form individual legs of the output side of a current mirror, whose input side resides inside the PTAT generator. Transistors  3214  function as cascode transistors to improve the matching and power supply rejection of the mirror. Each of these transistor legs  3212  mirrors a weighted copy of the PTAT current, which is then dropped across a certain portion of the resistors in the resistor string. The total number of resistors that this current is dropped across differs from leg to leg. The weighting in the mirror legs is chosen in a binary fashion, by appropriately adjusting the number of fingers in each transistor. A net PTAT voltage is generated across the collective resistor string by adding up the individual IR (current times resistance) drops across each of the individual resistor segments in the resistor string. This net PTAT voltage then adds to the CTAT voltage generated by the emitter-to-base voltage of the diode-connected PNP bipolar transistor  3206  to form a bandgap voltage at node  3218  which in theory has a zero temperature coefficient (ZTC). By turning on and off different legs in the current mirror, the amount of net PTAT voltage that gets added to the fixed CTAT voltage is made larger or smaller, and thus the bandgap voltage can be varied from being PTAT to being ZTC to being CTAT, and in this way is therefore digitally programmable. Note that in this scheme, the value of the CTAT voltage is always kept fixed by ensuring that the current through the diode-connected transistors always remains the same. This is accomplished by always turning on one of the 0 bar to 4 bar signals whenever the corresponding 0 to 4 signal is turned off, and vice-versa. In this way, the net PTAT voltage is changed because the drops across the individual resistor segments is changed, but the total PTAT current flowing into the diode-connected CTAT generator  3206  always remains the same. 
     Referring now to  FIG. 33 , the precision oscillator  236  disclosed herein additionally has the ability to perform real time on-the-fly frequency trim. This process is software controlled and allows frequency trimming on-the-fly responsive to control values within a table  3304  stored within the SRAM memory  3302  as shown in  FIG. 33 . The temperature sensor  552  periodically provides on-chip temperature measurements to the core processor  140  through the multiplexer  113  and the SAR ADC  110 . The core processor  140  utilizes the provided temperature measurement to access a table  3304  within the RAM  3302  to determine if on-the-fly trimming of the oscillator frequency is necessary and finds the appropriate adjustment associated with the measured temperature. 
     This process is more fully illustrated in  FIG. 34 . A temperature reading is taken at step  3402  by the temperature sensor  552 , and the processing core  140  determines at inquiry step  3404  whether the present temperature reading equals the previous temperature. If so, there is no need to change the frequency of the oscillator, and the process waits at step  3406  until a next temperature reading is taken according to some internal counter. If the temperature reading does not equal the previous temperature reading, the frequency associated with the new temperature is located within the table  3304  at step  3308 . The new frequency associated with the new temperature is applied by the processing core at step  3410  which generates the necessary control signals to trim the oscillator to the new frequency. The new frequency is implemented in such a way that the adjustment of the frequency on-the-fly does not result in glitches within the clock signal from the oscillator. The fixed adjustment range in both the positive and negative directions is always available on-the-fly no matter how the part was initially trimmed at production. This is accomplished as shown in  FIG. 35  by including a programmable thermometer-coded array  3520  of capacitors in parallel with the coarse-tune  3512  and fine-tune capacitor  3516  arrays in the design. At the nominal setting, this bank of capacitors is in the middle of its range. Therefore, no matter how the coarse-tune  3512  and fine-tune  3516  arrays are trimmed at production, there is always equal positive and negative range in the separate thermometer-coded temperature trim capacitor array. Since the coding in the temperature trim array is thermometer, each transition of the setting only results in a single capacitor being turned on or off, causing no clock glitches. If on the other hand, the temperature trim array were to have been implemented with binary-coding, then a worst-case DNL-error step, e.g. 0111 to 1000 would result in 3 binary-weighted capacitors being turned off and 1 binary-weighted capacitor being turned on all at the same time, causing a serious glitch in oscillator frequency. 
     Referring now to  FIG. 35 , there is illustrated how the coarse and fine tune frequency trimming of the capacitors of the RC circuit  410  are broken apart such that the coarse and fine tuning are performed separately at production. The RC circuit  410  illustrated in  FIG. 35  includes a transistor  3502  having its source/drain path connected between VDD and node  3504 . Resistor  3506  is connected between node  3504  and  3508 . Transistor  3510  has its drain/source path connected between node  3508  and ground. The variable coarse capacitor array  3512  is connected between node  3508  and ground. The variable coarse capacitor array  3512  comprises a binary coded capacitor array. The fine capacitor array  3516  is connected between node  3508  and ground. The fine capacitor array  3516  includes binary coded capacitors for the lower significant bits and thermometer coded capacitors for the more significant bits. The temperature capacitor array  3520  is connected between node  3508  and ground. The temperature capacitor array  3520  includes only thermometer coded capacitors. 
     The binary coded capacitor array associated with the coarse capacitor  3512  is illustrated in  FIG. 36 . The binary coded capacitor array consists of a plurality of capacitors  3602  connected in parallel. A transistor  3604  is connected in series with each capacitor  3602 . The transistor  3604  has its drain/source path connected between the associated capacitor  3602  and ground. The capacitive values of the capacitors  3602  double with each capacitor such that the first capacitor has a value of 1x, the second capacitor has a value of 2x, the third capacitor has a value of 4x, the fourth capacitor has a value of 8x, the fifth capacitor has a value of 16x, the sixth capacitor has a value of 32x and the seventh capacitor has a value of 64x. Likewise, the size of the transistors  3604  associated with each of the capacitors increase in range from 1x for the transistors associated with the 1x and 2x capacitors up to 2x through 32x for the transistors associated with the 4x through 64x capacitors. The coarse tune capacitor array  3512  contributes the majority of the total timing capacitance for the oscillator. Note that we have specifically chosen to place the switching transistors beneath their respective capacitors, instead of on top of them, for the following reasons: (1) Considerably less parasitic junction capacitance (which has a very high and nonlinear tempco) is added to the capacitor array from the switch, (2) The step size between each capacitance setting is smaller which leads to higher resolution, (3) Process variations in the switches will never cause the step size to go above a certain mathematically bounded value, and therefore also places a mathematical bound on the worst-case trim resolution, (4) The resistance of the switch is fixed and does not vary with Vgs or Vsb and thus the temperature variation of the switches has a more linear tempco and less variation with supply voltage. 
     The binary coded and thermometer coded capacitor array comprising the fine capacitor array  3516  is illustrated in  FIG. 37 . The binary coded portion of the array consists of a parallel combination of capacitors  3702 . Each of the capacitors  3702  are in series with a capacitor  3704 . In series with each capacitor  3702  and in parallel with each capacitor  3704  is transistor switch  3706 . The transistor  3706  has its drain connected to capacitor  3702 , its source connected to output node  3710  and its gates to signals Cal( 0 ) and Cal( 1 ). The thermometer coded portion  3716  of the fine capacitor array  3516  consists of a parallel combination of the following repeating circuit connected between top node  3708  and bottom node  3710 . The repeating circuit includes a capacitor  3720  connected between the top node  3708  and node  3722 . A second capacitor  3724  is connected between node  3722  and the bottom node  3710  in series with capacitor  3720 . A switching transistor  3726  has its drain/source path connected between node  3722  and bottom node  3710 . The gate of the transistor  3726  is connected to receive a trim control signal Cal(X) at its input gate. The desired capacitance is achieved by connecting/disconnecting capacitors into/from the capacitor array by applying a trim control signal to the gate of transistor  3726 . Note that we have specifically chosen to place the switches beneath capacitors  3702  and  3720  for the same four reasons as previously explained with regards to the coarse array. 
     The temperature capacitor array  3720  consists of a thermometer coded capacitor array as illustrated in  FIG. 38 . The thermometer coded capacitor array consists of the following circuit repeated multiple times in parallel between a top node  3802  and a bottom node  3804 . The repeating circuit includes a capacitor  3806  connected between node  3802  and node  3808 . A second capacitor  3810  is in series with capacitor  3806  between node  3808  and node  3804 . A switching transistor  3812  has its drain/source path connected between node  3808  and node  3804 . The gate of transistor  3812  is connected to receive a trim control signal. The desired capacitance is achieved by connecting capacitors into the capacitor array by applying a trim control signal to the gate of transistor  3812 . Note that we have specifically chosen to place the switches beneath capacitors  3806  for the same four reasons as previously explained with regards to the coarse array. 
     Coarse trimming of oscillator frequency using the coarse array and fine trimming of frequency using the fine array are performed separately during production trimming. Separation of the coarse and fine frequency trims, like this, significantly reduces the worst-case DNL error in the oscillator trimming, and therefore significantly improves the achievable frequency trimming resolution. 
     The LIN (Local Interconnect Network) interface  135  is an asynchronous, serial communications interface used primarily in automotive networks. LIN compatible devices implement a complete LIN interface  135  having a number of features. These features include a selectable master and slave modes, unique self-synchronization without a quartz crystal or a ceramic resonator in both the master and slave modes. The LIN interface includes fully configurable transmission/reception characteristics via special function registers (SFRs). 
     The LINBUS is a small, slow network system as illustrated in  FIG. 39  that may be used as a cheap sub-network of a CAN (controller area network) BUS to integrate intelligent sensor devices or actuators in, for example, automobiles. LIN is a broadcast serial network comprising one master  3902  and up to 20 slaves  3904 . No collision detection exists, thus all messages are initiated by the master with at most one slave replying for a given message identifier. In the present embodiment, the described circuitry would comprise the master  3902 . However, in some embodiments the described circuitry could also be utilized as slaves  3904 . The slaves  3904  may comprise smart sensors and actuators for obtaining data that is transmitted back to the processing core through the master  3902 . 
     Referring now to  FIG. 40 , there is illustrated a block diagram of the main blocks of the LIN interface  135  enabling communications over a LINBUS. The LIN interface  135  includes register blocks  4002 , LIN interface registers  4004  and various data buffers  4006 . These are each in communication with the control free state machine and bit streaming logic  4008 . The register blocks  4002  contain all registers used to control the functionalities of the LIN interface  135 . The register blocks  4002  include LINCTRL; LINST; LINERR; LINSIZE; LINDIB; LINMUL and LINID. The LIN interface register  4004  provide the interface between the microcontroller core and a peripheral LIN device which is communicating with the core. The LIN interface registers  4004  include the LINCF; LINDAT; and LINADDR. The data buffers  4006  contain the registers where transmitted and received message data bytes are placed from transmissions between the microcontroller core and the peripheral LIN devices. The data buffer registers include LINDT 1  through LINDT 8 . The control free state machine and bit streaming logic  4008  contain the hardware necessary for serializing messages, and the circuitry for providing timing control to the peripheral LIN devices. 
     Communications with the LIN interface  135  are done indirectly through a pair of LIN interface registers  4004  called LINADDR  4010  and LINDATA  4012 . The selection of the master or slave mode and the automatic baud rate feature are accomplished through the LINCF register  4014 . In order to write to a specific register block  4002  other than the three LIN interface registers  4004  requires the system to first load the LINADDR register  4010  with the address of the required LIN register  4002  and then to load the data to be transferred to the register block  4002  using the LINDATA register  4012 . This process is more fully illustrated in  FIG. 41 . An instruction to write to one of the register blocks  4002  is received at step  4102 . An address of the register block to which the data is to be written is loaded at step  4104  into the LINADDR register  4010  of the LIN interface registers  4004 . Next, at step  4106 , the data to be loaded into the register block  4002  is loaded into the LINDATA register  4012  of the LIN interface registers  4004 . Finally, the data from the LIN data register  4012  is written to the register block  4002  indicated by the LINADDR register  4010 . 
     Referring now to  FIGS. 42 through 44 , there are illustrated the control register tables for the LINADDR register  4010 , the LINDATA register  4004  and the LINCF register  4014 .  FIG. 42  illustrates the control bits for the LINADDR register  4010 . The register contains eight bits for storing addresses to which the LIN peripheral devices may write.  FIG. 43  illustrates the control bits for the LINDATA register  4012 . This register contains eight bits for writing data to and from the register blocks  4002  and data buffers  4006 . Finally,  FIG. 44  illustrates the LINCF register  4014  bits. Bits  0 - 5  are used for data and bit  6  is used to illustrate whether an automatic bit rate selection or manual bit rate selection system is to be used. This bit is only utilized within the slave mode of operation for the LIN devices. Bit  7  is used to indicate the LIN operation mode selection. A “1” is used to indicate the master mode of operation and a “0” is used to indicate the slave mode of operation. 
     Referring now to  FIG. 45 , there is illustrated the configuration of the remaining LIN data control registers including the register blocks  4002  and the data registers  4006 . Each of the register block registers  4002  and data block registers  4006  are used in each of the master and slave modes. Register bits that are marked with (m) are accessible only in the master mode of operation where the register bits marked with the (s) are accessible only in the slave mode of operation. All remaining register bits are accessible in both modes of operation. 
     The data buffer registers consist of the registers LINDT 1  through LINDT 8 . These registers each include eight bits for storing a single serial data byte that is to be received by or transmitted by the LIN interface registers  4004 . 
     The LIN control register (LINCTRL) is a register block  4002 . Bit  7  of the LIN control register comprises the stop bit (STOP). This bit is to be set by an application to block the processing of the LIN communications until a next SYNC BREAK signal. The stop bit is used when the application is handling a data request interrupt and cannot use the frame&#39;s content with the received identifier. Bit  6  comprises the sleep mode warning bit (SLEEP). This bit is set by an application to warn the LIN peripheral that a sleep mode frame has been received and that the LINBUS is in the sleep mode. Alternatively, it notifies the peripheral if a bus idle time out interrupt has been requested. The application resets the sleep mode warning bit when a wake up interrupt is requested. Bit  5  of the LIN control register comprises the transmit/receive selection bit (TXRX). This bit is set by an application to select if the current frame is a transmit frame or a receive frame. Bit  4  of the LIN control register comprises the data acknowledge bit (DTACK). This bit is only utilized in the slave mode of operation. This bit is set by the application after handling a data request interrupt and is reset by a LIN peripheral. Bit  3  comprises the interrupt reset bit (RSTINT) of the LINCTRL register. This bit is set by an application to reset the interrupt bit in the LIN status register (LINST). Bit  2  comprises the error reset bit (RSTERR) of the LIN control register. The application must set the RSTERR bit in order to reset the error bits in the LIN status register (LINST) and the LIN error register (LINERR) bits. Bit  1  comprises the wake up request bit (WUPREQ). This bit is set by an application to end the sleep mode of the LIN bus by sending a wake up signal. The bit  0  bit comprises the start request bit (STREQ) of the LINCTRL register. This bit is only utilized in the master mode of operation. This bit is set by an application to start a LIN transmission. It may be set only after loading the identifier, data link and data buffer. The bit is reset by a peripheral LIN device upon completion of the transmission or error protection. 
     The LIN status register (LINST) includes eight different control bits. Bit  7  comprises the LINBUS activity bus bit (ACTIVE). This bit shows when transmission activity on the LINBUS is detected by a peripheral device. Bit  6  comprises the bus idle timeout (IDLTOUT) of the LIN status register. This bit is set by the peripheral device if no bus activity is detected over a period of 4 seconds and the sleep bit in the LIN control register (LINCTRL) is not set by the application. Upon settling this bit, the peripheral also sets the interrupt request bit (LININT) and the applications can then assume that the LINBUS is in sleep mode and set the sleep bit. Bit  5  comprises the aborted transmission signal bit (ABORT). This bit is only used in the slave mode of operation. The aborted transmission signal bit is set by a peripheral device when a new SYNC BREAK signal is detected before the end of end of the last transmission. The transmission is aborted and the new frame is processed. The aborted transmission signal bit is also set when the application sets the stop bit of the LINCTRL register. Once a SYNC BREAK signal is received this signal is reset. Bit  4  comprises the data request bit (DTREQ). This bit is only used in the slave mode of operation. A peripheral device sets this bit after receiving the identifier and requests an interrupt. Bit  3  comprises the interrupt request bit (LININT). This bit is set when an interrupt is issued and has to be reset by the application by setting the RSTINT bit within the LINCTRL register. Bit  2  comprises the communications error bit (ERROR). A peripheral device sets this bit if an error has been detected. The bit must be reset by the application by setting the RSTERR bit of the LINCTRL register. Bit  1  comprises the wake up request bit (WAKEUP). This bit is set when a peripheral is transmitting a wake up signal or has received a wake up signal. Finally, Bit  0  comprises the transmission complete bit (DONE). A peripheral device sets this bit at the end of a successful transmission and resets the bit at the start of another transmission. 
     The LIN error register (LINERR) also includes 8 bits. Bits  7  through  5  are unused in the LIN error register. Bit  4  is the synchronization error bit (SYNC) and is only used in the slave mode of operation. A peripheral device detects edges of a SYNC FIELD outside the maximum tolerance and sets this bit in response thereto. Bit  3  comprises the parity error bit (PRTY). This bit is only used in the slave mode of operation and is set when a parity error is detected. Bit  2  comprises the time out error bit (TOUT). This bit is set whenever one of a number of time out error conditions are met. Bit  1  comprises the checksum error bit (CHK). This bit is set when the peripheral device detects a checksum error. The bit  0  bit comprises the bit error bit (BITERR). The error bit is set when the bit value monitored by the peripheral is different from the ones transmitted. 
     The LIN message size register (LINSIZE) comprises an eight bit register. Bit  7  comprises the checksum version selection bit (ENHCHK). This provides an indication of the checksum version used by the peripheral. Bits  6  through  4  are unused in the LIN message size register (LINSIZE). Bits  3  through  0  indicate the size of the LIN data field. The data field may comprise 2, 4 or 8 bytes. 
     The LIN divider register (LINDIV) comprises an eight bit register using bits  7  through  0  for containing the eight least significant bits of the divider used to generate the baud rate of the LINBUS. The LIN multiplier register (LINMUL) is an eight bit register wherein bits  7  and  6  comprise a prescaler used to create the baud rate. Bits  5  through  1  comprise a multiplier used to create the baud rate and bit  0  comprises the most significant bit of the divider used to create the baud rate. The LIN ID register (LINID) is an eight bit register wherein bits  7  and  6  are unused. Bits  5  through  0  are used for the identifier. 
     Using the LIN interface enables the device to operate within a LIN network as a master node or slave nodes. All nodes would include a slave communication task that is split into a transmit and a receive task while the master node further includes an additional master transmit task. In most applications, the described device will operate as the master node within a LIN network. It may communicate with a number of different LIN peripheral devices acting as slaves. In one example, the slave nodes may comprise various sensors within an automobile associated with major systems of the car such as the transmission, tires, oil sensor, temperature sensor, etc. Automotive applications include body control, driver information, multimedia, climate control, safety equipment, cockpit electronics and human/machine interface. 
     Referring now to  FIG. 46 , there is illustrated a configuration of multiple master devices  4602 . Each of the master devices  4602  are interconnected with each other via a CAN (Control Area Network) bus. Communications may occur between each of the masters  4602  via the CAN bus  4604 . Each of the masters  4602  are also connected with up to twenty different slave devices  4606 . The slaves  4606  are interconnected with the master devices  4602  via a LINBUS network  4608 . Any of the slave devices  4606  may communicate with only the master  4602  with which they are connected on the LINBUS network  4608 . The present configuration of LINBUS networks enable up to twenty slave devices  4606  to be connected with one master  4602 . In order for any additional slave devices to be utilized, an additional master  4602  must be configured. The master slave configuration using the LINBUS network  4608  and the CAN network  4604  are often implemented within automobile systems. 
     This implementation is more particularly illustrated in  FIG. 47  which shows an automobile system including both CAN network and LINBUS network configurations. The system illustrated includes a CAN bus  4702  which interconnects a variety of master controller units within the automotive system. For example, the lock controller  4704  is interconnected with a number of slave devices including a mirror  4706 , door controls  4708  and a window lift  4710 . Each of these components is interconnected with the lock master controller  4704  via a LINBUS network  4712 . Other master controllers such as the seat controller  4714  are interconnected with a number of different driver motors  4716 , seat control panels  4718  and heating sensors/controllers  4720 . Other examples of master microcontrollers include the climate control master  4722  connecting to various climate control motors  4724 . The previous illustrations of master controllers and slave devices are merely exemplary and any number of master control devices and slave devices may be utilized within an automotive system using a combination of a CAN network and LINBUS networks. 
     Referring now to  FIG. 48 , there is illustrated the manner by which a master device  4602  ( FIG. 46 ) initiates communications with a slave device  4606  ( FIG. 46 ) using a message frame  4800 . The LINBUS message frame  4800  is divided into a message header  4802  and the message response  4804 . The message header  4802  consists of a sync break  4806  which indicates the beginning of the message frame when the signal is pulled low for a predetermined period of time. The sync break  4806  is initiated when the signal line is pulled low for at least 13 bits. The sync break  4806  may also be longer than 13 bits. Following the sync break  4806  is a synch field  4808 , which is essentially a start field for the message frame  4800 . The sync field  4808  includes a set number of pulses  4809  to assist with frame synchronization of the frame. Following the sync field  4808  is the identifier field  4810  which provides an indication of the command to be performed on the LINBUS connection. Types of commands may include an indication that a particular slave device is to receive information from the master, that the slaves are to listen for communications from the master or that a slave has the ability to transmit data to the master. The format of the identifier field includes a start bit  4812  (the line being pulled low) followed by an 8-bit data field  4814  and a stop bit  4816  (the line remaining high). Following the message header  4802  is a message response section  4804  which includes up to eight 8-bit data fields  4818  in which information may be provided over the LINBUS. Finally, a checksum field  4820  is included for assisting in the assurance of data integrity within the message frame  4800 . 
     While the LINBUS architecture has proved very effective in implementations such as an automotive system, the LINBUS network includes one major design limitation in that only up to twenty slave devices may be connected with a single master device over a LINBUS network. While this comprises a large number of slave devices, in complex mechanical systems such as an automotive system there is often the need for hundreds if not thousands of sensors and controllers that may be implemented within the system and when these devices are interconnected using a LINBUS network the number of master controllers can greatly increase the cost of the system when each twenty sensors requires a separate controller in order to operate within a LINBUS environment. If another CAN controller and LINBUS master are required, this will increase costs. 
     Referring now to  FIG. 49 , there is illustrated a method for interconnecting a microcontroller unit  4902  as described previously using the crossbar switch  4904  therein to interconnect the microcontroller unit  4902 , which is acting as a master device, with a plurality of different groupings of slave devices  4906 . The slave devices  4906  are each connected to the master controller  4902  through a LINBUS interface circuit  4908 . The LINBUS interface circuit  4908  includes a resistor  4910  connected between system power and node  4912 . A transistor  4914  has its drain/source path connected between node  4912  and ground. A first input of the LINBUS interface circuit  4908  interconnects node  4912  with the microcontroller  4902  crossbar switch  4904  through a pair of the microcontroller input ports. The RX input connected to node  4912  provides the interconnection between the LINBUS circuitry  4916  of the master microcontroller unit  4902  and the slave devices  4906 . The TX input of the LINBUS interface circuit  4908  connects the LINBUS circuitry  4916  to the gate of the transistor  4914  to enable transmissions from the master  4902  to the slave devices  4906  over the LINBUS network. The slave connection of the LINBUS interface circuit  4904  is connected to the bus  4918  interconnecting each of the slave devices  4906 . 
     Using the described configuration, the master microcontroller  4902  can be connected to a plurality of groups of slave devices such that the microcontroller  4902  is not limited to the twenty slave device limit imposed by the LINBUS network protocol. Thus, the microcontroller  4902  may be selectively connected to group A consisting of slave devices  4906 A, to group B consisting of slave devices  4906 B, to group C consisting of slave devices  4906 C or to group D consisting of slave devices  4906 D. During operation, the LINBUS hardware  4916  may only be connected to a single group of slave devices  4906 . Thus, at any particular time, only one of the interface circuits  4908  will enable interconnection of the LINBUS hardware  4916  with the associated group of slaves  4906 . A LINBUS interface circuit  4908  is actuated enabling the interconnection between the LINBUS hardware  4916  and the associated group of slaves  4906 . The RX connection enables the LINBUS hardware  4916  to monitor signals from the slave devices  4906  on bus  4918 . The TX connection enables the LINBUS hardware  4916  to transmit data to the slave devices  4906  on bus  4918 . However, the monitoring of the RX port when connected to the LINBUS circuitry  4916  only allows that one LINBUS be monitored. This will be described in more detail hereinbelow. 
     The crossbar switch  4904  interconnecting the LINBUS hardware  4916  with, for example, slave devices  4906 A provides an interconnection of the LINBUS hardware  4916  to the circuit interface  4908 A through pin pads P 0  and P 1 . The crossbar switch  4904  also connects the special function register  4920  to the remaining LINBUS interfaces  4908 . The SFR  4920  provides a logical low signal to pins P 3 , P 5  and P 7 . The bits are set to logical low “0” such that the transistor  4914  in the associated LINBUS interface  4908  is turned off to disable transmissions on the associated line  4918  while the one LINBUS interface circuit  4908   a  provides an interconnection between the LINBUS hardware  4916  and associated slave devices  4906 . When a particular group of slave devices  4906  are interconnected, the associated pin P 0 , P 2 , P 4  or P 6  is selectively connected to the LINBUS hardware  4916  through the crossbar switch  4904 . The remaining unselected ones of the pin pads of P 0 , P 2 , P 4  and P 6  which are not interconnected to the LINBUS circuitry  4916  are allowed to float but may be monitored by the processing core of the master controller  4902  for a port match condition, as described below. The port match configuration is a configuration of the GPIO pins of the crossbar switch  4904  that causes generation of an interrupt when a value monitored on the GPIO pin does not equal a compared set value. 
     The processing core of the microcontroller  4902  will establish the mask values within the SFR register  4920  determining upon which set of slave devices  4906  the microcontroller  4902  should be attached to. Additionally, the processing core will control the crossbar switch  4904  to interconnect the SFR register  4920  with each of pins P 1 , P 3 , P 5  and P 7  and to connect the LINBUS circuitry  4916  with a selected pair of the port pins as appropriate. While the description with respect to  FIG. 49  has illustrated a crossbar switch  4904  which may interconnect the LINBUS hardware  4916  with four different groups of slave devices  4906 , the configuration described herein is applicable to any number of groups of slave devices. Alternatively, while the above description describes connecting groups of slave devices  4906  to only a single group of LINBUS hardware  4916 , multiple groups of LINBUS hardware  4916  may each be connected with an associated group of slave devices  4906  within a single chip. 
     The values on the transmit (TX) lines of each unconnected LINBUS interface circuit  4908  consisting of ports P 2 , P 4  and P 6  in  FIG. 49 , are compared with a logical value stored in a SFR register  4950 . The SFR register  4950  comprises the P#MAT register ( FIG. 50   a ), where # is the number of the port pin. There is a separate P#MAT register associated with each of the port pins of the master controller  4902 . The P#MAT register is an 8-bit register that contains the value that unmasked port pins are compared against in the port switch mode. In the case illustrated in  FIG. 49 , the associated P#MAT registers  4950  would have the value within the registers compared against port pins P 2 , P 4  and P 6 . The SFR register P#MASK  4952  is an 8-bit SFR register which is used to select the port pins which will be compared to the value stored in the P#MAT register  4950 , shown in  FIG. 50   a . Within the example in  FIG. 49 , the port P 0  would be the only masked port as all of the other port pins P 2 , P 4  and P 6  would be unmasked to enable comparison with the P#MAT register value. The P#MASK register  4952  is more fully illustrated in  FIG. 50   b . The value stored within the P#MAT register  4950  is compared with the associated values on the unconnected RX lines for the LINBUS interface  4908  within software by the processing core of the master microcontroller unit  4902 . Alternatively, the values at the RX line may be compared with the value in the SFR register  4950  using the comparator circuit CPO or CPI more fully illustrated in  FIG. 1  and discussed herein. 
     If these compared values match, no action is taken as this condition provides no indication that a slave device  4906  upon one of the unconnected slave device groups has indicated a need to communicate with the LINBUS master  4902 . However, when one of the lines has been pulled low, the port match condition will indicate a lack of a match between the associated port connected to the RX line of the slave device  4906  wanting to communicate and the stored value in register  4950 . An interrupt will be generated to the processing core of the master controller  4902  responsive to this condition. When the LINBUS hardware  4916  provides an indication to the processing core that it has completed actions on the presently connected group of slave devices, the processing core of the master controller  4902  configures the crossbar switch  4904  to disconnect the presently connected group of slave devices and connect with the group of slave devices  4906  causing the indication via the interrupt. 
     This process is more fully illustrated in the flow chart illustrated in  FIG. 51 . The LINBUS hardware  4916  is initially connected to a first slave device group at step  5102  in order to provide communications to the various slave devices  4906  within the group. Once the LINBUS hardware  4916  has been connected with the slave device group, the LINBUS hardware  4916  initiates a wake up procedure at step  5104  with the slave devices  4918  to begin communications with the slave devices of the connected group. At step  5106 , the remaining pins of the crossbar switch  4904  connecting the receive connections of the LINBUS interfaces  4908  to the LINBUS hardware  4916  are set to the port match mode. Thus, when the BUS line  4918  is pulled low by a slave device within an unconnected group of slave devices, an interrupt associated with the port of a connected slave device wishing to communicate with the master  4902  is generated. Additionally, the transmit ports connected to the base of the transistors  4914  within the LINBUS interface  4908  are connected to the SFR registers  4920  to provide a logical “0” value to the gates of these transistors  4914  turning them off. 
     Inquiry step  5110  determines whether it is time to switch to a next group of slave devices. If so, the LINBUS hardware  4916  is connected at step  5112  to the next group of slave devices and the LINBUS circuitry initiates a wake up process at step  5114  to the slave devices within the connected slave device group. Control passes to step  5106  to disconnect the remaining groups of slave devices. If inquiry step  5110  determines it is not time to switch to a next slave group based upon some predetermined time length or other parameter established by the system, inquiry step  5116  determines if a port match condition exists on any of the receive pins of the LINBUS interfaces  4908  of the remaining slave groups (noting that the port match feature is an interrupt driven process). If the indication is that all ports are still matched, control passes back to inquiry step  5110 . If a port match condition does not exist on one of the pins, the LINBUS hardware is connected at step  5118  to the pin of the slave group that has an interrupt indicating that the port match condition does not exist, and a wake up process is initiated at step  5120  for this slave group. Control returns back to step  5106  to disconnect the transmit and receive ports of the remaining slave groups and connect them with the appropriate SFR registers. 
     Rather than initiating the wake up process between the master device  4902  and any connected slave devices  4906  when switching to a new group of slave devices  4906 , the cross bar switch  4904  can be used to temporarily connect the port associated with the receive line pin of the interface  4908  to ground to simulate the receipt by the LINBUS hardware  4916  of an indication by a slave  4906  to communicate with the master  4902 . The crossbar switch  4904  would then reconnect the temporarily grounded port to the node  4912  of the communication interface  4908 . 
     Referring now to  FIG. 52 , there is illustrated a flow diagram describing the operation of a LINBUS network including the microcontroller  4902  and slave devices  4906  of  FIG. 49 . Initially, at step  5202  a group of slaves are selected for connection to the LINBUS circuitry  4916  within the master microcontroller  4902  such as that discussed above with respect to  FIG. 51 . The selection of the group of slaves for interconnection with the master microcontroller may be done in any number of fashions under control of the processing core of the microcontroller  4902 . Once a group of slaves are selected, at step  5204 , the transistor within the LINBUS interface circuit  4908  associated with the group of transistors is turned on to pull the BUS line  4918  low by applying a logical high signal to the transistor gate. Additionally, a logical low “0” signal is applied to the gates of the remaining transistors  4914  within the other LINBUS interface circuits  4908 . Finally, the slave devices  4906  are connected to the LINBUS circuitry  4916  through the RX connection of the interface circuits  4908 . The process described with respect to  FIG. 51  describes one manner of selecting a group of slaves. 
     Referring now to  FIG. 53 , there is illustrated another embodiment for the manner of selecting the group of slave devices  4918  for interconnection to the master microcontroller unit  4902 . In this routine, the master controller  4902  is initially connected to a first group of the slave devices at step  5302 . Inquiry step  5304  determines whether a period of time during which the LINBUS circuitry  4916  of the microcontroller  4902  is supposed to be connected with the present group of slave devices  4906  has expired. If not, inquiry step  5304  continues to monitor for expiration of this time period. Once this time period expires, the master microcontroller  4902  is instructed by its processing core to switch to the next group of slave devices at step  5306 . This process would involve initiating the connection through the associated LINBUS interface circuit  4908  and turning off the LINBUS interface circuit  4908  associated with the previous group of slave devices. Control then passes back to step  5304  where the master controller  4902  waits for expiration of its next time period. Thus, in this manner the microcontroller  4902  would merely cycle through each of the groups of slave devices  4906  with each group of slave devices being connected to the LINBUS circuitry  4916  for a predetermined period of time. 
     It will be appreciated by those skilled in the art having the benefit of this disclosure that this invention provides a LINBUS interface within a processing device enabling connections to multiple groups of slave devices. It should be understood that the drawings and detailed description herein are to be regarded in an illustrative rather than a restrictive manner, and are not intended to limit the invention to the particular forms and examples disclosed. On the contrary, the invention includes any further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments apparent to those of ordinary skill in the art, without departing from the spirit and scope of this invention, as defined by the following claims. Thus, it is intended that the following claims be interpreted to embrace all such further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments.