Patent Publication Number: US-8539411-B2

Title: Multiple derating factor sets for delay calculation and library generation in multi-corner STA sign-off flow

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     [none] 
     BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention relates generally to the art of microelectronic integrated circuits. In particular, the present invention relates to the art of computing delays for cells in ASICs. 
     2. Description of Related Art 
     An integrated circuit chip (hereafter referred to as an “integrated circuit” (IC), “ASIC”, or a “chip”) comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells. 
     A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. 
     A net is a set of two or more pins which must be connected. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins which must be connected in various combinations, the chip also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins. All the pins of a net must be connected. The number of the nets for a chip is typically in the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins. Some nets may include hundreds of pins to be connected. A netlist is a list of nets for a chip; more generally a netlist is a description of the logic cells and their connections. 
     Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in several layers. 
     The layout is then checked to ensure that it meets all of the design requirements. The result is a set of design files in a particular unambiguous representation known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator. 
     During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The component formation requires very exacting details about geometric patterns and separation between them. The process of converting the specifications of an electrical circuit into a layout is called the physical design. 
     Currently, the minimum geometric feature size of a component is on the order of less than 45 nm, at the process node of 45 nm. Feature sizes will be reduced even further as technology progresses. This small feature size allows fabrication of many transistors on a chip. This trend is expected to continue, with even smaller feature geometries and more circuit elements on an integrated circuit, and of course, larger die (or chip) sizes will allow far greater numbers of circuit elements on them. 
     ASIC design flow is a combination of logical design and physical design, and includes a variety of steps, which include and are not limited to design entry, logic synthesis, system partitioning, floorplanning, placement, routing, and simulation, with constant feedback in these processes. The objective of physical design is to determine an optimal arrangement of devices in a plane or in a three dimensional space, and an efficient interconnection or routing scheme between the devices to obtain the desired functionality. Libraries characterize different devices and components used in the ASIC design flow, with the components simulated according to the program SPICE (Simulation Program with Integrated Circuit Emphasis), a general purpose analog electronic circuit simulator used in IC design to check the integrity of circuit designs and to predict circuit behavior. Libraries exist to characterize semiconductor devices at various parameters including process node, voltage, temperature and the like. 
     ASIC designers further need a timing model for each cell used in an ASIC to determine the performance of the ASIC, including timing closure. Timing closure includes the ability of an ASIC cell or block to transmit and/or process a signal within specified time parameters in a specification. Various types of delay exist in an IC including but not limited to pin-to-pin delay between input and output pins of a logic cell, pin delay, and net or wire delay. Typically it is too time-consuming to build every cell in silicon and measure actual cell delays, instead, designers simulate the delay in a cell, a process called characterization. 
     Due to the large number of components and the exacting details required by the fabrication process, logical and physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use Computer Aided Design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. 
     In an ASIC, the layout design process involves several steps. The input to the physical design problem is a circuit diagram, and the output is the layout of the circuit. This is accomplished in several stages including partitioning, floor planning, placement, routing and compaction. 
     Regarding partitioning, a chip may contain several million transistors. Layout of the entire circuit cannot be handled due to the limitation of memory space as well as the computation power available. Therefore, the layout is normally partitioned by grouping the components into blocks such as sub-circuits and modules. The actual partitioning process considers many factors such as the size of the blocks, number of blocks and number of interconnections between the blocks. 
     The output of partitioning is a set of blocks, along with the interconnections required between blocks. The set of interconnections required is the netlist. In large circuits, the partitioning process is often hierarchical, although non-hierarchical (e.g. flat) processes can be used, and at the topmost level a circuit can have between 5 to 25 or more blocks. However, greater numbers of blocks are possible and contemplated. Each block is then partitioned recursively into smaller blocks. 
     Regarding floor planning and placement, this step is concerned with selecting good layout alternatives for each block of the entire chip, as well as between blocks and to the edges. Floor planning is a critical step as it sets up the ground work for a good layout. During placement, the blocks are exactly positioned on the chip. The goal of placement is to find a minimum area arrangement for the blocks that allows completion of interconnections between the blocks. Placement is typically done in two phases. In the first phase, an initial placement is created. In the second phase, the initial placement is evaluated and iterative improvements are made until the layout has minimum area and conforms to design specifications. 
     Regarding routing, the objective of the routing phase is to complete the interconnections between blocks according to the specified netlist. First, the space not occupied by blocks, which is called the routing space, is partitioned into rectangular regions called channels. The goal of a router is to complete all circuit connections using the shortest possible wire length and using only the channel. Routing is usually done in two phases referred to as the global routing and detailed routing phases. In global routing, connections are completed between the proper blocks of the circuit disregarding the exact geometric details of each wire and terminal. For each wire, a global router finds a list of channels that are to be used as a passageway for that wire. In other words, global routing specifies the loose route of a wire through different regions of the routing space. 
     Global routing is followed by detailed routing which completes point-to-point connections between terminals on the blocks. Loose routing is converted into exact routing by specifying the geometric information such as width of wires and their layer assignments. Detailed routing includes the exact channel routing of wires. 
     In order for circuit designers to calculate the performance of ASICs, the designers need to compute the delays of the cells in the ASICs. Two types of delays are considered. The first type of delay is the propagation delay of a cell. A propagation delay of a cell is defined as the time duration a signal takes to travel from the input to the output of a cell. The measurement point at the input is called the switching threshold. A propagation delay of a cell is defined for every input to output pin combination of a cell under both the rising and falling input conditions. The propagation delay is also affected by a given process (P), voltage (V) and temperature (T). 
     The second type of delay is the setup/hold time delay which is an input constraint for sequential cells. The setup time is defined as the time duration a data signal is required to be available at the input of a cell before the clock signal transition, and the hold time is defined as the time duration a data signal is required to be stable after the clock signal transition. For the purpose of explanation, both propagation delay and setup/hold time, can be referred as delay. 
     As the semiconductor industry advances to a smaller process node, especially 90 nm and below, there is a need for more sign-off corners in STA (statistical timing analysis). Corners is a term of art and may be thought of as extremes in process (P), voltage (V) and temperature (T) at which a circuit design has to achieve timing closure for a particular time requirement and operate according to specification; a sign-off is a guarantee that the circuit can perform at a particular corner combination. A sign-off corner is thus a sort of factor of safety that a chip or ASIC can operate satisfactorily. 
     However, more sign-off corners have a drawback: more library generation at each specific corner, which results in tremendous characterization time. By way of example, a cell library may have as parameters three external variables P (process, i.e., N-doped/P-doped parameters at a particular feature size), T (temperature) and V (voltage), with each of these variables being split into nominal (NOM), best case (BC) or worse case (WC), to factor in a factor of safety, with temperature varying from a low of say −40 C to a high of 125 C, and voltage varying +/−10% from VDD. If one were to generate all corner libraries for all the different PVT combinations to satisfy all possible customers, there might be over twenty combinations, such as: BC PVT (best case for P, V and T); BC PV+WC T (best case for P, V and worse case for T); BC P+WC VT (best case for P, worse case for V and T); WC PVT (worse case P, V and T); WC PV+BC T (worse case P, V and best case T); and WC P+BC VT (worse case P and best case V, T). 
     A derating equation is used to rapidly compute the delay in an ASIC cell; otherwise calculating delay would take longer. The derating equation(s) used by the assignee of the present invention to compute the delay of a cell for a given P, V and T of a cell is given by U.S. Pat. No. 6,820,048 (the &#39;048 patent), issued to Bhutani et al. (Nov. 16, 2004), and U.S. Pat. No. 6,484,297 (the &#39;297 patent), issued to Dixit et al. (Nov. 19, 2002), all incorporated herein by reference in their entireties. 
     Further, the following equations are used for deratings, which are derivatives of the equations in the &#39;048 and &#39;297 patents:
 
DelayCorner=Delay0+( K 1 *V *Fanout +K 2 *V *Ramptime+ K 3 V *Fanout*Ramptime +K 4 V )*Delta V   Equation 1
 
DelayCorner=Delay0+( K 1 *T *Fanout +K 2 *T *Ramptime+ K 3 T *Fanout*Ramptime +K 4 T )*Delta V   Equation 2
 
     where: Delay 0  is a prior delay; K 1 , K 2  are derating equation factors as described in the &#39;297 and &#39;048 patents; T, V are temperature and voltage; and Fanout, Ramptime are the fan-out and ramptime of the ASIC components under investigation. 
     The above equation is also equally good for other timing considerations like setup/hold. When calculating delay, a cell delay library is used, with the cell delay library including a table for each timing arc in the library, indexed by input ramptime and output fanout load. The base corner library is then characterized for delay values, at four points. The delay number of these four points plus equations (1) and (2) is used to calculate the four K factors. Once the K factors are obtained, another library can be generated from this base library, using equations (1) and (2). However, since equations (1) and (2) are linear with respect to V and T, and vary as the square with respect to Fanout and Ramptime, the delay vs. PVT is highly nonlinear, and this causes a decrease in accuracy when a corner library is far away from the base corner. 
     What is lacking in the prior art is a method and apparatus for an improved process to calculate delay and to generate libraries for ASIC components during STA, such as taught in the present invention. 
     SUMMARY OF THE INVENTION 
     Accordingly, an aspect of the present invention is a method to increase the accuracy when generating delay calculations when characterizing ASIC cells in low submicron processes. 
     A further aspect of the present invention is a method of using multiple derating factors for different STA sign-off corners. 
     Another aspect of the present invention is a method of increasing the accuracy of delay calculations and library generation at corners other than standard corners, such as off-corners. 
     Another aspect of the present invention is keep the library generation time to a minimum while maintaining acceptable accuracy. 
     Yet another aspect of the present invention is to propose a method for delay calculation flow to use multi-set of multi-point derating factors K, to do delay calculations or to generate off-corner libraries in STA timing sign off, all the while keeping the characterized base library calculation numbers to a minimum, speeding up the delay and characterization. 
     Thus the present invention enables a fast, accurate way for timing library generation for deep sub-micron semiconductors. 
     The sum total of all of the above advantages, as well as the numerous other advantages disclosed and inherent from the invention described herein, creates an improvement over prior techniques. 
     The above described and many other features and attendant advantages of the present invention will become apparent from a consideration of the following detailed description when considered in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Detailed description of preferred embodiments of the invention will be made with reference to the accompanying drawings. Disclosed herein is a detailed description of the best presently known mode of carrying out the invention. This description is not to be taken in a limiting sense, but is made merely for the purpose of illustrating the general principles of the invention. The section titles and overall organization of the present detailed description are for the purpose of convenience only and are not intended to limit the present invention. 
         FIG. 1  is a basic flowchart for achieving the present invention. 
         FIG. 2  is data illustrating the improvement in performance over prior techniques in accordance with the present invention. 
     
    
    
     It should be understood that one skilled in the art may, using the teachings of the present invention, vary embodiments shown in the drawings without departing from the spirit of the invention herein. In the figures, elements with like numbered reference numbers in different figures indicate the presence of previously defined identical elements. 
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is a method to insert multiple corner deratings for delay calculations and library generation in a multi-corner STA sign-off methodology. An apparatus and method is disclosed to characterize a new process using an improved delay calculation. Multiple derating factors are used for different STA sign off corners. The approach of the present invention does not add any extra work in cell library characterization, while in the mean it increases the accuracy of the delay calculation and the library generation at corners other than standard corners. 
     In a preferred embodiment, the method and apparatus of the present invention can employ a mainframe or personal computer to run any software tool that incorporates the invention, and in general any compatible piece of hardware or virtual machine can run the present invention, in particular during the logical and physical design of a circuit such as an ASIC. Thus a preferred method and apparatus of the present invention is a computing platform running a software tool, which can accept human input, and may be written in any computer language (such as C, C++, Perl, Java or the like), and/or an Object Oriented programming (OOP) language, run by a computer system having an operating system. The computer system typically has one or more processors, primary and secondary memory cooperating with the processor(s), which executes instructions stored in the memory, I/O means such as monitor, mouse and keyboard, and any necessary specialized hardware or firmware. Depending on the language used to construct and implement the software tool, the object code of the tool may have any number of classes, functions, objects, variables, templates, lines of code, portions of code and constructs (collectively and generally, “a process step”, “step”, “block”, “method”, “module”, “functional module” or “software module”) to carry out the invention in successive stages as described and taught herein, and may be either a standalone software application, or employed inside of or called by another software application, or as firmware. The software process or software module may be constructed so that one portion of code in the application performs a plurality of functions, as for instance in Object Oriented programming (e.g., an overloaded process). The converse is also true, in that a plurality of portions of code could perform a plurality of functions, and still be functionally the same as a single portion of code. At any stage of the process step of the present invention, intermediate values, variables and data may be stored for later use by the program. 
     Turning attention now to  FIG. 1 , the flowchart of the present invention is shown. The steps of the flowchart are not necessarily rigid and structured to flow from a first step A to a second step B, but are more free flowing, as indicated by the boxes and the arrows, which represent a number of steps within each box, consistent with the complex, multifaceted steps associated with ASIC design. 
     Thus, a first step would be to characterize the libraries forming the base corners, from which the so-called off-corner libraries are measured. In  FIG. 1 , this step is illustrated by box  105  labeled “Characterized Libraries At 3 Base Corners”. Characterization may be performed by standard ASIC tools for this purpose, known per se in the art, which may be homegrown or commercial products, e.g. such as NanoChar by Synopsys. For purposes of this invention, the base corner libraries or base corner points chosen from the set of all possible libraries or points include: BC PVT (best case for P, V and T); NOM PVT (nominal case for P, V and T); and WC PVT (worse case for P, V and T). Note this is a smaller set of base corner points than the set of all possible corner libraries or points that can be generated for all the different PVT combinations, such as indicated in the background of the invention, hence these base corner library points or base corners can be termed a limited set of base corner library points from the set of all possible library points. 
     Next, a second step would be to derive two sets (four points) to be used for calculating derating K factors at near and far ends of the spectrum of parameters from the base corner voltage (V) and temperature (T) parameters, given a particular process, called “off-corner” points. This is indicated in  FIG. 1  by the step box  110  labeled “Characterized At 4 Other Points At Near And Far End Of The Base Corner VT”. At these points STA is performed by standard ASIC tools for this purpose, known per se in the art, e.g. such as by NanoChar. Hence, to give but one example, if the base corner library is BC PVT (best case for P, V and T), then two sets of off-corner points would be: 
     Off-corner point A: BC PV+WCT (best case P, V and worse case T) 
     Off-corner point B: BC PV+BCT+ΔT (best case P, V and best case T plus a small deviation/perturbation in temperature, ΔT) 
     Off-corner point C: BC PT+WCV (best case P, T and worse case V) 
     Off-corner point D: BC PT+BCV+ΔV (best case P, T and best case V plus a small deviation/perturbation in voltage, ΔV) 
     To give a concrete example, but in no way limiting, for a 90 nm process node (the parameter(s) for a particular process node being shared in common by the base corner library and off-corner points) a best case temperature (BCT) might be a low temperature such as −40 C, while a worse case temperature (WCT) might be a high temperature such as 125 C, while a best case voltage (BCV) might be a high voltage like using the supply voltage plus 10%, i.e., VDD+10%, while a worse case voltage (WCV) might be a low voltage like using the supply voltage minus 10%, i.e., VDD−10%. The off-corner points A, C, above, involving the worse case for temperature and voltage, are termed “far” points to the base corner, while the off-corner points B, D above, involving the best case for temperature and voltage, and a small perturbation Δ as shown, are termed the “near” points to the base corner. The above values for near and far points are only illustrative and not limiting. For example, the near point temperature might be slightly higher than the nominal temperature yet still be considered a near point. For instance, say the nominal base case temperature is 25 C; the far point temperature might be 125 C, which is hot and deleterious long term, while the near point temperature might be say 35 C, slightly higher than the nominal base case temperature. Yet the nomenclature of “near” and “far” would still hold. 
     The far off-corner points are used mainly for legacy purposes for enabling computation using libraries and methodologies from larger process nodes (i.e., using libraries and calculations from 130 nm in a 90 nm process), while the near off-corner points are used mainly for present processes. 
     Off-corner points are likewise chosen for the other remaining base corners, i.e. in the example herein for base corners NOM PVT and WC PVT. Hence these off-corner points would be as follows: 
     For the NOM PVT (Nominal P, V and T) base corner: 
     Off-corner point A 2 : NOM PV+WCT (nominal P, V and worse case T) 
     Off-corner point B 2 : NOM PV+BCT+ΔT (nominal P, V and best case T plus a small deviation/perturbation temperature, ΔT) 
     Off-corner point C 2 : NOM PT+WCV (nominal P, T and worse case V) 
     Off-corner point D 2 : NOM PT+BCV+ΔV (nominal P, T and best case V plus a small deviation/perturbation voltage, ΔV) 
     The off-corner “far” points above would be A 2 , C 2 , while the off-corner “near” points would be B 2 , D 2 . 
     For the WC PVT (Worse case P, V and T) base corner: 
     Off-corner point A 3 : WC PV+WCT+ΔT (worse case P, V and worse case T plus a small deviation/perturbation temperature, ΔT) 
     Off-corner point B 3 : WC PV+BCT (worse case P, V and best case T) 
     Off-corner point C 3 : WC PT+WCV+ΔV (worse case P, T and worse case V plus a small deviation/perturbation voltage, ΔV) 
     Off-corner point D 3 : WC PT+BCV (worse case P, T and best case V). 
     The off-corner “far” points above would be B 3 , D 3 , while the off-corner “near” points would be C 3 , A 3 . 
     The above example for off-corner points and particular base corners are representative rather than limiting, and other base corners and off-corner points may be chosen by one of ordinary skill from the teachings herein. 
     Next, in step  115  in  FIG. 1 , at the box labeled “Build Libraries At 3 Base Corners, Calculate 4 K Derating Factors At Near And Far End Of The Base Corner VT”, using the methodology of the present invention, as implemented by suitable computer hardware, one will build libraries associated with the circuit components at the three base corners (in our example BC PVT, NOM PVT and WC PVT). Libraries may be built using standard off-the-shelf third party programs, as is known per se, including but not limited to NanoChar, and SPICE or HSPICE by Synopysis. 
     Further, at step  115 , the K derating factors are computed for the off-corner points for all the near and far points, for every two sets of off-corner points as described herein, for each of the three base corners. The two sets of derating K factors are calculated for each base corner using eq. (1) and (2) as described in the background of the invention, and the methodology of the &#39;048 and &#39;297 patents. 
     Next, in step  120  of the box in  FIG. 1  labeled “Build Libraries At Off Corners Using K Factors With VT Near The Base Corner Library”, the results from step  115  are used to build libraries, using commercial off-the-shelf programs including but not limited to SPICE, using the K factors and using the near off-corner points for V, T, as explained herein. From a SPICE correlation result it was found that that accuracy improved by two-fold over prior techniques, as explained more fully in  FIG. 2 . 
     Finally, in step  125  of the box of  FIG. 1  labeled “Do Delay Calculation And Deratings Using K Factors With VT Near the Base Corner Library”, the K factors are used from step  115 , as explained and derived herein, to help compute delay calculations for the near off-corner points for V, T for the delay in the ASIC under consideration. 
     Numerous base corners may be chosen, as can be appreciated by one of of ordinary skill in the art; the examples given in a preferred embodiment herein are merely illustrative. 
     Turning attention now to  FIG. 2 , there is shown data illustrating the improvement in performance over prior techniques in accordance with the present invention. As indicated herein, when comparing SPICE calculations up to a two-fold improvement in accuracy is possible over prior techniques. Further, an experiment was performed to test the accuracy of the present invention, and summarized in  FIG. 2 , where the rise timing delay for a cell termed “nd2m1d” was found, the A to Z rise timing delay from data in the present assignee&#39;s LSI Glxd 13 nm technology. For an off-corner consisting of WC PV+BC T, the data of columns labeled % Diff 1  and % Diff 2  in  FIG. 2  show the accuracy of the delay number with respect to a so-called “golden characterization number”. The golden characterization number value is the exact value that would be computed by a “golden” (or exact) simulator like HSPICE, and this is the value that is being predicted by the model of the present invention. In  FIG. 2 , the column % Diff 1  is using the K factors obtained near the base corner WC PVT, while the column % Diff 2  is using the K factors obtained from near the off-corner WC PV+BT. Generally these percentage differences in accuracy are very satisfactory, given the time constraints. 
     In addition, the two sets of deratings factors for each off-corner are also good for calculating not only the propagation delays and output slew rates, but are also good for computing setup and hold times; collectively termed delay for the ASIC being constructed in accordance with the present invention. 
     Although the present invention has been described in terms of the preferred embodiments above, numerous modifications and/or additions to the above-described preferred embodiments would be readily apparent to one skilled in the art. 
     It is intended that the scope of the present invention extends to all such modifications and/or additions and that the scope of the present invention is limited solely by the claims set forth below.