Patent Publication Number: US-10761757-B2

Title: Apparatus and method for coherent, accelerated conversion between data representations

Description:
BACKGROUND 
     Field of the Invention 
     The embodiments of the invention relate generally to the field of computer processors. More particularly, the embodiments relate to an apparatus and method for coherent, accelerated conversion between data representations. 
     Description of the Related Art 
     Deep Learning workloads often progress through various phases, each benefiting from a different numeric representation for tensor data elements. Generally, some phases of the workload processing need less precision and can be performed with smaller element sizes while other phases need higher precision and utilize larger element sizes. Typically, tensor operations-per-second (TOPS) scales inversely with element size—so working with smaller (i.e. lower precision) elements results in higher TOPS. 
     However, when tensor data transitions from phase to phase, numeric representation conversion is necessary. The conversion is traditionally handled by software, which can impact performance. Furthermore, the conversion process involves more than just manipulation of individual tensor elements, as the overall tensor has a defined (and often multi-dimensional) structure that needs to be preserved. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which: 
         FIGS. 1A and 1B  are block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof according to embodiments of the invention; 
         FIGS. 2A-C  are block diagrams illustrating an exemplary VEX instruction format according to embodiments of the invention; 
         FIG. 3  is a block diagram of a register architecture according to one embodiment of the invention; and 
         FIG. 4A  is a block diagram illustrating both an exemplary in-order fetch, decode, retire pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention; 
         FIG. 4B  is a block diagram illustrating both an exemplary embodiment of an in-order fetch, decode, retire core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention; 
         FIG. 5A  is a block diagram of a single processor core, along with its connection to an on-die interconnect network; 
         FIG. 5B  illustrates an expanded view of part of the processor core in  FIG. 5A  according to embodiments of the invention; 
         FIG. 6  is a block diagram of a single core processor and a multicore processor with integrated memory controller and graphics according to embodiments of the invention; 
         FIG. 7  illustrates a block diagram of a system in accordance with one embodiment of the present invention; 
         FIG. 8  illustrates a block diagram of a second system in accordance with an embodiment of the present invention; 
         FIG. 9  illustrates a block diagram of a third system in accordance with an embodiment of the present invention; 
         FIG. 10  illustrates a block diagram of a system on a chip (SoC) in accordance with an embodiment of the present invention; 
         FIG. 11  illustrates a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention; 
         FIGS. 12A-B  illustrate different processor architectures on which embodiments of the invention may be implemented; 
         FIGS. 13-18  illustrate the operation of different embodiments of a tensor conversion instruction for up-converting tensor data elements; 
         FIGS. 19-24  illustrates the operation of different embodiments of a tensor conversion instruction for down-converting tensor data elements; and 
         FIG. 25  illustrates a method in accordance with one embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. It will be apparent, however, to one skilled in the art that the embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments of the invention. 
     Exemplary Processor Architectures, Instruction Formats, and Data Types 
     An instruction set includes one or more instruction formats. A given instruction format defines various fields (number of bits, location of bits) to specify, among other things, the operation to be performed (opcode) and the operand(s) on which that operation is to be performed. Some instruction formats are further broken down though the definition of instruction templates (or subformats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format&#39;s fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands. 
     Embodiments of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed. 
     Generic Vector Friendly Instruction Format 
     A vector friendly instruction format is an instruction format that is suited for vector instructions (e.g., there are certain fields specific to vector operations). While embodiments are described in which both vector and scalar operations are supported through the vector friendly instruction format, alternative embodiments use only vector operations the vector friendly instruction format. 
       FIGS. 1A-1B  are block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof according to embodiments of the invention.  FIG. 1A  is a block diagram illustrating a generic vector friendly instruction format and class A instruction templates thereof according to embodiments of the invention; while  FIG. 1B  is a block diagram illustrating the generic vector friendly instruction format and class B instruction templates thereof according to embodiments of the invention. Specifically, a generic vector friendly instruction format  100  for which are defined class A and class B instruction templates, both of which include no memory access  105  instruction templates and memory access  120  instruction templates. The term generic in the context of the vector friendly instruction format refers to the instruction format not being tied to any specific instruction set. 
     While embodiments of the invention will be described in which the vector friendly instruction format supports the following: a 64 byte vector operand length (or size) with 32 bit (4 byte) or 64 bit (8 byte) data element widths (or sizes) (and thus, a 64 byte vector consists of either 16 doubleword-size elements or alternatively, 8 quadword-size elements); a 64 byte vector operand length (or size) with 16 bit (2 byte) or 8 bit (1 byte) data element widths (or sizes); a 32 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); and a 16 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); alternative embodiments may support more, less and/or different vector operand sizes (e.g., 256 byte vector operands) with more, less, or different data element widths (e.g., 128 bit (16 byte) data element widths). 
     The class A instruction templates in  FIG. 1A  include: 1) within the no memory access  105  instruction templates there is shown a no memory access, full round control type operation  110  instruction template and a no memory access, data transform type operation  115  instruction template; and 2) within the memory access  120  instruction templates there is shown a memory access, temporal  125  instruction template and a memory access, non-temporal  130  instruction template. The class B instruction templates in  FIG. 1B  include: 1) within the no memory access  105  instruction templates there is shown a no memory access, write mask control, partial round control type operation  112  instruction template and a no memory access, write mask control, vsize type operation  117  instruction template; and 2) within the memory access  120  instruction templates there is shown a memory access, write mask control  127  instruction template. 
     The generic vector friendly instruction format  100  includes the following fields listed below in the order illustrated in  FIGS. 1A-1B . 
     Format field  140 —a specific value (an instruction format identifier value) in this field uniquely identifies the vector friendly instruction format, and thus occurrences of instructions in the vector friendly instruction format in instruction streams. As such, this field is optional in the sense that it is not needed for an instruction set that has only the generic vector friendly instruction format. 
     Base operation field  142 —its content distinguishes different base operations. 
     Register index field  144 —its content, directly or through address generation, specifies the locations of the source and destination operands, be they in registers or in memory. These include a sufficient number of bits to select N registers from a P×Q (e.g. 32×512, 16×128, 32×1024, 64×1024) register file. While in one embodiment N may be up to three sources and one destination register, alternative embodiments may support more or less sources and destination registers (e.g., may support up to two sources where one of these sources also acts as the destination, may support up to three sources where one of these sources also acts as the destination, may support up to two sources and one destination). 
     Modifier field  146 —its content distinguishes occurrences of instructions in the generic vector instruction format that specify memory access from those that do not; that is, between no memory access  105  instruction templates and memory access  120  instruction templates. Memory access operations read and/or write to the memory hierarchy (in some cases specifying the source and/or destination addresses using values in registers), while non-memory access operations do not (e.g., the source and destinations are registers). While in one embodiment this field also selects between three different ways to perform memory address calculations, alternative embodiments may support more, less, or different ways to perform memory address calculations. 
     Augmentation operation field  150 —its content distinguishes which one of a variety of different operations to be performed in addition to the base operation. This field is context specific. In one embodiment of the invention, this field is divided into a class field  168 , an alpha field  152 , and a beta field  154 . The augmentation operation field  150  allows common groups of operations to be performed in a single instruction rather than 2, 3, or 4 instructions. 
     Scale field  160 —its content allows for the scaling of the index field&#39;s content for memory address generation (e.g., for address generation that uses 2 scale *index+base). 
     Displacement Field  162 A—its content is used as part of memory address generation (e.g., for address generation that uses 2 scale *index+base+displacement). 
     Displacement Factor Field  1628  (note that the juxtaposition of displacement field  162 A directly over displacement factor field  1628  indicates one or the other is used)—its content is used as part of address generation; it specifies a displacement factor that is to be scaled by the size of a memory access (N)—where N is the number of bytes in the memory access (e.g., for address generation that uses 2 scale *index+base+scaled displacement). Redundant low-order bits are ignored and hence, the displacement factor field&#39;s content is multiplied by the memory operands total size (N) in order to generate the final displacement to be used in calculating an effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field  174  (described later herein) and the data manipulation field  154 C. The displacement field  162 A and the displacement factor field  162 B are optional in the sense that they are not used for the no memory access  105  instruction templates and/or different embodiments may implement only one or none of the two. 
     Data element width field  164 —its content distinguishes which one of a number of data element widths is to be used (in some embodiments for all instructions; in other embodiments for only some of the instructions). This field is optional in the sense that it is not needed if only one data element width is supported and/or data element widths are supported using some aspect of the opcodes. 
     Write mask field  170 —its content controls, on a per data element position basis, whether that data element position in the destination vector operand reflects the result of the base operation and augmentation operation. Class A instruction templates support merging-writemasking, while class B instruction templates support both merging- and zeroing-writemasking. When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one embodiment, preserving the old value of each element of the destination where the corresponding mask bit has a 0. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, an element of the destination is set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the write mask field  170  allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While embodiments of the invention are described in which the write mask field&#39;s  170  content selects one of a number of write mask registers that contains the write mask to be used (and thus the write mask field&#39;s  170  content indirectly identifies that masking to be performed), alternative embodiments instead or additional allow the mask write field&#39;s  170  content to directly specify the masking to be performed. 
     Immediate field  172 —its content allows for the specification of an immediate. This field is optional in the sense that is it not present in an implementation of the generic vector friendly format that does not support immediate and it is not present in instructions that do not use an immediate. 
     Class field  168 —its content distinguishes between different classes of instructions. With reference to  FIGS. 1A-B , the contents of this field select between class A and class B instructions. In  FIGS. 1A-B , rounded corner squares are used to indicate a specific value is present in a field (e.g., class A  168 A and class B  168 B for the class field  168  respectively in  FIGS. 1A-B ). 
     Instruction Templates of Class A 
     In the case of the non-memory access  105  instruction templates of class A, the alpha field  152  is interpreted as an RS field  152 A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round  152 A. 1  and data transform  152 A. 2  are respectively specified for the no memory access, round type operation  110  and the no memory access, data transform type operation  115  instruction templates), while the beta field  154  distinguishes which of the operations of the specified type is to be performed. In the no memory access  105  instruction templates, the scale field  160 , the displacement field  162 A, and the displacement scale filed  162 B are not present. 
     No-Memory Access Instruction Templates—Full Round Control Type Operation 
     In the no memory access full round control type operation  110  instruction template, the beta field  154  is interpreted as a round control field  154 A, whose content(s) provide static rounding. While in the described embodiments of the invention the round control field  154 A includes a suppress all floating point exceptions (SAE) field  156  and a round operation control field  158 , alternative embodiments may support may encode both these concepts into the same field or only have one or the other of these concepts/fields (e.g., may have only the round operation control field  158 ). 
     SAE field  156 —its content distinguishes whether or not to disable the exception event reporting; when the SAE field&#39;s  156  content indicates suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler. 
     Round operation control field  158 —its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field  158  allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the invention where a processor includes a control register for specifying rounding modes, the round operation control field&#39;s  150  content overrides that register value. 
     No Memory Access Instruction Templates—Data Transform Type Operation 
     In the no memory access data transform type operation  115  instruction template, the beta field  154  is interpreted as a data transform field  1546 , whose content distinguishes which one of a number of data transforms is to be performed (e.g., no data transform, swizzle, broadcast). 
     In the case of a memory access  120  instruction template of class A, the alpha field  152  is interpreted as an eviction hint field  152 B, whose content distinguishes which one of the eviction hints is to be used (in  FIG. 1A , temporal  152 B. 1  and non-temporal  152 B. 2  are respectively specified for the memory access, temporal  125  instruction template and the memory access, non-temporal  130  instruction template), while the beta field  154  is interpreted as a data manipulation field  154 C, whose content distinguishes which one of a number of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation; broadcast; up conversion of a source; and down conversion of a destination). The memory access  120  instruction templates include the scale field  160 , and optionally the displacement field  162 A or the displacement scale field  162 B. 
     Vector memory instructions perform vector loads from and vector stores to memory, with conversion support. As with regular vector instructions, vector memory instructions transfer data from/to memory in a data element-wise fashion, with the elements that are actually transferred is dictated by the contents of the vector mask that is selected as the write mask. 
     Memory Access Instruction Templates—Temporal 
     Temporal data is data likely to be reused soon enough to benefit from caching. This is, however, a hint, and different processors may implement it in different ways, including ignoring the hint entirely. 
     Memory Access Instruction Templates—Non-Temporal 
     Non-temporal data is data unlikely to be reused soon enough to benefit from caching in the 1st-level cache and should be given priority for eviction. This is, however, a hint, and different processors may implement it in different ways, including ignoring the hint entirely. 
     Instruction Templates of Class B 
     In the case of the instruction templates of class B, the alpha field  152  is interpreted as a write mask control (Z) field  152 C, whose content distinguishes whether the write masking controlled by the write mask field  170  should be a merging or a zeroing. 
     In the case of the non-memory access  105  instruction templates of class B, part of the beta field  154  is interpreted as an RL field  157 A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round  157 A. 1  and vector length (VSIZE)  157 A. 2  are respectively specified for the no memory access, write mask control, partial round control type operation  112  instruction template and the no memory access, write mask control, VSIZE type operation  117  instruction template), while the rest of the beta field  154  distinguishes which of the operations of the specified type is to be performed. In the no memory access  105  instruction templates, the scale field  160 , the displacement field  162 A, and the displacement scale filed  162 B are not present. 
     In the no memory access, write mask control, partial round control type operation  110  instruction template, the rest of the beta field  154  is interpreted as a round operation field  159 A and exception event reporting is disabled (a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler). 
     Round operation control field  159 A—just as round operation control field  158 , its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field  159 A allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the invention where a processor includes a control register for specifying rounding modes, the round operation control field&#39;s  150  content overrides that register value. 
     In the no memory access, write mask control, VSIZE type operation  117  instruction template, the rest of the beta field  154  is interpreted as a vector length field  159 B, whose content distinguishes which one of a number of data vector lengths is to be performed on (e.g., 128, 256, or 512 byte). 
     In the case of a memory access  120  instruction template of class B, part of the beta field  154  is interpreted as a broadcast field  157 B, whose content distinguishes whether or not the broadcast type data manipulation operation is to be performed, while the rest of the beta field  154  is interpreted the vector length field  159 B. The memory access  120  instruction templates include the scale field  160 , and optionally the displacement field  162 A or the displacement scale field  162 B. 
     With regard to the generic vector friendly instruction format  100 , a full opcode field  174  is shown including the format field  140 , the base operation field  142 , and the data element width field  164 . While one embodiment is shown where the full opcode field  174  includes all of these fields, the full opcode field  174  includes less than all of these fields in embodiments that do not support all of them. The full opcode field  174  provides the operation code (opcode). 
     The augmentation operation field  150 , the data element width field  164 , and the write mask field  170  allow these features to be specified on a per instruction basis in the generic vector friendly instruction format. 
     The combination of write mask field and data element width field create typed instructions in that they allow the mask to be applied based on different data element widths. 
     The various instruction templates found within class A and class B are beneficial in different situations. In some embodiments of the invention, different processors or different cores within a processor may support only class A, only class B, or both classes. For instance, a high performance general purpose out-of-order core intended for general-purpose computing may support only class B, a core intended primarily for graphics and/or scientific (throughput) computing may support only class A, and a core intended for both may support both (of course, a core that has some mix of templates and instructions from both classes but not all templates and instructions from both classes is within the purview of the invention). Also, a single processor may include multiple cores, all of which support the same class or in which different cores support different class. For instance, in a processor with separate graphics and general purpose cores, one of the graphics cores intended primarily for graphics and/or scientific computing may support only class A, while one or more of the general purpose cores may be high performance general purpose cores with out of order execution and register renaming intended for general-purpose computing that support only class B. Another processor that does not have a separate graphics core, may include one more general purpose in-order or out-of-order cores that support both class A and class B. Of course, features from one class may also be implement in the other class in different embodiments of the invention. Programs written in a high level language would be put (e.g., just in time compiled or statically compiled) into an variety of different executable forms, including: 1) a form having only instructions of the class(es) supported by the target processor for execution; or 2) a form having alternative routines written using different combinations of the instructions of all classes and having control flow code that selects the routines to execute based on the instructions supported by the processor which is currently executing the code. 
     VEX Instruction Format 
     VEX encoding allows instructions to have more than two operands, and allows SIMD vector registers to be longer than 28 bits. The use of a VEX prefix provides for three-operand (or more) syntax. For example, previous two-operand instructions performed operations such as A=A+B, which overwrites a source operand. The use of a VEX prefix enables operands to perform nondestructive operations such as A=B+C. 
       FIG. 2A  illustrates an exemplary AVX instruction format including a VEX prefix  202 , real opcode field  230 , Mod R/M byte  240 , SIB byte  250 , displacement field  262 , and IMM8  272 .  FIG. 2B  illustrates which fields from  FIG. 2A  make up a full opcode field  274  and a base operation field  241 .  FIG. 2C  illustrates which fields from  FIG. 2A  make up a register index field  244 . 
     VEX Prefix (Bytes 0-2)  202  is encoded in a three-byte form. The first byte is the Format Field  290  (VEX Byte 0, bits [7:0]), which contains an explicit C4 byte value (the unique value used for distinguishing the C4 instruction format). The second-third bytes (VEX Bytes 1-2) include a number of bit fields providing specific capability. Specifically, REX field  205  (VEX Byte 1, bits [7-5]) consists of a VEX.R bit field (VEX Byte 1, bit [7]-R), VEX.X bit field (VEX byte 1, bit [6]-X), and VEX.B bit field (VEX byte 1, bit[5]-B). Other fields of the instructions encode the lower three bits of the register indexes as is known in the art (rrr, xxx, and bbb), so that Rrrr, Xxxx, and Bbbb may be formed by adding VEX.R, VEX.X, and VEX.B. Opcode map field  215  (VEX byte 1, bits [4:0]-mmmmm) includes content to encode an implied leading opcode byte. W Field  264  (VEX byte 2, bit [ 7 ]-W)—is represented by the notation VEX.W, and provides different functions depending on the instruction. The role of VEX.vvvv  220  (VEX Byte 2, bits [6:3]-vvvv) may include the following: 1) VEX.vvvv encodes the first source register operand, specified in inverted (1s complement) form and is valid for instructions with 2 or more source operands; 2) VEX.vvvv encodes the destination register operand, specified in 1s complement form for certain vector shifts; or 3) VEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. If VEX.L  268  Size field (VEX byte 2, bit [2]-L)=0, it indicates 28 bit vector; if VEX.L=1, it indicates 256 bit vector. Prefix encoding field  225  (VEX byte 2, bits [1:0]-pp) provides additional bits for the base operation field  241 . 
     Real Opcode Field  230  (Byte 3) is also known as the opcode byte. Part of the opcode is specified in this field. 
     MOD R/M Field  240  (Byte 4) includes MOD field  242  (bits [7-6]), Reg field  244  (bits [5-3]), and R/M field  246  (bits [2-0]). The role of Reg field  244  may include the following: encoding either the destination register operand or a source register operand (the rrr of Rrrr), or be treated as an opcode extension and not used to encode any instruction operand. The role of R/M field  246  may include the following: encoding the instruction operand that references a memory address, or encoding either the destination register operand or a source register operand. 
     Scale, Index, Base (SIB)—The content of Scale field  250  (Byte 5) includes SS 252  (bits [7-6]), which is used for memory address generation. The contents of SIB.xxx  254  (bits [5-3]) and SIB.bbb  256  (bits [2-0]) have been previously referred to with regard to the register indexes Xxxx and Bbbb. 
     The Displacement Field  262  and the immediate field (IMM8)  272  contain data. 
     Exemplary Register Architecture 
       FIG. 3  is a block diagram of a register architecture  300  according to one embodiment of the invention. In the embodiment illustrated, there are 32 vector registers  310  that are 512 bits wide; these registers are referenced as zmm0 through zmm31. The lower order 256 bits of the lower 6 zmm registers are overlaid on registers ymm0-15. The lower order 128 bits of the lower 6 zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15. 
     General-purpose registers  325 —in the embodiment illustrated, there are sixteen 64-bit general-purpose registers that are used along with the existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R 8  through R 15 . 
     Scalar floating point stack register file (x87 stack)  345 , on which is aliased the MMX packed integer flat register file  350 —in the embodiment illustrated, the x87 stack is an eight-element stack used to perform scalar floating-point operations on 32/64/80-bit floating point data using the x87 instruction set extension; while the MMX registers are used to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers. 
     Alternative embodiments of the invention may use wider or narrower registers. Additionally, alternative embodiments of the invention may use more, less, or different register files and registers. 
     Exemplary Core Architectures, Processors, and Computer Architectures 
     Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high performance general purpose out-of-order core intended for general-purpose computing; 3) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures. Detailed herein are circuits (units) that comprise exemplary cores, processors, etc. 
     Exemplary Core Architectures 
       FIG. 4A  is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention.  FIG. 4B  is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention. The solid lined boxes in  FIGS. 4A-B  illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described. 
     In  FIG. 4A , a processor pipeline  400  includes a fetch stage  402 , a length decode stage  404 , a decode stage  406 , an allocation stage  408 , a renaming stage  410 , a scheduling (also known as a dispatch or issue) stage  412 , a register read/memory read stage  414 , an execute stage  416 , a write back/memory write stage  418 , an exception handling stage  422 , and a commit stage  424 . 
       FIG. 4B  shows processor core  490  including a front end unit  430  coupled to an execution engine unit  450 , and both are coupled to a memory unit  470 . The core  490  may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core  490  may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like. 
     The front end unit  430  includes a branch prediction unit  432  coupled to an instruction cache unit  434 , which is coupled to an instruction translation lookaside buffer (TLB)  436 , which is coupled to an instruction fetch unit  438 , which is coupled to a decode unit  440 . The decode unit  440  (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit  440  may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core  490  includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit  440  or otherwise within the front end unit  430 ). The decode unit  440  is coupled to a rename/allocator unit  452  in the execution engine unit  450 . 
     The execution engine unit  450  includes the rename/allocator unit  452  coupled to a retirement unit  454  and a set of one or more scheduler unit(s)  456 . The scheduler unit(s)  456  represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s)  456  is coupled to the physical register file(s) unit(s)  458 . Each of the physical register file(s) units  458  represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit  458  comprises a vector registers unit and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s)  458  is overlapped by the retirement unit  454  to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit  454  and the physical register file(s) unit(s)  458  are coupled to the execution cluster(s)  460 . The execution cluster(s)  460  includes a set of one or more execution units  462  and a set of one or more memory access units  464 . The execution units  462  may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)  456 , physical register file(s) unit(s)  458 , and execution cluster(s)  460  are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s)  464 ). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order. 
     The set of memory access units  464  is coupled to the memory unit  470 , which includes a data TLB unit  472  coupled to a data cache unit  474  coupled to a level 2 (L2) cache unit  476 . In one exemplary embodiment, the memory access units  464  may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit  472  in the memory unit  470 . The instruction cache unit  434  is further coupled to a level 2 (L2) cache unit  476  in the memory unit  470 . The L2 cache unit  476  is coupled to one or more other levels of cache and eventually to a main memory. 
     By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline  400  as follows: 1) the instruction fetch  438  performs the fetch and length decoding stages  402  and  404 ; 2) the decode unit  440  performs the decode stage  406 ; 3) the rename/allocator unit  452  performs the allocation stage  408  and renaming stage  410 ; 4) the scheduler unit(s)  456  performs the schedule stage  412 ; 5) the physical register file(s) unit(s)  458  and the memory unit  470  perform the register read/memory read stage  414 ; the execution cluster  460  perform the execute stage  416 ; 6) the memory unit  470  and the physical register file(s) unit(s)  458  perform the write back/memory write stage  418 ; 7) various units may be involved in the exception handling stage  422 ; and 8) the retirement unit  454  and the physical register file(s) unit(s)  458  perform the commit stage  424 . 
     The core  490  may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.), including the instruction(s) described herein. In one embodiment, the core  490  includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data. 
     It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyperthreading technology). 
     While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units  434 / 474  and a shared L2 cache unit  476 , alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor. 
     Specific Exemplary In-Order Core Architecture 
       FIGS. 5A-B  illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip. The logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with some fixed function logic, memory I/O interfaces, and other necessary I/O logic, depending on the application. 
       FIG. 5A  is a block diagram of a single processor core, along with its connection to the on-die interconnect network  502  and with its local subset of the Level 2 (L2) cache  504 , according to embodiments of the invention. In one embodiment, an instruction decoder  500  supports the x86 instruction set with a packed data instruction set extension. An L1 cache  506  allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit  508  and a vector unit  510  use separate register sets (respectively, scalar registers  512  and vector registers  514 ) and data transferred between them is written to memory and then read back in from a level 1 (L1) cache  506 , alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back). 
     The local subset of the L2 cache  504  is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache  504 . Data read by a processor core is stored in its L2 cache subset  504  and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset  504  and is flushed from other subsets, if necessary. The ring network ensures coherency for shared data. The ring network is bi-directional to allow agents such as processor cores, L2 caches and other logic blocks to communicate with each other within the chip. Each ring data-path is 1024-bits wide per direction in some embodiments. 
       FIG. 5B  is an expanded view of part of the processor core in  FIG. 5A  according to embodiments of the invention.  FIG. 5B  includes an L1 data cache  506 A part of the L1 cache  504 , as well as more detail regarding the vector unit  510  and the vector registers  514 . Specifically, the vector unit  510  is a 6-wide vector processing unit (VPU) (see the 16-wide ALU  528 ), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit  520 , numeric conversion with numeric convert units  522 A-B, and replication with replication unit  524  on the memory input. 
     Processor with Integrated Memory Controller and Graphics 
       FIG. 6  is a block diagram of a processor  600  that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention. The solid lined boxes in  FIG. 6  illustrate a processor  600  with a single core  602 A, a system agent  610 , a set of one or more bus controller units  616 , while the optional addition of the dashed lined boxes illustrates an alternative processor  600  with multiple cores  602 A-N, a set of one or more integrated memory controller unit(s)  614  in the system agent unit  610 , and special purpose logic  608 . 
     Thus, different implementations of the processor  600  may include: 1) a CPU with the special purpose logic  608  being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores  602 A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with the cores  602 A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores  602 A-N being a large number of general purpose in-order cores. Thus, the processor  600  may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor  600  may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS. 
     The memory hierarchy includes one or more levels of cache within the cores  604 A-N, a set or one or more shared cache units  606 , and external memory (not shown) coupled to the set of integrated memory controller units  614 . The set of shared cache units  606  may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit  612  interconnects the integrated graphics logic  608 , the set of shared cache units  606 , and the system agent unit  610 /integrated memory controller unit(s)  614 , alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units  606  and cores  602 -A-N. 
     In some embodiments, one or more of the cores  602 A-N are capable of multi-threading. The system agent  610  includes those components coordinating and operating cores  602 A-N. The system agent unit  610  may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores  602 A-N and the integrated graphics logic  608 . The display unit is for driving one or more externally connected displays. 
     The cores  602 A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores  602 A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set. 
     Exemplary Computer Architectures 
       FIGS. 7-10  are block diagrams of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable. 
     Referring now to  FIG. 7 , shown is a block diagram of a system  700  in accordance with one embodiment of the present invention. The system  700  may include one or more processors  710 ,  715 , which are coupled to a controller hub  720 . In one embodiment, the controller hub  720  includes a graphics memory controller hub (GMCH)  790  and an Input/Output Hub (IOH)  750  (which may be on separate chips); the GMCH  790  includes memory and graphics controllers to which are coupled memory  740  and a coprocessor  745 ; the IOH  750  is couples input/output (I/O) devices  760  to the GMCH  790 . Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory  740  and the coprocessor  745  are coupled directly to the processor  710 , and the controller hub  720  in a single chip with the IOH  750 . 
     The optional nature of additional processors  715  is denoted in  FIG. 7  with broken lines. Each processor  710 ,  715  may include one or more of the processing cores described herein and may be some version of the processor  600 . 
     The memory  740  may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub  720  communicates with the processor(s)  710 ,  715  via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface, or similar connection  795 . 
     In one embodiment, the coprocessor  745  is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub  720  may include an integrated graphics accelerator. 
     There can be a variety of differences between the physical resources  710 ,  7155  in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. 
     In one embodiment, the processor  710  executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor  710  recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor  745 . Accordingly, the processor  710  issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor  745 . Coprocessor(s)  745  accept and execute the received coprocessor instructions. 
     Referring now to  FIG. 8 , shown is a block diagram of a first more specific exemplary system  800  in accordance with an embodiment of the present invention. As shown in  FIG. 8 , multiprocessor system  800  is a point-to-point interconnect system, and includes a first processor  870  and a second processor  880  coupled via a point-to-point interconnect  850 . Each of processors  870  and  880  may be some version of the processor  600 . In one embodiment of the invention, processors  870  and  880  are respectively processors  710  and  715 , while coprocessor  838  is coprocessor  745 . In another embodiment, processors  870  and  880  are respectively processor  710  coprocessor  745 . 
     Processors  870  and  880  are shown including integrated memory controller (IMC) units  872  and  882 , respectively. Processor  870  also includes as part of its bus controller units point-to-point (P-P) interfaces  876  and  878 ; similarly, second processor  880  includes P-P interfaces  886  and  888 . Processors  870 ,  880  may exchange information via a point-to-point (P-P) interface  850  using P-P interface circuits  878 ,  888 . As shown in  FIG. 8 , IMCs  872  and  882  couple the processors to respective memories, namely a memory  832  and a memory  834 , which may be portions of main memory locally attached to the respective processors. 
     Processors  870 ,  880  may each exchange information with a chipset  890  via individual P-P interfaces  852 ,  854  using point to point interface circuits  876 ,  894 ,  886 ,  898 . Chipset  890  may optionally exchange information with the coprocessor  838  via a high-performance interface  892 . In one embodiment, the coprocessor  838  is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. 
     A shared cache (not shown) may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors&#39; local cache information may be stored in the shared cache if a processor is placed into a low power mode. 
     Chipset  890  may be coupled to a first bus  816  via an interface  896 . In one embodiment, first bus  816  may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another I/O interconnect bus, although the scope of the present invention is not so limited. 
     As shown in  FIG. 8 , various I/O devices  814  may be coupled to first bus  816 , along with a bus bridge  818  which couples first bus  816  to a second bus  820 . In one embodiment, one or more additional processor(s)  815 , such as coprocessors, high-throughput MIC processors, GPGPU&#39;s, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus  816 . In one embodiment, second bus  820  may be a low pin count (LPC) bus. Various devices may be coupled to a second bus  820  including, for example, a keyboard and/or mouse  822 , communication devices  827  and a storage unit  828  such as a disk drive or other mass storage device which may include instructions/code and data  830 , in one embodiment. Further, an audio I/O  824  may be coupled to the second bus  816 . Note that other architectures are possible. For example, instead of the point-to-point architecture of  FIG. 8 , a system may implement a multi-drop bus or other such architecture. 
     Referring now to  FIG. 9 , shown is a block diagram of a second more specific exemplary system  900  in accordance with an embodiment of the present invention. Like elements in  FIGS. 8 and 9  bear like reference numerals, and certain aspects of  FIG. 8  have been omitted from  FIG. 9  in order to avoid obscuring other aspects of  FIG. 9 . 
       FIG. 9  illustrates that the processors  870 ,  880  may include integrated memory and I/O control logic (“CL”)  972  and  982 , respectively. Thus, the CL  972 ,  982  include integrated memory controller units and include I/O control logic.  FIG. 9  illustrates that not only are the memories  832 ,  834  coupled to the CL  872 ,  882 , but also that I/O devices  914  are also coupled to the control logic  872 ,  882 . Legacy I/O devices  915  are coupled to the chipset  890 . 
     Referring now to  FIG. 10 , shown is a block diagram of a SoC  1000  in accordance with an embodiment of the present invention. Similar elements in  FIG. 6  bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. In  FIG. 10 , an interconnect unit(s)  1002  is coupled to: an application processor  1010  which includes a set of one or more cores  102 A-N, cache units  604 A-N, and shared cache unit(s)  606 ; a system agent unit  610 ; a bus controller unit(s)  616 ; an integrated memory controller unit(s)  614 ; a set or one or more coprocessors  1020  which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit  1030 ; a direct memory access (DMA) unit  1032 ; and a display unit  1040  for coupling to one or more external displays. In one embodiment, the coprocessor(s)  1020  include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like. 
     Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the invention may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. 
     Program code, such as code  830  illustrated in  FIG. 8 , may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example; a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor. 
     The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language. 
     One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor. 
     Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritable&#39;s (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions. 
     Accordingly, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products. 
     Emulation (Including Binary Translation, Code Morphing, Etc.) 
     In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or part on and part off processor. 
       FIG. 11  is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof.  FIG. 11  shows a program in a high level language  1102  may be compiled using an first compiler  1104  to generate a first binary code (e.g., x86)  1106  that may be natively executed by a processor with at least one first instruction set core  1116 . In some embodiments, the processor with at least one first instruction set core  1116  represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The first compiler  1104  represents a compiler that is operable to generate binary code of the first instruction set  1106  (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one first instruction set core  1116 . Similarly,  FIG. 11  shows the program in the high level language  1102  may be compiled using an alternative instruction set compiler  1108  to generate alternative instruction set binary code  1110  that may be natively executed by a processor without at least one first instruction set core  1114  (e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif. and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.). The instruction converter  1112  is used to convert the first binary code  1106  into code that may be natively executed by the processor without an first instruction set core  1114 . This converted code is not likely to be the same as the alternative instruction set binary code  1110  because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter  1112  represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have a first instruction set processor or core to execute the first binary code  1106 . 
     Apparatus and Method for Coherent, Accelerated Conversion Between Data Representations 
     As mentioned, when tensor data transitions from phase to phase, numeric representation conversion is necessary. The conversion is traditionally handled by software, which can impact performance. 
     One embodiment of the invention includes a new instruction, sometimes referred to herein with the mnemonic CONVNUMERIC, and associated processor circuitry to convert tensor data from one numeric representation to another and maintain structural coherence. A Matrix Processing Unit is integrated within the execution circuitry of the processor for efficiently performing the various tensor operations described herein. One embodiment of the CONVNUMERIC instruction includes software-specified fields indicating the input numeric representation and the desired output numeric representation. Due to possible differences in input/output element sizes, the Matrix Processing Unit may include a buffer to manage differences in required input and output bandwidth. 
       FIGS. 12A and 12B  illustrates example processor architectures on which embodiments of the invention may be implemented. The illustrated architecture includes a core region  1201  and a shared, or “uncore” region  1210 . The shared region  1210  includes data structures and circuitry shared by all or a subset of the cores  1201   a - b . In the illustrated embodiment, the plurality of cores  1201   a - b  are simultaneous multithreaded cores capable of concurrently executing multiple instruction streams or threads. Although only two cores  1201   a - b  are illustrated in  FIG. 12A  for simplicity it will be appreciated that the core region  1201  may include any number of cores, each of which may include the same architecture as shown for Core  1201   a . Another embodiment includes heterogeneous cores (e.g., low power cores combined with high power/performance cores). 
     The various components illustrated in  FIG. 12A  may be implemented in the same manner as corresponding components in  FIGS. 1-11 . For example, the core  1201   a  may execute the CONVNUMERIC instruction using one of the instruction formats in  FIGS. 1 a - b  and 2 a - c   , and/or using the register architecture illustrated in  FIG. 3 . In addition, the cores  1201   a  may include the components of core  490  shown in  FIG. 4 b   , and may include any of the processor/core components described herein (e.g.,  FIGS. 5 a - b   ,  FIG. 6 , etc). 
     Each of the cores  1201   a - b  include instruction pipeline components for performing simultaneous, out-of-order (or in-order) execution of instruction streams including instruction fetch circuitry  1218  which fetches instructions from system memory  1260  or the L1 instruction cache  1210  and decode circuitry  1209  to decode the instructions. Execution circuitry  1208  executes the decoded instructions to perform the underlying operations, as specified by the instruction operands, opcodes, and any immediate values. 
     In the illustrated embodiment, the decode unit  1209  includes CONVNUMERIC decode circuitry  1209   a  to decode the CONVNUMERIC instruction into a plurality of micro-operations which are then executed by a Matrix Processing Unit (MPU)  1208   a  of the execution circuitry  1208 . In one embodiment, the MPU  1208   a  is coupled to a high speed temporary local storage  1208   b  to store conversion results generated by the conversion instruction, prior to storing the results back to the system memory  1260 . While illustrated as a separate unit, the MPU  1208   a  may be implemented by various functional units spread throughout the execution circuitry  1208 . Moreover, although illustrated as a component within the execution circuitry  1208 , the temporary storage (TS)  1208   b  may be implemented within one or more levels of cache (e.g., within the data cache  1202 ), or as a separate high speed memory (e.g., a scratchpad memory), accessible by the execution circuitry  1208  and decode circuitry  1209 . 
     In an alternate embodiment, illustrated in  FIG. 12B , an MPU accelerator  1201   d  is tightly coupled to the processor cores  1201   a - b  over a cache coherent interconnect (e.g., in which the MPU participates in the same set of cache coherent memory transactions as the cores). In this embodiment, the decoders  1209  decode the numeric CONVNUMERIC instructions described herein and the resulting microoperations are passed for execution to the MPU accelerator  1201   b  which performs the numeric conversions described herein with tensor conversion circuitry  1201   e  and a local buffer or memory  1201   f . In one embodiment, the local buffer/memory  1201   f  comprises a cache of the MPU accelerator  1201   d  which participates in the cache coherency protocol implemented by the memory subsystem. In yet another embodiment, the MPU accelerator  1201   d  comprises a dedicated fetch unit and decode unit to fetch the conversion instructions from memory and decode the instructions, respectively. It should be noted, however, that the particular manner in which the MPU is integrated within a processor architecture is not pertinent to the underlying principles of the invention. 
     Also illustrated in  FIGS. 12 a - b    are general purpose registers (GPRs)  1218   d , a set of vector registers  1218   b , a set of mask registers  1218   a , and a set of control registers  1218   c . In one embodiment, multiple vector data elements are packed into each vector register  1206  which may have a 512 bit width for storing two 256 bit values, four 128 bit values, eight 64 bit values, sixteen 32 bit values, etc. However, the underlying principles of the invention are not limited to any particular size/type of vector data. In one embodiment, the mask registers  1207  include eight 64-bit operand mask registers used for performing bit masking operations on the values stored in the vector registers  1206  (e.g., implemented as mask registers k0-k7 described above). However, the underlying principles of the invention are not limited to any particular mask register size/type. 
     The control registers  1218   c  store various types of control bits or “flags” which are used by executing instructions to determine the current state of the processor core  1201   a . By way of example, and not limitation, in an x86 architecture, the control registers include the EFLAGS register. 
     An interconnect  1206  such as an on-die interconnect (IDI) implementing an IDI/coherence protocol communicatively couples the cores  1201   a - b  (and potentially an MPU accelerator  1201   d ) to one another and to various components within the shared region  1210 . For example, the interconnect  1206  couples core  1201   a  via interface  1207  to a level 3 (L3) cache and an integrated memory controller  1230  which couples the processor to a system memory  1260 . 
     The integrated memory controller  1230  provides access to a system memory  1260  when performing memory operations (e.g., such as a MOV from system memory  1260  to a register). One or more input/output (I/O) circuits (not shown) such as PCI express circuitry may also be included in the shared region  1210 . 
     An instruction pointer register  1212  stores an instruction pointer address identifying the next instruction to be fetched, decoded, and executed. Instructions may be fetched or prefetched from system memory  1260  and/or one or more shared cache levels such as an L2 cache  1213 , the shared L3 cache  1220 , or the L1 instruction cache  1210 . In addition, an L1 data cache  1202  stores data loaded from system memory  1260  and/or retrieved from one of the other cache levels  1213 ,  1220  which cache both instructions and data. An instruction TLB (ITLB)  1211  stores virtual address to physical address translations for the instructions fetched by the fetch circuitry  1218  and a data TLB (DTLB)  1203  stores virtual-to-physical address translations for the data processed by the decode circuitry  1209  and execution circuitry  1208 . 
       FIGS. 12A-B  also illustrates a branch prediction unit  1221  for speculatively predicting instruction branch addresses and branch target buffers (BTBs)  1222  for storing branch addresses and target addresses. In one embodiment, a branch history table (not shown) or other data structure is maintained and updated for each branch prediction/misprediction and is used by the branch prediction unit  1221  to make subsequent branch predictions. 
     Note that  FIGS. 12A-B  are not intended to provide a comprehensive view of all circuitry and interconnects employed within a processor. Rather, components which are not pertinent to the embodiments of the invention are not shown. Conversely, some components are shown merely for the purpose of providing an example architecture in which embodiments of the invention may be implemented. 
     Conversion of the numeric representation of tensor data falls into two broad categories. First are the “down-conversion” cases where the incoming number of meaningful significand/mantissa bits per element is greater than the outgoing number of meaningful significand/mantissa bits per element. Second are the “up-conversion” cases where the incoming number of meaningful significand/mantissa bits per element is less than the outgoing number of meaningful significand/mantissa bits per element. Thus, in the context of the present application, up-conversion and down-conversion refer to increasing and decreasing the total bit width of the numeric representation, respectively. 
     Note that up/down conversion is often associated with an increase/decrease in the number of storage bits per element—but not always. For example, converting from a 16-bit fixed point representation to a half-precision floating point representation doesn&#39;t reduce the number of storage bits per element despite being a down-conversion case (i.e., because half precision floating point comprises 16-bit floating point). In cases where conversion changes the number of storage bits per element, some temporary buffering may be required in hardware as described below. 
     Examples of conversions performed by various forms of the CONVNUMERIC instruction are described below with respect to  FIGS. 13-24 . These figures illustrate an example tensor stored in a memory array of width  512   b  to illustrate the memory organization and tensor structure coherence. When converting from a numeric type with fewer bits/element (bpe) to one with greater bpe, the post-conversion data requires more bandwidth than the input data. In some embodiments, a temporary storage such as a buffer or queue is used to improve performance. In all cases, the conversion performed by the MPU  1208   a / 1201   d  involves more than just manipulation of individual tensor elements, as the overall tensor has a defined (and often multi-dimensional) structure which needs to be preserved. 
     The embodiments described below perform the conversions while preserving this coherent structure. For example, in one embodiment, regions of memory are identified for each individual converted tensor block prior to memory storage to ensure proper structural ordering within the overall output tensor data structure. In some cases this may require reserving one or more block-sized gaps in memory between converted tensor blocks to ensure that subsequent converted tensor blocks are stored in the correct structural location. 
     Referring first to  FIG. 13 , two different views of the memory organization for a 1024×1024 matrix are provided for clarity, including a memory array view  1301  and a logical view  1302 . The memory array view  1301  comprises an arrangement having a width of the memory array— 512   b  in the illustrated embodiment—with each tensor block is arranged in a stack from the first (A0,0) to last (A15,15). The logical view  1302  arranges the tensor elements in rows and columns. For example, the first row includes tensor blocks A0,0 to A0,15, the second row (not shown) includes tensor blocks A1,0 to A1,15, and so on. 
       FIGS. 14-24  similarly include both memory array views  1401 ,  1501 ,  1601 ,  1701 ,  1801 ,  1901 ,  2001 ,  2101 ,  2201 ,  2301 ,  2401  and logical views  1402 ,  1502 ,  1602 ,  1702 ,  1802 ,  1902 ,  2002 ,  2102 ,  2202 ,  2302 ,  2402 , respectively, for different conversion instructions for converting between different numeric formats. Note, that these different views are provided merely for the purpose of visualizing the underlying data but are not meant to indicate that an operation is being performed to transition between the views. In addition, each figure illustrates (from the perspective of the logical view), how each individual block of tensor data is converted to the new tensor data format  1304 ,  1404 ,  1504 ,  1604 ,  1704 ,  1804 ,  1904 ,  2004 ,  2104 ,  2204 ,  2304 ,  2404  and also illustrates the memory array view  1305 ,  1405 ,  1505 ,  1605 ,  1705 ,  1805 ,  1905 ,  2005 ,  2105 ,  2205 ,  2305 ,  2405 , respectively, for the converted tensor values. 
     Returning to  FIG. 13 , the memory organization for 8 bpe to 16 bpe conversion is illustrated. The block size of a square tensor stored in a memory array of width  512   b  changes from 64×64 to 32×32. That is, the MPU  1208   a  decomposes each 64×64 8 bpe tensor into four 32×32 16 bpe tensors  1304 , illustrated as blocks (A′0,0), (A′0,1), (A′1,0), and (A′1,1) for tensor block (A0,0). Although not shown for simplicity, the MPU  1208   a  (or  1201   d ) performs similar operations in parallel for each of the remaining elements from (A0,1) to (A15,15). It can be seen here that each of the 32×32 tensors occupies the same storage in memory as the original 64×64 blocks. 
     In one embodiment, in response to the CONVNUMERIC instruction the MPU  1208   a  (or  1201   d ) first receives and stores the entire upper half of A0,0 (32×64) in its temporary storage memory  1208   b , represented as blocks (A′0,0) and (A′0,1) in  FIG. 13 . The MPU  1208   a / 1201   d  then performs multiple conversion passes through the stored data to generate A′0,0 completely followed by A′0,1. As with the input data, both a logical view  1304  and a memory array view  1305  are provided to illustrate the resulting 16 bpe elements. The process continues with the lower half of A0,0 (32×64), with the MPU  1208   a / 1201   d  working in passes to generate A′1,0 completely followed by A′1,1. In one embodiment, the MPU  1208   a / 1201   d  stores the elements within memory array (see, e.g., view  1305 ) with sufficient gaps in memory to store the remaining A′0, * blocks, A′1, * blocks, etc, in sequential order, up to the A′31,31 block. Once original block A0,0 has been processed, the MPU  1208   a / 1201   d  then proceeds to process the 8 bpe A0,1 block, operating on this block in a similar manner. 
     Different down-conversions operations may be executed by the MPU  1208   a / 1201   d  as described below in response to different versions of the CONVNUMERIC instruction. In one embodiment, these different versions are specified in the specific opcode used for the CONVNUMERIC instruction. Alternatively, or in addition, the different versions may be specified using an immediate value and/or based on the specific operands referenced by the instruction. 
       FIG. 14  illustrates an example of the conversion operations performed by the MPU  1208   a / 1201   d  in response to a 16 bpe to 32 bpe CONVNUMERIC instruction. That is, the MPU  1208   a / 1201   d  decomposes each 32×32 16 bpe tensor (once again illustrated in a memory array view  1401  and logical view  1402 ), into four 16×16 32 bpe tensors  1404 , illustrated as blocks (A′0,0), (A′0,1), (A′1,0), and (A′1,1) for tensor block (A0,0). Although not shown for simplicity, the MPU  1208   a / 1201   d  performs similar operations for each of the remaining elements from (A0,1) to (A31,31). It can be seen that each of the 16×16 tensors occupies the same storage in memory as the original 32×32 blocks. 
     In one embodiment, in response to the CONVNUMERIC instruction the MPU  1208   a / 1201   d  first receives and stores the entire upper half of A0,0 (16×32) in its temporary storage memory  1208   b , represented as blocks (A′0,0) and (A′0,1) in  FIG. 14 . The MPU  1208   a / 1201   d  then performs multiple conversion passes through the stored data to generate A′0,0 completely followed by A′0,1. As with the input data, both a logical view  1404  and a memory array view  1405  are provided to illustrate the resulting 32 bpe elements. The process continues with the lower half of A0,0, with the MPU  1208   a / 1201   d  working in passes to generate A′1,0 completely followed by A′1,1. In one embodiment, the MPU  1208   a / 1201   d  stores the elements within memory array (see, e.g., view  1405 ) with sufficient gaps in memory to store the remaining A′0, * blocks, A′1, * blocks, etc, in sequential order, up to the A′63,63 block. Once original block A0,0 has been processed, the MPU  1208   a / 1201   d  then proceeds to process the 8 bpe A0,1 block, operating on this block in a similar manner. 
       FIG. 15  illustrates another embodiment which performs an up-conversion of tensor data elements. In this case, the MPU  1208   a / 1201   d  executes an 8 bpe to 32 bpe CONVNUMERIC instruction. Here the MPU  1208   a / 1201   d  decomposes each 64×64 8 bpe tensor (once again illustrated in a memory array view  1501  and logical view  1502 ), into 16×16 32 bpe tensors, illustrated as blocks (A′0,0) to (A′0,3), and (A′3,0), and (A′3,3) within the logical view  1503  and with blocks (A′0,0) and (A′3,0) shown in the memory array view  1504 . Although not shown for simplicity, the MPU  1208   a / 1201   d  performs similar operations in parallel for each of the remaining blocks. 
     Note that various other data formats and element sizes may be used while still complying with the underlying principles of the invention. For example, an alternate memory format may store the 16 bit data types as 32×32, the 32 bit data type as 32×16, and the 8 bit data type as 32×64. Some embodiments using these data formats are illustrated in  FIGS. 16-18 , respectively. 
       FIG. 16  illustrates another embodiment which performs an up-conversion of tensor data elements. In this case, the MPU  1208   a / 1201   d  executes a CONVNUMERIC instruction to convert sets of 64 8-bit elements to 32 16-bit elements. An example is shown for tensor block (A0,0) with 64 8-bit elements arranged into 32 rows, which is converted to two tensor blocks (A′0,0) and (A′0,1) each of which has 32 16-bit elements arranged in 32 rows (tensor block  1603 ). 
       FIG. 17  illustrates an embodiment which performs an up-conversion of tensor data elements. The MPU  1208   a / 1201   d  executes a CONVNUMERIC instruction to convert sets of 32 16-bit elements to sets of 16 32-bit elements. An example is shown for tensor block (A0,0) with 32 8-bit elements arranged into 32 rows, which is converted to two tensor blocks (A′0,0) and (A′0,1) each of which has 16 32-bit elements arranged in 32 rows (tensor block  1703 ). 
       FIG. 18  illustrates an embodiment which performs an up-conversion of tensor 8-bit tensor data elements to 32-bit tensor data elements. The MPU  1208   a / 1201   d  executes a CONVNUMERIC instruction to convert 32 rows of 64 8-bit elements to 32 rows of 16 32-bit tensor elements. An example is shown for tensor block (A0,0) with 64 8-bit elements arranged into 32 rows, which is converted to four tensor blocks (A′0,0), (A′0,1), (A′0,2), and (A′0,3) each of which has 32 rows of 16 32-bit tensor elements (tensor block  1803 ). 
     When converting from a tensor with larger bpe to one with fewer bpe, the post-conversion data requires less bandwidth than the input data. The hardware stores the converted output into temporary storage until sufficient result elements are accumulated for output. 
     During down conversion, multiple input tensor blocks combine to generate a single output block. In this embodiment, the temporary storage  1208   b  used by the MPU  1208   a / 1201   d  is sufficiently large to hold all the input data for various scenarios for the upper row blocks. 
       FIG. 19  illustrates one embodiment which converts blocks of 16 bpe values to 8 bpe values. As in the embodiments described above, two different views of the memory organization are provided including a memory array view  1901  and a logical view  1902 . In this embodiment, the input tensor blocks are 32×32×16 bpe blocks. The MPU  1208   a / 1201   d  converts four of these input blocks to one 64×64×8 bpe block. For example, in  FIG. 19 , input blocks (A0,0), (A0,1), (A1,0), and (A1,1) are converted to output block (A′0,0)  1903  which is then stored in the first memory location within the memory array  1904 . In one embodiment, the MPU  1208   a / 1201   d  uses the next set of four blocks (not shown) to generate the next output block (A′0,1) (e.g., input blocks (A0,2), (A0,3), (A1,2), and (A1,3)). 
       FIG. 20  illustrates one embodiment which converts blocks of 32 bpe values to 16 bpe values. A memory array view  2001  and a logical view  2002  are provided as with previous embodiments. In this embodiment, the input tensor blocks are 16×16×32 bpe blocks. The MPU  1208   a / 1201   d  converts four of these input blocks to one 32×32×16 bpe block. For example, in  FIG. 20 , input blocks (A0,0), (A0,1), (A1,0), and (A1,1) are converted to output block (A′0,0)  2003  which is then stored in the first memory location within the memory array  2004 . In one embodiment, the MPU  1208   a / 1201   d  uses the next set of four blocks (not shown) to generate the next output block (A′0,1) (e.g., input blocks (A0,2), (A0,3), (A1,2), and (A1,3)). 
       FIG. 21  illustrates one embodiment which converts blocks of 32 bpe values to 8 bpe values. A memory array view  2101  and a logical view  2102  are provided as with previous embodiments. In this embodiment, the input tensor blocks are 16×16×32 bpe blocks. The MPU  1208   a / 1201   d  converts sixteen of these input blocks to one 64×64×8 bpe block. For example, in  FIG. 20 , input blocks (A0,0), (A0,3), (A3,0), and (A3,3) are converted to output block (A′0,0)  2103  which is then stored in the first memory location within the memory array  2104 . In one embodiment, the MPU  1208   a / 1201   d  uses the next set of four blocks (not shown) to generate the next output block (A′0,1). 
       FIG. 22  illustrates another embodiment which converts blocks of 16 bpe values to 8 bpe values. A memory array view  2201  and a logical view  2202  are provided as with previous embodiments. In this embodiment, the input tensor blocks are 32×32×16 bpe blocks. The MPU  1208   a / 1201   d  converts two of these input blocks to one 32×64×8 bpe block. For example, in  FIG. 20 , input blocks (A0,0) and (A0,1), are converted to output block (A′0,0)  2203  which is then stored in the first memory location within the memory array  2204 . In one embodiment, the MPU  1208   a / 1201   d  uses the next set of two blocks (not shown) to generate the next output block (A′0,1). 
       FIG. 23  illustrates another embodiment which converts blocks of 16 bpe values to 8 bpe values. A memory array view  2301  and a logical view  2302  are provided as with previous embodiments. In this embodiment, the input tensor blocks are 32 rows of 16 32-bit elements. The MPU  1208   a / 1201   d  converts two of these input blocks to one tensor block of 32 16-bit elements arranged in 32 rows  2303 . For example, in  FIG. 23 , input blocks (A0,0) and (A0,1) are converted to output block (A′0,0)  2303  which is then stored in the first memory location within the memory array  2304 . In one embodiment, the MPU  1208   a / 1201   d  uses the next set of two blocks (e.g., (A0,2) and (A0,3)) to generate the next output block (A′0,1). 
       FIG. 24  illustrates an embodiment which converts blocks of 32 bpe tensor values to 8 bpe values. A memory array view  2401  and a logical view  2402  are provided as with previous embodiments. In this embodiment, the input tensor blocks comprise 32 rows of 16 32-bit elements. The MPU  1208   a / 1201   d  converts four of these input blocks to one tensor block of 64 8-bit elements arranged in 32 rows  2403 . For example, in  FIG. 24 , input blocks (A0,0) and (A0,3) are converted to output block (A′0,0)  2403  which is then stored in the first memory location within the memory array  2404 . In one embodiment, the MPU  1208   a / 1201   d  uses the next set of four blocks (not shown) to generate the next output block (A′0,1). 
     A method in accordance with one embodiment of the invention is illustrated in  FIG. 25 . The method may be implemented on the processor and system architectures described herein, but is not limited to any particular architecture. 
     At  2501 , a numeric conversion instruction (e.g., CONVNUMERIC) is fetched having a source operand identifying a source tensor data structure comprising a plurality of input tensor blocks. As mentioned, the input tensor blocks have a predefined, coherent structural arrangement which must be preserved in the output/converted tensor blocks. The numeric conversion instruction includes one or more fields identifying an input numeric representation and an output numeric representation. 
     As mentioned, for “up-conversion” cases, the number of bits per element of the input tensor blocks is less than the number of bits per element of the output tensor blocks. Conversely, for “down-conversion” cases, the number of bits per element of the input tensor blocks is greater than the number of bits per element of the output tensor blocks. 
     At  2502 , the numeric conversion instruction is decoded. In a micro-coded processor, for example, decoding generates one or more microoperations which are scheduled and executed on functional units within the execution circuitry. 
     At  2503 , one or more of the input tensor blocks are retrieved (e.g., from memory) and stored in a temporary/local storage. In one embodiment, the temporary/local storage is a local cache or a high speed buffer storage within the execution circuitry. 
     At  2504 , the numeric conversion instruction is executed, converting tensor elements in each input tensor block from the first numeric representation to the second numeric representation in one or more destination tensor blocks of a destination tensor data structure. In one embodiment, the coherent structural arrangement of the destination tensor blocks is maintained within the destination tensor data structure. This may be accomplished, for example, by anticipating the eventual arrangement of blocks in the destination tensor data structure and creating gaps in memory between completed destination tensor blocks which are to be filled with other destination tensor blocks which have yet to be generated (see, e.g., tensor block (A′1,0) in  FIG. 13 ). 
     If additional input tensor blocks remain, determined at  2505 , then they are retrieved and stored in temporary/local storage at  2503  and the numeric conversion operation  2504  is performed on these blocks. This process repeats until no input tensor blocks remain to be processed. At  2506  the numeric conversion instruction is retired and the architectural state of the processor is updated (i.e., to reflect the completed destination tensor data structure). The retiring of the instruction may occur in parallel to the local storage conversion, since the conversion memory may be too small to fit the entire tensor. 
     In the foregoing specification, the embodiments of invention have been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. 
     Components, features, and details described for any of the apparatus may also optionally apply to any of the methods, which in embodiments may be performed by and/or with such apparatus. Any of the processors described herein may be included in any of the systems disclosed herein. In some embodiments, the computer system may include an interconnect, a processor coupled with the interconnect, and a dynamic random access memory (DRAM) coupled with the interconnect. Alternatively, instead of DRAM, other types of volatile memory that don&#39;t need to be refreshed may be used, or flash memory may be used. 
     In the description and claims, the terms “coupled” and/or “connected,” along with their derivatives, may have be used. These terms are not intended as synonyms for each other. Rather, in embodiments, “connected” may be used to indicate that two or more elements are in direct physical and/or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical and/or electrical contact with each other. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. For example, an execution unit may be coupled with a register and/or a decode unit through one or more intervening components. In the figures, arrows are used to show connections and couplings. 
     The term “and/or” may have been used. As used herein, the term “and/or” means one or the other or both (e.g., A and/or B means A or B or both A and B). 
     In the description above, specific details have been set forth in order to provide a thorough understanding of the embodiments. However, other embodiments may be practiced without some of these specific details. The scope of the invention is not to be determined by the specific examples provided above, but only by the claims below. In other instances, well-known circuits, structures, devices, and operations have been shown in block diagram form and/or without detail in order to avoid obscuring the understanding of the description. Where considered appropriate, reference numerals, or terminal portions of reference numerals, have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar or the same characteristics, unless specified or clearly apparent otherwise. 
     Certain operations may be performed by hardware components, or may be embodied in machine-executable or circuit-executable instructions, that may be used to cause and/or result in a machine, circuit, or hardware component (e.g., a processor, portion of a processor, circuit, etc.) programmed with the instructions performing the operations. The operations may also optionally be performed by a combination of hardware and software. A processor, machine, circuit, or hardware may include specific or particular circuitry or other logic (e.g., hardware potentially combined with firmware and/or software) is operative to execute and/or process the instruction and store a result in response to the instruction. 
     Some embodiments include an article of manufacture (e.g., a computer program product) that includes a machine-readable medium. The medium may include a mechanism that provides, for example stores, information in a form that is readable by the machine. The machine-readable medium may provide, or have stored thereon, an instruction or sequence of instructions, that if and/or when executed by a machine are operative to cause the machine to perform and/or result in the machine performing one or operations, methods, or techniques disclosed herein. 
     In some embodiments, the machine-readable medium may include a non-transitory machine-readable storage medium. For example, the non-transitory machine-readable storage medium may include a floppy diskette, an optical storage medium, an optical disk, an optical data storage device, a CD-ROM, a magnetic disk, a magneto-optical disk, a read only memory (ROM), a programmable ROM (PROM), an erasable-and-programmable ROM (EPROM), an electrically-erasable-and-programmable ROM (EEPROM), a random access memory (RAM), a static-RAM (SRAM), a dynamic-RAM (DRAM), a Flash memory, a phase-change memory, a phase-change data storage material, a non-volatile memory, a non-volatile data storage device, a non-transitory memory, a non-transitory data storage device, or the like. The non-transitory machine-readable storage medium does not consist of a transitory propagated signal. In some embodiments, the storage medium may include a tangible medium that includes solid matter. 
     Examples of suitable machines include, but are not limited to, a general-purpose processor, a special-purpose processor, a digital logic circuit, an integrated circuit, or the like. Still other examples of suitable machines include a computer system or other electronic device that includes a processor, a digital logic circuit, or an integrated circuit. Examples of such computer systems or electronic devices include, but are not limited to, desktop computers, laptop computers, notebook computers, tablet computers, netbooks, smartphones, cellular phones, servers, network devices (e.g., routers and switches), Mobile Internet devices (MIDs), media players, smart televisions, nettops, set-top boxes, and video game controllers. 
     Reference throughout this specification to “one embodiment,” “an embodiment,” “one or more embodiments,” “some embodiments,” for example, indicates that a particular feature may be included in the practice of the invention but is not necessarily required to be. Similarly, in the description various features are sometimes grouped together in a single embodiment, Figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of the invention. 
     Embodiments of the invention may include various steps, which have been described above. The steps may be embodied in machine-executable instructions which may be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, these steps may be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components. 
     As described herein, instructions may refer to specific configurations of hardware such as application specific integrated circuits (ASICs) configured to perform certain operations or having a predetermined functionality or software instructions stored in memory embodied in a non-transitory computer readable medium. Thus, the techniques shown in the Figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., an end station, a network element, etc.). Such electronic devices store and communicate (internally and/or with other electronic devices over a network) code and data using computer machine-readable media, such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read only memory; flash memory devices; phase-change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustical or other form of propagated signals—such as carrier waves, infrared signals, digital signals, etc.). In addition, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input/output devices (e.g., a keyboard, a touchscreen, and/or a display), and network connections. The coupling of the set of processors and other components is typically through one or more busses and bridges (also termed as bus controllers). The storage device and signals carrying the network traffic respectively represent one or more machine-readable storage media and machine-readable communication media. Thus, the storage device of a given electronic device typically stores code and/or data for execution on the set of one or more processors of that electronic device. Of course, one or more parts of an embodiment of the invention may be implemented using different combinations of software, firmware, and/or hardware. 
     Throughout this detailed description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without some of these specific details. In certain instances, well known structures and functions were not described in elaborate detail in order to avoid obscuring the subject matter of the present invention. Accordingly, the scope and spirit of the invention should be judged in terms of the claims which follow.