Patent Publication Number: US-2023157002-A1

Title: Semiconductor memory device and method of fabricating the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0155938, filed on Nov. 12, 2021, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. 
     BACKGROUND 
     1. Field 
     Embodiments relate to a semiconductor device and a method of fabricating the same. 
     2. Description of the Related Art 
     Higher integration of semiconductor devices may help satisfy consumer demands for superior performance and inexpensive prices. In the case of semiconductor devices, integration is an important factor in determining product prices, and increased integration may be desirable. In the case of two-dimensional or planar semiconductor devices, their integration may be mainly determined by the area occupied by a unit memory cell, and integration may be greatly influenced by the level of a fine pattern forming technology. 
     SUMMARY 
     The embodiments may be realized by providing a semiconductor memory device including a stack including layer groups vertically stacked on a substrate, each of the layer groups including a word line, a lower channel layer, an upper channel layer, and a data storing element electrically connected to the lower channel layer and the upper channel layer; and a bit line at a side of the stack, the bit line extending vertically, wherein the bit line includes a protruding portion connected to the lower channel layer and the upper channel layer of each layer group, the word line of each layer group extends in a first direction parallel to a top surface of the substrate, and the word line of each layer group is sandwiched between the lower channel layer and the upper channel layer of the layer group. 
     The embodiments may be realized by providing a semiconductor memory device including a stack including layer groups vertically stacked on a substrate, each of the layer groups including a word line, a lower channel layer, an upper channel layer, and a data storing element electrically connected to the lower channel layer and the upper channel layer; and a bit line at a side of the stack, the bit line extending vertically, wherein in each of the layer groups, the upper channel layer and the lower channel layer are vertically separated from each other, the word line of each of the layer groups extends horizontally between the lower channel layer and the upper channel layer, the lower channel layer and the upper channel layer of each of the layer groups are electrically connected to the bit line, the layer groups include a first layer group and a second layer group, which are sequentially stacked, and a first vertical distance between the lower channel layer of the first layer group and the upper channel layer of the first layer group is different from a second vertical distance between the upper channel layer of the first layer group and the lower channel layer of the second layer group. 
     The embodiments may be realized by providing a semiconductor memory device including a stack including layer groups vertically stacked on a substrate, each of the layer groups including a memory cell transistor and a data storing element electrically connected to the memory cell transistor; and a bit line at a side of the stack, the bit line extending vertically, wherein the bit line electrically connects the stacked memory cell transistors of the layer groups to each other, the memory cell transistor of each of the layer groups includes a lower channel layer between the bit line and the data storing element; an upper channel layer between the bit line and the data storing element, the upper channel layer being vertically separated from the lower channel layer; and a word line between the lower channel layer and the upper channel layer, the word line of each of the layer groups includes a gate portion sandwiched between and overlapped with the lower channel layer and the upper channel layer; and a connecting portion connecting the gate portions that are adjacent to each other, and a width of the gate portion is larger than a width of the connecting portion, as measured in a same direction. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features will be apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which: 
         FIG.  1    is a circuit diagram of a cell array of a three-dimensional semiconductor memory device according to an embodiment. 
         FIG.  2    is a perspective view of a three-dimensional semiconductor memory device according to an embodiment. 
         FIG.  3    is a sectional view taken along a line A-A′ of  FIG.  2   . 
         FIGS.  4 A to  4 C  are plan views of some examples of a data storing element of  FIG.  2   . 
         FIGS.  5 ,  6 , and  7    are perspective views, each of which illustrates a three-dimensional semiconductor memory device according to an embodiment. 
         FIG.  8    is a plan view of a three-dimensional semiconductor memory device according to an embodiment. 
         FIGS.  9 A to  9 H  are sectional views, which are respectively taken along lines A-A′, B-B′, C-C′, D-D′, E-E′, F-F′, G-G′, and H-H′ of  FIG.  8   . 
         FIGS.  10 ,  12 ,  14 ,  16 ,  18 ,  20 ,  22 ,  24 ,  26 ,  28 ,  30 ,  32 ,  34 ,  36 ,  38 ,  40 ,  42 , and  44    are plan views of stages in a method of fabricating a three-dimensional semiconductor memory device according to an embodiment. 
         FIGS.  11 A,  13 A,  15 A,  17 A,  19 A,  21 A,  23 A,  25 A,  27 A,  29 A,  31 A,  33 A,  35 A,  37 A,  39 A,  41 A,  43 A, and  45 A  are sectional views taken along lines A-A′ of  FIGS.  10 ,  12 ,  14 ,  16 ,  18 ,  20 ,  22 ,  24 ,  26 ,  28 ,  30 ,  32 ,  34 ,  36 ,  38 ,  40 ,  42 , and  44   , respectively. 
         FIGS.  11 B,  13 B,  15 B,  17 B,  19 B,  21 B,  23 B,  25 B,  27 B,  29 B,  31 B,  33 B,  35 B,  37 B,  39 B,  41 B,  43 B, and  45 B  are sectional views taken along lines B-B′ of  FIGS.  10 ,  12 ,  14 ,  16 ,  18 ,  20 ,  22 ,  24 ,  26 ,  28 ,  30 ,  32 ,  34 ,  36 ,  38 ,  40 ,  42 , and  44   , respectively. 
         FIGS.  11 C,  13 C,  15 C,  17 C,  19 C,  21 C,  23 C,  25 C,  27 C,  29 C,  31 C,  33 C,  35 C,  37 C,  39 C,  41 C,  43 C, and  45 C  are sectional views taken along lines C-C′ of  FIGS.  10 ,  12 ,  14 ,  16 ,  18 ,  20 ,  22 ,  24 ,  26 ,  28 ,  30 ,  32 ,  34 ,  36 ,  38 ,  40 ,  42 , and  44   , respectively. 
         FIGS.  11 D,  13 D,  15 D,  17 D,  19 D,  21 D,  23 D,  25 D,  27 D,  29 D,  31 D,  33 D,  35 D,  37 D,  39 D,  41 D,  43 D, and  45 D  are sectional views taken along lines D-D′ of  FIGS.  10 ,  12 ,  14 ,  16 ,  18 ,  20 ,  22 ,  24 ,  26 ,  28 ,  30 ,  32 ,  34 ,  36 ,  38 ,  40 ,  42 , and  44   , respectively. 
         FIGS.  11 E,  13 E,  15 E,  17 E,  19 E,  21 E,  23 E,  25 E,  27 E,  29 E,  31 E,  33 E,  35 E,  37 E,  39 E,  41 E,  43 E, and  45 E  are sectional views taken along lines E-E′ of  FIGS.  10 ,  12 ,  14 ,  16 ,  18 ,  20 ,  22 ,  24 ,  26 ,  28 ,  30 ,  32 ,  34 ,  36 ,  38 ,  40 ,  42 , and  44   , respectively. 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1    is a circuit diagram of a cell array of a three-dimensional semiconductor memory device according to an embodiment. 
     Referring to  FIG.  1   , a three-dimensional semiconductor memory device may include a cell array CA including a plurality of sub-cell arrays SCA. The sub-cell arrays SCA may be arranged in a first direction D 1 . 
     Each of the sub-cell arrays SCA may include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cell transistors MCT. Each of the memory cell transistors MCT may be between a corresponding one of the word lines WL and a corresponding one of the bit lines BL. 
     Each of the bit lines BL may be a conductive pattern (e.g., metal line) which extends (e.g., lengthwise) in a direction (i.e., a third direction D 3 ) perpendicular to a substrate. The bit lines BL in each sub-cell array SCA may be arranged in a second direction D 2 . The bit line BL may be connected in common to the memory cell transistors MCT, which are stacked in the third direction D 3 . 
     The word lines WL may be conductive patterns (e.g., metal lines), which are stacked on the substrate in the third direction D 3 . Each of the word lines WL may extend (e.g., lengthwise) in the first direction D 1 . Each of the word lines WL may be connected in common to the memory cell transistors MCT of the sub-cell arrays SCA while extending in the first direction D 1 . 
     The memory cell transistor MCT may include a gate and a first source/drain, which are respectively connected to the word line WL and the bit line BL. The memory cell transistor MCT may further include a second source/drain, which is connected to a data storing element DS. In an implementation, the data storing element DS may be a capacitor. The second source/drain of the memory cell transistor MCT may be connected to a first electrode of the capacitor. 
       FIG.  2    is a perspective view of a three-dimensional semiconductor memory device according to an embodiment.  FIG.  3    is a sectional view taken along a line A-A′ of  FIG.  2   .  FIGS.  4 A to  4 C  are plan views of some examples of a data storing element of  FIG.  2   . 
     Referring first to  FIGS.  1  and  2   , a first stack SS 1  and a second stack SS 2  may be on a substrate SUB. The substrate SUB may be, e.g., a silicon wafer, a germanium wafer, or a silicon-germanium wafer. The substrate SUB may include a cell array region CAR and a connection region CNR. As used herein, the term “or” is not an exclusive term, e.g., “A or B” would include A, B, or A and B. 
     The first and second stacks SS 1  and SS 2  may extend in from the cell array region CAR of the substrate SUB to the connection region CNR in the first direction D 1 . 
     The first and second stacks SS 1  and SS 2  on the cell array region CAR of the substrate SUB may constitute the cell array CA of the three-dimensional semiconductor memory device previously described with reference to  FIG.  1   . 
     In an implementation, each of the first and second stacks SS 1  and SS 2  may include a first layer (e.g., layer group) L 1 , a second layer L 2 , a third layer L 3 , and a fourth layer L 4 , which are sequentially stacked on the substrate SUB. The first to fourth layers L 1  to L 4  may be sequentially stacked to be spaced apart from each other in the vertical or third direction D 3 . Each of the first to fourth layers L 1  to L 4  may include the word line WL extending in in the first direction D 1 , a plurality of channel layers CHL on the word line WL, and a plurality of data storing elements DS connected to the channel layers CHL, respectively. 
     The word line WL in each layer may be a line-shaped pattern extending in the first direction D 1 . The word line WL may include a plurality of gate portions GEP, which are adjacent to the channel layers CHL, respectively (e.g., see  FIG.  3   ). The word line WL may be formed of or include a conductive material. In an implementation, the conductive material may include, e.g., doped semiconductor materials (e.g., doped silicon, doped germanium, or the like), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, or the like), metals (e.g., tungsten, titanium, tantalum, or the like), or metal-semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, or the like). 
     Referring to  FIG.  3   , a gate insulating layer GI may cover a surface of the word line WL. In an implementation, the surface of the word line WL may be surrounded or wrapped with the gate insulating layer GI. The gate insulating layer GI may be formed of or include a high-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride, and may have a single- or multi-layered structure. In an implementation, the high-k dielectric materials may include, e.g., hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. 
     The channel layers CHL of each layer may be arranged in the first direction D 1 . Each of the channel layers CHL may extend in the second direction D 2  crossing the first direction D 1 . Each of the channel layers CHL may include an upper channel layer UCHL and a lower channel layer LCHL, which are respectively on and below the gate portion GEP of the word line WL. The upper channel layer UCHL and the lower channel layer LCHL may serve as channel regions of a single memory cell transistor. The upper and lower channel layers UCHL and LCHL may be spaced apart from each other and, In an implementation, they may behave like a single channel layer. A relationship between the upper and lower channel layers UCHL and LCHL and the gate portion GEP of the word line WL will be described in more detail with reference to  FIG.  3   . 
     The gate insulating layer GI may be between the upper and lower channel layers 
     UCHL and LCHL and the word line WL. In an implementation, the upper and lower channel layers UCHL and LCHL may be spaced apart from the word line WL by the gate insulating layer GI. The upper and lower channel layers UCHL and LCHL may include a semiconductor material, which may be formed on the word line WL using a deposition process. The channel layer CHL may include a semiconductor material, which may be used as a channel region of a memory cell transistor even when it has an amorphous structure as a result of the deposition process. 
     In an implementation, the upper and lower channel layers UCHL and LCHL may be formed of or include an amorphous oxide semiconductor material. In an implementation, the channel layer CHL may be formed of or include a compound containing oxygen (O) and at least two of zinc (Zn), indium (In), gallium (Ga), and tin (Sn). In an implementation, the upper and lower channel layers UCHL and LCHL may be formed of or include indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO). 
     In an implementation, the upper and lower channel layers UCHL and LCHL may be formed of or include a two-dimensional semiconductor material. In an implementation, the upper and lower channel layers UCHL and LCHL may be formed of or include, e.g., metal chalcogenide, transition metal chalcogenide, graphene, or phosphorene. The metal chalcogenide or transition metal chalcogenide may be a metal compound, which may be represented by the chemical formula of MX y , where y may be an integer (e.g., 1, 2, or 3). In the chemical formula, M may be a metal atom or a transition metal atom and may include, e.g., W, Mo, Ti, Zn, Zs, or Zr. In the chemical formula, X may be a chalcogen atom and may include, e.g., S, Se, O, or Te. In an implementation, the upper and lower channel layers UCHL and LCHL may be formed of or include, e.g., graphene, phosphorene, MoS 2 , MoSe 2 , MoTe 2 , WS 2 , WSe 2 , WTe 2 , ReS 2 , ReSe 2 , TiS 2 , TiSe 2 , TiTe 2 , ZnO, ZnS 2 , ZsSe 2 , WO 3 , or MoO 3 . Each of the upper and lower channel layers UCHL and LCHL may have a mono-layered structure or a multi-layered structure, in which 2 to 100 layers are stacked. The multi-layered structure may be realized using several pairs of monolayers coupled by a Van der Waals force. 
     By using the channel layer CHL according to an embodiment, it may be possible to prevent a floating body effect, which could otherwise occur when a channel region is formed of a semiconductor material such as silicon (Si). In addition, the amorphous oxide semiconductor material or the two-dimensional semiconductor material for the channel layer CHL may be formed using a deposition process, it may be easy to realize vertically-stacked channels or a three-dimensional structure of channels. 
     Referring back to  FIG.  2   , the data storing element DS may be connected to an end of the channel layer CHL. The data storing element DS may be parallel to an extension direction of the channel layer CHL (i.e., the second direction D 2 ). A first electrode EL 1  of the data storing element DS, which will be described below, may be extended parallel to the second direction D 2 . 
     The data storing element DS may be a memory element, which is configured to store data. A capacitor, a magnetic tunnel junction pattern, or a variable resistance material (e.g., a phase-change material) may be used as a memory element in the data storing element DS. In an implementation, the data storing element DS may be a capacitor. 
     The data storing elements DS of the first and second stacks SS 1  and SS 2  may be three-dimensionally arranged. The data storing elements DS may be connected in common to a plate PLT provided between the first and second stacks SS 1  and SS 2 . 
       FIGS.  4 A to  4 C  illustrate some examples of the capacitor provided as the data storing element DS. Referring to  FIG.  4 A , the data storing element DS may include a first electrode EL 1 , a second electrode EL 2 , and a dielectric layer DL. The first electrode EL 1  may be connected to an end of the channel layer CHL. The end of the channel layer CHL connected to the first electrode EL 1  may be a drain region (or a source region). The second electrode EL 2  may be connected to the plate PLT. The dielectric layer DL may be between the first electrode EL 1  and the second electrode EL 2 . The first electrode EL 1  may have a hollow cylinder shape. The second electrode EL 2  may be in an internal space of the hollow cylindrical first electrode EL 1 . 
     Each of the first and second electrodes EL 1  and EL 2  may be independently formed of or include, e.g., metallic materials (e.g., titanium, tantalum, tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), or doped semiconductor materials (e.g., doped silicon or doped germanium). The dielectric layer DL may be formed of or include, e.g., high-k dielectric materials (e.g., hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate). 
     Referring to  FIG.  4 B , the first electrode EL 1  may have a hollow cylinder shape, like that in  FIG.  4 A . The second electrode EL 2  may be not only in an internal space of the first electrode EL 1  but also on an outer surface of the first electrode EL 1 . In an implementation, the second electrode EL 2  may surround the first electrode EL 1 . 
     Referring to  FIG.  4 C , the first electrode EL 1  may be provided in the form of a solid cylinder or a pillar. The second electrode EL 2  may face an outer surface of the first electrode EL  1 . 
     In an implementation, the capacitor of the data storing element DS may have various shapes illustrated in  FIGS.  4 A to  4 C , or may have other suitable shapes. 
     Referring back to  FIGS.  2  and  3   , a plurality of the bit lines BL, which extend in a vertical direction (i.e., the third direction D 3 ), may be on the substrate SUB. The channel layers UCHL and LCHL, which are vertically stacked in the third direction D 3 , may be connected to each other through the bit line BL. The bit lines BL may be arranged in the first direction D 1 . Each of the bit lines BL may be electrically connected to the source regions (or the drain regions) of the vertically-stacked channel layers UCHL and LCHL. The bit line BL may be formed of or include a conductive material (e.g., doped semiconductor materials, conductive metal nitrides, metals, or metal-semiconductor compounds). 
     The three-dimensional semiconductor memory device may include the bit line BL, which is vertically extended, and the word line WL, which is horizontally extended to cross the bit line BL. Accordingly, it may be possible to reduce a process defect in a process of forming a three-dimensional memory cell array and to improve reliability of the device. 
     Each of the word lines WL may include a pad portion PDP on the connection region CNR of the substrate SUB. The pad portion PDP may be at an end of the word line WL. The pad portions PDP stacked on the connection region CNR may be arranged to form a staircase structure. Contacts CNT may be respectively coupled to the pad portions PDP of the staircase structure. 
     In an implementation, empty spaces in the first and second stacks SS 1  and SS 2  may be filled with an insulating material. In an implementation, the insulating material may include, e.g., silicon oxide, silicon nitride, or silicon oxynitride. Interconnection lines, which are electrically connected to the bit lines BL and the word lines WL, may be on the first and second stacks SS 1  and SS 2 . In an implementation, the interconnection line may be electrically connected to the word line WL through the contact CNT. 
     Referring back to  FIG.  3   , the upper and lower channel layers UCHL and LCHL and the gate portion GEP of the word line WL of each of the first to fourth layers L 1  to L 4  may constitute one of the memory cell transistors MCT illustrated in  FIG.  1   . Each of the upper and lower channel layers UCHL and LCHL may include a first end EN 1  and a second end EN 2 , which are opposite to each other in the second direction D 2 . The first end EN 1  of the channel layer UCHL or LCHL may be used as a source region (or a drain region) and may be connected to the bit line BL. The second end EN 2  of the channel layer UCHL or LCHL may be used as the drain region (or the source region) and may be connected to the data storing element DS. 
     The gate portion GEP may be sandwiched between the upper and lower channel layers UCHL and LCHL. In an implementation, the gate portion GEP may be between a top surface TOS of the lower channel layer LCHL and a bottom surface BTS of the upper channel layer UCHL. The gate portion GEP may have an inner gate structure, which may be in a space enclosed by the channel layer UCHL and LCHL. In the memory cell transistor according to an embodiment, a channel region may enclose a gate electrode or to have a three-dimensional structure. The top surface TOS of the lower channel layer LCHL and the bottom surface BTS of the upper channel layer UCHL may be covered with the gate insulating layer GI. 
     A distance (in the third direction D 3 , e.g., a vertical distance) between the lower channel layer LCHL of the first layer L 1  and the upper channel layer UCHL of the first layer L 1  may be a first distance PI 1 . In the present specification, the term “distance” may mean a vertical pitch. In an implementation, the first distance PI 1  may be a vertical distance between a top surface of the lower channel layer LCHL of the first layer L 1  and a top surface of the upper channel layer UCHL of the second layer L 2 . 
     A vertical distance between the upper channel layer UCHL of the first layer L 1  and the lower channel layer LCHL of the second layer L 2  may be a second distance PI 2 . In an implementation, the first distance PI 1  may be different from the second distance PI 2 . In an implementation, the first distance PI 1  may be larger or smaller than the second distance PI 2 . In an implementation, the first distance PI 1  may be substantially equal to the second distance PI 2 . 
       FIGS.  5 ,  6 , and  7    are perspective views, each of which illustrates a three-dimensional semiconductor memory device according to an embodiment. In the following description of the embodiments of  FIGS.  5  to  7   , an element previously described with reference to  FIGS.  1  to  4 C  may be identified by the same reference number without repeating an overlapping description thereof. 
     Referring to  FIG.  5   , a peripheral circuit layer PER may be on the substrate SUB. The peripheral circuit layer PER may be between the substrate SUB and the first and second stacks SS 1  and SS 2 . In an implementation, the peripheral circuit layer PER may be below a memory cell array layer composed of the first and second stacks SS 1  and SS 2 . 
     The peripheral circuit layer PER may include a plurality of peripheral transistors PET and a plurality of peripheral interconnection lines PEI, which are on the substrate SUB. The peripheral interconnection lines PEI may be on the peripheral transistors PET and may be connected to the peripheral transistors PET through contact plugs. 
     The penetration contacts TCT may be further between the peripheral circuit layer PER. The penetration contact TCT may vertically extend from the interconnection lines on the first and second stacks SS 1  and SS 2  toward the peripheral circuit layer PER. The peripheral circuit layer PER may be electrically connected to the interconnection lines on the first and second stacks SS 1  and SS 2  through the penetration contacts TCT. 
     In an implementation, the peripheral circuit layer PER may include sense amplifiers electrically connected to the bit lines BL. In an implementation, the peripheral circuit layer PER may include row decoders or sub-word line drivers, which are electrically connected to the word lines WL. 
     Referring to  FIG.  6   , an upper substrate USUB and a peripheral circuit layer PER may be on the memory cell array layer composed of the first and second stacks SS 1  and SS 2 . The peripheral circuit layer PER may be provided on the upper substrate USUB (e.g., a semiconductor wafer). The peripheral circuit layer PER may be configured to have substantially the same features as that in  FIG.  5   . The upper substrate USUB may be bonded to the substrate SUB, on which the first and second stacks SS 1  and SS 2  are provided, in a wafer bonding manner. 
     At least one penetration contact TCT may vertically extend from the peripheral interconnection line PEI of the peripheral circuit layer PER to penetrate the upper substrate USUB. The penetration contact TCT may be connected to the interconnection lines on the first and second stacks SS 1  and SS 2 . In an implementation, the peripheral circuit layer PER may be electrically connected to the interconnection lines on the first and second stacks SS 1  and SS 2  through the penetration contacts TCT. 
     Referring to  FIG.  7   , an upper substrate USUB and a peripheral circuit layer PER may be on the memory cell array layer composed of the first and second stacks SS 1  and SS 2 . The peripheral circuit layer PER may face the substrate SUB. In an implementation, the upper substrate USUB may be at a topmost level of the memory device and may be exposed to the outside. 
     In an implementation, a metal pad (e.g., copper) may be between the peripheral circuit layer PER and the memory cell array layer to electrically connect them to each other. In an implementation, a first metal pad, which is at the uppermost level of the memory cell array layer, may be bonded to a second metal pad, which is at the lowermost level of the peripheral circuit layer PER, to electrically connect the interconnection line of the memory cell array layer to the peripheral interconnection line PEI of the peripheral circuit layer PER. 
       FIG.  8    is a plan view of a three-dimensional semiconductor memory device according to an embodiment.  FIGS.  9 A to  9 H  are sectional views, which are respectively taken along lines A-A′, B-B′, C-C′, D-D′, E-E′, F-F′, G-G′, and H-H′ of  FIG.  8   . In the following description of the embodiment of  FIGS.  8  and  9 A to  9 H , an element previously described with reference to  FIGS.  1  to  7    may be identified by the same reference number without repeating an overlapping description thereof 
     First, a cell array structure, which is on the cell array region CAR of the substrate SUB, will be described with reference to  FIGS.  8  and  9 A to  9 E . The first and second stacks SS 1  and SS 2  may be on the cell array region CAR of the substrate SUB. The first and second stacks SS 1  and SS 2 , which are adjacent to each other in the second direction D 2 , may be spaced apart from each other with the plate PLT therebetween. The first and second stacks SS 1  and SS 2  may have a mirror-symmetry to each other with respect to the plate PLT. 
     Referring to  FIG.  9 B , each of the first and second stacks SS 1  and SS 2  may include first to tenth layers L 1  to L 10 , which are sequentially stacked on the substrate SUB. Each of the first to tenth layers L 1  to L 10  may include the word line WL, the upper and lower channel layers UCHL and LCHL, the gate insulating layer GI, a capping pattern CSP, and a protruding portion PRP, which is a portion of the bit line BL. Each of the first to tenth layers L 1  to L 10  may further include the data storing element DS, which is electrically connected to the upper and lower channel layers UCHL and LCHL. In an implementation, the first to tenth layers L 1  to L 10  may be present, or additional layers may be repeatedly stacked on the tenth layer L 10 . In each of the first to tenth layers L 1  to L 10 , the gate portion GEP of the word line WL may be sandwiched between the upper and lower channel layers UCHL and LCHL. 
     A fifth insulating layer IL 5  may be between adjacent layers. In an implementation, the fifth insulating layer IL 5  may be between the upper channel layer UCHL of the first layer L 1  and the lower channel layer LCHL of the second layer L 2 . In an implementation, the fifth insulating layer IL 5  may include a silicon oxide layer. 
     The bit line BL may extend in the vertical direction (i.e., the third direction D 3 ) or along a sidewall of a corresponding one of the stacks SS 1  and SS 2 . The bit line BL may include a plurality of protruding portions PRP, which horizontally extend toward the channel layer UCHL or LCHL. The upper and lower channel layers UCHL and LCHL in each layer may be connected to each other by the protruding portion PRP of the bit line BL. The channel layers UCHL and LCHL of the first to tenth layers L 1  to L 10 , which are aligned to each other in the third direction D 3 , may be connected in common to the bit line BL through the protruding portions PRP. 
     The word lines WL of the first to tenth layers L 1  to L 10  may be stacked to be aligned to each other in the third direction D 3 . Each of the word lines WL may have a line shape extending in the first direction D 1 . The word line WL may include the gate portions GEP and connecting portions CNP, which may connect the gate portions GEP to each other. The gate portions GEP may be respectively between the upper and lower channel layers UCHL and LCHL. The connecting portion CNP may connect the gate portions GEP, which are adjacent to each other in the first direction D 1 , to each other. The gate portions GEP, which are arranged in the first direction D 1 , may be connected to each other by the connecting portions CNP, thereby constituting a single word line WL. 
     Referring to  FIG.  8   , when viewed in a plan view, the word line WL may have a first recessed sidewall RSP 1  and a second recessed sidewall RSP 2 , which are opposite to each other in the second direction D 2 . The connecting portion CNP may be defined by the first and second recessed sidewalls RSP 1  and RSP 2 . Due to the presence of the first and second recessed sidewalls RSP 1  and RSP 2 , the connecting portion CNP may have a linewidth smaller than that of the gate portion GEP. The connecting portion CNP may have a bottleneck shape. Owing to the connecting portion CNP defined by the first and second recessed sidewalls RSP 1  and RSP 2 , the word line WL may have a wavy sidewall profile, rather than a straight or flat profile. 
     Referring to  FIG.  9 B , the capping pattern CSP may be between the gate portion GEP of the word line WL and the bit line BL. The capping pattern CSP may electrically disconnect or isolate the gate portion GEP of the word line WL from the bit line BL. 
     The gate portion GEP may be between the upper and lower channel layers 
     UCHL and LCHL in each layer. As described above, the memory cell transistor may have an inner gate structure (i.e., a three-dimensional structure), in which the gate portion GEP is placed in the channel layer UCHL and LCHL. Owing to the three-dimensional structure of the gate portion GEP and the channel layer UCHL or LCHL, the channel controllability by the gate portion GEP may be improved in the memory cell transistor according to the present embodiment. 
     In an implementation, as previously described with reference to  FIG.  3   , a first vertical distance between the lower and upper channel layers LCHL and UCHL in one of the layers may be different from a second vertical distance between the lower and upper channel layers LCHL and UCHL in others of the layers. 
     In an implementation, the fifth insulating layer IL 5  between a vertically-adjacent pair of the word lines WL may include a shielding pattern. The shielding pattern may help suppress a crosstalk issue between adjacent ones of the word lines WL and thereby may reduce a coupling capacitance therebetween. In an implementation, the shielding pattern, along with the word line WL, may extend in the first direction D 1  and may be connected to a node applied with a ground voltage. 
     In an implementation, the fifth insulating layer IL 5  between the vertically-adjacent pair of the word lines WL may include an air gap. Due to a relatively low dielectric constant of the air gap, it is possible to help suppress a crosstalk issue between the adjacent ones of the word lines WL and thereby to reduce a coupling capacitance therebetween. If the air gap were absent, a thickness of the fifth insulating layer IL 5  could be increased to lower a capacitance between the word lines WL. However, according to the present embodiment, the air gap having a low dielectric constant may be between the word lines WL, and it is possible to reduce the thickness of the fifth insulating layer IL 5 . As a result, the stacks SS 1  and SS 2  may have a relatively small thickness. 
     Each of the channel layers UCHL and LCHL may include a channel region, a source region, and a drain region. The source region (or the drain region) of the channel layer UCHL or LCHL may be connected to the protruding portion PRP of the bit line BL. The drain region (or the source region) of the channel layer UCHL or LCHL may be connected to the first electrode EL 1  of the data storing element DS. The channel region of the channel layer UCHL or LCHL may be between the source region and the drain region. The channel region of the channel layer UCHL or LCHL may be vertically overlapped with the gate portion GEP. 
     The gate insulating layer GI may be between the channel layer UCHL or LCHL and the gate portion GEP. The gate insulating layer GI may cover a surface of the word line WL. The gate insulating layer GI may cover a surface of the capping pattern CSP. 
     The protruding portion PRP of the bit line BL may extend to an end of the channel layer UCHL or LCHL and may be in direct contact with the channel layer UCHL or LCHL. As a result, the bit line BL may be electrically connected to the source region (or the drain region) of the channel layer UCHL or LCHL. 
     Referring to  FIGS.  8  and  9 A , a plurality of first insulating pillars INP 1  may penetrate the stacks SS 1  and SS 2 . The first insulating pillars INP 1  may be arranged in the first direction D 1 . The first recessed sidewall RSP 1  of the word line WL may be defined by each of the first insulating pillars INP 1 . 
     A plurality of second insulating pillars INP 2  may penetrate the stacks SS 1  and SS 2 . The second insulating pillars INP 2  may be arranged in the first direction D 1 . The second insulating pillars INP 2  may be adjacent to the first insulating pillars INP 1 , and the connecting portions CNP of the word line WL may be respectively between first and second insulating pillars INP 1  and INP 2 . The second recessed sidewall RSP 2  of the word line WL may be defined by each of the second insulating pillars INP 2 . 
     Referring to  FIG.  9 A , the first and second insulating pillars INP 1  and INP 2  may be electrically connected to each other by a filling insulating layer FIN. Referring to  FIG.  9 D , the channel layers UCHL and LCHL in adjacent ones of the layers may be separated from each other by the filling insulating layer FIN and the fifth insulating layer IL 5 . In an implementation, each of the first and second insulating pillars INP 1  and INP 2  may be formed of or include silicon oxide. 
     Referring to  FIGS.  9 B and  9 E , each of the data storing elements DS may include the first electrode EL 1 , the dielectric layer DL, and the second electrode EL 2 . The data storing elements DS in each of the first and second stacks SS 1  and SS 2  may share one dielectric layer DL and one second electrode EL 2 . In an implementation, a plurality of first electrodes EL 1  may be in each of the first and second stacks SS 1  and SS 2 , and surfaces of the first electrodes EL 1  may be covered with one dielectric layer DL. In an implementation, one second electrode EL 2  may be on one dielectric layer DL. 
     The data storing element DS in the present embodiment may have the capacitor structure previously described with reference to  FIG.  4 A . In an implementation, as shown in  FIG.  9 E , the first electrode EL 1  may have a hollow cylinder shape. The second electrode EL 2  may be in the cylindrical internal space of the first electrode EL 1 . In an implementation, the data storing element DS may have the same structure as that illustrated in  FIG.  4 B or  4 C . 
     The first electrodes EL 1  in each layer may be arranged in the first direction D 1 . 
     The first electrode EL 1  may be connected to an end of the channel layer UCHL or LCHL. In an implementation, the first electrode EL 1  may be connected to the drain region (or the source region) of the channel layer UCHL or LCHL. The second electrodes EL 2  may be connected in common to the plate PLT. The plate PLT may be between the first and second stacks SS 1  and SS 2 . 
     Each of the first and second stacks SS 1  and SS 2  may include at least one dummy word line DWL and at least one dummy channel layer DCHL, which are on the uppermost layer (e.g., the tenth layer L 10 ). In an implementation, the dummy word line DWL and the dummy channel layer DCHL may be a buffer structure in a process of forming the memory cell transistors and the data storing elements DS which are composed of the first to tenth layers L 1  to L 10 . 
     A first interlayer insulating layer ILD 1  may be on a side surface of each of the first and second stacks SS 1  and SS 2 . The first interlayer insulating layer ILD 1  may cover the bit lines BL. The bit lines BL, which are arranged in the first direction D 1 , may be electrically separated from each other by the first interlayer insulating layer ILD 1 . 
     A second interlayer insulating layer ILD 2  may be on the first and second stacks 
     SS 1  and SS 2 . Referring to  FIG.  9 A , the plate PLT may include an upper portion that extends to penetrate the second interlayer insulating layer ILD 2  and to have an upward protruding shape. Third and fourth interlayer insulating layers ILD 3  and ILD 4  may be on the second interlayer insulating layer ILD 2 . Each of the first to fourth interlayer insulating layers ILD 1  to ILD 4  may include a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxynitride layer. 
     Each of the bit lines BL may include a pad CEP at the top level thereof. A bit-line contact BLCT may penetrate the second to fourth interlayer insulating layers ILD 2 , ILD 3 , and ILD 4 . The bit-line contact BLCT may be coupled to the pad CEP of the bit line BL. 
     Bit line straps BLIL may be on the fourth interlayer insulating layer ILD 4 . The bit-line straps BLIL may be line-shaped patterns, which extend in the second direction D 2  and parallel to each other. Each of the bit-line straps BLIL may be a metal line. The bit-line strap BLIL may be connected to the bit-line contact BLCT, and the bit-line strap BLIL may be electrically connected to the bit line BL through the bit-line contact BLCT. 
     A plate contact PLCT may penetrate the third and fourth interlayer insulating layers ILD 3  and ILD 4  and to be coupled to the protruding portion of the plate PLT. The plate contact PLCT may be electrically connected to an upper metal line through a via plug. 
     Now, a pad structure on the connection region CNR of the substrate SUB will be described in more detail with reference to  FIGS.  8  and  9 F to  9 H . The word lines WL may extend from the cell array region CAR to the connection region CNR in the first direction D 1 . Each of the word lines WL may include the pad portion PDP, which is on the connection region CNR. 
     The word lines WL on the connection region CNR may form the staircase structure (hereinafter, STS), as previously described with reference to  FIG.  2   . A height of the staircase structure STS may decrease in the first direction D 1 . Due to the staircase structure STS, top surfaces of the stacked word lines WL may be exposed sequentially to the outside of the stack SS 1  or SS 2  from top to bottom. 
       FIG.  9 G  illustrates the pad portion PDP in the uppermost one of the word line WL (i.e., in the word line WL of the tenth layer L 10 ). The word line WL may have a second thickness TK 2 . The pad portion PDP of the word line WL may have a first thickness TK 1 . The first thickness TK 1  may be larger than the second thickness TK 2 . For example, the thickness of the word line WL may be abruptly increased at the pad portion PDP. 
     Referring to  FIG.  9 G , an upper insulating layer UIL may be provided on the staircase structure STS. The upper insulating layer UIL may cover the staircase structure STS. The contact CNT may penetrate the upper insulating layer UIL and may be connected to the pad portion PDP. In an implementation, the contact CNT may be coupled to the pad portion PDP of the word line WL of the tenth layer L 10 . A bottom surface of the contact CNT may be lower than a top surface of the pad portion PDP. 
     As the staircase structure STS extends in the first direction D 1 , the pad portions PDP of the first to ninth layers L 1  to L 9  may be sequentially (i.e., from top to bottom) exposed to the outside of the stack SS 1  or SS 2 . The contacts CNT may be respectively coupled to the exposed pad portions PDP in the same manner as described with reference to  FIG.  2   . 
     The contacts CNT may be respectively coupled with word-line contacts WLCT, which penetrate the second to fourth interlayer insulating layers ILD 2  to ILD 4 . The word-line contacts WLCT may be electrically connected to upper metal lines through via plugs. 
     According to an embodiment, the three-dimensional semiconductor memory device may include the word lines WL, which are sequentially stacked and have end portions serving as the pad portions PDP, respectively. A signal applied to the pad portion PDP may be directly delivered to the cell array region CAR through the word line WL. This may make it possible to improve an operation speed and electric characteristics of the memory device. 
       FIGS.  10 ,  12 ,  14 ,  16 ,  18 ,  20 ,  22 ,  24 ,  26 ,  28 ,  30 ,  32 ,  34 ,  36 ,  38 ,  40 ,  42 , and  44    are plan views of stages in a method of fabricating a three-dimensional semiconductor memory device according to an embodiment.  FIGS.  11 A,  13 A,  15 A,  17 A,  19 A,  21 A,  23 A,  25 A,  27 A,  29 A,  31 A,  33 A,  35 A,  37 A,  39 A,  41 A,  43 A, and  45 A  are sectional views taken along lines A-A′ of  FIGS.  10 ,  12 ,  14 ,  16 ,  18 ,  20 ,  22 ,  24 ,  26 ,  28 ,  30 ,  32 ,  34 ,  36 ,  38 ,  40 ,  42 , and  44   , respectively.  FIGS.  11 B,  13 B,  15 B,  17 B,  19 B,  21 B,  23 B,  25 B,  27 B,  29 B,  31 B,  33 B,  35 B,  37 B,  39 B,  41 B,  43 B, and  45 B  are sectional views taken along lines B-B′ of  FIGS.  10 ,  12 ,  14 ,  16 ,  18 ,  20 ,  22 ,  24 ,  26 ,  28 ,  30 ,  32 ,  34 ,  36 ,  38 ,  40 ,  42 , and  44   , respectively.  FIGS.  11 C,  13 C,  15 C,  17 C,  19 C,  21 C,  23 C,  25 C,  27 C,  29 C,  31 C,  33 C,  35 C,  37 C,  39 C,  41 C,  43 C, and  45 C  are sectional views taken along lines C-C′ of FIGS.  10 ,  12 ,  14 ,  16 ,  18 ,  20 ,  22 ,  24 ,  26 ,  28 ,  30 ,  32 ,  34 ,  36 ,  38 ,  40 ,  42 , and  44 , respectively.  FIGS.  11 D,  13 D,  15 D,  17 D,  19 D,  21 D,  23 D,  25 D,  27 D,  29 D,  31 D,  33 D,  35 D,  37 D,  39 D,  41 D,  43 D, and  45 D  are sectional views taken along lines D-D′ of  FIGS.  10 ,  12 ,  14 ,  16 ,  18 ,  20 ,  22 ,  24 ,  26 ,  28 ,  30 ,  32 ,  34 ,  36 ,  38 ,  40 ,  42 , and  44   , respectively.  FIGS.  11 E,  13 E,  15 E,  17 E,  19 E,  21 E,  23 E,  25 E,  27 E,  29 E,  31 E,  33 E,  35 E,  37 E,  39 E,  41 E,  43 E, and  45 E  are sectional views taken along lines E-E′ of  FIGS.  10 ,  12 ,  14 ,  16 ,  18 ,  20 ,  22 ,  24 ,  26 ,  28 ,  30 ,  32 ,  34 ,  36 ,  38 ,  40 ,  42 , and  44   , respectively. 
     A method of fabricating a three-dimensional memory cell array on the cell array region CAR of the substrate SUB will be described. Referring to  FIGS.  10  and  11 A to  11 E , a stack SS may be formed on the substrate SUB. The formation of the stack SS may include sequentially stacking the first to tenth layers L 1  to L 10 . 
     In an implementation, a second insulating layer IL 2  may be formed on the substrate SUB. First insulating layers IL 1  and second insulating layers IL 2  may be alternately and repeatedly stacked on the second insulating layer IL 2 . Each of the first to tenth layers L 1  to L 10  may include one first insulating layer 
     The first insulating layers IL 1  may be formed of or include silicon nitride. The second insulating layers IL 2  may be formed of or include a material (e.g., silicon oxide) having an etch selectivity with respect to the first insulating layers IL 1 . 
     The stack SS may be patterned to form first holes HO 1  and second holes HO 2  penetrating the stack SS. The first holes HO 1  may be arranged at a specific pitch in the first direction D 1 . The second holes HO 2  may be formed to be adjacent to the first holes HO 1 , respectively, in the second direction D 2 . The second holes HO 2  may be arranged at the specific pitch in the first direction D 1 . Each of the first and second holes HO 1  and HO 2  may be formed to expose a top surface of the substrate SUB. 
     Referring to  FIGS.  12  and  13 A to  13 E , first sacrificial pillars SAP 1  and second sacrificial pillars SAP 2  may be respectively formed by filling the first and second holes HO 1  and HO 2  with an insulating material. The first sacrificial pillars SAP 1  may be formed to completely fill the first holes HO 1 , respectively, and the second sacrificial pillars SAP 2  may be formed to completely fill the second holes HO 2 , respectively. In an implementation, the first and second sacrificial pillars SAP 1  and SAP 2  may be formed of or include silicon oxide. 
     The stack SS may be patterned to form first and second trenches TR 1  and TR 2  penetrating the stack SS. The stack SS may be bisected into the first stack SS 1  and the second stack SS 2  by the first and second trenches TR 1  and TR 2 . 
     The first trench TR 1  may be between the first and second stacks SS 1  and SS 2 . 
     The second trench TR 2  may be at a side of each of the first and second stacks SS 1  and SS 2 . A sidewall of each of the second sacrificial pillars SAP 2  may be exposed through the first trench TR 1 . A sidewall of each of the first sacrificial pillars SAP 1  may be exposed through the second trench TR 2 . 
     Referring to  FIGS.  14  and  15 A to  15 E , a first stopper layer STL 1  may be conformally formed in each of the first and second trenches TR 1  and TR 2 . In an implementation, the first stopper layer STL 1  may be formed to have a thickness that is too small to completely fill the trench TR 1  or TR 2 . The first stopper layer STL 1  may have a roughly U-shaped section (e.g., see  FIGS.  15 A and  15 B ). 
     A gap-fill layer GFL may be formed in each of the first and second trenches TR 1  and TR 2 . The gap-fill layer GFL may be formed on the first stopper layer STL 1 . The gap-fill layer GFL may be formed to completely fill (e.g., remaining parts of) the trench TR 1  or TR 2 . In an implementation, the first stopper layer STL 1  may be formed of or include silicon nitride, and the gap-fill layer GFL may be formed of or include silicon oxide. 
     Referring to  FIGS.  16  and  17 A to  17 E , a second stopper layer STL 2  may be formed to cover a top surface of the first stopper layer STL 1  and a top surface of the gap-fill layer GFL. In an implementation, the second stopper layer STL 2  may be formed to cover only the top surface of the first stopper layer STL 1  and the top surface of the gap-fill layer GFL, and in this case, top surfaces of the first and second stacks SS 1  and SS 2  may be exposed to the outside of the second stopper layer STL 2 . Top surfaces of the first and second sacrificial pillars SAP 1  and SAP 2  may be exposed to the outside of the second stopper layer STL 2 . 
     A wet etching process using the second stopper layer STL 2  as an etch mask may be performed to selectively remove the first and second sacrificial pillars SAP 1  and SAP 2 . The first and second sacrificial pillars SAP 1  and SAP 2  may be removed, and the first and second holes HO 1  and HO 2  may be again exposed to the outside. 
     The wet etching process may be performed to selectively etch only a silicon oxide layer, such as the first and second sacrificial pillars SAP 1  and SAP 2 . Thus, the second insulating layers IL 2  in the first and second stacks SS 1  and SS 2  may also be removed during the removal process of the first and second sacrificial pillars SAP 1  and SAP 2 . This may be because the second insulating layers IL 2  include silicon oxide. 
     Empty spaces ETS may be formed as the removal of the second insulating layers IL 2 . In an implementation, the empty spaces ETS may be formed in the first and second stacks SS 1  and SS 2  by the wet etching process. The first and second holes HO 1  and HO 2 , which are adjacent to each other, may be connected to each other through the empty spaces ETS (e.g., see  FIG.  17 A ). Each of the empty spaces ETS may be between adjacent ones of the first insulating layers IL 1 . 
     In an implementation, the gap-fill layer GFL may include silicon oxide, and it may not be removed by the etching process and may be left as it is, because it is encapsulated or sealed by the first and second stopper layers STL 1  and STL 2 . 
     Referring to  FIGS.  18  and  19 A to  19 E , the channel layer UCHL or LCHL may be conformally deposited on the substrate SUB. The channel layer UCHL or LCHL may be formed in each of the empty spaces ETS. The channel layer UCHL or LCHL may be formed on a bottom surface of each of the first insulating layers IL 1 . In an implementation, the channel layer UCHL or LCHL may be formed on a top surface of each of the first insulating layers IL 1 . 
     The channel layer UCHL or LCHL may be formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The channel layer UCHL or LCHL may be formed to a relatively small thickness such that the entirety of the empty space ETS is not filled with the channel layer UCHL or LCHL. 
     In an implementation, the channel layer UCHL or LCHL may include a semiconductor material that may be formed using a deposition process or that may be suitably used as a channel of a memory cell transistor. In an implementation, the channel layer UCHL or LCHL may be formed of or include an amorphous oxide semiconductor material (e.g., IGZO or ITZO). In an implementation, the channel layer UCHL or LCHL may be formed of or include a two-dimensional semiconductor material (e.g., metal chalcogenide, graphene, or phosphorene). 
     Next, the fifth insulating layer IL 5  may be deposited on the substrate SUB. The fifth insulating layer IL 5  may be formed to completely fill each of the empty spaces ETS. As wet trimming process may be performed on the fifth insulating layer IL 5  to leave the fifth insulating layer IL 5  in only the empty space ETS. In an implementation, the fifth insulating layer IL 5  may be formed of or include silicon oxide. 
     The channel layer UCHL or LCHL may be etched using the fifth insulating layers IL 5  as an etch mask, and as a result, the upper channel layer UCHL and the lower channel layer LCHL may be formed in each of the empty spaces ETS. In an implementation, the channel layer UCHL or LCHL in each layer may include the upper channel layer UCHL and the lower channel layer LCHL. The upper channel layer UCHL and the lower channel layer LCHL may be connected to each other (e.g., see  FIG.  19 B ). The fifth insulating layer IL 5  may be between the upper channel layer UCHL and the lower channel layer LCHL. 
     Referring to  FIGS.  20  and  21 A to  21 E , a wet etching process may be performed on the sidewalls of the channel layers UCHL and LCHL, which are exposed through the first and second holes HO 1  and HO 2 . The wet etching process may be performed to partially etch each of the channel layers UCHL and LCHL in a horizontal direction. The wet etching process may be performed to selectively etch only the channel layers UCHL and LCHL. A recessed region RSR may be formed, as a result of the partial etching of each of the channel layers UCHL and LCHL. 
     Referring to  FIG.  20   , each of the channel layers UCHL and LCHL may have a bar shape extending in the second direction D 2 , as a result of the horizontal and partial wet etching process. In an implementation, a width of the channel layer UCHL or LCHL in the first direction D 1  may be reduced by the wet etching process, as shown in  FIG.  21 C . 
     Referring to  FIG.  21 D , the channel layer UCHL or LCHL in each of the layers L 1  to L 10  may be divided into a plurality of channel layers UCHL and LCHL by the wet etching process. In an implementation, one channel layer UCHL or LCHL may be divided into a plurality of the channel layers UCHL and LCHL, which are horizontally spaced apart from each other. The recessed region RSR may be between the channel layers UCHL and LCHL, which are horizontally spaced apart from each other. 
     Referring to  FIGS.  22  and  23 A to  23 E , the first insulating pillars INP 1  and the second insulating pillars INP 2  may be respectively formed by filling the first and second holes HO 1  and HO 2  with an insulating material. The first insulating pillars INP 1  may be formed to completely fill the first holes HO 1 , respectively, and the second insulating pillars INP 2  may be formed to completely fill the second holes HO 2 , respectively. In an implementation, the first and second insulating pillars INP 1  and INP 2  may be formed of or include silicon oxide. 
     The filling insulating layers FIN may be formed during the formation of the first and second insulating pillars INP 1  and INP 2  (e.g., see  FIG.  23 A ). Adjacent ones of the first and second insulating pillars INP 1  and INP 2  may be connected to each other by the filling insulating layers FIN. In an implementation, the filling insulating layer FIN may be formed in the recessed region RSR. 
     A first mask pattern MAP 1  may be formed on top surfaces of the first and second stacks SS 1  and SS 2  and a top surface of the gap-fill layer GFL in the first trench TR 1 . The first mask pattern MAP 1  may be formed to expose the gap-fill layer GFL in the second trench TR 2 . 
     The exposed gap-fill layer GFL may be selectively removed using the first mask pattern MAP 1  as an etch mask. Thus, the first stopper layer STL 1  on the sidewall of each of the first and second stacks SS 1  and SS 2  may be exposed to the outside. In an implementation, the first stopper layer STL 1  in the second trench TR 2  may be exposed. 
     Referring to  FIGS.  24  and  25 A to  25 E , the first stopper layer STL 1  in the second trench TR 2  may be selectively removed through the second trench TR 2 . Next, the first insulating layers IL 1  exposed through the second trench TR 2  may be partially removed. In an implementation, the removal of the first stopper layer STL 1  and the first insulating layers IL 1  may include performing a wet etching process of selectively removing a silicon nitride layer. The wet etching process may be performed to horizontally and partially etch each of the first insulating layers IL  1 . 
     Referring to  FIG.  25 B , each of the first insulating layers IL 1  may be horizontally etched, and a first recess RS 1 , which is extended from the second trench TR 2  in the second direction D 2 , may be formed in the first stack SS 1 . Similarly, the first recess RS 1 , which extends from the second trench TR 2 , may be formed in the second stack SS 2 . The first recess RS 1  may be formed between the lower and upper channel layers LCHL and UCHL. 
     Referring to  FIGS.  26  and  27 A to  27 E , the gate insulating layer GI may be conformally deposited on the substrate SUB. The gate insulating layer GI may be formed in the first recess RS 1  through the second trench TR 2 . 
     Next, the word line WL may be formed in the first recess RS 1 . The word line WL may be formed on the gate insulating layer GI. In an implementation, the formation of the word line WL may include depositing a metal layer in the first recess RS 1  through the second trench TR 2  and performing a wet etching process of etching the metal layer using an etchant supplied through the second trench TR 2 , and as a result, the word line WL may be left in the first recess RS 1 . 
     The word lines WL may be formed in the first recesses RS 1 , respectively, and may be stacked in the third direction D 3 . Each of the word lines WL may have a line shape extending in the first direction D 1 . The word line WL may include the first and second recessed sidewalls RSP 1  and RSP 2 , which are respectively formed by the first and second insulating pillars INP 1  and INP 2  which are adjacent to each other. 
     The word line WL may include the gate portion GEP, which is between the upper and lower channel layers UCHL and LCHL, and the connecting portion CNP, which is between the first and second insulating pillars INP 1  and INP 2 . The connecting portion CNP may connect the gate portions GEP, which are adjacent to each other in the first direction D 1 , to each other. The gate portion GEP may be formed such that a width thereof in the second direction D 2  is larger than a width of the connecting portion CNP in the second direction D 2 . 
     Referring to  FIGS.  28  and  29 A to  29 E , the capping pattern CSP may be formed on an exposed sidewall of the gate portion GEP of the word line WL. The capping pattern CSP may be formed between the first insulating pillars INP 1 , which are adjacent to each other in the first direction D 1 . Next, the gate insulating layer GI, which is exposed to the outside, may be partially removed using the capping pattern CSP as an etch mask. 
     Referring to  FIG.  29 B , the channel layer UCHL or LCHL and the fifth insulating layer IL 5  may be etched horizontally (e.g., recessed in the second direction D 2 ) through the second trench TR 2 . As a result of the horizontal recessing of the channel layer UCHL or LCHL, the upper channel layer UCHL in a lower layer may be disconnected from the lower channel layer LCHL in an upper layer. The fifth insulating layer IL 5  may be between the upper channel layer UCHL in the lower layer and the lower channel layer LCHL in the upper layer. As a result of the horizontal recessing process, a second recess RS 2  may be formed to expose the channel layer UCHL or LCHL and the fifth insulating layer IL 5 . 
     In an implementation, a doping process may be performed on an end portion of the channel layer UCHL or LCHL exposed by the second recess RS 2 . The doping process may be performed to allow the end portion of the channel layer UCHL or LCHL to have electric characteristics that are suitable for a source (or drain) electrode of a memory cell transistor. In an implementation, in the case where the channel layer UCHL or LCHL includes an amorphous oxide semiconductor material, the doping process may include injecting dopants or impurities (e.g., hydrogen (H), oxygen (O), or silicon (Si) ions) into the channel layer UCHL or LCHL. 
     Referring to  FIGS.  30  and  31 A to  31 E , a conductive layer CDL may be conformally deposited in the second trench TR 2  and the second recess RS 2 . The conductive layer CDL may be formed on a sidewall of each of the first and second stacks SS 1  and SS 2 . 
     The conductive layer CDL may be formed such that it is connected to an end of each of the channel layers UCHL and LCHL exposed by the second recess RS 2 . In an implementation, the conductive layer CDL may include the protruding portion PRP filling the second recess RS 2 . The protruding portion PRP may be connected in common to the upper and lower channel layers UCHL and LCHL. 
     The first interlayer insulating layer ILD 1  may be formed on the conductive layer CDL to fill the second trench TR 2 . In an implementation, the first interlayer insulating layer ILD 1  may include a silicon oxide layer. A top surface of the first interlayer insulating layer ILD 1  may be coplanar with a top surface of the first mask pattern MAP 1 . 
     Referring to  FIGS.  32  and  33 A to  33 E , a second mask pattern MAP 2  may be formed on the first mask pattern MAP 1  and the first interlayer insulating layer ILD 1 . The second mask pattern MAP 2  may include a plurality of first openings OPN 1 . Each of the first openings OPN 1  may be formed to partially expose the conductive layer CDL. 
     An exposed portion of the first interlayer insulating layer ILD 1  and an exposed portion of the conductive layer CDL may be removed using the second mask pattern MAP 2  as an etch mask. The conductive layer CDL may be partially removed through the first openings OPN 1 , and a plurality of the bit lines BL, which are separated from each other in the first direction D 1 , may be formed from one conductive layer CDL (e.g., see  FIG.  32   ). Each of the bit lines BL may extend in the third direction D 3  or along the sidewall of the stack SS 1  or SS 2 . Each of the bit lines BL may be connected to the channel layer UCHL or LCHL through the protruding portion PRP. Each of the bit lines BL may include the pad CEP formed at the topmost level thereof. 
     Referring to  FIGS.  34  and  35 A to  35 E , an insulating layer may be formed in spaces, which were etched through the first openings OPN 1 . The insulating layer, which is formed by this process, may form one first interlayer insulating layer ILD 1 , along with the left portion of the first interlayer insulating layer ILD 1 . 
     A planarization process may be performed to expose a top surface of the first interlayer insulating layer ILD 1  and top surfaces of the first and second insulating pillars INP 1  and INP 2 . The first and second mask patterns MAP 1  and MAP 2  may be removed by the planarization process. 
     The second interlayer insulating layer ILD 2  may be formed on the first interlayer insulating layer ILD 1  and the first and second stacks SS 1  and SS 2 . The second interlayer insulating layer ILD 2  may be patterned to form a second opening OPN 2  overlapped with the first trench TR 1 . The gap-fill layer GFL exposed by the second opening OPN 2  may be selectively removed. 
     Referring to  FIGS.  36  and  37 A to  37 E , the first stopper layer STL 1 , which is exposed through the second opening OPN 2 , may be removed. Accordingly, the first trench TR 1  may be fully exposed again. Next, the first insulating layers ILL which are exposed through the first trench TR 1 , may be fully removed (e.g., see  FIG.  37 B ). In an implementation, the removal of the first stopper layer STL 1  and the first insulating layers IL 1  may include performing a wet etching process of selectively removing a silicon nitride layer. 
     Referring to  FIGS.  37 B and  37 E , third recesses RS 3 , which horizontally extend from the first trench TR 1 , may be formed, as a result of the removal of the first insulating layers IL 1 . Each of the third recesses RS 3  may be formed between a pair of the channel layers UCHL or LCHL, which are respectively included in a vertically adjacent pair of the layers. The third recess RS 3  may be formed to expose the gate insulating layer GI. 
     Referring to  FIGS.  38  and  39 A to  39 E , a wet etching process may be performed on the channel layers UCHL and LCHL exposed through the third recesses RS 3  and the first trench TR 1 . The wet etching process may be performed to etch each of the channel layers UCHL and LCHL partially. The wet etching process may be performed to selectively etch only the channel layers UCHL and LCHL. 
     Referring to  FIG.  39 B , as a result of the etching process, the lower and upper channel layers LCHL and UCHL may be completely separated from each other with the fifth insulating layer IL 5  therebetween. In an implementation, an end portion of the channel layer UCHL or LCHL may be vertically aligned to a sidewall of the word line WL by the etching process. 
     In an implementation, a doping process may be performed on the end portion of the channel layer UCHL or LCHL exposed through the third recess RS 3 . The doping process may be performed to allow the end portion of the channel layer UCHL or LCHL to have electric characteristics that are suitable for a source (or drain) electrode of a memory cell transistor. In an implementation, in the case where the channel layer UCHL or LCHL includes an amorphous oxide semiconductor material, the doping process may include injecting dopants (e.g., hydrogen (H), oxygen (O), or silicon (Si) ions) into the channel layer UCHL or LCHL. 
     An electrode layer ELL may be conformally deposited in the third recess RS 3  through the first trench TR 1 . The electrode layer ELL may be connected to a portion of the channel layer UCHL or LCHL, which is exposed though the third recess RS 3 . 
     Referring to  FIGS.  40  and  41 A to  41 E , a sacrificial mask layer SML may be formed on the electrode layer ELL to fill the third recess RS 3 . The sacrificial mask layer SML may be formed of or include a material having an etch selectivity with respect to the electrode layer ELL. 
     The first electrode EL 1  may be formed by partially removing exposed portions of the electrode layer ELL using the sacrificial mask layer SML as an etch mask. The first electrode EL 1  may be formed to have a hollow cylinder shape left in the third recess RS 3  (e.g., see  FIG.  41 E ). 
     Referring to  FIGS.  42  and  43 A to  43 E , the sacrificial mask layers SML may be selectively removed. When the sacrificial mask layers SML are removed, the second insulating pillars INP 2 , which are exposed through the first trench TR 1 , may be horizontally etched. Thus, a fourth recess RS 4  may be formed between the first electrodes EL 1 , which are adjacent to each other in the first direction D 1  (e.g., see  FIG.  42   ). 
     Referring to  FIGS.  44  and  45 A to  44 E , the dielectric layer DL and the second electrode EL 2  may be sequentially formed on the first electrode EL 1  through the first trench TR 1 . The second electrode EL 2  between the first and second stacks SS 1  and SS 2  may serve as the plate PLT. An upper portion of the plate PLT may be exposed through the first trench TR 1 . 
     Referring back to  FIGS.  8  and  9 A to  9 E , the third interlayer insulating layer 
     ILD 3  and the fourth interlayer insulating layer ILD 4  may be sequentially formed on the second interlayer insulating layer ILD 2 . The plate contact PLCT may be formed to penetrate the third and fourth interlayer insulating layers ILD 3  and ILD 4  and to be coupled to the plate PLT. The bit-line contact BLCT may be formed to penetrate the second to fourth interlayer insulating layers ILD 2 , ILD 3 , and ILD 4  and to be coupled to the pad CEP of the bit line BL. The bit-line strap BLIL may be formed on the bit-line contact BLCT. 
     In an implementation, each of the silicon oxide layer and the silicon nitride layer, which may be used in the afore-described fabrication method, may further contain carbon (C), nitrogen (N), oxygen (O), or boron (B). 
     By way of summation and review, extremely expensive process equipment may be used to increase pattern fineness and may a practical limitation on increasing integration for two-dimensional or planar semiconductor devices. To overcome such a limitation, three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells have recently been considered. 
     According to an embodiment, a three-dimensional semiconductor memory device may include a channel layer, which may be realized using an amorphous oxide semiconductor material or a two-dimensional semiconductor material, and in this case, it is possible to help prevent a floating body effect in a memory cell transistor. In addition, the channel layer may be formed by a deposition process, it is possible to easily realize a three-dimensional array of memory cells. 
     According to an embodiment, a three-dimensional semiconductor memory device may include word lines, which are sequentially stacked and may have end portions serving as contact pads, respectively. A signal applied to the contact pad may be directly delivered to a cell array region through the word line. This may make it possible to improve an operation speed and electric characteristics of the memory device. 
     In a three-dimensional semiconductor memory device according to an embodiment, a bit line may be vertically formed, and a word line may be horizontally formed. This may make it possible to reduce a process defect in a process of forming a three-dimensional array of memory cells and to improve reliability of the device. 
     One or more embodiments may provide a three-dimensional semiconductor memory device with improved electrical characteristics. 
     One or more embodiments may provide a three-dimensional semiconductor memory device with improved electric characteristics and an increased integration density. 
     One or more embodiments may provide a method of fabricating a three-dimensional semiconductor memory device with improved electric characteristics and an increased integration density. 
     Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.