Patent Publication Number: US-2023153375-A1

Title: Computing in memory cell

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional application of and claims the priority benefit of U.S. application Ser. No. 17/013,646, filed on Sep. 6, 2020, which claims the priority benefit of Taiwan application no. 109121085, filed on Jun. 22, 2020. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
    
    
     TECHNICAL FIELD 
     The disclosure relates to a memory circuit, and more particularly, relates to a computing in memory cell. 
     BACKGROUND 
     Artificial intelligence (AI) networks, such as deep neural networks (DNN), are often required to perform a matrix multiplication. Matrix data is transmitted (moved) from a memory to a computing circuit for the matrix multiplication. In the computing process of the AI network, the movement of a large amount of data will consume time and energy. Computing in memory (CIM) technology can reduce the number of data movements. CIM technology has the advantages of increasing computing power and reducing power consumption. 
     SUMMARY 
     The disclosure provides a computing in memory (CIM) cell to realize computing in memory. 
     In an embodiment of the invention, the computing in memory cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element is adapted to receive a bias voltage corresponding to a first weight. A control terminal of the first semiconductor element is adapted to be coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element is adapted to receive an inverted signal of the computing word-line. The fourth semiconductor element is configured to selectively provide a weight resistance corresponding to a weight. A first terminal of the fourth semiconductor element is adapted to be coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is adapted to be coupled to a second computing bit-line. A control terminal of the fourth semiconductor element is coupled to the second terminal of the second semiconductor element. 
     Based on the above, the computing word-lines described in the embodiments of the invention can provide one data bit (a first data bit for control a first semiconductor element to be turned on/off) in one matrix, and the memory cell circuit can provide one data bit (a second data bit for controlling a second semiconductor element to be turned on/off) in another matrix. The operation of the first semiconductor element and the second semiconductor element is equivalent to a multiplication operation performed on the first data bit and the second data bit. As a result, the in-memory computing cell can realize in-memory computing. 
     To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a circuit block diagram of a memory according to an embodiment of the disclosure. 
         FIG.  2    is a circuit block diagram of a computing in memory cell CC 1  shown by  FIG.  1    according to an embodiment of the disclosure. 
         FIG.  3    is an equivalent circuit diagram of semiconductor elements shown by  FIG.  2    according to an embodiment of the disclosure. 
         FIG.  4    is an equivalent circuit diagram of the computing in memory cells shown by  FIG.  1    according to an embodiment of the disclosure. 
         FIG.  5    is a circuit block diagram of the computing in memory cell shown by  FIG.  1    according to another embodiment of the disclosure. 
         FIG.  6    is an equivalent circuit diagram of semiconductor elements shown by  FIG.  5    according to an embodiment of the disclosure. 
         FIG.  7    is a circuit block diagram of the computing in memory cell shown by  FIG.  1    according to yet another embodiment of the disclosure. 
         FIG.  8    is an equivalent circuit diagram of the computing in memory cell shown by  FIG.  1    according to another embodiment of the disclosure. 
         FIG.  9    is a circuit block diagram of a memory according to another embodiment of the disclosure. 
         FIG.  10    is a circuit block diagram of a computing in memory cell shown by  FIG.  9    according to another embodiment of the disclosure. 
         FIG.  11    is a circuit block diagram of the computing in memory cell shown by  FIG.  9    according to another embodiment of the disclosure. 
         FIG.  12    is a circuit block diagram of the computing in memory cell shown by  FIG.  1    according to yet another embodiment of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The term “coupled (or connected)” used in this specification (including claims) may refer to any direct or indirect connection means. For example, “a first device is coupled (connected) to a second device” can be interpreted as “the first device is directly connected to the second device” or “the first device is indirectly connected to the second device through other devices or connection means”. The terms such as “first”, “second” and the like as recited in full text of the specification (including claims) are intended to give the elements names or distinguish different embodiments or scopes, and are not intended to limit an upper limit or a lower limit of the number of the elements nor limit an order of the elements. Moreover, wherever possible, elements/components/steps with same reference numerals represent same or similar parts in the drawings and embodiments. Elements/components/steps with the same reference numerals or names in different embodiments may be cross-referenced. 
       FIG.  1    is a circuit block diagram of a memory according to an embodiment of the disclosure. According to design requirements, the memory may be a static random access memory (SRAM), a dynamic random access memory (DRAM), or other types of memories. The memory has a memory cell array. The memory cell array includes a plurality of computing in memory (CIM) cells. The number of the computing in memory cells in the memory cell array may be determined according to design requirements. For instance, the memory cell array shown by  FIG.  1    includes computing in memory cells CC 1 , CC 2 , CC 3 , CC 4 , CCS, CC 6 , CC 7 , CCB, CC 9 , 
     CC 10 , CC 11 , CC 12 , CC 13 , CC 14 , CC 15 , and CC 16 . Each of the computing in memory cells CC 1  to CC 16  can provide a general memory cell function. In addition, each of the computing in memory cells CC 1  to CC 16  can further provide a computing in memory (CIM) function. 
     A computing word-line RWL&lt; 0 &gt; is coupled to the computing in memory cells CC 1 , CC 2 , CC 3 , and CC 4 ; a computing word-line RWL&lt; 1 &gt; is coupled to the computing in memory cells CC 5 , CC 6 , CC 7 , and CC 8 ; a computing word-line RWL&lt; 2 &gt; is coupled to the computing in memory cells CC 9 , CC 10 , CC 11 , and CC 12 ; and a computing word-line RWL&lt; 3 &gt; is coupled to the computing in memory cells CC 13 , CC 14 , CC 15 , and CC 16 . A computing bit-line RBL&lt; 0 &gt; is coupled to the computing in memory cells CC 1 , CC 5 , CC 9 , and CC 13 . A sense amplifier SA 1  can sense a current of the computing bit-line RBL&lt; 0 &gt; and output a sensed result HVout&lt; 0 &gt;. A computing bit-line RBL&lt; 1 &gt; is coupled to the computing in memory cells CC 2 , CC 6 , CC 10 , and CC 14 . A sense amplifier SA 2  can sense a current of the computing bit-line RBL&lt; 1 &gt; and output a sensed result HVout&lt; 1 &gt;. A computing bit-line RBL&lt; 2 &gt; is coupled to the computing in memory cells CC 3 , CC 7 , CC 11 , and CC 15 . A sense amplifier SA 3  can sense a current of the computing bit-line RBL&lt; 2 &gt; and output a sensed result HVout&lt; 2 &gt;. A computing bit-line RBL&lt; 3 &gt; is coupled to the computing in memory cells CC 4 , CC 8 , CC 12 , and CC 16 . A sense amplifier SA 4  can sense a current of the computing bit-line RBL&lt; 3 &gt; and output a sensed result HVout&lt; 3 &gt;. 
     The memory cell array shown by  FIG.  1    can perform matrix multiplication, that is, calculate a matrix A times a matrix B. For example, the matrix B can be stored in the computing in memory cells CC 1  to CC 16 , and the computing word-lines RWL&lt; 0 &gt; to RWL&lt; 3 &gt; can provide (transmit) elements (data bits) in a row of the matrix A. Each of the computing in memory cells CC 1  to CC 16  can perform a multiplication operation on one element (data bit) of the matrix A and one element (data bit) of the matrix B, and provide a resistance corresponding to a result of the multiplication operation (i.e., provide a corresponding current). The current of each of the computing bit-lines RBL&lt; 0 &gt; to RBL&lt; 3 &gt; is equivalent to a sum of the results of the multiplication operations of the corresponding computing in memory cells. In this way, the memory cell array shown by  FIG.  1    can perform the matrix multiplication. The memory shown by  FIG.  1    can realize the computing in memory. 
       FIG.  2    is a circuit block diagram of a computing in memory cell CC 1  shown by  FIG.  1    according to an embodiment of the disclosure. The other computing in memory cells CC 2  to CC 16  shown by  FIG.  1    can be inferred by referring to the relevant description of the computing in memory cell CC 1 , which is not repeated hereinafter. In the embodiment shown by  FIG.  2   , the computing in memory cell CC 1  includes a memory cell circuit  210 , a semiconductor element  220 , and a semiconductor element  230 . This embodiment does not limit the implementation of the memory cell circuit  210 . According to design requirements, in other embodiments, the memory cell circuit  210  may include memory cells of the SRAM, the memory cells of the DRAM, or other types of memory cells. 
     In the embodiment shown by  FIG.  2   , the memory cell circuit  210  includes a static random access memory cell  211 , a switch M 5 , and a switch M 6 . The static random access memory cell  211  has a data node Q and a data node QB. A first terminal of the switch M 6  is coupled to the data node Q, a second terminal of the switch M 6  is adapted to be coupled to a data bit-line BL, and a control terminal of the switch M 6  is adapted to be coupled to a data word-line WL. A first terminal of the switch M 5  is coupled to the data node QB, a second terminal of the switch M 5  is adapted to be coupled to a data bit-line BLB, and a control terminal of the switch M 5  is adapted to be coupled to the data word-line WL. 
     In the embodiment shown by  FIG.  2   , the static random access memory cell  211  includes a transistor M 1 , a transistor M 2 , a transistor M 3 , and a transistor M 4 . The transistors M 1  and M 3  may be N-channel metal oxide semiconductor (NMOS) transistors. The transistors M 2  and M 4  may be P-channel metal oxide semiconductor (PMOS) transistors. A control terminal (e.g., gate) of the transistor M 1  is coupled to the data node Q, a first terminal (e.g., drain) of the transistor M 1  is coupled to the data node QB, and a second terminal (e.g., source) of the transistor M 1  is adapted to receive a reference voltage (e.g., a ground voltage or other fix voltages). A control terminal (e.g., gate) of the transistor M 2  is coupled to the data node Q, a first terminal (e.g., drain) of the transistor M 2  is coupled to the data node QB, and a second terminal (e.g., source) of the transistor M 2  is adapted to receive a system voltage VDD. A control terminal (e.g., gate) of the transistor M 3  is coupled to the data node QB, a first terminal (e.g., drain) of the transistor M 3  is coupled to the data node Q, and a second terminal (e.g., source) of the transistor M 3  is adapted to receive the reference voltage (e.g., the ground voltage or other fix voltages). A control terminal (e.g., gate) of the transistor M 4  is coupled to the data node QB, a first terminal (e.g., drain) of the transistor M 4  is coupled to the data node Q, and a second terminal (e.g., source) of the transistor M 4  is adapted to receive the system voltage VDD. 
     According to design requirements, the semiconductor element  220  and (or) the semiconductor element  230  may be composed of NMOS transistors, PMOS transistors, or other types of transistors. A first terminal of the semiconductor element  220  is adapted to be coupled to the computing bit-line RBL&lt; 0 &gt;. The sense amplifier SA 1  can serve as a voltage source of the computing bit-line RBL&lt; 0 &gt;. A control terminal of the semiconductor element  220  is coupled to the data node Q in the memory cell circuit  210 . A first terminal of the semiconductor element  230  is coupled to a second terminal of the semiconductor element  220 , and a second terminal of the semiconductor element  230  is adapted to be coupled to a computing bit-line RBLB. 
     According to design requirements, the computing bit-line RBLB can be coupled to a voltage source (not shown) to receive the reference voltage. For instance, the second terminal of the semiconductor element  230  can receive the ground voltage (or other reference voltage) through the computing bit-line RBLB. A control terminal of the semiconductor element  230  is adapted to be coupled to the computing word-line RWL&lt; 0 &gt;. 
       FIG.  3    is an equivalent circuit diagram of the semiconductor elements  220  and  230  shown by  FIG.  2    according to an embodiment of the disclosure. When the computing word-line RWL&lt; 0 &gt; is at logic “1”, a voltage of the computing word-line RWL&lt; 0 &gt; is a bias voltage corresponding a weight. Here, a voltage difference between the bias voltage and a voltage of the computing bit-line RBLB is less than a threshold voltage of the semiconductor element  230 . The weight and the bias voltage may be determined according to design requirements. Therefore, when the computing word-line RWL&lt; 0 &gt; is at logic “1”, the semiconductor element  230  can provide a weight resistance corresponding to the weight. Based on the setting of the bias voltage, the weight resistance may be determined according to design requirements. When the computing word-line RWL&lt; 0 &gt; is at logic “0”, the voltage of the computing word-line RWL&lt; 0 &gt; may be the ground voltage or a voltage sufficient to turn off the semiconductor element  230 . Therefore, when the computing word-line RWL&lt; 0 &gt; is at logic “0”, the semiconductor element  230  is turned off (i.e., the resistance of the semiconductor element  230  is ideally infinite). 
     The sense amplifier SA 1  can provide a voltage (or a current) to the computing bit-line RBL&lt; 0 &gt;. When the data node Q in the memory cell circuit  210  is at logic “1” (e.g., high logic level), the semiconductor element  220  is turned on (i.e., the resistance of the semiconductor element  220  is very small). In the case where the computing word-line RWL&lt; 0 &gt; is at logic 1”, the currents of the semiconductor elements  220  and  230  are mainly determined by the weight resistance of the semiconductor element  230  (because the weight resistance of the semiconductor element  230  is far greater than a turn-on resistance of the semiconductor element  220 ). 
     Moreover, it is also possible that the weight resistance of the semiconductor element  230  is far greater than a parasitic resistance on an electrical path so the weight resistance of the semiconductor element  230  can dominate the current on the electrical path in such a case. When the data node Q in the memory cell circuit  210  is at logic “0” (e.g., low logic level), the semiconductor element  220  is turned off (i.e., the resistance of the semiconductor element  220  is ideally infinite). Therefore, the semiconductor elements  220  and  230  have no current (considering the actual leakage, the currents of the semiconductor elements  220  and  230  are currents close to 0). 
     In terms of operation of the semiconductor elements  220  and  230 , the semiconductor elements  220  and  230  will have the currents (at logic “1”) only when the data node Q is at logic “1” and the computing word-line RWL&lt; 0 &gt; is also at logic “1”. Such operation is equivalent to a multiplication operation performed on logic “1” of the data node Q and logic “1” of the computing word-line RWL&lt; 0 &gt;, i.e., 1*1=1. 
       FIG.  4    is an equivalent circuit diagram of the computing in memory cells CC 1 , CC 5 , CC 9 , and CC 13  shown by  FIG.  1    according to an embodiment of the disclosure. The computing in memory cells CC 1 , CC 5 , CC 9 , and CC 13  shown by  FIG.  4    can be inferred by referring to the relevant description of  FIG.  2    and  FIG.  3   . In the scenario shown by  FIG.  4   , the data nodes Q of the computing in memory cells CC 1 , CC 5 , CC 9 , and CC 13  are at logic “1”, “0”, “1”, and “1”, respectively, and the computing word-lines RWL&lt; 0 &gt;, RWL&lt; 1 &gt;, RWL&lt; 2 &gt;, and RWL&lt; 3 &gt; of the computing in memory cells CC 1 , CC 5 , CC 9 , and CC 13  are all at logic “1”. It is assumed here that based on the setting of the bias voltages of RWL&lt; 0 &gt;, RWL&lt; 1 &gt;, RWL&lt; 2 &gt;, and RWL&lt; 3 &gt;, the currents of the computing in memory cells CC 1 , CC 9 , and CC 13  are I. The sense amplifier SA 1  can sense that the current of the computing bit-line RBL&lt; 0 &gt; is 3*I. Such operation is equivalent to a matrix multiplication operation perform on a row of elements (data bits) [1 0 1 1] of the matrix A and a column of elements (data bits) [1 1 1 1] of the matrix B to generate a matrix multiplication operation result of 1*1+0*1+1*1+1*1=3 (i.e., the current is 3*I). 
       FIG.  5    is a circuit block diagram of the computing in memory cell CC 1  shown by  FIG.  1    according to another embodiment of the disclosure. The other computing in memory cells CC 2  to CC 16  shown by  FIG.  1    can be inferred by referring to the relevant description of the computing in memory cell CC 1 , which is not repeated hereinafter. In the embodiment shown by  FIG.  5   , the computing in memory cell CC 1  includes a memory cell circuit  210 , a semiconductor element  510 , a semiconductor element  520 , and a semiconductor element  530 . The memory cell circuit  210  shown by  FIG.  5    can be inferred by referring to the relevant description of the memory cell circuit  210  shown by  FIG.  2   , which is not repeated hereinafter. 
     Referring to  FIG.  5   , the semiconductor element  510 , the semiconductor element  520 , and (or) the semiconductor element  530  may be composed of NMOS transistors, PMOS transistors, or other types of transistors. A first terminal of the semiconductor element  510  is adapted to be coupled to the computing bit-line RBL&lt; 0 &gt;. The sense amplifier SA 1  can serve as a voltage source of the computing bit-line RBL&lt; 0 &gt;. A control terminal of the semiconductor element  510  is coupled to the data node Q in the memory cell circuit  210 . A first terminal of the semiconductor element  520  is coupled to a second terminal of the semiconductor element  510 , and a control terminal of the semiconductor element  520  is adapted to be coupled to the computing word-line RWL&lt; 0 &gt;. A first terminal of the semiconductor element  530  is coupled to a second terminal of the semiconductor element  520 , and a second terminal of the semiconductor element  530  is adapted to be coupled to a computing bit-line RBLB. According to design requirements, the computing bit-line RBLB can be coupled to a voltage source (not shown) to receive the reference voltage. For instance, the second terminal of the semiconductor element  530  can receive the ground voltage (or other reference voltage) through the computing bit-line RBLB. A control terminal of the semiconductor element  530  is adapted to receive a bias voltage Vweight corresponding to a weight. The weight and the bias voltage Vweight may be determined according to design requirements. A voltage difference between the bias voltage Vweight of the control terminal of the semiconductor element  530  and a voltage of the computing bit-line RBLB is less than a threshold voltage of the semiconductor element  530 . 
       FIG.  6    is an equivalent circuit diagram of the semiconductor elements  510 ,  520 , and  530  shown by  FIG.  5    according to an embodiment of the disclosure. When the computing word-line RWL&lt; 0 &gt; is at logic “1” (e.g., high logic level), the semiconductor element  520  is turned on (i.e., the resistance of the semiconductor element  520  is very small). When the computing word-line RWL&lt; 0 &gt; is at logic “0” (e.g., low logic level), the semiconductor element  520  is turned off (i.e., the resistance of the semiconductor element  520  is ideally infinite). When the data node Q in the memory cell circuit  210  is at logic “1” (e.g., high logic level), the semiconductor element  510  is turned on (i.e., the resistance of the semiconductor element  510  is very small). When the data node Q in the memory cell circuit  210  is at logic “0” (e.g., low logic level), the semiconductor element  510  is turned off (i.e., the resistance of the semiconductor element  510  is ideally infinite). 
     The sense amplifier SA 1  can provide a voltage (or a current) to the computing bit-line RBL&lt; 0 &gt;. In the case where both the semiconductor elements  510  and  520  are turned on, the semiconductor element  530  can provide a weight resistance corresponding to the weight. Based on the setting of the bias voltage Vweight, the weight resistance may be determined according to design requirements. In the case where the semiconductor elements  510  and  520  are both turned on, the currents of the semiconductor elements  510  and  520  are mainly determined by the weight resistance of the semiconductor element  530  (because the weight resistance of the semiconductor element  530  is far greater than turn-on resistances of the semiconductor elements  510  and  520 ). Moreover, it is also possible that the weight resistance of the semiconductor element  530  is far greater than a parasitic resistance on an electrical path so the weight resistance of the semiconductor element  530  can dominate the current on the electrical path in such a case. In the case where the semiconductor elements  510  and (or)  520  are turned off, the semiconductor elements  510  and  520  have no current (considering the actual leakage, the currents of the semiconductor elements  510  and  520  are currents close to 0). 
     In terms of operation of the semiconductor elements  510  and  520 , the semiconductor elements  510  and  520  will have the currents (at logic “1”) only when the data node Q is at logic “1” and the computing word-line RWL&lt; 0 &gt; is also at logic “1”. Such operation is equivalent to a multiplication operation performed on logic “1” of the data node Q and logic “1” of the computing word-line RWL&lt; 0 &gt;, i.e., 1*1=1. 
     Based on the description of  FIG.  6   , the computing in memory cells CC 1 , CCS, CC 9 , and CC 13  can perform matrix multiplication operations. That is, the relevant description of  FIG.  4    can also be analogized to the embodiments shown by  FIG.  5    and  FIG.  6   . It is assumed that the data nodes Q of the computing in memory cells CC 1 , CC 5 , CC 9 , and CC 13  are at logic “1”, “0”, “1”, and “1”, respectively, and the computing word-lines RWL&lt; 0 &gt;, RWL&lt; 1 &gt;, RWL&lt; 2 &gt;, and RWL&lt; 3 &gt; of the computing in memory cells CC 1 , CC 5 , CC 9 , and CC 13  are at logic “1”, “1”, “0”, and “1”, respectively. Therefore, the currents of the computing in memory cells CC 1  and CC 13  are I. The sense amplifier SA 1  can sense that the current of the computing bit-line RBL&lt; 0 &gt; is 2*I Such operation is equivalent to a matrix multiplication operation perform on a row of elements (data bits) [1 0 1 1] of the matrix A and a column of elements (data bits) [1 1 0 1] of the matrix B to generate a matrix multiplication operation result of 1*1+0*1+1*0+1*1=2 (i.e., the current is 2*I). 
       FIG.  7    is a circuit block diagram of the computing in memory cell CC 1  shown by  FIG.  1    according to yet another embodiment of the disclosure. The other computing in memory cells CC 2  to CC 16  shown by  FIG.  1    can be inferred by referring to the relevant description of the computing in memory cell CC 1 , which is not repeated hereinafter. In the embodiment shown by  FIG.  7   , the computing in memory cell CC 1  includes a memory cell circuit  210 , a semiconductor element  710 , a semiconductor element  720 , and a semiconductor element  730 . The memory cell circuit  210  shown by  FIG.  7    can be inferred by referring to the relevant description of the memory cell circuit  210  shown by  FIG.  2   , which is not repeated hereinafter. 
     Referring to  FIG.  7   , the semiconductor element  710 , the semiconductor element  720 , and (or) the semiconductor element  730  may be composed of NMOS transistors, PMOS transistors, or other types of transistors. A first terminal of the semiconductor element  710  is adapted to be coupled to the computing bit-line RBL&lt; 0 &gt;. The sense amplifier SA 1  can serve as a voltage source of the computing bit-line RBL&lt; 0 &gt;. A control terminal of the semiconductor element  710  is adapted to be coupled to the computing word-line RWL&lt; 0 &gt;. The semiconductor element  710  shown by  FIG.  7    can be analogized with reference to the related description of the semiconductor element  520  shown by  FIG.  5   . A first terminal of the semiconductor element  720  is coupled to a second terminal of the semiconductor element  710 . A control terminal of the semiconductor element  720  is coupled to the data node Q in the memory cell circuit  210 . The semiconductor element  720  shown by  FIG.  7    can be analogized with reference to the related description of the semiconductor element  510  shown by  FIG.  5   . 
     A first terminal of the semiconductor element  730  is coupled to a second terminal of the semiconductor element  720 . A second terminal of the semiconductor element  730  is adapted to be coupled to the computing bit-line RBLB. According to design requirements, the computing bit-line RBLB can be coupled to a voltage source (not shown) to receive the reference voltage. For instance, the second terminal of the semiconductor element  730  can receive the ground voltage (or other reference voltage) through the computing bit-line RBLB. A control terminal of the semiconductor element  730  is adapted to receive a bias voltage Vweight corresponding to a weight. The weight and the bias voltage Vweight may be determined according to design requirements. A voltage difference between the bias voltage Vweight of the control terminal of the semiconductor element  730  and a voltage of the computing bit-line RBLB is less than a threshold voltage of the semiconductor element  730 . The semiconductor element  730  shown by  FIG.  7    can be analogized with reference to the related description of the semiconductor element  530  shown by  FIG.  5   . 
     The sense amplifier SA 1  can provide a voltage (or a current) to the computing bit-line RBL&lt; 0 &gt;. In the case where both the semiconductor elements  710  and  720  are turned on, the semiconductor element  730  can provide a weight resistance corresponding to the weight. Based on the setting of the bias voltage Vweight, the weight resistance may be determined according to design requirements. In the case where the semiconductor elements  710  and  720  are both turned on, the currents of the semiconductor elements  710  and  720  are mainly determined by the weight resistance of the semiconductor element  730  (because the weight resistance of the semiconductor element  730  is far greater than turn-on resistances of the semiconductor elements  710  and  720 ). Moreover, it is also possible that the weight resistance of the semiconductor element  730  is far greater than a parasitic resistance on an electrical path so the weight resistance of the semiconductor element  730  can dominate the current on the electrical path in such a case. In the case where the semiconductor elements  710  and (or)  720  are turned off, the semiconductor elements  710  and  720  have no current (considering the actual leakage, the currents of the semiconductor elements  710  and  720  are currents close to 0). 
     In terms of operation of the semiconductor elements  710  and  720 , the semiconductor elements  710  and  720  will have the currents (at logic “1”) only when the data node Q is at logic “1” and the computing word-line RWL&lt; 0 &gt; is also at logic “1”. Such operation is equivalent to a multiplication operation performed on logic “1” of the data node Q and logic “1” of the computing word-line RWL&lt; 0 &gt;, i.e., 1*1=1. 
       FIG.  8    is an equivalent circuit diagram of the computing in memory cells CC 1 , CCS, CC 9 , and CC 13  shown by  FIG.  1    according to another embodiment of the disclosure. The computing in memory cells CC 1 , CCS, CC 9 , and CC 13  shown by  FIG.  8    can be inferred by referring to the relevant description of  FIG.  7   . In the scenario shown by  FIG.  8   , the computing word-lines RWL&lt; 0 &gt;, RWL&lt; 1 &gt;, RWL&lt; 2 &gt;, and RWL&lt; 3 &gt; of the computing in memory cells CC 1 , CCS, CC 9 , and CC 13  are at logic “1”, “0”, “0”, and “1”, respectively, and the data nodes Q of the computing in memory cells CC 1 , CCS, CC 9 , and CC 13  are at logic “1”, “0”, “1”, and “1”, respectively. It is assumed here that the bias voltages Vweight of the computing in memory cells CC 1  and CC 5  are set to bias voltages Vweight 1  so that the current of the computing in memory cell CC 1  is I. It is assumed here that the bias voltages Vweight of the computing in memory cells CC 9  and CC 13  are set to bias voltages Vweight 2  so that the current of the computing in memory cell CC 13  is 2*I That is, in the case where the weights of the computing in memory cells CC 1  and CC 5  are 1, the weights of the computing in memory cells CC 9  and CC 13  are 2. The sense amplifier SA 1  can sense that the current of the computing bit-line RBL&lt; 0 &gt; is 3*I. Such operation is equivalent to a matrix multiplication operation perform on a row of elements (data bits) [1 0 0 1] of the matrix A and a column of elements (data bits) [1 1 1 1] of the matrix B to generate a matrix multiplication operation result of 1*1*1+0*1*1+0*1*2+1*1*2=1+0+0+2=3 (i.e., the current is 3*I). 
       FIG.  9    is a circuit block diagram of a memory according to another embodiment of the disclosure. According to design requirements, the memory shown by  FIG.  9    may be the SRAM, the DRAM, or other types of memories. The memory shown by  FIG.  9    has a memory cell array. The memory cell array includes a plurality of computing in memory (CIM) cells. The number of the computing in memory cells in the memory cell array may be determined according to design requirements. For instance, the memory cell array shown by  FIG.  9    includes computing in memory cells CC 17 , CC 18 , CC 19 , CC 20 , CC 21 , CC 22 , CC 23 , CC 24 , CC 25 , CC 26 , CC 27 , CC 28 , CC 29 , CC 30 , CC 31 , and CC 32 . Each of the computing in memory cells CC 17  to CC 32  can provide a general memory cell function. In addition, each of the computing in memory cells CC 17  to CC 32  can further provide a computing in memory (CIM) function. In the embodiment shown by  FIG.  9   , a direction of the computing bit-lines RBL&lt; 0 &gt; to RBL&lt; 3 &gt; is different from a direction of computing bit-lines VBL&lt; 0 &gt; to VBL&lt; 3 &gt;. Further, in the embodiment shown by  FIG.  9   , a direction of the computing word-lines RWL&lt; 0 &gt; to RWL&lt; 3 &gt; is different from a direction of computing word-lines VWL&lt; 0 &gt; to VWL&lt; 3 &gt;. 
     The computing bit-line RBL&lt; 0 &gt; and the computing word-line VWL&lt; 0 &gt; are coupled to the computing in memory cells CC 17 , CC 21 , CC 25 , and CC 29 . A sense amplifier SA 1  can sense a current of the computing bit-line RBL&lt; 0 &gt; and output a sensed result HVout&lt; 0 &gt;. The computing bit-line RBL&lt; 1 &gt; and the computing word-line VWL&lt; 1 &gt; are coupled to the computing in memory cells CC 18 , CC 22 , CC 26 , and CC 30 . A sense amplifier SA 2  can sense a current of the computing bit-line RBL&lt; 1 &gt; and output a sensed result HVout&lt; 1 &gt;. The computing bit-line RBL&lt; 2 &gt; and the computing word-line VWL&lt; 2 &gt; are coupled to the computing in memory cells CC 19 , CC 23 , CC 27 , and CC 31 . A sense amplifier SA 3  can sense a current of the computing bit-line RBL&lt; 2 &gt; and output a sensed result HVout&lt; 2 &gt;. The computing bit-line RBL&lt; 3 &gt; and the computing word-line VWL&lt; 3 &gt; are coupled to the computing in memory cells CC 20  CC 24 , CC 28 , and CC 32 . A sense amplifier SA 4  can sense a current of the computing bit-line RBL&lt; 3 &gt; and output a sensed result HVout&lt; 3 &gt;. 
     The computing word-line RWL&lt; 0 &gt; and the computing bit-line VBL&lt; 0 &gt; are coupled to the computing in memory cells CC 17 , CC 18 , CC 19 , and CC 20 . A sense amplifier SA 5  can sense a current of the computing bit-line VBL&lt; 0 &gt; and output a sensed result VVout&lt; 0 &gt;. The computing word-line RWL&lt; 1 &gt; and the computing bit-line VBL&lt; 1 &gt; are coupled to the computing in memory cells CC 21 , CC 22 , CC 23 , and CC 24 . A sense amplifier SA 6  can sense a current of the computing bit-line VBL&lt; 1 &gt; and output a sensed result VVout&lt; 1 &gt;. The computing word-line RWL&lt; 2 &gt; and the computing bit-line VBL&lt; 2 &gt; are coupled to the computing in memory cells CC 25 , CC 26 , CC 27 , and CC 28 . A sense amplifier SA 7  can sense a current of the computing bit-line VBL&lt; 2 &gt; and output a sensed result VVout&lt; 2 &gt;. The computing word-line RWL&lt; 3 &gt; and the computing bit-line VBL&lt; 3 &gt; are coupled to the computing in memory cells CC 29 , CC 30 , CC 31 , and CC 32 . A sense amplifier SA 8  can sense a current of the computing bit-line VBL&lt; 3 &gt; and output a sensed result VVout&lt; 3 &gt;. 
     The memory cell array shown by  FIG.  9    can perform matrix multiplication, that is, calculate a matrix A times a matrix B. For example, the matrix B can be stored in the computing in memory cells CC 17  to CC 32 , and the computing word-lines RWL&lt; 0 &gt; to RWL&lt; 3 &gt; can provide (transmit) elements (data bits) in a row of the matrix A. Each of the computing in memory cells CC 17  to CC 32  can perform a multiplication operation on one element (data bit) of the matrix A and one element (data bit) of the matrix B, and provide a resistance corresponding to a result of the multiplication operation (i.e., provide a corresponding current). The current of each of the computing bit-lines RBL&lt; 0 &gt; to RBL&lt; 3 &gt; is equivalent to a sum of the results of the multiplication operations of the corresponding computing in memory cells. In this way, the memory cell array shown by  FIG.  9    can perform the matrix multiplication. The memory shown by  FIG.  9    can realize the computing in memory. 
     The memory cell array shown by  FIG.  9    may further calculate the matrix A times a transpose matrix BT. Here, the transpose matrix BT is a transpose of the matrix B. For example, the matrix B can be stored in the computing in memory cells CC 17  to CC 32 , and the computing word-lines VWL&lt; 0 &gt; to VWL&lt; 3 &gt; can provide (transmit) elements (data bits) in a row of the matrix A. The current of each of the computing bit-lines VBL&lt; 0 &gt; to VBL&lt; 3 &gt; is equivalent to a sum of the results of the multiplication operations of the corresponding computing in memory cells. Regardless of whether “the matrix A times matrix B” or “the matrix A times the transpose matrix BT” is to be performed, the matrix B stored in memory cells CC 17  to CC 32  does not need to be transposed. Therefore, the memory shown in  FIG.  9    can avoid the movement of data as much as possible. 
       FIG.  10    is a circuit block diagram of a computing in memory cell CC 17  shown by  FIG.  9    according to an embodiment of the disclosure. The other computing in memory cells CC 18  to CC 32  shown by  FIG.  9    can be inferred by referring to the relevant description of the computing in memory cell CC 17 , which is not repeated hereinafter. In the embodiment shown by  FIG.  10   , the computing in memory cell CC 17  includes a memory cell circuit  210 , a semiconductor element  1010 , a semiconductor element  1020 , a semiconductor element  1030 , and a semiconductor element  1040 . The memory cell circuit  210  shown by  FIG.  10    can be inferred by referring to the relevant description of the memory cell circuit  210  shown by  FIG.  2   , which is not repeated hereinafter. 
     Referring to  FIG.  10   , the semiconductor element  1010 , the semiconductor element  1020 , the semiconductor element  1020 , and (or) the semiconductor element  1040  may be composed of NMOS transistors, PMOS transistors, or other types of transistors. The semiconductor element  1010 , the semiconductor element  1020 , and the semiconductor element  1030  shown by  FIG.  10    may be inferred by referring to the relevant description of the semiconductor element  710 , the semiconductor element  720 , and the semiconductor element  730  sown by  FIG.  7   , which is not repeated hereinafter. 
     A first terminal of the semiconductor element  1040  shown by  FIG.  10    is adapted to be coupled to the computing bit-line VBL&lt; 0 &gt;. A second terminal of the semiconductor element  1040  is coupled to a first terminal of the semiconductor element  1020 . A control terminal of the semiconductor element  1040  is adapted to be coupled to the computing word-line VWL&lt; 0 &gt;. Here, it is assumed that one element (data bit) of the matrix B is stored in the memory cell circuit  210  of computing in memory cell CC 17 . When “the matrix A times the matrix B” is to be performed, the semiconductor element  1040  can be disabled (or turned off). The computing word-line RWL&lt; 0 &gt; can provide (transmit) one element (a first data bit) of the matrix A to the control terminal of the semiconductor element  1010 , and the memory cell circuit  210  can provide one element (a second data bit) of the matrix B to the control terminal of the semiconductor element  1020 . Accordingly, the computing in memory cell CC 17  can perform a multiplication operation on the first data bit and the second data bit and present a multiplication operation result (current) on the computing bit-line RBL&lt; 0 &gt;. 
     When “the matrix A times the transpose matrix BT” is to be performed, the semiconductor element  1010  can be disabled (turned off). The computing word-line VWL&lt; 0 &gt; can provide (transmit) one element (a first data bit) of the matrix A to the control terminal of the semiconductor element  1040 , and the memory cell circuit  210  can provide one element (a second data bit) of the matrix B to the control terminal of the semiconductor element  1020 . Accordingly, the computing in memory cell CC 17  can perform a multiplication operation on the first data bit and the second data bit and present a multiplication operation result (current) on the computing bit-line VBL&lt; 0 &gt;. 
       FIG.  11    is a circuit block diagram of the computing in memory cell CC 17  shown by  FIG.  9    according to another embodiment of the disclosure. The other computing in memory cells CC 18  to CC 32  shown by  FIG.  9    can be inferred by referring to the relevant description of the computing in memory cell CC 17 , which is not repeated hereinafter. In the embodiment shown by  FIG.  11   , the computing in memory cell CC 17  includes a memory cell circuit  210 , a semiconductor element  1110 , a semiconductor element  1120 , a semiconductor element  1130 , a semiconductor element  1140 , and a semiconductor element  1150 . The semiconductor elements  1110 ,  1120 ,  1130 ,  1140 , and (or)  1150  may be composed of NMOS transistors, PMOS transistors, or other types of transistors. The memory cell circuit  210  shown by  FIG.  11    can be inferred by referring to the relevant description of the memory cell circuit  210  shown by  FIG.  2   . The semiconductor elements  1110 ,  1120 ,  1130 , and  1140  shown by  FIG.  11    can be analogized with reference to the related description of the semiconductor elements  1010 ,  1120 ,  1130 , and  1040  shown by  FIG.  10   , which is not repeated hereinafter. 
     A first terminal of the semiconductor element  1150  shown by  FIG.  11    is coupled to a second terminal of the semiconductor element  1120 . A second terminal of the semiconductor element  1150  is adapted to be coupled to a computing bit-line VBLB. According to design requirements, the computing bit-line VBLB can be coupled to a voltage source (not shown) to receive the reference voltage. For instance, the second terminal of the semiconductor element  1150  can receive the ground voltage (or other reference voltage) through the computing bit-line VBLB. A control terminal of the semiconductor element  1150  is adapted to receive a bias voltage Vweight 3  corresponding to a weight. The weight and the bias voltage Vweight 3  may be determined according to design requirements. A voltage difference between the bias voltage Vweight 3  of the control terminal of the semiconductor element  1150  and a voltage of the computing bit-line VBLB is less than a threshold voltage of the semiconductor element  1150 . 
     The sense amplifier SA 5  shown by  FIG.  9    can provide a voltage (or a current) to the computing bit-line VBL&lt; 0 &gt;. In the case where both the semiconductor elements  1140  and  1120  are turned on, the semiconductor element  1150  shown by  FIG.  11    can provide a weight resistance corresponding to the weight. Based on the setting of the bias voltage Vweight 3 , the weight resistance of the semiconductor element  1150  may be determined according to design requirements. 
       FIG.  12    is a circuit block diagram of the computing in memory cell CC 1  shown by  FIG.  1    according to yet another embodiment of the disclosure. The other computing in memory cells CC 2  to CC 16  shown by  FIG.  1    can be inferred by referring to the relevant description of the computing in memory cell CC 1 , which is not repeated hereinafter. In the embodiment shown by  FIG.  12   , the computing in memory cell CC 1  includes a memory cell circuit  210 , a semiconductor element  1210 , a semiconductor element  1220 , a semiconductor element  1230 , a semiconductor element  1240 , and a NOT gate  1250 . The memory cell circuit  210  shown by  FIG.  12    can be inferred by referring to the relevant description of the memory cell circuit  210  shown by  FIG.  2   , which is not repeated hereinafter. 
     Referring to  FIG.  12   , the semiconductor elements  1210 ,  1220 ,  1230 , and (or)  1240  may be composed of NMOS transistors, PMOS transistors, or other types of transistors. A first terminal of the semiconductor element  1210  is adapted to receive a bias voltage Vweight corresponding to a weight, and a control terminal of the semiconductor element  1210  is adapted to be coupled to the computing word-line RWL&lt; 0 &gt;. A control terminal of the semiconductor element  1220  is coupled to the data node Q in the memory cell circuit  210 . A first terminal of the semiconductor element  1220  is coupled to a second terminal of the semiconductor element  1210 . A control terminal of the semiconductor element  1240  is coupled to a second terminal of the semiconductor element  1220 . A first terminal of the semiconductor element  1240  is adapted to be coupled to the computing bit-line RBL&lt; 0 &gt;. A second terminal of the semiconductor element  1240  is adapted to be coupled to the computing bit-line RBLB. According to design requirements, the computing bit-line RBLB can be coupled to a voltage source (not shown) to receive the reference voltage. For instance, the second terminal of the semiconductor element  1240  can receive the ground voltage (or other reference voltage) through the computing bit-line RBLB. 
     A first terminal of the semiconductor element  1230  is coupled to a second terminal of the semiconductor element  1220 . A second terminal of the semiconductor element  1230  is adapted to receive the reference voltage (e.g., the ground voltage or other fix voltages). A control terminal of the semiconductor element  1230  is adapted to receive an inverted signal of the computing word-line RWL&lt; 0 &gt;. For instance, an input terminal of the NOT gate  1250  is adapted to be coupled to the computing word-line RWL&lt; 0 &gt;, and an output terminal of the NOT gate  1250  can provide the inverted signal to the control terminal of the semiconductor element  1230 . When the computing word-line RWL&lt; 0 &gt; is at logic “1” (e.g., high logic level), the semiconductor element  1230  is turned off. When the computing word-line RWL&lt; 0 &gt; is at logic “0” (e.g., low logic level), the semiconductor element  1230  is turned on to discharge the control terminal of the semiconductor element  1240 . 
     In the case where both the semiconductor elements  1210  and  1220  are turned on, the bias voltage Vweight can be transmitted to the control terminal of the semiconductor element  1240 . The bias voltage Vweight may be determined according to design requirements. A voltage difference between the bias voltage Vweight of the control terminal of the semiconductor element  1240  and a voltage of the computing bit-line RBLB is less than a threshold voltage of the semiconductor element  1240 . Based on the setting of the bias voltage Vweight, the weight resistance of the semiconductor element  1240  may be determined according to design requirements. 
     In summary, the computing word-lines RWL described in the foregoing embodiments can provide one element (a first data bit for control a first semiconductor element to be turned on/off) in the matrix A, and the memory cell circuit can provide one element (a second data bit for controlling a second semiconductor element to be turned on/off) in the other matrix B. The operation of the first semiconductor element (e.g.,  710 ,  1010 ,  1110 , or  1210 ) and the second semiconductor element (e.g.,  720 ,  1020 ,  1120 , or  1220 ) is equivalent to a multiplication operation performed on the first data bit and the second data bit. As a result, the in-memory computing cell can realize in-memory computing. 
     Although the present disclosure has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the disclosure. Accordingly, the scope of the disclosure will be defined by the attached claims and not by the above detailed descriptions.