Patent Publication Number: US-10762815-B2

Title: Display panel with an opening

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 106138608, filed on Nov. 8, 2017. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     BACKGROUND OF THE INVENTION 
     Field of Invention 
     The invention relates to a display panel; more particularly, the invention relates to a display panel having an opening. 
     Description of Related Art 
     At present, screens of smart phones are bigger and bigger, and on the premise of not increasing the volume of the smart phones, many manufacturers of the smart phones have adopted high resolution display panels with narrow border or ultra-narrow border, so as to increase the proportion of the display parts and further expand the display parts. Here, the display part accounts for at least 80% of the whole screen of the smart phone, which seems to have become the standard of the smart phones. However, the sound-optic components (e.g., lenses, speakers, and so forth) on the smart phones reduce the proportion accounted for by the rectangular display panels. As such, a display panel having an opening has been developed to increase the proportion accounted for by the display panel. However, no circuit may be disposed at the opening; hence, a new circuit layout should be developed for the display panel with the opening, so as to drive pixels on the display panel in a normal manner. 
     SUMMARY OF INVENTION 
     The invention provides a display panel which may ensure that pixels around an opening are not squeezed, so as not to lessen display effects of the pixels. 
     In an embodiment of the invention, a display panel includes a substrate, an opening, a first gate driving circuit, a second gate driving circuit, a plurality of first gate lines, a plurality of second gate lines, and a plurality of third gate lines. The substrate has a display area, a first peripheral region, and a second peripheral region, wherein the first peripheral region is located on a first side of the display area, and the second peripheral region is located on a second side of the display area opposite to the first side. The opening is located in the display area. The first gate driving circuit is located in the first peripheral region. The second gate driving circuit is located in the second peripheral region. The first gate lines are located between the opening and the first gate driving circuit, electrically connected to the first gate driving circuit, and electrically insulated from the second gate driving circuit. The second gate lines are located between the opening and the second gate driving circuit, electrically connected to the second gate driving circuit, and electrically insulated from the first gate driving circuit. The third gate lines are located between the first gate driving circuit and the second gate driving circuit, and each of the third gate lines is electrically connected to at least one of the first gate driving circuit and the second gate driving circuit. 
     In the display panel provided in an embodiment of the invention, the first gate lines and the second gate lines are electrically connected to the first gate driving circuit and the second gate driving circuit, respectively; therefore, no additional traces or conductive wires are required. That is, the pixels around the opening are not squeezed, and the display effects of the pixels are not lessened. 
     To make the foregoing features and advantages of the invention clearer and more comprehensible, embodiments are described below in detail with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
         FIG. 1  is a schematic view illustrating a system of a display panel according to a first embodiment of the invention. 
         FIG. 2A  to  FIG. 2D  schematically illustrate driving waveforms of the display panel according to the first embodiment of the invention. 
         FIG. 3  is a schematic view illustrating a system of a display panel according to a first embodiment of the invention. 
         FIG. 4  is a schematic view illustrating a system of a display panel according to a first embodiment of the invention. 
         FIG. 5  is a schematic view illustrating a system of a display panel according to a first embodiment of the invention. 
     
    
    
     DESCRIPTIONS OF THE EMBODIMENTS 
       FIG. 1  is a schematic view illustrating a system of a display panel according to a first embodiment of the invention. With reference to  FIG. 1 , in the present embodiment, the display panel  100  includes a substrate  101 , an opening OP 1 , a first gate driving circuit GD 1 , a second gate driving circuit GD 2 , a plurality of first gate lines (e.g., LG 11 -LG 13 ), a plurality of second gate lines (e.g., LG 21 -LG 23 ), a plurality of third gate lines (e.g., LG 31 -LG 36 ), and a plurality of fan-out lines (e.g., F 11 -F 16 , F 21 -F 26 ). The number of components provided herein is merely exemplary, while the invention is not limited thereto. 
     The substrate  101  has a display area AA, a first peripheral region PH 1 , and a second peripheral region PH 2 . The first peripheral region PH 1  is located on a first side S 1  of the display area AA (e.g., the left side in  FIG. 1 ), the second peripheral region PH 1  is located on a second side S 2  of the display area AA (e.g., the right side in  FIG. 1 ), and the second side S 2  is opposite to the first side S 1 . There are a plurality of pixels PX in the display area AA. In some embodiments, the first peripheral region PH 1  and the second peripheral region PH 2  may be on a side of the substrate  101  or on the back of the substrate  101 . 
     The first gate driving circuit GD 1  is located in the first peripheral region PH 1  and has a plurality of shift registers arranged in the first peripheral region PH 1 . Here, six shift registers LSR 1 -LSR 6  are taken as an example. The second gate driving circuits GD 2  is located in the second peripheral region PH 2  and has a plurality of shift registers arranged in the second peripheral region PH 2 . Here, six shift registers RSR 1 -RSR 6  are taken as an example. The opening OP 1  is located in the display area AA, wherein the opening OP 1  is aligned with a third side S 3  of the display area AA different from the first side S 1  and the second side S 2 , and the opening OP 1  is located in the middle of the third side S 3 . Here, the upper side in  FIG. 1  is taken as an example of the third side S 3 . 
     The first gate lines (e.g., LG 11 -LG 03 ) are located in the display area AA and between the opening OP 1  and the first gate driving circuit GD 1 ; namely, the horizontal position of the first gate lines (e.g., LG 11 -LG 13 ) is the same as the horizontal position of the opening OP 1 . The first gate lines (e.g., LG 11 -LG 13 ) are electrically connected to the first gate driving circuit GD 1  and electrically insulated from the second gate driving circuit GD 2 . That is, the first gate lines (e.g., LG 11 -LG 13 ) are electrically connected to the corresponding shift registers LSR 1 -LSR 3 , respectively, but the first gate lines (e.g., LG 11 -LG 13 ) are not electrically connected to the shift registers RSR 1 -RSR 6 . 
     The second gate lines (e.g., LG 21 -LG 23 ) are located in the display area AA and between the opening OP 1  and the second gate driving circuit GD 2 ; namely, the horizontal position of the second gate lines (e.g., LG 21 -LG 23 ) is the same as the horizontal position of the opening OP 1 . The second gate lines (e.g., LG 21 -LG 23 ) are electrically connected to the second gate driving circuit GD 2  but electrically insulated from the first gate driving circuit GD 1 . That is, the second gate lines (e.g., LG 21 -LG 23 ) are only electrically connected to the corresponding shift registers RSR 1 -RSR 3  respectively and not electrically connected to the shift registers LSR 1 -LSR 6 . 
     The third gate lines (e.g., LG 31 -LG 36 ) are located in the display area AA and between the first gate driving circuit GD 1  and the second gate driving circuit GD 2 ; namely, the horizontal position of the third gate lines (e.g., LG 31 -LG 36 ) is different from the horizontal position of the opening OP 1 . Each of the third gate lines (e.g., LG 31 -LG 36 ) are electrically connected to one of the first gate driving circuit GD 1  and the second gate driving circuit GD 2  in an alternate manner. For instance, some of the third gate lines LG 32 , LG 34 , LG 36  . . . are electrically connected to the shift registers LSR 4 -LSR 6 , and some of the third lines LG 31 , LG 33 , LG 35  . . . are electrically connected to the shift registers RSR 4 -RSR 6 . The rest connection relationship may be deduced from the above with reference to the drawings. Namely, the third gate lines (e.g., LG 32 , LG 34 , LG 36  . . . ) electrically connected to the shift registers LSR 4 -LSR 6  of the first gate driving circuit GD 1  are not adjacent, and the third gate lines (e.g., LG 31 , LG 33 , LG 35  . . . ) electrically connected to the shift registers RSR 4 -RLSR 6  of the second gate driving circuit GD 2  are not adjacent. 
     In addition, in the present embodiment, the number of shift registers (e.g., LSR 1 -LSR 6 ) of the first gate driving circuit GD 1  is the same as the number of shift registers (e.g., RSR 1 -RSR 6 ) of the second gate driving circuit GD 2  but less than the number of rows of pixels PX. Hence, the shift registers LSR 1 -LSR 6  and the shift registers RSR 1 -RSR 6  may extend in a vertical direction. That is, the shift registers LSR 1 -LSR 6  may evenly share the first peripheral region PH 1 , and the shift registers RSR 1 -RSR 6  may evenly share the second peripheral region PH 2 . Thereby, the widths of the shift registers LSR 1 -LSR 6  and the shift registers RSR 1 -RSR 6  (e.g., the lengths in a horizontal direction) may be reduced, so as to reduce the width of borders of the display panel  100 . 
     On the other hand, the number of shift registers (e.g., LSR 1 -LSR 6 ) of the first gate driving circuit GD 1  is the same as the number of shift registers (e.g., RSR 1 -RSR 6 ) of the second gate driving circuit GD 2  and is less than the number of rows of pixels PX. Since the shift registers LSR 1 -LSR 6  and the shift registers RSR 1 -RSR 6  are unable to be aligned with the corresponding first gate lines (e.g., LG 11 -LG 13 ), the corresponding second gate lines (e.g., LG 21 -LG 23 ), or the corresponding third gate lines (e.g., LG 31 -LG 36 ), the first gate lines (e.g., LG 11 -LG 13 ) and the third gate lines (e.g., LG 32 , LG 34 , and LG 36 ) are electrically connected to the corresponding shift registers LSR 1 -LSR 6  through the fan-out lines F 11 -F 16 , respectively, and the second gate lines (e.g., LG 21 -LG 23 ) and the third gate lines (e.g., LG 31 , LG 33 , and LG 35 ) are electrically connected to the corresponding shift registers through the fan-out lines F 21 -F 26 , respectively. 
     In the present embodiment, it is illustrated that the first gate lines (e.g., LG 11 -LG 13 ) are each aligned with the corresponding second gate lines (e.g., LG 21 -LG 23 ); however, in consideration of different circuit designs, the first gate lines (e.g., LG 11 -LG 13 ) are not required to be aligned with the second gate lines (e.g., LG 21 -LG 23 ), which may be determined according to the structure of the display panel  100  and should not be limited to the present embodiment. 
     According to the present embodiment, the first peripheral region PH 1 , the second peripheral region PH 2 , and the display area AA are located on the same surface of the substrate  101 ; however, in other embodiments of the invention, the first peripheral region PH 1  and the second peripheral region PH 2  may be located on a side of the substrate  101  or on the back of the substrate  101  (e.g., on other surfaces relative to the surface of the display area AA). 
     In light of the foregoing, the first gate lines (e.g., LG 11 -LG 13 ) and the second gate lines (e.g., LG 21 -LG 23 ) are driven by the first gate driving circuit GD 1  and the second gate driving circuit GD 2 , respectively; therefore, no additional traces or conductive wires are required. That is, the pixels PX around the opening OP 1  are not squeezed, and the display effects of the pixels PX are not lessened. 
       FIG. 2A  to  FIG. 2D  schematically illustrate driving waveforms of the display panel according to the first embodiment of the invention. With reference to  FIG. 1  and  FIG. 2A , in the present embodiment, the first gate lines (e.g., LG 11 -LG 13 ) are sequentially enabled, the second gate lines (e.g., LG 21 -LG 23 ) are sequentially enabled, and the third gate lines (e.g., LG 31 -LG 36 ) are sequentially enabled. The first gate lines (e.g., LG 11 -LG 13 ) and the second gate lines (e.g., LG 21 -LG 23 ) are simultaneously enabled, and the third gate lines (e.g., LG 31 -LG 36 ) are enabled after the first gate lines (e.g., LG 11 -LG 13 ) are enabled. Here, enabled times of the first gate lines (e.g., LG 11 -LG 13 ), enabled times of the second gate lines (e.g., LG 21 -LG 23 ), and enabled times of the third gate lines (e.g., LG 31 -LG 36 ) are all set as two horizontal scanning time (labeled as 2 h). 
     With reference to  FIG. 1  and  FIG. 2B , in the present embodiment, the first gate lines (e.g., LG 11 -LG 13 ) are sequentially enabled, the second gate lines (e.g., LG 21 -LG 23 ) are sequentially enabled, and the third gate lines (e.g., LG 31 -LG 36 ) are sequentially enabled. The first gate lines (e.g., LG 11 -LG 13 ) and the second gate lines (e.g., LG 21 -LG 23 ) are simultaneously enabled, and the third gate lines (e.g., LG 31 -LG 36 ) are enabled after the first gate lines (e.g., LG 11 -LG 13 ) are enabled. Here, the enabled times of the first gate lines (e.g., LG 11 -LG 13 ), the enabled times of the second gate lines (e.g., LG 21 -LG 23 ), and the enabled times of the third gate lines (e.g., LG 31 -LG 36 ) are all set as one horizontal scanning time (labeled as 1 h). 
     With reference to  FIG. 1  and  FIG. 2C , in the present embodiment, the first gate lines (e.g., LG 11 -LG 13 ) are sequentially enabled, the second gate lines (e.g., LG 21 -LG 23 ) are sequentially enabled, and the third gate lines (e.g., LG 31 -LG 36 ) are sequentially enabled. The first gate lines (e.g., LG 11 -LG 13 ) and the second gate lines (e.g., LG 21 -LG 23 ) are simultaneously enabled, and the third gate lines (e.g., LG 31 -LG 36 ) are enabled after the first gate lines (e.g., LG 11 -LG 13 ) are enabled. Here, the enabled times of the first gate lines (e.g., LG 11 -LG 13 ) and the enabled times of the second gate lines (e.g., LG 21 -LG 23 ) are identically set as one horizontal scanning time (labeled as 1 h), while the enabled times of the third gate lines (e.g., LG 31 -LG 36 ) are set as two horizontal scanning time (labeled as 2 h) and are different from the enabled times of second gate lines (e.g., LG 21 -LG 23 ). 
     With reference to  FIG. 1  and  FIG. 2D , in the present embodiment, the first gate lines (e.g., LG 11 -LG 13 ) are sequentially enabled, the second gate lines (e.g., LG 21 -LG 23 ) are sequentially enabled, and the third gate lines (e.g., LG 31 -LG 36 ) are sequentially enabled. The first gate lines (e.g., LG 11 -LG 13 ) and the second gate lines (e.g., LG 21 -LG 23 ) are simultaneously enabled, and the third gate lines (e.g., LG 31 -LG 36 ) are enabled after the first gate lines (e.g., LG 11 -LG 13 ) are enabled. Here, the enabled times of the first gate lines (e.g., LG 11 -LG 13 ) and the enabled times of the second gate lines (e.g., LG 21 -LG 23 ) are identically set as two horizontal scanning time (labeled as 2 h), while the enabled times of the third gate lines (e.g., LG 31 -LG 36 ) are set as one horizontal scanning time (labeled as 1 h) and are different from the enabled times of the second gate lines (e.g., LG 21 -LG 23 ). 
       FIG. 3  is a schematic view illustrating a system of a display panel according to a first embodiment of the invention. With reference to  FIG. 1  and  FIG. 3 , in this embodiment, the display panel  200  is substantially the same as the display panel  100  except for the position of the opening OP 2 . In this embodiment, the opening OP 2  is still aligned with the third side S 3  of the display area AA but located closer to the first side S 1 , so that the first gate lines (e.g., LG 11   a -LG 13   a ) appear to be shorter, while the second gate lines (e.g., LG 21   a -LG 23   a ) appears to be longer. 
       FIG. 4  is a schematic view illustrating a system of a display panel according to a first embodiment of the invention. With reference to  FIG. 1  and  FIG. 4 , in this embodiment, the display panel  300  is substantially the same as the display panel  100  except for the position of the opening OP 3 . In this embodiment, the opening OP 3  is away from the sides (such as S 1  and S 2 ) of the display area AA; that is, the opening OP 3  is not aligned with any side (such as S 1  or S 2 ) of the display area AA. Therefore, the third gate lines LG 31   a  and LG 32   a  are located above the opening OP 3 . That is, the first gate lines (e.g., LG 11   b -LG 13   b ) and the second gate lines (e.g., LG 21   b -LG 23   b ) are located between the third gate lines LG 32   a  and LG 33 . 
       FIG. 5  is a schematic view illustrating a system of a display panel according to a first embodiment of the invention. With reference to  FIG. 1  and  FIG. 5 , in this embodiment, the display panel  400  is substantially the same as the display panel  100  except for the number of the shift registers LSR 1   a -LSR 9   a  and the number of the shift registers RSR 1   a -RSR 9   a  (e.g., nine shift registers in this embodiment). In this embodiment, the first gate lines (e.g., LG 11 -LG 13 ) are electrically connected to the corresponding shift registers LSR 1   a -LSR 3   a , respectively, the second gate lines (e.g., LG 21 -LG 23 ) are electrically connected to the corresponding shift registers RSR 1   a -RSR 3   a , and each of the third gate lines (e.g., LG 31 -LG 36 ) is electrically connected to the first gate driving circuit GD 1   a  and the second gate driving circuit GD 2   a  at the same time, i.e., each of the third gate lines (e.g., LG 31  to LG 36 ) is electrically connected to the corresponding shift registers (e.g., LSR 4   a  to LSR 9   a ) in the first gate driving circuit GD 1   a  and the corresponding shift registers (e.g., RSR 4   a  to RSR 9   a ) in the second gate driving circuit GD 2   a.    
     In the present embodiment, the number of shift registers (e.g., LSR 1   a -LSR 9   a ) of the first gate driving circuit GD 1   a  is the same as the number of shift registers (e.g., RSR 1   a -RSR 9   a ) of the second gate driving circuit GD 2   a  and is the same as the number of rows of the pixels PX; therefore, the shift registers LSR 1   a -LSR 9   a  are individually aligned with the corresponding first gate lines (e.g., LG 11 -LG 13 ) or the corresponding third gate lines (e.g., LG 31 -LG 36 ), and the shift register RSR 1   a -RSR 9   a  are individually aligned with the corresponding second gate lines (e.g., LG 21 -LG 23 ) or the corresponding third gate lines (e.g., LG 31 -LG 36 ). Therefore, the first gate lines (e.g., LG 11 -LG 13 ) and the third gate lines (e.g., LG 31 -LG 36 ) do not need to be electrically connected to the corresponding shift registers LSR 1   a -LSR 9   a  through fan-out lines, and the second gate lines (e.g., LG 21 -LG 23 ) and the third gate lines (e.g., LG 31 -LG 36 ) do not need to be electrically connected to the corresponding shift registers RSR 1   a -RSR 9   a  through fan-out lines. 
     In view of the above, the display panel provided in the embodiment of the invention at least includes the substrate  101 , the opening (e.g., OP 1 , OP 2 , or OP 3 ), the first gate driving circuit (e.g., GD 1  or GD 1   a ), the second gate driving circuit (e.g., GD 2  or GD 2   a ), a plurality of first gate lines (e.g., LG 11 -LG 13 , LG 11   a -LG 13   a , or LG 11   b -LG 13   b ), a plurality of second gate lines (e.g., LG 21 -LG 23 , LG 21   a -LG 23   a , or LG 21   b -LG 23   b ), and a plurality of third gate lines (e.g., LG 31 -LG 36 , LG 31   a , or LG 32   a ). The substrate has a display area AA, a first peripheral region PH 1 , and a second peripheral region PH 2 . The opening (e.g., OP 1 , OP 2 , or OP 3 ) is located in the display area AA. The first gate driving circuit (e.g., GD 1  or GD 1   a ) is located in the first peripheral region PH 1 . The second gate driving circuit (e.g., GD 2  or GD 2   a ) is located in the second peripheral region PH 2 . The first gate lines (e.g., LG 11 -LG 13 , LG 11   a -LG 13   a , or LG 11   b -LG 13   b ) are located between the opening (e.g., OP 1 , OP 2 , or OP 3 ) and the first gate driving circuit (e.g., GD 1  or GD 1   a ), electrically connected to the first gate driving circuit (e.g., GD 1  or GD 1   a ), and electrically insulated from the second gate driving circuit (e.g., GD 2  or GD 2   a ). The second gate lines (e.g., LG 21 -LG 23 , LG 21   a -LG 23   a , or LG 21   b -LG 23   b ) are located between the opening (e.g., OP 1 , OP 2 , or OP 3 ) and the second gate driving circuit (e.g., GD 2  or GD 2   a ), electrically connected to the second gate driving circuit (e.g., GD 2  or GD 2   a ), and electrically insulated from the first gate driving circuit (e.g., GD 1  or GD 1   a ). The third gate lines (e.g., LG 31 -LG 36 , LG 31   a , or LG 32   a ) are located between the first gate driving circuit (e.g., GD 1  or GD 1   a ) and the second gate driving circuit (e.g., GD 2  or GD 2   a ), and each of the third gate lines (e.g., LG 31 -LG 36 , LG 31   a , or LG 32   a ) is electrically connected to at least one of the first gate driving circuit (e.g., GD 1  or GD 1   a ) and the second gate driving circuit (e.g., GD 2  or GD 2   a ). 
     To sum up, in the display panel provided in an embodiment of the invention, the first gate lines and the second gate lines are electrically connected to the first gate driving circuit and the second gate driving circuit, respectively; therefore, no additional traces or conductive wires are required. That is, the pixels around the opening are not squeezed, and the display effects of the pixels are not lessened. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.