Patent Publication Number: US-9898623-B2

Title: Method for performing an encryption with look-up tables, and corresponding encryption apparatus and computer program product

Description:
BACKGROUND 
     Technical Field 
     The present description relates to techniques for implementing an encryption method using a look-up table. 
     Description of the Related Art 
     Look-up tables (LUTs), also referred to as association tables, are data structures that enable association to any admissible combination of input data of a corresponding (not necessarily unique) configuration of output data. Normally, the use of a look-up table makes it possible to speed up operations, in so far as access to the datum in the table is faster than calculation of the datum itself. 
     Look-up tables are hence frequently used in encryption algorithms, whether hardware or software, to carry out complex calculations. For example, a look-up table, the so-called “Substitution Box” or “S-Box,” is used in the known AES (Advanced Encryption Standard) encryption algorithm for implementing operations such as, for example, the SubBytes operation. 
     In order to discover the key, in particular of symmetric-key block-encryption algorithms, such as the AES algorithm, but even algorithms with non-symmetric public key, it is known to use the so-called side-channel attacks, e.g., attacks that exploit the information that can be derived, through a so-called leakage process, e.g., a process of leakage of information, from physical implementation of the encryption procedure, for example by measuring the energy absorption of the circuit. 
     Several of the countermeasures against the above side-channel attacks exploit the presence of look-up tables in the circuits that implement the algorithms, performing operations of initialization of the values contained in these tables. 
     The way in which the LUT is initialized may impact the effectiveness of protection against side-channel attacks, and it is difficult to obtain protection from high-order attacks. In general, a side-channel attack is defined as v-variant if it combines a number v of time instances, for example clock cycles, of the controlled physical manifestation, and is said to be of the d-th order if it requires statistical momenta of order d to be considered for distinguishing the correct hypotheses from the erroneous ones. 
     It is known, for example, to use as a countermeasure against side-channel attacks operations of linear, Boolean, masking of the data. According to this technique, each datum is masked via a Boolean XOR operation with mask values. It is convenient to incorporate also the mask values in the look-up table. 
     It is known in general to initialize a look-up table where there are input data din, e.g., the data that indicate the address or location of the values to be retrieved in the table, via a first input mask R 1  and to mask output data dout, e.g., the values retrieved at the address or location specified by the input data din, via a first output mask R 2 . This is done by storing in the location of the look-up table corresponding to the address given by din⊕R 1 , e.g., by the XOR operation between the input data din and the first input mask R 1 , a value given by dout⊕R 2 , e.g., by the XOR operation between the output data dout and the first output mask R 2 . This is usually done one at a time for all the possible values of the input data din and performing the operation of storage in the look-up table of the corresponding output data. 
     The so-called high order side-channel attacks attack different points of the algorithm that use the same mask values so that the protection of the aforesaid mask can be removed. In general, given a mask, initialization of the look-up table with this mask and access to the masked data during computation means having at least two different operations in two different cycles that use one and the same mask, the corresponding attack thus qualifying as second-order attack. 
     In the above context, the countermeasures against high-order attacks are usually complex and are very penalizing in terms of latency time and circuit area required for their implementation. Moreover, in hardware implementations, the level of protection may need to be defined at the moment of design, because this affects the design itself and, as has been said, the area of the circuit to be designed. This constitutes a further complexity and drawback. 
     The foregoing is encountered in particular in AES encryption apparatuses, which, as has been said, implement S-Box devices in order to carry out operations, such as, for example, the SubBytes operation, that comprise at least one look-up table, in particular for carrying out the inversion required by the SubBytes operation. 
     The look-up table that implements the S-Box has a considerable size, and this determines a high latency, which limits the performance of the countermeasures against side-channel attacks. 
     BRIEF SUMMARY 
     In an embodiment, a method comprises: initializing a look-up table of an electronic circuit by: applying a logical combination of two of a plurality of address-masks to a masked address, generating an address corresponding to application of one of the two address-masks to an unmasked address; and applying a logical combination of two of a plurality of data-masks to masked data, generating data corresponding to application of one of the two data-masks to unmasked data; and ciphering based on the initialized look-up table. In an embodiment, the method comprises: applying a first of the plurality of address-masks to the unmasked address, generating the masked address; and applying a first of the plurality of data-masks to the unmasked data, generating the masked data. In an embodiment, the method comprises: retrieving the logical combination of two of the plurality of address-masks, without retrieving or generating of the one of the two address-masks by the electronic circuit; and retrieving the logical combination of two of the plurality of data-masks, without retrieving or generating of the one of the two data-masks by the electronic circuit. In an embodiment, the logical combination of two of the plurality of address-masks is an exclusive OR (XOR) between values of a first address-mask and values of a second address-mask of the plurality of address-masks; and the logical combination of two of the plurality of data-masks is an exclusive OR (XOR) between values of a first data-mask and values of a second data-mask of the plurality of data-masks. In an embodiment, the initializing the look-up table comprises, in at least one iteration of a plurality of iterations, applying, to a masked-address-result of a previous iteration, a logical combination of: an address-mask of a logical combination of address-masks of the previous iteration; and a subsequent address-mask of the plurality of address-masks, generating a masked-address-result of the iteration corresponding to application of the subsequent address-mask to the unmasked address; and applying, to a masked-data-result of the previous iteration, a logical combination of: a data-mask of a logical combination of data-masks of the previous iteration; and a subsequent data-mask of the plurality of data-masks, generating a masked-data-result of the iteration corresponding to application of the subsequent data mask to the unmasked data. In an embodiment, the method comprises selecting a number of the plurality of iterations. In an embodiment, the ciphering comprises applying an Advanced Encryption Standard (AES) encryption procedure and a SubBytes operation of said AES encryption procedure includes the initializing of the look-up table. In an embodiment, the method comprises: using a selected one of a plurality of sets of logical combinations of address-masks in a first round of said AES encryption procedure; and reusing the selected one of the plurality of sets of logical combinations of address-masks in another round of said AES encryption procedure, wherein the another round is separated from the first round by at least one round. 
     In an embodiment, a device comprises: a look-up table; and circuitry configured to initializing the look-up table by: applying a logical combination of two of a plurality of address-masks to a masked address, generating an address corresponding to application of one of the two address-masks to an unmasked address; and applying a logical combination of two of a plurality of data-masks to masked data, generating data corresponding to application of one of the two data-masks to unmasked data. In an embodiment, the circuitry is configured to: apply a first of the plurality of address-masks to the unmasked address, generating the masked address; and apply a first of the plurality of data-masks to the unmasked data, generating the masked data. In an embodiment, the circuitry is configured to: retrieve the logical combination of two of the plurality of address-masks, without retrieving or generating of the one of the two address-masks; and retrieve the logical combination of two of the plurality of data-masks, without retrieving or generating of the one of the two data-masks. In an embodiment, the logical combination of two of the plurality of address-masks is an exclusive OR (XOR) between values of a first address-mask and values of a second address-mask of the plurality of address-masks; and the logical combination of two of the plurality of data-masks is an exclusive OR (XOR) between values of a first data-mask and values of a second data-mask of the plurality of data-masks. In an embodiment, the circuitry is configured to initialize the look-up table by, in at least one iteration of a plurality of iterations, applying, to a masked-address-result of a previous iteration, a logical combination of: an address-mask of a logical combination of address-masks of the previous iteration; and a subsequent address-mask of the plurality of address-masks, generating a masked-address-result of the iteration corresponding to application of the subsequent address-mask to the unmasked address; and applying, to a masked-data-result of the previous iteration, a logical combination of: a data-mask of a logical combination of data-masks of the previous iteration; and a subsequent data-mask of the plurality of data-masks, generating a masked-data-result of the iteration corresponding to application of the subsequent data mask to the unmasked data. In an embodiment, the circuitry is configured to selecting a number of the plurality of iterations. In an embodiment, the circuitry is configured to perform an Advanced Encryption Standard (AES) ciphering procedure and a SubBytes operation of said AES ciphering procedure includes the initializing of the look-up table. In an embodiment, the circuitry is configured to: use a selected one of a plurality of sets of logical combinations of address-masks in a first round of said AES ciphering procedure; and reuse the selected one of the plurality of sets of logical combinations of address-masks in another round of said AES ciphering procedure, wherein the another round is separated from the first round by at least one round. In an embodiment, the device comprises an S-Box including the look-up table. In an embodiment, the S-Box comprises a plurality of composite look-up tables each being smaller than the look-up table and the S-Box is configured to perform a non-linear operation in a finite field, using the plurality of composite look-up tables to implement said non-linear operation in a composite field of finite subfields deriving from said finite field. In an embodiment, said composite look-up tables comprise a plurality of flip-flops and the S-Box is configured to initialize the flip-flops using the logical combination of two of the plurality of address-masks and the logical combination of two of the plurality of data-masks. In an embodiment, the circuitry is configured to apply the logical combination of two of the plurality of address-masks to the masked address and to apply the logical combination of two of the plurality of data-masks to masked data in a single clock cycle. 
     In an embodiment, a system comprises: one or more terminals to receive and output data; and security circuitry coupled to the one or more interfaces and including an S-Box configured to initializing one or more look-up tables by: applying a logical combination of two of a plurality of address-masks to a masked address, generating an address corresponding to application of one of the two address-masks to an unmasked address; and applying a logical combination of two of a plurality of data-masks to masked data, generating data corresponding to application of one of the two data-masks to unmasked data. In an embodiment, the security circuitry is configured to: retrieve the logical combination of two of the plurality of address-masks, without retrieving or generating of the one of the two address-masks; and retrieve the logical combination of two of the plurality of data-masks, without retrieving or generating of the one of the two data-masks. In an embodiment, the S-Box is configured to, in at least one iteration of a plurality of iterations, apply, to a masked-address-result of a previous iteration, a logical combination of: an address-mask of a logical combination of address-masks of the previous iteration; and a subsequent address-mask of the plurality of address-masks, generating a masked-address-result of the iteration corresponding to application of the subsequent address-mask to the unmasked address; and apply, to a masked-data-result of the previous iteration, a logical combination of: a data-mask of a logical combination of data-masks of the previous iteration; and a subsequent data-mask of the plurality of data-masks, generating a masked-data-result of the iteration corresponding to application of the subsequent data mask to the unmasked data. In an embodiment, the S-Box is configured to: use a selected one of a plurality of sets of logical combinations of address-masks in a first round of an Advanced Encryption Standard (AES) ciphering procedure; and reuse the selected one of the plurality of sets of logical combinations of address-masks in another round of said AES ciphering procedure, wherein the another round is separated from the first round by at least one round. In an embodiment, the system comprises at least one of: set-top box control circuitry; and smart-card control circuitry. 
     In an embodiment, a non-transitory computer-readable medium&#39;s contents configure an Advanced Encryption Standard (AES) system to perform a method, the method comprising: initializing one or more look-up tables by: applying a logical combination of two of a plurality of address-masks to a masked address, generating an address corresponding to application of one of the two address-masks to an unmasked address; and applying a logical combination of two of a plurality of data-masks to masked data, generating data corresponding to application of one of the two data-masks to unmasked data. In an embodiment, the method comprises: retrieving the logical combination of two of the plurality of address-masks, without retrieving or generating of the one of the two address-masks; and retrieving the logical combination of two of the plurality of data-masks, without retrieving or generating of the one of the two data-masks. In an embodiment, the initializing comprises a plurality of iterations, at least one iteration of the plurality of iterations including, applying, to a masked-address-result of a previous iteration, a logical combination of: an address-mask of a logical combination of address-masks of the previous iteration; and a subsequent address-mask of the plurality of address-masks, generating a masked-address-result of the iteration corresponding to application of the subsequent address-mask to the unmasked address; and applying, to a masked-data-result of the previous iteration, a logical combination of: a data-mask of a logical combination of data-masks of the previous iteration; and a subsequent data-mask of the plurality of data-masks, generating a masked-data-result of the iteration corresponding to application of the subsequent data mask to the unmasked data. In an embodiment, the method comprises: using a selected one of a plurality of sets of logical combinations of address-masks in a first round of an AES ciphering procedure; and reusing the selected one of the plurality of sets of logical combinations of address-masks in another round of said AES ciphering procedure, wherein the another round is separated from the first round by at least one round. 
     In an embodiment, a method uses a look-up table to perform one or more operations of an encryption procedure. The look-up table is initialized. An input mask masks the inputs to the look-up table and an output mask masks the data at output from the look-up table. 
     In an embodiment, an encryption method performs an encryption procedure including operations that comprise accessing a look-up table, said operation of accessing a look-up table comprising an operation of initialization of the look-up table that comprises writing initialization values in said look-up table by applying an input mask to input data that identify a location of said look-up table and an output mask to data at output from a location of said look-up table, wherein at least one second step of initialization of said look-up table is carried out, which comprises: providing at least one second input mask and one second output mask; and computing corresponding initialization values as a function of a logic combination of said first input mask and said second input mask and of a logic combination of said first output mask and said second output mask, in such a way that in the resulting table the input data are masked only by the second input mask and the output data are masked only by the second output mask. In an embodiment, said logic combination is the result of an operation of exclusive OR (XOR) between the values of said first input mask and said second input mask and, respectively, between the values of said first output mask and said second output mask. In an embodiment, the method comprises repeating the computation a given number of times, supplying each time a further input mask and a further output mask, and computing said logic combinations as a function of said further input mask or output mask and of the input mask or output mask provided previously. In an embodiment, said given number of times is chosen at run-time, for regulating the performance or the level of protection of the encryption procedure in regard to side-channel attacks. In an embodiment, said encryption procedure is an AES (Advanced Encryption Standard) encryption procedure and in that said initialization steps are applied to the SubBytes operation of said AES encryption procedure. In an embodiment, the method comprises re-using the masks applied to different data in different rounds of said AES encryption procedure for minimizing the number thereof, in particular by setting a distance of two rounds of AES operations between two values associated to one and the same mask. In an embodiment, an encryption apparatus is configured to implement an encryption procedure disclosed herein. In an embodiment, said encryption procedure is an AES (Advanced Encryption Standard) encryption procedure and said look-up table is comprised in a device of an S-Box type. In an embodiment, said device of an S-Box type comprises at least one module configured for performing a non-linear operation in a finite field (GF(2 8 )) of an encryption method implemented by said encryption apparatus, said module comprising at least one reprogrammable look-up table, said module further comprising a plurality of composite look-up tables that implement said non-linear operation in a composite field of finite subfields deriving from said finite field, each of said composite look-up tables being smaller than a look-up table that is able to implement autonomously said non-linear operation in a finite field. In an embodiment, said composite look-up tables are implemented via flip-flop structures, which are configured for being initialized by said logic combination of said first input mask and second said input mask and said logic combination of said first output mask and said second output mask. In an embodiment, an apparatus is configured for carrying out said initialization operations in one clock cycle. In an embodiment, the apparatus is in a set-top box and/or in a smart card. In an embodiment, a computer program product that can be loaded into the memory of at least one computer, comprises portions of software code suitable for implementing an embodiment of a method disclosed herein. 
     Various embodiments may provide a reasonable synthesis between safety from attacks and computational speed, in particular by varying the number of iterations of the initialization steps or by varying the number of masks used for initialization. Various embodiments may envisage use of S-Boxes for AES encryption. Various embodiments may envisage that this S-Box for AES encryption uses a structure of look-up tables with tower-of-fields architecture implemented via flip-flops, to enable a fast execution, in particular in a single clock cycle, of the steps of initialization of a method disclosed herein. 
     Various embodiments may refer also to an encryption method as likewise to a computer program product that can be loaded into the memory of at least one computer (e.g., a terminal in a network) and comprises portions of software code suitable for carrying out the steps of an embodiment of a method when the program is run on at least one computer. As used herein, the aforesaid computer program product is understood as being equivalent to a computer-readable medium containing instructions for control of the computer system so as to co-ordinate execution of a method according to an embodiment. Reference to “at least one computer” is meant to highlight the possibility of implementation in a modular and/or distributed form. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       Various embodiments will now be described, purely by way of example, with reference to the annexed figures, wherein: 
         FIGS. 1 a  and 1 b    show blocks diagrams illustrating an embodiment of a method; 
         FIGS. 2 a  and 2 b    show blocks diagrams illustrating application of an embodiment of a method to AES encryption; 
         FIG. 3  shows a block diagram illustrating details corresponding to application of an embodiment of  FIG. 2   b;    
         FIG. 4  shows a known block diagram of an S-Box device; 
         FIG. 5  shows blocks composing the non-linear part of the device of  FIG. 4 ; 
         FIG. 6  shows a block diagram illustrating details of blocks of the device of  FIG. 5 ; 
         FIG. 7  shows a block diagram of a device according to an embodiment; 
         FIG. 8  shows a block diagram illustrating details of blocks of an embodiment of the device of  FIG. 7 ; 
         FIG. 9 a    shows a circuit implementation of an element of the device according to the known art; and 
         FIG. 9 b    shows a circuit implementation of an element of the device according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In the ensuing description, numerous specific details are provided in order to facilitate as much as possible understanding of the embodiments provided by way of example. The embodiments may be implemented with or without specific details, or else with other methods, components, materials, etc. In other cases, structures, materials, or operations that are well known are not shown or described in detail so that aspects of the embodiments will not be obscured. Reference in the framework of the present description to “an embodiment” or “one embodiment” means that a given peculiarity, structure, or characteristic described in connection with the embodiment is comprised in at least one embodiment. Hence, recurrence of phrases such as “in an embodiment” or “in one embodiment” in various points of the present description does not necessarily refer to one and the same embodiment. Moreover, the peculiarities, structures, or characteristics may be combined in any convenient way in one or more embodiments. 
     The notations and references are here provided only for convenience of the reader and do not define the scope or the meaning of the embodiments. 
     An embodiment envisages in general carrying out an operation of initialization of the look-up table by masking via a first input mask the data at input to the look-up table and with a first output mask the data at output from the look-up table. It is then envisaged to re-initialize the look-up table via the steps of providing a second input mask and a second output mask, and computing the values of re-initialization of the look-up table as a function of a logic combination of the values of the first and second input masks and of a logic combination of the values of the first and second output masks. The above initialization operations may be carried out on one or more of the composite look-up tables of the S-Box device, which will be described in greater detail in what follows with reference to  FIGS. 4-9 . 
     With reference to  FIGS. 1 a  and 1 b    the encryption method according to an embodiment is now described in greater detail, specifically the initialization procedure  100 , which writing initialization values in the look-up table, applying at least two successive initialization steps,  110  and  120 . 
     With reference to  FIG. 1 a   , represented therein is the step of initialization  110  of a look-up table  50 , for example the look-up table of an S-Box for implementing AES encryption. The reference  110  designates the initialization operations, e.g., the operations of writing in the look-up table  50 . 
     In the framework of the above initialization operation  110 , first-initialization output data dout ref  are sent at input to the look-up table  50 , where they are combined, in an XOR block  110   a , with the first data or output mask R 2 , in order to produce masked output data dout mask . 
     These masked output data dout mask  are written in the look-up table  50  at a masked input datum, or, address, din mask , which is in turn obtained from a first-initialization address din ref  combined in an XOR block  110   b  with the first address or input mask R 1 . 
     The masked output data dout mask =dout ref ⊕R 2  are written in the look-up table  50  at the masked addresses din mask =din ref ⊕R 1  according to the formula
 
 d out mask   =F ( d in mask   ⊕R   1 )⊕ R   2   (1)
 
where F is a generic function F(x) implemented via the look-up table  50 ; in the case provided by way of example, F(x) may correspond to S-Box(x), more specifically to one of the suboperations that constitute the inversion, for example the inversion in GF(2 4 ). If the look-up table  50  were not subject to masking, its content would simply correspond to the function F(x) applied to the inputs. We denote in what follows by LUT 0  the function implemented by the masked look-up table, which supplies the masked output data dout mask .
 
     The first-initialization output data dout ref  and the first-initialization addresses din ref  are plaintext data that may usually come from a reference table that implements the function F (see also in this regard blocks  420 - 423  in  FIG. 9 a   , described in the sequel of the present disclosure). 
     The reference  130  designates, instead, an operation of reading of the data; by accessing the look-up table  50  with the masked address din mask , it returns the output
 
 d out mask =LUT 0 ( d in mask )  (2)
 
       FIG. 1 b    shows, instead, an operation of sequential initialization  120 , or re-initialization, that, according to an embodiment, is carried out after the first initialization  110 . According to an embodiment, it is, in fact, envisaged to define a second input mask R′ 1  and a second output mask R′ 2 , and to evaluate a combination of input masks Δ 1  as XOR operation between the first input mask R 1  and the second input mask R′ 1 , Δ 1 =R′ 1 ⊕R 1 , as well as to evaluate a combination of output masks Δ 2  as XOR operation between the first output mask R 2  and the second output mask R′ 2 , Δ 2 =R′ 2 ⊕R 2  according to the formula
 
 d out′ mask =LUT 0 ( d in′ mask ⊕( R′   1   ⊕R   1 ))⊕( R′   2   ⊕R   2 )  (3)
 
Consequently, once the initialization step  110  has been carried out, instead of repeating the same step  110  and simply using the new, or second, input and output masks R′ 1  and R′ 2  for generating a new masked look-up table, the new content LUT of the table  50  is generated starting from the previous version according to step  120 , e.g., the content LUT 0  deriving from the operation  110 , reading in the aforesaid content LUT 0  of the previous look-up table for each of the possible addresses that can be generated din mask =din ref ⊕R 1  the corresponding value stored, which, for what has been said, is dout mask =dout ref ⊕R 2 . Starting from the masked input datum din mask =din ref ⊕R 1 , a new masked input datum din′ mask =din mask ⊕Δ 1  is generated, where Δ 1 =R′ 1 ⊕R 1 . It should be noted how, if all the terms are rendered explicit, the new masked input datum din′ mask =din mask ⊕Δ 1  will involve cancelling out of the contribution of the first, or past, input mask R 1 , there remaining only the contribution of the second, or new, input mask R′ 1 , so that din′ mask =din ref ⊕R′ 1 .
 
     Likewise, starting from the masked output datum dout mask =dout ref ⊕R 2 , a new masked output datum dout′ mask =dout mask ⊕Δ 2  is obtained, where Δ 2 =R′ 2 ⊕R 2  with a corresponding cancelling out of the contribution of the first, or past, output mask R 2 , there remaining just the contribution of the second, or new, output mask R′ 2  so that dout mask =dout ref ⊕R′ 2 . 
     The new masked output datum dout′ mask  is stored as new content LUT′ of the look-up table  50  at the address corresponding to the new masked input datum, or address, din′ mask . This new content LUT′ of the look-up table  50  is based only upon the content of the second, or new, masks, namely, the input mask R′ 1  and the output mask R′ 2 , as follows:
 
 d out′ mask   =F ( d in′ mask ⊕( R′   1 ))⊕( R′   2 )  (4)
 
     Consequently, at output from the look-up table  50 , we obtain in a reading operation  140 , for a given address specified by input data din′ mask  
 
 d out′ mask =LUT′( d in′ mask )  (5)
 
     In this way, it may be appreciated how the side-channel of each initialization operation provided by step  120  will be linked to the combination of masks Δ 1 =R′ 1 ⊕R 1  rather than to the second input mask R′ 1  alone, whereas the datum is masked by the second input mask R′ 1  alone. The same applies to the output datum and the mask R′ 2 . A high-order attack would thus require three elements: the data masked by the second input mask R′ 1 , the operation of initialization that involves the combination of masks Δ 1 =R′ 1 ⊕R 1 , and at least some other operation that involves the first input mask R 1  alone. 
     The method according to an embodiment has been described, with reference to  FIGS. 1 a  and 1 b   , only as regards a first initialization  110  and a re-initialization  120 . It is clear that the method according to an embodiment can be extended iteratively, using more than two masks. 
     For example, it is possible to carry out an initialization at step  110  with the first input mask R 1 , a second initialization at step  120  with a combination of the first mask R 1  and of the second mask R′ 1 , R′ 1 ⊕R 1 , a third initialization at step  120  with a combination of the second mask R′ 1  and of a third mask R″ 1 , R″ 1 ⊕R′ 1 , a fourth initialization at step  120  with a combination of the third mask R″ 1  and of a fourth mask R′″ 1 , R″ 1 ⊕R″ 1 . The look-up table would then be used for calculations on masked data via the fourth mask R″ 1 . A side-channel attack would in this case require operating on the latter fourth-initialization operation, as well as on all the previous initializations, from the first to the third. 
     It should be noted that in general the method according to an embodiment, also in the embodiment described with reference to  FIGS. 1 a  and 1 b   , may be considered as comprising iteration of an initialization step in which the first masks R 1  and R 2  are set to zero, e.g., the case where the table at start is not masked. 
     The method according to an embodiment envisages in general choosing the given number of steps of iteration, e.g., the number of times of execution, of the operation  120  of initialization at the moment of run-time, without requiring any further hardware in an embodiment, simply applying a criterion of trade-off between performance and level of protection. 
     There now follows a more detailed description of an embodiment of an implementation of the method of  FIGS. 1 a  and 1 b    within an AES encryption procedure. 
       FIG. 2 a    shows an implementation  200  of the AES encryption procedure or algorithm. The steps represented constitute some of the steps for encryption of a 16-byte block, known as AES state. This procedure  200 , as likewise the details of the operations  210 ,  220 ,  230 ,  240  are known to a person skilled in the sector. See, e.g., NIST, Announcing the Advanced Encryption Standard, Federal Information Processing Standards Publication 197 (Nov. 26, 2001). 
     The AES state to be encrypted, designated by A, is subjected to a first SubBytes operation  210 , supplying at output a state B, which is subjected to a set  220  of operations ShiftRows+MixColumns+Add Key, to generate a state C. The operations  210 ,  220  correspond to a first round. Then, in a next round, a second SubBytes operation  230  is carried out, to obtain a state D, as well as a further set  240  of operations ShiftRows+MixColumns+AddKey, to generate a state E. There is carried out a number of rounds envisaged by the procedure  200  according to the number of corresponding round subkeys to be added. The various modes of handling of the AES rounds are in any case in themselves known to a person skilled in the sector. 
     As has been said, the SubBytes operation  210  or  230 , which contains a non-linear portion, as will be described in greater detail in what follows, is carried out with the aid of a Substitution Box, or S-Box, which comprises a look-up table. 
       FIG. 2 a    describes one of the possible (unprotected) implementations of AES.  FIG. 2 b    refers of the same implementation with the introduction of the countermeasure against side-channel attacks. 
     Prior to start of the AES encryption procedure  200  an initial setting of the S-Box is envisaged that serves as base for initialization via the combinations of masks Δ, of the type carried out in step  110  described previously. The masks according to the method are hence applied to the plaintext (e.g., the initial unencrypted AES state). 
     During execution of a round, the S-Box (or S-Boxes where a plurality of them is present) is set with the real masks that have been applied to the AES state via the combinations of masks Δ (initialization  120 ), and the computation envisaged in steps  210  and  220  is then carried out. This is performed at each round. 
     At the end of the AES encryption procedure  200 , the masked S-Boxes are released by carrying out an operation that is the reverse of that of the initial setup, and the masks are removed from the ciphertext that is the product of the AES encryption procedure  200 . 
     During the AES encryption procedure  200 , the SubBytes operation at step  210  or  230  is calculated by itself; hence, the look-up table of the S-Box is initialized just before each use so that the table will incorporate the masks applied to the datum that is to be processed, which in general may differ from one datum to another. 
     It is possible to carry out a number of initializations of the look-up table of the S-Box between two consecutive uses in order to separate the masks associated thereto. 
     This increases protection against side-channel attacks, given that the possibility of leakage towards a side channel depends upon the sequence of combinations of masks Δ. 
     These operations of multiple initializations are carried out also during initial setup and at the end of the procedure for final release of the ciphertext. As for the sequence of multiple initializations, the initial setup envisages applying in sequence combinations of masks Δ to the plaintext in such a way as to obtain, upon completion of this step, the AES state protected by just one real mask, e.g., a mask effectively stored in the system unlike the combinations of masks, without this mask having ever been used. Likewise, at the end of the procedure, the real mask is removed from the ciphertext using only combinations of masks Δ, and never directly the real mask. 
     In order to prevent leakage due to the single masks, just the combinations of masks Δ are generated and passed on for processing, just the combinations of masks Δ are stored in registers, and just the combinations of masks Δ are used for initialization of the look-up table or tables. 
       FIG. 2 b    shows the masks applied by the method with reference to the same encryption procedure  200  as that of  FIG. 2   a.    
     For input to the S-Box (1-byte input of 16-byte AES states), input masks L are provided for masking in the first round (steps  210 - 220 ), and the input masks N are provided for masking in the second round (steps  230 - 240 ). Output masks M are provided for masking in the first round (steps  210 - 220 ), and output masks O are provided for masking in the second round (steps  230 - 240 ). 
     In this regard, it is possible to consider re-employing the masks to minimize their number using, for example, the following criterion: a distance of two rounds between two values associated to one and the same mask. 
       FIG. 3  shows the masks, of 1 byte each, for initialization of each S-Box prior to the procedure  200 . The size of the masks in this step depends upon how many S-Boxes are present. Hence, with 16 S-Boxes there will be 16 bytes for each mask, but with just one S-Box there will be 1 byte for each mask. Input masks R, S are used for the initial setup and final release, and output masks T, U are used for the initial setup and final release. 
     As shown in  FIG. 3 , in a step  310  initialization of the input and of the output with the setup masks R (input mask) and T (output mask) is carried out. Next, in a step  320  an initialization of the table is carried out via the combination of the setup mask R (input mask) with the mask S (input mask). The same is performed on the output using the setup masks T and U. Next, a further initialization step  330  is carried out with the input mask L and the output mask M, shown with reference to  FIG. 2B , by combining them with the setup masks S and U. The operation  210  of the first round, in which the data are masked by the masks L and M, is then performed. 
     Hence, with reference to what is shown in  FIG. 3 , as regards the first two rounds of the AES encryption algorithm in the example in which there is envisaged re-use of the masks every two rounds, the following 16-byte values are generated and stored, which are then also used for initialization of the S-Boxes:
         α=M⊕O   β=U⊕M   γ=T⊕U   δ=T   ε=R⊕S   ζ=R       

     As may be noted, except for the initial masks R and T, only combinations of two logic values are generated and stored. For example, in an embodiment the logic value of the mask M that protects the AES state is never generated alone, is never stored alone, and is never used alone to initialize the S-Boxes. This facilitates ensuring that the side-channel information produced by handling of the values listed above will never be associated to a single mask, but to combinations of masks, which also contribute to the need to gather various points to carry out an attack. 
     In order to maintain consistency between the masks applied to the data during the linear part of the algorithm, indicated by blocks  220  and  240  in  FIG. 2 , further values can be calculated starting from the ones introduced previously, as follows:
 
η= S⊕L =MixCols(α⊕β)⊕[ε⊕MixCols(γ)]⊕[ζ⊕MixCols(δ)]
 
θ= L⊕N =MixCols(α)
 
where:
         L=MixCols(O)   N=MixCols(M)       

     As may be noted, the values to be derived for use of the masks in the linear part of the algorithm are also calculated starting from combinations of two or more logic values, given that the operations to be performed are linear. This ensures that also the side-channel information produced by computation of these values will not be associated to a single mask, but to combinations of masks. 
     From what has been described so far, it emerges clearly how the method according to an embodiment envisages carrying out frequent initializations of the look-up tables. 
     The time of latency involved in an operation of initialization depends upon the size of the look-up table and limits both the performance and the efficiency of the countermeasures against side-channel attacks. 
     In hardware implementations, for requirements linked to the area of the circuits, the look-up tables are usually implemented via a reprogrammable memory such as a RAM. The RAM must be filled for initialization by entering one datum at a time, as has been mentioned, entering all the possible input values and storing the respective output values at the corresponding addresses. Hence, it emerges clearly how the latency required depends upon the size of the look-up table (for example, 256 input data for the AES S-Box). 
     Whenever the mask changes, the look-up table must be initialized with that mask. 
     Known countermeasures envisage: 
     initializing the look-up table before each operation as completely new masks and hence paying the price of all the latencies associated to these operations; or 
     reusing the same masks for different operations and data, rendering, however, the process more vulnerable to high-order side-channel attacks. 
     In implementations that present constraints, for example, of area or of memory size available, a single look-up table is shared between all the bytes of the data, rendering even more evident the disadvantage deriving from initialization. 
     In the light of the initialization operations, in particular in the context of the masking procedure described, the countermeasures against multi-variate high-order attacks may use a look-up table that facilitates: 
     initialization of the entire table in a single cycle, generating all the data to be entered and storing them in the same cycle; it should be noted that falling in any case within the scope of the disclosure are also implementations that operate on a greater number of cycles; the example itself described herein can be used on a number of cycles if the latency due to the initialization operations is accepted; and 
     initialization via the combination of masks Δ; in this way, the leakage that may possibly be analyzed for a side-channel attack is correlated to the combination of masks Δ instead of to the masks proper. 
     Consequently, to meet the need of balancing performance and efficiency in carrying out the initialization operations, in particular the operations of the method according to an embodiment, which involves repeated initialization operations, according to an embodiment an S-Box device is here proposed that has a specific structure of look-up table, in particular the look-up table that implements the function required for the AES S-Box. 
     In order to exploit as much as possible the effectiveness of protection of the initializations within the method according to an embodiment, a device is moreover proposed comprising at least one look-up table, wherein said look-up table is divided into smaller look-up tables, in particular applying the so-called “tower of fields” architecture. The modes of implementation of this architecture with respect to the AES S-Box are in themselves known, in so far as it is known to use the tower-of-fields architecture for reducing the area occupation of the AES S-Box when it is implemented using pure combinational logic. 
     Via the operation of division of the look-up table into smaller tables, it becomes possible to replace the RAM normally used as reprogrammable memory with flip-flop memory structures, in particular structures that define memory registers. This thus facilitates writing all the registers in a single clock cycle and consequently carry out initialization of the entire look-up table, in particular of the entire S-Box, in a single clock cycle. 
     Moreover, as will be described in what follows, implementation of the operations in subfields by the look-up tables facilitates freedom of regulation of the tables in order to improve the properties thereof for an effective protection against side-channel attacks. 
     In this way, advantageously, the countermeasures against side-channel attacks may have a lower impact on the performance of the encryption system, whereas the countermeasures against high-order attacks of the method illustrated in  FIGS. 1 a , 1 b    are, instead, possible also in devices that present a limitation in regard to the area available. 
     In general, with the device proposed comprising a look-up table, the designer has a greater freedom in devising implementation of the tables, in so far as they are no longer linked to the structure of the RAM cell, and a greater freedom in defining the scheme of the countermeasure, in so far as the disadvantage deriving from execution of the initialization operations is removed. 
     The device comprising look-up tables proposed herein can moreover be exploited also for countermeasures in regard to so-called “fault attacks,” e.g., attacks with injection of faults. 
     There now follows a more detailed description of the device comprising an S-Box suitable for operating with the method according to an embodiment. 
     It is envisaged to implement the S-Box isolating the non-linear part of the multiplicative inversion in the finite field, and performing it via finite subfields. 
     The S-Box, which normally operates on the specific Galois field GF(2 8 ) described in the FIPS197 standard, is implemented via decomposition into smaller finite fields, GF(2 4 ) 2  and GF((2 2 ) 2 ) 2 . 
     More precisely, the above operation of composition envisages: 
     a) mapping all the elements of the Galois field GF(2 8 ) over the composite field using an isomorphism; 
     b) computing the multiplying inverse in the composite field; and 
     c) mapping the results of the above computation over the Galois field GF(2 8 ), using the inverse of the isomorphism used for decomposition. 
     As has been said, the procedure of decomposition into smaller finite fields is in itself known and for any detail the reader is referred, for example, to the paper by Satoh et al. “A Compact Rijndael Hardware Architecture with S-Box Optimization,” ASIACRYPT 2001, LNCS 2248, sect. 4.1-4.3, pp. 245-248 (2001). In particular, for the steps a) and c), by way of example, it is possible to use the isomorphism described on page 248, Eq. 13, and for step b) Eqs. 9, 10, 11 on page 247. 
     It is envisaged to implement this approach in an extended way in order to maintain the hardware compact. 
     In particular, it is envisaged to replace the single 256×8 look-up table used in the S-Box with a plurality of smaller reprogrammable look-up tables. 
     As shown in  FIG. 4 , an S-Box  10  presents to the input data din[8], which specify an 8-bit address, two computation modules, of which a module  11  for performing a non-linear operation, in particular inversion of the SubBytes operation. This module  11  is the main reason why the S-Box is implemented via a look-up table. The module  11  for performing a non-linear operation supplies its own output data dout[8], with the result of the inversion, to a portion  12  for performing a linear operation, specifically the affine transformation of the SubBytes operation. The module  12  supplies at output the output data of the S-Box sbox_dout[8], e.g., the input data din[8] on which the SubBytes operation has been carried out. In the above module  12  it is possible to maintain the additive masking, as is applies in a known way in the KeyAddition and MixColumns operations. 
     An embodiment is applied in particular in a look-up table in the module  11  for implementing the inversion. 
       FIG. 4  represents the scheme for the direct S-Box function alone, used for AES encryption. In the case of decryption, the inverse function is necessary, called Sbox −1 . As shown in the paper by Satoh et al. referred to previously, it is possible to re-use the same inversion of block  11  for both functions by adding a further block for the inverse function of the affine transformation. This solution is represented in  FIG. 5  on page 246 of the paper cited. It is thus clear that what is described for block  11  enables implementation of both the direct function and the inverse function of the SubBytes operation. 
     For a better understanding, described in detail in  FIG. 5  is an implementation  22 , which already presents a decomposition in GF(2 4 ) of the function of inversion of the SubBytes operation, which normally operates, instead, on the Galois field GF(2 8 ). The input data din[8] are supplied to a transformation block  24  that implements the isomorphism that maps the elements of the 8-bit field GF(2 8 ), into elements of the subfields GF(2 4 ) by dividing the input into 4-bit blocks. This type of implementation is in itself known (see, for example, the aforementioned paper by Satoh et al.,  FIG. 6 ) and comprises three 4-bit multipliers  25   a ,  25   b ,  25   c  that carry out the function MUL4 in the field GF(2 4 ), a squaring block  26 , a block for multiplication by a constant  31  (corresponding to one of the polynomials chosen for the decomposition into subfields), a first XOR block  27 , a second XOR block  28  for the sum of elements of the field, and a look-up table  29  for the inversion INV4. Upstream of the output is a transformation block  30  that recomposes the 8-bit datum to form the output data dout[8], implementing the inverse isomorphism of block  24 . Operation of this circuit, as has been said, is in itself known. 
     It should be noted that in this known implementation there is a single look-up table  29  that operates on 4-bit data, whereas the rest of the modules is implemented via combinational logic. 
     Each block represented in  FIG. 5  can be in turn decomposed into subfields and hence into blocks that operate on elements of smaller size.  FIG. 6  shows in detail, to facilitate understanding, one of the multiplication modules MUL4 25, which in turn, in a known way, is implemented via three multipliers, three 2-bit multipliers  251 , and one multiplier for multiplication by a constant  252 . This multiplication module MUL4 25 also comprises at input two transformation blocks  253  for dividing the two pairs of 4-bit input data dinA[4] and dinB[4], a transformation block  255  for recomposing the 4-bit output data dout[4], and XOR modules  256  for carrying out the additions. 
     It should be noted that the fact that the multiplier  25  has a pair of 4-bit input data, dinA[4] and dinB[4], renders not convenient implementation thereof via a LUT because it is cumbersome, thus annulling the benefits of the tower-of-fields decomposition. 
     It is envisaged to implement the function of inversion for the module  11  of the S-Box device by exploiting the fact that the algebraic structure enables decomposition of the function. The criteria listed below are followed: 
     implementing the linear operations via combinational logic; 
     implementing the non-linear operations via look-up tables; and 
     dividing the above look-up tables until they have a sufficiently small size; by way of example, for the multiplications it is preferable to use GF((2 2 ) 2 ) 2 , because, as has been said, it would not be convenient to have the module MUL4 25 implemented as a LUT; for the inversion it is possible to choose whether to stop at GF(2 4 ) or also in this case use GF((2 2 ) 2 ) 2 . 
     Each of the look-up tables that implement non-linear operations may be masked by a respective pair of, input and output, masks. 
     In general, the original LUT is made up of 256×8=2048 bits. By appropriately decomposing the blocks with the tower-of-fields method, a number of LUTs are obtained, which, however, are smaller. For example, the inversion in GF(2 4 ) is made up of 16×4=64 bits. Or else, each of the operations MUL2 in GF((2 2 ) 2 ) 2  is made up of 16×2=32 bits. Since in the example described all the LUTs as a whole require a fraction of the memory bits required for the entire LUT of the S-Box, they can be implemented, and in an embodiment are implemented, using flip-flops. 
     In this way, the initialization of the entire LUT can be obtained in a single clock cycle given that all the data can be entered in parallel in one and the same clock cycle. Likewise, all the LUTs can be initialized in parallel. 
       FIG. 7  hence describes in detail an implementation  32  of the inversion module of the S-Box  33  suitable for operating with the method according to an embodiment. Unlike the implementation  22  of  FIG. 5 , the squaring with multiplication by a constant (condensed in a single block  36 ), the inversion INV4 39, in addition to the blocks forming the three 4-bit multipliers  35   a ,  35   b ,  35   c  are obtained through look-up tables that incorporate input and output masks. A transformation block  33  that recomposes the data is provided upstream of the output. 
     In particular, in the above module  32 , 8-bit masks are provided for the input data din[8] and the output data dout[8]. Within the module  32 , additional 4-bit masks are present for the outputs of the squaring block  36 , of the look-up table  39  for the inversion INV4, and of one of the multipliers  35 . Moreover, since, as is shown in  FIG. 7 , the multiplier MUL4 35 is in turn implemented in a way similar to the multiplier  25 , but also in this case condensing in a single block  352  a multiplication with the multiplication by a constant and implementing both this block  352  and the multipliers  351  as look-up tables, three additional 2-bit masks are also provided. 
     Hence, as a whole, the circuit of  FIG. 7  uses 34 independent bits for the mask. Even though the function of multiplication is the same, in practice it is possible to consider that there are different LUTs, because they will have different masks. Each of the three multipliers MUL4 is made up of three look-up tables. The implementation described in  FIG. 7  shows a 4-bit inversion in block  39 , but it is clear that also this block, in variant embodiments, may be decomposed into 2-bit inversion blocks. 
     It should be noted that the decomposition with use of LUTs enables decomposition of the original function, e.g., the S-Box, not necessarily having to use only operations defined over the fields, such as for example multiplication, squaring, and inversion. Even though the known tower-of-fields decompositions are always based on the above few operations, the solution proposed via the use of LUTs enables definition and use of functions that do not have any relation with the above classic operations, or else condensation of a number of operations in one and the same LUT (as is the case described for blocks  25 ,  35 , which carry out squaring with multiplication by a constant), an operation that is problematical to implement with the combinational logic and hence is rarely used. Moreover, since the decomposition of the S-Box device described herein is functional for protection from side-channel attacks, the LUTs can be designed according to this purpose and not for the known use of reducing the area, for example by implementing a decomposition that will maintain redundant operations, which are less efficient from the standpoint of area occupation, but can produce benefits as regards protection against side-channel attacks. 
       FIG. 9 b    shows an implementation of a look-up table  40  according to an embodiment, which operates on 2-bit data at input and 2-bit data at output. In general, the size in bits of the input data may differ from the size in bits of the output data. The scheme of this table  40  may be used for building, for example, the table  351  of  FIG. 8  and implementing the multiplication function, but may moreover be used for implementing any LUT used within the S-Box proposed. In this table  40  the method according to an embodiment described with reference, for example, to  FIG. 1 b    is moreover used. 
     Designated by  410 - 413  are registers that operate as memory cells for the data contained in the LUT, which are designated, respectively, by d 0 , . . . , d 3 . Each of these data d 0 , . . . , d 3  are sent from the output of the respective register  410 - 413  in parallel to a block  419  for selection of the output datum dout and to a respective XOR module  400 - 403 , which carries out thereon the logic XOR with the logic combination of output masks Δ 2 . Next, an interconnection matrix  405 , provided with a number of multiplexers, under the control of the logic combination of input masks Δ 1 , carries out masking, storing the outputs of the XOR modules  400 - 403  in the registers  410 - 413  in the order indicated by the logic combination of input masks Δ 1 . 
     The selection block  419  is a set of multiplexers, which, in a way of in itself known, under the control of the input datum din, which contains the address of the data in the LUT, selects the appropriate output of the registers  410 - 413 , supplying it as output datum dout, thus implementing the reading operation  140  of  FIG. 1   b.    
     It is emphasized how the look-up-table structure  40  of  FIG. 9 b    is here referred to use with the AES S-Box device, but this structure  40  can be used for implementing any look-up table that can be initialized via the combinations of masks of the initialization method, even in other encryption algorithms. 
       FIG. 9 a    shows by way of comparison the implementation of a look-up table  41  according to the known art that uses a method similar to the operation  110  described with reference to  FIG. 1 a   . Reference numbers that are the same as the ones used in  FIG. 9 b    identify similar components. As may be noted, the XOR modules  400 - 403  receive at input the first output mask R 2  and directly the reference initialization values F(0), . . . , F(3), which may be non-modifiable pre-set values, e.g., hardwired, or, as in the example described, may be contained in specific registers  420 - 423 , storing the outputs of the XOR modules  400 - 403  in the registers  410 - 413  in the order indicated by the first input mask R 1 . Advantageously, instead, the table  40  of  FIG. 9 b    sends to the XOR modules  400 - 403  the logic combinations of output masks Δ 2  and the data d 0 , . . . , d 3  from the output of the respective register  410 - 413 , storing the outputs of the XOR modules  400 - 403  in the registers  410 - 413  in the order indicated by the logic combination of input masks Δ 1 . 
     The encryption method according to an embodiment, via operations of initialization based upon combinations of masks, means that the possible correlations obtained by side-channel attacks are always linked to these combinations, but not to the values of the individual masks that originate them. 
     An embodiment of the proposed device comprising look-up tables, via a decomposition of the table of the S-Box of the AES encryption into smaller tables, implements these tables via flip-flop structures, which can be updated in a single clock cycle. Consequently, the encryption method according to an embodiment implemented in an apparatus that comprises the S-Box device according to an embodiment can be executed in a fast way, enabling a repeated and flexible use of the initialization steps that renders the AES encryption procedure even more impervious to side-channel attacks also of high order. 
     In this way, the countermeasures against side-channel attacks can have a lower impact on the performance of the encryption system, whereas, instead, it is possible to implement the countermeasures against high-order attacks according to the method of an embodiment also in devices that present limitation in regard to the area available. 
     The method according to an embodiment applies in general to data stored in data media and in particular to data stored in data media of any apparatus that envisages execution of an encryption algorithm comprising operations that include access to a look-up table, for example an AES encryption system, for example in set-top boxes or smartcards. This AES encryption system can be regarded as a peripheral within a System-on-Chip, which is not used as stand-alone component, but is integrated in a chip of a smartcard or a chip of a set-top box or even chips of other applications that require AES encryption. 
     In general, the above apparatus comprises or is associated to data-processing means and, in particular, comprises one or more processors. 
     Some embodiments may take the form of or include computer program products. For example, according to one embodiment there is provided a computer readable medium including a computer program adapted to perform one or more of the methods or functions described above. The medium may be a physical storage medium such as for example a Read Only Memory (ROM) chip, or a disk such as a Digital Versatile Disk (DVD-ROM), Compact Disk (CD-ROM), a hard disk, a memory, a network, or a portable media article to be read by an appropriate drive or via an appropriate connection, including as encoded in one or more barcodes or other related codes stored on one or more such computer-readable mediums and being readable by an appropriate reader device. 
     Furthermore, in some embodiments, some of the systems and/or modules and/or circuits and/or blocks may be implemented or provided in other manners, such as at least partially in firmware and/or hardware, including, but not limited to, one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuitry, logic gates, standard integrated circuits, state machines, look-up tables, controllers (e.g., by executing appropriate instructions, and including microcontrollers and/or embedded controllers), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., as well as devices that employ RFID technology, and various combinations thereof. 
     The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
     These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.