Patent Publication Number: US-6711063-B1

Title: EEPROM memory cell array architecture for substantially eliminating leakage current

Description:
FIELD OF THE INVENTION 
     The present invention relates to EEPROM memory cell array architectures such as are used, for example, in programmable logic devices (PLDs) such as complex programmable logic devices (CPLDs). More particularly, the present invention concerns a memory cell array architecture that substantially eliminates leakage current to allow for reading memory cells in a memory cell array of, for example, a CPLD at lower voltages than are possible with prior art architectures, thereby facilitating development of low voltage applications. 
     DESCRIPTION OF THE PRIOR ART 
     Referring to FIG. 1, a conventional electrically erasable programmable read-only memory (EEPROM) cell  20  is shown which is commonly used to implement embedded non-volatile memory circuitry in a CPLD, wherein the EEPROM cell  20  serves as a memory cell in an array of memory cells operable to store a designed configuration. As illustrated, each such EEPROM cell  20  broadly comprises a bitline read (BLrd) node  22 ; a bitline program (BLpr) node  24 ; a bitline ground (BLgrnd) node  26 ; an access gate (AG) node  28 ; an AG program transistor  30 ; an AG read transistor  32 ; a floating gate (FG) memory transistor  34 ; and a control gate (CG) node  36 . 
     Referring also to FIG. 2, a prior art memory cell array architecture  40  is shown wherein a plurality of the EEPROM cells  20  are connected to bitlines  42  of programming paths and read paths. The BLrd nodes  22  of all of the EEPROM cells  20  in each bitline  42  are connected to a sense amplifier (sense-amp)  46 . The BLgrnd nodes  26  of all of the EEPROM cells  20  in the bitline  42  are connected together and to a common ground. The result is that all leakage currents from unselected EEPROM cells  20  are added together along bitline  42 . In order to keep the total leakage current sufficiently low, so as not to trip the sense amplifier  46 , the threshold voltage (Vt) of read access gate transistor  32  needs to be sufficiently high, or about 0.8V. Consequently, in order to reliably read a selected cell, this requires that the gate voltage on access gate node  28 , or Vdd, to be sufficiently high. The power supply Vdd would therefore need to be such that Vg−Vt=Vdd−Vt=1.0V, or Vdd=0.8+1.0=1.8V. 
     Current trends toward lower V dd  in integrated circuit electronics pose new challenges to circuit implementation. One problem that has arisen, for example, is that threshold voltages (Vt) in CMOS transistors, such as, for example, the EEPROM cell AG read transistor  32 , cannot fall below a certain lower limit without giving rise to undesirable off-state leakage currents. This limitation is encountered when reading the EEPROM cells  20  using the sense-amp  46 . 
     In the prior architecture  40 , the read path bitlines  42 , in which the AG transistor  32  of each EEPROM cell  20  is connected in series with its FG memory transistor  34 , are connected in parallel. The sense-amp  46  triggers at a bitline current of approximately 6 μA. When V dd =1.8V and V t =0.8V for the AG read transistor  32 , gate voltage (V g )−V t =1.0V. With this drive voltage, the EEPROM cells  20  will deliver sufficient read current, approximately 15 μA, to reliably trigger the sense-amp  46 . Maximum allowable leakage current from a non-selected EEPROM cell  20 , however, can be no more than the total bitline leakage current, which is less than approximately 1 μA, so that the leakage current doesn&#39;t trigger the sense-amp  46 . Because each bitline  42  may include, for example,  100  EEPROM cells  20  connected in parallel, the maximum leakage current per EEPROM cell  20  must be less than 10 nA. 
     Furthermore, because reading of the memory cell array is triggered on power-up of the CPLD, the V dd  at the time of power-on reset (POR) will be lower than the target V dd  by approximately 0.4V, making V dd =1.4V at power-up. Therefore, the maximum allowable read current for a selected programmed (low V t ) EEPROM cell  20  is 
     
       
         I read &gt;˜10 μA when V dd =1.4V. 
       
     
     At the same time, the EEPROM cell  20  must not exceed the maximum allowable leakage current for an unselected EEPROM cell  20 , which, as mentioned, is 
     
       
         maximum V dd =1.9V so I off &lt;10 nA. 
       
     
     It is possible to accomplish this with an AG read transistor  32  having a V t  of 0.8V. Unfortunately, lowering the V t  increases the leakage current by approximately one order of magnitude per 0.1V t  shift, making it practically impossible to lower the V t  of the AG read transistor  32  below 0.8V without risking a read failure due to the EEPROM cell read path bitline leakage current. Thus, with prior art architectures, it is not possible to meet read reliability requirements as V dd  is lowered below 1.8V. 
     Due to the above-identified and other problems and disadvantages in the art, there exists a distinct need for an improved memory cell array architecture. 
     SUMMARY OF THE INVENTION 
     The present invention solves the above-described and other problems and disadvantages in the prior art to provide a memory cell array architecture that substantially eliminates leakage current to allow for reading memory cells in a memory cell array at lower voltages than are possible with prior art architectures, thereby advantageously facilitating development of low voltage applications, particularly hand-held low voltage battery-powered devices. The architecture may be used, for example, to implement embedded non-volatile memory circuitry in a PIC device such as a CPLD, wherein the memory cells are conventional EEPROM cells. 
     In the architecture of the present invention, all of the BLgrnd nodes of the EEPROM cells in the same wordline are connected together in a common BLgrnd line, and each common BLgrnd line is connected through a select transistor to ground. In one embodiment, the select transistor is driven by the same high voltage wordline (HV WL) signal used to select the AG read transistor of each EEPROM cell in the wordline. This results in all unselected EEPROM cells in each bitline having floating BLgrnd nodes, thereby eliminating the off-state leakage current contribution from unselected EEPROM cells. The V t  of the AG read transistor can then be reduced from 0.8V to a significantly lower value, such as, for example, between approximately 0.4V and 0.5V, thereby allowing the EEPROM cell to be successfully read at a correspondingly lower V dd  voltage. Furthermore, since the access gate read transistor  32  and the access gate programming transistor  30  typically have the same Vt&#39;s, the lower Vt of the AG programming transistor  30  results in a lowered voltage drop across the AG programming transistor, which results in a corresponding improvement in the programming efficiency of the cell and a lower programmed Vt of the FG memory transistor  34 , in turn leading to a higher read current in a selected cell. 
     Thus, it will be appreciated that the memory cell array architecture of the present invention provides a number of substantial advantages over prior art architectures, including, for example, that the leakage current contribution from unselected EEPROM cells is advantageously eliminated. Furthermore, the architecture advantageously allows for reducing the V t  of the AG read and programming transistors from 0.8V to a significantly lower value, such as, for example, approximately between 0.4V and 0.5V, thereby allowing the EEPROM cell to be successfully read at a correspondingly lower V dd  voltage. Additionally, the lower V t  of the AG programming transistor of each EEPROM cell allows for improved cell programming because the voltage drops across the AG programming transistor is reduced, which results in a corresponding improvement in the programmed V t  of the FG memory transistor. 
     These and other important features of the present invention are more fully described in the DETAILED DESCRIPTION below. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A preferred embodiment of the present invention is described in detail below with reference to the attached drawing figures, wherein: 
     FIG. 1 is a circuit schematic of a conventional EEPROM cell; 
     FIG. 2 is a circuit schematic of a prior art EEPROM cell array architecture; 
     FIG. 3 is a circuit schematic of a first embodiment of the EEPROM cell array architecture of the present invention, wherein a virtual ground connection is provided by an HV NMOS select transistor; and 
     FIG. 4 is a circuit schematic of a second embodiment of the EEPROM cell array architecture of the present invention, wherein the virtual ground connection is provided by an LV NMOS select transistor. 
    
    
     DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT 
     Referring to FIG. 3, a memory cell array architecture  50  is shown constructed in accordance with a first embodiment of the present invention. The architecture  50  substantially eliminates leakage current to allow for reading memory cells  20  in a memory cell array at lower voltages than are possible with prior art architectures  40  (see, for example, FIG.  2  and the discussion above), thereby advantageously facilitating development of low voltage applications, particularly hand-held low voltage battery-powered devices. As illustrated, the architecture  50  may be used to implement embedded non-volatile memory circuitry in a PLD device such as a CPLD, wherein the memory cells  20  are conventional EEPROM cells  20  (see FIG.  1  and the discussion above). 
     Referring to FIG. 2, in prior art architectures, all of the BLgrnd nodes  34  of the EEPROM cells  20  in a bitline  42  are connected together and connected to a common ground. The result is that all leakage currents from unselected EEPROM cells  20  are added together, thereby requiring a relatively high V dd  or risk exceeding the maximum allowable leakage current. 
     Referring again to FIG. 3, in the architecture  50  of the present invention, all of the BLgrnd nodes  34  of the EEPROM cells  20  in the same wordline  52  are connected together in a common BLgrnd line  54 , and each virtual ground common BLgrnd line  54  is connected through a select transistor  56  to ground. In this first embodiment, the select transistor  60  is driven by the same wordline (HV WL) signal used to select the AG transistors  30 , 32  of each EEPROM cell  20  in the wordline  52 . This results in all unselected EEPROM cells  20  in each bitline  42  having floating virtual ground BLgrnd nodes  34 , thereby eliminating the off-state leakage current contribution from unselected EEPROM cells  20 . For a selected EEPROM cell  20 , the vitual ground BLgrnd node  34  is connected to ground. 
     This simplifies the EEPROM cell requirements in that the leakage current from a selected erased EEPROM cell  20  must now be less than 100 nA and the read current from a selected programmed EEPROM cell  20  must now be greater than 10 μA. Because this current ratio is only a factor of 100, it becomes possible to reduce the V t  of the AG read transistor  32  from 0.8V to a significantly lower value, such as, for example, between approximately 0.4V and 0.5V, thereby allowing the EEPROM cell  20  to be successfully read at a correspondingly lower V dd  voltage. 
     Furthermore, the lower V t  of the AG programming transistor  30  of each EEPROM cell  20  allows for improved cell programming because the voltage drop across the AG programming transistor  30  is reduced, which results in a corresponding improvement in the programmed V t  of the FG memory transistor  34   
     With regard to the select transistors  60 , it is required that they not limit the read current, and that, for an unselected wordline  52 , the leakage current  1   off  be less than 10 nA. This is accomplished by making the width and the length of virtual ground select transistor  60  sufficiently large. 
     In the first embodiment, the select transistors  60  are high voltage (HV) NMOS transistors. This may be the most straightforward implementation because, as mentioned, the same HV WL signal that selects the AG read transistors  32  of the EEPROM cells  20  of each wordline  52  can be used to drive the select transistor  60 . For some applications, however, given that the select transistors  60  must carry the total read current of all of the EEPROM cells  20  along the wordline  52 , the physical size of the select transistors  60  could be substantial. 
     Referring also to FIG. 4, in the second embodiment of the array architecture  150 , if it is desirable that the physical size of the select transistors  60  be minimized, the select transistors  60  are low voltage (LV) NMOS transistors. This is possible because the maximum voltage in the read path is V dd . In this second embodiment, however, the select transistors  60  must be driven by a separate low voltage wordline (LV WL) signal on a low voltage wordline  153  rather than the HV WL signal of the first embodiment. 
     From the preceding description, it will be appreciated that the various preferred embodiments of the memory cell array architecture  50  of the present invention provide a number of substantial advantages over prior art architectures  40 , including, for example, that the leakage current contribution from unselected EEPROM cells  20  is advantageously eliminated. Furthermore, the architecture  50  advantageously allows for reducing the V t  of the AG read transistors  32  from 0.8V to a significantly lower value, such as, for example, approximately between 0.4V and 0.5V, thereby allowing the EEPROM cell  20  to be successfully read at a correspondingly lower V dd  voltage. Additionally, the lower V t  of the AG programming transistor  30  of each EEPROM cell  20  allows for improved cell programming because the voltage drop across the AG programming transistor  30  is reduced, which results in a corresponding improvement in the V t  of the FG memory transistor  34 . 
     Although the invention has been described with reference to the preferred embodiments illustrated in the attached drawings, it is noted that equivalents may be employed and substitutions made herein without departing from the scope of the invention as recited in the claims.