Patent Publication Number: US-11050431-B1

Title: Single-ended successive approximation register analog-to-digital converter

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to a successive approximation register (SAR) analog-to-digital converter (ADC), and more particularly to switchably operate in a single-ended mode or a differential mode. 
     2. Description of Related Art 
     A successive approximation register (SAR) analog-to-digital converter (ADC) is a type of ADC that coverts an analog signal to a digital equivalent of the signal. The SAR ADC performs conversion by comparison and searching through all possible quantization levels to obtain a digital output. The SAR ADC requires less silicon area and power consumption than other ADC architectures. 
     A differential SAR ADC is one type of SAR ADC that digitizes differential analog input voltages. A single-ended SAR ADC is another type of SAR ADC that digitizes single analog input voltage relative to ground. Single-ended SAR ADC can simplify ADC driver requirement with reduced complexity and lower power dissipation, but has narrower dynamic range and less SNR performance than the differential SAR ADC. 
     The single-ended SAR ADC commonly suffers inadequate comparison benchmark due to a lack of clear voltage source, and thus ordinarily generates an inaccurate output code. A need has arisen to propose a novel scheme to overcome drawbacks of the conventional single-ended SAR ADC. 
     SUMMARY OF THE INVENTION 
     In view of the foregoing, it is an object of the embodiment of the present invention to provide a single-ended successive approximation register (SAR) analog-to-digital converter (ADC) capable of generating a comparison benchmark by self-charge redistribution in a self-based manner. 
     According to one embodiment, A single-ended successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC), a second DAC, a comparator and a SAR controller. The first DAC is coupled to receive an input voltage via a first sampling switch. The second DAC is coupled to receive a ground voltage via a second sampling switch. The comparator has a positive input node coupled to receive a first output voltage of the first DAC, and a negative input node coupled to receive a second output voltage of the second DAC. The SAR controller controls switching of the first DAC and the second DAC according to a comparison output of the comparator, thereby generating an output code. The first DAC includes a first capacitor associated with a most significant bit (MSB) of the output code, and a second capacitor associated with other bit or bits of the output code; and the second DAC includes a first capacitor associated with a MSB of the output code, and a second capacitor associated with other bit or bits of the output code. A bottom plate of the first capacitor of the second DAC is connected to a negative reference voltage in all phases. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  shows a block diagram illustrating a single-ended successive approximation register (SAR) analog-to-digital converter (ADC) according to one embodiment of the present invention; 
         FIG. 1B  shows a detailed circuit diagram of the single-ended SAR ADC of  FIG. 1A ; 
         FIG. 2A  to  FIG. 2C  show configurations of the single-ended SAR ADC before sampling, in sampling phase and in top-plate level shifting phase, respectively; and 
         FIG. 3  shows exemplary waveforms at the input node and the output node of the (first/second) DAC. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1A  shows a block diagram illustrating a single-ended successive approximation register (SAR) analog-to-digital converter (ADC)  100  according to one embodiment of the present invention, and  FIG. 1B  shows a detailed circuit diagram of the single-ended SAR ADC  100  of  FIG. 1A . 
     In the embodiment, the single-ended SAR ADC  100  may include a first digital-to-analog converter (DAC)  11 A coupled, at its input node, to receive an input voltage V i  via a first sampling switch SW 1 . The input voltage V i  may swing between a full-scale voltage (e.g., 1 volt) and a ground voltage (e.g., 0 volt). The single-ended SAR ADC  100  may include a second DAC  11 B coupled, at its input node, to receive the ground voltage via a second sampling switch SW 2 . 
     The single-ended SAR ADC  100  of the embodiment may include a comparator  12  having a positive input node coupled to receive a first output voltage V o1  (at an output node) of the first DAC  11 A, and a negative input node coupled to receive a second output voltage V o2  (at an output node) of the second DAC  11 B. The single-ended SAR ADC  100  of the embodiment may include a first boost switch SW b1  coupled between the positive input node of the comparator  12  and a common mode boost voltage V com_boost , and a second boost switch SWb 2  coupled between the negative input node of the comparator  12  and the common mode boost voltage V com_boost . The first boost switch SW b1  and the second boost switch SW b2  can raise a common mode voltage for the comparator  12 . 
     The single-ended SAR ADC  100  of the embodiment may include a SAR controller  13  configured to control switching of the first DAC  11 A and the second DAC  11 B according to a comparison output of the comparator  12 , thereby generating an output code from a most significant bit (MSB) to a least significant bit (LSB) in sequence. The SAR controller  13  may enter a single-ended mode or a differential mode according to a mode signal Sm. The single-ended mode is assumed in the following embodiment. 
     Specifically, the first DAC  11 A may include a first capacitor C T1 , a second capacitor C T2  and an (optional) redundant capacitor C redun . The first capacitor C T1  is associated with the most significant bit (MSB) of the output code, and the second capacitor C T2  is associated with other bit(s) of the output code. In the embodiment, the second capacitor C T2  may represent a plurality of parallel-connected capacitors collectively. Top plates of the first capacitor C T1 , the second capacitor C T2  and the redundant capacitor C redun  may be connected together to the input node of the first DAC  11 A. Bottom plates of the first capacitor C T1 , the second capacitor C T2  and the redundant capacitor C redun  may be switchably connected to a positive reference voltage V refp  (e.g., 1 volt) and a negative reference voltage V refn  (e.g., 0 volt). The first DAC  11 A may include a boost capacitor C com_boost  coupled between the input node and the output node of the first DAC  11 A for raising the common mode voltage for the comparator  12 . 
     In one embodiment, the first DAC  11 A may include a first parasitic capacitor C para1  having a top plate coupled to the input node of the first DAC  11 A, and a bottom plate coupled to receive a parasitic voltage V para . The first DAC  11 A may include a second parasitic capacitor C para2  having a top plate coupled to the output node of the first DAC  11 A, and a bottom plate coupled to receive the parasitic voltage V para . 
     Similarly, the second DAC  11 B may include a first capacitor C T1 , a second capacitor C T2  and an (optional) redundant capacitor C redun . The first capacitor C T1  is associated with the most significant bit (MSB) of the output code, and the second capacitor C T2  is associated with other bit(s) of the output code. In the embodiment, the second capacitor C T2  may represent a plurality of parallel-connected capacitors collectively. Top plates of the first capacitor C T1 , the second capacitor C T2  and the redundant capacitor C redun  are connected together to the input node of the second DAC  11 B. Bottom plates of the first capacitor C T1 , the second capacitor C T2  and the redundant capacitor C redun  may be switchably connected to a positive reference voltage V refp  (e.g., 1 volt) and a negative reference voltage V refn  (e.g., 0 volt). The second DAC  11 B may include a boost capacitor C com_boost  coupled between the input node and the output node of the second DAC  11 B. 
     In one embodiment, the second DAC  11 B may include a first parasitic capacitor C para1  having a top plate coupled to the input node of the second DAC  11 B, and a bottom plate coupled to receive the parasitic voltage V para . The second DAC  11 B may include a second parasitic capacitor C para2  having a top plate coupled to the output node of the second DAC  11 B, and a bottom plate coupled to receive the parasitic voltage V para . 
       FIG. 2A  to  FIG. 2C  show configurations of the single-ended SAR ADC  100  before sampling (or at end of previous conversion phase), in sampling phase and in top-plate level shifting phase, respectively.  FIG. 3  shows exemplary waveforms at the input node and the output node of the (first/second) DAC  11 A/ 11 B. 
     Specifically, in sampling phase as shown in  FIG. 2B , the first sampling switch SW 1  and the second sampling switch SW 2  are turned on (i.e., closed) to respectively sample the input voltage V i  and the ground voltage, and the first boost switch SW b1  and the second boost switch SW b2  are turned off (i.e., open). According to one aspect of the embodiment, the bottom plate of the first capacitor C T1  of the second DAC  11 B may be switchably connected to the negative reference voltage V refn  (e.g., 0 volt) in all phases of each cycle. 
     According to another aspect of the embodiment, in sampling phase, the first capacitor C T1 , the second capacitor C T2  and the redundant capacitor C redun  of the first DAC  11 A and the redundant capacitor C redun  of the second DAC  11 B are swichably coupled to receive the positive reference voltage V refp , while the second capacitor C T2  of the second DAC  11 B are switchably coupled to receive the negative reference voltage V refn . In one embodiment, the positive reference voltage V refp  for an N-bit single-ended SAR ADC  100  may be expressed as
 
 V   refp =(2 N−1   +C   para1   +C   redun ±( C   com_boost   ∥C   para2 ))/2 N−1  
 
     In top-plate level shifting phase as shown in  FIG. 2C , the first sampling switch SW 1  and the second sampling switch SW 2  are turned off (i.e., open), and the first boost switch SW b1  and the second boost switch SW b2  remain turned off (i.e., open). According to one aspect of the embodiment, in top-plate level shifting phase, the first capacitor C T1 , the second capacitor C T2  and the redundant capacitor C redun  of the first DAC  11 A and the redundant capacitor C redun  of the second DAC  11 B remain coupled to receive the positive reference voltage V refp , the first capacitor C T1  of the second DAC  11 B remains coupled to receive the negative reference voltage V refn , but the second capacitor C T2  of the second DAC  11 B is switchably coupled to receive the positive reference voltage V refp . The top-plate level shifting phase is followed by conversion phase and pre-charging phase. 
     According to the embodiment as disclosed above, a comparison benchmark at the input node of the second DAC  11 B may be properly generated according to swing of the positive reference voltage V refp . Specifically, the comparison benchmark is generated according to voltage division among the first capacitor C T1 , the second capacitor C T2  and the redundant capacitor C redun  of the second DAC  11 B. 
     In the differential mode, a differential input voltage (not shown) is sampled by the first DAC  11 A and the second DAC  11 B via the first sampling switch SW 1  and the second sampling switch SW 2  respectively, and the bottom plate of the first capacitor C T1  of the second DAC  11 B is connected to the positive reference voltage V refp  or the negative reference voltage V refn  according to the control of the SAR controller  13 . 
     Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.