Patent Publication Number: US-8994425-B2

Title: Techniques for aligning and reducing skew in serial data signals

Description:
FIELD OF THE DISCLOSURE 
     The present invention relates to electronic circuits, and more particularly, to techniques for aligning and reducing skew in serial data signals. 
     BACKGROUND 
     A field programmable gate array (FPGA) integrated circuit includes input/output (I/O) regions, regions of programmable logic circuits, and programmable interconnect resources that can be used to interconnect the regions of programmable logic circuits with each other and with the I/O regions. By properly programming or configuring the programmable logic circuits and the programmable interconnect resources, a user can configure an FPGA to perform a desired function. The I/O regions also may be programmable. 
     The interconnect resources of an FPGA may include global interconnect resources that carry signals to and among many different parts of the integrated circuit, regional interconnect resources that carry signals within a substantial portion, but less than all, of the integrated circuit, and local interconnect resources that carry signals within groupings of programmable logic circuits. 
     FPGAs have been continually increasing in size and capability. Many FPGAs have a large number of channels in the I/O regions that receive and transmit data signals with external devices. However, as the number of channels on an FPGA has increased, the amount of interconnect resources, including both signal lines and switching or routing resources to create desired signal paths, also has increased. In many current FPGAs, the interconnect resources consume a substantial portion of the die area of the integrated circuit. Thousands of interconnect wires may be used to connect multiple FPGAs to each other and to other integrated circuits on a circuit board. 
     BRIEF SUMMARY 
     According to some embodiments described herein, a circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals. 
     Various objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an example of a data transmission system, according to an embodiment of the present invention. 
         FIG. 2  illustrates an example of two integrated circuits that are connected by an interposer, according to an embodiment of the present invention. 
         FIG. 3  illustrates an example of an align and deskew circuit, according to an embodiment of the present invention. 
         FIG. 4  illustrates an example of an aligner circuit, according to an embodiment of the present invention. 
         FIG. 5  illustrates an example of a control circuit that generates control signals used in the aligner circuit of  FIG. 4 , according to an embodiment of the present invention. 
         FIG. 6  is a timing diagram that illustrates exemplary waveforms for signals associated with the align and deskew circuit of  FIG. 3 , according to an embodiment of the present invention. 
         FIG. 7  illustrates an example of a deskew circuit, according to an embodiment of the present invention. 
         FIG. 8  is a simplified partial block diagram of a field programmable gate array (FPGA) that can include embodiments of the present invention. 
         FIG. 9  shows a block diagram of an exemplary digital system that can embody techniques of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Multiple data signals can be transmitted in serial through conductors on an integrated circuit or between integrated circuits. For example, multiple serial data signals can be transmitted across an integrated circuit die. As another example, data signals can be transmitted in serial from one integrated circuit to another integrated circuit through an interposer. Transmitting the data signals in serial rather than in parallel reduces the number of conductors used to transmit the data signals and reduces routing congestion. However, if the conductors used to transmit the data signals in serial have different lengths, the data signals may be skewed relative to each other when the data signals arrive at their destination. According to some embodiments described herein, data signals that have been transmitted in serial are aligned at a receiving circuit based on a common control signal and de-skewed relative to each other. 
       FIG. 1  illustrates an example of a data transmission system  100 , according to an embodiment of the present invention. Data transmission system  100  includes an input/output (I/O) circuit  101  and a circuit  110 . I/O circuit  101  and circuit  110  are connected by conductors  121 - 124 . In one embodiment, I/O circuit  101 , circuit  110 , and conductors  121 - 124  are in the same integrated circuit die. In this embodiment, I/O circuit  101  and circuit  110  are in two separate regions of the integrated circuit die. In another embodiment, I/O circuit  101  and circuit  110  are in two separate integrated circuit dies and conductors  121 - 124  are external routing conductors. 
     I/O circuit  101  includes a receiver circuit  102 , a transmitter circuit  103 , an align and deskew circuit  104 , and a clock multiplier unit (CMU) circuit  105 . As an example, I/O circuit  101  may be a high speed serial interface (HSSI) circuit in an integrated circuit. As another example, I/O circuit  101  may be a memory interface circuit in a memory integrated circuit. 
     Circuit  110  includes a data circuit  111 , an align and deskew circuit  112 , a clock tree  113 , a deserializer (DESER) circuit  114 , a serializer circuit  115 , a data circuit  116 , and a clock tree  117 . As an example, circuit  110  may be in a field programmable gate array integrated circuit, and data circuits  111  and  116  may include programmable logic circuits. As another example, circuit  110  may be in a memory integrated circuit, and data circuits  111  and  116  may be memory circuits. 
     An N number of input data signals DATAIN are transmitted to inputs of receiver circuit  102  in I/O circuit  101 . N may be any integer number greater than 1. Each of the input data signals DATAIN is transmitted in serial to receiver circuit  102 . The input data signals DATAIN indicate a set of input data. In an embodiment, receiver circuit  102  includes an N number of clock data recovery circuits. Each of the clock data recovery circuits in receiver circuit  102  receives a different one of the serial input data signals DATAIN. Each of the clock data recovery circuits in receiver circuit  102  generates a recovered clock signal based on the serial input data signal received at that clock data recovery circuit using a clock data recovery technique. 
     Receiver circuit  102  provides the input data indicated by signals DATAIN to align and deskew circuit  112  as an N number of data signals DATARX[1:N] through an N number of conductors  121 . Each of the data signals DATARX[1:N] is transmitted in serial to circuit  112  through one of conductors  121 . Receiver circuit  102  provides one of the recovered clock signals to align and deskew circuit  112  as clock signal RCLK through conductor  122 . Align and deskew circuit  112  aligns the input data indicated by data signals DATARX[1:N] based on a common control signal and reduces skew between data signals DATARX[1:N] to generate an N number of serial deskewed data signals DATAW. Deserializer circuit  114  converts the serial deskewed data signals DATAW into parallel data signals DATAY. 
     Data signals DATAY indicate the same input data as data signals DATARX[1:N]. Data signals DATAY are provided to data circuit  111 . In an embodiment, the N number of serial data signals DATARX[1:N] is substantially less than the number of parallel data signals DATAY, and therefore, serial data signals DATARX[1:N] use less conductors for transmission than parallel data signals DATAY, reducing routing congestion. 
     Align and deskew circuit  112  generates a clock signal YCLK based on clock signal RCLK. Clock signal YCLK is provided to data circuit  111  through clock tree  113  as clock signal ZCLK. Data circuit  111  may be any type of circuit that stores or processes data. For example, data circuit  111  may be a memory circuit that stores the data indicated by signals DATAY or processing circuitry that processes the data indicated by signals DATAY. 
     Data circuit  116  provides a set of data signals DATAZ in parallel to serializer circuit  115  in response to a clock signal XCLK. Data circuit  116  may be any type of circuit that stores or processes data. For example, data circuit  116  may be a memory circuit that stores the data indicated by signals DATAZ or processing circuitry that processes the data indicated by signals DATAZ. 
     CMU circuit  105  includes a phase-locked loop circuit that generates clock signals SCLK and ACLK. Clocks signals SCLK and ACLK may have the same frequencies or different frequencies. Clock signal SCLK is provided through conductor  124  to serializer circuit  115 . Serializer circuit  115  generates a clock signal WCLK using a frequency divider circuit that divides the frequency of clock signal SCLK to generate the frequency of WCLK. Clock signal WCLK is provided to data circuit  116  through clock tree  117  as clock signal XCLK. 
     Serializer circuit  115  converts the parallel data signals DATAZ into an N number of serial data signals DATASR[1:N] in response to clock signal SCLK. Data signals DATASR[1:N] are provided in serial to align and deskew circuit  104  through an N number of conductors  123 . In an embodiment, the N number of serial data signals DATASR[1:N] is substantially less than the number of parallel data signals DATAZ, and therefore, data signals DATASR[1:N] use less conductors for transmission than data signals DATAZ. 
     Align and deskew circuit  104  aligns the data indicated by data signals DATASR[1:N] based on a common control signal and reduces skew between data signals DATASR[1:N] to generate an N number of deskewed serial data signals DATATX[1:N]. Data signals DATATX[1:N] indicate the same data as data signals DATASR[1:N]. Data signals DATATX[1:N] are provided in serial through an N number of conductors to transmitter circuit  103 . Transmitter circuit  103  transmits the data indicated by serial data signals DATATX[1:N] outside the integrated circuit as a set of N serial output data signals DATAOUT in response to clock signal ACLK. Transmitter circuit  103  generates a clock signal BCLK based on clock signal ACLK. Clock signal BCLK is provided to align and deskew circuit  104 . 
       FIG. 2  illustrates an example of two integrated circuits that are connected by an interposer, according to an embodiment of the present invention.  FIG. 2  is shown in a cross-sectional view. The system of  FIG. 2  includes two integrated circuit (IC) dies  201  and  202 , an interposer  203 , a circuit board  204 , and conductive bumps  205 - 207 . In an embodiment, I/O circuit  101  shown in  FIG. 1  is in integrated circuit  201 , and circuit  110  shown in  FIG. 1  is in integrated circuit  202 . In other embodiments, I/O circuit  101  and circuit  110  are both in integrated circuit  201  or are both in integrated circuit  202 . 
     Integrated circuit die  201  is connected to interposer  203  through conductive bumps  205 . Integrated circuit die  202  is connected to interposer  203  through conductive bumps  206 . Interposer  203  is connected to circuit board  204  through conductive bumps  207 . 
     Data signals are transmitted in serial between integrated circuit  201  and integrated circuit  202  through conductors  211 - 213  and other conductors in interposer  203 . Each of the conductors  211 ,  212 , and  213  transmits a single serial data signal, such as one of the serial data signals DATAIN or one of the serial data signals DATAOUT. Three conductors  211 - 213  that transmit serial signals between integrated circuits  201  and  202  are shown in  FIG. 2  to simplify the drawing. Interposer  203  may have many more conductors that transmit serial signals between integrated circuits  201  and  202 . 
     Signals are transmitted between circuit board  204  and integrated circuit  201  through conductors in interposer  203 , such as conductor  214 . Signals are transmitted between circuit board  204  and integrated circuit  202  through conductors in interposer  203 , such as conductor  215 . 
       FIG. 3  illustrates an example of an align and deskew circuit  300 , according to an embodiment of the present invention. Align and deskew circuit  300  includes an N number of aligner circuits and a deskew circuit  310 . Five aligner circuits  301 - 305  are shown in  FIG. 3  as an example. Circuit  300  may include any number of aligner circuits. Align and deskew circuit  300  is an example of circuitry in align and deskew circuit  112 . Align and deskew circuit  300  is also an example of circuitry in align and deskew circuit  104 . In an embodiment of  FIG. 1 , each of the align and deskew circuits  104  and  112  includes an align and deskew circuit  300  as shown in  FIG. 3 . 
     A single serial data signal is provided to an input of each of the aligner circuits in circuit  300 . An N number of serial data signals are provided to the N number of aligner circuits in circuit  300 . Each of the aligner circuits in circuit  300  receives a different one of the serial data signals. Serial data signals DATA 1 , DATA 2 , DATA 3 , DATA 4 , and DATA 5  are provided to inputs of aligner circuits  301 ,  302 ,  303 ,  304 , and  305 , respectively, as shown in  FIG. 3 . 
     8 control signals PH 1 , PH 2 , PH 3 , PH 4 , PH 5 , PH 6 , PH 7 , and PH 8  are provided to 8 inputs of each of the aligner circuits in circuit  300 . Each of the aligner circuits in circuit  300  samples one of the serial data signals and then aligns the data indicated by that serial data signal with an edge of the first control signal PH 1  to generate an aligned serial data signal. For example, aligner circuits  301 - 305  sample serial data signals DATA 1 , DATA 2 , DATA 3 , DATA 4 , and DATA 5  and then align the data indicated by serial data signals DATA 1 , DATA 2 , DATA 3 , DATA 4 , and DATA 5  with control signal PH 1  to generate aligned serial data signals DATA 1 C, DATA 2 C, DATA 3 C, DATA 4 C, and DATA 5 C, respectively. The aligner circuits in circuit  300  generate an N number of aligned serial data signals. 
     The aligned serial data signals, including data signals DATA 1 C, DATA 2 C, DATA 3 C, DATA 4 C, and DATA 5 C, generated by the aligner circuits are provided to inputs of deskew circuit  310 . Deskew circuit  310  reduces skew between the N number of aligned serial data signals to generate an N number of deskewed serial data signals. For example, deskew circuit  310  reduces skew between aligned serial data signals DATA 1 C, DATA 2 C, DATA 3 C, DATA 4 C, and DATA 5 C to generate deskewed serial data signals DATA 1 D, DATA 2 D, DATA 3 D, DATA 4 D, and DATA 5 D, respectively. Deskewed data signals DATA 1 D, DATA 2 D, DATA 3 D, DATA 4 D, and DATA 5 D indicate the same data as data signals DATA 1 C, DATA 2 C, DATA 3 C, DATA 4 C, and DATA 5 C, respectively. 
     For align and deskew circuit  104 , the N serial data signals DATA 1 -DATA 5  etc. in  FIG. 3  are the data signals DATASR[1:N] shown in  FIG. 1 , and the N serial data signals DATA 1 D-DATA 5 D etc. in  FIG. 3  are the data signals DATATX[1:N] shown in  FIG. 1 . For align and deskew circuit  112 , the N data signals DATA 1 -DATA 5  etc. in  FIG. 3  are the data signals DATARX[1:N] shown in  FIG. 1 , and the N serial data signals DATA 1 D-DATA 5 D etc. in  FIG. 3  are the data signals DATAW shown in  FIG. 1 . 
       FIG. 4  illustrates an example of an aligner circuit  400 , according to an embodiment of the present invention. Aligner circuit  400  includes D flip-flop circuits  401 - 408 , D flip-flop circuits  411 - 418 , middle bit selector circuit  420 , multiplexer circuit  421 , and D flip-flop circuit  422 . Aligner circuit  400  is an example of each of the N number of aligner circuits in align and deskew circuit  300 . In an embodiment, each of the aligner circuits  301 - 305  etc. in align and deskew circuit  300  includes an aligner circuit  400 . Flip-flop circuits  401 - 408 ,  411 - 418 , and  422  are storage circuits. 
     A first control signal PH 1  is provided to the clock inputs of flip-flop circuits  401  and  411 . A second control signal PH 2  is provided to the clock inputs of flip-flop circuits  402  and  412 . A third control signal PH 3  is provided to the clock inputs of flip-flop circuits  403  and  413 . A fourth control signal PH 4  is provided to the clock inputs of flip-flop circuits  404  and  414 . A fifth control signal PH 5  is provided to the clock inputs of flip-flop circuits  405  and  415 . A sixth control signal PH 6  is provided to the clock inputs of flip-flop circuits  406  and  416 . A seventh control signal PH 7  is provided to the clock inputs of flip-flop circuits  407  and  417 . An eighth control signal PH 8  is provided to the clock inputs of flip-flop circuits  408  and  418 . 
     According to alternative embodiments, aligner circuit  400  includes a different number of flip-flop circuits. For example, instead of two sets of 8 flip-flop circuits, aligner circuit  400  may have two sets of 5, 6, 7, 9, 10, 11, 12, etc. flip-flop circuits that receive a corresponding number of control signals. 
       FIG. 5  illustrates an example of a control circuit  500  that generates the control signals PH 1 -PH 8 , according to an embodiment of the present invention. Control circuit  500  is an example of additional circuitry in align and deskew circuit  112  that generates control signals PH 1 -PH 8 . Control circuit  500  is also an example of additional circuitry in align and deskew circuit  104  that generates control signals PH 1 -PH 8 . In an embodiment of  FIG. 1 , each of the align and deskew circuits  104  and  112  includes a control circuit  500  as shown in  FIG. 5 . 
     Control circuit  500  includes a counter circuit  501  and eight comparator circuits  511 - 518 . A clock signal CLOCK is provided to a clock input of counter circuit  501 , and a reset signal RESET is provided to a reset input of counter circuit  501 . Counter circuit  501  generates 3 count signals CNT in parallel at 3 outputs in response to clock signal CLOCK and reset signal RESET. The CLOCK, RESET, CNT, and PH 1 -PH 8  signals are all digital signals that have rising and falling edges. In align and deskew circuit  112 , the CLOCK signal may be clock signal RCLK shown in  FIG. 1  or derived from clock signal RCLK. In align and deskew circuit  104 , the CLOCK signal may be clock signal BCLK shown in  FIG. 1  or derived from clock signal BCLK. 
     The three count signals CNT are provided to three inputs of each of the comparator circuits  511 - 518 . A set of 3 digital reference signals having constant binary values are provided to three additional inputs of each of the comparator circuits  511 - 518 . Digital reference signals having constant binary values of 001, 010, 011, 100, 101, 110, 111, and 000 are provided to inputs of comparator circuits  511 - 518 , respectively, as shown in  FIG. 5 . As described herein, 0 refers to a logic low state of a digital signal, and 1 refers to a logic high state of a digital signal. 
     Counter circuit  501  is a 3-bit asynchronous binary counter circuit. While the RESET signal is in a logic high state, counter circuit  501  maintains the digital value of each of the three count signals CNT at zero, causing the count signals CNT to have a binary value of 000. When the RESET signal is in a logic low state, counter circuit  501  is enabled to increase the binary value of the count signals CNT. In response to each rising and falling edge in the CLOCK signal that occurs while the RESET signal is in a logic low state, counter circuit  501  increases the binary value of the count signals CNT by 1. 
     When the binary value of the count signals CNT increases from 000 to 001, comparator  511  generates a rising edge in control signal PH 1 , and comparator  518  generates a falling edge in control signal PH 8 . When the binary value of the count signals CNT increases from 001 to 010, comparator  511  generates a falling edge in control signal PH 1 , and comparator  512  generates a rising edge in control signal PH 2 . When the binary value of the count signals CNT increases from 010 to 011, comparator  512  generates a falling edge in control signal PH 2 , and comparator  513  generates a rising edge in control signal PH 3 . When the binary value of the count signals CNT increases from 011 to 100, comparator  513  generates a falling edge in control signal PH 3 , and comparator  514  generates a rising edge in control signal PH 4 . 
     When the binary value of the count signals CNT increases from 100 to 101, comparator  514  generates a falling edge in control signal PH 4 , and comparator  515  generates a rising edge in control signal PH 5 . When the binary value of the count signals CNT increases from 101 to 110, comparator  515  generates a falling edge in control signal PH 5 , and comparator  516  generates a rising edge in control signal PH 6 . When the binary value of the count signals CNT increases from 110 to 111, comparator  516  generates a falling edge in control signal PH 6 , and comparator  517  generates a rising edge in control signal PH 7 . 
     On the next rising or falling edge of the CLOCK signal that occurs after the count signals CNT reach a binary value of 111, counter circuit  501  resets the binary value of the count signals CNT from 111 to 000. When the binary value of the count signals CNT changes from 111 to 000, comparator  517  generates a falling edge in control signal PH 7 , and comparator  518  generates a rising edge in control signal PH 8 . The counter circuit  501  then begins to increase the binary value of the count signals CNT by 1 in response to each subsequent rising and falling edge in the CLOCK signal until the count signals CNT reach a binary value of 111. The cycle repeats with comparator circuits  511 - 518  generating rising edges in control signals PH 1 -PH 8  when the binary value of count signals CNT changes to 001, 010, 011, 100, 101, 110, 111, and 000, respectively. Control signals PH 1 -PH 8  are periodic signals while the RESET signal is in a logic low state. 
     Referring again to  FIG. 4 , a DATA signal is provided to the D input of each of the 8 flip-flop circuits  401 - 408 . Each of the 17 flip-flop circuits  401 - 408 ,  411 - 418 , and  422  shown in  FIG. 4  is a positive edge-triggered flip-flop that stores the logic state of the signal applied to its D input at its Q output only in response to a rising edge in the signal applied to its clock input. Each of the 8 flip-flop circuits  401 ,  402 ,  403 ,  404 ,  405 ,  406 ,  407 , and  408  stores the logic state of the DATA signal at its Q output in the respective signal DA 1 -DA 8  in response to each rising edge in the respective control signal PH 1 -PH 8  that is provided to the clock input of that flip-flop circuit. The 8 signals DA 1 -DA 8  stored at the Q outputs of flip-flop circuits  401 - 408  are provided to inputs of middle bit selector circuit  420 . 
     The 8 signals DA 1 -DA 8  stored at the Q outputs of flip-flop circuits  401 - 408  are also provided to the D inputs of flip-flop circuits  411 - 418 , respectively. Flip-flop circuits  411 ,  412 ,  413 ,  414 ,  415 ,  416 ,  417 , and  418  store the logic states of signals DA 1 , DA 2 , DA 3 , DA 4 , DA 5 , DA 6 , DA 7 , and DA 8  at their Q outputs as signals DB 1 , DB 2 , DB 3 , DB 4 , DB 5 , DB 6 , DB 7 , and DB 8  in response to rising edges in control signals PH 1 , PH 2 , PH 3 , PH 4 , PH 5 , PH 6 , PH 7 , and PH 8 , respectively. The 8 signals DB 1 -DB 8  stored at the Q outputs of flip-flop circuits  411 - 418  are provided to inputs of middle bit selector circuit  420 . The 8 signals DB 1 -DB 8  stored at the Q outputs of flip-flop circuits  411 - 418  are also provided to the 8 multiplexing inputs of multiplexer circuit  421 . 
       FIG. 6  is a timing diagram that illustrates exemplary waveforms for signals associated with the align and deskew circuit  300 , according to an embodiment of the present invention.  FIG. 6  illustrates exemplary waveforms for signals CLOCK, PH 1 -PH 8 , RESET, and DATA. The CLOCK signal may, for example, be generated by a phase-locked loop, a delay-locked loop, or a clock data recovery circuit that generates periodic oscillations in the CLOCK signal, as shown in  FIG. 6 . 
     Initially, a training pattern is provided in each of the N serial data signals DATA 1 -DATA 5  etc. shown in  FIG. 3 . The align and deskew circuit  300  uses the training pattern in each of the N serial data signals DATA 1 -DATA 5  etc. to align the data signals based on a common control signal and to reduce any skew between the data signals. In  FIG. 4 , the DATA signal in aligner circuit  400  corresponds to the serial data signal DATA 1 -DATA 5  etc. provided to the respective aligner circuit  301 - 305  etc. shown in  FIG. 3 . The output signal DATAC of aligner circuit  400  corresponds to the serial data signal DATA 1 C-DATA 5 C etc. generated by the respective aligner circuit  301 - 305  etc. shown in  FIG. 3 . 
       FIG. 6  illustrates an example of a training pattern for the DATA signal. During the exemplary training pattern of  FIG. 6 , the DATA signal is initially in a logic low state. After the falling edge in the RESET signal, a logic high state pulse is generated in the DATA signal for the training pattern, as shown in  FIG. 6 . The logic high state pulse in the DATA signal begins with a rising edge and ends with a falling edge. The logic high state pulse that is generated in the DATA signal for the training pattern lasts for 4 periods of the CLOCK signal. 
     The RESET signal transitions from a logic high state to a logic low state to start counter circuit  501  varying count signals CNT, as described with respect to  FIG. 5 . Control circuit  500  begins to generate repeating logic high pulses in each of the control signals PH 1 -PH 8  after the falling edge in the RESET signal, as shown in  FIG. 6 . 
     During the exemplary training pattern in the DATA signal shown in  FIG. 6 , flip-flop circuits  401 - 408  store the logic states 0, 0, 1, 1, 1, 1, 1, and 1 of the DATA signal in signals DA 1 -DA 8  in response to the first set of rising edges in control signals PH 1 -PH 8 , respectively, shown in  FIG. 6 . In response to the second set of rising edges in control signals PH 1 -PH 8  shown in  FIG. 6 , flip-flop circuits  411 - 418  store the logic states 0, 0, 1, 1, 1, 1, 1, and 1 of signals DA 1 -DA 8  in their output signals DB 1 -DB 8 , respectively, and flip-flop circuits  401 - 408  store the logic states 1, 1, 0, 0, 0, 0, 0, and 0 of the DATA signal in signals DA 1 -DA 8 , respectively. 
     Control signals PH 1 -PH 8  are provided to middle bit selector circuit  420 . Middle bit selector circuit  420  determines the two middle 1 bits among the eight signals having logic high states (i.e., eight 1 bits) that are stored by flip-flop circuits  401 - 408  and  411 - 418  after the second set of rising edges in control signals PH 1 -PH 8  generated during the training pattern. The two middle 1 bits correspond to two signals that are sampled near the middle of the logic high state pulse in the DATA signal during the training pattern. As an example, middle bit selector circuit  420  may be a state machine. 
     Middle bit selector circuit  420  then generates three digital select signals SEL that indicate one of the signals DB 1 -DB 8  having one of the two middle 1 bits. The select signals SEL are provided to select inputs of multiplexer circuit  421 . Multiplexer circuit  421  selects the signal among signals DB 1 -DB 8  that is indicated by the select signals SEL. Multiplexer circuit  421  provides the signal indicated by the select signals SEL (i.e., one of signals DB 1 -DB 8 ) to the D input of flop-flop circuit  422  as signal DSL. Flip-flop circuit  422  stores the logic state of signal DSL at its Q output as signal DATAC in response to each rising edge in control signal PH 1 . 
     In the exemplary training pattern of the DATA signal shown in  FIG. 6  and described above, signals DA 1 -DA 2  and DB 3 -DB 8  have logic high states (i.e., 1) and signals DA 3 -DA 8  and DB 1 -DB 2  have logic low states (i.e., 0) after the second set of rising edges in control signals PH 1 -PH 8  shown in  FIG. 6 . Middle bit selector circuit  420  determines that signals DB 6  and DB 7  store the middle 1 bits among the eight signals DA 1 -DA 2  and DB 3 -DB 8  having logic high states after the second set of rising edges in control signals PH 1 -PH 8 . Middle bit selector circuit  420  then generates logic states for the select signals SEL that cause multiplexer circuit  421  to provide signal DB 6  (or DB 7 ) to the D input of flip-flop circuit  422  as signal DSL. The logic state of signal DSL is stored at the Q output of flip-flop circuit  422  as signal DATAC in response to each rising edge in control signal PH 1 . Thus, aligner circuit  400  aligns a signal that is sampled near the middle of the logic high state pulse in the DATA signal during the training pattern with the phase of the control signal PH 1  to generate output data signal DATAC. 
       FIG. 7  illustrates an example of deskew circuit  310  shown in  FIG. 3 , according to an embodiment of the present invention. The N number of aligned serial data signals generated by the aligner circuits  301 - 305  etc., including data signals DATA 1 C-DATA 5 C, are provided to inputs of deskew circuit  310 , as shown in  FIG. 7 . Deskew circuit  310  reduces or removes skew between the N number of aligned serial data signals to generate an N number of deskewed serial data signals. For example, deskew circuit  310  reduces or removes skew between aligned serial data signals DATA 1 C, DATA 2 C, DATA 3 C, DATA 4 C, and DATA 5 C to generate deskewed serial data signals DATA 1 D, DATA 2 D, DATA 3 D, DATA 4 D, and DATA 5 D, respectively. 
     Deskew circuit  310  in  FIG. 7  includes four banks of D flip-flop circuits, an N number of multiplexer circuits, and an arrival of logic 1s detector circuit  750 . Each of the four banks of D flip-flop circuits has an N number of D flip-flop circuits. The first, second, third, and fourth banks of D flip-flop circuits include D flip-flop circuits  701 - 705 ,  711 - 715 ,  721 - 725 , and  731 - 735 , respectively. Each of the N number of D flip-flop circuits in each of the four banks of D flip-flop circuits in circuit  310  is a positive edge-triggered flip-flop that stores the logic state of the signal applied to its D input at its Q output only in response to a rising edge in the signal applied to its clock input. Each of the D flip-flop circuits in each of the four banks of D flip-flop circuits is a storage circuit. The N multiplexer circuits include multiplexer circuits  741 - 745 . 
     The N number of aligned serial data signals generated by the aligner circuits  301 - 305  etc. of  FIG. 3  are provided to the D inputs of the flip-flop circuits in the first bank. For example, serial data signals DATA 1 C, DATA 2 C, DATA 3 C, DATA 4 C, and DATA 5 C are provided to the D inputs of flip-flop circuits  701 - 705 , respectively, in the first bank. The first control signal PH 1  is provided to the clock input of each of the flip-flop circuits in the four banks. For example, control signal PH 1  is provided to the clock inputs of flip-flop circuits  701 - 705 ,  711 - 715 ,  721 - 725 , and  731 - 735  shown in  FIG. 7 . 
     In response to each rising edge in control signal PH 1 , the flip-flop circuits in the first bank store the logic states of the N number of aligned serial data signals generated by the aligner circuits of  FIG. 3  at their Q outputs. For example, flip-flop circuits  701 - 705  in the first bank store the logic states of serial data signals DATA 1 C, DATA 2 C, DATA 3 C, DATA 4 C, and DATA 5 C at their Q outputs as stored signals DE 1 , DE 2 , DE 3 , DE 4 , and DE 5 , respectively, in response to each rising edge in control signal PH 1 . 
     The signals stored at the Q outputs of the flip-flop circuits in the first bank are provided to the D inputs of the flip-flop circuits in the second bank. In response to each rising edge in control signal PH 1 , the flip-flop circuits in the second bank store at their Q outputs the logic states of the signals stored by the flip-flop circuits in the first bank. For example, flip-flop circuits  711 - 715  in the second bank store the logic states of signals DE 1 , DE 2 , DE 3 , DE 4 , and DE 5  at their Q outputs as stored signals DF 1 , DF 2 , DF 3 , DF 4 , and DF 5 , respectively, in response to each rising edge in control signal PH 1 . 
     The signals stored at the Q outputs of the flip-flop circuits in the second bank are provided to the D inputs of the flip-flop circuits in the third bank. In response to each rising edge in control signal PH 1 , the flip-flop circuits in the third bank store at their Q outputs the logic states of the signals stored by the flip-flop circuits in the second bank. For example, flip-flop circuits  721 - 725  in the third bank store the logic states of signals DF 1 , DF 2 , DF 3 , DF 4 , and DF 5  at their Q outputs as stored signals DG 1 , DG 2 , DG 3 , DG 4 , and DG 5 , respectively, in response to each rising edge in control signal PH 1 . 
     The signals stored at the Q outputs of the flip-flop circuits in the third bank are provided to the D inputs of the flip-flop circuits in the fourth bank. In response to each rising edge in control signal PH 1 , the flip-flop circuits in the fourth bank store at their Q outputs the logic states of the signals stored by the flip-flop circuits in the third bank. For example, flip-flop circuits  731 - 735  in the fourth bank store the logic states of signals DG 1 , DG 2 , DG 3 , DG 4 , and DG 5  at their Q outputs as stored signals DH 1 , DH 2 , DH 3 , DH 4 , and DH 5 , respectively, in response to each rising edge in control signal PH 1 . 
     Deskew circuit  310  has an N number of serial shift registers. Flip-flop circuits  701 ,  711 ,  721 , and  731  are coupled as a first serial shift register. Flip-flop circuits  702 ,  712 ,  722 , and  732  are coupled as a second serial shift register. Flip-flop circuits  703 ,  713 ,  723 , and  733  are coupled as a third serial shift register. Flip-flop circuits  704 ,  714 ,  724 , and  734  are coupled as a fourth serial shift register. Flip-flop circuits  705 ,  715 ,  725 , and  735  are coupled as a fifth serial shift register. 
     The signals stored by each of the N number of serial shift registers in deskew circuit  310  are provided to the multiplexing inputs of one of the multiplexer circuits. The signals DE 1 , DF 1 , DG 1 , and DH 1  stored by the first serial shift register are provided to the multiplexing inputs of multiplexer circuit  741 . The signals DE 2 , DF 2 , DG 2 , and DH 2  stored by the second serial shift register are provided to the multiplexing inputs of multiplexer circuit  742 . The signals DE 3 , DF 3 , DG 3 , and DH 3  stored by the third serial shift register are provided to the multiplexing inputs of multiplexer circuit  743 . The signals DE 4 , DF 4 , DG 4 , and DH 4  stored by the fourth serial shift register are provided to the multiplexing inputs of multiplexer circuit  744 . The signals DE 5 , DF 5 , DG 5 , and DH 5  stored by the fifth serial shift register are provided to the multiplexing inputs of multiplexer circuit  745 . 
     Skew between signals refers to the difference in arrival time between signals that are transmitted at the same time. The serial data signals DATARX[1:N] shown in  FIG. 1  may develop skew when transmitted through conductors  121  to align and deskew circuit  112 . The serial data signals DATASR[1:N] shown in  FIG. 1  may develop skew when transmitted through conductors  123  to align and deskew circuit  104 . 
     The N number of aligned serial data signals generated by the aligner circuits of  FIG. 3  and provided to deskew circuit  310  may have skew that is greater than zero. One or more of the N number of aligned serial data signals generated by the aligner circuits of  FIG. 3  and provided to deskew circuit  310  may be delayed relative to the other aligned serial data signals generated by the aligner circuits of  FIG. 3 . For example, if one of signals DATA 1 C-DATA 5 C is delayed relative to the other signals DATA 1 C-DATA 5 C, then the middle 1 bit selected by the aligner circuit  400  for the delayed signal may be stored in an earlier bank of flip-flops in circuit  310  relative to the middle 1 bits selected by the aligner circuits  400  for the other signals DATA 1 C-DATA 5 C. 
     Each of the signals stored by each of the flip-flop circuits in each of the four banks in circuit  310  is provided to the arrival of logic 1s detector circuit  750 . For example, signals DE 1 -DE 5 , DF 1 -DF 5 , DG 1 -DG 5 , and DH 1 -DH 5  are provided to inputs of arrival of logic 1s detector circuit  750 . Arrival of logic 1s detector circuit  750  determines the logic state of each of the signals stored by each of the flip-flop circuits in each of the four banks in deskew circuit  310 . Arrival of logic 1s detector circuit  750  determines when all of the N number of serial shift registers in deskew circuit  310  have stored a signal having a logic high state (i.e., a 1 bit). 
     Arrival of logic 1s detector circuit  750  then generates N sets of selects signals, including select signals S 1 -S 5 , based on which of the signals stored by the flip-flop circuits are in logic high states in response to the training patterns in the N serial data signals DATA 1 -DATA 5  etc. The select signals are provided to select inputs of the multiplexer circuits. For example, select signals S 1 , S 2 , S 3 , S 4 , and S 5  are provided to the select inputs of multiplexer circuits  741 - 745 , respectively. Arrival of logic 1s detector circuit  750  generates logic states for the select signals that cause each of the multiplexer circuits in deskew circuit  310  to select the signal stored by the corresponding shift register having a logic high state as the deskewed output serial data signal. As a result, deskew circuit  310  reduces or removes any skew between the serial data signals DATA 1 C, DATA 2 C, DATA 3 C, DATA 4 C, DATA 5 C etc. to generate deskewed serial data signals DATA 1 D, DATA 2 D, DATA 3 D, DATA 4 D, DATA 5 D etc., respectively. 
     As a specific example, if the DATA 5 C signal is delayed by one period of control signal PH 1  relative to the DATA 1 C-DATA 4 C signals, flip-flop circuit  705  stores a logic high state in signal DE 5  indicating the selected middle 1 bit of signal DATA 5 C, while flip-flop circuits  711 - 714  store logic high states in signals DF 1 -DF 4  indicating the selected middle 1 bits of signals DATA 1 C-DATA 4 C, respectively. The selected middle 1 bits of signals DATA 1 C-DATA 5 C were generated in response to the training patterns in the serial data signals DATA 1 -DATA 5 , respectively, as described above. In this example, arrival of logic is detector circuit  750  generates logic states for the select signals S 1 -S 4  that cause multiplexer circuits  741 - 744  to provide signals DF 1 -DF 4  to their outputs as serial data signals DATA 1 D-DATA 4 D, respectively. Also, in this example, arrival of logic is detector circuit  750  generates logic states for the select signals S 5  that cause multiplexer circuit  745  to provide signal DE 5  to its output as serial data signal DATA 5 D. 
     As another specific example, if the DATA 1 C signal is delayed by 3 period of control signal PH 1  relative to the DATA 2 C-DATA 5 C signals, flip-flop circuit  701  stores a logic high state in signal DE 1  indicating the selected middle 1 bit of signal DATA 1 C, while flip-flop circuits  732 - 735  store logic high states in signals DH 2 -DH 5  indicating the selected middle 1 bits of signals DATA 2 C-DATA 5 C, respectively. In this example, arrival of logic is detector circuit  750  generates logic states for the select signals S 2 -S 5  that cause multiplexer circuits  742 - 745  to provide signals DH 2 -DH 5  to their outputs as serial data signals DATA 2 D-DATA 5 D, respectively. Also, in this example, arrival of logic 1s detector circuit  750  generates logic states for the select signals S 1  that cause multiplexer circuit  741  to provide signal DE 1  to its output as serial data signal DATA 1 D. 
     Thus, deskew circuit  310  reduces or removes the skew between the N number of aligned serial data signals (i.e., DATA 1 C-DATA 5 C etc.) to generate deskewed serial output data signals (i.e., DATA 1 D-DATA 5 D etc.) that are closer to being aligned with each other in time. Deskew circuit  310  reduces or removes the skew from the serial data signals during the transmission of the training patterns in the serial data signals. 
     After the training patterns are complete, and deskew circuit  310  has reduced or removed any skew from the serial data signals, data is transmitted through conductors  121  and  123  in the serial data signals DATARX[1:N] and DATASR[1:N], respectively. After deskew circuit  310  has generated logic states for the select signals S 1 -S 5  etc. that reduce or remove skew from the serial data signals, deskew circuit  310  maintains the logic states of the select signals S 1 -S 5  etc. constant during the transmission of data in the serial data signals DATARX[1:N] and DATASR[1:N]. Thus, deskew circuit  310  continues to reduce or remove the same amount of skew between the serial data signals during the transmission of data. Also, each of the aligner circuits  400  maintains the logic states of its select signals SEL constant during the transmission of data in the serial data signals DATARX[1:N] and DATASR[1:N]. Thus, the aligner circuits  301 - 305  etc. continue to align the serial data signals to the control signal PH 1  during the transmission of data in the serial data signals DATARX[1:N] and DATASR[1:N]. 
     According to alternative embodiments, deskew circuit  310  may have a different number of flip-flop banks. For example, deskew circuit  310  may have 2, 3, 5, 6, 7, 8, etc. banks of flip-flops instead of the 4 banks of flip-flops shown in  FIG. 7 . 
       FIG. 8  is a simplified partial block diagram of a field programmable gate array (FPGA)  800  that can include embodiments of the present invention. FPGA  800  is merely one example of an integrated circuit that can include features of the present invention. It should be understood that embodiments of the present invention can be used in numerous types of integrated circuits such as field programmable gate arrays (FPGAs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), programmable logic arrays (PLAs), application specific integrated circuits (ASICs), memory integrated circuits, central processing units, microprocessors, analog integrated circuits, etc. 
     FPGA  800  includes a two-dimensional array of programmable logic array blocks (or LABs)  802  that are interconnected by a network of column and row interconnect conductors of varying length and speed. LABs  802  include multiple (e.g., 10) logic elements (or LEs). 
     A logic element (LE) is a programmable logic circuit block that provides for efficient implementation of user defined logic functions. An FPGA has numerous logic elements that can be configured to implement various combinatorial and sequential functions. The logic elements have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic elements in almost any desired configuration. 
     FPGA  800  also includes a distributed memory structure including random access memory (RAM) blocks of varying sizes provided throughout the array. The RAM blocks include, for example, blocks  804 , blocks  806 , and block  808 . These memory blocks can also include shift registers and first-in-first-out (FIFO) buffers. 
     FPGA  800  further includes digital signal processing (DSP) blocks  810  that can implement, for example, multipliers with add or subtract features. Input/output elements (IOEs)  812  support numerous single-ended and differential input/output standards. IOEs  812  include input and output buffers that are coupled to pins of the integrated circuit. The pins are external terminals of the FPGA die that can be used to route, for example, input data signals, output data signals, and supply voltages between the FPGA and one or more external devices. One or more of the IOEs  812  may include an I/O circuit  101 . FPGA  800  is described herein for illustrative purposes. Embodiments of the present invention can be implemented in many different types of integrated circuits. 
     Embodiments of the present invention can also be implemented in a system that has an FPGA as one of several components.  FIG. 9  shows a block diagram of an exemplary digital system  900  that can embody techniques of the present invention. System  900  can be a programmed digital computer system, digital signal processing system, specialized digital switching network, or other processing system. Moreover, such systems can be designed for a wide variety of applications such as telecommunications systems, automotive systems, control systems, consumer electronics, personal computers, Internet communications and networking, and others. Further, system  900  can be provided on a single board, on multiple boards, or within multiple enclosures. 
     System  900  includes a processing unit  902 , a memory unit  904 , and an input/output (I/O) unit  906  interconnected together by one or more buses. According to this exemplary embodiment, an FPGA  908  is embedded in processing unit  902 . FPGA  908  can serve many different purposes within the system of  FIG. 9 . FPGA  908  can, for example, be a logical building block of processing unit  902 , supporting its internal and external operations. FPGA  908  is programmed to implement the logical functions necessary to carry on its particular role in system operation. FPGA  908  can be specially coupled to memory  904  through connection  910  and to I/O unit  906  through connection  912 . 
     Processing unit  902  can direct data to an appropriate system component for processing or storage, execute a program stored in memory  904 , receive and transmit data via I/O unit  906 , or other similar functions. Processing unit  902  can be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, field programmable gate array programmed for use as a controller, network controller, or any type of processor or controller. Furthermore, in many embodiments, there is often no need for a CPU. 
     For example, instead of a CPU, one or more FPGAs  908  can control the logical operations of the system. As another example, FPGA  908  acts as a reconfigurable processor that can be reprogrammed as needed to handle a particular computing task. Alternatively, FPGA  908  can itself include an embedded microprocessor. Memory unit  904  can be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, flash memory, tape, or any other storage means, or any combination of these storage means. 
     The foregoing description of the exemplary embodiments of the present invention has been presented for the purposes of illustration and description. The foregoing description is not intended to be exhaustive or to limit the present invention to the examples disclosed herein. In some instances, features of the present invention can be employed without a corresponding use of other features as set forth. Many modifications, substitutions, and variations are possible in light of the above teachings, without departing from the scope of the present invention.