Patent Publication Number: US-10790860-B2

Title: Dynamic detection for flash memory

Description:
FIELD 
     Embodiments described herein relate generally to methods and devices for decoding data stored in non-volatile memory and particularly to ways of determining a log likelihood ratio for soft decoding of such data. 
     BACKGROUND 
     Memory cells in NAND flash memory cells consist of field effect transistors that comprise a floating gate interposed between the gate and the channel. NAND flash memory cells are organised into multiple blocks. Memory cells within each block are arranged horizontally along word-lines (for example around 32-64 word lines per block) that connect the gates of horizontally adjacent FETs, and vertically along (often thousands of) bit-lines, connecting drains and sources of vertically adjacent FETs. The control gates of all the cells along a word-line are connected to the address bus while the drains of the cells along a bit-line are connected the data bus. The unit for read/write operations is the word-line, whereas erasure is applied block-wise. Data may be programmed in logical units of a fixed size. Such logical units are sometimes referred to as pages. One or a plurality of pages of data may be stored along a single word-line. 
     To determine the storage state of a memory cell a bias voltage is applied to the wordline connected to the memory cell and a separate bias voltage is applied across the memory cell&#39;s channel. The gate voltage applied to all other memory cells that are connected to the memory cells that are to be read is such that the other memory cells are fully conducting so that the bias voltage applied along the bit-line is applied, to the large largest extent possible, across the channel of the memory cell to be read. 
     The conductivity of the channel of the memory cell to be read is supposed to be influenced solely by the amount of charge stored on the memory cell&#39;s floating gate and by the bias voltage applied to the gate of the memory cell. The source-drain current that can be sensed as flowing through the channel of/along the bit line connected to the memory cell allows concluding whether the amount of charge stored by the memory cell is above or below an amount required for rendering the channel of the memory cell conductive for a given gate bias voltage. 
     The stored charges in the floating gate of a memory cell charges are progressively injected into the floating gate using incremental step pulse program (ISPP). The amount of charge stored on the floating gate is monitored (for example using the above discussed sensing technique) to keep track of programming progress. Once it is determined that a charge that is sufficient to render the memory cell conductive for a given threshold voltage has been stored in a floating gate of the memory cell programming is completed. 
     It is worth noting that programming is a one-way process in a sense that the amount of charge stored on the floating gate cannot selectively be reduced. Instead, once the amount of charge stored in a memory cell exceeds a desired amount all of the charges on the memory cell need to be removed from the floating gate and programming re-started. Such erasure takes place simultaneously for all memory cells in a block of flash memory. 
     NAND flash memory cells are subject to various types of impairments that affect its performance, such as inaccurate programming, retention noise, random telegraph noise and more importantly inter-cell interference (ICI). It will be appreciated that charges stored on the floating gate generate electric fields that can influence the conductivity of the channel of an adjacent memory cell, thereby interfering with and potentially falsifying perceived memory cell storage state, as illustrated in  FIG. 2 . As flash memory architectures continue to be miniaturised the effect electric fields have on adjacent cells becomes more pronounced, thereby increasing ICI. 
     One way of mitigating the increasing ICI effect is to employ soft-decision error correction codes. Towards this purpose, a flash memory controller may start by comparing the threshold voltage against the hard decision boundaries, and upon failure of hard-decision decoding the controller will resort to generating soft information (e.g., LLRs) to be fed to the iterative decoder. However, as the channel model is not precisely known, it is desirable to have a simple and dynamic LLR estimation algorithm instead of relying on precomputed lookup table that may undermine the performance of the soft detection method. 
    
    
     
       In the following, embodiments will be described with reference to the drawings in which: 
         FIG. 1  shows a system that comprises a computing device and a non-volatile Flash storage memory; 
         FIG. 2  shows an architecture of memory cells within a flash array; 
         FIG. 3  illustrates a number of memory cells arranged along a word-line; 
         FIG. 4 a    shows storage state distributions in an MLC hard and soft decision boundaries and associated quantisation bins for reading the MSB; 
         FIG. 4 b    shows storage state distributions in an MLC hard and soft decision boundaries and associated quantisation bins for reading the LSB; 
         FIG. 5  illustrates possible errors in reading a SLC or the MSB of a MLC; 
         FIG. 6  shows additional quantisation bin being provided for higher precision soft decoding for the MSB of a MLC; 
         FIG. 7  shows a method according to an embodiment, and 
         FIG. 8  shows illustrates the results of simulations of the performance of an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     According to an embodiment there is provided a method of decoding data stored in non-volatile memory, wherein each memory cell stores data by adopting one of a plurality of storage states. The method comprises using a threshold for determining a physical property of said memory cells to distinguish between at least two storage states, reading a data codeword from a plurality of the memory cells using said threshold and determining a bit error rate for the data codeword read using the threshold, repeatedly modifying said threshold and re-reading said data codeword using said modified threshold and determining a modified bit error rate for the data codeword read using the modified threshold, selecting the one of the modified thresholds for which the mutual information content between the stored data input and the read data is maximised based on the bit error rate for the data codeword read using the threshold and the bit error rate for the data codeword read using the modified threshold, determining a log likelihood ratio of a quantisation interval bounded by the said threshold and the selected threshold, generating soft decoded data by performing soft decoding of the data using said log likelihood ratio and outputting said soft decoding data. 
     Each of the modified thresholds may bound a quantisation interval. In an embodiment the method further comprises determining a hard bit estimate within the quantisation interval based on the bit error rate for the data codeword read using the threshold and the bit error rate for the data codeword read using the modified threshold. 
     The method may further comprise selecting a second threshold between the said selected threshold and the said threshold, repeatedly modifying said second threshold and re-reading said data codeword using said modified second threshold and determining a modified bit error rate for the data codeword read using the modified second threshold and selecting the one of the modified second thresholds for which the mutual information content between the stored data input and the read data is maximised based on the bit error rate for the data codeword read using the threshold and the bit error rate for the data codeword read using the modified threshold. 
     The selected modified second threshold and the said threshold may define a second quantisation interval. The method may further comprise determining a second hard bit estimate for the second quantisation interval and determining a hard bit estimate for a quantisation interval bounded by the selected modified threshold and the selected second modified threshold based on second hard bit estimate and the hard bit estimate. 
     The method may further comprise initially determining said threshold so as to minimise the determined bit error rate. 
     Said threshold can be an only threshold required to distinguish between the storage states the memory cell is capable of storing to read a stored bit or one of a plurality of thresholds required to distinguish between the storage states the memory cell is capable of storing to read a stored bit. 
     The method may further comprise optimising a threshold used for soft decoding for more than one or all of the plurality of thresholds. 
     According to another embodiment there is provided a non-volatile memory comprising program instructions for execution by a processor, the program instructions, when executed by the processor causing the processor to perform any of the aforementioned methods. 
     According to another embodiment there is provided a storage device comprising non-volatile memory and a memory controller for controlling the memory. The memory is configured to store data by adopting one of a plurality of storage states. The controller is configured to use a threshold for determining a physical property of memory cells in said memory to distinguish between at least two storage states, read a data codeword from a plurality of memory cells using said threshold and determine a bit error rate for the data codeword read using the threshold, repeatedly modify said threshold and re-reading said data codeword using said modified threshold and determine a modified bit error rate for the data codeword read using the modified threshold, select the one of the modified thresholds for which the mutual information content between the stored data input and the read data is maximised based on the bit error rate for the data codeword read using the threshold and the bit error rate for the data codeword read using the modified threshold, determine a log likelihood ratio of a quantisation interval bounded by the said threshold and the selected threshold, generate soft decoded data by performing soft decoding of the data using said log likelihood ratio and output said soft decoding data. 
     Error correction codes to which soft decoding can be applied include a LDPC (low-density parity check) code, a BCH code, a turbo code, an RS (Reed-Solomon code), a convolution code, an RSC (Recursive Systematic Code), or coded modulation such as TCM (Trellis-Coded Modulation), BCM (Block Coded Modulation), and so on. Soft deciding algorithms that can be used include, amongst others, mini-sum algorithms and Viterbi decoding. For soft decoders to work in the best possible way they require knowledge of the reliability of (e.g., log-likelihood ratios (LLRs)) of the read information to be fed to the iterative decoder. The incorporation of error correction codes to which soft decoding can be applied to replace legacy hard-decision ones can boost the reliability for flash memory beyond its current limits. Memory channels vary significantly depending on several factors (e.g., ambient temperature, program-erase cycles, retention time, among others) and the estimated soft metrics (i.e., the log-likelihood ratios) need to be updated accordingly to avoid performance degradation. 
     Firstly, the controller adapts the hard decision boundaries through minimizing the estimated BER. Upon failure of hard detection, the controller directly estimates the number of errors in each soft quantization bin and the soft values are fed to the decoder. The LLR values are estimated for the soft quantization bins in embodiments. However, if a finer soft quantization is needed finer reading intervals can be used and the method of embodiments be applied to such finer intervals. 
       FIG. 1  shows a system that comprises a computing device  100  and non-volatile Flash storage memory  110 . The computing device may be a mobile computing device, such as a mobile phone, tablet computer, laptop, camera or any other type of mobile computing device. Alternatively the computing device  100  may be stationary, such as a desktop computer or indeed part of a stationary server or part of a storage bank, such as part of a RAID solution. 
     The non-volatile Flash storage memory  110  may take any form of non-volatile storage device comprising Flash memory. The non-volatile Flash storage memory  110  may, for example, be a “thumb drive”, a solid-state drive (SSD), a memory card. 
     The computing device  100  and the non-volatile Flash storage memory  110  are in communicative connection with each other in a manner that allows the computing device  100  to transmit data and commands indicating the processing the data is to be subjected to by the non-volatile Flash storage memory  110  to the non-volatile Flash storage memory  110  and that allows the non-volatile Flash storage memory  110  return data retrieved from memory to the computing device  100 . The computing device  100  may also provide power to the non-volatile Flash storage memory  110 . A number of interfaces that allow communication between a computing device  100  and a non-volatile Flash storage memory  110  are known. The exact nature of the interface is not pertinent to the embodiments. Exemplary interfaces include the USB interface, SD, microSD, xD, CompactFlash, MMC, to name but a few. 
     The non-volatile Flash storage memory  110  comprises a memory controller  120  and non-volatile flash memory  130 . The memory controller  120  interfaces with the computing device  100  as well as with the flash memory  130 . The memory controller  120  provides power to the flash memory  130  and is moreover connected to the flash memory  130  wire command, control, address and data lines. The memory controller  120  may control all of the operations flash memory  130 . 
     As shown in  FIG. 2 , memory cells in NAND flash memory consist of field effect transistors that comprise a floating gate interposed between the FET&#39;s gate and channel. NAND flash memory cells are organised into multiple blocks. Memory cells within each block are arranged horizontally along word-lines (for example around 32-64 word lines per block; in  FIG. 2  three word lines, WL k+1 , WL k  and WL k−1  are shown) that connect the gates of horizontally adjacent FETs, and vertically along (often thousands of) bit-lines (BL 1  to BL n  in  FIG. 2 ), connecting drains and sources of vertically adjacent FETs. The control gates of all the cells along a word-line are connected to the address bus while the drains of the cells along a bit-line are connected to the data bus. The unit for read/write operations is the word-line, whereas erasure is applied block-wise. A block comprises a number of word lines. 
       FIG. 3  illustrates a number of memory cells  200  arranged along a word-line (WL). Although only a few memory cells  200  are shown in  FIG. 3 , several thousand memory cells may be arranged along each word-line (WL). Several word-lines (WL) tend to be arranged so that their memory cells are connected (in  FIG. 3  in the vertical direction) along bit lines BLs. In an embodiment all memory cells along a word line WL are programmed simultaneously. The data unit used for programming is illustrated in  FIG. 3  by logical page  210 . Each logical page may comprise smaller sub-units  220 . The sub-units are referred to as codewords in embodiments described herein. More generally, however, a codeword is a string of data that has its own error correction codes associated with it. A sub-unit may, for example be 512 kByte in size to mimic the size of hard drive sectors and so that the flash memory can be addressed in the same manner as hard drives. The sub-units are referred to as pages in the following. Although  FIG. 3  shows each page to be programmed into a group of consecutive memory cells  200  it is possible for data in pages to be programmed in every other cell or with more than one cell interleaved between the cells that contain the data of the page. The cells that are not programmed to comprise data of a particular page are programmed with data of one or more other pages, often in the same programming operation as the operation in which the page data is programmed. 
     For memory cells  200  that are to store only a single bit of data it is sufficient to adopt only one of two storage states. To operate memory cells to store more than one bit of data (memory cells for storing two bits of data are referred to as MLCs hereinafter while memory cells for storing three (resp. four) bits of data are referred to as TLCs (resp. QLCs) hereinafter) the program and read circuitry connected to the word and/or bit lines respectively are configured to distinguish between more than two storage states. To store two bits of data in a memory cell, for example, it is necessary to distinguish between four storage states (as shown in  FIG. 4 ). 
     Data bits stored in each memory cell may be stored so that they are independent from each other. For example, data stored in a multi-bit memory cell may originate from different data pages, wherein a first page is programmed to a group of memory cells before a second or further pages are programmed to the group of memory cells. This is illustrated in  FIG. 3 . In a first programming pass a first set of pages  220  are programmed to the memory cells along word line WL. In the example shown in  FIG. 3  the information stored in the left-most memory cell is a binary ‘0’. In a second programming pass a second set of pages  240  are programmed to the memory cells along word line WL. In the example shown in  FIG. 3  the information stored in the left-most memory cell is a binary ‘10’. In a third programming pass a second set of pages  260  are programmed to the memory cells along word line WL. In the example shown in  FIG. 3  the information stored in the left-most memory cell is a binary ‘110’. 
     To determine the storage state of a memory cell a bias voltage is applied to the word line connected to the memory cell in question and a separate bias voltage is applied across the memory cell&#39;s channel. The gate voltage applied to all other memory cells that are connected to the memory cells that is to be read is such that the other memory cells are fully conducting so that the bias voltage applied along the bit-line is applied, to the largest extent possible, across the channel of the memory cell to be read. 
     In the following it is assumed that the different memory logical pages (i.e., MSB page and LSB page for MLC flash memory) are encoded independently. 
     In the embodiment the memory controller starts with initial estimates of the hard boundaries (the boundaries used when writing) and checks the validity of the hard estimate of the stored codeword by evaluating its syndrome. If the syndrome has weight zero the codeword estimate is a legitimate codeword and decoding is successful. Otherwise, the estimated BER {acute over (p)} e  in the i-th page is calculated according to: 
     
       
         
           
             
               
                 
                   
                     
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     where w(s) denotes the weight of the syndrome s associated with the i-th page, d c  denotes the check nodes degree (assuming a regular LDPC code is used) and N c  denotes the number of parity check constraints. 
     The controller repeats the above procedure for varying hard boundaries until the number of estimated erroneous bits is minimized. Let the estimated hard boundaries that minimize (1) be denoted by t 1 *, . . . , t M-1 *, where M is the number of storage states supported by the cell. Upon failure of the hard detection (i.e., if the syndrome has a non-zero weight), the controller resorts to the more powerful soft detection. 
     It is well known that the optimal soft boundaries are non-uniformly distributed where more boundaries are required in the overlap region between adjacent threshold voltage levels. In an embodiment, each hard boundary is first surrounded with two soft boundaries as depicted in  FIG. 4 a    (for the MSB) and  FIG. 4 b    (for the LSB). The soft-decision boundaries are sought to be optimised through maximizing the mutual information between the binary input X and the quantized read voltage Y. 
     As can be seen from  FIGS. 4 a  and 4 b   , the overlap between the storage distributions in a 2-bit memory cell can lead to situations in which charges injected in the floating gate of a cell in an attempt to program it to a particular storage state, say to the “00” state to the right of the t 2 * hard read boundary, cause the cell to conduct at a threshold voltage that is somewhat below the voltage t 2 *, i.e. for the example in which the cell was programmed to the “00” storage state the threshold voltage may be in the hatched area of the “00” storage state distribution that falls to the left of the t 2 * threshold voltage. If this happens the storage state of the memory cell is incorrectly determined, in the example as storage state “10”. 
       FIG. 5  shows the possible transitions for the MSB of a 2-bit memory cell between the programmed bit and the quantisation intervals/bins    1  to    4  shown in  FIG. 4 a   . As will be appreciated, if a memory cell that is programmed to represent a logical “1” is detected to have a threshold voltage that falls within bin    3  or bin    4  then the detected programming state is incorrect. Equally if a memory cell that is programmed to represent a logical “0” is detected to have a threshold voltage that falls within bin    1  or bin    2  then the detected programming state is incorrect. The total number of errors within a codeword per bin and originating from the binary input X but being programmed to incorrect storage bins are indicated as ϵ 1  to ϵ 4  in  FIG. 5 . Arrows in  FIG. 5  relating to correctly programmed storage states are not labelled. 
     The MSB page of MLC flash memory is modelled with three reads as a discrete memoryless channel (DMC) with binary input and quaternary output representing the quantized voltage reads as depicted in  FIG. 5 . The mutual information between the input and the quantized read voltage is expressed as 
     
       
         
           
             
               
                 
                   
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                               ( 
                               
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     where h b (.) is the binary entropy function. In (a) we assumed that ‘0’ and ‘1’ are equally likely. In order to locate the left soft boundary t l * shown in  FIG. 4 a   , the controller compares the cells&#39; threshold voltage against multiple references {t 2 *−iδ: i=1, . . . , L} then evaluates the resulting syndromes and re-estimates the raw BER according to equation (1)(1) and obtains: 
     
       
         
           
             
               
                 
                   
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     where n j  denotes the number of cells that falls into    j , {circumflex over (p)} e  denotes the estimated BER for the current reference voltage, p e * denotes the estimated BER for reference voltage t 2 * and N  denotes the codeword length. Recalling that the entropy H(X) is a concave functional of p(x), the mutual information in equation (2) can be lower bounded as: 
     
       
         
           
             
               
                 
                   
                     
                       
                         
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     where p e *= (Y∈   2 )ϵ 2 + (Y∉   2 ) e 2   . The controller knows ϵ 2  from equation (3) above as well as the number of cells in interval    2  and the overall error probability p e *. The memory controller can consequently calculate the right hand side of inequality (4) for a given soft boundary. By repeatedly reading the memory cells using different soft boundaries and using the results of these reads to calculate the right hand side of inequality (4) allows finding the soft boundary for which the right hand side of inequality (4) is maximised. 
     Similarly, by varying the reference voltage over {t 2 *+iδ:i=1, . . . , L} the controller obtains: 
     
       
         
           
             
               
                 
                   
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     t r * is then found in the manner discussed above with reference to equation (4). 
     The LLR value associated with the j-th bin of the soft quantisation bins {   j :j=1, . . . , n} is defined as: 
     
       
         
           
             
               
                 
                   
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     where V th  is the threshold voltage. Equivalently, the above can be written as: 
     
       
         
           
             
               
                 
                   
                     L 
                     j 
                   
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                         ( 
                         
                           - 
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                           ^ 
                         
                         j 
                       
                     
                     ⁢ 
                     
                       log 
                       ⁡ 
                       
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                   7 
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     where {circumflex over (b)} j  (resp. ϵ j ) denotes the hard bit estimate (resp. the bit-error rate) for the j-th soft bin. 
     The bits falling into the outermost regions (i.e.,    1  and    4 ) are the most reliable and hence their LLR magnitude is set to a fixed high value. 
     When considering the LSB page, two hard-decision boundaries (t 1 * and t 3 * shown in  4   b ) need to be estimated compared to only one hard-decision boundary to estimate (t 2 * shown in  4   a ) for the MSB case. Threshold voltages for these two hard decision boundaries are determined so as to minimise the number of errors in the LSB codeword. One approach is to start by estimating t 1 * by sensing the cells with multiple reference voltages (typically close to the writing threshold) while fixing all other threshold voltages that influence the error rate of the bit that is to be read, in the case in which t 1 * is read in the 2-bit example of  FIG. 4 b    this is {circumflex over (t)} 3 . For every voltage reference, the raw BER estimate can be obtained according to Equation (1), and the voltage reference resulting in the minimum estimated raw BER will be denoted t 1 *. The next step consists to repeating the same steps but while varying {circumflex over (t)} 3  and fixing t 1 *. At the end, t 1 * and t 3 * and the corresponding BER p e * are available to the controller. The soft detection boundaries are determined in the same manner as described above with reference to  FIG. 4 a   . The controller fixes t 3 * and estimates ϵ 2 * and ϵ 3 *. Next, the same steps are repeated but for fixed t 1 * to obtain ϵ 5 * and ϵ 6 *. The bits that fall into the remaining quantization bins are highly unlikely to be erroneously detected and hence are assigned a large LLR magnitude. 
     Generalisation to Denser Cells: 
     The aforementioned procedure is generalizable to cover denser cells such as triple-level cells (TLC) and quad-level cells (QLC). This is mainly due to the separate encoding/decoding of logical pages. 
     Higher Reading Precision 
     The memory controller may need to feed the LDPC iterative decoder with a higher-precision LLRs for the decoding to be successful. For that purpose, the soft quantization bins in the uncertainty region are further divided into finer ones (e.g., as in  FIG. 6 ). Suppose that the quantization bins    2 ∪   3  and    4 ∪   5  have been estimated in the previous decoding round and that the objective is now to determine    3  and    4 . The controller is configured to estimate the BER corresponding to    3  as shown in equation (3). As the total BER associated to    2 ∪   3  (say ϵ 23 ) has been already inferred in the previous decoding attempt one has 
     
       
         
           
             
               
                 
                   
                     ϵ 
                     2 
                   
                   = 
                   
                     
                       
                         ϵ 
                         23 
                       
                       ⁡ 
                       
                         ( 
                         
                           1 
                           + 
                           
                             
                               n 
                               3 
                             
                             
                               n 
                               2 
                             
                           
                         
                         ) 
                       
                     
                     - 
                     
                       
                         ϵ 
                         3 
                       
                       ⁢ 
                       
                         
                           n 
                           3 
                         
                         
                           n 
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
     ϵ 4 , ϵ 5  are likewise determined and the blind maximization of the mutual information approach can be used to determine the soft decoding boundaries of    3  and    4  respectively. 
     The flow chart of the detection algorithm of the embodiment is depicted in  FIG. 7 . It is worth noting that if no errors are detected and the BER is set to zero the resulting LLR would be very high. This would cause decoding failure. To avoid this, a cap is applied to the permitted LLR values and, should a calculated LLR value exceed this cap the LLR value is set to a maximum LLR value LLR max  to account for estimation errors. Once soft-decoding is completed the decoded value may be output by the flash memory. 
     Known soft detection algorithms may assume that the memory channel is perfectly known to the controller. This is not practical because the memory channel depends on a plurality of factors that are not necessarily known to or quantified by the controller. This includes ambient temperature, the number of programme-erase cycles the memory cells have undergone, retention time and parasitic coupling, among others. The algorithm of the embodiments does not assume any prior channel knowledge, 
     The approach of the embodiments provides an estimate of the LLRs associated with the soft bins. The estimation does not incure additional computational costs, only a few additional sensing operations are needed. Moreover, the proposed detection scheme can be applied repeatedly to yield finer quantization until decoding is successful. 
     The performance of embodiments has been evaluated using simulation. We compared the soft detection performance of the proposed scheme against simple hard detection and a genie-aided scheme. The hard detection scheme dynamically adapts the hard decision boundary and maps the detected bit to a predetermined LLR value (a binary “0” may, for example be mapped to a predetermined LLR value of “6” while a binary “1” may be mapped to a predetermined LLR value of “−6”. These LLR values are provided to the LDPC iterative decoder to reconstruct the original data. The genie-aided scheme optimizes the hard/soft boundaries by maximizing the mutual information between the binary input and the quantized read voltage (J. Wang and et al., “Enhanced Precision Through Multiple Reads for LDPC Decoding in Flash Memories,”  IEEE Journal on Selected Areas in Communications , vol. 32, no. 5, pp. 880-891, 2014) and then counts the actual number of errors in every quantization bin which is then used to compute the actual LLR value according to Equation (7). The employed ECC is a (9216,8192) regular LDPC (randomly generated) with girth 6. As can be seen from  FIG. 8 , the proposed detector clearly outperforms the hard-decision based scheme and provides near-optimal performance. Whilst certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices, and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices, methods and products described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.