Patent Publication Number: US-8116156-B2

Title: Semiconductor memory device

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor memory device, and more particularly relates to a layout of a semiconductor memory device having a redundant memory cell that replaces a defective normal memory cell. 
     2. Description of Related Art 
     Because a semiconductor memory device represented by DRAM (Dynamic Random Access Memory) has many memory cells, it is difficult to manufacture all the memory cells without a defect. Thus, besides normal memory cells, redundant memory cells that can replace the normal memory cells when they are defective are generally prepared beforehand (see Japanese Patent Application Laid-open Nos. 2000-268596 and H6-314498). Such a semiconductor memory device uses a repair determining circuit for determining whether an address to which access is requested is a defective address, and a redundant driver circuit for accessing a redundant memory cell when the address is determined as a defective address by the repair determining circuit. 
     First, when an address is supplied from outside, whether the address is a defective address is determined by the repair determining circuit. Subsequently, either a driver circuit or a redundant driver circuit starts operating based on the result of the determination, and thereby, the access is executed to one of the normal memory cell and the redundant memory cell. 
     However, determination by the repair determining circuit takes a relatively long time. Thus, for example, in a DRAM, there is a problem that a period tRCD from inputting of an active command indicating an input timing of a row address until inputting of a read or write command indicating an input timing of a column address is rate-controlled by a determining operation performed by the repair determining circuit, and thus a random RAS access is delayed. 
     To solve such a problem, there is a method for a parallel execution of some of access operations to the normal memory cells and the determining operation by the repair determining circuit (see Japanese Patent Application Laid-open No. 2000-293998). According to this method, the access speed at the row side is improved, and thus the period tRCD can be shortened. In the case where a defective address is detected by the repair determining circuit, the normal memory cells are not accessed, thereby preventing a state that a plurality of memory cells are selected simultaneously. Specifically, after activating a main word line and before activating a sub-word line, only the sub-word lines corresponding to the redundant memory cells are activated by resetting the main word lines corresponding to the normal memory cells. 
     As described above, in a general semiconductor memory device, the determining operation by the repair determining circuit is performed first, and after its completion, the decode operation by the predecoder is performed. Thus, it is general that the repair determining circuit is placed near an address latch circuit while the predecoder is arranged near a main decoder. However, in a case of the semiconductor memory device described in Japanese Patent Application Laid-open No. 2000-293998, there is a problem that when some of the access operations to the normal memory cells are executed in parallel with the determining operation by the repair determining circuit, the distance from the repair determining circuit to the main decoder becomes considerably long as compared to the distance from the predecoder to the main decoder when the general layout, is adopted, and the effect of the high-speed access realized by the parallel operation is reduced. 
     SUMMARY 
     The present invention seeks to solve one or more of the above problems, or to improve upon those problems at least in part. 
     In one embodiment, there is provided a semiconductor memory device comprising: a memory cell array including a normal memory cell and a redundant memory cell that replaces the normal memory cell when it is defective; a first sub-word driver that selects the normal memory cell; a second sub-word driver that selects the redundant memory cell; a predecoder that predocodes an address to which access is requested irrespective of whether the address is a defective address; a main decoder that controls the first and second sub-word drivers based on a predecode signal generated by the predecoder; and a repair determining circuit that determines whether the address to which access is requested is the defective address, wherein the main decoder, the predecoder, and the repair determining circuit all have a shape in which a first direction is set to be a longitudinal direction, and the predecoder and the repair determining circuit are arranged adjacent to each other in the first direction, and are arranged in parallel with the main decoder. 
     It is preferable that the memory cell array is divided into a plurality of memory mats. In this case, it is preferable that the second sub-word driver accesses the redundant memory cell belonging to a memory mat different from a memory mat including the normal memory cell indicated by the address to which access is requested. 
     According to the present invention, the distance from the predecoder to the main decoder, and the distance from the repair determining circuit to the main decoder are almost the same, and thus in a semiconductor memory device in which the access operation to the normal memory cells is performed in parallel with the determining operation by the repair determining circuit, the high-speed access by the parallel operation can be performed effectively. Thereby, the access speed can be further improved. 
     By allocating the defective normal memory cells and the redundant memory cells that replace these cells in memory mats different to each other, it becomes possible to perform the actual access operations to the normal memory cells concurrently with the determining operation by the repair determining circuit. For example, it becomes also possible to activate the sub-word line corresponding to the defective normal memory cell, as well as the sub-word line corresponding to the redundant memory cell. Thus, as compared to the conventional technique, the access speed can be further improved. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a block diagram showing a configuration of main parts of a semiconductor memory device according to a preferred embodiment of the present invention; 
         FIG. 2  is a circuit diagram of a row predecoder shown in  FIG. 1 ; 
         FIG. 3  is a circuit diagram of a clock control circuit shown in  FIG. 1 ; 
         FIG. 4  is a signal waveform chart for explaining the operation of the clock control circuit; 
         FIG. 5  is a circuit diagram of a repair determining circuit shown in  FIG. 1 ; 
         FIG. 6  is a circuit diagram of a repair address decoder shown in  FIG. 1 ; 
         FIG. 7  is a circuit diagram of a main word driver MWD included in a main word driver shown in  FIG. 1 ; 
         FIG. 8  is a circuit diagram of a main word driver MWDR included in the main word driver; 
         FIG. 9  is a circuit diagram of a control circuit ARAC included in an array control circuit shown in  FIG. 1 ; 
         FIG. 10  is a circuit diagram of a control circuit ARACR included in the array control circuit; 
         FIG. 11  is a circuit diagram of a sub-word driver SWD included in a memory cell array shown in  FIG. 1 ; 
         FIG. 12  is a circuit diagram of a sub-word driver SWDR included in the memory cell array; 
         FIG. 13  is a circuit diagram of a sense amplifier SA included in the memory cell array; 
         FIG. 14  is a circuit diagram of a normal memory cell MC and the redundant memory cell RMC included in the memory cell array; 
         FIG. 15  is a schematic plan view for explaining an example of a preferred layout on the chips of the semiconductor memory device; 
         FIG. 16  is a schematic diagram for explaining an example of a memory mat configuration in each bank; 
         FIG. 17  is an enlarged view showing the details of the main parts of a region C shown in  FIG. 16 ; 
         FIG. 18  is a schematic diagram showing the layout of the circuits constituting a row main decoder XDEC shown in  FIG. 16 ; 
         FIG. 19  is an explanatory diagram of the configuration of the memory mats MAT and RMAT; 
         FIG. 20  is a circuit diagram of a Y switch; 
         FIG. 21  is a circuit diagram of a sub-amplifier; 
         FIG. 22  is a schematic plan view for explaining another example of a preferred layout on the chips of the semiconductor memory device; 
         FIG. 23  is a timing chart for explaining the operation when a defective address is not detected during the normal operation; 
         FIG. 24  is a timing chart for explaining the operation when a defective address is detected during the normal operation; 
         FIG. 25  is a timing chart for explaining the operation when the semiconductor memory device is in the refresh mode; 
         FIG. 26  is a schematic diagram for explaining another example of the memory mat configuration in each bank; 
         FIG. 27  is a schematic diagram for explaining still another example of the memory mat configuration in each bank; 
         FIG. 28  is a schematic diagram for explaining still another example of the memory mat configuration in each bank; 
         FIG. 29  is a schematic diagram for explaining still another example of the memory mat configuration in each bank; and 
         FIG. 30  is a circuit diagram of the repair address decoder when the layout shown in  FIG. 26  is adopted. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Preferred embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. 
       FIG. 1  is a block diagram showing a configuration of main parts of a semiconductor memory device according to a preferred embodiment of the present invention. 
     Although not particularly limited, the semiconductor memory device according to the present embodiment is a DRAM (Dynamic Random Access Memory). The DRAM includes a row system circuit that performs an access operation based on a row address and a column system circuit that performs an access operation based on a column address. In  FIG. 1 , out of the both circuits, only the row system circuit related to the present invention is shown. This is because an object of the semiconductor memory device according to the embodiment is to increase the speed of a random RAS access by shortening a period (tRCD) from inputting of an active command indicating a supply timing of a row address until inputting of a read or write command indicating a supply timing of a column address, thereby primarily ameliorating a row circuit as compared to the conventional technique. 
     As shown in  FIG. 1 , in the semiconductor memory device according to the present embodiment, an address terminal  10  to which an address signal ADD is inputted and a command terminal  20  to which a command signal CMD is inputted are arranged. A data input/output terminal, a power supply terminal or the like are also included as other external terminals. However, these components are omitted in  FIG. 1 . 
     The address signal ADD inputted to the address terminal  10  is fetched to an address latch circuit  30 . Out of the address signal ADD fetched to the address latch circuit  30 , a row address RADT is supplied to a row predecoder  100 . Although not particularly limited, the row address RADT is a 14-bit signal. The command signal CMD inputted to the command terminal  20  is decoded by a command decoder  40 , and various internal commands are generated. Out of the various internal commands, an active signal MSACT is supplied to the address latch circuit  30 , and thereby, the operation of the address latch circuit  30  is controlled. 
       FIG. 2  is a circuit diagram of the row predecoder  100 . 
     As shown in  FIG. 2 , the row predecoder  100  is configured by five decoders  110 ,  120 ,  130 ,  140 , and  150 . The row address RADT predecoded by the row predecoder  100  is a 14-bit signal, and is written as RADT&lt;13:0&gt; in  FIG. 2 . This means that the row address RADT is a 14-bit signal constituted by RADT&lt; 13 &gt; to RADT&lt; 0 &gt;. 
     The five decoders  110 ,  120 ,  130 ,  140 , and  150  configuring the row predecoder  100  decode a 2-bit RADT&lt;1:0&gt;, a 3-bit RADT&lt;4:2&gt;, a 3-bit RADT&lt;7:5&gt;, a 3-bit RADT&lt;10:8&gt;, and a 3-bit RADT&lt;13:11&gt; of the row address, respectively. Thereby, the decoder  110  generates a 4-bit predecode signal RFOB&lt;3:0&gt;, the decoder  120  generates an 8-bit predecode signal RF 2 T&lt;7:0&gt;, the decoder  130  generates an 8-bit predecode signal RF 5 T&lt;7:0&gt;, the decoder  140  generates an 8-bit predecode signal RF 8 T&lt;7:0&gt;, and the decoder  150  generates a 4-bit predecode signal RF 11 T&lt;3:0&gt; and a 2-bit predecode signal RF 13 T&lt;1:0&gt;. 
     These predecode signals are supplied to a main word driver  500  and an array control circuit  600 , as shown in  FIG. 1 . Although the detail is described later, the main word driver  500  includes two types of main word drivers MWD and MWDR, and the array control circuit  600  includes two types of control circuits, ARAC and ARACR. The main word driver MWD and the control circuit ARAC are circuits for accessing a normal memory cell MC, and the main word driver MWDR and the control circuit ARACR are circuits for accessing a normal memory cell MC or a redundant memory cell RMC. 
     On the other hand, the address latch circuit  30  synchronizes with an output timing of the row address RADT to generate a timing signal R 1 . The timing signal R 1  is supplied to a clock control circuit  200  shown in  FIG. 1 . 
       FIG. 3  is a circuit diagram of the clock control circuit  200 . 
     As shown in  FIG. 3 , the clock control circuit  200  includes delay circuits  201  to  203  that delay the timing signal R 1 . Output of the delay circuit  203  is outputted as a timing signal RLACT, and supplied to the array control circuit  600  as shown in  FIG. 1 . On the other hand, outputs of the delay circuits  201  and  202  are supplied to an NOR circuit  211 . Output of the NOR circuit  211  is supplied to a sense-amplifier control circuit  220  as a sense stop signal SAOFFT, and also supplied to the delay circuits  204  and  205 . 
     Output of the delay circuit  204  is supplied to a pulse generating circuit  230  constituted by the delay circuit  231  and the NAND circuit  232 . Output of the pulse generating circuit  230  is supplied to a flip-flop circuit  250  so that the flip-flop circuit  250  is changed to a set state. On the other hand, output of the delay circuit  205  is supplied to a pulse generating circuit  240  constituted by a delay circuit  241  and a NAND circuit  242 . Output of the pulse generating circuit  240  is supplied to the flip-flop circuit  250  so that the flip-flop circuit  250  is changed to a reset state. 
     Output of the flip-flop circuit  250  is supplied to the sense-amplifier control circuit  220 , and also outputted as a timing signal R 2 ACT. The timing signal R 2 ACT is supplied to the array control circuit  600  shown in  FIG. 1 . The sense-amplifier control circuit  220  activates a sense-amplifier operation signal SAT in response to the output of the flip-flop circuit  250 , and also inactivates the sense-amplifier operation signal SAT in response to the sense stop signal SAOFFT. As described later, the sense-amplifier operation signal SAT includes timing signals SAP 1 T, SAP 2 T, and SAN. 
     The output of the pulse generating circuit  240  is supplied also to the delay circuit  206 . Outputs of the delay circuits  201  and  206  are supplied to an OR circuit  212 . Output of the OR circuit  212  is supplied, as a fuse enable signal RFUET, to a repair determining circuit  300  shown in  FIG. 1 . 
     As shown in  FIG. 3 , a refresh signal REF is supplied to delay circuits  203  and  204 . The delay circuits  203  and  204  perform a delay operation when the refresh signal REF is activated, i.e., when the delay circuits  203  and  204   a  are in a refresh mode. When the refresh signal REF is not activated, i.e., during the normal operation, the delay circuits  203  and  204  do not perform the delay operation, and pass through the inputted signals just as they are. In place of the refresh signal REF, or in addition to the refresh signal REF, a test signal TEST that is activated during a test operation can also be used. 
       FIG. 4  is a signal waveform chart for explaining the operation of a clock control circuit  200 . In  FIG. 4 , a solid line indicates a waveform during the normal operation, and a broken line indicates a waveform during the refresh operation (or during the test operation). 
     As shown in  FIG. 4 , during both the normal operation and refresh operation, timing signals R 1 ACT and R 2 ACT are activated in this order. However, during the refresh operation, because of the delay caused by the delay circuits  203  and  204 , the timing of activating the timing signals R 1 ACT and R 2 ACT is slower than that during the normal operation. However, with respect to a timing at which the timing signals R 1 ACT and R 2 ACT return to the non-activated state, there is no difference in timing. 
       FIG. 5  is a circuit diagram of the repair determining circuit  300 . 
     As shown in  FIG. 5 , the repair determining circuit  300  includes a plurality (64 in this embodiment) of fuse sets  310 . The fuse sets  310  each store therein a defective address, that is, an address of a normal memory cell to be replaced in a non-volatile manner. The types of devices that store therein with the address are not particularly limited. A fuse device cuttable by laser beam or a large current, and an anti-fuse device capable of transitioning from a non-conductive state to a conductive state by insulation breakdown may be included. 
     Each fuse set  310  is supplied with the row address RADT and the fuse enable signal RFUET, and in response to activation of the fuse enable signal RFUET, compares the supplied row address RADT with the stored defective address. When the both addresses do not match as a result of the comparison (in a case of mishit), a corresponding mishit signal RRMIST is activated to a high level. On the other hand, when the both addresses match (in a case of hit), the corresponding mishit signal RRMIST is set to a low level. The mishit signal RRMIST is supplied to the repair address decoder  400  shown in  FIG. 1 . 
     The fuse enable signal RFUET supplied to the repair determining circuit  300  is inverted by an inverter  320 . The inverted fuse enable signal RFUEB is supplied to the repair address decoder  400 . 
     Although the details are described later, in the semiconductor memory device according to the present embodiment, a memory cell array  700  is divided into a plurality of memory mats. The redundant memory cells accessed by the respective mishit signals PRMIST are allocated memory mats which are different from those corresponding to the defective addresses stored in the corresponding fuse sets  310  and which are not adjacent to the memory mats corresponding to the defective addresses. Accordingly, when either one of the mishit signals PRMIST is activated, an alternate access is attempted to a memory mat which is different from a memory mat that should be accessed by a supplied row address RADT and which is not adjacent. 
     As described later, the semiconductor memory device according to the present embodiment is of a so-called open-bit type, and selection-side bit lines and reference-side bit lines are allocated to memory mats different to each other. Accordingly, the “non-adjacent memory mat” in the present embodiment means a memory mat different from those which are adjacent over a sense amplifier. In other words, it means that a memory mat in which selection-side bit lines are allocated is different from that in which reference-side bit lines are allocated. 
     Such an allocation can be set during a wafer test performed at the production stage. During the wafer test, an operation test is performed for all the memory cells included in the memory cell array  700 , and thereby, the address of the defective memory cells (defective address) is detected. The detected defective addresses are recorded in any fuse set  310 . The relationship between each fuse set  310  and the repair-destination memory mat is fixed, and thus depending on the fuse set  310  in which the detected defective address is recorded, the relationship between the repair-source memory mat and the repair-destination memory mat is determined. Accordingly, by recording the detected defective address in a predetermined fuse set  310 , it becomes possible to perform the allocation according to the rule. That is, the defective address of a memory mat different from the repair-destination memory mat and of a memory mat not adjacent to the repair-destination memory mat is stored in each fuse set  310 . 
     The “memory mat” is the smallest division unit of the memory cell array  700 , and the sub-word lines and bit lines are shared in the same memory mat. In the present embodiment, a word line is hierarchized into a main word line and a sub-word line, and the sub-word line becomes a gate electrode of a cell transistor. 
       FIG. 6  is a circuit diagram of the repair address decoder  400 . 
     As shown in  FIG. 6 , the repair address decoder  400  includes 16 control circuits  410  each of which receives the corresponding 4-bit misfit signal RRMIST, and a NAND circuit  420  that generates a hit signal RHITOR. 
     In response to the mishit signal RRMIST, each control circuit  410  generates corresponding 4-bit repair addresses RREDF 0 B and 1-bit repair address RREDMSB. Among these, each repair address RREDF 0 B (64 bits in all) is supplied to the array control circuit  600  shown in  FIG. 1 , and the repair address RREDMSB (16 bits in all) is supplied to the main word driver  500  and the array control circuit  600  shown in  FIG. 1 . 
     Further, the repair address RREDMSB is supplied also to the NAND circuit  420 . The NAND circuit  420  is a circuit that activates the hit signal RHITOR to a high level when any one of the 16-bit repair addresses RREDMSB is activated. That is, the hit signal RHITOR is activated when any one of the fuse sets  310  included in the repair determining circuit  300  detects a match. 
     The hit signal RHITOR, together with the repair address RREDMSB, is supplied to the main word driver  500  and the array control circuit  600 , and used as a cancel signal for canceling access to the normal memory cell. Therefore, the NAND circuit  420  generating the hit signal RHITOR constitutes a cancel-signal generating circuit of the present invention. 
     The main word driver  500  is explained next. In the main word driver  500 , a plurality of two types of main word drivers MWDs and MWDRs are included, respectively. 
       FIG. 7  is a circuit diagram of the main word driver MWD included in the main word driver  500 . 
     The main word driver MWD is a circuit that accesses to the normal memory cell MC, and includes a plurality of driver circuits  510 , a precharge control circuit  520  that determines precharge timings of nodes A 0 , A 1 , . . . , and a discharge control circuit  530  that determines discharge timings of the nodes A 0 , A 1 , . . . , as shown in  FIG. 7 . 
     The driver circuits  510  are circuits each driving the corresponding main word lines MWL 0 B&lt; 0 &gt;, &lt; 1 &gt;, based on levels of the nodes A 0 , A 1 , . . . , and is configured by a precharge transistor  511  connected between a power supply potential VPP and the nodes A 0 , A 1 , . . . , a discharge path  512  connected in series to the nodes A 0 , A 1 , . . . , a latch circuit  513  that maintains precharge states of the nodes A 0 , A 1 , . . . , and a level converting circuit  514  that level-converts output of the latch circuit  513 . 
     A gate electrode of the precharge transistor  511  is supplied with an output signal RMSXDP of the precharge control circuit  520 , and when the output signal RMSXDP becomes a low level, the nodes A 0 , A 1 , . . . are precharged to the power supply potential VPP. The discharge path  512  is constituted by three transistors connected in series to the nodes A 0 , A 1 , . . . , and gate electrodes thereof are supplied with one bit of the predecode signal RF 2 T, one bit of the predecode signal RF 5 T, and one bit of the predecode signal RF 13 T, respectively. The combination of the predecode signals RF 2 T, RF 5 T, and RF 13 T supplied to the discharge path  512  differs depending on each driver circuit  510 , and when the bits corresponding to the predecode signals RF 2 T, RF 5 T, and RF 13 T are all at a high level, the discharge path  512  becomes conductive. 
     The level converting circuit  514  is a circuit that converts a potential on a low side from a VSS level (ground level) to a VKK level (&lt;VSS). Accordingly, the main word lines MWL 0 B&lt; 0 &gt;, &lt; 1 &gt;, . . . driven by the main word driver MWD are transitioned between the VKK level and the VPP level. 
     On the other hand, the precharge control circuit  520  is configured by a plurality of logical circuits  521  to  524  and a level converting circuit  525 . The logical circuits  521  to  524  controls the precharge transistor  511  based on one bit of the predecode signal RF 8 T, one bit of the predecode signal RF 11 T, the hit signal RHITOR, and the timing signal R 1 ACT. Among these, the logical circuits  521  to  523  are operated by a normal power supply (VDD), while the logical circuit  524  is operated by a boosted power supply VPP. Accordingly, the level converting circuit  525  converts the signal level between the logical circuits  523  and  524 . 
     The combination of the predecode signals RF 8 T and RF 11 T supplied to the precharge control circuit  520  differs depending on each main word driver MWD, and when both of the bits corresponding to the predecode signals RF 8 T and RF 11 T are at a high level, the precharge of the nodes A 0 , A 1 , . . . is stopped in response to the activation of the timing signal R 1 ACT. When the hit signal RHITOR is activated, the precharge operation is resumed irrespective of the predecode signals RF 8 T and RF 11 T. 
     The discharge control circuit  530  is configured by an inverter  531  connected to the discharge path  512  and a plurality of logical circuits  532  to  535  that control the inverter  531 . The discharge control circuit  530  is supplied with timing signals R 1 ACT and R 2 ACT, and when both of the bits corresponding to the predecode signals RF 8 T and RF 11 T are at a high level, sets output of the inverter  531  to a low level and permits the discharge of the nodes A 0 , A 1 , . . . in response to the activation of the timing signal R 2 ACT. However, when the hit signal RHITOR is activated, the output of the inverter  531  is at a high level irrespective of the predecode signals RF 8 T and RF 11 T, and the discharge of the nodes A 0 , A 1 , . . . is prohibited. 
     By such a circuit configuration, the main word driver MWD can activate the predetermined main word lines MWL 0 B&lt; 0 &gt;, &lt; 1 &gt;, . . . , corresponding to the row address RADT. When the hit signal RHITOR is activated by the detection of the defective address, it becomes possible to stop the selection operation of the main word lines MWL 0 B&lt; 0 &gt;, &lt; 1 &gt;, . . . to reset all the main word lines MWL 0 B&lt; 0 &gt;, &lt; 1 &gt;, . . . , to an inactivated state. In other words, at a stage before the level of the hit signal RHITOR is finalized, the driver circuit  510  activates the main word lines MWL 0 B&lt; 0 &gt;, &lt; 1 &gt;, . . . , irrespective of whether the row address RADT is a defective address. 
     As described above, in the main word driver  500 , such a main word driver MWD is provided in plural. 
       FIG. 8  is a circuit diagram of the main word driver MWDR included in the main word driver  500 . 
     The main word driver MWDR is a circuit that accesses the normal memory cell MC or the redundant memory cell RMC, and has a configuration in which two driver circuits  540 , a precharge control circuit  550  that determines precharge timings of the nodes B 0  and B 1 , and a discharge control circuit  560  that determines discharge timings of the nodes B 0  and B 1  are added, as shown in  FIG. 8 . The rest of the configuration is the same as that of the main word driver MWD shown in  FIG. 7 , and thus the same parts are designated by the same reference numerals and redundant explanations will be omitted. 
     The driver circuit  540  is a circuit that drives the corresponding redundant main-word lines RWML 0 B&lt; 0 &gt; and &lt; 1 &gt; based on levels of the nodes B 0  and B 1 , respectively. The driver circuit  540  has a circuit configuration similar to that of the driver circuit  510  shown in  FIG. 7  except that a discharge path  542  is configured by two transistors. To one of the transistors configuring the discharge path  542 , an inverted signal of the repair address RREDMSB, which is output of the repair address decoder  400 , is supplied. 
     The precharge control circuit  550  is configured by a plurality of logical circuits  551  and  552 , and a level converting circuit  553 . The logical circuits  551  and  552  control the precharge transistor  541  based on the repair address RREDMSB and the timing signal R 1 ACT. The repair address RREDMSB is a low-active signal, and is at a high level at a normal time. When any one of the repair addresses RREDMSB is changed to a low level by the detection of the defective address, the precharges of the nodes B 0  and B 1  are stopped in response to the activation of the timing signal R 1 ACT. 
     The discharge control circuit  560  is configured by an inverter  561  connected to the discharge path  542  and a plurality of logical circuits  562  to  564  that control the inverter  561 . The discharge control circuit  560  is supplied with the timing signals R 1 ACT and R 2 ACT and the repair address RREDMSB, and when any one of the repair addresses RREDMSB is at a low level, sets the output of the inverter  561  to a low level in response to the activation of the timing signal R 2 ACT to permit the discharge of the nodes B 0  and B 1 . 
     By such a circuit configuration, in addition to the function of the main word driver MWD shown in  FIG. 7 , the main word driver MWDR becomes to be imparted with a function of activating the predetermined redundant main-word lines RMWL 0 B&lt; 0 &gt; and &lt; 1 &gt; when a defective address is detected. Thus, when the row address RADT is a defective address, the driver circuit  540  activates the redundant main-word lines RMWL 0 B&lt; 0 &gt; and &lt; 1 &gt;. 
     As described above, in the main word driver  500 , such a main word driver MWDR is provided in plural. 
     The array control circuit  600  is explained next. In the array control circuit  600 , two types of control circuits ARAC and ARACR are each included in plural. 
       FIG. 9  is a circuit diagram of a control circuit ARAC included in the array control circuit  600 . 
     As shown in  FIG. 9 , the control circuit ARAC is configured by an equalize control circuit  610  that generates an equalize signal BLEQ 0 B and a sub-word control circuit  620  that generates a sub-word line selection signal FX 0 B. The equalize control circuit  610  and the sub-word control circuit  620  are both configured by a plurality of logical circuits. 
     The equalize control circuit  610  generates the equalize signal BLEQ 0 B based on two bits of the predecode signal RF 8 T, one bit of the predecode signal RF 11 T, one bit of the predecode signal RF 13 T, the hit signal RHITOR, and the timing signals R 1 ACT and R 2 ACT. The combination of the predecode signals RF 8 T, RF 11 T, and RF 13 T supplied to the equalize control circuit  610  differs depending on each control circuit ARAC, and when the signals match a predetermined combination, the equalize signal BLEQ 0 B is inactivated to a high level. When the hit signal RHITOR is activated, the equalize signal BLEQ 0 B is at a low level (active) irrespective of the predecode signals RF 8 T, RF 11 T, and RF 13 T. 
     The sub-word control circuit  620  generates a sub-word line selection signal FX 0 B based on one bit of the predecode signal RF 0 B, two bits of the predecode signal RF 8 T, one bit of the predecode signal RF 11 T, one bit of the predecode signal RF 13 T, the hit signal RHITOR, and the timing signal R 2 ACT. The combination of the predecode signals RF 0 B, RF 8 T, RF 11 T, and RF 13 T supplied to the sub-word control circuit  620  also differs depending on each control circuit ARAC, and when the predecode signals match a predetermined combination, the sub-word-line selection signal FX 0 B is activated to a low level. When the hit signal RHITOR is activated, the sub-word line selection signal FX 0 B is at a high level (inactive) irrespective of the predecode signals RF 0 B, RF 8 T, RF 11 T, and RF 13 T. 
       FIG. 10  is a circuit diagram of a control circuit ARACR included in the array control circuit  600 . 
     As shown in  FIG. 10 , the control circuit ARACR is configured by an equalize control circuit  630  that generates an equalize signal BLEQ 0 B and a sub-word control circuit  640  that generates a sub-word line selection signal FX 0 B. The equalize control circuit  630  and the sub-word control circuit  640  are both configured by a plurality of logical circuits. 
     The equalize control circuit  630  is similar to the equalize control circuit  610  shown in  FIG. 9 , however, differs in that it generates the equalize signal BLEQ 0 B additionally based on the repair address RREDMSB. By the circuit configuration shown in  FIG. 10 , the equalize control circuit  630  inactivates the equalize signal BLEQ 0 B to a high level not only when the predecode signals RF 8 T, RF 11 T, and RF 13 T match a predetermined combination but also when the repair address RREDMSB is activated. 
     The sub-word control circuit  640  is also similar to the sub-word control circuit  620  shown in  FIG. 9 , however, differs in that it generates the sub-word line selection signal FX 0 B additionally based on the repair address RREDF 0 B. By the circuit configuration shown in  FIG. 10 , the sub-word control circuit  640  activates the sub-word line selection signal FX 0 B to a low level not only when the predecode signals RF 0 B, RF 8 T, RF 11 T, and RF 13 T match a predetermined combination, but also when the repair address RREDF 0 B is activated. 
     Various signals generated by the main word driver  500  and the array control circuit  600  are supplied to the memory cell array  700  shown in  FIG. 1 . In the memory cell array  700 , a plurality of sub-word drivers SWD and SWDR that drive the sub-word line SWL and the redundant sub-word line RSWL, respectively, and a plurality of sense amplifiers SA connected to the bit line BL are arranged. At a crosspoint between the sub-word line SWL and the bit line BL, the normal memory cell MC is arranged, and at a crosspoint between the redundant sub-word line RSWL and the bit line BL, the redundant memory cell RMC is arranged. Although not shown, in the actual memory cell array  700 , the redundant bit line or the like are also arranged. 
       FIG. 11  is a circuit diagram of the sub-word driver SWD. 
     As shown in  FIG. 11 , the sub-word driver SWD is configured by an inverter  710  that inverts the level of the main word line MWL 0 B, an inverter  711  that supplies voltage to the inverter  710  based on the sub-word line selection signal FX 0 B, and a reset transistor  712  that resets the sub-word line SWL based on the sub-word line selection signal FX 0 B. By such a configuration, both the main word line MWL 0 B and the sub-word line selection signal FX 0 B are activated to a low level, the corresponding sub-word line SWL is driven to a high level. In other cases, the corresponding sub-word line SWL is fixed to a low level. 
       FIG. 12  is a circuit diagram of the sub-word driver SWDR. As shown in  FIG. 12 , the sub-word driver SWDR has the same circuit configuration as that of the sub-word driver SWD shown in  FIG. 11  except that a redundant main-word line RMWL 0 B and a redundant sub-word line RSWL are used instead of the main word line MWL 0 B and the sub-word line SWL. 
       FIG. 13  is a circuit diagram of the sense amplifier SA. 
     As shown in  FIG. 13 , the sense amplifier SA includes a sense circuit unit  720  connected to bit-line pairs BLT and BLB, an equalize circuit  730  that equalizes the sense circuit unit  720 , and a driver circuit  740  that drives the sense circuit unit  720 , and serves a role for amplifying data of the accessed normal memory cell MC or redundant memory cell RMC. 
     The sense circuit unit  720  is a cross-coupled flip-flop circuit of which the one input/output node a 1  is connected to a bit line BLT and of which the other input/output node a 2  is connected to a bit line BLB. The equalize circuit  730  is a circuit that is activated in response to the equalize signal BLEQ 0 B. When the equalize signal BLEQ 0 B is at a low level, the equalize circuit  730  equalizes the input/output nodes a 1  and a 2  of the sense circuit unit  720  to the same potential VBLP. At this time, wirings PCS and NCS that supply an operation voltage to the sense circuit unit  720  are also equalized to the same potential. 
     The driver circuit  740  is a circuit that supplies an operation voltage to the sense circuit unit  720  via the wirings PCS and NCS, and is configured by transistors  741  and  742  connected to the wiring PCS and a transistor  743  connected to the wiring NCS. 
     The transistor  741  is a transistor that supplies an overdrive potential VOD (&gt;VARY) to the wiring PCS in response to the timing signal SAP 1 T, and is turned on in an initial stage of a sense operation. The transistor  742  is a transistor that supplies an array potential VARY (high-side potential of the memory cell) to the wiring PCS in response to the timing signal SAP 2 T, and is turned on after the end of the overdrive by the transistor  741 . The transistor  743  is a transistor that supplies a ground potential VSS (low-side potential of the memory cell) to the wiring NCS in response to the timing signal SAN, and is turned on all the time during the sense operation. As described above, the timing signals SAP 1 T, SAP 2 T, and SAN configure the sense-amplifier operation signal SAT shown in  FIG. 1  and  FIG. 3 . 
     When the equalize circuit  730  is in an inactivated state and the driver circuit  740  is in an activated state by such a circuit configuration, data reading and writing to and from the memory cells MC and RMC via the bit-line pairs BLT and BLB become possible. 
       FIG. 14  is a circuit diagram of the normal memory cell MC and the redundant memory cell RMC. 
     As shown in  FIG. 14 , the normal memory cell MC and the redundant memory cell RMC have the same circuit configuration, and both are configured by a cell transistor CT and a storage capacitor SC connected in series to the bit line BL (BLT or BLB). In the normal memory cell MC, a gate electrode of the cell transistor CT is connected to the sub-word line SWL, and in the redundant memory cell RMC, a gate electrode of the cell transistor CT is connected to the redundant sub-word line RSWL. By such a configuration, when the sub-word line SWL or the redundant sub-word line RSWL is activated, the corresponding cell transistor CT is turned on, and the storage capacitor SC is connected to the bit line BL. Thereby, it becomes possible to transmit and receive charge via the bit line BL. 
     Thus, the circuit configuration of the semiconductor memory device is described. By such a circuit configuration, at a stage before the level of the hit signal RHITOR is finalized, the sub-word driver SWD can execute an access operation to the normal memory cell irrespective of whether the row address RADT is a defective address. When the row address RADT is a defective address, the sub-word driver SWDR can execute an access operation to the redundant memory cell. 
     A preferred layout on the chips of the semiconductor memory device is described next. 
       FIG. 15  is a schematic plan view for explaining an example of the preferred layout on the chips of the semiconductor memory device. 
     As shown in  FIG. 15 , in this example, the memory cell array  700  is divided into eight banks from BANK 0  to BANK 7 . A row main decoder XDEC, a column decoder YDEC, a read-write amplifier RWAMP, a repair determining circuit RF, a row predecoder RP, a column fuse CF, and a column predecoder CP are allocated to each bank, respectively. 
     Among these, the row main decoder XDEC is a circuit block including the main word driver  500  and the array control circuit  600  shown in  FIG. 1 . The repair determining circuit RF shown in  FIG. 15  is a circuit block including not only the repair determining circuit  300  but also the repair address decoder  400  shown in  FIG. 1 . Further, the row predecoder RP is a circuit block including the row predecoder  100  and the clock control circuit  200  shown in  FIG. 1 . A plurality of external terminals including the address terminal  10  and the command terminal  20  shown in  FIG. 1  are arranged in a region between the even-numbered banks BANK 0 , BANK 2 , BANK 4 , and BANK 6 , and odd-numbered banks BANK 1 , BANK 3 , BANK 5 , and BANK 7 . 
     As shown in  FIG. 15 , all of the row main decoder XDEC, the row predecoder RP, and the repair determining circuit RF have a shape in which the column direction is set to be a longitudinal direction. Therefore, the row predecoder RP and the repair determining circuit RF are arranged adjacent to each other in the column direction, and are arranged parallel to the row main decoder XDEC. The read-write amplifier RWAMP also has a shape in which the column direction is set to be a longitudinal direction, and is arranged parallel to the row main decoder XDEC. 
       FIG. 16  is a schematic diagram for explaining an example of the memory mat configuration in each bank. 
     As shown in  FIG. 16 , in the present embodiment, each bank is divided into two by the row main decoder XDEC, and each part is configured by memory mats MAT or RMAT of 33 rows×16 columns. Among the memory mats shown in  FIG. 16 , those shown as shaded are the memory mats RMAT (redundant memory mats) that include the redundant sub-word lines RSWL, and the other are the memory mats MAT (normal memory mats) that do not include the redundant sub-word lines RSWL. 
     In the present embodiment, 256 sub-word lines SWL and 512 bit lines BL are allocated to one memory mat MAT, and normal memory cells MC are arranged at their cross points. In contrast, eight redundant sub-word lines RSWL are added to the memory mat RMAT, and the redundant memory cells RMC are arranged at the cross points of the redundant sub-word lines RSWL and bit lines BL. 
     While column redundant circuits such as redundant bit lines are also included in practice, explanations thereof will be omitted. 
     When it is assumed that the leftmost row shown in  FIG. 16  as a row number  0 , the memory mats RMAT that include the redundant sub-word lines RSWL are to be arranged in the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth rows. The Memory mats RMAT arranged in the same rows are those that are selected by the same redundant main word line RMWL 0 B. As shown in  FIG. 16 , the repair determining circuit RF is arranged in the lower part of the rows in which the memory mats RMAT are arranged, and each fuse set  310  (see  FIG. 5 ) and the control circuit  410  (see  FIG. 6 ) included in the repair determining circuit RF are arranged in the corresponding row or in its vicinity. Thereby, redundant signals RREDMSB and RREDF 0 B can be arranged almost linearly, without having to route their wiring. 
     As described above, the reason for the uneven distribution of the memory mats RMAT in a part of the area of the memory cell array (the left-side area in  FIG. 16 ) is to attempt to substantially match the positions in the column direction of each row in which memory mats RMAT are arranged and the corresponding fuse sets  310 . As shown in  FIG. 16 , the reason for arranging memory mats RMAT in alternate rows is because the area occupied by fuse sets  310  on the chips is comparatively large, and by arranging the memory mats RMAT in alternate rows, the corresponding positions of the memory mats RMAT and the fuse set  310  can be substantially aligned. Accordingly, when the size of fuse sets  310  is relatively large, the memory mats RMAT can even be, for example, arranged in every third row, and conversely, when the size of the fuse sets  310  is relatively small, the memory mats RMAT can even be arranged continuously. When selecting the repair-destination memory mats, it is necessary to select memory mats which are different from the repair-source memory mats and which are not adjacent to the repair-source memory mats. Thus, by arranging the memory mats RMAT in alternate rows, the repair efficiency can be also increased. 
     The row predecoder RP is arranged adjacent to the repair determining circuit RF. This is because in the semiconductor memory device, the determining operation by the repair determining circuit and the access operation to the normal memory cells MC by the row predecoder RP are performed in parallel, as described later, and thus it is desired that the distance from the row predecoder RP to the row main decoder XDEC and the distance from the repair determining circuit RF to the row main decoder XDEC are as equal as possible. 
     That is, in a general semiconductor memory device, the determining operation by the repair determining circuit is performed first, and it is only after this operation is completed that the decode operation by the row predecoder is performed. Thus, it is desired that the repair determining circuit be arranged near the address latch circuit, while the row predecoder be arranged near the row main decoder. However, when such an arrangement is adopted in the present embodiment, the distance from the repair determining circuit RF to the row main decoder XDEC becomes considerably long as compared to the distance from the row predecoder RP to the row main decoder XDEC, and the effect of the high-speed access by the parallel operation is reduced. 
     In contrast, in the present embodiment, according to the layout shown in  FIG. 16 , the distance from the row predecoder RP to the row main decoder XDEC, and the distance from the repair determining circuit RF to the row main decoder XDEC are substantially the same, and thus it becomes possible to effectively execute high-speed access by the parallel operation. 
     As shown in  FIG. 16 , the column fuse CF and the column predecoder CP are arranged in parallel next to the row predecoder RP. The read-write amplifier RWAMP is arranged between the repair determining circuit RF, the row predecoder RP, the column fuse CF, and the column predecoder CP and the memory mats MAT and RMAT. 
       FIG. 17  is an enlarged view showing the details of the main parts of a region C shown in  FIG. 16 . 
     As shown in  FIG. 17 , signal wirings of two redundant signals RREDMSB and eight redundant signals RREDF 0 B (total 10) are arranged on each row in which the memory mats RMAT are arranged. There are eight rows in which the memory mats RMAT are arranged, and thus the number of these redundant signals is 80 in all. On the other hand, eight main I/O lines MIO connected to the read-write amplifiers RWAMP are arranged on the memory mats MAT each arranged on the even-numbered rows, respectively. Apart from these, approximately 40 signal wires are arranged from the row predecoders RP to the row main decoders XDEC. Thus, when the wirings of redundant signals RREDMSB and RREDF 0 B are arranged on the corresponding memory mats RMAT, the wiring length can be shortened to the minimum limit. 
       FIG. 18  is a schematic diagram showing the layout of the circuits constituting the row main decoder XDEC. 
     As shown in  FIG. 18 , the row main decoder XDEC is configured by 33 main word drivers MWD and MWDR and the control circuits ARAC and ARACR arranged between the adjacent driver circuits. The circuit configuration of these main word drivers MWD and MWDR, as well as that of control circuits ARAC and ARACR, is as shown in  FIG. 7  to  FIG. 10 , respectively. 
     The main word driver MWD is a circuit that drives  64  main word lines MWL 0 B and 64 main word lines MWL 1 B, respectively. In addition to these main word lines, the main word driver MWDR also drives two redundant main word lines RMWL 0 B and two redundant main word lines RMWL 1 B. 
     33 main word drivers MWD and MWDR respectively correspond to each row of memory mats MAT and RMAT shown in  FIG. 16 . Accordingly, the main word drivers MWDR are allocated to the rows corresponding to the memory mats RMAT that include the redundant sub-word lines RSWL. The main word drivers MWD are allocated to the other rows. 
       FIG. 19  is an explanatory diagram of the configuration of the memory mats MAT and RMAT, and  FIG. 19  is an enlarged view of a region D shown in  FIG. 16 . 
     As shown in  FIG. 19 , a plurality of sense amplifiers SA are arranged between the memory mats MAT and RMAT adjacent in the column direction. As shown with the help of  FIG. 13 , the sense amplifier SA is a circuit connected to a pair of bit lines BLT and BLB that amplifies their potential difference. The semiconductor memory device has a so-called open-bit type layout, and accordingly, these pairs of bit lines BLT and BLB are allocated to the memory mats MAT and RMAT different to each other. That is, the two adjacent memory mats share the same sense amplifier. 
     A sub-word driver SWD is arranged in the row direction of the memory mat MAT, and a sub-word driver SWDR is arranged in the row direction of the memory mat RMAT. The circuit configurations of sub-word drivers SWD and SWDR are as shown in  FIG. 11  and  FIG. 12 , respectively. 
     According to such a layout, when the sub-word line SWL belonging to a certain memory mat MAT or RMAT is selected, a bit line BL belonging to the adjacent memory mat MAT or RMAT is used as the reference-side bit line. In consideration of this point, in the present embodiment, the corresponding repair-source memory mat and repair-destination memory mat are differed, and allocated in a manner that they are not adjacent to each other. The “repair-source memory mat” indicates a memory mat MAT or RMAT corresponding to a defective address stored in the fuse hit  310 , and the “repair-destination memory mat” indicates a memory mat RMAT accessed by a mishit signal PRMIST that is activated by the defective address. 
     Accordingly, as the replacement destination of the central memory mat MAT shown in  FIG. 19 , a memory mat RMAT other than the left and right memory mats RMAT adjacent in the column direction (that is, another memory mat RMAT that is not shown in  FIG. 19 ) is allocated. The reason for adopting such an allocation is that an access to the normal memory cell MC corresponding to the row address RA is executed in parallel, without waiting for the determining operation of the repair determining circuit  300 . 
     That is, in the present embodiment, there is a period during which both the repair-source sub-word line SWL and the repair-destination redundant sub-word line RSWL are activated when a defective address is detected by the repair determining circuit  300 , and thus it is definitely not possible to allocate both in the same memory mat, and it is not possible to allocate them in the adjacent memory mats sharing the same sense amplifier SA, either. This is because when such an allocation is adopted, the two sub-word lines (the repair-source sub-word line SWL and the repair-destination redundant sub-word line RSWL) are selected simultaneously for a pair of bit lines BLT and BLB. To avoid such abnormality, the above allocation is adopted in the present embodiment. 
     The output of the sense amplifier SA is supplied to a local I/O line LIO via a Y switch YSW shown in  FIG. 20 . In the example shown in  FIG. 20 , a single sense amplifier block is connected to four pairs of local I/O lines LIO (LIOT and LIOB) by the Y switch YSW. The read data supplied to the local I/O line LIO is supplied to a main I/O line MIO via a sub-amplifier SAMP shown in  FIG. 21 . In the sub-amplifier SAMP shown in  FIG. 21 , when the memory mats are not selected, signals LIOEQB, LIOREAD, and LIOWRIT are at a low level while the signal LIOPREB is at a high level. On the other hand, when the memory mats are selected, the signal LIOEQB becomes high level, and the signals LIOPREB, LIOREAD, and LIOWRIT are used to perform control. The main I/O line MIO connected to the local I/O line LIO by the sub-amplifier SAMP is connected to a read-write amplifier RWAMP, as described above. 
     An example of the preferred layout on the chips of the semiconductor memory device is as described above. 
       FIG. 22  is a schematic plan view for explaining another example of the preferred layout on the chips of the semiconductor memory device. 
     In the example shown in  FIG. 22 , the memory cell array  700  is divided into four banks from BANK 0  to BANK 3 . The row main decoder XDEC is arranged along a first side (side in the column direction) of the memory cell array, and the read-write amplifier RWAMP is arranged along a second side (side in the row direction) orthogonal to the first side of the memory cell array. 
     Also in this example, the repair determining circuit RF and the row predecoder RP are arranged in parallel, and the distance from the row main decoder XDEC is set substantially the same. However, contrary to the layout shown in  FIG. 15 , the row main decoder XDEC and the repair determining circuit RF, and the row predecoder RP are arranged adjacently, and no read-write amplifier RWAMP or the like exists therebetween. 
     According to this layout, the distance between the row main decoder XDEC and the repair determining circuit RF, and the row predecoder RP is shortened considerably, and thus the load capacitance of the wiring connecting these is substantially reduced, enabling not only a higher-speed access but also a reduction in the power consumption. Moreover, due to the fact that no read-write amplifier RWAMP exists between the row main decoder XDEC, and the repair determining circuit RF and the row predecoder RP, there is no need to route wirings for the predecode signals and the redundant signals to avoid the read-write amplifier RWAMP. 
     Thus, according to the layout shown in  FIG. 22 , it is possible to achieve a higher speed access and reduced power consumption. 
     The operation of the semiconductor memory device is described next. 
       FIG. 23  is a timing chart for explaining the operation when a defective address is not detected during the normal operation. 
     First, as shown in  FIG. 23 , when the row address RA is inputted simultaneously of the issuance of the active command ACT, an active signal MSACT, a fuse enable signal RFUET, and a timing signal R 1 ACT are activated, and a sense stop signal SAOFFT is non-activated at time t 11 . Thereby, the determining operation by the repair determining circuit  300  is started, and also precharging of nodes A 0 , A 1 , . . . within the main word driver  500  is stopped. The change timing of these signals needs not to match completely, and these signals can change sequentially with a predetermined time difference. 
     A certain amount of time is taken for the determining operation by the repair determining circuit  300 , and thus the level of the hit signal RHITOR is not finalized at this point. 
     The timing signal R 2 ACT is activated next at time t 12 . Thereby, the discharge of nodes A 0 , A 1 , . . . within the main word driver  500  is allowed. Thus, when predecode signals RF 2 T, RF 5 T, RF 8 T, RF 11 T, and RF 13 T are finalized, any one of the main word lines MWL 0 B is activated. 
     Further, in response to the activation of the timing signal R 2 ACT, the non-activation of an equalize signal BLEQ 0 B by an array control circuit  600 , and the activation of a sub-word-line selection signal FX 0 B are allowed. Thus, when predecode signals RF 0 B, RF 8 T, RF 11 T, and RF 13 T are finalized, together with the non-activation of the predetermined equalize signal BLEQ 0 B, the sub-word-line selection signal FX 0 B is activated. 
     Thereby, the sub-word lines SWL corresponding to the row address RADT are activated, and the corresponding normal memory cells MC are selected. However, even at this point, the level of the hit signal RHITOR is not finalized. Thus, it is probable that the activated main word lines MWL 0 B is the main word lines MWL 0 B corresponding to the defective address, and the activated sub-word lines SWL is the sub-word lines SWL corresponding to the defective address. In this way, irrespective of whether the row address RADT is defective, the sub-word driver SWD preferentially accesses the normal memory cell MC. 
     Thereafter, the determining operation by the repair determining circuit  300  is completed at time t 13 , and the level of the hit signal RHITOR is finalized.  FIG. 23  shows the operation when a defective address is not detected, and thus the hit signal RHITOR maintains a low level even at time t 13 . Accordingly, operations such as resetting of the main word line MWL 0 B and the sub-word-line selection signal FX 0 B are not performed, and the access operation is continued as it is. 
     Thereafter, the driver circuit  740  within the sense amplifier SA is activated at time t 14 , and the sense operation is started. Thereby, reading or writing of the data from and to the selected normal memory cell MC is executed. 
     As described above, in the present embodiment, the access to the normal memory cells MC corresponding to row addresses RA is executed without waiting for the determining operation by the repair determining circuit  300 . That is, the determining operation by the repair determining circuit  300  and the actual access operation to the normal memory cells MC are executed in parallel. Thereby, the period T 1  from the supply of the row address RA until the activation of the sense amplifier SA can be shortened. Accordingly, the period (tRCD) from inputting of the active command until inputting of the read or write command can be shortened, and the speed of the random RAS access can be accelerated. 
       FIG. 24  is a timing chart for explaining the operation when a defective address is detected during the normal operation. 
     As shown in  FIG. 24 , as a result of the determining operation by the repair determining circuit  300 , when it is detected that the row address RADT is a defective address, any one of the mishit signals RRMIST is non-activated, and the hit signal RHITOR is changed to high level at time t 13 . 
     Thereby, the main word drivers MWD and MWDR again return the nodes A 0 , A 1 , . . . that are already discharged at time t 12  to the precharged state. That is, the main word line MWL 0 B that is activated preferentially is reset. Any one of the redundant signals RREDMSB is activated, and thus the discharge of the nodes B 0  and B 1  within the main word driver MWDR is allowed, and any one of the redundant main word lines RMWL 0 B is activated. 
     Thereby, the sub-word line SWL corresponding to the row address RADT; i.e., the repair-source sub-word line SWL is reset, and in place thereof, the sub-word driver SWDR activates the repair-destination redundant sub-word line RSWL. 
     As described above, the memory mat RMAT to which the repair-destination redundant sub-word line RSWL belongs is that which is different from the memory mats MAT and RMAT to which the repair-source sub-word line SWL belongs and which are not adjacent to one another. Thus, the two sub-word lines (the repair-source sub-word line SWL and the repair-destination redundant sub-word line RSWL) are not selected for a pair of bit lines BLT and BLB, and the replacement operation can be performed correctly. 
     When the sense operation is started at time t 14 , reading or writing of the data from or to the redundant memory cell RMC is executed. 
     In the present embodiment, the repair-source sub-word lines SWL are activated once, and thus the data of the memory cells MC connected to these sub-word lines SWL are destructed. However, since these memory cells MC are not in use (cannot be accessed), even when the data is destruction, there is no problem. From this viewpoint, it is not essential to reset the repair-source sub-word lines SWL before starting the sense operation, and as long as data does not collide on the local I/O lines LIO and main I/O lines MIO, the sense operation can be performed in both the repair destination as well as the repair source. However, when the sense operation is performed on the repair source, the unnecessary power consumption increases, and thus it is preferable to reset the repair-source sub-word lines SWL before starting the sense operation, as described in the present embodiment. 
       FIG. 25  is a timing chart for explaining the operation when the semiconductor memory device is in the refresh mode. Although  FIG. 25  shows a case that a defective address is detected, except for the fact that the hit signal RHITOR is fixed at low level, the same applies to the case that a defective address is not detected. 
     As shown in  FIG. 25 , during the refresh operation, the activation of timing signals R 1 ACT and R 2 ACT is delayed for a certain time period. Specifically, these timing signals R 1 ACT and R 2 ACT are activated after the lapse of the time t 13  when the level of the hit signal RHITOR is determined. As shown in  FIG. 25 , the timing signal R 1 ACT is activated at time t 14 , and the timing signal R 2 ACT is activated at time t 15 . Along with this, the start timing of the sense operation is also delayed up to time t 16 . Such a delay is caused by the operation of the clock control circuit  200  shown in  FIG. 3 . 
     Thereby, during the refresh operation, the sub-word lines SWL or the redundant sub-word lines RSWL are selected after the level of the hit signal RHITOR is finalized. That is, similar to a general semiconductor memory device, the sub-word lines SWL or the redundant sub-word lines RSWL are activated after waiting for the result of the determining operation by the repair determining circuit  300 . Accordingly, when the row address RADT is a defective address, the sub-word driver SWD does not execute the access to the normal memory cell MC. 
     As described above, during the refresh operation in which a high-speed access is not requested, the parallel operation is not performed, and the sub-word lines SWL or the redundant sub-word lines RSWL are activated after waiting for the result of the determining operation by the repair determining circuit  300 . Thus, the power consumption during the refresh operation can be reduced. Stopping the parallel operation in this way can be performed not only during the refresh operation, but also during various operation modes (such as the test mode) in which a high-speed access is not requested. 
     As described above, according to the present embodiment, the access to the normal memory cell MC corresponding to the row address RA is executed without waiting for the determining operation by the repair determining circuit  300 , and thus the period T 1  from the supply of the row address RA until the activation of the sense amplifier SA can be shortened. Thus, the period (tRCD) from inputting of the active command until inputting of the read or write command can be shortened. 
     Furthermore, the memory mats RMAT that are different from the repair-source memory mats MAT and RMAT and that are not adjacent are allocated as the repair-destination memory mats. Accordingly, even when the access to the normal memory cell MC is preferentially attempted, the read operation and write operation can be correctly performed. 
     Further, as in the refresh operation, because the parallel operation is stopped in operation modes in which the high-speed access is not requested, the power consumption in such operation modes can be also reduced. 
     In the present embodiment, the row predecoder RP and the repair determining circuit RF are arranged adjacent to each other, thereby resulting in the layout in which the distance from the row predecoder RP to the row main decoder XDEC and that from the repair determining circuit RF to the row main decoder XDEC are substantially the same. Thus, the high-speed access can be performed effectively by the parallel operation. 
       FIG. 26  is a schematic diagram for explaining another example of the memory mat configuration in each bank. 
     In the example shown in  FIG. 26 , each bank is divided into two by the row main decoder XDEC, and each part is configured by the memory mats MAT or RMAT of 17 rows×16 columns. Among the memory mats shown in  FIG. 26 , those shown as shaded are the memory mats RMAT that include the redundant sub-word lines RSWL, and the rest are the memory mats MAT that do not include the redundant sub-word lines RSWL. Five hundred twelve sub-word lines SWL and 512 bit lines BL are allocated to one memory mat MAT, and the normal memory cells MC are arranged at their cross points. In contrast, eight redundant sub-word lines RSWL are added to a memory mat RMAT, and redundant memory cells RMC are arranged at the cross points of the redundant sub-word lines RSWL and bit lines BL. 
     That is, as compared to the example shown in  FIG. 16 , in the example shown in  FIG. 26 , the number of the sub-word lines SWL included in a single memory mat is increased from 256 to 512. Thereby, the number of sense amplifiers is reduced by half, so that the chip area can be compressed. However, as compared to the example shown in  FIG. 16 , the bit line capacitance increases, and thus the access speed is slightly lowered. 
     In this example, when it is assumed the leftmost row as a row number  0 , the memory mats RMAT that include the redundant sub-word lines RSWL are arranged in first, second, fourth, fifth, seventh, eighth, tenth, and eleventh rows. That is, three memory mats including two adjacent memory mats RMAT and one memory mat MAT are provided as one set, and these sets are arranged repeatedly. 
     In this example, the repair determining circuit RF is divided into two, i.e., repair determining circuits RF 1  and RF 2 , and while the repair determining circuit RF 1  is allocated to the memory mats RMAT of the first, second, fourth, and fifth rows, the repair determining circuit RF 2  is allocated to the memory mats RMAT of the seventh, eighth, tenth, and eleventh rows. The row predecoder RP is arranged between these two repair determining circuits RF 1  and RF 2 . According to this layout, a nearly linear layout can be achieved, without having to route the wiring for redundant signals. 
     That is, as shown in  FIG. 27 , similar to the example shown in  FIG. 16 , when the memory mats RMAT are arranged in the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth rows, the positions in the column direction of the memory mats RMAT are dispersed, and this results in a longer length of the wiring of the redundant signals. 
     First, as shown in  FIG. 28 , when the memory mats RMAT are arranged in the first to eighth rows, the memory mats RMAT can be distributed unevenly in the left area of the memory cell array. However, in such a case, the repair efficiency declines. That is, when it is assumed that the repair-source memory mat is in the second row, the memory mats RMAT in the adjacent first and third rows cannot be selected as the repair destination, and thus the repair-destination memory mat RMAT is limited to the memory mats RMAT in the fourth to eighth rows (40 redundant sub-word lines RSWL). 
     When the number of the redundant sub-word lines RSWL allocated to a single memory mat RMAT is increased from 8 to 16, the memory mats RMAT can be unevenly distributed in the left area of the memory cell array, as shown in  FIG. 29 . However, in such a case, the repair efficiency declines further. That is, when it is assumed that the repair-source memory mat is in the second row, the memory mats RMAT in the adjacent first and third rows cannot be selected as the repair destination, and thus the repair-destination memory mat RMAT is limited to the memory mats RMAT in the fifth and seventh rows (32 redundant sub-word lines RSWL). 
     In contrast, when the layout shown in  FIG. 26  is adopted, it becomes possible to secure high repair efficiency while preventing routing the wiring of the redundant signals. That is, when it is assumed that the repair-source memory mat is in the third row, the memory mats RMAT in the adjacent second and fourth rows cannot be selected as the repair destination. However, because the repair-destination memory mat RMAT can be selected from the memory mats RMAT in the first, fifth, seventh, eighth, tenth, and eleventh rows, 48 redundant sub-word lines RSWL can be used. 
       FIG. 30  is a circuit diagram of the repair address decoder  400  when the layout shown in  FIG. 26  is adopted. 
     In the example shown in  FIG. 16 , the output signal of the repair address decoder  400  is supplied as it is to the row main decoder XDEC. However, when the layout shown in  FIG. 26  is adopted, a logic gate  430  with up to two levels needs to be present in the output signal of the repair address decoder  400 , as shown in  FIG. 30 . This is because in contrast to the alternate arrangement of the memory mats MAT and RMAT in the layout shown in  FIG. 16 , the memory mats MAT are arranged in every third row in the layout shown in  FIG. 26 . 
     As shown in  FIG. 30 , when the layout shown in  FIG. 26  is adopted, the number of logic gates slightly increases. However, as is obvious from  FIG. 30 , the number of logic levels in each signal path is all within four, and this feature remains the same in comparison with the maximum number of logic levels when the layout shown in  FIG. 16  is adopted (see  FIG. 6 ). Accordingly, despite the fact that the number of logic gates increases, there is no change in the maximum number of logic levels, and thus the access speed is not lowered due to an increase in the number of logic gates. 
     It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention. 
     In the above embodiment, the present invention is applied to the DRAM as an example. However, an application target of the present invention is not limited thereto, and the present invention can be also applied to other types of semiconductor memory devices such as a flash memory, a phase change memory (PRAM), and a variable resistance memory (RRAM). 
     In the present embodiment, both the sub-word lines SWL corresponding to the defective normal memory cells MC, and the redundant sub-word lines RSWL corresponding to the redundant memory cells RMC are activated. However, this is not essential in the present invention. That is, although the parallel operation is performed partially, as in the semiconductor memory device of Japanese Patent Application Laid-open No. 2000-293998, when a defective address is detected by the repair determining circuit, a method in which the access to the normal memory cell is not executed can be used. In such a case, any memory mat can be allocated as the repair destination, and it is not necessary to allocate a memory mat that is different from the repair-source memory mat and that is not adjacent, as described in the above embodiment. 
     In the above embodiment, a memory mat that is different from the repair-source memory mat and that is not adjacent is allocated as the repair-destination memory mat. However, as in a folded-bit type layout, in a case of a circuit configuration in which the same sense amplifier is not shared between the two adjacent memory mats, any memory mat can be allocated as the repair-destination memory mat as long as it is different from the repair-source memory mat. That is, in the present invention, it is not essential to allocate the memory mat not adjacent to the repair-source memory mat as the repair-destination memory mat. 
     In the above embodiment, when the row address RADT is a defective address, access to the normal memory cell is interrupted in the middle. However, as long as there is no collision of data on the I/O lines or the like, it is not essential to interrupt the access to the normal memory cell in the middle.