Patent Publication Number: US-2023152518-A1

Title: Photonic chip security structure

Description:
FIELD OF THE INVENTION 
     The present disclosure relates to semiconductor structures and, more particularly, to a photonic chip security structure and methods of manufacture. 
     BACKGROUND 
     Photonic semiconductors have many applications in modern consumer electronics. For example, photonic semiconductors include optical modulators, quantum well (QW) lasers, photodiodes, and waveguide structures, etc. Silicon waveguides are also of special interest as they have unique guiding properties. For example, due to their unique guiding properties, waveguides can be used for communications, interconnects, and biosensors. 
     Silicon photonic devices can be made using existing semiconductor fabrication techniques, and because silicon is already used as the substrate for most integrated circuits, it is possible to create hybrid devices in which the optical and electronic components are integrated onto a single microchip. However, unlike electronic devices which have known protection techniques, the silicon photonic devices remain vulnerable to both physical and non-invasive attacks aimed at obtaining cryptographic encryption keys, certificates, intellectual property and other critical or sensitive data. 
     SUMMARY 
     In an aspect of the disclosure, a structure includes an optical component; and a photonic chip security structure including a vertical wall composed of light absorbing material surrounding the optical component. 
     In an aspect of the disclosure, a structure includes a semiconductor on insulator substrate; an optical component on the semiconductor on insulator substrate; a dielectric stack of material over the semiconductor on insulator substrate; and a vertical wall with lateral projections within the dielectric stack of material and surrounding the optical component. 
     In an aspect of the disclosure, a method includes forming an optical component; and forming a photonic chip security structure including a vertical wall composed of light absorbing material surrounding the optical component and further comprising lateral projections. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure. 
         FIG.  1    shows an optical component, amongst other features, and respective fabrication processes in accordance with aspects of the present disclosure. 
         FIG.  2    shows trenches formed through a dielectric stack and surrounding the optical component, amongst other features, and respective fabrication processes in accordance with aspects of the present disclosure. 
         FIG.  3    shows lateral projections extending from the trenches, amongst other features, and respective fabrication processes in accordance with aspects of the present disclosure. 
         FIG.  4    shows the trenches filled with light absorbing material, amongst other features, and respective fabrication processes in accordance with aspects of the present disclosure. 
         FIGS.  5 - 9    show various alternate embodiments of trenches filled with light absorbing material, amongst other features, and respective fabrication processes in accordance with additional aspects of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The present disclosure relates to semiconductor structures and, more particularly, to a photonic chip security structure and methods of manufacture. In embodiments, the photonic chip security structure includes a semiconductor absorption and scattering material surrounding a photonics component. As used herein, the term “surrounding” may be interpreted as walls on sides of the photonics component, on sides and over the photonics component or a complete enclosure about the photonics component. As to the latter example, the enclosure may include sidewalls, a top wall and a bottom wall, as an example. The semiconductor absorption and scattering material may be a vertical wall or enclosure surrounding the photonics component which absorbs any optical hacking signal (e.g., incoming radiation). Advantageously, the vertical semiconductor absorption and scattering layer provides security for optical signals for sensitive optical parts without impacting optical performance and functionality of the photonics component. 
     More specifically, the semiconductor absorption and scattering layer may be a vertical wall that surrounds an optical component, e.g., optical photonic waveguides or other critical optical components. The vertical semiconductor absorption and scattering material (e.g., vertical wall) may surround the optical component on either or both sides of the optical component in order to absorb and/or scatter incoming radiation (e.g., to absorb any optical hacking signal). For example, the semiconductor absorption and scattering material may be a vertical wall comprising polyGermanium (polyGe) or polySilicon (polySi) or polySiGe, any of which may absorb incoming radiation. In embodiments, the vertical wall may also include lateral projections which are structured to scatter incoming radiation. The semiconductor absorption and scattering material can also include a top layer and, in embodiments, a bottom layer, to form a security box around the optical component. The optical component may be front end of the line Si components or a back end of the line dielectric waveguide components, amongst other optical components. 
     The photonic chip security structure composed of the semiconductor absorption and scattering layer of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the photonic chip security structure of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the photonic chip security structure uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask. 
       FIG.  1    shows an optical component, amongst other features, and respective fabrication processes in accordance with aspects of the present disclosure. More specifically, the structure  10  includes a substrate  12  and dielectric stack of materials  14  with one or more electronic component  16  and an optical component  18 . In embodiments, the electronic components  16  may be any passive or active device including, e.g., transistors with contacts and metal wiring layers, etc. The optical component  18  may be any optical component such as, e.g., a waveguide or other photonic devices amongst many different examples. 
     The substrate  12  is preferably a semiconductor-on-insulator (SOI) substrate. For example, the substrate  12  includes a semiconductor handle substrate  12   a , an insulator layer  12   b  and a semiconductor layer  12   c . In embodiments, the semiconductor handle substrate  12   a  and semiconductor layer  12   c  may be composed of any suitable material including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. The semiconductor layer  12   c  may also comprise any suitable crystallographic orientation (e.g., a (100), (110), (111), or (001) crystallographic orientation). The insulator layer  12   b  may include a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, boron nitride or a combination thereof and, preferably, a buried oxide layer (BOX) supported on the semiconductor handle substrate  12   a.    
     Still referring to  FIG.  1   , the dielectric stack of materials  14  may comprise alternating layers of dielectric material  14   a ,  14   b . For example, the dielectric stack of materials  14  may include alternating layers of oxide material  14   a  and nitride material  14   b . In more specific embodiments, the oxide material  14   a  may include SiO 2  and the nitride material  14   b  may include SiN. The alternating layers of dielectric material  14   a ,  14   b  may be deposited by conventional deposition methods such as, e.g., chemical vapor deposition (CVD). 
     In  FIG.  2   , trenches  20  are formed through the dielectric stack  14 . In more specific embodiments, the trenches  20  are formed through the dielectric stack of materials  14  on sides of the optical component  18 . In this layout scheme, the optical component  18  may be a front end of the line Si optical component; although, it is also contemplated that the optical component  18  may be a back end of the line SiN optical component within the dielectric stack of materials  14 . 
     The trenches  20  can be formed by conventional lithography and etching methods known to those of skill in the art. For example, a resist formed over the dielectric stack of materials  14  is exposed to energy (light) to form a pattern (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), will be used to transfer the pattern from the resist layer to the dielectric stack of materials  14  to form one or more trenches  20  in the dielectric stack of materials  14 . In embodiments, the trenches  20  will extend to the buried insulator layer  12   b ; however, it is also contemplated that the trenches  20  can extend into the insulator layer  12   b.    
     As shown in  FIG.  3   , an additional etching process may be performed to form lateral projections  20   a  on opposing sides of the trenches  20 . In embodiments, the additional etching process may be a hot phosphorous etch which selectively attacks the exposed alternating dielectric layers  14   b  within the trenches  20 , providing a pull back of these layers  14   b  starting from the trenches  20 . In this way, the lateral projections  20   a  are formed in the alternating dielectric layers  14   b , e.g., between the layers  14   a.    
     As shown in  FIG.  4   , light absorbing material  24  may be formed within the trenches  20  and lateral projections  20   a  to form the photonic chip security structure. In this way, the photonic chip security structure includes a vertical wall of the light absorbing material  24  which surrounds the optical component  18 , e.g., photonic waveguides or functional optical devices. In embodiments, the vertical wall of the light absorbing material  24  may be polyGe material or polySi material or polySiGe material, as examples. The light absorbing material  24  may be deposited using, for example, CVD processes. Any residual material on the surface of the dielectric stack of materials  14  may be removed by conventional chemical mechanical polishing (CMP) processes. 
     In embodiments, the Ge content in the SiGe material is preferably greater than 25%; although other percentage contents may be used depending on the desired absorption rate of incoming radiation. In further embodiments, the polysilicon material can be used for shorter wavelengths of incoming radiation. In any scenario described herein, the polyGe material or polySi material or polySiGe material provides absorption properties of the incoming radiation; whereas the material within the lateral projections  20   a  provides a scattering effect of the incoming radiation. 
       FIG.  5    shows an alternative photonic chip security structure  10   a . In this embodiment, the photonic chip security structure  10   a  includes a top layer of light absorbing material  26  connected to the vertical walls of the light absorbing material  24 . In this way, an enclosure is formed around (e.g., surrounding) the optical component  18  from sides and a top. In embodiments, the light absorbing material  26  can be the same material as the light absorbing material  24 . In alternative embodiments, the light absorbing material  24  can be a different material than the light absorbing material  24 . For example, the light absorbing material  26  may be polyGe and the light absorbing material  24  may be polySi. The present disclosure also contemplates other combinations of the polyGe material or polySi material or polySiGe material. 
       FIG.  6    shows another embodiment of the photonic chip security structure  10   b . In this embodiment, the photonic chip security structure  10   b  includes vertical walls of the light absorbing material  24   a  extending into the buried insulator layer  12   b . The remaining features are similar to that described in  FIG.  4   . 
       FIG.  7    shows an embodiment of the photonic chip security structure  10   c  with lateral projections  20   a ,  20   b ,  20   c ,  20   d  of different lengths (and/or sizes) within the different alternating layers  14   b  . . .  14   n  of the dielectric stack of materials  14 . Although  FIG.  7    shows that the lateral projections  20   a ,  20   b ,  20   c ,  20   d  become progressively smaller and narrower in width from top to bottom, the present disclosure contemplates any arrangement of different lengths within the different alternating layers  14   b  . . .  14   n . In this embodiment, different thicknesses of the alternating layers  14   b  . . .  14   n  of the dielectric stack of materials  14  are used, with the use of the thicker layers resulting in a longer and wider lateral projection. For example, the longer and wider lateral projections are formed in the thicker layers due to the fact that more etchants can reach further into the layers as they become thicker. The remaining features are similar to that described in  FIG.  4   . 
       FIG.  8    shows another embodiment of the photonic chip security structure  10   d . In this embodiment, the lateral projections  20   a  are devoid of any light absorbing material. In this way, the lateral projections  20   a  can be airgaps on opposing sides of the vertical wall of light absorbing material  24 . The airgaps may be formed by using a non-conformal deposition method which results in a pinch-off phenomenon as is known in the art. The remaining features are similar to that described in  FIG.  4   . 
     In  FIG.  9   , an embodiment of the photonic chip security structure  10   e  includes a back end of the line SiN optical component within the dielectric stack of materials  14  and which is completely surrounded by vertical sidewalls of the light absorbing material  24 , in addition to a top wall of light absorbing material  26  and a bottom wall of light absorbing material  28 . As in the previous embodiments, the vertical walls  24 , top wall  26  and bottom wall  28  may be fabricated using conventional lithography, etching and deposition methods as described herein. In addition, any combination of light absorbing material may be used in the vertical walls  24 , top wall  26  and bottom wall  28 . For example, the light absorbing material in the top wall  26  and bottom wall  28  can be the same material or different material as the light absorbing material in the vertical wall  24 . In alternative embodiments, the light absorbing material  24  can be a different material in the top wall  26  and bottom  28 , etc. The remaining features are similar to that described in  FIG.  4   . 
     The semiconductor absorption and scattering layer can be utilized in system on chip (SoC) technology. The SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as in Smartphones) and edge computing markets. SoC is also used in embedded systems and the Internet of Things. 
     The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections and buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
     The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.