Patent Publication Number: US-2022223702-A1

Title: Method for manufacturing an integrated circuit device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation application based on pending application Ser. No. 16/404,857, filed May 7, 2019. the entire contents of which is hereby incorporated by reference. 
     Korean Patent Application No. 10-2018-0087280, filed on Jul. 26, 2018, in the Korean Intellectual Property Office, and entitled: “Integrated Circuit Device,” is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     1. Field 
     Embodiments relate to an integrated circuit device. 
     2. Description of the Related Art 
     As electronic technology has been developed, integrated circuit devices have been rapidly down-scaled. 
     SUMMARY 
     The embodiments may be realized by providing an integrated circuit device including a substrate having a device active region; a fin-type active region protruding from the substrate on the device active region; a gate line intersecting the fin-type active region and covering a top surface and both side walls of the fin-type active region; a gate insulating capping layer covering a top surface of the gate line; source/drain regions at sides of the gate line on the fin-type active region; a pair of first conductive plugs respectively connected to the source/drain regions; a hard mask layer covering a top surface of each first conductive plug of the pair of first conductive plugs; and a second conductive plug between the first conductive plugs of the pair of first conductive plugs, the second conductive plug being connected to the gate line by passing through the gate insulating capping layer and having a top surface at a level that is higher than a level of the top surface of each first conductive plug of the pair of first conductive plugs, wherein the hard mask layer protrudes from the top surface of each first conductive plug of the pair of first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the top surface of each first conductive plug of the pair of first conductive plugs. 
     The embodiments may be realized by providing an integrated circuit device including a substrate having a device active region; a fin-type active region protruding from the substrate on the device active region; a gate line intersecting the fin-type active region and covering a top surface and both side walls of the fin-type active region; source/drain regions at sides of the gate line on the fin-type active region; a pair of first conductive plugs respectively connected to the source/drain regions; a hard mask layer including a cover mask layer covering a top surface of each first conductive plug of the pair of first conductive plugs and a cover spacer covering a side surface of the cover mask layer and overhanging from an edge of the top surface of each first conductive plug of the pair of first conductive plugs; a second conductive plug between the first conductive plugs of the pair of first conductive plugs, the second conductive plug being connected to the gate line and having a top surface at a level that is higher than a level of the top surface of each first conductive plug of the pair of first conductive plugs; wherein the hard mask layer protrudes toward the second conductive plug, and a side wall insulating capping layer under the cover spacer and between the pair of first conductive plugs and the second conductive plug. 
     The embodiments may be realized by providing an integrated circuit device including a substrate having a device active region; a fin-type active region protruding from the substrate on the device active region; a gate line intersecting the fin-type active region and covering a top surface and both side walls of the fin-type active region; source/drain regions at sides of the gate line on the fin-type active region; a pair of first conductive plugs respectively connected to the source/drain regions; a pair of hard mask layers respectively covering top surfaces of the pair of first conductive plugs and protruding from the top surfaces of the pair of first conductive plugs; a second conductive plug between the first conductive plugs of the pair of first conductive plugs and the pair of hard mask layers covering the pair of first conductive plugs and connected to the gate line, wherein the pair of hard mask layers protrude toward the second conductive plug; and via contacts passing through the pair of hard mask layers and connected to the pair of first conductive plugs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features will be apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which: 
         FIG. 1  illustrates a planar layout diagram of an integrated circuit device according to embodiments; 
         FIGS. 2A and 2B  illustrate cross-sectional views of an integrated circuit device according to an embodiment; 
         FIGS. 3A through 3Q  illustrate cross-sectional views of stages in a method of manufacturing an integrated circuit device in a process order, according to an embodiment; 
         FIG. 4A  illustrates a cross-sectional view of a stage in a method of manufacturing an integrated circuit device, according to an embodiment; 
         FIG. 4B  illustrates a cross-sectional view of an integrated circuit device according to an embodiment; 
         FIG. 5A  illustrates a cross-sectional view of a stage in a method of manufacturing an integrated circuit device, according to an embodiment; 
         FIG. 5B  illustrates a cross-sectional view of an integrated circuit device according to an embodiment; 
         FIG. 6A  illustrates a cross-sectional view of a stage in a method of manufacturing an integrated circuit device, according to an embodiment; 
         FIG. 6B  illustrates a cross-sectional view of an integrated circuit device according to an embodiment; 
         FIG. 7A  illustrates a cross-sectional view of a stage in a method of manufacturing an integrated circuit device, according to an embodiment; 
         FIG. 7B  illustrates a cross-sectional view of an integrated circuit device according to an embodiment; 
         FIGS. 8A and 8B  illustrate cross-sectional views of stages in a method of manufacturing an integrated circuit device in a process order, according to an embodiment; 
         FIG. 8C  illustrates a cross-sectional view of an integrated circuit device according to an embodiment; and 
         FIG. 9  illustrates a cross-sectional view of an integrated circuit device according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  illustrates a planar layout diagram of an integrated circuit device  1  according to embodiments. 
     Referring to  FIG. 1 , the integrated circuit device  1  may include a fin field-effect transistor (FinFET) device. The FinFET device may constitute a logic cell. The logic cell may be configured in various ways to include a plurality of circuit elements such as a transistor and a register. The logic cell may constitute, e.g., an AND, a NAND, an OR, a NOR, an XOR (exclusive OR), an XNOR (exclusive NOR), an INV (inverter), an ADD (adder), a BUF (buffer), a DLY (delay), an FIL (filter), a multiplexer (MXT/MXIT), an OAI (OR/AND/INVERTER), an AO (AND/OR), an AOI (AND/OR/INVERTER), a D flip-flop, a reset flip-flop, (master-slaver flip-flop), and a latch, and may constitute a standard cell for performing a desired logic function such as a counter or a buffer. 
     In the integrated circuit device  1 , a plurality of fin-type active regions FA may protrude in a device active region AC. The plurality of fin-type active regions FA may extend parallel to one another in a first direction (e.g., an X direction). 
     A plurality of gate lines GL may extend in a second direction (e.g., a Y direction) intersecting the plurality of fin-type active regions FA. 
     A plurality of MOS transistors may be formed along the plurality of gate lines GL on the device active region AC. The plurality of MOS transistors may be MOS transistors having a three-dimensional (3D) structure in which channels are formed on a top surface and both side walls of each of the plurality of fin-type active regions FA. 
     A plurality of first conductive plugs CP 1  may be formed on the plurality of fin-type active regions FA. The plurality of first conductive plugs CP 1  may extend to cross the plurality of fin-type active regions FA. For example, the plurality of first conductive plugs CP 1  may extend in the second direction (e.g., the Y direction). The plurality of first conductive plugs CP 1  may be connected to a plurality of source/drain regions  120  (see  FIG. 2A ). In  FIG. 1 , the first conductive plugs CP 1  are formed on three fin-type active regions FA to cross the three fin-type active regions FA in the Y direction. 
     The integrated circuit device  1  may include a plurality of via contacts VC that are conductive and are connected to the plurality of first conductive plugs CP 1 . 
     The integrated circuit device  1  may include a second conductive plug CP 2  connected to at least one of the plurality of gate lines GL. In an implementation, the second conductive plug CP 2  may be connected to one gate line GL from among the plurality of gate lines GL in  FIG. 1 . In an implementation, the second conductive plugs CP 2  may be connected to remaining gate lines GL from among the plurality of gate lines GL. 
     The plurality of first conductive plugs CP 1  and the second conductive plug CP 2  may be located in the device active region AC. The second conductive plug CP 2  may be located between one pair of first conductive plugs CP 1 . 
       FIGS. 2A and 2B  illustrate cross-sectional views of an integrated circuit device  100  according to an embodiment. For example,  FIG. 2A  illustrates a cross-sectional view of the integrated circuit device  100  taken along lines X 1 -X 1 ′ and X 2 -X 2 ′ of  FIG. 1 .  FIG. 2B  illustrates a cross-sectional view of the integrated circuit device  100  taken along line Y-Y′ of  FIG. 1 . 
     Referring to  FIGS. 2A and 2B , the integrated circuit device  100  may include a substrate  110  having the device active region AC, and the plurality of fin-type active regions FA protruding from the substrate  110  in the device active region AC. The substrate  110  may have a main surface  110 M extending in a horizontal direction (e.g., an X-Y planar direction). The substrate  110  may include a semiconductor such as silicon (Si) or germanium (Ge) or a compound semiconductor such as SiGe, SiC, GaAs, or InP. The substrate  110  may include a conductive region, e.g., an impurity-doped well or an impurity-doped structure. 
     The plurality of fin-type active regions FA may extend parallel to one another in the first direction (e.g., the X direction). A device isolation film  112  may be formed between the fin-type active regions FA on the device active region AC. The plurality of fin-type active regions FA may upwardly protrude beyond (e.g., above) the device isolation film  112  to have fin shapes. 
     The device isolation film  112  may be, e.g., a silicon oxide film. In an implementation, the device isolation film  112  may include a first insulating liner, a second insulating liner, and a buried insulating film sequentially stacked on the substrate  110 . 
     A plurality of gate lines GL may be located on the substrate  110  and may extend in the second direction (e.g., the Y direction) that intersects the plurality of fin-type active regions FA. The plurality of gate lines GL may have the same width in the first direction (e.g., the X direction) and may be arranged at constant pitches in the first direction (e.g., the X direction). Gate insulating films  142  may be located between the plurality of gate lines GL and the plurality of fin-type active regions FA. Each of the gate insulating films  142  may cover a bottom surface and both side walls of each of the plurality of gate lines GL. 
     The plurality of gate lines GL may cover top surfaces and both side walls of the plurality of fin-type active regions FA and a top surface of the device isolation film  112 . A plurality of MOS transistors may be formed along a plurality of gate lines GL in the device active region AC. The plurality of MOS transistors may be MOS transistors having a 3D structure in which channels are formed on the top surface and both side walls of each of the plurality of fin-type active regions FA. 
     The plurality of gate insulating films  142  may include a silicon oxide film, a high-k film, or a combination thereof. The high-k film may be formed of a material having a dielectric constant that is higher than that of a silicon oxide film. For example, the plurality of gate insulating films  142  may have a dielectric constant ranging from about 10 to about 25. The high-k film may be formed of metal oxide or metal oxynitride. In an implementation, the high-k film may be formed of, e.g., hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, or a combination thereof. An interface film may be located between the fin-type active region FA and the gate insulating films  142 . The interface film may include an oxide film, a nitride film, or an oxynitride film. 
     The plurality of gate lines GL may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-fill metal film are sequentially stacked. The metal nitride layer and the metal layer may include at least one metal, e.g., titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), or hafnium (Hf). The gap-fill metal film may include a tungsten (W) film or an aluminum (Al) film. Each of the plurality of gate lines GL may include a work function metal-containing layer. The work function metal-containing layer may include at least one metal, e.g., titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), or palladium (Pd). In an implementation, each of the plurality of gate lines GL may include, e.g., a TiAlC/TiN/W stacked structure, a TiN/TaN/TiAlC/TiN/W stacked structure, or a TiN/TaN/TiN/TiAlC/TiN/W stacked structure. 
     Gate insulating spacers  132  may be located on both side walls of each of the plurality of gate lines GL. The gate insulating spacers  132  may cover both side walls of each of the plurality of gate lines GL. The gate insulating spacers  132  may extend parallel to the gate lines GL in the second direction (e.g., the Y direction) that is a longitudinal direction of the gate lines GL. The gate insulating spacers  132  may include a silicon nitride film, a SiOCN film, a SiCN film, or a combination thereof. In an implementation, the plurality of gate insulating spacers  132  may include a material film, e.g., a SiOCN film, a SiCN film, or a combination thereof, having a dielectric constant that is lower than that of a silicon nitride film. In an implementation, the gate insulating films  142  may be located between the gate lines GL and the gate insulating spacers  132  and may extend in a third direction (e.g., a Z direction) that is perpendicular to the main surface  110 M of the substrate  110 . 
     A top surface of each of the plurality of gate lines GL may be covered by a gate insulating capping layer  150 . A plurality of the gate insulating capping layers  150  may include a silicon nitride film. The plurality of gate insulating capping layers  150  may perpendicularly overlap the gate lines GL and the gate insulating spacers  132  and extend parallel to the gate lines GL. 
     One pair of source/drain regions  120  may be formed at both sides of each of the plurality of gate lines GL on the plurality of fin-type active regions FA. The gate line GL and the source/drain regions  120  may be spaced apart from each other with the gate insulating film  142  and the gate insulating spacers  132  therebetween. The plurality of source/drain regions  120  may include an impurity ion-implanted region formed in a part of the fin-type active region FA, a semiconductor epitaxial layer epitaxially grown from a plurality of recess regions R 1  formed in the fin-type active region FA, or a combination thereof. The plurality of source/drain regions  120  may include a Si layer that is epitaxially grown, a SiC layer that is epitaxially grown, or a plurality of SiGe layers that are epitaxially grown. When a transistor formed on the plurality of fin-type active regions FA is an NMOS transistor, the plurality of source/drain regions  120  may include a Si layer that is epitaxially grown or a SiC layer that is epitaxially grown, and may include N-type impurities. When a transistor formed on the plurality of fin-type active regions FA is a PMOS transistor, the plurality of source/drain regions  120  may include a SiGe layer that is epitaxially grown and may include P-type impurities. 
     Some of the plurality of source/drain regions  120  may be covered by an inter-gate insulating film  134 . The inter-gate insulating film  134  may include a silicon oxide film. 
     An upper insulating layer  160  may cover the inter-gate insulating film  134  and the gate insulating capping layer  150 . The upper insulating layer  160  may include a silicon oxide film. For example, the upper insulating layer  160  may include a tetraethyl orthosilicate (TEOS) film or an ultra low-k (ULK) film having an ultra low dielectric constant ranging from about 2.2 to about 2.4. The ULK film may include a SiOC film or a SiCOH film. 
     The plurality of first conductive plugs CP 1  connected to the plurality of source/drain regions  120  may be formed on the plurality of fin-type active regions FA. The plurality of first conductive plugs CP 1  may extend to cross the plurality of fin-type active regions FA. Each of the plurality of first conductive plugs CP 1  may include a first conductive barrier layer  212  and a first conductive core layer  214 . The first conductive barrier layer  212  may cover a side surface and a bottom surface of the first conductive core layer  214  to surround the first conductive core layer  214 . In an implementation, the first conductive barrier layer  212  may be formed of, e.g., Ti, Ta, TiN, TaN, or a combination thereof, and the first conductive core layer  214  may be formed of, e.g., Co, W, or a combination thereof. 
     In an implementation, a silicide layer may be located between the first conductive barrier layer  212  and each of the source/drain regions  120 . The silicide layer may include, e.g., tungsten silicide (WSi), titanium silicide (TiSi), cobalt silicide (CoSi), or nickel silicide (NiSi). 
     A first level LV 1  that is a level of a top surface of each of the first conductive plugs CP 1  on the first fin-type active region FA may be higher than a level of a top surface of each of the gate lines GL and may be lower than a second level LV 2  that is a level of a top surface of the upper insulating layer  160 . For example, the level may refer to a distance from the main surface  110 M of the substrate  110 . For example, when a surface is described as being at a same level as another surface, the surfaces may be coplanar. 
     In an implementation, each of the plurality of first conductive plugs CP 1  may have a stepped portion CP 1 S at an interface between the upper insulating layer  160  and the gate insulating capping layer  150  so that a width of a portion of the first conductive plug CP 1  in the upper insulating layer  160  is greater than a width of a portion of the first conductive plug CP 1  in the gate insulating capping layer  150 . 
     In an implementation, a first side cover layer  172  and a second side cover layer  174   a  may cover a side surface of the first conductive plug CP 1 . The first side cover layer  172  may cover a side surface of a lower portion of the first conductive plug CP 1  from a level of a bottom surface of the first conductive plug CP 1  to a level of a top surface of the gate insulating capping layer  150 . The second side cover layer  174   a  may cover a side surface of an upper portion of the first conductive plug CP 1  from a level of a bottom surface of the upper insulating layer  160  to a level of a top surface thereof. For example, the first side cover layer  172  may be located between the first conductive plug CP 1 , the gate insulating spacers  132 , and the gate insulating capping layer  150 , and the second side cover layer  174   a  may be located between the first conductive plug CP 1  and the upper insulating layer  160 . A level of an uppermost end of the second side cover layer  174   a  may be at the first level LV 1  (that is the level of the top surface of the first conductive plug CP 1 ). In an implementation, the first side cover layer  172  and the second side cover layer  174   a  may be spaced apart from each other. 
     A hard mask layer HM may be located on the first conductive plug CP 1 . The hard mask layer HM may protrude or extend (e.g., upwardly) from the top surface of the first conductive plug CP 1  and (e.g., laterally) toward the second conductive plug CP 2 . For example, a portion of the hard mask layer HM may overhang from the top surface of the first conductive plug CP 1  (e.g., may extend laterally outwardly beyond an outer edge of the first conductive plug CP 1 ). The hard mask layer HM may include a cover mask layer  222  covering the top surface of the first conductive plug CP 1  and a cover spacer  242  covering a side surface of the cover mask layer  222 . The cover mask layer  222  may cover top surfaces of the first conductive plug CP 1  and the second side cover layer  174   a , and the cover spacer  242  may not overlap the first conductive plug CP 1  and the second side cover layer  174   a  in the third direction (e.g., the Z direction) perpendicular to the main surface  110 M of the substrate  110 . For example, the cover spacer  242  may be a portion of the hard mask layer HM that laterally protrudes (e.g., from the top surface of the first conductive plug CP 1 ) toward the second conductive plug CP 2  and overhangs from the top surface of the first conductive plug CP 1 . 
     A level of a top surface of the hard mask layer HM may be at the second level LV 2  (that is a level of the top surface of the upper insulating layer  160 ). 
     The hard mask layer HM may be formed of an insulating material having an etch selectivity with respect to oxide and nitride. The hard mask layer HM may be formed of a silicon carbide-based material (e.g., a silicon carbide material). For example, the hard mask layer HM may be formed of SiC, SiOCN, SiCN, or a combination thereof. In an implementation, the hard mask layer HM may be formed of a doped silicon carbide material. For example, the hard mask layer HM may include a doped SiOCN film, a doped SiCN film, or a combination thereof. For example, the hard mask layer HM may include boron (B), silicon (Si), carbon (C), nitrogen (N), arsenic (As), phosphorus (P), oxygen (O), fluorine (F), argon (Ar), germanium (Ge), hydrogen (H), or helium (He) as a dopant. 
     The cover mask layer  222  and the cover spacer  242  may be formed of the same material, e.g., silicon carbide materials having the same carbon content. In an implementation, the cover mask layer  222  and the cover spacer  242  may be formed of silicon carbide materials having different carbon contents. 
     The integrated circuit device  100  may include the via contact VC that passes through the hard mask layer HM and is connected to the first conductive plug CP 1 . The via contact VC may include a conductive via barrier layer  262  and a conductive via core layer  264 . The conductive via barrier layer  262  may cover a side surface and a bottom surface of the conductive via core layer  264  to surround the conductive via core layer  264 . The conductive via barrier layer  262  may be formed of Ti, Ta, TiN, TaN, or a combination thereof, and the conductive via core layer  264  may be formed of W or Cu. 
     In an implementation, a level of a top surface of the via contact VC may be at the second level LV 2  (that is a level of the top surface of the hard mask layer HM). In an implementation, when the via contact VC is formed by using a dual damascene process, the via contact VC may be integrally formed with a wiring line located on the upper insulating layer  160 , and a level of a bottom surface of the wiring line may be the second level LV 2 . 
     The integrated circuit device  100  may include the second conductive plug CP 2  connected to at least one of the plurality of gate lines GL. The second conductive plug CP 2  may include a second conductive barrier layer  252  and a second conductive core layer  254 . The second conductive barrier layer  252  may cover a side surface and a bottom surface of the second conductive core layer  254  to surround the second conductive core layer  254 . In an implementation, the second conductive barrier layer  252  may be formed of, e.g., Ti, Ta, TiN, TaN, or a combination thereof, and the second conductive core layer  254  may be formed of, e.g., Co, W, or a combination thereof. The second conductive plug CP 2  may pass through the upper insulating layer  160  and the gate insulating capping layer  150  and may contact the gate line GL. A level of a top surface of the second conductive plug CP 2  may be higher (e.g., farther from the main surface  110 M of the substrate  110 ) than the first level LV 1  (that is a level of the top surface of each of the plurality of first conductive plugs CP 1 ). A level of the top surface of the second conductive plug CP 2  may be at the second level LV 2  (that is a level of the top surface of the upper insulating layer  160 ). A level of the top surface of the second conductive plug CP 2  may be the same as a level of the top surface of the hard mask layer HM. 
     A first wiring  300  and a second wiring  400  may be located on the second conductive plug CP 2  and the via contact VC. In an implementation, the first wiring  300  and the second wiring  400  may extend in different horizontal directions (e.g., the X-Y planar direction). For example, the first wiring  300  and the second wiring  400  may perpendicularly intersect each other and may extend in the horizontal direction (e.g., the X-Y planar direction). The first wiring  300  may be connected to the second conductive plug CP 2  and the via contact VC. In an implementation, the second conductive plug CP 2  and the via contact VC may be electrically connected to, e.g., different first wirings  300 . In an implementation, the first wiring  300  may electrically connect the second conductive plug CP 2  and the via contact VC. 
     The first wiring  300  and the second wiring  400  may be connected to each other by a first inter-wiring plug  340  that passes through a first inter-wiring insulating layer  320  covering the first wiring  300 . In an implementation, the first inter-wiring insulating layer  320  may contact a bottom surface of the second wiring  400  and does not contact a side surface of the second wiring  400 , as illustrated in  FIGS. 2A and 2B . In an implementation, the first inter-wiring insulating layer  320  may contact both the bottom surface and the side surface of the second wiring  400 . 
     The second wiring  400  may be connected to a second inter-wiring plug  440  that passes through a second inter-wiring insulating layer  420  covering the second wiring  400 . The second inter-wiring plug  440  may electrically connect the second wiring  400  and a wiring or a conductive layer located on the second wiring  400 . 
     A side wall of the second conductive plug CP 2  may be covered by the cover spacer  242  of the hard mask layer HM, the upper insulating layer  160 , a side wall insulating capping layer  162 , and the gate insulating capping layer  150 . The gate insulating capping layer  150  may cover a side surface of a lower portion of the second conductive plug CP 2  (e.g., downward from or below a level of the top surface of the gate insulating capping layer  150 ). The side wall insulating capping layer  162  and the cover spacer  242  may cover a side surface of an upper portion of the second conductive plug CP 2  from a level of the bottom surface of the upper insulating layer  160  to a level of the top surface of the upper insulating layer  160 . 
     The side wall insulating capping layer  162  may be located under (e.g., closer to the substrate  110  than) the cover spacer  242  and may cover a portion of the side surface of the upper portion of each of the plurality of first conductive plugs CP 1 . The side wall insulating capping layer  162  may be formed of, e.g., silicon oxide. The side wall insulating capping layer  162  may be formed of the same material as that of the upper insulating layer  160 . The side wall insulating capping layer  162  may be a portion of the upper insulating layer  160 . A top surface of the side wall insulating capping layer  162  may be covered by the cover spacer  242 . 
     The second conductive plug CP 2  may be formed by using a self-aligned contact (SAC) process using the hard mask layer HM. The side wall insulating capping layer  162  may be formed when a portion  160   a  (see  FIG. 3L ) of the upper insulating layer  160  that is covered by the cover spacer  242  remains without being removed during an SAC process of forming the second conductive plug CP 2  (see  FIGS. 3L through 3N ). 
     The second level LV 2  (that is a level of the top surface of the second conductive plug CP 2 ) may be higher than the first level LV 1  (that is a level of the top surface of each of the plurality of first conductive plugs CP 1 ) on the fin-type active region FA, and the hard mask layer HM may be located on the first conductive plug CP 1 . The hard mask layer HM may include the cover spacer  242  protruding laterally toward the second conductive plug CP 2  so as not to overlap the first conductive plug CP 1  in the third direction (e.g., the Z direction) and overhanging from the top surface of the first conductive plug CP 1 , and the side surface of the upper portion of the second conductive plug CP 2  that is higher than the first level LV 1  that is a level of the top surface of the first conductive plug CP 1  may be covered by the cover spacer  242 . Also, the side wall insulating capping layer  162  may be between the first conductive plug CP 1  and the second conductive plug CP 2  and between the top surface of the gate insulating capping layer  150  and a bottom surface of the cover spacer  242 . 
     For example, the side wall insulating capping layer  162  may be formed by the cover spacer  242 , and an insulating distance in the horizontal direction (e.g., the X-Y planar direction) between the first conductive plug CP 1  and the second conductive plug CP 2  may be secured. Also, the second conductive plug CP 2  may be formed by using an SAC process using the hard mask layer HM including the cover spacer  242 , and undesired misalignment during an etching process for forming the second conductive plug CP 2  may be prevented. 
       FIGS. 3A through 3Q  illustrate cross-sectional views of stages in a method of manufacturing an integrated circuit device in a process order, according to an embodiment. For example,  FIGS. 3A through 3Q  illustrate cross-sectional views taken along lines X 1 -X 1 ′ and X 2 -X 2 ′ of  FIG. 1 . In  FIGS. 3A through 3Q , the same elements are denoted by the same reference numerals as those in  FIGS. 2A and 2B , and a detailed explanation thereof will not be given. 
     Referring to  FIG. 3A , the fin-type active region FA that upwardly protrudes in the third direction (e.g., the Z direction) from the main surface  110 M of the substrate  110  and extends in the first direction (e.g., the X direction) may be formed by etching a portion of the device active region AC of the substrate  110 . The fin-type active region FA may have a cross-sectional shape as shown in  FIG. 2B  in the second direction (e.g., the Y direction). The plurality of fin-type active regions FA may be formed on the device active region AC. 
     The device active region AC of the substrate  110  may be a region for forming a transistor having at least one conductivity type from among a PMOS transistor and an NMOS transistor. 
     The device isolation film  112  (see  FIG. 2B ) that covers both lower side walls of a portion of the fin-type active region FA may be formed on the substrate  110 . The fin-type active region FA may protrude beyond or above (e.g., farther from the substrate  110  than) a top surface of the device isolation film  112 . 
     Referring to  FIG. 3B , a plurality of dummy gate structures DGS extending to intersect the fin-type active region FA may be formed on the fin-type active region FA. 
     Each of the plurality of dummy gate structures DGS may include a dummy gate insulating film D 214 , a dummy gate line D 216 , and a dummy gate capping layer D 218  that are sequentially stacked on the fin-type active region FA. The dummy gate insulating film D 214  may include silicon oxide. The dummy gate line D 216  may include polysilicon. The dummy gate capping layer D 218  may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. 
     The gate insulating spacers  132  may be formed on both side walls of the dummy gate structure DGS. In order to form the gate insulating spacers  132 , atomic layer deposition (ALD) or chemical vapor deposition (CVD) may be performed. 
     A plurality of recess regions R 1  may be formed by etching portions of the fin-type active region FA exposed at both sides of the dummy gate structure DGS, and the plurality of source/drain regions  120  may be formed by forming semiconductor layers through epitaxial growth from the plurality of recess regions R 1 . Each of the plurality of source/drain regions  120  may have a top surface whose level is, e.g., higher than that of a top surface of the fin-type active region FA. 
     The inter-gate insulating film  134  covering the plurality of source/drain regions  120 , the plurality of dummy gate structures DGS, and the gate insulating spacers  132  may be formed. In order to form the inter-gate insulating film  134 , an insulating film covering the plurality of source/drain regions  120 , the plurality of dummy gate structures DGS, and the gate insulating spacers  132  may be formed to a sufficient thickness, and then a resultant structure including the insulating film may be planarized to expose a top surface of the dummy gate capping layer D 218 . 
     Referring to  FIG. 3C , a plurality of gate spaces GS may be formed by removing the plurality of dummy gate structures DGS from a resultant structure of  FIG. 3B . The gate insulating spacers  132 , the fin-type active region FA, and the device isolation film  112  (see  FIG. 2B ) may be exposed through the plurality of gate spaces GS. 
     A wet etching process may be performed to remove the plurality of dummy gate structures DGS. In order to perform the wet etching process, an etchant including, e.g., HNO 3 , diluted fluoric acid (DHF), NH 4 OH, tetramethyl ammonium hydroxide (TMAH), potassium hydroxide (KOH), or a combination thereof, may be used. 
     Next, the gate insulating films  142  and gate conductive layers may be formed in the plurality of gate spaces GS. Before the gate insulating films  142  are formed, a process of forming an interface film on a surface of the fin-type active region FA exposed through the plurality of gate spaces GS may be further performed. In order to form the interface film, portions of the fin-type active region FA exposed in the gate spaces GS may be oxidized. 
     The gate insulating films  142  and the gate conductive layers may be formed to fill the gate spaces GS and to cover a top surface of the inter-gate insulating film  134 . The gate insulating film  142  and the gate conductive layer may be formed by using ALD, CVD, physical vapor deposition (PVD), metal organic ALD (MOALD), or metal organic CVD (MOCVD). 
     The plurality of gate insulating films  142  and the plurality of gate lines GL may be formed in the plurality of gate spaces GS by removing unnecessary portions of the gate insulating films  142  and the gate conductive layers to expose the top surface of the inter-gate insulating film  134 . 
     Referring to  FIG. 3D , a plurality of first recess spaces RS 1  may be formed over or on the gate lines GL by removing upper portions of the plurality of gate lines GL, the plurality of gate insulating films  142 , and the plurality of gate insulating spacers  132 . A width of the plurality of first recess spaces RS 1  may be limited by the inter-gate insulating film  134 . 
     In an etching process for forming the first recess space RS 1 , an etch rate of each of the gate line GL and the gate insulating spacers  132  may be controlled so that a level of a top surface of the gate insulating spacers  132  is higher than a level of a top surface of the gate line GL exposed in the first recess space RS 1 . A height of the gate insulating spacers  132  in the first recess space RS 1  may increase away from the gate line GL. A bottom surface of the first recess space RS 1  may have a round cross-sectional profile having a lowest level at the gate line GL. 
     When the gate insulating spacers  132  include a material film, e.g., a SiOCN film, a SiCN film, or a combination thereof, having a dielectric constant that is lower than that of a silicon nitride film, an undesired parasitic capacitance between the gate line GL and a conductive structure formed adjacent to the gate line GL in a subsequent process, e.g., the first conductive plug CP 1  (see  FIG. 3H ), may be suppressed by covering both side walls of the gate line GL to a sufficient height by using the gate insulating spacers  132  formed of a low-k material. 
     Next, the gate insulating capping layer  150  filling the first recess space RS 1  may be formed. The gate insulating capping layer  150  may be formed by forming a capping material layer to fill the inside of the first recess space RS 1  and cover the top surface of the inter-gate insulating film  134  and then removing an unnecessary or selected portion of the capping material layer to expose the top surface of the inter-gate insulating film  134 . The gate insulating capping layer  150  may include, e.g., a silicon nitride film. 
     Referring to  FIG. 3E , the upper insulating layer  160  covering the inter-gate insulating film  134  and the gate insulating capping layer  150  is formed, and a plurality of first contact holes CH 1  each passing through the upper insulating layer  160 , the inter-gate insulating film  134 , and the gate insulating capping layer  150  and exposing the plurality of source/drain regions  120  are formed. In a process of forming each of the plurality of first contact holes CH 1 , although a portion of the gate insulating spacers  132  may also be removed, the gate insulating film  142  and the gate line GL in the plurality of first contact holes CH 1  may not be exposed. The upper insulating layer  160  may include a silicon oxide film. For example, the upper insulating layer  160  may include a TEOS film, or a ULK film having an ultra-low dielectric constant ranging from about 2.2 to about 2.4. The ULK film may include a SiOC film or a SiCOH film. 
     In an implementation, in an etching process for forming the plurality of first contact holes CH 1 , an etch rate of the upper insulating layer  160  may be higher than an etch rate of the gate insulating capping layer  150 . In this case, each of the plurality of first contact holes CH 1  may be formed so that a width of a portion of the first contact hole CH 1  formed in the upper insulating layer  160  is greater than a width of a portion of the first contact hole CH 1  formed in the gate insulating capping layer  150 , and may have a stepped portion at an interface between the upper insulating layer  160  and the gate insulating capping layer  150 . 
     A cover layer conformably covering a top surface of the upper insulating layer  160  and an inner surface and a bottom surface of each of the plurality of first contact holes CH 1  may be formed, and the first side cover layer  172  covering surfaces of the gate insulating spacers  132  and the gate insulating capping layer  150  from among inner surfaces of each of the plurality of first contact holes CH 1  and a second side cover layer  174  covering a surface of the upper insulating layer  160  may be formed by performing anisotropic etching on the cover layer. When each of the plurality of first contact holes CH 1  has a stepped portion at an interface between the upper insulating layer  160  and the gate insulating capping layer  150 , the first side cover layer  172  and the second side cover layer  174  may be spaced apart from each other or otherwise discontinuous. The cover layer may be formed of, e.g., silicon nitride. 
     Referring to  FIG. 3G , the first conductive barrier layer  212  and the first conductive core layer  214  may be formed in each of the plurality of first contact holes CH 1 . The first conductive barrier layer  212  and the first conductive core layer  214  may be formed to fill the inside of the first contact hole CH 1  and cover the top surface of the upper insulating layer  160 . The first conductive barrier layer  212  may be formed of Ti, Ta, TiN, TaN, or a combination thereof, and the first conductive core layer  214  may be formed of Co, W, or a combination thereof. 
     Referring to  FIG. 3H , the plurality of first conductive plugs CP 1  filling lower portions of the plurality of first contact holes CH 1  and each including the first conductive barrier layer  212  and the first conductive core layer  214  may be formed by removing unnecessary or selected portions of the first conductive barrier layer  212  and the first conductive core layer  214  so that the top surface of the upper insulating layer  160  is exposed and a plurality of second recess spaces RS 2  are formed in upper portions of the plurality of first contact holes CH 1  (see  FIG. 3F ). 
     A level of each of top surfaces of the plurality of first conductive plugs CP 1  may be at the first level LV 1  (that is lower than a level of the top surface of the upper insulating layer  160 ). 
     In a process of forming each of the plurality of first conductive plugs CP 1 , a portion of the second side cover layer  174  that is higher than the first level LV 1  of  FIG. 3G  may also be removed. Accordingly, the second side cover layer  174   a  may cover a side surface of the first conductive plug CP 1 , and a level of an uppermost end of the second side cover layer  174   a  may be at the first level LV 1  that is a level of the top surface of the first conductive plug CP 1 . 
     Referring to  FIG. 3I , a mask layer  220  filling each of the second recess spaces RS 2  may be formed on a resultant structure of  FIG. 3H . The mask layer  220  may be formed to fill the inside of the second recess space RS 2  and cover the top surface of the upper insulating layer  160 . The mask layer  220  may be formed of a silicon carbide material. For example, the mask layer  220  may be formed of SiC, SiOCN, SiCN, or a combination thereof. 
     Referring to  FIG. 3J , a cover mask layer  222  may be formed by removing an upper portion of the upper insulating layer  160  and an upper portion of the mask layer  220  from a resultant structure of  FIG. 3I . In order to form the cover mask layer  222 , the upper portion of the upper insulating layer  160  and the upper portion of the mask layer  220  may be removed by using chemical mechanical polishing (CMP). The cover mask layer  222  may cover the top surface of the first conductive plug CP 1 . 
     Referring to  FIG. 3K , a protective insulating layer  180  covering the upper insulating layer  160  and the cover mask layer  222  may be formed. The protective insulating layer  180  may include a silicon oxide film. For example, the protective insulating layer  180  may include a TEOS film. A mask pattern M 1  having an opening OP may be formed on the protective insulating layer  180 . The opening OP may expose portions of the protective insulating layer  180  corresponding to the second conductive plug CP 2  and an upper portion of the cover mask layer  222  adjacent to the second conductive plug CP 2  of  FIG. 2A . 
     Referring to  FIG. 3L , a third recess space RS 3  (through which the portion  160   a  of the upper insulating layer  160  is exposed) may be formed in a bottom surface by removing portions of the protective insulating layer  180  and the upper insulating layer  160  by using the mask pattern M 1  and the cover mask layer  222  as etch masks. 
     A level of a top surface of the portion  160   a  of the upper insulating layer  160  exposed at a bottom surface of the third recess space RS 3  may be at the first level LV 1  (that is a level of the top surface of each of the plurality of first conductive plugs CP 1 ). 
     Referring to  FIG. 3M , a preliminary spacer layer covering a top surface of the protective insulating layer  180  and an inner surface and the bottom surface of the third recess space RS 3  may be formed, and then the cover spacer  242  covering a side surface of the cover mask layer  222  and a residual spacer  244  covering a side surface of the protective insulating layer  180  in the third recess space RS 3  may be formed by performing anisotropic etching on the preliminary spacer layer and removing a portion of the preliminary spacer layer formed on the top surface of the portion  160   a  of the upper insulating layer  160  exposed in the third recess space RS 3 . In an implementation, the preliminary spacer layer may be formed of the same material as that of the cover mask layer  222 . For example, the preliminary spacer layer may be formed of a silicon carbide material having the same carbon content as that of the cover mask layer  222 . 
     Referring to  FIG. 3N , a second contact hole CH 2  that communicates with or is open to the third recess space RS 3  and exposes the gate line GL may be formed by performing an etching process on a resultant structure of  FIG. 3M  by using the cover mask layer  222  and the cover spacer  242  as etch masks. The second contact hole CH 2  may pass through the portion  160   a  of the upper insulating layer  160  and the gate insulating capping layer  150  and may expose the gate line GL at a bottom surface thereof. 
     In an etching process of forming the second contact hole CH 2 , a portion of the portion  160   a  of the upper insulating layer  160  under the cover spacer  242  may not be removed and may remain as the side wall insulating capping layer  162  covering a side surface of an upper portion of the first conductive plug CP 1 . 
     The gate insulating spacers  132 , the gate insulating capping layer  150 , and the side wall insulating capping layer  162  may be sequentially formed on an inner space of the second contact hole CH 2 . Also, a side surface of the first conductive plug CP 1  may be sequentially covered by the gate insulating spacers  132 , the gate insulating capping layer  150 , and the side wall insulating capping layer  162 . 
     Accordingly, the second contact hole CH 2  may be formed by using an SAC process using the cover mask layer  222  and the cover spacer  242 , and the side wall insulating capping layer  162  remaining due to the cover spacer  242  during an etching process for forming the second contact hole CH 2  may cover the side wall of the first conductive plug CP 1 , and may prevent the first conductive plug CP 1  from being exposed in the second contact hole CH 2 . 
     Referring to  FIG. 3O , the second conductive barrier layer  252  and the second conductive core layer  254  filling the second contact hole CH 2  and the third recess space RS 3  may be formed on a resultant structure of  FIG. 3N . The second conductive barrier layer  252  and the second conductive core layer  254  may be formed to fill the insides of the second contact hole CH 2  and the third recess space RS 3  and cover the top surface of the upper insulating layer  160 . The second conductive barrier layer  252  may be formed of Ti, Ta, TiN, TaN, or a combination thereof, and the second conductive core layer  254  may be formed of Co, W, or a combination thereof. 
     Referring to  FIG. 3P , the second conductive plug CP 2  filling the second contact hole CH 2  (see  FIG. 3N ), including the second conductive barrier layer  252  and the second conductive core layer  254 , and having a bottom surface connected to the gate line GL may be formed by removing unnecessary or selected portions of the second conductive barrier layer  252  and the second conductive core layer  254  to expose a top surface of the cover mask layer  222 . 
     A level of a top surface of the second conductive plug CP 2  may be higher than the first level LV 1  (that is a level of the top surface of the first conductive plug CP 1 ). A level of the top surface of the second conductive plug CP 2  may be at a level of the top surface of the cover mask layer  222 , e.g., at the second level LV 2  (that is a level of the top surface of the upper insulating layer  160 ). 
     The cover mask layer  222  and the cover spacer  242  may be formed of the same material and may constitute the hard mask layer HM. 
     Referring to  FIG. 3Q , the plurality of via contacts VC that are conductive and are connected to the plurality of first conductive plugs CP 1  may be formed by passing through the cover mask layer  222 . 
     Next, as shown in  FIGS. 2A and 2B , the integrated circuit device  100  may be formed by forming the first wiring  300 , the first inter-wiring insulating layer  320 , the first inter-wiring plug  340 , the second wiring  400 , the second inter-wiring insulating layer  420 , and the second inter-wiring plug  440 . 
       FIG. 4A  illustrates a cross-sectional view of a stage in a method of manufacturing an integrated circuit device, according to an embodiment.  FIG. 4B  illustrates a cross-sectional view of an integrated circuit device  100   a , according to an embodiment. For example,  FIGS. 4A and 4B  illustrate cross-sectional views taken along lines X 1 -X 1 ′ and X 2 -X 2 ′ of  FIG. 1 . 
     Referring to  FIG. 4A , a second contact hole CH 2   a  communicating with the third recess space RS 3  and exposing the gate line GL may be formed by performing an etching process on a resultant structure of  FIG. 3M  by using the cover mask layer  222  and the cover spacer  242  as etch masks. The second contact hole CH 2   a  may pass through the portion  160   a  (see  FIG. 3M ) of the upper insulating layer  160  and the gate insulating capping layer  150  and may expose the gate line GL at a bottom surface thereof. 
     In an etching process of forming the second contact hole CH 2   a , a region of the portion  160   a  of the upper insulating layer  160  located under the cover spacer  242  may not be removed and may remain as a side wall insulating capping layer  162   a  covering a side surface of an upper portion of the first conductive plug CP 1 . 
     In an etching process for forming the second contact hole CH 2   a , when an etch rate of the upper insulating layer  160  is higher than an etch rate of the gate insulating capping layer  150 , a width of the side wall insulating capping layer  162   a  in the horizontal direction (e.g., the X-Y planar direction) may be less than a width of the side wall insulating capping layer  162  of  FIG. 3N . In this case, the second contact hole CH 2   a  may outwardly extend toward the side wall insulating capping layer  162   a.    
     Accordingly, a portion of a bottom surface of the cover spacer  242  may contact a top surface of the side wall insulating capping layer  162   a , a remaining portion of the bottom surface of the cover spacer  242  may not contact the top surface of the side wall insulating capping layer  162   a , and the cover spacer  242  may be shaped so that a portion of the cover spacer  242  protrudes from the cover mask layer  222  toward the second contact hole CH 2   a  beyond the side wall insulating capping layer  162   a  and overhangs from the side wall insulating capping layer  162   a.    
     Referring to  FIG. 4B , the integrated circuit device  100   a  may be formed on a resultant structure of  FIG. 4A  by forming the second conductive plug CP 2   a  filling the second contact hole CH 2   a  by performing a process similar to that of  FIGS. 3O through 3Q . The second conductive plug CP 2   a  may include a second conductive barrier layer  252   a  and a second conductive core layer  254   a . The second conductive plug CP 2   a  may have a projection CP 2 P protruding (e.g., laterally) toward the side wall insulating capping layer  162   a.    
     The integrated circuit device  100   a  of  FIG. 4B  is the same as the integrated circuit device  100  of  FIGS. 2A and 2B  except that a width of the side wall insulating capping layer  162   a  in the horizontal direction (e.g., the X-Y planar direction) is less than a width of the side wall insulating capping layer  162  and the second conductive plug CP 2   a  outwardly protrudes toward the side wall insulating capping layer  162   a , and thus a detailed explanation thereof will not be given. 
     A portion of the bottom surface of the cover spacer  242  may contact the top surface of the side wall insulating capping layer  162   a , and a remaining portion of the bottom surface of the cover spacer  242  may contact a portion of the second conductive plug CP 2   a  outwardly protruding toward the side wall insulating capping layer  162   a.    
       FIG. 5A  illustrates a cross-sectional view of a stage in a method of manufacturing an integrated circuit device, according to an embodiment.  FIG. 5B  illustrates a cross-sectional view of an integrated circuit device  100   b , according to an embodiment. For example,  FIGS. 5A and 5B  illustrate cross-sectional views taken along lines X 1 -X 1 ′ and X 2 -X 2 ′ of  FIG. 1 . 
     Referring to  FIG. 5A , a third recess space RS 3   a  exposing a portion  160   b  of the upper insulating layer  160  at a bottom surface thereof may be formed on a resultant structure of  FIG. 3K  by removing portions of the protective insulating layer  180  and the upper insulating layer  160  by using the mask pattern M 1  and the cover mask layer  222  as etch masks. 
     A level of a top surface of the portion  160   b  of the upper insulating layer  160  exposed at the bottom surface of the third recess space RS 3   a  may be higher than the first level LV 1  that is a level of a top surface of each of the plurality of first conductive plugs CP 1 . 
     Referring to  FIG. 5B , the integrated circuit device  100   b  may be formed on a resultant structure of  FIG. 5A  by forming a second conductive plug CP by performing a process similar to that of  FIGS. 3M through 3Q . 
     The integrated circuit device  100   b  may include a hard mask layer HMb including the cover mask layer  222  and a cover spacer  242   b  covering a side surface of the cover mask layer  222 . A bottom surface of the cover spacer  242   b  may have or be at a level that is higher than that of a bottom surface of the cover mask layer  222 . A portion of the upper insulating layer  160  located under the cover spacer  242   b  may be a side wall insulating capping layer  162   b  surrounding a side surface of an upper portion of the first conductive plug CP 1  and a side surface of a lower portion of the cover mask layer  222 . 
     For example, each of the bottom surface of the cover spacer  242   b  and a top surface of the side wall insulating capping layer  162   b  may have or be at a level that is higher than the first level LV 1  (that is a level of the top surface of the first conductive plug CP 1 ). 
     The integrated circuit device  100   b  of  FIG. 5B  is the same as the integrated circuit device  100  of  FIGS. 2A and 2B  except that the side wall insulating capping layer  162   b  further extends in the third direction (e.g., the Z direction) perpendicular to the main surface  110 M of the substrate  110  and covers the side surface of the lower portion of the cover mask layer  222 , and thus a detailed explanation thereof will not be given. 
       FIG. 6A  illustrates a cross-sectional view of a stage in a method of manufacturing an integrated circuit device, according to an embodiment.  FIG. 6B  illustrates a cross-sectional view of an integrated circuit device  100   c  according to an embodiment. For example,  FIGS. 6A and 6B  illustrate cross-sectional views taken along lines X 1 -X 1 ′ and X 2 -X 2 ′ of  FIG. 1 . 
     Referring to  FIG. 6A , a third recess space RS 3   b  exposing a portion  160   c  of the upper insulating layer  160  at a bottom surface may be formed on a resultant structure of  FIG. 3K  by removing portions of the protective insulating layer  180  and the upper insulating layer  160  by using the mask pattern M 1  and the cover mask layer  222  as etch masks. 
     A level of a top surface of the portion  160   c  of the upper insulating layer  160  exposed at the bottom surface of the third recess space RS 3   b  may be lower than the first level LV 1  (that is a level of a top surface of each of the plurality of first conductive plugs CP 1 ). 
     Referring to  FIG. 6B , the integrated circuit device  100   c  may be formed on a resultant structure of  FIG. 6A  by forming a second conductive plug CP by performing a process similar to that of  FIGS. 3M through 3Q . 
     The integrated circuit device  100   c  may include a hard mask layer HMc including the cover mask layer  222  and a cover spacer  242   c  covering a side surface of the cover mask layer  222 . The cover spacer  242   c  may protrude toward the substrate  110  beyond or below a bottom surface of the cover mask layer  222 . A portion of the cover spacer  242   c  protruding toward the substrate  110  beyond the bottom surface of the cover mask layer  222  may cover a side surface of an upper portion of the first conductive plug CP 1 . A portion of the upper insulating layer  160  located under the cover spacer  242   c  may be a side wall insulating capping layer  162   c  covering a side surface adjacent to the upper portion of the first conductive plug CP 1 . 
     For example, each of a bottom surface of the cover spacer  242   c  and a top surface of the side wall insulating capping layer  162   c  may have or be at a level lower than the first level LV 1  (that is a level of the top surface of the first conductive plug CP 1 ). 
     Accordingly, a side surface of the first conductive plug CP 1  may be covered by a portion of the cover spacer  242   c , the side wall insulating capping layer  162   c , the gate insulating capping layer  150 , and the gate insulating spacers  132  along a lower end from an upper end. 
     The integrated circuit device  100   c  of  FIG. 6B  is the same as the integrated circuit device  100  of  FIGS. 2A and 2B  except that the cover spacer  242   c  may further protrude toward the substrate  110  and may cover the side surface of the upper portion of the first conductive plug CP 1  and the side wall insulating capping layer  162   c  has a height that is less than that of the side wall insulating capping layer  162  by a height of a portion of the cover spacer  242   c  protruding toward the substrate  110  beyond the bottom surface of the cover mask layer  222 , and thus a detailed explanation thereof will not be given. 
     Accordingly, the hard mask layer HMc including the cover mask layer  222  and the cover spacer  242   c  covering the side surface of the cover mask layer  222  may cover both the top surface of the first conductive plug CP 1  and the side surface of the upper portion of the first conductive plug CP 1 . 
       FIG. 7A  illustrates a cross-sectional view of a stage in a method of manufacturing an integrated circuit device, according to an embodiment.  FIG. 7B  illustrates a cross-sectional view of an integrated circuit device  100   d  according to an embodiment. For example,  FIGS. 7A and 7B  illustrate cross-sectional views taken along lines X 1 -X 1 ′ and X 2 -X 2 ′ of  FIG. 1 . 
     Referring to  FIG. 7A , an auxiliary spacer  272  and an auxiliary residual spacer  274  respectively covering an inner surface of the second contact hole CH 2  and an inner surface of the third recess space RS 3  may be formed on a resultant structure of  FIG. 3N . 
     The auxiliary spacer  272  may cover a side surface of the cover spacer  242 , a side surface of the side wall insulating capping layer  162 , and a side surface of the gate insulating capping layer  150  in the second contact hole CH 2 . The auxiliary residual spacer  274  may cover a side surface of a residual spacer  244 . 
     Each of the auxiliary spacer  272  and the auxiliary residual spacer  274  may be formed by forming a preliminary auxiliary spacer layer conformably covering an exposed surface of a resultant structure of  FIG. 3N  and performing anisotropic etching. 
     Each of the auxiliary spacer  272  and the auxiliary residual spacer  274  may be formed of, e.g., silicon nitride or a silicon carbide material. 
     Referring to  FIG. 7B , the integrated circuit device  100   d  may be formed on a resultant structure of  FIG. 7A  by forming the second conductive plug CP 2  by performing a process similar to that of  FIGS. 3O through 3Q . In the integrated circuit device  100   d , a side surface of the second conductive plug CP 2  may be covered by the auxiliary spacer  272 . 
     The integrated circuit device  100   d  of  FIG. 7B  is the same as the integrated circuit device  100  of  FIGS. 2A and 2B  except that the auxiliary spacer  272  covering the side surface of the second conductive plug CP 2  is further included, and thus a detailed explanation thereof will not be given. 
     The auxiliary spacer  272  may be between the side surface of the second conductive plug CP 2  and the side surface of the cover spacer  242 , the side surface of the side wall insulating capping layer  162 , and the side surface of the gate insulating capping layer  150  covering a side surface of the second conductive plug CP 2 , and may help prevent a short circuit between the first conductive plug CP 1  and the second conductive plug CP 2 . 
       FIGS. 8A and 8B  illustrate cross-sectional views of stages in a method of manufacturing an integrated circuit device in a process order, according to an embodiment.  FIG. 8C  illustrates a cross-sectional view of an integrated circuit device  100   e  according to an embodiment.  FIGS. 8A through 8C  illustrate cross-sectional views taken along lines X 1 -X 1 ′ and X 2 -X 2 ′ of  FIG. 1 . 
     Referring to  FIG. 8A , the plurality of first conductive plugs CP 1  filling lower portions of the plurality of first contact holes CH 1  and each including the first conductive barrier layer  212  and the first conductive core layer  214  may be formed on a resultant structure of  FIG. 3G  by removing unnecessary or selected portions of the first conductive barrier layer  212  and the first conductive core layer  214  so that a top surface of the upper insulating layer  160  is exposed and a plurality of second recess spaces RS 2   a  are formed in upper portions of the plurality of first contact holes CH 1  (see  FIG. 3F ). 
     In a process of forming the plurality of first conductive plugs CP 1 , a portion of the second side cover layer  174  that has or is at a level higher than the first level LV 1  may not be removed and may remain on inner surfaces of the second recess space RS 2   a . In an implementation, a width of the portion of the second side cover layer  174  having a level higher than the first level LV 1  in the horizontal direction (e.g., the X-Y direction) may be less than a width of a portion of the second side cover layer  174  in the horizontal direction (e.g., the X-Y direction) having a level lower than the first level LV 1 . 
     Referring to  FIG. 8B , the cover mask layer  222  covering a top surface of the first conductive plug CP 1  may be formed by using a process similar to that of  FIGS. 31  through  3 J. A second side cover layer  174   b  may cover both a side surface of the first conductive plug CP 1  and a side surface of the cover mask layer  222 . 
     Referring to  FIG. 8C , the integrated circuit device  100   e  may be formed by performing a process similar to that of  FIGS. 3K through 3Q . 
     The integrated circuit device  100   e  of  FIG. 8C  is the same as the integrated circuit device  100  of  FIGS. 2A and 2B  except that the second side cover layer  174   b  upwardly extends from the side surface of the first conductive plug CP 1  beyond the first level LV 1  in the vertical direction (e.g., the Z direction) to cover the side surface of the cover mask layer  222 , and thus a detailed explanation thereof will not be given. 
     A hard mask layer HMe may include the cover mask layer  222  and the cover spacer  242 . A portion of the second side cover layer  174   b  facing the second conductive plug CP 2  may extend from a space between the upper insulating layer  160  and the first conductive plug CP 1  to a space between the cover mask layer  222  and the cover spacer  242 . Accordingly, the cover mask layer  222  and the cover spacer  242  may face each other with the second side cover layer  174   b  therebetween. 
       FIG. 9  illustrates a cross-sectional view of an integrated circuit device  100   f  according to an embodiment.  FIG. 9  illustrates a cross-sectional view taken along lines X 1 -X 1 ′ and X 2 -X 2 ′ of  FIG. 1 . 
     Referring to  FIG. 9 , the integrated circuit device  100   f  may include the plurality of first conductive plugs CP 1  and the second conductive plug CP 2 . A hard mask layer HMf may be located on the first conductive plug CP 1 . The hard mask layer HMf may include the cover mask layer  222  covering a top surface of the first conductive plug CP 1  and a cover spacer  242   f  covering a side surface of the cover mask layer  222 . 
     The cover mask layer  222  and the cover spacer  242   f  may be formed of silicon carbide materials having different carbon contents. For example, a carbon content of a material of the cover mask layer  222  may be less than a carbon content of a material of the cover spacer  242   f.    
     By way of summation and review, in down-scaled integrated circuit devices, distances between wirings and contacts may be reduced and short circuits between the wirings and the contacts may be prevented. 
     An integrated circuit device according to the one or more embodiments may include a plurality of first conductive plugs located in a device active region and a second conductive plug located between first conductive plugs of one pair of first conductive plugs and having a top surface whose level is higher than a level of a top surface of each of the first conductive plugs. A hard mask layer protruding toward the second conductive plug and overhanging from the top surface of the first conductive plug may be located on the first conductive plug, and a side wall insulating capping layer may be located under a cover spacer that is a portion overhanging from the top surface of the first conductive plug and between the first conductive plug and the second conductive plug. 
     In the integrated circuit device according to the one or more embodiments, the second conductive plug may be formed by using an SAC process using the hard mask layer including the cover spacer, and an undesirable misalignment may be prevented during an etching process for forming the second conductive plug. Also, in the integrated circuit device according to the one or more embodiments, a horizontal insulating distance between the first conductive plug and the second conductive plug may be secured by using the side wall insulating capping layer formed by the cover spacer, and an insulation margin between the first conductive plug and the second conductive plug may be secured, thereby preventing a short circuit between the first conductive plug and the second conductive plug. 
     One or more embodiments may provide an integrated circuit device including a conductive plug connected to a transistor. 
     One or more embodiments may provide an integrated circuit device having a structure in which as the integrated circuit device is down-scaled and the area of a device region is reduced, an insulation margin between conductive plugs that are located adjacent to each other may be secured. 
     Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.