Patent Publication Number: US-2022224343-A1

Title: High Gain Detector Techniques for High Bandwidth Low Noise Phase-Locked Loops

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to U.S. Provisional Patent Application No. 63/136,245 filed Jan. 12, 2021, the entirety of which is incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     This relates to high gain phase detector techniques for a low noise feedback loop. 
     BACKGROUND 
     Low phase noise operation for phase-locked loops (PLLs) or related feedback structures is enabled by high gain phase detector (PD) techniques. A high gain PD allows low detector noise to be achieved, which is typically a key bottleneck to achieving low phase noise at low frequency offsets. 
     There are several techniques for achieving high gain PD functionality. An example is a slope-based sampling PD structure, see, for example: “A 28-nm 75-fsrms Analog Fractional-N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction,” Wanghua Wu et al, 2019. Another example is an Up/Down resistor-capacitor (RC) charging circuit that utilize a limited time range for the Up/Dn timing window, see, for example: “A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator Phase detector,” Michael H. Perrott, et al, 2010. The slope-based sampling PD structure offers high gain but suffers from process and temperature (PT) sensitivity of that gain since the slope will generally be impacted by PT variations. The Up/Dn RC charging circuits offer gain that is generally robust against PT variation but are generally more limited by supply voltage than the slope-based structure. Both approaches are sensitive to supply noise. 
     SUMMARY 
     In described examples, a PLL analog loop filter structure with high BW includes a passive feedforward path that is AC-coupled to a (lossy) integrating path containing an opamp circuit. The lossy integrating path utilizes both inverting and non-inverting gains of the opamp fed by phase detectors with opposite gain polarity to reduce impact of supply noise and opamp noise. In some examples, the structure is augmented with a frequency detector controlling a resistor or current switching in order to achieve initial phase lock. A wide range of phase detectors can be used, including high gain PD and XOR-based PD. 
     In some described examples a digital-to-time converter is utilized to reduce quantization error from delta-sigma dithering of divider so as to avoid noise folding due to nonlinearity of the high gain PD. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of an example phase locked loop (PLL). 
         FIG. 2  is an example noise model of the PLL of  FIG. 1 . 
         FIGS. 3-5  are plots of phase noise level (dBc/Hz) versus offset frequency (f) for the noise model of  FIG. 2 . 
         FIG. 6A  is a schematic and  FIG. 6B  is a timing diagram of a prior art phase detector and loop filter. 
         FIG. 7A  is a schematic and  FIG. 7B  is a timing diagram of another prior art phase detector. 
         FIG. 8A  is a schematic and  FIG. 8B  is a timing diagram of another prior art phase detector. 
         FIG. 9A  is a schematic and  FIG. 9B  is a timing diagram of an example high gain phase detector. 
         FIG. 10  is a schematic of an equivalent circuit for the phase detector of  FIG. 9A . 
         FIG. 11A  is a schematic and  FIG. 11B  is a timing diagram of an example phase to charge converter without charge pump boosting. 
         FIG. 12  is a timing diagram showing the effect of charge pump structures provided in the phase detector of  FIG. 9A . 
         FIG. 13A  is a schematic and  FIG. 13B  is a timing diagram of another example high gain phase detector. 
         FIG. 14  is a schematic diagram of an example differential high gain phase detector and loop filter. 
         FIG. 15  is a schematic of a simple XOR phase detector. 
         FIG. 16  is a schematic diagram of an example XOR differential high gain phase detector and loop filter. 
         FIG. 17  is a schematic of an example phase detector and frequency detector circuit. 
         FIG. 18  is a timing diagram illustrating operation of the example circuit of  FIG. 17 . 
         FIG. 19  is a plot illustrating phase noise in an example PLL. 
         FIG. 20  is a block diagram of an example voltage supply for a PLL. 
         FIG. 21  is a plot of noise vs frequency for the supply of  FIG. 20 . 
         FIG. 22  is a block diagram of an example feedback loop with high gain phase detector. 
         FIG. 23  is a timing diagram illustrating operation of the high gain phase detector within the feedback loop of  FIG. 22 . 
         FIG. 24  is a schematic of an example phase to digital converter for a low BW feedback loop. 
         FIG. 25  is a simulation model for the resistor switching section of  FIG. 24 . 
         FIG. 26  is a schematic of an example fully differential phase to digital converter for a low BW feedback loop. 
         FIG. 27  is a schematic of another example fully differential phase to digital converter for a low BW feedback loop. 
         FIG. 28  is a schematic of an example alternative switched resistor phase to charge converter. 
         FIG. 29  is a schematic of an example alternative switch scheme. 
         FIG. 30  is a schematic illustrating example configurability options for an example phase to digital converter. 
         FIG. 31  is a block diagram and  FIG. 32  is a timing diagram of an example circuit to generate early/late pulses. 
         FIGS. 33-36  are schematics and timing diagrams for example linear phase detectors. 
         FIGS. 37A-37E  are timing diagrams illustrating example bang-bang timing with linear phase detector timing. 
         FIG. 38  is a schematic of an example circuit to generate bang-bang signals. 
         FIG. 39  is a block diagram of an example 2 nd  order MASH delta-sigma modulator. 
         FIG. 40  is a block diagram of an example enhanced 2 nd  order MASH delta-sigma modulator. 
         FIG. 41  is an example noise model of the example enhanced delta-sigma of  FIG. 40 . 
         FIG. 42  is a plot illustrating simulation results for the enhanced delta-sigma of  FIG. 40 . 
         FIG. 43  is a block diagram of an example analog phase locked loop controlled by the feedback loop of  FIG. 22 . 
         FIG. 44  is a block diagram of the example analog phase locked loop of  FIG. 43  augmented by a digital PLL. 
         FIG. 45  is a plot illustrating phase noise level (dBc/Hz) versus offset frequency for simulated operation of example noise model of  FIG. 2 . 
         FIG. 46  is a plot illustrating phase noise level (dBc/Hz) versus offset frequency for simulated operation of example system 4300 of  FIG. 43 . 
         FIGS. 47A, 47B  are plots illustrating operation of an example bang-bang circuit. 
     
    
    
     DETAILED DESCRIPTION 
     In the drawings, like elements are denoted by like reference numerals for consistency. 
     In examples described herein, achievement of low phase noise at low offset frequencies for phase-locked loops (PLLs) or related feedback structures is enabled by high gain phase detector (PD) techniques. In particular, a high gain PD allows reduction of the impact of detector noise to be achieved, which is typically a key bottleneck to achieving low phase noise at low frequency offsets. 
     In other examples described herein, low noise PLLs or related feedback structures are greatly aided by achieving a wide bandwidth (BW) for the PLL in order to suppress voltage-controlled oscillator (VCO) noise. However, wide BW PLLs are significantly impacted by phase detector noise, and therefore must achieve low phase detector noise in order to achieve low jitter. High gain phase detector techniques allow low detector noise impact to be achieved. 
     While high gain PD techniques exist, they are generally sensitive to process and temperature (PT) variation, voltage supply noise, and/or limited supply voltage (often &lt;1.2V for core devices in advanced CMOS). PD gain variations can degrade PLL jitter performance across PT variation due to corresponding changes in the PLL bandwidth. 
     Voltage supply noise can degrade the low frequency phase noise performance. While such supply noise can be reduced with passive lowpass filtering, such filters require substantial area and may even require inclusion of undesired off-chip components such as discrete capacitors. Lower supply voltage is desired to reduce power consumption and allow use of core devices in advanced CMOS but can degrade PLL performance due to reduced PD gain. 
     There are several techniques for achieving high gain PD functionality. An example is a slope-based sampling PD structure. Another example is an Up/Down resistor-capacitor (RC) charging circuit that utilizes a limited time range for the Up/Dn timing window. The slope-based sampling PD structure offers high gain but suffers from PT sensitivity of that gain since the slope will generally be impacted by PT variations. The Up/Dn RC charging circuits offer gain that is generally robust against PT variation but are generally more limited by supply voltage than the slope-based structure. Both approaches are sensitive to supply noise. 
     In examples described herein, high gain PD techniques reduce sensitivity to supply noise by leveraging a differential structure. In another example, a technique is described for augmenting a delta-sigma modulator to reduce its low frequency quantization noise without substantially increasing high frequency quantization noise, which is useful for improving low frequency phase noise performance without incurring additional noise folding due to nonlinearity of the phase detector. In another example, a digital-to-time converter is used as an alternative for reducing the quantization noise with the benefit of enabling wider bandwidth, but comes at the cost of higher complexity, power, and area. 
     Examples described herein are based on improvements to the Up/Dn RC charging circuit approach to achieve higher PD gain and to reduce sensitivity to supply noise. A higher PD gain is achieved by leveraging charge pump techniques to increase the effective supply voltage seen by the PD during the Up/Dn charge/discharge times. 
     A lower sensitivity to supply noise is achieved through loop filter topologies that may be combined with various phase detector techniques. Single-ended and differential versions of example loop filter topologies are described herein. Some examples described herein utilize a differential structure in order to reduce sensitivity to supply noise while maintaining high gain for the PD. In some described examples, an ADC is included to digitize the differential signal. 
     In general, achievement of lower noise through brute force methods such as increased power/area encounter practical limits due power/area constraints for a product. In examples described herein, techniques to increase PD gain utilize circuit topologies that can be implemented with modest power/area requirements and enable state-of-the art jitter requirements to be met. Achievement of insensitivity to low frequency supply noise can often be achieved with external capacitors, but this is undesirable due to increased cost to the final system and difficulties in board design to avoid noise injection into the routing traces and pins associated with the external capacitors. Examples described herein use techniques for reducing supply sensitivity that avoid the need for such external capacitors. 
       FIG. 1  is a block diagram of an example phase locked loop (PLL)  100 . A voltage-controlled oscillator (VCO)  108  outputs a variable frequency signal on oscillator output node  122  that is tuned according to a control voltage  107 . Feedback is used to lock the VCO output frequency to a multiple of the reference frequency input signal  120  through the use of a multi-modulus frequency divider (MMD)  110 , phase detector (PD)  102 , and loop filter  106 . In this example, the phase detector  102  also includes frequency detection (FD) logic  104 . Phase detector  102  includes pulse generation (PG) logic  103  that produces up and down pulses whose pulse width varies with the phase difference between the reference frequency  120 , Ref, and divider (Div) output  121 . A phase to charge converter (PCC)  105  converts the up and down PD signals into pulses that are then filtered by loop filter  106  to form the control voltage  107 . PCC  105  is configured to provide a high gain for PD  102   
     Digital-to-time converter (DTC)  112  is utilized to reduce quantization error from delta-sigma modulator  114  dithering of divider  110  so as to avoid noise folding due to nonlinearity of the high gain PD  102 . In some examples, DTC  112  allows a phase adjustment. DTC  112  produces a variable delay that is determined by a digital input value provided by delta sigma  114  and MMD  110 . The frequency divide value of MMD  112  is controlled by delta sigma  114 . The output of MMD  110  serves as a clock input to delta sigma  114  and an input to DTC  112 . 
     In some examples, the divisor value of multi-modulus divider  110  may be changed dynamically. 
       FIG. 2  is an example noise model  200  of the PLL of  FIG. 1 .  FIG. 3  is a plot of raw phase noise level (dBc/Hz) versus offset frequency (f) for the noise model of  FIG. 2 .  FIG. 3  is a plot of phase noise level before filtering within PLL  100  ( FIG. 1 ).  FIG. 4  is a plot of phase noise level after filtering within PLL  100  ( FIG. 1 ). This example model includes phase detector  202 , loop filter  206 , VCO  208 , and divider  210 . KD  202  is the gain of phase detector  102 . H(s)  206  is the transfer function of loop filter  106 . (2πKv)/s  208  is the transfer function for VCO  108 . N is the divider value of divider  110 . 
     Various sources of noise contribute to degradation of loop performance, such as: phase detector noise  221 , quantization noise from the divider, DTC thermal noise and delta sigma dithering noise  223 , some residual noise that is not canceled, supply noise, etc. Supply noise affects all blocks, but especially is an issue for the phase detector and loop filter. Delta sigma modulator  114  causes noise  223  to rise to higher frequencies that can be filtered by the loop filter  206 . VCO noise  222  gets high-pass filtered by the loop, but some low frequency noise gets through. Phase detector  202  is low pass filtered by the loop filter  206  but some high frequency noise gets through. 
     As illustrated in  FIG. 4 , after filtering by PLL  100 , detector noise  421  dominates at low frequency offsets relative to the PLL bandwidth indicated at  301 . VCO noise  422  dominates at high frequency offsets. DTC and DS noise  422  is reduced due to filtering by the PLL. 
     Referring to  FIG. 2 , expression (1) quantifies the transfer function relationship from detector noise to the output signal on output terminal  122 . For the case where s is much less than PLL bandwidth (BW), expression (1) can be simplified to expression (2). 
     
       
         
           
             
               
                 
                   
                     
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     Thus, detector noise  421  is approximately equal to N/K D , therefore, maximizing detector gain K D  results in minimizing the impact of detector noise on output  122 . 
       FIG. 5  illustrates noise folding that may occur if DTC  112  (see  FIG. 1 ) is not included in PLL  100 . Without DTC  112 , nonlinearity in phase detector  102  leads to noise folding of delta sigma noise  423 , as indicated at  523 . Such noise folding is avoided by the use of DTC  112  which reduces the impact of dithering by delta sigma modulator  114  (see  FIG. 1 ) on phase error. 
       FIG. 6A  is a schematic of a prior art phase detector  601  and loop filter  602  for use in a feedback structure such as a phase locked loop. Phase detector  601  generates an up-pulse signal  624  and a down-pulse signal  625  whose widths are a function of phase difference between reference frequency signal  620  and feedback divided signal  621 , as illustrated in  FIG. 6B . 
     Charge pump  626  is turned on in response to up pulse signal  624  and charge pump  627  is turned on in response to down pulse signal  625 . Charge pumps  626 ,  627  are added to allow up or down control of the VCO tuning voltage formed on node  628 . Expression (3) represents the loop filter transfer function, H(s), from output of the charge pump to the VCO tuning voltage  628 . In general, larger charge pump current, which is advantageous for improved detector noise, must be accompanied by an increase in loop filter capacitors to achieve a given PLL bandwidth. This often leads to the requirement of large physical capacitors that typically must be located off chip, which is undesirable for an integrated single chip solution. 
     
       
         
           
             
               
                 
                   
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       FIG. 7A  is a schematic of a prior art phase detector  701  and loop filter for use in a feedback structure such as a phase locked loop that does not use current sources to increase phase detector gain. Instead, the ratio of the reference signal period (Tref) to the divided feedback signal period (Tdiv) is increased. In this example, the divisor is selected so that the feedback divided signal  721  frequency is four times the frequency of the reference signal  720 . Phase detector  701  sees a phase error range over a smaller phase window and the corresponding phase detector gain is increased due to the small phase error range. In this example, there is a 4× improvement due to 4× frequency ratio. This provides a relatively stable phase detector gain since the Tref/Tdiv ratio is PVT insensitive. However, this phase detector and loop filter approach is very sensitive to supply voltage (Vdd) noise and there is some impact of noise folding for fractional-N implementations due to nonlinearity from RC charging behavior within the loop filter. 
     Phase detector  701  generates an up-pulse signal  724  and a down-pulse signal  725  whose widths are a function of phase difference between reference frequency signal  720  and feedback divided signal  721 , as illustrated in  FIG. 7B . 
     Phase detector  701  is based on an RC charging mechanism with resistor R 1  and capacitor C 1 . While up signal  724  is active capacitor C 1  is charged via resistor R 1 . While down signal  725  is active C 1  is discharged. When up or down are not present, then capacitor C 1  holds the voltage. 
       FIG. 8A  is a schematic and  FIG. 8B  is a timing diagram of another prior art switched resistor phase detector  801  and loop filter  802 . In this example, only the phase to charge module  805  of the phase detector is illustrated in detail for simplicity. Pulse generation module  803  generates the pulse signals illustrated in  FIG. 8B . In this example, a separate up-charge resistor Rup and down-charge resistor Rdn are connected to charging node  828  and charging capacitor Cdet. In this example, the phase detector includes a pulse generation circuit  803  to generate the up-pulse signal  824 , down-pulse signal  825  and gate signal  826 . 
     In this example, the divider is configured to provide a divided feedback signal  821  that has a frequency that is lower than the frequency of the reference signal  820 . As in the example of  FIG. 7A , gain of the phase detector is increased due to the ratio of Fref/Fdiv. 
     Switch  830  is controlled by gate signal  826  to only transfer charge from RC node  828  to loop filter  802  for a limited period of time. The resulting increase in phase detector gain reduces the impact of noise that is transferred from phase to charge converter  805  to loop filter  802 . 
     Phase detectors  701  ( FIG. 7A ) and  802  are described in more detail in “A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator Phase detector,” Michael H. Perrott, et al, 2010. 
     HIGH BANDWIDTH, HIGH GAIN PHASE DETECTOR EXAMPLES 
       FIG. 9A  is a schematic of a switched resistor phase detector  901  and loop filter  902 . In this example, the gain of phase detector  901  is improved with a structure that alters RC charging. Phase detector gain is limited by the supply voltage. If a larger supply voltage is used, the gain can be increased. However, process limitations limit the magnitude of the supply voltage without device problems due to overvoltage issues. In this example, the “effective” supply voltage on the RC charging circuit is raised by using a voltage boosting structure  926 ,  927  (also referred to as a “charge pump”) that augments the phase detector. To do this, capacitors Cup2 and Cdn2 are added along with inverters  926  and  927  in order to inject additional charge into capacitors Cup 1 and Cdn1 during assertion of Up and Dn signals, respectively. This injection of extra charge has a similar effect on RC charging as what would be achieved with a higher supply voltage. An extra switch  932  allows the Up and Dn network charge states to be shared after the Up and Dn charging events occur. Switches  933  and  934  pass the combined Up and Dn charge states to capacitor C 1  such that a phase error voltage signal (Vfilt) is achieved which can be further filtered before influencing the VCO control voltage Vctrl. 
     In described examples, charge pumps  926 ,  927  boost a charging voltage on boost capacitors Cup2, Cdn2, respectively in order to increase gain of the phase detector. In another example, a charge pump structure that boosts a current into a suitable element, such as an inductor, may be used to increase an effective supply voltage to increase the gain of a phase detector. 
       FIG. 9B  is a timing diagram illustrating timing signals  924 ,  925 ,  926  generated by pulse generator module  903  in response to a reference signal  920  (Ref_xN) and a feedback signal  921  (Div). The time duration of Up pulse  924  is proportional to the time between an edge of reference signal  920  and feedback signal  921 . The time duration of Dn pulse  925  is proportional to the time between an edge of reference signal  920  and feedback signal  921 . The total length of Up pulse  924  and Dn pulse  925  is constrained to be the period of the reference signal, Tspan. 
     For example, when down-pulse  925  becomes asserted and switch  931  is closed, the output of inverter  927  will transition to a high voltage state and thereby charge capacitor Cdn2 through resistor Rdn to ground via Vdn RC node  937  and also share charge with capacitor Cdn1. Then, when up-pulse  924  is asserted and switch  930  is closed, the output of inverter  926  will become low and thereby charge capacitor Cup2 through resistor Rup from Vreg via Vup RC node  936  and also share charge with capacitor Cup1. Then, when up-pulse  924  and down-pulse  925  are de-asserted and switches  930 ,  931  are open, gate pulse  926  is activated to close switches  932 ,  933  and  934  and thereby couple the RC nodes  936 ,  937  to filter capacitor C 1  at phase error output node  928   
     In this example, only the phase to charge converter  905  of the phase detector  901  is illustrated in detail for simplicity. Pulse generation module  903  generates the pulse signals illustrated in  FIG. 9B . Pulse generation circuit  903  generates the up-pulse signal  924 , down-pulse signal  925  and gate signal  926 . In this example, down-pulse signal  925  is enabled only from the rising edge of ref signal  920  to the rising edge of divide signal  921 , and the up-pulse signal  924  is enabled only from the rising edge of divide signal  921  to the rising edge of ref signal  920 . In this manner, up-pulse signal  924  and down pulse signal  925  are non-overlapping and have a total active time that is equivalent the period (Tspan) of ref signal  920 . 
     In this example, the divider is configured to provide a divided feedback signal  921  that has a frequency that is lower than the frequency of the reference signal  920 . Gain of the phase detector is increased due to the ratio of Fref/Fdiv. 
     Switches  933 ,  934  are controlled by gate signal  926  to transfer charge from RC nodes  936 ,  937  to output node  928  for a limited period while gate signal  926  is active. This prevents the phase error voltage Vfilt as well as the VCO control voltage Vctrl from being disturbed by the RC charging activity during enablement of Up and Dn pulses. 
     Up-pulse  924  and down-pulse  925  are enabled while the gate switches  932 ,  933 ,  934  are off. Phase detector gain is improved by an alpha factor, which is a ratio of the caps as given by expression (4). equation. Expression (5) represents the total gain factor of phase detector  901  assuming capacitors Cup1 and Cdn1 are equal in value and that capacitors Cup2 and Cdn2 are also equal in value. 
     
       
         
           
             
               
                 
                   
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     In some examples, multiple capacitors may be provided that may be selectively switched off using switches, a multiplexor, or other known or later developed technique to dynamically change the gain of the system by varying the capacitor ratio alpha to optimize the gain. If one considers only minimization of the impact of detector noise, alpha should be selected to be as high as possible. However, other considerations such as implementation area, achievable switching speed of inverters  926  and  927  with capacitive loading, and impact on supply may impact the optimal setting of alpha. 
       FIG. 10  is a schematic of an equivalent circuit  1005  for the phase to charge converter  905  for the phase detector  901  of  FIG. 9A . As described for  FIG. 9A , charge pump structures  926 ,  927  and Cup2, Cdn2 produce an effect equivalent to raising the supply voltage. In this example, the result is the same as if the supply voltage is raised by an amount equal to α det  times one half the supply voltage and the ground voltage is lowered by an amount equal to α det  times one half the supply voltage. In this example, the supply voltage for phase detector  901  is a regulated voltage Vreg. In other examples, the supply voltage for the phase detector may be the chip wide supply voltage Vdd or another different voltage source. In this example, the use of charge pump structures  926 ,  927  and Cup2, Cdn2 allows an effective increase in phase detector gain as determined by the capacitor ratio α det . 
       FIG. 11A  is a schematic and  FIG. 11B  is a timing diagram of an example phase to charge converter (PCC)  1105  that is similar to PCC  905  ( FIG. 9A ) without charge pump structures  926 ,  927 . In this example without gain boosting charge pumps, discharge at Vup node  1136  during up-pulse  924  and discharge at Vdn node  1137  during down-pulse  925  starts at approximately Vreg/2 for both the up and down path. A resulting Vfilt signal is formed on output node  1128 . 
       FIG. 12  is a timing diagram of example PCC  905  showing the effect of charge pump structures  926 ,  927  and Cup2, Cdn2. In this example, gain boosting is achieved by increasing the initial voltage across the Rup, Rdn resistors during the enable times of up-pulse  924  and down-pulse  925  as indicated on Vup  936  and Vdn  937  at  1242 ,  1243  respectively. This results in a larger change in the amplitude of Vfilt  928  for a given change in phase error. Thus, PCC  905  with charge pump structures  926 ,  927  and Cup2, Cdn2 has a higher gain than PCC  1105  without charge pump structures. 
       FIG. 13A  is a schematic of another example high gain phase to charge converter (PCC)  1305  that is similar to PCC  905  ( FIG. 9A ). In this example, gate  932  is controlled by gate0 signal  13260 , while gates  933 ,  934  are controlled by an offset gate1 signal  13261 . 
       FIG. 13B  is a timing diagram illustrating timing signals  924 ,  925 ,  13260 ,  13261  generated by a pulse generator module similar to PG  903  ( FIG. 9A ) in response to a reference signal  920  (Ref_xN) and a feedback signal  921  (Div). Gate0 signal  13260  is offset from gate1 signal  13261  by a small amount so that gate  932  is closed slightly before gates  933 ,  934 . This allows ripple on nodes  1336 ,  1337  to settle out prior to closing switches  933 ,  934  and thereby reduces ripple sent to filter  1302  and output Vctrl. In this example, the offset time is approximately 5%-10% of Tspan, though optimal offset time will vary according to settling behavior when switch  13260  is on as well as other constraints. Note that Gate0 signal is shown to become de-asserted before Gate1 signal, but other implementations could have Gate0 signal become de-asserted at the same time or after Gate1 signal. 
       FIG. 14  is a schematic diagram of an example differential high gain phase detector and loop filter  1400  that can be used in the example PLL  100  of  FIG. 1 . In this example, a wide band feed-forward (FF) path  1401  includes a high gain PCC cell  1410  coupled to FF filter  1412 . Lossy integrating path  1402  includes an opamp  1420  with an inverting input  1421  coupled to receive a filtered output from PCC cell  1425  and a non-inverting input  1422  coupled to receive a filtered output from PCC cell  1426 . 
     Lossy integrating path  1402  also includes a frequency detection path  1424  in which switch  1411  is configured to couple inverting input  1421  to ground through resistor Rfd lo when a signal FDlo asserts in cases where the frequency of an output signal, such as Out signal  122  ( FIG. 1 ) is too low and in which switch  1412  is configured to couple inverting input  1421  to Vreg through resistor Rfd_hi when a signal FDhi asserts in cases where the frequency of the output signal is too high. 
     FF filter  1412  combines the output  1407  of PCC cell  1410  and integrating path  1402  to produce a control signal Vctrl on output node  1414 . Control signal Vctrl is used to control a variable frequency oscillator that produces Out signal  122  ( FIG. 1 ). In another example, additional filtering may be provided for control signal Vctrl before being output on node  1414 . 
     PCC cells  1410 ,  1425 , and  1426  can be the same as PCC  905  ( FIG. 9A ), PCC  1005  ( FIG. 10 ), PCC  1105  ( FIG. 11B ), PCC  1305  ( FIG. 13A ) or another known or later developed PCC cell. However, notice that the Up signal  924  and Dn signal  925  are opposite between PCC  1425  and PVV  1426 . This allows cancellation of low frequency supply noise and use of both the inverting input  1421  and non-inverting input  1422  of opamp  1420 . In this manner, opamp  1420  noise impact is reduced by approximately 2× by leveraging both the inverting and non-inverting gain paths. 
     The DC gain of the inverting path of the opamp corresponds to the ratio of the resistor across the feedback to the input resistor −(r13/(r10+r11)), while the noninverting path has DC gain of (1+r13/(r10+r11)). In the case where the magnitude of the DC gain of the inverting path is significantly larger than 1, then the magnitude of the DC gain of the noninverting path will have similar magnitude. As such, any common-mode signals such as supply noise in high gain PD cells  1425  and  1426  will be largely cancelled out. For example, if the DC gain of inverting path has magnitude of 10, then the DC gain of the noninverting path has magnitude of 1+10=11. In this case, supply noise will be attenuated by approximately 90% assuming the supply noise has the same effect on both high gain PD cells  1425  and  1426 . Thus, good supply noise cancellation is provided in a single ended system (as opposed to a differential two output system) which is convenient for doing analog control of a VCO since a VCO typically has a single ended control input. 
     This example provides the benefit of supply noise cancellation of low frequencies, and effectively gets more gain out of the opamp. If just the inverting terminal is used, then gain is 10 (in this example), however, in this case there is the gain of −10 on the inverting input and 11 on the noninverting, then the total gain of the lossy integrating path is effectively doubled in comparison with value of 21. As such, the opamp output provides double the phase error signal compared to just using either the inverting or noninverting path. This is important because the noise from the opamp is gained up by the noninverting path gain so that doubling the gain of the phase error signal relative to the noninverting path leads to roughly 2× improvement in Signal-to-Noise ratio at the opamp output. In effect, the opamp noise impact is reduced by about a factor of two. Therefore, this example provides the benefit of cancelation of low frequency supply noise by the integrating path and the benefit of reduced impact of opamp noise in the system. 
     In this example, each PCC cell  1410 ,  1425 ,  1426  is operated on a 1.1V regulated voltage Vreg. In another example, a different supply voltage may be used. Each PCC cell  1410 ,  1425 ,  1426  and associated filter network can be optimized independently. 
     In this example, integrating path  1402  is described as being “lossy” integrator. To avoid saturation problems, feedback capacitor C 13  is shunted by a feedback resistance R 13 . The parallel combination of C 13  and R 13  behave like a practical capacitor which dissipates power, unlike an ideal capacitor. For this reason, a practical integrator is referred to as a lossy integrator. In another example, the amount of loss contributed by R 13  may be selected based on other parameters to control saturation. 
       FIG. 15  is a schematic of a simple XOR phase detector cell  1500 . In this example, a reference signal  1520  and a divided feedback signal  1521  are connected to inputs of XOR gate  1501 . Feedback signal  1521  is like feedback signal  121  ( FIG. 1 ) for PLL  100  ( FIG. 1 ). Inverting buffer  1504  provides buffered phase detect signal Vpdb  1507 . Inverting buffer  1505  provides on opposite phase detect signal Vpd  1506 . 
       FIG. 16  is a schematic diagram of an example XOR differential high gain phase detector  1600  that uses simple XOR PD cells of  FIG. 15  in place of PCC cells. This structure is useful when a high frequency reference signal, such as Ref  1520 , is available. A way to increase PD gain is to decrease the time range that it takes to achieve a given voltage error signal from the PD after filtering, which is the case when operating frequency of the PD is increased. A typical reference frequency is less than a few hundred MHz, however, in this example the reference oscillator runs at 2.5 GHz, while the VCO runs at multi-GHz. Since the reference frequency is very high, then don&#39;t need a PCC configuration where the reference frequency and the feedback divided signal are multiples of each other and can instead use a simple XOR type PD, such as PD  1500  ( FIG. 15 ). In this example, the PD gain does not need to be increased; instead, a simple implementation is desired in order to allow robust operation at very high frequency. Due to the avoidance of narrow output pulses during steady-state operation, XOR PD provides a very linear behavior in a system where delta sigma modulation is included in the feedback loop as long as the instantaneous phase error deviation is not so large as to create very small pulses at the PD output. 
     In this example, a wide band feed-forward (FF) path  1601  includes a PD cell  1610  coupled to FF filter  1412 . Lossy integrating path  1602  includes an opamp  1420  with an inverting input  1421  coupled to receive a filtered output from PD cell  1425  and a non-inverting input  1422  coupled to receive a filtered output from PD cell  1426 . 
     Lossy integrating path  1602  also includes a frequency detection path  1424  in which switch  1411  is configured to couple inverting input  1421  to ground through resistor Rfd lo when a signal FDlo asserts in cases where the frequency of an output signal, such as Out signal  122  ( FIG. 1 ) is too low and in which switch  1412  is configured to couple inverting input  1421  to Vreg through resistor Rfd_hi when a signal FDhi asserts in cases where the frequency of the output signal is too high. 
     FF filter  1412  combines the output  1507  of PD cell  1610  and integrating path  1602  to produce a control signal Vctrl on output node  1614 . Control signal Vctrl is used to control a variable frequency oscillator that produces Out signal  122 . In another example, additional filtering may be provided for control signal Vctrl before being output on node  1414 . 
     In this example, PD cells  1410 ,  1425 , and  1426  are the same as PD cell  1500  ( FIG. 15 ), or another known or later developed PD cell. However, notice that output signal Vpd  1506  is coupled to inverting input  1421  of opamp  1420 , while the opposite polarity output signal Vpdb  1507  is coupled on non-inverting input  1422 . This allows cancellation of low frequency supply noise and use of both the inverting input  1421  and non-inverting input  1422  of opamp  1420 . In this manner, opamp  1420  noise impact is reduced by approximately 2X by leveraging both the inverting and non-inverting gain paths. 
     The DC gain of the inverting path of the opamp corresponds to the ratio of the resistor across the feedback to the input resistor −(r13/(r10+r11)), while the noninverting path has DC gain of (1+r13/(r10+r11)). In the case where the magnitude of the DC gain of the inverting path is significantly larger than 1, then the magnitude of the DC gain of the noninverting path will have similar magnitude. As such, any common-mode signals such as supply noise in high gain PD cells  1425  and  1426  will be largely cancelled out. For example, if the DC gain of inverting path has magnitude of 10, then the DC gain of the noninverting path has magnitude of 1+10=11. In this case, supply noise will be attenuated by approximately 90% assuming the supply noise has the same effect on both high gain PD cells  1425  and  1426 . Thus, good supply noise cancellation is provided in a single ended system (as opposed to a differential two output system) which is convenient for doing analog control of a VCO since a VCO typically has a single ended control input. 
     This example provides the benefit of supply noise cancellation of low frequencies, and effectively gets more gain out of the opamp. If just the inverting terminal is used, then gain is 10 (in this example), however, in this case there is the gain of −10 on the inverting input and 11 on the noninverting, then the total gain of the lossy integrating path is effectively doubled in comparison with value of 21. As such, the opamp output provides double the phase error signal compared to just using either the inverting or noninverting path. This is important because the noise from the opamp is gained up by the noninverting path gain so that doubling the gain of the phase error signal relative to the noninverting path leads to roughly 2× improvement in Signal-to-Noise ratio at the opamp output. In effect, the opamp noise impact is reduced by about a factor of two. Therefore, this example provides the benefit of cancelation of low frequency supply noise by the integrating path and the benefit of reduced impact of opamp noise in the system. 
     In this example, each PD cell  1610 ,  1625 ,  1626  is operated on a 1.1V regulated voltage Vreg. In another example, a different supply voltage may be used. Each PD cell  1610 ,  1625 ,  1626  and associated filter network can be optimized independently. 
       FIG. 17  is a schematic of an example phase detector pulse generation (PG) circuit  1701 , frequency detector circuit  1702 , and bang-bang phase detector circuit  1703 . Reference frequency signal  120  and divided feedback signal  121  are provided as inputs to these circuits. PG circuit  1701  generates phase detector control signals Up  924 , Dn  925 , and Gate  926  that are used in the PCC cells described in more detail hereinabove. Frequency detector  1702  generates the FDhi and FDlo signals described hereinabove in more detail when the frequency of the oscillator output is outside of a selected range in order to achieve an initial lock of the PLL. Bang-bang PD circuit  1703  is used for DTC calibration and will be described in more detail hereinbelow. 
       FIG. 18  is a timing diagram illustrating operation of the PG portion  1701  of the example circuit of  FIG. 17 . In this example, the frequency of reference frequency signal  120  is 1.25GHz. The frequency of divided feedback signal  121  is 625MHz, such that Ref  120  has a frequency of 2× Div  121 . In another example, a larger multiple could be used, and also a higher reference frequency. The 2× difference in frequency between Ref  120  and Div  121  provides the equivalent of a 2× gain in the PD/PCC cell. Alternatively, in another example the frequency of Div  121  could be configured to be a multiple of the frequency of Ref  120 . 
     Up/Dn pulses  924 ,  925  change width in opposite manner as a function of phase error. This relationship provides high linearity even in the presence of mismatch between Up/Dn loop filter paths. This is in contrast to prior techniques in which either Up or Dn pulses changes width independently. 
       FIG. 19  is a plot of noise in dBc/Hz vs offset frequency (Hz) illustrating noise in an example PLL In this example, a PLL  100  ( FIG. 1 ) is equipped with the PCC blocks and loop filter circuit  1400  ( FIG. 14 ) using the timing circuits  1701 ,  1702  ( FIG. 17 ). In this example, the reference frequency is 1.25 GHz and the feedback frequency is 625 MHz. Low frequency noise from the regulated supply voltage (Vreg) is well suppressed as indicated by plot line  1902 . Overall noise is indicated by plot line  1901 . Overall jitter integrated from 12 kHz to 20 MHz is 46.0 fs (rms). 
     In descried examples, a method of operating a phase locked loop (PLL) is described. A first phase error signal is generated for a difference in phase between a reference signal and a feedback signal with first phase detector cell  1425  ( FIG. 14 ) having a gain polarity. A second phase error signal is generated for a difference in phase between the reference signal and the feedback signal with a second phase detector cell  1426  having an opposite gain polarity. The first phase error signal and the second phase error signal are amplified by opamp  1420  ( FIGS. 14 ) and combined the results to form an integrated phase error signal. A third phase error signal is generated for a difference in phase between the reference signal and the feedback signal with a third phase detector cell  1410  ( FIG. 14 ) to form a feed-forward phase error signal. The feed-forward phase error signal is combined with the integrated phase error signal to form a control signal Vctrl  1414  ( FIG. 14 ). 
     In described examples, a voltage-controlled oscillator (VCO)  108  ( FIG. 1 ) is operated responsive to the control signal Vctrl to generate an output signal Out  122  ( FIG. 1 ). The frequency of the output signal is continuously monitored to determine if it is outside a target frequency range. A magnitude (value and/or sign) of the integrated phase error signal Vctrl is adjusted when the frequency of the output signal is outside the target frequency range. 
     In described examples, the output of a divider  110  ( FIG. 1 ) coupled to the VCO is modulated with a delta sigma modulator. The feedback signal is delayed a varying amount responsive to the modulated output of the divider by DTC  112  ( FIG. 1 ). 
     In described examples, a first phase error signal is generated by applying a first voltage to a first resistor-capacitor Rup, Cup1 ( FIG. 9A ) for an amount of time proportional to a first phase difference to form a first RC node voltage, wherein the magnitude of the voltage is augmented by a first charge pump  926 ( FIG. 9A ). A second voltage is applied to a second resistor-capacitor Rdn, Cdn1( FIG. 9A ) for an amount of time proportional to a second phase difference to form second RC node voltage, wherein the magnitude of the voltage is augmented by a second charge pump  927  ( FIG. 9A ). The first RC node voltage and the second RC node voltage are combined to form a combined RC node voltage by closing switch  932  ( FIG. 9A ). The combined RC node voltage is transferred to a filter by switches  933 ,  934  ( FIG. 9A ). In some examples, the transfer of the combined RC node voltage to the filter is delayed for a period of time by gate signals  13260 ,  13261  ( FIG. 13B ) to allow the combined RC node voltage to stabilize. 
     LOW BANDWIDTH, HIGH GAIN PHASE DETECTOR EXAMPLES 
     In the following examples, a differential switched RC front end is used to cancel low frequency noise from a voltage regulator. A differential front end is combined with partial and fully differential loop filter and ADC (analog to digital converter). Gain of the loop filter is set high enough such that ADC noise impact is sufficiently reduced. 
     In some examples, a linear PD is augmented with a bang-bang detector and frequency detector for reasonable lock-in time. 
     In some examples, a digital Delta-Sigma modulator is augmented to reduce quantization noise at low frequencies without substantially increasing noise folding by avoiding significant increase of quantization noise spectral magnitude at high frequencies. 
       FIG. 20  is a block diagram of an example voltage supply for an example PLL. In a typical PLL system, a supply voltage  2001  is provided by a circuit, such as a bandgap circuit, that creates an accurate reference voltage Vref. While Vref provides an accurate voltage value that is reasonably consistent across PVT variations, it is often prone to being accompanied by high noise and also does not provide sufficient output current to function as the supply for various circuits within the integrated circuit including the PLL. As such, a voltage supply regulator Vreg  2003  is utilized to provide sufficient output current for the PLL and other blocks, and Vref  2001  is utilized as a reference voltage for Vreg in order to achieve an accurate voltage across PVT. The noise present in Vref is filtered  2002  before being supplied to Vreg. As such, a typical supply regulator for the PLL has an output noise spectral density noise that is highest at low frequencies due to the impact of band gap noise which is lowpass filtered. 
       FIG. 21  is an example plot of noise spectral density (V/rHz) vs frequency (Hz) for the voltage supply regulator of  FIG. 20 , illustrating the impact of Vref noise at lower frequencies. 
       FIG. 22  is a block diagram of an example feedback loop  2200  that provides a digital frequency ratio signal “OutN” on output node that is derived from comparison in phase/frequency of a high frequency bulk acoustic wave (BAW) oscillator  2201  and reference frequency Ftcxo. In particular, output signal OutN on node  2215  is the estimated instantaneous ratio of the frequency of BAW output signal  2202  and the frequency of reference signal  2204 , which in this example is provided by a temperature-controlled crystal oscillator (TCXO)  2203 . BAW resonators featuring 0  high operating frequency up to a few GHz and small size have been used for mobile applications such as filters in the RF front-end of wireless transceivers for many years. The BAW resonator is a piezoelectric thin film resonator, which operates similarly to a quartz crystal, is utilized by a BAW oscillator circuit to create a periodic oscillation signal. In this example, BAW oscillator  2204  operates at 2.5 GHz. 
     Multi-modulus divider (MMD)  2206  divides BAW frequency signal  2202  by ratio number N of feedback signal  2217  provided by digital delta sigma modulator  2216 . Div_early and div_late pulses are generated by MMD  2206 , as illustrated in  FIG. 23 . In this example, delta sigma modulator  2216  is clocked by div_late pulse  2219 . 
     Phase detector  2208  uses reference signal  2204  and div_early and div_late pulses to generate phase difference signals including up pulse  2209  and down pulse  2210  in response to the timing relationship between reference signal  2204  and the div_early and div_late pulses. 
     Phase to digital converter (P2DC)  2212  produces a digital output value  2213  responsive to up pulse  2209  and down pulse  2210 . Digital loop filter  2214  filters digital value  2213  to produce output signal OutN on node  2215 . 
     In this example, initial lock-in time is improved by a “bang-bang” (BB) loop  2220 ,  2221  that will be described in more detail hereinbelow. The BB loop augments the system with an extra phase detector when it is initially settling. The BB loop provides an error signal to drive the system. Once the system locks, the BB loop drops out in activity and does not affect noise, etc. 
     In this example, delta sigma  2216  is designed to reduce delta sigma noise impact without aggravating noise folding, as will be described in more detail hereinbelow. 
       FIG. 23  is a timing diagram illustrating timing signals generated by MMD  2206  ( FIG. 22 ) and PD  2208  ( FIG. 22 ). 
       FIG. 24  is a schematic of an example P2DC  2412  for a low BW feedback loop, such as feedback loop  2200  ( FIG. 22A ). 
     Module  2412  includes switched resistor phase to charge converters (PCC)  2425 ,  2426  that are configured in a differential manner. Each PCC  2425 ,  2426  includes two switches, such as switches  2451 ,  2452  that are controlled by Up pulse signal  2209  and Dn pulse signal  2210 , respectively. In this example, switches  2451 ,  2452  are each implemented as an FET transistor. 
     Differential loop filter  2401  includes opamp  2420 . An output from PCC  2425  is coupled to inverting input  2421  of opamp  2420  and an output from PCC  2426  is coupled to non-inverting input  2422  of opamp  2420 . Notice that signals Up  2209  and Dn  2210  received from PD  2208  ( FIG. 22A ) are reversed between PCC  2425  and  2426 . 
     Anti-alias filter  2430  attenuates frequencies above the Nyquist sampling rate of analog to digital converter (ADC)  2431  to eliminate aliasing. 
     ADC  2431  converts the amplified output from opamp  2420  into a digital value that is output on node  2215 . Such a digital value is useful for a digital phase locked loop (DPLL). 
     In this example, the differential configuration suppresses low frequency noise on the regulated supply voltage Vreg and reduces the impact of noise produced by opamp  2420 , as described in more detail for opamp  1420  ( FIG. 14 ). 
       FIG. 25  is a simulation model for the resistor switching section of  FIG. 24 , such as switching section  2426 . A value for equivalent resistor Rdet  2501  is given by expression ( 6 ), though this expression is approximate in that Rdet can be reduced by the impact of parasitic capacitance in networks  2425  and  2426  in  FIG. 24 . 
     
       
         
           
             
               
                 
                   
                     R 
                     det 
                   
                   = 
                   
                     
                       
                         
                           2 
                           ⁢ 
                           
                             T 
                             ref 
                           
                         
                         
                           T 
                           span 
                         
                       
                       ⁢ 
                       
                         R 
                         up 
                       
                     
                     || 
                     
                       R 
                       dn 
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     Block  2508 , which corresponds to the DC gain from phase error to Verror, indicates that the DC gain of phase detector  2412  is increased by the ratio of the period of reference signal  2204  ( FIG. 22 ) and the time span Tspan between the rising edges of Div_early and Div_late. 
     The DC gain of the loop filter circuit that is fed by Verror changes as a function of reference (TCXO) frequency based on expression (7), where Rdet is given by expression (6). Lower frequency for reference signal  2204  leads to increased R det  and therefore lower DC gain. Higher frequency for reference signal  2204  leads to reduced Rdet and therefore higher DC gain. 
       DC gain of loop filter=1+2*R fb /(R det +R neg )   (7)
 
     The input to ADC  2431  ( FIG. 24 ) and the output of opamp  2420  each have a limited voltage range. This leads to a tradeoff between effective phase error resolution and effective phase error range. Effective phase error range must be wide enough to accommodate jitter (including Delta-Sigma dithering). Effective phase error range is influenced by the ADC opamp voltage range, PD gain, and loop filter gain (expression (7)). 
       FIG. 26  is a schematic of an example fully differential P2DC  2600  for a low BW feedback loop, such as feedback loop  2200  ( FIG. 22 ). In this example, phase to charge converters (PCC)  2425 ,  2426  are configured in a differential manner and coupled to two separate opamps  2420 ,  2620 . 
     Differential loop filter  2601  includes opamps  2420  and  2620 . An output from PCC  2425  is coupled to inverting input  2421  of opamp  2420  and an output from PCC  2426  is coupled to non-inverting input  2422  of opamp  2420 . Similarly, an output from PCC  2425  is coupled to non-inverting input  2622  of opamp  2620  and an output from PCC  2426  is coupled to inverting input  2621  of opamp  2620 . Notice that signals Up  2209  and Dn  2210  received from PD  2208  ( FIG. 22A ) are reversed between PCC  2425  and  2426 . 
     An output  2423  from opamp  2420  and an output  2623  from opamp  2620  are coupled to inputs of differential ADC  2631 . ADC  2631  quantifies the difference in voltage appearing on signal lines  2423  and  2623  and converts it to a digital output. The output of ADC  2631  is then provided on output node  2215 . ADC  2631  may be fully differential or pseudo-differential. 
       FIG. 27  is a schematic of an example fully differential P 2 DC  2700  for a low BW feedback loop, such as feedback loop  2200  ( FIG. 22 ). In this example, phase to charge converters (PCC)  2425 ,  2426  are configured in a differential manner with differential loop filter  2701  that includes a single differential opamp  2720 . An output from PCC  2425  is coupled to inverting input  2721  of opamp  2720  and an output from PCC  2426  is coupled to non-inverting input  2722  of opamp  2720 . Opamp  2720  provides differential outputs  2723 ,  2724  that are coupled to differential ADC  2631 . ADC  2631  quantifies the difference in voltage appearing signal lines  2723  and  2724  and converts it to a digital output. The output of ADC  2631  is then provided on output node  2215 . ADC  2631  may be fully differential or pseudo-differential. 
       FIG. 28  is a schematic of an example alternative switched resistor phase to charge converter. In this example, switched PCC  2825  that has a single resistor Rdet1 can replace PCC  2425  that has two resistors Rup1 and Rdn1. Similarly, switched PCC  2826  that has a single resistor Rdet0 can replace PCC  2426  that has two resistors Rup0 and Rdn0. This alternative configuration can be used in any of the previously described systems  2412 ,  2600 , or  2700 . 
       FIG. 29  is a schematic of an example alternative switch scheme for PCC  2426 , see  FIG. 24 . A similar configuration can be used in PCC  2425  ( FIG. 24 ). In this example, a buffer  2951  is inserted between switching FET  2451  and Vreg and tracks the Up signal  2209 . In this configuration the supply voltage provided to switching transistor  2451  is provided by the output of buffer  2951 . Therefore, when Up signal  2209  is inactive, a voltage that is approximately at ground potential is provided to switch  2451 . Similarly, a buffer  2952  is inserted between switching FET  2452  and ground and inverts the Dn signal  2210 . In this configuration the supply voltage provided to switching transistor  2452  is provided by the output of buffer  2952 . Therefore, when Dn signal  2952  is inactive, a voltage that is approximately Vreg potential is provided to switch  2452 . In this manner, the off-resistance of switching circuit  2951 ,  2952  is increased significantly. The on-resistance is increased only slightly due to the resistance of buffers  2951 ,  2952 . 
       FIG. 30  is a schematic illustrating example configurability options for an example PCC  3012  that has the same overall schematic as example PCC  2412  ( FIG. 24 ). It is beneficial to keep loop filter gain high enough so that ADC  2413  quantization noise is well scrambled (i.e., so that at least several ADC codes are exercised by noise or other signals). Referring to expressions (6) and (7), loop filter gain varies with the period of the reference frequency, Tref. Therefore, it is beneficial to maintain sufficient loop filter gain as Tref varies by adjusting or trimming various resistor and capacitor values in PCC  3012  as appropriate. 
     In this example, Rup0, Rup1, Rdn0, Rdn1, Rop_p, Rneg, Rfb, Cdet0, Cdet1 and Cfb can each be individually adjusted using trimming switches and additional resistors and capacitors in appropriate configurations, such as connecting trimming components in series or in parallel. In this example, the trimming switches are controlled by a configuration register (not shown) that is set by a control processor (not shown) for the system. In another example, trimming may be controlled using known or later developed techniques, such as: fusible links, erasable programmable read only memory (EPROM) bits, etc. 
       FIG. 31  is a block diagram and  FIG. 32  is a timing diagram of an example circuit  3100  to generate early/late pulses  2218 ,  2219  in multi-modulus divider  2206  as illustrated in  FIG. 22 . Multistage divider topology  3102  provides a Div_early output pulse signal  2218  that is retimed from the Div_In feedback signal  2217  (see  FIG. 22 ). In this example, configurable shift register  3104  is utilized to accurately delay the Div_late output pulse signal  2219  by a selected number of Div_in  2217  pulses. In this manner, the length of time, Tspan, between a rising edge of Div_early  2218  and a rising edge of Div_late  2219  is accurately set. In some examples, shift register  3104  may be configured to allow Tspan to be adjusted by half cycles of Div_In feedback signal  2217 . Known or later developed techniques can be used with multiplexors and registers to control the configuration of delay register  3104  and thereby select a value for Tspan. 
       FIG. 33  is a schematic and  FIG. 34  is a timing diagram for an example linear phase detector  3300  that is included within PD  2208 , see  FIG. 22 . In this example, flip-flop  3302  receives the Div_early  2218  pulse signal on a clock input and Div_late  2219  pulse signal on a reset input. A solid “one” logic level is applied to a D input. Flip-flop  3302  generates pd_pulse signal  3303  that is coupled to inputs on gates  3304 ,  3306 . Reference signal  2204  is coupled to a second input of gate  3304  and an inverted version of reference signal  2204  is coupled to a second input of gate  3306 . And-gate  3304  generates Dn pulse signal  2210 , while and-gate  3306  generates Up pulse signal  2209 . In this example, an optional delay module  3308  is included to delay Dn pulse  2210  by a small amount so that the Up pulse and Dn pulse do not overlap. In this example, Tdelay is implemented using inverters. In another example, other types of known or later developed techniques or circuit elements may be used to produce a delay. In some examples, delay  3308  may be omitted if overlapping Up/Dn pulses are acceptable. 
       FIG. 35  is a schematic and  FIG. 36  is a timing diagram for an example linear phase detector  3500  that is included within PD  2208 , see  FIG. 22 . In this example, flip-flop  3502  receives reference signal  2204  on a clock input, a solid one logic level on a D input, and div_early on a reset input. Flip-flop  3502  generates do pulse signal  2210 . Flip-flop  3504  receives reference signal  2204  on a clock input, a solid one logic level on a D input, and div_late on a reset input. Flip-flop  3504  generates up pulse signal  2209 . In this example, an optional delay module  3508  is included to delay Dn pulse  2210  by a small amount so that the Up pulse and Dn pulse do not overlap. In this example, Tdelay is implemented using inverters. In another example, other types of known or later developed techniques or circuit elements may be used to produce a delay. In some examples, delay  3308  may be omitted if overlapping Up/Dn pulses are acceptable. 
       FIGS. 37A-37E  are timing diagrams illustrating example bang-bang (BB) timing signals generated by timing circuitry inside PD  2208  ( FIG. 22 ) along with linear phase detector signals Up and Dn. As long as the rising edge of reference signal  2204  falls within the Tspan window  3701 , which is defined by the time between a rising edge of Div_early pulse  2218  and a following rising edge of Div_late  2219 , BB late  2223  and BB early  2222  are inactive, as illustrated in  FIGS. 37B, 37C, and 37D .  FIG. 37A  illustrates an example case in which a rising edge of reference signal  2204  occurs before the Tspan window  3701 . In this case, BB early signal  2222  is activated.  FIG. 37E  illustrates an example case in which a rising edge of reference signal  2204  occurs after the Tspan window  3701 . In this case, BB late signal  2223  is activated. Thus, in this example as long as both Up signal  2209  and Dn signal  2201  are active indicating that the feedback loop  2200  ( FIG. 22 ) is in lock, BB early and BB late are inactive. Note there are cases, such as encountered with the PD circuit of  35 , that Up and Dn could have activity outside of the Tspan window without disturbing the relationship of BB early and BB late becoming inactive outside of the Tspan window. 
       FIG. 38  is a schematic of an example circuit included within PD  2208  ( FIG. 22 ) to generate bang-bang signals. As long as the rising edge of reference signal  2204  falls within the Tspan window  3701  ( FIG. 37A ), which is defined by the time between a rising edge of Div_early pulse  2218  and a following rising edge of Div_late  2219 , BB late  2223  and BB early  2222  are inactive. 
     Re-timing flip-flops  3801 ,  3802  synchronize the timing of BB_early and BB_late to the div_late clock signal  2218 , assuming sigma delta module is clocked by the div_late clock signal  2218 . Re-timing flip-flops  3803 ,  3804  synchronize the timing of BB_early and BB_late to the ADC clock signal  2226 , assuming ADC  2431  ( FIG. 24 ) or ADC  2631  ( FIG. 26 or 27 ) module is clocked by the ADC clock signal  2226 . 
     ENHANCED DIGITAL DELTA SIGMA MODULATOR 
     As described hereinabove for  FIGS. 1-5 , noise folding may occur if DTC  112  (see  FIG. 1 ) is not included in PLL  100 . Without DTC  112 , nonlinearity in phase detector  102  leads to noise folding of delta sigma noise  223 , as indicated at 523 ( FIG. 5 ). Such noise folding is avoided by the use of DTC  112  which reduces the impact of dithering by delta sigma modulator  114  (see  FIG. 1 ) on phase error. DTC  112  reduces phase variation into phase detector  102  ( FIG. 1 ) and also allows wide bandwidth operation. However, a DTC adds complexity, power consumption and area on an integrated circuit. 
     Delta-sigma (ΔΣ; or sigma-delta, ΣΔ) modulation is a method for encoding analog signals into digital signals as found in an analog-to-digital converter (ADC). It is also used to convert high bit-count digital signals with relatively low frequency content into lower bit-count, higher-frequency digital signals in which the relatively low frequency content is preserved. For example, conversion of digital signals into analog as part of a digital-to-analog converter (DAC) as well as fractional-N frequency synthesizers may utilize Delta-Sigma modulation. The delta-sigma modulation technique is known, see for example: “Delta-sigma modulation,” Wikipedia, 9 August 2021 or later. 
       FIG. 39  is a block diagram of a 2 nd  order MASH digital delta-sigma modulator  3901 . The multi-stage noise shaping (MASH) digital structure has a noise shaping property and is commonly used in digital audio and fractional-N frequency synthesizers. It includes two or more cascaded overflowing accumulators, each of which is equivalent to a first-order sigma-delta modulator. The carry outputs are combined through summations and delays to produce a binary output, the width of which depends on the number of stages (order) of the MASH. 
     RC charging of a high gain PCC, such as PCC  2212  ( FIG. 22 ), has nonlinearity that causes noise folding of delta-sigma noise produced by delta-sigma module  2216  ( FIG. 22 ). 2 nd  order MASH delta-sigma  3901  often yields acceptably low noise folding, but not sufficient noise shaping. However, a 3 rd  order delta-sigma often yields unacceptably high noise folding. 
       FIG. 40  is a block diagram of an example enhanced 2 nd  order MASH delta-sigma modulator  4001 . In this example, 2 nd  order MASH delta-sigma  3901  is enhanced with a feedback loop that uses design parameters “K” and “a.” In this example, feedback block  4009  acts as a digital lowpass filter that extracts the low frequency quantization noise so that it can suppressed through the action of feedback. The resulting feedback leads to a change in the DC gain of the closed loop system which is compensated by a cascaded gain block  4007 . 
       FIG. 41  is an example noise model of the example enhanced delta-sigma modulator  4001  of  FIG. 40 . In this example, expression (8) represents a transfer function of delta-sigma quantization noise  4010  to output node  4005 . An overall delta-sigma noise spectrum is represented by expression (9), where “n” is the MASH order of the delta-sigma. A signal transfer function from input  4003  to output  4005  is represented by expression (10). 
     
       
         
           
             
               
                 
                   
                     
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       FIG. 42  is a plot illustrating simulation results in dB/Hz vs frequency (MHz) for the enhanced delta-sigma of  FIG. 40  compared to conventional order 2 and order 3 MASH structures. Plot line  4201  represents 2 nd  order MASH delta-sigma  3901  ( FIG. 39 ). Plot line  4202  represents enhanced 2 nd  order MASH delta-sigma  4001  ( FIG. 40 ). Plot line  4203  represents a 3 rd  MASH delta-sigma (not shown). 
     In this example, K is selected to be 3 and is set to achieve lowpass bandwidth in feedback loop  4009  ( FIG. 40 ) of approximately 1/100 of the clock frequency. In this example, the high frequency noise stays about the same, but an improvement of approximately 9 dB is observed at lower frequencies. 
     PHASE LOCKED LOOP EXAMPLES 
       FIG. 43  is a block diagram of an example frequency generating system  4300  that includes high bandwidth analog phase locked loop  4301  controlled by a low bandwidth feedback loop  2200  of  FIG. 22 . High BW PLL  4301  is similar to high BW PLL  100  ( FIG. 1 ). In this example, high BW PLL  4301  is locked to reference frequency Fbaw  2202  provided by BAW oscillator  2201  that provides a high frequency and low jitter. In this example, divider  4302  divides high frequency reference signal  2202  by a factor of four for simplicity, but high gain PD techniques discussed could be applied and therefore lead to changes in the best choice of this divide value. In another example, a reference frequency may be provided by another known or later developed technique, such as a crystal-based reference oscillator. 
     In this example, low BW feedback loop  2200  is also locked to Fbaw reference frequency signal  2202  and to Ftcxo reference frequency signal  2204  provided by a temperature-controlled crystal oscillator. In another example, a reference frequency may be provided by another known or later developed technique, such as a crystal-based reference oscillator. 
     In this example, high BW PLL  4301  may include a high gain phase detector  102  as described hereinabove in more detail. In this example, low BW feedback loop  2200  may include a high gain PD  2208  as described hereinabove in more detail. 
     In this example, digital processing logic  4310  receives OutN signal  2215  from feedback loop  2200 . OutN signal  2215  provides the value of the ratio between the frequency of Fbaw reference signal  2202  and Ftcxo reference signal  2204 . Processing logic  4310  converts this ratio into a fraction value Nfrac  4311  that is provided to delta-sigma  114 . By doing so, the ppm accuracy of Fvcol can be set according to Ftcxo, and suppression of low frequency phase noise of the BAW can be achieved. 
     In this example, APLL  4301  is described. In another example, a digital PLL may be used in place of APLL  4301 . 
       FIG. 44  is a block diagram an example frequency generating system that includes the example frequency generating system  4300  of  FIG. 43  augmented by a digital PLL (DPLL)  4401 . In this example, open loop cancellation of BAW low offset phase noise is provided by TCXO feedback loop  2200  and analog PLL  4301 , as described hereinabove in more detail. 
     In this example, DPLL  4401  provides closed loop tracking to Fref  4406  to provide PPM accuracy and very low offset phase noise suppression. DPLL  4401  includes time to digital converter (TDC)  4402 , digital loop filter  4403 , multi-modulus divider  4404 , and delta-sigma  4405 . 
     In this example, APLL  4301  is described. In another example, a digital PLL may be used in place of APLL  4301 . Similarly, in this example digital PLL  4401  is described. In another example, an analog PLL may be used in place of digital PLL  4401 . 
     SIMULATIONS 
       FIG. 45  is a plot of phase noise level (dBc/Hz) versus offset frequency for simulated operation of example noise model of  FIG. 2  illustrating noise folding effects of delta-sigma noise, see  FIG. 5 . In this example, plot line  4510  represents overall phase noise at output  122  ( FIG. 1 ). In this example, the carrier frequency is 312.5 MHz, reference frequency  120  ( FIG. 2 ) is 40.0 MHz, divider  210  ( FIG. 2 ) input is 2.5 GHz, BW is 14.7 kHz. Significant degradation occurs at low frequencies due to noise folding of delta-sigma quantization noise, but total noise remains below noise targets for two example systems, as indicated at  4501 ,  4502 . 
       FIG. 46  is a plot illustrating phase noise level (dBc/Hz) versus offset frequency for simulated operation of example system  4300  of  FIG. 43 . In this example, the carrier frequency is 312.5 MHz, BAW reference frequency  2202  ( FIG. 43 ) is 40.0 MHz, divider  110  ( FIG. 43 ) input is 2.5 GHz, BW is 14.7 kHz. In this example, plot line  4610  illustrates overall phase noise appearing on output  122  ( FIG. 43 ). Plot line  4611  illustrates delta-sigma noise with folding in TCXO loop  2200  ( FIG. 43 ). Plot line  4612  illustrates BAW noise from a simulated parallel BAW oscillator  2201  ( FIG. 43 ). Plot line  4613  illustrates quantization noise for a 10-bit, 4.0 MHz ADC quantizer within TXCO loop  2200  ( FIG. 43 ). Total noise remains below noise targets for two example systems, as indicated at  4501 ,  4502 . 
       FIGS. 47A, 47B  are plots illustrating operation of an example bang-bang circuit generated by timing circuitry inside PD  2208  ( FIG. 22 ). In this example, plot line  4701  illustrates a simulated step response of a fractional ratio value  4311  ( FIG. 43 ) feed into the delta-sigma  114  ( FIG. 43 ). Prior to the step, bang-bang output signals  2222 ,  2223  ( FIG. 22 ) are quiescent, as illustrated at  4702 . After the step input, BB output signals  2222 ,  2223  are active for a small amount of time (ms) as indicated at  4703  in order to more quickly stabilize the ratio value. After a short period of time, the BB output signals  2222 ,  2223  again go quiescent, as indicated at  4704  once the ratio value has stabilized. 
     OTHER EMBODIMENTS 
     In described examples, high gain, high BW phase detectors and high gain, low BW phase detectors are presented. In described examples, these are combined in various combinations to provide variable frequency systems that produce stable frequency signals that have low noise. In another example, these components may be configured in various topologies to provide enhanced low noise system performance. 
     In this description, the term “phase detector” is used to refer to a circuit that detects a difference in phase between a reference signal and a feedback signal. In some examples, a phase detector may include a pulse generator timing circuit, such a PG circuit  1701  ( FIG. 17 ). In other examples, a phase detector may be a simple XOR gate as shown in  FIG. 15 . In some examples, a phase detector may include a “phase to charge converter” (PCC) such as PCC  905  ( FIG. 9 ). In some examples, a phase detector may include a phase to digital converter, such as phase to digital converter  2212  ( FIG. 22 ). 
     In described examples, an opamp is used in the PCC. In another example, another type of known or later developed amplifier configuration that has an inverting and a non-inverting input may be used. 
     In this description, the term “couple” and derivatives thereof mean an indirect, direct, optical, and/or wireless electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, through an indirect electrical connection via other devices and connections, through an optical electrical connection, and/or through a wireless electrical connection. 
     Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.