Patent Publication Number: US-2011060431-A1

Title: Audio output devices

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to an audio output device, and more particularly to an audio output device for reducing crosstalk between audio output paths. 
     2. Description of the Related Art 
       FIG. 1  shows a conventional audio output device. A conventional audio output device  1  comprises a signal source  10 , a plurality of digital-to-analog converters (DACs)  11 , a plurality of amplifiers  12 , and a plurality of speakers  13 . In  FIG. 1 , two DACs  11   1 - 11   2 , two amplifiers  12   1  and  12   2 , and two speakers  13   1  and  13   2  are given as an example. One set of the DAC  11   1 , the amplifier  12   1 , and the speaker  13   1  forms one audio output path, and the other set of the DAC  11   2 , the amplifier  12   2 , and the speaker  13   2  forms the other audio output path. The signal source  10  generates two digital signals S 10   1  and S 10   2  to the DACs  11   1  and  11   2  respectively. The DACs  11   1  and  11   2  convert the received digital signals S 10   1  and S 10   2  to analog signals S 11   1  and S 11   2  respectively. The amplifiers  12   1  and  12   2  receive the analog signals S 11   1  and S 11   2  and amplify analog signals S 11   1  and S 11  to generate amplified signals S 12   1  and S 12   2 , respectively. The speakers  13   1  and  13   2  produce sound according to the amplified signals S 12   1  and S 12   2  respectively. 
     Assume that the digital signal S 10   1  is continuously switched between a high logic level and a low logic level, while the digital signal S 10   2  is continuously at a constant logic level, such as the low logic level (that is the audio output path corresponding to the digital signal S 10   2  is at a mute mode). In this case, the speaker  13   1  produces sound according to the amplified signal S 12   1  derived from the digital signal S 10   1 . Further, the speaker  13   2  should not produce sound according to the amplified signal S 12   2  derived from the digital signal S 10   2 . However, since the DACs  11   1  and  11   2 , the amplifiers  12   1  and  12   2 , and the speakers  13   1  and  13   2  of the two audio output paths use the same reference voltage and the same power source, crosstalk is generated between the two audio output paths, so that the speaker  13   2  undesirably products noises from the other audio output path. 
     Thus, it is desired to provide an audio output device which can prevent an audio output path at a mute mode from being influenced by crosstalk. 
     BRIEF SUMMARY OF THE INVENTION 
     An exemplary embodiment of an audio output device comprises a signal source, a detector, a plurality of digital-to-analog converters, and a plurality of amplifiers. The signal source generates a plurality of digital signals. The detector receives the digital signals and detects states of the digital signals to generate a plurality of control signals according to the detection results respectively. The digital-to-analog converters receive the digital signals and convert the digital signals to a plurality of analog signals, respectively. The amplifiers receive the analog signals and generate a plurality of amplified signals according to the control signals, respectively. 
     In an embodiment, when the detector detects that at least one of the digital signals is in a predetermined state, the detector controls the corresponding amplifier according to the corresponding control signal to not generate the amplified signal. 
     In another embodiment, when the detector detects that the at least one digital signal is in the predetermined state, the detector further controls the corresponding digital-to-analog converter according to the corresponding control signal to not generate the analog signal. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  shows a conventional audio output device; 
         FIG. 2  shows an exemplary embodiment of an audio output device; 
         FIG. 3  shows an exemplary embodiment of the detector in  FIG. 2 ; 
         FIG. 4  shows an exemplary embodiment of the detection unit in  FIG. 3 ; 
         FIG. 5  shows an exemplary embodiment of the amplifiers in  FIG. 2 ; 
         FIG. 6  shows another exemplary embodiment of an audio output device; and 
         FIG. 7  shows another exemplary embodiment of an audio output device. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
     Audio output devices are provided. In an exemplary embodiment of an audio output device in  FIG. 2 , an audio output device  2  comprises a signal source  20 , a plurality of digital-to-analog converter (DACs)  21 , a plurality of amplifiers  22 , a plurality of speakers  23 , and a detector  24 . In practice, the numbers of DACs  21 , amplifiers  22 , and speakers  23  are determined according to system requirements. However, in the embodiment of  FIG. 2 , two DACs  21   1  and  21   2 , two amplifiers  22   1  and  22   2 , and two speakers  23   1  and  23   2  are given as an example. One set of the DAC  21   1 , the amplifier  22   1 , and the speaker  23   1  forms one audio output path P 1 , and the other set of the DAC  21   2 , the amplifier  22   2 , and the speaker  23   2  forms the other audio output path P 2 . 
     Referring to  FIG. 2 , the signal source  20  generates a digital signal S 20   1  for the DAC  21   1  of the audio output path P 1 , while the signal source  20  further generates a digital signal S 20   2  for the DAC  21   2  of the audio output path P 2 . The DACs  21   1  and  21   2  receive the digital signals S 20   1  and S 20   2  respectively. The DAC  21   1  converts the received digital signal S 20   1  to an analog signal S 21   1 , and the DAC  21   2  converts the received digital signal S 20   2  to an analog signal S 21   2 . The amplifiers  22   1  and  22   2  receive the analog signals S 21   1  and S 21   2  respectively. The amplifier  22   1  amplifies the analog signal S 21   1  and generates an amplified signal S 22   1  according to a control signal S 24   1 . The amplifier  22   2  amplifies the analog signal S 21   2  and generates an amplified signal S 22   2  according to a control signal S 24   2 . The speakers  23   1  and  23   2  receive the amplified signals S 22   1  and S 22   2  and produce sound according to the amplified signals S 22   1  and S 22   2 , respectively. In the embodiment, the control signals S 24   1  and S 24   2  for controlling the amplifiers  22   1  and  22   2  are generated by the detector  24 . The detector  24  receives the digital signals S 20   1  and S 20   2 . The detector  24  detects states of the digital signals S 20   1  and S 20   2  and generates the control signals S 24   1  and S 24   2  according to the detection result related to the digital signals S 20   1  and S 20   2  respectively. 
     A digital signal generated by the signal source  20  may be continuously switched between a high logic level and a low logic level or in a predetermined state. In the embodiment, a digital signal generated by the signal source  20  in the predetermined state means that the digital signal is continuously at a constant logic level, such as a low logic level, for a predetermined time, wherein the predetermined time is determined according to system setting or specification. When a digital signal generated by the signal source  20  is continuously switched between a high logic level and a low logic level, the corresponding audio output path produces sound according to the corresponding amplified signal. When a digital signal generated by the signal source  20  is continuously at a constant logic level for a predetermined time (in the predetermined state), the corresponding audio output path does not produce sound according to the corresponding amplified signal; in other words, the corresponding audio output path is at a mute mode. 
     Thus, by detecting the states of the digital signals S 20   1  and S 20   2 , the detector  24  can determine whether the audio output paths P 1  and P 2  are at a mute mode. The detector  24  generates the control signals S 24   1  and S 24   2  according to the detection result to control the amplifiers  22   1  and  22   2  to generate the amplified signals S 22   1  and S 22   2  or not, respectively. The process for the detector  24  to control the amplifiers  22   1  and  22   2  will be described in the following. 
     Assume that the digital signal S 20   1  is continuously switched between a high logic level and a low logic level, while the digital signal S 20   2  is continuously at the low logic level for a predetermined time (in the predetermined state). Thus, the audio output path P 2  is at a mute mode. The detector  24  detects that the digital signal S 20   1  is continuously switched between the high logic level and the low logic level and de-asserts the control signal S 24   1  according to the detection result. The detector  24  controls the amplifier  22   1  of the audio output path P 1  according to the de-asserted control signal S 24   1 , and the amplifier  22   1  generates the amplified signal S 22   1  according to the analog signal S 21   1  derived from the digital signal S 20   1 . Then, the speaker  23   1  of the audio output path P 1  produces sound according to the amplified signal S 22   1 . On the contrary, the detector  24  detects that the digital signal S 20   2  is continuously at the low logic level (in the predetermined state) and asserts the control signal S 24   2  according to the detection result. The detector  24  controls the amplifier  22   2  of the audio output path P 2  according to the asserted control signal S 24   2 , and the amplifier  22   2  does not generate the amplified signal S 22   2  according to the analog signal S 21   2  derived from the digital signal S 20   2 . Thus, the speaker  23   2  does not receive any signal from the amplifier  22   2  and does not produce sound. 
     According to the above embodiment, when the audio output path P 2  is at the mute mode, the detector  24  controls the amplifier  22   2  of the audio output path P 2  to not generate the amplified signal S 22   2 . Since the speaker  23   2  of the audio output path P 2  does not receive the signal from the amplifier  22   2 , the sound derived from the audio output path P 1  is not transferred to the speaker  23   2 . Thus, crosstalk generated between the audio output paths P 1  and P 2  is minimized, reducing the noises produced by the speaker  23   2 . 
       FIG. 3  shows an exemplary embodiment of the detector  24  in  FIG. 2 . Referring to  FIG. 3 , the detector  24  comprises two detection units  30   1  and  30   2 . In the embodiment, the number of detection units is equal to the number of audio output paths. The detection units  30   1  and  30   2  detect the states of the digital signals S 20   1  and S 20   2  and generate the control signals S 24   1  and S 24   2 , respectively. Referring to  FIG. 4 , each of the detection units  30   1  and  30   2  comprises a plurality of delay circuits  40  and a logic gate  41 . In the following, the detection unit  30   1  is given as an example for description. Assume that the digital signal S 20   1  generated by the signal source  20  has M bits B 1 -B M . Thus, the detection unit  30   1  comprises M delay circuits  40   1 ˜ 40   M  for respectively receiving the bits B 1 -B M  of the digital signal S 20   1 . Each of the delay circuits  40   1 ˜ 40   M  comprises N D-type flip-flops (DFFs)  400  which is coupled in series and controlled by a clock signal CLK. In one delay circuit, the first D-type flip-flop among the D-type flip-flops receives the corresponding bit of the digital signal S 20   1 , and each D-type flip-flops generates a delay signal according to the corresponding bit. For example, the delay circuit  40   1  receives the first bit B 1  of the digital signal S 20   1  and comprises N D-type flip-flops  400   1-1 ˜ 400   1-N . The first D-type flip-flop  400   1-1  receives the bit B 1 . The D-type flip-flops  400   1-1 ˜ 400   1-N  generate the delay signals S 400   1-1 ˜S 400   1-N  in response to the bit B 1  of the digital signal S 20   1  respectively. Similarly, in the delay circuit  40   2 , the D-type flip-flop  400   2-1  receives the bit B 2  of the digital signal S 20   1 , and the D-type flip-flops  400   2-1 ˜ 400   2-N  generate the delay signals S 400   2-1 ˜S 400   2-N  in response to the bit B 2 ; in the delay circuit  40   M , the D-type flip-flop  400   M-1  receives the bit B M  of the digital signal S 20   1 , and the D-type flip-flops  400   M-1 ˜ 400   M-N  generate the delay signals S 400   M-1 ˜S 400   M-N  in response to the bit B M . 
     In the embodiment, the logic gate  41  is implemented by an exclusive OR (XOR) gate. The XOR gate  41  receives the delay signals S 400   1-1 ˜S 400   1-N , S 400   2-1 ˜S 400   2-N , . . . S 400   M-1 ˜S 400   M-N  and generates the control signal S 24   1  according to the delay signals S 400   1-1 ˜S 400   1-N , S 400   2-1 ˜S 400   2-N , . . . S 400   M-1 ˜S 400   M-N . According to the logic operation of the XOR gate  41 , when the digital signal S 20   1  is switched between the high logic level and the low logic level, the XOR gate  41  generates the control signal S 24   1  with a high level; that is the control signal S 24   1  is de-asserted. On the contrary, when the digital signal S 20   1  is continuously at the low logic level, the XOR gate  41  generates the control signal S 24   1  with a low level; that is the control signal S 24   1  is asserted. Then, whether the amplifier  22   1  generates the amplified signal S 22   1  is determined according to the control signal S 24   1 . 
     Referring to  FIG. 5 , in the embodiment, each of the amplifiers  22   1  and  22   2  may comprise a mute control unit  50  and an amplifying unit  51 . In the following, the amplifier  22   1  is given as an example for description. The mute control unit  50  is controlled by the detector  24 , in other words, whether the mute control unit  50  is enabled by the detector  24  is determined according to the control signal S 24   1 . The amplifying unit  51  receives the analog signal S 21   1  and amplifies the analog signal S 21   1  to generate the amplified signal S 22   1 . When receiving the de-asserted control signal S 24   1 , the mute control unit  50  is disabled, so that the amplifying unit  51  can amplify the analog signal S 21   1  to generate the amplified signal S 22   1  for the speaker  23   1 . On the contrary, when receiving the asserted control signal S 24   1 , the mute control unit  50  is enabled, so that the amplifying unit  51  is disabled by the mute control unit  50  and stops generating the amplified signal S 22   1  for the speaker  23   1 . 
     According to the above assumptions, since the digital signal S 20   1  is switched between the high logic level and the low logic level, the XOR gate  41  of the detection unit  30   1  generates the de-asserted control signal S 24   1 , and the mute control unit  50  of the amplifier  22   1  is disabled, so that the amplifying unit  51  of the amplifier  22   1  can amplify the analog signal S 21   1  to generate the amplified signal S 22   1  for the speaker  23   1 . Further, since the digital signal S 20   2  is continuously at the low logic level, the XOR gate  41  of the detection unit  30   2  generates the asserted control signal S 24   2 , and the mute control unit  50  of the amplifier  22   2  is enabled, so that the amplifying unit  51  of the amplifier  22   2  is disabled by the mute control unit  50  and stops generating the amplified signal S 22   2  for the speaker  23   2 . 
       FIG. 6  shows another exemplary embodiment of an audio output device. An audio output device  6  in  FIG. 6  is similar as the audio output device  2 . The difference between the audio output devices  2  and  6  is that the control signal S 24   1  in  FIG. 6  further controls the DAC  21   1  in the audio output path P 1  and that the control signal S 24   2  in  FIG. 6  further controls the DAC  21   2  in the audio output path P 2 . 
     In the above assumptions, since the digital signal S 20   1  is switched between the high logic level and the low logic level, the detector  24  generates the de-asserted control signal S 24   1 , so that the DAC  21   1  generates the analog signal S 21   1  according to the de-asserted control signal S 24   1 , and the amplifier  22   1  generates the amplified signal S 22   1  according to the de-asserted control signal S 24   1 . Since the digital signal S 20   2  is at the predetermined state (being continuously at the low logic level), the detector  24  generates the asserted control signal S 24   2 , so that the DAC  21   2  does not generate the analog signal S 21   2  according to the asserted control signal S 24   2 , and the amplifier  22   2  does not generate the amplified signal S 22   2  according to the asserted control signal S 24   2 . Thus, in the embodiment of  FIG. 6 , crosstalk generated between the audio output paths P 1  and P 2  is much degraded. 
     In some embodiments, the control signals S 24   1  and S 24   2  generated by the detector  24  can be used to only control the DACs  21   1  and  21   2 , as shown in  FIG. 7 . In the above embodiments, according to system requirements, the control signals S 24   1  and S 24   2  generated by the detector  24  can be used to control the amplifier  22   1  and  22   2 , the DACs  21   1  and  21   2 , or both of the amplifier  22   1  and  22   2  and DACs  21   1  and  21   2 . 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.