Patent Publication Number: US-10763357-B2

Title: Semiconductor device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation-in-part of U.S. application Ser. No. 16/392,591 filed on Apr. 23, 2019, which itself is a continuation of U.S. application Ser. No. 15/723,186 filed on Oct. 3, 2017, now U.S. Pat. No. 10,312,364. The above-mentioned applications are included in their entirety herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to the field of semiconductor technology. More particularly, the present invention relates to a trench-type semiconductor device and a fabrication method thereof. 
     2. Description of the Prior Art 
     Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. 
     Transistors are circuit components or elements that are often formed on semiconductor devices. Many transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, depending on the circuit design. A field effect transistor (FET) is one type of transistor. 
     Generally, a transistor includes a gate stack formed between source and drain regions. The source and drain regions may include a doped region of a substrate and may exhibit a doping profile suitable for a particular application. The gate stack is positioned over the channel region and may include a gate dielectric interposed between a gate electrode and the channel region in the substrate. 
     SUMMARY OF THE INVENTION 
     It is one object of the invention to provide an improved semiconductor device with two-dimensional material layer. 
     One aspect of the invention provides a semiconductor device including a substrate; a first dielectric layer on the substrate; a hard mask layer on the first dielectric layer; a trench in the hard mask layer and the first dielectric layer; a first source/drain electrode layer on a sidewall of the trench; a second dielectric layer on the first source/drain electrode layer in the trench; a second source/drain electrode layer on the second dielectric layer in the trench, wherein both of the first source/drain electrode layer and the second source/drain electrode layer extend along the sidewall and a bottom of the trench; a third dielectric layer on the second source/drain electrode layer in the trench; a fourth dielectric layer in the trench, dividing the second source/drain electrode layer into two portions comprising a first portion and a second portion in the trench; an n-type field-effect transistor (nFET) disposed over the trench; and a p-type field-effect transistor (pFET) disposed over the trench and spaced apart from the nFET, wherein the nFET and the pFET share one common gate electrode spanning the trench, wherein the nFEP and the pFET are configured to form an inverter. 
     Another aspect of the invention provides a semiconductor device includes a substrate, a first dielectric layer on the substrate, a hard mask layer on the first dielectric layer, a trench in the hard mask layer and the first dielectric layer, a first source/drain electrode layer on a sidewall of the trench, a second dielectric layer on the first source/drain electrode layer in the trench, a second source/drain electrode layer on the second dielectric layer in the trench, a third dielectric layer on the second source/drain electrode layer in the trench, an inter-layer dielectric (ILD) layer overlying the trench, an n-type field-effect transistor (nFET) disposed over the trench, and a p-type field-effect transistor (pFET) disposed over the trench and spaced apart from the nFET. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic top view showing a semiconductor device according to one embodiment of the invention. 
         FIG. 2  is a cross-sectional view taken along line I-I′ in  FIG. 1 . 
         FIG. 3  to  FIG. 7  illustrate an exemplary method for fabricating a semiconductor device according to one embodiment of the invention. 
         FIG. 8  to  FIG. 12  illustrate an exemplary method for fabricating a semiconductor device according to another embodiment of the invention. 
         FIG. 13  is a schematic top view showing a semiconductor device according to another embodiment of the invention. 
         FIG. 14  is a cross-sectional view taken along line II-II′ in  FIG. 13 . 
         FIG. 15  to  FIG. 17  illustrate an exemplary method of fabricating the semiconductor device as depicted in  FIG. 13  and  FIG. 14 . 
         FIG. 18  is a schematic top view showing a semiconductor device according to still another embodiment of the invention. 
         FIG. 19  is a cross-sectional view taken along line III-III′ in  FIG. 18 . 
         FIG. 20  is a schematic top view showing a semiconductor device according to still another embodiment of the invention. 
         FIG. 21  is a cross-sectional view taken along line IV-IV′ in  FIG. 20 . 
         FIG. 22  to  FIG. 29  are schematic, cross-sectional diagrams showing a method for fabricating the semiconductor device as depicted in  FIG. 18  and  FIG. 19 . 
         FIG. 30  is a schematic top view showing a semiconductor device according to still another embodiment of the invention. 
         FIG. 31  is a cross-sectional view taken along line V-V′ in  FIG. 30 . 
         FIG. 32  is a schematic top view showing a semiconductor device according to still another embodiment of the invention. 
         FIG. 33  is a cross-sectional view taken along line VI-VI′ in  FIG. 32 . 
         FIG. 34  is a cross-sectional view taken along line VII-VII′ in  FIG. 32 . 
       FIG. 35  is a schematic top view showing a semiconductor device according to still another embodiment of the invention. 
         FIG. 36  is a cross-sectional view taken along line VIII-VIII′ in  FIG. 35 . 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural changes may be made without departing from the scope of the present disclosure. 
     The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. 
     As described in the embodiments herein, steps such as deposition, patterning or etching of various films (including conductive films, metals, dielectric layers, etc.) can be accomplished using known processes such as chemical vapor deposition, physical vapor deposition, sputtering, atomic layer deposition, optical lithography processes, plasma dry etching, wet etching, reactive ion etching, and the like, the details of which will not be repeated. 
     The present invention pertains to a trench-type semiconductor transistor device, which may be applicable to various technologies including, but not limited to, single-type transistors, transmission gate transistors, CMOS transistors, or common-gate inverter designs. 
     Please refer to  FIG. 1  and  FIG. 2 .  FIG. 1  is a schematic top view showing a semiconductor device according to one embodiment of the invention.  FIG. 2  is a cross-sectional view taken along line I-I′ in  FIG. 1 . As shown in  FIG. 1  and  FIG. 2 , the semiconductor device  1  comprises a substrate  100 . According to one embodiment, the substrate  100  may be a semiconductor substrate such as a silicon substrate, a silicon-on-insulator (SOI) substrate, but is not limited thereto. It is understood that the substrate  100  may be composed of other suitable materials such as glass, ceramic, or metals. 
     A first dielectric layer  104  such as an inter-layer dielectric (ILD) layer may be formed on the substrate  100 . According to one embodiment, the first dielectric layer  104  may comprise silicon oxide, but is not limited thereto. According to one embodiment, an etch stop layer  102  such as a silicon nitride layer may be provided between the substrate  100  and the first dielectric layer  104 . According to one embodiment, a hard mask layer  106  such as a silicon nitride layer is formed on the first dielectric layer  104 . 
     According to one embodiment, a trench  204  is formed in the hard mask layer  106  and the first dielectric layer  104 . As can be seen in  FIG. 1 , the trench  204  may have a rectangular shape when viewed from the above. However, it is understood that the trench  204  may have other shapes, for example, circular shape or oval shape. 
     According to one embodiment, a first source/drain electrode layer  210  extends along a sidewall and a bottom of the trench  204 . According to one embodiment, the first source/drain electrode layer  210  may comprise conductive materials, for example, metals or polysilicon, but is not limited thereto. The first source/drain electrode layer  210  conformally covers the sidewall and the bottom of the trench  204 . The first source/drain electrode layer  210  is in direct contact with the hard mask layer  106  and the first dielectric layer  104  at the sidewall of the trench  204  and is in direct contact with the etch stop layer  102  at the bottom of the trench  204 . 
     According to one embodiment, a second dielectric layer  220  is conformally deposited on the first source/drain electrode layer  210  in the trench  204 . For example, the second dielectric layer  220  may be a silicon oxide layer, but is not limited thereto. A second source/drain electrode layer  230  such as a metal layer or a polysilicon layer is conformally formed on the second dielectric layer  220  in the trench  204 . A third dielectric layer  240  such as a silicon oxide layer is deposited on the second source/drain electrode layer  230  in the trench  204 . The second source/drain electrode layer  230  is insulated from the first source/drain electrode layer  210  by the second dielectric layer  220 . 
     The first source/drain electrode layer  210 , the second dielectric layer  220 , the second source/drain electrode layer  230 , and the third dielectric layer  240  completely fill up the trench  204 . The third dielectric layer  240  has a top surface that is flush with a top surface of the hard mask layer  106 . The top surface of the first source/drain electrode layer  210 , a top surface of the second dielectric layer  220 , a top surface of the second source/drain electrode layer  230 , a top surface of the third dielectric layer  240 , and a top surface of the hard mask layer  106  are coplanar. 
     As shown in  FIG. 1 , the first source/drain electrode layer  210  and the second source/drain electrode layer  230  are ring shaped and are concentrically arranged in the trench  204  around the third dielectric layer  230 . 
     According to one embodiment, a two-dimensional (2D) material layer  110  overlies the hard mask layer  106 , the first source/drain electrode layer  210 , the second dielectric layer  220 , the second source/drain electrode layer  230 , and the third dielectric layer  240 . According to one embodiment, the 2D material layer may comprise transition metal dichalcogenide, graphene, or boron nitride, but is not limited thereto. 
     According to one embodiment, the first source/drain electrode layer  210  extends vertically along the sidewall of the trench  204  between the 2D material layer  110  and the etch stop layer  102 . A top surface of the first source/drain electrode layer  210  is in direct contact with the 2D material layer  110  and a bottom surface of the first source/drain electrode layer  210  is in direct contact with the etch stop layer  102 . 
     According to one embodiment, a gate dielectric layer  120  is conformally deposited on the 2D material layer  110 . For example, the gate dielectric layer  120  may be a silicon oxide layer, but is not limited thereto. According to one embodiment, a gate electrode  130  is disposed on the gate dielectric layer  120 . For example, the gate electrode  130  may comprise metals or polysilicon, but is not limited thereto. The region between the first source/drain electrode layer  210  and the second source/drain electrode layer  230  that is directly under the gate electrode  130  constitutes a gate channel region. 
     As shown in  FIG. 1 , exemplary contact elements  310 ,  330  and  430  are disposed on the first source/drain electrode layer  210 , the second source/drain electrode layer  230 , and the gate electrode  130 , respectively. 
     Please refer to  FIG. 3  to  FIG. 7 .  FIG. 3  to  FIG. 7  illustrate an exemplary method for fabricating a semiconductor device according to one embodiment of the invention. As shown in  FIG. 3 , a substrate  100  is provided. According to one embodiment, the substrate  100  may be a semiconductor substrate such as a silicon substrate, a silicon-on-insulator (SOI) substrate, but is not limited thereto. It is understood that the substrate  100  may be composed of other suitable materials such as glass, ceramic, or metals. 
     According to one embodiment, an etch stop layer  102  is then deposited on the substrate  100 . For example, the etch stop layer  102  may comprise silicon nitride, but is not limited thereto. A first dielectric layer  104  is then deposited on the etch stop layer  102 . For example, the first dielectric layer  104  may comprise silicon oxide, but is not limited thereto. A hard mask layer  106  is then deposited on the first dielectric layer  104 . For example, the hard mask layer  106  may comprise silicon nitride, but is not limited thereto. 
     As shown in  FIG. 4 , a lithographic process and a dry etching process may be performed to form a trench  204  in the hard mask layer  106  and the first dielectric layer  104 . The trench  204  has opposite vertical sidewalls  204   a  and a bottom surface  204   b.  The bottom surface  204   b  of the trench  204  is also the exposed top surface of the etch stop layer  102 . 
     As shown in  FIG. 5 , a first source/drain electrode layer  210  is conformally deposited on the sidewall  204   a  and the bottom surface  204   b  of the trench  204 . The first source/drain electrode layer  210  also covers the top surface of the hard mask layer  106  outside the trench  204  at this point. According to one embodiment, the first source/drain electrode layer  210  may comprise conductive materials, for example, metals or polysilicon, but is not limited thereto. According to one embodiment, the first source/drain electrode layer  210  may be deposited by methods known in the art, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. 
     Subsequently, a second dielectric layer  220  is conformally deposited on the first source/drain electrode layer  210 . For example, the second dielectric layer  220  may be a silicon oxide layer, but is not limited thereto. A second source/drain electrode layer  230  such as a metal layer or a polysilicon layer is then conformally deposited on the second dielectric layer  220 . A third dielectric layer  240  such as a silicon oxide layer is then deposited on the second source/drain electrode layer  230 . The second source/drain electrode layer  230  is insulated from the first source/drain electrode layer  210  by the second dielectric layer  220 . The first source/drain electrode layer  210 , the second dielectric layer  220 , the second source/drain electrode layer  230 , and the third dielectric layer  240  together completely fill up the trench  204 . 
     As shown in  FIG. 6 , subsequently, a chemical mechanical polishing (CMP) process may be performed to planarize the first source/drain electrode layer  210 , the second dielectric layer  220 , the second source/drain electrode layer  230 , and the third dielectric layer  240 . After the CMP, the third dielectric layer  240  has a top surface that is flush with a top surface of the hard mask layer  106 . The top surface of the first source/drain electrode layer  210 , a top surface of the second dielectric layer  220 , a top surface of the second source/drain electrode layer  230 , a top surface of the third dielectric layer  240 , and a top surface of the hard mask layer  106  are coplanar. 
     As shown in  FIG. 7 , a two-dimensional (2D) material layer  110  is conformally coated on the hard mask layer  106 , the first source/drain electrode layer  210 , the second dielectric layer  220 , the second source/drain electrode layer  230 , and the third dielectric layer  240 . According to one embodiment, the 2D material layer  110  may comprise transition metal dichalcogenide, graphene, or boron nitride, but is not limited thereto. The formation of the 2D material layer  110  is well-known in the art. For example, the 2D material layer  110  may be formed by various coating methods such as spin coating, dip coating, or bar coating. The 2D material layer  110  may have a nanometer-level or nano-scale thickness. Optionally, an annealing process may be performed after coating the 2D material layer  110 . 
     According to one embodiment, the first source/drain electrode layer  210  extends vertically along the sidewall of the trench  204  between the 2D material layer  110  and the etch stop layer  102 . The first source/drain electrode layer  210  also extends horizontally along the bottom surface  204   b.  A top surface of the first source/drain electrode layer  210  is in direct contact with the 2D material layer  110  and a bottom surface of the first source/drain electrode layer  210  is in direct contact with the etch stop layer  102 . 
     According to one embodiment, subsequently, a gate dielectric layer  120  is conformally deposited on the 2D material layer  110 . For example, the gate dielectric layer  120  may be a silicon oxide layer, but is not limited thereto. According to one embodiment, a gate electrode  130  is then disposed on the gate dielectric layer  120 . For example, the gate electrode  130  may comprise metals or polysilicon, but is not limited thereto. 
     Please refer to  FIG. 8  to  FIG. 12 .  FIG. 8  to  FIG. 12  illustrate an exemplary method for fabricating a semiconductor device according to another embodiment of the invention, wherein like numeral numbers designate like layers, regions, or elements. As shown in  FIG. 8 , likewise, after the formation of the hard mask layer  106 , a trench  204  is etched into the hard mask layer  106  and the first dielectric layer  104 . The trench  204  has opposite vertical sidewalls  204   a  and a bottom surface  204   b.  The bottom surface  204   b  of the trench  204  is also the exposed top surface of the etch stop layer  102 . 
     As shown in  FIG. 9 , a first source/drain electrode layer  210  is conformally deposited on the sidewall  204   a  and the bottom surface  204   b  of the trench  204 . The first source/drain electrode layer  210  also covers the top surface of the hard mask layer  106  outside the trench  204  at this point. According to one embodiment, the first source/drain electrode layer  210  may comprise conductive materials, for example, metals or polysilicon, but is not limited thereto. According to one embodiment, the first source/drain electrode layer  210  may be deposited by methods known in the art, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. 
     As shown in  FIG. 10 , subsequently, an anisotropic dry etching process is performed to etch the first source/drain electrode layer  210 , thereby forming a conductive, ring-shaped spacer  210 ′ on the sidewall  204   a  of the trench  204 . 
     As shown in  FIG. 11 , a second dielectric layer  220  is conformally deposited on the conductive, ring-shaped spacer  210 ′. For example, the second dielectric layer  220  may be a silicon oxide layer, but is not limited thereto. A second source/drain electrode layer  230  such as a metal layer or a polysilicon layer is then conformally deposited on the second dielectric layer  220 . 
     As shown in  FIG. 12 , subsequently, an anisotropic dry etching process is performed to etch the second source/drain electrode layer  230 , thereby forming a conductive, ring-shaped spacer  230 ′ on the sidewall  204   a  of the trench  204 . The conductive, ring-shaped spacer  230 ′ is insulated from the conductive, ring-shaped spacer  210 ′ by the second dielectric layer  220 . 
     Subsequently, a third dielectric layer  240  such as a silicon oxide layer is then deposited into the trench  204  to cover the conductive, ring-shaped spacer  230 ′ and the second dielectric layer  220 . The conductive, ring-shaped spacer  210 ′, the second dielectric layer  220 , the conductive, ring-shaped spacer  230 ′, and the third dielectric layer  240  together completely fill up the trench  204 . 
     As shown in  FIG. 12 , subsequently, a chemical mechanical polishing (CMP) process may be performed to planarize the conductive, ring-shaped spacer  210 ′, the second dielectric layer  220 , the conductive, ring-shaped spacer  230 ′, and the third dielectric layer  240 . After the CMP, the third dielectric layer  240  has a top surface that is flush with a top surface of the hard mask layer  106 . The top surface of the conductive, ring-shaped spacer  210 ′, a top surface of the second dielectric layer  220 , a top surface of the conductive, ring-shaped spacer  230 ′, a top surface of the third dielectric layer  240 , and a top surface of the hard mask layer  106  are coplanar. 
     A 2D material layer  110  is then conformally coated on the hard mask layer  106 , the conductive, ring-shaped spacer  230 ′, the second dielectric layer  220 , the conductive, ring-shaped spacer  230 ′, and the third dielectric layer  240 . According to one embodiment, the 2D material layer  110  may comprise transition metal dichalcogenide, graphene, or boron nitride, but is not limited thereto. The 2D material layer  110  may have a nanometer-level or nano-scale thickness. Optionally, an annealing process may be performed after coating the 2D material layer  110 . 
     Subsequently, a gate dielectric layer  120  is conformally deposited on the 2D material layer  110 . For example, the gate dielectric layer  120  may be a silicon oxide layer, but is not limited thereto. According to one embodiment, a gate electrode  130  is then disposed on the gate dielectric layer  120 . For example, the gate electrode  130  may comprise metals or polysilicon, but is not limited thereto. 
       FIG. 13  is a schematic top view showing a semiconductor device according to another embodiment of the invention.  FIG. 14  is a cross-sectional view taken along line II-II′ in  FIG. 13 , wherein like numeral numbers designate like layers, regions, or elements. As shown in  FIG. 13  and  FIG. 14 , the semiconductor device  2  may be a transmission gate device. The semiconductor device  2  comprises two field effect transistors (FETs) comprising an n-type FET (nFET)  21  and a p-type FET (pFET)  22 . The gate electrode  130   a  of the nFET  21  is separated from the gate electrode  130   b  of the pFET  22 . 
     According to one embodiment, the nFET  21  further comprises a gate dielectric layer  120   a  and an n-type doped 2D material layer  110   a.  The pFET  22  further comprises a gate dielectric layer  120   b  and a p-type doped 2D material layer  110   b.  According to one embodiment, the gate dielectric layer  120   a  is separated from the gate dielectric layer  120   b,  and the n-type doped 2D material layer  110   a  is separated from the p-type doped 2D material layer  110   b.  The film stack within the trench  204  is identical with that as depicted in  FIG. 1  and  FIG. 2 . 
       FIG. 15  to  FIG. 17  illustrate an exemplary method of fabricating the semiconductor device  2  as depicted in  FIG. 13  and  FIG. 14 . As shown in  FIG. 15 , after the formation of the film stack within the trench  204  as set forth in  FIG. 6 , an n-type doped 2D material layer  110   a  and a p-type doped 2D material layer  110   b  are formed over the substrate  100 . The n-type doped 2D material layer  110   a  is separated from the p-type doped 2D material layer  110   b.    
     As shown in  FIG. 16 , a gate dielectric layer  120  is conformally deposited on the n-type doped 2D material layer  110   a,  the p-type doped 2D material layer  110   b,  and the third dielectric layer  240 . For example, the gate dielectric layer  120  may be a silicon oxide layer, but is not limited thereto. According to one embodiment, a gate electrode  130  is then disposed on the gate dielectric layer  120 . For example, the gate electrode  130  may comprise metals or polysilicon, but is not limited thereto. 
     As shown in  FIG. 17 , a lithographic process and a dry etching process are then performed to pattern the gate electrode  130  and the gate dielectric layer  120 , thereby forming the gate electrode  130   a  of the nFET  21  and the gate electrode  130   b  of the pFET  22 . 
       FIG. 18  is a schematic top view showing a semiconductor device according to still another embodiment of the invention.  FIG. 19  is a cross-sectional view taken along line III-III′ in  FIG. 18 , wherein like numeral numbers designate like layers, regions, or elements. As shown in  FIG. 18  and  FIG. 19 , the semiconductor device  3   a  may be a CMOS device with a common gate. The semiconductor device  3   a  comprises an n-type MOS (nMOS)  31  and a p-type MOS (pMOS)  32 . The nMOS  31  and the pMOS  32  share one gate electrode  130 . 
     The nMOS  31  comprises a first source/drain electrode layer  210   a,  a second source/drain electrode layer  230   a  insulated from the first source/drain electrode layer  210   a  by the second dielectric layer  220  in the trench  204 . An n-type doped 2D material layer  110   a  is disposed over the first source/drain electrode layer  210   a  and the second source/drain electrode layer  230   a.  The pMOS  32  comprises a first source/drain electrode layer  210   b,  a second source/drain electrode layer  230   b  insulated from the first source/drain electrode layer  210   b  by the second dielectric layer  220  in the trench  204 . A p-type doped 2D material layer  110   b  is disposed over the first source/drain electrode layer  210   b  and the second source/drain electrode layer  230   b.  The film stack is similar with that depicted in  FIG. 6  except that discontinuities are provided between the first source/drain electrode layer  210   a  and the first source/drain electrode layer  210   b  and between the second source/drain electrode layer  230   a  and the second source/drain electrode layer  230   b.    
       FIG. 20  is a schematic top view showing a semiconductor device according to still another embodiment of the invention.  FIG. 21  is a cross-sectional view taken along line IV-IV′ in  FIG. 20 , wherein like numeral numbers designate like layers, regions, or elements. As shown in  FIG. 20  and  FIG. 21 , the semiconductor device  3   b  may be a CMOS device with separated gates. Likewise, the semiconductor device  3   b  comprises an nMOS  31  and a pMOS  32 . The nMOS  31  has its own gate electrodes  130   a  and the pMOS  32  has its own gate electrodes  130   b.  That is, the gate electrode  130   a  of the nMOS  31  is separated from the gate electrode  130   b  of the pMOS  32 . 
       FIG. 22  to  FIG. 29  are schematic, cross-sectional diagrams showing a method for fabricating the semiconductor device  3   a  as depicted in  FIG. 18  and  FIG. 19 , wherein like numeral numbers designate like layers, regions, or elements. 
     As shown in  FIG. 22 , a lithographic process and a dry etching process may be performed to form a trench  204  in the hard mask layer  106  and the first dielectric layer  104 . The trench  204  has opposite vertical sidewalls  204   a  and a bottom surface  204   b.  The bottom surface  204   b  of the trench  204  is also the exposed top surface of the etch stop layer  102 . 
     As shown in  FIG. 23 , a first source/drain electrode layer  210  is conformally deposited on the sidewall  204   a  and the bottom surface  204   b  of the trench  204 . The first source/drain electrode layer  210  also covers the top surface of the hard mask layer  106  outside the trench  204  at this point. According to one embodiment, the first source/drain electrode layer  210  may comprise conductive materials, for example, metals or polysilicon, but is not limited thereto. According to one embodiment, the first source/drain electrode layer  210  may be deposited by methods known in the art, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. 
     Subsequently, a second dielectric layer  220  is conformally deposited on the first source/drain electrode layer  210 . For example, the second dielectric layer  220  may be a silicon oxide layer, but is not limited thereto. A second source/drain electrode layer  230  such as a metal layer or a polysilicon layer is then conformally deposited on the second dielectric layer  220 . A third dielectric layer  240  such as a silicon oxide layer is then conformally deposited on the second source/drain electrode layer  230 . The second source/drain electrode layer  230  is insulated from the first source/drain electrode layer  210  by the second dielectric layer  220 . At this point, a recess  241  may be formed on the third dielectric layer  240  within the trench  204 . 
     As shown in  FIG. 24 , the third dielectric layer  240  and the second source/drain electrode layer  230  are subjected to an anisotropic dry etching process so as to form separated second source/drain electrode layers  230   a  and  230   b  and separated third dielectric layers  240   a  and  240   b  on the second dielectric layer  220 . A central opening  510  is formed within the trench  204 . 
     As shown in  FIG. 25 , through the central opening  510 , an etching process may be carried out to etch the second dielectric layer  220  and the first source/drain electrode layer  210 , thereby forming separated first source/drain electrode layers  210   a  and  210   b.    
     As shown in  FIG. 26 , a fourth dielectric layer  250  such as a silicon oxide layer may be deposited over the substrate  100  in a blanket manner. The fourth dielectric layer  250  fills up the central opening  510 . 
     As shown in  FIG. 27 , the fourth dielectric layer  250  is then subjected to a CMP process. The layers above the hard mask layer  106  are removed so as to form a planar surface. 
     As shown in  FIG. 28 , an n-type doped 2D material layer  110   a  and a p-type doped 2D material layer  110   b  are formed over the substrate  100 . The n-type doped 2D material layer  110   a  is separated from the p-type doped 2D material layer  110   b.    
     As shown in  FIG. 29 , a gate dielectric layer  120  is conformally deposited on the n-type doped 2D material layer  110   a,  the p-type doped 2D material layer  110   b,  and the third dielectric layer  240 . For example, the gate dielectric layer  120  may be a silicon oxide layer, but is not limited thereto. According to one embodiment, a gate electrode  130  is then disposed on the gate dielectric layer  120 . For example, the gate electrode  130  may comprise metals or polysilicon, but is not limited thereto. 
       FIG. 30  is a schematic top view showing a semiconductor device according to still another embodiment of the invention.  FIG. 31  is a cross-sectional view taken along line V-V′ in  FIG. 30 , wherein like numeral numbers designate like layers, regions, or elements. As shown in  FIG. 30  and  FIG. 31 , the semiconductor device  4  may be an inverter design with common gate. The layer stack structure is similar to that as depicted in  FIG. 19 , except that only the second source/drain electrode layer  230  is divided into two separated portions: the second source/drain electrode layers  230   a  and  230   b.    
     As shown in  FIG. 30 , exemplary contact elements  310 ,  330   a,    330   b  and  430  are disposed on the first source/drain electrode layer  210 , the second source/drain electrode layer  230   a,  the second source/drain electrode layer  230   b,  and the gate electrode  130 , respectively. For example, the contact elements  310  may be coupled to V out  signal, the contact elements  330   a  may be coupled to V ss  signal, the contact elements  330   b  may be coupled to V dd  signal, and the contact element  430  may be coupled to V in  signal. 
       FIG. 32  is a schematic top view showing a semiconductor device according to still another embodiment of the invention, wherein like numeral numbers designate like layers, regions, or elements.  FIG. 33  is a cross-sectional view taken along line VI-VI′ in  FIG. 32 .  FIG. 34  is a cross-sectional view taken along line VII-VII′ in  FIG. 32 . As shown in  FIG. 32  to  FIG. 34 , the semiconductor device  5  may be an inverter design with common gate. The layer stack structure is similar to that as depicted in  FIG. 30 . Likewise, the second source/drain electrode layer  230  is divided into two a first portion  230   a  and a second portion  230   b  by the fourth dielectric layer  250 . The gate electrode  130  extends along a first direction (or the reference X axis direction). 
     As depicted in  FIG. 33  and  FIG. 34 , an inter-layer dielectric (ILD) layer  108  is deposited to cover the semiconductor device  5 . Signal lines  501 ˜ 505  extending along a second direction (or the reference Y axis direction) are disposed on the ILD layer  108 . The first direction is not parallel with the second direction. The contact elements  310   a,    310   b,    330   a,    330   b  and  430  are disposed on the first source/drain electrode layer  210 , the second source/drain electrode layer  230   a,  the second source/drain electrode layer  230   b,  and the gate electrode  130 , respectively. 
     The contact elements  310   a  are electrically connected to the signal line  501  and the contact elements  310   b  are electrically connected to the signal line  505 . The contact elements  330   a  are electrically connected to the signal line  502  and the contact elements  330   b  are electrically connected to the signal line  504 . The contact element  430  is electrically connected to the signal line  503 . The signal lines  501  and  505  are electrically coupled to V out  signal, the signal line  502  is electrically coupled to V ss  signal, the signal line  504  is electrically coupled to V dd  signal, and signal line  503  is electrically coupled to V in  signal. As depicted in  FIG. 34 , the contact elements  330   a,    330   b  may penetrate through the ILD layer  108  and the third dielectric layer  240   b  and may be in direct contact with the horizontal bottom of the second portion  230   b.    
     FIG. 35  is a schematic top view showing a semiconductor device according to still another embodiment of the invention.  FIG. 36  is a cross-sectional view taken along line VIII-VIII′ in  FIG. 35 , wherein like numeral numbers designate like layers, regions, or elements. As shown in  FIG. 35  and  FIG. 36 , the semiconductor device  6  may be a transmission gate device. The semiconductor device  6  comprises two field effect transistors (FETs) comprising an n-type FET (nFET)  21  and a p-type FET (pFET)  22 . The gate electrode  130   a  of the nFET  21  is separated from the gate electrode  130   b  of the pFET  22 . The gate electrode  130   a  and  130   b  may extend along a first direction (or the reference X axis direction). 
     As depicted in  FIG. 36 , the ILD layer  108  is deposited to cover the semiconductor device  6 . Signal lines  601 ˜ 606  extending along a second direction (or the reference Y axis direction) are disposed on the ILD layer  108 . The first direction is not parallel with the second direction. The contact elements  310   a,    310   b,    330   a,    330   b,    430   a,  and  430   b  are disposed on the first source/drain electrode layer  210 , the second source/drain electrode layer  230 , the gate electrode  130   a,  and the gate electrode  130   b,  respectively. 
     The contact elements  310   a  are electrically connected to the signal line  602  and the contact elements  310   b  are electrically connected to the signal line  605 . The contact elements  330   a  are electrically connected to the signal line  603  and the contact elements  330   b  are electrically connected to the signal line  604 . The contact element  430   a  is electrically connected to the signal line  601 . The contact element  430   b  is electrically connected to the signal line  606 . The signal lines  602  and  605  are electrically coupled to V out  signal, the signal line  606  is electrically coupled to V ss  signal, the signal line  601  is electrically coupled to V dd  signal, and signal line  603  and  604  are electrically coupled to V in  signal. As depicted in  FIG. 36 , the contact elements  430   a,    430   b  may penetrate through the ILD layer  108 . 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.