Patent Publication Number: US-6704847-B1

Title: Host access to shared memory with a high priority mode

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is related to co-assigned U.S. patent applications Ser. No. 09/591,076, Ser. No. 09/591,623; and Ser. No. 09/591,615, co-filed contemporaneously herewith and incorporated herein by reference. 
    
    
     This application claims priority to S.N. 99401390.2, filed in Europe on Jun. 9, 1999. 
     TECHNICAL FIELD OF THE INVENTION 
     This invention generally relates to microprocessors, and more specifically to improvements in shared access memory circuits, systems, and methods of making. 
     BACKGROUND OF THE INVENTION 
     Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor. 
     Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for&#39;specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible. 
     To further improve performance of a digital system, two or more processors can be interconnected. For example, a DSP may be interconnected with a general purpose processor in a digital system. The DSP performs numeric intensive signal processing algorithms while the general purpose processor manages overall control flow. The two processors communicate and transfer data for signal processing via shared memory. 
     SUMMARY OF THE INVENTION 
     Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims. The present invention is directed to improving the performance of processors, such as for example, but not exclusively, digital signal processors. 
     In accordance with a first aspect of the invention, there is provided a digital system having a memory circuit that can be accessed by several requestor circuits. A scheduling circuit is connected to the requester circuits and is operable to sequentially schedule memory accesses to the memory circuit. A selection circuit is connected to one of the requester circuits and to the output of the scheduling circuit. 
     Priority circuitry is provided for comparing a first priority for the first requestor and a second priority for the second requestor. The priority circuitry is controllably connected to the selection circuit, such that both the first requestor circuit and the second requestor circuit can sequentially access the memory circuit when the priority circuitry indicates a first relative priority state between the first priority and the second priority and such that the first requestor circuit has exclusive access to the memory circuit when the priority circuitry indicates a second relative priority state. 
     According to another aspect of the present invention, there is a first priority register for holding the first priority for the first requestor circuit and a second priority register for holding the second priority for the second requestor. The first priority register and the second priority register can be changed in response to a write transaction by at least one of the requestor circuits. 
     According to another aspect of the present invention, there is a clock circuit connected to the second requestor and to the memory circuit. The memory circuit operates synchronously with the clock circuit when the priority circuitry indicates the first relative priority state exists. The memory circuit operates in an asynchronous manner when the priority circuitry indicates the second relative priority state. 
     According to another aspect of the present invention, a method of operating a digital system having a memory circuit that is shared by a plurality of requester circuits each having a priority level is provided, comprising the steps of: (a) setting the priority levels to have a first set of relative values, (b) sharing access to the memory circuit between the plurality of requestor circuits while the priority levels have the first set of relative values, (c) setting the priority levels to have a second set of relative values, and (d) limiting access to the memory circuit to only a first requestor of the plurality of requesters while the priority levels have the second set of relative values, such that the first requestor has faster memory access during limited access. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     Particular embodiments in accordance with the invention will now be described, by way of example only, and with reference to the accompanying drawings in which like reference signs are used to denote like parts and in which the Figures relate to the digital system of FIG. 3, unless otherwise stated, and in which: 
     FIG. 1 is a block diagram of two processors sharing a block of memory, in which one of the processors can bypass the scheduling circuitry in a high priority mode, according to an aspect of the present invention; 
     FIG. 2 is a block diagram of another digital system that includes an embodiment of the present invention; 
     FIG. 3 is a more detailed block diagram of a megacell from FIG. 2, 
     FIG. 4 is a detailed block diagram of the DMA controller of FIG. 3; 
     FIG. 5 is a block diagram showing portions of the host port interface of the DMA controller; 
     FIG. 6 is a timing diagram illustrating a memory access in SAM mode; 
     FIG. 7 is a timing diagram illustrating a memory access in HOM mode; 
     FIG. 8 is a schematic representation of an integrated circuit incorporating the digital system of FIG. 1; and 
     FIG. 9 illustrates an exemplary implementation of an example of such an integrated circuit in a mobile telecommunications device, such as a mobile telephone. 
    
    
     Corresponding numerals and symbols in the different figures and tables refer to corresponding parts unless otherwise indicated. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Although the invention finds particular application to Digital Signal Processors (DSPs), implemented, for example, in an Application Specific Integrated Circuit (ASIC), it also finds application to other forms of processors. An ASIC may contain one or more megacells which each include custom designed functional circuits combined with pre-designed functional circuits provided by a design library. 
     FIG. 1 is a block diagram of digital system  1  which has a host processor  10  and DSP  20  sharing a block of memory  60 . A scheduling block  40  receives transfer requests from a memory access node in host processor  10  connected to bus  11  and transfer requests from a memory access node in DSP  20  connected to bus  21 . Scheduler  40  interleaves these requests in a sequential manner and presents them to the memory block  60  via a request output node connected to bus  41 . DSP  20 , scheduler  40  and memory  60  operate synchronously to a DSP clock signal provided by clock circuit  22 . Host  10  operates with reference to a host clock signal provided by clock circuit  12 . Scheduler circuit  40  includes synchronization circuits to synchronize memory accesses by the host to the DSP clock signal. 
     Accesses by the host processor can be categorized as either low priority or high priority accesses. Likewise, accesses by the DSP processor can be categorized as either low priority or high priority accesses. Priority circuitry  54  receives priority indicators from the host via signal  55  and from the DSP via signal  56  and compares the priority of pending requests. When an access request by host  10  has a higher priority than a pending access request by DSP  20 , the access by the host will bypass synchronization circuitry within scheduler  40  that synchronizes timing to DSP timing. Selector mux  50  receives bus  11  on one input and bus  41  on a second input and provides access to memory circuit  60  via an output node connected to bus  51 . Selector mux  50  is controlled by select signal  57  from priority circuit  54 . Bus  11  is selected when priority of the host is higher than the priority of the DSP. Bus  41  is selected when the priority of the host is the same as or less than the priority of the DSP. Memory circuit  60  is accessed directly in high priority mode by bus  11  in a manner that bypasses scheduler  40 . When memory circuit  60  is accessed directly by host  10  in high priority mode, memory circuit  60  operates in an asynchronous mode in response to signal  57  so that the host access need not be synchronized to the DSP signal. Host accesses in high priority mode are thus faster since a synchronization and scheduling delay is not incurred. 
     In an alternative embodiment of the present invention, the host and DSP may both operate in reference to the same clock signal. In such an embodiment, synchronization is not involved, but a high priority host access still bypasses scheduling delay imposed by scheduler  40 . 
     FIG. 2 is a block diagram of another digital system that includes an embodiment of the present invention. Megacell  100  includes a CPU, DMA controller and memory circuits, and will be described in greater detail later. Host processor  110  is connected to megacell  100  via enhanced host port interface (EHPI)  112 . EHPI  112  provides multiplexing of the host address and data bus  111  to match the host port interface  115  provided by megacell  100 . Memory  122 , general purpose peripherals  132  and dedicated peripherals  134  can be accessed by host processor  110  or the CPU within megacell  100 . Control circuitry  170  provides timing signals for circuitry within megacell  100 . MCU  110  includes its own timing circuitry, which requires that accesses by MCU  110  to resources controlled by megacell  100  must be synchronized to the time base of megacell  100 . 
     JTAG test port  160  contains hardware extensions for advanced debugging features. These assist in the user&#39;s development of the application system (software and the hardware) utilizing only the JTAG interface, a test access port and boundary-scan architecture defined by the IEEE 1149.1 standard with extended operating mode enhancements, as described in U.S. Pat. No. 5,828,824. Emulation circuitry  150  provides debug program control and execution tracing facilities. 
     FIG. 3 is a more detailed block diagram of megacell  100 . CPU  200  is a digital signal processor (DSP). CPU  200  access memory circuits  220 ,  222  and  224  and EMIF  120  via memory interface circuitry  202 . CPU  200  access other resources via RHEA bridge  230  to RHEA bus  130 . DMA controller  210  is a multi-channel DMA controller with separate channel and port controllers with each port having local scheduling circuitry. DMA  210  can be programmed to transfer data between various sources and destinations within digital system  10 , such as single access RAM  220 , dual access RAM  222 , external memory  122  via external memory interface  120 , and peripheral devices on resource bus (RHEA)  130  via RHEA bridge  230 . MCU  110  can also access these resources via host port interface (HPI)  115  which is connected to DMA controller  210 . The path between the HPI port and the Memory is a DMA channel. 
     Memory circuit  220  is a 128 K×16 Single Access RAM (SARAM), comprising sixteen 32 K byte modules. DMA  210  can access the SARAM by a 16 bit DMA bus. The DMA bus access (R/W) can be in SAM (Shared access mode) or in HOM mode (Host only mode). An access by MCU  110  in HOM mode will bypass synchronization circuitry within DMA  210  that synchronizes MCU timing to megacell  100  timing. According to an aspect of the present invention, a HOM size register is provided so that the size of the HOM memory can be specified by the host processor. 
     The priority scheme between CPU  200  and DMA  210  is programmable. The priority circuitry is implemented in the SARAM, whereas the control register is located in the DMA IO space accessible via RHEA bus branch  130   a.    
     Memory circuit  222  is a 32 K×16 Dual Access RAM (DARAM) comprising four 16 K byte modules. CPU  200  can perform two accesses to one DARAM memory module in one cycle; for example, a single read and single write, or a long read and a long write, a dual read and a single write etc. The priorities assigned to the different accesses are handled by the DARAM. The priority scheme between CPU and DMA is programmable. The priority circuitry is implemented in the DARAM, whereas the control register is located in the DMA IO space accessible via the RHEA bus. 
     Another embodiment of the present invention may have different configurations of memory and peripherals. 
     FIG. 3 only shows those portions of megacell  100  that are relevant to an understanding of an embodiment of the present invention. Details of general construction for DSPs are well known, and may be found readily elsewhere. For example, U.S. Pat. No. 5,072,418 issued to Frederick Boutaud, et al, describes a DSP in detail and is incorporated herein by reference. U.S. Pat. No. 5,329,471 issued to Gary Swoboda, et al, describes in detail how to test and emulate a DSP and is incorporated herein by reference. Details of portions of DMA controller  210  relevant to an embodiment of the present invention are explained in sufficient detail hereinbelow, so as to enable one of ordinary skill in the microprocessor art to make and use the invention. 
     Table 1 summarizes several of the acronyms used throughout this document. 
     
       
         
           
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 Glossary of Terms 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
            
               
                 DMA 
                 Direct Memory Access 
               
               
                 MIF 
                 Memory Interface 
               
               
                 EMIF 
                 External Memory Interface 
               
               
                 HPI 
                 Host Port Interface 
               
               
                 RHEA 
                 Resource access bus, for peripheral devices and memory 
               
               
                   
                 mapped register access 
               
               
                 SARAM 
                 Single Access RAM 
               
               
                 DARAM 
                 Dual Access RAM 
               
               
                 PDROM 
                 Program and Data ROM 
               
               
                 HOM_M 
                 Host Only Mode Memory 
               
               
                 SAM_M 
                 Share Access Mode Memory 
               
               
                 HOM_R 
                 Host Only Mode RHEA 
               
               
                 SAM_R 
                 Share Access Mode RHEA 
               
               
                 DSP 
                 Digital Signal Processor 
               
               
                 CPU 
                 a microprocessor within a megacell on an integrated circuit 
               
               
                   
                 (IC), such as a DSP. 
               
               
                 MCU 
                 a second processor that interacts with the CPU, may act as a 
               
               
                   
                 master, or host, processor 
               
               
                 EHPI 
                 Enhanced Host Port Interface. 
               
               
                 Element 
                 the atomic unit of data transferred by the DMA. An element 
               
               
                   
                 can be a word, 2 words, a burst of 4 words, or a burst of 
               
               
                   
                 8 words. 
               
               
                 Frame 
                 set of elements. 
               
               
                 FIFO 
                 first in, first out buffer 
               
               
                   
               
            
           
         
       
     
     DMA controller  210  transfers data between points in the memory space without intervention by the CPU. The DMA allows movements of data to and from internal memory, external memory and peripherals to occur in background of CPU operation. The DMA has six independent programmable channels allowing six different contexts for DMA operation, executed in Time Division Multiplexed (TDM) mode. 
     The DMA architecture is organized around ports and channels. Referring still to FIG. 3, each resource the DMA can access has its own port: SARAM port  212   a , DARAM port  212   b , EMIF port  212   c , and RHEA port  212   d . HPI port  214  is a special case, which will be discussed later. A port can make read and write accesses to the resource to which it is connected, through a dedicated bus. 
     This DMA controller meets the need of high rate flow and multi-channel applications such as wireless telephone base stations or cellular handset data traffic. 
     FIG. 4 is a detailed block diagram of the DMA controller of FIG. 3. A channel is made of a source port, a FIFO and a destination port. Six channels are available in the present embodiment, although other embodiments may have alternate numbers of channels. Six channel controllers  310 - 315  control the six channels. All six channels are multiplexed on each port via respective port multiplexers  330 - 333 . Each channel control has a respective FIFO(n). The FIFOs aren&#39;t shared by the channels; each channel has its own FIFO. This allows more independence between transfers. A DMA transfer in channel (n) is made in two steps: the source port performs a read access on a source resource, gets the data and puts it in the channel (n) FIFO; once the data is in the FIFO, the destination port is activated and performs a write access to the destination resource to write the data. Each channel controller includes a separate read address unit RAU( 0 - 5 ) and a separate write address unit WAU( 0 - 5 ). 
     All of the ports operate in parallel. In this embodiment, there are four ports connected the four data storage resources, therefore, four concurrent read/write accesses can be made on the same clock cycle. In order to support this access rate, the address computation and the interleaving are pipelined. Maximum transfer rate for this embodiment with four ports is two words (two reads and two writes) per CPU cycle. This is achieved when sources and destinations are independent. An alternate embodiment may have a larger number of ports with a correspondingly higher maximum transfer rate. 
     A read address bus RA includes seven individual buses for conveying a channel read address from each read address unit RAU( 0 - 5 ) and from the HPI port to each port input mux  330 - 333  in parallel. A write address bus WA includes seven individual buses for conveying a channel write address from each write address unit WAU( 0 - 5 ) and from the HPI port to each port input mux  330 - 333  in parallel. Likewise, a data output bus DO includes seven individual buses for conveying a data output value from each FIFO( 0 - 5 ) and from the HPI port to each port input mux  330 - 333  in parallel. A data input bus DI includes four individual buses for conveying a data input value from each port to each FIFO( 0 - 5 ) and to the HPI port in parallel. 
     A DMA port sends a request to its associated memory to read or write a data item in this memory. A transfer of one word consists of a read request on a source port i following by a write request on destination port j (i can be equal to j). A request is defined by its type (r for read, w for write) and the channel it belongs to. 
     
       
         
           
               
               
               
             
               
                   
                   
               
             
            
               
                   
                 example: 
                 r i  is a read request in channel i 
               
               
                   
                   
                 w j  is a write request in channel j 
               
               
                   
                   
               
            
           
         
       
     
     Each port has its own interleaver  350 - 353  to control the channel multiplexing on the associated port. The interleaver receives read and write requests from each channel, computes which is the next request that must be served, and triggers a port control state machine to serve this request. 
     DMA controller  210  has a request allocator  340 . There can be up to thirteen requests pending on any given clock cycle: six read requests, six write requests, and an HPI request. In order to reduce interleaver complexity, an interleaver in the present embodiment can interleave a maximum of five simultaneous requests at the same time. Request allocator  340  scans the DMA configuration and pending requests signals and selects a maximum of five request signals to send to each interleaver for processing. In an alternate embodiment, the allocator may be divided into separate portions such that each port has allocator circuitry included within the port. In another embodiment, a more complex interleaver may directly receive and schedule all requests provided by all of the channels. 
     Each port has an associated port control block  360 - 363 . These blocks are responsible for initiating the read/write accesses to the memories and peripherals. They implement the transaction access protocol between the memories or peripherals and the DMA. These protocols are the same for SARAM and DARAM. The RHEA bus protocol and the EMIF protocol are different. Thus, each port is tailored to the type of resource to which it is connected. 
     Each channel controller has an associated priority block PRIO( 0 - 5 ). The function of this block is to implement a three level priority scheme available in the DMA: highest priority for HPI, high priority for channels, low priority for channels. 
     Each channel controller has an associated event synchronization block EVENT( 0 - 5 ). Each event synchronization block waits for events that trigger a transfer in its channel. Each block also looks for event drops. 
     Channel FIFOs each have eight stages in this embodiment. FIFO receive the data communicated from a source port to a destination port. They allow the pipelining of DMA transfers and the bursting to/from external memories. Bursts of eight data words are possible in all channels. 
     Interrupt generator  370  generates interrupts to the CPU according to the DMA configuration and state. Each channel has its own associated interrupt signal, dma_nirq( 5 - 0 ). 
     RHEA interface  380  interfaces RHEA bus  130   a  from the RHEA bridge. RHEA interface  380  is used only for CPU reads and writes in the DMA configuration registers. DMA accesses to RHEA peripherals are made through the RHEA port, not through the RHEA interface. 
     Descriptor blocks CFG( 0 - 5 ) are used to control and monitor the status of the DMA transfers. There is one descriptor block per channel. They are read/written via RHEA interface  380 . Descriptor block  320  is used to control and monitor the status of host processor transfers. 
     HPI port  214  allows direct transfers between the HOST and the memory when the host has a higher priority than the DMA channels. This path also supports HOM mode. In HOM mode, the DMA Registers are by-passed. Switching from SAM to HOM requires the DMA HOST channel to be empty before switching. 
     HPI port 
     The HPI port will now be described in more detail. FIG. 5 is a block diagram showing portions of the host port interface of DMA controller  210 . Table 2 summarizes the HPI different modes of operation. In HOM mode, the DMA is totally bypassed when the HPI performs an access to SARAM. Therefore, during HOM mode, portions or all of the DMA controller and CPU  200  can be placed in a low power state without affecting transfers by the host processor. When in SAM mode and the HPI has priority over the DMA channels the DMA is totally bypassed when HPI accesses SARAM or DARAM. This allows a transfer bandwidth of up 20 Mwords/s from MCU to internal memory. When the HPI has the same priority as the DMA channels, all HPI requests are processed through the DMA. 
     
       
         
           
               
             
               
                 TABLE 2 
               
             
            
               
                   
               
               
                 HPI Modes of Operation 
               
            
           
           
               
               
               
               
            
               
                 DMA mode 
                 HPI priority 
                 HPI access 
                 HPI request processing 
               
               
                   
               
               
                 HOM 
                 no matter 
                 SARAM only 
                 DMA is bypassed 
               
               
                 SAM 
                 highest 
                 SARAM 
                 DMA is bypassed 
               
               
                   
                   
                 DARAM 
               
               
                   
                   
                 EMIF 
                 through the DMA 
               
               
                   
                 same as channels 
                 SARAM 
                 through the DMA 
               
               
                   
                   
                 DARAM 
               
               
                   
                   
                 EMIF 
               
               
                   
               
            
           
         
       
     
     A DMA Enable/Disable Control Register (DMEDC)  600  is a 16-bit read/write register accessed via the RHEA bus. It contains the DMA transfer priority and transfer enable control for each DMA channel. A DMA Enable/Disable Control Bit (DE[ 5 : 0 ]) field specifies the DMA enable/disable control for each channel (0=disabled, 1=enabled). The DE[ 5 : 0 ] fields are set to zero upon reset. 
     A Channel priority PRIO[ 5 : 0 ] field defines the priority of each channel: PRIO[i]=0 indicates channel i has a low priority; PRIO[i]=1 indicates channel i has a high priority. An HPI priority HPI[ 1 : 0 ] field defines the priority of the host port in relation to the DMA channels. When HPI[ 1 : 0 ]=10 or 11, the HPI has the HIGHEST priority versus all DMA Channels, and can access on-chip RAM only. Other DMA channels cannot access on-chip RAM. When HPI[ 1 : 0 ]=01, the HPI is sequenced into the DMA channel Time Division Multiplex (TDM) access flow and is treated as a HIGH priority channel. When HPI[ 1 : 0 ]=00, the HPI is integrated in the DMA channel TDM flow and is treated as a LOW priority channel. HPI[ 1 : 0 ]=11 upon reset. 
     Transfers of all channels are Time Division Multiplexed in a round-robin fashion. In a given round-robin queue, each channel is switched to the next channel after its read has been triggered. The low priority channels will be pending as long as high priority channels need to be triggered. Low priority channels are triggered in a round-robin fashion when event synchronized high priority channels are waiting for events and non synchronized high priority channels are completed. 
     Still referring to DMEDC register  600 , a CPU/DMA bus priority bit specifies the priority of CPU  200  with respect to DMA controller  210  when both access the same memory resource. When CPU/DMA=1, CPU  200  busses have priority over DMA  210  busses for all internal and external memory accesses. When CPU/DMA=0, DMA  210  busses have priority over CPU  200  busses for all internal and external memory accesses. 
     When HPI has the highest priority (HPI[ 1 : 0 ]=10 or 11), it has exclusive access to SARAM and DARAM. All the DMA channels involving SARAM or DARAM are stopped. Other DMA channels can continue operation. 
     In HOM mode, transfers to and from the MCU are made through the HPI only. The DMA is bypassed and SARAM access protocol is directly driven by HPI. In the present embodiment, SARAM  220  is 128 k×16 bit words. Sixteen memory banks  650 ( 0 )- 650 ( 15 ) are each 8 k×16. Transfers by the DMA that do not require access to SARAM  220  can go on while the DMA is in HOM mode, if the DMA isn&#39;t idled. 
     HPI priority change block  620  generates signal HPI_direct_access  621  in response to the state of HPI priority HPI[ 1 : 0 ] bits in DMEDC register  600 . Signal  621  is used in HPI mux control logic blocks  610 ,  612  and  614  to enable/disable HPI direct access to SARAM and DARAM according to HPI priority. This signal must change only when all the channels accessing SARAM and DARAM are halted and when there are no more requests pending on the SARAM and DARAM port, to prevent HPI accesses interfering with DMA accesses. Ready signals (not shown) are provided by the ports to indicate when a priority change can be performed by block  620 . 
     HPI priority block and chip select demultiplexer block  630  implements the HPI two priority levels (low, high) when HPI priority is equal to priority of the DMA channels and sends the HPI requests (saram_api_req, daram_api_req, and emi_api_req) to the target ports  212   a-c  in response to the HPI chip select signal cs_HPI. 
     HPI SARAM multiplexers  640  select either address/data signals  641  directly from host port interface  115  or address/data signals  642  from SARAM port  212   a  to provide to SARAM  220  in response to a select signal provided by SARAM mux control block  610 . The data out bus from SARAM is directly connected to the DMA HPI data out bus. The acknowledge signal from SARAM is muxed with other memory acknowledges by ready mux  648 . 
     HPI DARAM multiplexers  644  select either address/data signals  641  directly from host port interface  115  or address/data signals  645  from DARAM port  212   b  to provide to DARAM  222  in response to a select signal provided by DARAM mux control block  612 . The data out bus from DARAM is directly connected to the DMA HPI data out bus. The acknowledge signal from DARAM is muxed with other memory acknowledges by ready mux  648 . 
     SARAM 
     Host accesses to the SARAM are made using HPI interface  115  via HPI port  214  and a DMA channel. As described above, two access modes are possible. In shared access mode (SAM) both the MCU and the DSP may access the SARAM. All accesses are synchronous to the DSP clock and the priority is controlled by DMEDC configuration register  600 . In host only mode (HOM) and host high priority mode, only the MCU can access the SARAM and all accesses are asynchronous to the DSP clock. In this case, the DMA channel is bypassed. In this embodiment, high priority accesses are enabled using the same circuitry as HOM accesses, therefore in the following discussion both type accesses will be referred to as HOM mode accesses. 
     FIG. 6 is a timing diagram illustrating an SARAM memory access in SAM mode. The Figure shows the timing for both a SAM mode read and a SAM mode write. In SAM mode, all requests are made synchronously to DSP clock signal dsp_clk provided by clock circuitry in control block  170 . A request is made by the HPI driving the request signal Areq low. Signal Areq is responsive to the HPI request signal saram_api_req. The address signals Aabus, read/write signal Armw, byte signals Awrbyte etc. are also driven in the same clock cycle. As soon as the request is granted by the arbitration logic, the Aready_out signal is driven active (low) as shown at  800 . 
     For a SAM read, the data is driven on data output bus Adbusout by the SARAM in the second cycle on the low phase of dsp_clk as indicated at  810 . The data is received and latched in the HPI on the following rising edge of dsp_clk at  811 . 
     For a write, the data must be driven by the HPI on the data input bus Adbusin in the second cycle as shown at  820 . 
     FIG. 7 is a timing diagram illustrating a memory access in HOM/high priority mode. As discussed above, in this mode, the DMA is bypassed. Therefore, HOM mode makes a direct link between the HPI interface and the SARAM HPI/DMA port and memory accesses are performed in an asynchronous manner without regard to the clock signal used by DSP  200  and DMA  210 . 
     On system startup, while reset is active, the HPI module will configure the HPI in HOM mode, and load boot code into the SARAM memory. Thus HOM mode accesses must be allowed while reset is active. 
     In HOM/high priority mode, the HPI module has exclusive access to the SARAM. A HOM mode request is initiated by the HPI asserting the chip select signal Acs at  900 . This signal is provided by demux block  630 . This signal is used to enable the SARAM memory core while request signal Areq is the core strobe signal. The core is accessed on the falling edge of Areq, indicated at  910 , for memory reads and writes; thus address bus Aabus, control signals and data input bus Adbusin signals must be valid for a setup time Tsetup before this edge. 
     As no other module can access the SARAM in HOM mode, the ready signal Aready_out will always be granted at  911  and is simply a buffered version of the Areq input. For a read, the data will be valid after access time Tacc after Aready_out goes active. 
     FIG. 8 is a schematic representation of an integrated circuit  1040  incorporating processor  100 . As shown, the integrated circuit includes a plurality of contacts for surface mounting. However, the integrated circuit could include other configurations, for example a plurality of pins on a lower surface of the circuit for mounting in a zero insertion force socket, or indeed any other suitable configuration. 
     FIG. 9 illustrates an exemplary implementation of an example of such an integrated circuit in a mobile telecommunications device, such as a mobile telephone with integrated keyboard  1012  and display  1014 . As shown in FIG. 9, the digital system  10  included in integrated circuit  1040  is connected to the keyboard  1012 , where appropriate via a keyboard adapter (not shown), to the display  1014 , where appropriate via a display adapter (not shown) and to radio frequency (RF) circuitry  1016 . The RF circuitry  1016  is connected to an aerial  1018 . 
     Fabrication of digital system  10  involves multiple steps of implanting various amounts of impurities into a semiconductor substrate and diffusing the impurities to selected depths within the substrate to form transistor devices. Masks are formed to control the placement of the impurities. Multiple layers of conductive material and insulative material are deposited and etched to interconnect the various devices. These steps are performed in a clean room environment. 
     A significant portion of the cost of producing the data processing device involves testing. While in wafer form, individual devices are biased to an operational state and probe tested for basic operational functionality. The wafer is then separated into individual dice which may be sold as bare die or packaged. After packaging, finished parts are biased into an operational state and tested for operational functionality. 
     Digital system  10  contains hardware extensions for advanced debugging features. These assist in the development of an application system. Since these capabilities are part of the core of CPU  200  itself, they are available utilizing only the JTAG interface with extended operating mode extensions. They provide simple, inexpensive, and speed independent access to the core for sophisticated debugging and economical system development, without requiring the costly cabling and access to processor pins required by traditional emulator systems or intruding on system resources. 
     Thus, a digital system is provided with a memory that can be shared by two or more data requesters. Various priority levels of access are provided. In a high priority access mode, the memory is connected directly to one of the requestors, such as a host processor, so that high bandwidth transfers can be performed. 
     As used herein, the terms “applied,” “connected,” and “connection” mean electrically connected, including where additional elements may be in the electrical connection path. “Associated” means a controlling relationship, such as a memory resource that is controlled by an associated port. 
     While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various other embodiments of the invention will be apparent to persons skilled in the art upon reference to this description. For example, the portion of memory selected for HOM mode may be selected using a finer or courser grain than sixteen banks. The size register may be in the form of a ROM that is electrically alterable or mask programmed, for example. The memory banks may operate in different combinations of sync/async; for example, the memory may operate synchronously to the DSP clock in SAM mode and synchronously to the host processor clock in HOM mode. The HOM selection circuits may be in the form of the SARAM multiplexers or may be tri-stated buses, for example. A different number of channel controllers and/or ports may be implemented. Different types of memory resources may be associated with a port by tailoring the port to match the memory resource. 
     It is therefore contemplated that the appended claims will cover any such modifications of the embodiments as fall within the true scope and spirit of the invention.