Patent Publication Number: US-7719305-B2

Title: Signal isolator using micro-transformers

Description:
RELATED APPLICATIONS 
   This application is a continuation-in-part application of U.S. patent application Ser. No. 11/481,997 entitled “SIGNAL ISOLATORS USING MICRO-TRANSFORMERS,” filed on Jul. 6, 2006 which claims priority to U.S. patent application Ser. No. 10/834,959 filed on Apr. 29, 2004, which claims priority to U.S. Provisional Application Ser. No. 60/466,602 filed on Apr. 30, 2003. 

   FIELD OF THE INVENTION 
   The subject invention relates to signal isolators, more particularly digital signal isolators, and even more particularly to digital signal isolators employing transformers to establish an isolation barrier. 
   BACKGROUND OF THE INVENTION 
   In a variety of environments, signals must be transmitted between diverse sources and circuitry using those signals, while maintaining electrical (i.e., galvanic) isolation between the sources and the using circuitry. Isolation may be needed, for example, between microcontrollers, on the one hand, and devices or transducers which use microcontroller output signals, on the other hand. Electrical isolation is intended, inter alia, to prevent extraneous transient signals, including common-mode transients, from inadvertently being processed as status or control information, or to protect the equipment from shock hazards or to permit the equipment on each side of an isolation barrier to be operated at a different supply voltage, among other known objectives and uses. 
   A variety of isolation techniques are known, including the use of optical isolators that convert input electrical signals to light levels or pulses generated by light emitting diodes, and then to receive and convert the light signals back into electrical signals. Isolators also exist which are based upon the use of Hall effect devices, magneto-resistive sensors, capacitive isolators and coil- or transformer-based isolators. 
   Optical isolators, which are probably the most prevalent, present certain well-known limitations. Among other limitations, they require significant space on a card or circuit board, they draw a large current, they do not operate well at high frequencies, and they are very inefficient. They also provide somewhat limited levels of isolation. To achieve greater isolation, optical-electronic isolators have been made with some attempts at providing an electrostatic shield between the optical transmitter and the optical receiver. However, a conductive shield which provides a significant degree of isolation is not sufficiently transparent for use in this application. 
   In the area of non-optical isolation amplifiers for use in digital signaling environments, U.S. Pat. No. 4,748,419 to Somerville, shows the differentiation of an input data signal to create a pair of differential signals that are each transmitted across high-voltage capacitors to create differentiated spike signals for the differential input pair. Circuitry on the other side of the capacitor barrier has a differential amplifier, a pair of converters for comparing the amplified signal against high and low thresholds, and a set/reset flip-flop to restore the spikes created by the capacitors into a logic signal. In such a capacitively-coupled device, however, during a common mode transient event, the capacitors couple high, common-mode energy into the receiving circuit. As the rate of voltage change increases in that common-mode event, the current injected into the receiver increases. This current potentially can damage the receiving circuit and can trigger a faulty detection. Such capacitively coupled circuitry thus couples signals that should be rejected. The patent also mentions, without elaboration, that a transformer with a short R/L time constant can provide an isolation barrier, but such a differential approach is nonetheless undesirable because any mismatch in the non-magnetic (i.e., capacitive) coupling of the windings would cause a common-mode signal to appear as a difference signal. Transformer cost and size may also be a negative factor, and transformers having cores of magnetic materials such as ferrites become inefficient at high frequencies and are not useful for coupling high-speed digital signals. 
   Commonly-owned U.S. Pat. No. 5,952,849 shows another logic isolator which avoids use of optical coupling. This logic isolator exhibits high transient immunity for isolating digital logic signals. 
   A need exists, however, for a less expensive, higher performance digital signal isolator with good dynamic characteristics at high frequencies or speeds. 
   Moreover, needs exist for logic isolators which provide improved low-cost bidirectional signal transmission capabilities and which can be configured for a variety of signal transmission configurations. 
   A need further exists for improved signaling schemes for use in isolators, to permit a logic isolator to be based on a single micro-transformer. 
   These needs are addressed with a logic signal isolator comprising, in a first aspect, a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically (i.e., electrically) isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals. The isolator&#39;s receiver may include circuitry for distinguishing between the received signals corresponding to the transmitted signals of the first type and second type and using the distinguished received signals to reconstitute the received logic signal. The signals of the first type may, for example, comprise multiple pulses in a predetermined pattern and the signals of the second type comprise one or more pulses in a different pattern. The signals of the first type also may comprise pulses of a first duration and the signals of the second type may comprise pulses of a second, distinguishable duration. At least one of the signals of the first or the second type also may comprise at least one burst. If both comprise bursts, they may be at different frequencies or be for different durations. 
   The transmitter circuit may be on a first substrate and the receiver may be on a second substrate electrically isolated from the first substrate. 
   The primary winding and the secondary winding desirably may be substantially planar windings arrange in a stacked arrangement with at least one of the windings substantially in or on one of the substrates. The primary winding then may be a bottom winding (closer to the substrate) and the secondary winding may be a top winding (further from the substrate). When the primary winding is a bottom winding, the isolator may further include a compensation network connected to the top winding for damping its response. Alternatively, the primary winding may be a top winding and the secondary winding may be a bottom winding. 
   According to another aspect of the invention, a bi-directional isolator is provided by including a second transmitter connected to drive said secondary winding in response to a second received logic signal, such that in response to a first type of edge in the second received logic signal, a signal of a third predetermined type is supplied to the secondary winding and in response to a second type of edge in the second received logic signal, a signal of a fourth predetermined type is supplied to said secondary winding, the secondary winding and the second transmitter being referenced to the second ground; and the primary winding being referenced to the first ground and said primary winding supplying to a second receiver circuit signals received in correspondence to the signals provided to the secondary winding, the second receiver reconstructing the second received logic signal. The isolator&#39;s second receiver may include circuitry for distinguishing between the signals received from the primary winding and using the distinguished received signals to reconstitute the second received logic signal. The signals from the first transmitter and the second transmitter may be similar or different. 
   According to another aspect, a digital logic isolator comprises a transformer having a primary winding referenced to a first ground and a secondary winding referenced to a second ground isolated from the first ground, means for providing to the primary winding signals of a first type in response to transitions of a first type in an input logic signal, means for providing to the primary winding signals of a second type different from the signals of the first type in response to transitions of a second type in the input logic signal, and means for receiving from the secondary winding signals corresponding to the signals of the first and second types and for reconstituting the input logic signal from them. 
   According to still another aspect of the invention, a method of providing an isolated logic signal output in response to a logic signal input comprises providing a transformer having a primary winding referenced to a first ground and a secondary winding referenced to a second ground isolated from the first ground, providing to the primary winding signals of a first type in response to transitions of a first type in the input logic signal, providing to the primary winding signals of a second type different from the signals of the first type in response to transitions of a second type in the input logic signal, and receiving from the secondary winding signals corresponding to the signals of the first and second types and reconstituting the input logic signal from them. 
   The signals of a first type may comprise multiple pulses, the signals of the second type may comprise a single pulse and reconstituting the input logic signal may comprise distinguishing between the signals corresponding to said multiple pulses and the signals corresponding to said single pulses so as to provide an output signal reconstituting the transitions in the input logic signal. The signals of a first type or the signals of a second type comprise a burst. If both the signals of a first type and the signals of a second type comprise bursts, they may be distinguishable from each other by frequency, duration or other characteristic. A signal of the first type alternatively may comprise a pulse of a first duration and a signal of the second type may comprise a pulse of a second duration different from the first duration and distinguishable therefrom; and reconstituting the input logic signal may comprise distinguishing between received signals corresponding to the pulses of a first duration and the pulses of a second duration so as to provide an output signal reconstituting the transitions in the input logic signal. 
   According to another aspect of the invention, a logic isolator comprises a micro-transformer comprising, on a substrate, vertically stacked, a bottom winding and a top winding disposed over and insulated from the bottom winding, with a damping network connected across the top winding. A transmitter circuit receives a logic input signal and drives a signal to said bottom winding; and a receiving circuit is connected to receive from the top winding a signal corresponding to the signal driving the bottom winding and generates an output comprising a reconstituted logic input signal. 
   According to still another aspect, a logic isolator comprises a micro-transformer having, on a substrate, vertically stacked, a bottom winding and a top winding disposed over and insulated from the bottom winding; a damping network connected across the top winding; a transmitter circuit receiving a logic input signal and providing a transformer driving signal; a receiving circuit connected to receive from the transformer a signal corresponding to the driving signal and generating an output comprising a reconstituted logic input signal; and means for programming the isolator by coupling the driving signal to a selected one of the windings and coupling the receiving circuit to the other one of the windings. In such an isolator, the means for programming may comprise a fusible connection(s) programmed by blowing open a conductive path(s). The means for programming alternatively may comprise bond wires provided between the transformer windings on the one hand and the transmitter and receiving circuits, on the other hand. As a further alternative, the means for programming comprises programmable circuitry configurable to connect the transmitter circuit to either the top winding or the bottom winding and to connect the receiving circuit to the other winding. The programmable circuitry may include programmable switching circuits and a memory containing programming to control the switching circuits. The memory may be read-only memory. 
   According to yet another aspect, a logic isolator comprises a micro-transformer comprising, on a substrate, vertically stacked, a bottom winding and a top winding disposed over and insulated from the bottom winding; a damping network connected across the top winding; a first module coupled to the top winding capable of either receiving a logic input signal and providing a transformer driving signal or receiving from the transformer a signal corresponding to the driving signal and generating an output comprising a reconstituted logic input signal; a second module coupled to the bottom winding capable of either receiving a logic input signal and providing a transformer driving signal or receiving from the transformer a signal corresponding to the driving signal and generating an output comprising a reconstituted logic input signal; and means for programming the isolator such that the first module operates in the transformer drive mode while the second circuit operates in the receive mode or that the first module operates in the receive mode while the second module operates in the transformer drive mode. Various alternatives may be used as the means for programming. Such means may comprise, for example, at least one fusible connection programmed by blowing open at least one conductive path. As another example, the means for programming may comprise one or more bond wires provided between the transformer windings on the one hand and the first and second modules, on the other hand. The means for programming also may comprise programmable circuitry configurable to connect the first module to either the top winding or the bottom winding and to connect the second module to the other winding. Such programmable circuitry may include programmable switching circuits and a memory containing programming to control the switching circuits. The memory may include a read-only memory. 
   According to still another aspect, a dual-channel, bi-directional isolator comprises first and second micro-transformers arranged on a first substrate, each transformer having a top winding and a bottom winding. A first transmitter circuit is connected to drive the bottom winding of the first transformer; a second transmitter circuit is connected to drive the top winding of the second transformer. A first receiver circuit is connected to receive signals from the bottom winding of the second transformer. A second receiver circuit is connected to receive signals from the top winding of the first transformer. Preferably, but not necessarily, the first transmitter circuit and first receiver circuit are on the first substrate, and the second transmitter circuit and second receiver circuit are on a second substrate which is electrically isolated from the first substrate. 
   Yet another aspect of the invention is a single channel bi-directional isolator comprising a micro-transformer arranged on a first substrate, the transformer having a top winding and a bottom winding; a first transmitter circuit connected to drive the bottom winding; a second transmitter circuit connected to drive the top winding; a first receiver circuit connected to receive signals from the top winding; a second receiver circuit connected to receive signals from the bottom winding; and the first and second transmitter circuits transmitting so as to avoid interfering with each other. Preferably, but not necessarily, the first transmitter circuit and the second receiver circuit are on the first substrate and the second transmitter circuit and the first receiver circuit are on a second substrate which is electrically isolated from the first substrate. 
   According to still another aspect, there is provided a delay element for use in pulse generating circuits for generating pulses usable, for example, to drive a transformer as above-described. The delay element is useful for generating a delay interval, and therefore a pulse duration, of a length that is substantially independent of the supply voltage—i.e., is insensitive to variations in supply voltage. The delay element comprises first and second current sources which supply currents I 1  and I 2 , respectively, in parallel, and a switching element. The sum of currents I 1  and I 2  is directly proportional to the supply voltage, and a threshold of the switching element is a predetermined portion of the supply voltage. The delay element may further include a capacitor of capacitance C, connected to a node in common with the input of the switching element and the current sources, chargeable by the current sources. Preferably, the first current source comprises a single transistor and a resistor, the resistor, of resistance value R, having one end connected to the supply voltage and the other end connected to said transistor. Current I 1 =(VDD−VT)/R, where the transistor is a MOS transistor, VT is the threshold voltage of the MOS transistor, VDD is the supply voltage, I 2 =VT/R, I 1 +I 2 =VDD/R. The delay interval is then approximately 0.5 RC if the switching threshold of the switching element is set to be VDD/2, and is relatively insensitive to changes in VDD. Such a delay element may be used in conventional pulse generating circuits that rely upon use of a delay element. 
   The subject invention features a logic signal isolator comprising a micro-transformer with a primary winding and a secondary winding, A transmitter circuit drives the primary winding in response to a received input logic signal such that, in response to a first type of edge in the logic signal, at least a first amplitude signal is supplied to the primary winding and, in response to a second type of edge in the logic signal, a second different amplitude signal is supplied to the primary winding. A receiver circuit receives corresponding first amplitude and second amplitude signals from the secondary winding and reconstructs the received logic input signal from the received signals. 
   In one example, the transmitter circuit includes a first differentiator for generating a first pulse in response to the first type of edge and a second differentiator for generating a second pulse in response to the second type of edge. The transmitter may include a gate connected to both differentiators and responsive to a first voltage for generating the first amplitude signal and responsive to a second voltage for generating the second amplitude signal. The transmitter circuit may further include a refresh circuit for periodically sending a refresh signal across the micro-transformer. 
   In one example, the receiver circuit includes a first threshold detector connected to the secondary winding generating pulses in response to both the first amplitude and second amplitude signals and a second threshold detector connected to the secondary winding generating a pulse in response to the first amplitude signal. The receiver circuit may further include a gate responsive to both threshold detectors. The preferred gate is a NOR gate and produces a high signal only when no pulses are present. The receiver circuit may also include a watchdog circuit. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     Other objects, features and advantages will occur to those skilled in the art from the following description of a preferred embodiment and the accompanying drawings, in which: 
     The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. In the drawings: 
       FIG. 1  is a simplified schematic circuit diagram of a transformer-based isolator according to the prior art; 
       FIG. 2  is a simplified schematic circuit diagram of a glitch filter for use in an isolator according to the invention; 
       FIG. 3  is a set of waveforms for the circuit of  FIG. 2 ; 
       FIG. 4  is a simplified schematic circuit diagram of a first embodiment of a transformer-based isolator embodying aspects taught herein; 
       FIG. 5  is a set of waveforms for the circuit of  FIG. 4 ; 
       FIG. 6  is a simplified schematic circuit diagram of a second embodiment of a transformer-based isolator embodying aspects taught herein. 
       FIG. 7  is a waveform depicting two distinguishable pulses of different pulse width, such as may be used in an alternative embodiment of an isolator as taught herein; 
       FIG. 8  is a diagrammatic illustration of an isolator according to some aspects of the invention, wherein the primary winding is a top winding; 
       FIG. 9  is an illustration of input and output waveforms when driving a micro-transformer of the type preferably employed in implementing embodiments of the isolators taught herein, particularly illustrating the difference between driving top and bottom transformer windings; 
       FIG. 10  is a diagrammatic illustration of an isolator according to some aspects of the invention, wherein the primary winding is a bottom winding; 
       FIG. 11  is a diagrammatic illustration of a bi-directional dual channel isolator such as may be implemented using the teachings herein; 
       FIG. 12  is a simplified schematic circuit diagram for a supply-independent delay element for use in a pulse generator (transmitter) in isolators such as are taught herein; 
       FIGS. 13 and 14  are simplified schematic circuit diagrams for current sources for use in the delay element of  FIG. 12 ; 
       FIG. 15  is a highly schematic block diagram showing an embodiment of a logic signal isolator in accordance with the subject invention; 
       FIGS. 16A-16D  are schematic timing diagrams showing the various signals processed and produced by the logic isolator of  FIG. 15 ; 
       FIG. 17  is a schematic circuit diagram showing an example of a logic signal isolator in accordance with the subject invention; and 
       FIG. 18  is a schematic circuit diagram of an example of a logic gate used in the circuit of  FIG. 17 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Aside from the preferred embodiment or embodiments disclosed below, this invention is capable of other embodiments and of being practiced or being carried out in various ways. Thus, it is to be understood that the invention is not limited in its application to the details of construction and the arrangements of components set forth in the following description or illustrated in the drawings. If only one embodiment is described herein, the claims hereof are not to be limited to that embodiment. Moreover, the claims hereof are not to be read restrictively unless there is clear and convincing evidence manifesting a certain exclusion, restriction, or disclaimer. 
   Although specific features of the invention are shown in some drawings and not in others, this is for convenience only as each feature may be combined with any or all of the other features in accordance with the invention. The words “including”, “comprising”, “having”, and “with” as used herein are to be interpreted broadly and comprehensively and are not limited to any physical interconnection. Moreover, any embodiments disclosed in the subject application are not to be taken as the only possible embodiments. Other embodiments will occur to those skilled in the art and are within the following claims. 
   In addition, any amendment presented during the prosecution of the patent application for this patent is not a disclaimer of any claim element presented in the application as filed: those skilled in the art cannot reasonably be expected to draft a claim that would literally encompass all possible equivalents, many equivalents will be unforeseeable at the time of the amendment and are beyond a fair interpretation of what is to be surrendered (if anything), the rationale underlying the amendment may bear no more than a tangential relation to many equivalents, and/or there are many other reasons the applicant can not be expected to describe certain insubstantial substitutes for any claim element amended. 
   This invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways. Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having,” “containing”, “involving”, and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. 
   Micro-transformer based digital isolators have been developed in recent years by applicants and their colleagues. This genus of digital isolators shows dramatic improvements over traditional opto-isolators in terms of speed, power, edge symmetry and cost. The transmission methods employed in these micro-transformer based digital isolators fall into two main categories. The first category is based on edge detection; the second, on level detection. Those designs that are based on edge detection have the advantage of lower power, lower pulse width distortion and higher common mode transient immunity over those based on level detection. Typically, implementations based on edge detection require two transmitters, two receivers and two transformers to make a single channel isolator. A need exists for a less expensive design. 
   As shown herein, a digital isolator may be formed, which is based on a micro-transformer-created isolation barrier, using only a single transmitter, a single receiver and a single transmitter. This approach dramatically reduces the die cost while still preserving the merits of edge detection. Further, in a vertically stacked arrangement of micro-transformer windings, the present invention enables bi-directional signal transfer. That is, the signal can be transferred from the top coil to the bottom coil or from the bottom coil to the top coil. This capability can be leveraged to make bi-directional, multi-channel signal isolators or to program the channel direction of a single data channel. This invention preserves the main advantages of high speed, low power, high common-mode immunity and adds to them a reduction in size and enhanced ease of integration. 
   By the term “micro-transformer,” there is meant transformer formed in, partially in, or on, a semiconductor substrate of flat, parallel conductive windings and having no magnetic core. These transformers are also referred to as “air-core” transformers though there actually will be more than air between the windings, typically one or more layers of dielectric materials. 
   A block diagram of a typical prior art example of a transformer-based isolator for digital signals is shown in  FIG. 1 . There, the isolator  100  comprises (after an optional, though preferable, glitch filter  101 ), a pair of edge detectors  102  and  104 , edge detector  104  being driven by the logical complement to the signal driving edge detector  102 , by means of inverter  106 . The output of edge detector  102  provides a pulse, the SET_HI signal to the primary winding of transformer  108  responsive to detection of a low-to-high transition (i.e., a leading edge) in the output of the glitch filter  101 . The secondary winding of transformer  108  is connected to the set input of a flip-flop  110 . The output of edge detector  104  is a pulse named the SET_LO signal which is supplied to the primary winding  120 A of transformer  120  responsive to detection of a high-to-low transition (i.e., a falling edge) in the output of the glitch filter  101 . The secondary winding of transformer  120  is supplied to the reset input of flip-flop  110 . Typically, though not shown for the sake of avoiding obfuscation, the connection from each transformer secondary winding to the flip-flop  110  is not direct, but is made through a Schmitt trigger or other waveform-shaping circuitry intended to provide clean, fast transitions to the flip-flop. 
   Note that the primary windings  108 A and  120 A of transformers  108  and  120 , respectively, as well as the glitch filter and the two edge detectors, are connected (referenced) to a first electrical ground, GNDA, while the secondary windings  108 A and  120 B, together with the flip-flop  110 , are referenced to a second electrical ground, GNDB, which is isolated from the first ground. 
   The outputs of the edge detectors  102  and  104  comprise encoded leading edge and falling edge indicators. These indicators may be in the form of pulses, short bursts, or any periodic signal. So, the edge detectors may be monostable multivibrators, differentiators or other suitable circuits. In the illustration, a single pulse of about ins duration is shown as an edge indicator signal. 
   Glitch filter  101  may be of any suitable design. A brick wall filter is typical. Typically, it should have a bandwidth larger than that to which the edge detectors respond.  FIG. 2  provides a schematic circuit diagram for a usable filter, corresponding timing diagrams showing the waveforms at the input, nodes A-D and the filter output being provided in  FIG. 3 . The filtered pulse width is given approximately by CVthreshold/i, where Vthreshold is the threshold voltage of the Schmitt triggers  22  and  24  and i is the current from current sources  26 ,  28 . 
   Turning now to  FIG. 4 , a basic embodiment for practicing the present invention is shown.  FIG. 4  illustrates a logic signal isolator  200  in which encoded leading and falling edge indicators from a pair of edge detectors  202  and  204  (corresponding to edge detectors  102  and  104  of  FIG. 1 ) are sent to a single transformer  210 . Unlike the above-discussed design, however, the leading edge and falling edge indicators are encoded as different, distinguishable signals. That is, the SET_HI signal output from leading edge detector  202  is distinct from the SET_LO signal output from falling edge detector  204 . The receiving side circuitry connected to the secondary winding  210 B of transformer  210  (again, typically via a Schmitt trigger or other suitable wave-shaping circuit, not show) then reconstructs the logic edges based on distinguishing between those two signals. 
   An example is illustrated wherein edge detector  202  produces two consecutive short pulses  232  and  234  as a leading edge indicator and edge detector  204  produces only a single pulse  236  as a falling edge indicator. The pulses  232  and  234  preferably have a known, fixed spacing between them. If transformer  210  is a high bandwidth micro-transformer, the pulse widths may be as narrow as 1 ns or even less. The outputs of edge detectors  202  and  204  are combined by and OR gate  240 , to drive the primary winding  210 A of the transformer. The pulses cannot be so short or weak in amplitude that the OR gate will not respond properly. 
   Of course, the concept is to use two different, distinguishable signals. They need not be a single pulse and a double pulse. For example, a narrow pulse (e.g., 1 ns) could be used as one edge indicator and a wider pulse (e.g., 2 ns) could be used as the other edge indicator. It is only necessary that the receiver be able to distinguish the two signals. The concept lends itself to the use of other distinguishable signals but at the same time, one would not wish to use an unnecessarily complicated arrangement or one which would add any significant delay in signal processing. For signals other than those illustrated, it might be necessary to replace OR gate  240  with other elements that would effectively combine the outputs of the edge detectors into a single signal for driving the transformer. 
   The two pulses in the SET_HI signal have a known, fixed spacing between them. The total duration of the two pulses and the intervening gap between them in the SET-HI signal, if sufficiently short with respect to the shortest interval between two leading edges in the input signal, will permit resolution between the SET-HI and SET_LO pulses. 
   A receiver circuit  250 , connected to secondary winding  210 B, recovers the output of transformer  210 , distinguishes between the SET_HI and SET_LO pulses, and reconstructs the input logic signal as a data out signal. More specifically, the received pulses at node  252  clock a D-type flip-flop  254  and also act as the input to a non-retriggerable edge-triggered mono-stable multivibrator  256 . The multivibrator  256  puts out a pulse on line  258  that is of duration at least as long as the combination of pulse  232  and the interval between pulse  232  and pulse  234  in the SET_HI signal. If the two pulses  232  and  234  are each approximately 1 ns in duration and the interval between them is of like duration, then the pulse on line  258  should be at least about 2 ns long; 3 ns is used in this example to allow some “hold” time to facilitate clocking of flip-flop  254 . Line  258  connects to the D input of flip-flop  254 , to the reset input of that flip-flop and to the input of inverter  262 . The output of inverter  262  is connected to the input of an edge detector  264  and the QB output (the complementary output) of flip-flop  254  is connected to the input of another edge detector  266 . The output of edge detector  264  is connected to one input of each of AND gates  272  and  274 . The output of edge detector  266  is connected to the second input of AND gate  272  and through inverter  276  to the second input of AND gate  274 . In turn, the output of AND gate  272  is connected to the set input of set/reset flip-flop  278  and the output of AND gate  274  is connected to the reset input of flip-flop  278 . The DATA OUT signal, corresponding to an isolated and slightly delayed version of the DATA IN signal received by the glitch filter, appears at the Q output of flip-flop  278 . 
   The operation of this circuit will now be explained with reference to the waveforms of  FIG. 5 . Assume that the DATA IN input has the waveform  302 . At node  252 , the COIL signal is received. Pulses  232  and  234  have been generated by edge detector (i.e., transmitter)  202  in response to the leading, positive-going edge of the input signal and pulse  236  has been generated by edge detector  204  in response to the negative-going, trailing edge of the input signal. The edge-triggered mono-stable (ETMS) multivibrator  256  generates an output waveform on line  258  as shown at ETMS. In the ETMS signal, the leading edge of pulse  232  causes the pulse  304  to be generated. The multivibrator  256  does not do anything in response to the falling edge of pulse  232  or to either edge of the second pulse  234 . Only after pulse  304  has been output is the multivibrator  256  able to respond to a new input, which it does when it receives the leading edge of pulse  236 . Detection of the leading edge of pulse  236  causes the outputting of pulse  306 . 
   The second of the two initial pulses, pulse  234 , is detected and the output signal is formed as follows. When the first pulse  232  clocks the flip-flop  254 , the D input of the flip-flop still sees a low output from the edge-triggered mono-stable multivibrator on line  258 . That means the QB output of the flip-flop  254  is set to a high value and the Q output is set to a low value. When the second pulse  234  is received and clocks flip-flop  254 , the output of the edge-triggered mono-stable is now high and the QB output of flip-flop  254  transitions to a low value, meaning that the Q output of flip-flop  254  goes high as at the leading edge of the pulse  308  in the “2 Pulse Detect” signal on  FIG. 5 . This H-L edge is sensed by edge detector  266 , which produces a pulse  310  to the second (bottom) input of AND gate  272 . The output of the edge-triggered mono-stable is also supplied to the input of inverter  262 . So, after the propagation delay through inverter  262 , edge detector  264  sees a high-to-low transition (edge) at the output of inverter  262  and responsively generates a positive-going pulse  312  to the first (top) input of AND gate  272  and to a first (top) input of AND gate  274 . Inverter  262  is designed to have a propagation delay that is substantially equal to that from the D input to the QB output of flip-flop  254 . Hence, edge detectors  264  and  266  produce substantially concurrent output pulses  310  and  312  to AND gate  272 . As a result, the output  314  of AND gate  272  goes from low to high at the same time and sets the set (S) input of the SR flip-flop  278 ; and the Q output thereof, being the DATA OUT signal, goes high. As the second (bottom) input of AND gate  274  is responsive to the output of edge detector  266  through inverter  276 , the first and second pulses have no impact on the output of AND gate  274  and do not affect the output of flip-flop  278 . However, when third pulse  236  triggers edge-triggered mono-stable  256 , to produce its second output pulse  306 , this results as stated above, in the generation of a pulse at the output of edge detector  264  upon the falling edge of the mono-stable output pulse. The second input of AND gate  274  from inverter  276  will be high at this time because the only time it is low is when the output of edge detector  266  generates the second pulse detection signal  308 . Therefore, the reset (R) input of flip-flop  278  sees the output pulse  316  from AND gate  274  upon the falling edge of the output pulse from edge detector  264  (plus propagation delay), and flip-flop  278  is reset and the DATA OUT signal goes low. 
   An alternative embodiment  200 ′ for the pulse receiver circuitry is shown in  FIG. 6 . Edge detectors  264 ,  266  and gates  272 ,  274  and  276  have been eliminated and the output flip-flop  278 ′ is changed from a set-reset flip-flop to a D-type flip-flop. Again, the first pulse  232  clocks flip-flop  254  before the edge-triggered mono-stable  256  has generated an output pulse on the D input of flip-flop  278 ′. Therefore, the Q output of flip-flop  254  assumes a low state. When the second pulse  234  clocks flip-flop  254 , the D input thereof now sees the output pulse  304  from the edge-triggered mono-stable and the Q output of flip-flop  254  transitions to a high value. The falling edge of the mono-stable pulse  304  is coupled to the clock input of flip-flop  278 ′ through inverter  262 , and clocks flip-flop  278 ′; as a result, the high value from the Q output of flip-flop  254  supplies a high value on the Q output of flip-flop  278 ′, and the DATA OUT signal. The falling edge of the mono-stable output pulses also reset flip-flop  254  via its RB (i.e., R complement) input. The output flip-flop  278 ′ is next clocked, again, by the falling edge of the output pulse from the mono-stable, being edge  306 B, of pulse  306  generated in response to the third pulse,  236 , on the transformer. At the time of edge  306 B, flip-flop  254  has been reset to have a low output and the output of flip-flop  278 ′ accordingly goes low. 
   To assure proper operating states, a reset signal termed PWReset_B is supplied to the reset (complement) input of flip-flop  278 ′ and causes flip-flop  278 ′ to be reset whenever device power is reset. 
   An alternative signaling arrangement, mentioned above, is shown in  FIG. 7 . There, instead of using two pulses to indicate a rising edge and one pulse to indicate a falling edge in the input signal, a double-width pulse  350  is used to indicate a rising edge and a single-width pulse  360  is used to indicate a falling edge. Those skilled in the art of electrical engineering will readily be able to device logic circuitry to discriminate between a pulse of single width duration Δ and a pulse of double width duration  2 Δ. 
   An exemplary physical implementation for an isolator according to the present invention, capable of being packaged in an integrated circuit form, is shown in  FIG. 8 . There, a transmitter (or driver) circuit  802  is formed on a first substrate  804 . A transformer comprising a first winding  806 A and a second winding  806 B is formed on a second substrate  808 , along with a receiver circuit  810 . Wire leads  812 A,  812 B from bond pads  814 A and  814 B on substrate  804  connect the driver output to the primary winding  806 A of the transformer. As shown there, obviously, the primary (driving) coil winding is the top coil  806 A and the secondary (receiving) coil winding is the bottom coil  806 B. It is important to note that the two coils, even if made in the same dimensions and geometry, will exhibit different quality factor Q, because the bottom coil has higher capacitance to substrate  808 . 
   Referring to  FIG. 9A , when an idealized square voltage pulse  902  drives the top winding  904  of such a transformer, the voltage received at the bottom winding  906  will exhibit a waveform something like  908 . By contrast, if the bottom coil  906  is driven by the idealized pulse  912  as shown in  FIG. 9B , then the received voltage waveform at the top coil  904  will typically be as shown at  914 , exhibiting ringing due to the fact that the top coil has a higher Q than the bottom coil. This undesired ringing makes it difficult to use the transformer for bi-directional signal transfer. However, bi-directional signal transfer is desired in at least some embodiments of the present invention and it is possible to establish a greater degree of symmetry as shown in  FIG. 9C , by adding a damping network  916  on the receiving top coil. The damping network consists of a resistor  922  and a capacitor  924  in series. Damping with a resistor only would dramatically reduce the received signal and typically would not be acceptable. The capacitor  924  has very low impedance at high frequencies and blocks DC current through the damping resistor, providing the desired response characteristics. Note that with the damping network, the received waveform  926  from the top coil is substantially the same as the received waveform from the bottom coil as shown at  908  in  FIG. 9A . 
   Through use of such a damping network, the edge-detection based isolator above described can be implemented as pictured in  FIG. 10 . There, it can be seen that the primary coil is the bottom coil  906  instead of the top coil  904 . 
   A bi-directional dual isolator arrangement as shown in  FIG. 11  is thus enabled. This bi-directional isolator has a pair of stacked transformers arranged side by side. A first transformer is formed by the windings  1102 A and  1102 B, while a second transformer is formed by the windings  1104 A and  1104 B. Only one substrate  1106  carries the transformer structure because the primary winding now can be the top coil or bottom coil of a transformer. Absent this possibility, each of the two substrates  1106  and  1108  would need to have an isolated transformer structure thereon and the product would be considerably more expensive to make. 
   Alternatively, it is possible to make a single channel bi-directional isolator having only one vertically stacked transformer, with one transmitter driving the transformer while the other transmitter is idled. Synchronization of the transmissions in two directions can be programmed externally or through proper command encoding/decoding. 
   For some applications, where bandwidth and data rate are not paramount considerations, instead of using pulses to drive the transformer primaries, other signals such as analog bursts at predetermined frequencies and of predetermined durations may be employed. In such situations, signals can be transmitted bi-directionally concurrently through a single transformer. 
   Advantageously, single- and multiple-channel isolators can be manufactured so that the selection of configuration (i.e., which channels transmit in which directions) can be made in final assembly and test steps of production. That lowers product cost by allowing one product core to be made and sold for multiple configurations. The designs shown above lend themselves to this approach in one of two ways. In a first approach, a logic isolator comprises a micro-transformer having, on a substrate, vertically stacked, a bottom winding and a top winding disposed over and insulated from the bottom winding; a damping network connected across the top winding; a transmitter circuit receiving a logic input signal and providing a transformer driving signal; a receiving circuit connected to receive from the transformer a signal corresponding to the driving signal and generating an output comprising a reconstituted logic input signal; and means for programming the isolator by coupling the driving signal to a selected one of the windings and coupling the receiving circuit to the other one of the windings. In general, the programming would have to be effected before final testing of the isolator in order to maintain isolation between input and output. In such an isolator, the means for programming may, for example, comprise a fusible connection(s) programmed by blowing open a conductive path(s). The means for programming alternatively may comprise bond wires provided between the transformer windings on the one hand and the transmitter and receiving circuits, on the other hand. In either instance, the isolator cannot be tested until isolation-destroying paths are blown open or isolation-destroying bond wires are removed (if there had been any); of course, bond wires could selectively be installed as the last step in manufacture, before testing. As a further alternative, the means for programming may comprise programmable circuitry configurable to connect the transmitter circuit to either the top winding or the bottom winding and to connect the receiving circuit to the other winding. Again, however, only one set of valid connections can be established if input-output isolation is to be maintained. The programmable circuitry may include programmable switching circuits and a memory containing programming to control the switching circuits. The memory may be read-only memory. A second approach may be based on providing modules, each having both a transformer-driving circuit (i.e., transmitter) and a receiver circuit, such that the module is configured to operate only as a driving circuit or only as a receiving circuit, configuring done at final assembly or by the user. In this approach, a logic isolator comprises a micro-transformer having, on a substrate, vertically stacked, a bottom winding and a top winding disposed over and insulated from the bottom winding; a damping network connected across the top winding; a first module coupled to the top winding capable of either receiving a logic input signal and providing a transformer driving signal or receiving from the transformer a signal corresponding to the driving signal and generating an output comprising a reconstituted logic input signal; a second module coupled to the bottom winding capable of either receiving a logic input signal and providing a transformer driving signal or receiving from the transformer a signal corresponding to the driving signal and generating an output comprising a reconstituted logic input signal; and means for programming the isolator such that the first module operates in the transformer drive mode while the second circuit operates in the receive mode or that the first module operates in the receive mode while the second module operates in the transformer drive mode. Various alternatives may be used as the means for programming. Such means may comprise, for example, at least one fusible connection programmed by blowing open at least one conductive path. As another example, the means for programming may comprise one or more bond wires provided between the transformer windings on the one hand and the first and second modules, on the other hand. The means for programming also may comprise programmable circuitry configurable to connect the first module to either the top winding or the bottom winding and to connect the second module to the other winding. Such programmable circuitry may include programmable switching circuits and a memory containing programming to control the switching circuits. The memory may include a read-only memory. 
   Utilizing these approaches, a dual-channel, bi-directional isolator comprises first and second micro-transformers arranged on a first substrate, each transformer having a top winding and a bottom winding. A first transmitter circuit is connected to drive the bottom winding of the first transformer; a second transmitter circuit is connected to drive the top winding of the second transformer. A first receiver circuit is connected to receive signals from the bottom winding of the second transformer. A second receiver circuit is connected to receive signals from the top winding of the first transformer. Preferably, but not necessarily, the first transmitter circuit and first receiver circuit are on the first substrate, and the second transmitter circuit and second receiver circuit are on a second substrate which is electrically isolated from the first substrate. 
   Similarly, a single channel bi-directional isolator comprising a micro-transformer arranged on a first substrate, the transformer having a top winding and a bottom winding; a first transmitter circuit connected to drive the bottom winding; a second transmitter circuit connected to drive the top winding; a first receiver circuit connected to receive signals from the top winding; a second receiver circuit connected to receive signals from the bottom winding; and the first and second transmitter circuits transmitting so as to avoid interfering with each other. Preferably, but not necessarily, the first transmitter circuit and the second receiver circuit are on the first substrate and the second transmitter circuit and the first receiver circuit are on a second substrate which is electrically isolated from the first substrate. 
   Such isolators typically have to work with a wide range of supply voltage. If such a characteristic is desired, and the driving signals are to be pulses, then it is also necessary that the transmitters (i.e., edge detectors or pulse generators of whatever nature) be able to generate pulses of precise, voltage-independent pulse width. Methods to generate such voltage-independent pulse widths will now be discussed. A delay element typically is required in such pulse generators. And as illustrated schematically in  FIG. 12 , a delay element  1200  comprises two current sources  1202  and  1204  which supply currents I 1  and I 2 , respectively, one capacitor, C, and one switching element such as an inverter or a Schmitt trigger  1206 . The sum of currents I 1  and I 2  is such that it is directly proportional to the supply voltage, and the switching threshold is half or some other constant portion of the supply voltage. A simplified example of a current source  1202  for generating current I 1  is shown in  FIG. 13 . There, current source  1202  comprises a single transistor  1212  and a resistor R. The resistor R has one end connected to the supply voltage VDD and the other end connected to the drain of transistor  1212 . 
   Current I 1 =(VDD−VT)/R, where VT is the threshold voltage of the MOS transistor  1212 . Current I 2 =VT/R, I 1 +I 2 =VDD/R. Consequently, the delay time will be 0.5 RC if the switching threshold is set to be VDD/2. Current source  1204  for generating current I 2  can be easily implemented. For example, a simplified schematic circuit diagram for such a current source is shown in  FIG. 14 . Transistor  1214  imposes the voltage VT across resistor R, inducing current I 2  and that current is mirrored in the drain path of transistor  1214 . 
   The delay element  1200  can be easily used to generate pulses whose width is independent of the supply voltage. 
   Of course, the illustrated design need not be used to form the required current source. Any design can be used that will produce a supply-independent pulse width. In the examples shown, this is achieved by adding a first current that is proportional to the supply voltage to a second current that is inversely proportional to the supply voltage. Other approaches are not ruled out. 
   In one embodiment, a driver or transmitter circuit  2000 ,  FIG. 15  is responsive to a first type of edge, e.g., a rising edge  2004   a ,  FIG. 16A  of an input signal and generates a first high amplitude signal  2006   a ,  FIG. 16B  supplied to the primary winding of transformer  2002 ,  FIG. 15 . In response to falling edge  2004   b ,  FIG. 16A  of the input signal, driver circuit  2000 ,  FIG. 15  generates lower amplitude signal  2006   b ,  FIG. 16B  supplied to the primary winding of the transformer. 
   Receiver circuit  2008 ,  FIG. 15  receives, as shown  FIG. 16C , corresponding first high and second low amplitude signals  2006   a ′ and  2006   b ′ from the secondary winding and reconstructs the logic input signal as shown in  FIG. 16D  as an output of the signal isolator. 
   In one particular example, driver circuit  2000  is configured as shown in  FIG. 17 . Differentiator  2010   a  generates pulse  2012   a  in response to rising edge  2004   a  of the input signal and differentiator  2010   b  generates a pulse  2012   b  in response to falling edge  2004   b  of the input signal. OR gate  2014  is responsive to a high voltage V 1  and to a low voltage V 2 . In response to pulse  2012   a  and high voltage V 1 , gate  2014  generates higher amplitude pulse  2006   a . In response to pulse  2012   b  and lower voltage source V 2 , gate  2014  generates lower amplitude pulse  2006   b . Pulses  2006   a  and  2006   b  are supplied to primary  2016  of micro-transformer  2002  and, as noted above, corresponding pulses  2006   a ′ and  2006   b ′ are output by secondary  2018 . 
   Receiver circuit  2008 , in this example, includes threshold detector  2020   a  tied to a high reference and threshold detector  2020   b  tied to a low reference. In this way, threshold detector  2020   a  produces an output in response to high amplitude pulse  2006   a ′ and threshold detector  2020   b  produces an output in response to both high amplitude pulse  2006   a  and lower amplitude pulse  2006   b . NOR gate  2022  is response to both threshold detectors and produces a high signal only when no pulses are input thus recreating the input logic signal. As shown, transmitter circuit  2000  may include glitch filter  2030  as described above with reference to  FIG. 1 . 
   Also, transmitter circuit  2000  may include refresh circuit  2040  configured to periodically send a refresh signal across micro-transformer  2002 . 
   A stable  2042  through differentiator  2044  will generate a refresh signal  2006   a  when the input is high and neither an edge  2004   a  nor an edge  2004   b  was detected for 1 us. Similarly, through differentiator  2044 , a stable  2042  will generate a refresh signal  2006   b  when the input is low and neither an edge  2004   a  nor an edge  2004   b  was detected. The refresh signals are generated to ensure the output is always updated. Correspondingly, there is a watchdog circuit  2060  inside receiver circuit  2008  to check if there are any pulses coming out of comparators  2020   a  or  2020   b  through NOR gate  2022 . If there area no pulses detected for 2 us, the watchdog will set the output to a default state. 
   In one embodiment, gate  2014 ,  FIG. 17 , is configured as shown in  FIG. 18 . Gate  2014  is similar to a normal OR gate except that PMOS  2080   a  and PMOS  2080   b  have their source tied to different power supplies, one to V 1  and one to V 2 . 
   In this way, a higher speed isolator is realized in only a single channel. A single pulse with two different amplitudes can be used to differentiate the rising edge from the falling edge of the input signal which is easier to decode since the input signal is recovered based on different pulse amplitudes. 
   Having discussed the principles involved and having illustrated multiple embodiments, it will be further apparent that various alterations thereto and additional embodiments will occur to those skilled in the art. Any such alterations, amendments, improvements and additional embodiments are intended to be within the spirit and scope of the invention, which is not limited by the foregoing examples but only as required by the appended claims and equivalence thereto.