Patent Publication Number: US-2023162648-A1

Title: Input signal correction device

Description:
TECHNICAL FIELD 
     The present invention relates to an input signal correction device for correcting input signals with respect to a display panel having uneven numbers of R, G and B subpixels. 
     BACKGROUND ART 
     Conventionally, as described in Patent Document 1, LCD, OLED, micro LED and other display panels having uneven numbers of R, G and B subpixels, also called a PenTile (registered trademark) structure, are known. Display panels having such a structure are able to secure a resolution with a small number of subpixels, and have recently been widely employed in smartphone displays and other devices. 
     As shown in  FIG.  6   , in a display panel  1  having an RGBG pixel structure, a 1st pixel P 1  includes an R subpixel P 1R  and a G subpixel P 1G , a 2nd pixel P 2  includes a B subpixel P 2B  and a G subpixel P 2G , a (2k+1)th pixel P (2k+1)  (where k is an integer greater than or equal to 1) includes an R subpixel P (2k+1)R  and a G subpixel P (2k+1)G , and a (2k+2)th pixel P (2k+2)  includes an B subpixel P (2k+2)B  and a G subpixel P (2k+2)G . This display panel  1  may have an input signal correction device  2  such as shown in  FIG.  7   , so that even if the panel body is structurally susceptible to mura (clouding), input image signals are corrected with software to eliminate mura (demura process) before being output to the panel body. 
     The input signal correction device  2  includes an input circuit  3  configured to operate at an operating frequency f and to receive input of R, G and B input signals (image signals), an extension circuit  4  configured to operate at the operating frequency f and to extend the period of an input signal Ri relating to R subpixels and an input signal Bi relating to B subpixels, out of the R, G and B input signals input to the input circuit  3 , by a factor of 2 and output preprocessing signals RiA and BiA, a delay circuit  5  configured to operate at the operating frequency f and to delay an input signal Gi relating to G subpixels, out of the R, G and B input signals input to the input circuit  3 , and output a preprocessing signal GiA at substantially the same time as output of the preprocessing signals RiA and BiA by the extension circuit  4 , a demura circuit  6  configured to operate at the operating frequency f and to correct the preprocessing signals RIA, BiA and GIA and output correction signals ΔRo, ΔBo and ΔGo, a delay adjustment circuit  7  configured to operate at the operating frequency f and to delay the input signals Ri, Bi and Gi and output delay signals RiD, BiD and GiD, an adder circuit  8  configured to add the correction signals ΔRo, ΔBo and ΔGo to the delay signals RiD, BiD and GiD and output output signals Ro, Bo and Go (Ro=RiD+ΔRo, Bo=BiD+ΔBo, Go=GiD+ΔGo), and a clock circuit  9  configured to generate a clock signal of operating frequency f to be input to the input circuit  3 , the extension circuit  4 , the delay circuit  5 , the demura circuit  6  and the delay adjustment circuit  7 . As described in Patent Document 2, mura of the panel body is corrected by inputting the output signals Ro, Bo and Go to the panel body, rather than directly inputting the input signals Ri, Bi and Gi. 
     CITATION LIST 
     Patent Document 
     
         
         Patent Document 1: JP4647213 
         Patent Document 2: JP6220674 
       
    
     SUMMARY OF INVENTION 
     Technical Problem 
     Incidentally, in the past, the mura correction performance of the input signal correction device was important for technical competitiveness, but with the marked improvements in display panel performance in recent years, reduction in power consumption is now becoming the differentiating point. In particular, increases in the screen size and processor speed of mobile devices such as smartphones has meant that batteries are more easily drained, and reduction in power consumption relating to display panels has become an issue. 
     The present invention has been made in view of the above circumstances, and an object thereof is to provide an input signal correction device capable of reducing power consumption. 
     Solution to Problem 
     In order to solve the above problem, the invention is an input signal correction device for correcting input signals with respect to a display panel in which numbers of R, G and B subpixels are uneven at a ratio of minority subpixels to majority subpixels of 1:N, where N is an integer of 2 or more, including an input circuit configured to operate at an operating frequency f and to receive input of R, G and B input signals, an extension circuit configured to operate at the operating frequency f and to extend a period of a first input signal relating to the minority subpixels, out of the R, G and B input signals input to the input circuit, by a factor of N and output a first preprocessing signal, a degenerate circuit configured to operate at the operating frequency f and to degenerate a second input signal relating to the majority subpixels, out of the R, G and B input signals input to the input circuit, to 1/N and output a second preprocessing signal at substantially the same time as the first preprocessing signal, a correction circuit configured to operate at an operating frequency f/N and to correct the first preprocessing signal and output a first correction signal and also correct the second preprocessing signal and output a second correction signal, a separation circuit configured to operate at the operating frequency f and to reduce a period of the first correction signal to 1/N and output a first differential signal, a recovery circuit configured to operate at the operating frequency f and to reduce a period of the second correction signal to 1/N and output the same second differential signal over N periods, a delay adjustment circuit configured to operate at the operating frequency f and to delay the first input signal and output a first delay signal and also delay the second input signal and output a second delay signal, and an adder circuit configured to add the first differential signal to the first delay signal and also add the second differential signal to the second delay signal. 
     This input signal correction device may include a clock circuit configured to generate a clock signal of operating frequency f to be input to the input circuit, the extension circuit, the degenerate circuit, the separation circuit, the recovery circuit and the delay adjustment circuit, and a frequency divider circuit configured to generate a clock signal of operating frequency f/N to be input to the correction circuit, by dividing a frequency of the clock signal of operating frequency f. 
     Alternatively, the invention is an input signal correction device for correcting input signals with respect to a display panel in which numbers of R, G and B subpixels are uneven at a ratio of minority subpixels to majority subpixels of 1:N, where N is an integer of 2 or more, including an input circuit configured to operate based on a clock signal of frequency f and to receive input of R, G and B input signals, an extension circuit configured to operate based on the clock signal and to extend a period of a first input signal relating to the minority subpixels, out of the R, G and B input signals input to the input circuit, by a factor of N and output a first preprocessing signal, a degenerate circuit configured to operate based on the clock signal and to degenerate a second input signal relating to the majority subpixels, out of the R, G and B input signals input to the input circuit, to 1/N and output a second preprocessing signal at substantially the same time as the first preprocessing signal, a correction circuit configured to operate based on the clock signal and receive input of a clock enable signal for switching the clock signal between enabled and disabled at a frequency f/N, and to correct the first preprocessing signal and output a first correction signal and also correct the second preprocessing signal and output a second correction signal, a separation circuit configured to operate based on the clock signal and to reduce a period of the first correction signal to 1/N and output a first differential signal, a recovery circuit configured to operate based on the clock signal and to reduce a period of the second correction signal to 1/N and output the same second differential signal over N periods, a delay adjustment circuit configured to operate based on the clock signal and to delay the first input signal and output a first delay signal and also delay the second input signal and output a second delay signal, and an adder circuit configured to add the first differential signal to the first delay signal and also add the second differential signal to the second delay signal. 
     This input signal correction device may include a clock circuit configured to generate the clock signal, and a clock enable circuit configured to generate the clock enable signal based on the clock signal. 
     Furthermore, the correction circuit may correct the first preprocessing signal to reduce mura of the display panel and output the first correction signal, and correct the second preprocessing signal to reduce mura of the display panel and output the second correction signal. 
     Advantageous Effects of Invention 
     According to an input signal correction device of the present invention, power consumption can be reduced. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1    is a block diagram showing an input signal correction device according to an embodiment of the invention. 
         FIG.  2    is an illustrative diagram showing a panel body of a display panel to which the input signal correction device of  FIG.  1    is applied. 
         FIG.  3    is an illustrative diagram showing outputs of an input circuit, an extension circuit, a degenerate circuit, a demura circuit, a separation circuit, a recovery circuit and an adder circuit of the input signal correction device in  FIG.  1   . 
         FIG.  4    is a block diagram showing another input signal correction device according to an embodiment of the invention. 
         FIG.  5    is an illustrative diagram showing outputs of an input circuit, an extension circuit, a degenerate circuit, a demura circuit, a separation circuit, a recovery circuit and an adder circuit of the input signal correction device in  FIG.  4   . 
         FIG.  6    is an illustrative diagram showing a panel body of a display panel having an RGBG pixel structure. 
         FIG.  7    is a block diagram showing a conventional input signal correction device. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Embodiments of the invention will be described using the drawings. 
       FIG.  1    shows an input signal correction device according to the present embodiment. This input signal correction device  10  superposes a signal obtained by inverting the polarity of a mura signal acquired in advance on an input image signal and cancels mura of the panel body in a display panel  11  shown in  FIG.  2    having an RGBG pixel structure similarly to the display panel  1 . 
     In the panel body of the display panel  11 , pixels consisting of an R subpixel and a G subpixel and pixels consisting of a B subpixel and a G subpixel are alternately arrayed horizontally and vertically. Specifically, a 1st pixel P 1  includes an R subpixel P 1R  and a G subpixel P 1G , a 2nd pixel P 2  includes a B subpixel P 2B  and a G subpixel P 2G , a (2k+1)th pixel P (2k+1)  includes an R subpixel P (2k+1)R  and a G subpixel P (2k+1)G , and a (2k+2)th pixel P (2k+2)  includes a B subpixel P (2k+2)B  and a G subpixel P (2k+2)G . 
     Also, the input signal correction device  10  includes an input circuit  12 , an extension circuit  13 , a degenerate circuit  14 , a demura circuit  15 , a separation circuit  16 , a recovery circuit  17 , a delay adjustment circuit  18 , an adder circuit  19 , a clock circuit  20  and a frequency divider circuit  21 . 
     The input circuit  12  is configured to operate at an operating frequency f and to receive input of R, G and B input signals (image signals) and output input signals to the extension circuit  13 . 
     The extension circuit  13  is configured to operate at the operating frequency f and to extend an input signal Ri relating to R subpixels and an input signal Bi relating to B subpixels, out of the input signals of R, G and B input signals input to the input circuit  12 , by a factor of 2 and output preprocessing signals RiA and BiA. 
     That is, as shown in  FIG.  3   , a signal R 1  relating to the R subpixel P 1R  of the 1st pixel P 1 , for example, is input in the first period to the extension circuit  13  and a signal relating to an R subpixel of the 2nd pixel P 2  does not exist and is thus not input in the second period, and, in the extension circuit  13 , a preprocessing signal RiA obtained by extending the signal R 1  of the first period to the second period is generated. 
     Also, a signal B 2  relating to the B subpixel P 2B  of the 2nd pixel P 2  is input in the second period to the extension circuit  13 , and, in the extension circuit  13 , a preprocessing signal BiA obtained by adding a dummy signal having no data in the first period to the signal B 2  is generated. 
     The degenerate circuit  14  is configured to operate at the operating frequency f and to degenerate an input signal Gi relating to G subpixels, out of the R, G and B input signals input to the input circuit  12 , and output a preprocessing signal GiA at substantially the same time as output of the preprocessing signals RiA and BiA by the extension circuit  13 . Here, “degenerate” involves converting data of X pixels into data of Y pixels (Y&lt;X) by deriving an arithmetic mean value, a weighted mean value, a central value or the like. A signal G 1  relating to the G subpixel P 1G  of the 1st pixel P 1  is input in the first period and a signal G 2  relating to the G subpixel P 2G  of the 2nd pixel P 2  is input in the second period to the degenerate circuit  14 , and, in the degenerate circuit  14 , a preprocessing signal GiA obtained by assigning a signal (G 1 +G 2 )/2 obtained by taking the arithmetic mean of the signal G 1  and the signal G 2  to the second period and adding a dummy signal in the first period is generated. 
     The demura circuit  15  is configured to operate at an operating frequency f/2 and to correct the preprocessing signals RiA, BiA and GiA and output correction signals ΔRo, ΔBo and ΔGo. That is, the signals R 1 , B 2  and (G 1 +G 2 )/2, which are the preprocessing signals RiA, BiA and GiA of the second period, are input to the demura circuit  15 , and, in the demura circuit  15 , signals ΔRo 1 , ΔBo 2  and ΔGo 12  are generated as the correction signals ΔRo, ΔBo and ΔGo, by correcting the signals R 1 , B 2  and (G 1 +G 2 )/2 based on correction data stored in the demura circuit  15 . At this time, the operating frequency of the demura circuit  15  is f/2, and thus the signal lengths of the correction signals ΔRo 1 , ΔBo 2 , and ΔGo 12  will be doubled (two periods worth). 
     The separation circuit  16  is configured to operate at the operating frequency f and to reduce the period of the correction signals ΔRo and ΔBo to ½ and output differential signals ΔRoR and ΔBoR. That is, the signal ΔRo 1  is input as the correction signal ΔRo in the first period and the signal ΔBo 2  is input as the correction signal ΔBo in the second period to the separation circuit  16 , and, in the separation circuit  16 , a signal ΔRoR 1  obtained by adding a dummy signal in the second period to the signal ΔRo 1  and separating the signal ΔRo 1  in the first period is generated, and a signal ΔBoR 2  obtained by adding a dummy signal in the first period to the signal ΔBo 2  and separating the signal ΔBo 2  in the second period is generated. 
     The recovery circuit  17  is configured to operate at the operating frequency f and to reduce the period of the correction signal ΔGo to ½ and output the same differential signal ΔGoR over two periods. That is, the signal ΔGo 12  is input as the correction signal ΔGo in the first period to the recovery circuit  17 , and, in the recovery circuit  17 , the signal ΔGo 12  is also copied to the second period and recovered in the second period similarly to the input signal Gi (signal relating to G subpixel P 1G  of 1st pixel P 1  and signal relating to G subpixel P 2G  of 2nd pixel P 2 ), and a signal ΔGoR 12  is generated. 
     The delay adjustment circuit  18  is configured to operate at the operating frequency f and to delay the input signals Ri, Bi and Gi and output delay signals RiD, BiD and GiD, and, in the delay adjustment circuit  18 , when input of the signals R 1 , B 1 , and G 1  is received, signals RiD 1 , BiD 1  and GiD 1  obtained by delaying the signals R 1 , B 1  and G 1  are generated. 
     The adder circuit  19  is configured to add the differential signals ΔRoR, ΔBoR and ΔGoR to the delay signals RiD, BiD and GiD and output output signals Ro, Bo and Go (Ro=RiD+ΔRoR, Bo=BiD+ΔBoR, Go=GiD+ΔGoR; note that differential signals ΔRoR, ΔBoR and ΔGoR may be positive or may be negative), and, in the adder circuit  19 , the signal ΔRo 1  is added to the signal RiD 1  and a signal Ro 1  is generated, the signal ΔBo 2  is added to the signal BiD 2  and a signal Bo 2  is generated, the signal ΔGo 12  is added to the signal GiD 1  and a signal Go 1  is generated, and the signal ΔGo 12  is added to a signal GiD 2  and the signal Go 1  is generated. 
     The clock circuit  20  generates a clock signal of operating frequency f to be input to the input circuit  12 , the extension circuit  13 , the degenerate circuit  14 , the separation circuit  16 , the recovery circuit  17  and the delay adjustment circuit  18 , and the frequency divider circuit  21  generate a clock signal of operating frequency f/2 to be input to the demura circuit  15 , by dividing the frequency of the clock signal of operating frequency f by 2. 
     The input signal correction device  10  according to the present embodiment includes the input circuit  12  configured to operate at the operating frequency f and to receive input of R, G and B input signals, the extension circuit  13  configured to operate at the operating frequency f and to extend the period of the input signal Ri relating to R subpixels and the input signal Bi relating to B subpixels, out of the R, G and B input signals input to the input circuit  12 , by a factor of 2 and output the preprocessing signals RiA and BiA, the degenerate circuit  14  configured to operate at the operating frequency f and to degenerate (here, calculate the mean of) the input signal Gi relating to G subpixels, out of the R, G and B input signals input to the input circuit  2 , and output the preprocessing signal GiA at substantially the same time as the preprocessing signals RiA and BiA that are output by the extension circuit  13 , the demura circuit  15  configured to operate at the operating frequency f/2 and to correct the preprocessing signals RiA, BiA and GiA and output the correction signals ΔRo, ΔBo and ΔGo, the separation circuit  16  configured to operate at the operating frequency f and to reduce the period of the correction signals ΔRo and ΔBo to ½ and output the differential signals ΔRoR and ΔBoR, the recovery circuit  17  configured to operate at the operating frequency f and to reduce the period of the correction signal ΔGo to ½ and output the same differential signal ΔGo over two periods, the delay adjustment circuit  18  configured to operate at the operating frequency f and to delay the input signals Ri, Bi and Gi and output the delay signals RiD, BiD and GiD, and the adder circuit  19  configured to add the differential signals ΔRoR, ΔBoR and ΔGoR to the delay signals RiD, BiD and GiD and output the output signals Ro, Bo and Go. Accordingly, the operating frequency of the demura circuit  15  can be lowered to ½, by degenerating the input signal Gi to ½ with the degenerate circuit  14 , and thus the power consumption required for demura (mura correction) can be reduced by substantially half. 
       FIG.  4    shows another input signal correction device according to the present embodiment. This input signal correction device  30  superposes a signal obtained by inverting the polarity of a mura signal acquired in advance on an input image signal and cancels mura of the panel body in the display panel  11 , and, apart from the operation of the demura circuit  15  being different from the input signal correction device  10  and a clock enable circuit  31  being provided instead of the frequency divider circuit  21 , has a similar configuration to the input signal correction device  10 . 
     In the input signal correction device  30 , the clock enable circuit  31  generates a clock enable signal for switching between enabling and disabling the clock signal at a frequency f/N, based on the clock signal of frequency f generated by the clock circuit  20 , and outputs this clock enable signal to the demura circuit  15 . 
     As shown in  FIG.  5   , the demura circuit  15  operates based on the clock signal of frequency f generated by the clock circuit  20 , and receives input of the clock enable signal generated by the clock enable circuit  31 , and, in the demura circuit  15 , similarly to the case of the input signal correction device  10 , the signals R 1 , B 2  and (G 1 +G 2 )/2, which are the preprocessing signals RiA, BiA and GIA of the second period, are input at the timing at which the clock enable signal is High (at this time, the clock signal is enabled, and when the clock enable signal is Low, the clock signal is disabled). In the demura circuit  15 , the signals ΔRo 1 , ΔBo 2  and ΔGo 12  are generated as the correction signals ΔRo, ΔBo and ΔGo, by correcting the signals R 1 , B 2  and (G 1 +G 2 )/2 based on correction data stored in the demura circuit  15 . 
     This input signal correction device  30  includes the input circuit  12  configured to operate based on the clock signal of operating frequency f and to receive input of R, G and B input signals, the extension circuit  13  configured to operate based on the clock signal of operating frequency f and to extend the period of the input signal Ri relating to R subpixels and the input signal Bi relating to B subpixels, out of the R, G and B input signals input to the input circuit  12 , by a factor of 2 and output the preprocessing signals RIA and BiA, the degenerate circuit  14  configured to operate based on the clock signal of operating frequency f and to degenerate the input signal Gi relating to G subpixels, out of the R, G and B input signals input to the input circuit  2 , and output the preprocessing signal GIA at substantially the same time as the preprocessing signals RiA and BiA that are output by the extension circuit  13 , the demura circuit  15  configured to operate based on the clock signal of frequency f and receive input of the clock enable signal for switching the clock signal between enabled and disabled at the frequency f/2, and to correct the preprocessing signals RiA, BiA and GiA and output the correction signals ΔRo, ΔBo and ΔGo, the separation circuit  16  configured to operate based on the clock signal of frequency f and to reduce the period of the correction signals ΔRo and ΔBo to ½ and output the differential signals ΔRoR and ΔBoR, the recovery circuit  17  configured to operate based on the clock signal of frequency f and to reduce the period of the correction signal ΔGo to ½ and output the same differential signal ΔGo over two periods, the delay adjustment circuit  18  configured to operate based on the clock signal of frequency f and to delay the input signals Ri, Bi and Gi and output the delay signals RiD, BiD and GiD, and the adder circuit  19  configured to add the differential signals ΔRoR, ΔBoR and ΔGoR to the delay signals RiD, BiD and GiD and output the output signals Ro, Bo and Go. Accordingly, the demura circuit  15  can be operated in an equivalent manner to the input signal correction device  10 , by degenerating the input signal G to ½ with the degenerate circuit  14  and inputting the clock enable signal to the demura circuit  15 , and power consumption required for demura can be reduced. 
     Although embodiments of the present invention are illustrated above, the embodiments of the invention are not limited to those described above, and changes and the like can be made as appropriate without departing from the spirit of the invention. 
     For example, the panel body of the display panel to which the input signal correction device is applied is not limited to a panel body having an RGBG pixel structure, and may have an RBGB pixel structure in which pixels including an R subpixel and a B subpixel and pixels including a G subpixel and a B subpixel are combined, or may have an RBRG pixel structure in which pixels including a G subpixel and an R subpixel and pixels including a G subpixel and an R subpixel are combined. 
     Also, the numbers of R, G and B subpixels do not necessarily need to satisfy a ratio of minority subpixels to majority subpixels of 1:2, and may, for example, be a ratio of minority subpixels to majority subpixels of 1:3, such that the signal of the majority subpixels is degenerated to ⅓ rather than ½ by the degenerate circuit, and the frequency divider circuit is a ⅓ frequency divider circuit rather than a ½ frequency divider circuit. 
     Furthermore, the correction of input signals is not limited to mura correction, and the input signal correction device according to the present invention may perform any manner of correction. 
     LIST OF REFERENCE NUMERALS 
     
         
         
           
               10  Input signal correction device 
               11  Display panel 
               12  Input circuit 
               13  Extension circuit 
               14  Degenerate circuit 
               15  Demura circuit (correction circuit) 
               16  Separation circuit 
               17  Recovery circuit 
               18  Delay adjustment circuit 
               19  Adder circuit 
               20  Clock circuit 
               21  Frequency divider circuit 
               30  Input signal correction device 
               31  Clock enable circuit