Patent Publication Number: US-2023155092-A1

Title: Led display unit group and display panel

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a National Stage Application filed under 35 U. S.C.  371  based on International Patent Application No. PCT/CN2021/082932, filed on Mar. 25, 2021, which claims priority to Chinese Patent Application No. 202010247535.4 filed with the China National Intellectual Property Administration (CNIPA) on Mar. 31, 2020, the disclosures of which are incorporated herein by reference in their entireties. 
    
    
     TECHNICAL FIELD 
     Embodiments of the present application relate to the field of light-emitting diode (LED) display technologies, for example, an LED display unit group and a display panel. 
     BACKGROUND 
     With the development of display technologies, the indoor small-pitch LED display screen has become the main technology expending space in the future. The pixel unit density of the indoor small-pitch LED display screen needs to satisfy increasingly higher requirements, that is, the pixel unit pitch is required to be as small as possible. 
     As the number of light-emitting units integrated in the small-pitch LED display screen increases, more metal pads, conductive leads and pins need to be configured, causing the subsequent welding to be difficult and the wiring of the printed circuit board (PCB) to be more complicated. 
     The structure of a traditional LED display unit group cannot achieve the improvement of the integration level of small-pitch LEDs and the improvement of the circuit stability of the LED display unit group at the same time. 
     SUMMARY 
     In view of this, embodiments of the present application provide a LED display unit group and a display panel, so as to solve the technical problem in the related art that the improvement of the integration level of small-pitch LEDs and the improvement of the circuit stability of the LED display unit group cannot be achieved at the same time. 
     An embodiment of the present application provides a LED display unit group. The LED display unit group includes a circuit board and pixel units. 
     The circuit board includes N metal wiring layers stacked in sequence and an insulating plate disposed between adjacent metal wiring layers among the N metal wiring layers, and the N metal wiring layers are electrically connected through conductive vias on the insulating plate, where N≥2. 
     The pixel units are arranged in an array of m rows and n columns and disposed on the circuit board, where each of the pixel units includes at least two LED light-emitting chips with different emitted colors, each of the at least two LED light-emitting chips is fixed on a first metal wiring layer among the N metal wiring layers, m≥2, and n≥2. 
     The first metal wiring layer includes m common A-electrode pads, a plurality of A-electrode pads, and a plurality of B-electrode pads, where the plurality of A-electrode pads are disposed in one-to-one correspondence with A electrodes of LED light-emitting chips, the plurality of B-electrode pads are disposed in one-to-one correspondence with B electrodes of the LED light-emitting chips, and all A-electrode pads corresponding to each row of pixel units are integrally formed with and electrically connected to one of the m common A-electrode pads corresponding to the each row of pixel units. 
     Each of the m common A-electrode pads includes at least one bend part, and a bending direction of the at least one bend part of one of the m common A-electrode pads corresponding to a first row of pixel units is opposite to a bending direction of the at least one bend part of one of the m common A-electrode pads corresponding to an m-th row of pixel units. 
     In an embodiment, an N-th metal wiring layer among the N metal wiring layers includes m common A-electrode pins and 3n common B-electrode pins, where one of the m common A-electrode pins is electrically connected to one of the m common A-electrode pads corresponding to A electrodes of all LED light-emitting chips in one row of pixel units, and one of the 3n common B-electrode pins is electrically connected to a plurality of B-electrode pads corresponding to B electrodes of all LED light-emitting chips with a same emitted color in one column of pixel units. 
     In an embodiment, a plurality of A-electrode pads of one of the pixel units in an i-th column and a row, a plurality of A-electrode pads of one of the pixel units in an (i+1)-th column and the same row, and one of the m common A-electrode pads connected to the plurality of A-electrode pads of the one of the pixel units in the i-th column and the row and the plurality of A-electrode pads of the one of the pixel units in the (i+1)-th column and the same row are U-shaped, where i&lt;n. 
     In an embodiment, a plurality of B-electrode pads of the one of the pixel units in the i-th column and the row and a plurality of B-electrode pads of the one of the pixel units in the (i+1)-th column and the same row are disposed in a U-shaped opening, where i is an odd number. 
     In an embodiment, in two adjacent pixel units of the pixel units in a same row, a direction of a connection line from an A electrode to a B electrode of one of the at least two LED light-emitting chips in one of the two adjacent pixel units is opposite to a direction of a connection line from an A electrode to a B electrode of one of the at least two LED light-emitting chips in another one of the two adjacent pixel units. 
     In an embodiment, conductive vias electrically connected to a plurality of B-electrode pads corresponding to all the at least two LED light-emitting chips of each of the pixel units are not on a same vertical line. 
     In an embodiment, each of the pixel units comprises following three LED light-emitting chips: a LED light-emitting chip with a first emitted color, a LED light-emitting chip with a second emitted color, and a LED light-emitting chip with a third emitted color, where the three LED light-emitting chips with different emitted colors are in one-to-one correspondence with three B-electrode pads of the plurality of B-electrode pads, and the three B-electrode pads in one-to-one correspondence with the three LED light-emitting chips with different emitted colors are a first B-electrode pad corresponding to the LED light-emitting chip with the first emitted color, a second B-electrode pad corresponding to the LED light-emitting chip with the second emitted color, and a third B-electrode pad corresponding to the LED light-emitting chip with the third emitted color, respectively. 
     In an embodiment, in the case where N=4, a metal wire connecting all first B-electrode pads of each column of pixel units and a metal wire connecting all third B-electrode pads of each column of pixel units are disposed on a third metal wiring layer among the N metal wiring layers. 
     In an embodiment, in the case where N=4, a metal wire connecting all second B-electrode pads of each column of pixel units is disposed on a second metal wiring layer among the N metal wiring layers. 
     In an embodiment, an identification mark for identifying electrodes of pins is disposed on one insulating plate in contact with an N-th metal wiring layer among the N metal wiring layers. 
     In an embodiment, an identification mark that is used for identifying electrodes of pins and is made of a same material as the m common A-electrode pins and the 3n common B-electrode pins is disposed on one insulating plate in contact with the N-th metal wiring layer and the identification mark is not electrically connected. 
     In an embodiment, a distance between every two adjacent ones of the identification mark, the m common A-electrode pins, and the 3n common B-electrode pins is the same. 
     An embodiment of the present application provides a display panel including any LED display unit group described above. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1    is a top view of a LED display unit group according to an embodiment of the present application; 
         FIG.  2    is a sectional diagram taken along a line A-A′ of  FIG.  1   ; 
         FIG.  3    is a structural diagram of a first metal wiring layer according to an embodiment of the present application; 
         FIG.  4    is a structural diagram of a fourth metal wiring layer according to an embodiment of the present application; 
         FIG.  5    is a structural diagram of a second metal wiring layer according to an embodiment of the present application; and 
         FIG.  6    is a structural diagram of a third metal wiring layer according to an embodiment of the present application. 
     
    
    
     DETAILED DESCRIPTION 
     As described in the above background, the structure of the traditional LED display unit group is limited by sizes of the pads and metal wires. Therefore, the size of the display unit group is difficult to be further reduced, and it is impossible to improving the integration level of the small-pitch LEDs and improving the circuit stability of the LED display unit group at the same time. 
     To solve the preceding technical problem, embodiments of the present application provide the technical schemes described below. 
     An LED display unit group includes a circuit board and pixel units. The circuit board includes N metal wiring layers stacked in sequence and an insulating plate disposed between adjacent metal wiring layers. The N metal wiring layers are electrically connected through conductive vias on the insulating plate, and N≥2. The pixel units are arranged in an array of m rows and n columns and disposed on the circuit board, each pixel unit includes at least two LED light-emitting chips with different emitted colors, and each LED light-emitting chip is fixed on a first metal wiring layer, where m≥2 and n≥2. The first metal wiring layer includes m common A-electrode pads, multiple A-electrode pads, and multiple B-electrode pads. The multiple A-electrode pads are disposed in one-to-one correspondence with A electrodes of LED light-emitting chips, the multiple B-electrode pads are disposed in one-to-one correspondence with B electrodes of the LED light-emitting chips, and all the A-electrode pads corresponding to each row of pixel units are integrally formed with and electrically connected to one common A-electrode pad corresponding to each row of pixel units. Each common A-electrode pad includes at least one bend part, and a bending direction of the bend part of the common A-electrode pad corresponding to a first row of pixel units is opposite to a bending direction of the bend part of the common A-electrode pad corresponding to an m-th row of pixel units. 
       FIG.  1    is a top view of a LED display unit group according to an embodiment of the present application.  FIG.  2    is a sectional diagram taken along a line A-A′ of  FIG.  1   .  FIG.  3    is a structural diagram of a first metal wiring layer according to an embodiment of the present application. 
     For ease of description, in the embodiments of the present application, the technical schemes in the embodiment of the present application are described by using an example in which N=4, m=5, n=4 and each pixel unit includes three LED light-emitting chips with different emitted colors. 
     Referring to  FIGS.  1 ,  2  and  3   , exemplarily, the circuit board includes four metal wiring layers stacked in sequence, and the four metal wiring layers are a first metal wiring layer  10 , a second metal wiring layer  20 , a third metal wiring layer  30 , and a fourth metal wiring layer  40  in sequence from top to bottom. The insulating plate is disposed between every two adjacent metal wiring layers, and there are a first insulating plate  50 , a second insulating plate  51 , and a third insulating plate  52  in sequence from top to bottom. Two separate PCBs are pressed to form the circuit board. Each PCB includes two metal wiring layers and the insulating plate between the two metal wiring layers, another insulating plate is disposed between the two PCBs, and the three are pressed together to form the circuit board. The four metal wiring layers are electrically connected through the conductive vias (not shown in the figures). Twenty pixel units Ps arranged in an array of five rows and four columns are disposed on the circuit board, and each pixel unit P includes three LED light-emitting chips  60  with different emitted colors, which are a LED light-emitting chip  601  with a first emitted color, a LED light-emitting chip  602  with a second emitted color, and a LED light-emitting chip  603  with a third emitted color, respectively. Each LED light-emitting chip  60  is fixed on the first metal wiring layer  10 . Each LED light-emitting chip  60  includes an A electrode  60 A and a B electrode  60 B. The polarity of the A electrode  60 A and the polarity of the B electrode  60 B are opposite, and the A electrode  60 A and the B electrode  60 B are electrically connected to the first metal wiring layer  10 . In the embodiments of the present application, the A electrode  60 A may be a cathode of the LED light-emitting chip  60 , and the B electrode  60 B may be an anode of the LED light-emitting chip  60 . The first metal wiring layer  10  includes five common A-electrode pads  101 , multiple A-electrode pads  102 , and multiple B-electrode pads  103 . The A-electrode pads  102  are disposed in one-to-one correspondence with the A electrodes of the LED light-emitting chips  60  in the pixel units, the B electrode pads  103  are disposed in one-to-one correspondence with the B electrodes of the LED light-emitting chips  60  in the pixel units, each common A-electrode pad  101  is integrally formed with all the A electrode pads  102  corresponding to one row of pixel units, and all the A-electrode pads  102  corresponding to each row of pixel units Ps are electrically connected to a corresponding common A-electrode pad  101 . Each common A-electrode pad  101  includes at least one bend part  101 A, and the bending direction of the bend part  101 A of the common A-electrode pad  101  corresponding to the first row of pixel units is opposite to the bending direction of the bend part  101 A of the common A-electrode pad corresponding to the m-th row of pixel units. Referring to  FIG.  3   , on the first metal wiring layer  10 , the bending direction of the bend part  101 A of the common A-electrode pad  101  corresponding to the first three rows of pixel units is opposite to the bending direction of the bend part  101 A of the common A-electrode pad  101  corresponding to the fourth row of pixel units and the fifth row of pixel units. 
     In the LED display unit group provided in the embodiments of the present application, the circuit board includes at least two metal wiring layers stacked in sequence and the insulating plate disposed between adjacent metal wiring layers. At least two metal wiring layers are electrically connected through the conductive vias on the insulating plate. The pixel units Ps arranged in an array of at least 2 rows and 2 columns are disposed on the circuit board. Each pixel unit includes at least two LED light-emitting chips  60  with different emitted colors. Each LED light-emitting chip  60  is fixed on the first metal wiring layer  10 . The first metal wiring layer  10  includes at least two common A-electrode pads  101 , multiple A-electrode pads  102 , and multiple B-electrode pads  103 . The A-electrode pads  102  are disposed in one-to-one correspondence with the A electrodes of the LED light-lighting chips  60  in the pixel units. The B-electrode pads  103  are disposed in one-to-one correspondence with the B electrodes  60 B of the LED light-emitting chips  60  in the pixel units. Each common A-electrode pad  101  is integrally formed with all the A-electrode pads  102  corresponding to one row of pixel units. All the A-electrode pads  102  corresponding to each row of pixel units are electrically connected to a corresponding common A-electrode pad  101 . Each common A-electrode pad  101  includes at least one bend part  101 A, and the bending direction of the bend part  101 A of the common A-electrode pad  101  corresponding to the first row of pixel units is opposite to the bending direction of the bend part of the common A-electrode pad corresponding to the m-th row of pixel units. An electrical signal required by the A-electrode pad is transmitted to the A-electrode pad  102  through the common A-electrode pad  101 , so as to solve the problem in the related art that the size of the display unit group is difficult to be reduced due to the limitation of the sizes of the pads and metal wires, thereby improving the integration level of the LED light-emitting chips while the circuit stability is ensured. 
     In an embodiment, an N-th metal wiring layer includes m common A-electrode pins and 3n common B-electrode pins. One common A-electrode pin is electrically connected to the common A-electrode pad corresponding to the A electrodes of the LED light-emitting chips in one row of pixel units, and one common B-electrode pin is electrically connected to the B-electrode pads corresponding to the B electrodes of the LED light-emitting chips with a same emitted color in one column of pixel units.  FIG.  4    is a structural diagram of a fourth metal wiring layer according to an embodiment of the present application. Referring to  FIG.  4   , in this embodiment, the N-th metal wiring layer is the fourth metal wiring layer  40 . Referring to  FIG.  4   , the fourth metal wiring layer  40  includes five common A-electrode pins, which are a common A-electrode pin  401  in the first row, a common A-electrode pin  402  in the second row, a common A-electrode pin  403  in the third row, a common A-electrode pin  404  in the fourth row, and a common A-electrode pin  405  in the fifth row. Twelve common B-electrode pins are a first common B-electrode pin  406 A in the first column, a second common B-electrode pin  406 B in the first column, a third common B-electrode pin  406 C in the first column, a first common B-electrode pin  407 A in the second column, a second common B-electrode pin  407 B in the second column, a third common B-electrode pin  407 C in the second column, a first common B-electrode pin  408 A in the third column, a second common B-electrode pin  408 B in the third column, a third common B-electrode pin  408 C in the third column, a first common B-electrode pin  409 A in the fourth column, a second common B-electrode pin  409 B in the fourth column, and a third common B-electrode pin  409 C in the fourth column, respectively. One common A-electrode pin is electrically connected to one common A-electrode pad corresponding to the A electrodes of the LED light-emitting chips in one row of pixel units through the conductive via, and one common B-electrode pin is electrically connected to the B-electrode pads corresponding to the B electrodes of the LED light-emitting chips with the same emitted color in one column of pixel units. 
     In the embodiment of the present application, the common A-electrode pins and the common B-electrode pins disposed on the fourth metal wiring layer  40  transmit driving electrical signals to the A electrodes and the B electrodes of the LED light-emitting chips on the first metal wiring layer  10  through the conductive vias, so as to solve the problem in the related art that the size of the display unit group is difficult to be reduced due to the limitation of the sizes of the pads and metal wires, thereby improving the integration level of the LED light-emitting chips while the circuit stability is ensured. 
     In an embodiment, multiple A-electrode pads of the pixel unit in an i-th column and a row, multiple A-electrode pads of the pixel unit in an (i+1)-th column and the same row, and one common A-electrode pad connected to the multiple A-electrode pads of the pixel unit in the i-th column and the row and the multiple A-electrode pads of the pixel unit in the (i+1)-th column and the same row are U-shaped, where i&lt;n. Exemplarily, referring to  FIG.  3   , multiple A-electrode pads  102  of the pixel unit in the first column and a row, multiple A-electrode pads  102  of the pixel unit in the second column and the same row, and the common A-electrode pad  101  connected to the multiple A-electrode pads  102  of the two pixel units are U-shaped, and multiple A-electrode pads  102  of the pixel unit in the third column and a row, multiple A-electrode pads  102  of the pixel unit in the fourth column and the same row, and the common A-electrode pad  101  connected to the multiple A-electrode pads  102  of the two pixel units are U-shaped. 
     In an embodiment, multiple B-electrode pads of the pixel unit in the i-th column and a row and multiple B-electrode pads of the pixel unit in the (i+1)-th column and the same row are disposed in a U-shaped opening, where i is an odd number. Exemplarily, referring to  FIG.  3   , multiple B-electrode pads of the pixel unit in the first column and a row and multiple B-electrode pads of the pixel unit in the second column and the same row are disposed in the U-shaped opening. Multiple B-electrode pads of the pixel unit in the third column and a row and multiple B-electrode pads of the pixel unit in the fourth column and the same row are disposed in the U-shaped opening. 
     In an embodiment, in two adjacent pixel units in a same row, a direction of a connection line from the A electrode to the B electrode of the LED light-emitting chip in one of the two adjacent pixel units is opposite to a direction of a connection line from the A electrode to the B electrode of the LED light-emitting chip in another one of the two adjacent pixel units. Referring to  FIGS.  1  and  2   , in each row of pixel units, a direction of a connection line from the A electrode  60 A to the B electrode  60 B of one of two LED light-emitting chips  601  with the first emitted color in adjacent pixel units Ps is opposite to a direction of a connection line from the A electrode  60 A to the B electrode  60 B of the other one of two LED light-emitting chips  601  with the first emitted color in the adjacent pixel units Ps. In each row of pixel units, a direction of a connection line from the A electrode  60 A to the B electrode  60 B of one of two LED light-emitting chips  602  with the second emitted color in adjacent pixel units Ps is opposite to a direction of a connection line from the A electrode  60 A to the B electrode  60 B of the other one of two LED light-emitting chips  602  with the second emitted color in the adjacent pixel units Ps. In each row of pixel units, a direction of a connection line from the A electrode  60 A to the B electrode  60 B of one of two LED light-emitting chips  603  with the third emitted color in adjacent pixel units Ps is opposite to a direction of a connection line from the A electrode  60 A to the B electrode  60 B of the other one of two LED light-emitting chips  603  with the third emitted color in the adjacent pixel units Ps. 
     In an embodiment, the conductive vias electrically connected to multiple B-electrode pads corresponding to all the LED light-emitting chips of each pixel unit are not on a same vertical line. Referring to  FIG.  3   , the conductive vias electrically connected to multiple B-electrode pads  103  corresponding to all the LED light-emitting chips of each pixel unit are conductive vias D 2 , D 3 , and D 4 , respectively. Referring to  FIG.  3   , a connection line between the conductive via D 2  and the conductive via D 3  and a connection line between the conductive via D 3  and the conductive via D 4  forms a certain angle with a vertical direction, that is, the conductive vias are disposed in a misaligned manner and not in the same vertical line. 
     In an embodiment, each pixel unit includes a LED light-emitting chip with the first emitted color, a LED light-emitting chip with the second emitted color, and a LED light-emitting chip with the third emitted color, the three LED light-emitting chips with different emitted colors are in one-to-one correspondence with three B-electrode pads, and the three B-electrode pads in one-to-one correspondence with the three LED light-emitting chips with different emitted colors are a first B-electrode pad corresponding to the LED light-emitting chip with the first emitted color, a second B-electrode pad corresponding to the LED light-emitting chip with the second emitted color, and a third B-electrode pad corresponding to the LED light-emitting chip with the third emitted color, respectively. Referring to  FIGS.  1  and  3   , each pixel unit P includes the LED light-emitting chip  601  with the first emitted color, the LED light-emitting chip  602  with the second emitted color, and the LED light-emitting chip  603  with the third emitted color, the three LED light-emitting chips with different emitted colors are in one-to-one correspondence with three B-electrode pads  103 , and the three B-electrode pads  103  in one-to-one correspondence with the three LED light-emitting chips with different emitted colors are a first B-electrode pad  103 A corresponding to the LED light-emitting chip  601  with the first emitted color, a second B-electrode pad  103 B corresponding to the LED light-emitting chip  602  with the second emitted color, and a third B-electrode pad  103 C corresponding to the LED light-emitting chip  603  with the third emitted color, respectively. 
     In an embodiment, in the case where N=4, a metal wire connecting first B-electrode pads corresponding to each column of pixel units and a metal wire connecting third B-electrode pads corresponding to each column of pixel units are disposed on a third metal wiring layer.  FIG.  6    is a structural diagram of a third metal wiring layer according to an embodiment of the present application. Referring to  FIGS.  4  and  6   , in the case where N=4, a metal wire connecting first B-electrode pads  103 A corresponding to each column of pixel units and a metal wire connecting third B-electrode pads  103 C corresponding to each column of pixel units are disposed on the third metal wiring layer  30 . The first B-electrode pad  103 A on the first metal wiring layer  10  is electrically connected to the conductive via D 2  penetrating from the first metal wiring layer  10  to the third metal wiring layer  30 , a first metal wire  301  is electrically connected to the conductive via D 2  and electrically connected to a conductive via D 21  penetrating the third metal wiring layer  30  and the fourth metal wiring layer  40 , and the corresponding conductive via D 21  in the first column of pixel units is electrically connected to the first common B-electrode pin  406 A in the first column. The corresponding conductive via D 21  in the second column of pixel units is electrically connected to the first common B-electrode pin  407 A in the second column on the fourth metal wiring layer  40 . The corresponding conductive via D 21  in the third column of pixel units is electrically connected to the first common B-electrode pin  408 A in the third column on the fourth metal wiring layer  40 . The corresponding conductive via D 21  in the fourth column of pixel units is electrically connected to the first common B-electrode pin  409 A in the fourth column on the fourth metal wiring layer  40 . 
     The third B-electrode pad  103 C on the first metal wiring layer  10  is electrically connected to the conductive via D 4 , a third metal wire  302  is electrically connected to the conductive via D 4  penetrating from the first metal wiring layer  10  to the third metal wiring layer  30  and electrically connected to a conductive via D 41  penetrating the third metal wiring layer  30  and the fourth metal wiring layer  40 , and the corresponding conductive via D 41  in the first column of pixel units is electrically connected to the third common B-electrode pin  406 C in the first column on the fourth metal wiring layer  40 . The corresponding conductive via D 41  in the second column of pixel units is electrically connected to the third common B-electrode pin  407 C in the second column on the fourth metal wiring layer  40 . The corresponding conductive via D 41  in the third column of pixel units is electrically connected to the third common B-electrode pin  408 C in the third column on the fourth metal wiring layer  40 . The corresponding conductive via D 41  in the fourth column of pixel units is electrically connected to the third common B-electrode pin  409 C in the fourth column on the fourth metal wiring layer  40 . 
     In an embodiment, in the case where N=4, a metal wire connecting the second B-electrode pad corresponding to each column of pixel units is disposed on the second metal wiring layer. 
       FIG.  5    is a structural diagram of a second metal wiring layer according to an embodiment of the present application. Referring to  FIGS.  4  and  5   , the second B-electrode pad  103 B on the first metal wiring layer  10  is electrically connected to the conductive via D 3  penetrating the first metal wiring layer  10  and the second metal wiring layer  20 , a second metal wire  201  is electrically connected to the conductive via D 3  and electrically connected to a conductive via D 31  penetrating the second metal wiring layer  20  and the fourth metal wiring layer  40 , and the corresponding conductive via D 31  in the first column of pixel units is electrically connected to the second common B-electrode pin  406 B in the first column on the fourth metal wiring layer  40 . The corresponding conductive via D 31  in the second column of pixel units is electrically connected to the second common B-electrode pin  407 B in the second column on the fourth metal wiring layer  40 . The corresponding conductive via D 31  in the third column of pixel units is electrically connected to the second common B-electrode pin  408 B in the third column on the fourth metal wiring layer  40 . The corresponding conductive via D 31  in the fourth column of pixel units is electrically connected to the second common B-electrode pin  409 B in the fourth column on the fourth metal wiring layer  40 . 
     In an embodiment, an identification mark for identifying electrodes of pins is disposed on the insulating plate in contact with an N-th metal wiring layer. 
     Referring to  FIG.  4   , an identification mark for identifying electrodes of pins is disposed on the insulating plate in contact with the fourth metal wiring layer. In an embodiment, an insulating layer is disposed on a side of the fourth metal wiring layer facing away from the insulating plate. The material of the insulating layer includes white oil, resin, green oil or the like for the purpose of insulation and protection. The insulating layer consists of two different colors of insulating material, such as white oil and green oil, and a dividing line of the two different colors of insulating material divides the insulating layer into two parts of different colors, forming an identification mark for identifying the electrodes of the pins. 
     In an embodiment, the insulating layer (such as white oil) may be coated on a side of the fourth metal wiring layer facing away from the insulating plate, and then an insulating material (such as green oil) with quite a different color from the color of the insulating layer is coated on the surface of the insulating layer, where the shape of the coating may be a triangle or another shape for identifying the electrodes of the pins. 
     In an embodiment, an identification mark  410  that is used for identifying the electrodes of the pins and is made of the same material as the common A-electrode pins and the common B-electrode pins may be disposed on the insulating plate in contact with the N-th metal wiring layer and the identification mark  410  is not electrically connected. A shape of the identification mark is different from a shape of the common A-electrode pin and a shape of the common B-electrode pin. A distance between every two adjacent ones of the identification mark, the m common A-electrode pins, and the 3n common B-electrode pins is the same. 
     In an embodiment, in the preceding embodiments, the conductive via is filled with insulating material, and the insulating material does not extend beyond upper and lower surfaces of the circuit board. The insulating material includes resin or green oil and does not exceed out from the upper and lower surfaces of the circuit board. Filling is performed in this manner so that a contact area between the encapsulation material and the circuit board is increased during the subsequent device encapsulation, thereby strengthening the adhesion between the encapsulation material and the circuit board and improving the sealing performance. 
     In an embodiment, the conductive vias in the embodiments of the present application may also be replaced with metal columns (for example, copper columns). In an embodiment, a diameter of the metal column is less than 0.2 mm. Holes are drilled on the PCB, and then electroplating copper deposition is performed. Due to the small aperture, metal copper fills the holes and directly forms the copper columns. The smaller the aperture is, the better the sealing performance of the device is. 
     In the preceding embodiments, ink layers are disposed between pixel regions of adjacent rows and adjacent columns, and the ink may be black ink or other relatively dark ink and formed by the inkjet printing technology, thereby improving the contrast of the device surface and improving the fidelity of the display color. 
     Based on the same concept, an embodiment of the present application further provides a display panel. The display panel includes any LED display unit group described in the preceding schemes.