Patent Publication Number: US-2022216372-A1

Title: Light-emitting chip and device using the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority of Chinese Invention Patent Application No. 202110007123.8, filed on Jan. 5, 2021, and Chinese Invention Patent Application No. 202110500339.8, filed on May 8, 2021. 
     FIELD 
     The disclosure relates to a light-emitting diode (LED), and more particularly to a light-emitting chip and a light-emitting device including the same. The disclosure also relates to an optical-projecting device. 
     BACKGROUND 
     In some applications, light-emitting chips are required to have a high current density. For example, each of the light-emitting chip in the micro projector currently on market may include a blue/green channel that requires a current density of 5 A/mm 2  to 6 A/mm 2 , and a red channel that requires a current density of 4 A/mm 2  to 5 A/mm 2 . In addition, certain light-emitting products may have two 2.0 mm 2  ultra-vertical chips electrically connected in parallel to obtain a 4.0 mm 2  light-emitting surface in the blue channel, and the driving current required for the ultra-vertical chips can reach as high as 20 A. 
     The driving current of a 2.0 mm 2  horizontal and vertical chip may be 10 A at 5 A/mm 2 , and may even reach 12 A at 6 A/mm 2 . In consideration of the fact that the driving current continues to increase, and that selection of a power supply for the product (e.g., a light-emitting chip) becomes more stringent, a horizontal and vertical chip structure have been introduced into the market to be made into a tandem high-voltage low-current light source. 
     With continued increase of current density, the need for chip current distribution and thermal management of chip package have also increased. The use of insulating substrates in horizontal and vertical chips can achieve wafer-level thermoelectric separation. In addition of optimizing via configuration (e.g., blue/green channel(s)) and extension bar configuration (e.g., red channel(s) of a P side up light-emitting chip), electrode distribution also has a significant impact on current distribution. In a product with a high current density demand and/or being made of semiconductor materials with a low carrier mobility, optimization of electrode distribution in a light-emitting chip is required in order to improve current distribution. 
     Referring to  FIGS. 1 and 2 , a conventional light-emitting chip  1  is provided.  FIG. 2  is a perspective front view of the conventional light-emitting chip  1  shown in  FIG. 1 . The conventional light-emitting chip  1  includes an N-type electrode  11  and a P-type electrode  12  (i.e., an electrode layout of 1P1N). The conventional light-emitting chip further includes a semiconductor stack  13  containing a first conductivity type semiconductor layer  131  (N-type), a second conductivity type semiconductor layer (P-type)  132 , and a photoelectric active layer  133  disposed between the first conductivity type semiconductor layer  131  and the second conductivity type semiconductor layer  132 . 
     The N-type electrode  11  is electrically connected to the first conductivity type semiconductor layer  131  through a first electrical connection layer  14 . The first electrical connection layer  14  contacts at least a part of a bottom portion of the first conductivity type semiconductor layer  131 , and is disposed between the first conductivity type semiconductor layer  131  and a permanent substrate  10 . 
     The first electrical connection layer  14  has an exposed portion that is exposed from the first conductivity type semiconductor layer  131  and that forms a first platform  141 . The N-type electrode  11  is formed on the exposed portion (i.e., first platform  141 ) of the first electrical connection layer  14 . The first platform  141  provides an electrical connection (e.g., N-type electrical connection) between the N-type electrode  11  and the first conductivity type semiconductor layer  131 . 
     In some wafer manufacturing processes, the first conductivity type semiconductor layer  131 , the second conductivity type semiconductor layer  132 , and the photoelectric active layer  133  of the semiconductor stack  13  are sequentially grown by vapor deposition on a growth substrate (not shown), and then the growth substrate is peeled off from the semiconductor stack  13 , followed by forming the first electrical connection layer  14  on the first conductivity type semiconductor layer  131 . The first electrical connection layer  14  is then connected to the permanent substrate  10 . 
     A second electrical connection layer  15  might be disposed between the P-type electrode  12  and the second conductivity type semiconductor layer  132 . The second electrical connection layer  15  functions as a second platform  141  for supporting the P-type electrode  12 , and provides electrical connection between the P-type electrode  12  and the second conductivity type semiconductor layer  132 . The second electrical connection layer  15  might include a metal layer, a transparent current spread layer, or a doped semiconductor layer. The P-type electrode  12  and the first electrical connection layer  14  are respectively arranged on opposite sides of the semiconductor stack  13 . An electric current is vertically injected from the P-type electrode  12  into the semiconductor stack  13 , and flows from the semiconductor stack  13  to the first electrical connection layer  14 . The arrows shown in  FIG. 2  indicate schematically a direction of the electric current flowing through the conventional light-emitting chip  1 . Since the P-type electrode  12  has a high current density, it is likely to cause local heat accumulation and brightness reduction problems in the conventional light-emitting chip  1 . 
     SUMMARY 
     Therefore, an object of the disclosure is to provide a light-emitting chip, a light-emitting device, and an optical-projecting device that can alleviate at least one of the drawbacks of the prior art. In this disclosure, the light-emitting chip is provided with an improved current spread, reduced heat accumulation, and improved brightness. 
     According to a first aspect of the present disclosure, the light-emitting chip includes a light-emitting unit, a first electrode unit, and a second electrode unit. The light-emitting unit includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer sequentially arranged along a first direction. The first electrode unit includes two first electrodes which are spaced apart from each other by a first distance, and which are electrically connected to the first conductivity type semiconductor layer. The second electrode unit includes two second electrodes which are electrically connected to the second conductivity type semiconductor layer. The first electrode unit and the second electrode unit are spaced apart from each other by a second distance, and the first distance is greater than the second distance. 
     According to a second aspect of the present disclosure, the light-emitting device includes at least one of the aforesaid light-emitting chip and a circuit board electrically connected to the light-emitting chip. 
     According to a third aspect of the present disclosure, the optical-projecting device includes at least one of the aforesaid light-emitting chip, a support for holding the light-emitting chip, and a power supply for supplying power to the light-emitting chip. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other features and advantages of the disclosure will become apparent in the following detailed description of the embodiments with reference to the accompanying drawings, of which: 
         FIG. 1  is a schematic top view of a conventional light-emitting chip with a P-type electrode and an N-type electrode; 
         FIG. 2  is a perspective front view of the conventional light-emitting chip; 
         FIG. 3  is a schematic top view of a first embodiment of a light-emitting chip having two P-type electrodes and two N-type electrodes according to the present disclosure; 
         FIG. 4  is a perspective cross-sectional view along line A-B of the first embodiment of the light-emitting chip shown in  FIG. 3 ; 
         FIG. 5  is a perspective cross-sectional view of a second embodiment of the light-emitting chip according to the present disclosure; 
         FIG. 6  is a plot showing forward voltages of the conventional light-emitting chip and the second embodiment of the light-emitting chip of the present disclosure at different current densities; 
         FIG. 7  is a plot showing output power of the conventional light-emitting chip and the second embodiment of the light-emitting chip of the present disclosure at different current densities; 
         FIG. 8  is a plot showing peak wavelengths of the conventional light-emitting chip and the second embodiment of the light-emitting chip of the present disclosure at different current densities; 
         FIG. 9  is a plot showing main wavelengths (WLD) of the conventional light-emitting chip and a third embodiment of the light-emitting chip of the present disclosure at different current densities; 
         FIGS. 10 and 11  are schematic top views of a fourth embodiment of the light-emitting chip according to the present disclosure; 
         FIG. 12  is a schematic top view of a fifth embodiment of the light-emitting chip according to the present disclosure; and 
         FIG. 13  is a schematic top view of a sixth embodiment of the light-emitting chip according to the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Before the disclosure is described in greater detail, it should be noted that where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics. 
     Referring to  FIGS. 3 and 4 , a first embodiment of a light-emitting chip  2  according to the present disclosure is provided.  FIG. 4  is a cross-sectional view along line A-B of the light-emitting chip  2  shown in  FIG. 3 . The light-emitting chip  2  includes an electrically insulating substrate  20 , a first electrode unit  21 , a second electrode unit  22 , and a light-emitting unit  23 . The first electrode unit  21 , the second electrode unit  22 , and the light-emitting unit  23  are disposed on the electrically insulating substrate  20 . The light-emitting unit  23  includes a first conductivity type semiconductor layer  231 , an active layer  233 , and a second conductivity type semiconductor layer  232  sequentially arranged along a first direction. The first electrode unit  21  includes two first electrodes  211  which are spaced apart from each other by a first distance (D 1 ) and which are electrically connected to the first conductivity type semiconductor layer  231 . In some embodiments, the first conductivity type semiconductor layer  231  is an N-type semiconductor layer, and the first electrodes  211  are N-type electrodes. The second electrode unit  22  includes two second electrodes  221  which are electrically connected to the second conductivity type semiconductor layer  232 . In some embodiments, the second conductivity type semiconductor layer  232  is a P-type semiconductor layer, and the second electrodes  221  are P-type electrodes. In this embodiment, the first electrode unit  21  and the second electrode unit  22  are spaced apart from each other by a second distance (D 2 ), and the first distance (D 1 ) is greater than the second distance (D 2 ). Each of the first electrodes  211  and the second electrodes  221  has a projection on a surface of the electrically insulating substrate  20 . The second distance (D 2 ) is a minimum distance between the projection of one of the first electrodes  211  and the projection of a corresponding one of the second electrodes  221  that is relatively close to the one of the first electrodes  211 . The two first electrodes  211  are spaced apart from the light-emitting unit  23  and respectively disposed at opposite sides of the light-emitting unit  23 . The two second electrodes  221  are respectively disposed on the light-emitting unit  23  at opposite sides of the light-emitting unit  23 . 
     In some embodiments, the first electrode unit  21  may have a plurality of pairs of the first electrodes  211 , and the second electrode unit  22  may have a plurality of pairs of the second electrodes  221 . In certain embodiments, the light-emitting chip  2  includes 2n of the first electrode unit  21 , n being a positive integer. In certain embodiments, the light-emitting chip  2  includes 2m of the second electrode unit  22 , m being a positive integer. 
     In some embodiments, each of the first electrodes  211  and the second electrodes  221  has a rectangular cross-section perpendicular to the first direction. The rectangular cross-section has a long side and a short side. In certain embodiments, the long side has a length that is about 4 times to about 8 times a length of the short side, which is convenient for multiple wires to bond to a single electrode since the greater the length of the long side of the electrodes (i.e., the first electrodes  211  and the second electrodes  221 ), the larger the area available for connecting the wires. In certain embodiments, the length of the short side ranges from about 30 μm to about 80 μm. 
     In some embodiments, the light-emitting chip  2  may further include a first electrical interconnection layer  24  and a second electrical interconnection layer  25 . The first electrical interconnection layer  24  electrically connects the first electrodes  211  of the first electrode unit  21  to the first conductivity type semiconductor layer  231 . The second electrical interconnection layer  25  electrically connects the second electrodes  221  of the second electrode unit  22  to the second conductivity type semiconductor layer  232 . The first electrical interconnection layer  24  may be disposed under the first conductivity type semiconductor layer  231  and may have an exposed portion exposed from the first conductivity type semiconductor layer  231 . The exposed portion functions as a first platform  241  on which the first electrodes  211  are disposed. The second electrical interconnection layer  25  is formed with a second platform  251  to support the second electrodes  221  (i.e., the second electrodes  221  of the second electrode unit  22  are disposed on the second electrical interconnection layer  25 ). In certain embodiments, the active layer  233  may be disposed between the first electrical interconnection layer  231  and the second electrode unit  22 . In some embodiments, each of the second electrodes  221  has a first surface  2211  and a second surface  2212  opposite to the first surface  2211 . The first surface  2211  of each of the second electrodes  221  faces toward the active layer  233 , and the second surface  2212  of each of the second electrodes  221  faces toward the first direction (i.e., facing a direction away from the active layer  233 ). Each of the first electrodes  211  has a first surface  2111  and a second surface  2112  opposite to the first surface  2111 . The first surface  2111  of each of the first electrodes  211  faces toward the first electrical interconnection layer  24 , and the second surface  2112  of each of the first electrodes  211  faces toward the first direction (i.e., faces a direction away from the first electrical interconnection layer  24 ). In other words, in this embodiment, the light-emitting chip  2  is a lateral light-emitting chip. 
     In some chip manufacturing processes, semiconductor layers (i.e., the first conductivity type semiconductor layer  231 , the active layer  233 , and the second conductivity type semiconductor layer  232 ) are sequential grown on a temporary substrate (not shown) by vapor deposition, and then the temporary substrate are separated from the semiconductor layers by laser or etching techniques. The first electrical interconnection layer  24  is then formed on the first conductivity type semiconductor layer  231 , and the first electrical interconnection layer  24  is bonded to the electrically insulating substrate  20 . In this embodiment, the first electrical interconnection layer  24  is disposed between the electrically insulating substrate  20  and the first conductivity type semiconductor layer  231 . In certain embodiments, the light-emitting chip  2  has an area that ranges from about 1 mm 2  to about 3 mm 2 . To be specific, the electrically insulating substrate  20  of the light-emitting chip  2  has a surface  234  distal from the first electrical interconnection layer  24 . The surface  234  has an area that ranges from about 1 mm 2  to about 3 mm 2 . 
     The arrows shown in  FIG. 4  indicate schematically a direction of electric current paths which are optimized in the light-emitting chip  2 . The electric current flows from the second electrodes  221  into the light-emitting chip  2 . When the lateral current spreading ability of the light-emitting unit  23  is low, the current tends to concentrate mainly under the second electrodes  221 . Therefore, in some embodiments, the first distance (D 1 ) is at least 10 times greater than the second distance (D 2 ) so as to control current distribution in the light-emitting chip  2 . In this embodiment, the light-emitting chip has a rectangular cross-section that is perpendicular to the first direction and that has a long side and a short side. In some embodiments, the first distance (D 1 ) is greater than about 50% of a length of the long side of the rectangular cross-section of the light-emitting chip  2 . The first electrodes  211  and the second electrodes  221  may be made of at least one of a material including, but not limited to, gold, tin, platinum, titanium, chromium, aluminum, and nickel. 
     The light-emitting chip  2  may have great reliability under a high current. In some embodiments, the light-emitting chip  2  may be operated under a current higher than 8 A, and have a current density of greater than about 3 A/mm 2 . 
     In high-current applications, the second electrodes  221  of this embodiment are disposed as far away as possible from each other on the second platform  251 . By combining the aforesaid design of the second electrodes  221  with the design of the first electrodes  211  according to the present disclosure, the current can be laterally distributed on the second platform  251  to reduce current accumulation, which improves photoelectric performance of a product using the light-emitting chip  2  of the present disclosure. 
     Referring to  FIG. 5 , a second embodiment of the light-emitting chip  2  according to the present disclosure is provided. The second embodiment of the light-emitting chip  2  has a structure similar to that of the first embodiment, except that, in the second embodiment, the light-emitting chip  2  is a gallium arsenide-based light-emitting chip in which at least one of the first conductivity type semiconductor layer  231 , the second conductivity type semiconductor layer  232 , and the active layer  233  is a gallium arsenide-based layer made of a gallium arsenide-based material. 
     In this embodiment, the gallium arsenide-based material of the at least one the first conductivity type semiconductor layer  231 , the second conductivity type semiconductor layer  232 , and the active layer  233  has a carrier mobility (e.g., electron mobility) that is usually not greater than about 500 cm 2 /V·s. Since the carrier mobility of the gallium arsenide-based material is lower than that of gallium nitride, the lateral current spreading ability of the current in the light emitting unit  2  is relatively poor. Therefore, the second electrical interconnection layer  25  of the second embodiment of the light-emitting chip  2  disposed between the second conductivity type semiconductor layer  232  and the second electrodes  221  may be made of a metal, a transparent and electrically conductive material, or a doped semiconductor material to improve current spreading. For example, a doped gallium phosphide-based layer with a roughened surface may be disposed between the second conductivity type semiconductor layer  232  and the second electrodes  221  to serve as the second electrical interconnection layer  25 . In certain embodiments, the doped gallium phosphide-based layer has an electron mobility of not greater than about 500 cm 2 /(V·s) and greater than that of the gallium arsenide-based material. The roughened surface of the doped gallium phosphide-based layer and a light-exiting surface of the light-emitting chip  2  face toward a same direction so that light extraction efficiency is improved. In some embodiments, the doped gallium phosphide-based layer has a thickness that ranges from about 2 μm to about 4 μm. In certain embodiments, the doped gallium phosphide-based layer includes magnesium. In some other embodiments, the second electrical interconnection layer  25  may be a transparent current spreading layer. 
     Referring to  FIGS. 6 to 8 , forward voltage, output power, and peak wavelength at different current densities are compared between the conventional light-emitting chip  1  with the 1P1N electrode layout (see  FIGS. 1 and 2 ) and the second embodiment of the light-emitting chip  2  with the 2P2N electrode layout. The conventional light-emitting chip  1  and the second embodiment of the light-emitting chip  2  used for testing in the present disclosure are both red p-side up light-emitting chips. The data show that under the same epitaxial process conditions, the second embodiment of the light-emitting chip (i.e., the light-emitting chip with the 2P2N electrode layout) has an improved photoelectric efficiency and a reduced forward voltage compared with the conventional light-emitting chip  1  (i.e., the light-emitting chip with the 1P1N electrode layout) at a current density below 500 A/cm 2 , that is, below 5 A/mm 2 , with each of the light-emitting chips  1 ,  2  having a chip area of 2 mm 2 . Compared with the conventional light-emitting chip  1 , at 500 A/cm 2 , the forward voltage (V f ) of the second embodiment of the light-emitting chip  2  is reduced by about 0.4 V (shown in  FIG. 6 ), the output power (i.e., brightness) of the second embodiment of the light-emitting chip  2  is increased by about 0.5 W (shown in  FIG. 7 ), a wall-plug efficiency (WPE) of the second embodiment of the light-emitting chip  2  is increased by about 24% (can be inferred from the results shown in  FIGS. 6 and 7 ), and the saturation current of the second embodiment of the light-emitting chip  2  has increased. The aforesaid measured data shows that reliability of the light-emitting chip  2  operating under high current conditions has improved. 
     In addition, the degree of red shift of the second embodiment of the light-emitting chip  2  is slightly different from that of the conventional light-emitting chip  1  as current density increases, which also suggests that the overall current distribution and heat distribution has improved by optimization of the electrode layout, i.e., using the 2P2N electrode layout of the present disclosure. 
     A third embodiment of the light-emitting chip  2  of the present disclosure has a structure similar to that of the second embodiment, except that in the third embodiment, the light-emitting chip  2  is a gallium nitride-based light-emitting chip in which at least one of the first conductivity type semiconductor layer  231 , the second conductivity type semiconductor layer  232 , and the active layer  233  is a gallium nitride-based layer. Referring to  FIG. 9 , due to the 2P2N electrode layout of the third embodiment of the light-emitting chip  2 , the current path in the light-emitting chip  2  is improved, and the WPE is also improved compared with those of the conventional light-emitting chip  1 . Since gallium arsenide has a carrier mobility lower than that of gallium nitride, the overall improvement relative to the 1P1N electrode layout may not be as large as that of the gallium arsenide-based light-emitting chip  2  disclosed in the second embodiment. 
     In order to meet the packaging requirements of a high-voltage device or a series connecting device, a fourth embodiment of the light-emitting chip  2 , which is a light-emitting device including the light-emitting chip  2  of the present disclosure, is provided. The light-emitting device includes a plurality of the light-emitting chips  2 , and the light-emitting chips  2  are electrically connected to each other. Referring to  FIG. 10 , the light-emitting chips  2  are electrically connected by wires  3 . Each of the light-emitting chips  2  has a structure the same as any of the first to third embodiments. Since the first electrodes  211  and the second electrodes  221  are located at opposite sides of the light-emitting unit  23 , such design facilitates wire connection between the light-emitting chips  2  of the light-emitting device, which simplifies circuit design of the light-emitting device and shortens wiring distance. 
     Referring to  FIG. 11 , as mentioned in the first embodiment, each of the first electrodes  211  and the second electrodes  221  of the light-emitting device has the rectangular cross-section, which has the long side and the short side. In certain embodiments, the short side has a length that ranges from about 30 μm to about 80 μm. When the light-emitting device is applied with a high current, for example, a current greater than 3 A, multiple wires  3  are used for shunting the current. 
     To be specific, in this embodiment, two light-emitting chips  2  are connected in series in the light-emitting device. In this embodiment, four wires  3  are preferably used to connect each of the electrodes (i.e., the first and second electrodes  211 ,  221 ) and the circuit board  4 , and the four wires  3  are designed to shunt the input current. 
     In some embodiments, connection between the light-emitting chips  2  of the light-emitting device can be altered according to the locations of the first and second electrodes  211 ,  221 . 
     Referring to  FIG. 12 , a fifth embodiment of the light-emitting chip  2  of the present disclosure is provided. The fifth embodiment of the light-emitting chip  2  has a structure similar to that of the first embodiment, except that in the fifth embodiment, the first electrodes  211  of the first electrode unit  21  are arranged diagonally with respect to the light-emitting unit  23 , disposed at opposite sides of the light-emitting unit  23 , and are spaced apart from the light-emitting unit  23  and the second electrodes  221 . The second electrodes  221  of the second electrode unit  22  are arranged diagonally at opposite sides of the light-emitting unit  23 , disposed on the light-emitting unit  23 , and are spaced apart from the first electrodes  211 . The distance (D 1 ) between the first electrodes  211  is greater than the distance (D 2 ) between the one of the first electrodes  211  and the second electrode  212  adjacent to the first electrode  211 . 
     Referring to  FIG. 13 , a sixth embodiment of the light-emitting chip  2  of the present disclosure is provided. By removing a portion of the light-emitting unit  23  to expose the first electrical interconnection layer  24 , a plurality of the first platforms  241  (i.e., exposed portions of the first electrical interconnection layer  24 ) are formed and are arranged at intervals at one side of the light-emitting unit  23 . In this embodiment, the first electrodes  211  and the second electrodes  221  are alternately arranged at one side of the light-emitting unit  23  and are spaced apart from each other. The distance (D 1 ) between the first electrodes  211  is greater than the distance (D 2 ) between one of the first electrodes  211  and a corresponding one of the second electrodes  221  that is adjacent to the one of the first electrodes  211 . 
     An optical-projecting device including one of the light-emitting chips  2  and the light-emitting devices disclosed in the first to sixth embodiments of the present disclosure is also disclosed. To be specific, the optical-projecting device includes one of the light-emitting chips  2  and the light-emitting devices disclosed in the first to sixth embodiments, a support for holding the light-emitting chip  2  and/or the light-emitting device, and a power supply for supplying power to the light-emitting chip  2  and/or the light-emitting device. The support may be, but not limited to, a box or a frame structure. 
     The embodiments of the present disclosure have the following advantages. The light-emitting chip of the present disclosure is mainly used for producing gallium arsenide-based epitaxial products that emits red light, and is designed so that under a high current density, the light-emitting chip has a reduced working voltage, an improved brightness, an improved photoelectric conversion efficiency, and an increased saturation current. In addition, there is a slight difference in the degree of red shift of the light-emitting chip as current density increases, which also supports the fact that optimization of electrode distribution according to the present disclosure improves overall current distribution and heat distribution of the light-emitting chip. The light-emitting chip of the present disclosure may also be used for producing gallium nitride-based epitaxial products. 
     In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiments. It will be apparent, however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. It should also be appreciated that reference throughout this specification to “one embodiment,” “an embodiment,” an embodiment with an indication of an ordinal number and so forth means that a particular feature, structure, or characteristic may be included in the practice of the disclosure. It should be further appreciated that in the description, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects, and that one or more features or specific details from one embodiment may be practiced together with one or more features or specific details from another embodiment, where appropriate, in the practice of the disclosure. 
     While the disclosure has been described in connection with what are considered the exemplary embodiments, it is understood that this disclosure is not limited to the disclosed embodiment(s) but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.