Patent Publication Number: US-3878482-A

Title: Wide-band, voltage controlled oscillator utilizing complimentary metal oxide semiconductor integrated circuits and a constant current MOS-FET field effect transistor

Description:
United States Patent [191 Schowe, Jr.  
 [ 51 Apr. 15, 1975 [75] Inventor: Lester F. Schowe, Jr., Endwell, N.Y.  
 [73] Assignee: General Electric Company,  
 Binghamton, N.Y.  
 [22] Filed: Oct. 4, 1973 [21] Appl. No.: 403,472  
 [52] US. Cl. 331/108 D; 331/111 [51] Int. Cl. H03k 3/282 [58] Field of Search 331/108, 111, 113  
 [56] References Cited UNITED STATES PATENTS 11/1972 Steudel 331/108 D OTHER PUBLICATIONS RCA Publication, Digital Integrated Circuits, Mar. 1971, pgs. 353-360.  
 Primary Examiner.lohn Kominski Attorney, Agent, or Firm-l. David Blumenfeld [5 7] ABSTRACT A wide-band, voltage controlled oscillator is described which has a frequency range of six decades. The voltage controlled oscillator (VCO), which uses complementary metal oxide, semiconductor field effect transistor elements (C-MOS-FETs), is basically an astable multivibrator which is operated from a voltage controlled, variable amplitude, constant current source. The constant current source includes a p-channel MOS-PET operated in a saturated mode to provide a constant current which may be selectively varied as a function of the gate to source voltage. The current source is coupled to a capacitor storage element through a pair of C-MOS-FETs which selectively establish a conducting path between the capacitor and the constant current source to charge and discharge the capacitor. The C-MOS-FET elements through which the capacitor charges and discharges are controlled by a C-MOS-FET switch means which is actuated in response to the voltage level on the capacitor. By utilizing a constant current source to charge the capacitor, linear charging is easily achieved. Furthermore, the rate at which the capacitor is charged, and hence, the oscillator frequency, may be readily varied over a wide range of values by varying the current level as a function of the input voltage applied to the gate of the constant current p-channel MOS-PET. In one example, a VCO is described which is capable of operating over a frequency range from 5 Hz to 5.5 MHz, and may, in one application described herein, form part of a Phase Locked Loop which is capable of operating over a dynamic frequency range of five decades, i.e., 50 Hz to 5 MHz.  
 8 Claims, 3 Drawing Figures WIDE-BAND. VOLTAGE CONTROLLED OSCILLATOR UTILIZING COMPLIMENTARY METAL OXIDE SEMICONDUCTOR INTEGRATED CIRCUITS AND A CONSTANT CURRENT MOS-FET FIELD EFFECT TRANSISTOR The instant invention relates to a voltage controlled oscillator (VCO) useful in a Phase Locked Loop. and more particularly, to a voltage controlled oscillator which has a very wide dynamic frequency range and which may be constructed in the form of an integrated circuit using complementary, metal oxide semiconductor. field effect transistors (C-MOS-FET&#39;s).  
  Voltage controlled oscillator circuits. as the name indicates. are signal generators which produce output signals. the frequency of which vary as a function of an input control voltage. Such voltage controlled oscillators have a variety of applications in measuring and sensing circuits; in Phase Locked Loops; and. in fact, in any situation where a variable frequency output signal is required as a function of an input voltage. The prior art voltage controlled oscillators (VCO) have. however been characterized by a fairly limited frequency range. Typically. prior art VCOs have a dynamic frequency range limited to half a decade so that the oscillator frequency excursion is limited to a range of about 5 to 1. This limited operational range obviously circumscribes the usefulness of the VCO in many applications. Thus. there is a need for a voltage controlled oscillator which has a very wide dynamic frequency range. i.e.. several decades or more. which is relatively uncomplicated from a circuit standpoint. and which. preferably. may be fabricated on a single integrated circuit chip.  
  It is therefore a primary objective of the instant invention to provide a wide range. voltage controlled os cillator having a dynamic frequency range of several decades.  
  Another objective of the invention is to provide a wide range voltage controlled oscillator which has a dynamic frequency range of at least 6 decades.  
  Still another objective of the invention is to provide a wide range voltage controlled oscillator which utilizes integrated circuit components of the metal oxide. semiconductor (MOS) type.  
 A further objective of the invention is to provide a wide range. voltage controlled oscillator which utilizes metal oxide. semiconductor components which may be fabricated and a single integrated circuit chip.  
  Yet another objective of the invention is to provide a wide range. voltage controlled. oscillator utilizing complementary. metal oxide. semiconductor (C-MOS) components which include a voltage controlled constant current source.  
  Still a further objective of the invention is to provide a phase locked loop utilizing a voltage controlled oscillator having a wide dynamic frequency range and constructed of metal oxide. semiconductor integrated circuits.  
  Yet a further objective of the invention is to produce a wide range voltage controlled oscillator which minimizes circuit complexity. may be fabricated by integrated circuit techniques. and is easy to manufacture.  
  Other objectives and advantages of the invention will become apparent as the description thereof proceeds.  
  The various objectives and advantages of the invention are realized in an arrangement in which a plurality of complementary. metal oxide. semiconductor field effect transistor pairs (hereinafter referred to as C- MOS-FET&#39;s) mounted on a single chip or substrate are interconnected with a storage capacitor in an astable multivibrator configuration. One of the C-MOS field effect transistors of one pair is utilized as a saturated constant current source. a second C-MOS-FET pair alternately establishes a charging and discharging path for one side of the capacitor, and the remaining C- MOS-FET pair is utilized as a switching element for controlling the charge and discharge path and also for connecting the storage capacitor to different reference potentials. A voltage sensing gating or switch element is connected between the capacitor and the switching elements to initiate switching whenever the voltage across the capacitor reaches a predetermined level or threshold. thereby instantaneously switching the capacitor connection to produce alternate charging and discharging of the capacitor.  
  By varying the voltage applied to the constant current source. the level of current from the constant current source may be selectively varied thereby varying the time constant or charging rate of the capacitor and hence. the frequency of the output from the voltage controlled oscillator.  
  The novel features which are believed to be characteristic of this invention are set forth with particularity in the appended claims. The invention itself. however. both as to its organization and mode of operation. together with further objectives and advantages. may best be understood by reference to the following description taken in connection with the according drawing in which:  
  FIG. 1 is a circuit diagram of the voltage controlled oscillator of the instant invention.  
  FIG. 2a and b are wave form diagrams useful in understanding the operation of the voltage controlled oscillator.  
  FIG. 3 is a block diagram of a phase locked loop including the voltage controlled oscillator of the instant invention.  
  The voltage controlled oscillator embodying the instant inventionis shown in FIG. 1 and consists of a plurality of C-MOS-FET pairs ll, 12 and 13 mounted on a common substrate or chip 10; a capacitor 16; a NAND gate 21 and buffer 22. Although the circuit implementation is shown using standard C-MOS integrated circuits, it will be apparent that the invention is not limited thereto since the circuit can be implemented using a single integrated circuit chip. The benefits and advantages which flow from fabricating the entire assembly on a single chip are apparent and will obviously result in a smaller. more compact device.  
  Each of the C-MOS-FET pairs 11, 12 and 13 includes a p-channel enhancement MOS-FET. Q Q and Q and an n-channel enhancement MOS-FET Q Q and Q C-MOS-FET pair 11 consists of p-channel MOS- FET Q. and n-channel MOS-FET Q connected in series across the power supply while C-MOS-FET pair 12 consists ofp and n-channel MOS-FETs Q2 and Q connected in series between +V,,,, and V C-MOS-FET pair 13 consists ofp and n-channel MOS-FETs Q3 and Q. connected in series between MOS-FET Q1 of C- MOS-FET pair 11 and V with the source electrode of 0:; connected to drain electrode 15 of MOS-FET Q, via lead 17 while the source electrode of MOS-FET O is connected to V P-channel MOS-FET Q functions as a voltage controlled, constant current source and to this end. the gate electrode of p-channel MOS-FET Q is connected to an input terminal 14 which has a suitable control voltage impressed thereon. The drain source voltages +V and -V are of such polarity and magnitude that p-channel MOS-FET O is biased to operate in the saturated region and thus acts as a constant current source for any given input voltage between +V,,,, and V That is, the p-channel MOS-FET is biased into saturation so that the magnitude of the saturation drain current 1,, flowing at drain electrode 15 is constant for a given gate-source voltage applied at input terminal 14. However, the magnitude of the saturated drain current may be varied by varying the gate to source voltage V,. applied at input terminal 14 and thus, the level of the constant drain current 1,, may be controlled by varying V It will be apparent that n-channel MOS-FET Q, of C-MOS-FET pair 11 is not utilized as part of the constant current source and could be dispensed with. However, since it is part of a standard C-MOS-FET pair, it is left in place on the chip but not utilized.  
  Voltage controlled constant current source O is connected to storage capacitor 16 through C-MOS-FET pair 13 to charge the capacitor at a rate proportional to the magnitude of drain current l,,. The complementary p and n channel transistor Q3 and Q alternately establish a conducting path between the capacitor and constant current source Q and between the capacitor and a reference current source to permit selective charging and discharging of capacitor 16. Since the source electrode of p-channel MOS-FET Q; is connected to the drain electrode of p-channel transistor Q, by lead 17, and the drain electrode of O is connected directly to one side of capacitor 16 (shown as point A) by lead 18, it is obvious that the constant current source Q, is connected to capacitor 16 whenever Q conducts.  
  Alternatively, when n-channel MOS-FET Q is in the conducting state, capacitor 16 is connected to Q which functions as a fixed reference current source. Thus, with p-channel MOS-FET Q conducting, the current 1,, from voltage controlled constant current source Q flows through MOS-FET Q and over lead 18 to charge capacitor 16. The rate at which capacitor 16 charges is a function of the amplitude of the drain current 1,, which in turn, may be varied by the gate to source voltage V impressed on the gate of Q When the conducting states of transistors Q and Q reverse to turn-off p-channel MOS-FET Q and drive n-channel MOS-FET Q, into conduction, point A and capacitor 16 are connected by lead 18 to 0,, so that capacitor 16 discharges at a rate determined by the maximum drain current of n-channel MOS-FET Q The C-MOS-FET pair 13 consisting of MOS-FET transistors Q and Q thus functions as a charging and discharging path for capacitor 16 and controls the flow of current to the capacitor.  
  The conducting states of Q3 and Q..- in the charging and discharging path are controlled by a switching means which responds to the voltage level on capacitor 16 so that the circuit functions essentially as a freerunning astable multivibrator. To this end, the control or gate electrodes of the C-MOS-FET pair 12, which includes p-channel MOS-FET Q and n-channel MOS- FET connected in series between +V,,,, and V are coupled to point A of capacitor 16 through NAND Gate 21 and the output drain electrodes coupled to the gate electrodes of MOS-FET transistors Q1; and Q6 and to the other side of capacitor 16 (shown as point B). When n-channel MOS-FET Q; is in the conducting state, the voltage at the drain electrodes is essentially the voltage at the negative terminal V As a result, p-channel MOS-FET transistor O3 is driven into conduction connecting constant current source O to point A of storage capacitor 16. Alternatively, when p-MOS- FET transistor O is conducting the positive +V,,,, voltage is applied to the gate electrodes of transistors Q and Q driving the n-channel MOS-FET Q into con duction and connecting point A of the storage capacitor to &#39;V q5 and discharging the capacitor at a rate determined by the drain current of the n-channel MOS- FET Q,;.  
  A pair of protective diodes l9 and 20, which in actuality, are part of the internal protective circuits of transistors Q3 and Q are connected in series across +V,,,, and V and their junction is connected to point A, Le, to the lower plate of capacitor 16. The cathode of diode 19 and the anode of diode 20 are respectively connected to the positive +V,,,, terminal and the negative V terminal so that they are normally reverse biased. Diodes 19 and 20 conduct only if the voltage at point A exceeds +V,,,, or V thereby limiting the excursion of the voltage at point A of capacitor 16. Whenever point A becomes more positive than +V,,,,, diode l9 conducts and similarly, when point A becomes more negative than V diode 20 conducts. Thus, the positive excursion of point A which is controlled by diode 19 is limited to +V,,,, plus the forward voltage drop of diode 19, which is approximately 1 volt. i.e., (V,,,, 1). Similarly, the negative excursion of point A which is controlled by diode 20 is limited to the negative voltage -V less the forward voltage drop of diode 20, i.e., V,s.s&#39; l).  
  The switching of MOS-FET&#39;S Q and 0;, which form part of the oscillator switching means is controlled by a voltage sensitive logic element 21 which is shown as a NAND gate having its two input terminals connected to point A and its output connected to the gate electrodes of MOS-FETs Q and Q Whenever voltage at point A is below a reference voltage V which controls switching of gate 21 and which may, for example, be ground potential, the output of NAND gate 21 is positive. With the output of NAND gate positive, n-channel MOS-FET O is biased into conduction. The output O.-, which is connected to point B of capacitor 16 and to the gates of Q and O is essentially at V and Q3 is conducting. Whenever the voltage at point A exceeds the threshold level V the output of NAND gate 21 becomes negative thereby driving p-channel MOS-FET Q into conduction and n-channel MOS-FET Q into the non-conducting state. This connects point B and the gate electrodes of Q and Q to the positive +V,,,, terminal through MOS-FET Q As the conducting states of Q and Q,-, are reversed, MOS-FETs Q and Q,; are similarly switched to connect point A of capacitor 16 either to constant current source Q through p channel MOS-FET 0;; or to n-channel MOS-FET Q The operation of the voltage controlled oscillator of FIG. 1 may be best understood in connection with the wave form diagrams illustrated in FIGS. 2a and 2b which show the variations of the voltages at points A and B of capacitor 16 and hence, the manner in which the frequency of the oscillator may be varied as a function of the input voltage to terminal 14. FIG. 2a illustrates the voltage variations at point A and the lower plate of capacitor 16 and FIG. 2b illustrates the voltage variations at point B and the upper plate of capacitor 16 with the voltage variations at point B representing the output of the oscillator which is coupled through a buffer 22 to terminal 23. At time 1,, as shown in FIG. 2a. the voltage at point A is at some value which is more negative than the threshold voltage V for NAND gate 21. Consequently. the output of the voltage sensitive logic element represented by NAND gate 21 is positive. N-channel MOS-FET Q, is therefore in the conducting state connecting point B to the V terminal so that the upper plate B of capacitor 16 is, as illustrated in FIG. 2b, clamped at V The negative voltage V at point B also controls charging and discharging path formed by C-MOS-FET pair 13 so that p-channel MOS-FET Q, is conducting and the n-channel MOS- FET 0,, is non-conducting. With Q3 Conducting, the lower plate of capacitor 16, i.e.. point A, is connected to the source of constant current 1,, and capacitor 16 is charging in the positive direction so that point A becomes progressively more positive relative to point B. Capacitor l6 continues to charge in the positive direction until at time 1,, the voltage across the capacitor is sufficiently large that point A reaches the threshold voltage V As point A becomes more positive than V,,, which is the logic threshold of the logic element 21&#39;, the output of NAND gate 21 switches and goes negative so that n-channel MOS-FET Q,-, becomes non-conducting and p-channel MOS-FET O is driven into the conducting state. As a result, the voltage at the output of MOS- FETs O and Q,-, goes from approximately V to +V,,,,. Hence, at time I,, point B is driven almost instantaneously from V to +V,,,,.  
  As point B goes from V to +V,,,, at 1,, p-channel transistor 0;, is turned off and n-channel MOS-FET 0,, is switched into conduction connecting point A to V Even though n-channel transistor Q is now conducting, capacitor 16 cannot discharge instantaneously so that the voltage at point A goes sharply positive at 1,.  
  That is, the transition at point B of capacitor 16 from -V to +V,,,, causes point A to be instantly driven in a positive direction by an amount AV, equal to AV, VD!) (-V where V, is equal to the transition voltage at point B.  
  Point A does not, however. rise to the full value of V AV, since diode 19 is driven into conduction when point A exceeds +V,,,, so that the excursion at point A is clamped at +V,,,, 1 volt, i.e., +V,,,, plus the forward voltage drop of diode 19 in its conducting state. Thus. as may be seen in FIGS. 2a and 2b, at 1,. point B is driven to +V,,,, and point A is driven to +V,,,, 1 volt.  
  Almost immediately thereafter at time 1 (for clarity the interval between I, and t, in FIG. 2a is exaggerated) capacitor 16 begins to discharge through n-channel MOS-FET 0,, at a rate determined by the maximum drain current of Q As capacitor 16 discharges. the voltage at point A goes in a negative direction. At the voltage at point A again reaches and passes the threshold voltage V,,. The input to logic element 21 again goes through the threshold in the negative direction and the output of NAND gate 21 goes positive. As the output from NAND gate 21 goes positive, the conducting states of C-MOS-FETs Q and Q, are again switched so that n-channel MOS-FET Q conducts and p-channel MOS-FET Q becomes non-conducting and point B is again connected to the negative -V,, terminal. Similarly, the conducting states of the C-MOS- FETs Q and O in the charging and discharging path are switched so that n-channel MOS-FET Q is driven into the non-conducting state and p-channel MOS-FET 0;, into conduction again connecting point A to constant current source Q,. As the voltage at point B is switched to V point A is instantaneously driven negative by an amount equal to AV, Since capacitor C, cannot charge instantaneously at I, when p-channel MOS-FET Q, is driven into conduction, the voltage at point A goes instantaneously negative toward V AV,. However, the voltage excursion of point A in the negative direction is limited by diode 20 so that point A goes to negative by an amount equal to V plus the forward drop across diode, or, lV 1 I volts. Capacitor 16 now begins to charge from constant current source Q, and the voltage across capacitor 16 and the voltage at point A again begins going in the positive direction. This process is repeated since the system is free-running and dependent on the voltage at point A to initiate switching.  
  The time required for capacitor 16 to charge so that point A again reaches the threshold voltage V is obviously a function of the magnitude of the current 1,, from constant current source Q, since the capacitance is fixed for any given circuit. The period T as will be shown in detail later, varies with 1,, and is defined by the expression T (V ,-V,,-l X /I Since V V and C, are fixed for any given circuit configuration. it can be seen that the period T and hence, the pulse rate is determined by the constant current source Q, since any changes in the magnitude of l,, as a function of the input voltage controls the period and hence, the repetition frequency of the oscillator output. It will also be noted that since the capacitor charges from a current source which has a constant output current for any given level of input voltage, the charging and discharging of the capacitor is linear and may be readily varied by varying the level of the current.  
  As pointed out above. the time period for charging capacitor 16 and hence. the repetition frequency of the pulse rate is controlled by the magnitude of the drain current I from constant current source Q, and hence. may be controlled by the input voltage. This may be readily seen from the following analysis. The voltage level on capacitor 16 is defined by the well-known formula:  
 Where Q is the charge on the capacitor, C is the capacitance of capacitor 16 and V is the voltage across the capacitor. The current flowing into capacitor 16 is defined by the equation:  
 The charge Q is therefore the time integral of ldr. i.e..  
 Q I I d! Since the current is constant and equal to the drain current 1,, of pchannel transistor Q l l,, and Q 1,, f (It Since the capacitance is that of capacitor 16 and is fixed for any given oscillator. and the voltage V is determined by the maximum voltage excursion of point A when switching transistor O is switched off and Q; is switched on. namely AV V -lV the formula for the charging period T, of capacitor 16 is Ill For any given circuit the values of V,- and V are fixed so that Consequently.  
 T AV m/ n The period T of the generator thus varies inversely with the drain current 1,, and the repetition rate varies directly with l,,. Hence. the greater the drain current, the smaller the period. T and the greater the repetition frequency of the voltage controlled oscillator.  
  The maximum required outputfrequency (F,,,,,,) for the Worst Case conditions under which the oscillator functions basically determined the value ofC By the Worst Case condition is meant the situation for a given C-MOS-FET and for a given maximum temperature since this establishes the minimum drain current available for a given input voltage to the constant current source. Once the value for C for F,,,,, under the Worst Case condition is established, the voltage controlled oscillator operating range is from the value F value to 6 decades below F,,,,, or in other words. a dynamic range of 6 decades.  
  By definition F,,,,, is the reciprocal of the total period:  
 where T,.,,,,, is the Worst Case value of T,, for the given biasing condition of n-channel transistor Qt; and the given Worst Case temperature conditions. at which the frequency is maximum. Similarly. T,,,,,,, is the Worst Case value of T at the value of input voltage (i.e., gate to source voltage to the constant current source C- MOS-FET) at which the frequency is maximum. i.e.,  
  y/s t) II:  
 ( l l l where V,,, is the threshold voltage of the p-channel transistor. The threshold voltage V is that voltage at which the channel material changes from the original H type to p type. That is. there is a voltage at which a material is electrically neutral (intrinsic) and the channel is neither 11 type nor p type and this voltage is known as the threshold voltage V,,,.  
  T, is a function of C and the minimum l,, of nchannel MOS-FET Q That is, the discharge of capacitor 16 through n-channel MOS-FET Q&#34; under any condition is defined by the equation:  
  m AVA where A VIIII+ l t| T on the other hand is a function of the capacitance of C and the minimum drain current of the p channel current source (I at for the worst temperature case. Consequently T may be defined by the equation:  
 Combining Equations l0. l5 and 17 results in the following expression for F,,,,,,,;  
 C 16 VR The capacitance pf C required to reach a desired value of F,,,,, for any given combination of C-MOS- FET. Worst Case temperature and supply voltages may be calculated from Equation (19) by converting the general formulation into a specific expression for the given component and parameters. To give one example of this procedure, a specific expression for C will be derived for the combination of a CD4007AD C-MOS- FET. a drain voltage V +6v; a source voltage V 6. a logic threshold voltage V 0. a diode forward voltage drop of 1 volt and a Worst Case temperature of 125C.  
  The minimum drain current of a CD4007AD nchannel MOS-FET at 125C is:  
  Ds-u X iO amps The minimum drain current of a CD4007AD pchannel MOS-FET at 125C is For these circuit parameters:  
 The value of capacitance for any F may then be calculated from Equation (24). For example. if the desired F,,,,, SMHz then m7 x 10-&#34; (3.; 5 X 33 PICOFARAD Utilizing the nearest even value of C PICO- FARAD the actual F,,,,,, may be calculated from Equation (24):  
 controlled oscillator as a function of output frequency. For this purpose, T,, will be set at 0 since it has negligible effect on gain at low frequency and tends to make gain linearity more favorable at high frequencies. Consequently. Equation (10) can be rewritten as:  
 The current-voltage relationship of a saturated pchannel C-MOS transistor is:  
  By substituting Equation (26) into Equation (25) and differentiating the rate of change of frequency with respect to gate source voltage may be defined as:  
  a.- (1.4 ia-Pu,  
 From Equation (26) it can be seen that:  
 Substituting Equation (28) into Equation (27):  
 Since F &#34;.1... occurs at mm. q n 5) an now be rewritten as:  
 Utilizing the same CD4007AD C-MOS-FET. the value ofk 0.2 X 10&#34; A/V-. With 1 1.75 X 10 and V 6 volts Equation (32) reduces to:  
 Hz per volt. (33) It can be seen from Equation (33) that the rate of change of frequency with change in the input voltage with constant current source is not linear but varies inversely with the value of capacitance and linearly as the one-half power of the ratio of the operating frequency to the maximum frequency. However. it will be obvious that such a voltage controlled oscillator may be used in an environment where linearity of output is not required.  
  FIG. 3 shows an arrangement in which the voltage controlled oscillator is utilized in a phase locked loop in which a reference frequency is applied to one input ofa phase detector 30 and compared to a feedback signal from the loop. The phase detector generates an error signal proportional to the phase difference between the reference frequency and the feedback signal. The feedback signal is the output of a voltage controlled oscillator of the type described above divided by a factor n. i.e..  
 The output of the phase detector is applied to an integrator 32 which integrates in the positive or negative direction depending on the polarity of the phase error. The change integrator output causes a corresponding change in the control voltage input to voltage controlled oscillator 31 and causes the output frequency of the VCO to change correspondingly in a direction to reduce the phase error. The output of the voltage controlled oscillator is applied to the digital divider 32 which divides the output frequency from the voltage controlled oscillator by a factor n and an output digital divider 33 which divides the output frequency by a factor m. At steady state, the phase difference between F and F is constant and as a result F F The input signal F to digital divider 32 is therefore F nF,.,.,. lf the F signal from the voltage controlled oscillator is now divided by the factor m in digital divider 34 the output frequency F =n/m X F Thus. the wide band voltage controlled oscillator described above can be utilized in a frequency mulitplier/divider or utilizing a phase locked loop of the type shown in FIG. 3 and may be utilized in any number of applications where such mulitpliers/dividers or frequency synthesizers are utilized and operate over as wide frequency range thereby eliminating band switching and all the other alternative means hitherto used for producing a wide band frequency output range from a single oscillator.  
  It will be apparent from the previous description that a novel. voltage controlled oscillator has been described which has an extremely wide dynamic frequency range. a frequency range extending over six decades. In one example. such a wide range voltage controlled oscillator is described which has a frequency range from 5.5 MHz down to 50 Hz. Furthermore, the wide range voltage controlled oscillator is particularly applicable to manufacture through known integrated circuit techniques utilizing a plurality of C-MOS-FET devices which may be mounted on a single substrate or chip.  
  What is claimed as new and desired to be secured by Letters Patent of the United States is:  
 1. A voltage controlled oscillator comprising:  
 a. a voltage controlled constant current source including a Complementary Metal Oxide Semiconductor element;  
 b. an input terminal coupled to said constant current source adapted to receive an input voltage to vary the current level from said source as a function of the input voltage.  
 c. a storage element;  
 d. means including a Complementary Metal Oxide Semiconductor FET pair coupled between said constant current source and said storage element for alternately establishing a charging and discharging path for said storage element one of said FET elements connecting the storage element to said constant current source to charge said capacitor from said source and the other FET of said pair rapidly discharging said capacitor through said FET to a point other than the constant current source.  
 e. semiconductor switching means having an input coupled to said storage element and an output coupled to said means for establishing a charging and discharging path. said switching means being actuated in response to the voltage level on said storage element to connect said storage element intermittently to said constant current source to charge said element at a rate proportional to said current.  
  2. The voltage controlled oscillator according to claim 1 wherein said semiconductor switching means includes a complementary Metal Oxide Semiconductor FET pair having their &#39;gate electrodes coupled to said storage element to control the conducting states of the FET pair in response to the voltage level on said storage element and the drain electrodes of said C-MOS- FET pair being connected to the gate electrodes of the C-MOS-FET pair in said charging and discharging path.  
  3. The voltage controlled oscillator according to claim 1 wherein all the semiconductor elements in said current source, said charging and discharging path and the switching means are Complementary Metal Oxide Semiconductor FETs mounted on a common substrate.  
  4. The voltage controlled oscillator according to claim 1 including a voltage sensitive logic element coupled between said storage element and the input of said switch means, said logic element being responsive to the voltage level on said storage element to actuate the switching means.  
  5. The voltage controlled oscillator according to claim 4 wherein said voltage sensitive logic element is a NAND gate.  
  6. The voltage controlled oscillator according to claim 2 wherein a voltage sensitive logic element is coupled between said storage element and the gate electrodes of the C-MOS-FET pair of said switching means. the polarity of the output from said logic element is reversed when the voltage across said storage exceeds a reference level to switch the conducting states of C-MOS-FET&#39;s of the pair.  
  7. The voltage controlled oscillator according to claim 6 wherein said logic element is a NAND gate.  
  8. The voltage controlled oscillator according to claim 2 wherein the source electrode of one of the FETs in the charging and discharging path is connected to the constant current source, and the drain electrodes both FETs in the charging and discharging path are connected to said storage element whereby said storage element is charged from said constant current source whenever said one of the FETs is in the conducting state.