Patent Publication Number: US-2020294969-A1

Title: Stacked transistors with dielectric between source/drain materials of different strata

Description:
BACKGROUND 
     Conventional integrated circuit devices include a single device layer in which transistors are arranged. Above this device layer are interconnect layers that provide electrical connections between various ones of the transistors in the device layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings. 
         FIGS. 1A-1B  are cross-sectional views of an integrated circuit (IC) structure, in accordance with various embodiments. 
         FIGS. 2A-2B, 3A-3B, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, 10A-10B, 11A-11B, 12A - 12 B,  13 A- 13 B,  14 A- 14 B,  15 A- 15 B,  16 A- 16 B, and  17 A- 17 B are cross-sectional views of stages in an example process of manufacturing the IC structure of  FIG. 1 , in accordance with various embodiments. 
         FIGS. 18A-18B, 19A-19B, 20A-20B, 21A-21B, 22A-22B, 23A-23B, 24, and 25  are cross-sectional views of example IC structures, in accordance with various embodiments. 
         FIG. 26  is a top view of a wafer and dies that may include any of the IC structures disclosed herein, in accordance with any of the embodiments disclosed herein. 
         FIG. 27  is a side, cross-sectional view of an IC device that may include any of the IC structures disclosed herein, in accordance with any of the embodiments disclosed herein. 
         FIG. 28  is a side, cross-sectional view of an IC package that may include any of the IC structures disclosed herein, in accordance with various embodiments. 
         FIG. 29  is a side, cross-sectional view of an IC device assembly that may include any of the IC structures disclosed herein, in accordance with any of the embodiments disclosed herein. 
         FIG. 30  is a block diagram of an example electrical device that may include any of the IC structures disclosed herein, in accordance with any of the embodiments disclosed herein. 
     
    
    
     DETAILED DESCRIPTION 
     Disclosed herein are stacked transistors with dielectric between source/drain materials of different strata, as well as related methods and devices. In some embodiments, an integrated circuit (IC) structure may include stacked strata of transistors, wherein a dielectric material is between source/drain materials of adjacent strata, and the dielectric material is conformal on underlying source/drain material. 
     In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. 
     Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. 
     For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration, and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features. 
     The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, a “package” and an “integrated circuit (IC) package” are synonymous. When used to describe a range of dimensions, the phrase “between X and Y” represents a range that includes X and Y. For convenience, the phrase “ FIG. 1 ” may be used to refer to the collection of drawings of  FIGS. 1A-1B , the phrase “ FIG. 2 ” may be used to refer to the collection of drawings of  FIGS. 2A-2B , etc. 
       FIG. 1  illustrates an IC structure  100 ;  FIG. 1A  is a cross-sectional view through the section A-A of  FIG. 1B , and  FIG. 1B  is a cross-sectional view through the section B-B of  FIG. 1A . In particular,  FIG. 1A  is a cross-sectional view taken across multiple device stacks  128 , and  FIG. 1B  is a cross-sectional view taken along a single device stack  128 . All of the “A” and “B” sub-figures in the accompanying drawings share the perspective of the cross-sectional views of  FIGS. 1A and 1B , respectively. 
     The IC structure  100  includes one or more device stacks  128 , with each device stack  128  including two or more device strata  130 . Although various ones of the accompanying drawings depict a particular number of device stacks  128  (e.g., three) and a particular number of device strata  130  (e.g., two), this is simply for ease of illustration, and an IC structure  100  may include more or fewer transistors stacks  128  and/or more device strata  130 . 
     The device strata  130  in a device stack  128  may be oriented vertically relative to an underlying base  102 ; that is, different ones of the device strata  130  in a device stack  128  may be arrayed perpendicularly to the surface of the base  102 . In  FIG. 1  (and others of the accompanying drawings), the device stratum  130 - 1  is between the device stratum  130 - 2  and the base  102 . Corresponding ones of the device strata  130  of different ones of the device stacks  128  may be aligned; for example, the device stratum  130 - 1  of one device stack  128  may have features aligned with corresponding features of the device stratum  130 - 1  of a different device stack  128 . For ease of illustration, the device strata  130  will largely be discussed herein without reference to a particular device stack  128  of which they are a part. However, some or all of the device strata  130  in one device stack  128  may be different from the corresponding device strata  130  in another device stack  128  (e.g., by selective masking and separate processing of the different device stacks  128 ). 
     The base  102  may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The base  102  may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. The base  102  may include a layer of silicon dioxide on a bulk silicon or gallium arsenide substrate. The base  102  may include a converted layer (e.g., a silicon layer that has been converted to silicon dioxide during an oxygen-based annealing process). In some embodiments, the base  102  may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the base  102 . Although a few examples of materials from which the base  102  may be formed are described here, any material or structure that may serve as a foundation for an IC structure  100  may be used. The base  102  may be part of a singulated die (e.g., the dies  1502  of  FIG. 26 ) or a wafer (e.g., the wafer  1500  of  FIG. 26 ). In some embodiments, the base  102  may itself include an interconnect layer, an insulation layer, a passivation layer, an etch stop layer, additional device layers, etc. 
     Each device stratum  130  may include channel material  106  having a longitudinal axis (into the page from the perspective of  FIG. 1A  and left-right from the perspective of  FIG. 1B ). The channel material  106  of a device stratum may be arranged in any of a number of ways. For example,  FIG. 1  illustrates the channel material  106 - 1  of the device stratum  130 - 1  as including multiple semiconductor wires (e.g., nanowires or nanoribbons), as does the channel material  106 - 2  of the device stratum  130 - 2 . Although various ones of the accompanying drawings depict a particular number of wires in the channel material  106  of a device stratum  130 , this is simply for ease of illustration, and a device stratum  130  may include more or fewer wires as the channel material  106 . In other embodiments, the channel material  106  of one or more of the device strata  130  may include a semiconductor fin instead of or in addition to one or more semiconductor wires; examples of such embodiments are discussed below with reference to  FIGS. 20 and 21 . In some embodiments, the channel material  106  may include silicon and/or germanium. In some embodiments, the channel material  106  may include indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, or further materials classified as group II-VI, III-V, or IV. In some embodiments, the channel material  106  may include a semiconducting oxide (e.g., indium gallium zinc oxide). In some embodiments, the material composition of the channel material  106  used in different ones of the device strata  130  may be different, or may be the same. For example, in some embodiments, the channel material  106  in the device stratum  130 - 1  ( 130 - 2 ) may include silicon while the channel material  106  used in the device stratum  130 - 2  ( 130 - 1 ) may include germanium. In another example, in some embodiments, the channel material  106  in the device stratum  130 - 1  ( 130 - 2 ) may include silicon or germanium while the channel material  106  used in the device stratum  130 - 2  ( 130 - 1 ) may include a III-V material. 
     Source/drain (S/D) material  118  may be in electrical contact with the longitudinal ends of the channel material  106 , allowing current to flow from one portion of S/D material  118  to another portion of S/D material  118  through the channel material  106  (upon application of appropriate electrical potentials to the S/D material  118  through S/D contacts, not shown) during operation. In some embodiments, the material composition of the S/D material  118  used in different ones of the device strata  130  may be different; for example,  FIG. 1  illustrates an S/D material  118 - 1  in the device stratum  130 - 1  and an S/D material  118 - 2  in the device stratum  130 - 2 . In other embodiments, the material composition of the S/D material  118  used in different ones of the device strata  130  may be the same. In a single device stack  128 , the S/D material  118  of different device strata  130  may be electrically isolated, or may be in electrical contact. For example,  FIG. 1B  illustrates a dielectric material  120  disposed between the S/D material  118 - 1  and the S/D material  118 - 2  to electrically isolate the S/D material  118 - 1  from the S/D material  118 - 2 . In other embodiments, the dielectric material  120  may not be present, and the S/D material  118 - 1  may be in contact (physical and electrical) with the S/D material  118 - 2 . Different portions of the S/D material  118  in different device strata  130  may be isolated/coupled to achieve a desired circuit; an example of an IC structure  100  including selective coupling of S/D material  118  in different device strata  130  is illustrated in  FIG. 18  and discussed below. The dielectric material  120  is also discussed in further detail below. 
     In some embodiments, the S/D materials  118  may include a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, S/D materials  118  may include dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D materials  118  may include one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. For p-type metal oxide semiconductor (PMOS) transistors, S/D materials  118  may include, for example, group IV semiconductor materials such as silicon, germanium, silicon germanium, germanium tin, or silicon germanium alloyed with carbon. Example p-type dopants in silicon, silicon germanium, and germanium include boron, gallium, indium, and aluminum. For n-type metal oxide semiconductor (NMOS) transistors, S/D materials  118  may include, for example, group III-V semiconductor materials such as indium, aluminum, arsenic, phosphorous, gallium, and antimony, with some example compounds including indium aluminum arsenide, indium arsenide phosphide, indium gallium arsenide, indium gallium arsenide phosphide, gallium antimonide, gallium aluminum antimonide, indium gallium antimonide, or indium gallium phosphide antimonide. In some embodiments, the S/D material  118  may be comprised of a thin semiconductor region (e.g., 1 nanometer to 10 nanometers in thickness) and a metal region. The thin semiconductor region may be positioned between the metal region and the channel material  106  so that the thin semiconductor region provides the interface between the channel material  106  and the S/D material  118 . Such an embodiment may achieve a low barrier height between the channel material  106  and the S/D material  118 , as well as low contact resistivity (due to the metal region). The metal region may include any suitable metal, such as copper, tungsten, ruthenium, cobalt, titanium, aluminum, or other metals or alloys of multiple metals. In some embodiments, this metal region may partially react with the semiconductor region to form a thin region that includes a compound of the semiconductor and metal (e.g., a silicide or germanide). In some embodiments, the S/D material  118 - 1  may include silicon germanium doped with boron, while the S/D material  118 - 2  may include silicon doped with phosphorous. In some embodiments, the S/D material  118 - 2  may include silicon doped with phosphorous, while the S/D material  118 - 2  may include silicon germanium doped with boron. 
     The dielectric material  120  may be conformal on the upper surface of the underlying S/D material  118  (e.g., the S/D material  118 - 1 ). As used herein, a first material may be “conformal” on a second material if the contours of the first material substantially preserve the contours of the second material. In some embodiments, the thickness  162  of the dielectric material  120  may be between 5 nanometers and 20 nanometers. The dielectric material  120  may be an oxide of a material of the underlying S/D material  118 . For example, if the S/D material  118 - 1  includes silicon and/or germanium, the dielectric material  120  may include silicon oxide and/or germanium oxide, respectively. If the S/D material  118 - 1  includes a III-V material, the dielectric material  120  may include an oxide of that III-V material. 
     In some embodiments, a layer of oxidation catalyst  152  may be conformal on the upper surface of the dielectric material  120 , between the dielectric material  120  and the S/D material  118 - 2 . The thickness  164  of the oxidation catalyst  152  may be between 5 Angstroms and 5 nanometers. The oxidation catalyst  152  may include a metal and oxygen. For example, the oxidation catalyst  152  may include aluminum and oxygen (e.g., in the form of aluminum oxide) or lanthanum and oxygen (e.g., in the form of lanthanum oxide). In other embodiments, as discussed below with reference to  FIG. 23 , no oxidation catalyst  152  may be present in the IC structure  100 . 
     When the S/D material  118  is formed by epitaxial growth, the upper surface of the S/D material  118  may not be flat, but may instead be very irregular, with many undulations. To illustrate this concept, various ones of the accompanying figures depict the upper surface of the S/D material  118 - 1  as irregular. In some embodiments, the variation window  160  of the upper surface of the S/D material  118  (i.e., the vertical distance between the lowest point and the highest point of the upper surface of the S/D material  118 , as shown in  FIG. 1 ), may be greater than 2 nanometers, greater than 5 nanometers, greater than 10 nanometers, or greater than 20 nanometers. In some embodiments, the variation window  160  may be between 2 nanometers and 30 nanometers. The upper surface of the S/D material  118 - 2  may also include undulations, as illustrated for the S/D material  118 - 1 , but such features are omitted from the accompanying drawings for ease of illustration. When the upper surface of the S/D material  118 - 1  exhibits such irregularity, it may be difficult to form a thin layer of insulating material on this surface using conventional deposition techniques. Instead, using such techniques, deposition of a fairly thick layer of insulating material (e.g., having a thickness greater than 20 nanometers) may be required to achieve an adequate layer of the dielectric material  120 . This thickness constraint has therefore limited how small of a z-height can be achieved for a stacked transistor structure using conventional approaches. Disclosed herein are techniques and structures for forming the dielectric material  120  that result in adequate isolation with a thinner layer of insulating material than previously achievable. 
     The channel material  106  may be in contact with a gate dielectric  122 . In some embodiments, the gate dielectric  122  may surround the channel material  106  (e.g., when the channel material  106  includes wires, as shown in  FIG. 1 ), while in other embodiments, the gate dielectric  122  may not surround the channel material  106  (e.g., when the channel material  106  includes a fin, as discussed below with reference to  FIGS. 20 and 21 ). Although a single “gate dielectric  122 ” is used to refer to the gate dielectric present in all of the device strata  130  of the IC structures  100  disclosed herein, the material composition of the gate dielectric  122  used in different ones of the device strata  130  may differ, as desired. The gate dielectric  122  may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric  122  include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric  122  to improve its quality when a high-k material is used. 
     The gate dielectric  122  may be disposed between the channel material  106  and a gate metal  124 . In some embodiments, the gate metal  124  may surround the channel material  106  (e.g., when the channel material  106  includes wires, as shown in  FIG. 1 ), while in other embodiments, the gate metal  124  may not surround the channel material  106  (e.g., when the channel material  106  includes a fin, as discussed below with reference to  FIGS. 20 and 21 ). In some embodiments, the material composition of the gate metal  124  used in different ones of the device strata  130  may be different; for example,  FIG. 1  illustrates a gate metal  124 - 1  in the device stratum  130 - 1  and a gate metal  124 - 2  in the device stratum  130 - 2 . In other embodiments, the material composition of the gate metal  124  used in different ones of the device strata  130  may be the same. Together, the gate metal  124  and the gate dielectric  122  may provide a gate for the associated channel material  106 , with the electrical impedance of the channel material  106  modulated by the electrical potential applied to the associated gate (through gate contacts, not shown). The gate metal  124  may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor of which it is a part is to be a PMOS or an NMOS transistor. In some implementations, the gate metal  124  may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer (e.g., tantalum, tantalum nitride, an aluminum-containing alloy, etc.). In some embodiments, a gate metal  124  may include a resistance-reducing cap layer (e.g., copper, gold, cobalt, or tungsten). For a PMOS transistor, metals that may be used for the gate metal  124  include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed herein with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate metal  124  include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning). In some embodiments, the gate metal  124  may include grading (increasing or decreasing) of the concentration of one or more materials therein. Spacers  116  may separate the gate metal  124  from the proximate S/D material  118 . The spacers  116  may include silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, silicon oxynitride, or silicon oxynitride doped with carbon, for example. Together, a channel material  106 , gate dielectric  122 , gate metal  124 , and associated S/D materials  118  may provide a transistor. 
     The dimensions of the elements of the IC structure  100  may take any suitable values. In some embodiments, the width  136  of the channel material  106  may be between 3 nanometers and 30 nanometers. In some embodiments, the thickness  140  of the channel material  106  may be between 1 nanometer and 500 nanometers (e.g., between 40 nanometers and 400 nanometers when the channel material  106  is a fin, and between 5 nanometers and 40 nanometers when the channel material  106  is a wire). In some embodiments, the thickness  138  of the spacers  116  may be between 6 nanometers and 12 nanometers. In some embodiments in which a device stratum  130  includes semiconductor wires, the spacing  142  between adjacent ones of the wires may be between 5 nanometers and 40 nanometers. In some embodiments, the spacing  144  between channel material  106  of one device stratum  130  and channel material  106  of an adjacent device stratum  130  in the same device stack  128  may be between 5 nanometers and 50 nanometers. In some embodiments in which a device stratum  130  includes semiconductor wires as the channel material  106 , the spacing  142  between adjacent instances of the wires may not be constant between each wire. 
     In some embodiments, the IC structure  100  may be part of a memory device, and transistors of the IC structure  100  may store information in the IC structure  100  or facilitate access to (e.g., read and/or write) storage elements of the memory device. In some embodiments, the IC structure  100  may be part of a processing device. In some embodiments, the IC structure  100  may be part of a device that includes memory and logic devices (e.g., in a single die  1502 , as discussed below), such as a processor and cache. More generally, the IC structures  100  disclosed herein may be part of memory devices, logic devices, or both. 
       FIGS. 2-17  illustrate stages in an example process for manufacturing the IC structure  100  of  FIG. 1 . Although the operations of the process may be illustrated with reference to particular embodiments of the IC structures  100  disclosed herein, the process of  FIGS. 2-17  and variants thereof may be used to form any suitable IC structure  100  (e.g., the IC structures  100  illustrated in  FIGS. 18-25 ). Operations are illustrated a particular number of times and in a particular order in  FIGS. 2-17 , but the operations may be reordered and/or repeated as desired (e.g., with different operations performed in parallel when manufacturing multiple IC structures  100  simultaneously). 
       FIG. 2  illustrates an assembly  200  including a base  102  and a stack of material layers on the base  102 . The stack of material layers may include a set of layers corresponding to the device stratum  130 - 1  and a set of layers corresponding to the device stratum  130 - 2 . The set of layers corresponding to the device stratum  130 - 1  may include layers of the channel material  106 - 1  spaced apart from each other (and from the base  102  and the device stratum  130 - 2 ) by intervening layers of sacrificial material  104 . Similarly, the set of layers corresponding to the device stratum  130 - 2  may include layers of the channel material  106 - 2  spaced apart from each other by intervening layers of sacrificial material  104 . The size and arrangement of the material layers in the assembly  200  corresponds to the desired size and arrangement of the channel material  106  in the IC structure  100 , as will be discussed further below, and thus the material layers in the assembly  200  may vary from the particular embodiment illustrated in  FIG. 2 . The sacrificial material  104  may be any material that may be appropriately selectively removed in later processing operations (as discussed below with reference to  FIG. 15 ). For example, the sacrificial material  104  may be silicon dioxide and the channel material  106  may be silicon or germanium. In another example, the sacrificial material  104  may be gallium arsenide and the channel material  106  may be indium gallium arsenide, germanium, or silicon germanium. The assembly  200  may be formed using any suitable deposition techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a layer transfer process. 
       FIG. 3  illustrates an assembly  205  subsequent to forming fins  146  in the material stack of the assembly  200  ( FIG. 2 ). Standard masking and etch techniques may be used to form the fins  146 , including wet and/or dry etch schemes, as well as isotropic and/or anisotropic etch schemes. The width of the fins  146  may be equal to the width  136  of the channel material  106 , as discussed above. Any suitable number of fins  146  may be included in the assembly  205  (e.g., more or fewer than 3). Although the fins  146  depicted in  FIG. 3  (and others of the accompanying drawings) are perfectly rectangular, this is simply for ease of illustration, and in practical manufacturing settings, the shape of the fins  146  may not be perfectly rectangular. For example, the fins  146  may be tapered, widening toward the base  102 . The top surface of the fins  146  may not be flat, but may be curved, rounding into the side surfaces of the fins  146 . Examples of IC structures  100  including some such non-idealities are discussed below with reference to  FIGS. 24 and 25 . 
       FIG. 4  illustrates an assembly  210  subsequent to forming a conformal layer of the dummy gate dielectric  110  over the assembly  205  ( FIG. 3 ), forming a dummy gate metal  112 , and then depositing a hardmask  114 . The dummy gate metal  112  may extend over the top surfaces of the fins  146 , as shown. The dummy gate dielectric  110  may be formed by any suitable technique (e.g., ALD), and the dummy gate metal  112  and hardmask  114  may be formed using any suitable techniques. The dummy gate dielectric  110  and the dummy gate metal  112  may include any suitable materials (e.g., silicon oxide and polysilicon, respectively). The hardmask  114  may include any suitable materials (e.g., silicon nitride, carbon-doped silicon oxide, or carbon-doped silicon oxynitride). 
       FIG. 5  illustrates an assembly  215  subsequent to patterning the hardmask  114  of the assembly  210  ( FIG. 4 ) into strips that are oriented perpendicular to the longitudinal axis of the fins  146  (into and out of the page in accordance with the perspective of  FIG. 5 ), and then etching the dummy gate metal  112  and dummy gate dielectric  110  using the patterned hardmask  114  as a mask. The locations of the remaining dummy gate metal  112  and dummy gate dielectric  110  may correspond to the locations of the gates in the IC structure  100 , as discussed further below. 
       FIG. 6  illustrates an assembly  220  subsequent to removing the sacrificial material  104  that is not covered by the dummy gate metal  112  and dummy gate dielectric  110  in the assembly  215  ( FIG. 5 ). Any suitable selective etch technique may be used to remove the sacrificial material  104 . 
       FIG. 7  illustrates an assembly  225  subsequent to forming spacers  116  on side faces of the hardmask  114 , dummy gate metal  112 , and dummy gate dielectric  110  of the assembly  220  ( FIG. 6 ), and then removing the channel material  106  that is not covered by the dummy gate metal  112 , the dummy gate dielectric  110 , or spacers  116  to form open volumes  148 . In some embodiments, the “exposed” channel material  106  may not be fully removed in the assembly  225 ; instead, “stubs” may extend into the open volumes  148 , and will ultimately extend into the S/D material  118  in the IC structure  100 , as discussed below with reference to  FIG. 19 . The spacers  116  may be formed by conformally depositing the material of the spacers  116  on the assembly  220 , then directionally etching this material “downwards” to leave the spacers  116  on “vertical” surfaces of the assembly  220  while removing it from “horizontal” surfaces. 
       FIG. 8  illustrates an assembly  230  subsequent to forming S/D material  118 - 1  in the open volumes  148  in the device strata  130 - 1  of the assembly  225  ( FIG. 7 ). The S/D material  118 - 1  may be formed by epitaxial growth, and may include any of the materials discussed herein with reference to the S/D material  118 . For example, the S/D material  118 - 1  may include silicon, germanium, or a III-V material. When the S/D material  118 - 1  will be part of an NMOS transistor, the S/D material  118 - 1  may include an n-type dopant, such as phosphorous, arsenic, antimony, bismuth, or lithium. When the S/D material  118 - 1  will be part of a PMOS transistor, the S/D material  118 - 1  may include a p-type dopant, such as boron, aluminum, gallium, or indium. The upper surface  158  of the S/D material  118 - 1  in the assembly  230  may be coplanar with sacrificial material  104  between the device stratum  130 - 1  and the device stratum  130 - 2 , as shown. As discussed above with reference to  FIG. 1 , the upper surface  158  of the S/D material  118 - 1  may be irregular, having a variation window  160  in accordance with any of the embodiments disclosed herein. 
       FIG. 9  illustrates an assembly  231  subsequent to depositing a conformal layer of oxidation catalyst  152  on the assembly  230  ( FIG. 8 ). The oxidation catalyst  152  may be any material that increases the rate of oxidation of the underlying material when exposed to a desired set of conditions (e.g., during an anneal). The thickness  164  of the oxidation catalyst  152  may take any of the forms discussed above with reference to  FIG. 1 . Any suitable conformal deposition process may be used to deposit the oxidation catalyst  152 , such as ALD. As discussed above, the oxidation catalyst  152  may include a metal and oxygen (e.g., in the form of a metal oxide). Examples of metals that may be included in the oxidation catalyst  152  include aluminum, lanthanum, and copper, among others. As discussed below with reference to  FIG. 13 , the oxidation catalyst  152  may facilitate the oxidation of the underlying material during an anneal process. 
       FIG. 10  illustrates an assembly  232  subsequent to depositing and then recessing a mask material  154  on the assembly  231  ( FIG. 9 ). The mask material  154  may take the form of any of the hardmasks disclosed herein (e.g., a carbon hardmask), and may be recessed to a level that is between the device stratum  130 - 1  and the device stratum  130 - 2  (e.g., coplanar with the sacrificial material  104  between the device strata  130 ). The mask material  154  may protect the oxidation catalyst  152  in the device stratum  130 - 1 , while leaving the oxidation catalyst  152  in the device stratum  130 - 2  exposed. Any suitable technique may be used to deposit and recess the mask material  154 , such as spin-on deposition followed by a recess process. 
       FIG. 11  illustrates an assembly  233  subsequent to removing the exposed oxidation catalyst  152  from the assembly  232  ( FIG. 10 ), leaving the oxidation catalyst  152  protected by the mask material  154  in place. Any suitable technique may be used to remove the exposed oxidation catalyst  152 , such as a wet etch process. 
       FIG. 12  illustrates an assembly  234  subsequent to removing the mask material  154  from the assembly  233  ( FIG. 11 ). Any suitable technique may be used to remove the mask material  154 , such as an ash process (e.g., when the mask material  154  is a carbon hardmask). 
       FIG. 13  illustrates an assembly  235  subsequent to annealing the assembly  234  ( FIG. 12 ) to cause the oxidation of the S/D material  118 - 1  (catalyzed by the oxidation catalyst  152 ); the oxidized S/D material  118 - 1  is the dielectric material  120 . The annealing process may include steam oxidation, forming the dielectric material  120  to a desired thickness  162 . A dielectric material  120  formed in this manner may be conformal on the remaining S/D material  118 , as shown. In some embodiments, the oxidation catalyst  152  may remain on the dielectric material  120  during subsequent processing operations, while in other embodiments, the oxidation catalyst  152  may be removed before further processing is performed (e.g., as discussed below with reference to  FIG. 23 ). Although various ones of the accompanying drawings illustrate dielectric material  120  between all portions of the S/D materials  118 - 1  and the corresponding portions of the S/D materials  118 - 2 , the dielectric material  120  may be formed so as to only be selectively present between various portions of the S/D material  118 - 1  and the S/D material  118 - 2  (e.g., as discussed below with reference to  FIG. 18 ). 
       FIG. 14  illustrates an assembly  236  subsequent to forming S/D material  118 - 2  above the dielectric material  120  and in the device strata  130 - 2 . The S/D material  118 - 2  may be formed by epitaxial growth, as discussed above with reference to the S/D material  118 - 1 . In some embodiments, the S/D material  118 - 1  and the S/D material  118 - 2  may have opposite polarities; the S/D material  118 - 1  may include an n-type dopant (p-type dopant) while the S/D material  118 - 2  includes a p-type dopant (n-type dopant).  FIG. 15  illustrates an assembly  237  subsequent to removing the hardmask  114 , the dummy gate dielectric  110 , and the dummy gate metal  112  from the assembly  236  ( FIG. 14 ). Any suitable etch processes may be used to remove the hardmask  114 , the dummy gate dielectric  110 , and the dummy gate metal  112 . 
       FIG. 16  illustrates an assembly  240  subsequent to forming a conformal layer of the gate dielectric  122  over the assembly  237  ( FIG. 15 ). As shown, the gate dielectric  122  may be formed on the exposed surfaces of the channel material  106 . In embodiments in which the gate dielectric  122  in the device stratum  130 - 1  is different than the gate dielectric  122  in the device stratum  130 - 2 , the gate dielectric  122  for the device stratum  130 - 1  may be initially formed, a sacrificial material may be deposited to cover the gate dielectric  122  in the device stratum  130 - 1 , the initially formed gate dielectric  122  in the device stratum  130 - 2  may be removed, a new gate dielectric  122  for the device stratum  130 - 2  may be formed, and then the sacrificial material may be removed. In some embodiments, the gate dielectric  122  in the device stratum  130 - 1  has the same material composition as the gate dielectric  122  in the device stratum  130 - 2 , but with different thicknesses. For example, a relatively thicker gate dielectric  122  may be used for a high voltage transistor, while a relatively thinner gate dielectric may be used for a logic transistor. 
       FIG. 17  illustrates an assembly  245  subsequent to forming gate metal  124 - 1  around the gate dielectric  122  in the device strata  130 - 1  of the assembly  240  ( FIG. 16 ), and then forming gate metal  124 - 2  around the gate dielectric  122  in the device strata  130 - 2 . In embodiments in which the gate metal  124 - 1  has a same material composition as the gate metal  124 - 2 , the formation of the gate metal  124  be performed in a single operation. The assembly  245  may take the form of the IC structure  100  of  FIG. 1 . Subsequent manufacturing operations, including the formation of conductive contacts to the gate metal  124  and the S/D material  118 , may then be performed. 
       FIGS. 18-25  illustrate additional example IC structures  100 . Any of the features discussed with reference to any of  FIGS. 1 and 18-25  herein may be combined with any other features to form an IC structure  100 . For example, as discussed further below,  FIG. 18  illustrates an embodiment in which the S/D material  118  of different device strata  130  are not isolated from each other, and  FIG. 19  illustrates an embodiment in which the channel material  106  extends into the S/D material  118 . These features of  FIGS. 18 and 19  may be combined so that the S/D material  118  of different device strata  130  in an IC structure  100  are not isolated from each other and the channel material  106  extends into the S/D material  118 . This particular combination is simply an example, and any combination may be used. A number of elements of  FIG. 1  are shared with  FIGS. 18-25 ; for ease of discussion, a description of these elements is not repeated, and these elements may take the form of any of the embodiments disclosed herein. 
       FIG. 18  illustrates an IC structure  100  in which the dielectric material  120  is present between some portions of the S/D material  118 - 1  and the S/D material  118 - 2 , while other portions of the S/D material  118 - 1  and the S/D material  118 - 2  are in physical contact (and thus electrical contact). The selective use of dielectric material  120  may allow desired circuit connections to be made between the S/D material  118 - 1  and the S/D material  118 - 2 ; for example, when the transistors of the device strata  130 - 1  in the dashed box are PMOS transistors, and the transistors of the device strata  130 - 2  in the dashed box are NMOS transistors (or vice versa), the circuit in the dashed box may be an inverter. The dielectric material  120  may be patterned by patterning the mask material  154  to selectively expose the oxidation catalyst  152  on top of the S/D material  118 - 1  in the assembly  232  ( FIG. 10 ) when no dielectric material  120  is desired on that S/D material  118 - 1 ; this exposed oxidation catalyst  152  may then be removed during the operations discussed above with reference to  FIG. 10 , and the newly exposed S/D material  118 - 1  will not significantly oxidize during the annealing process of  FIG. 13  (due to the lack of contact with the oxidation catalyst  152 ). As shown in  FIG. 18 , the upper surface of the S/D material  118 - 1  where no dielectric material  120  is present may be coplanar with the upper surface of the dielectric material  120  on other portions of the S/D material  118 - 1 . 
       FIG. 19  illustrates an IC structure  100  in which the channel material  106  is not “trimmed” to be flush with the outer surface of the spacers  116  (as discussed above with reference to  FIG. 7 ), but instead extends into the S/D material  118 . 
     As noted above, the channel material  106  in different device strata  130  may include one or more wires and/or one or more fins.  FIG. 20  illustrates an IC structure  100  in which the channel material  106 - 1  in the device stratum  130 - 1  is a fin in contact with the base  102  (and thus the gate dielectric  122  and gate metal  124 - 1  does not wrap entirely around the channel material  106 - 1 ), while the channel material  106 - 2  in the device stratum  130 - 2  includes multiple wires (each surrounded by the gate dielectric  122  and the gate metal  124 - 2 ).  FIG. 21  illustrates an IC structure  100  in which the channel material  106 - 1  in the device stratum  130 - 1  includes multiple wires (each surrounded by the gate dielectric  122  and the gate metal  124 - 1 ), while the channel material  106 - 2  in the device stratum  130 - 2  is a fin in contact with an insulating material  156  (and thus the gate dielectric  122  nor the gate metal  124 - 2  contact the channel material  106 - 2  entirely around the channel material  106 - 2 ).  FIG. 22  illustrates an IC structure  100  in which the channel material  106 - 1  in the device stratum  130 - 1  is a fin in contact with the base  102  (and thus the gate dielectric  122  and gate metal  124 - 1  does not wrap entirely around the channel material  106 - 1 ), while the channel material  106 - 2  in the device stratum  130 - 2  is a fin in contact with an insulating material  156  (and thus the gate dielectric  122  nor the gate metal  124 - 2  contact the channel material  106 - 2  entirely around the channel material  106 - 2 ). The IC structures  100  of  FIGS. 20-22  may be formed by adjusting the material stack of the assembly  200  accordingly, and then proceeding with the remainder of the operations discussed above with reference to  FIGS. 3-17 . 
     In some embodiments, the oxidation catalyst  152  on the dielectric material  120  may remain in the IC structure  100 , while in other embodiments, the oxidation catalyst  152  may be removed. Removing the oxidation catalyst  152  may be appropriate when the thickness  164  of the oxidation catalyst  152  is significant enough that removal of the oxidation catalyst  152  may desirably decrease the z-height of the IC structure  100 . Removing the oxidation catalyst  152  may also be appropriate when the oxidation catalyst  152  includes materials that may decompose and/or contaminate nearby structures during further processing. Removing the oxidation catalyst  152  may also be appropriate when the oxidation catalyst  152  is a conductor (e.g., when the oxidation catalyst  152  includes copper oxide). The oxidation catalyst  152  may be removed from the assembly  235  ( FIG. 13 ) using any suitable process, such as a wet clean. 
     As noted above, the IC structures  100  depicted in various ones of the accompanying drawings are shown as having precise rectilinear features, but this assembly for ease of illustration, and devices manufactured using practical manufacturing processes deviate from rectilinearity.  FIG. 24  is a depiction of the IC structure  100  of  FIG. 1  (sharing the perspective of  FIG. 1A ) that includes some of the rounding and tapering that is likely to occur when the IC structure  100  is practically manufactured. Similarly,  FIG. 25  is a depiction of the IC structure  100  of  FIG. 20  (sharing the perspective of  FIG. 16A ) that includes some of the rounding and tapering that is likely to occur when the IC structure  100  is practically manufactured. The IC structures  100  of  FIGS. 24 and 25  include some tapering of the channel materials  106 , with the channel materials  106  widening closer to the base  102  (as discussed above with reference to  FIG. 3 ), as well as rounding of the channel materials  106  themselves. Other non-idealities may also be present in a manufactured IC structure  100 . 
     The IC structures  100  disclosed herein may be included in any suitable electronic component.  FIGS. 26-30  illustrate various examples of apparatuses that may include any of the IC structures  100  disclosed herein. 
       FIG. 26  is a top view of a wafer  1500  and dies  1502  that may include one or more IC structures  100  in accordance with any of the embodiments disclosed herein. The wafer  1500  may be composed of semiconductor material and may include one or more dies  1502  having IC structures formed on a surface of the wafer  1500 . Each of the dies  1502  may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer  1500  may undergo a singulation process in which the dies  1502  are separated from one another to provide discrete “chips” of the semiconductor product. The die  1502  may include one or more IC structures  100  (e.g., as discussed below with reference to  FIG. 27 ), one or more transistors (e.g., some of the transistors of the device region  1604  of  FIG. 27 , discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer  1500  or the die  1502  may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die  1502 . For example, a memory array formed by multiple memory devices may be formed on a same die  1502  as a processing device (e.g., the processing device  1802  of  FIG. 30 ) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array. 
       FIG. 27  is a side, cross-sectional view of an IC device  1600  that may include one or more IC structures  100  in accordance with any of the embodiments disclosed herein. One or more of the IC devices  1600  may be included in one or more dies  1502  ( FIG. 26 ). The IC device  1600  may include a base  102 , which may include some of the wafer  1500  of  FIG. 26  and may be included in a die (e.g., the die  1502  of  FIG. 26 ). The base  102  may take any of the forms disclosed herein. 
     The IC device  1600  may include a device region  1604  including multiple device strata  130  on the base  102 . The device region  1604  may include any of the multi-strata IC structures  100  disclosed herein. Further, the device region  1604  may include regions having only a single device stratum  130 , or regions having different numbers of device strata  130 . For example, one or more regions of the device region  1604  may include the multi-strata IC structures  100  disclosed herein, and other regions of the device region  1604  may include a single device strata  130  including planar transistors (e.g., bipolar junction transistors (BJT), heterojunction bipolar transistors (HBT), or high-electron-mobility transistors (HEMT)) or non-planar transistors (e.g., double-gate transistors, tri-gate transistors, or wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors). The device region  1604  may further include electrical contacts to the gates of the transistors included in the device region  1604  (e.g., to the gate metal  124  of the IC structures  100 ) and to the S/D materials of the transistors included in the device region  1604  (e.g., to the S/D materials  118  of the IC structures  100 ). 
     Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., the transistors) of the device region  1604  through one or more interconnect layers disposed on the device region  1604  (illustrated in  FIG. 27  as interconnect layers  1606 - 1610 ). For example, electrically conductive features of the device region  1604  (e.g., the gate metal  124  and the S/D materials  118 ) may be electrically coupled with the interconnect structures  1628  of the interconnect layers  1606 - 1610 . The one or more interconnect layers  1606 - 1610  may form a metallization stack (also referred to as an “ILD stack”)  1619  of the IC device  1600 . 
     The interconnect structures  1628  may be arranged within the interconnect layers  1606 - 1610  to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures  1628  depicted in  FIG. 27 ). Although a particular number of interconnect layers  1606 - 1610  is depicted in  FIG. 27 , embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted. 
     In some embodiments, the interconnect structures  1628  may include lines  1628   a  and/or vias  1628   b  filled with an electrically conductive material such as a metal. The lines  1628   a  may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the base  102  upon which the device region  1604  is formed. For example, the lines  1628   a  may route electrical signals in a direction in and out of the page from the perspective of  FIG. 27 . The vias  1628   b  may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the base  102  upon which the device region  1604  is formed. In some embodiments, the vias  1628   b  may electrically couple lines  1628   a  of different interconnect layers  1606 - 1610  together. 
     The interconnect layers  1606 - 1610  may include a dielectric material  1626  disposed between the interconnect structures  1628 , as shown in  FIG. 27 . In some embodiments, the dielectric material  1626  disposed between the interconnect structures  1628  in different ones of the interconnect layers  1606 - 1610  may have different compositions; in other embodiments, the composition of the dielectric material  1626  between different interconnect layers  1606 - 1610  may be the same. 
     A first interconnect layer  1606  may be formed above the device region  1604 . In some embodiments, the first interconnect layer  1606  may include lines  1628   a  and/or vias  1628   b , as shown. The lines  1628   a  of the first interconnect layer  1606  may be coupled with contacts (e.g., contacts to the S/D materials  118  of the IC structures  100 ) of the device region  1604 . 
     A second interconnect layer  1608  may be formed above the first interconnect layer  1606 . In some embodiments, the second interconnect layer  1608  may include vias  1628   b  to couple the lines  1628   a  of the second interconnect layer  1608  with the lines  1628   a  of the first interconnect layer  1606 . Although the lines  1628   a  and the vias  1628   b  are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer  1608 ) for the sake of clarity, the lines  1628   a  and the vias  1628   b  may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments. 
     A third interconnect layer  1610  (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer  1608  according to similar techniques and configurations described in connection with the second interconnect layer  1608  or the first interconnect layer  1606 . In some embodiments, the interconnect layers that are “higher up” in the metallization stack  1619  in the IC device  1600  (i.e., farther away from the device region  1604 ) may be thicker. 
     The IC device  1600  may include a solder resist material  1634  (e.g., polyimide or similar material) and one or more conductive contacts  1636  formed on the interconnect layers  1606 - 1610 . In  FIG. 27 , the conductive contacts  1636  are illustrated as taking the form of bond pads. The conductive contacts  1636  may be electrically coupled with the interconnect structures  1628  and configured to route the electrical signals of the transistor(s) of the device region  1604  to other external devices. For example, solder bonds may be formed on the one or more conductive contacts  1636  to mechanically and/or electrically couple a chip including the IC device  1600  with another component (e.g., a circuit board). The IC device  1600  may include additional or alternate structures to route the electrical signals from the interconnect layers  1606 - 1610 ; for example, the conductive contacts  1636  may include other analogous features (e.g., posts) that route the electrical signals to external components. 
       FIG. 28  is a side, cross-sectional view of an example IC package  1650  that may include one or more IC structures  100  in accordance with any of the embodiments disclosed herein. In some embodiments, the IC package  1650  may be a system-in-package (SiP). 
     The package substrate  1652  may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, glass, an organic material, an inorganic material, combinations of organic and inorganic materials, embedded portions formed of different materials, etc.), and may have conductive pathways extending through the dielectric material between the face  1672  and the face  1674 , or between different locations on the face  1672 , and/or between different locations on the face  1674 . These conductive pathways may take the form of any of the interconnects  1628  discussed above with reference to  FIG. 27 . 
     The package substrate  1652  may include conductive contacts  1663  that are coupled to conductive pathways (not shown) through the package substrate  1652 , allowing circuitry within the dies  1656  and/or the interposer  1657  to electrically couple to various ones of the conductive contacts  1664  (or to devices included in the package substrate  1652 , not shown). 
     The IC package  1650  may include an interposer  1657  coupled to the package substrate  1652  via conductive contacts  1661  of the interposer  1657 , first-level interconnects  1665 , and the conductive contacts  1663  of the package substrate  1652 . The first-level interconnects  1665  illustrated in  FIG. 28  are solder bumps, but any suitable first-level interconnects  1665  may be used. In some embodiments, no interposer  1657  may be included in the IC package  1650 ; instead, the dies  1656  may be coupled directly to the conductive contacts  1663  at the face  1672  by first-level interconnects  1665 . More generally, one or more dies  1656  may be coupled to the package substrate  1652  via any suitable structure (e.g., a silicon bridge, an organic bridge, one or more waveguides, one or more interposers, wirebonds, etc.). 
     The IC package  1650  may include one or more dies  1656  coupled to the interposer  1657  via conductive contacts  1654  of the dies  1656 , first-level interconnects  1658 , and conductive contacts  1660  of the interposer  1657 . The conductive contacts  1660  may be coupled to conductive pathways (not shown) through the interposer  1657 , allowing circuitry within the dies  1656  to electrically couple to various ones of the conductive contacts  1661  (or to other devices included in the interposer  1657 , not shown). The first-level interconnects  1658  illustrated in  FIG. 28  are solder bumps, but any suitable first-level interconnects  1658  may be used. As used herein, a “conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket). 
     In some embodiments, an underfill material  1666  may be disposed between the package substrate  1652  and the interposer  1657  around the first-level interconnects  1665 , and a mold compound  1668  may be disposed around the dies  1656  and the interposer  1657  and in contact with the package substrate  1652 . In some embodiments, the underfill material  1666  may be the same as the mold compound  1668 . Example materials that may be used for the underfill material  1666  and the mold compound  1668  are epoxy mold materials, as suitable. Second-level interconnects  1670  may be coupled to the conductive contacts  1664 . The second-level interconnects  1670  illustrated in  FIG. 28  are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects  1670  may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects  1670  may be used to couple the IC package  1650  to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to  FIG. 29 . 
     The dies  1656  may take the form of any of the embodiments of the die  1502  discussed herein (e.g., may include any of the embodiments of the IC device  1600 ). In embodiments in which the IC package  1650  includes multiple dies  1656 , the IC package  1650  may be referred to as a multi-chip package (MCP). The dies  1656  may include circuitry to perform any desired functionality. For example, or more of the dies  1656  may be logic dies (e.g., silicon-based dies), and one or more of the dies  1656  may be memory dies (e.g., high bandwidth memory). 
     Although the IC package  1650  illustrated in  FIG. 28  is a flip chip package, other package architectures may be used. For example, the IC package  1650  may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package  1650  may be a wafer-level chip scale package (WLCSP) or a panel fanout (FO) package. Although two dies  1656  are illustrated in the IC package  1650  of  FIG. 28 , an IC package  1650  may include any desired number of dies  1656 . An IC package  1650  may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face  1672  or the second face  1674  of the package substrate  1652 , or on either face of the interposer  1657 . More generally, an IC package  1650  may include any other active or passive components known in the art. 
       FIG. 29  is a side, cross-sectional view of an IC device assembly  1700  that may include one or more IC packages or other electronic components (e.g., a die) including one or more IC structures  100  in accordance with any of the embodiments disclosed herein. The IC device assembly  1700  includes a number of components disposed on a circuit board  1702  (which may be, e.g., a motherboard). The IC device assembly  1700  includes components disposed on a first face  1740  of the circuit board  1702  and an opposing second face  1742  of the circuit board  1702 ; generally, components may be disposed on one or both faces  1740  and  1742 . Any of the IC packages discussed below with reference to the IC device assembly  1700  may take the form of any of the embodiments of the IC package  1650  discussed above with reference to  FIG. 28  (e.g., may include one or more IC structures  100  in a die). 
     In some embodiments, the circuit board  1702  may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board  1702 . In other embodiments, the circuit board  1702  may be a non-PCB substrate. 
     The IC device assembly  1700  illustrated in  FIG. 29  includes a package-on-interposer structure  1736  coupled to the first face  1740  of the circuit board  1702  by coupling components  1716 . The coupling components  1716  may electrically and mechanically couple the package-on-interposer structure  1736  to the circuit board  1702 , and may include solder balls (as shown in  FIG. 29 ), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure. 
     The package-on-interposer structure  1736  may include an IC package  1720  coupled to a package interposer  1704  by coupling components  1718 . The coupling components  1718  may take any suitable form for the application, such as the forms discussed above with reference to the coupling components  1716 . Although a single IC package  1720  is shown in  FIG. 29 , multiple IC packages may be coupled to the package interposer  1704 ; indeed, additional interposers may be coupled to the package interposer  1704 . The package interposer  1704  may provide an intervening substrate used to bridge the circuit board  1702  and the IC package  1720 . The IC package  1720  may be or include, for example, a die (the die  1502  of  FIG. 26 ), an IC device (e.g., the IC device  1600  of  FIG. 27 ), or any other suitable component. Generally, the package interposer  1704  may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the package interposer  1704  may couple the IC package  1720  (e.g., a die) to a set of BGA conductive contacts of the coupling components  1716  for coupling to the circuit board  1702 . In the embodiment illustrated in  FIG. 29 , the IC package  1720  and the circuit board  1702  are attached to opposing sides of the package interposer  1704 ; in other embodiments, the IC package  1720  and the circuit board  1702  may be attached to a same side of the package interposer  1704 . In some embodiments, three or more components may be interconnected by way of the package interposer  1704 . 
     In some embodiments, the package interposer  1704  may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the package interposer  1704  may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the package interposer  1704  may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The package interposer  1704  may include metal lines  1710  and vias  1708 , including but not limited to through-silicon vias (TSVs)  1706 . The package interposer  1704  may further include embedded devices  1714 , including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer  1704 . The package-on-interposer structure  1736  may take the form of any of the package-on-interposer structures known in the art. 
     The IC device assembly  1700  may include an IC package  1724  coupled to the first face  1740  of the circuit board  1702  by coupling components  1722 . The coupling components  1722  may take the form of any of the embodiments discussed above with reference to the coupling components  1716 , and the IC package  1724  may take the form of any of the embodiments discussed above with reference to the IC package  1720 . 
     The IC device assembly  1700  illustrated in  FIG. 29  includes a package-on-package structure  1734  coupled to the second face  1742  of the circuit board  1702  by coupling components  1728 . The package-on-package structure  1734  may include an IC package  1726  and an IC package  1732  coupled together by coupling components  1730  such that the IC package  1726  is disposed between the circuit board  1702  and the IC package  1732 . The coupling components  1728  and  1730  may take the form of any of the embodiments of the coupling components  1716  discussed above, and the IC packages  1726  and  1732  may take the form of any of the embodiments of the IC package  1720  discussed above. The package-on-package structure  1734  may be configured in accordance with any of the package-on-package structures known in the art. 
       FIG. 30  is a block diagram of an example electrical device  1800  that may include one or more IC structures  100  in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the electrical device  1800  may include one or more of the IC device assemblies  1700 , IC packages  1650 , IC devices  1600 , or dies  1502  disclosed herein. A number of components are illustrated in  FIG. 30  as included in the electrical device  1800 , but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device  1800  may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die. 
     Additionally, in various embodiments, the electrical device  1800  may not include one or more of the components illustrated in  FIG. 30 , but the electrical device  1800  may include interface circuitry for coupling to the one or more components. For example, the electrical device  1800  may not include a display device  1806 , but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device  1806  may be coupled. In another set of examples, the electrical device  1800  may not include an audio input device  1824  or an audio output device  1808 , but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device  1824  or audio output device  1808  may be coupled. 
     The electrical device  1800  may include a processing device  1802  (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device  1802  may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device  1800  may include a memory  1804 , which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory  1804  may include memory that shares a die with the processing device  1802 . This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM). 
     In some embodiments, the electrical device  1800  may include a communication chip  1812  (e.g., one or more communication chips). For example, the communication chip  1812  may be configured for managing wireless communications for the transfer of data to and from the electrical device  1800 . The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. 
     The communication chip  1812  may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip  1812  may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip  1812  may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip  1812  may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip  1812  may operate in accordance with other wireless protocols in other embodiments. The electrical device  1800  may include an antenna  1822  to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions). 
     In some embodiments, the communication chip  1812  may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip  1812  may include multiple communication chips. For instance, a first communication chip  1812  may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip  1812  may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip  1812  may be dedicated to wireless communications, and a second communication chip  1812  may be dedicated to wired communications. 
     The electrical device  1800  may include battery/power circuitry  1814 . The battery/power circuitry  1814  may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device  1800  to an energy source separate from the electrical device  1800  (e.g., AC line power). 
     The electrical device  1800  may include a display device  1806  (or corresponding interface circuitry, as discussed above). The display device  1806  may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display. 
     The electrical device  1800  may include an audio output device  1808  (or corresponding interface circuitry, as discussed above). The audio output device  1808  may include any device that generates an audible indicator, such as speakers, headsets, or earbuds. 
     The electrical device  1800  may include an audio input device  1824  (or corresponding interface circuitry, as discussed above). The audio input device  1824  may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). 
     The electrical device  1800  may include a GPS device  1818  (or corresponding interface circuitry, as discussed above). The GPS device  1818  may be in communication with a satellite-based system and may receive a location of the electrical device  1800 , as known in the art. 
     The electrical device  1800  may include an other output device  1810  (or corresponding interface circuitry, as discussed above). Examples of the other output device  1810  may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. 
     The electrical device  1800  may include an other input device  1820  (or corresponding interface circuitry, as discussed above). Examples of the other input device  1820  may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader. 
     The electrical device  1800  may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device  1800  may be any other electronic device that processes data. 
     The following paragraphs provide various examples of the embodiments disclosed herein. 
     Example 1 is an integrated circuit (IC) structure, including: a first device stratum including a first source/drain material; a second device stratum including a second source/drain material, wherein the second source/drain material is above and aligned with the first source/drain material; and a dielectric material between the first source/drain material and the second source/drain material, wherein the dielectric material is conformal on an upper surface of the first source/drain material so that the contours of the dielectric material substantially preserve the contours of the upper surface of the first source/drain material. 
     Example 2 includes the subject matter of Example 1, and further specifies that the upper surface of the first source/drain material has a variation window that is greater than 2 nanometers, wherein the variation window is equal to a vertical distance between a lowest point of the upper surface and a highest point of the upper surface. 
     Example 3 includes the subject matter of Example 1, and further specifies that the upper surface of the first source/drain material has a variation window that is greater than 5 nanometers. 
     Example 4 includes the subject matter of Example 1, and further specifies that the upper surface of the first source/drain material has a variation window that is greater than 10 nanometers. 
     Example 5 includes the subject matter of Example 1, and further specifies that the upper surface of the first source/drain material has a variation window that is greater than 20 nanometers. 
     Example 6 includes the subject matter of any of Examples 1-5, and further specifies that the upper surface of the first source/drain material has a variation window that is less than 30 nanometers. 
     Example 7 includes the subject matter of any of Examples 1-6, and further specifies that the dielectric material has a thickness that is between 5 nanometers and 20 nanometers. 
     Example 8 includes the subject matter of any of Examples 1-7, and further specifies that the dielectric material includes oxygen. 
     Example 9 includes the subject matter of any of Examples 1-8, and further specifies that the first source/drain material includes at least one element, and the dielectric material includes oxygen and the at least one element. 
     Example 10 includes the subject matter of Example 9, and further specifies that the at least one element includes silicon. 
     Example 11 includes the subject matter of any of Examples 9-10, and further specifies that the at least one element includes germanium. 
     Example 12 includes the subject matter of Example 9, and further specifies that the element includes a III-V element. 
     Example 13 includes the subject matter of any of Examples 1-12, and further specifies that the first source/drain material includes an n-type dopant and the second source/drain material includes a p-type dopant. 
     Example 14 includes the subject matter of any of Examples 1-12, and further specifies that the first source/drain material includes a p-type dopant and the second source/drain material includes an n-type dopant. 
     Example 15 includes the subject matter of any of Examples 13-14, and further specifies that the p-type dopant includes boron. 
     Example 16 includes the subject matter of any of Examples 13-15, and further specifies that the n-type dopant includes phosphorous. 
     Example 17 includes the subject matter of any of Examples 1-16, and further specifies that the first source/drain material is an epitaxial material. 
     Example 18 includes the subject matter of any of Examples 1-17, and further specifies that the second source/drain material is an epitaxial material. 
     Example 19 includes the subject matter of any of Examples 1-18, and further includes: a material layer between the dielectric material and the second source/drain material. 
     Example 20 includes the subject matter of Example 19, and further specifies that the material layer includes a metal. 
     Example 21 includes the subject matter of Example 20, and further specifies that the material layer includes aluminum or lanthanum. 
     Example 22 includes the subject matter of any of Examples 19-21, and further specifies that the material layer has a thickness between 5 Angstroms and 5 nanometers. 
     Example 23 includes the subject matter of any of Examples 19-22, and further specifies that the material layer is conformal on an upper surface of the dielectric material. 
     Example 24 includes the subject matter of any of Examples 1-23, and further specifies that the first device stratum further includes a first channel material, the second device stratum includes a second channel material, and the second channel material is above and aligned with the first channel material. 
     Example 25 includes the subject matter of Example 24, and further specifies that the first channel material or the second channel material includes a semiconductor fin. 
     Example 26 includes the subject matter of Example 25, and further specifies that the first channel material includes a semiconductor fin and the second channel material includes a semiconductor fin. 
     Example 27 includes the subject matter of any of Examples 24-26, and further specifies that the first channel material or the second channel material includes a plurality of semiconductor wires. 
     Example 28 includes the subject matter of Example 27, and further specifies that an individual one of the semiconductor wires has a height between 5 nanometers and 30 nanometers. 
     Example 29 includes the subject matter of any of Examples 27-28, and further specifies that the first channel material includes a plurality of semiconductor wires and the second channel material includes a plurality of semiconductor wires. 
     Example 30 includes the subject matter of any of Examples 24-29, and further specifies that the first source/drain material is at an end of the first channel material, and the second source/drain material is at an end of the second channel material. 
     Example 31 includes the subject matter of any of Examples 24-30, and further specifies that (1) the first channel material extends into the first source/drain material or (2) the second channel material extends into the second source/drain material. 
     Example 32 includes the subject matter of any of Examples 24-30, and further specifies that (1) the first channel material does not extend into the first source/drain material or (2) the second channel material does not extend into the second source/drain material. 
     Example 33 includes the subject matter of any of Examples 24-32, and further specifies that the first device stratum includes a first gate metal and the second device stratum includes a second gate metal. 
     Example 34 includes the subject matter of Example 33, and further specifies that the first gate metal has a same material composition as the second gate metal. 
     Example 35 includes the subject matter of Example 33, and further specifies that the first gate metal has a different material composition than the second gate metal. 
     Example 36 includes the subject matter of any of Examples 33-35, and further specifies that the first device stratum includes a first gate dielectric and the second device stratum includes a second gate dielectric. 
     Example 37 includes the subject matter of Example 36, and further specifies that the first gate dielectric has a same material composition as the second gate dielectric. 
     Example 38 includes the subject matter of Example 36, and further specifies that the first gate dielectric has a different material composition than the second gate dielectric. 
     Example 39 includes the subject matter of any of Examples 36-38, and further specifies that the first gate dielectric is between the first channel material and the first gate metal, and the second gate dielectric is between the second channel material and the second gate metal. 
     Example 40 includes the subject matter of any of Examples 1-39, and further specifies that the first device stratum is between a silicon-on-insulator structure and the second device stratum. 
     Example 41 is an integrated circuit (IC) die, including: a first device stratum including a first source/drain material; a second device stratum including a second source/drain material, wherein the second source/drain material is above the first source/drain material; a dielectric material between the first source/drain material and the second source/drain material; and a material layer between the dielectric material and the second source/drain material, wherein the material layer includes a metal. 
     Example 42 includes the subject matter of Example 41, and further specifies that the dielectric material is conformal on an upper surface of the first source/drain material. 
     Example 43 includes the subject matter of any of Examples 41-42, and further specifies that an upper surface of the first source/drain material has a variation window that is greater than 2 nanometers. 
     Example 44 includes the subject matter of any of Examples 41-42, and further specifies that an upper surface of the first source/drain material has a variation window that is greater than 5 nanometers. 
     Example 45 includes the subject matter of any of Examples 41-42, and further specifies that an upper surface of the first source/drain material has a variation window that is greater than 10 nanometers. 
     Example 46 includes the subject matter of any of Examples 41-42, and further specifies that an upper surface of the first source/drain material has a variation window that is greater than 20 nanometers. 
     Example 47 includes the subject matter of any of Examples 41-46, and further specifies that an upper surface of the first source/drain material has a variation window that is less than 30 nanometers. 
     Example 48 includes the subject matter of any of Examples 41-47, and further specifies that the dielectric material has a thickness that is between 5 nanometers and 20 nanometers. 
     Example 49 includes the subject matter of any of Examples 41-48, and further specifies that the dielectric material includes oxygen. 
     Example 50 includes the subject matter of any of Examples 41-49, and further specifies that the first source/drain material includes at least one element, and the dielectric material includes oxygen and the at least one element. 
     Example 51 includes the subject matter of Example 50, and further specifies that the at least one element includes silicon. 
     Example 52 includes the subject matter of any of Examples 50-51, and further specifies that the at least one element includes germanium. 
     Example 53 includes the subject matter of Example 50, and further specifies that the element includes a III-V element. 
     Example 54 includes the subject matter of any of Examples 41-53, and further specifies that the first source/drain material includes an n-type dopant and the second source/drain material includes a p-type dopant. 
     Example 55 includes the subject matter of any of Examples 41-53, and further specifies that the first source/drain material includes a p-type dopant and the second source/drain material includes an n-type dopant. 
     Example 56 includes the subject matter of any of Examples 54-55, and further specifies that the p-type dopant includes boron. 
     Example 57 includes the subject matter of any of Examples 54-56, and further specifies that the n-type dopant includes phosphorous. 
     Example 58 includes the subject matter of any of Examples 41-57, and further specifies that the first source/drain material is an epitaxial material. 
     Example 59 includes the subject matter of any of Examples 41-58, and further specifies that the second source/drain material is an epitaxial material. 
     Example 60 includes the subject matter of any of Examples 41-59, and further specifies that the metal includes aluminum or lanthanum. 
     Example 61 includes the subject matter of any of Examples 41-60, and further specifies that the material layer has a thickness between 5 Angstroms and 5 nanometers. 
     Example 62 includes the subject matter of any of Examples 41-61, and further specifies that the material layer is conformal on an upper surface of the dielectric material. 
     Example 63 includes the subject matter of any of Examples 41-62, and further specifies that the first device stratum further includes a first channel material, the second device stratum includes a second channel material, and the second channel material is above and aligned with the first channel material. 
     Example 64 includes the subject matter of Example 63, and further specifies that the first channel material or the second channel material includes a semiconductor fin. 
     Example 65 includes the subject matter of Example 64, and further specifies that the first channel material includes a semiconductor fin and the second channel material includes a semiconductor fin. 
     Example 66 includes the subject matter of any of Examples 63-65, and further specifies that the first channel material or the second channel material includes a plurality of semiconductor wires. 
     Example 67 includes the subject matter of Example 66, and further specifies that an individual one of the semiconductor wires has a height between 5 nanometers and 30 nanometers. 
     Example 68 includes the subject matter of any of Examples 66-67, and further specifies that the first channel material includes a plurality of semiconductor wires and the second channel material includes a plurality of semiconductor wires. 
     Example 69 includes the subject matter of any of Examples 63-68, and further specifies that the first source/drain material is at an end of the first channel material, and the second source/drain material is at an end of the second channel material. 
     Example 70 includes the subject matter of any of Examples 63-69, and further specifies that (1) the first channel material extends into the first source/drain material or (2) the second channel material extends into the second source/drain material. 
     Example 71 includes the subject matter of any of Examples 63-69, and further specifies that (1) the first channel material does not extend into the first source/drain material or (2) the second channel material does not extend into the second source/drain material. 
     Example 72 includes the subject matter of any of Examples 63-71, and further specifies that the first device stratum includes a first gate metal and the second device stratum includes a second gate metal. 
     Example 73 includes the subject matter of Example 72, and further specifies that the first gate metal has a same material composition as the second gate metal. 
     Example 74 includes the subject matter of Example 72, and further specifies that the first gate metal has a different material composition than the second gate metal. 
     Example 75 includes the subject matter of any of Examples 72-74, and further specifies that the first device stratum includes a first gate dielectric and the second device stratum includes a second gate dielectric. 
     Example 76 includes the subject matter of Example 75, and further specifies that the first gate dielectric has a same material composition as the second gate dielectric. 
     Example 77 includes the subject matter of Example 75, and further specifies that the first gate dielectric has a different material composition than the second gate dielectric. 
     Example 78 includes the subject matter of any of Examples 75-77, and further specifies that the first gate dielectric is between the first channel material and the first gate metal, and the second gate dielectric is between the second channel material and the second gate metal. 
     Example 79 includes the subject matter of any of Examples 41-78, and further specifies that the first device stratum is between a silicon-on-insulator structure and the second device stratum. 
     Example 80 includes the subject matter of any of Examples 41-79, and further includes: a metallization stack including conductive pathways electrically coupled to the first device stratum and the second device stratum. 
     Example 81 includes the subject matter of any of Examples 41-80, and further includes: a plurality of conductive contacts at an outer face of the IC die, wherein at least some of the conductive contacts are in electrical contact with the first device stratum or the second device stratum. 
     Example 82 is a computing device, including: a circuit board; and an integrated circuit (IC) package coupled to the circuit board, wherein the IC package includes a package substrate and an IC die coupled to the package substrate, and the IC die includes stacked strata of transistors, wherein a dielectric material is between source/drain materials of adjacent strata, and the dielectric material is conformal on underlying source/drain material. 
     Example 83 includes the subject matter of Example 82, and further specifies that channel material of at least one stratum includes a semiconductor fin. 
     Example 84 includes the subject matter of any of Examples 82-83, and further specifies that channel material of at least one stratum includes a plurality of semiconductor wires. 
     Example 85 includes the subject matter of any of Examples 82-84, and further specifies that an upper surface of the underlying source/drain material has a variation window that is greater than 2 nanometers. 
     Example 86 includes the subject matter of any of Examples 82-84, and further specifies that an upper surface of the underlying source/drain material has a variation window that is greater than 5 nanometers. 
     Example 87 includes the subject matter of any of Examples 82-84, and further specifies that an upper surface of the underlying source/drain material has a variation window that is greater than 10 nanometers. 
     Example 88 includes the subject matter of any of Examples 82-84, and further specifies that an upper surface of the underlying source/drain material has a variation window that is greater than 20 nanometers. 
     Example 89 includes the subject matter of any of Examples 82-88, and further specifies that an upper surface of underlying first source/drain material has a variation window that is less than 30 nanometers. 
     Example 90 includes the subject matter of any of Examples 82-89, and further specifies that the dielectric material has a thickness that is between 5 nanometers and 20 nanometers. 
     Example 91 includes the subject matter of any of Examples 82-90, and further specifies that the dielectric material includes oxygen. 
     Example 92 includes the subject matter of any of Examples 82-91, and further specifies that the underlying source/drain material includes at least one element, and the dielectric material includes oxygen and the at least one element. 
     Example 93 includes the subject matter of Example 92, and further specifies that the at least one element includes silicon. 
     Example 94 includes the subject matter of any of Examples 92-93, and further specifies that the at least one element includes germanium. 
     Example 95 includes the subject matter of Example 92, and further specifies that the element includes a III-V element. 
     Example 96 includes the subject matter of any of Examples 82-95, and further specifies that the underlying source/drain material includes an n-type dopant and a source/drain material above the dielectric material includes a p-type dopant. 
     Example 97 includes the subject matter of any of Examples 82-95, and further specifies that the underlying source/drain material includes a p-type dopant and a source/drain material above the dielectric material includes an n-type dopant. 
     Example 98 includes the subject matter of any of Examples 96-97, and further specifies that the p-type dopant includes boron. 
     Example 99 includes the subject matter of any of Examples 96-98, and further specifies that the n-type dopant includes phosphorous. 
     Example 100 includes the subject matter of any of Examples 82-99, and further specifies that the underlying source/drain material is an epitaxial material. 
     Example 101 includes the subject matter of any of Examples 82-100, and further specifies that a source/drain material above the dielectric material is an epitaxial material. 
     Example 102 includes the subject matter of any of Examples 82-101, and further includes: a material layer between the dielectric material and a source/drain material above the dielectric material. 
     Example 103 includes the subject matter of Example 102, and further specifies that the material layer includes a metal. 
     Example 104 includes the subject matter of Example 103, and further specifies that the material layer includes aluminum or lanthanum. 
     Example 105 includes the subject matter of any of Examples 102-104, and further specifies that the material layer has a thickness between 5 Angstroms and 5 nanometers. 
     Example 106 includes the subject matter of any of Examples 102-105, and further specifies that the material layer is conformal on an upper surface of the dielectric material. 
     Example 107 includes the subject matter of any of Examples 82-106, and further specifies that the IC die is coupled to the package substrate by solder balls. 
     Example 108 includes the subject matter of any of Examples 82-107, and further specifies that the circuit board is a motherboard. 
     Example 109 includes the subject matter of any of Examples 82-108, and further includes: wireless communication circuitry electrically coupled to the circuit board. 
     Example 110 includes the subject matter of any of Examples 82-109, and further includes: a display electrically coupled to the circuit board. 
     Example 111 includes the subject matter of any of Examples 82-110, and further specifies that the computing device is a tablet computing device, a handheld computing device, a smart phone, a wearable computing device, or a server. 
     Example 112 is a method of manufacturing an integrated circuit (IC) structure, including: forming a first source/drain material; forming an oxidation catalyst on the first source/drain material; annealing the first source/drain material and the oxidation catalyst to form a dielectric material; and forming a second source/drain material above the dielectric material. 
     Example 113 includes the subject matter of Example 112, and further specifies that the oxidation catalyst includes a metal. 
     Example 114 includes the subject matter of any of Examples 112-113, and further specifies that forming the oxidation catalyst comprises: depositing a conformal layer of the oxidation catalyst; and recessing the conformal layer of the oxidation catalyst. 
     Example 115 includes the subject matter of any of Examples 112-114, and further includes: before forming the second source/drain material, removing the oxidation catalyst. 
     Example 116 includes the subject matter of any of Examples 112-115, and further specifies that forming the first source/drain material includes epitaxial growth of the first source/drain material. 
     Example 117 includes the subject matter of any of Examples 112-116, and further specifies that forming the second source/drain material includes epitaxial growth of the second source/drain material. 
     Example 118 is a method of manufacturing an integrated circuit (IC) structure, including performing any of the manufacturing operations disclosed herein.