Patent Publication Number: US-10763838-B2

Title: Semiconductor device and semiconductor system for detecting voltage-drop level

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2018-0155017, filed on Dec. 5, 2018, the disclosure of which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Field 
     Various exemplary embodiments of the present invention generally relate to a semiconductor design technique. Particularly, the embodiments relate to a semiconductor device for detecting a degree to which an internal voltage is out of a target voltage level. 
     2. Description of the Related Art 
     A semiconductor device operates on power supply voltages supplied from an external system. The semiconductor device may generate a plurality of internal voltages having various voltage levels required for internal operations thereof, using the external power supply voltages. In order to generate the internal voltages with more stable voltage levels, it is necessary to monitor the degree to which the internal voltages are out of a target voltage level (e.g., voltage drop levels). 
     In general, there is no way to directly measure the voltage drop level of the internal voltage since it occurs inside the semiconductor device. To monitor the internal voltage at a desired measurement location inside the semiconductor device, a pad has to be inserted into the semiconductor device and the internal voltage is monitored at the measurement location through the pad. In this case, it is difficult to accurately monitor the voltage drop level of the internal voltage because it acts as a very large load when a measurement equipment (i.e., a tester) is in contact with the pad. 
     SUMMARY 
     Various embodiments of the present invention are directed to a semiconductor device and a semiconductor system for detecting a voltage drop level of an internal voltage. 
     In accordance with an embodiment of the present invention, a semiconductor device includes: a voltage adjust circuit suitable for generating an adjusting voltage according to a counting signal; an oscillating circuit operable by an oscillating control signal, and suitable for outputting an operational clock signal whose frequency is controlled by the adjusting voltage; a pumping circuit suitable for generating an internal voltage by pumping a source voltage according to the operational clock signal; and a counting circuit suitable for generating the counting signal by counting the operational clock signal according to the oscillating control signal. 
     In accordance with an embodiment of the present invention, a semiconductor device includes: a voltage adjust circuit suitable for generating an adjusting voltage according to a counting signal; a reference voltage generation circuit suitable for adjusting a voltage level of a reference voltage according to the adjusting voltage; a detecting circuit suitable for outputting an oscillating control signal by comparing the reference voltage with an internal voltage; an oscillating circuit suitable for outputting an operational clock signal in response to the oscillating control signal; a pumping circuit suitable for generating the internal voltage by pumping a source voltage according to the operational clock signal; and a counting circuit suitable for generating the counting signal by counting the operational clock signal according to the oscillating control signal. 
     In accordance with an embodiment of the present invention, a semiconductor system includes: a first semiconductor device that includes a voltage adjust circuit suitable for generating an adjusting voltage according to a counting signal; and a second semiconductor device that includes: a voltage generation circuit operable by an oscillating control signal, and suitable for outputting an operational clock signal according to the adjusting voltage and generating an internal voltage by pumping a source voltage according to the operational clock signal; and a counting circuit suitable for generating the counting signal by counting the operational clock signal according to the oscillating control signal. 
     In accordance with an embodiment of the present invention, a semiconductor system includes: a voltage adjust circuit suitable for generating an adjusting voltage having a variable level dependent on a variable frequency; an oscillating circuit suitable for generating, while an internal voltage is lower than a reference voltage, an operational clock signal having the frequency dependent on the level; and a pumping circuit suitable for generating the internal voltage according to the frequency. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating a semiconductor system in accordance with an embodiment of the present invention. 
         FIG. 2  is a circuit diagram of an oscillating circuit shown in  FIG. 1 . 
         FIG. 3  is a circuit diagram of a pumping circuit shown in  FIG. 1 , in accordance with an embodiment of the present invention. 
         FIG. 4  is a circuit diagram of a pumping circuit shown in  FIG. 1 , in accordance with another embodiment of the present invention. 
         FIG. 5  is a circuit diagram of a detecting circuit shown in  FIG. 1 . 
         FIG. 6  is a circuit diagram of a counting circuit shown in  FIG. 1 , in accordance with an embodiment of the present invention. 
         FIGS. 7A and 7B  are timing diagrams for describing an operation of detecting a voltage drop level of an internal voltage in accordance with an embodiment of the present invention. 
         FIG. 8  is a block diagram illustrating a semiconductor system in accordance with an embodiment of the present invention. 
         FIG. 9  is a circuit diagram of a reference voltage generation circuit of  FIG. 8 . 
     
    
    
     DETAILED DESCRIPTION 
     Various exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete, and fully conveys the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. It is noted that reference to “an embodiment” does not necessarily mean only one embodiment, and different references to “an embodiment” are not necessarily to the same embodiment(s). 
     It will be understood that, although the terms “first”, “second”, “third”, and so on may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element described below could also be termed as a second or third element without departing from the spirit and scope of the present invention. 
     It will be further understood that when an element is referred to as being “connected to”, or “coupled to” another element, it may be directly on, connected to, or coupled to the other element, or one or more intervening elements may be present. In addition, it will also be understood that when an element is referred to as being “between” two elements, it may be the only element between the two elements, or one or more intervening elements may also be present. Communication between two elements, whether directly or indirectly connected/coupled, may be wired or wireless, unless stated or the context indicates otherwise. 
     As used herein, singular forms may include the plural forms as well and vice versa, unless the context clearly indicates otherwise. 
     It will be further understood that the terms “comprises,” “comprising,” “includes,” and “including” when used in this specification, specify the presence of the stated elements and do not preclude the presence or addition of one or more other elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     Hereinafter, the various embodiments of the present invention will be described in detail with reference to the attached drawings. 
     Semiconductor memory devices, among semiconductor devices, may generate a plurality of internal voltages having various levels using an external voltage. The internal voltages are used for various internal operations of the semiconductor memory devices. 
     Existing methods for generating the internal voltages using the external voltage are largely divided into two schemes. According to a first scheme, an internal voltage lower than an external voltage may be generated by down-converting the external voltage to a lower potential. According to a second scheme, an internal voltage higher than an external voltage or lower than a ground voltage may be generated by charge-pumping the external voltage. 
     A high voltage VPP and a back-bias voltage VBB are widely used as the internal voltages generated by charge-pumping the external voltage. The high voltage VPP is generated in order for a gate of a cell transistor (or word line) to have a higher potential than a source voltage VDD, i.e., the external voltage, thereby accessing a memory cell without a loss of cell data. The back-bias voltage VBB is generated in order for a bulk of a cell transistor to have a lower potential than a ground voltage VSS, i.e., the external voltage, thereby preventing a loss of cell data. 
     Hereinafter, a voltage generation circuit for generating the high voltage VPP using the source voltage VDD will be described as a representative example. 
       FIG. 1  is a block diagram illustrating a semiconductor system  10  in accordance with an embodiment of the present invention. 
     Referring to  FIG. 1 , the semiconductor system  10  may include a first semiconductor device  20  and a second semiconductor device  30 . The first semiconductor device  20  may include a memory device, and the second semiconductor device  30  may include a memory controller for controlling the memory device, or a test device for testing/monitoring the memory device. 
     The second semiconductor device  30  may include a voltage adjust circuit  300  for generating an adjusting voltage VCH according to a counting signal CNT. The voltage adjust circuit  300  may provide the adjusting voltage VCH to the first semiconductor device  20 . The voltage adjust circuit  300  may increase a voltage level of the adjusting voltage VCH in proportion to a counting value of the counting signal CNT. 
     The first semiconductor device  20  may include a voltage generation circuit  100  and a counting circuit  200 . 
     The voltage generation circuit  100  may be operable by an oscillating control signal OSC_EN, and generate operational clock signals CLK 1  and CLK 2  whose frequency is controlled by the adjusting voltage VCH. The voltage generation circuit  100  may generate a high voltage VPP by pumping a source voltage VDD according to the operational clock signals CLK 1  and CLK 2 . 
     The counting circuit  200  may generate the counting signal CNT by counting an oscillating signal OSC corresponding to the operational clock signals CLK 1  and CLK 2  in response to the oscillating control signal OSC_EN. The counting circuit  200  may be activated by a rising edge of the oscillating control signal OSC_EN and may be initialized by a falling edge of the oscillating control signal OSC_EN. In the case where the first semiconductor device  20  is a memory device, the counting signal CNT may be outputted to the second semiconductor device  30  through at least one data input/output (I/O) pad, i.e., DQ pads. The counting signal CNT may be a multi-bit signal. The multi-bit values of the counting signal CNT may be serially outputted through any of the DQ pads or may be outputted in parallel through some of the DQ pads. 
     In detail, the voltage generation circuit  100  may include an oscillating circuit  110 , a pumping circuit  120 , and a detecting circuit  130 . 
     The oscillating circuit  110  may be activated by the oscillating control signal OSC_EN, and output the operational clock signals CLK 1  and CLK 2  whose frequency is controlled by the adjusting voltage VCH. The operational clock signals CLK 1  and CLK 2  may include a first clock signal CLK 1  and a second clock signal CLK 2 , which have an opposite phase to each other. The oscillating circuit  110  may output the oscillating signal OSC which has the same phase as one of the first clock signal CLK 1  and the second clock signal CLK 2 . Hereinafter, a case where the oscillating circuit  110  outputs the oscillating signal OSC having the same phase as the first clock signal CLK 1  is described as a representative example. 
     The pumping circuit  120  may generate the high voltage VPP by pumping the source voltage VDD according to the first clock signal CLK 1  and the second clock signal CLK 2 . The pumping circuit  120  may pump the source voltage VDD faster such that the level of the source voltage VDD as the high voltage VPP reaches a target voltage level in shorter time as a frequency of the first clock signal CLK 1  and the second clock signal CLK 2  increases. 
     The detecting circuit  130  may output the oscillating control signal OSC_EN by comparing a reference voltage VREF with the high voltage VPP. For example, the detecting circuit  130  enables the oscillating control signal OSC_EN to a logic high level when a voltage level of the high voltage VPP is lower than the reference voltage VREF. The detecting circuit  130  disables the oscillating control signal OSC_EN to a logic low level when the voltage level of the high voltage VPP is higher than or equal to the reference voltage VREF. 
     Meanwhile, in the semiconductor system  10  of  FIG. 1 , the voltage adjust circuit  300  is provided in the second semiconductor device  30 . However, the present invention is not limited thereto. According to an embodiment, the voltage adjust circuit  300  may be provided in the first semiconductor device  20 , with the voltage generation circuit  100   
     As described above, the present invention can detect a voltage drop level of an internal voltage in real time, using the voltage generation circuit  100  within a semiconductor device. Additionally, the present invention can adjust a voltage level of the internal voltage based on a voltage drop detection result (i.e. the counting signal CNT) to generate the internal voltage having a more stable voltage level. 
       FIG. 2  is a circuit diagram of the oscillating circuit  110  shown in  FIG. 1 . 
     Referring to  FIG. 2 , the oscillating circuit  110  may include a voltage supplier  112  and an oscillator  114 . The voltage supplier  112  may provide a driving voltage V_DR according to the source voltage VDD or the adjusting voltage VCH. The voltage supplier  112  may output the source voltage VDD as the driving voltage V_DR when the adjusting voltage VCH is not inputted from the second semiconductor device  30 . The voltage supplier  112  may output the adjusting voltage VCH as the driving voltage V_DR when the adjusting voltage VCH is inputted from the second semiconductor device  30 . 
     The oscillator  114  may generate the oscillating signal OSC by using the driving voltage V_DR, and generate the first clock signal CLK 1  and the second clock signal CLK 2  according to the oscillating signal OSC. The oscillator  114  may include a first period section  1142  and a second period section  1144 . 
     The first period section  1142  may be implemented with a ring oscillator. The first period section  1142  may include a NAND gate ND 1 , a first inverter chain INV_CH 1  and a second inverter chain INV_CH 2 . Each of the first inverter chain INV_CH 1  and the second inverter chain INV_CH 2  may include an odd number of inverters. For example, the first inverter chain INV_CH 1  may include first to third inverters IV 1  to IV 3 , and the second inverter chain INV_CH 2  may include fourth to sixth inverters IV 4  to IV 6 . The NAND gate ND 1  may perform a NAND operation on the oscillating control signal OSC_EN and a feedback signal FB. The first inverter chain INV_CH 1  may invert and delay an output of the NAND gate ND 1  to output the oscillating signal OSC. The second inverter chain INV_CH 2  may invert and delay the oscillating signal OSC to output the feedback signal FB to the NAND gate ND 1 . As described above, the first period section  1142  may output the oscillating signal OSC which toggles with a frequency corresponding to the driving voltage V_DR when the oscillating control signal OSC_EN is enabled to a logic high level. 
     The second period section  1144  may include a first clock generator  1144 A and a second clock generator  1144 B. The first clock generator  1144 A may buffer the oscillating signal OSC to output the first clock signal CLK 1 . The first clock generator  1144 A may include seventh and eighth inverters IV 7  and IV 8 . The second clock generator  1144 B may invert the oscillating signal OSC to output the second clock signal CLK 2 . The second clock generator  1144 B may include a ninth inverter IV 9 . As described above, the second period section  1144  may output the first clock signal CLK 1  having substantially the same phase and frequency as the oscillating signal OSC, and output the second clock signal CLK 2  having substantially the same frequency as the oscillating signal OSC but having a phase opposite to the oscillating signal OSC. According to an embodiment, the first clock signal CLK 1  and the second clock signal CLK 2  may be designed so that they are alternately enabled within one cycle. 
       FIG. 3  is a circuit diagram of the pumping circuit  120  shown in  FIG. 1 . 
     Referring to  FIG. 3 , the pumping circuit  120  may be a cross-coupled charge pump circuit for amplifying an input voltage, i.e., the source voltage VDD, and output an output voltage, i.e., the high voltage VPP. 
     The pumping circuit  120  may include first to fourth transistors Q 1  to Q 4 , first and second capacitors C 1  and C 2 , and first and second inverters IV 10  and IV 11 . The first and second transistors Q 1  and Q 2  may be composed of NMOS transistors. The third and fourth transistors Q 3  and Q 4  may be composed of PMOS transistors. The first and second transistors Q 1  and Q 2  may have drains coupled to the source voltage VDD, and gates and sources which are cross-coupled with each other. The first and second transistors Q 1  and Q 2  may be turned on/off in response to the first clock signal CLK 1  and the second clock signal CLK 2 . The third and fourth transistors Q 3  and Q 4  may have drains coupled to an output terminal of the pumping circuit  120 , sources coupled to those of the first and second transistors Q 1  and Q 2  at a first node N 1  and a second node N 2 , respectively, and gates coupled to those of the first and second transistors Q 1  and Q 2  at the second node N 2  and the first node N 1 , respectively. The high voltage VPP may be outputted from the output terminal. The third and fourth transistors Q 3  and Q 4  may be turned on/off in response to the first clock signal CLK 1  and the second clock signal CLK 2 . 
     An operation of the pumping circuit  120  is described as follows. 
     When the source voltage VDD is supplied, the first and second transistors Q 1  and Q 2  may alternately apply the source voltage VDD to the first node N 1  and the second node N 2 . Under this circumstance, when the first clock signal CLK 1  and the second clock signal CLK 2  are applied, the first and second capacitors C 1  and C 2  store a charging voltage (VC) and alternately apply the charging voltage (VC) to the first node N 1  and the second node N 2 . As a result, a voltage having a value “VDD+VC” may be alternately applied at the first node N 1  and the second node N 2 . Finally, the voltage at the first node N 1  and the second node N 2  may be outputted at the output terminal through the third and fourth transistors Q 3  and Q 4 . 
     As described above, the pumping circuit  120  may vary the charging voltage (VC) according to the frequency/amplitude of the first clock signal CLK 1  and the second clock signal CLK 2  thereby varying a charge pump ratio thereof. 
       FIG. 4  is a circuit diagram of another example of the pumping circuit  120  shown in  FIG. 1 . 
     Referring to  FIG. 4 , the pumping circuit  120  may include first to fourth transistors Q 6  to Q 9 , first to fourth capacitors C 4  to C 7 , an output transistor Q 5 , and an output capacitor C 3 . The transistors Q 5  to Q 9  may be, for example, NMOS transistors having drain and gate coupled to each other to function as a diode. 
     The first to fourth transistors Q 6  to Q 9  and the output transistor Q 5  may be coupled in series between an input terminal and an output terminal of the pumping circuit  120 . The first clock signal CLK 1  and the second clock signal CLK 2  may be alternately applied to a common node of two adjacent transistors of the first to fourth transistors Q 6  to Q 9  and the output transistor Q 5 , through the first to fourth capacitors C 4  to C 7 , except for the output capacitor C 3  coupled to the output terminal. 
     During a first half cycle, the first clock signal CLK 1  has a logic low level and the second clock signal CLK 2  has a logic high level. The first capacitor C 4  may be charged with the source voltage VDD. During a subsequent half cycle, the first clock signal CLK 1  has a logic high level and the second clock signal CLK 2  has a logic low level. The first clock signal CLK 1  may cause a voltage of the first capacitor C 4  to increase to a level twice that of the source voltage VDD. Further, the first transistor Q 6  may be turned off, the second transistor Q 7  may be turned on. Thus, a voltage of the second capacitor C 5  may increase to a level twice that of the source voltage VDD. 
     During a first half cycle subsequent to the first cycle, the first clock signal CLK 1  has a logic low level and the second clock signal CLK 2  has a logic high level. The second clock signal CLK 2  may cause the voltage of the second capacitor C 5  to increase to a level three times that of the source voltage VDD, and the third capacitor C 6  may be charged with the voltage of the second capacitor C 5 . Through such a process, the pumping circuit  120  may amplify the source voltage VDD to generate the high voltage VPP. For example, when the pumping circuit  120  includes an N number of transistors, the high voltage VPP may be N times the source voltage VDD. 
       FIG. 5  is a circuit diagram of the detecting circuit  130  shown in  FIG. 1 . 
     Referring to  FIG. 5  the detecting circuit  130  may include a voltage divider  132  and a voltage comparator  134 . 
     The voltage divider  132  may output a division voltage VPP_D by dividing high voltage VPP outputted from the pumping circuit  120  by a certain ratio. The voltage divider  132  may include a first resistor R 1  and a second resistor R 2  coupled in series between a high voltage (VPP) terminal and a ground voltage (VSS) terminal. 
     The voltage comparator  134  may output the oscillating control signal OSC_EN by comparing the division voltage VPP_D with the reference voltage VREF. Preferably, the voltage comparator  134  may be composed of a differential amplifier. 
     The voltage comparator  134  may include first to fifth transistors QP 1 , QP 2 , QN 1 , QN 2  and QN 3  and an inverter IV 12 . The first and second transistors QP 1  and QP 2  may be composed of PMOS transistors, and the third to fifth transistors QN 1 , QN 2  and QN 3  may be composed of NMOS transistors. The first transistor QP 1  is coupled between a supply voltage (VDD) terminal and a first node N 3 . The second transistor QP 2  is coupled between the VDD terminal and a second node N 4 . The first and second transistors QP 1  and QP 2  may be composed of a current mirror-type PMOS transistors whose gates are coupled to the first node N 3  in common. The third transistor QN 1  is coupled between the first node N 3  and a third node N 5 , and receives the division voltage VPP_D through its gate. The fourth transistor QN 2  is coupled between the second node N 4  and the third node N 5 , and receives the reference voltage VREF through its gate. The fifth transistor QN 3  is coupled between the third node N 5  and the VSS terminal, and receives a bias voltage VBIAS (i.e., a source voltage VDD) through its gate. The inverter IV 12  inverts a signal at the second node N 4  to output the oscillating control signal OSC_EN. 
     An operation of the voltage comparator  134  is described as follows. 
     Signals at the first and second nodes N 3  and N 4  have logic levels different from each other according to voltage levels of the division voltage VPP_D and the reference voltage VREF applied to the third and fourth transistors QN 1  and QN 2 . For example, when the division voltage VPP_D has a voltage level greater than the reference voltage VREF, the third transistor QN 1  is turned on so that the ground voltage VSS is applied to the first node N 3 , and the signal at the second node N 4  becomes a logic high level. Accordingly, the oscillating control signal OSC_EN of a logic low level is outputted through the inverter IV 12 . The oscillating circuit  110  may be disabled in response to the oscillating control signal OSC_EN of a logic low level, and stops an oscillating operation. Accordingly, the voltage level of the high voltage VPP outputted by the pumping circuit  120  decreases. 
     On the contrary, when the division voltage VPP_D has a voltage level less than the reference voltage VREF, the fourth transistor QN 2  is turned on so that the ground voltage VSS is applied to the second node N 4 , and thus the oscillating control signal OSC_EN of a logic high level is outputted through the inverter IV 12 . The oscillating circuit  110  may be activated to perform the oscillating operation. Accordingly, the voltage level of the high voltage VPP outputted by the pumping circuit  120  increases. 
     In sum, the voltage comparator  134  may output the oscillating control signal OSC_EN for stopping the oscillating operation of the oscillating circuit  110  when the division voltage VPP_D has a voltage level greater than the reference voltage VREF. The voltage comparator  134  may output the oscillating control signal OSC_EN for performing the oscillating operation of the oscillating circuit  110  when the division voltage VPP_D has a voltage level less than the reference voltage VREF. 
     Meanwhile, since semiconductor devices are increasingly demanding refinement, even transistors configured to have the same characteristics within the semiconductor device can be subject to fine differences due to process variation. Thus, it is necessary to implement a device capable of monitoring characteristics of the transistors placed within the semiconductor device. 
     A semiconductor device may include a ring oscillator delay (ROD) having characteristics dependent on a process, a voltage and a temperature (PVT) variation. The ROD may measure individual characteristics, for example, an operating speed, of a NMOS transistor and a PMOS transistor therein to monitor process variations. This may allow the semiconductor device to compensate an operation according to a monitoring result. The ROD may use a counting circuit when measuring the operating speed of the NMOS transistor and the PMOS transistor therein. In accordance with an embodiment of the present invention, the counting circuit  200  may be implemented with a counter used in a ROD provided in the first semiconductor  20 . 
       FIG. 6  is a circuit diagram of the counting circuit  200  shown in  FIG. 1 . 
     Referring to  FIG. 6 , the counting circuit  200  may include a first monitoring block  220 , a second monitoring block  240 , a ROD selector  250 , a counting selector  260 , and a counter  270 . 
     The first monitoring block  220  may be embodied in a ROD for monitoring characteristics of a PMOS transistor. The second monitoring block  240  may be embodied in a ROD for monitoring characteristics of an NMOS transistor. 
     The first monitoring block  220  may include a plurality of first delay cells  222 _ 1  to  222 _K coupled in series to each other, and a first monitoring control unit  224  for controlling the first delay cells  222 _ 1  to  222 _K to perform a monitoring operation based on a first enable signal ROD_EN 1 . The first delay cells  222 _ 1  to  222 _K may be composed of an even number, that is, K is an even number. The first delay cells  222 _ 1  to  222 _K constitute a delay chain composed of a plurality of inverters. Each of the first delay cells  222 _ 1  to  222 _K may include a pull-up transistor PU 1  and a pull-down transistor PD 1  that are coupled in series to each other. When the first enable signal ROD_EN 1  is enabled, the first monitoring control unit  224  may invert an output of the delay cell  222 _K disposed last among the first delay cells  222 _ 1  to  222 _K, that is, a first monitoring signal ROD 1 _OUT, to provide an inverted signal of the first monitoring signal ROD 1 _OUT to an input terminal IN 1  of the delay cell  222 _ 1  disposed first among the first delay cells  222 _ 1  to  222 _K. The first monitoring control unit  224  may be composed of a NAND gate ND 2  that performs a NAND operation on the first enable signal ROD_EN 1  and the first monitoring signal ROD 1 _OUT. 
     The first monitoring block  220  may further include a plurality of pull-up coupling units  226 _ 1  to  226 _K which maintain a turn-on state. The respective pull-up coupling units  226 _ 1  to  226 _K are arranged between input terminals and gates of the pull-up transistors PU 1  of the respective first delay cells  222 _ 1  to  222 _K. By way of example but not limitation, the first pull-up coupling unit  226 _ 1  may be composed of a PMOS transistor CP 1  whose one side is coupled to the input terminal IN 1  of the first delay cell  222 _ 1 , the other side is coupled to the gate of the pull-up transistor PU 1  of the first delay cell  222 _ 1 , and gate is coupled to a ground voltage VSS terminal. The first monitoring block  220  may monitor the characteristics of the PMOS transistor, i.e., the pull-up transistor PU 1  by using the pull-up coupling units  226 _ 1  to  226 _K, each of which is arranged in front of the gate of the pull-up transistor PU 1 . 
     The second monitoring block  240  may include a plurality of second delay cells  242 _ 1  to  242 _K coupled in series to each other, and a second monitoring control unit  244  for controlling the second delay cells  242 _ 1  to  242 _K to perform a monitoring operation based on a second enable signal ROD_EN 2 . The second delay cells  242 _ 1  to  242 _K may be composed of an even number, that is, K is an even number. The second delay cells  242 _ 1  to  242 _K constitute a delay chain composed of a plurality of inverters. Each of the second delay cells  242 _ 1  to  242 _K may include a pull-up transistor PU 2  and a pull-down transistor PD 2  that are coupled in series to each other. When the second enable signal ROD_EN 2  is enabled, the second monitoring control unit  244  may invert an output of the delay cell  242 _K disposed last among the second delay cells  242 _ 1  to  242 _K, that is, a second monitoring signal ROD 2 _OUT, to provide an inverted signal of the second monitoring signal ROD 2 _OUT to an input terminal IN 2  of the delay cell  242 _ 1  disposed first among the second delay cells  242 _ 1  to  242 _K. The second monitoring control unit  244  may be composed of a NAND gate ND 3  that performs a NAND operation on the second enable signal ROD_EN 2  and the second monitoring signal ROD 2 _OUT. 
     The second monitoring block  240  may further include a plurality of pull-down coupling units  246 _ 1  to  246 _K which maintain a turn-on state. The respective pull-down coupling units  246 _ 1  to  246 _K are arranged between input terminals and gates of the pull-down transistors PD 2  of the respective second delay cells  242 _ 1  to  242 _K. By way of example but not limitation, the first pull-down coupling unit  246 _ 1  may be composed of an NMOS transistor CN 1  whose one side is coupled to the input terminal IN 2  of the second delay cell  242 _ 1 , the other side is coupled to a gate of the pull-up transistor PU 2  of the second delay cell  242 _ 1 , and gate is coupled to a power source voltage VDD terminal. The second monitoring block  240  may monitor the characteristics of the NMOS transistor, i.e., the pull-down transistor PD 2  by using the pull-down coupling units  246 _ 1  to  246 _K, each of which is arranged in front of the gate of the pull-down transistor PD 2 . 
     The ROD selector  250  may select the first monitoring signal ROD 1 _OUT or the second monitoring signal ROD 2 _OUT in response to a ROD selection signal ROD_SEL. The ROD selector  250  may output the selected signal as a ROD monitoring signal ROD_OUT. The ROD selection signal ROD_SEL may have a logic low level when the first enable signal ROD_EN 1  is enabled, and the ROD selection signal ROD_SEL may have a logic high level when the second enable signal ROD_EN 2  is enabled. 
     The counting selector  260  may select the ROD monitoring signal ROD_OUT outputted from the ROD selector  250  or the oscillating signal OSC outputted from the oscillating circuit  110  in response to the oscillating control signal OSC_EN. The counting selector  260  may output the selected signal as a final monitoring signal SEL_OUT. The counting selector  260  may output the final monitoring signal SEL_OUT by selecting the ROD monitoring signal ROD_OUT when the oscillating control signal OSC_EN is disabled. The counting selector  260  may output the final monitoring signal SEL_OUT by selecting the oscillating signal OSC when the oscillating control signal OSC_EN is enabled. 
     The counter  270  may count a toggling number of the final monitoring signal SEL_OUT based on a counting enable signal ROD_CNT_EN or the oscillating control signal OSC_EN. The counter  270  may output a counted toggling number as the counting signal CNT. The counting enable signal ROD_CNT_EN may be enabled when either the first enable signal ROD_EN 1  or the second enable signal ROD_EN 2  is enabled. The counter  270  may perform a counting operation when the counting enable signal ROD_CNT_EN or the oscillating control signal OSC_EN is enabled. The counter  270  may initialize the counting signal when the counting enable signal ROD_CNT_EN or the oscillating control signal OSC_EN is disabled. For example, the counter  270  may initialize the counting signal in response to a falling edge of the oscillating control signal OSC_EN. 
     Although not illustrated, the counting circuit  200  may further include a decoder that receives mode set signals from a mode register set (MRS) or a test mode register set (TMRS), and decodes the mode set signals to generate the first enable signal ROD_EN 1  and the second enable signal ROD_EN 2 . 
     When the first enable signal ROD_EN 1  or the second enable signal ROD_EN 2  is enabled, the first monitoring block  220 , the second monitoring block  240  and the ROD selector  250  of the counting circuit  200  may monitor the characteristics of the PMOS transistor or the characteristics of the NMOS transistor, and output the ROD monitoring signal ROD_OUT. The counting selector  260  may output the ROD monitoring signal ROD_OUT as the final monitoring signal SEL_OUT when the oscillating control signal OSC_EN is disabled. The counter  270  may count the toggling number of the final monitoring signal SEL_OUT, and output the counting signal CNT. At this time, the first semiconductor  20  may monitor the process variation based on the counting signal CNT, and compensate an operation according to a monitoring result. 
     On the contrary, when the oscillating control signal OSC_EN is enabled, the counting selector  260  may output oscillating signal OSC as the final monitoring signal SEL_OUT. The counter  270  may count the toggling number of the final monitoring signal SEL_OUT, and output the counting signal CNT. At this time, the voltage adjust circuit  300  may generate the adjusting voltage VCH according to the counting signal CNT. The voltage adjust circuit  300  may increase the voltage level of the adjusting voltage VCH in proportion to the counting value of the counting signal CNT. 
     In accordance with an embodiment of the present invention, the counting circuit  200  may be implemented by using an existing ROD, thereby detecting a voltage drop level of an internal voltage without increasing an area. 
     Hereinafter, an operation of detecting a voltage drop level of an internal voltage will be described with reference to  FIG. 1  to  FIG. 7B . 
       FIGS. 7A and 7B  are timing diagrams for describing an operation of detecting a voltage drop level of an internal voltage in accordance with an embodiment of the present invention. 
     Referring to  FIG. 7A , it is illustrated that the voltage drop level of the high voltage VPP is relatively small. 
     The voltage generation circuit  100  generates the oscillating signal OSC, which is toggling, while the oscillating control signal OSC_EN is enabled to a logic high level. The counting circuit  200  generates the counting signal CNT by counting the toggling number of the oscillating signal OSC. When the oscillating control signal OSC_EN is enabled to a logic high level for a relatively short time, the counting value (e.g., 4) of the counting signal CNT is relatively small. The voltage adjust circuit  300  increases the voltage level of the adjusting voltage VCH in proportion to the counting value (e.g., 4) of the counting signal CNT. For example, the adjusting voltage VCH has a voltage level greater than the source voltage VDD by a first level. 
     The oscillating circuit  110  of the voltage generation circuit  100  generates the first clock signal CLK 1  and the second clock signal CLK 2  which have a higher frequency according to the adjusting voltage VCH. The pumping circuit  120  pumps the source voltage VDD faster so that the high voltage VPP can reach a target voltage level more quickly. 
     Referring to  FIG. 7B , it is illustrated that the voltage drop level of the high voltage VPP is relatively large. 
     The voltage generation circuit  100  generates the oscillating signal OSC, which is toggling, while the oscillating control signal OSC_EN is enabled to a logic high level. The counting circuit  200  generates the counting signal CNT by counting the toggling number of the oscillating signal OSC. When the oscillating control signal OSC_EN is enabled to a logic high level for a relatively long time, the counting value (e.g., 24) of the counting signal CNT is relatively large. The voltage adjust circuit  300  increases the voltage level of the adjusting voltage VCH in proportion to the counting value (e.g., 24) of the counting signal CNT. For example, the adjusting voltage VCH has a voltage level greater than the source voltage VDD by a second level greater than the first level. 
     The oscillating circuit  110  of the voltage generation circuit  100  generates the first clock signal CLK 1  and the second clock signal CLK 2  which have a higher frequency according to the adjusting voltage VCH. The pumping circuit  120  pumps the source voltage VDD faster so that the high voltage VPP can reach a target voltage level more quickly. 
     Meanwhile, in the embodiment shown in  FIG. 1 , it is illustrated that an operation of the oscillating circuit  110  is controlled by the adjusting voltage VCH. Hereinafter, a case where the reference voltage VREF is adjusted by the adjusting voltage VCH will be described. 
       FIG. 8  is a block diagram illustrating a semiconductor system  40  in accordance with an embodiment of the present invention. 
     Referring to  FIG. 8 , the semiconductor system  40  may include a first semiconductor device  50  and a second semiconductor device  60 . 
     The second semiconductor device  60  may include a voltage adjust circuit  700  for generating an adjusting voltage VCH according to a counting signal CNT. The second semiconductor device  60  may be substantially the same as the second semiconductor device  30  of  FIG. 1 . 
     The first semiconductor device  50  may include a reference voltage generation circuit  400 , a voltage generation circuit  500  and a counting circuit  600 . 
     The reference voltage generation circuit  400  may adjust a voltage level of the reference voltage VREF according to the adjusting voltage VCH. The voltage generation circuit  500  may generate the oscillating control signal OSC_EN based on a high voltage VPP and the reference voltage VREF. The voltage generation circuit  500  may generate operational clock signals CLK 1  and CLK 2  according to the oscillating control signal OSC_EN. The voltage generation circuit  500  may generate the high voltage VPP by pumping the source voltage VDD according to the operational clock signals CLK 1  and CLK 2 . The counting circuit  600  may generate the counting signal CNT by counting an oscillating signal OSC corresponding to the operational clock signals CLK 1  and CLK 2  in response to the oscillating control signal OSC_EN. The counting circuit  600  may be substantially the same as the counting circuit  200 . 
     The voltage generation circuit  500  may include an oscillating circuit  510 , a pumping circuit  520 , and a detecting circuit  530 . 
     The oscillating circuit  510  may be activated by the oscillating control signal OSC_EN, and output the operational clock signals CLK 1  and CLK 2 . The oscillating circuit  510  may be substantially the same as the oscillator  114 , except that the oscillating circuit  510  uses the source voltage VDD instead of the driving voltage V_DR. The pumping circuit  520  and the detecting circuit  530  may be substantially the same as the pumping circuit  120  and the detecting circuit  130 . 
       FIG. 9  is a circuit diagram of the reference voltage generation circuit  400  of  FIG. 8 . 
     Referring to  FIG. 9 , the reference voltage generation circuit  400  may include a trimming controller  410 , a band-gap voltage generator  420  and a voltage trimmer  430 . 
     The trimming controller  410  may generate a trimming code TRIM_C&lt;n−1:1&gt; having multiple bits, according to the adjusting voltage VCH. The trimming controller  410  may detect a voltage level of the adjusting voltage VCH, and generate the trimming code TRIM_C&lt;n−1:1&gt; corresponding to the detected voltage level. The trimming controller  410  may generate the trimming code TRIM_C&lt;n−1:1&gt; so the reference voltage generation circuit  400  generates the reference voltage VREF having a higher voltage level as the voltage level of the adjusting voltage VCH increases. 
     The band-gap voltage generator  420  may be a bad-gap voltage VBG having a constant voltage level regardless of a variation of a voltage supplied from an external. 
     The voltage trimmer  430  may output the reference voltage VREF by trimming the bad-gap voltage VBG according to the trimming code TRIM_C&lt;n−1:1&gt;. 
     In detail, the voltage trimmer  430  may include a comparator OP 1 , a pull-up driver PU_DR 1 , a plurality of trimming resistors RT 1  to RTn, and a plurality of switches SW 1  to SWn−1. The pull-up driver PU_DR 1  may be composed of a PMOS transistor, and the plurality of switches SW 1  to SWn−1 may be composed of transistors, e.g., NMOS transistors. 
     The comparator OP 1  may output a driving control signal OPOUT by comparing the bad-gap voltage VBG with a feedback voltage VFB. The comparator OP 1  may output the driving control signal OPOUT transiting to a logic low level when the feedback voltage VFB has a voltage level lower than the bad-gap voltage VBG. 
     The pull-up driver PU_DR 1  may drive a first node DND 1  to a source voltage VDD according to the driving control signal OPOUT. 
     The plurality of trimming resistors RT 1  to RTn may be coupled in series between the first node DND 1  and a ground voltage (VSS) terminal. For reference, the feedback voltage VFB may be outputted from a common node CND 2  of two adjacent resistors RTn−1 and RTn, which are closest to the ground voltage (VSS) terminal among the plurality of trimming resistors RT 1  to RTn. 
     The plurality of switches SW 1  to SWn−1 may be coupled to an output terminal VREF_ND and respective common nodes of two adjacent resistors among the plurality of trimming resistors RT 1  to RTn. The reference voltage VREF may be outputted from the output terminal VREF_ND. For example, a first switch SW 1  may be coupled between the output terminal VREF_ND and a common node CND 1  of a first trimming resistor RT 1  and a second trimming resistor RT 2 . Each of the plurality of switches SW 1  to SWn−1 may be turned on in response to a corresponding bit of the trimming code TRIM_C&lt;n−1:1&gt;. 
     Accordingly, a voltage of the first node DND 1  is divided by the plurality of trimming resistors RT 1  to RTn, and the reference voltage VREF outputted from the output terminal VREF_ND has a voltage level determined according to a turned-on switch of the plurality of switches SW 1  to SWn−1. For example, when the first switch SW 1  is turned on in response to a first bit TRIM_C&lt;1&gt; of the trimming code TRIM_C&lt;n−1:1&gt;, the reference voltage VREF may be outputted by dividing the voltage of the first node DND 1  by a ratio of the first trimming resistor RT 1  to the remainder resistors RT 2  to RTn. 
     As described above, the reference voltage generation circuit  400  may generate the trimming code TRIM_C&lt;n−1:1&gt; according to the adjusting voltage VCH, and adjust the voltage level of a reference voltage VREF according to the trimming code TRIM_C&lt;n−1:1&gt;. The reference voltage generation circuit  400  may generate the trimming code TRIM_C&lt;n−1:1&gt; so that the reference voltage VREF has a higher voltage level as the voltage level of the adjusting voltage VCH increases. 
     The voltage generation circuit  500  may adjust a voltage level of the high voltage VPP according to the reference voltage VREF whose voltage level is adjusted by the adjusting voltage VCH. 
     In accordance with the present invention, a semiconductor device can detect a voltage drop level of an internal voltage in real time, and adjust a voltage level of the internal voltage based on a voltage drop detection results, thereby producing the internal voltage having a more stable voltage level. 
     As is apparent from the above descriptions, the semiconductor device in accordance with the embodiment selects a clock used for sampling data depending on a clock tree delay value during a training operation, and samples data based on the selected clock during a write operation. Therefore, the semiconductor device may secure a sufficient margin for the setup/hold time at the time of data sampling. 
     While the present invention has been described with respect to specific embodiments, the embodiments are not intended to be restrictive, but rather descriptive. Further, it is noted that the present invention may be achieved in various ways through substitution, change, and modification, by those skilled in the art without departing from the spirit and/or scope of the present invention as defined by the following claims.