Patent Publication Number: US-10321087-B2

Title: Solid-state image sensor and image sensing system

Description:
This is a continuation of U.S. patent application Ser. No. 14/662,604, filed Mar. 19, 2015. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to a solid-state image sensor and image sensing system. 
     Description of the Related Art 
     FIG. 2 of Japanese Patent Laid-Open No. 2001-223566 shows a comparator including pixels 201, 202, and 203, a current path formation block 210, a current path 211, and a comparison unit 215. The current path formation block 210 includes MOS transistors 204, 205, and 206 having gates to which charge-voltage converters of the pixels 201, 202, and 203 are respectively connected. The current path 211 includes a MOS transistor having a gate to which a reference voltage 212 is supplied. The comparison unit 215 includes an arithmetic amplifier including the current path formation block 210 and current path 211 as a differential pair, and can obtain a digital signal corresponding to a pixel signal based on the output from the comparison unit 215. 
     In this arrangement shown in FIG. 2 of Japanese Patent Laid-Open No. 2001-223566, a transistor 213 which forms the differential pair together with the amplification transistors 204, 205, and 206 of the pixels 201, 202, and 203 is provided outside the pixels 201, 202, and 203. In an arrangement like this, it is difficult to improve the balance between one current path and the other current path forming the differential pair, and this sometimes makes it difficult to sufficiently increase the readout accuracy of a pixel signal. 
     SUMMARY OF THE INVENTION 
     The present invention provides a technique advantageous to increase the readout accuracy of a pixel signal. 
     One of aspects of the present invention provides a solid-state image sensor comprising an image sensing unit including a plurality of pixel blocks, and a readout unit configured to read out a signal from the image sensing unit, wherein the pixel block includes a photoelectric converter, a first transistor, a second transistor, and a current source, a first main electrode of the first transistor and a first main electrode of the second transistor are connected to a common node, and the current source is provided in a path between the common node and a predetermined voltage, a readout operation for reading out a signal from the image sensing unit includes an operation in which a voltage corresponding to charges generated in the photoelectric converter is supplied to a control electrode of the first transistor, and a temporally changing reference voltage is supplied to a control electrode of the second transistor, and the readout unit reads out a signal from the image sensing unit via a second main electrode of the first transistor. 
     Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a view showing the arrangement of a solid-state image sensor according to one embodiment of the present invention; 
         FIG. 2  is a view showing the arrangement of a solid-state image sensor according to another embodiment of the present invention; 
         FIG. 3  is a view for exemplarily explaining the principle of the present invention; 
         FIG. 4  is a view showing the arrangement of an image sensing unit of the solid-state image sensor according to the first embodiment of the present invention; 
         FIG. 5  is a view showing the operation of the solid-state image sensor according to the first embodiment of the present invention; 
         FIG. 6  is a view showing the arrangement of an image sensing unit of a solid-state image sensor according to the second embodiment of the present invention; 
         FIG. 7  is a view showing the operation of the solid-state image sensor according to the second embodiment of the present invention; 
         FIGS. 8A and 8B  are views showing arrangement examples of a signal processing unit applicable to the first and second embodiments; 
         FIG. 9  is a view showing the arrangement of an image sensing unit of a solid-state image sensor according to the third embodiment of the present invention; 
         FIG. 10  is a view showing an arrangement example of a signal processing unit applicable to the third embodiment; 
         FIG. 11  is a view showing the arrangement of an image sensing unit of a solid-state image sensor according to the fourth embodiment of the present invention; 
         FIG. 12  is a view showing the operation of the solid-state image sensor according to the fourth embodiment of the present invention; 
         FIG. 13  is a view showing the arrangement of an image sensing unit of a solid-state image sensor according to the fifth embodiment of the present invention; 
         FIG. 14  is a view showing the operation of the solid-state image sensor according to the fifth embodiment of the present invention; 
         FIG. 15  is a view showing the arrangement of an image sensing unit of a solid-state image sensor according to the sixth embodiment of the present invention; 
         FIG. 16  is a view showing the first application example as an application example of the first embodiment shown in  FIG. 4 ; 
         FIG. 17  is a view showing the operation of the first application example; 
         FIG. 18  is a view showing an arrangement example of a signal processing unit in the first application example; 
         FIG. 19  is a view showing another operation of the first application example; 
         FIG. 20  is a view for explaining still another operation of the first application example; 
         FIG. 21  is a view showing the second application example as an application example of the fourth embodiment shown in  FIG. 11 ; 
         FIG. 22  is a view showing the operation of the second application example; 
         FIG. 23  is a view showing the third application example as another application example of the fourth embodiment shown in  FIG. 11 ; and 
         FIG. 24  is a view showing the arrangement of an image sensing system as an embodiment of the present invention. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Exemplary embodiments of the present invention will be explained below with reference to the accompanying drawings. 
       FIG. 1  shows the arrangement of a solid-state image sensor  1  according to one embodiment of the present invention. The solid-state image sensor  1  includes an image sensing unit  110 , and a readout unit  140  for reading out a signal from the image sensing unit  110 . The image sensing unit  110  includes a plurality of pixels  112  as arranged as to form a plurality of rows and a plurality of columns, and each pixel  112  includes a photoelectric converter such as a photodiode. In other viewpoints, the image sensing unit  110  includes a plurality of pixel blocks, each pixel block includes at least one pixel  112 , and each pixel includes a photoelectric converter. 
     The solid-state image sensor  1  includes a vertical scanning unit (vertical selecting unit)  120  and horizontal scanning unit (horizontal selecting unit)  150  for selecting a pixel  112  from which a signal is read out. The vertical scanning unit  120  selects a row to be read out from a plurality of rows in the image sensing unit  110 , and the readout unit  140  reads out signals of the pixels  112  in the selected row through a vertical transmission path  114 . The horizontal scanning unit  150  selects the pixels  112  in a column to be read out from the signals of the pixels  112  in the plurality of columns read out by the readout unit  140 , and outputs signals of the selected pixels  112  to an output signal line  160 . That is, the horizontal scanning unit  150  selects a column to be read out from the plurality of columns in the image sensing unit  110 . 
     The solid-state image sensor  1  further includes a reference voltage generator  130 . The reference voltage generator  130  generates a temporally changing reference voltage. This temporally changing reference voltage is typically a ramp signal. The reference voltage generated by the reference voltage generator  130  can be supplied, via the vertical scanning unit  120 , to a pixel block  113  including the pixels  112  in the row to be read out of the image sensing unit  110 . The reference voltage may also be supplied to the pixel block  113  without using the vertical scanning unit  120 . As exemplarily shown in  FIG. 3 , each pixel block  113  includes at least one photoelectric converter (for example, a photodiode) PD, a first transistor M 1 , a second transistor M 2 , and a current source M 3 . The first main electrode (in this example, the source electrode) of the first transistor M 1  and the first main electrode (in this example, the source electrode) of the second transistor M 2  are connected to a common node CN, and the third transistor M 3  is provided in a path between the common node CN and a predetermined potential (in this example, a ground potential). The third transistor M 3  functions as a current source when a predetermined bias voltage is applied to the control electrode (gate). The first transistor M 1 , second transistor M 3 , and current source M 3  form a differential amplifier circuit. An output from this differential amplifier circuit is transmitted to the readout unit  140  through the vertical transmission path  114 . In the example shown in  FIG. 3 , one vertical transmission path  114  includes first and second vertical signal lines  114   a  and  114   b  which form a differential signal line pair. In another example, one vertical transmission path  114  includes one vertical signal line  114   a.    
     A readout operation for reading out a signal from the image sensing unit  110  includes an operation in which a voltage corresponding to charges generated in the photoelectric converter PD of the pixel  112  to be read out is supplied to the control electrode of the first transistor M 1 , and a temporally changing reference voltage VRMP is supplied to the control electrode of the second transistor M 2 . Note that the control electrode is the gate electrode. The readout unit  140  reads out a signal from the image sensing unit  110  through the second main electrode (in this example, the drain electrode) of the first transistor M 1  and the vertical transmission path  114 . In the example shown in  FIG. 3 , the readout unit  140  reads out a signal from the image sensing unit  110  based on a signal transmitted to the first vertical signal line  114   a  connected to the second main electrode of the first transistor M 1 , and a signal transmitted to the second vertical signal line  114   b  connected to the main electrode of the second transistor M 2 . The charges generated in the photoelectric converter PD are transferred, through a transfer transistor MT, to a charge-voltage converter (floating diffusion) fd connected to the control electrode (gate) of the first transistor M 1 , and converted into a voltage by the charge-voltage converter fd. The voltage of the charge-voltage converter fd is reset by a voltage control transistor MR. 
     A transfer signal φT driven by the vertical scanning unit  120  is applied to the gate of the transfer transistor MT. A voltage control signal φR driven by the vertical scanning unit  120  is applied to the gate of the voltage control transistor MR. In the following description, when distinguishing between one transfer signal and another transfer signal, numbers are added after φT like φT 1  and φT 2 . Similarly, when distinguishing between one voltage control signal and another voltage control signal, numbers are added after φR like φR 1  and φR 2 . This applies to other signals. 
     The readout unit  140  converts a signal transmitted from the pixel  112  of the image sensing unit  110  through the vertical transmission path  114  into a digital signal, and outputs the signal to the output signal line  160 . In a general solid-state image sensor which outputs a pixel signal as a digital signal, a column amplifier formed for each column of an image sensing unit reads out a signal from a pixel in the form of an analog voltage signal, and an AD converter converts this analog voltage signal into a digital signal. To the contrary, in the solid-state image sensor  1  of this embodiment, a signal transmitted from a pixel to the vertical transmission path  114  has a form in current signal, and this current signal is converted into a digital signal. 
     The readout unit  140  can include a signal processing unit  142 , counter  144 , and memory  146 . A set of the signal processing unit  142 , counter  144 , and memory  146  can be formed for each column of the image sensing unit  110 . The signal processing unit  142  receives an electric current supplied from the second main electrode of the first transistor M 1  through the vertical transmission path  114 . Based on the value of this electric current, the signal processing unit  142  detects a timing at which the magnitude relation between the voltage of the control electrode of the first transistor M 1  (this voltage is also the voltage of the charge-voltage converter fd) and the voltage (reference voltage VRMP) of the control electrode of the second transistor M 2  inverts. For example, the signal processing unit  142  compares the value of a first electric current supplied from the second main electrode of the first transistor M 1  through the first vertical signal line  114   a  with the value of a second electric current supplied from the second main electrode of the second transistor M 2  through the second vertical signal line  114   b . Then, the signal processing unit  142  outputs a comparison result signal indicating the magnitude relation between the values of the first and second electric currents. The inversion of this comparison result signal means that the magnitude relation between the values of the first and second electric currents has inverted. Also, the inversion of the magnitude relation between the values of the first and second electric currents is equivalent to the inversion of the magnitude relation between the voltages of the control electrodes of the first and second transistors M 1  and M 2 . 
     The counter  144  starts a count operation at a predetermined timing, and stops the count operation in accordance with the inversion of the comparison result signal. The memory  146  holds a count value (that is, a pixel value) obtained by the counter  144 , and outputs the count value to the output signal line  160  when selected by the horizontal scanning unit  150 . That is, the readout unit  140  decides that the count value of the counter  144  is the value of a signal read out from the image sensing unit  110 , in accordance with the inversion of the output from the signal processing unit  142 . 
       FIG. 2  shows the arrangement of a solid-state image sensor  1 ′ of another embodiment of the present invention. The solid-state image sensor  1 ′ differs from the solid-state image sensor  1  in that the plurality of counters  144  (that is, the counter  144  formed for each column) of the solid-state image sensor  1  are replaced with one common counter  148 . In the solid-state image sensor  1 ′, the memory  146  holds the count value of the counter  148  in response to the inversion of the comparison result signal from the signal processing unit  142 . In the example shown in  FIG. 2 , the readout unit  140  decides, for each column, that the count value of the common counter  148  is the value of a signal read out from the image sensing unit  110 , in accordance with the inversion of the output from the signal processing unit  142 . 
     In the architecture as described above, the first transistor M 1 , second transistor M 2 , and current source M 3  are provided close to each other. This makes it possible to decrease both the parasitic resistances on the source sides of the first and second transistors M 1  and M 2 . Accordingly, it is possible to improve the balance between the current path including the first transistor M 1  and the current path including the second transistor M 2 , thereby improving the differential input characteristic balance. As a consequence, the pixel signal readout accuracy increases. 
     More practical embodiments will be explained below.  FIG. 4  shows the arrangement of an image sensing unit  110  of a solid-state image sensor of the first embodiment. For the sake of simplicity, a plurality of pixels  112  forming the image sensing unit  110  are represented by two rows×two columns of pixels  112 . In this solid-state image sensor of the first embodiment, one pixel  112  forms one pixel block. Each pixel  112  (a pixel block) includes a photoelectric converter PD such as a photodiode, a first transistor M 1 , a second transistor M 2 , and a current source M 3  formed by a transistor or the like. Each pixel  112  can also include a transfer transistor MT and voltage control transistor MR. 
     The first main electrode (source electrode) of the first transistor M 1  and the first main electrode (source electrode) of the second transistor M 2  are connected to a common node CN, and the third transistor M# is provided in a path between the common node CN and a predetermined potential (in this example, a ground potential). The third transistor M 3  functions as a tail current source when a predetermined bias voltage Vbias is applied to the control electrode (gate). The first transistor M 1 , second transistor M 2 , and current source M 3  form a differential amplifier circuit. This circuit formed by the first transistor M 1 , second transistor M 2 , and current source M 3  can also be regarded as a voltage comparator for comparing the voltage of the control electrode of the first transistor M 1  (this voltage is also the voltage of a charge-voltage converter fd) with the voltage (a reference voltage VRMP) of the control electrode of the second transistor M 2 . 
     A readout operation for reading out a signal from the image sensing unit  110  includes an operation in which a voltage corresponding to charges generated in the photoelectric converter PD of the pixel  112  to be read out is supplied to the control electrode of the first transistor M 1 , and the temporally changing reference voltage VRMP is supplied to the control electrode of the second transistor M 2 . A readout unit  140  reads out a signal from the image sensing unit  110  through the second main electrode of the first transistor M 1  and a vertical transmission path  114 . 
       FIG. 5  shows the operation of the solid-state image sensor of the first embodiment, more specifically, a two-row signal readout operation.  FIG. 5  shows a one-row readout period as “1H” (one horizontal scanning period). A first-row readout period is a period in which a first-row bias signal φB 1  is High (a bias voltage), and a second-row bias signal φB 2  is Low. When the bias signal φB 1  activates the current source M 3  of the pixels  112  in the first row, the pixels  112  in the first row are set in a selected state. When the bias signal φB 1  deactivates the current source M 3  of the pixels  112  in the first row, the pixels  112  in the first row are set in an unselected state. When the bias signal φB 2  activates the current source M 3  of the pixels  112  in the second row, the pixels  112  in the second row are set in the selected state. When the bias signal φB 2  deactivates the current source M 3  of the pixels  112  in the second row, the pixels  112  in the second row are set in the unselected state. 
     In the first-row readout period, a predetermined bias voltage Vbias is applied to the gate of the transistor forming each current source M 3  in the first row, and the current source M 3  functions as a tail constant current source. First, a voltage control signal φR 1  is activated to High level. Consequently, the voltage control transistor MR is turned on, and the charge-voltage converter fd is reset to a voltage (reset voltage) corresponding to a reset voltage VRES. 
     Then, the voltage control signal φR 1  is deactivated to Low level, and the charge-voltage converter fd floats. The initial voltage of the reference voltage VRMP is set to be much higher than the reset voltage of the charge-voltage converter fd such that almost the while electric current supplied by the current source M 3  (the electric current defined by the current source M 3 ) flows through the second transistor M 2 , and an electric current flowing through the first transistor M 1  is almost zero. The reference voltage VRMP is linearly dropped, and a counter  144  ( 148 ) measures a time before the comparison result signal output from the signal processing unit  142  inverts due to the inversion of the magnitude relation between the reset voltage and reference voltage VRMP. The count value obtained by the counter  144  ( 148 ) and held in a memory  146  is a digital value (to be referred to as a noise value hereinafter) corresponding to the reset voltage (noise level) of the pixel  112 . Reference symbol N_AD denotes the operation of holding the digital value corresponding to the reset voltage in the memory  146  as described above. 
     Subsequently, the reference voltage VRMP is returned to the initial voltage, and the transfer signal φT 1  is activated to High level. As a consequence, charges photoelectrically converted and accumulated by the photoelectric converter PD are transferred to the charge-voltage converter fd. After the transfer signal φT 1  is deactivated to Low level, the reference voltage VRMP is linearly dropped. The counter  144  ( 148 ) measures a time before the comparison result signal output from the signal processing unit  142  inverts due to the inversion of the magnitude relation between the voltage of the charge-voltage converter fd and the reference voltage VRMP. The count value obtained by the counter  144  ( 148 ) and held in the memory  146  is a digital value (to be referred to as an optical signal value hereinafter) corresponding to the amount of charges generated by photoelectric conversion in the photoelectric converter PD of the pixel  112 . Reference symbol S_AD denotes the operation of holding the digital value corresponding to the amount of charges generated by photoelectric conversion in the memory  146  as described above. The noise value and optical signal value held in the memory  146  can separately be output. It is also possible to output a value obtained by subtracting the noise value from the optical signal value (that is, a value subjected to CDS (Correlated Double Sampling)). 
     A second readout period is a period in which the second-row bias signal φB 2  is High (a bias voltage), and the first-row bias signal φB 1  is Low. A second-row read operation is executed by the same method as that for the first row. 
       FIG. 6  shows the arrangement of an image sensing unit  110  of a solid-state image sensor of the second embodiment.  FIG. 7  shows the operation of the solid-state image sensor of the second embodiment, more specifically, a two-row signal readout operation.  FIG. 7  shows a one-row readout period as “1H” (one horizontal scanning period). For the sake of simplicity, a plurality of pixels  112  forming the image sensing unit  110  are represented by two rows×two columns of pixels  112 . In the second embodiment, two pixels  112  share a third transistor M 3  functioning as a tail current source. In the first embodiment, the bias signals φB 1  and φB 2  control row selection and non-selection. In the second embodiment, selection signals φSEL 1  and φSEL 2  control row selection and non-selection. In addition, in the second embodiment, a selection transistor MS is provided between a second transistor M 2  and the current source M 3  by the selection signals φSEL (φSEL 1  and φSEL 2 ). The second embodiment is the same as the first embodiment except the above differences. 
     In the second embodiment, two pixels  112  share the third transistor M 3 . However, more pixels  112  may share the third transistor M 3 . For example, the pixels  112  in one column may share the third transistor M 3 . 
       FIG. 8A  shows the first example of the signal processing unit  142  applicable to the first and second embodiments. A first vertical signal line  114   a  is connected to a current mirror CM 1  formed by a transistor such as a PMOS transistor. A second vertical signal line  114   b  is connected to a current mirror CM 2  formed by a transistor such as a PMOS transistor. A transistor M 71  is provided between the current mirror CM 1  and a reference potential, a transistor M 72  is provided between the current mirror CM 2  and reference potential, and the transistors M 71  and M 72  form a current mirror. Consequently, the voltage of an output node between the current mirror CM 1  and transistor M 71  is determined by the magnitude relation between the electric currents of the first and second vertical signal lines  114   a  and  114   b . A signal appearing at this output node is output as a comparison result signal comp out via a buffer circuit BF such as an inverter. Current sources CS 1  and CS 2  may also be connected to the first and second vertical signal lines  114   a  and  114   b , respectively. The current sources CS 1  and CS 2  prevent the electric current flowing through the current mirrors CM 1  and CM 2  from becoming zero, thereby improving the response characteristic of the signal processing unit  142 . The electric currents supplied by the current sources CS 1  and CS 2  are preferably smaller than the electric current supplied by the current source M 3 . 
       FIG. 8B  shows the second example of the signal processing unit  142  applicable to the first and second embodiments. A first vertical signal line  114   a  is pulled up to a predetermined power supply VDD by a pull-up resistor R 1 . Likewise, a second vertical signal line  114   b  is pulled up to the power supply voltage VDD by the pull-up resistor R 1 . Consequently, electric currents flowing through the first and second vertical signal lines  114   a  and  114   b  are converted into voltages by nodes N 1  and N 2 , respectively. The nodes N 1  and N 2  are connected to the input nodes of a differential amplifier DA in an open-loop state. The differential amplifier DA outputs a comparison result signal comp out. 
       FIG. 9  shows the arrangement of an image sensing unit  110  of a solid-state image sensor of the third embodiment. For the sake of simplicity, a plurality of pixels  112  forming the image sensing unit  110  are represented by two rows×two columns of pixels  112 . The third embodiment differs from the first and second embodiments in that each vertical transmission path  114  is formed by one vertical signal line  114   a . In the third embodiment, a predetermined potential (for example, a power supply voltage VDD) is supplied to the second main electrode of a second transistor M 2 .  FIG. 10  shows the first example of a signal processing unit  142  applicable to the third embodiment. A vertical signal line  114   a  and current source CS 3  are connected to a current mirror CM 3 , the value of an electric current flowing through the vertical signal line  114   a  is compared with the value of an electric current flowing through the current source CS 3 , and a comparison result signal comp out is output. The signal processing unit  142  generates the comparison result signal comp out indicating the magnitude relation between the voltage of a charge-voltage converter fd and a reference voltage VRMP in the third embodiment as well. 
       FIG. 11  shows the arrangement of an image sensing unit  110  of a solid-state image sensor of the fourth embodiment.  FIG. 12  shows the operation of the solid-state image sensor of the fourth embodiment, more specifically, a two-row signal readout operation.  FIG. 12  shows a one-row readout period as “1H” (one horizontal scanning period). For the sake of simplicity, a plurality of pixels  112  forming the image sensing unit  110  are represented by two rows×two columns of pixels  112 . 
     In the fourth embodiment, when a pixel  112   a  is a pixel to be read out, a signal of the pixel  112   a  is read out by using a transistor M 2  of a pixel  112   b  different from the pixel  112   a  as a second transistor. Also, when the pixel  112   b  is a pixel to be read out, a signal of the pixel  112   b  is read out by using a transistor M 1  of the pixel  112   a  different from the pixel  112   b  as a second transistor. In another viewpoint, it is possible to regard that the pixels  112   a  and  112   b  form one pixel block  113 , and the pixel block  113  includes the first transistor M 1 , the second transistor M 2 , and a current source M 3 . A readout operation for reading out a signal from the image sensing unit  110  includes an operation in which a voltage corresponding to charges generated in a photoelectric converter PD of the pixel block  113  is supplied to the control electrode of the first transistor M 1 , and a temporally changing reference voltage VRMP is supplied to the control electrode of the second transistor M 2 . 
     A reset voltage VRES or the reference voltage VRMP is supplied to the drain of a voltage control transistor TR via switches S (S 1  and S 2 ). More specifically, the reset voltage VRES is supplied to a charge-voltage converter fd (fd 1  or fd 2 ) of the pixel  112  ( 112   a  or  112   b ) to be read out in the pixel block  113 . On the other hand, the reference voltage VRMP is supplied to the charge-voltage converter fd of the pixel  112  ( 112   a  or  112   b ) not to be read out. 
     In a first-row readout period, φS 1  and φR 2  are changed to High level, and φS 2  is changed to Low level. First, a first-row voltage control signal φR 1  is activated to High level. Consequently, the voltage control transistor MR of the pixel  112   a  in the first row is turned on, and the charge-voltage converter fd 1  of the pixel  112   a  in the first row is reset to a voltage (reset voltage) corresponding to the reset voltage VRES. The reference voltage VRMP is supplied to the charge-voltage converter fd 2  of the pixel  112   b  in the second row. Accordingly, as in the first embodiment, an operation (N_AD) of holding a digital value corresponding to the reset voltage in a memory  146  and an operation (S_AD) of holding a digital value corresponding to the amount of charges generated by photoelectric conversion in the memory  146  are performed. 
     In a second-row readout period, φS 2  and φR 1  are changed to High level, and φS 1  is changed to Low level. First, a second-row voltage control signal φR 2  is activated to High level. Consequently, the voltage control transistor MR of the pixel  112   b  in the second row is turned on, and the charge-voltage converter fd 2  of the pixel  112   b  in the second row is reset to the voltage (reset voltage) corresponding to the reset voltage VRES. The reference voltage VRMP is supplied to the charge-voltage converter fd 1  of the pixel  112   a  in the first row. Accordingly, the operation (N_AD) of holding the digital value corresponding to the reset voltage in the memory  146  and the operation (S_AD) of holding the digital value corresponding to the amount of charges generated by photoelectric conversion in the memory  146  are performed for the pixel in the second row. 
       FIG. 13  shows the arrangement of an image sensing unit  110  of a solid-state image sensor of the fifth embodiment.  FIG. 14  shows the operation of the solid-state image sensor of the fifth embodiment, more specifically, a four-row signal readout operation. For the sake of simplicity, a plurality of pixels  112  forming the image sensing unit  110  are represented by four rows×two columns of pixels  112 . In the fifth embodiment, a signal line for supplying a reference voltage VRMP and a signal line for supplying a reset voltage VRES are integrated as a common signal line VRES/VRMP. A first switch MR 1  controlled by a first voltage control signal φR 1  is provided in a path between a first charge-voltage converter fd 1  and the signal line VRES/VRMP. Also, a second switch MR 2  controlled by a second voltage control signal φR 2  is provided in a path between a second charge-voltage converter fd 2  and the signal line VRES/VRMP. Furthermore, in the fifth embodiment, two photoelectric converters in adjacent rows share one charge-voltage converter. More specifically, photoelectric converters PD 1  and PD 2  share the first charge-voltage converter fd 1 , and photoelectric converters PD 3  and PD 4  share the second charge-voltage converter fd 2 . 
     In read periods of the first to fourth rows, a bias voltage Vbias is supplied to the control electrode (gate) of a third transistor M 3 . In the first-row read period, the first voltage control signal φR 1  for the first and second rows is activated to High level, and a reset voltage (a voltage lower than the initial voltage of the reference voltage) is supplied from the signal line VRES/VRMP. After that, the first voltage control signal φR 1  is deactivated to Low level. In the period during which the first voltage control signal φR 1  is activated to High level, the resetting of the first charge-voltage converter fd 1  for the first and second rows is complete. 
     Then, the reference voltage VRMP is supplied to the signal line VRES/VRMP, and the second voltage control signal φR 2  for the third and fourth rows is activated to High level. Consequently, the reference voltage VRMP is supplied to the second charge-voltage converter fd 2  for the third and fourth rows. The reference voltage VRMP is linearly dropped, and a counter  144  ( 148 ) measures a time before a comparison result signal output from a signal processing unit  142  inverts due to the inversion of the magnitude relation between the reset voltage and reference voltage VRMP (N_AD). Subsequently, the reference voltage VRMP is returned to the initial voltage, and a transfer signal φT 1  is activated to High level. As a consequence, charges photoelectrically converted and accumulated by the photoelectric converter PD 1  in the first row are transferred to the first charge-voltage converter fd 1 . After the transfer signal φT 1  is deactivated to Low level, the reference voltage VRMP is linearly dropped. Then, the counter  144  ( 148 ) measures a time before the comparison result signal output from the signal processing unit  142  inverts due to the inversion of the magnitude relation between the voltage of the first charge-voltage converter fd 1  and the reference voltage VRMP (S_AD). 
     In the second-row readout period, the first voltage control signal φR 1  for the first and second rows is activated to High level, and the reset voltage (a voltage lower than the initial voltage of the reference voltage) is supplied from the signal line VRES/VRMP. After that, the first voltage control signal φR 1  is deactivated to Low level. In the period during which the first voltage control signal φR 1  is activated to High level, the resetting of the first charge-voltage converter fd 1  for the first and second rows is complete. 
     Then, the reference voltage VRMP is supplied to the signal line VRES/VRMP, and the second voltage control signal φR 2  for the third and fourth rows is activated to High level. Consequently, the reference voltage VRMP is supplied to the second charge-voltage converter fd 2  for the third and fourth rows. The reference voltage VRMP is linearly dropped, and the counter  144  ( 148 ) measures a time before the comparison result signal output from the signal processing unit  142  inverts due to the inversion of the magnitude relation between the reset voltage and reference voltage VRMP (N_AD). Subsequently, the reference voltage VRMP is returned to the initial voltage, and a transfer signal φT 2  is activated to High level. As a consequence, charges photoelectrically converted and accumulated by the photoelectric converter PD 2  in the second row are transferred to the first charge-voltage converter fd 1 . After the transfer signal φT 2  is deactivated to Low level, the reference voltage VRMP is linearly dropped. Then, the counter  144  ( 148 ) measures a time before the comparison result signal output from the signal processing unit  142  inverts due to the inversion of the magnitude relation between the voltage of the charge-voltage converter fd and the reference voltage VRMP (S_AD). 
     In the third-row readout period, the second voltage control signal φR 2  for the third and fourth rows is activated to High level, and the reset voltage (a voltage lower than the initial voltage of the reference voltage) is supplied from the signal line VRES/VRMP. After that, the second voltage control signal φR 2  is deactivated to Low level. In the period during which the second voltage control signal φR 2  is activated to High level, the resetting of the second charge-voltage converter fd 2  for the third and fourth rows is complete. 
     Then, the reference voltage VRMP is supplied to the signal line VRES/VRMP, and the first voltage control signal φR 1  for the first and second rows is activated to High level. Consequently, the reference voltage VRMP is supplied to the first charge-voltage converter fd 1  for the first and second rows. The reference voltage VRMP is linearly dropped, and the counter  144  ( 148 ) measures a time before the comparison result signal output from the signal processing unit  142  inverts due to the inversion of the magnitude relation between the reset voltage and reference voltage VRMP (N_AD). Subsequently, the reference voltage VRMP is returned to the initial voltage, and a transfer signal φT 3  is activated to High level. As a consequence, charges photoelectrically converted and accumulated by the photoelectric converter PD 3  in the third row are transferred to the second charge-voltage converter fd 2 . After the transfer signal φT 3  is deactivated to Low level, the reference voltage VRMP is linearly dropped. Then, the counter  144  ( 148 ) measures a time before the comparison result signal output from the signal processing unit  142  inverts due to the inversion of the magnitude relation between the voltage of the second charge-voltage converter fd 2  and the reference voltage VRMP (S_AD). 
     In the fourth-row readout period, the second voltage control signal φR 2  for the third and fourth rows is activated to High level, and the reset voltage (a voltage lower than the initial voltage of the reference voltage) is supplied from the signal line VRES/VRMP. After that, the second voltage control signal φR 2  is deactivated to Low level. In the period during which the second voltage control signal φR 2  is activated to High level, the resetting of the second charge-voltage converter fd 2  for the third and fourth rows is complete. 
     Then, the reference voltage VRMP is supplied to the signal line VRES/VRMP, and the first voltage control signal φR 1  for the first and second rows is activated to High level. Consequently, the reference voltage VRMP is supplied to the first charge-voltage converter fd 1  for the first and second rows. The reference voltage VRMP is linearly dropped, and the counter  144  ( 148 ) measures a time before the comparison result signal output from the signal processing unit  142  inverts due to the inversion of the magnitude relation between the reset voltage and reference voltage VRMP (N_AD). Subsequently, the reference voltage VRMP is returned to the initial voltage, and a transfer signal φT 4  is activated to High level. As a consequence, charges photoelectrically converted and accumulated by the photoelectric converter PD 4  in the fourth row are transferred to the second charge-voltage converter fd 2 . After the transfer signal φT 4  is deactivated to Low level, the reference voltage VRMP is linearly dropped. Then, the counter  144  ( 148 ) measures a time before the comparison result signal output from the signal processing unit  142  inverts due to the inversion of the magnitude relation between the voltage of the second charge-voltage converter fd 2  and the reference voltage VRMP (S_AD). 
     In the fifth embodiment, two photoelectric converters share one charge-voltage converter. However, more photoelectric converters may also share one charge-voltage converter. The signal line VRES/VRMP may be connected to the charge-voltage converters in the same column via the reset switches MR, and may also be connected to all the charge-voltage converters via the reset switches MR. Accordingly, the signal line VRES/VRMP may be provided along the column direction, and may also be provided in a matrix along the row and column directions. 
       FIG. 15  shows the arrangement of an image sensing unit  110  of a solid-state image sensor of the sixth embodiment. In the sixth embodiment, switches M 4  and M 5  which are opened and closed under the control of φS 1  and φS 2  are added between a first transistor M 1  and first vertical signal line  114   a . Also, switches M 6  and M 7  which are opened and closed under the control of φS 2  and φS 1  are added between a second transistor M 2  and second vertical signal line  114   b . In the sixth embodiment, it is possible to transmit a signal corresponding to a noise level and optical signal via the first vertical signal line  114   a , and transmit a signal corresponding to a reference voltage VRMP via the second vertical signal line  114   b , regardless of a row to be read out. Accordingly, it is unnecessary to switch operations of a signal processing unit  142  in accordance with a row to be read out. 
       FIG. 16  shows the first application example as an application example of the first embodiment shown in  FIG. 4 . In the first application example, a signal processing unit  104  generates and outputs a signal (for example, a signal obtained by averaging a plurality of pixel signals) representing signals of at least two pixels  112   a  and  112   b  (at least two pixel blocks  113 ) belonging to different rows. When a signal is thus output by averaging a plurality of pixel signals, the effective number of pixels reduces, and the spatial resolution decreases, but a high-S/N image can be output at high speed, and this can be the merit of the system. The first application example is different from the first embodiment shown in  FIG. 4  in that the switches controlled by the bias signals φB 1  and φB 2  are simultaneously connected to the Vbias side. 
     The operation of the first application example will be explained with reference to  FIG. 17 . When the voltage control signals φR 1  and φR 2  are simultaneously activated to High level, fd 1  and fd 2  are simultaneously reset to the reset voltage VRES. The reference voltage VRMP is supplied to the transistor M 2 . Then, N_AD is performed which changing the reference voltage VRMP. Subsequently, the transfer signals φT 1  and φT 2  are simultaneously activated to High level, and photoelectrically converted charges are transferred to the charge-voltage converters fd 1  and fd 2 . Then, S_AD is performed while changing the reference signal VRMP. In each of the pixels  112   a  and  112   b , the first and second transistors M 1  and M 2  form a differential signal line pair. The second main electrode of the first transistor M 1  is connected to the first vertical signal line  114   a , and the second main electrode of the second transistor M 2  is connected to the second vertical signal line  114   b . The current sources M 3  of the pixels  112   a  and  112   b  are simultaneously activated. The current sources M 3  of the pixels  112   a  and  112   b  have the same structure. Values I_VL 1  and I_VL 2  of electric currents flowing through the vertical signal lines  114   a  and  114   b  can change as shown in, for example,  FIG. 17 . 
     Details will be explained below. In N_AD and S_AD, the initial voltage of the reference voltage VRMP is controlled to be higher than voltages Vfd 1  and Vfd 2  of the charge-voltage converters fd 1  and fd 2 , that is, controlled such that VRMP&gt;Vfd 1  and VRMP&gt;Vfd 2 . As a result, in the pixels  112   a  and  112   b , the second transistors M 2  are turned on, and the first transistors M 1  are turned off. Accordingly, the electric current I_VL 1  flowing through the vertical signal line  114   a  is the sum of electric currents flowing through the current sources M 3  of the two pixels  112   a  and  112   b . Also, the electric current I_VL 2  flowing through the vertical signal line  114   b  is 0. 
     Subsequently, ramp-down of the reference voltage VRMP is started, and VRMP&lt;Vfd 1  holds at time  1  in N_AD and at time t 3  in S_AD. In the pixel  112   a , therefore, M 1  is turned on, M 2  is turned off, I_VL 1  reduces, and I_VL 2  increases. In addition, when VRMP&lt;Vfd 2  holds at time t 2  in N_AD and at time t 4  in S_AD, M 1  is turned on, M 2  is turned off, and I_VL 2  further reduces to 0 in the pixel  112   b . Consequently, I_VL 2  further increases and becomes the sum of the electric currents flowing through the current sources M 3  of the two pixels  112   a  and  112   b.    
     The signal processing unit  104  detects changes in electric currents I_VL 1  and/or I_VL 2 , thereby detecting times t 1  and t 2  in the N_AD period and times t 3  and t 4  in the S_AD period. Letting fclk be the frequency of the count clock in a period from the start of count by the counter  144  ( 148 ) to t 1  or t 3 , the frequency of the count clock from t 1  or t 3  to t 2  or t 4  at which the count is terminated can be controlled to fclk/2. This makes it possible to obtain the average value of the signals of the pixels  112   a  and  112   b . Although the frequency of the count clock is changed in the first application example, the substance of the first application example is to detect times t 1 , t 2 , t 3 , and t 4 , so changing the count clock frequency is merely an example. For example, it is also possible to use two counters which operate by count clocks having the same frequency, output, as digital codes, a period from the start of count to t 1  or t 3  and a period from the start of count to t 2  or t 4 , and add these codes by digital addition. 
       FIG. 18  shows one arrangement example of the signal processing unit  142  according to the first application example. By setting the current mirror ratio as exemplified in  FIG. 18 , current changes can be detected by two different thresholds. The detection results are output from two inverters shown in  FIG. 18 . 
       FIG. 19  shows an example in which a signal indicating a median value is generated from a plurality of pixel signals as a signal representing the plurality of signals. Referring to  FIG. 19 , an example in which a signal indicating the median value of signals of three pixels ( 112   a ,  112   b , and  112   c ) is output is provided. The current sources M 3  of the pixels  112   a ,  112   b , and  112   c  have the same structure.  FIG. 19  shows only a period during which the reference voltage VRMP is linearly dropped. As exemplified in  FIG. 19 , three change points t 1 , t 2 , and t 3  appear in I_VL 1  and I_VL 2 . To obtain a signal indicating the median value of the signals of the three pixels, counting need only be stopped at t 2 , so an intermediate threshold need only be set to be able to detect t 2 . The example in which a signal indicating the median value of signals of three pixels is generated has been explained, but the median value can easily be obtained for a larger number of pixels. 
       FIG. 20  shows an example in which signals of two pixels are simultaneously read out and A/D conversion is performed on each signal. Assume that the magnitudes (current values) of the current sources M 3  of the two pixels  112   a  and  112   b  shown in  FIG. 16  are different, and M 3  of pixel  112   a &gt;M 3  of pixel  112   b  holds.  FIG. 20  shows only a period during which the reference voltage VRMP is linearly dropped. A change in I_VL 1  is (case1) or (case2) shown in  FIG. 20  due to the magnitude relation between the signals of the pixels  112   a  and  112   b  (that is, the magnitude relation between the voltages Vfd 1  and Vfd 2 ). 
     (Case1) is a case in which Vfd 1 &lt;Vfd 2 . The reference voltage VRMP starts linearly dropping. First, at time t 1  at which VRMP&lt;Vfd 2 , in the pixel  112   b  shown in  FIG. 16 , M 1  is turned on, M 2  is turned off, and I_VL 1  reduces by the magnitude of the current source M 3  of the pixel  112   b . Since M 3  of pixel  112   a &gt;M 3  of pixel  112   b , the reduction amount of the electric current is relatively small. Subsequently, at time t 2  at which VRMP&lt;Vfd 1 , in the pixel  112   a  shown in  FIG. 16 , M 1  is turned on, M 2  is turned off, and I_VL 1  reduces by the magnitude of the current source M 3  of the pixel  112   a . Since M 3  of pixel  112   a &gt;M 3  of pixel  112   b , the reduction amount of the electric current is relatively large. 
     (Case2) is a case in which Vfd 1 &gt;Vfd 2 . The reference voltage VRMP starts linearly dropping. First, at time t 3  at which VRMP&lt;Vfd 1 , in the pixel  112   a  shown in  FIG. 16 , M 1  is turned on, M 2  is turned off, and I_VL 1  reduces by the magnitude of M 3  of the pixel  112   a . Since M 3  of pixel  112   a &gt;M 3  of pixel  112   b , the reduction amount of the electric current is relatively large. Subsequently, at time t 4  at which VRMP&lt;Vfd 2 , in the pixel  112   b  shown in  FIG. 16 , M 1  is turned on, M 2  is turned off, and I_VL 1  reduces by the magnitude of the current source M 3  of the pixel  112   b . Since M 3  of pixel  112   a &gt;M 3  of pixel  112   b , the reduction amount of the electric current is relatively small. 
     By detecting the current change by the three thresholds (thresholds  1 ,  2 , and  3 ) exemplified in  FIG. 20 , whether fd 1  or fd 2  is determined can be detected. That is, in (case1), it is possible to determine that time t 1  (count 1 ) corresponds to fd 2  of the pixel  112   b , and time t 2  (count 2 ) corresponds to fd 1  of the pixel  112   a . In (case2), it is possible to determine that time t 3  (count 3 ) corresponds to fd 1  of the pixel  112   a , and time t 4  (count 4 ) corresponds to fd 2  of the pixel  112   b . Accordingly, it is possible to individually obtain the A/D-converted values of two pixels in one A/D period. 
       FIG. 21  shows the second application example as an application example of the fourth embodiment shown in  FIG. 11 . In the second application example, one signal obtained from a plurality of pixels  112   a ,  112   b ,  112   c , and  112   d  belonging to different rows (for example, a signal obtained by averaging signals of a plurality of pixels) is read out. Referring to  FIG. 21 , M 1  and M 2  form one differential signal pair, and M 4  and M 5  form one differential signal pair. The drains of M 1  and M 4  are connected to the vertical signal line  114   b , and the drains of the M 2  and M 5  are connected to the vertical signal line  114   a . Current sources M 3  and M 6  are simultaneously activated. 
     The operation of the second application example will be explained with reference to  FIG. 22 . In a first period (1H), φS 1  and φR 2  are controlled to High, φS 2  is controlled to Low. Accordingly, the reference voltage VRMP is supplied to M 2  and M 5 , and signals of fd 1  and fd 3  are simultaneously read out. Subsequently, in a second period (1H), in a second period (1H), φS 2  and φR 1  are controlled to High, and φS 1  is controlled to Low. Accordingly, the reference voltage VRMP is supplied to M 1  and M 4 , and signals of fd 2  and fd 4  are simultaneously read out. 
       FIG. 23  shows the third application example as another application example of the fourth embodiment shown in  FIG. 11 . In the arrangements shown in  FIGS. 16 and 21 , signals of pixels adjacent to each other in the vertical direction are simultaneously processed. In the third application example, a plurality of vertical signal lines are connected via switches HASW, and signals of pixels adjacent to each other in the horizontal direction are simultaneously processed. 
       FIG. 24  shows the arrangement of an image sensing system of one embodiment of the present invention. An image sensing system  800  includes an optical unit  810 , image sensing element  100 , image signal processing unit  830 , record/communication unit  840 , timing control unit  850 , system control unit  860 , and playback/display unit  870 . An image sensing unit  820  includes the image sensing element  100  and image signal processing unit  830 . The image sensing element  100  is a solid-state image sensor represented by the solid-state image sensors  1  and  1 ′ explained in the above-mentioned embodiments. 
     The optical unit  810  as an optical system such as a lens images light from an object on an image sensing unit  110  of the image sensing element  100 , in which a plurality of pixels are two-dimensionally arranged, thereby forming an image of the object. The image sensing element  100  outputs a signal corresponding to the light imaged on the image sensing unit  110 , at a timing based on a signal from the timing control unit  850 . The output signal from the image sensing element  100  is input to the image signal processing unit  830  as an image signal processor, and the image signal processing unit  830  performs signal processing in accordance with a method determined by a program or the like. The signal obtained by the processing in the image signal processing unit  830  is transmitted as image data to the record/communication unit  840 . The record/communication unit  840  transmits a signal for forming an image to the playback/display unit  870 , and causes the playback/display unit  870  to playback/display a moving image or still image. When receiving the signal from the image signal processing unit  830 , the record/communication unit  840  communicates with the system control unit  860 , and also records a signal for forming an image on a recording medium (not shown). 
     The system control unit  860  comprehensively controls the operation of the image sensing system, and controls the driving of the optical unit  810 , timing control unit  850 , record/communication unit  840 , and playback/display unit  870 . Also, the system control unit  860  includes a storage device (not shown) such as a recording medium, and records, for example, programs necessary to control the operation of the image sensing system in the storage device. Furthermore, the system control unit  860  supplies, for example, a signal for switching driving modes in accordance with a user&#39;s operation to the image sensing system. Practical examples are a change of a read target row or reset target row, a change of the angle of view caused by electronic zooming, and a shift of the angle of view caused by electronic vibration isolation. The timing control unit  850  controls the driving timings of the image sensing element  100  and image signal processing unit  830  under the control of the system control unit  860 . 
     While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions. 
     This application claims the benefit of Japanese Patent Application No. 2014-066812, filed Mar. 27, 2014, and Japanese Patent Application No. 2014-265780, filed Dec. 26, 2014, which are hereby incorporated by reference herein in their entirety.