Patent Publication Number: US-2023152830-A1

Title: Device design for short-circuit protection of transistors

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application claims priority under 35 U.S.C. § 120 as a continuation of U.S. patent application Ser. No. 16/448,538, filed Jun. 21, 2019, the entire content of which is incorporated herein by reference as if set forth fully herein. 
    
    
     FIELD 
     The present disclosure is related to transistor semiconductor die, and in particular to transistor semiconductor die with improved protection against short circuit events. 
     BACKGROUND 
     Transistor devices such as metal-oxide semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), junction field-effect transistors (JFETs), and bipolar junction transistors (BJTs) are often used in power electronics, in which they may be used to selectively deliver current to and from a load. In certain situations, a load may provide a short circuit across a transistor device. Such a short circuit event may cause the transistor device to fail. 
     In recent years, there has been a push towards using wide bandgap semiconductor material systems for devices used in power electronics. For example, silicon carbide transistors are now in widespread use in power electronics. Compared to their silicon counterparts, silicon carbide transistors provide better performance, for example, by providing higher blocking voltage, lower on-state resistance, and lower switching loss. Silicon carbide transistors are also much smaller in size, and thus have higher current density. Accordingly, the short circuit withstand time, or the amount of time that a device can survive without failure during a short circuit event, of a silicon carbide transistor is much lower than that of a similar silicon device. 
     In light of the above, there is a present need for silicon carbide transistor devices with improved short circuit protection. 
     SUMMARY 
     In one embodiment, a transistor semiconductor die includes a first current terminal, a second current terminal, and a control terminal. A semiconductor structure is between the first current terminal, the second current terminal, and the control terminal and configured such that a resistance between the first current terminal and the second current terminal is based on a control signal provided at the control terminal. Short circuit protection circuitry is coupled between the control terminal and the second current terminal. In a normal mode of operation, the short circuit protection circuitry is configured to provide a voltage drop between the control terminal and the second current terminal that is greater than a voltage of the control signal. In a short circuit protection mode of operation, the short circuit protection circuitry is configured to provide a voltage drop between the control terminal and the second current terminal that is less than a voltage of the control signal. Accordingly, the short circuit protection circuit is configured to protect the transistor semiconductor die from failure due to a short circuit condition while not interfering with the operation of the transistor semiconductor die in a normal mode of operation. 
     Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
         FIG.  1    is a schematic representation of a transistor semiconductor die according to one embodiment of the present disclosure. 
         FIG.  2    is a schematic representation of a transistor semiconductor die according to one embodiment of the present disclosure. 
         FIG.  3    is a graph illustrating a relationship between drain-source voltage, drain-source current, and gate-source voltage for a metal-oxide semiconductor field-effect transistor (MOSFET) according to one embodiment of the present disclosure. 
         FIG.  4    is a cross-sectional view of a portion of a transistor semiconductor die according to one embodiment of the present disclosure. 
         FIG.  5    is a cross-sectional view of a portion of a transistor semiconductor die according to one embodiment of the present disclosure. 
         FIG.  6    is a schematic representation of a transistor semiconductor die according to one embodiment of the present disclosure. 
         FIG.  7    is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure. 
         FIG.  8    is a schematic representation of a transistor semiconductor die according to one embodiment of the present disclosure. 
         FIG.  9    is a schematic representation of a transistor semiconductor die according to one embodiment of the present disclosure. 
         FIG.  10    is a schematic representation of a transistor semiconductor die according to one embodiment of the present disclosure. 
         FIG.  11    is a schematic representation of a transistor semiconductor die according to one embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
     Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
       FIG.  1    shows a schematic representation of a transistor semiconductor die  10  according to one embodiment of the present disclosure. The transistor semiconductor die  10  includes a first current terminal  12 , a second current terminal  14 , and a control terminal  16 . A semiconductor structure between the first current terminal  12 , the second current terminal  14 , and the control terminal  16  forms a transistor device Q ig  such that a resistance between the first current terminal  12  and the second current terminal  14  is based on a control signal CNT provided at the control terminal  16 . As shown in  FIG.  1   , the transistor device Q ig  is a metal-oxide semiconductor field-effect transistor (MOSFET). Accordingly, the first current terminal  12  is a drain terminal, the second current terminal  14  is a source terminal, and the control terminal  16  is a gate terminal. However, the principles of the present disclosure apply equally to any transistor device such as an insulated gate bipolar transistor (IGBT). In the case of an IGBT, the first current terminal  12  is a collector terminal, the second current terminal  14  is an emitter terminal, and the control terminal  16  is a gate terminal. Since the transistor device Q ig  may be used for power electronics, a freewheeling anti-parallel diode D fw  may be coupled in anti-parallel with the transistor device Q ig  so that current can be conducted bidirectionally between the first current terminal  12  and the second current terminal  14 . In various embodiments, the freewheeling diode D fw  may be external from the transistor device Q ig , or may be internal to the transistor device Q ig , e.g., a body diode. 
     While the transistor device Q ig  is shown herein as an insulated gate device, the principles of the present disclosure apply equally to any transistor device such as bipolar junction transistors (BJTs), and junction field-effect transistors (JFETs). In the case of a BJT, the first current terminal  12  is a collector terminal, the second current terminal  14  is an emitter terminal, and the control terminal  16  is a base terminal. In the case of a JFET, the first current terminal  12  is a drain terminal, the second current terminal  14  is a source terminal, and the control terminal  16  is a gate terminal. Further, the transistor device Q ig  may be a thyristor. In the case of a thyristor, the first current terminal  12  is an anode, the second current terminal  14  is a cathode, and the control terminal  16  is a gate terminal. 
     The transistor semiconductor die  10  may utilize a wide bandgap material system such as silicon carbide. As discussed above, the silicon carbide transistor semiconductor die  10  may be more sensitive to short circuit events than their silicon counterparts due to the smaller size and higher current density thereof. Accordingly, short circuit protection circuitry  18  is coupled between the control terminal  16  and the second current terminal  14 . The short circuit protection circuitry  18  is configured to operate in a normal mode of operation and a short circuit protection mode of operation. In the normal mode of operation, the short circuit protection circuitry  18  is configured to provide a voltage drop between the control terminal  16  and the second current terminal  14  that is greater than a voltage of the control signal CNT. In the short circuit protection mode of operation, the short circuit protection circuitry  18  is configured to provide a voltage drop between the control terminal  16  and the second current terminal  14  that is less than a voltage of the control signal CNT. In the normal mode of operation when a voltage drop across the short circuit protection circuitry  18  is greater than a voltage of the control signal CNT, the operation of the transistor device Q ig  is relatively unaffected. In the short circuit protection mode of operation when a voltage drop across the short circuit protection circuitry  18  is less than a voltage of the control signal CNT, a voltage at the control terminal  16  is lowered such that voltage between the control terminal  16  and the second current terminal  14  (i.e., the gate-to-source voltage of the transistor device Q ig ) is reduced, which in turn partially or completely shuts off the device. Shutting off the transistor device Q ig  protects the device during a short circuit event in order to prevent a failure. 
     One way in which the above-mentioned functionality may be accomplished is by providing the short circuit protection circuitry  18  such that it has a negative temperature coefficient with respect to a voltage drop across the short circuit protection circuitry  18 . In other words, the short circuit protection circuitry  18  may be provided such that a voltage drop across the short circuit protection circuitry  18  decreases as temperature increases. Since during a short circuit event a temperature of the transistor semiconductor die  10  will rapidly increase far above normal operating temperatures thereof, the short circuit protection circuitry  18  may significantly reduce a voltage drop between the control terminal  16  and the second current terminal  14  only when a short circuit event occurs. Note that this functionality requires adequate thermal coupling between the short circuit protection circuitry  18  and the current carrying portion of the transistor semiconductor die  10 . 
     Notably, the short circuit protection circuitry  18  is located on the transistor semiconductor die  10 . As discussed in detail below, the short circuit protection circuitry  18  takes up minimal area on the transistor semiconductor die  10  and may be capable of extending a short circuit withstand time of the transistor semiconductor die  10  significantly, and in some cases indefinitely. 
       FIG.  2    is a schematic representation of the transistor semiconductor die  10  showing details of the short circuit protection circuitry  18  according to one embodiment of the present disclosure. As shown in  FIG.  2   , the short circuit protection circuitry  18  may include a number of short circuit protection diodes D sc  coupled in series between the control terminal  16  and the second current terminal  14 . In particular, the short circuit protection diodes D sc  are coupled anode-to-cathode between the control terminal  16  and the second current terminal  14  such that an anode of a first one of the short circuit protection diodes D sc  is coupled to the control terminal  16  and a cathode of a last one of the short circuit protection diodes D sc  is coupled to the second current terminal  14 . As discussed above, the short circuit protection diodes D sc  may be provided with a negative temperature coefficient (e.g., an exponential negative temperature coefficient) with respect to a forward voltage drop thereof. In other words, the short circuit protection diodes D sc  may be provided such that a forward voltage drop across the diodes decreases as temperature increases. Such a negative temperature coefficient is naturally present in silicon carbide diodes. The negative temperature coefficient enables a voltage drop across the short circuit protection diodes D sc  to be greater than a voltage of the control signal CNT in the normal mode of operation (and thus not interfere with the operation of the transistor device Q ig ) and be less than a voltage of the control signal CNT in the short circuit protection mode of operation (thus partially or completely turning off the transistor device Q ig ). Note that this functionality requires adequate thermal coupling between the short circuit protection circuitry  18  and the current carrying portion of the transistor semiconductor die  10 . The number of short circuit protection diodes D sc  may be chosen such that when a temperature of the transistor semiconductor die  10  is below a short circuit threshold temperature a voltage drop across the short circuit protection diodes D sc  is greater than or equal to a voltage of the control signal CNT and when a temperature of the transistor semiconductor die  10  is above the short circuit threshold temperature a voltage drop across the short circuit protection diodes D sc  is significantly less than the voltage of the control signal CNT such that a voltage at the control terminal  16  is lowered enough to partially or completely turn off the transistor device Q ig . 
     In addition to protecting the transistor device Q ig  against short circuit events, the short circuit protection circuitry  18  also clamps the maximum voltage of the gate to the combined forward voltage drop of the short circuit protection diodes D sc . This has the additional benefits of protecting the transistor device Q ig  against electrostatic discharge (ESD) and provides voltage overshoot protection for the gate of the transistor device Q ig . 
     The short circuit protection circuitry  18  may enable significant improvements in the short circuit withstand time of the transistor semiconductor die  10 . As discussed herein, the short circuit protection circuitry  18  may require minimal active area on the transistor semiconductor die  10 . In various embodiments, an on-state resistance of the transistor semiconductor die  10  may be between 0.1 mΩ/cm 2  and 3.0 mΩ/cm 2 , a blocking voltage of the transistor semiconductor die  10  may be between 600V and 10 kV, and a short circuit withstand time of the transistor semiconductor die  10  may be greater than 3 μs. Notably, the on-state resistance of the transistor semiconductor die  10  may fall anywhere in the above range, such as between 0.5 mΩ/cm 2  and 3.0 mΩ/cm 2 , between 1.0 mΩ/cm 2  and 3.0 mΩ/cm 2 , between 1.5 mΩ/cm 2  and 3.0 mΩ/cm 2 , between 2.0 mΩ/cm 2  and 3.0 mΩ/cm 2 , between 2.5 mΩ/cm 2  and 3.0 mΩ/cm 2 , and the like. The blocking voltage of the transistor semiconductor die  10  may similarly fall anywhere inside the above range, such as between 600V and 1 kV, between 600V and 2 kV, between 600V and 5 kV, between 1 kV and 5 kV, between 5 kV and 10 kV, and the like. A relationship between the on-state resistance and the blocking voltage of the transistor semiconductor die  10  may be expressed according to Equation (1): 
         R   on =0.8×(3×10 −8 )× V   block   2.4    (1)
 
     where R on  is the on-state resistance of the transistor semiconductor die and V block is the blocking voltage of the transistor semiconductor die  10 . 
     The short circuit withstand time of the transistor semiconductor die  10  may be less than 10 s in some embodiments, but the principles of the present disclosure may also enable the transistor semiconductor die  10  to indefinitely withstand a short circuit event in some circumstances. The short circuit withstand time of the transistor semiconductor die  10  may fall anywhere in the above ranges such that the short circuit withstand time is between 4 μs and 10 s, between 5 μs and 10 s, between 10 μs and 10 s, between 50 μs and 10 s, between 5 ms and 10 s, between 10 ms and 10 s, between 50 ms and 10 s, between is and 10 s, and the like. 
       FIG.  3    is a graph illustrating a relationship between drain-source voltage, drain-source current, and gate-source voltage in a MOSFET. As shown, a relationship between drain-source voltage and drain-source current is dependent on gate-source voltage such that as the gate-source voltage increases, a steepness of the curve between drain-source voltage and drain-source current increases. Accordingly, higher gate-source voltages will lead to higher drain-source currents during a short circuit event. When a drain-source current becomes high enough, the device will fail. By reducing the gate-source voltage during a short circuit event, the drain-source current is significantly reduced such that a failure of the device can be prevented. 
       FIG.  4    is a cross-sectional view of a portion of the transistor semiconductor die  10  according to one embodiment of the present disclosure. The transistor semiconductor die  10  includes a substrate  20 , a drift layer  22  on the substrate  20 , a number of implants  24  in the drift layer  22 , a top metallization layer  26 , and a bottom metallization layer  28 . In particular, on the right side of the transistor semiconductor die  10  the transistor device Q ig  is provided as a vertical MOSFET including a pair of junction implants  30  in the drift layer  22  such that the junction implants  30  are separated by a JFET gap  32 . A gate contact  34  on top of a gate oxide layer  36  runs between the junction implants  30  on a surface of the drift layer  22  opposite the substrate  20 . A source contact  38  (which may also be the second current terminal  14 ) also contacts each one of the junction implants  30  on the surface of the drift layer  22  opposite the substrate. A drain contact  40  (which may also be the first current terminal  12 ) is on the substrate  20  opposite the drift layer  22 . The source contact  38  is provided by a portion of the top metallization layer  26 . The drain contact  40  is provided by the bottom metallization layer  28 . 
     On the left side of the transistor semiconductor die  10 , the control terminal  16  is provided by a portion of the top metallization layer  26 . While not shown, the control terminal  16  is coupled to the gate contact  34  of the transistor device Q ig  on a plane not shown in the cross-section (e.g., via a gate runner  42  provided on a field oxide layer  44  below the top metallization layer  26 ). The control terminal  16  is also coupled to the source contact  38  of the transistor device Q ig  through a number of P-N junctions  46  formed in the drift layer  22 . Each one of these P-N junctions  46  forms one of the short circuit protection diodes D sc  discussed above with respect to  FIG.  2   . The top metallization layer  26  is appropriately patterned to form connections between the control terminal  16  and the source contact  38  through the P-N junctions  46  as shown. An intermetal dielectric layer  48  may insulate different portions of the top metallization layer  26  to form the desired connection pattern. 
     While only one unit cell of the transistor device Q ig  is shown in  FIG.  4   , the transistor device Q ig  may comprise any number of cells coupled together to provide a desired forward current rating of the transistor semiconductor die  10 . Further, while the short circuit protection diodes D sc  are shown one next to another in the drift layer  22  in  FIG.  4   , the short circuit protection diodes D sc  may be distributed in any suitable manner in the transistor semiconductor die  10 . For example, the short circuit protection diodes D sc  may be distributed between different cells of the transistor device Q ig  in a pattern in order to reduce the total active area devoted to the short circuit protection diodes D sc . In general, the short circuit protection diodes D sc  will consume very little area when compared to the transistor device Q ig  and thus will have a minimal impact on the total active area of the transistor semiconductor die  10 . 
       FIG.  5    shows the transistor semiconductor die  10  according to an additional embodiment of the present disclosure. The transistor semiconductor die  10  shown in  FIG.  5    is substantially similar to that shown in  FIG.  4   , except that the short circuit protection diodes D sc  are provided as a number of P-N junctions  50  formed in an additional semiconductor layer  52  (e.g., a polysilicon layer) that is provided on the drift layer  22  (with the field oxide layer  44  between the additional semiconductor layer  52  and the drift layer  22  to avoid interaction between the layers). A number of metal jumpers  53  may be provided between each adjacent P-N junction  50 . In the embodiment shown in  FIG.  5    the short circuit protection diodes D sc  may be Zener diodes. In such an embodiment, the short circuit protection diodes D sc  are coupled in series cathode-to-anode between the insulted gate terminal  16  and the second current terminal  14  such that a cathode of a first one of the short circuit protection diodes D sc  is coupled to the control terminal  16  and an anode of a last one of the short circuit protection diodes D sc  is coupled to the second current terminal  14 . However, the P-N junctions  50  in  FIG.  5    may be reversed such that they are coupled anode-to-cathode between the insulated gate terminal  16  and the second current terminal  14  as shown. Providing the short circuit protection diodes D sc  in the additional semiconductor layer  52  that is provided on the drift layer  22  may allow a reduction or elimination of the active area devoted to the short circuit protection circuitry  18 , since the short circuit protection diodes D sc  can be moved over the transistor device Q ig  in some embodiments. 
       FIG.  6    is a schematic representation of the transistor semiconductor die  10  according to an additional embodiment of the present disclosure. The transistor semiconductor die  10  shown in  FIG.  6    is substantially similar to that shown in  FIG.  2   , except that the short circuit protection circuitry  18  further includes a short circuit protection resistive element R sc  coupled in series with the short circuit protection diodes D sc . The short circuit protection resistive element R sc  may be used to achieve a precise voltage drop across the short circuit protection circuitry  18  that may be difficult to achieve using diodes alone. Since using only diodes in the short circuit protection circuitry  18  effectively limits the total voltage drop across the short circuit protection circuitry  18  to integer multiples of the forward voltage drop of the diodes, providing the short circuit protection resistive element R sc  allows for more precise tuning of the voltage drop across the short circuit protection circuitry  18 . The short circuit protection circuitry  18  may be provided with a negative temperature coefficient with respect to the resistance thereof, such that as the temperature of the transistor semiconductor die  10  increases, the resistance of the short circuit protection resistive element R sc  decreases. 
       FIG.  7    is a cross-sectional view of a portion of the transistor semiconductor die  10  according to an additional embodiment of the present disclosure. The transistor semiconductor die  10  shown in  FIG.  7    is substantially similar to that shown in  FIG.  4   , except that the transistor semiconductor die  10  further includes the short circuit protection resistive element R sc  coupled between the control terminal  16  and the second current terminal  14 . The short circuit protection resistive element R sc  may be implemented using a deep N-doped well  54 . Providing the short circuit protection resistive element R sc  in this manner may ensure a negative temperature coefficient with respect to resistance. While not shown, in other embodiments, the short circuit protection resistive element R sc  may be implemented using a highly doped polysilicon resistor, a metal resistor with sufficiently high positive temperature coefficient with respect to resistance, or any other suitable type of resistive element. 
       FIG.  8    is a schematic representation of the transistor semiconductor die  10  according to an additional embodiment of the present disclosure. The transistor semiconductor die  10  shown in  FIG.  8    is substantially similar to that shown in  FIG.  1   , except that the transistor semiconductor die  10  further includes a gate resistive element R g  coupled between the control terminal  16  and a gate of the transistor device Q ig . The gate resistive element R g  is provided with a positive temperature coefficient with respect to a resistance thereof In other words, a resistance of the gate resistive element R g  increases as a temperature of the transistor semiconductor die  10  increases. Note that this functionality requires adequate thermal coupling between the short circuit protection circuitry  18  and the current carrying portion of the transistor semiconductor die  10 . This may reduce a gate drive current in the event of a short circuit event, thereby enhancing the action of the short circuit protection circuitry  18 . 
     As discussed above, while the foregoing examples of transistor semiconductor die  10  are primarily shown depicting the transistor device Q ig  as a MOSFET, the principles of the present disclosure apply equally to any type of transistor devices including IGBTs, BJTs, JFETs, and the like. Accordingly, for the sake of completeness  FIG.  9    shows a schematic view of the transistor semiconductor die  10  wherein the transistor device Q ig  is an IGBT instead of a MOSFET. In this case, the first current terminal  12  is a collector terminal and the second current terminal  14  is an emitter terminal. Those skilled in the art will readily appreciate that the MOSFET depicted in the cross-sectional views of the transistor semiconductor die  10  shown above can be readily replaced with an IGBT, for example, by adding an injector layer between the substrate  20  and the drift layer  22 .  FIG.  10    shows a schematic view of the transistor semiconductor die  10  wherein the transistor device Q ig  is a BJT instead of a MOSFET. In this case, the first current terminal  12  is a collector terminal, the second current terminal  14  is an emitter terminal, and the control terminal  14  is a base terminal. Those skilled in the art will readily appreciate that the MOSFET depicted in the cross-sectional views of the transistor semiconductor die  10  shown above can be readily replaced with a BJT.  FIG.  11    shows a schematic view the transistor semiconductor die  10  wherein the transistor device Q ig  is a JFET instead of a MOSFET. In this case, the first current terminal  12  is a drain terminal, the second current terminal  14  is a source terminal, and the control terminal  16  is a gate terminal. Those skilled in the art will readily appreciate that the MOSFET depicted in the cross-sectional views of the transistor semiconductor die  10  shown above can be readily replaced with a JFET. 
     Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.