Patent Publication Number: US-11658646-B2

Title: Electronic circuit for tripling frequency

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 17/025,288, entitled “ELECTRONIC CIRCUIT FOR TRIPLING FREQUENCY,” and filed on Sep. 18, 2020, which claims the benefit of Italian Patent Application No. 102019000016871, filed on Sep. 20, 2019, which applications are hereby incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The present invention relates to an electronic circuit, and in particular embodiment, to an electronic circuit for tripling frequency. 
     BACKGROUND 
     As is known, communications at millimeter-wave (mm-wave) range have drawn a lot of attention in recent years due to the wide available bandwidth yielding higher data transmission capacity. Thus, current systems use transceivers that convert the exchanged signals from the base frequency to the selected communication frequency and vice versa. To this end, the transceivers use circuitry to generate a local oscillation (LO). Design of the local oscillation transceivers is critical because many conflicting parameters, i.e., tuning range, phase noise, output power and level of spurious tones, affect the performances. Differently from what is commonly pursued at other radio frequencies, local oscillation generation with a PLL (Phase Locked Loop) circuit comprising a VCO (Voltage Controlled Oscillator) at the desired output frequency is not viable at mm-wave range. In fact, the severe impact of parasitic structures and effects in silicon technology and the low quality factor of passive components (mostly, variable capacitors) impair the achievable tuning range and phase noise. Moreover, traditional frequency dividers in the PLL cause excessive power consumption. 
     A more promising approach consists in providing a PLL in a lower range (e.g., in the 10-20 GHz range), where the silicon VCO features the best figure of merit, followed by a frequency multiplier chain. 
     For example,  FIG.  1    shows a typical frequency multiplier system  1  for obtaining a multiplication by 6, for example, for obtaining a 60 GHz voltage from a 10 GHz source. Here, a low-frequency voltage generator  2  supplies an input voltage Vin at a base frequency f o , e.g., at 10 GHz, to a frequency tripler  3 , which generates an intermediate voltage V 1  at a triple frequency (3f o ). The intermediate voltage V 1  is available at a first output O 1  through a first buffer  4  and fed to a frequency doubler  5  that generates an output voltage Vo at output frequency 6f o . The output voltage Vo is made available at a second output O 2  through a second buffer  6 . 
     The frequency multiplier system  1  has to provide a good suppression of the driving signal and of undesired harmonics in order not to impair the transceiver performance. In particular, in the frequency multiplier system  1 , it is desired that the first stage (frequency tripler  3 ) features the highest suppression, because its spurious tones are shifted close to the final LO frequencies by the intermodulation of the cascaded stages. Moreover, this issue is more critical for odd-order multipliers, because even-order multipliers (here, the frequency doubler  5 ) may exploit push-push transistors for suppression of signal components at undesired frequencies. 
     Odd-order multipliers, such as the frequency tripler  3  of the frequency multiplier system  1 , typically comprise a transistor with low conduction angle (e.g., class-C biased transistor) that generates a harmonic-rich current and the desired component is selected with a band-pass filter or an injection-locked oscillator. 
     For example,  FIG.  2    shows the basic structure of a class-C tripler circuit, indicated by  10 . The class-C tripler circuit  10  comprises a transistor  11 , here of bipolar type, fed at a base terminal B by the input voltage
 
 V in= A  sin(2π f   o   t )
 
through an input capacitor  12  and coupled to a bias voltage Vb through a resistor  13 . The transistor  11  has an emitter terminal E grounded, and a collector terminal C coupled to an output terminal  14  and to a supply voltage VCC through an LC resonant circuit  15  tuned at 3f o .
 
     In a per se known manner, the class-C tripler circuit  10  conducts a current Io whose harmonic content is set by the conduction angle θ determined by the bias voltage Vb and shown in the simulations of  FIGS.  3 A and  3 B . 
     In detail,  FIG.  3 A  shows the plot of the output current density Jo (output current Io normalized to the area A of the transistor  11 ) for the fundamental (If o ), the third harmonic (I3f o ) and the fifth harmonic (I5f o ).  FIG.  3 B  shows the plot of the ratio If o /I3f o (=Jf o /J3f o ) of the amplitudes of the normalized fundamental Jf o  and the normalized third harmonic (J3f o ) as a function of the conduction angle θ. 
     As may be seen in  FIG.  3 A , the total harmonic rejection ratio HRR is dominated by the fundamental Jf o , i.e., the leakage of the driving signal, which is always larger than the normalized third harmonic J3f o . At conduction angle θ≈150°, the amplitude of normalized third harmonic J3f o  is maximized (point M in  FIG.  3 A ), but the fundamental Jf o  is still 9 dB larger than the third harmonic J3f o  (as also visible in  FIG.  3 B ). Even dimensioning the LC resonant circuit  15  to maximize suppression while compromising bandwidth, the class-C tripler circuit  10  has a very poor suppression, that cannot be increased over 20 dB. 
     Class-C tripler circuits may be improved, in principle, by using a more complex filter topology or by cascading multiple filtering stages, but at the cost of a high design complexity, big area, bandwidth limitation and higher consumption. 
     Also the injection-locked oscillator solution (see, e.g., N. Mazor et al., “A high suppression frequency tripler for 60-GHz transceivers,” in 2015 IEEE MIT-S International Microwave Symposium, 2015, pp. 1-4), although providing a better suppression (up to about 30 dB), does not satisfactorily solve the problem. 
     SUMMARY 
     Some embodiments provide a frequency tripler that improves the suppression of the driving signal frequency at the output. 
     Some embodiments relate to tripling frequency, in particular for radiofrequency applications in the millimeter-wave range. 
     Some embodiments relate to an electronic circuit for tripling frequency. Some embodiments related to a corresponding method. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For the understanding of the present invention, embodiments thereof are now described, purely as a non-limitative example, with reference to the drawings, wherein: 
         FIG.  1    shows a block diagram of the general structure of a frequency multiplier chain; 
         FIG.  2    is a circuit diagram of a known frequency multiplier; 
         FIGS.  3 A and  3 B  are plots of quantities related to the circuit of  FIG.  2   ; 
         FIG.  4    is a circuit diagram of a frequency tripler, according to an embodiment of the present invention; 
         FIG.  5    shows the plot of a desired trans-characteristic and the actual characteristic of the circuit of  FIG.  4   , according to an embodiment of the present invention; 
         FIG.  6    is a circuit diagram of a tripler device including the circuit of  FIG.  4   , according to an embodiment of the present invention; 
         FIG.  7    is a circuit diagram of an embodiment of a block of the tripler device of  FIG.  6   ; 
         FIG.  8    shows plots of quantities related to the circuit of  FIG.  4   , according to an embodiment of the present invention; and 
         FIG.  9    shows comparative plots of the power spectrum obtained with the circuit of  FIG.  4    and the circuit of  FIG.  1   . 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
       FIG.  4    shows a tripler circuit  20  that allows obtaining a high suppression of undesired harmonics, according to an embodiment of the present invention. 
     The tripler circuit  20  represents an implementation of an ideal transistor-based tripler circuit having a polynomial trans-characteristic f(V in ) (later on also called ideal polynomial trans-characteristic) according to the following equation (1): 
                     f   ⁡     (     V     i   ⁢   n       )       =       (         3   A     ⁢     V     i   ⁢   n         -       4     A   3       ⁢     V     i   ⁢   n     3         )     ⁢     g   m               (   1   )               
where g m  is the transconductance of the transistor in the tripler circuit (at a specific DC biasing condition).
 
     In particular, as may be demonstrated with some calculation, the above ideal trans-characteristics allows a tripler circuit, receiving at its input a sinusoidal driving voltage:
 
 V   in   =A  sin(2π f   0   t )= A  sin(ω 0   t )
 
having amplitude A and base frequency f o  is able to generate an output current Io:
 
 I   o   =f ( V   in )= g   m  sin(32π f   0   t )= g   m  sin(3ω 0   t )
 
having only the third harmonic (3f o ).
 
       FIG.  4    shows the structure of the tripler circuit  20  that has a trans-characteristics approximating the above polynomial trans-characteristics f(V in ), as discussed later on. 
     In detail, with reference to  FIG.  4   , the tripler circuit  20  comprises a first and a second pair of transistors, cross-coupled to each other. In particular, the first pair of transistors comprises a first and a second transistor Q 1 , Q 2 , here of the bipolar NPN-type, and the second pair of transistors comprises a third and a fourth transistor Q 3 , Q 4 , here also of the bipolar NPN-type. Transistors Q 1 -Q 4  have same parameters, in particular same emitter area. 
     In detail, the first and second transistors Q 1 , Q 2  have emitter terminals coupled to each other and to a common node  21 , base terminals coupled to a first and, respectively, a second input node  22 ,  23  and collector terminals coupled to a first and, respectively, a second output node  24 ,  25  supplying a first and, respectively, a second single-ended current Io− and Io+. 
     The third and fourth transistor Q 3 , Q 4  have emitter terminals coupled to each other and to the common node  21 , base terminals coupled to a third and, respectively, a fourth input node  27 ,  28 , and collector terminals coupled to the second and, respectively, the first output node  25 ,  24 . 
     A biasing current source  26 , configured to generate bias current I b , is coupled between the common node  21  and ground. 
     The first and the second input nodes  22 ,  23  receive each a fraction equal to ½ of the input voltage V in , in counter-phase, both reduced by a DC voltage (offset voltage V os ). The third and the fourth input nodes  27 ,  28  receive each an attenuation α/2 of the input voltage, in counter-phase, the attenuation α being selected so that, during operation, at low values of the input voltage V in  and considering also the offset voltage V os , the first pair of transistors Q 1 , Q 2  is still off, while the second pair of transistors Q 3 , Q 4  are on, as discussed in detail below. 
     Specifically, the first input node  22  receives first voltage V 1 :
 
 V 1= V   in /2− V   os ;
         the second input node  23  receives voltage V 2 :
 
 V 2=− V   in /2− V   os ;
   the third input node  27  receives voltage V 3 :
 
 V 3=α Vin /2; and
   the fourth input node  28  receives voltage V 4 :
 
 V 4=−α V   in /2
 
where V os  is the DC offset voltage and α is the attenuation, as indicated above.
       

     The tripler circuit  20  of  FIG.  4    operates as follows. As indicated above, at small values of the input voltage V in , the first and second transistors Q 1 , Q 2  have low base-to-emitter biasing voltages and are off; thus the output currents I o+  and I o−  are governed only by the third and fourth transistors Q 3 , Q 4 , approximating equation (1). When the value of the input voltage V in  increases, the first and second transistors Q 1 , Q 2  turn on, subtracting current from the output nodes  24 ,  25 . In particular, after reaching their maximum amplitudes, the output differential current I o =I o+ −I o+  reduces, reversing the slope of the trans-characteristic. 
     The trans-characteristic of the tripler circuit  20  of  FIG.  4    is shown by curve A plotted in  FIG.  5    with dotted line as normalized output current I on  versus normalized input voltage V in /A. For reference,  FIG.  5    shows also the ideal trans-characteristic (1) with continuous line B. 
     In particular, the normalized output current I on  is the differential current I o+ −I o+ , normalized with respect to its maximum amplitude (equal to I b ). 
     The values of attenuation α and offset voltage V os  are selected so that the trans-characteristic of the tripler circuit  20  tracks the ideal polynomial trans-characteristic of equation (1), that is so that the trans-characteristic of the tripler circuit  20  is null at V in =0, then increases with a similar slope as the ideal polynomial trans-characteristic, then decreases again to zero and to negative values, following the ideal trans-characteristic. The opposite happens for negative values of V in . 
     In particular, the zero-crossings (besides of that at V in =0) of the trans-characteristic of the tripler circuit  20  occur when the voltage at the base terminal of the third transistor Q 3  (at the third input node  27 ) equals the voltage at the base terminal of the first transistor Q 1  (at the first input node  22 ) as well as when the voltage at the base terminal of the fourth transistor Q 4  (at the fourth input node  28 ) equals the voltage at the base terminal of the second transistor Q 2  (at the second input node  23 ), that is when condition (2) is satisfied: 
     
       
         
           
             
               
                 
                   
                     
                       
                         ± 
                         
                           
                             V 
                             
                               i 
                               ⁢ 
                               n 
                             
                           
                           2 
                         
                       
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                         V 
                         OS 
                       
                     
                     = 
                     
                       
                         ± 
                         α 
                       
                       ⁢ 
                       
                         
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                             i 
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                             n 
                           
                         
                         2 
                       
                     
                   
                   . 
                 
               
               
                 
                   ( 
                   2 
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     The zero-crossings occur thus at the following values of the input voltage V in : 
     
       
         
           
             
               
                 
                   
                     
                       V 
                       
                         i 
                         ⁢ 
                         n 
                       
                     
                     = 
                     
                       ± 
                       
                         
                           2 
                           ⁢ 
                           
                             V 
                             OS 
                           
                         
                         
                           ( 
                           
                             1 
                             - 
                             α 
                           
                           ) 
                         
                       
                     
                   
                   . 
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     On the other hand, the zero-crossings of the trans-characteristics (1) (besides of that at V in =0) occur at the following values of the input voltage V in : 
     
       
         
           
             
               
                 
                   
                     
                       V 
                       
                         i 
                         ⁢ 
                         n 
                       
                     
                     = 
                     
                       
                         ± 
                         
                           
                             3 
                           
                           2 
                         
                       
                       ⁢ 
                       A 
                     
                   
                   . 
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     It follows that the trans-characteristic of the tripler circuit  20  and the ideal trans-characteristic have same zero-crossings when attenuation α and offset voltage V os  satisfy the following condition: 
     
       
         
           
             
               
                 
                   
                     
                       
                         2 
                         ⁢ 
                         
                           V 
                           OS 
                         
                       
                       
                         ( 
                         
                           1 
                           - 
                           α 
                         
                         ) 
                       
                     
                     = 
                     
                       
                         
                           3 
                         
                         2 
                       
                       ⁢ 
                       A 
                     
                   
                   . 
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     Analysis of the derivatives of the ideal polynomial trans-characteristic (1) shows that its slope at the zero crossings at V in =±√{square root over (3)}A/2 is ±2 times that of the origin. Further circuit analysis proves that it is enough to design attenuation α=0.2 to have the slopes of the two trans-characteristics identical at zero crossings, such that the shape of the actual trans-characteristic of the tripler circuit  20  keeps as close as possible to the ideal one (see  FIG.  5   ). However, circuit analysis proves that a value of attenuation α comprised in the range 0.1 to 0.35 allows the trans-characteristic of the tripler circuit  20  to suitably fit the plot of the ideal polynomial trans-characteristic (1). In fact, the spread of the value of attenuation α may be compensated through the offset voltage V os , as discussed below. 
     By fixing the value of attenuation α, the value of the offset voltage V os  is obtained as a linear function of the amplitude A of the input voltage V in , based on condition (5). 
     In this case, also a non-optimal value of the attenuation α may be set, and the envelope detector operates as an open loop able to compensate and maintain the linear desired relationship of condition (5). 
     For example,  FIG.  6    shows a tripler circuit, indicated by  30 , comprising the tripler  20  of  FIG.  5    and an envelope detector, according to an embodiment of the present invention. 
     In  FIG.  6   , an input transformer T 1  has a primary winding  31  coupled between a first and a second circuit input  32 ,  33  and a secondary winding  35  coupled between the input nodes  22 ,  23  of the tripler circuit  20 . The secondary winding  35  has a central tap  36  connected to a first output  37  of an envelope detector  38  and set at a first biasing voltage Vb 1 . 
     A voltage divider  40 , of capacitive type, is coupled between the input nodes  22 ,  23  of the tripler circuit  20  and comprises a first branch  41  and a second branch  42 . 
     The first branch  41  of the voltage divider  40  comprises a first capacitor  45 , a first resistor  46 , a second resistor  47  and a second capacitor  48  connected in series. The first and second capacitors  45 ,  48  have same capacitance C 1 ; the first and second resistors  46 ,  47  have same resistance R. 
     The first branch  41  has a central tap between the first and second resistors  46 ,  47  coupled to a second output  50  of the envelope detector  38 , which generates a second biasing voltage Vb 2 . The first branch  41  also has a first intermediate node  51  between the first capacitor  45  and the first resistor  46  and a second intermediate node  52  between the second resistor  47  and the second capacitor  48 . The voltage difference Vb 2 -Vb 1  forms the offset voltage V os  of the tripler  20  of  FIG.  5   . 
     The second branch  42  of the voltage divider  40  comprises a third capacitor  54  coupled between the first and second intermediate nodes  51 ,  52 . The third capacitor  54  has a capacitance C 2 . First and second intermediate nodes  51 ,  52  are also coupled to the third and, respectively, the fourth input node  27 ,  28  of the tripler circuit  20 . 
     The first and second input nodes  22 ,  23  of the tripler circuit  20  are also coupled to a first, respectively a second input  55 ,  56  of the envelope detector  38  through respective capacitors  57 ,  58 . 
     The tripler circuit  30  also comprises an output transformer T 2  having a primary winding  61  coupled between the first and second output nods  24 ,  25  of the tripler  20  and a second winding  62  coupled between a first and second circuit outputs  64 ,  65 ; and an LC network  66  formed by a shunt capacitor  67  and a tail inductor  68  is coupled between the common node  21  of the tripler  20  and ground. 
     The first and second circuit outputs  64 ,  65  may be connected to an output buffer similar to the first buffer  4  of frequency multiplier system  1  of  FIG.  1    and/or to a frequency multiplier such as the frequency doubler  5  of the frequency multiplier system  1  of  FIG.  1   . 
     In the tripler circuit  30  of  FIG.  6   , the first transformer T 1  operates for line adaptation (as a balun transformer) and generates a differential signal (corresponding to input voltage V in  of  FIG.  4    and thus identified with the same reference) directly applied on the first and second input nodes  22 ,  23  of the tripler circuit  20  (and thus on the base terminals of the first and second transistors Q 1 , Q 2 ). The differential signal V in  is reduced by the attenuation α by the capacitive divider  40  and applied to the third and fourth input nodes  27 ,  28  of the tripler circuit  20  (and thus on the base terminals of the third and fourth transistors Q 3 , Q 4 ). 
     The tail inductor  68  resonates with shunt equivalent capacitance existing at the common node  21  and the shunt capacitance  67  is sized sufficiently large to act as an AC-short at the operating frequency of common node  21 , which is 2f o . In fact, LC network  66  allows the shunt parasitic capacitances at common node  21  to charge-discharge at high frequency using the current being exchanged with the tail inductor  68 , hence not to lag behind the base voltages of the input transistors Q 1 -Q 4  when operating at high input frequency. 
       FIG.  7    shows an exemplary implementation of envelope detector  38  generating the offset voltage V os  that satisfies condition (5), according to an embodiment of the present invention. 
     In the specific implementation shown in  FIG.  6   , envelope detector  38  comprises an input differential pair  70  formed by a fifth and a sixth transistor Q 5  and Q 6  and driven by the input voltage V in . A current source  71 , generating a second reference current 2I REF , twice the reference current I REF , is coupled to the emitter terminals of the fifth and sixth transistors Q 5  and Q 6  and to an averaging RC filter  72 . The averaging filter RC  72  includes an averaging resistor  73  having resistance R E  and is coupled to a first voltage generating network  75 . First voltage generating network  75  comprises a first current generating branch  76  and a first current mirroring branch  77 . First current generating branch  76  includes a first current source  80  generating reference current I REF  and a transistor Q 7 ; first current mirroring branch  77  includes a transistor Q 8  that is base-coupled to transistor Q 7  of the first current generating branch  76 , has a collector terminal forming first output  37  of the envelope detector  38  and generates the first biasing voltage Vb 1 . A second voltage generating network  81 , having the same basic structure of the first voltage generating network  75 , has coupled transistors Q 9  and Q 10  and generates the second biasing voltage Vb 2  at a collector of transistor Q 9  coupled to the second output  50  of the envelope detector  38 . The second voltage generating network  81  also includes a second current source  82  generating the reference current I REF . 
     A supply voltage V CC  is applied to the collector terminals of the fifth and sixth transistors Q 5  and Q 6  and to supply nodes of the first and second voltage generating networks  75 ,  81 . Supply voltage V CC  is also applied to a central tap of the second transformer T 2 . 
     All transistors Q 5 -Q 10  in the envelope detector  38  share a same bias voltage V CM . In this way, transistors Q 5 -Q 6  (driven by |V in (t)|) and Q 7 , cause the voltage V RE  on averaging resistor  73  to be equal to the average value of |V in (t)|. Since V in (t)=A sin(2πf o t), voltage on the averaging resistor  73  is V RE =(4/π)A and the current through it is I RE =(4/π)A/R E . MOSFET transistors M 1 , M 2  in the first voltage generating network  75  mirror current I REF +I RE  into a first output resistor  85  (coupled to the first output  37  of the envelope detector  38 ) with resistance R 1 , while MOSFET transistors M 3 , M 4  in the second voltage generating network  81  mirror current I REF  into a second output resistor  86  with resistance R 2  (coupled to the second output  50  of the envelope detector  38 ). Thus:
 
 Vb 1= V   CC −( I   REF   +I   RE )· R 1,
 
 Vb 2= V   CC   −I   REF   ·R 2.
 
     Assuming R 1 =R 2 ,
 
 V   os   =Vb 2− Vb 1= R 1· I   RE =(4/π)( R 1/ R   E ) A.  
 
     The ratio R 1 /R E  is designed such that V os  satisfies condition (5), thus allowing to maintain good suppression of the fundamental frequency component independently from the amplitude of the input signal. 
     Measurements made by the Applicant confirm that the tripler circuit  20  suppresses almost completely the component at fundamental frequency f o  in the output current I o . For example,  FIG.  8    shows the plot of the output power P 3fo  measured at 3f o  when the input power P in  is swept at 12.5 GHz and the plot of the sum P sum  of the output powers P fo  (measured at f o ) and P 5fo  (measured at 5f o ) obtained with the frequency tripler  20 . As may be seen, in the range −5 dBm to 10 dBm, the output power P 3fo  is higher than the sum power P sum  of about 40 dBm in almost the entire input power range and in any case never lower than 36 dBm. 
     The improvement of the tripler circuit  20  with respect to a conventional tripler using class-C operating transistors is also visible from  FIG.  9   , showing the output spectrum obtainable with the present frequency tripler  20  (curve Tr 1 _ 3 fo), the undesired output spectrum at f o  obtainable with a conventional tripler using class-C operating transistors (curve Tr 2 _fo) and the undesired output spectrum at f o  obtainable with the present frequency tripler  20  (curve Tr 1 _fo). As visible, curve Tr 1 _fo is 20 dB lower than curve Tr 2 _fo and 40 dB lower than curve Tr 1 _ 3 fo. 
     Advantages of embodiments of the present invention are clear from the above. For example, it is underlined that, in some embodiments, the tripler circuit is advantageously able to suppress undesired fundamental and harmonics in a much better way than with conventional circuits. 
     In some embodiments, the tripler circuit advantageously operates at low power compared with conventional designs exploiting class-C transistors and filters. 
     Finally, it is clear that numerous variations and modifications may be made to the frequency tripling electronic circuit described and illustrated herein, all falling within the scope of the invention as defined in the attached claims. 
     For example, the bipolar transistors Q 1 -Q 10  could be replaced by MOSFET transistors; the transistors may be made in any technology, such as silicon, gallium arsenide (GaAs), indium phosphide (InP), etc.; the structure of the envelope detector may be any other, provided it performs the functionalities depicted above, specifically it gets Vb 2 −Vb 1 =Vos satisfying relation (5).