Patent Publication Number: US-11665895-B2

Title: Method for manufacturing semiconductor structure and capable of controlling thicknesses of oxide layers

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a division of U.S. application Ser. No. 16/853,764, filed on Apr. 21, 2020, which claims the benefit of U.S. Provisional Application No. 62/915,619, filed on Oct. 15, 2019. The contents of these applications are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The disclosure is related to a method for manufacturing a semiconductor structure, and more particularly, a method for manufacturing a semiconductor structure and capable of controlling thicknesses of oxide layers. 
     2. Description of the Prior Art 
     In a memory device, a program operation can be performed by pulling electrons into a gate terminal (e.g., a floating gate terminal) with the hot carrier injection (HEI) effect. An erase operation can be performed by pulling electrons out of a gate terminal with the Fowler-Nordheim (F-N) tunneling effect. 
     To properly perform a program operation and an erase operation, the thickness of an oxide layer of the gate terminal should be well controlled. However, it is difficult to control the thickness of an oxide layer. 
     When the oxide layer is overly thick, it is difficult to pull electrons into or out of a gate terminal, and the program operation and the erase operation will fail. 
     When the oxide layer is overly thin, electrons stored in the gate terminal will unexpectedly escape to generate leakage currents, and more defects will occur to worsen reliability. 
     As above, it has been a challenge to control the thickness of the oxide layer of a memory device, and another challenge is to further consider an input/output (IO) device. 
     An oxide layer of an IO device should have a proper thickness according to an operation voltage of the IO voltage. However, an IO device and a memory device are formed on the same wafer, and the oxide layer of the IO device may be formed along with the oxide layer of the memory device. This will cause the oxide layer of the memory device to be too thick or too thin. 
     Hence, a proper solution is in need to separately and accurately control the thicknesses of oxide layers of memory device and input/output (IO) device. 
     SUMMARY OF THE INVENTION 
     An embodiment provides a method for manufacturing a semiconductor structure. The method includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; performing a polishing process to planarize a surface of the silicon nitride layer; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer. 
     Another embodiment provides a method for manufacturing a semiconductor structure. The method includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; performing a polishing process to planarize a surface of the silicon nitride layer; removing the silicon nitride layer and the first oxide layer; forming a second oxide layer; implanting ions to form a plurality of well regions; using a first photomask to apply a first photoresist for covering a first part of the second oxide layer on a first area and exposing a second part of the second oxide layer on a second area; and removing the second part of the second oxide layer while remaining the first part of the second oxide layer. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment. 
         FIG.  2    to  FIG.  8    illustrate the process of performing the method of  FIG.  1   . 
         FIG.  9    is a flowchart of a method for manufacturing a semiconductor structure according to another embodiment. 
         FIG.  10    to  FIG.  13    illustrate the process of performing the method of  FIG.  9   . 
         FIG.  14    is a flowchart of a method for manufacturing a semiconductor structure according to another embodiment. 
         FIG.  15    to  FIG.  20    illustrate the process of performing the method of  FIG.  14   . 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1    is a flowchart of a method  100  for manufacturing a semiconductor structure  1  according to an embodiment.  FIG.  2    to  FIG.  8    are cross sectional views during the manufacturing process of the semiconductor structure  1 . 
     Steps S 110  to S 130  may be corresponding to  FIG.  2   . Step S 135  may be corresponding to  FIG.  3   . Steps S 140  to S 145  may be corresponding to  FIG.  4   . Steps S 150  to S 155  may be corresponding to  FIG.  5   . Step S 160  may be corresponding to  FIG.  6   . Step S 165  may be corresponding to  FIG.  7   . Step S 170  may be corresponding to  FIG.  8   . 
     The method  100  may include the following steps. 
     Step S 110 : form a first oxide layer  110  on a wafer  155 ; 
     Step S 115 : form a silicon nitride layer  115  on the first oxide layer  110 ; 
     Step S 120 : form a plurality of trenches; 
     Step S 125 : fill an oxide material in the trenches to form a plurality of shallow trench isolation regions  188 ; 
     Step S 130 : perform a polishing process to planarize the surface of the silicon nitride layer  115 ; 
     Step S 135 : remove the silicon nitride layer  115  without removing the first oxide layer  110 ; 
     Step S 140 : use a photomask to apply a photoresist  166  for covering a first part of the first oxide layer  110  on a first area A 1  and exposing a second part of the first oxide layer  110  on a second area A 2 ; 
     Step S 145 : remove the second part of the first oxide layer  110  while remaining the first part of the first oxide layer  110 ; 
     Step S 150 : remove the photoresist  166 ; 
     Step S 155 : perform a first oxidation process to form a second oxide layer  120  on the second area A 2  and increase a thickness of the first part of the first oxide layer  110 ; 
     Step S 160 : implant ions to form a plurality of well regions W 1 , W 2  and W 3 ; 
     Step S 165 : remove the second oxide layer  120 ; and 
     Step S 170 : perform a second oxidation process to form a third oxide layer  130  on the second area A 2  and increase the thickness of the first part of the first oxide layer  110 . 
     According to an embodiment, in  FIG.  1    to  FIG.  8   , the first oxide layer  110  may be a pad oxide layer. The second oxide layer  120  may be a sacrificial oxide layer. The third oxide layer  130  may be a gate oxide layer of an input/output (IO) device also known as an IO gate oxide layer. 
     A pad oxide layer may be generated using a chemical vapor deposition (CVD) process or a thermal oxidation process, and be formed between a silicon material and a silicon nitride layer to prevent physical strain due to temperature changes or other causes. A sacrificial oxide layer may be used to reduce damages caused by ion implantation. A thickness of an IO gate oxide layer may be adjusted to a proper value according to an operation voltage of the IO device; otherwise, the IO device cannot properly operate with the operation voltage. 
     In  FIG.  2    to  FIG.  8   , the first area A 1  may be corresponding to a memory device, and the second area A 2  may be corresponding to an IO device. 
     In Step S 125 , the oxide material filled in the trenches may be silicon dioxide (SiO 2 ). 
     In Step S 130 , the polishing process may be a chemical-mechanical polishing (CMP) process, also known as a chemical-mechanical planarization process. 
     In Step S 135 , phosphoric acid (e.g., H 3 PO 4 ) or other suitable chemicals may be used to remove the silicon nitride layer  115  by an etching process. 
     In Steps S 140  to S 150 , a part of the first oxide layer  110  may be selectively removed as shown in  FIG.  4    by means of the photomask. The second part of the first oxide layer  110  which is not covered by the photoresist  166  may be removed with an etching process. For example, hydrofluoric acid (e.g., HF) or other suitable chemicals may be used in the etching process. 
     In Step S 155  and Step S 170 , each of the first oxidation process and the second oxidation process may include one of a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process and a thermal oxidation process. 
     In Step S 155 , if the second oxide layer  120  is formed using a deposition process such as a PECVD process, the thickness of the first part of the first oxide layer  110  may be increased from top because additional oxide material may be deposited onto the first oxide layer  110 . 
     In another case, in Step S 155 , if the second oxide layer  120  is formed using a thermal oxidation process, the thickness of the first part of the first oxide layer  110  may be increased from bottom because oxygen ions may move into the bottom of the first part of the first oxide layer  110  to generate additional oxide material. However, no matter a deposition process or a thermal oxidation process is used, a similar structure can be formed. 
     In Step S 160  and  FIG.  6   , ions may be implanted through the first oxide layer  110  and the second oxide layer  120 , so the quality of the first oxide layer  110  and the second oxide layer  120  may be deteriorated. In order to have an IO gate oxide layer with a higher quality and a more optimized thickness, the second oxide layer  120  is removed as mentioned in  FIG.  7    and Step S 165 , and the third oxide layer  130  is newly formed as shown in  FIG.  8    and Step S 170 . 
     As shown in  FIG.  6   , the types of the wells W 1 , W 2  and W 3  may be determined by the ions implanted. For example, the wells W 1 , W 2  and W 3  may be (but not limited to) an n-type well, a p-type well and an n-type well respectively. 
     In this example, the wells W 1  and W 2  may be used to generate elements of a non-volatile memory (NVM), and the well W 3  may be used to generate elements of an IO device. 
     In Step S 165  and  FIG.  7   , as in Step S 145 , an etching process may be performed to remove the second oxide layer  120 . The etching process may also reduce the thickness of the first oxide layer  110 ; however, the thickness of the first oxide layer  110  can be increased afterward as described below. 
     In Step S 170  and  FIG.  8   , as in Step S 155 , the thickness of the first oxide layer  110  may be increased along with the formation of the third oxide layer  130  from top or from bottom according to the type of the second oxidation process. 
     After performing the second oxidation process in Step S 170 , as shown in  FIG.  8   , the thickness TH 1  of the first oxide layer  110  may be larger than the thickness TH 3  of the third oxide layer  130 . 
     For example, the thickness TH 1  of the first oxide layer  110  may be 70 to 100 Å or even larger than 100 Å for a memory device on the area A 1  to operate with an operation voltage of 3.3 volts. 
     The thickness TH 3  of the third oxide layer  130  may be approximately 50 Å for the IO device formed on the area A 2  to operate with an operation voltage of 2.5 volts. 
     The thicknesses and voltage described herein are merely examples instead of limiting the scope of the embodiments. 
     As shown in  FIG.  8   , the oxide layer  110  (of the memory device on the area A 1 ) and the oxide  130  (of the IO device on the area A 2 ) may have different thicknesses. The oxide layer for a memory device (aka memory cell) may be thicker. Because the oxide layer  130  is newly formed, the quality of the IO gate oxide layer can be optimized. By using the photomask and photoresist described in Step S 140 , the thicknesses of different oxide layers can be better controlled. 
       FIG.  9    is a flowchart of a method  900  for manufacturing a semiconductor structure  9  according to an embodiment. 
       FIG.  10    to  FIG.  13    are cross sectional views during the manufacturing process of the semiconductor structure  9 . 
     Steps S 910  to S 930  in  FIG.  9    may be similar to Steps S 110  to S 130  in  FIG.  1    and corresponding to  FIG.  2   , so the steps are not repeatedly described, and the related structural cross-sectional views are not repeatedly shown. 
     Steps S 935  to S 945  may be corresponding to  FIG.  10   . Step S 947  may be corresponding to  FIG.  11   . Steps S 950  and S 955  may be corresponding to  FIG.  12   . Steps S 960  and S 965  may be corresponding to  FIG.  13   . 
     The method  900  may include the following steps. 
     Step S 910 : form a first oxide layer  110  on a wafer  155 ; 
     Step S 915 : form a silicon nitride layer  115  on the first oxide layer  110 ; 
     Step S 920 : form a plurality of trenches; 
     Step S 925 : fill an oxide material in the trenches to form a plurality of shallow trench isolation regions  188 ; 
     Step S 930 : perform a polishing process to planarize a surface of the silicon nitride layer  155 ; 
     Step S 935 : remove the silicon nitride layer  115  and the first oxide layer  110 ; 
     Step S 940 : form a second oxide layer  920 ; 
     Step S 945 : implant ions to form a plurality of well regions W 1 , W 2  and W 3 ; 
     Step S 947 : perform a thinning process to reduce a thickness of the second oxide layer  920 ; 
     Step S 950 : use a photomask to apply a photoresist  966  for covering a first part of the second oxide layer  920  on a first area A 1  and exposing a second part of the second oxide layer  920  on a second area A 2 ; 
     Step S 955 : remove the second part of the second oxide layer  920  while remaining the first part of the second oxide layer  920 ; 
     Step S 960 : remove the photoresist  966 ; and 
     Step S 965 : perform an oxidation process to form a third oxide layer  930  on the second area A 2  and increase a thickness of the first part of the second oxide layer  920 . 
     In  FIG.  10    to  FIG.  13   , the oxide layer  920  may be a sacrificial oxide layer, and the oxide layer  930  may be a gate oxide layer of an input/output device (IO gate oxide layer). 
     In  FIG.  10   , the thickness TH 92  of the oxide layer  920  may be 90 Å to 120 Å. 
     In  FIG.  11    and Step S 947 , the thinning process may be (but not limited to) an etching process. The thickness TH 92  of the oxide layer  920  may be 40 Å to 80 Å after the thinning process is performed. 
     In  FIG.  12    and Step S 950 , the photoresist  966  may be similar to the photoresist  166  in  FIG.  4   , and be used to retain the oxide layer  920  on the first area A 1 , where a memory device can be formed in the first area A 1 . The thickness TH 92  of the oxide layer  920  in  FIG.  11    may be kept the same in  FIG.  12   . In Step S 955 , the oxide layer  920  on the area A 2  may be removed by etching. 
     In  FIG.  13    and Step S 965 , the oxidation process may include one of a CVD process, a PVD process, a PECVD process and a thermal oxidation process. The thickness TH 92  of the oxide layer  920  in  FIG.  13    may be increased from top or from bottom according to the type of the oxidation process in Step S 965 . 
     In  FIG.  13   , after performing the oxidation process, the thickness TH 92  of the oxide layer  920  may be larger than the thickness TH 93  of the oxide layer  930 . 
     For example, in  FIG.  13   , the thickness TH 92  may be increased to be 90 Å to 120 Å, and the thickness TH 93  may be approximately 50 Å. 
     A memory device may be formed in the area A 1 , and an IO device may be formed in the area A 2 . According to the thicknesses TH 92  and TH 93  in  FIG.  13   , the memory device may operate with an operation voltage of 3.3 volts, and the IO device may operate with an operation voltage of 2.5 volts. 
     In  FIG.  13   , as in  FIG.  8   , the oxide layer for a memory device (aka memory cell) may be thicker. Because the oxide layer  930  is newly formed, the quality of the IO gate oxide layer can be optimized. By using the photomask and photoresist described in Step S 950 , the thicknesses of different oxide layers can be better controlled. 
       FIG.  14    is a flowchart of a method  1400  for manufacturing a semiconductor structure  14  according to an embodiment.  FIG.  15    to  FIG.  20    are cross sectional views during the manufacturing process of the semiconductor structure  14 . In  FIG.  14   , Steps S 1410  to S 1445  may be similar to Steps S 910  to S 945  in  FIG.  9   , so the steps are not repeatedly described, and the related structures similar to  FIGS.  2  and  10    are not repeatedly shown. 
     However, in  FIG.  14   , because more shallow trench isolation region(s)  188  may be formed, the number of trenches may be different from that of  FIG.  9   . 
     In  FIG.  14   , Steps S 1445  and S 1450  may be corresponding to  FIG.  15   . Step S 1455  may be corresponding to  FIG.  16   . Steps S 1460  and S 1465  may be corresponding to  FIG.  17   . Step S 1470  may be corresponding to  FIG.  18   . Step S 1475  may be corresponding to  FIG.  19   . Steps S 1480  and S 1485  may be corresponding to  FIG.  20   . 
     As shown in  FIG.  14   , the method  1400  may include following steps. 
     Step S 1410 : form a first oxide layer  110  on a wafer  155 ; 
     Step S 1415 : form a silicon nitride layer  115  on the first oxide layer  110 ; 
     Step S 1420 : form a plurality of trenches; 
     Step S 1425 : fill an oxide material in the trenches to form a plurality of shallow trench isolation regions  188 ; 
     Step S 1430 : perform a polishing process to planarize a surface of the silicon nitride layer  155 ; 
     Step S 1435 : remove the silicon nitride layer  115  and the first oxide layer  110 ; 
     Step S 1440 : form a second oxide layer  920 ; 
     Step S 1445 : implant ions to form a plurality of well regions W 1 , W 2 , W 3  and W 4 ; 
     Step S 1450 : use a first photomask to apply a first photoresist  966  for covering a first part of the second oxide layer  920  on a first area A 1  and exposing a second part of the second oxide layer  920  on a second area A 2 ; 
     Step S 1455 : remove the second part of the second oxide layer  920  while retaining the first part of the second oxide layer  920 ; 
     Step S 1460 : remove the first photoresist  966 ; 
     Step S 1465 : perform a first oxidation process to form a third oxide layer  930  on the second area A 2  and increase a thickness of the first part of the second oxide layer  920 ; 
     Step S 1470 : use a second photomask to apply a second photoresist  1466  for covering a first part of the third oxide layer  930  and exposing a second part of the third oxide layer  930 ; 
     Step S 1475 : perform an etching process to remove the second part of the third oxide layer  930  and reduce the thickness of the first part of the second oxide layer  920 ; 
     Step S 1480 : remove the second photoresist  1466 ; and 
     Step S 1485 : perform a second oxidation process to form a fourth oxide layer  1440 , increase the thickness of the first part of the second oxide layer  920 , and increase a thickness of the first part of the third oxide layer  930 . 
     In Step S 1445 , compared with Step S 945  of  FIG.  9   , a well W 4  may be further formed. 
     Compared with  FIG.  9   , as shown in  FIG.  14   , Step S 947  of  FIG.  9    may be selectively omitted so as not to thin the second oxide layer  920 . 
     In  FIG.  14    to  FIG.  20   , the wells W 1  and W 3  may be n-type wells, and the wells W 2  and W 4  may be p-type wells. However, this is merely an example instead of limiting the scope of the embodiments. 
     In  FIG.  14   , the first oxide layer  110  (as shown in  FIG.  2   ) may be a pad oxide layer, the second oxide layer  920  (as shown in  FIG.  20   ) may be a sacrificial oxide layer, the third oxide layer  930  (as shown in  FIG.  20   ) may be a gate oxide layer of an input/output device (IO gate oxide layer), and the fourth oxide layer  1440  (as shown in  FIG.  20   ) may be an oxide layer of a core device. For example, a core device may include a circuit formed with logic gate components. 
     In  FIG.  18    and Step S 1470 , the first part of the third oxide layer  930  may be on the first part A 21  of the second area A 2 , and the second part of the third oxide layer  930  may be on the second part A 22  of the second area A 2 . 
     The first area A 1  may be corresponding to a memory device. The first part A 21  of the second area A 2  may be corresponding to an IO device. The second part A 22  of the second area A 2  may be corresponding to a core device. 
     Regarding the methods shown in  FIG.  1   ,  FIG.  9    and  FIG.  14   , the second oxide layer  920  may be annealed after implanting the ions to enhance the quality of the oxide layer  920 . 
     In Step S 965  and Step S 1485 , each of the first oxidation process and the second oxidation process may include one of a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process and a thermal oxidation process. 
     In  FIG.  15    and  FIG.  16   , the thickness of the oxide layer  920  may be 90 Å to 120 Å. 
     In  FIG.  17    and  FIG.  18   , the thickness of the oxide layer  920  may be increased to 140 Å to 170 Å. The thickness of the oxide layer  930  may be approximately 50 Å. 
     In  FIG.  19   , the thickness of the oxide layer  920  may be reduced to 90 Å to 120 Å. The thickness of the oxide layer  930  may be approximately 50 Å. The abovementioned thicknesses are merely of an example for describing the changes of the thicknesses of oxide layers in different stages instead of limiting the scope of the embodiments. 
     As shown in FIG. 20 , after performing Step S 1485 , the thickness of the second oxide layer  920  may be larger than the thickness of the third oxide layer  930 . The thickness of the third oxide layer  930  may be larger than the thickness of the fourth oxide layer  1440 . The thickness of the oxide layer  1440  may be less than 50 Å. 
     After performing Step S 1485 , a standard (STD) logic process flow may be performed to fabricate a core device. 
     In summary, according to methods shown in  FIG.  1   ,  FIG.  9    and  FIG.  14   , by applying the photoresist  966  and/or the photoresist  1466  mentioned above, oxide layers of a memory device, an IO device and a core device may be separately and accurately formed to have different thicknesses. Hence, the memory device can be better programmed and erased and have improved reliability, and the IO cell can be operated with a proper operation voltage such as 3.3 volts, 5 volts, 2.5 volts or 1.8 volts. Advanced manufacture processes can be better applied to fabricate the I 0  device and the memory device with fewer problems related to oxide layers. The problems of the field can hence be reduced. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.