Patent Publication Number: US-8988260-B2

Title: Method and circuit for continuous-time delta-sigma DAC with reduced noise

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation application of U.S. patent application Ser. No. 13/053,303 to Martin Kinyua, filed Mar. 22, 2011, entitled “Method and Circuit for Continuous-Time Delta-Sigma DAC With Reduced Noise,” the entirety of which is hereby incorporated by reference herein. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to continuous-time delta-sigma digital-to-analog converters (DACs) and to methods of reducing noise in same. 
     BACKGROUND 
     Delta-sigma modulators generally employ noise-shaping (filtering) and over-sampling to perform digital-to-analog (“D/A”) conversion at relatively high resolution for signals of modest bandwidth. The higher the order of the sigma-delta modulator, the further the quantization noise is pushed into the frequency band, away from the signal base band being converted. As such, DACs using delta-sigma modulators have become popular in a wide range of high precision applications, such as audio applications. 
     In a typical sigma-delta DAC architecture, a digital data signal (e.g. 16 bit audio data at a rate of 48 kHz) is upsampled by an interpolator at some multiple of the original data rate (e.g., at an upsampling ratio of 128 times (6.144 MHz/48 kHz)). The resulting oversampled digital signal is applied to a multi-bit sigma-delta modulator. The multi-bit digital data outputted by the modulator is applied to a multi-bit DAC, which may comprise a multi-bit current DAC (IDAC) to generate a multi-level analog current signal followed by a current-to-voltage converter to convert this analog current signal to an analog voltage signal. Finally, the stepped voltage signal is applied to a low pass filter to provide a smoothed analog output signal. 
     There are several problems with the known approaches to delta-sigma DACs, some of which are noted hereafter. First, known DACs require intrinsically low noise circuits, which are power and area hungry. Second, known approaches require the use of chopper stabilization to reduce low frequency 1/f noise in the CMOS circuits, which adds design complexity. Finally, these approaches require current sources with very high output impedances. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings illustrate preferred embodiments of the disclosure, as well as other information pertinent to the disclosure, in which: 
         FIG. 1  is a block diagram illustrating a sigma-delta DAC; 
         FIGS. 2 and 3  are signal flow diagrams illustrating an embodiment of the noise-shaping loop of an improved continuous-time sigma-delta DAC topology; and 
         FIG. 4  illustrates an embodiment of a reconstruction DAC/Low Pass Filter (henceforth LPF) circuit for use in an improved continuous-time sigma-delta DAC topology. 
     
    
    
     DETAILED DESCRIPTION 
     This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. Terms concerning electrical attachments, coupling and the like, such as “connected”, “interconnected,” and “coupled” refer to a relationship wherein structures communicate with one another either directly or indirectly through intervening structures, unless expressly described otherwise. In contrast, for example, when an element is referred to as being “directly coupled” to another element, there are no intervening elements present. 
     By way of introduction,  FIG. 1  is a block diagram view of a sigma-delta DAC. The DAC includes digital and analog sections. The digital section includes an interpolation filter  10  and a noise-shaping loop  12 , and the analog section includes a DAC  14  (which can really be considered the bridge from the digital section to the analog section), and a low pass filter  16 . The output of the sigma-delta DAC is coupled to an analog output device, such as headphones  16  or other device (e.g., speakers). As will be familiar to those in the art, the interpolation filter  10  is a conventional device that upsamples the digital input N 0  (e.g. 16 bit audio data at a rate of 48 kHz) and provides some oversampled digital output N 1  (e.g., at an oversampling ratio of 128 times (6.144 MHz/48 kHz)). The oversampling ratio is some ratio beyond the Nyquist rate so that the noise is spread beyond the original frequency band and over a larger frequency band. The interpolation filter is of conventional design and will not be described further herein. 
     The noise-shaping loop  12  takes the quantization noise that has been spread over a larger bandwidth by the interpolation filter  10  and suppresses the low frequency noise. More specifically, the noise shaping loop pushes most of the noise out to higher frequencies. Digital signal N 2  typically has fewer bits (i.e., lower resolution) than N 1  as there is a truncation operation in the noise-shaping loop  12 . The DAC  14  then converts the signal to analog. This DAC can be operated in a continuous or discrete time fashion. With respect to the present disclosure, the DAC is operated in continuous time. Finally, the low pass filter  14  filters out images of the signal and out-of-band noise to recover the original analog signal. 
     The present disclosure focuses on improvements to the noise-shaping loop  12 , DAC  14  and low pass filter  16  blocks shown in  FIG. 1 . Embodiments of an over-sampled continuous time sigma-delta digital-to-analog converter (DAC) with reduced noise and methods of digital-to-analog conversion using the same are illustrated herein. As described in more detail below, the novel noise-shaping loop offers the ability to achieve higher resolution for the same area as prior art sigma-delta DACs. An improved output DAC/filter stage is also provided in the analog stage which exhibits the ability to reduce thermal and 1/f noise. This stage converts the output current into voltage using a reconstruction amplifier in a manner such that substantial amount of this noise is converted into common-mode, which is rejected by the differential nature of the circuit. 
     The sigma-delta topography described herein does not: (i) require either the intrinsically low noise circuits of the prior art, which by default will consume more power and area than the proposed solution; (ii) require the use of chopper stabilization circuits, which increase design complexity, to reduce 1/f noise in circuits; or (iii) require current sources with very high output impedance. By 1/f noise, those of skill in the art will understand that it is meant the noise that is dominant at lower frequencies due to impurities in the channel-oxide interface of the transistors of CMOS devices and is common to all CMOS devices. Because this noise dominates at low frequencies, it is a particular concern for audio outputs. 
       FIG. 2  illustrates an embodiment of a noise shaping loop of an improved continuous time sigma-delta DAC. With reference to  FIG. 1 , the diagram of  FIG. 2  relates principally to the noise-shaping loop block  12  and secondarily to the DAC block  14 . The combination of the noise shaping loop and DAC are referred to by the reference  100 . The operation of these components is illustrated in  FIG. 2  by way of signal flow diagram. The noise-shaping loop includes a first delta-sigma modulator stage  102  and a second multi-stage delta-sigma modulator stage  150 . A digital input (represented by “x”) is provided at input node  104  to the first delta-sigma modulator stage  102 , and an analog output (represented by “y”) is provided at output node  106 , which is coupled through a LPF to provide the final analog representation A(z) of the digital input signal “x”. The first stage  102  is a classical first order delta sigma modulator with a noise shaping loop  108  having a noise transfer function NTF(z), where the variable “z” represents the sampled-data transform variable as generally recognized in the art. As will be understood, the noise shaping loop  108  typically includes an n-stage integrator and a coarse quantization stage (i.e., truncator), with its relatively large coarse quantization error represented by error signal e 1 (z). The digital input signal x is reduced to a low resolution bit stream in the noise-shaping loop. The output bit stream of the first stage  102  is provided to a first DAC  110 , labeled M1-bit DAC, which has a resolution of M1-bits and converts the output of the noise shaping loop  108  linearly. In embodiments, M1 is one bit, though this is not a requirement and any practical number of bits can be selected (i.e., 1 or more). 
     The residual truncation error signal e1(z) is coupled to the second multi-stage delta-sigma modulator stage  150 . More specifically, the first error signal e1(z) is coupled to the second stage  150  through an inter-stage gain  112 . The function is set preferably to a constant gain K1. The second stage  150  includes a pair of cascaded quantizers, specifically a first quantization stage  160  including a first multi-bit quantizer (truncator)  162 , which quantizes the next most significant bits, and a second quantization stage  170  including a second multi-bit quantizer  172 , which quantizes the least significant bits. 
     Quantization noise signals generated by quantizers  162  and  172  are illustrated as noise signals e 2 (z) and e 3 (z). Specifically, noise signal −e 2  is provided from summer  164 , which subtracts the output of the first quantizer  162  from its input, and noise signal e 3  is provided from summer  174 , which subtracts the input of the second quantizer  172  from its output. The output of first quantization stage, i.e., error signal −e 2 , is provided to the input of the second quantization stage  170  after passing through the block represented by gain stage  114 . The filtering function of this stage is set preferably to a constant gain K 2 . 
     The output of the second quantizer  172  is scaled by gain stage  116 . The function of this stage is set preferably to a constant gain 1/K 2  (i.e., to the inverse of gain stage  114 ). The conversion results of the first and second quantization stages  160 ,  170 , i.e., the output of truncator  162  and the output of the gain stage  116 , are summed in summer  180 . 
     The noise-shaping filter represented by the filter transfer function F(z) in block  182  filters the error signal e 3 , producing a filtered quantization error signal at its output. This filtered quantization error signal is subtracted from the filtered quantization error signal e 1  at summer  184  to produce the input signal for the quantizer  162  in the quantization stage  160 . 
     The output of summer  180  is scaled by gain stage  118 . The scaling function of this stage  118  is set preferably to constant gain 1/K 1  (i.e., to the inverse of gain stage  112 ). The output of gain stage  118  is filtered in noise-shaping filtering block  190  to produce the conversion of results of the cascaded multi-stage delta-sigma modulator  150 . Noise-shaping filtering block  190  has the same transfer function as that of the noise shaping loop  108  (i.e., NTF(z)). These conversion results are provided to a second DAC  120 , labeled M2-bit DAC, which has a finer resolution of M2-bits than DAC  110  (i.e., M2&gt;M1). The outputs of DACs  110 ,  120  are summed by summer  192  to provide analog output signal y. 
       FIG. 3  illustrates another way of looking at the DAC  100 , and specifically the noise shaping loop  108 , where: X(z) is the digital input signal; STF(z) is the signal transfer function of the noise shaping loop  108 ; NTF(z) is the noise transfer function of the noise shaping loop  108 ; A(z) is the output; e 1 (z) is the first stage truncation error; K 1  is a first inter-stage gain; e 2 (z) is the multi-bit truncation error of quantizer  162 ; e 3 (z) is the multi-bit truncation error of quantizer  172 ; K 2  is a second inter-stage gain; and F(z) is a digital filter. The output y(z) can be expressed by the following equation: y(z)=x(z)·STF(z)+e 3 /(k 1 ·k 2 )·(1−F(z)·k 2 )·NTF(z). From the equation, it can be seen that the new topology introduces several design options for quantization noise cancelation and higher-order noise shaping. The choice of the noise-shaping filters depends on practical considerations, such as ease of implementation, sensitivity of noise cancellation to analog circuit non-idealities, and dynamic range. 
     For example, assume the following conditions: (i) STF(z)=z −1 , which is a simple delay function; (ii) NTF(z)=(1−z −1 ) n , which represents an nth order differencing function; and (iii) F(z)=z −1 /k 2 . Using these conditions, we know that (1−F(z)·k 2 )=1−z −1 . As such, these conditions yield: Y(z)=x(z)·z −2 +(1−z −1 ) 3 ·e 3 /(k 1 ·k 2 ). The first part of the sum (i.e., x(z)·z −2 ) simply represents a delay in the input signal. More significantly, the second part of the sum illustrates a third order noise shaping (i.e., high pass filtering) of the error e 3 , scaled by the K 1  and K 2  inter-stage gains. Of particular note, coarse quantization error e 1  and the error e 2  of quantization stage  160  are removed. All that remains is the fine error of the final cascade stage  170  but scaled down and filtered. 
     The quantization noise suppression corresponds to a single composite DAC with M2*k 1 *k 2  levels, which would be the equivalent composite DAC, while employing (as noted above) fewer DAC unit elements than prior art approaches. For example, assume a DAC resolution of M1+M2 bits. With the approach described above in connections with  FIGS. 2 and 3 , the number of DAC elements would be 2 M1 +2 M2 . So, if M1 is 2 and M2 is 3, then the approach uses 12 DAC elements. In comparison to, for example, the approach described in T. Rueger, et al., “A 110 dB Ternary PWM Current-Mode Audio DAC with Monolithic 2Vrms Driver”, §20.7 (2004), that approach would use 2( M1+M2 ) DAC elements, which is an exponential increase over the approach described herein, and would require 32 DAC elements. With the approach described in  FIGS. 2 and 3 , there is a reduction in analog computation in exchange for increased digital computation. This allows for reduced DAC component count and thus reduced area and lower power for the same resolution as the prior art, or increased resolution at the same area cost as the prior art. 
     As noted above, improvements in the reconstruction DAC and LPF of a continuous time delta-sigma DAC are also disclosed herein.  FIG. 4  illustrates a circuit diagram of a reconstruction DAC/low pass filter  200 . The M1-bit DAC  110  and M2-bit DAC  120  from  FIGS. 2 and 3  are also shown for ease of illustration. These DACs, which are multi-bit current DACS (IDACs) have fully differential analog current outputs I DAC1,P /I DAC1,N  and I DAC2,P /I DAC2,N . IDACs are known in the art and are not described in further detail so as to not obscure the present disclosure. Currents I DAC1,P  and I DAC2,P  are summed together at node  202 . A prior art DAC error suppression method known as Dynamic Element Matching (DEM) is applied to linealize the IDAS and also reduce 1/f noise. Currents I DAC1,N  and I DAC2,N  are summed together at node  204 . These summed currents are inputs to a continuous time current-voltage (I-V) reconstruction amplifier. 
     The continuous-time I-V reconstruction amplifier includes first and second operational amplifiers  206 ,  208 . The inverting inputs (−) of the first and second op-amps  206 ,  208  are coupled to nodes  202 ,  204 , respectively, and the non-inverting inputs (+) are coupled common mode bias voltage V CM,IN . The outputs of the op-amps  206 ,  208  are fed back to the inverting inputs via respective paths that include a resistor R F  in parallel with a capacitor C F . The op-amps in connection with the resistors R F  act as a current-to-voltage converter. The resistors R F  in parallel with the capacitors C F  act as a low pass filter. 
     A pair of common mode current sources  210 ,  212 , which provide common mode currents I DAC1,CM  and I DAC2,CM , respectively, for setting the output common mode current level are coupled to node  214 . Node  214  is coupled to the nodes  202 ,  204  via a pair of cascode transistor devices  216 ,  218 , respectively. These cascode devices  216 ,  218  do not introduce transistor noise to the output node, These transistors act to increase the output impedance of the current sources  210 ,  212  to avoid a large drift in the output common mode. Summing currents I DAC2,CM  and I DAC1,CM  at node  214  and connecting that node to the inverting inputs of the op-amps  206 ,  208  allows for the differential canceling of any noise (mainly thermal and 1/f) introduced by the common mode current sources  210 ,  212 . 
     It should be understood that IDAC1,CM corresponds to M1 Bit DAC and IDAC2,CM corresponds to M2 Bit DAC in  FIG. 4 . Current IDAC1,CM sets the common mode level of the aggregate currents at the output. For example, looking at the contribution of the M1 bit DAC and IDAC1,CM currents to the outputs, in one embodiment, if IDAC1,CM=IDAC1P+IDAC1N, then the currents at the output nodes Vop and Von become the following: at node Vop current is IDAC1P−IDAC1,CM/2; and at node Von current is IDAC1N−IDAC1,CM/2. The differential current is the current at Vop minus the current at Von, which is IDAC1P−IDAC1N. The common mode current is the sum of the currents, divided by 2, which is 0 because IDAC1,CM=IDAC1P+IDAC1N. Therefore IDAC1,CM effectively sets the output common mode level of the aggregated M1 BIT DAC and IDAC1,CM currents. The same analysis applies looking instead at the contribution of the M2 bit DAC and IDAC2,CM currents to the outputs. 
     Voltages Vb1 and Vb2 can be the same or different, depending on the design. These voltages are bias voltages to set the IDAC1,CM and IDAC2,CM currentrs respectively. 
     With prior art circuits, such as those described in U.S. Pat. No. 7,205,920 to Morrow et al. and T. Rueger, et al., “A 110 dB Ternary PWM Current-Mode Audio DAC with Monolithic 2Vrms Driver”, ISSCC (2004), each common mode current generator injects a current noise into the output nodes, and this noise is not canceled at the output by the differential subtraction of I DAC,P  and I DAC,N . As such, in prior art circuits, chopper stabilization is typically used to reduce in-band 1/f noise at both the IDACs  110 ,  120  and at the pulldown current sources  210 ,  212 . This chopper stabilization is conspicuously absent from the common mode current sources  210 ,  212 . The improved approach shown in  FIG. 4  for connecting the common mode current sources eliminates the need for chopping at the pull down current sources. Nor are dynamic element matching (DEM) techniques (shown illustratively at the IDAC stages  110 ,  120 ) required to counter 1/f noise in the lower half of the circuit  200 . 
     That the illustrated configuration of circuit  200  adds no noise to the output from the common mode current sources  210 ,  212 , which would require countermeasures like DEM and/or chopper stabilization to remove, can be mathematically illustrated. The output V 0  can be derived as shown below, per Kirchoffs&#39;s Current Law. 
     First, we know that the output current of the op-amp  206  must equal its input current, per application of the current law at node  202 . Thus, equation 1: (V op −V cm,in )/R F +(I dac1,cm +I dac2,cm )/2+I dac1,p +I dac2,p =0. 
     Likewise, we know that the output current of the op-amp  208  must equal its input current, per application of the current law at node  204 . Thus, equation 2: (V on −V cm,in )/R F +(I dac1,cm +I dac2,cm )/2+I dac1,n +I dac2,n =0. 
     Subtracting equation 1 from equation 2 provides: (V op −V on )/R f +I dac1,p +I dac2,p −(I dac1,n +I dac2,n )=0. Solving for V o , which equals V op −V on , then V o =((I dac1,p +I dac2,p )−(I dac1,n +I dac2,n ))·R F . As can be seen from this equation, the output voltage V o  has no I DAC1,CM  or I DAC2,CM  term, meaning it contains no noise from the common mode current sources  210 ,  212  even without providing 1/f chopping stabilization. In addition any other errors in current sources  210  and  212  have no impact on the differential output because they appear as common mode artifacts. Therefore those current sources do not require high output impedance in contrast to prior art implementations. 
     The ability to reduce thermal and 1/f transistor noise in this way is somewhat counterintuitive, as the common wisdom in the art is that that in order to reduce these types of transistor noise it is necessary to either increase power (i.e., current consumption) and/or the size (W/L area) of the transistor. However, as demonstrated above, this new configuration illustrates the ability to cancel out the noise attributable to the transistors of the common mode current sources  210 ,  212  without increasing either transistor size or current consumption. 
     The noise shaping loop of  FIGS. 2 and 3  and described herein was modeled as a second order loop using MATLAB/SIMULINK™ software. A representative noise simulation of the DAC/LPF disclosed herein was also modeled using CADENCE/SPECTRE™ software. The combined results, which are illustrative of the performance of a continuous-time delta-sigma DAC constructed in accordance with these teachings, showed about a 6 dB improvement in signal-to-noise ratio over conventional designs for the same input power. 
     Per the foregoing description, a continuous time sigma-delta DAC is presented that employs a novel configuration for higher order noise shaping cascaded stages with feedback and error quantization error filtering. The DAC can also employ an improved reconstruction DAC/LPF circuit that converts part of their noise into common mode, which is then cancelled by fully differential implementation. Some advantages of these approaches when compared to conventional approaches include the ability to attain higher resolution than conventional designs for the same component count, better noise performance with less circuit complexity, and higher SNR for the same power. Further, the common mode level setting current sources do not limit the noise performance or linearity of the DAC. Moreover, no output common-mode amplifier is required in contrast with certain conventional designs. 
     In one embodiment of a continuous-time delta-sigma digital-to-analog converter (DAC), the DAC includes: a first delta-sigma modulator configured to quantize a most significant bit or bits of a digital input signal and produce a first quantization error signal, and a second multi-stage delta-sigma modulator configured to quantize less significant bits of the digital input signal. The second multi-stage delta sigma modulator includes a first quantization stage coupled to a difference of the first quantization error signal and a second quantization error signal and configured to quantize next most significant bits of the digital input signal and produce a third quantization error signal representing a difference between an input and an output of the first quantization stages; a second quantization stage with an input coupled to the third quantization error signal and configured to quantize least significant bits of the digital input signal and produce the second quantization error signal representing a difference between the input and an output of the second quantization stage; a first noise-shaping filter for filtering the second quantization error signal, the output of the first noise-shaping filter subtracted from the first quantization error signal to produce the input of the first quantization state; and a second noise-shaping filter having an input coupled to a sum of an output of the first quantization stage and an output of the second quantization stage. The continuous-time delta-sigma modulator also includes a first DAC coupled to an output of the first delta-sigma modulator; a second DAC coupled to an output of the second noise-shaping filter; and a low pass output filter coupled to a sum of an output of the first DAC and an output of the second DAC, wherein the second DAC has a greater resolution than the first DAC. 
     An exemplary embodiment of a method of continuous-time digital-to-analog conversion, includes the steps of: receiving a digital input signal; converting the digital input signal to a low resolution digital signal representing the most significant bit or bits of the digital input signal with a first delta-sigma modulator; producing a first quantization error signal resulting from converting the digital input signal to the low resolution digital signal in the first delta-sigma modulator; and quantizing less significant bits of the digital input signal in a second multi-stage delta-sigma modulator, the quantizing comprising. The quantizing includes the following steps: quantizing next most significant bits of the digital input signal in a first quantization stage of the second multi-stage delta-sigma modulator using a difference of the first quantization error signal and a second quantization error signal; producing a third quantization error signal representing a difference between an input and an output of the first quantization stage of the second multi-stage delta-sigma modulator; quantizing in a second quantization stage of the second multi-stage delta-sigma modulator least significant bits of the digital input signal with an input coupled to the third quantization error signal; producing the second quantization error signal representing a difference between the input of the second quantization stage and an output of the second quantization stage of the second multi-stage delta-sigma modulator; coupling a first noise-shaping filter to the second quantization error signal, and subtracting an output of the first noise-shaping filter from the first quantization error signal to produce the input of the first quantization stage of the second multi-stage delta-sigma modulator; and coupling a sum of an output of the first quantization stage and an output of the second quantization stage to a second noise-shaping filter. The output of the first delta-sigma modulator is coupled to a first digital-to-analog converter (DAC), and the output of the second noise-shaping filter is coupled to a second DAC. The method includes the further step of low pass filtering a sum of an output of the first DAC and an output of the second DAC, wherein the second DAC has a greater resolution than the first DAC. 
     Although the invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly to include other variants and embodiments of the invention that may be made by those skilled in the art without departing from the scope and range of equivalents of the invention.