Patent Publication Number: US-8120407-B1

Title: Techniques for varying phase shifts in periodic signals

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to electronic circuits, and more particularly, to techniques for varying phase shifts in periodic signals. 
     Many modern digital data systems transmit high-speed data without a clock signal. A receiver that receives the transmitted data generates a clock signal from a reference frequency signal using a phase-locked loop. The receiver then phase-aligns the clock signal to the transitions in the data using a clock and data recovery (CDR) circuit. 
     Periodic jitter in the data or in the reference frequency signal may cause the CDR circuit to get caught in a dead-zone. When the CDR circuit is caught in a dead-zone, the CDR circuit fails to adjust the phase of the recovered clock signal to the appropriate phase in response to the transitions of the input data signal. The CDR circuit may sample incorrect data when the CDR circuit is caught in a dead-zone. Therefore, it would be desirable to provide a CDR circuit that does not get caught in a dead-zone. 
     BRIEF SUMMARY OF THE INVENTION 
     According to some embodiments, a circuit includes a phase detection circuit and a phase change circuit. The phase detection circuit compares a phase of a first periodic signal to an input signal to generate a gain signal. The phase change circuit provides phase shifts to the first periodic signal in first and second directions when the gain signal has a first value. The phase change circuit increases phase shifts provided to the first periodic signal in the first direction in response to the gain signal changing from the first value to a second value. The phase change circuit provides phase shifts to the first periodic signal in the second direction when the gain signal has the second value that are smaller than the phase shifts provided to the first periodic signal in the first direction when the gain signal has the second value. 
     Various objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an example of a clock and data recovery (CDR) circuit, according to an embodiment of the present invention. 
         FIG. 2  is a flow chart that illustrates the operation of the CDR circuit of  FIG. 1 , according to an embodiment of the present invention. 
         FIG. 3A  is a timing diagram that illustrates an example of an ideal timing relationship between the input Data signal and the recovered clock signals, according to an embodiment of the present invention. 
         FIGS. 3B ,  3 C, and  3 D are timing diagrams that illustrate examples of timing relationships between the input Data signal and the recovered clock signals that cause the second phase detector in  FIG. 1  to generate a logic high state in its output signal, according to embodiments of the present invention. 
         FIGS. 3E-3F  are timing diagrams that illustrate examples of timing relationships between the input Data signal and the recovered clock signals that cause the second phase detector in  FIG. 1  to generate a logic low state in its output signal, according to embodiments of the present invention. 
         FIG. 4  is a simplified partial block diagram of a field programmable gate array (FPGA) that can include aspects of the present invention. 
         FIG. 5  shows a block diagram of an exemplary digital system that can embody techniques of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  illustrates an example of a clock and data recovery (CDR) circuit  100 , according to an embodiment of the present invention. CDR circuit  100  includes phase detector circuit  101 , phase detector circuit  102 , up counter circuit  103 , down counter circuit  104 , up counter circuit  105 , count logic circuitry  106 , phase interpolator control circuit  107 , phase interpolator circuit block  108 , and phase-locked loop circuit  109 . 
     CDR circuit  100  is typically fabricated in an integrated circuit such as, for example, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a memory integrated circuit, a processor or controller integrated circuit, an analog integrated circuit, etc. 
     Phase-locked loop (PLL) circuit  109  generates a set of 8 periodic digital clock signals PCLK[0:7] that have the same frequency in response to a reference clock signal REFCLK. PLL  109  can be a digital or an analog PLL. PLL  109  can generate the 8 clock signals PCLK[0:7] using, for example, an oscillator circuit. The 8 clock signals PCLK[0:7] are transmitted from PLL  109  to inputs of phase interpolator circuit block  108 . 
     Phase interpolator circuit block  108  generates 8 recovered periodic digital clock signals CLK 0 , CLK 45 , CLK 90 , CLK 135 , CLK 180 , CLK 225 , CLK 270 , and CLK 315  in response to the 8 clock signals PCLK[0:7] generated by PLL  109 . Clock signals CLK 0 , CLK 45 , CLK 90 , CLK 135 , CLK 180 , CLK 225 , CLK 270 , and CLK 315  have relative phases of 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°, respectively. Clock signals CLK 0 , CLK 45 , CLK 90 , CLK 135 , CLK 180 , CLK 225 , CLK 270 , and CLK 315  are referred to herein as the recovered clock signals. Each of the 8 recovered clock signals CLK 0 , CLK 45 , CLK 90 , CLK 135 , CLK 180 , CLK 225 , CLK 270 , and CLK 315  has the same frequency as each of the other recovered clock signals. 
     Phase interpolator circuit block  108  shifts the phases of clock signals CLK 0 , CLK 45 , CLK 90 , CLK 135 , CLK 180 , CLK 225 , CLK 270 , and CLK 315  in response to changes in the logic states of a set of phase control signals PCS generated by phase interpolator control circuit  107 . The PCS signals are a set of digital signals that encode the phase setting for phase interpolator circuit block  108 . 
     Phase interpolator circuit block  108  may include one or multiple component phase interpolator circuits. For example, phase interpolator circuit block  108  can include 1, 2, 4, or 8 component phase interpolator circuits. In an embodiment in which phase interpolator circuit block  108  includes 8 component phase interpolator circuits, each of the 8 component phase interpolator circuits can, for example, have the circuit design disclosed in commonly-assigned U.S. patent application Ser. No. 12/496,387, filed Jul. 1, 2009 by Pan et al., which is incorporated by reference herein in its entirety. 
     According to another embodiment in which phase interpolator circuit block  108  includes 8 component phase interpolator circuits, each of the 8 component phase interpolator circuits can have one of the circuit designs disclosed in commonly-assigned U.S. patent application Ser. No. 12/537,634, filed Aug. 7, 2009 by Ho et al., which is incorporated by reference herein in its entirety. Phase interpolator circuit block  108  converts the sinusoidal output signals of the component phase interpolator circuits into square waveforms that are the 8 recovered clock signals CLK 0 , CLK 45 , CLK 90 , CLK 135 , CLK 180 , CLK 225 , CLK 270 , and CLK 315 . 
       FIG. 2  is a flow chart that illustrates the operation of CDR circuit  100 , according to an embodiment of the present invention. The operation of CDR circuit  100  is now described with reference to  FIGS. 1 and 2 . As shown in  FIG. 2 , CDR circuit  100  is initialized at step  201 . At step  202 , phase interpolator (PI) circuit block  108  generates the 8 phase recovered clock signals CLK 0 , CLK 45 , CLK 90 , CLK 135 , CLK 180 , CLK 225 , CLK 270 , and CLK 315  in response to the 8 clock signals PCLK[0:7] generated by PLL  109 . 
     An input Data signal and four of the recovered clock signals CLK 0 , CLK 90 , CLK 180 , and CLK 270  are transmitted to inputs of phase detector  101 . At step  203 , phase detector (PD) circuit  101  compares transitions in the input Data signal to the 4 phases of clock signals CLK 0 , CLK 90 , CLK 180 , and CLK 270  to generate two digital phase comparison signals UP and DN. Clock signals CLK 0 , CLK 90 , CLK 180 , and CLK 270  are offset in phase at 90° phase intervals. The UP and DN phase comparison signals are indicative of the phase differences between the Data signal and clock signals CLK 0 , CLK 90 , CLK 180 , and CLK 270 . 
     In a half-rate embodiment of CDR circuit  100 , a unit interval in the input Data signal is one-half the period of the recovered clock signals. One unit interval equals one bit period in the input Data signal. In a half-rate embodiment, phase detector  101  generates a logic high state in the UP signal and a logic low state in the DN signal in response to transitions in the input Data signal occurring less than one-half a unit interval earlier in time than the rising edges in the CLK 90  and CLK 270  clock signals. Phase detector  101  generates a logic low state in the UP signal and a logic high state in the DN signal in response to transitions in the input Data signal occurring less than one-half a unit interval later in time than the rising edges in the CLK 90  and CLK 270  clock signals. 
     According to another embodiment, CDR circuit  100  can be a full-rate CDR circuit, in which the periods of the recovered clock signals and the input Data signal are equal. Alternatively, CDR circuit  100  can be a quad rate CDR circuit, in which the period of the input Data signal equals one-quarter of the periods of the recovered clock signals. CDR  100  can also be used in embodiments having larger or smaller data rates. 
     The UP phase comparison signal is transmitted from phase detector  101  to an input of up counter circuit  103 . Up counter circuit  103  generates an up count value. The clock signal CLK 0  is transmitted to inputs of counters  103 - 105 . After each logic low-to-high transition (i.e., rising edge) of CLK 0  that occurs while the UP signal is in a logic high state, up counter  103  adds one to the up count value. Counter  103  continues to increment the up count value without resetting the up count value to zero in response to each consecutive or non-consecutive rising edge of CLK 0  that occurs while the UP signal is in a logic high state. The up count value of counter  103  only resets to zero in response to the Reset signal described below. For example, if the UP signal is high on a first rising edge of CLK 0 , low on a second rising edge of CLK 0 , and high on a third rising edge of CLK 0 , counter  103  sets the up count value to 2. 
     At step  204 , up counter  103  determines if the up count value equals a maximum count number N (e.g., 32). After the up count value equals the maximum count number N, up counter  103  causes its output signal UCT to transition from a logic low state to a logic high state. 
     Signal UCT is transmitted to a first input of count logic circuitry  106 . Count logic circuitry  106  generates Strobe and UP/DN signals. In response to a logic low-to-high transition in the UCT signal, count logic circuitry  106  drives the Strobe signal from a logic low state to a logic high state, count logic circuitry  106  causes the UP/DN signal to transition to or remain in a logic high state, and CDR circuit  100  proceeds to step  205 . 
     Up counter circuit  105  generates a Gain signal. The UP/DN, Strobe, and Gain signals are transmitted to inputs of phase interpolator control circuit  107 . Phase interpolator control circuit  107  generates the phase control signals PCS that are transmitted to inputs of phase interpolator block  108 . Phase interpolator control circuit  107  sets the logic states of the phase control signals PCS based on the logic states of the UP/DN, Strobe, and Gain signals. Phase interpolator control circuit  107  can be, for example, a state machine circuit or a controller circuit. Phase interpolator control circuit  107  can, for example, be implemented using programmable logic blocks configured to perform the functions described herein. Phase interpolator block  108  decodes the phase control signals PCS to generate decoded signals that select the phases of the recovered clock signals CLK 0 , CLK 45 , CLK 90 , CLK 135 , CLK 180 , CLK 225 , CLK 270 , and CLK 315 . 
     At step  205 , phase interpolator control circuit  107  determines if the Gain signal is in a logic high state. As an example, it is assumed that the Gain signal is in a logic low state during this particular iteration of the flow chart of  FIG. 2 , and CDR circuit  100  proceeds from step  205  to step  207 . 
     At step  207 , phase interpolator control circuit  107  changes the phase control signals PCS to logic states that cause the phases of the recovered clock signals CLK 0 , CLK 45 , CLK 90 , CLK 135 , CLK 180 , CLK 225 , CLK 270 , and CLK 315  to occur earlier in time by 1 phase interval (i.e., +1P). Phase interpolator control circuit  107  and phase interpolator block  108  shift the phases of the recovered clock signals by +1P in response to the Gain signal being in a logic low state, the UP/DN signal being in a logic high state, and a logic low-to-high transition in the Strobe signal. 1 phase interval (1P), for example, refers to the smallest phase change that phase interpolator block  108  can generate in the recovered clock signals CLK 0 , CLK 45 , CLK 90 , CLK 135 , CLK 180 , CLK 225 , CLK 270 , and CLK 315 . As a specific example, 1 phase interval (1P) may be 5.625° (i.e., 360°/64 phase steps). The examples provided herein are not intended to be limiting. 
     Phase interpolator control circuit  107  also generates a Reset signal. The Reset signal is transmitted from phase interpolator control circuit  107  to counters  103 - 105 . Phase interpolator control circuit  107  generates a logic high pulse in the Reset signal after each logic low-to-high transition in the Strobe signal. For example, phase interpolator control circuit  107  generates a logic high pulse in the Reset signal at step  207 . After the Reset signal transitions to a logic high state, up counter  103  resets the UCT signal to a logic low state, counter  104  resets the DCT signal to a logic low state, and up counter  105  resets the Gain signal to a logic low state. Count logic circuitry  106  resets the Strobe signal to a logic low state in response to a logic high-to-low transition in the UCT or DCT signals. 
     At step  202 , phase interpolator block  108  shifts the phases of the recovered clock signals CLK 0 , CLK 45 , CLK 90 , CLK 135 , CLK 180 , CLK 225 , CLK 270 , and CLK 315  to occur earlier in time by 1P based on the change in the phase control signals PCS. The phase shifted recovered clock signals are transmitted to phase detectors  101  and  102 . 
     The DN phase comparison signal is transmitted from phase detector  101  to an input of down counter  104 . Down counter circuit  104  generates a down count value. After each rising edge of CLK 0  that occurs while the DN signal is in a logic high state, down counter  104  adds one to the down count value. Counter  104  continues incrementing the down count value without resetting the down count value to zero in response to each consecutive or non-consecutive rising edge of CLK 0  that occurs while DN is in a logic high state. The down count value of counter  104  only resets to zero in response to the Reset signal. For example, if the DN signal is high on a first rising edge of CLK 0 , low on a second rising edge of CLK 0 , and high on a third rising edge of CLK 0 , counter  104  sets the down count value to 2. 
     At step  206 , down counter  104  determines if the down count value equals the maximum count number N (e.g., 32). After the down count value equals the maximum count number N, down counter  104  causes its output signal DCT to transition from a logic low state to a logic high state. Signal DCT is transmitted to a second input of count logic circuitry  106 . In response to a logic low-to-high transition in the DCT signal, count logic circuitry  106  causes the Strobe signal to transition from a logic low state to a logic high state, and count logic circuitry  106  causes the UP/DN signal to transition to or remain in a logic low state. 
     Then at step  208 , phase interpolator control circuit  107  changes the phase control signals PCS to logic states that cause the phases of the recovered clock signals CLK 0 /CLK 45 /CLK 90 /CLK 135 /CLK 180 /CLK 225 /CLK 270 /CLK 315  to occur later in time by 1 phase interval (i.e., −1P), in response to the UP/DN signal being in a logic low state and a logic low-to-high transition in the Strobe signal. After the low-to-high transition in the Strobe signal, phase interpolator control circuit  107  generates a logic high pulse in the Reset signal at step  208 , which causes the UCT, DCT, Gain, and Strobe signals to reset to logic low states. At step  202 , phase interpolator block  108  shifts the phases of the recovered clock signals CLK 0 , CLK 45 , CLK 90 , CLK 135 , CLK 180 , CLK 225 , CLK 270 , and CLK 315  to occur later in time by −1P based on the change in the phase control signals PCS. In this embodiment, +1P equals the absolute value of −1P. 
     The input Data signal and four of the recovered clock signals CLK 45 , CLK 135 , CLK 225 , and CLK 315  are transmitted to inputs of phase detector circuit  102 . At step  218 , phase detector circuit  102  compares transitions in the input Data signal to the 4 phases of the 4 clock signals CLK 45 , CLK 135 , CLK 225 , and CLK 315  to generate digital phase comparison signal DZ. Clock signals CLK 45 , CLK 135 , CLK 225 , and CLK 315  are offset in phase at 90° phase intervals. The DZ phase comparison signal is indicative of the phase differences between the Data signal and clock signals CLK 45 , CLK 135 , CLK 225 , and CLK 315 . Phase detector circuit  102  generates a logic high state in the DZ signal when CDR circuit  100  is in or near a dead-zone. In a half-rate embodiment, CDR circuit  100  is in or near a dead-zone when the rising edges of each of the CLK 0  and CLK 180  clock signals occur more than one-quarter of a unit interval before or after the center of the sampling window of the input Data signal, e.g., between −0.25 unit interval (UI) and 0.25 UI, between 0.75 UI and 1.25 UI, between 1.75 UI and 2.25 UI, etc. 
     In a half-rate embodiment, phase detector  102  generates a logic high state in the DZ signal when the mid-points of the transitions in the input Data signal (i.e., at 0 UI, 1.0 UI, 2.0 UI, etc.) do not occur between the rising edges of CLK 45  and CLK 135  or between the rising edges of CLK 225  and CLK 315 . Phase detector  102  generates a logic low state in the DZ signal in response to the mid-points of transitions in the input Data signal occurring between the rising edges of CLK 45  and CLK 135  and between the rising edges of CLK 225  and CLK 315 . 
     One or both of phase detectors  101  and  102  can be, for example, a bang-bang phase detector, such as the differential bang-bang phase detector disclosed in commonly-assigned U.S. Pat. No. 7,482,841 issued Jan. 27, 2009, which is incorporated by reference herein in its entirety. The input Data signal can be a single-ended or differential signal. 
     The DZ phase comparison signal is transmitted from the output of phase detector  102  to the input of up counter circuit  105 . Up counter circuit  105  generates an up count value. After each rising edge of CLK 0  that occurs while the DZ signal is in a logic high state, up counter  105  adds one to its up count value. Counter  105  continues incrementing its up count value without resetting its up count value to zero in response to each consecutive and non-consecutive rising edge of CLK 0  that occurs while DZ is in a logic high state. The up count value of counter  105  only resets to zero in response to the Reset signal. 
     At step  209 , up counter  105  continues to increase its up count value until its up count value is greater than or equal to a maximum count number M (e.g., 16). In some embodiments, counters  103 - 105  are programmable counter circuits that have programmable maximum count numbers N and M. In these embodiments, count numbers N and M can be programmed to any desired values. In some embodiments, the maximum count number M is one-half of the maximum count number N of counters  103 - 104 . 
     After the up count value of counter  105  equals or exceeds the maximum count number M, up counter  105  causes its output signal Gain to transition from a logic low to a logic high state (i.e., Gain=1) at step  210 . The Gain signal is transmitted to an input of phase interpolator control circuit  107 . At step  205 , phase interpolator control circuit  107  determines that the Gain signal is in a logic high state. 
     As discussed above, a logic low-to-high transition occurs in the Strobe signal and the UP/DN signal is in a logic high state in response to the up count value of counter  103  reaching the maximum count number N. If the Gain, UP/DN, and Strobe signals are in logic high states, CDR circuit  100  proceeds from step  205  to step  211 . At step  211 , phase interpolator control circuit  107  changes the phase control signals PCS to logic states that cause the phases of the recovered clock signals CLK 0 , CLK 45 , CLK 90 , CLK 135 , CLK 180 , CLK 225 , CLK 270 , and CLK 315  to occur earlier in time by 2 phase intervals (i.e., +2P), in response to the UP/DN, Strobe, and Gain signals being in logic high states. 2 phase intervals (+2P) may, for example, equal two times the smallest phase change that phase interpolator block  108  can generate in the recovered clock signals. 
     After the logic low-to-high transition in the Strobe signal, phase interpolator control circuit  107  generates a logic high pulse in the Reset signal at step  211 , which causes the UCT, DCT, Gain, and Strobe signals to reset to logic low states. At step  202 , phase interpolator block  108  shifts the phases of the recovered clock signals CLK 0 , CLK 45 , CLK 90 , CLK 135 , CLK 180 , CLK 225 , CLK 270 , and CLK 315  to occur earlier in time by 2 phase intervals based on the change in the phase control signals PCS. 
     Up counter  105  asserts the Gain signal after CDR circuit  100  remains in or near a dead-zone for a predefined number M of consecutive or non-consecutive clock cycles. CDR circuit  100  typically generates alternating pulses in the UP and DN signals (e.g., UP, DN, UP, DN, UP, etc.) when CDR circuit  100  is stuck in the dead-zone. In a half-rate embodiment, the dead-zone occurs when the rising edges in the CLK 0  and CLK 180  signals occur near 0 UI, 1.0 UI, 2.0 UI, etc. 
     CDR circuit  100  increases the phases of the recovered clock signals by a larger phase shift (e.g., by +2P) in response to logic high pulses in the UCT and Gain signals. CDR circuit  100  decreases the phases of the recovered clock signals by a smaller phase shift (e.g., by −1P) in response to logic high pulses in the DCT and Gain signals. Thus, when CDR circuit  100  is in or near a dead-zone, CDR circuit  100  generates an unbalanced gain in the phases of the recovered clock signals that shifts the rising edges of CLK 0  and CLK 180  out of the dead-zone and into the sampling window in response to the Gain signal. 
     For example, if CDR circuit  100  is generating alternating UP and DN pulses as a result of being stuck in a dead-zone, phase interpolator block  108  generates alternating phase shifts of +2P and −1P in the recovered clock signals that cause the phases of the recovered clock signals to shift earlier in time by 1P for every 2 logic high pulses of the Strobe signal. As a result, the CLK 0  and CLK 180  signals shift out of the dead-zone and into the sampling windows of the Data signal. Subsequently, the Gain signal is de-asserted and phase interpolator block  108  generates equal phase shifts of +1P and −1P in the recovered clock signals, as described above. 
     In other embodiments, CDR circuit  100  increases the phases of the recovered clock signals by an amount other than +2P in response to logic high pulses in the UCT and Gain signals. For example, CDR circuit  100  can increase the phases of the recovered clock signals by +1.5P, +1.75P, +2.25P, or +2.5P in response to logic high pulses in the UCT and Gain signals. 
       FIG. 3A  is a timing diagram that illustrates an example of an ideal timing relationship between the input Data signal and the recovered clock signals, according to an embodiment of the present invention. The waveforms shown in  FIGS. 3A-3F  represent examples of the input Data signal. The upward pointing arrows in  FIGS. 3A-3F  represent the rising edges of the recovered clock signals generated by phase interpolator block  108 . In  FIGS. 3A-3F , UI represents a unit interval in the input Data signal. 
     In an embodiment, clock signals CLK 0  and CLK 180  are used to sample the input Data signal. In this embodiment, the rising edges of clock signals CLK 0  and CLK 180  ideally occur at the center of the sampling window in each unit interval (UI) of the input Data signal, as shown, for example, in  FIG. 3A . The centers of the sampling windows of the input Data signal occur at −0.50 UI, 0.50 UI, 1.50 UI, 2.50 UI, etc. When the rising edges of clock signals CLK 0  and CLK 180  occur at the centers of the sampling windows, phase detector  102  generates a logic low state in the DZ signal, and phase detector  101  dithers between generating logic high pulses in the UP and DN signals. 
       FIGS. 3B-3D  are timing diagrams that illustrate examples of timing relationships between the input Data signal and the recovered clock signals that cause phase detector  102  to generate a logic high state in the DZ signal. In each of the examples of  FIGS. 3B-3D , the rising edges of clock signal CLK 0  occur in or near the dead-zone between −0.25 UI and 0.25 UI, and the rising edges of clock signal CLK 180  occur in or near the dead-zone between 0.75 UI and 1.25 UI. 
     Also, the first state transitions in the input Data signal at 0 UI shown in the examples of  FIGS. 3B-3D  occur before the rising edges in CLK 45 , and the second state transitions in the input Data signal at 1.0 UI occur after the rising edges in CLK 135 . As a result, the phase relationships between the input Data signal and the recovered clock signals shown in  FIGS. 3B-3D  cause phase detector  102  to generate a logic high state in the DZ signal. 
     After CDR circuit  100  has been in or near the dead-zone for more than a predefined number of clock cycles as measured by counter  105 , the Gain signal is asserted, and CDR circuit  100  shifts the phases of the recovered clock signals to occur earlier in time by 2 phase intervals (i.e., +2P) in response to the UCT signal. Because CDR circuit  100  increases the phases of the recovered clock signals by a larger phase shift (i.e., +2P) in response to the UCT signal than the phase shift (i.e., −1P) that occurs in the recovered clock signals in response to the DCT signal when the Gain signal is asserted, clock signals CLK 0  and CLK 180  move away from the dead-zone and into the sampling window. 
       FIGS. 3E-3F  are timing diagrams that illustrate examples of timing relationships between the input Data signal and the recovered clock signals that cause phase detector  102  to generate a logic low state in the DZ signal. In each of the examples of  FIGS. 3E-3F , the rising edges of clock signal CLK 0  occur within the sampling window between 0.25 UI and 0.75 UI. In  FIG. 3E , the rising edge of clock signal CLK 180  occurs in the sampling window between 1.25 UI and 1.75 UI. In  FIG. 3F , the rising edge of clock signal CLK 180  occurs in the sampling window between −0.75 UI and −0.25 UI. 
     Also, the first state transitions in the input Data signal at 0 UI shown in the examples of  FIGS. 3E-3F  occur before the rising edges in CLK 45 , and the second state transitions in the input Data signal at 1.0 UI occur before the rising edges in CLK 135 . As a result, the phase relationships between the input Data signal and the recovered clock signals shown in  FIGS. 3E-3F  cause phase detector  102  to generate a logic low state in the DZ signal. 
     According to additional embodiments, the techniques described herein can be applied to delay-locked loop (DLL) circuits and to phase-locked loop (PLL) circuits. 
     CDR circuit  100  can be used as a delay-locked loop circuit by replacing the input Data signal with a periodic input reference clock signal that is transmitted to the inputs of phase detectors  101  and  102 . CDR circuit  100  can be modified to be a phase-locked loop circuit by replacing the input Data signal with a periodic input reference clock signal that is transmitted to the inputs of phase detectors  101  and  102  and by replacing phase interpolator block  108  with an oscillator circuit (e.g., a ring oscillator or an LC tank oscillator). 
       FIG. 4  is a simplified partial block diagram of a field programmable gate array (FPGA)  400  that can include aspects of the present invention. FPGA  400  is merely one example of an integrated circuit that can include features of the present invention. It should be understood that embodiments of the present invention can be used in numerous types of integrated circuits such as field programmable gate arrays (FPGAs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), programmable logic arrays (PLAs), application specific integrated circuits (ASICs), memory integrated circuits, central processing units, microprocessors, analog integrated circuits, etc. 
     FPGA  400  includes a two-dimensional array of programmable logic array blocks (or LABs)  402  that are interconnected by a network of column and row interconnect conductors of varying length and speed. LABs  402  include multiple (e.g., 10) logic elements (or LEs). 
     An LE is a programmable logic circuit block that provides for efficient implementation of user defined logic functions. An FPGA has numerous logic elements that can be configured to implement various combinatorial and sequential functions. The logic elements have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic elements in almost any desired configuration. 
     FPGA  400  also includes a distributed memory structure including random access memory (RAM) blocks of varying sizes provided throughout the array. The RAM blocks include, for example, blocks  404 , blocks  406 , and block  408 . These memory blocks can also include shift registers and first-in-first-out (FIFO) buffers. 
     FPGA  400  further includes digital signal processing (DSP) blocks  410  that can implement, for example, multipliers with add or subtract features. Input/output elements (IOEs)  412  located, in this example, around the periphery of the chip, support numerous single-ended and differential input/output standards. IOEs  412  include input and output buffers that are coupled to pads of the integrated circuit. The pads are external terminals of the FPGA die that can be used to route, for example, input signals, output signals, and supply voltages between the FPGA and one or more external devices. IOEs  412  also include clock and data recovery circuits, such as CDR circuit  100 , that receive input data signals transmitted through pads of the integrated circuit from an external source. It should be understood that FPGA  400  is described herein for illustrative purposes only and that the present invention can be implemented in many different types of integrated circuits. 
     The present invention can also be implemented in a system that has an FPGA as one of several components.  FIG. 5  shows a block diagram of an exemplary digital system  500  that can embody techniques of the present invention. System  500  can be a programmed digital computer system, digital signal processing system, specialized digital switching network, or other processing system. Moreover, such systems can be designed for a wide variety of applications such as telecommunications systems, automotive systems, control systems, consumer electronics, personal computers, Internet communications and networking, and others. Further, system  500  can be provided on a single board, on multiple boards, or within multiple enclosures. 
     System  500  includes a processing unit  502 , a memory unit  504 , and an input/output (I/O) unit  506  interconnected together by one or more buses. According to this exemplary embodiment, an FPGA  508  is embedded in processing unit  502 . FPGA  508  can serve many different purposes within the system of  FIG. 5 . FPGA  508  can, for example, be a logical building block of processing unit  502 , supporting its internal and external operations. FPGA  508  is programmed to implement the logical functions necessary to carry on its particular role in system operation. FPGA  508  can be specially coupled to memory  504  through connection  510  and to I/O unit  506  through connection  512 . 
     Processing unit  502  can direct data to an appropriate system component for processing or storage, execute a program stored in memory  504 , receive and transmit data via I/O unit  506 , or other similar functions. Processing unit  502  can be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, field programmable gate array programmed for use as a controller, network controller, or any type of processor or controller. Furthermore, in many embodiments, there is often no need for a CPU. 
     For example, instead of a CPU, one or more FPGAs  508  can control the logical operations of the system. As another example, FPGA  508  acts as a reconfigurable processor that can be reprogrammed as needed to handle a particular computing task. Alternatively, FPGA  508  can itself include an embedded microprocessor. Memory unit  504  can be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, flash memory, tape, or any other storage means, or any combination of these storage means. 
     The foregoing description of the exemplary embodiments of the present invention has been presented for the purposes of illustration and description. The foregoing description is not intended to be exhaustive or to limit the present invention to the examples disclosed herein. In some instances, features of the present invention can be employed without a corresponding use of other features as set forth. Many modifications, substitutions, and variations are possible in light of the above teachings, without departing from the scope of the present invention.