Patent Publication Number: US-10311782-B2

Title: Light-emitting diode display with reduced leakage

Description:
This application claims the benefit of provisional patent application No. 62/350,650, filed Jun. 15, 2016, which is hereby incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     This relates generally to displays, and, more particularly, to displays with pixels formed from light-emitting diodes. 
     Electronic devices often include displays. For example, cellular telephones and portable computers include displays for presenting information to users. 
     Displays such as organic light-emitting diode displays have arrays of pixels based on light-emitting diodes. In this type of display, each pixel includes a light-emitting diode and thin-film transistors for controlling application of a signal to the light-emitting diode to produce light. The thin-film transistors include drive transistors, switching transistors, and emission enabled transistors. Each drive transistor is coupled in series with a respective light-emitting diode and controls current flow through that light-emitting diode. 
     In certain circumstances, the thin-film transistors may experience undesirable current leakage. In particular, at low temperatures it may be necessary to increase the amount of current through the light-emitting diode to achieve a desired luminance level which may result in current leakage in the transistors. 
     It would therefore be desirable to be able to provide a display with improved pixels with minimized thin-film transistor leakage. 
     SUMMARY 
     A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. 
     The seven transistors of each pixel may receive control signals over three or more control lines, may receive data over a data line, may receive one or more reference voltages from respective reference voltage terminals, and may receive power from a pair of power supply terminals. The transistors may be positioned to minimize leakage. In particular, the pixels may have reduced leakage in the event that a ground voltage is lowered to account for low temperature conditions. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of an illustrative electronic device having a display in accordance with an embodiment. 
         FIG. 2  is a schematic diagram of an illustrative display in accordance with an embodiment. 
         FIG. 3  is a diagram of an illustrative pixel circuit in accordance with an embodiment. 
         FIG. 4  is a diagram of an illustrative pixel circuit with reduced T 4  and T 7  leakage in accordance with an embodiment. 
         FIG. 5  is a diagram of an illustrative pixel circuit with reduced T 3 , T 4 , and T 7  leakage in accordance with an embodiment. 
         FIG. 6  is a diagram of an illustrative pixel circuit with reduced T 3 , T 4 , and T 7  leakage in accordance with an embodiment. 
         FIG. 7  is a schematic diagram of illustrative gate driver circuitry for a display with a single reference voltage line in accordance with an embodiment. 
         FIG. 8  is a schematic diagram of illustrative gate driver circuitry for a display with dynamic reference voltage lines in accordance with an embodiment. 
         FIG. 9  is a top view of an illustrative display with a conductive mesh shorted to the ground power supply terminal in accordance with an embodiment. 
         FIG. 10  is a schematic diagram of illustrative gate driver circuitry for a display with multiple scan lines for per-transistor leakage control in accordance with an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Electronic devices may be provided with displays. A schematic diagram of an illustrative electronic device with a display is shown in  FIG. 1 . Device  10  of  FIG. 1  may be a computing device such as a laptop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular telephone, a media player, or other handheld or portable electronic device, a smaller device such as a wrist-watch device (e.g., a watch with a wrist strap), a pendant device, a headphone or earpiece device, a device embedded in eyeglasses or other equipment worn on a user&#39;s head, or other wearable or miniature device, a television, a computer display that does not contain an embedded computer, a gaming device, a navigation device, an embedded system such as a system in which electronic equipment with a display is mounted in a kiosk or automobile, equipment that implements the functionality of two or more of these devices, or other electronic equipment. 
     As shown in  FIG. 1 , electronic device  10  may have control circuitry  16 . Control circuitry  16  may include storage and processing circuitry for supporting the operation of device  10 . The storage and processing circuitry may include storage such as hard disk drive storage, nonvolatile memory (e.g., flash memory or other electrically-programmable-read-only memory configured to form a solid state drive), volatile memory (e.g., static or dynamic random-access-memory), etc. Processing circuitry in control circuitry  16  may be used to control the operation of device  10 . The processing circuitry may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application specific integrated circuits, etc. 
     Input-output circuitry in device  10  such as input-output devices  18  may be used to allow data to be supplied to device  10  and to allow data to be provided from device  10  to external devices. Input-output devices  18  may include buttons, joysticks, scrolling wheels, touch pads, key pads, keyboards, microphones, speakers, tone generators, vibrators, cameras, sensors, light-emitting diodes and other status indicators, data ports, etc. A user can control the operation of device  10  by supplying commands through input-output devices  18  and may receive status information and other output from device  10  using the output resources of input-output devices  18 . 
     Input-output devices  18  may include one or more displays such as display  14 . Display  14  may be a touch screen display that includes a touch sensor for gathering touch input from a user or display  14  may be insensitive to touch. A touch sensor for display  14  may be based on an array of capacitive touch sensor electrodes, acoustic touch sensor structures, resistive touch components, force-based touch sensor structures, a light-based touch sensor, or other suitable touch sensor arrangements. 
     Control circuitry  16  may be used to run software on device  10  such as operating system code and applications. During operation of device  10 , the software running on control circuitry  16  may display images on display  14 . 
     Display  14  may be an organic light-emitting diode display, a display formed from an array of discrete light-emitting diodes each formed from a crystalline semiconductor die, or any other suitable type of display. Configurations in which the pixels of display  14  include light-emitting diodes are sometimes described herein as an example. This is, however, merely illustrative. Any suitable type of display may be used for device  10 , if desired. 
     Input-output devices  18  may also include a temperature sensor. During operation of displays such as organic light-emitting diode display  14 , temperature changes can lead to changes in the properties of the display pixels. These changes can cause undesired artifacts if not corrected. For example, as a result of the increased current required to operate light-emitting diodes at low temperatures, transistor leakage may occur. To address these issues, a temperature sensor may be included in the electronic device. The temperature sensor may be used to estimate the temperature of the display in real time. 
       FIG. 2  is a diagram of an illustrative display. As shown in  FIG. 2 , display  14  may include layers such as substrate layer  26 . Substrate layers such as layer  26  may be formed from rectangular planar layers of material or layers of material with other shapes (e.g., circular shapes or other shapes with one or more curved and/or straight edges). The substrate layers of display  14  may include glass layers, polymer layers, composite films that include polymer and inorganic materials, metallic foils, etc. 
     Display  14  may have an array of pixels  22  for displaying images for a user such as pixel array  28 . Pixels  22  in array  28  may be arranged in rows and columns. The edges of array  28  may be straight or curved (i.e., each row of pixels  22  and/or each column of pixels  22  in array  28  may have the same length or may have a different length). There may be any suitable number of rows and columns in array  28  (e.g., ten or more, one hundred or more, or one thousand or more, etc.). Display  14  may include pixels  22  of different colors. As an example, display  14  may include red pixels, green pixels, and blue pixels. If desired, a backlight unit may provide backlight illumination for display  14 . 
     Display driver circuitry  20  may be used to control the operation of pixels  28 . Display driver circuitry  20  may be formed from integrated circuits, thin-film transistor circuits, and/or other suitable circuitry. Illustrative display driver circuitry  20  of  FIG. 2  includes display driver circuitry  20 A and additional display driver circuitry such as gate driver circuitry  20 B. Gate driver circuitry  20 B may be formed along one or more edges of display  14 . For example, gate driver circuitry  20 B may be arranged along the left and right sides of display  14  as shown in  FIG. 2 . 
     As shown in  FIG. 2 , display driver circuitry  20 A (e.g., one or more display driver integrated circuits, thin-film transistor circuitry, etc.) may contain communications circuitry for communicating with system control circuitry over signal path  24 . Path  24  may be formed from traces on a flexible printed circuit or other cable. The control circuitry may be located on one or more printed circuits in electronic device  10 . During operation, the control circuitry (e.g., control circuitry  16  of  FIG. 1 ) may supply circuitry such as a display driver integrated circuit in circuitry  20  with image data for images to be displayed on display  14 . Display driver circuitry  20 A of  FIG. 2  is located at the top of display  14 . This is merely illustrative. Display driver circuitry  20 A may be located at both the top and bottom of display  14  or in other portions of device  10 . 
     To display the images on pixels  22 , display driver circuitry  20 A may supply corresponding image data to data lines D while issuing control signals to supporting display driver circuitry such as gate driver circuitry  20 B over signal paths  30 . With the illustrative arrangement of  FIG. 2 , data lines D run vertically through display  14  and are associated with respective columns of pixels  22 . 
     Gate driver circuitry  20 B (sometimes referred to as gate line driver circuitry or horizontal control signal circuitry) may be implemented using one or more integrated circuits and/or may be implemented using thin-film transistor circuitry on substrate  26 . Horizontal control lines G (sometimes referred to as gate lines, scan lines, emission control lines, etc.) run horizontally through display  14 . Each gate line G is associated with a respective row of pixels  22 . If desired, there may be multiple horizontal control lines such as gate lines G associated with each row of pixels. Individually controlled and/or global signal paths in display  14  may also be used to distribute other signals (e.g., power supply signals, etc.). 
     Gate driver circuitry  20 B may assert control signals on the gate lines G in display  14 . For example, gate driver circuitry  20 B may receive clock signals and other control signals from circuitry  20 A on paths  30  and may, in response to the received signals, assert a gate line signal on gate lines G in sequence, starting with the gate line signal G in the first row of pixels  22  in array  28 . As each gate line is asserted, data from data lines D may be loaded into a corresponding row of pixels. In this way, control circuitry such as display driver circuitry  20 A and  20 B may provide pixels  22  with signals that direct pixels  22  to display a desired image on display  14 . Each pixel  22  may have a light-emitting diode and circuitry (e.g., thin-film circuitry on substrate  26 ) that responds to the control and data signals from display driver circuitry  20 . 
     An illustrative pixel circuit of the type that may be used for each pixel  22  in array  28  is shown in  FIG. 3 . In the example of  FIG. 3 , pixel circuit  22  has seven transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7  and one capacitor Cst, so pixel circuit  22  may sometimes be referred to as a 7T1C pixel circuit. Other numbers of transistors and capacitors may be used in pixels  22  if desired. The transistors may be p-channel transistors (as shown in  FIG. 3 ) and/or may be n-channel transistors or other types of transistors. The active regions of thin-film transistors for pixel circuit  22  and other portions of display  14  may be formed from silicon (e.g., polysilicon channel regions), semiconducting oxides (e.g., indium gallium zinc oxide channel regions), or other suitable semiconductor thin-film layers. 
     As shown in  FIG. 3 , pixel circuit  22  includes light-emitting diode  44  (e.g., an organic light-emitting diode, a crystalline micro-light-emitting diode die, etc.). Light-emitting diode  44  may emit light  46  in proportion to the amount of current I that is driven through light-emitting diode  44  by transistor T 1 . Transistor T 5 , Transistor T 1 , Transistor T 6 , and light-emitting diode  44  may be coupled in series between respective power supply terminals (see, e.g., positive power supply terminal  40  (ELVDD) and ground power supply terminal  42  (ELVSS). Transistor T 1  may have a source terminal (S) coupled to positive power supply terminal  40 , a drain terminal (D) coupled to node N 2 , and a gate terminal coupled to node N 1 . The terms “source” and “drain” terminals of a transistor can sometimes be used interchangeably and may therefore be referred to herein as “source-drain” terminals. The voltage on node N 1  at the gate of transistor T 1  controls the amount of current I that is produced by transistor T 1 . This current is driven through light-emitting diode  44 , so transistor T 1  may sometimes be referred to as a drive transistor. 
     Transistors T 5  and T 6  can be turned off to interrupt current flow between transistor T 1  and diode  44  and may be turned on to enable current flow between transistor T 1  and diode  44 . Emission enable control signal EM is applied to the gates of transistors T 5  and T 6 . During operation, transistors T 5  and T 6  are controlled by emission enable control signal EM and are sometimes referred to as emission transistors or emission enable transistors. Control signals GW and GI, which may sometimes be referred to as switching transistor control signals, are applied to the gates of switching transistors T 2 , T 3 , T 4 , and T 7  and control the operation of transistors T 2 , T 3 , T 4 , and T 7 . In particular, control signal GW is used to control transistors T 2  and T 3 , while control signal GI is used to control transistors T 4  and T 7 . The capacitor Cst of pixel circuit  22  may be used for data storage. Pixel  22  may also include reference voltage terminal  38  (VINI). Reference voltage terminal  38  may be used to supply a reference voltage (e.g., VINI may be approximately −3.4 Volts or any other desired voltage). 
     Operation of pixel  22  may be generally have two primary phases: a data writing phase and an emission phase. During the data writing phase, data may be loaded from data lines D (labeled as DATA in  FIG. 3 ) to node N 1 . The data may be a data voltage that is loaded to Node  1  by turning on transistors T 2 , T 1 , and T 3 . After the data voltage has been loaded into pixel  22 , display driver circuitry  20  places pixel  22  in its emission state. During the emission state, the value of the data voltage on node N 1  controls the state of drive transistor T 1  and thereby controls the amount of light  46  emitted by light-emitting diode  44 . 
     It should be noted that manufacturing variations and variations in operating conditions can cause the threshold voltages of drive transistor T 1  to vary. This may cause pixel brightness fluctuations which may give rise to undesired visible artifacts on a display. To help reduce visible artifacts, display  14  may employ any desired threshold voltage compensation techniques to compensate for threshold voltage variation in drive transistor T 1 . 
     At low temperatures, it may be necessary to increase the amount of current through the light-emitting diode to achieve a desired luminance level. To compensate for this effect, the voltage of ground power supply terminal  42  (ELVSS) may be adjusted based on temperature. For example, at room temperature, ELVSS may be approximately −5.0 Volts. If the temperature drops to freezing (32° F., 0° C.), however, ELVSS may be dropped to approximately −8.0 Volts. As a consequence for the reduction of ELVSS, some of the transistors in pixel  22  (e.g., T 3  and T 7 ) may experience a higher voltage drop across the transistors and be more susceptible to leakage. The leakage may cause light-emitting diode  44  to emit undesirably high levels of light. Additional undesirable leakage may occur due to the voltage drop across transistor T 4 . The aforementioned examples of ELVSS voltage levels were merely illustrative, and any ELVSS voltage level may be used at any desired temperature. 
     There are a number of ways to reduce leakage in pixel  22  and avoid undesired artifacts.  FIG. 4  shows an illustrative pixel circuit with reduced leakage for transistors T 4  and T 7 . In  FIG. 3 , transistor T 4  has a first source-drain terminal coupled to N 1 , a second source-drain terminal coupled to VINI, and a gate terminal coupled to GI, whereas in  FIG. 4 , transistor T 4  has a first source-drain terminal coupled to N 1 , a second source-drain terminal coupled to VINI- 1 , and a gate terminal coupled to GI. Similarly, In  FIG. 3 , transistor T 7  has a first source-drain terminal coupled to light-emitting diode  44 , a second source-drain terminal coupled to VINI, and a gate terminal coupled to GI, whereas in  FIG. 4 , transistor T 7  has a first source-drain terminal coupled to light-emitting diode  44 , a second source-drain terminal coupled to AVSS, and a gate terminal coupled to GI. Importantly, in  FIGS. 3 , T 4  and T 7  are both coupled to the same reference voltage VINI, while in  FIGS. 4 , T 4  and T 7  are coupled to different reference voltages VINI- 1  and AVSS. Using two reference voltage terminals  38 - 1  and  38 - 2  allows for independent control of leakage through transistors T 4  and T 7  which reduces leakage in the transistors. 
     Another pixel circuit for reduced leakage is shown in  FIG. 5 . The structure of pixel  22  in  FIG. 5  enables reduced leakage for transistors T 3 , T 4 , and T 7 . In particular, in  FIGS. 3, 4, and 5 , T 3  has a first source-drain terminal coupled to node N 1  and a gate terminal coupled to GW. However, in  FIGS. 3 and 4 , T 3  has a second source-drain terminal coupled to node N 2  (between T 1  and T 6 ), while in  FIG. 5  T 3  has a second source-drain terminal coupled to N 3  (between T 1  and T 5 ). Similarly, in  FIGS. 3, 4, and 5 , T 2  has a first source-drain terminal coupled to DATA and a gate terminal coupled to GW. However, in  FIGS. 3 and 4 , T 2  has a second source-drain terminal coupled to node N 3  (between T 1  and T 5 ), while in  FIG. 5  T 2  has a second source-drain terminal coupled to N 2  (between T 1  and T 6 ). Positioning T 3  in this manner eliminates the T 3  leakage experienced in  FIGS. 3 and 4  without affecting the data voltage writing. 
       FIG. 5  shows T 4  coupled to VINI- 1  and T 7  coupled to AVSS. As discussed in connection with  FIG. 4 , this may reduce leakage in transistors T 4  and T 7 . However, this example is merely illustrative, and T 4  and T 7  may optionally be both connected to a single reference voltage terminal VINI, as shown in  FIG. 3 , while still using the T 3  position showed in  FIG. 5 . 
       FIG. 6  shows another pixel circuit with reduced leakage for transistors T 3 , T 4 , and T 7 . In  FIGS. 3, 4, and 6 , T 3  has a first source-drain terminal coupled to N 1 , and a gate terminal coupled to GW. However, in  FIGS. 3 and 4 , T 3  has a second source-drain terminal coupled to N 2 , while in  FIG. 6 , T 3  has a second source-drain terminal coupled to T 1 , which has a split structure. An enlarged version of region  60  (showing the relationship between T 1  and T 3 ) is included in  FIG. 6 . As shown, T 1  is split such that there is a first gate terminal for a first transistor portion and a second gate terminal for a second transistor portion. Both of the gate terminals are coupled to node  1 . T 1  has an additional terminal (node  4 ) halfway between T 1  (i.e., node  4  is interposed between the first transistor portion and the second transistor portion). Because T 1  is split into a dual gate transistor structure, the voltage drop across the source and drain of each transistor portion is (approximately) half as much as if a single gate transistor structure was used. Thus, by coupling the second source-drain terminal of T 3  in between the two transistor portions of T 1  at node  4 , the voltage drop of T 3  is lessened and leakage of T 3  is reduced. 
     An additional benefit of the pixel circuit shown in T 3  is that the reduced leakage of T 3  may enable T 3  to be implemented as a single gate thin-film transistor (whereas in  FIG. 3 , T 3  may be implemented as a dual gate thin-film transistor). The space saved by making T 3  a single gate thin-film transistor may be used to increase the area of the storage capacitor C ST . Yet another advantage of the structure shown in  FIG. 6  is that faster threshold voltage sampling may be achieved due to a smaller effective T 1  length. As previously mentioned, T 1  may undergo threshold voltage compensation to ensure adequate display performance. Part of the threshold voltage compensation process may include sampling the threshold voltage of T 1 . In  FIG. 6 , the channel length of T 1  may be shorter than the channel length of T 1  in  FIG. 3 , enabling faster threshold voltage sampling in the pixel circuit of  FIG. 6  when compared to pixel circuit of  FIG. 3 . 
       FIG. 6  shows T 4  coupled to VINI- 1  and T 7  coupled to AVSS. As discussed in connection with  FIG. 4 , this may reduce leakage in transistors T 4  and T 7 . However, this example is merely illustrative, and T 4  and T 7  may optionally be both connected to a single reference voltage terminal VINI, as shown in  FIG. 3 , while still using the T 3  position showed in  FIG. 6 . 
     There are a number of other ways to reduce transistor leakage in the display pixels. As discussed in connection with  FIG. 4 , one way to reduce leakage for transistors T 4  and T 7  is to include separate reference voltage terminals  38 - 1  and  38 - 2 . However, another way to reduce leakage for transistors T 4  and T 7  is to adjust the value of VINI using the gate driver circuitry.  FIG. 7  shows illustrative gate driver circuitry  20 B with a plurality of gate integrated panels (GIPs). As shown, one way to provide reference voltage VINI to the pixels in active area  29  (AA) of display  14  is to have a single line  70 . Reference voltage line  70  may be configured to supply a reference voltage VINI to display pixels in the active area of the display via lines  74 . In order to enable dynamic VINI control and reduce leakage in transistors T 4  and T 7 , gate driver circuitry of the type shown in  FIG. 8  may be used. 
     As shown in  FIG. 8 , two reference voltage lines  70 - 1  and  70 - 2  may be provided. The reference voltage lines may have switches  72  coupled to each line  74 . In this way the gate-integrated panels (GIPs) can provide two reference voltages (VINI- 1  on line  70 - 1  and AVSS on line  70 - 2 ). The switches can then be controlled to determine which reference voltage will actually be coupled to line  74  and supplied to the pixel. Thus, even though there is only a single VINI input per pixel in the active area, the VINI value can be switched between VINI- 1  and AVSS. This allows for control of leakage in transistors T 4  and T 7 . Switches  72  may be implemented using thin-film transistors or other desired methods. 
     As previously discussed, transistor leakage can become particularly prevalent if the ground power supply terminal (ELVSS) has to be lowered to enable increased luminance in the display. One way to help avoid this problem is to therefore enable increased luminance through methods aside from lowering the ground voltage level. An example of this is shown in  FIG. 9 . As shown, ELVSS (sometimes referred to as the cathode) may be formed from metal layers  90  which are positioned on opposing sides of active area  29 . The metal layers  90  may be shorted to a thin conductive layer  92  that overlaps the active area. In some cases, conductive layer  92  may be positioned over the display pixels such that conductive layer  92  needs to be transparent (in order to not obscure the displayed image). Accordingly, in some embodiments, conductive layer  92  may be formed from a transparent conductive material (e.g., indium tin oxide). Conductive layer  92  may have any desired thickness (e.g., greater than 100 microns, less than 100 microns, less than 10 microns, less than 1 micron, less than 1000 Å, less than 100 Å, less than 50 Å, etc.). 
     Conductive layer  92  may experience a large voltage drop due to the large currents it is exposed to and the (relatively) high resistance of the conductive sheet. In order to reduce the resistance of the cathode, a conductive mesh  94  may be shorted to conductive sheet  92 . Conductive mesh  94  may lower the resistance of the cathode, therefore reducing the voltage drop across the cathode, thereby enabling a higher light-emitting diode luminance without reduction of the ground voltage value. The conductive mesh may be formed from any desired material (e.g., silver nanowire) and may have any desired thickness. The positive power supply terminal (ELVDD)  98  is also shown in  FIG. 9 . 
     Finally, a schematic diagram of illustrative gate driver circuitry for a display with multiple scan lines for per-transistor leakage control is shown in  FIG. 10 .  FIG. 4  described how independent control of reference voltages (VINI- 1  and AVSS) for respective transistors may reduce transistor leakage. Similarly, switching transistor control signals GW and GI may be split into multiple different switching transistor control signals for per-transistor leakage control. An example of this is shown in  FIG. 10  where there are three separate control signals (GW, GW 2 , and GI) instead of two as shown in  FIGS. 3-6 . Take as an example the control signal GW. In  FIG. 3 , the same control signal GW is applied to both T 2  and T 3 . In  FIG. 10 , two GW control signals (GW and GW 2 ) are provided instead of one. Control signal GW may be coupled to the gate terminal of T 2  while control signal GW 2  may be coupled to the gate terminal of T 3  (as an example). This way, the off-biasing point of transistors T 2  and T 3  can be independently controlled, allowing for reduced leakage. Although not shown in  FIG. 10 , control signal GI could similarly split into a first signal that controls T 4  and a second signal that controls T 7 . 
     In various embodiments, a display pixel may include a first power supply terminal, a second power supply terminal, an organic light-emitting diode, a first transistor that is a drive transistor, a second transistor that has a first-source drain terminal coupled to a data line and a second source-drain terminal coupled between the drive transistor and the organic light-emitting diode, a third transistor that has a first-source drain terminal coupled between the drive transistor and the first power supply terminal. The drive transistor may supply a current to the organic light-emitting diode, and the drive transistor and the organic light-emitting diode may be coupled in series between the first and second power supply terminals. 
     The drive transistor, the second transistor, and the third transistor may be asserted to load data onto a storage capacitor. The first power supply terminal may be a positive power supply terminal, and the second power supply terminal may be a ground power supply terminal. The organic light-emitting diode may be coupled to the ground power supply terminal. The display pixel may also include a first enable transistor coupled between the organic light-emitting diode and the drive transistor and a second emission enable transistor coupled between the positive power supply terminal and the drive transistor. The display pixel may also include a reference voltage terminal coupled to the storage capacitor. The display pixel may also include a fourth transistor that is coupled between the reference voltage terminal and the storage capacitor. 
     The display pixel may also include a fifth transistor. The fifth transistor may have a first source-drain terminal that is coupled between the fourth transistor and the reference voltage terminal and a second source-drain terminal that is coupled between the first emission enable transistor and the organic light-emitting diode. The reference voltage terminal may be configured to provide a first reference voltage to the fourth transistor, and the reference voltage terminal may be configured to provide a second reference voltage that is different than the first reference voltage to the fifth transistor. The fifth transistor may have a first source-drain terminal that is coupled to an additional reference voltage terminal that is different than the reference voltage terminal, and the fifth transistor may have a second source-drain terminal that is coupled between the first emission enable transistor and the organic light-emitting diode. 
     In various embodiments, a display pixel may include a first power supply terminal, a second power supply terminal, an organic light-emitting diode, a first transistor that is a drive transistor, a second transistor that has a first-source drain terminal coupled to a data line and a second source-drain terminal coupled between the drive transistor and the first power supply terminal, and a third transistor that has a first-source drain terminal coupled between the first and second transistor portions of the drive transistor. The drive transistor may supply a current to the organic light-emitting diode. The drive transistor and the organic light-emitting diode may be coupled in series between the first and second power supply terminals, and the drive transistor may be a dual gate transistor structure with first and second gates coupled to respective first and second transistor portions. 
     In various embodiments, an electronic device may include a display. The display may include a plurality of display pixels. Each display pixel may include a first power supply terminal, a second power supply terminal, an organic light-emitting diode, a first transistor that is a drive transistor that supplies a current to the organic light-emitting diode, a first reference voltage terminal that is configured to supply a first reference voltage to a second transistor, and a second reference voltage terminal that is configured to supply a second reference voltage that is different than the first reference voltage to a third transistor. The display may also include a conductive layer that forms the second power supply terminal and a conductive mesh that is shorted to the conductive layer. 
     The foregoing is merely illustrative and various modifications can be made by those skilled in the art without departing from the scope and spirit of the described embodiments. The foregoing embodiments may be implemented individually or in any combination.