Patent Publication Number: US-9418792-B2

Title: Multilayer ceramic capacitor

Description:
This application is the U.S. National Phase under 35 U.S.C. §371 of International Application PCT/JP2013/056091, filed Mar. 6, 2013, which claims priority to Japanese Patent Applications No. 2012-050106, filed Mar. 7, 2012. The International Application was published under PCT Article 21(2) in a language other than English. 
     TECHNICAL FIELD 
     The present invention relates to a multilayer ceramic capacitor having a structure of internal electrode layers laminated alternately with dielectric layers. 
     PRIOR ART 
     The demand for smaller, larger-capacity multilayer ceramic capacitors remains strong and to meet this demand, the internal electrode layer and dielectric layer must be made even thinner (refer to Patent Literature 1). 
     In light of the fact that the internal electrode layer of the multilayer ceramic capacitor is constituted by mutually bonded metal grains of various sizes, while the dielectric layer is constituted by mutually bonded ceramic grains of various sizes, in principle the internal electrode layer and dielectric layer can be made thinner by using finer metal grains and ceramic grains as the material grains for both. 
     On the other hand, ceramic grains that are classified as strong dielectrics, such as barium titanate grains, are generally used as the material grains for the dielectric layer; with such strong dielectric ceramic grains, however, a smaller grain size means a lower specific dielectric constant because of the sizing effect. In other words, using finer ceramic grains as the material grains for the dielectric layer with the purpose of making the dielectric layer thinner may cause the capacitance and capacity vs. temperature characteristics of the multilayer ceramic capacitor to drop due to a drop in the dielectric constant of the dielectric layer. 
     PRIOR ART LITERATURE 
     Patent Literature 
     Patent Literature 1: Japanese Patent Laid-open No. 2007-258566 
     SUMMARY OF THE INVENTION 
     Problems to Be Solved by the Invention 
     The object of the present invention is to provide a multilayer ceramic capacitor whose capacitance and capacity vs. temperature characteristics will not worsen even when the internal electrode layer is made thinner. 
     Means for Solving the Problems 
     To achieve the aforementioned object, the present invention provides a multilayer ceramic capacitor having a structure of internal electrode layers constituted by mutually bonded metal grains of various sizes being laminated alternately with dielectric layers constituted by mutually bonded ceramic grains of various sizes, wherein such multilayer ceramic capacitor is characterized in that the ceramic grains constituting the dielectric layer include coarse ceramic grains whose coarse grain size Dcoa meets the condition “Tmin≦Dcoa≦Tmax,” where Tmax represents the maximum thickness of the dielectric layer and Tmin represents the minimum thickness of the dielectric layer. 
     Effects of the Invention 
     According to the present invention, the capacitance and capacity vs. temperature characteristics will not worsen even when the internal electrode layer is made thinner, because the ceramic grains constituting the dielectric layer include coarse ceramic grains whose coarse grain size Dcoa meets the condition “Tmin representing the minimum thickness of the dielectric layer≦Dcoa≦Tmax representing the maximum thickness of the dielectric layer.” 
     The aforementioned and other objects, constitutions and characteristics, and operations and effects, of the present invention are made clear by the explanations below and drawings attached hereto. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a longitudinal section view of a multilayer ceramic capacitor. 
         FIG. 2  is an enlarged view of part A of the multilayer ceramic capacitor shown in  FIG. 1 . 
         FIGS. 3  (A) to  3  (F) are drawings explaining a manufacturing method for the multilayer ceramic capacitor shown in  FIG. 1 . 
         FIG. 4  is a table showing the specifications and characteristics of Samples 1 to 17. 
     
    
    
     MODE FOR CARRYING OUT THE INVENTION 
     {Overall Structure of Multilayer Ceramic Capacitor} 
       FIG. 1  is a longitudinal section view of a multilayer ceramic capacitor  10 . This multilayer ceramic capacitor  10  has a capacitor body  11  of roughly rectangular solid shape whose reference dimensions of length, width, and height satisfy the relationship of “Length&gt;Width=Height” or “Length&gt;Width&gt;Height,” and a pair of external electrodes  12  provided on both longitudinal ends of the capacitor body  11 . 
     The capacitor body  11  has a structure of internal electrode layers  13  laminated alternately with dielectric layers  14  in the height direction, where a margin (not indicated by any symbol) constituted by only dielectric layers  14  laminated together is present at the top part and also at the bottom part in the height direction. Each internal electrode layer  13  has a roughly rectangular shape whose length and width are smaller than the length and width of the capacitor body  11 , respectively, and in  FIG. 1 , the left edge of an odd-numbered internal electrode layer  13  from the top is electrically connected to the left external electrode  12 , while the right edge of an even-numbered internal electrode layer  13  from the top is electrically connected to the right external electrode  12 . Note that, while a total of 26 internal electrode layers  13  are shown in  FIG. 1  for the sake of illustrative convenience, the smaller, larger-capacity multilayer ceramic capacitor  10  can have 100 internal electrode layers  13  or more. 
     Each external electrode  12 , while not illustrated, has a two-layer structure comprised of a base layer of nickel, copper, etc., and a surface layer of tin, palladium, gold, zinc, etc., formed on the surface of the base layer, or a three-layer structure comprised of the aforementioned base layer and surface layer with an intermediate layer of platinum, palladium, gold, copper, nickel, etc., inserted in between. 
     {Detailed Structure of Internal Electrode Layer and Dielectric Layer} 
       FIG. 2  is an enlarged view of part A of the multilayer ceramic capacitor  10  shown in  FIG. 1 . Note that  FIG. 2  is based on an image obtained by observing a longitudinal cross-section of Sample 1 mentioned later, corresponding to  FIG. 1 , with a scanning electron microscope. 
     Each internal electrode layer  13  is constituted by mutually bonded metal grains of various sizes, while each dielectric layer  14  is constituted by mutually bonded ceramic grains SP of various sizes. The metal grains constituting each internal electrode  13  consist of grains of at least one type selected from nickel, copper, palladium and silver, while the ceramic grains SP constituting each dielectric layer  14  consist of strong dielectric grains containing at least one of barium titanate, strontium titanate, calcium titanate, magnesium titanate, calcium zirconate, calcium zirconate titanate, barium zirconate, and titanium oxide. 
     In addition, the top interface IFu and bottom interface IFd of each dielectric layer  14  have wave-like undulations, where “Undulation of top interface IFu (height gap ΔTu)&gt;Undulation of bottom interface IFd (height gap ΔTd).” The reason that these undulations manifest is explained in {Manufacturing Method for Multilayer Ceramic Capacitor} later on. 
     As shown in  FIG. 2 , the ceramic grains SP constituting each dielectric layer  14  include at least one coarse ceramic grain SPr whose coarse grain size Dcoa meets the condition “Tmin ≦Dcoa≦Tmax,” where Tmax represents the maximum thickness of the dielectric layer  14  and Tmin represents the minimum thickness of the dielectric layer  14 . If the coarse grain size Dcoa of the coarse ceramic grain SPr is smaller than the minimum thickness Tmin, prevention of the worsening of capacitance and capacity vs. temperature characteristics, which is the object to be achieved, becomes difficult. On the other hand, since it is possible for the maximum thickness Tmax to be roughly the same as the coarse grain size Dcoa in a certain mode, as is the case with the coarse ceramic grain SPr shown in the top left of  FIG. 2 , the maximum thickness Tmax represents the upper limit of the coarse grain size Dcoa of the coarse ceramic grain SPr. 
     Furthermore, the percentage of the coarse ceramic grains SPr included in the ceramic grains SP constituting each dielectric layer  14  is inside a range of 25 to 50 percent by volume, or preferably inside a range of 30 to 40 percent by volume. If the percentage of the coarse ceramic grains SPr included in the ceramic grains SP constituting each dielectric layer  14  is less than 25 percent by volume, prevention of the worsening of capacitance and capacity vs. temperature characteristics, which is the object to be achieved, becomes difficult. If the percentage of the coarse ceramic grains SPr included in the ceramic grains SP constituting each dielectric layer  14  exceeds 50 percent by volume, on the other hand, keeping the occurrence of short-circuiting low becomes difficult. Additionally when the percentage of the coarse ceramic grains SPr included in the ceramic grains SP constituting each dielectric layer  14  exceeds 50 percent by volume, it becomes difficult to make each dielectric layer  14  thinner, or specifically to reduce the average thickness Tabe obtained by the formula “(Tmax+Tmin)/2” or “Tmin+[(ΔTu+ΔTd)/2].” 
     Furthermore, the average grain size Dabe of the ceramic grains SP (including coarse ceramic grains SPr) constituting each dielectric layer  14  meets the condition “0.15×Tabe≦Dabe≦0.3×Tabe,” or preferably the condition “0.18×Tabe≦Dabe≦0.25×Tabe,” when the average thickness of each dielectric layer  14  is given by Tabe. If the average grain size Dabe of the ceramic grains SP constituting each electric layer  14  is smaller than 0.15×Tabe, prevention of the worsening of capacitance and capacity vs. temperature characteristics, which is the object to be achieved, becomes difficult. If the average grain size Dabe of the ceramic grains SP constituting each electric layer  14  exceeds 0.3×Tabe, on the other hand, keeping the occurrence of short-circuiting low becomes difficult. 
     {Manufacturing Method for Multilayer Ceramic Capacitor} 
       FIGS. 3  (A) to  3  (F) are drawings explaining a manufacturing method for the multilayer ceramic capacitor  10  shown in  FIG. 1 . The first step of manufacturing is to prepare a ceramic slurry and electrode paste. The ceramic slurry contains at least ceramic grains, solvent and binder, plus various additives as necessary. The electrode paste contains at least metal grains, solvent, and binder, plus various additives as necessary. 
     The ceramic grains contained in the ceramic slurry consist of strong dielectric grains containing at least one of barium titanate, strontium titanate, calcium titanate, magnesium titanate, calcium zirconate, calcium zirconate titanate, barium zirconate and titanium oxide, and have a specified d50 (median size) and grain size distribution. On the other hand, the solvent consists of at least one of methanol, ethanol, propanol, butanol, ethyl acetate, butyl acetate, toluene, and xylene, while the binder consists of at least one of polyvinyl butyral, acrylic resin, urethane resin, and polyvinyl acetal. For the various additives, dispersant, plasticizer, and leveling agent can be used, among others, where the types of dispersant that can be used include cationic dispersant, anionic dispersant, nonionic dispersant, amphoteric surface active agent, and polymeric dispersant, while the types of plasticizer and leveling agent are not limited in any way and any known plasticizer or leveling agent can be used. 
     The metal grains included in the electrode paste consist of grains of at least one type selected from nickel, copper, palladium, and silver, and have a specified d50 (median size) and grain size distribution. The solvent consists of at least one of terpineol (α, β, γ or mixture thereof), dihydroterpineol, dihydroterpineol acetate, octanol, decanol, tridecanol, butyl carbitol, butyl carbitol acetate, toluene, and ethanol, while the binder consists of at least one of ethyl cellulose, nitrocellulose, acrylic resin, and polyvinyl butyral. For the various additives, dispersant, plasticizer, and leveling agent can be used, among others, where the types of dispersant that can be used include cationic dispersant, anionic dispersant, nonionic dispersant, amphoteric surface active agent, and polymeric dispersant, while the types of plasticizer and leveling agent are not limited in any way and any known plasticizer or leveling agent can be used. 
     Next, as shown in  FIG. 3  (A), the ceramic slurry is applied onto the top face of a base film BF made of polyethylene terephthalate, etc., using a doctor blade, slit die, or other applicator, after which the slurry is dried to produce a first laminating sheet constituted by the base film BF with a slurry layer SL of a specified thickness t 1  formed on it. Ceramic grains of various sizes are irregularly arranged in this slurry layer SL. 
     Also, as shown in  FIG. 3  (B), the electrode paste is printed onto the top face of the slurry layer SL on the first laminating sheet using a screen printer, letterpress, or other printing machine, after which the paste is dried to produce a second laminating sheet constituted by the slurry layer SL with a paste layer PL of a specified thickness t 2  and specified shape formed on it according to a specified arrangement. Metal grains of various sizes are irregularly arranged in this paste layer PL. 
     Next, as shown in  FIG. 3  (C), the slurry layer SL on the first laminating sheet is stamped out to a specified size and the stamped-out slurry layer SL is picked up onto the flat bottom face of a pickup head AH and transferred, and the slurry layer SL is placed over the flat top face of a lamination table LT. Then, a similarly stamped-out slurry layer SL is picked up onto the flat bottom face of the pickup head AH and transferred, and the slurry layer SL is placed over the top face of the slurry layer SL already on the lamination table LT and thermally press-bonded, and this step is repeated for a specified number of times. 
     As shown in  FIG. 3  (D), no visible interface appears between the specified number of thermally press-bonded slurry layers SL′ because the layers are of the same composition, but because the ceramic grains of various sizes arranged irregularly in each slurry layer SL before thermocompression bonding are displaced during the thermocompression bonding process, the virtual mutual contact surface (refer to the broken lines) formed after thermocompression bonding undulates. 
     Next, as shown in  FIG. 3  (D), the slurry layer SL on the second laminating sheet is stamped out to a specified size and the stamped-out slurry layer SL (including a number of paste layers PL) is picked up, on the paste layer PL side, onto the flat bottom face of the pickup head AH and transferred, and the slurry layer SL is placed over the top face of the slurry layer SL′ that has been thermally press-bonded, to thermally press-bond the layers. Then, a similarly stamped-out slurry layer SL (including a number of paste layers PL) is picked up, on the paste layer PL side, onto the flat bottom face of the pickup head AH and transferred, and the slurry layer SL is placed over the top face of the paste layer PL′ that has been thermally press-bonded, to thermally press-bond the layers. This process is repeated for a specified number of times. 
     As shown in  FIG. 3  (E), a visible interface appears between the specified number of thermally press-bonded slurry layers SL′ and paste layers PL′ because the layers are of different compositions, and also the wave-like undulation of the top interface of the slurry layer SL′ sandwiched by paste layers PL′ becomes larger than the wave-like undulation of the bottom interface. This undulation appears partly because the ceramic grains of various sizes arranged irregularly in each slurry layer SL before thermocompression bonding are displaced during the thermocompression bonding process, and partly because the stamped-out slurry layer SL is thermally press-bonded in a condition where its paste layer PL side is picked up onto the flat bottom face of the pickup head AH and consequently the top interface of the slurry layer SL undulates easily during the thermocompression bonding process. 
     Next, as shown in  FIG. 3  (E), the slurry layer SL on the first laminating sheet is stamped out to a specified size and the stamped-out slurry layer SL is picked up onto the flat bottom face of the pickup head AH and transferred, and the slurry layer SL is placed over the top face of the paste layer PL′ that has been thermally press-bonded, to thermally press-bond the layers. Then, a similarly stamped-out slurry layer SL is picked up onto the flat bottom face of the pickup head AH and transferred, and the slurry layer SL is placed over the top face of the slurry layer SL′ that has been thermally press-bonded, to thermally press-bond the layers. This process is repeated for a specified number of times. 
     As shown in  FIG. 3  (F), no visible interface appears between the specified number of thermally press-bonded slurry layers SL′ because the layers are of the same composition, but because the ceramic grains of various sizes arranged irregularly in each slurry layer SL before thermocompression bonding are displaced during the thermocompression bonding process, the virtual mutual contact surface (refer to the broken line) formed after thermocompression bonding undulates. 
     Next, a hot hydrostatic press or other press machine is used to perform final thermocompression bonding of the thermally press-bonded layers mentioned above, to produce a laminate. Next, the laminate is cut to a lattice pattern using a dicer or other cutting machine, to produce a chip corresponding to the capacitor body  11  shown in  FIG. 1 . Next, a multiple number of these chips are put in a sintering furnace and sintered under specified conditions (binder is removed as part of the sintering process). 
     Since the sintered chip corresponds to the capacitor body  11  shown in  FIG. 1 , it has internal electrode layers  13  and dielectric layers  14  as shown in  FIG. 2 . One of the two methods described below can be adopted to make sure the ceramic grains SP constituting the dielectric layer  14  of the sintered chip include coarse ceramic grains SPr of the coarse grain size Dcoa that meets the condition “Tmin≦Dcoa≦Tmax” (where Tmin represents the minimum thickness of the dielectric layer  14 , while T max represents the maximum thickness of the dielectric layer  14 ). 
     The first method is to use the following as the ceramic grains to be contained in the ceramic slurry: (1) ceramic grains having a grain size distribution that includes coarse ceramic grains approximating the coarse ceramic grains SPr of the coarse grain size Dcoa, such as one type of ceramic grains whose grain size distribution includes the coarse grain size Dcoa at around d95; (2) a mixture of ceramic grains having a grain size distribution that does not include coarse ceramic grains SPr of the coarse grain size Dcoa on one hand, and coarse ceramic grains SPr of the coarse grain size Dcoa on the other; and (3) a mixture of ceramic grains whose d50 is small on one hand, and ceramic grains whose d50 is large and whose grain size distribution includes the coarse grain size Dcoa at around d95 on the other. 
     Under this method, a grain size distribution approximating the grain size distribution of the ceramic grains contained in the ceramic slurry manifests in the ceramic grains SP constituting the dielectric layer  14  of the sintered chip, and therefore it is desirable to add magnesium oxide, barium carbonate, calcium carbonate, manganese carbonate, manganese dioxide, holmium oxide, erbium oxide, ytterbium oxide, or other grain growth suppressant to the ceramic slurry beforehand so as to suppress change in grain size distribution during the sintering process as much as possible. In addition, by pre-adjusting the grain size distribution of the ceramic grains contained in the ceramic slurry, the percentage of the coarse ceramic grains SPr included in the ceramic grains SP constituting the dielectric layer  14  of the sintered chip can be kept inside a range of 25 to 50 percent by volume, and the average grain size Dabe of the ceramic grains SP constituting the dielectric layer  14  of the sintered chip also meets the condition “0.15×Tabe≦Dabe≦0.3×Tabe” (where Tabe represents the average thickness of the dielectric layer  14 ). 
     The second method is to use, as the ceramic grains to be contained in the ceramic slurry, ceramic grains having a grain size distribution that does not include coarse ceramic grains SPr of the coarse grain size Dcoa, which ceramic grains is subjected to grain growth during the sintering process, thereby forming coarse ceramic grains SPr. 
     Under this method, a grain size distribution different from the grain size distribution of the ceramic grains contained in the ceramic slurry manifests in the ceramic grains SP constituting the dielectric layer  14  of the sintered chip, and therefore it is desirable to add one of the same grain growth suppressants mentioned above to the ceramic slurry beforehand, as necessary, by considering change in grain size distribution, so that: the coarse grain size Dcoa of the coarse ceramic grains SPr included in the ceramic grains SP constituting the dielectric layer  14  of the sintered chip meets the condition “Tmin≦Dcoa≦Tmax” (where Tmin represents the minimum thickness of the dielectric layer  14 , while Tmax represents the maximum thickness of the dielectric layer  14 ); the percentage of the coarse ceramic grains SPr included in the ceramic grains SP constituting the dielectric layer  14  of the sintered chip can be kept inside a range of 25 to 50 percent by volume; and the average grain size Dabe of the ceramic grains SP included in the ceramic grains SP constituting the dielectric layer  14  of the sintered chip meets the condition “0.15×Tabe≦Dabe≦0.3×Tabe” (where Tabe represents the average thickness of the dielectric layer  14 ). 
     Next, a dip coater, roller coater or other coating machine is used to apply an electrode paste similar to the electrode paste mentioned above on both longitudinal ends of the sintered chip, after which the paste is baked to form a base layer for the external electrodes  12  shown in  FIG. 1 . Then, a surface layer is formed on the surface of the base layer using electroplating or other plating method, to produce external electrodes  12  of two-layer structure. Or, an intermediate layer and surface layer are formed, in this order, on the surface of the base layer using electroplating or other plating method, to produce external electrodes  12  of three-layer structure. 
     {Effects of Multilayer Ceramic Capacitor} 
     To verify the effects obtained by the multilayer ceramic capacitor  10  shown in  FIGS. 1 and 2 , 120 each of Samples 1 to 17 (multilayer ceramic capacitors) were manufactured according to the aforementioned {Manufacturing Method for Multilayer Ceramic Capacitor}. 
     [Sample 1]
         Reference dimensions of capacitor body: Length 1.0 mm×Width 0.5 mm×Height 0.2 mm   Internal electrode layer   Average thickness: 0.7 μm   Number of layers: 100   Metal grain: Nickel   Average grain size: 0.2 μm   Dielectric layer   Minimum thickness Tmin: 0.4 μm   Maximum thickness Tmax: 1.0 μm   Average thickness Tabe: 0.6 μm   Number of layers: 100   Ceramic grain SP: Barium titanate   Coarse grain size Dcoa: 0.75 μm   Average grain size Dabe: 0.11 μm   Percentage of coarse ceramic grains: 30 percent by volume       

     [Sample 2] 
     Same as in Sample 1, except that the coarse grain size Dcoa was 0.90 μm. 
     [Sample 3] 
     Same as in Sample 1, except that the coarse grain size Dcoa was 0.45 μm. 
     [Sample 4] 
     Same as in Sample 1, except that the coarse grain size Dcoa was 0.35 μm. 
     [Sample 5] 
     Same as in Sample 1, except that the percentage of coarse ceramic grains was 25 percent by volume. 
     [Sample 6] 
     Same as in Sample 1, except that the percentage of coarse ceramic grains was 35 percent by volume. 
     [Sample 7] 
     Same as in Sample 1, except that the percentage of coarse ceramic grains was 40 percent by volume. 
     [Sample 8] 
     Same as in Sample 1, except that the percentage of coarse ceramic grains was 45 percent by volume. 
     [Sample 9] 
     Same as in Sample 1, except that the percentage of coarse ceramic grains was 50 percent by volume. 
     [Sample 10] 
     Same as in Sample 1, except that the percentage of coarse ceramic grains was 20 percent by volume. 
     [Sample 11] 
     Same as in Sample 1, except that the percentage of coarse ceramic grains was 55 percent by volume. 
     [Sample 12] 
     Same as in Sample 1, except that the average grain size Dabe was 0.09 μm. 
     [Sample 13] 
     Same as in Sample 1, except that the average grain size Dabe was 0.13 μm. 
     [Sample 14] 
     Same as in Sample 1, except that the average grain size Dabe was 0.15 μm. 
     [Sample 15] 
     Same as in Sample 1, except that the average grain size Dabe was 0.17 μm. 
     [Sample 16] 
     Same as in Sample 1, except that the average grain size Dabe was 0.07 μm. 
     [Sample 17] 
     Same as in Sample 1, except that the average grain size Dabe was 0.21 μm. 
       FIG. 4  shows the specifications and characteristics of Samples 1 to 17 above, and how these specifications and characteristics shown in the figure were measured are explained below. 
     To measure the Tmin (minimum thickness), Tmax (maximum thickness) and Tabe (average thickness) of each of Samples 1 to 17, 10 each of Samples 1 to 17 were prepared and each sample piece was observed on its longitudinal cross-section corresponding to FIG. 1 using a scanning electron microscope at a magnification of ×3000 and the Tmin (minimum thickness) and Tmax (maximum thickness) of the dielectric layer inside the observed range were measured, to obtain the Tmin (minimum thickness) and Tmax (maximum thickness) of each of Samples 1 to 17 from the average Tmin (minimum thickness) of 10 sample pieces and average Tmax (maximum thickness) of 10 sample pieces, while the average thickness obtained from these Tmin (minimum thickness) and Tmax (maximum thickness) was used as the Tabe (average thickness) of each of Samples 1 to 17. 
     Also to measure the Dcoa (coarse grain size), percentage, and Dabe (average grain size) of the ceramic grains in each of Samples 1 to 17, the grain sizes of all ceramic grains inside the observed range were measured, where, if the number of ceramic grains in the observed range was less than 300, then the grain sizes of all ceramic grains inside a different observed range were measured successively so that at least 300 grains were measured, after which the Dcoa (coarse grain size), volumetric percentage of the coarse grains based on cross-section area, and Dabe (average grain size) were measured, respectively, to obtain the Dcoa (coarse grain size), percentage, and Dabe (average grain size) of each of Samples 1 to 17 from the average Dcoa (coarse grain size) of 10 sample pieces, average volumetric percentage of 10 sample pieces, and average Dabe (average grain size) of 10 sample pieces, respectively. 
     Among the characteristics of Samples 1 to 17, dielectric constant, capacitance, and rate of change in capacity were measured by preparing 10 each of Samples 1 to 17 and then measuring them for the dielectric constant of the dielectric layer and the overall capacitance at a frequency of 1 kHz, voltage of 1 V, and ambience of 25° C., while measuring the overall capacitance on the same sample pieces again at an ambience of 85° C., to obtain for each sample piece the percentage rate of change in capacity (rate of decrease in capacity) relative to a temperature shift from 25° C. to 85° C., to obtain the dielectric constant, capacitance, and rate of change in capacity of each of Samples 1 to 17 from the average dielectric constant of 10 sample pieces, average capacitance of 10 sample pieces, and average rate of change in capacity of 10 sample pieces. 
     Among the characteristics of Samples 1 to 17, short-circuiting ratio was measured by preparing 100 each of Samples 1 to 17 and then applying a voltage of 1 VDC to recognize those sample pieces whose resistance value was less than 1 kΩ as short-circuited, to obtain the short-circuiting ratio of each of Samples 1 to 17 from the percentage of short-circuited sample pieces out of 100. 
     As shown in  FIG. 4 , the capacitances of Samples 1 to 3 whose coarse grain size Dcoa of the coarse ceramic grains SPr included in the ceramic grains SP constituting the dielectric layer  14  meets the condition “Tmin≦Dcoa≦Tmax” are greater than the capacitance of Sample 4 whose coarse grain size Dcoa does not meet this condition, while the rates of change in capacity (capacity vs. temperature characteristics) of Samples 1 to 3 are better (within ±18%) than the rate of change in capacity (capacity vs. temperature characteristics) of Sample 4 whose coarse grain size Dcoa does not meet this condition. 
     Also, as shown in  FIG. 4 , the capacitances of Samples 1 and 5 to 9 whose percentage of the coarse ceramic grains SPr included in the ceramic grains SP constituting the dielectric layer  14  is inside a range of 25 to 50 percent by volume are greater than the capacitance of Sample 10 whose percentage of the coarse ceramic grains SPr is outside this range, while the short-circuiting ratios of Samples 1 and 5 to 9 are lower (15% or less) than the short-circuiting ratio of Sample 11 whose percentage of the coarse ceramic grains SPr is outside the range. 
     In addition, among Samples 1 and 5 to 9, the rates of change in capacity (capacity vs. temperature characteristics) of Samples 1, 6 and 7 whose percentage of the coarse ceramic grains SPr is inside a range of 30 to 40 percent by volume are better (within ±15%) than the rate of change in capacity (capacity vs. temperature characteristics) of Sample 5 whose percentage of the coarse ceramic grains SPr is outside this range, while the short-circuiting ratios of Samples 1, 6 and 7 are lower (8% or less) than the short-circuiting ratios of Samples 8 and 9 whose percentage of the coarse ceramic grains SPr is outside the range. 
     Furthermore, as shown in  FIG. 4 , the capacitances of Samples 1 and 12 to 15 whose average grain size Dabe of the ceramic grains SP constituting the dielectric layer  14  meets the condition “0.15×Tabe≦Dabe≦0.3×Tabe” (or specifically 0.09 μm≦Dabe≦0.18 μm here) are greater than the capacitance of Sample 16 whose average grain size Dabe does not meet this condition, while the short-circuiting ratios of Samples 1 and 12 to 15 are lower (12% or less) than the short-circuiting ratio of Sample 17 whose average grain size Dabe does not meet this condition. 
     Moreover, among Samples 1 and 12 to 15, the rates of change in capacity (capacity vs. temperature characteristics) of Samples 1, 13 and 14 whose average grain size Dabe meets the condition “0.18×Tabe≦Dabe≦0.25×Tabe” (or specifically 0.108 μm≦Dabe≦0.15 μm here) are better (within ±15%) than the rate of change in capacity (capacity vs. temperature characteristics) of Sample 12 whose average grain size Dabe does not meet this condition, while the short-circuiting ratios of Samples 1, 13 and 14 are lower (10% or less) than the short-circuiting ratio of Sample 15 whose average grain size Dabe does not meet this condition. 
     Description of the Symbols 
       10 —Multilayer ceramic capacitor,  11 —Capacitor body,  12 —External electrode,  13 —Internal electrode layer,  14 —Dielectric layer, SP—Ceramic grain, SPr—Coarse ceramic grain.