Patent Publication Number: US-2023162988-A1

Title: Semiconductor Fin Structure Cut Process

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to Chinese Patent Application No. 202111390542.0, filed on Nov. 23, 2021, the disclosure of which is incorporated herein by reference in its entirety. 
     TECHNICAL FIELD 
     The present application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a semiconductor fin structure cut process. 
     BACKGROUND 
     For planar transistors, the current flows in the planar channel below the gate, and the current in the channel is controlled by controlling the voltage of the gate. In order to improve the gated field effect of the gate, those skilled in the art have designed Fin Field-Effect Transistor (FinFET). FinFET includes a fin structure for forming a channel, a source and a drain are respectively located at two ends of the fin structure, and a gate covers sidewalls and a top of the fin structure. The fin structure increases the area of the gate around the channel, which can strengthen the control of the gate over the channel and slow down the short channel effect in the planar transistor. 
       FIG.  1   a    illustrates a sectional structure of a device before a cut process in the prior art.  FIG.  1   b    illustrates a sectional structure of a device after a cut process in the prior art. In the prior art, after several semiconductor fin structures  10  illustrated in  FIG.  1   a    are formed on a wafer, unnecessary fin structures need to be removed through a cut process. Usually, a lithography pattern  20  is directly formed through a lithography process, and a truncated region  30  is defined on the wafer. Then, the wafer with several semiconductor fin structures is etched according to the lithography pattern  20  to remove the fin structures in the truncated region. 
     However, with the miniaturization of integrated circuit devices, the Critical Dimension (CD) of a single fin structure continues to shrink. Therefore, in the prior art, the requirement on the process window of forming a hard mask pattern through lithography is high and the lithography process is more difficult. 
     BRIEF SUMMARY 
     The present application provides a semiconductor fin structure cut process, which can solve the problems that the requirement of the cut method of the prior art on the lithography process window is relatively high and the difficulty in lithography is great for the fin structure with small critical dimension. 
     In order to solve the technical problems in the background, the present application provides a semiconductor fin structure cut process. The semiconductor fin structure cut process includes the following steps performed sequentially: 
     providing a semiconductor substrate and forming a plurality of fin structures on the semiconductor substrate, a gap being formed between every two adjacent fin structures; 
     depositing a first dielectric layer, the first dielectric layer being filled in the gaps so that all fin structures are connected into a whole to form a semiconductor with fins; 
     forming a plurality of pattern layer strips on the semiconductor with fins, a groove being formed between every two adjacent pattern layer strips, an upper surface of the semiconductor with fins at the positions of the grooves being exposed, the fin structures closest to each pattern layer strip in the semiconductor with fins being necessary fin structures, and the remaining fin structures being unnecessary fin structures; 
     attaching mask strips onto side surfaces of each pattern layer strip, the mask strips covering the necessary fin structures; 
     etching the semiconductor with fins on the basis of a pattern formed by the mask strips so that the unnecessary fin structures not covered by the mask strips are truncated. 
     In some examples, the step of depositing a first dielectric layer, the first dielectric layer being filled in the gaps so that all fin structures are connected into a whole to form a semiconductor with fins includes: 
     depositing a first dielectric layer, the first dielectric layer being filled in the gaps so that all fin structures are connected into a whole; 
     enabling tops of the fin structures connected into a whole to be covered with the first dielectric layer to form the semiconductor with fins. 
     In some examples, after the semiconductor with fins is formed, the semiconductor fin structure cut process further includes: 
     performing chemical-mechanical polishing to a surface layer of the fin to planarize the upper surface of the semiconductor with fins. 
     In some examples, the step of attaching mask strips onto side surfaces of each pattern layer strip, the mask strips covering the necessary fin structures includes: 
     depositing second dielectric, so that the second dielectric is attached onto bottom surfaces of the grooves and side surfaces and top surfaces of the pattern layer strips to form a second dielectric layer, the second dielectric layer attached onto the side surfaces of the pattern layer strips covering the fin structures closest to the side surfaces of the pattern layer strips; 
     etching the second dielectric layer to remove the second dielectric layer covering the bottom surfaces of the grooves and the top surfaces of the pattern layer strips, the remaining second dielectric layer covering the necessary fin structures to form mask strips. 
     In some examples, the step of depositing second dielectric includes: 
     depositing second dielectric through silicon oxide atoms at temperature ranging from 80° C. to 200° C., so that the second dielectric is attached onto the bottom surfaces of the grooves and the side surfaces and top surfaces of the pattern layer strips to form a second dielectric layer. 
     In some examples, the step of forming a plurality of pattern layer strips on the semiconductor with fins, a groove being formed between every two adjacent pattern layer strips, an upper surface of the semiconductor with fins at the positions of the grooves being exposed includes: 
     sequentially forming a hard mask layer, an anti-reflection layer and a photoresist layer on the semiconductor with fins; 
     etching the photoresist layer through a photolithography process so that the remaining photoresist layer forms a first pattern; 
     etching the anti-reflection layer and the hard mask layer on the basis of the photoresist layer with the first pattern, so that the first pattern is transferred into the anti-reflection layer and the hard mask layer; 
     performing etching to remove the anti-reflection layer with the first pattern and reserve the hard mask layer with the first pattern. 
     In some examples, the anti-reflective layer with the first pattern includes a plurality of the pattern layer strips, and the groove is formed between every two adjacent layer strips. 
     In some examples, after the step of etching the fin on the basis of a pattern formed by the mask strips so that the unnecessary fin structures not covered by the mask strips are truncated, roots of the unnecessary fin structures are reserved to a height ranging from 18 mm to 22 mm. 
     In some examples, after the step of etching the semiconductor with fins on the basis of a pattern formed by the mask strips so that the unnecessary fin structures not covered by the mask strips are truncated, the semiconductor fin structure cut process further includes: 
     forming a third dielectric layer through deposition so that the third dielectric layer is filled in a spacing groove between every two adjacent necessary fin structures. 
     In some examples, after the step of forming a third dielectric layer through deposition so that the third dielectric layer is filled in a spacing groove between every two adjacent necessary fin structures, an upper surface of the third dielectric layer is planarized through chemical-mechanical polishing. 
     The technical solution of the present application at least has the following advantages: in the present application, pattern layer strips with a wide width are firstly formed on the semiconductor with fins, a groove is formed between every two adjacent pattern layer strips, then the second dielectric layer attached onto the side surfaces of the pattern layer strips are enabled to cover the fin structures closest to the side surfaces of the pattern layer strips through the second dielectric layer deposition process, and the fin structures closest to the side surfaces of the pattern layer strips are necessary fin structures. Then, the second dielectric layer is etched, and the second dielectric layer attached to the side surfaces of the pattern layer strips is reserved to form mask strips. The mask strips protect the necessary fin structures, so that after the subsequent etching according to the pattern formed by the mask strips, the necessary fin structures are reserved, and the unnecessary fin structures are truncated. The requirement of this present application on the lithography process window is low, and it can solve the problem of great difficulty in lithography in the prior art. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In order to more clearly describe the technical solutions in the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the description of the specific embodiments or the prior art. It is obvious that the drawings in the following description are some embodiments of the present application. For those skilled in the art, other drawings can be obtained according to these drawings without contributing any inventive labor. 
         FIG.  1   a    illustrates a sectional structure of a device before a cut process in the prior art. 
         FIG.  1   b    illustrates a sectional structure of a device after a cut process in the prior art. 
         FIG.  2    illustrates a flowchart of a semiconductor fin structure cut process provided by an embodiment of the present application. 
         FIG.  2   a    illustrates a sectional structure of a semiconductor with a plurality of fin structures in an embodiment of the present application. 
         FIG.  2   b    illustrates a semiconductor with fins formed after step S 2  in an embodiment of the present application. 
         FIG.  2   c    illustrates a sectional structure of a fine after chemical-mechanical polishing on the basis of a structure illustrated in  FIG.  2     b.    
         FIG.  3   a    illustrates a sectional structure of a device after step S 31  and step S 32  in an embodiment of the present application. 
         FIG.  3   b    illustrates a sectional structure of a device after step S 33  on the basis of a structure illustrated in  FIG.  3   a    in an embodiment of the present application. 
         FIG.  3   c    illustrates a sectional structure of a device after step S 34  on the basis of a structure illustrated in  FIG.  3   b    in an embodiment of the present application. 
         FIG.  4   a    illustrates a sectional structure of a device after step S 41  on the basis of a structure illustrated in  FIG.  3   c    in an embodiment of the present application. 
         FIG.  4   b    illustrates a sectional structure of a device after step S 42  on the basis of a structure illustrated in  FIG.  4   a    in an embodiment of the present application. 
         FIG.  5    illustrates a sectional structure of a device after step S 5  on the basis of a structure illustrated in  FIG.  4   b    in an embodiment of the present application. 
         FIG.  6   a    illustrates a sectional structure of a device after deposition of a third dielectric layer in an embodiment of the present application. 
         FIG.  6   b    illustrates a sectional structure of a device after planarization of an upper surface of the third dielectric layer illustrated in  FIG.  6     a.    
     
    
    
     DETAILED DESCRIPTION 
     The technical solution of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present application, instead of all of them. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without contributing any inventive labor still fall within the scope of protection of the present application. 
       FIG.  2    illustrates a flowchart of a semiconductor fin structure cut process provided by an embodiment of the present application. The semiconductor fin structure cut process includes the following steps performed sequentially: 
     In step S 1 , a semiconductor substrate is provided, a plurality of fin structures are formed on the semiconductor substrate and a gap is formed between every two adjacent fin structures. 
     Referring to  FIG.  2   a   , it illustrates a sectional structure of a semiconductor with a plurality of fin structures in an embodiment of the present application. 
     A plurality of fin structures  110  are formed on the semiconductor substrate  100  in  FIG.  2   a   , and a gap  120  is formed between every two adjacent fin structures  110 . Each fin structure  110  includes a fin semiconductor bottom layer  111 , a first fin dielectric layer  112 , a fin silicon nitride layer  113 , and a second fin dielectric layer  114  sequentially stacked from bottom to top. In some examples, the material of the first fin dielectric layer  112  and the second fin dielectric layer  114  is silicon oxide. 
     In step S 2 , a first dielectric layers deposited. The first dielectric layer is filled in the gaps so that all fin structures are connected into a whole to form a semiconductor with fins. 
     Referring to  FIG.  2   b   , it illustrates a semiconductor with fins formed after step S 2  in an embodiment of the present application. The semiconductor with fins  140  includes those fin structures  110  illustrated in  FIG.  2   a   . A first dielectric layer  130  is filled in those gaps  120  between the fin structures  110 , so that those fin structures  110  are connected into a whole to form the semiconductor with fins  140 . 
     After the semiconductor with fins  140  illustrated in  FIG.  2   b    is formed, chemical-mechanical polishing may be performed to the semiconductor with fins  140  illustrated in  FIG.  2   b    by using the fin silicon nitride layer  113  as a stop layer. The structure of the semiconductor with fins  140  formed after polishing is as illustrated in  FIG.  2     c.    
     In some examples, in the process of depositing the first dielectric layer, the tops of those fin structures connected into a whole may also be covered with the first dielectric layer to form a semiconductor with fins. Then, chemical-mechanical polishing is performed to a surface layer of the semiconductor with fins by using the fin silicon nitride layer as a stop layer to planarize the upper surface of the fin to form a structure illustrated in  FIG.  2     c.    
     In step S 3 , a plurality of pattern layer strips are formed on the semiconductor with fins. A groove is formed between every two adjacent pattern layer strips. The upper surface of the semiconductor with fins at the positions of the grooves is exposed. The fin structures closest to each pattern layer strip in the semiconductor with fins are necessary fin structures, and the remaining fin structures are unnecessary fin structures. 
     In some examples, in the process of performing step S 3 , the following step S 31  to step S 33  may be sequentially performed. 
     In step S 31 , a hard mask layer, an anti-reflection layer and a photoresist layer are sequentially formed on the semiconductor with fins. 
     In step S 32 , the photoresist layer is etched through a photolithography process so that the remaining photoresist layer forms a first pattern. 
     Referring to  FIG.  3   a   , it illustrates a sectional structure of a device after step S 31  and step S 32  in an embodiment of the present application. In this embodiment, a mask layer  210 , an anti-reflection layer  220  and a photoresist layer  230  are sequentially formed on the semiconductor with fins  140  illustrated in  FIG.  2   c    from bottom to top, and the photoresist layer  230  has a first pattern. 
     The critical dimension of the photoresist layer  230  with the first pattern is large, and the requirement on the etching process window of the lithography process is low. 
     In step S 33 , the anti-reflection layer and the hard mask layer are etched on the basis of the photoresist layer with the first pattern, so that the first pattern is transferred into the anti-reflection layer and the hard mask layer. 
     Referring to  FIG.  3   b   , it illustrates a sectional structure of a device after step S 33  on the basis of a structure illustrated in  FIG.  3   a    in an embodiment of the present application. 
     In  FIG.  3   b   , the anti-reflection layer  220  and the hard mask layer  210  are patterned through step S 32 , so that the first pattern of the photoresist layer  230  illustrated in  FIG.  3   a    is transferred into the anti-reflection layer  220  and the hard mask layer  210 . 
     In  FIG.  3   a    and  FIG.  3   b   , the anti-reflection layer  220  is used to absorb the reflected light generated in the lithography process and reduce problems such as lithography reflection or standing wave. The anti-reflection layer  220  may include an enhanced Dielectric Anti-Reflection Coating (DARC)  221  and a Bottom Anti-Reflection Coating (BARC)  222  sequentially stacked from bottom to top. 
     In step S 34 , etching is performed to remove the anti-reflection layer with the first pattern and reserve the hard mask layer with the first pattern. 
     Referring to  FIG.  3   c   , it illustrates a sectional structure of a device after step S 34  on the basis of a structure illustrated in  FIG.  3   b    in an embodiment of the present application. 
     In  FIG.  3   c   , the semiconductor with fins  140  is only covered with a hard mask layer with a first pattern layer. The hard mask layer with the first pattern layer includes a plurality of pattern layer strips  211 , a groove  212  is formed between every two adjacent pattern layer strips  211 , and the upper surface of the semiconductor with fins  140  at the positions of the grooves  212  is exposed. In  FIG.  3   c   , the fin structures  110  in the dotted boxes pointed by arrows are necessary fin structures, and the remaining fin structures are unnecessary fin structures. The necessary fin structures are next to the sidewalls of the pattern layer strips  211  and are one fin structures closest to the pattern layer strips  211 . 
     In step S 4 , mask strips are attached onto side surfaces of each pattern layer strip. The mask strips cover the necessary fin structures. 
     In some examples, the mask strips on the side surfaces of the pattern layer strips may be formed through the following step S 41  to step S 42 . 
     In step S 41 , second dielectric is deposited, so that the second dielectric is attached onto bottom surfaces of the grooves and side surfaces and top surfaces of the pattern layer strips to form a second dielectric layer. The second dielectric layer attached onto the side surfaces of the pattern layer strips covers the fin structures closest to the side surfaces of the pattern layer strips. 
     In some examples, second dielectric is deposited through silicon oxide atoms at temperature ranging from 80° C. to 200° C., so that the second dielectric is attached onto the bottom surfaces of the grooves and the side surfaces and top surfaces of the pattern layer strips to form a second dielectric layer. 
     Referring to  FIG.  4   a   , it illustrates a sectional structure of a device after step S 41  on the basis of a structure illustrated in  FIG.  3   c    in an embodiment of the present application. 
     The second dielectric layer  310  covers the bottom surfaces of the grooves  210  and the side surfaces and top surfaces of the pattern layer strips  211 . The second dielectric layer  310  attached onto the side surfaces of the pattern layer strips  211  covers the fin structures  110  at the positions of dotted boxes pointed by arrows in  FIG.  4   a   , that is, the fin structures  110  closest to the side surfaces of the pattern layer strips  211 . 
     In step S 42 , the second dielectric layer is etched to remove the second dielectric layer covering the bottom surfaces of the grooves and the top surfaces of the pattern layer strips. The remaining second dielectric layer covers the necessary fin structures to form mask strips. 
     Referring to  FIG.  4   b   , it illustrates a sectional structure of a device after step S 42  on the basis of a structure illustrated in  FIG.  4   a    in an embodiment of the present application. 
     After step S 42 , the remaining second dielectric layer forms mask strips  311 , the mask strips  311  cover the necessary fin structures  110 , and the necessary fin structures  110  are fin structures  110  at the positions of dotted boxes pointed by arrows in  FIG.  4     a.    
     In the process of etching the second dielectric layer to form the mask strips, there is no need for additional lithography process. By controlling the direction of etching, anisotropic etching can be used to reserve the second dielectric layer attached onto the side surfaces of the pattern layer strips. 
     In step S 5 , the semiconductor with fins is etched on the basis of a pattern formed by the mask strips so that the unnecessary fin structures not covered by the mask strips are truncated. 
     Referring to  FIG.  5   , it illustrates a sectional structure of a device after step S 5  on the basis of a structure illustrated in  FIG.  4   b    in an embodiment of the present application. 
     As can be seen from  FIG.  5   , the unnecessary fin structures are truncated, the remaining fin structures  110  are necessary fin structures, and a spacing groove  320  is formed between every two adjacent necessary fin structures. After the unnecessary fin structures are truncated, roots of the unnecessary fin structures are reserved to a height d ranging from 18 mm to 22 mm in the spacing groove  320 . 
     In this embodiment, pattern layer strips with a wide width are firstly formed on the semiconductor with fins, a groove is formed between every two adjacent pattern layer strips, then the second dielectric layer attached onto the side surfaces of the pattern layer strips are enabled to cover the fin structures closest to the side surfaces of the pattern layer strips through the second dielectric layer deposition process, and the fin structures closest to the side surfaces of the pattern layer strips are necessary fin structures. Then, the second dielectric layer is etched, and the second dielectric layer attached to the side surfaces of the pattern layer strips is reserved to form mask strips. The mask strips protect the necessary fin structures, so that after the subsequent etching according to the pattern formed by the mask strips, the necessary fin structures are reserved, and the unnecessary fin structures are truncated. The requirement of this present application on the lithography process window is low, and it can solve the problem of great difficulty in lithography in the prior art. 
     In other embodiments, after step S 5 , deposition is performed to form a third dielectric layer, so that the third dielectric layer is filled in the spacing groove between every two adjacent necessary fin structures. 
     Referring to  FIG.  6   a   , it illustrates a sectional structure of a device after deposition of a third dielectric layer. The formed third dielectric layer  410  is filled in the spacing grooves  230  illustrated in  FIG.  5   . 
     On the basis of the device structure illustrated in  FIG.  6   a   , chemical-mechanical polishing is performed by using the fin silicon nitride layer  113  of the fin structure  110  as a stop layer, so that an upper surface of the third dielectric layer  410  is planarized to form a device structure illustrated in  FIG.  6     b.    
     Obviously, the above embodiments are only examples for clear description, instead of limitations to the embodiments. For those skilled in the art, other changes or variations in different forms may be made on the basis of the above description. It is unnecessary and impossible to enumerate all embodiments here. Obvious changes or variations derived thereby are still within the scope of protection of the present application.