Patent Publication Number: US-8112615-B1

Title: Single cycle reduced complexity CPU

Description:
FIELD OF THE INVENTION 
     The field of the present invention pertains to digital electronic computer systems. More particularly, the present invention relates to an architecture for a central processor unit configured to execute instructions within a single clock cycle. 
     BACKGROUND OF THE INVENTION 
     Digital computers are being used today to perform a wide variety of tasks. Many different areas of business, industry, government, education, entertainment, and most recently, the home, are tapping into the enormous and rapidly growing list of applications developed for today&#39;s increasingly powerful computer devices. Computers and other types of “smart” devices have also become a key technology for communicating ideas, data, and trends between and among business professionals. Additionally, digital computers, or more particularly, digital central processor units (CPUs) are increasingly being embedded in a variety of devices that are not traditionally associated with information technology. Examples include microcontrollers for machine tools, mechanisms, engines, and the like. The power and flexibility of the CPUs makes them well-suited for incorporation into a large number of different types of devices. 
     As embedded computer systems become increasingly ubiquitous and widespread in their use, there is increasing interest in improving the performance and software execution speed of the computer systems. One of the methods used by designers to increase software execution speed is to increase the processor “clock speed.” Clock speed refers to the rate at which the CPU steps its way through the individual software instructions. Increasing the number of clock cycles per second directly increases the number of instructions executed per second. 
     Another method used by designers is to increase the density of the electrical components within integrated circuit dies. For example, many high-performance integrated circuit processors include tens of millions of transistors integrated into a single die (e.g., 60 million transistors or more). As density increases, the clock speeds possible within a given design also increase, for example, as circuit traces are packed ever more closely together. 
     Another method for increasing performance is to increase the efficiency of heat removal from a high-density high-performance integrated circuit. As component density increases and clock speed increases, the thermal energy that must be dissipated per unit area of silicon also increases. To maintain high performance, stable operating temperature must maintained. Accordingly, the use of carefully designed heat dissipation devices (e.g., heat sink fans, liquid cooling, heat spreaders, etc.) with high-performance processors has become relatively standardized. 
     There are limits to the extent to which each of the above methods of improving computer system performance can be reasonably implemented. For example, with respect to increasing clock speed, high clock speeds leads to excessively tight tolerances for wiring, chipsets, printed circuit board design, and the like in order to ensure reliable operation. Additionally, high clock speeds tend to increase power consumption of the CPU. With respect to increasing the density of the electrical components within the integrated circuit die, as more and more transistors and other circuit elements are able to be incorporated within an integrated circuit die, there is increasing pressure to incorporate other functions within the die which used to be separate discrete chips. Often, greater performance can be realized by incorporating additional amounts of memory, controller hardware, and the like, as opposed to incorporating circuit elements designed to purely increase the speed of the CPU. Accordingly, silicon area tends to be just as valuable with a high-density fabrication process as with a less advanced lower density fabrication process. With respect to heat removal, the use of carefully designed heat dissipation devices limits the packaging options available to a device designer. This is especially cumbersome in the case of embedded computer devices. As described above, high clock speeds tend to directly cause high heat dissipation requirements, thus, requiring expensive and more space consuming heat dissipation devices in order to ensure high-performance. 
     Because of these limitations, CPU designers also concentrate on designing the circuitry of the CPU such that instructions can execute as efficiently as possible. For example, with many microprocessor designs, one or more instructions are capable of being executed per clock cycle. RISC (reduced instruction set computing) CPUs are specifically designed to have instruction sets wherein the majority of the instructions are capable of being executed within a single clock cycle. Additionally, RISC CPUs are designed to be simple in comparison to more complex CPUs, such that they require less silicon area in their manufacture. Because of these advantages, many microcontroller type devices are often based on RISC type CPUs. 
     These processors are RISC based, but still require separate instruction fetch, decode, execute and write-back stages in order to implement many types of commonly used instructions. A separate clock cycle is required for each of these stages. Thus, for example, read-modify-write type instructions require a minimum of four clock cycles to complete. In order to perform instructions faster than four clock cycles each, complex pipelining and microcode are required. This leads to a very complex processor design which consumes a large amount of silicon area to implement on chip. Although pipelining improves instruction throughput, the instruction latency is still four clock cycles. The complex pipelining also imposes additional penalties with respect to instruction branching. In the event of a branch, all the instructions in the pipeline need to be flushed and the pipeline needs to be refilled with new instructions, thereby imposing a significant performance penalty. 
     Thus, a need exists for a RISC type processor solution that can execute many different types of instructions within a single clock cycle. A need exists for a solution that increases processor performance without relying solely upon increased clock speed, component density, or heat dissipation. 
     SUMMARY OF THE INVENTION 
     Embodiments of the present invention provide a RISC type processor that can execute many different types of instructions within a single clock cycle. Embodiments of the present invention increase processor performance by executing many different types of instructions within a single clock cycle and eliminating any latency penalties associated with pipelined bus architectures. 
     In one system embodiment, the present invention is implemented as a single cycle RISC CPU. In this embodiment, the single cycle RISC CPU includes an instruction decoder configured to perform an instruction fetch and an instruction decode. An arithmetic logic unit is coupled to the instruction decoder. The arithmetic logic unit is configured to perform an instruction execute and produce a resulting data output. A register file is coupled to the arithmetic logic unit. The register file includes a register input and a register output. The register file is configured to provide data for the instruction fetch via the register output and accept the resulting data output via the register input such that the instruction fetch, the instruction decode, and the instruction execute are performed in a single clock cycle. 
     In another embodiment, the single cycle RISC CPU has an internal configuration wherein the instruction decoder, the arithmetic logic unit, and the register file are coupled using a non-pipelined bus architecture. The non-pipelined bus architecture is configured to implement an instruction branch without incurring a latency penalty. Additionally, the RISC CPU can be configured to implement a link control sequencer for a communication system. 
     In another embodiment, the single cycle RISC CPU has a configuration that is in accordance with a Harvard architecture design. Additionally, the instruction decoder can be configured to function with instructions compatible with well known microcontroller instruction set standards. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: 
         FIG. 1  shows a block diagram of a single cycle RISC type processor in accordance with one embodiment of the present invention. 
         FIG. 2  shows a timing diagram of a single cycle RISC type processor in accordance with one embodiment of the present invention. 
         FIG. 3  shows a more detailed implementation of a single cycle RISC processor in accordance with one embodiment of the present invention. 
         FIG. 4  shows a flowchart of the steps of an operating process in accordance with one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of embodiments of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the embodiments of the present invention. 
     Embodiments of the present invention provide a single cycle RISC type processor that can execute many different types of instructions within a single clock cycle. Embodiments of the present invention increase processor performance by executing many different types of instructions within a single clock cycle and eliminating any latency penalties associated with pipelined bus architectures. Embodiments of the present invention and their benefits are further described below. 
       FIG. 1  shows a block diagram of a single cycle RISC type processor  100  in accordance with one embodiment of the present invention. As depicted in  FIG. 1 , processor  100  includes an instruction decoder  101  coupled to a first and second ALU (arithmetic logic unit)  102 - 103 . The first and second ALUs  102 - 103  are also coupled to a register file  104 . 
     In the system  100  embodiment, the components  101 - 105  are configured to implement a single cycle RISC CPU. In the present embodiment, the single cycle RISC CPU  100  includes the instruction decoder  101  configured to perform an instruction fetch and an instruction decode. Although the instruction decoder  101  is depicted as a single component, it should be noted that the instruction decoder  101  can be implemented as a separate instruction storage unit (e.g., instruction register) coupled to a separate instruction decoder. A pointer compute unit  105  is shown coupled to the instruction decoder  101  (e.g., for incrementing, decrementing, and otherwise tracking the instruction pointer). The arithmetic logic units  102 - 103  are coupled to the instruction decoder  101  as shown. The arithmetic logic units  102 - 103  are configured to perform an instruction execute (e.g., integer addition, address computation, etc.) and produce a resulting data output. In this embodiment, the data output of the ALU  103  is coupled to an input of the ALU  102 . 
     The register file  104  is coupled to the arithmetic logic units  102 - 103 . The register file  104  includes a register input  110  and a register output  111 . The register file  104  is configured to provide data (e.g., instruction pointer, etc.) for the instruction fetch (e.g., for the instruction decoder  101 ) via the register output  111  and accept the resulting data output via the register input  110  such that the instruction fetch, the instruction decode, and the instruction execute are performed in a single clock cycle. 
     Referring still to processor  100  of  FIG. 1 , the output of the instruction decoder  101  is coupled to the ALUs  102 - 103  as shown. These instructions enable the ALUs  102 - 103  to perform the instruction execute as commanded. The result of the instruction execute is provided to the input  110  of the register file  104  as shown. The output  111  of the register file  104  is provided to an input of the ALU  103 , which in turn, can provide the output  111  to the ALU  102 , the pointer compute  105 , and the instruction decoder  101 . 
     The processor  100  embodiment of the present invention utilizes a property of the register file  104  in that there will exist a brief period of time wherein data present on the input  110  will not change data present at the output  111  of the register file  104 . In other words, there is a discrete amount of time required for a change of the data at the input  110  to be reflected at the output  111 . During this discrete amount of time, processor  100  can read data at the output  111  (e.g., instruction fetch), decode this data (e.g., instruction decode), perform an instruction execute (e.g., using the ALUs  102 - 103 ), and provide the resulting data back to the input  110  so that it can be clocked into the register file  104  at the next rising edge. 
     In so doing, a complete instruction is executed within a single clock cycle. Particularly, a read-modify-write instruction is implemented within a single clock cycle, wherein data is read from a register, that data is modified through an instruction execution, and that data is written back to the register all within a single clock cycle. As known by those skilled in the art, such a read-modify-write instruction is impossible to implement within a single clock cycle using prior art RISC type CPUs. 
     In the present embodiment, the processor  100  has an internal configuration wherein the instruction decoder  101 , the ALUs  102 - 103 , and the register file  104  are coupled using a non-pipelined bus architecture comprising buses  140 - 144 . Because the nature in which single cycle instructions are executed, the processor  100  embodiment of the present invention does not require a pipelined bus architecture in order to ensure a high degree of instruction throughput. The non-pipelined bus architecture is thus configured to implement an instruction branch without incurring a latency penalty. As known by those skilled in the art, prior art type deeply pipelined RISC processors incur a very significant performance penalty on instruction branches, wherein the deep pipelines need to be flushed and completely refilled. 
     In the present embodiment, the processor  100  has a configuration that is in accordance with a Harvard architecture design (e.g., separate buses and storage systems for instructions and data). 
     The processor  100  embodiment is flexible in that the instruction decoder  101  can be configured to function with instructions compatible with well known microcontroller instruction set standards. This provides advantages in enabling a designer to use well known and widely used tools to develop software for the processor  100 . 
     Because of the speed of execution (e.g., 1 instruction executed per clock cycle) the processor  100  embodiment is well-suited for highly demanding applications which require high-performance and limited silicon area. For example, embodiments of the processor  100  architecture can be configured to implement a link control sequencer (LCS) for a communication system. In such embodiment, the link control sequencer would be used to perform CRC (cyclic redundancy checking) processing, packet computations and packet movement, and the like. Example applications include wireless transmission systems such as Bluetooth, and the like. 
       FIG. 2  shows a timing diagram  200  in accordance with one embodiment of the present invention. As depicted in  FIG. 2 , the timing diagram  200  shows the relationship between the input  110  of the register file  104  and the output  111  with respect to a clock signal  201 . 
     The components  101 - 105  of the processor  100  embodiment are latched on the rising edge of the clock signal  201 . Thus, the value on the input  110  is latched within the register file  104  synchronous to the rising edge of the clock signal  201 , as shown by the values “n” and “n+1.” As described above, there is a discrete amount of time required for the same values to be reflected at the output  110  of the register file  104 . This is shown as the slight offset delay for the values “n” and “n+1” on the output  111  with respect to the rising edge of the clock signal  201 . Hence, as described above, during this discrete amount of time, processor  100  can read data at the output  111  (e.g., instruction fetch), decode this data (e.g., instruction decode), perform an instruction execute (e.g., using the ALUs  102 - 103 ), and provide the resulting data back to the input  110 . 
       FIG. 3  shows a more detailed implementation of a single cycle RISC processor  300  in accordance with one embodiment of the present invention. The processor  300  functions in a manner substantially the same as processor  100   FIG. 1 . The processor  300  embodiment explicitly shows additional features with respect to separate external address and data buses  301 - 302 . The processor  300  embodiment also explicitly shows a separate instruction code storage unit  303  coupled to a separate instruction decoder  304 . The processor  300  embodiment also explicitly shows the register file  305  as a 128×8 bit register file. As with processor  100  of  FIG. 1 , processor  300  can be implemented in a manner compatible with the well known microcontroller instruction set standards. Additionally, as with processor  100  of  FIG. 1 , processor  300  can perform a complete instruction execution within a single clock cycle. 
       FIG. 4  shows a flowchart of the steps of a process  400  in accordance with one embodiment of the present invention. As depicted in  FIG. 4 , process  400  shows the operating steps of a single cycle RISC processor (e.g., processor  100   FIG. 1 ) as the processor executes a read-modify-write instruction within a single clock cycle. 
     Process  400  begins in step  401 , where an instruction decoder (e.g., instruction decoder  101 ) of a processor performs an instruction fetch from the output (e.g., output  111 ) of a register file (e.g., register file  104 ). In step  402 , the instruction decoder decodes the fetched instruction. In step  403 , the instruction decoder commands the ALU (e.g., ALUs  102 - 103 ) to execute the decoded instruction (e.g., perform an addition, address computation, branch evaluation, etc.). In step  404 , the resulting output of the instruction execution is coupled to the input of the register file. Subsequently, in step  405 , the resulting output is latched into the register file at the rising edge of the next clock. In this manner, process  400  executes a read-modify-write instruction within a single clock cycle. 
     Thus, embodiments of the present invention provide a RISC type processor that can execute many different types of instructions within a single clock cycle. Embodiments of the present invention increase processor performance by executing many different types of instructions within a single clock cycle and eliminating the latency penalties associated with pipelined bus architectures. 
     The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.