Patent Publication Number: US-6992902-B2

Title: Full bridge converter with ZVS via AC feedback

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   This invention generally relates to the field of power converters, and more particularly, to full bridge converters that operate with zero-voltage switching (ZVS). 
   2. Description of the Prior Art 
   Full-bridge switching power converters are a common DC/DC conversion topology used for supplying high power to a wide variety of electronic components, including telecommunication equipments, computers, servers, etc. A DC/DC switching converter contains an input port typically coupled to a DC power source, such as a battery, to provide DC power to a load connected to an output port. In general, full-bridge converters utilize two bridge legs with four switching elements in the primary side of a transformer that isolates the input port from the output port. Usually, a pulse width modulator is used to regulate the output voltage under various load conditions. 
   Important considerations in the design of converters include power density and conversion efficiency. Power density relates to the amount of delivered power relative to the volume occupied by the power converter, for example in terms of cubic centimeter or cubic inch. As such, for a specified power output, higher density power converters require a smaller size than lower density power converters. Another parameter influencing size of the converter is volt-second product that is applied to inductive converter elements. The volt-second product is a measure of maximum voltage applied during a period of time to the terminals of the inductive elements. 
   Power efficiency is the ratio of input power to output power, usually expressed in terms of percentages. Power efficiency is a measure of internal power losses when converting input power to output power. Switching power converters usually suffer from two types of losses: conduction losses and switching losses. Conduction losses are associated with energy dissipation in the form of heat due to resistive converter elements. Switching losses are associated with the switching elements of the power converter. A common approach utilized to minimize switching losses is known as zero voltage switching (ZVS). 
   A conventional full-bridge (FB) ZVS pulse-width-modulated (PWM) converter used in high-power applications is shown in  FIG. 1 . The major features of this converter are constant-frequency operation and ZVS of the primary switches with a reduced circulating energy. The control of the output voltage at a constant frequency is achieved by a phase-shift technique. In this technique, the turn-on of a switch in the Q 3 –Q 4  leg of the bridge is delayed, i.e., phase shifted, with respect to the turn-on instant of the corresponding switch in the Q 1 –Q 2  leg. If there is no phase-shift between the legs of the bridge, no voltage is applied across the primary of the transformer and, consequently, the output voltage is zero. On the other hand, if the phase shift is 180°, the maximum volt-second product is applied across the primary winding, which produces the maximum output voltage. 
   ZVS is achieved by discharging the energy stored injunction capacitances C 1 , C 2 , C 3  and C 4 , of the switches Q 1 , Q 2 , Q 3  and Q 4  into an inductive element in order to avoid hard switching conditions, before the switches are turned on. In the circuit of  FIG. 1 , the ZVS of the lagging-leg switches Q 3  and Q 4  is achieved primarily by discharging the corresponding junction capacitances C 3  and C 4  via an output filter inductor L F . Since the inductance of L F  is relatively large, the storable energy in L F  is sufficient to discharge this junction capacitances C 3  and C 4  of the switches Q 3  and Q 4  and, consequently, to achieve ZVS even at very light load currents, for example, when the delivered power to the load is substantially less than the rated power of the converter. However, the discharge of the junction capacitances C 1  and C 2  of the leading-leg switches Q 1  and Q 2  is done by the energy stored in the leakage inductance L LK  of the transformer because during the switching of Q 1  or Q 2  the transformer primary is shorted by the simultaneous conduction of rectifiers D R1  and D R2  that carry the output filter inductor current. Since the leakage inductance L LK  is small, the energy stored in L LK  is also small so that ZVS of Q 1  and Q 2  is hard to achieve even at relatively high load currents, for example, when the delivered power to the load is at the rated power of the converter. The ZVS range of the leading-leg switches can be extended to lower load currents by increasing the leakage inductance of the transformer and/or by adding a large external inductor on the primary side in series with the primary of the transformer, as shown in  FIG. 2 . If properly sized, the external inductor L P  can store enough energy to achieve ZVS of the leading-leg switches even at light load currents. However, a large external inductor also stores an excessive amount of energy at full load, i.e., when the delivered power is equal to the rated power, which produces a relatively large circulating energy that increases semiconductor components stress, as well as conversion efficiency. 
   In addition, a large inductance in series with the primary of the transformer extends the time that is needed for the primary current to change direction from positive to negative, and vice versa. This extended commutation time results in a loss of duty cycle on the secondary of the transformer, which further decreases the conversion efficiency. In order to provide full power at the output, the secondary-side duty-cycle loss can be compensated by reducing the turn-ratio of the transformer. With a smaller transformer turn-ratio, however, the reflected output current into the primary is increased, which increases the primary-side conduction losses, thereby creating undesired heat. Moreover, a smaller turn-ratio of the transformer increases the voltage stress on the secondary-side rectifiers. As a result, rectifiers with a higher voltage rating that typically have higher conduction losses may be required. 
   Yet another limitation of the circuit in  FIG. 1  is a severe parasitic ringing at the secondary of the transformer during the turn-off of the rectifier. This ringing is caused by the resonance of the rectifier&#39;s junction capacitance with the leakage inductance of the transformer and the external inductor, if any. In order to control this secondary-side ringing, a snubber or clamp circuit can be employed. For implementations without an external inductor in the primary of the transformer, a passive R-C-D snubber on the secondary-side is usually used, as indicated by dashed lines in  FIG. 2 . For implementations with an external primary inductor the more efficient way to control the secondary-side ringing is to use primary-side clamp diodes D C1  and D C2 , as shown in  FIG. 2 . This primary-side clamp circuit consisting of two clamp diodes was introduced and its operation described in U.S. Pat. No. 5,198,969 by Redl and Balogh. While this circuit offers a practical and efficient solution to the secondary-side ringing problem, it does not offer any improvement in the secondary-side duty-cycle loss. 
   A FB ZVS-PWM converter that achieves ZVS of the primary switches in the entire load and input voltage range with virtually no loss of secondary-side duty cycle and with minimum circulating energy was describe in U.S. Pat. No. 6,356,462 by Jang and Jovanović, which is assigned to the assigner of the present invention. This converter, shown in  FIG. 3 , employs a primary-side inductor connected to the primary center tap of the power transformer to achieve a wide-range ZVS. This converter utilizes the energy stored in the inductor to discharge the capacitance across any switch before it is turned on for achieving ZVS. At high loads, when the phase shift of the bridge is decreased, the inductor is subjected to the lowest volt-second product, with a minimum of 0 volts. At light loads, when the phase shift of the bridge is increased, the inductor is subjected to the highest volt-second product, with a maximum of +−V IN /2. As described in U.S. Pat. No. 6,356,462, since the energy stored in the inductor is decoupled from the output, the inductor does not participate in the parasitic resonance with the junction-capacitance of the secondary-side rectifier. 
   By properly selecting the value of the inductance of the inductor, the primary switches in the converter of  FIG. 3  can achieve ZVS even at no load. This is because the energy required to create ZVS conditions at light loads does not need to be stored in the leakage inductance, and thus, the transformer leakage inductance can be minimized. As a result, the loss of duty cycle on the secondary-side is also minimized, which maximizes the turns ratio of the transformer and, consequently, minimizes the conduction losses. In addition, the minimized leakage inductance of the transformer significantly reduces the secondary-side ringing caused by the resonance between the leakage inductance and junction capacitance of the rectifier, which greatly reduces the power dissipation of a snubber circuit that is used to dampen the ringing. 
   The energy storage capacity of the inductor used for storage of energy used to discharge junction capacitances that achieve ZVS is determined based on e=L*i 2 , where e, L, and I correspond to energy, inductance and current, respectively. As described above, the conventional techniques have relied on increasing the inductance of the inductor used for ZVS energy storage. However, with the ever increasing need to increase power density or otherwise reduce the size of power converters, there is a requirement to decrease the size of the ZVS storage inductor. More specifically, a converter is needed that offers ZVS switching in a wide load range with an acceptable duty cycle loss and reduced primary-side inductor size that is also capable of storing the required energy for achieving ZVS. 
   SUMMARY OF THE INVENTION 
   Briefly, the present invention relates to a converter that provides ZVS in a wide range of input voltage and load current conditions. The converter has an input port for receiving an input power source and an output port for supplying current to a load. At least one power transformer having a primary side and a secondary side converts input power to output power. A bridge having one or more controllable switching devices on the primary side of the transformer operates under the control of a controller that regulates load current. An alternating energy source is coupled to the power transformer and the controllable switching devices, supplying the required energy for switching the controllable switching elements at a substantially low voltage. More specifically, the energy supplied by the alternating energy source is used to turn on the controllable switching devices at a substantially zero voltage. A primary inductor can be used for storing the energy required to create the conditions for switching at least one controllable switching device at substantially low voltage in order to avoid a hard switching condition. The low voltage switching condition can correspond to the condition that achieves ZVS. As such, instead of increasing the inductance for storing the necessary energy to discharge junction capacitances, the converter of the present invention increases the amount of current delivered to the primary inductor, without increasing its size. 
   In an exemplary embodiment, the alternating energy source is an auxiliary transformer and the bridge includes first and second legs, each comprising a pair of controllable switching devices. Unlike the power transformer, which has a power transfer function, the main function of the auxiliary transformer is to supply energy, albeit relatively small, for achieving ZVS. Under this arrangement, the control circuit regulates the power delivered to the load by periodically switching on and off the controllable switching devices in the first and second legs, thereby creating an isolated, constant-frequency, phase-shift-modulated FB ZVS-PWM converter. 
   Finally, it should be noted that the circuits of this invention can be implemented with any type of secondary-side rectifier, for example, a full-wave rectifier with a center-tap secondary winding, full-wave rectifier with a current doubler, or a full-bridge full-wave rectifier. In addition, in all embodiments of the present invention, the primary inductor used for ZVS energy storage can be eliminated by utilizing the leakage inductance of the auxiliary transformer to store the required energy. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a conventional full-bridge ZVS-PWM converter. 
       FIG. 2  shows another conventional full-bridge ZVS-PWM converter with the primary inductor for ZVS energy storage. Also shown with dashed lines are the secondary-side passive R-C-D snubber and primary-side clamp diodes in accordance with a prior art implementation. 
       FIG. 3  shows yet another full-bridge ZVS-PWM converter. 
       FIG. 4  shows an exemplary embodiment for a converter in accordance with the present invention. 
       FIG. 5  shows a simplified circuit diagram for the converter of  FIG. 4 . 
       FIGS. 6(   a )–( e ) show topological stages during one half of the switching period of the converter of the invention: (a) topological stage [T 0 –T 1 ]; (b) topological stage [T 1 –T 2 ]; (c) topological stage [T 2 –T 3 ]; (d) topological stage [T 3 –T 4 ]; (e) topological stage [T 4 –T 5 ]. 
       FIGS. 7(   a )–( n ) show key waveforms of the converter of this invention: (a) control signal for switch S 1 ; (b) control signal for switch S 2 ; (c) control signal for switch S 3 ; (d) control signal for switch S 3 ; (e) voltages V S1  and V S2  across switches S 1  and S 2 ; (f) voltages V S3  and V S4  across switches S 3  and S 4 ; (g) bridge voltage V AB ; (h) primary voltage V P  of power transformer TR; (i) voltage v 2  of winding N 2  of auxiliary transformer TRA; (j) primary current i P  of power transformer TR; (k) current i 2  through winding N 2  of auxiliary transformer TRA; (l) current i D1  through diode D 1 ; (m) current i D2  through diode D 2 ; (n) voltage v S  at the input of output filter. 
       FIG. 8  shows another exemplary embodiment of the converter of the present invention with two winding coupled inductors. 
       FIG. 9  shows another implementation of the converter of  FIG. 8  with three-winding coupled primary inductor. 
       FIG. 10  shows yet another implementation of the converter of  FIG. 8  with two-winding coupled primary inductor. 
       FIG. 11  shows yet another implementation of the converter of the present invention with two-winding coupled primary inductor. 
       FIG. 12  shows an example of the implementation of the converter of the invention where ZVS energy is stored in the leakage inductance of auxiliary transformer TRA. 
       FIG. 13  shows an example of the implementation of the converter of the invention with power transformer TR connected directly across a bridge. 
       FIG. 14  shows the implementation of the converter of the invention with winding N 1  of the auxiliary transformer connected to the midpoint of the leading leg of a bridge. 
       FIG. 15  shows an example of the implementation of the converter of the invention with winding N 1  of the auxiliary transformer connected to a capacitive voltage divider. 
       FIG. 16  shows the implementation of the converter of the invention with a current-doubler rectifier. 
       FIG. 17  shows the implementation of the converter of the invention with a full-bridge, full-wave rectifier. 
       FIG. 18  shows an example of the implementation of the converter of the invention with two transformers. 
       FIG. 19  shows an example of the implementation of the converter of the invention with ZVS commutation circuits employed in two bridge legs. 
       FIG. 20  shows another example of the implementation of the converter of the invention with ZVS commutation circuits employed in both bridge legs. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INVENTION 
     FIG. 4  shows an exemplary embodiment for a converter in accordance with the present invention. The converter in  FIG. 4  is a full bridge converter having an input port for receiving input power source V IN  and an output port for supplying output power to load R L . The converter employs power transformer TR, auxiliary transformer TRA, and a bridge comprising leading-leg primary switches Q 1  and Q 2  and lagging-leg primary switches Q 3  and Q 4 , which are controllable switching devices. A controller regulates the load current by periodically switching controllable switching devices Q 1 , Q 2 , Q 3  and Q 4  into on and off states. Also included in the exemplary converter of the present invention is primary inductance L P , capacitor C B2 , primary diodes D 1  and D 2 , and blocking capacitor C B1 . On the secondary side, the converter in  FIG. 4  includes rectifiers D R1  and D R2  and a low pass filter comprising L f  and C f . As described further in detail below, the present invention provides an isolated phase shift controlled full bridge converter that creates conditions for achieving ZVS, particularly for the leading-leg primary switches Q 1  and Q 2  under a wide range of load currents and with high power intensity. 
   Under this arrangement, power transformer TR is used for the transfer of input power to the output of the converter, while auxiliary transformer TRA functions as an alternating energy source that isolates primary transformer TR from the switches and provides the needed energy for achieving ZVS. As shown, power transformer TR and auxiliary transformer TRA are connected to the leading and lagging legs of the full bridge such that a change in the phase shift between the two legs changes the volt-second product on the windings of power transformer TR and auxiliary transformer TRA. More specifically, a change in the phase shift between the two legs of the bridge increases the volt-second product on the windings of one transformer and decreases the volt-second product on the windings of the other transformer. The load is connected to the secondary winding(s) of power transformer TR whose volt-second product increases as the phase shift between the two legs increases. The primary of auxiliary transformer TRA is connected to the center tap of power transformer TR and ground through blocking capacitor C B1 , whereas its secondary is connected in series with the primary winding of power transformer TR and the leading leg of the bridge through primary inductor L P  that is employed to store the needed energy supplied by auxiliary transformer TRA for zero-voltage switching of the bridge switches Q 1  and Q 2 . Finally, two diodes D 1  and D 2  are connected from the node connecting the primary of power transformer TR and the secondary of auxiliary transformer TRA to the positive and negative (ground) rail of the bridge to provide a path for the current through primary inductor L P . 
   As described in more detail below, when the load current and/or input voltage changes, the phase shift between the bridge legs (comprising the leading-leg primary switches Q 1  and Q 2  and the lagging-leg primary switches Q 3  and Q 4 ) changes so that the volt-second product on the windings of power transformer TR also changes. At the same time, the volt-second product on the windings of auxiliary transformer TRA changes, which changes the energy stored in the primary inductor L P.  This is because the stored energy is proportional to the volt-second product of the secondary of auxiliary transformer TRA. As such, primary inductor L P  is connected in series with the leading-leg primary switches Q 1  and Q 2  for storing the energy supplied by the alternating energy source of the invention, i.e., auxiliary transformer TRA, to create the necessary conditions for switching these controllable switching devices at a substantially low voltage, e.g., substantially zero voltage, so as to avoid hard switching conditions. Due to the adaptive nature of the energy stored in primary inductor L P  which changes as the load current and/or input voltage changes, the present invention can achieve ZVS in a very wide range of input voltage and load current, including no load, with minimum circulating energy. 
   Because the ZVS energy stored in primary inductor L P  is dependent on its inductance value and the volt-second product of the secondary of auxiliary transformer TRA, the size of primary inductor L P  can be minimized by properly selecting the turns ratio of auxiliary transformer TRA. Consequently, the size of primary inductor L P  can be reduced compared to the prior art implementations. 
   In addition, since auxiliary transformer TRA does not need to store energy and is used as an alternating energy source for supplying energy to primary inductor L P , its size can be small. Also, because the sizes of primary inductor L P  and auxiliary transformer TRA are determined by the converter&#39;s maximum output power through the selection of the bridge switches, in particular, their total output capacitance, the sizes of primary inductor L P  and auxiliary transformer TRA do not change significantly as the maximum output power increases. 
   Moreover, since the energy used to create the ZVS condition at light loads is not stored in the leakage inductance of power transformer TR, the transformer&#39;s leakage inductance can also be minimized. As a result of the reduced total inductance, which comprises the inductance of primary inductor L P  and the leakage inductance of power transformer TR, the converter of the invention exhibits a relatively small duty-cycle loss, which minimizes both the conduction loss of the primary switches and the voltage stress on the components of the secondary side of power transformer TR, thereby improving conversion efficiency. Additionally, because of the reduced total inductance, the secondary-side parasitic ringing caused by a resonance between primary inductance L P  and the junction capacitance of rectifier comprising D R1  or D R2  is also reduced and is effectively controlled by primary side diodes D 1  and D 2 , which are connected between the rails and the node connecting the primary of power transformer TR and the secondary of auxiliary transformer TRA. 
   To facilitate the explanation of operation of the circuit in  FIG. 4 ,  FIG. 5  shows its simplified circuit diagram. In the simplified circuit is assumed that inductance of output filter L F  is large enough so that during a switching cycle the output filter can be modeled as a constant current source with the magnitude equal to output current I O . Also, it is assumed that the capacitance of capacitor C B2  is large enough so that the capacitor can be modeled as a constant voltage source. Because the average voltage of the windings of both transformers TR and TRA during a switching cycle must be zero and because when the phase-shift control is used, the pair of switches in each bridge leg operate with 50% duty cycle, the magnitude of the voltage sources that models C B2  is V IN /2. Blocking capacitor C B1 , which is used to prevent the transformer core saturation due to various bridge component mismatching, can be neglected since it has no significant effect on the operation of the circuit. 
   In order to further simplify the analysis, it is assumed that the resistance of the conducting semiconductor switches is zero, whereas the resistance of the non-conducting switches is infinite. In addition, the leakage inductance of the auxiliary transformer TRA and the magnetizing inductances of both transformers are neglected since their effect on the operation of the circuit is not significant. However, capacitances of primary switches C 1 –C 4  and the leakage inductance of power transformer L LK  are not neglected in this analysis since they are important for understanding of the operation of the circuit. Finally, since the turns ratio of the auxiliary transformer TRA, n A =N 1 /N 2 , is designed to be much greater than unity, current i 1  through winding N 1  of TRA is relatively small compared to primary current i P  and can be neglected and is assumed to be i 1 =0. 
     FIGS. 6(   a )–( e ) show topological stages of the converter of this invention during a half of the switching period, whereas  FIGS. 7(   a )–( n ) show its key waveforms. As shown in  FIG. 6(   a ), when diagonal switches S 1  and S 4  are conducting, primary voltage V P  is negative so that the load current is flowing through rectifier D R2  and the lower secondary of power transformer TR. Since during this topological stage, diodes D 1  and D 2  are reverse biased, reflected primary current i P =I O /n, where n=N P /N S , is flowing through the closed switch S 1 , primary inductor L P , winding N 2  of the auxiliary transformer TRA, the primary winding of power transformer TR and closed switch S 4 . It should be noted that in this topological stage, the voltages across the windings of auxiliary transformer TRA are zero, i.e., V 1 =V 2 =0, since the potential of the center tap of power transformer TR is VP/2=V IN /2, as shown in  FIG. 7(   h ). 
   After switch S 4  is turned off at t=T 1 , primary current i P =I O /n starts charging capacitance C 4  of switch S 4  and discharge capacitance C 3  of switch S 3 , as shown in  FIG. 6(   b ). As a result, voltage V S4  across switch S 4  starts increasing toward V IN , whereas voltage V S3  across switch S 3  starts decreasing at the same rate toward zero. At the same time, auxiliary transformer TRA winding voltages V 1  and V 2  start increasing from zero to V IN /2 and V IN /(2n A ), respectively. Because of the increasing voltage V 2 , diode D 1  becomes forward biased, which clamps the potential of node C to V IN.    
   Since the energy for charging C 4  and discharging C 3  is supplied from filter inductor L f , which generally has a large inductance, even at low currents this energy is large enough to completely discharge C 3 , as illustrated in  FIG. 7(   f ). After C 3  is completely discharge, i.e., after voltage across switch S 3  reaches zero at t=T 2 , primary current i P  continues to flow through the antiparallel diode of switch S 3 . To achieve ZVS of switch S 3 , transistor of switch S 3  should be turned on during the conduction of its antiparallel diode, as shown in  FIG. 7(   c ). 
   When the voltage across switch S 3  becomes zero, the voltage across power transformer TR also becomes zero since the primary of the transformer is shorted by simultaneous conduction of S 3  and D 1 , i.e., because voltage V CB =0. As a result, the secondary windings are also shorted so that rectifiers D R1  and D R2  can conduct the load current simultaneously. However, because of leakage inductance L LK  of power transformer TR, almost the entire load current is carried by the lower secondary through rectifier D R2  since no voltage is available to commutate the current, from lower secondary and D R2  to upper secondary and D R1  if ideal components are assumed. With real components, this commutation voltage exists, but is too small to commutate a significant amount of current from the lower to the upper secondary so that even with real components the majority of the current is still found in the lower secondary and its corresponding rectifier D R2 . As a result, during the topological stage when switches S 1  and S 3  are conducting, shown in  FIG. 6(   c ), primary current i P  stays virtually unchanged, i.e., i P =I O /n. 
   Since during the topological stage in  FIG. 6(   c ) diode D 1  is conducting, voltage V 2 =V IN /(2n A ) is applied directly across primary inductor L P,  which linearly increases current i 2  until switch S 1  is turned off at t=T 3 , as illustrated in  FIG. 7(   l ). During time interval T 2 –T 3 , linearly increasing current through diode D 1 , i D1 , is given by 
                   i   D1     ⁡     (   t   )       =           V   2       L   P       ·     (     t   -     T   2       )       =         V   IN       2   ⁢     n   A     ⁢     L   P         ·     (     t   -     T   2       )           ,           ⁢       T   2     ≤   t   ≤     T   3       ,           (   1   )             
 
so that current i 2  is 
                   i   2     ⁡     (   t   )       =         i   P     +       i   D1     ⁡     (   t   )         =         I   O     n     +         V   IN       2   ⁢     n   A     ⁢     L   P         ·     (     t   -     T   2       )             ,           ⁢       T   2     ≤   t   ≤       T   3     .               (   2   )             
 
   After switch S 1  is turned off at t=T 3 , current i 2  begins charging capacitance C 1  of switch S 1  and discharging capacitance C 2  of switch S 2 , as shown in  FIG. 6(   d ). For properly selected turns ratio nA of auxiliary transformer TRA and the value of inductance of L P , energy stored in L P  will be enough to discharge the capacitance of switch S 2  even at no load, as illustrated in  FIG. 7(   e ). After capacitance C 2  is discharged, primary current i P =i 2  continues to flow through the antiparallel diode of switch S 2  so that switch S 2  can be turned on with ZVS, as shown in  FIG. 7(   b ). 
   Because in this topological stage voltage V S1  across switch S 1  that is in opposition to voltage V 2  is increasing, current i D1  starts decreasing. When current i D1  becomes zero at t=T 4 , diode D 1  stops conducting so that primary current i P =i 2  starts decreasing because a negative voltage appears across primary inductor L P  and transformer leakage inductance L LK.  At the same time, load current I O  begins commutating from the lower secondary and its rectifier D R2  into the upper secondary and its corresponding rectifier D R1 . The rate of change of the primary current is given by 
                 ⅆ     i   P         ⅆ   t       =       -       V   IN         L   P     +     L   LK           ≈     -       V     I   ⁢           ⁢   N         L   P                   (   3   )             
 
since L P &gt;&gt;L LK.  
 
   When the commutation of the load current from the lower to the upper secondary is completed, the primary current commutation from positive to negative direction is also finished so that the primary current is i P =−I O /n. After the primary current is commutated in the negative direction, voltages V 1  and V 2  of the windings of auxiliary transformer TRA quickly collapse to zero, as illustrated in  FIG. 7(   h ). 
   The circuit stays in the topological mode shown in  FIG. 6(   e ) with diagonal switches S 2  and S 3  turned on until switch S 3  is turned off at t=T 5 , which marks the end of the first half of the switching period and the beginning of the second half of the switching period. In the second half of the switching period the operation of the circuit is exactly the same as the operation in the first half of the switching period. 
   As already explained, in the connector shown in  FIG. 4 , lagging-lag switches S 3  and S 4  can achieve a complete ZVS turn on even at very light load currents because the energy for creating ZVS conditions is stored in large filter inductor Lf. However, to achieve ZVS of leading-leg switches S 1  and S 2  in a wide load range it is necessary to store enough energy in primary inductor L P  by properly selecting turns ratio n A  of auxiliary transformer TRA and the inductance value of L P . The total energy stored in inductor L P  prior to the turn off of a leading-leg switch and the subsequent turn on of the other leading-leg switch is given by 
                 E   LP     =       1   2     ⁢     L   P     ⁢     i   2   2         ,           (   4   )             
 
Where i 2  is the value of i 2  at the moment of turn off of a leading-leg switch, i.e., at t=T 3  and t=T 7  in  FIGS. 7(   a ) and ( b ).
 
   Since 
                 i   2     ⁡     (     t   =     T   3       )       =         I   O     n     +       i   D1     ⁡     (     t   =     T   3       )                 (   5   )             and                               i   2     ⁡     (     t   =     T   7       )       =     -     (         I   O     n     +       i   D2     ⁡     (     t   =     T   7       )         )         ,           (   6   )             
 
substituting expression (1) for i D1  and i D2  into (4) and recognizing that i D1  and i D2  flow only during the off time (1−D)T S , as shown in  FIGS. 7(   l ) and ( m ), the stored energy in L P  available for ZVS of leading-leg switches can be expressed as 
                 E   LP     =         1   2     ⁢         L   P     ⁡     (         I   O     n     +         V     I   ⁢           ⁢   N         2   ⁢     n   A     ⁢     L   P         ⁢     (     1   -   D     )     ⁢     T   S         )       2       =       1   2     ⁢         L   P     ⁡     (         I   O     n     +         V     I   ⁢           ⁢   N       ⁡     (     1   -   D     )         2   ⁢     n   A     ⁢     L   P     ⁢     f   S           )       2           ,           (   7   )             
 
where f S =1/T S  is the switching frequency.
 
   Neglecting the transformer winding capacitances and any other parasitic capacitance, to achieve ZVS of leading-leg switches, stored energy E LP  must be at least equal to the energy required to charge up the capacitance of the leading-leg switch that is turning off to V IN  and discharge the capacitance of the leading-leg switch that is about to be turned on to zero, i.e.,
 
 E   LP ≧2 CV   IN   2 .  (8)
 
   From (7) and (8), it follows that the ZVS condition is 
                   L   P     ⁡     (         I   O     n     +         V   IN     ⁡     (     1   -   D     )         2   ⁢     n   A     ⁢     L   P     ⁢     f   S           )       2     ≥     4   ⁢       CV   IN   2     .               (   9   )             
 
   As can be seen from (9), at full load I O(MAX)  almost the entire energy stored in L P  is from the output current reflected into the primary since for a properly designed converter D≈1 at full load. Therefore, at full load the ZVS condition can be expressed as 
                   L   P     ⁡     (       I     O   ⁡     (   MAX   )         n     )       2     ≥     4   ⁢           ⁢   C   ⁢           ⁢       V   IN   2     .               (   10   )             
 
   However, according to (9), at no load (I O =0) the entire energy stored in L P  is due to currents i D1  or i D2 . Since at no load (or light loads) D&lt;&lt;1, the ZVS condition at no load can be rewritten as 
                   L   P     ⁡     (       V   IN       2   ⁢     n   A     ⁢     L   P     ⁢     f   S         )       2     ≥     4   ⁢           ⁢   C   ⁢           ⁢       V   IN   2     .               (   11   )             
 
   Expressions (10) and (11) can be used to estimate the required value of primary inductance L P  and the turns ratio of auxiliary transformer n A . From (10), L P  can be calculated as 
                 L   P     ≥       4   ⁢     CV     IN   ⁡     (   MAX   )       2           (       I     O   ⁡     (   MAX   )         /   n     )     2         ,           (   12   )             
 
where V IN(MAX)  is the high line input voltage since it represents the worst-case input voltage. To minimize amount of the full load circulating energy and the size of inductor L P , the smallest value of L P  that satisfies (12) should be taken, i.e., 
               L   P     ≈         4   ⁢           ⁢   C   ⁢           ⁢     V     IN   ⁢           ⁢     (   MAX   )       2           (       I     O   ⁡     (   MAX   )         /   n     )     2       .             (   13   )             
 
   Once L P  is determined according to (13), the desired range of n A  can be calculated from (11) as 
               n   A     ≤       1     4   ⁢           ⁢     f   S     ⁢       CL   P           .             (   14   )             
 
   To minimize the amount of no-load circulating energy and the size of the auxiliary transformer, the turns ratio of the auxiliary transformer should be maximized, i.e., n A  should be selected so that 
               n   A     ≈       1     4   ⁢           ⁢     f   S     ⁢       CL   P           .             (   15   )             
 
   With L P  and n A  selected according to (13) and (15), the circuit of this invention achieves a complete ZVS in the entire load range, i.e., from full load down to no load. 
   It should be noted that the value of primary inductance L P  in the circuit of this invention is many times smaller than the value of primary inductance L P  required to achieve ZVS of the primary switches in the conventional phase-shifted converter shown in  FIG. 2 . In fact, the value of L P  in the conventional converter L P(CONV)  is determined by the condition that L P(CONV)  has enough energy to achieve ZVS at the minimum desirable current, i.e., 
                 L     P   ⁡     (   CONV   )         ≥       4   ⁢           ⁢   C   ⁢           ⁢     V     IN   ⁢           ⁢     (   MAX   )       2           (       I     O   ⁡     (   MIN   )         /   n     )     2         ,           (   16   )             
 
where I O(MIN)  is the minimum current at which complete ZVS can be achieved.
 
   From (13) and (16), the ratio of the values of the primary inductor in the circuit of this invention and the conventional circuit is 
                 L   P       L     P   ⁡     (   CONV   )           =         (       I     O   ⁡     (   MIN   )           I     O   ⁡     (   MAX   )           )     2     .             (   17   )             
 
   Therefore, to achieve ZVS in the conventional circuit from full load I O(MAX)  down to only 50% of full load, L P(CONV)  must be four times larger than L P  in the circuit of this invention. To extend the ZVS range down to 30% of full load, L P(CONV)  that is nine times larger than L P  is required. The required value of L P(CONV)  can be somewhat reduced by increasing the magnetizing current (reducing the magnetizing inductance) of the transformer, since the increased magnetizing current that flows through L P(CONV)  increases the energy stored in L P(CONV) . Even with the optimally selected magnetizing inductance of the transformer, the required L P(CONV)  is substantially larger than required L P  in the circuit of this invention. 
   Because of a substantially reduced value of primary inductance L P  compared to the required value of L P(CONV)  in the conventional phase-shifted full-bridge converter, the secondary-side duty-cycle loss of the circuit of this invention is also substantially reduced compared to that of the conventional full-bridge ZVS-PWM converter. At the same time, the reduced value of L P  reduces the energy in the parasitic ringing on the secondary side. In fact, this parasitic ringing is very much suppressed in the circuit in  FIG. 4  because diodes D 1  and D 2  clamp the primary voltage of power transformer TR to the input voltage. Since the leakage of the power transformer in the circuit of this invention can be minimized because it is not used to store ZVS energy, the primary winding clamping also effectively clamps the secondary winding voltage. Any parasitic ringing due to the residual leakage inductance of the transformer can be controlled with a small (low-power) snubber circuit. 
   The exemplary circuit of this invention shown in  FIG. 4  can be implemented in a variety of ways. For example,  FIGS. 8 through 11  show some of the implementations with primary inductor L P  implemented as a two- or three-winding coupled inductor. The principle of operation of the circuits in  FIGS. 8 through 11  is the same as that of the circuit in  FIG. 4 . It also should be noted that the circuit of this invention can be implemented without inductor L P , as shown in  FIG. 12 . In the implementation in  FIG. 12 , the energy required for ZVS of leading-leg switches is stored in the leakage inductance of auxiliary transformer TRA. Of course, this implementation requires that auxiliary transformer TRA be designed with a proper value of the leakage inductance. 
   The circuit of this invention can also be implemented as shown in  FIG. 13 . In the implementation in  FIG. 13 , power transformer TR is directly coupled across the bridge legs so that the reflected load current into the primary is not flowing through primary inductor L P . By minimizing the leakage inductance of power transformer TR, the secondary-side duty-cycle loss can virtually be eliminated. 
   Generally, the circuits of this invention can also be implemented by connecting winding N 1  of auxiliary transformer TRA to any point in the circuit whose average voltage is V IN /2 instead of connecting it to the center tap of power transformer TR. An example of this implementation is shown in  FIG. 14 . The only difference between the circuit in  FIG. 14  and the circuit in  FIG. 4  is that the amount of energy stored in primary inductor L P  in the circuit in  FIG. 14  is independent of the load current and input voltage since a constant volt-second product is applied across L P  because, with the phase-shift control, the leading-leg switches always operate with 50% duty cycle.  FIG. 15  shows another implementation of the circuit in  FIG. 14 , where winding N 1  is connected to a capacitive divider that provides voltage V IN /2. Under this arrangement, the energy supplied by the alternating energy source is independent of current changes within the converter. 
   The converter of the invention shown in  FIG. 4  and any of its variations can be implemented with any type of secondary-side rectifier.  FIGS. 16 and 17  show implementations with a current doubler and a full-bridge full-wave rectifier, respectively. Furthermore, the circuits of this invention can also be implemented with multiple transformers as, for example, shown in  FIG. 18 . 
   Finally, the circuit of this invention can also be implemented with the described ZVS commutation network consisting of an auxiliary transformer and a primary inductance connected to each of the bridge legs, as shown in  FIGS. 19 and 20 . Under this arrangement, the lagging-leg switches Q 3  and Q 4  use a ZVS commutation network to achieve ZVS in a wide load and input-voltage range. Of course, the lagging-leg switches Q 3  and Q 4  can use the energy stored in the output-filter inductor to create the ZVS conditions. 
   It should be noted that the circuit of this invention could also be implemented with a primary-side ZVS commutating network consisting of a primary inductor, an auxiliary transformer, and a pair of diodes connected to each of the bridge-legs. 
   The control of the circuits of this invention is the same as the control of any other constant-frequency FB ZVS converter. In fact, any of the integrated phase-shift controllers or PMW controllers available on the market can be used to implement the control of the proposed circuit. 
   Finally, it also should be noted the above detailed descriptions are provided to illustrate specific embodiments of the present invention and are not intended to be limiting. Numerous other variations and modifications within the scope of this invention are possible. The present invention is set forth in the following claims.