Patent Publication Number: US-11646171-B2

Title: Scanning ion beam etch

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional of U.S. patent application Ser. No. 16/398,487 entitled: Scanning Ion Beam Etch filed on Apr. 30, 2019, which claims the benefit of U.S. Patent Application No. 62/666,324, filed on May 3, 2018, the contents of which is incorporated herein by reference in its entirety. 
    
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     n/a 
     TECHNICAL FIELD 
     The present disclosure relates to the field of charged particle sources including plasma sources for direct etching and deposition, broad-beam ion sources for ion beam deposition and etching, and electron sources for surface modification. 
     BACKGROUND 
       FIG.  1    illustrates an ion beam etch (IBE) system. In an IBE process, wafer  180  is placed in front of an ion source  105 . At least one surface of the wafer  180  can be exposed to a beam  130 . Ion source  105  can be comprised of a plasma chamber  110 , and an ion extraction grid system  150 . Ion extraction grid system  150  is comprised of a plurality of conducting plates that have multiple holes therein aligned from plate to plate. Grid system  150  extracts and helps collimate ion beamlets coming out of each of the holes of the plates, and forms a substantially collimated ion beam  130 . Plasma in the plasma source may be generated by methods known in the art including direct current (DC) and radio frequency (RF) inductively coupled plasma (ICP) coils  160 . The energy of the ions extracted from the ion source  105  is defined by the voltages applied to the grid system  150 . 
     An electron source  230 , may be placed between the ion extraction grid system  150  and a wafer stage to prevent charge damage from the impinging ions on the wafer. Wafer  180 , is placed on wafer stage  140 . The stage  140  can rotate the wafer about a central axis  220 . The stage  140  can tilt the wafer  180  with respect to the ion beam  130  for at least a portion of the etching process. Ions from the beam  130  can be directed at any angle with respect to the wafer surface by tilting the wafer  180 . Any solid material can be etched with an IBE process. Provisions may be made on the wafer stage  140  to cool the wafer  180  during the etching process to prevent thermal damage to the devices on the wafer  180 . Wafer  180  may also be heated to a specific temperature to enhance the ion beam etching process. 
     A typical wafer  180  can include many devices and may be covered with photoresist masks or other type of masks. The devices can be processed with ion beam exposure to etch the desired shape of the devices on the wafer  180 . The desired shape of the devices can be achieved by adjusting process parameters including, for example: wafer tilt angle during etch, duration of etch, beam energy, beam current, Photoresist mask sidewall angles, wafer temperature, etc. An end point detector  240  may be placed in line of sight of the wafer  180  when the devices are made of multilayer materials and precise end pointing of the etch at a predetermined layer is often desired. 
     The devices on wafer  180  being etched are expected to show similar shapes (e.g., sidewall profiles, etc.) However, devices can show different shapes depending on the location of the devices on the wafer  180 . One example of a specific type of shape difference is called inboard and outboard asymmetry.  FIGS.  2   a - 2   c    show a schematic representation of the asymmetry of the inboard (IB) side  191  of a device and the outboard (OB) side  192  of a device after ion beam etching. The asymmetry may be quantified as the sidewall angle differences on one side a versus the opposite side β.  FIG.  2   a    shows symmetric etching.  FIG.  2   b    and  FIG.  2   c    show asymmetric etching. 
     The asymmetry of the D 3  side  191 , and the OB side  192  of devices in ion beam etching often has a specific relationship to the tilting of the wafer  180 . This relationship is shown in  FIGS.  3   a - 3   b   .  FIG.  3   a    is a top view of a wafer  180  being etched. The tilt axis runs along the diagonal of the wafer as shown with respect to the wafer top view. In  FIG.  3   a   , wafer  180  is being etched by an ion beam impinging on it from a direction perpendicular to the plane of the paper.  FIG.  3   b    is a cross section view of  FIG.  3   a    along the wafer diagonal perpendicular to the tilt axis. In  FIG.  3   b   , the wafer cross-section, direction of tilt axis runs along the middle of the wafer, and perpendicular to the plane of the paper. Asymmetry between the D 3  side  191  of the device and the OB side  192  of the device can be seen on the devices located towards the top and bottom of the wafer  180 . The asymmetry becomes more pronounced the further away the device is from the tilt axis, and as the tilt angle is increased, e.g., the wafer  180  is tilted further from the normal angle of incidence of the incident beam. 
     In a perfect ion source, and grid system, all beamlets would be perfectly collimated, with no divergence of the ions from the intended direction. In such a system, all features etched on the wafer  180  would be perfectly symmetrical. Practical ion beam etch systems have non-zero beam divergence. 
     In practice, ion sources generate an ion beam that is a collection of beamlets with a finite non-zero beam divergence, as illustrated in  FIG.  4   . Beamlet divergence  131  is shown in this figure. A consequence of the beamlet divergence is that as the wafer is tilted away from normal beam incidence, there will be more intense etching on the side of the wafer  180  nearer to the ion source, and less intense etching on the side of the wafer  180  farther from the ion source. By rotating the wafer  180  about an axis  220 , the etch depths can be made more uniform in the areas of the wafer  180  that are feature free. Devices on the wafers  180  however are typically made of features in 3-dimensions and not flat surfaces. On 3-dimensional features on the wafer  180 , the effect of the tilting of the wafer  180  away from normal beam incidence, in conjunction with beam divergence, is that the inboard side  191  of the devices on the wafer  180  will experience a different amount of beam exposure than the outboard side  192  of the devices. This inboard and outboard asymmetry becomes more pronounced as the location of the devices is farther away from the tilt axis of the wafer  180 , and as the tilt angle is increased away from normal beam incidence. 
     Translating (e.g., scanning) the wafer  180  across the beam can address asymmetry between the inboard side  191  of the device and the outboard side  192  of the device. In  FIG.  5   , the region marked by double ended arrow  550  is the region where ion beam exposure of the wafer occurs. A single instance of translation of the wafer, translation starting at any point where all regions of the wafer is outside of the region shown by  550 , translation path taking the wafer through the region represented by  550 , is considered one scan. In  FIG.  7   , region  550 , where ion beam exposure occurs is defined through the introduction of physical beam blocks  171 , and  172 . 
     In some embodiments, the path of the wafer  180  during translation is defined as the scan path. The scan path can be within a plane that is parallel (or nearly parallel) to the plane of the tilted wafer surface for at least one scan. The scan path of wafer translation can be linear for at least one scan. The path of wafer translation can be non-linear (e.g., curved) for at least one scan. The scan path can be parallel to the tilted wafer  180  for at least one scan. The wafer tilt can be constant during the scan path for at least one scan. The wafer tilt can vary along the path of the scan for at least one scan. The scan path can be parallel to the wafer  180  during at least one point in the scan for at least one scan. The scan path can be parallel to the wafer  180  at all points during the scan for at least one scan. The scan path can be in a different plane than the wafer  180  for at least one scan. The scan path can be within a plane that is parallel (or nearly parallel) to the plane of the tilted wafer surface for all scans. The scan path of wafer translation can be linear for all scans. The path of wafer translation can be non-linear (e.g., curved) for all scans. The scan path can be parallel to the tilted wafer  180  for all scans. The wafer tilt can be constant during the scan path for all scans. The wafer tilt can vary along the path of the scan for all scans. The scan path can be parallel to the wafer  180  during at least one point in the scan for all scans. The scan path can be parallel to the wafer  180  at all points during the scan for all scans. The scan path can be in a different plane than the wafer  180  for all scans. 
     SUMMARY OF THE INVENTION 
     In accordance with an embodiment, the present disclosure relates to using asymmetric scanning velocity in an ion beam etch process to correct asymmetry of etching between the inboard side and the outboard side of device structures on a wafer while maintaining the overall uniformity of etch across the full wafer. 
     In accordance with another embodiment, the present disclosure relates to using asymmetric scanning velocity in an ion beam etch process to generate exaggerated asymmetry of etching between inboard and outboard sides of devices on a wafer, while maintaining the overall uniformity of etch across the full wafer. 
     In accordance with another embodiment, the present disclosure relates to using symmetric velocity scanning to enable control of inboard and outboard asymmetry even when the ion beam system is configured with a small ion source, and small grids. Without asymmetric velocity scanning, the ion source and grids will need to be of a lateral dimension larger than the sum of the wafer diameter, two times the beamlet divergence projected on the plane of the scan, and the ion beam density will need to be highly uniform across the lateral dimension. 
     In accordance with another embodiment, the present disclosure relates to using asymmetric velocity scans combined with symmetric velocity scans to address the inboard and outboard asymmetry and wafer etch uniformity, where the number of scans needed to finish the etch process may be a single scan or multiple scans. 
     In accordance with another embodiment, the present disclosure relates to a process whereby scan motion may be a straight linear motion of the wafer center across the ion beam or may include slight deviations from straight lines such as curved paths of motion of the wafer center across the ion beam. 
     In accordance with another embodiment, the present disclosure relates to an alternative to asymmetric velocity scan motion of the wafer where the ion beam current or the ion beam voltage is modulated as the wafer moves across the ion beam. The wafer may be exposed to either larger beam current or higher beam voltage when the wafer center is scanning on the far side of the scan beyond the mid-plane of the ion source. 
     In accordance with another embodiment, the present disclosure relates to an alternative to an asymmetric velocity profile scan by modulating the path of the scan, so that the wafer spends more time exposed to the ion beam on the far side of the scan after the wafer has passed the mid-plane of the ion source. 
     In accordance with another embodiment, the present disclosure relates to an alternative to the asymmetric velocity scan of the wafer across an ion beam by placing beam blocks in an asymmetric fashion with respect to the mid-plane of the ion source and grids, so that the wafer spends more time exposed to the ion beam on the far side of the scan even with the symmetrical velocity profile of the scan. 
     According to one aspect of an embodiment of the present disclosure, a method of correcting asymmetry during a wafer etching process is provided, where the method includes producing a plasma from a plasma source, the plasma source comprising a plasma chamber and an ion extraction grid system, the ion extraction grid system configured to produce an ion beam from the plasma, the ion beam having a central axis, supporting a wafer on a stage, scanning the wafer relative to the ion beam along a scan path, and modifying applied beam flux as a function of a position of the wafer. 
     According to another aspect of an embodiment of the present disclosure, a method of correcting asymmetry during a wafer etching process is provided, where the method includes producing a plasma from a plasma source, the plasma source comprising a plasma chamber and an ion extraction grid system, the ion extraction grid system configured to produce an ion beam from the plasma, the ion beam having a central axis, supporting a wafer on a stage including at least one of rotating the stage about the central axis and tilting the stage with respect to the ion beam during at least a portion of the etching process, scanning the wafer relative to the ion beam along a scan path in accordance with a scan velocity function, and modifying applied beam flux as a function of a position of the wafer by varying the scan velocity function as the wafer travels along the scan path. 
     According to another aspect of an embodiment of the present disclosure, a method of correcting asymmetry during a wafer etching process is provided, where the method includes producing a plasma from a plasma source, the plasma source comprising a plasma chamber and an ion extraction grid system, the ion extraction grid system configured to produce an ion beam from the plasma, the ion beam having a central axis, supporting a wafer on a stage, scanning the wafer relative to the ion beam along a scan path, the scan path comprising a scan out path from the first end of the ion beam to the second end of the ion beam according to a scan out velocity function and a scan back path from the second end of the ion beam to the first end of the ion beam according to a scan back velocity function, wherein one of the scan out velocity function and the scan back velocity function varies as a function of time, and modifying applied beam flux as a function of a position of the wafer. 
     According to another aspect of an embodiment of the present disclosure, a method of correcting asymmetry during a wafer deposition process is provided, where the method includes producing a plasma from a plasma source, the plasma source comprising a plasma chamber and an ion extraction grid system, the ion extraction grid system configured to produce an ion beam from the plasma, the ion beam having a central axis, supporting a wafer on a stage, scanning the wafer relative to the ion beam along a scan path, and modifying applied beam flux as a function of a position of the wafer. 
     Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or can be learned by practice of the herein disclosed principles. The features and advantages of the disclosure can be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other features of the disclosure will become more fully apparent from the following description and appended claims, or can be learned by the practice of the principles set forth herein. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In order to describe the manner in which the above-recited and other advantages and features of the disclosure can be obtained, a more particular description of the principles briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only exemplary embodiments of the disclosure and are not therefore to be considered to be limiting of its scope, the principles herein are described and explained with additional specificity and detail through the use of the accompanying drawings in which: 
         FIG.  1    illustrates an ion beam etch system; 
         FIG.  2   a    illustrates symmetric etching; 
         FIG.  2   b    illustrates asymmetric etching; 
         FIG.  2   c    illustrates asymmetric etching; 
         FIG.  3   a    is a top view of a wafer  180  being etched; 
         FIG.  3   b    is a cross section view of  FIG.  3   a    along the wafer diagonal perpendicular to the tilt axis; 
         FIG.  4    illustrates ion beam divergence; 
         FIG.  5    illustrates an improved scanning ion beam etch system according to an embodiment of the present disclosure; 
         FIG.  6    illustrates an improved scanning ion beam etch system according to an embodiment of the present disclosure; 
         FIG.  7    illustrates an improved scanning ion beam etch system according to an embodiment of the present disclosure; 
         FIG.  8    illustrates variable scan velocity according to an embodiment of the present disclosure; 
         FIG.  9    illustrates relative etch from the wafer center with constant scan velocity and variable scan velocity according to an embodiment of the present disclosure; 
         FIG.  10   a    illustrates beamlet divergence and effect of divergence on the inboard side of the wafer versus the outboard side of wafer as the wafer is scanned across beam according to an embodiment of the present disclosure; 
         FIG.  10   b    illustrates beamlet divergence and effect of divergence on the inboard side of the wafer versus the outboard side of wafer as the wafer is scanned across beam according to an embodiment of the present disclosure; 
         FIG.  11   a    illustrates a beam that has a higher flux at the center of the beam; 
         FIG.  11   b    illustrates a uniform beam where the flux is independent of position in the beam; 
         FIG.  12    illustrates the mid-plane of the source and far side of scan where preferential etching of the outboard side of devices occurs; 
         FIG.  13    illustrates one type of asymmetric velocity profile (solid lines) that preferentially etches the outboard side on the far side of the scan compared with a symmetric velocity (dashed lines) scan; 
         FIG.  14    illustrates the mid-plane of the source, and near side of scan where preferential etching of the inboard side of the devices occurs; and 
         FIG.  15    illustrates one type of an asymmetric velocity profile that is a step type (solid lines) that preferentially etches the outboard side on the far side of the scan compared with an asymmetric velocity profile that is smoothly changing type (dashed lines) scan. 
     
    
    
     Similar reference characters refer to similar parts throughout the several views of the drawings. 
     DETAILED DESCRIPTION 
       FIG.  5    shows an illustration of an improved scanning ion beam etch (IBE) system of the present disclosure. Wafer  180  can be tilted off normal incidence with respect to the ion beam, and scanned across the beam starting from outside the beam on one end to the outside of the beam on the opposite end. 
     In some embodiments, in order to compensate for a non-uniform beam flux, the wafer scan velocity can be varied during a wafer scan. As shown in  FIG.  5   , the wafer  180  is typically scanned back and forth in and/or through the beam  130 . A typical wafer scan can start with the wafer  180  in position  500 . The wafer  180  is scanned (e.g., translated) through the beam to position  510 . The wafer  180  can then be scanned (e.g., translated) back through the beam from position  510  to position  500 . The wafer  180  can be stopped (e.g., zero velocity) between scans (at either or both positions  500  and  510 ). The path from position  500  to position  510  and back again to position  500  can be a continuous path. The path the wafer  180  follows scanning from position  500  to position  510  can be the same as the path the wafer  180  follows scanning from position  510  to position  500 . The path the wafer  180  follows scanning from position  510  to  500  can be different from the path the wafer  180  follows scanning from position  500  to position  510 . 
     The wafer  180  in position  500  and/or position  510  can be at least partially exposed to the beam. The wafer  180  in position  500  and/or position  510  can be completely exposed to the beam. The wafer  180  in position  500  and/or position  510  can be at least partially outside (e.g., not exposed to) the beam. The wafer  180  in position  500  and/or position  510  can be completely outside (e.g., not exposed to) the beam. The position of  500  and/or  510  can be invariant between at least two scans. The position  500  and/or  510  can be invariant for more than two scans. The position  500  and/or  510  can be invariant for all scans. The position of  500  and/or  510  can be changed between at least two scans. The position  500  and/or position  510  can be changed between more than two scans. The position  500  and/or position  510  can be changed between every scan. The length of the wafer scan (e.g., the distance between point  500  and  510 ) can be constant for at least 2 scans. The length of the wafer scan be constant for all scans. The length of the wafer scan can be different between at least 2 scans. The length of the wafer scan can be different in more than 2 scans. The length of the wafer scan can be different for all wafer scans. 
     In some embodiments, at least a portion of the wafer  180  can start the scan outside the ion beam. All of the wafer  180  can start the scan outside the ion beam. A portion of the wafer  180  can be exposed to the beam during a scan. All of the wafer  180  can be exposed to the beam during the scan. A portion of the wafer  180  can be outside the beam (e.g., not exposed to the beam) at the end of a scan. All of the wafer  180  can be outside of the beam (e.g., not exposed to the beam) at the end of a scan. In one embodiment, the wafer  180  is not exposed to the beam at the start of a scan, a portion of the wafer  180  is exposed to the beam during the scan, and the wafer  180  is not exposed to the beam at the end of the scan. The wafer  180  can be scanned back and forth at a desired tilt angle with respect to the ion beam. The wafer  180  can be rotated about an axis  220  as it is scanned across the beam. The rotation speed can be constant during the scan. The rotation speed can vary during the scan. The process of scanning at fixed scan velocity can repeated until the desired etch depth is achieved. The scan path can be centered in the beam (e.g., the midpoint of the scan approximately coincides with the center of the beam). The scan path can be offset in the ion beam (e.g., the midpoint of the scan does not coincide with the center of the beam). 
     This scanning method addresses the inboard and outboard asymmetry arising from the tilt of the wafer  180  and the divergence of the beamlets that cause the near side of the wafer  180  to be etched at a higher rate than the far side of the wafer  180  in a conventional ion beam etch (IBE) machine. 
     Many ion beam operations, such as, ion beam smoothing, sidewall etching, and sidewall cleaning, require a large tilt angle with respect to the ion beam. The wafer  180  can be tilted greater than approximately 10 degrees off normal incidence of the ion beam. The wafer  180  can be tilted greater than 30 degrees off normal incidence of the ion beam. Scanning at large tilt angles as shown in  FIG.  6   , can result in the mid-point of the scan moving further away from the ion source, and the scan length increasing in order to be able to scan the wafer  180  across the ion beam. The increased scan length and the larger distance between the wafer  180  and the source can be difficult to accommodate in a High Vacuum/Ultra High Vacuum Chamber. 
     The required scan length can be decreased by inserting physical blocks,  171  and  172 , towards the ends of the scan, as shown in  FIG.  7   . The blocks  171  and  172  form an aperture that narrows the beam  130 , thus creating a portion or “slit” of the ion beam through which the wafer  180  is scanned. The blocks  171  and  172  may be inserted symmetrically with respect to the mid-plane  310  of the ion source  105  and ion extraction grid system  150  as shown in  FIG.  7   . The blocks  171  and  172  can be inserted asymmetrically with respect to the mid-plane  310 . The slit width can be made adjustable by adjusting the positions of the upper block  171 , or the lower block  172 , or both. However, in cases where scanning the wafer  180  across the slit at large tilt angles is required, the distance from the ion extraction grid system  150  to the wafer  180  at its scan midpoint can be much larger than in conventional ion beam etch (IBE) systems. 
     In practical IBE systems, the beam density of beam  130  can be spatially non-uniform. This non-uniformity can be due to beamlet divergence. This effect often increases as the source-to-wafer distance increases and can be amplified by a large distance between the wafer scan&#39;s mid-point. Scanning the wafer  180  through the beam  130  at constant scan velocity can result in an etch that is highly non-uniform, with the wafer center etching much faster than the edge of the wafer. Deploying a variable scan velocity, as illustrated in the schematic in  FIG.  8   , can dramatically improve the etch uniformity over the entire wafer  180 . Slowing down the velocity of the scan when the wafer  180  is away from the midpoint of the scan can enhance the etching at the points of the wafer  180  away from its center. 
     In some embodiments, the wafer velocity can be changed during the wafer scan. The wafer scan velocity can be continuously changing during a scan. The wafer scan velocity can be constant during some portion of a scan. The wafer velocity profile can be identical for at least 2 scans. The wafer scan velocity profile can be identical for all scans. The wafer scan velocity can change between at least two scans. The wafer scan velocity profile can change for each scan. The wafer scan velocity can be zero during at least one point during the scan. The wafer velocity profile can be symmetric (see  FIG.  8    for example). The scan velocity profile can be monotonic. The scan velocity profile can be discontinuous. 
     Examples of symmetric variable velocity to achieve highly uniform etching over the full wafer  180  are shown in  FIG.  8   . The midpoint of the scan is represented by X=0. The direction of the scan is along the x-axis. The negative x-axis positions are closer to the ion source  105  than the positive x-axis positions. Variable velocity, which is symmetric about the mid-point of the scan, is shown in the example in  FIG.  8   . Symmetric variable velocity of the scan can be used to obtain uniform etching across the wafer  180 . The symmetric variable velocity profile can be a step function, or a smooth function, as shown in the example in  FIG.  8   . Symmetric variable velocity as shown in the example here is used to obtain uniform etching across the full wafer  180 , as shown in  FIG.  9   . 
     Scanning the wafer  180  across the beam  130  does not address a second cause of inboard and outboard asymmetry of devices. This second cause of asymmetry is caused by the large distance needed to enable the scanning of a tilted wafer  180  across the beam  130 , the finite size of the ion source  105  and ion extraction grid system  150 , and the beamlet divergence. This effect is illustrated in  FIGS.  10   a - 10   b   . At large distances, the finite lateral size of the ion source  105 , and the beamlet divergences cause the inboard side  191  of the devices to be exposed to larger amount of ions compared to the outboard side of the device. This asymmetry is present at all tilt angles. This is illustrated in  FIGS.  10   a - 10   b   . A rotating wafer  180 , as it is being scanned across the beam  130 , causes the outboard side  192  of the device, at the outer edges of the wafer  180 , to etch much less than the inboard side  191  of the device as seen in  FIGS.  10   a - 10   b   . Solid angles projected from the inboard side  191  of the device and the outboard side  192  of the device, to the plane of the ion extraction grid system  150 , represent the amount of beam exposure on the inboard side  191 , and outboard side  192  respectively, as the wafer  180  is scanned across the beam  130 . The imbalance of the beam exposure of the inboard side  191  and outboard side  192  of the devices can be clearly seen in  FIG.  10   a    and  FIG.  10     b.    
     The inboard and outboard etch asymmetry associated with the finite dimension of the ion source  105  and beamlet divergence can be addressed by making the ion source  105  and grids of ion extraction grid system  150  significantly larger in the Y-axis direction, as shown in  FIGS.  11   a - 11   b   .  FIG.  11   a    shows a beam  130  that has a higher flux at the center of the beam  130 . It is possible to have a beam  130  that has a higher flux at the edge of the beam  130  than at the center of the beam  130  (not shown).  FIG.  11   b    shows a uniform beam  130  where the flux is independent of the position in the beam  130 . The Y-axis direction is the direction of a scan. Increasing the lateral dimension of the ion source  105  and grids of the ion extraction grid system  150  to be at least equal to the sum of wafer diameter and twice the beamlet divergence and making the ion flux uniform across the lateral dimension, as shown in  FIG.  11   b   , can allow both the inboard side  191  and outboard side  192  of the devices to be exposed to the same amount of ion beam exposure, and eliminate the asymmetry between the inboard side  191  and outboard side  192  of the devices. 
     The non-ideal ion beam shown in  FIG.  11   a    shows an example of when the flux of the ion beam  130  is higher in the center of the beam  130  compared to an edge of the beam  130 . It is possible to have an ion beam  130  where the flux of the ion beam  130  is higher at an edge of the beam  130  compared to the center of the beam  130  (e.g., through magnetic confinement of the beam, a non-uniform grid system, etc.). In this case, it may be desirable to increase the dose in the center of the wafer  180  compared to the edge of the wafer  180  during a scan. The scan velocity at an end of a scan can be greater than the scan velocity in the center of the scan (e.g., the scan velocity for at least one point towards the end of the scan is higher than a point toward the center of the scan). 
     Establishing and sustaining uniform plasma distribution across a large ion source  105  can be practically difficult. Large variations in plasma density across the lateral dimensions of the plasma source can be difficult to address. Large lateral dimension of grids can cause failures arising from mechanical instabilities related to thermal expansion and contraction cycles of ion source operation. Due to extraordinary challenges associated with larger dimensions of ion sources and large sized grids, it is desirable to address the asymmetry problem with a smaller ion source, and smaller grids. 
     Referring to  FIG.  12   , slowing down the scan velocity when the wafer center is on the far side of the scan  301  (e.g., wafer scan positions farther from the ion beam source  105 ) can also improve uniformity. As shown in  FIG.  12   , the scan velocity can be reduced for at least a portion of points below the mid-plane  310  of the ion source  105  and ion extraction grid system  150 . The reduced scan speed enhances the etching on the outboard side  192  of the devices. By slowing down the scan speed when the wafer center is on the far side of the scan, inboard and outboard asymmetry, which can be present in a symmetric velocity scan, can be improved. 
       FIG.  13    shows an example of a scan velocity profile described by the system of the present disclosure. In the schematic shown in  FIG.  13   , the positive x positions are the far side positions  301  of the wafer center where the scan speed is reduced to increase the etching on the outboard side  192  of the device. Overall excellent uniformity of etching across the full wafer  180  is preserved by increasing the scan velocity on the negative X side of the scan (e.g., when the wafer  180  is closer to the ion source  105 ), than what a symmetric variable scan profile  303  requires for good uniformity. 
     A scan velocity can be a function of the wafer distance from the ion beam  105  during a scan. A scan velocity can decrease as the distance between the wafer  180  and the ion beam  130  increases during a scan. A scan velocity can increase as the area of the wafer  180  exposed to the beam  130  increases. A scan velocity can decrease as the area of the wafer  180  exposed to the beam  130  decreases. 
     In some embodiments, a scan acceleration can vary during a scan. A scan acceleration profile can be asymmetric. A scan acceleration can be identical between at least 2 scans. A scan acceleration curve is a plot of the wafer acceleration vs. the position of the wafer  180  along the scan path. A scan acceleration curve can be identical for more than 2 scans. A scan acceleration curve can be identical for all scans. A scan acceleration curve can be different between at least 2 scans. A scan acceleration curve can be different for more than 2 scans. A scan acceleration curve can be different for all scans. A scan acceleration can be constant during at least a portion of a scan. A scan velocity can be selected to maintain a constant dose of ions across at least one region of the wafer  180  during a scan. A scan velocity can be selected to maintain a constant dose of ions across all exposed regions of the wafer  180  during a scan. 
     Increasing the scan velocity when the wafer center is on the near side of the scan  302 , which are the points above the mid-plane  310  of the ion source  105  and grid system  150 , as shown for example in  FIG.  14   , reduces the etching on the inboard side  191  of the devices. In the schematic shown in  FIGS.  8 ,  13 ,  14  and  15   , the negative X positions are on the near side  302  of the scan. When the wafer center is on the near side  302 , increasing the scan speed reduces etching on the inboard side  191  of the device. Overall excellent uniformity of etching across the full wafer  180  is preserved by lowering the scan velocity on the positive X side of the scan. The relationship of such a velocity profile with respect to a symmetric velocity profile  303  required for good film uniformity across the wafer  180  is shown in  FIG.  13     
     In some embodiments, the shape of the velocity versus position can be a stepped velocity configuration or a smoothly varied configuration, represented by  304  in  FIG.  15   . An asymmetrical velocity profile causes the wafer  180  to spend more time on the positive x-side (e.g., further away from the ion source  105 ) than on the negative x-side, assuring more etching on the outboard side  192  of devices compared to the inboard side  191  of the devices. This process of asymmetric velocity of the scan enables inboard and outboard asymmetry control even when the etching system is configured with an ion source  105  having lateral dimensions smaller than the sum of wafer diameter and twice the beamlet divergence projection on the wafer scan plane. 
     The inboard side  191  of the device can be preferentially etched by slowing down the scan speed on the near side to correct for asymmetry arising in systems with sources that have a beam of less density at the center of the source compared to the density away from the center of the source. 
     Exemplary ion beam etch process parameters are as follows.
         Plasma source power approximately in the range of 100 W-5 kW.   Process chamber pressures in the range of 1E-3 Torr to 1E-5 Torr.   Gas compositions can contain an inert gas (e.g., Ar, Kr, Xe, He, etc., or mixtures of these).   Gas compositions can contain reactive gases (e.g., halogen containing gases, C x H y F z , Cl 2 , oxygen containing gases, O 2 , nitrogen containing gases, N 2 , NF 3 , carbon containing gases, CH 4 , CO, CO 2 , sulfur containing gases, SF 6 , hydrogen containing gases, H 2 , H 2 O, or mixtures of these).   Gas compositions can contain a mixture of inert and reactive gases.   Wafer temperature can range from approximately −40 C to 400 C.   Wafer scan speeds can range from approximately 0.01 mm/sec to 1 cm/sec. In one embodiment, the wafer scan speeds range from 1 mm/sec to 100 mm/sec.   Wafer rotation speeds range from approximately 0.5 RPM to 1000 RPM.   Ion beam voltages are typically less than about 500 eV.   Wafer tilt angles range from approximately 1 degree (e.g., 1 degree off perpendicular to the ion beam  105 ) to about 85 degrees (e.g., a glancing angle to the ion beam  105 ).       

     Any of the steps and procedures described above, while referred to herein as being included in the etching process, may also be applied to a deposition process. 
     Although a variety of examples and other information was used to explain aspects within the scope of the appended claims, no limitation of the claims should be implied based on particular features or arrangements in such examples, as one of ordinary skill would be able to use these examples to derive a wide variety of implementations. Further and although some subject matter may have been described in language specific to examples of structural features and/or method steps, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to these described features or acts. For example, such functionality can be distributed differently or performed in components other than those identified herein. Rather, the described features and steps are disclosed as examples of components of systems and methods within the scope of the appended claims. Moreover, claim language reciting “at least one of” a set indicates that one member of the set or multiple members of the set satisfy the claim.