Patent Publication Number: US-11037508-B1

Title: Pixel driving circuit, display panel and methods for driving the same

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application claims priority to the Chinese Patent Application No. 201911189265.X filed on Nov. 28, 2019, which is incorporated herein by reference in its entirety. 
     TECHNICAL FIELD 
     The present disclosure relates to the field of display technology, and more particularly, to a pixel driving circuit, a display panel, and methods for driving the same. 
     BACKGROUND 
     Organic Light-emitting Diodes (OLEDs) have advantages such as self-emission, wide viewing angles, high contrast, low power consumption, and fast response speeds etc., and therefore have been widely used and developed. When an OLED display apparatus is used, it needs to compensate for pixels during use to improve their display performance. However, since a compensation circuit has a complicated structure, it needs to occupy a large layout space, thereby limiting the improvement of a resolution of the pixels of the OLED display apparatus. 
     SUMMARY 
     The present disclosure provides a pixel driving circuit, a display panel, and methods for driving the same. 
     According to an aspect of the present disclosure, there is provided a pixel driving circuit, comprising: 
     at least two driving sub-circuits, each configured to generate driving current based on a compensated data signal; 
     at least two light-emitting control sub-circuits coupled to the at least two driving sub-circuits respectively, each of the at least two light-emitting control sub-circuits is configured to output driving current generated by one of the at least two driving sub-circuits coupled thereto; 
     a writing control sub-circuit electrically coupled to the at least two driving sub-circuits and a data writing sub-circuit; and 
     the data writing sub-circuit configured to compensate for a data signal and write the compensated data signal into the respective at least two driving sub-circuits sequentially under control of the writing control sub-circuit. 
     In some embodiments, the data writing sub-circuit comprises: 
     a first transistor having a gate electrically coupled to receive a first reset signal, a first electrode electrically coupled to receive a first initialization signal, and a second electrode electrically coupled to a gate of a second transistor and a first electrode of the second transistor; 
     the second transistor having a second electrode electrically coupled to a first electrode of a third transistor; and 
     the third transistor having a gate electrically coupled to receive a scanning signal, and a second electrode electrically coupled to receive the data signal. 
     In some embodiments, the writing control sub-circuit comprises: 
     at least two switching sub-circuits electrically coupled to the at least two driving sub-circuits respectively, each switching sub-circuit is configured to receive a writing control signal and write the compensated data signal generated by the data writing sub-circuit into one of the at least two driving sub-circuit coupled thereto under control of the writing control signal. 
     In some embodiments, each of the at least two switching sub-circuits comprises: 
     a fourth transistor having a gate electrically coupled to receive the writing control signal, a first electrode electrically coupled to the data writing sub-circuit to receive the compensated data signal, and a second electrode electrically coupled to one of the at least two driving sub-circuits. 
     In some embodiments, each of the at least two driving sub-circuits comprises: 
     a fifth transistor having a gate electrically coupled to one of the at least two switching sub-circuits, a first electrode electrically coupled to one of the at least two light-emitting control sub-circuits, and a second electrode electrically coupled to receive a first voltage; and 
     a storage capacitor having a first terminal electrically coupled to the gate of the fifth transistor, and a second terminal electrically coupled to receive the first voltage. 
     In some embodiments, each of the at least two light-emitting control sub-circuits comprises: 
     a sixth transistor having a gate electrically coupled to receive a light-emitting control signal, a first electrode electrically coupled to output the driving current, and a second electrode electrically coupled to the first electrode of the fifth transistor. 
     In some embodiments, each of the light-emitting control sub-circuits further comprises: 
     a seventh transistor having a gate electrically coupled to receive a second reset signal, a first electrode electrically coupled to receive a second initialization signal, and a second electrode electrically coupled to the first electrode of the sixth transistor. 
     In some embodiments, a difference between a threshold voltage of the second transistor and a threshold voltage of a fifth transistor in each driving sub-circuit which is used as a driving transistor is within a preset first threshold range. 
     In some embodiments, a difference between a temperature drift amount of the threshold voltage of the second transistor and a temperature drift amount of the threshold voltage of the fifth transistor in each driving sub-circuit is within a preset second threshold range. 
     In some embodiments, an absolute value of the difference between the threshold voltage of the second transistor and the threshold voltage of the fifth transistor is less than or equal to 0.01V. 
     In some embodiments, an absolute value of the difference between the temperature drift amount of the threshold voltage of the second transistor and the temperature drift amount of the threshold voltage of the fifth transistor is equal to or less than 0.01V. 
     In some embodiments, the at least two driving sub-circuits comprise a first driving sub-circuit and a second driving sub-circuit, wherein the first driving sub-circuit is configured to generate first driving current based on the compensated data signal, and the second driving sub-circuit is configured to generate second driving current based on the compensated data signal; and 
     the at least two light-emitting control sub-circuits comprise a first light-emitting control sub-circuit and a second light-emitting control sub-circuit, wherein the first light-emitting control sub-circuit is coupled to the first driving sub-circuit and is configured to output the first driving current generated by the first driving sub-circuit under control of a first light-emitting control signal, and the second light-emitting control sub-circuit is coupled to the second driving sub-circuit, and is configured to output the second driving current generated by the second driving sub-circuit under control of a second light-emitting control signal. 
     In some embodiments, the writing control sub-circuit comprises: 
     a first switching sub-circuit electrically coupled between the first driving sub-circuit and the data writing sub-circuit, and configured to receive a first writing control signal, and provide the compensated data signal generated by the data writing sub-circuit to the first driving sub-circuit under control of the first writing control signal; and 
     a second switching sub-circuit electrically coupled between the second driving sub-circuit and the data writing sub-circuit, and configured to receive a second writing control signal, and provide the compensated data signal generated by the data writing sub-circuit to the second driving sub-circuit under control of the second writing control signal. 
     In some embodiments, the data writing sub-circuit is configured to compensate for a first data signal and write the compensated first data signal into the first driving sub-circuit, and compensate for a second data signal and write the compensated second data signal into the second driving sub-circuit, under control of the writing control sub-circuit. 
     According to another aspect of the present disclosure, there is provided a display panel comprising a plurality of pixel units arranged in an array, each pixel unit comprising: 
     the pixel driving circuit described above; and 
     at least two light-emitting elements electrically coupled in one-to-one correspondence with the at least two driving sub-circuits of the pixel driving circuit. 
     In some embodiments, the array is an M×N array, wherein M and N are both integers greater than 1; 
     pixel driving circuits of an i th  row of pixel units are coupled to receive an i th  scanning signal, wherein i is an integer, and 1≤i≤M; and 
     pixel driving circuits of a j th  column of pixel units are coupled to receive a j th  data signal, wherein j is an integer, and 1≤j≤N. 
     According to yet another aspect of the present disclosure, there is provided a method for driving the pixel driving circuit described above, comprising: 
     during a first period, compensating for, by the data writing sub-circuit, a k th  data signal and writing the compensated k th  data signal into a k th  driving sub-circuit of the pixel driving circuit under control of the writing control sub-circuit; 
     during a second period, outputting, by a k th  light-emitting control sub-circuit, k th  driving current generated by the k th  driving sub-circuit; 
     during a third period, compensating for, by the data writing sub-circuit, a (k+1) th  data signal and writing the compensated (k+1) th  data signal into a (k+1) th  driving sub-circuit of the pixel driving circuit under control of the writing control sub-circuit; and 
     during a fourth period, outputting, by a (k+1) th  light-emitting control sub-circuit, (k+1) th  driving current generated by the (k+1) th  driving sub-circuit, 
     wherein k is an integer, and 1≤k≤K−1, where K represents a number of driving sub-circuits of the pixel driving circuit, and is an integer greater than 1. 
     According to still another aspect of the present disclosure, there is provided a method for driving the display panel described above, comprising: for each pixel unit, 
     during a first period, writing, by a data writing sub-circuit of a pixel driving circuit of the pixel unit, a compensated data signal for a k th  light-emitting element of the pixel unit into a k th  driving sub-circuit of the pixel driving circuit; 
     during a second period, causing the k th  light-emitting element to emit light using the compensated data signal; 
     during a third period, writing, by the data writing sub-circuit of the pixel driving circuit, a compensated data signal for a (k+1) th  light-emitting element of the pixel unit into a (k+1) th  driving sub-circuit of the pixel driving circuit; and 
     during a fourth period, causing the (k+1) th  light-emitting element to emit light using the compensated data signal, 
     wherein k is an integer and 1≤k≤K−1, where K represents a number of driving sub-circuits of the pixel driving circuit in the pixel unit, and is an integer greater than 1. 
    
    
     
       BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS 
       The above and other purposes, features, and advantages of the embodiments of the present disclosure will be more obvious by describing the embodiments of the present disclosure with reference to the accompanying drawings. It should be illustrated that throughout the accompanying drawings, the same elements are represented by the same or similar reference signs. In the accompanying drawings: 
         FIG. 1  schematically illustrates a block diagram of a pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 2  schematically illustrates an exemplary circuit structure of a pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 3  schematically illustrates another exemplary circuit structure of a pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 4  schematically illustrates still another exemplary circuit structure of a pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 5  schematically illustrates a block diagram of a display panel according to an embodiment of the present disclosure; 
         FIG. 6  schematically illustrates a block diagram of a display apparatus according to an embodiment of the present disclosure; 
         FIG. 7  schematically illustrates a flowchart of a driving method according to an embodiment of the present disclosure; and 
         FIGS. 8A and 8B  schematically illustrate timing diagrams of a driving method according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the embodiments described are a part of the embodiments of the present disclosure instead of all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without contributing any creative work are within the protection scope of the present disclosure. In the following description, some specific embodiments are for illustrative purposes only and are not to be construed as limiting the present disclosure, but merely examples of the embodiments of the present disclosure. The conventional structure or construction will be omitted when it may cause confusion with the understanding of the present disclosure. It should be illustrated that shapes and dimensions of components in the figures do not reflect true sizes and proportions, but only illustrate contents of the embodiments of the present disclosure. 
     Unless otherwise defined, technical terms or scientific terms used in the embodiments of the present disclosure should be of ordinary meanings to those skilled in the art. “First”, “second” and similar words used in the embodiments of the present disclosure do not represent any order, quantity or importance, but are merely used to distinguish between different constituent parts. 
     Particularly, in the description of the embodiments of the present discourse, unless a source and a drain of a transistor are specified, a “first electrode” refers to a source or a drain of a switch transistor, and a “second electrode” refers to the drain or the source of the switch transistor, which will not be distinguished from each other. 
     Furthermore, in the description of the embodiments of the present disclosure, the term “connected to” or “connected with” may mean that two components are directly connected, or that two components are connected via one or more other components. In addition, the two components may be connected or coupled by wire or wirelessly. 
     The embodiments of the present disclosure provide a pixel driving circuit capable of compensating for a threshold voltage of a light-emitting element such as an OLED. The pixel driving circuit is configured to drive at least two light-emitting elements. A block diagram of the pixel driving circuit is shown in  FIG. 1 , and a structure of the pixel driving circuit according to the embodiment of the present disclosure will be described below with reference to  FIG. 1 . 
     As shown in  FIG. 1 , the pixel driving circuit  100  comprises at least two driving sub-circuits  101   1 , . . . ,  101   K , wherein K is a natural number greater than or equal to 2. Each of the driving sub-circuits is electrically coupled to a light-emitting element. Each of the at least two driving sub-circuits  101   1 , . . . ,  101   K  is configured to generate current (driving current) which causes respective one of the at least two light-emitting elements OLED 1 , . . . , OLED K  to emit light. 
     In  FIG. 1 , in order to facilitate description of an electrical connection between the pixel driving circuit  100  and the light-emitting elements, the light-emitting elements OLED 1 , . . . , OLED K  are shown in dotted lines. 
     In addition, in  FIG. 1 , the light-emitting elements are shown in a form of OLEDs, and it may be understood by those skilled in the art that the light-emitting elements may be other light-emitting elements for example current driving-type light-emitting elements, and the present disclosure is not limited thereto. 
     As shown in  FIG. 1 , the pixel driving circuit  100  may further comprise at least two light-emitting control sub-circuits  102   1 , . . . ,  102   K , wherein K is a natural number greater than or equal to 2. Each of the light-emitting control sub-circuits is electrically coupled between a driving sub-circuit and a light-emitting element. Each of the at least two light-emitting control sub-circuits  102   1 , . . . ,  102   K  is configured to provide current generated by the respective of the driving sub-circuits  101   1 , . . . ,  101   K  to the respective of the light-emitting elements OLED 1 , . . . , OLED K . 
     As shown in  FIG. 1 , the pixel driving circuit  100  may further comprise a writing control sub-circuit  103  and a data writing sub-circuit  104 . The writing control sub-circuit  103  is electrically coupled to the driving sub-circuits  101   1 , . . . ,  101   K  and the data writing sub-circuit  104 , and is used to control the data writing sub-circuit  104  to write a compensated data signal (for example, a signal which is obtained by adding a compensation signal to a data signal) into the driving sub-circuits  101   1 , . . . ,  101   K  sequentially. 
     The data writing sub-circuit  104  may write the compensated data signals for the at least two light-emitting elements OLED 1 , . . . , OLED K  respectively into the at least two driving sub-circuits  101   1 , . . . ,  101   K  sequentially under control of the writing control sub-circuit  103 . 
     In the pixel driving circuit according to the embodiment of the present disclosure, a threshold voltage of a pixel (for example, a driving transistor of a light-emitting element (for example, an OLED) of the pixel) may be compensated. With the development of OLED display technology, the demands for driving circuits are also increasing. In a manufacturing process in the factory, due to problems such as devices, processes etc., driving circuits of pixels are inevitably uneven. For example, threshold voltages of driving transistors of different pixels have distributivity. As another example, a temperature drift due to variation of a threshold voltage of a driving transistor with temperature also varies. These problems may affect the display effect. The display effect of the OLED display apparatus may be improved by compensating for the threshold voltages of the driving transistors. 
     According to the embodiment shown in  FIG. 1 , in an actual operation, the data signal is compensated before being written into each of the writing driving sub-circuits  101   1 , . . . ,  101   K , which may compensate for threshold voltages of the light-emitting elements OLED 1 , . . . , OLED K . 
     In the pixel driving circuit according to the embodiment of the present disclosure, one data writing sub-circuit (for example, the data writing sub-circuit  104 ) may be used to compensate for the threshold voltages of the at least two light-emitting elements. The data writing sub-circuit is provided and is shared between the at least two light-emitting elements, so that the compensated data signals for the light-emitting elements are written into the driving sub-circuits sequentially, which significantly reduces sizes of the pixel driving circuits. 
     With the gradual miniaturization of the application of OLED display technology and users&#39; demands for a resolution of an OLED display screen, how to increase a screen ratio, reduce peripheral wiring, and increase a resolution of pixels has become the current research and development direction. As shown in  FIG. 1 , in the embodiment of the present disclosure, the data writing sub-circuit  104  may be designed according to characteristics of driving transistors in the driving sub-circuits  101   1 , . . . ,  101   K  which drive the at least two light-emitting elements OLED 1 , . . . , OLED K , so that the data writing sub-circuit  104  may have a capability of data writing and compensation for the at least two light-emitting elements. Since at least two light-emitting elements may share one data writing and compensation circuit structure, wiring may be reduced, thereby reducing sizes of respective pixel units which form a display panel. Therefore, the pixel driving circuit according to the embodiment of the present disclosure may increase a screen area ratio and significantly reduce a size of the pixel driving circuit. 
     The embodiments of the present disclosure will be further described below in combination with specific examples. 
       FIG. 2  schematically illustrates an exemplary circuit structure of a pixel driving circuit according to an embodiment of the present disclosure. In this example, description is made using an arrangement configured to drive two light-emitting elements OLED 1  and OLED 2 , but the present disclosure is not limited thereto. In  FIG. 2 , the light-emitting elements OLED 1  and OLED 2  are shown in dotted lines. 
     As shown in  FIG. 2 , the pixel driving circuit  200  comprises a first driving sub-circuit  201   1  and a second driving sub-circuit  201   2 , a first light-emitting control sub-circuit  202   1  and a second light-emitting control sub-circuit  202   2 , a writing control sub-circuit  203 , and a data writing sub-circuit  204 . The first driving sub-circuit  201   1  is electrically coupled to the first light-emitting control sub-circuit  202   1  and a part of the writing control sub-circuit  203 , and is configured to provide a compensated data signal (for example, a first compensation signal and a first data signal) to the light-emitting element OLED 1 . The second driving sub-circuit  201   2  is electrically coupled to the second light-emitting control sub-circuit  202   2  and a part of the writing control sub-circuit  203 , and is configured to provide a compensated data signal (for example, a second compensation signal and a second data signal) to the light-emitting element OLED 2 . 
     The light-emitting elements OLED 1  and OLED 2  may be light-emitting elements in adjacent columns. For example, the light-emitting element OLED 1  is in an odd-numbered ((2n−1) th ) column of a matrix formed by the light-emitting elements, and the light-emitting element OLED 2  is in an even-numbered ((2n) th ) column of the matrix formed by the light-emitting elements, wherein k is a natural number. The above two structures electrically coupled to the light-emitting elements OLED 1  and OLED 2  respectively are arranged substantially symmetrically with respect to the data writing sub-circuit  204 , but the present disclosure is not limited thereto. 
     The data writing sub-circuit  204  is shared by the above two structures, and therefore the pixel driving circuit  200  according to the embodiment of the present disclosure may have a simplified driving circuit structure and save wiring of data lines. When 2N light-emitting elements are included in each row of an array (for example, a matrix) formed by the light-emitting elements on a display panel, only N data writing sub-circuits  204  and N data lines need to be arranged. 
     As shown in  FIG. 2 , the data writing sub-circuit  204  comprises a first transistor T 1 , a second transistor T 2 , and a third transistor T 3 . According to an example, the first transistor T 1  has a gate electrically coupled to receive a first reset signal REST 1 , a first electrode electrically coupled to receive a first initialization signal V init , and a second electrode electrically coupled to a gate and a first electrode (a drain) of the second transistor T 2 . The second transistor T 2  has a second electrode (a source) electrically coupled to a first electrode of the third transistor T 3 . The third transistor T 3  has a gate electrically coupled to receive a scanning signal V scan , and a second electrode electrically coupled to receive a data signal V data . 
     The first transistor T 1  may be turned on under control of the first reset signal REST 1  applied to the gate thereof, thereby applying the first initialization signal V init  to the gate and the first electrode (the drain) of the second transistor T 2 , wherein the first initialization signal V init  may enable the second transistor T 2  to be turned on. The third transistor T 3  may be turned on under control of the scanning signal V scan  applied to the gate thereof. In a case where the second transistor T 2  and the third transistor T 3  are both turned on, the compensated data signals may be written into the first driving sub-circuit  201   1  and the second driving sub-circuit  201   2  respectively under control of the writing control sub-circuit  203 . 
     In  FIG. 2 , the first transistor T 1 , the second transistor T 2 , and the third transistor T 3  are all shown as P-type transistors, but the present disclosure is not limited thereto. In other examples, the first transistor T 1 , the second transistor T 2 , and the third transistor T 3  may also be N-type transistors. Functions of the data writing sub-circuit  204  described above may be achieved by appropriately adjusting a connection relationship between the transistors and voltages of the first reset signal REST 1 , the first initialization signal V init , the data signal V data , and the scanning signal V scan . 
     As shown in  FIG. 2 , the writing control sub-circuit  203  comprises at least two switching sub-circuits, for example, a first switching sub-circuit comprising a fourth transistor T 4 _ 1  and a second switching sub-circuit comprising a fourth transistor T 4 _ 2 . In  FIG. 2 , the first switching sub-circuit is electrically coupled to the first driving sub-circuit  201   1  and the second switching sub-circuit is electrically coupled to the second driving sub-circuit  201   2 . The first switching sub-circuit may receive a writing control signal SW_ 1  (a first writing control signal) and provide the compensated data signal generated by the data writing sub-circuit  204  to the first driving sub-circuit  201   1  under control of the writing control signal SW_ 1 . The second switching sub-circuit may receive a writing control signal SW_ 2  (a second writing control signal) and provide the compensated data signal generated by the data writing sub-circuit  204  to the second driving sub-circuit  201   2  under control of the writing control signal SW_ 2 . 
     In  FIG. 2 , the fourth transistor T 4 _ 1  has a gate electrically coupled to receive the writing control signal SW_ 1  (the first writing control signal), a first electrode electrically coupled to the gate and the first electrode of the second transistor T 2 , and a second electrode electrically coupled to the first driving sub-circuit  201   1 . The fourth transistor T 4 _ 2  has a gate electrically coupled to receive the writing control signal SW_ 2  (the second writing control signal), a first electrode electrically coupled to the gate and the first electrode of the second transistor T 2 , and a second electrode electrically coupled to the second driving sub-circuit  201   2 . 
     As shown in  FIG. 2 , the fourth transistor T 4 _ 1  may be turned on under control of the writing control signal SW_ 1 , and the fourth transistor T 4 _ 2  may be turned on under control of the writing control signal SW_ 2 , so as to turn on respective electrical connection paths from the data writing sub-circuit  204  to the first driving sub-circuit  201   1  and the second driving sub-circuit  201   2  to write the compensated data signals into the first driving sub-circuit  201   1  and the second driving sub-circuit  201   2  respectively. 
     Likewise, the fourth transistors T 4 _ 1  and T 4 _ 2  are shown as P-type transistors, but the present disclosure is not limited thereto. In other examples, the fourth transistors T 4 _ 1  and T 4 _ 2  may also be N-type transistors. In this case, voltages of the writing control signals SW_ 1  and SW_ 2  may be changed accordingly to implement the functions of the writing control sub-circuit  203 . 
     As shown in  FIG. 2 , the first driving sub-circuit  201   1  may comprise a driving transistor (a fifth transistor) DTFT_ 1  and a storage capacitor C_ 1 , and the second driving sub-circuit  201   2  may comprise a driving transistor (a fifth transistor) DTFT_ 2  and a storage capacitor C_ 2 . The two driving sub-circuits may have the same structure. The driving transistor DTFT_ 1  and the driving transistor DTFT_ 2  may have substantially the same threshold voltage and substantially the same temperature drift amount of the threshold voltage. In some embodiments, the driving transistor DTFT_ 1  and the driving transistor DTFT_ 2  may be the same. 
     By taking the first driving sub-circuit  201   1  as an example, the driving transistor DTFT_ 1  has a gate electrically coupled to the second electrode of the fourth transistor T 4 _ 1 , a first electrode (drain) electrically coupled to the first light-emitting control sub-circuit  202   1 , and a second electrode (source) electrically coupled to receive a first voltage VDD. The storage capacitor C_ 1  has a first terminal electrically coupled to the second electrode of the fourth transistor T 4 _ 1 , and a second terminal electrically coupled to receive the first voltage VDD. 
     As shown in  FIG. 2 , the first driving sub-circuit  201   1  may store the compensated data signal (obtained by, for example, adding the first compensation signal (voltage) to the first data signal (voltage)) which is written through the writing control sub-circuit  203  and the data writing sub-circuit  204  in the storage capacitor C_ 1 . The driving transistor DTFT_ 1  may generate current (driving current) which causes the light-emitting element OLED 1  to emit light under control of a voltage (the compensated data signal) applied to the gate thereof, as shown in the following formula:
 
 I   1   =K   1 ·( V   GS1   −V   th1 ) 2  
 
wherein K 1  represents a parameter related to a process and design of the driving transistor DTFT_ 1 , and may be regarded as a constant for a specific transistor; V GS1  represents a voltage applied between the gate and the source of the driving transistor DTFT_ 1 , and V GS1 =V G1 −V DD  if V G1  represents the voltage applied to the gate of the driving transistor DTFT_ 1  and V DD  represents a voltage value of the first voltage VDD; V th1  represents a threshold voltage of the driving transistor DTFT_ 1 , and is a negative value for a P-type driving transistor DTFT_ 1 , and I 1  is resulting current.
 
     The second driving sub-circuit  201   2  may have the same structure as that of the first driving sub-circuit  201   1 . The driving transistor DTFT_ 2  may generate current I 2 =K 2 ·(V GS2 −V th2 ) 2  which causes the light-emitting element OLED 2  to emit light under control of a voltage applied to the gate thereof, wherein K 2  represents a parameter related to a process and design of the driving transistor DTFT_ 2 , and may be regarded as a constant for a specific transistor; V GS2  represents a voltage applied between the gate and the source of the driving transistor DTFT_ 2 , and V GS2 =V G2 −V DD  if V G2  represents the voltage applied to the gate of the driving transistor DTFT_ 2 ; V th2  represents a threshold voltage of the driving transistor DTFT_ 2 , and is a negative value for a P-type driving transistor DTFT_ 2 . 
     Likewise, the driving transistors DTFT_ 1  and DTFT_ 2  are shown as P-type transistors, but the present disclosure is not limited thereto. In other examples, the driving transistors DTFT_ 1  and DTFT_ 2  may also be N-type transistors. 
     As shown in  FIG. 2 , the first light-emitting control sub-circuit  202   1  comprises a sixth transistor T 6 _ 1 , the second light-emitting control sub-circuit  202   2  comprises a sixth transistor T 6 _ 2 , and the two light-emitting control sub-circuits have the same structure. 
     By taking the first light-emitting control sub-circuit  202   1  as an example, the sixth transistor T 6 _ 1  has a gate electrically coupled to receive a light-emitting control signal EM_ 1  (a first light-emitting control signal), a first electrode electrically coupled to the first terminal of the light-emitting element OLED 1 , and a second electrode electrically coupled to the drain of the driving transistor DTFT_ 1 . The sixth transistor T 6 _ 1  may be turned on under control of the light-emitting control signal EM_ 1  applied to the gate thereof, so as to provide the current generated by the first driving sub-circuit  201   1  to the light-emitting element OLED 1 . 
     A structure and a function of the second light-emitting control sub-circuit  202   2  are the same as those of the first light-emitting control sub-circuit  202   1 , and will not be described in detail here. 
     Likewise, the sixth transistors T 6 _ 1  and T 6 _ 2  are shown as P-type transistors, but the present disclosure is not limited thereto. In other examples, the sixth transistors T 6 _ 1  and T 6 _ 2  may also be N-type transistors. In a case of N-type transistors, functions of the first light-emitting control sub-circuit  202   1  and the second light-emitting control sub-circuit  202   2  are realized by changing voltages of the light-emitting control signal EM_ 1  (the first light-emitting control signal) and the light-emitting control signal EM_ 2  (the second light-emitting control signal) accordingly. 
     Different types of transistors generally have different threshold voltages. In addition, since a threshold voltage of a transistor may change with temperature, that is, a drift of the threshold voltage occurs, even for the same transistor, when an application environment changes, non-uniform display may occur due to the drift of the threshold voltage. 
     In the embodiment of the present disclosure, the threshold voltages of the driving transistors DTFT_ 1  and DTFT_ 2  are compensated by providing the common second transistor T 2  in the data writing sub-circuit  204 , wherein the second transistor T 2  has substantially the same electrical characteristics as those of the driving transistors DTFT_ 1  and DTFT_ 2 . 
     According to an embodiment, differences between a threshold voltage of the second transistor T 2  and the threshold voltages of the driving transistors DTFT_ 1  and DTFT_ 2  may be within a preset first threshold range, so that the threshold voltage of the second transistor T 2  may be considered as substantially equal to those of the driving transistors DTFT_ 1  and DTFT_ 2 . In addition, differences between a temperature drift amount of the threshold voltage of the second transistor T 2  and temperature drift amounts of the threshold voltages of the driving transistors DTFT_ 1  and DTFT_ 2  may also be within a preset second threshold range, so that the temperature drift amount of the threshold voltage of the second transistor T 2  may be considered as substantially equal to those of the driving transistors DTFT_ 1  and DTFT_ 2 . 
     For example, the threshold voltages of the second transistor T 2  and the driving transistors DTFT_ 1  and DTFT_ 2  are represented by V′ th , V th1  and V th2  respectively. The compensation signals (obtained by adding the threshold voltage V′ th  to voltages of the data signal) comprising the threshold voltage V′th of T 2  are written into the gate of the driving transistor DTFT_ 1  in the first driving sub-circuit  201   1  and the gate of the driving transistor DTFT_ 2  in the second driving sub-circuit  201   2  respectively through the writing control sub-circuit  203  and the data writing sub-circuit  204 . In this way, in a case where the threshold voltage of the second transistor T 2  is substantially equal to the threshold voltages of the driving transistors DTFT_ 1  and DTFT_ 2 , it may be considered that V′ th =V th1 =V th2 , and the influence of the threshold voltages V th1  and V th2  of the driving transistors DTFT_ 1  and DTFT_ 2  are eliminated from the formula I 1 =K 1 ·(V GS1 −V th1 ) 2  of current which is generated by the driving transistor DTFT_ 1  and the formula I 2 =K 2 ·(V GS2 −V th2 ) 2  of current which is generated by the driving transistor DTFT_ 2 . 
     According to an embodiment, an absolute value of the difference between the threshold voltage of the second transistor T 2  and the threshold voltages of the driving transistors DTFT_ 1  and DTFT_ 2  may be less than or equal to 0.01V. According to an embodiment, an absolute value of the difference between the temperature drift amount of the threshold voltage of the second transistor T 2  and the temperature drift amounts of the threshold voltages of the driving transistors DTFT_ 1  and DTFT_ 2  may be less than or equal to 0.01V. 
     According to an embodiment, transistors having substantially the same electrical characteristics may be manufactured using the following method. For example, in some embodiments, the second transistor T 2  may be arranged closer to the driving transistors DTFT_ 1  and DTFT_ 2 , for example, the driving transistors DTFT_ 1  and DTFT_ 2  are arranged in adjacent columns, and the second transistor T 2  is arranged between the driving transistor DTFT_ 1  and DTFT_ 2 . In some embodiments, the second transistor T 2  and the driving transistors DTFT_ 1  and DTFT_ 2  may be processed through processes such as environmental parameter testing and aging experiment debugging etc. In some embodiments, transistors having substantially the same electrical characteristics may be obtained by improving manufacturing processes of the second transistor T 2  and the driving transistors DTFT_ 1  and DTFT_ 2 . However, the present disclosure is not limited to the above embodiments, and any method which may enable the electrical characteristics of the second transistor T 2  to be substantially the same as those of the driving transistors DTFT_ 1  and DTFT_ 2  may be adopted. In addition, the second transistor T 2  and the driving transistors DTFT_ 1  and DTFT_ 2  according to the embodiment of the present disclosure have substantially the same electrical characteristics, but may have different sizes and shapes. 
     According to an embodiment of the present disclosure, the threshold voltages and the temperature shift amounts of the threshold voltages of the driving transistors DTFT_ 1  and DTFT_ 2  included in the first driving sub-circuit  201   1  and the second driving sub-circuit  201   2  may be compensated by the common data writing sub-circuit  204  comprising the second transistor T 2 , which reduces the size of the circuit while improving the display effect, and provides the possibility for improving the display resolution. 
       FIG. 3  schematically illustrates another exemplary circuit structure of a pixel driving circuit according to an embodiment of the present disclosure. 
     As shown in  FIG. 3 , the pixel driving circuit  300  comprises a first driving sub-circuit  301   1  and a second driving sub-circuit  301   2 , a first light-emitting control sub-circuit  302   1  and a second light-emitting control sub-circuit  302   2 , a writing control sub-circuit  303 , and a data writing sub-circuit  304 . In addition, the first driving sub-circuit  301   1  and the second driving sub-circuit  301   2 , the writing control sub-circuit  303 , and the data writing sub-circuit  304  may have the same structures as those of the first driving sub-circuit  201   1  and the second driving sub-circuit  201   2 , the writing control sub-circuit  203  and the data writing sub-circuit  204  of the pixel driving circuit  200 , and will not be described in detail here. 
     As shown in  FIG. 3 , the first light-emitting control sub-circuit  302   1  of the pixel driving circuit  300  comprises a sixth transistor T 6 _ 1  and a seventh transistor T 7 _ 1 , and the second light-emitting control sub-circuit  302   2  of the pixel driving circuit  300  comprises a sixth transistor T 6 _ 2  and a seventh transistor T 7 _ 2 . The sixth transistors T 6 _ 1  and T 6 _ 2  may be implemented with reference to the sixth transistor included in the first light-emitting control sub-circuit  202   1  of the pixel driving circuit  200  shown in  FIG. 2 . The seventh transistor T 7 _ 1  has a gate electrically coupled to receive a second reset signal REST 2 _ 1 , a first electrode electrically coupled to receive a second initialization signal V′ init , and a second electrode electrically coupled to the first terminal of the light-emitting element OLED 1 . 
     The seventh transistor T 7 _ 1  may be turned on under control of the second reset signal REST 2 _ 1  applied to the gate thereof to apply the second initialization signal V′ init  to the first terminal of the light-emitting element OLED 1  to set the light-emitting element OLED 1  to be in a predetermined state, which may effectively reduce afterimages during display. 
     The seventh transistor T 7 _ 2  may be coupled in a manner similar to that of the seventh transistor T 7 _ 1 . In  FIG. 3 , the gate of the seventh transistor T 7 _ 2  is shown as being electrically coupled to receive the second reset signal REST 2 _ 2 . The second reset signals REST 2 _ 1  and REST 2 _ 2  represent second reset signals applied to the first light-emitting control sub-circuit  302   1  and the second light-emitting control sub-circuit  302   2  respectively, and may have the same or different timings. 
     According to the embodiment of the present disclosure, the light-emitting elements OLED 1  and OLED 2  may be turned off faster by resetting the light-emitting elements OLED 1  and OLED 2 , which reduces the afterimages during the display while compensating for the threshold voltages of the driving transistors DTFT_ 1  and DTFT_ 2  and the temperature drift amounts of the threshold voltages, thereby further improving the display effect. 
       FIG. 4  schematically illustrates still another exemplary circuit structure of a pixel driving circuit according to an embodiment of the present disclosure. Compared with the pixel driving circuit  300  shown in  FIG. 3 , eighth transistors T 8 _ 1  and T 8 _ 2  are further added in the first light-emitting control sub-circuit  302   1  and the second light-emitting control sub-circuit  302   2  respectively. 
     As shown in  FIG. 4 , the eighth transistor T 8 _ 1  has a gate electrically coupled to receive another light-emitting control signal EM 2 _ 1 , a first electrode electrically coupled to the source of the driving transistor DTFT_ 1 , and a second electrode electrically coupled to receive the first voltage VDD. The eighth transistor T 8 _ 2  has a gate electrically coupled to receive another light-emitting control signal EM 2 _ 2 , a first electrode electrically coupled to the source of the driving transistor DTFT_ 2 , and a second electrode electrically coupled to receive the first voltage VDD. The eighth transistors T 8 _ 1  and T 8 _ 2  may be turned off during a non-light-emitting phase, so as to prevent the driving transistors DTFT_ 1  and DTFT_ 2  from providing driving current to the light-emitting elements during the non-light-emitting phase, which may further improve the display effect. 
       FIG. 5  schematically illustrates a block diagram of a display panel according to an embodiment of the present disclosure. 
     As shown in  FIG. 5 , the display panel  500  comprises a plurality of pixel units (as shown by dashed blocks, only one pixel unit is labeled in  FIG. 5  for simplicity) arranged in an array. Each of the pixel units comprises a pixel driving circuit  502  and at least two light-emitting elements  501  (two light-emitting elements are shown in  FIG. 5 ). The at least two light-emitting elements  501  are electrically coupled in one-to-one correspondence with at least two driving sub-circuits of the pixel driving circuit. The pixel driving circuits  502  may be implemented by the pixel driving circuits in any of the above embodiments. 
     In  FIG. 5 , the pixel units are arranged in an M×N array, wherein M and N are both integers greater than 1, and pixel driving circuits of an i th  row of pixel units are coupled to receive an i th  scanning signal V scan (i), wherein i is an integer, and 1≤i≤M, and pixel driving circuits of a j th  column of pixel units are coupled to receive a j th  data signal V data (j), wherein j is an integer and 1≤j≤N. 
     In a case where the pixel driving circuit  502  has any of the structures described above with reference to  FIGS. 2 to 4 , in the pixel driving circuits of the i th  row of pixel units, each of first light-emitting control sub-circuits  302   1  may be coupled to a first light-emitting control signal EM_ 1 ( i ) for the i th  row of pixel units, each of second light-emitting control sub-circuits  302   1  may be coupled to a second light-emitting control signal EM_ 2 ( i ) for the i th  row of pixel units, each of first switching sub-circuits (for example, the gate of the fourth transistor T 4 _ 1 ) may be coupled to receive a first writing control signal SW_ 1 ( i ) for the i th  row of pixel units, and each of second switching sub-circuits (for example, the gate of the fourth transistor T 4 _ 2 ) may be coupled to receive a second writing control signal SW_ 2 ( i ) for the i th  row of pixel units. 
     As shown in  FIG. 5 , the display panel  500  comprises a plurality of scanning lines SL 1 , SL 2 , SL 3 , . . . , SL M , a plurality of data lines DL 1 , DL 2 , . . . , DL N , a plurality of light-emitting elements  501 , and a plurality of pixel driving circuits  502 . 
     The plurality of light-emitting elements  501  are arranged in a matrix comprising rows and columns. The plurality of scanning lines SL 1 , SL 2 , SL 3 , . . . , SL M  are arranged in correspondence with respective rows of light-emitting elements. The plurality of data lines DL 1 , DL 2 , . . . , DL N  intersect with the plurality of scanning lines SL 1 , SL 2 , SL 3 , . . . , SL M , and a data line DL j  is arranged between a (2j−1) th  column of light-emitting elements  501  and a (2j) th  column of light-emitting elements  501 . The plurality of pixel driving circuits  502  according to the above embodiments are arranged at respective positions where the plurality of scanning lines intersect the plurality of data lines, and data writing sub-circuits of the pixel driving circuits  502  are electrically coupled to scanning lines and data lines corresponding to the intersection positions to receive scanning signals and data signals respectively. 
     In the display panel according to the embodiment of the present disclosure, one data line is shared between two adjacent columns of light-emitting elements, which may significantly reduce wiring of the data lines while compensating for the threshold voltages of the transistors, thereby reducing a scale of the circuit. 
       FIG. 6  schematically illustrates a block diagram of a display apparatus according to an embodiment of the present disclosure. As shown in  FIG. 6 , the display apparatus  600  according to the embodiment of the present disclosure comprises the display panel  601  according to the embodiment of the present disclosure. The display apparatus  600  according to the embodiment of the present disclosure may be any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. 
       FIG. 7  schematically illustrates a flowchart of a driving method according to an embodiment of the present disclosure, and  FIGS. 8A and 8B  schematically illustrate timing diagrams of the driving method according to an embodiment of the present disclosure. The driving method according to the embodiment of the present disclosure will be described below with reference to  FIGS. 7, 8A, and 8B  based on the pixel driving circuit  200  of the embodiment shown in  FIG. 2 . 
     As shown in  FIG. 7 , the driving method  700  comprises the following steps S 710  to S 740 . 
     In step S 710 , during a first period, the data writing sub-circuit of the pixel driving circuit compensates for a k th  data signal and writes the compensated k th  data signal (for example, a first compensation signal and a first data signal) into a k th  driving sub-circuit (for example, a first driving sub-circuit) of the pixel driving circuit under control of the writing control sub-circuit, wherein k is an integer, and 1≤k≤K−1, where K represents a number of driving sub-circuits of the pixel driving circuit, and K is an integer greater than 1. The compensated data signal provided to the k th  driving sub-circuit may be used to drive a k th  light-emitting element in a pixel unit where the pixel driving circuit is located. For example, for a pixel unit located in an i th  row and a j th  column, if the pixel unit comprises two light-emitting elements, a first one of the two light-emitting elements is located in an i th  row and a (2j−1) th  column in an array formed by light-emitting elements on a display panel, and a second one of the two light-emitting elements is located in the i th  row and a (2j) th  column in the array, and vice versa. 
     In step S 720 , during a second period, a k th  light-emitting control sub-circuit outputs k th  driving current generated by the k th  driving sub-circuit. For example, the k th  driving sub-circuit may generate driving current (the k th  driving current) for causing the k th  light-emitting element to emit light using the compensated k th  data signal (for example, the first compensation signal and the first data signal), and the k th  light-emitting control sub-circuit outputs the k th  driving current to the k th  light-emitting element. 
     In step S 730 , during a third period, the data writing sub-circuit of the pixel driving circuit compensates for a (k+1) th  data signal and writes the compensated (k+1) th  data signal (for example, a second compensation signal and a second data signal for a second light-emitting element of the pixel unit) into a (k+1)th driving sub-circuit (for example, a second driving sub-circuit) of the pixel driving circuit under control of the writing control sub-circuit. 
     In step S 740 , during a fourth period, a (k+1) th  light-emitting control sub-circuit outputs (k+1) th  driving current generated by the (k+1) th  driving sub-circuit. For example, the second driving sub-circuit generates driving current for causing the second light-emitting element to emit light using the second compensation signal and the second data signal, and the second light-emitting control sub-circuit outputs the second driving current to the second light-emitting element. 
     Although steps of the method have been described above in a specific order, the embodiments of the present disclosure are not limited thereto. For example, steps S 720  and S 740  may be performed at the same time after step S 730  is performed, that is, the compensated data signals may be written into the k th  driving sub-circuit and the (k+1) th  driving sub-circuit sequentially, and then the k th  driving signal and the (k+1) th  driving signal are output at the same time to light up the k th  light-emitting unit and the (k+1) th  light-emitting unit at the same time. 
     The above steps will be described in detail below with reference to the exemplary structure of  FIG. 2 . 
     As shown in  FIGS. 2 and 8A , the first period may comprise an initialization period t 1  and a data writing period t 2 . During the initialization period t 1 , the first reset signal REST 1  at a low level and the writing control signal SW_ 1  at a low level are provided. When the first reset signal REST 1  is at a low level, the first transistor T 1  is turned on, and the first initialization signal V init  is applied to the gate of the second transistor T 2  to ensure that the second transistor T 2  may be turned on. When the writing control signal SW_ 1  is at a low level, the fourth transistor T 4 _ 1  is turned on, so that an electrical connection path between the data writing sub-circuit  204  and the first driving sub-circuit  201   1  is turned on. 
     During the initialization period t 1 , the scanning signal V scan  is at a high level, and therefore the third transistor T 3  is turned off. The writing control signal SW_ 2  is at a high level, and therefore the fourth transistor T 4 _ 2  is turned off, and an electrical connection path between the data writing sub-circuit  204  and the second driving sub-circuit  201   2  is turned off. The light-emitting control signal EM_ 1  is at a high level, so that the sixth transistor T 6 _ 1  is turned off, and thereby the light-emitting element OLED 1  stops emitting light. The light-emitting control signal EM_ 2  is at a low level, that is, in a process of writing data into the light-emitting element OLED 1 , the light-emitting element OLED 2  may display normally. When data signals and compensation signals are not written, OLED 1  and OLED 2  are generally in a light-emitting state, that is, the light-emitting control signals EM_ 1  and EM_ 2  are at a low level. Therefore, before a data signal and a compensation signal are written, a light-emitting state of a light-emitting element into which the data is to be written may be disabled. As shown in  FIG. 8A , during a period of time before the initialization period t 1 , the light-emitting control signal EM_ 1  is set to a high level, so that the light-emitting element OLED 1  stops emitting light. 
     Next, during the data writing period t 2 , the writing control signal SW_ 1  is maintained at a low level, and therefore the fourth transistor T 4 _ 1  is maintained to be turned on. At the same time, the second transistor T 2  is maintained to be turned on under control of the first initialization signal V init . The scanning signal V scan  at a low level and a valid first data signal V data1  are provided. When the scanning signal V scan  is at a low level, the third transistor T 3  is turned on. In a case where both the second transistor T 2  and the third transistor T 3  are turned on, the first data signal V data1  charges the second terminal (that is, the gate of the driving transistor DTFT_ 1 ) of the storage capacitor C_ 1  through the third transistor T 3 , the second transistor T 2 , and the fourth transistor T 4 _ 1 . The charging process does not end until a gate voltage V G1  of the driving transistor DTFT_ 1  is equal to V data1 +V′ th , wherein V′ th  represents a threshold voltage of the second transistor T 2 . Thereby, both the first data signal V data1  and the first compensation signal V′ th  (for example, a compensated data signal having a voltage of V data1 +V′ th ) are written into the gate of the driving transistor DTFT_ 1 . 
     During the data writing period t 2 , the first reset signal REST 1  is at a high level, and therefore the first transistor T 1  is turned off. The light-emitting control signal EM_ 1  and the writing control signal SW_ 2  are maintained at a high level, the light-emitting control signal EM_ 2  is maintained at a low level, and therefore states of the sixth transistor T 6 _ 1 , the fourth transistor T 4 _ 2 , and the sixth transistor T 6 _ 2  are maintained to be unchanged. 
     Next, during a period t 3  (that is, a second period), the scanning signal V scan  is set to a high level to stop writing data, and the writing control signal SW_ 1  is set to a high level to turn off the electrical connection path between the data writing sub-circuit  204  and the first driving sub-circuit  201   1  and the light-emitting control signal EM_ 1  at a low level is provided to cause the light-emitting element OLED 1  to emit light using the written first data signal V data1  and the written first compensation signal V′ th . Current generated by the driving transistor DTFT_ 1  is 11=K 1 ·(V GS1 −V th1 ) 2 , wherein V GS1 =V G1 −V DD =V data1 +V′ th −V DD , and V th1  is the threshold voltage of DTFT_ 1 , and is a negative value. Since V th1  may be set to be equal to V′th, the current generated by the driving transistor DTFT_ 1  is I 1 =K 1 ·(V data1 −V DD ) 2 . That is, the resulting current has nothing to do with the threshold voltage of the driving transistor DTFT_ 1 , and has nothing to do with the temperature drift of the threshold voltage of DTFT_ 1 . Thereby, the electrical compensation is completed. 
     The third period may comprise an initialization period t 4  and a data writing period t 5 . During the third period, the light-emitting control signal EM_ 1  is at a low level, so that in a process of writing data into the light-emitting element OLED 2 , the light-emitting element OLED 1  may display normally. 
     During the initialization period t 4 , the first reset signal REST 1  at a low level and the writing control signal SW_ 2  at a low level are provided. When the first reset signal REST 1  is at a low level, the first transistor T 1  is turned on, and the first initialization signal V init  is applied to the gate of the second transistor T 2  to ensure that the second transistor T 2  may be turned on. When the writing control signal SW_ 2  is at a low level, the fourth transistor T 4 _ 2  is turned on, so that the electrical connection path between the data writing sub-circuit  204  and the second driving sub-circuit  201   2  is turned on. 
     During the initialization period t 4 , the scanning signal V scan  is at a high level, and therefore the third transistor T 3  is turned off. The writing control signal SW_ 1  is at a high level, and therefore the fourth transistor T 4 _ 1  is turned off, and the electrical connection path between the data writing sub-circuit  204  and the first driving sub-circuit  201   1  is turned off. The light-emitting control signal EM_ 2  is at a high level, so that the light-emitting element OLED 2  stops emitting light. When the data signals and the compensation signals are not written, the light-emitting elements OLED 1  and OLED 2  are generally in a light-emitting state, that is, the light-emitting control signals EM_ 1  and EM_ 2  are at a low level. Therefore, before a data signal and a compensation signal are written, a light-emitting state of a light-emitting element into which the data is to be written may be disabled. As shown in  FIG. 8A , before the initialization period t 4 , the light-emitting control signal EM_ 2  is set to a high level. 
     Next, during a data writing period t 5 , the writing control signal SW_ 2  is maintained at a low level, and therefore the fourth transistor T 4 _ 2  is maintained to be turned on. The second transistor T 2  is maintained to be turned on under control of the first initialization signal V init . The scanning signal V scan  at a low level and a valid second data signal V data2  are provided. When the scanning signal V scan  is at a low level, the third transistor T 3  is turned on. In a case where the second transistor T 2  and the third transistor T 3  are both turned on, the second data signal V data2  charges the second terminal (that is, the gate of the driving transistor DTFT_ 2 ) of the storage capacitor C_ 2  through the third transistor T 3 , the second transistor T 2 , and the fourth transistor T 4 _ 2 . The charging process does not end until a gate voltage V G2  of the driving transistor DTFT_ 2  is equal to V data2 +V′ th , wherein V′ th  represents a threshold voltage of the second transistor T 2 . Thereby, both the second data signal V data2  and the second compensation signal V′ th  are written into the gate of the driving transistor DTFT_ 2 . 
     During the data writing period t 5 , the first reset signal REST 1  is at a low level, and therefore the first transistor T 1  is turned off. The light-emitting control signal EM_ 2  and the writing control signal SW_ 1  are maintained at a high level, the light-emitting control signal EM_ 1  is maintained at a low level, and therefore states of the sixth transistor T 6 _ 2 , the fourth transistor T 4 _ 1 , and the sixth transistor T 6 _ 1  are maintained to be unchanged. 
     Next, during a period t 6  (that is, a fourth period), the scanning signal V scan  is set to a high level to stop writing data, the writing control signal SW_ 2  is set to a high level to turn off the electrical connection path between the data writing sub-circuit  204  and the second driving sub-circuit  201   2 , and the light-emitting control signal EM_ 2  at a low level is provided to cause the light-emitting element OLED 2  to emit light using the written second data signal V data2  and the written second compensation signal V′ th . Current generated by the driving transistor DTFT_ 2  is I 2 =K 2 ·(V GS2 −V th2 ) 2 , wherein V GS2 =V G2 −V DD =V data2 +V′ th −V DD , and V th2  is a threshold voltage of DTFT_ 2 , and is a negative value. Since V th2  may be set to V′ th , the current generated by the driving transistor DTFT_ 2  is I 2 =K 2 ·(V data2 −V DD ) 2 . That is, the resulting current has nothing to do with the threshold voltage of the driving transistor DTFT_ 2 , and has nothing to do with the temperature drift of the threshold voltage of DTFT_ 2 . Thereby, the electrical compensation is completed. 
     In some embodiments, the period t 3  and the period t 4  may be combined, that is, the data writing for the light-emitting element OLED 2  may be initialized while the light-emitting element OLED 1  is caused to emit light using the written first data signal V data1  and the written first compensation signal V′th, as shown in  FIG. 8B . The electrical connection path between the data writing sub-circuit  204  and the first driving sub-circuit  201   1  may be turned off by the writing control signal SW_ 1  before the data writing for the light-emitting element OLED 2  is initialized, so as to prevent the first driving sub-circuit  201   1  and the second driving sub-circuit  201   2  from being electrically coupled to the data writing sub-circuit  204  at the same time. Specific operations of the period t 3  (t 4 ) may be known with reference to  FIG. 8B  and the above related description of the period t 3  and the period t 4 , and will not be described in detail here. 
     It should be illustrated that, in the above description, the technical solutions according to the embodiments of the present disclosure are shown by way of example only, but it does not mean that the embodiments of the present disclosure are limited to the above steps and structures. Where possible, steps and structures may be adjusted and selected as needed. Therefore, certain steps and units are not elements necessary to implement the general inventive concept of the embodiments of the present disclosure. 
     The present disclosure has been described so far in connection with the preferred embodiments. It should be understood that those skilled in the art may make various other changes, substitutions, and additions without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of the embodiments of the present disclosure is not limited to the specific embodiments described above, but should be defined by the appended claims.