Patent Publication Number: US-11645073-B2

Title: Address-based filtering for load/store speculation

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation application of and claims priority from U.S. patent application Ser. No. 16/658,474, filed on Oct. 21, 2019. 
    
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     This disclosure was made with Government support under PathForward Project with Lawrence Livermore National Security (Prime Contract No. DE-AC52-07NA27344, Subcontract No. B620717) awarded by DOE. The Government has certain rights in this disclosure. 
    
    
     BACKGROUND 
     Computer processors that employ data speculation typically allow load and store instructions within the load store unit to complete out of program order. This data speculation requires that memory dependencies be checked for ordering violations to prevent ordering violation errors. These checks may require full physical address comparisons between a load or store and a subset of in-flight stores or loads. For some memory consistency models, the checks also require comparing the full physical address of an external probe to the physical address of an in-flight load. Preventing ordering violations typically involves the use of content addressable memory (CAM) structures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    sets forth a block diagram of an example system for address-based filtering for load/store speculation according to embodiments of the present disclosure. 
         FIG.  2    sets forth a block diagram of an example system for address-based filtering for load/store speculation according to embodiments of the present disclosure. 
         FIG.  3    sets forth a flow chart illustrating an exemplary method for address-based filtering for load/store speculation according to embodiments of the present disclosure. 
         FIG.  4    sets forth a flow chart illustrating an exemplary method for address-based filtering for load/store speculation according to embodiments of the present disclosure. 
         FIG.  5    sets forth a flow chart illustrating an exemplary method for address-based filtering for load/store speculation according to embodiments of the present disclosure. 
         FIG.  6    sets forth a flow chart illustrating an exemplary method for address-based filtering for load/store speculation according to embodiments of the present disclosure. 
         FIG.  7    sets forth a flow chart illustrating an exemplary method for address-based filtering for load/store speculation according to embodiments of the present disclosure. 
         FIG.  8    sets forth a flow chart illustrating an exemplary method for address-based filtering for load/store speculation according to embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Using content addressable memory (CAM) structures and lookup operations to prevent ordering violation errors is expensive in terms of power use. Therefore, by reducing the number of CAM lookups in the load store unit (LSU), the overall power use of the LSU is reduced. Embodiments of the present disclosure use a filtering mechanism to bypass memory operations such as CAM lookups for some incoming instructions. This filtering mechanism operates by maintaining a table of entries corresponding to addresses or address ranges of previously received store or load instructions. If an incoming store instruction, load instruction, or cache probe includes a target address in a range for which no previously received instruction has targeted that incoming store instruction, load instruction, or cache probe does not require a CAM lookup and is forwarded toward completion. This filtering mechanism, in some embodiments, is utilized in a number of different stages in the LSU pipeline. 
       FIG.  1    is a block diagram of a non-limiting example computing system ( 152 ) for address-based filtering for load/store speculation according to some embodiments. The computing system ( 152 ) of  FIG.  1    includes at least one computer processor ( 156 ) or ‘CPU’ as well as random access memory ( 168 ) (‘RAM’) which is connected through a high speed memory bus ( 166 ) and bus adapter ( 158 ) to processor ( 156 ) and to other components of the computing system ( 152 ). 
     Stored in RAM ( 168 ) is an operating system ( 154 ). Operating systems useful in computers for address-based filtering for load/store speculation include UNIX™, Linux™, Microsoft Windows™, AIX™, and others as will occur to those of skill in the art. The operating system ( 154 ) in the example of  FIG.  1    is shown in RAM ( 168 ), but many components of such software typically are stored in non-volatile memory also, such as, for example, on data storage ( 170 ), such as a disk drive. 
     The computing system ( 152 ) of  FIG.  1    includes disk drive adapter ( 172 ) coupled through expansion bus ( 160 ) and bus adapter ( 158 ) to processor ( 156 ) and other components of the computing system ( 152 ). Disk drive adapter ( 172 ) connects non-volatile data storage to the computing system ( 152 ) in the form of data storage ( 170 ). Disk drive adapters in some embodiments include Integrated Drive Electronics (‘IDE’) adapters, Small Computer System Interface (‘SCSI’) adapters, and others as will occur to those of skill in the art. Non-volatile computer memory, in some embodiments, is implemented as an optical disk drive, electrically erasable programmable read-only memory (so-called ‘EEPROM’ or ‘Flash’ memory), RAM drives, and so on, as will occur to those of skill in the art. 
     The example computing system ( 152 ) of  FIG.  1    includes one or more input/output (‘I/O’) adapters ( 178 ). I/O adapters implement user-oriented input/output through, for example, software drivers and computer hardware for controlling output to display devices such as computer display screens, as well as user input from user input devices ( 181 ) such as keyboards and mice. The example computing system ( 152 ) of  FIG.  1    includes a video adapter ( 209 ), which is an example of an I/O adapter specially designed for graphic output to a display device ( 180 ) such as a display screen or computer monitor. Video adapter ( 209 ) is connected to processor ( 156 ) through a high speed video bus ( 164 ), bus adapter ( 158 ), and the front side bus ( 162 ), which is also a high speed bus. 
     The exemplary computing system ( 152 ) of  FIG.  1    includes a communications adapter ( 167 ) for data communications with other computers and for data communications with a data communications network. Such data communications, in some embodiments, is carried out serially through RS-232 connections, through external buses such as a Universal Serial Bus (‘USB’), through data communications networks such as IP data communications networks, and in other ways as will occur to those of skill in the art. Communications adapters implement the hardware level of data communications through which one computer sends data communications to another computer, directly or through a data communications network. Examples of communications adapters, in some embodiments, includes modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications, and 802.11 adapters for wireless data communications. 
       FIG.  2    is a block diagram of a non-limiting example processor ( 156 ) for address-based filtering for load/store speculation according to some embodiments. As shown in  FIG.  2   , the example processor ( 156 ) includes a load store unit (LSU) ( 200 ), an address generation unit ( 202 ), control logic ( 204 ), a filtering table shift trigger ( 206 ), an ordering violation memory structure filtering table ( 208 ), and an ordering violation memory structure ( 210 ). The depiction of the LSU ( 200 ) in  FIG.  2    includes elements representative of different specific structures in the LSU ( 200 ). Specifically, the filtering table shift trigger ( 206 ) and the ordering violation memory structure ( 210 ), in some embodiments, apply to a number of different elements along the LSU ( 200 ) pipeline, as described below. 
     The LSU ( 200 ) is a portion of the processor ( 156 ) that executes load and store instructions. The LSU ( 200 ) is responsible for checking for memory dependencies and ordering violations when loads and stores are allowed to complete out of program order. The control logic ( 204 ) of the LSU ( 200 ) carries out the functionality of the LSU ( 200 ), including carrying out load instructions and store instructions to completion. The control logic ( 204 ) in  FIG.  2    is depicted as a separate element within the LSU ( 200 ) for illustrative purposes. In actuality, the control logic ( 204 ) is a collection of behaviors within and between other elements on the LSU ( 200 ). The address generation unit ( 202 ) computes the physical address for load instructions and store instructions, and provides the physical address to the LSU ( 200 ) as an initial step in carrying out the load instruction or store instruction. 
     The filtering table shift trigger ( 206 ) is a data structure used by the control logic ( 204 ) to trigger a shift in the filtering table ( 208 ). The control logic ( 204 ) monitors the filtering table shift trigger ( 206 ) for a specific condition upon which the control logic ( 204 ) initiates a shift in the filtering table ( 208 ). The shift in the filtering table is performed to maintain parity with the memory locations targeted by the load instructions and store instructions. The filtering table shift trigger ( 206 ), in some embodiments, is a queue allocated and deallocated in program order, such as the store queue (STQ) or load tracking queue (LTQ) of the LSU ( 200 ). The shift, in some embodiments, is triggered by the reuse of a particular pre-programed slot in the queue. The particular slot, in some embodiments, is pre-programmed using a basic input/output system (BIOS) setting. 
     The ordering violation memory structure ( 210 ) is a memory structure, such as a CAM structure, that operates as part of the control logic&#39;s memory dependency and ordering violation checks. Examples of ordering violation memory structures ( 210 ) include the store-to-load forwarding (STLF) CAM, the out-of-order buffer (OOB) CAM, and the load order queue (LOQ) CAM. Because lookup operations in these ordering violation memory structures are expensive in terms of power use, embodiments of the disclosure include a filtering table ( 208 ) to reduce the number of lookup operations by tracking residency of in-flight loads and stores in a pre-defined physical address range within the filtering table ( 208 ) without any full or partial address comparisons. 
     The STLF CAM is a memory structure used by the LSU ( 200 ) to verify that a load about to be executed has the same target address as an older store yet to be carried out. When the execution of the load is scheduled by the load store queue (LSQ), the control logic ( 204 ) compares all entries in the STLF CAM with the load&#39;s target address to determine whether there exists any prior older stores to the same target address as that of the load. The OOB CAM performs a similar function as the STLF CAM, but detects memory ordering violations between store instructions and load instructions that were missed when the load was first scheduled to memory by the LSQ. This is possible because at the time of the load&#39;s execution, not all prior older stores may have generated their physical addresses. A completed load stays in the OOB as long as it takes for all older stores to generate their physical addresses and check for dependencies. Similarly, the LOQ CAM detects memory ordering violations between load instructions (of the same or different threads) by monitoring cache events. Cache events include cache probes, such as a level 1 data cache probe, and cache evictions, such as a level 1 data cache eviction. 
     The ordering violation memory structure filtering table ( 208 ) is a mechanism to filter out, from the ordering violation memory structure ( 210 ), certain ordering check triggering transactions (e.g., load instructions, store instructions, and cache events) for which ordering violations including dependency violations exist. The filtering table ( 208 ) includes entries representing a target address (i.e., physical address or logical address) or range of target addresses of the ordering check triggering transactions. For example, the filtering table, in some embodiments, includes 2 N  entries, where N is a subset of the bits in the target address of the ordering check triggering transaction. A filtering table ( 208 ), in some embodiments, is implemented for each or any ordering violation memory structure ( 210 ) in the LSU ( 200 ). 
     The ordering violation memory structure filtering table ( 208 ), in some embodiments, is implemented as two or more separate filtering tables. Each of the filtering tables, in some embodiments, is devoted to a different set of ranges of target addresses. An initial determination, in some embodiments, is made by the control logic ( 204 ) as to which of the filtering tables to query based on a portion of the target address. 
       FIG.  3    sets forth a flow chart illustrating a non-limiting exemplary method for address-based filtering for load/store speculation according to some embodiments that includes maintaining ( 302 ) a filtering table including table entries associated with ranges of addresses. Maintaining ( 302 ) a filtering table including table entries associated with ranges of addresses, in some embodiments, is carried out by the control logic ( 204 ) placing indications in the filtering table for potential ordering violations. Maintaining ( 302 ) a filtering table including table entries associated with ranges of addresses, in some embodiments, is carried out by the control logic ( 204 ) shifting the table entry based on a condition of a filtering table shift trigger. 
     The method of  FIG.  3    further includes in response to receiving an ordering check triggering transaction ( 320 ), querying ( 304 ) the filtering table ( 208 ) using a target address of the ordering check triggering transaction ( 320 ) to determine if an instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address. Receiving an ordering check triggering transaction ( 320 ), in some embodiments, is carried out by the control logic ( 204 ) detecting that the address generation unit has provided a physical address for an ordering check triggering transaction ( 320 ) (e.g., a load instruction, a store instruction, a cache event). The control logic ( 204 ), in some embodiments, receives the physical address from the address generation unit and extracts a subset of the physical address for use as a key into the filtering table ( 208 ). Alternatively, the control logic ( 204 ), in some embodiments, uses a portion of the logical address as a key into the filtering table ( 208 ). 
     Querying ( 304 ) the filtering table ( 208 ) using a target address of the ordering check triggering transaction ( 320 ) to determine if an instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address, in some embodiments, is carried out by the control logic ( 204 ) generating a query entry identifier using a portion of the target address (i.e., physical address or logical address) and accessing the entry identified by the entry identifier. For example, the entry identifier, in some embodiments, is generated from the physical address using [M:M+N−1], where M is the starting address of memory window and N is the subset of physical address bits for the filtering table ( 208 ). 
     The method of  FIG.  3    further includes in response to determining that the filtering table ( 208 ) lacks an indication that the instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address, bypassing ( 306 ) a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction ( 320 ) is currently in-flight. “In-flight” refers to an instruction that has been completed but not yet retired. Determining that the filtering table ( 208 ) lacks an indication that the instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address, in some embodiments, is carried out by the control logic ( 204 ) accessing the entry in the filtering table and determining that the entry&#39;s contents are zero. Because there is no indication of a previous instruction dependent upon the ordering check triggering transaction ( 320 ), the control logic ( 204 ) is assured that no previous dependent instruction is currently in-flight (i.e., data has not been loaded from or stored to the target physical address by any in-flight instruction in the pipeline). 
     Bypassing ( 306 ) a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction ( 320 ) is currently in-flight, in some embodiments, is carried out by the control logic ( 204 ) operating as though the lookup operation in the ordering violation memory structure has been performed, and a response has been returned that indicates that no instruction dependent upon the ordering check triggering transaction ( 320 ) is currently in-flight (i.e. data has not been loaded from or stored to the target physical address by any in-flight instruction in the pipeline). 
     The above features improve the operation of the computer system by avoiding expensive lookup operations in memory structures by maintaining a filtering table for incoming ordering check triggering transactions (e.g., load instructions, store instructions, cache events) where, in some circumstances, a lack of dependent instructions can be identified using a less expensive accessing of the filtering table. Further, by lowering the dynamic power consumption without performance degradation, the execution of applications that execute large numbers of load/store micro-operations in the processor core is made more power efficient. 
     For further explanation,  FIG.  4    sets forth a flow chart illustrating a further exemplary method for address-based filtering for load/store speculation according to embodiments that includes maintaining ( 302 ) a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction ( 320 ), querying ( 304 ) the filtering table ( 208 ) using a target address of the ordering check triggering transaction ( 320 ) to determine if an instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address; and in response to determining that the filtering table ( 208 ) lacks an indication that the instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address, bypassing ( 306 ) a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction ( 320 ) is currently in-flight. 
     The method of  FIG.  4    differs from the method of  FIG.  3   , however, in that the method of  FIG.  4    further includes in response to determining that the filtering table ( 208 ) includes an indication that the instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address, performing ( 402 ) a lookup operation in an ordering violation memory structure ( 210 ) to determine whether the instruction dependent upon the ordering check triggering transaction ( 320 ) is currently in-flight. 
     Determining that the filtering table ( 208 ) includes an indication that the instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address, in some embodiments, is carried out by the control logic ( 204 ) accessing the entry in the filtering table and determining that the entry is not zero (i.e., the entry has been marked to indicate that a previous dependent instruction potentially is in-flight (i.e., data has not been loaded from or stored to the target physical address by any in-flight instruction)). If each entry represents a range of addresses, the marking of an entry does not necessarily indicate the existence of an ordering violation. Instead, the mark indicates that a dependent instruction has had a physical address generated that targets the same range. Because there is an indication of a previous instruction potentially dependent upon the ordering check triggering transaction ( 320 ), the control logic ( 204 ) has no assurance that a previous dependent instruction is not currently in-flight (i.e., data has not been loaded from or stored to the target physical address by any in-flight instruction). In such a case, the comparatively more expensive lookup operations in the ordering violation memory structure ( 210 ) is performed to determine whether the instruction dependent upon the ordering check triggering transaction ( 320 ) is currently in-flight. 
     For further explanation,  FIG.  5    sets forth a flow chart illustrating a further exemplary method for address-based filtering for load/store speculation according to embodiments that includes maintaining ( 302 ) a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction ( 320 ), querying ( 304 ) the filtering table ( 208 ) using a target address of the ordering check triggering transaction ( 320 ) to determine if an instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address; and in response to determining that the filtering table ( 208 ) lacks an indication that the instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address, bypassing ( 306 ) a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction ( 320 ) is currently in-flight. 
     The method of  FIG.  5    differs from the method of  FIG.  3   , however, in that maintaining ( 302 ) a filtering table including table entries associated with ranges of addresses includes detecting ( 502 ) that a dependent instruction has generated a physical address; indicating ( 504 ), in an entry of filtering table ( 208 ) associated with a target address of the dependent instruction, that the dependent instruction generated the physical address; and shifting ( 506 ) the table entries in the filtering table ( 208 ) in response to detecting that a particular slot has been reused in a queue deallocated in program order. 
     Detecting ( 502 ) that a dependent instruction has generated a physical address, in some embodiments, is carried out by the control logic ( 204 ) being notified by the address generation unit ( 202 ) that a physical address for a particular type of dependent instruction (e.g., a load instruction or a store instruction) has been generated. The control logic ( 204 ), in some embodiments, receives the physical address for the instruction, the logical address for the instruction, or a portion of either. 
     Indicating ( 504 ), in an entry of filtering table ( 208 ) associated with a target address of the dependent instruction, that the dependent instruction generated the physical address, in some embodiments, is carried out by the control logic ( 204 ) marking an entry for the target address in the filtering table ( 208 ). The control logic ( 204 ), in some embodiments, marks the entry in a manner that uses a minimal amount of power. For example, the control logic ( 204 ), in some embodiments, writes a value of “0x03” to indicate a non-zero entry. 
     Detecting that a particular slot has been reused in a queue deallocated in program order, in some embodiments, is carried out by the control logic ( 204 ) monitoring the filtering table shift trigger ( 206 ) for the condition upon which the filtering table ( 208 ) is to be shifted. The condition in some embodiments, is the reuse of a specified slot in the queue. Shifting ( 506 ) the table entries in the filtering table ( 208 ) in response to detecting that a particular slot has been reused in a queue deallocated in program order, in some embodiments, is carried out by the control logic ( 204 ) advancing each table entry by one unit to ensure that when an entry is zero then there is no load/store in-flight with the same physical address bits as the address indexing. The queue deallocated in program order in some embodiments, is the store queue or the load tracking queue, depending upon the ordering violation memory structure for which the filtering is performed. Alternatively, the filtering table shift trigger ( 206 ), in some embodiments, is the detection of a reuse of a pre-selected reorder buffer ID in the instruction window. 
     For further explanation,  FIGS.  6 ,  7 , and  8    set forth flow charts illustrating contextual examples of the methods described in  FIGS.  3 ,  4 , and  5   . Specifically,  FIGS.  6 ,  7 , and  8    set forth flow charts illustrating examples in the context of a store-to-load forwarding (STLF) CAM, an out-of-order buffer (OOB) CAM, and a load order queue (LOQ) CAM, respectively.  FIG.  6    sets forth a flow chart illustrating an exemplary method for address-based filtering for load/store speculation according to embodiments within the context of a STLF CAM. As in the combination of  FIGS.  3 ,  4 , and  5   ,  FIG.  6    includes maintaining ( 302 ) a filtering table including table entries associated with ranges of addresses, including detecting ( 502 ) that a dependent (store) instruction has generated a physical address, indicating ( 504 ), in an entry of filtering table ( 208 A) associated with a target address of the dependent (store) instruction, that the dependent (store) instruction generated the physical address, and shifting ( 506 ) the table entries in the filtering table ( 208 A) in response to detecting that a particular slot has been reused in a queue deallocated in program order.  FIG.  6    further includes in response to receiving an ordering check triggering transaction (load instruction) ( 320 ), querying ( 304 ) the filtering table ( 208 A) using a target address of the ordering check triggering transaction (load instruction) ( 320 ) to determine if a (store) instruction dependent upon the ordering check triggering transaction (load instruction) ( 320 ) has previously been generated a physical address; in response to determining that the filtering table ( 208 A) lacks an indication that the (store) instruction dependent upon the ordering check triggering transaction (load instruction) ( 320 ) has previously been generated a physical address, bypassing ( 306 ) a lookup operation in an ordering violation memory structure to determine whether the (store) instruction dependent upon the ordering check triggering transaction (load instruction) ( 320 ) is currently in-flight; and in response to determining that the filtering table ( 208 A) includes an indication that the (store) instruction dependent upon the ordering check triggering transaction (load instruction) ( 320 ) has previously been generated a physical address, performing ( 402 ) a lookup operation in an ordering violation memory structure ( 210 A) to determine whether the (store) instruction dependent upon the ordering check triggering transaction (load instruction) ( 320 ) is currently in-flight. 
     In the example method of  FIG.  6   , detecting ( 502 ) that a dependent instruction has generated a physical address is carried out by the control logic ( 204 ) detecting that a store instruction has been generated a physical address by the address generation unit ( 202 A). Each time the control logic ( 204 ) is notified that the address generation unit ( 202 A) has generated a physical address for a store instruction, the filtering table ( 208 A) for the STLF CAM ( 210 A) is updated. Specifically, in the example method of  FIG.  6   , indicating ( 504 ), in an entry of filtering table ( 208 A) associated with a target address of the dependent instruction, that the dependent instruction generated the physical address is carried out by the control logic ( 204 ) using a subset of the bits of the target address (i.e., a portion of the physical address or logical address) of the store instruction as an identification of an entry in the filtering table ( 208 A) for the STLF CAM ( 210 A). That entry, representing a range of target addresses, is marked with 0x03. This action indicates that an in-flight store instruction exists that targets an address within the indicated entry range. 
     In the example method of  FIG.  6   , shifting ( 506 ) the table entries in the filtering table ( 208 A) in response to detecting that a particular slot has been reused in a queue deallocated in program order is carried out by the control logic ( 204 ) detecting that a pre-programmed slot in the store queue ( 206 A) has been reused. In the event of a pipeline partial or full flush the table is not modified. Because the store queue is allocated and deallocated in program order, the store queue operates in a similar manner to a first-in-first-out queue, and a flush of the table is therefore not necessary. 
     In the example method of  FIG.  6   , receiving an ordering check triggering transaction ( 320 ) is carried out by the control logic ( 204 ) detecting that a load instruction has been generated a physical address by the address generation unit ( 202 A). Each time the control logic ( 204 ) is notified that the address generation unit ( 202 A) has generated a physical address for a load instruction, the filtering table ( 208 A) for the STLF CAM ( 210 A) is queried. In the example method of  FIG.  6   , querying ( 304 ) the filtering table ( 208 A) using a target address of the ordering check triggering transaction ( 320 ) to determine if an instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address is carried out by the control logic ( 204 ) querying the filtering table ( 208 A) using the target address of the load instruction to determine if an in-flight store instruction has previously been generated a physical address in the same range of the target address of the load instruction. 
     In the example method of  FIG.  6   , determining that the filtering table ( 208 A) lacks an indication that the instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address is carried out by the control logic ( 204 ) accessing the STLF CAM filtering table ( 208 A) using a portion of the target address of the load instruction and reading out a zero entry (e.g., “0x0”). Consequently, the control logic ( 204 ) determines that the associated entry in the filtering table ( 208 A) lacks an indication that an in-flight store instruction for the same target address range has previously been generated a physical address by the address generation unit ( 202 A). 
     In the example method of  FIG.  6   , bypassing ( 306 ) a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction ( 320 ) is currently in-flight is carried out by the control logic ( 204 ) bypassing the lookup operation in the STLF CAM ( 210 A) to determine whether the store instruction is currently in-flight (i.e., whether data was stored in the target physical address by an in-flight store instruction). 
     In the example method of  FIG.  6   , determining that the filtering table ( 208 A) includes an indication that the instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address is carried out by the control logic ( 204 ) accessing the STLF CAM filtering table ( 208 A) using a portion of the target address of the load instruction and reading out a non-zero entry. Consequently, the control logic ( 204 ) determines that the associated entry in the filtering table ( 208 A) includes an indication that an in-flight store instruction for the same target address range has previously been generated a physical address by the address generation unit ( 202 A). 
     In the example method of  FIG.  6   , performing ( 402 ) a lookup operation in an ordering violation memory structure ( 210 A) to determine whether the instruction dependent upon the ordering check triggering transaction ( 320 ) is currently in-flight is carried out by the control logic ( 204 ) performing a CAM lookup operation on the STLF CAM ( 210 A) to determine whether the load instruction is subject to a dependency with an in-flight store instruction. 
       FIG.  7    sets forth a flow chart illustrating an exemplary method for address-based filtering for load/store speculation according to embodiments within the context of an OOB CAM. As in the combination of  FIGS.  3 ,  4 , and  5   ,  FIG.  7    includes maintaining ( 302 ) a filtering table including table entries associated with ranges of addresses, including detecting ( 502 ) that a dependent (load) instruction has generated a physical address, indicating ( 504 ), in an entry of filtering table ( 208 B) associated with a target address of the dependent (load) instruction, that the dependent (load) instruction generated the physical address, and shifting ( 506 ) the table entries in the filtering table ( 208 B) in response to detecting that a particular slot has been reused in a queue deallocated in program order.  FIG.  7    further includes in response to receiving an ordering check triggering transaction (store instruction) ( 320 ), querying ( 304 ) the filtering table ( 208 B) using a target address of the ordering check triggering transaction (store instruction) ( 320 ) to determine if a (load) instruction dependent upon the ordering check triggering transaction (store instruction) ( 320 ) has previously been generated a physical address; in response to determining that the filtering table ( 208 B) lacks an indication that the (load) instruction dependent upon the ordering check triggering transaction (store instruction) ( 320 ) has previously been generated a physical address, bypassing ( 306 ) a lookup operation in an ordering violation memory structure to determine whether the (load) instruction dependent upon the ordering check triggering transaction (store instruction) ( 320 ) is currently in-flight; and in response to determining that the filtering table ( 208 B) includes an indication that the (load) instruction dependent upon the ordering check triggering transaction (store instruction) ( 320 ) has previously been generated a physical address, performing ( 402 ) a lookup operation in an ordering violation memory structure ( 210 B) to determine whether the (load) instruction dependent upon the ordering check triggering transaction (store instruction) ( 320 ) is currently in-flight. 
     In the example method of  FIG.  7   , detecting ( 502 ) that a dependent instruction has generated a physical address is carried out by the control logic ( 204 ) detecting that a load instruction has been generated a physical address by the address generation unit ( 202 B). Each time the control logic ( 204 ) is notified that the address generation unit ( 202 B) has generated a physical address for a load instruction, the filtering table ( 208 B) for the OOB CAM ( 210 B) is updated. Specifically, in the example method of  FIG.  7   , indicating ( 504 ), in an entry of filtering table ( 208 B) associated with a target address of the dependent instruction, that the dependent instruction generated the physical address is carried out by the control logic ( 204 ) using a subset of the bits of the target address (i.e., a portion of the physical address or logical address) of the load instruction as an identification of an entry in the filtering table ( 208 B) for the OOB CAM ( 210 B). That entry, representing a range of target addresses, is marked with 0x03. This action indicates that an in-flight load instruction exists that targets an address within the indicated entry range. 
     In the example method of  FIG.  7   , shifting ( 506 ) the table entries in the filtering table ( 208 B) in response to detecting that a particular slot has been reused in a queue deallocated in program order is carried out by the control logic ( 204 ) detecting that a pre-programmed slot in the load tracking queue ( 206 B) has been reused. The load tracking queue ( 206 B) is a bit vector indexed by load ID and is allocated at dispatch (in program order) and deallocated at retire (again in program order). The load tracking queue ( 206 B) sets a bit when the corresponding load ID has been reserved by an in-flight load. The load tracking queue ( 206 B) is managed as a first-in-first-out queue and upon a pipeline flush, the load tracking queue ( 206 B) is cleared with the load ID of the offending load or with the load ID of the oldest load closest to the offending instruction or micro-op that triggered the pipeline flush. 
     In the example method of  FIG.  7   , receiving an ordering check triggering transaction ( 320 ) is carried out by the control logic ( 204 ) detecting that a store instruction has been generated a physical address by the address generation unit ( 202 B). Each time the control logic ( 204 ) is notified that the address generation unit ( 202 B) has generated a physical address for a store instruction, the filtering table ( 208 B) for the OOB CAM ( 210 B) is queried. In the example method of  FIG.  7   , querying ( 304 ) the filtering table ( 208 B) using a target address of the ordering check triggering transaction ( 320 ) to determine if an instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address is carried out by the control logic ( 204 ) querying the filtering table ( 208 B) using the target address of the store instruction to determine if a load instruction has previously been generated a physical address in the same range of the target address of the store instruction. 
     In the example method of  FIG.  7   , determining that the filtering table ( 208 B) lacks an indication that the instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address is carried out by the control logic ( 204 ) accessing the OOB CAM filtering table ( 208 B) using a portion of the target address of the store instruction and reading out a zero entry. Consequently, the control logic ( 204 ) determines that the associated entry in the filtering table ( 208 B) lacks an indication that a load instruction for the same target address range has previously been generated a physical address by the address generation unit ( 202 B). 
     In the example method of  FIG.  7   , bypassing ( 306 ) a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction ( 320 ) is currently in-flight is carried out by the control logic ( 204 ) bypassing the lookup operation in the OOB CAM ( 210 B) to determine whether the load instruction is currently in-flight (i.e., whether data was loaded from the targeted physical address by an in-flight load). 
     In the example method of  FIG.  7   , determining that the filtering table ( 208 B) includes an indication that the instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address is carried out by the control logic ( 204 ) accessing the OOB CAM filtering table ( 208 B) using a portion of the target address of the store instruction and reading out a non-zero entry. Consequently, the control logic ( 204 ) determines that the associated entry in the filtering table ( 208 B) includes an indication that a load instruction for the same target address range has previously been generated a physical address by the address generation unit ( 202 B). 
     In the example method of  FIG.  7   , performing ( 402 ) a lookup operation in an ordering violation memory structure ( 210 B) to determine whether the instruction dependent upon the ordering check triggering transaction ( 320 ) is currently in-flight is carried out by the control logic ( 204 ) performing a CAM lookup operation on the OOB CAM ( 210 B) to determine whether the store instruction is subject to an ordering violation. 
       FIG.  8    sets forth a flow chart illustrating an exemplary method for address-based filtering for load/store speculation according to embodiments within the context of a LOQ CAM. As in the combination of  FIGS.  3 ,  4 , and  5   ,  FIG.  8    includes maintaining ( 302 ) a filtering table including table entries associated with ranges of addresses, including detecting ( 502 ) that a dependent (first load) instruction has generated a physical address, indicating ( 504 ), in an entry of filtering table ( 208 C) associated with a target address of the dependent (first load) instruction, that the dependent (first load) instruction generated the physical address, and shifting ( 506 ) the table entries in the filtering table ( 208 C) in response to detecting that a particular slot has been reused in a queue deallocated in program order.  FIG.  8    further includes in response to receiving an ordering check triggering transaction (second load instruction) ( 320 ), querying ( 304 ) the filtering table ( 208 C) using a target address of the ordering check triggering transaction (second load instruction) ( 320 ) to determine if an (first load) instruction dependent upon the ordering check triggering transaction (second load instruction) ( 320 ) has previously been generated a physical address; in response to determining that the filtering table ( 208 C) lacks an indication that the (first load) instruction dependent upon the ordering check triggering transaction (second load instruction) ( 320 ) has previously been generated a physical address, bypassing ( 306 ) a lookup operation in an ordering violation memory structure to determine whether the (first load) instruction dependent upon the ordering check triggering transaction (second load instruction) ( 320 ) is currently in-flight; and in response to determining that the filtering table ( 208 C) includes an indication that the (first load) instruction dependent upon the ordering check triggering transaction (second load instruction) ( 320 ) has previously been generated a physical address, performing ( 402 ) a lookup operation in an ordering violation memory structure ( 210 C) to determine whether the (first load) instruction dependent upon the ordering check triggering transaction (second load instruction) ( 320 ) is currently in-flight. 
     In the example method of  FIG.  8   , detecting ( 502 ) that a dependent instruction has generated a physical address is carried out by the control logic ( 204 ) detecting that a load instruction has been generated a physical address by the address generation unit ( 202 C). Each time the control logic ( 204 ) is notified that the address generation unit ( 202 C) has generated a physical address for a load instruction, the filtering table ( 208 C) for the LOQ CAM ( 210 C) is updated. Specifically, in the example method of  FIG.  8   , indicating ( 504 ), in an entry of filtering table ( 208 C) associated with a target address of the dependent instruction, that the dependent instruction generated the physical address is carried out by the control logic ( 204 ) using a subset of the bits of the target address (i.e., a portion of the physical address or logical address) of the load instruction as an identification of an entry in the filtering table ( 208 C) for the LOQ CAM ( 210 C). That entry, representing a range of target addresses, is marked with 0x03. This action indicates that an in-flight load instruction exists that targets an address within the indicated entry range. 
     In the example method of  FIG.  8   , shifting ( 506 ) the table entries in the filtering table ( 208 C) in response to detecting that a particular slot has been reused in a queue deallocated in program order is carried out by the control logic ( 204 ) detecting that a pre-programmed slot in the load tracking queue ( 206 C) has been reused. The load tracking queue ( 206 C), in some embodiments, is used as a filtering table shift trigger in both the OOB CAM context and the LOQ CAM contexts. 
     In the example method of  FIG.  8   , receiving an ordering check triggering transaction ( 320 ) is carried out by the control logic ( 204 ) detecting that a cache probe or cache eviction has occurred. Each time the control logic ( 204 ) is notified that a cache probe or cache eviction has occurred, the filtering table ( 208 C) for the LOQ CAM ( 210 B) is queried. In the example method of  FIG.  8   , querying ( 304 ) the filtering table ( 208 C) using a target address of the ordering check triggering transaction ( 320 ) to determine if an instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address is carried out by the control logic ( 204 ) querying the filtering table ( 208 C) using the target address of the cache probe or cache eviction victim to determine if a load instruction has previously been generated a physical address in the same range of the target address of the cache probe or cache eviction victim. 
     In the example method of  FIG.  8   , determining that the filtering table ( 208 C) lacks an indication that the instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address is carried out by the control logic ( 204 ) accessing the LOQ CAM filtering table ( 208 C) using a portion of the target address of the cache probe and reading out a zero entry. Consequently, the control logic ( 204 ) determines that the associated entry in the filtering table ( 208 B) lacks an indication that a load instruction for the same target address range has previously been generated a physical address by the address generation unit ( 202 C). 
     In the example method of  FIG.  8   , bypassing ( 306 ) a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction ( 320 ) is currently in-flight is carried out by the control logic ( 204 ) bypassing the lookup operation in the LOQ CAM ( 210 C) to determine whether the load instruction is currently in-flight (i.e., whether data was loaded from the targeted physical address by an in-flight load). 
     In the example method of  FIG.  8   , determining that the filtering table ( 208 C) includes an indication that the instruction dependent upon the ordering check triggering transaction ( 320 ) has previously been generated a physical address is carried out by the control logic ( 204 ) accessing the LOQ CAM filtering table ( 208 C) using a portion of the target address of the cache probe and reading out a non-zero entry. Consequently, the control logic ( 204 ) determines that the associated entry in the filtering table ( 208 C) includes an indication that a load instruction for the same target address range has previously been generated a physical address by the address generation unit ( 202 C). 
     In the example method of  FIG.  8   , performing ( 402 ) a lookup operation in an ordering violation memory structure ( 210 C) to determine whether the instruction dependent upon the ordering check triggering transaction ( 320 ) is currently in-flight is carried out by the control logic ( 204 ) performing a CAM lookup operation on the LOQ CAM ( 210 C) to determine whether the cache probe or cache eviction victim is subject to a memory ordering violation. 
     In view of the explanations set forth above, readers will recognize that the benefits of address-based filtering for load/store speculation according to embodiments include:
         Improving the operation of a computing system by maintaining a filtering table for incoming ordering check triggering transactions (e.g., load instructions, store instructions, cache probes, cache eviction) where, in some circumstances, a lack of dependent instructions can be identified using a less expensive accessing of the filtering table, increasing computing system power efficiency.   Improving the operation of a computing system by lowering the dynamic power consumption without performance degradation, increasing the power efficiency of load/store micro-operations in the processor core.       

     Exemplary embodiments are described largely in the context of a fully functional computer system for address-based filtering for load/store speculation. Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions. 
     The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions. 
     The above describes a method of address-based filtering for load/store speculation, including maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight. 
     The method may include, in response to determining that the filtering table includes an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, performing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight. 
     The above also describes a load store unit of a processor, a processor, and an apparatus with address-based filtering for load/store speculation. The load store unit includes a filtering table including table entries associated with ranges of addresses, and the control logic for the load store unit maintains the filtering table; in response to receiving an ordering check triggering transaction, query the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, bypass a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight. 
     The control logic, in response to determining that the filtering table includes an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, performs a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight. 
     Maintaining the filtering table including table entries for ranges of addresses may include detecting that a dependent instruction has generated a physical address; and indicating, in an entry of filtering table associated with a target address of the dependent instruction, that the dependent instruction generated the physical address. Maintaining the filtering table including table entries associated with ranges of addresses may also include shifting the table entries in the filtering table in response to detecting that a particular slot has been reused in a queue deallocated in program order. The queue deallocated in program order may be a store queue or a load tracking queue. Maintaining the filtering table including table entries associated with ranges of addresses may also include shifting the table entries in the filtering table in response to detecting a reuse of a pre-selected reorder buffer ID. The filtering table may include a plurality of separate tables. 
     The ordering check triggering transaction may be a load instruction. Accordingly, receiving the ordering check triggering transaction may include detecting that the load instruction has been generated a physical address, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address may include querying the filtering table using the target address of the load instruction to determine if a store instruction has previously been generated a physical address, determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address may include determining that the filtering table lacks an indication that the store instruction has previously been generated a physical address, and bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight may include bypassing the lookup operation in a store-to-load forwarding memory structure to determine whether the store is currently in-flight. 
     The ordering check triggering transaction may be a store instruction. Accordingly, receiving the ordering check triggering transaction may include detecting that the store instruction has been generated a physical address, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address may include querying the filtering table using the target address of the store instruction to determine if a load instruction has previously been generated a physical address, determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address may include determining that the filtering table lacks an indication that the load instruction has previously been generated a physical address, and bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight may include bypassing the lookup operation in an out-of-order buffer memory structure to determine whether the load is currently in-flight. 
     Readers will appreciate that the steps described herein may be carried out in a variety of ways and that no particular ordering is required. It will be further understood from the foregoing description that modifications and changes may be made in various embodiments of the present disclosure. The descriptions in this specification are for purposes of illustration only and are not to be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.