Patent Publication Number: US-6711658-B2

Title: Architecture and configuring method for a computer expansion board

Description:
This application is a continuation of U.S. application Ser. No. 08/570,256, filed Dec. 11,1995 now U.S. Pat. No. 6,240,496 which is a continuation of U.S. application Ser. No. 08/152,264, filed Nov. 12, 1993 (now abandoned) which is a continuation of U.S. application Ser. No. 07/440,826, filed Nov. 24, 1989 (now abandoned). 
    
    
     The present invention relates to an architecture for computer expansion boards. More particularly, it relates to an architecture which reduces the number of pins required to transfer configuration bits within such board. 
     BACKGROUND OF THE INVENTION 
     Many computer systems, such as the personal computer (PC) may be purchased with differing levels of functionality and/or storage capacity. Increased functionality and/or storage capacity may be obtained through upgrading a basic unit by connecting add-on boards to “expansion slots” provided on the PC. A typical expansion board is available to increase the memory capacity of the PC. Other expansion boards provide additional or supplemental processing power and/or provide interface capabilities for a variety of input/output (I/O) functions. Many such expansion boards include a microprocessor or controller to perform a designated function. 
     When an expansion board is added to a PC, the board may need to be provided with certain information that defines its relationship to the host or to other parts of the system. For example, a memory board that is to be addressable by the host must be provided with its starting and ending address so that it can function appropriately with respect to the other memory in the system. Other expansion boards may also have addressable memory space which requires a starting and ending address. In addition, there may be other information required by such other boards. For example, an expansion board for connecting the host to a local area network (LAN) may need information specifying its network node number, defining its interrupt level, etc. 
     The bits of data which define the information provided to the board are referred to as configuration bits and the act of providing the data bits to the board is referred to as configuring the board. Some boards are configured by manually operated switches which are connected to the board. These switches can be set prior to attaching the board to the host computer. When the board is powered up, the switches are read by the on board microprocessor or controller and the configuration information stored in the appropriate register for use as needed. 
     In the past, the on board microprocessor or controller received the configuration bits on dedicated lines. Since the microprocessor or controller is typically implemented as an integrated circuit chip, each line requires an additional pin. The number of pins used solely for configuration bits will vary but in some LAN cards is thirty-two. Together with the various control, data and address lines, the total number of pins can exceed one hundred. In general, the cost of a chip increases with an increase in the number of pins. In addition, the cost of the board to which the chip is attached is also more expensive in order to accommodate the extra pins. 
     OBJECTS OF THE INVENTION 
     It is therefore an object of the present invention to provide a new and improved circuit board for connecting to a host computer. 
     It is another object of the present invention to provide an enhancement board having a controller chip with a reduced number of pins. 
     It is a further object of the present invention to provide a new and improved method for configuring a circuit board connectable to a host computer. 
     It is yet another object of the present invention to provide an improved architecture for configuring an enhancement board. 
     SUMMARY OF THE INVENTION 
     One form of the present invention is a circuit board for connecting to a host computer. The board comprises a controller chip, a parallel bus, a memory for storing a plurality of configuration data bits, and a control line. The controller chip controls the operation of the board and has an internal register for storing a plurality of data bits. The parallel bus transfers data bits between the controller chip and other components on the board and is connected to the memory. The control line is connected between the controller and the memory for enabling the output of the memory to transfer the configuration bits to the internal register over the bus. 
     Another form of the present invention is a method for configuring a circuit board connectable to a host computer. The circuit board has a controller chip, an internal parallel data bus connected to the chip, and a memory connected to the bus. The method comprises programming the configuration data bits into the memory, providing a control signal to the memory, and transferring the configuration data bits to the controller over the bus. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A and 1B show a block diagram of an expansion circuit board which embodies the present invention. 
    
    
     DESCRIPTION OF A PREFERRED EMBODIMENT 
     FIGS. 1A and 1B show an expansion or circuit board  10  for connecting to a host computer  12  by means of a connector  14 . It will be clear from the following discussion that the architecture and method of the present invention has applicability to a variety of expansion boards. In the embodiment described herein, circuit board  10  is a LAN board, and, more particularly, is a board for interfacing a PC to an ARCNET network. (ARCNET is a type of LAN which employs a token passing system and in which all nodes hear all messages but only respond to those messages addressed to them.) 
     Circuit board  10  includes a controller  16 . In the described embodiment, controller  16  is a 90C198 ARCNET Controller chip available from NCR Microelectronics Products, 2001 Danfield Court, Fort Collins, Colo. 80525. Controller chip  16  controls the operation of board  10 . Chip  16  has internal registers  18   a  and  18   b , each capable of storing a plurality of data bits. Other components of board  10  include ROMs  20 , transceivers  22 , latches  24 , RAMs  26 , and a transceiver hyprid  28 , connected as shown. Circuit board  10  also includes an internal parallel bus  30  multiplexed for transferring both address and data bits between controller  16  and other components on board  10 . For example, each RAM  26  has an address port A 0 -A 12  connected to bus  30  through latches  24 , and a data port D 0 -D 7  connected to bus  30 . 
     Circuit board  10  also includes a memory  32  for storing a plurality of configuration control bits as will be explained. Memory  32  is connected to bus  30  and includes memory banks  34   a  and  34   b . Each memory bank  34   a  and  34   b  has a plurality of manual switches  36   a  and  36   b , respectively, for programming configuration data into memory  32 . Each memory bank  34   a  and  34   b  also has a plurality of tri-state buffers  38   a  and  38   b , respectively. Buffers  38   a  and  38   b  are connected between switches  36   a  and  36   b , respectively, and bus  30 . Other means for programming configuration data bits into memory  32  other than manual switches  36   a  and  36   b  are within the scope of the present invention. For example, memory banks  34   a  and  34   b  could consist of a programmable array logic (PAL). A PAL will provide a single fixed configuration. This means that the PAL would need to be replaced in order to change the address space. 
     Control lines  40   a  and  40   b  are connected between controller  16  and tri-state buffers  38   a  and  38   b , respectively. 
     In operation, configuration data bits are programmed into memory banks  34   a  and  34   b  by setting the manual switches  36   a  and  36   b , respectively. For example, some of the configuration data bits define the address space occupied by board  10  with respect to host computer  12 . The information defining the address space of the memory within board  10  is provided to board  10  by setting a plurality of the switches  36   a  and/or  36   b . Typically, switches  36   a  and  36   b  are set prior to board  10  being connected to host computer  12 . However, it may be possible to first connect board  10  to host computer  12 . 
     When power is provided to board  10 , controller  16  executes a series of microinstructions. These instructions include the serial generation of control signals to memory banks  34   a  and  34   b  over control lines  40   a  and  40   b , respectively. When the first control signal over control line  40   a  is received by tri-state buffer  38   a , its output is enabled and the configuration data bits in buffer  38   a  are transferred in parallel over bus  30  to register  18   a  within controller  16 . Similarly, when the second control signal over control line  40   b  is received by tri-state buffer  38   b , its output is enabled and the configuration data bits in buffer  38   b  are transferred in parallel over bus  30  to register  18   b  within controller  16 . In this manner, all of the configuration data bits are transferred into controller chip  16  over bus  30 . The only pins over and above those required for the normal operation of controller chip  16  are those associated with control lines  40   a  and  40   b . Once the configuration data bits are written into registers  18   a  and  18   b , controller  16  will continue its power up routine utilizing the configuration data bits to configure board  10 . 
     It will be clear to those skilled in the art that the present invention is not limited to the specific embodiment disclosed and illustrated herein. For example, subject to the width of bus  30  and the number of configuration data bits required by board  10 , any number of memory banks  34  and corresponding control lines  40  may be employed. In addition, the term “controller”, as used herein, is intended to include any microprocessor. 
     Numerous modifications, variations, and full and partial equivalents can be undertaken without departing from the invention as limited only by the spirit and scope of the appended claims. 
     What is desired to be secured by Letters Patent of the United States is as follows.