Patent Publication Number: US-11641203-B2

Title: Controlled current manipulation for regenerative charging of gate capacitance

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. Non-Provisional application Ser. No. 16/510,210, filed Jul. 12, 2019, which is a continuation of U.S. Non-Provisional application Ser. No. 15/833,857, now U.S. Pat. No. 10,355,688, filed Dec. 6, 2017, all of which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     A synchronous switching power converter (“converter) is an electronic power supply that efficiently converts power with the incorporation of at least one switching element, such as a field effect transistor (FET). A buck converter is an example of a synchronous switching power converter. Modern high-efficiency buck converter designs often use a synchronous FET as a rectifier, in place of a diode, to reduce conduction losses from forward diode voltage drop. To further reduce conduction losses, these FETs are made to be physically large. However, large FETs have significant gate capacitance which is charged and discharged every switching cycle. Significant power can be lost due to this capacitance, a problem which is only compounded by higher switching frequencies. 
     SUMMARY 
     In some embodiments, a circuit for controlled current manipulation for regenerative charging of gate capacitance includes an inductor having a first terminal and a second terminal. The circuit includes a FET that has a gate node which is coupled to the second terminal of the inductor. A bridged inductor driver circuit is coupled to the first terminal of the inductor and the second terminal of the inductor. The bridged inductor driver circuit includes switches. The circuit includes an output control circuit that is coupled to the bridged inductor driver circuit. A sense circuit is coupled to the gate node, and a timing control circuit is coupled to the output control circuit and to the sense circuit. The timing control circuit receives a first FET control signal at a first trigger time of a first switching cycle. The timing control circuit generates first output control signals in accordance with a first switch timing profile. The timing control circuit transmits the first output control signals to the output control circuit. The output control circuit holds one or more of the switches in an ON state for a first time period. The first time period is in accordance with the first switch timing profile. The output control circuit holds all of the switches in an OFF state for a second time period. The second time period is in accordance with the first switch timing profile. The sense circuit samples one or more first voltages of the gate node during the second time period and after the expiration of the first time period. The timing control circuit uses the sampled one or more first voltages to generate a second switch timing profile for a second switching cycle. 
     In some embodiments, a method for regenerative gate charging involves receiving a first FET control signal at a first trigger time of a first switching cycle at a timing control circuit. First output control signals are generated in accordance with a first switch timing profile using the timing control circuit. The first output control signals are transmitted to an output control circuit from the timing control circuit. One or more switches of a bridged inductor driver circuit are held in an ON state for a first time period using the output control circuit. The first time period is in accordance with the first switch timing profile, the bridged inductor driver is coupled to an inductor, and a gate node of a FET is coupled to the inductor. All of the switches are held in an OFF state for a second time period using the output control circuit. The second time period is in accordance with the first switch timing profile. One or more voltages of the gate node are sampled during the second time period and after an expiration of the first time period using a sense circuit. The sense circuit is coupled to the gate node and is coupled to the timing control circuit. A second switch timing profile for a second switching cycle is generated using the sampled one or more voltages at the timing control circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a simplified schematic of an example synchronous switching power converter circuit, in accordance with some embodiments. 
         FIG.  2    is a simplified schematic of an example circuit for regenerative charging of gate capacitance, in accordance with some embodiments. 
         FIG.  3 A  is a simplified signal timing diagram. 
         FIG.  3 B  is a simplified schematic of a portion of an example output control circuit, in accordance with some embodiments. 
         FIG.  3 C  is a simplified signal timing diagram. 
         FIGS.  4 A-B  are simplified signal timing diagrams. 
         FIGS.  5 A-B  are simplified signal timing diagrams. 
         FIG.  6    is a simplified schematic of a portion of an example signal processing circuit, in accordance with some embodiments. 
         FIGS.  7 A-C  are simplified schematics of a portion of an example signal processing circuit, in accordance with some embodiments. 
         FIGS.  8 A-B  are simplified schematics of example bridged inductor driver circuits, in accordance with some embodiments. 
         FIGS.  9 A-B  are simplified schematics of example control circuits, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Improved methods and circuits are described herein for controlled current manipulation for regenerative charging of gate capacitance. Large field effect transistors (e.g., power FETs) such as those used in synchronous switching power converter circuits require significant gate charge that is consumed from the supply rail on every switching cycle. If part of the energy used for charging and discharging the gate is recovered during a switching cycle, energy losses are reduced, and efficiency is improved. As described herein, this energy recovery can be achieved by transferring energy to and from the gate using an inductor. In some embodiments, the inductor and associated control circuitry are implemented in an integrated driver along with the FET as the timing of the control signals for operating the inductor can then be very accurately controlled. The improvement of the timing controls enables the advantage of ensuring optimal charging and discharging of gate capacitance for improved power consumption or minimization of power loss. Additionally, the inductor may be integrated on the same die or in the same package as the FET, which further enhances the advantages enabled by the accurate timing controls for the inductor. Other advantages or improvements of the methods and circuits described herein will also become apparent from the present disclosure. 
     In some embodiments, such methods and circuits involve circuits for charging and discharging a gate of a FET by controlling the current flow through an inductor coupled to the gate of the FET such that power loss is reduced. Such circuits accept input from a switched-mode controller and switch the FET on and off as determined by a desired duty cycle of the switching power converter. Current flow through the inductor and to the gate of the FET is controlled by a switch timing profile that has static and tunable delay portions. The tunable delay portions of the switch timing profile are adjusted to further reduce power loss in subsequent switching cycles by sampling the gate voltage of the FET at a known time in a charge or discharge cycle of the gate of the FET. The sampled gate voltages are compared to desired voltages as a form of feedback regarding the previous gate charge or discharge cycle. Based on that feedback, the adjustable delay portions of the switch timing profile are tuned (e.g., a delay duration is lengthened or shortened) to modify current flow through the inductor during a subsequent gate charge or discharge cycle. 
       FIG.  1    is a simplified schematic of an example synchronous switching power converter (“converter”) circuit  100  that converts an input voltage V IN  at a V IN  node to an output voltage V OUT  at a V OUT  node, in accordance with some embodiments. In general, the converter circuit  100  includes a control circuit  104  that is coupled to a high-side field effect transistor (FET)  106  through a high-side drive circuit  108 . The control circuit  104  is also coupled to a low-side FET  110  through a low-side drive circuit  112 . A high-side source node of the high-side FET  106  and a low-side drain node of the low-side FET  110  are electrically coupled to the phase node  114 , which is electrically coupled to a capacitor  116  through an inductor  118 . A phase signal PH is a static or continuously changing voltage at the phase node  114 . The control circuit  104  is electrically coupled to the phase node  114  to receive the phase signal PH. A load, such as a load  120 , is typically electrically coupled in parallel with the capacitor  116 . In some embodiments, the control circuit  104  is electrically coupled to the V OUT  node (e.g., through a feedback path to receive V OUT ). The control circuit  104  receives V OUT  and the phase signal PH and may receive other signals which are not shown here for simplicity. The control circuit  104  outputs a signal H ON  and a signal L ON . The high-side drive circuit  108  receives the H ON  signal. The high-side drive circuit  108  buffers, amplifies, level-shifts, or otherwise conditions the signal H ON  to produce a signal H DRV  that is suitable for turning the high-side FET  106  on and off. The signal H DRV  is received at a high-side gate node of the high-side FET  106 . Similarly, the low-side drive circuit  112  receives the signal L ON . The low-side drive circuit  112  buffers, amplifies, level-shifts, or otherwise conditions the signal L ON  to produce a signal L DRV  that is suitable for turning the low-side FET  110  on and off. The signal L DRV  is received at a gate node of the low-side FET  110 . In some embodiments, the low-side drive circuit  112  receives external control signals from the control circuit  104 . 
       FIG.  2    is a simplified schematic of an example low-side drive circuit  112  for regenerative charging of gate capacitance of the low-side FET  110 . The portion of the low-side drive circuit  112  shown includes a timing control circuit  208  that receives the L ON  signal and triggers a series of events, timed by timer circuits  214   1-N . The timer circuits  214   1-N  include static delay circuits and adjustable delay circuits to provide static delays, as well as to provide variable (e.g., tunable) delays which are controlled by a configuration provided by the timing control circuit  208 . The low-side drive circuit  112  also includes a control loop that adjusts the variable delays based on feedback from previous gate charge/discharge cycles. The initial state of the low-side drive circuit  112  is set, in some embodiments, by a digital configuration circuit  210 , which sources configuration data signals Cfg 1-3  either from a non-volatile source, or an external supervising controller. The timing control circuit  208  outputs a sequence of timed pulses to an output control circuit  204  which contains combinational logic that converts the timed pulses into gate waveforms, and buffers these signals to control current flow through an inductor L 1  that is coupled to the gate of the low-side FET  110  to charge or discharge the gate of the low-side FET  110 . After the gate of the low-side FET  110  has finished charging or discharging, but the corresponding hold switch (or current source) is not enabled, a signal processing circuit  206  samples the gate voltage of the low-side FET  110  to generate the feedback to the timer control circuit  208  about the performance of the previous cycle. 
     As shown, the low-side drive circuit  112  generally includes the inductor L 1  coupled to the gate node of the low-side FET  110 . A bridged inductor driver circuit  202  is coupled to the inductor L 1  and to the output control circuit  204 . The signal processing circuit  206  is coupled to the gate node of the low-side FET  110 . The timing control circuit  208  is coupled to the timer circuits  214   1-N , to the output control circuit  204 , to the signal processing circuit  206 , and to the digital configuration circuit  210 . The digital configuration circuit  210  includes a non-volatile memory (NVM) circuit  212 . 
     In the example embodiment shown, the bridged inductor driver circuit  202  includes switches S 1-4 . Other embodiments of the bridged inductor driver circuit  202  are shown and discussed with reference to  FIGS.  8 A- 9 B . The timing control circuit  208  receives the signal L ON  from the control circuit  104  and based on that signal turns the low-side FET  110  on or off by charging the gate of the low-side FET  110  up to Vdd or discharging the gate of the low-side FET  110  down to Vss. To turn the low-side FET  110  on or off, the timing control circuit  208 , triggered by the signal L ON , generates output control signals (“Output Ctrl”) and transmits the Output Ctrl signals to the output control circuit  204 . The output control circuit  204  uses the Output Ctrl signals to control the bridged inductor driver circuit  202  to cause current to flow to and from the inductor L 1  and the gate node of the low-side FET  110 . In the example shown, the flow of current is caused by turning one or more of the switches S 1-4  on or off for a duration of time. In some embodiments, one or more of the switches S 1-4  is a FET. In other embodiments, one or more of the switches S 1-4  is a controlled current source or a diode. 
     The Output Ctrl signals sent to the output control circuit  204  are generated by the timing control circuit  208  in accordance with a switch timing profile. A switch timing profile is a timing sequence that defines or controls the flow of current to and from the inductor L 1  and the gate node of the low-side FET  110 . Example timing sequences are shown and discussed with reference to  FIGS.  4 A- 5 B . In some embodiments, switch timing profiles are stored in, and retrieved from, the digital configuration circuit  210  (e.g., using the NVM circuit  212 ). A default switch timing profile may be used while the converter circuit  100  reaches a steady state of operation on power-up or after reset. 
     During specific times during a switching cycle, measurements of the voltage and/or current related to the low-side FET  110  are made by the signal processing circuit  206 . A switching cycle is a duration of time in which both FETs  106 ,  110  have transitioned through full on and off states (e.g., the sequence of turning low-side FET  110  off . . . high-side FET  106  on . . . high-side FET  106  off . . . low-side FET  110  on . . . low-side FET  110  off . . . and so on). In the example shown the voltage V G  of the gate node of the low-side FET  110  is measured by the signal processing circuit  206 , but in other embodiments, other currents/voltages related to the low-side FET  110  are measured as well. These example embodiments are shown and discussed with reference to  FIGS.  7 A-C . Based on measurements made during the current switching cycle, the switch timing profile used in a subsequent switching cycle is created or updated (e.g., tuned). When the timing control circuit  208  receives a second FET control signal at a second trigger time of a subsequent switching cycle, the timing control circuit  208  generates output control signals in accordance with the updated or generated switch timing profile (based on measured gate voltages from the previous cycle) and transmits updated output control signals to the output control circuit  204 . The created or updated switch timing profile can be stored by the digital configuration circuit  210  (e.g., by transmitting configuration signals Cfg 4  from the timing control circuit  208  to the digital configuration circuit  210 ) and be recalled by the digital configuration circuit  210  for later use. An example embodiment of a portion of the signal processing circuit  206  is shown and discussed with reference to  FIG.  6   . 
     Upon, or before, receiving the FET control signal L ON  during a switching cycle (or upon or before the commencement of that switching cycle), the timing control circuit  208  configures the timer circuits  214   1-N  using respective control signals Ctrl 1-N  in accordance with a switch timing profile associated with that switching cycle. The switch timing profile used to configure the timer circuits  214   1-N  is either generated/updated in a previous switching cycle or is retrieved (e.g., from the NVM circuit  212 ) by the digital configuration circuit  210 . 
     In accordance with the switch timing profile, each of the timer circuits  214   1-N  is configured to apply an amount of static and/or adjustable delay to received trigger signals Trig 1-N  to produce delayed signals T 1-N . In some embodiments, each of the trigger signals Trig 1-N  corresponds to the signal L ON . The Output Ctrl signals transmitted from the timing control circuit  208  to the output control circuit  204  include the delayed signals T 1-N . An example simplified signal timing diagram  300  in  FIG.  3 A  shows the delayed signal T N  generated by the timer circuit  214   N  as it relates to the trigger signal Trig N  received by the timer circuit  214   N . After a first untriggered duration of time (“Untriggered 1 ”), a rising edge  302  of a trigger signal Trig N  (e.g., Trig 3 ) is sent from the timing control circuit  208  to the timer circuit  214   N . After a first static delay duration (“Static Delay 1 ”) and a first tunable delay duration (“Tunable Delay 1 ”), a delayed rising edge  304  of delayed signal T N  (e.g., T 3 ) is transmitted from the timer circuit  214   N  to the timing control circuit  208 . After a second untriggered duration of time (“Untriggered 2 ”), a falling edge  306  of the trigger signal Trig N  is transmitted from the timing control circuit  208  to the timer circuit  214   N . After a second static delay duration (“Static Delay 2 ”) and a second tunable delay duration (“Tunable Delay 2 ”), a delayed falling edge  308  of T N  is transmitted from the timer circuit  214   N  to the timing control circuit  208 . The timer circuit  214   N  remains untriggered for a second duration of time (“Untriggered 2 ”). 
     The timing control circuit  208  transmits T N , as well as other delayed signals (e.g., T 1 , T 2 ) to the output control circuit  204  as part of the Output Ctrl signals. The output control circuit  204  uses the received Output Ctrl signals to generate signals that control the bridged inductor driver circuit  202 , thereby controlling the flow of current through the inductor L 1  and to/from the gate node of the low-side FET  110 . A portion of an example embodiment of the output control circuit  204  is shown in  FIG.  3 B . 
     The portion of the circuit shown in  FIG.  3 B  illustrates the logical relationship between inputs and outputs of the output control circuit  204 . The output control circuit  204  converts delayed signals T 1-3  received by the output control circuit  204  into signals S 1-4  Out. Logic gates G 1-12 , coupled as shown, use delayed signals T 1-3  and the trigger signal L ON  to produce switch control signals S 1-4  Out. The switch control signals S 1-4  Out are used to control the bridged inductor driver circuit  202 . In some embodiments, the signals S 1-4  Out are buffered, level-shifted, amplified, or otherwise modified to control the bridged inductor driver circuit  202 . In some embodiments, one or more of the switch control signals S 1-4  Out control a controllable current supply circuit. Details of the logical relationship of L ON  and T 1-3  to S 1-4  Out, given the example embodiment of the output control circuit  204  shown in  FIG.  3 B , are shown in the simplified signal diagram  350  of  FIG.  3 C . 
     A simplified signal timing diagram  400  of an example 3-stage timing sequence for charging the gate node of the low-side FET  110  (e.g., turning the low-side FET  110  on) is shown in  FIG.  4 A . Based on the currently used timing profile of the current switching cycle, the timer circuits  214   1-N  shown in  FIG.  2    are configured to produced delayed signals T 1-3  which are received by the output control circuit  204  to generate switch control signals S 1-4  Out. During a pre-trigger stage, while L ON  is de-asserted (e.g., the low-side FET  110  is off), signal S 1  Out is asserted, and signals S 2-4  Out are de-asserted, thus holding the gate node of the low-side FET  110  at Vss. During the pre-trigger stage, the magnitude of current I L  through the inductor L 1  is zero. After the pre-trigger stage, a rising edge  402  of L ON  is received at the timing control circuit  208  from the control circuit  104  which triggers subsequent transitions of signals S 1-4  Out. The falling edge  404  of signal S 1  Out and the rising edge  406  of signal S 2  Out cause a rising magnitude of current I L  to flow into the inductor L 1  from Vdd. After a duration of time that includes both static and tunable delays (e.g., the static delay 1  and tunable delay 1  stages of  FIG.  3 A ), the falling edge  408  of S 2  Out and the rising edge  410  of S 3  Out cause current sourced from Vdd and the inductor L 1  to charge the low-side gate of the low-side FET  110 . As the gate voltage V G  rises, the magnitude of current I L  falls. After another duration of time that includes both static and tunable delays (e.g., the static delay 2  and tunable delay 2  stages of  FIG.  3 A ), the falling edge  412  of S 3  Out and the rising edge  414  of S 4  Out cause the low-side gate of the low-side FET  110  to be held at V dd  (designated as the “Holding” stage). As shown, the signal processing circuit  206  only samples the gate voltage V G  during the duration of time between the falling edge  412  and the rising edge  414  (designated as the “Sampling” stage). This sampled voltage is used as an input to the control loop (e.g., a “loop” formed as the effects of Output Ctrl on the gate voltage V G  measured by the signal processing circuit  206  at specific times, the sampled voltages being fed back to the timing control circuit  208  to generate new Output Ctrl signals, and so on). The control loop adjusts switch timing profiles used during future cycles (e.g., tuning the tunable delay portions for use in a subsequent switching cycle). During this duration of time, current is not being provided to the gate node of the low-side FET  110  from Vdd and current from the gate node is not being sourced to Vss (e.g., all the switches or current sources of the bridged inductor driver circuit  202  are off). Because the gate voltage V G  is only sampled during this duration of time, the signal processing circuit  206  can be advantageously simplified. 
     A simplified signal timing diagram  450  of an example 4-stage timing sequence for charging the gate node of the low-side FET  110  (e.g., turning the low-side FET  110  on) is shown in  FIG.  4 B . The 4-stage timing sequence adds a pre-charge stage to the 3-stage timing sequence discussed with reference to  FIG.  4 A . During a pre-trigger stage while L ON  is de-asserted, signal S 1  Out is asserted, and signals S 2-4  Out are de-asserted, thus holding the gate node of the low-side FET  110  at Vss. During the pre-trigger stage, the magnitude of current I L  through the inductor L 1  is zero. After the pre-trigger stage, a rising edge  452  of L ON  is received at the timing control circuit  208  from the control circuit  104 , the reception of which triggers subsequent transitions of signals S 1-4  Out. A rising edge  454  of S 2  Out causes a rising magnitude of current I L  to flow through the inductor L 1  from Vdd to Vss. A falling edge  456  of signal S 1  Out causes the current I L  to cease flowing to Vss and instead begin charging the gate node of the low-side FET  110 . This causes a rising gate voltage V G . After a duration of time that includes both static and tunable delays, a falling edge  458  of signal S 2  Out and a rising edge  460  of signal S 3  Out stops the flow of current from Vdd to the inductor L 1 . Current I L  from the inductor L 1  continues to flow to the gate node of the low-side FET  110 . This causes the gate voltage V G  of the FET  110  to continue rising while the magnitude of the current I L  falls. After another duration of time that includes both static and tunable delays, the falling edge  462  of S 3  Out and the rising edge  464  of S 4  Out cause the low-side gate of the low-side FET  110  to be held at V dd  (designated as the “Holding” stage). As shown, the signal processing circuit  206  only samples the gate voltage V G  during the duration of time between the falling edge  462  and the rising edge  464  (designated as the “Sampling” stage). This sampled voltage is used as an input to the control loop for adjusting future cycles. During this duration of time, current is not being provided to the gate node of the low-side FET  110  from Vdd and current from the gate node is not being sourced to Vss. 
     A simplified signal timing diagram  500  of an example 3-stage timing sequence for discharging the gate node of the low-side FET  110  (e.g., turning the low-side FET  110  off) is shown in  FIG.  5 A . Based on the currently used timing profile of the current switching cycle, the timer circuits  214   1-N  shown in  FIG.  2    are configured to produced delayed signals T 1-3  which are received by the output control circuit  204  to generate switch control signals S 1-4  Out. During a pre-trigger stage while L ON  is asserted (e.g., the low-side FET  110  is on), signal S 4  Out is asserted, and signals S 1-3  Out are de-asserted, thus holding the gate node of the low-side FET  110  at Vdd. During the pre-trigger stage, the magnitude of current I L  through the inductor L 1  is zero. After the pre-trigger stage, a falling edge  502  of L ON  is received at the timing control circuit  208  from the control circuit  104 , the reception of which triggers subsequent transitions of signals S 1-4  Out. The rising edge  504  of signal S 3  Out and the falling edge  506  of signal S 4  Out cause a rising magnitude (e.g., away from the steady-state of zero current) of current I L  to flow into the inductor L 1  from the gate node of the low-side FET  110 , thereby causing the gate voltage V G  to decrease. After a duration of time that includes both static and tunable delays (e.g., the static delay 1  and tunable delay 1  stages of  FIG.  3 A ), a rising edge  508  of S 2  Out and a falling edge  510  of S 3  Out causes current to flow through the inductor L 1  to Vdd. As the gate voltage V G  continues to decrease, the magnitude of current I L  falls (e.g., returning to a steady state of zero). After another duration of time that includes both static and tunable delays (e.g., the static delay 2  and tunable delay 2  stages of  FIG.  3 A ), the falling edge  512  of S 2  Out and the rising edge  514  of S 1  Out cause the low-side gate of the low-side FET  110  to be held at Vss (designated as the “Holding” stage). As shown, the signal processing circuit  206  only samples the gate voltage V G  during the duration of time between the falling edge  512  and the rising edge  514  (designated as the “Sampling” stage). This sampled voltage is used as an input to the control loop for adjusting future cycles. During this duration of time, current from the gate node is not being sourced to Vss (e.g., all the switches or current sources of the bridged inductor driver circuit  202  are off). Because the gate voltage V G  is only sampled during this duration of time, the signal processing circuit  206  can be advantageously simplified. 
     A simplified signal timing diagram  550  of an example 4-stage timing sequence for discharging the gate node of the low-side FET  110  (e.g., turning the low-side FET  110  off) is shown in  FIG.  5 B . The 4-stage timing sequence adds a Pre-charge stage to the 3-stage timing sequence discussed with reference to  FIG.  5 A . During a pre-trigger stage while L ON  is asserted, signal S 4  Out is asserted, and signals S 1-3  Out are de-asserted, thus holding the gate node of the low-side FET  110  at Vdd. During the pre-trigger stage, the magnitude of current I L  through the inductor L 1  is zero. After the pre-trigger stage, a falling edge  552  of L ON  is received at the timing control circuit  208  from the control circuit  104 , the reception of which triggers subsequent transitions of signals S 1-4  Out. A rising edge  554  of S 3  Out causes a rising magnitude (e.g., away from the steady-state of zero current) of current I L  to flow through the inductor L 1  from Vdd to Vss. A falling edge  556  of signal S 4  Out causes the current I L  to cease flowing to Vdd and continue flowing from the gate node of the low-side FET  110  to Vss. This causes a decreasing gate voltage V G . After a duration of time that includes both static and tunable delays, a rising edge  558  of signal S 2  Out and a falling edge  560  of signal S 3  Out causes causes current to flow through the inductor L 1  to Vdd. This causes the gate voltage V G  of the FET  110  to continue falling while the magnitude of the current I L  also falls (e.g., approaches the steady-state of zero current). After another duration of time that includes both static and tunable delays, the falling edge  562  of S 2  Out and the rising edge  564  of S 1  Out cause the low-side gate of the low-side FET  110  to be held at Vss (designated as the “Holding” stage). As shown, the signal processing circuit  206  only samples the gate voltage V G  during the duration of time between the falling edge  562  of S 2  Out and the rising edge  564  of S 1  Out (designated as the “Sampling” stage). This sampled voltage is used as an input to the control loop for adjusting future cycles. During this duration of time, current from the gate node is not being sourced to Vss (e.g., all the switches or current sources of the bridged inductor driver circuit  202  are off). Because the gate voltage V G  is only sampled during this duration of time, the signal processing circuit  206  can be advantageously simplified. 
     A circuit schematic of an example embodiment of a portion of the signal processing circuit  206  is shown in  FIG.  6   . Other embodiments of a signal processing circuit for sampling a gate voltage of a FET as are known in the art could be used in some embodiments. In some embodiments, the signal processing circuit  206  includes a digital-to-analog converter instead of, or in addition to, high-speed latching comparators. In the example embodiment shown, the signal processing circuit  206  generally includes a first high-speed latching comparator  602  and a second high-speed latching comparator  604  coupled as shown in  FIG.  6   . The first comparator  602  receives the gate voltage V G  from the gate node of the low-side FET  110  at a non-inverting input and receives Vdd at an inverting input to compare the gate voltage Vg to the rail-voltage Vdd. The second comparator  604  receives the gate voltage V G  from the gate node of the low-side FET  110  at an inverting input and receives Vss at a non-inverting input to compare the gate voltage Vg to the rail-voltage Vss. Outputs of the comparators  602 ,  604  (Vdd Feedback and Vss Feedback, respectively) are transmitted to the timing control circuit  208  as part of the “Smp” signals shown in  FIG.  2   . Additionally, the comparators  602 ,  604  can receive trigger signals (not shown) and/or reset signals from the timing control circuit  208  as part of the “Trig” signals shown in  FIG.  2    to control the reset and subsequent sample latching of the comparators  602 ,  604 . As was discussed with reference to  FIGS.  4 A- 5 B , the signal processing circuit  206  advantageously samples the gate voltage only during select times of the switching cycle. 
     In some embodiments, other voltages and currents related to the low-side FET  110  are measured in addition to the gate voltage V G . Example embodiments of a portion of the signal processing section of the low-side drive circuit  112  are shown in  FIGS.  7 A-C . Each of the signal processing sections  700 ,  720  and  750  are coupled to the low-side FET  110  and generally include a respective signal processing circuit  706 ,  726 ,  756  which is similar to the signal processing circuit  206 . Samples produced by the signal processing circuits  706 ,  726 ,  756  are transmitted to the timing control circuit  208  as part of the Smp signals shown in  FIG.  2   . Additionally, trigger signals are transmitted from the timing control circuit  208  to a respective signal processing circuit  706 ,  726 ,  756  as part of the Trig signals shown in  FIG.  2   . Configuration signals Cfg 3  are received the signal processing circuits  706 ,  726 ,  756  from the digital configuration circuit  210 . As shown in  FIG.  7 A , in some embodiments, a gate current I G  and the gate voltage V G  of the gate node of the low-side FET are sampled by the signal processing circuit  706  for zero-current-switching. As shown in  FIG.  7 B , in some embodiments, the gate voltage V G  of the gate node and a drain current I D  of a low-side drain node of the low-side FET are sampled by the signal processing circuit  726  for zero-current-switching. As shown in  FIG.  7 C , in some embodiments, the gate voltage V G  of the gate node and a drain voltage V D  of the low-side drain node of the low-side FET are sampled by the signal processing circuit  756  for zero-voltage-switching. 
     Other example embodiments of the bridged inductor driver circuit  202  of  FIG.  2    are shown in  FIGS.  8 A-B . As shown in the simplified circuit schematic of  FIG.  8 A , one or more of the switches S 1-4  shown in  FIG.  2    are replaced, in some embodiments, by a controllable current source I 1-4  to control the flow of current through the inductor L 1 . As shown in the simplified circuit schematic of  FIG.  8 B , the switch S 3  shown in  FIG.  2    is replaced, in some embodiments, by a diode D 1 . 
     The inductance of the inductor L 1  and bridged inductor driver circuits may be distributed amongst a distributed power FET, in accordance with some embodiments. As shown in the simplified circuit schematics of  FIGS.  9 A-B , in some embodiments, the low-side FET  110  includes N fingers  910   1-N . In such embodiments, the inductance of the inductor L 1  is distributed across the N fingers  910   1-N  as inductors L 1   1-N . Similarly, the bridged inductor driver circuit  202  is distributed across the N fingers as bridged inductor driver circuits  902   1-N , the distributed bridged inductor driver circuits  902   1-N  having, in some embodiments, switches S 1   1-N , S 2   1-N , S 3   1-N , and S 4   1-N . In some embodiments, as shown in the simplified circuit schematic  900  of  FIG.  9 A , the output control circuit  204  is also distributed across the N fingers as output control circuits  904   1-N . As shown in the simplified circuit schematic  950  of  FIG.  9 B , in some embodiments, a single output control circuit  954  is coupled to each of the distributed bridged inductor driver circuits  902   1-N . 
     In some embodiments, the high-side drive circuit  108  is similar to the low-side drive circuit  112  and is used for regenerative charging of gate capacitance of the high-side FET  106 . In some embodiments, the static delay portions are set at design time and are dependent on the specific switch and inductor sizes used. In some embodiments, a monolithic integration of the low-side FET  110 , the bridged inductor driver circuit  202  and the circuitry of the low-side drive circuit  112  occur on a mixed signal LDMOS process node. In some embodiments, the low-side FET  110  is a large NMOS device. In some embodiments, all or a portion of the low-side drive circuit  112  includes analog circuits rather than digital circuits. In some embodiments, a single inductor is shared amongst many power FETs (e.g., a single inductor L 1  coupled to respective gate nodes of multiple FETs), such as in a multi-phase design. In some embodiments, the inductor L 1  is constructed with bond wires on top of a chip that includes the low-side drive circuit  112 . In some embodiments, the inductor L 1  is constructed as a traditional planar spiral inductor. In some embodiments, the inductor L 1  is constructed using metal layers or a redistribution layer (RDL). In some embodiments, the inductor L 1  is external to a chip that includes the low-side drive circuit  112  or forms a part of a multi-component hybrid. In some embodiments, the inductor L 1  is constructed using bond-wires that terminate off a chip that includes the low-side drive circuit  112  such that a spiral is formed away from the chip itself. Any other suitable form of on-chip or off-chip inductor as known to one of skill in the art may be used as the inductor L 1 . 
     For ease of description, example embodiments described herein relate to the low-side FET  110 . One of ordinary skill in the art will understand that the same or similar methods and circuits can be used to drive the high-side FET  106  or another FET entirely. In some embodiments, the FET controlled by gate driver circuits described herein is an NMOS or PMOS device. In some embodiments, the low-side drive circuit  112  is only used for charging the gate of the low-side FET  110 . In some embodiments, the low-side drive circuit  112  is only used for discharging the low-side FET  110 . In some embodiments, regenerative gate charging and discharging is not used during each switching cycle but is still used during some switching cycles. In some embodiments, regenerative gate charging and discharging is used during each switching cycle. In some embodiments, the signal processing circuit  206  continuously samples the gate voltage V G . In some embodiments, the signal processing circuit  206  uses a Digital-to-Analog Converter instead of a comparator. In some embodiments, the signal processing circuit  206  uses an attained peak gate voltage rather than the final resting voltage for feedback. In some embodiments, analog components of the circuits described herein are replaced with digital inputs. In some embodiments, the Vdd and Vss supplies are separated from the low-voltage system rails, and may dynamically change over operating conditions. In some embodiments, tunable delay timings are controlled by an external system controller. In some embodiments, the configuration is provided by on-chip NVM, from an external source, or from a PWM signal. In some embodiments, the circuits and methods described herein are recursively applied to the switches of the bridged inductor driver circuit  202 . 
     Reference has been made in detail to embodiments of the disclosed invention, one or more examples of which have been illustrated in the accompanying figures. Each example has been provided by way of explanation of the present technology, not as a limitation of the present technology. In fact, while the specification has been described in detail with respect to specific embodiments of the invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. For instance, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present subject matter covers all such modifications and variations within the scope of the appended claims and their equivalents. These and other modifications and variations to the present invention may be practiced by those of ordinary skill in the art, without departing from the scope of the present invention, which is more particularly set forth in the appended claims. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the invention.