Patent Publication Number: US-2006001447-A1

Title: Level shifting circuit between isolated systems

Description:
This invention relates to the field of electronics, and in particular to a level-shifting circuit that provides an interface between and among two or more isolated systems.  
      Isolated systems are commonly used for improved fault tolerance in bus systems and networks, wherein a fault in one system, such as a voltage shorted to ground, does not necessarily cause a fault in the other, isolated, system. Automotive networks, for example, commonly provide isolated systems for safety equipment, such as airbag deployment systems.  
       FIG. 1  illustrates a conventional level shifting circuit  10  that couples an input signal Iin of a first system (not shown) to a pair of voltage outputs Vout 1  and Vout 2  of a second system (also not shown). The first and second systems are isolated, in that they each have independent ground systems. The first system has a ground reference of Vgnd 1 , and the second system has a ground reference of Vgnd 2 , which may differ from Vgnd 1 . Such a circuit  10  is disclosed in U.S. Pat. No. 6,154,061, “CAN BUS DRIVER WITH SYMMETRICAL DIFFERENTIAL OUTPUT SIGNALS”, issued on 28 Nov. 2000 to Hendrik Boezen, Martinus Bredius, Aloysius J. M. Boomkamp, Cecilius G. Kwakemaat, and Abraham K. Van Den Heuvel, and in U.S. Pat. No. 6,452,418 “LEVEL SHIFTER WITH INDEPENDENT GROUNDS AND IMPROVED EME-ISOLATION”, issued 17 Sep. 2002 to Balwinder Singh, Klaas-Jan De Langen, and Martijn Bredius, both of which patents are incorporated by reference herein.  
      In a non-fault mode, both ground references Vgnd 1  and Vgnd 2  are nominally at the same potential. In this non-fault mode, Vdd 1  will be substantially greater than Vgnd 2 , and Vdd 2  will be substantially greater than Vgnd 1 , and therefore diodes D 1  and D 2  will be forward biased and allow conduction. The input current Iin is mirrored by both current mirrors M 1 , M 2  and M 3 , M 4 , to produce output currents Iout 1  and Iout 2 , respectively, because both diodes D 1  and D 2  are conducting. Nominally, Iout 1  will equal Iout 2 , assuming that both current mirrors match well, and therefore there is no overall current flow between the isolated systems. Note, however, that N-channel devices are used in current-mirror M 1 , M 2  and P-channel devices are used in current mirror M 3 , M 4 , which complicates the task of matching the high-frequency response of the current mirrors over a range of temperature and process variations. When current flows between the grounds of two systems, electromagnetic emissions from the systems increase.  
      If a fault causes the ground potentials Vgnd 1  and Vgnd 2  to differ, one of two possibilities occur. If Vgnd 1  approaches or exceeds Vdd 2 , diode D 1  enters a non-conductive state and blocks Iout 1 ; or, if Vgnd 2  approaches or exceeds Vdd 1 , diode D 2  enters a non-conductive state and blocks Iout 2 . In either state, at least one of the currents Iout 1  or Iout 2  flows, so that the input signal Iin is coupled to either Vout 1  or Vout 2 .  
      Because the input signal Iin may be coupled to either Vout 1  or Vout 2  or both, depending upon whether a fault occurs, and the particular effects of such a fault, a combining circuit (not shown) is required to determine a single-output, or differential-output, corresponding to the input Iin, for coupling to subsequent circuitry in the isolated system. The combining of these signals Vout 1 , Vout 2  to produce a common output corresponding to the input current Iin is particularly difficult if the input and output signals are analog signals.  
      It is an object of this invention to provide a level shifting circuit for use between isolated systems that produces a single output voltage at one of the isolated systems corresponding to an input current at the other isolated system. It is a further object of this invention to provide a level shifting circuit for use between isolated systems that couples an input current of one system to an output voltage of the other system that facilitates the minimization of current flow between the two systems.  
      These objects and others are achieved by a level shifting circuit for coupling an input current from one system to another, isolated, system, that drives a single load via one or more current mirrors of a common type. In a first embodiment, two similar type (either N-type or P-type) current mirrors provide output current to a common load. Diodes are used to split the input current between the two current mirrors during normal, non-faulty conditions, and to turn off either one of the two current mirrors during a fault condition to permit proper operation in the presence of a fault. In a second embodiment, a single current mirror mirrors the input current to the output load and a pair of diodes selects which of the isolated systems to use as the power source in the event of a fault. A variety of techniques are presented for minimizing the current flow between the two systems, to thereby minimize electromagnetic emissions (ME) from the level shifting circuit. 
    
    
       FIG. 1  illustrates an example circuit diagram of a prior art level shifting circuit for coupling signals between two isolated systems.  
       FIG. 2  illustrates an example circuit diagram of a level shifting circuit for coupling signals between two isolated systems.  
       FIGS. 3A and 3B  each illustrates an example circuit diagram of another level shifting circuit for coupling signals between two isolated systems.  
       FIG. 4  illustrates an example circuit diagram of a level shifting circuit for coupling signals between and among multiple isolated systems.  
       FIG. 5  illustrates an example circuit diagram of a level shifting circuit that is particularly well suited for coupling an analog signal between two isolated systems.  
       FIG. 6  illustrates an example circuit diagram of a level shifting circuit that is particularly well suited for coupling a digital signal between two isolated systems.  
       FIG. 7  illustrates an example block diagram of a compensated isolated level shifting circuit for coupling signals between two isolated systems.  
       FIG. 8  illustrates an example circuit diagram of a compensated level shifting circuit for coupling signals between two isolated systems.  
       FIG. 9  illustrates an example circuit diagram of a differential compensated level shifting circuit for coupling signals between two isolated systems.  
       FIG. 10  illustrates an example circuit diagram of a compensated level shifting circuit that is particularly well suited for coupling analog signals between isolated systems.  
       FIG. 11  illustrates an example circuit diagram of an alternative compensating level shifting circuit for coupling signals between two isolated systems.  
       FIG. 12  illustrates an example implementation of a level shifting circuit for coupling signals between two isolated systems.  
       FIG. 13  illustrates an example block diagram of a level shifting system for coupling multiple signals between two isolated systems.  
       FIG. 14  illustrates an example circuit diagram of a power supply, with compensation, for use in a level shifting system.  
       FIG. 15  illustrates an example circuit diagram of a level shifting circuit for use in a level shifting system.  
       FIG. 16  illustrates an example block diagram of another compensated level shifting circuit.  
       FIG. 17  illustrates an example embodiment of a compensated level shifting circuit. 
    
    
       FIG. 2  illustrates an example circuit diagram of a level shifting circuit  20  for coupling signals between two isolated systems. The input system includes voltage references Vdd 1  and Vgnd 1 , and the output system includes voltage references Vdd 2  and Vgnd 2 .  
      In the normal, non-faulty operation of circuit  20 , the input current Iin is split into two currents Iin 1  and Iin 2 , each providing the input current to a corresponding current mirror M 1 , M 2  and M 3 , M 4 , respectively. Each of these current mirrors M 1 , M 2 , and M 3 , M 4  comprise P-type devices, and each provides current Iout 1 , Iout 2 , respectively, to a common load L, to produce a voltage output Vout relative to the second ground potential Vgnd 2 . If the current mirrors M 1 , M 2  and M 3 , M 4  are well matched, there is no net current flow between the systems. Because both current mirrors M 1 , M 2 , and M 3 , M 4  are of the same type, current matching can be more easily achieved over a wide range of temperature, compared to the circuit  10  in  FIG. 1 .  
      If, due to a fault, Vgnd 1  rises and approaches or exceeds Vdd 2 , diode D 2  turns off and decouples current mirror M 3 , M 4  from the input. The full input current Iin is then mirrored by current mirror M 1 , M 2  to the load L. If, due to a fault, Vgnd 2  rises and approaches or exceeds Vdd 1 , diode D 1  turns off and decouples mirror M 1 , M 2  from the input. The full current Iin is then mirrored by current mirror M 3 , M 4  to the load L.  
      A complementary circuit configuration to that of  FIG. 2 , using N-channel current mirrors, and with the current source Iin and the load L in series between the reference voltages Vdd 1  and Vdd 2  and the current mirrors, can be provided as well.  
       FIGS. 3A and 3B  each illustrates an example circuit diagram of another level shifting circuit  30   a ,  30   b  for coupling signals between two isolated systems. Circuit  30   a  illustrates a level shifter that uses P-channel devices, and circuit  30   b  illustrates its complementary circuit, which uses N-channel devices.  
      Each circuit  30   a ,  30   b  uses a single current mirror M 1 , M 2  to mirror the input current Iin to the output load L. Each circuit  30   a ,  30   b  uses a pair of diodes D 1 , D 2  to select which system supplies the current Iout. In circuit  30   a , Vmax is the higher of Vdd 1  and Vdd 2 ; in circuit  30   b , Vmin is the lower of Vgnd 1  and Vgnd 2 . In this manner, the current Iout is provided regardless of the voltage difference between the two isolated systems. Preferably, and particularly for analog signal coupling, the choice of using circuit  30   a ,  30   b  is made so as to minimize the switching of the diodes, based on the expected voltage differences between the isolated systems during normal, non-faulty, operation. If it is common, for example, that one of the reference voltages Vdd 1 , Vdd 2  is consistently larger than the other, while the ground potentials Vgnd 1 , Vgnd 2  are approximately equal, the circuit of  30   a  would be preferred, because the diode D 1 , D 2  at the consistently higher voltage Vdd 1 , Vdd 2  would be consistently turned on. Alternatively, if one of the grounds Vgnd 1 , Vgnd 2  consistently floats at a higher potential than the other, the circuit of  30   b  would be preferred, because the diode D 1 , D 2  at the lower voltage Vgnd 1 , Vgnd 2  would be consistently turned on. If the relative voltages are unpredictable, the circuit  30   b  would generally be preferred, for the inherently faster switching characteristics of N-type devices. Other characteristics of these circuits may suggest a preference of one over the other, as well.  
       FIG. 4  illustrates an example circuit diagram of a level shifting circuit  40  for coupling signals between and among three multiple isolated systems. Reference voltage pairs Vdd 1 -Vgnd 1 , Vdd 2 -Vgnd 2 , and Vdd 3 -Vgnd 3  each form one of the three isolated voltage systems. This circuit is illustrated using P-channel devices; its complement, using N-channel devices, may also be used. The principles of this circuit  40  may be extended to any number of multiple isolated systems.  
      The diode arrangement D 1 , D 2 , D 3  selects the highest voltage Vmax from among the isolated reference voltages Vdd 1 , Vdd 2 , Vdd 3 . This voltage Vmax provides the output current to each of the loads L 1 , L 2   a , L 2   b , and L 3 , via the current mirrors M 1 , M 2 ; M 3 , M 4 ; M 3 , M 5 ; and M 6 , M 7 , respectively. Preferably, one of the reference voltages Vdd 1 , Vdd 2 , Vdd 3  is biased relative to the other two so that the corresponding diode D 1 , D 2 , D 3 , respectively, is continuously on, to avoid diode switching during normal, non-faulty, operation.  
      Current inputs Iin 1  and Iin 2  and load L 3  are illustrated as being referenced to the first isolated ground Vgnd 1 ; loads L 1  and L 2   a  are illustrated as being referenced to the second isolated ground Vgnd 2 ; and current input Iin 3  and load L 2   b  are illustrated as being reference to the third isolated ground Vgnd 3 .  
      The current input Iin 1  relative to Vgnd 1  is mirrored by current mirror M 1 , M 2  to produce a current in load L 1  to produce an output voltage Vout 1  relative to Vgnd 2 . The current input In 2  relative to Vgnd 1  is mirrored by current mirrors M 3 , M 4  and M 3 , M 5  to produce a current in load L 2   a  and a current in load L 2   b , to produce an output voltage Vout 2   a  relative to Vgnd 2  and an output voltage Vout 2   b  relative to Vgnd 3 , respectively. In like manner, the current input Iin 3  relative to Vgnd 3  is mirrored by current mirror M 6 , M 7  to produce a current in load L 3  to produce an output voltage Vout 3  relative to Vgnd 1 .  
      The following example circuits of  FIGS. 5 and 6  are provided to illustrate how the operation of the circuits  20 ,  30   a ,  30   b , and  40  may be further enhanced with respect to noise that may be introduced via changes in the supply reference voltages. The remaining figures illustrate techniques for minimizing current flow between the systems.  
       FIG. 5  illustrates an example circuit diagram of a level shifting circuit  50  that is particularly well suited for coupling an analog signal between two isolated systems. The current mirror M 1 , M 2  and diodes D 1 , D 2  correspond to the level-shifting circuit  30   b  of  FIG. 3B . The input current Iin is mirrored by current mirror M 5 , M 6 , by current mirror M 1 , M 2 , and finally by current mirror M 3 , M 4 , yielding an output current Iout that is substantially equal to the input current Iin. Diodes D 1  and D 2  select the lower of the two ground potentials Vgnd 1  and Vgnd 2  creating Vmin. Therefore the input current is always transferred to the output independent of the difference between the two ground potentials. Each of the current mirrors M 1 , M 2 ; M 3 , M 4 ; M 5 , M 6  is cascoded using transistors M 11 , M 12 ; M 13 , M 14 ; and M 15 , M 16 , respectively, to increase the supply rejection. Thus, the influence of changes in the difference between the two ground potentials is reduced. In addition, devices M 22  and M 26  have been added to cancel signals introduced by the gate-drain capacitance of M 12  and M 16 , respectively, as a result of the changes in the difference of the ground potentials. Suppose, for example, that Vgnd 1  is larger than Vgnd 2  so that D 1  is blocking while D 2  is conducting. In this case transistors M 1  and M 11  are connected to Vgnd 2  by D 2 . When Vgnd 1  and Vdd 1  are changing with respect to Vgnd 2  the gate-drain capacitance of M 16  is injecting current at the input of cascoded current mirror M 1 , M 2 ; M 11 , M 12 . The gate-drain capacitance of M 26  is subtracting a similar signal at the output of the current mirror M 1 , M 2  cancelling the influence of the gate-drain capacitance of M 16 . Similarly, the gate-drain capacitance of M 22  cancels the influence of the gate-drain capacitance of M 12  when Vdd 2  changes with respect to Vmin. Transistor M 25 , biased by current source I 25 , isolates the gate-drain capacitance of M 16  from the input current.  
       FIG. 6  illustrates an example circuit diagram of a level shifting circuit  60  that is particularly well suited for coupling a digital signal between two isolated systems. The core of the digital level-shift circuit comprising M 1 , M 12  and M 21 , M 22  is completely differential to obtain high power-supply rejection in order to cope with changes in one ground potential with respect to the other ground potential. Another advantage of the fully-differential level shift is that the digital switching does not influence the current drawn from the supplies Vdd 1  and Vdd 2  or the current delivered to the grounds Vgnd 1  and Vgnd 2 , so that the current flowing between the two grounds is not affected by the digital switching. This is an important advantage over the circuit discussed in the prior art and yields improved EME performance.  
      At the heart of the circuit are two P-channel current mirrors M 3 , M 5  and M 4 , M 6  similar to the level shifter  30   a  shown in  FIG. 3A . These current mirrors perform the level shift of the current signals using Vmax created by diodes D 1  and D 2 , from supply voltages Vsup 1  and Vsup 2  that are each higher than Vdd 1  and Vdd 2 , respectively. The differential currents for the level-shift current mirrors are produced by differential pair M 1 , M 2 . Transistor M 1  is driven by the digital input signal Vin while M 2  is driven by the inverted input signal created by inverter M 13 , M 14 . The differential stage M 1 , M 2  drives the level-shift current mirrors M 3 , M 5  and M 4 , M 6  via cascodes M 21  and M 22 . These cascodes are DMOS transistors that can handle high voltages at the drain connection while limiting the voltage across the low-voltage CMOS transistors M 1  and M 2 . Therefore, the circuit can still operate with large voltage differences between Vgnd 1  and Vgnd 2 . The level-shifting current mirrors M 3 , M 5  and M 4 , M 6  then drive current mirrors M 7 , M 9  and M 8 , M 10 , respectively. Finally, the drain current of M 9  is mirrored by current mirror M 11 , M 12  and added to the drain current of M 10  producing a single-ended signal within the range of the digital supply Vdd 2  referenced to the second ground potential Vgnd 2 . This signal is buffered by inverters M 15 , M 16  and M 17 , M 18  creating the output signal Vout. Current sources M 32  and M 33  have been added to maintain a minimum bias current in transistors M 3  through M 12  and M 21 , M 22  improving the speed of the circuit. As an example consider the case when the input signal Vin is high. In that case the gate of M 1  is high and the gate of M 2  is low. Therefore, transistors M 21 , M 3 , M 5 , M 7 , M 9 , M 11  and M 12  are biased at a high current while transistors M 2 , M 22 , M 4 , M 6 , M 8  and M 10  are biased at a low current so that the voltage at the drains of M 10  and M 12  goes up and therefore also the output OUT goes high.  
      The following figures present a variety of techniques for minimizing current flow between isolated systems, herein referred to as “compensation” techniques.  
       FIG. 7  illustrates an example block diagram of a compensated isolated level shifting circuit  70  for coupling signals between two isolated systems. The isolated systems include a first system with reference voltages Vdd 1  and Vgnd 1 , and a second system with reference voltages Vdd 2  and Vgnd 2 . The circuit  70  includes a voltage source Vos that is configured to offset the biasing of the level shifter  71 . This offset voltage Vos biases the level shifter  71  sufficiently so that the voltage source Vdd 1  consistently provides power to the level shifter  71 , to avoid transient switching. A current generator Icomp provides a compensating current from the second system to the first system that offsets the current that is provided by the first voltage source to the second system, to provide a substantially zero net current flow between the systems. The offset voltage Vos could also be configured to bias the level shifter  71  so that Vdd 2  provides the power to the level shifter  71 , and so on. In like manner, the current generator Icomp could be configured to provide current from the first system to the second, or a combination of compensation generators could be used to substantially equalize the current flow from each system, and so on.  
       FIG. 8  illustrates an example circuit diagram of a compensated level shifting circuit  80  for coupling signals between two isolated systems. The core of this example circuit  80  corresponds to circuit  30   a  of  FIG. 3A . The voltage source Vos offsets the voltage Vdd 2  so that diode D 2  is consistently turned off, and diode D 1  is consistently turned on, during normal fault-free operation, thereby minimizing switching transients. Current generator Icomp provides a current from the second system (Vdd 2 ) to the first system (Vgnd 1 ) that, over a wide frequency range, matches the current Iout that is provided by the first system (Vdd 1 ) to the load L in the second system. In this manner, the net current flow between the two systems is substantially zero.  
       FIG. 9  illustrates an example circuit diagram of a differential compensated level shifting circuit  90  for coupling signals between two isolated systems that embodies the principles presented in the circuit  80  of FIG.,  8 . The core of this circuit  90  corresponds to the example circuit  60  of  FIG. 6 , discussed above. The compensation circuitry includes diode D 40  and transistors M 40  and M 41 . It is assumed in this example circuit  90  that Vsup 1  is configured to be higher than Vsup 2 , and therefore Vsup 1  provides the current to the circuit  90  during non-fault operation. The bias current Ibias controls the current from Vsup 2  through the compensation circuitry to Vgnd 1  to compensate for the current that is provided by Vsup 1  to Vgnd 2  via M 5  and M 6 .  
       FIG. 10  illustrates an example circuit diagram of a compensated level shifting circuit  100  that is particularly well suited for coupling analog signals between isolated systems. The core of this example circuit  100  corresponds to example circuit  50  in  FIG. 5 , discussed above. In this circuit the input current Iin is first duplicated using cascoded current mirror M 7 , M 9 ; M 17 , M 19 . One output at the drain of M 18  is used as input for the current mirror M 5 , M 6 ; M 15 , M 16 ; M 15 , M 25 . The second output at the drain of M 19  is mirrored by cascoded current mirror M 31 , M 32 ; M 33 , M 34  so that a current is flowing from Vdd 1  via blocking diode D 32  to Vgnd 2 . In this case it is assumed that during normal operation Vgnd 2  is larger than Vgnd 1  so that D 2  blocks and the drain current of M 2  flows from Vdd 2  via D 1  to Vgnd 1 . This current is compensated by the current created by M 32 .  
       FIG. 11  illustrates an example circuit diagram of an alternative compensating level shifting circuit  110  for coupling signals between two isolated systems. This example circuit  110  provides the general principle for automatic current compensation using this example technique. Assume a first example wherein Vdd 1  is larger than Vdd 2 , so that only current I 1  is provided to the level shifting circuit  110 . Half of this current I 1  will flow through each leg of the current mirror M 1 , M 2 , the current through M 2  (of magnitude I 1 / 2 ) flowing into the second system via the load L to Vgnd 2 . The current generator I 1 / 2  draws this same amount of compensation current from Vdd 2  to Vgnd 1  via diode D 3 . In like manner, when Vdd 2  provides the current I 2  to the level shifting circuit  110 , current generator I 2 / 2  draws the compensation current from Vdd 1  to Vgnd 2  via diode D 4 .  
       FIG. 12  illustrates an example implementation of a level shifting circuit  120  for coupling signals between two isolated systems, using the principles discussed with regard to the example circuit  110  of  FIG. 11 . The basic level-shift circuit, again, consists of current mirror M 1 , M 2 , input current Iin and load L, while diodes D 1 , D 2  select the highest supply voltage from Vdd 1  and Vdd 2 . By placing diode-connected transistors M 11  and M 12  between the diodes and current mirror M 1 , M 2  the currents I 1 , I 2  flowing through the diodes D 1 , D 2  are measured and provided to current mirrors M 15 , M 17  and M 16 , M 18 . The W/L ratio of transistors M 15  and M 16  are configured to be twice that of transistors M 17  and M 18 , so that half of the measured currents I 1  and I 2  are drawn from the supplies Vdd 1  and Vdd 2  via blocking diodes D 4  and D 3 . The total current drawn from Vdd 1  is equal to two times I 1  plus half I 2 . Assuming the W/L ratios of transistors M 1  and M 2  are equal so that Iout equals Iin, the current delivered to Vgnd 1  via M 1  is equal to half the sum of I 1  and I 2 , and the current delivered to Vgnd 1  via M 15  and M 17  is one and a half I 1 , for a total of two times I 1  plus half I 2 . Thus, the current to Vgnd 1  is substantially identical to the current provided by Vdd 1 , and thus substantially zero net current flows from the first system of Vdd 1 -Vgnd 1 . Similarly, the current delivered to Vgnd 2  is substantially equal to the current provided by Vdd 2 . Although the circuit is more complicated than the previously discussed compensation circuit and consumes more bias current, the compensation is automatic so that the compensation circuit does not have to be adapted according to the number of level-shift circuits. Thus, multiple signals can be transferred using only one current compensation arrangement, as illustrated in  FIGS. 13-15 .  
       FIG. 13  illustrates an example block diagram of a level shifting system  130  for coupling multiple signals between isolated systems using the principles discussed above regarding circuits  110  and  120  of  FIGS. 11 and 12 . The system  130  includes a common compensated voltage supply  140 , and one or more level shifting modules  150 . The supply  140  provides the supply voltage Vmax to each module  150 , and also includes current measuring and compensating circuitry, as detailed below. Each level shifting module  150 , illustrated further in  FIG. 15 , couples an input signal Iini to a corresponding output Vouti (i=1 to j), using the principles discussed with regard to the example circuit  60  of  FIG. 6 .  
       FIG. 14  illustrates an example circuit diagram of a power supply  140 , with compensation, for use in a level shifting system  130 . This circuit employs the current measuring and compensating techniques discussed with regard to circuits  110  and  120  of  FIGS. 11 and 12 . In this circuit all current mirrors M 11 -M 18  are cascoded by transistors M 21 -M 28 . Operation at reasonably low supply voltages is maintained by biasing the cascodes inside the gate-source voltages of the current-mirror transistors M 11 -M 18 . Instead of placing the cascades M 21 -M 28  on top of the current-mirror transistors M 11 -M 18 , the gates of the cascodes M 21 -M 28  are connected to the gates of the current-mirror transistors M 11 -M 18  via diodes D 21 , D 22 , D 25 , and D 26 . The diodes generate a voltage drop so that the drain-source voltage of the current-mirror transistors is sufficient for proper operation. Also, supply Vmax is provided from the drain of M 11  and M 12  instead of the gate of M 11  and M 12  or the gate of M 21  and M 22 . That is, the current mirror M 11 , M 13 , M 21 , M 23  and M 12 , M 14 , M 22 , M 24  can be considered as folded-cascode current mirrors. Thus, the voltage drop between the Vsup 1  and Vmax or Vsup 2  and Vmax is limited to approximately two diode voltage drops.  
       FIG. 16  illustrates an example block diagram of another compensated level shifting circuit  160 . In this example embodiment, two switches S 1 , S 2  are controlled based on which system is supplying the current to the level shifting circuit  160 . If Vdd 1  is higher than Vdd 2 , diode D 1  is forward biased, diode D 2  is reverse biased, and current I 1  flows through diode D 1  to both legs of the current mirror M 1 , M 2 . The current through transistor M 1  is referred to in this example circuit as I 2 . In this example, I 1  is larger than I 2 , switches S 1  and S 2  are set as illustrated in  FIG. 16 , enabling the current generator I 1 -I 2  to draw the difference current I 1 -I 2  from source Vdd 2  via D 3 . In this example, the total current from Vdd 1  is I 1 , and the total current to Vgnd 1  is also I 1 . In like manner, if Vdd 2  supplies the current to the level shifter, I 1  is substantially zero, I 2  is greater than I 1 , and switches S 1  and S 2  are set opposite to the state illustrated in  FIG. 16 . In this case, Vdd 2  provides current I 2  to Vgnd 1  via M 1 , and Vdd 1  provides a substantially equal current I 2  to Vgnd 2  via D 4 , for a net current flow of substantially zero between the systems.  
       FIG. 17  illustrates an example embodiment of a compensated level shifting circuit  170 , using the principles discussed with regard to the example circuit  160  of  FIG. 16 . The compensation circuit is shown together with a simple level-shift circuit comprising transistors M 1 , M 2  and diodes D 1 , D 2 . The current I 1  flowing through diode D 1  is measured by M 11  and mirrored by current mirror M 11 , M 13 , M 21 , M 23 . The current I 2  flowing from the level shift into the first ground Vgnd 1  is measured by M 12  and mirrored by mirror M 12 , M 14 , M 22 , M 24 . The outputs of the two current mirrors at the drains of M 23  and M 24  are connected together yielding the difference of I 1  and  12 . This current difference is flowing into the source of M 15  or the source of M 16 . When I 1  is larger than I 2  the current difference is flowing into the source of M 16  and is mirrored by cascoded current mirror M 18 , M 20 , M 28 , M 30 . The current difference is then drawn from Vdd 2  via blocking diode D 4 . When I 2  is larger than I 1  the current difference is flowing through M 15  and is mirrored by cascoded current mirror M 17 , M 19 , M 27 , M 29 . Thus, the current difference is flowing into Vgnd 2  via blocking diode D 3 . Transistors M 35  and M 36 , connected in the same way to transistors M 25  and M 26  as transistors-M 15  and M 16 , form a source of current I 11  that is used to set the quiescent current in mirrors M 11 , M 13 , M 21 , M 23  and M 12 , M 14 , M 22 , M 24  so that both mirrors are always biased even when diode D 1  is blocking. This improves the dynamic behavior. The value of I 11  does not affect the current difference I 1 -I 2  flowing into the source of M 15  and M 16 . Current sources I 25  and I 26  and transistors M 25  and M 26  set the quiescent current for transistors M 15  and M 16  and also for current mirrors M 18 , M 20 , M 28 , M 30  and M 17 , M 19 , M 27 , M 29 . Since this quiescent current is drawn substantially equally from both supplies and is delivered substantially equally to both grounds there is substantially no resulting current flowing between the two grounds. Therefore, the whole circuit is always biased and the dynamic behavior is much better than the dynamic behavior of the compensation circuits based on the first technique. Also, because the difference of currents is used, less current is consumed. The reference voltage Vref is used to bias the sources of M 15  and M 16  somewhere in the middle of the supply-voltage range so that M 23  and M 24  are properly biased. It is also possible to remove voltage source Vref and replace current source I 26  by a voltage source, a number of diodes, or a few diode-connected MOS transistors.  
      The foregoing merely illustrates the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are thus within the spirit and scope of the following claims.