Patent Publication Number: US-11641002-B2

Title: Optical transmission/reception circuit

Description:
BACKGROUND 
     Technical Field 
     The present disclosure generally concerns electronic circuits and, more specifically, an optical transduction circuit. 
     Description of the Related Art 
     Certain electronic circuits comprise an electronic chip housed in a package. Such a package often comprises a substrate having the chip affixed thereon, and a cover covering the chip and the substrate. 
     When such a device is an optical signal transduction circuit, for example, a time-of-flight measurement proximity sensor, the electronic chip comprises one or a plurality of optical signal transduction regions. The package then comprises transparent elements adapted to the wavelengths of the optical signals, for example, infrared radiations. The transparent elements are placed opposite the transmission/reception regions, and are for example made of glass. 
     BRIEF SUMMARY 
     An embodiment overcomes all or part of the disadvantages of known optical transduction devices. 
     An embodiment provides a device comprising a substrate and an optoelectronic chip buried in the substrate. 
     According to an embodiment, the substrate comprises an opening, preferably filled with a transparent material, above a first optical transduction region of the chip. 
     According to an embodiment, the opening is continued above a second optical transduction region. 
     According to an embodiment, the second region is a region of an additional chip buried in the substrate. 
     According to an embodiment, a cover covers the substrate. 
     According to an embodiment, the cover comprises an element, preferably transparent, crossing the cover above the first region. 
     According to an embodiment, the through element is continued above the second region. 
     According to an embodiment, a shield is located on the through element above the second region. 
     According to an embodiment, the cover has a planar surface mechanically coupled to the substrate, preferably glued to the substrate or in direct adhesive contact with the substrate. 
     According to an embodiment, the cover and the substrate are made of a same material. 
     Another embodiment provides a method of manufacturing the above device. 
     According to an embodiment, the method comprises a step of overmolding the cover on the substrate. 
     According to an embodiment, the overmolding is film assisted. 
     According to an embodiment, the method comprises a step of removing a protection located on the chip. 
     According to an embodiment, the protection is flush with a surface of the substrate. 
     The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIG.  1    is a simplified cross-section view illustrating an embodiment of an optical transduction device; 
         FIGS.  2 A to  2 C  are simplified cross-section views illustrating alternative embodiments of the device of  FIG.  1   ; 
         FIGS.  3 A to  3 G  are simplified cross-section views illustrating steps of a method of manufacturing the device of  FIG.  1   ; 
         FIGS.  4 A to  4 C  are simplified cross-section views illustrating another embodiment of an optical transduction device; and 
         FIGS.  5 A to  5 C  are simplified cross-section views illustrating steps of a method of manufacturing the device of  FIG.  4 A . 
     
    
    
     DETAILED DESCRIPTION 
     The same elements have been designated with the same reference numerals in the various drawings and, further, the various drawings are not to scale. For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, the chip is not detailed, the described embodiments and variations being compatible with most current chips. 
     In the following description, when reference is made to terms qualifying absolute positions, such as terms “front”, “rear”, “top”, “bottom”, “left”, “right”, etc., or relative positions, such as terms “above”, “under”, “upper”, “lower”, etc., or to terms qualifying directions, such as terms “horizontal”, “vertical”, etc., it is referred to the orientation of the concerned element in the concerned drawings, it being understood that, in practice, the described devices may be oriented differently. The terms “approximately”, “substantially”, and “in the order of” are used herein to designate a tolerance of plus or minus 10%, preferably of plus or minus 5%, of the value in question, or, relating to an orientation, of plus or minus 10 degrees, preferably of plus or minus 5 degrees. 
       FIG.  1    is a simplified cross-section view illustrating an embodiment of an optical transduction device  100  for transmitting and/or receiving optical signals. More particularly,  FIG.  1    illustrates an example of a time of-flight measurement proximity sensor. 
     Device  100  comprises a substrate  110 . Substrate  110  is for example an assembly of glass fibers, of resin, and of conductive layers. Substrate  110  preferably has the shape of a plate, for example having two opposite surfaces  112  (upper surface) and  114  (lower surface). As an example, lower surface  114  is planar. 
     The device comprises a chip  120 A. Chip  120 A preferably comprises a portion of a semiconductor wafer, for example, made of silicon. Chip  120 A is buried in the substrate, that is, it is buried in the substrate and at least partially covered with a portion of the substrate. Chip  120 A is entirely comprised between the levels of surfaces  112  and  114  of substrate  110 . As an example, chip  120 A has a surface  122 A, preferably planar, facing the side of surface  112  of substrate  110 . Electronic circuits, not shown, are located in chip  120 A on the side of surface  122 A. Preferably, chip  120 A is an optoelectronic chip. As an example, chip  120 A comprises, on the side of surface  122 A, an optical transduction region  124 A, preferably an optical transmission region. Chip  120 A may comprise a plurality of optical transduction regions. 
     As an example, device  100  further comprises an additional chip  120 B buried in substrate  110 . Preferably, chip  120 B comprises a semiconductor wafer portion, for example, made of silicon. Chips  120 A and  120 B for example have the same thickness. Preferably, chips  120 A and  120 B have their respective upper surfaces  122 A and  122 B located in a same plane, parallel to surface  112  of substrate  110 . Preferably, chip  120 B is an optoelectronic chip, comprising both electronic circuits and one or a plurality of optical transduction regions on the side of surface  122 B. In the illustrated example, chip  120 B comprises two optical reception regions  124 B and  124 C. Region  124 C is preferably located between optical region  124 B of chip  120 B and optical region  124 A of chip  120 A. 
     As an example, substrate  110  comprises an opening  116 A above region  124 A. Opening  116 A extends from the level of surface  112  of substrate  110  to that of surface  122 A. Opening  116 A is for example empty or may be filled with a gas such as air. Preferably, opening  116 A is filled with a transparent material. “Transparent” here means a material giving way to all or part of optical signals transmitted or received by an optical transduction region of an optoelectronic chip. The transparent material may be an optical resin. The material of substrate  110  is preferably opaque for these optical signals. 
     In the illustrated example, the substrate further comprises an opening  116 B located above region  124 B. Preferably, openings  116 A and  116 B are separated by an opaque wall  118 . Opening  116 B may be filled with a transparent material. Preferably, opening  116 A extends above region  124 C. Regions  124 A and  124 C are then located under the same opening  116 A. 
     As a variation, chips  124 A and  124 B are replaced with a single chip comprising the three regions  124 A,  124 B, and  124 C. In another variation, the device comprises more than two chips. 
     As an example, device  100  further comprises metallizations  130  located on lower surface  114  of substrate  110 . Metallizations  130  enable to electrically couple device  100  to an external circuit, not shown, for example, a PCB (“Printed Circuit Board”). Electric connections  132  couple metallizations  130  to chip  120 A and to optional chip  120 B. The electric connections are located inside of substrate  110 . Preferably, the electric connections are in contact with chip  120 A on the side of its surface  122 A, and with optional chip  120 B on the side of its surface  122 B. Electric connections  132  couple metallizations  130  to the circuits of chip  120 A and or optional chip  120 B. 
     Preferably, a cover  140  covers substrate  110  on the side of its surface  112 . Cover  140  is preferably made of a polymer material, for example, of a thermosetting polymer such as epoxy resin. The material of cover  140  is preferably opaque. Cover  140  preferably has the shape of a plate. Cover  140  has a planar surface  142  mechanically coupled to upper surface  112  of substrate  110 . The mechanical coupling between cover  140  and substrate  110  may be performed by means of glue  144 . As a variation, the mechanical coupling between cover  140  and substrate  110  is achieved by direct adhesive contact with the substrate, for example, obtained by overmolding of cover  140  on substrate  110 . Cover  140  further comprises a through opening  146 A located above optical transduction region  124 A. A transparent element  150 A is housed in through openings  146 A. Transparent element  150 A is preferably made of glass. Transparent element  150 A for example forms an optical lens or a filter. In the illustrated example, the cover further comprises a through opening  146 B located above region  124 B, and a transparent element  150 B housed in opening  146 B. 
     Due to the fact that the optoelectronic chip is buried in substrate  110 , device  100  has, between lower surface  114  of substrate  110  and the upper surface of cover  140 , a particular small total thickness, smaller than that of usual devices. A total thickness smaller than 500 μm may typically be obtained. This enables to solve various integration problems, for example, in the case where the device has to be integrated in a compact assembly such as a cell phone. Preferably, the thickness of substrate  110  between surfaces  112  and  114  is smaller than 300 μm, for example, in the range from 150 μm to 250 μm. Preferably, the thickness of cover  140  is smaller than 300 μm, for example, in the order of 250 μm. In the illustrated example, when the time of-flight measurement distance sensor is operating, transmission region  124 A transmits an optical signal through opening  116 A and transparent element  150 A. Due to the fact that regions  124 A and  124 C are located under the same opening  116 A, reception region  124 C receives part of the optical signal. Opaque wall  118  prevents part of the optical signal from reaching reception region  124 B without coming out of the device. Part of the optical signal reaches reception region  124 B after having been reflected and having crossed transparent element  150 B and opening  116 B. The time of flight corresponds to the difference between the times of reception by regions  124 C and  124 B. 
       FIGS.  2 A to  2 C  are simplified cross-section views illustrating alternative embodiments of the device of  FIG.  1   . 
     The device of  FIG.  2 A  comprises a substrate  210 , chips  120 A and  120 B buried in substrate  210 , and a cover  240 A covering substrate  210 . Substrate  210  corresponds to substrate  110  of the device of  FIG.  1   , where opening  116 A does not extend above region  124 C, and the substrate comprises, above region  124 C, an opening  116 C separate from opening  116 A. As a variation, chips  120 A and  120 B are replaced with a single chip comprising the three regions  124 A,  124 B, and  124 C, or with more than two chips. Cover  240 A differs from cover  140  of  FIG.  1    in that it comprises a cavity  246 A above region  124 A. Cavity  246 A is located on the side of the cover facing the chip. Preferably, cavity  246 A extends above region  124 C. As an example, transparent element  150 A has a thickness smaller than the total thickness of the cover. 
     Cavity  246 A is preferably filled with a transparent material. The transparent material is for example an optical resin. In operation, cavity  246 A of the device of  FIG.  2 A  transmits towards region  124 C part of the optical signal emitted by region  124 A. 
     The device of  FIG.  2 B  comprises a substrate  210  and chips  120 A and  120 B, identical or similar to those of the device of  FIG.  2 A , arranged in identical or similar fashion. Substrate  210  is covered with a cover  240 B. Cover  240 B differs from cover  240 A of the device of  FIG.  2 A  in that it further comprises a cavity  246 B above region  124 B. Cavity  246 B extends, from above opening  116 B, all around opening  116 B on surface  112  of substrate  210 . Cavity  246 B thus has lateral dimensions greater than those of opening  116 B. Cavity  246 B is located on the side of the cover which faces chip  124 B. As an example, transparent element  150 B has a thickness smaller than the total thickness of cover  240 B. 
     Preferably, transparent elements  150 A and  150 B have the same thickness. Portions  248  of the cover located between and around openings  246 A and  246 B thus form feet which have the same height. Due to the fact that the lateral dimensions of cavities  246 A and  246 B are greater than those of respective openings  116 A and  116 B, problems of glue overflow in openings  116 A and  116 B are avoided. 
     The device of  FIG.  2 C  comprises a substrate  210  and chips  120 A and  120 B, identical or similar to those of the device of  FIG.  2 A , arranged in identical or similar fashion. Substrate  210  is covered with a cover  240 C. Cover  240 C differs from that of  FIG.  1    in that opening  146 A and transparent through element  150 A are continued above region  124 C. An opaque shield  260 , for example, a layer of an opaque material, covers transparent element  150 A above region  124 C. In operation, opaque shield  260  prevents regions  124 C from receiving the reflected optical signals. 
       FIGS.  3 A to  3 G  are simplified cross-section views illustrating steps of an embodiment of the device of  FIG.  1   , in the example of a device comprising two chips  120 A and  120 B. 
     As an example, a plurality of devices arranged in an array are simultaneously manufactured. 
     At the step of  FIG.  3 A , a first layer  110 - 1  of the material of the future substrate  110 , comprising openings  300  at the locations of chips  120 A and  120 B, is provided. Layer  110 - 1  preferably has the same thickness as chips  120 A and  120 B. Openings  300  may be through openings. 
     Layer  110 - 1  is positioned on a planar surface of an adhesive support, for example, an adhesive film  310 . As an example, adhesive film  310  is a polymer film, having a thickness preferably in the range from 10 μm to 400 μm. The polymer film is covered with a layer of an adhesive allowing a temporary mechanical connection. 
     At the step of  FIG.  3 B , chips  120 A and  120 B are placed in openings  3000 . Chips  120 A and  120 B are pasted to adhesive film  310 . Preferably, openings  300  have dimensions identical, to within a functional clearance, to those of chips  120 A and  120 B. 
     Chips  120 A and layer  110 - 1  are partially covered, at the respective locations of the future openings  116 A and  116 B, with elements  320 A and  320 B, for example, portions of a layer. Preferably, elements  320 A and  320 B are made of a polymer material selectively etchable over the material of the future substrate  110 . Protection elements  320 A and  320 B are for example portions of a resin film, of an opaque film, of a dry film, or of a polymer film. 
     At the step of  FIG.  3 C , layer  110 - 1  and chips  120 A and  120 B are covered with a layer  110 - 2 . Preferably, the material of layer  110 - 2  is the same as that of layer  110 - 1 . Layer  110 - 2  preferably has a planar upper surface  112 . The thickness of layer  110 - 2  corresponds to the height of the future openings  116 A and  116 B, that is, to the distance separating the upper surfaces of chips  120 A and  120 B from surface  112  of the future substrate  110 . 
     Preferably, elements  320 A and  320 B have a thickness smaller than that of layer  110 - 2 . Elements  320 A and  320 B protect the upper surface of chips  120 A and  120 B and of layer  110 - 1 , at the locations of the openings, against a direct contact with layer  110 - 2 . 
     At the step of  FIG.  3 D , adhesive film  310  is removed. Chips  120 A and  120 B are in direct adhesive contact with layer  110 - 2 . The portions of layer  110 - 2  located above protection elements  320 A and  320 B are etched at the locations of the future openings  116 A and  116 B. Protection elements  320 A and  320 B are then removed, preferably, by a selective etching. Openings  116 A and  116 B have thus been obtained. 
     As a variation, protection elements  320 A and  320 B have the same thickness as layer  110 - 2 . The step of etching the portions of layer  110 - 2  located above protection elements  320 A and  320 B is then omitted. 
     At the step of  FIG.  3 E , the lower surface of layer  110 - 1  and of chips  120 A and  120 B is covered with a layer  110 - 3 , and connections  132  and metallizations  130  are formed. The material of layer  110 - 3  is preferably the same as that of layers  110 - 1  and  110 - 2 . The lower surface of layer  110 - 3  forms lower surface  114  of substrate  110 . 
     At the step of  FIG.  3 F , openings  116 A and  116 B are filled with a transparent material  330 . Transparent elements  150 A and  150 B are then arranged at their respective locations above regions  124 A and  124 B. 
     At the step of  FIG.  3 G , cover  140  is formed by film assisted molding. To achieve this, elements  150 A and  150 B are covered with a film  340 . Film  340  bears against the upper surfaces of elements  150 A and  150 B. Film  340  is for example parallel to the plane of the layers. The entire obtained structure is then placed in a mold, not shown. A layer  140 - 1 , for example, of constant thickness, is formed by molding. During the molding, film  340  bears against the inner surface of the mold. Layer  140 - 1  is for example made of a thermosetting material. The material of layer  140 - 1  may be the same as that of substrate  110 . Elements  150 A and  150 B then cross layer  140 - 1  across its entire thickness. Film  340  is then removed. Film  340  eases the release from the mold and avoids for a portion of the material of layer  140 - 1  to cover elements  150 A and  150 B. Although the above-described molding is assisted by film  340 , film  340  may be omitted and a molding which is not film-assisted may be performed. 
     After this, the devices are separated into individual devices, by cutting along cutting lines  350 . 
     In each obtained device, substrate  110  is formed of layers  110 - 3 ,  110 - 1 , and  110 - 2 , and cover  140  is formed of layer  140 - 1 . Cover  140 , which has been overmolded on the substrate, is mechanically coupled by direct adhesive bonding to layer  110 - 2 . 
     As a variation, steps  3 E and  3 F may be replaced with a step of manufacturing cover  140  independently from the structure obtained at the step of  FIG.  3 D , followed by a step of bonding cover  140  to the structure obtained at the step of  FIG.  3 D . 
     The above-described method is compatible with the alternative embodiments of  FIGS.  2 A to  2 C  and is compatible with any number of chips, for example, optoelectronic. 
       FIGS.  4 A to  4 C  are simplified cross-section views illustrating examples of another embodiment of an optical transduction device  400 . More particularly,  FIGS.  4 A to  4 C  illustrate examples of time-of-flight measurement proximity sensors. 
     In the examples of  FIGS.  4 A to  4 C , device  400  comprises a substrate  410 . Substrate  410  is for example an assembly of glass fibers, of resin, and of conductive layers. Substrate  410  is preferably made of an opaque material. Substrate  410  is for example in the shape of a plate, for example, having two opposite surfaces  412  (upper surface) and  414  (lower surface). As an example, surface  412  is planar. 
     Device  400  comprises a chip  120 A and an optional chip  120 B, identical or similar to those of  FIG.  1   . Chip  120 A has a surface  122 A, preferably planar, which is flush with surface  412  of substrate  410 . Optional chip  120 B has a surface  122 B, preferably planar, which is flush with surface  412  of substrate  410 . As a variation, chips  120 A and  120 B are replaced with a single chip comprising three optical transmission/reception regions  124 A,  124 B, and  124 C. As a variation, device  400  comprises more than two chips. 
     Device  400  may further comprise, on surface  414 , metallizations  130  identical or similar to metallizations  130  of the device of  FIG.  1   . Electric connections  432  thoroughly cross the substrate, from metallizations  130  to surface  412 , preferably vertically. 
     In each of the examples of  FIGS.  4 A to  4 C , substrate  410  is covered with a different example of cover. Due to the fact that chip  120 A and optional chip  120 B are flush with the upper surface of the substrate, the device has a total thickness from the lower surface of the substrate to the upper surface of the cover which is particularly decreased in each of these examples. 
     In the example of  FIG.  4 A , device  400  comprises a cover  440 A covering substrate  410  on the side of surface  412 . Cover  440 A comprises elements identical or similar to those of cover  240 A of  FIG.  2 A , arranged in identical or similar fashion. Thus, cover  440 A comprises, on the side of substrate  410 , a cavity  246 A. Regions  124 A and  124 C are located under the same cavity  246 A. Cover  440 A further comprises through elements  150 A and  150 B, preferably transparent. Through elements  150 A and  150 B are respectively located above regions  124 A and  124 B. Cavity  246 A is preferably filled with a transparent material. 
     Cover  440 A further comprises electric connections. Connections  434  couple the tops of connections  432  to the upper surfaces of chip  120 A and of optional chip  120 B. Certain connections  434  may be included in the material of cover  440 A. Certain connections  434  may be included in the transparent material of cavity  246 A. Certain connections  434  may be partly included in the material of cover  440 A and partly included in that of cavity  246 A. 
     In the example of  FIG.  4 B , device  400  further comprises a cover  440 B covering substrate  410  on the side of surface  412 . Cover  440 B comprises elements identical or similar to those of cover  240 B of  FIG.  2 B . In particular, the cover comprises, in addition to cavity  246 A, a cavity  246 B. Cavities  246 A and  246 B may be empty or filled with air. Cover  440 B may then be formed independently from substrate  410  and the elements located in the substrate, and then bonded to surface  412 . To achieve this, it is provided for connections  434  to be entirely located in cavities  246 A and  246 B. Further, due to the fact that the portions of the cover located between and around cavities  246 A and  246 B form feet  248  of same height, the arranging of cover  440 B on substrate  410  enables to easily obtain, between openings  246 A and  246 B, an opaque wall in contact with the upper surface of chip  120 B flush with the upper surface of substrate  410 . 
     In the example of  FIG.  4 C , device  400  further comprises a cover  440 C covering substrate  410  on the side of surface  412 . Cover  440 C comprises elements identical or similar to those of cover  240 C of  FIG.  2 C . An opaque shield  260  covers transparent element  150 A of cover  440 C above region  124 C. Connections  434  are preferably included in the material of cover  440 C. 
       FIGS.  5 A to  5 C  are simplified cross-section views illustrating steps of an example of a method of manufacturing the device of  FIG.  4 A , in the example of a device comprising two chips  120 A and  120 B. 
     As an example, a plurality of devices arranged in an array are simultaneously manufactured. 
     At the step of  FIG.  5 A , a layer comprising a plurality of substrates  410  arranged in an array is provided. A single substrate  410  is shown in  FIGS.  5 A to  5 C . Substrate  410  comprises, on the side of its upper surface  412 , a housing  500 A for chip  120 A. The depth of housing  500 A corresponds to the thickness of chip  120 A. Substrate  410  comprises, on the side of its upper surface  412 , a housing  500 B for chip  120 B. The depth of housing  500 B corresponds to the thickness of chip  120 B. The substrate further comprises metallizations  130  and connections  432 . 
     Chips  120 A and  120 B are then arranged in their respective housings  500 A and  500 B. The chips are flush with upper surface  412  of substrate  410 . Connections  434  are formed, each connection  434  coupling the top of a connection  432  to the upper surface of one of the chips. 
     At the step of  FIG.  5 B , a portion of layer  510  of transparent material is formed at the location of the future cavity  246 A. The portion of layer  510  covers both region  124 A and region  124 C. The portion of layer  510  may partially or totally cover some of connections  434 . Elements  150 A and  150 B are then arranged on respective regions  124 A and  124 B. As an example, element  150 B may be bonded by means of a transparent glue  520  to region  124 B. 
     At the step of  FIG.  5 C , a molding, preferably film assisted, is carried out similarly to that described in relation with  FIG.  3 G . Elements  150 A and  150 B are covered with a film  540 . Film  540  bears against the upper surfaces of elements  150 A and  150 B. A layer  440 - 1  is then formed by molding, film  540  bearing against an inner wall of a mold. 
     The devices are then separated into individual devices by cutting along lines  550 . 
     The above-described method is compatible with the examples of  FIGS.  4 B and  4 C  and is compatible with any number of chips, for example, optoelectronic. 
     Specific embodiments have been described. Various alterations, modifications, and improvements will readily occur to those skilled in the art. 
     Various embodiments with different variations have been described hereinabove. It should be noted that those skilled in the art may combine various elements of these various embodiments and variations without showing any inventive step. 
     Finally, the practical implementation of the described embodiments is within the abilities of those skilled in the art based on the functional indications given hereinabove. 
     Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. 
     The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.