Patent Publication Number: US-4150310-A

Title: Track and hold circuit

Description:
BACKGROUND OF THE INVENTION 
     The present invention is a track and hold circuit for use in conjunction with electrical measuring equipment, such as multimeters. 
     A wide variety of electronic equipment in use today uses or generates pulses to activate or deactivate other circuitry or mechanisms. In many cases, it is important that the pulse have certain characteristics, such as a particular amplitude and width. In the field, service personnel have generally tested for the presence of such pulses by looking on an analog meter for a &#34;tick&#34; in the measured quantity (a slight dip or rise on the pointer). Such a technique is unreliable and inaccurate, and gives no information about pulse characteristics. Without an oscilloscope or other expensive and bulky instrument, the characteristics of the pulse remain essentially unkown. 
     Accordingly, the principal object of the present invention is to provide a device to adapt a multimeter to measure pulse profile. 
     It is a further object to provide a track and hold capability at minimum power consumption so that essentially shelf-life of an ordinary 9V battery will be achieved, i.e. current &lt;0.1 milliamper. 
     SUMMARY OF THE INVENTION 
     These and other objects are achieved by providing an input circuit for receiving an input signal, a storage device connected to the input circuit for storing a signal corresponding to the instantaneous value of the amplitude of a pulse applied to the input circuit, an output circuit receiving the output of the storage device, a pulse detector for detecting a pulse, and a switching circuit connected to the pulse detector to isolate the storage device from the input so that the output signal represents the amplitude of the pulse. In the preferred embodiment the pulse detector is connected to monitor the output circuit. The preferred embodiment also includes a delay circuit for interposing a delay of selectable duration prior to activating the switching circuit and means for selecting the duration of such delay. When a delay of zero duration is selected, the signal on the storage device corresponds to the initial pulse amplitude. When a delay of larger duration is selected, the signal corresponding to initial pulse amplitude will have passed from the storage device to the output circuit when the switching circuit is activated; the signal on the storage device when the switching circuit is activated corresponds to the pulse amplitude at the selected delay time after the leading edge. Hence, the pulse amplitude at any position from the leading edge forward can be isolated so that the entire pulse profile may be measured. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects, features and advantages of the present invention will be more apparent from the following description which refers to the accompanying drawings, wherein: 
     FIG. 1 is a block diagram showing the major operating components of the track and hold system according to the present invention; 
     FIG. 2 are timing diagrams of various representative signals occurring in the apparatus of FIG. 1; and 
     FIG. 3(a) is a more detailed circuit diagram of the apparatus shown in FIG. 1, further including a bypass switch to bypass the delay circuit 18 shown in FIG. 1 and FIG. 3(b) is a circuit diagram of a power supply of FIG. 3(a). 
    
    
     DESCRIPTION OF A PREFERRED EMBODIMENT 
     Referring to FIG. 1, an input terminal 10 receives an unknown analog signal and applies such signal through the voltage divider formed by resistors R 1  and R 2  to the input of buffer amplifier A 1 . The output of amplifier A 1  is applied through a normally closed switch S 1  to a first side of capacitor C 1 , the second side of which is grounded. Capacitor C 1  is driven by the low impedance of A 1  so that the voltage across it follows the output of amplifier A 1 . A slight lag is minimized by selecting an appropriate value for capacitor C 1 . The first side of capacitor C 1  is connected to the input of output amplifier A 2 , the output of which is applied to output terminal 14. An attenuated output is taken from the junction of the voltage divider formed by resistors R 18  and R 19  and applied to output terminal 16. 
     A pulse detecting circuit 17 is connected to the output of amplifier A 2 . Pulse detection circuit 17 detects voltage rises which have a preselected rate of increase appearing at the output of amplifier A 2  and provides a trigger signal coincident with the leading edge of such a pulse. The trigger signal is applied to a delay circuit 18 which provides a delay of selectable duration after which it applies a signal to timer 20. In response thereto, timer 20 generates an output for a predetermined period which opens switch S 1 . Switch S 1  thereby isolates capacitor C 1  from the signal applied to input terminal 10. In this mode, the system provides an essentially constant amplitude output at output 14 corresponding to the last value of the analog input stored in capacitor C 1 . This mode is of sufficient duration so that a test instrument such as a multimeter can measure the initial amplitude of a pulse detected by the track and hold system. By varying the delay of circuit 18, the entire pulse profile may be measured, as set forth above. 
     Certain test instruments such as the WESTON® DMM 6000 are provided with a &#34;hold&#34; mechanism or input whereby the multimeter will hold the readout of the unknown measured immediately prior to the hold command. The &#34;hold&#34; signal can be used to prevent incorrect, partial amplitude readings being displayed by the multimeter. The preferred embodiment of the present invention provides such a hold command to the input terminal of the test instrument. Hold circuit 22 receives an input from timer 20 and applies a hold command for a predetermined period, illustratively 200 milliseconds, to hold output 24 which, in use, is connected to the hold input of the associated meter. Additionally, hold circuit 22 includes an autohold facility which is described below. 
     The operation of the circuit is best understood by refering to FIGS. 1 and 2. As shown in FIG 2(a), a signal is applied to input terminal 10 of the track and hold system. The baseline signal may be a DC voltage or a slowly varying AC voltage, or a combination thereof. This signal is applied to output terminal 14 while the system tracks the applied input signal. A pulse as shown in FIG. 2(a) appears on Capacitor C 1  as shown in FIG. 2(b). When the leading edge of that pulse on capacitor C 1  is encountered by the pulse detecting circuit 17, a trigger signal in response thereto is applied to delay circuit 18. Initially, the delay circuit 18 is set to interpose no delay, and accordingly, timer 20 is activated as soon as the leading edge of the pulse is detected. (In the more detailed circuit diagram of FIG. 3, the trigger signal is selectively applied by a switch to either delay 18 or timer 20.) In response to the trigger signal, timer 20 opens switch S 1  for a preselected period, for instance 1500  millliseconds. Accordingly, the voltage at output terminal 14 as shown in FIG. 2(c) corresponds to the initial pulse amplitude, since a voltage representative thereof remains on capacitor C 1 . This output endures for 1500 milliseconds, providing a sufficient time for a meter to take a measurement. 
     Simultaneously with the opening of switch S 1 , timer 20 applies a signal to hold circuit 22 which applies a hold command to hold output 24 for a period illustratively of 200 milliseconds as shown in FIG. 2(d). Output 24 is normally held at a voltage of one or two volts, and is dropped to zero volts for the hold signal. A second hold command is applied to hold output 24 by hold circuit 22 when switch S 1  is closed at the end of the 1500 millisecond period. The hold signal applied by hold circuit 22 to output 24 directs the associated meter to retain the previously measured quantity on its display (while continuing to measure new unknowns). Otherwise a voltage intermediate the baseline and maximum of V 14  (FIG. 2(c)), i.e., a voltage on the leading or trailing ramp, might be displayed. Such hold commands therefore ensure that the associated masuring instrument has a full measurement cycle for sensing or integrating the applied unknown and that intermediate voltages are not displayed. 
     Additionally, the preferred embodiment of the present invention includes an autohold facility of hold circuit 22 which applies a hold command of 200 milliseconds, illustratively, at the beginning of the 1500 millisecond switch opening and an openend hold command as shown in FIG. 2(e) when the switch S 1  is closed. This allows a user of the meter to reset or release the meter hold manually, which is particularly useful when the user is not in a position to read the meter at once. 
     The track and hold circuit according to the invention cooperates with a measuring instrument to determine the pulse amplitude at any desired point on a pulse and its pulse width by selecting the delay time of delay circuit 18. The delay period is measured after the pulse leading edge, so that the voltage on capacitor C 1  after the switch S 1  opens corresponds to pulse amplitude at any time of interest. As the delay is increased gradually from zero, the meter continues to measure pulse amplitude. Ultimately, the duration of the delay will be set at a time period which exceeds the duration of the pulse applied to input 10. At such time, the meter will register zero or the baseline voltage. The pulse width can be determined by observing the minimum delay time which exceeds the pulse duration. Accordingly, the entire pulse profile may be determined. 
     A further feature of the preferred embodiment track and hold circuit of the present invention is an &#34;inhibit&#34; connection 28 between hold circuit 22 and delay circuit 18. This connection is particularly useful when pulse width measurements are being taken on one of a train of pulses. Absent such an &#34;inhibit&#34; connection, inaccurate readings may be made. For example, when one pulse is detected, switch S 1  is opened illustratively for 1500 milliseconds in response thereto. When switch S 1  closes, an intermediate pulse characteristic of a subsequent pulse may be falsely interpreted by pulse detection circuit 17 as the start of a new pulse rather than an intermediate characteristic. Accordingly, an &#34;inhibit&#34; signal of 200 milliseconds is provided when switch S 1  closes to disable delay circuit 18, so that no new opening of switch S 1  can occur immediately. 
     As shown in the more detailed circuit diagram of FIG. 3(a), an input applied to input terminal 10 is connected through a voltage divider formed by series resistors R 1  and R 2  to the non-inverting input of buffer amplifier A 1 , a standard type 776 operational amplifier made by Fairchild Semiconductor, for example. The output 50 of amplifier A 1  is fed back to its inverting input by conductor 52 to provide a unity voltage gain characteristic. 
     The output 50 of amplifier A 1  is applied to the source of field effect transistor Q 1 , which constitutes switch S 1  of FIG. 1. The drain of FET Q 1  is connected to one side of a non-polar capacitor C 1 . The other side of capacitor C 1  is grounded. 
     The ungrounded side of capacitor C 1  is connected also to the non-inverting input of amplifier A 2 , also a 776 type operational amplifier. The output 60 of amplifier A 2  is fed back to its inverting input through the voltage divider formed by resistors R 4  and R 5 , with resistor R 5  connected between output 60 of amplifier A 2  and the inverting input, and R 4  connected between the inverting input and ground. The output 60 of amplifier A 2  is connected to output terminal 14. Output 60 is connected also to both the upper contact 62 of a first side of a double-pole double-throw polarity switch S 2  and to the lower contact 64 of the second side of S 2 . Both the lower contact 66 of the first side and the upper contact 68 of the second side of switch S 2  are connected to ground. The blade 70 of the first side of S 2  is connected through resistor R 7  and series capacitor C 2  to the inverting input of trigger amplifier A 3 , illustratively a 776 type operational amplifier. The blade 72 of the second side of S 2  is connected to the non-inverting input of trigger amplifier A 3 . The output 78 of amplifier A 3  is fed back to its inverting input through resistor R 8  which is connected parallel to diode D 1 , the cathode of which is connected to output 78 and the anode of which is connected to the inverting input. 
     The output 78 of amplifier A 3  is connected to the anode of diode D 2 , the cathode of which is connected by conductor 80 to the clock input C of a D-type flip-flop 180, illustratively one-half of a National Semiconductor 74C74. Resistor R 10  is connected between the cathode of diode D 2  and ground. The Q output of flip-flop 180 is connected to the anode of diode D 3 , the cathode of which is applied to the &#34;clear&#34; input &#34;Clr&#34; of flip-flop 180. Variable resistor R 11  is connected parallel to D 3 . In the preferred embodiment, resistor R 11  is a potentiometer having its shaft extending out of the casing of the track and hold system. Surrounding the shaft and on the casing is a scale calibrated in milliseconds. A suitable pointer-knob is affixed to the potentiometer so that the scale is correlated to the value of resistance R 11  and, therefore, as explained below, the delay time interposed by the delay circuit using flip-flop 180. The clear input is connected to one side of capacitor C 3 , the other side of which is connected to ground. 
     Circuit 80 is connected to one contact 82 of single-pole double-throw by-pass switch S 3 . The Q output of flip-flop 180 is connected to the second contact 84 of switch S 3 . The blade 86 of switch S 3  is connected to the clock input C of flip-flop 200, also a D-type and, conveniently, the second half of the 74C74. 
     Hence, switch S 3  operates as a selector or by-pass switch, either to connect flip-flop 180 to or isolate flip-flop 180 from flip-flop 200. Flip-flop 180 and its associated components constitute the delay circuit 18 of FIG. 1. As mentioned above, delay circuit 18 may be by-passed when only initial pulse amplitude measurement is desired. 
     Both the data input &#34;D&#34; and the preset input &#34;Pre&#34; of flip-flop 200 are connected to a positive output provided by power supply 500. The Q output of flip-flop 200 is connected to the anode of diode D 4 , the cathode of which is connected to the clear input &#34;Clr&#34; of flip-flop 200. Resistor R 12  is connected parallel to D 4 . The clear input &#34;Clr&#34; is connected also to one side of a capacitor C 4 , the other side of which is grounded. The Q output of flip-flop 200 is connected to capacitor C 5 . The other side of C 5  is connected through resistor R 13  to ground. The junction of C 5  and R 13  is connected to the anode of diode D 5 , the cathode of which is connected to a point 90. Point 90 is connected through resistor R 14  to ground. 
     Similarly, the Q output of flip-flop 200 is connected to capacitor C 6 , the other side of which is connected through resistor R 15  to ground. The junction of C 6  and R 15  is connected to the anode of diode D 6 , the cathode of which is connected to point 90. 
     Point 90 is connected to the clock input &#34;C&#34; of the &#34;hold&#34; flip-flop 220, the data input &#34;D&#34; and the preset input &#34;Pre&#34; of which are connected to the positive output of power supply 500. The Q output of flip-flop 220 is connected to the anode of diode D 7 , the cathode of which is connected to the clear input &#34;Clr&#34; of flip-flop 220. Resistor R 16  is connected parallel to diode D 8 . A capacitor C 7  is grounded at one side, and connected at the other side to the clear input &#34;Clr&#34; of flip-flop 220. The Q output of flip-flop 220 is connected to the data input &#34;D&#34; of delay flip-flop 180 and to the cathode of diode D 8 , the anode of which is connected to hold output 24. 
     An &#34;autohold&#34; flip-flop 240 has its clock input &#34;C&#34; connected to the Q output of timer flip-flop 200. Both the preset input &#34;Pre&#34; and the data input &#34;D&#34; of autohold flip-flop 240 are connected to the positive output of power supply 500. The Q output of flip-flop 240 is connected to the cathode of a diode D 9 , the anode of which is connected to one contact of a single-pole single-throw switch S 4  used to activate the &#34;autohold&#34; circuit. The second contact of S 4  is connected to hold output terminal 24. The clear input &#34;Clr&#34; of flip-flop 240 is connected through resistor R 17  to the positive output of power supply 500. Also, the clear input &#34;Clr&#34; is connected to one contact of momentary contact reset switch S 5 , the other side of which is grounded. 
     The Q output of timer flip-flop 200 is connected to the anode of a diode D 10 , the cathode of which is connected to the gate of FET Q 1 . 
     FIG. 3(b) shows a power supply 500 suitable for use with the circuit of FIG. 3(a). Preferably the power supply used will operate from a single 9 volt dry cell, so the unit will be wholly portable. Power supply 500 provides positive and negative outputs of ±4.5 volts. 
     Component values which have been found to be suitable for the circuit of FIG. 3(a) are provided in the following list: 
     
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R.sub.1 976.KΩ R.sub.10   22.MΩ                               
R.sub.2 24.9KΩ R.sub.11   2.MΩ                                
R.sub.3 1.KΩ   R.sub.12 -R.sub.17                                   
                                22.MΩ                               
R.sub.4 249.KΩ R.sub.18   1.13MΩ                              
R.sub.5 1.MΩ   R.sub.19   11.5MΩ                              
R.sub.6 88.MΩ  R.sub.20   7.32MΩ                              
R.sub.7 48.7KΩ R.sub.21   7.32Ω                               
R.sub.8 22.MΩ  R.sub.22   22.MΩ                               
R.sub.9 1.MΩ                                                        
C.sub.1 .18μf     C.sub.7    .0056μf                                
C.sub.2 470.pf       C.sub.8    .018μf                                 
C.sub.3 .18μf     C.sub.9    .018μf                                 
C.sub.4 .082μf    C.sub.10   6.9μf                                  
C.sub.5 .0047μf   C.sub.11   6.8μf                                  
C.sub.6 .0047μf                                                        
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     D 1  -d 9  1n914 type 
     A 1  -a 4  776 type 
     Q 1  p 1087e p-channel FET 
     The circuit of FIG. 3(a) operates as follows. Unity gain amplifier A 1  provides current amplification for the attenuated input signal and applies it to capacitor C 1  through normally conducting FET Q 1  to charge capacitor C 1  to the signal voltage. Amplifier A 2  amplifies the signal on capacitor C 1  and applies it to output terminal 14. Resistances R 1 , R 2 , R 4  and R 5  are preselected so that the voltage at output 14 is attenuated by a factor of 10 from the input signal. This enables the track and hold system to operate on a wider range of signals while using a single 9 volt dry cell. Conveniently, resistors R 18  and R 19  are preselected so that the voltage at output 16 is attenuated by a factor of 1000 from the input signal, so that a millivolt scale can be used on an associated meter to provide full voltage readings. 
     The leading edge of a pulse at the output 60 of amplifier A 2  is detected by the AC pulse amplifier including trigger amplifier A 3 . The design parameters, including amplification factor and the size of input capacitor C 2 , taken in conjunction with the trigger threshold voltage of flip-flop 180 or 200, determine what input risetime characteristics constitute a pulse. The position of trigger polarity switch S 2  determines whether the AC amplifier incorporating amplifier A 3  will produce a positive output at the anode of diode D 2  for a positive input signal at amplifier A 2  or whether the positive A 3  output will be produced for a negative signal at amplifier A 2 . Switch S 2  is manually selectable in the illustrated embodiment of the invention. Diode D 2  passes unipolar positive pulses to the clock input of flip-flop 180 or 200, depending on the position of S 3 . Diode D 2  reduces the stress on the flip-flop by excluding negative pulses, and the diode drop maximizes the positive baseline conditions while maintaining proper circuit operation. The values given for this illustrative embodiment will produce an appropriate activation signal for a one volt input signal excursion at input 10 with a risetime faster than 2 milliseconds. 
     The operation of the delay timing circuit including flip-flop 180 proceeds as follows. Initially the clock input C is low and the data input D is high, the Q output and the clear input &#34;Clr&#34; are also high. When a positive pulse is applied to the clock input C, the flip-flop 180 stores the D value as Q so that Q becomes high and Q goes low. This condition presists even after the positive input at C has disappeared. When Q goes low, capacitor C 3  is gradually discharged through selectable resistance R 11 . At some time the voltage applied to the clear input by capacitor C 3  causes Q to reset to the zero or low state and Q to change to the high state, and the circuit can then be retriggered. This time may be read from the scale surrounding the R 11  potentiometer shaft. Diode D 3  reduces the retrigger set up time by quickly charging C 3 . 
     In the position shown in FIG. 3(a), by-pass switch S 3  connects the Q output of flip-flop 180 to the clock input &#34;C&#34; of timer flip-flop 200. The low to high return of the Q output of flip-flop 180 clocks flip-flop 200. Since &#34;D&#34; and &#34;Pre&#34; are both high, the Q output goes high and the Q output goes low. As a first consequence, FET Q 1  is turned off and disconnects capacitor C 1  from any new input signals. Thus, while the Q output of timer flip-flop 200 remains high the signal applied to output terminal 14 is determined by the potential stored on capacitor C 1  which is representative of the pulse amplitude after the delay period caused by delay flip-flop 180. 
     Also, when timer flip-flop 200 is clocked, the voltage rise at its Q output is coupled through capacitor C 6  and diode D 6  to clock hold flip-flop 220. Hence, the Q output of flip-flop 220 goes low, causing the normally high output at 24 to go low. The duration of this hold command is set by the discharge time of capacitor C 7  through resistor R 16 , illustratively 200 milliseconds. 
     Flip-flop 200 functions like delay flip-flop 180 and after a time illustratively 1500 milliseconds the voltage applied to the clear input by capacitor C 4  causes its Q output thereof to return to low, and, correspondingly, its Q output to return to high. One consequence of this is the FET Q 1  will close (turn on), so that new input signals can pass to C 1 . Another consequence is that the transition of Q from low to high causes point 90 to go high again. Since the Q output is coupled through capacitor C 5  and diode D 5  to the clock input of hold flip-flop 220, the voltage rise again clocks flip-flop 220. Hence, a second &#34;hold&#34; command for 200 milliseconds is applied to hold output 24, as described above. 
     The Q output of flip-flop 220 is connected to the &#34;D&#34; of flip-flop 180. If the data input D is held in the low state, the presence of a positive pulse at C does not cause the delay circuit to operate. Hence, flip-flop 180 is disabled for the duration of the hold command, so that timer flip-flop 200 cannot be clocked during that hold command. As a result, intermediate characteristics of pulses reaching trigger amplifier A 3  when the FET Q 1  is closed can not open the FET even if A 3  is triggered. 
     Finally, an autohold flip-flop 240 is engaged when switch S 4  is closed. The return of the Q output of timer flip-flop 200 from low to high will clock flip-flop 240, providing an open-end hold command at output 24 until switch S 5  is closed to ground the clear input. 
     It will be appreciated that the track and hold circuit of present invention achieves the aforementioned objectives and provides an extremely useful result. This track and hold circuit used in conjunction with a multimeter is fully capable of measuring pulse amplitude at any position on a pulse, as well as pulse duration. Moreover as a result of taking the trigger after the storage device, filtering against noise sources is achieved for reliable operation. 
     It will be apparent to those skilled in the art that various modifications of the present invention are possible. For example, modifications to the trigger amplifier can be made to accommodate a wide range of pulse recognition or level change conditions. The functions of the delay and timer circuits could be implemented by more conventional single shot multivibrator integrated circuits. However, the embodiment shown herein provides very low power consumption, an important feature for portable, battery-powered devices.