Patent Publication Number: US-10770565-B2

Title: Memory structure and manufacturing method thereof

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to a semiconductor structure and a manufacturing method thereof, and particularly relates to a memory structure and a manufacturing method thereof. 
     Description of Related Art 
     In the process of memory structure, it is difficult to accurately form a salicide block (SAB) layer between the memory cell structure and the select gate structure by a patterning process. As a result, it is difficult to control the formation position of the subsequently formed metal silicide, thereby causing a decrease in the yield and reliability of the memory device. 
     SUMMARY OF THE INVENTION 
     The invention provides a memory structure and a manufacturing method thereof which can accurately control the formation position of the subsequently formed metal silicide. 
     The invention provides a memory structure, which includes a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer. The first gate structure includes a first gate and a charge storage layer. The first gate is disposed on the substrate. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate at one side of the first gate structure. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate. 
     According to an embodiment of the invention, in the memory structure, a height of the first spacer may be higher than the height of the second gate. 
     According to an embodiment of the invention, in the memory structure, the first gate structure may further include a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed between the charge storage layer and the substrate. The second dielectric layer is disposed between the first gate and the charge storage layer. 
     According to an embodiment of the invention, in the memory structure, the second gate structure may further include a third dielectric layer. The third dielectric layer is disposed between the second gate and the substrate. 
     According to an embodiment of the invention, the memory structure may further include a fourth spacer. The fourth spacer is disposed on a sidewall of the second gate away from the first gate structure. 
     According to an embodiment of the invention, the memory structure may further include a fifth spacer. The fifth spacer is disposed on the second spacer. 
     According to an embodiment of the invention, the memory structure may further include a sixth spacer. The sixth spacer is disposed on the third spacer. 
     According to an embodiment of the invention, the memory structure may further include a first metal silicide layer, a second metal silicide layer, a third metal silicide layer, and a fourth metal silicide layer. The first metal silicide layer is disposed on the first gate. The second metal silicide layer is disposed on the top surface of the second gate exposed by the third spacer. The third metal silicide layer is disposed on the substrate at one side of the first gate structure. The fourth metal silicide layer disposed on the substrate at the other side of the first gate structure. 
     The invention provides a method of manufacturing a memory structure, which includes the following steps. A first gate structure is formed on a substrate. The first gate structure includes a first gate and a charge storage layer. The first gate is disposed on the substrate. The charge storage layer is disposed between the first gate and the substrate. A second gate structure is formed on the substrate at one side of the first gate structure. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. A first spacer and a second spacer are respectively formed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. A third spacer is formed on a sidewall of the first spacer. The third spacer covers a portion of a top surface of the second gate. 
     According to an embodiment of the invention, in the method of manufacturing the memory structure, a height of the first spacer may be higher than the height of the second gate. 
     According to an embodiment of the invention, the method of manufacturing the memory structure may further include forming a fourth spacer on a sidewall of the second gate away from the first gate structure. 
     According to an embodiment of the invention, the method of manufacturing the memory structure may further include forming a fifth spacer on the second spacer. 
     According to an embodiment of the invention, the method of manufacturing the memory structure may further include forming a sixth spacer on the third spacer. 
     According to an embodiment of the invention, in the method of manufacturing the memory structure, a method of forming the third spacer may include the following steps. A second gate material layer covering the first gate structure is formed. A portion of the second gate material layer is removed until a top surface of the second gate material layer is lower than a top surface of the first gate. A spacer material layer is conformally formed on the first gate structure and the second gate material layer. An etch-back process is performed on the spacer material layer to form the third spacer on the first spacer and a seventh spacer on the second spacer. The seventh spacer is removed. 
     According to an embodiment of the invention, in the method of manufacturing the memory structure, a method of removing the portion of the second gate material layer may include an etch-back method or a combination of a chemical mechanical polishing (CMP) method and the etch-back method. 
     According to an embodiment of the invention, in the method of manufacturing the memory structure, a method of forming the second gate may include patterning the second gate material layer. 
     According to an embodiment of the invention, in the method of manufacturing the memory structure, the first gate structure may further include a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed between the charge storage layer and the substrate. The second dielectric layer is disposed between the first gate and the charge storage layer. 
     According to an embodiment of the invention, in the method of manufacturing the memory structure, the first gate structure may further include a cap layer. The cap layer is disposed on the first gate. 
     According to an embodiment of the invention, the method of manufacturing the memory structure may further include the following steps. A first metal silicide layer is formed on the first gate. The cap layer is removed before the first metal silicide layer is formed. A second metal silicide layer is formed on the top surface of the second gate exposed by the third spacer. A third metal silicide layer is formed on the substrate at one side of the first gate structure. A fourth metal silicide layer is formed on the substrate at the other side of the first gate structure. 
     According to an embodiment of the invention, in the method of manufacturing the memory structure, the second gate structure may further include a third dielectric layer. The third dielectric layer is disposed between the second gate and the substrate. 
     Based on the above description, in the memory structure and the manufacturing method thereof, the third spacer is disposed on the sidewall of the first spacer and covers a portion of the top surface of the second gate. Therefore, the formation position of the subsequently formed metal silicide can be accurately controlled by the third spacer, and the yield and reliability of the memory device can be improved. 
     In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
         FIG. 1A  to  FIG. 1H  are schematic cross-sectional views illustrating a manufacturing method of a memory structure according to an embodiment of the invention. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
       FIG. 1A  to  FIG. 1H  are schematic cross-sectional views illustrating a manufacturing method of a memory structure according to an embodiment of the invention. 
     Referring to  FIG. 1A , a gate structure  102  is formed on a substrate  100 . The substrate  100  may be a semiconductor substrate, such as a silicon substrate. The gate structure  102  may be used as a memory cell structure. 
     The gate structure  102  includes a gate  104  and a charge storage layer  106 . The gate structure  102  may further include at least one of a dielectric layer  108 , a dielectric layer  110 , and a cap layer  112 . The gate  104  is disposed on the substrate  100 . The material of the gate  104  is, for example, doped polysilicon. The charge storage layer  106  is disposed between the gate  104  and the substrate  100 . The charge storage layer  106  may be a charge trapping layer or a floating gate. In the present embodiment, the charge storage layer  106  is exemplified by the charge trapping layer, but the invention is not limited thereto. The material of the charge trapping layer is, for example, silicon nitride. The material of the floating gate is, for example, doped polysilicon. The dielectric layer  108  is disposed between the charge storage layer  106  and the substrate  100 . The dielectric layer  110  is disposed between the gate  104  and the charge storage layer  106 . The cap layer  112  is disposed on the gate  104 . The material of the dielectric layer  108 , the dielectric layer  110 , and the cap layer  112  is, for example, silicon oxide. The method of forming the gate structure  102  is, for example, a combination of a deposition method, a lithography method and an etching method. 
     A spacer  114  and a spacer  116  are respectively formed on one sidewall and the other sidewall of the gate structure  102 . The spacer  114  and the spacer  116  may be respectively a single-layer structure or a multilayer structure. The multilayer structure is, for example, a composite layer having a silicon oxide layer/a silicon nitride layer/a silicon oxide layer (ONO). The single-layer structure is, for example, a silicon oxide layer. The method of forming the spacer  114  and the spacer  116  may include following steps. A spacer material layer (not shown) is conformally formed on the gate structure  102 , and then an etch-back process is performed on the spacer material layer to form the spacer  114  and the spacer  116 . 
     A dielectric layer  118  may be formed on the substrate exposed by the gate structure  102 , the spacer  114 , and the spacer  116 . The material of the dielectric layer  118  is, for example, silicon oxide. The method of forming the dielectric layer  118  is, for example, a thermal oxidation method or a chemical vapor deposition (CVD) method. 
     Referring to  FIG. 1B , a gate material layer  120  covering the gate structure  102  is formed. The material of the gate material layer  120  is, for example, doped polysilicon. The method of forming the gate material layer  120  is, for example, a CVD method. 
     Referring to  FIG. 1C , a portion of the gate material layer  120  is removed until the top surface of the gate material layer  120  is lower than the top surface of the gate  104 . A method of removing the portion of the gate material layer  120  may include an etch-back method or a combination of a chemical mechanical polishing (CMP) method and the etch-back method. For example, a CMP process is performed on the gate material layer  120 , and then an etch-back process is performed on the gate material layer  120 . 
     A spacer material layer  122  is conformally formed on the gate structure  102  and the gate material layer  120 . The material of the spacer material layer  122  is, for example, silicon nitride. The method of forming the spacer material layer  122  is, for example, a CVD method 
     Referring to  FIG. 1D , an etch-back process is performed on the spacer material layer  122  to form a spacer  122   a  on the spacer  114  and a spacer  122   b  on the spacer  116 . In the present embodiment, the spacer  122   a  is formed on the sidewall of spacer  114 . The etch-back process is, for example, a dry etching process. 
     Referring to  FIG. 1E , a patterned photoresist layer  124  may be formed, wherein the patterned photoresist layer  124  may cover the spacer  122   a  and a portion of the gate material layer  120  at one side of the gate structure  102 . The patterned photoresist layer  124  may further cover the cap layer  112  and the spacer  114 . The method of forming the patterned photoresist layer  124  is, for example, a lithography method. 
     The spacer  122   b  exposed by the patterned photoresist layer  124  is removed. The method of removing the spacer  122   b  is, for example, a wet etching method. 
     A portion of the gate material layer  120  exposed by the patterned photoresist layer  124  is removed. The method of removing the portion of the gate material layer  120  is, for example, a dry etching method. 
     Referring to  FIG. 1F , the patterned photoresist layer  124  is removed. The method of removing the patterned photoresist layer  124  is, for example, a dry stripping method or a wet stripping method. 
     A patterned photoresist layer  126  is formed, wherein the patterned photoresist layer  126  may cover a portion of the gate material layer  120 . The patterned photoresist layer  126  may further cover the spacer  122   a , the spacer  114 , the cap layer  112 , the spacer  116 , and the dielectric layer  118 . The method of forming the patterned photoresist layer  126  is, for example, a lithography method. 
     The gate material layer  120  exposed by the patterned photoresist layer  126  is removed to form a gate  120   a  at one side of the gate structure  102 . The height of the gate  104  is higher than the height of the gate  120   a . The height of the spacer  114  may be higher than the height of the gate  120   a . The spacer  122   a  covers a portion of a top surface of the gate  120   a . The method of removing gate material layer  120  exposed by the patterned photoresist layer  126  is, for example, a dry etching method. The method of forming the gate  120   a  may include patterning the gate material layer  120  by the abovementioned method, but the invention is not limited thereto. 
     Referring to  FIG. 1G , the patterned photoresist layer  126  is removed. The method of removing the patterned photoresist layer  126  is, for example, a dry stripping method or a wet stripping method. 
     A spacer  128  may be formed on a sidewall of the gate  120   a  away from the gate structure  102 . A spacer  130  may be formed on the spacer  116 . A spacer  132  may be formed on the spacer  122   a . The material of the spacer  128 , the spacer  130 , and spacer  132  is, for example, silicon nitride. The method of forming the spacer  128 , the spacer  130  and spacer  132  may include the following steps. A spacer material layer (not shown) is conformally formed on the gate  120   a , the spacer  116 , the spacer  122   a , and the cap layer  112 , and then an etch-back process is performed on the spacer material layer to form the spacer  128 , the spacer  130 , and spacer  132 . In the present embodiment, the spacer  128 , the spacer  130 , and spacer  132  may be simultaneously formed by the same process, but the invention is not limited thereof. 
     Referring to  FIG. 1H , the cap layer  112  may be removed to exposed the gate  104 . A portion of the dielectric layer  118  not covered by the gate  120   a , the spacer  128 , and the spacer  130  may be removed to expose a portion of the substrate  100  and form a dielectric layer  118   a , wherein the dielectric layer  118   a  is located between the gate  120   a  and the substrate  100 . The cap layer  112  and the portion of the dielectric layer  118  may be simultaneously or separately removed by performing an etching process, but the invention is not limited thereto. By the abovementioned method, a gate structure  134  is formed on the substrate  100  at one side of the gate structure  102 . The gate structure  134  includes a gate  120   a  and may further include a dielectric layer  118   a . The dielectric layer  118   a  is disposed between the gate  120   a  and the substrate  100 . The spacer  114  is located between the gate structure  102  and the gate structure  134 . The method of forming the gate structure  134  is exemplified by the abovementioned method, but the invention is not limited thereto. 
     A metal silicide layer  136  is formed on the gate  104 . A metal silicide layer  138  is formed on the top surface of the gate  120   a  exposed by the spacer  122   a . A metal silicide layer  140  is formed on the substrate  100  at one side of the gate structure  102 . A metal silicide layer  142  is formed on the substrate  100  at the other side of the gate structure  102 . The material of the metal silicide layer  136 , metal silicide layer  138 , metal silicide layer  140 , and the metal silicide layer  142  is, for example, cobalt silicide or nickel silicide. The method of forming material of the metal silicide layer  136 , metal silicide layer  138 , metal silicide layer  140 , and the metal silicide layer  142  is, for example, performing a salicidation process. 
     In the following, the memory structure  10  of the above embodiments is described with  FIG. 1H . 
     Referring to  FIG. 1H , in one embodiment, the memory structure  10  includes a substrate  100 , a gate structure  102 , a gate structure  134 , a spacer  114 , a spacer  116 , and a spacer  122   a . Based on product design requirement, one or more desired doped regions (not shown) may be formed in the substrate  100 . The gate structure  102  includes a gate  104  and a charge storage layer  106 . The gate  104  is disposed on the substrate  100 . The charge storage layer  106  is disposed between the gate  104  and the substrate  100 . The gate structure  102  may further include a dielectric layer  108  and a dielectric layer  110 . The dielectric layer  108  is disposed between the charge storage layer  106  and the substrate  100 . The dielectric layer  110  is disposed between the gate  104  and the charge storage layer  106 . The gate structure  134  is disposed on the substrate  100  at one side of the gate structure  102 . The gate structure  134  includes a gate  120   a  and may further include a dielectric layer  118   a . The dielectric layer  118   a  is disposed between the gate  120   a  and the substrate  100 . In two adjacent memory structures  10 , two gate structures  134  may be located between two adjacent gate structure  102 . The height of the gate  104  is higher than a height of the gate  120   a . The spacer  114  and the spacer  116  are respectively disposed on one sidewall and the other sidewall of the gate structure  102 . The spacer  114  is located between the gate structure  102  and the gate structure  134 . The spacer  122   a  is disposed on a sidewall of the spacer  114  and covers a portion of a top surface of the gate  120   a . The height of the spacer  114  may be higher than the height of the gate  120   a.    
     The memory structure  10  include may further include at least one of a spacer  128 , a spacer  130 , a spacer  132 , a metal silicide layer  136 , a metal silicide layer  138 , a metal silicide layer  140 , and a metal silicide layer  142 . The spacer  128  is disposed on a sidewall of the gate  120   a  away from the gate structure  102 . The spacer  130  is disposed on the spacer  116 . The spacer  132  is disposed on the spacer  122   a . The metal silicide layer  136  is disposed on the gate  104 . The metal silicide layer  138  is disposed on the top surface of the gate  120   a  exposed by the spacer  122   a  and the spacer  132 . The metal silicide layer  140  is disposed on the substrate  100  at one side of the gate structure  102 . The metal silicide layer  142  disposed on the substrate  100  at the other side of the gate structure  102 . 
     In addition, the material, the arrangement, the forming method, the effect, and the like of each component in the memory structure  10  of  FIG. 1H  are described in detail in the embodiments above and are not repeated herein. 
     Based on the above description, in the memory structure  10  and the manufacturing method thereof, the spacer  122   a  is disposed on the sidewall of the spacer  114  and covers a portion of the top surface of the gate  120   a . Therefore, the formation position of the subsequently formed metal silicide  138  can be accurately controlled by the spacer  122   a , and the yield and reliability of the memory device can be improved. 
     In summary, in the memory structure of the aforementioned embodiments and the method of manufacturing the same, the metal silicide can be accurately formed on the predetermined position by the spacer. Therefore, the yield and reliability of the memory device can be improved. 
     Although the invention has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the invention. Accordingly, the scope of the invention is defined by the attached claims not by the above detailed descriptions.