Patent Publication Number: US-11664218-B2

Title: Semiconductor device and method

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application is a continuation of U.S. patent application Ser. No. 16/848,356, filed on Apr. 14, 2020, entitled “Semiconductor Device and Method,” which is a division of U.S. patent application Ser. No. 16/050,800, filed on Jul. 31, 2018, entitled “Semiconductor Device and Method,” now U.S. Pat. No. 10,636,651 issued on Apr. 28, 2020, which is a division of U.S. patent application Ser. No. 15/151,100, filed on May 10, 2016, entitled “Semiconductor Device and Method,” now U.S. Pat. No. 10,109,477 issued on Oct. 23, 2018, which application claims priority to and the benefit of U.S. Provisional Application No. 62/273,628, filed on Dec. 31, 2015, entitled “Tunable Gap Ultra-Thin-Body Transistor Based on a Topological Insulator,” which applications are hereby incorporated herein by reference in their entirety. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. 
     Transistors are circuit components or elements that are often formed on semiconductor devices. Many transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, depending on the circuit design. Improvements in transistor designs are desired. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    illustrates a formation of a channel layer, a gate dielectric layer, and a gate electrode layer in accordance with some embodiments. 
         FIGS.  2 A- 2 C  illustrate band gaps of topological insulators in accordance with some embodiments. 
         FIG.  3    illustrates a patterning of the channel layer, the gate dielectric layer, and the gate electrode layer in accordance with some embodiments. 
         FIGS.  4 A- 4 B  illustrate a formation of source/drain regions in accordance with some embodiments. 
         FIGS.  5 A- 5 C  illustrate a formation of the channel and source/drain regions in accordance with some embodiments. 
         FIGS.  6 A- 6 B  illustrate a formation of the channel on the gate dielectric in accordance with some embodiments. 
         FIG.  7    illustrates a formation of a second channel layer, a second gate dielectric layer, and a second gate electrode in accordance with some embodiments. 
         FIGS.  8 A- 8 B  illustrate a formation of source/drain regions in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Embodiments will now be described with respect to a tunable gap ultra-thin body transistor which is based on a topological insulator. However, the embodiments described herein may be applied in any suitable application. 
     With reference now to  FIG.  1   , there is illustrated a substrate  101 , a first channel layer  103 , a first gate dielectric layer  105 , and a first gate electrode layer  107 . In an embodiment the substrate  101  may comprise bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that may be used include sapphire, multi-layered substrates, gradient substrates, or hybrid orientation substrates. Any suitable substrate may be utilized. 
     The first channel layer  103  may be formed over the substrate  101  and will be used to form a first channel  305  (not illustrated in  FIG.  1    but illustrated and discussed below with respect to  FIG.  3   ) for a single-gate transistor  400  (also not illustrated in  FIG.  1    as being completed but illustrated and described below with respect to  FIG.  4 A ). In an embodiment the first channel layer  103  may be a topological insulator material wherein the material has a bulk structure with an insulating or semiconducting (gapped) structure as well as conducting (gapless) edges or surfaces due to non-trivial topology of a band structure caused by interactions between spin and orbital degrees of freedom. In particular embodiments in which the first channel layer  103  is a topological insulating material, the first channel layer  103  may be a material such as Bi 2 Se 3 , Bi 2 Te 3 , Sb 2 Te 3 , or tetradymite-like ternary compounds with a structure such as M 2 X 2 Y such as Bi 2 Te 2 Se, Bi 2 Te 2 S, Bi 2 Se 2 S, Sb 2 Te 2 Se, Sb 2 Te 2 S, or the like. However, any suitable topological insulator may be utilized. 
     Additionally, with respect to the materials utilized for the first channel layer  103 , the material of the first channel layer  103  will have a critical thickness T c , wherein the thickness of the material of the first channel layer  103  will determine the properties of the material of the first channel layer  103  and the properties of the material for the first channel layer  103  will change as the thickness of the material for the first channel layer  103  changes. For example, in a particular embodiment in which Bi 2 Se 3  is utilized as the material for the first channel layer  103 , the Bi 2 Se 3  will have a critical thickness of six quintuple layers (e.g., layers of Se—Bi—Se—Bi—Se), below which the Bi 2 Se 3  will have properties of a semiconductor material and above which the Bi 2 Se 3  will have properties of a topological insulator which has bulk insulator properties along with conductive surface states. 
       FIG.  2 A  helps to illustrate this change and separation of properties based upon thicknesses. When the thickness of a Bi 2 Se 3  film is reduced to several nanometres, the surface-state wavefunctions from the two surfaces of Bi 2 Se 3  film are interfered and overlapped. Therefore, a gap opens and no surface state exists. As illustrated in  FIG.  2 A , a single quintuple layer (1QL) of Bi 2 Se 3  has an energy band gap that does not allow for the conduction of electricity and causes the Bi 2 Se 3  to have the properties of a semiconductor material. However, as illustrated in  FIG.  2 B , as the number of layers of Bi 2 Se 3  increases, the surface states can very well exist when the critical thickness of Bi 2 Se 3  has been reached (which for Bi 2 Se 3  is about 6 quintuple layers), the band gap is bridged, and the Bi 2 Se 3  will have the properties of a topological insulator, such that the material is an insulator but which has conductive surface states such that electricity will flow along the surface of the topological insulator. As such, the thickness of the material utilized for the first channel layer  103  determines its properties, and control of this thickness will also control the properties that are obtained from the formation of the first channel layer  103 . 
       FIG.  2 C  helps to illustrate this change in properties based upon the thickness of the material of the first channel layer  103  in another fashion. In particular,  FIG.  2 C  illustrates the bandgap of each number of quintuple layers from 1 quintuple layer of Bi 2 Se 3  to 7 quintuple layers of Bi 2 Se 3  and illustrates that at 6 quintuple layers the bandgap reaches zero and the Bi 2 Se 3  has the properties of a topological insulator with metallic surface states that allows for the flow of electricity. However, below 6 quintuple layers, there is a non-zero bandgap which causes the Bi 2 Se 3  to have the properties of a semiconductor material. 
     In order to function appropriately as the first channel  305 , the first channel layer  103  is formed to have a first thickness T 1  that is below the critical thickness T c  (shown in relative located in  FIG.  1   ) of the material used for the first channel layer  103 . In a particular embodiment in which the first channel layer  103  is Bi 2 Se 3 , Bi 2 Te 3 , or Sb 2 Te 3 , the first channel layer  103  is formed to have a thickness of less than 6 quintuple layers, such as having a thickness of 1 quintuple layer, or about 1 nm. However, any suitable thickness may be utilized depending upon the properties of the topological insulator material being utilized. By forming the first channel layer  103  to have the first thickness T 1  below the critical thickness T c  of the material chosen for the first channel layer  103 , the first channel layer  103  will have a material with semiconductor properties and not conductive properties. 
     The first channel layer  103  may be formed using a process such as an epitaxial growth process. In a particular embodiment in which the first channel layer  103  is formed from a material such as Bi 2 Se 3 , the epitaxial growth process may proceed at a temperature of between about 100° C. and about 500° C., and at a pressure less than about 2.0×10 −9  Torr, using any suitable source or sources for bismuth and selenium, such as evaporated high-purity Bi (99.99%) and Se (99.99%). However, any suitable growth or deposition process, such as an atomic layer deposition process or the like, may also be used. 
     Additionally, the epitaxial growth process may be continued for a time that is sufficient to grow the first channel layer  103  to the first thickness T 1  without growing the first channel layer  103  to a thickness greater than the critical thickness T c . In an embodiment in which the deposition rate of Bi 2 Se 3  films is about 0.67 angstrom/min, the epitaxial growth process may be performed for a first time of between about 70 sec and about 270 sec. However, any suitable time may be utilized. 
     Once the first channel layer  103  has been formed, a first gate dielectric layer  105  and a first gate electrode layer  107  may be formed over the first channel layer  103 . The first gate dielectric layer  105  may be formed from a high permittivity (high-k) material (e.g., with a relative permittivity greater than about 5) such as aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), lanthanum oxide (La 2 O 3 ), or zirconium oxide (ZrO 2 ), or combinations thereof, with an equivalent oxide thickness of about 0.5 nm to about 2 nm. Additionally, any combination of silicon dioxide, silicon oxynitride, and/or high-k materials may also be used for the first gate dielectric layer  105 . The first gate dielectric layer  105  may be formed using a process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like. 
     The first gate electrode layer  107  may comprise a conductive material and may be selected from a group comprising of gold, titanium, platinum, aluminum, polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. Examples of metallic nitrides include tungsten nitride, molybdenum nitride, titanium nitride, and tantalum nitride, or their combinations. Examples of metallic silicide include tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, or their combinations. Examples of metallic oxides include ruthenium oxide, indium tin oxide, or their combinations. Examples of other metals that may be used include tantalum, tungsten, copper, molybdenum, nickel, etc. Any suitable material may be used to form the first gate electrode layer  107 . 
     The first gate electrode layer  107  may be deposited by sputter deposition, chemical vapor deposition (CVD), or other techniques known and used in the art for depositing conductive materials. The thickness of the first gate electrode layer  107  may be in the range of about 200 angstroms to about 4,000 angstroms. Dopants may or may not be introduced into the first gate electrode layer  107  at this point. Dopants may be introduced, for example, by molecular doping techniques thru charge transfer. 
       FIG.  3    illustrates that, once the first gate electrode layer  107  has been formed, the first gate electrode layer  107  may be patterned to form a first gate electrode  301 . The first gate electrode  301  may be formed by depositing and patterning a first gate mask (not illustrated in  FIG.  3   ) on the first gate electrode layer  107  using, for example, deposition and photolithography techniques known in the art. The first gate mask may incorporate commonly used masking materials, such as (but not limited to) photoresist material, silicon oxide, silicon oxynitride, and/or silicon nitride. Once the first gate mask has been placed, the first gate electrode layer  107  may be etched using plasma etching to form the first gate electrode  301 . In an embodiment the first gate electrode layer  107  may be patterned to have a first width W 1  of between about 7 nm and about 100 μm. 
       FIG.  3    also illustrates a patterning of the first gate dielectric layer  105  and the first channel layer  103 . In an embodiment the patterning of the first gate dielectric layer  105  and the first channel layer  103  may be initiated by removing the first gate mask using, e.g., an ashing or other removal process, and a second gate mask may be deposited and patterned. In an embodiment the second gate mask may be deposited and patterned using, for example, deposition and photolithography techniques known in the art. The second gate mask may incorporate commonly used masking materials, such as (but not limited to) photoresist material, silicon oxide, silicon oxynitride, and/or silicon nitride. Once the second gate mask has been placed, the first gate dielectric layer  105  and the first channel layer  103  may be etched using plasma etching to form the first gate dielectric  303  and the first channel  305 . In an embodiment the first gate dielectric  303  and the first channel  305  may be patterned to have a second width W 2  of between about 7 nm and about 100 μm. 
       FIGS.  4 A- 4 B  illustrate a formation of source/drain regions  401  in contact with the first channel  305 . In an embodiment the source/drain regions  401  comprises a material with a critical thickness T c  as described herein, wherein the properties of the material used for the source/drain regions  401  are dependent at least in part upon the thickness of the material. In some embodiments the material of the source/drain regions  401  is a topological insulator and, in particular embodiments, is the same topological insulator material as the first channel  305 . For example, in an embodiment in which the first channel  305  is Bi 2 Se 3 , the source/drain regions  401  are also Bi 2 Se 3 , although any suitable material may be used. 
     However, while the first channel  305  is formed using a topological insulator with a thickness that keeps the properties of the topological insulator as a semiconductor material (e.g., below 6 quintuple layers for Bi 2 Se 3 , such as 1 quintuple layer), the source/drain regions  401  are formed using a topological insulator material with a second thickness T 2  that is greater than the critical thickness T c  of the material. By forming the material of the source/drain regions  401  to have the second thickness T 2  greater than the critical thickness T c , the material of the source/drain regions  401  will have different properties than the material of the first channel  205 , such as by having the properties of a topological insulator with bulk insulating properties as well as having surfaces with metallic behavior that allows for the conduction of electricity along the surface. In particular embodiments in which Bi 2 Se 3 , Bi 2 Te 3 , or Sb 2 Te 3  are utilized for the source/drain regions  401 , the source/drain regions  401  may be formed with the second thickness T 2  of six quintuple layers or greater, such as about 6 nm or greater. The source/drain regions  401  may be formed to have a third width W 3  of between about 7 nm and about 100 μm. 
     In an embodiment the source/drain regions  401  may be formed from similar materials and using similar processes as the first channel layer  103  (described above with respect to  FIG.  1   ). For example, the source/drain regions  401  may be formed using a process such as molecular beam epitaxial growth. However, for the process of forming the source/drain regions  401 , instead of continuing the process for the first time of between about 70 sec and about 270 sec, which would result in the first thickness T 1  below the critical thickness T c , the epitaxial growth process for the source/drain regions  401  is continued for a second time of between about 6 min and about 120 min, such that the source/drain regions  401  have the second thickness T 2  greater than the critical thickness T c . However, any suitable process may be utilized to form the source/drain regions  401 . 
       FIG.  4 B  illustrates a top-down view of the single-gate transistor  400 . As can be seen, the first gate dielectric  303  may be formed to have a first length L 1  of between about 7 nm and about 100 μm. Additionally, the source/drain regions  401  may be formed to have a second length L 2  of between about 7 nm and about 100 μm. The first gate electrode  301  may be formed to have a third length L 3  of between about 7 nm and about 100 μm. However, any suitable dimensions may be utilized. 
     By forming the first channel  305  to have the first thickness T 1  such that the first channel  305  has the properties of a semiconductor material and by also forming the source/drain regions  401  to have the second thickness T 2  such that the source/drain regions  401  have the properties of a topological insulator with a conductive surface, the same material (e.g., Bi 2 Se 3 ) can be used for both the first channel  305  as well as the source/drain regions  401  such that there is no lattice mismatch between the first channel  305  and the source/drain regions  401 . As such, the overall process may be simplified while taking advantage of the properties of the topological insulators in the formation of transistors. For example, by forming the single-gate transistor  400  with the first channel  305  and the source/drain regions  401  as described above, a normally-off topological insulator based transistor with a low contact resistance may be obtained. Additionally, because materials such as Bi 2 Se 3  have a layered crystal structure consisting of stacked Se—Bi—Se—Bi—Se quintuple layers (QLs), and since the channel thickness in some embodiments is nearly 1 QL, the short channel effects in devices that utilized these embodiments is the same as FETs based on two-dimensional materials. In other words, short-channel effects can be suppressed by reducing the gate dielectric thickness, which enhances the electrostatic control from the gate. 
       FIGS.  5 A- 5 C  illustrate an embodiment of a process that may be used to manufacture a second single-gate transistor  500  using, e.g., a topological insulator. In this embodiment the first channel layer  103  is formed on the substrate  101  as described above with respect to  FIG.  1    (e.g., an epitaxial growth process). In this embodiment, however, the first channel layer  103  is initially grown to the second thickness T 2  which is larger than the critical thickness T c  of the material chosen for the first channel layer  103 . As such, the first channel layer  103  in this embodiment is initially formed with the properties of the topological insulator, with both the bulk insulator along with the conductive surface. 
       FIG.  5 B  illustrates that, once the first channel layer  103  has been grown to the second thickness T 2 , the first channel  305  and the source/drain regions  401  are formed from the first channel layer  103  (with the separation between the first channel layer  103  and the source/drain regions  401  being illustrated by the dashed lines in  FIG.  5 B ). In an embodiment the first channel  305  and the source/drain regions  401  are formed simultaneously from the first channel layer  103  (with the second thickness T 2 ) by patterning the first channel layer  103  and reducing the thickness of the first channel layer  103  until the first channel  305  has the first thickness T 1  below the critical thickness T c  such that the first channel  305  has the properties of a semiconductor material. 
     The thickness of the first channel layer  103  may be reduced by initially placing a source/drain mask (not separately illustrated in  FIG.  5 B ) over those portions of the first channel layer  103  that are desired to be formed into the source/drain regions  401 . In an embodiment the source/drain mask may be deposited and patterned using, for example, deposition and photolithography techniques known in the art. The source/drain mask may incorporate commonly used masking materials, such as (but not limited to) photoresist material, silicon oxide, silicon oxynitride, and/or silicon nitride. Once the source/drain mask has been placed, the exposed portions of the first channel layer  103  may be etched using plasma etching to form the first channel  305  (with the thickness reduced to below the critical thickness T c ) and the source/drain regions  401  (without the thickness reduced to below the critical thickness T a ). 
       FIG.  5 C  illustrates that, once the first channel  305  and the source/drain regions  401  have been formed from the first channel layer  103 , the first gate dielectric  303  and the first gate electrode  301  may be formed over the first channel  305 . In an embodiment the first gate dielectric  303  may be formed as described above with respect to  FIGS.  1  and  3   . For example, the first gate dielectric layer  105  (not separately illustrated in  FIG.  5 C ) may be formed by initially forming a layer of material such as aluminum oxide or hafnium oxide using a process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like. By using a conformal deposition process such as atomic layer deposition, the first gate dielectric layer  105  will take on the shape of the underlying structures, forming a “U” shape between the source/drain regions  401  and over the first channel  205 . 
     Once the first gate dielectric layer  105  has been deposited, the first gate electrode layer  107  (not separately illustrated in  FIG.  5 C ) may be deposited over the first gate dielectric layer  105 . In an embodiment the first gate electrode layer  107  may be formed as described above with respect to  FIG.  1   . For example, the first gate electrode layer  107  may be deposited by depositing a conductive material such as gold, titanium, platinum, or aluminum over the dielectric material using a process such as sputtering, although any other suitable material or method of manufacture may be utilized. 
     Once the first gate dielectric layer  105  and the first gate electrode layer  107  have been formed, the first gate dielectric layer  105  and the first gate electrode layer  107  may be patterned into the first gate dielectric  303  and the first gate electrode  301 , respectively. In an embodiment the first gate dielectric layer  105  and the first gate electrode layer  107  may be patterned as described above with respect to  FIG.  3   , whereby one or more photoresists are deposited, exposed, developed, and then used as mask(s) in order to pattern the first gate dielectric layer  105  and the first gate electrode layer  107  into the desired shapes. In an embodiment the first gate electrode  301  may be patterned to a fourth width W 4  of between about 7 nm and about 100 μm, and the first gate dielectric  303  may be patterned to a fifth width W 5  of between about 7 nm and about 100 μm. 
       FIG.  6 A  illustrates another embodiment in which the first channel  305  and the source/drain regions  401  are formed over the first gate electrode  301  and the first gate dielectric  303 . In this embodiment the first gate electrode  301  and the first gate dielectric  303  are initially formed prior to the formation of the first channel  305  and the source/drain regions  401 . In an embodiment the first gate electrode  301  and the first gate dielectric  303  may be formed as described above with respect to  FIGS.  1  and  3   . For example, the first gate dielectric layer  105  and the first gate electrode layer  107  may be formed by initially forming a conductive material such as gold, titanium, platinum, or aluminum over the dielectric material using a process such as sputtering and then depositing a layer of material such as aluminum oxide, hafnium oxide, or silicon oxide using a process such as atomic layer deposition. Once the first gate dielectric layer  105  and the first gate electrode layer  107  have been formed, the first gate dielectric layer  105  and the first gate electrode layer  107  may be patterned, if desired, using a suitable photolithographic masking and etching process in order to form the first gate electrode  301  and the first gate dielectric  303 . However, any suitable process for depositing the first gate electrode  301  and the first gate dielectric  303  may be utilized. However, in this embodiment the first gate dielectric layer  105 , if desired, may be formed to a thickness of between about 50 nm to about 500 nm, although any suitable thickness may be utilized. 
     Once the first gate electrode  301  and the first gate dielectric  303  have been formed, the first channel  305  and the source/drain regions  401  may be formed over the first gate dielectric  303 . In an embodiment the first channel  305  and the source/drain regions  401  may be formed as described above with respect to  FIGS.  1 - 5 B . For example, the first channel  205  and the source/drain regions  401  may be formed by initially growing the first channel layer  103  to the second thickness T 2  such that the material of the first channel layer  103  has the properties of a topological insulator (with metallic conducting surface states), and then reducing the thickness of a portion of the original first channel layer  103  to the first thickness T 1  in order to form the first channel  305  with properties of a semiconductor (as described above with respect to  FIGS.  5 A- 5 B ). As such, the first gate dielectric  303  has a planar surface facing the first channel  305  and the source/drain region  401  is in physical contact that planar surface. 
     In another embodiment similar to the embodiment described above with respect to  FIGS.  1 - 4 B , the first channel layer  103  may be grown on the first gate dielectric  303  to the first thickness T 1  and without growing to a thickness greater than the critical thickness T c . As such, the first channel layer  103  is formed to have properties of a semiconductor material. Once the first channel layer  103  has been grown to the first thickness T 1 , the first channel layer  103  may be patterned into the first channel  305  by placing, exposing, and developing a photoresist (not separately illustrated in  FIG.  6 A ) over the first channel layer  103  before using the photoresist as a mask during an etching process such as a dry etch to form the first channel  305 . 
     In addition to forming the first channel  305 , the etching process will also expose the underlying first gate dielectric  303 . Once the underlying first gate dielectric  303  has been exposed, the source/drain regions  401  may be formed on opposite sides of the first channel  305  as described above with respect to  FIG.  4 A . For example, the source/drain regions  401  may be formed from the same material as the first channel  305  using an epitaxial growth process to epitaxially grow the source/drain regions  401  onto the first gate dielectric  303 . Additionally, the source/drain regions  401 , while being grown from the same material as the first channel  305 , will grow the source/drain regions  401  to have the second thickness T 2  greater than the critical thickness T c  such that the source/drain regions  401  will have the properties of a topological insulator with metallic surface states. For example, in an embodiment in which the source/drain regions  401  are Bi 2 Se 3 , the source/drain regions  401  will be grown to a thickness that is greater than six quintuple layers. However, any suitable thickness may be utilized. As such, the first gate dielectric  303  in this embodiment has a first planar surface facing the first channel  305  and a second planar surface perpendicular to the first planar surface, wherein the source/drain region  401  is in physical contact the second planar surface. 
       FIG.  6 B  illustrates a top-down view of the structure of  FIG.  6 A . In this view, it can be seen that the first channel  305  is over the first gate dielectric  303  and extends between the source/drain regions  401 . In an embodiment the first channel  305  in this structure has a fourth length L 4  of between about 7 nm and about 100 μm, while the source/drain regions  401  have a fifth length L 5  of between about 7 nm and about 100 μm. However, any suitable dimensions may be utilized. 
     By forming the first channel  305  and the source/drain regions  401  over the first gate dielectric  303 , additional flexibility in the manufacturing process may be obtained. Such flexibility allows manufacturers the ability to modify their processes to arrive at the most efficient use of resources, allowing for a more efficient process. 
       FIGS.  7 - 8 B  illustrate another embodiment in which a multiple channel, multiple gate transistor  800  is formed. In this embodiment, the first channel layer  103  is grown over the first gate dielectric  303 , which is already formed and located over the first gate electrode  301 . For example, the first channel layer  103  is formed to the first thickness T 1  (less than the critical thickness T c ) such that the first channel layer  103  has the properties of a semiconductor material, such as by being less than 6 quintuple layers in an embodiment in which the first channel layer  103  is Bi 2 Se 3 . 
     Once the first channel layer  103  has been formed, a first dielectric layer  701  may be formed over the first channel layer  103  in order to separate and isolate the first channel layer  103  (which will become the first channel  305  in the multiple channel, multiple gate transistor  800 ) from a second channel layer  703  (which will become a second channel  805  in the multiple channel, multiple gate transistor  800 ). In an embodiment the first dielectric layer  701  may be dielectric material such as aluminum oxide or hafnium oxide that is formed using a process such as ALD, CVD, PVD, combinations of these, or the like. The first dielectric layer  701  may be formed to have an equivalent oxide thickness of between about 0.5 nm and about 2 nm, although any suitable thickness may be utilized. 
     Once the first dielectric layer  701  has been formed, a second channel layer  703  may be formed on the first dielectric layer  701 . In an embodiment the second channel layer  703  will be used to form the second channel  805  of the multiple channel, multiple gate transistor  800  and, as such, may be similar to the first channel layer  103 . For example, the second channel layer  703  may be formed from a topological insulator material such as Bi 2 Se 3  and may be formed to have the first thickness T 1  which is below the critical thickness T c  of the material used for the second channel layer  703 . As such, the second channel layer  703  will have the properties of a semiconductor material. In a particular embodiment in which Bi 2 Se 3  is used as the material for the second channel layer  703 , the second channel layer  703  may be formed to have the first thickness T 1  of less than about six quintuple layers, although any suitable thickness may be utilized. 
     After the second channel layer  703  has been formed, a second gate dielectric layer  705  is formed over the second channel layer  703 . In an embodiment the second gate dielectric layer  705  may be formed from similar materials and using similar processes as the first gate dielectric layer  105  described above with respect to  FIG.  1   . For example, the second gate dielectric layer  705  may be formed from a dielectric material such as aluminum oxide or hafnium oxide to a thickness of between about 0.5 nm and about 2 nm using a process such as ALD, CVD, PVD, or the like. However, any suitable material or method of manufacturing may be utilized. 
     Once the second gate dielectric layer  705  has been formed, a second gate electrode layer  707  may be formed over the second gate dielectric layer  705 . In an embodiment the second gate electrode layer  707  may be formed from similar materials and using similar processes as the first gate electrode layer  107  described above with respect to  FIG.  1   . For example, the second gate electrode layer  707  may be formed from a conductive material such as gold, titanium, platinum, aluminum, or the like using a process such as ALD, CVD, PVD, or the like. However, any suitable material or method of manufacturing may be utilized. 
       FIG.  8 A  illustrates a formation of the source/drain regions  401 . In an embodiment the formation of the source/drain regions  401  may be initiated by first patterning the second gate electrode layer  707  into a second gate electrode  801 . In an embodiment the second gate electrode layer  707  is patterned in a similar fashion as the first gate electrode layer  107  was patterned into the first gate electrode  301  (described above with respect to  FIG.  3   ). For example, a photoresist may be placed, exposed, developed, and used as a mask in a photolithographic masking and etching process in order to pattern the second gate electrode layer  707  into the second gate electrode  801 . In an embodiment the second gate electrode  801  may be formed to have a sixth width W 6  of between about 7 nm and about 100 μm. 
     Once the second gate electrode  801  has been formed, the second gate dielectric layer  705 , the second channel layer  703 , the first dielectric layer  701 , and the first channel layer  103  may next be patterned for the eventual formation of the source/drain regions  401 . In an embodiment the second gate dielectric layer  705 , the second channel layer  703 , first dielectric layer  701 , and the first channel layer  103  may be patterned by initially placing, exposing, and developing a photoresist over the second gate electrode  801  and exposed second gate dielectric layer  705  and then using the photoresist as a mask during an etching process such as a dry etching process in order to etch through the second gate dielectric layer  705 , the second channel layer  703 , the first dielectric layer  701 , and the first channel layer  103  until the first gate dielectric  303  has been exposed. The patterning will form a second gate dielectric  803  (from the second gate dielectric layer  705 ), a second channel  805  (from the second channel layer  703 ) and the first channel  305  (from the first channel layer  103 ). In an embodiment the second gate dielectric  803 , the second channel  805  and the first channel  305  may be formed to have a seventh width W 7  of between about 7 nm and about 100 μm. although any suitable dimension may be utilized. 
     Once the underlying first gate dielectric  303  has been exposed, the source/drain regions  401  may be formed on opposite sides of the first channel  305  and the second channel  805 , and the source/drain regions  401  may be formed as described above with respect to  FIG.  4 A . For example, the source/drain regions  401  may be formed from the same material as the first channel  305  and the second channel  805  and using an epitaxial growth process to epitaxially grow the source/drain regions  401  onto the exposed first gate dielectric  303 . Additionally, the source/drain regions  401 , while being grown from the same material as the first channel  305  and the second channel  805 , will grow the source/drain regions  401  to have the second thickness T 2  that is at least greater than the critical thickness T c  of the material used for the source/drain regions  401  such that the source/drain regions  401  will have the properties of a topological insulator with metallic surface states. For example, in an embodiment in which Bi 2 Se 3  is used as the material for the source/drain regions  401 , the source/drain regions  401  may be grown to the second thickness T 2  that is greater than six quintuple layers. However, any suitable thickness may be utilized. 
       FIG.  8 B  illustrates a top down view of the multiple channel, multiple gate transistor  800 . In this embodiment the second gate dielectric  803  may be formed to have a sixth length L 6  of between about 7 nm and about 100 μm. while the second gate electrode  801  may be formed to have a seventh length L 7  of between about 7 nm and about 100 μm. Additionally, the source/drain regions  401  may be formed to have an eighth length L 8  of between about 7 nm and about 100 μm. However, any suitable dimensions may be utilized. 
     By utilizing the processes described above with respect to  FIGS.  7 - 8 B , a multiple channel, multiple gate transistor  800  may be formed. Such a transistor allows for a normally off transistor with the use of topological materials which also has the benefits that multiple channels and multiple gates provide. 
     In accordance with an embodiment, a method of manufacturing a semiconductor device comprising growing a layer of a first material to a first thickness onto a substrate, the first thickness being less than a critical thickness is provided. A gate dielectric layer and a gate electrode layer are deposited over the layer of the first material and the gate dielectric layer and the gate electrode layer are patterned into a gate stack. The first layer of material is patterned to expose a portion of the substrate, and source/drain regions are grown onto the portion of the substrate, wherein the growing the source/drain regions grows the first material to a thickness greater than the critical thickness. 
     In accordance with another embodiment, a method of manufacturing a semiconductor device comprising growing a layer of a first material to a first thickness onto a substrate, the first thickness being greater than a critical thickness, is provided. A portion of the first material is removed to form a channel region and an opening over the channel region, wherein the removing the portion of the first material reduces the thickness of at least a portion of the first material to less than the critical thickness and also modifies the properties of the first material within the channel region. A gate dielectric is formed within the opening, and a gate electrode is formed over the gate dielectric. 
     In accordance with yet another embodiment, a semiconductor device comprising a first channel region comprising a first material, wherein the first material has a critical thickness below which the first material has properties of a semiconductor material and above which the first material has properties of a topological insulator, wherein the first channel region has a first thickness less than the critical thickness is provided. A source/drain region is adjacent to the first channel region, wherein the source/drain region comprises the first material with a second thickness greater than the critical thickness. A gate dielectric is adjacent to the first channel region, and a gate electrode is on an opposite side of the gate dielectric from the first channel region. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.