Patent Publication Number: US-11646350-B2

Title: Semiconductor device, and method of manufacturing semiconductor device

Description:
This application is a continuation of U.S. patent application Ser. No. 16/430,444, filed Jun. 4, 2019; which is a divisional of U.S. patent application Ser. No. 15/169,740, filed on Jun. 1, 2016; which is a continuation of International Patent Application No. PCT/JP2015/072933, filed Aug. 13, 2015; which claims priority to Japanese Patent Application No. 2014-204849, filed Oct. 3, 2014, the entirety of the contents of each of which are hereby incorporated herein by reference. 
    
    
     BACKGROUND 
     1. Technical Field 
     The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device. 
     2. Related Art 
     Conventionally, a vertical semiconductor device in which an anode and a cathode are provided to the front surface and rear surface of a semiconductor substrate has been known. The semiconductor device is used for example as a FWD (free wheeling diode) (see Patent Document 1, for example). Related prior art documents include the following documents. 
     Patent Document 1: Japanese Patent Application Publication No. 2012-199577 
     Patent Document 2: WO 2013/100155 
     Patent Document 3: U.S. Pat. No. 6,482,681 
     Patent Document 4: U.S. Pat. No. 6,707,111 
     Patent Document 5: Japanese Patent Application Publication No. 2001-160559 
     Patent Document 6: Japanese Patent Application Publication No. 2001-156299 
     Patent Document 7: Japanese Patent Application Publication No. H7-193218 
     Patent Document 8: United States Patent Application Publication No. 2008-1257 
     Patent Document 9: United States Patent Application Publication No. 2008-54369 
     Preferred characteristics of the above-mentioned semiconductor device include a low reverse recovery loss (that is, a low peak current Irp of a reverse recovery current and a low tail current of a reverse recovery current) and gentle reverse recovery (that is, a gentle rate of temporal change dV/dt of reverse recovery voltage). 
     SUMMARY 
     [General Disclosure of the Invention] 
     In accordance with one aspect of the invention a semiconductor device comprises an n-type semiconductor substrate. A p-type semiconductor region is formed in a front surface side of the semiconductor substrate. An n-type field stop region is formed in a rear surface side of the semiconductor substrate. The n-type field stop region includes protons as a donor. A concentration distribution of the donor in the field stop region in a depth direction has a plurality of peaks including a first peak, a second peak that is closer to the rear surface of the semiconductor substrate than the first peak is, a third peak that is closer to the rear surface of the semiconductor substrate than the second peak is, and a fourth peak that is closer to the rear surface of the semiconductor substrate than the third peak is. Each of the plurality of peaks including the first peak, the second peak, the third peak and the fourth peak has a peak maximum point, and peak end points formed at both sides of the peak maximum point. The peak maximum point of the first peak and the peak maximum point of the second peak are higher than the peak maximum point of the third peak. The peak maximum point of the third peak is lower than the peak maximum point of the fourth peak. 
     In accordance with another aspect of the invention a method for manufacturing a semiconductor device comprises providing an n-type semiconductor substrate. A p-type semiconductor region is formed in a front surface side of the semiconductor substrate. An n-type field stop region is formed in a rear surface side of the semiconductor substrate, the n-type field stop region including protons as a donor. A concentration distribution of the donor in the field stop region in a depth direction has a plurality of peaks including a first peak, a second peak that is closer to the rear surface of the semiconductor substrate than the first peak is, a third peak that is closer to the rear surface of the semiconductor substrate than the second peak is, and a fourth peak that is closer to the rear surface of the semiconductor substrate than the third peak is. Each of the plurality of peaks including the first peak, the second peak, the third peak, and the fourth peak has a peak maximum point, and peak end points formed at both sides of the peak maximum point. The peak maximum point of the first peak and the peak maximum point of the second peak are higher than the peak maximum point of the third peak. The peak maximum point of the third peak is lower than the peak maximum point of the fourth peak. 
     The summary clause does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a sub-combination of the features described above. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    shows a figure illustrating the gist of a semiconductor device  100  according to an embodiment of the present invention. 
         FIG.  2    shows a sectional schematic view of the semiconductor device  100  and a figure illustrating the carrier concentration distribution in an FS region  40 . 
         FIG.  3    shows a schematic view illustrating a distribution example of the carrier lifetime of a semiconductor substrate  10  in its depth direction. 
         FIG.  4    shows a figure illustrating one exemplary leakage current waveform of the semiconductor device  100 . 
         FIG.  5    shows a figure illustrating one exemplary manufacturing direction of the semiconductor device  100 . 
         FIG.  6    shows a figure illustrating one example of an FS region formation step S 340  and a lifetime control step S 350 . 
         FIG.  7    shows a figure illustrating another example of the FS region formation step S 340  and the lifetime control step S 350 . 
         FIG.  8    shows a figure in which a leakage current waveform of a semiconductor device  100  manufactured by performing proton annealing and a leakage current waveform of a semiconductor device  100  manufactured without performing proton annealing are compared with each other. 
         FIG.  9    shows a figure illustrating another exemplary carrier lifetime distribution. 
         FIG.  10    shows a figure illustrating one exemplary end portion position of a depletion layer when a reverse voltage is applied to the semiconductor device  100 . 
         FIG.  11    shows a figure illustrating one exemplary relationship between the irradiation amount of helium as a local lifetime killer and forward voltage of the semiconductor device  100 . 
         FIG.  12    shows a figure illustrating exemplary temporal waveforms of anode-cathode voltage and anodic current at the time of reverse recovery. 
         FIG.  13    shows a figure illustrating the relationship between forward voltage and dV/dt when the semiconductor substrate  10  is divided into seven regions in its depth direction, and the carrier lifetimes of the respective regions are varied. 
         FIG.  14 A  shows the relationship between the carrier lifetime (forward voltage) of a region from the front surface to the depth of 1/7 of the semiconductor substrate  10 , and a temporal waveform of anode-cathode voltage V KA . 
         FIG.  14 B  shows the relationship between the carrier lifetime (forward voltage) of a region from the front surface to the depth of 1/7 of the semiconductor substrate  10 , and a temporal waveform of anode current I A . 
         FIG.  15 A  shows the relationship between the carrier lifetime (forward voltage) of a depth region from 1/7 to 2/7 and a temporal waveform of anode-cathode voltage V KA . 
         FIG.  15 B  shows the relationship between the carrier lifetime (forward voltage) of a depth region from 1/7 to 2/7 from the front surface of the semiconductor substrate  10 , and a temporal waveform of anode current I A . 
         FIG.  16 A  shows the relationship between the carrier lifetime (forward voltage) of a depth region from 2/7 to 3/7 and a temporal waveform of anode-cathode voltage V KA . 
         FIG.  16 B  shows the relationship between the carrier lifetime (forward voltage) of a depth region from 2/7 to 3/7 from the front surface of the semiconductor substrate  10 , and a temporal waveform of anode current I A . 
         FIG.  17 A  shows the relationship between the carrier lifetime (forward voltage) of a depth region from 3/7 to 4/7 and a temporal waveform of anode-cathode voltage V KA . 
         FIG.  17 B  shows the relationship between the carrier lifetime (forward voltage) of a depth region from 3/7 to 4/7 from the front surface of the semiconductor substrate  10 , and a temporal waveform of anode current I A . 
         FIG.  18 A  shows the relationship between the carrier lifetime (forward voltage) of a depth region from 4/7 to 5/7 and a temporal waveform of anode-cathode voltage V KA . 
         FIG.  18 B  shows the relationship between the carrier lifetime (forward voltage) of a depth region from 4/7 to 5/7 from the front surface of the semiconductor substrate  10 , and a temporal waveform of anode current I A . 
         FIG.  19 A  shows the relationship between the carrier lifetime (forward voltage) of a depth region from 5/7 to 6/7 and a temporal waveform of anode-cathode voltage V KA . 
         FIG.  19 B  shows the relationship between the carrier lifetime (forward voltage) of a depth region from 5/7 to 6/7 from the front surface of the semiconductor substrate  10 , and a temporal waveform of anode current I A . 
         FIG.  20 A  shows the relationship between the carrier lifetime (forward voltage) of a depth region from 6/7 to the rear surface of the semiconductor substrate  10 , and a temporal waveform of anode-cathode voltage V KA . 
         FIG.  20 B  shows the relationship between the carrier lifetime (forward voltage) of a depth region from 6/7 to the rear surface of the semiconductor substrate  10 , and a temporal waveform of anode current I A . 
         FIG.  21    shows a figure illustrating a configuration example of a semiconductor device  200  according to another embodiment. 
         FIG.  22    shows a figure illustrating one exemplary method of manufacturing the semiconductor device  200 . 
         FIG.  23    shows a figure illustrating another exemplary carrier concentration distribution in the FS region  40 . 
         FIG.  24    shows a figure illustrating one exemplary impurity concentration distribution of the semiconductor substrate  10  in its depth direction, together with the helium distribution and hydrogen distribution. 
     
    
    
     DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     Hereinafter, (some) embodiment(s) of the present invention will be described. The embodiment(s) do(es) not limit the invention according to the claims, and all the combinations of the features described in the embodiment(s) are not necessarily essential to means provided by aspects of the invention. 
       FIG.  1    shows a figure illustrating the gist of a semiconductor device  100  according to an embodiment of the present invention.  FIG.  1    shows a schematic view of a section of the semiconductor device  100 . The semiconductor device  100  in the present example is used as a free wheeling diode (FWD) provided to be parallel with a high withstand voltage switch such as an IGBT, for example. The semiconductor device  100  of the present example comprises an n − -type semiconductor substrate  10 , an insulation film  22 , an anode electrode  24  and a cathode electrode  32 . Also, a p + -type anode region  20  is formed in the semiconductor substrate  10  on its front surface side, and a field stop region (FS region  40 ) and an n + -type cathode region  30  are formed in the semiconductor substrate  10  on its rear surface side. 
     The semiconductor substrate  10  is a silicon substrate, for example. The insulation film  22  is formed to cover the front surface of the semiconductor substrate  10 . However, the insulation film  22  has an opening through which the anode region  20  is exposed. The insulation film  22  is formed with an insulating material such as silicon oxide or silicon nitride, for example. 
     The anode electrode  24  is formed on the anode region  20  exposed through the opening of the insulation film  22 . 
     The anode electrode  24  is formed with metal such as aluminum, for example. 
     The FS region  40  is an n-type region formed with protons (hydrogen ions) as the donor. The impurity concentration of the FS region (the donor concentration in the present example) is higher than the impurity concentration of the semiconductor substrate  10 . The cathode region  30  is formed in the semiconductor substrate  10  to be closer to its rear surface than the FS region  40  is. The cathode region  30  is an n + -type region formed with phosphorus or the like as the donor, for example. The impurity concentration of the cathode region  30  is higher than both the impurity concentration of the semiconductor substrate  10  and the impurity concentration of the FS region  40 . The cathode electrode  32  is formed on the rear surface of the semiconductor substrate  10 , and is connected with the cathode region  30 . With such a configuration, the semiconductor device  100  functions as a diode. 
       FIG.  2    shows a sectional schematic view of the semiconductor device  100  and a figure illustrating the carrier concentration distribution in the FS region  40 . In the sectional schematic view of the semiconductor device  100  shown in  FIG.  2   , the insulation film  22 , the anode electrode  24  and the cathode electrode  32  are omitted. Also, in the concentration distribution shown in  FIG.  2   , the horizontal axis indicates the depth position within the FS region  40  from its rear surface side end portion, and the vertical axis indicates the carrier concentration. The carrier concentration corresponds to the donor concentration of protons injected into the FS region  40 . 
     As shown in  FIG.  2   , the concentration distribution of the donor in the FS region  40  in its depth direction has a plurality of peaks. The peaks refer to maximum values, for example. A first peak, a second peak, a third peak and a fourth peak are present in the concentration distribution of the donor in the FS region  40  of the present example. The first peak is present at the deepest position in the FS region  40  as seen from the rear surface side (cathode side) of the semiconductor substrate  10 . In the present specification, locations whose distances from the rear surface side (cathode side) of the semiconductor substrate  10  are longer are referred to as “deeper positions”, and locations whose distances are shorter are referred to as “shallower positions.” 
     The second peak is present at a position shallower than that of the first peak. Also, the donor concentration of the second peak is lower than the donor concentration of the first peak. The third peak is present at a position shallower than that of the second peak. In the present example, the donor concentration of the third peak is higher than both the donor concentration of the second peak and the donor concentration of the first peak. The donor concentration of the third peak may be lower than at least either one of the donor concentration of the second peak and the donor concentration of the first peak. 
     The fourth peak is present at a position shallower than that of the third peak. In the present example, the fourth peak is present at the shallowest position in the FS region  40 . The fourth peak may be provided at a position adjacent to or apart from the cathode region  30 . The plurality of peaks may be provided at regular intervals or irregular intervals in the FS region  40  in its depth direction. In the present example, the donor concentration of the fourth peak is higher than the donor concentrations of all the other peaks. 
     That is, in the present example, while the concentration of a peak decreases as the distance, in the FS region  40 , from the rear surface side of the semiconductor substrate  10  increases, the concentration of the first peak at the deepest position becomes higher than the concentration of the second peak at the second deepest position. In this manner, by making the concentration of the first peak higher than the concentration of the second peak, the distribution of the carrier lifetime of the semiconductor substrate  10  in its depth direction can be controlled appropriately. 
     For example, in the semiconductor substrate  10 , the carrier lifetime is controlled by irradiation with an electron ray or the like. Irradiation with an electron ray or the like dissociates the bonds between atoms of silicon crystal or the like forming the semiconductor substrate  10 , and crystal defects occur. Thereby, the carrier lifetime becomes short. Irradiation with an electron ray or the like makes the carrier lifetime short almost uniformly over the entire semiconductor substrate  10 . 
     On the other hand, protons terminate atoms whose bonds have been dissociated to repair the above-mentioned crystal defects. That is, protons have a function of recovering a carrier lifetime. For this reason, the distribution of a carrier lifetime can be controlled by controlling the concentration distribution of protons to be injected into the semiconductor substrate  10 . 
       FIG.  3    shows a schematic view illustrating a distribution example of the carrier lifetime of the semiconductor substrate  10  in its depth direction. In  FIG.  3   , the horizontal axis indicates positions in the depth direction of the semiconductor substrate  10 , and the vertical axis indicates the carrier lifetimes. However, the distribution example shows in  FIG.  3    is schematic, and the thickness of the semiconductor substrate  10  and the thickness of the FS region  40  do not match those in the example of  FIG.  2   . For example, in  FIG.  3   , the first peak of the FS region is positioned near the center of the anode region  20  and the cathode region  30 . 
     When protons are injected and then diffused by annealing or the like so as to attain the concentration distribution shown in  FIG.  2   , the diffused protons hydrogen-terminate crystal defects to recover a carrier lifetime. Because in the present example, the concentration of protons injected to the deepest position of the FS region  40  is high, the carrier lifetime of an intermediate portion of the semiconductor substrate  10  becomes longer than those on the front surface and rear surface of the semiconductor substrate  10  as shown in  FIG.  3   . 
     That is, the carrier lifetime in at least a partial region between the anode region  20  and the cathode region  30  is longer than the carrier lifetimes in both the anode region  20  and the cathode region  30 . The concentration distribution of protons injected is controlled to attain such a distribution of carrier lifetimes. In the present example, the carrier lifetime at a depth position that exhibits the first peak shown in  FIG.  2    becomes longer than the carrier lifetimes in both the anode region  20  and the cathode region  30 . 
     By attaining such a distribution of carrier lifetimes, the peak current Irp and the tail current of a reverse recovery current can be made small to decrease a reverse recovery loss, and the rate of temporal change dV/dt of reverse recovery voltage can be made small to realize gentle reverse recovery. 
     Because protons are diffused toward the front surface side of the semiconductor substrate  10 , the region that has a carrier lifetime longer than that in the anode region  20  extends toward the front surface side of the semiconductor substrate  10  past a position that is at the deepest portion in the FS region  40  and exhibits the first peak, as shown in  FIG.  3   . The extension amount of the region is estimated to be approximately 30 to 40 μm from the position of the first peak as described below with reference to  FIG.  4   . The depth position of the first peak is preferably determined considering the extension amount. 
       FIG.  4    shows a figure illustrating one exemplary leakage current waveform of the semiconductor device  100 . In  FIG.  4   , the horizontal axis indicates the reverse voltage between the anode and the cathode, and the vertical axis indicates the leakage current. Also, as a comparative example, a leakage current waveform of a semiconductor device in which the FS region  40  is not formed is shown with a broken line. The semiconductor device  100  of the present example in which the FS region  40  is formed exhibits generally decreased leakage current as compared with the semiconductor device in which the FS region  40  is not formed. 
     The semiconductor device  100  of the present example exhibits a steep inclination of leakage current increase relative to reverse voltages of up to approximately 200 to 300 V. With a further larger reverse voltage, the inclination of current decreases. The decrease in the inclination of current is deemed to be attributable to the fact that the depletion layer expanded by increase in voltage entered a region where the carrier lifetime was recovered by protons. 
     The relationship between reverse voltage V and depletion layer width W is expressed as follows. 
     
       
         
           
             W 
             = 
             
               
                 
                   
                     2 
                     ⁢ 
                     ϵ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       N 
                       A 
                     
                   
                   
                     
                       qN 
                       D 
                     
                     ⁡ 
                     
                       ( 
                       
                         
                           N 
                           A 
                         
                         + 
                         
                           N 
                           D 
                         
                       
                       ) 
                     
                   
                 
                 ⁢ 
                 
                   ( 
                   
                     
                       V 
                       bi 
                     
                     - 
                     V 
                   
                   ) 
                 
               
             
           
         
       
     
     Here, Vbi is a built-in voltage, N A  is an accepter concentration, N D  is a donor concentration, ε is the dielectric constant of the semiconductor substrate  10 , and q is an electric charge. Calculation of the depletion layer width W corresponding to a voltage at a changing point at which the inclination of current changes with the expression shown above gives approximately 50 to 60 The first peak is positioned approximately 30 μm from the rear surface of the semiconductor substrate  10 . Also, the thickness of the semiconductor substrate  10  is approximately 110 Accordingly, as explained with reference to  FIG.  3   , protons are estimated to be diffused by approximately 30 μm from the position of the first peak toward the front surface side of the semiconductor substrate  10 . 
       FIG.  5    shows a figure illustrating one exemplary manufacturing direction of the semiconductor device  100 . First, at a substrate preparation step S 300 , a semiconductor substrate  12  is prepared. The semiconductor substrate  12  functions as the semiconductor substrate  10  by being ground at its rear surface at a grinding step S 320  described below. That is, the semiconductor substrate  12  is formed with a material which is the same as that of the semiconductor substrate  10 , and is thicker than the semiconductor substrate  10 . The substrate resistivities of the semiconductor substrate  12  and the semiconductor substrate  10  may be approximately 70 to 90 Ωcm. 
     Next, at a front surface side forming step S 310 , the element structure of the front surface side of the semiconductor substrate  12  is formed. In the present example, the anode region  20 , the insulation film  22  and the anode electrode  24  are formed on the front surface of the semiconductor substrate  12 . Also, after forming the element structure, a protection film to protect the element structure may be formed. The protection film may be removed after manufacturing the semiconductor device  100 . Because the structure of the front surface side is formed by using the thick semiconductor substrate  12 , the possibility of a crack or the like of the semiconductor substrate  12  occurring at the front surface side forming step S 310  can be lowered. 
     Next, at the grinding step S 320 , the rear surface side of the semiconductor substrate  12  is ground to form the semiconductor substrate  10 . The thickness of the semiconductor substrate  10  after grinding is determined based on a rated voltage or the like of the semiconductor device  100 . The thickness of the semiconductor substrate  10  in the present example is approximately 100 to 130 
     Next, at a cathode region formation step S 330 , the cathode region  30  is formed on the rear surface of the semiconductor substrate  10 . At S 330 , n-type impurities such as phosphorus are ion-injected from the rear surface side of the semiconductor substrate  10 . After ion-injecting the impurities, laser annealing, for example, is performed on a region where the cathode region  30  should be formed to activate impurity ions and turn them into a donor. Thereby, the cathode region  30  is formed. 
     Next, at an FS region formation step S 340 , protons are injected into a region where the FS region  40  should be formed. At S 340 , as shown in  FIG.  2   , protons are injected into the FS region  40  so that the concentration distribution of protons in the FS region  40  in its depth direction has a plurality of peaks. Among the plurality of peaks, the first peak closest to the front surface of the semiconductor substrate  10  may be higher than the second peak closer to the rear surface of the semiconductor substrate  10  than the first peak is. Thereby, the FS region  40  is formed. The condition ranges of the acceleration voltage and injection amount of protons in the present example are as follows. Each value shown in the parentheses is a value to be one example. Thereby, the concentration distribution similar to that in the example of  FIG.  2    is formed. 
     First peak: 1 to 4 MeV (1.5 MeV), 3E12 to 3E13 cm −2  (1E13 cm −2 ) 
     Second peak: 0.8 to 3 MeV (1 Mev), 1E12 to 1E13 cm −2  (7E12 cm −2 ) 
     Third peak: 0.6 to 2 MeV (0.8 MeV), 3E12 to 3E13 cm −2  (1E13 cm −2 ) 
     Fourth peak: 0.2 to 1 MeV (0.4 MeV), 3E13 to 1E15 cm −2  (3E14 cm −2 ) 
     Also, the preferred ranges of respective peak concentrations of the FS region  40  and depths from the rear surface in the present example are as follows. Each value shown in the parentheses is a value to be one example. Also, because the second peak, the third peak and the fourth peak are formed in passage regions of protons for deeper peaks, the donor concentrations are raised due to the influence of protons in the passage regions having been turned into the donor. For this reason, for example, even if the injection amount of protons at the first peak, and the injection amount of protons at the third peak are the same, the donor concentration of the third peak is higher than that of the first peak. Because the donor concentrations of the passage regions of protons of the first and second peak are added thereto. 
     First peak: 2E14 to 2E15 cm −3  (9E14 cm −3 ), 15 to 150 μm (30 μm) 
     Second peak: 1E14 to 1E15 cm −3  (5E14 cm −3 ), 10 to 100 μm (15 μm) 
     Third peak: 3E14 to 3E15 cm −3  (2E15 cm −3 ), 5 to 50 μm (10 μm) 
     Fourth peak: 3E14 to 3E16 cm −3  (5E15 cm −3 ), 1.5 to 15 μm (3 μm) 
     The position of the first peak may be determined according to the withstand voltage class of the semiconductor device  100 . As described above, protons are diffused by a certain distance toward the front surface side of the semiconductor substrate  10 . Because the size of a region on the front surface side of the semiconductor substrate  10  desired to be left as a region where protons are not diffused is determined according to the withstand voltage class of the semiconductor device  100 , the position of the first peak may be determined considering the distance by which protons are diffused. The position of the first peak in a 1700-V withstand voltage semiconductor device  100 , for example, is deeper than the position of the first peak in a 1200-V withstand voltage semiconductor device  100 . Also, in a 600-V withstand voltage semiconductor device  100 , the first peak is provided at a position shallower than that in the 1200-V withstand voltage semiconductor device  100 . 
     Next, at a lifetime control step S 350 , the rear surface side of the semiconductor substrate  10  is irradiated with a lifetime killer. At S 350 , the rear surface side of the semiconductor substrate  10  is irradiated for example with an electron ray. Although the lifetime killer is not limited to an electron ray, one that enables recovery, by protons, of a carrier lifetime shortened by the lifetime killer is used. At S 350 , after irradiation with the lifetime killer, the semiconductor substrate  10  is annealed. Thereby, protons are diffused within the semiconductor substrate  10 , and the carrier lifetime of a partial region recovers, and the carrier lifetime distribution as shown in  FIG.  3    is attained. 
     Next, at a cathode electrode formation step S 360 , the cathode electrode  32  is formed in the semiconductor substrate  10  on its rear surface side. After forming the cathode electrode  32 , a thermal process of the cathode electrode  32  may be performed. Thereby, the semiconductor device  100  can be manufactured. 
       FIG.  6    shows a figure illustrating one example of the FS region formation step S 340  and the lifetime control step S 350 . The FS region formation step S 340  of the present example has a proton injection step S 342  and a proton annealing step S 344 . Also, the lifetime control step S 350  has a lifetime killer irradiation step S 352  and a lifetime annealing step S 354 . 
     At the proton injection step S 342 , protons are injected into a region where the FS region  40  should be formed as described above. Then, at the proton annealing step S 344 , the semiconductor substrate  10  is annealed. By annealing the semiconductor substrate  10 , protons present excessively in the semiconductor substrate  10  can be expelled. At the proton annealing step S 344 , the annealing temperature is approximately 300 to 500° C., for example, and the annealing duration is approximately 0.5 to 10 hours, for example. 
     Then, after the proton annealing step S 344 , irradiation with a lifetime killer is performed (S 352 ), and lifetime annealing is performed (S 354 ). At the lifetime annealing step S 354 , the annealing temperature is approximately 300 to 500° C., for example, and the annealing duration is approximately 0.5 to 10 hours, for example. In the present example, irradiation with an electron ray of 80 kGy is performed. Because the present example comprises the proton annealing step S 344  of annealing the semiconductor substrate  10  between the proton injection step S 342  and the lifetime killer irradiation step S 352 , and excess protons are expelled from the semiconductor substrate  10  at the proton annealing step S 344 , an appropriate amount of the protons is diffused by lifetime annealing. Thereby, the carrier lifetime in a region where protons are diffused recovers. For this reason, both decrease in the carrier lifetimes on the anode region  20  side and cathode region  30  side by lifetime killer irradiation, and recovery of the carrier lifetime in a region between the anode region  20  and the cathode region  30  by proton diffusion can be realized. 
       FIG.  7    shows a figure illustrating another example of the FS region formation step S 340  and the lifetime control step S 350 . In the present example, the FS region formation step S 340  does not have the proton annealing step S 344 . Other respects are the same as the example shown in  FIG.  6   . 
       FIG.  8    shows a figure in which a leakage current waveform of a semiconductor device  100  manufactured by performing proton annealing and a leakage current waveform of a semiconductor device  100  manufactured without performing proton annealing are compared with each other. When lifetime annealing is performed after proton injection and lifetime killer irradiation without performing proton annealing, a large amount of protons is remaining at the time of the lifetime annealing, and almost all crystal defects formed by the lifetime killer irradiation recover. For this reason, there is no effect of the lifetime killer irradiation as shown in  FIG.  8   . On the other hand, when annealing is performed separately after proton injection and after lifetime killer irradiation, respectively, the remaining amount of protons at the time of lifetime killer annealing can be controlled appropriately. For this reason, control of the carrier lifetime distribution becomes easy. 
       FIG.  9    shows a figure illustrating another exemplary carrier lifetime distribution. In the present example, the carrier lifetime in the cathode region  30  is reduced as compared with that in the distribution shown in  FIG.  3   . In the semiconductor device  100  of the present example, a local lifetime killer to shorten the carrier lifetime is injected into the rear surface side of the semiconductor substrate  10 . The local lifetime killer in the present example is helium. Because the tail current can be made small by reducing the carrier lifetime on the cathode region  30  side as described below, a reverse recovery loss can be decreased. 
     However, when the depletion layer that expands at the time when a reverse voltage is applied to the semiconductor device  100  expands to a region where the local lifetime killer is present, a leakage current increases significantly. For this reason, a region where the local lifetime killer is present is preferably formed at a depth position that does not contact a depletion layer that expands from the boundary between the anode region  20  and an n-type region of the semiconductor substrate  10  when a rated reverse voltage of the semiconductor device  100  is applied. Also, a region where the local lifetime killer is present may be formed at a depth position that does not contact a depletion layer that expands from the boundary between the anode region  20  and an n-type region of the semiconductor substrate  10  when a breakdown voltage of the semiconductor device  100  is applied. 
       FIG.  10    shows a figure illustrating one exemplary end portion position of a depletion layer when a reverse voltage is applied to the semiconductor device  100 .  FIG.  10    shows the dope concentration distribution of impurities together. Also, in  FIG.  10   , distances, from the rear surface of the semiconductor substrate  10 , of depletion layer end portions when reverse voltages are 400 V, 600 V, 800 V, 1000 V, 1100 V and 1200 V are shown. 
     For example when a reverse voltage of 1200 V is applied, the depletion layer expands from the front surface toward the rear surface of the semiconductor substrate  10 , and the depletion layer end reaches the position of 4 μm from the rear surface. In the configuration of the present example, when the rated reverse voltage is 1200 V, the local lifetime killer is preferably neither injected nor diffused to positions deeper than 2.5 μm from the rear surface of the semiconductor substrate  10 , for example. 
     When the local lifetime killer is injected to shallow positions from the rear surface of the semiconductor substrate  10  in this manner, the local lifetime killer injection position overlaps the fourth peak position of the proton injection. Crystal defects that have occurred due to helium irradiation are influenced by defect recovery due to protons in a similar manner to electron ray irradiation. For this reason, the local lifetime killer injection amount is preferably adjusted according to the proton injection amount in the region. 
       FIG.  11    shows a figure illustrating one exemplary relationship between the irradiation amount of helium as a local lifetime killer and forward voltage of the semiconductor device  100 . The forward voltage in a case where irradiation with helium was not performed was approximately 1.5 to 1.6 V. 
     In the present example, the proton injection amount at the fourth peak is 3E14 cm −2 . In contrast to this, as shown in  FIG.  11   , with a range of the helium irradiation amount smaller than 1E12 cm −2 , increase in the forward voltage is not observed as compared with a case where irradiation with helium was not performed. This is deemed to be attributable to the fact that almost all the defects due to helium irradiation are hydrogen-terminated by protons because the helium irradiation amount was too small as compared with the proton injection amount. Accordingly, the local lifetime killer injection amount is preferably 1/300 or more of the proton injection amount. The local lifetime killer injection amount may be 1/150 or more, or 1/100 or more of the proton injection amount. Also, the local lifetime killer injection amount is preferably ⅓ or less of the proton injection amount. 
       FIG.  12    shows a figure illustrating exemplary temporal waveforms of anode-cathode voltage and anodic current at the time of reverse recovery. In the semiconductor device  100 , a reverse recovery loss can be decreased by making the peak current value Irp and the tail current shown in  FIG.  12    small. Also, by making the inclination dV/dt of the anode-cathode voltage steep, reverse recovery can be made gentle. 
       FIG.  13    shows a figure illustrating the relationship between forward voltage and dV/dt when the semiconductor substrate  10  is divided into seven regions in its depth direction, and the carrier lifetimes of the respective regions are varied. In the example shown in  FIG.  13   , the relationship is calculated by device simulation. Generally, the shorter the carrier lifetime, the higher the forward voltage Vf. 
       FIG.  14 A  shows the relationship between forward voltage Vf at the time when the carrier lifetime of a region from the front surface to the depth of 1/7 of the semiconductor substrate  10  is varied, and a temporal waveform of anode-cathode voltage V KA .  FIG.  14 B  shows the relationship between forward voltage Vf at the time when the carrier lifetime of a region from the front surface to the depth of 1/7 of the semiconductor substrate  10  is varied, and a temporal waveform of anode current I A .  FIG.  14 A  to  FIG.  20 B  show examples in the cases of Vf=1.66 V, 1.70 V, 1.80 V, 1.90 V and 2.00 V. Respective figures show graphs in the cases of Vf=1.66 V and 2.00 V with arrows, and graphs in the cases of Vf=1.70 V, 1.80 V and 1.90 V are arranged in the descending order of the magnitude of Vf between the graphs in the cases of Vf=1.66 V and 2.00 V. 
       FIG.  15 A  shows the relationship between forward voltage Vf at the time when the carrier lifetime of a depth region from 1/7 to 2/7 is varied, and a temporal waveform of anode-cathode voltage V KA .  FIG.  15 B  shows the relationship between forward voltage Vf at the time when the carrier lifetime of a depth region from 1/7 to 2/7 from the front surface of the semiconductor substrate  10  is varied, and a temporal waveform of anode current I A . 
       FIG.  16 A  shows the relationship between forward voltage Vf at the time when the carrier lifetime of a depth region from 2/7 to 3/7 is varied, and a temporal waveform of anode-cathode voltage V KA .  FIG.  16 B  shows the relationship between forward voltage Vf at the time when the carrier lifetime of a depth region from 2/7 to 3/7 from the front surface of the semiconductor substrate  10  is varied, and a temporal waveform of anode current I A . 
       FIG.  17 A  shows the relationship between forward voltage Vf at the time when the carrier lifetime of a depth region from 3/7 to 4/7 is varied, and a temporal waveform of anode-cathode voltage V KA .  FIG.  17 B  shows the relationship between forward voltage Vf at the time when the carrier lifetime of a depth region from 3/7 to 4/7 from the front surface of the semiconductor substrate  10  is varied, and a temporal waveform of anode current I A . 
       FIG.  18 A  shows the relationship between forward voltage Vf at the time when the carrier lifetime of a depth region from 4/7 to 5/7 is varied, and a temporal waveform of anode-cathode voltage V KA .  FIG.  18 B  shows the relationship between forward voltage Vf at the time when the carrier lifetime of a depth region from 4/7 to 5/7 from the front surface of the semiconductor substrate  10  is varied, and a temporal waveform of anode current I A . 
       FIG.  19 A  shows the relationship between forward voltage Vf at the time when the carrier lifetime of a depth region from 5/7 to 6/7 is varied, and a temporal waveform of anode-cathode voltage V KA .  FIG.  19 B  shows the relationship between forward voltage Vf at the time when the carrier lifetime of a depth region from 5/7 to 6/7 from the front surface of the semiconductor substrate  10  is varied, and a temporal waveform of anode current I A . 
       FIG.  20 A  shows the relationship between forward voltage Vf at the time when the carrier lifetime of a depth region from 6/7 to the rear surface of the semiconductor substrate  10  is varied, and a temporal waveform of anode-cathode voltage V KA .  FIG.  20 B  shows the relationship between forward voltage Vf at the time when the carrier lifetime of a depth region from 6/7 to the rear surface of the semiconductor substrate  10  is varied, and a temporal waveform of anode current I A . 
     The following knowledge can be gained from  FIG.  13    to  FIG.  20 A .
         In the region from the front surface (the anode side front surface) to 3/7 of the semiconductor substrate  10 , fluctuation of the forward voltage Vf has large influence on Irp. On the other hand, even when the forward voltage Vf increases, dV/dt tends to decrease. For this reason, in this region, the carrier lifetime is preferably short so as to reduce Irp.   In the region from 3/7 to 5/7 from the front surface of the semiconductor substrate  10 , fluctuation of the forward voltage Vf has large influence on dV/dt. For this reason, the carrier lifetime of this region is preferably long so as to realize gentle dV/dt.   In the region from 5/7, from the front surface of the semiconductor substrate  10 , to the rear surface (the cathode side front surface) of the semiconductor substrate  10 , fluctuation of the forward voltage Vf has large influence on a tail current. For this reason, the carrier lifetime is favorably short in order to make the tail current small. On the other hand, if the carrier lifetime is too short, carriers on the cathode side decrease so much that an oscillation phenomenon of voltage and current may occur at the time of reverse recovery. For this reason, the carrier lifetime of this region may be shorter than that in the region from 3/7 to 5/7, and longer than that in the region from the front surface of the semiconductor substrate  10  to 3/7.       

     The above-mentioned phenomenon can be understood also as follows. At the time of reverse recovery, the depletion layer expands from the anode region  20  side. Carriers that have been present in the region of the depletion layer are expelled to become a reverse recovery current. Accordingly, if there is a lot of carriers on the front surface side of the semiconductor substrate  10 , it becomes more likely that the peak Irp of current to flow first becomes higher. 
     Also, carriers present in the region between the depletion layer and the rear surface of the semiconductor substrate  10  in a state where expansion of the depletion layer is stopped flows as a tail current. For this reason, if there is a lot of carriers on the rear surface side of the semiconductor substrate  10 , it becomes more likely that a tail current becomes larger. 
     Also, when the semiconductor device  100  is used as a free wheeling diode such as an IGBT, the IGBT or the like draws a predetermined current from the semiconductor device  100 . At this time, if a lot of carriers is present in the semiconductor substrate  10 , the current can be supplied to the IGBT or the like even if the depletion layer expands slowly. On the other hand, when the number of carriers is small, the depletion layer expands fast in order to supply the current, and the inclination dV/dt of the reverse recovery voltage becomes steep. For this reason, when the number of carriers in a region in the middle of the semiconductor substrate  10  through which the depletion layer expands is large, the inclination of dV/dt of reverse recovery voltage becomes less steep. 
     Also, the first peak is preferably provided at a position corresponding to an end portion of the above-mentioned depletion layer on the rear surface side of the semiconductor substrate  10  when the inter-electrode voltage of the diode at the time of reverse recovery of the semiconductor device  100  becomes the half value of an applied voltage. Generally, an applied voltage at the time of reverse recovery is often set to be approximately the half of the withstand voltage of an element. For example, a 1200-V withstand voltage element is reverse-recovered at an applied voltage of 600 V. The moment when dV/dt becomes the largest at the time of reverse recovery is when the anode-cathode voltage becomes the half of an applied voltage. By locating the first peak at a position where the depletion layer is expanding at the time of the anode-cathode voltage, dV/dt can be made small efficiently. 
     In the semiconductor device  100  of the present example, the carrier lifetime is caused to recover by injecting protons to form the FS region  40 , and at the same time diffusing the protons. Because in the present example, the distribution of protons is like the one shown in  FIG.  2    or the like, as shown in  FIG.  3    or  FIG.  9   , the distribution of the carrier lifetime having a peak in the middle of the semiconductor substrate  10  can be formed. Thanks to the distribution of the carrier lifetime, as explained with reference to  FIG.  13    to  FIG.  20 A , the small peak current Irp, the small tail current and the gentle inclination dV/dt of reverse recovery voltage can be realized. 
       FIG.  21    shows a figure illustrating a configuration example of a semiconductor device  200  according to another embodiment. The semiconductor device  200  of the present example is an RC-IGBT device in which an IGBT element  140  and a FWD element  150  connected in anti-parallel are formed integrally. The semiconductor device  200  comprises the semiconductor substrate  10 , an insulation film  122 , an emitter anode electrode  124  and a collector cathode electrode  132 . 
     The semiconductor substrate  10  has p-type regions  120  formed on its front surface side. Also, the semiconductor substrate  10  has a plurality of trenches  104  formed to penetrate the p-type regions  120  from the front surface of the semiconductor substrate  10 . The leading end of each trench  104  on the rear surface side of the semiconductor substrate  10  protrudes past the end portions of the p-type regions  120 . Each trench  104  has a trench gate  102  formed to penetrate the p-type region  120  from the front surface of the semiconductor substrate  10 . Also, each trench gate  102  and each semiconductor layer are insulated by an insulation film  103 . 
     Also, among the plurality of p-type regions  120  separated by the trenches  104 , in some of the p-type regions  120  corresponding to the IGBT element  140 , n + -type regions  106  and p + -type region  108  are formed. The n + -type regions  106  are provided adjacent to the trenches  104  on the front surface of the p-type regions  120 . The p + -type regions  108  are provided being sandwiched by the n + -type regions  106  on the front surface of the p-type regions  120 . 
     Also, among the plurality of p-type regions  120 , p-type regions  120  corresponding to the FWD element  150  function as the anode region  20  explained with reference to  FIG.  1    to  FIG.  20 B . The n + -type regions  106  and the p + -type regions  108  may be formed also in the p-type regions  120  corresponding to the FWD element  150 . 
     The emitter anode electrode  124  is connected to the respective p-type regions  120 . When the n + -type regions  106  and the p + -type regions  108  are formed in the p-type regions  120 , the emitter anode electrode  124  is connected to both the n + -type regions  106  and the p + -type regions  108 . When the n + -type regions  106  and the p + -type regions  108  are not formed, the emitter anode electrode  124  is connected to the p-type regions  120 . 
     Also, the emitter anode electrode  124  and the trench gates  102  are insulated by the insulation film  122 . The respective trench gates  102  are connected to a gate electrode not shown in the figure. Due to a voltage being applied to the trench gates  102 , a channel in the vertical direction is formed in the p-type regions  120  between the n + -type regions  106  and the semiconductor substrate  10 . 
     The semiconductor substrate  10  comprises the FS region  40  formed on its rear surface side. The FS region  40  has the structure and characteristics which are the same as those of the FS region  40  explained with reference to  FIG.  1    to  FIG.  20 B . Also, among regions on the rear surface of the FS region  40 , in a region corresponding to the IGBT element  140 , a p-type collector region  130  is formed, and in a region corresponding to the FWD element  150 , the n-type cathode region  30  is formed. On the rear surfaces of the collector region  130  and the cathode region  30 , the common collector cathode electrode  132  is formed. 
     It is effective, also in the RC-IGBT semiconductor device  200  of the present example, to control the carrier lifetime by adjusting the proton injection concentration in the FS region  40  as explained with reference to  FIG.  1    to  FIG.  20 B . 
       FIG.  22    shows a figure illustrating one exemplary method of manufacturing the semiconductor device  200 . First, the semiconductor substrate  12  is prepared in a manner similar to that in the example of  FIG.  5   . Next, at a front surface element structure formation step S 402 , the element structure of the semiconductor substrate  12  on the front surface side thereof is formed. In the present example, the p-type regions  120 , the trenches  104 , the n + -type regions  106 , the p + -type regions  108 , the n-type regions  110  and the insulation film  122  are formed on the front surface of the semiconductor substrate  12 . 
     Next, at a front surface electrode formation step S 404 , the emitter anode electrode  124  is formed. Next, at a rear surface grinding step S 406 , the rear surface of the semiconductor substrate  12  is ground. Next, at a rear surface diffusion layer ion injection step S 408 , p-type impurity ions and n-type impurity ions are injected, respectively, into regions of the rear surface of the semiconductor substrate  10  corresponding to the collector region  130  and the cathode region  30 . Next, at a rear surface laser annealing step S 410 , the regions to which the p-type impurity ions and the n-type impurity ions are injected are laser-annealed to form the collector region  130  and the cathode region  30 . Next, at a front surface protection film formation step S 411 , a protection film is formed on the front surface of the semiconductor substrate  10 . 
     Next, at a proton injection step S 412  and a proton annealing step S 414 , the FS region  40  is formed. The proton injection step S 412  and the proton annealing step S 414  are the same as the proton injection step S 342  and the proton annealing step S 344  in  FIG.  6   . Thereby, the FS region  40  having the concentration distribution of protons as the one shown in  FIG.  2    is formed. 
     Next, at a lifetime killer irradiation step S 416  and a lifetime annealing step S 418 , the carrier lifetime is controlled. The lifetime killer irradiation step S 416  and the lifetime annealing step S 418  are the same as the lifetime killer irradiation step S 352  and the lifetime annealing step S 354  in  FIG.  6   . Thereby, the carrier lifetime distribution as the one shown in  FIG.  3    or  FIG.  9    is realized. 
     Then, at a rear surface electrode formation step S 420 , the collector cathode electrode  132  is formed. Thereby, the semiconductor device  200  is manufactured. 
     While the embodiments of the present invention have been described, the technical scope of the invention is not limited to the above described embodiments. It is apparent to persons skilled in the art that various alterations and improvements can be added to the above-described embodiments. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the invention. 
       FIG.  23    shows a figure illustrating another exemplary carrier concentration distribution in the FS region  40 . In  FIG.  23   , the horizontal axis indicates the depth position within the FS region  40  from its rear surface side end portion, and the vertical axis indicates the carrier concentration. The carrier concentration corresponds to the donor concentration of protons injected into the FS region  40 . 
     As shown in  FIG.  23   , the concentration distribution of the donor in the FS region  40  in its depth direction has a plurality of peaks. In the present example also, similarly to the example of  FIG.  2   , there are a first peak, a second peak, a third peak and a fourth peak. However, in the present example, the first to third peaks excluding the fourth peak closest to the rear surface side end portion of the FS region  40  have higher carrier concentrations as the distances from the rear surface end portion increase. That is, the carrier concentration of the first peak is higher than the carrier concentrations of the second peak and the third peak, and the carrier concentration of the second peak is higher than the carrier concentration of the third peak. 
     The FS region  40  prevents the depletion layer expanding from the boundary of the p + -type anode region  20  and the n − -type semiconductor substrate  10  from reaching the cathode region  30 . The depletion layer may expand, at most, to the peak closest to the rear surface end portion among the plurality of peaks. 
     In the present example, the concentrations of the first to third peak decrease gradually from the substrate front surface side toward the rear surface side. Also, the lowest peak concentration is higher than that in the example of  FIG.  2   . For this reason, the inclination dV/dt of reverse recovery voltage can be made small. 
       FIG.  24    shows a figure illustrating one exemplary impurity concentration distribution of the semiconductor substrate  10  in its depth direction, together with the helium distribution and hydrogen distribution. In  FIG.  24   , the p-type and n-type impurity concentrations are shown together. In the present example, the p-type anode region  20  with a high concentration is formed from the front surface of the semiconductor substrate  10  to the depth of approximately several μm. An n − -type region as a drift region is formed from an end portion of the anode region  20  to the depth of approximately 55 μm, and the FS region  40  and the cathode region  30  are formed to the depths of approximately 55 μm and more. 
     Also, in  FIG.  24   , the impurity concentration of a comparative example 300 is indicated with a dotted line. In the FS region  40  of the semiconductor device  100  of the present example, the peak of impurity concentration closest to the front surface of the semiconductor substrate  10  is higher than the corresponding peak in the comparative example 300. 
     Also, in the semiconductor device  100  of the present example, the front surface of the semiconductor substrate  10  is irradiated with helium ions in order to control the carrier lifetime on the front surface side of the semiconductor substrate  10 . In the present example, the average range of helium ions is Rp, and the half-value width of the range distribution of helium ions is ΔRp. 
     The peak position of a range of helium ions with which the front surface of the semiconductor substrate  10  is irradiated (that is, the position of a depth Rp from the front surface of the semiconductor substrate  10 ) may be located within a range of 40 μm from the peak closest to the front surface of the semiconductor substrate  10  from among the peaks in the concentration distribution of the donor in the FS region  40 . The distance from a peak may be measured from a position at which a donor concentration becomes a half of a maximum value of the peak on the substrate front surface side from the maximum point of the peak. 
     With such a configuration, a dangling bond attributable to holes generated due to irradiation with helium ions is terminated by a predetermined amount by hydrogen diffused from the peak of the FS region  40 . For this reason, a leakage current attributable to helium and holes can be decreased. Also, the carrier lifetime distribution shown in  FIG.  3    can be readily realized. 
     The half-value position Rp-ΔRp of the range distribution of helium ions may be within the range of 40 μm from the peak of the concentration distribution of the donor in the FS region  40 . Thereby, a leakage current can be decreased more efficiently. However, the distribution position of helium ions is not limited to these ranges. Even if the peak position Rp of the range of helium ions is apart from the peak of the concentration distribution of the donor in the FS region  40  by 40 μm or more, a leakage current can be decreased to a certain degree, although hydrogen diffused from the peak becomes less. 
     The operations, procedures, steps, and stages of each process performed by an apparatus, system, program, and method shown in the claims, embodiments, or diagrams can be performed in any order as long as the order is not indicated by “prior to,” “before,” or the like and as long as the output from a previous process is not used in a later process. Even if the process flow is described using phrases such as “first” or “next” in the claims, embodiments, or diagrams, it does not necessarily mean that the process must be performed in this order. 
     EXPLANATION OF REFERENCE SYMBOLS 
       10 : semiconductor substrate,  12 : semiconductor substrate,  20 : anode region,  22 : insulation film,  24 : anode electrode,  30 : cathode region,  32 : cathode electrode,  40 : FS region,  100 : semiconductor device,  102 : trench gate,  103 : insulation film,  104 : trench,  106 : n + -type region,  108 : p + -type region,  110 : n-type region,  120 : p-type region,  122 : insulation film,  124 : emitter anode electrode,  130 : collector region,  132 : collector cathode electrode,  140 : IGBT element,  150 : FWD element,  200 : semiconductor device,  300 : comparative example