Patent Publication Number: US-11664823-B2

Title: Early convergence for decoding of LDPC codes

Description:
CROSS REFERENCE TO OTHER APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 17/306,057 entitled EARLY CONVERGENCE FOR DECODING OF LDPC CODES filed May 3, 2021 which is incorporated herein by reference for all purposes. 
    
    
     BACKGROUND OF THE INVENTION 
     Low-density parity-check (LDPC) codes are a type of error correction code. In some applications, LDPC codes are used to correct for errors that are introduced by a (e.g., noisy) communication channel or by (e.g., degrading) storage media. New techniques which improve the performance of LDPC systems would be desirable. For example, reducing the processing time would be desirable because the error corrected data is output sooner and/or less processing resources or power is consumed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various embodiments of the invention are disclosed in the following detailed description and the accompanying drawings. 
         FIG.  1    is a flowchart illustrating an embodiment of a low-density parity-check (LDPC) decoding process with early convergence. 
         FIG.  2 A  is a diagram illustrating an embodiment of a low-density parity-check (LDPC) encoder and decoder used in a communications application. 
         FIG.  2 B  is a diagram illustrating an embodiment of a low-density parity-check (LDPC) encoder and decoder used in a storage application. 
         FIG.  3 A  is a diagram illustrating an example of a min-sum low-density parity-check (LDPC) decoder. 
         FIG.  3 B  is a diagram illustrating an example of a check node to variable node message update associated with a variable node to check node phase. 
         FIG.  3 C  is a diagram illustrating an example of a variable node to check node message update associated with a check node to variable node phase. 
         FIG.  4    is a diagram illustrating an example of a layered min-sum decoding process without early convergence. 
         FIG.  5    is a diagram illustrating an embodiment of a layered min-sum low-density parity-check (LDPC) decoder that monitors states to determine when an early convergence checkpoint has occurred. 
         FIG.  6 A  is a flowchart illustrating an embodiment of a low-density parity-check (LDPC) decoding process with early convergence that monitors check node states to determine when an early convergence checkpoint has occurred. 
         FIG.  6 B  is a flowchart illustrating an embodiment of a low-density parity-check (LDPC) decoding process with early convergence that monitors circulant states to determine when an early convergence checkpoint has occurred. 
         FIG.  7 A  is a diagram illustrating an embodiment of QC-LDPC circulants in an  H  matrix that are processed during a first layer. 
         FIG.  7 B  is a diagram illustrating an embodiment of QC-LDPC circulants in an  H  matrix that are processed during a second layer. 
         FIG.  7 C  is a diagram illustrating an embodiment of QC-LDPC circulants in an  H  matrix that are processed during a third layer. 
         FIG.  8    is a flowchart illustrating an embodiment of a low-density parity-check (LDPC) decoding process with early convergence that uses a fractional iteration count. 
         FIG.  9    is a diagram illustrating an embodiment of a permuted  H  matrix. 
         FIG.  10    is a flowchart illustrating an embodiment of a process to determine a minimal fractional iteration count. 
     
    
    
     DETAILED DESCRIPTION 
     The invention can be implemented in numerous ways, including as a process; an apparatus; a system; a composition of matter; a computer program product embodied on a computer readable storage medium; and/or a processor, such as a processor configured to execute instructions stored on and/or provided by a memory coupled to the processor. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. In general, the order of the steps of disclosed processes may be altered within the scope of the invention. Unless stated otherwise, a component such as a processor or a memory described as being configured to perform a task may be implemented as a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task. As used herein, the term ‘processor’ refers to one or more devices, circuits, and/or processing cores configured to process data, such as computer program instructions. 
     A detailed description of one or more embodiments of the invention is provided below along with accompanying figures that illustrate the principles of the invention. The invention is described in connection with such embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims and the invention encompasses numerous alternatives, modifications and equivalents. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. These details are provided for the purpose of example and the invention may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured. 
     Various embodiments of a low-density parity-check (LDPC) decoding technique that checks for early convergence are described herein. As will be described in more detail below, a (e.g., layered min-sum) LDPC decoder performs an early termination check before a full iteration of decoding is performed (e.g., at some fractional, pre-calculated iteration count). When decoding data with relatively few errors, an LDPC decoder which performs the techniques described herein can output the error corrected data earlier than other types of LDPC decoders which reduces processing time and/or conserves power. The following figure describes one LDPC decoding embodiment with early convergence. 
       FIG.  1    is a flowchart illustrating an embodiment of a low-density parity-check (LDPC) decoding process with early convergence. In various embodiments, the process may be performed in a hardware implementation (e.g., an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA)) or a software implementation (e.g., firmware or a computer program product embodied in a non-transitory computer readable medium and computer instructions). 
     At  100 , low-density parity-check (LDPC) encoded data with one or more errors is received. For example, the encoded data may have been received from a communication channel or read back from storage (e.g., after being stored for many years on degrading storage media) and errors were introduced into the LDPC encoded data. 
     At  102 , information associated with an early convergence checkpoint is received. In some embodiments, the information received at step  102  is a signal (e.g., a collective monitored state signal based on monitored states) that indicates when the early convergence checkpoint has been reached or passed. In some embodiments, the information received at step  102  is a partial and/or fractional iteration where the fractional iteration is strictly greater than 0 and strictly less than 1 and the fractional iteration corresponds to the early convergence checkpoint. The LDPC decoder in such embodiments tracks the (fractional) iteration count and pauses decoding when the fractional count received at step  102  is reached. 
     At  104 , the information associated with the early convergence checkpoint is used to perform (e.g., layered min-sum) LDPC decoding on the LDPC encoded data up to the early convergence checkpoint and generate a decoded codeword, wherein the early convergence checkpoint is prior to a first complete iteration of the LDPC decoding. 
     At  106 , it is determined if the LDPC decoding is successful. For example, the decoded codeword generated at step  100  may or may not still include errors and decoding is not declared a success (in one example) unless the syndrome vector is all zeros or otherwise indicates all errors have been successfully removed from the decoded data. 
     If it is determined that decoding is successful at  106 , the decoded codeword (e.g., generated at  104 ) is output at  110 . For example, if there are only a few errors, then a fraction of a complete iteration may be sufficient to remove all of the errors. With other types of LDPC decoders, the decoder completes at least one complete iteration before checking if decoding is successful. With early convergence checking, the decoded data can be output sooner and power and processing resources may be conserved when possible (e.g., only a few errors that do not require a full or complete decoding iteration). 
     If it is determined that decoding is not successful at  106 , the (e.g., layered min-sum) LDPC decoding continues at  108  (e.g., until successful or a timeout is reached). If the resumed LDPC decoding at step  108  is successful, the decoded codeword is output. In some cases, a timeout is reached and the resumed LDPC decoding is halted; an error is then declared or a different type of decoding (e.g., stronger but slower) is attempted. 
     Before describing more detailed examples of the early decoding termination process shown in  FIG.  1   , it may be helpful to illustrate some example applications in which such a technique may be used. The following figures illustrate some example applications. 
       FIG.  2 A  is a diagram illustrating an embodiment of a low-density parity-check (LDPC) encoder and decoder used in a communications application. In this example, an LDPC encoder ( 200   a ) inputs input data to encode before transmission. LDPC encoded data to transmit is output from the LDPC encoder ( 200   a ) and is passed to a transmitter ( 202 ) which modulates and/or formats the LDPC encoded data as appropriate for the particular communication channel and sends transmitted data over a communication channel ( 204 ), such as a wired or wireless channel and/or a network. 
     A receiver ( 206 ) coupled to the communication channel ( 204 ) inputs received data and demodulates and/or extracts LDPC encoded data with errors from the received data with errors. An LDPC decoder ( 208   a ) then decodes the received, compressed data and outputs the uncompressed data. In some embodiments, LDPC decoder ( 208   a ) performs an early decoding termination process (e.g.,  FIG.  1   ) which permits the LDPC decoding to end earlier than some other LDPC decoders, reducing delay. 
     The communication channel ( 204 ) introduces noise and/or errors so that the data received by the receiver ( 206 ) contains noise. Error correction encoding the data with an LDPC code prior to transmission may reduce the number of errors and/or indecipherable messages at the receiver. 
       FIG.  2 B  is a diagram illustrating an embodiment of a low-density parity-check (LDPC) encoder and decoder used in a storage application. In this example, input data to encode is passed to an LDPC encoder ( 200   b ). The LDPC encoder ( 200   b ) passes LDPC encoded data to be stored and/or written to storage interface ( 220 ) which in turn writes data to storage ( 222 ). 
     To obtain the original data, the storage interface ( 220 ) reads back data (with errors) stored on the storage ( 222 ) and passes the LDPC encoded data (with errors) to the LDPC decoder ( 208   b ). The LDPC decoder ( 208   b ) decodes the LDPC encoded data and outputs the data (e.g., error corrected as or if needed). In some embodiments, LDPC decoder ( 208   b ) performs an early decoding termination process (e.g.,  FIG.  1   ) which permits the LDPC decoding to end earlier than some other LDPC decoders, reducing delay. 
     Before describing more detailed examples of early decoding termination, it may be helpful to first describe LDPC decoding in more detail. First, an example of min-sum LDPC decoding is described. Then, a layered min-sum LDPC decoding example is described. 
       FIG.  3 A  is a diagram illustrating an example of a min-sum low-density parity-check (LDPC) decoder. Low-density parity-check (LDPC) codes have a very low density of 1&#39;s in their parity-check matrix (also referred to herein as an  H  matrix) used by an LDPC decoder. This makes it convenient to represent an LDPC code using a bipartite graph, called a Tanner Graph. There are two types of nodes in a Tanner graph, namely, variable nodes ( 302   a ) and check nodes ( 304   a ). Each variable node (or check node) corresponds to a column (or row) of the parity-check matrix  H . In examples described herein, V={v 1 , . . . , v n } is the set of variable nodes and C={c 1 , . . . , c m } is the set of check nodes. Each row of the  H  matrix is indexed by  ={1, 2, . . . , m} and each column of  H  by V={1, 2, . . . , n}. In the Tanner graph, variable node v i  is connected to check node c j  via an edge if H j =1, and the set of edges on the Tanner graph is denoted by set E. 
     Quasi-cyclic low-density parity-check (QC-LDPC) codes are a special class of the LDPC codes with a structured  H  matrix which can be generated by the expansion of an m b ×n b  base matrix. Each 1&#39;s element in the base matrix can be expanded by a circularly right-shifted b×b identity sub-matrix. QC-LDPC codes have advantages over other types of LDPC codes in hardware implementations of both encoding and decoding. Encoding of a QC-LDPC code can be efficiently implemented using simple shift registers. In some hardware implementation embodiments of a QC-LDPC decoder, the QC structure of the code simplifies the wire routing for message passing. 
     In this example, a message-passing (MP) LDPC decoder is shown. In general, the (layered) min-sum decoding controller ( 300 ) controls the message passing between the variable nodes ( 302   a ) and the check nodes ( 304   a ). Periodically, the controller ( 300 ) will check the syndrome vector ( 308 ); if the syndrome vector is all-zero then all of the errors have been removed from the LDPC encoded data and the decoded codeword ( 310 ) is output. Message passing is the most efficient way to achieve near-optimal decoding of LDPC codes. In message passing decoding, the variable node (VN) and check node (CN) update rules as follows. For brevity and notational conciseness, examples described herein may simply use i (instead of v i ) to denote a variable node and j (instead of c j ) to denote a check node. A variable node i receives an input message L i   ch  from the channel, typically the log-likelihood ratio (LLR) of the corresponding channel output, defined as follows: 
                       L   i     c   ⁢   h       =     log   ⁡   (       P   ⁢     r   ⁡   (       R   i     =         r   i     ❘     c   i       =   0       )         P   ⁢     r   ⁡   (       R   i     =         r   i     ❘     c   i       =   1       )         )       ,           (   1   )               
where c i ∈{0, 1} is the code bit and r i  is the corresponding received symbol.
 
     An iterative message passing decoder alternates between two phases: a variable node to check node phase during which variable nodes send messages to check nodes along their adjacent edges and a check node to variable node phase during which check nodes send messages to their adjacent variable nodes. The message update rules (which are described in more detail below) are depicted schematically in  FIGS.  3 B and  3 C , respectively. 
       FIG.  3 B  is a diagram illustrating an example of a check node to variable node message update associated with a variable node to check node phase. In this example, each check node ( 304   b ) receives LLR information from all of its neighboring variable nodes ( 302   b ). For each such variable node, an updated check-to-variable message is generated using the inputs from all other neighboring variable nodes. 
       FIG.  3 C  is a diagram illustrating an example of a variable node to check node message update associated with a check node to variable node phase. In this example, each variable node ( 302   c ) receives LLR information from all of its neighboring check nodes ( 304   c ). For each such variable node, an updated variable-to-check message is generated using the inputs from all other neighboring check nodes. 
     In the initialization step of the decoding process, variable node i forwards the same message to all of its neighboring check nodes, (i), namely the LLR L i   ch  derived from the corresponding channel output. In the check node-to-variable node message update phase, check node j uses the incoming messages and CN update rule to compute and forward, to variable node i∈(j), a new check node to variable node message, L j→i . Variable node i then processes its incoming messages according to the variable node update rule and forwards to each adjacent check node, (i), an updated variable node to check node message, L i→j . After a pre-specified number of iterations, variable node i sums all of the incoming LLR messages to produce an estimate of the corresponding code bit i. Note that all of the check node to variable node message updates can be done in parallel, as can all of the variable node to check node message updates. This enables efficient, high-speed software and hardware implementations of the iterative message passing decoding. 
     L i→j  and L j→i  are the messages sent from variable node i to check node j and from check node j to variable node i, respectively. (i) is the set of check nodes directly connected to variable node i and (j) is the set of variable nodes directly connected to check node j. Then, the message sent from variable node i to check node j in SPA decoding is given by: 
                       L     i   →   j       =       L   i     c   ⁢   h       +       ∑       j   ⁢   ′     ∈       C   ⁡   (   i   )     ∖   j           L       j   ⁢   ′     →   i             ,           (   2   )               
and the message from check node j to variable node i is computed as:
 
     
       
         
           
             
               
                 
                   
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     P i  is the a posterior probability (APP) message of variable node i: 
     
       
         
           
             
               
                 
                   
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     The decoded word  v  is defined as the hard-decision of the APP messages  P , that is:
 
[ v   1   ,v   2   ,v   3   , . . . ,v   n-1   ,v   n ]   hd ([ P   1   ,P   2   ,P   3   , . . . ,P   n-1   ,P   n ])  (5)
 
where hd(P i ) is 1 if P i &lt;0, or 0 otherwise. A decoding success is declared if the resulting syndrome vector (γ) is all zeros, such that:
 
γ     v · H =   0 .  (6)
 
     During the decoding process, the decoded word ( v ) and the syndrome vector (γ) are both initialized to all zeros, and incrementally updated upon processing of each variable node. Mathematically, this is represented as:
 
γ←γ⊕( v   i   old   ⊕v   i   new )· h   i   (7)
 
where v i   new   hd(P i ) is the updated hard decision i-th bit, and h i  denotes the i-th row of the parity check matrix  H .
 
     A popular way to perform min-sum decoding is to have variable nodes take log-likelihood ratios of received information from the channel as an initial input message (i.e., L i→j =L i   ch ) and employ the following equivalent check node update rule: 
                       L     j   →   i       =       [       ∏       i   ⁢       ′     ∈           V   ⁡   (   j   )     ∖   i           sign   (     L       i   ⁢   ′     →   j       )       ]     ·     ⌊         α   ·     min         i         ′     ∈       V   ⁡   (   j   )     ∖   i           ⁢       ❘   &#34;\[LeftBracketingBar]&#34;       L       i   ′     →   j         ❘   &#34;\[RightBracketingBar]&#34;         +   β     ⌋         ,           (   8   )               
where 0&lt;α and β&lt;1 are the attenuation factor and attenuation rounding parameter, respectively, which can be either pre-fixed or dynamically adjusted. These satisfy the requirement that:
 
α+β≥1.  (9)
 
This ensures that a minimum check node to variable node message of 1 is not attenuated to zero.
 
     Channel LLR inputs may be conveniently scaled for min-sum decoding but precise information is needed for the original sum-product decoding. The following notations help to simplify the above calculation in the algorithmic procedure. Let:
 
 s   i→j     hd ( L   i→j )  (10)
 
be the binary sign representation, which converts to the actual sign value in terms of:
 
sign( s )=(−1) s .
 
     Let s (j)  be the total sign of all variable nodes i&#39;s to the check nodes j:
 
 s   (j)   ⊕ i′∈V(j)   s   i′→j   (11)
 
     Let L 1   (j)  and i L     1     (j)  be the minimum variable node message to check node j and its associated index, respectively: 
                       L   1     (   j   )         =   Δ         min       i   ′     ∈     V   ⁡   (   j   )             ❘   &#34;\[LeftBracketingBar]&#34;       L       i   ′     →   j         ❘   &#34;\[RightBracketingBar]&#34;           ,            i     L   1       (   j   )         =   Δ           arg   ⁢   min           i   ′     ∈     V   ⁡   (   j   )           ⁢       ❘   &#34;\[LeftBracketingBar]&#34;       L       i   ′     →   j         ❘   &#34;\[RightBracketingBar]&#34;                   (   12   )               
and let L 2   (j)  be the second minimum (e.g., second lowest) variable node message to check node j:
 
     
       
         
           
             
               
                 
                   
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     Let {circumflex over (L)} 1   (j)  and {circumflex over (L)} 2   (j)  be the attenuated minimum and second minimum variable node messages to check node j, that is:
 
 {circumflex over (L)}   1   (j)     └α·L   1   (j)   +β┘,{circumflex over (L)}   2   (j)     └α·L   2   (j) +β┘  (14)
 
and therefore with the above notations, Equation (8) is conveniently re-expressed by:
 
     
       
         
           
             
               
                 
                   
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     A decoding success is declared if the all-zero syndrome results after the first full iteration. 
     When a QC-LDPC code with b×b circulants is in use, each circulant of b bits is updated independently and in parallel. 
     In hardware implementations of iterative message passing LDPC decoding, the decoding efficiency of min-sum decoding can be further improved using a layered approach. Layered min-sum decoding is based on a serial (e.g., sequential, ordered, etc.) update of check node messages. Instead of sending all messages from variable nodes to check nodes, and then all messages from check nodes to variable nodes, the layered coding goes over the check nodes in (some) sequential order such that, to each updating check node, all messages are sent in and processed, and then sent out to neighboring variable nodes. Such scheduled and/or serial updates to the check nodes enable immediate propagation of the newly updated message, unlike the flooded scheme where the updated messages can propagate only at the next iteration. To put it another way, the flooding approach is not amenable to stopping or pausing or decoding between decoding iterations and outputting the decoded codeword at that time whereas the scheduled and/or serial approach of layered decoding does permit or otherwise allow for this. 
     The layered min-sum decoding approach roughly increases convergence speed by two times compared to the flooded min-sum decoding approach. Moreover, it provides a good trade-off between speed and memory. This is achieved by iterating over dynamic check node to variable node messages, denoted by  Q   [Q 1 , Q 2 , . . . , Q n ]. Specifically, let variable node i∈V(j) and so Q i  over a layer j is defined as: 
                       Q   i     (   j   )         =   Δ         L     j   →   i       =       L   i     c   ⁢   h       +       ∑       j   ′     ∈       C   ⁡   (   i   )     ∖   j           L       j   ′     →   i       (   last   )               ,           (   16   )               
where the superscript (last)  denotes a latest updated piece of data. It is noted that in layered min-sum decoding, the variable node to check node message updated at the last layer (all but the last are from the current iteration) is utilized to update the check node to variable node Q i  in the current layer. In contrast, in flooded decoding updating, a check node to variable node message L j→i  utilizes the variable node to check node messages each generated at the last iteration.  Q   [Q 1 , Q 2 , . . . , Q n ] memory is initialized with the channel messages  L   ch   [L 1   ch , L 2   ch , . . . , L n   ch ] and no dedicated memory is needed to store  L   ch , whereas with the flooded approach  L   ch  is stored but not  Q . Q i , i=1, 2, . . . , n is iteratively calculated as follows. Let j be the current layer and j i  be the preceding layer associated with variable node i. A preceding layer is declared or otherwise defined (e.g., mathematically) as follows. Let j 1 &lt;j 2 &lt; . . . &lt;j k  be all check nodes directly connected to variable node i, then j l  (subscript letter l) is the preceding layer of j l+1  (subscript letter l plus number 1) for l=1, 2, . . . , k−1, and j k  is the preceding layer of j 1  (subscript number 1).
 
     The APP message P i  at the layer j is calculated as:
 
 P   i   (j)   =Q   i   (j     i     )   +L   j     i     →i   new   (17)
 
where L j     i     →i   new  (subscript j_sub_letter_i right arrow letter i) is newly updated and Q i  is iteratively updated by:
 
 Q   i   (j)   =P   i   (j)   −L   j→i   old   (18)
 
where L j→i   old  was saved during the preceding iteration. The layered decoding can be applied to all types of iterative message passing decoding, including the sum-product algorithm (SPA) and min-sum decoding. A hardware amenable layered min-sum decoding process without early convergence is described in  FIG.  4   .
 
       FIG.  4    is a diagram illustrating an example of a layered min-sum decoding process without early convergence. In this example, the process begins by initializing the data ( 400 ). In lines  1 - 8  ( 402 ), the process then goes through a first iteration of layered message passing and generates a decoded codeword ( v ) and syndrome (γ). 
     Line  9  ( 404 ) is the first opportunity for a (successfully) decoded codeword to be output. As shown in line  9 , the decoding process must be beyond the first iteration. This means that the first opportunity for the decoded codeword to be output in this older and slower technique is right after the first iteration when:  =0 (see, e.g., the for loop at line  1 ), j=0 (see, e.g., the for loop at line  2 ), and i=0 (see, e.g., the for loop at line  4 ). 
     Note the exemplary decoding process shown in  FIG.  4    treats each check node as a layer, such that   has single element. When a QC-LDPC code with b×b circulants is used, b check nodes within a circulant are treated as a layer, each being processed independently and in parallel. In this QC-LDPC scenario, line  1  ( 406 ) of the process shown in  FIG.  4    would instead be: 
                 1.         for   ⁢                ⁢   𝒥     =       {       t   ·   b     +   a     }       a   =   0       b   -   1         ,     t   =   0     ,   1   ,   2   ,   …         ,       m   b     -   1     ,           do   .           
To put it another way,   is a set iterating through indexes 0, 1, 2, . . . ,
 
                 m   b     -   1     ,         
such that  ={ab, ab+1, ab+2, . . . , ab+b−1}.
 
     Returning to the convergence check at the end of the first iteration at line  9  ( 404 ), the rationale behind this is based on the initialized values ( 400 ). Note that the decoded word ( v ) and syndrome (γ) are both initialized to all zeros. As a result, a false convergence (false positive) would occur if the syndrome were checked for all zeros (e.g., check if the syndrome vector indicates that decoding successful and all errors have been removed) at the beginning of an iteration. In contrast, at the end of decoding (e.g., at the end of the first full decoding iteration), all variable bits are updated by the decoder, thus truly reflecting a decoded word. Therefore, it is safe to check for convergence after the first iteration and to terminate the decoder when the syndrome is all zeros. 
     Although checking the syndrome at the end of the first full iteration (as shown in  FIG.  4   ) is a safe choice that ensures no false positives, with layered decoding it is possible to check the syndrome earlier than that while still ensuring that no false positives will occur. For example, note that the column weight of all practical LDPC parity check matrices  H  is at least 2 (i.e., w≥2). As a result, each variable bit is processed at least 2 times by the layered decoder in single iteration. In some cases (e.g., when there are only a few errors), a single pass by the decoder is sufficient to remove all errors and the second pass in that iteration (e.g., dictated by an exemplary column weight of 2) is not necessary. In other words, in some cases, it may only take a fraction of an iteration to successfully process all variable bits. Therefore, in some embodiments with early convergence, the number of unprocessed variable bits (e.g., the bits that are output by the variable nodes) is tracked and a syndrome check is performed as soon as the count reaches zero. The following figures show an example of this. 
       FIG.  5    is a diagram illustrating an embodiment of a layered min-sum low-density parity-check (LDPC) decoder that monitors states to determine when an early convergence checkpoint has occurred. To preserve the readability of the diagram, some elements that are not relevant to the technique (e.g., check nodes) are not shown. 
     In a non-QC-LDPC example, there are n variable nodes ( 500 ) that output a plurality of variable bits. n monitoring blocks ( 502 ) each input a corresponding variable bit and determine when that variable bit (variable node) has been (e.g., sufficiently) processed so that if a check of the syndromes were performed, a false positive would not result. For example, if a state signal output by a monitor ( 502 ) is a value of 1 (as an example), that means that the corresponding variable node or variable bit has had at least some LDPC decoding performed on it (e.g., so a syndrome which is generated from that variable node or variable bit can be trusted), whereas a 0 means that the corresponding variable bit has not yet been (e.g., sufficiently) processed. The monitoring blocks are illustrative and/or exemplary to convey the concept and in some embodiments are not necessary because there is already a signal within the system that can be reused or otherwise repurposed as the state signal. 
     The state signals generated by the monitoring blocks ( 402 ) are input to an AND block ( 504 ) to generate a collective state signal. The collective state signal is a 1 when all of the variable bits have been processed (e.g., indicated by the state signals all being 1). 
     The collective state signal is input by a layered min-sum decoding controller ( 506 ). When the collective state signal goes from a 0 to a 1, LDPC decoding is paused (e.g., message passing is paused) while the controller ( 506 ) checks the syndrome ( 508 ) to see if the syndrome is all zeros. If the syndrome ( 508 ) is all zeros, then the controller ( 506 ) outputs the decoded codeword ( 510 ) as the output data. 
     In some embodiments, a QC-LDPC code is used. In such embodiments, the  H  matrix is a quasi-cyclic  H  matrix where all bits within a circulant are processed in parallel. Therefore, in QC-LDPC embodiments, it is sufficient to track the number of unprocessed circulants. As shown herein, in a QC-LDPC example, the monitoring blocks ( 502 ) track the state of the circulants ( 500 ) instead of variable nodes. It is noted that there are (up to) 
             n   b         
circulants (as opposed to n variable nodes in the non-QC-LDPC example), so the number of monitoring blocks ( 502 ) is adjusted accordingly so that there are b monitoring blocks.
 
     The following figures describe this more formally and/or generally in a flowchart. 
       FIG.  6 A  is a flowchart illustrating an embodiment of a low-density parity-check (LDPC) decoding process with early convergence that monitors check node states to determine when an early convergence checkpoint has occurred.  FIG.  6 A  is related to  FIG.  1    and for convenience the same or similar reference numbers are used to indicate related steps. 
     At  100 , LDPC encoded data with one or more errors is received. 
     At  102   a , information associated with an early convergence checkpoint is received, including by receiving a collective state signal that is based at least in part on a plurality of states associated with a plurality of variable nodes. For example, in  FIG.  5   , the collective state signal is output by the AND block ( 504 ) based on the state signals from the monitoring blocks ( 502 ). 
     At  104   a , the information associated with the early convergence checkpoint is used to perform decoding on the LDPC encoded data up to the early convergence checkpoint and generate a decoded codeword, wherein the early convergence checkpoint is prior to a first complete iteration of the layered min-sum LDPC decoding; and in response to the collective state signal indicating that the early convergence checkpoint has been reached, pausing the LDPC decoding, wherein the LDPC decoding includes layered min-sum LDPC decoding. For example, the controller ( 506 ) in  FIG.  5    may stop message passing between the variable nodes ( 500 ) and check nodes in response to assertion of the collective state signal so that the controller can check the syndrome ( 508 ). 
     The process then continues to step  106  in  FIG.  1    and proceeds as described above. 
       FIG.  6 B  is a flowchart illustrating an embodiment of a low-density parity-check (LDPC) decoding process with early convergence that monitors circulant states to determine when an early convergence checkpoint has occurred.  FIG.  6 B  is related to  FIG.  1    and for convenience the same or similar reference numbers are used to indicate related steps. 
     At  100   b , LDPC encoded data with one or more errors is received, wherein the LDPC encoded data includes QC-LDPC encoded data. 
     At  102   b , information associated with an early convergence checkpoint is received, including by receiving a collective state signal that is based at least in part on a plurality of states associated with a plurality of circulants. As described above, with QC-LDPC codes, it is sufficient to monitor the circulants. This is more efficient (for QC-LDPC embodiments) than monitoring all of the variable nodes (as an example) since there are fewer circulants than variable nodes and so less monitoring logic and/or routing is used when circulants are monitored. 
     At  104   b , the information associated with the early convergence checkpoint is used to perform layered min-sum LDPC decoding on the LDPC encoded data up to the early convergence checkpoint and generate a decoded codeword, including by in response to the collective state signal indicating that the early convergence checkpoint has been reached, pausing the layered min-sum LDPC decoding, wherein the early convergence checkpoint is prior to a first complete iteration of the layered min-sum LDPC decoding and the LDPC decoding includes layered min-sum LDPC decoding. 
     The process then continues to step  106  in  FIG.  1    and proceeds as described above. 
     Depending upon the implementation and/or application, a different embodiment for determining when the early convergence checkpoint has occurred may be desirable. For example, suppose that due to the specific implementation of a layered min-sum decoder, the variable nodes or circulants are spread out. Monitoring (some examples of which are described in  FIGS.  5 - 6 B ) may therefore consume more routing area than is desirable for some applications. Or (again due to the specific implementation), the size of monitoring blocks (e.g.,  502  in  FIG.  5   ) may be larger than is desirable for some applications. For these reasons, it may be desirable to have other approaches for determining when the early convergence checkpoint has occurred. The following examples describe (pre-)calculating a fractional iteration count where a layered min-sum decoding controller stops when the current fractional iteration count reaches the target fractional iteration count. 
     With layered min-sum decoding, the sequence in which decoding is performed in the various layers (e.g., the ordering and/or timing when variable bits (circulants for QC-LDPC parallel processing) are processed within the first layer, the second layer, etc.) is known ahead of time. This known sequencing or ordering permits the exact layer number (denoted by τ) along with the associated variable index (circulant index for QC-LDPC parallel processing) (denoted by τ′) that corresponds to zero unprocessed variable bits (circulants for QC-LDPC parallel processing) which in turn permit a fractional iteration count (denoted by η) to be calculated or otherwise determined as: 
                   η     =   Δ         τ   m     +       τ   ′       m   ·     ω   τ                   (   19   )               
where m is the number of layers of  H  (or m/b in the case of QC parallel processing), and ω τ  denotes the weight of the τ-th layer. The layered min-sum decoder would then track the fractional iteration and when the current fractional iteration count exceeds the fractional iteration count η, decoding would be paused (e.g., at the next convenient point, such as at the end of the next layer).
 
     The following figures show a visual example of this calculation using a QC-LDPC example. 
       FIG.  7 A  is a diagram illustrating an embodiment of QC-LDPC circulants in an  H  matrix that are processed during a first layer. In this example, the  H  matrix ( 700   a ) gives the layered decoding schedule in which circulants (represented by shifted identity matrices I 0 , I 1 , I 2 , . . . , I 47 ) are iteratively processed in sequential order. In this example, the  H  matrix ( 700   a ) has 6 layers (note, for example, the 6 rows in the  H  matrix) and a constant weight of 3 (e.g., each layer or row is processed three times). 
     During the first layer ( 702 ), shifted identity matrices I 0 -I 6  are processed. Columns with a non-zero value (i.e., a circulant) that are processed during the first iteration are indicated using a check mark above those columns. 
       FIG.  7 B  is a diagram illustrating an embodiment of QC-LDPC circulants in an  H  matrix that are processed during a second layer. During the second layer ( 710 ), the shifted identity matrices I 7 -I 14  in the  H  matrix ( 700   b ) are processed. Check marks have been added above those columns that contain those shifted identity matrices processed in the second layer (i.e., the check marks shown are cumulative). 
       FIG.  7 C  is a diagram illustrating an embodiment of QC-LDPC circulants in an  H  matrix that are processed during a third layer. During the third layer ( 720 ), shifted identity matrices I 15 -I 22  in the  H  matrix ( 700   c ) are processed. Prior to the end of the third layer (e.g., going from left to right), I 20  ( 722 ) is the circulant at which all of the columns have been processed at least once with a non-zero value and/or circulant. Note, for example, that there is a check mark above each column when the processing sequence reaches I 20  ( 722 ). 
     Once all of the columns in the  H  matrix have been processed at least once with a non-zero value, this corresponds to a state in which there are zero unprocessed circulants (or variant bits) and it is therefore safe to check the syndromes to see if the decoding process can stop because all of the errors have been removed. In other words, I 20  ( 722 ) corresponds to the early convergence checkpoint at which a check of the decoder can safely be performed without worry about false positives. 
     Returning to Equation (19), the fractional iteration count (η) would be calculated using the QC-LDPC version of Equation (19) as 
                 η     Q   ⁢   C         =   Δ           τ     m   b       +       1     m   b       ·       τ   ′       ω   τ           =         2   6     +       1   6     ·     5   8         =     7     1   ⁢   6             ,         
wherein ω τ  denotes the Hamming weight of the τ-th layer, and τ′ denotes the threshold index of the last unprocessed circulant. Conceptually, the first term in the sum represents the number of complete or full layers to reach I 20  ( 722 ), in this case the first layer ( 702 ) in  FIG.  7 A  and the second layer ( 710 ) in  FIG.  7 B  out of 6 layers total. The second term in the sum represents the partial or fractional portion of the last layer to reach I 20  ( 722 ), in this case the number of columns in the third row ( 720 ) to reach I 20  ( 722 ) going from left to right in  FIG.  7 C .
 
     As a practical matter, it may be difficult to pause decoding in the middle of a layer. For example, in  FIG.  7 C , it may be difficult or impossible in some implementations to pause processing exactly after I 20  ( 722 ) and it may be more practical or feasible to pause processing at the end of the third layer ( 720 ). Accordingly, a simpler and/or more hardware convenient fractional iteration count (η simplified ) may be calculated as follows: 
                     η     simplified   ,   QC         =   Δ       τ     m   b               (   20   )               
where the equation is given for non-QC-LDPC codes. Conceptually, in the context of the  H  matrix ( 700   c ) shown in  FIG.  7 C , η simplified  is the number of full layers or rows to reach I 21  ( 722 ) plus one for the last (e.g., partial) layer or row that contains I 21  ( 722 ), divided by the total number of layers or rows
 
               (       i   .   e   .     ,       η     simplified   ,   QC         =   Δ         τ     m   b       =       2   6     =     1   3             )     .         
Another way to describe this is to say that it&#39;s not worth the effort of precisely calculating the second term in Equation (19) for those embodiments where the decoder cannot easily or feasibly stop in the middle of a layer or row, so the second term in Equation (19) is “rounded up” to the equivalent of a full layer or row.
 
     Returning briefly to the decoding example shown in  FIG.  4   , with the above technique, line  9  ( 404 ) would be replaced with: “If the syndrome γ=0 and the fractional iteration number &gt;η (any appropriate variety), then return the decoded codeword  v .” However, unlike the example of  FIG.  4   , the process described herein does not need to finish a complete or entire iteration before checking if all of the errors have been removed. 
     The following figure describes these examples more formally and/or generally in a flowchart. 
       FIG.  8    is a flowchart illustrating an embodiment of a low-density parity-check (LDPC) decoding process with early convergence that uses a fractional iteration count.  FIG.  8    is related to  FIG.  1    and for convenience the same or similar reference numbers are used to indicate related steps. 
     At  100 , LDPC encoded data with one or more errors is received. In some embodiments, the LDPC encoded data is QC-LDPC encoded data. 
     At  102   c , information associated with an early convergence checkpoint is received, including by receiving a fractional iteration count. For example, the fractional iteration count (η) may be calculated per Equation (19) or the fractional iteration count (η simplified ) may be calculated per Equation (20). 
     At  104   c , the information associated with the early convergence checkpoint is used to perform layered min-sum LDPC decoding on the LDPC encoded data up to the early convergence checkpoint and generate a decoded codeword, including by receiving a current iteration of the LDPC decoding; and in response to the current iteration exceeding the fractional iteration count, pausing the LDPC decoding, wherein the early convergence checkpoint is prior to a first complete iteration of the LDPC decoding and the LDPC decoding includes layered min-sum decoding. 
     As described above, in some cases there may be certain points at which it is easier or more convenient to pause decoding (e.g., at the end of a layer) and in some embodiments, the decoding is paused there. 
     The process then continues to step  106  in  FIG.  1    and proceeds as described above. 
     Returning briefly to  FIGS.  7 A- 7 C , it is noted that the  H  matrix can be pre-permuted on rows or columns (e.g., to optimize certain hardware design metrics, such as minimize η), while still retaining the code characteristics. The following figure shows an alternate form of the  H  matrices shown in  FIGS.  7 A- 7 C . 
       FIG.  9    is a diagram illustrating an embodiment of a permuted  H  matrix. In this example, the  H   per  matrix ( 900 ) is a permutation of the  H  matrix ( 700   a - 700   c ) shown in  FIGS.  7 A- 7 C . This matrix permutation or manipulation still maintains the code characteristics. 
     With the permutation shown in  H   per  matrix ( 900 ), the decoder performs processing up to I 22  ( 902 ) to ensure that all of the circulants (or variable bits) have been processed so that it is safe to check the syndromes. In this example, I 22  ( 902 ) is located in the second row or layer and so the decoder would be “on” for a shorter duration before the early convergence checkpoint in this example compared to the example of  FIGS.  7 A- 7 C . In other words, permutated or alternate forms of the  H  matrix (i.e., associated with different sequences or orderings) but which still have the appropriate code characteristics may be explored in order to minimize the amount of time before the early convergence checkpoint occurs. 
     The following figure describes these examples more formally and/or generally in a flowchart. 
       FIG.  10    is a flowchart illustrating an embodiment of a process to determine a minimal fractional iteration count. In some embodiments, this process is used to determine a fractional iteration count that is received as (part of) the information associated with an early convergence checkpoint at step  102  in  FIG.  1   . 
     At  1000 , a first layered decoding scheduling and a second layered decoding scheduling are received. As used herein, layered decoding scheduling refers to the schedule by which (e.g., a particular implementation of) layered min-sum decoding is performed. For example, the  H  matrices ( 700   a - 700   c ) in  FIGS.  7 A- 7 C  show one layered decoding scheduling and the  H   alt  matrix ( 900 ) in  FIG.  9    shows another layered decoding scheduling. 
     At  1002 , a first potential fractional iteration count is determined based at least in part on the first layered decoding scheduling. At  1004 , a second potential fractional iteration count is determined based at least in part on the second layered decoding scheduling. See, for example, Equations (19) and (20) and the example described in  FIGS.  7 A- 7 C . Although this example only describes two schedules and two potential fractional iteration counts, any number may be input and generated, respectively. 
     At  1006 , a minimum one of the first potential fractional iteration count or the second potential fractional iteration count is selected to be the fractional iteration count. For example, a lower fractional iteration count permits the early convergence checkpoint to be reached sooner so that more power and/or processing resources can be conserved. 
     Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed embodiments are illustrative and not restrictive.