Patent Publication Number: US-11394291-B2

Title: Ripple voltage control circuit and control method thereof

Description:
RELATED APPLICATIONS 
     This application claims the benefit of Chinese Patent Application No. 202010284553.X, filed on Apr. 13, 2020, which is incorporated herein by reference in its entirety. 
     FIELD OF THE INVENTION 
     The present invention generally relates to the field of power electronics, and more particularly to ripple voltage control circuits and methods. 
     BACKGROUND 
     A switched-mode power supply (SMPS), or a “switching” power supply, can include a power stage circuit and a control circuit. When there is an input voltage, the control circuit can consider internal parameters and external load changes, and may regulate the on/off times of the switch system in the power stage circuit. Switching power supplies have a wide variety of applications in modern electronics. For example, switching power supplies can be used to drive light-emitting diode (LED) loads. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic block diagram of an example ripple voltage control circuit based on constant on-time control. 
         FIG. 2  is a waveform diagram of example operation of the ripple voltage control circuit based on constant on-time control. 
         FIG. 3  is a schematic block diagram of an example ripple voltage control circuit, in accordance with embodiments of the present invention. 
         FIG. 4  is a waveform diagram of a first example operation of the ripple voltage control circuit, in accordance with embodiments of the present invention. 
         FIG. 5  is a schematic diagram of an example constant on-time generation circuit, in accordance with embodiments of the present invention. 
         FIG. 6  is a schematic diagram of an example ripple generation circuit, in accordance with embodiments of the present invention. 
         FIG. 7  is a schematic diagram of an example ripple compensation circuit, in accordance with embodiments of the present invention; 
         FIG. 8  is a waveform diagram of a second example operation of the ripple voltage control circuit, in accordance with embodiments of the present invention. 
         FIG. 9  is a schematic block diagram of another example ripple voltage control circuit, in accordance with embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Reference may now be made in detail to particular embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention may be described in conjunction with the preferred embodiments, it may be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it may be readily apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, processes, components, structures, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention. 
     Among the control method for buck converters, the ripple voltage control method based on constant on-time (COT) control has become the preferred approach for high-current buck converters due to its relatively small output ripple under light load and superior dynamic performance. In this control method, the simulated ripple voltage of the inductor current is superimposed on a feedback voltage of the converter. An inverting input terminal of an error comparator may receive the superimposed signal, and a non-inverting input terminal of the error comparator may receive a reference signal. When the superimposed signal is lower than the reference signal, the output signal generated by the error comparator switches to be a high level. Then, the pulse-width modulation (PWM) trigger/flip-flop can be controlled to generate a turn-on signal for the upper transistor of the buck converter. The upper transistor of the buck converter can then be turned on for a constant on-time, and then turned off. Then, the lower transistor can be turned on until the output signal of the error comparator switches to be a high level again, thereby realizing a steady state. 
     Referring now to  FIG. 1 , shown is a schematic block diagram of an example ripple voltage control circuit based on COT control. In this particular example, a non-inverting input terminal of the error comparator may receive reference voltage V REF , and an inverting input terminal of the error comparator may receive a superposition of ripple voltage V RIPPLE  of the simulated inductor current and feedback voltage V FB . In such a case, feedback voltage V FB  may not be directly compared against reference voltage V REF , such that feedback voltage V FB  may not be equal to reference voltage V REF  when the buck converter operates under the steady state without a steady-state error correction circuit. Moreover, feedback voltage V FB  and reference voltage V REF  can differ by a DC bias voltage. In order to eliminate the DC bias voltage resulting from ripple voltage V RIPPLE , error correction signal V CORR  generated by an error correction signal generation circuit can typically be superimposed on reference voltage V REF . 
     For example, the error correction signal generation circuit can mainly include an error integrator, receiving feedback voltage V FB  and reference voltage V REF . If there is a deviation between feedback voltage V FB  and reference voltage V REF , the error integrator can be adjusted to generate an appropriate level, in order to obtain error correction signal V CORR , and thereby eliminating the deviation by superimposing error correction signal V CORR  on reference voltage V REF . After the steady-state error is eliminated, error correction signal V CORR  may be less than zero and equal to 50% of the peak-to-peak value of ripple voltage V RIPPLE . In this example, there are actually two voltage loops. The voltage inner loop can quickly respond to the dynamic change of the load, and the voltage outer loop can eliminate steady-state error under the steady-state operation. The adjustment can be fast due to the voltage inner loop, while the adjustment can be slow due to the voltage outer loop, which is disadvantageous for fast dynamic performance. 
     Referring now to  FIG. 2 , shown is a waveform diagram of an example operation of the ripple voltage control circuit based on COT control. In this example, since output voltage V OUT  rises highly after the heavy load turns to the no load, feedback voltage V FB  may always be higher than reference voltage V REF . Therefore, the error integrator always may operate in the reverse integration state, and correction signal V CORR  can move in the negative direction. At this time, output current I OUT  can make a rapid transition from the no load to the heavy load, correction signal V CORR  may remain at a relatively low position at the moment of the load transition, and the adjustment of this voltage loop is relatively slow, resulting in a lack of recovery to a high position in a short time. Thus, output voltage V OUT  can drop deeply. Vdrop as shown is the excess output voltage drop caused by the presence of correction signal V CORR . In this way, the introduction of correction signal V CORR  may have an adverse effect on the dynamic performance. 
     Referring now to  FIG. 3 , shown is a schematic block diagram of an example ripple voltage control circuit, in accordance with embodiments of the present invention. In this particular example, the ripple voltage control circuit can include control circuit  31  and constant on-time generation circuit  32 . Control circuit  31  can generate ripple signal V NEG  by superimposing ripple voltage V RIPPLE  and compensation voltage V COMP  on feedback voltage V FB  that represents output voltage V OUT  of the switching converter. Reference signal V POS  can be generated by superimposing bias voltage offset on reference voltage V REF . Ripple signal V NEG  can be compared against reference signal V POS  in order to generate turn-on signal Vs for the main power switch of the switching converter. For example, control circuit  31  can include ripple generation circuit  311  for generating ripple voltage V RIPPLE , and ripple compensation circuit  312  for generating compensation voltage V COMP . 
     Compensation voltage V COMP  may adaptively vary with duty cycle D of the main power switch, such that ripple signal V NEG  is independent of duty cycle D and the trough of ripple signal V NEG  is also independent of duty cycle D. Control circuit  31  can also include comparison circuit  313 , which can include comparator CMP 1 . For example, a non-inverting terminal and an inverting terminal of comparator CMP 1  may respectively receive reference signal V POS  and ripple signal V NEG , and an output terminal of comparator CMP 1  can generate turn-on signal Vs. Constant on-time generation circuit  32  can compare on-time reference signal V 2  against ramp signal Vramp in order to generate turn-off signal rst to turn off the main power switch. 
     In particular embodiments, the peak-to-peak value of ripple voltage V RIPPLE  can be determined when the switching converter operates in the steady state with a certain/predetermined duty cycle based on COT control. Moreover, the peak-to-peak value of ripple voltage V RIPPLE  can be calculated with the variation curve of the duty cycle (e.g., in a linear relationship therewith). For example, the adaptive compensation voltage V COMP  can also be superimposed on the superimposed voltage of ripple voltage V RIPPLE  and feedback voltage V FB , thereby generating ripple signal V NEG . When switching mode converter operates with different duty cycles or different output voltages, the valley of ripple signal V NEG  can be maintained at the same horizontal line. That is, the valley value of ripple signal V NEG  can be maintained at the same threshold under different duty cycles or different voltages. In this way, it can be realized that feedback voltage V FB  is equal to reference voltage V REF  by superimposing bias voltage offset on reference voltage V REF  without an error correction circuit. 
     Referring now to  FIG. 4 , shown is a waveform diagram of a first example operation of the ripple voltage control circuit in accordance with embodiments of the present invention. In this particular example, bias voltage offset1 is half of the peak-to-peak value of ripple voltage V RIPPLE . That is: offset1=Vpp/2, and bias voltage offset2 is the peak-to-peak value of compensation voltage V COMP . In order to maintain feedback voltage V FB  as equal to reference voltage V REF , the sum of bias voltages offset1 and offset2 should be equal to bias voltage offset; that is: offset1+offset2=offset. In order to calculate the value of compensation voltage V COMP  that is to be superimposed, the relationship between peak-to-peak value Vpp of ripple voltage V RIPPLE , output voltage Vout, and duty cycle D is derived. 
     Referring now to  FIG. 5 , shown is a schematic diagram of an example constant on-time generation circuit, in accordance with embodiments of the present invention. In this particular example, some node voltages in the constant on-time generation circuit can be used to generate ripple voltage V RIPPLE . In this particular example, a buck converter is utilized, main power switch HS and rectifier power switch LS are shown, and inductors and capacitors of the power stage circuit are not shown. Constant on-time generation circuit  32  can include reference signal generation circuit  51 , ramp signal generation circuit  52 , and comparator  53 . For example, reference signal generation circuit  51  can include controlled current source CCS 1 , switch K 1 , resistor R 1 , and a filter circuit with a relatively large RC time constant. 
     Controlled current source CCS 1  can be controlled by input voltage V IN , and may generate current Iref that is proportional to input voltage V IN . Switch K 1  can be controlled by signal PWM to be turned on and off synchronously with main power switch HS. Resistor R 1  can connect between switch K 1  and ground. The filter circuit can be configured as a “π”-shaped RC filter circuit including capacitor C 1 , resistor R 2 , and capacitor C 5 . Here, in constant on-time generation circuit  32 , current Iref may flow through resistor R 1  under the control of switch K 1  forming a voltage drop. Further, the filter circuit can average signal V 1  across resistor R 1 , and may generate the average value of signal V 1  (e.g., on-time reference signal V 2 ). For example, on-time reference signal V 2  is equal to n1 times of output voltage V OUT  (e.g., V 2 =n 1 *V OUT ), and n1 is the coefficient. Ramp signal generation circuit  52  can include controlled current source CCS 2 , switch K 2 , and capacitor C 2 . For example, controlled current source CCS 2  can be controlled by input voltage V IN , and may generate current Tramp that is proportional to input voltage V IN . 
     Capacitor C 2  and switch K 2  can connect in parallel between the output terminal of controlled current source CCS 2  and ground, and switch K 2  can be controlled by signal PWMB to be turned on and off in the opposite way as main power switch HS. When main power switch HS is turned on, switch K 1  can be turned on, and switch K 2  turned off. When main power switch HS is turned off, switch K 1  can be turned off, and switch K 2  turned on. When switch K 2  is turned off, capacitor C 2  may be charged by current Iramp, such that ramp signal Vramp rises linearly. When switch K 2  is turned on, capacitor C 2  may be short-circuited and discharged, such that ramp signal Vramp quickly drops to zero and maintains at zero until switch K 2  is turned off again. Thus, ramp signal Vramp may have a ramp-shaped waveform. Moreover, comparator  53  can compare on-time reference signal V 2  against ramp signal Vramp, and may generate turn-off signal rst for the main power switch. When the buck converter operates in the steady state, the charging and discharging of capacitor C 2  establishes ampere-second balance. Moreover, signal V 1  across resistor R 1  can essentially be a stable triangular wave, and the phase of signal V 1  can be the same as that of the inductor current. After being filtered by the filter circuit with a large RC time constant, on-time reference signal V 2  (e.g., the average value of voltage V 1 ) can be obtained. 
     Referring now to  FIG. 6 , shown is a schematic diagram of an example ripple generation circuit in accordance with embodiments of the present invention. In particular embodiments, the ripple generation circuit can include a voltage-controlled voltage source. The voltage-controlled voltage source can receive signal V 1  and on-time reference signal V 2 , and may generate ripple voltage V RIPPLE . For example, ripple voltage V RIPPLE  may be proportional to the difference between signal V 1  and on-time reference signal V 2 . That is, V RIPPLE =k*(V 1 −V 2 ), and k is the proportional coefficient. The following formulas can be obtained as shown below in (1) and (2). 
     
       
         
           
             
               
                 
                   
                     V 
                     2 
                   
                   = 
                   
                     
                       
                         
                           V 
                           IN 
                         
                         
                           R 
                           IN 
                         
                       
                       * 
                       R 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                       * 
                       D 
                     
                     = 
                     
                       
                         n 
                         1 
                       
                       * 
                       
                         V 
                         OUT 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       V 
                       PP 
                     
                     2 
                   
                   = 
                   
                     
                       
                         
                           k 
                           * 
                           
                             T 
                             SW 
                           
                         
                         
                           2 
                           * 
                           
                             R 
                             IN 
                           
                           * 
                           
                             C 
                             1 
                           
                         
                       
                       * 
                       
                         V 
                         OUT 
                       
                       * 
                       
                         ( 
                         
                           1 
                           - 
                           D 
                         
                         ) 
                       
                     
                     = 
                     
                       m 
                       * 
                       
                         V 
                         OUT 
                       
                       * 
                       
                         ( 
                         
                           1 
                           - 
                           D 
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     Here, T SW  is the switching cycle. It can be seen that V PP /2 (e.g., bias voltage offset  1 ) as a roughly linear relationship with duty cycle D, and its slope is related to output voltage V OUT . In order to eliminate the influence by the change of duty cycle D, compensation voltage V COMP  should meet the following formula (3).
 
 V   COMP   =m*V   OUT   *D   (3)
 
     Thus, compensation voltage V COMP  should be proportional to duty cycle D and also proportional to output voltage V OUT . For example, compensation voltage V COMP  should be proportional to the product of output voltage V OUT  and duty cycle D. As discussed above, the ripple compensation circuit can generate compensation voltage V COMP  by constructing the information of V OUT *D, and then scaling by m times. 
     Referring now to  FIG. 7 , shown is a schematic diagram of an example ripple compensation circuit in accordance with embodiments of the present invention. In particular embodiments, on-time reference signal V 2  that represents the information of output voltage V OUT  is shown in constant on-time generation circuit  32 . For example, the ripple compensation circuit can include a current source controlled by on-time reference signal V 2 . The ripple compensation circuit can also include a switch controlled by signal PWM and connected in series with the current source. The ripple compensation circuit can also include a filter circuit, including resistor R 4  and capacitor C 3 , and connected to the switch and that can generate signal V 3  that represents the information of V OUT *D (e.g., a product of the output voltage and the duty cycle). 
     The ripple compensation circuit can also include a compensation voltage generation circuit that generates compensation voltage V COMP  according to signal V 3 . For example, the compensation signal generation circuit can include a current source controlled by signal V 3 . The compensation signal generation circuit can also include a switch controlled by signal PWM and signal PWMB and connected with the current source controlled by signal V 3 . The compensation signal generation circuit can also include capacitor C 4  charged by current I OD  that is generated by the current source controlled by signal V 3 , and a switch controlled by a pulse generated at the rising-edge of signal PWM. For example, compensation voltage V COMP  can be formed across capacitor C 4 , and the switching converter may operate on the continuous conduction mode (CCM), such that compensation voltage V COMP  is a sawtooth wave signal. As discussed above, the following formulas (4) and (5) can be obtained as shown. 
     
       
         
           
             
               
                 
                   
                     V 
                     3 
                   
                   = 
                   
                     
                       
                         V 
                         2 
                       
                       * 
                       
                         1 
                         
                           R 
                           OUT 
                         
                       
                       * 
                       
                         R 
                         3 
                       
                       * 
                       D 
                     
                     = 
                     
                       
                         
                           n 
                           1 
                         
                         * 
                         
                           1 
                           
                             R 
                             OUT 
                           
                         
                         * 
                         
                           R 
                           3 
                         
                         * 
                         
                           V 
                           OUT 
                         
                         * 
                         D 
                       
                       = 
                       
                         
                           n 
                           2 
                         
                         * 
                         
                           V 
                           OUT 
                         
                         * 
                         D 
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
             
               
                 
                   
                       
                   
                   ⁢ 
                   
                     
                       V 
                       COMP 
                     
                     = 
                     
                       
                         
                           V 
                           3 
                         
                         * 
                         
                           1 
                           
                             R 
                             OD 
                           
                         
                         * 
                         
                           
                             T 
                             SW 
                           
                           
                             C 
                             4 
                           
                         
                       
                       = 
                       
                         
                           n 
                           3 
                         
                         * 
                         
                           V 
                           OUT 
                         
                         * 
                         D 
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     When coefficient n3 is set to be m, the following formula (6) can be obtained.
 
 V   COMP   =m*V   OUT   *D   (6)
 
     In particular embodiments, new circuit parameters can be constructed and realized by utilizing existing circuit parameters, such that the circuit can be simplified. In order to maintain feedback voltage V FB  as equal to reference voltage V REF , the following formula (7) should be met. 
     
       
         
           
             
               
                 
                   offset 
                   = 
                   
                     
                       
                         offset 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       + 
                       
                         offset 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                     = 
                     
                       
                         
                           
                             V 
                             
                               P 
                               ⁢ 
                               P 
                             
                           
                           2 
                         
                         + 
                         
                           V 
                           COMP 
                         
                       
                       = 
                       
                         m 
                         * 
                         
                           V 
                           OUT 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     Therefore, a fixed bias voltage offset is received by the input terminal of comparator CMP 1 , with a value of m*V OUT , thereby realizing a design without an error correction circuit. Since bias voltage offset is proportional to output voltage V OUT  and on-time reference signal V 2  that represents information of output voltage V OUT  exists in the constant on-time circuit  32 , bias voltage offset can be set as proportional to on-time reference voltage V 2 , such that the bias voltage offset that meets the requirements can be obtained by a simple circuit. 
     Referring now to  FIG. 8 , shown is a waveform diagram of a second example operation of the ripple voltage control circuit, in accordance with embodiments of the present invention. In this particular example, when the switching converter operates with a certain duty cycle in the steady state at a certain output voltage V OUT , compensation voltage V COMP  can be determined by ripple compensation circuit  312 . Then, the determined compensation voltage V COMP  and ripple voltage V RIPPLE  may be superimposed on feedback voltage V FB  to generate ripple signal V NEG . Moreover, bias voltage offset can be superimposed on reference voltage V REF  as reference signal V POS . Further, ripple signal V NEG  can be compared against reference signal V POS , in order to generate turn-on signal Vs for the main power switch of the switching converter. 
     With appropriate design, the valley value of ripple signal V NEG  can be maintained at a certain threshold with ripple voltage V RIPPLE  and compensation voltage V COMP , such that bias voltage offset superimposed on reference voltage V REF  can be offset. In such a case, it can be realized that feedback voltage V FB  is maintained as equal to reference voltage V REF  when the switching converter operates with different duty cycles without an error correction circuit. Since the error correction circuit is not applied in the ripple voltage control circuit, the dynamic performance can be greatly improved when the load changes. 
     It can be understood that the peak-to-peak value of ripple voltage V RIPPLE  increases as the duty cycle decreases. Therefore, the clamp value of the error correction circuit may be selected the maximum peak-to-peak value of ripple voltage V RIPPLE . However, such a large clamp value can be excessive for the switching converter with a large duty cycle. In particular embodiments, compensation voltage V COMP  may adaptively vary along with duty cycle D of the main power switch, such that ripple signal V NEG  is independent of duty cycle D and the valley value of ripple signal V NEG  is also independent of duty cycle D. as such, the difficulty of setting the peak-to-peak value of ripple voltage V RIPPLE  under a full duty cycle can be reduced and the stability can be improved under a large duty cycle when the peak-to-peak value of ripple voltage V RIPPLE  is too small. For example, an error correction loop with a very narrow clamp value can also be kept in order to compensate for the error caused by the intermediate parameter transfer and the ripple of feedback voltage V FB  itself. 
     Referring now to  FIG. 9 , shown is a schematic block diagram of another example ripple voltage control circuit, in accordance with embodiments of the present invention. In this particular example, error correction circuit  314  can be applied in the ripple voltage control circuit. Error correction circuit  314  can substantially eliminate the steady-state error of the output voltage caused by the ripple of feedback voltage V FB . For example, error correction circuit  314  can generate error correction signal V CORR1  according to feedback voltage V FB  and reference voltage V REF . Then, bias voltage offset and error correction signal V CORR1  can be superimposed on reference voltage V REF  as reference signal V POS . Since the clamping value of the error correction circuit no longer needs to be set according to the maximum peak-to-peak value of ripple voltage V RIPPLE , the clamping value can be relatively small in this case. 
     The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with modifications as are suited to particular use(s) contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.