Patent Publication Number: US-4319084-A

Title: Multichannel digital speech synthesizer

Description:
FIELD OF THE INVENTION 
     Our present invention relates to a digital synthesizer of sound waves for electronically producing artificial speech. 
     BACKGROUND OF THE INVENTION 
     In the field of telecommunications, the synthesis of speech is of particular interest. It permits people unskilled in computer technology to receive so-called canned messages, e.g. by telephone, without the necessity of employing full-time human operators or of using costly subscriber terminals. Such messages may inform a calling subscriber of congestion at an exchange, of the cost and duration of a call, and of a changed directory number. 
     A digital system for synthesizing speech stores words or portions of words in coded form, a decoder being necessary to convert the digitally encoded signals into voice signals suitable for conventional transduction into sound waves. One particular system for the synthesis of speech elements stores PCM-coded waveform samples of diphones, i.e. phoneme pairs. Such a system generates a staccato-sounding speech and has the further disadvantage of requiring a large memory. 
     In an attempt to achieve natural-sounding synthesis, coding techniques have been developed on the basis of mathematical models simulating the production of speech by a human vocal tract. According to one model, the vocal tract is replaced by the combination of an excitation generator and a time-variable filtering system consisting of the resonant cavities of an acoustic tube having a variable cross-section. The excitation may be a sequence of periodic or pseudorandom pressure variations, depending on whether the output is to correspond to a voiced or an unvoiced sound. The filter has coefficients which represent the effects of reflection between different cavities of the tube and are continuous functions of time; the coefficient values, however, may be considered to be constant during sufficiently short time intervals, e.g. on the order of 10 msec. Furthermore, the filter can be controlled to have a variable gain corresponding to a varying sound intensity. 
     Thus, an element of synthesized speech may be represented by a set of parameters coding the duration of the element, the kind of excitation (whether voiced or unvoiced), filter gain, weighting coefficients and, in the case of voiced sound, the recurrence period of the excitation pulses. These parameters are obtained by analyzing human speech in accordance with the selected model. Such an analysis is described by P. M. Bertinetto, C. Miotti, S. Sandri and E. Vivalda in a paper titled &#34;An Interactive Synthesis System for the Detection of Italian Prosodic Rules&#34;, CSELT Technical Reports, vol. V, No. 5, December 1977. Prior synthesizers operating according to this model, however, vary the coefficients at constant intervals, thereby producing a degree of unnaturalness in the synthesized speech. 
     OBJECTS OF THE INVENTION 
     The object of our present invetion is to provide an improved speech synthesizer of the type referred to. 
     SUMMARY OF THE INVENTION 
     A digital speech synthesizer according to our present invention comprises signal-generating means delivering excitation pulses of varying amplitudes and polarities to a lattice filter for producing digital speech samples in response thereto. A digital-to-analog converter at the output of the filter translates the speech samples into voice signals. A computer of other programmed message source stores sets of processing parameters transmittable, in a predetermined sequence, to the signal-generating means for commanding the emission of the excitation pulses, and to the filter for controlling the processing of these pulses thereby; the processing parameters represent coded information relating to frequency distribution, volume and duration of speech elements such as diphones. An input unit, which may be one of several identical modules, operatively connects the signal-generating means and the filter to the message source for producing consecutive speech elements of a voice signal coded by the parameter-set sequence. The input unit includes counting means for controlling the respective duration of each speech element according to counter settings transmitted by the message source together with the processing parameters, these setting establishing different counts of validity intervals for the respective parameter sets A time base correlates the operation of the filter, the input unit and the signal generator. 
     According to another feature of our present invention, the signal-generating means includes a first generator adapted to emit periodic excitation pulses, i.e. digitized amplitude samples of alternating waveforms to produce voiced elements, and a second generator adapted to emit aperiodic excitation signals, i.e. constant-amplitude pulses free from recognizable periodicity, to produce unvoiced elements of synthesized speech. The parameters from the message source include a discriminating signal for the selective enablement of one or the other generator, which may be a read-only memory, according to the nature of the sound to be generated. 
     Preferably, the synthesizer according to our present invention includes a plurality of input units of the aforedescribed type each associated with a respective output channel, the time base being connected to the input units for individually activating them one at a time. In such a case, the excitation-pulse generators and the filter are controlled by the time base to operate in a time-division mode for establishing time slots respectively allocated to the several input units. 
     According to another feature of our present invention, the counting means of each input unit include two distinct counters, namely a validity-interval counter and a sound-interval counter. The latter is preloaded with a setting or preliminary count to be progressively decremented for measuring the length of an operating period for either the periodic-signal or the aperiodic-signal generator, depending on the nature (voiced or unvoiced) of the sound. A control unit advantageously forms an interface between the message source and the input units for temporarily storing parameter-set requests therefrom and for distributing parameter sets from that source to respective input units selected according to programmed address information. Each input unit may further include a pair of buffer memories for temporarily and alternatively storing successive parameter sets from the messsage source, the validity-interval counter being connected to these buffer memories for enabling an interchange of reading and writing functions therebetween upon detecting the termination of a current validity interval and for receiving upon such interchange, from whichever of these memories is enabled for reading, a counter setting determining the duration of the next validity interval. 
     According to yet another feature of our present invention, a switch operating in response to the aforementioned discriminating signal from the buffer memory enabled for reading controls the preloading of the sound-interval counter with unvoiced-interval settings equal to the encoded contents of the validity-interval counter or with pitch-period settings (i.e. a count of the cycle length of the fundamental sound frequency) from the enabled memory, these settings representing coded frequency characteristics of speech elements. An additional memory temporarily stores weighting coefficients and sound-intensity data transmitted from the read-enabled buffer memory in response to a reading signal generated by the sound-interval counter upon detecting the termination of a current sound interval; the additional memory is connected to the time base and to the filter for transmitting the weighting coefficients thereto in response to clock signals from the time base. 
     Pursuant to further features of our present invention, the control unit includes a logic network for enabling the transfer of a parameter request from an input unit to the message source only upon receiving therefrom consent signals indicating completion of an ongoing transmission of a parameter-set sequence to such input unit. A register temporarily stores the arriving parameters while a series-to-parallel converter decodes address signals from the message source to enable the transmission of the parameters from the register to a selected input unit. A parallel-to-series converter encodes the addresses of request-emitting input units, these addresses being temporarily stored in a read/write memory prior to their emission to the message source in response to a consent signal therefrom. 
     The lattice filter used in our improved speech processor may comprise a digital multiplier, a digital adder and a data store together generating a digital speech sample as a sum of terms including an excitation sample weighted by a sound-intensity coefficient and at least one term formed as a product of a reflection coefficient and a preceding digital speech sample. For the theoretical principles underlying the operation of such a filter, reference may be made to an article titled &#34;Digital Lattice and Ladder Filter Synthesis&#34; by A. H. Gray and John D. Markel, IEEE Transactions on Audio and Electroacoustics, Vol. AU-21, No. 6, December 1973, pages 491-500. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The above and other features of our present invention will now be described in detail, reference being made to the accompanying drawing in which: 
     FIG. 1 is a block diagram of a multichannel digital speech synthesizer according to our present invention, including a lattice filter operatively connected to a processor via a control interface and n input modules; 
     FIG. 2 is a block diagram of the control unit or interface illustrated in FIG. 1; 
     FIG. 3 is a block diagram of an input module shown in FIG. 1; 
     FIG. 4 is a hypothetical diagram illustrating the principle of operation of the filter of FIG. 1; 
     FIG. 5 is a block diagram showing the structure of the filter of FIG. 1; 
     FIG. 6 is a graph of binary signals for controlling and synchronizing the operations of the synthesizer of FIG. 1; and 
     FIG. 7 is a graph of durations of parallel operating states of an input module shown in FIGS. 1 and 3. 
    
    
     SPECIFIC DESCRIPTION 
     FIG. 1 shows a multichannel digital speech synthesizer SIN connected to an external message source UE such as a computer or programmer for receiving therefrom sets of parameters coding information related to frequency distributions, intensity levels and durations of consecutive speech elements. The synthesizer comprises, according to our present invention, a lattice filter TV processing excitation pulses to produce digital speech samples transmitted over a lead 41 to a digital-to-analog converter MU for translation into voice signals and distribution over n outgoing signal paths in the form of transmission lines u a  . . . u n . Converter MU is an output unit advantageously consisting of n D/A stages and a series-to-parallel decoder (not shown) distributing thereto time-division-multiplexed signals arriving from filter TV. 
     Filter TV receives excitation pulses via an input lead 40 extending from a signal generator GE which includes a pair of read-only memories EP and EC functioning respectively as a periodic-signal emitter and aperiodic-signal emitter designed to supply filter TV with pulse trains processed thereby into digital speech samples convertible by unit MU into voiced and unvoiced elements of synthesized speech. Binary-coded signals arriving from an input module IN a , IN b , . . . IN n  via respective lead groups 8a, 8b, . . . 8n, merging in a common multiple 8, represent a pitch-period parameter T characterizing the fundamental frequency of a voiced speech element. In response to these signals, read-only memory EP emits a train of T pulses including a first pulse having a positive polarity and a magnitude √T-1 and (T-1) pulses having a negative polarity and a magnitude 1/√T-1. Thus, the train of T pulses generated by memory EP, e.g. at a cadence of 8 KHz, forms an excitation signal having a zero mean value and unitary power whereby variations in the d-c voltage level between successive sound elements are eliminated and the sound intensity or volume becomes precisely controllable according to a gain coefficient G (see FIG. 4) transmitted from computer UE to filter TV via input modules IN a , IN b , . . . IN n , as described more fully hereinafter with reference to FIGS. 4 and 5. 
     Read-only memory EC generates trains of pulses of unitary magnitude and pseudo-random polarity. Each train constitutes an excitation signal of unitary power and substantially zero mean value. The periodicity of the pulse sequence will be practically imperceptible if that sequence is of sufficiently great length, e.g. of the order of 2 10  pulses. 
     Memories EP and EC are selectively connectable to filter TV by an electronic switch S 1  under the control of a signal transmitted from an input module IN a  -IN n  over a wired-OR connection comprising leads 7a, 7b, . . . 7n and a common conductor 7. Modules IN a  -IN n  also transmit to filter TV, over respective leads 9a, 9b, . . . 9n and a common conductor 9, the coded values of multiplicative reflection coefficients K 1 , K 2  etc. (FIG. 4) and of the gain coefficient G which are used by filter TV in processing the excitation signals from generator GE. The number of reflection coefficients K 1 , K 2  etc. depends on the number of functional cells in filter TV, i.e. on the number of recursive digital algebraic operations performed by the filter for each speech sample emitted to converter MU, as described in detail hereinafter with reference to FIGS. 4 and 5. Associated with each excitation pulse transmitted over lead 40 to filter TV is a respective set of weighting coefficients G, K 1 , K 2  etc. These coefficients, together with a discriminating bit carried by conductor 7, the signals coding the pitch period T (on multiple 8) and bits determining the duration of an interval D of validity for coefficients G, K 1 , K 2  etc., constitute a set of processing parameters transmitted from computer UE to an input module IN a , IN b , . . . IN n  a multiple 1 and a control unit UC which forms an interface between these input modules and the computer. 
     Unit UC receives, via a multiple 2 extending from computer UE, timing pulses inducing the loading of parameter signals carried by multiple 1, the latter multiple also transmitting control signals which are decoded by unit UC and serve at least in part for commanding the emission, over leads 5a, 5b, . . . 5n, of activating pulses enabling the selective loading of input modules IN a , IN b , . . . IN n  with parametric signals received from unit UC via a line 4. These modules, as described hereinafter with respect to FIGS. 2 and 3, emit parameter-request signals to processor UE via respective output leads 6a, 6b, . . . 6n, control unit UC and a multiple 3. On a lead 30, extending to control unit UC, computer UE transmits a verification code confirming the reception of a parameter request. 
     The operations of synthesizer SIN are correlated by a time base TB emitting selection signals CK a , CK b , . . . CK n  to input modules IN a , IN b , . . . IN n , respectively, reading signals CK 1  and TR 1  to memories EP, EC, and clock pulses CK x  (x=1, 2 . . . 5) as well as enabling signals TR Y  (y=2, 3 . . . 6) to filter TV. 
     As shown in FIG. 2, control unit UC comprises a first register RE 1  loading, in response to timing pulses carried by a lead 20, parametric signals transmitted on a lead 10. A second register RE 2  temporarily stores control words arriving on a lead 11, this register being enabled by timing pulses carried on a lead 21. Leads 10, 11 and 20, 21 form part of multiples 1 and 2, respectively. Register RE 1  has an output connected to line 4, while register RE 2  has a pair of output leads 12, 13 extending to n logic circuits L la  -L ln  associated with respective input modules IN a  -IN n  and with respective output channels u a  -u n . Register RE 2  has a further output lead 14 extending to a decoder DE which in turn has output connections 5a-5n working into logic circuits L la  -L ln  and into input modules IN a  -IN n , as heretofore described. Circuits L la  -L ln  are connected via associated leads 15a-15n to respective AND gates P a  -P n  whose output leads 16a-16n are linked to a read/write memory ME 1  via an encoder COD. This memory has a read-command input from a counter CN fed by the timing pulses on lead 20 and an output tied to computer UE via a lead 31 forming part of multiple 3 (FIG. 1). A logic network LN 1  is connected to memory ME 1  for inforing computer UE, via a lead 32 of multiple 3, that memory ME 1  contains at least one message. 
     Upon the transmission over lead 10 of the first in a sequence of parameter sets chosen by computer UE for synthesizing a predetermined voice signal to be emitted over a selected output channel u a  -u n , pulses on lead 20 enable the loading of the parameters by register RE 1 . A control word simultaneously carried on lead 11 is loaded into register RE 2  in response to timing pulses on lead 21. This control word includes a bit commanding the initiation of a parameter-set sequence and inducing the energization of lead 12. A signal emitted over lead 14 causes decoder DE to energize a lead 5a-5n corresponding to the selected output channel, e.g. channel u a . Owing to the presence of high-level logic signals on leads 12 and 5a, circuit L la  emits a high-level voltage on lead 15a, thereby enabling gate P a  to emit a pulse to encoder COD in response to a pulse transmitted from input module IN a  over lead 6a. Module IN a  will energize lead 6a, as described in detail hereinafter with reference to FIG. 3, upon detecting the termination of a validity interval D for a set of parameters already received by module IN a  from computer UE. Upon receiving from gate P a  a pulse signifying a parameter request from module IN a , encoder COD writes in memory ME 1  an address code corresponding to channel u a . The reception and storage of the address code is detected by logic network LN 1  and communicated thereby to computer UE via lead 32. Upon the counting of a predetermined number of timing pulses indicating the completed transmission of an entire parameter set via register RE 1 , counter CN generates a consent signal enabling the reading of an address code from memory ME 1 . This memory is provided with n storage locations, i.e. one for every channel u a  -u n . 
     As shown in FIG. 3, a generic input module IN i  representative of all modules IN a  -IN n  includes a pair of read/write memories ME 2 , ME 3  serving as buffer stores for parameter sets arriving over line 4. Lead 6i, which carries a parameter request from a validity-interval counter CD, works into memories ME 2 , ME 3  for effecting an interchange of writing and reading functions therebetween, so that these memories alternate in the reception and readout of parameter sets. The energization of lead 6i also causes the emission to counter CD, via a lead 91 and from the memory ME 2  or ME 3  enabled for reading, of a counter setting determining the validity interval D of the parameter set stored by this memory. Memories ME 2 , ME 3  have a common output connection 90 extending to an additional memory ME 4  for transferring parameter sets thereto; this transfer to memory ME 4  from the buffer memory ME 2  or ME 3  enabled for reading is caused by a sound-interval counter CT via a lead 60. The emission of a parameter set from memory ME 4  to filter TV via lead 9i occurs in response to clock signal CK i . 
     Counter CT is connected at a loading input to an electronic switch S 2  for receiving a sound-interval count from counter CD via a lead 61 or from read-enabled memory ME 2  or ME 3  via multiple 8i. According to whether the energization level of lead 7i indicates that the sound nature of a forthcoming speech sample is to be unvoiced or voiced, switch S 2  presets counter CT with an unvoiced-interval count equal to the current contents of component CD or with a voiced-interval count determined by the pitch-period signals carried by multiple 8i. The contents of counters CD, CT are decremented by stepping pulses SP emitted by time base TB. 
     Upon the loading of a control word into register RE 2  (FIG. 2) and the transmission to decoder DE of an address code indicating the output channel associated with module IN i , lead 5i is energized to apply a writing command to buffer memories ME 2 , ME 3  (FIG. 3). Let us assume that this control word corresponds to a first parameter set in a sequence. Counters CD and CT are then set to measure a predetermined time interval t 0  -t 1 , indicated in FIG. 7, sufficient for the loading of the first parameter set into the memory ME 2  or ME 3 , whichever happens to be enabled for writing; the counters CD, CT are preloaded with a common setting T 0  =D 0  at instant t 0 . Upon counting out the predetermined starting interval t 0  -t 1 , counter CD emits on lead 6i a pulse passed by the associated gate (P a  -P n , FIG. 2) and converted by encoder COD into a parameter request transmitted to computer UE via lead 31, as heretofore described. The pulse on lead 6i also interchanges reading and writing functions between memories ME 2 , ME 3  and, if memory ME 2  is assumed to accept the first parameter set, reads onto lead 91 a code group or byte from this memory to preload the counter CD with a validity-interval setting D 1  assigned to this parameter set. 
     At the same instant t 1  when counter CD emits a pulse on lead 6i, counter CT temporarily energizes lead 60, thereby reading from memory ME 2  onto leads 90, 7i and 8i respective code groups which represent a set of filter coefficients G(1), K 1  (1), K 2  (1) etc. controlling the processing in filter TV of a first excitation-pulse train, a discriminating signal indicating that the sound nature of a first speech element is voiced, and signals giving a pitch period T 1  for the fundamental frequency of this first speech element. The signal carried by lead 7i induces switch S 2  to preload counter CT with a setting corresponding to pitch period T 1 , this counter immediately beginning to decrement the count T 1  to measure a time interval t 1  -t 1  &#39;. During this interval the memory ME 4  is recurrently addressed by clock signal CK i , at a rate inversely proportional to the number n of synthesizer channels u a  -u n , to feed coefficients G(1), K 1  (1), K 2  (1) etc. to filter TV for determining the processing of excitation pulses transmitted from read-only memory EP according to the pitch period T 1 . 
     If there are eight output channels (n=8) and if the synthesizer SIN has a cycle length of 125 μsec, filter TV will have available an interval of almost 16 μsec per cycle for processing, according to weighting coefficients supplied by memory ME 4 , an excitation pulse emitted by memory EP (FIG. 1) in response to the pitch-period code carried by leads 8a, 8. As heretofore described, memory EP is addressed by this pitch-period code and by an enabling signal TR 1  to emit an excitation signal consisting of T 1  pulses. Generally, the voiced-sound interval counted by component CT, as determined by its presetting with the corresponding pitch-period count T, is substantially greater than the interval required for the emission of a complete excitation code by memory EP, whereby 10 to 100 identical excitation codes are processed by filter TV prior to the reading of another parameter set from buffer memories ME 2 , ME 3 . 
     Upon reaching its preset count of T 1 , component CT transmits a pulse via lead 60 to memories ME 2  -ME 4 . Because component CD has not yet finished counting, memories ME 2  and ME 3  are still enabled for reading and writing, respectively. Thus, the pulse on lead 60 again delivers the setting T 1  to counter CT and coefficients G(1), K 1  (1), K 2  (1) etc. to memory ME 4  whereupon the operations implemented during interval t 1  -t 2  are repeated in a subsequent interval t 1  &#39;-t 1  &#34; of identical duration. 
     At an instant t 2  determined by validity-interval setting D 1 , counter CD energizes lead 6i to communicate a parameter-set request to computer UE and to interchange reading and writing operations between memories ME 2  and ME 3 . A signal carried by lead 91 from memory ME 3  in response to the energization of lead 6i now preloads counter CD with a setting D 2  determining the next interval of validity for the parameters stored in memory ME 3 . These parameters are read from memory ME 3  by counter CT at instant t 1  &#34; and include a discriminating signal, emitted on lead 7i, indicating the sound of the next synthesized speech element to be unvoiced. This signal reverses switch S 2  to load counter CT with the current contents of counter CD and connects lead 40 (FIG. 1) to read-only memory EC. It is to be noted that, in the illustrative example of input-unit operation shown in FIG. 7, interval t 1  &#34;-t 3  is represented with dashed lines to indicate the emission of unvoiced samples by filter TV; time t 2  -t 3  is similarly represented to indicate a validity interval for unvoiced-sound parameters. During interval t 2  -t 3 , memory EC emits at least one excitation signal consisting of pulses of unitary magnitude and quasi-random polarity to be processed by filter TV according to a gain coefficient G(2) and reflection coefficients K 1  (2), K 2  (2) etc. which are fed to memory ME 4  upon the energization of lead 60 at instant t 1  &#34; and are subsequently transmitted to filter TV under the control of clock pulses CK i . During interval t 2  -t 3 , determined by the count D 2 , memory ME 2  receives a new parameter set from computer UE via control unit UC. 
     Because counter CT is loaded at instant t 1  &#34; with the contents of counter CD, these two components energize their respective output leads 60, 6i substantially simultaneously. Consequently, at instant t 3  the counter CD is preloaded to measure a time t 3  -t 4  according to a validity-interval setting D 3  transmitted from buffer ME 2  and counter CT is given a setting T 3  determining an interval t 3  -t 3  &#39;, while memory ME 4  is fed signals from buffer ME 2  representing a third set of filter coefficients G(3), K 1  (3), K 2  (3) etc. Signals generated on lead 8i represent pitch characteristics of a speech element to be synthesized during interval t 3  -t 3  &#39;, as well as the setting supplied to counter CT, and induce read-only memory EP to emit excitation signals constituted by a positive pulse of magnitude √T 3  -1 and (T 3  -1) negative pulses of magnitude 1/√T 3  -1, as heretofore described with reference to FIG. 1. One excitation pulse is emitted during each synthesizer cycle, i.e. each 125 μsec, to be processed into a digital speech sample by filter TV in response to weighting coefficients G(3), K 1  (3), K 2  (3) etc. read from memory ME 4  by clock pulses CK i . 
     At instant t 3  &#39;, owing to validity interval t 3  -t 4  being longer than voiced-sound interval t 3  -t 3  &#39;, counter CT again is preloaded with count T 3  and memory ME 4  receives weighting coefficients G(3), K 1  (3), K 2  (3) etc., whereby digital speech samples generated at the output of filter TV during interval t 3  -t 3  &#39; are represented during a succeeding interval t 3  &#39;-t 3  &#34;. At instant t 4 , counter CD enables buffers ME 2 , ME 3  for writing and for reading, respectively, and receives a setting D 4  which determines the duration of a validity interval t 4  -t 5 . During the latter interval a new parameter set is written into buffer ME 2  ; as indicated in FIG. 7, however, this set is replaced at instant t 5  by yet another set which controls the sound characteristics of a speech element produced by synthesizer SIN on the associated output channel during a subsequent interval t 3  &#34;-t 6 . Owing to the brief duration of validity interval t 4  -t 5 , the suppression of the corresponding sound is largely unnoticeable. 
     The processing of excitation pulses by filter TV is diagrammatically illustrated in FIG. 4. To produce a digital speech sample E 10  on the lead 41 extending to converter MU (FIG. 1), filter TV forms a product E 0 , at a multiplication stage MT, of an incoming excitation pulse and a gain factor G arriving via lead 9 from one of the input units IN a , IN b , . . . IN n . Product E 0  is then successively diminished at differential stages SM 1  of ten functional cells TV 1  to TV 10  of filter TV. Stage SM 1  of each of these cells yields a resulting value E 1  to E 10  formed by subtracting from the result of the operation of the preceding cell MT, TV 1  etc. a product π 1a  to π 10a  in turn formed, at a respective multiplication stage ML 1 , from a reflection coefficient K 1  to K 10  and a sum F 1  to F 10 , these sums F 1  to F 10  being generated by feedback during the production of a preceding digital speech sample and temporarily stored at delay stages Z. Each cell TV 2  to TV 10  has an adder stage SM 2  at which the sums F 1  to F 9  are derived as algebraic combinations of the sums at the outputs of delays Z and products π 2b  to π 10b  formed at respective multiplication stages ML 2  of cells TV 2  to TV 10  from filter coefficients K 2  to K 10  and from the results E 2  to E 10  of subtractor stages SM 1 . Thus, filter TV implements the following equations in processing an excitation pulse E 0  (τ) at a time τ to yield a digital speech sample E 10  (τ): ##EQU1## where 
     
         F.sub.j (τ)=E.sub.j (τ)·K.sub.2 (τ)+F.sub.j+l (τ-Δτ)                                      (2) 
    
     and Δτ represents the duration of a processing cycle of synthesizer SIN, e.g. 125 μsec. The values of the gain G and the multiplicative reflection coefficients K 1 , K 2 , . . . K 10 , which are stored in computer UE and transmitted to filter TV via an input module IN a , IN b , . . . IN n  as discussed above, are determined according to an acoustic-speech-production model as described in various publications listed in the aforementioned article by Bertinetto et al, including Speech Synthesis by J. L. Flanagan and L. R. Rabiner (Dowden, Hutchinson and Ross, Stroudsburg, PA., 1973) and On Some Factors Influencing the Quality of Synthesized Speech by C. Scagliola and E. Vivalda (First Colloque F.A.S.E., Paris, 1975). 
     An actual filter TV for executing the operation diagrammed in FIG. 4 is shown in FIG. 5. Lead 40 (see FIG. 1) extends to a register RE 3  via an analog-to-digital converter ADC which changes an incoming excitation pulse into a form suitable for the circuitry of filter TV; if the pulses emitted by memory EP (FIG. 1) are already coded in binary fashion, converter ADC may be omitted. Another register RE 4  has an input connected to lead 9 for receiving values of gain G and coefficients K 1 , K 2  etc. from input modules IN a  to IN n . Both registers RE 3 , RE 4  feed a multiplier ML 3  working into an output register RE 6 . This register loads an adder SM 3  via a logic network LN 2  for selectively changing the algebraic sign, in response to the logic level of a changeover signal A/S from time base BT, of products emitted by multiplier ML 3 . Register RE 6  has an output lead 42 extending to another register RE 5  and to a read/write memory ME 5  wherein reading and writing operations are controlled by a time-base signal R/W, register RE 5  and memory ME 5  working via a common output lead 41&#39; into adder SM 3  and register RE 3 . Adder SM 3  feeds yet another register RE 7  which shares output lead 42 with register RE 6 . 
     Registers RE 3 , RE 4  and RE 6  receive clock pulses CK 1 , CK 2  and TR 4  for timing the operations of multiplier ML 3  to execute the products E 0 , π 1a  to π 10a , π 1b  to π 10b  of stages MT, ML 1 , ML 2  (see FIG. 4), while registers RE 6 , RE 7  and logic network LN 2  respond to signals CK 2 , CK 4 , TR 4 , TR 5  and A/S to control the adder SM 3  for producing the differences E 1  to E 10  and the sums F 1  to F 9  resulting from the operations performed at filter stages SM 1  and SM 2 , respectively. Clock pulses CK 1 , CK 2 , CK 3  and CK 4  command the loading of registers RE 3  /RE 4 , RE 6 , RE 5  and RE 7 , respectively, while signals TR 2 , TR 3 , TR 4  and TR 5  are respectively applied to tristate circuits in register RE 5 , memory ME 5 , register RE 6  and register RE 7  for enabling the emission of the respective contents thereof onto leads 41&#39; and 42. A further memory ME 6  has an input tied to lead 41, extending from register RE 5  to converter MU (FIG. 1), and an output connected via lead 42 to memory ME 5  for feeding back a result E 10  to serve as a sum F 10  in a subsequent processing of an excitation pulse. 
     Generally, memory ME 5  stores the sums F 1  to F 10 , thereby carrying out the function of delays Z (FIG. 4). Register RE 5  temporarily memorizes the differences E 0  to E 10  during the processing of an excitation pulse. It is to be noted that filter TV performs the additive, subtractive and multiplicative operations, indicated in FIG. 4, for each speech sample emitted over any output channel u a  -u n . These operations are executed in a time-division mode under the control of time base TB and will now be described in detail with reference to FIGS. 4, 5 and 6. In FIG. 6, a high level of read/write signal R/W denotes a reading command while a high level of changeover signal A/S causes a sign inversion. 
     Let us assume that, at an instant v 1 , a channel-selection signal CK i  (cf. FIG. 3) coincides with a clock pulse CK 1  and a high level of enabling signal TR 1 , resulting in the emission of an excitation pulse from generator memory EP (FIG. 1) to input register RE 3  and the loading of a gain factor G into register RE 4 . During an accommodation interval of at least 100 nsec, which follows instant v 1 , enabling signals TR 2 , TR 3  have a low logic level, thereby preventing the reading of algebraic values from register R 5  or memory ME 5  to input register RE 3 . At an instant v 2 , these signals TR 2 , TR 3  taken on a high logic level, therby allowing memory ME 5  to feed back to that input register the coded sum F 1  (calculated in the preceding subcycle assigned to the selected channel) and commanding output register RE 6  to transmit the product E 0  from multiplier ML 3  onto lead 42. Upon the generation of clock pulses CK 1 , CK 2  at an instant v 3 , registers RE 3 , RE 4  load sum F 1  and reflection coefficient K 1  from memory ME 5  and input module IN i , respectively; register RE 6  memorizes the product E 0  present at the output of multiplier ML 3 , this product being transferred to register RE 5  in response to a clock pulse CK 3  at an instant v 4 . At the same instant the logic level of signal TR 3  goes low, thereby disconnecting memory ME 5  from output lead 41&#39;. 
     An increase of the voltage of signal TR 2  at an instant v 5  enables the transfer of product E 0  from register RE 5  to adder SM 3  via lead 41&#39;. The next clock pulse CK 2 , following after a 100-nsec delay, causes the loading of product π 1a  into register RE 6 . Because this register is already enabled by signal TR 4  and because logic network LN 2  is receiving a high-level signal A/S, product π 1a  is transmitted to adder SM 3  for subtraction from product E 0 , the resulting difference E 1  being temporarily stored in register RE 7  in response to a clock pulse CK 4  at an instant v 7 . Simultaneously with the rising edge of this pulse, the logic levels of signals TR 2 , TR 4  fall and the logic levels of signals TR 3 , TR 5  rise, whereby registers RE 5 , RE 6  are prevented from emitting signals onto leads 41&#39;, 42 whereas memory ME 5  and register RE 7  are enabled to feed back the coded algebraic values F 2 , E 1  to registers RE 3 , RE 5 , respectively. At a subsequent instant v 8 , clock pulses CK 1  and CK 3  induce the transfer of difference E 1  to register RE 5  and the loading of sum F 2  and of coefficient K 2  into registers RE 3  and RE 4  for transmission to multiplier ML 3  to form the product π 2a . Upon the reading of sum F 2  to register RE 3  and the emission of difference E 1  from register RE 7 , signals TR 3 , TR 5  assume a low level (instant v 9 ) to disconnect units ME 5  and RE 5  from output leads 41&#39; and 42. Signals TR 2  and TR 4  then resume, at an instant v 10 , their high levels for enabling the transmission of difference E 1  to adder SM 3  and of product π 2a  from multiplier ML 3  via register RE 6  and logic network LN 2  to adder SM 3 . Because signal A/S has a high level between instants v 11  and v 12 , the algebraic sign of product π 2a  is inverted by logic network LN 2  and the result loaded at instant v 12  into register RE 7  is a difference E 2 . The feeding of product π 2a  to output register RE 6  is commanded by a clock pulse CK 2  at instant v 11 , this instant terminating a first processing phase symbolized by the first filter cell TV 1  of FIG. 4. 
     Enabling signals TR 4 , TR 5  go low and high, respectively, at instant v 12 , thereby inhibiting further transmission from register RE 6  but allowing register RE 7  to generate on lead 42 a pulse code representing the value of difference E 2 . An ensuing clock pulse CK 3  (at an instant v 13 ) loads the value of this difference into register RE 5 . Owing to the high logic level of enabling signal TR 2 , register RE 5  transfers difference E 2  to unit RE 3  upon the appearance of a clock pulse CK 1  at an instant v 14 . This clock pulse also causes the loading of reflection coefficient K 2  into register RE 4 . During an ensuing interval v 14  -v 17 , multiplier ML 3  forms product π 2b . The common output lead 41&#39; is disconnected from register RE 5  and connected to memory ME 5  in response to the changing levels of signals TR 2  and TR 3  at an instant v 15  whereby sum F 3   is fed back to register RE 3 . 
     At an instant v 16 , signals A/S and TR 4  assume low and high logic levels, respectively, thereby enabling the transfer of product π 2b  without sign change from multiplier ML 3  to adder SM 3  upon the generation of clock pulse CK 2  at instant v 17 . At the same instant a clock pulse CK 1  loads register RE 3  with sum F 3  (calculated during the processing of the preceding excitation pulse assigned to the output channel here considered) and register RE 4  with coefficient K 3 , the product π 3a  formed from sum F 3  and coefficient K 3  being stored in register RE 6  at an instant v 21 . Clock pulse CK 4  at an instant v 18  induces the temporary memorization by register RE 7  of the newly formed sum F 1 . The passing, at instant v 18 , of signal TR 5  to a high logic level enables the transmission of the new sum F 1  from register RE 7  to memory ME 5  upon the appearance, at an instant v 19 , of a writing command in the form of a low level of signal R/W. The enabling of register RE 7  by signal TR 5  coincides with the return of changeover signal A/S to a high level, switching adder SM 3  to its subtractive mode, and the return of enabling signal TR 4  to a low level. 
     The subsequent processing phases of filter TV, corresponding to intermediate cells TV 3  to TV 9  omitted in FIG. 4 but indicated in FIG. 6, are the same as the operations symbolized by cell TV 2  occurring between instants v 11  and v 21  as described above. At an instant v 22 , marking the beginning of a final calculation phase symbolized by the tenth cell TV 10 , a clock pulse CK 2  loads product π 10a  into register RE 6 . Owing to the high levels of changeover and enabling signals A/S and TR 4 , the sign of the product is inverted in logic network LN 2  upon transmission thereto by register RE 6 . Adder SM 3  subtracts the product π 10a  from the difference E 9  (temporarily stored in register RE 5 ) to produce the difference E 10 . At an instant v 23 , signals CK 4 , TR 4  and TR 5  assume high, low and high logic levels, respectively, whereby register RE 7  receives difference E 10  and is enabled to transfer it to register RE 5  upon the appearance of a clock pulse CK 3  at an instant v 24 . At a subsequent time v 25  a clock pulse CK 5  enables the transfer of difference E 10  to converter MU (see FIG. 1) and to buffer memory ME 6  while a clock pulse CK 1  loads registers RE 3  and RE 4  with difference E 10  and coefficient K 10 , respectively, to be fed to multiplier ML 3  for the implementation of product π 10b . The altering of the voltage levels of signals TR 2 , TR 3  at a time v 26  blocks any emission from register RE 5  over lead 41&#39; and enables the transfer of sum F 10  (from the previous processing subcycle) to adder SM 3 . 
     With enabling signal A/S going low and enabling signal TR 4  going high at an instant v 27 , the appearance of a clock pulse CK 2  at an instant v 28  causes product π 10b  to be transmitted without change in sign to adder SM 3  for combination with sum F 10  to form a new sum F 9  which is then stored in register RE 7  in response to a pulse CK 4  at an instant v 29 . At the latter instant the levels of signals TR 2  and TR 5  go high and the levels of signals TR 3  and TR 4  go low, whereby the new sum F 9  is loaded into register RE 5 . Because signal TR 2  is high, a writing pulse at a time v 30  enables the transfer of sum F 9  to memory ME 5 . A subsequent writing pulse (instant v 32 ), occurring after the appearance of a clock pulse CK 6  enabling the connection of memory ME 6  to output lead 42, causes the storage in memory ME 5  of difference E 10 , which will serve as sum F 10  in the next processing subcycle assigned to the output channel here considered. The current subcycle terminates upon the return of signal CK i  to a low logic level at a time v 33 . The next subcycle begins at this time v 33  and is assigned to another output channel identified by the immediately following selection pulse CK a  -CK n .