Patent Publication Number: US-8970256-B2

Title: Sense amplifier

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a Non-Provisional Patent Application claiming priority to Provisional Patent Application Ser. No. 61/781,654 filed Mar. 14, 2013 entitled “A Sense Amplifier” in the name of Cheng Hung Lee, et al. and is hereby incorporated by reference. 
    
    
     BACKGROUND 
     Increasing memory capacity requirements within microelectronic devices of next-generation semiconductor technology nodes combined with lower power consumption and higher speed demands has driven an increase in the number of memory cells per bitline within memory arrays, resulting in a decrease in the supply voltage allocated to each memory cell within the array, which in turn drives lower noise margins and degrades sense amplifier reliability. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A-1C  illustrate pull-down mismatch between a pair of cross-coupled inverters. 
         FIGS. 2A-2D  illustrate some embodiments of a sense amplifier configured to compensate for pull-down device mismatch when reading data from a memory device. 
         FIG. 3  illustrates some embodiments of a method of sense amplification. 
         FIG. 4  illustrates some embodiments of a differential sense amplifier comprising cross-coupled inverters and current control elements configured to regulate current through the cross-coupled inverters. 
         FIGS. 5A-5B  illustrate some embodiments of a method of sense amplification of the differential sense amplifier of  FIG. 4  and an associated timing diagram. 
     
    
    
     DETAILED DESCRIPTION 
     The description herein is made with reference to the drawings, wherein like reference numerals are generally utilized to refer to like elements throughout, and wherein the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to facilitate understanding. It may be evident, however, to one of ordinary skill in the art, that one or more aspects described herein may be practiced with a lesser degree of these specific details. In other instances, known structures and devices are shown in block diagram form to facilitate understanding. 
     Some semiconductor memory devices include read-write memories such as static random-access memory (SRAM) in which data is stored as the state of a bistable memory cell, or dynamic random-access memory (DRAM) which stores data as a charge on a capacitor within a memory cell. Because the stored state of the SRAM or DRAM degrades in the absence of an external power supply, these storage types are considered volatile. Some non-volatile memory types, which can retain data when power is disabled, include read-only memory (ROM) and non-volatile read-write memory (NVRWM) such as flash memory. Semiconductor memory devices typically include an array of such memory cells. To discern between data states stored in the individual memory cells, sense amplifiers are also included in these memory devices. 
       FIG. 1A  illustrates a differential sense amplifier (SA)  100 A, comprising a first inverter  102 A and a second inverter  104 A arranged in a cross-coupled configuration. The differential SA  100 A is configured to receive a first complimentary data signal DL from a first switching element  106 A, and a second a complimentary data signal DLB from a second switching element  108 A. When a switch enable signal PG is turned on at t=0, as illustrated in  FIG. 1B , the first complimentary data signal DL charges a first internal node  110 A of the differential SA  100 A to a first potential DUN, and the second complimentary data signal DLB charges a second internal node  112 A of the differential SA  100 A to a second potential DLB_IN. 
     A read margin of the differential SA  100 A is defined as the delta voltage (ΔV) between DL_IN and DLB_IN when PG is turn on. The first inverter  102 A and the second inverter  104 A each comprise a pull-down element (e.g., an n-type transistor on series with a p-type transistor). In read mode, DL_IN and DLB_IN will charge to V DD  and V DD -ΔV, respectively. When these potentials discharge, the first inverter  102 A and the second inverter  104 A initially pull DL_IN and DLB_IN down. The delta voltage (ΔV) in conjunction with the cross-coupled configuration of the first inverter  102 A and the second inverter  104 A will result in DLB_IN being pulled to ground (i.e., logical “0”) with DL_IN being pulled to its original potential (i.e., logical “1”), as illustrated in  FIG. 1B . 
     For the first and the second inverters  102 A,  104 A with identical pull-down characteristics the pull-down of DL_IN and DLB_IN will be the same. However, device characteristic mismatches driven by process variation due to semiconductor scaling, and resulting in a relative increase in device variation, increases a relative mismatch between the pull-down characteristics of the first and the second inverters  102 A,  104 A. If the mismatch between the first and the second inverters  102 A,  104 A is large enough, or the read margin of the differential SA  100 A is less than a minimum threshold, the pull-down element of the second inverter  104 A will pull DLB_IN below DL_IN, and result in a read fail of the memory device, as illustrated in  FIG. 1C . 
     Accordingly, the present disclosure relates to a device and method to improve sense amplifier mismatch against process variation while simultaneously improving the read margin requirement for a differential sense amplifier. A differential sense amplifier comprising cross-coupled inverters with complimentary storage nodes is coupled to a current control element that changes a current through a first cross-coupled inverter based upon an output of a second cross-coupled inverter, and vice-versa. Other embodiments and associated methods are also disclosed. 
       FIG. 2A  illustrates some embodiments of a semiconductor memory device  200 A. The memory device  200 A includes a memory array  202 , which is made up of a plurality of memory cells  204  arranged in M rows and N columns. For clarity, the individual memory cells  204  in  FIG. 2A  are labeled C row-column . Wordlines WL 1 -WLN are coupled to the memory cells  204  along respective rows, and complimentary bitlines BL 1 -BLN, BLB 1 -BLBN are coupled to the memory cells  204  along respective columns. For example, wordline WL 1  is coupled to cells C 1-1  through C 1-N  along Row  1 , and complementary bitlines BL 1 /BLB 1  are coupled to cells C 1-1  through C M-1  along Col.  1 . To discern between two or more data states stored in the individual memory cells  204 , data paths  206 , which include corresponding sense amplifiers (SA)  208 , are coupled to columns of memory cells  204 . In some embodiments, the data paths  206  output data read from the memory device  200 A to a latch, or other storage device. 
     Although  FIG. 2A  shows an embodiment where each column has a separate data path  206  and a corresponding SA  208  to read data states from that column, in other embodiments a data path and its corresponding sense amplifier can be shared (e.g., multiplexed) between multiple columns of memory cells  204  rather than being devoted to a single column of memory cells  204 . 
       FIG. 2B  illustrates a more detailed example of a column  200 B (e.g., col.  1  of  FIG. 2A ), which includes memory cells  204  and a corresponding sense amplifier (SA)  208 . Each memory cell  204  is coupled to complementary bitlines BL 1 , BLB 1 . First and second switching elements,  210 A and  210 B respectively, which are under direction of signal PG, selectively couple the complimentary bitlines BL 1 , BLB 1  to SA  208 . The SA  208  includes first and second cross-coupled inverters,  212 A and  212 B respectively, with first and second complimentary storage nodes,  214 A and  214 B respectively. The SA  208  also includes a first current control element  216 A that changes a current through the first cross-coupled inverter  212 A based upon an output of a second cross-coupled inverter  212 B. Similarly, a second current control element  216 B changes a current through the second cross-coupled inverter  212 B based upon an output of a first cross-coupled inverter  212 A. The first and second current control elements  216 A,  216 B are configured to compensate for DL_IN and DLB_IN mismatch in read mode of the memory array  202 , to improve speed performance of the memory array  202  and reduce the read margin requirement for a successful read. 
     When the memory array  202  is in read mode, a first data input  218 A connected to the first complimentary storage node  214 A receives a first complimentary data signal DL from the first switching element  210 A, and a second data input  218 B connected to the second complimentary storage node  214 B receives a second complimentary data signal DLB. DL charges the first complimentary storage node  214 A to a first potential DL_IN. Likewise, DLB charges the second complimentary storage node  214 B to a second potential DLB_IN. For the embodiments of  FIG. 2B , the first potential DL_IN is greater than the second potential DLB_IN by a delta voltage (ΔV) value. 
     To read a data value from a memory cell  204  (e.g., Cell 1-1 ), the complimentary bitlines BL 1 , BLB 1  are first decoupled from the SA  208  by opening the first and second switching elements  210 A,  210 B (i.e., setting the signal PG=0), thereby decoupling complimentary bitlines BL 1 , BLB 1  from the first and second complimentary storage nodes  214 A,  214 B. While decoupled, a pre-determined amount of charge is leaked from a supply voltage V DD  onto the first and second complimentary storage nodes  214 A,  214 B. This pre-charged condition often represents a condition where the cross-coupled inverters  212 A,  212 B are in an intermediate, or “balanced” state, meaning that neither inverter  212 A,  212 B is strongly pulling towards a logical “0” or logical “1” state. After the first and second complimentary storage nodes  214 A,  214 B have been pre-charged to the intermediate state, the first and second switching elements,  210 A and  210 B, are closed, causing a voltage differential established on complimentary bitlines BL 1 , BLB 1  to leak onto the first and second data inputs  218 A,  218 B and to the first and second complimentary storage nodes  214 A,  214 B. This re-coupling “tweaks” the pre-charged condition and changes the voltage differential on the first and second complimentary storage nodes  214 A,  214 B, thereby causing the cross-coupled inverters  212 A,  212 B to pull one way or another depending on the data state read from Cell 1-1 , ultimately resulting in the cross-coupled inverters  212 A,  212 B mutually reinforcing the sensed data state. 
       FIG. 2C  illustrates a more detailed example of the sense amplifier (SA)  208  comprising a differential sense amplifier structure  224 . The differential sense amplifier structure  224  comprises the first and second cross-coupled inverters  212 A,  212 B with the first and second complimentary storage nodes  214 A,  214 B, and is configured such that a first current control element  216 A changes a current through the first cross-coupled inverter  212 A based upon an output of a second cross-coupled inverter  212 B, and a second current control element  216 B changes a current through the second cross-coupled inverter  212 B based upon an output of a first cross-coupled inverter  212 A. 
     The first current control element  216 A includes a first compensation switch  220 A coupled to a first complimentary compensation node  226 A, and configured to connect the first complimentary compensation node  226 A to the second complimentary data signal DLB. A first pull-down element  220 C is also connected to the first complimentary compensation node  226 A and configured to pull current from the first complimentary compensation node  226 A to ground based upon a second pull-down control signal received from the second complimentary storage node  214 B. The first current control element  216 A is also configured to couple the first complimentary compensation node  226 A to the first complimentary storage  214 A node through the first cross-coupled inverter  212 A. 
     Likewise, the second current control element  216 B includes a second compensation switch  220 A coupled to a second complimentary compensation node  226 B, and configured to connect the second complimentary compensation node  226 B to the first complimentary data signal DL. A second pull-down element  220 D is also connected to the second complimentary compensation node  226 B and configured to pull current from the second complimentary compensation node  226 B to ground based upon a first pull-down control signal received from the first complimentary storage node  214 A. The second current control element  216 B is also configured to couple the second complimentary compensation node  226 B to the second complimentary storage  214 B node through the second cross-coupled inverter  212 B. 
     The first compensation switch  220 A and the second compensation switch  220 B are controlled by a same control signal CS. The first pull-down element  220 C is connected to ground through an enable switch  222  such that a sense amp enable (SAE) signal instructs the enable switch  222  to send current from the first pull-down element  220 C to ground. Likewise, the second pull-down element  220 D is connected to ground through the enable switch  222  such that current is diverted from the second pull-down element  220 C to ground in response to the SAE signal. 
       FIG. 2D  illustrates another example of the sense amplifier (SA)  200 D. In read mode, PG directs first and second switching elements  210 A,  210 B comprising n-type field-effect transistors (NFETs) with respective drains connected to first and second complementary bitlines BL, BLB, and respective sources connected to first and second data inputs  218 A,  218 B, to send first and second complimentary data signals DL, DLB to a differential sense amplifier structure  224 . The differential sense amplifier structure  224  includes first and second respective cross-coupled inverters  212 A,  212 B connected to first and second respective complimentary storage nodes  214 A,  214 B which charge to first and second respective potentials DL_IN, DLB_IN. 
     The first cross-coupled inverter  212 A comprises a first pull-up p-type FET (PFET)  228 A with a drain connected to the first data input  218 A to receive the first complimentary data signal DL, and a source connected to the drain of a first pull-down NFET  230 A through the first complimentary storage node  214 A. Gates of the first pull-up PFET  228 A and the first pull-down NFET  230 A are connected to the second complimentary storage node  214 B. In a similar manner, the second cross-coupled inverter  212 B comprises a second pull-up PFET  228 B with a drain connected to the second data input  218 B to receive the second complimentary data signal DLB, and a source connected to the drain of a second pull-down NFET  230 B through the first complimentary storage node  214 B. Gates of the second pull-up PFET  228 A and the first pull-down NFET  230 A are connected to the second complimentary storage node  214 B. 
     By adding first and second pull-down elements  220 C,  220 D and first and second compensate switches  220 A,  220 B, first and second complimentary compensation nodes  226 A,  226 B will charge to the first and second respective potentials (i.e., D 1 →DL_IN, D 2 →DLB_IN) when CS is turned on. This coupling between the first and second respective complimentary storage nodes  214 A,  214 B and the first and second respective complimentary compensation nodes  226 A,  226 B can compensate for a mismatch of the pull-down characteristics of the first and second pull-down NFETs  230 A,  230 B. The first and second respective pull-down elements  220 C,  220 D act as a part of the first and second respective pull-down NFETs  230 A,  230 B in back-to-back inverters and separate first and second complimentary compensation nodes  226 A,  226 B from a shared node (NS). This compensation can be shown to reduce the SA mismatch by approximately 9% over some prior art approaches. 
       FIG. 3  illustrates some embodiments of a method  300  of sense amplification that may be utilized in accordance with the sense amplifiers of  FIGS. 2A-2D . While the method disclosed in  FIG. 3 , and subsequently the method of  FIG. 5A , are described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. 
     At  302  first and second complimentary storage nodes of first and second cross-coupled inverters are pre-charged to an intermediate state between logical “1” and logical “0.” 
     At  304  first and second complementary data signals DL, DLB charge the first and second complimentary storage nodes to first and second respective potentials DL_IN, DLB_IN, where the first potential DL_IN is greater than the second potential DLB_IN by a delta voltage (ΔV) value. Simultaneously, first and second complimentary compensation nodes which are coupled to the first and second complimentary storage nodes, respectively, are also charged to the first and second respective potentials DL_IN, DLB_IN. 
     At  306  the second complimentary storage node is pulled towards ground while changing current through the first cross-coupled inverter based upon a second output of the second cross-coupled inverter with a second current control element to amplify a difference between the first and second potentials. Because DLB_IN is less than DL by ΔV, the second complimentary storage node and the second complimentary compensation node are both pulled to ground (i.e., logical “0”) before the first complimentary storage node and the first complimentary compensation node. In some embodiments, changing current through the second cross-coupled inverter based upon the first output comprises coupling the first complimentary storage node to a first complimentary compensation node, charging the first complimentary compensation node to the first potential, and pulling the first complimentary compensation node towards ground. In some embodiments, pulling the first complimentary compensation node towards ground comprises coupling the first complimentary compensation node to a first compensation switch configured to charge the first complimentary storage node to the first potential DL_IN. And pulling the first complimentary compensation node towards ground further comprises connecting the first complimentary compensation node to a first pull-down element configured to pull current from the first complimentary compensation node to ground based upon a second pull-down control signal received from the second complimentary storage node, where the first complimentary compensation node is coupled to the first complimentary storage node through the first cross-coupled inverter. 
     At  308  the first complimentary storage node and the first complimentary compensation node retain the first potential (i.e., are pulled to logical “1”) while changing current through the second cross-coupled inverter based upon a first output of the first cross-coupled inverter, resulting in a mutually reinforcing the sensed data state. In some embodiments, changing current through the first cross-coupled inverter based upon the second output comprises coupling the second complimentary storage node to a second complimentary compensation node, charging the second complimentary compensation node to the second potential, and pulling the second complimentary compensation node towards ground. In some embodiments, pulling the second complimentary compensation node towards ground comprises coupling the second complimentary compensation node to a second compensation switch and configured to charge the second complimentary storage node to the second potential DLB_IN. And pulling the second complimentary compensation node towards ground further comprises connecting the second complimentary compensation node to a second compensation switch configured to pull current from the second complimentary compensation node to ground based upon a first pull-down control signal received from the first complimentary storage node, where the second complimentary compensation node is coupled to the second complimentary storage node through the second cross-coupled inverter. 
       FIG. 4  illustrates some embodiments of a differential sense amplifier  400  comprising first and second cross-coupled inverters  212 A,  212 B and first and second current control elements  216 A,  216 B configured to regulate current through the cross-coupled inverters first and second cross-coupled inverters  212 A,  212 B. The differential sense amplifier  400  includes first and second complimentary storage nodes  214 A,  214 B configured to receive first and second complimentary data signals DL, DLB from first and second data inputs  218 A,  218 B. The first and second current control elements  216 A,  216 B include first and second compensation switches  220 A,  220 B controlled by a same control signal (CS). The first and second compensation switches  220 A,  220 B comprise PFETs, and can be pass gates or transmission gates. The first and second compensation switches  220 A,  220 B are coupled to first and second complimentary compensation nodes  226 A,  226 B, and are configured to connect the first and second complimentary compensation nodes  226 A,  226 B to the second and first data inputs  218 B,  218 A, respectively. 
     The first and second current control elements  216 A,  216 B also include first and second pull-down elements  220 C,  220 D comprising NFETs connected to the first and second complimentary compensation nodes  226 A,  226 B, respectively. The first and second pull-down elements  220 C,  220 D are configured to pull current from the first and second complimentary compensation nodes  226 A,  226 B to ground based upon second and first pull-down control signals comprising the second and first potentials DLB_IN, DL_IN received from the second and first complimentary storage nodes,  214 B,  214 A respectively. The first complimentary compensation node  226 A is coupled to the first complimentary storage node  214 A through the first cross-coupled inverter  212 A, and the second complimentary compensation node  226 B is coupled to the second complimentary storage node  214 B through the second cross-coupled inverter  212 B. 
     A first source of the first pull-down element  220 C and a second source of the second pull-down element  220 D are connected to ground through an enable switch  222 . A first drain of the first pull-down element  220 C is connected to the first complimentary compensation node  226 A, and a second drain of the second pull-down element  220 D is connected to the second complimentary compensation node  226 B. A first gate of the first pull-down element  220 C is connected to the second complimentary storage node  214 B, and a second gate of the second pull-down element  220 D is connected to the first complimentary storage node  214 A. 
     For first and second complementary data signals DL, DLB which charge the first and second complimentary storage nodes  214 A,  214 B to first and second respective potentials DL_IN, DLB_IN, where the first potential DL_IN is greater than the second potential DLB_IN by a delta voltage (ΔV) value, if the pull-down characteristic of the first cross-coupled inverter  212 A (i.e., the NFET) is greater than the pull-down characteristic of the second cross-coupled inverter  212 B, DL_IN will be pulled up more than DLB_IN, because D 1  is larger than D 2  by ΔV (i.e., D 1 →DL_IN, D 2 →DLB_IN). Thus, the first and second current control elements  216 A,  216 B can keep DL_IN consistently above DLB_IN when SAE is turned on. 
       FIG. 5A  illustrates some embodiments of a method  500 A of sense amplification of the differential sense amplifier of  FIG. 4 .  FIG. 5B  illustrates an associated timing diagram to the method  500 A. 
     At  502  (t=0) PREB turns off, and the first and second complimentary storage nodes  214 A,  214 B stop charging an intermediate state (i.e., V DD ). 
     At  504  (t=t 1 ) PGB and CS are turn on, DLB_IN will discharge from the second complimentary storage node  214 B and the second complimentary compensation node  226 B. The voltage difference between the first and second complimentary storage nodes  214 A,  214 B (i.e., ΔV) is the same as the voltage difference between the first and second complimentary compensation nodes  226 A,  226 B. 
     At  506  (t=t 2 ) SAE turns on, both DL_IN and DLB_IN are pulled down with a voltage difference (ΔV) to compensate for the pull-down characteristic mismatch between the first and second cross-coupled inverters  212 A,  212 B. 
     At  508  (t=t 3 ) CS turns off and the compensation is completed. The first and second compensation switches  220 A disconnect the first and second pull-down elements  220 C,  220 D from the first and second complementary data signals DL, DLB. The first and second complimentary compensation nodes  226 A,  226 B are pulled to ground, and the voltage difference (ΔV) between the first and second complimentary storage nodes  214 A,  214 B pulls the second complimentary storage node  214 B to logic “0,” thus flipping the first complimentary storage node  214 A to logic “1” to achieve a mutually reinforcing the sensed data state. The sensed data is then sent through output buffers to first and second complementary global bitlines GBL, GBLB. 
     At  510  (t=t 4 ) PGB turns off for next read operation cycle. 
     It will also be appreciated that equivalent alterations and/or modifications may occur to one of ordinary skill in the art based upon a reading and/or understanding of the specification and annexed drawings. The disclosure herein includes all such modifications and alterations and is generally not intended to be limited thereby. In addition, while a particular feature or aspect may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features and/or aspects of other implementations as may be desired. Furthermore, to the extent that the terms “includes”, “having”, “has”, “with”, and/or variants thereof are used herein; such terms are intended to be inclusive in meaning—like “comprising.” Also, “exemplary” is merely meant to mean an example, rather than the best. It is also to be appreciated that features, layers and/or elements depicted herein are illustrated with particular dimensions and/or orientations relative to one another for purposes of simplicity and ease of understanding, and that the actual dimensions and/or orientations may differ substantially from that illustrated herein. 
     Therefore, the present disclosure relates to a device and method to improve sense amplifier mismatch against process variation while simultaneously improving the read margin requirement for a differential sense amplifier. A differential sense amplifier comprising cross-coupled inverters with complimentary storage nodes is coupled to a current control element that changes a current through a first cross-coupled inverter based upon an output of a second cross-coupled inverter, and vice-versa. 
     In some embodiments, the present disclosure relates to a sense amplifier comprising first and second cross-coupled inverters with first and second complimentary storage nodes, and a first current control element that changes a current through the first cross-coupled inverter based upon an output of a second cross-coupled inverter. 
     In some embodiments, the present disclosure relates to a sense amplifier comprising first and second cross-coupled inverters with first and second complimentary storage nodes configured to receive first and second complimentary data signals from first and second data inputs, respectively, a first current control element that changes a current through the first cross-coupled inverter based upon an output of a second cross-coupled inverter, and a second current control element that changes a current through the second cross-coupled inverter based upon an output of a first cross-coupled inverter. 
     In some embodiments, the present disclosure relates to a method of amplification comprising pre-charging a first and second complimentary storage nodes of first and second cross-coupled inverters to an intermediate state, charging the first and second complimentary storage nodes to first and second potentials, respectively, wherein the first potential is greater than the second potential, and pulling the second complimentary storage node towards ground while changing current through the first cross-coupled inverter based upon a second output of the second cross-coupled inverter with a second current control element to amplify a difference between the first and second potentials. The method of amplification further comprises retaining the first potential on the first complimentary storage node while changing current through the second cross-coupled inverter based upon a first output of the first cross-coupled inverter.