Patent Publication Number: US-2023154507-A1

Title: Bit line logic circuits and methods

Description:
PRIORITY CLAIM 
     The present application is a continuation of U.S. application Ser. No. 17/109,964, filed Dec. 2, 2020, which is a continuation of U.S. application Ser. No. 15/938,393, filed Mar. 28, 2018, now U.S. Pat. No. 10,867,646, issued Aug. 21, 2020, each of which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     Memory array data access includes read and write operations having speeds that depend on memory cell type, memory circuit design, parasitic resistance and capacitance levels, operating voltages, and temperature and manufacturing process variations. Overall speed of a system that includes a memory array is sometimes based on memory access speeds. 
     In many applications, memory circuits are operated at low voltages to limit power consumption and heat generation. As operating voltages decrease, circuit speeds and therefore memory access speeds typically decrease. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    is a diagram of a memory circuit, in accordance with some embodiments. 
         FIG.  2 A  is a diagram of a memory circuit, in accordance with some embodiments. 
         FIG.  2 B  is a plot of memory circuit operating parameters, in accordance with some embodiments. 
         FIG.  3 A  is a diagram of a memory circuit, in accordance with some embodiments. 
         FIG.  3 B  is a plot of memory circuit operating parameters, in accordance with some embodiments. 
         FIG.  4    is a diagram of a memory circuit, in accordance with some embodiments. 
         FIG.  5    is a diagram of a memory circuit, in accordance with some embodiments. 
         FIG.  6 A  is a diagram of a memory circuit, in accordance with some embodiments. 
         FIG.  6 B  is a diagram of a memory circuit, in accordance with some embodiments. 
         FIG.  7    is a flowchart of a method of biasing a bit line, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated  90  degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     In various embodiments, a memory circuit includes a switching circuit coupled between a voltage node and a bit line for a plurality of memory cells. The switching circuit includes a logic element that receives a bit line voltage as an input and is capable of causing the bit line to be coupled with the voltage node. During a write, pre-charge, or other operation, a write circuit biases the bit line toward a bias voltage level. As the bit line voltage approaches the bias voltage level, the switching circuit is configured to respond to the bit line voltage by coupling the bit line to the voltage node, thereby increasing the current available for biasing the bit line above a current level provided by the write circuit alone. Compared to approaches that do not increase the available current, the switching circuit causes the bit line to approach the bias voltage level more rapidly, thereby increasing overall operating speed of the memory circuit and enabling a lowered operating voltage for a given operating frequency. 
       FIG.  1    is a diagram of a memory circuit  100 , in accordance with some embodiments. Memory circuit  100  includes a write circuit  110  and a plurality of memory cells  120 . Each of write circuit  110  and plurality of memory cells  120  is electrically coupled with a bit line (BL) and with a bit line (hereinafter referred to as a bit line bar (BLB) and having a complementary signal from BL). A switching circuit  130 A includes input terminals A 1  and A 2 , and is electrically coupled with bit line BL, a voltage node VN 1 , and a voltage node VN 2 . A switching circuit  130 B includes input terminals B 1  and B 2 , and is electrically coupled with bit line BLB and voltage nodes VN 1  and VN 2 . 
     Two or more circuit elements are considered to be electrically coupled based on a direct electrical connection or an electrical connection that includes one or more additional circuit elements and is thereby capable of being controlled, e.g., made resistive or open by a transistor or other switching device. 
     Memory circuit  100  is a subset of a memory macro, e.g., a memory macro including memory circuit  600 A discussed below with respect to  FIG.  6 A  or a memory macro including memory circuit  600 B discussed below with respect to  FIG.  6 B , that includes one or more additional components, e.g., at least one plurality of memory cells (not shown) in addition to plurality of memory cells  120 . 
     Voltage node VN 1  is a reference node configured to carry a reference voltage VSS having a reference voltage level of memory circuit  100 . In some embodiments, memory circuit  100  is part of a larger system, and the reference voltage level of memory circuit  100  corresponds to a reference voltage level of the system. In some embodiments, memory circuit  100  is part of a larger system, and the reference voltage level of memory circuit  100  corresponds to a memory-specific reference voltage level. In some embodiments, reference voltage VSS is a ground voltage having a ground voltage level. 
     Voltage node VN 2  is a power supply node configured to carry a power supply voltage VDD having a power supply voltage level corresponding to an operational voltage level of memory circuit  100 . In some embodiments, memory circuit  100  is part of a larger system, e.g., a system on a chip, and the operational voltage level of memory circuit  100  corresponds to an operational voltage level of the system. In some embodiments, memory circuit  100  is part of a larger system, and the operational voltage level of memory circuit  100  corresponds to a memory-specific operational voltage level. 
     In some embodiments, the power supply voltage level corresponds to a logically high state and the reference voltage level corresponds to a logically low state. 
     Write circuit  110  is configured to bias voltage levels on bit lines BL and BLB responsive to one or more control signals (not shown). Write circuit  110  is configured to receive power supply voltage VDD and reference voltage VSS and bias one or both of bit lines BL or BLB toward a bias voltage level corresponding to one of the power supply voltage level or the reference voltage level. 
     In some embodiments, in a write operation on memory circuit  100 , write circuit  110  is configured to bias one of bit lines BL or BLB toward the power supply voltage level and the other of bit lines BL or BLB toward the reference voltage level. In some embodiments, in a read operation on memory circuit  100 , write circuit  110  is configured to pre-charge one or both of bit lines BL or BLB by biasing the one or both of bit lines BL or BLB toward either the power supply voltage level or the reference voltage level. 
     In operation, biasing a bit line, e.g., one of bit lines BL or BLB, toward a voltage level, e.g., one of the power supply or reference voltage levels, includes either causing a bit line voltage level to reach the voltage level or causing the bit line voltage level to approach, but not reach the voltage level. 
     In operation, biasing bit line BL using write circuit  110  includes driving a voltage level on bit line BL toward the bias voltage level with a current IBL. When the voltage level on bit line BL is lower than the bias voltage level, e.g., the power supply voltage level, current IBL has a positive value. When the voltage level on bit line BL is higher than the bias voltage level, e.g., the reference voltage level, current IBL has a negative value. 
     In operation, biasing bit line BLB using write circuit  110  includes driving a voltage level on bit line BLB toward the bias voltage level with a current IBLB. When the voltage level on bit line BLB is lower than the bias voltage level, e.g., the power supply voltage level, current IBLB has a positive value. When the voltage level on bit line BLB is higher than the bias voltage level, e.g., the reference voltage level, current IBLB has a negative value. 
     Bit lines BL and BLB are conductive lines capable of transferring the bias voltage levels to and/or from each memory cell of plurality of memory cells  120 , bit lines BL and BLB thereby corresponding to plurality of memory cells  120 . Memory circuit  100  is configured so that, in a write operation, bit lines BL and BLB have voltage levels corresponding to complementary logical states. 
     Plurality of memory cells  120  includes electrical, electromechanical, electromagnetic, or other devices (not individually labeled) configured to store bit data represented by logical states. The logical states of the memory cells in plurality of memory cells  120  are capable of being programmed in a write operation and detected in a read operation. 
     In some embodiments, a logical state corresponds to a voltage level of an electrical charge stored in a given memory cell. In some embodiments, a logical state corresponds to a physical property, e.g., a resistance or magnetic orientation, of a component of a given memory cell. 
     In some embodiments, plurality of memory cells  120  includes static random-access memory (SRAM) cells. In various embodiments, SRAM cells include five-transistor (5T). SRAM cells, six-transistor (6T) SRAM cells, eight-transistor (8T) SRAM cells, nine-transistor ( 9 T) SRAM cells, or SRAM cells having other numbers of transistors. In some embodiments, plurality of memory cells  120  includes dynamic random-access memory (DRAM) cells or other memory cell types capable of storing bit data. 
     Plurality of memory cells  120  includes a column of memory cells or a portion of a column of memory cells. In some embodiments, plurality of memory cells  120  includes a number of memory cells ranging from 128 to 1024. In some embodiments, plurality of memory cells  120  includes  256  memory cells. In some embodiments, plurality of memory cells  120  includes  512  memory cells. In some embodiments, plurality of memory cells  120  includes fewer than 128 memory cells. In some embodiments, plurality of memory cells  120  includes greater than 1024 memory cells. 
     Because a memory macro including memory circuit  100  includes one or more circuits capable of interacting with each memory cell of plurality of memory cells  120 , a number of memory cells fewer than  128  reduces the efficiency of the memory macro in some cases. 
     Because bit lines BL and BLB correspond to plurality of memory cells  120 , lengths and resistance values, of bit lines BL and BLB increase as a number of memory cells of plurality of memory cells  120  increases. A number of memory cells greater than  1024  therefore increases the effects of bit line resistance on write and read operations on plurality of memory cells  120 . 
     Switching circuit  130 A includes a logic circuit  131 A having an input terminal Al and a logic circuit  132 A having an input terminal A 2 . Each of logic circuits  131 A and  132 A has an additional input terminal electrically coupled with bit line BL. An output terminal of logic circuit  131 A is electrically coupled with a control terminal of a switching device  133 A, and an output terminal of logic circuit  132 A is electrically coupled with a control terminal of a switching device  134 A. 
     Each of logic circuits  131 A and  132 A includes one or more logic gates and is configured to generate a switching signal at the output terminal having a voltage level representing a logical state responsive to voltage levels representing logical states received at the input terminals. In various embodiments, logic circuits  131 A and  132 A include one or more of an inverter, OR gate, NOR gate, AND gate, NAND gate, or other logic gate suitable for applying a logic scheme. 
     Switching device  133 A includes terminals electrically coupled with bit line BL and voltage node VN 1 , and is configured to electrically connect bit line BL with voltage node VN 1  responsive to a voltage level of the switching signal at the control terminal of switching device  133 A. Switching device  134 A includes terminals electrically coupled with bit line BL and voltage node VN 2 , and is configured to electrically connect bit line BL with voltage node VN 2  responsive to a voltage level of the switching signal at the control terminal of switching device  134 A. 
     Each of switching devices  133 A and  134 A includes one or more electrical or electro-mechanical constructions capable of making and breaking electrical connections between two or more terminals responsive to voltage levels representing logical states received at the control terminal. In various embodiments, switching devices  133 A and  134 A include one or more of a transistor, transmission gate, or other device suitable for controlling electrical connections. 
     In various embodiments, a transistor includes one or a combination of a field-effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a fin field-effect transistor (FinFET), an n-type transistor, a p-type transistor, a vertical gate transistor, a bipolar or other transistor type. 
     Logic circuit  131 A is configured to cause switching device  133 A to electrically couple bit line BL with voltage node VN 1  responsive to both the voltage level on bit line BL and the reference voltage level corresponding to a logically low state. In operation, the voltage level on bit line BL corresponding to the logically low state is determined by the difference between the voltage level on bit line BL and the reference voltage level being less than or equal to a threshold value. In some embodiments, the threshold value is determined by a threshold voltage of a transistor in logic circuit  131 A. 
     In operation, the voltage level on bit line BL being equal to or within the threshold value of the reference voltage level corresponds to a first logical state of the switching signal at the output terminal of logic circuit  131 A, and the voltage level on bit line BL being above the reference voltage level by more than the threshold value corresponds to a second logical state of the switching signal at the output terminal of logic circuit  131 A. 
     Switching device  133 A is configured to, in operation, electrically couple bit line BL with voltage node VN 1  in response to the switching signal at the output terminal of logic circuit  131 A having the first logical state and to electrically decouple bit line BL from voltage node VN 1  in response to the switching signal at the output terminal of logic circuit  131 A having the second logical state. 
     Logic circuit  132 A is configured to cause switching device  134 A to electrically couple bit line BL with voltage node VN 2  responsive to both the voltage level on bit line BL and the power supply voltage level corresponding to a logically high state. In operation, the voltage level on bit line BL corresponding to the logically high state is determined by the difference between the voltage level on bit line BL and the power supply voltage level being less than or equal to a threshold value. In some embodiments, the threshold value is determined by a threshold voltage of a transistor in logic circuit  132 A. 
     In operation, the voltage level on bit line BL being equal to or within the threshold value of the power supply voltage level corresponds to a first logical state of the switching signal at the output terminal of logic circuit  132 A, and the voltage level on bit line BL being below the power supply voltage level by more than the threshold value corresponds to a second logical state of the switching signal at the output terminal of logic circuit  132 A. 
     Switching device  134 A is configured to, in operation, electrically couple bit line BL with voltage node VN 2  in response to the switching signal at the output terminal of logic circuit  132 A having the first logical state and to electrically decouple bit line BL from voltage node VN 2  in response to the switching signal at the output terminal of logic circuit  132 A having the second logical state. 
     In some embodiments, in operation, bit line BL has an initial voltage level corresponding to a first logical state, and write circuit  110  drives the voltage level on bit line BL toward a bias voltage level corresponding to a second logical state different from the first logical state. Switching circuit  130 A is configured to respond to the initial voltage level on bit line BL by maintaining bit line BL electrically decoupled from voltage node VN 1  or VN 2  carrying the bias voltage level, and to respond to the voltage level on bit line BL approaching the bias voltage level by electrically coupling bit line BL to the voltage node VN 1  or VN 2  carrying the bias voltage level. 
     In a discharging operation, logic circuit  131 A electrically couples bit line BL with voltage node VN 1  responsive to the voltage level on bit line BL approaching the reference voltage level, and a current IA 1  flows from bit line BL to voltage node VN 1  through switching device  133 A until such time as the voltage level on bit line BL is equal to the reference voltage level. In the discharging operation, current IA 1  provided by switching circuit  130 A is added to the (negative) current IBL provided by write circuit  110  as discussed above, thereby increasing the total current available to drive bit line BL toward the reference voltage level compared to approaches that do not add a current to a write circuit current. 
     In a charging operation, logic circuit  132 A electrically couples bit line BL with voltage node VN 2  responsive to the voltage level on bit line BL approaching the power supply voltage level, and a current IA 2  flows from voltage node VN 2  to bit line BL until such time as the voltage level on bit line BL is equal to the power supply voltage level. In the charging operation, current IA 2  provided by switching circuit  130 A is added to the (positive) current IBL provided by write circuit  110  as discussed above, thereby increasing the total current available to drive bit line BL toward the power supply voltage level compared to approaches that do not add a current to a write circuit current. 
     By increasing the discharging and charging currents, in operation, memory circuit  100  including switching circuit  130 A increases speeds at which bit line BL is biased toward bias voltage levels compared to approaches that do not add a current to a write circuit current. 
     By being configured to electrically couple bit line BL with one of voltage nodes VN 1  or VN 2  responsive to the voltage level on bit line BL, switching circuit  130 A is effectively self-triggered in operation, thereby avoiding the need for timing schemes and circuits used by other approaches to increase bit line currents above write circuit currents. Compared to approaches that include timing schemes and circuits, memory circuit  100  including switching circuit  130 A is less complex, occupies less space, and uses less power in some cases. 
     Switching circuit  130 A is configured to receive an enable signal ENB on input terminal Al and an enable signal EN on input terminal A 2 . Logic circuit  131 A is thereby configured to couple bit line BL with voltage node VN 1  responsive to the voltage level on bit line BL only when the voltage level of enable signal ENB corresponds to a first logical state. Logic circuit  132 A is thereby configured to couple bit line BL with voltage node VN 2  responsive to the voltage level on bit line BL only when the voltage level of enable signal EN corresponds to a second logical state. 
     In some embodiments, one of the first logical state or the second logical state is a logically low state and the other of the first logical state or the second logical state is a logically high state. In some embodiments, enable signals EN and ENB are complementary signals such that when the voltage level of one of enable signals EN or ENB corresponds to one of a logically low or high state, the voltage level of the other of enable signals EN or ENB corresponds to the other of the logically low or high state. 
     In some embodiments in which enable signals EN and ENB are complementary signals, switching circuit  130 A is configured to couple bit line BL with either one of voltage nodes VN 1  or VN 2  responsive to the voltage levels on bit lines BL when the voltage levels of enable signals ENB and EN correspond to respective first and second logical states and to disable coupling bit line BL with either one of voltage nodes VN 1  or VN 2  responsive to the voltage level on bit line BL when the voltage levels of enable signals ENB and EN correspond to respective second and first logical states. 
     In some embodiments, switching circuit  130 A does not include input terminal Al, logic circuit  131 A, and switching device  133 A, and is thereby configured to electrically couple bit line BL with voltage node VN 2  without being configured to electrically couple bit line BL with voltage node VN 1 . In some embodiments, switching circuit  130 A does not include input terminal A 2 , logic circuit  132 A, and switching device  134 A, and is thereby configured to electrically couple bit line BL with voltage node VN 1  without being configured to electrically couple bit line BL with voltage node VN 2 . 
     In some embodiments, switching circuit  130 A includes one or more input terminals (not shown) in addition to input terminals Al and/or A 2 , and switching circuit  130 A is configured to electrically couple bit line BL with one or both of voltage nodes VN 1  or VN 2  further responsive to one or more signals received on the one or more additional input terminals. 
     Switching circuit  130 B includes a logic circuit  131 B having an input terminal B 1  and a logic circuit  132 B having an input terminal B 2 . Each of logic circuits  131 B and  132 B has an additional input terminal electrically coupled with bit line BLB. An output terminal of logic circuit  131 B is electrically coupled with a control terminal of a switching device  133 B, and an output terminal of logic circuit  132 B is electrically coupled with a control terminal of a switching device  134 B. 
     Switching circuit  130 B is configured to receive enable signal ENB on input terminal B 1  and enable signal EN on input terminal B 2 . Switching circuit  130 B is configured to electrically couple bit line BLB with voltage nodes VN 1  and VN 2  responsive to voltage levels of enable signals ENB and EN and the voltage level on bit line BLB in a manner analogous to that discussed above for switching circuit  130 A. Switching circuit  130 B is thereby capable of realizing the benefits discussed above with respect to switching circuit  130 A. 
     In the embodiment depicted in  FIG.  1   , switching circuits  130 A and  130 B are separate circuits. In some embodiments, memory circuit  100  includes a single switching circuit, e.g., switching circuit  430  discussed below with respect to  FIG.  4   , configured to electrically couple each of bit lines BL and BLB to one or both of voltage nodes VN 1  or VN 2  responsive to voltage levels on bit lines BL and BLB. 
       FIG.  2 A  is a diagram of a memory circuit  200 , in accordance with some embodiments. Memory circuit  200  is usable as a portion of memory circuit  100 , discussed above with respect to  FIG.  1   . Memory circuit  200  includes bit lines BL and BLB, input terminals A 1  and B 1 , and voltage node VN 1 , each discussed above with respect to  FIG.  1   . Memory circuit  200  also includes NOR gate  231 A usable as logic circuit  131 A, NMOS transistor  233 A usable as switching device  133 A, NOR gate  231 B usable as logic circuit  131 B, and NMOS transistor  233 B usable as switching device  133 B, each discussed above with respect to  FIG.  1   . Gates of NMOS transistors  233 A and  233 B correspond to respective control terminals of switching devices  133 A and  133 B. 
     In operation, in response to a logically high state of enable signal ENB at input terminals A 1  and B 1 , NOR gates  231 A and  231 B output switching signals having logically low states for any voltage level on bit lines BL and BLB. In response to having logically low gate voltage levels, NMOS transistors  233 A and  233 B are switched off, thereby electrically decoupling bit lines BL and BLB from voltage node VN 1 . 
     In operation, in response to a logically low state of enable signal ENB at input terminals A 1  and B 1 , NOR gates  231 A and  231 B output switching signals having logical states responsive to respective voltage levels on bit lines BL and BLB. In response to a logically low bit line BL or BLB voltage level, the corresponding NOR gate  231 A or  231 B outputs a switching signal having a logically high voltage level, thereby causing the corresponding NMOS transistor  233 A or  233 B to switch on and electrically couple bit line BL or BLB to voltage node VN 1 . In response to a logically high bit line BL or BLB voltage level, the corresponding NOR gate  231 A or  231 B outputs a switching signal having a logically low voltage level, thereby causing the corresponding NMOS transistor  233 A or  233 B to switch off and electrically decouple the bit line BL or BLB from voltage node VN 1 . 
       FIG.  2 B  is a plot of memory circuit  200  operating parameters, in accordance with some embodiments.  FIG.  2 B  depicts enable signal ENB and two bit line voltages VB 21  and VB 22  as a function of time. Bit line voltage VB 21  represents a voltage level on either of bit lines BL or BLB driven only by a write circuit, e.g., write circuit  110  discussed above with respect to  FIG.  1   . Bit line voltage VB 22  represents a voltage level on either of bit lines BL or BLB driven by write circuit  110  in combination with NOR gate  231 A and NMOS transistor  233 A or NOR gate  231 B and NMOS transistor  233 B. 
     From times t 21  to t 22 , enable signal ENB transitions from a logically high state to a logically low state. Between times t 22  and t 23 , write circuit  110  drives voltages VB 21  and VB 22  toward reference voltage level VSS. 
     In the embodiment depicted in  FIG.  2 B , enable signal ENB transitions from the logically high state to the logically low state before write circuit  110  starts to drive voltages VB 21  and VB 22  toward reference voltage level VSS, thereby operating as a gating signal. In some embodiments, enable signal ENB transitions from the logically high state to the logically low state concurrently with write circuit  110  starting to drive voltages VB 21  and VB 22  toward reference voltage level VSS. 
     At time t 23 , in response to voltage VB 22  being above reference voltage VSS by within a threshold value corresponding to a threshold voltage of a transistor of NOR gate  231 A or  231 B, NOR gate  231 A or  231 B outputs a switching signal that causes corresponding NMOS transistor  233 A or  233 B to switch on, thereby electrically coupling the corresponding bit line BL or BLB to voltage node VN 1  and increasing the discharging current. 
     As a result of the increased discharging current, voltage VB 22  reaches a minimum value at time t 24 , before voltage VB 21  reaches a minimum value at time t 25 . In the embodiment depicted in  FIG.  2 B , voltage VB 22  also reaches a lower minimum value than the minimum value of voltage VB 21  based on the increased discharging current reducing a voltage drop caused by a resistance of bit line BL or BLB. 
     Memory circuit  200 , configured as discussed above, is thereby capable of realizing the benefits discussed above with respect to memory circuit  100  and  FIG.  1   . Memory circuit  200  is used for the purpose of illustration. Other circuits being otherwise configured to perform the operations discussed above with respect to memory circuits  100  and  200  are within the scope of the disclosure. 
       FIG.  3 A  is a diagram of a memory circuit  300 , in accordance with some embodiments. Memory circuit  300  is usable as a portion of memory circuit  100 , discussed above with respect to  FIG.  1   . Memory circuit  300  includes bit lines BL and BLB, input terminals A 2  and B 2 , and voltage node VN 2 , each discussed above with respect to  FIG.  1   . Memory circuit  300  also includes NAND gate  332 A usable as logic circuit  132 A, PMOS transistor  334 A usable as switching device  134 A, NAND gate  332 B usable as logic circuit  132 B, and PMOS transistor  334 B usable as switching device  134 B, each discussed above with respect to  FIG.  1   . Gates of PMOS transistors  334 A and  334 B correspond to respective control terminals of switching devices  134 A and  134 B. 
     In operation, in response to a logically low state of enable signal EN at input terminals A 2  and B 2 , NAND gates  332 A and  332 B output switching signals having logically high states for any voltage level on bit lines BL and BLB. In response to having logically high gate voltage levels, PMOS transistors  334 A and  334 B are switched off, thereby electrically decoupling bit lines BL and BLB from voltage node VN 2 . 
     In operation, in response to a logically high state of enable signal EN at input terminals A 2  and B 2 , NAND gates  332 A and  332 B output switching signals having logical states responsive to respective voltage levels on bit lines BL and BLB. In response to a logically high bit line BL or BLB voltage level, the corresponding NAND gate  332 A or  332 B outputs a switching signal having a logically low voltage level, thereby causing the corresponding PMOS transistor  334 A or  334 B to switch on and electrically couple bit line BL or BLB to voltage node VN 2 . In response to a logically low bit line BL or BLB voltage level, the corresponding NAND gate  332 A or  332 B outputs a switching signal having a logically high voltage level, thereby causing the corresponding PMOS transistor  334 A or  334 B to switch off and electrically decouple the bit line BL or BLB from voltage node VN 2 . 
       FIG.  3 B  is a plot of memory circuit  300  operating parameters, in accordance with some embodiments.  FIG.  3 B  depicts enable signal EN and two bit line voltages VB 31  and VB 32  as a function of time. Bit line voltage VB 31  represents a voltage level on either of bit lines BL or BLB driven only by a write circuit, e.g., write circuit  110  discussed above with respect to  FIG.  1   . Bit line voltage VB 32  represents a voltage level on either of bit lines BL or BLB driven by write circuit  110  in combination with NAND gate  332 A and PMOS transistor  334 A or NAND gate  332 B and PMOS transistor  334 B. 
     From times t 31  to t 32 , enable signal EN transitions from a logically low state to a logically high state. Between times t 32  and t 33 , write circuit  110  drives voltages VB 31  and VB 32  toward power supply voltage level VDD. 
     In the embodiment depicted in  FIG.  3 B , enable signal EN transitions from the logically low state to the logically high state before write circuit  110  starts to drive voltages VB 31  and VB 32  toward power supply voltage level VDD, thereby operating as a gating signal. In some embodiments, enable signal EN transitions from the logically low state to the logically high state concurrently with write circuit  110  starting to drive voltages VB 31  and VB 32  toward power supply voltage level VDD. 
     At time t 33 , in response to voltage VB 32  being below power supply voltage VDD by within a threshold value corresponding to a threshold voltage of a transistor of NAND gate  332 A or  332 B, NAND gate  332 A or  332 B outputs a switching signal that causes corresponding PMOS transistor  334 A or  334 B to switch on, thereby electrically coupling the corresponding bit line BL or BLB to voltage node VN 2  and increasing the charging current. 
     As a result of the increased charging current, voltage VB 32  reaches a maximum value at time t 34 , before voltage VB 31  reaches a maximum value at time t 35 . 
     Memory circuit  300 , configured as discussed above, is thereby capable of realizing the benefits discussed above with respect to memory circuit  100  and  FIG.  1   . Memory circuit  300  is used for the purpose of illustration. Other circuits being otherwise configured to perform the operations discussed above with respect to memory circuits  100  and  300  are within the scope of the disclosure. 
       FIG.  4    is a diagram of a memory circuit  430 , in accordance with some embodiments. Memory circuit  430  is usable as a combination of switching circuits  130 A and  130 B and includes input terminals A 1  and A 2 , discussed above with respect to  FIG.  1   . In addition to memory circuit  430 ,  FIG.  4    depicts bit lines BL and BLB and voltage nodes VN 1  and VN 2 , each discussed above with respect to  FIG.  1   . 
     In addition to input terminals A 1  and A 2 , memory circuit  430  includes NMOS transistors N 1  and N 3  coupled in series between bit line BL and voltage node VN 1 , NMOS transistors N 2  and N 4  coupled in series between bit line BLB and voltage node VN 1 , PMOS transistors P 1  and P 4  coupled in series between bit line BL and voltage node VN 2 , PMOS transistors P 3  and P 5  coupled in series between bit line BLB and voltage node VN 2 . Memory circuit  430  also includes a PMOS transistor P 2 , and inverters INV 1  and INV 2 . 
     An input terminal of inverter INV 1  is electrically coupled with bit line BL, and an output terminal of inverter INV 1  is electrically coupled with gate terminals of NMOS transistor N 1  and PMOS transistor P 4 . An input terminal of inverter INV 2  is electrically coupled with bit line BLB, and an output terminal of inverter INV 2  is electrically coupled with gate terminals of NMOS transistor N 2  and PMOS transistor P 5 . 
     Each of NMOS transistors N 3  and N 4  includes a gate terminal electrically coupled with input terminal A 1 , which is configured to receive an enable signal WAS-EN. Each of PMOS transistors P 1 , P 2 , and P 3  includes a gate terminal electrically coupled with input terminal A 2 , which is configured to receive an enable signal BLPRE-ENB. In some embodiments, enable signals WAS-EN and BLPRE-ENB are complementary signals. 
     Each of NMOS transistors N 1 , N 2 , N 3 , and N 4  includes a source/drain terminal electrically coupled with a node ND 1 , each of PMOS transistors P 1 , P 2 , and P 4  includes a source/drain terminal electrically coupled with a node ND 2 , and each of PMOS transistors P 2 , P 3 , and P 5  includes a source/drain terminal electrically coupled with a node ND 3 . 
     In operation, in response to a logically low state of enable signal WAS-EN at input terminal Al, NMOS transistors N 3  and N 4  are switched off, thereby electrically decoupling node ND 1  from voltage node VN 1 . With node ND 1  electrically decoupled from voltage node VN 1 , bit line BL is not capable of being electrically coupled with voltage node VN 1  when NMOS transistor N 1  is switched on so as to electrically couple bit line BL with node ND 1 , and bit line BLB is not capable of being electrically coupled with voltage node VN 1  when NMOS transistor N 2  is switched on so as to electrically couple bit line BLB with node ND 1 . 
     In operation, in response to a logically high state of enable signal WAS-EN at input terminal A 1 , NMOS transistors N 3  and N 4  are switched on, thereby electrically coupling node ND 1  with voltage node VN 1 . In response to a logically low bit line BL voltage level, inverter INV 1  outputs a logically high voltage level to the gate of NMOS transistor N 1 , thereby causing NMOS transistor N 1  to switch on and electrically couple bit line BL with node ND 1  and voltage node VN 1 . In response to a logically low bit line BLB voltage level, inverter INV 2  outputs a logically high voltage level to the gate of NMOS transistor N 2 , thereby causing NMOS transistor N 2  to switch on and electrically couple bit line BLB with node ND 1  and voltage node VN 1 . 
     In operation, in response to a logically high state of enable signal BLPRE-ENB at input terminal A 2 , PMOS transistors P 1 , P 2 , and P 3  are switched off, thereby electrically decoupling nodes ND 2  and ND 3  from voltage node VN 2 . With nodes ND 2  and ND 3  electrically decoupled from voltage node VN 2 , bit line BL is not capable of being electrically coupled with voltage node VN 2  when PMOS transistor P 4  is switched on so as to electrically couple bit line BL with node ND 2 , and bit line BLB is not capable of being electrically coupled with voltage node VN 2  when PMOS transistor P 5  is switched on so as to electrically couple bit line BLB with node ND 3 . 
     In operation, in response to a logically low state of enable signal BLPRE-ENB at input terminal A 2 , PMOS transistors P 1 , P 2 , and P 3  are switched on, thereby electrically coupling nodes ND 2  and ND 3  with voltage node VN 2 . In response to a logically high bit line BL voltage level, inverter INV 1  outputs a logically low voltage level to the gate of PMOS transistor P 4 , thereby causing PMOS transistor P 4  to switch on and electrically couple bit line BL with node ND 2  and voltage node VN 2 . In response to a logically high bit line BLB voltage level, inverter INV 2  outputs a logically low voltage level to the gate of PMOS transistor P 5 , thereby causing PMOS transistor P 5  to switch on and electrically couple bit line BLB with node ND 3  and voltage node VN 2 . 
     Memory circuit  430  is thereby configured to electrically couple bit line BL with voltage node VN 1  responsive to enable signal WAS-EN and the voltage level on bit line BL, electrically couple bit line BLB with voltage node VN 1  responsive to enable signal WAS-EN and the voltage level on bit line BLB, electrically couple bit line BL with voltage node VN 2  responsive to enable signal BLPRE-ENB and the voltage level on bit line BL, and electrically couple bit line BLB with voltage node VN 2  responsive to enable signal BLPRE-ENB and the voltage level on bit line BLB. 
     Memory circuit  430 , by the configuration discussed above, is capable of realizing the benefits discussed above with respect to memory circuit  100  and  FIG.  1   . 
       FIG.  5    is a diagram of a memory circuit  530 , in accordance with some embodiments. Memory circuit  530  is usable as a combination of switching circuits  130 A and  130 B and includes input terminal Al, discussed above with respect to  FIG.  1   . In addition to memory circuit  530 ,  FIG.  5    depicts bit lines BL and BLB and voltage nodes VN 1  and VN 2 , each discussed above with respect to  FIG.  1   . 
     In addition to input terminal A 1 , memory circuit  530  includes a PMOS transistor P 6  coupled between voltage node VN 2  and a node ND 4 , a PMOS transistor P 7  and an NMOS transistor N 5  coupled in series between node ND 4  and voltage node VN 1 , and a PMOS transistor P 8  and an NMOS transistor N 8  coupled in series between node ND 4  and voltage node VN 1 . 
     Each of PMOS transistor P 7  and NMOS transistor N 5  includes a gate terminal electrically coupled with bit line BL, and a source/drain terminal electrically coupled with a node NDS. PMOS transistor P 7  and NMOS transistor N 5  are thereby configured as an inverter having an input terminal electrically coupled with bit line BL and an output terminal electrically coupled with node NDS. An NMOS transistor N 9  includes a gate terminal electrically coupled with node ND 5  and is coupled between bit line BL and voltage node VN 1 , thereby being usable as switching device  133 A discussed above with respect to switching circuit  130 A and  FIG.  1   . 
     Each of PMOS transistor P 8  and NMOS transistor N 8  includes a gate terminal electrically coupled with bit line BLB, and a source/drain terminal electrically coupled with a node ND 6 . PMOS transistor P 8  and NMOS transistor N 8  are thereby configured as an inverter having an input terminal electrically coupled with bit line BLB and an output terminal electrically coupled with node ND 6 . An NMOS transistor N 10  includes a gate terminal electrically coupled with node ND 6  and is coupled between bit line BLB and voltage node VN 1 , thereby being usable as switching device  133 B discussed above with respect to switching circuit  130 B and  FIG.  1   . 
     An NMOS transistor N 6  is coupled between node ND 5  and voltage node VN 1 , and an NMOS transistor N 7  is coupled between node ND 6  and voltage node VN 1 . Each of PMOS transistor P 6  and NMOS transistors N 6  and N 7  includes a gate terminal electrically coupled with input terminal Al configured to receive enable signal ENB. 
     In operation, in response to a logically high state of enable signal ENB at input terminal Al, PMOS transistor P 6  switches off, thereby electrically decoupling node ND 4  from voltage node VN 2 . In response to the logically high state of enable signal ENB at input terminal Al, each of NMOS transistors N 6  and N 7  switches on, thereby electrically coupling each of nodes ND 5  and ND 6  with voltage node VN 1  and providing a logically low state at the gate terminals of NMOS transistors N 9  and N 10 . 
     In operation, in response to the logically low states at the gate terminals, NMOS transistors N 9  and N 10  switch off, thereby electrically decoupling bit lines BL and BLB from voltage node VN 1 . With node ND 4  electrically decoupled from voltage node VN 2  and each of transistors N 6  and N 7  switched on, bit lines BL and BLB are not capable of being electrically coupled with voltage node VN 1  in response to the logically high state of enable signal ENB. 
     In operation, in response to a logically low state of enable signal ENB at input terminal Al, PMOS transistor P 6  switches on, thereby electrically coupling node ND 4  with voltage node VN 2 , and each of NMOS transistors N 6  and N 7  switches off, thereby electrically decoupling each of nodes ND 5  and ND 6  from voltage node VN 1 . The inverter formed by PMOS transistor P 7  and NMOS transistor N 5  is thereby enabled to control a logical state at the gate terminal of NMOS transistor N 9  by outputting a switching signal on node ND 5 , and the inverter formed by PMOS transistor P 8  and NMOS transistor N 8  is thereby enabled to control a logical state at the gate terminal of NMOS transistor N 10  by outputting a switching signal on node ND 6 . 
     In operation, in response to a logically low bit line BL or BLB voltage level, the corresponding inverter outputs the switching signal having a logically high voltage level, thereby causing the corresponding NMOS transistor N 9  or N 10  to switch on and electrically couple bit line BL or BLB to voltage node VN 1 . In response to a logically high bit line BL or BLB voltage level, the corresponding inverter outputs the switching signal having a logically low voltage level, thereby causing the corresponding NMOS transistor N 9  or N 10  to switch off and electrically decouple the bit line BL or BLB from voltage node VN 1 . 
     Memory circuit  530 , by the configuration discussed above, is capable of realizing the benefits discussed above with respect to memory circuit  100  and  FIG.  1   . 
       FIGS.  6 A and  6 B  are diagrams of respective memory circuits  600 A and  600 B, in accordance with some embodiments. Each of memory circuits  600 A and  600 B is a subset of a memory macro and includes a plurality of instances of plurality of memory cells  120 , a corresponding plurality of bit lines BL and BLB, a corresponding plurality of write circuits  110 , and a corresponding plurality of switching circuits  630  usable as combinations of switching circuits  130 A and  130 B, each discussed above with respect to memory circuit  100  and  FIG.  1   . 
     Memory circuits  600 A and  600 B differ in the positioning of each switching circuit  630  relative to the corresponding plurality of memory cells  120 , as discussed below. 
     In addition to the plurality of instances of plurality of memory cells  120 , bit lines BL and BLB, write circuits  110 , and switching circuits  630 , each of memory circuits  600 A and  600 B includes an I 0  circuit  640  and a control circuit  650 . I 0  circuit  640  is configured to manage input and output operations related to storing and retrieving data to and from the plurality of instances of plurality of memory cells  120 , and I 0  circuit  640  includes the plurality of write circuits  110 . 
     Control circuit  650  is configured to control operations of each of memory circuits  600 A and  600 B, in part by generating one or both of enable signals EN and ENB, discussed above with respect to memory circuit  100  and  FIG.  1   , and to output the one or both of enable signals EN and ENB to a bus  652 . 
     Each switching circuit  630  is configured to receive the one or both of enable signals EN and ENB from bus  652 , and, responsive to the one or both of enable signals EN and ENB, electrically couple one or both of corresponding bit lines BL or BLB to one or both of voltage nodes VN 1  or VN 2  further responsive to voltage levels on the corresponding bit lines BL or BLB, as discussed above with respect to  FIGS.  1 - 5   . 
     Each instance of plurality of memory cells  120  has a corresponding cell edge  620 A at an end of the plurality of memory cells  120  distal to I 0  circuit  640 . In memory circuit  600 A, each switching circuit  630  is located at a corresponding cell edge  620 A such that an entirety of the corresponding plurality of memory cells  120  is between the switching circuit  630  and I 0  circuit  640 . 
     In the embodiment depicted in  FIG.  6 A , each switching circuit  630  of memory circuit  600 A is located at an upper end of a corresponding plurality of memory cells  120 . In various embodiments, one or more switching circuits  630  are located at one or more ends of corresponding pluralities of memory cells  120  having other orientations, e.g., a lower, left, or right end of a plurality of memory cells  120 . 
     A given bit line BL or BLB is biased toward a bias voltage by a corresponding write circuit  110  current IBL or IBLB and by a corresponding switching circuit current IA 1 , IA 2 , IB 1 , or IB 2 , as discussed above with respect to memory circuit  100  and  FIG.  1   . By the configuration discussed above for memory circuit  600 A, the given bit line BL or BLB is biased by a first current at a first end and by a second current at a second end. 
     Because the given bit line BL or BLB has a resistance distributed along its length, voltage drops along the length caused by current flow are reduced compared to approaches that do not bias a bit line by a first current at a first end and a second current at a second end. Accordingly, bit line voltage levels corresponding to low logical states for a corresponding plurality of memory cells  120  are effectively lower, and bit line voltage levels corresponding to high logical states for a corresponding plurality of memory cells  120  are effectively higher, than voltage levels in approaches that do not bias a bit line by a first current at a first end and a second current at a second end. 
     In contrast to the configuration of memory circuit  600 A, switching circuits  630  in memory circuit  600 B are not located at corresponding cell edges  620 A. Instead, each plurality of memory cells  120  includes additional cell edges  620 B and  620 C between cell edge  620 A and I 0  circuit  640 , and each switching circuit  630  is located between corresponding cell edges  620 B and  620 C. 
     Each cell edge  620 C is located at an end of a first portion of a corresponding plurality of memory cells  120  adjacent to IO circuit  640  such that the first portion of the plurality of memory cells  120  is located between cell edge  620 C and IO circuit  640 . 
     Each cell edge  620 B is located at an end of a second portion of the corresponding plurality of memory cells  120  such that the second portion of the plurality of memory cells  120  is located between cell edges  620 A and  620 B, and the first portion of the plurality of memory cells  120  is located between IO circuit  640  and the second portion of the plurality of memory cells  120 . 
     In some embodiments, each of the first and second portions of a plurality of memory cells  120  has an equal number of memory cells. In some embodiments, one of the first or second portions of a plurality of memory cells  120  has a number of memory cells greater than a number of memory cells of the other of the first or second portions of the plurality of memory cells  120 . 
     In the embodiment depicted in  FIG.  6 B , each switching circuit  630  of memory circuit  600 B is located in a corresponding plurality of memory cells  120  extending upward. In various embodiments, one or more switching circuits  630  are located in one or more corresponding pluralities of memory cells  120  extending in other directions, e.g., downward, leftward, or rightward. 
     By the configuration discussed above for memory circuit  600 B, a given bit line BL or BLB is biased by a first current at a first end and by a second current at a second location away from the first end. 
     Because the given bit line BL or BLB has a resistance distributed along its length, voltage drops along the length caused by current flow are reduced compared to approaches that do not bias a bit line by a first current at a first end and a second current at a second location away from the first end. Accordingly, bit line voltage levels corresponding to low logical states for a corresponding plurality of memory cells  120  are effectively lower, and bit line voltage levels corresponding to high logical states for a corresponding plurality of memory cells  120  are effectively higher, than voltage levels in approaches that do not bias a bit line by a first current at a first end and a second current at a second location away from the first end. 
       FIG.  7    is a flowchart of a method  700  of biasing a bit line of a memory circuit, in accordance with one or more embodiments. Method  700  is usable with a memory circuit, e.g., memory circuits  100 ,  600 A, and  600 B, discussed above with respect to  FIGS.  1 ,  6 A, and  6 B . 
     The sequence in which the operations of method  700  are depicted in  FIG.  7    is for illustration only; the operations of method  700  are capable of being executed in sequences that differ from that depicted in  FIG.  7   . In some embodiments, operations in addition to those depicted in  FIG.  7    are performed before, between, during, and/or after the operations depicted in  FIG.  7   . In some embodiments, the operations of method  700  are a subset of operations of a method of operating a memory circuit. 
     At operation  710 , using a write circuit, a bit line voltage of the bit line is biased from a first voltage level toward a bias voltage level. Using the write circuit includes the write circuit providing a positive current to charge the bit line or providing a negative current to discharge the bit line. In some embodiments, using the write circuit includes providing one of currents IBL or IBLB, discussed above with respect to memory circuit  100  and  FIG.  1   . In some embodiments, using the write circuit includes providing the current at one end of the bit line. 
     The bit line corresponds to a plurality of memory cells of the memory circuit. In some embodiments, the write circuit is write circuit  110 , the bit line is one of bit lines BL or BLB, and the plurality of memory cells is plurality of memory cells  120 , each discussed above with respect to memory circuits  100 ,  600 A, and  600 B and  FIGS.  1 ,  6 A , and  6 B. 
     In some embodiments, biasing the bit line voltage includes biasing the bit line voltage toward a voltage level, e.g., ground or VSS, corresponding to a low logical state. In some embodiments, biasing the bit line voltage includes discharging the bit line as part of a write operation of the memory circuit. 
     In some embodiments, biasing the bit line voltage includes biasing the bit line voltage toward a voltage level, e.g., VDD, corresponding to a high logical state. In some embodiments, biasing the bit line voltage includes charging the bit line as part of a pre-charge operation of the memory circuit. 
     At operation  720 , the bit line voltage is received at a first input terminal of a logic circuit. Receiving the bit line voltage at the first input terminal includes receiving the bit line voltage at a terminal by which a logical state of the logic circuit is controlled. In some embodiments, receiving the bit line voltage includes receiving the bit line voltage at a gate of a transistor. 
     In various embodiments, receiving the bit line voltage includes receiving the bit line voltage at the first terminal of the logic circuit having one, two, or more than two input terminals. In some embodiments, receiving the bit line voltage includes receiving the bit line voltage at an input terminal of one or more of logic circuits  131 A,  132 A,  131 B, or  133 B, discussed above with respect to memory circuit  100  and  FIG.  1   . 
     In various embodiments, receiving the bit line voltage includes receiving the bit line voltage at an input terminal of one of NOR gates  231 A or  231 B, discussed above with respect to memory circuit  200  and  FIGS.  2 A and  2 B , one of NAND gates  332 A or  332 B, discussed above with respect to memory circuit  300  and  FIGS.  3 A and  3 B , one of inverters INV 1  or INV 2 , discussed above with respect to memory circuit  430  and  FIG.  4   , or one of the gate terminals of PMOS transistor P 7  and NMOS transistor N 5  or the gate terminals of PMOS transistor P 8  and NMOS transistor N 8 , discussed above with respect to memory circuit  530  and  FIG.  5   . 
     At operation  730 , in some embodiments, an enable signal is received at a second input terminal of the logic circuit. Receiving the enable signal at the second input terminal includes receiving the enable signal at a terminal by which a logical state of the logic circuit is controlled. In some embodiments, receiving the enable signal includes receiving the enable signal at a gate of a transistor. 
     In some embodiments, receiving the enable signal includes receiving the enable signal having a voltage level corresponding to one of two logical states, and the logic circuit has a first logical state in response to the first of the two logical states, and a second logical state in response to the second of the two logical states. 
     In various embodiments, receiving the enable signal includes receiving one of enable signals EN, ENB, BLPRE-ENB, or WAS_EN at one or more of input terminals A 1 , A 2 , B 1 , or B 2 , discussed above with respect to switching circuits  130 A and  130 B, memory circuits  200 ,  300 ,  430 , and  530 , and  FIGS.  1 - 5   . 
     At operation  740 , in response to the bit line voltage being biased toward the bias voltage level, the logic circuit is used to couple the bit line with a voltage node carrying the bias voltage level. Responding to the bit line voltage being biased toward the bias voltage level includes responding to the bit line voltage approaching to within a threshold value of the bias voltage level. In some embodiments, the threshold value is determined by a threshold voltage of a transistor in the logic circuit, and responding to the bit line voltage being biased toward the bias voltage level includes using the transistor to change a logical state of the logic circuit. 
     Using the logic circuit to couple the bit line with the voltage node carrying the bias voltage level includes causing the bit line to be electrically coupled with the voltage node at a location along the bit line. In some embodiments, the location along the bit line corresponds to cell edge  620 A, discussed above with respect to memory circuit  600 A and  FIG.  6 A . In some embodiments, the location along the bit line corresponds to cell edges  620 B and  620 C, discussed above with respect to memory circuit  600 B and FIG. 
       6 B. 
     In some embodiments, using the logic circuit to couple the bit line with the voltage node carrying the bias voltage level includes coupling one or both of bit lines BL or BLB with one of voltage nodes VN 1  or VN 2 , discussed above with respect to memory circuits  100 ,  200 ,  300 ,  430 , and  530 , and  FIGS.  1 - 5   . 
     In some embodiments, using the logic circuit to couple the bit line with the voltage node carrying the bias voltage level includes generating a switching signal with the logic circuit, and, in response to a logical state of the switching signal, closing a switching device coupled between the bit line and the voltage node. 
     Generating the switching signal includes generating the switching signal having a first voltage level corresponding to a first logical state in response to the bit line voltage being within the threshold value of the bias voltage level, and having a second voltage level corresponding to a second logical state in response to the bit line voltage being above or below the bias voltage level beyond the threshold value. 
     Closing the switching device in response to the switching signal includes closing the switching device in response to the switching signal transitioning from one of the first voltage level to the second voltage level or the second voltage level to the first voltage level. 
     In various embodiments, closing the switching device includes closing one of switching devices  133 A,  134 A,  133 B, or  134 B, discussed above with respect to memory circuit  100  and  FIG.  1   , or switching on one of NMOS transistors  233 A or  233 B, discussed above with respect to memory circuit  200  and  FIGS.  2 A and  2 B , PMOS transistors  334 A or  334 B discussed above with respect to memory circuit  300  and  FIGS.  3 A and  3 B , NMOS transistors N 1  or N 2 , discussed above with respect to memory circuit  430  and  FIG.  4   , or NMOS transistors N 9  or N 10 , discussed above with respect to memory circuit  530  and  FIG.  5   . 
     In some embodiments, using the logic circuit to couple the bit line with the voltage node carrying the bias voltage level is further in response to the enable signal received at the second input terminal of the logic circuit. In some embodiments, using the logic circuit to couple the bit line with the voltage node in response to the enable signal includes the logic circuit transitioning from a first logical state to a second logical state in response to the enable signal. 
     In some embodiments, using the logic circuit to couple the bit line with the voltage node in response to the enable signal includes the logic circuit generating the switching signal having a voltage level corresponding to a logical state based on the enable signal. 
     In some embodiments, the switching device is a first switching device coupled between the bit line and the voltage node, and using the logic circuit to couple the bit line with the voltage node in response to the enable signal includes closing a second switching device coupled between the bit line and the voltage node in response to the enable signal. 
     In some embodiments, using the logic circuit to couple the bit line with the voltage node in response to the enable signal includes turning on one of PMOS transistors P 1 , P 2 , or P 3  or NMOS transistors N 3  or N 4 , discussed above with respect to memory circuit  430  and  FIG.  4   . 
     Using the logic circuit to couple the bit line with the voltage node causes a current to flow between the bit line and the voltage node until such time as the voltage level on the bit line is equal to the bias voltage level. In various embodiments, using the logic circuit to couple the bit line with the voltage node causes one or more of currents IA 1 , IA 2 , IB 1 , or IB 2  to flow, as discussed above with respect to memory circuit  100  and  FIG.  1   . 
     Using the logic circuit to couple the bit line with the voltage node includes coupling the bit line with the voltage node simultaneously with using the write circuit to bias the bit line voltage. Because the bit line voltage is thereby biased toward the bias voltage using the current caused by being coupled with the voltage in addition to the current provided by the write circuit, the bit line is biased toward the bias voltage more rapidly than if the bit line were biased by either current alone. 
     By executing the operations of method  700 , a bit line is biased using a write circuit and a logic circuit so as to increase the operational speed of one or more pluralities of memory cells compared to approaches that do not use the write circuit and logic circuit, thereby obtaining the benefits discussed above with respect to memory circuit  100  and  FIG.  1   . 
     In some embodiments, a memory circuit includes a column of memory cells coupled to a bit line pair, a write circuit coupled to a first end of the bit line pair, wherein the write circuit is configured to, during a write operation, bias one of the bit lines toward a power supply voltage level and the other of the bit lines toward a reference voltage level, and first and second switching circuits, each coupled to a second end of a corresponding first or second bit line of the bit line pair, wherein each of the first and second switching circuits includes first and second logic circuits, each including an input terminal coupled to the corresponding first or second bit line, and first and second switching devices, each including a gate coupled to an output terminal of the corresponding first or second logic circuit. The first logic circuit and switching device are configured to couple the corresponding first or second bit line to a power supply node having the power supply voltage level simultaneously with the write circuit biasing the corresponding first or second bit line toward the power supply voltage level, and the second logic circuit and switching device are configured to couple the corresponding first or second bit line to a reference node having the reference voltage level simultaneously with the write circuit biasing the corresponding first or second bit line toward the reference voltage level. In some embodiments, each first logic circuit is configured to cause the corresponding first switching device to couple the corresponding first or second bit line to the power supply node responsive to a voltage level on the corresponding first or second bit line, and each second logic circuit is configured to cause the corresponding second switching device to couple the corresponding first or second bit line to the reference node responsive to the voltage level on the corresponding first or second bit line. In some embodiments, each first logic circuit is configured to cause the corresponding first switching device to couple the corresponding first or second bit line to the power supply node further responsive to a first enable signal, and each second logic circuit is configured to cause the corresponding second switching device to couple the corresponding first or second bit line to the reference node further responsive to a second enable signal complementary to the first enable signal. In some embodiments, the column of memory cells comprises SRAM cells. In some embodiments, the column of memory cells includes a number of memory cells ranging from  128  to  1024 . In some embodiments, the column of memory cells includes a number of memory cells greater than  1024 . In some embodiments, the column of memory cells is a one column of a plurality of columns of memory cells, the write circuit is coupled to first ends of bit line pairs coupled to each column of the plurality of columns, and the memory circuit includes corresponding first and second switching circuits coupled to second ends of each of the bit line pairs. 
     In some embodiments, a memory circuit includes a column of memory cells coupled to a bit line pair, a write circuit coupled to a first end of the bit line pair, wherein the write circuit is configured to, during a write operation, bias one of the bit lines toward a power supply voltage level and the other of the bit lines toward a reference voltage level, and first and second switching circuits, each coupled to a second end of a corresponding first or second bit line of the bit line pair, wherein each of the first and second switching circuits includes a NAND gate and a NOR gate, each comprising an input terminal coupled to the corresponding first or second bit line, a PMOS transistor comprising a gate coupled to an output terminal of the NAND gate, and an NMOS transistor comprising a gate coupled to an output terminal of the NOR gate. The NAND gate and PMOS transistor are configured to couple the corresponding first or second bit line to a power supply node having the power supply voltage level simultaneously with the write circuit biasing the corresponding first or second bit line toward the power supply voltage level, and the NOR gate and the NMOS transistor are configured to couple the corresponding first or second bit line to a reference node having the reference voltage level simultaneously with the write circuit biasing the corresponding first or second bit line toward the reference voltage level. In some embodiments, each NAND gate is configured to cause the corresponding PMOS transistor to couple the corresponding first or second bit line to the power supply node responsive to a voltage level on the corresponding first or second bit line, and each NOR gate is configured to cause the corresponding NMOS transistor to couple the corresponding first or second bit line to the reference node responsive to the voltage level on the corresponding first or second bit line. In some embodiments, each NAND gate is configured to cause the corresponding PMOS transistor to couple the corresponding first or second bit line to the power supply node further responsive to a first enable signal, and each NOR gate is configured to cause the corresponding NMOS transistor to couple the corresponding first or second bit line to the reference node further responsive to a second enable signal complementary to the first enable signal. In some embodiments, the column of memory cells comprises a number of memory cells ranging from  128  to  1024 . In some embodiments, the column of memory cells is a one column of a plurality of columns of memory cells, the write circuit is coupled to first ends of bit line pairs coupled to each column of the plurality of columns, and the memory circuit includes corresponding first and second switching circuits coupled to second ends of each of the bit line pairs. In some embodiments, each first and second switching circuit corresponding to each column of the plurality of columns is configured to receive complementary enable signals on a signal bus, and couple the corresponding first or second bit line to the power supply or reference node responsive to the complementary enable signals. In some embodiments, each column of the plurality of columns of memory cells includes SRAM cells. 
     In some embodiments, a method of operating a memory circuit includes performing a first write operation by using a write circuit coupled to a first end of a bit line pair coupled to a column of memory cells to bias a first bit line of the bit line pair toward a power supply voltage level and the second bit line of the bit line pair toward a reference voltage level, using a first logic circuit and first switching device of a first switching circuit coupled to a second end of the first bit line to couple the first bit line to a power supply node having the power supply voltage level simultaneously with the write circuit biasing the first bit line toward the power supply voltage level, and using a first logic circuit and first switching device of a second switching circuit coupled to a second end of the second bit line to couple the second bit line to a reference node having the reference voltage level simultaneously with the write circuit biasing the second bit line toward the reference voltage level, and performing a second write operation by using the write circuit to bias the first bit line toward the reference voltage level and the second bit line toward the power supply voltage level, using a second logic circuit and second switching device of the first switching circuit to couple the first bit line to the reference node simultaneously with the write circuit biasing the first bit line toward the reference voltage level, and using a second logic circuit and second switching device of the second switching circuit to couple the second bit line to the power supply node simultaneously with the write circuit biasing the second bit line toward the power supply voltage level. In some embodiments, each of using the first logic circuit and first switching device of the first switching circuit to couple the first bit line to the power supply node and using the second logic circuit and second switching device of the second switching circuit to couple the second bit line to the power supply node includes using a NAND gate coupled to a PMOS transistor coupled between the power supply node and the corresponding first or second bit line. In some embodiments, using the NAND gate coupled to the PMOS transistor includes the NAND gate receiving an enable signal and a voltage level of the corresponding first or second bit line. In some embodiments, each of using the second logic circuit and second switching device of the first switching circuit to couple the first bit line to the reference node and using the first logic circuit and first switching device of the second switching circuit to couple the second bit line to the reference node includes using a NOR gate coupled to an NMOS transistor coupled between the reference node and the corresponding first or second bit line. In some embodiments, using the NOR gate coupled to the NMOS transistor includes the NOR gate receiving an enable signal and a voltage level of the corresponding first or second bit line. In some embodiments, each of performing the first write operation and performing the second write operation includes performing a write operation on a SRAM cell. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.