Patent Publication Number: US-6040818-A

Title: Method and apparatus for displaying pixels on a display device

Description:
This is a continuation of application Ser. No. 07/879,075 filed May 1, 1992 now abandoned, which is a continuation of Ser. No. 07/565,598 filed Aug. 10, 1990, now abandoned. 
    
    
     TECHNICAL FIELD 
     The present invention generally relates to a display device wherein foreground pixels are displayed by a dark or low luminance level and background pixels are displayed by a high luminance level. 
     BACKGROUND ART 
     Display devices are known wherein characters, cursor, lines, etc. are displayed by illuminated pixels (also known as dots, pels or picture elements) with a black or non-illuminated background on a display screen. The display operations for displaying characters, cursor, etc. by the illuminated pixels on a black background will be referred to as a negative display mode or a white on black mode. The negative display mode includes a normal mode and a high intensity mode. In the normal mode characters, cursor, etc. are displayed with low luminance pixels on a black or non-illuminated background. In the high intensity mode the characters, cursor, etc. are displayed with high luminance pixels on a black or non-illuminated background. To control the luminance of a pixel, two binary bits are assigned for each pixel, and represent the luminance of one pixel, as follows: 
     0 0 . . . Zero luminance (Black) 
     0 1 . . . Low luminance (Gray) 
     1 0 . . . High luminance (White) 
     1 1 . . . Not used 
     Pixel patterns generated from a font memory include foreground pixels representing the characters to be displayed in combination with background pixels. 
     Japanese patent application 47-98526 (Published examined patent application No. 54-3581) shows a CRT display device wherein the background is displayed by low luminance, negative value is displayed by zero luminance, and positive value is displayed by high luminance. As a result, the negative and positive values in an equation are distinguishably displayed on the display screen. The application 47-98526, however, does not disclose the concept of the invention. 
     DISCLOSURE OF THE INVENTION 
     The present invention provides a signal generating means responsive to a normal mode signal by generating control signals for displaying low luminance foreground pixels and high luminance background pixels. In addition, the signal generating means is responsive to a high intensity mode signal by generating control signals for displaying zero luminance foreground pixels and high luminance background pixels. 
     In the present invention, the signal generating means first receives a pixel pattern wherein the foreground pixels are represented by a first binary number and the background pixels are represented by a second binary number. The signal generating means then responds to a normal mode signal by generating control signals for displaying low luminance or gray level foreground pixels and high luminance or white level background pixels. The signal generating means also responds to a high intensity mode signal by generating control signals for displaying zero luminance or black level foreground pixels and high luminance or white level background pixels. The characters of the normal mode of the positive display mode and the characters of the high intensity mode of the positive display mode may be simultaneously displayed on the display screen. 
     The invention solves the problem of prior art display devices. That is, the illegibility of the screen and the fatigue of the eyes of the operator when both the normal and high intensity modes of the positive display mode are simultaneously displayed on the screen. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The foregoing and other objects, aspects and advantages of the invention will be better understood from the following Best Mode for Carrying Out the Invention with reference to the figures listed below, in which: 
     FIG. 1 shows a prior art mode switching circuit; 
     FIG. 2 shows various pixel patterns at various points of the circuit shown in FIG. 1; 
     FIG. 3 shows images displayed by the circuit of FIG. 2. 
     FIG. 4 is a circuit diagram of a display device incorporating a mode switching circuit; 
     FIG. 5 is a block diagram of the mode switching circuit shown in FIG. 4; 
     FIG. 6 shows various pixel patterns at various points of the circuit shown in FIG. 5; 
     FIG. 7 shows an image displayed on a screen in accordance with the present invention; and 
     FIG. 8 shows a second embodiment of the present invention. 
    
    
     BEST MODE FOR CARRYING OUT THE INVENTION 
     FIG. 1 shows a merge circuit and a mode switching circuit for generating the two binary bits for each pixel. The pixel patterns generated from the font memory are merged with a trim line, a ruler or a cursor by OR gate 61 in the merge circuit. For illustrative purposes, it is assumed that a character T is displayed in the normal mode of the negative display mode. It is also assumed that no additional functions (i.e., trim, ruler and cursor) are used and that a character is represented by 5 pixels×7 pixels. In the negative display mode, a positive mode signal to an exclusive OR (XOR) gate 62 is at a low level, a normal mode signal to an AND gate 63 is at a high level, and a high intensity mode signal to an AND gate 64 is at a low level. The resulting output pixel patterns at the outputs A, A&#39;, B and C are shown in FIG. 2. The two bits on the output lines C and B are used as the two binary bits for controlling luminance of each foreground and background pixel. 
     The bit on line C is a high order bit and the bit on the line B is a low order bit. Referring to the pixel patterns 71C and 71B generated in this mode, the high order bit for each pixel of the foreground image portion of the character T is 0 and the low order bit for each pixel of the foreground image is 1. In addition, the high order bit for each pixel of the background portion is 0 and the low order bit for each pixel of the background portion is 0. 
     Therefore, in the normal mode of the negative display mode, the two bit combination (0 1) is assigned to each pixel of the foreground character image and the two bit combination (0 0) is assigned to each pixel of the background. As a result, the foreground image is represented by low luminance or gray level pixels, and the background is represented by non-illuminated or black level pixels. 
     In the negative display mode, it is often necessary to display the foreground image with the high intensity mode in addition to the normal mode. In the high intensity mode, the positive mode signal is low level, the normal mode signal is low level and the high intensity mode signal is high level. FIG. 2 shows the resulting pixel patterns 72A, 72A&#39;, 72B and 72C at the outputs A, A&#39;, B and C of FIG. 1. In the high intensity mode of the negative display mode, the two bit combination (1 0) is assigned to each pixel of the foreground character image, and the two bit combination (0 0) is assigned to each pixel of the background. As a result, the foreground character image is represented by high luminance or white level pixels, and the background is represented by non-illuminated or black level pixels. 
     Recently, it has been necessary to display the characters, cursors, etc. in the positive display mode or black on white mode wherein the characters or the foreground image are represented by non-illuminated pixels and the background is represented by illuminated pixels. To perform the positive display mode, the Exclusive OR gate 62 is added into the mode switching circuit and the positive mode signal is applied to the Exclusive OR gate 62. 
     The positive display mode also includes a normal mode and a high intensity mode. In the normal mode of the positive display mode, the positive mode signal and the normal mode signal are at a high level, and the high intensity mode signal is at a low level. FIG. 2 shows the resulting pixel patterns 73A, 73A&#39;, 73B and 73C at the outputs A, A&#39;, B and C of FIG. 1. In the normal mode, the two bit combination (0 0) is assigned to each pixel of the foreground character image, and the two bit combination (0 1) is assigned to each pixel of the background. As a result, the foreground character image T is represented by non-illuminated or black level pixels, and the background is represented by low luminance or gray level pixels. 
     In the high intensity mode, the positive mode signal and the high intensity mode signal are at a high level and the normal mode signal is at a low level. FIG. 2 shows the resulting pixel patterns 74A, 74A&#39;, 74B and 74C at the outputs A, A&#39;, B and C of FIG. 1. In this high intensity mode of the positive display mode, the two bit combination (0 0) from the patterns 74C and 74B is assigned to each pixel of the foreground character image, and the two bit combination (1 0) from the pattern 74C and 74B is assigned to each pixel of the background. As a result, the foreground character image T is represented by non-illuminated or black level pixels and the background is represented by high luminance or white level pixels. 
     The problem in the positive display mode is that the luminance of the background in the normal mode is the low luminance or gray level specified by the two bit combination (0 1), while the luminance of the background in the high intensity mode is the high luminance or white level specified by the two bit combination (1 0). Thus, in the case that both the normal mode and high intensity mode are simultaneously displayed on a display screen 81, as shown in FIG. 3, the background is displayed by the two kinds of luminance (i.e., the low luminance or gray level and the high luminance or white level). For example, areas 82 and 83 of the high intensity mode have a high luminance background, while the areas 84, 85 and 86 of the normal mode have a low luminance background. The mixed display of these areas on the display screen is often illegible, and causes an asthenopia or fatigue of the operator&#39;s eyes. 
     As shown in FIG. 3, the mark # is a field attribute representing the normal mode, and the mark @ is a field attribute representing the high intensity mode. It is noted that both the marks # and @ are actually not displayed on the display screen. The field attribute is placed at the top of a field including plural character boxes, and defines the attribute characteristics of the field. 
     One reason for the background luminance changing in the positive display mode is a basic concept from the negative display mode. The luminance of the pixels represented by the binary number 1 of the pixel pattern of the output A&#39; in the FIG. 1 is changed between the two luminance levels. That is, in accordance with the concept of the negative display mode, the foreground pixels represented by the binary number 1 in the positive display mode correspond to the background pixels as shown in the pixel patterns 73A&#39; and 74A&#39; in FIG. 2. In addition, the luminance of the background pixels represented by the binary number 1 are switched between the low luminance (0 1) in the normal mode and the high luminance (1 0) in the high intensity mode. 
     FIG. 4 shows a circuit diagram of a display device or terminal incorporating a mode switching function in accordance with the present invention. A control device 1, such as a microprocessor, controls the operations of the blocks shown in FIG. 4. In practice, a large number of control lines for controlling the operations of the blocks are connected between control device 1 and the blocks. However, for simplifying the drawing, the control lines are not shown. 
     The circuit includes a column, line, row counter 2, an address generator 3, a character code buffer 4, an attribute buffer 5, a character code register (C/C) 6, a font memory 7, a parallel/serial converter 8, a merge circuit 9, a signal generating circuit or a mode switching circuit 10, a video circuit 11, and CRT display device 12. The operations of many of these blocks are well known in the art and are easily explained. 
     The character codes and the attributes of the characters displayed on CRT display device 12 are stored in character code buffer 4 and attribute buffer 5 under the control of control device 1. The display screen of CRT display device 12 is divided into plural character boxes, such as 80 (horizontal)×32 (vertical). That is, 32 character rows, each of which includes 80 character boxes or columns, are displayed on the display screen. For example, each character box includes 9×19 pixels or picture elements, and one character in the box is represented by 5×7 pixels. The positions of the character boxes in the horizontal and vertical directions are represented by columns and rows. One row includes 19 scan lines in this example. Scan lines are traced in accordance with a raster scan scheme. 
     Column, line, row counter 2 counts the number of columns, lines, rows in order to control the display of the characters on display device 12. The count values from column, line, row counter 2 are supplied to address generator 3, which generates addresses for sequentially accessing both character code and attribute buffers 4 and 5. The character codes of the characters of one row are stored in character code register 6 for repeatedly accessing the character pixel patterns in font memory 7, whereby the pixel patterns on one scan line of the character patterns in one row are supplied, in parallel, to parallel/serial converter 8. Converter 8 serially supplies the pixel patterns of plural characters on one scan line to merge circuit 9. In merge circuit 9 a trim line, a ruler line or a cursor is added to the pixel pattern of selected character boxes. The pixel patterns from merge circuit 9 are supplied to signal generating circuit or mode switching circuit 10. The attribute representing the normal mode or the high intensity mode is also supplied to mode switching circuit 10. 
     The details of merge circuit 9 and mode switching circuit 10 are shown in FIG. 5. Merge circuit 9 includes an OR gate 21. The pixel pattern generated by font memory 7 is merged with a trim line, a ruler line or a cursor by OR gate 21. For illustrative purposes, it is assumed that a character T is displayed and the trim, ruler and cursor are not merged. 
     Mode switching circuit 10 includes AND gates 22, 23, 25 and 26, NOR gate 24, an inverter 27 and an OR gate 28. The character pixel patterns on one scan line of one row are sequentially supplied to OR gate 21. The output line of OR gate 21 is connected to one input of AND gates 22 and 23. The normal mode signal is applied to the other input of AND gate 22, the high intensity mode signal is supplied to the other input of AND gate 23, and the positive display mode signal is supplied to the input of inverter 27. 
     Two bits (high and low) are used to control the luminance of each pixel in the character box on the display screen, in the same manner as the prior art technology described above. 
     The luminance assigned to the two bit combination is as follows: 
     0 0 . . . Zero luminance (Black level) 
     0 1 . . . Low luminance (Gray level) 
     1 0 . . . High luminance (White level) 
     1 1 . . . Not used 
     The luminance assignment is the same as that in the prior art technology. 
     Output B of AND gate 22 is used as the low order bit of the two bit combination. Output B of AND gate 22 is also supplied to the one input of NOR gate 24. Output C of AND gate 23 is supplied to one input of AND gate 26 and the other input of NOR gate 24. Output D of NOR gate 24 is supplied to one input of AND gate 25. The positive display mode signal is also supplied to the other input of AND gate 25. The output of inverter 27 is supplied to the other input of AND gate 26. The outputs of AND gates 25 and 26 are supplied to OR gate 28. Output E of OR gate 28 is used as the high order bit of the two bit combination. 
     FIG. 6 shows the pixel patterns of the character T at outputs A, B, C, D and E of the circuit shown in FIG. 5 in various modes of operation. For example, pixel patterns 31A, 32A, 33A and 34A show the output bits at output A of merge circuit 9 in FIG. 5. These pixel patterns are supplied to mode switching circuit 10 as the input pixel pattern in the respective operational mode. In the pixel pattern received by mode switching circuit 10, the foreground pixels (i.e. image pixels of the character T) are represented by one binary number (i.e. the binary number 1), and the background pixels of the character T are represented by the other binary number (i.e. the binary number 0). The two bit combination for each pixel is then supplied to video circuit 11 which controls the intensity of the scanning beam of the CRT display device 12. 
     In the normal mode of the negative display mode, the normal mode signal is at a high level, and both the high intensity mode signal and positive mode signal are at a low level. As shown by pixel patterns 31E and 31B, the high order bit of the foreground portion of the image is 0, and the low order bit of the foreground portion of the image is 1. As a result, the foreground image is displayed by low luminance specified by the two bit combination (0 1). In addition, the high order bit and the low order bit of the background portion of the image are both 0. As a result, the background is displayed by zero luminance specified by the two bit combination (0 0). 
     In the high intensity mode of the negative display mode, the high intensity mode signal is at a high level, and both the normal mode signal and positive display mode signal are at a low level. As shown in pixel patterns 32E and 32B, the foreground image is displayed by high luminance specified by the two bit combination (1 0) and the background is displayed by zero luminance specified by the two bit combination (0 0). 
     Thus, the present invention provides the same luminance as the prior art in the negative display mode (as described above with respect to pixel patterns 71B, 71C, 72B and 72C in FIG. 2). 
     In the normal mode of the positive display mode, the normal mode signal and the positive display mode signals are at a high level, and the high intensity mode signal is at a low level. The pixel patterns at outputs A, B, C, D and E of FIG. 5 in this mode are shown by pixel patterns 33A, 33B, 33C, 33D and 33E of FIG. 6. As shown by pixel patterns 33E and 33B, the high order bit of the foreground portion of the image is 0 and the low order bit of the foreground portion of the image is 1. Thus, each pixel of the foreground image is displayed by low luminance or gray level specified by the two bit combination (0 1). In addition, the high order bit and the low order bit of the background portion of the image are 1 and 0, respectively. Thus, the background is displayed by high luminance specified by the two bit combination (1 0). 
     In the high intensity mode of the positive display mode, the normal mode signal is at a low level, and both the high intensity mode signal and the positive display mode signal are at a high level. As shown in pixel patterns 34E and 34B, the foreground image is displayed by zero luminance or black level specified by the two pixel combination (0 0) and the background is displayed by high luminance specified by the two bit combination (1 0). 
     It is noted that the background in both the normal and high intensity modes of the positive display mode is displayed by high luminance. However, the luminance of the foreground image is switched between the low luminance in the normal mode and the zero luminance in the high intensity mode. 
     FIG. 7 shows an example of a displayed image on the screen of CRT display device 12 in accordance with the present invention. This displayed image matches the displayed image described in FIG. 3 above. As in FIG. 3, the mark @ in FIG. 7 is the field attribute representing the high intensity mode, and the mark # is the field attribute representing the normal mode. It is again noted that neither of the marks @ and # are actually displayed on the display screen. 
     In FIG. 7, although both the normal and high intensity modes are displayed together, the I.uminance of the entire background is high intensity. This is different from the prior art technology wherein the background areas 82 and 83 are displayed by high luminance and background areas 84, 85 and 86 are displayed by low luminance. As a result of this difference, The present invention solves the problems of screen illegibility and the asthenopia or fatigue of the operator&#39;s eyes caused by prior art technology. 
     FIG. 8 shows a second embodiment wherein the concept of the present invention is used in a liquid crystal display (LCD). Pixel 52 corresponds to one pixel shown in FIG. 6. Pixel 52 includes plural LCD cells, such as LCD cells 53A, 53B, 53C and 53D. Each LCD cell is switched between the first state wherein the liquid crystal material is in an opaque state, and the second state wherein the liquid crystal material is in a transparent state. 
     The two bit combination for each pixel is applied to an LCD control circuit 51. When the two bit combination (1 0) is applied, LCD control circuit 51 generates a high luminance pixel 52A by switching all four LCD cells to the transparent state whereby light, such as from a backlight source, is transmitted through the four cells. When the two bit combination (0 1) is applied, LCD control circuit 51 generates a low luminance pixel 52B by switching two LCD cells to the transparent state and the other two LCD cells to the opaque state. When the two bit combination (0 0) is applied, LCD control circuit 51 generates a zero luminance pixel 52C by switching all four LCD cells to the opaque state. 
     The invention can also be used to control a plasma display device, an electroluminescence display device, a LED display device, etc. The luminance of the foreground and background pixels of a color display device can also be controlled in accordance with the invention. 
     While the invention has been described with reference to the illustrated embodiment, this description is not intended to be construed in a limiting sense. Various modifications of the illustrated embodiment as well as other embodiments of the invention will become apparent to those persons skilled in the art upon reference to this description. It is, therefore, contemplated that these appended claims will cover any such modifications or embodiments as fall within the true scope of this invention.