Patent Publication Number: US-9892226-B2

Title: Methods for providing macro placement of IC

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This Application claims priority of U.S. Provisional Application No. 62/159,468, filed on May 11, 2015, and U.S. Provisional Application No. 62/214,509, filed on Sep. 4, 2015, the entirety of which is incorporated by reference herein. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to a method for providing a macro placement of an integrated circuit (IC), and more particularly to a method for providing a macro placement of an IC with smoothness and dynamic macro channel. 
     Description of the Related Art 
     In recent years, the developing process of integrated circuits (ICs) such as super larger scale integrated circuits (LSIs) generally utilizes computer assisted design (CAD). According to such a developing process based on CAD, abstract circuit data, which corresponds to functions of an integrated circuit to be developed, is defined by using a so-called hardware description language (HDL), and the defined circuit is used to form a concrete circuit structure to be mounted on a chip. 
     Before the IC chips are manufactured (or implemented), the placements, the floor plans, and the layout areas of the IC chips are first considered so as to determine a die size for each IC chip. In general, the die size will affect the manufacturing cost of the IC chip. Therefore, it is desirable to optimize the floor plan of an IC chip for minimizing the layout area of the IC chip. 
     BRIEF SUMMARY OF THE INVENTION 
     Methods for providing a macro placement of an integrated circuit and a non-transitory computer-readable storage medium storing instructions are provided. An embodiment of a method for providing a macro placement of an integrated circuit is provided. An initial placement of the integrated circuit is obtained, wherein the initial placement comprises a plurality of first macro blocks. The first macro blocks are divided into a plurality of groups according to the hierarchy of the integrated circuit. A value of placement area is obtained for each of the groups according to macro areas of the first macro blocks. A plurality of candidate placements are obtained for each of the groups according to the value of placement area corresponding to the group, wherein the candidate placement comprises the first macro blocks corresponding to the group. A first macro placement is obtained according to a specific placement selecting from the candidate placements for each of the groups. 
     Furthermore, another embodiment of a method for providing a macro placement of an integrated circuit is provided. An initial placement of the integrated circuit is obtained, wherein the initial placement comprises a plurality of first macro blocks. The first macro blocks are divided into a plurality of groups according to the hierarchy of the integrated circuit. A value of placement area is obtained for each of the groups according to macro areas of the first macro blocks. A plurality of candidate placements are obtained for each of the groups according to the value of placement area corresponding to the group, wherein the candidate placement comprises the first macro blocks corresponding to the group, and each of the candidate placements comprises a rectangle having an individual length and an individual width. A specific placement is selected from candidate placements for each of the groups, and channel widths between the first macro blocks are adjusted in the specific placements. A first macro placement is obtained according to the specific placements. 
     Moreover, an embodiment of a non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for providing a macro placement of an integrated circuit. An initial placement of the integrated circuit is obtained, wherein the initial placement comprises a plurality of first macro blocks. The first macro blocks are divided into a plurality of groups according to the hierarchy of the integrated circuit. A value of placement area is obtained for each of the groups according to macro areas of the first macro blocks. A plurality of candidate placements are obtained for each of the groups according to the value of placement area corresponding to the group, wherein the candidate placement comprises the first macro blocks corresponding to the group. A first macro placement is obtained according to a specific placement selecting from the candidate placements for each of the groups. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  shows a flow chart illustrating a typical hierarchical design process of an integrated circuit (IC); 
         FIG. 2  shows a method for providing a macro placement of an IC according to an embodiment of the invention, wherein the method of  FIG. 2  is performed by a computer capable of operating an electronic design automation (EDA) tool; 
         FIG. 3A  shows an example illustrating an intermediate placement of an IC; 
         FIG. 3B  shows an example illustrating a macro placement of the IC of  FIG. 3A ; 
         FIG. 4  shows a flowchart of the rectangle optimization procedure for each group MG of step S 230  of  FIG. 2  according to an embodiment of the invention; 
         FIGS. 5A-5H  show an example illustrating a plurality of rectangles for a group MG comprising a plurality of macro blocks MB; 
         FIG. 6  shows a flowchart of the first placement procedure for the groups MG of step S 240  of  FIG. 2  according to an embodiment of the invention; 
         FIG. 7  shows a schematic illustrating a data flow control in an intermediate placement of an IC; 
         FIGS. 8A-8B  show an example illustrating two candidate placements CP 1  and CP 2  for a group MG comprising a plurality of macro blocks MB; 
         FIG. 9A  shows a schematic illustrating an intermediate placement without performing a macro smoothness procedure; 
         FIG. 9B  shows a schematic illustrating an intermediate placement by performing a macro smoothness procedure (step S 630  of  FIG. 6 ) on the intermediate placement of  FIG. 9A ; 
         FIG. 10  shows a schematic illustrating an adjustment in the channel widths between the macro blocks MB; and 
         FIG. 11  shows a computer system according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 1  shows a flow chart illustrating a typical hierarchical design process of an integrated circuit (IC). First, in step S 110 , a register-transfer-level (RTL) code describing the function performed by the IC is obtained. Next, in step S 120 , the RTL code is synthesized to generate gates for the IC. In general, the IC comprises a plurality of macro blocks, and each macro block provides a significant function for the IC, such as a specific processor (e.g. an application processor, a video processor, an audio processor, or a controller), a memory (e.g. a SRAM module) and so on. Furthermore, each macro block has a corresponding RTL code, and then the RTL codes of each macro block are synthesized to generate the gates of the macro block. Next, in step S 130 , according to a macro placement comprising a plurality of placements of the macro blocks, a whole chip placement procedure is performed to generate a placement of the gates within a chip area of the IC. For example, assuming that the IC comprises N macro blocks, N placements of the N macro blocks will have previously been generated according to the RTL codes of the macro blocks. Thus, according to the N placements of the N macro blocks and the gates that do not belong to the N macro blocks, the whole chip placement procedure is performed and a whole chip placement is obtained. Next, the routing paths are obtained according to the whole chip placement (step S 140 ), and then it is checked whether there is any congestion in the whole chip placement according to the routing paths (step S 150 ). If there is no congestion, the IC is implemented according to the whole chip placement and routing paths (step S 170 ). If there is congestion, the chip area of the IC must be modified to handle the congestion (step S 160 ), and then the automatic place and route (APR) procedure is performed again (steps S 130  and S 140 ) so as to generate a new whole chip placement of the gates with the corresponding routing paths within the increased chip area of the IC. 
       FIG. 2  shows a method for providing a macro placement of an IC according to an embodiment of the invention, wherein the method of  FIG. 2  is performed by a computer capable of operating an electronic design automation (EDA) tool. First, in step S 210 , a processor of the computer obtains the initial placement of the IC, and the initial placement can be displayed in a graphical user interface (GUI). The initial placement comprises a plurality of macro blocks MB of the IC that are placed in a layout area of the IC. Next, in step S 220 , the processor performs a macro grouping procedure according to the hierarchy information of the macro blocks MB in the IC, so as to divide the macro blocks MB of the IC into a plurality of groups MG For example, the macro blocks MB corresponding to the same hierarchy path in the IC will be grouped/divided into the same group MG Next, in step S 230 , the processor performs a rectangle optimization procedure on each group MG, so as to obtain a plurality of candidate placements CP for each group MG Next, in step S 240 , the processor performs a first placement procedure for the groups MG, so as to select a placement from the candidate placements CP for each group MG, and to place the selected placements of the groups MG in the layout area of the IC according to a specific rule, thereby obtaining an intermediate placement for the groups MG of the IC. Next, in step S 250 , it is determined whether any macro block MB is removed from the corresponding placement of the group MG in the intermediate placement. If no macro block MB is removed from the corresponding placement of the group MG, a macro placement is obtained according to the first placement for the IC (step S 270 ). Conversely, if the macro blocks MB are removed from the corresponding placements of the groups MG, the processor performs a second placement procedure according to the intermediate placement, so as to place the removed macro blocks MB into the intermediate placement (step S 260 ), thereby obtaining a macro placement for the IC (step S 270 ). As described above, a whole chip APR is performed after obtaining the macro placement of all the macro blocks of an IC, e.g. steps S 130  and S 140  of  FIG. 1 . In the embodiment, by placing all the macros within a layout area of the IC, the macro placement of all the macro blocks can provide an optimum blank space between the macro blocks to optimize routability and satisfy timing constraints for the IC. Thus, cost of a place and route (APR) procedure (e.g. steps S 130  and S 140  of  FIG. 1 ) can be decreased. For example, manpower cost and execution time can be decreasing in the APR procedure. 
       FIG. 3A  shows an example illustrating a macro placement  300  of an IC, and  FIG. 3B  shows an example illustrating a macro placement  350  of the IC, wherein the IC comprises a plurality of groups MG 1 -MG 8 . The macro placement  300  of  FIG. 3A  is obtained via the first placement procedure (step S 240  of  FIG. 2 ), and the macro placement  350  of  FIG. 3B  is obtained via the second placement procedure (step S 270  of  FIG. 2 ). In the macro placement  300  of  FIG. 3A  and the macro placement  350  of  FIG. 3B , a plurality of placements CP 1 -CP 8  are the optimal placements for groups MG 1 -MG 8 , respectively. For example, the placement CP 1  is the optimal placement selected from the candidate placements CP of the group MG 1 , the placement CP 2  is the optimal placement selected from the candidate placements CP of the group MG 2 , and so on. In the embodiment, the placements CP 1 -CP 8  are placed around a layout area of the IC according to a specific rule. For example, the placements CP 1 -CP 8  are arranged in a surrounding portion of the layout area of the IC. Furthermore, a blank space BS between the placements CP 1 -CP 8  is used to place the standard cells or other macro blocks MB 1 -MB 12  of  FIG. 3B . In some embodiments, the macro blocks MB 1 -MB 12  are the macro blocks that are divided into groups MG 1 -MG 8  but are not disposed in the placements CP 1 -CP 8 , i.e. the macro blocks removed from the groups MG 1 -MG 8 . The details of the specific rule and the selection of the optimal placement of each group will be described below. 
       FIG. 4  shows a flowchart of the rectangle optimization procedure for each group MG of step S 230  of  FIG. 2  according to an embodiment of the invention. First, in step S 410 , the processor obtains the physical layout of each macro block MB in the group MG and obtains a macro area of each macro block MB according to the physical layout thereof. Next, in step S 420 , the processor sums up the macro areas of all the macro blocks MB within the group MG Next, in step S 430 , the processor obtains the value of placement area of the group MG according to the summed macro areas, layout information and constraints, e.g. the routing area estimation of the macro blocks MB, and the pin locations of each macro block MB. In general, the value of placement area of the group MG is larger than the summed macro areas. Next, in step S 440 , the processor obtaining a plurality of rectangles for the group MG according to the value of placement area of the group MG It should be noted that the area of each rectangle is equal to the value of placement area. Furthermore, the rectangles have different lengths and different widths. Next, in step S 450 , the processor places the macro blocks MB of the group MG into each rectangle, and further determine whether each rectangle with all the macro blocks MB is capable of being a candidate placement CP for the group MG For example, if all the macro blocks MB can be completely placed within the rectangle, the processor can determine that the rectangle with all the macro blocks MB is a candidate placement CP for the group MG Simultaneously, the processor dynamically adjusts a plurality of channel widths between the macro blocks MB into each rectangle. In some embodiments, if all the macro blocks MB cannot be completely placed within the rectangle (for example, at least one macro block MB exceeds a boundary of the rectangle), the processor can determine that the rectangle with all the macro blocks MB is not a candidate placement CP for the group MG In some embodiments, if all the macro blocks MB cannot be completely placed within the rectangle, the processor can remove the macro blocks MB exceeding the rectangle from the rectangle, and then the processor can determine that the rectangle with the remaining macro blocks MB is a candidate placement CP for the group MG. 
       FIGS. 5A-5H  show an example illustrating a plurality of rectangles  500 A- 500 H for a group MG comprising a plurality of macro blocks MB. The rectangles  500 A- 500 H are obtained according to a value of placement area of the group MG In the embodiment, area of each rectangle is equal to the value of placement area of the group MG Thus, the areas of the rectangles  500 A- 500 H are the same. Furthermore, the lengths of the rectangles  500 A- 500 H are different, and the widths of the rectangles  500 A- 500 H are also different. In  FIG. 5A , the macro blocks MB 1 -MB 4  exceed the rectangle  500 A, thus the processor may determine that the rectangle  500 A associated with the macro blocks MB is not a candidate placement CP for the group MG Similarly, the macro blocks MB 2 -MB 3  and MB 5 -MB 6  exceed the rectangle  500 B of  FIG. 5B , the macro blocks MB 7 -MB 10  exceed the rectangle  500 E of  FIG. 5E , and the macro blocks MB 4 -MB 5  exceed the rectangle  500 F of  FIG. 5F . Thus, the processor may also determine that the rectangles  500 B,  500 E and  500 F associated with the macro blocks MB are not the candidate placements CP for the group MG On the contrary, the processor may determine that the rectangles  500 C,  500 D,  500 G and  500 H associated with the macro blocks MB are the candidate placements CP for the group MG due to there being no macro block MB that exceeds the rectangles  500 C,  500 D,  500 G and  500 H. 
     In some embodiments, the processor may determine that the rectangle  500 B,  500 E or  500 F is the candidate placement CP for the group MG by removing the macro blocks MB exceeding the rectangle. For example, the rectangle  500 B can be the candidate placement CP for the group MG after removing the macro blocks MB 2 , MB 3 , MB 5  and MB 6  from the rectangle  500 B of  FIG. 5B . Furthermore, when the placement of the rectangle  500 B is selected from the candidate placements CP of the group MG, the processor can perform the second placement procedure (e.g. S 260  of  FIG. 2 ), so aso to place the removed macro blocks MB 2 , MB 3 , MB 5  and MB 6  into the intermediate placement obtained by the first placement procedure (e.g. S 240  of  FIG. 2 ). 
       FIG. 6  shows a flowchart of the first placement procedure for the groups MG of step S 240  of  FIG. 2  according to an embodiment of the invention. First, in step S 610 , the processor selects an optimal placement from the candidate placements CP for each group MG Next, in step S 620 , the processor places the optimal placements in the layout area of the IC according to a specific rule, and further adjusts channel widths between macro blocks for each group MG, thereby obtaining a first intermediate placement for the groups MG In the embodiment, the number of the selected optimal placements is equal to the number of the groups MG in the first intermediate placement, i.e. each group MG has an individual selected optimal placement. In some embodiments, the specific rule is determined according to a data flow control for the IC, and information regarding a data flow can be extracted from connections by EDA tools or can be directly input by designers of the IC. Next, in step S 630 , the processor performs a macro smoothness procedure on the optimal placements in the first intermediate placement, so as to smooth the arrangement of the macro blocks MB and obtain a second intermediate placement for the groups MG Compared with a blank space BS of the first intermediate placement, a blank space BS of the second intermediate placement is a better area in which to place the standard cells and to route the routing paths between the standard cells and the groups MG For example, the height difference of the two adjacent macro blocks MB can be decreased by performing a macro smoothness procedure, wherein the two adjacent macro blocks MB may belong to the same group or different groups. It should be noted that the processor can analyze the blank space BS in the first and second intermediate placements, and determine which intermediate placement is suitable to perform subsequent procedure according to actual applications and various EDA parameters. 
       FIG. 7  shows a schematic illustrating a data flow control in an intermediate placement  700  of an IC. As described above, the processor will select an optimal placement from the candidate placements CP for each group MG and places the optimal placements of the groups MG in the layout area of the IC according to the constraints of the data flow control. The intermediate placement  700  comprises a plurality of groups MG 1 -MG 8  and a plurality of standard cell groups SG 1 -SG  7 , wherein each of the groups SG 1 -SG 7  comprises a plurality of standard cells (or gates). In the embodiment, two data flows are considered in the intermediate placement  700 , wherein one data is transmitted and processed according to a transmission path S 1  and another data is transmitted and processed according to a transmission path S 2  in the IC. The transmission path S 1  is formed from the group MG 1  to the group MG 5  through the groups SG 1 , MG 2 , SG 2 , MG 3 , SG 3 , MG 4  and MG 4  in sequence. Furthermore, the transmission path S 2  is formed from the group MG 4  to the group SG 1  through the groups MG 4 , MG 5 , SG 5 , MG 6 , SG 6 , MG 7 , SG 7  and MG 8  in sequence. Furthermore, the processor can arrange the start and/or end locations of the transmission paths S 1  and S 2 , and the transmission directions of the transmission paths S 1  and S 2  (e.g. clockwise or anti-clockwise). For example, the processor may place the group MG 1  (a start point of the transmission path S 1 ) in a corner  710  of the intermediate placement  700 , and then arranges/places the groups MG 2 -MG 5  in an anti-clockwise direction. Simultaneously, the processor may place the group MG 4  (a start point of the transmission path S 2 ) at an edge  720  of the intermediate placement  700 , and then arranges/places the groups MG 5 -MG 8  in an anti-clockwise direction. According to various constraints in the data flow control, the processor can assign the start/end point location (e.g. a specific corner or edge), the transmission direction (e.g. clockwise or anti-clockwise), and the touch edge (e.g. the edge of the intermediate placement  700  that the transmission path is touched or passed through) of the transmission path, and pin locations of the groups corresponding to the transmission path. In some embodiments, the processor can further consider a routing resource for the transmission paths, such as channel widths between the groups MG, and a routing area on top of the groups MG 
       FIGS. 8A-8B  show an example illustrating two candidate placements CP 1  and CP 2  for a group MG comprising a plurality of macro blocks MB. Referring to  FIG. 8A  and  FIG. 8B  together, the rectangles  800 A and  800 B are obtained according to the value of placement area of the group MG As described above, area of each rectangle is equal to the value of placement area of the group MG Thus, the areas of the rectangles  800 A- 800 B are the same. Furthermore, the lengths of the rectangles  800 A- 800 B are different, and the widths of the rectangles  800 A- 800 B are also different. If the constraint of a data flow control indicates that the group MG should be placed in a specific corner of an intermediate placement, the processor will select the candidate placement CP 1  of  FIG. 8A  as an optimal placement for the group MG Conversely, if the constraint of the data flow control indicates that the group MG should be placed at a specific edge of the intermediate placement, the processor will select the candidate placement CP 2  of  FIG. 8B  as an optimal placement for the group MG 
       FIG. 9A  shows a schematic illustrating an intermediate placement  900 A without performing a macro smoothness procedure. The intermediate placement  900 A comprises a plurality of groups MG 1 -MG 4 , and each of the groups MG 1 -MG 4  comprises a plurality of macro blocks MB. In the embodiment, the processor places the optimal candidate placements of the groups MG 1 -MG 4  at four different corners  910 - 940  in the intermediate placement  900 A. According to the candidate placements of the groups MG 1 -MG 4 , the processor can calculate a smoothness (SM) value for the macro blocks MB. In the embodiment, the processor will obtain the midpoint of at least one side of each macro block MB, and the midpoint of an edge of the intermediate placement  900 A where no macro block is placed. For example, the bottom edge E 1  of the intermediate placement  900 A has a midpoint MP 1 . Furthermore, the left side of the macro block MB 1  has a midpoint MP 2 , and the top side of the macro block MB 1  has a midpoint MP 3 . In the embodiment, three neighboring midpoints can obtain an included angle θ. According to all the included angles  9  in the intermediate placement  900 A, the processor can obtain the macro smoothness value SM according to the following formula (1): 
                     SM   =     ∑       -            L   ⁢           ⁢   1     →            ⁢            L   ⁢           ⁢   2     →          ⁢   tan   ⁢           ⁢     θ   2           ,           (   1   )               
where L 1  represents the length of a first line between the first and second midpoints of three neighboring midpoints, L 2  represents the length of a second line between the second and third midpoints of three neighboring midpoints, and θ represents the included angle between an extending part of the first line and the second line. For example, θ 1  represents an included angle between an extending part of a first line formed by the midpoints MP 3 -MP 4  and a second line formed by the midpoints MP 4 -MP 5 . Ideally, the absolute value of SM is as small as possible, and the included angle θ should be small. In the intermediate placement  900 A, the macro block MB 3  of the group MG 4  has an included angle θ 2  of over 90 degrees. Thus, the height difference between the macro block MB 3  and the adjacent macro block is large, and therefore it is difficult to rout around the macro block MB 3 , i.e. it is hard to perform a routing procedure in a blank space BS 1  of the intermediate placement  900 A.
 
       FIG. 9B  shows a schematic illustrating an intermediate placement  900 B by performing a macro smoothness procedure (step S 630  of  FIG. 6 ) on the intermediate placement  900 A of  FIG. 9A . In the intermediate placement  900 B, no included angle θ exceeds  90  degrees. Thus, the height difference between two adjacent macro blocks is small. Therefore, it is easy to perform a routing procedure in a blank space BS 2  of the intermediate placement  900 B by the processor. It should be noted that the rectangles of the groups MG 1 -MG 4  will be modified by the processor and the area of the modified rectangle is changed. Furthermore, if the rectangle is not modified, some macro blocks may be moved outside the rectangle. In some embodiments, the moved macro blocks will be placed in the second placement procedure (S 260  of  FIG. 2 ). 
       FIG. 10  shows a schematic illustrating an adjustment in the channel widths between the macro blocks MB. As described above, the channel widths can be adjusted in step S 620  of  FIG. 6  or step S 450  of  FIG. 4 . In  FIG. 10 , a channel width CH 1  represents a routing area between the macro blocks MB 1  and MB 2 , a channel width CH 2  represents a routing area between the macro blocks MB 2  and MB 3 , a channel width CH 3  represents a routing area between the macro blocks MB 3  and MB 4 , and a channel width CH 4  represents a routing area between the macro blocks MB 4  and MB 5 . After adjusting the channel widths between the macro blocks MB, the channel widths CH 1 -CH 4  are increased, and it is easy to perform a routing procedure in the routing areas for the processor. 
       FIG. 11  shows a computer system  100  according to an embodiment of the invention. The computer system  100  comprises a computer  110 , a display device  120  and a user input interface  130 , wherein the computer  110  comprises a processor  140 , a memory  150 , and a storage device  160 . The computer  110  is coupled to the display device  120  and the user input interface  130 , wherein the computer  110  is capable of operating an electronic design automation (EDA) tool. Furthermore, the computer  110  is capable of receiving input instruction from the user input interface  130  and displaying the physical layouts and the placements of macro blocks of the IC on the display device  120 . In one embodiment, the display device  120  is a GUI for the computer  110 . Furthermore, the display device  120  and the user input interface  130  can be implemented in the computer  110 . The user input interface  130  may be a keyboard, a mouse and so on. In the computer  110 , the storage device  160  can store the operating systems (OSs), applications, and data that comprise input required by the applications and/or output generated by applications. The processor  140  of the computer  110  can perform one or more operations (either automatically or with user input) in any method that is implicitly or explicitly described in this disclosure. For example, during an operation, the processor  140  can load the applications of the storage device  160  into the memory  150 , and then the applications can be used by the user to create, view, and/or edit a placement, a floor plan and a physical layout for a circuit design. 
     The data structures and code described in this disclosure can be partially or fully stored on a computer-readable storage medium and/or a hardware module and/or hardware apparatus. A computer-readable storage medium includes, but is not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs), DVDs (digital versatile discs or digital video discs), or other media, now known or later developed, that are capable of storing code and/or data. Hardware modules or apparatuses described in this disclosure include, but are not limited to, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), dedicated or shared processors, and/or other hardware modules or apparatuses now known or later developed. 
     The methods and processes described in this disclosure can be partially or fully embodied as code and/or data stored in a computer-readable storage medium or device, so that when a computer system reads and executes the code and/or data, the computer system performs the associated methods and processes. The methods and processes can also be partially or fully embodied in hardware modules or apparatuses, so that when the hardware modules or apparatuses are activated, they perform the associated methods and processes. Note that the methods and processes can be embodied using a combination of code, data, and hardware modules or apparatuses. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.