Patent Publication Number: US-6223328-B1

Title: Wire processing method, wire processing equipment, and recording medium for wire processing program used in designing a large scale integrated circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a wiring processing method, wiring processing equipment, and recording medium for a wiring processing program suitable for use in designing a large scale integrated circuit (LSI) using the computer aided design (CAD) system. 
     In clock nets on a clock distributing circuit of a clock synchronous circuit, to equalize the delay time (propagation delay time of a clock) from a clock generator (driver) to each of clock receivers, namely, to decrease a clock skew being a difference of a clock propagation delay time is a very important technique for stabilizing the operation of the clock distributing circuit. If the clock skew is large, the receivers on the nets will have a problem with synchronizing operation on the nets; and therefore, the clock skew of the clock distributing circuit has to be reduced. 
     Further, to minimize the lengths of wirings to connect circuit elements on an LSI and to enhance quality of wiring is necessary to speed up the processes in the LSI. 
     In this case, to estimate a possibility of a wiring before executing the wiring and from the possibility to improve a layout of the circuits and to optimize a wiring area should also be considered. 
     Especially at present, a wiring objective is inclined to have a gigantic scale, and an early estimation and evaluation of the possibility of wirings has increased the need. 
     2. Description of the Related Art 
     There have been many reports on the wiring processing method for reducing the clock skew, namely, a difference of a clock propagation delay time in the clock synchronous circuit. 
     The IBM method will hereunder be described which is a typical wiring processing method for reducing the clock skew. This method is detailed in ‘Ren-Song Tsay, “Exact zero skew”, Proc. IEEE Int. Conference on CAD, pp336-339, 1991’. 
     Before explaining the wiring processing method for reducing a clock skew, first, FIG. 34 illustrates a configuration of a clock tree in a clock net on a clock distributing circuit of a clock synchronous circuit. 
     A clock tree  130  comprises a sub-clock tree consisting of a clock receiver (receiving circuit)  112  and a wiring  118  and another sub-clock tree consisting of a clock receiver (receiving circuit)  115  and a wiring  121 , which are connected at an equal delay branch point (tapping point) “x” where the sub-clock trees have an equal delay. 
     Thus, in the clock tree  130 , a clock driver (clock generator) not illustrated in FIG. 34 supplies a clock signal to the receiver  112  and  115  through the equal delay branch point “x”. 
     Here, the receiver  112  is composed of a flip-flop (time constant t 1 )  113  and a capacitor (capacitance C 1 )  114 , and the receiver  115  is composed of a flip-flop (time constant t 2 )  116  and a capacitor (capacitance C 2 )  117 . 
     The wire  118  forms a Π type RC circuit consisting of one resistor (resistance r 1 )  119  and two capacitors (capacitance c 1 /2)  120 . 
     Further, in the same manner as the wire  118 , the wire  121  also forms the Π type RC circuit consisting of one resistor (resistance r 2 )  122  and two capacitors (capacitance c 2 /2)  123 . 
     Here, the reason that a wiring between the receiver  112  and  115  is represented by means of the one Π type RC circuit in FIG. 34 will now be described. 
     First, a close look at one sub-clock tree is requested. 
     FIG. 32 illustrates a model for a clock tree with a buffer, and as shown in this figure, the clock tree with a buffer  100  comprises a clock generator (clock source)  101  as the driver, a clock receiver (latch)  103  as the receiver, and a buffer  102  through which the former two are connected. 
     Here, the clock source  101  is connected to the buffer  102  through a wire  104  and the buffer  102  is connected to the latch  103  through the wire  105 . 
     This clock tree  100  has a configuration as shown in FIG. 33 in detail. 
     The clock source  101  has a resistor (resistance r s )  106 ; the buffer  102  has a delay circuit (internal delay time d b )  111 , a resistor (resistance r b )  107 , and a capacitor (capacitance c b )  109 ; the latch  103  has a capacitor (capacitance c 1 )  110 . 
     The delay time from the clock source  101  to the latch  103  includes the delay time due to the wiring resistors and capacitors of the wiring  104  and  105 , and the internal delay time d b  by the delay circuit  111  of the buffer  102 . 
     The wiring resistor has become a big problem as not negligible, since the size of transistors and the cross-sectional area of wirings have decreased owing to the recent progress in the semiconductor microstructuring technique. 
     Accordingly, it has become necessary to deal with the wiring  104  and  105  as a distributed constant circuit from accuracy for estimating the delay time. Generally, as shown in FIG. 33, the wiring  104  and  105  have been evaluated by means of the Π type RC circuit composed of one resistor (resistance r s )  106  and two capacitors (capacitance c 1 /2)  108  as a concentrated constant circuit being a typical form of the distributed constant circuit. 
     Incidentally, the equal delay branch point “x” is an input point of a clock from the driver (clock generator) not illustrated in FIG.  34 . 
     In the clock tree  130  shown in FIG. 34, the clock skew by the two sub-clock trees of the clock tree 130 varies depending on the position of the equal delay branch point “x”. Therefore, the position of the equal delay branch point “x” has to be set very accurately so as to reduce the clock skew in the clock tree  130 . 
     According to the method (zero-skew-merge) to determine the equal delay branch point “x” in the wiring between the two sub-clock trees, the equal delay branch point “x” is known to satisfy the following equation. 
     
       
           r   1  ( c   1 /2 +C   1 )+ t   1   =r   2  ( c   2 /2 +C   2 )+ t   2 . 
       
     
     Where L, α, β are given as below, 
     L: wiring length between the two sub-clock trees 
     α: resistance for unit length of the line 
     β: capacitance for unit length of the line the equal delay branch point “x” is determined by the following: 
     
       
           x= [( t   2   −t   1 )+α L  ( C   2   +βL/ 2)]/[α L  (β L+C   1   +C   2 )]. 
       
     
     Incidentally, circuits on an LSI are connected through optimum wiring paths searched by means of an automatic wiring system. 
     There have been many reports on the automatic searching method for wiring paths, and the Mikami-Tabuchi method as a kind of the line segment searching method will hereafter be described. 
     The line segment searching method is a method to search wiring paths while sequentially generating vertical or horizontal probes, which has an advantage in a high speed processing with a small storage capacity. 
     In the Mikami-Tabuchi method, as shown in FIG. 35, first, temporal line segments of level 0 are generated in the horizontal direction from the search start point S and the search end point T. Where there is no overlapping with these temporal line segments, next, temporal line segments of level 1 intersecting vertically to the line segments of level 0 are generated. 
     And, repeating these steps, when the temporal line segments from both sides intersect, the intersecting line segments are searched backward, thereby finding a wiring path, for example, as shown in FIG.  36 . 
     The Mikami-Tabuchi method can find a wiring path invariably where there is a wiring path, however, the number of the temporal line segments increases rapidly as the level increases, and in the worst case, as many temporal line segments as the number of the grids have to be searched. Thus, the method is applied wherein the level number of the temporal line segments is limited to, for example, 2 or 3. 
     However, in the clock tree  130  as shown in FIG. 34, the foregoing wiring  118  and  121  each are evaluated by means of a single Π type RC circuit (Π type RC model). 
     This is because the resistance and capacitance for each unit grid in the wiring on both sides of the equal delay branch point x are assumed equal regardless of the position in determining the equal delay branch point “x”. 
     However in reality, it is impossible that the resistance and capacitance for each unit grid are equal regardless of the position; and therefore, it becomes necessary to determine the equal delay branch point “x” from the evaluation of a series Π type RC circuit (series Π type RC model) obtained by dividing the wiring  118  and  121  into a plurality of segments, which will be a problem to be solved. 
     Furthermore, in the clock tree  130  as shown in FIG. 34, there is another problem in determining the equal delay branch point “x” that the delay time from the clock driver to each of the clock receivers has to be set to a target value while considering gate delays (extra-source gate delay) increased by applying loads to the clock driver not illustrated. 
     In the Mikami-Tabuchi method being one method for automatic searching for wiring paths, the temporal line segments (search segments) of the same level are processed without influencing each other, and therefore, it is possible to speed up the search for the line segments when the processing of search segments can be executed in parallel. 
     However, in the Mikami-Tabuchi method, since a point once searched is not searched again, and when a wiring path not optimum is searched before an optimum wiring path is searched, the wiring path not optimum can possibly be selected, which is another problem. 
     Accordingly, to solve the problem requires a method whereby a plurality of wiring paths can be searched and an optimum wiring path can be selected therefrom. 
     Further as mentioned above, if the possibility of wiring can be estimated before executing a wiring in the design of an LSI, it will be possible to improve the layout of a circuit and to optimize a wiring area from the possibility of wiring. 
     However, it is difficult to know the wiring possibility of a wiring objective when finishing the layout of a circuit, and there is a problem that the wiring possibility cannot be known before finishing the wiring. 
     SUMMARY OF THE INVENTION 
     The present invention has been made in view of the foregoing problems, and it is therefore an object of the present invention to provide a wiring processing method suitable for use in the design of an LSI using the CAD. More concretely, it is an object to provide a wiring processing method and wiring processing equipment, whereby the clock skew of a clock distributing circuit can be reduced through determining an equal delay branch point (tapping point) and taking an external clock delay time into account, the processing speed can be increased through performing a parallel processing of search segments in searching wiring paths, the lengths of wirings connecting to the circuits on an LSI can be minimized and the quality of wiring can be improved through selecting optimum wiring paths, and the layout of the circuits on an LSI can be improved and the wiring areas can be optimized through estimating the wiring possibility before executing wiring. It is further an object to provide a recording medium in which a wiring processing program is recorded for a computer executing the procedure of the aforementioned wiring processing. 
     In order to accomplish the foregoing objects, a wiring processing method of the invention comprises: a segment dividing step for dividing a wiring connecting between two receivers of a clock net on a clock distributing circuit of a clock synchronous circuit into three or more segments through setting two or more dividing points; an equal delay branch segment determining step for comparing a first delay time from one dividing point on one end of the segment obtained by the segment dividing step to one receiver of the two receivers with a second delay time from the one dividing point to the other receiver of the two receivers, and comparing a third delay time from the other dividing point on the other end of the segment to the one receiver of the two receivers with a fourth delay time from the other dividing point to the other receiver of the two receivers, and determining a segment in which a magnitude of the first delay time against the second delay time and a magnitude of the third delay time against the fourth delay time are inverted as an equal delay branch segment where an equal delay branch point exists; and an equal delay branch point determining step for determining an equal delay branch point in the equal delay branch segment determined by the equal delay branch segment determining step. 
     The abovementioned dividing points set by the segment dividing step may be physical points on the wiring, or points at which an impedance for a unit length of the wiring changes. And, the segments obtained by the segment dividing step can be evaluated by means of a single Π type circuit. 
     Further, the first through the fourth delay time in the foregoing equal delay branch segment determining step can be obtained by the following equations:          the                 first                 delay                 time     =         ∑     i              =              1       k   -   1            [       r   i          (         ∑     j              =              1     i                     c   j                  -                  c   i     /   2                +                C   A       )       ]       +     t   A                 the                 second                 delay                 time     =         ∑     i              =              k     n          [       r   i          (         ∑     j              =              i     n                     c   j                  -                  c   i     /   2                +                C   B       )       ]       +     t   B                 the                 third                 delay                 time     =         ∑     i              =              1     k          [       r   i          (         ∑     j              =              1     i                     c   j                  -                  c   i     /   2                +                C   A       )       ]       +     t   A                 the                 fourth                 delay                 time     =         ∑     i              =                k              +              1       n          [       r   i          (         ∑     j              =              i     n                     c   j                  -                  c   i     /   2                +                C   B       )       ]       +     t   B                       
     here, 
     r i : resistance across a segment 
     c j : capacitance at a segment 
     C A : capacitance at the one receiver 
     C B : capacitance at the other receiver 
     t A : delay time by the one receiver 
     t B : delay time by the other receiver 
     n+1: total number of the dividing points 
     k: first number of the dividing points forming the equal delay branch segment. 
     Further, the equal delay branch point in the equal delay branch segment determining step can be obtained by 
     
       
         [( t   B   −t   A )+α L  ( C   B   +βL/ 2)]/[α L  (β L+C   A   +C   b )] 
       
     
     here, 
     L: wiring length between the two receivers 
     α: resistance for a unit length of the wiring 
     β: capacitance for a unit length of the wiring 
     C A : capacitance at the one receiver 
     C B : capacitance at the other receiver 
     t A : delay time by the one receiver 
     t B : delay time by the other receiver. 
     Accordingly, in the wiring processing method of the invention, a wiring connecting between two receivers of a clock net on a clock distributing circuit of a clock synchronous circuit is divided into three or more segments in obtaining an equal delay branch point, thereby, the equal delay branch point can accurately be obtained taking into account that a resistance and capacitance for a unit grid on the wiring are not equal independently of the positions. Therefore, the clock skew being a difference of a clock propagation delay in the clock synchronous circuit can be reduced. 
     According to another aspect of the invention, the wiring processing method comprises: a segment dividing step for dividing a wiring on a clock distributing circuit of a clock synchronous circuit into three or more segments through setting two or more dividing points; a propagation delay time determining step for obtaining a propagation delay time of the wiring in which the delay time of each of the segments obtained by the segment dividing step is taken into account; and a wiring length adjusting step for comparing the propagation delay time of the wiring obtained by the propagation delay time determining step with a preset time, and on the basis of the comparison result, adjusting a wiring length for each of the segments. 
     Further, the dividing points set by the foregoing segment dividing step may be points at which an impedance for a unit length of the wiring changes. 
     Furthermore, the segments obtained by the segment dividing step can be evaluated by means of a single Π type circuit. 
     Accordingly, in the wiring processing method of the invention, a wiring on a clock distributing circuit of a clock synchronous circuit is divided into three or more segments to adjust a wiring length for each segment, thereby, a delay time to each of the receivers can be made equal taking an external clock delay time into account. Therefore, the clock skew being a difference of a clock propagation delay in the clock synchronous circuit can be reduced. 
     According to another aspect of the invention, the wiring processing method comprises: a first segment dividing step for dividing a wiring connecting between two receivers of a clock net on a clock distributing circuit of a clock synchronous circuit into three or more segments through setting two or more dividing points; an equal delay branch segment determining step for comparing a first delay time from one dividing point on one end of the segment obtained by the first segment dividing step to one receiver of the two receivers with a second delay time from the one dividing point to the other receiver of the two receivers, comparing a third delay time from the other dividing point on the other end of the segment to the one receiver of the two receivers with a fourth delay time from the other dividing point to the other receiver of the two receivers, and determining a segment in which a magnitude of the first delay time against the second delay time and a magnitude of the third delay time against the fourth delay time are inverted as an equal delay branch segment where an equal delay branch point exists; an equal delay branch point determining step for determining an equal delay branch point in the equal delay branch segment determined by the equal delay branch segment determining step; a delay time determining step for obtaining a fifth delay time from the equal delay branch point obtained by the equal delay branch point determining step to each of the receivers; a second segment dividing step for setting two or more dividing points on a wiring from the equal delay branch point through an external clock source gate and dividing the wiring into three or more segments; a propagation delay time determining step for obtaining a propagation delay time of the wiring in which the delay time of each of the segments obtained by the second segment dividing step is taken into account, and a wiring length adjusting step for comparing the sum of the fifth delay time from the equal delay branch point to each of the receivers obtained by the delay time determining step and the propagation delay time of the wiring obtained by the propagation delay time determining step with a preset time, and on the basis of the comparison result, adjusting a wiring length for each segment. 
     In the foregoing wiring length adjusting step, the sum of the fifth delay time, the propagation delay time, and an external clock delay time at the external clock source gate is compared with a preset time, and on the basis of the comparison result, a wiring length may be adjusted for each segment. 
     Accordingly, in the wiring processing method of the invention, a wiring connecting between two receivers of a clock net on a clock distributing circuit of a clock synchronous circuit is divided into three or more segments to obtain an equal delay branch point and the length of a wiring from the equal delay branch point to an external clock source gate is adjusted for each segment while dividing the wiring into more than three segments. Thereby, the equal delay branch point can accurately be obtained taking into account that a resistance and capacitance for a unit grid on the wiring are not equal independently of the positions, and a delay time to each of the receivers can be made equal taking an external clock delay time into account. Therefore, the clock skew being a difference of a clock propagation delay time in the clock synchronous circuit can effectively be reduced. 
     According to another aspect of the invention relating to the wiring processing method, in determining a wiring path of a wiring on a circuit board, a wiring area is in advance divided into grids by a unit of a minimum pitch of the wiring, and an available flag to indicate whether a grid is available for the wiring or not, an arrival state flag to indicate that a search segment arrives at the grid, and an arrival direction flag to indicate a direction in which the search segment arrives at the grid are provided. With this provision, the wiring processing method comprises a forward search processing step that, when the available flag indicates an available state and the arrival flag indicates a non-arrival state of the search segment as for an adjoining grid next to the grid at which the arrival state flag indicates an arrival of the search segment, executes in parallel an adjoining grid flag processing procedure to set the arrival state flag at the adjoining gird to the arrival state of the search segment and to make the arrival direction flag at the adjoining grid to indicate a search direction of the search segment, and further repeats the adjoining grid flag processing procedure as to each of the search segments until the grid requiring the arrival state flag to indicate the arrival state of the search segment comes into nonexistence. The wiring processing method further comprises a backward search processing step for searching, after the forward search processing step, a wiring path backward from a desired grid in compliance with the arrival direction flag. 
     Therefore, in the wiring processing method of the invention, the parallel processing of the foregoing adjoining grid flag processing procedure can increase the speed of the operation in the forward search processing step, thus significantly reducing time for searching the wiring paths. 
     According to another aspect of the invention relating to the wiring processing method, in determining a wiring path of a wiring on a circuit board, a wiring area is in advance divided into grids by a unit of a minimum pitch of the wiring and an arrival direction flag to indicate a direction in which a search segment arrives at a grid is provided. The wiring processing method further comprises: a forward search processing step for searching each of the grids forward, while indicating a plurality of search directions of the search segments on the arrival direction flag; a backward search processing step for searching, after the forward search processing step, a plurality of wiring paths backward from a desired grid in compliance with the arrival direction flag; and an optimum wiring path determining step for determining an optimum wiring path out of a plurality of wiring paths obtained by the backward search processing step. 
     Accordingly, in the wiring processing method of the invention, a plurality of search directions are indicated on the arrival direction flag as for each of the grids, and thereby a plurality of wiring paths can be searched and an optimum wiring path can be selected therefrom. Therefore, it is possible to enhance quality of the wiring while minimizing a wiring length. 
     According to another aspect of the invention, the wiring processing method is provided with: a circuit layout determining step for determining a layout of circuits on a circuit board; and a wiring congestion degree evaluating step for evaluating, after the circuit layout determining step determines the layout of the circuits, a wiring congestion degree of a wiring from the (L−G)/L, in which L is a total wiring length of a wiring to connect the circuits, G is a number of dots used for the wiring. 
     Accordingly, in the wiring processing method of the invention, the wiring congestion degree of a circuit can be estimated for a wiring possibility at the finishing stage of a layout of a circuit before executing the wiring. Therefore, the estimation and evaluation of the wiring possibility becomes possible at an early stage, which is requested as wiring objectives become increasingly big. 
     The wiring processing equipment of the invention is provided with: a segment dividing processor for dividing a wiring connecting between two receivers of a clock net on a clock distributing circuit of a clock synchronous circuit into three or more segments through setting two or more branch points; an equal delay branch segment determining processor for comparing a first delay time from one branch point on one end of the segment obtained by the segment dividing processor to one receiver of the two receivers with a second delay time from the one branch point to the other receiver of the two receivers, and comparing a third delay time from the other branch point on the other end of the segment to the one receiver of the two receivers with a fourth delay time from the other branch point to the other receiver of the two receivers, and determining a segment in which a magnitude of the first delay time against the second delay time and a magnitude of the third delay time against the fourth delay time are inverted as an equal delay branch segment where an equal delay branch point exists; and an equal delay branch point determining processor for determining an equal delay branch point in the equal delay branch segment determined by the equal delay branch segment determining processor. 
     Accordingly, in the wiring processing equipment of the invention, the equal delay branch point can accurately be obtained taking into account that a resistance and capacitance for a unit grid on the wiring are not equal independently of the positions. Therefore, the clock skew being a difference of a clock propagation delay in the clock synchronous circuit can be reduced. 
     According to another aspect of the invention, the wiring processing equipment is provided with: a segment dividing processor for dividing a wiring on a clock distributing circuit of a clock synchronous circuit into three or more segments through setting two or more branch points; a propagation delay time determining processor for obtaining a propagation delay time of the wiring in which a delay time of each of the segments obtained by the segment dividing processor is taken into account; and a wiring length adjusting processor for comparing a propagation delay time of the wiring obtained by the propagation delay time determining processor with a preset time, and on the basis of the comparison result, adjusting a wiring length for each of the segments. 
     Accordingly, in the aforementioned wiring equipment of the invention, a delay time to each of the receivers can be made equal taking an external clock delay time into account, thereby reducing the clock skew being a difference of a clock propagation delay time in the clock synchronous circuit. 
     According to another aspect of the invention, the wiring processing equipment is provided with: a first segment dividing processor for dividing a wiring connecting between two receivers of a clock net on a clock distributing circuit of a clock synchronous circuit into three or more segments through setting two or more branch points; an equal delay branch segment determining processor for comparing a first delay time from one branch point on one end of the segment obtained by the first segment dividing processor to one receiver of the two receivers with a second delay time from the one branch point to the other receiver of the two receivers, comparing a third delay time from the other branch point on the other end of the segment to the one receiver of the two receivers with a fourth delay time from the other branch point to the other receiver of the two receivers, and determining a segment in which a magnitude of the first delay time against the second delay time and a magnitude of the third delay time against the fourth delay time are inverted as an equal delay branch segment where an equal delay branch point exists; an equal delay branch point determining processor for determining an equal delay branch point in the equal delay branch segment determined by the equal delay branch segment determining processor; a delay time determining processor for obtaining a fifth delay time from the equal delay branch point obtained by the equal delay branch point determining processor to each of the receivers; a second segment dividing processor for setting two or more branch points on a wiring from the equal delay branch point through an external clock source gate and dividing the wiring into three or more segments; a propagation delay time determining processor for obtaining a propagation delay time of the wiring in which the delay time of each of the segments obtained by the second segment dividing processor is taken into account; and a wiring length adjusting processor for comparing the sum of the fifth delay time from the equal delay branch point to each of the receivers obtained by the delay time determining processor and the propagation delay time of the wiring obtained by the propagation delay time determining processor with a preset time, and on the basis of the comparison result, adjusting a wiring length for each segment. 
     Accordingly, in the wiring processing equipment of the invention, the equal delay branch point can accurately be obtained taking into account that a resistance and capacitance for a unit grid on the wiring are not equal independently of the positions, and a delay time to each of the receivers can be made equal taking an external clock delay time into account. Therefore, the clock skew being a difference of a clock propagation delay time in the clock synchronous circuit can effectively be reduced. 
     According to another aspect of the invention, the wiring processing equipment is provided with: a forward searching processor that, as for an adjoining grid next to a grid at which an arrival state flag for indicating an arrival of a search segment at the grid obtained by dividing a wiring area into grids by a unit of a minimum pitch of a wiring on a circuit board indicates an arrival of the search segment, when an available flag for indicating whether a grid is available for a wiring or not indicates an available state and the arrival state flag indicates a non-arrival state of the search segment, executes in parallel an adjoining grid flag processing procedure that sets the arrival state flag at the adjoining gird to the arrival state of the search segment and makes an arrival direction flag for indicating an arrival direction of a search segment at the adjoining grid to indicate a search direction thereof, and further repeats the adjoining grid flag processing procedure as to each of the search segments until the grid requiring the arrival state flag to indicate the arrival state of the search segment comes into nonexistence; and a backward searching processor for searching backward, after the forward search processing finishes, a wiring path backward from a desired grid in compliance with the arrival direction flag. 
     Accordingly, the operation in the foregoing forward search processing procedure can be performed in an increased speed by the parallel processing, thus significantly reducing time for searching the wiring paths. 
     According to another aspect of the invention, the wiring processing equipment is provided with: a forward searching processor for searching forward each grid obtained by dividing a wiring area into grids by a unit of a minimum pitch of a wiring on a circuit board, while indicating a plurality of search directions of the search segments on an arrival direction flag for indicating a direction in which a search segment arrives at the grid; a backward searching processor for searching, after the forward search processing, a plurality of wiring paths backward from a desired grid in compliance with the arrival direction flag; and an optimum wiring path determining processor for determining an optimum wiring path out of a plurality of wiring paths obtained by the backward searching processor. 
     Accordingly, in the wiring processing equipment of the invention, a plurality of wiring paths can be searched and an optimum wiring path can be selected therefrom, thus enhancing quality of the wiring while minimizing a wiring length. 
     According to another aspect of the invention, the wiring processing equipment is provided with: a circuit layout determining processor for determining a layout of circuits on a circuit board; and a wiring congestion degree evaluating processor for evaluating, after the circuit layout determining processor determines a layout of the circuits, a wiring congestion degree of a wiring from the (L−G)/L, in which L is a total wiring length of the wiring to connect the circuits, G is a number of dots used for the wiring. 
     Accordingly, in the wiring processing equipment of the invention, the wiring congestion degree of a circuit can be estimated for a wiring possibility at the finishing stage of a layout of a circuit before executing the wiring. Therefore, the estimation and evaluation of the wiring possibility becomes possible at an early stage, which is requested as wiring objectives become increasingly big. 
     The recording medium for a wiring processing program according to the invention is characterized in that a wiring processing program is stored, whereby a computer executes: a segment dividing procedure for dividing a wiring connecting between two receivers of a clock net on a clock distributing circuit of a clock synchronous circuit into three or more segments through setting two or more branch points; an equal delay branch segment determining procedure for comparing a first delay time from one branch point on one end of the segment obtained by the segment dividing procedure to one receiver of the two receivers with a second delay time from the one branch point to the other receiver of the two receivers, and comparing a third delay time from the other branch point on the other end of the segment to the one receiver of the two receivers with a fourth delay time from the other branch point to the other receiver of the two receivers, and determining a segment in which a magnitude of the first delay time against the second delay time and a magnitude of the third delay time against the fourth delay time are inverted as an equal delay branch segment where an equal delay branch point exists; and an equal delay branch point determining procedure for determining an equal delay branch point in the equal delay branch segment determined by the equal delay branch segment determining procedure. 
     Accordingly, in the recording medium for a wiring processing program of the invention, the equal delay branch point can accurately be determined taking into account that a resistance and capacitance for a unit grid on the wiring are not equal independently of the positions. Therefore, the clock skew being a difference of a clock propagation delay in the clock synchronous circuit can be reduced. 
     According to another aspect of the invention, the recording medium for a wiring processing program is characterized in that a wiring processing program is stored, whereby a computer executes: a segment dividing procedure for dividing a wiring on a clock distributing circuit of a clock synchronous circuit into three or more segments through setting two or more branch points; a propagation delay time determining procedure for obtaining a propagation delay time of the wiring in which a delay time of each of the segments obtained by the segment branch procedure is taken into account; and a wiring length adjusting procedure for comparing a propagation delay time of the wiring obtained by the propagation delay time determining procedure with a preset time, and on the basis of the comparison result, adjusting a wiring length for each of the segments. 
     Accordingly, in the recording medium for a wiring processing program of the invention, a delay time to each of the receivers can be made equal taking an external clock delay time into account, thereby reducing the clock skew being a difference of a clock propagation delay time in the clock synchronous circuit. 
     According to another aspect of the invention, the recording medium for a wiring processing program is characterized in that a wiring processing program is stored, whereby a computer executes: a first segment dividing procedure for dividing a wiring connecting between two receivers of a clock net on a clock distributing circuit of a clock synchronous circuit into three or more segments through setting two or more branch points; an equal delay branch segment determining procedure for comparing a first delay time from one branch point on one end of the segment obtained by the first segment dividing procedure to one receiver of the two receivers with a second delay time from the one branch point to the other receiver of the two receivers, comparing a third delay time from the other branch point on the other end of the segment to the one receiver of the two receivers with a fourth delay time from the other branch point to the other receiver of the two receivers, and determining a segment in which a magnitude of the first delay time against the second delay time and a magnitude of the third delay time against the fourth delay time are inverted as an equal delay branch segment where an equal delay branch point exists; an equal delay branch point determining procedure for determining an equal delay branch point in the equal delay branch segment determined by the equal delay branch segment determining procedure; a delay time determining procedure for obtaining a fifth delay time from the equal delay branch point obtained by the equal delay branch point determining procedure to each of the receivers; a second segment dividing procedure for setting two or more branch points on a wiring from the equal delay branch point through an external clock source gate and dividing the wiring into three or more segments; a propagation delay time determining procedure for obtaining a propagation delay time of the wiring in which the delay time of each of the segments obtained by the second segment dividing procedure is taken into account; and a wiring length adjusting procedure for comparing the sum of the fifth delay time from the equal delay branch point to each of the receivers obtained by the delay time determining procedure and the propagation delay time of the wiring obtained by the propagation delay time determining procedure with a preset time, and on the basis of the comparison result, adjusting a wiring length for each segment. 
     Accordingly, in the recording medium for a wiring processing program of the invention, the equal delay branch point can accurately be obtained taking into account that a resistance and capacitance for a unit grid on the wiring are not equal independently of the positions, and a delay time to each of the receivers can be made equal taking an external clock delay time into account. Therefore, the clock skew being a difference of a clock propagation delay time in the clock synchronous circuit can effectively be reduced. 
     According to another aspect of the invention, the recording medium for a wiring processing program is characterized in that a wiring processing program is stored, whereby a computer executes: a forward searching procedure that, as for an adjoining grid next to a grid at which an arrival state flag for indicating an arrival of a search segment at the grid obtained by dividing a wiring area into grids by a unit of a minimum pitch of a wiring on a circuit board indicates an arrival of the search segment, when an available flag for indicating whether a grid is available for a wiring or not indicates an available state and the arrival state flag indicates a non-arrival state of the search segment, executes in parallel an adjoining grid flag procedure that sets the arrival state flag at the adjoining gird to the arrival state of the search segment and makes an arrival direction flag for indicating an arrival direction of a search segment at the adjoining grid to indicate a search direction thereof, and further repeats the adjoining grid flag processing procedure as to each of the search segments until the grid requiring the arrival state flag to indicate the arrival state of the search segment comes into nonexistence; and a backward searching procedure for searching, after the forward searching procedure finishes, a wiring path backward from a desired grid in compliance with the arrival direction flag. 
     Accordingly, in the recording medium for a wiring processing program of the invention, the operation in the forward searching procedure can be performed in an increased speed by the parallel processing, thus significantly reducing time for searching the wiring paths. 
     According to another aspect of the invention, the recording medium for a wiring processing program is characterized in that a wiring processing program is stored, whereby a computer executes: a forward searching procedure for searching forward each grid obtained by dividing a wiring area into grids by a unit of a minimum pitch of a wiring on a circuit board, while indicating a plurality of search directions of the search segments on an arrival direction flag for indicating a direction in which a search segment arrives at the grid; a backward searching procedure for searching, after the forward searching procedure, a plurality of wiring paths backward from a desired grid in compliance with the arrival direction flag; and an optimum wiring path determining procedure for determining an optimum wiring path out of a plurality of wiring paths obtained by the backward searching procedure. 
     Accordingly, in the recording medium for a wiring processing program of the invention, a plurality of wiring paths can be searched and an optimum wiring path can be selected therefrom, thus enhancing quality of the wiring while minimizing a wiring length. 
     According to another aspect of the invention, the recording medium for a wiring processing program is characterized in that a wiring processing program is stored, whereby a computer executes a wiring congestion degree evaluating procedure for evaluating a wiring congestion degree of a wiring from the (L−G )/L, in which L is a total wiring length of a wiring on a circuit board, G is a number of dots used for the wiring. 
     Accordingly, in the recording medium for a wiring processing program of the invention, the wiring congestion degree of a circuit can be estimated for a wiring possibility at the finishing stage of a layout of a circuit before executing the wiring. Therefore, the estimation and evaluation of the wiring possibility becomes possible at an early stage, which is requested as wiring objectives become increasingly big, presenting an advantage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be fully understood from the detailed description given below and from the accompanying drawings of the preferred embodiments of the invention, which, however, should not be taken to limit the specific embodiment, but are for explanation and understanding, in which: 
     FIG. 1 is a block diagram showing a construction of an interactive circuit designing equipment relating to one embodiment of the invention; 
     FIG. 2 is an illustration showing a total construction of the interactive circuit designing equipment relating to the embodiment of the invention; 
     FIG. 3 is an illustration of a model for a clock tree with a buffer in the first mode of the wiring processing method for reducing a clock skew according to the invention; 
     FIG. 4 is an illustration showing a major part of a construction of a clock tree with a buffer in the first mode of the wiring processing method for reducing the clock skew according to the invention; 
     FIGS. 5 and 6 are illustrations typically showing a construction of a clock tree of a clock net on a clock distributing circuit in the first mode of the wiring processing method for reducing the clock skew according to the invention; 
     FIG. 7 is a flow chart for explaining the first mode of the wiring processing method for reducing the clock skew according to the invention; 
     FIG. 8 is a functional block diagram for explaining the first mode of the wiring processing equipment for reducing the clock skew according to the invention; 
     FIGS. 9 and 10 are illustrations typically showing a construction of a clock net on a clock distributing circuit in the second mode of the wiring processing method for reducing the clock skew according to the invention; 
     FIG. 11 is an illustration for explaining a calculation method of y1, y2, and y3 for calculating the admittance; 
     FIG. 12 is an illustration for explaining an external clock delay; 
     FIG. 13 is a flow chart for explaining the second mode of the wiring processing method for reducing the clock skew according to the invention; 
     FIG. 14 is a functional block diagram for explaining the second mode of the wiring processing equipment for reducing the clock skew according to the invention; 
     FIG. 15 is a flow chart for explaining the third mode of the wiring processing method for reducing the clock skew according to the invention; 
     FIG. 16 is a functional block diagram for explaining the third mode of the wiring processing equipment for reducing the clock skew according to the invention; 
     FIG. 17 is an illustration for explaining a construction of an available flag, arrival state flag, and arrival direction flag; 
     FIGS.  18 ( a ) through  18 ( e ), FIGS.  19 ( a ) through  19 ( e ), FIGS.  20 ( a ) through  20 ( e ), FIGS.  21 ( a ) through  21 ( e ), FIGS.  22 ( a ) through  22 ( f ) are illustrations for explaining the first mode of the wiring processing method for determining a wiring path according to the invention; 
     FIG. 23 is a flow chart for explaining the first mode of the wiring processing method for determining a wiring path according to the invention; 
     FIG. 24 is a functional block diagram for explaining the first mode of the wiring processing equipment for determining a wiring path according to the invention; 
     FIGS.  25 ( a ),  25 ( b ), FIGS.  26 ( a ) and  26 ( b ) are illustrations for explaining the second mode of the wiring processing method for determining a wiring path according to the invention; 
     FIG. 27 is a flow chart for explaining the second mode of the wiring processing method for determining a wiring path according to the invention; 
     FIG. 28 is a functional block diagram for explaining the second mode of the wiring processing equipment for determining a wiring path according to the invention; 
     FIG. 29 is an illustration for explaining the third mode of the wiring processing method for determining a wiring path according to the invention; 
     FIG. 30 is a flow chart for explaining the third mode of the wiring processing method for determining a wiring path according to the invention; 
     FIG. 31 is a functional block diagram for explaining the third mode of the wiring processing equipment for determining a wiring path according to the invention; 
     FIG. 32 is an illustration of a model for a clock tree with a buffer; 
     FIG. 33 is an illustration showing a major part of a construction of a clock tree with a buffer; 
     FIG. 34 is an illustration showing a construction of a clock tree consisting of two sub-clock trees; 
     FIG. 35 is an illustration for explaining a method for searching a wiring path in an automatic wiring process; and 
     FIG. 36 is an illustration for explaining the method for searching a wiring path in the automatic wiring process. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Preferred embodiment of the present invention will hereafter be described in detail with reference to the accompanying drawings. 
     (a) Description on the Construction of an Interactive Circuit Designing Equipment relating to one Embodiment of the Invention 
     FIG. 1 is a block diagram showing a construction of an interactive circuit designing equipment being a wiring processing equipment relating to one embodiment of the invention. 
     In an interactive circuit designing equipment  1  shown in FIG. 1, numeral  3  is a display unit for displaying designing processes of various circuits and wiring paths etc. to connect circuits,  4  is a display control unit for controlling the display mode,  7  is an input device such as a key board and a mouse for a designer, referring to the data displayed on the display unit  3 , to enter an information responsive to the displayed data. 
       5  is an external file write unit that writes into an external file  5 A the wiring path drawings, etc. displayed on the display unit  3  by the display control unit  4  in accordance with the instruction from the input device  7 . 
       6  is a printing device that prints out on a specific printing paper the wiring path drawings, etc. displayed on the display unit  3  by the display control unit  4  in accordance with the instruction from the input device  7 . 
       8  is a hard disk in which all the data (logic circuit data, circuit layout data, etc.) used in designing circuits by the interactive circuit designing equipment  1  are stored and a wiring processing program (software) for the interactive circuit designing equipment  1  to execute the procedure for various wiring processing methods detailed later in (b) is stored, and in this embodiment, it functions as the recording medium for the wiring processing program. 
       2  is a CPU whereby each of the parts constituting the interactive circuit designing equipment  1  is administratively controlled. 
     Further, the function of the display control unit  4  is concretely achieved when the CPU  2  executes a program(software)stored in the hard disk  8 ; in FIG. 1, the display control unit  4  is illustrated in a block in order to define the function. 
     Accordingly, the interactive circuit designing equipment  1  relating to this embodiment can be embodied by a general computer system (refer to FIG. 2) that comprises the CPU  2 , display unit  3 , external file write unit  5 , printing device  6 , input device  7 , hard disk  8 , etc. In FIG. 2, numeral  9  is a computer main frame. 
     (b) Description on the Wiring Processing Method by the Interactive Circuit Designing Equipment relating to one Embodiment of the Invention 
     (b1) Description on the first Mode of the Wiring Processing Method for Reducing the Clock Skew 
     The first mode of the wiring processing method for the interactive circuit designing equipment  1  relating to one embodiment of the invention will be described, whereby the clock skew, namely, the difference of clock propagation delay time in a clock synchronous circuit can be reduced. 
     For explaining the first mode, FIGS. 5 and 6 illustrate a construction of a clock tree of a clock net on a clock distributing circuit of a clock synchronous circuit. 
     The clock tree  30  comprises, as shown in FIG. 6, a sub-clock tree consisting of a clock receiver(receiving circuit)  31  and a wiring  37  and another sub-clock tree consisting of a clock receiver(receiving circuit)  34  and a wiring  40 , which are connected at an equal delay branch point (tapping point) x where the sub-clock trees have an equal delay. 
     Thus, in the clock tree  30 , a clock driver (clock generator) not illustrated in FIG. 6 supplies a clock to the receiver  31  and  34  through the equal delay branch point x. 
     Here, the receiver  31  is composed of a flip-flop circuit (time constant t A )  32  and a capacitor (capacitance C A )  33 , and the receiver  34  is composed of a flip-flop circuit (time constant t B )  35  and a capacitor (capacitance C B )  36 . 
     The wiring  37  comprises a plurality of the Π type RC circuits (namely, segments  43 ) each of which consists of one resistor (resistance r 1 )  38  and two capacitors (capacitance c 1 /2)  39 , from a reason described later. 
     Further, in the same manner as the wiring  37 , the wiring  40  also comprises a plurality of the Π type RC circuits (namely, segments  43 ) consisting of one resistor (resistance r 2 )  41  and two capacitors (capacitance c 2 /2)  42 . 
     In FIG. 6, the Π type RC circuit (segment  43 ) is illustrated only for one circuit each for the wiring  37  and  40 , and the other segments are omitted. 
     Further in FIG. 5, the wiring  37  and  40  are omitted, however, a plurality of the segments in the wiring between the receiver  31  and  34  are illustrated with the symbol  43  (half-tone dot meshing in FIG.  5 ). 
     Incidentally, the equal delay branch point x shown in FIG. 6 is an input point of the clock from the driver (clock generator) not illustrated in FIG. 6, as described above. 
     In the clock tree  30  shown in FIG. 6, the clock skew by the two sub-clock trees of the clock tree  30  varies depending on the position of the equal delay branch point x. Therefore, the position of the equal delay branch point x has to be set very accurately to reduce the clock skew in the clock tree  30 . 
     The method for determining an equal delay branch point x on a wiring between two sub-clock trees will now be described. 
     The wiring processing method for determining the equal delay branch point x in the present mode comprises, as shown in FIG. 7, a segment dividing step (step S 1 ), equal delay branch segment determining step (step S 2 ), equal delay branch point determining step (step S 3 ). 
     The segment dividing step (step S 1 ) sets, as shown in FIG. 5, at least two or more dividing points (branch points) P 1 , . . . P n+1  on the wiring between the receiver  31  and  34  and divides the wiring into at least three or more segments  43 . 
     Here, the reason to divide the wiring (the wiring  37  and  40  shown in FIG. 6) between the receiver  31  and  34  into a plurality of segments  43  will be described. 
     First, a close look at one sub-clock tree is requested. 
     FIG. 3 illustrates a model for a clock tree with a buffer, and as shown in this figure, the buffer built-in clock tree  10  comprises a clock signal generator (clock source)  11  as the driver, a clock receiver (latch)  13  as the receiver, and a buffer  12  through which the former two are connected. 
     Here, the clock source  11  is connected to the buffer  12  through a wire  14  and the buffer  12  is connected to the latch  13  through a wire  15 . 
     This buffer built-in clock tree  10  has a configuration as shown in FIG. 4 in detail. 
     The clock source  11  has a resistor (resistance r s )  16 ; the buffer  12  has a delay circuit (internal delay time d b )  19 , a resistor (resistance r b )  17 , and a capacitor (capacitance c b )  18 ; the latch  13  has a capacitor (capacitance c 1 )  20 . 
     The delay time from the clock source  11  to the latch  13  includes, as already described by means of FIG. 33, the delay time due to the wiring resistors and capacitors of the wire  14  and  15 , and the internal delay time d b  by the delay circuit  19  of the buffer  12 . 
     The wiring resistor has become a problem as cannot be ignored, since the size of transistors and the cross-sectional area of wirings have decreased owing to the recent progress in the semiconductor microstructuring technique. 
     Accordingly, it has become necessary to deal with the wire  14  and  15  as a distributed constant circuit from accuracy for estimating the delay time. 
     In the buffer built-in clock tree  100  as already shown in FIG. 33, as a concentrated constant circuit being a typical form of the distributed constant circuit, the wire  104  and  105  each have been evaluated by means of one Π type RC circuit (single Π type RC model). In the present mode, from the consideration that the resistance and capacitance for unit grid in the wire  14  and  15  are not equal independently of the positions on the wiring, the delay time is evaluated by means of a plurality of the Π type RC circuits given by dividing the wire  14  and  15  into a plurality of segments  43 . 
     The wire  14  comprises a plurality of the Π type RC circuits  21  (namely, segments) each of which consists of one resistor (resistance r 1 , . . . , r k )  21 A and two capacitors [capacitance (c 1 /2), . . . , (c k /2)]  21 B, as shown in FIG.  4 . 
     The wire  15  also comprises a plurality of the Π type RC circuits  22  (namely, segments consisting of one resistor (resistance r m , . . . , r a )  22 A and two capacitors [capacitance (c m /2), . . . , (c n /2)]  22 B. 
     In the segment dividing step (step S 1 ), the wiring between the receiver  31  and  34  shown in FIG. 5 is divided into the segments  43  by the dividing points P 1 , . . . , P n+1  with the conditions mentioned below. 
     (1) a physical branch point on a wiring connecting between the receiver  31  and  34 . 
     Here, the physical branch point is a point at which a wiring layer changes, for example, in FIG. 5, the dividing point P 4  and P 7  are equivalent to the physical point. 
     (2) a point at which the impedance for a unit length of the wiring connecting between the receiver  31  and  34  changes. 
     Here, the impedance for a unit length of the wiring changes where the wiring layer changes, however, it changes even where the wiring layer does not change (for example, where a power supply is disposed in the underlayer of the wiring). Therefore, it is effective to divide the wiring at such a point that the impedance for a unit length of the wiring changes. Here, the impedance is resistance or capacitance. 
     (3) a point at which the length of a segment  43  exceeds a predetermined length s (s: optional constant). 
     Here, the length s is a length obtained from experience. 
     The segments  43  are divided at the dividing points P 1 , . . . , P n+1  which correspond to the aforementioned (1) through (3), each of which is evaluated by means of one Π type RC model. 
     The equal delay branch segment determining step (step S 2 ) determines the segment  43  containing the equal delay branch point x out of the segments  43  obtained by the segment dividing step (step S 1 ) as the equal delay branch segment. 
     Concretely, in the equal delay branch segment determining step (step S 2 ), the delay time from one dividing point P k  on one end of the segments  43  to one receiver of the foregoing two receivers  31 ,  34  (in FIG. 5, the receiver  31  connected to a gate A on the subsequent stage) is obtained as a first delay time [Delay (P k  → A)], and the delay time from one dividing point P k  to the other receiver of the foregoing two receivers  31 ,  34  (in FIG. 5, the receiver  34  connected to a gate B on the subsequent stage) is obtained as a second delay time [Delay (P k  → B)]. 
     And, the first delay time [Delay (P k  → A)] and the second delay time [Delay (P k  → B)] are compared. 
     Furthermore, the delay time from the other dividing point P k+1  on the other end of the segments  43  to one receiver of the foregoing two receivers  31 ,  34  is obtained as a third delay time [Delay (P k+1  → A)], and the delay time from the other dividing point Pk+1 to the other receiver of the foregoing two receivers  31 ,  34  is obtained as a fourth delay time [Delay (P k+1  → B)]. 
     And, the third delay time [Delay (P k+1  → A)] and the fourth delay time [Delay (P k+1  → B)] are compared. 
     If there is a segment in which the magnitude of the first delay time [Delay (P k  → A)] against the second delay time [Delay (P k  → B)] and the magnitude of the third delay time [Delay (P k+1  → A)] against the fourth delay time [Delay (P k+1  → 60  B)] are inverted, the segment is determined as an equal delay branch segment where the equal delay branch point “x” exists. 
     Namely, the equal delay branch segment determining step (step S 2 ) is to find out the dividing points P k , P k+1  which satisfy 
     
       
         Delay ( P   k    → A )≦Delay ( P   k    → B )  
       
     
     
       
         Delay ( P   k+1    → A )≧Delay ( P   k+1    → B ) 
       
     
     by means of dichotomy, out of the dividing points P 1  through P n+1 ; the equal delay branch segment is a segment (segment P k  P k+1 ) between the dividing point P k  and P k+1 . 
     Here, the first delay time [Delay (P k  → A)], the second delay time [Delay (P k  → B)], the third delay time [Delay (P k+1  → A)], and the fourth delay time [Delay (P k+1  → B)] are obtained from the following equations.          Delay                   (       P   k     →   A     )       =         ∑     i   =   1       k   -   1            [       r   i          (         ∑     j   =   1     i          c   j       -       c   i     /   2     +     C   A       )       ]       +     t   A                 Delay                   (       P   k     →   B     )       =         ∑     i   =   k     n          [       r   i          (         ∑     j   =   i     n          c   j       -       c   i     /   2     +     C   B       )       ]       +     t   B                 Delay                   (       P     k   +   1       →   A     )       =         ∑     i   =   1     k          [       r   i          (         ∑     j   =   1     i          c   j       -       c   i     /   2     +     C   A       )       ]       +     t   A                 Delay                   (       P     k   +   1       →   B     )       =         ∑     i   =     k   +   1       n          [       r   i          (         ∑     j   =   1     n          c   j       -       c   i     /   2     +     C   B       )       ]       +     t   B                       
     Here, 
     r i : resistance across a segment 
     r k : resistance of a resistor at an equal delay branch segment 
     c j : capacitance at a segment 
     c k : capacitance of a capacitor at an equal delay branch segment 
     C A : capacitance at the one receiver 
     C B : capacitance at the other receiver 
     t A : delay time by the one receiver 
     t B : delay time by the other receiver 
     n+1: total number of the dividing points 
     k: first number of the dividing points forming the equal delay branch segment. 
     Furthermore, the equal delay branch point determining step (step S 3 ) determines the equal delay branch point x in an equal delay branch segment given by the equal delay branch segment determining step (step S 2 ). 
     In this equal delay branch point determining step (step S 3 ), as shown in FIG. 6, t A  and C A  are calculated regarding the segment from the dividing point P k  to the gate A as a sub-clock tree A, and t B  and C B  are calculated regarding the segment from the dividing point P k+1  to the gate B as a sub-clock tree B. 
     Here, 
     C A : total capacitance from the dividing point P k  to the gate A 
     C B : total capacitance from the dividing point P k+1  to the gate B 
     t A : delay by the wiring from the dividing point P k  to the gate A 
     t B : delay by the wiring from the dividing point P k+1  to the gate B 
     In the segment from the dividing point P k  to P k+1 , since the capacitance and resistance for a unit length are equal, the equal delay branch point x can be determined by the following equation, in the same method as the conventional technique from IBM. 
     
       
           x=[t   B   −t   A )+α L ( C   B   +βL/ 2)]/[α L (β L+C   A   +C   B )] 
       
     
     here, 
     L: wiring length between the two receivers 
     α: resistance for a unit length of the wiring 
     β: capacitance for a unit length of the wiring. 
     Here, the wiring processing method formed of the foregoing steps (step S 1  through S 3 ) is executed on the basis that the CPU  2  (refer to FIG. 1) of the interactive circuit designing equipment  1  has the functions equivalent to a segment dividing processor A 1 , equal delay branch segment determining processor A 2 , and equal delay branch point determining processor A 3 , as shown in FIG.  8 . 
     The segment dividing processor A 1  divides the wiring connecting between the two receivers  31 ,  34  of the clock net on the clock distributing circuit of the clock synchronous circuit into at least three or more segments  43  through setting at least two or more dividing points P 1 , . . . , P n+1  on the wiring. The equal delay branch segment determining processor A 2  determines the segment  43  containing the equal delay branch point x out of the segments  43  picked up by the segment dividing processor A 1  as the equal delay branch segment. 
     Concretely, the equal delay branch segment determining processor A 2  compares the first delay time [Delay (P k  → A)] from one dividing point P k  on one end of the segment  43  to one receiver of the foregoing two receivers  31 ,  34  (in FIG. 5, the receiver  31  connected to a gate A on the subsequent stage) with the second delay time [Delay (P k  → B)] from the one dividing point P k  to the other receiver of the foregoing two receivers  31 ,  34  (in FIG. 5, the receiver  34  connected to a gate B on the subsequent stage), and compares the third delay time [Delay (P k+1  → A)] from the other dividing point P k+1  on the other end of the segment  43  to the one receiver of the foregoing two receivers  31 ,  34  with the fourth delay time [Delay (P k+1  → B)] from the other dividing point P k+1  to the other receiver of the foregoing two receivers  31 ,  34 . Further, the equal delay branch segment determining processor A 2  determines that the segment  43  in which the magnitude of the first delay time [Delay (P k  → A)] against the second delay time [Delay (P k  → B)] and the magnitude of the third delay time [Delay (P k+1  → A)] against the fourth delay time [Delay (P k+1  → B)] are inverted as the equal delay branch segment where the equal delay branch point x exists. 
     Furthermore, the equal delay branch point determining processor A 3  determines an equal delay branch point x in the equal delay branch segment given by the equal delay branch segment determining processor A 2 . 
     And in practice, such functions as being equivalent to these processors A 1  through A 3  can be embodied by a wiring processing program, stored in the hard disk  8 , whereby the CPU  2  of the interactive circuit designing equipment  1  executes the procedures described later. 
     Here, the wiring processing program in the present mode is a software whereby the interactive circuit designing equipment  1  executes a segment dividing procedure, equal delay branch segment determining procedure, and equal delay branch point determining procedure. 
     The segment dividing procedure sets at least two or more dividing points P 1 , . . . , P n+1  on the wiring between the receiver  31  and  34  of the clock net on the clock distributing circuit of the clock synchronous circuit and divides the wiring into at least three or more segments  43 . 
     The equal delay branch segment determining procedure determines the segment  43  containing the equal delay branch point “x” out of the segments  43  obtained by the segment dividing procedure as the equal delay branch segment. 
     Concretely, the equal delay branch segment determining procedure compares the first delay time [Delay (P k  → A)] from one dividing point P k  on one end of the segment  43  to one receiver of the foregoing two receivers  31 ,  34  (in FIG. 5, the receiver  31  connected to a gate A on the subsequent stage) with the second delay time [Delay (P k  → B)] from the one dividing point P k  to the other receiver of the foregoing two receivers  31 ,  34  (in FIG. 5, the receiver  34  connected to a gate B on the subsequent stage), and compares the third delay time [Delay (P k+1  → A)] from the other dividing point P k+1  on the other end of the segments  43  to the one receiver of the foregoing two receivers  31 ,  34  with the fourth delay time [Delay (P k+1  → B] from the other dividing point P k+1  to the other receiver of the foregoing two receivers  31 ,  34 . Further, the equal delay branch segment determining procedure determines the segment in which the magnitude of the first delay time [Delay (P k  → A)] against the second delay time [Delay (P k  → B)] and the magnitude of the third delay time [Delay (P k+1  → A)] against the fourth delay time [Delay (P k+1  → B)] are inverted as the equal delay branch segment where the equal delay branch point “x” exists. 
     Furthermore, the equal delay branch point determining procedure determines an equal delay branch point x in the equal delay branch segment given by the equal delay branch segment determining procedure. 
     Based on the foregoing construction, in the interactive circuit designing equipment  1  relating to the embodiment of the invention, the following operation determines the equal delay branch point x in the wiring between the two sub-clock trees. 
     In the interactive circuit designing equipment  1 , the segment dividing step (step S 1 ) sets at least two or more dividing points P 1 , . . . , P n+1  on the wiring between the receiver  31  and  34  by, and divides the wiring into at least three or more segments  43 . 
     Next, the equal delay branch segment determining step (step S 2 ) determines, as described above, the first through the fourth delay time [Delay (P k  → A), Delay (P k  → B), Delay (P k+1  → A), Delay (P k+1  → B)] out of the segments  43  obtained by the segment dividing step (Step S 1 ); and compares the first delay time [Delay (P k  → A)] with the second delay time [Delay (P k  → B)], and the third delay time [Delay (P k+1  → A)] with the fourth delay time [Delay (P k+1  → B)]. 
     The equal delay branch segment determining step (step S 2 ) further determines the segment in which the magnitude of the first delay time [Delay (P k  → A)] against the second delay time [Delay (P k  → B)] and the magnitude of the third delay time [Delay (P k+1  → A)] against the fourth delay time [Delay (P k+1  → B)] are inverted as the equal delay branch segment where the equal delay branch point “x” exists. 
     Furthermore, the equal delay branch point determining step (step S 3 ) determines the equal delay branch point “x” in the equal delay branch segment obtained by the equal delay branch segment determining step (step S 2 ). 
     According to the first mode of the wiring processing method for reducing the clock skew in the interactive circuit designing equipment  1  relating to the embodiment of the invention, in the clock net on the clock distributing circuit of the clock synchronous circuit, the wiring between the receiver  31  and  34  is divided into a plurality of segments  43  to evaluate the delay time by means of a plurality of single Π type RC circuits. Thereby, it is possible to take into account that the resistance and capacitance for a unit grid are not equal independently of the positions on the wiring, and to determine the equal delay branch point “x” accurately on the wiring between the receiver  31  and  34 . 
     Further, the dividing points P 1 , . . . , P n+1  are determined from (1) a physical branch point on a wiring connecting between the receiver  31  and  34 , (2) a point at which the impedance for a unit length of the wiring connecting between the receiver  31  and  34  changes, or (3) a point at which the length of a segment  43  exceeds a predetermined length s (s: optional constant). Thereby, the dividing points P 1 , . . . , P n+1  can be set so as to match the condition of each of the clock nets, and the equal delay branch point “x” can be determined more precisely. 
     Since it is possible to precisely determine the equal delay branch point in this manner, the delay time from the driver (not illustrated in FIG. 6) to the receiver  31  and  34  can be made equal; thereby, reducing the clock skew in the clock tree  30  on the clock nets. 
     (b2) Description on the second Mode of the Wiring Processing Method for Reducing the Clock Skew 
     Furthermore, the second mode of the wiring processing method for the interactive circuit designing equipment  1  relating to the embodiment of the invention will be described, whereby the clock skew, namely, the difference of clock propagation delay time in a clock synchronous circuit can be reduced. 
     The second mode of the wiring processing method for reducing the clock skew will be described in which the gate delay (extra-source gate delay) increased by applying the driver being the clock generator to a load is considered in determining the equal delay branch point on the wiring between the receivers. Further, the length of the wiring between the equal delay branch point and the driver output point (external clock source gate) can be adjusted to set the delay time from the driver to the receivers to a target value, thereby the clock skew on the clock nets can effectively be reduced. 
     FIG. 9 shows a typical construction of a clock net  44  including a driver (clock generator)  45 A and a clock tree  45 B. 
     Here, the clock net  44  lies on the clock distributing circuit of the clock synchronous circuit, and the clock tree  45 B comprises a plurality of clock trees (refer to FIGS. 5 and 6, reference symbol  30 ). 
     Namely, this FIG. 9 represents a state that a plurality of receivers (refer to FIGS. 5 and 6, reference symbol  31 ,  34 ) have completely been connected to form clock trees and a plurality of the clock trees thus formed have completely been connected each other to form the clock tree  45 B, and then, the equal delay branch point Q (the final equal delay branch point on the wiring between the receivers) and the driver output point P (external clock source gate) are connected by the shortest wiring. 
     In this mode, after the equal delay branch point Q is accurately determined on the clock tree  45 B, the length of the wiring between the equal delay branch point Q and the driver output point P is designed to be adjusted so that the delay time from the driver output point P to each of the receivers in the clock tree  45 B can be set to the predetermined time. 
     The wiring processing method in this mode comprises, as shown in FIG. 13, a first segment dividing step (step S 4 ), equal delay branch segment determining step (step S 5 ), equal delay branch point determining step (step S 6 ), delay time determining step (step S 7 ), second segment dividing step (step S 8 ), propagation delay time determining step (step S 9 ), and wiring length adjusting step (step S 10 ). 
     The first segment dividing step (step S 4 ) sets at least two or more dividing points (branch points) on the wiring (the same as one shown in FIG. 5) between the two receivers in the clock tree  45 B on the clock net  44  and divides the wiring into at least three or more segments. 
     In this mode, in the same manner as the abovementioned, from the consideration that the resistance and capacitance for a unit grid in the wiring are not equal independently of the positions, the delay time is evaluated by means of a plurality of the Π type RC circuits (refer to FIG. 6, reference symbol  43 ) given by dividing the wiring connecting between two receivers in the clock net  44  into a plurality of segments. 
     In FIG. 9, the dividing points and segments in the clock tree  45 B are omitted. 
     The dividing points are determined, in the same manner as the foregoing case, from (1) a physical branch point on a wiring connecting between the receivers, (2) a point at which the impedance for unit length of the wiring connecting between the receivers changes, or (3) a point at which the length of a segment exceeds a predetermined length s (s: optional constant). 
     Further, the equal delay branch segment determining step (step S 5 ) determines the segment containing the equal delay branch point Q out of the segments obtained by the first segment dividing step (step S 4 ) as the equal delay branch segment. 
     Concretely, the equal delay branch segment determining step (step S 5 ) compares, in the same manner as the foregoing case, the first delay time from one dividing point on one end of the segment to one receiver of the foregoing two receivers with the second delay time from the one dividing point to the other receiver of the foregoing two receivers, and compares the third delay time from the other dividing point on the other end of the segment to the one receiver of the foregoing two receivers with the fourth delay time from the other dividing point to the other receiver of the foregoing two receivers. The equal delay branch segment determining step (step S 5 ) further determines the segment in which the magnitude of the first delay time against the second delay time and the magnitude of the third delay time against the fourth delay time are inverted as the equal delay branch segment where the equal delay branch point Q exists. 
     The foregoing first through fourth delay time can be obtained in the same manner as the foregoing case (b1) [refer to Delay (P k  → A), Delay (P k  → B), Delay (P k+1  → A), Delay (P k+1  → B) in the above mentioned]. 
     Furthermore, the equal delay branch point determining step (step S 6 ) determines an equal delay branch point Q in the equal delay branch segment given by the equal delay branch segment determining step (step S 5 ). 
     The equal delay branch point Q can also be obtained in the same manner as the case described in (b1). 
     Further, the delay time determining step (step S 7 ) obtains the fifth delay time t R  from the equal delay branch point Q given by the equal delay branch point determining step (step S 6 ) to each of the receivers. 
     The fifth delay time t R  is a delay time from the equal delay branch point Q in the clock tree  45 B to each of the receivers, as shown in FIG.  10 . 
     Here, the fifth delay time t R  is obtained from the following equation: 
     
       
           t   R   =r   1  ( c   1 /2+ C   A )+ t   A   =α L Q  (β  L Q+C   A )+ t   A   
       
     
     here, 
     L: wiring length between the receivers 
     α: resistance for a unit length of the wiring 
     β: capacitance for a unit length of the wiring. 
     The second segment dividing step (step S 8 ) sets, as shown in FIG. 9, at least two or more dividing points (branch points) P 1 , . . . , P n+1  on the wiring from the equal delay branch point Q through the driver output point P and divides the wiring into at least three or more segments  46 . 
     In this mode, in the same manner as the abovementioned, from the consideration that the resistance and capacitance for a unit grid in the wiring are not equal independently of the positions, the delay time is evaluated by means of a plurality of the Π type RC circuits (refer to FIG. 10) given by dividing the wiring connecting between the equal delay point Q and the driver output point P into a plurality of segments  46 . 
     In the second segment dividing step (step S 8 ), the wiring between the equal delay point Q and the driver output point P is divided into the segments  46  by the dividing points P 1 , . . . , P n+1  with the conditions mentioned below. 
     (1) a point at which the impedance for a unit length of the wiring connecting between the equal delay point Q and the driver output point P changes. 
     Here, the impedance for a unit length of the wiring changes where the wiring layer changes, however, it changes even where the wiring layer does not change. Therefore, it is effective to divide the wiring at such a point that the impedance for a unit length of the wiring changes. Here, the impedance is a resistance or capacitance. 
     (2) a point at which the length of a segment  46  exceeds a predetermined length s (s: optional constant). 
     Here, the length s is a length determined from experience. 
     The segments  46  are divided at the dividing points P 1 , . . . , P n+1  which correspond to the aforementioned) (1) and (2), each of which is evaluated by means of the Π type RC circuit (Π type RC model) consisting of one resistor  48  (resistance Ra 1 , . . . , Ra n ) and two capacitors  47  [capacitance (Ca 1 /2), . . . , (Ca n /2)], as shown in FIG.  10 . 
     The propagation delay time determining step (step S 9 ) obtains a propagation delay time t PQ  of the wiring in which the delay time of each of the segments  46  given by the second segment dividing step (step S 8 ) is taken into account. 
     Here, the propagation delay time t PQ is obtained from the following equation.          t   PQ     =       ∑     i   =   1     n          [     Ra        (         ∑     j   =   i     n          Ca   j       -       Ca   i     /   2     +     C   R       )       ]                       
     n+1: total number of the dividing points 
     The wiring length adjusting step (step S 10 ) compares the delay time [Delay (P → each receiver)] from the driver output point P to each of the receivers with a preset time, and on the basis of the comparison result, adjusts the wiring length for each segment. 
     Here, the delay time [Delay (P → each receiver)] from the driver output point P to each of the receivers is the sum of the fifth delay time t R  from the equal delay branch point Q given by the delay time determining step (step S 7 ) to each of the receivers, the propagation delay time t PQ  of the wiring given by the propagation delay time determining step (step S  9 ), and the external clock delay time (extra-source gate delay) t LOAD  at the driver output point P. 
     Namely, as shown in FIG. 10, assuming that the delay time from the equal delay branch point Q to each of the receivers in the clock tree  45 B is t R  (the fifth delay time) and the total capacitance from the equal delay branch point Q to each of the receivers is C R , the delay time [Delay (P → each receiver)] from the driver output point P to each of the receivers is given by the following equation. 
     
       
         Delay ( P  → each receiver)≈ t   LOAD   +t   PQ   +t   R   
       
     
     Here, the external clock delay time (extra source gate delay) t LOAD  is described with reference to FIG.  12 . In the figure, the delay time T INTERCONNECT delay  delay in the wiring between the driver (SOURCE) and the receiver (LOAD) is given by the following equation: 
     
       
           T   INTERCONNECT delay     T   AC   −T   AB  (0)=[ T   AB ( L )− T   AB (0)]+ T   BC   
       
     
     here, 
     T AB  (0): delay through an unloaded source gate 
     T AB  (L): delay through the same source gate loaded by an interconnect net of length L. 
     And, [T AB  (L)−T AB  (0)] in the foregoing equation represents the external clock delay t LOAD . 
     In the wiring length adjusting step (step S 10 ), y1, y2, and y3 for calculating the admittance viewed from the dividing point P 1  shown in FIGS. 9,  10  are calculated in order to obtain t LOAD  at the dividing point P 1 . 
     Namely, t LOAD  at the dividing point P 1  can be obtained through the calculation that the equations y1, y2, and y3 for calculating the admittance viewed from the dividing point P 1  are calculated and a specific calculation (whose detailed content does not concern this mode) is carried out using these three equations. 
     Namely, t LOAD =F (y1, y2, y3). 
     In this embodiment, the calculation of y1, y2, and y3 for calculating the admittance is performed on the basis of the method mentioned in ‘P. R. O&#39;Brien and T. L. Savarino, “Modeling the Driving-Point Characteristics of Resistive Interconnect for Accurate Delay Estimation”, IEEE Intl. Conference on CAD, pp512-515, 1989’. 
     Here, a general wiring model to obtain y1, y2, and y3 is shown in FIG.  11 . 
     In FIG. 11, numeral  49  is a capacitor,  50  resistor,  51  output pin from the driver or receiver, and P 1 ˜P 9  are dividing points. 
     A calculation method of y1, y2, and y3 for calculating the admittance viewed from the dividing point P 1  will hereafter be described. 
     First, assuming that the Laplace transform expression is y 1  (s), the Laplace transform from the receiver to the driver will be given by the following. 
     
       
           y   8  ( s )= C   A   ·s {right arrow over (→)} y   6  ( s ) {right arrow over (→)}  y   4  ( s )  
       
     
     
       
           y   9  ( s )= C   B   ·s {right arrow over (→)} y   7  ( s ) {right arrow over (→)}  y   5  ( s )  
       
     
     
       
           y   3  ( s )= y   4  ( s )+ y   5  ( s ) {right arrow over (→)}  y   2  ( s )  
       
     
     
       
         {right arrow over (→)}  y   1  ( s ) 
       
     
     The tertiary approximation of y 1  (s) is expressed in the following equation: 
     
       
           y   1  ( s )= y 1· s+y 2· s   2   +y   3   ·s   3 , 
       
     
     and the coefficient y1, y2, and y3 are obtained from this equation. 
     Thus, in the wiring length adjusting step (step S 10 ), the delay time [Delay (P → each receiver)] from the driver output point P calculated by the foregoing equation to each of the receivers is compared with a preset time γ, and on the basis of this comparison, the wiring length between the equal delay branch point Q and the driver output point P can be adjusted for each segment. 
     When the delay time [Delay (P → each receiver)] from the driver output point P to each of the receivers exceeds the preset time γ at the beginning, the layout of the driver  45 A and/or the clock tree  45 B (refer to FIGS. 9 and 10) are relocated before the wiring length between the equal delay branch point Q and the driver output point P is readjusted. 
     Concretely, the relocation or the wiring length adjustment is done in accordance with the following: 
     
       
         if, Delay ( P  → each receiver)&gt;γ: relocation,  
       
     
     
       
         if, Delay ( P  → each receiver)=γ: end of processing,  
       
     
     
       
         if, Delay ( P  → each receiver)&lt;γ: wiring length adjustment. 
       
     
     The adjustment of the wiring length has to be done between the dividing point P 1  and P 2 . Assuming that the shortest wiring length between the dividing point P 1  and P 2  is L LOWER , the resistance α and capacitance β for unit length of the wiring between the dividing point P 1  and P 2  are as follows. 
     
       
         α= Ra   1   /L   LOWER    
       
     
     
       
         β= Ca   1   /L   LOWER   
       
     
     And, in the wiring newly arranged by the adjustment of the wiring length between the dividing point P 1  and P 2 , the length L to satisfy Delay (P → each receiver)=γ lies in L LOWER &lt;L&lt;L UPPER . 
     Here, L UPPER  is the longest permissible wiring length, and in order to obtain L UPPER , a segment of length s [which does not concern the s from the Laplace transform yi (s)] is inserted one by one and at each time of the insertion, y1, y2, and y3 are calculated to obtain t LOAD . 
     LUPPER can be obtained by the following recursive calculation. 
     
       
         
           t 
           0 
           =t 
           PQ 
           +t 
           R  
         
       
     
     
       
           C   0 =Σ i=1   n   Ca   i   +C   R    
       
     
     
       
         
           L 
           0 
           =L 
           LOWER  
         
       
     
     
       
           y 1 0   =y 1  
       
     
     
       
           y 2 0   =y 2  
       
     
     
       
           y 3 0   =y 3  
       
     
     
       
           t   i   =t   i−1   +αs  (β s/ 2+ C   i−1 )  
       
     
     
       
         
           C 
           i 
           =C 
           i−1 
           +βs  
         
       
     
     
       
         
           L 
           i 
           =L 
           i−1 
           +s 
         
       
     
     Here, referring to the literature by the P. R. O&#39;Brien and T. L. Savarino, 
     
       
           y 1 i   =f  ( y 1 i−1 )  
       
     
     
       
           y 2 i   =g  ( y 1 i−1   , y 2 i−1 )  
       
     
     
       
           y 3 i   =h  ( y 1 i−1   , y 2 i−1   , y 3 i−1 ),  
       
     
     
       
         thereby,  
       
     
     
       
           t   LOAD   =F  ( y 1 i   , y 2 i   , y 3 i ). 
       
     
     Here, the value of s·i+L LOWER  when t i +t LOAD &gt;γ is first met is regarded as L UPPER , and the value L i−1  is taken up as a new L LOWER . Here, the s is a natural number, and the number of about 50 is considered as appropriate. 
     Furthermore, while the wiring length L between the dividing point P 1  and P 2  is determined by means of the dichotomy between s·(i−1)+L LOWER  and L UPPER , the delay time [Delay (P→each receiver)] from the driver output point P to each of the receivers is calculated, and thereby the wiring length L with which the delay time becomes equal to the preset value γ is determined. 
     Assuming that the segment of length s is sequentially inserted between the driver output pin  51  and the dividing point P 1  and the calculation is continued until the delay time from the driver output point P (refer to FIGS. 9,  10 ) to each of the receivers exceeds the preset value γ, the segment of length s·i (i: number of repetition) is inserted in total when the delay time under calculation exceeds the preset value γ. 
     Since the wiring length L with which the delay time becomes equal to the preset value γ satisfies the inequality 
     
       
         [ s· ( i− 1)+ L   UPPER   ]&lt;L &lt;( s·i+L   UPPER ), 
       
     
     the wiring length L can be obtained by means of the dichotomy. 
     And, the wiring between the dividing point P 1  and P 2  is removed and the wiring is rearranged with the length L. 
     The wiring processing method formed of the foregoing steps (step S 4  through S 10 ) is executed on the basis that the CPU  2  (refer to FIG. 1) of the interactive circuit designing equipment  1  has the functions equivalent to a first segment dividing processor A 4 , equal delay branch segment determining processor A 5 , equal delay branch point determining processor A 6 , delay time determining processor A 7 , second segment dividing processor A 8 , propagation delay time determining processor A 9 , and wiring length adjusting processor A 10 , as shown in FIG.  14 . 
     The first segment dividing processor A 4  executes to divide the wiring connecting between the two receivers of the clock net  44  on the clock distributing circuit of the clock synchronous circuit into at least three or more segments through setting at least two or more dividing points on the wiring. 
     Still, the equal delay branch segment determining processor A 5  compares, in the segment given by the first segment dividing processor A 4 , the first delay time from one dividing point on one end of the segment to one receiver of the foregoing two receivers with the second delay time from the one dividing point to the other receiver of the foregoing two receivers, and compares the third delay time from the other dividing point on the other end of the segment to the one receiver of the foregoing two receivers with the fourth delay time from the other dividing point to the other receiver of the foregoing two receivers. The equal delay branch segment determining processor A 5  further determines the segment in which the magnitude of the first delay time against the second delay time and the magnitude of the third delay time against the fourth delay time are inverted as the equal delay branch segment where the equal delay branch point exists. 
     Furthermore, the equal delay branch point determining processor A 6  determines an equal delay branch point Q in the equal delay branch segment given by the equal delay branch segment determining processor A 5 . 
     Further, the delay time determining processor A 7  obtains the fifth delay time t  R  from the equal delay branch point Q given by the equal delay branch point determining processor A 6  to each of the receivers. 
     Further, the second segment dividing processor A 8  sets at least two or more dividing points P 1 , . . . , P n+1  on the wiring from the equal delay branch point Q through the driver output point P and divides the wiring into at least three or more segments  46 . 
     The propagation delay time determining processor A 9  gives a propagation delay time t  PQ  of the wiring in which the delay time of each of the segments  46  obtained by the second segment dividing processor A 8  is taken into account. 
     Still more, the wiring length adjusting processor A 10  compares the preset time γ with the delay time [Delay (P→each receiver)] from the driver output point P to each of the receivers, namely, the sum of the fifth delay time t  R  from the equal delay branch point Q given by the delay time determining processor A 7  to each of the receivers, the propagation delay time t  PQ  of the wiring given by the propagation delay time determining processor A 9 , and the external clock delay time t  LOAD  at the driver output point P; and on the basis of the comparison result, adjusts the wiring length for each segment. 
     And in practice, such functions as being equivalent to these processors A 4  through A 10  can be achieved by the wiring processing program, stored in the hard disk  8 , whereby the CPU  2  of the interactive circuit designing equipment  1  executes the procedures described later. 
     Here, the wiring processing program in the present mode is a software whereby the interactive circuit designing equipment  1  executes a first segment dividing procedure, equal delay branch segment determining procedure, equal delay branch point determining procedure, delay time determining procedure, second segment dividing procedure, propagation delay time determining procedure, and wiring length adjusting procedure. 
     The first segment dividing procedure sets at least two or more branch points on the wiring between the two receivers of the clock net  44  on the clock distributing circuit of the clock synchronous circuit and divides the wiring into at least three or more segments. 
     Furthermore, the equal delay branch segment determining procedure compares, in the segment obtained by the first segment dividing procedure, the first delay time from one dividing point on one end of the segment to one receiver of the foregoing two receivers with the second delay time from the one dividing point to the other receiver of the foregoing two receivers, and compares the third delay time from the other dividing point on the other end of the segment to the one receiver of the foregoing two receivers with the fourth delay time from the other dividing point to the other receiver of the foregoing two receivers. The equal delay branch segment determining procedure further determines the segment in which the magnitude of the first delay time against the second delay time and the magnitude of the third delay time against the fourth delay time are inverted as the equal delay branch segment where the equal delay branch point exists. 
     The equal delay branch point determining procedure determines an equal delay branch point Q in the equal delay branch segment obtained by the equal delay branch segment determining procedure. 
     Further, the delay time determining procedure obtains the fifth delay time t  R  from the equal delay branch point Q given by the equal delay branch point determining procedure to each of the receivers. 
     The second segment dividing procedure sets at least two or more dividing points P 1 , . . . , P n+1  on the wiring from the equal delay branch point Q through the driver output point P and divides the wiring into at least three or more segments  46 . 
     The propagation delay time determining procedure obtains a propagation delay time t  PQ  of the wiring in which the delay time of each of the segments  46  given by the second segment dividing procedure is taken into account. 
     Furthermore, the wiring length adjusting procedure compares the preset time γ with the delay time [Delay (P→each receiver)] from the driver output point P to each of the receivers, namely, the sum of the fifth delay time t  R  from the equal delay branch point Q given by the delay time determining procedure to each of the receivers, the propagation delay time t  PQ  of the wiring given by the propagation delay time determining procedure, and the external clock delay time t  LOAD  at the driver output point P, and on the basis of the comparison result, adjusts the wiring length for each segment. 
     Based on the foregoing construction, in the interactive circuit designing equipment  1  relating to the embodiment of the invention, the following operation determines the equal delay branch point Q and adjusts the wiring length between the equal delay branch point Q and the driver output point P. 
     Namely, in the interactive circuit designing equipment  1 , the first segment dividing step (step S 4 ) sets at least two or more dividing points on the wiring between the two receivers of the clock net  44 , and divides the wiring into at least three or more segments. 
     Next, the equal delay branch segment determining step (step S 5 ) determines the segment in which an equal delay branch point Q exists out of the segments obtained by the first segment dividing step (step S 4 ) as the equal delay segment. 
     Furthermore, the equal delay branch point determining step (step S 6 ) determines the equal delay branch point Q in the equal delay branch segment obtained by the equal delay branch segment determining step (step S 5 ). 
     Further, the delay time determining step (step S 7 ) obtains the fifth delay time t  R  from the equal delay branch point Q given by the equal delay branch point determining step (step S 6 ) to each of the receivers. 
     The second segment dividing step (step S 8 ) sets, as shown in FIG. 9, at least two or more dividing points (branch points) P 1 , . . . , P n+1  on the wiring from the equal delay branch point Q through the driver output point P and to divide the wiring into at least three or more segments  46 . 
     The propagation delay time determining step (step S 9 ) obtains a propagation delay time t  PQ  of the wiring in which the delay time of each of the segments  46  given by the second segment dividing step (step S 8 ) is taken into account. 
     Further, the wiring length adjusting step (step S 10 ) compares, the delay time [Delay (P→each receiver)] from the driver output point P (refer to FIGS. 9,  10 ) to each of the receivers with the preset time γ. 
     When the delay time [Delay (P→each receiver)] from the driver output point P to each of the receivers exceeds the preset time γ at the beginning [namely, Delay (P→each receiver)&gt;γ], the driver  45 A and/or clock tree  45 B are relocated (refer to FIGS. 9,  10 ). 
     When the delay time [Delay (P→each receiver)] from the driver output point P to each of the receivers is less than the preset time γ [namely, Delay (P→each receiver)&lt;γ], on the assumption that the segment of length s is sequentially inserted between the dividing point P 1  and P 2 , the delay time [Delay (P→each receiver)] from the driver output point P to each of the receivers is calculated on each time of the insertion. 
     The calculation of the delay time [Delay (P→each receiver)] from the driver output point P to each of the receivers is continued until the delay time under calculation exceeds the preset time g, and in consequence, the wiring length L between the dividing point P 1  and P 2  is acquired with which the delay time becomes equal to the preset time γ by means of dichotomy, thereby adjusting the wiring length between the equal delay branch point Q and the driver output point P. 
     According to the second mode of the wiring processing method for reducing the clock skew in the interactive circuit designing equipment  1  relating to the embodiment of the invention, in each of the clock nets  44  on the clock distributing circuit of the clock synchronous circuit, the wiring connecting between the receivers in the clock tree  45 B is divided into a plurality of segments to evaluate the delay time by means of a plurality of single Π type RC circuits. Thereby, it is possible to take into account that the resistance and capacitance for a unit grid are not equal independently of the positions on the wiring, and to determine the equal delay branch point Q accurately on the wiring connecting between the receivers. 
     Further, the dividing points are determined from (1) a physical branch point on a wiring connecting between the receivers, (2) a point at which the impedance for a unit length of the wiring connecting between the receivers changes, and (3) a point at which the length of a segment exceeds a predetermined length s (s: optional constant). Thereby, the dividing points can be set so as to match the condition of each of the clock nets  44 , and the equal delay branch point Q can be determined more precisely. 
     Furthermore, as shown in FIG. 9, the wiring from the equal delay branch point Q through the driver output point P is divided into a plurality of segments  46  and the delay time is evaluated by means of a plurality of single Π type RC circuits, and thereby it is possible to take into account that the resistance and capacitance for a unit grid in the wiring are not equal independently of the positions. And, it is also possible to set the dividing points P 1 , . . . , P n+1  so as to match the condition of each of the clock nets  44  by setting the dividing points P 1 , . . . , P n+1  to (1) a point at which the impedance for a unit length of the wiring connecting between the equal delay point Q and the driver output point P changes, or (2) a point at which the length of a segment  46  exceeds a predetermined length s (s: optional constant). 
     In the clock net  44 , the delay time [Delay (P→each receiver)] from the driver output point P to each of the receivers in the clock tree  45 B is compared with the preset time. On the basis of this comparison result, the length of the wiring from the equal delay branch point Q to the driver output point P is adjusted for each segment. Consequently, the delay time from the driver  45 A of the clock net  44  to each of the receivers in the clock tree  45 B can be made equal, while considering the external clock delay time increased with a load applied to the driver  45 A. Accordingly, the clock skew in the clock tree  45 B of the clock net  44  can be reduced more effectively. 
     (b3) Description on the third Mode of the Wiring Processing Method for Reducing the Clock Skew 
     Furthermore, the third mode of the wiring processing method for the interactive circuit designing equipment  1  relating to the embodiment of the invention will be described, whereby the clock skew, namely, the difference of clock propagation delay time in a clock synchronous circuit can be reduced. 
     In the third mode of the wiring processing method for reducing the clock skew, in each of the clock nets on the clock distributing circuit of the clock synchronous circuit, when the equal delay branch points in the wirings connecting between the receivers are accurately determined in advance, only adjusting the wiring length between the equal delay point and the driver output point (extra clock source gate) can reduce the clock skew in the clock net, while considering the external clock delay increased with a load applied to the driver. 
     The wiring processing method in this mode comprises, as shown in FIG. 15, a segment dividing step (step S 11 ), propagation delay time determining step (step S 12 ), and wiring length adjusting step (step S 13 ). 
     The segment dividing step (step S 11 ) sets at least two or more dividing points on the wiring between the equal delay point and the driver output point and divides the wiring into at least three or more segments. 
     The segment dividing step (step S 11 ) is the same step as the foregoing second segment dividing step (step S 8 ) in FIG.  13 . 
     The propagation delay time determining step (step S 12 ) gives a propagation delay time of the wiring in which the delay time for each of the segments obtained by the segment dividing step (step S 11 ) is taken into account. 
     The propagation delay time determining step (step S 12 ) is the same step as the foregoing propagation delay time determining step (step S 9 ) in FIG.  13 . 
     Further, the wiring length adjusting step (step S 13 ) compares the propagation delay time of the wiring obtained by the propagation delay time determining step (step S 12 ) with a preset time, and based on this comparison result, adjusts the wiring length for each segment. 
     The wiring length adjusting step (step S 13 ) is the same step as the foregoing wiring length adjusting step (step S 10 ) in FIG.  13 . 
     The wiring processing method formed of the foregoing steps (step S 11  through S 13 ) is executed on the basis that the CPU  2  (refer to FIG. 1) of the interactive circuit designing equipment  1  has the functions equivalent to a segment dividing processor A 11 , propagation delay time determining processor A 12 , and wiring length adjusting processor A 13 , as shown in FIG.  16 . 
     The segment dividing processor A 11  sets at least two or more dividing points on the wiring on the clock distributing circuit of the clock synchronous circuit and divides the wiring into at least three or more segments. 
     The propagation delay time determining processor A 12  gives a propagation delay time of the wiring in which the delay time for each of the segments obtained by the segment dividing processor A 11  is taken into account. 
     Furthermore, the wiring length adjusting processor A 13  compares the propagation delay time of the wiring obtained by the propagation delay time determining processor A 12  with the preset time, and based on the comparison result, adjusts the wiring length for each segment. 
     And in practice, such functions as equivalent to these processors A 11  through A 13  can be achieved by the wiring processing program, stored in the hard disk  8 , whereby the CPU  2  of the interactive circuit designing equipment  1  executes the procedures described later. 
     Here, the wiring processing program in the present mode is a software whereby the interactive circuit designing equipment  1  executes a segment dividing procedure, propagation delay time determining procedure, and wiring length adjusting procedure. 
     The segment dividing procedure sets at least two or more branch points on the wiring on the clock distributing circuit of the clock synchronous circuit and divides the wiring into at least three or more segments. 
     The propagation delay time determining procedure gives a propagation delay time of the wiring in which the delay time for each of the segments obtained by the segment dividing procedure is taken into account. 
     Furthermore, the wiring length adjusting procedure compares the propagation delay time of the wiring obtained by the propagation delay time determining procedure with the preset time, and based on the comparison result, adjusts the wiring length for each segment. 
     In the interactive circuit designing equipment  1  relating to the embodiment of the invention, based on the foregoing steps (step S 11 ˜S 13 ) shown in FIG. 15, the same operations as the steps (step S 8 ˜S 10 ) shown in FIG. 13 are performed, and the wiring length between the equal delay branch point and the driver output point is adjusted. 
     In this arrangement, the delay time from the driver of the clock net to each of the receivers can be made equal, and the clock skew in the clock tree on the clock net can be reduced effectively while considering the external clock delay increased with a load applied to the driver. 
     (b4) Description on the first Mode of the Wiring Processing Method for Determining a Wiring Path 
     The first mode on the wiring processing method for determining an optimum wiring path in connecting the circuits on an LSI will be described as a wiring processing method in the interactive circuit designing equipment  1  relating to the embodiment of the invention. 
     The circuits on an LSI will be connected in accordance with an optimum wiring path searched by the automatic wiring system, as described above. 
     The method for determining a wiring path in this mode will now be described. 
     The wiring processing method for determining a wiring path in this mode comprises, as shown in FIG. 23, a forward search processing step (step S 14 ) and a backward search processing step (step S 16 ). 
     First, in this mode, in determining a wiring path of a wiring on a circuit board, an available flag, arrival state flag, and arrival direction flag are provided in advance in the hard disk  8  or the memory not illustrated of the interactive circuit designing equipment  1  shown in FIGS. 1,  2 . 
     The available flag is to indicate whether the grid made by dividing the wiring area into grids by the unit of the minimum wiring pitch is available for the wiring or not. As shown in FIG. 18 ( b ), when the grid is available for wiring, “1” is set to the flag, when the grid is not available for wiring, “0” is set to the flag. 
     The arrival state flag is to indicate that a search segment arrives at the grid. As shown in FIG. 18 ( c ), when the search segment has arrived at the grid, “1” to show “arrived” is set to the flag, when the search segment has not arrived at the grid, “0” to show “not arrived” is set to the flag. 
     The available flag and arrival state flag each are provided with one bit for each wiring layer. 
     The arrival direction flag is to indicate the direction in which the search segment has arrived at the grid, and is provided with some bits for each wiring layer. 
     In case of one wiring layer, the available flag and arrival state flag are provided with one bit each. 
     When the X and Y axis are defined as the horizontal and vertical direction, respectively, the arrival direction flag is provided with a XY-direction flag [refer to FIG. 18 ( d )] that indicates the arriving direction to be the X axis direction or Y axis direction for one bit, and a positive-negative direction flag [refer to FIG. 18 ( e )] that indicates the arriving direction to be the positive or negative direction for one bit. 
     Further, the XY-direction flag is set with “1” when the arriving direction is the X axis direction, and set with “0” when the arriving direction is the Y axis direction, as shown in FIG.  18 ( d ). 
     The positive-negative direction flag is set with “1” when the arriving direction is the positive direction, and set with “0” when the arriving direction is the negative direction, as shown in FIG.  18 ( e ). 
     The foregoing available flag, arrival state flag, and arrival direction flag are arranged in such a table format that the byte address and bit number in the memory or the like directly represent the grid coordinates as shown in FIG. 17, in order to process in parallel the operation for segment search in the forward search processing step (step S 14 ), which will be described later in detail. 
     Namely, in order that the operation of searching the segments in the forward search processing step (step S 14 ) can be processed in parallel, each of the grids is expressed by one bit and the flags are arranged in a format as shown in FIG. 17 in this mode. 
     Here, a table  52  in FIG. 17 is arranged so that the current operation can be done by the parallel processing (parallel degree  8  in FIG. 17) for each one ward in the Y axis direction. 
     Further, to arrange the table  52  in FIG. 17 in such a format that the X axis is replaced with the Y axis and to hold the flags by the foregoing table can perform the current operation by the parallel processing for each one ward in the X axis direction. 
     In the wiring processing method in this mode, the forward search processing step (step S 14 ) executes an adjoining grid flag processing procedure S 15  in parallel. 
     Here, the adjoining grid flag processing procedure S 15  operates to set the arrival state flag of an adjoining grid to “1”, when the available flag is “1” and the arrival state flag is “0” as for the grid adjoining to the grid of which the arrival state flag is “1”, and makes the arrival direction flag of the adjoining grid to indicate the search direction (namely, in accordance with the search direction, set the XY-direction flag and sign direction flag to “1” or “0”). 
     Furthermore, the forward search processing step (step S 14 ) repeats the adjoining grid flag processing procedure S 15  until the grid of which the arrival state flag is “1” is not available as to the search segments, thereby the forward searching procedure is executed by producing the segments in sequence. 
     The backward search processing step (step S 16 ) searches, after the arrival state flag of the grid to indicate the end of search becomes “1” (namely, after the search segment reaches the end point) in the forward search processing step (step S 14 ), the wiring path in compliance with the arrival direction flag backward from the grid to indicate the end of search to the grid to indicate the start of search, thus finding out an optimum wiring path. 
     The wiring processing method of the foregoing steps (step S 14 , S 16 ) is executed on the basis that the CPU  2  (refer to FIG. 1) of the interactive circuit designing equipment  1  has the functions equivalent to a forward searching processor A 14  and backward searching processor A 16  shown in FIG.  24 . 
     The forward searching processor A 14  is provided with an adjoining grid flag processor A 15 , which executes in parallel the foregoing adjoining grid flag procedure S 15 . Further, the adjoining grid flag processor A 15  repeats to execute the adjoining grid flag processing procedure S 15  until the grid of which the arrival state flag is “1” is not available as to the search segments, thereby forward searching processing is executed to produce the segments in sequence. 
     Further, the backward searching processor A 16  searches, after the arrival state flag of the grid to indicate the end of search becomes “1” (namely, after the search segment reaches the end point) in the forward searching processor A 14 , the wiring path in compliance with the arrival direction flag backward from the grid to indicate the end of search to the grid to indicate the start of search, thus the backward searching procedure is executed by finding out an optimum wiring path. 
     And in practice, the functions equivalent to the processor A 14 , A 16  can be achieved by the wiring processing program, stored in the hard disk  8 , whereby the CPU  2  of the interactive circuit designing equipment  1  executes the procedures described later. 
     Here, the wiring processing program in this mode is a software whereby the interactive circuit designing equipment  1  executes the forward searching procedure and the backward searching procedure. 
     As for a grid adjoining to the grid obtained by dividing the wiring area into grids by the unit of the minimum wiring pitch on a circuit board, the grid of which the arrival state flag indicating the arrival of the search segment is “1”, when the available flag indicating whether the grid is available for wiring or not is “1” and the arrival state flag is “0”, the forward searching procedure executes in parallel the adjoining grid flag processing procedure S 15  (refer to FIG.  23 ), whereby the arrival state flag of the adjoining gird is set to “1” and the arrival direction flag indicating the arrival direction in which the search segment has arrived at the adjoining grid is made to indicate the search direction (namely, in accordance with the search direction, to set the XY-direction flag and positive-negative direction flag to “1” or “0”). Furthermore, the forward search procedure repeats the adjoining grid flag processing procedure S 15  until the grid of which the arrival state flag is “1” comes into nonexistence as to the search segments, thereby producing the segments in sequence. 
     The backward searching procedure searches, after the arrival state flag of the grid to indicate the end of search becomes “1” (namely, after the search segment reaches the end point) in the forward searching procedure, the wiring path in compliance with the arrival direction flag backward from the grid to indicate the end of search to the grid to indicate the start of search, thus finding out an optimum wiring path. 
     In the interactive circuit designing equipment  1  relating to the embodiment of the invention, the following operation based on the foregoing construction searches a wiring path and determines an optimum wiring path. 
     The method for determining a wiring path on a circuit board shown in FIG. 18 ( a ) will hereafter be described. 
     FIG. 18 ( a ) illustrates an initial state of a circuit board (a state before a wiring path is determined), in which the start point of search is indicated by S and the end point of search is indicated by T. Further, in FIG. 18 ( a ), wiring prohibited areas on the circuit board due to the presence of circuits and the like are illustrated by continuous lines. 
     The available flag, arrival state flag, XY-direction flag, and positive-negative direction flag at the initial state of the circuit board shown in FIG. 18 ( a ) each are illustrated in FIG. 18 ( b ) through FIG. 18 ( e ). 
     In FIG. 18 ( b ) through FIG. 18 ( e ), the grid of the flag “1” is shown with a half-tone dot meshing. As shown in FIG. 18 ( b ), the arrival state flag at the start point S is set to “1” at the initial state. 
     In the interactive circuit designing equipment  1 , when, as for the arrival state flag of “1”, the available flag of the grid adjoining in the direction searching the grid is “1” and the arrival state flag is “0”, the forward search processing step (step S 14 ) sets “1” to the arrival state flag of the adjoining grid and records the search direction into the arrival direction flag. 
     In the forward search processing step (step S 14 ), the foregoing operation is continued until the grid of which the arrival state flag is set to “1” comes into nonexistence as to the search segments. 
     When a wiring path is determined on a wiring on a circuit board as shown in FIG. 18 ( a ), first, as shown in FIG. 19 ( a ), a search segment is produced in the X axis direction from the start point S (search level  1 ). At this moment, the available flag, arrival state flag, XY-direction flag, and positive-negative direction flag each are illustrated in FIGS. 19 ( b ) through ( e ). 
     Next, as shown in FIG. 20 ( a ), a search segment is produced in the Y axis direction from the search segment produced in the foregoing search level  1  (search level  2 ). In this search level  2  and the subsequent search level (search level  3 ,  4 ), if the search segment is produced in parallel, the processing speed will increase. Here, the available flag, arrival state flag, XY-direction flag, and positive-negative direction flag each are illustrated in FIGS. 20 ( b ) through ( e ). 
     Further, as shown in FIG. 21 ( a ), a search segment is produced in the X axis direction from the search segment produced in the foregoing search level  2  (search level  3 ). Here, the available flag, arrival state flag, XY-direction flag, and positive-negative direction flag each are illustrated in FIGS. 21 ( b ) through ( e ). 
     Furthermore, as shown in FIG. 22 ( a ), a search segment is produced in the Y axis direction from the search segment produced in the foregoing search level  3  (search level  4 ). Here, the available flag, arrival state flag, XY-direction flag, and positive-negative direction flag each are illustrated in FIGS. 22 ( b ) through ( e ). 
     After the search segment reaches the end point T, as shown in FIG. 22 ( f ), the backward search processing step (step S 16 ) searches a wiring path backward from the end point T to the start point S in accordance with the arrival direction flag, thereby, determining an optimum wiring path. 
     Thus, according to the first mode of the wiring processing method for determining a wiring path in the interactive circuit designing equipment  1  relating to the embodiment of the invention, the available flag, arrival state flag, and arrival direction flag are arranged, as shown in FIG. 17, such that the byte address and bit number in the memory and the like directly indicate the coordinates of the grid. Thereby, the forward search processing step (step S 14 ) can process the operations in parallel in a high speed, thus significantly reducing time for searching a wiring path. 
     (b5) Description on the second Mode of the Wiring Processing Method for Determining a Wiring Path 
     Next, the second mode on the wiring processing method for determining an optimum wiring path in connecting the circuits on an LSI will be described as a wiring processing method in the interactive circuit designing equipment  1  relating to the embodiment of the invention. 
     The wiring processing method for determining a wiring path in this mode comprises, as shown in FIG. 27, a forward search processing step (step S 17 ), backward search processing step (step S 18 ), and optimum wiring path determining step (step S 19 ). 
     First, in this mode, in determining a wiring path on a circuit board, an arrival direction flag is provided in advance in the hard disk  8  or the memory not illustrated of the interactive circuit designing equipment  1  shown in FIGS. 1,  2 . 
     Here, the arrival direction flag is to indicate the direction in which the search segment has arrived at the grid made by dividing the wiring area into grids by the unit of the minimum wiring pith. 
     The arrival direction flag is provided with a flag that indicates the arrival of the search segment by “1” for each of the directions of the grids. 
     For example, in one layer wiring, if the X and Y axis are defined as the horizontal and vertical direction, respectively, the flags are provided to each of the positive and negative direction of the X axis and the positive and negative direction of the Y axis. 
     In case a plurality of wiring paths are not designed to be searched, a wiring path first searched is selected as the wiring path [the wiring path reached from left to the end point T, in case of FIG. 25 ( a )], and therefore, a wiring path which is not optimum is possibly selected. 
     Therefore, in this embodiment, a plurality of wiring paths are searched, as shown in FIG. 26 ( a ), and the optimum wiring path is designed to be selected among a plurality of the wiring paths [the wiring path of which the wiring length is the shortest, in case of FIG. 26 ( b )]; in order to accomplish the foregoing, the arrival direction flag is composed of four types of flags indicating that the search segments arrive from the directions. 
     The forward search processing step (step S 17 ) searches the grids forward in determining a wiring path on a circuit board as shown in FIG. 26 ( a ), while indicating a plurality of the search directions on the arrival direction flag. 
     Namely, in the forward search processing step (step S 17 ), when the search segments arrive at the grids from a plurality of directions, the arrival direction flag corresponding to the arriving direction is set to “1”. 
     The backward search processing step (step S 18 ) searches, after the arrival state flag of the grid to indicate the search end point becomes “1” (namely, after the search segment reaches the end point) in the forward search processing step (step S 17 ), the wiring path in compliance with the arrival direction flag backward from the grid to indicate the search end point T to the grid to indicate the search start point S as shown in FIG. 26 ( a ), thus finding out a plurality of the wiring paths [four wiring paths in FIG. 26 ( a )]. 
     Further, the optimum wiring path determining step (step S 19 ) gives the wiring lengths and costs of a plurality of the wiring paths obtained by the backward search step (step S 18 ), and determines an optimum wiring path as shown in FIG. 26 ( b ). 
     Concretely, the optimum wiring path determining step (step S 19 ) determines the wiring path of which the wiring length or the wiring cost is minimum as the optimum. 
     The wiring processing method consisting of the foregoing steps (step S 17  through S 19 ) is executed on the basis that the CPU  2  (refer to FIG. 1) of the interactive circuit designing equipment  1  has the functions equivalent to a forward search processor A 17 , backward search processor A 18 , and optimum wiring path determining processor A 19 , as shown in FIG.  28 . 
     The forward search processor A 17  searches forward the grids obtained by dividing the wiring area into grids by the unit of the minimum wiring pith in determining a wiring path on a circuit board as shown in FIG. 26 ( a ), while indicating a plurality of the search directions on the arrival direction flag indicating the arrival direction of the search segment. 
     Further, the backward search processor A 18  searches, after the arrival state flag of the grid to indicate the search end point becomes “1” in the forward search processor A  17  (namely, after the search segment reaches the end point), the wiring path in compliance with the arrival direction flag backward from the grid to indicate the search end point T to the grid to indicate the search start point S as shown in FIG. 26 ( a ), thus finding out a plurality of the wiring paths [four wiring paths in FIG. 26 ( a )]. 
     Furthermore, the optimum wiring path determining processor A 19  acquires the wiring length or wiring cost of a plurality of the wiring paths obtained by the backward search processor A 18 , and thereby determines, as shown in FIG. 26 ( b ), a wiring path that the wiring length or wiring cost is the minimum as an optimum wiring path. 
     And in practice, the functions equivalent to the processor A 17  through A 19  can be achieved by the wiring processing program, stored in the hard disk  8 , whereby the CPU  2  of the interactive circuit designing equipment  1  executes the procedures described later. 
     Here, the wiring processing program in this mode is a software whereby the interactive circuit designing equipment  1  executes the forward search procedure, backward search procedure, and the optimum wiring path determining procedure. 
     The forward searching procedure searches forward the grids obtained by dividing the wiring area into grids by the unit of the minimum wiring pitch in determining a wiring path on a circuit board as shown in FIG. 26 ( a ), while indicating a plurality of the search directions on the arrival direction flag indicating the arrival directions of the search segments. 
     Further, the backward searching procedure searches, after the arrival state flag of the grid to indicate the search end point becomes “1” in the forward searching procedure (namely, after the search segment reaches the end point), the wiring path in compliance with the arrival direction flag backward from the grid to indicate the search end point T to the grid to indicate the search start point S as shown in FIG. 26 ( a ), thus finding out a plurality of the wiring paths [four wiring paths in FIG. 26 ( a )]. 
     Furthermore, the optimum wiring path determining procedure acquires the wiring length or wiring cost of a plurality of the wiring paths obtained by the backward search procedure, and thereby determines, as shown in FIG. 26 ( b ), a wiring path that the wiring length or wiring cost is the minimum as an optimum wiring path. 
     Based on the foregoing arrangement in the interactive circuit designing equipment  1  relating to the embodiment of the invention, the following operation searches wiring paths and determines an optimum wiring path. 
     In the interactive circuit designing equipment  1 , first, the forward search processing step (step S 17 ) searches each of the grids forward while, in case search segments arrive at grids from a plurality of directions, setting the arrival flag corresponding to the directions to “1”. 
     The backward search processing step (step S 18 ) searches, after the arrival state flag of the grid to indicate the search end point becomes “1” (namely, after the search segment reaches the end point) in the forward search processing step (step S 17 ), wiring paths in compliance with the arrival direction flag backward from the grid to indicate the search end point T to the grid to indicate the search start point S as shown in FIG. 26 ( a ), thus finding out a plurality of the wiring paths. 
     In case of determining a wiring path on a circuit board as shown in FIG. 26 ( a ), the backward search processing step (step S 18 ) searches wiring paths backward in compliance with the arrival direction flag so as to find out four wiring paths. 
     Furthermore, in the backward search processing step (step S 18 ), when a plurality of the wiring paths are searched, the optimum wiring path determining step (step S 19 ) determines an optimum wiring path from these plural wiring paths, as shown in FIG. 26 ( b ). 
     In case of determining a wiring path on a circuit board as shown in FIG. 26 ( a ), the optimum wiring path determining step (step S 19 ) acquires a wiring length of each of the wiring paths obtained by the backward search processing step (step S 18 ), and thereby determines an wiring path of which the wiring length is the shortest. 
     Thus, according to the second mode of the wiring processing method for determining a wiring path in the interactive circuit designing equipment  1 , the arrival direction flag is designed to indicate the arrival direction of the search segment to the grid (concretely, the arrival direction flag is composed of four types of flags to indicate the arrival of the segments from each direction to the grid). Thereby, a plurality of the wiring paths can be searched so as to select an optimum wiring path among them, and therefore, the wiring length can be minimized to improve the wiring quality. 
     Further, based on the wiring congestion degree in each divided area in case a wiring area is divided into smaller areas and the delay value of each wiring layer in case plural wiring layers are provided, the wiring cost can also be set for each of the grids. With this arrangement, the foregoing optimum wiring path determining step (step S 19 ) can determine an optimum wiring path in which wiring quality and circuit performance are considered. 
     (b6) Description on the third Mode of the Wiring Processing Method for Determining a Wiring Path 
     The third mode of the wiring processing method for determining an optimum wiring path in connecting the circuits on an LSI will be described as a wiring method in the interactive circuit designing equipment  1  relating to the embodiment of the invention. 
     In this mode, to determine an optimum wiring path, a wiring congestion degree is estimated as a wiring possibility before executing a wiring at the stage where a circuit layout finishes, and according to the wiring congestion degree, the circuit layout is appropriately modified. 
     The wiring method for determining a wiring path in this mode comprises, as shown in FIG. 30, a circuit layout determining step (step S 20 ), wiring congestion degree evaluating step (step S 21 ), and circuit layout modifying step (step S 22 ). 
     Here, the circuit layout determining step (step S 20 ) determines a layout of a circuit on a circuit board. In this circuit layout determining step (step S 20 ), the layout of a circuit on a circuit board is determined by a conventional method and the like. 
     The wiring congestion degree evaluating step (step S 21 ) acquires, after the circuit layout determining step (step S 20 ) determined the layout of a circuit, a wiring congestion degree of a wiring to connect circuits, and thereby evaluates the circuit layout determined by the circuit layout determining step (step S 20 ). 
     The method for evaluating a wiring congestion degree in the wiring congestion evaluating step (step S 21 ) will now be described. 
     First, a probability whereby a net made by wirings as shown in FIG. 29 occupies dots in a wiring area is considered. 
     The probability whereby the net occupies the dots in the wiring area can be expressed by means of an area S of a minimum rectangle including terminals (terminals are shown by · mark in FIG. 29) of the net to be wired and the theoretical length l of the net. 
     A probability p i  whereby a net i of a theoretical length l i  occupies dots inside the rectangle of an area Si is assumed to be 
     
       
           p   i   =l   i   /S   i . 
       
     
     Here, assuming that the sum of the theoretical lengths l i  is a total wiring length L, the total wiring length L is defined as the following equation.        L   =       ∑   i          l   i                       
     On the other hand, the number G of the dots used for the wirings when overlapping of the nets is allowed can be obtained by summarizing the following as to all the dots contained in all the wiring areas. 
     ‘probability of only one net using the dots’ 
     + ‘probability of only two nets using the dots’ 
     + ‘probability of only three nets using the dots’ 
     + ‘probability of all the nets using the dots’ 
     Here, ‘probability of only one net using the dots’ is given by the following equation.            ∑   i            [       p   i                       ∏   j                     (     1   -     p   j       )         ]                   here       ,     i   ≠     j   .                       
     And, ‘probability of only two nets using the dots’ is given by the following equation.          (     1   /     2   !       )          ∑     [       p   i                     p   j            ∏   ij                     (     1   -     p   k       )         ]               here   ,     i   ≠   j     ,     j   ≠   k     ,     k   ≠     i   .                       
     In the same manner as above, ‘probability of only n nets using the dots’ is given by the following equation.          (     1   /     n   !       )          ∑         [       p   i                   ⋯                   p   j              n            Π        (     1   -     p   k       )                    ]                           
     The probability p i  of the net  i  of the theoretical length li occupying the dots is considered smaller than 1, and therefore, ‘probability of only n nets using the dots’ is considered to converge rapidly as n increases. 
     Therefore, the number G of the dots used for the wirings can be approximated using an appropriate number of the nets. 
     If, two wiring paths have an equal total wiring length L, one having a smaller number G of the dots used can be considered as having a larger wiring congestion degree, and therefore, as an evaluation scale of the wiring congestion degree, the following is considered. 
     
       
         (L−G)/L 
       
     
     Here, the total wiring length L is expressed as follows. 
     L=1×‘probability of only one net using the dots’+ . . . + 
     ‘number of all the nets’×‘probability of all the nets using the dots’ 
     Accordingly, calculating L by ignoring the terms in which more than four probabilities of the probability p i  of the net i of the theoretical length l i  occupying the dots are multiplied in the foregoing equation, 
     
       
           L−G=Σ [(½) T   1   2 +(½) T   1   T   2 −(½) T 2 −(⅙) T   1   3 −(⅓) T   3 ] 
       
     
     here, Σ means the sum in all the dots in the wiring area, T 1 =Σ p i , T 2 =Σ(p 1   2 ), T 3 =Σ(p i   3 ). 
     Therefore, (L−G) can be calculated by using the sum of the products by the probability of each of the nets occupying a dot. 
     Thus, (L−G)/L is calculated, which will be used as a scale for evaluating the wiring congestion degree to improve a wiring possibility. 
     In this manner, the wiring congestion evaluating step (step S 21 ) evaluates, after the circuit layout determining step (step S 20 ) determines a layout of a circuit, the wiring congestion degree from the foregoing (L−G)/L: here, L is the total wiring length of the wirings to connect the circuits, G is the number of the dots used for wiring. Thereby, a circuit layout determined by the circuit layout determining step (step S 20 ) is evaluated. 
     Further, the circuit layout modifying step (step S 22 ) modifies, after the wiring congestion evaluating step (step S 21 ) acquires a wiring congestion degree and evaluates a circuit layout, the circuit layout in accordance with the evaluation from the wiring congestion degree; and thereby, improves the circuit layout and optimizes the wiring areas. In this circuit layout modifying step (step S 22 ), improving the layout and optimizing the wiring areas are done by means of a conventional method and the like. 
     In the interactive circuit designing equipment  1 , after the circuit layout modifying step (step S 22 ) modifies the circuit layout as needed, the wiring processing is made to produce an optimum wiring path. 
     The wiring processing method consisting of the foregoing steps (step S 20  through S 22 ) is executed on the basis that the CPU  2  (refer to FIG. 1) of the interactive circuit designing equipment  1  has the functions equivalent to a circuit layout determining processor A 20 , wiring congestion degree evaluating processor A 21 , and circuit layout modifying processor A 22 , as shown in FIG.  31 . 
     The circuit layout determining processor A 20  determines a layout of a circuit on a circuit board. 
     The wiring congestion degree evaluating processor A 21  evaluates, after the circuit layout determining processor A 20  determines a layout of a circuit, the wiring congestion degree from the foregoing (L−G)/L: here, L is the total wiring length of the wirings to connect the circuits, G is the number of the dots used for wiring. Thereby, a circuit layout determined by the circuit layout determining processor A 20  is evaluated. 
     Further, the circuit layout modifying processor A 22  modifies, after the wiring congestion evaluating processor A 21  acquires a wiring congestion degree and evaluates a circuit layout, the circuit layout in accordance with the evaluation from the wiring congestion degree; and thereby, improves the circuit layout and optimizes the wiring areas. 
     And in practice, the functions equivalent to the processor A 20  through A 22  can be achieved by the wiring processing program, stored in the hard disk  8 , whereby the CPU  2  of the interactive circuit designing equipment  1  executes the procedures described later. 
     Here, the wiring processing program in this mode is a software whereby the interactive circuit designing equipment  1  executes the circuit layout determining procedure, wiring congestion degree evaluating procedure, and circuit layout modifying procedure. 
     The circuit layout determining procedure determines a layout of a circuit on a circuit board. 
     The wiring congestion degree evaluating procedure evaluates, after the circuit layout determining procedure determines the layout of the circuit, the wiring congestion degree from the foregoing (L−G)/L: here, L is the total wiring length of the wirings to connect the circuits, G is the number of the dots used for wiring. Thereby, a circuit layout determined by the circuit layout determining procedure is evaluated. 
     Further, the circuit layout modifying procedure modifies, after the wiring congestion degree evaluating procedure acquires a wiring congestion degree and evaluates a circuit layout, the circuit layout in accordance with the evaluation from the wiring congestion degree; and thereby, improves the circuit layout and optimizes the wiring areas. 
     Based on the foregoing arrangement, in the interactive circuit designing equipment  1  relating to the embodiment of the present invention, the following operation determines a circuit layout, evaluates the congestion degree of a circuit layout thus determined, and modifies the circuit layout in accordance with the evaluation from the congestion degree. 
     In the interactive circuit designing equipment  1 , first, the circuit layout determining step (step S 20 ) determines a layout of a circuit on a circuit board. 
     Next, after the circuit layout determining step (step S 20 ) determines a layout of a circuit, the wiring congestion degree evaluating step (step S 21 ) acquires a wiring congestion degree of the wirings to connect the circuits, and on the basis of this wiring congestion degree evaluates the circuit layout determined by the circuit layout determining step (step S 20 ). 
     Furthermore, in accordance with the evaluation from the wiring congestion degree by the wiring congestion degree evaluating step (step S 21 ), the circuit layout modifying step (step S 22 ) appropriately modifies a circuit layout. 
     And, in the interactive circuit designing equipment  1 , after a circuit layout is appropriately modified by the circuit layout modifying step (step S 22 ), the wiring processing is made to produce an optimum wiring path. 
     Thus, according to the third mode of the wiring processing method for determining a wiring path in the interactive circuit designing equipment  1  relating to the embodiment of the invention, at the stage where a circuit layout is completed and before the wiring is executed, the wiring congestion degree is estimated to evaluate the wiring possibility, and the circuit layout is appropriately modified in accordance with an evaluation from this wiring congestion degree; thus determining an optimum wiring path. 
     Furthermore, the value (L−G)/L is calculated to evaluate a wiring congestion degree, and a wiring possibility can be estimated at the stage where a layout of the circuits is completed before the wiring is executed; and therefore, an early estimation and evaluation of the wiring possibility becomes possible which is strongly requested as a wiring objective becomes increasingly gigantic. 
     On the basis of the value (L−G)/L to evaluate the wiring congestion degree, the circuit layout is further modified to optimize the wiring areas.