Patent Publication Number: US-2021173421-A1

Title: Fdsoi-technology electronic voltage divider circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to foreign French patent application No. FR 1913861, filed on Dec. 6, 2019, the disclosure of which is incorporated by reference in its entirety. 
     FIELD OF THE INVENTION 
     The present invention relates to a voltage divider circuit comprising transistors on insulating thin film (or FDSOI transistors, for “Fully Depleted Silicon On Insulator”), and able to be used in various circuits, for example a clock generator circuit including a ring oscillator. 
     BACKGROUND 
     Ring oscillators comprise an odd number of inverters forming a loop. An oscillating signal is obtained naturally at the output of each inverter. Their oscillating frequency is based on the switching time of the inverters, and is therefore linked directly to the number of inverters in the loop. The greater the number of inverters, the more the oscillating frequency decreases. The switching time of an inverter depends on various parameters, notably its supply voltage, its temperature, and this switching time may vary from one inverter to another owing to technological dispersions. The oscillating frequency is therefore strongly dependent on these parameters and may be difficult to control and stabilize. 
     To solve this problem, the prior art discloses ring oscillators comprising a circuit for generating a current/voltage supply, comprising a differential amplifier AO and a reference resistor R ref , as shown in  FIG. 1A . 
     The operating principle of this type of oscillator is that of slaving the intrinsic resistance (resulting from the inverters I 1 , I 2  and I 3 , which may be likened to switching capacitors) of the string of inverters I 1 , I 2 , I 3  to the reference resistance R ref . The reference resistance R ref  is fixed. The intrinsic resistance is then equal to the reference resistance R ref , since the potentials V ro  and V res  are identical and the currents i res , i ro  flowing in the two branches Bres and B ra  are identical. 
     This type of oscillator oscillates at a frequency f dependent on the intrinsic resistance, and therefore on the reference resistance R re f, on an equivalent capacitance C representing the switching of the inverters I 1 , I 2  and I 3  and on a parameter n representing the number of inverters in the loop, such that f=1/(n×C×R ref ). 
     However, for low-power oscillators, it is necessary to use a high-value reference resistor R ref  (approximately 10 to 100 MO), since the potentials V res  and V ro  at the input of the amplifier AO are a few hundred millivolts and the currents are as low as possible for consumption reasons. The resistor R ref  is therefore bulky and costly in terms of silicon surface. For example, for a voltage V ro =V res =500 mV and a current i of 100 nA, it will be necessary to use a resistor R ref  of 5 MΩ. The resistor R ref  will therefore be bulky and will in practice constitute virtually 80% of the silicon surface of the oscillator. 
     This architecture requires a compromise between oscillating frequency, consumed power and silicon surface of the reference resistor R ref  in a low-power application (approximately 10 to 50 nW). 
     Moreover, one drawback of the oscillator circuit shown in  FIG. 1  is that it is difficult in practice to make it insensitive to temperature variations. If the value of the reference resistor varies as a function of temperature, then the frequency of the oscillator will also vary. Using such an oscillator therefore requires using resistors that are only slightly or not temperature-sensitive if it is not desired to cause variations in the oscillating frequency. This limits the implementation options for the resistors and may lead to an extra surface cost for producing such resistors insensitive to temperature variations. It is furthermore rarely possible to have a temperature-compensated resistor, notably in FDSOI technologies. 
     More generally, this problem in terms of bulk of the silicon surface also arises in any application using a reference resistor, for example for reference current generators or reference voltage generators or more generally for any analogue voltage/current conversion system implemented in current generators, analogue-to-digital converters or oscillators. 
       FIG. 1B  shows one example of a circuit for generating a reference current. 
     The reference voltage V re f used in such a circuit is generally supplied by a “bandgap” circuit delivering a “high” voltage (conventionally 1.2 V). If it is also desired to have low electrical consumption, it is necessary for the current flowing in the resistor to be as low as possible. Thus, just like for the oscillator, it is necessary for the resistor to have a high value. It will furthermore be noted that this type of circuit also requires the use of a resistor insensitive to temperature variations if it is desired to obtain a generated reference current that is invariable in terms of temperature. 
     SUMMARY OF THE INVENTION 
     The invention aims to rectify the abovementioned drawbacks of the prior art by proposing an electronic voltage divider circuit produced using FDSOI technology (transistor on insulating thin film). 
     According to the invention, this aim is achieved by virtue of the clever use of the back-gate biases of FDSOI transistors of a circuit usually used to form a current source. 
     One subject of the invention is therefore an electronic voltage divider circuit comprising at least two FDSOI transistors on insulating thin film of a first type connected to a first supply potential and arranged in a current mirror structure and two FDSOI transistors on thin film of a second type and an electrical load of non-zero impedance, the transistors each having a front-face main gate and a back-face control gate, a drain of a first transistor of the second type being connected to the drain of a first transistor of the first type, a drain of a second transistor of the second type being connected to the drain of a second transistor of the first type, the drain of the first transistor of the second type being connected to the front-face gate of this same transistor, the front-face gates of the first and second transistors of the second type being connected to one another, the source of the first transistor of the second type being connected to a second supply potential and said load of non-zero impedance being placed between the source of the second transistor of the second type and said second supply potential, characterized in that the back-face gates of the first and second transistors of the second type are connected to an external circuit applying a non-zero input voltage between these two back-face gates, such that the back-face gate of the first transistor of the second type is brought to a potential lower than that of the back-face gate of the second transistor of the second type if these two transistors are of nMOS type, and that the back-face gate of the first transistor of the second type is brought to a potential greater than that of the back-face gate of the second transistor of the second type if these two transistors are of pMOS type, as a result of which the voltage across the terminals of said load constitutes an output voltage equal to a fraction of the input voltage. 
     Another subject of the invention is an electronic system comprising such an electronic circuit and comprising a third transistor of the first type of which the source is connected to the first supply potential, the gate being connected to the gates of the first and second transistors of the first type, and the drain being connected to a node connected to a load circuit. 
     Particular embodiments of the electronic voltage divider circuit and of the electronic system are the subject matter of the dependent claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other features, details and advantages of the invention will become apparent upon reading the description with reference to the appended figures, which are given by way of example and in which, respectively: 
         FIG. 1A , already described, shows a ring oscillator comprising a loop of inverters according to the prior art; 
         FIG. 1B , already described, shows a current source comprising a resistor and a control circuit for slaving the voltage across the terminals of the resistor according to the prior art; 
         FIG. 2  shows an FDSOI transistor according to the prior art; 
         FIG. 3  shows an electronic circuit for generating a reference voltage according to a first embodiment of the invention; 
         FIG. 4  and  FIG. 5  show the ratio between two potentials as a function of temperature for two types of transistors of the circuit according to the first embodiment of the invention; 
         FIG. 6  shows an electronic circuit according to a second embodiment of the invention; 
         FIG. 7  shows a ring oscillator according to a first embodiment of the invention; 
         FIG. 8  shows the oscillating frequency as a function of the temperature of the oscillator according to the first embodiment of the invention determined by simulation; 
         FIG. 9  shows a ring oscillator according to a second embodiment of the invention; 
         FIG. 10  shows a current generator formed from a circuit according to the invention; and 
         FIG. 11 a    and  FIG. 11 b    show simulation results obtained for the current generator from  FIG. 10 . 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 2  shows the internal structure of an FDSOI transistor (transistor formed on an insulating thin film). The FDSOI transistor comprises a layer of a p-type silicon substrate Sub, a buried layer of an insulating material Iso, also called BOX, separated from the substrate Sub by a ground plane PM. The insulating layer Iso is surmounted by an active silicon layer Act in which a source S, a channel C and a drain D are placed. The ground plane PM (or well NWELL or PWELL depending on its doping) makes it possible to improve the electrostatic control of the transistor by limiting the penetration of the electric fields that are generated by the drain D and the source S under the channel C. The channel C is covered by a gate oxide layer OxG. The gate oxide OxG is surmounted by a metal gate G. The FDSOI transistor has a front-face gate Gtop and a back-face gate G back . The front-face gate G top  is the main gate for choosing the operating mode of the transistor (off, on). The back-face gate Gback for its part forms a control gate, the voltage applied to this back gate making it possible to vary the operating characteristics of the transistor, notably its threshold voltage. 
     Generally speaking, it is possible to vary the threshold voltage V th , of FDSOI transistors by acting on the n or p doping of the well PM, on the connection metal of the gate and on the well voltage with respect to the source voltage applied to the transistor. To provide various types of transistor (different threshold voltage V th ), the manufacturing method is applied to the connection metal of the gate and to the doping of the well (n or p). A transistor with a low V th , called LVT (“low threshold voltage”) transistor, will have a relatively low voltage V th , (of the order of 400 to 450 mV), and a transistor with a high V th , called RVT (“regular threshold voltage”) transistor, will have a relatively higher voltage V th , (of the order of 500 to 550 mV). 
     When using transistors, the threshold voltage V th , of the transistors is modified dynamically by modifying the voltage difference between the well and the source, thereby advantageously making it possible to obtain lower threshold voltages V th , with LVT transistors (conventionally used to accelerate its speed) and to obtain higher threshold voltages V th  with RVT transistors (conventionally used to control and limit static losses). Specifically, a ground plane PM of the same type as the source S and the drain D makes it possible to obtain an FDSOI transistor having a low threshold voltage value V th , whereas a ground plane PM of a type different from the source S and the drain D makes it possible to obtain an FDSOI transistor having a high threshold voltage value V th . 
     An LVT nMOS FDSOI transistor therefore has a drain D and a source S that are n-doped and an n-doped ground plane PM (that is to say an n-doped well NWELL), while an RVT nMOS transistor has a drain D and a source S that are n-doped and a p-doped ground plane PM (that is to say a p-doped well PWELL). 
     An LVT pMOS FDSOI transistor has a drain D and a source S that are p-doped and a p-doped ground plane PM (that is to say a p-doped well PWELL), while an RVT pMOS FSDOI transistor has a drain D and a source S that are p-doped and an n-doped ground plane PM (that is to say an n-doped well NWELL). 
     A detailed description of the various transistor implementation options showing higher or lower voltage threshold ranges is given in patent EP2415079 in the name of the Applicant. 
       FIG. 3  shows an electronic voltage divider circuit according to a first embodiment of the invention. Two pMOS FDSOI transistors TP 1  and TP 2  are connected to one another so as to form a current mirror. The source of the transistor TP 1  and the source of the transistor TP 2  are connected to one and the same supply potential V DD , the front-face gate G top  of the transistor TP 1  is connected to the front-face gate of the transistor TP 2  and the front-face gate of the transistor TP 2  is connected to the drain of the transistor TP 2 . 
     It will be considered that the transistors TP 1  and TP 2  are identical, and therefore their W/L ratios are identical, where W is the width of the channel and L is the length of the front-face gate G top  of each of the transistors. The current mirror forms two branches B 1  and B 2  in which one and the same electric current i flows. 
     This current mirror is connected to a pair of nMOS FDSOI transistors TN 1  and TN 2 . The drain of the transistor TP 1  is connected to the drain of the transistor TN 1  and the drain of the transistor TP 2  is connected to the drain of the transistor TN 2 . The source of the nMOS transistor TN 1  is connected to an electrical ground. 
     A resistor R is placed between the source of the transistor TN 2  and the electrical ground. The drain of the transistor TN 1  is connected to the front-face gate G top  of the transistor TN 1  and the two front-face gates G top  of the transistors TN 1  and TN 2  are connected to one another. 
     The back-face gates G back  of the four FDSOI transistors TN 1 , TN 2 , TP 1  and TP 2  are biased by an “external” circuit CPGA. More specifically, the back gates Gback of the transistors TN 1  and TN 2  are respectively biased at potentials V BBN1  and V BBN2 , while the back gates G back  of the other transistors TP 1  and TP 2  are kept at a constant potential, equal in this example to the ground potential. As will be understood upon reading the explanations below, in order for the circuit to be functional (for a current to flow in the branches), it is necessary for the potentials V BBN2  and V BBN1  to be different, in practice significantly different, and for them to be such that V BBN2 &gt;V BBN1 . 
     V R  will be used to denote the potential of the source of the transistor TN 2  (corresponding to the voltage across the terminals of the resistor R), and this potential V R  has the value i×R, i being the current flowing in the two branches B 1  and B 2 . 
     The capability of a transistor will also be denoted β=(W/L)×μ×C ox , where (W/L) is the ratio between the width W and the length L of the channel of the transistor, μ is the mobility of the charge carriers and C ox  is the gate oxide capacitance of the transistor. 
     For the transistor TN 1 , it may be written that the current i is equal to: 
     
       
         
           
             
               
                 
                   i 
                   = 
                   
                     
                       β 
                       
                         TN 
                          
                         
                             
                         
                          
                         1 
                       
                     
                      
                     
                       J 
                       
                         D 
                          
                         
                             
                         
                          
                         0 
                       
                     
                      
                     
                       exp 
                        
                       
                         ( 
                         
                           
                             
                               V 
                               
                                 GTN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                             - 
                             
                               V 
                               
                                 ThTN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                           
                           
                             nV 
                             T 
                           
                         
                         ) 
                       
                     
                      
                     
                       ( 
                       
                         
                           e 
                           
                             - 
                             
                               
                                 V 
                                 
                                   STN 
                                   1 
                                 
                               
                               
                                 V 
                                 T 
                               
                             
                           
                         
                         - 
                         
                           e 
                           
                             
                               V 
                               
                                 DTN 
                                 1 
                               
                             
                             
                               V 
                               T 
                             
                           
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     Where β TN1  is the capability of the transistor TN 1 , J D0  is a constant representing the saturation threshold of the transistors, n is the slope factor, V GTN1  is the front-face gate G top  potential of the transistor TN 1 , V ThTN1  is the threshold voltage of the transistor TN 1 , V T  is the thermal voltage of the transistors, V STN1  is the source potential of the transistor TN 1  and V DTN1  is the drain potential of the transistor TN 1 . 
     For the transistor TN 2 , it may also be written that the current i is equal to: 
     
       
         
           
             
               
                 
                   i 
                   = 
                   
                     
                       β 
                       
                         TN 
                          
                         
                             
                         
                          
                         2 
                       
                     
                      
                     
                       J 
                       
                         D 
                          
                         
                             
                         
                          
                         0 
                       
                     
                      
                     
                       exp 
                        
                       
                         ( 
                         
                           
                             
                               V 
                               
                                 GTN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                             - 
                             
                               V 
                               
                                 ThTN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                           
                           
                             nV 
                             T 
                           
                         
                         ) 
                       
                     
                      
                     
                       ( 
                       
                         
                           e 
                           
                             - 
                             
                               
                                 V 
                                 
                                   STN 
                                    
                                   
                                       
                                   
                                    
                                   2 
                                 
                               
                               
                                 V 
                                 T 
                               
                             
                           
                         
                         - 
                         
                           e 
                           
                             
                               V 
                               
                                 DTN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                             
                               V 
                               T 
                             
                           
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     Where β TN2  is the capability of the transistor TN 2 , V GTN2  is the front-face gate Gtop potential of the transistor TN 2 , V ThTN2  is the threshold voltage of the transistor TN 2 , V STN2  is the source potential of the transistor TN 2  and V DTN2  is the drain potential of the transistor TN 2 . 
     Equation (1) may be developed in order to obtain: 
     
       
         
           
             
               
                 
                   i 
                   = 
                   
                     
                       β 
                       
                         TN 
                          
                         
                             
                         
                          
                         1 
                       
                     
                      
                     
                       J 
                       
                         D 
                          
                         
                             
                         
                          
                         0 
                       
                     
                      
                     
                       exp 
                        
                       
                         ( 
                         
                           
                             
                               V 
                               
                                 GTN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                             - 
                             
                               V 
                               
                                 ThTN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                           
                           
                             nV 
                             T 
                           
                         
                         ) 
                       
                     
                      
                     
                       ( 
                       
                         1 
                         - 
                         
                           e 
                           
                             
                               
                                 V 
                                 
                                   STN 
                                    
                                   
                                       
                                   
                                    
                                   1 
                                 
                               
                               
                                 V 
                                 T 
                               
                             
                             - 
                             
                               
                                 V 
                                 
                                   DTN 
                                    
                                   
                                       
                                   
                                    
                                   1 
                                 
                               
                               
                                 V 
                                 T 
                               
                             
                           
                         
                       
                       ) 
                     
                      
                     
                       e 
                       
                         
                           - 
                           
                             V 
                             
                               STN 
                                
                               
                                   
                               
                                
                               1 
                             
                           
                         
                         
                           V 
                           T 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     Now, the terms 
     
       
         
           
             
               e 
               
                 - 
                 
                   
                     V 
                     
                       STN 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   
                     V 
                     T 
                   
                 
               
             
             - 
             
               
                 e 
                 
                   
                     V 
                     
                       DTN 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   
                     V 
                     T 
                   
                 
               
                
               
                   
               
                
               and 
                
               
                   
               
                
               
                 e 
                 
                   - 
                   
                     
                       V 
                       
                         STN 
                          
                         
                             
                         
                          
                         2 
                       
                     
                     
                       V 
                       T 
                     
                   
                 
               
             
             - 
             
               e 
               
                 
                   V 
                   
                     DTN 
                      
                     
                         
                     
                      
                     2 
                   
                 
                 
                   V 
                   T 
                 
               
             
           
         
       
     
     are virtually identical between the transistor TN 1  and the transistor TN 2  with a cascode assembly (described below), and very close without a cascode assembly. It is therefore possible to combine equations (2) and (3) to obtain the following development: 
     
       
         
           
             
               
                 
                   
                     
                       β 
                       
                         TN 
                          
                         
                             
                         
                          
                         1 
                       
                     
                      
                     
                       J 
                       
                         D 
                          
                         
                             
                         
                          
                         0 
                       
                     
                      
                     
                       exp 
                        
                       
                         ( 
                         
                           
                             
                               V 
                               
                                 GTN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                             - 
                             
                               V 
                               
                                 ThTN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                           
                           
                             nV 
                             T 
                           
                         
                         ) 
                       
                     
                      
                     
                       e 
                       
                         - 
                         
                           
                             V 
                             
                               STN 
                                
                               
                                   
                               
                                
                               1 
                             
                           
                           
                             V 
                             T 
                           
                         
                       
                     
                   
                   = 
                   
                     
                       β 
                       
                         TN 
                          
                         
                             
                         
                          
                         2 
                       
                     
                      
                     
                       J 
                       
                         D 
                          
                         
                             
                         
                          
                         0 
                       
                     
                      
                     
                       exp 
                        
                       
                         ( 
                         
                           
                             
                               V 
                               
                                 GTN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                             - 
                             
                               V 
                               
                                 ThTN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                           
                           
                             nV 
                             T 
                           
                         
                         ) 
                       
                     
                      
                     
                       e 
                       
                         - 
                         
                           
                             V 
                             
                               STN 
                                
                               
                                   
                               
                                
                               2 
                             
                           
                           
                             V 
                             T 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     Since the source of the transistor TN 1  is connected to the electrical ground, the potential V STN1  of the source of the transistor TN 1  is zero. In addition, the potential V STN2  of the source of the transistor TN 2  has the value V R . Equation (4) becomes: 
     
       
         
           
             
               
                 
                   
                     
                       β 
                       
                         TN 
                          
                         
                             
                         
                          
                         1 
                       
                     
                      
                     
                       exp 
                        
                       
                         ( 
                         
                           
                             
                               V 
                               
                                 GTN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                             - 
                             
                               V 
                               
                                 ThTN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                           
                           
                             nV 
                             T 
                           
                         
                         ) 
                       
                     
                   
                   = 
                   
                     
                       β 
                       
                         TN 
                          
                         
                             
                         
                          
                         2 
                       
                     
                      
                     
                       exp 
                        
                       
                         ( 
                         
                           
                             
                               V 
                               
                                 GTN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                             - 
                             
                               V 
                               
                                 ThTN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                           
                           
                             nV 
                             T 
                           
                         
                         ) 
                       
                     
                      
                     
                       e 
                       
                         
                           - 
                           
                             V 
                             R 
                           
                         
                         
                           V 
                           T 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       β 
                       
                         TN 
                          
                         
                             
                         
                          
                         1 
                       
                     
                     
                       β 
                       
                         TN 
                          
                         
                             
                         
                          
                         2 
                       
                     
                   
                   = 
                   
                     
                       exp 
                        
                       
                         ( 
                         
                           - 
                           
                             
                               
                                 V 
                                 
                                   GTN 
                                    
                                   
                                       
                                   
                                    
                                   1 
                                 
                               
                               - 
                               
                                 V 
                                 
                                   ThTN 
                                    
                                   
                                       
                                   
                                    
                                   1 
                                 
                               
                             
                             
                               nV 
                               T 
                             
                           
                         
                         ) 
                       
                     
                      
                     
                       exp 
                        
                       
                         ( 
                         
                           - 
                           
                             
                               
                                 V 
                                 
                                   GTN 
                                    
                                   
                                       
                                   
                                    
                                   2 
                                 
                               
                               - 
                               
                                 V 
                                 
                                   ThTN 
                                    
                                   
                                       
                                   
                                    
                                   2 
                                 
                               
                             
                             
                               nV 
                               T 
                             
                           
                         
                         ) 
                       
                     
                      
                     
                       e 
                       
                         
                           - 
                           
                             V 
                             R 
                           
                         
                         
                           V 
                           T 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
             
               
                 
                   
                     ln 
                      
                     
                       ( 
                       
                         
                           β 
                           
                             TN 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                         
                           β 
                           
                             TN 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                       
                       ) 
                     
                   
                   = 
                   
                     
                       - 
                       
                         
                           
                             V 
                             
                               GTN 
                                
                               
                                   
                               
                                
                               1 
                             
                           
                           - 
                           
                             V 
                             
                               ThTN 
                                
                               
                                   
                               
                                
                               1 
                             
                           
                         
                         
                           nV 
                           T 
                         
                       
                     
                     + 
                     
                       ( 
                       
                         
                           
                             V 
                             
                               GTN 
                                
                               
                                   
                               
                                
                               2 
                             
                           
                           - 
                           
                             V 
                             
                               ThTN 
                                
                               
                                   
                               
                                
                               2 
                             
                           
                         
                         
                           nV 
                           T 
                         
                       
                       ) 
                     
                     - 
                     
                       
                         V 
                         R 
                       
                       
                         V 
                         T 
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
             
               
                 
                   
                     ln 
                      
                     
                       ( 
                       
                         
                           β 
                           
                             TN 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                         
                           β 
                           
                             TN 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                       
                       ) 
                     
                   
                   = 
                   
                     
                       
                         V 
                         
                           GTN 
                            
                           
                               
                           
                            
                           2 
                         
                       
                       - 
                       
                         V 
                         
                           GTN 
                            
                           
                               
                           
                            
                           1 
                         
                       
                       + 
                       
                         V 
                         
                           ThTN 
                            
                           
                               
                           
                            
                           1 
                         
                       
                       - 
                       
                         V 
                         
                           ThTN 
                            
                           
                               
                           
                            
                           2 
                         
                       
                       - 
                       
                         nV 
                         r 
                       
                     
                     
                       nV 
                       T 
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
             
               
                 
                   
                     V 
                     R 
                   
                   = 
                   
                     
                       
                         V 
                         T 
                       
                        
                       
                         ln 
                          
                         
                           ( 
                           
                             
                               β 
                               
                                 TN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                             
                               β 
                               
                                 TN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                           
                           ) 
                         
                       
                     
                     + 
                     
                       
                         
                           V 
                           
                             GTN 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                         - 
                         
                           V 
                           
                             GTN 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                       
                       n 
                     
                     + 
                     
                       
                         
                           V 
                           
                             ThTN 
                              
                             
                                 
                             
                              
                             1 
                           
                         
                         - 
                         
                           V 
                           
                             ThTN 
                              
                             
                                 
                             
                              
                             2 
                           
                         
                       
                       n 
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
     Since the gates of the transistors TN 1  and TN 2  are connected to one another, their potential difference (V GTN2 −V GTN1 ) is zero. The difference between the threshold voltages of the two transistors TN 1  and TN 2  will be denoted ΔV th , where ΔV th =V ThTN2 −V ThTN1 . Equation (9) therefore becomes: 
     
       
         
           
             
               
                 
                   
                     V 
                     R 
                   
                   = 
                   
                     
                       
                         V 
                         T 
                       
                        
                       
                         ln 
                          
                         
                           ( 
                           
                             
                               β 
                               
                                 TN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                             
                               β 
                               
                                 TN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                           
                           ) 
                         
                       
                     
                     - 
                     
                       
                         Δ 
                          
                         
                             
                         
                          
                         
                           V 
                           th 
                         
                       
                       n 
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
     Now, according to the thesis by Alyssa Bonnoit, “Reducing power using body biasing in microprocessors with dynamic voltage/frequency scaling”, the thesis by Jean-Philippe Noel, “Optimisation de dispositifs FDSOI pour la gestion de la consommation et de la vitesse: application aux nnennoire et fonctions logiques” [Optimization of FDSOI devices for managing consumption and speed: application to memory and logic functions] and the presentation by Andreia Cathelin “Analog/RF design techniques in 28 nm FDSOI technology” from  2017  at the SOI Industry Consortium, it may be written that ΔV Th =α(V BBN2_fixe −V BBN2 +V R ), where α is a real. 
     Equation (10) therefore becomes: 
     
       
         
           
             
               
                 
                   
                     V 
                     R 
                   
                   = 
                   
                     
                       
                         V 
                         T 
                       
                        
                       
                         ln 
                          
                         
                           ( 
                           
                             
                               β 
                               
                                 TN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                             
                               β 
                               
                                 TN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                           
                           ) 
                         
                       
                     
                     - 
                     
                       
                         n 
                          
                         
                           ( 
                           
                             
                               - 
                               
                                 V 
                                 
                                   BBN 
                                    
                                   
                                       
                                   
                                    
                                   2 
                                 
                               
                             
                             + 
                             
                               V 
                               R 
                             
                             + 
                             
                               V 
                               
                                 BBN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                           
                           ) 
                         
                       
                       n 
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       V 
                       R 
                     
                      
                     
                       ( 
                       
                         
                           n 
                           + 
                           a 
                         
                         n 
                       
                       ) 
                     
                   
                   = 
                   
                     
                       
                         V 
                         T 
                       
                        
                       
                         ln 
                          
                         
                           ( 
                           
                             
                               β 
                               
                                 TN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                             
                               β 
                               
                                 TN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                           
                           ) 
                         
                       
                     
                     - 
                     
                       
                         aV 
                         
                           BBN 
                            
                           
                               
                           
                            
                           2 
                         
                       
                       n 
                     
                     + 
                     
                       
                         α 
                          
                         
                           ( 
                           
                             V 
                             
                               BBN 
                                
                               
                                   
                               
                                
                               2 
                             
                           
                           ) 
                         
                       
                       n 
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
             
               
                 
                   
                     V 
                     R 
                   
                   = 
                   
                     
                       
                         V 
                         T 
                       
                        
                       
                         n 
                         
                           n 
                           + 
                           α 
                         
                       
                        
                       
                         ln 
                          
                         
                           ( 
                           
                             
                               β 
                               
                                 TN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                             
                               β 
                               
                                 TN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                           
                           ) 
                         
                       
                     
                     + 
                     
                       
                         α 
                          
                         
                           ( 
                           
                             
                               V 
                               
                                 BBN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                             - 
                             
                               V 
                               
                                 BBN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                               
                             
                           
                           ) 
                         
                       
                       
                         n 
                         + 
                         α 
                       
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
     It is observed from equation (13) that the potential V R  is linked to the potential difference V BBN2 −V BBN1  by a linear relationship in the second term of the equation. 
     The term 
     
       
         
           
             
               V 
               T 
             
              
             
               n 
               
                 n 
                 + 
                 α 
               
             
              
             
               ln 
                
               
                 ( 
                 
                   
                     β 
                     
                       TN 
                        
                       
                           
                       
                        
                       2 
                     
                   
                   
                     β 
                     
                       TN 
                        
                       
                           
                       
                        
                       1 
                     
                   
                 
                 ) 
               
             
           
         
       
     
     is zero in front of the term 
     
       
         
           
             
               α 
                
               
                 ( 
                 
                   
                     V 
                     
                       BBN 
                        
                       
                           
                       
                        
                       2 
                     
                   
                   - 
                   
                     V 
                     
                       BBN 
                        
                       
                           
                       
                        
                       1 
                     
                   
                 
                 ) 
               
             
             
               n 
               + 
               α 
             
           
         
       
     
     if the W/L ratios of the transistors TN 1  and TN 2  are identical. Equation (13) then becomes: 
     
       
         
           
             
               
                 
                   
                     V 
                     R 
                   
                   = 
                   
                     
                       α 
                        
                       
                         ( 
                         
                           
                             V 
                             
                               BBN 
                                
                               
                                   
                               
                                
                               2 
                             
                           
                           - 
                           
                             V 
                             
                               BBN 
                                
                               
                                   
                               
                                
                               1 
                             
                           
                         
                         ) 
                       
                     
                     
                       n 
                       + 
                       α 
                     
                   
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
           
         
       
     
     This equation 14 makes it possible to clearly observe that the proposed circuit readily makes it possible to form a voltage divider, the division factor being equal to 
     
       
         
           
             
               α 
               
                 n 
                 + 
                 α 
               
             
             . 
           
         
       
     
     Generically speaking, it is observed that equation (13) consists of two terms A+B, where A and B are defined as follows: 
     
       
         
           
             A 
             = 
             
               
                 V 
                 T 
               
                
               
                 n 
                 
                   n 
                   + 
                   α 
                 
               
                
               
                 ln 
                  
                 
                   ( 
                   
                     
                       β 
                       
                         TN 
                          
                         
                             
                         
                          
                         2 
                       
                     
                     
                       β 
                       
                         TN 
                          
                         
                             
                         
                          
                         1 
                       
                     
                   
                   ) 
                 
               
             
           
         
       
       
         
           
             B 
             = 
             
               
                 a 
                  
                 
                   ( 
                   
                     
                       V 
                       
                         BBN 
                          
                         
                             
                         
                          
                         2 
                       
                     
                     - 
                     
                       V 
                       
                         BBN 
                          
                         
                             
                         
                          
                         1 
                       
                     
                   
                   ) 
                 
               
               
                 n 
                 + 
                 α 
               
             
           
         
       
     
     By choosing different transistors TN 1  and TN 2  (therefore having different W/L ratios), it is possible to introduce temperature compensation, as is explained below. However, even if the W/L ratios of the transistors TN 1  and TN 2  are chosen to be different, in practice slightly different (for example 10% or even 20% at most, the percentage being understood with respect to the greatest W/L value), the first term A will often be lower than the term B if the potentials V BBN2  and V BBN1  are significantly different. It will be noted that the term A may be positive or negative depending on whether the transistor TN 2  is respectively larger or smaller than the transistor TN 1 . 
     By way of comparison, if the circuit of  FIG. 3  were to be used as in the prior art to form a current source, with identical back-gate potentials for V BBN2  and V BBN1 , there would be a ratio of 1 to 8 between the sizes of the transistors TN 1  and TN 2  so as to have a sufficient voltage across the terminals of the resistor. The term B would then be equal to 0 and the voltage V R  would be obtained only using the term A, using very significantly different geometries for TN 1  and TN 2  so that the term A is not too small. On the other hand, in a voltage divider circuit according to the present invention, more preference will be given to the term B by virtue of the input voltage, expressed by different potentials V BBN2  and V BBN1 . The term A is introduced only if it is desired to compensate temperature variations of the resistor. By way of example, for one and the same voltage V R  across the terminals of the resistor, there is a ratio of 11/12 (for understanding: the transistors TN 1  and TN 2  have respectively 11 and 12 elementary fingers) with the circuit of  FIG. 3 , with an input voltage of 2 V (difference between the potentials V BBN2  and V BBN1 ). 
     In addition, if one of the potentials V BBN1  or V BBN2  is equal to the standard potential Vss defining the electrical ground, it is possible to simplify equation (14), and consider that the term 
     
       
         
           
             
               α 
                
               
                   
               
                
               
                 V 
                 
                   BBN 
                    
                   
                     ( 
                     
                       2 
                        
                       
                           
                       
                        
                       or 
                        
                       
                           
                       
                        
                       1 
                     
                     ) 
                   
                 
               
             
             
               n 
               + 
               α 
             
           
         
       
     
     is virtually zero. 
     This abovementioned development is applied in the case of operation of the transistors TN 1  and TN 2  in weak inversion mode, in other words in the case of transistors TN 1  and TN 2  in the on state below the threshold. 
     The proposed circuit therefore makes it possible to lower the voltage V R  across the terminals of the resistor R with respect to the input voltage equal to V BBN2 −V BBN1 , while still retaining a low value of the current i in the two branches B 1  and B 2  and a resistor value R that makes it possible to minimize the bulk in terms of silicon surface. 
     It is possible to adopt the same reasoning for transistors TN 1  and TN 2  in strong inversion mode, where V DS &gt;V GS −V T , (and V GS &gt;V T ) where Vim is the voltage between the drain and the source of a transistor, V GS  is the voltage between the front gate and the source of the same transistor and V T  is the thermal voltage of the transistor. The current in the transistors TN 1  and TN 2  is written as follows: 
     
       
         
           
             
               
                 
                   
                       
                   
                    
                   
                     
                       i 
                       = 
                       
                         
                           β 
                           
                             ? 
                           
                         
                          
                         
                           
                             ( 
                             
                               
                                 V 
                                 GS 
                               
                               - 
                               
                                 V 
                                 th 
                               
                             
                             ) 
                           
                           2 
                         
                          
                         
                           ( 
                           
                             1 
                             + 
                             
                               λ 
                                
                               
                                   
                               
                                
                               
                                 V 
                                 DS 
                               
                             
                           
                           ) 
                         
                       
                     
                      
                     
                       
 
                     
                      
                     
                       
                         ? 
                       
                        
                       
                         indicates text missing or illegible when filed 
                       
                     
                   
                 
               
               
                 
                   ( 
                   15 
                   ) 
                 
               
             
           
         
       
     
     Where β is the capability of the transistor, Vis is the voltage between the gate and the source of the transistor, V th , is the threshold voltage of the transistor, Vim is the voltage between the drain and the source of the transistor and λ is the modulation coefficient of the channel length. 
     The current i is identical in both transistors TN 1  and TN 2  due to the current mirror structure, and it is therefore possible to write: 
       β TN1 ( V   STN1   −V   GTN1   −V   ThTN1 ) 2 (1+λ V   DSTN1 )=β TN2 ( V   STN2   −V   GTN2   −V   ThTN2 ) 2 (1+λ V   DSTN2 )  (16)
 
     For the same reasons as above, it is possible to neglect the two terms (1+λV DSTN2 ) and (1+λV DSTN1 ) and obtain: 
     
       
         
           
             
               
                 
                   
                     
                       V 
                       R 
                     
                     = 
                     
                       
                         
                           1 
                           
                             α 
                             + 
                             1 
                           
                         
                          
                         
                           
                             ? 
                           
                           
                             ? 
                           
                         
                          
                         
                           
                             
                               ? 
                             
                             
                               
                                 ? 
                               
                                
                               
                                 
                                   ? 
                                 
                                 
                                   ? 
                                 
                               
                             
                           
                         
                          
                         
                           ( 
                           
                             1 
                             - 
                             
                               1 
                               
                                 K 
                               
                             
                           
                           ) 
                         
                       
                       + 
                       
                         
                           α 
                           
                             α 
                             + 
                             1 
                           
                         
                          
                         
                           ( 
                           
                             
                               V 
                               
                                 BBN 
                                  
                                 
                                     
                                 
                                  
                                 2 
                               
                             
                             - 
                             
                               V 
                               
                                 BBN 
                                  
                                 
                                     
                                 
                                  
                                 1 
                                  
                                 _ 
                               
                             
                           
                           ) 
                         
                       
                     
                   
                    
                   
                     
 
                   
                    
                   
                     
                       ? 
                     
                      
                     
                       indicates text missing or illegible when filed 
                     
                   
                 
               
               
                 
                   ( 
                   17 
                   ) 
                 
               
             
           
         
       
     
     As above, equation (17) may be written in the form V R =A+B where 
     
       
         
           
             
                 
             
              
             
               A 
               = 
               
                 
                   1 
                   
                     α 
                     + 
                     1 
                   
                 
                  
                 
                   
                     ? 
                   
                   
                     ? 
                   
                 
                  
                 
                   
                     
                       ? 
                     
                     
                       
                         ? 
                       
                        
                       
                         
                           ? 
                         
                         
                           ? 
                         
                       
                     
                   
                 
                  
                 
                   ( 
                   
                     1 
                     - 
                     
                       1 
                       
                         K 
                       
                     
                   
                   ) 
                 
               
             
           
         
       
       
         
           
             
                 
             
              
             
               B 
               = 
               
                 
                   α 
                   
                     α 
                     + 
                     1 
                   
                 
                  
                 
                   ( 
                   
                     
                       V 
                       
                         BBN 
                          
                         
                             
                         
                          
                         2 
                       
                     
                     - 
                     
                       V 
                       
                         BBN 
                          
                         
                             
                         
                          
                         1 
                          
                         _ 
                       
                     
                   
                   ) 
                 
               
             
           
         
       
       
         
           
             
               ? 
             
              
             
               indicates text missing or illegible when filed 
             
           
         
       
     
     The ratio between the potential V R  and the difference V BBN2 −V BBN1_  is therefore substantially constant, regardless of the operating state of the transistors TN 1  and TN 2 , since n is close to 1 in FDSOI technology (around 1.2 to 1.6). This may be generalized by inverting the structure as described more precisely with reference to  FIG. 6 . 
     According to one possible embodiment, the transistor TN 2  has a front-face gate G top  width greater than that of the transistor TN 1  (or more precisely W 2 /L 2 &gt;W 1 /L 1 ), thereby making it possible to obtain an effect “proportional to temperature” (PTAT, or “Proportional to Absolute Temperature”) on the current i flowing in the resistor R due to the values of voltages between the gate and the source of the transistors, which increase with temperature. This is explained by the fact that V GS1 −V GS2 =V R , therefore, if the voltages Vis increase, then V R  also increases, and therefore so does the current i. This makes it possible to compensate a positive temperature coefficient of the resistor R, which leads to an effect “inversely proportional to temperature” (CPTAT, or “Conversely Proportional to Absolute Temperature”) on the current i. The two effects CPTAT and PTAT therefore compensate one another, and the ratio between V R  and V BBN2 −V BBN1_fixe  remains stable in terms of temperature. This is also explained by the fact that the coefficient A in formula (14) or (17) as a function of V T  is positive. Since V T  increases with temperature, the variation in A and therefore in V R  will be positive if 
       β TN2 &gt;β TN1  
 
     therefore if the transistor TN 2  is larger than the transistor TN 1 . 
     In the less common case in which the resistor that is used has a negative temperature coefficient, leading to a PTAT effect on the current i, it is possible to compensate this PTAT effect through a CPTAT effect by inversely unbalancing the geometric ratios of the transistors TN 2  and TN 1 , taking W 2 /L 2 &gt;W 1 /L 1 . This is also explained by the fact that the coefficient A will be negative in this case. Since V T  increases with temperature, the variation in A and therefore in V R  will be negative if β TN2 &lt;β TN1 , therefore if the transistor TN 2  is smaller than the transistor TN 1 . 
     The circuit shown in  FIG. 3  may be formed using LVT or RVT transistors. The choice of the type of LVT or RVT transistors for the transistors TN 1  and TN 2  depends on the contemplated application and on the technological manufacturing options for the FDSOI transistors, notably for forming wells Nwell/Pwell placed under the thin oxide layer and forming deep isolation wells for separating a well Pwell from the “solid” substrate, which is generally p-type. As is well known to a person skilled in the art, if the well Nwell or Pwell is biased at a voltage different from the substrate, and possibly from the deep well “Deep Nwell”, it is necessary to ensure that the diodes present between the well/substrate or well/Deep Nwell are not conductive. 
     The voltage divider circuit may be used with input potentials, on V BBN1  and V BBN2 , which are each fixed or variable. 
     The  2  input potentials, and therefore the input voltage, will be fixed if the voltage divider is used for example to generate the equivalent of a “low” reference voltage V R  from a “high” reference voltage, for example supplied by a circuit commonly denoted by the name “bandgap”, such a low reference voltage being able to be used, inter alia, in a reference current source circuit, as is described below with reference to  FIG. 10 . 
     The input voltage may be variable, for example by varying at least one of the two potentials. In the exemplary oscillator circuit described below, one of the potentials, V BBN1 , is fixed and the other potential, V BBN2 , may vary within a given range of values. If the divider circuit were to be connected for example to a sensor supplying a differential signal, the two potentials could be caused to fluctuate. 
     Regardless of the contemplated application of such a voltage divider circuit, the choice of LVT or RVT transistors will be guided primarily by the ease of implementation of the circuit. If at least one of the potentials is negative, it will be easier to use RVT nMOS transistors to be able to negatively bias the PWELL and isolate it from the grounded substrate through a deep well DeepNWELL. On the other hand, if the potentials are more positive, or very weakly negative (higher than −0.6 V), it will be possible to use LVT transistors, since it is possible to bias the well Nwell to these values without making the Nwell/Psubstrate diode conductive. 
     According to one possible embodiment, the transistors TN 1 , TN 2 , TP 1  and TP 2  are transistors comprising a plurality of “fingers”, for example identical fingers; the transistor TN 1  comprises X “fingers” and the transistor TN 2  comprises X+K “fingers”, where X and K are two integers, or vice versa if it is possibly desired for the transistor TN 2  to be smaller than the transistor TN 1 . 
     The advantage of using FDSOI transistors is that of being able to access an expanded range of values in terms of bias potential V BBN2  or V BBN1  for the back gate Gback of the FDSOI transistor TN 2  or TN 1  (or possibly the  2  of them), and thus also of having an expanded range of values in terms of the threshold voltage V th , of the transistor TN 2  and/or TN 1 , as shown in the presentation by Andreia Cathelin “Analog/RF design techniques in 28 nm FDSOI technology” from  2017  given at the SOI Industry Consortium. This leads to a low factor α (equation (11)) and therefore makes it possible to more greatly reduce the potential V R  (or voltage across the terminals of the resistor) with respect to the input voltage V BBN2 −V BBN1 , and thus to more advantageously limit the bulk of the resistor R on the silicon surface when it is desired to use a low-value bias current to limit its consumption. 
       FIG. 4  shows results of simulations performed with the circuit of  FIG. 3 , in which the transistors TN 1  and TN 2  are of the same size and of GO 1  LVT type, that is to say that their back-face insulator thickness makes it possible to withstand a voltage of approximately 1 V on the front gate G top  of the transistor, and the resistor R does not have any temperature coefficient. The potential V BBN1  in this example is equal to that of the ground, therefore zero. The ratio 
     
       
         
           
             
                 
             
              
             
               
                 
                   ? 
                 
                 
                   V 
                   R 
                 
               
               ~ 
               
                 
                   n 
                   + 
                   α 
                 
                 α 
               
             
           
         
       
       
         
           
             
               ? 
             
              
             
               indicates text missing or illegible when filed 
             
           
         
       
     
     is shown on the ordinate and the temperature of the circuit (therefore of all of the transistors in  FIG. 3 ) is shown on the abscissa. It is observed that, for a temperature varying between −45° C. and 150° C., the ratio 
     
       
         
           
             
                 
             
              
             
               
                 
                   ? 
                 
                 
                   V 
                   R 
                 
               
               ~ 
               
                 
                   n 
                   + 
                   α 
                 
                 α 
               
             
           
         
       
       
         
           
             
               ? 
             
              
             
               indicates text missing or illegible when filed 
             
           
         
       
     
     varies between 6.36 and 6.5. It may therefore be considered that this ratio is insensitive to the temperature of the circuit. The ratio 
     
       
         
           
             
                 
             
              
             
               
                 
                   ? 
                 
                 
                   V 
                   R 
                 
               
               ~ 
               
                 
                   n 
                   + 
                   α 
                 
                 α 
               
             
           
         
       
       
         
           
             
               ? 
             
              
             
               indicates text missing or illegible when filed 
             
           
         
       
     
     varies far more greatly in terms of temperature if these simulations are performed with a resistor R having a temperature coefficient. It is for this reason that the transistors TN 1  and TN 2  advantageously have different W/L ratios in order to compensate the temperature variation. 
     The circuit proposed in  FIG. 3  therefore makes it readily possible to form a voltage divider circuit, considering that V BBN2 −V BBN1  is the input voltage and the voltage across the terminals of the load (equal in the present case to V R ) is the output voltage, obtained by dividing V BBN2  by a factor 
     
       
         
           
             
               
                 n 
                 + 
                 α 
               
               α 
             
             &gt; 
             1 
           
         
       
     
     insensitive to temperature, and therefore to form a circuit for generating a reference voltage comprising a non-bulky reference resistor. 
       FIG. 5  shows results of simulations performed with the circuit of  FIG. 3  in which the transistors TN 1  and TN 2  are still of the same size but of GO 2  LVT type. They therefore have an insulator thickness that is twice as great (GO 2  transistors), thereby allowing them to withstand a higher bias voltage on their front gate. The ratio 
     
       
         
           
             
                 
             
              
             
               
                 
                   ? 
                 
                 
                   V 
                   R 
                 
               
               ~ 
               
                 
                   n 
                   + 
                   α 
                 
                 α 
               
             
           
         
       
       
         
           
             
               ? 
             
              
             
               indicates text missing or illegible when filed 
             
           
         
       
     
     is shown on the ordinate and the temperature of the circuit from  FIG. 3  is shown on the abscissa. It is observed that, for a temperature varying between −45° C. and 150° C., the ratio 
     
       
         
           
             
                 
             
              
             
               
                 
                   ? 
                 
                 
                   V 
                   R 
                 
               
               ~ 
               
                 
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               indicates text missing or illegible when filed 
             
           
         
       
     
     varies between 13.02 and 13.12. It may therefore be considered that this ratio is insensitive to the temperature of the circuit, and, as above, that the circuit proposed in  FIG. 3  makes it possible to form a voltage divider circuit that is temperature-insensitive and is able to adapt the division factor 
     
       
         
           
             
                 
             
              
             
               
                 
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                   V 
                   R 
                 
               
               ~ 
               
                 
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               indicates text missing or illegible when filed 
             
           
         
       
     
     by virtue of the thickness of the layer of thin oxide, of BOX oxide and of the silicon film, and thus to have a non-bulky reference resistor in terms of silicon surface. 
       FIG. 6  shows a second embodiment. Two nMOS FDSOI transistors TN 1  and TN 2  are connected to one another so as to form a current mirror. This current mirror is connected to a pair of pMOS FDSOI transistors TP 1  and TP 2 . The source of the pMOS transistor TP 1  is connected to the potential V DD , and the drains of the two transistors TP 1  and TP 2  are connected respectively to the drains of the nMOS transistors TN 1  and TN 2 . The sources of the nMOS transistors TN 1  and TN 2  are connected to an electrical ground. A resistor R is placed between the source of the transistor TP 2  and the potential V DD . The front-face gate of the transistor TN 2  is connected to the source of the transistor TN 2  and the two front-face gates of the transistors TN 1  and TN 2  are connected to one another. The front-face gate of the transistor TP 1  is connected to the source of the transistor TP 1  and the gates of the transistors TP 1  and TP 2  are connected to one another. It will be considered that the transistors TN 1  and TN 2  are identical, and therefore that their W/L ratios are identical. The current i flowing in the two branches B 1  and B 2  formed by the current mirror is identical. 
     The back gates of the four FDSOI transistors TN 1 , TN 2 , TP 1  and TP 2  are biased by an external circuit, not shown, analogous to the circuit CPGA from  FIG. 3 . More specifically, the back gates of the transistors TP 1  and TP 2  are respectively biased at potentials V BBP1  and V BBP2 , while the back-face gates of the other transistors TN 1 , TN 2  are kept at a constant potential, equal in this example to the ground. As will be understood upon reading the explanations below, in order for the circuit to be functional (for a current to flow in the branches), it is necessary for the potentials VBBP 2  and VBBP 1  to be different, in practice significantly different, and for them to be such that V BBP2 &lt;V BBP1 . 
     V R  will be used to denote the potential between the source of the transistor TP 2  and the resistor R. The voltage across the terminals of the resistor R, equal to V DD -V R , has the value i×R, where i is the current flowing in the two branches B 1  and B 2 . 
     It is possible to apply the same reasoning as that given for the circuits in the previous figures, specifically that the current i arriving on the source of the transistor TP 1  may be written as follows: 
     
       
         
           
             
               
                 
                   
                       
                   
                    
                   
                     
                       
                         i 
                         ~ 
                         
                           β 
                           
                             TP 
                              
                             
                                 
                             
                              
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                        
                       
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                         exp 
                         ( 
                         
                           
                             
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                             nV 
                             T 
                           
                         
                         ) 
                       
                        
                       
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                         indicates text missing or illegible when filed 
                       
                     
                   
                 
               
               
                 
                   ( 
                   23 
                   ) 
                 
               
             
           
         
       
     
     And the current i arriving on the source of the transistor TP 2  may be written as follows: 
     
       
         
           
             
               
                 
                   
                       
                   
                    
                   
                     
                       
                         i 
                         ~ 
                         
                           β 
                           
                             TP 
                              
                             
                                 
                             
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                         ? 
                       
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                        
                       
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                         indicates text missing or illegible when filed 
                       
                     
                   
                 
               
               
                 
                   ( 
                   24 
                   ) 
                 
               
             
           
         
       
     
     By combining equations (23) and (24) and based on the abovementioned thesis by Jean-Philippe Noel, a linear relationship linking the potentials V R  and V BBP2  is obtained: 
     
       
         
           
             
               
                 
                   
                       
                   
                    
                   
                     
                       
                         Vdd 
                         - 
                         
                           V 
                           R 
                         
                       
                       = 
                       
                         
                           
                             V 
                             T 
                           
                            
                           
                             n 
                             
                               n 
                               + 
                               α 
                             
                           
                            
                           
                             ln 
                             ( 
                             
                               
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                         + 
                         
                           
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                         indicates text missing or illegible when filed 
                       
                     
                   
                 
               
               
                 
                   ( 
                   25 
                   ) 
                 
               
             
           
         
       
     
     In order, as above, to have a voltage across the terminals of the resistor R (equal to V DD −V R ), it is necessary, in this complementary case in which the input voltage is applied between the back gates of the pMOS, for V BBP2  to be less than V BBP1 , and a voltage divider circuit is readily obtained. This thus makes it possible to reduce the value of the resistor R while still having a low current i value and a high input voltage V BBP1 −V BBP2 . 
     Just as above, equation (25) may be written in the form A+B where: 
     
       
         
           
             
                 
             
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               A 
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     It is then possible to compensate any variation in resistance as a function of temperature by proceeding as described above, by virtue of the presence of the term A in the formula giving the voltage V DD −V R . 
     Moreover, without reiterating all of the developments, in saturated state, an equation (26) equivalent to equation (17) is obtained, in this case too with two terms A and B as described above. 
     
       
         
           
             
               
                 
                   
                     
                       V 
                       dd 
                     
                     - 
                     
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                       R 
                     
                   
                   = 
                   
                     
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                         α 
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                       ( 
                       
                         
                           V 
                           
                             BBP 
                              
                             
                                 
                             
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                             1 
                           
                         
                         - 
                         
                           V 
                           
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                   ( 
                   26 
                   ) 
                 
               
             
           
         
       
     
     The circuits that are shown make it possible to form a voltage divider with a low reference resistance and a low current i. These circuits may have various applications. A first application, described with reference to  FIGS. 7 to 9 , is a circuit for generating a clock signal using a ring oscillator. 
       FIG. 7  shows one example of such a clock generation circuit comprising a circuit delivering a voltage and a current to a ring oscillator. The oscillator comprises three inverters I 1 , I 2  and I 3  that are connected to one another so as to form a loop. More generally, the oscillator may comprise 2N+1 inverters, where N is a natural integer greater than 1. 
     By using the electronic circuits shown in the above figures as a reference voltage/current generator to supply the inverters, it is possible to have a voltage V RO  across the terminals of the reference resistor of a few tens of millivolts and a low current i while still having low reference resistor R ref  values. Specifically, by virtue of the voltage divider formed by the invention, it is possible to lower the voltage V R  flowing in the reference resistor R re f and thus reduce the value thereof. 
     The circuit comprises the same components as those in the circuit from  FIG. 3  and furthermore comprises a transistor TP 5  connected to the transistors TP 1  and TP 2  so as to form a current mirror thus comprising three branches B 1 , B 2  and B 3  in which one and the same current i flows. The sources of the three transistors TP 1 , TP 2  and TP 5  are thus connected to one and the same potential V DD , and their front-face gates are connected to one another. 
     The back-face gate of the transistor TN 2  is connected to a “supply” node having a variable potential V RO , which is the supply potential of the inverters I 1 , I 2  and I 3 . This supply node is connected to the branch B 3  of the current mirror, the inverters therefore being supplied with the current i flowing in the branch B 3 . The branch B 3  and the three inverters therefore perform the role of the circuit CPGA in  FIG. 4 . 
     In this exemplary embodiment, the reference voltage circuit comprises transistors TN 3 , TN 4 , TP 3 , TP 4  and TP 6  configured in a cascode assembly with the transistors TN 1 , TN 2 , TP 1 , TP 2  and TP 5  that are already present. As is known to a person skilled in the art, this assembly makes it possible to ensure virtual equality between the voltages VDS of the transistors of each current mirror. Thus, with reference to the abovementioned equations giving the value of the current i, it is possible to eliminate the components linked to the voltages VDS and to have an “ideal” voltage divider. The pMOS transistors TP 3 , TP 4 , TP 6  and nMOS transistors TN 3 , TN 4  are thus placed respectively in series with the pMOS transistors TP 1 , TP 2 , TP 5  and the nMOS transistors TN 1  and TN 2 . The supply node (potential V RO ) is thus connected to the drain of the pMOS transistor TP 6 . 
     The back-face gates of all of the transistors, except for the transistor TN 2 , are kept at a constant potential equal in this example to the ground. 
     The source of the transistor TP 3  is connected to the drain of the transistor TP 1 , the source of the transistor TP 4  is connected to the drain of the transistor TP 2  and the source of the transistor TP 6  is connected to the drain of the transistor TP 5 . The front-face gates of the transistors TP 3  and TP 4  are connected to one another. The front-face gates of the transistors TP 5  and TP 6  are connected to one another. The front-face gates of the transistors TP 3  and TP 4  are connected to the front-face gates of the transistors TP 1  and TP 2 . The front-face gate of the transistor TP 4  is connected to the drain of the transistor TP 4  and the front-face gates of the transistors TP 5  and TP 6  are connected to the drain of the transistor TP 4 . 
     The drain of the transistor TN 3  is connected to the drain of TP 3  and the drain of TN 4  is connected to the drain of TP 4 . The front-face gates of the transistors TN 3  and TN 4  are connected to one another. The drain of TN 3  is connected to the front-face gate of the transistor TN 3 . The source of the transistor TN 3  is connected to the drain of the transistor TN 1  and the source of the transistor TN 4  is connected to the drain of the transistor TN 2 . 
     The back-face gates of all of the transistors, except for the transistor TN 2 , are kept at a constant potential that is equal in this example. The oscillating frequency f of this oscillator may be written as a function of the equivalent resistance of the ring oscillator, the oscillator constituting a “load” supplied by the branch B 3 ; f=1/(n*C*R equi ). The current flowing through the reference resistor R ref  is equal to that flowing through the equivalent resistance of the ring oscillator R equi , thus i=V R /R ref =V RO /R equi . Furthermore, as described above, V RO =KBB*V Rref , where KBB&gt;0. Thus, V R /R ref =KBB*V Rref /R equi , and R equi =KBB*R ref . The clock generation circuit that is shown forms a control loop for slaving the value of the equivalent resistance R equi  to the value of the reference resistor multiplied by this factor KBB. A significant advantage of this clock generation circuit using a voltage divider according to the present invention in comparison with the clock generation circuit shown in  FIG. 1  is that it requires a lower-value reference resistor than the desired equivalent resistance of the ring oscillator. Thus, since the ratio KBB may be large, easily between 5 and 10, it is possible to use a resistor 5 to 10 times smaller, and therefore a current and therefore a consumption 5 to 10 times smaller than that of the circuit from the prior art. 
       FIG. 8  shows the oscillating frequency f of the ring oscillator of the circuit from  FIG. 7  as a function of temperature, determined by simulations. It is observed that the frequency f is insensitive to the temperature of the circuit, since it varies between 9.04 MHz and 10.06 MHz for a temperature varying between −50° C. and 150° C. This is explained by the fact that the resistance R ref  decreases with temperature but, by having transistors TN 1  and TN 2  such that W 2 /L 2 &gt;W 1 /L 1 , stability of the ratio between V RO  and V R  is achieved, and therefore stability of the oscillating frequency f over a wide temperature range is achieved. 
       FIG. 9  shows a clock generation circuit based on a ring oscillator according to another embodiment of the invention, complementary to the one shown in  FIG. 7 . The oscillator comprises three inverters I 1 , I 2  and I 3  that are connected to one another so as to form a loop. More generally, the oscillator may comprise 2N+1 inverters, where N is a natural integer greater than 1. 
     As above, use is made of a voltage divider circuit with a current mirror to supply the inverters I 1 , I 2  and I 3 . 
     The oscillator thus comprises three nMOS transistors TN 1 , TN 2  and TN 5  connected to one another so as to form a current mirror comprising three branches B 1 , B 2  and B 3  in which one and the same current i flows. The sources of the three transistors TN 1 , TN 2  and TN 5  are thus connected to one and the same potential, which is here an electrical ground. Their front-face gates are connected to one another. 
     There are also two pMOS transistors TP 1  and TP 2  and a resistor R ref  placed between a supply voltage V DD  and the source of the transistor TP 2 . The front-face gates of the transistors TP 1  and TP 2  are connected to one another. The front-face gate of the transistor TP 1  is connected to the drain of TP 1 . 
     The reference voltage circuit also comprises transistors configured in a cascode assembly, with specifically nMOS transistors TN 3 , TN 4  and TN 6  and the pMOS transistors TP 3  and TP 4 . 
     The source of the transistor TN 3  is connected to the drain of the transistor TN 1 , the source of the transistor TN 4  is connected to the drain of the transistor TN 2  and the source of the transistor TN 6  is connected to the drain of the transistor TN 5 . The front-face gates of the transistors TN 1 , TN 2 , TN 3 , TN 4 , TN 5  and TN 6  are connected to one another and are connected to the drain of the transistor TN 4 . 
     The drain of the transistor TP 3  is connected to the drain of TN 3  and the drain of TN 4  is connected to the drain of TP 4 . The front-face gates of TP 3  and TP 4  are connected to one another, connected to the front-face gate of the transistor TP 3 . The source of TP 3  is connected to the drain of TP 1  and the source of TP 4  is connected to the drain of TP 2 . 
     The branch B 3  is connected to a low supply terminal of the ring oscillator. In other words, the inverters of the oscillator are placed between a “high” supply voltage V DD  and a low supply voltage, corresponding in this circuit to a supply node having a potential V RO . This supply node is connected to the branch B 3 , more precisely to the drain of the transistor TN 6 , and is also connected to the back gate of the transistor TP 2 . The branch B 3  and the three inverters therefore perform the role of the circuit CPGA in  FIG. 4 . 
     The back-face gates of all of the transistors, except for the transistor TP 2 , are also kept at a fixed potential, equal for example to the ground. 
       FIG. 10  shows a second application of the circuits according to the invention, specifically a current generator. The generated current i ref  is in this example equal to the current i from the three branches B 1 , B 2  and B 3  of the current mirror formed by the three identical pMOS transistors TP 1 , TP 2  and TP 3 . The current i ref  is then equal to V R /R ref . It may advantageously be substantially insensitive, as explained above. As is well known to a person skilled in the art, it is possible to obtain a current i re /that is a multiple of the current flowing in the branches B 1 /B 2  by providing different transistor sizes between firstly the transistor TP 3  and secondly the transistors TP 1 /TP 2 . If it is desired to have a fixed generated current, it is possible for example to use a reference voltage that is highly stable notably in terms of temperature, for example delivered by a bandgap circuit, in order to bias the back gate of the transistor TN 2  or TN 1 . The other back gates of the other transistors, and notably that of the other transistor TN 1  or TN 2  of the nMOS mirror, are biased to another potential value, advantageously the ground or V DD . The choice of the bias voltage depends notably, as has been explained above, on the type of LVT or RVT transistors used to form the circuit. 
     The generator thus formed is able to generate low current values i re /while still having a low-value and therefore non-bulky reference resistor R re f. Specifically, if the current generator is compared with the one from the prior art illustrated in Figure  ibis , using one and the same reference voltage, it is possible to use a resistance 5 to 10 times lower than that of the circuit from the prior art, by virtue of the voltage division between the reference voltage and the voltage present across the terminals of the resistor. 
       FIG. 11 a    and  FIG. 11 b    show simulation results obtained for the current generator from  FIG. 10 . 
     More specifically,  FIG. 11 a    shows the current i ref  generated as a function of temperature. This varies between 220.8 nA and 221.2 nA for a temperature between −40° C. and 150° C. This current generator is therefore highly stable in terms of temperature. 
       FIG. 11 b    shows the generated current i ref  as a function of the bias potential V BBN2  of the back gate of the transistor TN 2 . It is noted that these two variables are proportional, thereby confirming the fact that the ratio between V R  and V BBN2  is constant regardless of the value of V BBN2 . This ratio therefore remains stable whether the transistors are in weak inversion or strong inversion mode. 
     Generally speaking, it is possible to form an electronic system comprising an electronic circuit according to the invention. 
     Furthermore, the term external circuit has been used to denote an electronic circuit consisting of components other than those present in the two branches B 1  and B 2  and necessary to form an electronic voltage divider circuit according to the present invention. It will however be noted that all “external” circuits described above are in practice able to be formed preferably on one and the same integrated circuit.