Patent Publication Number: US-2023140934-A1

Title: Thread specialization for collaborative data transfer and computation

Description:
FIELD 
     At least one embodiment pertains to processing resources used to execute one or more programs utilizing parallel processing. For example, at least one embodiment pertains to processors or computing systems used to a perform an algorithm using parallel processing, where the algorithm is divided into different portions that are assigned to different processing resources. 
     BACKGROUND 
     Performing computational operations sequentially can use significant memory, time, or computing resources. The amount of memory, time, or computing resources used to perform computation operations can be improved using multiprocessing to perform computational operations in parallel. However, restructuring a task so that it can be performed in parallel can be difficult due to dependencies between individual sub tasks. Therefore, the development of new techniques that improve the ability to perform subordinate tasks in parallel is an important area of research. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    illustrates an example of a matrix multiplication, in accordance with at least one embodiment; 
         FIG.  2    illustrates an example of using multiple threads to perform a matrix multiplication with multiple sequential thread arrays, in accordance with at least one embodiment; 
         FIG.  3    illustrates an example of using two parallel thread arrays to perform a matrix multiplication, in accordance with at least one embodiment; 
         FIG.  4    illustrates an example of using thread groups dedicated to performing different parts of a matrix multiplication, in accordance with at least one embodiment; 
         FIG.  5    illustrates a first example of buffer management when performing a matrix multiplication, in accordance with at least one embodiment; 
         FIG.  6    illustrates a second example of buffer management when performing a matrix multiplication, in accordance with at least one embodiment; 
         FIG.  7    illustrates an example of locking used to prevent parallel execution for parts of a matrix multiplication, in accordance with at least one embodiment; 
         FIG.  8    illustrates an example of tile scheduling, in accordance with at least one embodiment; 
         FIG.  9    illustrates an example of a process that, as a result of being performed by one or more data loading threads, one or more first calculation threads, and one or more second calculation threads, in accordance with at least one embodiment; 
         FIG.  10    illustrates an exemplary data center, in accordance with at least one embodiment; 
         FIG.  11    illustrates a processing system, in accordance with at least one embodiment; 
         FIG.  12    illustrates a computer system, in accordance with at least one embodiment; 
         FIG.  13    illustrates a system, in accordance with at least one embodiment; 
         FIG.  14    illustrates an exemplary integrated circuit, in accordance with at least one embodiment; 
         FIG.  15    illustrates a computing system, according to at least one embodiment; 
         FIG.  16    illustrates an APU, in accordance with at least one embodiment; 
         FIG.  17    illustrates a CPU, in accordance with at least one embodiment; 
         FIG.  18    illustrates an exemplary accelerator integration slice, in accordance with at least one embodiment; 
         FIGS.  19 A- 19 B  illustrate exemplary graphics processors, in accordance with at least one embodiment; 
         FIG.  20 A  illustrates a graphics core, in accordance with at least one embodiment; 
         FIG.  20 B  illustrates a GPGPU, in accordance with at least one embodiment; 
         FIG.  21 A  illustrates a parallel processor, in accordance with at least one embodiment; 
         FIG.  21 B  illustrates a processing cluster, in accordance with at least one embodiment; 
         FIG.  21 C  illustrates a graphics multiprocessor, in accordance with at least one embodiment; 
         FIG.  22    illustrates a graphics processor, in accordance with at least one embodiment; 
         FIG.  23    illustrates a processor, in accordance with at least one embodiment; 
         FIG.  24    illustrates a processor, in accordance with at least one embodiment; 
         FIG.  25    illustrates a graphics processor core, in accordance with at least one embodiment; 
         FIG.  26    illustrates a PPU, in accordance with at least one embodiment; 
         FIG.  27    illustrates a GPC, in accordance with at least one embodiment; 
         FIG.  28    illustrates a streaming multiprocessor, in accordance with at least one embodiment; 
         FIG.  29    illustrates a software stack of a programming platform, in accordance with at least one embodiment; 
         FIG.  30    illustrates a CUDA implementation of a software stack of  FIG.  29   , in accordance with at least one embodiment; 
         FIG.  31    illustrates a ROCm implementation of a software stack of  FIG.  29   , in accordance with at least one embodiment; 
         FIG.  32    illustrates an OpenCL implementation of a software stack of  FIG.  29   , in accordance with at least one embodiment; 
         FIG.  33    illustrates software that is supported by a programming platform, in accordance with at least one embodiment; 
         FIG.  34    illustrates compiling code to execute on programming platforms of  FIGS.  29  - 32   , in accordance with at least one embodiment; 
         FIG.  35    illustrates in greater detail compiling code to execute on programming platforms of  FIGS.  29  -  32   , in accordance with at least one embodiment; 
         FIG.  36    illustrates translating source code prior to compiling source code, in accordance with at least one embodiment; 
         FIG.  37 A  illustrates a system configured to compile and execute CUDA source code using different types of processing units, in accordance with at least one embodiment; 
         FIG.  37 B  illustrates a system configured to compile and execute CUDA source code of  FIG.  37 A  using a CPU and a CUDA-enabled GPU, in accordance with at least one embodiment; 
         FIG.  37 C  illustrates a system configured to compile and execute CUDA source code of  FIG.  37 A  using a CPU and a non-CUDA-enabled GPU, in accordance with at least one embodiment; 
         FIG.  38    illustrates an exemplary kernel translated by CUDA-to-HIP translation tool of  FIG.  37 C , in accordance with at least one embodiment; 
         FIG.  39    illustrates non-CUDA-enabled GPU of  FIG.  37 C  in greater detail, in accordance with at least one embodiment; 
         FIG.  40    illustrates how threads of an exemplary CUDA grid are mapped to different compute units of  FIG.  39   , in accordance with at least one embodiment; and 
         FIG.  41    illustrates how to migrate existing CUDA code to Data Parallel C++ code, in accordance with at least one embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     The present document describes systems and methods that perform General Purpose Matrix multiplication (“GEMM”) and other operations using parallel processing techniques. General Purpose Matrix multiplication (GEMM) is a class of linear algebra operations that is widely used in various domains such as deep learning and high-performance computing. The speed with which GEMM problems can be solved may be accelerated using parallel processing. One method for implementing matrix multiplication on parallel processors is by partitioning the resulting matrix into tiles and using separate threads, thread groups (such as cooperative thread arrays in a GPU), processor cores, or sub-processors to calculate each tile. In one example, to solve an individual tile, a thread (or thread group) needs to go through a prolog(ue) stage for loading input data, a mainloop stage for matrix computation, and an epilog(ue) stage for post-processing and to output the resulting tile. 
     For a number or reasons, the prolog and epilog can be a significant portion of total time, especially when applied to a small GEMM-K size. In some examples, the higher math throughput of a processor makes the prolog and epilog overhead more evident. In other examples, concurrent thread execution leads to phase overlap during the multiple-tile execution that is not deterministic, and therefore the prolog and epilog time are potentially not hidden well due to the synchronized start of each tile thread. This sometimes starves individual prologs and epilogs of memory bandwidth, extending execution of prolog/epilog times. 
     At least one embodiment provides a way to implement GEMM that achieves deterministic prolog, epilog, and mainloop overlap and better prolog and epilog hiding. Instead of having all the threads doing the prolog, mainloop, and epilog steps in a lockstep fashion, specialized threads are used for performing prologs in serial, one after the other, such that the prolog for one tile is completed before another begins. In some examples, threads are organized so that specific groups of threads are allocated to different parts (prolog, mainloop calculation, or epilog) of the GEMM process. In at least one embodiment, specialized groups of threads (or warps of threads) are allocated to predetermined sequences of epilog, mainloop, and prolog functions. In the present document, in most situations, a group of threads can be substituted for a warp of threads. In some examples, each specialized type of thread group performs specialized operations. A cooperative thread array, or CTA, is a group of threads where all threads are guaranteed to be coresident at least at one point in time. Threads in a CTA can be arranged in one or more warps. A warp is group of threads in a symmetric multiprocessor and is usually limited to a finite number of threads (such as 32 threads per warp) based on the implementation of the processor. In one design, multiple cooperative thread arrays (“CTA”) are used, and each CTA has different types of warps, such as data loading warps performing the global memory load, and math warps performing the mainloop and epilog operations: 
     [0052] 1. By decoupling the data loading pipeline (prolog) via data loading warps and computation pipeline (mainloop) via math warps, the data loading warps and math warps can continuously execute their operations across different tiles in a persistent way within one CTA. In some examples, the data loading warps are able to continuously load input data across multiple tiles as long as there are empty buffers to hold them. Thus, performance of the prolog for many tiles can be performed in parallel with a math warp’s mainloop and epilog execution, effectively removing the prolog from the critical path, resulting in overall faster execution.   [0053] 2. In order to enable mainloop and epilog being executed in an overlapped way across tiles, in one design, some examples have concurrent thread groups that work on two different tiles, with one working on current tile’s epilog and the other one starting on next tile’s mainloop.   

     By utilizing fine-grain software synchronization control, at least one example is able to achieve precise overlap among different specialized warps or thread groups. As a result, with the specialized threads being executed persistently in one CTA, the prolog (except in the 1st tile) and epilog across tiles (except in the last tile) can run concurrently with mainloop in a precisely overlapped fashion. Thus, the prolog and epilog times are generally hidden across tiles. 
     Various embodiments may include one or more of the following features: 
     [0056] 1. CTA with Specialized Warps: A CTA can have multiple specialized warps with each type of warp being formed as a warp group. In one design, a CTA has 3 specialized warp groups, with 1 data loading warp group and 2 math warp groups. Other examples may include 1 data loading warp group and 1 math warp group. Some examples are implemented on a graphics processing unit (“GPU), and a data loading warp group loads a global input tile from off-chip memory into on-chip memory buffers (such as shared memory buffers) using a multi-stage pipelining way. A math warp group consumes the buffers by performing the math operations in the mainloop, and post-processes and outputs the result tile in an epilog.   [0057] 2. Resource reconfiguration: Specialized groups of threads may have different resource requirements such as registers per thread. For best performance and efficiency, various examples can leverage a hardware reconfiguration to improve performance by, for example, giving more registers to math thread groups and fewer registers to data loading thread groups.   [0058] 3. Buffer Synchronization between specialized warps or groups of threads: In some examples, data loading warps and Math warps communicate via the on-chip shared memory buffers. A data loading warp is a buffer producer while a math thread is a buffer consumer. For the synchronization of data loading threads and math threads on each shared memory buffer, various examples implement a dedicated barrier (buffer_empty_barrier) for synchronizing on the emptiness of the buffer, and a dedicated barrier (buffer_full_barrier) for synchronizing on the fullness of the buffer. For a data loading groups of threads, to perform the synchronization, one or more examples will first wait on the buffer_empty_barrier, then load its global input tile into the buffer and arrive on buffer_full_barrier. 
   [0059] In some examples, groups of math threads will wait on buffer full barrier of that buffer and then consume the buffer by performing matrix calculations, and then arrive on buffer_empty_barrier. The inter-warp synchronization can be implemented by shared memory barrier mechanism such as the efficient arrive-wait GPU barrier.   
   [0060] 4. Mutual Exclusion Synchronization between groups of threads: In at least one example, math warp groups use mutual exclusion synchronization between executing the mainloop and the epilog. This allows overlap between mainloop and epilog and prevents overlap between two mainloops or two epilogs. By preventing overlap, the warp groups can time-multiplex resources such as shared memory buffers used in the epilog. In such examples, mainloop or epilog can be implemented as a critical region that will be locked when one warp group enters and unlocked when it exits. In at least one embodiment, the mutex synchronization can be implemented with a fast CTA named barrier or an arrive-wait GPU barrier.   [0061] 5. Tile Scheduling: In at least one embodiment, data loading threads and math threads in a thread group continuously work on data loading and computation across the tiles. Each SM has one persistent thread group that processes the output tiles that are being distributed. To schedule all the matrix tiles into all different thread groups, various methods can be used. For example, one method is to statically schedule the tiles across the thread groups in a round-robin way, other methods including dynamic scheduling or hybrid scheduling, etc.   

     With flexible data loading warp and math warps, at least one example provides better programmability, and is more extensible to memory level optimizations than many alternatives. For example, one alternative implementation performs all operations in the same warp and requires careful instruction interleaving for better performance, which complicates program development. By separating the data loading and computation work into dedicated thread groups, it provides better programmability and easier development. Finally, various examples are also compatible with various useful memory level optimizations, including, prefetching residual matrix with dedicated specialized data loading thread groups, or persistent data reuse of on-chip (register file or shared memory) resident input matrix across multiple tiles per thread group. 
       FIG.  1    illustrates an example of a matrix multiplication, in accordance with at least one embodiment. A first matrix  102  having dimensions M by k is multiplied by a second matrix  104  with dimensions k by N. The result of the multiplication is a result matrix  106  with dimensions M by N. 
     In order to process the matrix multiplication in parallel, the result matrix  106  can be broken into tiles that can be calculated independently of each other. In the example illustrated, the result matrix  106  is broken into a first tile  108 , a second tile  110 , a third tile  112 , and a fourth tile  114 . A tile can be a single value, or a grid of values. Various examples can divide the result matrix  106  into any number of tiles based on the number of processors or threads to be used to solve the matrix multiplication. In some examples, the size of each tile can be determined based on the processing capability of a processor assigned to process that tile of results. For example, a faster processor with more memory resources can be assigned a larger tile, and a slower less capable processor can be assigned a smaller tile. 
     A matrix multiplication operation can be initiated using an application programming interface (“API”). In some examples, the API takes two arrays of scalar numbers, and the dimensions of those arrays. Some examples include other parameters such as a scale factor, a buffer location holding one or more of the parameters, and an output buffer location for the result. Some APIs also include information that identifies resources to be used to perform the matrix multiplication such as thread groups, CTA’s, execution contexts, or queues. 
       FIG.  2    illustrates an example of using multiple threads to perform a matrix multiplication with multiple sequential thread arrays, in accordance with at least one embodiment. In one example, a cooperative thread array (or alternatively a thread group) is assigned to process each tile of a matrix multiplication. Each CTA or thread group includes a plurality of threads which can be assigned to perform prologues, epilogs, or calculation portions of a matrix multiplication. In the illustrated example, only one CTA is allowed to be running at a time, and therefore parallelism is limited. 
     In the illustrated example, a first CTA is assigned to a first tile and processes a first prologue  202 , a first calculation  210 , and a first epilog  218 . As depicted and in the example scenario, the first calculation is not able to start until at least a first portion of the first prologue  202  is complete. In addition, since only one CTA is allowed to run at a time, the second prologue  204  is not able to start until the first epilog  218  completes. 
     After the first CTA completes, a second CTA is assigned to a second tile which processes the second prologue  204 , a second calculation  212 , and a second epilog  220 . The second calculation is not able to start until at least a portion of the second prologue  204  is complete. In addition, since only one CTA is allowed to run at a time, the third prologue  206  is not able to start until the second epilog  220  completes. 
     After the second CTA completes, a third CTA is assigned to a third tile which processes the third prologue  206 , a third calculation  214 , and a third epilog  222 . The third calculation is not able to start until at least a portion of the third prologue  206  is complete. In addition, since only one CTA is allowed to run at a time, the fourth prologue  208  is not able to start until the third epilog  222  completes. 
     After the third CTA completes, a fourth CTA is assigned to a fourth tile which processes the fourth prologue  208 , a fourth calculation  216 , and a fourth epilog  224 . The fourth calculation is not able to start until at least a portion of the fourth prologue  208  is complete. As can be seen in  FIG.  2   , there is limited parallelism between different phases of the solution, and only a portion of the prolog can be performed in parallel with calculation. 
       FIG.  3    illustrates an example of using two parallel thread arrays to perform a matrix multiplication, in accordance with at least one embodiment. The example illustrated demonstrates how the previous example can be scaled when more than one concurrent CTA is supported. In the example shown, a first CTA is used to process tiles 1 and 3, and the second CTA is used to process tiles 2 and 4. 
     The first CTA begins by processing the prolog of tile one  302  and begins the calculation of tile one  310  before the prolog completes. The epilog of tile one  318  follows the calculation, and the prolog of tile three  306  follows the epilog of tile one  318 . The cycle continues with the calculation of tile three  314  and the epilog of tile three  322 . 
     The second CTA begins by processing the prolog of tile two  304  and begins the calculation of tile two  312  before the prolog completes. The epilog of tile two  320  follows the calculation, and the prolog of tile four  308  follows the epilog of tile two  320 . The cycle continues with the calculation of tile four  316  and the epilog of tile four  324 . 
     The approach illustrated in  FIG.  3    shows that, although more thread groups are used, calculation cannot occur until at least a minimal portion of the prolog is finished. There is no overlap between prolog and calculation, or between epilog and calculation. In fact, some examples of this structure may exhibit degraded performance because more prologs are performed in parallel. These complete with each other for limited memory bandwidth, and therefore can extend the amount of time required before any of the prologs are sufficiently complete to allow calculations to begin. A similar effect can occur in the calculation stage where many calculations for many different tiles occur at once, competing for available calculation resources and therefore delaying when epilog processing can begin. These effects are illustrated by the extended times for prolog and epilog blocks in  FIG.  3   . 
       FIG.  4    illustrates an example of using thread groups dedicated to performing different parts of a matrix multiplication, in accordance with at least one embodiment. In the example illustrated in  FIG.  4   , a single CTA is divided into three groups of threads; a group of data loading threads that perform epilogs, a first group of calculation or math threads that determine half of the tiles of a result, and a second group of calculation threads that determine the other half of the tiles of the result. 
     In at least one example, work performed by the various thread groups is arranged in a way to increase parallelism between prolog, calculation, and epilog portions of the matrix multiplication. The data loading threads perform prologues for the various tiles in serial, which means that the prolog for a given tile is completed before another prologue for different tile is started. In some examples, multiple threads are used to complete each prologue, but the prolog of only one tile is worked on at a time. In the illustrated example, the data loading threads completes a first prologue  402  followed by a second prologue  404  followed by third prologue  406  followed by a fourth prologue  408 . In some embodiments, the number of tile prologues that can be performed in parallel is more than one but is limited to a threshold number. The threshold number can be based on available processing resources such as a memory bandwidth limiting transfer between memory of the GPU and system memory. By limiting the number of prologues that can be performed at one time, the amount of time necessary to complete the prolog is reduced and the amount of time before calculation can begin for a given tile is also reduced. 
     The first group of calculation threads calculates half of the tiles of the result, the second group of calculation threads produces the remaining half of the result. In various examples, the result matrix can be divided into any number of tiles of any size, but in the example shown the result is divided into 4 tiles and the first group of calculation threads performs the calculation and epilog portions of the first tile and the third tile, the second group of calculation threads performs the calculation and epilog portions of the second tile and the fourth tile. The calculation and epilog portions of the respective calculation thread groups are interleaved so that the first group of calculation threads performs the first calculation  410  and the first epilog  418 , the second group of calculation threads performs the second calculation  414  and the second epilog  422 , the first group of calculation threads performs the third calculation  412  and the third epilog  420 , and the second group of calculation threads performs the fourth calculation  416  and the fourth epilog  424 . In the example illustrated, the start of each calculation coincides with the completion of a sufficient amount of the corresponding prologue, and epilog of each tile begins after the corresponding calculation is complete. 
     Although the example illustrated uses two calculation thread groups, and four tiles, those skilled in the art will appreciate that these techniques can be adapted with any number of calculation thread groups based on the length of a prologue, the length of an epilog, and the length of the calculation process. In some examples, a barrier, semaphore, or other mechanism for managing a critical section is used to ensure that no two epilogs or no two calculation sections are performed in parallel. In other examples, exact timing of prologues and epilogs can be managed based on availability of shared buffers which are filled by prologues, used by calculation sections, and then emptied by calculations sections or epilogs. 
     By interleaving calculation sections and epilogs as described above, prologues, epilogs, and calculation sections are performed more in parallel. In many examples, this allows for more efficient utilization of processor and memory bandwidth resulting in a shorter overall processing time when performing a matrix multiplication. In general, processing resources are more quickly brought online and prologues and epilogs from different tiles do not compete with each other for limited memory bandwidth. 
       FIG.  5    illustrates a first example of buffer management when performing a matrix multiplication, in accordance with at least one embodiment. In the illustrated example, a set of buffers is shared between tile one and tile three of a matrix multiplication result. A first prologue  502  moves data from memory of a computer system into memory of a GPU where it is worked on by a set of calculation threads performing a first calculation  504 . The calculation itself is divided into multiple portions and upon completion of each portion, a corresponding portion of the buffer is emptied, and the signal sent to a prologue  506  associated with the third tile. As the third prologue  506  refills the buffers, a calculation  508  associated with the third tile is signaled and the calculation of each buffer portion is performed. 
     In the example illustrated in  FIG.  5   , execution of the calculation and prologue portions is controlled by buffer full and buffer empty signals so that calculation begins as soon the associated data is made available to the calculation task in the group of calculation threads. In addition, the start of the next prologue is controlled so that it does not start until buffer space is available to hold the data. 
       FIG.  6    illustrates a second example of buffer management when performing a matrix multiplication, in accordance with at least one embodiment. In the illustrated example, a set of buffers is shared between tile two and tile four of a matrix multiplication result. A first prologue  602  moves data from memory of a computer system into memory of a GPU where it is worked on by a set of calculation threads performing a first calculation  604 . The calculation itself is divided into multiple portions and upon completion of each portion, a corresponding portion of the buffer is emptied, and the signal sent to a prologue  606  associated with the fourth tile. As the fourth prologue  606  refills the buffers, a calculation  608  associated with the fourth tile receives a signal and the calculation of each buffer portion is performed. 
     In the example illustrated in  FIG.  6   , execution of the calculation and prologue portions is controlled by buffer full and buffer empty signals so that calculation begins as soon the associated data is made available to the calculation task in the group of calculation threads. In addition, the start of the next prologue is controlled so that it does not start until buffer space is available to hold the data. 
       FIG.  7    illustrates an example of locking used to prevent parallel execution for parts of a matrix multiplication, in accordance with at least one embodiment. In some examples, a locking mechanism is used to prevent parallel execution between calculation sections and/or epilogs so that two sections of the same type cannot run at the same time. A variety of mechanisms can be used including barriers, semaphores, flags, blocking calls, or messages. 
     In the example illustrated in  FIG.  7   , two locks are used, one for locking calculation tasks and another for locking epilogs. A first lock named Calc is locked at the beginning of each calculation task and unlocked at the end of each calculation task. A calculation task is blocked if the lock is locked when a locking operation is attempted. In this way only one calculation task can be performed at a time. In the illustrated example, only one or less of calculation tasks  702 ,  704 ,  706 , and  708  can be performed at any one time. A second lock named Epilog can be similarly configured to ensure that only one epilog runs at a time. In the illustrated example, the second lock ensures that only one of epilogs  710 ,  712 ,  714 , and  716  runs at any one time. 
       FIG.  8    illustrates an example of tile scheduling, in accordance with at least one embodiment. In the illustrated example, four thread groups or CTAs running on an GPU  802  are scheduled with static scheduling to perform a matrix multiplication. Each thread group is running on a dedicated symmetric multiprocessor (“SM”) of a graphics processing unit (“GPU”). A first SM  804  processes a first tile  812 , a fifth tile  820 , and a ninth tile  828 . A second SM  806  processes a second the tile  814 , a sixth tile  822 , and a tenth file  830 . A third SM  808  processes third tile  816 , a seventh tile  824 , and an eleventh tile  832 . A fourth SM  810  processes a fourth tile  818 , and an eighth tile  826 , and a twelfth tile  834 . 
     In various examples, the processing of each set of tiles dedicated to an SM is accomplished as described above with a set of threads dedicated to processing the prologues, and other threads dedicated to calculation tiles of the result matrix. In other examples, dynamic tile scheduling can be used which distributes tiles to SMs as they become available. 
       FIG.  9    illustrates an example of a process that, as a result of being performed by one or more data loading threads, one or more first calculation threads, and one or more second calculation threads, in accordance with at least one embodiment. In various examples, the one or more data loading threads, one or more first calculation threads, or one or more second calculation threads can be groups of threads such as groups of threads running on a symmetric multiprocessor of a GPU. In some examples threads can be groups of threads such as a warp of threads. 
     The process begins with the one or more data loading threads performing a prolog that loads  902  data for first tile from system memory into memory of a GPU. In some examples, the prolog task may handle other preliminary operations such as transferring data to memory or transmitting data over a computer network so that it’s available by the calculation threads. After performing that prolog for tile one, execution advances to block  904  and the data loading thread sends a signal indicating that the buffer into which the data has been loaded is full and ready for processing. In various examples, the signal can be an indication that the buffer is sufficiently full that processing on the data can begin, or the signal can be an indication that data has been received from a computer network. 
     The signal is received by the one or more first calculation threads at block  906 , and this causes the calculation thread to begin processing the data associated with tile one to produce the associated portion of the result. While this processing is occurring, the data loading thread continues to block  908  where data for the second tile is loaded into memory. Once the data is loaded, execution advances the block  910  and a signal indicating that the buffer for the second tile is full is sent to the second calculation thread. When the signal is received by the second calculation thread at block  912 , the second calculation thread begins processing the data to produce the second tile of the result. 
     After the first calculation thread completes processing the results for the first tile, execution advances to block  914  and a signal is returned to the data loading thread indicating that the data buffer is now empty. Upon receiving the signal, the data loading thread, at block  916 , is able to begin loading the data for tile 3 into the buffer which is now available. After sending the signal, the first calculation thread advances to block  918  and Epilog which moves the result data back to system memory can be performed. Meanwhile, the data loading thread, after filling the buffer  920  with the data for tile 3, again sends a signal  922  the first calculation thread indicating that the buffer contains data for processing. The first calculation thread receives the signal at block  922  and processes the data to produce the result for tile 3. 
     The second calculation thread, after processing the result for tile two, generates a signal at block  928  that indicates that its buffer is now available. The data loading thread receives the signal at block  924  and begins loading tile for data into the buffer which is now available. Similar to what occurs in the first calculation thread, the second calculation thread processes the epilogue for tile two at block  930  while the data loading thread refills the buffer with data for tile four. Once the data for tile four has been obtained, the data loading thread advances to block  926  where a signal is sent to the second calculation thread indicating that the buffer now contains the necessary information for tile four. At block  932 , the second calculation thread processes this information to produce the result for tile four. 
     The above pattern is repeated by both the first calculation thread and second calculation thread as illustrated with the first calculation thread signaling that it’s buffer is empty at  934  and processing the epilogue at block  936 . The second calculation thread indicates that it’s buffer is empty at  938 , and processes the fourth epilogue at block  940 . The data loading thread that receives these messages receives the next block of tile data in parallel, sends appropriate signals to the appropriate threads causing the next tile to be calculated and so on. 
     In this way, various examples are able to control the interleaving of calculation tasks, prologue tasks, and epilog tasks to improve the efficient use of available processing resources as described above. For example,  FIG.  9    illustrates one mechanism for performing calculations associated with a matrix multiplication that obtain data used by a set of prolog tasks, by performing the first set of tasks in serial using a set of dedicated threads. The calculations are divided into two portions which are performed by dedicated sets of threads, and the buffer messages enforce time-interleaving of the calculations so that processing resources are used more efficiently. 
     In the preceding and following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concepts may be practiced without one or more of these specific details. 
     Data Center 
     A data center such as exemplary data center  1000  can be used to perform a matrix multiplication, or other operation, as described herein. For example, a data center can be used to perform a first set of tasks that obtain data used by a second set of tasks, the first set of tasks performed in serial using a first set of thread, perform a first portion of the second set of tasks in parallel with the first set of tasks using a second set of threads, and perform a second portion of the second set of tasks in parallel with the first set of tasks, the second portion of the second set of tasks is time-interleaved with the first portion of the second set of tasks and performed using a third set of threads. Time-interleaving can be accomplished using buffer fill/empty messages, locking mechanisms, or a combination of both as described above. Some examples use prolog tasks to transfer data between system memory and a multiprocessing system with separate memory such as a GPU with register storage, whereas others may transfer data from one system to a plurality of other processing resources over a network. 
       FIG.  10    illustrates an exemplary data center  1000 , in accordance with at least one embodiment. In at least one embodiment, data center  1000  includes, without limitation, a data center infrastructure layer  1010 , a framework layer  1020 , a software layer  1030  and an application layer  1040 . 
     In at least one embodiment, as shown in  FIG.  10   , data center infrastructure layer  1010  may include a resource orchestrator  1012 , grouped computing resources  1014 , and node computing resources (“node C.R.s”)  1016 ( 1 )- 1016 (N), where “N” represents any whole, positive integer. In at least one embodiment, node C.R.s  1016 ( 1 )- 1016 (N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (“FPGAs”), data processing units (“DPUs”) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid state or disk drives), network input/output (“NW I/O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.s from among node C.R.s  1016 ( 1 )- 1016 (N) may be a server having one or more of above-mentioned computing resources. 
     In at least one embodiment, grouped computing resources  1014  may include separate groupings of node C.R.s housed within one or more racks (not shown), or many racks housed in data centers at various geographical locations (also not shown). Separate groupings of node C.R.s within grouped computing resources  1014  may include grouped compute, network, memory or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.s including CPUs or processors may grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination. 
     In at least one embodiment, resource orchestrator  1012  may configure or otherwise control one or more node C.R.s  1016 ( 1 )- 1016 (N) and/or grouped computing resources  1014 . In at least one embodiment, resource orchestrator  1012  may include a software design infrastructure (“SDI”) management entity for data center  1000 . In at least one embodiment, resource orchestrator  1012  may include hardware, software or some combination thereof. 
     In at least one embodiment, as shown in  FIG.  10   , framework layer  1020  includes, without limitation, a job scheduler  1032 , a configuration manager  1034 , a resource manager  1036  and a distributed file system  1038 . In at least one embodiment, framework layer  1020  may include a framework to support software  1052  of software layer  1030  and/or one or more application(s)  1042  of application layer  1040 . In at least one embodiment, software  1052  or application(s)  1042  may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud and Microsoft Azure. In at least one embodiment, framework layer  1020  may be, but is not limited to, a type of free and open-source software web application framework such as Apache SparkTM (hereinafter “Spark”) that may utilize distributed file system  1038  for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler  1032  may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center  1000 . In at least one embodiment, configuration manager  1034  may be capable of configuring different layers such as software layer  1030  and framework layer  1020 , including Spark and distributed file system  1038  for supporting large-scale data processing. In at least one embodiment, resource manager  1036  may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system  1038  and job scheduler  1032 . In at least one embodiment, clustered or grouped computing resources may include grouped computing resource  1014  at data center infrastructure layer  1010 . In at least one embodiment, resource manager  1036  may coordinate with resource orchestrator  1012  to manage these mapped or allocated computing resources. 
     In at least one embodiment, software  1052  included in software layer  1030  may include software used by at least portions of node C.R.s  1016 ( 1 )- 1016 (N), grouped computing resources  1014 , and/or distributed file system  1038  of framework layer  1020 . One or more types of software may include, but are not limited to, Internet web page search software, e-mail virus scan software, database software, and streaming video content software. 
     In at least one embodiment, application(s)  1042  included in application layer  1040  may include one or more types of applications used by at least portions of node C.R.s  1016 ( 1 )- 1016 (N), grouped computing resources  1014 , and/or distributed file system  1038  of framework layer  1020 . In at least one or more types of applications may include, without limitation, CUDA applications. 
     In at least one embodiment, any of configuration manager  1034 , resource manager  1036 , and resource orchestrator  1012  may implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions may relieve a data center operator of data center  1000  from making possibly bad configuration decisions and possibly avoiding underutilized and/or poor performing portions of a data center. 
     Computer-Based Systems 
     A computer-based system such as processing system  1100  can be used to perform a matrix multiplication, or other operation, as described herein. For example, a processing system can be used to perform a first set of tasks that obtain data used by a second set of tasks, the first set of tasks performed in serial using a first set of thread, perform a first portion of the second set of tasks in parallel with the first set of tasks using a second set of threads, and perform a second portion of the second set of tasks in parallel with the first set of tasks, the second portion of the second set of tasks is time-interleaved with the first portion of the second set of tasks and performed using a third set of threads. Time-interleaving can be accomplished using buffer fill/empty messages, locking mechanisms, or a combination of both as described above. Some examples use prolog tasks to transfer data between system memory and a multiprocessing system such as a GPU, whereas others may transfer data from one system to a plurality of other processing resources over a network. 
     The following figures set forth, without limitation, exemplary computer-based systems that can be used to implement at least one embodiment. 
       FIG.  11    illustrates a processing system  1100 , in accordance with at least one embodiment. In at least one embodiment, processing system  1100  includes one or more processors  1102  and one or more graphics processors  1108 , and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors  1102  or processor cores  1107 . In at least one embodiment, processing system  1100  is a processing platform incorporated within a system-on-a-chip (“SoC”) integrated circuit for use in mobile, handheld, or embedded devices. 
     In at least one embodiment, processing system  1100  can include, or be incorporated within a server-based gaming platform, a game console, a media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, processing system  1100  is a mobile phone, smart phone, tablet computing device or mobile Internet device. In at least one embodiment, processing system  1100  can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In at least one embodiment, processing system  1100  is a television or set top box device having one or more processors  1102  and a graphical interface generated by one or more graphics processors  1108 . 
     In at least one embodiment, one or more processors  1102  each include one or more processor cores  1107  to process instructions which, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores  1107  is configured to process a specific instruction set  1109 . In at least one embodiment, instruction set  1109  may facilitate Complex Instruction Set Computing (“CISC”), Reduced Instruction Set Computing (“RISC”), or computing via a Very Long Instruction Word (“VLIW”). In at least one embodiment, processor cores  1107  may each process a different instruction set  1109 , which may include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core  1107  may also include other processing devices, such as a digital signal processor (“DSP”). 
     In at least one embodiment, processor  1102  includes cache memory (‘cache”)  1104 . In at least one embodiment, processor  1102  can have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor  1102 . In at least one embodiment, processor  1102  also uses an external cache (e.g., a Level 3 (“L3”) cache or Last Level Cache (“LLC”)) (not shown), which may be shared among processor cores  1107  using known cache coherency techniques. In at least one embodiment, register file  1106  is additionally included in processor  1102  which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). In at least one embodiment, register file  1106  may include general-purpose registers or other registers. 
     In at least one embodiment, one or more processor(s)  1102  are coupled with one or more interface bus(es)  1110  to transmit communication signals such as address, data, or control signals between processor  1102  and other components in processing system  1100 . In at least one embodiment interface bus  1110 , in one embodiment, can be a processor bus, such as a version of a Direct Media Interface (“DMI”) bus. In at least one embodiment, interface bus  1110  is not limited to a DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., “PCI,” PCI Express (“PCIe”)), memory buses, or other types of interface buses. In at least one embodiment processor(s)  1102  include an integrated memory controller  1116  and a platform controller hub  1130 . In at least one embodiment, memory controller  1116  facilitates communication between a memory device and other components of processing system  1100 , while platform controller hub (“PCH”)  1130  provides connections to Input/Output (“I/O”) devices via a local I/O bus. 
     In at least one embodiment, memory device  1120  can be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as processor memory. In at least one embodiment memory device  1120  can operate as system memory for processing system  1100 , to store data  1122  and instructions  1121  for use when one or more processors  1102  executes an application or process. In at least one embodiment, memory controller  1116  also couples with an optional external graphics processor  1112 , which may communicate with one or more graphics processors  1108  in processors  1102  to perform graphics and media operations. In at least one embodiment, a display device  1111  can connect to processor(s)  1102 . In at least one embodiment display device  1111  can include one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device  1111  can include a head mounted display (“HMD”) such as a stereoscopic display device for use in virtual reality (“VR”) applications or augmented reality (“AR”) applications. 
     In at least one embodiment, platform controller hub  1130  enables peripherals to connect to memory device  1120  and processor  1102  via a high-speed I/O bus. In at least one embodiment, I/O peripherals include, but are not limited to, an audio controller  1146 , a network controller  1134 , a firmware interface  1128 , a wireless transceiver  1126 , touch sensors  1125 , a data storage device  1124  (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device  1124  can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as PCI, or PCIe. In at least one embodiment, touch sensors  1125  can include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver  1126  can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (“LTE”) transceiver. In at least one embodiment, firmware interface  1128  enables communication with system firmware, and can be, for example, a unified extensible firmware interface (“UEFI”). In at least one embodiment, network controller  1134  can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples with interface bus  1110 . In at least one embodiment, audio controller  1146  is a multi-channel high definition audio controller. In at least one embodiment, processing system  1100  includes an optional legacy I/O controller  1140  for coupling legacy (e.g., Personal System 2 (“PS/2”)) devices to processing system  1100 . In at least one embodiment, platform controller hub  1130  can also connect to one or more Universal Serial Bus (“USB”) controllers  1142  connect input devices, such as keyboard and mouse  1143  combinations, a camera  1144 , or other USB input devices. 
     In at least one embodiment, an instance of memory controller  1116  and platform controller hub  1130  may be integrated into a discreet external graphics processor, such as external graphics processor  1112 . In at least one embodiment, platform controller hub  1130  and/or memory controller  1116  may be external to one or more processor(s)  1102 . For example, in at least one embodiment, processing system  1100  can include an external memory controller  1116  and platform controller hub  1130 , which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with processor(s)  1102 . 
       FIG.  12    illustrates a computer system  1200 , in accordance with at least one embodiment. In at least one embodiment, computer system  1200  may be a system with interconnected devices and components, an SOC, or some combination. In at least on embodiment, computer system  1200  is formed with a processor  1202  that may include execution units to execute an instruction. In at least one embodiment, computer system  1200  may include, without limitation, a component, such as processor  1202  to employ execution units including logic to perform algorithms for processing data. In at least one embodiment, computer system  1200  may include processors, such as PENTIUM® Processor family, XeonTM, Itanium®, XScaleTM and/or StrongARMTM, Intel® Core™ , or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and like) may also be used. In at least one embodiment, computer system  1200  may execute a version of WINDOWS’ operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux for example), embedded software, and/or graphical user interfaces, may also be used. 
     In at least one embodiment, computer system  1200  may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (DSP), an SoC, network computers (“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system that may perform one or more instructions. 
     In at least one embodiment, computer system  1200  may include, without limitation, processor  1202  that may include, without limitation, one or more execution units  1208  that may be configured to execute a Compute Unified Device Architecture (“CUDA”) (CUDA® is developed by NVIDIA Corporation of Santa Clara, CA) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in a CUDA programming language. In at least one embodiment, computer system  1200  is a single processor desktop or server system. In at least one embodiment, computer system  1200  may be a multiprocessor system. In at least one embodiment, processor  1202  may include, without limitation, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In at least one embodiment, processor  1202  may be coupled to a processor bus  1210  that may transmit data signals between processor  1202  and other components in computer system  1200 . 
     In at least one embodiment, processor  1202  may include, without limitation, a Level 1 (“L1”) internal cache memory (“cache”)  1204 . In at least one embodiment, processor  1202  may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor  1202 . In at least one embodiment, processor  1202  may also include a combination of both internal and external caches. In at least one embodiment, a register file  1206  may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and instruction pointer register. 
     In at least one embodiment, execution unit  1208 , including, without limitation, logic to perform integer and floating point operations, also resides in processor  1202 . Processor  1202  may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit  1208  may include logic to handle a packed instruction set  1209 . In at least one embodiment, by including packed instruction set  1209  in an instruction set of a general-purpose processor  1202 , along with associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in a general-purpose processor  1202 . In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using full width of a processor’s data bus for performing operations on packed data, which may eliminate a need to transfer smaller units of data across a processor’s data bus to perform one or more operations one data element at a time. 
     In at least one embodiment, execution unit  1208  may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system  1200  may include, without limitation, a memory  1220 . In at least one embodiment, memory  1220  may be implemented as a DRAM device, an SRAM device, flash memory device, or other memory device. Memory  1220  may store instruction(s)  1219  and/or data  1221  represented by data signals that may be executed by processor  1202 . 
     In at least one embodiment, a system logic chip may be coupled to processor bus  1210  and memory  1220 . In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”)  1216 , and processor  1202  may communicate with MCH  1216  via processor bus  1210 . In at least one embodiment, MCH  1216  may provide a high bandwidth memory path  1218  to memory  1220  for instruction and data storage and for storage of graphics commands, data and textures. In at least one embodiment, MCH  1216  may direct data signals between processor  1202 , memory  1220 , and other components in computer system  1200  and to bridge data signals between processor bus  1210 , memory  1220 , and a system I/O  1222 . In at least one embodiment, system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH  1216  may be coupled to memory  1220  through high bandwidth memory path  1218  and graphics/video card  1212  may be coupled to MCH  1216  through an Accelerated Graphics Port (“AGP”) interconnect  1214 . 
     In at least one embodiment, computer system  1200  may use system I/O  1222  that is a proprietary hub interface bus to couple MCH  1216  to I/O controller hub (“ICH”)  1230 . In at least one embodiment, ICH  1230  may provide direct connections to some I/O devices via a local I/O bus. In at least one embodiment, local I/O bus may include, without limitation, a high-speed I/O bus for connecting peripherals to memory  1220 , a chipset, and processor  1202 . Examples may include, without limitation, an audio controller  1229 , a firmware hub (“flash BIOS”)  1228 , a wireless transceiver  1226 , a data storage  1224 , a legacy I/O controller  1223  containing a user input interface  1225  and a keyboard interface, a serial expansion port  1227 , such as a USB, and a network controller  1234 . Data storage  1224  may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device. 
     In at least one embodiment,  FIG.  12    illustrates a system, which includes interconnected hardware devices or “chips.” In at least one embodiment,  FIG.  12    may illustrate an exemplary SoC. In at least one embodiment, devices illustrated in  FIG.  12    may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system  1200  are interconnected using compute express link (“CXL”) interconnects. 
       FIG.  13    illustrates a system  1300 , in accordance with at least one embodiment. In at least one embodiment, system  1300  is an electronic device that utilizes a processor  1310 . In at least one embodiment, system  1300  may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more on-premise or cloud service providers, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device. 
     In at least one embodiment, system  1300  may include, without limitation, processor  1310  communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor  1310  is coupled using a bus or interface, such as an I 2 C bus, a System Management Bus (“SMBus”), a Low Pin Count (“LPC”) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a USB (versions 1, 2, 3), or a Universal Asynchronous Receiver/Transmitter (“UART”) bus. In at least one embodiment,  FIG.  13    illustrates a system which includes interconnected hardware devices or “chips.” In at least one embodiment,  FIG.  13    may illustrate an exemplary SoC. In at least one embodiment, devices illustrated in  FIG.  13    may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of  FIG.  13    are interconnected using CXL interconnects. 
     In at least one embodiment,  FIG.  13    may include a display  1324 , a touch screen  1325 , a touch pad  1330 , a Near Field Communications unit (“NFC”)  1345 , a sensor hub  1340 , a thermal sensor  1346 , an Express Chipset (“EC”)  1335 , a Trusted Platform Module (“TPM”)  1338 , BIOS/firmware/flash memory (“BIOS, FW Flash”)  1322 , a DSP  1360 , a Solid State Disk (“SSD”) or Hard Disk Drive (“HDD”)  1320 , a wireless local area network unit (“WLAN”)  1350 , a Bluetooth unit  1352 , a Wireless Wide Area Network unit (“WWAN”)  1356 , a Global Positioning System (“GPS”)  1355 , a camera (“USB 3.0 camera”)  1354  such as a USB 3.0 camera, or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”)  1315  implemented in, for example, LPDDR3 standard. These components may each be implemented in any suitable manner. 
     In at least one embodiment, other components may be communicatively coupled to processor  1310  through components discussed above. In at least one embodiment, an accelerometer  1341 , an Ambient Light Sensor (“ALS”)  1342 , a compass  1343 , and a gyroscope  1344  may be communicatively coupled to sensor hub  1340 . In at least one embodiment, a thermal sensor  1339 , a fan  1337 , a keyboard  1336 , and a touch pad  1330  may be communicatively coupled to EC  1335 . In at least one embodiment, a speaker  1363 , a headphones  1364 , and a microphone (“mic”)  1365  may be communicatively coupled to an audio unit (“audio codec and class d amp”)  1362 , which may in turn be communicatively coupled to DSP  1360 . In at least one embodiment, audio unit  1362  may include, for example and without limitation, an audio coder/decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”)  1357  may be communicatively coupled to WWAN unit  1356 . In at least one embodiment, components such as WLAN unit  1350  and Bluetooth unit  1352 , as well as WWAN unit  1356  may be implemented in a Next Generation Form Factor (“NGFF”). 
       FIG.  14    illustrates an exemplary integrated circuit  1400 , in accordance with at least one embodiment. In at least one embodiment, exemplary integrated circuit  1400  is an SoC that may be fabricated using one or more IP cores. In at least one embodiment, integrated circuit  1400  includes one or more application processor(s)  1405  (e.g., CPUs, DPUs), at least one graphics processor  1410 , and may additionally include an image processor  1415  and/or a video processor  1420 , any of which may be a modular IP core. In at least one embodiment, integrated circuit  1400  includes peripheral or bus logic including a USB controller  1425 , a UART controller  1430 , an SPI/SDIO controller  1435 , and an I 2 S/I 2 C controller  1440 . In at least one embodiment, integrated circuit  1400  can include a display device  1445  coupled to one or more of a high-definition multimedia interface (“HDMI”) controller  1450  and a mobile industry processor interface (“MIPI”) display interface  1455 . In at least one embodiment, storage may be provided by a flash memory subsystem  1460  including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller  1465  for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine  1470 . 
       FIG.  15    illustrates a computing system  1500 , according to at least one embodiment; In at least one embodiment, computing system  1500  includes a processing subsystem  1501  having one or more processor(s)  1502  and a system memory  1504  communicating via an interconnection path that may include a memory hub  1505 . In at least one embodiment, memory hub  1505  may be a separate component within a chipset component or may be integrated within one or more processor(s)  1502 . In at least one embodiment, memory hub  1505  couples with an I/O subsystem  1511  via a communication link  1506 . In at least one embodiment, I/O subsystem  1511  includes an I/O hub  1507  that can enable computing system  1500  to receive input from one or more input device(s)  1508 . In at least one embodiment, I/O hub  1507  can enable a display controller, which may be included in one or more processor(s)  1502 , to provide outputs to one or more display device(s)  1510 A. In at least one embodiment, one or more display device(s)  1510 A coupled with I/O hub  1507  can include a local, internal, or embedded display device. 
     In at least one embodiment, processing subsystem  1501  includes one or more parallel processor(s)  1512  coupled to memory hub  1505  via a bus or other communication link  1513 . In at least one embodiment, communication link  1513  may be one of any number of standards based communication link technologies or protocols, such as, but not limited to PCIe, or may be a vendor specific communications interface or communications fabric. In at least one embodiment, one or more parallel processor(s)  1512  form a computationally focused parallel or vector processing system that can include a large number of processing cores and/or processing clusters, such as a many integrated core processor. In at least one embodiment, one or more parallel processor(s)  1512  form a graphics processing subsystem that can output pixels to one of one or more display device(s)  1510 A coupled via I/O Hub  1507 . In at least one embodiment, one or more parallel processor(s)  1512  can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s)  1510 B. 
     In at least one embodiment, a system storage unit  1514  can connect to I/O hub  1507  to provide a storage mechanism for computing system  1500 . In at least one embodiment, an I/O switch  1516  can be used to provide an interface mechanism to enable connections between I/O hub  1507  and other components, such as a network adapter  1518  and/or wireless network adapter  1519  that may be integrated into a platform, and various other devices that can be added via one or more add-in device(s)  1520 . In at least one embodiment, network adapter  1518  can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter  1519  can include one or more of a Wi-Fi, Bluetooth, NFC, or other network device that includes one or more wireless radios. 
     In at least one embodiment, computing system  1500  can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, that may also be connected to I/O hub  1507 . In at least one embodiment, communication paths interconnecting various components in  FIG.  15    may be implemented using any suitable protocols, such as PCI based protocols (e.g., PCIe), or other bus or point-to-point communication interfaces and/or protocol(s), such as NVLink high-speed interconnect, or interconnect protocols. 
     In at least one embodiment, one or more parallel processor(s)  1512  incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (“GPU”). In at least one embodiment, one or more parallel processor(s)  1512  incorporate circuitry optimized for general purpose processing. In at least embodiment, components of computing system  1500  may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processor(s)  1512 , memory hub  1505 , processor(s)  1502 , and I/O hub  1507  can be integrated into an SoC integrated circuit. In at least one embodiment, components of computing system  1500  can be integrated into a single package to form a system in package (“SIP”) configuration. In at least one embodiment, at least a portion of the components of computing system  1500  can be integrated into a multi-chip module (“MCM”), which can be interconnected with other multi-chip modules into a modular computing system. In at least one embodiment, I/O subsystem  1511  and display devices  1510 B are omitted from computing system  1500 . 
     Processing Systems 
     A processing system such as APU  1600  or CPU  1700  can be used to perform a matrix multiplication, or other operation, as described herein. For example, a processing system can be used to perform a first set of tasks that obtain data used by a second set of tasks, the first set of tasks performed in serial using a first set of thread, perform a first portion of the second set of tasks in parallel with the first set of tasks using a second set of threads, and perform a second portion of the second set of tasks in parallel with the first set of tasks, the second portion of the second set of tasks is time-interleaved with the first portion of the second set of tasks and performed using a third set of threads. Time-interleaving can be accomplished using buffer fill/empty messages, locking mechanisms, or a combination of both as described above. Some examples use prolog tasks to transfer data between system memory and a multiprocessing system such as a GPU, whereas others may transfer data from one system to a plurality of other processing resources over a network. 
     The following figures set forth, without limitation, exemplary processing systems that can be used to implement at least one embodiment. 
       FIG.  16    illustrates an accelerated processing unit (“APU”)  1600 , in accordance with at least one embodiment. In at least one embodiment, APU  1600  is developed by AMD Corporation of Santa Clara, CA. In at least one embodiment, APU  1600  can be configured to execute an application program, such as a CUDA program. In at least one embodiment, APU  1600  includes, without limitation, a core complex  1610 , a graphics complex  1640 , fabric  1660 , I/O interfaces  1670 , memory controllers  1680 , a display controller  1692 , and a multimedia engine  1694 . In at least one embodiment, APU  1600  may include, without limitation, any number of core complexes  1610 , any number of graphics complexes  1650 , any number of display controllers  1692 , and any number of multimedia engines  1694  in any combination. For explanatory purposes, multiple instances of like objects are denoted herein with reference numbers identifying the object and parenthetical numbers identifying the instance where needed. 
     In at least one embodiment, core complex  1610  is a CPU, graphics complex  1640  is a GPU, and APU  1600  is a processing unit that integrates, without limitation,  1610  and  1640  onto a single chip. In at least one embodiment, some tasks may be assigned to core complex  1610  and other tasks may be assigned to graphics complex  1640 . In at least one embodiment, core complex  1610  is configured to execute main control software associated with APU  1600 , such as an operating system. In at least one embodiment, core complex  1610  is the master processor of APU  1600 , controlling and coordinating operations of other processors. In at least one embodiment, core complex  1610  issues commands that control the operation of graphics complex  1640 . In at least one embodiment, core complex  1610  can be configured to execute host executable code derived from CUDA source code, and graphics complex  1640  can be configured to execute device executable code derived from CUDA source code. 
     In at least one embodiment, core complex  1610  includes, without limitation, cores  1620 (1)-1620(4) and an L3 cache  1630 . In at least one embodiment, core complex  1610  may include, without limitation, any number of cores  1620  and any number and type of caches in any combination. In at least one embodiment, cores  1620  are configured to execute instructions of a particular instruction set architecture (“ISA”). In at least one embodiment, each core  1620  is a CPU core. 
     In at least one embodiment, each core  1620  includes, without limitation, a fetch/decode unit  1622 , an integer execution engine  1624 , a floating point execution engine  1626 , and an L2 cache  1628 . In at least one embodiment, fetch/decode unit  1622  fetches instructions, decodes such instructions, generates micro-operations, and dispatches separate micro-instructions to integer execution engine  1624  and floating point execution engine  1626 . In at least one embodiment, fetch/decode unit  1622  can concurrently dispatch one micro-instruction to integer execution engine  1624  and another micro-instruction to floating point execution engine  1626 . In at least one embodiment, integer execution engine  1624  executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine  1626  executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit  1622  dispatches micro-instructions to a single execution engine that replaces both integer execution engine  1624  and floating point execution engine  1626 . 
     In at least one embodiment, each core  1620 (i), where i is an integer representing a particular instance of core  1620 , may access L2 cache  1628 (i) included in core  1620 (i). In at least one embodiment, each core  1620  included in core complex  1610 (j), where j is an integer representing a particular instance of core complex  1610 , is connected to other cores  1620  included in core complex  1610 (j) via L3 cache  1630 (j) included in core complex  1610 (j). In at least one embodiment, cores  1620  included in core complex  1610 (j), where j is an integer representing a particular instance of core complex  1610 , can access all of L3 cache  1630 (j) included in core complex  1610 (j). In at least one embodiment, L3 cache  1630  may include, without limitation, any number of slices. 
     In at least one embodiment, graphics complex  1640  can be configured to perform compute operations in a highly-parallel fashion. In at least one embodiment, graphics complex  1640  is configured to execute graphics pipeline operations such as draw commands, pixel operations, geometric computations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex  1640  is configured to execute operations unrelated to graphics. In at least one embodiment, graphics complex  1640  is configured to execute both operations related to graphics and operations unrelated to graphics. 
     In at least one embodiment, graphics complex  1640  includes, without limitation, any number of compute units  1650  and an L2 cache  1642 . In at least one embodiment, compute units  1650  share L2 cache  1642 . In at least one embodiment, L2 cache  1642  is partitioned. In at least one embodiment, graphics complex  1640  includes, without limitation, any number of compute units  1650  and any number (including zero) and type of caches. In at least one embodiment, graphics complex  1640  includes, without limitation, any amount of dedicated graphics hardware. 
     In at least one embodiment, each compute unit  1650  includes, without limitation, any number of SIMD units  1652  and a shared memory  1654 . In at least one embodiment, each SIMD unit  1652  implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each compute unit  1650  may execute any number of thread blocks, but each thread block executes on a single compute unit  1650 . In at least one embodiment, a thread block includes, without limitation, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit  1652  executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize together and communicate via shared memory  1654 . 
     In at least one embodiment, fabric  1660  is a system interconnect that facilitates data and control transmissions across core complex  1610 , graphics complex  1640 , I/O interfaces  1670 , memory controllers  1680 , display controller  1692 , and multimedia engine  1694 . In at least one embodiment, APU  1600  may include, without limitation, any amount and type of system interconnect in addition to or instead of fabric  1660  that facilitates data and control transmissions across any number and type of directly or indirectly linked components that may be internal or external to APU  1600 . In at least one embodiment, I/O interfaces  1670  are representative of any number and type of I/O interfaces (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I/O interfaces  1670  In at least one embodiment, peripheral devices that are coupled to I/O interfaces  1670  may include, without limitation, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, and so forth. 
     In at least one embodiment, display controller AMD92 displays images on one or more display device(s), such as a liquid crystal display (“LCD”) device. In at least one embodiment, multimedia engine  1694  includes, without limitation, any amount and type of circuitry that is related to multimedia, such as a video decoder, a video encoder, an image signal processor, etc. In at least one embodiment, memory controllers  1680  facilitate data transfers between APU  1600  and a unified system memory  1690 . In at least one embodiment, core complex  1610  and graphics complex  1640  share unified system memory  1690 . 
     In at least one embodiment, APU  1600  implements a memory subsystem that includes, without limitation, any amount and type of memory controllers  1680  and memory devices (e.g., shared memory  1654 ) that may be dedicated to one component or shared among multiple components. In at least one embodiment, APU  1600  implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 caches  1728 , L3 cache  1630 , and L2 cache  1642 ) that may each be private to or shared between any number of components (e.g., cores  1620 , core complex  1610 , SIMD units  1652 , compute units  1650 , and graphics complex  1640 ). 
       FIG.  17    illustrates a CPU  1700 , in accordance with at least one embodiment. In at least one embodiment, CPU  1700  is developed by AMD Corporation of Santa Clara, CA. In at least one embodiment, CPU  1700  can be configured to execute an application program. In at least one embodiment, CPU  1700  is configured to execute main control software, such as an operating system. In at least one embodiment, CPU  1700  issues commands that control the operation of an external GPU (not shown). In at least one embodiment, CPU  1700  can be configured to execute host executable code derived from CUDA source code, and an external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, CPU  1700  includes, without limitation, any number of core complexes  1710 , fabric  1760 , I/O interfaces  1770 , and memory controllers  1780 . 
     In at least one embodiment, core complex  1710  includes, without limitation, cores  1720 ( 1 )- 1720 ( 4 ) and an L3 cache  1730 . In at least one embodiment, core complex  1710  may include, without limitation, any number of cores  1720  and any number and type of caches in any combination. In at least one embodiment, cores  1720  are configured to execute instructions of a particular ISA. In at least one embodiment, each core  1720  is a CPU core. 
     In at least one embodiment, each core  1720  includes, without limitation, a fetch/decode unit  1722 , an integer execution engine  1724 , a floating point execution engine  1726 , and an L2 cache  1728 . In at least one embodiment, fetch/decode unit  1722  fetches instructions, decodes such instructions, generates micro-operations, and dispatches separate micro-instructions to integer execution engine  1724  and floating point execution engine  1726 . In at least one embodiment, fetch/decode unit  1722  can concurrently dispatch one micro-instruction to integer execution engine  1724  and another micro-instruction to floating point execution engine  1726 . In at least one embodiment, integer execution engine  1724  executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine  1726  executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit  1722  dispatches micro-instructions to a single execution engine that replaces both integer execution engine  1724  and floating point execution engine  1726 . 
     In at least one embodiment, each core  1720 (i), where i is an integer representing a particular instance of core  1720 , may access L2 cache  1728 (i) included in core  1720 (i). In at least one embodiment, each core  1720  included in core complex  1710 (j), where j is an integer representing a particular instance of core complex  1710 , is connected to other cores  1720  in core complex  1710 ( j ) via L3 cache  1730 (j) included in core complex  1710 ( j ). In at least one embodiment, cores  1720  included in core complex  1710 ( j ), where j is an integer representing a particular instance of core complex  1710 , can access all of L3 cache  1730 (j) included in core complex  1710 ( j ). In at least one embodiment, L3 cache  1730  may include, without limitation, any number of slices. 
     In at least one embodiment, fabric  1760  is a system interconnect that facilitates data and control transmissions across core complexes  1710 ( 1 )- 1710 (N) (where N is an integer greater than zero), I/O interfaces  1770 , and memory controllers  1780 . In at least one embodiment, CPU  1700  may include, without limitation, any amount and type of system interconnect in addition to or instead of fabric  1760  that facilitates data and control transmissions across any number and type of directly or indirectly linked components that may be internal or external to CPU  1700 . In at least one embodiment, I/O interfaces  1770  are representative of any number and type of I/O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I/O interfaces  1770  In at least one embodiment, peripheral devices that are coupled to I/O interfaces  1770  may include, without limitation, displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, and so forth. 
     In at least one embodiment, memory controllers  1780  facilitate data transfers between CPU  1700  and a system memory  1790 . In at least one embodiment, core complex  1710  and graphics complex  1740  share system memory  1790 . In at least one embodiment, CPU  1700  implements a memory subsystem that includes, without limitation, any amount and type of memory controllers  1780  and memory devices that may be dedicated to one component or shared among multiple components. In at least one embodiment, CPU  1700  implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 caches  1728  and L3 caches  1730 ) that may each be private to or shared between any number of components (e.g., cores  1720  and core complexes  1710 ). 
       FIG.  18    illustrates an exemplary accelerator integration slice  1890 , in accordance with at least one embodiment. As used herein, a “slice” comprises a specified portion of processing resources of an accelerator integration circuit. In at least one embodiment, the accelerator integration circuit provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines included in a graphics acceleration module. The graphics processing engines may each comprise a separate GPU. Alternatively, the graphics processing engines may comprise different types of graphics processing engines within a GPU such as graphics execution units, media processing engines (e.g., video encoders/decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module may be a GPU with multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip. 
     An application effective address space  1882  within system memory  1814  stores process elements  1883 . In one embodiment, process elements  1883  are stored in response to GPU invocations  1881  from applications  1880  executed on processor  1807 . A process element  1883  contains process state for corresponding application  1880 . A work descriptor (“WD”)  1884  contained in process element  1883  can be a single job requested by an application or may contain a pointer to a queue of jobs. In at least one embodiment, WD  1884  is a pointer to a job request queue in application effective address space  1882 . 
     Graphics acceleration module  1846  and/or individual graphics processing engines can be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for setting up process state and sending WD  1884  to graphics acceleration module  1846  to start a job in a virtualized environment may be included. 
     In at least one embodiment, a dedicated-process programming model is implementation-specific. In this model, a single process owns graphics acceleration module  1846  or an individual graphics processing engine. Because graphics acceleration module  1846  is owned by a single process, a hypervisor initializes an accelerator integration circuit for an owning partition and an operating system initializes accelerator integration circuit for an owning process when graphics acceleration module  1846  is assigned. 
     In operation, a WD fetch unit  1891  in accelerator integration slice  1890  fetches next WD  1884  which includes an indication of work to be done by one or more graphics processing engines of graphics acceleration module  1846 . Data from WD  1884  may be stored in registers  1845  and used by a memory management unit (“MMU”)  1839 , interrupt management circuit  1847  and/or context management circuit  1848  as illustrated. For example, one embodiment of MMU  1839  includes segment/page walk circuitry for accessing segment/page tables  1886  within OS virtual address space  1885 . Interrupt management circuit  1847  may process interrupt events (“INT”)  1892  received from graphics acceleration module  1846 . When performing graphics operations, an effective address  1893  generated by a graphics processing engine is translated to a real address by MMU  1839 . 
     In one embodiment, a same set of registers  1845  are duplicated for each graphics processing engine and/or graphics acceleration module  1846  and may be initialized by a hypervisor or operating system. Each of these duplicated registers may be included in accelerator integration slice  1890 . Exemplary registers that may be initialized by a hypervisor are shown in Table 1.  
     
       
         
          TABLE 1
           
               
               
             
               
                 Hypervisor Initialized Registers 
               
             
            
               
                 1 
                 Slice Control Register 
               
               
                 2 
                 Real Address (RA) Scheduled Processes Area Pointer 
               
               
                 3 
                 Authority Mask Override Register 
               
               
                 4 
                 Interrupt Vector Table Entry Offset 
               
               
                 5 
                 Interrupt Vector Table Entry Limit 
               
               
                 6 
                 State Register 
               
               
                 7 
                 Logical Partition ID 
               
               
                 8 
                 Real address (RA) Hypervisor Accelerator Utilization Record Pointer 
               
               
                 9 
                 Storage Description Register 
               
            
           
         
       
     
     Exemplary registers that may be initialized by an operating system are shown in Table 2.  
     
       
         
          TABLE 2
           
               
               
             
               
                 Operating System Initialized Registers 
               
             
            
               
                 1 
                 Process and Thread Identification 
               
               
                 2 
                 Effective Address (EA) Context Save/Restore Pointer 
               
               
                 3 
                 Virtual Address (VA) Accelerator Utilization Record Pointer 
               
               
                 4 
                 Virtual Address (VA) Storage Segment Table Pointer 
               
               
                 5 
                 Authority Mask 
               
               
                 6 
                 Work descriptor 
               
            
           
         
       
     
     In one embodiment, each WD  1884  is specific to a particular graphics acceleration module  1846  and/or a particular graphics processing engine. It contains all information required by a graphics processing engine to perform work or it can be a pointer to a memory location where an application has set up a command queue of work to be completed. 
       FIGS.  19 A- 19 B  illustrate exemplary graphics processors, in accordance with at least one embodiment. In at least one embodiment, any of the exemplary graphics processors may be fabricated using one or more IP cores. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processors are for use within an SoC. 
       FIG.  19 A  illustrates an exemplary graphics processor  1910  of an SoC integrated circuit that may be fabricated using one or more IP cores, in accordance with at least one embodiment.  FIG.  19 B  illustrates an additional exemplary graphics processor  1940  of an SoC integrated circuit that may be fabricated using one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, graphics processor  1910  of  FIG.  19 A  is a low power graphics processor core. In at least one embodiment, graphics processor  1940  of  FIG.  19 B  is a higher performance graphics processor core. In at least one embodiment, each of graphics processors  1910 ,  1940  can be variants of graphics processor  1410  of  FIG.  14   . 
     In at least one embodiment, graphics processor  1910  includes a vertex processor  1905  and one or more fragment processor(s)  1915 A- 1915 N (e.g.,  1915 A,  1915 B,  1915 C,  1915 D, through  1915 N- 1 , and  1915 N). In at least one embodiment, graphics processor  1910  can execute different shader programs via separate logic, such that vertex processor  1905  is optimized to execute operations for vertex shader programs, while one or more fragment processor(s)  1915 A- 1915 N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor  1905  performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s)  1915 A- 1915 N use primitive and vertex data generated by vertex processor  1905  to produce a framebuffer that is displayed on a display device. In at least one embodiment, fragment processor(s)  1915 A- 1915 N are optimized to execute fragment shader programs as provided for in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in a Direct 3D API. 
     In at least one embodiment, graphics processor  1910  additionally includes one or more MMU(s)  1920 A- 1920 B, cache(s)  1925 A- 1925 B, and circuit interconnect(s)  1930 A- 1930 B. In at least one embodiment, one or more MMU(s)  1920 A- 1920 B provide for virtual to physical address mapping for graphics processor  1910 , including for vertex processor  1905  and/or fragment processor(s)  1915 A- 1915 N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in one or more cache(s)  1925 A- 1925 B. In at least one embodiment, one or more MMU(s)  1920 A- 1920 B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processor(s)  1405 , image processors  1415 , and/or video processors  1420  of  FIG.  14   , such that each processor  1405 - 1420  can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnect(s)  1930 A- 1930 B enable graphics processor  1910  to interface with other IP cores within an SoC, either via an internal bus of the SoC or via a direct connection. 
     In at least one embodiment, graphics processor  1940  includes one or more MMU(s)  1920 A- 1920 B, caches  1925 A- 1925 B, and circuit interconnects  1930 A- 1930 B of graphics processor  1910  of  FIG.  19 A . In at least one embodiment, graphics processor  1940  includes one or more shader core(s)  1955 A- 1955 N (e.g.,  1955 A,  1955 B,  1955 C,  1955 D,  1955 E,  1955 F, through  1955 N- 1 , and  1955 N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. In at least one embodiment, a number of shader cores can vary. In at least one embodiment, graphics processor  1940  includes an inter-core task manager  1945 , which acts as a thread dispatcher to dispatch execution threads to one or more shader cores  1955 A- 1955 N and a tiling unit  1958  to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches. 
       FIG.  20 A  illustrates a graphics core  2000 , in accordance with at least one embodiment. In at least one embodiment, graphics core  2000  may be included within graphics processor  1410  of  FIG.  14   . In at least one embodiment, graphics core  2000  may be a unified shader core  1955 A- 1955 N as in  FIG.  19 B . In at least one embodiment, graphics core  2000  includes a shared instruction cache  2002 , a texture unit  2018 , and a cache/shared memory  2020  that are common to execution resources within graphics core  2000 . In at least one embodiment, graphics core  2000  can include multiple slices  2001 A- 2001 N or partition for each core, and a graphics processor can include multiple instances of graphics core  2000 . Slices  2001 A- 2001 N can include support logic including a local instruction cache  2004 A- 2004 N, a thread scheduler  2006 A- 2006 N, a thread dispatcher  2008 A- 2008 N, and a set of registers  2010 A- 2010 N. In at least one embodiment, slices  2001 A- 2001 N can include a set of additional function units (“AFUs”)  2012 A- 2012 N, floating-point units (“FPUs”)  2014 A- 2014 N, integer arithmetic logic units (“ALUs”)  2016 - 2016 N, address computational units (“ACUs”)  2013 A- 2013 N, double-precision floating-point units (“DPFPUs”)  2015 A- 2015 N, and matrix processing units (“MPUs”)  2017 A- 2017 N. 
     In at least one embodiment, FPUs  2014 A- 2014 N can perform single-precision (32-bit) and half-precision (16-bit) floating point operations, while DPFPUs  2015 A- 2015 N perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs  2016 A- 2016 N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs  2017 A- 2017 N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. In at least one embodiment, MPUs  2017 - 2017 N can perform a variety of matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix to matrix multiplication (“GEMM”). In at least one embodiment, AFUs  2012 A- 2012 N can perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.). 
       FIG.  20 B  illustrates a general-purpose graphics processing unit (“GPGPU”)  2030 , in accordance with at least one embodiment. In at least one embodiment, GPGPU  2030  is highly-parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU  2030  can be configured to enable highly-parallel compute operations to be performed by an array of GPUs. In at least one embodiment, GPGPU  2030  can be linked directly to other instances of GPGPU  2030  to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU  2030  includes a host interface  2032  to enable a connection with a host processor. In at least one embodiment, host interface  2032  is a PCIe interface. In at least one embodiment, host interface  2032  can be a vendor specific communications interface or communications fabric. In at least one embodiment, GPGPU  2030  receives commands from a host processor and uses a global scheduler  2034  to distribute execution threads associated with those commands to a set of compute clusters  2036 A- 2036 H. In at least one embodiment, compute clusters  2036 A- 2036 H share a cache memory  2038 . In at least one embodiment, cache memory  2038  can serve as a higher-level cache for cache memories within compute clusters  2036 A- 2036 H. 
     In at least one embodiment, GPGPU  2030  includes memory  2044 A- 2044 B coupled with compute clusters  2036 A- 2036 H via a set of memory controllers  2042 A- 2042 B. In at least one embodiment, memory  2044 A- 2044 B can include various types of memory devices including DRAM or graphics random access memory, such as synchronous graphics random access memory (“SGRAM”), including graphics double data rate (“GDDR”) memory. 
     In at least one embodiment, compute clusters  2036 A- 2036 H each include a set of graphics cores, such as graphics core  2000  of  FIG.  20 A , which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for computations associated with CUDA programs. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters  2036 A- 2036 H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations. 
     In at least one embodiment, multiple instances of GPGPU  2030  can be configured to operate as a compute cluster. Compute clusters  2036 A- 2036 H may implement any technically feasible communication techniques for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU  2030  communicate over host interface  2032 . In at least one embodiment, GPGPU  2030  includes an I/O hub  2039  that couples GPGPU  2030  with a GPU link  2040  that enables a direct connection to other instances of GPGPU  2030 . In at least one embodiment, GPU link  2040  is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU  2030 . In at least one embodiment GPU link  2040  couples with a high speed interconnect to transmit and receive data to other GPGPUs  2030  or parallel processors. In at least one embodiment, multiple instances of GPGPU  2030  are located in separate data processing systems and communicate via a network device that is accessible via host interface  2032 . In at least one embodiment GPU link  2040  can be configured to enable a connection to a host processor in addition to or as an alternative to host interface  2032 . In at least one embodiment, GPGPU  2030  can be configured to execute a CUDA program. 
       FIG.  21 A  illustrates a parallel processor  2100 , in accordance with at least one embodiment. In at least one embodiment, various components of parallel processor  2100  may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (“ASICs”), or FPGAs. 
     In at least one embodiment, parallel processor  2100  includes a parallel processing unit  2102 . In at least one embodiment, parallel processing unit  2102  includes an I/O unit  2104  that enables communication with other devices, including other instances of parallel processing unit  2102 . In at least one embodiment, I/O unit  2104  may be directly connected to other devices. In at least one embodiment, I/O unit  2104  connects with other devices via use of a hub or switch interface, such as memory hub  2105 . In at least one embodiment, connections between memory hub  2105  and I/O unit  2104  form a communication link. In at least one embodiment, I/O unit  2104  connects with a host interface  2106  and a memory crossbar  2116 , where host interface  2106  receives commands directed to performing processing operations and memory crossbar  2116  receives commands directed to performing memory operations. 
     In at least one embodiment, when host interface  2106  receives a command buffer via I/O unit  2104 , host interface  2106  can direct work operations to perform those commands to a front end  2108 . In at least one embodiment, front end  2108  couples with a scheduler  2110 , which is configured to distribute commands or other work items to a processing array  2112 . In at least one embodiment, scheduler  2110  ensures that processing array  2112  is properly configured and in a valid state before tasks are distributed to processing array  2112 . In at least one embodiment, scheduler  2110  is implemented via firmware logic executing on a microcontroller. In at least one embodiment, microcontroller implemented scheduler  2110  is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on processing array  2112 . In at least one embodiment, host software can prove workloads for scheduling on processing array  2112  via one of multiple graphics processing doorbells. In at least one embodiment, workloads can then be automatically distributed across processing array  2112  by scheduler  2110  logic within a microcontroller including scheduler  2110 . 
     In at least one embodiment, processing array  2112  can include up to “N” clusters (e.g., cluster  2114 A, cluster  2114 B, through cluster  2114 N). In at least one embodiment, each cluster  2114 A- 2114 N of processing array  2112  can execute a large number of concurrent threads. In at least one embodiment, scheduler  2110  can allocate work to clusters  2114 A- 2114 N of processing array  2112  using various scheduling and/or work distribution algorithms, which may vary depending on the workload arising for each type of program or computation. In at least one embodiment, scheduling can be handled dynamically by scheduler  2110 , or can be assisted in part by compiler logic during compilation of program logic configured for execution by processing array  2112 . In at least one embodiment, different clusters  2114 A- 2114 N of processing array  2112  can be allocated for processing different types of programs or for performing different types of computations. 
     In at least one embodiment, processing array  2112  can be configured to perform various types of parallel processing operations. In at least one embodiment, processing array  2112  is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing array  2112  can include logic to execute processing tasks including filtering of video and/or audio data, performing modeling operations, including physics operations, and performing data transformations. 
     In at least one embodiment, processing array  2112  is configured to perform parallel graphics processing operations. In at least one embodiment, processing array  2112  can include additional logic to support execution of such graphics processing operations, including, but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing array  2112  can be configured to execute graphics processing related shader programs such as, but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit  2102  can transfer data from system memory via I/O unit  2104  for processing. In at least one embodiment, during processing, transferred data can be stored to on-chip memory (e.g., a parallel processor memory  2122 ) during processing, then written back to system memory. 
     In at least one embodiment, when parallel processing unit  2102  is used to perform graphics processing, scheduler  2110  can be configured to divide a processing workload into approximately equal sized tasks, to better enable distribution of graphics processing operations to multiple clusters  2114 A- 2114 N of processing array  2112 . In at least one embodiment, portions of processing array  2112  can be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. In at least one embodiment, intermediate data produced by one or more of clusters  2114 A- 2114 N may be stored in buffers to allow intermediate data to be transmitted between clusters  2114 A- 2114 N for further processing. 
     In at least one embodiment, processing array  2112  can receive processing tasks to be executed via scheduler  2110 , which receives commands defining processing tasks from front end  2108 . In at least one embodiment, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and/or pixel data, as well as state parameters and commands defining how data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler  2110  may be configured to fetch indices corresponding to tasks or may receive indices from front end  2108 . In at least one embodiment, front end  2108  can be configured to ensure processing array  2112  is configured to a valid state before a workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated. 
     In at least one embodiment, each of one or more instances of parallel processing unit  2102  can couple with parallel processor memory  2122 . In at least one embodiment, parallel processor memory  2122  can be accessed via memory crossbar  2116 , which can receive memory requests from processing array  2112  as well as I/O unit  2104 . In at least one embodiment, memory crossbar  2116  can access parallel processor memory  2122  via a memory interface  2118 . In at least one embodiment, memory interface  2118  can include multiple partition units (e.g., a partition unit  2120 A, partition unit  2120 B, through partition unit  2120 N) that can each couple to a portion (e.g., memory unit) of parallel processor memory  2122 . In at least one embodiment, a number of partition units  2120 A- 2120 N is configured to be equal to a number of memory units, such that a first partition unit  2120 A has a corresponding first memory unit  2124 A, a second partition unit  2120 B has a corresponding memory unit  2124 B, and an Nth partition unit  2120 N has a corresponding Nth memory unit  2124 N. In at least one embodiment, a number of partition units  2120 A- 2120 N may not be equal to a number of memory devices. 
     In at least one embodiment, memory units  2124 A- 2124 N can include various types of memory devices, including DRAM or graphics random access memory, such as SGRAM, including GDDR memory. In at least one embodiment, memory units  2124 A- 2124 N may also include 3D stacked memory, including but not limited to high bandwidth memory (“HBM”). In at least one embodiment, render targets, such as frame buffers or texture maps may be stored across memory units  2124 A- 2124 N, allowing partition units  2120 A- 2120 N to write portions of each render target in parallel to efficiently use available bandwidth of parallel processor memory  2122 . In at least one embodiment, a local instance of parallel processor memory  2122  may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory. 
     In at least one embodiment, any one of clusters  2114 A- 2114 N of processing array  2112  can process data that will be written to any of memory units  2124 A- 2124 N within parallel processor memory  2122 . In at least one embodiment, memory crossbar  2116  can be configured to transfer an output of each cluster  2114 A- 2114 N to any partition unit  2120 A- 2120 N or to another cluster  2114 A- 2114 N, which can perform additional processing operations on an output. In at least one embodiment, each cluster  2114 A- 2114 N can communicate with memory interface  2118  through memory crossbar  2116  to read from or write to various external memory devices. In at least one embodiment, memory crossbar  2116  has a connection to memory interface  2118  to communicate with I/O unit  2104 , as well as a connection to a local instance of parallel processor memory  2122 , enabling processing units within different clusters  2114 A- 2114 N to communicate with system memory or other memory that is not local to parallel processing unit  2102 . In at least one embodiment, memory crossbar  2116  can use virtual channels to separate traffic streams between clusters  2114 A- 2114 N and partition units  2120 A- 2120 N. 
     In at least one embodiment, multiple instances of parallel processing unit  2102  can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit  2102  can be configured to inter-operate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and/or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit  2102  can include higher precision floating point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit  2102  or parallel processor  2100  can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and/or embedded systems. 
       FIG.  21 B  illustrates a processing cluster  2194 , in accordance with at least one embodiment. In at least one embodiment, processing cluster  2194  is included within a parallel processing unit. In at least one embodiment, processing cluster  2194  is one of processing clusters  2114 A- 2114 N of  FIG.  21   . In at least one embodiment, processing cluster  2194  can be configured to execute many threads in parallel, where the term “thread” refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single instruction, multiple data (“SIMD”) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction, multiple thread (“SIMT”) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster  2194 . 
     In at least one embodiment, operation of processing cluster  2194  can be controlled via a pipeline manager  2132  that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager  2132  receives instructions from scheduler  2110  of  FIG.  21    and manages execution of those instructions via a graphics multiprocessor  2134  and/or a texture unit  2136 . In at least one embodiment, graphics multiprocessor  2134  is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures may be included within processing cluster  2194 . In at least one embodiment, one or more instances of graphics multiprocessor  2134  can be included within processing cluster  2194 . In at least one embodiment, graphics multiprocessor  2134  can process data and a data crossbar  2140  can be used to distribute processed data to one of multiple possible destinations, including other shader units. In at least one embodiment, pipeline manager  2132  can facilitate distribution of processed data by specifying destinations for processed data to be distributed via data crossbar  2140 . 
     In at least one embodiment, each graphics multiprocessor  2134  within processing cluster  2194  can include an identical set of functional execution logic (e.g., arithmetic logic units, load/store units (“LSUs”), etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. In at least one embodiment, same functional-unit hardware can be leveraged to perform different operations and any combination of functional units may be present. 
     In at least one embodiment, instructions transmitted to processing cluster  2194  constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor  2134 . In at least one embodiment, a thread group may include fewer threads than a number of processing engines within graphics multiprocessor  2134 . In at least one embodiment, when a thread group includes fewer threads than a number of processing engines, one or more of the processing engines may be idle during cycles in which that thread group is being processed. In at least one embodiment, a thread group may also include more threads than a number of processing engines within graphics multiprocessor  2134 . In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor  2134 , processing can be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor  2134 . 
     In at least one embodiment, graphics multiprocessor  2134  includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor  2134  can forego an internal cache and use a cache memory (e.g., L1 cache  2148 ) within processing cluster  2194 . In at least one embodiment, each graphics multiprocessor  2134  also has access to Level 2 (“L2”) caches within partition units (e.g., partition units  2120 A- 2120 N of  FIG.  21 A ) that are shared among all processing clusters  2194  and may be used to transfer data between threads. In at least one embodiment, graphics multiprocessor  2134  may also access off-chip global memory, which can include one or more of local parallel processor memory and/or system memory. In at least one embodiment, any memory external to parallel processing unit  2102  may be used as global memory. In at least one embodiment, processing cluster  2194  includes multiple instances of graphics multiprocessor  2134  that can share common instructions and data, which may be stored in L1 cache  2148 . 
     In at least one embodiment, each processing cluster  2194  may include an MMU  2145  that is configured to map virtual addresses into physical addresses. In at least one embodiment, one or more instances of MMU  2145  may reside within memory interface  2118  of  FIG.  21   . In at least one embodiment, MMU  2145  includes a set of page table entries (“PTEs”) used to map a virtual address to a physical address of a tile and optionally a cache line index. In at least one embodiment, MMU  2145  may include address translation lookaside buffers (“TLBs”) or caches that may reside within graphics multiprocessor  2134  or L1 cache  2148  or processing cluster  2194 . In at least one embodiment, a physical address is processed to distribute surface data access locality to allow efficient request interleaving among partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or miss. 
     In at least one embodiment, processing cluster  2194  may be configured such that each graphics multiprocessor  2134  is coupled to a texture unit  2136  for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor  2134  and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor  2134  outputs a processed task to data crossbar  2140  to provide the processed task to another processing cluster  2194  for further processing or to store the processed task in an L2 cache, a local parallel processor memory, or a system memory via memory crossbar  2116 . In at least one embodiment, a pre-raster operations unit (“preROP”)  2142  is configured to receive data from graphics multiprocessor  2134 , direct data to ROP units, which may be located with partition units as described herein (e.g., partition units  2120 A- 2120 N of  FIG.  21   ). In at least one embodiment, PreROP  2142  can perform optimizations for color blending, organize pixel color data, and perform address translations. 
       FIG.  21 C  illustrates a graphics multiprocessor  2196 , in accordance with at least one embodiment. In at least one embodiment, graphics multiprocessor  2196  is graphics multiprocessor  2134  of  FIG.  21 B . In at least one embodiment, graphics multiprocessor  2196  couples with pipeline manager  2132  of processing cluster  2194 . In at least one embodiment, graphics multiprocessor  2196  has an execution pipeline including but not limited to an instruction cache  2152 , an instruction unit  2154 , an address mapping unit  2156 , a register file  2158 , one or more GPGPU cores  2162 , and one or more LSUs  2166 . GPGPU cores  2162  and LSUs  2166  are coupled with cache memory  2172  and shared memory  2170  via a memory and cache interconnect  2168 . 
     In at least one embodiment, instruction cache  2152  receives a stream of instructions to execute from pipeline manager  2132 . In at least one embodiment, instructions are cached in instruction cache  2152  and dispatched for execution by instruction unit  2154 . In at least one embodiment, instruction unit  2154  can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group assigned to a different execution unit within GPGPU core  2162 . In at least one embodiment, an instruction can access any of a local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit  2156  can be used to translate addresses in a unified address space into a distinct memory address that can be accessed by LSUs  2166 . 
     In at least one embodiment, register file  2158  provides a set of registers for functional units of graphics multiprocessor  2196 . In at least one embodiment, register file  2158  provides temporary storage for operands connected to data paths of functional units (e.g., GPGPU cores  2162 , LSUs  2166 ) of graphics multiprocessor  2196 . In at least one embodiment, register file  2158  is divided between each of functional units such that each functional unit is allocated a dedicated portion of register file  2158 . In at least one embodiment, register file  2158  is divided between different thread groups being executed by graphics multiprocessor  2196 . 
     In at least one embodiment, GPGPU cores  2162  can each include FPUs and/or integer ALUs that are used to execute instructions of graphics multiprocessor  2196 . GPGPU cores  2162  can be similar in architecture or can differ in architecture. In at least one embodiment, a first portion of GPGPU cores  2162  include a single precision FPU and an integer ALU while a second portion of GPGPU cores  2162  include a double precision FPU. In at least one embodiment, FPUs can implement IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics multiprocessor  2196  can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. In at least one embodiment one or more of GPGPU cores  2162  can also include fixed or special function logic. 
     In at least one embodiment, GPGPU cores  2162  include SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment GPGPU cores  2162  can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores  2162  can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (“SPMD”) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for an SIMT execution model can executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform the same or similar operations can be executed in parallel via a single SIMD8 logic unit. 
     In at least one embodiment, memory and cache interconnect  2168  is an interconnect network that connects each functional unit of graphics multiprocessor  2196  to register file  2158  and to shared memory  2170 . In at least one embodiment, memory and cache interconnect  2168  is a crossbar interconnect that allows LSU  2166  to implement load and store operations between shared memory  2170  and register file  2158 . In at least one embodiment, register file  2158  can operate at a same frequency as GPGPU cores  2162 , thus data transfer between GPGPU cores  2162  and register file  2158  is very low latency. In at least one embodiment, shared memory  2170  can be used to enable communication between threads that execute on functional units within graphics multiprocessor  2196 . In at least one embodiment, cache memory  2172  can be used as a data cache for example, to cache texture data communicated between functional units and texture unit  2136 . In at least one embodiment, shared memory  2170  can also be used as a program managed cached. In at least one embodiment, threads executing on GPGPU cores  2162  can programmatically store data within shared memory in addition to automatically cached data that is stored within cache memory  2172 . 
     In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to host/processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, a GPU may be communicatively coupled to host processor/cores over a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In at least one embodiment, a GPU may be integrated on the same package or chip as cores and communicatively coupled to cores over a processor bus/interconnect that is internal to a package or a chip. In at least one embodiment, regardless of the manner in which a GPU is connected, processor cores may allocate work to the GPU in the form of sequences of commands/instructions contained in a WD. In at least one embodiment, the GPU then uses dedicated circuitry/logic for efficiently processing these commands/instructions. 
       FIG.  22    illustrates a graphics processor  2200 , in accordance with at least one embodiment. In at least one embodiment, graphics processor  2200  includes a ring interconnect  2202 , a pipeline front-end  2204 , a media engine  2237 , and graphics cores  2280 A- 2280 N. In at least one embodiment, ring interconnect  2202  couples graphics processor  2200  to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor  2200  is one of many processors integrated within a multi-core processing system. 
     In at least one embodiment, graphics processor  2200  receives batches of commands via ring interconnect  2202 . In at least one embodiment, incoming commands are interpreted by a command streamer  2203  in pipeline front-end  2204 . In at least one embodiment, graphics processor  2200  includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s)  2280 A- 2280 N. In at least one embodiment, for 3D geometry processing commands, command streamer  2203  supplies commands to geometry pipeline  2236 . In at least one embodiment, for at least some media processing commands, command streamer  2203  supplies commands to a video front end  2234 , which couples with a media engine  2237 . In at least one embodiment, media engine  2237  includes a Video Quality Engine (“VQE”)  2230  for video and image post-processing and a multi-format encode/decode (“MFX”) engine  2233  to provide hardware-accelerated media data encode and decode. In at least one embodiment, geometry pipeline  2236  and media engine  2237  each generate execution threads for thread execution resources provided by at least one graphics core  2280 A. 
     In at least one embodiment, graphics processor  2200  includes scalable thread execution resources featuring modular graphics cores  2280 A- 2280 N (sometimes referred to as core slices), each having multiple sub-cores  2250 A- 550 N,  2260 A- 2260 N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor  2200  can have any number of graphics cores  2280 A through  2280 N. In at least one embodiment, graphics processor  2200  includes a graphics core  2280 A having at least a first sub-core  2250 A and a second sub-core  2260 A. In at least one embodiment, graphics processor  2200  is a low power processor with a single sub-core (e.g., sub-core  2250 A). In at least one embodiment, graphics processor  2200  includes multiple graphics cores  2280 A- 2280 N, each including a set of first sub-cores  2250 A- 2250 N and a set of second sub-cores  2260 A- 2260 N. In at least one embodiment, each sub-core in first sub-cores  2250 A- 2250 N includes at least a first set of execution units (“EUs”)  2252 A- 2252 N and media/texture samplers  2254 A- 2254 N. In at least one embodiment, each sub-core in second sub-cores  2260 A- 2260 N includes at least a second set of execution units  2262 A- 2262 N and samplers  2264 A- 2264 N. In at least one embodiment, each sub-core  2250 A- 2250 N,  2260 A- 2260 N shares a set of shared resources  2270 A- 2270 N. In at least one embodiment, shared resources  2270  include shared cache memory and pixel operation logic. 
       FIG.  23    illustrates a processor  2300 , in accordance with at least one embodiment. In at least one embodiment, processor  2300  may include, without limitation, logic circuits to perform instructions. In at least one embodiment, processor  2300  may perform instructions, including x86 instructions, ARM instructions, specialized instructions for ASICs, etc. In at least one embodiment, processor  2310  may include registers to store packed data, such as 64-bit wide MMXTM registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, Calif. In at least one embodiment, MMX registers, available in both integer and floating point forms, may operate with packed data elements that accompany SIMD and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers relating to SSE2, SSE3, SSE4, AVX, or beyond (referred to generically as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processors  2310  may perform instructions to accelerate CUDA programs. 
     In at least one embodiment, processor  2300  includes an in-order front end (“front end”)  2301  to fetch instructions to be executed and prepare instructions to be used later in processor pipeline. In at least one embodiment, front end  2301  may include several units. In at least one embodiment, an instruction prefetcher  2326  fetches instructions from memory and feeds instructions to an instruction decoder  2328  which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder  2328  decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called “micro ops”or “uops”) for execution. In at least one embodiment, instruction decoder  2328  parses instruction into an opcode and corresponding data and control fields that may be used by micro-architecture to perform operations. In at least one embodiment, a trace cache  2330  may assemble decoded uops into program ordered sequences or traces in a uop queue  2334  for execution. In at least one embodiment, when trace cache  2330  encounters a complex instruction, a microcode ROM  2332  provides uops needed to complete an operation. 
     In at least one embodiment, some instructions may be converted into a single micro-op, whereas others need several micro-ops to complete full operation. In at least one embodiment, if more than four micro-ops are needed to complete an instruction, instruction decoder  2328  may access microcode ROM  2332  to perform instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing at instruction decoder  2328 . In at least one embodiment, an instruction may be stored within microcode ROM  2332  should a number of micro-ops be needed to accomplish operation. In at least one embodiment, trace cache  2330  refers to an entry point programmable logic array (“PLA”) to determine a correct micro-instruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM  2332 . In at least one embodiment, after microcode ROM  2332  finishes sequencing micro-ops for an instruction, front end  2301  of machine may resume fetching micro-ops from trace cache  2330 . 
     In at least one embodiment, out-of-order execution engine (“out of order engine”)  2303  may prepare instructions for execution. In at least one embodiment, out-of-order execution logic has a number of buffers to smooth out and re-order the flow of instructions to optimize performance as they go down a pipeline and get scheduled for execution. Out-of-order execution engine  2303  includes, without limitation, an allocator/register renamer  2340 , a memory uop queue  2342 , an integer/floating point uop queue  2344 , a memory scheduler  2346 , a fast scheduler  2302 , a slow/general floating point scheduler (“slow/general FP scheduler”)  2304 , and a simple floating point scheduler (“simple FP scheduler”)  2306 . In at least one embodiment, fast schedule  2302 , slow/general floating point scheduler  2304 , and simple floating point scheduler  2306  are also collectively referred to herein as “uop schedulers  2302 ,  2304 ,  2306 .” Allocator/register renamer  2340  allocates machine buffers and resources that each uop needs in order to execute. In at least one embodiment, allocator/register renamer  2340  renames logic registers onto entries in a register file. In at least one embodiment, allocator/register renamer  2340  also allocates an entry for each uop in one of two uop queues, memory uop queue  2342  for memory operations and integer/floating point uop queue  2344  for non-memory operations, in front of memory scheduler  2346  and uop schedulers  2302 ,  2304 ,  2306 . In at least one embodiment, uop schedulers  2302 ,  2304 ,  2306 , determine when a uop is ready to execute based on readiness of their dependent input register operand sources and availability of execution resources uops need to complete their operation. In at least one embodiment, fast scheduler  2302  of at least one embodiment may schedule on each half of main clock cycle while slow/general floating point scheduler  2304  and simple floating point scheduler  2306  may schedule once per main processor clock cycle. In at least one embodiment, uop schedulers  2302 ,  2304 ,  2306  arbitrate for dispatch ports to schedule uops for execution. 
     In at least one embodiment, execution block  2311  includes, without limitation, an integer register file/bypass network  2308 , a floating point register file/bypass network (“FP register file/bypass network”)  2310 , address generation units (“AGUs”)  2312  and  2314 , fast ALUs  2316  and  2318 , a slow ALU  2320 , a floating point ALU (“FP”)  2322 , and a floating point move unit (“FP move”)  2324 . In at least one embodiment, integer register file/bypass network  2308  and floating point register file/bypass network  2310  are also referred to herein as “register files  2308 ,  2310 .” In at least one embodiment, AGUSs  2312  and  2314 , fast ALUs  2316  and  2318 , slow ALU  2320 , floating point ALU  2322 , and floating point move unit  2324  are also referred to herein as “execution units  2312 ,  2314 ,  2316 ,  2318 ,  2320 ,  2322 , and  2324 .” In at least one embodiment, an execution block may include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units, in any combination. 
     In at least one embodiment, register files  2308 ,  2310  may be arranged between uop schedulers  2302 ,  2304 ,  2306 , and execution units  2312 ,  2314 ,  2316 ,  2318 ,  2320 ,  2322 , and  2324 . In at least one embodiment, integer register file/bypass network  2308  performs integer operations. In at least one embodiment, floating point register file/bypass network  2310  performs floating point operations. In at least one embodiment, each of register files  2308 ,  2310  may include, without limitation, a bypass network that may bypass or forward just completed results that have not yet been written into register file to new dependent uops. In at least one embodiment, register files  2308 ,  2310  may communicate data with each other. In at least one embodiment, integer register file/bypass network  2308  may include, without limitation, two separate register files, one register file for low-order thirty-two bits of data and a second register file for high order thirty-two bits of data. In at least one embodiment, floating point register file/bypass network  2310  may include, without limitation, 128-bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width. 
     In at least one embodiment, execution units  2312 ,  2314 ,  2316 ,  2318 ,  2320 ,  2322 ,  2324  may execute instructions. In at least one embodiment, register files  2308 ,  2310  store integer and floating point data operand values that micro-instructions need to execute. In at least one embodiment, processor  2300  may include, without limitation, any number and combination of execution units  2312 ,  2314 ,  2316 ,  2318 ,  2320 ,  2322 ,  2324 . In at least one embodiment, floating point ALU  2322  and floating point move unit  2324  may execute floating point, MMX, SIMD, AVX and SSE, or other operations. In at least one embodiment, floating point ALU  2322  may include, without limitation, a 64-bit by 64-bit floating point divider to execute divide, square root, and remainder micro ops. In at least one embodiment, instructions involving a floating point value may be handled with floating point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs  2316 ,  2318 . In at least one embodiment, fast ALUS  2316 ,  2318  may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU  2320  as slow ALU  2320  may include, without limitation, integer execution hardware for long-latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load/store operations may be executed by AGUs  2312 ,  2314 . In at least one embodiment, fast ALU  2316 , fast ALU  2318 , and slow ALU  2320  may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU  2316 , fast ALU  2318 , and slow ALU  2320  may be implemented to support a variety of data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating point ALU  2322  and floating point move unit  2324  may be implemented to support a range of operands having bits of various widths. In at least one embodiment, floating point ALU  2322  and floating point move unit  2324  may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions. 
     In at least one embodiment, uop schedulers  2302 ,  2304 ,  2306  dispatch dependent operations before parent load has finished executing. In at least one embodiment, as uops may be speculatively scheduled and executed in processor  2300 , processor  2300  may also include logic to handle memory misses. In at least one embodiment, if a data load misses in a data cache, there may be dependent operations in flight in pipeline that have left a scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations might need to be replayed and independent ones may be allowed to complete. In at least one embodiment, schedulers and replay mechanisms of at least one embodiment of a processor may also be designed to catch instruction sequences for text string comparison operations. 
     In at least one embodiment, the term “registers” may refer to on-board processor storage locations that may be used as part of instructions to identify operands. In at least one embodiment, registers may be those that may be usable from outside of a processor (from a programmer’s perspective). In at least one embodiment, registers might not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform functions described herein. In at least one embodiment, registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. A register file of at least one embodiment also contains eight multimedia SIMD registers for packed data. 
       FIG.  24    illustrates a processor  2400 , in accordance with at least one embodiment. In at least one embodiment, processor  2400  includes, without limitation, one or more processor cores (“cores”)  2402 A- 2402 N, an integrated memory controller  2414 , and an integrated graphics processor  2408 . In at least one embodiment, processor  2400  can include additional cores up to and including additional processor core  2402 N represented by dashed lined boxes. In at least one embodiment, each of processor cores  2402 A- 2402 N includes one or more internal cache units  2404 A- 2404 N. In at least one embodiment, each processor core also has access to one or more shared cached units  2406 . 
     In at least one embodiment, internal cache units  2404 A- 2404 N and shared cache units  2406  represent a cache memory hierarchy within processor  2400 . In at least one embodiment, cache memory units  2404 A- 2404 N may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as an L2, L3, Level 4 (“L4”), or other levels of cache, where a highest level of cache before external memory is classified as an LLC. In at least one embodiment, cache coherency logic maintains coherency between various cache units  2406  and  2404 A- 2404 N. 
     In at least one embodiment, processor  2400  may also include a set of one or more bus controller units  2416  and a system agent core  2410 . In at least one embodiment, one or more bus controller units  2416  manage a set of peripheral buses, such as one or more PCI or PCI express buses. In at least one embodiment, system agent core  2410  provides management functionality for various processor components. In at least one embodiment, system agent core  2410  includes one or more integrated memory controllers  2414  to manage access to various external memory devices (not shown). 
     In at least one embodiment, one or more of processor cores  2402 A- 2402 N include support for simultaneous multi-threading. In at least one embodiment, system agent core  2410  includes components for coordinating and operating processor cores  2402 A- 2402 N during multi-threaded processing. In at least one embodiment, system agent core  2410  may additionally include a power control unit (“PCU”), which includes logic and components to regulate one or more power states of processor cores  2402 A- 2402 N and graphics processor  2408 . 
     In at least one embodiment, processor  2400  additionally includes graphics processor  2408  to execute graphics processing operations. In at least one embodiment, graphics processor  2408  couples with shared cache units  2406 , and system agent core  2410 , including one or more integrated memory controllers  2414 . In at least one embodiment, system agent core  2410  also includes a display controller  2411  to drive graphics processor output to one or more coupled displays. In at least one embodiment, display controller  2411  may also be a separate module coupled with graphics processor  2408  via at least one interconnect, or may be integrated within graphics processor  2408 . 
     In at least one embodiment, a ring based interconnect unit  2412  is used to couple internal components of processor  2400 . In at least one embodiment, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques. In at least one embodiment, graphics processor  2408  couples with ring interconnect  2412  via an I/O link  2413 . 
     In at least one embodiment, I/O link  2413  represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module  2418 , such as an eDRAM module. In at least one embodiment, each of processor cores  2402 A- 2402 N and graphics processor  2408  use embedded memory modules  2418  as a shared LLC. 
     In at least one embodiment, processor cores  2402 A- 2402 N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores  2402 A- 2402 N are heterogeneous in terms of ISA, where one or more of processor cores  2402 A- 2402 N execute a common instruction set, while one or more other cores of processor cores  2402 A- 2402 N executes a subset of a common instruction set or a different instruction set. In at least one embodiment, processor cores  2402 A- 2402 N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more cores having a lower power consumption. In at least one embodiment, processor  2400  can be implemented on one or more chips or as an SoC integrated circuit. 
       FIG.  25    illustrates a graphics processor core  2500 , in accordance with at least one embodiment described. In at least one embodiment, graphics processor core  2500  is included within a graphics core array. In at least one embodiment, graphics processor core  2500 , sometimes referred to as a core slice, can be one or multiple graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core  2500  is exemplary of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core  2500  can include a fixed function block  2530  coupled with multiple sub-cores  2501 A- 2501 F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed function logic. 
     In at least one embodiment, fixed function block  2530  includes a geometry/fixed function pipeline  2536  that can be shared by all sub-cores in graphics processor  2500 , for example, in lower performance and/or lower power graphics processor implementations. In at least one embodiment, geometry/fixed function pipeline  2536  includes a 3D fixed function pipeline, a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager, which manages unified return buffers. 
     In at least one embodiment, fixed function block  2530  also includes a graphics SoC interface  2537 , a graphics microcontroller  2538 , and a media pipeline  2539 . Graphics SoC interface  2537  provides an interface between graphics core  2500  and other processor cores within an SoC integrated circuit. In at least one embodiment, graphics microcontroller  2538  is a programmable sub-processor that is configurable to manage various functions of graphics processor  2500 , including thread dispatch, scheduling, and pre-emption. In at least one embodiment, media pipeline  2539  includes logic to facilitate decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline  2539  implements media operations via requests to compute or sampling logic within sub-cores  2501 - 2501 F. 
     In at least one embodiment, SoC interface  2537  enables graphics core  2500  to communicate with general-purpose application processor cores (e.g., CPUs) and/or other components within an SoC, including memory hierarchy elements such as a shared LLC memory, system RAM, and/or embedded on-chip or on-package DRAM. In at least one embodiment, SoC interface  2537  can also enable communication with fixed function devices within an SoC, such as camera imaging pipelines, and enables use of and/or implements global memory atomics that may be shared between graphics core  2500  and CPUs within an SoC. In at least one embodiment, SoC interface  2537  can also implement power management controls for graphics core  2500  and enable an interface between a clock domain of graphic core  2500  and other clock domains within an SoC. In at least one embodiment, SoC interface  2537  enables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. In at least one embodiment, commands and instructions can be dispatched to media pipeline  2539 , when media operations are to be performed, or a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline  2536 , geometry and fixed function pipeline  2514 ) when graphics processing operations are to be performed. 
     In at least one embodiment, graphics microcontroller  2538  can be configured to perform various scheduling and management tasks for graphics core  2500 . In at least one embodiment, graphics microcontroller  2538  can perform graphics and/or compute workload scheduling on various graphics parallel engines within execution unit (EU) arrays  2502 A- 2502 F,  2504 A- 2504 F within sub-cores  2501 A- 2501 F. In at least one embodiment, host software executing on a CPU core of an SoC including graphics core  2500  can submit workloads one of multiple graphic processor doorbells, which invokes a scheduling operation on an appropriate graphics engine. In at least one embodiment, scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. In at least one embodiment, graphics microcontroller  2538  can also facilitate low-power or idle states for graphics core  2500 , providing graphics core  2500  with an ability to save and restore registers within graphics core  2500  across low-power state transitions independently from an operating system and/or graphics driver software on a system. 
     In at least one embodiment, graphics core  2500  may have greater than or fewer than illustrated sub-cores  2501 A- 2501 F, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core  2500  can also include shared function logic  2510 , shared and/or cache memory  2512 , a geometry/fixed function pipeline  2514 , as well as additional fixed function logic  2516  to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic  2510  can include logic units (e.g., sampler, math, and/or inter-thread communication logic) that can be shared by each N sub-cores within graphics core  2500 . Shared and/or cache memory  2512  can be an LLC for N sub-cores  2501 A- 2501 F within graphics core  2500  and can also serve as shared memory that is accessible by multiple sub-cores. In at least one embodiment, geometry/fixed function pipeline  2514  can be included instead of geometry/fixed function pipeline  2536  within fixed function block  2530  and can include same or similar logic units. 
     In at least one embodiment, graphics core  2500  includes additional fixed function logic  2516  that can include various fixed function acceleration logic for use by graphics core  2500 . In at least one embodiment, additional fixed function logic  2516  includes an additional geometry pipeline for use in position only shading. In position-only shading, at least two geometry pipelines exist, whereas in a full geometry pipeline within geometry/fixed function pipeline  2516 ,  2536 , and a cull pipeline, which is an additional geometry pipeline which may be included within additional fixed function logic  2516 . In at least one embodiment, cull pipeline is a trimmed down version of a full geometry pipeline. In at least one embodiment, a full pipeline and a cull pipeline can execute different instances of an application, each instance having a separate context. In at least one embodiment, position only shading can hide long cull runs of discarded triangles, enabling shading to be completed earlier in some instances. For example, in at least one embodiment, cull pipeline logic within additional fixed function logic  2516  can execute position shaders in parallel with a main application and generally generates critical results faster than a full pipeline, as a cull pipeline fetches and shades position attribute of vertices, without performing rasterization and rendering of pixels to a frame buffer. In at least one embodiment, a cull pipeline can use generated critical results to compute visibility information for all triangles without regard to whether those triangles are culled. In at least one embodiment, a full pipeline (which in this instance may be referred to as a replay pipeline) can consume visibility information to skip culled triangles to shade only visible triangles that are finally passed to a rasterization phase. 
     In at least one embodiment, additional fixed function logic  2516  can also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for accelerating CUDA programs. 
     In at least one embodiment, each graphics sub-core  2501 A- 2501 F includes a set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. In at least one embodiment, graphics sub-cores  2501 A- 2501 F include multiple EU arrays  2502 A- 2502 F,  2504 A- 2504 F, thread dispatch and inter-thread communication (“TD/IC”) logic  2503 A- 2503 F, a 3D (e.g., texture) sampler  2505 A- 2505 F, a media sampler  2506 A- 2506 F, a shader processor  2507 A- 2507 F, and shared local memory (“SLM”)  2508 A- 2508 F. EU arrays  2502 A- 2502 F,  2504 A- 2504 F each include multiple execution units, which are GPGPUs capable of performing floating-point and integer/fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. In at least one embodiment, TD/IC logic  2503 A- 2503 F performs local thread dispatch and thread control operations for execution units within a sub-core and facilitate communication between threads executing on execution units of a sub-core. In at least one embodiment, 3D sampler  2505 A- 2505 F can read texture or other 3D graphics related data into memory. In at least one embodiment, 3D sampler can read texture data differently based on a configured sample state and texture format associated with a given texture. In at least one embodiment, media sampler  2506 A- 2506 F can perform similar read operations based on a type and format associated with media data. In at least one embodiment, each graphics sub-core  2501 A- 2501 F can alternately include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each of sub-cores  2501 A- 2501 F can make use of shared local memory  2508 A- 2508 F within each sub-core, to enable threads executing within a thread group to execute using a common pool of on-chip memory. 
       FIG.  26    illustrates a parallel processing unit (“PPU”)  2600 , in accordance with at least one embodiment. In at least one embodiment, PPU  2600  is configured with machine-readable code that, if executed by PPU  2600 , causes PPU  2600  to perform some or all of processes and techniques described herein. In at least one embodiment, PPU  2600  is a multi-threaded processor that is implemented on one or more integrated circuit devices and that utilizes multithreading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) on multiple threads in parallel. In at least one embodiment, a thread refers to a thread of execution and is an instantiation of a set of instructions configured to be executed by PPU  2600 . In at least one embodiment, PPU  2600  is a GPU configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data in order to generate two-dimensional (“2D”) image data for display on a display device such as an LCD device. In at least one embodiment, PPU  2600  is utilized to perform computations such as linear algebra operations and machine-learning operations.  FIG.  26    illustrates an example parallel processor for illustrative purposes only and should be construed as a non-limiting example of a processor architecture that may be implemented in at least one embodiment. 
     In at least one embodiment, one or more PPUs  2600  are configured to accelerate High Performance Computing (“HPC”), data center, and machine learning applications. In at least one embodiment, one or more PPUs  2600  are configured to accelerate CUDA programs. In at least one embodiment, PPU  2600  includes, without limitation, an I/O unit  2606 , a front-end unit  2610 , a scheduler unit  2612 , a work distribution unit  2614 , a hub  2616 , a crossbar (“Xbar”)  2620 , one or more general processing clusters (“GPCs”)  2618 , and one or more partition units (“memory partition units”)  2622 . In at least one embodiment, PPU  2600  is connected to a host processor or other PPUs  2600  via one or more high-speed GPU interconnects (“GPU interconnects”)  2608 . In at least one embodiment, PPU  2600  is connected to a host processor or other peripheral devices via a system bus or interconnect  2602 . In at least one embodiment, PPU  2600  is connected to a local memory comprising one or more memory devices (“memory”)  2604 . In at least one embodiment, memory devices  2604  include, without limitation, one or more dynamic random access memory (DRAM) devices. In at least one embodiment, one or more DRAM devices are configured and/or configurable as high-bandwidth memory (“HBM”) subsystems, with multiple DRAM dies stacked within each device. 
     In at least one embodiment, high-speed GPU interconnect  2608  may refer to a wire-based multi-lane communications link that is used by systems to scale and include one or more PPUs  2600  combined with one or more CPUs, supports cache coherence between PPUs  2600  and CPUs, and CPU mastering. In at least one embodiment, data and/or commands are transmitted by high-speed GPU interconnect  2608  through hub  2616  to/from other units of PPU  2600  such as one or more copy engines, video encoders, video decoders, power management units, and other components which may not be explicitly illustrated in  FIG.  26   . 
     In at least one embodiment, I/O unit  2606  is configured to transmit and receive communications (e.g., commands, data) from a host processor (not illustrated in  FIG.  26   ) over system bus  2602 . In at least one embodiment, I/O unit  2606  communicates with host processor directly via system bus  2602  or through one or more intermediate devices such as a memory bridge. In at least one embodiment, I/O unit  2606  may communicate with one or more other processors, such as one or more of PPUs  2600  via system bus  2602 . In at least one embodiment, I/O unit  2606  implements a PCIe interface for communications over a PCIe bus. In at least one embodiment, I/O unit  2606  implements interfaces for communicating with external devices. 
     In at least one embodiment, I/O unit  2606  decodes packets received via system bus  2602 . In at least one embodiment, at least some packets represent commands configured to cause PPU  2600  to perform various operations. In at least one embodiment, I/O unit  2606  transmits decoded commands to various other units of PPU  2600  as specified by commands. In at least one embodiment, commands are transmitted to front-end unit  2610  and/or transmitted to hub  2616  or other units of PPU  2600  such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly illustrated in  FIG.  26   ). In at least one embodiment, I/O unit  2606  is configured to route communications between and among various logical units of PPU  2600 . 
     In at least one embodiment, a program executed by host processor encodes a command stream in a buffer that provides workloads to PPU  2600  for processing. In at least one embodiment, a workload comprises instructions and data to be processed by those instructions. In at least one embodiment, buffer is a region in a memory that is accessible (e.g., read/write) by both a host processor and PPU  2600  — a host interface unit may be configured to access buffer in a system memory connected to system bus  2602  via memory requests transmitted over system bus  2602  by I/O unit  2606 . In at least one embodiment, a host processor writes a command stream to a buffer and then transmits a pointer to the start of the command stream to PPU  2600  such that front-end unit  2610  receives pointers to one or more command streams and manages one or more command streams, reading commands from command streams and forwarding commands to various units of PPU  2600 . 
     In at least one embodiment, front-end unit  2610  is coupled to scheduler unit  2612  that configures various GPCs  2618  to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit  2612  is configured to track state information related to various tasks managed by scheduler unit  2612  where state information may indicate which of GPCs  2618  a task is assigned to, whether task is active or inactive, a priority level associated with task, and so forth. In at least one embodiment, scheduler unit  2612  manages execution of a plurality of tasks on one or more of GPCs  2618 . 
     In at least one embodiment, scheduler unit  2612  is coupled to work distribution unit  2614  that is configured to dispatch tasks for execution on GPCs  2618 . In at least one embodiment, work distribution unit  2614  tracks a number of scheduled tasks received from scheduler unit  2612  and work distribution unit  2614  manages a pending task pool and an active task pool for each of GPCs  2618 . In at least one embodiment, pending task pool comprises a number of slots (e.g.,32 slots) that contain tasks assigned to be processed by a particular GPC  2618 ; active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by GPCs  2618  such that as one of GPCs  2618  completes execution of a task, that task is evicted from active task pool for GPC  2618  and one of other tasks from pending task pool is selected and scheduled for execution on GPC  2618 . In at least one embodiment, if an active task is idle on GPC  2618 , such as while waiting for a data dependency to be resolved, then the active task is evicted from GPC  2618  and returned to a pending task pool while another task in the pending task pool is selected and scheduled for execution on GPC  2618 . 
     In at least one embodiment, work distribution unit  2614  communicates with one or more GPCs  2618  via XBar  2620 . In at least one embodiment, XBar  2620  is an interconnect network that couples many units of PPU  2600  to other units of PPU  2600  and can be configured to couple work distribution unit  2614  to a particular GPC  2618 . In at least one embodiment, one or more other units of PPU  2600  may also be connected to XBar  2620  via hub  2616 . 
     In at least one embodiment, tasks are managed by scheduler unit  2612  and dispatched to one of GPCs  2618  by work distribution unit  2614 . GPC  2618  is configured to process task and generate results. In at least one embodiment, results may be consumed by other tasks within GPC  2618 , routed to a different GPC  2618  via XBar  2620 , or stored in memory  2604 . In at least one embodiment, results can be written to memory  2604  via partition units  2622 , which implement a memory interface for reading and writing data to/from memory  2604 . In at least one embodiment, results can be transmitted to another PPU  2604  or CPU via high-speed GPU interconnect  2608 . In at least one embodiment, PPU  2600  includes, without limitation, a number U of partition units  2622  that is equal to number of separate and distinct memory devices  2604  coupled to PPU  2600 . 
     In at least one embodiment, a host processor executes a driver kernel that implements an application programming interface (“API”) that enables one or more applications executing on host processor to schedule operations for execution on PPU  2600 . In at least one embodiment, multiple compute applications are simultaneously executed by PPU  2600  and PPU  2600  provides isolation, quality of service (“QoS”), and independent address spaces for multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause a driver kernel to generate one or more tasks for execution by PPU  2600  and the driver kernel outputs tasks to one or more streams being processed by PPU  2600 . In at least one embodiment, each task comprises one or more groups of related threads, which may be referred to as a warp. In at least one embodiment, a warp comprises a plurality of related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, cooperating threads can refer to a plurality of threads including instructions to perform a task and that exchange data through shared memory. 
       FIG.  27    illustrates a GPC  2700 , in accordance with at least one embodiment. In at least one embodiment, GPC  2700  is GPC  2618  of  FIG.  26   . In at least one embodiment, each GPC  2700  includes, without limitation, a number of hardware units for processing tasks and each GPC  2700  includes, without limitation, a pipeline manager  2702 , a pre-raster operations unit (“PROP”)  2704 , a raster engine  2708 , a work distribution crossbar (“WDX”)  2716 , an MMU  2718 , one or more Data Processing Clusters (“DPCs”)  2706 , and any suitable combination of parts. 
     In at least one embodiment, operation of GPC  2700  is controlled by pipeline manager  2702 . In at least one embodiment, pipeline manager  2702  manages configuration of one or more DPCs  2706  for processing tasks allocated to GPC  2700 . In at least one embodiment, pipeline manager  2702  configures at least one of one or more DPCs  2706  to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, DPC  2706  is configured to execute a vertex shader program on a programmable streaming multiprocessor (“SM”)  2714 . In at least one embodiment, pipeline manager  2702  is configured to route packets received from a work distribution unit to appropriate logical units within GPC  2700  and, in at least one embodiment, some packets may be routed to fixed function hardware units in PROP  2704  and/or raster engine  2708  while other packets may be routed to DPCs  2706  for processing by a primitive engine  2712  or SM  2714 . In at least one embodiment, pipeline manager  2702  configures at least one of DPCs  2706  to implement a computing pipeline. In at least one embodiment, pipeline manager  2702  configures at least one of DPCs  2706  to execute at least a portion of a CUDA program. 
     In at least one embodiment, PROP unit  2704  is configured to route data generated by raster engine  2708  and DPCs  2706  to a Raster Operations (“ROP”) unit in a partition unit, such as memory partition unit  2622  described in more detail above in conjunction with  FIG.  26   . In at least one embodiment, PROP unit  2704  is configured to perform optimizations for color blending, organize pixel data, perform address translations, and more. In at least one embodiment, raster engine  2708  includes, without limitation, a number of fixed function hardware units configured to perform various raster operations and, in at least one embodiment, raster engine  2708  includes, without limitation, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile coalescing engine, and any suitable combination thereof. In at least one embodiment, a setup engine receives transformed vertices and generates plane equations associated with geometric primitive defined by vertices; plane equations are transmitted to a coarse raster engine to generate coverage information (e.g., an x, y coverage mask for a tile) for a primitive; the output of the coarse raster engine is transmitted to a culling engine where fragments associated with a primitive that fail a z-test are culled, and transmitted to a clipping engine where fragments lying outside a viewing frustum are clipped. In at least one embodiment, fragments that survive clipping and culling are passed to a fine raster engine to generate attributes for pixel fragments based on plane equations generated by a setup engine. In at least one embodiment, the output of raster engine  2708  comprises fragments to be processed by any suitable entity such as by a fragment shader implemented within DPC  2706 . 
     In at least one embodiment, each DPC  2706  included in GPC  2700  comprise, without limitation, an M-Pipe Controller (“MPC”)  2710 ; primitive engine  2712 ; one or more SMs  2714 ; and any suitable combination thereof. In at least one embodiment, MPC  2710  controls operation of DPC  2706 , routing packets received from pipeline manager  2702  to appropriate units in DPC  2706 . In at least one embodiment, packets associated with a vertex are routed to primitive engine  2712 , which is configured to fetch vertex attributes associated with vertex from memory; in contrast, packets associated with a shader program may be transmitted to SM  2714 . 
     In at least one embodiment, SM  2714  comprises, without limitation, a programmable streaming processor that is configured to process tasks represented by a number of threads. In at least one embodiment, SM  2714  is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently and implements a SIMD architecture where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on same set of instructions. In at least one embodiment, all threads in group of threads execute same instructions. In at least one embodiment, SM  2714  implements a SIMT architecture wherein each thread in a group of threads is configured to process a different set of data based on same set of instructions, but where individual threads in group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, a call stack, and an execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within a warp diverge. In another embodiment, a program counter, a call stack, and an execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. In at least one embodiment, an execution state is maintained for each individual thread and threads executing the same instructions may be converged and executed in parallel for better efficiency. At least one embodiment of SM  2714  is described in more detail in conjunction with  FIG.  28   . 
     In at least one embodiment, MMU  2718  provides an interface between GPC  2700  and a memory partition unit (e.g., partition unit  2622  of  FIG.  26   ) and MMU  2718  provides translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In at least one embodiment, MMU  2718  provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses into physical addresses in memory. 
       FIG.  28    illustrates a streaming multiprocessor (“SM”)  2800 , in accordance with at least one embodiment. In at least one embodiment, SM  2800  is SM  2714  of  FIG.  27   . In at least one embodiment, SM  2800  includes, without limitation, an instruction cache  2802 ; one or more scheduler units  2804 ; a register file  2808 ; one or more processing cores (“cores”)  2810 ; one or more special function units (“SFUs”)  2812 ; one or more LSUs  2814 ; an interconnect network  2816 ; a shared memory/L1 cache  2818 ; and any suitable combination thereof. In at least one embodiment, a work distribution unit dispatches tasks for execution on GPCs of parallel processing units (PPUs) and each task is allocated to a particular Data Processing Cluster (DPC) within a GPC and, if a task is associated with a shader program, then the task is allocated to one of SMs  2800 . In at least one embodiment, scheduler unit  2804  receives tasks from a work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM  2800 . In at least one embodiment, scheduler unit  2804  schedules thread blocks for execution as warps of parallel threads, wherein each thread block is allocated at least one warp. In at least one embodiment, each warp executes threads. In at least one embodiment, scheduler unit  2804  manages a plurality of different thread blocks, allocating warps to different thread blocks and then dispatching instructions from a plurality of different cooperative groups to various functional units (e.g., processing cores  2810 , SFUs  2812 , and LSUs  2814 ) during each clock cycle. 
     In at least one embodiment, “cooperative groups” may refer to a programming model for organizing groups of communicating threads that allows developers to express granularity at which threads are communicating, enabling expression of richer, more efficient parallel decompositions. In at least one embodiment, cooperative launch APIs support synchronization amongst thread blocks for execution of parallel algorithms. In at least one embodiment, APIs of conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., syncthreads( ) function). However, in at least one embodiment, programmers may define groups of threads at smaller than thread block granularities and synchronize within defined groups to enable greater performance, design flexibility, and software reuse in the form of collective group-wide function interfaces. In at least one embodiment, cooperative groups enable programmers to define groups of threads explicitly at sub-block and multi-block granularities, and to perform collective operations such as synchronization on threads in a cooperative group. In at least one embodiment, a sub-block granularity is as small as a single thread. In at least one embodiment, a programming model supports clean composition across software boundaries, so that libraries and utility functions can synchronize safely within their local context without having to make assumptions about convergence. In at least one embodiment, cooperative group primitives enable new patterns of cooperative parallelism, including, without limitation, producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks. 
     In at least one embodiment, a dispatch unit  2806  is configured to transmit instructions to one or more of functional units and scheduler unit  2804  includes, without limitation, two dispatch units  2806  that enable two different instructions from same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit  2804  includes a single dispatch unit  2806  or additional dispatch units  2806 . 
     In at least one embodiment, each SM  2800 , in at least one embodiment, includes, without limitation, register file  2808  that provides a set of registers for functional units of SM  2800 . In at least one embodiment, register file  2808  is divided between each of the functional units such that each functional unit is allocated a dedicated portion of register file  2808 . In at least one embodiment, register file  2808  is divided between different warps being executed by SM  2800  and register file  2808  provides temporary storage for operands connected to data paths of functional units. In at least one embodiment, each SM  2800  comprises, without limitation, a plurality of L processing cores  2810 . In at least one embodiment, SM  2800  includes, without limitation, a large number (e.g., 128 or more) of distinct processing cores  2810 . In at least one embodiment, each processing core  2810  includes, without limitation, a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes, without limitation, a floating point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, floating point arithmetic logic units implement IEEE 754-2008 standard for floating point arithmetic. In at least one embodiment, processing cores  2810  include, without limitation, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores. 
     In at least one embodiment, tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing cores  2810 . In at least one embodiment, tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D = A X B + C, where A, B, C, and D are 4×4 matrices. 
     In at least one embodiment, matrix multiply inputs A and B are 16-bit floating point matrices and accumulation matrices C and D are16-bit floating point or 32-bit floating point matrices. In at least one embodiment, tensor cores operate on 16-bit floating point input data with 32-bit floating point accumulation. In at least one embodiment, 16-bit floating point multiply uses 64 operations and results in a full precision product that is then accumulated using 32-bit floating point addition with other intermediate products for a 4×4×4 matrix multiply. Tensor cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements, in at least one embodiment. In at least one embodiment, an API, such as a CUDA-C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use tensor cores from a CUDA-C++ program. In at least one embodiment, at the CUDA level, a warp-level interface assumes 16×16 size matrices spanning all 32 threads of a warp. 
     In at least one embodiment, each SM  2800  comprises, without limitation, M SFUs  2812  that perform special functions (e.g., attribute evaluation, reciprocal square root, and like). In at least one embodiment, SFUs  2812  include, without limitation, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, SFUs  2812  include, without limitation, a texture unit configured to perform texture map filtering operations. In at least one embodiment, texture units are configured to load texture maps (e.g., a 2D array of texels) from memory and sample texture maps to produce sampled texture values for use in shader programs executed by SM  2800 . In at least one embodiment, texture maps are stored in shared memory/L1 cache  2818 . In at least one embodiment, texture units implement texture operations such as filtering operations using mip-maps (e.g., texture maps of varying levels of detail). In at least one embodiment, each SM  2800  includes, without limitation, two texture units. 
     In at least one embodiment, each SM  2800  comprises, without limitation, N LSUs  2814  that implement load and store operations between shared memory/L1 cache  2818  and register file  2808 . In at least one embodiment, each SM  2800  includes, without limitation, interconnect network  2816  that connects each of the functional units to register file  2808  and LSU  2814  to register file  2808  and shared memory/ L1 cache  2818 . In at least one embodiment, interconnect network  2816  is a crossbar that can be configured to connect any of the functional units to any of the registers in register file  2808  and connect LSUs  2814  to register file  2808  and memory locations in shared memory/L1 cache  2818 . 
     In at least one embodiment, shared memory/L1 cache  2818  is an array of on-chip memory that allows for data storage and communication between SM  2800  and a primitive engine and between threads in SM  2800 . In at least one embodiment, shared memory/L1 cache  2818  comprises, without limitation, 128KB of storage capacity and is in a path from SM  2800  to a partition unit. In at least one embodiment, shared memory/L1 cache  2818  is used to cache reads and writes. In at least one embodiment, one or more of shared memory/L1 cache  2818 , L2 cache, and memory are backing stores. 
     In at least one embodiment, combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory accesses. In at least one embodiment, capacity is used or is usable as a cache by programs that do not use shared memory, such as if shared memory is configured to use half of capacity, texture and load/store operations can use remaining capacity. In at least one embodiment, integration within shared memory/L1 cache  2818  enables shared memory/L1 cache  2818  to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, when configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. In at least one embodiment, fixed function GPUs are bypassed, creating a much simpler programming model. In at least one embodiment and in a general purpose parallel computation configuration, a work distribution unit assigns and distributes blocks of threads directly to DPCs. In at least one embodiment, threads in a block execute the same program, using a unique thread ID in a calculation to ensure each thread generates unique results, using SM  2800  to execute a program and perform calculations, shared memory/L1 cache  2818  to communicate between threads, and LSU  2814  to read and write global memory through shared memory/L1 cache  2818  and a memory partition unit. In at least one embodiment, when configured for general purpose parallel computation, SM  2800  writes commands that scheduler unit  2804  can use to launch new work on DPCs. 
     In at least one embodiment, PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), a PDA, a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and more. In at least one embodiment, PPU is embodied on a single semiconductor substrate. In at least one embodiment, PPU is included in an SoC along with one or more other devices such as additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter (“DAC”), and like. 
     In at least one embodiment, PPU may be included on a graphics card that includes one or more memory devices. In at least one embodiment, a graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In at least one embodiment, PPU may be an integrated GPU (“iGPU”) included in chipset of motherboard. 
     Software Constructions for General-Purpose Computing 
     Software constructions such as software stack  2900  can be used to perform a matrix multiplication, or other operation, as described herein. For example, a software application can be used to perform a first set of tasks that obtain data used by a second set of tasks, the first set of tasks performed in serial using a first set of thread, perform a first portion of the second set of tasks in parallel with the first set of tasks using a second set of threads, and perform a second portion of the second set of tasks in parallel with the first set of tasks, the second portion of the second set of tasks is time-interleaved with the first portion of the second set of tasks and performed using a third set of threads. Time-interleaving can be accomplished using buffer fill/empty messages, locking mechanisms, or a combination of both as described above. Some examples use prolog tasks to transfer data between system memory and a multiprocessing system such as a GPU, whereas others may transfer data from one system to a plurality of other processing resources over a network. The software application may, for example, transfer a set of kernels to memory of a GPU, store input matrix data into memory to be transferred by a prolog, and reserve memory to receive result tiles from one or more epilogs. 
     The following figures set forth, without limitation, exemplary software constructs for implementing at least one embodiment. 
       FIG.  29    illustrates a software stack of a programming platform, in accordance with at least one embodiment. In at least one embodiment, a programming platform is a platform for leveraging hardware on a computing system to accelerate computational tasks. A programming platform may be accessible to software developers through libraries, compiler directives, and/or extensions to programming languages, in at least one embodiment. In at least one embodiment, a programming platform may be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL™ is developed by Khronos group), SYCL, or Intel One API. 
     In at least one embodiment, a software stack  2900  of a programming platform provides an execution environment for an application  2901 . In at least one embodiment, application  2901  may include any computer software capable of being launched on software stack  2900 . In at least one embodiment, application  2901  may include, but is not limited to, an artificial intelligence (“AI”)/machine learning (“ML”) application, a high performance computing (“HPC”) application, a virtual desktop infrastructure (“VDI”), or a data center workload. 
     In at least one embodiment, application  2901  and software stack  2900  run on hardware  2907 . Hardware  2907  may include one or more GPUs, CPUs, FPGAs, AI engines, and/or other types of compute devices that support a programming platform, in at least one embodiment. In at least one embodiment, such as with CUDA, software stack  2900  may be vendor specific and compatible with only devices from particular vendor(s). In at least one embodiment, such as in with OpenCL, software stack  2900  may be used with devices from different vendors. In at least one embodiment, hardware  2907  includes a host connected to one more devices that can be accessed to perform computational tasks via application programming interface (“API”) calls. A device within hardware  2907  may include, but is not limited to, a GPU, FPGA, AI engine, or other compute device (but may also include a CPU) and its memory, as opposed to a host within hardware  2907  that may include, but is not limited to, a CPU (but may also include a compute device) and its memory, in at least one embodiment. 
     In at least one embodiment, software stack  2900  of a programming platform includes, without limitation, a number of libraries  2903 , a runtime  2905 , and a device kernel driver  2906 . Each of libraries  2903  may include data and programming code that can be used by computer programs and leveraged during software development, in at least one embodiment. In at least one embodiment, libraries  2903  may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and/or message templates. In at least one embodiment, libraries  2903  include functions that are optimized for execution on one or more types of devices. In at least one embodiment, libraries  2903  may include, but are not limited to, functions for performing mathematical, deep learning, and/or other types of operations on devices. In at least one embodiment, libraries  2903  are associated with corresponding APIs  2902 , which may include one or more APIs, that expose functions implemented in libraries  2903 . 
     In at least one embodiment, application  2901  is written as source code that is compiled into executable code, as discussed in greater detail below in conjunction with  FIGS.  34  -  36   . Executable code of application  2901  may run, at least in part, on an execution environment provided by software stack  2900 , in at least one embodiment. In at least one embodiment, during execution of application  2901 , code may be reached that needs to run on a device, as opposed to a host. In such a case, runtime  2905  may be called to load and launch requisite code on the device, in at least one embodiment. In at least one embodiment, runtime  2905  may include any technically feasible runtime system that is able to support execution of application S01. 
     In at least one embodiment, runtime  2905  is implemented as one or more runtime libraries associated with corresponding APIs, which are shown as API(s)  2904 . One or more of such runtime libraries may include, without limitation, functions for memory management, execution control, device management, error handling, and/or synchronization, among other things, in at least one embodiment. In at least one embodiment, memory management functions may include, but are not limited to, functions to allocate, deallocate, and copy device memory, as well as transfer data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions to launch a function (sometimes referred to as a “kernel” when a function is a global function callable from a host) on a device and set attribute values in a buffer maintained by a runtime library for a given function to be executed on a device. 
     Runtime libraries and corresponding API(s)  2904  may be implemented in any technically feasible manner, in at least one embodiment. In at least one embodiment, one (or any number of) API may expose a low-level set of functions for fine-grained control of a device, while another (or any number of) API may expose a higher-level set of such functions. In at least one embodiment, a high-level runtime API may be built on top of a low-level API. In at least one embodiment, one or more of runtime APIs may be language-specific APIs that are layered on top of a language-independent runtime API. 
     In at least one embodiment, device kernel driver  2906  is configured to facilitate communication with an underlying device. In at least one embodiment, device kernel driver  2906  may provide low-level functionalities upon which APIs, such as API(s)  2904 , and/or other software relies. In at least one embodiment, device kernel driver  2906  may be configured to compile intermediate representation (“IR”) code into binary code at runtime. For CUDA, device kernel driver  2906  may compile Parallel Thread Execution (“PTX”) IR code that is not hardware specific into binary code for a specific target device at runtime (with caching of compiled binary code), which is also sometimes referred to as “finalizing” code, in at least one embodiment. Doing so may permit finalized code to run on a target device, which may not have existed when source code was originally compiled into PTX code, in at least one embodiment. Alternatively, in at least one embodiment, device source code may be compiled into binary code offline, without requiring device kernel driver  2906  to compile IR code at runtime. 
       FIG.  30    illustrates a CUDA implementation of software stack  2900  of  FIG.  29   , in accordance with at least one embodiment. In at least one embodiment, a CUDA software stack  3000 , on which an application  3001  may be launched, includes CUDA libraries  3003 , a CUDA runtime  3005 , a CUDA driver  3007 , and a device kernel driver  3008 . In at least one embodiment, CUDA software stack  3000  executes on hardware  3009 , which may include a GPU that supports CUDA and is developed by NVIDIA Corporation of Santa Clara, CA. 
     In at least one embodiment, application  3001 , CUDA runtime  3005 , and device kernel driver  3008  may perform similar functionalities as application  2901 , runtime  2905 , and device kernel driver  2906 , respectively, which are described above in conjunction with  FIG.  29   . In at least one embodiment, CUDA driver  3007  includes a library (libcuda.so) that implements a CUDA driver API  3006 . Similar to a CUDA runtime API  3004  implemented by a CUDA runtime library (cudart), CUDA driver API  3006  may, without limitation, expose functions for memory management, execution control, device management, error handling, synchronization, and/or graphics interoperability, among other things, in at least one embodiment. In at least one embodiment, CUDA driver API  3006  differs from CUDA runtime API  3004  in that CUDA runtime API  3004  simplifies device code management by providing implicit initialization, context (analogous to a process) management, and module (analogous to dynamically loaded libraries) management. In contrast to high-level CUDA runtime API  3004 , CUDA driver API  3006  is a low-level API providing more fine-grained control of the device, particularly with respect to contexts and module loading, in at least one embodiment. In at least one embodiment, CUDA driver API  3006  may expose functions for context management that are not exposed by CUDA runtime API  3004 . In at least one embodiment, CUDA driver API  3006  is also language-independent and supports, e.g., OpenCL in addition to CUDA runtime API  3004 . Further, in at least one embodiment, development libraries, including CUDA runtime  3005 , may be considered as separate from driver components, including user-mode CUDA driver  3007  and kernel-mode device driver  3008  (also sometimes referred to as a “display” driver). 
     In at least one embodiment, CUDA libraries  3003  may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and/or signal/image/video processing libraries, which parallel computing applications such as application  3001  may utilize. In at least one embodiment, CUDA libraries  3003  may include mathematical libraries such as a cuBLAS library that is an implementation of Basic Linear Algebra Subprograms (“BLAS”) for performing linear algebra operations, a cuFFT library for computing fast Fourier transforms (“FFTs”), and a cuRAND library for generating random numbers, among others. In at least one embodiment, CUDA libraries  3003  may include deep learning libraries such as a cuDNN library of primitives for deep neural networks and a TensorRT platform for high-performance deep learning inference, among others. 
       FIG.  31    illustrates a ROCm implementation of software stack  2900  of  FIG.  29   , in accordance with at least one embodiment. In at least one embodiment, a ROCm software stack  3100 , on which an application  3101  may be launched, includes a language runtime  3103 , a system runtime  3105 , a thunk  3107 , and a ROCm kernel driver  3108 . In at least one embodiment, ROCm software stack  3100  executes on hardware  3109 , which may include a GPU that supports ROCm and is developed by AMD Corporation of Santa Clara, CA. 
     In at least one embodiment, application  3101  may perform similar functionalities as application  2901  discussed above in conjunction with  FIG.  29   . In addition, language runtime  3103  and system runtime  3105  may perform similar functionalities as runtime  2905  discussed above in conjunction with  FIG.  29   , in at least one embodiment. In at least one embodiment, language runtime  3103  and system runtime  3105  differ in that system runtime  3105  is a language-independent runtime that implements a ROCr system runtime API  3104  and makes use of a Heterogeneous System Architecture (“HSA”) Runtime API. HSA runtime API is a thin, user-mode API that exposes interfaces to access and interact with an AMD GPU, including functions for memory management, execution control via architected dispatch of kernels, error handling, system and agent information, and runtime initialization and shutdown, among other things, in at least one embodiment. In contrast to system runtime  3105 , language runtime  3103  is an implementation of a language-specific runtime API  3102  layered on top of ROCr system runtime API  3104 , in at least one embodiment. In at least one embodiment, language runtime API may include, but is not limited to, a Heterogeneous compute Interface for Portability (“HIP”) language runtime API, a Heterogeneous Compute Compiler (“HCC”) language runtime API, or an OpenCL API, among others. HIP language in particular is an extension of C++ programming language with functionally similar versions of CUDA mechanisms, and, in at least one embodiment, a HIP language runtime API includes functions that are similar to those of CUDA runtime API  3004  discussed above in conjunction with  FIG.  30   , such as functions for memory management, execution control, device management, error handling, and synchronization, among other things. 
     In at least one embodiment, thunk (ROCt)  3107  is an interface  3106  that can be used to interact with underlying ROCm driver  3108 . In at least one embodiment, ROCm driver  3108  is a ROCk driver, which is a combination of an AMDGPU driver and a HSA kernel driver (amdkfd). In at least one embodiment, AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs similar functionalities as device kernel driver  2906  discussed above in conjunction with  FIG.  29   . In at least one embodiment, HSA kernel driver is a driver permitting different types of processors to share system resources more effectively via hardware features. 
     In at least one embodiment, various libraries (not shown) may be included in ROCm software stack  3100  above language runtime  3103  and provide functionality similarity to CUDA libraries  3003 , discussed above in conjunction with  FIG.  30   . In at least one embodiment, various libraries may include, but are not limited to, mathematical, deep learning, and/or other libraries such as a hipBLAS library that implements functions similar to those of CUDA cuBLAS, a rocFFT library for computing FFTs that is similar to CUDA cuFFT, among others. 
       FIG.  32    illustrates an OpenCL implementation of software stack  2900  of  FIG.  29   , in accordance with at least one embodiment. In at least one embodiment, an OpenCL software stack  3200 , on which an application  3201  may be launched, includes an OpenCL framework  3210 , an OpenCL runtime  3206 , and a driver  3207 . In at least one embodiment, OpenCL software stack  3200  executes on hardware  3009  that is not vendor-specific. As OpenCL is supported by devices developed by different vendors, specific OpenCL drivers may be required to interoperate with hardware from such vendors, in at least one embodiment. 
     In at least one embodiment, application  3201 , OpenCL runtime  3206 , device kernel driver  3207 , and hardware  3208  may perform similar functionalities as application  2901 , runtime  2905 , device kernel driver  2906 , and hardware  2907 , respectively, that are discussed above in conjunction with  FIG.  29   . In at least one embodiment, application  3201  further includes an OpenCL kernel  3202  with code that is to be executed on a device. 
     In at least one embodiment, OpenCL defines a “platform” that allows a host to control devices connected to the host. In at least one embodiment, an OpenCL framework provides a platform layer API and a runtime API, shown as platform API  3203  and runtime API  3205 . In at least one embodiment, runtime API  3205  uses contexts to manage execution of kernels on devices. In at least one embodiment, each identified device may be associated with a respective context, which runtime API  3205  may use to manage command queues, program objects, and kernel objects, share memory objects, among other things, for that device. In at least one embodiment, platform API  3203  exposes functions that permit device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices, among other things. In addition, OpenCL framework provides various built-in functions (not shown), including math functions, relational functions, and image processing functions, among others, in at least one embodiment. 
     In at least one embodiment, a compiler  3204  is also included in OpenCL frame-work  3210 . Source code may be compiled offline prior to executing an application or online during execution of an application, in at least one embodiment. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment may be compiled online by compiler  3204 , which is included to be representative of any number of compilers that may be used to compile source code and/or IR code, such as Standard Portable Intermediate Representation (“SPIR-V”) code, into binary code. Alternatively, in at least one embodiment, OpenCL ap-plications may be compiled offline, prior to execution of such applications. 
       FIG.  33    illustrates software that is supported by a programming platform, in accordance with at least one embodiment. In at least one embodiment, a programming platform  3304  is configured to support various programming models  3303 , middlewares and/or libraries  3302 , and frameworks  3301  that an application  3300  may rely upon. In at least one embodiment, application  3300  may be an AI/ML application implemented using, for example, a deep learning framework such as MXNet, PyTorch, or TensorFlow, which may rely on libraries such as cuDNN, NVIDIA Collective Communications Library (“NCCL”), and/or NVIDA Developer Data Loading Library (“DALI”) CUDA libraries to provide accelerated computing on underlying hardware. 
     In at least one embodiment, programming platform  3304  may be one of a CUDA, ROCm, or OpenCL platform described above in conjunction with  FIG.  30   ,  FIG.  31   , and  FIG.  32   , respectively. In at least one embodiment, programming platform  3304  supports multiple programming models  3303 , which are abstractions of an underlying computing system permitting expressions of algorithms and data structures. Programming models  3303  may expose features of underlying hardware in order to improve performance, in at least one embodiment. In at least one embodiment, programming models  3303  may include, but are not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++AMP”), Open Multi-Processing (“OpenMP”), Open Accelerators (“OpenACC”), and/or Vulcan Compute. 
     In at least one embodiment, libraries and/or middlewares  3302  provide implementations of abstractions of programming models  3304 . In at least one embodiment, such libraries include data and programming code that may be used by computer programs and leveraged during software development. In at least one embodiment, such middlewares include software that provides services to applications beyond those available from programming platform  3304 . In at least one embodiment, libraries and/or middlewares  3302  may include, but are not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. In addition, in at least one embodiment, libraries and/or middlewares  3302  may include NCCL and ROCm Communication Collectives Library (“RCCL”) libraries providing communication routines for GPUs, a MIOpen library for deep learning acceleration, and/or an Eigen library for linear algebra, matrix and vector operations, geometrical transformations, numerical solvers, and related algorithms. 
     In at least one embodiment, application frameworks  3301  depend on libraries and/or middlewares  3302 . In at least one embodiment, each of application frameworks  3301  is a software framework used to implement a standard structure of application software. Returning to the AI/ML example discussed above, an AI/ML application may be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning frameworks, in at least one embodiment. 
       FIG.  34    illustrates compiling code to execute on one of programming platforms of  FIGS.  29  -  32   , in accordance with at least one embodiment. In at least one embodiment, a compiler  3401  receives source code  3400  that includes both host code as well as device code. In at least one embodiment, compiler  3401  is configured to convert source code  3400  into host executable code  3402  for execution on a host and device executable code  3403  for execution on a device. In at least one embodiment, source code  3400  may either be compiled offline prior to execution of an application, or online during execution of an application. 
     In at least one embodiment, source code  3400  may include code in any programming language supported by compiler  3401 , such as C++, C, Fortran, etc. In at least one embodiment, source code  3400  may be included in a single-source file having a mixture of host code and device code, with locations of device code being indicated therein. In at least one embodiment, a single-source file may be a .cu file that includes CUDA code or a .hip.cpp file that includes HIP code. Alternatively, in at least one embodiment, source code  3400  may include multiple source code files, rather than a single-source file, into which host code and device code are separated. 
     In at least one embodiment, compiler  3401  is configured to compile source code  3400  into host executable code  3402  for execution on a host and device executable code  3403  for execution on a device. In at least one embodiment, compiler  3401  performs operations including parsing source code  3400  into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment in which source code  3400  includes a single-source file, compiler  3401  may separate device code from host code in such a single-source file, compile device code and host code into device executable code  3403  and host executable code  3402 , respectively, and link device executable code  3403  and host executable code  3402  together in a single file, as discussed in greater detail below with respect to  FIG.  35   . 
     In at least one embodiment, host executable code  3402  and device executable code  3403  may be in any suitable format, such as binary code and/or IR code. In the case of CUDA, host executable code  3402  may include native object code and device executable code  3403  may include code in PTX intermediate representation, in at least one embodiment. In the case of ROCm, both host executable code  3402  and device executable code  3403  may include target binary code, in at least one embodiment. 
       FIG.  35    is a more detailed illustration of compiling code to execute on one of programming platforms of  FIGS.  29  -  32   , in accordance with at least one embodiment. In at least one embodiment, a compiler  3501  is configured to receive source code  3500 , compile source code  3500 , and output an executable file  3510 . In at least one embodiment, source code  3500  is a single-source file, such as a .cu file, a .hip.cpp file, or a file in another format, that includes both host and device code. In at least one embodiment, compiler  3501  may be, but is not limited to, an NVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in .cu files, or a HCC compiler for compiling HIP code in .hip.cpp files. 
     In at least one embodiment, compiler  3501  includes a compiler front end  3502 , a host compiler  3505 , a device compiler  3506 , and a linker  3509 . In at least one embodiment, compiler front end  3502  is configured to separate device code  3504  from host code  3503  in source code  3500 . Device code  3504  is compiled by device compiler  3506  into device executable code  3508 , which as described may include binary code or IR code, in at least one embodiment. Separately, host code  3503  is compiled by host compiler  3505  into host executable code  3507 , in at least one embodiment. For NVCC, host compiler  3505  may be, but is not limited to, a general purpose C/C++ compiler that outputs native object code, while device compiler  3506  may be, but is not limited to, a Low Level Virtual Machine (“LLVM”)-based compiler that forks a LLVM compiler infrastructure and outputs PTX code or binary code, in at least one embodiment. For HCC, both host compiler  3505  and device compiler  3506  may be, but are not limited to, LLVM-based compilers that output target binary code, in at least one embodiment. 
     Subsequent to compiling source code  3500  into host executable code  3507  and device executable code  3508 , linker  3509  links host and device executable code  3507  and  3508  together in executable file  3510 , in at least one embodiment. In at least one embodiment, native object code for a host and PTX or binary code for a device may be linked together in an Executable and Linkable Format (“ELF”) file, which is a container format used to store object code. 
       FIG.  36    illustrates translating source code prior to compiling source code, in accordance with at least one embodiment. In at least one embodiment, source code  3600  is passed through a translation tool  3601 , which translates source code  3600  into translated source code  3602 . In at least one embodiment, a compiler  3603  is used to compile translated source code  3602  into host executable code  3604  and device executable code  3605  in a process that is similar to compilation of source code  3400  by compiler  3401  into host executable code  3402  and device executable  3403 , as discussed above in conjunction with  FIG.  34   . 
     In at least one embodiment, a translation performed by translation tool  3601  is used to port source  3600  for execution in a different environment than that in which it was originally intended to run. In at least one embodiment, translation tool  3601  may include, but is not limited to, a HIP translator that is used to “hipify” CUDA code intended for a CUDA platform into HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, translation of source code  3600  may include parsing source code  3600  and converting calls to API(s) provided by one programming model (e.g., CUDA) into corresponding calls to API(s) provided by another programming model (e.g., HIP), as discussed in greater detail below in conjunction with  FIGS.  37 A -  38   . Returning to the example of hipifying CUDA code, calls to CUDA runtime API, CUDA driver API, and/or CUDA libraries may be converted to corresponding HIP API calls, in at least one embodiment. In at least one embodiment, automated translations performed by translation tool  3601  may sometimes be incomplete, requiring additional, manual effort to fully port source code  3600 . 
     CONFIGURING GPUS FOR GENERAL-PURPOSE COMPUTING 
     The following figures set forth, without limitation, exemplary architectures for compiling and executing compute source code, in accordance with at least one embodiment. 
       FIG.  37 A  illustrates a system 37A00 configured to compile and execute CUDA source code  3710  using different types of processing units, in accordance with at least one embodiment. In at least one embodiment, system 37A00 includes, without limitation, CUDA source code  3710 , a CUDA compiler  3750 , host executable code  3770 ( 1 ), host executable code  3770 ( 2 ), CUDA device executable code  3784 , a CPU  3790 , a CUDA-enabled GPU  3794 , a GPU  3792 , a CUDA to HIP translation tool  3720 , HIP source code  3730 , a HIP compiler driver  3740 , an HCC  3760 , and HCC device executable code  3782 . 
     In at least one embodiment, CUDA source code  3710  is a collection of human-readable code in a CUDA programming language. In at least one embodiment, CUDA code is human-readable code in a CUDA programming language. In at least one embodiment, a CUDA programming language is an extension of the C++ programming language that includes, without limitation, mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, device code is source code that, after compilation, is executable in parallel on a device. In at least one embodiment, a device may be a processor that is optimized for parallel instruction processing, such as CUDA-enabled GPU  3790 , GPU 37192, or another GPGPU, etc. In at least one embodiment, host code is source code that, after compilation, is executable on a host. In at least one embodiment, a host is a processor that is optimized for sequential instruction processing, such as CPU  3790 . 
     In at least one embodiment, CUDA source code  3710  includes, without limitation, any number (including zero) of global functions  3712 , any number (including zero) of device functions  3714 , any number (including zero) of host functions  3716 , and any number (including zero) of host/device functions  3718 . In at least one embodiment, global functions  3712 , device functions  3714 , host functions  3716 , and host/device functions  3718  may be mixed in CUDA source code  3710 . In at least one embodiment, each of global functions  3712  is executable on a device and callable from a host. In at least one embodiment, one or more of global functions  3712  may therefore act as entry points to a device. In at least one embodiment, each of global functions  3712  is a kernel. In at least one embodiment and in a technique known as dynamic parallelism, one or more of global functions  3712  defines a kernel that is executable on a device and callable from such a device. In at least one embodiment, a kernel is executed N (where N is any positive integer) times in parallel by N different threads on a device during execution. 
     In at least one embodiment, each of device functions  3714  is executed on a device and callable from such a device only. In at least one embodiment, each of host functions  3716  is executed on a host and callable from such a host only. In at least one embodiment, each of host/device functions  3716  defines both a host version of a function that is executable on a host and callable from such a host only and a device version of the function that is executable on a device and callable from such a device only. 
     In at least one embodiment, CUDA source code  3710  may also include, without limitation, any number of calls to any number of functions that are defined via a CUDA runtime API  3702 . In at least one embodiment, CUDA runtime API  3702  may include, without limitation, any number of functions that execute on a host to allocate and deallocate device memory, transfer data between host memory and device memory, manage systems with multiple devices, etc. In at least one embodiment, CUDA source code  3710  may also include any number of calls to any number of functions that are specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API that is designed for use by CUDA code. In at least one embodiment, CUDA APIs include, without limitation, CUDA runtime API  3702 , a CUDA driver API, APIs for any number of CUDA libraries, etc. In at least one embodiment and relative to CUDA runtime API  3702 , a CUDA driver API is a lower-level API but provides finer-grained control of a device. In at least one embodiment, examples of CUDA libraries include, without limitation, cuBLAS, cuFFT, cuRAND, cuDNN, etc. 
     In at least one embodiment, CUDA compiler  3750  compiles input CUDA code (e.g., CUDA source code  3710 ) to generate host executable code  3770 ( 1 ) and CUDA device executable code  3784 . In at least one embodiment, CUDA compiler  3750  is NVCC. In at least one embodiment, host executable code  3770 ( 1 ) is a compiled version of host code included in input source code that is executable on CPU  3790 . In at least one embodiment, CPU  3790  may be any processor that is optimized for sequential instruction processing. 
     In at least one embodiment, CUDA device executable code  3784  is a compiled version of device code included in input source code that is executable on CUDA-enabled GPU  3794 . In at least one embodiment, CUDA device executable code  3784  includes, without limitation, binary code. In at least one embodiment, CUDA device executable code  3784  includes, without limitation, IR code, such as PTX code, that is further compiled at runtime into binary code for a specific target device (e.g., CUDA-enabled GPU  3794 ) by a device driver. In at least one embodiment, CUDA-enabled GPU  3794  may be any processor that is optimized for parallel instruction processing and that supports CUDA. In at least one embodiment, CUDA-enabled GPU  3794  is developed by NVIDIA Corporation of Santa Clara, CA. 
     In at least one embodiment, CUDA to HIP translation tool  3720  is configured to translate CUDA source code  3710  to functionally similar HIP source code  3730 . In a least one embodiment, HIP source code  3730  is a collection of human-readable code in a HIP programming language. In at least one embodiment, HIP code is human-readable code in a HIP programming language. In at least one embodiment, a HIP programming language is an extension of the C++ programming language that includes, without limitation, functionally similar versions of CUDA mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, a HIP programming language may include a subset of functionality of a CUDA programming language. In at least one embodiment, for example, a HIP programming language includes, without limitation, mechanism(s) to define global functions  3712 , but such a HIP programming language may lack support for dynamic parallelism and therefore global functions  3712  defined in HIP code may be callable from a host only. 
     In at least one embodiment, HIP source code  3730  includes, without limitation, any number (including zero) of global functions  3712 , any number (including zero) of device functions  3714 , any number (including zero) of host functions  3716 , and any number (including zero) of host/device functions  3718 . In at least one embodiment, HIP source code  3730  may also include any number of calls to any number of functions that are specified in a HIP runtime API  3732 . In at least one embodiment, HIP runtime API  3732  includes, without limitation, functionally similar versions of a subset of functions included in CUDA runtime API  3702 . In at least one embodiment, HIP source code  3730  may also include any number of calls to any number of functions that are specified in any number of other HIP APIs. In at least one embodiment, a HIP API may be any API that is designed for use by HIP code and/or ROCm. In at least one embodiment, HIP APIs include, without limitation, HIP runtime API  3732 , a HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, etc. 
     In at least one embodiment, CUDA to HIP translation tool  3720  converts each kernel call in CUDA code from a CUDA syntax to a HIP syntax and converts any number of other CUDA calls in CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in a CUDA API, and a HIP call is a call to a function specified in a HIP API. In at least one embodiment, CUDA to HIP translation tool  3720  converts any number of calls to functions specified in CUDA runtime API  3702  to any number of calls to functions specified in HIP runtime API  3732 . 
     In at least one embodiment, CUDA to HIP translation tool  3720  is a tool known as hipify-perl that executes a text-based translation process. In at least one embodiment, CUDA to HIP translation tool  3720  is a tool known as hipify-clang that, relative to hipify-perl, executes a more complex and more robust translation process that involves parsing CUDA code using clang (a compiler front-end) and then translating resulting symbols. In at least one embodiment, properly converting CUDA code to HIP code may require modifications (e.g., manual edits) in addition to those performed by CUDA to HIP translation tool  3720 . 
     In at least one embodiment, HIP compiler driver  3740  is a front end that determines a target device  3746  and then configures a compiler that is compatible with target device  3746  to compile HIP source code  3730 . In at least one embodiment, target device  3746  is a processor that is optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver  3740  may determine target device  3746  in any technically feasible fashion. 
     In at least one embodiment, if target device  3746  is compatible with CUDA (e.g., CUDA-enabled GPU  3794 ), then HIP compiler driver  3740  generates a HIP/NVCC compilation command  3742 . In at least one embodiment and as described in greater detail in conjunction with  FIG.  37 B , HIP/NVCC compilation command  3742  configures CUDA compiler  3750  to compile HIP source code  3730  using, without limitation, a HIP to CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to HIP/NVCC compilation command  3742 , CUDA compiler  3750  generates host executable code  3770 ( 1 ) and CUDA device executable code  3784 . 
     In at least one embodiment, if target device  3746  is not compatible with CUDA, then HIP compiler driver  3740  generates a HIP/HCC compilation command  3744 . In at least one embodiment and as described in greater detail in conjunction with  FIG.  37 C , HIP/HCC compilation command  3744  configures HCC  3760  to compile HIP source code  3730  using, without limitation, an HCC header and a HIP/HCC runtime library. In at least one embodiment and in response to HIP/HCC compilation command  3744 , HCC  3760  generates host executable code  3770 ( 2 ) and HCC device executable code  3782 . In at least one embodiment, HCC device executable code  3782  is a compiled version of device code included in HIP source code  3730  that is executable on GPU  3792 . In at least one embodiment, GPU  3792  may be any processor that is optimized for parallel instruction processing, is not compatible with CUDA, and is compatible with HCC. In at least one embodiment, GPU  3792  is developed by AMD Corporation of Santa Clara, CA. In at least one embodiment GPU,  3792  is a non-CUDA-enabled GPU  3792 . 
     For explanatory purposes only, three different flows that may be implemented in at least one embodiment to compile CUDA source code  3710  for execution on CPU  3790  and different devices are depicted in  FIG.  37 A . In at least one embodiment, a direct CUDA flow compiles CUDA source code  3710  for execution on CPU  3790  and CUDA-enabled GPU  3794  without translating CUDA source code  3710  to HIP source code  3730 . In at least one embodiment, an indirect CUDA flow translates CUDA source code  3710  to HIP source code  3730  and then compiles HIP source code  3730  for execution on CPU  3790  and CUDA-enabled GPU  3794 . In at least one embodiment, a CUDA/HCC flow translates CUDA source code  3710  to HIP source code  3730  and then compiles HIP source code  3730  for execution on CPU  3790  and GPU  3792 . 
     A direct CUDA flow that may be implemented in at least one embodiment is depicted via dashed lines and a series of bubbles annotated A1-A3. In at least one embodiment and as depicted with bubble annotated A1, CUDA compiler  3750  receives CUDA source code  3710  and a CUDA compile command  3748  that configures CUDA compiler  3750  to compile CUDA source code  3710 . In at least one embodiment, CUDA source code  3710  used in a direct CUDA flow is written in a CUDA programming language that is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment and in response to CUDA compile command  3748 , CUDA compiler  3750  generates host executable code  3770 ( 1 ) and CUDA device executable code  3784  (depicted with bubble annotated A2). In at least one embodiment and as depicted with bubble annotated A3, host executable code  3770 ( 1 ) and CUDA device executable code  3784  may be executed on, respectively, CPU  3790  and CUDA-enabled GPU  3794 . In at least one embodiment, CUDA device executable code  3784  includes, without limitation, binary code. In at least one embodiment, CUDA device executable code  3784  includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime. 
     An indirect CUDA flow that may be implemented in at least one embodiment is depicted via dotted lines and a series of bubbles annotated B1-B6. In at least one embodiment and as depicted with bubble annotated B1, CUDA to HIP translation tool  3720  receives CUDA source code  3710 . In at least one embodiment and as depicted with bubble annotated B2, CUDA to HIP translation tool  3720  translates CUDA source code  3710  to HIP source code  3730 . In at least one embodiment and as depicted with bubble annotated B3, HIP compiler driver  3740  receives HIP source code  3730  and determines that target device  3746  is CUDA-enabled. 
     In at least one embodiment and as depicted with bubble annotated B4, HIP compiler driver  3740  generates HIP/NVCC compilation command  3742  and transmits both HIP/NVCC compilation command  3742  and HIP source code  3730  to CUDA compiler  3750 . In at least one embodiment and as described in greater detail in conjunction with  FIG.  37 B , HIP/NVCC compilation command  3742  configures CUDA compiler  3750  to compile HIP source code  3730  using, without limitation, a HIP to CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to HIP/NVCC compilation command  3742 , CUDA compiler  3750  generates host executable code  3770 ( 1 ) and CUDA device executable code  3784  (depicted with bubble annotated B5). In at least one embodiment and as depicted with bubble annotated B6, host executable code  3770 ( 1 ) and CUDA device executable code  3784  may be executed on, respectively, CPU  3790  and CUDA-enabled GPU  3794 . In at least one embodiment, CUDA device executable code  3784  includes, without limitation, binary code. In at least one embodiment, CUDA device executable code  3784  includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime. 
     A CUDA/HCC flow that may be implemented in at least one embodiment is depicted via solid lines and a series of bubbles annotated C1-C6. In at least one embodiment and as depicted with bubble annotated C1, CUDA to HIP translation tool  3720  receives CUDA source code  3710 . In at least one embodiment and as depicted with bubble annotated C2, CUDA to HIP translation tool  3720  translates CUDA source code  3710  to HIP source code  3730 . In at least one embodiment and as depicted with bubble annotated C3, HIP compiler driver  3740  receives HIP source code  3730  and determines that target device  3746  is not CUDA-enabled. 
     In at least one embodiment, HIP compiler driver  3740  generates HIP/HCC compilation command  3744  and transmits both HIP/HCC compilation command  3744  and HIP source code  3730  to HCC  3760  (depicted with bubble annotated C4). In at least one embodiment and as described in greater detail in conjunction with  FIG.  37 C , HIP/HCC compilation command  3744  configures HCC  3760  to compile HIP source code  3730  using, without limitation, an HCC header and a HIP/HCC runtime library. In at least one embodiment and in response to HIP/HCC compilation command  3744 , HCC  3760  generates host executable code  3770 ( 2 ) and HCC device executable code  3782  (depicted with bubble annotated C5). In at least one embodiment and as depicted with bubble annotated C6, host executable code  3770 ( 2 ) and HCC device executable code  3782  may be executed on, respectively, CPU  3790  and GPU  3792 . 
     In at least one embodiment, after CUDA source code  3710  is translated to HIP source code  3730 , HIP compiler driver  3740  may subsequently be used to generate executable code for either CUDA-enabled GPU  3794  or GPU  3792  without re-executing CUDA to HIP translation tool  3720 . In at least one embodiment, CUDA to HIP translation tool  3720  translates CUDA source code  3710  to HIP source code  3730  that is then stored in memory. In at least one embodiment, HIP compiler driver  3740  then configures HCC  3760  to generate host executable code  3770 ( 2 ) and HCC device executable code  3782  based on HIP source code  3730 . In at least one embodiment, HIP compiler driver  3740  subsequently configures CUDA compiler  3750  to generate host executable code  3770 ( 1 ) and CUDA device executable code  3784  based on stored HIP source code  3730 . 
       FIG.  37 B  illustrates a system  3704  configured to compile and execute CUDA source code  3710  of  FIG.  37 A  using CPU  3790  and CUDA-enabled GPU  3794 , in accordance with at least one embodiment. In at least one embodiment, system  3704  includes, without limitation, CUDA source code  3710 , CUDA to HIP translation tool  3720 , HIP source code  3730 , HIP compiler driver  3740 , CUDA compiler  3750 , host executable code  3770 ( 1 ), CUDA device executable code  3784 , CPU  3790 , and CUDA-enabled GPU  3794 . 
     In at least one embodiment and as described previously herein in conjunction with  FIG.  37 A , CUDA source code  3710  includes, without limitation, any number (including zero) of global functions  3712 , any number (including zero) of device functions  3714 , any number (including zero) of host functions  3716 , and any number (including zero) of host/device functions  3718 . In at least one embodiment, CUDA source code  3710  also includes, without limitation, any number of calls to any number of functions that are specified in any number of CUDA APIs. 
     In at least one embodiment, CUDA to HIP translation tool  3720  translates CUDA source code  3710  to HIP source code  3730 . In at least one embodiment, CUDA to HIP translation tool  3720  converts each kernel call in CUDA source code  3710  from a CUDA syntax to a HIP syntax and converts any number of other CUDA calls in CUDA source code  3710  to any number of other functionally similar HIP calls. 
     In at least one embodiment, HIP compiler driver  3740  determines that target device  3746  is CUDA-enabled and generates HIP/NVCC compilation command  3742 . In at least one embodiment, HIP compiler driver  3740  then configures CUDA compiler  3750  via HIP/NVCC compilation command  3742  to compile HIP source code  3730 . In at least one embodiment, HIP compiler driver  3740  provides access to a HIP to CUDA translation header  3752  as part of configuring CUDA compiler  3750 . In at least one embodiment, HIP to CUDA translation header  3752  translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs to any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, CUDA compiler  3750  uses HIP to CUDA translation header  3752  in conjunction with a CUDA runtime library  3754  corresponding to CUDA runtime API  3702  to generate host executable code  3770 ( 1 ) and CUDA device executable code  3784 . In at least one embodiment, host executable code  3770 ( 1 ) and CUDA device executable code  3784  may then be executed on, respectively, CPU  3790  and CUDA-enabled GPU  3794 . In at least one embodiment, CUDA device executable code  3784  includes, without limitation, binary code. In at least one embodiment, CUDA device executable code  3784  includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime. 
       FIG.  37 C  illustrates a system  3706  configured to compile and execute CUDA source code  3710  of  FIG.  37 A  using CPU  3790  and non-CUDA-enabled GPU  3792 , in accordance with at least one embodiment. In at least one embodiment, system  3706  includes, without limitation, CUDA source code  3710 , CUDA to HIP translation tool  3720 , HIP source code  3730 , HIP compiler driver  3740 , HCC  3760 , host executable code  3770 ( 2 ), HCC device executable code  3782 , CPU  3790 , and GPU  3792 . 
     In at least one embodiment and as described previously herein in conjunction with  FIG.  37 A , CUDA source code  3710  includes, without limitation, any number (including zero) of global functions  3712 , any number (including zero) of device functions  3714 , any number (including zero) of host functions  3716 , and any number (including zero) of host/device functions  3718 . In at least one embodiment, CUDA source code  3710  also includes, without limitation, any number of calls to any number of functions that are specified in any number of CUDA APIs. 
     In at least one embodiment, CUDA to HIP translation tool  3720  translates CUDA source code  3710  to HIP source code  3730 . In at least one embodiment, CUDA to HIP translation tool  3720  converts each kernel call in CUDA source code  3710  from a CUDA syntax to a HIP syntax and converts any number of other CUDA calls in source code  3710  to any number of other functionally similar HIP calls. 
     In at least one embodiment, HIP compiler driver  3740  subsequently determines that target device  3746  is not CUDA-enabled and generates HIP/HCC compilation command  3744 . In at least one embodiment, HIP compiler driver  3740  then configures HCC  3760  to execute HIP/HCC compilation command  3744  to compile HIP source code  3730 . In at least one embodiment, HIP/HCC compilation command  3744  configures HCC  3760  to use, without limitation, a HIP/HCC runtime library  3758  and an HCC header  3756  to generate host executable code  3770 ( 2 ) and HCC device executable code  3782 . In at least one embodiment, HIP/HCC runtime library  3758  corresponds to HIP runtime API  3732 . In at least one embodiment, HCC header  3756  includes, without limitation, any number and type of interoperability mechanisms for HIP and HCC. In at least one embodiment, host executable code  3770 ( 2 ) and HCC device executable code  3782  may be executed on, respectively, CPU  3790  and GPU  3792 . 
       FIG.  38    illustrates an exemplary kernel translated by CUDA-to-HIP translation tool  3720  of  FIG.  37 C , in accordance with at least one embodiment. In at least one embodiment, CUDA source code  3710  partitions an overall problem that a given kernel is designed to solve into relatively coarse sub-problems that can independently be solved using thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads. In at least one embodiment, each sub-problem is partitioned into relatively fine pieces that can be solved cooperatively in parallel by threads within a thread block. In at least one embodiment, threads within a thread block can cooperate by sharing data through shared memory and by synchronizing execution to coordinate memory accesses. 
     In at least one embodiment, CUDA source code  3710  organizes thread blocks associated with a given kernel into a one-dimensional, a two-dimensional, or a three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads, and a grid includes, without limitation, any number of thread blocks. 
     In at least one embodiment, a kernel is a function in device code that is defined using a “_global_” declaration specifier. In at least one embodiment, the dimension of a grid that executes a kernel for a given kernel call and associated streams are specified using a CUDA kernel launch syntax  3810 . In at least one embodiment, CUDA kernel launch syntax  3810  is specified as “KernelName«&lt;GridSize, BlockSize, SharedMemorySize, Stream»&gt;(KernelArguments);”. In at least one embodiment, an execution configuration syntax is a “«&lt;...»&gt;” construct that is inserted between a kernel name (“KernelName”) and a parenthesized list of kernel arguments (“KernelArguments”). In at least one embodiment, CUDA kernel launch syntax  3810  includes, without limitation, a CUDA launch function syntax instead of an execution configuration syntax. 
     In at least one embodiment, “GridSize” is of a type dim3 and specifies the dimension and size of a grid. In at least one embodiment, type dim3 is a CUDA-defined structure that includes, without limitation, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, then z defaults to one. In at least one embodiment, if y is not specified, then y defaults to one. In at least one embodiment, the number of thread blocks in a grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, “BlockSize” is of type dim3 and specifies the dimension and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread that executes a kernel is given a unique thread ID that is accessible within the kernel through a built-in variable (e.g., “threadIdx”). 
     In at least one embodiment and with respect to CUDA kernel launch syntax  3810 , “SharedMemorySize” is an optional argument that specifies a number of bytes in a shared memory that is dynamically allocated per thread block for a given kernel call in addition to statically allocated memory. In at least one embodiment and with respect to CUDA kernel launch syntax  3810 , SharedMemorySize defaults to zero. In at least one embodiment and with respect to CUDA kernel launch syntax  3810 , “Stream” is an optional argument that specifies an associated stream and defaults to zero to specify a default stream. In at least one embodiment, a stream is a sequence of commands (possibly issued by different host threads) that execute in order. In at least one embodiment, different streams may execute commands out of order with respect to one another or concurrently. 
     In at least one embodiment, CUDA source code  3710  includes, without limitation, a kernel definition for an exemplary kernel “MatAdd” and a main function. In at least one embodiment, main function is host code that executes on a host and includes, without limitation, a kernel call that causes kernel MatAdd to execute on a device. In at least one embodiment and as shown, kernel MatAdd adds two matrices A and B of size NxN, where N is a positive integer, and stores the result in a matrix C. In at least one embodiment, main function defines a threadsPerBlock variable as 16 by 16 and a numBlocks variable as N/16 by N/16. In at least one embodiment, main function then specifies kernel call “MatAdd«&lt;numBlocks, threadsPerBlock»&gt;(A, B, C);”. In at least one embodiment and as per CUDA kernel launch syntax  3810 , kernel MatAdd is executed using a grid of thread blocks having a dimension N/16 by N/16, where each thread block has a dimension of 16 by 16. In at least one embodiment, each thread block includes 256 threads, a grid is created with enough blocks to have one thread per matrix element, and each thread in such a grid executes kernel MatAdd to perform one pair-wise addition. 
     In at least one embodiment, while translating CUDA source code  3710  to HIP source code  3730 , CUDA to HIP translation tool  3720  translates each kernel call in CUDA source code  3710  from CUDA kernel launch syntax  3810  to a HIP kernel launch syntax  3820  and converts any number of other CUDA calls in source code  3710  to any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax  3820  is specified as “hipLaunchKernelGGL(KernelName,GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);”. In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments has the same meaning in HIP kernel launch syntax  3820  as in CUDA kernel launch syntax  3810  (described previously herein). In at least one embodiment, arguments SharedMemorySize and Stream are required in HIP kernel launch syntax  3820  and are optional in CUDA kernel launch syntax  3810 . 
     In at least one embodiment, a portion of HIP source code  3730  depicted in  FIG.  38    is identical to a portion of CUDA source code  3710  depicted in  FIG.  38    except for a kernel call that causes kernel MatAdd to execute on a device. In at least one embodiment, kernel MatAdd is defined in HIP source code  3730  with the same “_global_” declaration specifier with which kernel MatAdd is defined in CUDA source code  3710 . In at least one embodiment, a kernel call in HIP source code  3730  is “hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);”, while a corresponding kernel call in CUDA source code  3710  is “MatAdd«&lt;numBlocks, threadsPerBlock»&gt;(A, B, C);”. 
       FIG.  39    illustrates non-CUDA-enabled GPU  3792  of  FIG.  37 C  in greater detail, in accordance with at least one embodiment. In at least one embodiment, GPU  3792  is developed by AMD corporation of Santa Clara. In at least one embodiment, GPU  3792  can be configured to perform compute operations in a highly-parallel fashion. In at least one embodiment, GPU  3792  is configured to execute graphics pipeline operations such as draw commands, pixel operations, geometric computations, and other operations associated with rendering an image to a display. In at least one embodiment, GPU  3792  is configured to execute operations unrelated to graphics. In at least one embodiment, GPU  3792  is configured to execute both operations related to graphics and operations unrelated to graphics. In at least one embodiment, GPU  3792  can be configured to execute device code included in HIP source code  3730 . 
     In at least one embodiment, GPU  3792  includes, without limitation, any number of programmable processing units  3920 , a command processor  3910 , an L2 cache  3922 , memory controllers  3970 , DMA engines  3980 ( 1 ), system memory controllers  3982 , DMA engines  3980 ( 2 ), and GPU controllers  3984 . In at least one embodiment, each programmable processing unit  3920  includes, without limitation, a workload manager  3930  and any number of compute units  3940 . In at least one embodiment, command processor  3910  reads commands from one or more command queues (not shown) and distributes commands to workload managers  3930 . In at least one embodiment, for each programmable processing unit  3920 , associated workload manager  3930  distributes work to compute units  3940  included in programmable processing unit  3920 . In at least one embodiment, each compute unit  3940  may execute any number of thread blocks, but each thread block executes on a single compute unit  3940 . In at least one embodiment, a workgroup is a thread block. 
     In at least one embodiment, each compute unit  3940  includes, without limitation, any number of SIMD units  3950  and a shared memory  3960 . In at least one embodiment, each SIMD unit  3950  implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each SIMD unit  3950  includes, without limitation, a vector ALU  3952  and a vector register file  3954 . In at least one embodiment, each SIMD unit  3950  executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize together and communicate via shared memory  3960 . 
     In at least one embodiment, programmable processing units  3920  are referred to as “shader engines.” In at least one embodiment, each programmable processing unit  3920  includes, without limitation, any amount of dedicated graphics hardware in addition to compute units  3940 . In at least one embodiment, each programmable processing unit  3920  includes, without limitation, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of render back ends, workload manager  3930 , and any number of compute units  3940 . 
     In at least one embodiment, compute units  3940  share L2 cache  3922 . In at least one embodiment, L2 cache  3922  is partitioned. In at least one embodiment, a GPU memory  3990  is accessible by all compute units  3940  in GPU  3792 . In at least one embodiment, memory controllers  3970  and system memory controllers  3982  facilitate data transfers between GPU  3792  and a host, and DMA engines  3980 ( 1 ) enable asynchronous memory transfers between GPU  3792  and such a host. In at least one embodiment, memory controllers  3970  and GPU controllers  3984  facilitate data transfers between GPU  3792  and other GPUs  3792 , and DMA engines  3980 ( 2 ) enable asynchronous memory transfers between GPU  3792  and other GPUs  3792 . 
     In at least one embodiment, GPU  3792  includes, without limitation, any amount and type of system interconnect that facilitates data and control transmissions across any number and type of directly or indirectly linked components that may be internal or external to GPU  3792 . In at least one embodiment, GPU  3792  includes, without limitation, any number and type of I/O interfaces (e.g., PCIe) that are coupled to any number and type of peripheral devices. In at least one embodiment, GPU  3792  may include, without limitation, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU  3792  implements a memory subsystem that includes, without limitation, any amount and type of memory controllers (e.g., memory controllers  3970  and system memory controllers  3982 ) and memory devices (e.g., shared memories  3960 ) that may be dedicated to one component or shared among multiple components. In at least one embodiment, GPU  3792  implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 cache  3922 ) that may each be private to or shared between any number of components (e.g., SIMD units  3950 , compute units  3940 , and programmable processing units  3920 ). 
       FIG.  40    illustrates how threads of an exemplary CUDA grid  4020  are mapped to different compute units  3940  of  FIG.  39   , in accordance with at least one embodiment. In at least one embodiment and for explanatory purposes only, grid  4020  has a GridSize of BX by BY by 1 and a BlockSize of TX by TY by 1. In at least one embodiment, grid  4020  therefore includes, without limitation, (BX * BY) thread blocks  4030  and each thread block  4030  includes, without limitation, (TX * TY) threads  4040 . Threads  4040  are depicted in  FIG.  40    as squiggly arrows. 
     In at least one embodiment, grid  4020  is mapped to programmable processing unit  3920 ( 1 ) that includes, without limitation, compute units  3940 ( 1 )- 3940 (C). In at least one embodiment and as shown, (BJ * BY) thread blocks  4030  are mapped to compute unit  3940 ( 1 ), and the remaining thread blocks  4030  are mapped to compute unit  3940 ( 2 ). In at least one embodiment, each thread block  4030  may include, without limitation, any number of warps, and each warp is mapped to a different SIMD unit  3950  of  FIG.  39   . 
     In at least one embodiment, warps in a given thread block  4030  may synchronize together and communicate through shared memory  3960  included in associated compute unit  3940 . For example and in at least one embodiment, warps in thread block  4030 (BJ, 1 ) can synchronize together and communicate through shared memory  3960 ( 1 ). For example and in at least one embodiment, warps in thread block  4030 (BJ+ 1 , 1 ) can synchronize together and communicate through shared memory  3960 ( 2 ). 
       FIG.  41    illustrates how to migrate existing CUDA code to Data Parallel C++ code, in accordance with at least one embodiment. Data Parallel C++ (DPC++) may refer to an open, standards-based alternative to single-architecture proprietary languages that allows developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and also perform custom tuning for a specific accelerator. DPC++ use similar and/or identical C and C++ constructs in accordance with ISO C++ which developers may be familiar with. DPC++ incorporates standard SYCL from The Khronos Group to support data parallelism and heterogeneous programming. SYCL refers to a cross-platform abstraction layer that builds on underlying concepts, portability and efficiency of OpenCL that enables code for heterogeneous processors to be written in a “single-source” style using standard C++. SYCL may enable single source development where C++ template functions can contain both host and device code to construct complex algorithms that use OpenCL acceleration, and then re-use them throughout their source code on different types of data. 
     In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code which can be deployed across diverse hardware targets. In at least one embodiment, a DPC++ compiler is used to generate DPC++ applications that can be deployed across diverse hardware targets and a DPC++ compatibility tool can be used to migrate CUDA applications to a multiplatform program in DPC++. In at least one embodiment, a DPC++ base tool kit includes a DPC++ compiler to deploy applications across diverse hardware targets; a DPC++ library to increase productivity and performance across CPUs, GPUs, and FPGAs; a DPC++ compatibility tool to migrate CUDA applications to multi-platform applications; and any suitable combination thereof. 
     In at least one embodiment, a DPC++ programming model is utilized to simply one or more aspects relating to programming CPUs and accelerators by using modern C++ features to express parallelism with a programming language called Data Parallel C++. DPC++ programming language may be utilized to code reuse for hosts (e.g., a CPU) and accelerators (e.g., a GPU or FPGA) using a single source language, with execution and memory dependencies being clearly communicated. Mappings within DPC++ code can be used to transition an application to run on a hardware or set of hardware devices that best accelerates a workload. A host may be available to simplify development and debugging of device code, even on platforms that do not have an accelerator available. 
     In at least one embodiment, CUDA source code  4100  is provided as an input to a DPC++ compatibility tool  4102  to generate human readable DPC++  4104 . In at least one embodiment, human readable DPC++  4104  includes inline comments generated by DPC++ compatibility tool  4102  that guides a developer on how and/or where to modify DPC++ code to complete coding and tuning to desired performance  4106 , thereby generating DPC++ source code  4108 . 
     In at least one embodiment, CUDA source code  4100  is or includes a collection of human-readable source code in a CUDA programming language. In at least one embodiment, CUDA source code  4100  is human-readable source code in a CUDA programming language. In at least one embodiment, a CUDA programming language is an extension of the C++ programming language that includes, without limitation, mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, device code is source code that, after compilation, is executable on a device (e.g., GPU or FPGA) and may include or more parallelizable workflows that can be executed on one or more processor cores of a device. In at least one embodiment, a device may be a processor that is optimized for parallel instruction processing, such as CUDA-enabled GPU, GPU, or another GPGPU, etc. In at least one embodiment, host code is source code that, after compilation, is executable on a host. In least one embodiment, some or all of host code and device code can be executed in parallel across a CPU and GPU/FPGA. In at least one embodiment, a host is a processor that is optimized for sequential instruction processing, such as CPU. CUDA source code  4100  described in connection with  FIG.  41    may be in accordance with those discussed elsewhere in this document. 
     In at least one embodiment, DPC++ compatibility tool  4102  refers to an executable tool, program, application, or any other suitable type of tool that is used to facilitate migration of CUDA source code  4100  to DPC++ source code  4108 . In at least one embodiment, DPC++ compatibility tool  4102  is a command-line-based code migration tool available as part of a DPC++ tool kit that is used to port existing CUDA sources to DPC++. In at least one embodiment, DPC++ compatibility tool  4102  converts some or all source code of a CUDA application from CUDA to DPC++ and generates a resulting file that is written at least partially in DPC++, referred to as human readable DPC++  4104 . In at least one embodiment, human readable DPC++  4104  includes comments that are generated by DPC++ compatibility tool  4102  to indicate where user intervention may be necessary. In at least one embodiment, user intervention is necessary when CUDA source code  4100  calls a CUDA API that has no analogous DPC++ API; other examples where user intervention is required are discussed later in greater detail. 
     In at least one embodiment, a workflow for migrating CUDA source code  4100  (e.g., application or portion thereof) includes creating one or more compilation database files; migrating CUDA to DPC++ using a DPC++ compatibility tool  4102  ; completing migration and verifying correctness, thereby generating DPC++ source code  4108 ; and compiling DPC++ source code  4108  with a DPC++ compiler to generate a DPC++ application. In at least one embodiment, a compatibility tool provides a utility that intercepts commands used when Makefile executes and stores them in a compilation database file. In at least one embodiment, a file is stored in JSON format. In at least one embodiment, an intercept-built command converts Makefile command to a DPC compatibility command. 
     In at least one embodiment, intercept-build is a utility script that intercepts a build process to capture compilation options, macro defs, and include paths, and writes this data to a compilation database file. In at least one embodiment, a compilation database file is a JSON file. In at least one embodiment, DPC++ compatibility tool  4102  parses a compilation database and applies options when migrating input sources. In at least one embodiment, use of intercept-build is optional, but highly recommended for Make or CMake based environments. In at least one embodiment, a migration database includes commands, directories, and files: command may include necessary compilation flags; directory may include paths to header files; file may include paths to CUDA files. 
     In at least one embodiment, DPC++ compatibility tool  4102  migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ wherever possible. In at least one embodiment, DPC++ compatibility tool  4102  is available as part of a tool kit. In at least one embodiment, a DPC++ tool kit includes an intercept-build tool. In at least one embodiment, an intercept-built tool creates a compilation database that captures compilation commands to migrate CUDA files. In at least one embodiment, a compilation database generated by an intercept-built tool is used by DPC++ compatibility tool  4102  to migrate CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, DPC++ compatibility tool  4102  generates human readable DPC++  4104  which may be DPC++ code that, as generated by DPC++ compatibility tool  4102 , cannot be compiled by DPC++ compiler and requires additional plumbing for verifying portions of code that were not migrated correctly, and may involve manual intervention, such as by a developer. In at least one embodiment, DPC++ compatibility tool  4102  provides hints or tools embedded in code to help developers manually migrate additional code that could not be migrated automatically. In at least one embodiment, migration is a one-time activity for a source file, project, or application. 
     In at least one embodiment, DPC++ compatibility tool 41002 is able to successfully migrate all portions of CUDA code to DPC++ and there may simply be an optional step for manually verifying and tuning performance of DPC++ source code that was generated. In at least one embodiment, DPC++ compatibility tool  4102  directly generates DPC++ source code  4108  which is compiled by a DPC++ compiler without requiring or utilizing human intervention to modify DPC++ code generated by DPC++ compatibility tool  4102 . In at least one embodiment, DPC++ compatibility tool generates compile-able DPC++ code which can be optionally tuned by a developer for performance, readability, maintainability, other various considerations; or any combination thereof. 
     In at least one embodiment, one or more CUDA source files are migrated to DPC++ source files at least partially using DPC++ compatibility tool  4102 . In at least one embodiment, CUDA source code includes one or more header files which may include CUDA header files. In at least one embodiment, a CUDA source file includes a &lt;cuda.h&gt; header file and a &lt;stdio.h&gt; header file which can be used to print text. In at least one embodiment, a portion of a vector addition kernel CUDA source file may be written as or related to:  
     
       
         
           
               
            
               
                 #include &lt;cuda.h&gt; 
               
               
                         #include &lt;stdio.h&gt; 
               
               
                         #define VECTOR SIZE 256 
               
               
                         [] global_ void VectorAddKernel(float* A, float* B, float* C) 
               
               
                         { 
               
               
                           A[threadIdx.x] = threadIdx.x + 1.0f; 
               
               
                          B[threadIdx.x] = threadIdx.x + 1.0f; 
               
               
                         }C[threadIdx.x] = A[threadIdx.x] + B[threadIdx.x]; 
               
               
                        int main() 
               
               
                         { 
               
               
                           float *d_A, *d_B, *d_C; 
               
               
                           cudaMalloc(&amp;d_A, VECTOR_SIZE*sizeof(float)); 
               
               
                           cudaMalloc(&amp;d B, VECTOR_SIZE*sizeof(float)); 
               
               
                           cudaMalloc(&amp;d_C, VECTOR_SIZE*sizeof(float)); 
               
               
                           VectorAddKernel&lt;&lt;&lt;1, VECTOR_SIZE&gt;»(d_A, d_B, d_C); 
               
               
                           float Result[VECTOR_SIZE] = { }; 
               
               
                           cudaMemcpy(Result, d_C, VECTOR_SIZE*sizeof(float), 
               
               
                         cudaMemcpyDeviceToHost); 
               
               
                           cudaFree(d _A); 
               
               
                           cudaFree(d _B); 
               
               
                           cudaFree(d_C); 
               
               
                          for (int i=0; i&lt;VECTOR_SIZE; i++ { 
               
               
                            if (i % 16 == 0) { 
               
               
                           }}printf(“\n”); 
               
               
                            printf(“%f”, Result[i]); 
               
               
                         }return 0; 
               
            
           
         
       
     
     In at least one embodiment and in connection with CUDA source file presented above, DPC++ compatibility tool  4102  parses a CUDA source code and replaces header files with appropriate DPC++ and SYCL header files. In at least one embodiment, DPC++ header files includes helper declarations. In CUDA, there is a concept of a thread ID and correspondingly, in DPC++ or SYCL, for each element there is a local identifier. 
     In at least one embodiment and in connection with CUDA source file presented above, there are two vectors A and B which are initialized and a vector addition result is put into vector C as part of VectorAddKernel(). In at least one embodiment, DPC++ compatibility tool  4102  converts CUDA thread IDs used to index work elements to SYCL standard addressing for work elements via a local ID as part of migrating CUDA code to DPC++ code. In at least one embodiment, DPC++ code generated by DPC++ compatibility tool  4102  can be optimized - for example, by reducing dimensionality of an nd _item, thereby increasing memory and/or processor utilization. 
     In at least one embodiment and in connection with CUDA source file presented above, memory allocation is migrated. In at least one embodiment, cudaMalloc() is migrated to a unified shared memory SYCL call malloc_device() to which a device and context is passed, relying on SYCL concepts such as platform, device, context, and queue. In at least one embodiment, a SYCL platform can have multiple devices (e.g., host and GPU devices); a device may have multiple queues to which jobs can be submitted; each device may have a context; and a context may have multiple devices and manage shared memory objects. 
     In at least one embodiment and in connection with CUDA source file presented above, a main() function invokes or calls VectorAddKernel() to add two vectors A and B together and store result in vector C. In at least one embodiment, CUDA code to invoke VectorAddKernelU is replaced by DPC++ code to submit a kernel to a command queue for execution. In at least one embodiment, a command group handler cgh passes data, synchronization, and computation that is submitted to the queue, parallel for is called for a number of global elements and a number of work items in that work group where VectorAddKernel() is called. 
     In at least one embodiment and in connection with CUDA source file presented above, CUDA calls to copy device memory and then free memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISO C++ code for printing a vector of floating point variables) is migrated as is, without being modified by DPC++ compatibility tool  4102 . In at least one embodiment, DPC++ compatibility tool  4102  modify CUDA APIs for memory setup and/or host calls to execute kernel on the acceleration device. In at least one embodiment and in connection with CUDA source file presented above, a corresponding human readable DPC++  4104  (e.g., which can be compiled) is written as or related to:  
     
       
         
           
               
            
               
                 #include &lt;CL/sycl.hpp&gt; 
               
               
                         #include &lt;dpct/dpct.hpp&gt; 
               
               
                         #define VECTOR SIZE 256 
               
               
                        void VectorAddKernel(float* A, float* B, float* C, 
               
               
                                                             sycl::nd_item&lt;3&gt; item_ct1) 
               
               
                         { 
               
               
                           A[item_ctl.get_local_id(2)] = item_ctl.get_local_id(2) + 1.0f; 
               
               
                          B[item_ct1.get_local_id(2)] = item_ctl.get_local_id(2) + 1.0f; 
               
               
                           C[item_ctl.get_ local _id(2)] = 
               
               
                         }A[item_ctl.get_ local id(2)] + B[item_ctl.get_ local id(2)]; 
               
               
                        int main() 
               
               
                         { 
               
               
                           float *d_A, *d_B, *d_C; 
               
               
                           d_A = (float *)sycl::malloc_device(VECTOR_SIZE * sizeof(float), 
               
               
                            dpct: :get_ current_device(), 
               
               
                            dpct: :get_ default_context()); 
               
               
                           d_B = (float *)sycl::malloc_device(VECTOR_SIZE * sizeof(float), 
               
               
                            dpct: :get_ current_device(), 
               
               
                            dpct: :get_ default_context()); 
               
               
                           d_C = (float *)sycl::malloc_device(VECTOR_SIZE * sizeof(float), 
               
               
                            dpct: :get_ current_device(), 
               
               
                            dpct: :get_ default_context()); 
               
               
                           dpct::get_default_queue_wait().submit([&amp;](sycl::handler &amp;cgh) { 
               
               
                             cgh.parallel_for( 
               
               
                               sycl::nd_range&lt;3&gt;(sycl::range&lt;3&gt;(1, 1, 1) * 
               
               
                                                               sycl::range&lt;3&gt;(1, 1, VECTOR_SIZE) * 
               
               
                                                               sycl::range&lt;3&gt;(1, 1, VECTOR_SIZE)), 
               
               
                               [=](sycl::nd_items&lt;3&gt; item_ctl) { 
               
               
                           });VectorAddKemel(d_A, d_B, d_C, item_ctl); 
               
               
                           float Result[VECTOR_SIZE] = { }; 
               
               
                           dpct::getdefault_ queue _wait() 
               
               
                             .memcpy(Result, d_C, VECTOR_SIZE * sizeof(float)) 
               
               
                             .wait(); 
               
               
                           sycl: :free(d_A, dpct: : get_default_context()); 
               
               
                           sycl: :free(d_B, dpct: :get_default_context()); 
               
               
                           sycl: :free(d_C, dpct: :get_default_context()); 
               
               
                          for (int i=0; i&lt;VECTOR_SIZE; i++ { 
               
               
                            if (i % 16 == 0) { 
               
               
                           }}printf(“\n”); 
               
               
                            printf(“%f”, Result[i]); 
               
               
                         }return 0; 
               
            
           
         
       
     
     In at least one embodiment, human readable DPC++  4104  refers to output generated by DPC++ compatibility tool  4102  and may be optimized in one manner or another. In at least one embodiment, human readable DPC++  4104  generated by DPC++ compatibility tool  4102  can be manually edited by a developer after migration to make it more maintainable, performance, or other considerations. In at least one embodiment, DPC++ code generated by DPC++ compatibility tool 41002 such as DPC++ disclosed can be optimized by removing repeat calls to get_current_device() and/or get_default_context() for each malloc_device() call. In at least one embodiment, DPC++ code generated above uses a 3 dimensional nd _range which can be refactored to use only a single dimension, thereby reducing memory usage. In at least one embodiment, a developer can manually edit DPC++ code generated by DPC++ compatibility tool  4102  replace uses of unified shared memory with accessors. In at least one embodiment, DPC++ compatibility tool  4102  has an option to change how it migrates CUDA code to DPC++ code. In at least one embodiment, DPC++ compatibility tool  4102  is verbose because it is using a general template to migrate CUDA code to DPC++ code that works for a large number of cases. 
     In at least one embodiment, a CUDA to DPC++ migration workflow includes steps to: prepare for migration using intercept-build script; perform migration of CUDA projects to DPC++ using DPC++ compatibility tool  4102 ; review and edit migrated source files manually for completion and correctness; and compile final DPC++ code to generate a DPC++ application. In at least one embodiment, manual review of DPC++ source code may be required in one or more scenarios including but not limited to: migrated API does not return error code (CUDA code can return an error code which can then be consumed by the application but SYCL uses exceptions to report errors, and therefore does not use error codes to surface errors); CUDA compute capability dependent logic is not supported by DPC++; statement could not be removed. In at least one embodiment, scenarios in which DPC++ code requires manual intervention may include, without limitation: error code logic replaced with (*,0) code or commented out; equivalent DPC++ API not available; CUDA compute capability-dependent logic; hardware-dependent API (clock()); missing features unsupported API; execution time measurement logic; handling built-in vector type conflicts; migration of cuBLAS API; and more. 
     In at least one embodiment, one or more techniques described herein utilize a oneAPI programming model. In at least one embodiment, a oneAPI programming model refers to a programming model for interacting with various compute accelerator architectures. In at least one embodiment, oneAPI refers to an application programming interface (API) designed to interact with various compute accelerator architectures. In at least one embodiment, a oneAPI programming model utilizes a DPC++ programming language. In at least one embodiment, a DPC++ programming language refers to a high-level language for data parallel programming productivity. In at least one embodiment, a DPC++ programming language is based at least in part on C and/or C++ programming languages. In at least one embodiment, a oneAPI programming model is a programming model such as those developed by Intel Corporation of Santa Clara, CA. 
     In at least one embodiment, oneAPI and/or oneAPI programming model is utilized to interact with various accelerator, GPU, processor, and/or variations thereof, architectures. In at least one embodiment, oneAPI includes a set of libraries that implement various functionalities. In at least one embodiment, oneAPI includes at least a oneAPI DPC++ library, a oneAPI math kernel library, a oneAPI data analytics library, a oneAPI deep neural network library, a oneAPI collective communications library, a oneAPI threading building blocks library, a oneAPI video processing library, and/or variations thereof. 
     In at least one embodiment, a oneAPI DPC++ library, also referred to as oneDPL, is a library that implements algorithms and functions to accelerate DPC++ kernel programming. In at least one embodiment, oneDPL implements one or more standard template library (STL) functions. In at least one embodiment, oneDPL implements one or more parallel STL functions. In at least one embodiment, oneDPL provides a set of library classes and functions such as parallel algorithms, iterators, function object classes, range-based API, and/or variations thereof. In at least one embodiment, oneDPL implements one or more classes and/or functions of a C++ standard library. In at least one embodiment, oneDPL implements one or more random number generator functions. 
     In at least one embodiment, a oneAPI math kernel library, also referred to as oneMKL, is a library that implements various optimized and parallelized routines for various mathematical functions and/or operations. In at least one embodiment, oneMKL implements one or more basic linear algebra subprograms (BLAS) and/or linear algebra package (LAPACK) dense linear algebra routines. In at least one embodiment, oneMKL implements one or more sparse BLAS linear algebra routines. In at least one embodiment, oneMKL implements one or more random number generators (RNGs). In at least one embodiment, oneMKL implements one or more vector mathematics (VM) routines for mathematical operations on vectors. In at least one embodiment, oneMKL implements one or more Fast Fourier Transform (FFT) functions. 
     In at least one embodiment, a oneAPI data analytics library, also referred to as oneDAL, is a library that implements various data analysis applications and distributed computations. In at least one embodiment, oneDAL implements various algorithms for preprocessing, transformation, analysis, modeling, validation, and decision making for data analytics, in batch, online, and distributed processing modes of computation. In at least one embodiment, oneDAL implements various C++ and/or Java APIs and various connectors to one or more data sources. In at least one embodiment, oneDAL implements DPC++ API extensions to a traditional C++ interface and enables GPU usage for various algorithms. 
     In at least one embodiment, a oneAPI deep neural network library, also referred to as oneDNN, is a library that implements various deep learning functions. In at least one embodiment, oneDNN implements various neural network, machine learning, and deep learning functions, algorithms, and/or variations thereof. 
     In at least one embodiment, a oneAPI collective communications library, also referred to as oneCCL, is a library that implements various applications for deep learning and machine learning workloads. In at least one embodiment, oneCCL is built upon lower-level communication middleware, such as message passing interface (MPI) and libfabrics. In at least one embodiment, oneCCL enables a set of deep learning specific optimizations, such as prioritization, persistent operations, out of order executions, and/or variations thereof. In at least one embodiment, oneCCL implements various CPU and GPU functions. 
     In at least one embodiment, a oneAPI threading building blocks library, also referred to as oneTBB, is a library that implements various parallelized processes for various applications. In at least one embodiment, oneTBB is utilized for task-based, shared parallel programming on a host. In at least one embodiment, oneTBB implements generic parallel algorithms. In at least one embodiment, oneTBB implements concurrent containers. In at least one embodiment, oneTBB implements a scalable memory allocator. In at least one embodiment, oneTBB implements a work-stealing task scheduler. In at least one embodiment, oneTBB implements low-level synchronization primitives. In at least one embodiment, oneTBB is compiler-independent and usable on various processors, such as GPUs, PPUs, CPUs, and/or variations thereof. 
     In at least one embodiment, a oneAPI video processing library, also referred to as oneVPL, is a library that is utilized for accelerating video processing in one or more applications. In at least one embodiment, oneVPL implements various video decoding, encoding, and processing functions. In at least one embodiment, oneVPL implements various functions for media pipelines on CPUs, GPUs, and other accelerators. In at least one embodiment, oneVPL implements device discovery and selection in media centric and video analytics workloads. In at least one embodiment, oneVPL implements API primitives for zero-copy buffer sharing. 
     In at least one embodiment, a oneAPI programming model utilizes a DPC++ programming language. In at least one embodiment, a DPC++ programming language is a programming language that includes, without limitation, functionally similar versions of CUDA mechanisms to define device code and distinguish between device code and host code. In at least one embodiment, a DPC++ programming language may include a subset of functionality of a CUDA programming language. In at least one embodiment, one or more CUDA programming model operations are performed using a oneAPI programming model using a DPC++ programming language. 
     It should be noted that, while example embodiments described herein may relate to a CUDA programming model, techniques described herein can be utilized with any suitable programming model, such HIP, oneAPI, and/or variations thereof. 
     At least one embodiment of the disclosure can be described in view of the following clauses: 
     [0367] 1. A computer-implemented method of performing a task, comprising, performing a first set of tasks that obtain data used by a second set of tasks, the first set of tasks performed in serial using a first set of threads, and performing a first portion of the second set of tasks in parallel with the first set of tasks using a second set of threads, and performing a second portion of the second set of tasks in parallel with the first set of tasks, the second portion of the second set of tasks being time-interleaved with the first portion of the second set of tasks and performed using a third set of threads.   [0368] 2. The computer-implemented method of clause 1, wherein the task is a matrix multiplication, the second set of tasks calculates at least a portion of a result of the matrix multiplication, the first portion of the second set of tasks calculates a first tile of the result, and the second portion of the second set of tasks calculates a second tile of the result.   [0369] 3. The computer-implemented method of clause 1 or 2, wherein the first set of tasks transfers data to a memory accessible to the second set of tasks.   [0370] 4. The computer-implemented method of any of clauses 1 to 3, wherein the first portion of the second set of tasks is prevented from being performed in parallel with the second portion of the second set of tasks with a semaphore.   [0371] 5. The computer-implemented method of any of clauses 1 to 4, further comprising performing a first portion of a third set of tasks using the second set of threads after performing the first portion of the second set of tasks, and performing a second portion of the third set of tasks using the third set of threads after performing the second portion of the second set of tasks.   [0372] 6. The computer-implemented method of any of clauses 1 to 5, wherein performance of the first portion of the second set of tasks is started as a result of a portion of a memory being filled by the first set of tasks.   [0373] 7. The computer-implemented method of any of clauses 1 to 6, wherein performance of the first set of tasks is initiated by an indication that a portion of memory is available, the indication produced by the second set of tasks.   [0374] 8. The computer-implemented method of any of clauses 1 to 7, wherein the first set of threads, the second set of threads, and the third set of threads are threads in a cooperative thread array.   [0375] 9. A computer system comprising one or more processors and non-transitory computer-readable memory storing executable instructions that, as a result of being executed by the one or more processors, cause the computer system to perform a task by at least causing a first set of tasks to be performed in serial by a first set of threads of a multiprocessing system, the first set of tasks comprising one or more tasks to transfer data to a memory of the multiprocessing system, causing a first portion of a second set of tasks to be performed by a second set of threads of the multiprocessing system, the first portion of the second set of tasks comprising one or more tasks to perform calculations on the data to produce a first portion of results, causing a second portion of the second set of tasks to be performed by a third set of threads of the multiprocessing system, the second portion of the second set of tasks comprising one or more tasks to perform calculations on the data to produce a second portion of results, the first portion of the second set of tasks being performed in serial with the second portion of the second set of tasks, and causing the first and second portions of the results to be transferred to a memory of the computer system.   [0376] 10. The computer system of clause 9, wherein the task is a matrix multiplication, the second set of tasks calculates at least a portion of a result of the matrix multiplication, the first portion of the second set of tasks calculates a first tile of the result, and the second portion of the second set of tasks calculates a second tile of the result.   [0377] 11. The computer system of clause 9 or 10, wherein the first set of tasks transfers data to memory accessible by the second set of tasks.   [0378] 12. The computer system of any of clauses 9 to 11, wherein the first portion of the second set of tasks is prevented from being performed in parallel with the second portion of the second set of tasks with a semaphore.   [0379] 13. The computer system of any of clauses 9 to 12, wherein the executable instructions, as a result of being executed by the one or more processors, further cause the computer system to perform the task by at least, performing a first portion of a third set of tasks using the second set of threads after performing the first portion of the second set of tasks, and performing a second portion of the third set of tasks using the third set of threads after performing the second portion of the second set of tasks.   [0380] 14. The computer system of any of clauses 9 to 13, wherein performance of the first portion of the second set of tasks is started as a result of a portion of a memory being filled by the first set of tasks.   [0381] 15. The computer system of any of clauses 9 to 14, wherein performance of the first set of tasks is initiated by an indication that a portion of memory is available, the indication produced by the second set of tasks.   [0382] 16. The computer system of any of clauses 9 to 15, wherein the first set of threads, the second set of threads, and the third set of threads are threads in a cooperative thread array.   [0383] 17. A processor, comprising one or more circuits to perform a task by at least, using a first set of threads to perform a first task that provides data to a second set of threads and a third set of threads, beginning performing a first part of a second task with the second set of threads before using the first set of threads to provide the data to a third set of threads, performing a second part of the second task with the third set of threads, and providing a result of the task based at least in part on results of the first and second parts of the second task.   [0384] 18. The processor of clause 17, wherein the task is a matrix multiplication, the second task calculates at least a portion of a result of the matrix multiplication, the first part of the second task calculates a first tile of the result, and the second part of the second task calculates a second tile of the result.   [0385] 19. The processor of clause 17 or 18, wherein the first task transfers data to memory accessible by the second task.   [0386] 20. The processor of any of clauses 17 to 19, wherein the first part of the second task is prevented from being performed in parallel with the second part of the second task with a semaphore.   [0387] 21. The processor of any of clauses 17 to 20, wherein the one or more circuits perform the task by further performing a first portion of a third set of tasks using the second set of threads after performing the first portion of the second task, and performing a second portion of the third set of tasks using the third set of threads after performing the second portion of the second task.   [0388] 22. The processor of any of clauses 17 to 21, wherein performance of the first part of the second task is started as a result of a part of a memory being filled by the first task.   [0389] 23. The processor of any of clauses 17 to 22, wherein performance of the first task is initiated by an indication that a portion of memory is available, the indication produced by the second task.   [0390] 24. The processor of any of clauses 17 to 23, wherein the first set of threads, the second set of threads, and the third set of threads are threads in a cooperative thread array.   

     Other variations are within spirit of present disclosure. Thus, while disclosed techniques are susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in drawings and have been described above in detail. It should be understood, however, that there is no intention to limit disclosure to specific form or forms disclosed, but on contrary, intention is to cover all modifications, alternative constructions, and equivalents falling within spirit and scope of disclosure, as defined in appended claims. 
     Use of terms “a” and “an” and “the” and similar referents in context of describing disclosed embodiments (especially in context of following claims) are to be construed to cover both singular and plural, unless otherwise indicated herein or clearly contradicted by context, and not as a definition of a term. Terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (meaning “including, but not limited to,”) unless otherwise noted. term “connected,” when unmodified and referring to physical connections, is to be construed as partly or wholly contained within, attached to, or joined together, even if there is something intervening. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within range, unless otherwise indicated herein and each separate value is incorporated into specification as if it were individually recited herein. Use of term “set” (e.g., “a set of items”) or “subset” unless otherwise noted or contradicted by context, is to be construed as a nonempty collection comprising one or more members. Further, unless otherwise noted or contradicted by context, term “subset” of a corresponding set does not necessarily denote a proper subset of corresponding set, but subset and corresponding set may be equal. 
     Conjunctive language, such as phrases of form “at least one of A, B, and C,” or “at least one of A, B and C,” unless specifically stated otherwise or otherwise clearly contradicted by context, is otherwise understood with context as used in general to present that an item, term, etc., may be either A or B or C, or any nonempty subset of set of A and B and C. For instance, in illustrative example of a set having three members, conjunctive phrases “at least one of A, B, and C” and “at least one of A, B and C” refer to any of following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language is not generally intended to imply that certain embodiments require at least one of A, at least one of B and at least one of C each to be present. In addition, unless otherwise noted or contradicted by context, term “plurality” indicates a state of being plural (e.g., “a plurality of items” indicates multiple items). A number of items in a plurality is at least two, but can be more when so indicated either explicitly or by context. Further, unless stated otherwise or otherwise clear from context, phrase “based on” means “based at least in part on” and not “based solely on.” 
     Operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, a process such as those processes described herein (or variations and/or combinations thereof) is performed under control of one or more computer systems configured with executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs or one or more applications) executing collectively on one or more processors, by hardware or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium, for example, in form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transitory signals (e.g., a propagating transient electric or electromagnetic transmission) but includes non-transitory data storage circuitry (e.g., buffers, cache, and queues) within transceivers of transitory signals. In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media having stored thereon executable instructions (or other memory to store executable instructions) that, when executed (e.g., as a result of being executed) by one or more processors of a computer system, cause computer system to perform operations described herein. A set of non-transitory computer-readable storage media, in at least one embodiment, comprises multiple non-transitory computer-readable storage media and one or more of individual non-transitory storage media of multiple non-transitory computer-readable storage media lack all of code while multiple non-transitory computer-readable storage media collectively store all of code. In at least one embodiment, executable instructions are executed such that different instructions are executed by different processors — for example, a non-transitory computer-readable storage medium store instructions and a main central processing unit (“CPU”) executes some of instructions while a graphics processing unit (“GPU”) executes other instructions. In at least one embodiment, different components of a computer system have separate processors and different processors execute different subsets of instructions. 
     Accordingly, in at least one embodiment, computer systems are configured to implement one or more services that singly or collectively perform operations of processes described herein and such computer systems are configured with applicable hardware and/or software that enable performance of operations. Further, a computer system that implements at least one embodiment of present disclosure is a single device and, in another embodiment, is a distributed computer system comprising multiple devices that operate differently such that distributed computer system performs operations described herein and such that a single device does not perform all operations. 
     Use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate embodiments of disclosure and does not pose a limitation on scope of disclosure unless otherwise claimed. No language in specification should be construed as indicating any non-claimed element as essential to practice of disclosure. 
     All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein. 
     In description and claims, terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms may be not intended as synonyms for each other. Rather, in particular examples, “connected” or “coupled” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. 
     Unless specifically stated otherwise, it may be appreciated that throughout specification terms such as “processing,” “computing,” “calculating,” “determining,” or like, refer to action and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities within computing system’s registers and/or memories into other data similarly represented as physical quantities within computing system’s memories, registers or other such information storage, transmission or display devices. 
     In a similar manner, term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory and transform that electronic data into other electronic data that may be stored in registers and/or memory. As non-limiting examples, “processor” may be a CPU or a GPU. A “computing platform” may comprise one or more processors. As used herein, “software” processes may include, for example, software and/or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Also, each process may refer to multiple processes, for carrying out instructions in sequence or in parallel, continuously or intermittently. Terms “system” and “method” are used herein interchangeably insofar as system may embody one or more methods and methods may be considered a system. 
     In at least one embodiment, an arithmetic logic unit is a set of combinational logic circuitry that takes one or more inputs to produce a result. In at least one embodiment, an arithmetic logic unit is used by a processor to implement mathematical operation such as addition, subtraction, or multiplication. In at least one embodiment, an arithmetic logic unit is used to implement logical operations such as logical AND/OR or XOR. In at least one embodiment, an arithmetic logic unit is stateless, and made from physical switching components such as semiconductor transistors arranged to form logical gates. In at least one embodiment, an arithmetic logic unit may operate internally as a stateful logic circuit with an associated clock. In at least one embodiment, an arithmetic logic unit may be constructed as an asynchronous logic circuit with an internal state not maintained in an associated register set. In at least one embodiment, an arithmetic logic unit is used by a processor to combine operands stored in one or more registers of the processor and produce an output that can be stored by the processor in another register or a memory location. 
     In at least one embodiment, as a result of processing an instruction retrieved by the processor, the processor presents one or more inputs or operands to an arithmetic logic unit, causing the arithmetic logic unit to produce a result based at least in part on an instruction code provided to inputs of the arithmetic logic unit. In at least one embodiment, the instruction codes provided by the processor to the ALU are based at least in part on the instruction executed by the processor. In at least one embodiment combinational logic in the ALU processes the inputs and produces an output which is placed on a bus within the processor. In at least one embodiment, the processor selects a destination register, memory location, output device, or output storage location on the output bus so that clocking the processor causes the results produced by the ALU to be sent to the desired location. 
     In present document, references may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. Process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways such as by receiving data as a parameter of a function call or a call to an application programming interface. In some implementations, process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transferring data via a serial or parallel interface. In another implementation, process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transferring data via a computer network from providing entity to acquiring entity. References may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transferring data as an input or output parameter of a function call, a parameter of an application programming interface or interprocess communication mechanism. 
     Although discussion above sets forth example implementations of described techniques, other architectures may be used to implement described functionality, and are intended to be within scope of this disclosure. Furthermore, although specific distributions of responsibilities are defined above for purposes of discussion, various functions and responsibilities might be distributed and divided in different ways, depending on circumstances. 
     Furthermore, although subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that subject matter claimed in appended claims is not necessarily limited to specific features or acts described. Rather, specific features and acts are disclosed as exemplary forms of implementing the claims.