Patent Publication Number: US-9899263-B2

Title: Method of forming layout design

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application claims the benefit to and is a continuation of U.S. patent application Ser. No. 14/484,588, filed on Sep. 12, 2014, and entitled “METHOD OF FORMING LAYOUT DESIGN,” which application is incorporated herein by reference. 
    
    
     BACKGROUND 
     An integrated circuit (IC) is fabricated according to a layout design usable to form a plurality of masks for selectively forming or removing various layers of features, such as active regions, gate electrodes, various layers of isolation structures, and/or various layers of conductive structures. In some applications, an IC includes transistors having different threshold voltages. In one example, the transistors in the cells along a critical speed path of the IC having lower threshold voltages than those in the cells along a non-critical speed path of the IC. In another example, the gate structures at cell boundaries constitute dummy transistors and are adjusted to have higher threshold voltages than other functional transistors for reducing the current leakage through the dummy transistors. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1A  is a diagram of a portion of a layout design of a circuit in accordance with some embodiments. 
         FIG. 1B  is a diagram of a portion of a layout design of another circuit in accordance with some embodiments. 
         FIG. 1C  is a diagram of a portion of the layout design corresponding to the circuit of  FIG. 1A  or  FIG. 1B  in accordance with some embodiments. 
         FIG. 2  is a flow chart of a method of forming a layout design in accordance with some embodiments. 
         FIGS. 3A-3I  are diagrams of portions of various layout designs showing various examples for illustrating the operation of the method depicted in  FIG. 2  in accordance with some embodiments. 
         FIGS. 4A-4B  are cross-sectional views of portions of different ICs usable for illustrating two different threshold voltage tuning processes in accordance with some embodiments. 
         FIGS. 5A-5B  are cross-sectional views of a portion of an IC usable for illustrating a gate structure trimming process in accordance with some embodiments. 
         FIG. 6  is a flow chart of a method of fabricating an IC in accordance with some embodiments. 
         FIG. 7  is a block diagram of a layout designing system in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     In some embodiments, a layout layer usable to for a plurality of gate structures has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. Also, a mask layout layer usable for forming a mask defining the areas for performing an electrical characteristic adjustment process of the resulting transistors has a minimum pitch equal the predetermined pitch. Compared with a mask layout layer having a minimum pitch greater than twice the predetermined pitch, the cost for forming a mask according the present disclosure is greater, but the overall gate density of the resulting integrated circuit (IC) is higher. In some embodiments, the overall cost for fabricating an IC according to the present disclosure is in fact lower than that fabricated according to a mask layout layer having a minimum pitch greater than twice the predetermined pitch. 
       FIG. 1A  is a diagram of a portion of a layout design  100 A of a circuit in accordance with some embodiments. Layout design  100 A depicts overlapping layout patterns from various layout layers of layout design  100 A. Some layout patterns and some layout layers of layout design  100 A are simplified or omitted. Layout design  100 A depicts a non-limiting example for facilitating the illustration of the present disclosure. 
     Layout design  100 A includes a first oxide diffusion (OD) layout pattern  102 , a second OD layout pattern  104 , a plurality of gate structure layout patterns  121 ,  123 ,  125 ,  127 , and  129 , a plurality of conductive feature layout patterns  132 ,  134 ,  136 ,  142 ,  144 , and  146 , and a plurality of via layout patterns  150 . Layout design  100 A also includes a first power layout pattern  162 , a second power layout pattern  164 , and a gate structure cutting layout pattern  166 . The components depicted in  FIG. 1A  are arranged to form two logic cells  172  and  174  encompassed by cell boundaries  176  and  178 , respectively. 
     Cell boundary  176  has an upper edge  176   a  ( FIG. 1C ) running through the middle of the power layout pattern  162 , a lower edge  176   b  ( FIG. 1C ) running through the middle of the power layout pattern  164 , a left edge  176   c  ( FIG. 1C ) overlapping gate structure layout pattern  121 , and a right edge  176   d  ( FIG. 1C ) overlapping gate structure layout pattern  125 . Cell boundary  178  has an upper edge  178   a  ( FIG. 1C ) running through the middle of the power layout pattern  162 , a lower edge  178   b  ( FIG. 1C ) running through the middle of the power layout pattern  164 , a left edge  178   c  ( FIG. 1C ) overlapping gate structure layout pattern  125 , and a right edge  178   d  ( FIG. 1C ) overlapping gate structure layout pattern  129 . In the embodiment depicted in  FIG. 1A , the right edge  176   d  of cell boundary  176  and the left edge  176   c  of cell boundary  178  also overlap. 
     OD layout pattern  102  is usable to form an N-well region extending along a direction X through cells  172  and  174 ; and OD layout pattern  104  is usable to form a P-well region extending along direction X through cells  172  and  174 . Power layout pattern  162  is usable to form a power rail extending along direction X through cells  172  and  174  and configured to carry a power supply voltage; and power layout pattern  164  is usable to form a power rail extending along direction X through cells  172  and  174  and configured to carry a ground references voltage. 
     Conductive feature layout pattern  132  is usable to form a conductive feature connecting the N-well region defined by OD layout pattern  102  and the power rail defined by power layout pattern  162  through a via plug defined by a corresponding via layout pattern  150 . Conductive feature layout pattern  134  is usable to form a conductive feature connecting the P-well region defined by OD layout pattern  104  and the power rail defined by power layout pattern  164  through a via plug defined by a corresponding via layout pattern  150 . Conductive feature layout pattern  136  is usable to form a conductive feature connecting the N-well region defined by OD layout pattern  102  and the P-well region defined by OD layout pattern  104 . Gate structure layout pattern  123  is between conductive feature layout pattern  136  and conductive feature layout patterns  132  and  134  and is usable to form gate structures over the N-well region and the P-well region. 
     Gate structure layout patterns  121 ,  123 ,  125 ,  127 , and  129  extend along a direction Y and have a pitch P G  measurable along direction X. Gate structure layout patterns  121 ,  123 ,  125 ,  127 , and  129  are usable to form a plurality of hard mask features or gate electrode features from which a plurality of gate electrodes is made. In some embodiments, the pitch P G  is smaller than a spatial resolution of a predetermined lithographic technology, and therefore gate structure layout patterns  121 ,  123 ,  125 ,  127 , and  129  are usable for a multiple-patterning process based on the predetermined lithographic technology. 
     Gate structure layout pattern  123 , conductive feature layout pattern  132 , and conductive feature layout pattern  136  are usable of forming a P-type transistor having a source (corresponding to layout pattern  132 ), a drain (layout pattern  136 ), and a gate (layout pattern  123 ). Gate structure layout pattern  123 , conductive feature layout pattern  134 , and conductive feature layout pattern  136  are usable of forming an N-type transistor (corresponding to layout pattern  134 ), a drain (layout pattern  136 ), and a gate (layout pattern  123 ). The above-listed features together are usable of forming an inverter having an input (corresponding to layout pattern  123 ) and an output (layout pattern  136 ). As such, cell  172  is an inverter cell. 
     In cell  174 , gate structure layout pattern  127  corresponds to gate structure layout pattern  123 ; conductive feature layout pattern  142  corresponds to conductive feature layout pattern  132 ; conductive feature layout pattern  144  corresponds to conductive feature layout pattern  134 ; and conductive feature layout pattern  146  corresponds to conductive feature layout pattern  136 . Therefore, gate structure layout pattern  127 , conductive feature layout pattern  142 , and conductive feature layout pattern  146  are usable of forming a P-type transistor; gate structure layout pattern  127 , conductive feature layout pattern  144 , and conductive feature layout pattern  146  are usable of forming an N-type transistor; and cell  174  is also an inverter cell. 
     Gate structure layout pattern  125 , OD layout pattern  102 , and conductive feature layout patterns  136  and  146  are usable of forming a dummy P-type transistor  182 . Gate structure layout pattern  125 , OD layout pattern  104 , and conductive feature layout patterns  136  and  146  are also usable of forming a dummy N-type transistor  184 . In order to isolate cells  172  and  174 , dummy transistors  182  and  184  are turned off by tying the gate electrode (corresponding to layout pattern  125 ) of dummy transistor  182  to the power rail (layout pattern  162 ); tying the gate electrode (layout pattern  125 ) of dummy transistor  184  to the power rail (layout pattern  164 ); and removing a portion of the gate electrode corresponding to layout pattern  125  that is encompassed by gate structure cutting layout pattern  166 . 
       FIG. 1B  is a diagram of a portion of a layout design  100 B of a circuit in accordance with some embodiments. Components in  FIG. 1B  that are the same or similar to those in  FIG. 1A  are given the same or similar reference numbers. Layout design  100 B depicts another non-limiting example for facilitating the illustration of the present disclosure. 
     Compared with layout design  100 A, in layout design  100 B, the OD layout pattern  102  and  104  are replaced and/or supplemented by fin structure layout patterns  106  and  108 . Fin structure layout patterns  106  and  108  are usable to form a plurality of fin structures over a substrate of the circuit. The resulting transistors fabricated according to layout design  100 B have a multi-gate architecture and sometimes also known as FinFETs. 
       FIG. 1C  is a diagram of a portion of the layout design  100 C corresponding to the circuit of  FIG. 1A  or  FIG. 1B  in accordance with some embodiments. Components in  FIG. 1C  that are the same or similar to those in  FIG. 1A  of  FIG. 1B  are given the same or similar reference numbers. Layout design  100 C summarizes the examples as illustrated in  FIGS. 1A and 1B  and de-emphasized or omitted various layout patterns in  FIGS. 1A and 1B  for facilitating the illustration of the present disclosure. 
     As illustrated above in conjunction with  FIG. 1A , the dummy transistors  182  and  184  corresponding to gate electrode structure layout pattern  125  are turned off. To reduce the leakage current through the dummy transistors  182  and  184 , the dummy transistors are subject to be further processed to increase their threshold voltages. Therefore, layout patterns  192  and  194  are introduced to define the areas subject to an electrical characteristic tuning process. In some embodiments, the layout patterns  192  and  194  are also usable for adjusting the electrical characteristics of functional transistors, such as the transistors constituting the P-type and N-type transistors of the inverters corresponding to gate structure layout pattern  123  and  127 . 
     In some embodiments, layout patterns  192  and  194  are usable to define openings in a mask layer that expose the areas subject to the electrical characteristic tuning process. In some embodiments, layout patterns  192  and  194  are usable to define blocking areas in a mask layer for exposing the areas on which the electrical characteristic tuning process will be performed. In some embodiments, the electrical characteristic tuning process is usable for leakage reduction of a dummy transistor of the IC or power adjustment of a functional transistor of an integrated circuit. In some embodiments, suitable electrical characteristic tuning processes includes a threshold voltage tuning process or a gate structure trimming process. In some embodiments, the affected electrical characteristics of the transistors underwent the tuning processes includes their corresponding threshold voltages, turn-on current, or leakage current. 
     In some embodiments, layout patterns  192  and  194  have a width W 1  less than twice the pitch P G . In some embodiments, width W 1  equals pitch P G . In some embodiments, layout patterns  192  and  194  are formed on a mask layout layer, and the mask layout layer has a minimum pitch equals pitch P G . 
       FIG. 2  is a flow chart of a method  200  of forming a layout design in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method  200  depicted in  FIG. 2 , and that some other processes may only be briefly described herein. 
     Method  200  begins with operation  210 , where one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design are identified. The one or more identified areas correspond to one or more regions of the IC subject to an electrical characteristic tuning process for fabricating the IC. In some embodiments, the purpose of performing the electrical characteristic tuning process is to increase or decrease threshold voltages of corresponding transistors. 
     The method proceeds to operation  220 , where a set of layout patterns overlapping the one or more areas is generated in a mask layout layer of the layout design. The plurality of gate structure layout patterns has a predetermined pitch. The set of layout patterns has a minimum pitch equals to the predetermined pitch. In some embodiments, a width of a first layout pattern of the set of layout patterns or a gap between the first layout pattern and a second layout pattern set of layout patterns is less than twice the predetermined pitch of the plurality of gate structure layout patterns. In some embodiments, the width of the first layout pattern of the set of layout patterns is an integer multiple of the predetermined pitch. In some embodiments, the gap between the first layout pattern and the second layout pattern set of layout patterns is an integer multiple of the predetermined pitch. 
     Implementation of the method  200  of  FIG. 2  will now be explained by way of several examples.  FIGS. 3A-3I  are diagrams of portions of various layout designs in accordance with some embodiments. 
       FIG. 3A  is a diagram of a portion of a layout design  300 A for fabricating an IC in accordance with some embodiments. Layout design  300 A is usable to show various example layout patterns in the mask layout layer generated according to method  200 . 
     Layout design  300 A includes a power layout pattern  302  corresponding to power layout pattern  164  in  FIGS. 1A-1C , a first OD layout pattern  304 U corresponding to OD layout pattern  104 , and a second OD layout pattern  304 L also corresponding to OD layout pattern  104  and being an mirrored layout pattern of OD layout pattern  304 U about power layout pattern  302 . A reference line  306  corresponding to edges of logic cells, such as edge  176   b  and  178   b , runs through the middle of the power layout pattern  302 . 
     Layout design  300 A further includes a plurality of gate structure layout patterns  310   a - 310   s  and a set of layout patterns  320   a - 320   m  generated by a process corresponding to method  200 . The plurality of gate structure layout patterns  310   a - 310   s  extends along a direction Y and has a predetermined pitch P G  measurable along a direction X. In some embodiments, the pitch P G  is smaller than a spatial resolution of a predetermined lithographic technology, and therefore gate structure layout patterns  310   a - 310   s  are usable for a multiple-patterning process based on the predetermined lithographic technology. 
     One or more areas m the layout design  300 A occupied by one or more segments  312   a - 312   m  of the plurality of gate structure layout patterns  310   a - 310   s  are identified such that the one or more segments  312   a - 312   m  indicate the corresponding transistors that are subject to electrical characteristic tuning. An electrical characteristic tuning process will be performed for fabricating the IC, and the set of layout patterns  320   a - 320   m  corresponds to one or more openings or blocking features to be formed in a mask layer prior to performing the electrical characteristic tuning process. 
     Each layout pattern of the set of layout patterns  320   a - 320   m  has a width W 1  measurable along the direction X. Width W 1  is less than twice the predetermined pitch P G . In some embodiments, width W 1  equals predetermined pitch P G . The set of layout patterns  320   a - 320   m  demonstrates some of many possible layout combinations of the layout patterns of the mask layout layer. 
     In one example, layout pattern  320   a  has an edge overlapping a cell boundary represented by reference line  306  without abutting any other layout patterns of the mask layout layer. In another example, layout patterns  320   b  and  320   c  each have an edge overlapping the cell boundary  306 , and layout patterns  320   b  and  320   c  abut each other at the corresponding edges that overlap cell boundary  306 . 
     In another example, layout patterns  320   d  and  320   e  each have an edge overlapping the cell boundary  306 , and a corner of layout pattern  320   e  and a corner of layout pattern  320   e  on the edges overlapping cell boundary  306  abut each other. In another example, layout patterns  320   f  and  320   g  have an arrangement similar to that of layout patterns  320   d  and  320   e  except being mirrored about a reference axis in parallel with the direction Y. 
     In another example, layout patterns  320   h ,  320   i , and  320   j  each have an edge overlapping the cell boundary  306 . A left corner of layout pattern  320   i  and a corner of layout pattern  320   h  on the edges overlapping cell boundary  306  abut each other; and a right corner of layout pattern  320   i  and a corner of layout pattern  320   j  on the edges overlapping cell boundary  306  abut each other. Layout patterns  320   h  and  320   j  are separated by a gap having a width W 2  measurable along the direction X. Width W 2  is less than twice the predetermined pitch P G . In some embodiments, width W 2  equals predetermined pitch P G . In another example, layout patterns  320   k ,  3201 , and  320   m  have an arrangement similar to that of layout patterns  320   h ,  320   i , and  320   j  except being mirrored about a reference axis in parallel with the direction X. 
       FIGS. 3B-3I  are diagrams of portions of layout designs  300 B- 300 I in accordance with some embodiments.  FIGS. 3B-3I  depicts more example layout patterns as combinations based on the examples depicted in  FIG. 3A . Components in  FIGS. 3B-3I  that are the same or similar to those in  FIG. 3A  are given the same or similar reference numbers. Reference numbers for gate structure layout patterns and OD layout patterns are omitted for clarity. 
     In  FIG. 3B , layout design  300 B includes a set of layout patterns  330   a - 330   g  for forming the mask layer as illustrated above. Each layout patterns of the set of layout patterns  330   a - 330   g  has a width W 1  and is arranged along the reference line  306 . Layout patterns  330   a - 330   g  abut one another only at the corresponding corners overlapping cell boundary represented by reference line  306 . Layout patterns  330   a ,  330   c ,  330   e , and  330   g  are separated from one another by corresponding gaps having a width W 2 . Layout patterns  330   b ,  330   d , and  330   f  are separated from one another by corresponding gaps having a width W 2 . In some embodiments, width W 1  and width W 2  equal the predetermined pitch P G  of the gate structure layout patterns. 
     In  FIG. 3C , compared with layout design  300 B, layout patterns  330   c  and  330   e  are replaced by layout pattern  330   h  in layout design  300 C. Layout pattern  330   h  corresponds to an area covering three consecutive gate structure layout patterns and suitable to accommodate three unit layout patterns that has a width of the predetermined pitch P G . Here, layout pattern  330   h  has a width W 3  equals three times of the predetermined pitch P G . 
     In  FIG. 3D , compared with layout design  300 C, layout patterns  330   b - 330   f  are replaced by layout pattern  330   i  in layout design  300 D. Layout pattern  330   i  corresponds to an area covering five consecutive gate structure layout patterns and suitable to accommodate five unit layout patterns (such as layout pattern  320   a  in  FIG. 3A ) that has a width of the predetermined pitch P G . Here, layout pattern  330   i  has a width W 4  equals five times of the predetermined pitch P G . 
     In  FIG. 3E , compared with layout design  300 C, layout patterns  330   d  and  330   f  are replaced by layout pattern  330   j  in layout design  300 E. Layout pattern  330   j  corresponds to an area covering two consecutive gate structure layout patterns and suitable to accommodate two unit layout patterns that has a width of the predetermined pitch P G . Moreover, layout pattern  330   b  and  330   j  are separated by a gap having a width Ws. The gap between layout pattern  330   b  and  330   j  extends over an area corresponding to two consecutive gate structure layout patterns and suitable to accommodate two unit layout patterns that has a width of the predetermined pitch P G . Here, the width W 5  of the gap equals two times of the predetermined pitch P G . 
     As a variation of the embodiments depicted in  FIG. 3C  and  FIG. 3D , in some embodiments, a layout pattern has a width that is an integer multiple of the predetermined pitch P G . As a variation of the embodiment depicted in  FIG. 3E , in some embodiments, two layout patterns are separated by a gap having a width that is an integer multiple of the predetermined pitch P G . 
     For example, in  FIG. 3F , compared with layout design  300 E, layout pattern  330   h  is replaced by layout pattern  330   k  in layout design  300 F. Layout pattern  330   k  has a width of twice the predetermined pitch P G  instead of three times of the predetermined pitch P G  as layout pattern  330   h . A gap between layout pattern  330   k  and layout pattern  330   g  has a width of twice the predetermined pitch P G . In yet another example as depicted in  FIG. 3G , compared with layout design  300 E, layout patterns  330   b  and  330   j  are replaced by layout pattern  3301  in layout design  300 G. Layout pattern  3301  has a width of seven times the predetermined pitch P G . 
       FIG. 3H  depicts yet another example layout design  300 H, which includes layout patterns  330   a ,  330   m ,  330   n , and  3300 . Layout pattern  330   a  has a width of a single predetermined pitch P G . Layout pattern  330   m  has a width of four times the predetermined pitch P G . Layout pattern  330   n  has a width of three times the predetermined pitch P G . Layout pattern  330   m  has a width of twice the predetermined pitch P G . Layout pattern  330   n  abuts layout pattern  330   a  and layout pattern  330   m  at cell boundary  306 . Layout pattern  330   m  abuts layout pattern  330   n  as well as layout pattern  3300  at cell boundary  306 . Layout pattern  330   a  and layout pattern  330   m  are separated by a gap having a width of a single predetermined pitch P G . Layout pattern  330   n  and layout pattern  3300  are separated by a gap having a width of twice the predetermined pitch P G . 
       FIG. 3I  depicts yet another example layout design  300 I, which includes layout patterns  3301 ,  330   p ,  330   r , and  330   g . Layout pattern  330   g  has a width of a single predetermined pitch P G . Layout pattern  3301  has a width of seven times the predetermined pitch P G . Layout pattern  330   p  has a width of twice the predetermined pitch P G . Layout pattern  330   r  has a width of twice the predetermined pitch P G . Layout pattern  3301  abuts layout patterns  330   p ,  330   r , and  330   g  at cell boundary  306 . Layout pattern  330   p  and layout pattern  330   r  are separated by a gap having a width of a single predetermined pitch P G . Layout pattern  330   r  and layout pattern  330   g  are separated by a gap having a width of a single predetermined pitch P G . 
       FIG. 4A  is a cross-sectional view of a portion of an IC  400 A usable for illustrating a first example threshold voltage tuning processes in accordance with some embodiments.  FIG. 4A  is taken along a reference surface that does not cut through the corresponding gate structures. 
     IC  400 A includes a substrate  410 , a plurality of fin structures  412 ,  414 , and  416  protruding from an upper surface  410   a  of substrate  410 , an isolation layer  422  over the upper surface  410   a  of substrate  410  and partially cover the fin structures  412 ,  414 , and  416 , and a mask layer  424  over isolation layer  422  and fin structures  412  and  416 . Various components in IC  400 A are arranged in a first transistor region  432 , a second transistor region  434 , and a third transistor region  436 . First transistor region  432  corresponds to a transistor of a first type, and second transistor region  434  and third transistor region  436  correspond to transistor of a second type. In some embodiments, a transistor of the first type refers to an N-type transistor, and a transistor of the second type refers to a P-type transistor. In some embodiments, a transistor of the first type refers to a P-type transistor, and a transistor of the second type refers to an N-type transistor. 
     Mask layer  424  has an opening  426  defined therein and exposing a portion of fin structures  414 . In some embodiments, the mask layer  422  is formed according to a mask layout layer including the set of layout patterns  320   a - 320   m  in  FIG. 3A , or  330   a - 330   h  in  FIGS. 3B-3G . In some embodiments, the opening  426  is defined according to the set of layout patterns  320   a - 320   m  or  330   a - 330   h . In  FIG. 4A , transistors to be formed in transistor regions  434  and  436  are of the same type. However, the transistor formed in transistor region  434  is exposed by the opening  426  and thus will be process to adjust the electrical characteristic thereof. 
     For example, an implantation process  440  is performed to adjust an effective doping concentration at fin structures  414 . In some embodiments, implantation process  440  increases or decrease the effective doping concentration at fin structures  414  in comparison with a counterpart fin structures  416  usable to form transistors of the same type. As a result, a threshold voltage of the resulting transistor at transistor region  434  is different from that of the transistor in transistor region  436 . In some embodiments, if the resulting transistors in regions  434  and  436  are N-type transistors, increasing P-type doping concentration of fin structure  414  results in a smaller threshold voltage, and decreasing P-type doping concentration of fin structure  414  results in a greater threshold voltage. In some embodiments, if the resulting transistors in regions  434  and  436  are P-type transistors, increasing N-type doping concentration of fin structure  414  results in a smaller threshold voltage, and decreasing N-type doping concentration of fin structure  414  results in a greater threshold voltage. 
       FIG. 4B  is a cross-sectional view of a portion of an IC  400 B usable for illustrating a second example threshold voltage tuning processes in accordance with some embodiments. Components in  FIG. 4B  that are the same or similar to those in  FIG. 4A  are given the same reference numbers.  FIG. 4B  is taken along a reference surface that cuts through the corresponding gate structures  452 ,  454 , and  456 . 
     Compared with IC  400 A, instead of performing implantation process  440  in the opening  426 , gate electrode structure  454  is formed to have different material and/or structure than those of electrode structure  452  and  456 . In some embodiments, gate electrode structure  454  has a material having a work function metal different than that of gate electrode  456 . As a result, a threshold voltage of the resulting transistor at transistor region  434  is different from that of the transistor in transistor region  436 . 
     In some embodiments, the processes as illustrated in  FIGS. 4A and 4B  are both performed to adjust the threshold voltage of a transistor in an IC. In some embodiments, only one of the processes as illustrated by  FIGS. 4A and 4B  is performed to adjust the threshold voltage of a transistor in an IC. 
     In some embodiments, the dummy transistors corresponding to dummy transistors  182  and  184  in  FIG. 1A-1C  will be exposed or blocked according to the layout patterns corresponding to layout patterns  192  and  194  when performing the threshold voltage tuning processes. 
       FIGS. 5A-5B  are cross-sectional views of a portion of an IC  500  usable for illustrating a gate structure trimming process in accordance with some embodiments. 
     In  FIG. 5A , IC  500  includes a substrate  510 , a polysilicon layer  520  over substrate  510 , a plurality of hard mask features  532   a - 532   f  over polysilicon layer  520 , and a mask layer  542  over polysilicon layer  520  and hard mask features  532   a - 532   c  and  532   e - 532   f . Hard mask features  532   a - 532   f  are patterned according to a plurality of gate structure layout patterns, such as layout patterns  121 - 129  ( FIG. 1 ) or  310   a - 310   s  ( FIG. 3A ). Mask layer  542  has an opening  544  defined therein, and opening  544  is formed according to a mask layout layer having a set of layout patterns, such as layout patterns  320   a - 320   m  ( FIG. 3A ) or  330   a - 330   h  ( FIGS. 3B-3G ). In  FIG. 5A , a first etching process  550  is performed to reduce a width of hard mask features  532   d.    
     In  FIG. 5B , after the first etching process, hard mask features  532   d  is trimmed to become hard mask features  532   d ′, which has a smaller width. Mask layer  542  is removed, and then a second etching process  550  is performed to pattern polysilicon layer  520  into a plurality of polysilicon features  522 - 522   f . Polysilicon features  522   a - 522   f  are usable as gate structures or dummy gate structures subject to a subsequent gate replacement process. Because polysilicon feature  522   d  has a width smaller than that of other polysilicon features  522   a - 522   c  and  522   e - 522   f , a resulting transistor corresponding to polysilicon feature  522   d  has a faster operating speed than resulting transistors of the same type corresponding to polysilicon feature  522   a - 522   c  and  522   e - 522   f.    
     In some embodiments, the dummy transistors corresponding to dummy transistors  182  and  184  in  FIG. 1A-1C  will be blocked according to the layout patterns corresponding to layout patterns  192  and  194  when performing the gate structure trimming process. 
       FIG. 6  is a flow chart of a method  600  of fabricating an IC in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method  600  depicted in  FIG. 6 , and that some other processes may only be briefly described herein. 
     Method  600  begins with operation  610 , where a plurality of patterned features is formed according to a plurality of gate structure layout patterns, such as layout patterns  121 - 129  ( FIG. 1 ) or  310   a - 310   s  ( FIG. 3A ). The plurality of patterned features is formed using a multiple-patterning process based on a predetermined lithographic technology. The plurality of patterned features thus extends along a first direction corresponding to direction Y in  FIG. 3A  and has a predetermined pitch corresponding to pitch P G  in  FIG. 3A  measurable along direction X. In some embodiments, the pitch P G  is smaller than a spatial resolution of the predetermined lithographic technology. In some embodiments, the plurality of patterned features corresponds to hard mask features  532   a - 532   f  in  FIG. 5A  or polysilicon features formed according to hard mask features  522   a - 522   f.    
     The process proceeds to operation  620 , where a mask layer is formed over the plurality of patterned features. The mask layer includes one or more openings defined therein, and the one or more openings exposing one or more areas corresponding to one or more segments of the plurality of patterned features. In some embodiments, the mask layer corresponds to mask layer  542  in  FIG. 5A  with opening  544  defined therein. The one or more openings are defined according to a set of layout patterns of a mask layout layer, such as layout patterns  320   a - 320   m  or  330   a - 3301  in  FIGS. 3A-3G . Therefore, in some embodiments, the one or more openings have a minimal pitch that equals the predetermined pitch P G  of the plurality of patterned features. 
     The process proceeds to operation  630 , where an electrical characteristic tuning process is performed on the exposed one or more areas. In some embodiments, the electrical characteristic tuning process comprises a threshold voltage tuning process as illustrated in conjunction with  FIGS. 4A and 4B  or a gate structure trimming process as illustrated in conjunction with  FIG. 5 . 
       FIG. 7  is a block diagram of a layout designing system  700  in accordance with some embodiments. Layout designing system  700  is usable for implementing the method disclosed in  FIG. 2  and further explained in conjunction with  FIG. 1  and  FIGS. 3A-3G . 
     System  700  includes a hardware processor  710 , a non-transitory, computer readable storage medium  720 , an input/output interface  730  coupled to external circuitry, and a network interface  740  communicatively coupled with one another through a bus  750 . 
     Storage medium  720  is encoded with a set of executable instructions  722 . The processor  710  is configured to execute the set of executable instructions  722  in order to cause system  700  to be usable for performing a portion or all of the operations as depicted in  FIG. 2 . In some embodiments, the processor  710  is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. 
     In some embodiments, the computer readable storage medium  720  is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, the computer readable storage medium  720  includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In some embodiments using optical disks, the computer readable storage medium  720  includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD). 
     In some embodiments, the storage medium  720  stores the set of executable instructions  722  configured to cause system  700  to perform a method as depicted in  FIG. 2 . In some embodiments, the storage medium  720  also stores information needed for performing method  200  or generated during performing the method, such as layout design files  724 , identified segments of gate structure layout patterns  726 , and/or any intermediate date  728 . 
     Network interface  740  allows system  700  to communicate with a network  760 , to which one or more other computer systems are connected. Network interface  740  includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interface such as ETHERNET, USB, or IEEE-1394. In some embodiments, the method of  FIG. 2  is implemented in two or more system, and executable instructions or layout design information are exchanged between different systems  700  via the network  760 . 
     In accordance with one embodiment, a method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The one or more areas correspond to one or more regions of the IC subject to an electrical characteristic tuning process for fabricating the IC. The plurality of gate structure layout patterns extends along a first direction and has a predetermined pitch measurable along a second direction. The predetermined pitch is smaller than a spatial resolution of a predetermined lithographic technology. The set of layout patterns corresponds to one or more openings to be formed in a mask layer prior to performing the electrical characteristic tuning process. A first layout pattern of the set of layout patterns has a width measurable along the second direction, and the width of the first layout pattern is less than twice the predetermined pitch. 
     In accordance with another embodiment, a method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The one or more areas correspond to one or more regions of the IC subject to an electrical characteristic tuning process for fabricating the IC. The plurality of gate structure layout patterns extends along a first direction and has a predetermined pitch measurable along a second direction. The predetermined pitch is smaller than a spatial resolution of a predetermined lithographic technology. The set of layout patterns corresponds to one or more openings to be formed in a mask layer prior to performing the electrical characteristic tuning process. A first layout pattern and a second layout pattern of the set of layout patterns are separated by a first gap along the second direction, and a width of the first gap measurable along the second direction is less than twice the predetermined pitch. 
     In accordance with another embodiment, a layout design for fabricating an integrated circuit (IC) is disclosed. The Layout design includes a first layout layer and a second layout layer. The first layout layer includes a plurality of gate structure layout patterns. The plurality of gate structure layout patterns extends along a first direction and has a predetermined pitch measurable along a second direction, and the predetermined pitch is smaller than a spatial resolution of a predetermined lithographic technology. The second layout layer includes a set of mask layout patterns arranged based on one or more opening regions. The one or more opening regions overlap one or more of the plurality of gate structure layout patterns corresponding to one or more gate structures subject to an electrical characteristic tuning process. A first mask layout pattern of the set of mask layout patterns has a width measurable along the second direction, and the width of the first mask layout pattern is equal to the predetermined pitch. 
     One general aspect of embodiments described herein includes a method of manufacturing an integrated circuit (IC), the method including forming a plurality of gate structures, where at least one segment of the plurality of gate structures corresponds to a transistor to be subject to an electrical characteristic tuning process, the plurality of gate structures extending along a first direction and having a predetermined pitch measurable along a second direction, the predetermined pitch being smaller than a spatial resolution of a lithographic technology used to form the plurality of gate structures; depositing an insulating layer over the plurality of gate structures; and forming one or more openings in the insulating layer, the one or more openings having a width measurable along the second direction, the width of the respective openings being less than twice the predetermined pitch. 
     Another general aspect of embodiments described herein includes a method of manufacturing an integrated circuit (IC), the method including forming a plurality of transistors, the plurality of transistors including a plurality of source regions, a plurality of drain regions, and a plurality of gate structures overlying respective source regions and drain regions, the plurality of gate structures each extending along a first direction and having a predetermined pitch measurable along a second direction, the predetermined pitch being smaller than a spatial resolution of a lithographic technology used to form the plurality of gate structures; selecting a subset of the plurality of transistors for a tuning process; forming a patterned layer on the plurality of transistors, the patterned layer including a repeating pattern of features, the width of the features being less than twice the predetermined pitch; and performing the tuning process on the subset of transistors. 
     Yet another general aspect of embodiments described herein includes a method including: using a multiple patterning process, forming a plurality of gate structures, the plurality of gate structures extending along a first direction and having a predetermined pitch measurable along a second direction; depositing an insulating layer over the plurality of gate structures; forming one or more openings in the insulating layer, the one or more openings having a width measurable along the second direction, the width of the respective openings being less than twice the predetermined pitch; and performing an electrical characteristic tuning process on transistor structures exposed by the one or more openings 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.