Patent Publication Number: US-8537905-B2

Title: Method and system for adjusting interconnect voltage levels in low power high-speed differential interfaces

Description:
This invention relates generally to low power high-speed differential serial links, and in particular to a method and system for adjusting interconnect power levels in low power high-speed differential serial links. 
     In many low power devices such Cell Phones, PDAs, etc. parallel buses are more and more replaced by high-speed differential serial links for providing communication between various components, for example, different chips; a chip and a display; a base-band and an RF-module; a camera and a processor. 
     In high-speed differential serial links differential drivers are used for the generation of differential signals that are transmitted on pairs of conductors. The differential signals are referenced to each other rather than a ground potential. One of the differential signals in each differential signal pair is labeled “positive” or “true” while the other is labeled “negative” or “false”. A major advantage of high-speed differential serial links is a substantially lower power consumption and smaller size. 
     Using current CMOS technologies, high-speed differential serial links dissipate substantially less power than parallel buses. For example, a 400 mV differential voltage across a 100Ω transmission line requires a constant current of 4 mA. Therefore, using a voltage mode driver with a voltage supply of 1.2V the static or constant power dissipation is 4.8 mW, and using a current mode driver the constant power dissipation is approximately double, i.e. 9.6 mW. This power consumption of a few mW is considerably less than the power consumption of parallel buses, making high-speed differential serial links the preferred choice for data transmission in compact portable devices. However, while the power dissipated in high-speed differential serial links is low compared to parallel buses, it is still a major factor limiting integration and miniaturization of future generations of low power devices. 
     Therefore, it would be highly desirable to provide means for reducing power consumption in high-speed differential serial links. 
     It is, therefore, an object of the invention to provide a method and system for reducing power consumption in high-speed differential serial links by adjusting interconnect power levels. 
     In accordance with the present invention there is provided a method for adjusting interconnect power levels. A voltage regulating device in communication with a voltage supply port of a driver of a high-speed differential serial link is provided. The voltage regulating device receives at a control port a control signal indicative of a predetermined regulated voltage for provision to the driver for a pre-selected type of data transmission to a receiver via the high-speed differential serial link. The pre-selected type of data transmission has a corresponding interconnect power level. The voltage regulating device then provides the regulated supply voltage to the driver for transmission of a data signal according to the pre-selected type of data transmission to the receiver. 
     In accordance with another aspect of the invention there is provided a system for adjusting interconnect power levels that comprises a driver, a voltage regulating device, and control circuitry. The driver has a digital input port for receiving a digital data signal and differential output ports for being connected to a differential transmission line of a high-speed differential serial link. The driver converts the digital data signal into a differential signal for transmission via the differential transmission line to a receiver. The voltage regulating device is connected to a voltage supply port of the driver and comprises a control port for receiving a control signal. The voltage regulating device provides a regulated supply voltage to the driver in dependence upon the control signal. The control circuitry is in communication with the control port of the voltage regulating device and generates the control signal in dependence upon a pre-selected type of data transmission having a corresponding interconnect power level. The control signal is indicative of the regulated supply voltage with the regulated supply voltage being such that the differential signal has the corresponding interconnect power level. 
    
    
     
       Exemplary embodiments of the invention will now be described in conjunction with the following drawings, in which: 
         FIG. 1  is a simplified block diagram illustrating a SLVS driver and a receiver load; 
         FIG. 2  is a simplified block diagram illustrating the SLVS driver shown in  FIG. 1  in more detail; 
         FIG. 3  is a simplified block diagram illustrating the SLVS driver shown in  FIG. 2  with the NMOS switches being by ideal switches for illustrating power consumption of the SLVS driver; 
         FIG. 4   a  is a simplified block diagram of a preferred embodiment of a system for adjusting interconnect power levels according to the invention; 
         FIG. 4   b  is a simplified block diagram of a preferred embodiment of a voltage regulating device for use in the system shown in  FIG. 4   a ; and, 
         FIGS. 5   a  to  5   c  are simplified flow diagrams of three embodiments of a method for adjusting interconnect power levels according to the invention. 
     
    
    
     While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. 
     In the following, a preferred embodiment of the invention will be described in an implementation with a differential Scalable Low Voltage Signaling (SLVS) voltage driver. As will become evident to those of skill in the art, the invention is not limited to SLVS voltage drivers but also applicable to other voltage mode drivers as well as current mode drivers of high-speed differential serial links. In order to provide a better understanding, a state of the art example of a high-speed differential serial link—SLVS—will be shown, with reference to  FIGS. 1 to 3 . Of course, it is possible to derive the power consumption and options for reducing the same, as shown in the following example, in similar fashion for other applications. 
     Referring to  FIG. 1 , an example of a high-speed differential serial link employing a SLVS voltage driver with fixed output impedance is shown. A high-speed differential voltage driver  10  is connected to a receiver termination  14  via a differential transmission line  12 . It is noted that the transmission line  12  has no bearing on the static power dissipation and is used here for illustration only. 
       FIG. 2  shows a more detailed diagram of a Digital-To-Analog (D2A) driver of the SLVS link shown in  FIG. 1 . The D2A driver  10  is of a push-pull type with all NMOS switches—m 1  to m 4 . The top NMOS switches—m 1  and m 2 —are of follower type, i.e. the source—output—voltage follows the gate voltage, and the bottom switches—m 3  and m 4 —are normal operating devices. 
       FIG. 3  illustrates a simplified equivalent driver representation showing ideal switches in place of the NMOS switches and with resistors Rb=Rt=50Ω. In an ideal case, the pull up and the pull down structure each have 50Ω impedance. The total impedance RT from voltage source Vdde  16  to ground is then the summation of the pull-up impedance, the receiver impedance, and the pull-down impedance, i.e. RT=50Ω+100Ω+50Ω=200Ω. Since the driver  10  is a differential driver, a continuous current flows from the voltage source Vdde  16  into the resistor of the receiver termination  14  and then to ground, regardless of the path, i.e. which pull-up and pull-down switches are ON. The static power dissipation is then determined as follows:
 
 I ( vdde )= vdde/RT,  
 
with I(vdde) being the current to ground for a given supply voltage vdde from the voltage source Vdde  16 ;
 
 v (out)=100Ω* I ( vdde ),
 
with v(out) being the output voltage of the driver  10  and the receiver impedance being 100Ω; and,
 
 P ( vdde )= vdde*I ( vdde )= vdde   2   /RT,  
 
with P(vdde) being the dissipated power for the given supply voltage vdde.
 
For example, for a supply voltage vdde=0.8 V follows:
 
 I ( vdde )=4 mA;
 
 v (out)=400 mV; and,
 
 P ( vdde )=3.2 mW.
 
Using the above equations for supply voltages vdde=0.4V and 0.2 V, we obtain:
 
 I ( vdde )=2 mA and 1 mA;
 
 v (out)=200 mV and 100 mV; and,
 
 P ( vdde )=0.8 mW and 0.2 mW, respectively.
 
From the above equations follows, for example, that a reduction of the supply voltage vdde by a factor of 4 reduces the output voltage of the driver  10  by a factor of 4, while the dissipated power is reduced by a factor of 16. Therefore, a reduction of the output voltage by reducing the supply voltage vdde results in a substantial reduction of the dissipated power, i.e. power consumption.
 
     Referring to  FIGS. 4   a  and  4   b , a preferred embodiment of a system  100  for adjusting interconnect power levels according to the invention is shown. In the system  100  use is made of the fact that it is possible to supply a voltage mode driver—as well as a current mode driver—with a lower supply voltage while maintaining its characteristic impedance. The system includes the basic components as the system shown in  FIGS. 1 to 3 . For the sake of clarity, same reference numerals are used for same components. A digital signal received at digital input port  18  is converted in driver  10  into a corresponding differential signal and provided to output ports  20 A and  20 B connected to differential transmission line  12  for provision to receiver  14 . For adjusting the interconnect power levels between the driver  10  and the receiver  14  a voltage regulator  110  is interposed between the voltage source  16  and the driver  10 . The voltage regulator  110  provides, via port  111 , a regulated supply voltage vddeR to the driver  10  in dependence upon a control signal received from control circuitry  160 . Optionally, the control circuitry  160  is connected via receiver control port  144  to receiver control circuitry  142  of the receiver  14 . This allows, for example, controlling a receiver termination  15  and providing receiver feedback, as will be described below. 
       FIG. 4   b  shows an example embodiment of a voltage regulator  110  for use with the system  100  shown in  FIG. 4   a . A resistor ladder—or resistor divider— 118  connected via reference supply port  114  to a reference supply  116  and connected at an opposite end to ground provides multiple reference voltage steps to Analog Multiplexer  120 . For example, the reference supply  116  is a core voltage of the device or a bandgap reference. The Analog Multiplexer  120  selects a reference voltage in dependence upon a decoder control signal received from the control circuitry  160  at control port  112  and provides it to a direct input port  130  of amplifier  122  such as a high gain op-amp. Output port  123  of the amplifier  122  is connected to a gate of NMOS Follower  124  interposed between voltage source  16  and node  126  connected to the regulated supply voltage port  111 . Feedback loop  128  interposed between the node  126  and inverse input port  132  of the amplifier  122  ensures that the regulated output voltage is substantially the same as the selected reference voltage. High impedance RI to ground is used to provide a trickle current for maintaining the feedback loop  128 . Optionally, the regulated output voltage is decoupled by means of capacitor C 1 . Of course, the number of reference voltage steps is easily modified depending on the application. 
     Alternatively, other types of voltage regulating devices are implemented in the system  100 . For example, a high-speed “switcher” allows reducing the total power consumption approximately to the power dissipated in the driver  10 . 
     The addition of the voltage regulator  110 —or the switcher—does not impact the driver or receiver design. The voltage regulator  110  or the switcher is, preferably, implemented on a same chip  150  with the driver  10 . Alternatively, the voltage regulator  110 - or the switcher—is employed as an external component. 
     Optionally, the receiver  14  comprises switches  140 A and  140 B for switching resistor  15  IN for high-speed operation, and OUT for enabling reflective wave transmission during low-speed operation. In many cases it is possible to use a high-speed link in a low-speed mode. Using reflective wave transmission—i.e. un-terminated receiver—in such cases, only dynamic power is consumed while the static power consumption is reduced to zero. In this mode only a 100 mV supply is needed to transmit a 100 mV differential signal, further reducing the dynamic power consumption. 
     Knowing system requirements of a high-speed differential serial link and interconnect power level requirements it is possible to design the system  100  for controlling interconnect power levels by executing commands based on the above description and commonly available design parameters for various components stored on a storage medium. 
     Table 1 shows the reduction of the power consumption as the regulated voltage is reduced—compared to a case without voltage regulation. 
                                                 TABLE 1               VR   impedance   vdde   vddeR   Vout   Static current   Static vddeR power   Static vdde power                  No   100   0.8 v   NA   0.4 v   4 mA   NA   3.2 mW       Yes   100   1.2 v   0.4 v   0.2 v   2 mA   0.8 mW   2.4 mW       Yes   100   1.2 v   0.2 v   0.1 v   1 mA   0.2 mW   1.2 mW       Yes   100   0.8 v   0.4 v   0.2 v   2 mA   0.8 mW   1.6 mW       Yes   100   0.8 v   0.2 v   0.1 v   1 mA   0.2 mW   0.8 mW       NA   NA   0.8 v   0.8/0.4   0.8/0.4   0 mA     0 mW     0 mW                    
It is noted that the power consumption P(vddeR) represents the power consumption in the driver  10 , while the power consumption P(vdde) represents the total power consumption using a linear voltage regulator. The last row of table 1 represents the case of low-speed operation using an un-terminated receiver, with the static power consumption being reduced to zero.
 
     The system  100  allows a single differential line driver  10  and receiver  14  to be utilized in different applications with different interconnect power requirements and signal to noise S/N ratios by enabling, for example, provision of higher interconnect power levels for noisy or high-speed environments, and provision of lower interconnect power levels for quite or lower speed environments. In portable devices such as cell phones RF radiation interferes with device to device communication. The S/N ratio is more prominent in low swing high-speed serial links. The S/N ratio has been measured, modeled, and simulated for numerous applications and is, therefore, well understood. This allows to preset an interconnect power level of a given differential serial link to overcome the S/N ratio or interference. Alternatively, a Bit Error Rate (BER) of the differential link is determined while the interconnect power level is adjusted during high and low noise activities, allowing to preset the interconnect power level to one level or multiple levels depending on the noise level. In other applications, such as PDAs, RF interference is not present. However, there are numerous other sources causing noise or interferences. In any case, using a high-speed differential serial link with an adjustable interconnect power level is highly beneficial by enabling a substantial reduction of power consumption resulting in an increase of battery life and/or employment of smaller batteries, and by allowing use of a same link for different transmission having different interconnect power level requirements. Furthermore, since the system  100  is operable over a wide range of interconnect power levels—or differential voltages—over a wide frequency range it enables use of a same system in numerous applications substantially simplifying the design process. Yet further, designers of new mega chips are enabled to choose a preferred voltage for each digital core and use the voltage regulator  110 —or the switcher—of the system  100  to adapt the same to the chosen core voltage. 
     Referring to  FIG. 5   a , a first embodiment  200  of a method for controlling interconnect power levels according to the invention is shown. In a first step—box  210 , the voltage regulator  110  receives from the control circuitry  160  at the control port  112  a control signal indicative of a predetermined regulated voltage for provision to the driver  10  for a following pre-selected type of data transmission. In dependence upon the received control signal the voltage regulator selects the corresponding reference voltage and provides it to the driver  10 —box  220 . Using the driver  10 , the data signal is then transmitted to the receiver according to the pre-selected type of data transmission—box  230 . The regulated voltage is determined by the control circuitry  160  in dependence upon the required interconnect power level of the pre-selected type of data transmission. For example, the control circuitry  160  selects a preset regulated voltage that corresponds to the type of data transmission. The control signal is provided to the voltage regulator  110  prior provision of a data signal to the driver  10  for transmission to the receiver  14 . Optionally—indicated by dashed lines, the control circuitry  160  provides a control signal indicative of a high-speed or a low-speed data transmission to the receiver  14 —box  240 . Upon receipt of the control signal the switches  140 A and  140 B are switched IN in case of a type of high-speed transmission, or OUT in case of a type of low-speed transmission—box  250 . 
     Referring to  FIG. 5   b , a second embodiment  300  of a method for controlling interconnect power levels according to the invention is shown. Referring to box  310 , the voltage regulator  110  receives from the control circuitry  160  at the control port  112  also a control signal indicative of a predetermined regulated voltage for provision to the driver  10  for a following pre-selected type of data transmission. In dependence upon the received control signal the voltage regulator selects the corresponding reference voltage and provides it to the driver  10 —box  320 . Using the driver  10 , the data signal is then transmitted to the receiver according to the pre-selected type of data transmission—box  330 . During transmission of the data signal the regulated supply voltage is adjusted in dependence upon a feedback signal provided by the receiver—box  340 . The feedback signal is indicative of a quality of the transmitted data signal. For example, if the feedback control signal is indicative of a “noisy” signal the control circuitry  160  determines an increased regulated voltage and provides a corresponding control signal to the voltage regulator  110 . For example, this process is repeated until the feedback control signal is indicative of a satisfying signal quality. This is achieved, for example, by determining an S/N ratio or a BER. Optionally, the control circuitry  160  determines a decreased regulated voltage and provides a corresponding control signal to the voltage regulator  110  until the feedback control signal is indicative of a “noisy” signal. This process is performed, for example, in preset intervals and is advantageous by reducing power consumption during data transmission of long duration. Of course, the regulated voltages are adjusted such that the interconnect power level is high enough to prevent data corruption during transmission. 
     Referring to  FIG. 5   c , a third embodiment  400  of a method for controlling interconnect power levels according to the invention is shown. Referring to box  410 , the voltage regulator  110  receives from the control circuitry  160  at the control port  112  a control signal indicative of a predetermined regulated voltage for provision to the driver  10  for a following pre-selected type of data transmission. In dependence upon the received control signal the voltage regulator selects the corresponding reference voltage and provides it to the driver  10 —box  420 . Using the driver  10 , a suitable test signal is then transmitted to the receiver according to the pre-selected type of data transmission—box  430 . During transmission of the test signal the regulated supply voltage is adjusted in dependence upon a feedback signal provided by the receiver—box  440 . The feedback signal is indicative of a quality of the transmitted test signal. Upon completion of the adjustment, the data signal is then transmitted to the receiver  14  using the driver  10  with the adjusted regulated supply voltage—box  450 . Optionally, data indicative of the adjusted regulated voltage is stored in memory for use as a pre-set regulated voltage for the pre-selected type of data transmission. 
     The implementation of the system  100  for controlling interconnect power levels has been illustrated using a preferred embodiment, but as is evident, is not limited thereto. There are various possibilities for implementing the voltage regulation based on control signals determined using one of the above methods, modifications, or combinations thereof, to accommodate different requirements of numerous applications. 
     Numerous other embodiments of the invention will be apparent to persons skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.