Patent Publication Number: US-2022216335-A1

Title: Semiconductor device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. P2021-001061 filed on Jan. 6, 2021, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device, and more particularly to a technique for relaxing an electric field crowding in an edge-termination area of the semiconductor device. 
     2. Description of the Related Art 
     Conventionally, silicon (Si) semiconductors are used in power semiconductor devices which are mainly applied for power conversion devices and the like. Recently, silicon carbide (SiC), which is a wide-gap semiconductor, is expected as a semiconductor material to replace Si. The SiC power semiconductor devices have advantages, such as high breakdown voltage, low loss, high-speed operation, stable operation in high-temperature environments and the like, in comparison to the conventional Si power semiconductor devices. Such advantages are given by the properties of the SiC material itself in relation to Si, in that the band gap is about three times larger, the dielectric breakdown field strength is about ten times higher, the saturation drift velocity is about two times larger, and the thermal conductivity is about three times larger. 
     As power semiconductor devices, Schottky barrier diodes (SBDs), field effect transistors (FETs), static induction transistors (SITs), insulated gate bipolar transistors (IGBTs), and the like have been commercialized. A trench MOSFET is a semiconductor device having a three-dimensional structure in which a trench is formed in the SiC semiconductor substrate and a sidewall of the trench is used as a channel. Therefore, when comparing elements having the same on-resistance, the trench MOSFET can have an overwhelmingly smaller element area than the planar type vertical MOSFET, and the trench MOSFET is considered to be a particularly promising semiconductor element structure. 
     In a high-voltage semiconductor device, a high electric field is likely to be generated in an edge region of an outer-edge area of the semiconductor device, and an edge-termination structure to mitigate the electric field crowding is important. If the edge-termination structure is not provided, the electric field will be crowded in the edge region of the semiconductor device, and the semiconductor device may be destroyed at a low voltage. Therefore, the edge-termination structure such as a guard ring is provided in the edge region. Further, in the trench MOSFET, in addition to the edge-termination structure in the edge region, a structure for relaxing the electric field crowding at the bottom of the gate trench to prevent the gate insulating film from being destroyed is also required. 
     The guard ring as the edge-termination structure is generally formed by processing technology such as photolithography, ion implantation and the like. For example, in the case of MOSFET, an ion-implantation mask is fabricated by photolithography and the like using a photomask for the guard ring, and the guard ring is formed by implantation of p-type impurity ions on a top surface of an n-type drift layer. Therefore, at least the photomask for the guard ring, and processes of ion-implantation and mesa-groove forming are required, resulting in an increase in manufacturing time and cost. 
     In JP 2016-225455 A, the base-bottom embedded region and the guard ring are simultaneously formed by the ion-implantation through the trench and the embedded growth to fill the trench. In JP 2019-054087 A, the impurity ions are implanted deep inside from the top surface of the drift layer to selectively form the guard ring together with the base-bottom embedded region. In the semiconductor devices described in JP 2016-225455 A and JP 2019-054087 A, the electric field relaxation structure is not provided at the bottom of the gate trench. 
     SUMMARY OF THE INVENTION 
     A first aspect of the present invention inheres in a semiconductor device having an active area in which a main current flows and an outer-edge area surrounding the active area, includes: (a) a semiconductor layer having a first conductivity type made of a wide bandgap semiconductor; (b) a plurality of guard rings each having a second conductivity type provided inside the semiconductor layer in the outer-edge area to surround the active area; and (c) a separation region provided in a concentric ring shape in the outer-edge area to be in contact with both of the adjacent guard rings, wherein the separation region contains both first impurities of the first conductivity type and second impurities of the second conductivity type. 
     A second aspect of the present invention inheres in a method for manufacturing a semiconductor device having an active area in which a main current flows and an outer-edge area surrounding the active area in a first conductivity type semiconductor layer made of a wide bandgap semiconductor, including: (a) forming a second conductivity type semiconductor region on a top surface of the semiconductor layer from the active area to the outer-edge area; and (b) forming separation regions by implanting first conductivity type impurity ions into the semiconductor region to reach the semiconductor layer, the separation regions each having a concentric ring shape and guard rings sandwiching between the respective separation regions in the outer-edge area. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic plan view illustrating an example of a semiconductor device according to a first embodiment of the present invention; 
         FIG. 2  is a schematic cross-sectional view taken along the line II-II in  FIG. 1 ; 
         FIG. 3  is a schematic cross-sectional view illustrating an example of a process in a manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 4  is a schematic cross-sectional view illustrating an example of a process following  FIG. 3  in the manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 5  is a schematic cross-sectional view illustrating an example of a process following  FIG. 4  in the manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 6  is a schematic cross-sectional view illustrating an example of a process following  FIG. 5  in the manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 7  is a schematic cross-sectional view illustrating an example of a process following  FIG. 6  in the manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 8  is a schematic cross-sectional view illustrating an example of a process following  FIG. 7  in the manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 9  is a schematic cross-sectional view illustrating an example of a process following  FIG. 8  in the manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 10  is a schematic cross-sectional view illustrating an example of a process following  FIG. 9  in the manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 11  is a schematic cross-sectional view illustrating an example of a process following  FIG. 10  in the manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 12  is a schematic cross-sectional view illustrating an example of a process following  FIG. 11  in the manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 13  is a schematic cross-sectional view illustrating an example of a process following  FIG. 12  in the manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 14  is a schematic cross-sectional view illustrating an example of a process following  FIG. 13  in the manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 15  is a schematic cross-sectional view illustrating an example of a process following  FIG. 14  in the manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 16  is a schematic cross-sectional view illustrating an example of a process following  FIG. 15  in the manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 17  is a schematic cross-sectional view illustrating an example of a process following  FIG. 16  in the manufacturing method of the semiconductor device according to the first embodiment of the present invention; 
         FIG. 18  is a schematic cross-sectional view illustrating an example of a semiconductor device according to a first modification of the first embodiment of the present invention; 
         FIG. 19  is a schematic cross-sectional view illustrating an example of a process in a manufacturing method of the semiconductor device according to the first modification of the first embodiment of the present invention; 
         FIG. 20  is a schematic cross-sectional view illustrating an example of a process following  FIG. 19  in the manufacturing method of the semiconductor device according to the first modification of the first embodiment of the present invention; 
         FIG. 21  is a schematic cross-sectional view illustrating an example of a process following  FIG. 20  in the manufacturing method of the semiconductor device according to the first modification of the first embodiment of the present invention; 
         FIG. 22  is a schematic cross-sectional view illustrating an example of a process following  FIG. 21  in the manufacturing method of the semiconductor device according to the first modification of the first embodiment of the present invention; 
         FIG. 23  is a schematic cross-sectional view illustrating an example of a process following  FIG. 22  in the manufacturing method of the semiconductor device according to the first modification of the first embodiment of the present invention; 
         FIG. 24  is a schematic cross-sectional view illustrating an example of a semiconductor device according to a second modification of the first embodiment of the present invention; 
         FIG. 25  is a schematic cross-sectional view illustrating an example of a process in a manufacturing method of the semiconductor device according to the second modification of the first embodiment of the present invention; 
         FIG. 26  is a schematic cross-sectional view illustrating an example of a process following  FIG. 25  in the manufacturing method of the semiconductor device according to the second modification of the first embodiment of the present invention; 
         FIG. 27  is a schematic cross-sectional view illustrating an example of a process following  FIG. 26  in the manufacturing method of the semiconductor device according to the second modification of the first embodiment of the present invention; 
         FIG. 28  is a schematic cross-sectional view illustrating an example of a process following  FIG. 27  in the manufacturing method of the semiconductor device according to the second modification of the first embodiment of the present invention; 
         FIG. 29  is a schematic cross-sectional view illustrating an example of a process following  FIG. 28  in the manufacturing method of the semiconductor device according to the second modification of the first embodiment of the present invention; 
         FIG. 30  is a schematic cross-sectional view illustrating an example of a semiconductor device according to a second embodiment of the present invention; 
         FIG. 31  is a schematic cross-sectional view illustrating an example of a process in a manufacturing method of the semiconductor device according to the second embodiment of the present invention; 
         FIG. 32  is a schematic cross-sectional view illustrating an example of a process following  FIG. 31  in the manufacturing method of the semiconductor device according to the second embodiment of the present invention; 
         FIG. 33  is a schematic cross-sectional view illustrating an example of a process following  FIG. 32  in the manufacturing method of the semiconductor device according to the second embodiment of the present invention; 
         FIG. 34  is a schematic cross-sectional view illustrating an example of a process following  FIG. 33  in the manufacturing method of the semiconductor device according to the second embodiment of the present invention; 
         FIG. 35  is a schematic cross-sectional view illustrating an example of a process following  FIG. 34  in the manufacturing method of the semiconductor device according to the second embodiment of the present invention; 
         FIG. 36  is a schematic cross-sectional view illustrating an example of a process following  FIG. 35  in the manufacturing method of the semiconductor device according to the second embodiment of the present invention; 
         FIG. 37  is a schematic cross-sectional view illustrating an example of a process following  FIG. 36  in the manufacturing method of the semiconductor device according to the second embodiment of the present invention; 
         FIG. 38  is a schematic cross-sectional view illustrating another example of the edge-termination structure of the semiconductor device according to the second embodiment of the present invention; 
         FIG. 39  is a schematic cross-sectional view illustrating another example of the edge-termination structure of the semiconductor device according to the second embodiment of the present invention; 
         FIG. 40  is a schematic cross-sectional view illustrating another example of the edge-termination structure of the semiconductor device according to the second embodiment of the present invention; 
         FIG. 41  is a schematic cross-sectional view illustrating another example of the edge-termination structure of the semiconductor device according to the second embodiment of the present invention; 
         FIG. 42  is a diagram illustrating an example of impurity concentration distribution by ion-implantation of the edge-termination structure of the semiconductor device according to the second embodiment of the present invention. 
         FIG. 43  is a schematic cross-sectional view illustrating an example of the edge-termination structure having the impurity concentration distribution illustrated in  FIG. 42 ; 
         FIG. 44  is a schematic plan view illustrating an example of a semiconductor substrate used for manufacturing a semiconductor device according to a third embodiment of the present invention; 
         FIG. 45  is a schematic cross-sectional view taken along the line XLV-XLV in  FIG. 44 ; 
         FIG. 46  is a schematic cross-sectional view illustrating an example of the edge-termination structure of the semiconductor device according to the third embodiment of the present invention. 
         FIG. 47  is a schematic cross-sectional view illustrating another example of the edge-termination structure of the semiconductor device according to the third embodiment of the present invention; 
         FIG. 48  is a schematic cross-sectional view illustrating an example of an edge-termination structure of a semiconductor device according to other embodiment of the present invention; 
         FIG. 49  is a schematic cross-sectional view illustrating another example of the edge-termination structure of the semiconductor device according to the other embodiment of the present invention; and 
         FIG. 50  is a schematic cross-sectional view illustrating another example of the edge-termination structure of the semiconductor device according to the other embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, first to third embodiments of the present invention will be described with reference to the drawings. In the descriptions of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and duplicate explanation is omitted. However, the drawings are schematic, the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, etc. may be different from the actual one. In addition, parts having different dimensional relations and ratios may also be included between drawings. In addition, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the invention does not specify the material, shape, structure, or arrangement of the elements described below. 
     In the present specification, the source region of the MOS transistor is the “one main region (first main region)” that can be selected as the emitter region of the insulated gate bipolar transistor (IGBT). Further, in a thyristor such as a MOS-controlled electrostatic induction thyristor (SI thyristor), one main region can be selected as a cathode region. The drain region of the MOS transistor is the “other main region (second main region)” of the semiconductor device, which can be selected as the collector region in the IGBT and the anode region in the thyristor. As used herein, the term “main region” means either the first main region or the second main region, which is appropriate from the common general technical knowledge of those skilled in the art. 
     Further, in the following descriptions, the terms relating to directions, such as “top and bottom” are merely defined for illustration purposes, and thus, such definitions do not limit the technical spirit of the present invention. Therefore, for example, when the paper plane is rotated by 90 degrees, the “top and bottom” are read in exchange to the “left and right”. When the paper plane is rotated by 180 degrees, the “top” is changed to the “bottom”, and the “bottom” is changed to the “top”. Further, in the following description, the case where a first conductivity type is n-type and a second conductivity type is p-type will be exemplarily described. However, it is also possible to select the conductivity type in an inverse relationship so that the first conductivity type is p-type and the second conductivity type is n-type. Further, the superscript “+” or “−” added to the mark “n” or “p” denotes that a semiconductor region has relatively high or low impurity concentration than a region without the superscript “+” or “−” added. It should be noted that semiconductor regions denoted by the same mark, such as “n”, do not necessarily have exactly the same impurity concentration. Further, in the specification, “−” in the Miller index notation denotes a bar on top of the following Miller index, and a negative index is denoted with adding “−” before the index. 
     First Embodiment 
     &lt;Structure of Semiconductor Device&gt; 
     As illustrated in  FIG. 1 , an SiC semiconductor device (semiconductor chip)  100  according to a first embodiment of the present invention includes an active area  101  and an outer-edge area  102 . For example, the active area  101  has a rectangular planar shape, and the outer-edge area  102  is arranged around the active area  101  so as to surround the active area  101 .  FIG. 2  is a cross-sectional view taken from the direction taken along the line II-II in  FIG. 1 . As illustrated in  FIG. 2 , the active area  101  includes an active element and the outer-edge area  102  includes an edge-termination structure.  FIG. 2  illustrates a case including a MOSFET having a trench gate structure provided on a first conductivity type (n − -type) drift layer  2  as the active element and a plurality of electric-field relaxation regions (guard rings)  6   a  as the edge-termination structure. 
     As illustrated in  FIG. 2 , a second conductivity type (p-type) base region  6  is arranged on a top surface of the drift layer  2 . The drift layer  2  and the base region  6  are provided by epitaxial growth layers (hereinafter, referred to as “epitaxial layers”) made of SIC. A p + -type base contact region  8  having a higher impurity concentration than the base region  6  is selectively provided on the base region  6 . An n + -type first main region (source region)  7  having a higher impurity concentration than the drift layer  2  is selectively provided on the base region  6  so as to be in contact with the base contact region  8 . 
     For example, the impurity concentration of the drift layer  2  is 1×10 14  cm −3  or more and 1×10 16  cm −3  or less, and the impurity concentration of the base region  6  is 1×10 17  cm −3  or more and 1×10 18  cm −3  or less. The impurity concentration of the base contact region  8  is 5×10 18  cm −3  or more and 5×10 20  cm −3  or less, and the impurity concentration of the source region  7  is 5×10 18  cm −3  or more and 5×10 20  cm −3  or less. 
     A trench (first groove)  9  having a width of 1 μm or less is provided so as to penetrate the base region  6  from the top surfaces of the source region  7  and the base region  6 . That is, the source regions  7  and the base region  6  are in contact with an outer sidewall of the trench  9 . A gate insulating film  11  is provided on a bottom surface and a sidewall inside the trench  9 . A gate electrode  12  is embedded in the trench  9  via the gate insulating film  11  to form an insulated-gate electrode-structure ( 11 ,  12 ). For the gate insulating film  11 , in addition to a silicon oxide (SiO 2 ) film, a dielectric film, such as a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si 3 N 4 ) film, an aluminum oxide (Al 2 O 3 ) film, a magnesium oxide (MgO) film, an yttrium oxide (Y 2 O 3 ) film, a hafnium oxide (HfO 2 ) film, a zirconium oxide (ZrO 2 ) film, a tantalum oxide (Ta 2 O 5 ) film, and a bismuth oxide (Bi 2 O 3 ) film, may be adopted. Moreover, a single-layer film of any one of the above-mentioned dielectric films or a composite film in which the plural dielectric films are laminated, may be used. For a material of the gate electrode  12 , for example, a polysilicon layer doped with impurities, such as phosphorus (P), boron (B) and the like, at a high concentration, that is a doped polysilicon layer, may be used. 
     An n + -type current spreading layer (CSL)  3  having a higher impurity concentration than the drift layer  2  is selectively provided on the drift layer  2 . The bottom of the trench  9  reaches the current spreading layer  3 . The current spreading layer  3  does not necessarily have to be provided. When the current spreading layer  3  is not provided, the bottom of the trench  9  reaches the drift layer  2 . A p + -type gate-bottom protection region  4   b  is provided in the current spreading layer  3  so as to be in contact with the bottom of the trench  9 . In the current spreading layer  3 , a first base-bottom embedded region  4   a  is provided below the base contact region  8  at the same level of depth as the gate-bottom protection region  4   b  and away from the gate-bottom protection region  4   b . A second base-bottom embedded region  5  is provided in an upper portion of the current spreading layer  3  so as to be in contact with a top surface of the first base-bottom embedded region  4   a  and a bottom surface of the base region  6 . The second base-bottom embedded region  5  is also provided below the base contact region  8 . 
     An interlayer insulating film  13  is arranged on the top surface of the gate electrode  12 . For the interlayer insulating film  13 , a silicon oxide film to which boron (B) and phosphorus (P) are doped, that is BPSG, may be used. However, for the interlayer insulating film  13 , a silicon oxide film to which phosphorus (P) is doped, that is PSG, a non-doped SiO 2  film called “NSG”, in which phosphorus (P) or boron (B) is not added, a silicon oxide film to which boron (B) is doped, that is BSG, a Si 3 N 4  film, or the like, may be used. Alternatively, a composite film in which the above-mentioned films are laminated, may be adopted. 
     A source contact layer  14  is provided so as to physically contact the source region  7  and the base contact region  8 , which are exposed between the interlayer insulating films  13 . A first main electrode (source electrode)  15  is provided so as to cover the interlayer insulating film  13  and the source contact layer  14 . A barrier metal layer (not shown) may be provided between the interlayer insulating film  13  and the first main electrode (source electrode)  15 , and between the source contact layer  14  and the first main electrode (source electrode)  15 . The first main electrode (source electrode)  15  is electrically connected to the source region  7  and the base contact region  8  via the barrier metal layer and the source contact layer  14 . For example, a nickel silicide (NiSi x ) film for the source contact layer  14 , a titanium nitride (TiN) film or a titanium (Ti) film for the barrier metal layer, and an aluminum (Al) film or an aluminum-silicon (Al—Si) film for the source electrode  15  may be adopted. The source electrode  15  is arranged to be separated from a gate surface electrode (not shown). Although not shown, a gate electrode pad (not shown) arranged on a top surface of a field insulating film  10  is electrically connected to the gate electrode  12 . 
     An n + -type second main region (drain region)  1  is arranged on a bottom surface of the drift layer  2 . A second main electrode (drain electrode)  16  is arranged on a bottom surface of the drain region  1 . For the drain electrode  16 , for example, a single-layer film made of gold (Au) or a metal film in which Ti, nickel (Ni), and Au are laminated in this order may be used, and further a metal film, such as molybdenum (Mo), tungsten (W) or the like, may be laminated as the lowermost layer of the drain electrode  16 . Further, a drain contact layer may be provided between the drain region  1  and the drain electrode  16 . The drain contact layer may be a nickel silicide (NiSi x ) film, for example. 
     The impurity concentration of the current spreading layer  3  is 5×10 16  cm −3  or more and 3×10 18  cm −3  or less, and the impurity concentration of the first base-bottom embedded region  4   a  and the gate-bottom protection region  4   b  is 1×10 18  cm −3  or more and 1×10 19  cm −3  or less. The impurity concentration of the second base-bottom embedded region  5  is 1×10 18  cm −3  or more and 1×10 19  cm −3  or less. The impurity concentration in the drain region  1  is 1×10 18  cm −3  or more and 1×10 19  cm −3  or less. 
     In the semiconductor device according to the first embodiment, a structure having the drain region  1  implemented by the semiconductor substrate made of SiC or the SiC substrate and the drift layer  2  implemented by the epitaxial layer made of SiC or the SiC layer, is exemplified. The semiconductor regions implementing the semiconductor device according to the first embodiment which include the drain region  1  and the drift layer  2  is not limited to SiC. In addition to SiC, a hexagonal semiconductor material having the forbidden bandgap wider than 1.1 eV of Si, such as gallium nitride (GaN), lonsdaleite (hexagonal diamond), aluminum nitride (AlN) and the like, may be used. As for values of the forbidden bandgaps at room temperature, 3.26 eV for 4H-SiC, 3.02 eV for 6H-SiC, 3.4 eV for GaN, 5.5 eV for diamond and 6.2 eV for AlN, are reported respectively. In the present invention, a semiconductor having a forbidden bandgap larger than that of silicon may be defined as a wide bandgap semiconductor. 
     During operation of the semiconductor device according to the first embodiment, a positive voltage is applied to the drain electrode  16  with the source electrode  15  as the ground potential and a positive voltage equal to or higher than the threshold value is applied to the gate electrode  12 . Thus, an inversion layer (a channel) is induced in the base region  6  at the sidewall of the trench  9  to turn on the semiconductor device. The inversion layer is formed on the side surface of the base region  6  located on the sidewall of the trench  9  as an interface between the gate dielectric film  11  and the base region  6  where the base region  6  faces the gate electrode  12 . In the on-state, a current flows from the drain electrode  16  to the source electrode  15  via the drain region  1 , the drift layer  2 , the current spreading layer  3 , the inversion layer in the base region  6 , and the source region  7 . On the other hand, when the voltage applied to the gate electrode  12  is less than the threshold value, the inversion layer is not induced in the base region  6 . Thus, the semiconductor device is turned off and no current flows from the drain electrode  16  to the source electrode  15 . 
     As illustrated in  FIG. 2 , in the outer-edge area  102 , a plurality of n-type separation regions  17  which penetrate through the p-type base region  6  extending from the active area  101  into to the n-type drift layer  2 , are provided. The separation regions  17  have concentric ring shapes so as to surround the active area  101 . Portions of the p-type base region  6  sandwiched between the adjacent separation regions  17  implement the plural p-type electric-field relaxation regions (guard rings)  6   a . Therefore, the guard rings  6   a  and the separation regions  17  are alternately provided in contact with each other. The impurity concentration of the second conductivity type or p-type impurities contained in each of the p-type base region  6 , the guard ring  6   a , and separation region  17  is the same. The p-type electric-field relaxation regions (guard rings)  6   a  are provided in the concentric ring shape separated from each other by the separation regions  17 . The p-type impurity concentration of each of the guard rings  6   a  is 1×10 17  cm −3  or more and 1×10 18  cm −3  or less. Each of the separation regions  17  is a co-doped region formed by doping the n-type impurities to the base region  6  containing the p-type impurities. Thus, in the co-doped region, the p-type impurity concentration is 1×10 17  cm −3  or more and 1×10 18  cm −3  or less and the n-type impurity concentration is 1×10 17  cm −3  or more and 3×10 18  cm −3  or less. Although the n-type separation region  17  is illustrated in  FIG. 2 , the separation region  17  may be a p-type. When there is a difference in the p-type impurity concentrations between the guard ring  6   a  and the separation region  17 , it is possible to mitigate the electric field crowding. The interlayer insulating film  13  extending from the active area  101  is provided on the top surfaces of the guard ring  6   a  and the separation regions  17  via the field insulating film  10 . 
     In the outer end of the outer-edge area  102 , an n + -type channel stopper may be provided concentrically on an upper portion of an outermost separation region  17 . In addition, a p + -type channel stopper may be provided instead of the n + -type channel stopper. 
     In the semiconductor device according to the first embodiment, n-type impurities are selectively doped to the p-type base region  6  extending from the active area  101  to the outer-edge area  102  to form the separation regions  17  each having the concentric ring-shape. The portions of the base region  6  which is the p-type epitaxial layer, left between the adjacent separation regions  17  implement the p-type guard rings  6   a  each having the concentric ring shape. The semiconductor device according to the first embodiment does not require a mesa-groove-forming process, and the guard rings  6   a  can be provided by forming the separation regions  17  by implantation of the n-type impurity ions. As described above, the semiconductor device according to the first embodiment has a simple configuration, and the manufacturing process can be simplified. Since the implantation of p-type impurity ions requires high-temperature ion-implantation in order to improve the implantation efficiency, a photoresist film cannot be used as an ion-implantation mask, and an oxide film and the like is required as a mask material. On the other hand, since the implantation of n-type impurity ions is possible even at room temperature, a photoresist film can be used as an ion-implantation mask. As described above, it is not necessary to deposit an oxide film and the like, and the guard-ring-forming process can be shortened. Further, in the photolithography technique, it is possible to miniaturize a photoresist pattern. Further, since the active area  101  and the outer-edge area  102  may be flat, the photoresist pattern can be further miniaturized, and the patterns of the guard rings  6   a  formed on the outer-edge area  102  can be reduced. Thus, it is possible to increase the current capacity by to increasing in a dimension of the active area and to reduce the size of the semiconductor chip. As described above, the man-hours of the guard-ring-forming process and the mesa-groove-forming process can be reduced, and it is possible to shorten the manufacturing time of the semiconductor device and to reduce the manufacturing cost. 
     &lt;Manufacturing Method of Semiconductor Device&gt; 
     Next, a manufacturing method of the SiC semiconductor device according to the first embodiment will be given by taking a trench gate MOSFET as an example, with reference to the cross-sectional views of  FIGS. 3 to 14 . Note that the manufacturing method of the trench gate MOSFET described below is merely an example and may be achieved by various other manufacturing methods including a modification as long as the gist described in the claims is included. 
     First, an n + -type SiC semiconductor substrate (substrate)  1   p  in which n-type impurities such as nitrogen (N) are doped, is prepared. As illustrated in  FIG. 3 , the n − -type drift layer  2   p  is epitaxially grown on a top surface of the substrate  1   p . Then, a photoresist film is applied to a top surface of the drift layer  2   p , and a mask pattern is delineated to the photoresist film by photolithography technique and the like. The delineated photoresist film is used as an ion-implantation mask to selectively implant n-type impurity ions, such as nitrogen (N) and the like, from the upper side of the drift layer  2   p  in the active area  101  of the drift layer  2 . Thus, the n-ion implanted layer  3   p  is formed on an upper portion of the drift layer  2   p  of the active area  101 . 
     An oxide film made of SiO 2  is deposited on the top surfaces of the n-ion implanted layer  3   p  and the drift layer  2   p  by CVD technique and the like. A photoresist film is applied to the top surface of the oxide film, and a mask pattern is delineated to the oxide film by photolithography technique, dry etching technique and the like. Using the delineated oxide film  40  as an ion-implantation mask, p-type impurity ions, such as aluminum (Al) and the like, are implanted into the n-ion implanted layer  3   p  by multiple-energy ion implantation. As a result, as illustrated in  FIG. 4 , the first base-bottom embedded region  4   a  and the gate-bottom protection region  4   b  are selectively formed on an upper portion of the n-ion implanted layer  3   p.    
     After removing the oxide film  40 , an n-type epitaxial layer  55  is grown on top surfaces of the n-ion implanted layer  3   p , the first base-bottom embedded region  4   a , the gate-bottom protection region  4   b  and the drift layer  2   p . A photoresist film is applied to a top surface of the epitaxial layer  55 , and a mask pattern is delineated to the photoresist film by photolithography technique and the like. Using the delineated photoresist film as an ion-implantation mask, n-type impurity ions, such as nitrogen (N) and the like, are selectively implanted into the upper portion of the epitaxial layer  55  from the upper side of the epitaxial layer  55  by multiple-energy ion implantation. As a result, as illustrated in  FIG. 5 , the n-ion implanted layer  5   p  is formed on the n-ion implanted layer  3   p , the first base-bottom embedded region  4   a  and the gate-bottom protection region  4   b . As will be described later, the n-ion implanted layer  3   p  and the n-ion implanted layer  5   p  implement the current spreading layer  3 , and the impurity concentration of the n-ion implantation layer  5   p  is preferably higher than that of the n-ion implantation layer  3   p.    
     Thereafter, an oxide film made of SiO 2  is deposited on the top surfaces of the n-ion implanted layer  5   p  and the epitaxial layer  55  by CVD technique and the like. A photoresist film is applied to a top surface of the oxide film, and a mask pattern is delineated to the photoresist film by photolithography technique, dry etching technique and the like. Using the delineated oxide film  60  as an ion-implantation mask, p-type impurity ions, such as aluminum (Al) and the like, are selectively implanted into the n-ion implanted layer  5   p  by multiple-energy ion implantation. As a result, as illustrated in  FIG. 6 , the second base-bottom embedded region  5  is selectively formed on the first base-bottom embedded region  4   a . Further, the drift layer  2   p  and the epitaxial layer  55  implement the drift layer  2 . 
     After removing the oxide film  60 , a p-type base region  6   p  is epitaxially grown on the top surfaces of the second base-bottom embedded region  5 , the n-ion implanted layer  5   p  and the drift layer  2 . An oxide film made of SiO 2  is deposited on a top surface of the base region  6   p  by CVD technique and the like. A photoresist film is applied to a top surface of the oxide film, and a mask pattern is delineated to the oxide film by photolithography technique, dry etching technique and the like. Using the delineated oxide film as an ion-implantation mask, p-type impurity ions, such as aluminum (Al) and the like, are selectively implanted into the base region  6   p  from the upper side of the base region  6   p  by multiple-energy ion implantation. As a result, as illustrated in  FIG. 7 , the base contact region  8  is formed on the top surfaces of the base region  6   p  above the second base-bottom embedded region  5  and the n-ion implanted layer  5   p.    
     After removing the oxide film used as the ion-implantation mask, an oxide film made of SiO 2  is deposited on the top surfaces of the base contact region  8  and the base region  6   p  by CVD technique or the like. A photoresist film is applied to a top surface of the oxide film, and a mask pattern is delineated to the oxide film by photolithography technique, dry etching technique and the like. Using the delineated oxide film  70  as an ion-implantation mask, n-type impurity ions, such as phosphorus (P) and the like, are selectively implanted into the base region  6   p  from the upper side of the base region  6   p  by multiple-energy ion implantation. As a result, as illustrated in  FIG. 8 , the source region  7  is formed on the top surface of the base region  6   p  above the n ion implanted layer  5   p.    
     After removing the oxide film  70  used as the ion-implantation mask, a photoresist film is applied to the top surfaces of the base contact region  8 , the source region  7  and the base region  6   p , and a mask pattern is delineated to the photoresist film by photolithography technique and the like. Using the delineated photoresist film  80  as an ion-implantation mask, n-type impurity ions, such as nitrogen (N) and the like, are selectively implanted in the base region  6   p  from the upper side of the base region  6   p  by multiple-energy ion implantation so as to reach the drift layer  2  through the base region  6   p . As a result, the plural n-type separation regions  17  are provided in the base region  6   p  of the outer-edge area  102 . As illustrated in  FIG. 9 , portions of the base region  6   p  sandwiched between the separation regions  17  implement the plural p-type guard rings  6   a , which are separated from each other and formed in the concentric ring shapes. That is, the guard rings  6   a  and the separation regions  17  are alternately provided in contact with each other. Further, the base region  6   p  in the active area  101  implements the base region  6 . Therefore, the impurity concentration of the second conductivity type (p-type) impurities contained in each of the p-type base region  6 , the p-type guard ring  6   a , and the n-type separation region  17  is the same. 
     After removing the photoresist film  80  used as the ion-implantation mask, an oxide film made of SiO 2  is deposited on the top surfaces of the base contact region  8 , the source region  7  and the base region  6  by CVD technique and the like. A photoresist film is applied to a top surface of the oxide film, and a mask pattern is delineated to the oxide film by photolithography technique, dry etching technique and the like. Using the delineated oxide film  90  as an etching mask, the trench  9  is selectively formed by dry etching technique such as ICP-RIE and the like. The trench  9  penetrates the source region  7 , the base region  6  and the n-ion implanted layer  5   p  to reach the gate-bottom protection region  4   b . After removing the oxide film  90 , a carbon (C) film is deposited on an exposed surface of the trench  9  by carbon sputtering technique and the like. 
     Thereafter, the implanted n-type and p-type impurity ions are simultaneously activated by activation annealing. As a result, as illustrated in  FIG. 10 , the n + -type current spreading layer  3  implemented by the n-ion implanted layer  3   p  and the n-ion implanted layer  5   p  is formed in the upper portion of the drift layer  2 . The p + -type first base-bottom embedded region  4   a , the p + -type second base-bottom embedded region  5  sandwiched between the first base-bottom embedded region  4   a  and the base region  6 , and the p + -type gate-bottom protection region  4   b  on the bottom of the trench  9  are formed in the current spreading layer  3 . Further, the n + -type source region  7  is formed on the top surface of the base region  6  so as to be in contact with the trench  9 , and the p + -type base contact region  8  is formed on the top surface of the base region  6  so as to be in contact with the source regions  7 . Furthermore, the p-type guard rings  6   a  having the concentric ring shapes are formed on the outer-edge area  102  so as to be separated from each other by the n-type separation regions  17 . 
     A field oxide film is deposited on the exposed surface after removing the carbon film by CVD technique and the like. A photoresist film is applied to a top surface of the field oxide film, and a mask pattern is delineated to the photoresist film by photolithography technique, dry etching technique and the like. The delineated photoresist film is used as an etching mask to selectively remove the field oxide film. As a result, as illustrated in  FIG. 11 , the field insulating film  10  is formed on top surfaces of the guard rings  6   a  and the separation regions  17 . 
     As illustrated in  FIG. 12 , a gate insulating film  11   p  such as a SiO 2  film is formed on the bottom surface and sidewall of the trench  9 , and the top surfaces of the source region  7  and the base contact region  8  by thermal oxidation method or chemical vapor deposition (CVD) technique. Then, a polysilicon layer (doped polysilicon layer)  12   p  in which impurities, such as phosphorus (P) and boron (B), are doped at a high concentration is deposited so as to fill the trench  9  by CVD technique and the like. As illustrated in  FIG. 12 , the polysilicon layer  12   p  extends so as to cover the top surface of the field insulating film  10  in the outer-edge area  102 . 
     Thereafter, a part of the polysilicon layer  12   p  and a part of the gate insulating film  11   p  are selectively removed by photolithography technique, dry etching technique and the like. As illustrated in  FIG. 13 , the insulated-gate electrode structure ( 11 ,  12 ) is formed by patterning the gate insulating film  11  and the gate electrode  12  of the polysilicon layer. Then, an insulating film is deposited on a top surface of the insulated-gate electrode structure ( 11 ,  12 ) implemented by the gate electrode  12  and the gate insulating film  11  by CVD technique and the like. For the insulating film, boro-phospho silicate glass (BPSG), NSG and the like may be used. Then, a part of the deposited insulating film is selectively removed by photolithography technique, dry etching technique and the like. As a result, as illustrated in  FIG. 13 , the interlayer insulating film  13  in which a source electrode contact-hole is opened is formed. Although not illustrated, a gate contact-hole is also opened in the interlayer insulating film  13  so as to expose a part of the gate surface electrode connected to the gate electrode  12  at a position different from the source electrode contact-hole. 
     A metal layer, such as a Ni film and the like, is deposited by sputtering method, evaporation method and the like, and a pattern of the metal layer is delineated by photolithography technique, RIE technique and the like. Thereafter, a NiSi x  film is formed by rapid thermal annealing (RTA) technique, for example, at about 1000° C. Then, the unreacted Ni film is removed to form the source contact layer  14  on the top surfaces of the source region  7  and the base contact region  8  illustrated in  FIG. 14 . Next, a barrier metal layer (not illustrated), such as a Ti film, a TiN film and the like, and a metal layer, such as an Al film and the like, are deposited by sputtering technique and the like, and the pattern of the barrier metal layer and the metal layer are delineated by photolithography technique, RIE technique and the like. As a result, a laminated structure of the barrier metal layer and the source electrode  15  is formed so as to cover the source contact layer  14  and the interlayer insulating film  13 . Further, the patterns of the source electrode  15  and the gate surface electrode are separated, and the gate surface electrode is electrically connected to the gate electrode  12   a  via an interconnection layer (not illustrated) provided on the field insulating film  10 . 
     Further, the bottom surface of the substrate  1   p  is polished by chemical mechanical polishing (CMP) technique and the like to adjust the thickness to form the drain region  1 . Thereafter, the drain electrode  16  made of Ti, Ni, Au and the like is deposited on the entire bottom surface of the drain region  1  by sputtering method, evaporation method and the like. Thus, the trench gate semiconductor device illustrated in  FIG. 2  is completed. 
     In the manufacturing method of the semiconductor device according to the first embodiment, the separation regions  17  are formed by implanting the n-type impurity ions into the base region  6  extending to the outer-edge area  102 , and thus, the p-type guard rings  6   a  are formed to be separated from each other and in the concentric rings. In the conventional trench gate semiconductor device, the base region is removed by forming the mesa groove in the outer-edge area  102 , and the p-type impurity ions are implanted into the exposed drift layer to form the guard rings. In the semiconductor device according to the first embodiment, the mesa-groove-forming process is not necessary, and the manufacturing process steps may be shortened. Further, the guard rings  6   a  can be provided by forming the separation regions  17  by the implantation of the n-type impurity ions. Since the implantation of the p-type impurity ions requires high-temperature ion-implantation in order to improve the implantation efficiency, a photoresist film cannot be used as an ion-implantation mask, and an oxide film and the like is required as a mask material. On the other hand, since the implantation of the n-type impurity ions can be executed even at room temperature, the photoresist film can be used as the ion-implantation mask. As described above, it is not necessary to deposit any oxide film and the like in the guard-ring-forming process, and the guard-ring-forming process can be shortened. In addition, in the photolithography technique, a fine photoresist pattern can be formed. And further, since the top surface from the active area  101  to the outer-edge area  102  may be flat, the photoresist pattern can be made further finer, and the patterns of the guard rings  6   a  formed on the outer-edge area  102  can be miniaturized. Thus, it is possible to increase the current capacity of the semiconductor chip and to reduce the size of the semiconductor chip. As described above, the man-hours of the guard-ring-forming process and the mesa-groove-forming process can be cut down, and it is possible to shorten the manufacturing time of the semiconductor device and to reduce the manufacturing cost. 
     In the above description, in order to form the guard rings  6   a , the separation regions  17  are formed by ion-implantation so as to penetrate the base region  6  to reach the drift layer  2 . When the capability of the ion-implanter is insufficient to allow ion-implantation through the base region  6 , the base region  6  may be formed in multiple times, for example, twice, as follows. 
     For example, as illustrated in  FIG. 6 , the second base-bottom embedded region  5  is selectively formed on the first base-bottom embedded region  4   a . Then, as illustrated in  FIG. 15 , a p-type first base region  6   pa  is epitaxially grown on the top surfaces of the second base-bottom embedded region  5 , the n-ion implanted layer  5   p  and the drift layer  2 . A photoresist film is applied to a top surface of the first base region  6   pa , and a mask pattern is delineated to the photoresist film by photolithography technique and the like. Using the delineated photoresist film as the ion-implantation mask, n-type impurity ions, such as nitrogen (N) and the like, are selectively implanted in the first base region  6   pa  from the upper side of the first base region  6   pa  by multiple-energy ion implantation in the first base region  6   pa  to reach the drift layer  2 . As a result, as illustrated in  FIG. 15 , a plurality of n-type first separation regions  17   a  are formed in the first base region  6   pa  in the outer-edge area  102 , and a plurality of p-type first guard rings  6   aa  are formed to be separated from each other and in the concentric ring shapes. 
     After removing the photoresist film used as the ion-implantation mask, a p-type second base region  6   pb  is epitaxially grown on top surfaces of the first base region  6   pa , the first guard rings  6   aa  and the first separation regions  17   a . A photoresist film is applied to a top surface of the first base region  6   pb , and a mask pattern is delineated to the photoresist film by photolithography technique and the like. Using the delineated photoresist film  72  as an ion-implantation mask, n-type impurity ions such as nitrogen (N) are selectively implanted in the second base region  6   pb  from the upper side of the second base region  6   pb  by multi-energy ion implantation to reach the first separation regions  17   a . As a result, as illustrated in  FIG. 16 , a plurality of n-type second separation regions  17   b  are formed to be in contact with the first separation regions  17   a  in the second base region  6   pb  of the outer-edge area  102 . Further, a plurality of p-type second guard rings  6   ab  are formed to be separated from each other and in the concentric ring shapes, to be in contact with the first guard rings  6   aa.    
     After removing the photoresist film  72 , the base region  6   p  implemented by the first and second base regions  6   pa ,  6   pb , the guard rings  6   a  implemented by the first and second guard rings  6   aa ,  6   ab , and separation regions  17  implemented by the first and second separation regions  17   a ,  17   b  are formed, respectively. An oxide film made of SiO 2  is deposited on the top surfaces of the base region  6   p , the guard rings  6   a  and the separation regions  17  by CVD technique and the like. A photoresist film is applied to a top surface of the oxide film, and a mask pattern is delineated to the oxide film by photolithography technique, dry etching technique and the like. Using the delineated oxide film as an ion-implantation mask, p-type impurity ions such as aluminum (Al) are selectively implanted into the base region  6   p  from the upper side of the base region  6   p . As a result, the base contact region  8  is formed on the top surface of the base region  6   p  above the second base-bottom embedded region  5  and the n-ion implanted layer  5   p.    
     After removing the oxide film used as the ion-implantation mask, an oxide film made of SiO 2  is deposited on the top surfaces of the base contact region  8  and the base region  6   p  by CVD technique and the like. A photoresist film is applied to a top surface of the oxide film, and a mask pattern is delineated to the oxide film by photolithography technique, dry etching technique and the like. Using the delineated oxide film as an ion-implantation mask, n-type impurity ions such as phosphorus (P) are selectively implanted into the base region  6   p  from the upper side of the base region  6   p . As a result, as illustrated in  FIG. 17 , the source region  7  is formed on the top surface of the base region  6   p  above the n-ion implanted layer  5   p . Subsequent processes are the same as the processes illustrated in  FIGS. 10 to 14 , so duplicate description will be omitted. When forming a channel stopper at the outer end portion of the outer-edge area  102 , the channel stopper may be formed by ion-implantation into the outer end portion during the processes of forming the base contact region  8  or the source region  7 . 
     (First Modification) 
     As illustrated in  FIG. 18 , a semiconductor device according to a first modification of the first embodiment differs from the first embodiment in that a plurality of n + -type separation regions  7   b  which penetrate a p + -type base contact region  8   a  extending from the active area  101  to the outer-edge area  102  to reach an n-type semiconductor layer  66 , are provided. The semiconductor layer  66  is provided on the top surface of the drift layer  2  in the outer-edge area  102  with a depth level of a base region  6   b , and is in contact with a side surface of the base region  6   b  in the active area  101 , bottom surfaces of the separation regions  7   b , and bottom surfaces of guard rings  8   b . An n + -type source region  7   a  having a higher impurity concentration than that of the drift layer  2  is selectively provided in an upper portion of the base region  6   b  so as to be in contact with the base contact region  8   a . The other configurations are the same as those of the semiconductor device according to the first embodiment, and thus, redundant descriptions will be omitted. 
     After the second base-bottom embedded region  5 , as illustrated in  FIG. 6 , is selectively formed on the first base-bottom embedded region  4   a , the n-type semiconductor layer  66  is epitaxially grown on the top surfaces of the second base bottom embedded region  5 , the n-ion implanted layer  5   p  and the drift layer  2  as illustrated in  FIG. 19 . An oxide film made of SiO 2  is deposited on a top surface of the semiconductor layer  66  by CVD technique and the like. A photoresist film is applied to a top surface of the oxide film, and a mask pattern is delineated to the oxide film by photolithography technique, dry etching technique and the like. Using the delineated oxide film as an ion-implantation mask, p-type impurity ions such as aluminum (Al) are selectively implanted into the semiconductor layer  66  from the upper side of the semiconductor layer  66  by multiple-energy ion implantation. As a result, as illustrated in  FIG. 20 , a base region  6   bp  is formed on the top surfaces of the second base-bottom embedded region  5  and the n-ion implanted layer  5   p.    
     After removing the oxide film used as the ion-implantation mask, p-type impurity ions such as aluminum (Al) are implanted into the base region  6   bp  and the semiconductor layer  66  from the upper sides of the base region  6   bp  and the semiconductor layer  66  by multiple-energy ion implantation. As a result, as illustrated in  FIG. 21 , a base contact region  8   p  is formed on upper portions of the base region  6   bp  and the semiconductor layer  66 . 
     Thereafter, a photoresist film is applied to a top surface of the base contact region  8   p , and a mask pattern is delineated to the photoresist film by photolithography technique and the like. Using the delineated photoresist film as an ion-implantation mask, n-type impurity ions such as phosphorus (P) are selectively implanted into the base contact region  8   p  from the upper side of the base contact region  8   p . As a result, as illustrated in  FIG. 22 , the n + -type source region  7   a  is formed in the base contact region  8   a  on the base region  6   b . Further, the n + -type separation regions  7   b  which penetrate the base contact region  8   p  extending on the semiconductor layer  66  to reach the semiconductor layer  66  are formed. Thus, the p + -type guard rings  8   b  are formed in the concentric ring shapes so as to be separated from each other. Each of the separation regions  7   b  contains not only the ion-implanted n-type impurities but also the p-type impurities doped in the base contact region  8   a . In such case, since each impurity concentration of the p + -type base contact region  8   a  and the n + -type source region  7   a  is more than an order of magnitude higher than the impurity concentration of the semiconductor layer  66  or the base region  6   b , the base contact region  8   a  and the guard rings  8   b  may be the same depth. Further, each depth of the separation regions  7   b  may be the same as the source region  7   a . In addition, although the separation regions  7   b  have been described as n-type semiconductor layers, the separation regions  7   b  may be p-type semiconductor layers. Further, after the p-type base region  6   b  has been grown on the entire surface by epitaxial growth, the semiconductor layer  66  may be formed by implantation of n-type impurity ions. 
     Thereafter, the trench  9  is formed by CVD technique, photolithography technique, dry etching technique and the like. The trench  9  penetrates the source region  7   a , the base region  6   b  and the n-ion implanted layer  5   p  to reach the gate-bottom protection region  4   b . The carbon (C) film is deposited on the exposed surface of the trench  9  by carbon sputtering technique and the like. The ion-implanted n-type and p-type impurity ions are simultaneously activated by activation annealing and the like. After removing the carbon film, the field insulating film  10  is selectively formed on the top surfaces of the guard rings  8   b  and the separation regions  7   b  by CVD technique, photolithography technique, dry etching technique, and the like. As illustrated in  FIG. 23 , the gate insulating film  11   p  such as a SiO 2  film is formed on the bottom surface and sidewall of the trench  9 , and on the top surfaces of the source region  7   a  and the base contact region  8   a  by thermal oxidation method or CVD technique. Then, the polysilicon layer  12   p  to which impurities, such as phosphorus (P) and boron (B), are doped at a high concentration is deposited so as to fill the trench  9  by CVD technique and the like. As illustrated in  FIG. 23 , the polysilicon layer  12   p  extends so as to cover the top surface of the field insulating film  10  in the outer-edge area  102 . The subsequent process steps are the same as the process steps illustrated in  FIGS. 13 and 14 , and thus, redundant descriptions will be omitted. 
     In the first modification of the first embodiment, the n + -type separation regions  7   b  are formed in the outer-edge area  102  so as to penetrate the p + -type base contact region  8   a  extending from the active area  101  to reach the n-type semiconductor layer  66 . Then, the p-type guard rings  8   b  are formed to be separated from each other in the concentric rings. In the first modification of the first embodiment, the mesa-groove-forming process is not necessary, and the manufacturing process may be shortened. Further, the guard rings  8   b  can be provided by forming the separation regions  7   b  by the implantation of the n-type impurity ions. Since the implantation of n-type impurity ions can be executed even at room temperature, the photoresist film can be used as the ion-implantation mask. As described above, it is not necessary to deposit any oxide film and the like, and the guard-ring-forming process can be shortened. In addition, in the photolithography technique, a fine pattern of the photoresist film can be made. And further, since the top surface from the active area  101  to the outer-edge area  102  may be flat, the pattern of the photoresist film can be made further finer, and the patterns of the guard rings  8   b  formed on the outer-edge area  102  can be miniaturized. Thus, the size of the semiconductor chip can be reduced. As described above, in the first modification of the first embodiment, the man-hours of the guard-ring-forming process and the mesa-groove-forming process can be cut down, and it is possible to shorten the manufacturing time of the semiconductor device and to reduce the manufacturing cost. 
     (Second Modification) 
     As illustrated in  FIG. 24 , a semiconductor device according to a second modification of the first embodiment differs from the first modification of the first embodiment in that a mesa groove  9   b  is provided at the boundary between the active area  101  and the outer-edge area  102 . Further, a p + -type base contact region  8   c  provided on a top surface of a p-type base region  6   c  in the active area  101  extends to the top surface of the drift layer  2  in the outer-edge area  102  via the mesa groove  9   b . An n + -type source region  7   c  having a higher impurity concentration than the drift layer  2  is selectively provided on an upper portion of the base region  6   c  so as to be in contact with the base contact region  8   c . The other configurations are the same as those of the semiconductor device according to the first modification of the first embodiment, and thus, redundant descriptions will be omitted. 
     After the second base-bottom embedded region  5 , as illustrated in  FIG. 6 , is selectively formed on the first base-bottom embedded region  4   a , a p-type base region  6   cp  is epitaxially grown on the top surfaces of the second base-bottom embedded region  5 , the n-ion implanted layer  5   p  and the drift layer  2  as illustrated in  FIG. 25 . An oxide film made of SiO 2  is deposited on a top surface of the base region  6   cp  by CVD technique and the like. A photoresist film is applied to a top surface of the oxide film, and a mask pattern is delineated to the oxide film by photolithography technique, dry etching technique and the like. Using the delineated oxide film  71  as an etching mask, a part of the base region  6   cp  is selectively etched by dry etching technique and the like to form the mesa groove  9   b  as illustrated in  FIG. 26 . In the outer-edge area  102 , the base region  6   cp  remains on the top surface of the drift layer  2 . 
     After removing the oxide film  71  used as the etching mask, p-type impurity ions such as aluminum (Al) are implanted into the entire surface of the base region  6   cp  from the upper side of the base region  6   cp  by multiple-energy ion implantation. As a result, as illustrated in  FIG. 27 , a base contact region  8   cp  is formed on the top surfaces of the base region  6   c  and the drift layer  2 . 
     Then, a photoresist film is applied to a top surface of the base contact region  8   cp , and a mask pattern is delineated to the photoresist film by photolithography technique and the like. Using the delineated photoresist film  81  as an ion-implantation mask, n-type impurity ions such as phosphorus (P) are selectively implanted into the base contact region  8   cp  from the upper side of the base contact region  8   cp . As a result, as illustrated in  FIG. 28 , the n + -type source region  7   c  is formed in the base contact region  8   c  on the base region  6   c . Further, the n + -type separation regions  7   d  which penetrate the base contact region  8   c  extending on the top surface of the drift layer  2  and reach the drift layer  2 , are formed. In such case, the base contact region  8   cp  left in the active area  101  implements the base contact region  8   c . Further, portions of the base contact region  8   cp  sandwiched between the separation regions  7   d  implement the p + -type guard rings  8   d  which are separated from each other and formed in the concentric ring shapes. Each of the separation regions  7   d  contains not only the ion-implanted n-type impurities but also the p-type impurities doped in the base contact region  8   c . The guard rings  8   d  and the separation regions  7   d  are alternately provided in contact with each other. The impurity concentration of the second conductivity type (p-type) impurities in the guard rings  8   d  is the same as the impurity concentration of the second conductivity type (p-type) impurities in the base contact region  8   c . Further, the impurity concentration of the first conductivity type (n-type) impurities in the separation regions  7   d  is the same as the impurity concentration of the first conductivity type impurities (n-type) in the source region  7   c . In addition, although the separation regions  7   d  have been described as n-type semiconductor layers, the separation regions  7   d  may be p-type semiconductor layers. 
     Thereafter, the trench  9  is formed by CVD technique, photolithography technique, dry etching technique and the like. The trench  9  penetrates the source region  7   c , the base region  6   c  and the n-ion implanted layer  5   p  to reach the gate-bottom protection region  4   b . The carbon (C) film is deposited on the exposed surface of the trench  9  by carbon sputtering technique and the like. The implanted n-type and p-type impurity ions are simultaneously activated by activation annealing and the like. After removing the carbon film, the field insulating film  10   a  is selectively formed on the top surfaces of the guard ring  8   d  and the separation region  7   d  by CVD technique, photolithography technique, dry etching technique and the like. As illustrated in  FIG. 29 , the gate insulating film  11   p  such as a SiO 2  film is formed on the bottom surface and sidewall of the trench  9 , and on the top surfaces of the source region  7   c  and the base contact region  8   c  by thermal oxidation method or CVD technique. Then, the polysilicon layer  12   p  to which impurities, such as phosphorus (P) and boron (B), are doped at a high concentration is deposited so as to fill the trench  9  by CVD technique and the like. As illustrated in  FIG. 29 , the polysilicon layer  12   p  extends so as to cover the top surface of the field insulating film  10   a  in the outer-edge area  102 . The subsequent steps are the same as the steps illustrated in  FIGS. 13 and 14 , and thus, redundant descriptions will be omitted. 
     In the second modification of the first embodiment, the mesa groove  9   b  is provided at the boundary between the active area  101  and the outer-edge area  102 , and in the outer-edge area  102 , the n + -type separation regions  7   d  which penetrate the p + -type base contact region  8   c  extending from the active area  101  and reach the n-type drift layer  2  are formed. Then, the p-type guard rings  8   d  are formed to be separated from each other and in the concentric rings. In the second modification of the first embodiment, although the mesa-groove forming process is introduced, the base contact region  8   c  is formed by ion-implantation to the entire top surface of the base region  6   cp  without any mask, a number of photomasks and a number of manufacturing processes can be reduced. Further, the guard rings  8   d  are provided by forming the separation regions  7   d  by implantation of the n-type impurity ions. Since the implantation of n-type impurity ions can be executed even at room temperature, the photoresist film  81  can be used as the ion-implantation mask. As described above, it is not necessary to deposit any oxide film and the like, and the guard-ring-forming process can be shortened. In addition, in the photolithography technique, the fine pattern of the photoresist film can be formed, and the patterns of the guard rings  8   b  formed on the outer-edge area  102  can be miniaturized. Thus, the size of the semiconductor chip can be reduced. As described above, in the second modification of the first embodiment, the man-hours of the base-contact-region-forming process and guard-ring-forming process can be cut down, and it is possible to shorten the manufacturing time of the semiconductor device and to reduce the manufacturing cost. 
     Second Embodiment 
     &lt;Structure of Semiconductor Device&gt; 
     As illustrated in  FIG. 30 , a semiconductor device according to a second embodiment of the present invention differs from the first embodiment in that a mesa groove  9   c  penetrating the base region  6   d  is provided on the outer-edge area  102  and a plurality of p + -type guard rings ( 4   c ,  5   a ) and a plurality of n + -type separation regions  5   n  are provided on the drift layer  2 . Each of the guard rings ( 4   c ,  5   a ) is implemented by a p + -type first region  4   c  and a p + -type second region  5   a . The second regions  5   a  of the guard ring ( 4   c ,  5   a ) and the separation regions  5   n  are alternately provided in contact with each other. The first region  4   c  is provided at the same depth level as the first base-bottom embedded region  4   a  and the gate-bottom protection region  4   b , and the second region  5   a  is at the same depth level as the second base-bottom embedded region  5 . An n + -type source region  7   e  having a higher impurity concentration than the drift layer  2  is selectively provided on the base region  6   d  so as to be in contact with the base contact region  8   e . A field insulating film  10   b  and an interlayer insulating film  13   b  extend from the vicinity of the boundary between the active area  101  and the outer-edge area  102  to a bottom of the mesa groove  9   c . The other configurations are the same as those of the semiconductor device according to the first modification of the first embodiment, and thus, redundant descriptions will be omitted. 
     In the semiconductor device according to the second embodiment, each of the guard rings ( 4   c ,  5   a ) is implemented by the first region  4   c  and the second region  5   a . The first region  4   c  may be formed by simultaneously implanting the p-type impurity ions with the first base-bottom embedded region  4   a  and the gate-bottom protection region  4   b  located at the same depth level. Similarly, the second region  5   a  may be formed by simultaneously implanting the p-type impurity ions with the second base-bottom embedded region  5  located at the same depth level. As described above, in the second embodiment, the guard rings ( 4   c ,  5   a ) can be formed in the forming process of the first base-bottom embedded region  4   a  and the gate-bottom protection region  4   b  and the forming process of the second base-bottom embedded region  5 . Since a dedicated photomask of guard-ring-forming and the guard-ring-forming process may be cut down, it is possible to shorten the manufacturing time of the semiconductor device and to reduce the manufacturing cost of the semiconductor device. 
     &lt;Manufacturing Method of Semiconductor Devices&gt; 
     Next, a manufacturing method of the SiC semiconductor device according to the second embodiment will be given by taking a trench gate MOSFET as an example, with reference to the cross-sectional views of  FIGS. 31 to 37 . Note that the manufacturing method of the trench gate MOSFET described below is merely an example and may be achieved by various other manufacturing methods including a modification as long as the gist described in the claims is included. 
     First, the n + -type SiC semiconductor substrate (substrate)  1   p  in which n-type impurities such as nitrogen (N) are doped, is prepared. A photoresist film is applied to the top surface of the n-type drift layer  2  which is epitaxially grown on the top surface of the substrate  1   p , and a mask pattern is delineated to the photoresist film by photolithography technique and the like. Using the delineated photoresist film as an ion-implantation mask, n-type impurity ions such as nitrogen (N) are selectively implanted in the active area  101  of the drift layer  2  from the upper side of the drift layer  2 . Thus, the n + -type n-ion implanted layer  3   p  is formed on the upper portion of the drift layer  2  of the active area  101 . 
     An oxide film made of SiO 2  is deposited on the top surfaces of the n-ion implanted layer  3   p  and the drift layer  2  by CVD technique and the like. A photoresist film is applied to the top surface of the oxide film, and a mask pattern is delineated to the oxide film by photolithography technique, dry etching technique and the like. Using the delineated oxide film as an ion-implantation mask, p-type impurity ions such as aluminum (Al) are implanted into the n-ion implanted layer  3   p  by multiple-energy ion implantation. As a result, as illustrated in  FIG. 31 , in the active area  101 , the p + -type first base-bottom embedded region  4   a  and the p + -type gate-bottom protection region  4   b  are selectively formed on the upper portion of the drift layer  2  so as to be in contact with the n-ion implanted layer  3   p . In the outer-edge area  102 , the p + -type first regions  4   c  are formed on the upper portion of the drift layer  2 . 
     After removing the oxide film used as the ion-implantation mask, n − -type epitaxial layer is grown on top surfaces of the n-ion implanted layer  3   p , the first base-bottom embedded region  4   a , the gate-bottom protection region  4   b , the first region  4   c  and the drift layer  2 . Then, p-type impurity ions are implanted on the entire surface of the epitaxial layer to form a p + -type p-ion implanted layer  55   a  as illustrated in  FIG. 32 . A photoresist film is applied to a top surface of the p-ion implanted layer  55   a , and a mask pattern is delineated to the photoresist film by photolithography technique and the like. Using the delineated photoresist film  50  as an ion-implantation mask, n-type impurity ions such as nitrogen (N) are selectively implanted on the p-ion implanted layer  55   a  from the upper side of the p-ion implantation layer  55   a . As a result, as illustrated in  FIG. 33 , in the active area  101 , the n + -type n-ion implanted layer  5   p  is formed on the n-ion implanted layer  3   p  and the gate-bottom protection region  4   b . Further, a portion of the p-ion implanted layer  55   a  where the n-type impurity ions are not implanted, is formed on the first base-bottom embedded region  4   a  to implement the second base-bottom embedded region  5 . As will be described later, the n-ion implanted layer  3   p  and the n-ion implanted layer  5   p  implement the current spreading layer  3 , and the impurity concentration of the n-ion implantation layer  5   p  is preferably higher than that of the n-ion implantation layer  3   p.    
     In the outer-edge area  102 , the n + -type separation regions  5   n  are formed on the drift layer  2  sandwiched between the first regions  4   c . Then, the portions of the p-ion implantation layer  55   a  left between the separation regions  5   n  implement the p + -type second regions  5   a  which are provided on the first region  4   c . The guard rings ( 4   c ,  5   a ) implemented by the first regions  4   c  and the second regions  5   a  are formed in the concentric ring shapes so as to be separated from each other. Therefore, the second regions  5   a  of the guard ring ( 4   c ,  5   a ) and the separation regions  5   n  are alternately provided in contact with each other. Each of the separation regions  5   n  contains both n-type (first conductivity type) impurities and p-type (second conductivity type) impurities, and the impurity concentration of the p-type (second conductivity type) impurities in the separation regions  5   n  is the same as the impurity concentration of the p-type (second conductivity type) impurities in the second region  5   a . Further, the impurity concentration of the p-type (second conductivity type) impurities in the second region  5   a  is the same as the impurity concentration of the p-type (second conductivity type) impurities in the second base-bottom embedded region  5 . The impurity concentration of the n-type (first conductivity type) impurities in the separation region  5   n  is the same as the impurity concentration of the n-type (first conductivity type) impurities in the current spreading layer  3 , or the n-ion implanted layer  5   p.    
     After removing the photoresist film  50  used as the ion-implantation mask, a p-type base region  6   tp  is epitaxially grown on the top surfaces of the second base-bottom embedded region  5 , the n-ion implanted layer  5   p , the guard rings ( 4   c ,  5   a ) and the separation regions  5   n , as illustrated in  FIG. 34 . An oxide film made of SiO 2  is deposited on a top surface of the base region  6   dp  by CVD technique and the like. A photoresist film is applied to a top surface of the oxide film, and a mask pattern is delineated to the oxide film by photolithography technique, dry etching technique, and the like. Using the delineated oxide film as an etching mask, the base region  6   dp  is selectively etched by dry etching technique and the like to form the mesa groove  9   c  as illustrated in  FIG. 35 . The base region  6   d  is left in the active area  101 , and the top surfaces of the second regions  5   a  of the guard ring ( 4   c ,  5   a ) and the top surface of the separation regions  5   n  are exposed on a bottom surface of the mesa groove  9   c  in the outer-edge area  102 . 
     After removing the etching mask, an oxide film made of SiO 2  is deposited on the top surface of the base region  6   d  and the bottom surface of the mesa groove  9   c  by CVD technique and the like. A photoresist film is applied to a top surface of the oxide film, and a mask pattern is delineated to the oxide film by photolithography technique, dry etching technique and the like. Using the delineated oxide film as an ion-implantation mask, p-type impurity ions such as aluminum (Al) are selectively implanted into the base region  6   d  from the upper side of the base region  6   d  by multiple-energy ion implantation. As a result, the p + -type base contact region  8   e  is formed on the top surface of the base region  6   d  above the second base-bottom embedded region  5  and the n-ion implanted layer  5   p.    
     After removing the oxide film used as the ion-implantation mask, an oxide film made of SiO 2  is deposited on the top surfaces of the base contact region  8   e  and the base region  6   d , and the bottom surface of the mesa groove  9   c  by CVD technique and the like. A photoresist film is applied to a top surface of the oxide film, and a mask pattern is delineated to the oxide film by photolithography technique, dry etching technique and the like. Using the delineated oxide film as an ion-implantation mask, n-type impurity ions such as phosphorus (P) are selectively implanted into the base region  6   d  from the upper side of the base region  6   d . As a result, as illustrated in  FIG. 36 , the n + -type source region  7   e  is formed on the top surface of the base region  6   d  above the n-ion implanted layer  5   p.    
     An oxide film made of SiO 2  is deposited on the top surfaces of the base contact region  8   e  and the source region  7   e , and the bottom surface of the mesa groove  9   c  by CVD technique and the like. A photoresist film is applied to a top surface of the oxide film, and a mask pattern is delineated to the oxide film by photolithography technique, dry etching technique and the like. Using the delineated oxide film as an etching mask, the trench  9  is selectively formed by dry etching technique. The trench  9  penetrates the source region  7   e , the base region  6   d  and the n-ion implanted layer  5   p  to reach the gate-bottom protection region  4   b . After removing the oxide film used as the etching mask, the field insulating film  10   b  is deposited on the exposed surfaces of the trench  9 , the mesa groove  9   c  and the like by CVD technique and the like. A photoresist film is applied to the top surface of the field insulating film  10   b , and a mask pattern is delineated to the photoresist film by photolithography technique, dry etching technique and the like. A part of the field insulating film  10   b  is selectively removed by using the delineated photoresist film as an etching mask. 
     As illustrated in  FIG. 37 , the gate insulating film  11  such as a SiO 2  film is formed on the bottom surface and the sidewall of the trench  9 , and the top surfaces of the source region  7   e  and the base contact region  8   e  by thermal oxidation method or chemical vapor deposition (CVD) technique. Then, a polysilicon layer (doped polysilicon layer) to which impurities, such as phosphorus (P) and boron (B), are doped at a high concentration is deposited so as to fill the trench  9  by CVD technique and the like. 
     Thereafter, a part of the polysilicon layer and a part of the gate insulating film  11  are selectively removed by photolithography technique, dry etching and the like. As illustrated in  FIG. 37 , the insulated-gate electrode structure ( 11 ,  12 ) is formed by patterning the gate insulating film  11  and the gate electrode  12  of the polysilicon layer. Then, an insulating film is deposited on the top surface of the insulated-gate electrode structure ( 11 ,  12 ) implemented by the gate electrode  12  and the gate insulating film  11  by CVD technique and the like. For the insulating film, boro-phospho silicate glass (BPSG), NSG and the like may be used. Then, a part of the deposited insulating film is selectively removed by photolithography technique, dry etching technique and the like. As a result, as illustrated in  FIG. 37 , the interlayer insulating film  13  in which a source electrode contact-hole is opened is formed. Although not illustrated, the gate contact-hole is also opened in the interlayer insulating film  13  so as to expose a part of the gate surface electrode connected to the gate electrode  12  at a position different from the source electrode contact-hole. 
     A metal layer such as a Ni film is deposited by sputtering method or evaporation method and the like, and a pattern of the metal layer is delineated by photolithography technique, RIE technique and the like. Then, by rapid thermal annealing (RTA) technique, for example, at about 1000° C., the source contact layer  14  is formed on the top surfaces of the source region  7   e  and the base contact region  8   e , as illustrated in  FIG. 37 . Then, a barrier metal layer (not illustrated), such as a Ti film, a TiN film and the like, and a metal layer, such as an Al film and the like, are deposited by sputtering technique and the like, and the pattern of the barrier metal layer and the metal layer is delineated by photolithography technique, RIE technique and the like. As a result, as illustrated in  FIG. 30 , a laminated structure of the barrier metal layer (not illustrated) and the source electrode  15  is formed so as to cover the source contact layer  14  and the interlayer insulating film  13 . Further, the patterns of the source electrode  15  and the gate surface electrode are separated, and the gate surface electrode is electrically connected to the gate electrode  12  via an interconnection layer (not illustrated) provided on the field insulating film  10   b.    
     Further, the bottom surface of the substrate  1   p  is polished by chemical mechanical polishing (CMP) technique and the like to adjust the thickness to form the drain region  1 . Thereafter, the drain electrode  16  made of Ti, Ni, Au and the like is deposited on the entire bottom surface of the drain region  1  by sputtering method, evaporation method and the like. Thus, the trench gate type semiconductor device illustrated in  FIG. 30  is completed. 
     In the second embodiment, the mesa groove  9   c  which penetrates the base region  6   d  is formed on the outer-edge area  102 , and the p + -type guard rings ( 4   c ,  5   a ) are provided on the drift layer  2 . Each of the guard rings ( 4   c ,  5   a ) is implemented by the first region  4   c  and the second region  5   a  provided to be in contact with the upper surface of the first region  4   c . The second regions  5   a  of the guard ring ( 4   c ,  5   a ) and the separation regions  5   n  are alternately formed in contact with each other. The first regions  4   c  are simultaneously formed by ion-implantation of the p-type impurity with the first base-bottom embedded region  4   a  and the gate-bottom protection region  4   b  at the same depth level. Similarly, the second regions  5   a  are simultaneously formed by ion-implantation of the p-type impurity with the second base-bottom embedded region  5  at the same depth level. As described above, in the second embodiment, the guard rings ( 4   c ,  5   a ) can be formed in the forming process of the first base-bottom embedded region  4   a  and the gate-bottom protection region  4   b , and the forming process of the second base-bottom embedded region  5 . Therefore, a dedicated photomask of guard-ring-forming and the guard-ring-forming process may be cut down, and it is possible to shorten the manufacturing time of the semiconductor device and to reduce the manufacturing cost of the semiconductor device. 
     In the above description, the first region  4   c  and the second region  5   a  of the guard ring ( 4   c ,  5   a ) have the same width. In the photolithography process, the mask pattern of the second region  5   a  is formed in accordance with the pattern of the first region  4   c  that has been formed before the second region  5   a . A misalignment may occur between the pattern of the first region  4   c  and the mask pattern of the second region  5   a . If the misalignment between the patterns is large, the relaxation of electric-field crowding degrades and it becomes difficult to maintain the withstand voltage of the semiconductor device. 
     In order to suppress the misalignment between the patterns, for example, as illustrated in  FIG. 38 , each width of the second regions  5   b  may be decreased by twice a width d with respect to each width of the first regions  4   d . As the width d, for example, the maximum misalignment width of an aligner used in the photolithography process may be adopted. When using the aligner to align the mask pattern of the second region  5   b  with the pattern of the first region  4   d , the second region  5   b  may be formed without protruding from the top surface of the first region  4   d  even if the resultant misalignment is the maximum misalignment width of the aligner. Further, as illustrated in  FIG. 39 , each width of the second regions  5   a  may be increased by twice the width d with respect to each width of the first regions  4   c . In order to maintain the withstand voltage of the semiconductor device, it is preferable to relax the electric field crowding at a position deeper from the top surface of the drift layer  2 . Therefore, the guard rings ( 4   d ,  5   b ) illustrated in  FIG. 38  in which the first regions  4   d  are wider than the second regions  5   b  are more desirable. 
     Further, as a countermeasure against the misalignment, as illustrated in  FIG. 40 , the first region  4   e  may be a continuous integral pattern and a plurality of second regions  5   b  may be provided to be separated from each other. In such case, even if the mask pattern of the second regions  5   b  is misaligned, the second regions  5   b  will be in contact with the top surface of the first region  4   e , and thus, the influence on relaxation of the electric-field crowding may be suppressed. Further, as illustrated in  FIG. 41 , a plurality of first regions  4   c  may be formed to be separated from each other and the second region  5   c  may be formed as a continuous integral pattern. Also in such case, the influence on relaxation of the electric field crowding caused by the misalignment may be suppressed, and the withstand voltage of the semiconductor device may be maintained. 
     Further, for example, in the guard ring ( 4   d ,  5   b ) illustrated in  FIG. 38 , the implanted p-type impurity ions are distributed in the depth direction as illustrated in  FIG. 42 . In  FIG. 42 , the broken line CB 1  corresponds to the impurity concentration distribution in the first region  4   d , and the solid line CB 2  corresponds to the impurity concentration distribution in the second region  5   b . As illustrated in  FIG. 42 , even when a portion having a flat impurity concentration in the second region  5   b  is removed, a tail of the impurity concentration distribution in which the impurity concentration derived from the second region  5   b  decreases remains in the first region  4   d.    
       FIG. 43  illustrates a case where the tail in the impurity concentration distribution of the ion-implanted p-type impurities on the first region  4   c  is used as a second region  5   t . In such case, in the forming process of the mesa groove  9   c , the second region  5   t  may be partially removed to the depth level of a portion where the impurity concentration is flat by dry etching. As illustrated in  FIG. 43 , the second region  5   t  is made narrower than the first region  4   c  by twice the width d. Therefore, even if the misalignment occurs, the second region  5   t  may be formed on the upper portions of the first regions  4   c , the influence on relaxation of the electric field crowding may be suppressed, and the withstand voltage of the semiconductor device may be maintained. 
     Third Embodiment 
     As illustrated in  FIG. 44 , a semiconductor device according to a third embodiment is manufactured based on a semiconductor substrate  110  having a plane orientation (0001) made of SiC. An orientation flat OF indicating the crystal orientation of the semiconductor substrate  110  is provided on the outer-edge area of the semiconductor substrate  110 . The semiconductor substrate  110  is sliced along a direction in which the plane is inclined by a certain offset angle, or off-angle, with respect to a specific crystal orientation, and the position of the orientation flat OF is determined by the crystal orientation. Instead of the orientation flat OF, a notch may be provided on the outer-edge area of the semiconductor substrate  110 . In  FIG. 44 , the X direction is the &lt;11-20&gt; direction, and the Y direction is the &lt;1-100&gt; direction. On the top surface of the semiconductor substrate  110 , trenches of the semiconductor device extend in a stripe shape along the &lt;11-20&gt; direction, that is, the X direction. 
     As illustrated in  FIG. 45 , in the X direction, the top surface of the semiconductor substrate  110  has an off-angle h of greater than 0° and equal to or less than about 10° in the &lt;11-20&gt; direction with respect to the &lt;0001&gt; (c-axis) direction. The off-angle h is the angle between the plane perpendicular to the c-axis (base plane), which is the (0001) plane, that is the Si plane, or (000-1) plane, that is the C plane, and the top surface of the semiconductor substrate  110 . For example, when an epitaxial layer is grown on the top surface of the semiconductor substrate  110  on which an uneven pattern such as an alignment mark is delineated, the uneven pattern observed on the top surface of the epitaxial layer displaces a certain distance parallel to the main surface of the semiconductor substrate  110  toward the X direction, as illustrated by the arrows in  FIG. 45 . Since the epitaxial layer grows in the c-axis direction, the amount of shift is a value proportional to the thickness of the epitaxial layer. In the direction where the off-angle is not provided, that is the Y direction, no such shift occurs. For example, when the off-angle h is set to 4°, the shift of about 0.112 μm occurs in the X direction when the thickness of the epitaxial layer is about 1.6 μm. 
     Therefore, when the epitaxial layer is grown on the drift layer  2  on which the first region  4   c  is formed, and the second region  5   d  is formed by ion-implantation from the upper side of the epitaxial layer, it is desirable to design a pattern in anticipation of a shifting width based on the thickness of the epitaxial layer. Further, it is desirable to design the width of the second region  5   d  with respect to the first region  4   c  also in consideration of the width of the misalignment in photolithography. 
     Specifically, as illustrated in  FIG. 46 , in the X direction where the off-angle is provided, a width dx between each side surface of the first regions  4   c  and each side surface of the second regions  5   d  may be determined in consideration of the amount of shift based on the thickness of the epitaxial layer and the width of the misalignment in photolithography. Further, as illustrated in  FIG. 47 , in the Y direction where no off-angle is provided, a width dy between each side surface of the first regions  4   c  and each side surface of the second regions  5   d  may be determined in consideration of only the width of the misalignment in photolithography. Thus, by making the width dx in the X direction larger than the width dy in the Y direction, the influence of the shift based on the epitaxial layer thickness can be minimized. 
     Other Embodiments 
     While the insulated gate semiconductor device according to the first to third embodiments of the present invention has been described, it should be understood that the present invention is not intended to be limited to the descriptions of the specification and the drawings implementing part of this disclosure. Various alternative embodiments, examples, and technical applications will be apparent to those skilled in the art according to this disclosure. 
     In the semiconductor device according to the second embodiment, a plurality of p + -type guard rings  4   f  illustrated in  FIG. 48  may be used instead of the guard rings ( 4   c ,  5   a ) in the outer-edge area  102  illustrated in  FIG. 30 . In such case, p-type impurity ions are simultaneously implanted with the first base-bottom embedded region  4   a  and the gate-bottom protection region  4   b  illustrated in  FIG. 31  to form a continuous integral p-ion implanted layer. Then, n-type impurity ions are simultaneously implanted to the p-ion implanted layer with the n-ion implanted layer  3   p , to selectively form the n + -type separation regions  3   n . Thus, the guard rings  4   f  having the concentric ring shapes can be formed so as to be separated from each other. Alternatively, as illustrated in  FIG. 49 , a plurality of p + -type second region  5   f  may be provided inside the guard rings  4   f . In such case, p-type impurity ions are selectively implanted into the p-ion implanted layer simultaneously with the second base-bottom embedded region  5 , to form the second regions  5   f  separated from each other in the p-ion implanted layer. Then, n-type impurity ions are simultaneously implanted into the p-ion implanted layer with the n-ion implanted layer  5   p , to selectively form a plurality of separation regions  3   n . In such way, a plurality of guard rings ( 4   f ,  5   f ) having the concentric ring shapes can be formed so as to be separated from each other. Further, as illustrated in  FIG. 50 , widths of the first regions  4   c  and the second regions  5   e  may be different in the guard rings ( 4   c ,  5   e ) in the outer-edge area  102 . In addition, the widths of the first regions  4   c  and the second regions  5   e , which are different from each other, may be changed in the X direction and the Y direction, respectively. 
     In the first to third embodiments, the MISFET having the trench structure is exemplified, but the present invention is not limited thereto, and the present invention is applicable to a semiconductor device having various trench structures such as an IGBT having a trench structure. As the trench gate IGBT, the n + -type source region  7  of the MISFET illustrated in  FIGS. 2, 18 and 30  may be used as an emitter region, and a p + -type collector region may be provided on the bottom surface of the drift layer  2  instead of the n + -type drain region  1 . The present invention is also applicable to diodes such as a SBD. 
     In the first to third embodiments, the semiconductor device using SiC has been exemplified, but the present invention can also be applied to a semiconductor device using another hexagonal wide bandgap semiconductor such as gallium nitride (GaN), aluminum nitride (AlN), diamond and the like. 
     As described above, it should be noted that the present invention includes various embodiments, which are not disclosed herein, including elements optionally modified as alternatives to those illustrated in the above embodiments and modified examples. Therefore, the scope of the present invention is defined only by the technical features specifying the invention prescribed by the claims reasonably derived from the description heretofore.