Patent Publication Number: US-11658216-B2

Title: Method and structure for metal gate boundary isolation

Description:
PRIORITY 
     This claims the benefits to U.S. Provisional Application Ser. No. 63/137,569 filed Jan. 14, 2021, the entire disclosure of which is incorporated herein by reference. 
    
    
     BACKGROUND 
     The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices that are simultaneously able to support a greater number of increasingly complex and sophisticated functions. To meet these demands, there is a continuing trend in the integrated circuit (IC) industry to manufacture low-cost, high-performance, and low-power ICs. Thus far, these goals have been achieved in large part by reducing IC dimensions (for example, minimum IC feature size), thereby improving production efficiency and lowering associated costs. However, such scaling has also increased complexity of the IC manufacturing processes. Thus, realizing continued advances in IC devices and their performance requires similar advances in IC manufacturing processes and technology. 
     One area of advances is how to provide CMOS devices with proper threshold voltages (Vt) for both NMOS and PMOS transistors for boosting performance while reducing power consumption. Particularly, Vt engineering has been challenging as devices continue to scale down to multi-gate devices, such as FinFET, gate-all-around (GAA) devices including nanowire devices and nanosheet devices, and other types of multi-gate devices. An area of improvement is needed in isolating metal gates of adjacent multi-gate devices. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1 A  is a diagrammatic top view of a semiconductor device, in portion, according to the present disclosure.  FIGS.  1 B,  1 C, and  1 D  are diagrammatic cross-sectional views of the semiconductor device in  FIG.  1 A , in portion, along the “B-B,” “C-C,” and “D-D” line in  FIG.  1 A , respectively, according to the present disclosure. 
         FIG.  2    is a flow chart of a method for fabricating a semiconductor device according to various aspects of the present disclosure. 
         FIGS.  3 A- 1  and  3 A- 2    are diagrammatic cross-sectional views of the semiconductor device in  FIG.  1 A , in portion, along the “B-B” and “C-C” lines in  FIG.  1 A , respectively, at a fabrication stage (such as those associated with the method in  FIG.  2   ) according to an embodiment of the present disclosure. 
         FIGS.  3 A- 3 ,  3 B,  3 C,  3 D,  3 E,  3 F,  3 G,  3 H,  31 , and  3 J  are diagrammatic cross-sectional views of the semiconductor device in  FIG.  1 A , in portion, along the “D-D” line in  FIG.  1 A  at various fabrication stages (such as those associated with the method in  FIG.  2   ) according to an embodiment of the present disclosure. 
         FIG.  4    is a flow chart of a method for fabricating a semiconductor device according to another embodiment of the present disclosure. 
         FIGS.  5 A and  5 B  are diagrammatic cross-sectional views of the semiconductor device in  FIG.  1 A , in portion, along the “D-D” line in  FIG.  1 A  at various fabrication stages (such as those associated with the method in  FIG.  4   ) according to an embodiment of the present disclosure. 
         FIG.  6    is a flow chart of a method for fabricating a semiconductor device according to another embodiment of the present disclosure. 
         FIGS.  7 A and  7 B  are diagrammatic cross-sectional views of the semiconductor device in  FIG.  1 A , in portion, along the “D-D” line in  FIG.  1 A  at various fabrication stages (such as those associated with the method in  FIG.  6   ) according to an embodiment of the present disclosure. 
         FIG.  8    illustrates a diagrammatic cross-sectional view of the semiconductor device in  FIG.  1 A , in portion, according to another embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term encompasses numbers that are within certain variations (such as +/−10% or other variations) of the number described, in accordance with the knowledge of the skilled in the art in view of the specific technology disclosed herein, unless otherwise specified. For example, the term “about 5 nm” may encompass the dimension range from 4.5 nm to 5.5 nm, from 4.0 nm to 5.0 nm, and so on. 
     The present disclosure relates generally to semiconductor structures and fabrication processes, and more particularly to providing diffusion barriers (or isolation) between different metal gates (MG) and/or between different metal layers in the same metal gate. With the continued technology scaling and pitch restrictions, multi-threshold voltage (or multi-V t ) devices may be formed by using dipole engineering and/or patterning different work function metal (WFM) layers. However, metals (such as Al and La) from a HKMG (high-k metal gate) of one device might diffuse into a HKMG of an adjacent device. Such diffusion causes V t  non-uniformity in an IC. For example, transistors that are supposed to have the same Vt (for example, standard Vt) by design may have a large variation in their Vt due to such diffusion during manufacturing process or during the operational life of the IC. The present disclosure relates to preventing (or mitigating) the diffusion and intermixing of metal elements in HKMGs. 
       FIG.  1 A  shows a diagrammatic top view of a semiconductor device  200 , in portion, according to the present disclosure. Referring to  FIG.  1 A , the device  200  includes active regions  204  (two shown) oriented lengthwise generally along “x” direction and gate regions  206  (four shown) oriented lengthwise generally along “y” direction perpendicular to the “x” direction. Transistors such as field effect transistors (FET) may be formed with the gate regions  206  and the active regions  204 . For illustration purposes,  FIG.  1 A  illustrates two FETs,  200 A and  200 B, in the device  200 . The semiconductor device  200  may be an intermediate device fabricated during processing of an IC, or a portion thereof, that may comprise static random access memory (SRAM) and/or logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs such as FinFETs and gate-all-around devices, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof. 
       FIGS.  1 B,  1 C, and  1 D  are diagrammatic cross-sectional views of the semiconductor device  200 , in portion, along the “B-B,” “C-C,” and “D-D” lines in  FIG.  1 A , respectively, according to the present disclosure. The embodiments of FETs  200 A and  200 B illustrated in  FIGS.  1 B,  1 C, and  1 D  are FinFETs, where their channel layers are in the shape of one or more semiconductor fins  215 . In various embodiments, the FETs  200 A and  200 B can have other configurations. For example, either or both of the FETs  200 A and  200 B can be a FinFET, a nanowire FET, a nanosheet FET, or a planar FET. 
     Referring to  FIGS.  1 B- 1 D  collectively, the device  200  includes a substrate (e.g., a wafer)  202 . In the depicted embodiment, the substrate  202  includes silicon. Alternatively, or additionally, the substrate  202  includes another semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Alternatively, the substrate  202  is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. 
     Each of the FETs  200 A and  200 B includes a pair of source/drain features  260 . For n-type FET (or NFET), the source/drain features  260  are of n-type. For p-type FET (or PFET), the source/drain features  260  are of p-type. In the depicted embodiment, the source/drain features  260  are higher than the semiconductor channel layer (the fins  215 ) in the same FET to apply stress to the semiconductor channel layer. The source/drain features  260  may be formed by epitaxially growing semiconductor material(s) (e.g., Si or SiGe) to fill trenches in the device  200 , for example, using CVD deposition techniques (e.g., Vapor Phase Epitaxy), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The source/drain features  260  are doped with proper n-type dopants and/or p-type dopants. For example, for NFET, the source/drain features  260  may include silicon and be doped with carbon, phosphorous, arsenic, other n-type dopant, or combinations thereof; and for PFET, the source/drain features  260  may include silicon, silicon germanium, or germanium and be doped with boron, other p-type dopant, or combinations thereof. In some embodiments, one of the FETs  200 A and  200 B is an NFET and the other is a PFET and they collectively form a CMOSFET. In some embodiments, both the FETs  200 A and  200 B are NFET or both are PFET. In some embodiments, the gate electrodes of the FETs  200 A and  200 B share some common metal layers, as will be further discussed. 
     Each of the FETs  200 A and  200 B further includes one or more semiconductor fins (or simply, fins)  215  extending from the substrate  202  and through isolation features  230 . The fins  215  connect the pair of source/drain features  260  and serve as the transistor channels for the respective FET. In the embodiment depicted in  FIGS.  1 B- 1 D , each FET  200 A and  200 B includes a single fin  215 . In alternative embodiments, each FET  200 A and  200 B may include a single fin  215  or multiple fins  215 . The fins  215  may have a height (along the “z” direction) about 40 nm to about 70 nm and a width (along the “y” direction) about 4 nm to about 8 nm, for example. 
     The fins  215  may include crystalline silicon, germanium, silicon germanium, or other suitable semiconductor materials; and may be formed using any suitable methods including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in an embodiment, a sacrificial layer is formed over the substrate  202  and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used as a masking element for patterning the fins  215 . For example, the masking element may be used for etching recesses into semiconductor layers over or in the substrate  202 , leaving the fins  215  on the substrate  202 . The etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. 
     The device  200  further includes isolation feature(s)  230  to isolate various regions, such as the various active regions  204 . The isolation features  230  include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material (for example, including silicon, oxygen, nitrogen, carbon, or other suitable isolation constituent), or combinations thereof. In an embodiment, the isolation features  230  are formed by etching trenches in or over the substrate  202  (e.g., as part of the process of forming the fins  215 ), filling the trenches with an insulating material, and performing a chemical mechanical planarization (CMP) process and/or an etching back process to the insulating material, leaving the remaining insulating material as the isolation features  230 . The isolation features  230  can include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and/or local oxidation of silicon (LOCOS) structures. The isolation features  230  can include multiple layers of insulating materials. 
     As shown in  FIGS.  1 B- 1 D , the FET  200 A includes a gate stack  240 A engaging the fin  215  and the FET  200 B includes a gate stack  240 B engaging another fin  215 . The gate stacks  240 A and  240 B are provided in the gate region  206 . The gate stack  240 A includes an interfacial layer  280 , a gate dielectric layer (such as a high-k gate dielectric layer)  282 , a work function metal (WFM) layer  284 A, a diffusion barrier  304 , another WFM layer  284 B, and a bulk metal layer  286 . The gate stack  240 B includes the interfacial layer  280 , the gate dielectric layer  282 , the WFM layer  284 B, and the bulk metal layer  286 . 
     In an embodiment, the interfacial layer  280  includes a dielectric material such as silicon oxide (SiO 2 ) or silicon oxynitride (SiON), and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable methods. The gate dielectric layer  282  may include SiO 2  in an embodiment. The gate dielectric layer  282  may include HfO 2 , HfSiO, HfSiO 4 , HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO 2 , ZrSiO 2 , AlSiO, Al 2 O 3 , TiO 2 , LaO, LaSiO, Ta 2 O 3 , Ta 2 O 5 , Y 2 O 3 , SrTiO 3 , BaZrO, BaTiO 3  (BTO), (Ba,Sr)TiO 3  (BST), Si 3 N 4 , hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloy, other suitable high-k dielectric material, or combinations thereof. High-k dielectric material generally refers to dielectric materials having a high dielectric constant, for example, greater than that of silicon oxide (k≈3.9). The gate dielectric layer  282  may be formed by ALD and/or other suitable methods. 
     In an embodiment, the FETs  200 A and  200 B have different threshold voltages, which are provided at least in part by the different WFM layers  284 A and  284 B therein. Each of the WFM layers  284 A and  284 B may include one layer or multiple layers of metallic materials. Each of the WFM layers  284 A and  284 B can include an n-type work function metal or a p-type work function metal. Example n-type work function metals include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, TiAlN, other n-type work function material, or combinations thereof. Example p-type work function metals include TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN ZrSi 2 , MoSi 2 , TaSi 2 , NiSi 2 , other p-type work function material, or combinations thereof. The WFM layers  284 A and  284 B may be deposited by ALD, CVD, PVD, and/or other suitable process. 
     Referring to  FIG.  1 D , the WFM layer  284 B of the FET  200 B and the WFM layer  284 A of the FET  200 A are disposed at the same stack level. For example, both are disposed directly on the gate dielectric layer  282  in the depicted embodiment. The device  200  further includes a diffusion barrier  302  disposed laterally between the WFM layer  284 B of the FET  200 B and the WFM layer  284 A of the FET  200 A. The diffusion barrier  302  prevents the metal elements of the WFM layers  284 A and  284 B of the two FETs from intermixing. In the FET  200 A, the diffusion barrier  304  is disposed between the WFM layers  284 A and  284 B and prevents the metal elements of the WFM layers  284 A and  284 B of the same FET from intermixing. In the present embodiment, the diffusion barrier  304  is conductive. Thus, the layers  284 A,  304 ,  284 B, and  286  in the gate stack  240 A collectively function as a gate electrode. In embodiments, the diffusion barrier  302  may be conductive or insulative. Formation of the diffusion barriers  302  and  304  will be discussed in detail later. 
     Having the diffusion barriers  302  and  304  advantageously maintains the threshold voltages of the FETs  200 A and  200 B during manufacturing processes and throughout the operational life of the device  200 . It also improves the uniformity of the threshold voltages of the same type of FETs in the device  200  according to design specification. For example, the device  200  may provide FETs with various threshold voltages (Vt), such as ultra-low Vt, low Vt, standard Vt, high Vt, and so on. The different threshold voltages may be provided using different WFM layers in different FETs or by incorporating different dipole materials in the gate stacks of different FETs. Without the diffusion barriers (such as  302  and  304 ), the different WFM layers or different dipole materials may diffuse and intermix between different FETs, undesirably causing variations in the FETs&#39; threshold voltages to be out of design specification. For example, aluminum, a common metal for work function engineering, is known to diffuse through various materials. Without the diffusion barriers (such as  302  and  304 ), aluminum in a WFM layer of a gate stack is likely to diffuse into an adjacent WFM layer of the same gate stack or another gate stack. Such diffusion of aluminum would alter the intended work function of the gate stack, thus altering the intended Vt of the FET. Having the diffusion barriers  302  and  304  solves the above problems. 
     The bulk metal layer  286  may include a metal such as aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and/or other suitable materials; and may be deposited using plating, CVD, PVD, or other suitable processes. In the embodiment shown in  FIG.  1 D , the gate stacks  240 A and  240 B share some common metal layers such as the WFM layer  284 B and the bulk metal layer  286  and these common metal layers electrically connect the gate stacks  240 A and  240 B. In various embodiments, the gate stacks  240 A and  240 B may share at least one common metal layer or does not share any common metal layer (i.e., not electrically connected by a common metal layer). 
     Referring to  FIGS.  1 B- 1 C , the device  200  further includes gate spacers  247  over sidewalls of the gate stacks  240 A and  240 B. The gate spacers  247  may include silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN)). In some embodiments, the gate spacers  247  include a multi-layer structure, such as a first dielectric layer that includes silicon nitride and a second dielectric layer that includes silicon oxide. The gate spacers  247  may be formed by deposition (e.g., CVD, PVD, ALD, etc.) and etching processes (e.g., dry etching). 
     The device  200  further includes a contact etch stop layer (CESL)  268  disposed over the isolation features  230 , the source/drain features  260 , and the gate spacers  247 . The CESL  268  includes silicon and nitrogen, such as silicon nitride or silicon oxynitride. The CESL  268  may be formed by a deposition process, such as CVD, or other suitable methods. The device  200  further includes an inter-layer dielectric (ILD) layer  270  over the CESL  268 . The ILD layer  270  includes a dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS formed oxide, PSG, BPSG, low-k dielectric material, other suitable dielectric material, or combinations thereof. The ILD layer  270  may be formed by a deposition process, such as CVD, flowable CVD (FCVD), or other suitable methods. 
       FIG.  2    is a flow chart of a method  100  for fabricating an embodiment of the device  200  according to various aspects of the present disclosure. Additional processing is contemplated by the present disclosure. Additional steps can be provided before, during, and after the method  100 , and some of the steps described can be moved, replaced, or eliminated for additional embodiments of the method  100 . The method  100  is described below in conjunction with  FIGS.  3 A- 1  through  3 J .  FIGS.  3 A- 1 ,  3 A- 2 , and  3 A- 3    are diagrammatic cross-sectional views of the device  200 , in portion, along the “B-B,” “C-C,” and “D-D” lines, respectively, in  FIG.  1 A .  FIGS.  3 B- 3 J  are diagrammatic cross-sectional views of the device  200 , in portion, along the “D-D” line in  FIG.  1 A  at various fabrication stages associated with the method  100  in  FIG.  2   . 
     At the operation  102 , the method  100  ( FIG.  2   ) provides an initial structure (or a workpiece) of the device  200 , such as shown in  FIGS.  3 A- 1 ,  3 A- 2 , and  3 A- 3   . The device  200  includes substrate  202 , fins  215 , source/drain features  260 , gate spacers  247 , CESL  268 , and ILD  270 , as discussed above. The fins  215  are exposed in a gate trench  275  which is resulted from the removal of a dummy gate from a gate region  206  ( FIG.  1 A ). 
     At the operation  104 , the method  100  ( FIG.  2   ) forms an interfacial gate dielectric layer (or simply, interfacial layer)  280  over the fins  215  and form a gate dielectric layer (such as a high-k (or HK) gate dielectric layer)  282  over the interfacial layer  280 , such as shown in  FIG.  3 B . Turning to  FIG.  3 B , in the depicted embodiment, the interfacial layer  280  is disposed on surfaces of the fins  215 , but not on the isolation features  230 . For example, the interfacial layer  280  may be formed by oxidizing semiconductor material(s) in the fins  215 , which does not produce the interfacial layer  280  on the isolation features  230 . In some embodiments, the interfacial layer  280  is also disposed on the isolation features  230 , for example, by atomic layer deposition (ALD) of a dielectric material as the interfacial layer  280 . The interfacial layer  280  includes a dielectric material, such as SiO 2 , HfSiO, SiON, other silicon-containing dielectric material, other suitable dielectric material, or combinations thereof. The interfacial layer  280  is formed by any of the processes described herein, such as thermal oxidation, chemical oxidation, ALD, CVD, other suitable process, or combinations thereof. The interfacial layer  280  may have a thickness of about 0.5 nm to about 1.5 nm, for example. In alternative embodiments, the interfacial layer  280  may be omitted in the FETs  200 A and  200 B. 
     The gate dielectric layer  282  is disposed over the interfacial layer  280  and the isolation features  230 . The gate dielectric layer  282  includes HfO 2  in an embodiment. In another embodiment, the gate dielectric layer  282  includes another hafnium-containing high-k dielectric material, such as HfSiO 4 , HfSiON (nitrided hafnium silicate), lanthanum hafnium oxide (such as Hf 2 La 2 O 7 ), HfTaO, HfTiO, HfZrO, hafnium-aluminum-oxide (i.e., HfAlO x ), or hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloy. In another embodiment, the gate dielectric layer  282  includes another high-k dielectric material such as ZrO 2 , ZrSiO 4 , Al 2 SiO 5 , Al 2 O 3 , TiO 2 , La 2 O 3 , La 4 Si 3 O 12 , Ta 2 O 3 , Ta 2 O 5 , Y 2 O 3 , SrTiO 3 , BaZrO 3 , BaTiO 3  (BTO), (Ba,Sr)TiO 3  (BST), or combinations thereof. The gate dielectric layer  282  is formed by any of the processes described herein, such as ALD, CVD, PVD, oxidation-based deposition process, other suitable process, or combinations thereof. The gate dielectric layer  282  may have a thickness of about 0.2 nm to about 1.5 nm, for example. 
     At the operation  106 , the method  100  ( FIG.  2   ) forms a work function metal (WFM) layer  284 A over the gate dielectric layer  282 , such as shown in  FIG.  3 C . In an embodiment, the WFM layer  284 A includes TiN. In some embodiments, the WFM layer  284 A includes another nitride-based metallic material, such as TaN, WN, TiCN, TaCN, WCN, TiAlN, or TaAlN. In some embodiments, the WFM layer  284 A may include TiAlC, TiAlSiC, TaC, TaAl, TaAlC, TaSiAlC, or other suitable work function metal. In some examples, the WFM layer  284 A has a thickness of about 1 nm to about 2.5 nm, such as from about 1 nm to about 1.5 nm. The WFM layer  284 A is formed by any of the processes described herein, such as ALD, CVD, PVD, other suitable process, or combinations thereof. The WFM layer  284 A may include one layer of material or multiple layers of materials. 
     At the operation  108 , the method  100  ( FIG.  2   ) forms an etch mask  290  that covers the area for the FET  200 A and exposes the area for the FET  200 B, such as shown in  FIG.  3 D . The mask  290  includes a material that is different than a material of the WFM layer  284 A and the gate dielectric layer  282  to achieve etching selectivity during the etching of the WFM layer  284 A and during the removal of the etch mask  290 . For example, the mask  290  may include a resist material (and thus may be referred to as a patterned resist layer and/or a patterned photoresist layer). In some embodiments, the mask  290  has a multi-layer structure, such as a resist layer disposed over an anti-reflective coating (ARC) layer. The present disclosure contemplates other materials for the mask  290 , so long as the above etching selectivity is achieved. In some embodiments, the operation  108  includes a lithography process that includes forming a resist layer over the device  200  (e.g., by spin coating), performing a pre-exposure baking process, performing an exposure process using a photomask, performing a post-exposure baking process, and developing the exposed resist layer in a developer solution. After development, the patterned resist layer (e.g., patterned mask  290 ) includes a resist pattern that corresponds with the photomask. Alternatively, the exposure process can be implemented or replaced by other methods, such as maskless lithography, e-beam writing, ion-beam writing, or combinations thereof. 
     At the operation  110 , with the etch mask  290  in place, the method  100  ( FIG.  2   ) etches the WFM layer  284 A and removes it from the transistor  200 B, such as shown in  FIG.  3 E . The gate dielectric layer  282  in the transistor  200 B and a sidewall  284 A′ of the WFM layer  284 A are exposed after the etching finishes. The etching process can be a dry etching process, a wet etching process, or a reactive ion etching process that has a high etching selectivity with respect to the WFM layer  284 A relative to the gate dielectric layer  282 . Thus, the gate dielectric layer  282  is not etched or insignificantly etched by the operation  110 . In some embodiments, the etching process further has an etching selectivity with respect to WFM layer  284 A relative to the mask  290 . In some embodiments, the etching process partially etches the mask  290 . 
     At the operation  112 , with the etch mask  290  or at least a part thereof still in place, the method  100  ( FIG.  2   ) forms a diffusion barrier (or simply, barrier)  302  on the exposed sidewall of the  284 A′ of the WFM layer  284 A, such as shown in  FIG.  3 F . The barrier  302  is not formed on the gate dielectric layer  282  of the FET  200 B. The barrier  302  is formed such that it prevents or substantially blocks chemical elements (such as Al) from diffusing into the WFM layer  284 A in the FET  200 A. In other words, the barrier  302  has low permeability for aluminum and/or other chemical elements that may adversely affect the WFM layer  284 A in the FET  200 A. The following disclosure discusses three ways of forming the barrier  302 . Alternative ways of forming the barrier  302  are also contemplated. 
     In a first embodiment, the operation  112  forms the barrier  302  by applying an oxidizing agent to the sidewall  284 A′. The oxidizing agent reacts with the elements in the sidewall  284 A′ and forms an oxide compound as the barrier  302 . For example, the oxidizing agent may include H 2 O 2  or ozonized DIW (de-ionized water). The composition of the barrier  302  depends on the material of the WFM layer  284 A. In some embodiments, the barrier  302  may include TiO, TION, TiAlO, WO, WCO, WCNO, RuO, WON, TaO, TaCO, TaAlO TaTiO, TiOH, WOH, AlOH, TaOH, or a combination thereof. The oxidizing agent does not react with the gate dielectric layer  282 . Thus, the barrier  302  is not formed on the gate dielectric layer  282 . In some instances, the oxidizing agent helps to improve the quality of the gate dielectric layer  282  by re-oxidizing it or by reducing the 0-vacancies in the gate dielectric layer  282 . For example, oxygen from the oxidizing agent may diffuse into the gate dielectric layer  282  and repair dangling bonds therein. In some embodiments, the barrier  302  has a thickness of about 0.5 nm to about 10 nm. If the barrier  302  is too thin (such as less than 0.5 nm), it may not effectively block aluminum or other elements from diffusing into the WFM layer  284 A. If the barrier  302  is too thick (such as more than 10 nm), it may take up too much space and leave too little space for the WFM layer  284 A for the FET  200 A and the WFM layer  284 B for the FET  200 B (see  FIG.  3 I ). This would go against the downscaling of the device  200 . 
     In a second embodiment, the operation  112  forms the barrier  302  by selectively depositing a tungsten-containing layer on the sidewall  284 A′ as the barrier  302 . The tungsten-containing layer is not deposited on the gate dielectric layer  282 . Thus, the deposition is selective. For example, the operation  112  may form the tungsten-containing layer using a precursor having WCl 5  and H 2  with B 2 H 6  as a reducing agent. Alternatively, the operation  112  may form the tungsten-containing layer using a precursor having WCl 5  and H 2  with SiH 4  as a reducing agent. Alternatively, the operation  112  may form the tungsten-containing layer using a gas mixture of WF 6  and SiH 4 . Alternatively, the operation  112  may form the tungsten-containing layer using a gas mixture of WF 6  and H 2 . In another embodiment, the operation  112  may form the tungsten-containing layer using a precursor having Bis(dimethyl amido-W). The deposition may be performed at a temperature that is in a range of about 150° C. to about 450° C. at a pressure about 10 torr to 350 torr. In this embodiment, the barrier  302  may include W, WC, WCN, WCl, WF, WB, WS, or a combination thereof; and may have a thickness in a range of about 0.5 nm to about 10 nm. The significance of this thickness has been discussed with reference to the first embodiment above. 
     In a third embodiment, the operation  112  forms the barrier  302  by selectively treating the sidewall  284 A′ of the WFM layer  284 A with fluorine (F) radicals. For example, fluorine radicals may be generated from F 2 , CF 4 , NF 3 , other fluorine-containing gases, or a combination thereof. The fluorine radicals react with the sidewall  284 A′ (or a thin outer layer of the WFM layer  284 A) to produce a fluorinated barrier  302 . In this embodiment, the barrier  302  includes the material(s) of the WFM layer  284 A and fluorine. It has been demonstrated that aluminum has strong affinity for fluorine. Thus, the fluorine elements in the barrier  302  can bond with aluminum elements that may come from other layers (such as the WFM layer  284 B) and prevent the aluminum elements from diffusing into the WFM layer  284 A. In this embodiment, the barrier  302  may have a thickness in a range of about 0.5 nm to about 10 nm. The significance of this thickness has been discussed with reference to the first embodiment above. 
     At the operation  114 , the method  100  ( FIG.  2   ) removes the etch mask  290 , for example, by a resist stripping process or other suitable process. As shown in  FIG.  3 G , an outer surface (including a top surface)  284 A″ of the WFM layer  284 A is exposed after the etch mask  290  is removed. 
     At the operation  116 , the method  100  ( FIG.  2   ) selectively forms a diffusion barrier (or simply, barrier)  304  on the exposed outer surface  284 A″ of the WFM layer  284 A, such as shown in  FIG.  3 H . The barrier  304  is not formed on the gate dielectric layer  282  of the FET  200 B. The barrier  304  is formed such that it prevents or substantially blocks chemical elements (such as Al) from diffusing into the WFM layer  284 A in the FET  200 A. In other words, the barrier  304  has low permeability for aluminum and/or other chemical elements that may adversely affect the WFM layer  284 A in the FET  200 A. Further, the barrier  304  is conductive, making it part of the gate electrode for the FET  200 A. The following disclosure discusses two ways of forming the barrier  304 . Alternative ways of forming the barrier  304  are also contemplated. 
     In a first embodiment, the operation  116  forms the barrier  304  by selectively depositing a tungsten-containing layer on the outer surface  284 A″ as the barrier  304 . The tungsten-containing layer is not deposited on the gate dielectric layer  282 . Thus, the deposition is selective. This embodiment of the operation  116  can be the same as the second embodiment of the operation  112 . For example, the operation  116  may form the tungsten-containing layer using a precursor having WCl 5  and H 2  with either B 2 H 6  or SiH 4  as a reducing agent, a precursor having WF 6  and H 2 , a precursor having WF 6  and SiH 4 , or a precursor having Bis(dimethyl amido-W). The deposition may be performed at a temperature that is in a range of about 150° C. to about 450° C. at a pressure about 10 torr to 350 torr. In this embodiment, the barrier  304  may include W, WC, WCN, WCl, WF, WB, WS, or a combination thereof; and may have a thickness in a range of about 0.5 nm to about 10 nm. The significance of this thickness has been discussed with reference to the first embodiment of the operation  112  above. In an embodiment, the barrier  302  and the barrier  304  are formed to have different thicknesses. In an alternative embodiment, the barrier  302  and the barrier  304  are formed to have the same thickness. 
     In a second embodiment, the operation  116  forms the barrier  304  by selectively treating the outer surface  284 A″ with fluorine (F) radicals. This embodiment of the operation  116  can be the same as the third embodiment of the operation  112 . For example, fluorine radicals may be generated from F 2 , CF 4 , NF 3 , other fluorine-containing gases, or a combination thereof. The fluorine radicals react with the outer surface  284 A″ (or a thin outer layer of the WFM layer  284 A) to produce a fluorinated barrier  304 . In this embodiment, the barrier  304  includes the material(s) of the WFM layer  284 A and fluorine. In this embodiment, the barrier  304  may have a thickness in a range of about 0.5 nm to about 10 nm. The significance of this thickness has been discussed above. 
     In some embodiments, the barriers  302  and  304  include different materials. For example, the barrier  302  may be formed using the first embodiment of the operation  112  (thus, the barrier  302  includes an oxide compound), and the barrier  304  includes either a tungsten-containing layer or a fluorine-containing layer as discussed above with reference to the operation  116 . For another example, the barrier  302  includes a tungsten-containing layer, and the barrier  304  includes a fluorine-containing layer. For yet another example, the barrier  302  includes a fluorine-containing layer, and the barrier  304  includes a tungsten-containing layer. In some embodiments, the barriers  302  and  304  include the same materials although they are formed separately. For example, both may include a tungsten-containing layer or a fluorine-containing layer. 
     At operation  118 , the method  100  ( FIG.  2   ) forms another work function metal (WFM) layer  284 B over the gate dielectric layer  282  in the FET  200 B and over the barrier  304  in the FET  200 A, such as shown in  FIG.  3 I . The WFM layer  284 B is also deposited over the barrier  302 . The barrier  302  is disposed horizontally between a portion of the WFM layer  284 B for the FET  200 B and a portion of the WFM layer  284 A for the FET  200 A. In an embodiment, the barrier  302  directly contacts the portion of the WFM layer  284 B for the FET  200 B and the portion of the WFM layer  284 A for the FET  200 A. The barrier  304  is sandwiched between a portion of the WFM layer  284 B for the FET  200 A and the WFM layer  284 A for the FET  200 A. In an embodiment, the barrier  304  directly contacts the portion of the WFM layer  284 B for the FET  200 A and the WFM layer  284 A for the FET  200 A. The barriers  302  and  304  separate (but may not insulate) the WFM layer  284 A from the WFM layer  284 B. The WFM layers  284 A and  284 B include different materials. In an embodiment, the WFM layer  284 B includes aluminum. For example, the WFM layer  284 B may include TiAlN, TaAlN, TiAl, TiAlC, TiAlSiC, TaAl, TaAlC, or TaSiAlC. The barriers  302  and  304  block aluminum in the WFM layer  284 B from diffusing into the WFM layer  284 A. The WFM layer  284 B may include other elements in alternative embodiments. In some examples, the WFM layer  284 B has a thickness of about 1 nm to about 2.5 nm, such as from about 1 nm to about 1.5 nm. The WFM layer  284 B is formed by any of the processes described herein, such as ALD, CVD, PVD, other suitable process, or combinations thereof. The WFM layer  284 B may include one layer of material or multiple layers of materials. 
     At operation  120 , the method  100  ( FIG.  2   ) forms a bulk metal layer  286  over the WMF layer  284 B in the FETs  200 A and  200 B, such as shown in  FIG.  3 J . For example, a CVD process or a PVD process deposits the bulk metal layer  286 , such that it fills any remaining portion of the gate trenches  275  (see  FIGS.  3 A- 1 ,  3 A- 2 , and  3 A- 3   ). The bulk metal layer  286  includes a suitable conductive material, such as Al, W, and/or Cu. The bulk metal layer  286  may additionally or collectively include other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof. In some implementations, one or more WFM layers (not shown) are formed (e.g., by ALD) over the WFM layers  284 A and  284 B before forming the bulk metal layer  286 . In some implementations, a blocking layer (not shown) is formed (e.g., by ALD) over the WFM layers  284 A and  284 B before forming the bulk metal layer  286 , such that the bulk metal layer  286  is disposed on the blocking layer. After the bulk metal layer  286  is deposited, a planarization process may then be performed to remove excess gate materials from the device  200 . For example, a CMP process is performed until a top surface of the ILD layer  270  is reached (exposed). 
     At operation  122 , the method  100  ( FIG.  2   ) performs further fabrications such as forming contacts that electrically connect to the source/drain features  260 , forming gate vias that electrically connect to the bulk metal layer  286 , and forming multi-layer interconnects that connect the transistors  200 A and  200 B to various parts of the device  200  to form a complete IC. 
       FIG.  4    is a flow chart of another embodiment of the method  100 . In this embodiment, the method  100  ( FIG.  4   ) skips (or omits) the operation  112  and proceeds from the operation  110  to the operation  114 . At the operation  114 , the method  100  ( FIG.  4   ) removes the etch mask  290 , as discussed above. The resultant structure is shown in  FIG.  5 A , where the sidewall surface  284 A′ and other outer surfaces  284 A″ are exposed. Then, the method  100  ( FIG.  4   ) proceeds to operation  116 A to form the barriers  302  and  304  simultaneously on the surfaces  284 A′ and  284 A″. The resultant structure is shown in  FIG.  5 B . The barrier  302  is formed on the sidewall  284 A′ and the barrier  304  is formed on other outer surfaces  284 A″. The operation  116 A is the same as the operation  116  discussed with reference to  FIG.  2    except that it processes more surfaces than operation  116  does. For example, in a first embodiment, the operation  116 A forms the barriers  302  and  304  by selectively depositing a tungsten-containing layer on the exposed surfaces  284 A′ and  284 A″ of the WFM layer  284 A, which is similar to the first embodiment of the operation  116 . In a second embodiment, the operation  116 A forms the barriers  302  and  304  by selectively treating the exposed surfaces  284 A′ and  284 A″ of the WFM layer  284 A with fluorine (F) radicals, which is similar to the second embodiment of the operation  116 . In this embodiment of the method  100 , the barriers  302  and  304  include the same material. For example, both may include a tungsten-containing layer or a fluorine-containing layer depending on which embodiment of the operation  116 A is used. After finishing the operation  116 A, the method  100  ( FIG.  4   ) proceeds to the operation  118 , as discussed with reference to  FIG.  2   . 
       FIG.  6    is a flow chart of another embodiment of the method  100 . In this embodiment, the method  100  ( FIG.  6   ) skips (or omits) the operation  116  and proceeds from the operation  114  (see  FIG.  3 G ) to the operation  118 . Thus, the barrier  304  is not formed in this embodiment. At the operation  118 , the method  100  ( FIG.  6   ) forms the WFM layer  284 B over the gate dielectric layer  282  in the FET  200 B, over the barrier  302 , and over the WFM layer  284 A in the FET  200 A, such as shown in  FIG.  7 A . The WFM layer  284 B may directly contact the WFM layer  284 A in the FET  200 A. Then, the method  100  ( FIG.  6   ) proceeds to the operation  120  to form the bulk metal layer  286  over the WMF layer  284 B in the FETs  200 A and  200 B, such as shown in  FIG.  7 B . In this embodiment of the method  100 , only the barrier  302  is formed. 
       FIG.  8    illustrates another embodiment of the device  200  according to the present disclosure. The device  200  includes FETs  200 A,  200 B, and  200 C, one next to another. The FETs  200 A,  200 B, and  200 C include gate stacks  240 A,  240 B, and  240 C, respectively, and the three gate stacks  240 A-C have different work functions. The gate stack  240 A includes WFM layers  284 A,  284 B, and  284 C where the WFM layer  284 A is disposed over the gate dielectric layer  282 , the WFM layer  284 B is disposed over the WFM layer  284 A, and the WFM layer  284 C is disposed over the WFM layer  284 B. The gate stack  240 B includes WFM layer  284 B disposed over the gate dielectric layer  282  and WFM layer  284 C disposed over the WFM layer  284 B. The gate stack  240 C includes WFM layer  284 C disposed over the gate dielectric layer  282 . In an embodiment, the WFM layer  284 C includes an element (such as aluminum) that is prone to out-diffusion. Thus, diffusion barriers  302  and  304  (which may include the same material or different materials as discussed above) are formed between the WFM layer  284 C and the WFM layer  284 B to block the elements in the WFM layer  284 C from diffusing into the WFM layer  284 B. In various embodiments, a gate stack in the device  200  may include any suitable number of WFM layers and the barrier layers  302  and  304  may be formed over any WFM layer. 
     Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and the formation thereof. For example, embodiments of the present disclosure provide methods for forming diffusion barriers on a work function metal layer. The diffusion barrier can effectively block elements (such as aluminum) in adjacent structures from diffusing into the work function metal layer, thereby improving the uniformity of transistors&#39; threshold voltage across an IC. In other words, the same type of transistors in an IC can be provided with a uniform threshold voltage with the present disclosure. The diffusion barriers also reduce defects associated with metal gates during the manufacturing processes and during the operational life of an IC. The present embodiments can be readily integrated into existing CMOS fabrication processes. 
     In one example aspect, the present disclosure is directed to a method that includes depositing a gate dielectric layer over semiconductor channel layers; depositing a work-function (WF) metal layer over the gate dielectric layer; forming an etch mask covering a second portion of the WF metal layer and having an opening above a first portion of the WF metal layer; and etching the WF metal layer through the etch mask, thereby removing the first portion of the WF metal layer while keeping the second portion of the WF metal layer, wherein a sidewall of the second portion of the WF metal layer is exposed after the etching. The method further includes forming a first barrier on the sidewall of the second portion of the WF metal layer and depositing a gate metal layer, wherein a first portion of the gate metal layer is deposited over the gate dielectric layer and at a same level as the first barrier, a second portion of the gate metal layer is deposited over the first barrier and over the second portion of the WF metal layer, and the first barrier is disposed between the first portion of the gate metal layer and the second portion of the WF metal layer. 
     In an embodiment of the method, the gate metal layer includes aluminum and the first barrier has low permeability for aluminum. In another embodiment, the forming of the first barrier includes applying an oxidizing agent to the sidewall of the second portion of the WF metal layer. In a further embodiment, the oxidizing agent includes H 2 O 2  or ozonized de-ionized water. 
     In an embodiment of the method, the forming of the first barrier includes selectively depositing a tungsten-containing layer as the first barrier, wherein the tungsten-containing layer is deposited on the sidewall of the second portion of the WF metal layer but not on the gate dielectric layer. In a further embodiment, the forming of the first barrier includes applying a precursor having WCl 5  and H 2  with either B 2 H 6  or SiH 4  as a reducing agent, WF 6  and SiH 4 , WF 6  and H 2 , or Bis(dimethyl amido-W). 
     In an embodiment, the forming of the first barrier includes selectively treating the sidewall of the second portion of the WF metal layer with fluorine radicals. 
     In another embodiment, after the forming of the first barrier and before the depositing of the gate metal layer, the method further includes removing the etch mask, thereby exposing a top surface of the second portion of the WF metal layer and forming a second barrier on the top surface of the second portion of the WF metal layer. In a further embodiment, the forming of the second barrier includes selectively depositing another tungsten-containing layer as the second barrier, wherein the another tungsten-containing layer is deposited on the top surface of the second portion of the WF metal layer but not on the gate dielectric layer. In another further embodiment, the forming of the second barrier includes selectively treating the top surface of the second portion of the WF metal layer with fluorine radicals. 
     In another example aspect, the present disclosure is directed to a method that includes depositing a gate dielectric layer over a substrate and depositing a work-function (WF) metal layer over the gate dielectric layer, wherein the gate dielectric layer and the WF metal layer are deposited over an area of the substrate defined for first and second devices that have different threshold voltages. The method further includes forming an etch mask covering the WF metal layer for the second device and etching the WF metal layer through the etch mask, thereby removing a first portion of the WF metal layer while keeping a second portion of the WF metal layer, wherein a sidewall of the second portion of the WF metal layer is exposed after the etching. The method further includes removing the etch mask, thereby exposing a top surface of the second portion of the WF metal layer; and forming a first barrier on the sidewall of the second portion of the WF metal layer and forming a second barrier on the top surface of the second portion of the WF metal layer. 
     In an embodiment, the method further includes depositing a gate metal layer, wherein a first portion of the gate metal layer is deposited at a same level as the first barrier and a second portion of the gate metal layer is deposited over the first barrier and the second barrier. In a further embodiment, the gate metal layer includes aluminum and the first and the second barriers have low permeability for aluminum. 
     In an embodiment, both the first barrier and the second barrier include tungsten. In another embodiment, both the first barrier and the second barrier include fluorine. 
     In yet another example aspect, the present disclosure is directed to a semiconductor structure that includes a first transistor adjacent a second transistor. The first transistor includes a first gate metal layer over a gate dielectric layer, and the second transistor includes a second gate metal layer over the gate dielectric layer, wherein the first and the second gate metal layers include different materials. The semiconductor structure further includes a first barrier disposed horizontally between the first gate metal layer and the second gate metal layer, wherein one of the first and the second gate metal layers includes aluminum and the first barrier has low permeability for aluminum. 
     In an embodiment, the first gate metal layer also extends above the first barrier and the second gate metal layer. In a further embodiment, the semiconductor structure further includes a second barrier layer disposed vertically between the first gate metal layer and the second gate metal layer. 
     In an embodiment, the first barrier includes oxygen and a material included in the second gate metal layer. In another embodiment, the first barrier includes tungsten or fluorine. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.