Patent Publication Number: US-10333480-B2

Title: Crystal oscillator device and method of measuring crystal oscillator characteristic

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This present application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2016-116461, filed on Jun. 10, 2016, the entire contents of which are incorporated herein by reference. 
     FIELD 
     The present disclosure relates to a crystal oscillator device and a method of measuring a characteristic of a crystal oscillator. 
     BACKGROUND 
     A technique of measuring an output frequency of a crystal oscillator is known in which an oscillation output of a crystal oscillator is transmitted in a form of a radio wave from a transmission antenna to a temperature tank such that the radio wave is received by a reception antenna provided in the temperature tank, and the output frequency is measured based on an output of the reception antenna. 
     [Patent Document 1] Japanese Laid-open Patent Publication No. 01-186003 
     However, it is difficult to detect a state of the crystal oscillator before a transition to an output stop state (for example, clock stop) based on such a measurement result of the output frequency of the crystal oscillator that is obtained according to the conventional technique as described above. Such an output stop of the crystal oscillator may occur suddenly due to abnormality of the crystal oscillator or the like. 
     SUMMARY 
     According to one aspect of the disclosure, a crystal oscillator device is provided, which includes: a casing; a crystal piece; a pair of excitation electrodes; a transmission antenna electrically coupled to one of the excitation electrodes; a reception antenna configured to receive a radio wave from the transmission antenna; and an alarm generator configured to generate an alarm based on a signal whose amplitude is equal to or less than a reference value, the signal being received by the reception antenna. 
     The object and advantages of the embodiment will be realized and attained by means of the elements and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1A  is a top view schematically illustrating a configuration of a crystal oscillator according to a first embodiment. 
         FIG. 1B  is a cross-sectional view along a line B-B in  FIG. 1A . 
         FIG. 2  is an explanatory diagram of an implementation example of a transmission antenna and a reception antenna. 
         FIG. 3  is a diagram schematically illustrating an example of a circuit configuration of a crystal oscillator device including a crystal oscillator and an IC. 
         FIG. 4  is a diagram for illustrating an example of an inverting amplifier. 
         FIG. 5  is an explanatory diagram of characteristics in a case where the crystal oscillator is a normal product. 
         FIG. 6  is an explanatory diagram of an output stop event of the crystal oscillator due to abnormality. 
         FIG. 7A  is a diagram illustrating a time-series waveform of a signal appearing at a point A in the case of an abnormal product. 
         FIG. 7B  is a diagram illustrating a time-series waveform of a signal appearing at a point B in the case of an abnormal product. 
         FIG. 7C  is a diagram illustrating a time-series waveform of a signal appearing at a point C in the case of an abnormal product. 
         FIG. 7D  is a diagram illustrating a time-series waveform of a signal appearing in the reception antenna in the case of an abnormal product. 
         FIG. 8  is a diagram explaining an example of an operation according to the first embodiment. 
         FIG. 9  is a diagram explaining an implementation example of transmission antenna according to a second embodiment. 
         FIG. 10A  is a cross-sectional view schematically illustrating an implementation example of a reception antenna. 
         FIG. 10B  is a cross-sectional view schematically illustrating another implementation example of a reception antenna. 
         FIG. 10C  is a cross-sectional view schematically illustrating yet another implementation example of a reception antenna. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     In the following, embodiments are described in detail with reference to appended drawings. 
     First Embodiment 
       FIG. 1A  is a top view schematically illustrating a configuration of a crystal oscillator  100  according to a first embodiment, and  FIG. 1B  is a cross-sectional view along a line B-B in  FIG. 1A .  FIG. 2  is a diagram explaining an example of implementation of a transmission antenna  60  and a reception antenna  69  according to the second embodiment, and a two-side view (plan views illustrating an upper surface and a lower surface) of a crystal piece  10 . In  FIG. 1A , a lid of a casing  30  is not illustrated so that an inside can be seen, and invisible elements (an external electrode  41 , etc.) are indicated by broken lines. In addition, in  FIG. 1A , only an outline of the crystal piece  10  is indicated by an alternate long and short dash line (the transmission antenna  60 , the reception antenna  69 , etc., are not illustrated). It is noted that  FIGS. 1A and 1B  illustrate an IC  200  in addition to the crystal oscillator  100 . 
     Hereinafter, a thickness direction of the crystal piece (crystal blank)  10  (vertical direction in  FIG. 1B ) is defined as the vertical direction, and the side of the casing  30  having the lid is referred to as “upper side”. However, an orientation of the installation of the crystal oscillator  100  is arbitrary. In the following, an “outer surface” refers to a surface exposed to an outside of the casing  30 , and an “inner surface” refers to a surface exposed to an inner space of the casing  30 . Further, as illustrated in  FIG. 1A , an X direction is defined as a direction corresponding to a direction of a main vibration (thickness shear vibration) direction of the crystal oscillator  100 . 
     The crystal oscillator  100  includes a crystal piece  10 , excitation electrodes  20 , a casing  30 , external electrodes  41  to  44 , a transmission antenna  60 , and a reception antenna  69 . As illustrated in  FIGS. 1A and 1B , the crystal oscillator  100  is of a surface mounting type. 
     The crystal piece  10  may be, for example, an AT-cut artificial quartz crystal substrate. An outer shape of the crystal piece  10  is arbitrary, and in the first embodiment, it is a rectangle, but other shapes may be used. Although the supporting structure of the crystal piece  10  is arbitrary. For example, the crystal piece  10  may be supported by the casing  30  in a cantilever structure. In the example illustrated in  FIGS. 1A and 1B , the crystal piece  10  is supported in a cantilever structure on a bank portion  31  of the casing  30 . When the crystal oscillator  100  is driven, the crystal piece  10  vibrates in the X direction (thickness shear vibration). 
     The excitation electrodes  20  excite the crystal piece  10 . The excitation electrodes  20  include an upper excitation electrode  21  provided on the upper surface of the crystal piece  10  and a lower excitation electrode  22  provided on the lower surface of the crystal piece  10 . The excitation electrodes  20  excite the crystal piece  10  by a potential difference between the upper excitation electrode  21  and the lower excitation electrode  22 . It is noted that the excitation electrodes  20  may be made of gold, silver, aluminum, or the like. 
     The excitation electrodes  20  are electrically connected to an IC (Integrated Circuit)  200 . The way of electrically connecting the excitation electrodes  20  and the IC  200  is arbitrary. In the example illustrated in  FIGS. 1A and 2 , the upper excitation electrode  21  is electrically connected to the IC  200  via a conductive pattern  47  (see  FIG. 2 ) formed on an upper surface of the crystal piece  10 , an electrically conductive adhesive  49 , a conductive pattern  471  formed on an inner surface of a lower part of the casing  30 , and a wire  473 . Further, the lower excitation electrode is electrically connected to the IC  200  via a conductive pattern  48  (see  FIG. 2 ) formed on a lower surface of the crystal piece  10 , an electrically conductive adhesive  49 B, a conductive pattern  481  formed on an inner surface of a lower part of the casing  30 , and a wire  483 . It is noted that the wires  473  and  483  (the same applies to a wire  493 , etc., described hereinafter) may be formed by wire bonding. It is noted that the electrically conductive adhesives  49 ,  49 B (as well as a conductive adhesive  49 A described hereinafter) may be provided at an edge portion of the crystal piece (i.e., the edge on the cantilevered side). 
     The casing  30  accommodates the crystal piece  10 . The casing  30  is made of, for example, a ceramic material. In this case, the casing  30  may be, for example, a ceramic package formed by laminating ceramic material layers. The casing  30  includes a lid  34  (see  FIG. 1B  and the like), and hermetically encloses the crystal piece  10  in an internal space (cavity) thereof. For example, the internal space of the casing  30  under vacuum or filled with dry nitrogen and sealed with the lid  34 . It is noted that the lid  34  may be a metal plate or a ceramic plate. 
     The external electrodes  41  to  44  are provided on the casing  30 . In the example illustrated in  FIGS. 1A and 1B , the external electrodes  41  to  44  are provided on an outer surface of the lower portion of the casing  30 . The external electrodes  41  to  44  may be electrically connected to the IC  200 . The way of electrically connecting the external electrodes  41  to  44  and the IC  200  is arbitrary. In the example illustrated in  FIGS. 1A and 1B , the external electrode  41  is electrically connected to the IC  200  via a conductive pattern  411  formed on the outer surface of the lower portion of the casing  30 , a via  412  formed in the casing  30 , and a wire  413 . Similarly, the external electrode is electrically connected to the IC  200  via a conductive pattern  441  formed on the outer surface of the lower portion of the casing  30 , a via  442  formed in the casing  30 , and a wire  443 . Although not illustrated, the external electrodes  42 ,  43  and the IC  200  may also be electrically connected via a conductive pattern or the like in the same manner. 
     The external electrodes  41  to  44  may be electrically connected to an external device or the like outside of the casing  30 . That is, the external electrodes  41  to  44  are electrically connected to the IC  200  and the external device to electrically connect the IC  200  to the external device or the like. In the example illustrated in  FIGS. 1A and 1B , the external electrodes  41  and  44  may be used to extract signals from an alarm output terminal  222  and a clock output terminal  220  (see  FIG. 3 ) of the IC  200 . Further, in the example illustrated in  FIGS. 1A and 1B , the external electrodes  42 ,  43  may be used for electrically connecting the IC  200  to ground and a power supply (both not illustrated) (wirings are not illustrated). 
     The transmission antenna  60  and the reception antenna  69  may be formed by a linear antenna pattern. The transmission antenna  60  transmits a radio wave corresponding to an output waveform of the crystal oscillator  100 . The reception antenna  69  receives the radio wave transmitted from the transmission antenna  60 . The transmission antenna  60  and the reception antenna  69  are electrically connected to the IC  200 , respectively. The way of electrically connecting the transmission antenna  60  and the reception antenna  69  to the IC  200  is arbitrary. The electrical connection between the transmission antenna  60  and the reception antenna  69  and the IC  200  may be implemented by, for example, wire bonding or the like. 
     In the example illustrated in  FIGS. 1A and 2 , the transmission antenna  60  and the reception antenna  69  are respectively formed on the lower surface of the crystal piece  10 . Each pattern of the transmission antenna  60  and the reception antenna  69  forms an open end at one end thereof. The other ends of the patterns of the transmission antenna  60  and the reception antenna  69  are electrically connected to the electrodes  601  and  691 , respectively. The electrode  601  is shared with the electrode related to the lower excitation electrode  22 . Accordingly, the transmission antenna  60  is electrically connected to the IC  200  via the lower excitation electrode  22 , the conductive adhesive  49 B, the conductive pattern  481 , and the wire  483 . However, the electrode  601  may be formed separately from the electrode related to the lower excitation electrode  22 . As illustrated in  FIG. 1A , the electrode  691  is electrically connected to the IC  200  via an electrically conductive adhesive  49 A, a conductive pattern  491  formed on the inner surface of the lower portion of the casing  30 , and a wire  493 . Accordingly, the reception antenna  69  is electrically connected to the IC  200  via the electrode  691 , the conductive adhesive  49 A, the conductive pattern  491 , and the wire  493 . 
     It is noted that, in the example illustrated in  FIGS. 1A and 2 , the transmission antenna  60  and the reception antenna  69  are respectively formed on the lower surface of the crystal piece  10 ; however, the transmission antenna  60  and the reception antenna  69  may be formed on the upper surface of the crystal piece  10 . 
     As described above, the IC  200  is electrically connected to the excitation electrodes  20 , the transmission antenna  60 , and the reception antenna  69  of the crystal oscillator  100 . The IC  200  forms an example of a crystal oscillator device together with the crystal oscillator  100 . In the example illustrated in  FIGS. 1A and 1B , the IC  200  is provided on an inner surface of the lower portion of the casing  30 . That is, the IC  200  is provided in the internal space of the casing  30 . However, in the modified example, the IC  200  may be provided outside the casing  30 . In this case, for example, the excitation electrodes  20 , the transmission antenna  60 , and the reception antenna  69  may be electrically connected to the external electrodes  41  to  44 , respectively, and the IC  200  may be electrically connected to the external electrodes  41  to  44 . 
     It is noted that, in the examples illustrated in  FIGS. 1A and 1B , the IC  200  may be provided with bumps (terminals) on the bottom surface thereof. In this case, the IC  200  may be electrically connected to the via  412  or the like via the bumps instead of the wire  413  or the like. 
       FIG. 3  is a diagram schematically illustrating an example of a circuit configuration of the crystal oscillator  100  and the IC  200 . In  FIG. 3 , with respect to IC  200 , capacitors of terminals, stray capacitance of wiring patterns of the printed circuit board, resistance for limiting the current (see arrow i in  FIG. 3 ) flowing through the crystal oscillator  100 , etc., are not illustrated. 
     In the example illustrated in  FIG. 3 , the upper excitation electrode  21  and the lower excitation electrode  22  of the crystal oscillator  100  are electrically connected to an input terminal  202  and an output terminal  204  of the IC  200 , respectively. However, the lower excitation electrode  22  and the upper excitation electrode  21  of the crystal oscillator  100  may be connected to the input terminal  202  and the output terminal  204  of the IC  200 , respectively. The crystal oscillator  100  cooperates with the IC  200  to generate a clock (reference clock) used in an arbitrary device (for example, a communication control device such as a base station device or a relay station device). 
     A matching capacitor  300  is electrically connected to the crystal oscillator  100 . Specifically, a first capacitor  302  is electrically connected between the upper excitation electrode  21  of the crystal oscillator  100  and ground, and a second capacitor  304  is electrically connected between the lower excitation electrode  22  of the crystal oscillator  100  and ground. The matching capacitor  300  is provided for adjustment (matching adjustment) so that the output frequency (initial value) of the crystal oscillator  100  becomes a desired value (designed value) when the total capacitance (load capacitance value) in the overall circuit of the IC  200  including the crystal oscillator  100  is added. It is noted that, in  FIG. 3 , an area surrounded by a dotted line forms an oscillation circuit. 
     As described above, the transmission antenna  60  and the reception antenna  69  are electrically connected to the IC  200 . The transmission antenna  60  is electrically connected to an arbitrary point in the oscillation circuit of the crystal oscillator  100 . In the first embodiment, as an example, as described above, the transmission antenna  60  is electrically connected between the inverting amplifier  206  and the output buffer  208  (see point B in  FIG. 3 ) in the oscillation circuit of the crystal oscillator  100 . In the example illustrated in  FIG. 3 , the transmission antenna  60  is electrically connected between the point P, which is between the lower excitation electrode  22  and the point B, and the second capacitor  304 . 
     The transmission antenna  60  transmits a radio wave corresponding to an output waveform of the crystal oscillator  100 . That is, in a state where the crystal oscillator  100  is oscillating at a certain frequency, an electric field (electric wave due to a standing wave) is generated in the transmission antenna  60  at that frequency. Specifically, when the crystal oscillator  100  is in the oscillation state, a standing wave is formed on the transmission antenna  60  based on the current i (see  FIG. 3 ) related to the output of the crystal oscillator  100 . As a result, the radio waves are transmitted (radiated) from the transmission antenna  60 . Therefore, the radio wave transmitted from the transmission antenna  60  vibrates with the amplitude corresponding to the oscillation level of the crystal oscillator  100 . The reception antenna  69  receives the radio wave transmitted from the transmission antenna  60 . Therefore, the amplitude of the reception signal of the radio wave generated by the transmission antenna  60  decreases as the oscillation level of the crystal oscillator  100  decreases (described hereinafter with reference to  FIG. 7D ). 
     It is noted that, in the examples illustrated in  FIGS. 1A to 3 , the transmission antenna  60  is electrically connected to the output side of the crystal oscillator  100  in order to increase the intensity of radio waves from the transmission antenna  60 . This is because, as described above, the signal is amplified by the inverting amplifier  206  on the output side of the crystal oscillator  100  so that the amplitude of the signal on the output side of the crystal oscillator  100  is greater than that on the instruction side. However, the transmission antenna  60  may be electrically connected to the input side of the crystal oscillator  100 . 
     The IC  200  includes an inverting amplifier  206 , an output buffer (buffer circuit)  208 , an alarm issuing circuit  250  (an example of an alarm generator), a gain control circuit  260  (an example of a gain control unit), and a reference voltage generating unit  270 . 
     As described above, the inverting amplifier  206  inverts and amplifies the output of the crystal oscillator  100  (the signal input from the upper excitation electrode  21  to the input terminal  202 ). That is, the signal input from the upper excitation electrode  21  to the input terminal  202  is inverted and amplified by the inverting amplifier  206 . The inverted and amplified signal is input to the output buffer  208  and input to the lower excitation electrode  22  via the output terminal  204 . 
     The gain (gain) of the inverting amplifier  206  is variable. It is noted that the inverting amplifier  206  may be of a type that is used for AGC (Automatic Gain Control) (for example, a type that uses a variable resistor or a field effect transistor as a variable resistance element). However, in the first embodiment, control for adjusting the gain of the inverting amplifier  206  (i.e., the automatic gain control) to always keep the output constant is not performed, as described hereinafter. That is, no automatic gain control circuit is provided. As a result, since a circuit configuration for automatic gain control becomes unnecessary, a simple configuration can be realized, and power saving can be achieved. 
     In the first embodiment, as an example, as illustrated in  FIG. 4 , the inverting amplifier  206  includes an operational amplifier OP, a resistor R 2  (an example of a first resistor), and a resistor R 3  (an example of a second resistor). The resistors R 2  and R 3  are provided in parallel on a line which is provided for returning the output of the operational amplifier OP to the inverting terminal. The inverting amplifier  206  further includes a switch SW. The switch SW has a first state in which an inverting terminal of the operational amplifier OP is electrically connected to an output terminal of the operational amplifier OP via the resistor R 2 , and a second state in which the inverting terminal of the operational amplifier OP is electrically connected to the output terminal of the operational amplifier OP via the resistor R 3 . The state of the switch SW is controlled by the gain control circuit  260 . In the first state, the relationship between the input voltage Vi and the output voltage Vo is Vo=R 2 /R 1 ×Vi, and R 2 /R 1  is the amplification factor. In the second state, the relationship between the input voltage Vi and the output voltage Vo is Vo=R 3 /R 1 ×Vi, and R 3 /R 1  is the amplification factor. For example, if R 3 &gt;R 2 , since R 3 /R 1 &gt;R 2 /R 1 , the amplification factor (that is, the gain of the inverting amplifier  206 ) becomes higher in the second state than in the first state. According to the example illustrated in  FIG. 4 , it is possible to realize the inverting amplifier  206  whose gain is variable with a simple configuration, as compared with the inverting amplifier of the type using a variable resistor or the like. 
     The output buffer  208  may be formed by a CMOS (Complementary Metal Oxide Semiconductor), for example. The output buffer  208  generates a signal (pulse signal) representing the oscillation state of the crystal oscillator  100  based on the input signal (the signal inverted and amplified by the inverting amplifier  206 ). The output buffer  208  outputs “voltage VOH” when the level of the input signal (hereinafter also referred to as “input level”) exceeds a first threshold value and outputs “voltage VOL” when the input level becomes lower than a second threshold value. It is noted that the first threshold value and the second threshold value may be set to the same or may be set differently, depending on a voltage value (threshold level) at which a P-type MOS and a N-type MOS, which form the CMOS of the output buffer  208 , are turned on/off. In this way, in the example illustrated in  FIG. 3 , the output of the crystal oscillator  100  is not directly output from the crystal oscillator  100  but is output to the clock output terminal  220  via the output buffer  208 . 
     The alarm issuing circuit  250  has a function (hereinafter referred to as “pre-output stop state detection function”) for detecting a state (hereinafter referred to as “pre-output stop state”) before the crystal oscillator  100  stops outputting. It is noted that, the fact that the crystal oscillator  100  stops outputting means that the oscillation circuit stops outputting. The fact that the crystal oscillator  100  stops outputting means the transition to the state in which the output from the output buffer  208  does not change (i.e., the state in which a normal output, which alters between “VOH” and “VOL” at the cycle corresponding to the output frequency of the crystal oscillator  100 , cannot be obtained. 
     The alarm issuing circuit  250  is electrically connected to the reception antenna  69 . The alarm issuing circuit  250  realizes the pre-output stop state detection function by monitoring the signal received by the reception antenna  69 . The alarm issuing circuit  250  generates an alarm when the amplitude of the signal received by the reception antenna  69  becomes equal to or less than a predetermined reference value β. The amplitude of the signal may be based on the difference between the maximum value and the average value of the level of the signal for the most recent predetermined period, the difference between the average value and the minimum value of the level of the signal for the latest predetermined period, half of the difference between the maximum value and the minimum value of the level of the signal for the latest predetermined period, etc. It is noted that the alarm issuing circuit  250  may use the maximum value of the level of the signal for the latest predetermined period as the amplitude. This is because, for example, the maximum value of the signal level of the most recent one cycle is correlated with the amplitude of the same signal in the same cycle. Alternatively, the alarm issuing circuit  250  may use integrated value of the amplitude values of the signal over the latest predetermined period as the amplitude. 
     The reference value β is set to a value greater than the amplitude Bm of the signal that is received by the reception antenna  69  when the amplitude of the input to the output buffer  208  becomes an input lower limit value. For example, the reference value β may be β=1.1×Bm or β&gt;1.1×Bm. The input lower limit value of the output buffer  208  corresponds to the lower limit value of the input level (magnitude of the input voltage) to the output buffer  208  when the output is obtained from the output buffer  208 . That is, even if the input to the output buffer  208  alters periodically, a significant output from the output buffer  208  (an output that can function as a clock source) cannot be obtained in a state in which the level of the input to the output buffer  208  is below a certain lower limit value and thus the CMOS is not turned on/off. The input lower limit value of the output buffer  208  corresponds to the lower limit value. It is noted that the reference value β may be uniformly set based on a design value of the input lower limit value of the output buffer  208 . Alternatively, the reference value β may be set for each individual based on measured values for individuals, corresponding to input lower limit values or the like which may differ for each individual of the output buffer  208 . In this case, for example, the reference value β may be set based on an actually measured value at the time of shipment of a product including the crystal oscillator  100  and the IC  200  (for example, an actually measured value of the amplitude Bm). 
     The alarm generated by the alarm issuing circuit  250  is output to the outside via the alarm output terminal  222  and input to the gain control circuit  260 . It is noted that the alarm output via the alarm output terminal  222  may be transmitted to, for example, an external user device (not illustrated). When the output of the crystal oscillator  100  functions as a clock of the communication control device, the user device may be, for example, a central management server that manages a base station or the like. In this case, the alarm may be a signal causing an alarm output including a voice or a display, or may include information of an index value (for example, the current value of the amplitude of the signal received by the reception antenna  69 ) representing the lowered state of the current oscillation level. Upon receipt of such an alarm output, for example, a user who is a telecommunications carrier, can plan the repair/replacement work for the communication control device that includes the crystal oscillator  100  (the crystal oscillator  100  in which the pre-output stop state was detected). 
     The gain control circuit  260  has a function of increasing the gain of the inverting amplifier  206  in synchronization with the occurrence of the alarm. That is, when an alarm from the alarm issuing circuit  250  is input, the gain control circuit  260  increases the gain of the inverting amplifier  206  from a first value to a second value. The second value is significantly greater than the first value, for example the maximum value of the variable range. This increases the amplitude of the output from the inverting amplifier  206  and increases the amplitude of the input to the output buffer  208 . In the example illustrated in  FIG. 4 , when the alarm from the alarm issuing circuit  250  is input, the gain control circuit  260  controls the switch SW to switch from the first state to the second state (see the arrow in  FIG. 4 ). As a result, the gain of the inverting amplifier  206  increases from R 2 /R 1  to R 3 /R 1 . 
     The gain control circuit  260  maintains the gain of the inverting amplifier  206  at the first value until the alarm from the alarm issuing circuit  250  is input, and when the alarm is input, the gain of the inverting amplifier  206  is set to the second value, and thereafter, the gain of the inverting amplifier  206  is maintained at the second value. In this case, the first value (R 2 /R 1 ) is smaller than the second value (R 3 /R 1 ). Accordingly, while power saving is implemented until the alarm from the alarm issuing circuit  250  is input, the state in which the gain of the inverting amplifier  206  is increased can be maintained after the alarm from the alarm issuing circuit  250  is input. 
     The reference voltage generating unit  270  generates a voltage corresponding to the reference value β, used in the alarm issuing circuit  250 . For example, the voltage generated by the reference voltage generating unit  270  may be input to a comparator (not illustrated) of the alarm issuing circuit  250 . 
     Next, with reference to  FIGS. 5 to 7D , effects of the first embodiment are described. Hereinafter, in some cases, the effects of the first embodiment will be described in comparison with a comparative example which does not include the gain control circuit  260 . 
       FIG. 5  is an explanatory diagram of characteristics in a case where the crystal oscillator  100  is a normal product. 
       FIG. 5  illustrates, on the upper side, a frequency characteristic diagram illustrating the time-varying characteristics of the output frequency of the crystal oscillator  100 , taking the time on the horizontal axis and the output frequency of the crystal oscillator  100  on the vertical axis. In the frequency characteristic diagram, a frequency standard lower limit value with respect to the output frequency of the crystal oscillator  100  is illustrated, and the time variation characteristic F 1  related to a normal product is illustrated. 
       FIG. 5  illustrates, on the lower side, an output change characteristic diagram indicating the time-varying characteristics C 1   a , C 1   b , C 1   c  of the amplitudes at each point A, B, C, respectively, taking the time on the horizontal axis and the amplitude of the signal appearing at each point A, B, C in the oscillation circuit illustrated in  FIG. 3  on the vertical axis. In the output change characteristic diagram, the input lower limit value of the output buffer  208  is also illustrated. 
     In the case of a normal product, the output frequency of the crystal oscillator  100  decreases from the value f 0  in a proportional manner with respect to the exponential increase in time, as illustrated by the time variation characteristic F 1  on the upper side of  FIG. 5  due to aging (aged deterioration). However, in the case of a normal product, the output frequency of the crystal oscillator  100  does not fall below the frequency standard lower limit value before the design life (for example, 6 years). It is noted that the main cause of the frequency change is the oxidation of the excitation electrodes  20  of the crystal oscillator  100 . The amount of the frequency change due to aging can be controlled to some extent by management of the manufacturing process or the like. If the crystal oscillator  100  is as designed, the output frequency of the crystal oscillator  100  does not fall below the frequency standard lower limit value before the design life, as illustrated in  FIG. 5 . 
     In the case of a normal product, the amplitude of the signal appearing at the point B in the oscillation circuit illustrated in  FIG. 3  decreases due to aging as indicated by the time variation characteristic C 1   b  on the lower side of  FIG. 5 . As in the case of the frequency change, the main cause of the amplitude change is the mass increase due to the oxidation of the excitation electrode  20  of the crystal oscillator  100 . However, in the case of a normal product, before the design life, the amplitude of the signal appearing at the point B illustrated in  FIG. 3  does not fall below the input lower limit value of the output buffer  208 . That is, if the crystal oscillator device is configured as designed, the amplitude of the input to the output buffer  208  does not fall below the input lower limit value before the design life. Therefore, in the case of a normal product, the amplitude of the signal appearing at the point C illustrated in  FIG. 3  does not change and is constant as indicated by the time variation characteristic C 1   c  on the lower side of  FIG. 5 . That is, in the case of a normal product, until the design life, the output (that is, normal output) switching between “VOH” and “VOL” at the cycle corresponding to the output frequency of the crystal oscillator  100  can be obtained at the point C illustrated in  FIG. 3 . 
       FIGS. 6 to 7D  are explanatory diagrams of output stoppage of the crystal oscillator  100  caused by abnormality. In  FIG. 6 , t 1  represents a time point at which the crystal oscillator  100  starts to operate, t 2  represents a time point immediately before the crystal oscillator  100  stops outputting, t 3  represents a time point when the crystal oscillator  100  stops outputting, and t 4  represents the point of design life. 
       FIG. 6  illustrates, on the upper side, a frequency characteristic diagram illustrating the time-varying characteristics of the output frequency of the crystal oscillator  100 , taking the time on the horizontal axis and the output frequency of the crystal oscillator  100  on the vertical axis. In the frequency characteristic diagram, the frequency standard lower limit value with respect to the output frequency of the crystal oscillator  100  is illustrated, and the time variation characteristic F 1  (dotted line) related to a normal product and the time variation characteristic F 2  (solid line) related to an abnormal product that stops outputting before the design life are illustrated. As an example, the time variation characteristic F 2  relating to an abnormal product indicates a case where the output stops after about 100 days from the start of operation. 
       FIG. 6  illustrates, on the lower side, an output change characteristic diagram indicating the time-varying characteristics C 2   a , C 2   b , C 2   c  (i.e., the time-varying characteristics related to an abnormal product) of the amplitudes at each point A, B, C, respectively, taking the time on the horizontal axis and the amplitude of the signal appearing at each point A, B, C in the oscillation circuit illustrated in  FIG. 3  on the vertical axis. In the output change characteristic diagram, the input lower limit value of the output buffer  208 , and the time variation characteristic C 1   c  (dotted line) related to a normal product are also illustrated. 
       FIGS. 7A to 7D  are diagrams illustrating time-series waveforms of the signal appearing in the case of an abnormal product.  FIG. 7A  illustrates the waveform of the signal appearing at point A illustrated in  FIG. 3 .  FIG. 7B  illustrates the waveform of the signal appearing at point B illustrated in  FIG. 3 .  FIG. 7C  illustrates the waveform of the signal appearing at point C illustrated in  FIG. 3 .  FIG. 7D  illustrates the waveform of the signal received by the reception antenna  69 . In  FIG. 7A  to  FIG. 7D , from the top, the waveform within a certain time period from the time point t 1 , the waveform within a certain time period before time point t 2 , and the waveform within a certain time period from time point t 3  are illustrated. In  FIG. 7B , a positive voltage value Vmin having the same magnitude as the input lower limit value and a negative voltage value Vmin having the same magnitude as the input lower limit value are also illustrated. In addition, in  FIG. 7C , the voltage level “High” to be exceeded in a positive direction by the output VOH and the voltage level “Low” to be exceeded in a negative direction by the output VOL are also illustrated. In addition, the reference value β is also illustrated in  FIG. 7D . 
     Here, there are cases where the decrease rate of the output frequency of the crystal oscillator  100  and the oscillation level become significant due to abnormality of a manufacturing process or contamination from contaminants. In such a case, an abnormal product that causes output stoppage before the design life may be generated. 
     Specifically, in the case of an abnormal product, the output frequency of the crystal oscillator  100  decreases from the initial value f 0  with decrease speed significantly higher than the decrease speed due to aging in a normal product, as illustrated in the time variation characteristic F 2  on the upper side of  FIG. 6 . In the case where the output of the crystal oscillator  100  is used as the clock of the standalone system, even if the frequency decrease progresses up to the time t 2 , there is a possibility that the frequency decrease may be permissible with a slight decrease in calculation speed. However, at time t 3 , the output suddenly stops and the whole system goes down. 
     More specifically, in the case of an abnormal product, the amplitude of the signal appearing at the point A in the oscillation circuit illustrated in  FIG. 3  decreases by a significantly greater amount than the decrease amount due to aging in the case of a normal product, as illustrated in the time variation characteristic C 2   a  on the lower side in  FIG. 6  and  FIG. 7A . Correspondingly, in the case of an abnormal product, the amplitude of the signal appearing at the point B in the oscillation circuit illustrated in  FIG. 3  decreases by a significantly greater amount than the decrease amount due to aging in the case of a normal product, as illustrated in the time variation characteristic C 2   b  on the lower side in  FIG. 6  and  FIG. 7B . Thus, in the case of an abnormal product, before the design life, the amplitude of the signal appearing at the point B illustrated in  FIG. 3  may fall below the input lower limit value of the output buffer  208 . 
     In this respect, in the case of an abnormal product illustrated in  FIG. 6 , in the comparative example, the amplitude of the signal appearing at the point B in the oscillation circuit illustrated in  FIG. 3  falls below the input lower limit value of the output buffer  208  at the time t 3 , as illustrated in the time variation characteristic C 2   b  on the lower side of  FIG. 6  and  FIG. 7B . In this way, in the case of an abnormal product illustrated in  FIG. 6 , the amplitude of the signal appearing at the point B in the oscillation circuit illustrated in  FIG. 3 , that is, the amplitude of the input to the output buffer  208  falls below the input lower limit value before the design life. If the amplitude of the input to the output buffer  208  falls below the input lower limit value of the output buffer  208 , the signal level appearing at the point C illustrated in  FIG. 3  becomes a constant value 0, as illustrated in the time variation characteristic C 2   c  on the lower side of  FIG. 6  and  FIG. 7C . That is, prior to the design life, the crystal oscillator  100  stops outputting while the crystal oscillator  100  remains in the oscillation state (see  FIG. 7A ). 
     Here, the abnormality of the crystal oscillator  100  often causes abnormal frequency change. Since the oscillation circuit including the crystal oscillator  100  itself is a clock generation source, a reference clock with higher accuracy may be required to directly detect the frequency change of the crystal oscillator  100 . Therefore, it is difficult to detect the abnormality in the frequency of the crystal oscillator  100  (for example, a characteristic like the time variation characteristic F 2  in  FIG. 6 ) by a simple method. 
     In this respect, the frequency change of the crystal oscillator  100  due to contamination from contaminants or the like correlates with the change (decrease) in the oscillation level of the crystal oscillator  100  as illustrated in  FIGS. 6 and 6 . This is because, in the case where the mass of the excitation electrodes  20  is increased due to contamination from contaminants, for example, both the output frequency and the oscillation level of the crystal oscillator  100  are reduced due to the mass increase. Therefore, even when the frequency change of the crystal oscillator  100  cannot be directly detected, it may be possible to indirectly detect the frequency change of the crystal oscillator  100  by monitoring the oscillation level of the crystal oscillator  100 . 
     On the other hand, as described above, the output of the crystal oscillator  100  is not directly output from the oscillation circuit including the crystal oscillator  100  but output through the output buffer  208 . As illustrated in  FIG. 6 , etc., as long as the amplitude of the input exceeds the input lower limit value of the output buffer  208 , the output of the output buffer  208  oscillates between the output VOH and the output VOL at the frequency that corresponds to the output frequency, even in the case of an abnormal product. The levels of the output VOH and the output VOL are substantially constant as long as the amplitude of the input exceeds the input lower limit value of the output buffer  208  even in the case of an abnormal product. Therefore, based on the output from the output buffer  208 , it is not possible to directly read the abnormality of the oscillation circuit (for example, the abnormality of the crystal oscillator  100 ). Therefore, the failure of the oscillation circuit including the crystal oscillator  100  is often recognized only when its output falls below the standard (for example, the frequency standard lower limit value) or when the output stops. It is noted that there may be often the case that the main cause of failure of the oscillation circuit resulted from the crystal oscillator  100  included therein. 
     As described above, the abnormality of the crystal oscillator  100  is often known only after the crystal oscillator  100  has stopped outputting. This means that the repair/replacement timing of the crystal oscillator  100  suddenly comes in, which is significantly inconvenient for a user of a system using an output from the oscillation circuit including the crystal oscillator  100  as a clock source. Especially, when the crystal oscillator  100  is used in a system that requires high reliability, the adverse effect when the system suddenly goes down may be significant. In addition, when the crystal oscillator  100  is used in a relay station device or the like installed in a remote mountainous area or the like, it may take time to repair or exchange it, which may increase the down time of the system. Although such a disadvantage can be avoided to some extent by providing a redundant system, providing a redundant system adds cost. 
     In this regard, according to the first embodiment, as described above, the alarm issuing circuit  250  generates the alarm when the amplitude of the signal received by the reception antenna  69  becomes equal to or less than the reference value β. As described above, the reference value β is set to a value greater than the amplitude Bm of the signal when the amplitude of the input to the output buffer  208  becomes the input lower limit value. Therefore, according to the first embodiment, the alarm can be generated by the alarm issuing circuit  250  before the amplitude of the signal appearing at the point B in the oscillation circuit illustrated in  FIG. 3  falls below the input lower limit value of the output buffer  208 . As a result, it is possible to notify the user of the system using the output from the oscillation circuit including the crystal oscillator  100  as the clock source in advance the necessity of repair/replacement due to the alarm. That is, before the crystal oscillator  100  stops outputting, the user can be notified of necessity of repair/replacement by the alarm in advance. As a result, it is possible to avoid situations where the system suddenly goes down if the user, who is notified of necessity of repair/replacement by the alarm in advance, plans appropriate repair/replacement work. 
     In addition, according to the first embodiment, as described above, the gain control circuit  260  increases the gain of the inverting amplifier  206  in synchronization with the occurrence of the alarm. When the gain of the inverting amplifier  206  is increased, the amplitude of the output from the inverting amplifier  206  (the amplitude of the input to the output buffer  208 ) increases. Therefore, according to the first embodiment, the amplitude of the input to the output buffer  208  can be increased in synchronization with the occurrence of the alarm, and as a result, the period until the crystal oscillator  100  stops outputting can be extended. That is, according to the first embodiment, even in the case of an abnormal product, the period until the crystal oscillator  100  stops outputting can be extended in response to the occurrence of the alarm. As a result, it becomes easier for the user to secure the necessary time for executing appropriate repair/replacement work. This effect is particularly useful when the crystal oscillator  100  is used for a relay station apparatus or the like installed in a remote mountainous area or the like. This is because, in such a case, it takes time for repair and exchange work in many cases. 
     Further, in the above-described first embodiment, since the output of the crystal oscillator  100  in the oscillating state can be monitored via the transmission antenna  60  and the reception antenna  69 , a monitoring system independent of the oscillation circuit can be formed. Therefore, according to the first embodiment, it is possible to monitor the output of the crystal oscillator  100  in the oscillating state in a manner that does not affect the oscillation circuit. 
       FIG. 8  is a diagram explaining an example of an operation according to the first embodiment. In  FIG. 8 , t 1  represents a time point at which the crystal oscillator  100  starts to operate, t 5  represents a detection time of the pre-output stop state, t 6  represents a time point when the crystal oscillator  100  stops outputting, and t 4  represents the point of design life. Further, in  FIG. 8 , the output stop time t 3  in the case of  FIG. 6  is illustrated for comparison.  FIG. 8  illustrates a case where the crystal oscillator  100  is not repaired or replaced until the crystal oscillator  100  stops outputting. 
       FIG. 8  illustrates, as in the case of  FIG. 6  described above, on the upper side, a frequency characteristic diagram illustrating the time-varying characteristics of the output frequency of the crystal oscillator  100 , taking the time on the horizontal axis and the output frequency of the crystal oscillator  100  on the vertical axis. In the frequency characteristic diagram, the frequency standard lower limit value with respect to the output frequency of the crystal oscillator  100  is illustrated, and the time variation characteristic F 1  (dotted line) related to a normal product and the time variation characteristic F 3  (solid line) related to an abnormal product that stops outputting before the design life are illustrated. The abnormal product in  FIG. 8  is assumed to be the same as the abnormal product in  FIG. 6 . 
       FIG. 8  illustrates, similar to  FIG. 6 , on the lower side, an output change characteristic diagram indicating the time-varying characteristics C 3   a , C 3   b , C 3   c , C 3   d  (i.e., the time-varying characteristics related to an abnormal product), taking the time on the horizontal axis and the amplitude. Time-varying characteristics C 3   d  is the time-varying characteristics of the amplitude of the signal appearing in the reception antenna  69  (the same characteristics according to an abnormal product). In the output change characteristic diagram, the input lower limit value of the output buffer  208 , the reference value β, and the time variation characteristic C 1   c  (dotted line) related to a normal product are also illustrated. 
     In the case of an abnormal product, similar to  FIG. 6 , the output frequency of the crystal oscillator  100  is significantly higher than the decrease speed due to aging in a normal product, as illustrated in the time variation characteristic F 3  on the upper side of  FIG. 8 . However, in the first embodiment, as described above, unlike  FIG. 6 , the gain control circuit  260  functions to prevent the entire system from stopping outputting and thus being down at time t 3 . That is, even in the case of an abnormal product, as illustrated in the time varying characteristic F 3  at the top of  FIG. 8 , until time t 6  after time t 3 , it is possible to delay the timing at which the entire system is down. It is noted that, in the example illustrated in  FIG. 8 , a timing when the output frequency of the crystal oscillator  100  falls below the frequency standard lower limit value is the same as a timing when the entire system is down (i.e., the timing at which the level of the signal appearing at point C becomes the constant value 0); however, this is not indispensable. However, preferably, the timing, at which the output frequency of the crystal oscillator  100  falls below the frequency standard lower limit value, does not arrive before the timing at which the entire system is down. 
     Further, in the case of an abnormal product, the amplitude of the signal appearing at the point A in the oscillation circuit illustrated in  FIG. 3  decreases by a significantly greater amount than the decrease due to aging in the case of a normal product, as illustrated in the time variation characteristic C 3   a  on the lower side in  FIG. 8 . Thus, in the case of an abnormal product, the amplitude of the signal appearing at the point B in the oscillation circuit illustrated in  FIG. 3  decreases by a significantly greater amount than the decrease due to aging in the case of a normal product, as illustrated in the time variation characteristic C 3   b  on the lower side in  FIG. 8 . Thus, in the case of an abnormal product, similar to  FIG. 6 , before the design life, the amplitude of the signal appearing at the point B illustrated in  FIG. 3  may fall below the input lower limit value of the output buffer  208 . 
     In this regard, according to the first embodiment, as schematically illustrated by an arrow at the bottom of  FIG. 8 , the alarm is generated at time t 5  at which the amplitude of the signal appearing in the reception antenna  69  is equal to or less than a reference value β. Accordingly, the gain of the inverting amplifier  206  is increased, and, as illustrated in the time varying characteristic C 3   b  at the lower side of  FIG. 8 , the amplitude (i.e., the amplitude of the input to the output buffer  208 ) of the signal appearing at point B in the oscillation circuit illustrated in  FIG. 3  increases. It is noted that, accordingly, the oscillation level of the crystal oscillator  100  is increased, the amplitude of the signal appearing at point A in the oscillation circuit illustrated in  FIG. 3  increases, as illustrated in the time varying characteristic C 3   a  at the lower side of  FIG. 8 . Thus, at time t 5 , the amplitude of the signal appearing at point B in the oscillation circuit illustrated in  FIG. 3  increases. However, because of an abnormal product, even at time t 5 , the amplitude of the signal appearing at point B in the oscillation circuit illustrated in  FIG. 3  continues to decrease by the decrease amount significantly greater than the decrease amount due to the aging of a normal product. Then, before the design life, the amplitude of the signal appearing at the point B illustrated in  FIG. 3  may fall below the input lower limit value of the output buffer  208 . In the case of an abnormal product illustrated in  FIG. 8 , the amplitude of the signal appearing at the point B in the oscillation circuit illustrated in  FIG. 3  falls below the input lower limit value of the output buffer  208  at the time t 6 , as illustrated in the time variation characteristic C 3   b  on the lower side of  FIG. 8 . In this way, in the case of an abnormal product illustrated in  FIG. 8 , the amplitude of the signal appearing at the point B in the oscillation circuit illustrated in  FIG. 3 , that is, the amplitude of the input to the output buffer  208  falls below the input lower limit value before the design life, and thus the crystal oscillator  100  transitions to the output stop state. However, in the first embodiment, as can be seen in comparison with  FIG. 6 , a timing t 6  when the crystal oscillator  100  transitions to the output stop state, comes later than the timing t 3  in  FIG. 6 . That is, in the first embodiment, even in the case of an abnormal product, as compared with the comparative example, the timing when the crystal oscillator  100  transitions to the output stop state can be delayed. In other words, in the first embodiment, as compared with the comparative example, the repair or replacement timing of the crystal oscillator  100  can be delayed by a period of time t 3  to time t 6 . It is noted that, in the example illustrated in  FIG. 8 , if the repair or replacement of the crystal oscillator  100  is performed during the period from time t 3  to time t 6 , it is possible to avoid a situation where the system ends up down suddenly at time t 6 . 
     It is noted that, in the first embodiment described above, the functions of the alarm issuing circuit  250 , the gain control circuit  260 , and the reference voltage generating unit  270  are implemented by the IC  200 ; however, at least a part of the functions may be realized by a computer. For example, the functions of the alarm issuing circuit  250  and the gain control circuit  260  may be implemented by a CPU of the computer executing a program, and the function of the reference voltage generating unit  270  may be implemented by a memory of the computer. 
     Second Embodiment 
     A crystal oscillator device according to the second embodiment differs from the crystal oscillator device according to the first embodiment described above in that the crystal oscillator  100  is replaced with a crystal oscillator  100 C. The crystal oscillator  100 C according to the second embodiment differs from the crystal oscillator  100  according to the first embodiment described above in an arrangement of the reception antenna  69 . Other elements of the crystal oscillator  100 C according to the second embodiment may be the same as those of the crystal oscillator  100  according to the first embodiment described above, and explanation thereof is omitted. 
       FIG. 9  is a diagram explaining an example of implementation of a transmission antenna  60  according to the second embodiment, and a two-side view (plan views illustrating an upper surface and a lower surface) of a crystal piece  10 . 
     As illustrated in  FIG. 9 , in the second embodiment, the reception antenna  69  is not formed on the crystal piece  10 . That is, in the second embodiment, as illustrated in  FIG. 9 , on the crystal piece  10 , the transmission antenna  60  is formed in the same manner as in the first embodiment described above. 
       FIGS. 10A to 10C  are sectional views schematically showing several exemplary implementation of the reception antenna  69 . 
     The reception antenna  69  may be disposed at any position where the reception antenna  69  can receive radio waves transmitted from the transmission antenna  60 . For example, the reception antenna  69  is formed in the lid  34  of the casing  30 , as illustrated in  FIG. 10A . In the example illustrated in  FIG. 10A , the reception antenna  69  is formed on the lower surface of the lid  34  of the casing  30 ; however, the reception antenna  69  may be formed on the upper surface of the lid  34 . Further, the reception antenna  69  may be formed on a side wall portion  35  of a cavity of the casing  30 , as illustrated in  FIG. 10B . Further, the reception antenna  69  may be disposed on the upper surface of the IC  200 , as illustrated in  FIG. 10C . Alternatively, although not illustrated, the reception antenna  69  may be formed on the inner surface of the bottom of the casing  30 . It is noted that, in  FIGS. 10A to 10C , the reception antenna  69  may be formed in any pattern as long as the reception antenna  69  can receive the radio waves transmitted from the transmission antenna  60 . 
     Also, according to the second embodiment, the same effects as in the first embodiment can be obtained. 
     It is noted that, in the second embodiment, the transmission antenna  60  is formed on the crystal piece  10 , and the reception antenna  69  is provided in a location other than the crystal piece  10 ; however, it may be reversed. That is, the reception antenna  69  may be formed on the crystal piece  10 , and the transmission antenna  60  may be provided in a location other than the crystal piece  10  in crystal oscillator  100 C. Further, the transmission antenna and reception antenna  69  may be provided in locations other than the crystal piece  10  in crystal oscillator  100 C. Further, one or both of the transmission antenna  60  and reception antenna  69 , together with IC  200 , for example, may be provided outside the casing  30  of the crystal oscillator  100 C. 
     All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiment(s) of the present inventions have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention. Further, all or part of the components of the embodiments described above can be combined.