Patent Publication Number: US-6670845-B1

Title: High D.C. voltage to low D.C. voltage circuit converter

Description:
TECHNICAL FIELD 
     The present invention generally relates to a circuit for converting high DC voltage to low DC voltage and more particularly to a semiconductor integrated circuit. 
     BACKGROUND OF THE INVENTION 
     Semiconductor integrated circuit devices are well known in the art. Typically, they are constructed in a semiconductor substrate and powered by an external DC power source. A typical externally supplied voltage is 3.3 volts. However, as the scale of integration increases and the dimensions of the critical components of the active elements within a circuit decreases due to increased shrinkage of the semiconductor integrated circuit, the voltage that can cause breakdown of the various components also decreases. Thus, these integrated circuits must be operated at a lower DC voltage. 
     Where the semiconductor integrated circuit components have shrunk such that the operating voltage is lowered to e.g. 1.8 volts, but the semiconductor integrated device must still fit in a “socket” designed to operate at 3.3 volts, a high DC voltage to low DC voltage converter circuit must be used to convert the externally supplied 3.3 volts to an internal DC voltage of 1.8 volts. Although high DC voltage to low DC voltage converters are well known in the art, they have shortcomings which are addressed by the circuit converter of the present invention. 
     SUMMARY OF THE INVENTION 
     Accordingly, in one non-limiting aspect of the present invention, a high DC voltage to low DC voltage circuit converter comprises a first NMOS transistor having a first terminal, a second terminal and a gate for controlling the flow of current between the first terminal and the second terminal. The first terminal is connected to the high DC voltage and the second terminal provides the converted low DC voltage. A resistor divider circuit has a first node, a middle node, and a second node. The first node is also connected to the high DC voltage. The middle node is connected to the gate of the first NMOS transistor. A plurality of serially connected NMOS transistors has a first end and a second end with the first end connected to the second node, and the second end connected to ground. Each of the plurality of serially connected NMOS transistors has a first terminal, a second terminal and a gate for controlling the flow of current between the first terminal and the second terminal. The first terminal of one NMOS transistor is connected to its gate and to a second terminal of an adjacent NMOS transistor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block level diagram of an integrated circuit device having the high DC voltage to low DC voltage circuit of the present invention, as well as an integrated circuit to which the generated low DC voltage is supplied. 
     FIG. 2 is a detailed circuit diagram of the preferred embodiment of the high DC voltage to low DC voltage circuit of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, there is shown a block level diagram of a semiconductor integrated circuit device  50  with the high DC voltage to low DC voltage circuit  10  of the present invention. The semiconductor integrated circuit device  50  is typically made from a semiconductor substrate having many circuit elements constructed thereon. It is connected to receive an externally supplied high DC voltage designated at Vccext. The externally supplied DC voltage Vccext is supplied to the high DC voltage to low DC voltage circuit converter  10  of the present invention, which generates a low DC voltage designated as Vccint. The low DC voltage Vccint which is the output of the circuit converter  10  of the present invention is supplied to a second circuit  30  of the integrated circuit device  50 . 
     In one typical application of the circuit converter  10  of the present invention, the integrated circuit device  50  is an SRAM memory device or an embedded SRAM memory product with logic circuit and the second circuit  30  which receives the low DC voltage Vccint is an SRAM memory cell array. The circuit converter  10  receives an externally supplied high DC voltage Vccext, such as 3.3 volts, and generates an internally supplied low DC voltage Vccint, such as 1.8 volts. Other portions of the integrated circuit device  50  will continue to receive the device  50  is made of thin oxide and thus a lower DC voltage must be used. The oxide in the memory circuit portion  30  is thinner in comparison to the oxide in the rest of the integrated circuit device  50 . 
     Referring to FIG. 2, there is shown a detailed circuit diagram of the circuit converter  10  of the present invention. The circuit converter  10  has a first NMOS transistor  12  having a first terminal, a second terminal and a gate for controlling the flow of current between the first terminal and the second terminal. The first terminal is connected to Vccext and receives the externally supplied high DC voltage. The second terminal is connected to Vccint and provides the generated low DC voltage as the output of the circuit converter  10 . 
     A resistor divider circuit comprising of a first resistor  14  and a second resistor  16  has a first end connected to Vccext and a second end connected to node  20 . The first resistor  14  and the second resistor  16  are serially connected at a middle node  22  there between. The middle node  22  is connected to the gate of the first NMOS transistor  12 . As will be shown, in the preferred embodiment the first resistor  14  and the second resistor  16  are both made in an N-well in a semiconductor p type substrate or in a semiconductor p type well. 
     A plurality of serially connected NMOS transistors designated  18   a ,  18   b ,  18   c , etc. is connected between node  20  and ground. Each of the NMOS transistors  18 ( a-c ) in the chain of serially connected NMOS transistors has a first terminal, a second terminal and a gate for controlling the flow of current between the first terminal and the second terminal. Each of the NMOS transistors  18  has its first terminal connected to its gate and connected to the second terminal of an adjacent NMOS transistor. Thus, NMOS transistor  18   c  has its first terminal connected to its gate and connected to the second terminal of the NMOS transistor  18   b . The second terminal is connected to ground. Similarly, the first terminal of the NMOS transistor  18   b  is connected to its gate and connected to the second terminal of the NMOS transistor  18   a . The first terminal of the NMOS transistor  18   a  is connected to its gate and connected to the node  20 . 
     The circuit converter  10  also comprises four capacitors designated as C 1 , C 2 , C 3  and C 4 . Each of the capacitors is an MOS capacitor made from an MOS transistor having a first terminal and a second terminal connected together as one end of the capacitor and the gate of the MOS transistor as the second end of the capacitor. In the preferred embodiment, capacitor C 1 , C 3  and C 4  are made of NMOS transistor and capacitor C 2  is made from a PMOS transistor. 
     The first capacitor C 1  has its gate connected to the node  20  and its first and second terminals connected together to ground. The second capacitor C 2  is a PMOS transistor having its first and second terminals connected together to Vccext and its gate connected to the output Vccint. The third capacitor C 3  has its first and second terminals connected together to ground and its gate connected to Vccint. The fourth capacitor C 4  is an NMOS transistor having its first and second terminals connected together to the second terminal of the NMOS transistor  18   a . The gate of the NMOS transistor forming the capacitor C 4  is connected to node  20 . 
     The operation of the circuit converter  10  is as follows: A current, designated as I C1  will flow from Vccext through first resistor  14  to node  22 , through second resistor  16  to node  20  and through the chain of serially connected NMOS transistors  18 ( a-c ) to ground. Thus, the voltage at node  22 , designated as V C1 , is determined by the current I C1 , times the resistance through the first resistor  14  and subtracted from Vccext. The voltage output of the circuit converter  10 , Vccint, is equal to V C1  minus the threshold voltage of the NMOS transistor  12 . When Vccext increases, the current I C1  will also increase. This will then cause a larger voltage drop to occur at node  22 . The result is that V C1  will not increase as much as Vccext and as a result Vccint will not increase as much when Vccext increases. Similarly, the operation of the circuit converter  10  will generate a Vccint which does not decrease as much if Vccext were to decrease. Thus, the low DC voltage produced Vccint is relatively stable. 
     The circuit converter  10  of the present invention is also able to compensate for temperature variation. If temperature increases, then V C1  at node  22  will decrease. However, when temperature increases, the threshold voltage of the MOS transistor  12  will also decrease. As a result, since the voltage at Vccint is equal to the voltage at node  22  or V C1  minus V th  of MOS transistor  12 , Vccint would increase. In order to reduce this increase, the resistance of the first and second resistors  14  and  16  are chosen such that they each have a positive temperature coefficient. Typically, the resistors are made in an N-well in the semiconductor p-type substrate or well  50 . At the same time, however, since each of the MOS transistors  18 ( a-c ) of the chain of plurality of serially connected MOS transistors is also of an NMOS type, the voltage threshold will also decrease due to the increase in temperature. In that event, the voltage at node  20  will also drop thereby dropping V C1 . The result is that Vccint is relatively stable and is immune to changes in increase in temperature. 
     Similarly, if temperature should decrease, then the threshold voltage of MOS transistor  12  will increase and Vccint will decrease. For a drop in temperature, the decrease of resistances of resistors  14  and  16  and the increase of the threshold voltage. of each of the serially connected NMOS transistors  18 ( a-c ) will cause the voltage at node  20  to increase. This again makes Vccint stable and immune to decreases in temperature. 
     The circuit converter  10  of the present invention is also advantageous in that the Vccint generated is relatively immune to processes corner irregularities. In process corner irregularities, if for example, the target for the threshold voltage of the transistor  12  is 0.6 volts, due to process variation, the V th  of MOS transistor  12  can have a range from 0.5 volts to 0.7 volts. If the threshold voltage of the MOS transistor  12  is decreased due to process variation, then Vccint will increase. However, because the MOS transistors of the serially connected chain of MOS transistors  18 ( a-c ) are also of an MOS type, V th  of those transistors will also decrease. This lowers the voltage at node  20 , which causes Vccint to decrease. As a result, Vccint is relatively immune to process variations that causes V th  to decrease. Similarly, if due to process variations V th  of MOS transistor  12  is above the target that is still within the acceptable variation, the action of Vccint decreasing due to the increase in V th  of MOS transistor  12  is offset by the voltage at node  20  increasing due to the V th  of each of the serially connected NMOS transistors  18 ( a-c ) increasing. 
     In addition, the initial voltage of Vccint can reduce the stress on the gate oxide of the MOS transistor  12 . Finally, the positive temperature coefficient of the first and second resistors  14  and  16  can be made very positive such that Vccint at high temperature is less than at low temperature, thereby reducing the semiconductor standby current at high temperature caused by junction leakage. 
     Further advantages of the circuit converter  10  occur from the use of the capacitors C 1 -C 4 . The total decoupling capacitance of the circuit converter  10  is approximately the capacitance of C 2  plus C 3 . During power up, Vccint is initially at approximately C 2 /(C 2 +C 3 )*Vccext. Thus, the capacitor C 2  relieves the oxide stress during initial application of Vccext. The capacitor C 2  is optional, in that if the difference between Vccext and Vccint is small, the stress on the oxide of MOS transistor  12  will be minimal. 
     The capacitor C 1  stabilizes the voltage at node  20 . The capacitor C 1  provides an RC time constant (where the resistance for the RC time constant is from the sum of the resistors  14  and  16 ). The capacitor C 1  decouples the ripple from Vccint to the MOS transistor  12  to the voltage at node  22 . Thus, the capacitor C 1  decouples the noise from Vccext and the noise for the voltage at node  22 . 
     The capacitor C 4  serves the same function as capacitor C 2 , in that the capacitor across the MOS transistor  18   a  serves to decouple the stress across the transistor  18   a  during power up. Finally, the capacitors C 2  and C 3  serve to decouple noise from Vccint.