Patent Publication Number: US-4319148-A

Title: High speed 3-way exclusive OR logic circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a high speed Exclusive OR logic circuit, and more particularly to a high speed 3-way Exclusive OR logic circuit with essentially a single stage logic delay. 
     2. Description of the Prior Art 
     U.S. Pat. No. 2,926,850 to R. K. Richards, issued Mar. 1, 1960 and assigned to the assignee of the present application, shows a 3-way Exclusive OR circuit as a summer portion (23-28, 32-34 of FIG. 2 of the patent) of a binary adder/subtractor. The Exclusive OR circuit disclosed comprises a combination of diode AND circuits, diode OR circuits and inverter circuits. A 3-way OR circuit is provided to produce a &#34;1&#34; output whenever one or more input operands are &#34;1&#34;. Three 2-way AND circuits, an OR-Inverter and a 2-way AND circuit are used to inhibit &#34;1&#34; output of the 3-way OR circuit whenever two or more input operands are &#34;1&#34;. A 3-way AND circuit is provided to produce &#34;1&#34; output when all of the three input operands are &#34;1&#34;. The outputs of the 3-way OR circuit and the 3-way AND circuit are ORed to provide final Exclusive OR function. Because of series combination of several logic elements, the 3-way Exclusive OR circuit disclosed includes three-stage logic delay. In addition, it needs relatively large numbers of logic elements. 
     U.S. Pat. No. 2,850,647 to H. Fleisher, issued Sept. 2, 1958 and assigned to the assignee of the present application, shows a 2-way Exclusive OR circuit. A block diagram of FIG. 5 of the patent shows that an output from a 2-way OR circuit and an output from a 2-way AND circuit are combined in an Inhibit circuit (AND plus INV) to obtain 2-way Exclusive OR function. Although this patent uses the output of the 2-way AND circuit to inhibit the output of the 2-way OR circuit when both input operands are &#34;1&#34;, it does not teach any specific manner to perform 3-way Exclusive OR function with essentially a single stage logic delay. 
     U.S. Pat. No. 3,649,844 to F. K. Kroos, issued Mar. 14, 1972 and assigned to Siemens AG, shows a 3-way Exclusive OR circuit. It uses four current switches constructed in accordance with two-level current switch tree configuration. Because of this configuration, the 3-way Exclusive OR circuit disclosed requires a level shifter for one of the input operands, and a higher voltage supply than is usually required for one-level current switch circuit. 
     U.S. Pat. No. 4,041,326 to B. J. Robinson, issued Aug. 9, 1977 and assigned to FCI Corp., shows a 3-way Exclusive OR circuit implemented by current switches. This circuit, however, requires both true and complement input operands for each of the three input operands. This means that one-stage logic delay is additionally included to produce complement forms of input operands. In addition, the circuit disclosed uses a three-level current switch tree which requires higher voltage supply and two levels of logic level shifters. 
     U.S. Pat. No. 2,927,733 to C. M. Campbell, Jr., issued Mar. 8, 1960 and assigned to Burroughs Corp., shows a 3-way Exclusive OR which comprises a combination of NPN transistor current switches and PNP transistor current switches. Since the PNP transistor current switches are included, the operation speed of the circuit is slow because the PNP transistor circuit is normally two to three times as slow as the NPN circuit. In addition, time-consuming and complicated process is needed to construct the PNP-NPN transistor circuit on a single chip. 
     IBM Technical Disclosure Bulletin by J. E. Gersbach, entitled &#34;FOUR-WAY EXCLUSIVE-OR&#34;, Vol. 11, No. 9, February 1969, pages 1162-1163 shows a 4-way Exclusive OR circuit which uses a two-level current switch tree. In addition, this circuit requires true form of input operands for two operands and complement form of input operands for two other operands. 
     IBM Technical Disclosure Bulletin by J. E. Gersbach entitled &#34;CASCODE EXCLUSIVE OR&#34;, Vol. 19, No. 6, November 1976, pages 2010-2011, shows a 5-way Exclusive OR circuit implemented by a five-level cascode current switch tree which requires a high voltage supply and several level shifters. 
     IBM Technical Disclosure Bulletin by F. H. Lohrey et al entitled &#34;GATED EXCLUSIVE OR CIRCUIT&#34;, Vol. 19, No. 6, November 1976, page 2080, shows an Exclusive OR circuit which performs a logical function of (A·B·C·D) V (E·F·G·H). It shows a circuit structure constructed in accordance with a Schottky diode-transistor logic to perform the above logic function. 
     None of the prior art teaches a 3-way Exclusive OR logic circuit which includes essentially single stage logic delay, does not require a multi-level current switch tree and hence does not require a high voltage supply, and does not require both true and complement input operands. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a high speed 3-way Exclusive OR circuit with essentially a single stage logic delay. 
     It is another object of the present invention to provide a high speed 3-way Exclusive OR circuit which operates with a low voltage supply. 
     It is another object of the present invention to provide a high speed 3-way Exclusive OR circuit which can be readily implemented on an IC chip. 
     It is a further object of the present invention to provide a high speed 3-way Exclusive OR circuit which can be implemented using commonly available semiconductor circuits and processes. 
     In accordance with the present invention, a 3-way OR circuit is provided to produce a &#34;1&#34; output whenever one or more of three input operands are &#34;1&#34;. A TWO AND ONLY TWO logic circuit is provided to detect when two and only two of three input operands are &#34;1&#34;.  Output of this TWO AND ONLY TWO logic circuit is used to inhibit the &#34;1&#34; output of the 3-way OR circuit when two and only two of the input operands are &#34;1&#34;. As a result, the inhibit circuit produces &#34;1&#34; output only when one or three of the input operands are &#34;1&#34;, which is a desired Exclusive OR function. 
     One of the significant features of the present invention is that an entire circuit is constructed in such a manner that only a single stage logic delay is included from a circuit input to a circuit output. 
     In one preferred form of the invention, the TWO AND ONLY TWO logic circuit is implemented by three Schottky diode-transistor logic circuits, which are high speed in nature, while in another preferred form of the invention it is implemented by three current switch circuits, which are also high speed in nature. Since no multi-level cascode tree of the current switches is included, the circuit operates with a low voltage power supply. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a block diagram of a 3-way Exclusive OR circuit constructed in accordance with a principle of the present invention. 
     FIG. 2 shows a detailed block diagram of the 3-way Exclusive OR circuit shown in FIG. 1. 
     FIG. 3 shows a circuit diagram of one preferred embodiment of the 3-way Exclusive OR circuit of the present invention. 
     FIG. 4 shows a circuit diagram of another preferred embodiment of the 3-way Exclusive OR circuit of the present invention. 
     FIG. 5 shows a block diagram of a 9-way Exclusive OR circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     As is old in the art, a 3-way Exclusive OR circuit performs a logical function of A V B V C=A·B·C+A·B·C+A·B·C+A·B·C, where A, B and C are input operands in true form and A, B and C are input operands in complement form. The above Exclusive OR function may be illustrated using binary notations. 
     
                       TABLE 1                                                     
______________________________________                                    
Combination   A     B         C   OUT                                     
______________________________________                                    
1             0     0         0   0                                       
2             1     0         0   1                                       
3             0     1         0   1                                       
4             0     0         1   1                                       
5             1     1         0   0                                       
6             0     1         1   0                                       
7             1     0         1   0                                       
8             1     1         1   1                                       
______________________________________                                    
 
    
     There are eight different combinations of three input operands A, B and C. In a proper Exclusive OR operation, only the combinations 2, 3, 4 and 8 should produce &#34;1&#34; outputs. The principle of the present invention is ORing the three input operands to produce &#34;1&#34; outputs for any of the combinations 2 through 8 and inhibiting those &#34;1&#34; outputs only when two and only two input operands are &#34;1&#34;, that is, only for the combinations 5, 6 and 7. 
     Referring to FIG. 1, the above principle of operation is implemented by a combination of a 3-way OR circuit 10, a TWO AND ONLY TWO logic circuit 20 and a 2-way AND circuit 30. The OR circuit 10 produces &#34;1&#34; outputs for the input operand combinations 2, 3, 4, 5, 6, 7 and 8 of the Table 1 above. The TWO AND ONLY TWO &#34;1&#34;&#39;s circuit produces &#34;1&#34; output for the combinations 5, 6 and 7. By applying the output of the OR circuit 10 to one input of the AND circuit 30 while applying the output of the TWO AND ONLY TWO logic circuit 20 to an inhibit input of the AND circuit 30, the &#34;1&#34; outputs from the OR circuits 10 are inhibited only when two of the input operands A, B and C are &#34;1&#34;, that is, for the combinations 5, 6 and 7. As a result, final outputs from the AND circuit 30 represent the Exclusive OR function of the three input operands A, B and C. 
     FIG. 2 shows a detailed block diagram of the circuit of FIG. 1. In FIG. 2, the TWO AND ONLY TWO logic circuit 20 of FIG. 1 has been replaced by a circuit 20A which comprises three 3-way NAND circuits 22, 24 and 26 each having one inhibit input connected to a different one of the three input operands A, B and C. The outputs of the NAND circuits 22, 24 and 26 and the output from the OR circuit 10 are DOT-ANDed at a DOT-AND circuit 30A. The combination of the circuits 20A and 30A is functionally equivalent to the combination of the circuits 20 and 30 in FIG. 1. The operation of the circuit of FIG. 2 is outlined below. The NAND circuit 22 receives the operand A at the inhibit input terminal and receives the operands B and C at normal input terminals. Thus, the NAND circuit 22 produces &#34;0&#34; output only when (A, B, C)=(0, 1, 1) which corresponds to the combination 6 in Table 1. Similarly, the NAND circuits 24 and 26 produce &#34;0&#34; outputs only when (A, B, C)=(1, 0, 1) (corresponding to the combination 7 in Table 1) and (A, B, C)=(1, 1, 0) (corresponding to the combination 5 in Table 1), respectively. Those three &#34;0&#34; outputs from the NAND circuits 22, 24 and 26 together with the DOT-AND circuit 30A are effective to inhibit the &#34;1&#34; outputs from the OR circuit 10 so that the DOT-AND circuit 30A produces &#34;1&#34; output only for the combinations 2, 3, 4 and 8. 
     A novel and important aspect of the present invention resides in a specific manner in which each of the logic blocks shown in FIG. 2 is implemented by a semiconductor circuit such that total circuit delay does not exceed one stage logic delay. 
     Referring to FIG. 3, there is shown one preferred embodiment of the present invention in accordance with the principle of operation described with reference to FIGS. 1 and 2. The same reference numerals as those in FIGS. 1 and 2 are used to indicate the like logic block. The OR circuit 10 comprises four transistors Q4, Q5, Q6 and Q7 having their emitters commonly connected to a constant current source J1. The base of the transistor Q4 is connected to a reference potential which is ground potential in the illustrated embodiment, while bases of the transistors Q5, Q6 and Q7 are connected to operand input terminals A, B and C, respectively. Collectors of the transistor Q5, Q6 and Q7 are connected in common to a voltage source Vcc while the collector of the transistor Q4 is connected to a load resistor R4, the other end of which is connected to the voltage source Vcc. Thus, the transistors Q4-Q7 function as a well-known OR circuit such that whenever one or more of the three input operands A, B and C are UP or &#34;1&#34; the transistor Q4 is nonconductive and the collector potential of the transistor Q4 is UP or &#34;1&#34;. This UP or &#34;1&#34; signal at the collector of Q4 is conveyed to a base of an emitter follower transistor Q8 which acts as the AND circuit 30 shown in FIG. 2, as will be explained hereinafter. 
     The NAND circuits 22, 24 and 26 shown in FIG. 2 are implemented in the illustrated embodiment by diode-transistor logic, preferably Schottky diode-transistor logic. The NAND circuit 22 comprises a transistor Q1, two Schottky diodes SD1 and SD2 and a resistor R1, the NAND circuit 24 comprises a transistor Q2, two Schottky diodes SD3 and SD4 and a resistor R2, and the NAND circuit 26 comprises a transistor Q3, two Schottky diodes SD5 and SD6 and a resistor R3. For the NAND circuit 22, the emitter of the transistor Q1 is connected to the operand A input terminal and cathodes of the diodes SD1 and SD2 are connected to operand C and B input terminals. Anodes of the diodes SD1 and SD2 are connected in common to the base of the transistor Q1 and to one terminal of the resistor R1, the other terminal of which is connected to a voltage source. The NAND circuits 24 and 26 are constructed similarly except that the connections to the operand input terminals are different. Collectors of the three transistors Q1, Q2 and Q3 are connected in common with the collector of the transistor Q4 to provide a DOT-AND function. A Schottky diode SD7 is used to limit the UP level of the bases of the transistors Q1-Q3. A separate locally generated bias source may be used instead. 
     The operation of the circuit of FIG. 3 is now explained. As described before, the circuit 10 is a conventional current switch OR circuit. Assuming that the NAND circuits 22, 24 and 26 were not provided, an UP level or &#34;1&#34; output is produced at the emitter of the transistor Q8 whenever one, two or all of the three input operands A, B and C are UP or &#34;1&#34;. The function of the circuits 22, 24 and 26 is to inhibit the &#34;1&#34; output from appearing at the emitter of Q8 if and only if two of the three input operands A, B and C are UP or &#34;1&#34;. The NAND circuit 22 produces DOWN or &#34;0&#34; output at the collector of the transistor Q1 if and only if (A, B, C)=(DOWN, UP, UP) or (0, 1, 1). That is, the transistor Q1 conducts only when A is DOWN and B and C are UP. In other cases, for example, when A and C are DOWN and B is UP, Q1 does not conduct because the diode SD1 draws current to drop the base potential of the transistor Q1. Thus, circuit 22 performs a logical function of A·B·C. Similarly, the circuits 24 produces DOWN or &#34;0&#34; output if and only if (A, B, C)=(1, 1, 0). In other words, the circuits 24 and 26 perform logical functions of A·B·C and A·B·C, respectively. 
     The A·B·C, A·B·C and A B C outputs from the circuits 22, 24 and 26, respectively, and the (A+B+C) output from the circuit 10 are DOT-ANDed at the input of the circuit 30 so that the output from the circuit 30 represents A·B·C+A·B·C+A·B·C+A.multidot.B⃡C. 
     It should be noted that the circuit of FIG. 3 is constructed by Schottky diode-transistor logic circuits, a current switch circuit and an emitter follower circuit, all of which are high speed in nature. Since the inhibit action of the output for two &#34;1&#34;&#39;s happens in parallel or simultaneously rather than sequentially, the delay included is only single stage logic delay. That is, the combination of circuits 22, 24, 26 and 30A includes one stage logic delay and the combination of circuits 10 and 30A includes one stage logic delay. Since those combinations function in parallel, the total delay included is one stage logic delay. It should also be noted that only one form of input operands A, B, C is required to perform the 3-way Exclusive OR. This is a great advantage because additional logic delay would be involved if the circuit would require both true and complement forms of input operands. In addition, since the illustrated circuit includes no multi-level current circuit tree, it operates with a low voltage supply. By way of non-limiting example, the circuit operates satisfactorily with Vcc=+1.4 volts, Vee=- 2.2 volts and Vt=-0.7 volts. 
     FIG. 4 shows another preferred embodiment of the present invention. In FIG. 4, the same symbols and reference numerals as those in FIG. 3 are used to represent the same or like elements. In the embodiment of FIG. 4, the Schottky diodes have now been eliminated by the introduction of three current switches as shown. More specifically, a NAND circuit 22A comprises transistors Q1, Q9, Q10, Q11 and Q12, a resistor R1A and a current source J2. The transistors Q9 to Q12 are connected to form a current switch with the base of Q9 being connected to the operand A input terminal and bases of Q10 to Q12 being connected to a reference potential, ground potential in the illustrated embodiment. The collector of the transistor Q9 is connected to the voltage source Vcc, the collector of the transistor Q10 is connected in series with the transistor Q1, the collector of the transistor Q11 is connected to the base of the transistor Q2, and the collector of the transistor Q12 is connected to the base of the transistor Q3. The base of the transistor Q1 is connected to one terminal of the resistor R1A and the collector of the transistor Q1 is connected in common with the collectors of the transistors Q2, Q3 and Q4 as is the case of FIG. 3. The NAND circuits 24A and 26A which include transistors Q2, Q13 to Q16 and Q3, Q17 to Q20, respectively, are constructed in the same manner as the NAND circuit 22A except that they receive different input operands. The OR circuit 10 and the DOT-AND circuit 30A are identical to those of FIG. 3 and hence no additional explanation will be required. 
     The circuit of FIG. 4 operates under the same operation principle as that of FIG. 3. Again, the circuits 22A, 24A and 26A function to inhibit the &#34;1&#34; outputs from the OR circuit 10 from appearing at the output of the circuit 30 when two and only two operands are &#34;1&#34;. Now, assuming that (A, B, C)=(0, 1, 1), the current switch transistors Q10, Q11, Q12, Q13, Q17 are ON and Q9, Q14, Q15, Q16, Q18, Q19 Q20 are OFF. Since Q14 and Q18 are OFF, the transistors Q2 and Q3 do not draw current. The base of the transistor Q1 is sufficiently high because the transistors Q15 and Q19 are OFF. As a result, the transistor Q1 draws a current resulting in a DOWN level at the collector thereof. Similarly, when (A, B, C)=(1, 0, 1) or (1, 1, 0) the transistors Q2 or Q3, respectively, draws a current. On the other hand, if none, only one or all of the three input operands are &#34;1⃡, none of the transistors Q1, Q2 and Q3 draws current. For example, if (A, B, C)=(0, 0, 1), the transistors Q9 and Q13 are OFF and the transistor Q17 is ON. Since the transistor Q15 is ON at this time, the potential at the base of the transistor Q1 is not high enough to render the transistor Q1 to draw sufficient current. Similarly, the potential at the base of the transistor Q2 is not high enough to render the transistor Q2 to draw sufficient current because the transistor Q11 is ON. The Transistor Q3 does not draw a current because the transistor Q18 is OFF. Thus, none of the transistors Q1, Q2 and Q3 draws sufficient current and the potential at the collectors of Q1, Q2 and Q3 remains at UP level. If (A, B, C)=(1, 1, 1), the transistors Q10, Q14 and Q18 are OFF and hence none of the transistors Q1, Q2 and Q3 can draw current. If (A, B, C)=(0, 0, 0), the transistors Q9, Q13 and Q17 are OFF and the transistors Q10-Q12, Q14-Q16, Q18-Q20 are ON. However, the transistor Q1 does not draw sufficient current because the potential at the base of Q1 is low since the transistors Q15 and Q19 are ON. Similarly, the transistors Q2 and Q3 do not draw sufficient current because their base potentials are low. In this case, however, the transistor Q4 of the OR circuit 10 is ON resulting in DOWN level at the junction of the collectors of the transistors Q1-Q4. 
     While the circuits of FIGS. 3 and 4 have been specifically shown and described using the NPN transistors, it should be understood that PNP transistors can be equally used with appropriate change of polarities of various voltage sources and diodes. In the PNP transistor versions, however, a negative logic rather than a positive logic is used. 
     Although not specifically shown in FIG. 4 for clarity, load resistors can obviously be connected from Vcc to the collectors of transistors Q10-Q12, Q14-Q16 and Q18-Q20. Furthermore, antisaturation clamps can also be used across the base-collector junctions of these transistors (Q10-Q12, Q14-Q16 and Q18-Q20) to prevent delays due to saturation. Alternately, the anodes of such clamps can be connected to external dc bias sources, instead of to the bases of the transistors. Since these antisaturation and speed enhancement techniques are well known, no further explanation is necessary here. 
     FIG. 5 shows in block form how the 3-way Exclusive OR circuits 50, 60, 70 and 80 of the present invention are assembled to form a 9-way Exclusive OR circuit. By using the 3-way Exclusive OR circuits of the present invention, a total delay included in the 9-way Exclusive OR is only two-stage logic delay. Such a 9-way Exclusive OR circuit may be advantageously used to generate an odd parity for 9-bit block. 
     While the invention has been described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the above and other changes may be made therein without departing from the spirit and scope of the invention.