Patent Publication Number: US-10784822-B2

Title: High power radio frequency amplifiers and methods of manufacture thereof

Description:
PRIORITY CLAIM 
     This application is a continuation-in-part of and claims priority to U.S. patent application Ser. No. 16/226,012, filed Dec. 19, 2018, which is hereby incorporated by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     Embodiments of the subject matter described herein relate generally to radio frequency (RF) amplifiers, and more particularly to broadband power transistor devices and amplifiers, and methods of manufacturing such devices and amplifiers. 
     BACKGROUND 
     Many systems employ power amplifiers for increasing the power of radio frequency (RF) signals. For example, in both radar and wireless communication systems high power RF amplifiers may form a portion of the last amplification stage in a transmission chain before provision of the amplified signal to an antenna for radiation over the air interface. High bandwidth, high gain, high linearity, stability, and a high level of power-added efficiency can be characteristics of a desirable high power RF amplifier in such systems. 
     In the past, high-power radio frequency amplifiers have commonly used silicon-based devices (e.g., laterally diffused metal oxide semiconductor (LDMOS). However, such silicon-based devices exhibit relatively low efficiencies and power densities when compared with the efficiencies and power densities of gallium nitride (GaN)-based power amplifier devices. Accordingly, GaN-based power amplifier devices have been increasingly considered for high power broadband applications. However, there are challenges to using GaN technology to achieve broadband power amplification (e.g., over 20 percent fractional bandwidth). 
     Thus, there remains a continuing need for improved amplifiers that can provide high power output at high frequencies and over a wide frequency bandwidth. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete understanding of the subject matter may be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures. 
         FIG. 1  is a schematic diagram of an class F amplifier device in accordance with an exemplary embodiment; 
         FIG. 2  is a graphical representation of a voltage waveform and current waveform in an exemplary class F amplifier; 
         FIGS. 3-5  are circuit diagrams of class F amplifiers in accordance with various exemplary embodiments; 
         FIG. 6  is a circuit diagrams of a baseband decoupling circuit in accordance with various exemplary embodiments; 
         FIG. 7  is a schematic view of a class F RF power amplifier device that includes multiple parallel amplification paths in accordance with an example embodiment; 
         FIG. 8  is a top view of a portion of packaged class F RF power amplifier device in accordance with an example embodiment; 
         FIG. 9  is a cross-sectional side view of a portion of packaged class F RF power amplifier device in accordance with an example; 
         FIG. 10  is a flowchart of a method for fabricating a packaged class F RF power amplifier device in accordance with an example embodiment; 
         FIG. 11  is a schematic diagram of an inverse class F amplifier device in accordance with an exemplary embodiment; 
         FIG. 12  is a graphical representation of a voltage waveform and current waveform in an exemplary inverse class F amplifier; 
         FIGS. 13-15  are circuit diagrams of inverse class F amplifiers in accordance with various exemplary embodiments; 
         FIG. 16  is a circuit diagrams of a baseband decoupling circuit in accordance with various exemplary embodiments; 
         FIG. 17  is a schematic view of an inverse class F RF power amplifier device that includes multiple parallel amplification paths in accordance with an example embodiment; 
         FIG. 18  is a top view of a portion of packaged inverse class F RF power amplifier device in accordance with an example embodiment; 
         FIG. 19  is a cross-sectional side view of a portion of packaged inverse class F RF power amplifier device in accordance with an example; and 
         FIG. 20  is a flowchart of a method for fabricating a packaged inverse class F RF power amplifier device in accordance with an example embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments described herein provide radio frequency (RF) amplifiers, and in some embodiments provide RF amplifiers that can be used in high power RF applications. The amplifiers described herein may be implemented to include one or more matching networks and one or more transistor encased together inside a device package. Specifically, the amplifiers can be implemented with at least one transistor and an output matching network packaged together, where the output matching network includes a plurality of resonant circuits configured to facilitate efficient amplifier operation at high frequencies and over wide bandwidths. For example, the plurality of resonant circuits in the output matching network can be implemented to facilitate class F or inverse class F amplifier operation. Additionally, the plurality of resonant circuits can also be implemented with other circuit elements to provide output impedance transformation in a way that facilitates efficient high power amplifier operation. 
     The plurality of resonant circuits in the output matching network can include inductive and capacitive elements that are implemented with bondwires and integrated passive devices (IPDs). In some such embodiments, the resonant circuits of the matching network can be fully implemented inside the package, and as such may provide the amplifier with high power, high frequency and/or wide bandwidth performance. Furthermore, in some embodiments these RF amplifier devices can be implemented with gallium nitride (GaN)-based transistors that can provide high efficiency and high power density. As such, the embodiments described herein can overcome the challenges to using GaN technology to achieve broadband power amplification (e.g., over 20 percent fractional bandwidth). 
     The embodiments described herein provide both class F amplifiers, inverse class F amplifiers, and methods of operation. So implemented, the class F and inverse class F amplifiers can be used to provide high efficiency amplification for a variety of applications, including radio frequency (RF) applications. A class F implementation will now be described with reference to  FIGS. 1-10 . An inverse class F implementation will then be described with reference to  FIGS. 11-20 . 
     Turning now to  FIG. 1 , an exemplary class F amplifier  100  is illustrated schematically. In this embodiment, the amplifier  100  includes a first transistor  102 , a first input matching network  103 , a first output matching network  104 , and a package  111  that includes a first input lead  112  and a first output lead  114 . During operation, the amplifier  100  receives an input signal at a first input lead  112 , and outputs an amplified signal through the output matching network  104  and the first output lead  114 . The output amplified signal has signal energy at a fundamental frequency (f 0 ) and additional signal energy at multiple harmonic frequencies, including a second harmonic frequency of twice the fundamental frequency (2f 0 ) and a third harmonic frequency of three times the fundamental frequency (3f 0 ). 
     In accordance with the embodiments described herein, the output matching network  104  includes three resonant circuits: a first 2f 0  resonant circuit  106 , a first 3f 0  resonant circuit  108 , and a second 3f 0  resonant circuit  110 . In general, the first 2f 0  resonant circuit  106  is configured to resonate at a second harmonic frequency (2f 0 ), and the first 3f 0  resonant circuit  108  and the second 3f 0  resonant circuit  110  are configured to resonate at a third harmonic frequency (3f 0 ). As will be described below, these three resonant circuits ( 106 ,  108  and  110 ) facilitate the operation of the amplifier  100  as an effective, high efficiency, class F amplifier. 
     As also will be described in greater detail below, the three resonant circuits ( 106 ,  108  and  110 ) in the output matching network  104  include inductive elements and capacitive elements. The various inductive elements may be implemented with IPDs and/or bondwires inside the device package  111 . Likewise, the various capacitive elements may be implemented with IPDs inside the device package  111 , and/or with discrete capacitors. Implementing the output matching network  104  with such components inside the device package  111  may facilitate improved high frequency performance in the amplifier  100 , particularly in high power applications. 
     In typical implementations the transistor  102  is formed on a transistor die, and that transistor die typically includes a first input terminal (e.g., a gate control terminal), a first output terminal (e.g., a first current conducting terminal, such as a drain terminal), and a second output terminal (e.g., a second current conducting terminal, such as a source terminal) that are used to connect to the transistor  102 . In one specific embodiment, the transistor  102  comprises a gallium nitride (GaN) field-effect transistor (FET), but other transistor types can also be used. As more specific examples, various III-V field effect transistors may be used (e.g., a high electron mobility transistor (HEMT)), such as a GaN FET (or another type of III-V transistor, including a gallium arsenide (GaAs) FET, a gallium phosphide (GaP) FET, an indium phosphide (InP) FET, or an indium antimonide (InSb) FET). In other examples the transistor  102  may be implemented with a III-V FET or with a silicon-based FET (e.g., a laterally-diffused metal oxide semiconductor (LDMOS) FET). 
     In general, class F amplifiers generate specific defined output voltage and current waveforms. These output waveforms minimize power consumption by reducing the portions of each cycle where current and voltage overlap. Turning to  FIG. 2 , a graph  200  illustrates an idealized output voltage and graph  250  illustrates an idealized output current for an exemplary class F amplifier (e.g., amplifier  100 ). As can be seen in  FIG. 2 , the output voltage is a square wave that is non-zero over the first half of the output cycle, and the output current is a half-sinusoid that is non-zero only over the second half of the output signal. When so implemented with substantially non-overlapping voltage and current output waveforms, power consumption is reduced, and a high efficiency class F amplifier is provided. 
     To generate such voltage and current waveforms and provide class F amplifier operation, the impedance presented at a transistor (e.g., transistor  102 ), as referenced to the current source in the transistor, should exhibit high impedance to frequencies at the odd harmonic frequencies and low impedance to frequencies at even harmonic frequencies. In particular, providing low impedance for signal energy at the second harmonic frequency is of particular importance, with diminishing importance for higher order even harmonic frequencies. Likewise, providing high impedance for signal energy at the third harmonic frequency is of particular importance, with diminishing importance for higher order odd harmonic frequencies. Thus for many applications, providing a low impedance (e.g., short circuit) for signal energy at the second harmonic frequency (2f 0 ) and providing a high impedance (e.g., open circuit) for signal energy at the third harmonic frequency (3f 0 ) can be sufficient to provide effective class F amplifier performance. 
     Returning to  FIG. 1 , the amplifier  100  is configured to provide high efficiency, class F operation through the use of the three resonant circuits ( 106 ,  108  and  110 ) in the output matching network  104 . In general, the first 2f 0  resonant circuit  106  is configured to resonate at a second harmonic frequency (2f 0 ), and the first 3f 0  resonant circuit  108  and the second 3f 0  resonant circuit  110  are configured to resonate at a third harmonic frequency (3f 0 ). Specifically, the first 2f 0  resonant circuit  106  is configured to resonate at a second harmonic frequency (2f 0 ) and create a short circuit between the first output terminal and a ground for signal energy at the second harmonic frequency (2f 0 ). Likewise, the first 3f 0  resonant circuit  108  is configured to resonate at a third harmonic frequency (3f 0 ) and create a short circuit between the first output lead  114  and the ground for signal energy at the third harmonic frequency (3f 0 ). Finally, the second 3f 0  resonant circuit  110  is configured to resonate at the third harmonic frequency (3f 0 ) and create an open circuit between the first output terminal and the first output lead  114  for signal energy at the third harmonic frequency (3f 0 ). 
     Again, the first 3f 0  resonant circuit  108  is configured create a short circuit between the first output lead  114  and the ground for signal energy at the third harmonic frequency (3f 0 ). It should be noted that this configuration is not typically found in a class F implementation, as class F amplifiers need high impedance (e.g., open circuit) at the output for signal energy at the third harmonic frequency (3f 0 ). However, in the embodiments described herein, the short circuit created by the first 3f 0  resonant circuit  108  allows the second 3f 0  resonant circuit  110  to be realized. Specifically, the second 3f 0  resonant circuit  110  is only realized when the first 3f 0  resonant circuit  108  resonates and generates a short circuit. Thus, the second 3f 0  resonant circuit  110  is not in a form that will resonate at the third harmonic frequency (3f 0 ) without the simultaneous resonating of the first 3f 0  resonant circuit  108 . Stated another way, the second 3f 0  resonant circuit  110  is dependent upon the resonating of the first 3f 0  resonant circuit  108 . Furthermore, when the second 3f 0  resonant circuit  110  resonates it creates a high impedance or open circuit. Thus, when the first 3f 0  resonant circuit  108  resonates, the second 3f 0  resonant circuit  110  is realized and when also resonating creates the needed high impedance (e.g., open circuit) for signal energy at the third harmonic frequency (3f 0 ). 
     In one specific embodiment, the second 3f 0  resonant circuit  110  is implemented in part with an inductance provided by a first bondwire array that is connected between a first output terminal of the transistor  102  and the first output lead  114 . In such an embodiment, the first bondwire array provides the high power RF signal transmission path between the transistor  102  and the first output lead. As such, the first bondwire array is typically a relatively large bondwire array that can create a relatively large inductance. 
     Likewise, in one specific embodiment the first 3f 0  resonant circuit  108  is implemented in part with an inductance provided by a second bondwire array that is connected between the first output lead and an IPD die. In such an embodiment the first 3f 0  resonant circuit  108  is effectively implemented on the output lead side of the device, with the inductance provided by second bondwire array in a bond-back configuration from the output lead  114  to the IPD die. Implementing the first 3f 0  resonant circuit  108  with the second bondwire array in a bond-back configuration, and implementing the second 3f 0  resonant circuit  110  to include the first bondwire array providing the main connection between transistor  102  and the output lead  114  can provide distinct performance advantages. For example, such a configuration can facilitate class F operation using only bondwires as the inductive elements of the output matching network  104  rather than using additional integrated or discrete inductors. Using only bondwires to provide the inductances can minimize the overall amount of losses in the amplifier  100 . Furthermore, such a configuration can provide a high impedance (e.g., open circuit) for signal energy at the third harmonic frequency (3f 0 ) at transistor output terminal, no matter what impedance is presented outside of the package. 
     In one embodiment that will be described in greater detail below, the second 3f 0  resonant circuit  110  is implemented to include a first capacitance provided by the intrinsic output capacitance of the transistor  102 , a first inductance provided by a first bondwire array, and the components of the first 2f 0  resonant circuit. It should be noted that in such an embodiment the inclusion of the intrinsic output capacitance in the second 3f 0  resonant circuit  110  can at least partially compensate for the generally adverse effects of that capacitance. 
     Specifically, the intrinsic output capacitance of a typical transistor (e.g., transistor  102 ) can allow a capacitive reactance path to ground for high frequency signal energy, including signal energy at the third harmonic frequency (3f 0 ). Such a capacitive reactance path would, if left uncompensated, provide a low impedance path for signal energy at third harmonic frequencies, and thus would prevent efficient class F operation. The embodiments described herein can overcome this by incorporating the intrinsic output capacitance into a second 3f 0  resonant circuit in a way that eliminates the low impedance path that would otherwise exist for signal energy at the third harmonic frequency (3f 0 ). 
     In one embodiment, the output matching network  104  is implemented with a second bondwire array, the second bondwire array connected to the first output lead and a first capacitive element. In this embodiment, the second bondwire array provides a second inductance, the first capacitive element provides a second capacitance, and the first 3f 0  resonant circuit includes the second inductance and the second capacitance. As one specific example, the second bondwire array can be arranged in bond-back configuration, connecting from the first output lead back to an IPD die inside the package  111 . 
     In yet another embodiment, the output matching network  104  is further implemented with a third bondwire array, the third bondwire array connected to the first output terminal and a second capacitive element. In this embodiment the third bondwire array provides a third inductance, the second capacitive element provides a third capacitance, and the first 2f 0  resonant circuit includes the third inductance and the third capacitance. In such embodiments both the second capacitive element and the third capacitive element can comprise IPDs formed on an IPD die. As one specific example, these capacitive elements can be implemented with one or more metal-insulator-metal (MIM) capacitors formed on an IPD die. 
     In yet another embodiment the output matching network  104  can further include a shunt inductive element and a shunt capacitive element connected to the first output terminal. And in some variations on this embodiment a video bandwidth circuit or baseband termination circuit can be coupled to a connection node between the shunt inductive element and the shunt capacitive element. 
     Next, it should be noted that in many applications the amplifier  100  can be implemented to include multiple transistors  102  in parallel, and that these multiple transistors  102  can be implemented in multiple parallel amplification paths. An example of such an implementation will be described in detail with reference to  FIG. 7  below. In such embodiments each amplification path can include at least one transistor  102  and at least one output matching network  104 , with each output matching network  104  including the resonant circuits  106 ,  108  and  110 . 
     Finally, it should be noted that amplifier  100  is a simplified representation of a portion of an amplifier, and in a more typical implementation the amplifier  100  would include additional features not illustrated in  FIG. 1 . Also, as used herein, the term “package” means a collection of structural components (e.g., including a flange or other package substrate) to which the primary electrical components (e.g., input and output leads, transistor dies, IPD dies, and various electrical interconnections) are coupled and/or encased. The package  111  is thus a distinct device that may be mounted to a printed circuit board (PCB) or other substrate that includes other devices and portions of a circuit. As specific examples, the package  111  can comprise an air cavity or over-molded package having a suitable package substrate, input leads, and output leads. 
     Turning now to  FIG. 3 , a circuit diagram representation of an exemplary amplifier  300  is illustrated. In this embodiment, the amplifier  300  again includes a transistor  302  and an output matching network  304 . Note that an input matching network (e.g., input matching network  103 ) would also typically be included in amplifier  300 , but is not illustrated in  FIG. 3  for clarity. During operation, the amplifier  300  receives an input signal at an input terminal  312 , and outputs an amplified signal through the output matching network  304  and the load terminal  318 . In a typical packaged implementation the input terminal  312  would be coupled to an input lead (e.g., first input lead  112 ) and the load terminal  318  would be coupled to an output lead (e.g., first output lead  114 ). Also, in a typical RF application the amplified signal would have include significant signal energy at a fundamental frequency (f 0 ), and would include lesser signal energy at multiple harmonic frequencies, including signal energy at a second harmonic (2f 0 ) frequency and third harmonic (3f 0 ) frequency. 
     In  FIG. 3  the transistor  302  is modelled as a current source  320  and associated resistances and capacitances. A control terminal (e.g., a gate) of the transistor  302  is coupled to the input terminal  312 , a first transistor output terminal  326  or first current conducting terminal (e.g., a drain terminal) is coupled to the output matching network  304 , and a second current conducting terminal (e.g., a source terminal) is coupled to a ground node (or another voltage reference). Included in this transistor model is an intrinsic input capacitance  324  and an intrinsic output capacitance  322 . In a typical field-effect transistor implementation, the intrinsic output capacitance  322  would represent a drain-source capacitance commonly referred to as C DS . In a typical bipolar transistor, the intrinsic output capacitance  322  would be a collector-emitter capacitance commonly referred to as C CE . 
     It should be noted that at high frequencies such an intrinsic output capacitance  322  would normally provide a capacitive reactance path to ground that would prevent efficient class F operation. However, in the embodiments described herein, the intrinsic output capacitance  322  is selectively resonated with resonant circuits in output matching network  304  to block the path to ground  310  for signal energy at the third harmonic frequency (3f 0 ), and this facilitates class F amplifier operation. 
     In the embodiment illustrated in  FIG. 3 , the output matching network  304  is implemented with capacitive elements  332 ,  334  and with inductive elements  340 ,  342 ,  344 . These various capacitive elements and inductive elements in the output matching network  304  are configured to provide three resonant circuits in the amplifier  300 . Taken together, these three resonant circuits in the output matching network  304  facilitate the operation of the amplifier  300  as an effective, high efficiency, class F amplifier. Specifically, to generate the voltage and current waveforms needed for class F amplifier operation, these three resonant circuits are implemented to provide a low impedance path (e.g., short circuit) to ground at the transistor  302  for signal energy at the second harmonic frequency (2f 0 ) and to provide a high impedance path (e.g., open circuit) to ground for signal energy at the third harmonic frequency (3f 0 ). 
     Turning now to  FIG. 4 , the exemplary class F amplifier  300  is again illustrated schematically. However, in this illustration the resonant circuits  412 ,  414  and  416  are individually identified and labelled. In general, the first 2f 0  resonant circuit  412  is a series inductor-capacitor (LC) circuit implemented to resonate and provide a low impedance path (e.g., short circuit) to ground at the transistor  302  for signal energy at the second harmonic frequency (2f 0 ). Likewise, the first 3f 0  resonant circuit  414  is a series LC circuit implemented to resonate and provide a low impedance path (e.g., short circuit) between the load terminal  318  and ground for signal energy at the third harmonic frequency (3f 0 ). Finally, the second 3f 0  resonant circuit  416  is equivalent to a parallel LC circuit implemented to resonate and provide a high impedance path (e.g., open circuit) between the transistor  302  and ground for signal energy at the third harmonic frequency (3f 0 ). Taken together, these resonant circuits can thus generate the voltage and current waveforms needed for class F amplifier operation. 
     In the example of  FIG. 4 , the first 2f 0  resonant circuit  412  includes capacitive element  332  and inductive element  340 , and circuit  412  is configured to resonate at a second harmonic frequency (2f 0 ). The first 3f 0  resonant circuit  414  includes capacitive element  334  and inductive element  344 , and circuit  414  is configured to resonate at a third harmonic frequency (3f 0 ). Finally, the second 3f 0  resonant circuit  416  includes intrinsic output capacitance  322 , capacitive element  332  and inductive elements  340  and  342 , and circuit  416  is configured to resonate at the third harmonic frequency (3f 0 ). Specifically, the first 2f 0  resonant circuit  412  is configured to resonate at the second harmonic frequency (2f 0 ) and create a short circuit between the first transistor output terminal  326  and a ground for signal energy at the second harmonic frequency (2f 0 ). Likewise, the first 3f 0  resonant circuit  414  is configured to resonate at a third harmonic frequency (3f 0 ) and create a short circuit between the load terminal  318  (and the associated output lead) and the ground for signal energy at the third harmonic frequency (3f 0 ). Finally, the second 3f 0  resonant circuit  416  is configured to resonate at the third harmonic frequency (3f 0 ) and create an open circuit between the transistor  302  output and the load terminal  318  (and associated output lead) for signal energy at the third harmonic frequency (3f 0 ). 
     Furthermore, it should be noted that in this embodiment the second 3f 0  resonant circuit  416  is dependent upon the resonating of at least the first 3f 0  resonant circuit  414  to be realized. More specifically, the first 3f 0  resonant circuit  414  is a series LC circuit (e.g., one or more inductors and capacitors in series) configured to resonate at 3f 0 . Series LC circuits provide low impedance paths (e.g., short circuit) when resonating. Thus, for signal energy at 3f 0 , the first 3f 0  resonant circuit  414  resonates and provides a low impedance connection between the load terminal  318  and ground  310 . 
     With the first 3f 0  resonant circuit  414  resonating and providing a low impedance connection, the second 3f 0  resonant circuit  416  is realized to be equivalent to a parallel LC circuit configured to resonate at 3f 0 . Specifically, with the first 3f 0  resonant circuit  412  resonating and providing a short circuit, the intrinsic output capacitance  322 , the inductive element  342  and the series combination of capacitive element  332  and inductive element  340  are then in parallel and form a parallel LC circuit configured to resonate at 3f 0 . Thus, for signal energy at 3f 0 , the second 3f 0  resonant circuit  416  provides high impedance path (e.g., open circuit) between the transistor  302  output and ground  310 . 
     Again, the first 3f 0  resonant circuit  414  is a series LC circuit and thus is configured create a short circuit between the load terminal  318  (and the associated output lead) and the ground for signal energy at the third harmonic frequency (3f 0 ). It should again be noted that this configuration is not typically found in a class F implementation, as class F amplifiers need high impedance (e.g., open circuit) at the transistor  302  output for signal energy at the third harmonic frequency (3f 0 ). However, in this embodiment described herein, the short circuit created by the first 3f 0  resonant circuit  414  allows the second 3f 0  resonant circuit  416  to be realized. Specifically, the second 3f 0  resonant circuit  416  is only realized when the first 3f 0  resonant circuit  414  resonates and generates a short circuit path to ground. Thus, the second 3f 0  resonant circuit  416  is not in a form that will resonate at the third harmonic frequency (3f 0 ) without the simultaneous resonating of the first 3f 0  resonant circuit  414 . Stated another way, the second 3f 0  resonant circuit  416  is dependent upon the resonating of the first 3f 0  resonant circuit  414 . Furthermore, the second 3f 0  resonant circuit  416  is a parallel LC circuit and when it resonates it creates high impedance or open circuit at the transistor  302  output. Thus, when the first 3f 0  resonant circuit  414  resonates, the second 3f 0  resonant circuit  416  is realized, and when circuit  416  also is resonating it creates the needed high impedance (e.g., open circuit) for signal energy at the third harmonic frequency (3f 0 ). 
     It should also be noted that in addition to facilitating class F operation, the resonating of the second 3f 0  resonant circuit  416  also may effectively reduce the potentially negative effects of the intrinsic output capacitance  322 . Specifically, the resonating of the second 3f 0  resonant circuit  416  provides a high impedance path to ground  310 , which blocks the current path through the intrinsic output capacitance  322  for signal energy at 3f 0 . Without such blocking, the intrinsic output capacitance  322  would provide a path to the ground  310  that can interfere with efficient amplifier operation. 
     As was described above, in various embodiments of amplifier  300  the various capacitive elements  332 ,  334  and inductive elements  340 ,  342 ,  344  are implemented inside the device package with the transistor  302 . For examples, the various capacitive elements  332 ,  334  and inductive elements  340 ,  342 ,  344  may be implemented with integrated passive devices (IPDs), which comprise a semiconductor substrate with a passive device formed in built-up conductive and dielectric layers overlying the semiconductor substrate. In other embodiments, some of the capacitive and/or inductive elements may be implemented with discrete components. Furthermore, in some embodiments, some or all of the various inductive elements  340 ,  342 ,  344  may be implemented with bondwires inside the device package. In one specific embodiment that will be described in greater detail below, the inductive element  342  may be implemented by a first bondwire array that is connected between the first transistor output terminal  326  and an output lead. Likewise, the inductive element  344  may be implemented as a second bondwire array in a bond-back configuration, connecting from output lead back to a capacitor and/or an IPD die inside the package. Finally, in such an embodiment the capacitive elements  332  and  334  can be implemented on the IPD die inside the package. And again, implementing these capacitive elements  332 ,  334  and inductive elements  340 ,  342 ,  344  with such components inside the device package may facilitate improved high frequency performance in the amplifier  100 ,  300 , particularly in high power applications. 
     Turning now to  FIG. 5 , a circuit diagram representation of an exemplary amplifier  500  is illustrated. In this embodiment, the amplifier  500  again includes a transistor  302  and an output matching network  504 . Note that an input matching network (e.g., input matching network  103 ) would also typically be included in amplifier  500 , but is not illustrated in  FIG. 5  for clarity. During operation, the amplifier  500  receives an input signal at an input terminal  312 , and outputs an amplified signal through the output matching network  504  and to the load terminal  318 . In a typical packaged implementation the input terminal  312  would be coupled to an input lead (e.g., first input lead  112 ) and the load terminal  318  would be coupled to an output lead (e.g., first output lead  114 ). Also, in a typical RF application the amplified signal would have significant signal energy at a fundamental frequency (f 0 ), and would include additional signal energy at multiple harmonic frequencies, including signal energy at a second harmonic (2f 0 ) frequency and third harmonic (3f 0 ) frequency. 
     The amplifier  500  includes capacitances and inductances that are configured to form three resonant circuits in the output matching network  504 , which facilitates the operation of the amplifier  500  as an effective, high efficiency, class F amplifier. However, in this embodiment the second 3f 0  resonant circuit  516  includes an additional capacitive element  532  and an additional inductive element  534 . Thus, in this embodiment the second 3f 0  resonant circuit  516  includes intrinsic output capacitance  322 , capacitive elements  332 ,  532  and inductive elements  340 ,  342 ,  534  and is configured to resonate at the third harmonic frequency (3f 0 ). When so resonating the second 3f 0  resonant circuit  516  is configured to create an open circuit between the transistor  302  output and the load terminal  318  (and associated output lead) for signal energy at the third harmonic frequency (3f 0 ). 
     In this embodiment the additional capacitive element  532  and an additional inductive element  534  are arranged in a shunt configuration. Thus, the capacitive element  532  provides a shunt capacitive element and the inductive element  534  provides a shunt inductive element. In general, this configuration of the capacitive element  532  and inductive element  523  can help provide an appropriate impedance transformation for signal energy at the fundamental frequency (f 0 ). Specifically, the capacitive element  532  can be implemented with relatively large capacitor that acts as a near short circuit for signal energy at the fundamental frequency (f 0 ). Thus, this signal energy sees only the shunt inductance provided by the inductive element  534 . Accordingly, the combination of inductive element  534  and capacitive element  532  can be considered a high-pass matching circuit. 
     Furthermore, the node  538  between the inductive element  534  and capacitive element  532  provides a point of low impedance for RF signal energy. This RF low-impedance point at node  538  provides a coupling point for a baseband decoupling circuit  536  (sometimes referred to as a video bandwidth (VBW) circuit). In general, the baseband decoupling circuit  536  is coupled between the RF low impedance point and ground, and is implemented to provide a desired impedance response in the baseband frequency region below the fundamental frequency (f 0 ). At these low baseband frequencies the inductive element  534  essentially acts as a short circuit while the capacitive element  532  acts as an open circuit. Thus, at these low frequencies the transistor  302  essentially only sees the impedance provided by the baseband decoupling circuit  536 . Thus, by implementing the baseband decoupling circuit  536 , the desired impedance response in the baseband region can be provided. In one specific embodiment, the baseband decoupling circuit  536  is configured to improve the low frequency resonance (LFR) of the amplifier  500  caused by the interaction between the input or output impedance matching circuits and the bias feeds (not shown) by presenting a low impedance at envelope frequencies and/or a high impedance at RF frequencies. When properly implemented the baseband decoupling circuit  536  essentially may be considered to be “invisible” from an RF matching standpoint, as it primarily affects the impedance at the low baseband frequencies by providing low impedance terminations for signal energy at these frequencies. The baseband decoupling circuit  536  may have any of a number of different circuit configurations, in various embodiments. 
     Turning now to  FIG. 6 , a circuit diagram of an exemplary baseband decoupling circuit  636  is illustrated. The baseband decoupling circuit  636  is one example of the type of circuit that can be used in amplifiers described herein. Thus, the baseband decoupling circuit  636  is an example of the type of circuit that can be used as the baseband decoupling circuit  536  in  FIG. 5 . The baseband decoupling circuit  636  includes a resistive element  602 , an inductive element  604 , and a capacitive element  606 . In this illustrated example the resistive element  602 , the inductive element  604 , and the capacitive element  606  are coupled together in series between a node  608  and ground  610 . In a typical embodiment the node  608  of the baseband decoupling circuit  636  would be connected to an RF low-impedance point (e.g., node  538  in  FIG. 5 ) in the output matching network of the amplifier. 
     In this illustrated embodiment the resistive element  602 , inductive element  604 , and capacitive element  606  serve as an envelope resistance, envelope inductance and envelope capacitive element respectively. With the resistive element  602 , inductive element  604 , and capacitive element  606  so configured, the baseband decoupling circuit  636  can provide a desired impedance response in the baseband frequency region below the fundamental frequency (f 0 ). Specifically, at these low baseband frequencies, the baseband decoupling circuit  636  presents a relatively low impedance for signal energy at baseband (e.g., envelope) frequencies and a relatively high impedance for signal energy at RF frequencies. 
     As described above, in many embodiments the baseband decoupling circuit  636  would be implemented inside the device package, with the transistor (e.g., transistor  302 ) and the output matching network (e.g., output matching network  502 ). In such embodiments the resistive element  602 , inductive element  604 , and capacitive element  606  can be implemented with integrated devices on IPDs, discrete devices, bondwires, etc. A detailed example of such an implementation will be shown in  FIG. 9 . 
     Finally, it should be noted that baseband decoupling circuit  636  is just one example of the type of circuit that can be employed. For example, the order of the resistive element  602 , inductive element  604 , and capacitive element  606  in the series circuit can be changed in some other embodiments. In yet other embodiments “bypass” or “parallel” inductances, resistances, and capacitances can be added across some or all of the resistive element  602 , inductive element  604 , and capacitive element  606 . A variety of specific exemplary video bandwidth circuits that could be used as baseband decoupling circuits can be found in U.S. patent application Ser. No. 15/983,974, entitled “Broadband Power Transistor Devices and Amplifiers and Methods of Manufacture Thereof”, and filed on May 18, 2018, which is incorporated herein by reference. 
     Turning now to  FIG. 7 , a schematic view of an amplifier  700  in accordance with an exemplary embodiment is illustrated. In this example, amplifier  700  includes a package  711 , four field effect transistors (FETs)  702 , four output matching networks  704 , four input matching networks  705 , two input leads  712 , and two output leads  714 . In this example, amplifier  700  implements two amplification paths, with each amplification path including two parallel input matching networks  705 , two FETs  702 , and two output matching networks  704 , all encased together in one package  711 . For example, the package  711  may include a package substrate (e.g., flange or other substrate with a conductive top surface that serves as a ground plane) to which the various FET dies and IPDs are connected, along with conductive leads that are electrically isolated from the substrate and electrically connected to the circuitry contained within the package  711 . The package  711  may be an air-cavity package or a plastic encapsulated (overmolded) package. 
     In accordance with the embodiments described herein, output matching networks  704 , are implemented to include a first 2f 0  resonant circuit configured to resonate at a second harmonic frequency (2f 0 ), and first and second 3f 0  resonant circuits configured to resonate at a third harmonic frequency (3f 0 ). And as was described above, each of the capacitive, inductive and resistive elements used to implement these resonant circuits can be implemented inside the package  711 . 
     It should be noted that the amplifier  700  illustrated in  FIG. 7  is just one example, and many other device implementations are possible. For example, other amplifiers can include more or fewer amplification paths, transistors, and matching networks. 
     For example,  FIG. 8  is a top view of an embodiment of a partial packaged RF amplifier device  800 . For enhanced understanding,  FIG. 8  should be viewed in conjunction with  FIG. 9 , which is a cross-sectional, side view of a portion of the amplifier device  800 . Specifically,  FIG. 9  shows a cross-sectional view through a portion of flange  806 , transistor die  830 , IPD assembly  880 , and output lead  804 . 
     The packaged RF amplifier device  800  embodies two parallel instances of a class F amplifier (e.g., amplifier  100 ,  300 ,  500 ) implemented in a package  811 , although only one instance is shown in the partial top view of  FIG. 8 . As will be described in greater detail below, the amplifier device  800  includes an output side IPD assembly  880  and various bondwires which together implement an output matching network (e.g., output matching network  104 ,  304 ,  504 ). 
     The amplifier device  800  includes a flange  806  (or “device substrate”) as part of the package  811 . In one embodiment, the flange  806  includes a rigid electrically-conductive substrate with a thickness that is sufficient to provide structural support for various electrical components and elements of amplifier device  800 . In addition, flange  806  may function as a heat sink for transistor die  830  and other devices mounted on flange  806 . Flange  806  has top and bottom surfaces (only a central portion of the top surface is visible in  FIG. 8 ), and a substantially-rectangular perimeter that corresponds to the perimeter of the amplifier device  800 . 
     Flange  806  is formed from an electrically conductive material, and may be used to provide a ground reference node for the device  800  (e.g., providing ground  310 ,  610 ). For example, various components and elements may have terminals that are electrically coupled to flange  806 , and flange  806  may be electrically coupled to a system ground when the device  800  is incorporated into a larger electrical system. At least the top surface of flange  806  is formed from a layer of conductive material, and possibly all of flange  806  is formed from bulk conductive material. 
     An isolation structure  808  is attached to the top surface of flange  806 , in an embodiment. Isolation structure  808 , which is formed from a rigid, electrically insulating material, provides electrical isolation between conductive features of the device (e.g., between leads  802  and  804  and flange  806 ). Isolation structure  808  has a frame shape, in an embodiment, which includes a substantially enclosed, four-sided structure with a central opening. Isolation structure  808  may have a substantially rectangular shape, as shown in  FIG. 8 , or isolation structure  808  may have another shape (e.g., annular ring, oval, and so on). 
     A portion of the top surface of flange  806  that is exposed through the opening in isolation structure  808  is referred to herein as the “active area” of device  800 . Transistor die  830  is positioned within the active device area of device  800 , along with IPD assemblies  818 , and  880 , which will be described in more detail later. For example, the transistor die  830  and the IPD assemblies  818  and  880  may be coupled to the top surface of flange  806  using conductive epoxy, solder, solder bumps, sintering, and/or eutectic bonds. 
     As noted above, the amplifier device  800  houses two amplifiers having two amplifier paths, although only one is illustrated in  FIG. 8 . The illustrated portion of the amplifier device  800  includes an input lead  802  and an output lead  804 . The input lead  802  and the output lead  804  are mounted on a top surface of the isolation structure  808  on opposed sides of the central opening, and thus the input and output leads  802 ,  804  are elevated above the top surface of the flange  806 , and are electrically isolated from the flange  806 . Generally, the input and output leads  802 ,  804  are oriented to allow for attachment of bondwires between the input and output leads  802 ,  804  and components and elements within the central opening of isolation structure  808 . 
     Transistor die  830  includes an integrated power FET, where the FET has a control terminal (e.g., a gate) and two current conducting terminals (e.g., a drain terminal and a source terminal), with one of those current conducting terminals configured as a transistor output terminal. A control terminal of a FET within the transistor die  830  is coupled through an input impedance matching circuit  810  to the input lead  802 . In addition, one current conducting terminal (e.g., the drain terminal) of a FET within the transistor die  830  is coupled through the output matching circuit  850  to the output lead  804 . The other current conducting terminal (e.g., the source) of a FET within the transistor die  830  is electrically coupled to the flange  806  (e.g., to ground), in an embodiment. 
     In addition to the input and output leads  802 ,  804 , device  800  also may include bias leads  890 ,  892 . Input-side bias lead  890  is typically electrically coupled through bondwires and other conductors to a control terminal of a FET within the transistor die  830 . Likewise, output-side bias lead  892  is typically electrically coupled through bondwires and other conductors to a current conducting terminal or output terminal (e.g., the drain) of a FET within the transistor die  830 . These bias leads  890  and  892  may be electrically coupled to external bias circuits (not shown) to provide bias voltages to the FET. In other embodiments, either or both the input-side or output-side bias leads  890  and  892  may be excluded. 
     According to one embodiment, the package  811  of the amplifier device  800  is an air cavity package, in which transistor die  830 , IPD assemblies  880  and various other components are located within an enclosed air cavity. Basically, the air cavity is bounded by flange  806 , isolation structure  808 , and a cap (not shown) overlying and in contact with the isolation structure  808  and leads  802 ,  804 ,  890 ,  892 . In other embodiments, the package  811  may include an overmolded package (i.e., a package in which the electrical components within the active device area are encapsulated with a non-conductive molding compound, and in which portions of the leads  802 ,  804 ,  890 ,  892  also may be encompassed by the molding compound). In such an overmolded package, isolation structure  808  may be excluded. 
     As noted above, the input impedance matching network is coupled between a control terminal (e.g., the gate) of the FET within the transistor die  830  and the input lead  802 . Likewise, the output matching network  850  is coupled between a current conducting terminal (e.g., the drain terminal) of a FET within a transistor die  830  and the output lead  804 . In accordance with the embodiments described herein, the output matching network  850  is implemented to include a first 2f 0  resonant circuit configured to resonate at a second harmonic frequency (2f 0 ), and first and second 3f 0  resonant circuits configured to resonate at a third harmonic frequency (3f 0 ). And as was described above, each of the capacitive, inductive and resistive elements used to implement these resonant circuits can be implemented inside the package  811 . 
     Specifically, in the amplifier device  800  the output matching network  850  is implemented using capacitive elements  832 ,  834 ,  835  and with inductive elements  840 ,  842 ,  844 ,  845 . In this illustrated example capacitive element  832  can correspond to capacitive element  332  of  FIGS. 3, 4 and 5 , capacitive element  834  can correspond to capacitive element  334  of  FIGS. 3, 4 and 5 , and capacitive element  835  can correspond to capacitive element  532  of  FIG. 5 . Likewise, inductive element  840  can correspond to inductive element  340  of  FIGS. 3, 4 and 5 , inductive element  842  can correspond to inductive element  342  of  FIGS. 3, 4 and 5 , inductive element  844  can correspond to inductive element  344  of  FIGS. 3, 4 and 5 , and inductive element  845  can correspond to inductive element  534  of  FIG. 5 . These various capacitances and inductances in the output matching network  850  are configured to provide three resonant circuits in the amplifier device  800 . Taken together, these three resonant circuits in the output matching network  850  facilitates the operation of the amplifier device  800  as an effective, high efficiency, class F amplifier. 
     In the amplifier device  800  the capacitive elements  832 ,  834  and  835  are implemented with integrated capacitors on the output side IPD assembly  880 . For example, the capacitive elements  832 ,  834  and  835  may be implemented as metal-insulator-metal (MIM) capacitors within the IPD assembly  880 . In other embodiments, one or more of these capacitive elements may be implemented with a discrete capacitor, or a capacitor that is formed in another type of assembly (e.g., a low-temperature co-fired ceramic (LTCC) assembly). 
     In the amplifier device  800  the inductive elements  840 ,  842 ,  844 ,  845  are implemented with bondwires. Specifically, each inductive element  840 ,  842 ,  844 ,  845  is implemented with a plurality of generally parallel, closely-spaced sets of bondwires, generally referred to as a bondwire array. It should be noted that the number and arrangement of bondwires would be selected based on the power handling requirements and the desired inductances of the bondwires. Thus, for connections that require more power handling ability more bondwires can be provided. 
     In the example of  FIG. 8 , the inductive element  840  includes a plurality of bondwires coupled between a transistor output terminal  828  on the transistor die  830  and a bond pad terminal  932  that is electrically coupled to the capacitive element  832  on the IPD assembly  880 . For clarity, only two of the bondwires of inductive element  840  are labeled in  FIG. 8 . However, it should be understood that inductive element  840  includes all bondwires coupled between the transistor output terminal  828  and the bond pad terminal  932  of the capacitive element  832 . Likewise, the inductive element  842  includes a plurality of bondwires coupled between the transistor output terminal  828  on the transistor die  830  and the output lead  804  (again, for clarity only three of the bondwires of inductive element  842  are labeled in  FIG. 8 ). Likewise, the inductive element  844  includes a plurality of bondwires coupled between the output lead  804  and a bond pad terminal  934  that is electrically coupled to capacitive element  834  on the IPD assembly  880  in a bond-back configuration (again, for clarity only two of the bondwires of inductive element  844  are labeled in  FIG. 8 ). Finally, the inductive element  845  includes a plurality of bondwires coupled between the transistor output terminal  828  on the transistor die  830  and a bond pad terminal  935  that is electrically coupled to capacitive element  835  on the IPD assembly  880  (again, for clarity only two of the bondwires of inductive element  845  are labeled in  FIG. 8 ). 
     It should be noted that in the example of  FIG. 8  each the inductive elements in the three resonant circuits of the output matching network  850  are implemented with bondwires rather than using additional integrated or discrete inductors. Again, using only bondwires to provide the inductances of the resonant circuits can reduce the number of components used to implement the output matching network  850  and can thus minimize the overall amount of losses in the amplifier  800  and generally improve amplifier performance. In alternate embodiments, some portion of these inductive elements could be implemented using integrated inductors and/or discrete inductor devices. 
       FIG. 9  more clearly illustrates example embodiments of the capacitive elements  832 ,  834 ,  835  and inductive elements  840 ,  842 ,  844 ,  845  of the exemplary output matching network (e.g., output matching network  504 ). Again, the capacitive elements  832 ,  834  and  835  are implemented with integrated capacitors on the output side IPD assembly  880 . For example, the capacitive elements  832 ,  834  and  835  may be implemented as metal-insulator-metal (MIM) capacitors within the IPD assembly  880 . 
     In general, MIM capacitors are integrated capacitors formed from patterned conductive and dielectric layers on a semiconductor substrate. Portions of the conductive layers corresponding to electrodes are aligned with each other and separated (electrically and physically) from each other by dielectric layers. Specifically, the conductive electrodes are formed from patterned portions of the conductive layers of a build-up structure, where the build-up structure includes alternating dielectric and conductive layers. Each electrode may include a portion of a single conductive layer or multiple conductive layers, where the patterned portions of the conductive layers for a single electrode can be electrically connected using conductive vias, and the conductive layers for the two electrodes are interleaved with each other in an alternating arrangement. The amount of capacitance provided by a MIM capacitor can thus be determined by the patterned size and shape of the conductive layers (electrodes), the dielectric constant and thickness of the intervening dielectric layers, and the number of conductive layers electrically connected together to form each capacitor electrode. Furthermore, in a typical embodiment a number of MIM capacitors will be formed on an IPD assembly (e.g., IPD assembly  880 ) and a selected subset of those MIM capacitors can be electrically coupled together to provide a capacitive element with the desired capacitance value. Thus, some or all of the various capacitive elements  832 ,  834  and  835  can be implemented with one or more MIM capacitors electrically connected together to provide the desired capacitance value. 
     Alternatively, some or all of the capacitive elements  832 ,  834  and  835  may be implemented, for example, as discrete capacitors that are connected (e.g., using solder, a conductive epoxy, or other means) to a top surface of the IPD assembly  880 . Although particular two-plate capacitor structures are shown in  FIG. 9  for capacitive elements  832 ,  834  and  835 , a variety of other capacitor structures alternatively may be utilized, as would be understood by one of skill in the art based on the description herein. 
     Also illustrated in  FIGS. 8 and 9  are the elements of an exemplary baseband decoupling circuit (e.g., baseband decoupling circuit  536 ,  636 ). In this example, the baseband decoupling circuit includes an inductive element, a resistance, and a capacitance coupled together in series. Specifically, the baseband decoupling circuit includes an envelope resistor  902  (e.g., resistive element  602 ,  FIG. 6 ), an envelope inductor  904  (e.g., inductive element  604 ,  FIG. 6 ), and an envelope capacitor  906  (e.g., capacitive element  606 ,  FIG. 6 ) electrically connected between an RF low-impedance point between inductive element  845  and capacitive element  835  and a ground reference (e.g., flange  806 ). 
     In this embodiment, the envelope resistor  902  is integrally formed as part of the IPD assembly  880 . For example, each envelope resistor  902  may be a polysilicon resistor formed from a layer of polysilicon. In other alternate embodiments, the envelope resistor  902  may be formed from tungsten silicide or another material, may be a thick or thin film resistor, or may be a discrete component coupled to a top surface of IPD assembly  880 . 
     In this embodiment, the envelope inductor  904  is also integrally formed as part of the IPD assembly  880 . For example, the envelope inductor  904  may be a patterned conductor formed from portion(s) of one or more conductive layers of the build-up structure. In alternate embodiments, the envelope inductor  904  may be implemented as a plurality of bondwires, or as a spiral inductor (e.g., integrated within, on or proximate to the top surface of IPD assembly  880 ), or as a discrete inductor coupled to a top surface of IPD assembly  880 . 
     In this embodiment, the envelope capacitor  906  is also integrally formed as part of the IPD assembly  880 . Specifically, envelope capacitor  906  may be a MIM capacitor that is integrally formed with the IPD substrate of IPD assembly  880 . In some embodiments, envelope capacitor  906  may be formed in the build-up structure entirely above the semiconductor substrate, or instead may have portions that extend into the semiconductor substrate or are otherwise coupled to, or in contact with, the semiconductor substrate. According to an embodiment, the envelope capacitor  906  may be formed from a first electrode, a second electrode, and a dielectric material between the first and second electrodes. The dielectric material of envelope capacitor  906  may include one or more layers of polysilicon, various oxides, a nitride, or other suitable materials. In various embodiments, the first and second electrodes of envelope capacitor  906  may include horizontal portions of conductive layers (e.g., portions that are parallel to the top and bottom surfaces of IPD assembly  880 ) and/or vertical portions (e.g., portions that are parallel to the sides of IPD assembly  880 ) of conductive layers that are interconnected. Further, the first and second electrodes of envelope capacitor  906  may be formed from metal layers and/or from conductive semiconductor materials (e.g., polysilicon). Alternatively, the envelope capacitor  906  may be, for example, a discrete capacitor that is connected (e.g., using solder, a conductive epoxy, or other means) to a top surface of the IPD assembly  880 . Again, although a particular two-plate capacitor structure is shown in  FIG. 9  for envelope capacitor  906 , a variety of other capacitor structures alternatively may be utilized, as would be understood by one of skill in the art based on the description herein. 
     Turning now to  FIG. 10 , a flowchart illustrates a method  1000  for fabricating a packaged RF power amplifier device (e.g., class F amplifier  100 ,  300 ,  500 ,  700 ,  800 ,  FIGS. 1, 3-5, 7-9 ) that includes an output matching network (e.g., output matching network  104 ,  304 ,  504 ,  704 ,  850 ). The output matching network is implemented to include three resonant circuits (e.g., a first 2f 0  resonant circuit  106 , a first 3f 0  resonant circuit  108 , and a second 3f 0  resonant circuit  110 ). These three resonant circuits facilitate the operation of the amplifier as an effective, high efficiency, class F amplifier. 
     The output matching network is implemented to include inductive and capacitive elements that define these three resonant circuits elements. At least some of the inductive elements (e.g., inductive elements  340 ,  342 ,  344 ,  535 ,  840 ,  842 ,  844 ,  845 ) are implemented with bondwires while other inductive elements (e.g., inductive element  604 ,  904 ) may be implemented with bondwires, discrete inductors, or integrated inductors. Likewise, the capacitive elements (e.g., capacitive elements  332 ,  334 ,  532 ,  832 ,  834 ,  835 ,  906 ) are implemented with integrated capacitors, although some or all of the capacitive elements could be implemented with discrete capacitors. In such implementations the three resonant circuits in the output matching network can be fully implemented inside the package, and may provide the amplifier with good performance at relatively high frequencies and over a relatively wide bandwidth. 
     The method  1000  may begin, in block  1002 , by providing a package having a package substrate, input lead, and output lead (e.g., package  811 , flange  806 , input lead  802 , output lead  804 ). In block  1004  a first transistor die (e.g., transistor die  830  is coupled to the device package. This coupling can be accomplished by affixing the transistor die to package substrate (e.g., flange  806 ) using conductive epoxy, solder, solder bumps, sintering, and/or eutectic bonds, to give non-limiting examples. 
     In block  1006  an integrated passive device die (e.g., IPD assembly  880 ) is coupled to the device substrate between the transistor die and the output lead. As described above, the IPD die includes integrated passive devices, such as integrated MIM capacitors (e.g., capacitive elements  832 ,  834 ,  835 ,  906 ), integrated resistors (e.g., resistor  902 ), and integrated inductors (e.g., inductor  904 ). 
     In block  1008  an output matching network is created by connecting the inductive elements and capacitive elements. As described above, bondwires can be used to provide electrical connections between the integrated capacitive elements, the transistor, and the package leads. When so implemented, these bondwires also provide at least some of the inductive elements of the three resonant circuits (e.g., inductive elements  340 ,  342 ,  344 ,  534  of the resonant circuits  412 ,  414 ,  416 ,  516 ). 
     In block  1010  the device is capped (e.g., for an air cavity package) or encapsulated (e.g., with mold compound for an overmolded package). The resulting packaged amplifier device may then be incorporated into a larger electrical system. 
     It should be noted that the method  1000  can be expanded to also provide an input matching network (e.g., input matching network  103 ,  705 ) in the amplifier. 
     Taken together, the method  1000  can thus facilitate an implementation of an amplifier device with an output matching network that includes three or more resonant circuits. Taken together, these resonant circuits in the output matching network facilitate the operation of the amplifier as an effective, high efficiency, class F amplifier. Specifically, to generate the voltage and current waveforms needed for class F amplifier operation, the three resonant circuits are implemented to provide a low impedance (e.g., short circuit) at the transistor for signal energy at the second harmonic frequency (2f 0 ) and to provide a high impedance (e.g., open circuit) for signal energy at the third harmonic frequency (3f 0 ). Furthermore, the method  1000  allows these three resonant circuits to be fully implemented inside the device package, and as such may provide the amplifier with high frequency, wide bandwidth performance. Furthermore, in some embodiments these amplifier devices can be implemented with GaN-based transistors that can provide high efficiency and high power density. 
     In one embodiment a class F radio frequency (RF) amplifier configured to operate at a fundamental frequency (f 0 ) is provided, the class F RF amplifier comprising: a device package including at least a first output lead and a first input lead, the device package encasing: a first transistor die, wherein the first transistor die includes a first transistor, a first input terminal, and a first output terminal, the first transistor including an intrinsic output capacitance providing a first capacitance; and a first output matching network coupled between the first output terminal and the first output lead, the first output matching network including: a first bondwire array connected between the first output terminal and the first output lead, the first bondwire array providing a first inductance; a first 2f 0  resonant circuit configured to resonate at a second harmonic frequency (2f 0 ) and create a short circuit between the first output terminal and a ground for signal energy at the second harmonic frequency (2f 0 ); a first 3f 0  resonant circuit configured to resonate at a third harmonic frequency (3f 0 ) and create a short circuit between the first output lead and the ground for signal energy at the third harmonic frequency (3f 0 ); and wherein when the first 3f 0  resonant circuit resonates, a second 3f 0  resonant circuit is realized, where the second 3f 0  resonant circuit includes the intrinsic output capacitance, the first inductance, and the first 2f 0  resonant circuit, and wherein the second 3f 0  resonant circuit is configured to resonate at the third harmonic frequency (3f 0 ) and create an open circuit. 
     In another embodiment a packaged class F radio frequency (RF) amplifier configured to operate at a fundamental frequency (f 0 ) is provided, the packaged class F RF amplifier comprising: a package substrate; a first input lead coupled to the package substrate; a first output lead coupled to the package substrate; a first transistor die coupled to the package substrate, wherein the first transistor die includes a first transistor, a first input terminal, and a first output terminal, and wherein the first transistor includes an intrinsic output capacitance providing a first capacitance; a first output matching network coupled between the first output terminal and the first output lead, the first output matching network including: a first integrated passive device (IPD) die coupled to the package substrate, the first IPD die including a first integrated capacitive element providing a second capacitance, and a second integrated capacitive element providing a third capacitance; a first bondwire array connected between the first output terminal and the first output lead, the first bondwire array providing a first inductance; a second bondwire array directly connected between the first output lead and the first IPD die, the second bondwire array providing a second inductance; a third bondwire array connected between the first output terminal and the first IPD die, the third bondwire array providing a third inductance; a first 2f 0  resonant circuit configured to resonate at a second harmonic frequency (2f 0 ) and create a short circuit between the first output terminal and a ground for signal energy at the second harmonic frequency (2f 0 ), wherein the first 2f 0  resonant circuit includes the third inductance in series with and the third capacitance; a first 3f 0  resonant circuit configured to resonate at a third harmonic frequency (3f 0 ) and create a short circuit between the first output lead and the ground for signal energy at the third harmonic frequency (3f 0 ), wherein the first 3f 0  resonant circuit includes the second inductance in series with the second capacitance; and wherein when the first 3f 0  resonant circuit resonates, a second 3f 0  resonant circuit is realized, where the second 3f 0  resonant circuit includes the intrinsic output capacitance in parallel with the first inductance and in parallel with a combination of the third inductance in series with the third capacitance, and wherein the second 3f 0  resonant circuit is configured to resonate at the third harmonic frequency (3f 0 ) and create an open circuit between the first output terminal and the first output lead for signal energy at the third harmonic frequency (3f 0 ). 
     In another embodiment a method of manufacturing a class F radio frequency (RF) amplifier device is provided, the method comprising the steps of: coupling a first input lead to a package substrate; coupling a first output lead to the package substrate; coupling a first transistor die to the package substrate, wherein the first transistor die includes a first transistor, a first input terminal, and a first output terminal, the first transistor including an intrinsic output capacitance providing a first capacitance; coupling an integrated passive device to the package substrate between the transistor die and the first output lead, wherein the integrated passive device includes one or more first integrally formed capacitors providing a second capacitance and one or more second integrally formed capacitors providing a third capacitance; and creating an output matching network coupled between the first output terminal and the first output lead by: connecting a first bondwire array between the first output terminal and the first output lead; connecting a second bondwire array between the first output lead and the integrated passive device, the second bondwire array providing a second inductance, such that a first 3f 0  resonant circuit that includes the second inductance and the second capacitance is created, wherein the first 3f 0  resonant circuit is configured to resonate at a third harmonic frequency (3f 0 ) and create an open circuit between the first output terminal and a ground for signal energy at the third harmonic frequency (3f 0 ); connecting a third bondwire array between the first output terminal and the integrated passive device, the third bondwire array providing a third inductance, such that a first 2f 0  resonant circuit that includes the third inductance and the third capacitance is created, wherein the first 2f 0  resonant circuit is configured to resonate at a second harmonic frequency (2f 0 ) and create a short circuit between the first output terminal and the ground for signal energy at the second harmonic frequency (2f 0 ); and wherein the first bondwire array provides a first inductance, and wherein the connecting of the first bondwire array between the first output terminal and the first output lead is such that when the first 3f 0  resonant circuit resonates a second 3f 0  resonant circuit is realized, where the second 3f 0  resonant circuit includes the intrinsic output capacitance, the first inductance, and the first 2f 0  resonant circuit, and wherein the second 3f 0  resonant circuit is configured to resonate at the third harmonic frequency (3f 0 ) and create an open circuit between the first output terminal and the first output lead for signal energy at the third harmonic frequency (3f 0 ). 
     Turning now to  FIG. 11 , an exemplary inverse class F amplifier  1100  is illustrated schematically. In this embodiment, the amplifier  1100  includes a first transistor  1102 , a first input matching network  1103 , a first output matching network  1104 , and a package  1111  that includes a first input lead  1112  and a first output lead  1114 . During operation, the amplifier  1100  receives an input signal at a first input lead  1112 , and outputs an amplified signal through the output matching network  1104  and the first output lead  114 . The output amplified signal has signal energy at a fundamental frequency (f 0 ) and additional signal energy at multiple harmonic frequencies, including a second harmonic frequency of twice the fundamental frequency (2f 0 ) and a third harmonic frequency of three times the fundamental frequency (3f 0 ). 
     In accordance with the embodiments described herein, the output matching network  1104  includes three resonant circuits: a first 3f 0  resonant circuit  1106 , a first 2f 0  resonant circuit  1108 , and a second 2f 0  resonant circuit  1110 . In general, the first 3f 0  resonant circuit  1106  is configured to resonate at a third harmonic frequency (3f 0 ), and the first 2f 0  resonant circuit  1108  and the second 2f 0  resonant circuit  1110  are configured to resonate at a second harmonic frequency (2f 0 ). As will be described below, these three resonant circuits ( 1106 ,  1108  and  1110 ) facilitate the operation of the amplifier  1100  as an effective, high efficiency, inverse class F amplifier. 
     As also will be described in greater detail below, the three resonant circuits ( 1106 ,  1108  and  1110 ) in the output matching network  1104  include inductive elements and capacitive elements. The various inductive elements may be implemented with IPDs and/or bondwires inside the device package  1111 . Likewise, the various capacitive elements may be implemented with IPDs inside the device package  1111 , and/or with discrete capacitors. Implementing the output matching network  1104  with such components inside the device package  1111  may facilitate improved high frequency performance in the amplifier  1100 , particularly in high power applications. 
     In typical implementations the transistor  1102  is formed on a transistor die, and that transistor die typically includes a first input terminal (e.g., a gate control terminal), a first output terminal (e.g., a first current conducting terminal, such as a drain terminal), and a second output terminal (e.g., a second current conducting terminal, such as a source terminal) that are used to connect to the transistor  1102 . In one specific embodiment, the transistor  1102  comprises a gallium nitride (GaN) field-effect transistor (FET), but other transistor types can also be used. As more specific examples, various III-V field effect transistors may be used (e.g., a high electron mobility transistor (HEMT)), such as a GaN FET (or another type of III-V transistor, including a gallium arsenide (GaAs) FET, a gallium phosphide (GaP) FET, an indium phosphide (InP) FET, or an indium antimonide (InSb) FET). In other examples the transistor  1102  may be implemented with a III-V FET or with a silicon-based FET (e.g., a laterally-diffused metal oxide semiconductor (LDMOS) FET). 
     In general, inverse class F amplifiers generate specific defined output voltage and current waveforms. These output waveforms minimize power consumption by reducing the portions of each cycle where current and voltage overlap. Turning to  FIG. 12 , a graph  1200  illustrates an idealized output voltage and graph  1250  illustrates an idealized output current for an exemplary inverse class F amplifier (e.g., amplifier  1100 ). As can be seen in  FIG. 12 , the output voltage is a half-sinusoid that is non-zero over the first half of the output cycle, and the output current is a square wave that is non-zero only over the second half of the output signal. When so implemented with substantially non-overlapping voltage and current output waveforms, power consumption is reduced, and a high efficiency inverse class F amplifier is provided. 
     To generate such voltage and current waveforms and provide inverse class F amplifier operation, the impedance presented at a transistor (e.g., transistor  1102 ), as referenced to the current source in the transistor, should exhibit high impedance to frequencies at the even harmonic frequencies and low impedance to frequencies at odd harmonic frequencies. In particular, providing high impedance for signal energy at the second harmonic frequency is of particular importance, with diminishing importance for higher order even harmonic frequencies. Likewise, providing low impedance for signal energy at the third harmonic frequency is of particular importance, with diminishing importance for higher order odd harmonic frequencies. Thus for many applications, providing a high impedance (e.g., open circuit) for signal energy at the second harmonic frequency (2f 0 ) and providing a low impedance (e.g., short circuit) for signal energy at the third harmonic frequency (3f 0 ) can be sufficient to provide effective inverse class F amplifier performance. 
     Returning to  FIG. 11 , the amplifier  1100  is configured to provide high efficiency, inverse class F operation through the use of the three resonant circuits ( 1106 ,  1108  and  1110 ) in the output matching network  1104 . In general, the first 3f 0  resonant circuit  1106  is configured to resonate at a third harmonic frequency (3f 0 ), and the first 2f 0  resonant circuit  1108  and the second 2f 0  resonant circuit  1110  are configured to resonate at a second harmonic frequency (2f 0 ). Specifically, the first 3f 0  resonant circuit  1106  is configured to resonate at a third harmonic frequency (3f 0 ) and create a short circuit between the first output terminal and a ground for signal energy at the third harmonic frequency (3f 0 ). Likewise, the first 2f 0  resonant circuit  1108  is configured to resonate at a second harmonic frequency (2f 0 ) and create a short circuit between the first output lead  1114  and the ground for signal energy at the second harmonic frequency (2f 0 ). Finally, the second 2f 0  resonant circuit  1110  is configured to resonate at the second harmonic frequency (2f 0 ) and create an open circuit between the first output terminal and the first output lead  1114  for signal energy at the second harmonic frequency (2f 0 ). 
     Again, the first 2f 0  resonant circuit  1108  is configured create a short circuit between the first output lead  114  and the ground for signal energy at the second harmonic frequency (2f 0 ). It should be noted that this configuration is not typically found in an inverse class F implementation, as inverse class F amplifiers need high impedance (e.g., open circuit) at the output for signal energy at the second harmonic frequency (2f 0 ). However, in the embodiments described herein, the short circuit created by the first 2f 0  resonant circuit  1108  allows the second 2f 0  resonant circuit  1110  to be realized. Specifically, the second 2f 0  resonant circuit  1110  is only realized when the first 2f 0  resonant circuit  1108  resonates and generates a short circuit. Thus, the second 2f 0  resonant circuit  1110  is not in a form that will resonate at the second harmonic frequency (2f 0 ) without the simultaneous resonating of the first 2f 0  resonant circuit  1108 . Stated another way, the second 2f 0  resonant circuit  1110  is dependent upon the resonating of the first 2f 0  resonant circuit  1108 . Furthermore, when the second 2f 0  resonant circuit  1110  resonates it creates a high impedance or open circuit. Thus, when the first 2f 0  resonant circuit  1108  resonates, the second 2f 0  resonant circuit  1110  is realized and when also resonating creates the needed high impedance (e.g., open circuit) for signal energy at the second harmonic frequency (2f 0 ). 
     In one specific embodiment, the second 2f 0  resonant circuit  1110  is implemented in part with an inductance provided by a first bondwire array that is connected between a first output terminal of the transistor  1102  and the first output lead  1114 . In such an embodiment, the first bondwire array provides the high power RF signal transmission path between the transistor  1102  and the first output lead. As such, the first bondwire array is typically a relatively large bondwire array that can create a relatively large inductance. 
     Likewise, in one specific embodiment the first 2f 0  resonant circuit  1108  is implemented in part with an inductance provided by a second bondwire array that is connected between the first output lead and an IPD die. In such an embodiment the first 2f 0  resonant circuit  1108  is effectively implemented on the output lead side of the device, with the inductance provided by second bondwire array in a bond-back configuration from the output lead  1114  to the IPD die. Implementing the first 2f 0  resonant circuit  1108  with the second bondwire array in a bond-back configuration, and implementing the second 2f 0  resonant circuit  1110  to include the first bondwire array providing the main connection between transistor  1102  and the output lead  1114  can provide distinct performance advantages. For example, such a configuration can facilitate inverse class F operation using only bondwires as the inductive elements of the output matching network  1104  rather than using additional integrated or discrete inductors. Using only bondwires to provide the inductances can minimize the overall amount of losses in the amplifier  1100 . Furthermore, such a configuration can provide a high impedance (e.g., open circuit) for signal energy at the second harmonic frequency (2f 0 ) at transistor output terminal, no matter what impedance is presented outside of the package. 
     In one embodiment that will be described in greater detail below, the second 2f 0  resonant circuit  1110  is implemented to include a first capacitance provided by the intrinsic output capacitance of the transistor  1102 , a first inductance provided by a first bondwire array, and the components of the first 3f 0  resonant circuit. It should be noted that in such an embodiment the inclusion of the intrinsic output capacitance in the second 2f 0  resonant circuit  1110  can at least partially compensate for the generally adverse effects of that capacitance. 
     Specifically, the intrinsic output capacitance of a typical transistor (e.g., transistor  1102 ) can allow a capacitive reactance path to ground for high frequency signal energy, including signal energy at the second harmonic frequency (2f 0 ). Such a capacitive reactance path would, if left uncompensated, provide a low impedance path for signal energy at second harmonic frequencies, and thus would prevent efficient inverse class F operation. The embodiments described herein can overcome this by incorporating the intrinsic output capacitance into a second 2f 0  resonant circuit in a way that eliminates the low impedance path that would otherwise exist for signal energy at the second harmonic frequency (2f 0 ). 
     In one embodiment, the output matching network  1104  is implemented with a second bondwire array, the second bondwire array connected to the first output lead and a first capacitive element. In this embodiment, the second bondwire array provides a second inductance, the first capacitive element provides a second capacitance, and the first 2f 0  resonant circuit includes the second inductance and the second capacitance. As one specific example, the second bondwire array can be arranged in bond-back configuration, connecting from the first output lead back to an IPD die inside the package  1111 . 
     In yet another embodiment, the output matching network  1104  is further implemented with a third bondwire array, the third bondwire array connected to the first output terminal and a second capacitive element. In this embodiment the third bondwire array provides a third inductance, the second capacitive element provides a third capacitance, and the first 3f 0  resonant circuit includes the third inductance and the third capacitance. In such embodiments both the second capacitive element and the third capacitive element can comprise IPDs formed on an IPD die. As one specific example, these capacitive elements can be implemented with one or more metal-insulator-metal (MIM) capacitors formed on an IPD die. 
     In yet another embodiment the output matching network  1104  can further include a shunt inductive element and a shunt capacitive element connected to the first output terminal. And in some variations on this embodiment a video bandwidth circuit or baseband termination circuit can be coupled to a connection node between the shunt inductive element and the shunt capacitive element. 
     Next, it should be noted that in many applications the amplifier  1100  can be implemented to include multiple transistors  1102  in parallel, and that these multiple transistors  1102  can be implemented in multiple parallel amplification paths. An example of such an implementation will be described in detail with reference to  FIG. 17  below. In such embodiments each amplification path can include at least one transistor  1102  and at least one output matching network  1104 , with each output matching network  1104  including the resonant circuits  1106 ,  1108  and  1110 . 
     Finally, it should be noted that amplifier  1100  is a simplified representation of a portion of an amplifier, and in a more typical implementation the amplifier  1100  would include additional features not illustrated in  FIG. 11 . Also, as used herein, the term “package” means a collection of structural components (e.g., including a flange or other package substrate) to which the primary electrical components (e.g., input and output leads, transistor dies, IPD dies, and various electrical interconnections) are coupled and/or encased. The package  1111  is thus a distinct device that may be mounted to a printed circuit board (PCB) or other substrate that includes other devices and portions of a circuit. As specific examples, the package  1111  can comprise an air cavity or over-molded package having a suitable package substrate, input leads, and output leads. 
     Turning now to  FIG. 13 , a circuit diagram representation of an exemplary amplifier  1300  is illustrated. In this embodiment, the amplifier  1300  again includes a transistor  1302  and an output matching network  1304 . Note that an input matching network (e.g., input matching network  1103 ) would also typically be included in amplifier  1300 , but is not illustrated in  FIG. 13  for clarity. During operation, the amplifier  1300  receives an input signal at an input terminal  1312 , and outputs an amplified signal through the output matching network  1304  and the load terminal  1318 . In a typical packaged implementation the input terminal  1312  would be coupled to an input lead (e.g., first input lead  1112 ) and the load terminal  1318  would be coupled to an output lead (e.g., first output lead  1114 ). Also, in a typical RF application the amplified signal would have include significant signal energy at a fundamental frequency (f 0 ), and would include lesser signal energy at multiple harmonic frequencies, including signal energy at a second harmonic (2f 0 ) frequency and third harmonic (3f 0 ) frequency. 
     In  FIG. 13  the transistor  1302  is modelled as a current source  1320  and associated resistances and capacitances. A control terminal (e.g., a gate) of the transistor  1302  is coupled to the input terminal  1312 , a first transistor output terminal  1326  or first current conducting terminal (e.g., a drain terminal) is coupled to the output matching network  1304 , and a second current conducting terminal (e.g., a source terminal) is coupled to a ground node (or another voltage reference). Included in this transistor model is an intrinsic input capacitance  1324  and an intrinsic output capacitance  1322 . In a typical field-effect transistor implementation, the intrinsic output capacitance  1322  would represent a drain-source capacitance commonly referred to as C DS . In a typical bipolar transistor, the intrinsic output capacitance  1322  would be a collector-emitter capacitance commonly referred to as C CE . 
     It should be noted that at high frequencies such an intrinsic output capacitance  1322  would normally provide a capacitive reactance path to ground that would prevent efficient inverse class F operation. However, in the embodiments described herein, the intrinsic output capacitance  1322  is selectively resonated with resonant circuits in output matching network  1304  to block the path to ground  1310  for signal energy at the second harmonic frequency (2f 0 ), and this facilitates inverse class F amplifier operation. 
     In the embodiment illustrated in  FIG. 13 , the output matching network  1304  is implemented with capacitive elements  1332 ,  1334  and with inductive elements  1340 ,  1342 ,  1344 . These various capacitive elements and inductive elements in the output matching network  1304  are configured to provide three resonant circuits in the amplifier  1300 . Taken together, these three resonant circuits in the output matching network  1304  facilitate the operation of the amplifier  1300  as an effective, high efficiency, inverse class F amplifier. Specifically, to generate the voltage and current waveforms needed for inverse class F amplifier operation, these three resonant circuits are implemented to provide a high impedance path (e.g., open circuit) to ground at the transistor  1302  for signal energy at the second harmonic frequency (2f 0 ) and to provide a low impedance path (e.g., short circuit) to ground for signal energy at the third harmonic frequency (3f 0 ). 
     Turning now to  FIG. 14 , the exemplary inverse class F amplifier  1300  is again illustrated schematically. However, in this illustration the resonant circuits  1412 ,  1414  and  1416  are individually identified and labelled. In general, the first 3f 0  resonant circuit  1412  is a series inductor-capacitor (LC) circuit implemented to resonate and provide a low impedance path (e.g., short circuit) to ground at the transistor  102  for signal energy at the third harmonic frequency (3f 0 ). Likewise, the first 2f 0  resonant circuit  1414  is a series LC circuit implemented to resonate and provide a low impedance path (e.g., short circuit) between the load terminal  1318  and ground for signal energy at the second harmonic frequency (2f 0 ). Finally, the second 2f 0  resonant circuit  1416  is equivalent to a parallel LC circuit implemented to resonate and provide a high impedance path (e.g., open circuit) between the transistor  1302  and ground for signal energy at the second harmonic frequency (2f 0 ). Taken together, these resonant circuits can thus generate the voltage and current waveforms needed for inverse class F amplifier operation. 
     In the example of  FIG. 14 , the first 3f 0  resonant circuit  1412  includes capacitive element  1332  and inductive element  1340 , and circuit  1412  is configured to resonate at a third harmonic frequency (3f 0 ). The first 2f 0  resonant circuit  1414  includes capacitive element  1334  and inductive element  1344 , and circuit  1414  is configured to resonate at a second harmonic frequency (2f 0 ). Finally, the second 2f 0  resonant circuit  1416  includes intrinsic output capacitance  1322 , capacitive element  1332  and inductive elements  1340  and  1342 , and circuit  1416  is configured to resonate at the second harmonic frequency (2f 0 ). Specifically, the first 3f 0  resonant circuit  1412  is configured to resonate at the third harmonic frequency (3f 0 ) and create a short circuit between the first transistor output terminal  1326  and a ground for signal energy at the third harmonic frequency (3f 0 ). Likewise, the first 2f 0  resonant circuit  1414  is configured to resonate at a second harmonic frequency (2f 0 ) and create a short circuit between the load terminal  1318  (and the associated output lead) and the ground for signal energy at the second harmonic frequency (2f 0 ). Finally, the second 2f 0  resonant circuit  1416  is configured to resonate at the second harmonic frequency (2f 0 ) and create an open circuit between the transistor  1302  output and the load terminal  1318  (and associated output lead) for signal energy at the second harmonic frequency (2f 0 ). 
     Furthermore, it should be noted that in this embodiment the second 2f 0  resonant circuit  1416  is dependent upon the resonating of at least the first 2f 0  resonant circuit  1414  to be realized. More specifically, the first 2f 0  resonant circuit  1414  is a series LC circuit (e.g., one or more inductors and capacitors in series) configured to resonate at 2f 0 . Series LC circuits provide low impedance paths (e.g., short circuit) when resonating. Thus, for signal energy at 2f 0 , the first 2f 0  resonant circuit  1414  resonates and provides a low impedance connection between the load terminal  1318  and ground  1310 . 
     With the first 2f 0  resonant circuit  1414  resonating and providing a low impedance connection, the second 2f 0  resonant circuit  1416  is realized to be equivalent to a parallel LC circuit configured to resonate at 2f 0 . Specifically, with the first 2f 0  resonant circuit  1412  resonating and providing a short circuit, the intrinsic output capacitance  1322 , the inductive element  1342  and the series combination of capacitive element  1332  and inductive element  1340  are then in parallel and form a parallel LC circuit configured to resonate at 2f 0 . Thus, for signal energy at 2f 0 , the second 2f 0  resonant circuit  1416  provides high impedance path (e.g., open circuit) between the transistor  1302  output and ground  1310 . 
     Again, the first 2f 0  resonant circuit  1414  is a series LC circuit and thus is configured create a short circuit between the load terminal  1318  (and the associated output lead) and the ground for signal energy at the second harmonic frequency (2f 0 ). It should again be noted that this configuration is not typically found in an inverse class F implementation, as inverse class F amplifiers need high impedance (e.g., open circuit) at the transistor  1302  output for signal energy at the second harmonic frequency (2f 0 ). However, in this embodiment described herein, the short circuit created by the first 2f 0  resonant circuit  1414  allows the second 2f 0  resonant circuit  1416  to be realized. Specifically, the second 2f 0  resonant circuit  1416  is only realized when the first 2f 0  resonant circuit  1414  resonates and generates a short circuit path to ground. Thus, the second 2f 0  resonant circuit  1416  is not in a form that will resonate at the second harmonic frequency (2f 0 ) without the simultaneous resonating of the first 2f 0  resonant circuit  1414 . Stated another way, the second 2f 0  resonant circuit  1416  is dependent upon the resonating of the first 2f 0  resonant circuit  1414 . Furthermore, the second 2f 0  resonant circuit  1416  is a parallel LC circuit and when it resonates it creates high impedance or open circuit at the transistor  1302  output. Thus, when the first 2f 0  resonant circuit  1414  resonates, the second 2f 0  resonant circuit  1416  is realized, and when circuit  1416  also is resonating it creates the needed high impedance (e.g., open circuit) for signal energy at the second harmonic frequency (2f 0 ). 
     It should also be noted that in addition to facilitating inverse class F operation, the resonating of the second 2f 0  resonant circuit  1416  also may effectively reduce the potentially negative effects of the intrinsic output capacitance  1322 . Specifically, the resonating of the second 2f 0  resonant circuit  1416  provides a high impedance path to ground  1310 , which blocks the current path through the intrinsic output capacitance  1322  for signal energy at 2f 0 . Without such blocking, the intrinsic output capacitance  1322  would provide a path to the ground  1310  that can interfere with efficient amplifier operation. 
     As was described above, in various embodiments of amplifier  1300  the various capacitive elements  1332 ,  1334  and inductive elements  1340 ,  1342 ,  1344  are implemented inside the device package with the transistor  1302 . For examples, the various capacitive elements  1332 ,  1334  and inductive elements  1340 ,  1342 ,  1344  may be implemented with integrated passive devices (IPDs), which comprise a semiconductor substrate with a passive device formed in built-up conductive and dielectric layers overlying the semiconductor substrate. In other embodiments, some of the capacitive and/or inductive elements may be implemented with discrete components. Furthermore, in some embodiments, some or all of the various inductive elements  1340 ,  1342 ,  1344  may be implemented with bondwires inside the device package. In one specific embodiment that will be described in greater detail below, the inductive element  1342  may be implemented by a first bondwire array that is connected between the first transistor output terminal  1326  and an output lead. Likewise, the inductive element  1344  may be implemented as a second bondwire array in a bond-back configuration, connecting from output lead back to a capacitor and/or an IPD die inside the package. Finally, in such an embodiment the capacitive elements  1332  and  1334  can be implemented on the IPD die inside the package. And again, implementing these capacitive elements  1332 ,  1334  and inductive elements  1340 ,  1342 ,  1344  with such components inside the device package may facilitate improved high frequency performance in the amplifier  1100 ,  1300 , particularly in high power applications. 
     Turning now to  FIG. 15 , a circuit diagram representation of an exemplary amplifier  1500  is illustrated. In this embodiment, the amplifier  1500  again includes a transistor  1302  and an output matching network  1504 . Note that an input matching network (e.g., input matching network  1103 ) would also typically be included in amplifier  1500 , but is not illustrated in  FIG. 15  for clarity. During operation, the amplifier  1500  receives an input signal at an input terminal  1312 , and outputs an amplified signal through the output matching network  1504  and to the load terminal  1318 . In a typical packaged implementation the input terminal  1312  would be coupled to an input lead (e.g., first input lead  1112 ) and the load terminal  1318  would be coupled to an output lead (e.g., first output lead  1114 ). Also, in a typical RF application the amplified signal would have significant signal energy at a fundamental frequency (f 0 ), and would include additional signal energy at multiple harmonic frequencies, including signal energy at a second harmonic (2f 0 ) frequency and third harmonic (3f 0 ) frequency. 
     The amplifier  1500  includes capacitances and inductances that are configured to form three resonant circuits in the output matching network  1504 , which facilitates the operation of the amplifier  1500  as an effective, high efficiency, inverse class F amplifier. However, in this embodiment the second 2f 0  resonant circuit  1516  includes an additional capacitive element  1532  and an additional inductive element  1534 . Thus, in this embodiment the second 2f 0  resonant circuit  1516  includes intrinsic output capacitance  1322 , capacitive elements  1332 ,  1532  and inductive elements  1340 ,  1342 ,  1534  and is configured to resonate at the second harmonic frequency (2f 0 ). When so resonating the second 2f 0  resonant circuit  1516  is configured to create an open circuit between the transistor  1302  output and the load terminal  1318  (and associated output lead) for signal energy at the second harmonic frequency (2f 0 ). 
     In this embodiment the additional capacitive element  1532  and an additional inductive element  1534  are arranged in a shunt configuration. Thus, the capacitive element  1532  provides a shunt capacitive element and the inductive element  1534  provides a shunt inductive element. In general, this configuration of the capacitive element  1532  and inductive element  1523  can help provide an appropriate impedance transformation for signal energy at the fundamental frequency (f 0 ). Specifically, the capacitive element  1532  can be implemented with relatively large capacitor that acts as a near short circuit for signal energy at the fundamental frequency (f 0 ). Thus, this signal energy sees only the shunt inductance provided by the inductive element  1534 . Accordingly, the combination of inductive element  1534  and capacitive element  1532  can be considered a high-pass matching circuit. 
     Furthermore, the node  1538  between the inductive element  1534  and capacitive element  1532  provides a point of low impedance for RF signal energy. This RF low-impedance point at node  1538  provides a coupling point for a baseband decoupling circuit  1536  (sometimes referred to as a video bandwidth (VBW) circuit). In general, the baseband decoupling circuit  1536  is coupled between the RF low impedance point and ground, and is implemented to provide a desired impedance response in the baseband frequency region below the fundamental frequency (f 0 ). At these low baseband frequencies the inductive element  1534  essentially acts as a short circuit while the capacitive element  1532  acts as an open circuit. Thus, at these low frequencies the transistor  1302  essentially only sees the impedance provided by the baseband decoupling circuit  1536 . Thus, by implementing the baseband decoupling circuit  1536 , the desired impedance response in the baseband region can be provided. In one specific embodiment, the baseband decoupling circuit  1536  is configured to improve the low frequency resonance (LFR) of the amplifier  1500  caused by the interaction between the input or output impedance matching circuits and the bias feeds (not shown) by presenting a low impedance at envelope frequencies and/or a high impedance at RF frequencies. When properly implemented the baseband decoupling circuit  1536  essentially may be considered to be “invisible” from an RF matching standpoint, as it primarily affects the impedance at the low baseband frequencies by providing low impedance terminations for signal energy at these frequencies. The baseband decoupling circuit  1536  may have any of a number of different circuit configurations, in various embodiments. 
     Turning now to  FIG. 16 , a circuit diagram of an exemplary baseband decoupling circuit  1636  is illustrated. The baseband decoupling circuit  1636  is one example of the type of circuit that can be used in amplifiers described herein. Thus, the baseband decoupling circuit  1636  is an example of the type of circuit that can be used as the baseband decoupling circuit  1536  in  FIG. 15 . The baseband decoupling circuit  1636  includes a resistive element  1602 , an inductive element  1604 , and a capacitive element  1606 . In this illustrated example the resistive element  1602 , the inductive element  1604 , and the capacitive element  1606  are coupled together in series between a node  1608  and ground  1610 . In a typical embodiment the node  1608  of the baseband decoupling circuit  1636  would be connected to an RF low-impedance point (e.g., node  1538  in  FIG. 15 ) in the output matching network of the amplifier. 
     In this illustrated embodiment the resistive element  1602 , inductive element  1604 , and capacitive element  1606  serve as an envelope resistance, envelope inductance and envelope capacitive element respectively. With the resistive element  1602 , inductive element  1604 , and capacitive element  1606  so configured, the baseband decoupling circuit  1636  can provide a desired impedance response in the baseband frequency region below the fundamental frequency (f 0 ). Specifically, at these low baseband frequencies, the baseband decoupling circuit  1636  presents a relatively low impedance for signal energy at baseband (e.g., envelope) frequencies and a relatively high impedance for signal energy at RF frequencies. 
     As described above, in many embodiments the baseband decoupling circuit  1636  would be implemented inside the device package, with the transistor (e.g., transistor  1302 ) and the output matching network (e.g., output matching network  1502 ). In such embodiments the resistive element  1602 , inductive element  1604 , and capacitive element  1606  can be implemented with integrated devices on IPDs, discrete devices, bondwires, etc. A detailed example of such an implementation will be shown in  FIG. 19 . 
     Finally, it should be noted that baseband decoupling circuit  1636  is just one example of the type of circuit that can be employed. For example, the order of the resistive element  1602 , inductive element  1604 , and capacitive element  1606  in the series circuit can be changed in some other embodiments. In yet other embodiments “bypass” or “parallel” inductances, resistances, and capacitances can be added across some or all of the resistive element  1602 , inductive element  1604 , and capacitive element  1606 . A variety of specific exemplary video bandwidth circuits that could be used as baseband decoupling circuits can be found in U.S. patent application Ser. No. 15/983,974, entitled “Broadband Power Transistor Devices and Amplifiers and Methods of Manufacture Thereof”, and filed on May 18, 2018, which is incorporated herein by reference. 
     Turning now to  FIG. 17 , a schematic view of an amplifier  1700  in accordance with an exemplary embodiment is illustrated. In this example, amplifier  1700  includes a package  1711 , four field effect transistors (FETs)  1702 , four output matching networks  1704 , four input matching networks  1705 , two input leads  1712 , and two output leads  1714 . In this example, amplifier  1700  implements two amplification paths, with each amplification path including two parallel input matching networks  1705 , two FETs  1702 , and two output matching networks  1704 , all encased together in one package  1711 . For example, the package  1711  may include a package substrate (e.g., flange or other substrate with a conductive top surface that serves as a ground plane) to which the various FET dies and IPDs are connected, along with conductive leads that are electrically isolated from the substrate and electrically connected to the circuitry contained within the package  1711 . The package  1711  may be an air-cavity package or a plastic encapsulated (overmolded) package. 
     In accordance with the embodiments described herein, output matching networks  7104 , are implemented to include a first 3f 0  resonant circuit configured to resonate at a third harmonic frequency (3f 0 ), and first and second 2f 0  resonant circuits configured to resonate at a second harmonic frequency (2f 0 ). And as was described above, each of the capacitive, inductive and resistive elements used to implement these resonant circuits can be implemented inside the package  1711 . 
     It should be noted that the amplifier  1700  illustrated in  FIG. 17  is just one example, and many other device implementations are possible. For example, other amplifiers can include more or fewer amplification paths, transistors, and matching networks. 
     For example,  FIG. 18  is a top view of an embodiment of a partial packaged RF amplifier device  1800 . For enhanced understanding,  FIG. 18  should be viewed in conjunction with  FIG. 19 , which is a cross-sectional, side view of a portion of the amplifier device  1800 . Specifically,  FIG. 19  shows a cross-sectional view through a portion of flange  1806 , transistor die  1830 , IPD assembly  1880 , and output lead  1804 . 
     The packaged RF amplifier device  1800  embodies two parallel instances of an inverse class F amplifier (e.g., amplifier  1100 ,  1300 ,  1500 ) implemented in a package  1811 , although only one instance is shown in the partial top view of  FIG. 18 . As will be described in greater detail below, the amplifier device  1800  includes an output side IPD assembly  1880  and various bondwires which together implement an output matching network (e.g., output matching network  1104 ,  1304 ,  1504 ). 
     The amplifier device  1800  includes a flange  1806  (or “device substrate”) as part of the package  1811 . In one embodiment, the flange  1806  includes a rigid electrically-conductive substrate with a thickness that is sufficient to provide structural support for various electrical components and elements of amplifier device  1800 . In addition, flange  1806  may function as a heat sink for transistor die  1830  and other devices mounted on flange  1806 . Flange  1806  has top and bottom surfaces (only a central portion of the top surface is visible in  FIG. 18 ), and a substantially-rectangular perimeter that corresponds to the perimeter of the amplifier device  1800 . 
     Flange  1806  is formed from an electrically conductive material, and may be used to provide a ground reference node for the device  1800  (e.g., providing ground  1310 ,  1610 ). For example, various components and elements may have terminals that are electrically coupled to flange  1806 , and flange  1806  may be electrically coupled to a system ground when the device  1800  is incorporated into a larger electrical system. At least the top surface of flange  1806  is formed from a layer of conductive material, and possibly all of flange  1806  is formed from bulk conductive material. 
     An isolation structure  1808  is attached to the top surface of flange  1806 , in an embodiment. Isolation structure  1808 , which is formed from a rigid, electrically insulating material, provides electrical isolation between conductive features of the device (e.g., between leads  1802  and  1804  and flange  1806 ). Isolation structure  1808  has a frame shape, in an embodiment, which includes a substantially enclosed, four-sided structure with a central opening. Isolation structure  1808  may have a substantially rectangular shape, as shown in  FIG. 18 , or isolation structure  1808  may have another shape (e.g., annular ring, oval, and so on). 
     A portion of the top surface of flange  1806  that is exposed through the opening in isolation structure  1808  is referred to herein as the “active area” of device  1800 . Transistor die  1830  is positioned within the active device area of device  1800 , along with IPD assemblies  1818 , and  1880 , which will be described in more detail later. For example, the transistor die  1830  and the IPD assemblies  1818  and  1880  may be coupled to the top surface of flange  1806  using conductive epoxy, solder, solder bumps, sintering, and/or eutectic bonds. 
     As noted above, the amplifier device  1800  houses two amplifiers having two amplifier paths, although only one is illustrated in  FIG. 18 . The illustrated portion of the amplifier device  1800  includes an input lead  1802  and an output lead  1804 . The input lead  1802  and the output lead  1804  are mounted on a top surface of the isolation structure  1808  on opposed sides of the central opening, and thus the input and output leads  1802 ,  1804  are elevated above the top surface of the flange  1806 , and are electrically isolated from the flange  1806 . Generally, the input and output leads  1802 ,  1804  are oriented to allow for attachment of bondwires between the input and output leads  1802 ,  1804  and components and elements within the central opening of isolation structure  1808 . 
     Transistor die  1830  includes an integrated power FET, where the FET has a control terminal (e.g., a gate) and two current conducting terminals (e.g., a drain terminal and a source terminal), with one of those current conducting terminals configured as a transistor output terminal. A control terminal of a FET within the transistor die  1830  is coupled through an input impedance matching circuit  1810  to the input lead  1802 . In addition, one current conducting terminal (e.g., the drain terminal) of a FET within the transistor die  1830  is coupled through the output matching circuit  1850  to the output lead  1804 . The other current conducting terminal (e.g., the source) of a FET within the transistor die  1830  is electrically coupled to the flange  1806  (e.g., to ground), in an embodiment. 
     In addition to the input and output leads  1802 ,  1804 , device  1800  also may include bias leads  1890 ,  1892 . Input-side bias lead  1890  is typically electrically coupled through bondwires and other conductors to a control terminal of a FET within the transistor die  1830 . Likewise, output-side bias lead  1892  is typically electrically coupled through bondwires and other conductors to a current conducting terminal or output terminal (e.g., the drain) of a FET within the transistor die  1830 . These bias leads  1890  and  1892  may be electrically coupled to external bias circuits (not shown) to provide bias voltages to the FET. In other embodiments, either or both the input-side or output-side bias leads  1890  and  1892  may be excluded. 
     According to one embodiment, the package  1811  of the amplifier device  1800  is an air cavity package, in which transistor die  1830 , IPD assemblies  1880  and various other components are located within an enclosed air cavity. Basically, the air cavity is bounded by flange  1806 , isolation structure  1808 , and a cap (not shown) overlying and in contact with the isolation structure  1808  and leads  1802 ,  1804 ,  1890 ,  1892 . In other embodiments, the package  1811  may include an overmolded package (i.e., a package in which the electrical components within the active device area are encapsulated with a non-conductive molding compound, and in which portions of the leads  1802 ,  1804 ,  1890 ,  1892  also may be encompassed by the molding compound). In such an overmolded package, isolation structure  1808  may be excluded. 
     As noted above, the input impedance matching network is coupled between a control terminal (e.g., the gate) of the FET within the transistor die  1830  and the input lead  1802 . Likewise, the output matching network  1850  is coupled between a current conducting terminal (e.g., the drain terminal) of a FET within a transistor die  1830  and the output lead  1804 . In accordance with the embodiments described herein, the output matching network  1850  is implemented to include a first 3f 0  resonant circuit configured to resonate at a third harmonic frequency (3f 0 ), and first and second 2f 0  resonant circuits configured to resonate at a second harmonic frequency (2f 0 ). And as was described above, each of the capacitive, inductive and resistive elements used to implement these resonant circuits can be implemented inside the package  1811 . 
     Specifically, in the amplifier device  1800  the output matching network  1850  is implemented using capacitive elements  1832 ,  1834 ,  1835  and with inductive elements  1840 ,  1842 ,  1844 ,  1845 . In this illustrated example capacitive element  1832  can correspond to capacitive element  1332  of  FIGS. 13, 14 and 15 , capacitive element  1834  can correspond to capacitive element  1334  of  FIGS. 13, 14 and 15 , and capacitive element  1835  can correspond to capacitive element  1532  of  FIG. 15 . Likewise, inductive element  1840  can correspond to inductive element  1340  of  FIGS. 13, 14 and 15 , inductive element  1842  can correspond to inductive element  1342  of  FIGS. 13, 14 and 15 , inductive element  1844  can correspond to inductive element  1344  of  FIGS. 13, 14 and 15 , and inductive element  1845  can correspond to inductive element  1534  of  FIG. 15 . These various capacitances and inductances in the output matching network  1850  are configured to provide three resonant circuits in the amplifier device  1800 . Taken together, these three resonant circuits in the output matching network  1850  facilitates the operation of the amplifier device  1800  as an effective, high efficiency, inverse class F amplifier. 
     In the amplifier device  1800  the capacitive elements  1832 ,  1834  and  1835  are implemented with integrated capacitors on the output side IPD assembly  1880 . For example, the capacitive elements  1832 ,  1834  and  1835  may be implemented as metal-insulator-metal (MIM) capacitors within the IPD assembly  1880 . In other embodiments, one or more of these capacitive elements may be implemented with a discrete capacitor, or a capacitor that is formed in another type of assembly (e.g., a low-temperature co-fired ceramic (LTCC) assembly). 
     In the amplifier device  1800  the inductive elements  1840 ,  1842 ,  1844 ,  1845  are implemented with bondwires. Specifically, each inductive element  1840 ,  1842 ,  1844 ,  1845  is implemented with a plurality of generally parallel, closely-spaced sets of bondwires, generally referred to as a bondwire array. It should be noted that the number and arrangement of bondwires would be selected based on the power handling requirements and the desired inductances of the bondwires. Thus, for connections that require more power handling ability more bondwires can be provided. 
     In the example of  FIG. 18 , the inductive element  1840  includes a plurality of bondwires coupled between a transistor output terminal  1828  on the transistor die  1830  and a bond pad terminal  1932  that is electrically coupled to the capacitive element  1832  on the IPD assembly  1880 . For clarity, only two of the bondwires of inductive element  1840  are labeled in  FIG. 18 . However, it should be understood that inductive element  1840  includes all bondwires coupled between the transistor output terminal  1828  and the bond pad terminal  1932  of the capacitive element  1832 . Likewise, the inductive element  1842  includes a plurality of bondwires coupled between the transistor output terminal  1828  on the transistor die  1830  and the output lead  1804  (again, for clarity only three of the bondwires of inductive element  842  are labeled in  FIG. 18 ). Likewise, the inductive element  1844  includes a plurality of bondwires coupled between the output lead  1804  and a bond pad terminal  1934  that is electrically coupled to capacitive element  1834  on the IPD assembly  1880  in a bond-back configuration (again, for clarity only two of the bondwires of inductive element  1844  are labeled in  FIG. 18 ). Finally, the inductive element  1845  includes a plurality of bondwires coupled between the transistor output terminal  1828  on the transistor die  1830  and a bond pad terminal  1935  that is electrically coupled to capacitive element  1835  on the IPD assembly  1880  (again, for clarity only two of the bondwires of inductive element  1845  are labeled in  FIG. 18 ). 
     It should be noted that in the example of  FIG. 18  each the inductive elements in the three resonant circuits of the output matching network  1850  are implemented with bondwires rather than using additional integrated or discrete inductors. Again, using only bondwires to provide the inductances of the resonant circuits can reduce the number of components used to implement the output matching network  1850  and can thus minimize the overall amount of losses in the amplifier  1800  and generally improve amplifier performance. In alternate embodiments, some portion of these inductive elements could be implemented using integrated inductors and/or discrete inductor devices. 
       FIG. 19  more clearly illustrates example embodiments of the capacitive elements  1832 ,  1834 ,  1835  and inductive elements  1840 ,  1842 ,  1844 ,  1845  of the exemplary output matching network (e.g., output matching network  1504 ). Again, the capacitive elements  1832 ,  1834  and  1835  are implemented with integrated capacitors on the output side IPD assembly  1880 . For example, the capacitive elements  1832 ,  1834  and  1835  may be implemented as metal-insulator-metal (MIM) capacitors within the IPD assembly  1880 . 
     In general, MIM capacitors are integrated capacitors formed from patterned conductive and dielectric layers on a semiconductor substrate. Portions of the conductive layers corresponding to electrodes are aligned with each other and separated (electrically and physically) from each other by dielectric layers. Specifically, the conductive electrodes are formed from patterned portions of the conductive layers of a build-up structure, where the build-up structure includes alternating dielectric and conductive layers. Each electrode may include a portion of a single conductive layer or multiple conductive layers, where the patterned portions of the conductive layers for a single electrode can be electrically connected using conductive vias, and the conductive layers for the two electrodes are interleaved with each other in an alternating arrangement. The amount of capacitance provided by a MIM capacitor can thus be determined by the patterned size and shape of the conductive layers (electrodes), the dielectric constant and thickness of the intervening dielectric layers, and the number of conductive layers electrically connected together to form each capacitor electrode. Furthermore, in a typical embodiment a number of MIM capacitors will be formed on an IPD assembly (e.g., IPD assembly  1880 ) and a selected subset of those MIM capacitors can be electrically coupled together to provide a capacitive element with the desired capacitance value. Thus, some or all of the various capacitive elements  1832 ,  1834  and  1835  can be implemented with one or more MIM capacitors electrically connected together to provide the desired capacitance value. 
     Alternatively, some or all of the capacitive elements  1832 ,  1834  and  1835  may be implemented, for example, as discrete capacitors that are connected (e.g., using solder, a conductive epoxy, or other means) to a top surface of the IPD assembly  1880 . Although particular two-plate capacitor structures are shown in  FIG. 19  for capacitive elements  1832 ,  1834  and  1835 , a variety of other capacitor structures alternatively may be utilized, as would be understood by one of skill in the art based on the description herein. 
     Also illustrated in  FIGS. 18 and 19  are the elements of an exemplary baseband decoupling circuit (e.g., baseband decoupling circuit  1536 ,  1636 ). In this example, the baseband decoupling circuit includes an inductive element, a resistance, and a capacitance coupled together in series. Specifically, the baseband decoupling circuit includes an envelope resistor  1902  (e.g., resistive element  1602 ,  FIG. 16 ), an envelope inductor  1904  (e.g., inductive element  1604 ,  FIG. 16 ), and an envelope capacitor  1906  (e.g., capacitive element  1606 ,  FIG. 16 ) electrically connected between an RF low-impedance point between inductive element  1845  and capacitive element  1835  and a ground reference (e.g., flange  1806 ). 
     In this embodiment, the envelope resistor  1902  is integrally formed as part of the IPD assembly  1880 . For example, each envelope resistor  1902  may be a polysilicon resistor formed from a layer of polysilicon. In other alternate embodiments, the envelope resistor  1902  may be formed from tungsten silicide or another material, may be a thick or thin film resistor, or may be a discrete component coupled to a top surface of IPD assembly  1880 . 
     In this embodiment, the envelope inductor  1904  is also integrally formed as part of the IPD assembly  1880 . For example, the envelope inductor  1904  may be a patterned conductor formed from portion(s) of one or more conductive layers of the build-up structure. In alternate embodiments, the envelope inductor  1904  may be implemented as a plurality of bondwires, or as a spiral inductor (e.g., integrated within, on or proximate to the top surface of IPD assembly  1880 ), or as a discrete inductor coupled to a top surface of IPD assembly  1880 . 
     In this embodiment, the envelope capacitor  1906  is also integrally formed as part of the IPD assembly  1880 . Specifically, envelope capacitor  1906  may be a MIM capacitor that is integrally formed with the IPD substrate of IPD assembly  1880 . In some embodiments, envelope capacitor  1906  may be formed in the build-up structure entirely above the semiconductor substrate, or instead may have portions that extend into the semiconductor substrate or are otherwise coupled to, or in contact with, the semiconductor substrate. According to an embodiment, the envelope capacitor  1906  may be formed from a first electrode, a second electrode, and a dielectric material between the first and second electrodes. The dielectric material of envelope capacitor  1906  may include one or more layers of polysilicon, various oxides, a nitride, or other suitable materials. In various embodiments, the first and second electrodes of envelope capacitor  1906  may include horizontal portions of conductive layers (e.g., portions that are parallel to the top and bottom surfaces of IPD assembly  1880 ) and/or vertical portions (e.g., portions that are parallel to the sides of IPD assembly  1880 ) of conductive layers that are interconnected. Further, the first and second electrodes of envelope capacitor  1906  may be formed from metal layers and/or from conductive semiconductor materials (e.g., polysilicon). Alternatively, the envelope capacitor  1906  may be, for example, a discrete capacitor that is connected (e.g., using solder, a conductive epoxy, or other means) to a top surface of the IPD assembly  1880 . Again, although a particular two-plate capacitor structure is shown in  FIG. 19  for envelope capacitor  1906 , a variety of other capacitor structures alternatively may be utilized, as would be understood by one of skill in the art based on the description herein. 
     Turning now to  FIG. 20 , a flowchart illustrates a method  2000  for fabricating a packaged RF power amplifier device (e.g., inverse class F amplifier  1100 ,  1300 ,  1500 ,  1700 ,  1800 ,  FIGS. 11, 13-15, 17-19 ) that includes an output matching network (e.g., output matching network  1104 ,  1304 ,  1504 ,  1704 ,  1850 ). The output matching network is implemented to include three resonant circuits (e.g., a first 3f 0  resonant circuit  1106 , a first 2f 0  resonant circuit  1108 , and a second 2f 0  resonant circuit  1110 ). These three resonant circuits facilitate the operation of the amplifier as an effective, high efficiency, inverse class F amplifier. 
     The output matching network is implemented to include inductive and capacitive elements that define these three resonant circuits elements. At least some of the inductive elements (e.g., inductive elements  1340 ,  1342 ,  1344 ,  1535 ,  1840 ,  1842 ,  1844 ,  1845 ) are implemented with bondwires while other inductive elements (e.g., inductive element  1604 ,  1904 ) may be implemented with bondwires, discrete inductors, or integrated inductors. Likewise, the capacitive elements (e.g., capacitive elements  1332 ,  1334 ,  1532 ,  1832 ,  1834 ,  1835 ,  1906 ) are implemented with integrated capacitors, although some or all of the capacitive elements could be implemented with discrete capacitors. In such implementations the three resonant circuits in the output matching network can be fully implemented inside the package, and may provide the amplifier with good performance at relatively high frequencies and over a relatively wide bandwidth. 
     The method  2000  may begin, in block  2002 , by providing a package having a package substrate, input lead, and output lead (e.g., package  1811 , flange  1806 , input lead  1802 , output lead  1804 ). In block  2004  a first transistor die (e.g., transistor die  1830  is coupled to the device package. This coupling can be accomplished by affixing the transistor die to package substrate (e.g., flange  1806 ) using conductive epoxy, solder, solder bumps, sintering, and/or eutectic bonds, to give non-limiting examples. 
     In block  2006  an integrated passive device die (e.g., IPD assembly  1880 ) is coupled to the device substrate between the transistor die and the output lead. As described above, the IPD die includes integrated passive devices, such as integrated MIM capacitors (e.g., capacitive elements  1832 ,  1834 ,  1835 ,  1906 ), integrated resistors (e.g., resistor  1902 ), and integrated inductors (e.g., inductor  1904 ). 
     In block  2008  an output matching network is created by connecting the inductive elements and capacitive elements. As described above, bondwires can be used to provide electrical connections between the integrated capacitive elements, the transistor, and the package leads. When so implemented, these bondwires also provide at least some of the inductive elements of the three resonant circuits (e.g., inductive elements  1340 ,  1342 ,  1344 ,  1534  of the resonant circuits  1412 ,  1414 ,  1416 ,  1516 ). 
     In block  2010  the device is capped (e.g., for an air cavity package) or encapsulated (e.g., with mold compound for an overmolded package). The resulting packaged amplifier device may then be incorporated into a larger electrical system. 
     It should be noted that the method  2000  can be expanded to also provide an input matching network (e.g., input matching network  1103 ,  1705 ) in the amplifier. 
     Taken together, the method  2000  can thus facilitate an implementation of an amplifier device with an output matching network that includes three or more resonant circuits. Taken together, these resonant circuits in the output matching network facilitate the operation of the amplifier as an effective, high efficiency, inverse class F amplifier. Specifically, to generate the voltage and current waveforms needed for inverse class F amplifier operation, the three resonant circuits are implemented to provide a high impedance (e.g., open circuit) at the transistor for signal energy at the second harmonic frequency (2f 0 ) and to provide a low impedance (e.g., short circuit) for signal energy at the third harmonic frequency (3f 0 ). Furthermore, the method  2000  allows these three resonant circuits to be fully implemented inside the device package, and as such may provide the amplifier with high frequency, wide bandwidth performance. 
     Furthermore, in some embodiments these amplifier devices can be implemented with GaN-based transistors that can provide high efficiency and high power density. 
     In one embodiment an inverse class F radio frequency (RF) amplifier configured to operate at a fundamental frequency (f 0 ), the inverse class F RF amplifier comprising: a device package including at least a first output lead and a first input lead, the device package encasing: a first transistor die, wherein the first transistor die includes a first transistor, a first input terminal, and a first output terminal, the first transistor including an intrinsic output capacitance providing a first capacitance; and a first output matching network coupled between the first output terminal and the first output lead, the first output matching network including: a first bondwire array connected between the first output terminal and the first output lead, the first bondwire array providing a first inductance; a first 3f 0  resonant circuit configured to resonate at a third harmonic frequency (3f 0 ) and create a short circuit between the first output terminal and a ground for signal energy at the third harmonic frequency (3f 0 ); a first 2f 0  resonant circuit configured to resonate at a second harmonic frequency (2f 0 ) and create a short circuit between the first output lead and the ground for signal energy at the second harmonic frequency (2f 0 ); and wherein when the first 2f 0  resonant circuit resonates, a second 2f 0  resonant circuit is realized, where the second 2f 0  resonant circuit includes the intrinsic output capacitance, the first inductance, and the first 3f 0  resonant circuit, and wherein the second 2f 0  resonant circuit is configured to resonate at the second harmonic frequency (2f 0 ) and create an open circuit between the first output terminal and the first output lead for signal energy at the second harmonic frequency (2f 0 ). 
     In another embodiment a packaged inverse class F radio frequency (RF) amplifier configured to operate at a fundamental frequency (f 0 ), the packaged inverse class F RF amplifier comprising: a package substrate; a first input lead coupled to the package substrate; a first output lead coupled to the package substrate; a first transistor die coupled to the package substrate, wherein the first transistor die includes a first transistor, a first input terminal, and a first output terminal, and wherein the first transistor includes an intrinsic output capacitance providing a first capacitance; a first output matching network coupled between the first output terminal and the first output lead, the first output matching network including: a first integrated passive device (IPD) die coupled to the package substrate, the first IPD die including a first integrated capacitive element providing a second capacitance, and a second integrated capacitive element providing a third capacitance; a first bondwire array connected between the first output terminal and the first output lead, the first bondwire array providing a first inductance; a second bondwire array directly connected between the first output lead and the first IPD die, the second bondwire array providing a second inductance; a third bondwire array connected between the first output terminal and the first IPD die, the third bondwire array providing a third inductance; a first 3f 0  resonant circuit configured to resonate at a third harmonic frequency (3f 0 ) and create a short circuit between the first output terminal and a ground for signal energy at the third harmonic frequency (3f 0 ), wherein the first 3f 0  resonant circuit includes the third inductance in series with and the third capacitance; a first 2f 0  resonant circuit configured to resonate at a second harmonic frequency (2f 0 ) and create a short circuit between the first output lead and the ground for signal energy at the second harmonic frequency (2f 0 ), wherein the first 2f 0  resonant circuit includes the second inductance in series with the second capacitance; and wherein when the first 2f 0  resonant circuit resonates, a second 2f 0  resonant circuit is realized, where the second 2f 0  resonant circuit includes the intrinsic output capacitance in parallel with the first inductance and in parallel with a combination of the third inductance in series with the third capacitance, and wherein the second 2f 0  resonant circuit is configured to resonate at the second harmonic frequency (2f 0 ) and create an open circuit between the first output terminal and the first output lead for signal energy at the second harmonic frequency (2f 0 ). 
     In another embodiment a method of manufacturing a radio frequency (RF) amplifier device is provided method of manufacturing an inverse class F radio frequency (RF) amplifier device, the method comprising the steps of: coupling a first input lead to a package substrate; coupling a first output lead to the package substrate; coupling a first transistor die to the package substrate, wherein the first transistor die includes a first transistor, a first input terminal, and a first output terminal, the first transistor including an intrinsic output capacitance providing a first capacitance; coupling an integrated passive device to the package substrate between the transistor die and the first output lead, wherein the integrated passive device includes one or more first integrally formed capacitors providing a second capacitance and one or more second integrally formed capacitors providing a third capacitance; and creating an output matching network coupled between the first output terminal and the first output lead by: connecting a first bondwire array between the first output terminal and the first output lead; connecting a second bondwire array between the first output lead and the integrated passive device, the second bondwire array providing a second inductance, such that a first 2f 0  resonant circuit that includes the second inductance and the second capacitance is created, wherein the first 2f 0  resonant circuit is configured to resonate at a second harmonic frequency (2f 0 ) and create an open circuit between the first output terminal and a ground for signal energy at the second harmonic frequency (2f 0 ); connecting a third bondwire array between the first output terminal and the integrated passive device, the third bondwire array providing a third inductance, such that a first 3f 0  resonant circuit that includes the third inductance and the third capacitance is created, wherein the first 3f 0  resonant circuit is configured to resonate at a third harmonic frequency (3f 0 ) and create a short circuit between the first output terminal and the ground for signal energy at the third harmonic frequency (3f 0 ); and wherein the first bondwire array provides a first inductance, and wherein the connecting of the first bondwire array between the first output terminal and the first output lead is such that when the first 2f 0  resonant circuit resonates a second 2f 0  resonant circuit is realized, where the second 2f 0  resonant circuit includes the intrinsic output capacitance, the first inductance, and the first 3f 0  resonant circuit, and wherein the second 2f 0  resonant circuit is configured to resonate at the second harmonic frequency (2f 0 ) and create an open circuit between the first output terminal and the first output lead for signal energy at the second harmonic frequency (2f 0 ). 
     The preceding detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description. 
     The connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in an embodiment of the subject matter. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms “first”, “second” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context. 
     As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, or the like, at which a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes may be realized by one physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even though received or output at a common node). 
     The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with, electrically or otherwise) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted subject matter. 
     While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application.