Patent Publication Number: US-2022231060-A1

Title: Image sensor

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0006813, filed on Jan. 18, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. 
     TECHNICAL FIELD 
     The present inventive concept relates to an image sensor, and more particularly, to an image sensor including a photodiode. 
     DISCUSSION OF RELATED ART 
     An image sensor may be a device configured to convert an optical image into an electric signal, and may have a plurality of pixels. Each of the pixels may include a photodiode region configured to receive incident light and convert the incident light into an electron-hole pair, therefore generating charges, and a pixel circuit may output a pixel signal using the charges generated in the photodiode region. 
     Due to the increased demand for image sensors, image sensors capable of embodying not only color images but also three-dimensional (3D) images are being developed. In addition, the image sensors may employ a global shutter scheme, in which all the pixels are simultaneously exposed to provide high quality imaging at high speeds. 
     SUMMARY 
     The present inventive concept provides an image sensor, which has enhanced shutter efficiency and may prevent noise from occurring. 
     According to an example embodiment of the present inventive concept, there is provided an image sensor including a semiconductor substrate having a first surface and a second surface. Transistors are disposed on the first surface of the semiconductor substrate. First and second lower pad electrodes are spaced apart from each other on a first interlayer insulating film, and the first interlayer insulating film covers the transistors. A mold insulating layer is disposed on the first and second lower pad electrodes. A first lower electrode is formed inside a first opening, and the first opening passes through the mold insulating layer. The first lower electrode is on the first lower pad electrode. A second lower electrode is formed inside a second opening, and the second opening passes through the mold insulating layer. The second lower electrode is on the second lower pad electrode. A dielectric film and an upper electrode are disposed on the first lower electrode and the second lower electrode. A first contact plug passes through the mold insulating layer and is connected to a top surface of the first lower pad electrode. A second contact plug passes through the mold insulating layer and is connected to a top surface of the second lower pad electrode. 
     According to an example embodiment of the present inventive concept, there is provided an image sensor including a semiconductor substrate having a first surface and a second surface. A photoelectric conversion region is formed in the semiconductor substrate. Transistors are disposed on the first surface of the semiconductor substrate. First and second lower pad electrodes are spaced apart from each other on a first interlayer insulating film that covers the transistors. Each of the first and second lower pad electrodes has a main pad portion having a rectangular horizontal cross-section and an extension protruding from the main pad portion. A plurality of first lower electrodes are disposed on the first lower pad electrode. A plurality of second lower electrodes are disposed on the second lower pad electrode. A dielectric film and an upper electrode are sequentially formed on a sidewall and a top surface of each of the plurality of first lower electrodes and a sidewall and a top surface of each of the plurality of second lower electrodes. A first contact plug is located on a top surface of the extension of the first lower pad electrode. A second contact plug is located on a top surface of the second lower pad electrode. 
     According to an example embodiment of the present inventive concept, there is provided an image sensor including a semiconductor substrate having a first surface and a second surface. A photoelectric conversion region is formed in the semiconductor substrate. Transistors are disposed on the first surface of the semiconductor substrate. First and second lower pad electrodes are spaced apart from each other on a first interlayer insulating film, and the first insulating film covers the transistors. A mold insulating layer is disposed on the first and second lower pad electrodes. A first lower electrode is formed inside a first opening, and the first opening passes through the mold insulating layer. The first lower electrode is on the first lower pad electrode and has a cylindrical shape. A second lower electrode is formed inside a second opening, and the second opening passes through the mold insulating layer. The second lower electrode is on the second lower pad electrode and has a cylindrical shape. A dielectric film and an upper electrode are formed on the first lower electrode and the second lower electrode. An upper pad electrode is disposed on the upper electrode and includes a doped semiconductor material. A second interlayer insulating film covers the mold insulating layer and the upper pad electrode. First and second contact plugs pass through the mold insulating layer and the second interlayer insulating film and are connected to top surfaces of the first and second lower pad electrodes, respectively. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Example embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG. 1  is a layout diagram of an image sensor according to an example embodiment of the present inventive concept; 
         FIGS. 2 and 3  are layout diagrams of an image sensor according to an example embodiment of the present inventive concept; 
         FIG. 4  is a cross-sectional view taken along line A 1 -A 1 ′ of  FIGS. 2 and 3 ; 
         FIG. 5  is a cross-sectional view taken along line A 2 -A 2 ′ of  FIGS. 2 and 3 ; 
         FIG. 6  is a cross-sectional view taken along line A 3 -A 3 ′ of  FIGS. 2 and 3 ; 
         FIG. 7  is an enlarged view of region CX 2  of  FIG. 4 ; 
         FIG. 8  is a circuit diagram of a pixel of an image sensor, according to an example embodiment of the present inventive concept; 
         FIG. 9  is a cross-sectional view of an image sensor according to an example embodiment of the present inventive concept; 
         FIG. 10  is a layout diagram of an image sensor according to an example embodiment of the present inventive concept; 
         FIG. 11  is a cross-sectional view of an image sensor according to an example embodiment of the present inventive concept; 
         FIG. 12  is an enlarged view of region CX 2  of  FIG. 11 ; 
         FIG. 13  is a schematic view of an image sensor according to an example embodiment of the present inventive concept; 
         FIGS. 14 to 22  are cross-sectional views of a method of manufacturing an image sensor, according to an example embodiment of the present inventive concept; and 
         FIG. 23  is a block diagram of a configuration of an image sensor according to an example embodiment of the present inventive concept. 
     
    
    
     Since the drawings in  FIGS. 1-23  are intended for illustrative purposes, the elements in the drawings are not necessarily drawn to scale. For example, some of the elements may be enlarged or exaggerated for clarity purpose. 
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. 
       FIG. 1  is a diagram illustrating the layout of an image sensor  100  according to an example embodiment of the present inventive concept. 
     Referring to  FIG. 1 , the image sensor  100  may include an active pixel region APR, a peripheral circuit region PCR, and a pad region PDR, which are formed in a semiconductor substrate  110 . 
     The active pixel region APR may be in a central portion of the semiconductor substrate  110 , and the peripheral circuit region PCR may be on both sides of the active pixel region APR. For example, the peripheral circuit region PCR may be on the right side and the left side of the active pixel region APR. A pad region PDR may be in an edge portion of the semiconductor substrate  110 . For example, the pad region PDR may be in the top edge portion and at the bottom edge portion in a view from above. 
     The active pixel region APR may include a plurality of pixels PX, and a plurality of photoelectric conversion regions (refer to PD in  FIG. 4 ) may be respectively in the plurality of pixels PX. In the active pixel region APR, the plurality of pixels PX may be arranged in a matrix form of rows and columns in a first direction parallel to a top surface of the semiconductor substrate  110  and a second direction parallel to the top surface of the semiconductor substrate  110 . The second direction may be perpendicular to the first direction. However, the present inventive concept is not limited thereto. For example, the plurality of pixels PX may be arranged in a pentile matrix shape, or a diamond shape. 
     Although the peripheral circuit region PCR is illustrated as being on both sides of the active pixel region APR in a view from above, the present inventive concept is not limited thereto, and the peripheral circuit region PCR may entirely surround the active pixel region APR. Alternatively, the peripheral circuit region PCR may surround three sides of the active pixel region APR. A conductive pad PAD may be in the pad region PDR. The conductive pad PAD may be on the edge portion of the semiconductor substrate  110 . 
       FIGS. 2 and 3  are diagrams illustrating the layout of an image sensor  100  according to an example embodiment of the present inventive concept. For example,  FIG. 2  is an enlarged layout diagram of region II of  FIG. 1  at a first vertical level LV 1 , and  FIG. 3  is an enlarged layout diagram of region II of  FIG. 1  at a second vertical level LV 2  (see  FIG. 4 ).  FIG. 4  is a cross-sectional view taken along line A 1 -A 1 ′ of  FIGS. 2 and 3 .  FIG. 5  is a cross-sectional view taken along line A 2 -A 2 ′ of  FIGS. 2 and 3 .  FIG. 6  is a cross-sectional view taken along line A 3 -A 3 ′ of  FIGS. 2 and 3 .  FIG. 7  is an enlarged view of region CX 2  of  FIG. 4 .  FIG. 8  is a circuit diagram of a pixel PX of the image sensor  100 , according to an example embodiment of the present inventive concept. 
     Referring to  FIGS. 2 to 8 , the image sensor  100  may include an image sensor of a global shutter type. During an operation of the image sensor of the global shutter type, charges may be simultaneously stored in each of pixels PX by simultaneously exposing all the pixels PX, and pixel signals may be sequentially output for each row. For example, because the image sensor of the global shutter type exposes all of the pixels PX at the same time, it may enable the capture of distortion-free images in comparison to a rolling shutter type. 
     The pixel PX of the image sensor  100  may include a photoelectric conversion region PD, a transfer transistor TG, a first floating diffusion region FD 1 , a reset transistor RG, a dual conversion gain (DCG) transistor DCG, a second floating diffusion region FD 2 , a first source follower transistor SF 1 , a pre-charge transistor PC, a sample transistor SAM, a first capacitor C 1 , a second capacitor C 2 , a calibration transistor CAL, a second source follower transistor SF 2 , a first selection transistor SEL 1 , a second selection transistor SEL 2 , a first node X, and a second node Y. 
     One pixel PX may be electrically insulated from a pixel PX adjacent thereto by a pixel device isolation film  130 . For example, each pixel PX may be surrounded by the pixel device isolation film  130 . First to fourth active regions AC 1 , AC 2 , AC 3 , and AC 4  may be defined in one pixel PX by a device isolation film STI. The photoelectric conversion region PD, the transfer transistor TG, the first floating diffusion region FD 1 , the first source follower transistor SF 1 , the pre-charge transistor PC, the second source follower transistor SF 2 , and the first selection transistor SEL 1  may be in the first active region AC 1 . The reset transistor RG, the DCG transistor DCG, the second floating diffusion region FD 2 , and the calibration transistor CAL may be in the second active region AC 2 . The sample transistor SAM may be in the third active region AC 3 , and the second selection transistor SEL 2  may be in the fourth active region AC 4 . 
     The photoelectric conversion region PD may be in the first active region AC 1  and include, for example, an N-type impurity region. Electric charge may be generated from the photoelectric conversion region PD by, for example, absorbing light. The first floating diffusion region FD 1  may be adjacent to the photoelectric conversion region PD in the first active region AC 1 . A transfer gate electrode  140  of the transfer transistor TG may be adjacent to the first floating diffusion region FD 1 . The photoelectric conversion region PD may be coupled with the transfer transistor TG that transfers the accumulated charge to the first floating diffusion region FD 1 . 
     A DCG gate electrode  151  of the DCG transistor DCG and a reset gate electrode  152  of the reset transistor RG may be on the second active region AC 2 , and the second floating diffusion region FD 2  may be in the second active region AC 2  between the DCG gate electrode  151  and the reset gate electrode  152 . The second floating diffusion region FD 2  may be shared between the reset transistor RG and the DCG transistor DCG. The second floating diffusion region FD 2  may serve as sources or drains of the reset transistor RG and the DCG transistor DCG. The first and second floating diffusion regions FD 1  and FD 2  may be regions which convert charges into voltages, and charges may be accumulatively stored in the first and second floating diffusion regions FD 1  and FD 2 . 
     In an example embodiment of the present inventive concept, the DCG transistor DCG may be connected between the first floating diffusion region FD 1  and the reset transistor RG. The reset transistor RG may be connected to the first floating diffusion region FD 1  via the DCG transistor DCG. Alternatively, the reset transistor RG may be connected between the first floating diffusion region FD 1  and the DCG transistor DCG. The reset transistor RG and the DCG transistor DCG may be connected in series to the first floating diffusion region FD 1 . Alternatively, the DCG transistor DCG may be omitted. 
     The pre-charge transistor PC may be connected to the first source follower transistor SF 1 , and a pre-charge gate electrode  153  of the pre-charge transistor PC may be on the first active region AC 1 . The sample transistor SAM may be connected between the first source follower transistor SF 1  and the pre-charge transistor PC, and a sample gate electrode  154  of the sample transistor SAM may be on the third active region AC 3 . The calibration transistor CAL may be connected to a third electrode C 22  of the second capacitor C 2 , and a calibration gate electrode  155  of the calibration transistor CAL may be on the second active region AC 2 . For example, the second capacitor C 2  may be between the calibration transistor CAL and the first capacitor C 1 , and by increasing the capacitance of the second capacitor C 2 , the noise generated when calibration transistor CAL is turned off may be reduced. 
     The first selection transistor SEL 1  may be connected to a second source follower transistor SF 2 . A first selection gate electrode  156  of the first selection transistor SEL 1  and a first source follower gate electrode  158  of the first source follower transistor SF 1  may be connected to the first floating diffusion region FD 1 . A fourth electrode C 24  of the second capacitor C 2  may be connected to the sample transistor SAM and a second electrode C 14  of the first capacitor C 1 . The second source follower gate electrode  159  of the second source follower transistor SF 2  may be connected to the calibration transistor CAL and the third electrode C 22  of the second capacitor C 2 . The first selection gate electrode  156  of the first selection transistor SEL 1 , the first source follower gate electrode  158  of the first source follower transistor SF 1 , the transfer gate electrode  140  of the transfer transistor TG, and the second source follower gate electrode  159  of the second source follower transistor SF 2  may be on the first active region AC 1 . 
     One end of each of the reset transistor RG, the first source follower transistor SF 1 , the second source follower transistor SF 2 , and the calibration transistor CAL may be connected to a power source Vpix. One end of each of the first source follower transistor SF 1  and the second source follower transistor SF 2  may be connected to the first power source Vpix 1 , and one end of each of the reset transistor RG and the calibration transistor CAL may be connected to a second power source Vpix 2 . One end of the pre-charge transistor PC may be connected to a pre-charge voltage Vpc. In an example embodiment of the present inventive concept, the pre-charge voltage Vpc may be a ground voltage. A first electrode C 12  of the first capacitor C 1  may be connected to the second power source Vpix 2 . One end of the first selection transistor SEL 1  and one end of the second selection transistor SEL 2  may be connected to a power line Vout. The second selection gate electrode  157  of the second selection transistor SEL 2  may be on the fourth active region AC 4 . 
     One end of the sample transistor SAM may be connected to the second electrode C 14  of the first capacitor C 1  and the fourth electrode C 24  of the second capacitor C 2  to constitute the first node X. Another end of the sample transistor SAM may be connected to one end of the second selection transistor SEL 2  and another end of the first source follower transistor SF 1 . Another end of the calibration transistor CAL may be connected to the third electrode C 22  of the second capacitor C 2  and the second source follower gate electrode  159  of the second source follower transistor SF 2  to constitute the second node Y. 
     Although  FIG. 2  illustrates an example layout of the pixel PX, in another case, the second selection transistor SEL 2  may be omitted, and a first power source Vpix 1  may be applied to both one end of the calibration transistor CAL and one end of the second source follower transistor SF 2 . 
     As exemplarily shown in  FIGS. 3 and 4 , the semiconductor substrate  110  may include a first surface  110 F 1  and a second surface  110 F 2 , which are opposite to each other. In an example embodiment of the present inventive concept, the semiconductor substrate  110  may include a P-type semiconductor substrate. For example, the semiconductor substrate  110  may include a P-type silicon (Si) substrate. In an example embodiment of the present inventive concept, the semiconductor substrate  110  may include a P-type bulk silicon (Si) substrate and a P-type or N-type epitaxial layer grown on the P-type bulk silicon (Si) substrate. In an example embodiment of the present inventive concept, the semiconductor substrate  110  may include an N-type bulk silicon (Si) substrate and a P-type or N-type epitaxial layer grown thereon. Alternatively, the semiconductor substrate  110  may include an organic plastic substrate. 
     A plurality of pixels PX may be arranged in a matrix form in the semiconductor substrate  110 . A plurality of photoelectric conversion regions PD may be respectively in the plurality of pixels PX. Each of the plurality of photoelectric conversion regions PD may include a photodiode region and a well region. 
     The pixel device isolation film  130  may be in the semiconductor substrate  110 , and the plurality of pixels PX may be defined by the pixel device isolation film  130 . For example, the pixel device isolation film  130  may be formed to surround each of the plurality of pixels PX. The pixel device isolation film  130  may be between one of the plurality of photoelectric conversion regions PD and the photoelectric conversion region PD adjacent thereto. One photoelectric conversion region PD may be physically and electrically isolated from another photoelectric conversion region PD adjacent thereto by the pixel device isolation film  130 . The pixel device isolation film  130  may be between the respective ones of the plurality of photoelectric conversion regions PD, which are arranged in a matrix form. The pixel device isolation film  130  may have a grid or mesh shape in a view from above. 
     The pixel device isolation film  130  may be formed inside a pixel trench  130 T, which passes through the semiconductor substrate  110  from the first surface  110 F 1  of the semiconductor substrate  110  to the second surface  110 F 2  thereof. The pixel device isolation film  130  may include an insulating layer  132  conformally formed on a sidewall of the pixel trench  130 T and a conductive layer  134  formed on the insulating layer  132  to fill the inside of the pixel trench  130 T. In an example embodiment of the present inventive concept, the insulating layer  132  may include a metal oxide such as, for example, hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), and/or tantalum oxide (Ta 2 O 5 ). In this case, the insulating layer  132  may serve as a negative fixed charge layer, but the present inventive concept is not limited thereto. In an example embodiment of the present inventive concept, the insulating layer  132  may include an insulating material such as, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), and/or silicon oxynitride (SiON). The conductive layer  134  may include at least one of, for example, doped polysilicon (p-Si), a metal, a metal silicide, a metal nitride, or a metal-containing film. 
     In an example embodiment of the present inventive concept, an upper insulating film  136  may be in a portion of the pixel trench  130 T, which is adjacent to the first surface  110 F 1  of the semiconductor substrate  110 . In an example embodiment of the present inventive concept, the formation of the upper insulating film  136  may include etching back portions of the insulating layer  132  and the conductive layer  134 , which are at an entrance of the pixel trench  130 T, and filling the remaining space of the pixel trench  130 T with an insulating material. For example, the pixel device isolation film  130  may have a structure configured to refract incident light obliquely incident on the photoelectric conversion region PD. Also, the pixel device isolation film  130  may limit or prevent the migration of photocharges generated in one pixel during light exposure to the neighboring pixels to enhance the image quality. 
       FIG. 4  illustrates an example in which the pixel device isolation film  130  extends from the first surface  110 F 1  of the semiconductor substrate  110  to the second surface 110 F 2  thereof and passes through the semiconductor substrate  110 . In another case, however, the pixel device isolation film  130  may extend from the second surface  110 F 2  of the semiconductor substrate  110  into the semiconductor substrate  110  and may not be exposed at the first surface  110 F 1  of the semiconductor substrate  110 . 
     As exemplarily shown in  FIG. 4 , the device isolation film STI defining the first to fourth active regions ACT 1  to ACT 4  may be formed in the semiconductor substrate  110  at the first surface  110 F 1 . The device isolation film STI may be in a device isolation trench (refer to  110 T in  FIG. 14 ), which is formed to have a predetermined depth from the first surface  110 F 1  of the semiconductor substrate  110 . For example, a depth at which the device isolation film STI is formed may be shallower than a depth at which the pixel device isolation film  130  is formed. The device isolation film STI may include an insulating material. The device isolation film STI may surround an upper sidewall of the pixel device isolation film  130  (e.g., a sidewall of the upper insulating film  136 ). 
     Transistors constituting pixel circuits may be on the first to fourth active regions ACT 1  to ACT 4 . The sources, drains and channels of these transistors may be formed in the first to fourth active regions ACT 1  to ACT 4  of the semiconductor substrate  110 . For example, as exemplarily shown in  FIG. 2 , the transfer gate electrode  140 , the DCG gate electrode  151 , the reset gate electrode  152 , the pre-charge gate electrode  153 , the sample gate electrode  154 , the calibration gate electrode  155 , the first and second selection gate electrodes  156  and  157 , and the first and second source follower gate electrodes  158  and  159  may be on the first surface  110 F 1  of the semiconductor substrate  110 . For example, the transistors constituting the pixel circuits may be disposed on the first surface  110 F 1  of the semiconductor substrate  110 . 
     The first floating diffusion region FD 1  may be in a portion of the first active region ACT 1 , for example, a portion of the first active region ACT 1  adjacent to the transfer gate electrode  140 . 
     As exemplarily shown in  FIG. 4 , the transfer gate electrode  140  may be in a transfer gate trench  140 T, which extends from the first surface  110 F 1  of the semiconductor substrate  110  into the semiconductor substrate  110 . The DCG gate electrode  151 , the reset gate electrode  152 , the pre-charge gate electrode  153 , the sample gate electrode  154 , the calibration gate electrode  155 , the first and second selection gate electrodes  156  and  157 , and the first and second source follower gate electrodes  158  and  159  may be collectively referred to as a planar gate electrode  150 . The planar gate electrode  150  may be on the first surface  110 F 1  of the semiconductor substrate  110 . In an example embodiment of the present inventive concept, the transfer gate electrode  140  and the planar gate electrode  150  may include at least one of, for example, doped polysilicon (p-Si), a metal, a metal silicide, a metal nitride, or a metal-containing film. 
     A transfer gate insulating layer  1401  may be on an inner wall of the transfer gate trench  140 T to surround a sidewall and a bottom surface of the transfer gate electrode  140 . A transfer gate spacer  140 S may be on a sidewall of the transfer gate electrode  140 . A gate insulating layer  1501  may be between the planar gate electrode  150  and the first surface  110 F 1  of the semiconductor substrate  110 . A gate spacer  150 S may be on a sidewall of the planar gate electrode  150 . 
     A first interlayer insulating film  160  may be on the first surface  110 F 1  of the semiconductor substrate  110  to cover the transfer gate electrode  140  and the planar gate electrode  150 . For example, the first interlayer insulating film  160  may be formed to cover the transistors constituting the pixel circuits. The first interlayer insulating film  160  may have a stack structure including a lower insulating layer  162  and an upper insulating layer  164  sequentially stacked on the first surface  110 F 1  of the semiconductor substrate  110 . The lower insulating layer  162  may cover the transfer gate electrode  140  and the planar gate electrode  150  on the first surface  110 F 1  of the semiconductor substrate  110 , and the upper insulating layer  164  may be on the lower insulating layer  162 . A first wiring layer M 1  may be on the lower insulating layer  162 , and the upper insulating layer  164  may cover the first wiring layer M 1 . In an example embodiment of the present inventive concept, an etch stop layer may be formed between the lower insulating layer  162  and the first surface  110 F 1  of the semiconductor substrate  110 . The etch stop layer may include a material having an etch selectivity with respect to that of the lower insulating layer  162 . 
     The first capacitor C 1  and the second capacitor C 2  may be on the first interlayer insulating film  160 . An upper pad electrode CUP may be shared by both the first capacitor C 1  and the second capacitor C 2 . 
     As exemplarily shown in  FIGS. 3 and 4 , a first lower pad electrode LP 1  and a second lower pad electrode LP 2  may be spaced apart from each other on the first interlayer insulating film  160 . The first lower pad electrode LP 1  and the second lower pad electrode LP 2  may be in parallel with the first surface  110 F 1  of the semiconductor substrate  110  in a central region of the pixel PX. For example, the first lower pad electrode LP 1  and the second lower pad electrode LP 2  may be formed at the same vertical level. The first and second lower pad electrodes LP 1  and LP 2  may occupy at least 50% of an area of the pixel PX (see  FIG. 3 ). A mold insulating layer  170  may be formed on the first interlayer insulating film  160  to cover the first lower pad electrode LP 1  and the second lower pad electrode LP 2 . The mold insulating layer  170  may include at least one of, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or silicon oxynitride (SiON). 
     A plurality of first lower electrodes LE 1  may be respectively inside a plurality of first openings  170 H 1  (see  FIGS. 7 and 17 ), which pass through the mold insulating layer  170  and expose a top surface of the first lower pad electrode LP 1 . A plurality of second lower electrodes LE 2  may be respectively inside a plurality of second openings  170 H 2  (see  FIGS. 7 and 17 ), which pass through the mold insulating layer  170  and expose a top surface of the second lower pad electrode LP 2 . As shown in  FIG. 3 , the first and second lower electrodes LE 1  and LE 2  may be arranged in a zigzag form along a first direction parallel to a top surface of the semiconductor substrate  110  and a second direction parallel to the top surface of the semiconductor substrate  110 . The second direction may be perpendicular to the first direction. However, the present inventive concept is not limited thereto. Each of the first lower electrode LE 1  and the second lower electrode LE 2  may have a cylindrical shape. 
     A dielectric film DL and an upper electrode CUE may be sequentially formed on the first lower electrode LE 1  and the second lower electrode LE 2 . The dielectric film DL may be conformally formed on top surfaces and inner walls of the first lower electrode LE 1  and the second lower electrode LE 2 , which have cylindrical shapes. The upper electrode CUE may be formed on the dielectric film DL to fill the remaining space of the plurality of first openings  170 H 1  and the plurality of second openings  170 H 2 . The first and second lower electrodes LE 1  and LE 2  and the upper electrode CUE may each include a film including a metal having a high melting point, such as, for example, cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W) or molybdenum (Mo), and/or a metal nitride film, such as, for example, a titanium nitride film (TiN), a titanium silicon nitride film (TiSiN), a titanium aluminum nitride film (TiAlN), a tantalum nitride film (TaN), a tantalum silicon nitride film (TaSiN), a tantalum aluminum nitride film (TaAlN), or a tungsten nitride film (WN). The dielectric film DL may include one or a combination of single films selected from combinations of a metal oxide, such as, for example, hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), or titanium oxide (TiO 2 ), and a dielectric material having a perovskite structure, such as, for example, strontium titanium oxide (SrTiO 3 , STO), barium strontium titanium oxide ((Ba,Sr)TiO 3 , BST), barium titanium oxide (BaTiO 3 ), lead zirconate titanate (Pb(Ti,Zr)O 3 , PZT), or lead lanthanum zirconium titanate ((Pb,La)(Zr,Ti)O 3 , PLZT). 
     An upper pad electrode CUP may be on the mold insulating layer  170  to cover an upper portion of the upper electrode CUE. The upper pad electrode CUP may vertically overlap the first and second lower pad electrodes LP 1  and LP 2 . The upper pad electrode CUP may include a conductive material different from that of the upper electrode CUE, or may include a doped semiconductor material. The upper pad electrode CUP may include, for example, doped polysilicon (p-Si), silicon germanium (SiGe), and/or a metal, such as, for example, tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta). 
     A second wiring layer M 2  may be spaced apart from the first and second lower pad electrodes LP 1  and LP 2  on the upper insulating layer  164  (see  FIGS. 3 and 6 ). For example, the second wiring layer M 2 , the first lower pad electrode LP 1  and the second lower pad electrode LP 2  may be formed at the same vertical level. For example, the second wiring layer M 2  may surround the first and second lower pad electrodes LP 1  and LP 2  in a view from above. Because the second wiring layer M 2  is on an edge of the pixel PX to surround the first and second lower pad electrodes LP 1  and LP 2 , the second wiring layer M 2  may be referred to as an edge wiring layer. 
     The first capacitor C 1  may include the first lower pad electrode LP 1 , the plurality of first lower electrodes LE 1 , the dielectric film DL, the upper electrode CUE, and the upper pad electrode CUP. The first lower pad electrode LP 1  and the plurality of first lower electrodes LE 1  may correspond to the first electrode C 12 , and the upper electrode CUE and the upper pad electrode CUP may correspond to the second electrode C 14 . The second capacitor C 2  may include the second lower pad electrode LP 2 , the plurality of second lower electrodes LE 2 , the dielectric film DL, the upper electrode CUE, and the upper pad electrode CUP. The second lower pad electrode LP 2  and the plurality of second lower electrodes LE 2  may correspond to the third electrode C 22 , and the upper electrode CUE and the upper pad electrode CUP may correspond to the fourth electrode C 24 . For example, the upper electrode CUE and the upper pad electrode CUP may be shared by both the second electrode C 14  of the first capacitor C 1  and the fourth electrode C 24  of the second capacitor C 2 . Because the first capacitor C 1  and the second capacitor C 2  respectively include the first and second lower electrodes LE 1  and LE 2  having cylindrical shapes, the capacitances of the first and second capacitors C 1  and C 2  may be increased, and the loss of charges and the generation of noise may be reduced during a global shutter operation, thereby enhancing shutter efficiency. 
     A second interlayer insulating film  172  may be on the mold insulating layer  170 , and may have a stack structure including first to fourth insulating layers  172 A,  172 B,  172 C, and  172 D sequentially stacked on the mold insulating layer  170 . For example, the first insulating layer  172 A may be on the mold insulating layer  170  to cover the upper pad electrode CUP. A third wiring layer M 3  may be on the first insulating layer  172 A, and the second insulating layer  172 B may be on the first insulating layer  172 A to cover the third wiring layer M 3 . A fourth wiring layer M 4  may be on the second insulating layer  172 B, and the third insulating layer  172 C may be on the second insulating layer  172 B to cover the fourth wiring layer M 4 . A fifth wiring layer M 5  may be on the third insulating layer  172 C, and the fourth insulating layer  172 D may be on the third insulating layer  172 C to cover the fifth wiring layer M 5 . 
     The first to fifth wiring layers M 1 , M 2 , M 3 , M 4 , and M 5  may include at least one of, for example, doped or undoped polysilicon (p-Si), a metal, a metal silicide, a metal nitride, or a metal-containing film. For example, the first to fifth wiring layers M 1 , M 2 , M 3 , M 4 , and M 5  may each include, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten silicide (WSi 2 ), titanium silicide (TiSi 2 ), tungsten nitride (WN), titanium nitride (TiN), and/or doped polysilicon (p-Si). The first to fourth insulating layers  172 A,  172 B,  172 C, and  172 D may each include an insulating material, such as, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or silicon oxynitride (SiON). 
     A first lower contact plug LCP 1  may pass through the lower insulating layer  162  of the first interlayer insulating film  160  and be connected to the first wiring layer M 1 . The first lower contact plug LCP 1  may be electrically connected to the first wiring layer M 1  and an impurity region (a source/drain region) of a transistor located within one of the first to fourth active regions AC 1  to AC 4 . A second lower contact plug LCP 2  (see  FIG. 6 ) may pass through the upper insulating layer  164  of the first interlayer insulating film  160  and be connected to the second wiring layer M 2  and the first wiring layer M 1 . A first upper contact plug UCP 1  may be on the upper pad electrode CUP to pass through the first insulating layer  172 A, and the first upper contact plug UCP 1  may be electrically connected to the third wiring layer M 3  and the upper pad electrode CUP. In addition, a second upper contact plug UCP 2  may pass through the second insulating layer  172 B and connect the third wiring layer M 3  to the fourth wiring layer M 4 . A third upper contact plug UCP 3  may pass through the third insulating layer  172 C and connect the fourth wiring layer M 4  to the fifth wiring layer M 5 . A third contact plug CP 3  (see  FIG. 6 ) may pass through the mold insulating layer  170  and the first insulating layer  172 A and electrically connect the second wiring layer M 2  (or the edge wiring layer) to the third wiring layer M 3 . 
     As exemplarily shown in  FIG. 3 , the first lower pad electrode LP 1  may include a main pad portion MP 1  and an extension EX 1  protruding from the main pad portion MP 1 . The main pad portion MP 1  may have a rectangular horizontal cross-section. The second lower pad electrode LP 2  may include a main pad portion MP 2  and an extension EX 2  protruding from the main pad portion MP 2 . The main pad portion MP 2  may have a rectangular horizontal cross-section. 
     In an example embodiment of the present inventive concept, a first contact plug CP 1  may be on a top surface of the extension EX 1  of the first lower pad electrode LP 1  (see  FIGS. 3 and 5 ). The first contact plug CP 1  may pass through the mold insulating layer  170  and the second interlayer insulating film  172  (e.g., the first insulating layer  172 A of the second interlayer insulating film  172 ) and be connected to the third wiring layer M 3 . The first contact plug CP 1  may be electrically connected to the third wiring layer M 3  and the first lower pad electrode LP 1 . A bottom surface of the first lower pad electrode LP 1  may be entirely covered by the first interlayer insulating film  160 . For example, the bottom surface of the first lower pad electrode LP 1  may be entirely in contact with the first interlayer insulating film  160 . 
     A second contact plug CP 2  may be on a top surface of the extension EX 2  of the second lower pad electrode LP 2  (see  FIGS. 3 and 6 ). The second contact plug CP 2  may pass through the mold insulating layer  170  and the second interlayer insulating film  172  (e.g., the first insulating layer  172 A of the second interlayer insulating film  172 ) and be connected to the third wiring layer M 3 . The second contact plug CP 2  may be electrically connected to the third wiring layer M 3  and the second lower pad electrode LP 2 . A bottom surface of the second lower pad electrode LP 2  may be entirely covered by the first interlayer insulating film  160 . For example, the bottom surface of the second lower pad electrode LP 2  may be entirely in contact with the first interlayer insulating film  160 . For example, the first wiring layer M 1  may be located at a vertical level lower than that of the first and second lower pad electrodes LP 1  and LP 2 , and the third wiring layer M 3  may be located at a vertical level higher than that of the first and second lower pad electrodes LP 1  and LP 2 . The second lower pad electrode LP 2  is not directly connected to the first wiring layer M 1  through the second contact plug CP 2  or any other contact plug, and the second lower pad electrode LP 2  is connected to the third wiring layer M 3  through the second contact plug CP 2 . 
     As shown in  FIG. 6 , the second lower pad electrode LP 2  may be connected to the third wiring layer M 3  through the second contact plug CP 2  located on the top surface of the extension EX 2  and be connected to an impurity region N+ of the calibration transistor CAL through the third contact plug CP 3  connected to the third wiring layer M 3 , the second wiring layer M 2 , the second lower contact plug LCP 2 , the first wiring layer M 1 , and the first lower contact plug LCP 1 . That is, as shown in  FIG. 6 , the second lower pad electrode LP 2  may be connected to the impurity region N+ of the calibration transistor CAL along a bypass electrical path C 2 _DP. 
     Since the second lower pad electrode LP 2  may be electrically connected to the impurity region N+ of the calibration transistor CAL along the bypass electrical path C 2 _DP, which is formed by the second contact plug CP 2 , the third wiring layer M 3 , the third contact plug CP 3 , the second wiring layer M 2 , the second lower contact plug LCP 2 , the first wiring layer M 1 , and the first lower contact plug LCP 1 , damage may be prevented from being built up in the semiconductor substrate  110  due to plasma used in a process of forming the first capacitor C 1  and the second capacitor C 2 . Because the second contact plug CP 2  is formed after the process of forming the first capacitor C 1  and the second capacitor C 2 , the first capacitor C 1  and the second capacitor C 2  may not be electrically connected to the impurity region N+ of the calibration transistor CAL during the process of forming the first capacitor C 1  and the second capacitor C 2 . 
     As shown in  FIG. 4 , a rear insulating layer  182  may be formed on the second surface  110 F 2  of the semiconductor substrate  110 . For example, the rear insulating layer  182  may be on substantially the entire area of the second surface  110 F 2  of the semiconductor substrate  110 . The rear insulating layer  182  may be in contact with a top surface of the pixel device isolation film  130  at a level the same as that of the second surface  110 F 2  of the semiconductor substrate  110 . In an example embodiment of the present inventive concept, the rear insulating layer  182  may include a metal oxide, such as, for example, hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), and/or tantalum oxide (Ta 2 O 5 ). In an example embodiment of the present inventive concept, the rear insulating layer  182  may include an insulating material, such as, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), and/or a low-k dielectric material. 
     A passivation layer  184  may be on the rear insulating layer  182 , and a color filter  186  and a microlens  188  may be on the passivation layer  184 . Light may be incident on the second surface  110 F 2  of the semiconductor substrate  110  through the microlens  188 , the color filter  186 , the passivation layer  184  and the rear insulating layer  182 . Optionally, a support substrate may be further located on the first surface  110 F 1  of the semiconductor substrate  110 . 
     According to the above-described example embodiments of the present inventive concept, the image sensor  100  may be a global-shutter-type image sensor having an increased capacitance, and shutter efficiency may be increased during a global shutter operation. For example, the capacitances of the first and second capacitors C 1  and C 2  may be increased when the first capacitor C 1  and the second capacitor C 2  respectively include the first and second lower electrodes LE 1  and LE 2  having cylindrical shapes. In addition, because the second lower pad electrode LP 2  is connected to a storage node (e.g., the impurity region N+ of the calibration transistor CAL) along the bypass electrical path C 2 _DP, plasma damage may be prevented from being built up in the storage node of the semiconductor substrate  110  during the process of forming the first and second capacitors C 1  and C 2 . For example, the bypass electrical path C 2 _DP may be formed after the process of forming the first and second capacitors C 1  and C 2 . Accordingly, white spots may be prevented from occurring due to a junction leakage current, and thus, the image sensor  100  may be prevented from causing noise. 
       FIG. 9  is a cross-sectional view of an image sensor  100 A according to an example embodiment of the present inventive concept. In  FIG. 9 , the same reference numerals are used to denote the same elements as in  FIGS. 1 to 8 . 
     Referring to  FIG. 9 , a second lower pad electrode LP 2  may be connected to one of third wiring layers M 3  through a second contact plug CP 2  located on a top surface of an extension EX 2 , and may be electrically connected to an impurity region N+ of a calibration transistor CAL through a second upper contact plug UCP 2  connected to the third wiring layer M 3 , a fourth wiring layer M 4  connected to the second upper contact plug UCP 2 , an other second upper contact plug UCP 2  connected to the fourth wiring layer M 4 , an other third wiring layer M 3  connected to the other second upper contact plug UCP 2 , a third contact plug CP 3  connected to the other third wiring layer M 3 , a second wiring layer M 2  (or an edge wiring layer) connected to the third contact plug CP 3 , a second lower contact plug LCP 2  connected to the second wiring layer M 2 , and a first wiring layer M 1  and a first lower contact plug LCP 1 , which are connected to the second lower contact plug LCP 2 . That is, as shown in  FIG. 9 , the second lower pad electrode LP 2  may be connected to the impurity region N+ of the calibration transistor CAL along a bypass electrical path C 2 _DP. The bypass electrical path C 2 _DP of  FIG. 9  adds two second upper contact plugs UCP 2  and the fourth wiring layer M 4  to connect two separated third wiring layers in the path in comparison to the bypass electrical path C 2 _DP of  FIG. 6 . 
     Since the second lower pad electrode LP 2  may be connected to the impurity region N+ of the calibration transistor CAL along the bypass electrical path C 2 _DP, which is formed by the second contact plug CP 2 , the third wiring layer M 3 , the second upper contact plug UCP 2 , the fourth wiring layer M 4 , the third contact plug CP 3 , the second wiring layer M 2 , the second lower contact plug LCP 2 , the first wiring layer M 1 , and the first lower contact plug LCP 1 , damage may be prevented from being built up in a semiconductor substrate  110  due to plasma used in a process of forming a first capacitor C 1  and a second capacitor C 2 . For example, the bypass electrical path C 2 _DP of  FIG. 9  may be formed after the process of forming the first and second capacitors C 1  and C 2 . Accordingly, plasma damage may be prevented from being built up in the semiconductor substrate  110 , especially, in an impurity region N+ of a calibration transistor CAL during the process of forming the first capacitor C 1  and the second capacitor C 2 . 
       FIG. 10  is a diagram illustrating the layout of an image sensor  100 B according to an example embodiment of the present inventive concept. In  FIG. 10 , the same reference numerals are used to denote the same elements as in  FIGS. 1 to 9 . 
     Referring to  FIG. 10 , a first lower pad electrode LP 1  may include a main pad portion MP 1  having a rectangular shape with a long side and a short side and an extension EX 1  that protrudes outward from the short side of the main pad portion MP 1 . A second lower pad electrode LP 2  may include a main pad portion MP 2  having a rectangular shape with a long side and a short side and an extension EX 2  that protrudes outward from the short side of the main pad portion MP 2 . For example, the extension EX 1  of the first lower pad electrode LP 1  and the extension EX 2  of the second lower pad electrode LP 2  may be at positions vertically overlapping a pixel device isolation film  130 . The second lower pad electrode LP 2  described here with reference to  FIG. 10  is different from the second lower pad electrode LP 2  illustrated in  FIG. 3 . In  FIG. 3 , the extension EX 2  of the second lower pad electrode LP 2  protrudes outward from the long side of the main pad portion MP 2 . 
       FIG. 10  illustrates an example in which the extension EX 1  of the first lower pad electrode LP 1  and the extension EX 2  of the second lower pad electrode LP 2 , which are included in one pixel PX, protrude in the same direction. In another case, however, the extension EX 1  of the first lower pad electrode LP 1  may protrude in an upward direction of  FIG. 10 , and the extension EX 2  of the second lower pad electrode LP 2  may protrude in a downward direction of  FIG. 10 . 
       FIG. 11  is a cross-sectional view of an image sensor  100 C according to an example embodiment of the present inventive concept, and  FIG. 12  is an enlarged view of region CX 2  of  FIG. 11 . In  FIGS. 11 and 12 , the same reference numerals are used to denote the same elements as in  FIGS. 1 to 10 . 
     Referring to  FIGS. 11 and 12 , the first capacitor C 1  may include a first lower pad electrode LP 1 , a plurality of first lower electrodes LE 1 , a first dielectric film DL 1 , a first upper electrode UE 1 , and a first upper pad electrode UP 1 , and the second capacitor C 2  may include a second lower pad electrode LP 2 , a plurality of second lower electrodes LE 2 , a second dielectric film DL 2 , a second upper electrode UE 2 , and a second upper pad electrode UP 2 . 
     Each of the plurality of first lower electrodes LE 1  may have a pillar shape and extend in a vertical direction, and the first dielectric film DL 1  may conformally cover a top surface and a sidewall of each of the plurality of first lower electrodes LE 1 . The first upper electrode UE 1  may cover all of the plurality of first lower electrodes LE 1  on the first dielectric film DL 1 . The first upper pad electrode UP 1  may be in a flat plate shape on a top surface of the first upper electrode UE 1 . The first upper electrode UE 1  and the first upper pad electrode UP 1  may correspond to the second electrode C 14  of the first capacitor C 1 . 
     Each of the plurality of second lower electrodes LE 2  may have a pillar shape and extend in the vertical direction, and the second dielectric film DL 2  may conformally cover a top surface and a sidewall of each of the second lower electrodes LE 2 . The second upper electrode UE 2  may cover all of the plurality of second lower electrodes LE 2  on the second dielectric film DL 2 . The second upper pad electrode UP 2  may be in a flat plate shape on a top surface of the second upper electrode UE 2 . The second upper electrode UE 2  and the second upper pad electrode UP 2  may correspond to the fourth electrode C 24  of the second capacitor C 2 . Although the first upper pad electrode UP 1  and the second upper pad electrode UP 2  are spaced apart from each other, the first upper pad electrode UP 1  and the second upper pad electrode UP 2  may be connected to the same node (e.g., the first node X shown in  FIG. 8 ) each by a first upper contact plug UCP 1 . For example, the second electrode C 14  of the first capacitor C 1  and the fourth electrode C 24  of the second capacitor C 2  may be connected to the same node (e.g., the first node X shown in  FIG. 8 ). 
     A mold insulating layer (refer to  170  in  FIG. 4 ) may be omitted from the image sensor  100 C shown in  FIGS. 11 and 12 . The first capacitor C 1  and the second capacitor C 2  may be covered by a first insulating layer  172 A of a second interlayer insulating film  172 . A first contact plug (refer to CP 1  in  FIG. 5 ) and a second contact plug CP 2  may pass through the first insulating layer  172 A. 
       FIG. 13  is a schematic view of an image sensor  200  according to an example embodiment of the present inventive concept. 
     Referring to  FIG. 13 , the image sensor  200  may be a stack-type image sensor including a first chip CHIP 1  and a second chip CHIP 2 , in which the first chip CHIP 1  may be stacked on the second chip CHIP 2  in a vertical direction. The first chip CHIP 1  may include an active pixel region APR and a first pad region PDR 1 , and the second chip CHIP 2  may include a peripheral circuit region PCR and a second pad region PDR 2 . 
     A plurality of first pads PAD 1  of the first pad region PDR 1  may transmit and receive electric signals to and from an external device. The peripheral circuit region PCR may include a logic circuit block LC and a plurality of CMOS transistors. The peripheral circuit region PCR may provide a constant signal to each active pixel PX of the active pixel region APR or control an output signal of each active pixel PX. The first pads PAD 1  of the first pad region PDR 1  may be electrically connected to second pads PAD 2  of the second pad region PDR 2  by a via structure VS. 
       FIGS. 14 to 22  are cross-sectional views of a method of manufacturing an image sensor  100 , according to an example embodiment of the present inventive concept. In  FIGS. 14 to 22 , the same reference numerals are used to denote the same elements as in  FIGS. 1 to 13 . 
     Referring to  FIG. 14 , a semiconductor substrate  110  including a first surface  110 F 1  and a second surface  110 F 2 , which are opposite each other, may be prepared. A photoelectric conversion region PD may be formed by performing an ion implantation process on the first surface  110 F 1  of the semiconductor substrate  110 . Thus, the photoelectric conversion region PD may be formed in the semiconductor substrate  110 . For example, a photoelectric conversion region PD may include a photodiode region and a well region. The photodiode region may be doped with N-type impurities, and the well region may be doped with P-type impurities. 
     Next, a first mask pattern may be formed on the first surface  110 F 1  of the semiconductor substrate  110 , and a device isolation trench  110 T may be formed in the semiconductor substrate  110  by using the first mask pattern as an etch mask. For example, the device isolation trench  110 T may be formed by removing a portion of the semiconductor substrate  110  through an etching process. 
     Subsequently, the device isolation trench  110 T may be filled with an insulating material, and thus, a device isolation film STI may be formed inside the device isolation trench  110 T. The device isolation film STI may be formed to cover the first mask pattern. 
     Thereafter, a second mask pattern may be formed on the first surface  110 F 1  of the semiconductor substrate  110 , and pixel trenches  130 T may be formed in the semiconductor substrate  110  by using the second mask pattern as an etch mask. The pixel trenches  130 T may have a predetermined depth from the first surface  110 F 1  of the semiconductor substrate  110  and be arranged in a matrix form in a view from above. For example, a depth of the pixel trenches  130 T may be larger than a depth of the device isolation trench  110 T. 
     An insulating layer  132  may be then conformally formed on the first surface  110 F 1  of the semiconductor substrate  110  and an inner wall of the pixel trench  130 T by using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. Thereafter, a conductive layer  134  may be formed on the insulating layer  132  to fill an inner wall of the pixel trench  130 T. 
     A portion of the insulating layer  132  and a portion of the conductive layer  134  may be removed so that the first surface  110 F 1  of the semiconductor substrate  110  may be exposed. Afterwards, a portion of the insulating layer  132  and a portion of the conductive layer  134 , which are in an upper portion of the pixel trench  130 T, may be further removed using an etchback process, and a vacant space of the pixel trench  130 T may be filled with an insulating material, and thus, an upper insulating film  136  may be formed on the insulating layer  132  and the conductive layer  134  in the upper portion of the pixel trench  130 T. 
     Referring to  FIG. 15 , a mask pattern may be formed on the first surface  110 F 1  of the semiconductor substrate  110 , and a portion of the semiconductor substrate  110  may be removed using the mask pattern as an etch mask, thereby forming a transfer gate trench  140 T. 
     A transfer gate electrode  140  and a planar gate electrode  150  may be formed on the first surface  110 F 1  of the semiconductor substrate  110  and an inner wall of the transfer gate trench  140 T. In an example embodiment of the present inventive concept, before the transfer gate electrode  140  and the planar gate electrode  150  are formed, a transfer gate insulating layer  1401  may be formed on the inner wall of the transfer gate trench  140 T and a gate insulating layer  1501  may be formed on the first surface  110 F 1  under the planar gate electrode  150 . Next, a transfer gate spacer  140 S and a gate spacer  150 S may be further respectively formed on a sidewall of the transfer gate electrode  140  and a sidewall of the planar gate electrode  150 . 
     Afterwards, an ion implantation process may be performed on a partial region of the first surface  110 F 1  of the semiconductor substrate  110 , thereby forming an impurity region in the semiconductor substrate  110 . 
     Referring to  FIG. 16 , a lower insulating layer  162  may be formed on the first surface  110 F 1  of the semiconductor substrate  110 , and a first lower contact hole LCPH may be formed to pass through the lower insulating layer  162 . Afterwards, the first lower contact hole LCPH may be filled with a conductive material to form a first lower contact plug LCP 1 . A first wiring layer M 1  may be formed on the lower insulating layer  162 , and an upper insulating layer  164  may be formed on the lower insulating layer  162  to cover the first wiring layer M 1 . Thereafter, a second lower contact hole may be formed to pass through the upper insulating layer  164 . The second lower contact hole may be filled with a conductive material to form a second lower contact plug (refer to LCP 2  in  FIG. 6 ). 
     Subsequently, a conductive layer may be formed on the upper insulating layer  164  and patterned to form a first lower pad electrode LP 1 , a second lower pad electrode LP 2 , and a second wiring layer M 2  (see  FIG. 6 ). The first lower pad electrode LP 1 , the second lower pad electrode LP 2 , and the second wiring layer M 2  may be formed using the same material. For example, the second wiring layer M 2  (or an edge wiring layer) may be disposed on the second lower contact plug (refer to LCP 2  in  FIG. 6 ) and located at a vertical level the same as that of the first and second lower pad electrodes LP 1  and LP 2 . The second lower pad electrode LP 2  may not be in direct contact with the second lower contact plug (refer to LCP 2  in  FIG. 6 ). As shown in  FIG. 3 , in a view from above, the first lower pad electrode LP 1  may include a main pad portion MP 1  and an extension EX 1 , and the second lower pad electrode LP 2  may include a main pad portion MP 2  and an extension EX 2 . 
     Referring to  FIG. 17 , a mold insulating layer  170  may be formed on the first interlayer insulating film  160 . Next, a mask pattern may be formed on the mold insulating layer  170 , and a plurality of first openings  170 H 1  and a plurality of second openings  170 H 2  may be formed in the mold insulating layer  170  using the mask pattern as an etch mask. The first lower pad electrode LP 1  may be exposed at bottom portions of the plurality of first openings  170 H 1 , and the second lower pad electrode LP 2  may be exposed at bottom portions of the plurality of second openings  170 H 2 . 
     Referring to  FIG. 18 , a preliminary lower electrode layer may be formed on the mold insulating layer  170  to conformally cover inner walls of the plurality of first openings  170 H 1  and inner walls of the plurality of second openings  170 H 2 . Portions of the preliminary lower electrode layer covering a top surface of the mold insulating layer  170  may be removed, and thus, a plurality of first lower electrodes LE 1  may be formed on the inner walls of the plurality of first openings  170 H 1  and a plurality of second lower electrodes LE 2  may be formed on the inner walls of the plurality of second openings  170 H 2 . Each of the first lower electrode LE 1  and the second lower electrode LE 2  may have a cylindrical shape. 
     A dielectric film DL and an upper electrode CUE may be formed on the mold insulating layer  170  to conformally cover the inner walls of the plurality of first openings  170 H 1  and the inner walls of the plurality of second openings  170 H 2 . A first capacitor C 1  and a second capacitor C 2  may be formed by forming an upper pad electrode CUP on the upper electrode CUE. Since the first capacitor C 1  and the second capacitor C 2  respectively include the first and second lower electrodes LE 1  and LE 2  having cylindrical shapes, the capacitances of the first and second capacitors C 1  and C 2  may be increased. For example, the upper pad electrode CUP may include a semiconductor material (e.g., silicon germanium (SiGe)) doped with impurities. A process of implanting impurity ions into the upper pad electrode CUP may be performed during the process of forming the upper pad electrode CUP. 
     In an example embodiment of the present inventive concept, a plasma-related process may be used in the process of forming the first capacitor C 1  and the second capacitor C 2 . For example, a plasma-based etching process may be used in a process of etching the mold insulating layer  170 . Even when the plasma-based etching process is performed, because the first and second lower pad electrodes LP 1  and LP 2  remain electrically insulated from the semiconductor substrate  110 , plasma damage may be prevented from being built up in the semiconductor substrate  110 , especially, in an impurity region N+(refer to  FIG. 6 ) of a calibration transistor CAL. For example, the first and second lower pad electrodes LP 1  and LP 2  may not be electrically connected to a storage node (or the impurity region N+ of a calibration transistor CAL) during the process of forming the first capacitor C 1  and the second capacitor C 2 . Accordingly, plasma damage may be prevented from being built up in the storage node (or the impurity region N+ of the calibration transistor CAL). 
     Referring to  FIG. 19 , a first insulating layer  172 A may be formed on the mold insulating layer  170  and the upper pad electrode CUP. Subsequently, an upper contact hole UCPH passing through the first insulating layer  172 A and a contact hole CPH passing through the first insulating layer  172 A and the mold insulating layer  170  may be formed. For example, the contact hole CPH may expose a top surface of the second lower pad electrode LP 2 , a top surface of the first lower pad electrode LP 1 , and a top surface of a second wiring layer (refer to M 2  in  FIG. 6 ). 
     Referring to  FIG. 20 , the upper contact hole UCPH and the contact hole CPH may be filled with a conductive layer, and an upper portion of the conductive layer may be planarized so that a top surface of the first insulating layer  172 A may be exposed. Thus, a first upper contact plug UCP 1  may be formed in the upper contact hole UCPH and first to third contact plugs CP 1 , CP 2 , and CP 3  (see  FIGS. 5 and 6 ) may be formed in the contact holes CPH. 
     Referring to  FIG. 21 , a process of forming a conductive layer on the first insulating layer  172 A, a process of patterning the conductive layer, and a process of forming an insulating layer to cover the patterned conductive layer may be repeatedly performed, thereby forming a second interlayer insulating film  172 , which includes the first to fourth insulating layers  172 A,  172 B,  172 C, and  172 D, and third to fifth wiring layers M 3 , M 4 , and M 5 . For example, the third wiring layer M 3  may be formed on the first insulating layer  172 A and covered by the second insulating layer  172 B, the fourth wiring layer M 4  may be formed on the second insulating layer  172 B and covered by the third insulating layer  172 C, and the fifth wiring layer M 5  may be formed on the third insulating layer  172 C and covered by the fourth insulating layer  172 D. A first upper contact plug UCP 1  may be formed on the upper pad electrode CUP to pass through the first insulating layer  172 A to electrically connect the upper pad electrode CUP and the third wiring layer M 3 . A second upper contact plug UCP 2  may pass through the second insulating layer  172 B and connect the third wiring layer M 3  to the fourth wiring layer M 4 . A third upper contact plug UCP 3  may pass through the third insulating layer  172 C and connect the fourth wiring layer M 4  to the fifth wiring layer M 5 . 
     Referring to  FIG. 22 , a support substrate may be adhered to a first surface  110 F 1  of the semiconductor substrate  110  including the above described capacitor structures and wiring layers, and the semiconductor substrate  110  may be reversed so that a second surface  110 F 2  of the semiconductor substrate  110  may face upward. 
     Subsequently, a planarization process, such as a chemical mechanical polishing (CMP) process or an etchback process, may be performed so that a top surface of a pixel device isolation film  130  (e.g., an end portion of the pixel device isolation film  130  adjacent to the second surface  110 F 2  of the semiconductor substrate  110 ) may be exposed, and thus, a portion of the semiconductor substrate  110  may be removed from the second surface  110 F 2  of the semiconductor substrate  110 . 
     Afterwards, a rear insulating layer  182  may be formed on the second surface  110 F 2  of the semiconductor substrate  110 . The rear insulating layer  182  may be formed over the entire area of the second surface  110 F 2  of the semiconductor substrate  110  to cover the pixel device isolation layer  130 . 
     Subsequently, a passivation layer  184  may be formed on the rear insulating layer  182 , and a color filter  186  and a microlens  188  may be formed on the passivation layer  184 . 
     The manufacture of the image sensor  100  may be completed due to the above-described processes. 
     According to an example embodiment of the present inventive concept, even when a plasma-related process is used in a process of forming the first capacitor C 1  and the second capacitor C 2 , because the first and second lower pad electrodes LP 1  and LP 2  remain electrically insulated from the semiconductor substrate  110 , plasma damage may not be built up in the semiconductor substrate  110 , especially, in the impurity region N+ of the calibration transistor CAL. Accordingly, white spots may be prevented from occurring due to a junction leakage current, and thus, the image sensor  100  may be prevented from causing noise. 
       FIG. 23  is a block diagram of a configuration of an image sensor  1100  according to an example embodiment of the present inventive concept. 
     Referring to  FIG. 23 , the image sensor  1100  may include a pixel array  1110 , a controller  1130 , a row driver  1120 , and a pixel signal processor  1140 . The image sensor  1100  may include at least one of the image sensors  100 ,  100 A,  100 B,  100 C, or  200  described above with reference to  FIGS. 1 to 13 . 
     The pixel array  1110  may include a plurality of unit pixels arranged two-dimensionally, and each of the unit pixels may include a photoelectric conversion element. The photoelectric conversion element may absorb light, generate charges, and provide an electric signal (or an output voltage) corresponding to the generated charges to the pixel signal processor  1140  through a vertical signal line. The unit pixels included in the pixel array  1110  may provide one output voltage at a time in units of rows. Thus, unit pixels in one row of the pixel array  1110  may be simultaneously activated in response to a selection signal output by the row driver  1120 . For example, the unit pixels included in the pixel array  1110  may be driven by a plurality of drive signals such as, for example, selection signals, reset signals, and charge transfer signals from the row driver  1120 . Unit pixels in a selected row may provide an output voltage corresponding to absorbed light to an output line of a column corresponding thereto. 
     The controller  1130  may control the row driver  1120  such that the pixel array  1110  absorbs light to accumulate charges or temporarily stores the accumulated charges and outputs an electric signal corresponding to the stored charges to the outside of the pixel array  1110 . In addition, the controller  1130  may control the pixel signal processor  1140  to measure the output voltage provided by the pixel array  1110 . 
     The pixel signal processor  1140  may include a correlated double sampler (CDS)  1142 , an analog-to-digital converter (ADC)  1144 , and a buffer  1146 . The output voltage converted from an optical signal (absorbed light) by the unit pixels included in the pixel array  1110  may be provided to the CDS  1142 . The CDS  1142  may sample and hold the output voltage provided by the pixel array  1110 . The CDS  1142  may double sample a specific noise level and a level corresponding to the generated output voltage and output a difference level corresponding to a difference between the noise level and the level corresponding to the generated output voltage. Furthermore, the CDS  1142  may receive ramp signals generated by a ramp signal generator  1148 , compare the ramp signals, and output a comparison result. 
     The ADC  1144  may convert an analog signal corresponding to a level received from the CDS  1142  into a digital signal. The buffer  1146  may latch the digital signal, and latched signals may be sequentially output to the outside of the image sensor  1100  and transmitted to an image processor. 
     While the present inventive concept has been particularly shown and described with reference to the example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the appended claims.