Patent Publication Number: US-7592797-B2

Title: Semiconductor device and electronics device

Description:
REFERENCE TO RELATED APPLICATION 
     This Applications is a Continuation Application and claims the benefits of priority from U.S. patent application Ser. No. 11/434,736, now U.S. Pat. No. 7,358,718, filed May 17, 2006, which also claims the benefit of priority from Japanese patent Application No. 2006-040379, filed on Feb. 17, 2006, of which the entirety is incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a semiconductor device and an electronics device composed of the same. 
     2. Description of the Related Art 
     In recent years, portable electronics devices (a mobile phone, etc.) driven with a battery have been popular. There has been a strong demand for semiconductor devices mounted in the portable electronics devices to operate at a high-speed with low power consumption in order to realize advanced functions of the electronics devices and a long-term use of a battery. 
     Furthermore, along with the miniaturization of the structure of semiconductor devices, a power supply voltage applied to the semiconductor devices has been lowered. A small difference between the power supply voltage and a threshold voltage of the transistor due to low power supply voltage makes it difficult for the transistor to turn on, thereby decreasing the operating speed of the semiconductor device. To realize the high-speed operation of the semiconductor device with a low power supply voltage, it is necessary to set low the threshold voltage of the transistor. However, sub-threshold leakage current (off-state leakage current) of the transistor during an off state increases as the threshold voltage of the transistor lowers or an operation temperature rises. As a result, at a low set threshold voltage of the transistor, the high-speed operation of the semiconductor device is achievable, however, power consumption in the standby period of the semiconductor device increases. 
     In a semiconductor device including a plurality of circuit blocks, for example, a threshold voltage of the transistor within the circuit block is set low in order to realize the high-speed operation, and a switch transistor (a leakage cut-off transistor) is disposed between the power supply terminal of the circuit block and the power supply line to turn on in the active period and turn off in the standby period, in order to achieve low power consumption by reducing off-state leakage current of the transistor in the standby period. 
     Also, WO00/11486 discloses a technique to easily, accurately detect whether there is leakage current larger than a predetermined value in a semiconductor device. 
     The semiconductor device with the function of curtailing off-state leakage current (a leakage cut-off function) using the leakage cut-off transistor includes a test mode (the leakage cut-off function is invalid) in which the leakage cut-off transistor is constantly turned on regardless of an operation state of the semiconductor device, in addition to a normal mode (the leakage cut-off function is valid) in which the leakage cut-off transistor is turned on according to an operation state of the semiconductor device. 
     In a test, process of the semiconductor device as described above, a function test is performed in the normal mode. When a result of the test is a fail, the function test is performed again in the test mode. It is possible to determine whether defects have occurred due to the leakage cut-off function based on the result of the test, pass/fail, in the test mode. It is, however, not possible to find details of the defects such as to identify a circuit block having the defects due to the leakage cut-off function from a plurality of circuit blocks. Because of this, defect analysis cannot be efficiently performed, consuming an enormous amount of time. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to efficiently analyze defects due to the leakage cut-off function in a short period of time. 
     According to an aspect of the invention, a semiconductor device mounted in an electronics device includes a plurality of circuit blocks, a plurality of switch circuits, a setting circuit and a switch control circuit. The plurality of switch circuits are disposed so as to correspond to the plurality of circuit blocks, respectively. Each of the plurality of switch circuits is connected between a power supply terminal of a corresponding circuit block and a power supply line. The setting circuit is disposed to set each of the plurality of switch circuits to be in a valid or invalid state. When each of the switch circuits is set in the valid state by the setting circuit, the switch control circuit turns on each switch circuit in accordance with a first control signal, and when each of the switch circuits is set in the invalid state by the setting circuit, turns on each switch circuit regardless of the first control signal. The first control signal indicates an operation state (an active state or a standby state) of the plurality of circuit blocks. 
     Accordingly, being set to be valid by the setting circuit, each of the switch circuits turns on in the active period of the plurality of circuit blocks (the active period of the semiconductor device) and turns off in the standby period of the plurality of circuit blocks (the standby period of the semiconductor device). Therefore, for example, when all of the switch circuits are set to ‘valid’ by the setting circuit, it is possible to reduce off-state leakage current of all the circuit blocks in the standby period of the semiconductor device. This accordingly makes both of high-speed operation and low power consumption of the semiconductor device feasible at the same time, even when a threshold voltage of a transistor in each circuit block is set low in order to realize the high-speed operation. 
     In the test process of such a semiconductor device, the function test is performed in a state that all of the switch circuits are set to ‘valid’ by the setting circuit. When the result of the function test is a fail, the function test is sequentially performed while the state (valid or invalid) of each switch circuit is changed by the setting circuit. Based on the results of the function tests, pass/fail, and on the state of each switch circuit, it is possible to find where a defect occurs due to the leakage cut-off function. Therefore, defect analysis can be performed efficiently in a short period of time. 
     In a preferable example of one aspect of the invention, the setting circuit includes a test mode circuit. In a normal mode the test, mode circuit inactivates a plurality of test mode signals corresponding to the plurality of switch circuits respectively. In a test mode the test mode circuit activates one of the plurality of test mode signals designated by test mode information. The switch control circuit turns on each of the plurality of switch circuits in accordance with the first control signal when a corresponding test mode signal is inactivated, and turns on each of the plurality of switch circuits regardless of the first control signal when the corresponding test mode signal is activated. 
     In the test process of such a semiconductor device, the function test is performed in the normal mode. When the result of the function test is a fail, the function test is sequentially performed while the state (active or inactive) of each test mode signal is changed according to the test mode information. Based on the results of the function tests, pass/fail, and on the state of each test mode signal, it is possible to find which one of the plurality of circuit blocks has a defect due to the leakage cut-off function. 
     In a preferable example of the aspect of the invention, the setting circuit includes a plurality of storage circuits. The plurality of storage circuits are disposed so as to correspond to the plurality of switch circuits, respectively. Each of the plurality of storage circuits stores validity or invalidity of a corresponding switch circuit and activates a storage state signal when storing, the invalidity. For example, each of the plurality of storage circuits may include a fuse circuit programming validity or invalidity of the corresponding switch circuit. The switch control circuit turns on each of the plurality of switch circuits in accordance with the first control signal when a corresponding storage state signal is inactivated and turns on each of the plurality of switch circuits regardless of the first control signal when the corresponding storage state signal is activated. 
     In the test process of such a semiconductor device, the function test is performed in a state that all of the storage circuits store validity. When the result of the function test is a fail, the function test is sequentially performed while the number of the storage circuits storing the invalidity is increased. Based on the results of the function tests, pass or fail, and on the state (that validity or invalidity is stored) of each storage circuit, it is possible to find which one of the plurality of circuit blocks has a defect due to the leakage cut-off function. 
     In a preferred example of the aspect of the invention, the setting circuit includes a test mode circuit, a plurality of storage circuits and a uniting circuit. In the normal mode the test mode circuit inactivates a plurality of test mode signals corresponding to the plurality of switch circuits, respectively. In a test mode the test mode circuit activates, one of the plurality of test mode signals designated by the test mode information. The plurality of storage circuits are disposed so as to correspond to the plurality of switch circuits respectively, store validity or invalidity of a corresponding switch circuit, and activates a storage state signal when storing the invalidity. For example, each of the plurality of storage circuits may include a fuse circuit programming validity or invalidity of the corresponding switch circuit. The uniting circuit activates each of a plurality of second control signals corresponding to the plurality of switch circuits respectively when one of a corresponding test mode signal and a corresponding, storage state signal is activated. The switch control circuit turns on each of the plurality of switch circuits in accordance with the first control signal when a corresponding second control signal is inactivated, and turns on each of the plurality of switch circuits regardless of the first control signal when the corresponding second control signal is activated. 
     In the test process of such a semiconductor device, the function test is performed in the normal mode in a state that all of the storage circuits store validity. When the result of the function test is a fail, the function test is sequentially performed in the test mode while the state of each test mode signal is changed according to test mode information. Based on the results of the function tests, pass/fail, and on the state of each test mode signal, it is possible to find which one of the plurality of circuit blocks has a defect due to the leakage cut-off function. 
     Furthermore, once the invalidity is stored in a storage circuit corresponding to a circuit block having a defect, the result of the function test of the circuit block in the normal mode will be “pass”. However, in the circuit block, the off-state leakage current is not reduced, thereby slightly increasing power consumption of the semiconductor device in the standby period. However, if the power consumption increase is not a big problem for a user of the semiconductor device, the semiconductor device can be provided as a good product without waiting for correcting the defect. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by identical reference numbers, in which: 
         FIG. 1  is a circuit diagram showing a first embodiment of the invention; 
         FIGS. 2(   a ) to  2 ( d ) are, explanatory views showing an electronics device in which a semiconductor device of  FIG. 1  is mounted; 
         FIG. 3  is a circuit diagram showing a circuit block in  FIG. 1 ; 
         FIG. 4  is a circuit diagram showing a test mode signal generating circuit in  FIG. 1 ; 
         FIG. 5  is a signal-flow diagram illustrating an operation of a test mode signal generating circuit in  FIG. 4 ; 
         FIG. 6  is a signal-flow diagram illustrating an operation example (without defect) during a normal mode in a semiconductor device of  FIG. 1 ; 
         FIG. 7  is a signal-flow diagram illustrating an operation example (with defect) during a normal mode in a semiconductor device of  FIG. 1 ; 
         FIG. 8  is a signal-flow diagram illustrating an operation example (with defect) during a test mode in a semiconductor device of  FIG. 1 ; 
         FIG. 9  is a circuit diagram showing a comparison example of the invention; 
         FIG. 10  is a signal-flow diagram illustrating an operation example (with defect) during a test mode in a semiconductor device of  FIG. 9 ; 
         FIG. 11  is a circuit diagram showing a second embodiment of the invention; 
         FIG. 12  is a circuit diagram showing a fuse circuit in  FIG. 11 ; 
         FIG. 13  is a signal flow diagram illustrating an operation of a fuse circuit in  FIG. 12 ; 
         FIG. 14  is a circuit diagram showing a third embodiment of the invention; and 
         FIG. 15  is a circuit diagram showing an EOR circuit in  FIG. 14 . 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, embodiments of the invention will be described with reference to the accompanying drawings.  FIG. 1  shows a first embodiment of the invention.  FIGS. 2(   a ) to  2 ( d ) show an electronics device in which a semiconductor device of  FIG. 1  is mounted. The semiconductor device SD 10  according to the first embodiment may be mounted in an electronics device having a function block construction as shown in  FIGS. 2(   a ) to  2 ( d ). The semiconductor device SD 10  may implement at least one of the function blocks (a memory, a processor, or a memory controller). Furthermore, the electronics devices may be constructed by using any one of MCP (Multi Chip Package), SiP (System in Package) and SoC (System on Chip) techniques. 
     The semiconductor device SD 10  includes a control signal generating circuit CGCT, a test mode signal generating circuit TGC (a test mode circuit), leakage cut-off control circuits LCC 0  to LCC 3  (a switch control circuit), circuit blocks BLK 0  to BLK 3  and leakage cut-off transistors LTP 0  to LTP 3  and LTN 0  to LTN 3  (switch circuits). 
     When the control signal generating circuit CGCT analyzes a command signal CMD received through a command terminal CMD and detects a test mode entry command, the control signal generating circuit CGCT temporarily activates a test mode entry signal ENTRY to ‘1’. When the control signal generating circuit CGCT analyzes the command signal CMD and detects a test mode exit command, the control signal generating circuit CGCT temporarily activates a test mode exit signal /EXIT to ‘0’. The control signal generating circuit CGCT also temporarily activates a start signal /START to ‘0’ when the semiconductor device SD 10  is powered. 
     The test mode signal generating circuit TGC outputs test mode signals T 0  to T 3  on the basis of the test mode entry signal ENTRY, the test mode exit signal /EXIT, the start signal /START, and address signals TA 0  and TA 1  (test mode information) for identifying a test mode of the command signal CMD. When the operation mode of the semiconductor device SD 10  is a normal mode, all of the test mode signals T 0  to T 3  are inactivated to ‘1’. When the operation mode of the semiconductor device SD 10  is a test mode, at least one of the test mode signals T 0  to T 3  is activated to ‘1’. 
     The leakage cut-off control circuit LCCi (i=0, 1, 2, 3) has inverters  100  and  101  and a NAND gate G 00 . The inverter  100  inverts the test mode signal Ti and outputs the inverted signal. The NAND gate G 00  performs a NAND operation for a leakage cut-off control signal POFF (first control signal) and an output signal of the inverter  100  and outputs the result as a leakage cut-off control signal /OFFi. The inverter  101  inverts the leakage cut-off control signal /OFFi (output signal of the NAND gate G 00 ) and outputs the inverted signal as a leakage cut-off control signal OFFi. Furthermore, the leakage cut-off control signal POFF is activated to ‘1’ in the standby period of the semiconductor device SD 10  (standby period of the circuit blocks BLK 0  to BLK 3 ) and is inactivated to ‘0’ in the active period of the semiconductor device SD 10  (active period of the circuit blocks BLK 0  to BLK 3 ). 
     Therefore, if the test mode signal Ti is inactivated to ‘0’, the leakage cut-off control signals OFFi and /OFFi are activated to ‘1’ and ‘0’, respectively, in the standby period of the semiconductor device SD 10  and are inactivated to ‘0’ and ‘1’, respectively, in the active period of the semiconductor device SD 10 . Meanwhile, if the test mode signal Ti is activated to ‘1’, the leakage cut-off control signals OFFi and /OFFi are respectively inactivated to ‘0’ and ‘1’ regardless of the operation state of the semiconductor device SD 10  (operation state of the circuit blocks BLK 0  to BLK 3 ). 
     The circuit block BLKi outputs an internal signal /SIGi+1 on the basis of an internal signal /SIGi. The internal signal /SIG 0  is temporarily activated to ‘0 only in the active period of the semiconductor device SD 10  at a desired timing. The leakage cut-off transistor LTPi includes a pMOS transistor and is connected between a power supply terminal PHi of the circuit block BLKi and a power supply line VDD. A leakage cut-off transistor LTNi includes an nMOS transistor and is connected between a power supply terminal PLi of the circuit block BLKi and a ground line VSS. The leakage cut-off transistor LTPi has a gate to which the leakage cut-off control signal OFFi is applied. The leakage cut-off transistor LTNi has a gate to which the leakage cut-off control signal and /OFFi is applied. 
     Therefore, if the test mode signal Ti is inactivated to ‘0’, the leakage cut-off transistors LTPi and LTNi are turned on in the active period of the semiconductor device SD 10  and are turned off in the standby period of the semiconductor device SD 10 . Meanwhile, if the test mode signal Ti is activated to ‘1’, the leakage cut-off transistors LTPi and LTNi are always turned on regardless of the operation state of the semiconductor device SD 10 . In other words, the leakage cut-off transistors LTPi and LTNi are set to ‘valid’ when the test mode signal Ti is inactivated to ‘0’ and is set to ‘invalid’ when the test mode signal Ti is activated to ‘1’. 
       FIG. 3  shows a circuit block in  FIG. 1 . The circuit block BLki includes pMOS transistors TP 10  to TP 13  and nMOS transistors TN 10  to TN 13 . The pMOS transistor TP 10  has a source connected to the power supply terminal PHi. In other words, the source of the pMOS transistor TP 10  is connected to the power supply line VDD through the leakage cut-off transistor LTPi. A drain of the pMOS transistor TP 10  is connected to a drain of the nMOS transistor TN 10 . The NMOS transistor TN 10  has a source connected to the ground line VSS. Gates of the pMOS transistor TP 10  and, the nMOS transistor TN 10  are applied with the internal signal /SIGi. 
     The pMOS transistor TP 11  has a source connected to the power supply line VDD. A drain of the pMOS transistor TP 11  is connected to a drain of the nMOS transistor TN 11 . The nMOS transistor TN 11  has a source connected to the power supply terminal PLi. In other words, the source of the nMOS transistor TN 11  is connected to the ground line VSS through the leakage cut-off transistor LTNi. Gates of the pMOS transistor TP 11  and the nMOS transistor TN 11  are applied with a signal generated in the connection node of the pMOS transistor TP 10  and the nMOS transistor TN 10 . 
     The pMOS transistor TP 12  has a source connected to the power supply terminal PHi. In other words, the source of the pMOS transistor TP 12  is connected to the power supply line VDD through the leakage cut-off transistor LTPi. A drain of the pMOS transistor TP 12  is connected to a drain of the nMOS transistor TN 12 . The nMOS transistor TN 12  has a source connected to the ground line VSS. Gates of the pMOS transistor TP 12  and the nMOS transistor TN 12  are applied with a signal generated in the connection node of the pMOS transistor TP 11  and the nMOS transistor TN 11 . 
     The pMOS transistor TP 13  has a source connected to the power supply line VDD. A drain of the pMOS transistor TP 13  is connected to a drain of the nMOS transistor TN 13 . The nMOS transistor TN 13  has a source connected to the power supply terminal. In other words, the source of the nMOS transistor TN 13  is connected to the ground line VSS through the leakage cut-off transistor LTNi. Gates of the pMOS transistor TP 13  and the nMOS transistor TN 13  are applied with a signal generated in the connection node of the pMOS transistor TP 12  and the nMOS transistor TN 12 . A signal generated in the connection node of the pMOS transistor TP 13  and the nMOS transistor TN 13  is output as the internal signal /SIGi+1. As described above, the circuit block BLki includes the four inverters connected in series. 
     Furthermore, to realize the high speed operation of the circuit block BLki, threshold voltages of the pMOS transistors TP 10  and TP 12 , which are turned on when the internal signal /SIGi is activated, may be set lower than those of the pMOS transistors TP 11  and TP 13 , which are turned off when the internal signal /SIGi activated. Similarly, threshold voltages of the nMOS transistors TN 11  and TN 13 , which are turned on when the internal signal /SIGi is activated, may be set lower than those of the nMOS transistors TN 10  and TN 12 , which are turned off when the internal signal /SIGi is activated. 
     In the standby period of the semiconductor device SD 10 , since the internal signal /SIG 0  is inactivated to ‘1’, the internal signals /SIG 1  to /SIG 4  are also inactivated to ‘1’. Accordingly, in the standby period of the semiconductor device SD 10 , the pMOS transistors TP 10  and TP 12  and the nMOS transistors TN 11  and TN 13  in which the threshold voltages are set low are turned off. Furthermore, sources of the pMOS transistors TP 10  and TP 12  are connected to the power supply line VDD through the leakage cut-off transistor LTPi. Sources of the nMOS transistors TN 11  and TN 13  are connected to the ground line VSS through the leakage cut-off transistor LTNi. When the operation mode of the semiconductor device SD 10  is the normal mode, the leakage cut-off transistors LTPi and LTNi are turned off in the standby period of the semiconductor device SD 10 . As a result, in the standby period of the semiconductor device SD 10 , off-state leakage current occurring in the circuit blocks BLK 0  to BLK 3  can be significantly reduced. Consequently, it is possible to prevent the power, consumption of the semiconductor device SD 10  from being increased when the threshold voltages of the pMOS transistors TP 10  and TP 12  and the threshold voltages of the nMOS transistors TN 11  and TN 13  are set low. Therefore, both the high-speed operation and low power consumption of the semiconductor device SD 10  can be realized. Furthermore, in the present embodiment, it has been described that the circuit blocks BLK 0  to BLK 3  have the same internal construction. However, the circuit blocks BLK 0  to BLK 3  may have different internal constructions. 
       FIG. 4  shows a test mode signal generating circuit in  FIG. 1 . The test mode signal generating circuit TGC includes input circuits IC 0  and IC 1 , a decode circuit DEC, and output circuits OC 0  to OC 3 . The input circuit ICO (IC 1 ) has a transfer gate TG and inverters I 20  to I 23 . The transfer gate TG includes a pMOS transistor and an nMOS transistor, which are connected in parallel. A gate of the pMOS transistor of the transfer gate TG is applied with the test mode entry signal ENTRY through the inverter I 20 . A gate of the nMOS transistor of the transfer gate TG is applied with the test mode entry signal ENTRY. Therefore, the transfer gate TG is turned on when the test mode entry signal ENTRY is activated, and supplies an address signal TA 0 (TA 1 ), which is received through one end, to the other end. The transfer gate TG is turned off when the test mode entry signal ENTRY is inactivated and stops to supply the address signal TA 0  (TA 1 ) to the other end. The inverters I 21  and I 22  are connected in a ring form so as to form a latch circuit. A connection node of an input terminal, of the I 21  and an output terminal of the inverter I 22  is connected to the other end of the transfer gate TG. The inverter I 23  inverts the output signal of the inverter I 21  and outputs the inverted signal. 
     In the input circuit IC 0  (IC 1 ) constructed as described above, if the command signal CMD for indicating the test mode entry command is input to the control signal generating circuit CGCT and the test mode entry signal ENTRY supplied from the control signal generating circuit CGCT is activated, the transfer gate TG is turned on and the address signal TA 0  (TA 1 ) is supplied to the latch circuit including the inverters I 21  and I 22 . Therefore, the output signal of the inverter I 23  is set to the same logic level as that of the address signal TA 0  (TA 1 ) of the command signal CMD for indicating the test mode entry command. 
     The decode circuit DEC includes inverters I 30  to I 35  and NAND gates G 30  to G 33 . The inverter I 30  inverts the output signal (the output signal of the inverter I 23  of the input circuit IC 0 ) of the input circuit KO and outputs the inverted signal. The inverter I 31  inverts the output signal (the output signal of the inverter I 23  of the input circuit IC 1 ) of the input circuit IC 1  and outputs the inverted signal. The NAND gate G 30  performs an NAND operation for the output signal of the inverter I 30  and the output signal of the inverter I 31  and outputs the operation result. The NAND gate G 31  performs an NAND operation for the output signal of the input circuit IC 0  and the output signal of the inverter I 31  and outputs the operation result. The NAND gate G 32  performs an NAND operation for the output signal of the inverter I 30  and the output signal of the input circuit IC 1  and outputs the operation result. The NAND gate G 33  performs an NAND operation for the output signal of the input circuit IC 0  and the output signal of the input circuit IC 1  and outputs the operation result. The inverter I 32  inverts the output signal of the NAND gate G 30  and outputs the inverted signal as the test mode signal PT 0 . The inverter I 33  inverts the output signal of the NAND gate G 31  and outputs the inverted signal as the test mode signal PT 1 . The inverter I 34  inverts the output signal of the NAND gate G 32  and outputs the inverted signal as the test mode signal PT 2 . The inverter I 35  inverts the output signal of the NAND gate G 33  and outputs the inverted signal as the test mode signal PT 3 . 
     Through such a circuit construction, the test mode signal PT 0  is activated to ‘I’ when the output signal of the input circuit ICO is set to ‘0’ and the output signal of the input circuit ICI is set to ‘0’. The test mode signal PT 1  is activated to ‘1’ when the output signal of the input circuit IC 0  is set to ‘0’ and the output signal of the input circuit IC 1  is set to ‘1’. The test mode signal PT 2  is activated to ‘1’ when the output signal of the input circuit IC 0  is set to ‘1’ and the output signal of the input circuit IC 1  is set to ‘0’. The test mode signal PT 3  is activated to ‘1’ when the output signal of the input circuit IC 0  is set to ‘1’ and the output signal of the input circuit IC 1  is set to ‘1’. 
     A delay circuit DLY delays the test mode entry signal ENTRY by a predetermined ‘0 time and outputs the delayed signal as a test mode entry signal ENTRYD. The predetermined time may be set such that the test mode entry signal ENTRYD is activated after any one of the test mode signals PT 0  to PT 3  is activated when the test mode entry signal ENTRY is activated. 
     The output circuit OCi includes NAND gates G 40  to G 42  and inverters I 40  and I 41 . The NAND gate G 40  performs an NAND operation for the test mode signal PTi and the test mode entry signal ENTRYD and outputs the operation result. The NAND gate G 41  performs an NAND operation for the output signal of the NAND gate G 40  and an output signal of the NAND gate G 42  and outputs the operation result. The NAND gate G 42  performs an NAND operation for the output signal of the NAND gate G 41 , the test mode exit signal /EXIT and the start signal /START and outputs the operation result. The I 40  inverts the output signal of the NAND gate G 41  and outputs the inverted signal. The inverter I 41  inverts the output signal of the inverter I 40  and outputs the inverted signal as the test mode signal Ti. 
       FIG. 5  illustrates an operation of a test mode signal generating circuit in  FIG. 4 . If the semiconductor device SD 10  is powered, the power supply voltage VDD rises ((a) of  FIG. 5 ). When the start signal /START supplied from the control signal generating circuit CGCT is activated to ‘0’ ((b) of  FIG. 5 ), the test mode signal Ti supplied from the output circuit OCi of the test mode signal generating circuit TGC is inactivated to ‘0’ ((c) of  FIG. 5 ). 
     Thereafter, if the command signal CMD for indicating the test mode entry command (the address signals TA 0  and TA 1  indicate a decimal ‘i’) is input to the control signal generating circuit CGCT and the test mode entry signal ENTRY supplied from the control signal generating circuit CGCT is activated to ‘1’ ((d) of  FIG. 5 ), the test mode signal PTi supplied from the decode circuit DEC of the test mode signal generating circuit TGC is activated to ‘1’ ((e) of  FIG. 5 ). Furthermore, if the test mode entry signal ENTRYD supplied from the delay circuit IDLY is activated to ‘1’ after a predetermined time elapses from the activation of the test mode entry signal ENTRY ((f) of  FIG. 5 ), the test mode signal Ti is activated to ‘1’ ((g) of  FIG. 5 ). Thereafter, if the command signal CMD for indicating the test mode exit command is input to the control signal generating circuit CGCT and the test mode exit signal /EXIT supplied from the control signal generating circuit CGCT is activated to ‘0’ ((h) of  FIG. 5 ), the test mode signal Ti is inactivated to ‘0’ ((i) of  FIG. 5 ). 
       FIG. 6  illustrates an operation example (without defect) during a normal mode in a semiconductor device of  FIG. 1 . In this operation example, the operation mode of the semiconductor device SD 10  is the normal mode and the test mode signals T 0  to T 3  supplied from the test mode signal generating circuit TGC are respectively inactivated to ‘0’. In other words, all of the leakage cut-off transistors LTP 0  to LTP 3  and LTN 0  to LTN 3  are set to ‘valid’. 
     In this state, if the semiconductor device SD 10  shifts from the standby state to the active state, the leakage cut-off control signal POFF is inactivated to ‘0’ ((a) of  FIG. 6 ). The leakage cut-off control signals /OFF 0  to /OFF 3  supplied from the leakage, cut-off control circuits LCC 0  to LCC 3  are respectively inactivated to ‘1’ in response to the inactivation of the leakage cut-off control signal POFF ((b) of  FIG. 6 ). The leakage cut-off control signals OFF 0  to OFF 3  supplied from the leakage cut-off control circuits LCC 0  to LCC 3  are respectively inactivated to ‘0’ in response to the inactivation of the leakage cut-off control signals /OFF 0  to /OFF 3  ((c) of  FIG. 6 ). Since the leakage cut-off transistors LTP 0  to LTP 3  and LTN 0  to LTN 3  are turned on, each of voltages of nodes NL 0  to NL 3  within the circuit blocks BLK 0  to BLK 3  is set to the ground voltage VSS ((d) of  FIG. 6 ) and each of voltages of nodes NH 0  to NH 3  within the circuit blocks BLK 0  to BLK 3  is set to the power supply voltage VDD ((e) of  FIG. 6 ). In addition, if the internal signal /SIG 0  is activated to ‘0’ ((f) of  FIG. 6 ), the internal signals /SIG 1 , /SIG 2 , /SIG 3  and /SIG 4  are sequentially activated to ‘0’ ((g), (h), (i) and (j) of  FIG. 6 ). 
     Meanwhile, if the semiconductor device SD 10  shifts from the active state to the standby state, the leakage cut-off control signal POFF is activated to ‘1’ ((k) of  FIG. 6 ). The leakage cut-off control signals /OFF 0  to /OFF 3  are respectively activated to ‘0’ in response to the activation of the leakage cut-off control signal POFF Op of  FIG. 6 ). The leakage cutoff control signals OFF 0  to OFF 3  are respectively activated to ‘1’ in response to the activation of the leakage cut-off control signals /OFF 0  to /OFF 3  ((in) of  FIG. 6 ). Since the leakage cut-off transistors LTP 0  to LTP 3  and LTN 0  to LTN 3  are turned off, voltages of the nodes NL 0  to NL 3  and voltages of the nodes NH 0  to NH 3  become undefined ((n) and (o) of  FIG. 6 ). If the semiconductor device SD 10  operates as in the operation example of  FIG. 6  in the normal mode, the result of the function test during the normal mode in the test process is a pass. Accordingly, the semiconductor device SD 10  is determined to be a good product. 
       FIG. 7  illustrates an operation example (with defect) during a normal mode in a semiconductor device of  FIG. 1 . In this operation example, the activation timing of the leakage cut-off control signal POFF is earlier than that of the operation example of  FIG. 6  (a dotted line in the drawing) ((a) of  FIG. 7 ). Therefore, the activation timings of the leakage cut-off control signals /OFF 0  to /OFF 3  and OFF 0  to OFF 3  are earlier than those of the operation example of  FIG. 6  ((b) and (c) of  FIG. 7 ). Due to this, off timings of the leakage cut-off transistors LTP 0  to LTP 3  and LTN 0  to LTN 3  come earlier and voltages of the nodes NL 0  to NL 3  and the nodes NH 0  to NH 3  go unstable immediately after the internal signal /SIG 3  is inactivated ((d) and (e) of  FIG. 7 ). Consequently, the internal signal /SIG 4  is not activated ((f) of  FIG. 7 ). If the semiconductor device SD 10  operates as in the operation example of  FIG. 7  during the normal mode, the result of the function test during the normal mode in the test process will be a fail. Accordingly, the semiconductor device SD 10  is determined to be a defective product. 
     In the test process of the semiconductor device SD 10 , if the result of the function test during the normal mode is a fail, defect analysis of the semiconductor device SD 10  can be performed as follows. First, the command signal CMD for indicating the test mode entry command is input four times while sequentially setting the address signals TA[1:0] (the address signals TA 1  and TA 0 ) to ‘00’, ‘01’, ‘10’ and ‘11’, respectively, thereby activating all of the test mode signals T 0  to T 3  to ‘1’. As a result, all of the leakage cut-off transistors LTP 0  to LTP 3  and LTN 0  to LTN 3  are set to ‘invalid’. When the result of the function test is a pass in this state, it is determined that defects have occurred due to the leakage cut-off function. When it is determined that defects have occurred due to the leakage cut-off function, all of the test mode signals T 0  to T 3  are inactivated to ‘0’ by inputting the command signal CMD for indicating the test mode exit command. Accordingly, all of the leakage cut-off transistors LTP 0  to LTP 3  and LTN 0  to LTN 3  are set to ‘valid’. 
     Next, in a state where the address signal TA [1:0] is set to ‘00’, the test mode signal T 0  is activated to ‘1’ by inputting the command signal CMD for indicating the test mode entry command. As a result, only the leakage cut-off transistors LTP 0  and LTN 0  are set to ‘invalid’. In this state, if the result of the function test is a pass, it is determined that defects have occurred in the circuit block BLK 0  due to the leakage cut-off function. Meanwhile, if the result of the function test is a fail, the test mode signal T 0  is inactivated to ‘0’ by inputting the command signal CMD for indicating the test mode exit command. Accordingly, the leakage cut-off transistors LTP 0  and LTN 0  are set to ‘valid’ again. 
     Next, in a state where the address signal TA [1:0] is set to ‘01’, the test mode signal T 1  is activated to ‘1’ by inputting the command signal CMD for indicating the test mode entry command. As a result, only the leakage cut-off transistors LTP 1  and LTN 1  are set to ‘invalid’. In this state, if the result of the function test is a pass, it is determined that defects have occurred in the circuit block BLK 1  due to the, leakage cut-off function. Meanwhile, if the result of the function test is a fail, the test mode signal T 1  is inactivated to ‘0’ by inputting the command signal CMD for indicating the test mode exit command. Accordingly, the leakage cut-off transistors LTP 1  and LTN 1  are set to ‘valid’ again. 
     Next, in a state where the address signal TA [1:0] is set to ‘10’, the test mode signal T 2  is activated to ‘1’ by inputting the command signal CMD for indicating the test mode entry command. As a result, only the leakage cut-off transistors LTP 2  and LTN 2  are set to ‘invalid’. In this state, if the result of the function test is a pass, it is determined that defects have occurred in the circuit block BLK 2  due to the leakage cut-off function. Meanwhile, if the result of the function test is a fail, the test mode signal T 2  is inactivated to ‘0’ by inputting the command signal CMD for indicating the test mode exit command. Accordingly, the leakage cut-off transistors LTP 2  and LTN 2  are set to ‘valid’ again. 
     Thereafter, in a state where the address signal TA [1:0] is set to ‘11’, the test mode signal T 3  is activated to ‘1’ by inputting the command signal CMD for indicating the test mode entry command. As a result, only the leakage cut-off transistors LTP 3  and LTN 3  are set to ‘invalid’. In this state, if the result of the function test is a pass, it is determined that defects have occurred in the circuit block BLK 3  due to the leakage cut-off function. For example, if the semiconductor device SD 10  operates in the same manner as the operation example of  FIG. 7  during the normal mode, a pass is determined as the result of the function test in this state and it is determined that defects have occurred in the circuit block BLK 3  due to the leakage cut-off function. 
       FIG. 8  illustrates an operation example (with defect) during a test mode in a semiconductor device of  FIG. 1 . This operation example corresponds to the operation of the semiconductor device SD 10  during the test mode, which operates in the same manner as the operation example of  FIG. 7  during the normal mode. In this operation example, the operation mode of the semiconductor device SD 10  is the test mode, and the test mode signals T 0  to T 2  are respectively inactivated to ‘0’ and the test mode signal T 3  is activated to ‘1’. Accordingly, the leakage cut-off control signal /OFF 3  is always inactivated to ‘1’ ((a) of  FIG. 8 ) and the leakage cut-off control signal OFF 3  is always inactivated to ‘0’ ((b) of  FIG. 8 ). In other words, the leakage cut-off transistors LTP 3  and LTN 3  are set to ‘invalid’. Therefore, a voltage of the node NL 3  within the circuit block BLK 3  is always set to the ground voltage VSS ((c) of  FIG. 8 ) and a voltage of the node NH 3  within the circuit block BLK 3  is always set to the power supply voltage VDD ((d) of  FIG. 8 ). For this reason, even when the semiconductor device SD 10  operate in the same manner as the operation example of  FIG. 7  during the normal mode, the internal signal ISIG 4  is activated to ‘0’ ((e) of  FIG. 8 ) in the same manner as the operation example of  FIG. 6 . Therefore, in the case where in the test process of the semiconductor device SD 10 , the result of the function test performed in the normal mode is a fail, through the above-mentioned processings, the result will be a pass when the function test is performed in a state where only the test mode signal T 3  is activated to ‘1’. This can lead to specifying that the circuit block BLK 3  is the one having defects due to the leakage cut-off function. As described above, in the semiconductor device SD 10  according to the first embodiment, it is possible to easily determine a location at which a defect has been occurred due to the leakage cut-off function and to improve the easiness of defect analysis. 
       FIG. 9  shows a comparison example of the invention. In describing the comparison example, the same parts as those of the first embodiment are represented by the same reference numerals, and the descriptions thereof will be omitted. A semiconductor device SD 10   a  includes a leakage cut-off control circuit LCC 0 , circuit blocks BLK 0  to BLK 3  and leakage cut-off transistors LTP 0  and LTN 0  The leakage cut-off control circuit LCC 0  receives a test mode signal TEST as an input signal of an inverter  100 . The test mode signal TEST is inactivated to ‘0’ when the operation mode of the semiconductor device SD 10   a  is the normal mode and is activated to ‘1’ when the operation mode of the semiconductor device SD 10   a  is the test mode. Therefore, the leakage cut-off transistors LTP 0  and LTN 0  are set to ‘valid’ when the operation mode of the semiconductor device SD 10   a  is the normal mode and are set to ‘invalid’ when the operation mode of the semiconductor device SD 10   a  is the test mode. 
     A power supply terminal PH 1  of the circuit block BLK 1 , a power supply terminal PH 2  of the circuit block BLK 2  and a power supply terminal PH 3  of the circuit block BLK 3  are connected to a power supply line VDD through the leakage cut-off transistor LTP 0  in the same manner as a power supply terminal PH 0  of the circuit block BLK 0 . A power supply terminal PL 1  of the circuit block BLK 1 , a power supply terminal PL 2  of the circuit block BLK 2  and a power supply terminal PL 3  of the circuit block BLK 3  are connected to a ground line VSS through the leakage cut-off transistor LTN 0  in the same manner as a power supply terminal PL 0  of the circuit block BLK 0 . 
       FIG. 10  illustrates an operation example (with defect) during a test mode in a semiconductor device of  FIG. 9 . This operation example corresponds to the operation of the semiconductor device SD 10   a  during the test mode, which operates in the same manner as the operation example of  FIG. 7  during the normal mode. In the operation example, the operation mode of the semiconductor device SD 10   a  is the test mode and the test mode signal TEST is activated to ‘1’. Due to this, the leakage cut-off control signal /OFF 0  is always inactivated to ‘1’ ((a) of  FIG. 10 ) and the leakage cut-off control signal OFF 0  is always inactivated to ‘0’ ((b) of  FIG. 10 ). In other words, the leakage cut-off transistors LTP 0  and LTN 0  are set to ‘invalid’. Therefore, voltages of nodes NL 0  to NL 3  within the circuit blocks BLK 0  to BLK 3  are always set to the ground voltage VSS ((c) of  FIG. 10 ) and voltages of nodes NH 0  to NH 3  within the circuit blocks BLK 0  to BLK 3  are always set to the power supply voltage VDD ((d) of  FIG. 10 ). Therefore, even when the semiconductor device SD 10   a  operates in the same manner as the operation example of  FIG. 7  during the normal mode, the internal signal /SIG 4  is activated to ‘0’ ((e) of  FIG. 10 ) in the same manner as the operation example of  FIG. 6 . 
     Accordingly, in the test process of the semiconductor device SD 10   a , if the result of the function test during the normal mode is a fail, the result wilt become a pass when the function test is performed again in the test mode. This reveals that defects have occurred due to the leakage cut-off function. However, it is not able to specify that the circuit block BLK 3  is the one having defects due to the leakage cut-off function. As described above, in the semiconductor device SD 10   a  of the comparison example, it is not possible to specify a location at which a defect has been occurred due to the leakage cut-off function. Therefore, efficient defect analysis is not feasible, consuming an enormous amount of time. 
       FIG. 11  shows a second embodiment of the invention. In describing the second embodiment, the same parts are represented by the same reference numerals, and the descriptions thereof will be omitted. A semiconductor device SD 20  according to the second embodiment may be mounted in an electronics device having the function block construction as shown in  FIGS. 2(   a ) to  2 ( d ) in the same manner as the semiconductor device SD 10  according to the first embodiment. The semiconductor device SD 20  may implement at least one of the function blocks. The semiconductor device SD 20  includes a control signal generating circuit CGCF, fuse circuits FC 0  to FC 3  (storage circuits), leakage cut-off control circuits LCC 0  to LCC 3 , circuit blocks BLK 0  to BLK 3  and leakage cut-off transistors LTP 0  to LTP 3  and LTN 0  to LTN 3 . 
     The control signal generating circuit CGCF temporarily activates a fuse reset signal /FSR to ‘0’ when the semiconductor device SD 20  is powered. The control signal generating circuit CGCF temporarily activates a fuse set signal FSS to ‘1’ after the fuse reset signal /FSR is inactivated. The fuse circuit FCi (i=0, 1, 2, 3) outputs a fuse state signal Fi (a storage state signal) for indicating whether a fuse FS is blown or not on the basis of the fuse reset signal /FSR and the fuse set signal FSS. The leakage cut-off control circuit LCCi receives the fuse state signal Fi as an input signal of an inverter  100 . Therefore, the leakage cut-off transistors LTPi and LTNi are set to ‘valid’ when the fuse state signal Fi is inactivated to ‘0’ and are set to ‘invalid’ when the fuse state signal Fi is activated to ‘1’. 
       FIG. 12  shows a fuse circuit in  FIG. 11 . The fuse circuit FCi includes pMOS transistors TP 50  and TP 51 , nMOS transistors TN 50  to TN 52 , the fuse FS and inverters I 50  and I 51 . The pMOS transistor TP 50  has a source connected to the power supply line VDD. A drain of the pMOS transistor TP 50  is connected to a drain of the nMOS transistor TN 50 . The nMOS transistor TN 50  has a source connected to the ground line VSS through the fuse FS. The pMOS transistor TP 50  has a gate to which the fuse reset signal /FSR is input. The nMOS transistor TN 50  has a gate to which the fuse set signal FSS is input. 
     The pMOS transistor TP 51  has a source connected to the power supply line VDD. A drain of the pMOS transistor TP 51  is connected to a drain of the nMOS transistor TN 51 . A source of the nMOS transistor TN 51  is connected to a source of the nMOS transistor T 52 . The nMOS transistor TN 52  has a source connected to the ground line VSS. The pMOS transistor TP 51  and the nMOS transistor TN 51  have gates to which the output signal of the inverter I 50  is input. The nMOS transistor TN 52  has a gate to which the fuse reset signal /FSR is input. A connection node of the pMOS transistor TP 50  and the NMOS transistor TN 50 , a connection node of the pMOS transistor TP 51  and the nMOS transistor TN 51  and an input terminal of the inverter I 50  are interconnected. The inverter I 51  inverts the output signal of the inverter I 50  and outputs the inverted signal as the fuse state signal Fi. 
       FIG. 13  illustrates an operation of a fuse circuit in  FIG. 12 . If the semiconductor device SD 20  is powered, the power supply voltage VDD rises ((a) of  FIG. 13 ). If the fuse reset signal /FSR supplied from the control signal generating circuit CGCF is activated to ‘0’ ((b) of  FIG. 13 ), the pMOS transistor TP 50  of the fuse circuit FCi is turned on and the nMOS transistor TN 52  of the fuse circuit FCi is turned off. Since the output signal of the inverter I 50  of the fuse circuit FCi is set to ‘0’, the fuse state signal Fi supplied from the inverter I 51  of the fuse circuit FCi is activated to ‘1’ ((c) of  FIG. 13 ). Furthermore, if the fuse reset signal /FSR is inactivated to ‘1’, the pMOS transistor TP 50  of the fuse circuit FCi is turned off and the nMOS transistor TN 52  of the fuse circuit FCi is turned on. 
     If the fuse set signal FSS supplied from the control signal generating circuit CGCF is activated to ‘1’ after the fuse reset signal /FSR is inactivated to ‘1’ ((d) of  FIG. 13 ), the nMOS transistor TN 50  of the fuse circuit FCi is turned on. If the fuse FS of the fuse circuit FCi has not been blown, the output signal of the inverter I 50  of the fuse circuit FCi changes from ‘0’ to ‘1’. Accordingly, the fuse state signal Fi is inactivated to ‘0’ ((e) of  FIG. 13 ). Meanwhile, if the fuse FS of the fuse circuit FCi has been blown, the fuse state signal Fi is activated to ‘1’ since the output signal of the inverter I 50  of the fuse circuit FCi does not change from ‘0’ to ‘1’. Therefore, the leakage cut-off transistors LTPi and LTNi are set to ‘valid’ when the fuse FS of the fuse circuit FCi is not blown and are set to ‘invalid’ when the fuse FS of the fuse circuit FCi is blown. 
     In the test process of the semiconductor device SD 20  constructed as described above, the function test is performed in order to make a pass/fail determination. It is then determined whether the semiconductor device SD 20  is good or defective based on the pass/fail determination. Furthermore, at this point, the fuses FS of the fuse circuits FC 0  to FC 3  are not blown. If the result of the function test is a fail, the function test can be sequentially performed while the fuses FS is blown in order of the fuse circuits FC 0 , FC 1 , FC 2  and FC 3 . A location at which a defect has been occurred due to the leakage cut-off function can be easily determined based on the pass/fail determination and the state (blown or non-blown state) of the fuses FS at the fuse circuits FC 0  to FC 3 . For example, if the semiconductor device SD 20  can be operated in the same manner as the operation example of  FIG. 7  in a state where all of the fuses FS of the fuse circuits FC 0  to FC 3  are not blown, a pass is obtained through the function test performed in a state where the fuse FS of the fuse circuit FC 3  is blown. Accordingly, it is possible to specify that the circuit block BLK 3  is the one having defects due to the leakage cut-off function. As described above, in the semiconductor device SD 20  according to the second embodiment, a location at which a defect has been occurred due to the leakage cut-off function can be easily determined so as to improve the easiness of defect analysis in the same manner as the semiconductor device SD 10  according to the first embodiment. 
       FIG. 14  shows a third embodiment of the invention. In the third embodiment, the same parts are represented by the same reference numerals as those of the first and second embodiments, and the descriptions thereof will be omitted. A semiconductor device SD 30  according to the third embodiment may be mounted in an electronics device having the function block construction as shown in  FIGS. 2(   a ) to  2 ( d ) in the same manner as the semiconductor device SD 10  according to the first embodiment. The semiconductor device SD 30  may implement at least one of the function blocks. 
     The semiconductor device SD 30  includes a control signal generating circuit. CGCT, a test mode signal generating circuit TOG, a control signal generating circuit CGCF, fuse circuits FC 0  to FG 3 , EOR circuits EC 0  to EC 3  (a uniting circuit), leakage cut-off control circuits LCC 0  to LCC 3 , circuit blocks BLK 0  to BLK 3  and leakage cut-off transistors LTP 0  to LTP 3  and LTN 0  to LTN 3 . The EOR circuit ECi (i=0, 1, 2, 3) performs an exclusive OR operation on a test mode signal Ti received from the test mode signal, generating circuit TGC and a fuse state signal Fi received from the fuse circuit FCi and outputs the operation result as a control signal TFi (a second control signal). The leakage cut-off control circuit LCCi receives the control signal TFi as an input signal of an inverter  100 . Therefore, the leakage cut-off transistors LTPi and LTNi, are set to ‘valid’ when the control signal TFi is inactivated to ‘0’ and are set to ‘invalid’ when the control signal TFi is activated to ‘1’. 
       FIG. 15  shows an EOR circuit in  FIG. 14 . The EOR circuit ECi includes inverters I 60  and I 61  and NAND gates G 60  to G 62 . The inverter I 60  inverts the fuse state signal Fi received from the fuse circuit FCi and outputs the inverted signal. The inverter I 61  inverts the test mode signal Ti received from the test mode signal generating circuit TOG and outputs the inverted signal. The NAND gate G 60  performs an NAND operation for the test mode signal Ti and an output signal of the inverter I 60  and outputs the operation result. The NAND gate G 61  performs an NAND operation for an output signal of the inverter I 61  and the fuse state signal Fi and, outputs the operation result. The NAND gate G 62  performs an NAND operation for an output signal of the NAND gate G 60  and an output signal of the NAND gate G 61  and outputs the operation result. Through such a circuit construction, the control signal TFi is activated to ‘1’ when either the test mode signal Ti or the fuse state signal Fi is activated to ‘1’. The control signal TFi is inactivated to ‘0’ when both the test mode signal Ti and the fuse state signal Fi are inactivated to ‘0’ or when both the test mode signal Ti and the fuse state signal Fi are activated to ‘1’. 
     In the case where the semiconductor device SD 30  constructed as described above operates in the same manner as the operation example of  FIG. 7  during the normal mode, the result of the function test performed during the normal mode in the test process will be a fail. In this, case, it is possible to specify that the circuit block having defects due to the leakage cut-off function is the circuit block BLK 3 , by performing the same defect analysis as that of the first embodiment. Therefore, defect analysis can be also performed within a short period of time in the semiconductor device SD 30  of the third embodiment as in the semiconductor device SD 10  according to the first embodiment. 
     Furthermore, if the fuse FS of the fuse circuit FC 3  corresponding to the circuit block BLK 3  having defects is blown, the result of the function test performed in the normal mode will be a pass. However, off-state leakage current is not reduced in the circuit block BLK 3  and power consumption in the standby period of the semiconductor device SD 30  slightly increases. However, if the power consumption increase does not cause a problem to a user of the semiconductor device SD 30 , the semiconductor device SD 30  can be provided as a good product without waiting for correcting defects. 
     The invention is not limited to the above embodiments and various modifications may be made without departing from the spirit and scope of the invention. Any improvement may be made in part or all of the components.