Patent Publication Number: US-2023157112-A1

Title: Display apparatus including overlapping elements

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0157097, filed on Nov. 15, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. 
     TECHNICAL FIELD 
     The present disclosure relates to a display and, more specifically, to a display apparatus including overlapping capacitors or connection lines. 
     DISCUSSION OF THE RELATED ART 
     A display apparatus displays data visually and may be used in a wide variety of electronic devices including large devices like televisions and electronic billboards and small devices such as smartphones and watches. 
     The display apparatus may display an image using a plurality of pixels that each receive an electrical signal and emit light so that they may together display an image. Each pixel includes a display element; for example, an organic light-emitting diode display includes an organic light-emitting diode (OLED) as a display element. In general, in an organic light-emitting display apparatus, a thin-film transistor and an organic light-emitting diode are formed on a substrate, and an image is formed as the organic light-emitting diodes emit light. 
     SUMMARY 
     A display apparatus includes a first transistor. The first transistor includes a first semiconductor layer and a first electrode that at least partially overlaps the first semiconductor layer in a depth direction. The display apparatus further includes a first capacitor including the first electrode and a second electrode that at least partially overlaps the first electrode in a depth direction. A second capacitor includes the second electrode and a third electrode that at least partially overlapping the second electrode in a depth direction. A first data line is configured to transfer a data voltage. First and second scan lines are configured to transfer first and second scan signals, respectively. A second transistor connects the first data line to the second electrode in response to the first scan signal. A third transistor connects the first electrode to a drain of the first transistor in response to the second scan signal. 
     As used herein, the phrase “connects X to Y in response to Z” means that a connection between X and Y is established and/or terminated as a result of the reception of or the change in value for a signal Z. 
     The depth direction is a direction orthogonal to a plane of a display surface of the display apparatus. The display surface may be a surface through which the display is viewed and may be a front surface of the display device. 
     The third transistor may be arranged over the first transistor and may include a second semiconductor layer and a fourth electrode that at least partially overlaps the second semiconductor layer. The first semiconductor layer may include a silicon semiconductor material. The second semiconductor layer may include an oxide semiconductor material. 
     The display apparatus may further include a substrate in which a display area and a peripheral area that at least partially surrounds the display area are defined. Second and third data lines are arranged in the display area. A pad portion is arranged at one side of the peripheral area and the pad portion includes first to third data pads. A first connection line connects the first data line arranged in the display area to the first data pad. A second connection line connects the second data line to the second data pad. A third connection line connects the third data line to the third data pad. The first to third connection lines are arranged on different layers from each other. 
     The first connection line may be arranged on a same layer as the first electrode. The second connection line may be arranged on a same layer as the fourth electrode. The third connection line may be arranged on a same layer as the third electrode. 
     The display apparatus may further include a fifth electrode that is arranged below the second semiconductor layer, at least partially overlaps the second semiconductor layer, and is electrically connected to the fourth electrode. 
     The fifth electrode may be arranged on a same layer as either the second electrode or the third electrode. 
     The first transistor may have a conductivity type that is opposite to a conductivity type of the third transistor. 
     The second transistor may have a same conductivity type as a conductivity type of the third transistor. 
     The display apparatus may further include a power line electrically connected to the third electrode and configured to transfer a driving voltage. 
     The display apparatus may further include a display element having an anode and a cathode. A third scan line may be configured to transfer a third scan signal. A fourth scan line may be configured to transfer a fourth scan signal. An emission control line may be configured to transfer an emission control signal. A first voltage line may be configured to transfer an initialization voltage. A fourth transistor may connect the first voltage line to the first electrode in response to the third scan signal. A fifth transistor may connect the power line to a source of the first transistor in response to the emission control signal. A sixth transistor may connect the drain of the first transistor to the anode of the display element in response to the emission control signal. A seventh transistor may connect the first voltage line to the anode of the display element in response to the fourth scan signal. 
     The display apparatus may further include a second voltage line configured to transfer a reference voltage. An eighth transistor may connect the second voltage line to the second electrode in response to the second scan signal. 
     The display apparatus may further include a third voltage line configured to transfer a bias voltage. A ninth transistor may connect the third voltage line to the source of the first transistor in response to the fourth scan signal. 
     A display apparatus includes a substrate in which a display area and a peripheral area that at least partially surrounds the display area are defined. A plurality of data lines is arranged in the display area with each of the plurality of data lines being extended in a first direction. A pad portion is arranged at one side of the peripheral area and includes a plurality of data pads. A plurality of first connection lines connects first data lines, among the plurality of data lines, to corresponding data pads from among the plurality of data pads. A plurality of second connection lines connect second data lines, among the plurality of data lines, to corresponding data pads from among the plurality of data pads. A plurality of third connection lines connect third data lines, among the plurality of data lines, to corresponding data pads from among the plurality of data pads. The plurality of first connection lines, the plurality of second connection lines, and the plurality of third connection lines are arranged on different layers from each other. 
     The plurality of first connection lines and the plurality of second connection lines may be each arranged between two third connection lines, among the plurality of third connection lines, that are adjacent to each other in the first direction. 
     The plurality of second connection lines may be arranged over the plurality of first connection lines. The plurality of third connection lines may be arranged over the plurality of second connection lines. 
     A number of the plurality of third connection lines per unit area may be greater than a number of the plurality of first connection lines per unit area. The number of the plurality of third connection lines per unit area may be greater than a number of the plurality of second connection lines per unit area. 
     A number of the plurality of first connection lines per unit area may be equal to the number of the plurality of second connection lines per unit area. 
     The plurality of third connection lines may have a multi-layered structure. 
     Each of the plurality of third connection lines may include a first layer, a third layer disposed over the first layer, and a second layer disposed between the first layer and the third layer. 
     The plurality of second connection lines may have a same layer structure as a layer structure of the plurality of third connection lines. 
     The display apparatus may further include a first transistor arranged in the display area. The first transistor may include a first semiconductor layer and a first electrode that at least partially overlaps the first semiconductor layer. A first capacitor may be arranged in the display area and may include the first electrode and a second electrode that at least partially overlaps the first electrode. A second capacitor may be arranged in the display area and may include the second electrode and a third electrode that at least partially overlaps the second electrode. A second transistor may be arranged over the first transistor in the display area and may include a second semiconductor layer and a fourth electrode that at least partially overlaps the second semiconductor layer. 
     The plurality of first connection lines may be arranged on a same layer as the first electrode. The plurality of second connection lines may be arranged on a same layer as the third electrode. The plurality of third connection lines may be arranged on a same layer as the fourth electrode. 
     The plurality of first connection lines may be arranged on a same layer as the first electrode. The plurality of second connection lines may be arranged on a same layer as the second electrode. The plurality of third connection lines may be arranged on a same layer as the third electrode. 
     The plurality of first connection lines may be arranged on a same layer as the first electrode. The plurality of second connection lines may be arranged on a same layer as the second electrode. The plurality of third connection lines may be arranged on a same layer as the fourth electrode. 
     The plurality of first connection lines may be arranged on a same layer as the second electrode. The plurality of second connection lines may be arranged on a same layer as the third electrode. The plurality of third connection lines may be arranged on a same layer as the fourth electrode. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects and features of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: 
         FIG.  1    is a plan view schematically illustrating a display apparatus according to an embodiment of the present disclosure; 
         FIG.  2    is a plan view schematically illustrating a display apparatus according to an embodiment of the present disclosure; 
         FIG.  3    is an equivalent circuit diagram illustrating a pixel arranged in a display apparatus, according to an embodiment of the present disclosure; 
         FIG.  4    is a cross-sectional view schematically illustrating a portion of a pixel, according to an embodiment of the present disclosure; 
         FIG.  5    is a cross-sectional view schematically illustrating a portion of a pixel, according to an embodiment of the present disclosure; 
         FIG.  6    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure; 
         FIG.  7    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure; 
         FIG.  8    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure; 
         FIG.  9    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure; 
         FIG.  10    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure; 
         FIG.  11    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure; 
         FIG.  12    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure; and 
         FIG.  13    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure t. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals may refer to like elements throughout the specification and the drawings. In this regard, the present embodiments may have different forms and should not necessarily be construed as being limited to the descriptions set forth herein. As used herein, the term “and/or” may include any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. 
     As the present disclosure allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. The effects and features of the present disclosure, and ways to achieve them will become apparent by referring to embodiments that will be described later in detail with reference to the drawings. However, the present disclosure is not necessarily limited to the following embodiments but may be embodied in various forms. 
     Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, and in the description with reference to the drawings, like reference numerals may refer to like elements and to the extent that a detailed description of an element is omitted, it may be assumed that the element is at least similar to a corresponding element that has been described elsewhere within the specification. 
     The terms “first”, “second”, etc. may be used herein to describe various elements, but these elements should not necessarily be limited by these terms. 
     An expression used in the singular may encompass the expression of the plural, unless it has a clearly different meaning in the context. 
     In the embodiments below, it will be further understood that the terms “comprise” or “have” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements. 
     In the embodiments below, it will be understood when a portion such as a layer, an area, or an element is referred to as being “on” or “above” another portion, it can be directly on or above the other portion, or intervening portion may also be present. 
     It should be understood that even though a process may be described in terms of a sequence of steps, these steps are not necessarily intended to be performed in the order in which they are listed and these steps may be performed in any order or all at the same time. 
     In the present specification, “A and/or B” refers to A, B, or A and B. In addition, “at least one of A and B” refers to A, B, or A and B. 
     In the embodiments below, it will be understood when a layer, an area, or an element or the like is referred to as being “connected” to another one, it can be directly connected to the other one, or it can be indirectly connected to the other one and intervening layers, areas, elements, or the like may also be present. For example, it will also be understood that when a layer, an area, or an element or the like is referred to as being “electrically connected to” another one, it can be directly electrically connected to the other one, or it can be indirectly electrically connected to the other one and intervening layers, areas, elements, or the like may be present. 
     An x-axis, a y-axis, and a z-axis are not necessarily limited to three axes on a Cartesian coordinates system but may be construed as including these axes. For example, an-x axis, a y-axis, and a z-axis may be at right angles or may also indicate different directions from one another, which are not at right angles. 
       FIG.  1    is a plan view schematically illustrating a display apparatus according to an embodiment of the present disclosure. 
     Referring to  FIG.  1   , a display apparatus  1  includes a display area DA displaying an image and a peripheral area PA at least partially surrounding the display area DA. The display apparatus  1  may display an image to a user by using light emitted from the display area DA. Also, as the display apparatus  1  includes a substrate  100 , it may be said that the substrate  100  includes the display area DA and the peripheral area PA. 
     The substrate  100  may include various materials such as glass, metal, or plastic. According to an embodiment of the present disclosure, the substrate  100  may include a flexible material. The flexible material may refer to a material that is easily bent and curved and is foldable or rollable to a noticeable extent without cracking or otherwise sustaining damage. The substrate  100  including a flexible material may include super-thin glass, metal, or plastic. 
     Pixels PX including various display elements such as an organic light-emitting diode OLED may be arranged in the display area DA of the substrate  100 . The pixels PX are provided in plural, and the plurality of pixels PX may be arranged in various forms such as a stripe arrangement, a pentile arrangement, or a mosaic arrangement to realize an image. 
     While  FIG.  1    illustrates that the display area DA has a rectangular planar shape, the display area DA may have a polygonal shape such as a triangle, a pentagon, or a hexagon, a circular shape, an oval shape, or an irregular shape or any other shape. 
     The peripheral area PA of the substrate  100  may include an area around the display area DA, where an image is not displayed and no display pixels are present. Various wires configured to transfer an electrical signal to be applied to the display area DA, a printed circuit board or a driver integrated circuit (IC) chip may be disposed in the peripheral area PA. 
       FIG.  2    is a plan view schematically illustrating a display apparatus according to an embodiment of the present disclosure. 
     Referring to  FIG.  2   , the display apparatus  1  (see  FIG.  1   ) may include a display panel  10 , a printed circuit board PCB, and a data driving circuit  150 . 
     The display panel  10  may include the display area DA and the peripheral area PA at least partially surrounding the display area DA. The display area DA may be covered using an encapsulation member to be protected from external air or moisture or the like. 
     The display panel  10  may include a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL, a plurality of power lines PL, which are arranged in the display area DA. 
     The pixels PX may each include a display element such as an organic light-emitting diode OLED. Each pixel PX may emit, for example, red, green, blue, or white light through the organic light-emitting diode OLED. Hereinafter, in the present specification, each pixel PX refers to a sub-pixel emitting different colors from each other, and each pixel PX may be, for example, one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel. 
     The scan lines SL may each extend in a first direction (e.g., a ±x direction) connected to those pixels PX located in the same row from among the plurality of pixels PX. The scan lines SL may be arranged in a second direction (e.g., ±y direction). In  FIG.  2   , the scan lines SL are illustrated as a single wire, but alternatively, the scan lines SL may include a plurality of wires. 
     The emission control lines EL may each extend in the first direction (e.g., a ±x direction) connected to those pixels PX located in the same row from among the plurality of pixels PX. The emission control lines EL may be arranged in the second direction (e.g., ±y direction). In  FIG.  2   , the emission control lines EL are illustrated as a single wire, but alternatively, the emission control lines EL may include a plurality of wires. 
     The data lines DL may each extend in the second direction (e.g., the ±y direction) connected to those pixels PX located in the same column from among the plurality of pixels PX. The data lines DL may be arranged in the first direction (e.g., a ±x direction). 
     The power lines PL may each extend in the second direction (e.g., the ±y direction) connected to those pixels PX located in the same column from among the plurality of pixels PX. The power lines PL may be arranged in the first direction (e.g., a ±x direction). 
     The display panel  10  may include a first gate driving circuit  130 , a second gate driving circuit  131 , a first voltage supply wire  160 , a second voltage supply wire  170 , and a pad portion  140 , which are arranged in the peripheral area PA. Each pixel PX may be electrically connected to outer circuits arranged in the peripheral area PA. 
     The first gate driving circuit  130  and the second gate driving circuit  131  may each include a scan driving circuit and an emission control driving circuit. The scan driving circuit may carry a scan signal to each pixel PX via the scan line SL. The emission control driving circuit may carry an emission control signal to each pixel PX via the emission control line EL. 
     The second gate driving circuit  131  may be arranged in parallel with the first gate driving circuit  130  with the display area DA disposed therebetween. Some of the pixels PX arranged in the display area DA may be electrically connected to the first gate driving circuit  130 , and others may be electrically connected to the second gate driving circuit  131 . The second gate driving circuit  131  may be omitted. 
     The first voltage supply wire  160  may include a first sub-wiring  162  and the second sub-wiring  163  extending in parallel in the first direction (e.g., ±x direction) with the display area DA disposed therebetween. The second voltage supply wire  170  may partially surround the display area DA in a loop shape with one side open. 
     The pad portion  140  may be arranged at one side of the peripheral area PA. The pad portion  140  may include a plurality of pads such as a data pad DP. The pad portion  140  might not be covered by an insulating layer but exposed and electrically connected to the printed circuit board PCB. The pads of the pad portion  140  may be electrically connected to a terminal portion PCB-P of the printed circuit board PCB. The printed circuit board PCB may transfer a signal or voltage of a controller to the display panel  10 . 
     A control signal generated by the controller may be transferred to the first gate driving circuit  130  and the second gate driving circuit  131  through the printed circuit board PCB and the pad portion  140 , respectively. 
     A first driving voltage ELVDD (see  FIG.  3   ) generated by the controller may be transferred to the first voltage supply wire  160  through a first connection wiring  161  connected to the pads of the pad portion  140 . The first driving voltage ELVDD may be provided to each pixel PX through the power line PL connected to the first voltage supply wire  160 . 
     A second driving voltage ELVSS (see  FIG.  3   ) generated by the controller may be transferred to the second voltage supply wire  170  through a second connection wiring  171  connected to the pads of the pad portion  140 . The second driving voltage ELVSS may be provided to a cathode (or an opposite electrode) of a display element connected to the second voltage supply wire  170 . 
     The data driving circuit  150  may be electrically connected to the data lines DL. A data signal (or data voltage) of the data driving circuit  150  may be carried to each pixel PX through a connection line CL connected to the data pad DP of the pad portion  140  and a data line DL connected to the connection line CL. 
     While the data driving circuit  150  is illustrated as being arranged on the printed circuit board PCB in  FIG.  2   , alternatively, the data driving circuit  150  may be arranged on the substrate  100 . For example, the data driving circuit  150  may be arranged between the pad portion  140  and the first voltage supply wire  160 . 
     As described above, the connection line CL may connect the data line DL to the data pad DP. For example, a plurality of first connection lines CL 1  may connect first data lines DL 1 , which are some of the plurality of data lines DL, to a corresponding data pad (e.g., a first data pad DP 1 ) from among the plurality of data pads DP. A plurality of second connection lines CL 2  may connect second data lines DL 2 , which are some other ones among the plurality of data lines DL, to a corresponding data pad (e.g., a second data pad DP 2 ) from among the plurality of data pads DP. A plurality of third connection lines CL 3  may connect third data lines DL 3 , which are other ones among the plurality of data lines DL, to a corresponding data pad (e.g., a third data pad DP 3 ) from among the plurality of data pads DP. 
     In an embodiment, the first connection lines CL 1 , the second connection lines CL 2 , and the third connection lines CL 3  may be arranged on different layers as illustrated in  FIGS.  6  to  13    which are described later. When the first connection lines CL 1 , the second connection lines CL 2 , and the third connection lines CL 3  are arranged on different layers from each other, compared to when the third connection lines CL 3  are arranged on a same layer as the first connection lines CL 1  or the second connection lines CL 2 , respective widths of the first connection line CL 1 , the second connection lines CL 2 , and the third connection lines CL 3  may be adjusted freely. For example, respective widths of the first connection lines CL 1 , the second connection lines CL 2 , and the third connection lines CL 3  may be increased. When the respective widths of the first connection lines CL 1 , the second connection lines CL 2 , and the third connection lines CL 3  are increased, respective resistances of the first connection lines CL 1 , the second connection lines CL 2 , and the third connection lines CL 3  may be decreased. This will be described in further detail with reference to  FIGS.  6  to  13   . 
       FIG.  3    is an equivalent circuit diagram illustrating a pixel arranged in a display apparatus, according to an embodiment of the present disclosure. 
     Referring to  FIG.  3   , one pixel PX may include a pixel circuit PC and a display element electrically connected to the pixel circuit PC. The display element may include an organic light-emitting diode OLED having an anode (or pixel electrode) and a cathode (or counter electrode). 
     For example, as illustrated in  FIG.  3   , the pixel circuit PC may include first to ninth transistors T 1  to T 9 , a first capacitor C 1 , and a second capacitor C 2 . The first to ninth transistors T 1  to T 9 , the first capacitor C 1 , and the second capacitor C 2  are connected to first to fourth scan lines GWL, GCL, GIL, and GBL configured to respectively transfer first to fourth scan signals GW, GC, GI, and GB, the data line DL configured to transfer a data voltage Dm, the emission control line EML configured to transfer an emission control signal EM, the power line PL configured to transfer the first driving voltage ELVDD, a first voltage line VL 1  configured to transfer an initialization voltage Vint, a second voltage line VL 2  configured to transfer a reference voltage Vref, a third voltage line VL 3  configured to transfer a bias voltage Vbias, and a common electrode to which the second driving voltage ELVSS is applied. 
     The first transistor T 1  may include a driving transistor, a drain current of which is determined according to a gate-source voltage, and the second to ninth transistors T 2  to T 9  may include switching transistors that are turned on or off according to a gate-source voltage, substantially according to a gate voltage. The first to ninth transistors T 1  to T 9  may include thin-film transistors. 
     Some of the first to ninth transistors T 1  to T 9  may be n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) (NMOS), and the others may be p-channel MOSFETs (PMOS). For example, as illustrated in  FIG.  3   , from among the first to ninth transistors T 1  to T 9 , the second transistor T 2 , the third transistor T 3 , the fourth transistor T 4 , and the eighth transistor T 8  may be NMOS, and the others may be PMOS. Alternatively, from among the first to ninth transistors T 1  to T 9 , the third transistor T 3 , the fourth transistor T 4 , and the eighth transistor T 8  may be NMOS, and the others may be PMOS. 
     One of the first to ninth transistors T 1  to T 9  may be NMOS, and the others may be PMOS. Alternatively, all of the first to ninth transistors T 1  to T 9  may be NMOS or PMOS. 
     The first capacitor C 1  and the second capacitor C 2  are connected between the power line PL and a gate of the first transistor T 1 . The first capacitor C 1  may have a first lower electrode CE 1  connected to the gate of the first transistor T 1  and a first upper electrode CE 2  connected to a second lower electrode CE 3  of the second capacitor C 2 . The second capacitor C 2  may have the second lower electrode CE 3  connected to the first upper electrode CE 2  of the first capacitor C 1  and a second upper electrode CE 4  connected to the power line PL. 
     As illustrated in  FIG.  4   , the first capacitor C 1  and the second capacitor C 2  may at least partially overlap each other. For example, the first upper electrode CE 2  of the first capacitor C 1  may function as the second lower electrode CE 3  of the second capacitor C 2 . For example, the second lower electrode CE 3  of the second capacitor C 2  may function as the first upper electrode CE 2  of the first capacitor C 1 . 
     Referring back to  FIG.  3   , the first transistor T 1  may control the magnitude of a driving current Id flowing from the power line PL to the organic light-emitting diode OLED according to the gate-source voltage. The first transistor T 1  may have the gate connected to the first lower electrode CE 1  of the first capacitor C 1 , a source connected to the power line PL through the fifth transistor T 5 , and a drain connected to the organic light-emitting diode OLED through the sixth transistor T 6 . 
     The first transistor T 1  may output the driving current Id to the organic light-emitting diode OLED according to the gate-source voltage. The magnitude of the driving current Id is determined based on a difference between the gate-source voltage of the first transistor T 1  and a threshold voltage. The organic light-emitting diode OLED may receive the driving current Id from the first transistor T 1  and emit light with a brightness according to the magnitude of the driving current Id. 
     The second transistor T 2  may connect the data line DL to the first upper electrode CE 2  of the first capacitor C 1  (or the second lower electrode CE 3  of the second capacitor C 2 ) in response to the first scan signal GW. The second transistor T 2  may transfer the data voltage Dm to the first upper electrode CE 2  of the first capacitor C 1  (or the second lower electrode CE 3  of the second capacitor C 2 ) in response to the first scan signal GW. 
     The third transistor T 3  may connect the drain and the gate of the first transistor T 1  to each other in response to the second scan signal GC. The third transistor T 3  may be connected in series between the drain and the gate of the first transistor T 1 . 
     The fourth transistor T 4  may connect the first voltage line VL 1  to the gate of the first transistor T 1 , in response to the third scan signal GI. The fourth transistor T 4  may apply the initialization voltage Vint to the gate of the first transistor T 1  in response to the third scan signal GI. 
     The fifth transistor T 5  may connect the power line PL to the source of the first transistor T 1  in response to the emission control signal EM. The fifth transistor T 5  may connect the power line PL and the source of the first transistor T 1  to each other in response to the emission control signal EM. 
     The sixth transistor T 6  may connect the drain of the first transistor T 1  to the anode of the organic light-emitting diode OLED in response to the emission control signal EM. The sixth transistor T 6  may connect the drain of the first transistor T 1  and the anode of the organic light-emitting diode OLED to each other in response to the emission control signal EM. 
     While the fifth transistor T 5  and the sixth transistor T 6  are illustrated as operating in response to the same light emission control signal EM, in an embodiment of the present disclosure, the fifth transistor T 5  and the sixth transistor T 6  may operate in response to different light emission control signals, respectively. For example, the fifth transistor T 5  may have a gate connected to a first emission control line and may connect the power line PL to the source of the first transistor T 1  in response to a first emission control signal. The sixth transistor T 6  may have a gate connected to a second emission control line and may connect the drain of the first transistor T 1  to the anode of the organic light-emitting diode OLED in response to a second emission control signal. 
     The seventh transistor T 7  may connect the first voltage line VL 1  to the anode of the organic light-emitting diode OLED in response to the fourth scan signal GB. The seventh transistor T 7  may apply the initialization voltage Vint to the anode of the organic light-emitting diode OLED in response to the fourth scan signal GB. 
     The eighth transistor T 8  may connect the second voltage line VL 2  to the first upper electrode CE 2  of the first capacitor C 1  (or the second lower electrode CE 3  of the second capacitor C 2 ) in response to the second scan signal GC. The eighth transistor T 8  may apply the reference voltage Vref to the first upper electrode CE 2  of the first capacitor C 1  (or the second lower electrode CE 3  of the second capacitor C 2 ) in response to the second scan signal GC. 
     While the third transistor T 3  and the eighth transistor T 8  are illustrated as operating in response to the same second scan signal GC in  FIG.  3   , in an embodiment of the present disclosure, the third transistor T 3  and the eighth transistor T 8  may operate in response to different scan signals, respectively. 
     The ninth transistor T 9  may connect the third voltage line VL 3  to the source of the first transistor T 1  in response to the fourth scan signal GB. The ninth transistor T 9  may apply the bias voltage Vbias to the source of the first transistor T 1  in response to the fourth scan signal GB. 
     While the seventh transistor T 7  and the ninth transistor T 9  are illustrated as operating in response to the same fourth scan signal GB, in an embodiment of the present disclosure, the seventh transistor T 7  and the ninth transistor T 9  may operate in response to different scan signals, respectively. 
     The second scan signal GC may be substantially synchronized with the first scan signal GW. The third scan signal GI may be substantially synchronized with the first scan signal GW of a previous row. The fourth scan signal GB may be substantially synchronized with the first scan signal GW. According to an example embodiment of the present disclosure, the fourth scan signal GB may be substantially synchronized with the first scan signal GW of a next row or the third scan signal GI of a next row. 
     In an embodiment, the first to ninth transistors T 1  to T 9  may include a semiconductor layer including silicon. For example, the first to ninth transistors T 1  to T 9  may include a semiconductor layer including low temperature poly-silicon (LTPS). A polysilicon material has high electron mobility (100 cm 2 /Vs or more), and thus has low energy consumption and excellent reliability. 
     For example, semiconductor layers of the first to ninth transistors T 1  to T 9  may include an oxide of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce) and/or zinc (Zn). For example, the semiconductor layers may include an InSnZnO (ITZO) semiconductor layer, an InGaZnO (IGZO) semiconductor layer, or the like. 
     For example, some semiconductor layers from among the first to ninth transistors T 1  to T 9  may include LTPS, and some other semiconductor layers may include an oxide semiconductor (e.g., IGZO). 
       FIG.  4    is a cross-sectional view schematically illustrating a portion of a pixel, according to an embodiment of the present disclosure.  FIG.  4    is an exemplary cross-sectional view of a portion of a pixel according to an embodiment of the present disclosure, and to the extent that a detailed description of an element is omitted, it may be assumed that the element is at least similar to a corresponding element that has been described elsewhere within the specification. 
     Referring to  FIG.  4   , a first thin-film transistor TFT 1 , a second thin-film transistor TFT 2 , a first capacitor C 1 , and a second capacitor C 2  may be arranged in the display area DA. The first thin-film transistor TFT 1  may correspond to the first transistor T 1  of  FIG.  3   , and the second thin-film transistor TFT 2  corresponds to the second transistor T 2 , the third transistor T 3 , the fourth transistor T 4  or the eighth transistor T 8  of  FIG.  3   . 
     The first thin-film transistor TFT 1  may include a first semiconductor layer Act 1  and a first electrode E 1  that at least partially overlaps the first semiconductor layer Act 1 . The first electrode E 1  corresponds to a gate (or a gate electrode) of the first thin-film transistor TFT 1 . 
     The second thin-film transistor TFT 2  may include a second semiconductor layer Act 2  and a fifth electrode E 5  that at least partially overlaps the second semiconductor layer Act 2 . The fifth electrode E 5  corresponds to a gate (or gate electrode) of the second thin-film transistor TFT 2 . The second thin-film transistor TFT 2  may be arranged over the first thin-film transistor TFT 1 . 
     In an embodiment, a conductivity type of the first thin-film transistor TFT 1  may be opposite to a conductivity type of the second thin-film transistor TFT 2 . For example, the first thin-film transistor TFT 1  may be a PMOS, and the second thin-film transistor TFT 2  may be NMOS. 
     In an embodiment, the first semiconductor layer Act 1  of the first thin-film transistor TFT 1  and the second semiconductor layer Act 2  of the second thin-film transistor TFT 2  may include different materials from each other. For example, the first semiconductor layer Act 1  may include a silicon semiconductor material, and the second semiconductor layer Act 2  may include an oxide semiconductor material. 
     The first capacitor C 1  may include a first electrode E 1  and a second electrode E 2  that at least partially overlaps the first electrode E 1 . The first capacitor C 1  may at least partially overlap the first thin-film transistor TFT 1 . For example, the first electrode E 1  may function as the first lower electrode CE 1  of the first capacitor C 1 . For example, the first electrode E 1  may correspond to the first lower electrode CE 1  of the first capacitor C 1 . 
     The second capacitor C 2  may include a second electrode E 2  and a third electrode E 3  that at least partially overlaps the second electrode E 2 . The second capacitor C 2  may at least partially overlap the first capacitor C 1 . For example, the second electrode E 2  may function as the first upper electrode CE 2  of the first capacitor C 1  and function as the second lower electrode CE 3  of the second capacitor C 2 . For example, the second electrode E 2  may correspond to the first upper electrode CE 2  of the first capacitor C 1  and may correspond to the second lower electrode CE 3  of the second capacitor C 2 . 
     As in an embodiment of the present disclosure, when the first capacitor C 1  and the second capacitor C 2  overlap each other in a ±z direction (e.g., the depth direction), the number of pixels that may be arranged in a xy plane may be increased compared to when the first capacitor C 1  and the second capacitor C 2  do not overlap each other and are provided separately. As the number of pixels arranged on the xy plane per unit area may be increased, a resolution of the display apparatus may be increased. The resolution of the display apparatus may be increased. 
     While  FIG.  4    illustrates that a width of the first electrode E 1  and a width of the second electrode E 2  are the same, and a width of the second electrode E 2  and a width of the third electrode E 3  are different from each other, but this is only an example and various other modifications may be made. 
     Hereinafter, elements included in the display apparatus will be described in further detail according to a stack structure. 
     The substrate  100  may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. When the substrate  100  has flexible or bendable characteristics, the substrate  100  may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate or cellulose acetate propionate. 
     The substrate  100  may have a single-layer or multi-layer structure of the material, and when substrate  100  has a multi-layer structure, an inorganic layer may be further included. In some embodiments, the substrate  100  may have an organic material/inorganic material/organic material structure. 
     A barrier layer may be further disposed between the substrate  100  and a buffer layer  110 . The barrier layer may have a function of preventing or minimizing penetration of impurities from the substrate  100  or the like into the first semiconductor layer Act 1  and the second semiconductor layer Act 2 . The barrier layer may include an inorganic material such as an oxide or nitride, an organic material, or an organic-inorganic composite material, and may have a single-layer or multi-layer structure of an inorganic material and an organic material. 
     A bottom metal layer BML may be between the substrate  100  and the buffer layer  110 . The bottom metal layer BML may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and/or the like, and may have a multi-layer or single-layer structure including the above material. 
     The bottom metal layer BML may at least partially overlap the first semiconductor layer Act 1 . The bottom metal layer BML may have a function of protecting the first semiconductor layer Act 1 . The bottom metal layer BML may receive an arbitrary (or preset) voltage. Through the bottom metal layer BML to which an arbitrary voltage is applied, when driving a pixel circuit including an NMOS and a PMOS through the bottom metal layer BML, to which an arbitrary voltage is applied, accumulation of unnecessary charges in the first semiconductor layer Act 1  may be prevented. As a result, characteristics of the first thin-film transistor TFT 1  including the first semiconductor layer Act 1  may be maintained stably. 
     The first semiconductor layer Act 1  may be arranged on the buffer layer  110 . The first semiconductor layer Act 1  may include amorphous silicon or polysilicon. The first semiconductor layer Act 1  may include a channel region, a source region, and a drain region arranged on opposite sides of the channel region. The source region and the drain region may be regions doped by adding a dopant. The first semiconductor layer Act 1  may include a single layer or multiple layers. 
     A first insulating layer  111  and a second insulating layer  113  may be stacked on the substrate  100  to cover the first semiconductor layer Act 1 . The first insulating layer  111  and the second insulating layer  113  may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), and/or zinc oxide (ZnO x ), or the like. Zinc oxide (ZnO x ) may include zinc oxide (ZnO) and/or zinc peroxide (ZnO 2 ). 
     The first electrode E 1  may be arranged on the first insulating layer  111 . The first electrode E 1  may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like, and may have a multi-layer or single-layer structure including the above material. 
     The second electrode E 2  may be arranged on the second insulating layer  113 . The second electrode E 2  may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti), and the like, and may have a multi-layer or single-layer structure including the above material. 
     The first electrode E 1  and the second electrode E 2  overlap each other with the second insulating layer  113  therebetween, and form capacitance. Here, the second insulating layer  113  may act as a dielectric layer of the first capacitor C 1 . 
     A third insulating layer  115  may arranged on the second insulating layer  113  to cover the second electrode E 2 . The third insulating layer  115  may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), and/or zinc oxide (ZnO x ), or the like. Zinc oxide (ZnO x ) may include zinc oxide (ZnO) and/or zinc peroxide (ZnO 2 ). 
     A third electrode E 3  and a fourth electrode E 4  may be arranged on the third insulating layer  115 . The third electrode E 3  and the fourth electrode E 4  may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti), and the like, and may have a multi-layer or single-layer structure including the above material. 
     The second electrode E 2  and the third electrode E 3  overlap each other with the third insulating layer  115  disposed therebetween, and this structure may form capacitance. Here, the third insulating layer  115  may act as a dielectric layer of the second capacitor C 2 . 
     The fourth electrode E 4  may at least partially overlap the second semiconductor layer Act 2 . The fourth electrode E 4  may have a function of protecting the second semiconductor layer Act 2 . The fourth electrode E 4  may be electrically connected to the fifth electrode E 5  through a second connection electrode CM 2  described later. 
     In  FIG.  4   , the fourth electrode E 4  is illustrated as being arranged on the same layer as the third electrode E 3 . Alternatively, the fourth electrode E 4  may be arranged on the same layer as the second electrode E 2 . This will be described later with reference to  FIG.  5   . 
     A fourth insulating layer  117  may be arranged on the third insulating layer  115  to cover the third electrode E 3  and the fourth electrode E 4 . The fourth insulating layer  117  may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), and/or zinc oxide (ZnO x ), or the like. Zinc oxide (ZnO x ) may include zinc oxide (ZnO) and/or zinc peroxide (ZnO 2 ). 
     The second semiconductor layer Act 2  may be arranged on the fourth insulating layer  117 . The second semiconductor layer Act 2  may include an oxide semiconductor material. The second semiconductor layer Act 2  may include an oxide such as indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and/or zinc (Zn). 
     For example, the second semiconductor layer Act 2  may include an ITZO semiconductor layer, an IGZO semiconductor layer, or the like. An oxide semiconductor has a wide band gap (about 3.1 eV), and thus high carrier mobility and a low leakage current, and accordingly the voltage drop thereof is not large despite a long driving time, and thus, the luminance thereof according to the voltage drop is not changed greatly even during low-frequency driving. 
     The second semiconductor layer Act 2  may include a channel region, a source region, and a drain region arranged on opposite sides of the channel region. The second semiconductor layer Act 2  may include a single layer or multiple layers. 
     As described above, the fourth electrode E 4  may be arranged under the second semiconductor layer Act 2 . The second semiconductor layer Act 2  including an oxide semiconductor material is vulnerable to light, and thus, the second semiconductor layer Act 2  may be protected through the fourth electrode E 4 . The fourth electrode E 4  may have a function of preventing a change in device characteristics of the second thin-film transistor TFT 2  including an oxide semiconductor, as a photocurrent is induced in the second semiconductor layer Act 2  by external light incident from the side of the substrate  100 . 
     A fifth insulating layer  119  may be arranged on the second semiconductor layer Act 2 . The fifth insulating layer  119  may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), and/or zinc oxide (ZnO x ), or the like. Zinc oxide (ZnO x ) may include zinc oxide (ZnO) and/or zinc peroxide (ZnO 2 ). 
     While  FIG.  4    illustrates that the fifth insulating layer  119  is arranged on the entire surface of the substrate  100  to cover the second semiconductor layer Act 2 , in an embodiment of the present disclosure, the fifth insulating layer  119  may be patterned to overlap a portion of the second semiconductor layer Act 2 . For example, the fifth insulating layer  119  may be patterned to overlap the channel region of the second semiconductor layer Act 2 . 
     The fifth electrode E 5  may be arranged on the fifth insulating layer  119 . The fifth electrode E 5  may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti), and the like, and may have a multi-layer or single-layer structure including the above material. 
     A sixth insulating layer  121  may arranged on the fifth insulating layer  119  to cover the fifth electrode E 5 . The sixth insulating layer  121  may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), and/or zinc oxide (ZnO x ), or the like. Zinc oxide (ZnO x ) may include zinc oxide (ZnO) and/or zinc peroxide (ZnO 2 ). 
     A first connection electrode CM 1 , the second connection electrode CM 2 , and a third connection electrode CM 3  may be arranged on the sixth insulating layer  121 . The first connection electrode CM 1 , the second connection electrode CM 2 , and the third connection electrode CM 3  may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti), and the like, and include a multi-layer or single layer structure including the above material. For example, the first connection electrode CM 1 , the second connection electrode CM 2 , and the third connection electrode CM 3  may have a multi-layer structure of Ti/Al/Ti. 
     The first connection electrode CM 1  may be connected to the first semiconductor layer Act 1  through a first contact hole CNT 1  formed in the first to sixth insulating layers  111 ,  113 ,  115 ,  117 ,  119 , and  121 . A portion of the first connection electrode CM 1  may be buried in the first contact hole CNT 1 , and the first connection electrode CM 1  and the first semiconductor layer Act 1  may be connected to each other. 
     The second connection electrode CM 2  may be connected to the fourth electrode E 4  through a second contact hole CNT 2  formed in the fourth to sixth insulating layers  117 ,  119 , and  121 . A portion of the second connection electrode CM 2  may be buried in the second contact hole CNT 2 , and the second connection electrode CM 2  and the fourth electrode E 4  may be connected to each other. The second connection electrode CM 2  may be connected to the fifth electrode E 5  through a third contact hole CNT 3  formed in the sixth insulating layer  121 . A portion of the second connection electrode CM 2  may be buried in the third contact hole CNT 3 , and the third connection electrode CM 3  and the fifth electrode E 5  may be connected to each other. The second connection electrode CM 2  may act as a bridge connecting the fourth electrode E 4  to the fifth electrode E 5 . 
     The third connection electrode CM 3  may be connected to the third electrode E 3  through a fourth contact hole CNT 4  formed in the fourth to sixth insulating layers  117 ,  119 , and  121 . A portion of the third connection electrode CM 3  may be buried in the fourth contact hole CNT 4 , and the third connection electrode CM 3  and the third electrode E 3  may be connected to each other. 
     A first planarization layer  123  and a second planarization layer  125  may be stacked on the sixth insulating layer  121 . The first planarization layer  123  and the second planarization layer  125  may be formed as a single layer or a multilayer structure including an organic material and may provide a flat upper surface. The first planarization layer  123  and the second planarization layer  125  may include general-purpose polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, acrylic polymer, imide-based polymer, arylether-based polymer, amide-based polymer, fluorine-based polymer, p-xylene-based polymer, vinyl alcohol-based polymer, or a blend thereof. 
     A fourth connection electrode CM 4  and the power line PL may be arranged on the first planarization layer  123 . The fourth connection electrode CM 4  and the power line PL may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like, and may have a multi-layer or single-layer structure including the above material. For example, the fourth connection electrode CM 4  and the power line PL may have a multilayer structure of Ti/Al/Ti. 
     The fourth connection electrode CM 4  may be connected to the first connection electrode CM 1  through a fifth contact hole CNT 5  formed in the first planarization layer  123 . A portion of the fourth connection electrode CM 4  may be buried in the fifth contact hole CNT 5 , and the fourth connection electrode CM 4  and the first connection electrode CM 1  may be connected to each other. The fourth connection electrode CM 4  may be connected to the first semiconductor layer Act 1  through the first connection electrode CM 1 . 
     The power line PL may be connected to the third connection electrode CM 3  through a sixth contact hole CNT 6  formed in the first planarization layer  123 . A portion of the power line PL may be buried in the sixth contact hole CNT 6 , and the power line PL and the third connection electrode CM 3  may be connected to each other. The power line PL may be connected to the third electrode E 3  through the third connection electrode CM 3 . 
     A display element  200  may be arranged on the second planarization layer  125 . The display element  200  may include a pixel electrode  210 , an intermediate layer  220  including an organic emission layer, and an opposite electrode  230 . 
     The pixel electrode  210  may include a transmissive or semi-transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode  210  may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and/or aluminum zinc oxide (AZO). In some embodiments, the pixel electrode  210  may have an ITO/Ag/ITO structure. 
     The pixel electrode  210  may be connected to the fourth connection electrode CM 4  through the sixth contact hole CNT 6  formed in the second planarization layer  125 . A portion of the pixel electrode  210  may be buried in the sixth contact hole CNT 6 , and the pixel electrode  210  and the fourth connection electrode CM 4  may be connected to each other. The pixel electrode  210  may be electrically connected to the first semiconductor layer Act 1  through the fourth connection electrode CM 4  and the first connection electrode CM 1 . 
     A pixel defining layer  127  may be arranged on the second planarization layer  125 . The pixel defining layer  127  may increase a distance between the edges of the pixel electrode  210  and the opposite electrode  230  above the pixel electrode  210  to thereby prevent arcing of electricity, or the like, at the edges of the pixel electrode  210 . 
     The pixel defining layer  127  may include at least one organic insulating material such as polyimide, polyamide, acrylic resin, BCB, and/or phenol resin, and may be formed by spin coating or the like. The pixel defining layer  127  may include an organic insulating material. Alternatively, the pixel defining layer  127  may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and/or silicon oxide. Alternatively, the pixel defining layer  127  may include an organic insulating material and an inorganic insulating material. In some embodiments, the pixel defining layer  127  may include a light-blocking material and may be black. The light-blocking material may include carbon black, carbon nanotubes, a resin or paste containing a black dye, metal particles such as nickel, aluminum, molybdenum and alloys thereof, metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride) and the like. When the pixel defining layer  127  includes a light-blocking material, reflection of external light by metal structures arranged below the pixel defining layer  127  may be reduced. 
     The intermediate layer  220  may be arranged in an opening formed by the pixel defining layer  127 . The intermediate layer  220  may include an organic emission layer. The organic emission layer may include an organic material including a fluorescent or phosphorescent material, which emit red, green, blue, or white light. The organic emission layer may include a low molecular weight organic material or a polymer organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL) may be selectively further arranged below and above the organic emission layer. 
     The intermediate layer  220  may be arranged to correspond to each of a plurality of pixel electrodes  210 . However, the present disclosure is not necessarily limited thereto. Various modifications may be made to the intermediate layer  220 ; for example, the intermediate layer  220  may include a single layer over the plurality of pixel electrodes  210 . 
     The opposite electrode  230  may include a transmissive electrode or a reflective electrode. In some embodiments, the opposite electrode  230  may include a transparent or semi-transparent electrode and may include a metal thin-film having a small work function and including Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, and compounds thereof. As understood herein, a small work function is understood to be any work function that is equal to or smaller than the work function of the aforementioned substances. Also, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO or In 2 O 3  may be further arranged on the metal thin-film. The opposite electrode  230  may be arranged over the display area DA, and may be arranged on the intermediate layer  220  and the pixel defining layer  127 . The opposite electrode  230  may be formed integrally with respect to a plurality of display elements  200  to correspond to the plurality of pixel electrodes  210 . 
     The display element  200  may be covered by an encapsulation layer. The encapsulation layer may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. The at least one inorganic encapsulation layer may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and/or silicon oxynitride. The at least one inorganic encapsulation layer may include a single layer or multiple layers including the above-described material. The at least one organic encapsulation layer may include a polymer-based material. The polymer-based material may include polymethyl methacrylate, an acrylic resin such as polyacrylic acid, an epoxy resin, polyimide, polyethylene, and the like. In an embodiment, the at least one organic encapsulation layer may include an acrylate polymer. 
     While the first to sixth insulating layers  111 ,  113 ,  115 ,  117 ,  119 , and  121  are illustrated as each having the same thickness in  FIG.  4   , this is merely an example and various other modifications may be made. 
       FIG.  5    is a cross-sectional view schematically illustrating a portion of a pixel, according to an embodiment of the present disclosure.  FIG.  5    is a modified embodiment of  FIG.  4   , and there is a difference in the structure of a fourth electrode. Hereinafter, for repeated details, the description provided with reference to  FIG.  4    will be referred to, and description will focus on differences. 
     Referring to  FIG.  5   , a fourth electrode E 4 ′ may be arranged on the second insulating layer  113 . The fourth electrode E 4 ′ may be arranged on the same layer as the second electrode E 2 . 
     The second connection electrode CM 2  may be connected to the fourth electrode E 4 ′ through a second contact hole CNT 2 ′ formed in the third to sixth insulating layers  115 ,  117 ,  119 , and  121 . A portion of the second connection electrode CM 2  may be buried in the second contact hole CNT 2 ′, and the second connection electrode CM 2  and the fourth electrode E 4 ′ may be connected to each other. 
     In an embodiment, the first to fourth contact holes CNT 1 , CNT 2 , CNT 3 , and CNT 4  might not be formed at the same time. For example, after forming the first contact hole CNT 1  and the second contact hole CNT 2 ′, the third contact hole CNT 3  and the fourth contact hole CNT 4  may be formed. A depth of each of the first contact hole CNT 1  and the second contact hole CNT 2 ′ may be greater than a depth of each of the third contact hole CNT 3  and the fourth contact hole CNT 4 . When contact holes having different depths are simultaneously formed, a surface of a conductive layer exposed by contact holes having a relatively small depth may be damaged. However, when the contact holes having different depths are separately formed, instead of forming the same at the same time as in the embodiment, damage to the surface of the conductive layer exposed by the contact holes may be prevented. 
       FIG.  6    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure. In detail,  FIG.  6    is a cross-sectional view of a portion of the display panel  10  of  FIG.  2    cut along line X-X′, and some members may be omitted therein. In  FIG.  6   , like reference numerals as those of  FIG.  4    may denote like elements, and thus, to the extent that a detailed description of an element is omitted, it may be assumed that the element is at least similar to a corresponding element that has been described elsewhere within the specification. 
     Referring to  FIG.  6   , a plurality of connection lines CL and the first sub-wiring  162  may be arranged in the peripheral area PA. 
     The plurality of connection lines CL may connect the plurality of data lines DL to a corresponding data pad DP among the plurality of data pads DP of the pad portion  140  as described above with reference to  FIG.  2   . For example, the plurality of connection lines CL may include the first connection lines CL 1 , the second connection lines CL 2 , and the third connection lines CL 3 . The first connection lines CL 1  may connect the first data lines DL 1 , which are some of the plurality of data lines DL, to a corresponding data pad (e.g., the first data pad DP 1 ) from among the plurality of data pads DP. The second connection lines CL 2  may connect the second data lines DL 2 , which are some others among the plurality of data lines DL, to a corresponding data pad (e.g., the second data pad DP 2 ) from among the plurality of data pads DP. The third connection lines CL 3  may connect the third data lines DL 3 , which are some others among the plurality of data lines DL, to a corresponding data pad (e.g., the third data pad DP 3 ) from among the plurality of data pads DP. 
     In an embodiment, the plurality of first connection lines CL 1  and the plurality of second connection lines CL 2  may be arranged between two third connection lines CL 3  that are adjacent to each other in the first direction (e.g., ±x direction) from among the third connection lines CL 3 . The plurality of first connection lines CL 1  and the plurality of second connection lines CL 2  may be alternately arranged in the first direction (e.g., the ±x direction). 
     In an embodiment, the number of third connection lines CL 3  per unit area may be greater than the number of first connection lines CL 1  per unit area. The number of third connection lines CL 3  per unit area may be greater than the number of second connection lines CL 2  per unit area. 
     In an embodiment, the number of first connection lines CL 1  per unit area may be the same as the number of second connection lines CL 2  per unit area. 
     In an embodiment, the first connection lines CL 1 , the second connection lines CL 2 , and the third connection lines CL 3  may be arranged on different layers from each other. For example, the second connection lines CL 2  may be arranged over the first connection lines CL 1 , and the third connection lines CL 3  may be arranged over the second connection lines CL 2 . As illustrated in  FIG.  6   , the first connection lines CL 1  may be arranged on the first insulating layer  111 , the second connection lines CL 2  may be arranged on the third insulating layer  115 , and the third connection lines CL 3  may be arranged on the fifth insulating layer  119 . For example, the first connection lines CL 1  may be arranged on the same layer as the first electrode E 1  (see  FIG.  4   ), and the second connection lines CL 2  may be arranged on the same layer as the third electrode E 3  (see  FIG.  4   ), and the third connection lines CL 3  may be arranged on the same layer as the fourth electrode E 4  (refer to  FIG.  4   ). 
     While  FIG.  6    illustrates that the first connection lines CL 1  are arranged on the same layer as the first electrode E 1 , the second connection lines CL 2  are arranged on the same layer as the third electrode E 3 , and the third connection lines CL 3  are arranged on the same layer as the fourth electrode E 4 , this is only an example and various modifications may be made. This will be described in further detail with reference to  FIGS.  9  to  13   . 
     In addition, although  FIG.  6    illustrates that the second connection lines CL 2  and the third connection lines CL 3  at least partially overlap each other, in an embodiment of the present disclosure, the second connection lines CL 2  and the third connection lines CL 3  might not overlap each other. Alternatively, the first connection lines CL 1  and the third connection lines CL 3  may at least partially overlap each other. Alternatively, the first connection lines CL 1  and the third connection lines CL 3  might not overlap each other. 
     When the first connection lines CL 1 , the second connection lines CL 2 , and the third connection lines CL 3  are arranged on different layers as in an embodiment of the present disclosure, the number of connection lines CL arranged on each layer may be reduced compared to when the third connection lines CL 3  are arranged on the same layer as the first connection lines CL 1  or the second connection lines CL 2 . When the connection lines CL are arranged on three different layers, the number of connection lines CL arranged on each layer may be reduced. As the number of connection lines CL arranged on each layer is reduced, a width of each of the connection lines CL may be freely changed. For example, the width of each of the connection lines CL may be increased. When a first width w 1  of each of the first connection lines CL 1  arranged between the first insulating layer  111  and the second insulating layer  113  is increased, the resistance of each of the first connection lines CL 1  may be decreased. When a second width w 2  of each of the second connection lines CL 2  arranged between the third insulating layer  115  and the fourth insulating layer  117  is increased, the resistance of each of the second connection lines CL 2  may be decreased. When a third width w 3  of each of the third connection lines CL 3  arranged between the fifth insulating layer  119  and the sixth insulating layer  121  is increased, the resistance of each of the third connection lines CL 3  may be decreased. 
     The first sub-wiring  162  may include a 1-1 th  sub-wiring  162   a  and a 1-2 th  sub-wiring  162   b  that are spaced apart by the first planarization layer  123 . Although not illustrated in  FIG.  6   , the 1-1 th  sub-wiring  162   a  and the 1-2 th  sub-wiring  162   b  may be electrically connected to each other. 
     Although  FIG.  6    illustrates that the first planarization layer  123  is arranged in the peripheral area PA, alternatively, at least a portion of the first planarization layer  123  may be omitted in the peripheral area PA. 
     Also, while  FIG.  6    illustrates that the first sub-wiring  162  includes the 1-1 th  sub-wiring  162   a  and the 1-2 th  sub-wiring  162   b , alternatively, one of the 1-1 th  sub-wiring  162   a  and the 1-2 th  sub-wiring  162   b  may be omitted. 
     As the third connection line CL 3  and the 1-1 th  sub-wiring  162   a  are not connected to each other by the sixth insulating layer  121 , an additional insulating layer might not be additionally arranged as illustrated in  FIG.  12    described later. Accordingly, a mask for arranging an additional insulating layer might not be added. 
       FIG.  7    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure.  FIG.  7    is a modified embodiment of  FIG.  6   , and there is a difference in the structure of the second connection lines and the third connection lines. Hereinafter, for repeated details, the description provided with reference to  FIG.  6    will be referred to, and description will focus on differences. 
     Referring to  FIG.  7   , the second connection lines CL 2  and the third connection lines CL 3  may have a multi-layered structure. For example, each of the second connection lines CL 2  may include a first layer L 1   a , a third layer L 3   a  above the first layer L 1   a , and second layer L 2   a  between the first layer L 1   a  and the third layer L 3   a . Each of the third connection lines CL 3  may include a first layer L 1   b , a third layer L 3   b  above the first layer L 1   b , and a second layer L 2   b  between the first layer L 1   b  and the third layer L 3   b.    
     The first layers L 1   a  and L 1   b , the second layers L 2   a  and L 2   b , and the third layers L 3   a  and L 3   b  may include a conductive material including molybdenum (Mo), aluminum (Al), an aluminum alloy (Al-alloy), copper (Cu), titanium (Ti), titanium nitride (TiN), and/or niobium (Nb), or the like. For example, the first layers L 1   a  and L 1   b  may include titanium (Ti), the second layers L 2   a  and L 2   b  may include aluminum (Al), and the third layers L 3   a  and L 3   b  may include titanium (Ti). In this case, the respective resistances of the second connection lines CL 2  and the third connection lines CL 3  may decrease. 
     While  FIG.  7    illustrates that each of the second connection lines CL 2  and each of the third connection lines CL 3  includes three layers, in an embodiment of the present disclosure, the first layers L 1   a  and L 1   b  may be omitted. 
       FIG.  8    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure.  FIG.  8    is a modified embodiment of  FIG.  6   , and there is a difference in the structure of the third connection lines. Hereinafter, for repeated details, the description provided with reference to  FIG.  6    will be referred to, and description will focus on differences. 
     Referring to  FIG.  8   , the third connection lines CL 3  may have a multi-layered structure. For example, each of the third connection lines CL 3  may include a first layer L 1   b , a third layer L 3   b  above the first layer L 1   b , and a second layer L 2   b  between the first layer L 1   b  and the third layer L 3   b.    
     The first layer L 1   b , the second layer L 2   b , and the third layer L 3   b  may include a conductive material including molybdenum (Mo), aluminum (Al), an aluminum alloy (Al-alloy), copper (Cu), titanium (Ti), titanium nitride (TiN), and/or niobium (Nb), or the like. For example, the first layer L 1   b  may include titanium (Ti), the second layer L 2   b  may include aluminum (Al), and the third layer L 3   b  may include titanium (Ti). In this case, the resistances of the third connection lines CL 3  may decrease. 
     While  FIG.  8    illustrates that each of the third connection lines CL 3  includes three layers, in an embodiment of the present disclosure, the first layer L 1   b  may be omitted. 
       FIG.  9    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure.  FIG.  9    is a modified embodiment of  FIG.  6   , and there is a difference in the structure of connection lines CLa. Hereinafter, for repeated details, the description provided with reference to  FIG.  6    will be referred to, and description will focus on differences. 
     Referring to  FIG.  9   , first connection lines CL 1   a , second connection lines CL 2   a , and third connection lines CL 3   a  may be arranged on different layers from each other. For example, the second connection lines CL 2   a  may be arranged over the first connection lines CL 1   a , and the third connection lines CL 3   a  may be arranged over the second connection lines CL 2   a . As illustrated in  FIG.  9   , the first connection lines CL 1   a  may be arranged on the first insulating layer  111 , the second connection lines CL 2   a  may be arranged on the second insulating layer  113 , and the third connection lines CL 3   a  may be arranged on the third insulating layer  115 . For example, the first connection lines CL 1   a  may be arranged on the same layer as the first electrode E 1  (see  FIG.  4   ), and the second connection lines CL 2   a  may be arranged on the same layer as the second electrode E 2  (see  FIG.  4   ), and the third connection lines CL 3   a  may be arranged on the same layer as the third electrode E 3  (see  FIG.  4   ). 
     When the connection lines CLa are arranged separately on three different layers from each other as in the embodiment, the number of the connection lines CLa arranged on each layer may be reduced. As the number of connection lines CLa arranged on each layer is reduced, a width of each of the connection lines CLa may be increased. According to the increase in the width of each connection line CLa, the resistance of each connection line CLa may be reduced. 
       FIG.  10    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure.  FIG.  10    is a modified embodiment of  FIG.  6   , and there is a difference in the structure of connection lines CLb. Hereinafter, for repeated details, the description provided with reference to  FIG.  6    will be referred to, and description will focus on differences. 
     Referring to  FIG.  10   , first connection lines CL 1   b , second connection lines CL 2   b , and third connection lines CL 3   b  may be arranged on different layers from each other. For example, the second connection lines CL 2   b  may be arranged over the first connection lines CL 1   b , and the third connection lines CL 3   b  may be arranged over the second connection lines CL 2   b . As illustrated in  FIG.  10   , the first connection lines CL 1   b  may be arranged on the first insulating layer  111 , the second connection lines CL 2   b  may be arranged on the second insulating layer  113 , and the third connection lines CL 3   b  may be arranged on the fifth insulating layer  119 . For example, the first connection lines CL 1   b  may be arranged on the same layer as the first electrode E 1  (see  FIG.  4   ), and the second connection lines CL 2   b  may be arranged on the same layer as the second electrode E 2  (see  FIG.  4   ), and the third connection lines CL 3   b  may be arranged on the same layer as the fourth electrode E 4  (see  FIG.  4   ). 
     When the connection lines CLb are arranged separately on three different layers from each other as in the embodiment, the number of the connection lines CLb arranged on each layer may be reduced. As the number of connection lines CLb arranged on each layer is reduced, a width of each of the connection lines CLb may be increased. According to the increase in the width of each connection line CLb, the resistance of each connection line CLb may be reduced. 
       FIG.  11    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure.  FIG.  11    is a modified embodiment of  FIG.  6   , and there is a difference in the structure of connection lines CLc. Hereinafter, for repeated details, the description provided with reference to  FIG.  6    will be referred to, and description will focus on differences. 
     Referring to  FIG.  11   , first connection lines CL 1   c , second connection lines CL 2   c , and third connection lines CL 3   c  may be arranged on different layers from each other. For example, the second connection lines CL 2   c  may be arranged over the first connection lines CL 1   c , and the third connection lines CL 3   c  may be arranged over the second connection lines CL 2   c . As illustrated in  FIG.  11   , the first connection lines CL 1   c  may be arranged on the second insulating layer  113 , the second connection lines CL 2   c  may be arranged on the third insulating layer  115 , and the third connection lines CL 3   c  may be arranged on the fifth insulating layer  119 . For example, the first connection lines CL 1   c  may be arranged on the same layer as the second electrode E 2  (see  FIG.  4   ), and the second connection lines CL 2   c  may be arranged on the same layer as the third electrode E 3  (see  FIG.  4   ), and the third connection lines CL 3   c  may be arranged on the same layer as the fourth electrode E 4  (see  FIG.  4   ). 
     When the connection lines CLc are arranged separately on three different layers from each other as in the embodiment, the number of the connection lines CLc arranged on each layer may be reduced. As the number of connection lines CLc arranged on each layer is reduced, a width of each of the connection lines CLc may be increased. According to the increase in the width of each connection line CLc, the resistance of each connection line CLc may be reduced. 
       FIG.  12    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure.  FIG.  12    is a modified embodiment of  FIG.  6   , and there is a difference in the structure of connection lines CLd. Hereinafter, for repeated details, the description provided with reference to  FIG.  6    will be referred to, and description will focus on differences. 
     Referring to  FIG.  12   , first connection lines CL 1   d , second connection lines CL 2   d , and third connection lines CL 3   d  may be arranged on different layers from each other. For example, the second connection lines CL 2   d  may be arranged over the first connection lines CL 1   d , and the third connection lines CL 3   d  may be arranged over the second connection lines CL 2   d . As illustrated in  FIG.  12   , the first connection lines CL 1   d  may be arranged on the first insulating layer  111 , the second connection lines CL 2   d  may be arranged on the second insulating layer  113 , and the third connection lines CL 3   d  may be arranged on the sixth insulating layer  121 . For example, the first connection lines CL 1   d  may be arranged on the same layer as the first electrode E 1  (see  FIG.  4   ), and the second connection lines CL 2   d  may be arranged on the same layer as the second electrode E 2  (see  FIG.  4   ), and the third connection lines CL 3   d  may be arranged on the same layer as the first connection electrode CM 1  (see  FIG.  4   ). 
     When the connection lines CLd are arranged separately on three different layers from each other as in the embodiment, the number of the connection lines CLd arranged on each layer may be reduced. As the number of connection lines CLd arranged on each layer is reduced, a width of each of the connection lines CLd may be increased. According to the increase in the width of each connection line CLd, the resistance of each connection line CLd may be reduced. 
     The first sub-wiring  162  may be arranged on the third connection line CL 3   d . In order to prevent the first sub-wiring  162  and the third connection line CL 3   d  from being connected to each other, a seventh insulating layer  122  may be arranged between the first sub-wiring  162  and the third connection line CL 3   d . The seventh insulating layer  122  may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), and/or zinc oxide (ZnO x ), or the like. Zinc oxide (ZnO x ) may include zinc oxide (ZnO) and/or zinc peroxide (ZnO 2 ). 
       FIG.  13    is a cross-sectional view schematically illustrating connection lines according to an embodiment of the present disclosure.  FIG.  13    is a modified embodiment of  FIG.  12   , and there is a difference in the structure of connection lines CLe. Hereinafter, for repeated details, the description provided with reference to  FIG.  12    will be referred to, and description will focus on differences. 
     Referring to  FIG.  13   , first connection lines CL 1   e , second connection lines CL 2   e , and third connection lines CL 3   e  may be arranged on different layers from each other. For example, the second connection lines CL 2   e  may be arranged over the first connection lines CL 1   e , and the third connection lines CL 3   e  may be arranged over the second connection lines CL 2   e . As illustrated in  FIG.  13   , the first connection lines CL 1   e  may be arranged on the first insulating layer  111 , the second connection lines CL 2   e  may be arranged on the third insulating layer  115 , and the third connection lines CL 3   e  may be arranged on the sixth insulating layer  121 . For example, the first connection lines CL 1   e  may be arranged on the same layer as the first electrode E 1  (see  FIG.  4   ), and the second connection lines CL 2   e  may be arranged on the same layer as the third electrode E 3  (see  FIG.  4   ), and the third connection lines CL 3   e  may be arranged on the same layer as the first connection electrode CM 1  (see  FIG.  4   ). 
     When the connection lines CLe are arranged separately on three different layers from each other as in the embodiment, the number of the connection lines CLe arranged on each layer may be reduced. As the number of connection lines CLe arranged on each layer is reduced, a width of each of the connection lines CLe may be increased. According to the increase in the width of each connection line CLe, the resistance of each connection line CLe may be reduced. 
     While the description above has focused on a display apparatus, the present disclosure is not necessarily limited thereto. For example, a method of manufacturing the display apparatus as described above is also included in the scope of the present disclosure. 
     According to various embodiments of the present disclosure, the resistance of connection lines for connecting a data line to a pad portion may be reduced. However, the scope of the present disclosure is not necessarily limited by the above-described effects. 
     It should be understood that embodiments described herein should be considered in a descriptive sense. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.