Patent Publication Number: US-2003222672-A1

Title: Testing optical displays

Description:
BACKGROUND  
       [0001] This invention relates generally to optical displays and to techniques for testing optical displays.  
       [0002] A variety of optical displays exist for displaying information in association with processor-based systems. For example, liquid crystal on silicon (LCOS) or micromirror-based displays may be utilized to display information generated by processor-based or other systems.  
       [0003] Optical displays may exhibit a variety of internal faults that can cause high quiescent current states. Examples of such internal faults include bridging and stuck at faults, often the result of an electrical defect that creates an unwanted conducting path or short. In other words, the optical displays may exhibit high quiescent currents at times when low quiescent currents would be expected.  
       [0004] As a result of these high quiescent currents, the characteristics of the display may be degraded. Thus, it would be desirable to locate these faults in a cost effective fashion.  
       [0005] Especially in large optical displays, including those that have on the order of over a million individual optical modules or pixels, even a few faults may affect the overall quality of the display. Typically, these faults are verified by human visual inspection. Thus, these techniques may be slow and costly. Machine vision techniques may be applied on fully assembled devices when either pixel defects cannot be tolerated or when displays are of lower pixel counts. Often pixels have a response time of greater than 10 milliseconds. Thus, machine vision techniques may be time consuming and relatively expensive.  
       [0006] Thus, there is a need for better ways to test optical displays. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0007]FIG. 1 is a schematic depiction of one embodiment of the present invention;  
     [0008]FIG. 2 is a hypothetical graph of current versus time for an optical display that passes a test in accordance with one embodiment of the present invention;  
     [0009]FIG. 3 is a hypothetical graph of current versus time for a device that fails a test in accordance with one embodiment of the present invention; and  
     [0010]FIG. 4 is a block depiction of a portion of a display that has failed a test in accordance with one embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION  
     [0011] Referring to FIG. 1, in accordance with one embodiment of the present invention an optical display  10  may be in the form of a liquid crystal on silicon (LCOS) optical modulator. However, embodiments of the present invention may be applicable to a wide variety of other optical displays including silicon micromirror displays. The display  10  may have a closely coupled integrated circuit and optical modulator whose properties may include the ability to function in a static manner, requiring relatively small operating currents when compared to currents induced when abnormal shorting of the modulators occurs.  
     [0012] Referring again to FIG. 1, the display  10  may include a transparent electrode  20 , which may be formed on a glass substrate, that is typically grounded, in close proximity to a reflective electrode array  18  on the metal stack of an integrated circuit coupled to drive electronics. Between the electrode  20  and the integrated circuit represented by the electrodes  18 , is a layer of liquid crystal which is a dielectric. The optical modulator, therefore, presents itself as a capacitive load to the drive electronics.  
     [0013] Under normal conditions, once a driver  16  has charged or discharged the effective capacitance, the driver  16  draws no additional current. If the circuitry on the integrated circuit were fully static, there would be no current flow except for transistor leakage currents when the display  10  is no longer clocked and its inputs remain fixed. If, however, the driven electrode  18  were shorted to a node of opposite polarity, such as an adjacent pixel, the driver  16  may continue to sink or source current. This is detectable at the device power supply as increased quiescent current.  
     [0014] Thus, a tester  22  may include current measuring circuits and may also control or drive the decoders and/or access circuitry  12  of the optical display  10 . The decoders/access circuitry  12  may drive a plurality of memory elements  14   a  through  14   n . Each memory element  14 , in turn, drives a driver  16   a  through  16   n . Each driver  16  is coupled to a reflective electrode  18   a  through  18   n  in one embodiment. A pixel is defined between each electrode  18  and the transparent electrode  20 .  
     [0015] The tester  22  operates the display  10  in a manner to potentially activate a short condition between pixels at each electrode  18 . In two dimensional displays  10 , a checkerboard pattern and its inverse may be sufficient to locate most shorts. Additional patterns may be used to further isolate faulty pixels to faulty rows, columns, quadrants, or individual pixels. Special patterns specific to unique topographies or routings may require additional patterns to activate potential shorts.  
     [0016] The tester  22  may be an external tester in one embodiment or the tester  22  may be an internal or built-in self-test (BIST) circuit in another embodiment.  
     [0017] The tester  22  measures the power supply current after sufficient time has elapsed and the display  10  supply current has reached a steady state. The measured current is statistically compared to measured currents in known good displays to determine if the current measured in the device under test was excessive. Excessive currents are indicative of a detected fault.  
     [0018] The current draw of the display  10  may also be measured indirectly by a voltage droop in some embodiments. With this approach, after the display  10  has reached the steady state, the power supply may be disconnected. The internal capacitance of the display  10  discharges at a characteristic rate depending on whether the display  10  is faulty. This discharge may be measured as a voltage at the power supply input to the display  10 .  
     [0019] Referring to FIG. 2, in accordance with one embodiment of the present invention, the tester  22  may automatically drive each electrode  18  through a set-up period and then into a test period. In the test period, the display electrode passes if low quiescent current is detected. However, as shown in FIG. 3, if higher quiescent current is detected during the test period, the display  10  may be considered to have a fault or defect, as indicated in FIG. 3.  
     [0020] Thus, as shown in FIG. 4, a value one, of the checkerboard pattern of alternating one and zero values, may be driven on one electrode  18   b  and a value zero may be driven on an adjacent electrode  18   a . If there is a short, as indicated at D, excessive quiescent current may be detected.  
     [0021] Thus, in accordance with some embodiments of the present invention, an electrical test may be implemented in an automated fashion. No human or machine vision testing may be required in some cases. As a result of its automated nature, the test may be run rapidly and is limited only by the settling time of the display electronics, not the response time of the optical modulator. A simple test pattern, such as the checkerboard and its inverse, may be utilized. The test pattern may check all the pixels for shorts. In some embodiments the test may not require full assembly of the display  10 . The test may be accomplished at wafer sort, as one example. The test may also be done after the display  10  is fully assembled. In addition, in some embodiments, the techniques described herein may increase overall test coverage. Additionally, the quiescent test vectors may be implemented to find display electronics failures unrelated to the optical modulator in some cases.  
     [0022] While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.