Patent Publication Number: US-11038355-B2

Title: Power transmission system preventing power transmission efficiency from degrading due to delay, and capable of reducing effects of high frequency noise

Description:
CROSS-REFERENCE OF RELATED APPLICATIONS 
     This application is the U.S. National Phase under 35 U.S.C. § 371 of International Patent Application No. PCT/JP2018/007007, filed on Feb. 26, 2018, which in turn claims the benefit of Japanese Application No. 2017-040797, filed on Mar. 3, 2017, the entire disclosures of which Applications are incorporated by reference herein. 
     TECHNICAL FIELD 
     The present disclosure relates to a power transmitter apparatus which transmits power (electric power) via a transmission path, a power receiver apparatus which receives power via a transmission path, and a power transmission system including the power transmitter apparatus and the power receiver apparatus. 
     BACKGROUND ART 
     In recent years, power supplies of renewable energy, typically photovoltaic power generation, wind power generation, and biofuel power generation, are increasingly used, as well as conventional power supplies provided by power companies, such as thermal power generation, hydropower generation, and nuclear power generation. In addition, apart from large-scale commercial power networks currently provided, local and small-scale power networks capable of achieving local production and local consumption of power have been being spread worldwide in order to reduce losses of long-distance power transmission. 
     In a small-scale power network, power can be supplied self-sufficiently by using a natural energy power generator, and electric load equipment capable of efficient power regeneration. This type of power network is highly promising as a power transmission system for supplying electricity to non-electrified areas, such as desert oasis and remote islands. 
     For example, each of Patent Documents 1 to 3 discloses a power transmission system which transmits power from a power supply to a load via a power line. 
     CITATION LIST 
     Patent Documents 
     PATENT DOCUMENT 1: Japanese Patent Publication No. JP 5612718 B 
     PATENT DOCUMENT 2: Japanese Patent Publication No. JP 5612920 B 
     PATENT DOCUMENT 3: Japanese Patent laid-open Publication No. JP 2011-091954 A 
     SUMMARY OF INVENTION 
     Technical Problem 
     In order to transmit power from a power supply to a load via a power line, a power transmission system includes: a power transmitter apparatus which transmits power supplied from the power supply via a transmission path; and a power receiver apparatus which receives the power via the transmission path and supplies the power to the load. When transmitting power from the power transmitter apparatus to the power receiver apparatus in the power transmission system thus configured, it may be required to surely synchronize between the power transmitter apparatus and the power receiver apparatus with each other. If a delay occurs between the power transmitter apparatus and the power receiver apparatus for some reason, then power transmission efficiency may degrade. 
     An object of the present disclosure is to solve the aforementioned problems, and to provide a power transmitter apparatus capable of preventing power transmission efficiency from degrading due to a delay between the power transmitter apparatus and a power receiver apparatus. 
     Solution to Problem 
     According an aspect of the present disclosure, a power transmitter apparatus transmits power to at least one power receiver apparatus via a transmission path. The power transmitter apparatus is provided with: a code modulation circuit connected to a power supply via a first reactor and supplied with source power from the power supply, the code modulation circuit modulating the source power to generate a code-modulated wave by code modulation using a modulation code based on a code sequence, and transmitting the code-modulated wave to the power receiver apparatus via the transmission path; and a control circuit that controls the code modulation circuit. The code modulation circuit is provided with: first and second ports connected to the power supply via the first reactor, third and fourth ports connected to the transmission path, a first switch circuit connected between the first and third ports, a second switch circuit connected between the second and third ports, a third switch circuit connected between the first and fourth ports, and a fourth switch circuit connected between the second and fourth ports, The control circuit sets a first state to the code modulation circuit, the first state defined in which the first and fourth switch circuits are turned on, and the second and third switch circuits are turned off. The control circuit sets a second state to the code modulation circuit, the second state defined in which the first and fourth switch circuits are turned off, and the second and third switch circuits are turned on. The control circuit sets a third state to the code modulation circuit during transition from the first state to the second state, and during transition from the second state to the first state, the third state defined in which all the first to fourth switch circuits are turned on. The power transmitter apparatus is further provided with at least one of: a first filter circuit connected between the first and second ports, a second filter circuit connected between the third and fourth ports, and a third filter circuit connected in parallel to each of the first to fourth switch circuits. 
     These generic and specific aspects may be implemented as a system, as a method, or as any combination of systems and methods. 
     Advantageous Effects of Invention 
     According to the power transmitter apparatus of one aspect of the present disclosure, it is possible to prevent power transmission efficiency from degrading due to a delay between the power transmitter apparatus and a power receiver apparatus. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a block diagram showing a configuration of a power transmission system according to a first embodiment. 
         FIG. 2  is a waveform in diagram showing an exemplary signal waveform of a modulated current I 2  of the power transmission system of  FIG. 1 . 
         FIG. 3  is a waveform diagram showing an exemplary signal waveform of a modulated current I 2  of a communication system according to a comparison example. 
         FIG. 4  is a waveform diagram showing exemplary signal waveforms in the power transmission system of  FIG. 1 , in which: (a) shows a signal waveform of a generated current I 1 ; (b) shows a signal waveform of a modulated current I 2 ; and (c) shows a signal waveform of a demodulated current I 3 . 
         FIG. 5  is a block diagram showing a configuration of a code modulator  2  of  FIG. 1 . 
         FIG. 6  is a block diagram showing a configuration of a code demodulator  4  of  FIG. 1 . 
         FIG. 7  is a block diagram showing configurations of a code modulation circuit  23  and a code demodulation circuit  33  of  FIG. 1 . 
         FIG. 8A  is a diagram showing an example of a modulation code of the code modulator  2  and a demodulation code of the code demodulator  4  in the power transmission system of  FIG. 1 , as a first implementation example in which direct-current power is transmitted and received. 
         FIG. 8B  is a diagram showing an example of a modulation code of the code modulator  2  and a demodulation code of the code demodulator  4  in the power transmission system of  FIG. 1 , as a second implementation example in which direct-current power is transmitted and received. 
         FIG. 9  is a waveform diagram showing exemplary signal waveforms in the power transmission system according to a second embodiment, in which: (a) shows a signal waveform of a generated current I 1 ; (b) shows a signal waveform of a modulated current I 2 ; and (c) shows a signal waveform of a demodulated current I 3 . 
         FIG. 10  is a block diagram showing a partial configuration of a code modulator  2 A of the power transmission system according to the second embodiment. 
         FIG. 11  is a block diagram showing a partial configuration of a code demodulator  4 A of the power transmission system according to the second embodiment. 
         FIG. 12A  is a diagram showing an example of a modulation code of the code modulator  2 A and a demodulation code of the code demodulator  4 A in the power transmission system according to the second embodiment, as a third implementation example in which alternating-current power is transmitted and received. 
         FIG. 12B  is a diagram showing an example of a modulation code of the code modulator  2 A and a demodulation code of the code demodulator  4 A in the power transmission system according to the second embodiment, as a fourth implementation example in which direct-current power is transmitted and received. 
         FIG. 13A  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 21 A for a code modulation circuit  23 A used in a power transmission system according to a modified embodiment of the second embodiment. 
         FIG. 13B  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 22 A for the code modulation circuit  23 A used in the power transmission system according to the modified embodiment of the second embodiment. 
         FIG. 13C  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 23 A for the code modulation circuit  23 A used in the power transmission system according to the modified embodiment of the second embodiment. 
         FIG. 13D  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 24 A for the code modulation circuit  23 A used in the power transmission system according to the modified embodiment of the second embodiment. 
         FIG. 14A  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 31 A for a code demodulation circuit  33 A used in the power transmission system according to the modified embodiment of the second embodiment. 
         FIG. 14B  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 32 A for the code demodulation circuit  33 A used in the power transmission system according to the modified embodiment of the second embodiment. 
         FIG. 14C  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 33 A for the code demodulation circuit  33 A used in the power transmission system according to the modified embodiment of the second embodiment. 
         FIG. 14D  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 34 A for the code demodulation circuit  33 A used in the power transmission system according to the modified embodiment of the second embodiment. 
         FIG. 15  is a block diagram showing a configuration of a power transmission system according to a third embodiment. 
         FIG. 16A  is a diagram showing an example of a modulation code of a code modulator  2 A- 1  and a demodulation code of a code demodulator  4 A- 1  in the power transmission system of  FIG. 15 , as a fifth implementation example in which direct-current power is transmitted and received. 
         FIG. 16B  is a diagram showing an example of a modulation code of the code modulator  2 A- 2  and a demodulation code of the code demodulator  4 A- 2  in the power transmission system of  FIG. 15 , as a sixth implementation example in which direct-current power is transmitted and alternating-current power is received. 
         FIG. 17  is a waveform diagram showing exemplary signal waveforms in the power transmission system according to the third embodiment, in which: (a) shows a signal waveform of a generated current I 11 ; (b) shows a signal waveform of a generated current I 12 ; (c) shows a signal waveform of a modulated current I 2 ; (d) shows a signal waveform of a demodulated current I 31 ; and (e) shows a signal waveform of a demodulated current I 32 . 
         FIG. 18  is a circuit diagram showing a configuration of a power transmission system according to a fourth embodiment. 
         FIG. 19  is a timing chart showing modulation codes m 1  and m 2  and demodulation codes d 1  and d 2  used in a power transmission system according to a comparison example of the fourth embodiment, in which: (a) shows a case without delay; and (b) shows a case with delay. 
         FIG. 20  is a diagram showing current flow with a delay in the power transmission system according to the comparison example of the fourth embodiment. 
         FIG. 21  is a block diagram showing a configuration of a power transmission system according to an implementation example and a comparison example of the fourth embodiment. 
         FIG. 22  is a graph showing variations of load voltages Vout 1  and Vout 2  when power is transmitted without delay in the power transmission system according to the comparison example of the fourth embodiment. 
         FIG. 23  is a graph showing variations of the load voltages Vout 1  and Vout 2  when a delay occurs in the power transmission system according to the comparison example of the fourth embodiment. 
         FIG. 24  is a timing chart showing modulation codes m 1  and m 2  and demodulation codes d 1  and d 2  used in the power transmission system according to the fourth embodiment. 
         FIG. 25  is a diagram showing current flow in a time period P 1  of  FIG. 24 . 
         FIG. 26  is a diagram showing current flow in each of time periods P 2  and P 4  in  FIG. 24 . 
         FIG. 27  is a diagram showing current flow in a time period P 3  of  FIG. 24 . 
         FIG. 28  is a timing chart showing the modulation codes m 1  and m 2  and the demodulation codes d 1  and d 2  when a delay shorter than a simultaneous ON time occurs in the power transmission system according to the fourth embodiment. 
         FIG. 29  is a diagram showing current flow in a time period P 2   a  of  FIG. 28 . 
         FIG. 30  is a graph showing variations of load voltages Vout 1  and Vout 2  when power is transmitted without delay in the power transmission system according to the implementation example of the fourth embodiment. 
         FIG. 31  is a graph showing variations of the load voltages Vout 1  and Vout 2  when a delay occurs in the power transmission system according to the implementation example of the fourth embodiment. 
         FIG. 32  is an equivalent circuit diagram when the power transmission system according to the fourth embodiment is in a state as shown in  FIG. 25  or  FIG. 27 . 
         FIG. 33  is an equivalent circuit diagram when the power transmission system according to the fourth embodiment is in a state as shown in  FIG. 26 . 
         FIG. 34  is a schematic diagram showing variations of output voltage when time periods of  FIGS. 32 and 33  are alternated. 
         FIG. 35  is a timing chart showing the modulation codes m 1  and m 2  and the demodulation codes d 1  and d 2  when a delay longer than the simultaneous ON time occurs in the power transmission system according to the fourth embodiment. 
         FIG. 36  is a timing chart showing modulation codes m 1  and m 2  and demodulation codes d 1  and d 2  used in a power transmission system according to a fifth embodiment, in which: (a) shows a case where a delay equal to or shorter than an allowable delay time occurs; and (b) shows a case where a delay longer than the allowable delay time occurs. 
         FIG. 37  is a graph showing variations of load voltages Vout 1  and Vout 2  when a delay longer than the allowable delay time does not occur in a power transmission system according to an implementation example of the fifth embodiment. 
         FIG. 38  is a graph showing variations of the load voltages Vout 1  and Vout 2  when a delay longer than the allowable delay time does not occur in the power transmission system according to the implementation example of the fifth embodiment. 
         FIG. 39  is a graph showing variations of the load voltages Vout 1  and Vout 2  when a delay longer than the allowable delay time occurs in the power transmission system according to the implementation example of the fifth embodiment. 
         FIG. 40  is a graph showing variations of the load voltages Vout 1  and Vout 2  when a delay longer than the allowable delay time occurs in the power transmission system according to the implementation example of the fifth embodiment. 
         FIG. 41  is a timing chart showing modulation codes m 1  and m 2  and demodulation codes d 1  and d 2  used in a power transmission system according to a comparison example of the fifth embodiment. 
         FIG. 42  is a timing chart showing modulation codes m 1  and m 2  and demodulation codes d 1  and d 2  used in a power transmission system according to a sixth embodiment, in which: (a) shows a case where a delay equal to an allowable delay time occurs; and (b) shows a case where a delay shorter than the allowable delay time occurs. 
         FIG. 43  is a graph showing variations of load voltages Vout 1  and Vout 2  when a delay longer than the allowable delay time does not occur in a power transmission system according to an implementation example of the sixth embodiment. 
         FIG. 44  is a sequence diagram showing a process of synchronizing a controller  10 , a code modulator  2 , and a code demodulator  4  in the power transmission system according to each of the fourth to sixth embodiments. 
         FIG. 45  is a circuit diagram showing a configuration of a power transmission system according to a seventh embodiment. 
         FIG. 46  is a circuit diagram showing filter circuits  45   a  and  45   b  used in the power transmission system of  FIG. 45 . 
         FIG. 47  is a circuit diagram showing a filter circuit  45   c  used in the power transmission system of  FIG. 45 . 
         FIG. 48  is a circuit diagram showing a filter circuit  45   d  used in the power transmission system of  FIG. 45 . 
         FIG. 49  is a circuit diagram showing the filter circuit  45   d  used in the power transmission system of  FIG. 45 . 
         FIG. 50  is a circuit diagram showing a first example of the filter circuits  41  to  45   d  of  FIGS. 45 to 49 . 
         FIG. 51  is a circuit diagram showing a second example of the filter circuits  41  to  45   d  of  FIGS. 45 to 49 . 
         FIG. 52  is a circuit diagram showing a third example of the filter circuits  41  to  45   d  of  FIGS. 45 to 49 . 
         FIG. 53  is a circuit diagram showing a fourth example of the filter circuits  41  to  45   d  of  FIGS. 45 to 49 . 
         FIG. 54  is a circuit diagram showing a fifth example of the filter circuits  41  to  45   d  of  FIGS. 45 to 49 . 
         FIG. 55  is a circuit diagram showing a sixth example of the filter circuits  41  to  45   d  of  FIGS. 45 to 49 . 
         FIG. 56  is a circuit diagram showing a seventh example of the filter circuits  41  to  45   d  of  FIGS. 45 to 49 . 
         FIG. 57  is a circuit diagram showing a configuration of a power transmission system including filter circuits according to an eighth example of the seventh embodiment. 
         FIG. 58  is a block diagram showing a configuration of a power transmission system including filter circuits according to a ninth example of the seventh embodiment. 
         FIG. 59  is a circuit diagram showing the configuration of the power transmission system including the filter circuits according to the ninth example of the seventh embodiment. 
         FIG. 60  is a graph showing a relationship between a modulation code and a resonance waveform of a filter circuit in a power transmission system according to an eighth embodiment. 
         FIG. 61  is a diagram illustrating resonance of the filter circuit in the power transmission system according to the eighth embodiment. 
         FIG. 62  is a diagram showing a relationship between output voltage of the code modulator  2  and input voltage of the code demodulator  4  when a resonance frequency of the filter circuit in the power transmission system according to the eighth embodiment is identical to a modulation clock frequency. 
         FIG. 63  shows a simulation result of a power transmission system according to a comparison example of the seventh embodiment, in which: (a) is a graph showing gate voltage of switch elements S 1  and S 4 ; (b) is a graph showing current flowing in the switch elements S 1  and S 4 ; and (c) is a graph showing voltage across both ends of the switch elements S 1  and S 4 . 
         FIG. 64  shows a simulation result of a power transmission system according to a first implementation example of the seventh embodiment, in which: (a) is a graph showing gate voltage of switch elements S 1  and S 4 ; (b) is a graph showing current flowing in the switch elements S 1  and S 4 ; and (c) is a graph showing voltage across both ends of the switch elements S 1  and S 4 . 
         FIG. 65  is a diagram showing how to measure current and voltage of  FIGS. 63 and 64 . 
         FIG. 66  is a graph showing a simulation result of the power transmission system according to the comparison example of the seventh embodiment, showing voltage applied to both ends of a diode D 101  of a switch circuit. 
         FIG. 67  is a graph showing an enlarged diagram of a part of  FIG. 66 . 
         FIG. 68  is a graph showing a simulation result of the power transmission system according to the comparison example of the seventh embodiment, showing voltage applied to both ends of a switch element S 101  of the switch circuit. 
         FIG. 69  is a graph showing an enlarged diagram of a part of  FIG. 68 . 
         FIG. 70  shows a simulation result of a power transmission system according to a second implementation example of the seventh embodiment, in which: (a) is a graph showing voltage applied to both ends of the diode D 101  of the switch circuit; and (b) is a graph showing voltage applied to both ends of the switch element S 101  of the switch circuit. 
         FIG. 71  is a diagram showing how to measure voltages shown in  FIGS. 66 to 70 . 
         FIG. 72  shows a simulation result of a power transmission system according to a third implementation example of the seventh embodiment, in which: (a) is a graph showing voltage across both ends of the switch elements S 1  and S 4 ; (b) is a graph showing gate voltage of the switch elements S 1  and S 4 ; and (c) is a graph showing current flowing in the switch elements S 1  and S 4 . 
         FIG. 73  is a graph showing an enlarged diagram of a part of  FIG. 72 . 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Findings Underlying Present Disclosure 
     Patent Document 1 discloses an interconnection apparatus for power transmitter apparatuses, the interconnection apparatus being capable of transmitting and receiving power among a plurality of power systems. According to Patent Document 1, the interconnection apparatus is provided with a converter and an inverter. For power transmission, the converter converts transmitting power from alternating current to direct current, and the converted power is transmitted to the interconnection apparatus connected to a receiving power system. At the interconnection apparatus of the receiving power system, the inverter converts the power so as to have a desired frequency, thus providing power having an optimum frequency for the power system to which the interconnection apparatus is connected. Moreover, Patent Document 2 discloses a configuration further provided with a power storage apparatus, in addition to the components of Patent Document 1. 
     On the other hand, Patent Document 3 discloses a method of transmitting power from a plurality of power transmitter apparatuses to a plurality of power receiver apparatuses. According to Patent Document 3, power is transmitted from the plurality of power transmitter apparatuses to the plurality of power receiver apparatuses in a time division manner. According to Patent Document 3, control signals are wirelessly transmitted among the power transmitter apparatuses and the power receiver apparatuses in order to transmit and receive power. 
     However, according to Patent Documents 1 and 2, the interconnection apparatus is provided with the inverter and converter, and basically, individual power transmission cables are required for all combinations of the power systems transmitting and receiving power. According to Patent Documents 1 and 2, the interconnection apparatus may be configured so as to reduce the number of power transmission cables, however, in any case, a large number of power transmission cables are required. Thus, installation costs and the cables&#39; material costs increase. In addition, the interconnection apparatus should be provided with the same number of pairs of the inverter and the converter as the number of the power systems to be connected. Accordingly, the cables&#39; costs may increase, and costs may further increase due to the increased size of the interconnection apparatus. 
     In addition, according to Patent Document 3, it is possible to transmit and receive power among the plurality of power transmitter apparatuses and the plurality of power receiver apparatuses in a time division manner, and advantageously, it is possible to reduce the number of power transmission cables. However, in case of time-division power transmission, it is not possible to transmit and receive power among the plurality of power systems, simultaneously. In other words, it may not be possible to immediately handle a power demand from a load connected to a power receiver. Furthermore, when transmitting and receiving power among a large number of pairs of the power transmitter apparatuses and the power receiver apparatuses, only a short time is allocated for one pair of the power transmitter apparatus and the power receiver apparatus to transmit and receive power, and therefore, large pulse power is transmitted via the power transmission cable. Accordingly, the transmission cable with a high power durability is required, and thus, it may increase costs. In addition, since time intervals in which power can not be received occur, it may be required to provide the power receiver apparatuses with a buffer for large power. Furthermore, in order to transmit and receive power in a time division manner, time-synchronization is required among the plurality of power transmitter apparatuses and the plurality of power receiver apparatuses. In order to achieve such synchronization, very accurate controls among the apparatuses are required, and thus, it may increase the entire system costs. 
     As described above, according to both Patent Documents 1 and 2, a large number of power transmission cables are used, and therefore, it is not possible to reduce the power transmission cables by multiplexed power transmission. Further, the interconnection apparatus requires a pair of inverter and converter for each of the power transmission cables, and therefore, it is not possible to reduce the size of the interconnection apparatus. Accordingly, it is difficult to transmit and receive power among a large number of power systems. On the other hand, according to Patent Document 3, power is transmitted and received among the plurality of power transmitter apparatuses and the plurality of power receiver apparatuses via the power transmission cables in a time division manner, thus reducing the number of the power transmission cables. However, it is not possible to provide a transmission system capable of transmitting and receiving power among the plurality of power systems, simultaneously. Accordingly, there is a demand for a power transmission system with a reduced number of power transmission cables, and capable of transmitting and receiving power from a plurality of power transmitter apparatuses to a plurality of power receiver apparatuses, simultaneously, and more reliably, while reducing sizes and thicknesses of the power transmitter apparatuses and the power receiver apparatuses. 
     Further, as described above, when transmitting power from a power transmitter apparatus to a power receiver apparatus in a power transmission system, it may be required to surely synchronize the power transmitter apparatus and the power receiver apparatus. If a delay occurs between the power transmitter apparatus and the power receiver apparatus for some reason, then power transmission efficiency may degrade. 
     Based on the above consideration, the inventors provide the following aspects of the invention. 
     Hereinafter, embodiments according to the present disclosure will be described with reference to the drawings. In the following embodiments, similar constituent elements are denoted by identical reference numerals. 
     An object of the present disclosure is to provide a power transmitter apparatus, a power receiver apparatus, and a power transmission system capable of preventing power transmission efficiency from degrading due to a delay between the power transmitter apparatus and the power receiver apparatus. In first to third embodiments, we describe preparatory overviews of power transmission systems. Thereafter, in fourth to eighth embodiments, we describe power transmission systems which solves the problems. 
     First Embodiment 
       FIG. 1  is a block diagram showing a configuration of a power transmission system according to the first embodiment. Referring to  FIG. 1 , the power transmission system according to the first embodiment is provide with a power generator  1 , a code modulator  2 , a transmission path  3 , a code demodulator  4 , a load  5 , and a controller  10 . The transmission path  3  is, for example, a wired transmission path including two power lines, or a wireless transmission path. 
     The controller  10  is provided with a control circuit  11  and a communication circuit  12 . The control circuit  11  communicates with the code modulator  2  and the code demodulator  4  via the communication circuit  12 , and controls operations of the code modulator  2  and the code demodulator  4 . 
     In the power transmission system of  FIG. 1 , the code modulator  2  operates as a power transmitter apparatus, and the code demodulator  4  operates as a power receiver apparatus. The code modulator  2  modulates first power to generate a code-modulated wave by code modulation using a modulation code based on a code sequence, and transmits the code-modulated wave to the code demodulator  4  via the transmission path  3 . The code demodulator  4  receives the code-modulated wave from the code modulator  2  via the transmission path  3 , and demodulates the received code-modulated wave to generate second power by code demodulation using a demodulation code based on a code sequence identical to the code sequence of the modulation code used for the code modulation. The first power is, for example, direct-current power generated by the power generator  1 , and is shown as a generated current I 1  in  FIG. 1 . The code-modulated wave is alternating-current power modulated by code modulation, and is shown as a modulated current I 2  in  FIG. 1 . The second power is, for example, direct-current power to be supplied to the load  5 , and is shown as a demodulated current I 3  in  FIG. 1 . 
     The power transmission system of  FIG. 1  is further provided with power meters  1   m  and  5   m . The power meter  1   m  is first power measuring means which measures an amount of the first power. More specifically, the power meter  1   m  measures an amount of direct-current power generated by the power generator  1  and transmitted from the power generator  1  to the code modulator  2 . The power meter  1   m  may be provided to the power generator  1 , or disposed between the power generator  1  and the code modulator  2 . The power meter  5   m  is second power measuring means for measuring an amount of the second power. More specifically, the power meter  5   m  measures an amount of direct-current power transmitted from the code demodulator  4  to the load  5 , and used by the load  5 . The power meter  5   m  may be provided to the load  5 , or may be disposed between the code demodulator  4  and the load  5 . The amounts of powers measured by the power meters  1   m  and  5   m  are transmitted to the controller  10 . 
     The controller  10  controls operations of the code modulator  2  and the code demodulator  4  based on the amounts of powers received from the power meters  1   m  and  5   m . For example, the controller  10  transmits control signals to the code modulator  2  and the code demodulator  4 , the control signals including synchronization signals for synchronizing the code modulator  2  and the code demodulator  4  to each other, thus achieving code modulation and code demodulation of power in an accurately synchronized manner. 
     The controller  10  sets a modulation code to the code modulator  2 , and a demodulation code to the code demodulator  4 , based on one code sequence. The code sequence of the modulation code used for modulation by the code modulator  2 , and the code sequence of the demodulation code used for demodulation by the code demodulator  4  may be set in advance to the code modulator  2  and the code demodulator  4 . In addition, for example, the controller  10  may transmit, as the control signals, the code sequence of the modulation code used for modulation by the code modulator  2 , and the code sequence of the demodulation code used for demodulation by the code demodulator  4 . Further, the controller  10  may transmit, as the control signals, only information specifying the code sequences, without transmitting the code sequences themselves, so that the code modulator  2  and the code demodulator  4  to generates the code sequences, respectively. In this case, it is possible to achieve code modulation and code demodulation between the code modulator  2  and the code demodulator  4  corresponding to each other in an accurately synchronized manner. 
       FIG. 2  is a waveform diagram showing an exemplary signal waveform of the modulated current I 2  of the power transmission system of  FIG. 1 . In addition,  FIG. 3  is a waveform diagram showing an exemplary signal waveform of a modulated current I 2  of a communication system according to a comparison example. 
     The code modulator  2  of  FIG. 1  modulates a current of power, which is generated by the power generator  1 , by code modulation using a modulation code based on a predetermined code sequence. In this case, the code modulator  2  generates an alternating-current code-modulated wave made of currents flowing in directions corresponding to code values of “1” and “−1.”, respectively, as shown in  FIG. 2 . This code-modulated wave can transmit power in both periods of positive current flows, and periods of negative current flows (e.g., period T 01  of  FIG. 2 ). While the first embodiment indicates an example in which direct-current power is modulated by code modulation, alternating-current power may be modulated by code modulation as in a second embodiment described below. 
     In the data transmission system according to the comparison example, e.g., to be used for communication, code values of “1” and “0” are typically used for code modulation, as shown in  FIG. 3 . However, according to the code-modulated wave as shown in  FIG. 3 , when the code value of the modulation code is “0” (e.g., period T 02  of  FIG. 3 ), a modulated current or voltage becomes zero, that is, a period of no power transmission occurs. Such periods of no power transmission may reduce overall power transmission efficiency. More specifically, for the case of communication, since information such as data should be transmitted in an accurately synchronized manner, it is only required that the code demodulator accurately distinguish between “0” and “1”. On the other hand, for the case of power transmission, a power loss due to the period of no power transmission is not permissible from a viewpoint of efficiency in use of energy. Accordingly, by using an alternating-current code-modulated wave flowing in directions corresponding to the code values of “1” and “−1”, respectively, as shown in  FIG. 2 , it is possible to transmit power with higher transmission efficiency than that of the comparison example. 
       FIG. 4  is a waveform diagram, where (a) to (c) show exemplary signal waveforms in the power transmission system of  FIG. 1 . In  FIG. 4 , (a) shows a signal waveform of the generated current I 1 , (b) shows a signal waveform of the modulated current I 2 , and (c) shows a signal waveform of the demodulated current I 3 . The power generator  1  generates the direct-current generated current I 1 . The code modulator  2  multiplies the generated current I 1  by a modulation code m 0  to generate the alternating-current modulated current I 2 . The code demodulator  4  multiplies the modulated current I 2  by a demodulation code d 0  identical to the modulation code m 0  to reproduce the direct-current power generated by the power generator  1 , and supply the reproduced direct-current power to the load  5 . 
     Referring to  FIG. 4 , T 10  indicates a period of one cycle of the modulation code m 0  and the demodulation code d 0 . The same also applies to subsequent drawings. 
     According to the exemplary signal waveform of  FIG. 4 , the direct-current generated current I 1  ( FIG. 4( a ) ) is multiplied by the modulation code m 0  having a frequency of 35 kHz, to generate the modulated current I 2  ( FIG. 4( b ) ) of the code-modulated wave. In this case, the duration of each bit of the modulation code m 0  is 1/(35 kHz)/2=14.2 microseconds. 
     Each bit of the modulation code m 0  and the demodulation code d 0  has a code value “1” or “−1”. The code value “1” of the modulation code m 0  indicates that the code modulator  2  outputs a current in the same direction as the direction of an inputted current, and the code value “−1” of the modulation code m 0  indicates that the code modulator  2  outputs a current in the direction opposite to the direction of the inputted current. Similarly, the code value “1” of the demodulation code d 0  indicates that the code demodulator  4  outputs a current in the same direction as the direction of an inputted current, and the code value “−1” of the demodulation code d 0  indicates that the code demodulator  4  outputs a current in the direction opposite to the direction of the inputted current. 
     For example, the modulation code m 0  and the demodulation code d 0  are given as follows.
 
 m 0=[1 −1 1 1 1 −1 −1 −1 1 −1 −1 −1 1 1]  (1)
 
 d 0= m 0=[1 −1 1 1 1 −1 −1 −1 1 −1 −1 −1 1 1]  (2)
 
     Subsequently, the modulated current I 2  of the code-modulated wave generated by the modulation code m 0  is multiplied by the demodulation code d 0 . This multiplication is denoted as follows.
 
 m 0× d 0=[1 1 1 1 1 1 1 1 1 1 1 1 1 1]  (3)
 
     As apparent from Mathematical Expression (3), the demodulated current I 3  ( FIG. 4( c ) ) is obtained, which is direct current similarly to the original generated current I 1 . 
     As described above, it is possible to achieve direct-current power transmission in an accurately synchronized manner, without power loss, by using the code modulator  2  and the code demodulator  4  according to the present embodiment. In addition, it is possible to achieve efficient power transmission for a longer period, for example, by repeatedly using the modulation code m 0  and demodulation code d 0  as described above. 
     Further, the modulation code m 0  can be divided into its first half code portion m 0   a , and its second half code portion m 0   b , as follows.
 
 m 0 a =[1 −1 1 1 1 −1 −1]  (4)
 
 m 0 b =[−1 1 −1 −1 −1 1 1]  (5)
 
     In this case, the code portion m 0   b  is generated by inverting the sign of the code value of each bit of the code portion m 0   a . More specifically, when the code value of a certain bit of the code portion m 0   a  is “1”, the code value of a corresponding bit of the code portion m 0   b  is “−1”. Similarly, when the code value of a certain bit of the code portion m 0   a  is “−1.”, the code value of a corresponding bit of the code portion m 0   b  is “1”. 
       FIG. 5  is a block diagram showing a configuration of the code modulator  2  of  FIG. 1 . Referring to  FIG. 5 , the code modulator  2  is provided with a control circuit  20 , a communication circuit  21 , a code generation circuit  22 , and a code modulation circuit  23 . The communication circuit  21  receives a synchronization signal and a control signal from the controller  10 , the control signal including a code sequence itself or information specifying the code sequence, and outputs the received signals to the control circuit  20 . In this case, the synchronization signal may be, for example, trigger signals to start and end modulation, or time information indicating a start time and an end time of modulation. Based on the control signal, the control circuit  20  controls the code generation circuit  22  so as to generate a modulation code based on a code sequence and output the modulation code to the code modulation circuit  23 , and controls start and end of operation of the code modulation circuit  23 . The code modulation circuit  23  has input ports T 1  and T 2  (first and second ports) connected to the power generator  1 , and output ports T 3  and T 4  (third and fourth ports) connected to the transmission path  3 . 
       FIG. 6  is a block diagram showing a configuration of the code demodulator  4  of  FIG. 1 . Referring to  FIG. 6 , The code demodulator  4  is provided with a control circuit  30 , a communication circuit  31 , a code generation circuit  32 , and a code demodulation circuit  33 . The communication circuit  31  receives a synchronization signal and a control signal from the controller  10 , the control signal including a code sequence itself or information specifying the code sequence, and outputs the received signals to the control circuit  30 . In this case, the synchronization signal may be, for example, trigger signals to start and end demodulation, or time information indicating a start time and an end time of demodulation. Based on the control signal, the control circuit  30  controls the code generation circuit  32  so as to generate a demodulation code based on a code sequence and output the demodulation code to the code demodulation circuit  33 , and controls start and end of operation of the code demodulation circuit  33 . The code demodulation circuit  33  has input ports T 11  and T 12  (fifth and sixth ports) connected to the transmission path  3 , and output ports T 13  and T 14  (seventh and eighth ports) connected to the load  5 . 
     Note that in the power transmission system of  FIG. 1 , the control signals from the controller  10  to the code modulator  2  and the code demodulator  4  may be transmitted via control signal lines different from the transmission path  3 , or may be transmitted via the transmission path  3  in a manner multiplexed with the code-modulated wave using some multiplexing scheme. In the latter case, it is possible to omit cables provided for communication from the controller  10  to the code modulator  2  and the code demodulator  4 , and reduce cost. 
       FIG. 7  is a block diagram showing configurations of the code modulation circuit  23  and the code demodulation circuit  33  of  FIG. 1 . Referring to  FIG. 7 , the code modulation circuit  23  is provided with first to fourth switch circuits SS 1  to SS 4  connected in a bridge configuration. The switch circuits SS 1  to SS 4  include unidirectional switch elements S 1  to S 4 , respectively, each made of, for example, a metal-oxide-semiconductor (MOS) transistor. In addition, the code demodulation circuit  33  is provided with fifth to eighth switch circuits SS 11  to SS 14  connected in a bridge configuration. The switch circuits SS 11  to SS 14  include unidirectional switch elements S 11  to S 14 , respectively, each made of, for example, an MOS transistor. 
     The code generation circuit  22  generates and outputs the modulation codes m 1  and m 2  to the code modulation circuit  23  under control of the control circuit  20 , in order to operate the code modulator  2  according to the modulation code m 0  as described above. The switch elements S 1  and S 4  of the code modulation circuit  23  are controlled according to the modulation code m 1 , and the switch elements S 2  and S 3  of the code modulation circuit  23  are controlled according to the modulation code m 2 . Each of the modulation codes m 1  and m 2  has code values “1” and “0”. For example, when a signal of the code value “1” is inputted to each of the switch elements S 1  to S 4 , each of the switch elements S 1  to S 4  is turned on. When a signal of the code value “0” is inputted to each of the switch elements S 1  to S 4 , each of the switch elements S 1  to S 4  is turned off. Note that switch elements other than the switch elements S 1  to S 4  described in the present specification operate in a similar manner. In this case, the switch elements S 1  to S 4  have directionality as follows. When the switch element S 1  is turned on, the switch element S 1  outputs a generated current inputted from the port T 1 , to the port T 3 . When the switch element S 3  is turned on, the switch element S 3  outputs a generated current inputted from the port T 1 , to the port T 4 . When the switch element S 2  is turned on, the switch element S 2  outputs a modulated current inputted from the port T 3 , to the port T 2 . When the switch element S 4  is turned on, the switch element S 4  outputs a modulated current inputted from the port T 4 , to the port T 2 . 
     The code generation circuit  32  generates and outputs the demodulation codes d 1  and d 2  to the code demodulation circuit  33  under control of the control circuit  30 , in order to operate the code demodulator  4  according to the demodulation code d 0  as described above. The switch elements S 11  and S 14  of the code demodulation circuit  33  are controlled according to the demodulation code d 2 , and the switch elements S 12  and S 13  of the code demodulation circuit  33  are controlled according to the demodulation code d 1 . Each of the demodulation codes d 1  and d 2  has code values “1” and “0”. In this case, the switch elements S 11  to S 14  have directionality as described below. When the switch element S 11  is turned on, the switch element S 11  outputs a modulated current inputted from the port T 12 , to the port T 13 . When the switch element S 13  is turned on, the switch element S 13  outputs a modulated current inputted from the port T 11 , to the port T 13 . When the switch element S 12  is turned on, the switch element S 12  outputs a demodulated current inputted from the port T 14 , to the port T 12 . When the switch element S 14  is turned on, the switch element S 14  outputs a demodulated current inputted from the port T 14 , to the port T 11 . 
     In the notation of  FIG. 7 , directions of current flows in the switch elements S 11  to S 14  of the code demodulator  4  are opposite to directions of current flows in the switch elements S 1  to S 4  of the code modulator  2 . 
       FIG. 8A  is a diagram showing an example of a modulation code of the code modulator  2  and a demodulation code of the code demodulator  4  in the power transmission system of  FIG. 1 , as a first implementation example in which direct-current power is transmitted and received. More specifically,  FIG. 8A  shows an example of the modulation codes m 1  and m 2  inputted to the switch elements S 1  to S 4  of the code modulator  2 , and the demodulation codes d 1  and d 2  inputted to the switch elements S 11  to S 14  of the code demodulator  4 . 
     As shown in  FIG. 8A , the modulation code m 1  and the demodulation code d 1  are identical to each other, and each is made of a code sequence c 1   a . In addition, the modulation code m 2  and the demodulation code d 2  are identical to each other, and each is made of a code sequence c 1   b . In addition, the code sequences c 1   a  and c 1   b  are configured such that when the code value of a certain bit of the code sequence c 1   a  is “1”, the code value of a corresponding bit of the code sequence c 1   b  is “0”; and when the code value of a certain bit of the code sequence c 1   a  is “0”, the code value of a corresponding bit of the code sequence c 1   b  is “1”. 
     Accordingly, among the switch elements S 1  to S 4  and S 11  to S 14  of  FIG. 7 , when a switch element receiving the code value of a certain bit of the code sequence c 1   a  is turned on, the switch element receiving the code value of a corresponding bit of the code sequence c 1   b  is turned off. In addition, when the switch element receiving the code value of a certain bit of the code sequence c 1   a  is turned off, the switch element receiving the code value of a corresponding bit of the code sequence c 1   b  is turned on. 
     According to the code modulation circuit  23  of  FIG. 7 , when the switch elements S 1  and S 4  are turned on, the switch elements S 2  and S 3  are turned off; and when the switch elements S 1  and S 4  are turned off, the switch elements S 2  and S 3  are turned on. Thus, when the switch elements S 1  and S 4  are turned on, and the switch elements S 2  and S 3  are turned off, the modulated current I 2  flows in the transmission path  3  in a positive direction, i.e., in a direction of solid arrows. On the other hand, when the switch elements S 1  and S 4  are turned off, and the switch elements S 2  and S 3  are turned on, the modulated current I 2  flows in the transmission path  3  in a negative direction, i.e., in a direction of dotted arrows. Accordingly, as shown in  FIG. 4 , when the direct-current generated current I 1  is inputted to the code modulator  2 , the alternating-current modulated current I 2  can be transmitted to the transmission path  3 . 
     In the code demodulation circuit  33  of  FIG. 7 , the switch elements S 11  to S 14  are turned on or off in response to the demodulation codes d 1  and d 2  in synchronization with the code modulation circuit  23 . In this case, the switch elements S 12  and S 13  are turned on or off in accordance with the demodulation code d 1  identical to the modulation code m 1 , and the switch elements S 11  and S 14  are turned on or off in accordance with the demodulation code d 2  identical to the modulation code m 2 . Thus, when the code value of the modulation code m 1  is “1”, and the code value of the modulation code m 2  is “0”, i.e., when the modulated current I 2  flows in the transmission path  3  in the positive direction, the code value of the demodulation code d 1  is “1”, and the code value of the demodulation code d 2  is “0”. Accordingly, by turning on the switch elements S 13  and S 12  and turning off the switch elements S 11  and S 14 , the demodulated current I 3  flows at the output ports T 13  and T 14  of the code demodulation circuit  33  in the positive direction, i.e., in the direction of the solid arrows. On the other hand, when the code value of the modulation code m 1  is “0”, and the code value of the modulation code m 2  is “1”, i.e., when the modulated current I 2  flows in the transmission path  3  in the negative direction, the code value of the demodulation code d 1  is “0”, and the code value of the demodulation code d 2  is “1”. Accordingly, by turning on the switch elements S 11  and S 14  and turning off the switch elements S 12  and S 13 , the demodulated current I 3  again flows at the output ports T 13  and T 14  of the code demodulation circuit  33  in the positive direction, i.e., in the direction of the solid arrows. 
     As described above, when using the modulation codes m 1  and m 2  and the demodulation codes d 1  and d 2  of  FIG. 8A , equivalently, the code modulator  2  operates according to the modulation code m 0  of Mathematical Expression (1), and the code demodulator  4  operates according to the demodulation code d 0  of Mathematical Expression (2). 
     As described above, according to  FIGS. 7 and 8A , when the direct-current generated current I 1  is inputted to the code modulator  2 , it is possible to extract the demodulated current I 3  from the code demodulator  4 , the demodulated current I 3  being also a direct current similarly to the generated current I 1  inputted to the code modulator  2 . Therefore, according to the first embodiment, it is possible to modulate the direct-current generated current I 1  by code modulation into the alternating-current modulated current I 2 , and then, transmit the modulated current I 2  via the transmission path  3 , and then, demodulate the modulated current I 2  into the direct-current demodulated current I 3 . 
       FIG. 8B  is a diagram showing an example of a modulation code of the code modulator  2  and a demodulation code of the code demodulator  4  in the power transmission system of  FIG. 1 , as a second implementation example in which direct-current power is transmitted and received. When in each of the code sequences c 1   a  and c 1   b , the number of bits of the code value “1” is equal to the number of bits of the code value “0”, the modulated current I 2  being modulated by code modulation and flowing in the transmission path  3  includes, in average, no direct-current component, but includes only an alternating-current component. However, in some code sequence, the number of bits of the code value “1” is different from the number of bits of the code value “0”, and thus, a direct-current component occurs. When using such a code sequence, by concatenating the code sequence with a code sequence of bits having code values inverted from those of corresponding bits, respectively, it is possible to generate a modulation code and a demodulation code, in each of which the number of bits of the code value “1” is equal to the number of bits of the code value “0”. According to the example of  FIG. 8B , each of the modulation code m 1  and the demodulation code d 1  is a code sequence [c 1   a  c 1   b ] which is a concatenation of the code sequence c 1   a  and the code sequence c 1   b , and each of the modulation code m 2  and the demodulation code d 2  is a code sequence [c 1   b  c 1   a ] which is a concatenation of the code sequence c 1   b  and the code sequence c 1   a . As a result, the average value of the code-modulated current I 2  flowing in the transmission path  3  becomes zero, and the modulated current I 2  includes only an alternating-current component. 
     Note that the power generator  1  or the load  5  may be a power storage apparatus, such as a battery and a capacitor. When a power storage apparatus is incorporated in the power transmission system according to the present embodiment, it is possible to effectively utilize power generated during hours of low or no power consumption, and thus, improve overall power efficiency. 
     Second Embodiment 
     In the first embodiment, we have described the power transmission system which modulates and transmits a direct-current generated current by code modulation. Meanwhile, in a second embodiment, we describe a power transmission system which modulates and transmits an alternating-current generated current by code modulation. 
     The power transmission system according to the second embodiment includes a code modulator  2 A and a code demodulator  4 A, which will be described below with reference to  FIGS. 10 and 11 , in place of the code modulator  2  and the code demodulator  4  of  FIG. 1 . The other portions of the power transmission system according to the second embodiment are configured in a manner similar to that of the power transmission system according to the first embodiment. 
       FIG. 9  is a waveform diagram, where (a) to (c) show exemplary signal waveforms in the power transmission system according to the second embodiment. In  FIG. 9 , (a) shows a signal waveform of a generated current I 1 ; (b) shows a signal waveform of a modulated current I 2 ; and (c) shows a signal waveform of a demodulated current I 3 . More specifically,  FIG. 9  shows exemplary signal waveforms generated as follows: the code modulator  2 A modulates the (single-phase) alternating-current generated current I 1  by code modulation, and then, the modulated current I 2  is transmitted via a transmission path  3 , and then, the code demodulator  4 A demodulates the modulated current I 2  by code demodulation. 
     The power generator  1  generates the alternating-current generated current I 1 . For example, the alternating-current generated current I 1  has a rectangular waveform at a frequency of 5 kHz, which cyclically repeats positive and negative periods every 200 microseconds. Also in this case, the code modulator  2 A multiplies the generated current I 1  by a modulation code m 0  to generate the alternating modulated current I 2 , in a manner similar to the code modulation of the direct-current generated current I 1  as shown in  FIG. 4 . The code demodulator  4 A multiplies the modulated current I 2  by a demodulation code d 0  identical to the modulation code m 0  to reproduce the alternating-current power generated by the power generator  1 , and supply the reproduced alternating-current power to a load  5 . 
     The frequency of the modulation code m 0  and the demodulation code d 0  is set to frequencies higher than the frequency of the generated current I 1  and the frequency of the demodulated current I 3 . According to the exemplary signal waveform of  FIG. 9 , the alternating-current generated current I 1  ( FIG. 9( a ) ) is multiplied by the modulation code m 0  having a frequency of 35 kHz to generate the modulated current I 2  ( FIG. 9( b ) ) of the code-modulated wave. In this case, the duration of each bit of the modulation code m 0  is 1/(35 kHz)/2=14.2 microseconds. 
     Each bit of the modulation code m 0  and the demodulation code d 0  has a code value “1” or “−1”. In case of transmission of the alternating-current generated current I 1 , the meaning of the code value “1” or “−1” in a period when the generated current I 1  is positive (period from 0 to 100 microsecond in  FIG. 9( a ) ) is different from that of a period when the generated current I 1  is negative (period from 100 to 200 microsecond in  FIG. 9( a ) ). In the period when the generated current I 1  is positive, the code value “1” of the modulation code m 0  indicates that the code modulator  2 A outputs a current in the same direction as the direction of an inputted current, and the code value “−1” of the modulation code m 0  indicates that the code modulator  2 A outputs a current in the direction opposite to the direction of an inputted current. Similarly, in the period when the generated current I 1  is positive, the code value “1” of the demodulation code d 0  indicates that the code demodulator  4 A outputs a current in the same direction as the direction of an inputted current, and the code value “−1” of the demodulation code d 0  indicates that the code demodulator  4 A outputs a current in the direction opposite to the direction of an inputted current. In the period when the generated current I 1  is negative, the code value “1” of the modulation code m 0  indicates that the code modulator  2 A outputs a current in the direction opposite to the direction of an inputted current, and the code value “−1” of the modulation code m 0  indicates that the code modulator  2 A outputs a current in the same direction as the direction of an inputted current. Similarly, in the period when the generated current I 1  is negative, the code value “1” of the demodulation code d 0  indicates that the code demodulator  4 A outputs a current in the direction opposite to the direction of an inputted current, and the code value “−1” of the demodulation code d 0  indicates that the code demodulator  4 A outputs a current in the same direction as the direction of an inputted current. 
     For example, the modulation code m 0  and the demodulation code d 0  are given as follows.
 
 m 0=[1 −1 1 1 1 −1 −1 −1 1 −1 −1 −1 1 1]  (6)
 
 d 0= m 0=[1 −1 1 1 1 −1 −1 −1 1 −1 −1 −1 1 1]  (7)
 
     Similarly to the code demodulation according to the first embodiment, the modulated current I 2  of the code-modulated wave generated by the modulation code m 0  is multiplied by the demodulation code d 0 . This multiplication is denoted as follows.
 
 m 0× d 0=[1 1 1 1 1 1 1 1 1 1 1 1 1 1]  (8)
 
     As apparent from Mathematical Expression (8), the demodulated current I 3  ( FIG. 8( c ) ) is obtained, which is an alternating current similarly to the original generated current I 1 . 
     As described above, it is possible to achieve power transmission in an accurately synchronized manner, without power loss, by using the method of code modulation and code demodulation according to the present embodiment. In addition, it is possible to achieve efficient power transmission for a longer period, for example, by repeatedly using the modulation code m 0  and demodulation code d 0  as described above. 
       FIG. 10  is a block diagram showing a partial configuration of the code modulator  2 A of the power transmission system according to the second embodiment. The code modulator  2 A of  FIG. 10  is provided with a code generation circuit  22 A and a code modulation circuit  23 A, in place of the code generation circuit  22  and the code modulation circuit  23  of  FIG. 5 . The code modulator  2 A of  FIG. 10  is further provided with a control circuit  20  and a communication circuit  21  similarly to the code modulator  2  of  FIG. 5 , which are omitted in  FIG. 10  for ease of illustration. 
     The code generation circuit  22 A and the code modulation circuit  23 A of  FIG. 10  are different from the code generation circuit  22  and the code modulation circuit  23  of  FIG. 7  in following points. 
     (1) The code generation circuit  22 A generates four modulation codes m 1  to m 4  in place of the two modulation codes m 1  and m 2 , and outputs the generated modulation codes m 1  to m 4  to the code modulation circuit  23 A. 
     (2) The code modulation circuit  23 A is provided with first to fourth bidirectional switch circuits SS 21  to SS 24  connected in a bridge configuration, in place of the unidirectional switch circuits SS 1  to SS 4 . 
     The code generation circuit  22 A generates and outputs the modulation codes m 1  to m 4  to the code modulation circuit  23 A under control of the control circuit  20 , in order to operate the code modulator  2 A according to the modulation code m 0  as described above. Each of the modulation codes m 1  to m 4  has code values “1” and “0”. 
     In the code modulation circuit  23 A, the switch circuit SS 21  is provided with the switch element S 1  of  FIG. 7  to be turned on and off in response to the modulation code m 1 , and further provided with a switch element S 21  having directionality opposite to that of the switch element S 1 , connected in parallel to the switch element S 1 , and to be turned on and off in response to the modulation code m 3 . The switch circuit SS 22  is provided with the switch element S 2  of  FIG. 7  to be turned on and off in response to the modulation code m 2 , and further provided with a switch element S 22  having directionality opposite to that of the switch element S 2 , connected in parallel to the switch element S 2 , and to be turned on and off in response to the modulation code m 4 . The switch circuit SS 23  is provided with the switch element S 3  of  FIG. 7  to be turned on and off in response to the modulation code m 2 , and further provided with a switch element S 23  having directionality opposite to that of the switch element S 3 , connected in parallel to the switch element S 3 , and to be turned on and off in response to the modulation code m 4 . The switch circuit SS 24  is provided with the switch element S 4  of  FIG. 7  to be turned on and off in response to the modulation code m 1 , and further provided with a switch element S 24  having directionality opposite to that of the switch element S 4 , connected in parallel to the switch element S 4 , and to be turned on and off in response to the modulation code m 3 . Each of the switch elements S 21  to S 24  is made of, for example, an MOS transistor. The code modulation circuit  23 A has ports T 1  and T 2  (first and second ports) connected to a power generator  1 , and ports T 3  and T 4  (third and fourth ports) connected to the transmission path  3 . Alternating-current power is inputted from the power generator  1  to the code modulation circuit  23 A. The code modulation circuit  23 A modulates the alternating-current power by code modulation, and then, outputs a code-modulated wave to the transmission path  3 . 
       FIG. 11  is a block diagram showing a partial configuration of the code demodulator  4 A of the power transmission system according to the second embodiment. The code demodulator  4 A of  FIG. 11  is provided with a code generation circuit  32 A and a code demodulation circuit  33 A, in place of the code generation circuit  32  and the code demodulation circuit  33  of  FIG. 6 . The code demodulator  4 A of  FIG. 11  is further provided with a control circuit  30  and a communication circuit  31  similarly to the code demodulator  4  of  FIG. 5 , which are omitted in  FIG. 11  for ease of illustration. 
     The code generation circuit  32 A and the code demodulation circuit  33 A of  FIG. 11  are different from the code generation circuit  32  and the code demodulation circuit  33  of  FIG. 7  in following points. 
     (1) The code generation circuit  32 A generates four demodulation codes d 1  to d 4  in place of the two modulation codes d 1  and d 2 , and outputs the generated demodulation codes d 1  to d 4  to the code demodulation circuit  33 A. 
     (2) The code demodulation circuit  33 A is provided with fifth to eighth bidirectional switch circuits SS 31  to SS 34  connected in a bridge configuration, in place of the unidirectional switch circuits SS 11  to SS 14 . 
     The code generation circuit  32 A generates and outputs the demodulation codes d 1  to d 4  to the code demodulation circuit  33 A under control of the control circuit  30 , in order to operate the code demodulator  4 A according to the demodulation code d 0  as described above. Each of the demodulation codes d 1  and d 4  has code values “1” and “0”. 
     In the code demodulation circuit  33 A, the switch circuit SS 31  is provided with the switch element S 11  of  FIG. 7  to be turned on and off in response to the demodulation code d 2 , and further provided with a switch element S 31  having directionality opposite to that of the switch element S 11 , connected in parallel to the switch element S 11 , and to be turned on and off in response to the demodulation code d 4 . The switch circuit SS 32  is provided with the switch element S 12  of  FIG. 7  to be turned on and off in response to the demodulation code d 1 , and further provided with a switch element S 32  having directionality opposite to that of the switch element S 12 , connected in parallel to the switch element S 12 , and to be turned on and off in response to the demodulation code d 3 . The switch circuit SS 33  is provided with the switch element S 13  of  FIG. 7  to be turned on and off in response to the demodulation code d 1 , and further provided with a switch element S 33  having directionality opposite to that of the switch element S 13 , connected in parallel to the switch element S 13 , and to be turned on and off in response to the demodulation code d 3 . The switch circuit SS 34  is provided with the switch element S 14  of  FIG. 7  to be turned on and off in response to the demodulation code d 2 , and further provided with a switch element S 34  having directionality opposite to that of the switch element S 14 , connected in parallel to the switch element S 14 , and to be turned on and off in response to the demodulation code d 4 . Each of the switch elements S 31  to S 34  is made of, for example, an MOS transistor. The code demodulation circuit  33 A has ports T 11  and T 12  (fifth and sixth ports) connected to the transmission path  3 , and ports T 13  and T 14  (seventh and eighth ports) connected to the load  5 . An alternating-current code-modulated wave is inputted from the transmission path  3  to the code demodulation circuit  33 A. The code demodulation circuit  33 A demodulates the code-modulated wave by code demodulation into alternating-current demodulated power, and then outputs the demodulated power to the load  5 . 
       FIG. 12A  is a diagram showing an example of a modulation code of the code modulator  2 A and a demodulation code of the code demodulator  4 A in the power transmission system according to the second embodiment, as a third implementation example in which alternating-current power is transmitted and received. More specifically,  FIG. 12A  shows an example of the modulation codes m 1  to m 4  inputted to the bidirectional switch circuits SS 21  to SS 24  of the code modulation circuit  23 A, and the demodulation codes d 1  to d 4  inputted to the bidirectional switch circuits SS 31  to SS 34  of the code demodulation circuit  33 A. 
     As shown in  FIG. 12A , the modulation code m 1  and the demodulation code d 1  are identical to each other, and the modulation code m 2  and the demodulation code d 2  are identical to each other. Similarly, the modulation code m 3  and the demodulation code d 3  are identical to each other, and the modulation code m 4  and the demodulation code d 4  are identical to each other. In addition, similarly to the case of direct-current power transmission, code sequences c 1   a  and c 1   b  are configured such that when the code value of a certain bit of the code sequence c 1   a  is “1”, the code value of a corresponding bit of the code sequence c 1   b  is “0”; and when the code value of a certain bit of the code sequence c 1   a  is “0”, the code value of a corresponding bit of the code sequence c 1   b  is “1”. 
       FIG. 12A  shows a case in which the duration of the code sequence c 1   a  and the code sequence c 1   b  is set to be equal to a half of the cycle of the alternating-current generated current I 1 . In a period when the alternating-current generated current I 1  flows in the positive direction (in example of  FIG. 12A , first half period of each cycle), the modulation codes m 1  and m 2  are the code sequences c 1   a  and c 1   b , respectively, and on the other hand, all code values of the modulation codes m 3  and m 4  are “0”. In a period when the alternating-current generated current I 1  flows in the negative direction (in example of  FIG. 12A , second half period of each cycle), all the code values of the modulation codes m 1  and m 2  are “0”, and on the other hand, the modulation codes m 3  and m 4  are the code sequences c 1   a  and c 1   b , respectively. Each of the modulation codes m 1  to m 4  for one cycle is generated by concatenating bits for a first half of each cycle with bits for a second half of each cycle. Accordingly, in the first half of each cycle, the switch elements S 1  to S 4  are turned on and off according to the modulation codes m 1  and m 2 , and on the other hand, the switch elements S 21  to S 24  are disconnected and no current flows. In addition, in the second half of each cycle, the switch elements S 1  to S 4  are disconnected and no current flows, and on the other hand, the switch elements S 21  to S 24  are turned on and off according to the modulation codes m 3  and m 4 . Similarly to the modulation codes m 1  to m 4 , each of the demodulation codes d 1  to d 4  for one cycle is generated by concatenating bits for the first half of each cycle with bits for the second half of each cycle. 
     Now, operation of the code modulation circuit  23 A is described. 
     At first, operation is described for a case in which the generated current I 1  flows at the input ports T 1  and T 2  in the positive direction, i.e., in a direction of solid arrows A 1 . In this case, when the switch elements S 1  and S 4  receiving the code value “1” of the modulation code m 1  are turned on, the switch elements S 2  and S 3  receiving the code value “0” of the modulation code m 2  are turned off. In addition, when the switch elements S 1  and S 4  receiving the code value “0” of the modulation code m 1  are turned off, the switch elements S 2  and S 3  receiving the code value “1” of the modulation code m 2  are turned on. Thus, when the switch elements S 1  and S 4  are turned on, and the switch elements S 2  and S 3  are turned off, the modulated current I 2  flows in the transmission path  3  in a positive direction, i.e., in a direction of the solid arrows A 1 . On the other hand, when the switch elements S 1  and S 4  are turned off, and the switch elements S 2  and S 3  are turned on, the modulated current I 2  flows in the transmission path  3  in a negative direction, i.e., in a direction of dotted arrows A 2 . Accordingly, when the current of positive period of the alternating-current generated current I 1  is inputted to the code modulation circuit  23 A, it is possible to transmit the alternating-current modulated current I 2  to the transmission path  3 , as shown in  FIG. 9( b ) . 
     Next, operation is described for a case in which the generated current I 1  flows at the input ports T 1  and T 2  in a negative direction, i.e., in a direction of chain arrows B 1 . In this case, when the switch elements S 21  and S 24  receiving the code value “1” of the modulation code m 3  are turned on, the switch elements S 22  and S 23  receiving the code value “0” of the modulation code m 4  are turned off. In addition, when the switch elements S 21  and S 24  receiving the code value “0” of the modulation code m 3  are turned off, the switch elements S 22  and S 23  receiving the code value “1” of the modulation code m 4  are turned on. Thus, when the switch elements S 21  and S 24  are turned on, and the switch elements S 22  and S 23  are turned off, the modulated current I 2  flows in the transmission path  3  in a negative direction, i.e., in a direction of the chain arrows B 1 . On the other hand, when the switch elements S 21  and S 24  are turned off, and the switch elements S 22  and S 23  are turned on, the modulated current I 2  flows in the transmission path  3  in a positive direction, i.e., in a direction of two-dot chain arrows B 2 . Accordingly, when the current of negative period of the alternating-current generated current I 1  is inputted to the code modulation circuit  23 A, it is possible to transmit the alternating-current modulated current I 2  to the transmission path  3 , as shown in  FIG. 9( b ) . 
     As described with reference to  FIG. 10 , the code modulation circuit  23 A can generate the alternating-current modulated current I 2 , as shown in  FIG. 9( b ) , in both the positive and negative periods of the alternating-current generated current I 1 . 
     Next, operation of the code demodulation circuit  33 A of  FIG. 11  is described. 
     At first, we consider a case in which the generated current I 1  flows at the input ports T 1  and T 2  of the code modulation circuit  23 A in the positive direction, i.e., in the direction of the solid arrows A 1 . In this case, the alternating-current modulated current I 2  flowing in the positive and negative directions is inputted to the input ports T 11  and T 12  of the code demodulation circuit  33 A via the transmission path  3 . When the code demodulation circuit  33 A correctly performs demodulation operation, the demodulated current I 3  flows at the output ports T 13  and T 14  of the code demodulation circuit  33 A in a positive direction, i.e., in a direction of solid arrows C 1 . These operations are described below. In this case, all code values of the demodulation code d 3  and the demodulation code d 4  are “0”, and all the switch elements S 31  to S 34  are turned off. 
     At first, operation of the code demodulation circuit  33 A is described for a case in which the generated current I 1  flows at the input ports T 1  and T 2  of the code modulation circuit  23 A in the positive direction, and the modulated current I 2  flows at the input ports T 11  and T 12  of the code demodulation circuit  33 A in the positive direction, i.e., in the direction of the solid arrows C 1 . In this case, the code value of the code sequence c 1   a  is “1”, and the code value of the code sequence c 1   b  is “0”. Accordingly, the switch elements S 12  and S 13  receiving the code value “1” of the demodulation code d 1  are turned on, and the switch elements S 11  and S 14  receiving the code value “0” of the demodulation code d 2  are turned off. Therefore, the demodulated current I 3  flows at the output ports T 13  and T 14  in the positive direction, i.e., in the direction of the solid arrows C 1 . 
     Next, operation of the code demodulation circuit  33 A is described for a case in which the generated current I 1  flows at the input ports T 1  and T 2  of the code modulation circuit  23 A in the positive direction, and the modulated current I 2  flows at the input ports T 11  and T 12  of the code demodulation circuit  33 A in the negative direction, i.e., in the direction of dotted arrows C 2 . In this case, the code value of the code sequence c 1   a  is “0”, and the code value of the code sequence c 1   b  is “1”. Accordingly, the switch elements S 12  and S 13  receiving the code value “0” of the demodulation code d 1  are turned off, and the switch elements S 11  and S 14  receiving the code value “1” of the demodulation code d 2  are turned on. Therefore, the demodulated current I 3  flows at the output ports T 13  and T 14  in the positive direction, i.e., in the direction of the solid arrows C 1 . Accordingly, when the current of positive period of the alternating-current generated current I 1  is inputted to the code modulation circuit  23 A, the code demodulation circuit  33 A can output the demodulated current I 3  which is correctly demodulated with positive polarity, to the load  5 , as shown in  FIG. 9( c ) . 
     Next, we consider a case in which the generated current I 1  flows at the input ports T 1  and T 2  of the code modulation circuit  23 A in the negative direction, i.e., in the direction of the chain arrows B 1 . Similarly to the above case, the alternating-current modulated current I 2  flowing in the positive and negative directions is inputted to the input ports T 11  and T 12  of the code demodulation circuit  33 A via the transmission path  3 . When the code demodulation circuit  33 A correctly performs demodulation operation, the demodulated current I 3  flows at the output ports T 13  and T 14  of the code demodulation circuit  33 A in the negative direction, i.e., in a direction of the dotted arrows C 2 . These operations are described below. In this case, all code values of the demodulation codes d 1  and d 2  are “0”, and all the switch elements S 11  to S 14  are turned off. 
     At first, described is operation of the code demodulation circuit  33 A for a case in which the generated current I 1  flows at the input ports T 1  and T 2  of the code modulation circuit  23 A in the negative direction, and the modulated current I 2  flows at the input ports T 11  and T 12  of the code demodulation circuit  33 A in the negative direction, i.e., in the direction of dotted arrows C 2 . In this case, the code value of the code sequence c 1   a  is “1”, and the code value of the code sequence c 1   b  is “0”. Accordingly, the switch elements S 32  and S 33  receiving the code value “1” of the demodulation code d 3  are turned on, and the switch elements S 31  and S 34  receiving the code value “0” of the demodulation code d 4  are turned off. Therefore, the demodulated current I 3  flows at the output ports T 13  and T 14  in the negative direction, i.e., in the direction of the dotted arrows C 2 . 
     Next, operation of the code demodulation circuit  33 A is described for a case in which the generated current I 1  flows at the input ports T 1  and T 2  of the code modulation circuit  23 A in the negative direction, and the modulated current I 2  flows at the input ports T 11  and T 12  of the code demodulation circuit  33 A in the positive direction, i.e., in the direction of the solid arrows C 1 . In this case, the code value of the code sequence c 1   a  is “0”, and the code value of the code sequence c 1   b  is “1”. Accordingly, the switch elements S 32  and S 33  receiving the code value “0” of the demodulation code d 3  are turned off, and the switch elements S 31  and S 34  receiving the code value “1” of the demodulation code d 4  are turned on. Therefore, the demodulated current I 3  flows at the output ports T 13  and T 14  in the negative direction, i.e., in the direction of the dotted arrows C 2 . Accordingly, when the current of negative period of the alternating-current generated current I 1  is inputted to the code modulation circuit  23 A, the code demodulation circuit  33 A can output the demodulated current I 3  which is correctly demodulated with negative polarity, to the load  5 , as shown in  FIG. 9( c ) . 
     As described above, when using the modulation codes m 1  to m 4  and the demodulation codes d 1  to d 4  of  FIG. 12A , equivalently, the code modulator  2 A operates according to the modulation code m 0  of Mathematical Expression (6), and the code demodulator  4 A operates according to the demodulation code d 0  of Mathematical Expression (7). 
     As described above, according to  FIGS. 10, 11, and 12A , when the alternating-current generated current I 1  is inputted to the code modulator  2 A, it is possible to extract the demodulated current I 3  from the code demodulator  4 A, the demodulated current I 3  being also an alternating current similarly to the generated current I 1  inputted to the code modulator  2 A. Therefore, according to the second embodiment, it is possible to modulate the alternating-current generated current I 1  by code modulation into the alternating-current modulated current I 2 , and then, transmit the modulated current I 2  via the transmission path  3 , and then, demodulate the modulated current I 2  into the alternating-current demodulated current I 3 . 
       FIG. 12B  is a diagram showing an example of a modulation code of the code modulator  2 A and a demodulation code of the code demodulator  4 A in the power transmission system according to the second embodiment, as a fourth implementation example in which direct-current power is transmitted and received. In this case, in the code modulation circuit  23 A of  FIG. 10  and the code demodulation circuit  33 A of  FIG. 11 , all code values of the modulation codes m 3  and m 4  and the demodulation codes d 3  and d 4  are set to “0” as shown in  FIG. 12B , and thus, the switch elements S 21  to S 24  and S 31  to S 34  are turned off. Thus, the code modulation circuit  23 A of  FIG. 10  and the code demodulation circuit  33 A of  FIG. 11  operate as the code modulation circuit  23  and the code demodulation circuit  33  of  FIG. 7 , respectively. Accordingly, it is possible to achieve direct-current power transmission of  FIG. 4  by generating the modulation codes m 1  and m 2  and the demodulation codes d 1  and d 2  from the code sequences c 1   a  and c 1   b  as shown in  FIG. 12B . Thus, by changing the modulation codes m 1  to m 4  and the demodulation codes d 1  to d 4 , it is possible to achieve a favorable power transmission system capable of supporting both direct-current power transmission and alternating-current power transmission using the code modulation circuit  23 A of  FIG. 10  and the code demodulation circuit  33 A of  FIG. 11 . 
     The direct-current power generator  1  may be, for example, a photovoltaic power generator. The alternating-current power generator  1  may be, for example, a power generator provided with a turbine rotated by thermal power, hydraulic power, wind power, nuclear power, tidal power, or the like. 
     As described above, by using the modulation code and the demodulation code identical to each other, the power transmission system according to the second embodiment is capable of modulating and transmitting the direct-current generated current I 1  and demodulating the modulated current into the direct-current demodulated current I 3 , and is also capable of modulating and transmitting the alternating-current generated current I 1  and demodulating the modulated current into the alternating-current demodulated current I 3 . In addition, by using the demodulation code different from the modulation code, the power transmission system according to the second embodiment is capable of modulating and transmitting the direct-current generated current I 1  and demodulating the modulated current into the alternating-current demodulated current I 3 , and is also capable of modulating and transmitting the alternating-current generated current I 1  and demodulating the modulated current into the direct-current demodulated current I 3 . 
     Since the code modulation circuit  23 A of  FIG. 10  and the code demodulation circuit  33 A of  FIG. 11  are provided with the bidirectional switch circuits SS 21  to SS 24  and SS 31  to SS 34 , these circuits are reversible. More specifically, the code modulation circuit  23 A is also operable as a code demodulation circuit to demodulate a modulated current inputted from the ports T 3  and T 4  and output the demodulated current from the ports T 1  and T 2 . The code demodulation circuit  33 A is also operable as a code modulation circuit to modulate a generated current inputted from the ports T 13  and T 14  and output the modulated current from the ports T 11  and T 12 . Thus, it is possible to transmit power from the code demodulator  4 A provided with the code demodulation circuit  33 A, to the code modulator  2 A provided with the code modulation circuit  23 A. 
       FIGS. 10 to 11  show the example in which each of the bidirectional switch circuits SS 21  to SS 34  is made of a pair of switch elements connected in parallel such that currents flow in opposite directions (S 1 , S 21 ; S 2 , S 22 ; S 3 , S 23 ; S 4 , S 24 ; S 11 , S 31 ; S 12 , S 32 ; S 13 , S 33 ; S 14 , S 34 ). Alternatively, each of the bidirectional switch circuits SS 21  to SS 34  may be made of a pair of switch elements connected in series, as shown in  FIGS. 13A to 14D  (S 41 , S 51 ; S 42 , S 52 ; S 43 , S 53 ; S 44 , S 54 ). In each of  FIGS. 13A to 14D , the direction from top to bottom is referred to as a “positive direction”, and the direction from bottom to top is referred to as a “negative direction”. 
       FIG. 13A  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 21 A for a code modulation circuit  23 A used in a power transmission system according to a modified embodiment of the second embodiment. The switch circuit SS 21 A of  FIG. 13A  corresponds to the switch circuit SS 21  of  FIG. 10 , and is made of series connection of: (1) a switch element S 41  connected in parallel with a diode D 1  allowing a current to flow in the negative direction, and turned on and off in accordance with the modulation code m 1 ; and (2) a switch element S 51  connected in parallel with a diode D 11  allowing a current to flow in the positive direction, and turned on and off in accordance with the modulation code m 3 . 
       FIG. 13B  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 22 A for the code modulation circuit  23 A used in the power transmission system according to the modified embodiment of the second embodiment. The switch circuit SS 22 A of  FIG. 13B  corresponds to the switch circuit SS 22  of  FIG. 10 , and is made of series connection of: (1) a switch element S 42  connected in parallel with a diode D 2  allowing a current to flow in the negative direction, and turned on and off in accordance with the modulation code m 2 ; and (2) a switch element S 52  connected in parallel with a diode D 12  allowing a current to flow in the positive direction, and turned on and off in accordance with the modulation code m 4 . 
       FIG. 13C  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 23 A for the code modulation circuit  23 A used in the power transmission system according to the modified embodiment of the second embodiment. The switch circuit SS 23 A of  FIG. 13C  corresponds to the switch circuit SS 23  of  FIG. 10 , and is made of series connection of: (1) a switch element S 43  connected in parallel with a diode D 3  allowing a current to flow in the negative direction, and turned on and off in accordance with the modulation code m 2 ; and (2) a switch element S 53  connected in parallel with a diode D 13  allowing a current to flow in the positive direction, and turned on and off in accordance with the modulation code m 4 . 
       FIG. 13D  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 24 A for the code modulation circuit  23 A used in the power transmission system according to the modified embodiment of the second embodiment. The switch circuit SS 24 A of  FIG. 13D  corresponds to the switch circuit SS 24  of  FIG. 10 , and is made of series connection of: (1) a switch element S 44  connected in parallel with a diode D 4  allowing a current to flow in the negative direction, and turned on and off in accordance with the modulation code m 1 ; and (2) a switch element S 54  connected in parallel with a diode D 14  allowing a current to flow in the positive direction, and turned on and off in accordance with the modulation code m 3 . 
       FIG. 14A  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 31 A for a code demodulation circuit  33 A used in the power transmission system according to the modified embodiment of the second embodiment. The switch circuit SS 31 A of  FIG. 14A  corresponds to the switch circuit SS 31  of  FIG. 11 , and is made of series connection of: (1) a switch element S 61  connected in parallel with a diode D 31  allowing a current to flow in the positive direction, and turned on and off in accordance with the demodulation code d 2 ; and (2) a switch element S 71  connected in parallel with a diode D 21  allowing a current to flow in the negative direction, and turned on and off in accordance with the demodulation code d 4 . 
       FIG. 14B  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 32 A for the code demodulation circuit  33 A used in the power transmission system according to the modified embodiment of the second embodiment. The switch circuit SS 32 A of  FIG. 14B  corresponds to the switch circuit SS 32  of  FIG. 11 , and is made of series connection of: (1) a switch element S 62  connected in parallel with a diode D 32  allowing a current to flow in the positive direction, and turned on and off in accordance with the demodulation code d 1 ; and (2) a switch element S 72  connected in parallel with a diode D 22  allowing a current to flow in the negative direction, and turned on and off in accordance with the demodulation code d 3 . 
       FIG. 14C  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 33 A for the code demodulation circuit  33 A used in the power transmission system according to the modified embodiment of the second embodiment. The switch circuit SS 33 A of  FIG. 14C  corresponds to the switch circuit SS 33  of  FIG. 11 , and is made of series connection of: (1) a switch element S 63  connected in parallel with a diode D 33  allowing a current to flow in the positive direction, and turned on and off in accordance with the demodulation code d 1 ; and (2) a switch element S 73  connected in parallel with a diode D 23  allowing a current to flow in the negative direction, and turned on and off in accordance with the demodulation code d 3 . 
       FIG. 14D  is a circuit diagram showing a configuration of a bidirectional switch circuit SS 34 A for the code demodulation circuit  33 A used in the power transmission system according to the modified embodiment of the second embodiment. The switch circuit SS 34 A of  FIG. 14D  corresponds to the switch circuit SS 34  of  FIG. 11 , and is made of series connection of: (1) a switch element S 64  connected in parallel with a diode D 34  allowing a current to flow in the positive direction, and turned on and off in accordance with the demodulation code d 2 ; and (2) a switch element S 74  connected in parallel with a diode D 24  allowing a current to flow in the negative direction, and turned on and off in accordance with the demodulation code d 4 . 
     Referring to  FIG. 13A  to  FIG. 14D , each of the switch elements S 41  to S 74  may be made of, for example, an MOS transistor. Parallel parasitic (body) diodes D 1  to D 34  of MOS transistors may be used. For example, when each of the switch circuits SS 21 A to SS 34 A of  FIGS. 13A to 14D  is implemented by a switch element of an MOS transistor and one diode, two MOS transistors and two diodes are required for each one of the bidirectional switch circuit SS 21 A to SS 34 A. Meanwhile, packaged MOS transistors are widely available, including a built-in diode having good reverse characteristics. When using such packaged MOS transistors, each of the bidirectional switch circuits SS 21 A to SS 34 A can be made of two switch elements, and thus, size can be reduced. 
     Third Embodiment 
     In the first and second embodiments, we have described the power transmission systems which transmit power from the one power generator  1  to the one load  5 . Meanwhile, in a third embodiment, we describe a power transmission system which transmits powers from a plurality of power generators to a plurality of loads. 
       FIG. 15  is a block diagram showing a configuration of a power transmission system according to the third embodiment. Referring to  FIG. 15 , the power transmission system according to the third embodiment includes a plurality of power generators  1 - 1  and  1 - 2 , a plurality of code modulators  2 A- 1  and  2 A- 2 , a transmission path  3 , a plurality of code demodulators  4 A- 1  and  4 A- 2 , a plurality of loads  5 - 1  and  5 - 2 , and a controller  10 A. 
     The controller  10 A is provided with a control circuit  11  and a communication circuit  12 A. The control circuit  11  communicates with the code modulators  2 A- 1  and  2 A- 2  and the code demodulators  4 A- 1  and  4 A- 2  via the communication circuit  12 A, and controls operations of the code modulators  2 A- 1  and  2 A- 2  and the code demodulators  4 A- 1  and  4 A- 2 . 
     In the power transmission system of  FIG. 15 , each of the code modulators  2 A- 1  and  2 A- 2  operates as a power transmitter apparatus, and each of the code demodulators  4 A- 1  and  4 A- 2  operates as a power receiver apparatus. Each code modulator of the code modulators  2 A- 1  and  2 A- 2  modulates first power to generate a code-modulated wave by code modulation using a modulation code based on a code sequence, and transmits the code-modulated wave to one of the code demodulators  4 A- 1  and  4 A- 2  via the transmission path  3 . Each one of the code demodulators  4 A- 1  and  4 A- 2  receives the code-modulated wave from one of the code modulators  2 A- 1  and  2 A- 2  via the transmission path  3 , and demodulates the received code-modulated wave to generate second power by code demodulation using a demodulation code based on a code sequence identical to the code sequence of the modulation code used for the code modulation. The first powers are, for example, powers generated by the power generators  1 - 1  and  1 - 2 , and are shown as generated currents I 11  and  112  in  FIG. 15 . The code-modulated wave is alternating-current power modulated by code modulation, and is shown as a modulated current I 2  in  FIG. 15 . The second power are, for example, powers to be supplied to the loads  5 - 1  and  5 - 2 , and are shown as demodulated currents I 31  and I 32  in  FIG. 15 . 
     In this case, the code modulators  2 A- 1  and  2 A- 2  and the code demodulators  4 A- 1  and  4 A- 2  of  FIG. 15  are configured and operated similarly to the code modulator  2 A and the code demodulator  4 A according to the second embodiment. 
     The power transmission system of  FIG. 15  is further provided with power meters  1   m - 1 ,  1   m - 2 ,  5   m - 1 , and  5   m - 2 . Each of the power meters  1   m - 1  and  1   m - 2  is first power measuring means which measures an amount of the first power. More specifically, each of the power meters  1   m - 1  and  1   m - 2  measures an amount of power generated by the power generators  1 - 1  and  1 - 2  and transmitted from the power generators  1 - 1  and  1 - 2  to the code modulators  2 A- 1  and  2 A- 2 . Each of the power meters  5   m - 1  and  5   m - 2  is second power measuring means which measures an amount of the second power. More specifically, each of the power meters  5   m - 1  and  5   m - 2  measures an amount of power transmitted from the code demodulators  4 A- 1  and  4 A- 2  to the loads  5 - 1  and  5 - 2 , and used by the loads  5 - 1  and  5 - 2 . The amounts of powers measured by the power meters  1   m - 1 ,  1   m - 2 ,  5   m - 1 , and  5   m - 2  are transmitted to the controller  10 A. 
     The controller  10 A controls operations of the code modulators  2 A- 1  and  2 A- 2  and the code demodulators  4 A- 1  and  4 A- 2  based on the amounts of powers received from the power meters  1   m - 1 ,  1   m - 2 ,  5   m - 1 , and  5   m - 2 . For example, the controller  10 A transmits control signals to the code modulators  2 A- 1  and  2 A- 2  and the code demodulators  4 A- 1  and  4 A- 2 , the control signals including synchronization signals for synchronizing the code modulators  2 A- 1  and  2 A- 2  and the code demodulators  4 A- 1  and  4 A- 2  to each other, thus achieving code modulation and code demodulation of power in an accurately synchronized manner. 
     The controller  10 A transmits the code sequences of the modulation codes, or information specifying the code sequences, to at least one of the code modulators  2 A- 1  and  2 A- 2 , which is to transmit power, and transmits the code sequences of the demodulation codes, or information specifying the code sequences, to at least one of the code demodulators  4 A- 1  and  4 A- 2 , which is to receive power. For example, when transmitting power from the code modulator  2 A- 1  to the code demodulator  4 A- 1 , the controller  10 A sets a modulation code to the code modulator  2 A- 1 , and a demodulation code to the code demodulator  4 A- 1 , based on one code sequence. When simultaneously transmitting power from the code modulator  2 A- 2  to the code demodulator  4 A- 2 , the controller  10 A sets a modulation code to the code modulator  2 A- 2 , and a demodulation code to the code demodulator  4 A- 2 , based on another different code sequence. When simultaneously transmitting powers from the plurality of code modulators  2 A- 1  and  2 A- 2  to the plurality of code demodulators  4 A- 1  and  4 A- 2 , a plurality of low-correlated (e.g., orthogonal) code sequences may be used. 
     Thus, it is possible to transmit powers from the plurality of power generators  1 - 1  and  1 - 2  to the plurality of loads  5 - 1  and  5 - 2 . 
     Now, we describe exemplary operations of the code modulators  2 A- 1  and  2 A- 2  and the code demodulators  4 A- 1  and  4 A- 2  for transmitting powers generated by the power generators  1 - 1  and  1 - 2  to the loads  5 - 1  and  5 - 2 . 
     In the third embodiment, we describe a case in which the power generators  1 - 1  and  1 - 2  output direct-current powers, direct-current power is inputted to the load  5 - 1 , and alternating-current power is inputted to the load  5 - 2 . That is, when transmitting power from the power generator  1 - 2  to the load  5 - 2 , direct-current power is converted into alternating-current power. 
       FIG. 16A  is a diagram showing an example of a modulation code of the code modulator  2 A- 1  and a demodulation code of the code demodulator  4 A- 1  in the power transmission system of  FIG. 15  according to the third embodiment, in which direct-current power is transmitted and received. In addition,  FIG. 16B  is a diagram showing an example of a modulation code of the code modulator  2 A- 2  and a demodulation code of the code demodulator  4 A- 2  in the power transmission system of  FIG. 15  according to the third embodiment, in which direct-current power is transmitted and alternating-current power is received. 
       FIG. 16A  shows modulation codes and demodulation codes inputted to the switch elements S 1  to S 44  of the code modulator  2 A- 1  and the code demodulator  4 A- 1 . In this case, modulation codes m 1   a  to m 4   a  correspond to the modulation codes m 1  to m 4  of the code modulation circuit  23 A of  FIG. 10 , respectively, and demodulation codes d 1   a  to d 4   a  correspond to the demodulation codes d 1  to d 4  of the code demodulation circuit  33 A of  FIG. 11 , respectively. In this case, as described with reference to  FIG. 12B , by setting all the code values of the modulation codes m 3   a  and m 4   a  and the demodulation codes d 3   a  and d 4   a  to “0”, the switch elements S 21  to S 24  and S 31  to S 34  are turned off. In addition, the modulation codes m 1   a  and m 2   a  and the demodulation codes d 1   a  and d 2   a  are generated from the code sequence c 1   a  and the code sequence c 1   b , as described with reference to  FIG. 12B . 
     Further,  FIG. 16B  shows modulation codes and demodulation codes inputted to the switch elements S 1  to S 44  of the code modulator  2 A- 2  and the code demodulator  4 A- 2 . In this case, modulation codes m 1   a  to m 4   a  correspond to the modulation codes m 1  to m 4  of the code modulation circuit  23 A of  FIG. 10 , respectively, and demodulation codes d 1   a  to d 4   a  correspond to the demodulation codes d 1  to d 4  of the code demodulation circuit  33 A of  FIG. 11 , respectively. In this case, by setting all the code values of the modulation codes m 3   b  and m 4   b  to “0”, the switch elements S 21  to S 24  are turned off. In addition, the modulation codes m 1   b  and m 2   b  and the demodulation codes d 1   b  to d 4   b  are generated from the code sequence c 2   a  and the code sequence c 2   b . The principle of code modulation and code demodulation of currents is similar to that of the first and second embodiments, and therefore, its explanation is omitted here. 
     Now, with reference to  FIG. 17 , we describe an operation of transmitting powers from the plurality of power generators  1 - 1  and  1 - 2  to the plurality of loads  5 - 1  and  5 - 2 . 
       FIG. 17  are waveform diagrams, where (a) to (e) show exemplary signal waveforms of the power transmission system according to the third embodiment. In  FIG. 17 , (a) shows a signal waveform of a generated current I 11 , (b) shows a signal waveform of a generated current I 12 , (c) shows a signal waveform of a modulated current I 2 , (d) shows a signal waveform of a demodulated current I 31 , and (e) shows a signal waveform of a demodulated current I 32 . 
     The code modulator  2 A- 1  modulates the direct-current generated current I 11  by code modulation into an alternating-current code-modulated wave. Similarly, the code modulator  2 A- 2  modulates the direct-current generated current I 12  by code modulation into an alternating-current code-modulated wave. As shown in  FIG. 17( c ) , the code-modulated wave generated by the code modulator  2 A- 1  and the code-modulated wave generated by the code modulator  2 A- 2  are transmitted as the combined modulated current I 2  via the transmission path  3 . 
     As described above, the code modulators  2 A- 1  and  2 A- 2  have an identical configuration, and are configured in a manner similar to that of the code modulator  2 A of  FIG. 10 . In addition, the code demodulators  4 A- 1  and  4 A- 2  also have an identical configuration, and are configured in a manner similar to that of the code demodulator  4 A of  FIG. 11 . The difference between the code modulators  2 A- 1  and  2 A- 2 , and the difference between the code demodulators  4 A- 1  and  4 A- 2  reside in the use of different sets of the code sequences c 1   a  and c 1   b , and the code sequences c 2   a  and c 2   b . The code modulator  2 A- 1  and the code demodulator  4 A- 1  use the code sequences c 1   a  and c 1   b , and the code modulator  2 A- 2  and the code demodulator  4 A- 2  use the code sequences c 2   a  and c 2   b . In this case, the code sequences c 1   a  and c 2   a  are orthogonal to each other, and therefore, the code sequences c 1   b  and c 2   b  are also orthogonal to each other. In this case, Gold sequences of seven stages are adopted, and different Gold sequences are set to the code sequences c 1   a  and c 2   a.    
     The code demodulators  4 A- 1  and  4 A- 2  can demodulate the modulated current I 2  to extract powers generated by the corresponding code modulators  2 A- 1  and  2 A- 2 , respectively, by using the orthogonal code sequences c 1   a  and c 2   a . Accordingly, as shown in  FIGS. 17( d ) and ( e ) , the generated currents I 11  and  112  are inputted to the code modulators  2 A- 1  and  2 A- 2 , and then, the currents are transmitted as code-modulated waves, and then, the corresponding code demodulators  4 A- 1  and  4 A- 2  correctly demodulate and output the demodulated currents I 31  and I 32 . As a result, the demodulated currents I 31  and I 32  having desired waveforms (direct current or alternating current) and desired magnitudes are supplied to the loads  5 - 1  and  5 - 2 , respectively. 
     As described above, according to the present embodiment, it is possible to simultaneously perform two power transmissions via the one transmission path  3  in a multiplexed manner, and separate the transmitted powers from each other, by using the code modulators  2 A- 1  and  2 A- 2  and the code demodulators  4 A- 1  and  4 A- 2 . Accordingly, it is possible to achieve a favorable power transmission system capable of simultaneously transmitting currents of desired magnitudes from the two power generators  1 - 1  and  1 - 2  to the two loads  5 - 1  and  5 - 2 . 
     By measuring instantaneous powers at the code modulators  2 A- 1  and  2 A- 2  or the code demodulators  4 A- 1  and  4 A- 2  and comparing the instantaneous powers with the code sequences, it is possible to know which of the power generators  1 - 1  and  1 - 2  transmits power, which of the loads receives power, and what amount of power is transmitted. Accordingly, when a plurality of the different power generators  1 - 1  and  1 - 2  requiring different generation costs are connected, it is possible to conduct power business with electricity charges dependent on which of the power generators  1 - 1  and  1 - 2  transmits power. Alternatively, in case of a system having variable power transmission efficiency depending on which of the power generators  1 - 1  and  1 - 2  transmits power and which of the loads  5 - 1  and  5 - 2  receives the power, it is possible to achieve optimum power supply by managing and analyzing information on power transmission. 
     As described above, according to the present embodiment, it is possible to provide the power transmission system capable of efficiently supplying power from the one or more power generators  1 - 1  and  1 - 2  to the one or more loads  5 - 1  and  5 - 2 , by using the code modulators  2 A- 1  and  2 A- 2  and the code demodulators  4 A- 1  and  4 A- 2 . 
     In the above described embodiment, we indicated the example of the power transmission system including the two power generators  1 - 1  and  1 - 2  and the two loads  5 - 1  and  5 - 2 , but the present disclosure is not limited thereto. It is possible to provide power transmission systems including the one power generator  1 - 2  and the two or more loads  5 - 1  and  5 - 2 , or including two or more power generators  1 - 1  and  1 - 2  and the two or more loads  5 - 1  and  5 - 2 . In this case, it is possible to simultaneously perform a number of power transmissions using one transmission path  3 . Accordingly, it is possible to reduce costs for installation of the transmission path  3 , and reduce costs by reducing the number of transmission paths  3 , etc. 
     In the above described embodiment, we indicated the example in which each of the code modulators  2 A- 1  and  2 A- 2  of  FIG. 15  is configured as the code modulation circuit  23 A of  FIG. 10 , but the present disclosure is not limited thereto. For example, when the output powers from the power generators  1 - 1  and  1 - 2  are direct-current powers, each of the code modulators  2 A- 1  and  2 A- 2  may be configured as the code modulation circuit  23  of  FIG. 7 . In addition, when the input powers to the loads  5 - 1  and  5 - 2  are direct-current powers, each of the code demodulators  4 A- 1  and  4 A- 2  may be configured as the code demodulation circuit  33  of  FIG. 7 . In these cases, it is possible to simplify the circuit configurations of the code modulators  2 A- 1  and  2 A- 2  and the code demodulators  4 A- 1  and  4 A- 2 , and accordingly, there are advantageous effects of reducing the number of parts, reducing costs, and reducing size of the apparatuses. 
     In the third embodiment, we indicated the example of the power transmission system which transmits powers from two power generators each having direct-current output power, to one load having direct-current input power, and to one load having alternating-current input power, but the present disclosure is not limited thereto. The power transmission system may receive powers from any number of power generators each having direct-current output power, and from any number of power generators each having alternating-current output power. In addition, the power transmission system may supply powers to any number of loads each having direct-current input power, and to any number of loads each having alternating-current input power. 
     Photovoltaic power generation, which generates most of natural energy, generates direct-current power. On the other hand, wind power generation and geothermal power generation generate alternating-current power. In this case, since it is not desirable that both direct-current power supplies and alternating-current power supplies are connected to the same power network, according to conventional power transmission systems, all power generators (power supplies) and loads should be of only direct current or only alternating current. 
     On the other hand, according to the power transmission system according to the present embodiment, by using code modulation and code demodulation, it is possible simultaneously transmit powers from a direct-current power supply to a direct-current load, from a direct-current power supply to an alternating-current load, from an alternating-current power supply to a direct-current load, and from an alternating-current power supply to an alternating-current load, via one transmission path. 
     Thus, according to the first to third embodiments, it is possible to provide a favorable power transmission system capable of correctly perform code modulation and code demodulation of power, and further, capable of simultaneously performing a plurality of power transmissions in a multiplexed manner via one transmission path. 
     Fourth Embodiment 
       FIG. 18  is a circuit diagram showing a configuration of a power transmission system according to a fourth embodiment. The power generator  1 , the code modulator  2 , the transmission path  3 , the code demodulator  4 , and the load  5  of  FIG. 18  are configured in a manner similar to that of the corresponding constituent elements of  FIG. 1 . The power generator  1  supplies DC generated current to the code modulator  2 . The load  5  is supplied with DC load current from the code demodulator  4 . In  FIG. 18 , the controller  10 , the power meters  1   m  and  5   m , and constituent elements of the code modulator  2  other than the switch elements S 1  to S 4 , and constituent elements of the code demodulator  4  other than the switch elements S 11  to S 14  of  FIG. 1  are omitted for ease of illustration. 
     The power transmission system of  FIG. 18  is further provided with: a first reactor L 1  connected between the code modulator  2  and the power generator  1 , and a second reactor L 2  connected between the code demodulator  4  and the load  5 . Due to the reactor L 1 , switching noise generated in the code modulation circuit  23  of the code modulator  2  is less likely to reach the power generator  1 . In addition, due to the reactor L 2 , switching noise generated in the code demodulation circuit  33  of the code demodulator  4  is less likely to reach the load  5 . In addition, due to the reactors L 1  and L 2 , it is possible to maintain continuity of current even when the switch elements S 1  to S 4  and S 11  to S 14  are turned on or off. Accordingly, it is possible to improve quality and safety of power transmission. 
     Usually, the switch elements S 1  to S 4  of the code modulator  2  are synchronized in time with the switch elements S 11  to S 14  of the code demodulator, such that the switch elements S 1  to S 4  and S 11  to S 14  are simultaneously turned on or off. However, it is difficult to maintain perfect time synchronization, and therefore, time delay and time advance may occur. In the case that the power transmission system is provided with the reactors L 1  and L 2 , if a delay occurs in turning on or off the switch elements S 1  to S 4  and S 11  to S 14 , then a period of no power transmission occurs, and therefore, the voltage can not arise at the code demodulator  4 . 
       FIG. 19  is a timing chart showing modulation codes m 1  and m 2  and demodulation codes d 1  and d 2  used in a power transmission system according to a comparison example of the fourth embodiment. In  FIG. 19 , (a) shows a case without delay, and (b) shows a case with delay. In  FIG. 19( b ) , the demodulation codes d 1  and d 2  are delayed from the modulation codes m 1  and m 2 . 
     For example, a delay occurs for the following reasons: 
     loss of synchronization between the code modulator  2  and the code demodulator  4 ; 
     delay in signal transmission among the code modulator  2 , the code demodulator  4 , and the controller  10 ; 
     delay in power transmission between the code modulator  2  and the code demodulator  4 ; and 
     mismatch in clock frequency between the code modulator  2  and the code demodulator  4 . 
       FIG. 20  is a diagram showing current flow with a delay in the power transmission system according to the comparison example of the fourth embodiment. If a delay occurs as shown in  FIG. 19( b ) , then power can not be supplied to the load  5 , since the switch elements S 11  and S 14  of the code demodulator  4  are turned off even when the switch elements S 2  and S 3  of the code modulator  2  are turned on. 
       FIG. 21  is a block diagram showing a configuration of a power transmission system according to an implementation example and a comparison example of the fourth embodiment. The power transmission system of  FIG. 21  is provided with: power generators  1 - 1  and  1 - 2 , code modulators  2 - 1  and  2 - 2 , the transmission path  3 , code demodulators  4 - 1  and  4 - 2 , loads  5 - 1  and  5 - 2 , and reactors L 1 - 1 , L 1 - 2 , L 2 - 1 , and L 2 - 2 . A simulation was performed for the power transmission system of  FIG. 21  under the following conditions. Each of the power generators  1 - 1  and  1 - 2  generated a DC voltage of 115 V. Each of the reactors L 1 - 1  and L 2 - 1  had an inductance of 10 mH, and each of the reactors L 1 - 2  and L 2 - 2  had an inductance of 100 mH. The load  5 - 1  had an impedance of 4.3Ω, and the load  5 - 2  had an impedance of 60Ω. The code modulators  2 - 1  and  2 - 2  and the code demodulators  4 - 1  and  4 - 2  operated at a modulation clock frequency of 20 kHz. The modulation clock frequency is a bit rate of a modulation code or a demodulation code. Each switch element of the code modulators  2 - 1  and  2 - 2  and the code demodulators  4 - 1  and  4 - 2  had a loss of 0.2Ω. The code modulator  2 - 1  transmits power to the code demodulator  4 - 1 , and the code modulator  2 - 2  transmits power to the code demodulator  4 - 2 . 
       FIG. 22  is a graph showing variations of load voltages Vout 1  and Vout 2  when power is transmitted without delay in the power transmission system according to the comparison example of the fourth embodiment.  FIG. 23  is a graph showing variations of the load voltages Vout 1  and Vout 2  when a delay occurs in the power transmission system according to the comparison example of the fourth embodiment. A simulation was performed for the power transmission system of  FIG. 21 . In the case of  FIG. 22 , both the pair of code modulator  2 - 1  and code demodulator  4 - 1 , and the pair of code modulator  2 - 2  and code demodulator  4 - 2  use the modulation code and the demodulation code shown in  FIG. 19( a ) . On the other hand, in the case of  FIG. 23 , the pair of code modulator  2 - 2  and code demodulator  4 - 2  use the modulation code and the demodulation code shown in  FIG. 19( a ) , but the pair of code modulator  2 - 1  and code demodulator  4 - 1  use the modulation code and the demodulation code shown in  FIG. 19( b ) . In the latter case, the demodulation codes d 1  and d 2  are delayed from the modulation codes m 1  and m 2  by 1% of the modulation clock cycle (time length corresponding to one bit of modulation code and demodulation code). 
     As can be seen from  FIGS. 22 and 23 , when a delay occurs between code modulator  2  and code demodulator  4  in the power transmission system provided with the reactors L 1  and L 2 , the load voltage can not arise, and power can not be transmitted. Power can not be transmitted when the demodulation codes d 1  and d 2  are delayed from the modulation codes m 1  and m 2  only by 1% of the modulation clock cycle. Accordingly, in order to transmit power, an impracticable requirement is imposed that the code modulator  2  and the code demodulator  4  are perfectly synchronized with each other. 
     Now, we describe an operation of the power transmission system according to the fourth embodiment, capable of preventing power transmission efficiency from degrading due to a delay. 
       FIG. 24  is a timing chart showing the modulation codes m 1  and m 2  and the demodulation codes d 1  and d 2  used in the power transmission system according to the fourth embodiment. 
     Referring to  FIG. 24 , the control circuit  20  of the code modulator  2  sets first to third states to the code modulation circuit  23 , the first to third states indicating different states of the switch elements S 1  to S 4  (switch circuits SS 1  to SS 4  of  FIG. 7 ). In the first state, the switch elements S 1  and S 4  are turned on, and the switch elements S 2  and S 3  are turned off (time period P 1 ). In the second state, the switch elements S 1  and S 4  are turned off, and the switch elements S 2  and S 3  are turned on (time period P 3 ). In the third state, all the switch elements S 1  to S 4  are turned on (time periods P 2 , P 4 ) during transition from the first state to the second state, and during transition from the second state to the first state. In the present specification, the third state is also referred to as a “simultaneous ON state” of the code modulator  2 . 
     In addition, referring to  FIG. 24 , the control circuit  30  of the code demodulator  4  sets fourth to sixth states to the code demodulation circuit  33 , the fourth to sixth states indicating different states of the switch elements S 11  to S 14  (switch circuits SS 11  to SS 14  of  FIG. 7 ). In the fourth state, the switch elements S 11  and S 14  are turned off, and the switch elements S 12  and S 13  are turned on (time period P 1 ). In the fifth state, the switch elements S 11  and S 14  are turned on, and the switch elements S 12  and S 13  are turned off (time period P 3 ). In the sixth state, all the switch elements S 11  to S 14  are turned on (time period P 2 , P 4 ) during transition from the fourth state to the fifth state, and during transition from the fifth state to the fourth state. In the present specification, the sixth state is also referred to as a “simultaneous ON state” of the code demodulator  4 . 
     Each of the third and sixth states (time period P 2 , P 4 ) has a predetermined time length. In the present specification, this time length is referred to as a “simultaneous ON time”. 
       FIG. 25  is a diagram showing current flow in the time period P 1  of  FIG. 24 . In the time period P 1 , the switch elements S 1  and S 4  of the code modulator  2  are turned on, and the switch elements S 12  and S 13  of the code demodulator  4  are turned on. Accordingly, current flows as shown in  FIG. 24 , and power is supplied to the load  5 . 
       FIG. 26  is a diagram showing current flow in each of the time periods P 2  and P 4  of  FIG. 24 . When the code modulation circuit  23  is in the third state, the ports T 1  and T 2  are short-circuited in the code modulator  2 , and a current flowing in the code modulator  2  returns from the port T 1  to the port T 2 . In this case, the switch elements S 1  to S 4  form a resistive power divider, and therefore, current flows through all paths in the code modulator  2 . However, since the current&#39;s energy is absorbed by the reactor L 1 , the switch elements S 1  to S 4  and the like on the current path are protected. In addition, since the code modulation circuit  23  is set to the third state for a very short time length with reference to the inductance of reactor L 1 , even when a current flow as shown in  FIG. 26 , the switch element S 1  to S 4  and the like on the current path are unlikely to be broken. Note that in practice, when the code modulation circuit  23  is in the third state, a part of the current in the code modulator  2  also flows to the transmission path  3 . This current can be ignored, since the amount of this current is smaller than the amount of the current returning from the port T 1  to the port T 2  through the resistive power divider made of the switch elements S 1  to S 4 , and smaller than the amount of energy absorbed by the reactor L 1 . Similarly, when the code demodulation circuit  33  is in the sixth state, the ports T 13  and T 14  are short-circuited in the code demodulator  4 , and a current flowing in the code demodulator  4  returns from the port T 13  to the port T 14 . 
       FIG. 27  is a diagram showing current flow in the time period P 3  of  FIG. 24 . In the time period P 3 , the switch elements S 2  and S 3  of the code modulator  2  are turned on, and the switch elements S 11  and S 14  of the code demodulator  4  are turned on. Accordingly, current flows as shown in  FIG. 27 , and power is supplied to the load  5 . 
       FIGS. 24 to 27  show power transmission without delay in the power transmission system. In the time period P 1  of  FIG. 24 , the code modulation circuit  23  is in the first state, and the code demodulation circuit  33  is in the fourth state ( FIG. 25 ). In the time periods P 2  and P 4  of  FIG. 24 , the code modulation circuit  23  is in the third state, and the code demodulation circuit  33  is in the sixth state ( FIG. 26 ). In the time period P 3  of  FIG. 24 , the code modulation circuit  23  is in the second state, and the code demodulation circuit  33  is in the fifth state ( FIG. 27 ). 
       FIG. 28  is a timing chart showing the modulation codes m 1  and m 2  and the demodulation codes d 1  and d 2  when a delay shorter than the simultaneous ON time occurs in the power transmission system according to the fourth embodiment. In the case of  FIG. 28 , the demodulation codes d 1  and d 2  are delayed from the modulation codes m 1  and m 2  by a time length shorter than the simultaneous ON time P 2 . In a time period P 2   a  of  FIG. 28 , the code modulation circuit  23  is in the third state (simultaneous ON state), and the code demodulation circuit  33  is in the fourth state. In a time period P 2   b  of  FIG. 28 , the code modulation circuit  23  is in the third state (simultaneous ON state), and the code demodulation circuit  33  is in the sixth state (simultaneous ON state). In a time period Plc of  FIG. 28 , the code modulation circuit  23  is in the second state, and the code demodulation circuit  33  is in the sixth state (simultaneous ON state). In addition, in a time period P 1 ′ of  FIG. 28 , the code modulation circuit  23  is in the first state, and the code demodulation circuit  33  is in the fourth state. In a time period P 3 ′ of  FIG. 28 , the code modulation circuit  23  is in the second state, and the code demodulation circuit  33  is in the fifth state. 
     Accordingly, in the time period P 2   a , only the code modulator  2  is in the simultaneous ON state. In the time period P 2   b , both the code modulator  2  and the code demodulator  4  are in the simultaneous ON state. In the time period P 2   c , only the code demodulator  4  is in the simultaneous ON state. 
       FIG. 29  is a diagram showing current flow in the time period P 2   a  of  FIG. 28 . A part of generated current is supplied to the load  5  via the transmission path  3 , and another part of the generated current returns from the port T 1  to the port T 2  in the code modulator  2 . 
     In the time period P 2   c , a current is supplied from the power generator  1  to the load  5  via the transmission path  3 , and a current flowing in the code demodulator  4  returns from the port T 13  to the port T 14 . 
     Accordingly, the currents flowing in the reactors L 1  and L 2  do not become zero in any of the time periods P 1 ′, P 2   a , P 2   b  (time period in which current flows as shown in  FIG. 26 ), P 2   c , and P 3 ′ of  FIG. 28 . 
     Power transmission does not stop, as long as the delay time of the demodulation codes d 1  and d 2  from the modulation codes m 1  and m 2  does not exceed the simultaneous ON time (time length of time period P 2 ). 
       FIG. 30  is a graph showing variations of the load voltages Vout 1  and Vout 2  when power is transmitted without delay in the power transmission system according to the implementation example of the fourth embodiment.  FIG. 31  is a graph showing variations of the load voltages Vout 1  and Vout 2  when a delay occurs in the power transmission system according to the implementation example of the fourth embodiment. A simulation was performed for the power transmission system of  FIG. 21 . In the cases of  FIGS. 30 and 31 , the simultaneous ON time of the code modulator  2  and the code demodulator  4  was set to 10% of the modulation clock cycle. In the case of  FIG. 30 , both the pair of code modulator  2 - 1  and code demodulator  4 - 1 , and the pair of code modulator  2 - 2  and code demodulator  4 - 2  use the modulation code and the demodulation code shown in  FIG. 24 . On the other hand, in the case of  FIG. 31 , the pair of code modulator  2 - 2  and code demodulator  4 - 2  use the modulation code and the demodulation code shown in  FIG. 24 , but the pair of code modulator  2 - 1  and code demodulator  4 - 1  use the modulation code and the demodulation code shown in  FIG. 28 . In the latter case, the demodulation codes d 1  and d 2  were delayed from the modulation codes m 1  and m 2  by a delay time corresponding to 10% of the modulation clock cycle, i.e., a delay time equal to or shorter than the simultaneous ON time. As shown in  FIGS. 30 and 31 , by introducing the simultaneous ON state to each of the code modulator  2  and the code demodulator  4 , no time period occurs in which the generated current and the load current become zero. Accordingly, power transmission is not stopped even when a delay occurs, as long as the delay time does not exceed the simultaneous ON time. 
     Now, we describe two methods for determining the time length of the simultaneous ON state time. 
     At first, we describe a first method for determining the time length of the simultaneous ON state. While we have described an exemplary case with the delay between the code modulator  2  and the code demodulator  4 , power transmission may be similarly stopped due to an advance in time. In addition to the delay between the code modulator  2  and the code demodulator  4 , power transmission may be similarly stopped due to a time difference (delay or advance) among operations of the switch elements S 1  to S 4  of the code modulator  2 , and due to a time difference (delay or advance) among operations of the switch element S 11  to S 14  of the code demodulator  4 . Here, Δt_Tx denotes the time difference (delay or advance) among operations of the switch elements S 1  to S 4  of the code modulator  2 . Δt_Rx denotes the time difference (delay or advance) among operations of the switch elements S 11  to S 14  of the code demodulator  4 . Δt_Tx−Rx denotes the time difference (delay or advance) among the code modulator  2  and the code demodulator  4 . These time differences indicate a delay or an advance from a reference time of the power transmission system. In this case, the simultaneous ON time is given as follows. 
     Simultaneous ON time≥Δt_Tx+Δt_Tx−Rx+Δt_Rx 
     Accordingly, the time length of the simultaneous ON state is set to be equal to or longer than the sum of: the time difference among operations of the switch elements S 1  to S 4  of the code modulator  2 ; the time difference between the code modulator  2  and the code demodulator  4 ; and the time difference among operations of the switch elements S 11  to S 14  of the code demodulator  4 . 
     Further, we consider a case where the power transmission system includes a plurality of code modulators  2 - i  (1≤i≤M) and a plurality of code demodulators  4 - j  (1≤j≤N). Δt_Txi denotes a time difference among operations of the switch elements S 1  to S 4  of the code modulator  2 - i . Δt_Rxj denotes a time difference among operations of the switch elements S 11  to S 14  of the code demodulator  4 - j . Δt_Txi−Rxj denotes a time difference between the code modulator  2 - i  and the code demodulator  4 - j . In this case, the simultaneous ON time is given as follows.
 
Simultaneous ON time≥max(Δ t _ Txi+Δt _ Txi−Rxj+Δt _ Rxj )
 
     In this case, a maximum of the right side is calculated for varying “i” and “j”. 
     Accordingly, the time length of the simultaneous ON state is set to be equal to or longer than the sum of: a maximum of the time differences each among operations of the switch elements S 1  to S 4  of each one of the code modulators  2 ; a maximum of the time differences each between one of the code modulators and one of the code demodulators; and a maximum of the time differences each among operations of the switch elements S 11  to S 14  of each one of the code demodulators  4 . 
     Next, with reference to  FIGS. 32 to 34 , we describe a second method for determining the time length of the simultaneous ON state. 
       FIG. 32  is an equivalent circuit diagram when the power transmission system according to the fourth embodiment is in the state as shown in  FIG. 25  or  FIG. 27 .  FIG. 33  is an equivalent circuit diagram when the power transmission system according to the fourth embodiment is in the state as shown in  FIG. 26 .  FIG. 34  is a schematic diagram showing variations of output voltage when time periods of  FIGS. 32 and 33  are alternated. 
     In general, in a circuit including a reactor having an inductance value L, a change of current Δi and a change of output voltage ΔVo for a time period Δt are given as follows.
 
Change of Current: Δ i= 1/ L×Δv×Δt  
 
Change of output voltage: Δ Vo=Z×Δi=Z×Δv×Δt/L  
 
     Where Δv denotes a change of voltage of the reactor for an infinitesimal time Δt, and Z denotes an impedance of the load  5 . 
     In the case of  FIG. 32 , a change of the load voltage ΔVo_ 1  in a time period Δt_ 1  is proportional to Δt_ 1 /(L 1 +L 2 ). In the case of  FIG. 33 , a change of the load voltage ΔVo_ 2  in a time period Δt_ 2  is proportional to Δt_ 2 /L 2 . Here, the time period Δt_ 2  denotes the simultaneous ON time of the code demodulator  4 , and the time period Δt_ 1  denotes a time length remaining after subtracting the simultaneous ON time from the modulation clock cycle of the code demodulator  4 . Since ΔVo_ 1 &gt;ΔVo_ 2  always holds, the following inequality is obtained.
 
Δ t _1/( L 1+ L 2)&gt;Δ t _2/ L 2
 
     This inequality is transformed as follows, as a condition on a time length of the simultaneous ON state.
 
Δ t _2/Δ t _1&lt; L 2/( L 1+ L 2)
 
     Accordingly, in the code demodulator  4 , a ratio of the time length of the sixth state to the total time length of the fourth and fifth states is set to be smaller than a ratio of the inductance of the second reactor to the sum of the inductances of the first and second reactors. 
       FIG. 35  is a timing chart showing the modulation codes m 1  and m 2  and the demodulation codes d 1  and d 2  when a delay longer than the simultaneous ON time occurs in the power transmission system according to the fourth embodiment. In the case of  FIG. 35 , the demodulation codes d 1  and d 2  are delayed from the modulation codes m 1  and m 2  by a time length longer than the simultaneous ON time P 2 . In this case, such a time period in which power can not be supplied from the power generator  1  to the load  5  occurs in a manner similar to that of  FIG. 19( b ) . In the time period P 2  of  FIG. 35 , the code modulation circuit  23  is in the third state (simultaneous ON state), and the code demodulation circuit  33  is in the fourth state. In a time period P 5  of  FIG. 35 , the code modulation circuit  23  is in the second state, and the code demodulation circuit  33  is in the fourth state. In a time period P 6  of  FIG. 35 , the code modulation circuit  23  is in the second state, and the code demodulation circuit  33  is in the sixth state (simultaneous ON state). In the time period P 5 , power can not be supplied to the load  5 , since the switch elements S 11  and S 14  of the code demodulator  4  are turned off even when the switch elements S 2  and S 3  of the code modulator  2  are turned on, as shown in  FIG. 20 . 
     According to the power transmission system of the fourth embodiment, by introducing the simultaneous ON state to each of the code modulator  2  and the code demodulator  4 , it is possible to prevent power transmission efficiency from degrading due to a delay between the code modulator  2  and the code demodulator  4 . 
     According to the power transmission system of the fourth embodiment, power transmission is not stopped even when a delay occurs, as long as the delay time does not exceed the simultaneous ON time. 
     If there is a time period in which all the switch elements are turned off in the code modulator  2  or the code demodulator  4 , then a surge may occur, and a noise may increase. According to the power transmission system of the fourth embodiment, since there is no time period in which all the switch elements are turned off, it is possible to improve safety of the code modulator  2  and the code demodulator  4 . 
     Fifth Embodiment 
     In the fourth embodiment, the simultaneous ON state is set to both the code modulator  2  and the code demodulator  4 . On the other hand, in the fifth embodiment, we describe a case where the simultaneous ON state is set to only the code modulator  2 . 
       FIG. 36  is a timing chart showing the modulation codes m 1  and m 2  and the demodulation codes d 1  and d 2  used in a power transmission system according to the fifth embodiment. In  FIG. 36 , (a) shows a case where a delay equal to or shorter than an allowable delay time occurs, and (b) shows a case where a delay longer than the allowable delay time occurs. The allowable delay time indicates, for example, a time difference among operations of the switch elements S 11  to S 14  of the code demodulator  4 . When the power transmission system includes a plurality of the code demodulators  4 , the allowable delay time indicates a maximum of time differences each among operations of the switch elements S 11  to S 14  of each one of the code demodulators  4 . A simultaneous ON time P 11  of the code modulator  2  is set to twice or more the allowable delay time. Power transmission is not stopped even when the demodulation codes d 1  and d 2  is delayed from the modulation codes m 1  and m 2 , as long as the delay time does not exceed the allowable delay time. 
       FIG. 37  is a graph showing variations of the load voltages Vout 1  and Vout 2  when a delay longer than the allowable delay time does not occur in a power transmission system according to an implementation example of the fifth embodiment.  FIG. 38  is a graph showing variations of the load voltages Vout 1  and Vout 2  when a delay longer than the allowable delay time does not occur in the power transmission system according to the implementation example of the fifth embodiment.  FIG. 39  is a graph showing variations of the load voltages Vout 1  and Vout 2  when a delay longer than the allowable delay time occurs in the power transmission system according to the implementation example of the fifth embodiment.  FIG. 40  is a graph showing variations of the load voltages Vout 1  and Vout 2  when a delay longer than the allowable delay time occurs in the power transmission system according to the implementation example of the fifth embodiment. A simulation was performed for the power transmission system of  FIG. 21 . In the cases of  FIGS. 37 to 40 , the simultaneous ON time of the code modulator  2  was set to 10% of the modulation clock cycle. 
     In the case of  FIG. 37 , in both the pair of code modulator  2 - 1  and code demodulator  4 - 1 , and the pair of code modulator  2 - 2  and code demodulator  4 - 2 , the demodulation codes d 1  and d 2  were delayed from the modulation codes m 1  and m 2  by 1% of the modulation clock cycle. 
     In the case of  FIG. 38 , in the pair of code modulator  2 - 1  and code demodulator  4 - 1 , the demodulation codes d 1  and d 2  were delayed from the modulation codes m 1  and m 2  by 5% of the modulation clock cycle; and in the pair of code modulator  2 - 2  and code demodulator  4 - 2 , the demodulation codes d 1  and d 2  were synchronized with the modulation codes m 1  and m 2 . 
     In the case of  FIG. 39 , in the pair of code modulator  2 - 1  and code demodulator  4 - 1 , the demodulation codes d 1  and d 2  were delayed from the modulation codes m 1  and m 2  by 6% of the modulation clock cycle; and in the pair of code modulator  2 - 2  and code demodulator  4 - 2 , the demodulation codes d 1  and d 2  were synchronized with the modulation codes m 1  and m 2 . 
     In the case of  FIG. 40 , in the pair of code modulator  2 - 1  and code demodulator  4 - 1 , the demodulation codes d 1  and d 2  were delayed from the modulation codes m 1  and m 2  by 10% of the modulation clock cycle; and in the pair of code modulator  2 - 2  and code demodulator  4 - 2 , the demodulation codes d 1  and d 2  were synchronized with the modulation codes m 1  and m 2 . 
     As shown in  FIGS. 37 to 40 , by introducing the simultaneous ON state to the code modulator  2 , power transmission is not stopped even when a delay occurs, as long as the delay time does not exceed the allowable delay time. 
     The time length of the simultaneous ON state of the code modulator  2  is set to twice or more the delay time of the code demodulator  4 . When the power transmission system includes a plurality of the code demodulators  4 , the time length of the simultaneous ON state of the code modulator  2  is set to twice or more a maximum of the delay times of the code demodulators  4 . 
       FIG. 41  is a timing chart showing the modulation codes m 1  and m 2  and the demodulation codes d 1  and d 2  used in a power transmission system according to a comparison example of the fifth embodiment. According to the fifth embodiment, power can not be transmitted when all the switch elements S 11  to S 14  of the code demodulator  4  are turned off for any time period P 12  due to desynchronization of the demodulation codes d 1  and d 2  or other reasons. 
     According to the power transmission system of the fifth embodiment, by introducing the simultaneous ON state of the code modulator  2 , it is possible to prevent power transmission efficiency from degrading due to a delay between the code modulator  2  and the code demodulator  4 . 
     Sixth Embodiment 
     In the fifth embodiment, the simultaneous ON state is set to only the code modulator  2 . On the other hand, in a sixth embodiment, we describe a case where the simultaneous ON state is set to only the code demodulator  4 . 
       FIG. 42  is a timing chart showing the modulation codes m 1  and m 2  and the demodulation codes d 1  and d 2  used in a power transmission system according to the sixth embodiment. In  FIG. 42 , (a) shows a case where a delay equal to an allowable delay time occurs, and (b) shows a case where a delay shorter than the allowable delay time occurs. The allowable delay time indicates, for example, a time difference among operations of the switch elements S 1  to S 4  of the code modulator  2 . When the power transmission system includes a plurality of the code modulators  2 , the allowable delay time indicates a maximum of time differences each among operations of the switch elements S 1  to S 4  of each one of the code modulators  2 . A simultaneous ON time P 21  of the code modulator  2  is set to twice or more the allowable delay time. Power transmission is not stopped even when the demodulation codes d 1  and d 2  is delayed from the modulation codes m 1  and m 2 , as long as the delay time does not exceed the allowable delay time. 
       FIG. 43  is a graph showing variations of the load voltages Vout 1  and Vout 2  when a delay longer than the allowable delay time does not occur in a power transmission system according to an implementation example of the sixth embodiment. A simulation was performed for the power transmission system of  FIG. 21 . In the case of  FIG. 43 , the simultaneous ON time of the code demodulator  4  was set to 10% of the modulation clock cycle. In the case of  FIG. 43 , in the pair of code modulator  2 - 1  and code demodulator  4 - 1 , the demodulation codes d 1  and d 2  were delayed from the modulation codes m 1  and m 2  by 1% of the modulation clock cycle; and in the pair of code modulator  2 - 2  and code demodulator  4 - 2 , the demodulation codes d 1  and d 2  were synchronized with the modulation codes m 1  and m 2 . As shown in  FIG. 43 , by introducing the simultaneous ON state to the code demodulator  4 , power transmission is not stopped even a delay occurs, as long as the delay time does not exceed the allowable delay time. 
     The time length of the simultaneous ON state of the code demodulator  4  is set to twice or more the delay time of the code modulator  2 . When the power transmission system includes a plurality of the code modulators  2 , the time length of the simultaneous ON state of the code demodulator  4  is set to twice or more a maximum of the delay times of the code modulators  2 . 
     According to the power transmission system of the sixth embodiment, by introducing the simultaneous ON state to the code demodulator  4 , it is possible to prevent power transmission efficiency from degrading due to a delay between the code modulator  2  and the code demodulator  4 . 
     In the fourth to sixth embodiments, we have described the power transmission system similar to the first embodiment, including the DC power supply and the DC load. The present disclosure is also applicable to a power transmission system similar to the second embodiment, including an AC power supply and an AC load. In the code modulator  2 A provided with the code modulation circuit  23 A of  FIG. 10 , the control circuit  20  sets first to third states to the code modulation circuit  23 A, the first to third states indicating different states of switch circuits SS 21  to SS 24 . In the first state, the switch circuits SS 21  and SS 24  are turned on, and the second and third switch circuits SS 22  and SS 23  are turned off. In the second state, the switch circuits SS 21  and SS 24  are turned off, and the switch circuits SS 22  and SS 23  are turned on. In the third state, all the switch circuits SS 21  to SS 24  are turned on during transition from the first state to the second state, and during transition from the second state to the first state. In the decode modulator  4 A provided with the code demodulation circuit  33 A of  FIG. 11 , the control circuit  30  sets fourth to sixth states to the code demodulation circuit  33 A, the fourth to sixth states indicating different states of switch circuits SS 31  to SS 34 . In the fourth state, the switch circuits SS 31  and SS 34  are turned off, and the switch circuits SS 32  and SS 33  are turned on. In the fifth state, the switch circuits SS 31  and SS 34  are turned on, and the switch circuits SS 32  and SS 33  are turned off. In the sixth state, all the switch circuits SS 31  to SS 34  are turned on during transition from the fourth state to the fifth state, and during transition from the fifth state to the fourth state. 
     In the fourth to sixth embodiments, the code modulator  2 , the code demodulator  4 , and the controller  10  are synchronized with each other in some manner before starting power transmission. Next, we describe an operation of the power transmission system according to the fourth to sixth embodiments, including transmitting and receiving control signals for preparation for power transmission, in particular, for synchronization of the code modulator  2  and the code demodulator  4 . 
     Each of Patent Documents 1 to 3 describes time synchronization of an entire power transmission system. However, in order to transmit power modulated by code modulation, it is necessary not only to synchronize in time the entire power transmission system, but also to synchronize demodulation of the code demodulator  4  with the phase of received power, in consideration of the travel time from the code modulator  2  to the code demodulator  4 . If the demodulation of the code demodulator  4  is not synchronized with the phase of the received power, the a loss occurs during demodulation of the received power. According to the power transmission system of  FIG. 1 , the phase is synchronized by means of communication between the power line communication circuit  24  of the code demodulator  4  and the power line communication circuit  34  of the code demodulator  4 . 
     According to the power transmission system of  FIG. 1 , power is generated by the power generator  1 , the generated power is modulated by the code modulator  2 , the modulated power is transmitted to the code demodulator  4  via the transmission path  3  and demodulated by the code demodulator  4 , and then, the demodulated power is supplied to the load  5 . Now, we describe an exemplary case of phase synchronization of the code demodulator  4 , in which the transmission path  3  between the code modulator  2  and the code demodulator  4  has a path length L 1 , and it takes a travel time of Δt 1  to transmit power modulated by the code modulator  2  via the transmission path  3 . In this case, by delaying a start time of demodulation of the code demodulator  4  from a start time of modulation of the code demodulator  4  by Δt 1  seconds, it is possible to start demodulation just at a time when modulated power having transmitted over the transmission path  3  arrives at the code demodulator  4 , and thus, it is possible to demodulate power in an efficient manner. As described above, in the power transmission system of  FIG. 1 , it is important to surely synchronize the demodulation of the code demodulator  4  with the phase of received power. 
       FIG. 44  is a sequence diagram showing a process of synchronizing the controller  10 , the code modulator  2 , and the code demodulator  4  in the power transmission system according to each of the fourth to sixth embodiments. In this case, control signals for establishing synchronization are transmitted from the code modulator  2  to the code demodulator  4  via the transmission path  3 . Each of the code modulator  2  and the code demodulator  4  may be provided with a power line communication circuit in order to transmit and receive the control signals. The control signals are transmitted from the power line communication circuit of the code modulator  2 , and received by the power line communication circuit of the code demodulator  4  via the transmission path  3 . The code demodulator  4  receives the control signals from the code modulator  2  via the transmission path  3  to measure a travel time Δt 1  from the code modulator  2  to the code demodulator  4  via the transmission path  3 . 
     Specifically, for example, the controller  10  transmits a system synchronization signal as a reference signal for synchronization of the entire power transmission system, so that operations of the code modulator  2  and the code demodulator  4  are synchronized in advance with operation of the controller  10 . Thus, operations of the code modulator  2  and the code demodulator  4  are synchronized in time with each other at a system synchronization time t 0 . The code modulator  2  transmits a beacon to the code demodulator  4  as a control signal for synchronizing demodulation of the code demodulator  4  with the phase of received power. The beacon includes information indicating a time when transmitting the beacon with reference to the system synchronization time t 0  (or information indicating a time length Δτ 0  from system synchronization time t 0  to the time when transmitting the beacon). The code demodulator  4  receives the beacon, and determines a time when receiving the beacon with reference to the system synchronization time t 0  (or a time length ΔΣ 1  from system synchronization time t 0  to the time when receiving the beacon). The code demodulator  4  obtains the travel time Δt 1  in the transmission path  3 : Δt 1 =Δτ 1 −Δt 0 . The control circuit  30  of the code demodulator  4  delays a start time of demodulation of the code demodulation circuit  33  from a start time of modulation of the code modulation circuit  23  (i.e., start time of power transmission) by the travel time Δt 1 . When receiving power from the code modulator  2  via the transmission path  3 , the code demodulator  4  demodulates the power in synchronization with the phase of the power based on the travel time Δt 1 . Thus, it is possible to efficiently demodulate the power in synchronization with the phase of the power received from the code modulator  2 . 
     Note that the system synchronization signal is not limited to the signal transmitted from the controller  10 , but may be a signal transmitted from other signal sources, such as a global positioning system (GPS) signal, or a standard time radio signal (radio-controlled clock). Thus, there is an advantageous effect of more accurate synchronization of the entire power transmission system. Furthermore, since it is not necessary for the controller  10  to transmit the system synchronization signal, there is an advantageous effect of reducing cost of the controller  10 . 
     Note that when a delay occurs for mismatch in clock frequency between the code modulator  2  and the code demodulator  4  as described above, the code modulator  2  and the code demodulator  4  may regularly correct their clock frequencies (frequency synchronization) For example, the clock frequencies of the code modulator  2  and the code demodulator  4  may be corrected by regularly transmitting a reference clock signal from the controller  10  to the code modulator  2  and the code demodulator  4 . 
     Seventh Embodiment 
     According to the power transmission systems of the fourth to sixth embodiments, when the code modulator  2  and the code demodulator  4  are in the simultaneous ON state (third and sixth states), a steep current peak occurs as follows. 
     
       
         
           
             
               
                 
                   
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                     E 
                     
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                             e 
                             
                               
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                                   R 
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                     Mathematical 
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     Where “E” denotes an input voltage of each of the code modulator  2  and the code demodulator  4 , “L” denotes an inductance of each of the reactors L 1  and L 2 , and “R” denotes an internal resistance of each of the switch elements S 1  to S 4  and S 11  to S 14 . 
     At a moment of transitioning from the simultaneous ON state to the other states (first, second, fourth, and fifth states) by turning off any one of the switch elements, a steep voltage peak occurs in the switch element due to energy accumulated in the reactors L 1  and L 2 . When high frequency noise including such voltage peaks occurs, the following problems may occur: 
     breakage of switch elements or the like of code modulator  2  and code demodulator  4  due to overvoltage; 
     malfunction of code modulator  2  and code demodulator  4 ; and 
     propagation of high frequency noise to power supply, load, or other apparatuses connected via transmission path  3 . 
     On the other hand, according to a seventh embodiment, a power transmission system capable of reducing effects of high frequency noise is provided. 
       FIG. 45  is a circuit diagram showing a configuration of a power transmission system according to the seventh embodiment. According to the power transmission system of  FIG. 45 , the power generator  1 , the code modulator  2 , the transmission path  3 , the code demodulator  4 , the load  5 , and the reactors L 1  and L 2  are configured in a manner similar to that of the corresponding constituent elements of  FIG. 18 . In  FIG. 45 , the controller  10 , the power meters  1   m  and  5   m , constituent elements of the code modulator  2  other than the switch elements S 1  to S 4 , and constituent elements of the code demodulator  4  other than the switch elements S 11  to S 14  of  FIG. 1  are omitted for ease of illustration. 
     According to the power transmission system of  FIG. 45 , the code modulator  2  may be further provided with a first filter circuit  41  connected between the ports T 1  and T 2 , and a second filter circuit  42  connected between the ports T 3  and T 4 . In addition, the code modulator  2  may be further provided with third filter circuits  45   a  to  45   d  connected in parallel to the switch elements S 1  to S 4  as shown in  FIGS. 46 to 49 . The code demodulator  4  may be further provided with a fourth filter circuit  43  connected between the ports T 11  and T 12 , and a fifth filter circuit  44  connected between the ports T 13  and T 14 . In addition, the code demodulator  4  may be further provided with sixth filter circuits  45   a  to  45   d  connected in parallel to the switch elements S 11  to S 14  as shown in  FIGS. 46 to 49 . 
       FIG. 46  is a circuit diagram showing filter circuits  45   a  and  45   b  used in the power transmission system of  FIG. 45 . When each of the switch elements S 1  to S 4  and S 11  to S 14  is provided with a diode D 101  and a switch element S 101  connected in series with each other, the filter circuits  45   a  and  45   b  may be connected in parallel to the diode D 101  and the switch element S 101 , respectively, as shown in  FIG. 46 . 
       FIG. 47  is a circuit diagram showing a filter circuit  45   c  used in the power transmission system of  FIG. 45 . When each of the switch elements S 1  to S 4  and S 11  to S 14  is provided with the diode D 101  and the switch element S 101  connected in series with each other, the one filter circuit  45   c  may be connected in parallel to the diode D 101  and the switch element S 101  as shown in  FIG. 47 . 
       FIG. 48  is a circuit diagram showing the filter circuit  45   d  used in the power transmission system of  FIG. 45 . A switch circuit SS 110  of  FIG. 48  is provided with diodes D 111  and D 112  and switch elements S 111  and S 112 , and is configured in a manner similar to that of the switch circuits SS 21 A to SS 24 A of  FIGS. 13A to 13D . When the seventh embodiment is applied to the power transmission system according to the second embodiment, the one filter circuit  45   d  may be connected in parallel to the diode D 111  and the switch element S 111 , and the further filter circuit  45   d  may be connected in parallel to the diode D 112  and the switch element S 112 . 
       FIG. 49  is a circuit diagram showing the filter circuit  45   d  used in the power transmission system of  FIG. 45 . A switch circuit SS 120  of  FIG. 49  is provided with diodes D 121  and D 122  and switch elements S 121  and S 122 , and is configured in a manner similar to that of the switch circuits SS 31 A to SS 34 A of  FIGS. 14A to 14D . When the seventh embodiment is applied to the power transmission system according to the second embodiment, the one filter circuit  45   d  may be connected in parallel to the diode D 121  and the switch element S 121 , and the further filter circuit  45   d  may be connected in parallel to the diode D 122  and the switch element S 122 . 
     The code modulator  2  may be provided with at least one of the first filter circuit  41 , the second filter circuit  42 , and the third filter circuits  45   a  to  45   d . The code demodulator  4  may be provided with at least one of the fourth filter circuit  43 , the fifth filter circuit  44 , and the sixth filter circuits  45   a  to  45   d.    
     The filter circuit  41  is connected between the code modulator  2  and the reactor L 1 . Similarly, the filter circuit  44  is connected between the code demodulator  4  and the reactor L 2 . The filter circuits  41  and  44  disposed at these positions can most effectively reduce a surge due to the reactors L 1  and L 2 , using a small number of parts. The filter circuits  41  and  44  may be designed in consideration of the inductance of the reactors L 1  and L 2 . 
     The filter circuits  42  and  43  are connected to both ends of the transmission path  3 . The filter circuits  42  and  43  disposed at these positions can most effectively reduce a surge mainly due to wiring inductance of the transmission path  3 , using a small number of parts. The filter circuits  42  and  43  may be designed in consideration of the wiring inductance of the transmission path  3 . 
     Since the inductance of the reactors L 1  and L 2  is much larger than the wiring inductance of the transmission path  3 , the filter circuits  41  and  44  are more effective than the filter circuits  42  and  43 . 
     The filter circuits  45   a  to  45   d  are connected in parallel to the switch elements S 1  to S 4  and S 11  to S 14 . The filter circuits  41  and  44  disposed at these positions can effectively reduce both the surge due to the reactors L 1  and L 2 , and the surge mainly due to the wiring inductance of the transmission path  3 . 
     The filter circuits  41  to  44  may be provided alone or in combination. The filter circuits  45   a  and  45   b  of  FIG. 46  are always used in combination. When regenerative current of a motor is used as a power source, for example, a combination of the filters  41  and  42  are effective. 
     Although  FIG. 45  shows a capacitor Ca 1  connected in parallel to the power generator  1  and a capacitor Ca 2  connected in parallel to the load  5 , the capacitors Ca 1  and Ca 2  may be removed as necessary. 
     Next, we describe examples of the filter circuits  41  to  45   d  with reference to  FIGS. 50 to 56 . 
       FIG. 50  is a circuit diagram showing a first example of the filter circuits  41  to  45   d  of  FIGS. 45 to 49 . The filter circuit of  FIG. 50  is provided with a snubber circuit, including a resistor R 201  and a capacitor C 201  connected in series with each other. In the filter circuit of  FIG. 50 , the capacitor C 201  is charged with a steep current which may result in a surge voltage. The current also flows in the resistor R 201  while charging and discharging the capacitor C 201 , and therefore, energy which may result in a surge voltage is consumed. However, in the filter circuit of  FIG. 50 , a large loss occurs at the resistor R 201 . 
       FIG. 51  is a circuit diagram showing a second example of the filter circuits  41  to  45   d  of  FIGS. 45 to 49 . The filter circuit of  FIG. 51  is provided with the resistor R 201  and the capacitor C 201  of  FIG. 50 , and further provided with a diode D 201  connected in parallel to the resistor R 201 . Also in the filter circuit of  FIG. 51 , the capacitor C 201  is charged with a steep current which may resulting in a surge voltage. The current flows in the diode D 201  of a low loss type while charging the capacitor C 201 , and therefore, the filter circuit of  FIG. 51  is more effective than a snubber circuit including only the resistor R 201  and the capacitor C 201 . 
       FIG. 52  is a circuit diagram showing a third example of the filter circuits  41  to  45   d  of  FIGS. 45 to 49 . The filter circuit of  FIG. 52  is provided with a Zener diode ZD. The filter circuit of  FIG. 52  utilizes reverse characteristics of a Zener diode. Forward characteristics of a Zener diode are similar to characteristics of a normal PN junction diode. However, when a reverse voltage is applied to a Zener diode, a constant voltage is maintained regardless of the current flowing therein. A surge voltage can be reduced by connecting the Zener diode ZD such that a surge voltage is applied in the reverse direction of the Zener diode ZD. 
       FIG. 53  is a circuit diagram showing a fourth example of the filter circuits  41  to  45   d  of  FIGS. 45 to 49 . The filter circuit of  FIG. 53  is provided with a snubber circuit including resistors R 211  and R 212  and a capacitor C 211 , and further provided with a diode bridge circuit including diodes D 211  to D 214 . In the filter circuit of  FIG. 53 , the capacitor C 211  is charged with a steep current which may results in a surge voltage. The diode bridge circuit limits charge and discharge of the capacitor C 211 , and therefore, a resistive loss decreases. 
       FIG. 54  is a circuit diagram showing a fifth example of the filter circuits  41  to  45   d  of  FIGS. 45 to 49 . The filter circuit of  FIG. 54  is provided with the resistor R 201  and the capacitor C 201  of  FIG. 50 , and further provided with diodes D 221  and D 222  and switch elements S 221  and S 222  connected in parallel to the resistor R 201 . The diodes D 221  and D 222  are connected in directions opposite to each other. In the filter circuit of  FIG. 54 , the capacitor C 201  is charged with a steep current which may result in a surge voltage. When a positive voltage is applied across both ends of the snubber circuit, the switch element S 221  is turned on, and when a negative voltage is applied across both ends of the snubber circuit, the switch element S 222  is turned on. Thus, the diodes D 221  and D 222  limit charge and discharge of the capacitor C 201  regardless whether positive voltage or negative voltage is applied across both ends of the snubber circuit, and therefore, a resistive loss decreases. 
     When DC power is applied, any of the filter circuits shown in  FIGS. 50 to 54  can be used. On the other hand, when AC power is applied, since both positive and negative voltages are applied to the filter circuit, non-polarized filter circuits shown in  FIGS. 50, 53 and 54  are can be used. 
     Since a frequency of surge voltage is much higher than a frequency of modulated power, the filter circuit may be configured, including a low pass filter or a band pass filter for reducing high-frequency noise signal components. 
       FIG. 55  is a circuit diagram showing a sixth example of the filter circuits  41  to  45   d  of  FIGS. 45 to 49 . The filter circuit of  FIG. 55  is a low pass filter, including an inductor L 211  and a capacitor C 211 . The filter circuit of  FIG. 55  passes signals having frequencies lower than a cutoff frequency. 
       FIG. 56  is a circuit diagram showing a seventh example of the filter circuits  41  to  45   d  of  FIGS. 45 to 49 . The filter circuit of  FIG. 56  is a band pass filter, including an inductor L 221 , a capacitor C 221 , and a resistor R 221 . The filter circuit of  FIG. 56  passes signals in a specific frequency band. 
     Since each of the filter circuits of  FIG. 55  and  FIG. 56  are an LC resonant circuit, voltage oscillation is likely to occur. 
     The inductance of each of the filter circuits of  FIG. 55  and  FIG. 56  may be shared with an inductance of the reactors L 1  and L 2 , and/or wiring inductance of the transmission path  3 . 
       FIG. 57  is a circuit diagram showing a configuration of a power transmission system including filter circuits according to an eighth example of the seventh embodiment. The power transmission system of  FIG. 57  is provided with: a capacitor Ca 3  connected between the ports T 3  and T 4 ; and a capacitor Ca 4  connected between the ports T 11  and T 12 . The capacitor Ca 3 , the reactor L 1 , and the transmission path  3  make a filter circuit having a resonance frequency determined by the capacitance of the capacitor Ca 3 , the inductance of the reactor L 1 , and the wiring inductance of the transmission path  3 . Similarly, the capacitor Ca 4 , the reactor L 2 , and the transmission path  3  make a filter circuit having a resonant frequency determined by the capacitance of the capacitor Ca 4 , the inductance of the reactor L 2 , and the wiring inductance of the transmission path  3 . 
     In the power transmission system, the reactors L 1  and L 2  have designed and known inductances, and therefore, the filter circuit can be designed based on the value of their inductances. On the other hand, the transmission path  3  may have an unknown inductance. In particularly, in a power transmission system including a plurality of the code modulators  2  and a plurality of the code demodulators  4 , the path length of the transmission path  3  varies in accordance with a combination of the code modulator  2  and the code demodulator  4  between which power is transmitted, as a result, the transmission path  3  may have a variable inductance. Accordingly, it is difficult to design an effective filter using the capacitors Ca 3  and Ca 4  having fixed capacitances. 
       FIG. 58  is a block diagram showing a configuration of a power transmission system including filter circuits according to a ninth example of the seventh embodiment. With reference to  FIG. 58 , we describe a power transmission system provide with variable capacitors, in place of the capacitors Ca 3  and Ca 4  of  FIG. 57 . The power transmission system of  FIG. 58  is provided with: the power generator  1 , a code modulator  2 B, the transmission path  3 , a code demodulator  4 B, the load  5 , and a controller  10 B. The code modulator  2 B and the code demodulator  4 B are provided with variable capacitors, respectively, and set their capacitances under control of the controller  10 B. The controller  10 B is provided with a control circuit  11  and a communication circuit  12 B. The control circuit  11  communicates with the code modulator  2 B and the code demodulator  4 B via the communication circuit  12 B, and controls operations of the code modulator  2 B and the code demodulator  4 B. 
       FIG. 59  is a circuit diagram showing the configuration of the power transmission system including the filter circuits according to the ninth example of the seventh embodiment. The code modulator  2 B is provided with: a variable capacitor Ca 5  connected between the ports T 3  and T 4 ; a current meter  51 ; and a voltage meter  52 . The current meter  51  measures current outputted from the code modulator  2 B to the transmission path  3 . The voltage meter  52  measures voltage outputted from the code modulator  2  to the transmission path  3 . The code modulator  2 B transmits a current value measured by the current meter  51 , and a voltage value measured by the voltage meter  52 , to the controller  10 B, and sets the capacitance of the variable capacitor Ca 5  under control of the controller  10 B. The code demodulator  4 B is provided with: a variable capacitor Ca 6  connected between the ports T 11  and T 12 ; a voltage meter  53 ; and a current meter  54 . The voltage meter  53  measures voltage inputted from the transmission path  3  to the code demodulator  4 B. The current meter  54  measures current inputted from the transmission path  3  to the code demodulator  4 B. The code demodulator  4 B transmits a voltage value measured by the voltage meter  53 , and a current value measured by the current meter  54 , to the controller  10 B, and sets the capacitance of the variable capacitor Ca 6  under control of the controller  10 B. 
     The controller  10 B determines the capacitances of the variable capacitors Ca 5  and Ca 6  as follows. 
     Firstly, at a time “ta”, a voltage V 1  outputted from the code modulator  2 B to the transmission path  3  is measured, and a voltage V 2  inputted from the transmission path  3  to the code demodulator  4 B is measured. 
     For a certain duration from the time “ta” to a time “tb”, Δt=tb−ta, a change of current outputted from the code modulator  2 B to the transmission path  3 , ΔI 1 =I 1   b −I 1   a , or a change of current inputted from the transmission path  3  to the code demodulator  4 B, ΔI 2 =I 2   b −I 2   a , is measured. 
     A voltage applied to the wiring inductance value L of the transmission path  3 , V=V 2 −V 1 , is given as follows. 
     
       
         
           
             
               
                 
                   V 
                   = 
                   
                     
                       - 
                       L 
                     
                     ⁢ 
                     
                       
                         dI 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       dt 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Mathematical 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   ] 
                 
               
             
           
         
       
     
     The unknown inductance value L is calculated using this mathematical expression. 
     Based on a capacitance value C of the variable capacitors Ca 5  and Ca 6 , and the inductance value L, a cutoff frequency fc of the filter circuit is given as follows. 
     
       
         
           
             
               
                 
                   fc 
                   = 
                   
                     1 
                     
                       2 
                       ⁢ 
                       π 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         LC 
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Mathematical 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                   
                   ] 
                 
               
             
           
         
       
     
     The capacitance value C of the variable capacitors Ca 5  and Ca 6  is determined such that the cutoff frequency fc is higher than the frequency of the modulation code and the demodulation code. 
     Thus, it is possible to provide an appropriate filter circuit even when the transmission path  3  has an unknown inductance. 
     According to the power transmission system of the seventh embodiment, it is possible to prevent power transmission efficiency from degrading due to a delay between the code modulator  2  and the code demodulator  4 , and can reduce effects of high frequency noise by providing the filter circuit(s). 
     Eighth Embodiment 
     In an eighth embodiment, we describe reduction of switching losses of the code modulator  2  and the code demodulator  4  of the power transmission system according to the seventh embodiment, the power transmission system being provided with LC resonant circuits as filter circuits. 
     A power transmission system according to the eighth embodiment is configured in a manner similar to that of the power transmission systems of  FIGS. 57 to 59 . 
       FIG. 60  is a graph showing a relationship between a modulation code and a resonance waveform of the filter circuit in the power transmission system according to the eighth embodiment. The capacitances of the capacitors Ca 3  and Ca 4  are determined such that a half period of a resonance waveform determined by the inductances of the reactors L 1  and L 2  and the capacitances of the capacitors Ca 3  and Ca 4  matches one bit (modulation clock frequency) of the modulation code and the demodulation code. In this case, the switch elements are turned on or off at each moment when the drain-source voltage of the switch element is zero, and therefore, switching losses are considerably reduced. 
       FIG. 61  is a diagram illustrating resonance of the filter circuit in the power transmission system according to the eighth embodiment.  FIG. 62  is a diagram showing a relationship between output voltage of the code modulator  2  and input voltage of the code demodulator  4  when a resonance frequency of the filter circuit in the power transmission system according to the eighth embodiment is identical to a modulation clock frequency. As shown in  FIG. 61 , the impedance Z is considerably reduced at the resonance frequency of the filter circuit. Accordingly, as shown in  FIG. 62 , when the switch elements of the code modulator  2  or the code demodulator  4  operate at a frequency equal to the resonance frequency of the filter circuit, a sinusoidal output voltage is generated by a rectangular input voltage. 
     The resonance frequency of the power transmission system is determined by the total inductances and total capacitances in a current path including the code modulator  2 , the transmission path  3 , and the code demodulator  4 . The capacitor Ca 3  or Ca 4  having the capacitance value C is provided for the reactors L 1  and L 2  having very large inductances. In this case, the capacitance value C is determined such that nodes of the following resonance waveform (resonance frequency f res ) match with respective bits of the modulation code and the demodulation code in one-by-one basis. 
     
       
         
           
             
               
                 
                   
                     f 
                     res 
                   
                   = 
                   
                     1 
                     
                       2 
                       ⁢ 
                       π 
                       ⁢ 
                       
                         
                           
                             ( 
                             
                               
                                 L 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                               + 
                               
                                 L 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                             ) 
                           
                           × 
                           C 
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Mathematical 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     4 
                   
                   ] 
                 
               
             
           
         
       
     
     When f sw  is the modulation clock frequency, and N is any integer, the resonance frequency f res  is determined as follows. 
     
       
         
           
             
               
                 
                   
                     f 
                     res 
                   
                   = 
                   
                     
                       
                         f 
                         sw 
                       
                       2 
                     
                     × 
                     N 
                   
                 
               
               
                 
                   [ 
                   
                     Mathematical 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     5 
                   
                   ] 
                 
               
             
           
         
       
     
     In this case, the voltage is zero at moments of transition of the modulation code and the demodulation code. 
     Since each of the code modulator  2  and the code demodulator  4  may be provided with at least one capacitor, the capacitance of the capacitor Ca 3  or Ca 4  may be determined as follows. 
     
       
         
           
             
                 
             
             ⁢ 
             
               [ 
               
                 Mathematical 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 Expression 
                 ⁢ 
                 
                   
                       
                   
                   ⁢ 
                   
                       
                   
                 
                 ⁢ 
                 6 
               
               ] 
             
           
         
       
       
         
           
             
               f 
               res 
             
             = 
             
               1 
               
                 2 
                 ⁢ 
                 π 
                 ⁢ 
                 
                   
                     
                       ( 
                       
                         
                           L 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                         + 
                         
                           L 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                       ) 
                     
                     × 
                     
                       ( 
                       
                         
                           Ca 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           3 
                         
                         + 
                         
                           Ca 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           4 
                         
                       
                       ) 
                     
                   
                 
               
             
           
         
       
     
     Note that in actual design, since there are parasitic components of semiconductor devices, and wiring inductances of a substrate and the transmission path  3 , it is necessary to determine the capacitances in consideration of the parasitic components. 
     Thus, the resonant circuit including the reactors L 1  and L 2  and the capacitors Ca 3  and Ca 4  is configured to have a resonance frequency equal to N/2 times the modulation clock frequency, and thus, it is possible to reduce switching losses of the code modulator  2  and the code demodulator  4 . 
     Next, with reference to  FIGS. 63 to 73 , we describe simulation results of the power transmission system according to the seventh embodiment. 
     Simulations were performed for the power transmission systems according to the seventh and eighth embodiments, each including the one code modulator  2 A and the one code demodulator  4 A of the second embodiment. A DC voltage source of 115V was connected to the code modulator  2 A. The load  5  of 12Ω was connected to the code demodulator  4 A. The inductance of the reactors L 1  and L 2  was 15 mH. The modulation code and the demodulation code were Gold code sequences of seven stages, and their modulation clock frequency of these codes was 20 kHz. 
     At first, with reference to  FIGS. 63 to 65  we describe a simulation result of the power transmission system according to a first implementation example of the seventh embodiment.  FIG. 65  is a diagram showing how to measure current and voltage of  FIGS. 63 and 64 . 
       FIG. 63  shows a simulation result of a power transmission system according to a comparison example of the seventh embodiment. In  FIG. 63 , (a) is a graph showing gate voltage of switch elements S 1  and S 4 , (b) is a graph showing current flowing in the switch elements S 1  and S 4 , and (c) is a graph showing voltage across both ends of the switch elements S 1  and S 4 .  FIG. 63  shows current and voltage of the power transmission system without filter circuit. As can be seen from  FIG. 63( c ) , a large voltage peak occurs at moments when the switch elements S 1  and S 4  are turned off. 
       FIG. 64  shows a simulation result of a power transmission system according to the first implementation example of the seventh embodiment. In  FIG. 64 , (a) is a graph showing gate voltage of switch elements S 1  and S 4 , (b) is a graph showing current flowing in the switch elements S 1  and S 4 , and (c) is a graph showing voltage across both ends of the switch elements S 1  and S 4 .  FIG. 64  shows current and voltage of the power transmission system provided with: the capacitor Ca 3  connected between the ports T 3  and T 4 ; and the capacitor Ca 4  connected between the ports T 11  and T 12 . As can be seen from comparison between  FIG. 63( c )  and  FIG. 64( c ) , since the power transmission system according to the implementation example is provided with filter circuits, a sinusoidal voltage, instead of a rectangular voltage, is applied to each of the switch elements S 1  and S 4 , and a voltage peak at the moments of turning off of the switch elements S 1  and S 4  is significantly reduced. Accordingly, it is possible to reduce switching losses. 
     At first, with reference to  FIGS. 66 to 70 , we describe a simulation result of a power transmission system according to a second implementation example of the seventh embodiment.  FIG. 71  is a diagram showing how to measure voltage shown in  FIGS. 66 to 70 . 
       FIG. 66  is a graph showing a simulation result of the power transmission system according to the comparison example of the seventh embodiment, showing voltage applied to both ends of the diode D 101  of the switch circuit.  FIG. 67  is a graph showing an enlarged diagram of a part of  FIG. 66 .  FIG. 68  is a graph showing a simulation result of the power transmission system according to the comparison example of the seventh embodiment, showing voltage applied to both ends of the switch element S 101  of the switch circuit.  FIG. 69  is a graph showing an enlarged diagram of a part of  FIG. 68 . Each of  FIGS. 66 to 69  shows current and voltage of the power transmission system without filter circuit. As can be seen from  FIGS. 66 to 69 , large overvoltages are applied to both the diode D 101  and the switch element S 101 . 
       FIG. 70  shows a simulation result of the power transmission system according to the second implementation example of the seventh embodiment. In  FIG. 70 , (a) is a graph showing voltage applied to both the ends of the diode D 101  of the switch circuit, and (b) is a graph showing voltage applied to both the ends of the switch element S 101  of the switch circuit.  FIG. 70  shows voltage when the power transmission system is provided with the filter circuits  41  and  44 , each provided with a snubber circuit including a resistor of 20Ω and a capacitor of 22 μF connected in series with each other. 
     A following model was used for the simulation of  FIG. 70 . 
     
       
         
           
             
               
                 
                   
                     
                       i 
                       peak 
                     
                     ⁡ 
                     
                       ( 
                       t 
                       ) 
                     
                   
                   = 
                   
                     
                       E 
                       
                         R 
                         on 
                       
                     
                     ⁢ 
                     
                       ( 
                       
                         1 
                         - 
                         
                           e 
                           
                             
                               - 
                               
                                 
                                   R 
                                   on 
                                 
                                 L 
                               
                             
                             ⁢ 
                             t 
                           
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Mathematical 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     7 
                   
                   ] 
                 
               
             
             
               
                 
                   
                     i 
                     out 
                   
                   = 
                   
                     E 
                     
                       R 
                       out 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Mathematical 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     8 
                   
                   ] 
                 
               
             
             
               
                 
                   
                     C 
                     s 
                   
                   = 
                   
                     
                       
                         L 
                         ⁡ 
                         
                           ( 
                           
                             
                               i 
                               peak 
                             
                             + 
                             
                               i 
                               out 
                             
                           
                           ) 
                         
                       
                       2 
                     
                     
                       
                         ( 
                         
                           E 
                           - 
                           
                             V 
                             cap 
                           
                         
                         ) 
                       
                       2 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Mathematical 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     9 
                   
                   ] 
                 
               
             
             
               
                 
                   
                     
                       i 
                       s 
                     
                     ⁡ 
                     
                       ( 
                       t 
                       ) 
                     
                   
                   = 
                   
                     
                       E 
                       
                         R 
                         s 
                       
                     
                     ⁢ 
                     
                       e 
                       
                         
                           - 
                           
                             1 
                             
                               
                                 C 
                                 s 
                               
                               ⁢ 
                               
                                 R 
                                 s 
                               
                             
                           
                         
                         ⁢ 
                         t 
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Mathematical 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     10 
                   
                   ] 
                 
               
             
             
               
                 
                   
                     R 
                     s 
                   
                   ≤ 
                   
                     1 
                     
                       
                         C 
                         s 
                       
                       ⁢ 
                       
                         f 
                         sw 
                       
                       ⁢ 
                       ln 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       0.9 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Mathematical 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     Expression 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     11 
                   
                   ] 
                 
               
             
           
         
       
     
     Where the following notations are used: 
     i peak : inrush current flowing when code modulator  2  is in simultaneous ON state, 
     E: input voltage of code modulator  2 , 
     L: inductance of reactor L 1 , 
     R on : internal resistance of each switch element S 1  to S 4 , 
     i out : output current of code modulator  2 , 
     R out : impedance of load  5 , 
     C s : snubber capacitor, 
     V cap : clamp voltage of snubber capacitor, 
     i s : charge current to snubber capacitor, 
     R s : snubber resistance, and 
     f sw : switching frequency. 
     As can be seen from  FIG. 70 , since the filter circuits  41  and  44  are provided, the voltage applied to both ends of the diode D 101  decreased from −2500V to −115V, and the voltage applied to both ends of the switch element S 101  decreased from 25000V to 115V. By providing the filter circuits  41  and  44 , it is possible to considerably reduce surge voltages generated in the switch elements S 1  to S 4 . 
     Next, with reference to  FIGS. 72 to 73 , we describe a simulation result of a power transmission system according to an implementation example of the seventh embodiment. 
       FIG. 72  shows a simulation result of a power transmission system according to a third implementation example of the seventh embodiment. In  FIG. 72 , (a) is a graph showing voltage across both ends of the switch elements S 1  and S 4 , (b) is a graph showing gate voltage of the switch elements S 1  and S 4 , and (c) is a graph showing current flowing in the switch elements S 1  and S 4 .  FIG. 73  is a graph showing an enlarged diagram of a part of  FIG. 72 . As shown in  FIG. 73 , it is possible to measure a change of current outputted from the code modulator  2  to the transmission path  3 , ΔI 1 , for a certain duration Δt. Similarly, it is possible to measure a change of current inputted from the transmission path  3  to the code demodulator  4 , ΔI 2 , for the certain duration Δt. Thus, it is possible to calculate the wiring inductance of the transmission path  3  based on the waveform of the current, as described above. 
     Other Embodiments 
     In the third embodiment, a plurality of code modulators may use the same modulation code, and a plurality of code demodulators may use the same demodulation code. Thus, one code modulator may transmit powers to a plurality of code demodulators, a plurality of code modulators may transmit powers to one code demodulator, and a plurality of code modulators may transmit powers to a plurality of code demodulators. 
     In the first to eighth embodiments, we have indicated the example in which power is transmitted using code modulation and code demodulation of current, but the power transmission is not limited thereto. Power may be transmitted using code modulation and code demodulation of direct-current or alternating-current voltage. In this case, similar advantageous effects can be achieved. 
     A power transmitter apparatus, a power receiver apparatus, and a power transmission system according to several aspects of the present disclosure have following configurations. 
     According to a power transmitter apparatus of a first aspect, a power transmitter apparatus transmits power to at least one power receiver apparatus via a transmission path. The power transmitter apparatus is provided with: a code modulation circuit connected to a power supply via a first reactor and supplied with source power from the power supply, the code modulation circuit modulating the source power to generate a code-modulated wave by code modulation using a modulation code based on a code sequence, and transmitting the code-modulated wave to the power receiver apparatus via the transmission path; and a control circuit that controls the code modulation circuit. The code modulation circuit is provided with: first and second ports connected to the power supply via the first reactor, third and fourth ports connected to the transmission path, a first switch circuit connected between the first and third ports, a second switch circuit connected between the second and third ports, a third switch circuit connected between the first and fourth ports, and a fourth switch circuit connected between the second and fourth ports, The control circuit sets a first state to the code modulation circuit, the first state defined in which the first and fourth switch circuits are turned on, and the second and third switch circuits are turned off. The control circuit sets a second state to the code modulation circuit, the second state defined in which the first and fourth switch circuits are turned off, and the second and third switch circuits are turned on. The control circuit sets a third state to the code modulation circuit during transition from the first state to the second state, and during transition from the second state to the first state, the third state defined in which all the first to fourth switch circuits are turned on. 
     According to a power receiver apparatus of a second aspect, a power receiver apparatus receives a code-modulated wave from at least one power transmitter apparatus via a transmission path, the code-modulated wave including power modulated by code modulation using a modulation code based on a code sequence. The power receiver apparatus is provided with: a code demodulation circuit connected to a load via a second reactor, the code demodulation circuit demodulating the received code-modulated wave to generate demodulated power by code demodulation using a demodulation code based on a code sequence identical to the code sequence of the modulation code used for the code modulation, and supplying the demodulated power to the load; and a control circuit that controls the code demodulation circuit. The code demodulation circuit is provided with: fifth and sixth ports connected to the transmission path, seventh and eighth ports connected to the load via the second reactor, a fifth switch circuit connected between the sixth and seventh ports, a sixth switch circuit connected between the sixth and eight ports, a seventh switch circuit connected between the fifth and seventh ports, and an eighth switch circuit connected between the fifth and eighth ports. The control circuit sets a fourth state to the code demodulation circuit, the fourth state defined in which the fifth and eighth switch circuits are turned off, the sixth and seventh switch circuits are turned on. The control circuit sets a fifth state to the code demodulation circuit, the fifth state defined in which the fifth and eighth switch circuits are turned on, and the sixth and seventh switch circuits are turned off. The control circuit sets a sixth state to the code demodulation circuit during transition from the fourth state to the fifth state, and during transition from the fifth state to the fourth state, the sixth state defined in which all the fifth to eighth switch circuits are turned on. 
     According to a power transmission system of a third aspect, a power transmission system includes: at least one power transmitter apparatus of the first aspect; and at least one power receiver apparatus of the second aspect. 
     According to a power transmission system of a fourth aspect, in the power transmission system of the third aspect, a time length of each of the third and sixth states is set to equal to or longer than a sum of: a maximum of time differences each among operations of the switch circuits of each one of the at least one power transmitting apparatus; a maximum of time differences each between one of the at least one power transmitting apparatus and one of the at least one power receiving apparatus; and a maximum of time differences each among operations of the switch circuits of each one of the at least one power receiving apparatus. 
     According to a power transmission system of a fifth aspect, in the power transmission system of the third or fourth aspect, a ratio of a time length of the sixth state to a total time length of the fourth and fifth states is set to be smaller than a ratio of an inductance of the second reactor to a sum of inductances of the first and second reactors. 
     According to a power transmission system of a sixth aspect, A power transmission system includes: at least one power transmitter apparatus of the first aspect; and at least one power receiver apparatus. The power receiver apparatus receives the code-modulated wave from the power transmitter apparatus via the transmission path, demodulates the received code-modulated wave to generate demodulated power by code demodulation using a demodulation code based on a code sequence identical to the code sequence of the modulation code used for the code modulation, and supplies the demodulated power to the load. 
     According to a power transmission system of a seventh aspect, in the power transmission system of the sixth aspect, the time length of the third state is set to twice or more a maximum of time differences each among operations of the switch circuits of each one of the at least one power receiving apparatus. 
     According to a power transmission system of an eighth aspect, A power transmission system includes: at least one power transmitter apparatus; and at least one power receiver apparatus as of the second aspect. The power transmitter apparatus modulates power to generate a code-modulated wave by code modulation using a modulation code based on a code sequence, and transmits the code-modulated wave to the power receiver apparatus via the transmission path. 
     According to a power transmission system of a ninth aspect, in the power transmission system of the eighth aspect, the time length of the sixth state is set to twice or more a maximum of time differences each among operations of the switch circuits of each one of the at least one power transmitting apparatus. 
     According to a power transmitter apparatus of a 10th aspect, a power transmitter apparatus transmits power to at least one power receiver apparatus via a transmission path. The power transmitter apparatus is provided with: a code modulation circuit connected to a power supply via a first reactor and supplied with source power from the power supply, the code modulation circuit modulating the source power to generate a code-modulated wave by code modulation using a modulation code based on a code sequence, and transmitting the code-modulated wave to the power receiver apparatus via the transmission path; and a control circuit that controls the code modulation circuit. The code modulation circuit is provided with: first and second ports connected to the power supply via the first reactor, third and fourth ports connected to the transmission path, a first switch circuit connected between the first and third ports, a second switch circuit connected between the second and third ports, a third switch circuit connected between the first and fourth ports, and a fourth switch circuit connected between the second and fourth ports, The control circuit sets a first state to the code modulation circuit, the first state defined in which the first and fourth switch circuits are turned on, and the second and third switch circuits are turned off. The control circuit sets a second state to the code modulation circuit, the second state defined in which the first and fourth switch circuits are turned off, and the second and third switch circuits are turned on. The control circuit sets a third state to the code modulation circuit during transition from the first state to the second state, and during transition from the second state to the first state, the third state defined in which all the first to fourth switch circuits are turned on. The power transmitter apparatus is further provided with at least one of: a first filter circuit connected between the first and second ports, a second filter circuit connected between the third and fourth ports, and a third filter circuit connected in parallel to each of the first to fourth switch circuits. 
     According to a power transmitter apparatus of an 11th aspect, in the power transmitter apparatus of the 10th aspect, the filter circuit is provided with a snubber circuit including a resistor and a capacitor connected in series with each other. 
     According to a power transmitter apparatus of a 12th aspect, in the power transmitter apparatus of the 11th aspect, the filter circuit is further provided with a diode connected in parallel to the resistor. 
     According to a power transmitter apparatus of a 13th aspect, in the power transmitter apparatus of the 11th aspect, the filter circuit is further provided with a diode bridge circuit. 
     According to a power transmitter apparatus of a 14th aspect, in the power transmitter apparatus of the 10th aspect, the filter circuit is provided with a Zener diode. 
     According to a power transmitter apparatus of a 15th aspect, in the power transmitter apparatus of the 10th aspect, the filter circuit is a low pass filter including an inductor and a capacitor. 
     According to a power transmitter apparatus of a 16th aspect, in the power transmitter apparatus of the 10th aspect, the filter circuit is a band pass filter including an inductor, a capacitor, and a resistor. 
     According to a power receiver apparatus of a 17th aspect, a power receiver apparatus receives a code-modulated wave from at least one power transmitter apparatus via a transmission path, the code-modulated wave including power modulated by code modulation using a modulation code based on a code sequence. The power receiver apparatus is provided with: a code demodulation circuit connected to a load via a second reactor, the code demodulation circuit demodulating the received code-modulated wave to generate demodulated power by code demodulation using a demodulation code based on a code sequence identical to the code sequence of the modulation code used for the code modulation, and supplying the demodulated power to the load; and a control circuit that controls the code demodulation circuit. The code demodulation circuit is provided with: fifth and sixth ports connected to the transmission path, seventh and eighth ports connected to the load via the second reactor, a fifth switch circuit connected between the sixth and seventh ports, a sixth switch circuit connected between the sixth and eight ports, a seventh switch circuit connected between the fifth and seventh ports, and an eighth switch circuit connected between the fifth and eighth ports. The control circuit sets a fourth state to the code demodulation circuit, the fourth state defined in which the fifth and eighth switch circuits are turned off, the sixth and seventh switch circuits are turned on. The control circuit sets a fifth state to the code demodulation circuit, the fifth state defined in which the fifth and eighth switch circuits are turned on, and the sixth and seventh switch circuits are turned off. The control circuit sets a sixth state to the code demodulation circuit during transition from the fourth state to the fifth state, and during transition from the fifth state to the fourth state, the sixth state defined in which all the fifth to eighth switch circuits are turned on. The power receiver apparatus is further provided with at least one of: a fourth filter circuit connected between the fifth and sixth ports, a fifth filter circuit connected between the seventh and eighth ports, and a sixth filter circuit connected in parallel to each of the fifth to eighth switch circuits. 
     According to a power receiver apparatus of an 18th aspect, in the power receiver apparatus of the 17th aspect, the filter circuit is provided with a snubber circuit including a resistor and a capacitor connected in series with each other. 
     According to a power receiver apparatus of a 19th aspect, in the power receiver apparatus of the 18th aspect, the filter circuit is further provided with a diode connected in parallel to the resistor. 
     According to a power receiver apparatus of a 20th aspect, in the power receiver apparatus of the 18th aspect, the filter circuit is further provided with a diode bridge circuit. 
     According to a power receiver apparatus of a 21st aspect, in the power receiver apparatus of the 17th aspect, the filter circuit is provided with a Zener diode. 
     According to a power receiver apparatus of a 22nd aspect, in the power receiver apparatus of the 17th aspect, the filter circuit is a low pass filter including an inductor and a capacitor. 
     According to a power receiver apparatus of a 23rd aspect, in the power receiver apparatus of the 17th aspect, the filter circuit is a band pass filter including an inductor, a capacitor, and a resistor. 
     According to a power transmission system of a 24th aspect, a power transmission system includes: at least one power transmitter apparatus of any one of the 10th to 16th aspects; and at least one power receiver apparatus of any one of the 17th to 23th aspects. 
     According to a power transmission system of a 25th aspect, A power transmission system including: at least one power transmitter apparatus of the 10th aspect; and at least one power receiver apparatus of the 17th aspect. The filter circuit includes a capacitor. For an integer N, a resonant circuit including the first and second reactors and the capacitor is configured to have a resonance frequency equal to N/2 times a clock frequency of the modulation code and the demodulation code. 
     INDUSTRIAL APPLICABILITY 
     A power transmission system according to the present disclosure is suitable for power transmission from a power generator, such as solar power generation, wind power generation, and hydroelectric power generation, to a load, such as a railway and an electric vehicle (EV). 
     REFERENCE SIGNS LIST 
     
         
         
           
               1 ,  1 - 1  to  1 - 2 : POWER GENERATOR 
               1   m ,  1   m - 1 ,  1   m - 2 : POWER METER 
               2 ,  2 - 1 ,  2 - 2 ,  2 A,  2 A- 1  to  2 A- 2 ,  2 B: CODE MODULATOR 
               3 : TRANSMISSION PATH 
               4 ,  4 - 1 ,  4 - 2 ,  4 A,  4 A- 1  to  4 A- 2 ,  4 B: CODE DEMODULATOR 
               5 ,  5 - 1  to  5 - 2 : LOAD 
               5   m ,  5   m - 1  to  5   m - 2 : POWER METER 
               10 ,  10 A to  10 B: CONTROLLER 
               11 : CONTROL CIRCUIT 
               12 ,  12 A,  12 B: COMMUNICATION CIRCUIT 
               20 : CONTROL CIRCUIT 
               21 : COMMUNICATION CIRCUIT 
               22 ,  22 A: CODE GENERATION CIRCUIT 
               23 ,  23 A: CODE MODULATION CIRCUIT 
               30 : CONTROL CIRCUIT 
               31 : COMMUNICATION CIRCUIT 
               32 ,  32 A: CODE GENERATION CIRCUIT 
               33 ,  33 A: CODE DEMODULATION CIRCUIT 
               41  to  45   d : FILTER CIRCUIT 
               51 ,  54 : CURRENT METER 
               52 ,  53 : VOLTAGE METER 
             Ca 1  to Ca 4 , C 201  to C 221 : CAPACITOR 
             Ca 5 , Cab: VARIABLE CAPACITOR 
             D 1  to D 34 , D 101  to D 222 : DIODE 
             L 1 , L 2 : REACTOR 
             R 201  to R 221 : RESISTOR 
             S 1  to S 74 , S 101  to S 222 : SWITCH ELEMENT 
             SS 1  to SS 34 , SS 21 A to SS 34 A: SWITCH CIRCUIT 
             T 1  to T 14 : PORT 
             ZD: ZENER DIODE