Patent Publication Number: US-11394390-B2

Title: Analog/digital converter

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a national phase entry of PCT Application No. PCT/JP2019/032569, filed on Aug. 21, 2019, which claims priority to Japanese Application No. 2018-165111, filed on Sep. 4, 2018, which applications are hereby incorporated herein by reference. 
     TECHNICAL FIELD 
     The present invention relates to an analog-to-digital converter that converts analog input signals into digital signals individually in each frequency band thereof, and then synthesizes the converted signals into one on a frequency axis and outputs the result. 
     BACKGROUND 
     An Analog-to-Digital Converter (ADC) used in optical communication, measuring instruments, and so on is preferably, from the viewpoint of circuit integration, manufactured by a CMOS process in which integration with a Digital Signal Processor (DSP) is easy. However, a CMOS process has a narrow bandwidth, meaning that there is a limit on the extent to which the bandwidth of the ADC can be widened. 
     A band division method using a frequency converter manufactured by a process having a wider bandwidth has been proposed in the current system as a technique for widening the bandwidth of an ADC (see NPL 1 and so on, for example).  FIG. 4  is a block diagram showing a configuration of a conventional analog-to-digital converter.  FIG. 4  shows a case in which a frequency band W of an analog input signal Sx is divided into N partial bands Wi (i=1 to N, N being an integer), and signal components of the respective partial bands Wi are A/D-converted individually on channels (processing systems) CHi provided respectively for the partial bands Wi. 
     As shown in  FIG. 4 , a conventional analog-to-digital converter  50  includes, as processing blocks for each CHi, an analog processing block Ai of an analog processing circuit portion  50 A and a digital processing block Bi of a digital processing circuit portion  50 B. 
     First, in each Aj (j=2 to the integer N) of the analog processing circuit portion  50 A i  a filter  61  extracts a signal s 1   j  of a corresponding partial band Wj from the analog input signal Sx having the wide frequency band W. Next, a frequency converter  62  down-converts s 1   j  to a low frequency-side signal S 2   j  using a corresponding local signal fj. Next, a sub A/D converter  63  (SADC) converts S 2   j  into a digital signal S 3   j.    
     Next, in each B j  of the digital processing circuit portion  50 B i  a frequency converter  64  up-converts S 3   j  acquired by the corresponding Aj using a local signal fj and outputs a channel output signal syj of the CHj to an adder  70 . 
     In A 1  of the analog processing circuit portion  50 A i  meanwhile, the filter  61  extracts a signal s 11  of the corresponding partial band W 1  from the analog input signal Sx having the wide frequency band W. Next, s 11  is converted into a digital signal S 31  by the sub A/D converter  63  (SADC) without being down-converted. 
     Next, in B 1  of the digital processing circuit portion  50 B i  S 3   j  acquired by A 1  is output directly to the adder  70  as a channel output signal sy 1  of CH 1  without being up-converted. 
     Next, the adder  70  generates a digital output signal Sy corresponding to the original analog input signal Sx by adding together the channel output signals syi of the respective channels CHi so as to synthesize the signals on a frequency axis, and then outputs the generated digital output signal Sy. 
     CITATION LIST 
     Non Patent Literature 
     
         
         NPL1—G. Raybon, et al., “160-Gbaud coherent receiver based on 100-GHz bandwidth, 240-GS/s analog-to-digital conversion”, M2G. 1. pdf, OFC 2015 Conference Papers, Optical Fiber Communication Conference (OFC), 2015. 
       
    
     SUMMARY 
     Technical Problem 
     With this conventional technique, however, a plurality of filter circuits are required in order to extract the signals of the partial bands Wi on the input side, and these filter circuits lead to an increase in circuit area. Moreover, manufacturing filter circuits that satisfy desired filter characteristics (center frequency, bandwidth, rejection, and so on) at high frequencies with a high degree of precision results in an increase in the complexity of the circuit configuration. 
     Embodiments of the present invention have been designed to solve these problems, and an object thereof is to provide an analog-to-digital converter that can convert a wi de-band analog input signal into a digital output signal on the basis of a band division method without the need for filter circuits. 
     Means for Solving the Problem 
     To achieve this object, an analog-to-digital converter according to embodiments of the present invention includes N analog processing blocks Ai provided for respective channels CHi (i=1 to N, N being an integer), the channels CHi being acquired by dividing a frequency band corresponding to an analog input signal Sx into N parts, in order to process analog signals of the corresponding channels CHi, N digital processing blocks Bi provided for the respective channels CHi in order to process digital signals of the corresponding channels CHi, and an adder that outputs a digital output signal Sy corresponding to the analog input signal Sx by adding together channel output signals Syi from the channels CHi, the channel output signals Syi being acquired by the digital processing blocks Bi, so as to synthesize the channel output signals Syi on a frequency axis, wherein an analog processing block Aj (j=2 to the integer N) includes a frequency converter that down-converts the analog input signal Sx using a cutoff frequency fj- 1  of a channel CHj- 1 , and a sub A/D converter that A/D-converts an analog signal Saj acquired by the frequency converter, a digital processing block Bj includes a multiplier that doubles a signal strength of a first digital signal S 1   j  acquired by the sub A/D converter of the analog processing block Aj, a subtractor that subtracts a third digital signal S 3   j - 1  relating to the channel CHj- 1  from a second digital signal S 2   j  acquired by the multiplier, and outputs a third digital signal S 3   j  of a corresponding channel CH j , and a frequency converter that up-converts the third digital signal Sgj acquired by the subtractor using the cutoff frequency fj- 1  and outputs the result to the adder as a channel output signal Syj of the corresponding channel CHj, an analog processing block A 1  includes a sub A/D converter that A/D-converts the analog input signal Sx, and a digital processing block B 1  outputs a first digital signal S 11  acquired by the sub A/D converter of the analog processing block A 1  as a third digital signal of a corresponding channel CH 1 , and also outputs the first digital signal S 11  to the adder as a channel output signal Sy 1  of the corresponding channel CH 1 . 
     Further, in an example configuration of the analog-to-digital converter according to embodiments of the present invention, described above, the digital processing blocks Bi each include a digital filter that compensates for a frequency characteristic in a corresponding partial band Wi in the band of a first output signal Sit from the analog processing block Ai of the corresponding channel CHi on the basis of an inverse transfer function of a signal path through the analog processing block Ai. 
     Effects of Embodiments of the Invention 
     According to embodiments of the present invention, a wide-band analog input signal can be converted into a digital output signal on the basis of a band division method without the need for filter circuits. Hence, it is possible to avoid increases in the circuit area and the complexity of the circuit configuration, these increases being caused by filter circuits, and as a result, an analog-to-digital converter can easily be manufactured by a CMOS process in which integration with a digital signal processor (DSP) is easy. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing a configuration of an analog-to-digital converter according to a first embodiment. 
         FIG. 2  is an illustrative view showing simulation results according to the first embodiment. 
         FIG. 3  is a block diagram showing a configuration of an analog-to-digital converter according to a second embodiment. 
         FIG. 4  is a block diagram showing a configuration of a conventional analog-to-digital converter. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     Next, embodiments of the present invention will be described with reference to the figures. 
     First Embodiment 
     First, referring to  FIG. 1 , an analog-to-digital converter  10  according to a first embodiment of the present invention will be described.  FIG. 1  is a block diagram showing a configuration of an analog-to-digital converter according to the first embodiment. 
     The analog-to-digital converter  10  is a circuit that A/D-converts an analog input signal Sx on the basis of a band division method and outputs a digital output signal Sy. 
     As shown in  FIG. 1 , the analog-to-digital converter  10  includes, as main circuit portions, an analog processing circuit portion  10 A that performs analog signal processing for the purpose of A/D conversion, and a digital processing circuit portion  10 B that performs digital signal processing for the purpose of A/D conversion. The analog processing circuit portion  10 A is constituted by various circuit components, while the digital processing circuit portion  10 B is constituted by a calculation processing circuit in which a multiprocessor such as a DSP or a CPU cooperates with a program. 
     The analog-to-digital converter  10  according to this embodiment has a function for generating and outputting the digital output signal Sy corresponding to the original analog input signal Sx by dividing a frequency band W of Sx into N consecutive partial bands Wi (i=1 to N, N being an integer), individually A/D-converting signal components of the respective partial bands Wi on channels (processing systems) CHi provided respectively for the partial bands Wi, and synthesizing digital signals acquired as a result on a frequency axis. 
     Note that the partial bands Wi corresponding to channels CH 1 , CH 2 , CH 3 , . . . , CHN are set respectively at DC (direct current component) to f 1 , f 1  to f 2 , f 2  to f 3 , . . . , fN−1 to fN, and the respective bandwidths thereof are assumed to be equal. Note that a frequency fi denotes a frequency that is i times larger than f 1 , i being an integer. Further, signal components corresponding to CH 1 , CH 2 , CH 3 , . . . , CHN are expressed as D 1 ( f ), D 2 ( f ), D 3 ( f ), . . . , DN(f). Accordingly, a total signal component Dall(f) of Sx is expressed by D 1 ( f )+D 2 ( f )+D 3 ( f )+ . . . +DN(f). 
     The analog processing circuit portion  10 A includes N analog processing blocks Ai provided for the respective channels CHi in order to process the analog signals of the channels CHi. 
     Further, the digital processing circuit portion  10 B includes an adder  20  and N digital processing blocks Bi. The digital processing blocks Bi are provided for the respective channels CHi in order to process the digital signals of the channels CHi. The adder  20  is provided so as to be shared by the channels CHi, and the adder  20  generates and outputs Sy corresponding to the original Sx by adding together the channel output signals Syi of the respective channels CHi, which are acquired by the digital processing blocks Bi, so as to synthesize (connect) the channel output signals Syi on a frequency axis. 
     Analog processing blocks Aj (j=2 to the integer N), among the analog processing blocks Ai, each include a frequency converter (down-converter)  11  and a sub A/D converter (SADC)  12 . The frequency converter (down-converter)  11  down-converts Sx using a cutoff frequency (the lower limit frequency of CHj) fj- 1  of CHj- 1 , which is a local signal. The sub A/D converter (SADC)  12  A/D-converts an analog signal Saj acquired by the frequency converter  11 . 
     Further, an analog processing block A 1 , among the analog processing blocks Ai, includes the sub A/D converter (SADC)  12  for A/D-converting Sx (=Sa 1 ). Note that A 1  does not include the frequency converter  11 . 
     Digital processing blocks Bj (j=2 to the integer N), among the digital processing blocks Bi, each include a subtractor  14  and a frequency converter (up-converter)  15 . The subtractor  14  outputs, with a multiplier (×2)  13  for doubling the signal strength of a first digital signal S 1   j  acquired by the sub A/D converter  12  of Aj, a third digital signal S 3   j  of CHj by subtracting a third digital signal S 3   j - 1  relating to CHj- 1  from a second digital signal S 2   j  acquired by the multiplier  13 . The frequency converter (up-converter)  15  up-converts the third digital signal S 3   j  acquired by the subtractor  14  to an upper-side waveband using the cutoff frequency (the lower limit frequency of CHj) fj- 1  of CHj- 1 , which is a local signal, and outputs the result to the adder  20  as the channel output signal Syj of CHj. 
     Further, a digital processing block B 1 , among the digital processing blocks Bi, has a function for outputting a first digital signal S 11  acquired by the sub A/D converter  12  of A 1  as a third digital signal S 31  of CH 1 , and a function for outputting the same first digital signal S 11  to the adder  20  as a channel output signal Sy 1  of CH 1 . 
     Operations of First Embodiment 
     Next, referring to  FIG. 1 , operations of the analog-to-digital converter  10  according to this embodiment will be described. To facilitate understanding, a case in which the number N of divided bands is N=3 will be described below as an example. The present invention is not limited thereto, however, and may be applied similarly to cases in which N=2 or N&gt;3. 
     The analog input signal Sx is input into the analog processing blocks A 1 , A 2 , A 3  corresponding to the respective channels CH 1 , CH 2 , CH 3 . 
     First, in A 1  of CH 1 , since A 1  does not include the frequency converter  11 , Sx (=Sa 1 ) is converted into the first digital signal S 11  by the sub A/D converter  12 . Typically, an A/D converter itself has a low pass filter characteristic. Therefore, in the sub A/D converter  12 , in accordance with the low pass filter characteristic thereof, only a signal component D 1   a ( f ) in a range of DC (direct current component) to f 1 , within the total signal component Dall(f) of Sx, is subjected to A/D conversion and output as S 11 . 
     Hence, D 1   a ( f ) matches the signal component D 1 ( f ) of CH 1 , and is expressed by the following formula (1).
 
Formula 1
 
 D 1 a ( f )= D 1( f )  (1)
 
     Next, in A 2  of CH 2 , Sx is frequency-converted by the frequency converter  11 . At this time, Dall(f) is input into an RF port of the frequency converter  11 , and the cutoff frequency f 1  of CH 1  is input into an LO port. Accordingly, a signal component D 2   m ( f ) acquired by down-converting Dall(f) using f 1  is output from an IF port as an analog signal Sa 2 . D 2   m ( f ) is expressed by the following formula (2). 
     
       
         
           
             
               
                 
                   
                       
                   
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     Note that “*” in each formula represents a complex conjugate. The frequency converter  11  of A 2  is constituted by a mixer of a double side band (DBS), wherein the ports have infinite bandwidth and each port is completely isolated. Note, however, that an actual mixer has a limited bandwidth, and therefore, in the frequency converter  11  of A 2 , it is sufficient for the RF port to have a wider bandwidth than DC to f 2  and for the IF port to have a bandwidth of at least DC to f 1 . 
     Next, D 2   m ( f ) acquired by the frequency converter  11  is converted into a first digital signal S 12  by the sub A/D converter  12  of A 2 . At this time, similarly to CH 1 , the sub A/D converter  12 , due to the low pass filter characteristic thereof, A/D-converts only a signal component D 2   a ( f ) of D 2   m ( f ) in a range of DC (direct current component) to f 1 . D 2   a ( f ) is expressed by the following formula (3). 
     
       
         
           
             
               
                 
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     Next, in A 3  of CH 3 , Sx is frequency-converted by the frequency converter  11 . At this time, Dall(f) is input into the RF port of the frequency converter  11 , and the cutoff frequency f 2  of CH 2  is input into the LO port. Accordingly, a signal component D 3   m ( f ) acquired by down-converting Dall(f) using f 2  is output from the IF port as an analog signal Sa 3 . D 3   m ( f ) is expressed by the following formula (4). 
     
       
         
           
             
               
                 
                   
                       
                   
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     The frequency converter  11  of A 3  is also constituted by a mixer of a double side band (DBS), wherein the ports have infinite bandwidth and each port is completely isolated. Note, however, that an actual mixer has a limited bandwidth, and therefore, in the frequency converter  11  of A 3 , it is sufficient for the RF port to have a wider bandwidth than f 1  to f 3  and for the IF port to have a bandwidth of at least DC to f 1 . 
     Next, D 3   m ( f ) acquired by the frequency converter  11  is converted into a first digital signal S 13  by the sub A/D converter  12  of A 3 . At this time, due to the low pass filter characteristic of the sub A/D converter  12 , only a signal component D 3   a ( f ) of D 3   m ( f ) in a range of DC (direct current component) to f 1  is subjected to A/D conversion. D 3   a ( f ) is expressed by the following formula (5). 
     
       
         
           
             
               
                 
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     Thus, the first digital signals Sn, S 12 , S 13  acquired by the analog processing blocks A 1 , A 2 , A 3  corresponding to the respective channels CH 1 , CH 2 , CH 3  are input into the digital processing blocks B 1 , B 2 , B 3  corresponding to the respective channels CH 1 , CH 2 , CH 3 . 
     First, in B 1 , the signal component D 1   a ( f ) of S 11  input therein is output to the adder  20  as the channel output signal Sy 1  of CH 1 , which is constituted by the signal component D 1 ( f ). Further, S 11  is output to B 2  as a third digital signal S 31  of CH 1 . 
     Next, in B 2 , the signal component D 2   a ( f ) of S 12  input therein is doubled by the multiplier  13 , whereupon the subtractor  14  subtracts the signal component D 1   a ( f ) of the third digital signal S 31  of CH 1  from a second digital signal S 22  acquired by the multiplier  13 . The frequency converter  15  up-converts a third digital signal S 32  acquired by the subtractor  14  to the original frequency band using the cutoff frequency f 1  of CH 1 , whereupon the resulting signal is output to the adder  20  as a channel output signal Sy 2  of CH 2 , which is constituted by the signal component D 2 ( f ). 
     D 2 ( f ) acquired by the digital signal processing executed in B 2  is expressed by the following formula (6).
 
Formula 6
 
 D 2( f )=2× D 2 a ( f−f 1)− D 1 a *(− f )  (6)
 
     Next, in B 3 , the signal component D 3   a ( f ) of S 13  input therein is doubled by the multiplier  13 , whereupon the subtractor  14  subtracts the signal component D 2   a ( f ) of the third digital signal S 32  of CH 2  from the second digital signal S 23  acquired by the multiplier  13 . The frequency converter  15  up-converts a third digital signal S 33  acquired by the subtractor  14  to the original frequency band using the cutoff frequency f 2  of CH 2 , whereupon the resulting signal is output to the adder  20  as a channel output signal Sy 3  of CH 3 , which is constituted by the signal component D 3 ( f ). 
     D 3 ( f ) acquired by the digital signal processing executed in B 3  is expressed by the following formula (7).
 
Formula 7
 
 D 3( f )=2× D 3 a ( f−f 2)− D 2 a *(− f )  (7)
 
     Thereafter, the signal components D 1 ( f ), D 2 ( f ), D 3 ( f ) of the channel output signals Sy 1 , Sy 2 , Sy 3  of CH 1 , CH 2 , CH 3 , output from B 1 , B 2 , B 3 , are synthesized on the frequency axis by the adder  20 . At this time, the frequency bands of D 1 ( f ), D 2 ( f ), D 3 ( f ) are DC (direct current component) to f 1 , f 1  to f 2 , and f 2  to f 3 , respectively, and therefore the digital output signal Sy corresponding to the original analog input signal Sx is output from the adder  20 . 
     Simulation Results 
     Next, referring to  FIG. 2 , simulation results relating to the operations of the analog-to-digital converter  10  according to this embodiment will be described.  FIG. 2  is an illustrative view showing simulation results according to the first embodiment. A case in which the analog input signal Sx having a frequency band W of DC to 90 GHz, a strength of 1, and a random phase is divided into three (N=3) partial bands Wi (i=1, 2, 3) and the signal components of the respective partial bands Wi are individually A/D-converted on the channels (processing systems) CHi provided respectively for the partial bands Wi will be described below as an example. The present invention is not limited to this example, however, and may be applied similarly to cases in which N=2 or N&gt;3. 
     First, in the analog processing block A 1  of CH 1 , Sx is input directly into the sub A/D converter  12 . At this time, the cutoff frequencies of the low pass filter characteristics exhibited by the sub A/D converters  12  of the respective channels are all 30 GHz (f 1 ). Therefore, in A 1 , only the DC to 30 GHz signal component D 1   a ( f ) of Sx (=Sa 1 ) is converted by the sub A/D converter  12  into the first digital signal S 11  and output to the digital processing block B 1  of CH 1 . 
     In B 1 , S 11  input therein is output to the adder  20  as the channel output signal Sy 1  of CH 1 , which includes the DC to 30 GHz signal component D 1 ( f ). Further, S 11  is output to B 2  as the third digital signal S 31  of CH 1 . 
     In the analog processing block A 2  of CH 2 , meanwhile, Sx is first multiplied by a 30 GHz (f 1 ) local signal in the frequency converter  11  so as to be down-converted to the analog signal Sa 2  including the signal component D 2   m ( f ). Next, similarly to CH 1 , only the DC to 30 GHz signal component D 2   a ( f ) of Sa 2  is converted by the sub A/D converter  12  of A 2  into the first digital signal S 12  and output to the digital processing block B 2  of CH 2 . 
     In B 2 , the multiplier  13  converts S 12  input therein into the second digital signal S 22  having twice the signal strength, whereupon the subtractor  14  subtracts the signal component D 1   a ( f ) corresponding to the third digital signal S 31  of CH 1  from S 22 . The converter  15  of B 2  up-converts the third digital signal S 32  acquired as a result to the channel output signal Sy 2  of CH 2 , which includes the 30 to 60 GHz signal component D 2 ( f ), on the basis of a 30 GHz (f 1 ) local signal, and outputs the result to the adder  20 . 
     Similarly, in the analog processing block A 3  of CH 3 , Sx is first multiplied by a 60 GHz (f 2 ) local signal in the frequency converter  11  so as to be down-converted to the analog signal Sa 3  including the signal component D 3   m ( f ). Next, only the DC to 30 GHz signal component D 3   a ( f ) of Sa 3  is converted by the sub A/D converter  12  of A 3  into the first digital signal S 13  and output to the digital processing block B 3  of CH 3 . 
     In B 3 , the multiplier  13  converts S 13  input therein into the second digital signal S 23  having twice the signal strength, whereupon the subtractor  14  subtracts the signal component D 2   a ( f ) corresponding to the third digital signal S 32  of CH 2  from S 23 . The converter  15  of B 3  up-converts the third digital signal S 33  acquired as a result to the channel output signal Sy 3  of CH 3 , which includes the 60 to 90 GHz signal component D 3 ( f ), on the basis of a 60 GHz (f 2 ) local signal, and outputs the result to the adder  20 . 
     Next, the adder  20  synthesizes the channel output signals Sy 1 , Sy 2 , Sy 3  on the same frequency axis, and outputs the result as the digital output signal Sy corresponding to the original analog input signal Sx. 
     Effects of First Embodiment 
     Hence, in this embodiment, in the analog processing block Aj (j=2 to the integer N), the frequency converter  11  down-converts the analog input signal Sx using the cutoff frequency fj- 1  of the channel CHj- 1 , whereupon the sub A/D converter  12  A/D-converts the analog signal Saj acquired by the frequency converter  11 . Then, in the digital processing block Bj, the multiplier  13  doubles the signal strength of the first digital signal S 1   j  acquired by the sub A/D converter  12  of the analog processing block Aj, whereupon the subtractor  14  subtracts the third digital signal S 3   j - 1  of the channel CHj- 1  from the second digital signal S 2   j  acquired by the multiplier  13  and outputs the third digital signal S 3   j  of the corresponding channel CHj. The frequency converter  15  up-converts the third digital signal S 3   j  acquired by the subtractor  14  using the cutoff frequency fj- 1  and outputs the result to the adder  20  as the channel output signal Syj of the corresponding channel CHj. 
     Further, in the analog processing block A 1 , the sub A/D converter  12  A/D-converts the analog input signal Sx, whereupon the digital processing block B 1  outputs the first digital signal S 11  acquired by the sub A/D converter  12  of the analog processing block A 1  as the third digital signal S 31  of the corresponding channel CH 1  and also outputs the first digital signal S 11  to the adder  20  as the channel output signal Sy 1  of the corresponding channel CH 1 . 
     The adder  20  adds together the channel output signals Syi (i=1 to the integer N) of the channels CHi, acquired by the respective digital processing blocks Bi, thereby synthesizing the channel output signals Syi on a frequency axis, and as a result outputs the digital output signal Sy corresponding to the analog input signal Sx. 
     Thus, the channel output signals Syi including the signal components corresponding respectively to the partial bands Wi are acquired by signal processing on the digital processing circuit portion  10 B side without providing filter circuits corresponding to the respective partial bands Wi on the analog processing circuit portion  10 A side. Accordingly, the wide-band analog input signal Sx can be converted into the digital output signal Sy on the basis of a band division method without the need for filter circuits. Hence, it is possible to avoid increases in the circuit area and the complexity of the circuit configuration, these increases being caused by filter circuits, and as a result, an analog-to-digital converter can easily be manufactured by a CMOS process in which integration with a digital signal processor (DSP) is easy. 
     Second Embodiment 
     Next, referring to  FIG. 3 , the analog-to-digital converter  10  according to a second embodiment of the present invention will be described.  FIG. 3  is a block diagram showing a configuration of the analog-to-digital converter according to the second embodiment. 
     Typically, a circuit component may have a frequency characteristic in which the strength and phase of the output signal vary relative to the input signal, for example a characteristic in which the pass characteristic decreases or a ripple occurs in the pass characteristic as the frequency increases. When a circuit component used in the analog processing blocks Ai of the analog processing circuit portion  10 A has a non-flat frequency characteristic such as that described above, this leads to deterioration of the SN ratio of the channel output signal Syi during the addition and subtraction processing performed in the digital processing blocks Bi of the digital processing circuit portion  10 B. 
     In this embodiment, in response to cases of this type, a digital filter is provided at the input stage of each digital processing block Bi in order to compensate for the frequency characteristics of the respective channels CHi in the partial bands Wi. 
     More specifically, in this embodiment, as shown in  FIG. 3 , each digital processing block Bi includes a digital filter  16  that compensates for the frequency characteristic in a corresponding partial band Wi in the band of the first output signal Sit from the analog processing block Ai of the corresponding channel CHi on the basis of an inverse transfer function of a signal path through the analog processing block Ai. All other configurations of this embodiment are similar to the first embodiment, and therefore detailed description thereof has been omitted. 
     The inverse transfer function used by the digital filter  16  may be created by inputting a known test signal such as an impulse signal or a multitone signal, for example, into the actual analog processing block Ai and creating the inverse transfer function on the basis of the difference between the first digital signal S 1   i  output from the Ai and the test signal. 
     Thus, in B 2  of the channel CHj (j=2 to the integer N), the digital filter  16  compensates for the frequency characteristic of the first digital signal S 1   j  input therein in the corresponding partial band Wi, whereupon a fourth digital signal S 4   j  acquired as a result is input into the multiplier  13 . All other operations of this embodiment are similar to the first embodiment, and therefore detailed description thereof has been omitted. 
     Effects of Second Embodiment 
     Hence, in this embodiment, the digital filter  16  of the digital processing block Bi compensates for the frequency characteristic in a corresponding partial band Wi in the band of the first output signal Si 1  from the analog processing block Ai of the corresponding channel CH 1  on the basis of the inverse transfer function of the signal path through the analog processing block Ai. 
     Thus, deterioration of the SN ratio of the output signal Si 4  caused by the frequency characteristic of a circuit component of the analog processing block Ai can be reduced, and as a result, A/D conversion can be performed with a high degree of precision. 
     Expansion of the Embodiments 
     The present invention was described above with reference to embodiments, but the present invention is not limited to the above embodiments. Various modifications that could be understood by a person skilled in the art may be applied to the configurations and details of the present invention within the scope of the present invention. Moreover, the embodiments may be implemented in any desired combinations providing no contradictions arise as a result. 
     REFERENCE SIGNS LIST 
     
         
         
           
               10  Analog-to-digital converter 
               10 A Analog processing circuit portion 
               10 B Digital processing circuit portion 
             A 1 , A 2 , A 3 , AN, Ai, Aj Analog processing block 
             B 1 , B 2 , B 3 , BN, Bi, Bj Digital processing block 
               11  Frequency converter 
               12  Sub A/D converter (SADC) 
               13  Multiplier 
               14  Subtractor 
               15  Frequency converter 
               16  Digital filter 
               20  Adder 
             CH 1 , CH 2 , CH 3 , CHN, CH 1 , CHj Channel 
             Sx Analog input signal 
             Sy 1 , Sy 2 , Sy 3 , SyN, Sy 1 , Syj Channel output signal 
             Sy Digital output signal 
             W Frequency band 
             Wi, Wj Partial band 
             Sa 1 , Sa 2 , Sa 3 , SaN, Sai, Saj Analog signal 
             S 11 , S 12 , S 13 , SiN, S 1   i , S 1   j  First digital signal 
             S 21 , S 22 , S 23 , S 2 N, S 2   i , S 2   j  Second digital signal 
             S 31 , S 32 , S 33 , S 3 N, S 3   i , S 3   j  Third digital signal 
             S 41 , S 42 , S 43 , S 4 N, S 4   i , S 4   j  Fourth digital signal