Patent Publication Number: US-7586721-B2

Title: ESD detection circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an ESD (electrostatic discharge) detection circuit and related method, and more particularly, to an ESD detection circuit and related method capable of reducing a size of the ESD detection circuit itself and extending a duration of discharge. 
     2. Description of the Prior Art 
     Please refer to  FIG. 1 .  FIG. 1  is a diagram of a prior art ESD protection circuit  10 . The ESD protection circuit  10  includes a low-pass filter  11  having a resistor R and a capacitor C, an inverter  12 , and an ESD Clamp Circuit  13 . The inverter  12  is composed of a P-type field effect transistor (FET) MP and a N-type FET MN. When an electrostatic signal Sesd rises at a first node Na of the ESD protection circuit  10 , a voltage level at a second node Nb is temporarily maintained at a lower level because of the low-pass filter  11 . The P-type FET MP is turned on and the N-type FET MN is turned off. Accordingly, through the P-type FET MP, the electrostatic signal Sesd is converted into a current signal I_trig, which is utilized for triggering the ESD clamp circuit  13  to perform a discharge operation upon the electrostatic signal Sesd at the first node Na. However, when the voltage level at the first node Na is higher than that of a normal supply voltage VDD (e.g. the voltage level at the first node Na equals 3*VDD), gate-oxide layers of the capacitor C, the P-type FET MP, and the N-type FET MN will be damaged since voltage drops across the gate-oxide layers will become much larger. In summary, the ESD protection circuit  10  cannot absorb the electrostatic signal Sesd which has greater voltage amplitudes. Further description is detailed in US patent application pub. No. 20030076636A1. 
     In addition, according to U.S. Pat. No. 5,956,219, another ESD protection circuit is disclosed. Although the ESD protection circuit is able to absorb an electrostatic signal having greater voltage amplitudes, this ESD protection circuit implemented by a triple well process has some disadvantages. The ESD protection circuit increases cost of production and complicates the gate-driven technique, especially when an advanced nano-scale CMOS (Complementary Metal-Oxide-Semiconductor) process is applied. 
     Additionally, according to U.S. Pat. No. 6,954,098, an ESD protection circuit is further disclosed. Similarly, the ESD protection circuit is also capable of absorbing an electrostatic signal having greater voltage amplitudes. In addition to a normal supply voltage, however, this ESD protection circuit further requires a lower supply voltage for proper operation. If either one of the normal or lower supply voltages is not provided, gate-oxide layers of FETs within the ESD protection circuit could be damaged. Consequently, in order to avoid the above-mentioned problems, the ESD protection circuit disclosed by U.S. Pat. No. 6,954,098 is usually implemented by the thicker gate-oxide layer process technique, subsequently increasing cost of production. 
     SUMMARY OF THE INVENTION 
     It is therefore one of the objectives of the present invention to provide an ESD detection circuit and related method, to solve the above-mentioned problems. 
     According to an embodiment of the claimed invention, an ESD detection circuit is disclosed. The ESD detection circuit is coupled between a first node and a second node, and the ESD detection circuit comprises a triggering circuit, a bias circuit, a trigger controlling circuit, and an activating control circuit. The triggering circuit is utilized for generating an ESD trigger signal when the ESD detection circuit is in ESD mode. The bias circuit is coupled to the triggering circuit and utilized for providing at least a first bias voltage and a second bias voltage to control the operation of the triggering circuit. The trigger controlling circuit is coupled to the bias circuit and the triggering circuit, and the trigger controlling circuit is utilized for decreasing a voltage difference between the first bias voltage and the second bias voltage when the ESD detection circuit is in the ESD mode, to control a duration of the ESD trigger signal generated by the triggering circuit. The activating control circuit is coupled to the trigger controlling circuit and the trigger circuit, and it is utilized for activating the trigger controlling circuit and the triggering circuit to enter the ESD mode according to a voltage level at the first node. 
     According to another embodiment of the claimed invention, a method for generating an ESD trigger signal corresponding to a first node and a second node is disclosed. The method comprises: activating an ESD mode according to a voltage level at the first node; providing a trigger circuit and utilizing the trigger circuit to generate the ESD trigger signal in the ESD mode; providing at least a first bias voltage and a second bias voltage to control an operation of the trigger circuit; and decreasing a voltage difference between the first bias voltage and the second bias voltage in the ESD mode, for controlling a duration of the ESD trigger signal. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of a prior art ESD protection circuit. 
         FIG. 2  is a diagram of an ESD detection circuit according to an embodiment of the present invention. 
         FIG. 3  is a chart showing the electrostatic signal S ESD , the first bias voltage V 1 , the second bias voltage V 2 , and voltage levels at the nodes N b , N 3 , N 4 , N 5 , and N 6  when the ESD detection circuit shown in  FIG. 2  operates in the ESD mode. 
         FIG. 4  is a flowchart illustrating an operation of the ESD detection circuit shown in  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION 
     Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
     Please refer to  FIG. 2 .  FIG. 2  is a diagram of an ESD detection circuit  100  according to an embodiment of the present invention. The ESD detection circuit  100  includes a triggering circuit  101 , a bias circuit  102 , a trigger controlling circuit  103 , and an activating control circuit  104 . The ESD detection circuit  100  is coupled between a first node N VDD  and a second node N GND . The triggering circuit  101  is utilized for generating an ESD trigger signal S trigger  when the ESD detection circuit  100  is in ESD mode. The bias circuit  102  is coupled to the triggering circuit  101  and utilized for providing a first bias voltage V 1 , a second bias voltage V 2 , and a third bias voltage V 3 , for controlling the operation of the triggering circuit  101 . The trigger controlling circuit  103  is coupled to the bias circuit  102  and the triggering circuit  01  ; the trigger controlling circuit  103  is utilized for decreasing a voltage difference V diff  between the first bias voltage V 1  and the second bias voltage V 2  in the ESD mode, to control a duration T trigger  of the ESD trigger signal S trigger , which is generated by the triggering circuit  101 . The activating control circuit  104  is coupled to the trigger controlling circuit  103  and the triggering circuit  101 . The activating control circuit  104  is utilized for activating the trigger controlling circuit  103  and triggering circuit  101  to enter the ESD mode according to a voltage level V DD  at the first node N VDD . Please note that, in order to describe the spirit of the ESD detection circuit  100  disclosed in this embodiment more clearly, an ESD clamp circuit  105  is further coupled to the first node N VDD , the second node N GND , and the triggering circuit  101 . The ESD clamp circuit  105  is used for performing a discharge operation upon the voltage at the first node N VDD  according to the ESD trigger signal S trigger . Specifically, the ESD clamp circuit  105  includes a PNP BJT (bipolar junction transistor)  1051 , an NPN BJT  1052 , a N-well resistor  1053 , a P-well resistor  1054 , and a plurality of diodes  1055 . The configuration of the ESD clamp circuit  105  is shown in  FIG. 2  but is not detailed for the sake of brevity. 
     As shown in  FIG. 2 , the bias circuit  102  is coupled between the first node N VDD  and the second node N GND . The bias circuit  102  includes a plurality of P-type FETs M d1 , M d2 , M d3 , M d4 , M d5 , and M d6  with a first, second, third, fourth, fifth, and sixth diode-connected configurations, respectively. These diode-connected P-type FETs M d1 , M d2 , M d3 , M d4 , M d5 , and M d6  are connected between the first node N VDD  and the second node N GND  in a cascading arrangement, and they are utilized for generating the first bias voltage V 1 , the second bias voltage V 2 , and the third bias voltage V 3 , according to the voltage levels (i.e. V DD  and V GND ) at the first node N VDD  and second node N GND . In the bias circuit  102 , not all base terminals of the diode-connected FETs are coupled to source terminals of the same diode-connected FETs: the base terminals of the first and second P-type FETs M d1  and M d2  are coupled to the first node N VDD , the base terminals of the third and fourth P-type FETs M d3  and M d4  are coupled to the first bias voltage V 1 , and the base terminals of the fifth and sixth P-type FETs M d5  and M d6  are coupled to the second bias voltage V 2 . The activating control circuit  104  includes a resistor R 1  and a capacitor M C1 . The resistor R 1  is serially connected to the first node N VDD  and a first terminal N b  of the capacitor M C1 . 
     The trigger controlling circuit  103  includes a first P-type FET M 1 , a second P-type FET M 2 , a third P-type FET M 3 , a first switching FET M s1 , a second switching FET M s2 , and a voltage level controlling circuit  1031 . The P-type FET M 1  has a source terminal coupled to the first node N VDD  and a gate terminal coupled to the first terminal N b  of the capacitor M c1 . The second P-type FET M 2  has a source terminal coupled to a drain terminal (i.e. N 1 ) of the first P-type FET M 1  and a gate terminal (i.e. N 2 ) coupled to the first bias voltage V 1 . The third P-type FET M 3  has a source terminal coupled to a drain terminal (i.e. N 3 ) of the second FET M 2 , a gate terminal (i.e. a node N 4 ) coupled to the second bias voltage V 2 , and a drain terminal N dm3  coupled to the second node N GND . The first switching P-type FET M s1  has a drain terminal (i.e. N 2 ) coupled to the bias voltage V 1  and the activating control circuit  104 , a source terminal coupled to the triggering circuit  101  (i.e. N 5 ), and a gate terminal coupled to the drain terminal (i.e. N 3 ) of the second P-type FET M 2 . The second switching P-type FET M s2  has a drain terminal (i.e. N 4 ) coupled to the second bias voltage V 2 , a source terminal coupled to a node N 6  of the triggering circuit  101 , and a gate terminal (i.e. N 7 ) coupled to the third bias voltage. Additionally, the voltage level controlling circuit  1031  is coupled between the drain terminals of the first switching P-type FET M s1  and second switching P-type FET M s2 . The voltage level controlling circuit  1031  is utilized for decreasing the voltage difference V diff  between the first bias voltage V 1  and second bias voltage V 2  according to a voltage level V r  at the drain terminal of the second P-type FET M 2  when the ESD detection circuit  100  is in the ESD mode. In this embodiment, the voltage level controlling circuit  1031  includes a first inverter  10311  and a fourth P-type FET M 4 ; the first inverter  10311  is comprised of a P-type FET and a N-type FET (as shown in  FIG. 2 ). The first inverter  10311  has a first reference node coupled to the gate terminal (i.e. N 2 ) of the second P-type FET M 2 , a second reference node coupled to the gate terminal (i.e. N 4 ) of the third P-type FET M 3 , and an input node coupled to the drain terminal of the second P-type FET M 2 . The fourth P-type FET M 4  has a source terminal coupled to the gate terminal of the second P-type FET M 2 , a drain terminal coupled to the gate terminal of the third P-type FET M 3 , and a gate terminal coupled to an output node N 8  of the first inverter  10311 . 
     The triggering circuit  101  includes a fifth P-type FET M 5 , a sixth P-type FET M 6 , and a second inverter  1011 . The fifth P-type FET M 5  has a source terminal coupled to the first node N VDD , a gate terminal coupled to the first terminal N b  of the capacitor M c1 , and a drain terminal coupled to the source terminal (i.e. N 5 ) of the first switching P-type FET M s1 . The sixth P-type FET M 6  has a source terminal coupled to the drain terminal of the fifth P-type FET M 5  and source terminal of the first switching P-type FET M s1 , a gate terminal coupled to the drain terminal (i.e. N 2 ) of the first switching p-type FET M s1 , and a drain terminal (i.e. N 6 ) coupled to the source terminal of the second switching P-type FET M s2 . The second inverter  1011  is comprised of a P-type FET and a N-type FET (as shown in  FIG. 2 ). The second inverter  1011  has a first reference node coupled to the drain terminal of the sixth P-type FET M 6 , a second reference node coupled to the second node N GND , an input node coupled to the drain terminal of the second switching P-type FET M s2 , and an output node N 10  utilized for outputting the ESD trigger signal S trigger . 
     In this embodiment, the ESD detection circuit  100  can operate under two modes (the ESD mode and a normal mode). When the ESD detection circuit  100  operates in the normal mode, the N-type FET in the second inverter  1011  is utilized for maintaining a voltage level of the output node N 10  at the ground level V GND , and the first node N VDD  is coupled to a supply voltage V DD . In order to describe the spirit of the present invention more clearly, it is assumed that the ground level V GND  and the supply voltage V DD  equal zero and 3.3 volts respectively. Therefore, in normal mode, the first bias voltage V 1 , the second bias voltage V 2 , and the third bias voltage V 3  are respectively equal to 2.2 volts, 1.1 volts, and 0.6 volts. Please note that, since the base terminal of the P-type FET M d6  is coupled to the node N 4 , there exists a body effect in the P-type FET M d6 . The third bias voltage V 3  thus becomes 0.6 volts, and the second switching FET M s2  is turned on because of the third bias voltage V 3 . As shown in  FIG. 2 , due to the second bias voltage V 2 , a voltage level at the node N 6  is charged through the second switching FET M s2  until the voltage level at the node N 6  equals 1.1 volts. Since a voltage difference across the source-drain terminals of the P-type FET in the second inverter  1011  is zero, this P-type FET is turned off. Accordingly, in normal mode, the ESD detection circuit  100  does not generate the ESD trigger signal S trigger , and the ESD clamp circuit  105  is not enabled. Additionally, the N-type FET in the second inverter  1011  is turned on, so the phase margin of the ESD detection circuit  100  is widened for ensuring that the trigger controlling circuit  103  does not trigger the ESD clamp circuit  105  in normal mode. 
     Moreover, since the first P-type FET M 1  and fifth P-type FET M 5  are biased by the supply voltage V DD  equaling 3.3 volts, the first P-type FET M 1  and fifth P-type FET M 5  are turned off. In other words, in normal mode, a current path composed of the P-type FETs M 1 , M 2 , and M 3  is not conductive, and the P-type FET M 2  is turned off. That is to say, a voltage drop across the source-gate terminals of the P-type FET M 2  is lower than the threshold voltage |V tp | (i.e. 1.2 volts) of a common P-type FET. Therefore, the voltage level at the node N 1  is maintained between 2.2 volts and 2.2 volts plus the threshold voltage |V tp |. Similarly, the P-type FET M 3  is also turned off, and the voltage level at the node N 3  is maintained between 1.1 volts and 1.1 volts plus the threshold voltage |V tp |. When the P-type FET of the first inverter  10311  and the first switching FET M s1  are turned on, the voltage levels at the nodes N 2  and N 5  are equal to 2.2 volts. The voltage drops at the source-gate terminals of the N-type FET of the first inverter  10311 , the fourth P-type FET M 4 , and the sixth P-type FET M 6  are approximately equal to zero so that they are turned off. As mentioned above, in this embodiment, when the ESD detection circuit  100  operates in normal mode and the supply voltage VDD is equal to 3.3 volts, all FETs having voltage drops equal to 1.2 volts across their gate-oxide layers can operate correctly. 
     On the other hand, when the ESD protection circuit  100  is not in normal mode, the supply voltage V DD  at the first node N VDD  is equal to zero. However, when the electrostatic signal S DD  is introduced at the first node N VDD  (e.g. the power of the supply voltage V DD  is enabled instantaneously), an impulse signal will occur immediately at the voltage level of the first node N VDD . A peak value of the impulse signal is usually higher than the supply voltage V DD  (i.e. 3.3 volts) in normal mode. This will cause a circuitry coupled to the supply voltage V DD  to be damaged. In order to describe the spirit of the present invention more clearly, in this embodiment, a peak value of the electrostatic signal S ESD  is assumed to equal 6 volts for illustrative purposes. That is, when the power of the supply voltage V DD  is enabled instantaneously, the voltage level of the electrostatic signal S ESD  at the first node N VDD  rises from zero to 6 volts rapidly (as shown in  FIG. 3 ).  FIG. 3  is a chart showing the electrostatic signal S ESD , the first bias voltage V 1 , the second bias voltage V 2 , and voltage levels (i.e. V nb , V n3 , V n4 , V n5 , and V n6 ) at the nodes N b , N 3 , N 4 , N 5 , and N 6  when the ESD detection circuit  100  shown in  FIG. 2  operates in the ESD mode. When the electrostatic signal S ESD  rises and reaches 6 volts at timing t 1 , the voltage level V nb  at the first node N b  rises more slowly than the electrostatic signal S ESD  since the activating control circuit  104  is an RC low-pass filter. This will cause a voltage drop across the first node N VDD  and the first node N b . The P-type FET M 1  and M 5  are therefore turned on, and the nodes N 1  and N 5  are charged so that the voltage levels V n1  and V n5  at the nodes N 1  and N 5  raise rapidly. Since the first bias voltage V 1 , the second bias voltage V 2 , and the third bias voltage V 3  at the nodes N 2 , N 4 , and N 7  in the timing t 0  are approximately equal to zero, the P-type FETs M 2  and M 3  are also turned on and the nodes N 3  and N 6  are charged when the electrostatic signal S ESD  is introduced. Rising values of the voltage levels V n3  and V n6  at the nodes N 3  and N 6  are substantially equal to those at the nodes N 1  and N 5 . The second switching FET M s2  is subsequently turned on. This is because the voltage level at node N 7  still remains at a lower level than the voltage level V n6  at node N 6  even as the voltage level V n6  is rising. Accordingly, the voltage level V n4  at the node N 4  is charged and then rises to equal voltage level V n6 . In practice, however, an RC delay caused by the turned-on resistance of the second switching FET M s2  and parasitic capacitance at the node N 4  will maintain the voltage level V n4  of the node N 4  at a lower voltage level, as shown in  FIG. 3 . Because of the lower voltage level, the second switching FET M s2  will be continuously turned on when the electrostatic signal S ESD  occurs. Additionally, the voltage level V n3  at the gate terminal (i.e. the node N 3 ) of the P-type FET in the first inverter  10311  is higher that that (i.e. the voltage level V n4 ) at the node N 4 . The N-type FET is therefore turned on so that the voltage level V n8  at the node N 8  is approximately equal to that (i.e. the voltage level V n4 ) at the node N 4 . The P-type FET M 4  is then turned on so that the first bias voltage V 1  at the node N 2  is forced to be near the second bias voltage V 2  at the node N 4 . The voltage difference V diff  between the first bias voltage V 1  and second bias voltage V 2  equals the threshold voltage |V tp | of the P-type FET M 4 . 
     Additionally, when the ESD detection circuit  100  operates in the ESD mode, since a difference between the voltage levels at the gate and source terminals (i.e. the nodes N 3  and N 5 ) of the second switching FET M s2  is very small so that the second switching FET M s2  will be turned off. The first bias voltage V 1  comes to a voltage level which is lower than the voltage level V n5 . As mentioned above, the voltage levels at the gate terminals (i.e. N b  and N 2 ) of the P-type FETs M 5  and M 6  in the triggering circuit  101  and the voltage level at the gate terminal (i.e. N 4 ) of the P-type FET in the second inverter  1011  can be maintained at lower levels. Thus, the electrostatic signal S ESD  is rapidly converted into the ESD trigger signal S trigger , which is transmitted to the node N 10 . It should be noted that those skilled in this art should understand that the ESD trigger signal S trigger  is a current signal. Moreover, since the voltage level controlling circuit  1031  of the trigger controlling circuit  103  is a digital control circuit, a size of the trigger controlling circuit  103  can be considerably reduced and the leakage of electricity can also be decreased when the ESD detection circuit  100  operates in the normal mode. The operation of the ESD clamp circuit  105  should be understood by those skilled in this art; further description is not detailed for the sake of the brevity. Furthermore, it should be noted that the triggering circuit  101 , the bias circuit  102 , the trigger controlling circuit  103  and the activating control circuit  104  can be implemented by transistors having gate dielectrics where thickness of the gate dielectrics is substantially identical. This design modification also falls within the scope of the present invention. 
     Please refer to  FIG. 4 .  FIG. 4  is a flowchart illustrating a method for generating an ESD trigger signal corresponding to a first node and a second node according to a second embodiment of the present invention. Since the method for generating the ESD trigger signal can be implemented with the ESD detection circuit  100  shown in  FIG. 2 , the flowchart in the following is detailed in conjunction with the ESD detection circuit  100  for describing the spirit of the method more clearly. Provided that substantially the same result is achieved, the steps of the flowchart shown in  FIG. 4  need not be in the exact order shown and need not be contiguous; that is, other steps can be intermediate. The method includes the following steps: 
     Step  401 : Start. 
     Step  402 : Determine whether the ESD detection circuit  100  is in normal mode or in ESD mode. When the ESD detection circuit  100  operates under the normal mode, go to Step  403 ; otherwise, go to Step  406  when the ESD detection circuit  100  operates under the ESD mode. 
     Step  403 : Utilize the bias circuit  102  to generate the first bias voltage V 1 , the second bias voltage V 2 , and the third bias voltage V 3  according to the supply voltage V DD  at the first node N VDD . 
     Step  404 : Use the trigger controlling circuit  103  and activating control circuit  104  to disable the triggering circuit  101  according to the first bias voltage V 1 , the second bias voltage V 2 , and the third bias voltage V 3 . 
     Step  405 : Disable the ESD clamp circuit  105 . 
     Step  406 : Use the activating control circuit  104  to enable the triggering circuit  101  for generating the ESD trigger signal S trigger  to trigger the ESD clamp circuit  105 . 
     Step  407 : Utilize the trigger controlling circuit  103  to force the first bias voltage V 1  at the node N 2  to be near to the second bias voltage V 2  at the node N 4  for extending the duration T trigger  of the ESD trigger signal S trigger . 
     Step  408 : Use the ESD clamp circuit  105  to rapidly discharge the electrostatic signal S ESD  at the first node N VDD . 
     It should be noted that in Step  402 , the supply voltage V DD  at the first node N VDD  is equal to zero while the ESD detection circuit  100  in not the normal mode. In other words, when the electrostatic signal S ESD  rises at the first node N VDD , the voltage level at the first node N VDD  is initially also equal to zero. Therefore, in Step  407 , the trigger controlling circuit  103  will force the first bias voltage V 1  at node N 2  to be near zero (at node N 4 ). Additionally, the trigger controlling circuit  103  also utilizes the voltage level controlling circuit  1031  to control the P-type FET M 4  for forcing the first bias voltage V 1  at the node N 2  to be near the second bias voltage V 2  at the node N 4 . 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.