Patent Publication Number: US-6656794-B2

Title: Method of manufacturing semiconductor device including a memory area and a logic circuit area

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method of manufacturing a semiconductor device including a memory area and a logic circuit area. More specifically the invention pertains to a method of manufacturing a semiconductor device, on which each of non-volatile memory devices formed in the memory area has two charge accumulation regions relative to one word gate. 
     2. Description of the Related Art 
     One type of non-volatile semiconductor memory devices is MONOS (Metal Oxide Nitride Oxide Semiconductor) or SONOS (Silicon Oxide Nitride Oxide Silicon), in which a gate insulating layer between a channel area and a control gate is a multi-layered body of a silicon oxide layer and a silicon nitride layer and charges are trapped by the nitride silicon layer. 
     FIG. 22 shows a known MONOS non-volatile semiconductor memory device (refer to: Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers p. 122-123). 
     Each MONOS memory cell  100  has a word gate  14 , which is formed on a semiconductor substrate  10  via a first gate insulating layer  12 . A first control gate  20  and a second control gate  30  are formed as side walls on both sides of the word gate  14 . A second gate insulating layer  22  is present between the bottom of the first control gate  20  and the semiconductor substrate  10 . An insulating layer  24  is present between the side face of the first control gate  20  and the word gate  14 . Similarly the second gate insulating layer  22  is present between the bottom of the second control gate  30  and the semiconductor substrate  10 . The insulating layer  24  is present between the side wall of the second control gate  30  and the word gate  14 . Impurity layers  16  and  18 , each of which constitutes either a source area or a drain area, are formed in the semiconductor substrate  10  to be located between the control gate  20  and the control gate  30  of adjoining memory cells. 
     Each memory cell  100  accordingly has two MONOS memory elements on the side faces of the word gate  14 . These two MONOS memory elements are controlled independently. Namely each memory cell  100  is capable of storing 2-bit information. 
     A memory area including such MONOS memory cells and a logic circuit area including peripheral circuits of memories are formed on an identical semiconductor substrate in a semiconductor device. A prior art method of manufacturing such a semiconductor device first forms memory cells in the memory area and subsequently forms peripheral circuits in the logic circuit area. The manufacturing method forms diverse wiring layers via an insulating layer, after formation of the memory area and the logic circuit area. 
     The manufacturing method forms an insulating layer of, for example, silicon oxide, and polishes the insulating layer by CMP (chemical mechanical polishing) technique. The polishing is carried out until exposure of stopper layers under the insulating layer in the memory area. 
     The polishing rate of the insulating layer is, however, not constant but is varied, and the insulating layer in the logic circuit area is polished relatively faster than the insulating layer in the memory area. There is accordingly a possibility that gate electrodes in the logic circuit area are exposed, prior to exposure of the stopper layers in the memory area. 
     Exposure of the gate electrodes in the logic circuit area may cause resulting MOS transistors in the logic circuit area to be exposed to an etching gas, which affects the properties of the MOS transistors, in a subsequent process of patterning word gates of memory cells. 
     OF THE INVENTION 
     The object of the present invention is thus to provide a manufacturing method of a semiconductor device, which effectively prevents exposure of gate electrodes in a logic circuit area in an insulating layer polishing process. 
     In order to attain at least part of the above and the other related objects, the present invention is directed to a method of manufacturing a semiconductor device, which includes a memory area having a non-volatile memory device and a logic circuit area including a peripheral circuit of the non-volatile memory device. The manufacturing method includes the steps of (a) providing a semiconductor substrate, which includes a semiconductor layer, a first insulating layer formed on the semiconductor layer, a first conductive layer formed on the first insulating layer, and a stopper layer formed on the first conductive layer; (b) patterning the stopper layer and the first conductive layer in the memory area; (c) forming control gates as side walls on both side faces of the patterned first conductive layer via an oxide nitride oxide (ONO) membrane in the memory area; (d) etching out the stopper layer in the logic circuit area; (e) patterning the first conductive layer in the logic circuit area to form a gate electrode of an insulated gate field effect transistor; (f) forming a second insulating layer in both the memory area and the logic circuit area; and (g) polishing the second insulating layer to expose the stopper layer in the memory area. The step (d) performs over-etching to remove an upper portion of the first conductive layer, simultaneously with removal of the stopper layer. 
     The manufacturing method of the invention performs over-etching to remove an upper portion of the first conductive layer in the logic circuit area, simultaneously with etching out the stopper layer. The method subsequently patterns the first conductive layer to form the gate electrode in the logic circuit area. The height of the gate electrode is lowered, because of the removed upper portion of the first conductive layer. 
     In the manufacturing method of the invention, the height of the gate electrode formed in the logic circuit area is lowered. In the subsequent process of polishing the second insulating layer, even when the polishing rate of the second insulating layer is not constant but varied and the second insulating layer in the logic circuit area is polished relatively faster than the second insulating layer in the memory area, this arrangement of the invention effectively prevents exposure of the gate electrode in the logic circuit area, prior to exposure of the stopper layer in the memory area. 
     In one preferable application of the manufacturing method of the invention, the step (c) includes the sub-steps of: (c−1) forming the ONO membrane in at least the memory area; (c−2) forming a second conductive layer on the ONO membrane; and (c−3) etching the second conductive layer to form the control gates of the second conductive layer via the ONO membrane on both side faces of the patterned first conductive layer in the memory area. 
     These sub-steps enable the control gates to be formed as side walls via the ONO membrane on both side face of the patterned first conductive layer. 
     In one preferable embodiment of the manufacturing method of the semiconductor device according to the present invention, the step (g) applies CMP technique to polish the second insulating layer. 
     This technique is suitable for leveling off the inter-layer insulating layer over the whole surface of the semiconductor substrate. 
    
    
     The above and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiment with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a plan view schematically illustrating the layout of a memory area in a semiconductor device; 
     FIG. 2 is another plan view schematically illustrating the layout of the memory area in the semiconductor device; 
     FIG. 3 is a plan view schematically illustrating a main part of the semiconductor memory device; 
     FIG. 4 is a sectional view taken on the line A—A in FIG. 2; 
     FIG. 5 is a sectional view illustrating one process in a manufacturing method of the semiconductor device shown in FIGS. 1 through 4; 
     FIG. 6 is a sectional view illustrating one process in the manufacturing method of the semiconductor device shown in FIGS. 1 through 4; 
     FIG. 7 is a plan view showing one process in the manufacturing method of the semiconductor device shown in FIG. 6; 
     FIG. 8 is a sectional view illustrating one process in the manufacturing method of the semiconductor device shown in FIGS. 1 through 4; 
     FIG. 9 is a sectional view illustrating one process in the manufacturing method of the semiconductor device shown in FIGS. 1 through 4; 
     FIG. 10 is a sectional view illustrating one process in the manufacturing method of the semiconductor device shown in FIGS. 1 through 4; 
     FIG. 11 is a sectional view illustrating one process in the manufacturing method of the semiconductor device shown in FIGS. 1 through 4; 
     FIG. 12 is a sectional view illustrating one process in the manufacturing method of the semiconductor device shown in FIGS. 1 through 4; 
     FIG. 13 is a sectional view illustrating one process in the manufacturing method of the semiconductor device shown in FIGS. 1 through 4; 
     FIG. 14 is a sectional view illustrating one process in the manufacturing method of the semiconductor device shown in FIGS. 1 through  4 ; 
     FIG. 15 is a sectional view illustrating one process in the manufacturing method of the semiconductor device shown in FIGS. 1 through 4; 
     FIG. 16 is a sectional view illustrating one process in the manufacturing method of the semiconductor device shown in FIGS. 1 through 4; 
     FIGS.  17 (A) and  17 (B) show the details of the polishing process by CMP technique; 
     FIG. 18 is a sectional view illustrating a stopper layer removing process in a manufacturing method of a semiconductor device in one embodiment of the present invention; 
     FIG. 19 is a sectional view illustrating a gate electrode formation process in the manufacturing method of the semiconductor device in the embodiment of the present invention; 
     FIG. 20 is a sectional view illustrating an insulating layer formation process in the manufacturing method of the semiconductor device in the embodiment of the present invention; 
     FIG. 21 is a sectional view illustrating an insulating layer polishing process by the CMP technique in the manufacturing method of the semiconductor device in the embodiment of the present invention; and 
     FIG. 22 is a sectional view illustrating a known MONOS memory cell. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIGS. 1 and 2 are plan views illustrating the layout of a memory area in a semiconductor device manufactured according to a manufacturing method in one embodiment of the present invention. FIG. 3 is a plan view illustrating part of the semiconductor device manufactured according to the manufacturing method in the embodiment of the present invention. FIG. 4 is a sectional view taken on the line A—A in FIG.  3 . 
     The semiconductor device shown in FIGS. 1 through 4 has a memory area  1000  and a logic circuit area  2000  including peripheral circuits of memories. The memory area  1000  has a memory cell array, in which MONOS non-volatile memory devices (hereafter referred to as ‘memory cells’)  100  are arranged in lattice of multiple rows and multiple columns. 
     A. Structure of Device 
     The layout of the memory area  1000  is discussed first with reference to FIGS. 1 and 2. 
     FIG. 1 shows a first block B 1  and a second block B 2  adjoining to the first block B 1  as part of the memory area  1000 . FIG. 2 shows the contact structure of the first block B 1  with the second block B 2 . 
     An element separating region  300  is formed in a partial area between the first block B 1  and the second block B 2 . Multiple word lines  50  (WL) extending in a direction X (in a row direction) and multiple bit lines  60  (BL) extending in a direction Y (in a column direction) are arrayed in each block B 1  or B 2 . Each of the word lines  50  is connected to multiple word gates  14  arranged in the direction X. The bit lines  60  are composed of impurity layers  16  and  18 . 
     Conductive layers  40  are formed to surround the respective impurity layers  16  and  18  and constitute first and second control gates  20  and  30 . The first and the second control gates  20  and  30  respectively extend in the direction Y. The respective one ends of each pair of the first and the second control gates  20  and  30  are connected with each other via the conductive layer  40  extending in the direction X. The respective other ends of each pair of the first and the second control gates  20  and  30  are linked with one common contact element  200 . The first and the second control gates  20  and  30  accordingly have general functions as the control gate of the memory cell and wiring functions of connecting the paired control gates arranged in the direction Y. 
     Each memory cell  100  has one word gate  14 , the first and the second control gates  20  and  30  arranged on both sides of the word gate  14 , and the impurity layers  16  and  18  that are formed in the semiconductor substrate and located outside these control gates  20  and  30 . The impurity layers  16  and  18  are shared by the adjoining memory cells  100 . 
     The two impurity layers  16  adjoining to each other in the direction Y, that is, the impurity layer  16  formed in the block B 1  and the impurity layer  16  formed in the adjoining block B 2 , are electrically connected with each other via a contact impurity layer  400  formed in the semiconductor substrate. The contact impurity layer  400  is located opposite to the common contact element  200  of the control gates across the impurity layer  16 . 
     A contact  350  is formed on each contact impurity layer  400 . The bit lines  60  of the impurity layers  16  are electrically linked with an upper wiring layer via the contacts  350 . 
     Similarly, the two impurity layers  18  adjoining to each other in the direction Y are electrically connected with each other via the contact impurity layer  400  on the side without the common contact element  200  (see FIG.  2 ). 
     As shown in FIG. 1, the planar layout of the multiple common contact elements  200  in each block has a zigzag pattern, where the common contact elements  200  are arranged alternately on different sides of the impurity layers  16  and  18 . Similarly, as shown in FIG. 2, the planar layout of the multiple contact impurity layers  400  in each block has a zigzag pattern, where the contact impurity layers  400  are arranged alternately on different sides of the impurity layers  16  and  18 . 
     The planar structure and the sectional structure of the semiconductor device are discussed with reference to FIGS. 3 and 4. The logic circuit area  2000  including peripheral circuits of memories is formed adjacent to the memory area  1000 . The memory area  1000  is electrically separated from the logic circuit area  2000  by means of the element separating region  300 . The memory area  1000  includes at least the multiple memory cells  100 . The logic circuit area  2000  includes at least insulated gate field effect transistors (hereafter referred to as ‘MOS transistors’)  500  constructing logic circuits. 
     The description first regards the memory area  1000 . 
     As shown in FIG. 4, each memory cell  100  includes the word gate  14  that is formed on a semiconductor substrate  10  via a first gate insulating layer  12 , the impurity layers  16  and  18  that are formed in the semiconductor substrate  10  to constitute either a source area or a drain area, and the first and the second control gates  20  and  30  that are formed as side walls along both sides of the word gate  14 . Silicide layers  92  are arranged on the top of the impurity layers  16  and  18 . 
     The first control gate  20  is arranged on the semiconductor substrate  10  via a second gate insulating layer  22  and on one side face of the word gate  14  via a side insulating layer  24 . Similarly the second control gate  30  is arranged on the semiconductor substrate  10  via the second gate insulating layer  22  and on the other side face of the word gate  14  via the side insulating layer  24 . 
     The second gate insulating layer  22  and the side insulating layer  24  are ONO membranes. More specifically, the second gate insulating layer  22  and the side insulating layer  24  are multi-layered membranes including a silicon oxide bottom layer (first silicon oxide layer (O)), a silicon nitride layer (N), and a silicon oxide top layer (second silicon oxide layer (O)). 
     The first silicon oxide layer of the second gate insulating layer  22  makes a potential barrier between a channel area and a charge accumulation region. 
     The silicon nitride layer of the second gate insulating layer  22  functions as a charge accumulation region for trapping carriers (for example, electrons). 
     The second silicon oxide layer of the second gate insulating layer  22  makes a potential barrier between the control gate and the charge accumulation region. 
     The side insulating layer  24  electrically separates the word gate  14  from the control gates  20  and  30 . In order to prevent a short circuit between the word gate  14  and the first and the second control gates  20  and  30 , the upper end of the side insulating layer  24  is located above the upper ends of the control gates  20  and  30  relative to the semiconductor substrate  10 . 
     The side insulating layer  24  and the second gate insulating layer  22  are produced by the same film forming process and have the identical layer structure. 
     An embedded insulating layer  70  is disposed between the first control gate  20  and the second control gate  30  of the adjoining memory cells  100 . The embedded insulating layer  70  covers over at least the control gates  20  and  30  to prevent exposure thereof. In the concrete structure, the upper face of the embedded insulating layer  70  is located above the upper end of the side insulating layer  24  relative to the semiconductor substrate  10 . Such arrangement of the embedded insulating layer  70  ensures the electrical separation of the first and the second control gates  20  and  30  from the word gates  14  and the word lines  50 . 
     A conductive layer is formed on the common contact element  200  to apply a predetermined potential to the control gates  20  and  30 . The common contact element  200  includes a first contact insulating layer  212 , a second contact insulating layer  210 , a first contact conductive layer  214 , a second contact conductive layer  232 , a third contact insulating layer  252 , and a third contact conductive layer  260 . 
     The first contact insulating layer  212  is produced by the same manufacturing process as that of the first gate insulating layer  12 . 
     The second contact insulating layer  212  is produced by the same manufacturing process as that of the second gate insulating layer  22  and the side insulating layer  24 . The second contact insulating layer  210  is a multi-layered ONO membrane including a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer. 
     The first contact conductive layer  214  is produced by the same manufacturing process as that of the word gate  14 . The first contact conductive layer  214  is formed outside the second contact insulating layer  210 . 
     The second contact conductive layer  232  is formed inside the second contact insulating layer  210 . The second contact conductive layer  232  is produced by the same manufacturing process as that of the first and the second control gates  20  and  30  to be integrated with these control gates  20  and  30 . Namely the second contact conductive layer  232  and the control gates  20  and  30  are made of an identical material. 
     The third contact insulating layer  252  is formed inside the second contact conductive layer  232 . The third contact insulating layer  252  is produced by the same manufacturing process as that of side wall insulating layers  152 . 
     The third contact conductive layer  260  is produced by the same manufacturing process as that of the word line  50  and is linked with the first contact conductive layer  214  and the second contact conductive layer  232 . 
     The MOS transistors  500  are created in the logic circuit area  2000 . Each MOS transistor  500  includes a gate electrode  142  that is created on the semiconductor substrate  10  via a third gate insulating film  122 , impurity layers  162  and  182  that are formed in the semiconductor substrate  10  to constitute either a source area or a drain area, and side wall insulating layers  152  that are formed along both sides of the gate electrode  142 . Silicide layers  192  are arranged on the top of the impurity layers  162  and  182 , and a suicide layer  194  is arranged on the top of the gate electrode  142 . 
     In the logic circuit area  2000 , the MOS transistors  500  are covered with an insulating layer  270 . This insulating layer  270  is produced by the same manufacturing process as that of the embedded insulating layer  70 . 
     As shown in FIGS. 3 and 4, a boundary element  140   c , which is composed of the same material as that of the word gate  14  and the gate electrode  142 , is arranged in a boundary region between the memory area  1000  and the logic circuit area  2000 . The boundary element  140   c  is produced by the same film forming process as that of the word gate  14  and the gate electrode  142 . At least part of the boundary element  140   c  is formed above the element separating region  300 . 
     A side wall conductive layer  20   a , which is composed of the same material as that of the control gates  20  and  30 , is arranged on one side face of the boundary element  140   c  (on the side of the memory area  1000 ). The side wall conductive layer  20   a  extends in the direction Y and is electrically connected with the adjoining control gate  30  via the common contact element  200 . The side wall conductive layer  20   a  is not used as the control gate of the memory cell. The electrical connection of the side wall conductive layer  20   a  with the adjoining control gate  30  causes the electric properties of the control gate  30  adjacent to the side wall conductive layer  20   a  to be substantially equal to the electric properties of the other control gates. 
     A side wall insulating layer  152 , which is produced by the same manufacturing process as that of the side wall insulating layers  152  of the MOS transistor  500 , is arranged on the other side face of the boundary element  140   c  (on the side of the logic circuit area  2000 ). 
     An inter-layer insulating layer  72  is formed on the semiconductor substrate  10  with the memory cells  100  and the MOS transistors  500 . The inter-layer insulating layer  72  has contact holes, which run to, for example, the third contact conductive layer  260  of the common contact element  200 . Each contact hole is filled with a conductive layer  82  of, for example, a tungsten plug or a copper plug, which is connected to a wiring layer  80  located above the inter-layer insulating layer  72 . 
     B. Basic Manufacturing Method of Semiconductor Device 
     Prior to description of a manufacturing method of a semiconductor device in one embodiment of the present invention, a basic manufacturing method is discussed with reference to FIGS. 5 through 16. The respective sectional views of FIGS. 5 through 16 correspond to the part taken on the line A—A in FIG.  3 . In the drawings of FIGS. 5 through 16, like elements to those shown in FIGS. 1 through 4 are expressed by like numerals and are not specifically described here. 
     (1) Referring to FIG. 5, the method first forms the element separating regions  300  on the surface of the semiconductor substrate  10  by the technique of trench isolation. The method then forms the contact impurity layers  400  (see FIG. 1) in the semiconductor substrate  10  by the technique of ion implantation. 
     The method subsequently forms an insulating layer  120 , which constructs the gate insulating layers, on the surface of the semiconductor substrate  10 , and makes a gate layer  140 , which constructs the word gates  14  and the gate electrodes  142 , deposit on the insulating layer  120 . The gate layer  140  is made of doped polysilicon. A stopper layer S 100 , which works as an indication of the end of polishing in a later CMP (Chemical Mechanical Polishing) process is further formed on the gate layer  140 . The stopper layer S 100  is composed of the silicon nitride layer. 
     The insulating layer  120 , the gate layer  140 , and the stopper layer S 100  respectively correspond to the first insulating layer, the first conductive layer, and the stopper layer of the present invention. 
     (2) Referring to FIG. 6, a patterned gate layer  140   a  is formed in the memory area  1000 . One concrete procedure for formation of the patterned gate layer  140   a  forms a resist layer (not shown) on the stopper layer S 100  (see FIG. 5) to cover over the whole logic circuit area  2000  and to be extended to part of the memory area  1000 . The procedure then patterns the stopper layer S 100  with the resist layer as the mask, and etches the gate layer  140  with the patterned stopper layer as the mask. This results in patterning the gate layer  140  to give the patterned gate layer  140   a  shown in FIG.  6 . In this process, the gate layer  140  in the logic circuit area  2000  is not patterned. As a matter of convenience, hereafter the gate layer  140  in the logic circuit area  2000  is called the gate layer  140   b . 
     FIG. 7 is a plan view showing the state of the memory area  1000  after patterning. The patterning makes openings  160  and  180  in the multi-layered body of the gate layer  140  and the stopper layer S 100  in the memory area  1000 . The openings  160  and  180  substantially correspond to the regions in which the impurity layers  16  and  18  are formed by a later ion implantation process. The side insulating layers and the control gates are formed afterwards along the side faces of the openings  160  and  180 . 
     (3) Referring to FIG. 8, an ONO membrane  220  is formed over the whole face of the semiconductor substrate  10 . The ONO membrane  220  is obtained by successive deposition of a first silicon oxide layer (O), a silicon nitride layer (N), and a second silicon oxide layer (O). The first silicon oxide layer is formed, for example, by thermal oxidation technique or CVD technique. The silicon nitride layer is formed, for example, by CVD technique. The second silicon oxide layer is formed, for example, by CVD technique or more specifically by high temperature oxidation (HTO) technique. The preferable procedure carries out annealing treatment after formation of these layers to densify the respective layers. 
     A later patterning process of the ONO membrane  220  makes the second gate insulating layer  22 , the side insulating layer  24 , and the second contact insulating layer  210  (see FIG.  4 ). 
     (4) Referring to FIG. 9, a doped polysilicon layer  230  is made to deposit over the whole surface of the ONO membrane  220 . A later etching process of the doped polysilicon layer  230  gives the conductive layer  40  (see FIG. 1) of the control gates  20  and  30  and the second conductive layer  232  (see FIG. 3) of the common contact element  200 . 
     A resist layer R 100  is then formed in the region for the common contact element  200 . 
     (5) Referring to FIG. 10, anisotropic etching of the whole doped polysilicon layer  230  (see FIG. 9) with the resist layer R 100  as the mask gives the first and the second control gates  20  and  30  and the second contact conductive layer  232 . 
     This etching process makes the control gates  20  and  30  as the side walls along the side faces of the openings  160  and  180  (see FIG. 7) in the memory area  1000 . Simultaneously, the second contact conductive layers  232  are formed in the masked parts with the resist layer R 100  (see FIG.  9 ). The doped polysilicon layer  230  depositing in the logic circuit area  2000  is completely removed. In the boundary region, however, the doped polysilicon layer  230  remains as a side wall on the side face of one end of the gate layer  140   b  (on the side of the memory area  1000 ). The resist layer R 100  is then removed. 
     The ONO membrane  220 , the control gates  20  and  30 , and the doped polysilicon layer  230  respectively correspond to the ONO membrane, the control gate, and the second conductive layer of the present invention. 
     (6) Referring to FIG. 11, a resist layer R 200  is then formed to cover over the whole memory area  1000  and to be extended to part of the logic circuit area  2000 . The ONO membrane  220  and the stopper layer S 100  in the logic circuit area  2000  are removed with the resist layer R 200  as the mask. This etching process removes all the stopper layer S 100  in the logic circuit area  2000  except the boundary region. 
     The part of the gate layer  140   b  located in the boundary region between the memory area  1000  and the logic circuit area  2000  and covered with both the resist layer used in the etching process (2) (see FIG. 6) and the resist layer R 200  used in the etching process (6) forms the boundary element  140   c  (see FIG. 4) in a later process. A stopper layer S 100   a  remaining through this patterning process has a greater width than the width of the remaining stopper layers S 100  in the memory area  1000 . The resist layer R 200  is removed subsequently. 
     (7) Referring to FIG. 12, a resist layer R 300  is formed for creation of the gate electrodes  142 . The resist layer R 300  is patterned to cover over the whole memory area  1000  and a predetermined part in the logic circuit area  2000 . Etching of the gate layer  140   b  (see FIG. 11) with the resist layer R 300  as the mask gives the gate electrodes  142  in the logic circuit area  2000 . This etching process also gives the boundary element  140   c  in the boundary region in a self aligning manner with the resist layer R 300  and the stopper layer S 100   a  as the mask. 
     The resist layer R 300  is then removed. Subsequent doping of an N-type impurity creates extension layers  161  and  181  of the source areas and the drain areas in the logic circuit area  2000 . 
     (8) Referring to FIG. 13, an insulating layer  250  of silicon oxide or silicon oxide nitride is formed over the memory area  1000  and the logic circuit area  2000 . 
     (9) Referring to FIG. 14, anisotropic etching of the whole insulating layer  250  (see FIG. 13) gives the side wall insulating layers  152  on both sides of each gate electrode  142  in the logic circuit area  2000 . Simultaneously, the anisotropic etching gives the side wall insulating layer  152  on one side face of the boundary element  140   c  facing the logic circuit area  2000 . This etching process also makes insulating layers  152   a  remain on the control gates  20  and  30 , and forms the third contact insulating layer  252  covering over the second contact conductive layer  232 . The etching process removes the insulating layers depositing on specified regions for formation of silicide layers in a later process and on the gate electrodes  142  in the logic circuit area  2000  to expose the semiconductor substrate  10 . The specific regions include, for example, regions for formation of the impurity layers  16  and  18  in the memory area  1000  and regions for formation of the impurity layers  162  and  182  in the logic circuit area  2000  in a later ion implantation process. 
     Subsequent implantation of an N-type impurity ion forms the impurity layers  16  and  18 , each of which constitutes either a source area or a drain area in the memory area  1000 , and the impurity layers  162  and  182 , each of which constitutes either a source area or a drain area in the logic circuit area  2000 , in the semiconductor substrate  10 . 
     A subsequent process makes a metal for formation of a suicide deposit on the whole surface. Typical examples of the metal for formation of the suicide are titanium and cobalt. The metal depositing on the impurity layers  16 ,  18 ,  162 , and  182  and the gate electrodes  142  is subjected to a silicidation reaction. This forms the silicide layers  92  on the top of the impurity layers  16  and  18 , the suicide layers  192  on the top of the impurity layers  162  and  182 , and the silicide layer  194  on the top of the gate electrodes  142 . This silicidation process silicidates the gate electrodes and either the source areas or the drain areas of the MOS transistors  500  (see FIG. 4) in a self aligning manner in the logic circuit area  2000 . Simultaneously, the silicidation process silicidates the surface of either the source areas or the drain areas of the memory cells  100  (see FIG. 4) in a self aligning manner in the memory area  1000 . 
     The insulating layer  270  of silicon oxide or silicon oxide nitride is formed over the whole surface of the memory area  1000  and the logic circuit area  2000 . The insulating layer  270  is formed to cover over the stopper layers S 100  and S 100   a.    
     (10) Referring to FIG. 15, the insulating layer  270  is polished by the CMP technique to exposure of the stopper layers S 100  and S 100   a  and is leveled off. The polishing makes the insulating layer  270  remain between the two side insulating layers  24  facing each other across the control gates  20  and  30  to define the embedded insulating layer  70 . 
     The upper ends of the side insulating layers  24  formed on the side faces of the gate layer  140   a  and the stopper layer S 100  are located above the upper ends of the first and the second control gates  20  and  30  relative to the semiconductor substrate  10 . It is preferable that the MOS transistors  500  are completely covered with the insulating layer  270  in the logic circuit area  2000 . 
     On completion of this polishing process, the stopper layers S 100  and S 100   a  are accordingly present on the gate layer  140   a , which constructs the word gates  14 , and the boundary element  140   c , respectively. No stopper layer is present on the gate electrodes  142 , but the gate electrodes  142  are covered with the insulating layer  270 . 
     (11) The stopper layers S 100  and S 100   a  (see FIG. 15) are removed with hot phosphoric acid. This results in exposure of at least the upper faces of the gate layer  140   a  and the boundary element  140   c . A doped polysilicon layer is then made to deposit on the whole surface. 
     Referring to FIG. 16, a patterned resist layer R 400  is subsequently formed on the depositing doped polysilicon layer. Patterning of the doped polysilicon layer with the resist layer R 400  as the mask gives the word lines  50  and the third contact conductive layer  260 . 
     The gate layer  140   a  (see FIG. 15) is etched with the resist layer R 400  as the mask. The etching removes part of the gate layer  140   a  where the word lines  50  are not formed thereon. This gives the word gates  14  arranged in an array. The removed part of the gate layer  140   a  corresponds to the region of a P-type impurity layer (element separating impurity layer)  15  created in a later process (see FIG.  3 ). 
     The conductive layer  40 , which constructs the first and the second control gates  20  and  30 , is covered with the embedded insulating layer  70  and is thus not etched but remains by this etching process. The MOS transistors  500  in the logic circuit area  2000  are not affected by this etching process, as long as the MOS transistors  500  are completely covered with the insulating layer  270 . 
     The whole semiconductor substrate  10  is then doped with a P-type impurity. The P-type impurity layer (element separating impurity layer)  15  (see FIG. 3) is accordingly formed between each pair of the word gates  14  adjoining to each other in the direction Y The P-type impurity layer  15  ensures separation between the adjoining memory cells  100 . 
     (12) The process subsequently forms a first inter-layer insulating layer, makes contact holes by any known method, and creates a conductive layer in each contact hole and a first wiring layer. For example, as shown in FIG. 4, the process forms the inter-layer insulating layer  72 , makes contact holes in the inter-layer insulating layer  72 , and creates the conductive layer  82  and the wiring layer  80  connecting with each contact element  200 . This process simultaneously creates contact elements and a wiring layer in the logic circuit area  2000 . 
     The series of processes discussed above manufactures the semiconductor device shown in FIGS. 1 through 4. 
     C. Details of Polishing Process of Insulating Layer by CMP Technique 
     FIGS.  17 (A) and  17 (B) show the details of the polishing process by the CMP technique (see FIG. 15) discussed above in the process (10). FIG. 17 schematically illustrates the sectional area of the main part of the memory area and the logic circuit area in the semiconductor device. 
     As discussed above in the process (9), after the silicidation process, the insulating layer  270  is formed over the whole surface of the memory area  1000  and the logic circuit area  2000  (see FIG.  14 ). In the actual state, as shown in FIG.  17 (A), there are irregularities on the top surface of the insulating layer  270 , which correspond to the gate layers  140   a  in the memory area  1000  and the gate electrodes  142  in the logic circuit area  2000  under the insulating layer  270 . The gate layers  140   a  are formed at a relatively high density in the memory area  1000 , while the gate electrodes  142  are formed at a relatively low density in the logic circuit area  2000 . The density of the irregularities on the top surface of the insulating layer  270  is thus relatively high in the memory area  1000  and is relatively low in the logic circuit area  2000 . Especially the region of the memory area  1000  with the array of multiple memory cells  100  has a higher density of irregularities, compared with the logic circuit area  2000 . 
     After formation of the insulating layer  270 , the insulating layer  270  is polished by the CMP technique to exposure of the stopper layers S 100  and S 100   a , as discussed above in the process (10). There may be a variation in polishing rate of the insulating layer  270 , due to the varying density of the irregularities present on the top surface of the insulating layer  270 . More specifically, the insulating layer  270  in the logic circuit area  2000  having a relatively low density of the irregularities is polished relatively faster than the insulating layer  270  in the memory area  1000  having a relatively high density of the irregularities. This causes exposure of the gate electrodes  142  in the logic circuit area  2000 , prior to exposure of the stopper layers S 100   a  in the memory area  1000  as shown in FIG.  17 (B). 
     Exposure of the gate electrodes  142  causes the MOS transistors  500  in the logic circuit area  2000  to be exposed to the etching gas, which may affect the properties of the MOS transistors  500  in the process (11) discussed above (see FIG.  16 ), for example, in the process of patterning the word gates  14  of the memory cells  100  in the memory area  1000 . 
     In the polishing process (10) by the CMP technique discussed above, the gate electrodes  142  in the logic circuit area  2000  may be exposed, prior to exposure of the stopper layers S 100   a  in the memory area  1000 . This may cause the MOS transistors  500  in the logic circuit area  2000  to be exposed to the etching gas and change their properties in the subsequent process. 
     D. Manufacturing Method of Embodiment 
     A manufacturing method of a semiconductor device in one embodiment of the present invention changes the process of removing the stopper layer from the process (6) discussed above and shown in FIG. 11 to a process shown in FIG. 18, and then carries out the process (10) of polishing the insulating layer  270  by the CMP technique discussed above. 
     FIG. 18 is a sectional view illustrating a stopper layer removing process in the manufacturing method of the semiconductor device in the embodiment of the present invention. The cross section of a main part of the memory area and the logic circuit area in the semiconductor device is schematically shown in FIG.  18 . 
     Referring to FIG. 18, after formation of the resist layer R 200 , the process performs over-etching to remove the upper portion of the gate layer  140   b  located below the stopper layer S 100 , simultaneously with removal of the ONO membrane  220  and the stopper layer S 100  in the logic circuit area  2000  with the resist layer R 200  as the mask. This etching process removes the whole stopper layer S 100  and the upper portion of the gate layer  140   b  in the logic circuit area  2000  except the boundary region. 
     FIG. 19 is a sectional view illustrating a gate electrode formation process in the manufacturing method of the semiconductor device in the embodiment of the present invention. FIG. 20 is a sectional view illustrating an insulating layer formation process. The process of FIG. 19 corresponds to the process (7) discussed above and shown in FIG.  12 . The process of FIG. 20 corresponds to the process (9) discussed above and shown in FIG.  14 . The cross section of the main part of the memory area and the logic circuit area in the semiconductor device is schematically shown in FIGS. 19 and 20. 
     As discussed above, the stopper layer removal process removes the upper portion of the gate layer  140   b  in the logic circuit area  2000  by the over-etching technique. The subsequent gate electrode formation process etches the gate layer  140   b  with the resist layer R 300  as the mask and creates the gate electrodes  142  in the logic circuit area  2000 , as discussed above in the process (7). The height of the gate electrodes  142  created in the process of FIG. 19 is lower than the height of the gate electrodes  142  created in the process of FIG.  12 . 
     The subsequent insulating layer formation process forms the insulating layer  270  over the whole surface of the memory area  1000  and the logic circuit area  2000 , as discussed above in the process (9). The insulating layer  270  in the logic circuit area  2000  has the top surface as shown in FIG.  20 . The density of creation of the gate electrodes  142  is unchanged in the logic circuit area  2000 , while the height of the gate electrodes  142  is lowered in the logic circuit area  2000  by over-etching. The density of the irregularities on the top surface of the insulating layer  270  in the logic circuit area  2000  is accordingly kept lower than that in the memory area  1000 . The height of the irregularities on the top surface of the insulating layer  270  in the logic circuit area  2000  is, however, slightly lowered due to the lower height of the gate electrode  142 , compared with the case of FIG.  17 (A). 
     The gate electrode  142  and the insulating layer  270  respectively correspond to the gate electrode and the second insulating layer of the present invention. 
     After the above series of operations, the process of polishing the insulating layer by the CMP technique is carried out as discussed above in the process (10). 
     FIG. 21 is a sectional view illustrating an insulating layer polishing process by the CMP technique in the manufacturing method of the semiconductor device in the embodiment of the present invention. The cross section of the main part of the memory area and the logic circuit area in the semiconductor device is schematically shown in FIG.  21 . 
     As described above, polishing the insulating layer  270  by the CMP technique keeps the lower density of the irregularities on the top surface of the insulating layer  270  in the logic circuit area  2000 , compared with that in the memory area  1000 . The insulating layer  270  in the logic circuit area  2000  is polished relatively faster than the insulating layer  270  in the memory area  1000 . The height of the gate electrodes  142  in the logic circuit area  2000  is lowered by over-etching, as discussed above. When the insulating layer  270  is polished to exposure of the stopper layers S 100   a  in the memory area  1000 , there is no possibility that the gate electrodes  142  in the logic circuit area  2000  are exposed prior to exposure of the stopper layers S 100   a.    
     As discussed above, the manufacturing method of the semiconductor device in the embodiment effectively prevents exposure of the gate electrodes  142  in the logic circuit area  2000  prior to exposure of the stopper layers S 100   a  in the memory area  1000  in the insulating layer polishing process by the CMP technique. 
     At the stage of completion of the polishing process by the CMP technique, the MOS transistors  600  in the logic circuit area  2000  are completely covered with the insulating layer  270 . The insulating layer  270  has a certain thickness ‘e’ above the gate electrode  142 . 
     The subsequent word gate formation process etches out a desired part of the gate layer  140   a  in the memory area  1000  to create an array of the word gates  14  as discussed previously in the process (11). The arrangement of the embodiment effectively prevents the gate electrodes  142  in the logic circuit area  2000  from being affected by the etching. 
     In the stopper layer removal process of FIG. 18, the removed thickness ‘d’ of the upper portion of the gate layer  140   b  in the logic circuit area  2000  by over-etching is appropriately set by taking into account the polishing rate in the insulating layer polishing process by the CMP technique and the properties of the MOS transistors  500 . 
     The lower limit of the removed thickness ‘d’ of the gate layer  140   b  is set to ensure prevention of exposure of the gate electrodes  142  in the logic circuit area  2000  prior to exposure of the stopper layers  100   a  in the memory area  1000  in the insulating layer polishing process by the CMP technique. The upper limit of the removed thickness ‘d’ is set to leave a sufficient height of the gate electrodes  142  in the logic circuit area  2000  for the required functions of the resulting MOS transistors  500 . 
     The above embodiment and its application are to be considered in all aspects as illustrative and not restrictive. There may be many modifications, changes, and alterations without departing from the scope or spirit of the main characteristics of the present invention. 
     In the embodiment discussed above, the processes (2) through (5) form the gate layers  140   a  and the control gates  20  and  30  in the memory area  1000 , and the subsequent processes (6) through (9) form the gate electrodes  142  and the side wall insulating layers  152  in the logic circuit area  2000 . The technique of the present invention is, however, not limited to this order of operations. The process may inversely form the gate electrodes  142  and the side wall insulating layers  152  in the logic circuit area  2000 , prior to formation of the gate layers  140   a  and the control gates  20  and  30  in the memory area  1000 . 
     The bulk semiconductor substrate is applied for the semiconductor layer of the embodiment. An SOI semiconductor substrate may alternatively be applied for the semiconductor layer. 
     The scope and spirit of the present invention are indicated by the appended claims, rather than by the foregoing description.