Patent Publication Number: US-2020295044-A1

Title: Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same

Description:
CLAIM OF PRIORITY 
     This application is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 15/872,893, filed Jan. 16, 2018, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 15/389,883, filed Dec. 23, 2016, issued as U.S. Pat. No. 9,871,056, on Jan. 16, 2018, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 14/945,361, filed Nov. 18, 2015, issued as U.S. Pat. No. 9,536,899, on Jan. 3, 2017, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 14/476,511, filed Sep. 3, 2014, issued as U.S. Pat. No. 9,245,081, on Jan. 26, 2016, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 13/741,305, filed Jan. 14, 2013, issued as U.S. Pat. No. 8,872,283, on Oct. 28, 2014, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/753,798, filed Apr. 2, 2010, issued as U.S. Pat. No. 8,405,163, on Mar. 26, 2013, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 12/402,465, filed Mar. 11, 2009, issued as U.S. Pat. No. 7,956,421, on Jun. 7, 2011, which claims priority under 35 U.S.C. 119(e) to each of 1) U.S. Provisional Patent Application No. 61/036,460, filed Mar. 13, 2008, 2) U.S. Provisional Patent Application No. 61/042,709, filed Apr. 4, 2008, 3) U.S. Provisional Patent Application No. 61/045,953, filed Apr. 17, 2008, and 4) U.S. Provisional Patent Application No. 61/050,136, filed May 2, 2008. The disclosure of each above-identified patent application is incorporated in its entirety herein by reference. 
    
    
     CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is related to each application identified in the table below. The disclosure of each application identified in the table below is incorporated herein by reference in its entirety. 
     
       
         
           
               
               
               
               
             
               
                   
                   
               
               
                   
                 Attorney 
                 Application 
                 Filing 
               
               
                   
                 Docket No. 
                 No. 
                 Date 
               
               
                   
                   
               
             
            
               
                   
                 TELAP015AC1 
                 12/753,711 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC2 
                 12/753,727 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC3 
                 12/753,733 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC4 
                 12/753,740 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC5 
                 12/753,753 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC6 
                 12/753,758 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC6A 
                 13/741,298 
                 Jan. 14, 2013 
               
               
                   
                 TELAP015AC7 
                 12/753,766 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC7A 
                 13/589,028 
                 Aug. 17, 2012 
               
               
                   
                 TELAP015AC8 
                 12/753,776 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC9 
                 12/753,789 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC10 
                 12/753,793 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC11 
                 12/753,795 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC12 
                 12/753,798 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC12A 
                 13/741,305 
                 Jan. 14, 2013 
               
               
                   
                 TELAP015AC13 
                 12/753,805 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC14 
                 12/753,810 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC15 
                 12/753,817 
                 Apr. 2, 2010 
               
               
                   
                 TELAP015AC16 
                 12/754,050 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC17 
                 12/754,061 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC18 
                 12/754,078 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC19 
                 12/754,091 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC20 
                 12/754,103 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC21 
                 12/754,114 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC22 
                 12/754,129 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC23 
                 12/754,147 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC24 
                 12/754,168 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC25 
                 12/754,215 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC26 
                 12/754,233 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC27 
                 12/754,351 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC27A 
                 13/591,141 
                 Aug. 21, 2012 
               
               
                   
                 TELAP015AC28 
                 12/754,384 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC29 
                 12/754,563 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC30 
                 12/754,566 
                 Apr. 5, 2010 
               
               
                   
                 TELAP015AC31 
                 13/831,530 
                 Mar. 14, 2013 
               
               
                   
                 TELAP015AC32 
                 13/831,605 
                 Mar. 15, 2013 
               
               
                   
                 TELAP015AC33 
                 13/831,636 
                 Mar. 15, 2013 
               
               
                   
                 TELAP015AC34 
                 13/831,664 
                 Mar. 15, 2013 
               
               
                   
                 TELAP015AC35 
                 13/831,717 
                 Mar. 15, 2013 
               
               
                   
                 TELAP015AC36 
                 13/831,742 
                 Mar. 15, 2013 
               
               
                   
                 TELAP015AC37 
                 13/831,811 
                 Mar. 15, 2013 
               
               
                   
                 TELAP015AC38 
                 13/831,832 
                 Mar. 15, 2013 
               
               
                   
                 TELAP015AC40 
                 14/242,308 
                 Apr. 1, 2014 
               
               
                   
                 TELAP015AC45 
                 14/273,483 
                 May 8, 2014 
               
               
                   
                 TELAP015AC46 
                 14/303,587 
                 Jun. 12, 2014 
               
               
                   
                 TELAP015AC47 
                 14/476,511 
                 Sep. 3, 2014 
               
               
                   
                 TELAP015AC48 
                 14/642,633 
                 Mar. 9, 2015 
               
               
                   
                 TELAP015AC49 
                 14/945,361 
                 Nov. 18, 2015 
               
               
                   
                 TELAP015AC52 
                 15/389,883 
                 Dec. 23, 2016 
               
               
                   
                 TELAP015AC53 
                 15/872,893 
                 Jan. 16, 2018 
               
               
                   
                   
               
            
           
         
       
     
     BACKGROUND 
     A push for higher performance and smaller die size drives the semiconductor industry to reduce circuit chip area by approximately 50% every two years. The chip area reduction provides an economic benefit for migrating to newer technologies. The 50% chip area reduction is achieved by reducing the feature sizes between 25% and 30%. The reduction in feature size is enabled by improvements in manufacturing equipment and materials. For example, improvement in the lithographic process has enabled smaller feature sizes to be achieved, while improvement in chemical mechanical polishing (CMP) has in-part enabled a higher number of interconnect layers. 
     In the evolution of lithography, as the minimum feature size approached the wavelength of the light source used to expose the feature shapes, unintended interactions occurred between neighboring features. Today minimum feature sizes are approaching 45 nm (nanometers), while the wavelength of the light source used in the photolithography process remains at 193 nm. The difference between the minimum feature size and the wavelength of light used in the photolithography process is defined as the lithographic gap. As the lithographic gap grows, the resolution capability of the lithographic process decreases. 
     An interference pattern occurs as each shape on the mask interacts with the light. The interference patterns from neighboring shapes can create constructive or destructive interference. In the case of constructive interference, unwanted shapes may be inadvertently created. In the case of destructive interference, desired shapes may be inadvertently removed. In either case, a particular shape is printed in a different manner than intended, possibly causing a device failure. Correction methodologies, such as optical proximity correction (OPC), attempt to predict the impact from neighboring shapes and modify the mask such that the printed shape is fabricated as desired. The quality of the light interaction prediction is declining as process geometries shrink and as the light interactions become more complex. 
     In view of the foregoing, a solution is needed for managing lithographic gap issues as technology continues to progress toward smaller semiconductor device features sizes. 
     SUMMARY 
     An integrated circuit including a cross-coupled transistor configuration is disclosed. The cross-coupled transistor configuration includes two PMOS transistors and two NMOS transistors. In various embodiments, gate electrodes defined in accordance with a restricted gate level layout architecture are used to form the four transistors of the cross-coupled transistor configuration. The gate electrodes of a first PMOS transistor and of a first NMOS transistor are electrically connected to a first gate node so as to be exposed to a substantially equivalent gate electrode voltage. Similarly, the gate electrodes of a second PMOS transistor and of a second NMOS transistor are electrically connected to a second gate node so as to be exposed to a substantially equivalent gate electrode voltage. Also, each of the four transistors of the cross-coupled transistor configuration has a respective diffusion terminal electrically connected to a common output node. 
     Various embodiments of integrated circuits including the cross-coupled transistor configuration are described in the specification and drawings. The various embodiments include different arrangements of transistors. Some described embodiments also show different arrangements of conductive contacting structures and conductive interconnect structures. 
     Aspects and advantages of the invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the present invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  shows an SRAM bit cell circuit, in accordance with the prior art; 
         FIG. 1B  shows the SRAM bit cell of  FIG. 1A  with the inverters expanded to reveal their respective internal transistor configurations, in accordance with the prior art; 
         FIG. 2  shows a cross-coupled transistor configuration, in accordance with one embodiment of the present invention; 
         FIG. 3A  shows an example of gate electrode tracks defined within the restricted gate level layout architecture, in accordance with one embodiment of the present invention; 
         FIG. 3B  shows the exemplary restricted gate level layout architecture of  FIG. 3A  with a number of exemplary gate level features defined therein, in accordance with one embodiment of the present invention; 
         FIG. 4  shows diffusion and gate level layouts of a cross-coupled transistor configuration, in accordance with one embodiment of the present invention; 
         FIG. 5  shows a variation of the cross-coupled transistor configuration of  FIG. 4  in which the cross-coupled transistor configuration is defined on three gate electrode tracks with crossing gate electrode connections; 
         FIG. 6  shows a variation of the cross-coupled transistor configuration of  FIG. 4  in which the cross-coupled transistor configuration is defined on four gate electrode tracks with crossing gate electrode connections; 
         FIG. 7  shows a variation of the cross-coupled transistor configuration of  FIG. 4  in which the cross-coupled transistor configuration is defined on two gate electrode tracks without crossing gate electrode connections; 
         FIG. 8  shows a variation of the cross-coupled transistor configuration of  FIG. 4  in which the cross-coupled transistor configuration is defined on three gate electrode tracks without crossing gate electrode connections; 
         FIG. 9  shows a variation of the cross-coupled transistor configuration of  FIG. 4  in which the cross-coupled transistor configuration is defined on four gate electrode tracks without crossing gate electrode connections; 
         FIG. 10  shows a multi-level layout including a cross-coupled transistor configuration defined on three gate electrode tracks with crossing gate electrode connections, in accordance with one embodiment of the present invention; 
         FIG. 11  shows a multi-level layout including a cross-coupled transistor configuration defined on four gate electrode tracks with crossing gate electrode connections, in accordance with one embodiment of the present invention; 
         FIG. 12  shows a multi-level layout including a cross-coupled transistor configuration defined on two gate electrode tracks without crossing gate electrode connections, in accordance with one embodiment of the present invention; 
         FIG. 13  shows a multi-level layout including a cross-coupled transistor configuration defined on three gate electrode tracks without crossing gate electrode connections, in accordance with one embodiment of the present invention; 
         FIG. 14A  shows a generalized multiplexer circuit in which all four cross-coupled transistors are directly connected to the common node, in accordance with one embodiment of the present invention; 
         FIG. 14B  shows an exemplary implementation of the multiplexer circuit of  FIG. 14A  with a detailed view of the pull up logic, and the pull down logic, in accordance with one embodiment of the present invention; 
         FIG. 14C  shows a multi-level layout of the multiplexer circuit of  FIG. 14B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention; 
         FIG. 15A  shows the multiplexer circuit of  FIG. 14A  in which two cross-coupled transistors remain directly connected to the common node, and in which two cross-coupled transistors are positioned outside the pull up logic and pull down logic, respectively, relative to the common node, in accordance with one embodiment of the present invention; 
         FIG. 15B  shows an exemplary implementation of the multiplexer circuit of  FIG. 15A  with a detailed view of the pull up logic and the pull down logic, in accordance with one embodiment of the present invention; 
         FIG. 15C  shows a multi-level layout of the multiplexer circuit of  FIG. 15B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention; 
         FIG. 16A  shows a generalized multiplexer circuit in which the cross-coupled transistors are connected to form two transmission gates to the common node, in accordance with one embodiment of the present invention; 
         FIG. 16B  shows an exemplary implementation of the multiplexer circuit of  FIG. 16A  with a detailed view of the driving logic, in accordance with one embodiment of the present invention; 
         FIG. 16C  shows a multi-level layout of the multiplexer circuit of  FIG. 16B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention; 
         FIG. 17A  shows a generalized multiplexer circuit in which two transistors of the four cross-coupled transistors are connected to form a transmission gate to the common node, in accordance with one embodiment of the present invention; 
         FIG. 17B  shows an exemplary implementation of the multiplexer circuit of  FIG. 17A  with a detailed view of the driving logic, in accordance with one embodiment of the present invention; 
         FIG. 17C  shows a multi-level layout of the multiplexer circuit of  FIG. 17B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention; 
         FIG. 18A  shows a generalized latch circuit implemented using the cross-coupled transistor configuration, in accordance with one embodiment of the present invention; 
         FIG. 18B  shows an exemplary implementation of the latch circuit of  FIG. 18A  with a detailed view of the pull up driver logic, the pull down driver logic, the pull up feedback logic, and the pull down feedback logic, in accordance with one embodiment of the present invention; 
         FIG. 18C  shows a multi-level layout of the latch circuit of  FIG. 18B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention; 
         FIG. 19A  shows the latch circuit of  FIG. 18A  in which two cross-coupled transistors remain directly connected to the common node, and in which two cross-coupled transistors are positioned outside the pull up driver logic and pull down driver logic, respectively, relative to the common node, in accordance with one embodiment of the present invention; 
         FIG. 19B  shows an exemplary implementation of the latch circuit of  FIG. 19A  with a detailed view of the pull up driver logic, the pull down driver logic, the pull up feedback logic, and the pull down feedback logic, in accordance with one embodiment of the present invention; 
         FIG. 19C  shows a multi-level layout of the latch circuit of  FIG. 19B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention; 
         FIG. 20A  shows the latch circuit of  FIG. 18A  in which two cross-coupled transistors remain directly connected to the common node, and in which two cross-coupled transistors are positioned outside the pull up feedback logic and pull down feedback logic, respectively, relative to the common node, in accordance with one embodiment of the present invention; 
         FIG. 20B  shows an exemplary implementation of the latch circuit of  FIG. 20A  with a detailed view of the pull up driver logic, the pull down driver logic, the pull up feedback logic, and the pull down feedback logic, in accordance with one embodiment of the present invention; 
         FIG. 20C  shows a multi-level layout of the latch circuit of  FIG. 20B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention; 
         FIG. 21A  shows a generalized latch circuit in which cross-coupled transistors are connected to form two transmission gates to the common node, in accordance with one embodiment of the present invention; 
         FIG. 21B  shows an exemplary implementation of the latch circuit of  FIG. 21A  with a detailed view of the driving logic and the feedback logic, in accordance with one embodiment of the present invention; 
         FIG. 21C  shows a multi-level layout of the latch circuit of  FIG. 21B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention; 
         FIG. 22A  shows a generalized latch circuit in which two transistors of the four cross-coupled transistors are connected to form a transmission gate to the common node, in accordance with one embodiment of the present invention; 
         FIG. 22B  shows an exemplary implementation of the latch circuit of  FIG. 22A  with a detailed view of the driving logic, the pull up feedback logic, and the pull down feedback logic, in accordance with one embodiment of the present invention; 
         FIG. 22C  shows a multi-level layout of the latch circuit of  FIG. 22B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention; 
         FIG. 23  shows an embodiment in which two PMOS transistors of the cross-coupled transistors are respectively disposed over physically separated p-type diffusion regions, two NMOS transistors of the cross-coupled transistors are disposed over a common n-type diffusion region, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node; 
         FIG. 24  shows an embodiment in which two PMOS transistors of the cross-coupled transistors are disposed over a common p-type diffusion region, two NMOS transistors of the cross-coupled transistors are respectively disposed over physically separated n-type diffusion regions, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node; and 
         FIG. 25  shows an embodiment in which two PMOS transistors of the cross-coupled transistors are respectively disposed over physically separated p-type diffusion regions, two NMOS transistors of the cross-coupled transistors are respectively disposed over physically separated n-type diffusion regions, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node; 
         FIGS. 26-99, 150-157, and 168-172  illustrate various cross-coupled transistor layout embodiments in which two PMOS transistors of the cross-coupled transistors are disposed over a common p-type diffusion region, two NMOS transistors of the cross-coupled transistors are disposed over a common n-type diffusion region, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node; 
         FIGS. 45A-45B  show annotated versions of  FIG. 45 ; 
         FIGS. 51A-51B  show annotated versions of  FIG. 51 ; 
         FIGS. 59A-59B  show annotated versions of  FIG. 59 ; 
         FIGS. 68A-68C  show annotated versions of  FIG. 68 ; 
         FIGS. 156A-156B  show annotated versions of  FIG. 156 ; 
         FIGS. 157A-157B  show annotated versions of  FIG. 157 ; 
         FIGS. 170A-170B  show annotated versions of  FIG. 170 ; 
         FIGS. 103, 105, 112-149, 167, 184, and 186  illustrate various cross-coupled transistor layout embodiments in which two PMOS transistors of the cross-coupled transistors are respectively disposed over physically separated p-type diffusion regions, two NMOS transistors of the cross-coupled transistors are disposed over a common n-type diffusion region, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node; 
         FIGS. 158-166, 173-183, 185, and 187-191  illustrate various cross-coupled transistor layout embodiments in which two PMOS transistors of the cross-coupled transistors are respectively disposed over physically separated p-type diffusion regions, two NMOS transistors of the cross-coupled transistors are respectively disposed over physically separated n-type diffusion regions, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node; 
         FIGS. 100, 101, 102, 104, and 106-111  show exemplary cross-coupled transistor layouts in which the n-type and p-type diffusion regions of the cross-coupled transistors are shown to be electrically connected to a common node; 
         FIGS. 109A-109C  show annotated versions of  FIG. 109 ; 
         FIGS. 111A-111B  show annotated versions of  FIG. 111 ; and 
         FIG. 192  shows another exemplary cross-couple transistor layout in which the common diffusion node shared between the cross-coupled transistors  16601   p ,  16603   p ,  16605   p , and  16607   p  has one or more transistors defined thereover. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention. 
     SRAM Bit Cell Configuration: 
       FIG. 1A  shows an SRAM (Static Random Access Memory) bit cell circuit, in accordance with the prior art. The SRAM bit cell includes two cross-coupled inverters  106  and  102 . Specifically, an output  106 B of inverter  106  is connected to an input  102 A of inverter  102 , and an output  102 B of inverter  102  is connected to an input  106 A of inverter  106 . The SRAM bit cell further includes two NMOS pass transistors  100  and  104 . The NMOS pass transistor  100  is connected between a bit-line  103  and a node  109  corresponding to both the output  106 B of inverter  106  and the input  102 A of inverter  102 . The NMOS pass transistor  104  is connected between a bit-line  105  and a node  111  corresponding to both the output  102 B of inverter  102  and the input  106 A of inverter  106 . Also, the respective gates of NMOS pass transistors  100  and  104  are each connected to a word line  107 , which controls access to the SRAM bit cell through the NMOS pass transistors  100  and  104 . The SRAM bit cell requires bi-directional write, which means that when bit-line  103  is driven high, bit-line  105  is driven low, vice-versa. It should be understood by those skilled in the art that a logic state stored in the SRAM bit cell is maintained in a complementary manner by nodes  109  and  111 . 
       FIG. 1B  shows the SRAM bit cell of  FIG. 1A  with the inverters  106  and  102  expanded to reveal their respective internal transistor configurations, in accordance with the prior art. The inverter  106  include a PMOS transistor  115  and an NMOS transistor  113 . The respective gates of the PMOS and NMOS transistors  115 ,  113  are connected together to form the input  106 A of inverter  106 . Also, each of PMOS and NMOS transistors  115 ,  113  have one of their respective terminals connected together to form the output  106 B of inverter  106 . A remaining terminal of PMOS transistor  115  is connected to a power supply  117 . A remaining terminal of NMOS transistor  113  is connected to a ground potential  119 . Therefore, PMOS and NMOS transistors  115 ,  113  are activated in a complementary manner. When a high logic state is present at the input  106 A of the inverter  106 , the NMOS transistor  113  is turned on and the PMOS transistor  115  is turned off, thereby causing a low logic state to be generated at output  106 B of the inverter  106 . When a low logic state is present at the input  106 A of the inverter  106 , the NMOS transistor  113  is turned off and the PMOS transistor  115  is turned on, thereby causing a high logic state to be generated at output  106 B of the inverter  106 . 
     The inverter  102  is defined in an identical manner to inverter  106 . The inverter  102  include a PMOS transistor  121  and an NMOS transistor  123 . The respective gates of the PMOS and NMOS transistors  121 ,  123  are connected together to form the input  102 A of inverter  102 . Also, each of PMOS and NMOS transistors  121 ,  123  have one of their respective terminals connected together to form the output  102 B of inverter  102 . A remaining terminal of PMOS transistor  121  is connected to the power supply  117 . A remaining terminal of NMOS transistor  123  is connected to the ground potential  119 . Therefore, PMOS and NMOS transistors  121 ,  123  are activated in a complementary manner. When a high logic state is present at the input  102 A of the inverter  102 , the NMOS transistor  123  is turned on and the PMOS transistor  121  is turned off, thereby causing a low logic state to be generated at output  102 B of the inverter  102 . When a low logic state is present at the input  102 A of the inverter  102 , the NMOS transistor  123  is turned off and the PMOS transistor  121  is turned on, thereby causing a high logic state to be generated at output  102 B of the inverter  102 . 
     Cross-Coupled Transistor Configuration: 
       FIG. 2  shows a cross-coupled transistor configuration, in accordance with one embodiment of the present invention. The cross-coupled transistor configuration includes four transistors: a PMOS transistor  401 , an NMOS transistor  405 , a PMOS transistor  403 , and an NMOS transistor  407 . The PMOS transistor  401  has one terminal connected to pull up logic  209 A, and its other terminal connected to a common node  495 . The NMOS transistor  405  has one terminal connected to pull down logic  211 A, and its other terminal connected to the common node  495 . The PMOS transistor  403  has one terminal connected to pull up logic  209 B, and its other terminal connected to the common node  495 . The NMOS transistor  407  has one terminal connected to pull down logic  211 B, and its other terminal connected to the common node  495 . Respective gates of the PMOS transistor  401  and the NMOS transistor  407  are both connected to a gate node  491 . Respective gates of the NMOS transistor  405  and the PMOS transistor  403  are both connected to a gate node  493 . The gate nodes  491  and  493  are also referred to as control nodes  491  and  493 , respectively. Moreover, each of the common node  495 , the gate node  491 , and the gate node  493  can be referred to as an electrical connection  495 ,  491 ,  493 , respectively. 
     Based on the foregoing, the cross-coupled transistor configuration includes four transistors: 1) a first PMOS transistor, 2) a first NMOS transistor, 3) a second PMOS transistor, and 4) a second NMOS transistor. Furthermore, the cross-coupled transistor configuration includes three required electrical connections: 1) each of the four transistors has one of its terminals connected to a same common node, 2) gates of one PMOS transistor and one NMOS transistor are both connected to a first gate node, and 3) gates of the other PMOS transistor and the other NMOS transistor are both connected to a second gate node. 
     It should be understood that the cross-coupled transistor configuration of  FIG. 2  represents a basic configuration of cross-coupled transistors. In other embodiments, additional circuitry components can be connected to any node within the cross-coupled transistor configuration of  FIG. 2 . Moreover, in other embodiments, additional circuitry components can be inserted between any one or more of the cross-coupled transistors ( 401 ,  405 ,  403 ,  407 ) and the common node  495 , without departing from the cross-coupled transistor configuration of  FIG. 2 . 
     Difference Between SRAM Bit Cell and Cross-Coupled Transistor Configurations: 
     It should be understood that the SRAM bit cell of  FIGS. 1A-1B  does not include a cross-coupled transistor configuration. In particular, it should be understood that the cross-coupled “inverters”  106  and  102  within the SRAM bit cell neither represent nor infer a cross-coupled “transistor” configuration. As discussed above, the cross-coupled transistor configuration requires that each of the four transistors has one of its terminals electrically connected to the same common node. This does not occur in the SRAM bit cell. 
     With reference to the SRAM bit cell in  FIG. 1B , the terminals of PMOS transistor  115  and NMOS transistor  113  are connected together at node  109 , but the terminals of PMOS transistor  121  and NMOS transistor  123  are connected together at node  111 . More specifically, the terminals of PMOS transistor  115  and NMOS transistor  113  that are connected together at the output  106 B of the inverter are connected to the gates of each of PMOS transistor  121  and NMOS transistor  123 , and therefore are not connected to both of the terminals of PMOS transistor  121  and NMOS transistor  123 . Therefore, the SRAM bit cell does not include four transistors (two PMOS and two NMOS) that each have one of its terminals connected together at a same common node. Consequently, the SRAM bit cell does represent or include a cross-coupled transistor configuration, such as described with regard to  FIG. 2 . 
     Restricted Gate Level Layout Architecture: 
     The present invention implements a restricted gate level layout architecture within a portion of a semiconductor chip. For the gate level, a number of parallel virtual lines are defined to extend across the layout. These parallel virtual lines are referred to as gate electrode tracks, as they are used to index placement of gate electrodes of various transistors within the layout. In one embodiment, the parallel virtual lines which form the gate electrode tracks are defined by a perpendicular spacing therebetween equal to a specified gate electrode pitch. Therefore, placement of gate electrode segments on the gate electrode tracks corresponds to the specified gate electrode pitch. In another embodiment the gate electrode tracks are spaced at variable pitches greater than or equal to a specified gate electrode pitch. 
       FIG. 3A  shows an example of gate electrode tracks  301 A- 301 E defined within the restricted gate level layout architecture, in accordance with one embodiment of the present invention. Gate electrode tracks  301 A- 301 E are formed by parallel virtual lines that extend across the gate level layout of the chip, with a perpendicular spacing therebetween equal to a specified gate electrode pitch  307 . For illustrative purposes, complementary diffusion regions  303  and  305  are shown in  FIG. 3A . It should be understood that the diffusion regions  303  and  305  are defined in the diffusion level below the gate level. Also, it should be understood that the diffusion regions  303  and  305  are provided by way of example and in no way represent any limitation on diffusion region size, shape, and/or placement within the diffusion level relative to the restricted gate level layout architecture. 
     Within the restricted gate level layout architecture, a gate level feature layout channel is defined about a given gate electrode track so as to extend between gate electrode tracks adjacent to the given gate electrode track. For example, gate level feature layout channels  301 A-1 through  301 E-1 are defined about gate electrode tracks  301 A through  301 E, respectively. It should be understood that each gate electrode track has a corresponding gate level feature layout channel. Also, for gate electrode tracks positioned adjacent to an edge of a prescribed layout space, e.g., adjacent to a cell boundary, the corresponding gate level feature layout channel extends as if there were a virtual gate electrode track outside the prescribed layout space, as illustrated by gate level feature layout channels  301 A-1 and  301 E- 1 . It should be further understood that each gate level feature layout channel is defined to extend along an entire length of its corresponding gate electrode track. Thus, each gate level feature layout channel is defined to extend across the gate level layout within the portion of the chip to which the gate level layout is associated. 
     Within the restricted gate level layout architecture, gate level features associated with a given gate electrode track are defined within the gate level feature layout channel associated with the given gate electrode track. A contiguous gate level feature can include both a portion which defines a gate electrode of a transistor, and a portion that does not define a gate electrode of a transistor. Thus, a contiguous gate level feature can extend over both a diffusion region and a dielectric region of an underlying chip level. In one embodiment, each portion of a gate level feature that forms a gate electrode of a transistor is positioned to be substantially centered upon a given gate electrode track. Furthermore, in this embodiment, portions of the gate level feature that do not form a gate electrode of a transistor can be positioned within the gate level feature layout channel associated with the given gate electrode track. Therefore, a given gate level feature can be defined essentially anywhere within a given gate level feature layout channel, so long as gate electrode portions of the given gate level feature are centered upon the gate electrode track corresponding to the given gate level feature layout channel, and so long as the given gate level feature complies with design rule spacing requirements relative to other gate level features in adjacent gate level layout channels. Additionally, physical contact is prohibited between gate level features defined in gate level feature layout channels that are associated with adjacent gate electrode tracks. 
       FIG. 3B  shows the exemplary restricted gate level layout architecture of  FIG. 3A  with a number of exemplary gate level features  309 - 323  defined therein, in accordance with one embodiment of the present invention. The gate level feature  309  is defined within the gate level feature layout channel  301 A-1 associated with gate electrode track  301 A. The gate electrode portions of gate level feature  309  are substantially centered upon the gate electrode track  301 A. Also, the non-gate electrode portions of gate level feature  309  maintain design rule spacing requirements with gate level features  311  and  313  defined within adjacent gate level feature layout channel  301 B- 1 . Similarly, gate level features  311 - 323  are defined within their respective gate level feature layout channel, and have their gate electrode portions substantially centered upon the gate electrode track corresponding to their respective gate level feature layout channel. Also, it should be appreciated that each of gate level features  311 - 323  maintains design rule spacing requirements with gate level features defined within adjacent gate level feature layout channels, and avoids physical contact with any another gate level feature defined within adjacent gate level feature layout channels. 
     A gate electrode corresponds to a portion of a respective gate level feature that extends over a diffusion region, wherein the respective gate level feature is defined in its entirety within a gate level feature layout channel. Each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel. As illustrated by the example gate level feature layout channels  301 A-1 through  301 E-1 of  FIG. 3B , each gate level feature layout channel is associated with a given gate electrode track and corresponds to a layout region that extends along the given gate electrode track and perpendicularly outward in each opposing direction from the given gate electrode track to a closest of either an adjacent gate electrode track or a virtual gate electrode track outside a layout boundary. 
     Some gate level features may have one or more contact head portions defined at any number of locations along their length. A contact head portion of a given gate level feature is defined as a segment of the gate level feature having a height and a width of sufficient size to receive a gate contact structure, wherein “width” is defined across the substrate in a direction perpendicular to the gate electrode track of the given gate level feature, and wherein “height” is defined across the substrate in a direction parallel to the gate electrode track of the given gate level feature. It should be appreciated that a contact head of a gate level feature, when viewed from above, can be defined by essentially any layout shape, including a square or a rectangle. Also, depending on layout requirements and circuit design, a given contact head portion of a gate level feature may or may not have a gate contact defined thereabove. 
     A gate level of the various embodiments disclosed herein is defined as a restricted gate level, as discussed above. Some of the gate level features form gate electrodes of transistor devices. Others of the gate level features can form conductive segments extending between two points within the gate level. Also, others of the gate level features may be non-functional with respect to integrated circuit operation. It should be understood that the each of the gate level features, regardless of function, is defined to extend across the gate level within their respective gate level feature layout channels without physically contacting other gate level features defined with adjacent gate level feature layout channels. 
     In one embodiment, the gate level features are defined to provide a finite number of controlled layout shape-to-shape lithographic interactions which can be accurately predicted and optimized for in manufacturing and design processes. In this embodiment, the gate level features are defined to avoid layout shape-to-shape spatial relationships which would introduce adverse lithographic interaction within the layout that cannot be accurately predicted and mitigated with high probability. However, it should be understood that changes in direction of gate level features within their gate level layout channels are acceptable when corresponding lithographic interactions are predictable and manageable. 
     It should be understood that each of the gate level features, regardless of function, is defined such that no gate level feature along a given gate electrode track is configured to connect directly within the gate level to another gate level feature defined along a different gate electrode track without utilizing a non-gate level feature. Moreover, each connection between gate level features that are placed within different gate level layout channels associated with different gate electrode tracks is made through one or more non-gate level features, which may be defined in higher interconnect levels, i.e., through one or more interconnect levels above the gate level, or by way of local interconnect features at or below the gate level. 
     Cross-Coupled Transistor Layouts: 
     As discussed above, the cross-coupled transistor configuration includes four transistors (2 PMOS transistors and 2 NMOS transistors). In various embodiments of the present invention, gate electrodes defined in accordance with the restricted gate level layout architecture are respectively used to form the four transistors of a cross-coupled transistor configuration layout.  FIG. 4  shows diffusion and gate level layouts of a cross-coupled transistor configuration, in accordance with one embodiment of the present invention. The cross-coupled transistor layout of  FIG. 4  includes the first PMOS transistor  401  defined by a gate electrode  401 A extending along a gate electrode track  450  and over a p-type diffusion region  480 . The first NMOS transistor  407  is defined by a gate electrode  407 A extending along a gate electrode track  456  and over an n-type diffusion region  486 . The second PMOS transistor  403  is defined by a gate electrode  403 A extending along the gate electrode track  456  and over a p-type diffusion region  482 . The second NMOS transistor  405  is defined by a gate electrode  405 A extending along the gate electrode track  450  and over an n-type diffusion region  484 . 
     The gate electrodes  401 A and  407 A of the first PMOS transistor  401  and first NMOS transistor  407 , respectively, are electrically connected to the first gate node  491  so as to be exposed to a substantially equivalent gate electrode voltage. Similarly, the gate electrodes  403 A and  405 A of the second PMOS transistor  403  and second NMOS transistor  405 , respectively, are electrically connected to the second gate node  493  so as to be exposed to a substantially equivalent gate electrode voltage. Also, each of the four transistors  401 ,  403 ,  405 ,  407  has a respective diffusion terminal electrically connected to the common output node  495 . 
     The cross-coupled transistor layout can be implemented in a number of different ways within the restricted gate level layout architecture. In the exemplary embodiment of  FIG. 4 , the gate electrodes  401 A and  405 A of the first PMOS transistor  401  and second NMOS transistor  405  are positioned along the same gate electrode track  450 . Similarly, the gate electrodes  403 A and  407 A of the second PMOS transistor  403  and second NMOS transistor  407  are positioned along the same gate electrode track  456 . Thus, the particular embodiment of  FIG. 4  can be characterized as a cross-coupled transistor configuration defined on two gate electrode tracks with crossing gate electrode connections. 
       FIG. 5  shows a variation of the cross-coupled transistor configuration of  FIG. 4  in which the cross-coupled transistor configuration is defined on three gate electrode tracks with crossing gate electrode connections. Specifically, the gate electrode  401 A of the first PMOS transistor  401  is defined on the gate electrode track  450 . The gate electrode  403 A of the second PMOS transistor  403  is defined on the gate electrode track  456 . The gate electrode  407 A of the first NMOS transistor  407  is defined on a gate electrode track  456 . And, the gate electrode  405 A of the second NMOS transistor  405  is defined on a gate electrode track  448 . Thus, the particular embodiment of  FIG. 5  can be characterized as a cross-coupled transistor configuration defined on three gate electrode tracks with crossing gate electrode connections. 
       FIG. 6  shows a variation of the cross-coupled transistor configuration of  FIG. 4  in which the cross-coupled transistor configuration is defined on four gate electrode tracks with crossing gate electrode connections. Specifically, the gate electrode  401 A of the first PMOS transistor  401  is defined on the gate electrode track  450 . The gate electrode  403 A of the second PMOS transistor  403  is defined on the gate electrode track  456 . The gate electrode  407 A of the first NMOS transistor  407  is defined on a gate electrode track  458 . And, the gate electrode  405 A of the second NMOS transistor  405  is defined on a gate electrode track  454 . Thus, the particular embodiment of  FIG. 6  can be characterized as a cross-coupled transistor configuration defined on four gate electrode tracks with crossing gate electrode connections. 
       FIG. 7  shows a variation of the cross-coupled transistor configuration of  FIG. 4  in which the cross-coupled transistor configuration is defined on two gate electrode tracks without crossing gate electrode connections. Specifically, the gate electrode  401 A of the first PMOS transistor  401  is defined on the gate electrode track  450 . The gate electrode  407 A of the first NMOS transistor  407  is also defined on a gate electrode track  450 . The gate electrode  403 A of the second PMOS transistor  403  is defined on the gate electrode track  456 . And, the gate electrode  405 A of the second NMOS transistor  405  is also defined on a gate electrode track  456 . Thus, the particular embodiment of  FIG. 7  can be characterized as a cross-coupled transistor configuration defined on two gate electrode tracks without crossing gate electrode connections. 
       FIG. 8  shows a variation of the cross-coupled transistor configuration of  FIG. 4  in which the cross-coupled transistor configuration is defined on three gate electrode tracks without crossing gate electrode connections. Specifically, the gate electrode  401 A of the first PMOS transistor  401  is defined on the gate electrode track  450 . The gate electrode  407 A of the first NMOS transistor  407  is also defined on a gate electrode track  450 . The gate electrode  403 A of the second PMOS transistor  403  is defined on the gate electrode track  454 . And, the gate electrode  405 A of the second NMOS transistor  405  is defined on a gate electrode track  456 . Thus, the particular embodiment of  FIG. 8  can be characterized as a cross-coupled transistor configuration defined on three gate electrode tracks without crossing gate electrode connections. 
       FIG. 9  shows a variation of the cross-coupled transistor configuration of  FIG. 4  in which the cross-coupled transistor configuration is defined on four gate electrode tracks without crossing gate electrode connections. Specifically, the gate electrode  401 A of the first PMOS transistor  401  is defined on the gate electrode track  450 . The gate electrode  403 A of the second PMOS transistor  403  is defined on the gate electrode track  454 . The gate electrode  407 A of the first NMOS transistor  407  is defined on a gate electrode track  452 . And, the gate electrode  405 A of the second NMOS transistor  405  is defined on a gate electrode track  456 . Thus, the particular embodiment of  FIG. 9  can be characterized as a cross-coupled transistor configuration defined on four gate electrode tracks without crossing gate electrode connections. 
     It should be appreciated that although the cross-coupled transistors  401 ,  403 ,  405 ,  407  of  FIGS. 4-9  are depicted as having their own respective diffusion region  480 ,  482 ,  484 ,  486 , respectively, other embodiments may utilize a contiguous p-type diffusion region for PMOS transistors  401  and  403 , and/or utilize a contiguous n-type diffusion region for NMOS transistors  405  and  407 . Moreover, although the example layouts of  FIGS. 4-9  depict the p-type diffusion regions  480  and  482  in a vertically aligned position, it should be understood that the p-type diffusion regions  480  and  482  may not be vertically aligned in other embodiments. Similarly, although the example layouts of  FIGS. 4-9  depict the n-type diffusion regions  484  and  486  in a vertically aligned position, it should be understood that the n-type diffusion regions  484  and  486  may not be vertically aligned in other embodiments. 
     For example, the cross-coupled transistor layout of  FIG. 4  includes the first PMOS transistor  401  defined by the gate electrode  401 A extending along the gate electrode track  450  and over a first p-type diffusion region  480 . And, the second PMOS transistor  403  is defined by the gate electrode  403 A extending along the gate electrode track  456  and over a second p-type diffusion region  482 . The first NMOS transistor  407  is defined by the gate electrode  407 A extending along the gate electrode track  456  and over a first n-type diffusion region  486 . And, the second NMOS transistor  405  is defined by the gate electrode  405 A extending along the gate electrode track  450  and over a second n-type diffusion region  484 . 
     The gate electrode tracks  450  and  456  extend in a first parallel direction. At least a portion of the first p-type diffusion region  480  and at least a portion of the second p-type diffusion region  482  are formed over a first common line of extent that extends across the substrate perpendicular to the first parallel direction of the gate electrode tracks  450  and  456 . Additionally, at least a portion of the first n-type diffusion region  486  and at least a portion of the second n-type diffusion region  484  are formed over a second common line of extent that extends across the substrate perpendicular to the first parallel direction of the gate electrode tracks  450  and  456 . 
       FIG. 14C  shows that two PMOS transistors ( 401 A and  403 A) of the cross-coupled transistors are disposed over a common p-type diffusion region (PDIFF), two NMOS transistors ( 405 A and  407 A) of the cross-coupled transistors are disposed over a common n-type diffusion region (NDIFF), and the p-type (PDIFF) and n-type (NDIFF) diffusion regions associated with the cross-coupled transistors are electrically connected to a common node  495 . The gate electrodes of the cross-coupled transistors ( 401 A,  403 A,  405 A,  407 A) extend in a first parallel direction. At least a portion of a first p-type diffusion region associated with the first PMOS transistor  401 A and at least a portion of a second p-type diffusion region associated with the second PMOS transistor  403 A are formed over a first common line of extent that extends across the substrate perpendicular to the first parallel direction of the gate electrodes. Additionally, at least a portion of a first n-type diffusion region associated with the first NMOS transistor  405 A and at least a portion of a second n-type diffusion region associated with the second NMOS transistor  407 A are formed over a second common line of extent that extends across the substrate perpendicular to the first parallel direction of the gate electrodes. 
     In another embodiment, two PMOS transistors of the cross-coupled transistors are respectively disposed over physically separated p-type diffusion regions, two NMOS transistors of the cross-coupled transistors are disposed over a common n-type diffusion region, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node.  FIG. 23  illustrates a cross-coupled transistor layout embodiment in which two PMOS transistors ( 2301  and  2303 ) of the cross-coupled transistors are respectively disposed over physically separated p-type diffusion regions ( 2302  and  2304 ), two NMOS transistors ( 2305  and  2307 ) of the cross-coupled transistors are disposed over a common n-type diffusion region  2306 , and the p-type ( 2302 ,  2304 ) and n-type  2306  diffusion regions associated with the cross-coupled transistors are electrically connected to a common node  2309 . 
       FIG. 23  shows that the gate electrodes of the cross-coupled transistors ( 2301 ,  2303 ,  2305 ,  2307 ) extend in a first parallel direction  2311 .  FIG. 23  also shows that the first  2302  and second  2304  p-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction  2311  of the gate electrodes, such that no single line of extent that extends across the substrate in a direction  2313  perpendicular to the first parallel direction  2311  of the gate electrodes intersects both the first  2302  and second  2304  p-type diffusion regions. Also,  FIG. 23  shows that at least a portion of a first n-type diffusion region (part of  2306 ) associated with a first NMOS transistor  2305  and at least a portion of a second n-type diffusion region (part of  2306 ) associated with a second NMOS transistor  2307  are formed over a common line of extent that extends across the substrate in the direction  2313  perpendicular to the first parallel direction  2311  of the gate electrodes. 
     In another embodiment, two PMOS transistors of the cross-coupled transistors are disposed over a common p-type diffusion region, two NMOS transistors of the cross-coupled transistors are respectively disposed over physically separated n-type diffusion regions, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node.  FIG. 24  shows the cross-coupled transistor embodiment of  FIG. 23 , with the p-type ( 2302  and  2304 ) and n-type  2306  diffusion regions of  FIG. 23  reversed to n-type ( 2402  and  2404 ) and p-type  2406  diffusion regions, respectively.  FIG. 24  illustrates a cross-coupled transistor layout embodiment in which two PMOS transistors ( 2405  and  2407 ) of the cross-coupled transistors are disposed over a common p-type diffusion region  2406 , two NMOS transistors ( 2401  and  2403 ) of the cross-coupled transistors are respectively disposed over physically separated n-type diffusion regions ( 2402  and  2404 ), and the p-type  2406  and n-type ( 2402  and  2404 ) diffusion regions associated with the cross-coupled transistors are electrically connected to a common node  2409 . 
       FIG. 24  shows that the gate electrodes of the cross-coupled transistors ( 2401 ,  2403 ,  2405 ,  2407 ) extend in a first parallel direction  2411 .  FIG. 24  also shows that at least a portion of a first p-type diffusion region (part of  2406 ) associated with a first PMOS transistor  2405  and at least a portion of a second p-type diffusion region (part of  2406 ) associated with a second PMOS transistor  2407  are formed over a common line of extent that extends across the substrate in a direction  2413  perpendicular to the first parallel direction  2411  of the gate electrodes. Also,  FIG. 24  shows that the first  2402  and second  2404  n-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction  2411 , such that no single line of extent that extends across the substrate in the direction  2413  perpendicular to the first parallel direction  2411  of the gate electrodes intersects both the first  2402  and second  2404  n-type diffusion regions. 
     In yet another embodiment, two PMOS transistors of the cross-coupled transistors are respectively disposed over physically separated p-type diffusion regions, two NMOS transistors of the cross-coupled transistors are respectively disposed over physically separated n-type diffusion regions, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node.  FIGS. 25  shows a cross-coupled transistor layout embodiment in which two PMOS transistors ( 2501  and  2503 ) of the cross-coupled transistors are respectively disposed over physically separated p-type diffusion regions ( 2502  and  2504 ), two NMOS transistors ( 2505  and  2507 ) of the cross-coupled transistors are respectively disposed over physically separated n-type diffusion regions ( 2506  and  2508 ), and the p-type ( 2502  and  2504 ) and n-type ( 2506  and  2508 ) diffusion regions associated with the cross-coupled transistors are electrically connected to a common node  2509 . 
       FIG. 25  shows that the gate electrodes of the cross-coupled transistors ( 2501 ,  2503 ,  2505 ,  2507 ) extend in a first parallel direction  2511 .  FIG. 25  also shows that the first  2502  and second  2504  p-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction  2511 , such that no single line of extent that extends across the substrate in a direction  2513  perpendicular to the first parallel direction  2511  of the gate electrodes intersects both the first  2502  and second  2504  p-type diffusion regions. Also,  FIG. 25  shows that the first  2506  and second  2508  n-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction  2511 , such that no single line of extent that extends across the substrate in the direction  2513  perpendicular to the first parallel direction  2511  of the gate electrodes intersects both the first  2506  and second  2508  n-type diffusion regions. 
     In  FIGS. 4-9 , the gate electrode connections are electrically represented by lines  491  and  493 , and the common node electrical connection is represented by line  495 . It should be understood that in layout space each of the gate electrode electrical connections  491 ,  493 , and the common node electrical connection  495  can be structurally defined by a number of layout shapes extending through multiple chip levels.  FIGS. 10-13  show examples of how the gate electrode electrical connections  491 ,  493 , and the common node electrical connection  495  can be defined in different embodiments. It should be understood that the example layouts of  FIGS. 10-13  are provided by way of example and in no way represent an exhaustive set of possible multi-level connections that can be utilized for the gate electrode electrical connections  491 ,  493 , and the common node electrical connection  495 . 
       FIG. 10  shows a multi-level layout including a cross-coupled transistor configuration defined on three gate electrode tracks with crossing gate electrode connections, in accordance with one embodiment of the present invention. The layout of  FIG. 10  represents an exemplary implementation of the cross-coupled transistor embodiment of  FIG. 5 . The electrical connection  491  between the gate electrode  401 A of the first PMOS transistor  401  and the gate electrode  407 A of the first NMOS transistor  407  is formed by a multi-level connection that includes a gate contact  1001 , a (two-dimensional) metal-1 structure  1003 , and a gate contact  1005 . The electrical connection  493  between the gate electrode  403 A of the second PMOS transistor  403  and the gate electrode  405 A of the second NMOS transistor  405  is formed by a multi-level connection that includes a gate contact  1007 , a (two-dimensional) metal-1 structure  1009 , and a gate contact  1011 . The output node electrical connection  495  is formed by a multi-level connection that includes a diffusion contact  1013 , a (two-dimensional) metal-1 structure  1015 , a diffusion contact  1017 , and a diffusion contact  1019 . 
       FIG. 11  shows a multi-level layout including a cross-coupled transistor configuration defined on four gate electrode tracks with crossing gate electrode connections, in accordance with one embodiment of the present invention. The layout of  FIG. 11  represents an exemplary implementation of the cross-coupled transistor embodiment of  FIG. 6 . The electrical connection  491  between the gate electrode  401 A of the first PMOS transistor  401  and the gate electrode  407 A of the first NMOS transistor  407  is formed by a multi-level connection that includes a gate contact  1101 , a (two-dimensional) metal-1 structure  1103 , and a gate contact  1105 . The electrical connection  493  between the gate electrode  403 A of the second PMOS transistor  403  and the gate electrode  405 A of the second NMOS transistor  405  is formed by a multi-level connection that includes a gate contact  1107 , a (one-dimensional) metal-1 structure  1109 , a via  1111 , a (one-dimensional) metal-2 structure  1113 , a via  1115 , a (one-dimensional) metal-1 structure  1117 , and a gate contact  1119 . The output node electrical connection  495  is formed by a multi-level connection that includes a diffusion contact  1121 , a (two-dimensional) metal-1 structure  1123 , a diffusion contact  1125 , and a diffusion contact  1127 . 
       FIG. 12  shows a multi-level layout including a cross-coupled transistor configuration defined on two gate electrode tracks without crossing gate electrode connections, in accordance with one embodiment of the present invention. The layout of  FIG. 12  represents an exemplary implementation of the cross-coupled transistor embodiment of  FIG. 7 . The gate electrodes  401 A and  407 A of the first PMOS transistor  401  and first NMOS transistor  407 , respectively, are formed by a contiguous gate level structure placed on the gate electrode track  450 . Therefore, the electrical connection  491  between the gate electrodes  401 A and  407 A is made directly within the gate level along the single gate electrode track  450 . Similarly, the gate electrodes  403 A and  405 A of the second PMOS transistor  403  and second NMOS transistor  405 , respectively, are formed by a contiguous gate level structure placed on the gate electrode track  456 . Therefore, the electrical connection  493  between the gate electrodes  403 A and  405 A is made directly within the gate level along the single gate electrode track  456 . The output node electrical connection  495  is formed by a multi-level connection that includes a diffusion contact  1205 , a (one-dimensional) metal-1 structure  1207 , and a diffusion contact  1209 . 
     Further with regard to  FIG. 12 , it should be noted that when the gate electrodes  401 A and  407 A of the first PMOS transistor  401  and first NMOS transistor  407 , respectively, are formed by a contiguous gate level structure, and when the gate electrodes  403 A and  405 A of the second PMOS transistor  403  and second NMOS transistor  405 , respectively, are formed by a contiguous gate level structure, the corresponding cross-coupled transistor layout may include electrical connections between diffusion regions associated with the four cross-coupled transistors  401 ,  407 ,  403 ,  405 , that cross in layout space without electrical communication therebetween. For example, diffusion region  1220  of PMOS transistor  403  is electrically connected to diffusion region  1222  of NMOS transistor  407  as indicated by electrical connection  1224 , and diffusion region  1230  of PMOS transistor  401  is electrically connected to diffusion region  1232  of NMOS transistor  405  as indicated by electrical connection  1234 , wherein electrical connections  1224  and  1234  cross in layout space without electrical communication therebetween. 
       FIG. 13  shows a multi-level layout including a cross-coupled transistor configuration defined on three gate electrode tracks without crossing gate electrode connections, in accordance with one embodiment of the present invention. The layout of  FIG. 13  represents an exemplary implementation of the cross-coupled transistor embodiment of  FIG. 8 . The gate electrodes  401 A and  407 A of the first PMOS transistor  401  and first NMOS transistor  407 , respectively, are formed by a contiguous gate level structure placed on the gate electrode track  450 . Therefore, the electrical connection  491  between the gate electrodes  401 A and  407 A is made directly within the gate level along the single gate electrode track  450 . The electrical connection  493  between the gate electrode  403 A of the second PMOS transistor  403  and the gate electrode  405 A of the second NMOS transistor  405  is formed by a multi-level connection that includes a gate contact  1303 , a (one-dimensional) metal-1 structure  1305 , and a gate contact  1307 . The output node electrical connection  495  is formed by a multi-level connection that includes a diffusion contact  1311 , a (one-dimensional) metal-1 structure  1313 , and a diffusion contact  1315 . 
     In one embodiment, electrical connection of the diffusion regions of the cross-coupled transistors to the common node  495  can be made using one or more local interconnect conductors defined at or below the gate level itself. This embodiment may also combine local interconnect conductors with conductors in higher levels (above the gate level) by way of contacts and/or vias to make the electrical connection of the diffusion regions of the cross-coupled transistors to the common node  495 . Additionally, in various embodiments, conductive paths used to electrically connect the diffusion regions of the cross-coupled transistors to the common node  495  can be defined to traverse over essentially any area of the chip as required to accommodate a routing solution for the chip. 
     Also, it should be appreciated that because the n-type and p-type diffusion regions are physically separate, and because the p-type diffusion regions for the two PMOS transistors of the cross-coupled transistors can be physically separate, and because the n-type diffusion regions for the two NMOS transistors of the cross-coupled transistors can be physically separate, it is possible in various embodiments to have each of the four cross-coupled transistors disposed at arbitrary locations in the layout relative to each other. Therefore, unless necessitated by electrical performance or other layout influencing conditions, it is not required that the four cross-coupled transistors be located within a prescribed proximity to each other in the layout. Although, location of the cross-coupled transistors within a prescribed proximity to each other is not precluded, and may be desirable in certain circuit layouts. 
     In the exemplary embodiments disclosed herein, it should be understood that diffusion regions are not restricted in size. In other words, any given diffusion region can be sized in an arbitrary manner as required to satisfy electrical and/or layout requirements. Additionally, any given diffusion region can be shaped in an arbitrary manner as required to satisfy electrical and/or layout requirements. Also, it should be understood that the four transistors of the cross-coupled transistor configuration, as defined in accordance with the restricted gate level layout architecture, are not required to be the same size. In different embodiments, the four transistors of the cross-coupled transistor configuration can either vary in size (transistor width or transistor gate length) or have the same size, depending on the applicable electrical and/or layout requirements. 
     Additionally, it should be understood that the four transistors of the cross-coupled transistor configuration are not required to be placed in close proximity to each, although they may be closely placed in some embodiments. More specifically, because connections between the transistors of the cross-coupled transistor configuration can be made by routing through as least one higher interconnect level, there is freedom in placement of the four transistors of the cross-coupled transistor configuration relative to each other. Although, it should be understood that a proximity of the four transistors of the cross-coupled transistor configuration may be governed in certain embodiments by electrical and/or layout optimization requirements. 
     It should be appreciated that the cross-coupled transistor configurations and corresponding layouts implemented using the restricted gate level layout architecture, as described with regard to  FIGS. 2-13 , and/or variants thereof, can be used to form many different electrical circuits. For example, a portion of a modern semiconductor chip is likely to include a number of multiplexer circuits and/or latch circuits. Such multiplexer and/or latch circuits can be defined using cross-coupled transistor configurations and corresponding layouts based on the restricted gate level layout architecture, as disclosed herein. Example multiplexer embodiments implemented using the restricted gate level layout architecture and corresponding cross-coupled transistor configurations are described with regard to  FIGS. 14A-17C . Example latch embodiments implemented using the restricted gate level layout architecture and corresponding cross-coupled transistor configurations are described with regard to  FIGS. 18A-22C . It should be understood that the multiplexer and latch embodiments described with regard to  FIGS. 14A-22C  are provided by way of example and do not represent an exhaustive set of possible multiplexer and latch embodiments. 
     Example Multiplexer Embodiments 
       FIG. 14A  shows a generalized multiplexer circuit in which all four cross-coupled transistors  401 ,  405 ,  403 ,  407  are directly connected to the common node  495 , in accordance with one embodiment of the present invention. As previously discussed, gates of the first PMOS transistor  401  and first NMOS transistor  407  are electrically connected, as shown by electrical connection  491 . Also, gates of the second PMOS transistor  403  and second NMOS transistor  405  are electrically connected, as shown by electrical connection  493 . Pull up logic  1401  is electrically connected to the first PMOS transistor  401  at a terminal opposite the common node  495 . Pull down logic  1403  is electrically connected to the second NMOS transistor  405  at a terminal opposite the common node  495 . Also, pull up logic  1405  is electrically connected to the second PMOS transistor  403  at a terminal opposite the common node  495 . Pull down logic  1407  is electrically connected to the first NMOS transistor  407  at a terminal opposite the common node  495 . 
       FIG. 14B  shows an exemplary implementation of the multiplexer circuit of  FIG. 14A  with a detailed view of the pull up logic  1401  and  1405 , and the pull down logic  1403  and  1407 , in accordance with one embodiment of the present invention. The pull up logic  1401  is defined by a PMOS transistor  1401 A connected between a power supply (VDD) and a terminal  1411  of the first PMOS transistor  401  opposite the common node  495 . The pull down logic  1403  is defined by an NMOS transistor  1403 A connected between a ground potential (GND) and a terminal  1413  of the second NMOS transistor  405  opposite the common node  495 . Respective gates of the PMOS transistor  1401 A and NMOS transistor  1403 A are connected together at a node  1415 . The pull up logic  1405  is defined by a PMOS transistor  1405 A connected between the power supply (VDD) and a terminal  1417  of the second PMOS transistor  403  opposite the common node  495 . The pull down logic  1407  is defined by an NMOS transistor  1407 A connected between a ground potential (GND) and a terminal  1419  of the first NMOS transistor  407  opposite the common node  495 . Respective gates of the PMOS transistor  1405 A and NMOS transistor  1407 A are connected together at a node  1421 . It should be understood that the implementations of pull up logic  1401 ,  1405  and pull down logic  1403 ,  1407  as shown in  FIG. 14B  are exemplary. In other embodiments, logic different than that shown in  FIG. 14B  can be used to implement the pull up logic  1401 ,  1405  and the pull down logic  1403 ,  1407 . 
       FIG. 14C  shows a multi-level layout of the multiplexer circuit of  FIG. 14B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention. The electrical connection  491  between the gate electrode  401 A of the first PMOS transistor  401  and the gate electrode  407 A of the first NMOS transistor  407  is formed by a multi-level connection that includes a gate contact  1445 , a (two-dimensional) metal-1 structure  1447 , and a gate contact  1449 . The electrical connection  493  between the gate electrode  403 A of the second PMOS transistor  403  and the gate electrode  405 A of the second NMOS transistor  405  is formed by a multi-level connection that includes a gate contact  1431 , a (one-dimensional) metal-1 structure  1433 , a via  1435 , a (one-dimensional) metal-2 structure  1436 , a via  1437 , a (one-dimensional) metal-1 structure  1439 , and a gate contact  1441 . The common node electrical connection  495  is formed by a multi-level connection that includes a diffusion contact  1451 , a (one-dimensional) metal-1 structure  1453 , a via  1455 , a (one-dimensional) metal-2 structure  1457 , a via  1459 , a (one-dimensional) metal-1 structure  1461 , and a diffusion contact  1463 . Respective gates of the PMOS transistor  1401 A and NMOS transistor  1403 A are connected to the node  1415  by a gate contact  1443 . Also, respective gates of the PMOS transistor  1405 A and NMOS transistor  1407 A are connected to the node  1421  by a gate contact  1465 . 
       FIG. 15A  shows the multiplexer circuit of  FIG. 14A  in which the two cross-coupled transistors  401  and  405  remain directly connected to the common node  495 , and in which the two cross-coupled transistors  403  and  407  are positioned outside the pull up logic  1405  and pull down logic  1407 , respectively, relative to the common node  495 , in accordance with one embodiment of the present invention. Pull up logic  1405  is electrically connected between the second PMOS transistor  403  and the common node  495 . Pull down logic  1407  is electrically connected between the first NMOS transistor  407  and the common node  495 . With the exception of repositioning the PMOS/NMOS transistors  403 / 407  outside of their pull up/down logic  1405 / 1407  relative to the common node  495 , the circuit of  FIG. 15A  is the same as the circuit of  FIG. 14A . 
       FIG. 15B  shows an exemplary implementation of the multiplexer circuit of  FIG. 15A  with a detailed view of the pull up logic  1401  and  1405 , and the pull down logic  1403  and  1407 , in accordance with one embodiment of the present invention. As previously discussed with regard to  FIG. 14B , the pull up logic  1401  is defined by the PMOS transistor  1401 A connected between VDD and the terminal  1411  of the first PMOS transistor  401  opposite the common node  495 . Also, the pull down logic  1403  is defined by NMOS transistor  1403 A connected between GND and the terminal  1413  of the second NMOS transistor  405  opposite the common node  495 . Respective gates of the PMOS transistor  1401 A and NMOS transistor  1403 A are connected together at the node  1415 . The pull up logic  1405  is defined by the PMOS transistor  1405 A connected between the second PMOS transistor  403  and the common node  495 . The pull down logic  1407  is defined by the NMOS transistor  1407 A connected between the first NMOS transistor  407  and the common node  495 . Respective gates of the PMOS transistor  1405 A and NMOS transistor  1407 A are connected together at the node  1421 . It should be understood that the implementations of pull up logic  1401 ,  1405  and pull down logic  1403 ,  1407  as shown in  FIG. 15B  are exemplary. In other embodiments, logic different than that shown in  FIG. 15B  can be used to implement the pull up logic  1401 ,  1405  and the pull down logic  1403 ,  1407 . 
       FIG. 15C  shows a multi-level layout of the multiplexer circuit of  FIG. 15B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention. The electrical connection  491  between the gate electrode  401 A of the first PMOS transistor  401  and the gate electrode  407 A of the first NMOS transistor  407  is formed by a multi-level connection that includes a gate contact  1501 , a (one-dimensional) metal-1 structure  1503 , a via  1505 , a (one-dimensional) metal-2 structure  1507 , a via  1509 , a (one-dimensional) metal-1 structure  1511 , and a gate contact  1513 . The electrical connection  493  between the gate electrode  403 A of the second PMOS transistor  403  and the gate electrode  405 A of the second NMOS transistor  405  is formed by a multi-level connection that includes a gate contact  1515 , a (two-dimensional) metal-1 structure  1517 , and a gate contact  1519 . The common node electrical connection  495  is formed by a multi-level connection that includes a diffusion contact  1521 , a (one-dimensional) metal-1 structure  1523 , a via  1525 , a (one-dimensional) metal-2 structure  1527 , a via  1529 , a (one-dimensional) metal-1 structure  1531 , and a diffusion contact  1533 . Respective gates of the PMOS transistor  1401 A and NMOS transistor  1403 A are connected to the node  1415  by a gate contact  1535 . Also, respective gates of the PMOS transistor  1405 A and NMOS transistor  1407 A are connected to the node  1421  by a gate contact  1539 . 
       FIG. 16A  shows a generalized multiplexer circuit in which the cross-coupled transistors ( 401 ,  403 ,  405 ,  407 ) are connected to form two transmission gates  1602 ,  1604  to the common node  495 , in accordance with one embodiment of the present invention. As previously discussed, gates of the first PMOS transistor  401  and first NMOS transistor  407  are electrically connected, as shown by electrical connection  491 . Also, gates of the second PMOS transistor  403  and second NMOS transistor  405  are electrically connected, as shown by electrical connection  493 . The first PMOS transistor  401  and second NMOS transistor  405  are connected to form a first transmission gate  1602  to the common node  495 . The second PMOS transistor  403  and first NMOS transistor  407  are connected to form a second transmission gate  1604  to the common node  495 . Driving logic  1601  is electrically connected to both the first PMOS transistor  401  and second NMOS transistor  405  at a terminal opposite the common node  495 . Driving logic  1603  is electrically connected to both the second PMOS transistor  403  and first NMOS transistor  407  at a terminal opposite the common node  495 . 
       FIG. 16B  shows an exemplary implementation of the multiplexer circuit of  FIG. 16A  with a detailed view of the driving logic  1601  and  1603 , in accordance with one embodiment of the present invention. In the embodiment of  FIG. 16B , the driving logic  1601  is defined by an inverter  1601 A and, the driving logic  1603  is defined by an inverter  1603 A. However, it should be understood that in other embodiments, the driving logic  1601  and  1603  can be defined by any logic function, such as a two input NOR gate, a two input NAND gate, AND-OR logic, OR-AND logic, among others, by way of example. 
       FIG. 16C  shows a multi-level layout of the multiplexer circuit of  FIG. 16B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention. The electrical connection  491  between the gate electrode  401 A of the first PMOS transistor  401  and the gate electrode  407 A of the first NMOS transistor  407  is formed by a multi-level connection that includes a gate contact  1619 , a (two-dimensional) metal-1 structure  1621 , and a gate contact  1623 . The electrical connection  493  between the gate electrode  403 A of the second PMOS transistor  403  and the gate electrode  405 A of the second NMOS transistor  405  is formed by a multi-level connection that includes a gate contact  1605 , a (one-dimensional) metal-1 structure  1607 , a via  1609 , a (one-dimensional) metal-2 structure  1611 , a via  1613 , a (one-dimensional) metal-1 structure  1615 , and a gate contact  1617 . The common node electrical connection  495  is formed by a multi-level connection that includes a diffusion contact  1625 , a (one-dimensional) metal-1 structure  1627 , a via  1629 , a (one-dimensional) metal-2 structure  1631 , a via  1633 , a (one-dimensional) metal-1 structure  1635 , and a diffusion contact  1637 . Transistors which form the inverter  1601 A are shown within the region bounded by the dashed line  1601 AL. Transistors which form the inverter  1603 A are shown within the region bounded by the dashed line  1603 AL. 
       FIG. 17A  shows a generalized multiplexer circuit in which two transistors ( 403 ,  407 ) of the four cross-coupled transistors are connected to form a transmission gate  1702  to the common node  495 , in accordance with one embodiment of the present invention. As previously discussed, gates of the first PMOS transistor  401  and first NMOS transistor  407  are electrically connected, as shown by electrical connection  491 . Also, gates of the second PMOS transistor  403  and second NMOS transistor  405  are electrically connected, as shown by electrical connection  493 . The second PMOS transistor  403  and first NMOS transistor  407  are connected to form the transmission gate  1702  to the common node  495 . Driving logic  1701  is electrically connected to both the second PMOS transistor  403  and first NMOS transistor  407  at a terminal opposite the common node  495 . Pull up driving logic  1703  is electrically connected to the first PMOS transistor  401  at a terminal opposite the common node  495 . Also, pull down driving logic  1705  is electrically connected to the second NMOS transistor  405  at a terminal opposite the common node  495 . 
       FIG. 17B  shows an exemplary implementation of the multiplexer circuit of  FIG. 17A  with a detailed view of the driving logic  1701 ,  1703 , and  1705 , in accordance with one embodiment of the present invention. The driving logic  1701  is defined by an inverter  1701 A. The pull up driving logic  1703  is defined by a PMOS transistor  1703 A connected between VDD and the first PMOS transistor  401 . The pull down driving logic  1705  is defined by an NMOS transistor  1705 A connected between GND and the second NMOS transistor  405 . Respective gates of the PMOS transistor  1703 A and NMOS transistor  1705 A are connected together at the node  1707 . It should be understood that the implementations of driving logic  1701 ,  1703 , and  1705 , as shown in  FIG. 17B  are exemplary. In other embodiments, logic different than that shown in  FIG. 17B  can be used to implement the driving logic  1701 ,  1703 , and  1705 . 
       FIG. 17C  shows a multi-level layout of the multiplexer circuit of  FIG. 17B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention. The electrical connection  491  between the gate electrode  401 A of the first PMOS transistor  401  and the gate electrode  407 A of the first NMOS transistor  407  is formed by a multi-level connection that includes a gate contact  1723 , a (two-dimensional) metal-1 structure  1725 , and a gate contact  1727 . The electrical connection  493  between the gate electrode  403 A of the second PMOS transistor  403  and the gate electrode  405 A of the second NMOS transistor  405  is formed by a multi-level connection that includes a gate contact  1709 , a (one-dimensional) metal-1 structure  1711 , a via  1713 , a (one-dimensional) metal-2 structure  1715 , a via  1717 , a (one-dimensional) metal-1 structure  1719 , and a gate contact  1721 . The common node electrical connection  495  is formed by a multi-level connection that includes a diffusion contact  1729 , a (one-dimensional) metal-1 structure  1731 , a via  1733 , a (one-dimensional) metal-2 structure  1735 , a via  1737 , a (one-dimensional) metal-1 structure  1739 , and a diffusion contact  1741 . Transistors which form the inverter  1701 A are shown within the region bounded by the dashed line  1701 AL. Respective gates of the PMOS transistor  1703 A and NMOS transistor  1705 A are connected to the node  1707  by a gate contact  1743 . 
     Example Latch Embodiments 
       FIG. 18A  shows a generalized latch circuit implemented using the cross-coupled transistor configuration, in accordance with one embodiment of the present invention. The gates of the first PMOS transistor  401  and first NMOS transistor  407  are electrically connected, as shown by electrical connection  491 . The gates of the second PMOS transistor  403  and second NMOS transistor  405  are electrically connected, as shown by electrical connection  493 . Each of the four cross-coupled transistors are electrically connected to the common node  495 . It should be understood that the common node  495  serves as a storage node in the latch circuit. Pull up driver logic  1805  is electrically connected to the second PMOS transistor  403  at a terminal opposite the common node  495 . Pull down driver logic  1807  is electrically connected to the first NMOS transistor  407  at a terminal opposite the common node  495 . Pull up feedback logic  1809  is electrically connected to the first PMOS transistor  401  at a terminal opposite the common node  495 . Pull down feedback logic  1811  is electrically connected to the second NMOS transistor  405  at a terminal opposite the common node  495 . Additionally, the common node  495  is connected to an input of an inverter  1801 . An output of the inverter  1801  is electrically connected to a feedback node  1803 . It should be understood that in other embodiments the inverter  1801  can be replaced by any logic function, such as a two input NOR gate, a two input NAND gate, among others, or any complex logic function. 
       FIG. 18B  shows an exemplary implementation of the latch circuit of  FIG. 18A  with a detailed view of the pull up driver logic  1805 , the pull down driver logic  1807 , the pull up feedback logic  1809 , and the pull down feedback logic  1811 , in accordance with one embodiment of the present invention. The pull up driver logic  1805  is defined by a PMOS transistor  1805 A connected between VDD and the second PMOS transistor  403  opposite the common node  495 . The pull down driver logic  1807  is defined by an NMOS transistor  1807 A connected between GND and the first NMOS transistor  407  opposite the common node  495 . Respective gates of the PMOS transistor  1805 A and NMOS transistor  1807 A are connected together at a node  1804 . The pull up feedback logic  1809  is defined by a PMOS transistor  1809 A connected between VDD and the first PMOS transistor  401  opposite the common node  495 . The pull down feedback logic  1811  is defined by an NMOS transistor  1811 A connected between GND and the second NMOS transistor  405  opposite the common node  495 . Respective gates of the PMOS transistor  1809 A and NMOS transistor  1811 A are connected together at the feedback node  1803 . It should be understood that the implementations of pull up driver logic  1805 , pull down driver logic  1807 , pull up feedback logic  1809 , and pull down feedback logic  1811  as shown in  FIG. 18B  are exemplary. In other embodiments, logic different than that shown in  FIG. 18B  can be used to implement the pull up driver logic  1805 , the pull down driver logic  1807 , the pull up feedback logic  1809 , and the pull down feedback logic  1811 . 
       FIG. 18C  shows a multi-level layout of the latch circuit of  FIG. 18B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention. The electrical connection  491  between the gate electrode  401 A of the first PMOS transistor  401  and the gate electrode  407 A of the first NMOS transistor  407  is formed by a multi-level connection that includes a gate contact  1813 , a (one-dimensional) metal-1 structure  1815 , a via  1817 , a (one-dimensional) metal-2 structure  1819 , a via  1821 , a (one-dimensional) metal-1 structure  1823 , and a gate contact  1825 . The electrical connection  493  between the gate electrode  403 A of the second PMOS transistor  403  and the gate electrode  405 A of the second NMOS transistor  405  is formed by a multi-level connection that includes a gate contact  1827 , a (two-dimensional) metal-1 structure  1829 , and a gate contact  1831 . The common node electrical connection  495  is formed by a multi-level connection that includes a diffusion contact  1833 , a (one-dimensional) metal-1 structure  1835 , a via  1837 , a (one-dimensional) metal-2 structure  1839 , a via  1841 , a (two-dimensional) metal-1 structure  1843 , and a diffusion contact  1845 . Transistors which form the inverter  1801  are shown within the region bounded by the dashed line  1801 L. 
       FIG. 19A  shows the latch circuit of  FIG. 18A  in which the two cross-coupled transistors  401  and  405  remain directly connected to the output node  495 , and in which the two cross-coupled transistors  403  and  407  are positioned outside the pull up driver logic  1805  and pull down driver logic  1807 , respectively, relative to the common node  495 , in accordance with one embodiment of the present invention. Pull up driver logic  1805  is electrically connected between the second PMOS transistor  403  and the common node  495 . Pull down driver logic  1807  is electrically connected between the first NMOS transistor  407  and the common node  495 . With the exception of repositioning the PMOS/NMOS transistors  403 / 407  outside of their pull up/down driver logic  1805 / 1807  relative to the common node  495 , the circuit of  FIG. 19A  is the same as the circuit of  FIG. 18A . 
       FIG. 19B  shows an exemplary implementation of the latch circuit of  FIG. 19A  with a detailed view of the pull up driver logic  1805 , pull down driver logic  1807 , pull up feedback logic  1809 , and pull down feedback logic  1811 , in accordance with one embodiment of the present invention. As previously discussed with regard to  FIG. 18B , the pull up feedback logic  1809  is defined by the PMOS transistor  1809 A connected between VDD and the first PMOS transistor  401  opposite the common node  495 . Also, the pull down feedback logic  1811  is defined by NMOS transistor  1811 A connected between GND and the second NMOS transistor  405  opposite the common node  495 . Respective gates of the PMOS transistor  1809 A and NMOS transistor  1811 A are connected together at the feedback node  1803 . The pull up driver logic  1805  is defined by the PMOS transistor  1805 A connected between the second PMOS transistor  403  and the common node  495 . The pull down driver logic  1807  is defined by the NMOS transistor  1807 A connected between the first NMOS transistor  407  and the common node  495 . Respective gates of the PMOS transistor  1805 A and NMOS transistor  1807 A are connected together at the node  1804 . It should be understood that the implementations of pull up driver logic  1805 , pull down driver logic  1807 , pull up feedback logic  1809 , and pull down feedback logic  1811  as shown in  FIG. 19B  are exemplary. In other embodiments, logic different than that shown in  FIG. 19B  can be used to implement the pull up driver logic  1805 , the pull down driver logic  1807 , the pull up feedback logic  1809 , and the pull down feedback logic  1811 . 
       FIG. 19C  shows a multi-level layout of the latch circuit of  FIG. 19B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention. The electrical connection  491  between the gate electrode  401 A of the first PMOS transistor  401  and the gate electrode  407 A of the first NMOS transistor  407  is formed by a multi-level connection that includes a gate contact  1901 , a (one-dimensional) metal-1 structure  1903 , a via  1905 , a (one-dimensional) metal-2 structure  1907 , a via  1909 , a (one-dimensional) metal-1 structure  1911 , and a gate contact  1913 . The electrical connection  493  between the gate electrode  403 A of the second PMOS transistor  403  and the gate electrode  405 A of the second NMOS transistor  405  is formed by a multi-level connection that includes a gate contact  1915 , a (two-dimensional) metal-1 structure  1917 , and a gate contact  1919 . The common node electrical connection  495  is formed by a multi-level connection that includes a diffusion contact  1921 , a (one-dimensional) metal-1 structure  1923 , a via  1925 , a (one-dimensional) metal-2 structure  1927 , a via  1929 , a (two-dimensional) metal-1 structure  1931 , and a diffusion contact  1933 . Transistors which form the inverter  1801  are shown within the region bounded by the dashed line  1801 L. 
       FIG. 20A  shows the latch circuit of  FIG. 18A  in which the two cross-coupled transistors  403  and  407  remain directly connected to the output node  495 , and in which the two cross-coupled transistors  401  and  405  are positioned outside the pull up feedback logic  1809  and pull down feedback logic  1811 , respectively, relative to the common node  495 , in accordance with one embodiment of the present invention. Pull up feedback logic  1809  is electrically connected between the first PMOS transistor  401  and the common node  495 . Pull down feedback logic  1811  is electrically connected between the second NMOS transistor  405  and the common node  495 . With the exception of repositioning the PMOS/NMOS transistors  401 / 405  outside of their pull up/down feedback logic  1809 / 1811  relative to the common node  495 , the circuit of  FIG. 20A  is the same as the circuit of  FIG. 18A . 
       FIG. 20B  shows an exemplary implementation of the latch circuit of  FIG. 20A  with a detailed view of the pull up driver logic  1805 , pull down driver logic  1807 , pull up feedback logic  1809 , and pull down feedback logic  1811 , in accordance with one embodiment of the present invention. The pull up feedback logic  1809  is defined by the PMOS transistor  1809 A connected between the first PMOS transistor  401  and the common node  495 . Also, the pull down feedback logic  1811  is defined by NMOS transistor  1811 A connected between the second NMOS transistor  405  and the common node  495 . Respective gates of the PMOS transistor  1809 A and NMOS transistor  1811 A are connected together at the feedback node  1803 . The pull up driver logic  1805  is defined by the PMOS transistor  1805 A connected between VDD and the second PMOS transistor  403 . The pull down driver logic  1807  is defined by the NMOS transistor  1807 A connected between GND and the first NMOS transistor  407 . Respective gates of the PMOS transistor  1805 A and NMOS transistor  1807 A are connected together at the node  1804 . It should be understood that the implementations of pull up driver logic  1805 , pull down driver logic  1807 , pull up feedback logic  1809 , and pull down feedback logic  1811  as shown in  FIG. 20B  are exemplary. In other embodiments, logic different than that shown in  FIG. 20B  can be used to implement the pull up driver logic  1805 , the pull down driver logic  1807 , the pull up feedback logic  1809 , and the pull down feedback logic  1811 . 
       FIG. 20C  shows a multi-level layout of the latch circuit of  FIG. 20B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention. The electrical connection  491  between the gate electrode  401 A of the first PMOS transistor  401  and the gate electrode  407 A of the first NMOS transistor  407  is formed by a multi-level connection that includes a gate contact  2001 , a (one-dimensional) metal-1 structure  2003 , a via  2005 , a (one-dimensional) metal-2 structure  2007 , a via  2009 , a (one-dimensional) metal-1 structure  2011 , and a gate contact  2013 . The electrical connection  493  between the gate electrode  403 A of the second PMOS transistor  403  and the gate electrode  405 A of the second NMOS transistor  405  is formed by a multi-level connection that includes a gate contact  2015 , a (one-dimensional) metal-1 structure  2017 , and a gate contact  2019 . The common node electrical connection  495  is formed by a multi-level connection that includes a diffusion contact  2021 , a (two-dimensional) metal-1 structure  2023 , and a diffusion contact  2025 . Transistors which form the inverter  1801  are shown within the region bounded by the dashed line  1801 L. 
       FIG. 21A  shows a generalized latch circuit in which the cross-coupled transistors ( 401 ,  403 ,  405 ,  407 ) are connected to form two transmission gates  2103 ,  2105  to the common node  495 , in accordance with one embodiment of the present invention. As previously discussed, gates of the first PMOS transistor  401  and first NMOS transistor  407  are electrically connected, as shown by electrical connection  491 . Also, gates of the second PMOS transistor  403  and second NMOS transistor  405  are electrically connected, as shown by electrical connection  493 . The first PMOS transistor  401  and second NMOS transistor  405  are connected to form a first transmission gate  2103  to the common node  495 . The second PMOS transistor  403  and first NMOS transistor  407  are connected to form a second transmission gate  2105  to the common node  495 . Feedback logic  2109  is electrically connected to both the first PMOS transistor  401  and second NMOS transistor  405  at a terminal opposite the common node  495 . Driving logic  2107  is electrically connected to both the second PMOS transistor  403  and first NMOS transistor  407  at a terminal opposite the common node  495 . Additionally, the common node  495  is connected to the input of the inverter  1801 . The output of the inverter  1801  is electrically connected to a feedback node  2101 . It should be understood that in other embodiments the inverter  1801  can be replaced by any logic function, such as a two input NOR gate, a two input NAND gate, among others, or any complex logic function. 
       FIG. 21B  shows an exemplary implementation of the latch circuit of  FIG. 21A  with a detailed view of the driving logic  2107  and feedback logic  2109 , in accordance with one embodiment of the present invention. The driving logic  2107  is defined by an inverter  2107 A. Similarly, the feedback logic  2109  is defined by an inverter  2109 A. It should be understood that in other embodiments, the driving logic  2107  and/or  2109  can be defined by logic other than an inverter. 
       FIG. 21C  shows a multi-level layout of the latch circuit of  FIG. 21B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention. The electrical connection  491  between the gate electrode  401 A of the first PMOS transistor  401  and the gate electrode  407 A of the first NMOS transistor  407  is formed by a multi-level connection that includes a gate contact  2111 , a (one-dimensional) metal-1 structure  2113 , a via  2115 , a (one-dimensional) metal-2 structure  2117 , a via  2119 , a (one-dimensional) metal-1 structure  2121 , and a gate contact  2123 . The electrical connection  493  between the gate electrode  403 A of the second PMOS transistor  403  and the gate electrode  405 A of the second NMOS transistor  405  is formed by a multi-level connection that includes a gate contact  2125 , a (two-dimensional) metal-1 structure  2127 , and a gate contact  2129 . The common node electrical connection  495  is formed by a multi-level connection that includes a diffusion contact  2131 , a (one-dimensional) metal-1 structure  2133 , a via  2135 , a (one-dimensional) metal-2 structure  2137 , a via  2139 , a (two-dimensional) metal-1 structure  2141 , and a diffusion contact  2143 . Transistors which form the inverter  2107 A are shown within the region bounded by the dashed line  2107 AL. Transistors which form the inverter  2109 A are shown within the region bounded by the dashed line  2109 AL. Transistors which form the inverter  1801  are shown within the region bounded by the dashed line  1801 L. 
       FIG. 22A  shows a generalized latch circuit in which two transistors ( 403 ,  407 ) of the four cross-coupled transistors are connected to form a transmission gate  2105  to the common node  495 , in accordance with one embodiment of the present invention. As previously discussed, gates of the first PMOS transistor  401  and first NMOS transistor  407  are electrically connected, as shown by electrical connection  491 . Also, gates of the second PMOS transistor  403  and second NMOS transistor  405  are electrically connected, as shown by electrical connection  493 . The second PMOS transistor  403  and first NMOS transistor  407  are connected to form the transmission gate  2105  to the common node  495 . Driving logic  2201  is electrically connected to both the second PMOS transistor  403  and first NMOS transistor  407  at a terminal opposite the common node  495 . Pull up feedback logic  2203  is electrically connected to the first PMOS transistor  401  at a terminal opposite the common node  495 . Also, pull down feedback logic  2205  is electrically connected to the second NMOS transistor  405  at a terminal opposite the common node  495 . 
       FIG. 22B  shows an exemplary implementation of the latch circuit of  FIG. 22A  with a detailed view of the driving logic  2201 , the pull up feedback logic  2203 , and the pull down feedback logic  2205 , in accordance with one embodiment of the present invention. The driving logic  2201  is defined by an inverter  2201 A. The pull up feedback logic  2203  is defined by a PMOS transistor  2203 A connected between VDD and the first PMOS transistor  401 . The pull down feedback logic  2205  is defined by an NMOS transistor  2205 A connected between GND and the second NMOS transistor  405 . Respective gates of the PMOS transistor  2203 A and NMOS transistor  2205 A are connected together at the feedback node  2101 . It should be understood that in other embodiments, the driving logic  2201  can be defined by logic other than an inverter. Also, it should be understood that in other embodiments, the pull up feedback logic  2203  and/or pull down feedback logic  2205  can be defined logic different than what is shown in  FIG. 22B . 
       FIG. 22C  shows a multi-level layout of the latch circuit of  FIG. 22B  implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention. The electrical connection  491  between the gate electrode  401 A of the first PMOS transistor  401  and the gate electrode  407 A of the first NMOS transistor  407  is formed by a multi-level connection that includes a gate contact  2207 , a (one-dimensional) metal-1 structure  2209 , a via  2211 , a (one-dimensional) metal-2 structure  2213 , a via  2215 , a (one-dimensional) metal-1 structure  2217 , and a gate contact  2219 . The electrical connection  493  between the gate electrode  403 A of the second PMOS transistor  403  and the gate electrode  405 A of the second NMOS transistor  405  is formed by a multi-level connection that includes a gate contact  2221 , a (two-dimensional) metal-1 structure  2223 , and a gate contact  2225 . The common node electrical connection  495  is formed by a multi-level connection that includes a diffusion contact  2227 , a (one-dimensional) metal-1 structure  2229 , a via  2231 , a (one-dimensional) metal-2 structure  2233 , a via  2235 , a (two-dimensional) metal-1 structure  2237 , and a diffusion contact  2239 . Transistors which form the inverter  2201 A are shown within the region bounded by the dashed line  2201 AL. Transistors which form the inverter  1801  are shown within the region bounded by the dashed line  1801 L. 
     Exemplary Embodiments: 
     In one embodiment, a cross-coupled transistor configuration is defined within a semiconductor chip. This embodiment is illustrated in part with regard to  FIG. 2 . In this embodiment, a first P channel transistor ( 401 ) is defined to include a first gate electrode ( 401 A) defined in a gate level of the chip. Also, a first N channel transistor ( 407 ) is defined to include a second gate electrode ( 407 A) defined in the gate level of the chip. The second gate electrode ( 407 A) of the first N channel transistor ( 407 ) is electrically connected to the first gate electrode ( 401 A) of the first P channel transistor ( 401 ). Further, a second P channel transistor ( 403 ) is defined to include a third gate electrode ( 403 A) defined in the gate level of a chip. Also, a second N channel transistor ( 405 ) is defined to include a fourth gate electrode ( 405 A) defined in the gate level of the chip. The fourth gate electrode ( 405 A) of the second N channel transistor ( 405 ) is electrically connected to the third gate electrode ( 403 A) of the second P channel transistor ( 403 ). Additionally, each of the first P channel transistor ( 401 ), first N channel transistor ( 407 ), second P channel transistor ( 403 ), and second N channel transistor ( 405 ) has a respective diffusion terminal electrically connected to a common node ( 495 ). 
     It should be understood that in some embodiments, one or more of the first P channel transistor ( 401 ), the first N channel transistor ( 407 ), the second P channel transistor ( 403 ), and the second N channel transistor ( 405 ) can be respectively implemented by a number of transistors electrically connected in parallel. In this instance, the transistors that are electrically connected in parallel can be considered as one device corresponding to either of the first P channel transistor ( 401 ), the first N channel transistor ( 407 ), the second P channel transistor ( 403 ), and the second N channel transistor ( 405 ). It should be understood that electrical connection of multiple transistors in parallel to form a given transistor of the cross-coupled transistor configuration can be utilized to achieve a desired drive strength for the given transistor. 
     In one embodiment, each of the first ( 401 A), second ( 407 A), third ( 403 A), and fourth ( 405 A) gate electrodes is defined to extend along any of a number of gate electrode tracks, such as described with regard to  FIG. 3 . The number of gate electrode tracks extend across the gate level of the chip in a parallel orientation with respect to each other. Also, it should be understood that each of the first ( 401 A), second ( 407 A), third ( 403 A), and fourth ( 405 A) gate electrodes corresponds to a portion of a respective gate level feature defined within a gate level feature layout channel. Each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel. Each gate level feature layout channel is associated with a given gate electrode track and corresponds to a layout region that extends along the given gate electrode track and perpendicularly outward in each opposing direction from the given gate electrode track to a closest of either an adjacent gate electrode track or a virtual gate electrode track outside a layout boundary, such as described with regard to  FIG. 3B . 
     In various implementations of the above-described embodiment, such as in the exemplary layouts of  FIGS. 10, 11, 14C, 15C, 16C, 17C, 18C, 19C, 20C, 21C, 22C , the second gate electrode ( 407 A) is electrically connected to the first gate electrode ( 401 A) through at least one electrical conductor defined within any chip level other than the gate level. And, the fourth gate electrode ( 405 A) is electrically connected to the third gate electrode ( 403 A) through at least one electrical conductor defined within any chip level other than the gate level. 
     In various implementations of the above-described embodiment, such as in the exemplary layout of  FIG. 13 , both the second gate electrode ( 407 A) and the first gate electrode ( 401 A) are formed from a single gate level feature that is defined within a same gate level feature layout channel that extends along a single gate electrode track over both a p type diffusion region and an n type diffusion region. And, the fourth gate electrode ( 405 A) is electrically connected to the third gate electrode ( 403 A) through at least one electrical conductor defined within any chip level other than the gate level. 
     In various implementations of the above-described embodiment, such as in the exemplary layouts of  FIG. 12 , both the second gate electrode ( 407 A) and the first gate electrode ( 401 A) are formed from a first gate level feature that is defined within a first gate level feature layout channel that extends along a first gate electrode track over both a p type diffusion region and an n type diffusion region. And, both the fourth gate electrode ( 405 A) and the third gate electrode ( 403 A) are formed from a second gate level feature that is defined within a second gate level feature layout channel that extends along a second gate electrode track over both a p type diffusion region and an n type diffusion region. 
     In one embodiment, the above-described gate electrode cross-coupled transistor configuration is used to implement a multiplexer having no transmission gates. This embodiment is illustrated in part with regard to  FIGS. 14-15 . In this embodiment, a first configuration of pull-up logic ( 1401 ) is electrically connected to the first P channel transistor ( 401 ), a first configuration of pull-down logic ( 1407 ) electrically connected to the first N channel transistor ( 407 ), a second configuration of pull-up logic ( 1405 ) electrically connected to the second P channel transistor ( 403 ), and a second configuration of pull-down logic ( 1403 ) electrically connected to the second N channel transistor ( 405 ). 
     In the particular embodiments of  FIGS. 14B and 15B , the first configuration of pull-up logic ( 1401 ) is defined by a third P channel transistor ( 1401 A), and the second configuration of pull-down logic ( 1403 ) is defined by a third N channel transistor ( 1403 A). Respective gates of the third P channel transistor ( 1401 A) and third N channel transistor ( 1403 A) are electrically connected together so as to receive a substantially equivalent electrical signal. Moreover, the first configuration of pull-down logic ( 1407 ) is defined by a fourth N channel transistor ( 1407 A), and the second configuration of pull-up logic ( 1405 ) is defined by a fourth P channel transistor ( 1405 A). Respective gates of the fourth P channel transistor ( 1405 A) and fourth N channel transistor ( 1407 A) are electrically connected together so as to receive a substantially equivalent electrical signal. 
     In one embodiment, the above-described gate electrode cross-coupled transistor configuration is used to implement a multiplexer having one transmission gate. This embodiment is illustrated in part with regard to  FIG. 17 . In this embodiment, a first configuration of pull-up logic ( 1703 ) is electrically connected to the first P channel transistor ( 401 ), a first configuration of pull-down logic ( 1705 ) electrically connected to the second N channel transistor ( 405 ), and mux driving logic ( 1701 ) is electrically connected to both the second P channel transistor ( 403 ) and the first N channel transistor ( 407 ). 
     In the exemplary embodiment of  FIG. 17B , the first configuration of pull-up logic ( 1703 ) is defined by a third P channel transistor ( 1703 A), and the first configuration of pull-down logic ( 1705 ) is defined by a third N channel transistor ( 1705 A). Respective gates of the third P channel transistor ( 1703 A) and third N channel transistor ( 1705 A) are electrically connected together so as to receive a substantially equivalent electrical signal. Also, the mux driving logic ( 1701 ) is defined by an inverter ( 1701 A). 
     In one embodiment, the above-described gate electrode cross-coupled transistor configuration is used to implement a latch having no transmission gates. This embodiment is illustrated in part with regard to  FIGS. 18-20 . In this embodiment, pull-up driver logic ( 1805 ) is electrically connected to the second P channel transistor ( 403 ), pull-down driver logic ( 1807 ) is electrically connected to the first N channel transistor ( 407 ), pull-up feedback logic ( 1809 ) is electrically connected to the first P channel transistor ( 401 ), and pull-down feedback logic ( 1811 ) is electrically connected to the second N channel transistor ( 405 ). Also, the latch includes an inverter ( 1801 ) having an input connected to the common node ( 495 ) and an output connected to a feedback node ( 1803 ). Each of the pull-up feedback logic ( 1809 ) and pull-down feedback logic ( 1811 ) is connected to the feedback node ( 1803 ). 
     In the exemplary embodiments of  FIGS. 18B, 19B, and 20B , the pull-up driver logic ( 1805 ) is defined by a third P channel transistor ( 1805 A), and the pull-down driver logic ( 1807 ) is defined by a third N channel transistor ( 1807 A). Respective gates of the third P channel transistor ( 1805 A) and third N channel transistor ( 1807 A) are electrically connected together so as to receive a substantially equivalent electrical signal. Additionally, the pull-up feedback logic ( 1809 ) is defined by a fourth P channel transistor ( 1809 A), and the pull-down feedback logic ( 1811 ) is defined by a fourth N channel transistor ( 1811 A). Respective gates of the fourth P channel transistor ( 1809 A) and fourth N channel transistor ( 1811 A) are electrically connected together at the feedback node ( 1803 ). 
     In one embodiment, the above-described gate electrode cross-coupled transistor configuration is used to implement a latch having two transmission gates. This embodiment is illustrated in part with regard to  FIG. 21 . In this embodiment, driving logic ( 2107 ) is electrically connected to both the second P channel transistor ( 403 ) and the first N channel transistor ( 407 ). Also, feedback logic ( 2109 ) is electrically connected to both the first P channel transistor ( 401 ) and the second N channel transistor ( 405 ). The latch further includes a first inverter ( 1801 ) having an input connected to the common node ( 495 ) and an output connected to a feedback node ( 2101 ). The feedback logic ( 2109 ) is electrically connected to the feedback node ( 2101 ). In the exemplary embodiment of  FIG. 21B , the driving logic ( 2107 ) is defined by a second inverter ( 2107 A), and the feedback logic ( 2109 ) is defined by a third inverter ( 2109 A). 
     In one embodiment, the above-described gate electrode cross-coupled transistor configuration is used to implement a latch having one transmission gate. This embodiment is illustrated in part with regard to  FIG. 22 . In this embodiment, driving logic ( 2201 ) is electrically connected to both the second P channel transistor ( 403 ) and the first N channel transistor ( 407 ). Also, pull up feedback logic ( 2203 ) is electrically connected to the first P channel transistor ( 401 ), and pull down feedback logic ( 2205 ) electrically connected to the second N channel transistor ( 405 ). The latch further includes a first inverter ( 1801 ) having an input connected to the common node ( 495 ) and an output connected to a feedback node ( 2101 ). Both the pull up feedback logic ( 2203 ) and pull down feedback logic ( 2205 ) are electrically connected to the feedback node ( 2101 ). In the exemplary embodiment of  FIG. 22B , the driving logic ( 2201 ) is defined by a second inverter ( 2201 A). Also, the pull up feedback logic ( 2203 ) is defined by a third P channel transistor ( 2203 A) electrically connected between the first P channel transistor ( 401 ) and the feedback node ( 2101 ). The pull down feedback logic ( 2205 ) is defined by a third N channel transistor ( 2205 A) electrically connected between the second N channel transistor ( 405 ) and the feedback node ( 2101 ). 
     In one embodiment, cross-coupled transistors devices are defined and connected to form part of an integrated circuit within a semiconductor chip (“chip” hereafter). The chip includes a number of levels within which different features are defined to form the integrated circuit and cross-coupled transistors therein. The chip includes a substrate within which a number of diffusion regions are formed. The chip also includes a gate level in which a number of gate electrodes are formed. The chip further includes a number of interconnect levels successively defined above the gate level. A dielectric material is used to electrically separate a given level from its vertically adjacent levels. A number of contact features are defined to extend vertically through the chip to connect gate electrode features and diffusion regions, respectively, to various interconnect level features. Also, a number of via features are defined to extend vertically through the chip to connect various interconnect level features. 
     The gate level of the various embodiments disclosed herein is defined as a linear gate level and includes a number of commonly oriented linear gate level features. Some of the linear gate level features form gate electrodes of transistor devices. Others of the linear gate level features can form conductive segments extending between two points within the gate level. Also, others of the linear gate level features may be non-functional with respect to integrated circuit operation. It should be understood that the each of the linear gate level features, regardless of function, is defined to extend across the gate level in a common direction and to be devoid of a substantial change in direction along its length. Therefore, each of the gate level features is defined to be parallel to each other when viewed from a perspective perpendicular to the gate level. 
     It should be understood that each of the linear gate electrode features, regardless of function, is defined such that no linear gate electrode feature along a given line of extent is configured to connect directly within the gate electrode level to another linear gate electrode feature defined along another parallel line of extent, without utilizing a non-gate electrode feature. Moreover, each connection between linear gate electrode features that are placed on different, yet parallel, lines of extent is made through one or more non-gate electrode features, which may be defined in higher interconnect level(s), i.e., through one or more interconnect level(s) above the gate electrode level, or by way of local interconnect features within the linear gate level. In one embodiment, the linear gate electrode features are placed according to a virtual grid or virtual grate. However, it should be understood that in other embodiments the linear gate electrode features, although oriented to have a common direction of extent, are placed without regard to a virtual grid or virtual grate. 
     Additionally, it should be understood that while each linear gate electrode feature is defined to be devoid of a substantial change in direction along its line of extent, each linear gate electrode feature may have one or more contact head portion(s) defined at any number of location(s) along its length. A contact head portion of a given linear gate electrode feature is defined as a segment of the linear gate electrode feature having a different width than a gate portion of the linear gate electrode feature, i.e., than a portion of the linear gate electrode feature that extends over a diffusion region, wherein “width” is defined across the substrate in a direction perpendicular to the line of extent of the given linear gate electrode feature. It should be appreciated that a contact head of linear gate electrode feature, when viewed from above, can be defined by essentially any rectangular layout shape, including a square and a rectangle. Also, depending on layout requirements and circuit design, a given contact head portion of a linear gate electrode feature may or may not have a gate contact defined thereabove. 
     In one embodiment, a substantial change in direction of a linear gate level feature exists when the width of the linear gate level feature at any point thereon changes by more than 50% of the nominal width of the linear gate level feature along its entire length. In another embodiment, a substantial change in direction of a linear gate level feature exists when the width of the linear gate level feature changes from any first location on the linear gate level feature to any second location on the linear gate level feature by more that 50% of the linear gate level feature width at the first location. Therefore, it should be appreciated that the use of non-linear-shaped gate level features is specifically avoided, wherein a non-linear-shaped gate level feature includes one or more significant bends within a plane of the gate level. 
     Each of the linear gate level features has a width defined perpendicular to its direction of extent across the gate level. In one embodiment, the various gate level features can be defined to have different widths. In another embodiment, the various gate level features can be defined to have the same width. Also, a center-to-center spacing between adjacent linear gate level features, as measured perpendicular to their direction of extent across the gate level, is referred to as gate pitch. In one embodiment, a uniform gate pitch is used. However, in another embodiment, the gate pitch can vary across the gate level. It should be understood that linear gate level feature width and pitch specifications can be established for a portion of the chip and can be different for separate portions of the chip, wherein the portion of the chip may be of any size and shape. 
     Various embodiments are disclosed herein for cross-coupled transistor layouts defined using the linear gate level as described above. Each cross-coupled transistor layout embodiment includes four cross-coupled transistors, wherein each of these four cross-coupled transistors is defined in part by a respective linear gate electrode feature, and wherein the linear gate electrode features of the cross-coupled transistors are oriented to extend across the layout in a parallel relationship to each other. 
     Also, in each cross-coupled transistor layout, each of the gate electrodes of the four cross-coupled transistors is associated with, i.e., electrically interfaced with, a respective diffusion region. The diffusion regions associated with the gate electrodes of the cross-coupled transistors are electrically connected to a common node. In various embodiments, connection of the cross-coupled transistor&#39;s diffusion regions to the common node can be made in many different ways. 
     For example, in one embodiment, two PMOS transistors of the cross-coupled transistors are disposed over a common p-type diffusion region, two NMOS transistors of the cross-coupled transistors are disposed over a common n-type diffusion region, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node.  FIGS. 26-99, 150-157, and 168-172  illustrate various cross-coupled transistor layout embodiments in which two PMOS transistors of the cross-coupled transistors are disposed over a common p-type diffusion region, two NMOS transistors of the cross-coupled transistors are disposed over a common n-type diffusion region, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node. It should be understood that although  FIGS. 26-99  do not explicitly show an electrical connection of the n-type and p-type diffusion regions of the cross-coupled transistors to a common node, this common node connection between the n-type and p-type diffusion regions of the cross-coupled transistors is present in a full version of the exemplary layouts. 
     In another embodiment, two PMOS transistors of the cross-coupled transistors are respectively disposed over physically separated p-type diffusion regions, two NMOS transistors of the cross-coupled transistors are disposed over a common n-type diffusion region, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node.  FIGS. 103, 105, 112-149, 167, 184, and 186  illustrate various cross-coupled transistor layout embodiments in which two PMOS transistors of the cross-coupled transistors are respectively disposed over physically separated p-type diffusion regions, two NMOS transistors of the cross-coupled transistors are disposed over a common n-type diffusion region, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node. 
     In another embodiment, two PMOS transistors of the cross-coupled transistors are disposed over a common p-type diffusion region, two NMOS transistors of the cross-coupled transistors are respectively disposed over physically separated n-type diffusion regions, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node.  FIG. 100  as shown and each of  FIGS. 103, 105, 112-149, 167, 184, and 186  with the p-type and n-type diffusion regions reversed to n-type and p-type, respectively, illustrate various cross-coupled transistor layout embodiments in which two PMOS transistors of the cross-coupled transistors are disposed over a common p-type diffusion region, two NMOS transistors of the cross-coupled transistors are respectively disposed over physically separated n-type diffusion regions, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node. 
     In yet another embodiment, two PMOS transistors of the cross-coupled transistors are respectively disposed over physically separated p-type diffusion regions, two NMOS transistors of the cross-coupled transistors are respectively disposed over physically separated n-type diffusion regions, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node.  FIGS. 158-166, 173-183, 185, and 187-191  illustrate various cross-coupled transistor layout embodiments in which two PMOS transistors of the cross-coupled transistors are respectively disposed over physically separated p-type diffusion regions, two NMOS transistors of the cross-coupled transistors are respectively disposed over physically separated n-type diffusion regions, and the p-type and n-type diffusion regions associated with the cross-coupled transistors are electrically connected to a common node. 
     It should be understood that the electrical connection of the various p-type and n-type diffusion regions associated with the cross-coupled transistors to the common node can be made using electrical conductors defined within any level of the chip and within any number of levels of the chip, by way of contact and/or vias, so as to accommodate essentially any cross-coupled layout configuration defined in accordance with the linear gate level restrictions. In one embodiment, electrical connection of the diffusion regions of the cross-coupled transistors to the common node can be made using one or more local interconnect conductors defined within the gate level itself. This embodiment may also combine local interconnect conductors with conductors in higher levels (above the linear gate level) by way of contacts and/or vias to make the electrical connection of the diffusion regions of the cross-coupled transistors to the common node. Additionally, in various embodiments, conductive paths used to electrically connect the diffusion regions of the cross-coupled transistors to the common node can be defined to traverse over essentially any area of the chip as required to accommodate a routing solution for the chip. 
     Also, it should be appreciated that because the n-type and p-type diffusion regions are physically separate, and because the p-type diffusion regions for the two PMOS transistors of the cross-coupled transistors can be physically separate, and because the n-type diffusion regions for the two NMOS transistors of the cross-coupled transistors can be physically separate, it is possible in various embodiments to have each of the four cross-coupled transistors disposed at arbitrary locations in the layout relative to each other. Therefore, unless necessitated by electrical performance or other layout influencing conditions, it is not required that the four cross-coupled transistors be located within a prescribed proximity to each other in the layout. Although, location of the cross-coupled transistors within a prescribed proximity to each other is not precluded, and may be desirable in certain circuit layouts. 
       FIG. 26  is an illustration showing an exemplary cross-coupled transistor layout, in accordance with one embodiment of the present invention. The cross-couple layout includes four transistors  102   p ,  104   p ,  106   p ,  108   p . Transistors  102   p ,  106   p  are defined over a first diffusion region  110   p . Transistors  108   p ,  104   p  are defined over a second diffusion region  112   p . In one embodiment, the first diffusion region  110   p  is defined such that transistors  102   p  and  106   p  are NMOS transistors, and the second diffusion region  112   p  is defined such that transistors  104   p  and  108   p  are PMOS transistors. In another embodiment, the first diffusion region  110   p  is defined such that transistors  102   p  and  106   p  are PMOS transistors, and the second diffusion region  112   p  is defined such that transistors  104   p  and  108   p  are NMOS transistors. Additionally, the separation distance  114   p  between the first and second diffusion regions  110   p ,  112   p  can vary depending on the requirements of the layout and the area required for connection of the cross-coupled transistors between the first and second diffusion regions  110   p ,  112   p.    
     In the exemplary embodiments disclosed herein, it should be understood that diffusion regions are not restricted in size. In other words, any given diffusion region can be sized in an arbitrary manner as required to satisfy electrical and/or layout requirements. Additionally, any given diffusion region can be shaped in an arbitrary manner as required to satisfy electrical and/or layout requirements. Additionally, as discussed above, in various embodiments a cross-coupled transistor configuration can utilize physically separate n-channel diffusion regions and/or physically separate p-channel diffusion regions. More specifically, the two N-MOS transistors of the cross-coupled transistor configuration can utilize physically separate n-channel diffusion regions, and/or the two P-MOS transistors of the cross-coupled transistor configuration can utilize physically separate p-channel diffusion regions. 
     Also, it should be understood that the four transistors of the cross-coupled transistor configuration, as defined in accordance with the linear gate level, are not required to be the same size. In different embodiments, the four transistors of the cross-coupled transistor configuration can either vary in size (transistor width or transistor gate length) or have the same size, depending on the applicable electrical and/or layout requirements. Additionally, it should be understood that the four transistors of the cross-coupled transistor configuration are not required to be placed in close proximity to each, although they may be closely placed in some embodiments. More specifically, because connections between the transistors of the cross-coupled transistor configuration can be made by routing through as least one higher interconnect level, there is freedom in placement of the four transistors of the cross-coupled transistor configuration relative to each other. Although, it should be understood that a proximity of the four transistors of the cross-coupled transistor configuration may be governed in certain embodiments by electrical and/or layout optimization requirements. 
     The layout of  FIG. 26  utilizes a linear gate level as described above. Specifically, each of linear gate level features  116 Ap- 116 Fp, regardless of function, is defined to extend across the gate level in a common direction and to be devoid of a substantial change in direction along its length. Linear gate level features  116 Bp,  116 Fp,  116 Cp, and  116 Ep form the gate electrodes of transistors  102   p ,  104   p ,  106   p , and  108   p , respectively. The gate electrodes of transistors  106   p  and  108   p  are connected through gate contacts  118   p  and  120   p , and through a higher interconnect level feature  101   p . In one embodiment, the interconnect level feature  101   p  is a first interconnect level feature, i.e., Metal-1 level feature. However, in other embodiments, the interconnect level feature  101   p  can be a higher interconnect level feature, such as a Metal-2 level feature, or Metal-3 level feature. 
     In the illustrated embodiment, to facilitate fabrication (e.g., lithographic resolution) of the interconnect level feature  101   p , edges of the interconnect level feature  101   p  are substantially aligned with edges of neighboring interconnect level features  103   p ,  105   p . However, it should be understood that other embodiments may have interconnect level features placed without regard to interconnect level feature alignment or an interconnect level grid. 
     Additionally, in the illustrated embodiment, to facilitate fabrication (e.g., lithographic resolution), the gate contacts  118   p  and  120   p  are substantially aligned with neighboring contact features  122   p  and  124   p , respectively, such that the gate contacts are placed according to a gate contact grid. However, it should be understood that other embodiments may have gate contacts placed without regard to gate contact alignment or gate contact grid. 
     The gate electrode of transistor  102   p  is connected to the gate electrode of transistor  104   p  through gate contact  126   p , through interconnect level (e.g., Metal-1 level) feature  130   p , through via  132   p , through higher interconnect level (e.g., Metal-2 level) feature  134   p , through via  136   p , through interconnect level (e.g., Metal-1 level) feature  138   p , and through gate contacts  128   p . Although the illustrated embodiment of  FIG. 26  utilizes the Metal-1 and Metal-2 levels to connect the gate electrodes of transistors  102   p  and  104   p , it should be appreciated that in various embodiment, essentially any combination of interconnect levels can be used to make the connection between the gate electrodes of transistors  102   p  and  104   p.    
     It should be appreciated that the cross-coupled transistor layout of  FIG. 26  is defined using four transistors ( 102   p ,  104   p ,  106   p ,  108   p ) and four gate contacts ( 126   p ,  128   p ,  118   p ,  120   p ). Also, the layout embodiment of  FIG. 26  can be characterized in that two of the four gate contacts are placed between the NMOS and PMOS transistors of the cross-coupled transistors, one of the four gate contacts is placed outside of the NMOS transistors, and one of the four gate contacts is placed outside of the PMOS transistors. The two gate contacts placed between the NMOS and PMOS transistors are referred to as “inner gate contacts.” The two gate contacts placed outside of the NMOS and PMOS transistors are referred to as “outer gate contacts.” 
     In describing the cross-coupled layout embodiments illustrated in the various FIGS. herein, including that of  FIG. 26 , the direction in which the linear gate level features extend across the layout is referred to as a “vertical direction.” Correspondingly, the direction that is perpendicular to the direction in which the linear gate level features extend across the layout is referred to as a “horizontal direction.” With this in mind, in the cross-coupled layout of FIG.  26 , it can be seen that the transistors  102   p  and  104   p  having the outer gate contacts  126   p  and  128   p , respectively, are connected by using two horizontal interconnect level features  130   p  and  138   p , and by using one vertical interconnect level feature  134   p . It should be understood that the horizontal and vertical interconnect level features  130   p ,  134   p ,  138   p  used to connect the outer gate contacts  126   p ,  128   p  can be placed essentially anywhere in the layout, i.e., can be horizontally shifted in either direction away from the cross-coupled transistors  102   p ,  104   p ,  106   p ,  108   p , as necessary to satisfy particular layout/routing requirements. 
       FIG. 27  is an illustration showing the exemplary layout of  FIG. 26 , with the linear gate electrode features  116 Bp,  116 Cp,  116 Ep, and  116 Fp defined to include contact head portions  117 Bp,  117 Cp,  117 Ep, and  117 Fp, respectively. As previously discussed, a linear gate electrode feature is allowed to have one or more contact head portion(s) along its line of extent, so long as the linear gate electrode feature does not connect directly within the gate level to another linear gate electrode feature having a different, yet parallel, line of extent. 
       FIG. 28  is an illustration showing the cross-coupled transistor layout of  FIG. 26 , with the horizontal positions of the inner gate contacts  118   p ,  120   p  and outer gate contacts  126   p ,  128   p  respectively reversed, in accordance with one embodiment of the present invention. It should be understood that essentially any cross-coupled transistor configuration layout defined in accordance with a linear gate level can be represented in an alternate manner by horizontally and/or vertically reversing placement of the gate contacts that are used to connect one or both pairs of the four transistors of the cross-coupled transistor configuration. Also, it should be understood that essentially any cross-coupled transistor configuration layout defined in accordance with a linear gate level can be represented in an alternate manner by maintaining gate contact placements and by modifying each routing path used to connect one or both pairs of the four transistors of the cross-coupled transistor configuration. 
       FIG. 29  is an illustration showing the cross-coupled transistor layout of  FIG. 26 , with the vertical positions of the inner gate contacts  118   p  and  120   p  adjusted to enable alignment of the line end spacings between co-linearly aligned gate level features, in accordance with one embodiment of the present invention. Specifically, gate contact  118   p  is adjusted vertically upward, and gate contact  120   p  is adjusted vertically downward. The linear gate level features  116 Bp and  116 Ep are then adjusted such that the line end spacing  142   p  therebetween is substantially vertically centered within area shadowed by the interconnect level feature  101   p . Similarly, the linear gate level features  116 Cp and  116 Fp are then adjusted such that the line end spacing  140   p  therebetween is substantially vertically centered within area shadowed by the interconnect level feature  101   p . Therefore, the line end spacing  142   p  is substantially vertically aligned with the line end spacing  140   p . This vertical alignment of the line end spacings  142   p  and  140   p  allows for use of a cut mask to define the line end spacings  142   p  and  140   p . In other words, linear gate level features  116 Bp and  116 Ep are initially defined as a single continuous linear gate level feature, and linear gate level features  116 Cp and  116 Fp are initially defined as a single continuous linear gate level feature. Then, a cut mask is used to remove a portion of each of the single continuous linear gate level features so as to form the line end spacings  142   p  and  140   p . It should be understood that although the example layout of  FIG. 29  lends itself to fabrication through use of a cut mask, the layout of  FIG. 29  may also be fabricated without using a cut mask. Additionally, it should be understood that each embodiment disclosed herein as being suitable for fabrication through use of a cut mask may also be fabricated without using a cut mask. 
     In one embodiment, the gate contacts  118   p  and  120   p  are adjusted vertically so as to be edge-aligned with the interconnect level feature  101   p . However, such edge alignment between gate contact and interconnect level feature is not required in all embodiments. For example, so long as the gate contacts  118   p  and  120   p  are placed to enable substantial vertical alignment of the line end spacings  142   p  and  140   p , the gate contacts  118   p  and  120   p  may not be edge-aligned with the interconnect level feature  101   p , although they could be if so desired. The above-discussed flexibility with regard to gate contact placement in the direction of extent of the linear gate electrode features is further exemplified in the embodiments of  FIGS. 30 and 54-60 . 
       FIG. 30  is an illustration showing the cross-coupled transistor layout of  FIG. 29 , with the horizontal positions of the inner gate contacts  118   p ,  120   p  and outer gate contacts  126   p ,  128   p  respectively reversed, in accordance with one embodiment of the present invention. 
       FIG. 31  is an illustration showing the cross-coupled transistor layout of  FIG. 26 , with the rectangular-shaped interconnect level feature  101   p  replaced by an S-shaped interconnect level feature  144   p , in accordance with one embodiment of the present invention. As with the illustrated embodiment of  FIG. 26 , the S-shaped interconnect level feature  144   p  can be defined as a first interconnect level feature, i.e., as a Metal-1 level feature. However, in other embodiments, the S-shaped interconnect level feature  144   p  may be defined within an interconnect level other than the Metal-1 level. 
       FIG. 32  is an illustration showing the cross-coupled transistor layout of  FIG. 31 , with the horizontal positions of the inner gate contacts  118   p ,  120   p  and outer gate contacts  126   p ,  128   p  respectively reversed, in accordance with one embodiment of the present invention. It should be appreciated that the S-shaped interconnect level feature  144   p  is flipped horizontally relative to the embodiment of  FIG. 31  to enable connection of the inner contacts  120   p  and  118   p.    
       FIG. 33  is an illustration showing the cross-coupled transistor layout of  FIG. 31 , with a linear gate level feature  146   p  used to make the vertical portion of the connection between the outer contacts  126   p  and  128   p , in accordance with one embodiment of the present invention. Thus, while the embodiment of  FIG. 31  uses vias  132   p  and  136   p , and the higher level interconnect feature  134   p  to make the vertical portion of the connection between the outer contacts  126   p  and  128   p , the embodiment of  FIG. 33  uses gate contacts  148   p  and  150   p , and the linear gate level feature  146   p  to make the vertical portion of the connection between the outer contacts  126   p  and  128   p . In the embodiment of  FIG. 33 , the linear gate level feature  146   p  serves as a conductor, and is not used to define a gate electrode of a transistor. It should be understood that the linear gate level feature  146   p , used to connect the outer gate contacts  126   p  and  128   p , can be placed essentially anywhere in the layout, i.e., can be horizontally shifted in either direction away from the cross-coupled transistors  102   p ,  104   p ,  106   p ,  108   p , as necessary to satisfy particular layout requirements. 
       FIG. 34  is an illustration showing the cross-coupled transistor layout of  FIG. 33 , with the horizontal positions of the inner gate contacts  118   p ,  120   p  and outer gate contacts  126   p ,  128   p  respectively reversed, in accordance with one embodiment of the present invention. 
       FIG. 35  is an illustration showing the cross-coupled transistor layout of  FIG. 33  defined in connection with a multiplexer (MUX), in accordance with one embodiment of the present invention. In contrast to the embodiment of  FIG. 33  which utilizes a non-transistor linear gate level feature  146   p  to make the vertical portion of the connection between the outer contacts  126   p  and  128   p , the embodiment of  FIG. 35  utilizes a select inverter of the MUX to make the vertical portion of the connection between the outer contacts  126   p  and  128   p , wherein the select inverter of the MUX is defined by transistors  152   p  and  154   p . More specifically, transistor  102   p  of the cross-coupled transistors is driven through transistor  152   p  of the select inverter. Similarly, transistor  104   p  of the cross-coupled transistors is driven through transistor  154   p  of the select inverter. It should be understood that the linear gate level feature  116 Gp, used to define the transistors  152   p  and  154   p  of the select inverter and used to connect the outer gate contacts  126   p  and  128   p , can be placed essentially anywhere in the layout, i.e., can be horizontally shifted in either direction away from the cross-coupled transistors  102   p ,  104   p ,  106   p ,  108   p , as necessary to satisfy particular layout requirements. 
       FIG. 36  is an illustration showing the cross-coupled transistor layout of  FIG. 35 , with the horizontal positions of the inner gate contacts  118   p ,  120   p  and outer gate contacts  126   p ,  128   p  respectively reversed, in accordance with one embodiment of the present invention. 
       FIG. 37  is an illustration showing a latch-type cross-coupled transistor layout, in accordance with one embodiment of the present invention. The latch-type cross-coupled transistor layout of  FIG. 37  is similar to that of  FIG. 33 , with the exception that the gate widths of transistors  102   p  and  108   p  are reduced relative to the gate widths of transistors  106   p  and  104   p . Because transistors  102   p  and  108   p  perform a signal keeping function as opposed to a signal driving function, the gate widths of transistors  102   p  and  108   p  can be reduced. As with the embodiment of  FIG. 33 , the outer gate contact  126   p  is connected to the outer gate contact  128   p  by way of the interconnect level feature  130   p , the gate contact  148   p , the linear gate level feature  146   p , the gate contact  150   p , and the interconnect level feature  138   p.    
     Also, because of the reduced size of the diffusion regions  110   p  and  112   p  for the keeping transistors  102   p  and  108   p , the inner gate contacts  120   p  and  118   p  can be vertically aligned. Vertical alignment of the inner gate contacts  120   p  and  118   p  may facilitate contact fabrication, e.g., contact lithographic resolution. Also, vertical alignment of the inner gate contacts  120   p  and  118   p  allows for use of simple linear-shaped interconnect level feature  156   p  to connect the inner gate contacts  120   p  and  118   p . Also, vertical alignment of the inner gate contacts  120   p  and  118   p  allows for increased vertical separation of the line end spacings  142   p  and  140   p , which may facilitate creation of the line end spacings  142   p  and  140   p  when formed using separate cut shapes in a cut mask. 
       FIG. 38  is an illustration showing the cross-coupled transistor layout of  FIG. 37 , with the horizontal positions of the inner gate contacts  120   p ,  118   p  and outer gate contacts  126   p ,  128   p  respectively reversed, in accordance with one embodiment of the present invention. 
       FIG. 39  is an illustration showing the cross-coupled transistor layout of  FIG. 37 , with the interconnect level feature  134   p  used to make the vertical portion of the connection between the outer contacts  126   p  and  128   p , in accordance with one embodiment of the present invention. Thus, while the embodiment of  FIG. 37  uses gate contacts  148   p  and  150   p , and the linear gate level feature  146   p  to make the vertical portion of the connection between the outer contacts  126   p  and  128   p , the embodiment of  FIG. 39  uses vias  132   p  and  136   p , and the interconnect level feature  134   p  to make the vertical portion of the connection between the outer contacts  126   p  and  128   p . In one embodiment of  FIG. 39 , the interconnect level feature  134   p  is defined as second interconnect level feature, i.e., Metal-2 level feature. However, in other embodiments, the interconnect level feature  134   p  can be defined within an interconnect level other than the second interconnect level. It should be understood that the interconnect level feature  134   p , used to connect the outer gate contacts  126   p  and  128   p , can be placed essentially anywhere in the layout, i.e., can be horizontally shifted in either direction away from the cross-coupled transistors  102   p ,  104   p ,  106   p ,  108   p , as necessary to satisfy layout requirements. 
       FIG. 40  is an illustration showing the cross-coupled transistor layout of  FIG. 39 , with the horizontal positions of the inner gate contacts  120   p ,  118   p  and outer gate contacts  126   p ,  128   p  respectively reversed, in accordance with one embodiment of the present invention. 
       FIG. 41  is an illustration showing the latch-type cross-coupled transistor layout of  FIG. 37 , defined in connection with a MUX/latch, in accordance with one embodiment of the present invention. In contrast to the embodiment of  FIG. 37  which utilizes a non-transistor linear gate level feature  146   p  to make the vertical portion of the connection between the outer contacts  126   p  and  128   p , the embodiment of  FIG. 41  utilizes a select/clock inverter of the MUX/latch to make the vertical portion of the connection between the outer contacts  126   p  and  128   p , wherein the select/clock inverter of the MUX/latch is defined by transistors  160   p  and  162   p . More specifically, transistor  102   p  of the cross-coupled transistors is driven through transistor  160   p  of the select/clock inverter. Similarly, transistor  104   p  of the cross-coupled transistors is driven through transistor  162   p  of the select/clock inverter. It should be understood that the linear gate level feature  164   p , used to define the transistors  160   p  and  162   p  of the select/clock inverter and used to connect the outer gate contacts  126   p  and  128   p , can be placed essentially anywhere in the layout, i.e., can be horizontally shifted in either direction away from the cross-coupled transistors  102   p ,  104   p ,  106   p ,  108   p , as necessary to satisfy particular layout requirements. 
       FIG. 42  is an illustration showing the cross-coupled transistor layout of  FIG. 41 , with the horizontal positions of the inner gate contacts  118   p ,  120   p  and outer gate contacts  126   p ,  128   p  respectively reversed, in accordance with one embodiment of the present invention. 
       FIG. 43  is an illustration showing the latch-type cross-coupled transistor layout of  FIG. 37 , defined to have the outer gate contacts  126   p  and  128   p  connected using a single interconnect level, in accordance with one embodiment of the present invention. In contrast to the embodiment of  FIG. 37  which utilizes a non-transistor linear gate level feature  146   p  to make the vertical portion of the connection between the outer contacts  126   p  and  128   p , the embodiment of  FIG. 43  uses a single interconnect level to make the horizontal and vertical portions of the connection between the outer contacts  126   p  and  128   p . The gate electrode of transistor  102   p  is connected to the gate electrode of transistor  104   p  through gate contact  126   p , through horizontal interconnect level feature  166   p , through vertical interconnect level feature  168   p , through horizontal interconnect level feature  170   p , and through gate contact  128   p . In one embodiment, the interconnect level features  166   p ,  168   p , and  170   p  are first interconnect level features (Metal-1 features). However, in other embodiments, the interconnect level features  166   p ,  168   p , and  170   p  can be defined collectively within any other interconnect level. 
       FIG. 44  is an illustration showing the cross-coupled transistor layout of  FIG. 43 , with the horizontal positions of the inner gate contacts  118   p ,  120   p  and outer gate contacts  126   p ,  128   p  respectively reversed, in accordance with one embodiment of the present invention. 
       FIG. 45  is an illustration showing a cross-coupled transistor layout in which all four gate contacts  126   p ,  128   p ,  118   p , and  120   p  of the cross-coupled coupled transistors are placed therebetween, in accordance with one embodiment of the present invention. Specifically, the gate contacts  126   p ,  128   p ,  118   p , and  120   p  of the cross-coupled coupled transistors are placed vertically between the diffusion regions  110   p  and  112   p  that define the cross-coupled coupled transistors. The gate electrode of transistor  102   p  is connected to the gate electrode of transistor  104   p  through gate contact  126   p , through horizontal interconnect level feature  172   p , through vertical interconnect level feature  174   p , through horizontal interconnect level feature  176   p , and through gate contact  128   p . In one embodiment, the interconnect level features  172   p ,  174   p , and  176   p  are first interconnect level features (Metal-1 features). However, in other embodiments, the interconnect level features  172   p ,  174   p , and  176   p  can be defined collectively within any other interconnect level. The gate electrode of transistor  108   p  is connected to the gate electrode of transistor  106   p  through gate contact  120   p , through S-shaped interconnect level feature  144   p , and through gate contact  118   p . The S-shaped interconnect level feature  144   p  can be defined within any interconnect level. In one embodiment, the S-shaped interconnect level feature is defined within the first interconnect level (Metal-1 level). 
       FIG. 45A  shows an annotated version of  FIG. 45 . The features depicted in  FIG. 45A  are exactly the same as the features depicted in  FIG. 45 .  FIG. 45A  shows a first conductive gate level structure  45   a   01 , a second conductive gate level structure  45   a   03 , a third conductive gate level structure  45   a   05 , a fourth conductive gate level structure  45   a   07 , a fifth conductive gate level structure  45   a   09 , and a sixth conductive gate level structure  45   a   11 , each extending lengthwise in a parallel direction. As shown in  FIG. 45A , the second conductive gate level structure  45   a   03  and the third conductive gate level structure  45   a   05  are positioned in an end-to-end spaced apart manner and are separated from each other by a first end-to-end spacing  45   a   25 . As shown in  FIG. 45A , the fourth conductive gate level structure  45   a   07  and the fifth conductive gate level structure  45   a   09  are positioned in an end-to-end spaced apart manner and are separated from each other by a second end-to-end spacing  45   a   27 . 
     As shown in  FIG. 45A , the second conductive gate level structure  45   a   03  is defined to have an inner extension portion  45   a   19  over the inner non-diffusion region between the diffusion regions  110   p  and  112   p . As shown in  FIG. 45A , the third conductive gate level structure  45   a   05  is defined to have an inner extension portion  45   a   17  over the inner non-diffusion region between the diffusion regions  110   p  and  112   p . As shown in  FIG. 45A , the fourth conductive gate level structure  45   a   07  is defined to have an inner extension portion  45   a   23  over the inner non-diffusion region between the diffusion regions  110   p  and  112   p . As shown in  FIG. 45A , the fifth conductive gate level structure  45   a   09  is defined to have an inner extension portion  45   a   21  over the inner non-diffusion region between the diffusion regions  110   p  and  112   p . As shown in  FIG. 45A , a first electrical connection  45   a   13  (as denoted by the heavy solid black line) is formed between the second conductive gate level structure  45   a   03  and the fifth conductive gate level structure  45   a   09 . As shown in  FIG. 45A , a second electrical connection  45   a   15  (as denoted by the heavy dashed black line) is formed between the third conductive gate level structure  45   a   05  and the fourth conductive gate level structure  45   a   07 . 
       FIG. 45B  shows an annotated version of  FIG. 45 . The features depicted in  FIG. 45B  are exactly the same as the features depicted in  FIG. 45 . As shown in  FIG. 45B , the second conductive gate level structure  45   a   03  extends a distance  45   a   33  away from the contact  120   p  and in the parallel direction away from the gate electrode of transistor  108   p . As shown in  FIG. 45B , the third conductive gate level structure  45   a   05  extends a distance  45   a   31  away from the contact  126   p  and in the parallel direction away from the gate electrode of transistor  102   p . As shown in  FIG. 45B , the fourth conductive gate level structure  45   a   07  extends a distance  45   a   37  away from the contact  128   p  and in the parallel direction away from the gate electrode of transistor  104   p . As shown in  FIG. 45B , the fifth conductive gate level structure  45   a   09  extends a distance  45   a   35  away from the contact  118   p  and in the parallel direction away from the gate electrode of transistor  106   p.    
       FIG. 46  is an illustration showing the cross-coupled transistor layout of  FIG. 45 , with multiple interconnect levels used to connect the gate contacts  126   p  and  128   p , in accordance with one embodiment of the present invention. The gate electrode of transistor  102   p  is connected to the gate electrode of transistor  104   p  through gate contact  126   p , through horizontal interconnect level feature  172   p , through via  180   p , through vertical interconnect level feature  178   p , through via  182   p , through horizontal interconnect level feature  176   p , and through gate contact  128   p . In one embodiment, the horizontal interconnect level features  172   p  and  176   p  are defined within the same interconnect level, e.g., Metal-1 level, and the vertical interconnect level feature  178   p  is defined within a higher interconnect level, e.g., Metal-2 level. It should be understood, however, that in other embodiments each of interconnect level features  172   p ,  178   p , and  176   p  can be defined in separate interconnect levels. 
       FIG. 47  is an illustration showing the cross-coupled transistor layout of  FIG. 45 , with increased vertical separation between line end spacings  184   p  and  186   p , in accordance with one embodiment of the present invention. The increased vertical separation between line end spacings  184   p  and  186   p  can facilitate creation of the line end spacings  184   p  and  186   p  when formed using separate cut shapes in a cut mask. 
       FIG. 48  is an illustration showing the cross-coupled transistor layout of  FIG. 45 , using an L-shaped interconnect level feature  188   p  to connect the gate contacts  120   p  and  118   p , in accordance with one embodiment of the present invention. 
       FIG. 49  is an illustration showing the cross-coupled transistor layout of  FIG. 48 , with the horizontal position of gate contacts  126   p  and  118   p  reversed, and with the horizontal position of gate contacts  120   p  and  128   p  reversed, in accordance with one embodiment of the present invention. 
       FIG. 50  is an illustration showing the cross-coupled transistor layout of  FIG. 48 , with increased vertical separation between line end spacings  184   p  and  186   p , in accordance with one embodiment of the present invention. The increased vertical separation between line end spacings  184   p  and  186   p  can facilitate creation of the line end spacings  184   p  and  186   p  when formed using separate cut shapes in a cut mask. 
       FIG. 51  is an illustration showing the cross-coupled transistor layout of  FIG. 45 , in which gate contacts  120   p  and  118   p  are vertically aligned, in accordance with one embodiment of the present invention. A linear-shaped interconnect level feature  190   p  is used to connect the vertically aligned gate contacts  120   p  and  118   p . Also, in the embodiment of  FIG. 51 , an increased vertical separation between line end spacings  184   p  and  186   p  is provided to facilitate creation of the line end spacings  184   p  and  186   p  when formed using separate cut shapes in a cut mask, although use of a cut mask to fabricate the layout of  FIG. 51  is not specifically required. 
       FIG. 51A  shows an annotated version of  FIG. 51 . The features depicted in  FIG. 51A  are exactly the same as the features depicted in  FIG. 51 .  FIG. 51A  shows a first conductive gate level structure  51   a   01 , a second conductive gate level structure  51   a   03 , a third conductive gate level structure  51   a   05 , a fourth conductive gate level structure  51   a   07 , a fifth conductive gate level structure  51   a   09 , and a sixth conductive gate level structure  51   a   11 , each extending lengthwise in a parallel direction. As shown in  FIG. 51A , the second conductive gate level structure  51   a   03  and the third conductive gate level structure  51   a   05  are positioned in an end-to-end spaced apart manner and are separated from each other by a first end-to-end spacing  51   a   25 . As shown in  FIG. 51A , the fourth conductive gate level structure  51   a   07  and the fifth conductive gate level structure  51   a   09  are positioned in an end-to-end spaced apart manner and are separated from each other by a second end-to-end spacing  51   a   27 . 
     As shown in  FIG. 51A , the second conductive gate level structure  51   a   03  is defined to have an inner extension portion  51   a   19  over the inner non-diffusion region between the diffusion regions  110   p  and  112   p . As shown in  FIG. 51A , the third conductive gate level structure  51   a   05  is defined to have an inner extension portion  51   a   17  over the inner non-diffusion region between the diffusion regions  110   p  and  112   p . As shown in  FIG. 51A , the fourth conductive gate level structure  51   a   07  is defined to have an inner extension portion  51   a   23  over the inner non-diffusion region between the diffusion regions  110   p  and  112   p . As shown in  FIG. 51A , the fifth conductive gate level structure  51   a   09  is defined to have an inner extension portion  51   a   21  over the inner non-diffusion region between the diffusion regions  110   p  and  112   p . As shown in  FIG. 51A , a first electrical connection  51   a   13  (as denoted by the heavy solid black line) is formed between the second conductive gate level structure  51   a   03  and the fifth conductive gate level structure  51   a   09 . As shown in  FIG. 51A , a second electrical connection  51   a   15  (as denoted by the heavy dashed black line) is formed between the third conductive gate level structure  51   a   05  and the fourth conductive gate level structure  51   a   07 . 
       FIG. 51B  shows an annotated version of  FIG. 51 . The features depicted in  FIG. 51B  are exactly the same as the features depicted in  FIG. 51 . As shown in  FIG. 51B , the second conductive gate level structure  51   a   03  extends a distance  51   a   33  away from the contact  120   p  and in the parallel direction away from the gate electrode of transistor  108   p . As shown in  FIG. 51B , the third conductive gate level structure  51   a   05  extends a distance  51   a   31  away from the contact  126   p  and in the parallel direction away from the gate electrode of transistor  102   p . As shown in  FIG. 51B , the fourth conductive gate level structure  51   a   07  extends a distance  51   a   37  away from the contact  128   p  and in the parallel direction away from the gate electrode of transistor  104   p . As shown in  FIG. 51B , the fifth conductive gate level structure  51   a   09  extends a distance  51   a   35  away from the contact  118   p  and in the parallel direction away from the gate electrode of transistor  106   p.    
       FIG. 52  is an illustration showing the cross-coupled transistor layout of  FIG. 45 , in which a linear-shaped interconnect level feature  192   p  is used to connect the non-vertically-aligned gate contacts  120   p  and  118   p , in accordance with one embodiment of the present invention. It should be appreciated that the linear-shaped interconnect level feature  192   p  is stretched vertically to cover both of the gate contacts  120   p  and  118   p.    
       FIG. 53  is an illustration showing the cross-coupled transistor layout of  FIG. 52 , with multiple interconnect levels used to connect the gate contacts  126   p  and  128   p , in accordance with one embodiment of the present invention. The gate electrode of transistor  102   p  is connected to the gate electrode of transistor  104   p  through gate contact  126   p , through horizontal interconnect level feature  172   p , through via  180   p , through vertical interconnect level feature  178   p , through via  182   p , through horizontal interconnect level feature  176   p , and through gate contact  128   p . In one embodiment, the horizontal interconnect level features  172   p  and  176   p  are defined within the same interconnect level, e.g., Metal-1 level, and the vertical interconnect level feature  178   p  is defined within a higher interconnect level, e.g., Metal-2 level. It should be understood, however, that in other embodiments each of interconnect level features  172   p ,  178   p , and  176   p  can be defined in separate interconnect levels. 
       FIG. 54  is an illustration showing the cross-coupled transistor layout of  FIG. 53 , with the vertical positions of gate contacts  118   p  and  120   p  adjusted to enable alignment of the line end spacings between co-linearly aligned gate level features, in accordance with one embodiment of the present invention. Specifically, gate contact  118   p  is adjusted vertically upward, and gate contact  120   p  is adjusted vertically downward. The linear gate level features  116 Bp and  116 Ep are then adjusted such that the line end spacing  184   p  therebetween is substantially vertically centered within area shadowed by the interconnect level feature  192   p . Similarly, the linear gate level features  116 Cp and  116 Fp are then adjusted such that the line end spacing  186   p  therebetween is substantially vertically centered within area shadowed by the interconnect level feature  192   p . Therefore, the line end spacing  184   p  is substantially vertically aligned with the line end spacing  186   p . This vertical alignment of the line end spacings  184   p  and  186   p  allows for use of a cut mask to define the line end spacings  184   p  and  186   p . In other words, linear gate level features  116 Bp and  116 Ep are initially defined as a single continuous linear gate level feature, and linear gate level features  116 Cp and  116 Fp are initially defined as a single continuous linear gate level feature. Then, a cut mask is used to remove a portion of each of the single continuous linear gate level features so as to form the line end spacings  184   p  and  186   p . As previously discussed with regard to  FIG. 29 , although edge-alignment between the gate contacts  118   p ,  120   p  and the interconnect level feature  192   p  can be utilized in one embodiment, it should be understood that such edge-alignment between gate contact and interconnect level feature is not required in all embodiments. 
       FIG. 55  is an illustration showing a cross-coupled transistor layout in which the four gate contacts  126   p ,  128   p ,  120   p , and  118   p  are placed within three consecutive horizontal tracks of an interconnect level, in accordance with one embodiment of the present invention. The gate electrode of transistor  102   p  is connected to the gate electrode of transistor  104   p  through gate contact  126   p , through horizontal interconnect level feature  402   p , through gate contact  418   p , through vertical gate level feature  404   p , through gate contact  416   p , through horizontal interconnect level feature  424   p , and through gate contact  128   p . The vertical gate level feature  404   p  represents a common node to which the gate electrodes of transistors  426   p  and  428   p  are connected. It should be understood that the vertical gate level feature  404   p  can be shifted left or right relative to the cross-coupled transistors  102   p ,  104   p ,  106   p ,  108   p , as necessary for layout purposes. Also, the gate electrode of transistor  106   p  is connected to the gate electrode of transistor  108   p  through gate contact  118   p , through horizontal interconnect level feature  190   p , and through gate contact  120   p.    
     It should be appreciated that placement of gate contacts  126   p ,  128   p ,  120   p , and  118   p  within three consecutive horizontal interconnect level tracks allows for an interconnect level track  414   p  to pass through the cross-coupled transistor layout. Also, it should be understood that the interconnect level features  402   p ,  424   p , and  190   p  can be defined in the same interconnect level or in different interconnect levels. In one embodiment, each of the interconnect level features  402   p ,  424   p , and  190   p  is defined in a first interconnect level (Metal-1 level). 
       FIG. 56  is an illustration showing the cross-coupled transistor layout of  FIG. 55 , in which a non-transistor gate level feature  430   p  is used to make the vertical portion of the connection between gate contacts  126   p  and  126   p , in accordance with one embodiment of the present invention. The gate electrode of transistor  102   p  is connected to the gate electrode of transistor  104   p  through gate contact  126   p , through horizontal interconnected level feature  402   p , through gate contact  418   p , through vertical non-transistor gate level feature  430   p , through gate contact  416   p , through horizontal interconnect level feature  424   p , and through gate contact  128   p.    
       FIG. 57  is an illustration showing a cross-coupled transistor layout in which the four gate contacts  126   p ,  128   p ,  120   p , and  118   p  are placed within three consecutive horizontal tracks of an interconnect level, and in which multiple interconnect levels are used to connect the gate contacts  126   p  and  128   p , in accordance with one embodiment of the present invention. The gate electrode of transistor  102   p  is connected to the gate electrode of transistor  104   p  through gate contact  126   p , through horizontal interconnect level feature  432   p , through via  434   p , through vertical interconnect level feature  436   p , through via  438   p , through horizontal interconnect level feature  440   p , and through gate contact  128   p . The vertical interconnect level feature  436   p  is defined within an interconnect level different from the interconnect level in which the horizontal interconnect level features  432   p  and  440   p  are defined. In one embodiment, the horizontal interconnect level features  432   p  and  440   p  are defined within a first interconnect level (Metal-1 level), and the vertical interconnect level feature  436   p  is defined within a second interconnect level (Metal-2 level). It should be understood that the vertical interconnect level feature  436   p  can be shifted left or right relative to the cross-coupled transistors  102   p ,  104   p ,  106   p ,  108   p , as necessary for layout purposes. Also, the gate electrode of transistor  106   p  is connected to the gate electrode of transistor  108   p  through gate contact  118   p , through horizontal interconnect level feature  190   p , and through gate contact  120   p.    
       FIG. 58  is an illustration showing the cross-coupled transistor layout of  FIG. 57 , in which the gate contacts  126 Ap,  118 Ap,  120 Ap, and  128 Ap are extended in the vertical direction to provided additional overlap with their respective underlying gate level feature, in accordance with one embodiment of the present invention. The additional overlap of the gate level features by the gate contacts  126 Ap,  118 Ap,  120 Ap, and  128 Ap may be provided to satisfy design rules. 
       FIG. 59  is an illustration showing the cross-coupled transistor layout of  FIG. 57 , in which the gate contacts  126   p ,  118   p ,  120   p , and  128   p  are placed within four consecutive interconnect level tracks with an intervening vacant interconnect level track  704   p , in accordance with one embodiment of the present invention. The gate electrode of transistor  102   p  is connected to the gate electrode of transistor  104   p  through gate contact  126   p , through horizontal interconnect level feature  432   p , through via  434   p , through vertical interconnect level feature  436   p , through via  438   p , through horizontal interconnect level feature  440   p , and through gate contact  128   p . The gate electrode of transistor  106   p  is connected to the gate electrode of transistor  108   p  through gate contact  118   p , through L-shaped interconnect level feature  450   p , and through gate contact  120   p . As shown at locations  706   p  and  708   p , the L-shaped interconnect level feature  450   p  can be extended beyond the gate contacts  120   p  and  118   p  to provide sufficient overlap of the gate contacts by the L-shaped interconnect level feature  450   p , as needed to satisfy design rules. 
       FIG. 59A  shows an annotated version of  FIG. 59 . The features depicted in  FIG. 59A  are exactly the same as the features depicted in  FIG. 59 .  FIG. 59A  shows a first conductive gate level structure  59   a   01 , a second conductive gate level structure  59   a   03 , a third conductive gate level structure  59   a   05 , a fourth conductive gate level structure  59   a   07 , a fifth conductive gate level structure  59   a   09 , and a sixth conductive gate level structure  59   a   11 , each extending lengthwise in a parallel direction. As shown in  FIG. 59A , the second conductive gate level structure  59   a   03  and the third conductive gate level structure  59   a   05  are positioned in an end-to-end spaced apart manner and are separated from each other by a first end-to-end spacing  59   a   25 . As shown in  FIG. 59A , the fourth conductive gate level structure  59   a   07  and the fifth conductive gate level structure  59   a   09  are positioned in an end-to-end spaced apart manner and are separated from each other by a second end-to-end spacing  59   a   27 . 
     As shown in  FIG. 59A , the second conductive gate level structure  59   a   03  is defined to have an inner extension portion  59   a   19  over the inner non-diffusion region between the diffusion regions  110   p  and  112   p . As shown in  FIG. 59A , the third conductive gate level structure  59   a   05  is defined to have an inner extension portion  59   a   17  over the inner non-diffusion region between the diffusion regions  110   p  and  112   p . As shown in  FIG. 59A , the fourth conductive gate level structure  59   a   07  is defined to have an inner extension portion  59   a   23  over the inner non-diffusion region between the diffusion regions  110   p  and  112   p . As shown in  FIG. 59A , the fifth conductive gate level structure  59   a   09  is defined to have an inner extension portion  59   a   21  over the inner non-diffusion region between the diffusion regions  110   p  and  112   p . As shown in  FIG. 59A , a first electrical connection  59   a   13  (as denoted by the heavy solid black line) is formed between the second conductive gate level structure  59   a   03  and the fifth conductive gate level structure  59   a   09 . As shown in  FIG. 59A , a second electrical connection  59   a   15  (as denoted by the heavy dashed black line) is formed between the third conductive gate level structure  59   a   05  and the fourth conductive gate level structure  59   a   07 . 
       FIG. 59B  shows an annotated version of  FIG. 59 . The features depicted in  FIG. 59B  are exactly the same as the features depicted in  FIG. 59 . As shown in  FIG. 59B , the second conductive gate level structure  59   a   03  extends a distance  59   a   33  away from the contact  120   p  and in the parallel direction away from the gate electrode of transistor  108   p . As shown in  FIG. 59B , the third conductive gate level structure  59   a   05  extends a distance  59   a   31  away from the contact  126   p  and in the parallel direction away from the gate electrode of transistor  102   p . As shown in  FIG. 59B , the fourth conductive gate level structure  59   a   07  extends a distance  59   a   37  away from the contact  128   p  and in the parallel direction away from the gate electrode of transistor  104   p . As shown in  FIG. 59B , the fifth conductive gate level structure  59   a   09  extends a distance  59   a   35  away from the contact  118   p  and in the parallel direction away from the gate electrode of transistor  106   p.    
       FIG. 60  is an illustration showing the cross-coupled transistor layout of  FIG. 59 , with a variation in the overlap of the gate contact  120   p  by the L-shaped interconnect level feature  450   p , in accordance with one embodiment of the present invention. The overlap region  709   p  is turned horizontally so as to align with the horizontal interconnect level feature  440   p.    
       FIGS. 61-94  are illustrations showing variants of the cross-coupled transistor layouts of  FIGS. 26 and 28-60 , respectively. As previously mentioned, essentially any cross-coupled transistor layout defined in accordance with a linear gate level can be represented in an alternate manner by horizontally and/or vertically reversing placement of the gate contacts that are used to connect one or both pairs of the four transistors of the cross-coupled transistor configuration. Also, essentially any cross-coupled transistor layout defined in accordance with a linear gate level can be represented in an alternate manner by maintaining gate contact placements and by modifying each routing path used to connect one or both pairs of the four transistors of the cross-coupled transistor configuration. 
       FIGS. 95-99  show exemplary cross-coupled transistor layouts defined in accordance with the linear gate level, in which a folded transistor layout technique is implemented. A folded transistor is defined as a plurality of transistors whose gate electrodes share an identical electrical connectivity configuration. In other words, each individual transistor of a given folded transistor has its gate electrode connected to a common node and is defined to electrically interface with a common diffusion region. It should be understood that although each individual transistor of a given folded transistor has its gate electrode connected to a common diffusion region, it is not required that the common diffusion region be continuous, i.e., monolithic. For example, diffusion regions that are of the same type but are physically separated from each other, and have an electrical connection to a common output node, and share a common source/drain, satisfy the common diffusion region characteristic of the folded transistor. 
     In the example layout of  FIG. 95 , a first pair of the cross-coupled transistors is defined by a folded transistor  6901 Ap/ 6901 Bp and by a transistor  6903   p . Each of the individual transistors  6901 Ap and  6901 Bp that form the folded transistor is connected to a common diffusion region  6905   p  and has its gate electrode connected to a common node  6907   p  through respective gate contacts  6909 Ap and  6909 Bp. The gate contacts  6909 Ap and  6909 Bp are connected to a gate contact  6921   p  of transistor  6903   p  by way of a metal 1 interconnect level feature  6911   p , a contact  6913   p , a gate level feature  6915   p , a contact  6917   p , and a metal 1 interconnect level feature  6919   p . A second pair of the cross-coupled transistors is defined by a folded transistor  6923 Ap/ 6923 Bp and by a transistor  6925   p . Each of the individual transistors  6923 Ap and  6923 Bp that form the folded transistor is connected to a common diffusion region  6927   p  and has its gate electrode connected to a common node  6929   p  through respective gate contacts  693  lAp and  6931 Bp. The gate contacts  693  lAp and  6931 Bp are connected to a gate contact  6933   p  of transistor  6925   p  by way of a metal 1 interconnect level feature  6935   p . Transistors  6901 Ap,  6901 Bp, and  6925   p  are electrically interfaced with the diffusion region  6905   p . Also, transistors  6923 Ap,  6923 Bp, and  6903   p  are electrically interfaced with the diffusion region  6927   p . Additionally, although not explicitly shown, diffusion regions  6905   p  and  6927   p  are connected to a common output node. 
       FIG. 96  shows a variant of the cross-coupled transistor layout of  FIG. 95 , in which the connection between the folded transistor  6901 Ap/ 6901 Bp and the transistor  6903   p  is made using an alternate conductive path through the chip. Specifically, the gate contacts  6909 Ap and  6909 Bp are connected to the gate contact  6921   p  of transistor  6903   p  by way of a metal 1 interconnect level feature  7001   p , a via  7003   p , a metal 2 interconnect level feature  7005   p , a via  7007   p , and a metal 1 interconnect level feature  7009   p.    
     In the example layout of  FIG. 97 , a first pair of the cross-coupled transistors is defined by a folded transistor  7101 Ap/ 7101 Bp and by a folded transistor  7103 Ap/ 7103 Bp. Gate contacts  7105 Ap and  7105 Bp are connected to gate contacts  7107 Ap and  7107 Bp by way of a metal 1 interconnect level feature  7109   p , a via  7111   p , a metal 2 interconnect level feature  7113   p , a via  7115   p , and a metal 1 interconnect level feature  7117   p . A second pair of the cross-coupled transistors is defined by a folded transistor  7119 Ap/ 7119 Bp and by a folded transistor  7121 Ap/ 7121 Bp. Gate contacts  7123 Ap and  7123 Bp are connected to gate contacts  7125 Ap and  7125 Bp by way of a metal 1 interconnect level feature  7127   p , a via  7129   p , a metal 2 interconnect level feature  7131   p , a via  7133   p , a metal 1 interconnect level feature  7135   p , a via  7137   p , a metal 2 interconnect level feature  7139   p , a via  7141   p , and a metal 1 interconnect level feature  7143   p . Transistors  7101 Ap,  7101 Bp,  7121 Ap, and  7121 Bp are electrically interfaced with diffusion region  7145   p . Also, transistors  7119 Ap,  7119 Bp,  7103 Ap, and  7103 Bp are electrically interfaced with diffusion region  7147   p . Additionally, although not explicitly shown, portions of diffusion regions  7145   p  and  7147   p  which are electrically interfaced with the transistors  7101 Ap,  7101 Bp,  7103 Ap,  7103 Bp,  7119 Ap,  7119 Bp,  7121 Ap, and  7121 Bp are connected to a common output node. 
       FIG. 98  shows a variant of the cross-coupled transistor layout of  FIG. 97 , in which the electrical connections between the cross-coupled transistors are made using an alternate conductive paths through the chip. Specifically, the gate contacts  7105 Ap and  7105 Bp are connected to the gate contacts  7107 Ap and  7107 Bp by way of a metal 1 interconnect level feature  7201   p , a contact  7203   p , a gate level feature  7205   p , a contact  7207   p , and a metal 1 interconnect level feature  7209   p . Also, the gate contacts  7123 Ap and  7123 Bp are connected to the gate contacts  7125 Ap and  7125 Bp by way of a metal 1 interconnect level feature  7211   p . In this embodiment, the metal 1 interconnect level in unrestricted with regard to bends in conductive features. Therefore, the metal 1 interconnect level feature  7211   p  can be defined to “snake” through the metal 1 interconnect level to make the required cross-coupled transistor connections, as permitted by surrounding layout features. 
       FIG. 99  shows a variant of the cross-coupled transistor layout of  FIG. 97 , in which the connection between the folded transistor  7101 Ap/ 7101 Bp and the folded transistor  7103 Ap/ 7103 Bp is made using an alternate conductive path through the chip. Specifically, the gate contacts  7105 Ap and  7105 Bp are connected to the gate contacts  7107 Ap and  7107 Bp by way of the metal 1 interconnect level feature  7201   p , the contact  7203   p , the gate level feature  7205   p , the contact  7207   p , and the metal 1 interconnect level feature  7209   p . It should be understood that the cross-coupled transistor layouts utilizing folded transistors as shown in  FIGS. 95-99  are provided by way of example, and should not be construed as fully inclusive. 
     In each  FIGS. 26-99 , the cross-coupled transistor connections have been described by tracing through the various conductive features of each conductive path used to connect each pair of transistors in the cross-coupled layout. It should be appreciated that the conductive path used to connect each pair of transistors in a given cross-coupled layout can traverse through conductive features any number of levels of the chip, utilizing any number of contacts and vias as necessary. For ease of description with regard to  FIGS. 100 through 192 , the conductive paths used to connect the various NMOS/PMOS transistor pairs in each cross-coupled transistor layout are identified by heavy black lines drawn over the corresponding layout features. 
     As previously mentioned,  FIGS. 26-99  do not explicitly show connection of the diffusion regions of the cross-coupled transistors to a common node, although this connection is present.  FIGS. 100-111  show exemplary cross-coupled transistor layouts in which the n-type and p-type diffusion regions of the cross-coupled transistors are shown to be electrically connected to a common node. The conductive path used to connect the diffusion regions of the cross-coupled transistors to the common node in each of  FIGS. 100-111  is identified by a heavy black dashed line drawn over the corresponding layout features. For ease of description,  FIGS. 112-148  do not show the heavy black dashed line corresponding to the conductive path used to connect the diffusion regions of the cross-coupled transistors to the common node. However, some of  FIGS. 112-148  do show the layout features associated with the conductive path, or a portion thereof, used to connect the diffusion regions of the cross-coupled transistors to the common node. Again, although not explicitly shown in each of  FIGS. 26-148 , it should be understood that each of the exemplary cross-coupled transistor layout includes a conductive path that connects the diffusion regions of the cross-coupled transistors to a common output node. 
       FIG. 68A  shows an annotated version of  FIG. 68 . The features depicted in  FIG. 68A  are exactly the same as the features depicted in  FIG. 68 .  FIG. 68A  shows a first conductive gate level structure  68   a   02 , a second conductive gate level structure  68   a   04 , a third conductive gate level structure  68   a   06 , a fourth conductive gate level structure  68   a   08 , a fifth conductive gate level structure  68   a   10 , a sixth conductive gate level structure  68   a   12 , and a seventh conductive gate level structure  68   a   14 , each extending lengthwise in a parallel direction. As shown in  FIG. 68A , the first conductive gate level structure  68   a   02  forms a gate electrode of transistor  68   a   01  and a gate electrode of transistor  68   a   1   1 . As shown in  FIG. 68A , the second conductive gate level structure  68   a   04  forms a gate electrode of transistor  68   a   03 . As shown in  FIG. 68A , the third conductive gate level structure  68   a   06  forms a gate electrode of transistor  68   a   13 . As shown in  FIG. 68A , the fourth conductive gate level structure  68   a   08  forms a gate electrode of transistor  68   a   05 . As shown in  FIG. 68A , the fifth conductive gate level structure  68   a   10  forms a gate electrode of transistor  68   a   15 . As shown in  FIG. 68A , the sixth conductive gate level structure  68   a   12  forms a gate electrode of transistor  68   a   07  and a gate electrode of transistor  68   a   17 . As shown in  FIG. 68A , the seventh conductive gate level structure  68   a   14  forms a gate electrode of transistor  68   a   09  and a gate electrode of transistor  68   a   19 . 
     As shown in  FIG. 68A , the second conductive gate level structure  68   a   04  has an inner end position  68   a   27 . As shown in  FIG. 68A , the third conductive gate level structure  68   a   06  has an inner end position  68   a   25 . As shown in  FIG. 68A , the fourth conductive gate level structure  68   a   08  has an inner end position  68   a   31 . As shown in  FIG. 68A , the fifth conductive gate level structure  68   a   10  has an inner end position  68   a   29 . As shown in  FIG. 68A , a first electrical connection  68   a   23  (as denoted by the heavy solid black line) is formed between the second conductive gate level structure  68   a   04  and the fifth conductive gate level structure  68   a   10 , and through an interconnect structure  68   a   16  formed in a single interconnect level. As shown in  FIG. 68A , a second electrical connection  68   a   21  (as denoted by the heavy dashed black line) is formed between the third conductive gate level structure  68   a   06  and the fourth conductive gate level structure  68   a   08 . 
       FIG. 68B  shows an annotated version of  FIG. 68 . The features depicted in  FIG. 68B  are exactly the same as the features depicted in  FIG. 68 . As shown in  FIG. 68B , the second conductive gate level structure  68   a   04  and the third conductive gate level structure  68   a   06  are positioned in an end-to-end spaced apart manner and are separated from each other by a first end-to-end spacing  68   a   41 . As shown in  FIG. 68B , the fourth conductive gate level structure  68   a   08  and the fifth conductive gate level structure  68   a   10  are positioned in an end-to-end spaced apart manner and are separated from each other by a second end-to-end spacing  68   a   43 . As shown in  FIG. 68B , the first electrical connection  68   a   23  extends through a contact  68   a   35  that is connected to the second conductive gate level structure  68   a   04 , and through a contact  68   a   37  that is connected to the fifth conductive gate level structure  68   a   10 . As shown in  FIG. 68B , the second electrical connection  68   a   21  extends through a contact  68   a   33  that is connected to the third conductive gate level structure  68   a   06 , through the seventh conductive gate level structure  68   a   14 , and through a contact  68   a   39  that is connected to the fourth conductive gate level structure  68   a   08 . 
       FIG. 68C  shows an annotated version of  FIG. 68 . The features depicted in  FIG. 68C  are exactly the same as the features depicted in  FIG. 68 .  FIG. 68C  shows the first conductive gate level structure  68   a   02  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  68   a   45 .  FIG. 68C  shows each of the second conductive gate level structure  68   a   04  and third conductive gate level structure  68   a   06  to have their lengthwise centerlines substantially aligned with a gate electrode track  68   a   47 .  FIG. 68C  shows each of the third conductive gate level structure  68   a   08  and fourth conductive gate level structure  68   a   10  to have their lengthwise centerlines substantially aligned with a gate electrode track  68   a   49 .  FIG. 68C  shows the sixth conductive gate level structure  68   a   12  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  68   a   51 .  FIG. 68C  shows the seventh conductive gate level structure  68   a   14  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  68   a   53 . 
     As shown in  FIG. 68C , the gate electrodes of transistors  68   a   11  and  68   a   13  are separated by a centerline-to-centerline spacing  68   a   55 . As shown in  FIG. 68C , the gate electrodes of transistors  68   a   13  and  68   a   15  are separated by a centerline-to-centerline spacing  68   a   57 . As shown in  FIG. 68C , the gate electrodes of transistors  68   a   15  and  68   a   17  are separated by a centerline-to-centerline spacing  68   a   59 . As shown in  FIG. 68C , the gate electrodes of transistors  68   a   17  and  68   a   19  are separated by a centerline-to-centerline spacing  68   a   61 . As shown in  FIG. 68C , the gate electrodes of transistors  68   a   01  and  68   a   03  are separated by the centerline-to-centerline spacing  68   a   55 . As shown in  FIG. 68C , the gate electrodes of transistors  68   a   03  and  68   a   05  are separated by the centerline-to-centerline spacing  68   a   57 . As shown in  FIG. 68C , the gate electrodes of transistors  68   a   05  and  68   a   07  are separated by a centerline-to-centerline spacing  68   a   59 . As shown in  FIG. 68C , the gate electrodes of transistors  68   a   07  and  68   a   09  are separated by a centerline-to-centerline spacing  68   a   61 . As shown in  FIG. 68C , the centerline-to-centerline spacings  68   a   55 ,  68   a   57 ,  68   a   59 ,  68   a   61  are measured perpendicular to the parallel direction of the conductive gate level structures  68   a   02 ,  68   a   04 ,  68   a   06 ,  68   a   08 ,  68   a   10 ,  68   a   12 ,  68   a   14 . As shown in  FIG. 68C , the contact  68   a   35  is located at a first position  68   a   65  in the parallel direction. As shown in  FIG. 68C , the contact  68   a   37  is located at a second position  68   a   63  in the parallel direction. 
       FIG. 109A  shows an annotated version of  FIG. 109 . The features depicted in  FIG. 109A  are exactly the same as the features depicted in  FIG. 109 .  FIG. 109A  shows a first conductive gate level structure  109   a   02 , a second conductive gate level structure  109   a   04 , a third conductive gate level structure  109   a   06 , a fourth conductive gate level structure  109   a   08 , a fifth conductive gate level structure  109   a   10 , a sixth conductive gate level structure  109   a   12 , and a seventh conductive gate level structure  109   a   14 , each extending lengthwise in a parallel direction.  FIG. 109A  shows the first conductive gate level structure  109   a   02  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  109   a   09 .  FIG. 109A  shows the second conductive gate level structure  109   a   04  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  109   a   07 .  FIG. 109A  shows each of the third conductive gate level structure  109   a   06  and fourth conductive gate level structure  109   a   08  to have their lengthwise centerlines substantially aligned with a gate electrode track  109   a   05 .  FIG. 109A  shows the fifth conductive gate level structure  109   a   10  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  109   a   03 .  FIG. 109A  shows each of the sixth conductive gate level structure  109   a   12  and sixth conductive gate level structure  109   a   14  to have their lengthwise centerlines substantially aligned with a gate electrode track  109   a   01 . 
     As shown in  FIG. 109A , the gate electrode tracks  109   a   01 ,  109   a   03 ,  109   a   05 ,  109   a   07 , and  109   a   09  are consecutively separated by gate pitches  109   a   11 ,  109   a   13 ,  109   a   15 , and  109   a   17 . As shown in  FIG. 109A , the gate pitches  109   a   11 ,  109   a   13 ,  109   a   15 , and  109   a   17  are measured perpendicular to the parallel direction of the conductive gate level structures  109   a   02 ,  109   a   04 ,  109   a   06 ,  109   a   08 ,  109   a   10 ,  109   a   12 ,  109   a   14 . As shown in  FIG. 109A , a first electrical connection  109   a   21  (as denoted by the heavy solid black line) electrically connects the third conductive gate level structure  109   a   06  to the seventh conductive gate level structure  109   a   14 . As shown in  FIG. 109A , a second electrical connection  109   a   22  (as denoted by the heavy solid black line) electrically connects the sixth conductive gate level structure  109   a   12  to the fourth conductive gate level structure  109   a   08 . As shown in  FIG. 109A , a third electrical connection  109   a   19  (as denoted by the heavy dashed black line) represents the common node electrical connection. 
       FIG. 109B  shows an annotated version of  FIG. 109 . The features depicted in  FIG. 109B  are exactly the same as the features depicted in  FIG. 109 . As shown in  FIG. 109B , the second conductive gate level structure  109   a   04  forms a gate electrode of a transistor  109   a   31  and a gate electrode of a transistor  109   a   23 . As shown in  FIG. 109B , the third conductive gate level structure  109   a   06  forms a gate electrode of a transistor  109   a   33 . As shown in  FIG. 109B , the fourth conductive gate level structure  109   a   08  forms a gate electrode of a transistor  109   a   25 . As shown in  FIG. 109B , the fifth conductive gate level structure  109   a   10  forms a gate electrode of a transistor  109   a   35  and a gate electrode of a transistor  109   a   27 . As shown in  FIG. 109B , the sixth conductive gate level structure  109   a   12  forms a gate electrode of a transistor  109   a   37 . As shown in  FIG. 109B , the seventh conductive gate level structure  109   a   14  forms a gate electrode of a transistor  109   a   29 . 
     As shown in  FIG. 109B , the first electrical connection  109   a   21  extends through a contact  109   a   45  connected to the third conductive gate level structure  109   a   06 , through the first conductive gate level structure  109   a   02 , and through a contact  109   a   43  connected to the seventh conductive gate level structure  109   a   14 . As shown in  FIG. 109B , the second electrical connection  109   a   22  extends through a contact  109   a   41  connected to the sixth conductive gate level structure  109   a   12 , and through a contact  109   a   39  connected to the fourth conductive gate level structure  109   a   08 . As shown in  FIG. 109B , the third conductive gate level structure  109   a   06  and the fourth conductive gate level structure  109   a   08  are positioned in an end-to-end spaced apart manner and are separated from each other by a first end-to-end spacing  109   a   49 . As shown in  FIG. 109B , the sixth conductive gate level structure  109   a   12  and the seventh conductive gate level structure  109   a   14  are positioned in an end-to-end spaced apart manner and are separated from each other by a second end-to-end spacing  109   a   47 . 
       FIG. 109C  shows an annotated version of  FIG. 109 . The features depicted in  FIG. 109C  are exactly the same as the features depicted in  FIG. 109 .  FIG. 109C  shows an inner end position  109   a   55  of the third conductive gate level structure  109   a   06 .  FIG. 109C  shows an inner end position  109   a   57  of the fourth conductive gate level structure  109   a   08 .  FIG. 109C  shows an inner end position  109   a   51  of the sixth conductive gate level structure  109   a   12 . FIG.  109 C shows an inner end position  109   a   53  of the seventh conductive gate level structure  109   a   14 . 
       FIG. 111A  shows an annotated version of  FIG. 111 . The features depicted in  FIG. 111A  are exactly the same as the features depicted in  FIG. 111 .  FIG. 111A  shows a first conductive gate level structure  111   a   02 , a second conductive gate level structure  111   a   04 , a third conductive gate level structure  111   a   06 , a fourth conductive gate level structure  111   a   08 , a fifth conductive gate level structure  111   a   10 , a sixth conductive gate level structure  111   a   12 , a seventh conductive gate level structure  111   a   14 , and an eighth conductive gate level structure  111   a   16 , each extending lengthwise in a parallel direction.  FIG. 111A  shows the first conductive gate level structure  111   a   02  positioned to have its lengthwise centerline substantially aligned with a gate electrode track Mal 1.  FIG. 111A  shows the second conductive gate level structure  111   a   04  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  111   a   09 .  FIG. 111A  shows the third conductive gate level structure  111   a   06  and the fourth conductive gate level structure  111   a   08  positioned to have their lengthwise centerlines substantially aligned with a gate electrode track  111   a   07 .  FIG. 111A  shows the fifth conductive gate level structure  111   a   10  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  111   a   05 .  FIG. 111A  shows the sixth conductive gate level structure  111   a   12  and the seventh conductive gate level structure  111   a   14  positioned to have their lengthwise centerlines substantially aligned with a gate electrode track  111   a   03 .  FIG. 111A  shows the eighth conductive gate level structure  111   a   16  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  111   a   01 . As shown in  FIG. 111A , the gate electrode tracks  111   a   01 ,  111   a   03 ,  111   a   05 ,  111   a   07 ,  111   a   09 , and  111   a   11  are consecutively separated by gate pitches  111   a   13 ,  111   a   15 ,  111   a   17 ,  111   a   19 , and  111   a   21 . As shown in  FIG. 109A , the gate pitches  111   a   13 ,  111   a   15 ,  111   a   17 ,  111   a   19 , and  111   a   21  are measured perpendicular to the parallel direction of the conductive gate level structures  111   a   02 ,  111   a   04 ,  111   a   06 ,  111   a   08 ,  111   a   10 ,  111   a   12 ,  111   a   14 ,  111   a   16 . 
     As shown in  FIG. 111A , the first conductive gate level structure  111   a   02  forms a gate electrode of a transistor  111   a   41  and a gate electrode of a transistor  111   a   31 . As shown in  FIG. 111A , the second conductive gate level structure  111   a   04  forms a gate electrode of a transistor  111   a   39  and a gate electrode of a transistor  111   a   29 . As shown in  FIG. 111A , the third conductive gate level structure  111   a   06  forms a gate electrode of a transistor  111   a   37 . As shown in  FIG. 111A , the fourth conductive gate level structure  111   a   08  forms a gate electrode of a transistor  111   a   27 . As shown in  FIG. 111A , the fifth conductive gate level structure  111   a   10  forms a gate electrode of a transistor  111   a   35  and a gate electrode of a transistor  111   a   25 . As shown in  FIG. 111A , the sixth conductive gate level structure  111   a   12  forms a gate electrode of a transistor  111   a   33 . As shown in  FIG. 111A , the seventh conductive gate level structure  111   a   14  forms a gate electrode of a transistor  111   a   23 . 
     As shown in  FIG. 111A , a first electrical connection  111   a   45  (as denoted by the heavy solid black line) electrically connects the sixth conductive gate level structure  111   a   12  to the fourth conductive gate level structure  111   a   08 . As shown in  FIG. 111A , a second electrical connection  111   a   47  (as denoted by the heavy solid black line) electrically connects the third conductive gate level structure  111   a   06  to the seventh conductive gate level structure  111   a   14 . As shown in  FIG. 111A , the second electrical connection extends through the eighth conductive gate level feature  111   a   49 . As shown in  FIG. 111A , a third electrical connection  111   a   43  (as denoted by the heavy dashed black line) represents the common node electrical connection. 
       FIG. 111B  shows an annotated version of  FIG. 111 . The features depicted in  FIG. 111B  are exactly the same as the features depicted in  FIG. 111 . As shown in  FIG. 111B , the first electrical connection  111   a   45  extends through gate contact  111   a   57  connected to the sixth conductive gate level structure  111   a   12 , and through the gate contact  111   a   59  connected to the fourth conductive gate level structure  111   a   08 . As shown in  FIG. 111B , the first electrical connection  111   a   45  extends through a linear-shaped conductive interconnect structure  111   a   51  in a single interconnect level. As shown in  FIG. 111B , the second electrical connection  111   a   47  extends through gate contact  111   a   55  connected to the third conductive gate level structure  111   a   06 , and through the gate contact  111   a   53  connected to the seventh conductive gate level structure  111   a   14 . 
       FIGS. 112-148  show a number of exemplary cross-coupled transistor layouts in which the p-type diffusion regions that are electrically interfaced with the cross-coupled transistors are physically separated from each other. For example, with regard to  FIG. 112 , the p-type diffusion region  8601   p  is physically separated from the p-type diffusion region  8603   p . However, the p-type diffusion regions  8601   p  and  8603   p  are electrically connected to each other by way of contact  8605   p , metal 1 interconnect level feature  8607   p , and contact  8609   p . Although not shown, the diffusion regions  8601   p  and  8603   p  are also electrically connected to diffusion region  8611   p . It should be understood that a variant of each cross-coupled transistor layout as shown in each of  FIGS. 112-148 , can be defined by changing the p-type diffusion regions as shown to n-type diffusion regions, and by also changing the n-type diffusion regions as shown to p-type diffusions regions. Therefore, such variants of  FIGS. 112-148  illustrate a number of exemplary cross-coupled transistor layouts in which the n-type diffusion regions that are electrically interfaced with the cross-coupled transistors are physically separated from each other. 
       FIGS. 149-175  show a number of exemplary cross-coupled transistor layouts defined using two gate contacts to connect one pair of complementary (i.e., NMOS/PMOS) transistors in the cross-coupled transistor layout to each other, and using no gate contact to connect the other pair of complementary transistors in the cross-coupled transistor layout to each other. It should be understood that two gate electrodes of each pair of cross-coupled transistors, when considered as a single node, are electrically connected through at least one gate contact to circuitry external to the cross-coupled transistor portion of the layout. Therefore, it should be understood that the gate electrodes mentioned above, or absence thereof, with regard to connecting each pair of complementary transistors in the cross-coupled transistor layout, refer to gate electrodes defined within the cross-coupled transistor portion of the layout. 
     For example,  FIG. 149  shows a cross-coupled transistor layout in which a gate electrode of transistor  12301   p  is electrically connected to a gate electrode of transistor  12303   p  by way of two gate contacts  12309   p  and  12311   p  in combination with other conductive features. Also, the gate electrodes of transistors  12305   p  and  12307   p  are defined as a single, continuous linear conductive feature within the gate level. Therefore, a gate contact is not required to electrically connect the gate electrodes of transistors  12305   p  and  12307   p . The conductive path used to connect the diffusion regions of the cross-coupled transistors to the common output node in each of  FIGS. 149-175  is identified by a heavy black dashed line drawn over the corresponding layout features. 
     It should be appreciated that the cross-coupled transistor layout defined using two gate contacts to connect one pair of complementary transistors and no gate contact to connect the other pair of complementary transistors can be implemented in as few as two gate electrode tracks, wherein a gate electrode track is defined as a virtual line extending across the gate level in a parallel relationship to its neighboring gate electrode tracks. These two gate electrode tracks can be located essentially anywhere in the layout with regard to each other. In other words, these two gate electrode tracks are not required to be located adjacent to each other, although such an arrangement is permitted, and in some embodiments may be desirable. The cross-coupled transistor layout embodiments of  FIGS. 149-175  can be characterized in that two gate electrodes of one pair of connected complementary transistors in the cross-coupled layout are defined from a single, continuous linear conductive feature defined in the gate level. 
       FIG. 156A  shows an annotated version of  FIG. 156 . The features depicted in  FIG. 156A  are exactly the same as the features depicted in  FIG. 156 .  FIG. 156A  shows a first conductive gate level structure  156   a   02  that forms a gate electrode of a transistor  156   a   21 .  FIG. 156A  shows a second conductive gate level structure  156   a   04  that forms a gate electrode of a transistor  156   a   19  and a gate electrode of a transistor  156   a   11 .  FIG. 156A  shows a third conductive gate level structure  156   a   06  that forms a gate electrode of a transistor  156   a   13 .  FIG. 156A  shows a fourth conductive gate level structure  156   a   08  that forms a gate electrode of a transistor  156   a   23  and a gate electrode of a transistor  156   a   15 .  FIG. 156A  shows a fifth conductive gate level structure  156   a   10  that forms a gate electrode of a transistor  156   a   25  and a gate electrode of a transistor  156   a   17 . As shown in  FIG. 156A , each conductive gate level feature  156   a   02 ,  156   a   04 ,  156   a   06 ,  156   a   08 ,  156   a   10  extends lengthwise in a parallel direction. 
       FIG. 156A  shows the first conductive gate level structure  156   a   02  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  156   a   01 .  FIG. 156A  shows the second conductive gate level structure  156   a   04  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  156   a   03 .  FIG. 156A  shows the third conductive gate level structure  156   a   06  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  156   a   05 . As shown in  FIG. 156A , the first and second gate electrode tracks  156   a   01  and  156   a   03  are separated by a gate pitch  156   a   07 . As shown in  FIG. 156A , the second and third gate electrode tracks  156   a   03  and  156   a   05  are separated by a gate pitch  156   a   09 . As shown in  FIG. 156A , a first electrical connection  156   a   26  (as denoted by the heavy solid line) extends from the transistor  156   a   19  to the transistor  156   a   11 , through the second conductive gate level structure  156   a   04 . As shown in  FIG. 156A , a second electrical connection  156   a   27  (as denoted by the heavy solid line) extends from the transistor  156   a   21  to the transistor  156   a   13 . As shown in  FIG. 156A , a third electrical connection  156   a   29  (as denoted by the heavy dashed line) shows the common node electrical connection. 
       FIG. 156B  shows an annotated version of  FIG. 156 . The features depicted in  FIG. 156B  are exactly the same as the features depicted in  FIG. 156 . As shown in  FIG. 156B , the second electrical connection  156   a   27  extend through gate contact  156   a   53  and through gate contact  156   a   51 . As shown in  FIG. 156B , the gate contact  156   a   53  is located at a contact position  156   a   35 . As shown in  FIG. 156B , the gate contact  156   a   51  is located at a contact position  156   a   37 . As shown in  FIG. 156B , the second conductive gate level structure  156   a   04  is connected to gate contact  156   a   55 , which is located at a contact position  156   a   39 . As shown in  FIG. 156B , each of the first conductive gate level structure  156   a   02  and the third conductive gate level structure  156   a   06  has a respective end aligned to a common position  156   a   33  in the parallel direction. 
       FIG. 157A  shows an annotated version of  FIG. 157 . The features depicted in  FIG. 157A  are exactly the same as the features depicted in  FIG. 157 .  FIG. 157A  shows a first conductive gate level structure  157   a   02 , a second conductive gate level structure  157   a   04 , a third conductive gate level structure  157   a   06 , a fourth conductive gate level structure  157   a   08 , a fifth conductive gate level structure  157   a   10 , and a sixth conductive gate level structure  157   a   12 , each extending lengthwise in a parallel direction.  FIG. 157A  shows the first conductive gate level structure  157   a   02  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  157   a   01 .  FIG. 157A  shows the second conductive gate level structure  157   a   04  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  157   a   03 .  FIG. 157A  shows the third conductive gate level structure  157   a   06  and the fourth conductive gate level structure  157   a   08  positioned to have their lengthwise centerlines substantially aligned with a gate electrode track  157   a   05 .  FIG. 157A  shows the fifth conductive gate level structure  157   a   010  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  157   a   07 .  FIG. 157A  shows the sixth conductive gate level structure  157   a   12  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  157   a   09 . As shown in  FIG. 157A , the gate electrode tracks  157   a   01 ,  157   a   03 ,  157   a   05 ,  157   a   07 , and  157   a   09 , are consecutively separated by gate pitches  157   a   11 ,  157   a   13 ,  157   a   15 , and  157   a   17 . As shown in  FIG. 109A , the gate pitches  157   a   11 ,  157   a   13 ,  157   a   15 , and  157   a   17  are measured perpendicular to the parallel direction of the conductive gate level structures  157   a   02 ,  157   a   04 ,  157   a   06 ,  157   a   08 ,  157   a   10 ,  157   a   12 . 
     As shown in  FIG. 157A , the first conductive gate level structure  157   a   02  forms a gate electrode of a transistor  157   a   29 . As shown in  FIG. 157A , the second conductive gate level structure  157   a   04  forms a gate electrode of a transistor  157   a   27  and a gate electrode of a transistor  157   a   19 . As shown in  FIG. 157A , the third conductive gate level structure  157   a   06  forms a gate electrode of a transistor  157   a   31 . As shown in  FIG. 157A , the fourth conductive gate level structure  157   a   08  forms a gate electrode of a transistor  157   a   21 . As shown in  FIG. 157A , the fifth conductive gate level structure  157   a   10  forms a gate electrode of a transistor  157   a   23 . As shown in  FIG. 157A , the sixth conductive gate level structure  157   a   12  forms a gate electrode of a transistor  157   a   33  and a gate electrode of a transistor  157   a   25 . 
     As shown in  FIG. 157A , a first electrical connection  157   a   50  (as denoted by the heavy solid line) extends from the transistor  157   a   27  to the transistor  157   a   51 , through the second conductive gate level structure  157   a   04 . As shown in  FIG. 157A , a second electrical connection  157   a   51  (as denoted by the heavy solid line) extends from the transistor  157   a   29  to the transistor  157   a   21 . As shown in  FIG. 157A , a third electrical connection  157   a   53  (as denoted by the heavy dashed line) shows the common node electrical connection. 
       FIG. 157B  shows an annotated version of  FIG. 157 . The features depicted in  FIG. 157B  are exactly the same as the features depicted in  FIG. 157 . As shown in  FIG. 157B , the second electrical connection  157   a   51  extends through gate contact  157   a   41  and through gate contact  157   a   39 . As shown in  FIG. 157B , the gate contact  157   a   41  is located at a contact position  157   a   47 . As shown in  FIG. 157B , the gate contact  157   a   39  is located at a contact position  157   a   45 . As shown in  FIG. 157B , the second conductive gate level structure  157   a   50  is connected to gate contact  157   a   43 , which is located at a contact position  157   a   49 . As shown in  FIG. 157B , each of the first conductive gate level structure  157   a   02  and the fourth conductive gate level structure  157   a   08  has a respective end aligned to a common position  157   a   37  in the parallel direction. As shown in  FIG. 157B , the fifth conductive gate level structure  157   a   10  forms the gate electrode of the transistor  157   a   23  with the Pdiff regions and extends between and spaced apart from two Ndiff regions  157   a   69  and  157   a   67 . 
       FIG. 170A  shows an annotated version of  FIG. 170 . The features depicted in  FIG. 170A  are exactly the same as the features depicted in  FIG. 170 .  FIG. 170A  shows a first conductive gate level structure  170   a   02 , a second conductive gate level structure  170   a   04 , a third conductive gate level structure  170   a   06 , a fourth conductive gate level structure  170   a   08 , a fifth conductive gate level structure  170   a   10 , and a sixth conductive gate level structure  170   a   12 , each extending lengthwise in a parallel direction.  FIG. 170A  shows the first conductive gate level structure  170   a   02  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  170   a   01 .  FIG. 170A  shows the second conductive gate level structure  170   a   04  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  170   a   03 .  FIG. 170A  shows the third conductive gate level structure  170   a   06  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  170   a   05 .  FIG. 170A  shows the fourth conductive gate level structure  170   a   08  and the fifth conductive gate level structure  170   a   10  positioned to have their lengthwise centerlines substantially aligned with a gate electrode track  170   a   07 .  FIG. 170A  shows the sixth conductive gate level structure  170   a   12  positioned to have its lengthwise centerline substantially aligned with a gate electrode track  170   a   09 . As shown in  FIG. 170A , the gate electrode tracks  170   a   01 ,  170   a   03 ,  170   a   05 ,  170   a   07 , and  170   a   09 , are consecutively separated by gate pitches  170   a   11 ,  170   a   13 ,  170   a   15 , and  170   a   17 . As shown in  FIG. 170A , the gate pitches  170   a   11 ,  170   a   13 ,  170   a   15 , and  170   a   17  are measured perpendicular to the parallel direction of the conductive gate level structures  170   a   02 ,  170   a   04 ,  170   a   06 ,  170   a   08 ,  170   a   10 ,  170   a   12 . 
     As shown in  FIG. 170A , the first conductive gate level structure  170   a   02  forms a gate electrode of a transistor  170   a   33  and a gate electrode of a transistor  170   a   25 . As shown in  FIG. 170A , the second conductive gate level structure  170   a   04  forms a gate electrode of a transistor  170   a   29 . As shown in  FIG. 170A , the third conductive gate level structure  170   a   06  forms a gate electrode of a transistor  170   a   27  and a gate electrode of a transistor  170   a   19 . As shown in  FIG. 170A , the fourth conductive gate level structure  170   a   08  forms a gate electrode of a transistor  170   a   31 . As shown in  FIG. 170A , the fifth conductive gate level structure  170   a   10  forms a gate electrode of a transistor  170   a   21 . As shown in  FIG. 170A , the sixth conductive gate level structure  170   a   12  forms a gate electrode of a transistor  170   a   23 . 
     As shown in  FIG. 170A , a first electrical connection  170   a   60  (as denoted by the heavy solid line) extends from the transistor  170   a   27  to the transistor  170   a   19 , through the third conductive gate level structure  170   a   06 . As shown in  FIG. 170A , a second electrical connection  170   a   61  (as denoted by the heavy solid line) extends from the transistor  170   a   29  to the transistor  170   a   21 . As shown in  FIG. 170A , a third electrical connection  170   a   63  (as denoted by the heavy dashed line) shows the common node electrical connection. 
       FIG. 170B  shows an annotated version of  FIG. 170 . The features depicted in  FIG. 170B  are exactly the same as the features depicted in  FIG. 170 . As shown in  FIG. 170B , the second electrical connection  170   a   61  extends through gate contact  170   a   39  and through gate contact  170   a   37 . As shown in  FIG. 170B , the gate contact  170   a   39  is located at a contact position  170   a   45 . As shown in  FIG. 170B , the gate contact  170   a   37  is located at a contact position  170   a   43 . As shown in  FIG. 170B , the third conductive gate level structure  170   a   06  is connected to gate contact  170   a   41 , which is located at a contact position  170   a   47 . As shown in  FIG. 170B , each of the first conductive gate level structure  170   a   02 , the third conductive gate level structure  170   a   06 , and the fifth conductive gate level structure  170   a   10  has a respective end aligned to a common position  170   a   35  in the parallel direction. As shown in  FIG. 170B , the sixth conductive gate level structure  170   a   12  forms the gate electrode of the transistor  170   a   23  with the Pdiff regions and includes a portion  170   a   12   a  that extends next to and spaced apart from an Ndiff region. 
       FIGS. 176-191  show a number of exemplary cross-coupled transistor layouts defined using no gate contacts to connect each pair of complementary transistors in the cross-coupled transistor layout. Again, it should be understood that two gate electrodes of each pair of cross-coupled transistors, when considered as a single node, are electrically connected through at least one gate contact to circuitry external to the cross-coupled transistor portion of the layout. Therefore, it should be understood that the absence of gate electrodes with regard to connecting each pair of complementary transistors in the cross-coupled transistor layout refers to an absence of gate electrodes defined within the cross-coupled transistor portion of the layout. 
     For example,  FIG. 176  shows a cross-coupled transistor layout in which gate electrodes of transistors  15001   p  and  15003   p  are defined as a single, continuous linear conductive feature within the gate level. Therefore, a gate contact is not required to electrically connect the gate electrodes of transistors  15001   p  and  15003   p . Also, gate electrodes of transistors  15005   p  and  15007   p  are defined as a single, continuous linear conductive feature within the gate level. Therefore, a gate contact is not required to electrically connect the gate electrodes of transistors  15005   p  and  15007   p . The conductive path used to connect the diffusion regions of the cross-coupled transistors to the common output node in each of  FIGS. 176-191  is identified by a heavy black dashed line drawn over the corresponding layout features. It should be appreciated that the cross-coupled transistor layout defined using no gate contact to connect each pair of complementary transistors can be implemented in as few as one gate electrode track. The cross-coupled transistor layout embodiments of  FIGS. 176-191  can be characterized in that each pair of connected complementary transistors in the cross-coupled layout has its gate electrodes defined from a single, continuous linear conductive feature defined in the gate level. 
       FIG. 192  shows another exemplary cross-couple transistor layout in which the common diffusion node shared between the cross-coupled transistors  16601   p ,  16603   p ,  16605   p , and  16607   p  has one or more transistors defined thereover. Specifically,  FIG. 192  shows that transistors  16609 Ap and  16609 Bp are defined over the diffusion region  16613   p  between transistors  16605   p  and  16603   p . Also,  FIG. 192  shows that transistors  16611 Ap and  16611 Bp are defined over the diffusion region  16615   p  between transistors  16601   p  and  16607   p . It should be understood that diffusion regions  16613   p  and  16615   p  define the common diffusion node to which each of the cross-coupled transistors  16601   p ,  16603   p ,  16605   p , and  16607   p  is electrically interfaced. It should be appreciated that with this type of cross-coupled transistor layout, driver transistors, such as transistors  16609 Ap,  16609 Bp,  16611 Ap, and  16611 Bp, can be disposed over the common diffusion node of the cross-coupled transistors. Hence, the cross-coupled transistors can be considered as being placed “outside” of the driver transistors. 
     As illustrated in  FIGS. 26-192 , the cross-coupled transistor layout using a linear gate level can be defined in a number of different ways. A number of observations associated with the cross-coupled transistor layout defined using the linear gate level are as follows:
         In one embodiment, an interconnect level parallel to the gate level is used to connect the two “outside” transistors, i.e., to connect the two outer gate contacts.   In one embodiment, the end gaps, i.e., line end spacings, between co-aligned gate electrode features in the area between the n and p diffusion regions can be substantially vertically aligned to enable line end cutting.   In one embodiment, the end gaps, i.e., line end spacings, between gate electrode features in the area between the n and p diffusion regions can be separated as much as possible to allow for separation of cut shapes, or to prevent alignment of gate electrode feature line ends.   In one embodiment, the interconnect levels can be configured so that contacts can be placed on a grid to enhance contact printing.   In one embodiment, the contacts can be placed so that a minimal number of first interconnect level (Metal-1 level) tracks are occupied by the cross-couple connection.   In one embodiment, the contacts can be placed to maximize the available diffusion area for device size, e.g., transistor width.   In one embodiment, the contacts can be shifted toward the edges of the interconnect level features to which they connect to allow for better alignment of gate electrode feature line ends.   In pertinent embodiments, it should be noted that the vertical connection between the outside transistors of the cross-coupled transistor layout can be shifted left or right depending on the specific layout requirements.   There is no distance requirement between the n and p diffusion regions. If there are more interconnect level tracks available between the n and p diffusion region, the available interconnect level tracks can be allocated as necessary/appropriate for the layout.   The four transistors of the cross-coupled transistor configuration, as defined in accordance with the linear gate level, can be separated from each other within the layout by arbitrary distances in various embodiments.   In one embodiment, the linear gate electrode features are placed according to a virtual grid or virtual grate. However, it should be understood that in other embodiments the linear gate electrode features, although oriented to have a common direction of extent, are placed without regard to a virtual grid or virtual grate.   Each linear gate electrode feature is allowed to have one or more contact head portion(s) along its line of extent, so long as the linear gate electrode feature does not connect directly within the gate level to another linear gate electrode feature having a different, yet parallel, line of extent.   Diffusion regions associated with the cross-coupled transistor configuration, as defined in accordance with the linear gate level, are not restricted in size or shape.   The four transistors of the cross-coupled transistor configuration, as defined in accordance with the linear gate level, may vary in size as required to satisfy electrical requirements.   Essentially any cross-coupled transistor configuration layout defined in accordance with a linear gate level can be represented in an alternate manner by horizontally and/or vertically reversing placement of the gate contacts that are used to connect one or both pairs of the four transistors of the cross-coupled transistor configuration.   Essentially any cross-coupled transistor configuration layout defined in accordance with a linear gate level can be represented in an alternate manner by maintaining gate contact placements and by modifying each routing path used to connect one or both pairs of the four transistors of the cross-coupled transistor configuration.   A cross-coupled transistor configuration layout defined in accordance with a linear gate level can be optimized for a fabrication process that utilizes a cut mask.   In various embodiments, connections between gates of cross-coupled transistors can be made in essentially any manner by utilizing any level within the chip, any number of levels in the chip, any number of contacts, and/or any number of vias.       

     It should be appreciated that in the embodiments of  FIGS. 26-192 , a number of features and connections are not shown in order to avoid unnecessarily obscuring the cross-couple transistors in the various layouts. For example, in the embodiments of  FIGS. 26-60 , connections to source and drains are not shown. Also, it should be understood that in the exemplary embodiments of  FIGS. 26-192 , some features and connections that are not directly associated with the four cross-coupled transistors are displayed for exemplary purposes and are not intended to represent any restriction on the correspondingly displayed cross-coupled transistor layout. 
     Based on the foregoing, a cross-coupled transistor layout using commonly oriented linear gate level features and transistors having physically separate gate electrodes can be defined according to either of the following embodiments, among others:
         all four gate contacts used to connect each pair of complementary transistors in the cross-coupled transistor layout are placed between the diffusion regions associated with the cross-coupled transistor layout,   two gate contacts used to connect one pair of complementary transistors placed between the diffusion regions associated with the cross-coupled transistor layout, and two gate contacts used to connect another pair of complementary transistors placed outside the diffusion regions with one of these two gate contacts placed outside of each diffusion region,   all four gate contacts used to connect each pair of complementary transistors placed outside the diffusion regions associated with the cross-coupled transistor layout,   three gate contacts placed outside the diffusion regions associated with the cross-coupled transistor layout, and one gate contact placed between the diffusion regions associated with the cross-coupled transistor layout, and   three gate contacts placed between the diffusion regions associated with the cross-coupled transistor layout, and one gate contact placed outside one of the diffusion regions associated with the cross-coupled transistor layout.       

     It should be understood that the cross-coupled transistor layouts implemented within the restricted gate level layout architecture as disclosed herein can be stored in a tangible form, such as in a digital format on a computer readable medium. Also, the invention described herein can be embodied as computer readable code on a computer readable medium. The computer readable medium is any data storage device that can store data which can thereafter be read by a computer system. Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices. The computer readable medium can also be distributed over a network of coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. 
     Any of the operations described herein that form part of the invention are useful machine operations. The invention also relates to a device or an apparatus for performing these operations. The apparatus may be specially constructed for the required purpose, such as a special purpose computer. When defined as a special purpose computer, the computer can also perform other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose. Alternatively, the operations may be processed by a general purpose computer selectively activated or configured by one or more computer programs stored in the computer memory, cache, or obtained over a network. When data is obtained over a network the data maybe processed by other computers on the network, e.g., a cloud of computing resources. 
     The embodiments of the present invention can also be defined as a machine that transforms data from one state to another state. The data may represent an article, that can be represented as an electronic signal and electronically manipulate data. The transformed data can, in some cases, be visually depicted on a display, representing the physical object that results from the transformation of data. The transformed data can be saved to storage generally, or in particular formats that enable the construction or depiction of a physical and tangible object. In some embodiments, the manipulation can be performed by a processor. In such an example, the processor thus transforms the data from one thing to another. Still further, the methods can be processed by one or more machines or processors that can be connected over a network. Each machine can transform data from one state or thing to another, and can also process data, save data to storage, transmit data over a network, display the result, or communicate the result to another machine. 
     While this invention has been described in terms of several embodiments, it will be appreciated that those skilled in the art upon reading the preceding specifications and studying the drawings will realize various alterations, additions, permutations and equivalents thereof. Therefore, it is intended that the present invention includes all such alterations, additions, permutations, and equivalents as fall within the true spirit and scope of the invention.