Patent Publication Number: US-9412437-B2

Title: SRAM with buffered-read bit cells and its testing

Description:
CLAIM TO PRIORITY OF NONPROVISIONAL APPLICATION 
     This application is a divisional of U.S. application Ser. No. 14/010,881 filed Aug. 27, 2013, which is a divisional of U.S. application Ser. No. 13/135,198 filed Jun. 27, 2011, which claims the benefit under 35 U.S.C. §119(e) of Provisional Appl. No. 61/365,157, filed Jul. 16, 2010, the contents which are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     Embodiments of the present invention relate to a static random access memory (SRAM), particularly an SRAM with buffered-read bit cells and its testing. 
     Shrinking semiconductor integrated circuit feature sizes have placed increasing challenges on semiconductor integrated circuit processing. In particular, a balance between high packing density and yield requires a finely tuned manufacturing process. Minimum feature sizes of high density memory cells are frequently less than corresponding feature sizes of peripheral circuits. As a result, subtle defects at these minimum feature sizes can adversely impact product yield. Physical failure analysis (PFA) has often been used to determine the precise cause of these subtle defects. However, PFA is time consuming, destructive, and may not reveal all defects such as gate dielectric failure. Additional complexity of current memory cells such as the 8T SRAM memory cell disclosed by Chang et al., “Stable SRAM Cell Design for the 32 nm Node and Beyond,” 2005 Symposium on VLSI Technology, 8A-2, 128 (2005), further complicate PFA. Moreover, the 8T SRAM cell of Chang et al. further complicates characterization of individual memory cells in a functional memory circuit. Thus, there is a need to more accurately diagnose memory circuit defects without the time, expense, and complication of PFA. 
     BRIEF SUMMARY OF THE INVENTION 
     In a preferred embodiment of the present invention, an integrated circuit is formed having a plurality of memory cells. Each memory cell has a plurality of transistors. A first memory cell is arranged to store a data signal in response to an active write word line and to produce the data signal in response to an active read word line. The integrated circuit further includes a test circuit operable to test current and voltage characteristics of each transistor of the plurality of transistors of the first memory cell. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a static random access memory (SRAM) of the present invention; 
         FIG. 2  is a high level schematic diagram of an 8T memory cell with associated input/output (I/O) functional mode circuitry that may be used in the SRAM of  FIG. 1 ; 
         FIG. 3  is a high level schematic diagram of an 8T memory cell with associated input/output (I/O) direct bit line access (DBLA) circuitry that may be used in the SRAM of  FIG. 1 ; 
         FIG. 4  is a schematic diagram of an embodiment of word line driver circuitry that may be used in the SRAM of  FIG. 1 ; 
         FIG. 5  is a schematic diagram of an embodiment of column data selection circuitry for functional operation of the SRAM memory of  FIG. 1 ; 
         FIG. 6  is a schematic diagram of an embodiment of column data selection circuitry for direct bit line access (DBLA) operation of the SRAM memory of  FIG. 1 ; 
         FIGS. 7A-7E  are simplified schematic diagrams showing various tests that may be performed on a 2-transistor (2T) buffer portion of an 8T memory cell using DBLA of the present invention; 
         FIG. 8  is a table showing test conditions corresponding to  FIGS. 7A-7E ; 
         FIGS. 9A-9F  are simplified schematic diagrams showing various tests that may be performed on a 6-transistor (6T) latch portion of an 8T memory cell using DBLA of the present invention; and 
         FIG. 10  is a table showing test conditions corresponding to  FIGS. 9A-9F . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The preferred embodiments of the present invention provide significant advantages in electrical failure analysis and characterization of individual buffered-read memory cells or individual transistors of buffered-read memory cells of a functional static random access memory (SRAM) using functional test or direct bit line access (DBLA). 
     The present inventors have previously disclosed a circuit and method to characterize individual transistors of a 6-transistor (6T) SRAM memory cell by direct bit line access in application Ser. No. 12/347,928, filed Dec. 31, 2008, and incorporated herein by reference in its entirety. Additional disclosures by the present inventors regarding characterization of individual transistors of a 6T SRAM memory cell are also presented at Deng et al., “Characterization of Bit Transistors in a Functional SRAM,” 2008 Symposium on VLSI Technology, 44 (2008) and Deng et al., “Measurement of Bit Leakages in a Functional SRAM,” 2009 Proceedings from the 35th ISTFA, 16 (November 2009), both of which are incorporated herein by reference in their entirety. The present invention is directed to a circuit and method for testing and characterization of individual buffered-read bit cells and individual transistors of buffered-read bit cells in a functional SRAM. The following embodiments of the present invention are presented by way of example. Numerous alternative designs that fall within the scope of the present claimed invention will be obvious to one of ordinary skill in the art having access to the instant specification. 
     Referring now to  FIG. 1 , there is a block diagram of a static random access memory (SRAM) of the present invention. The SRAM of  FIG. 1  may be a stand alone integrated circuit memory or it may be embedded in a larger integrated circuit having, for example, a processor, nonvolatile memory, or analog circuits. The SRAM includes row periphery circuitry or row decode circuit  100 , column periphery circuitry or column decode and input/output (I/O) circuit  106 , SRAM memory array  102 , and control and test circuit  104 . The memory array  102  includes an array of memory cells in rows and columns. Each row of the memory cells shares a write word line WWLx and a read word line RWLx from the row periphery circuitry, where x is an integer from 0 to M−1. Each column of the memory cells shares a pair of write bit lines WBLTy/WBLBy and a read bit line RBLy from the column periphery circuitry, where y is an integer from 0 to N−1. The row periphery circuitry  100  typically includes row address decode and word line driver circuits and is operable to activate a read word line or a write word line during a read or write operation. The column periphery circuitry typically includes write, bit line precharge, column multiplexer, sense amplifier, and I/O circuits. It is operable to drive a data signal onto a pair of write bit lines during a write operation and to sense and amplify a data signal from a bit cell on a read bit line during a read operation. The small square terminals signify bond pads or ports for receiving external voltages and signals to operate the SRAM. For example, row decode circuit  100 , control and test circuit  104  and column decode and I/O circuit  106  are coupled to receive power supply voltage VDD and reference voltage VSS. Row decode circuit  100  also receives word line supply voltage VDDWL and row address signals RA. Column decode and I/O circuit  106  receives data input signals Din, and produces data output signals Qout in response to received column address signals CA. SRAM array  102  receives array voltage VDDA and array reference voltage VSSA. SRAM array  102  also receives read buffer reference voltage RVSS as will be explained in detail. Voltage supplies VNWA and VSBA are coupled to N-well regions and P-well regions, respectively, of the SRAM array  102 . 
     Referring now to  FIG. 2 , there is a high level schematic diagram of an 8T memory cell with associated input/output (I/O) functional mode circuitry that may be used in the SRAM of  FIG. 1 . Here and in the following discussion, functional operation or functional memory refers to an operational SRAM memory where data is written into each memory cell through digital write circuitry and read out from each memory cell by amplifying data signals on bit lines to digital levels through differential or single-ended sense amplifiers. This is in contrast to simpler test structures. The memory cell includes a 6-transistor (6T) latch portion  202  and a 2-transistor (2T) buffer portion  200 . The 6T latch portion is connected between write bit line true (WBLT)  206  and complementary write bit line bar (WBLB)  208 . Gates of N-channel access transistors are connected to write word line (WWL)  212 . The 2T buffer includes an N-channel access transistor having a gate connected to read word line (RWL)  210  and a driver or sense N-channel transistor having a gate connected to a storage node SNB of the 6T latch portion. RWL  210  and WWL  212  are driven by inverters  230  and  232 , respectively, and powered by VDDWL. The associated I/O circuitry includes 2T read amplifier  214  and 6T amplifier  216 . An output signal on RBL is amplified by the 2T read amplifier  214 . Correspondingly, an output signal from the latch portion  202  on WBLT and WBLB is amplified by the 6T amplifier  216 . Output signals from 2T read amplifier  214  and 6T amplifier  216  are applied to multiplex circuit  218 . Multiplex circuit  218  is coupled to receive mode signal (RBF). When RBF is high, mulitplex circuit  218  applies the output signal from the 2T read amplifier to multiplexers  220 ,  222 , and output terminal Qout  314 . Alternatively, when RBF is low, mulitplex circuit  218  applies the output signal from the 6T amplifier to multiplexers  220 ,  222 , and output terminal Qout  314 . Of course the number of multiplex circuits may vary depending on the organization of the memory circuit. Also, blocks  214  and  216  may each have one or more levels of column multiplexers. 
     Independently reading from the 2T buffer and the 6T latch portion is highly advantageous. If a read error occurs when reading only from the 2T buffer, there is no indication whether the 6T latch portion or the 2T buffer caused the error. Moreover, there is no indication that the latch portion was even written correctly. The ability to bypass the 2T buffer and read directly from the 6T latch portion indicates whether the latch portion correctly received and stored a data signal. Furthermore, if the latch portion does yield the correct data signal, then the 2T buffer is the likely cause of any read error. 
     Turning now to  FIG. 3 , there is a high level schematic diagram of an 8T memory cell with associated input/output (I/O) direct bit line access (DBLA) circuitry that may be used in the SRAM of  FIG. 1 . Here and in the following discussion, the same reference numerals are used to identify the same circuit elements. The 8T memory cell is the same as previously described with respect to  FIG. 2 . The 6T latch portion includes transistors T 1  through T 6 . The 2T buffer portion includes access or pass gate transistor T 7  and driver transistor T 8 . The I/O circuit also includes analog multiplexers  300  through  312 . These analog multiplexers are bidirectional and conduct a range of analog voltages and currents during transistor characterization as will be described in detail. They are typically formed by a P-channel transistor and an N-channel transistor having parallel current paths as is well known in the art. Other analog multiplex circuits as well known in the art may also be used. As previously discussed, the number of multiplexers may vary according to the organization of the memory circuit. Also, blocks  300 ,  302 , and  308  may each have one or more levels of column multiplexers. 
     Multiplex circuit  304  is coupled to receive mode signal (RBF). When RBF is high, mulitplex circuit  304  couples data input pad Din to RBL. This applies the analog voltage at external terminal Din to RBL. When RBF is low, and mulitplex circuit  304  couples data input terminal Din to WBLT. Multiplex circuits  308  through  312  couple external terminal Qout to WBLB. In each case, the multiplex circuits are designed to be much more conductive than the memory cell transistors so that their on resistance is negligible. 
     Referring now to  FIG. 4 , there is a schematic diagram of an embodiment of word line driver circuitry that may be used in the SRAM of  FIG. 1 . Here and in the following discussion, a “Z” suffix on a signal name indicates an active low signal. For example, word line enable (WLEZ) enables NOR gates  400  and  402  when low. In a similar manner read word line enable (RWLEZ) produces a high level output from enabled NOR gate  400  when low. Likewise, write word line enable (WWLEZ) produces a high level output from enabled NOR gate  402  when low. A high level from NOR gate  400  is buffered by inverters  404  and  230  to produce a read word line (RWL) signal at the VDDWL level. A high level from NOR gate  402  is buffered by inverters  406  and  232  to produce a write word line (WWL) signal at the VDDWL level. An advantage of this word line driver circuitry is that both RWLEZ and WWLEZ may be low at the same time in a test mode to simultaneously produce high levels of RWL and WWL as will be discussed in detail. 
     Two other points regarding the word line driver circuitry of  FIG. 4  are worthy of mention. First, when a high voltage level greater than nominal VDD is required for either RWL or WWL, VDD must be increased together with VDDWL to prevent simultaneously turning on P-channel and N-channel transistors of inverters  230  or  232 . Second, when VDDWL is used as a gate voltage to characterize N-channel transistors, the low voltage output level from inverters  230  and  232  is limited to about 0.2 V with P-channel transistors of each inverter operating in a sub threshold region. This is typically below the threshold voltage of the N-channel transistors and is, therefore, adequate. If a lower output voltage is necessary, one may add N-channel transistors between VDDWL and RWL and between VDDWL and WWL with their gates driven by the outputs of NOR gates  400  and  402 , respectively. 
     Turning now to  FIG. 5 , there is a schematic diagram of an embodiment of column data selection circuitry for functional operation of the SRAM memory of  FIG. 1 . The 2T read signal is from read amplifier  214  and the 6T read signal is from amplifier  216 . ( FIG. 2 ). Series connected delay latches  500  and  502  form a master-slave flip flop to latch the read data and apply it to CMOS pass gate  504  in response to latch control signal LATEZ. The 6T read signal is applied directly to CMOS pass gate  506 . Taken together, CMOS pass gates  504  and  506  and associated inverters form multiplex circuit  218  of  FIG. 2 . When mode signal RBF is low, CMOS pass gate  504  is off and CMOS pass gate  506  produces the 6T read signal as SAOUT. Correspondingly, when mode signal RBF is high, CMOS pass gate  506  is off and CMOS pass gate  504  produces the 2T read signal as SAOUT. As previously discussed, this arrangement is highly advantageous in determining the cause of any read errors that may occur in a functional SRAM without the time and expense of physical failure analysis. 
     Referring to  FIG. 6 , there is a schematic diagram of an embodiment of column data selection circuitry for direct bit line access (DBLA) operation of the SRAM memory of  FIG. 1 . CMOS pass gates  300  and  302  form the analog multiplexer  304  of  FIG. 3 . Parametric test enable signal (PTE) controls operation of the circuit and is high in a DBLA test mode. Complementary mode control signals RBFT and RBFZ enable either CMOS pass gate  300  or CMOS pass gate  302  when PTE is high. For example, when PTE is high CMOS pass gate  308  is on and connects external terminal Qout to WBLB. The high level of PTE enables NAND gates  602  and  606 . When RBFT is low and RBFZ is high, CMOS pass gate  300  is off. The high level of RBFZ produces a low level output from NAND gate  606  and a high level output from inverter  604  to turn on CMOS pass gate  302 . Thus, external terminal Din is connected to WBLT. Alternatively, when RBFT is high and RBFZ is low, CMOS pass gate  302  is off. The high level of RBFT produces a low level output from NAND gate  602  and a high level output from inverter  600  to turn on CMOS pass gate  300 . Thus, external terminal Din is connected to RBL. Of course, the number of such analog multiplex circuits may vary according to the organization and size of the SRAM memory. These analog multiplex circuits are highly advantageous in providing direct bit line access (DBLA) between external terminals and internal read and write bit lines. This permits application of analog voltage levels to individual transistors of each memory cell for characterization and parametric testing as will be discussed in detail. Moreover, such characterization reveals the cause of memory cell failures and marginal operation without the time and expense of physical failure analysis. 
     Referring now to  FIGS. 7A through 7E , there are simplified schematic diagrams showing various tests that may be performed on a 2-transistor (2T) buffer portion of an 8T memory cell using DBLA of the present invention. These tests allow the measurements of the current-voltage characteristics, threshold voltage, leakage, and conductivity of each transistor in the 2T buffer portion as will be described in detail. Operation of these tests will be explained with reference to corresponding rows A through E of  FIG. 8 . For the purpose of illustration, 1.2 V is a nominal voltage and 1.6 V is a high voltage for operation of the SRAM memory. In the following discussion, positive current flow is illustrated in the direction of the arrows of  FIGS. 7A through 7E . Current flow may also be measured in the opposite direction by polarity reversal of drain and source voltages as will be apparent to one of ordinary skill in the art having access to the instant specification. 
       FIG. 7A  and row A of  FIG. 8  illustrate conditions for read current (Iread) measurement of the 2T buffer of a selected memory cell. Here, read current refers to the ability of series transistors T 7  and T 8  to sink current in a read operation. First the true storage node SNT of the memory cell ( FIG. 3 ) is initialized to logic 0 and the complementary storage node SNB is initialized to logic 1. VDDA is set to 1.2 V. This places 1.2 V on the gate of transistor T 8 . RWL is enabled with VDDWL at 1.2 V to place 1.2 V on the gate of transistor T 7 . External terminal Din receives 1.2 V and read current A ( FIG. 7A ) is measured into the memory from Din. 
       FIG. 7B  and row B of  FIG. 8  illustrate conditions for driver transistor current-voltage measurement of the 2T buffer of a selected memory cell. Here, drive current refers to the current transistor T 8  is able to sink for a range of drain and gate voltages. Both RWL and WWL are enabled with 1.6 V on VDDWL. This high voltage makes transistor T 7  much more conductive than transistor T 8  so that measured current is due to T 8 . VDDA is set to the same value as Qout. A range of drain voltages for T 8  is applied to external terminal Din and a range of gate voltages for T 8  is applied to external terminal Qout. At each set of voltages drive current B ( FIG. 7B ) is measured into the memory from Din. 
       FIG. 7C  and row C of  FIG. 8  illustrate conditions for pass gate transistor current-voltage measurement of the 2T buffer of a selected memory cell. Here, pass gate current refers to the current transistor T 7  is able to pass for a range of drain and gate voltages. RWL is enabled and a range of gate voltages for T 7  is applied to RWL via VDDWL. Array voltage VDDA is set to 1.6 V. This high voltage makes transistor T 8  much more conductive than transistor T 7  so that measured current is due to T 7 . A range of drain voltages for T 7  is applied to external terminal Din. At each set of voltages pass gate current C ( FIG. 7C ) is measured into the memory from Din. 
       FIG. 7D  and row D of  FIG. 8  illustrate conditions for buffer leakage measurement of the 2T buffer of a selected memory cell. Here, buffer leakage current is the leakage current through transistor T 8  when it is off and transistor T 7  is on. First the true storage node SNT of the memory cell ( FIG. 3 ) is initialized to logic 1 and the complementary storage node SNB is initialized to logic 0. VDDA is set to 1.2 V. This places 0.0 V on the gate of transistor T 8 . RWL is enabled with VDDWL at 1.2 V to place 1.2 V on the gate of transistor T 7 . External terminal Din receives 0.6 V and leakage current D ( FIG. 7D ) is measured into the memory from Din. 
       FIG. 7E  and row E of  FIG. 8  illustrate conditions for an open circuit test of the 2T buffer of a selected memory cell. This is to test whether the 2T buffer is open when both T 7  and T 8  are strongly turned on. First the true storage node SNT of the memory cell ( FIG. 3 ) is initialized to logic 0 and the complementary storage node SNB is initialized to logic 1. VDDA is set to 1.4 V. This places 1.4 V on the gate of transistor T 8 . RWL is enabled with VDDWL at 1.4 V to place 1.4 V on the gate of transistor T 7 . External terminal Din receives 0.2 V and current E ( FIG. 7E ) is measured into the memory from Din. 
     Referring next to  FIGS. 9A through 9F , there are simplified schematic diagrams showing various tests that may be performed on a 6-transistor (6T) latch portion of an 8T memory cell using DBLA of the present invention. These tests allow the measurements of the current-voltage characteristics, threshold voltage, leakage, and conductivity of each transistor in the 6T latch portion as will be described in detail. Operation of these tests will be explained with reference to corresponding rows A through F of  FIG. 10 . For the purpose of illustration, 1.2 V is a nominal voltage and 1.6 V is a high voltage for operation of the SRAM memory. In the following discussion, positive current flow is illustrated in the direction of the arrows of  FIGS. 9A through 9F . Characterization of individual transistors of the left half of the 6T memory cell is explained in the following discussion. By symmetry, characterization of individual transistors of the right half of the 6T memory cell is performed in a similar manner with appropriate voltages applied to external terminals. 
     To characterize transistor T 5  in a read direction VDD, VNWA, VDDA and external terminal Qout are held at 1.6 V. Thus, the gate of transistor T 1  is at 1.6 V. This high voltage makes transistor T 1  much more conductive than transistor T 5  so that measured current is due to T 5 . VSS, VSBA, and VSSA are set to 0.0 V. A range of drain voltages for T 5  is applied to external terminal Din and a range of gate voltages for T 5  is applied to VDDWL. At each set of voltages current A ( FIG. 9A ) is measured into the memory from Din. 
     To characterize transistor T 5  in a write direction VDD, VNWA, VDDA and external terminal Qout are again held at 1.6 V. Thus, the gate of transistor T 1  is at 1.6 V. This high voltage makes transistor T 1  much more conductive than transistor T 5  so that measured current is due to T 5 . VSS, VSBA, and external terminal Din are set to 0.0 V. A range of drain voltages for T 5  is applied to external terminal VSSA and a range of gate voltages for T 5  is applied to VDDWL. At each set of voltages current B ( FIG. 9B ) is measured into the memory from Din. 
     To characterize transistor T 1  in a forward direction WWL is enabled and 1.6 V is applied to VDD, VNWA, and VDDWL. Thus, the gate of transistor T 5  is at 1.6 V. This high voltage makes transistor T 5  much more conductive than transistor T 1  so that measured current is due to T 1 . VSS, VSBA, and VSSA are set to 0.0 V. A range of drain voltages for T 1  is applied to external terminal Din and a range of gate voltages for T 1  is applied to VDDA and external terminal Qout. At each set of voltages current C ( FIG. 9C ) is measured into the memory from Din. 
     To characterize transistor T 1  in a reverse direction WWL is enabled and 1.6 V is applied to VDD, VNWA, and VDDWL. Thus, the gate of transistor T 5  is at 1.6 V. This high voltage makes transistor T 5  much more conductive than transistor T 1  so that measured current is due to T 1 . VSS, VSBA, and external terminal Din are set to 0.0 V. A range of drain voltages for T 1  is applied to VSSA and a range of gate voltages for T 1  is applied to VDDA and external terminal Qout. At each set of voltages current D ( FIG. 9D ) is measured into the memory from Din. 
     To characterize transistor T 3  in a forward direction WWL is enabled and 1.6 V is applied to VDD and VDDWL. Thus, the gate of transistor T 5  is at 1.6 V. This high voltage makes transistor T 5  much more conductive than transistor T 3  so that measured current is due to T 3 . VSSA and external terminal Qout are set to 0.0 V. A range of drain voltages for T 3  is applied to external terminal Din and a range of source voltages for T 3  is applied to VDDA and VNWA. Here, the gate to source voltage of T 3  is a difference between 0.0 V and the applied source voltage at VDDA while the drain to source voltage of T 3  is a difference between the applied drain voltage at Din and the source voltage at VDDA. At each set of voltages current E ( FIG. 9E ) is measured into the memory from Din. 
     To characterize transistor T 3  in a reverse direction WWL is enabled and 1.6 V is applied to VDD and VDDWL. Thus, the gate of transistor T 5  is at 1.6 V. This high voltage makes transistor T 5  much more conductive than transistor T 3  so that measured current is due to T 3 . VSS, VSBA and VDDA are set to 0.0 V. A range of source voltages for T 3  is applied to external terminal Din, VNWA, and VSSA. Here, the gate to source voltage of T 3  is a difference between the applied source voltage at external terminal Din and the applied gate voltage at external terminal Qout, while the drain to source voltage of T 3  is a difference between applied drain voltage at VDDA and the source voltage at external terminal Din. At each set of voltages current F ( FIG. 9F ) is measured into the memory from Din. 
     Still further, while numerous examples have thus been provided, one skilled in the art should recognize that various modifications, substitutions, or alterations may be made to the described embodiments while still falling within the inventive scope as defined by the following claims. For example, previously described voltages and test patterns are given by way of example only and are not intended to limit the scope of the claimed invention. Numerous design alternatives, test methods, and test voltages are possible for alternative memory designs such as using 8-transistor or other buffered-read SRAM cells and various processes. Other combinations will be readily apparent to one of ordinary skill in the art having access to the instant specification.