Patent Publication Number: US-2006007806-A1

Title: Apparatus and method for generating a tracking error signal in an optical disc drive

Description:
BACKGROUND OF THE INVENTION  
      1. Field of the Invention  
      The present invention relates to an optical disc drive, and more particularly, to an apparatus for generating a tracking error signal in the optical disc drive.  
      2. Description of the Prior Art  
      Optical discs are storage systems used nowadays. Data is recorded according to the pits in the optical disc tracks. A servo control system of an optical disc drive reads the data by focusing a laser light outputted from a laser light diode on a correct position of the track and detecting the reflection light beam of the laser light.  
      An optical sensor on a pick-up head (PUH) of the optical disc drive detects signals A, B, C, D reflected from different positions of the track and generates a tracking error signal TE. The servo control system determines whether the focus point of the laser light outputted by the laser light diode diverges from the track of the optical disc according to the changes in the tracking error signal TE.  
      Please refer to  FIG. 1 .  FIG. 1  is a schematic diagram of a prior art for generating a tracking error signal TE in an optical disc drive. The signals A and C detected by the optical sensor of the PUH are processed by the adder  112 , the equalizer  122 , and the slicer  132  and then the digitalized A and C are inputted to the phase detector  140 . The signals B and D detected by the optical sensor are processed by the adder  114 , the equalizer  124 , and the slicer  134  and then the digitalized B and D are inputted to the phase detector  140 . The phase detector  140  detects the phase difference between the digitalized signal A+C and the digitalized signal B+D, and the output signal from the phase detector  140  is then processed by the low pass filters (LPF)  152  and  154  and the differential amplifier  160  for generating the tracking error signal TE. The larger the phase difference between the signals A+C and B+D, the wider the signal pulse width outputted from the phase detector  140  is. Since the prior art determines the phase difference according to a pulse width, a high sampling rate to convert the analog signal into the digital signal is required for accurate tracking error signal TE and the backend circuits must operate in a higher frequency.  
     SUMMARY OF THE INVENTION  
      One objective of the claimed invention is to provide an apparatus and a method thereof, for generating a tracking error signal with high resolution and lower sampling rate.  
      The present invention discloses an apparatus for generating a tracking error signal in an optical disc drive. The apparatus comprises an optical detection module for generating a first analog signal and a second analog signal according to at least one reflection light beam of a laser light emitted to an optical disc; an ADC module coupled to the optical detection module for sampling the first and second analog signals in a first sampling time to generate a first digital value and a second digital value respectively, and sampling the first and second analog signals in a second sampling time to generate a third digital value and a fourth digital value respectively; a phase detection module coupled to the ADC module for calculating a digital phase difference value according to the first, second, third and fourth digital values; and a filter module coupled to the phase detection module for generating the tracking error signal according to the digital phase difference.  
      The present invention further discloses a method for generating a tracking error signal in an optical disc drive. The method comprises generating a first analog signal and a second analog signal according to at least one reflection light beam of a laser light emitted to an optical disc; converting the first and second analog signals into a first digital value and a second digital value respectively in a first sampling time; converting the first and second analog signals into a third digital value and a fourth digital value respectively in a second sampling time; calculating a digital phase difference value according to the first, second, third and fourth digital values; and generating the tracking error signal according to the digital phase difference.  
      These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       FIG. 1  is a prior art apparatus for generating a tracking error signal in an optical disc drive.  
       FIG. 2  is an apparatus according to an embodiment of the present invention.  
       FIG. 3  is an example of a waveform diagram of input and output signals of the ADC module shown in  FIG. 2 .  
       FIG. 4  is an apparatus in the phase detection module of  FIG. 2  for generating a DC offset compensating signal and a gain control signal according to an embodiment of the present invention.  
       FIG. 5  is a flowchart describing a method according to the present invention. 
    
    
     DETAILED DESCRIPTION  
      Please refer to  FIG. 2 .  FIG. 2  is a schematic diagram of an apparatus for generating a tracking error signal in an optical disc drive according to an embodiment of the present invention. The present invention comprises: an optical detection module  210 , a DC level adjusting module  220 , a gain adjusting module  230 , an ADC module  250 , a phase detection module  260  and a filter module  270 . The optical detection module  210  generates a first analog signal A+C and a second analog signal B+D according to signals A, B, C, and D generated by detecting the reflection light beam of a laser light emitted to an optical disc. The DC level adjusting module  220  utilizes the first and second DC offset compensating signals O 1  and O 2  to adjust DC levels of the first signal A+C and the second analog signal B+D respectively. The gain adjusting module  230  adjusts the first analog signal A+C and the second analog signal B+D according to the first gain control signal G 1  and the second gain control signal G 2  respectively. The ADC module  250  comprises two multi-bit ADCs  252  and  254  for generating the first digital signal S 1  and the second digital signal S 2  according to the first analog signal A+C and the second analog signal B+D respectively, wherein each sample point of the first and second digital signals S 1  and S 2  comprises a plurality of bits. The phase detection module  260  generates a digital phase difference signal Se according to the first and second digital signals S 1  and S 2 . The filter module  270  is utilized to filter the digital phase difference signal Se to generate the needed tracking error signal TE, and the filter module  270  can be a low pass filter.  
      The phase detection module  260  of the present embodiment detects the positive and negative sign of the first and second digital signals S 1  and S 2  to determine whether zero crossing occurs between which sample points and tp determine the degree of the phase difference between the signals S 1  and S 2 . Since the first digital signal S 1  corresponds to the first analog signal A+C and the second digital signal S 2  corresponds to the second analog signal B+D, a lead/lag situation between the first analog signal A+C and the second analog signal B+D can be determined according to the phase difference between the signals S 1  and S 2 . For example, assume the first and second digital signals S 1  and S 2  of a first digital value S 1 ( n − 1 ) and a second digital value S 2 ( n − 1 ) respectively in a first sampling time, and of a third digital value S 1 ( n ) and a fourth digital value S 2 ( n ) in a second sampling time. The phase detection module  260  determines whether a zero crossing exists between the first and second sampling times of the first and second digital signals S 1  and S 2  by comparing a predetermined value  0  with the first, second, third, and fourth digital values S 1 ( n − 1 ), S 2 ( n − 1 ), S 1 ( n ), S 2 ( n ). If the first digital value S 1 ( n − 1 ) is less than zero and the third digital value S 1 ( n ) is larger than zero, a zero crossing occurs from negative to positive between the first and second sampling times of the first digital signal S 1 . If the second digital value S 2 ( n − 1 ) is less than zero and the fourth digital value S 2 ( n ) is larger than zero, a zero crossing occurs from negative to positive between the first and second sampling times of the second digital signal S 2 . In the above mentioned situations, the phase detection module  260  utilizes the value of the sum of the first and third digital values S 1 ( n − 1 ), S 1 ( n ) minus the sum of the second and fourth digital values S 2 ( n − 1 ), S 2 ( n ) as a phase difference value Se(n). If the phase difference value Se(n) is positive, the first analog signal A+C precedes the second analog signal B+D. If the phase difference value Se(n) is negative, the second analog signal B+D precedes the first analog signal A+C. Whether the first analog signal A+C precedes the second analog signal B+D, the larger an absolute value of the phase difference value Se(n), the larger the phase difference between the first analog signal A+C and the second analog signal B+D is, and the smaller the absolute value of the phase difference value Se(n), the smaller the phase difference between the first analog signal A+C and the second analog signal B+D is.  
      Similarly, if the first digital value S 1 ( n − 1 ) is larger than zero and the third digital value S 1 ( n ) is smaller than zero, a zero crossing occurs from positive to negative between the first and second sampling times of the first digital signal S 1 . If the second digital value S 2 ( n − 1 ) is larger than zero and the fourth digital value S 2 ( n ) is smaller than zero, a zero crossing occurs from positive to negative between the first and second sampling times of the second digital signal S 2 . In the above mentioned two situations, the phase detection module  260  utilizes the value of the sum of the second and fourth digital values S 2 ( n − 1 ) and S 2 ( n ) minus the sum of the first and third digital values S 1 ( n − 1 ) and S 1 ( n ) as a phase difference value Se(n). If the phase difference value Se(n) is positive, it the first analog signal A+C precedes the second analog signal B+D, and if the phase difference value Se(n) is negative, the second analog signal B+D precedes the first analog signal A+C. Whether the first analog signal A+C precedes the second analog signal B+D, the greater an absolute value of the phase difference value Se(n), the greater the phase difference between the first analog signal A+C and the second analog signal B+D is, and the smaller the absolute value of the phase difference value Se(n), the smaller the phase difference between the first analog signal A+C and the second analog signal B+D is.  
       FIG. 3  is an example of a waveform diagram of input and output signals of the ADC module shown in  FIG. 2 . In this example, the first analog signal A+C precedes the second analog signal B+D. Since S 2 ( n − 1 )&lt;0 and S 2 ( n )&gt;0, the phase detection module  260  determines that a zero crossing occurs between the sample points (n− 1 ) and n of the signal S 2 , and hence the phase detection module  260  utilizes [S 1 ( n − 1 )+S 1 ( n )−S 2 ( n − 1 )−S 2 ( n )] as the value of Se(n). The Se(n) is positive at this moment, meaning that the phase of the first analog signal A+C precedes the phase of the second analog signal B+D. Similarly, if S 1 ( n )&gt;0 and S 1  ( n + 1 )&lt;0, the phase detection module  260  determines that a zero crossing occurs from positive to negative between the sample points n and (n+ 1 ) of the signal S 1 , and hence the phase detection module  260  utilizes [S 2 ( n )+S 2 ( n + 1 )−S 1 ( n )−S 1 ( n + 1 )] as the value of Se(n+ 1 ). In this case, Se(n+ 1 ) is positive at this moment, meaning that the phase of the first analog signal A+C precedes the phase of the second analog signal B+D. In other situations, the value of Se (n) are set to zero.  
      Since the ADC module  250  is a multi-bit ADC module, the larger the phase difference between the two signals S 1  and S 2  of the above two situations, the larger the digital phase difference signal Se is, meaning that the pulse height of the signal is higher, and hence the phase difference between the signals S 1  and S 2  is contained in the digital phase difference signal Se outputted from the phase detection module  260 . In this embodiment, the tracking error signal TE can be generated by determining and filtering with the LPF  270  the digital phase difference signal Se comprising a plurality of digital phase differences Se (n) at a plurality of sampling times.  
      The multi-level digital signals S 1  and S 2  are utilized for calculating the related level difference between the sampled A+C signal and B+D signals in order to obtain the corresponding phase difference. Therefore, the sampling rate is efficiently lowered. For example, the sampling rate can be lowered to 1/2T, wherein T is a period corresponding to a channel bit of the optical disc. The signal resolution required for the tracking error signal is also achieved.  
      Generally, the analog signals A+C and B+D generated by the optical detection module  210  includes DC offset and need to be amplified properly before being inputted to the ADC module  250 . Accordingly, the embodiment comprises the DC level adjusting module  220  for adjusting the DC offsets of the analog signals A+C and B+D, and the gain adjusting module  230  for amplifying the analog signals A+C and B+D. In this embodiment, the phase detection module  260  further comprises the apparatus shown in  FIG. 4 , the sign decision module  410  and the filter module  420  for generating the first and second DC offset compensating signals O 1  and O 2 , and the limitation decision module  430  and the filter module  440  for generating the first and second gain control signals G 1  and G 2 .  
      In this embodiment, the sign decision module  410  performs a sign operation according to the signals S 1  and S 2  respectively for generating a first sign signal SS 1  and a second sign signal SS 2 . The filter module filters the signals SS 1  and SS 2  respectively for generating the DC offset compensating signals O 1  and O 2 . When the corresponding value of the signal S 1  is larger than zero, the first sign signal SS 1  generated by the sign decision module  410  equals positive one. When the corresponding value of the signal S 1  is smaller than zero, the first sign signal SS 1  generated by the sign decision module  410  equals negative one. Obviously, if the DC offset of the analog signal A+C is positive, the first sign signal SS 1  comprises more positive values (+1) than negative values (−1). Accordingly, the filter module offers a positive DC offset compensating signal O 1  to the adder  220  for compensating the positive DC offset of the analog signal A+C. On the contrary, if the DC offset is negative, the signal SS 1  comprises more negative values (−1) than positive values (−1). Therefore, the filter module offers a negative DC offset compensating signal O 1  to the adder  220  for compensating the negative DC offset of the analog signal A+C.  
      In this embodiment, the limitation decision module  430  determines whether the signals S 1  and S 2  reach an upper limitation value or a lower limitation value to generate a first decision signal LS 1  and a second decision signal LS 2  respectively. The filter module filters the signals LS 1  and LS 2  to generate the gain control signals G 1  and G 2  respectively. Suppose the ADC module  250  is a three-bit ADC module. When the corresponding value of the signal S 1  reaches the upper limitation value  111  or the lower limitation value  000 , the first decision signal LS 1  generated by the limitation decision module  430  equals a first output value α. When the corresponding value of the signal S 1  does not reach the upper limitation value  111  or the lower limitation value  000 , the first decision signal LS 1  generated by the limitation decision module  430  equals a first output value β. If the gain of the amplifier  230  is too large, the larger part of the absolute value of the amplified analog signal A+C will exceed the range capable of conversion of the ADC  252 . Accordingly, more upper limitation values  111  or lower limitation values  000  are included in the signal S 1 , and the first decision signal LS 1  has more α values, meaning that the system can lower the gain of the amplifier  230 . On the contrary, if the gain of the amplifier  230  is too small, larger parts of the amplified analog signal A+C lies in the convertible range of the ADC  252 . Accordingly, less upper limitation values  111  or lower limitation values  000  are included in the signal S 1 . In this situation, the first decision signal LS 1  has more β values, meaning that the system can increase the gain of the amplifier  230 . The values α and β are designable.  
      Please note that the signals A and B can also be the first and second analog signals respectively or the signals C and D can be the first and second analog signals respectively.  
      Please refer to  FIG. 5 .  FIG. 5  is a flowchart for generating a tracking error signal in an optical disc drive according to the present invention. Each step is described as follows.  
      Step  510 : Generate a first analog signal and a second analog signal according to a reflection light beam of a laser light emitted to an optical disc. In the embodiment, the first analog signal corresponds to the signals A and C generated by the optical sensor, and the second analog signal corresponds to the signals B and D generated by the optical sensor.  
      Step  520 : Convert the first and second analog signals into a first digital signal S 1  and a second digital signal S 2  respectively. The first and second digital signals S 1  and S 2  are equal to a first digital value S 1 ( n − 1 ) and a second digital value S 2 ( n − 1 ) respectively in a first sampling time, and are equal to a third digital value S 1 ( n ) and a fourth digital value S 2 ( n ) respectively in a second sampling time.  
      Step  530 : Calculate a digital phase difference Se(n) according to the first, second, third, and fourth digital values S 1 ( n − 1 ), S 2 ( n − 1 ), S 1 ( n ), S 2 ( n ) respectively. A digital phase difference signal Se includes a plurality of digital phase differences Se(n) generated at different sampling times. The embodiment utilizes the signals S 1 ( n − 1 )+S 1 ( n )−S 2 ( n − 1 )−S 2 ( n ) as the digital phase differences Se(n) if the signal S 1 ( n − 1 ) is less than zero and the signal S 1 ( n ) is larger than zero or if the signal S 2 ( n − 1 ) is less than zero and the signal S 2 ( n ) is larger than zero. The embodiment utilizes the signals S 2 ( n − 1 )+S 2 ( n )−S 1 ( n − 1 )−S 1 ( n ) as the digital phase differences Se(n) if the signal S 1 ( n − 1 ) is larger than zero and the signal S 1 ( n ) is less than zero or if the signal S 2 ( n − 1 ) is larger than zero and the signal S 2 ( n ) is less than zero. In other situations, the digital phase differences Se(n) equals zero.  
      Step  540 : Generate the tracking error signal TE according to the digital phase difference signal Se.  
      The DC levels of the first and second analog signals can be adjusted dynamically in the above-mentioned steps. The present invention further comprises the following steps:  
      Step  610 : Perform a sign operation on the first and second digital signals S 1  and S 2  and generate a first sign signal SS 1  and a second sign signal SS 2 .  
      Step  620 : Filter the first and second sign signals SS 1  and SS 2  to generate a first DC offset compensating signal O 1  and a second DC offset compensating signal O 2  respectively.  
      Step  630 : Adjust the DC levels of the first and second analog signals according to the first and second DC offset compensating signals O 1  and O 2 .  
      Similarly, the gains of the first and second analog signals can be adjusted dynamically in the above-mentioned steps. The present invention further comprises the following steps:  
      Step  710 : Generate a first decision signal LS 1  and a second decision signal LS 2  according to the first and second digital signals S 1  and S 2 . When a digital signal reaches an upper limitation value or a lower limitation value, the decision signal corresponding to the digital signal has a first output value α. When the digital signal does not reach the upper limitation value or the lower limitation value, the decision signal corresponding to the digital signal has a second output value β.  
      Step  720 : Filter the first and second decision signals LS 1  and LS 2  to generate a first gain control signal G 1  and a second gain control signal G 2  respectively.  
      Step  730 : Amplify the first and second analog signals according to the first and second gain control signals G 1  and G 2 .  
      Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.