Patent Publication Number: US-9853125-B2

Title: Vertical tunneling field-effect transistor cell and fabricating the same

Description:
PRIORITY DATA 
     The present application is a divisional application of U.S. patent application Ser. No. 13/745,459, filed Jan. 18, 2013, which is incorporated herein by reference in its entirety. 
    
    
     CROSS-REFERENCE 
     This patent is related to U.S. Ser. No. 13/745,225, filed Jan. 18, 2103, now U.S. Pat. No. 8,754,470, entitled “A Vertical Tunneling Field-Effect Transistor Cell And Fabricating The Same,” which is hereby incorporated by reference in its entirety. 
     BACKGROUND 
     The semiconductor integrated circuit industry has experienced rapid growth in the past several decades. Technological advances in semiconductor materials and design have produced increasingly smaller and more complex circuits. These material and design advances have been made possible as the technologies related to processing and manufacturing have also undergone technical advances. In the course of semiconductor evolution, the number of interconnected devices per unit of area has increased as the size of the smallest component that can be reliably created has decreased. 
     However, as the size of the smallest component has decreased, numerous challenges have risen. As features become closer, current leakage can become more noticeable, signals can crossover more easily, and power usage has become a significant concern. The semiconductor integrated circuit industry has produced numerous developments in effort to continue the process of scaling. One of the developments is the potential replacement or supplementation of the conventional MOS field-effect transistor by the tunneling field-effect transistor (TFET). 
     Tunneling FETs are promising devices that may enable further scaling of power supply voltage without substantially increasing off-state leakage currents due to its sub-60 mV/dec subthreshold swing. However, existing TFETs have not been satisfactory in every respect. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1  is a flowchart of an example method for fabricating a semiconductor device constructed according to various aspects of the present disclosure. 
         FIGS. 2A, 3 to 9  are cross-sectional views of an example semiconductor device at fabrication stages constructed according to the method of  FIG. 1 . 
         FIG. 2B  is a top, schematic view of a portion of the semiconductor device of  FIG. 2A . 
     
    
    
     DETAILED DESCRIPTION 
     It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the performance of a first process before a second process in the description that follows may include embodiments in which the second process is performed immediately after the first process, and may also include embodiments in which additional processes may be performed between the first and second processes. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity. Furthermore, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. 
       FIG. 1  is a flowchart of one embodiment of a method  100  of fabricating one or more TFET devices according to aspects of the present disclosure. The method  100  is discussed in detail below, with reference to a TFET device  200  shown in  FIGS. 2A to 9  for the sake of example. 
     The method  100  begins at step  102  by providing a substrate  210 . The substrate  210  includes silicon. In alternative embodiments, the substrate  210  may include germanium, silicon germanium, gallium arsenide, silicon carbide, indium arsenide, indium phosphide, gallium arsenic phosphide, gallium indium, or other appropriate semiconductor materials. Alternatively and for some embodiments, the substrate  210  may include an epitaxial layer. For example, the substrate  210  may have an epitaxial layer overlying a bulk semiconductor. Further, the substrate  210  may be strained for performance enhancement. For example, the epitaxial layer may include a semiconductor material different from those of the bulk semiconductor such as a layer of silicon germanium overlying bulk silicon or a layer of silicon overlying a bulk silicon germanium formed by a process including selective epitaxial growth (SEG). Furthermore, the substrate  210  may include a semiconductor-on-insulator (SOI) structure such as a buried dielectric layer. Also alternatively, the substrate  210  may include a buried dielectric layer such as a buried oxide (BOX) layer, such as that formed by a method referred to as separation by implantation of oxygen (SIMOX) technology, wafer bonding, SEG, or other appropriate methods. In fact various embodiments may include any of a variety of substrate structures and materials. The substrate  210  may also include various p-type doped regions and/or n-type doped regions, implemented by a process such as ion implantation and/or diffusion. Those doped regions include n-well and p-well. 
     Referring to  FIGS. 1 and 2A , the method  100  proceeds to step  104  by etching the substrate  210  to form a frustoconical protrusion structure  220 , which protrudes out of the plane of substrate  210 . The frustoconical protrusion structure  220  is referred as a core structure  220 . The core structure  220  may be formed by lithography and etching processes. In one embodiment, a hard mask layer  215  is deposited on the substrate  210  first. The hard mask  215  includes silicon oxide, silicon nitride, silicon oxynitride, or any other suitable dielectric material. The hard mask  215  may be patterned by lithography and etching processes to define the core structure  220  with a first width w 1 . The substrate  210  is etched by using the patterned hard mask  215  as an etching mask to form the core structure  220 . The etch process may include wet etch, dry etch, or a combination thereof. The core structure  220  can be formed with sidewalls having an angle α with the planar surface of the substrate  210  ranging from approximately 45 degrees to around 90 degrees. 
     In one embodiment, the core structure  220  is formed as a cylinder shape. A top view of the cylinder core structure  220  is shown in  FIG. 2B . The first width w 1  is in a range from 5 nm to 50 nm. Alternatively, the core structure  220  is formed as square-column, oval cylinder, rectangular column, hexagonal column, or other polygon-column shape. 
     Referring to  FIGS. 1 and 3 , the method  100  proceeds to step  106  by forming isolation features  230  on the substrate  210 , including between each core structure  220 . The isolation features  230  include different structures formed by using different processing technologies. In one embodiment, the isolation features  230  are shallow trench isolation (STI) features. The formation of a STI may include etching a trench in the substrate  210  and filling in the trench with insulator materials such as silicon oxide, silicon nitride, or silicon oxynitride. The filled trench may have a multi-layer structure such as a thermal oxide liner layer with silicon nitride filling the trench. 
     Referring to  FIGS. 1 and 4 , the method  100  proceeds to step  108  by forming a drain region  310  with a second width w 2  on the substrate  210 . The second width w 2  is substantially larger than the first width w 1 . In one embodiment, the drain region  310  is concentric with the core structure  220 . The drain region  310  is formed by doping a predetermined top portion of the substrate  210  by a suitable technique, such as implantation with a patterned photo resist as an implantation mask. In the present embodiment, the drain region  310  is adjacent to the core structure  220 . For a p-type TFET, the drain region  310  may be doped with p-type dopants, such as boron or BF 2 . For an n-type TFET, the drain region  310  may be doped with n-type dopants, such as phosphorus, arsenic, or combinations thereof. After the implantation, one or more annealing processes may be performed for dopant activation. The annealing processes may include rapid thermal anneal (RTA), laser anneal, or other suitable annealing process. As an example, high-temperature anneal includes a “spike” annealing process that has a very short time duration. During the formation, the dopant is diffused up to a bottom portion of the core structure  220  with a first height of h 1 , referred as to a raised drain region  310 . 
     Referring to  FIGS. 1 and 5 , the method  100  proceeds to step  110  by forming a first isolation dielectric layer  410  over the drain region  310  by deposition and recess processes. The first isolation dielectric layer  410  includes silicon oxide, silicon nitride, silicon carbide, oxynitride or other suitable materials. The isolation dielectric layer  410  includes a single layer or multiple layers. The first isolation dielectric layer  410  is deposited by a suitable technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, or combinations thereof. In the present embodiment, the isolation dielectric layer  410  is etched back to a second height h 2 , which is substantial less than the first height h 1  of the raised drain region  310 . The first isolation dielectric layer  410  may be recessed by a selective dry etch, a selective wet etch, or combinations thereof. 
     Referring to  FIGS. 1 and 6 , the method  100  proceeds to step  112  by forming a gate stack  510 . The gate stack  510  includes a planar portion, which is parallel to the surface of substrate  210  and over the first isolation dielectric layer  410 , and a gating surface, which wraps around a middle portion of the core structure  220 . A total width of the gate stack  510 , a third width w 3 , is substantially larger than the first width w 1  of the core structure  220  and less than the second width w 2  of the drain region  310 . In one embodiment, the out-of-plane gating surface of gate stack  510  overlaps a portion of the raised drain region  310 . 
     The gate stack  510  is formed by any suitable process or processes. For example, the gate stack  510  is formed by a procedure including depositing, photolithography patterning, and etching processes. The deposition processes include CVD, PVD, ALD, metalorganic CVD (MOCVD), other suitable methods, and/or combinations thereof. The photolithography patterning processes include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, and/or combinations thereof. The etching process includes a dry etch, a wet etch, or a combination of dry etch and wet etch. The dry etching process may implement fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6 ), chlorine-containing gas (e.g., Cl 2 , CHCl 3 , CCl 4 , and/or BCl 3 ), bromine-containing gas (e.g., HBr and/or CHBR 3 ), iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. The etching process may include a multiple-step etching to gain etch selectivity, flexibility and desired etch profile. 
     Referring also to  FIG. 6 , in one embodiment, the gate stack  510  is a high-k (HK)/metal gate (MG). The HK/MG includes a gate dielectric layer  520  and a MG  530 . The gate dielectric layer  520  may include an interfacial layer (IL) and a high-k (HK) dielectric layer. The IL includes oxide, HfSiO and oxynitride. The HK dielectric layer may include LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3  (STO), BaTiO 3  (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3  (BST), Al 2 O 3 , Si 3 N 4 , oxynitrides (SiON), or other suitable materials. The MG  530  may include a single layer or multi layers, such as a metal layer, a liner layer, a wetting layer, and an adhesion layer. The MG  530  may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, or any suitable materials. 
     In another embodiment, the gate stack  510  is a polysilicon gate stack. The polisilicon gate stack may include a gate dielectric layer and a polysilicon layer deposited over the gate dielectric layer. The gate dielectric layer includes silicon oxide, silicon nitride, or any other suitable materials. 
     Referring to  FIGS. 1 and 7 , the method  100  proceeds to step  114  by forming a second isolation dielectric layer  610  over the first isolation dielectric layer  410 , including over the planar portion of the gate stack  510 . The second isolation dielectric layer  610  is similar in many respects to those discussed above in association with the first isolation dielectric layer  410  in  FIG. 5 . The second isolation dielectric layer  610  is etched back to expose a predetermined height of a top portion of the gating surface of gate stack  510 . In one embodiment, the predetermined height is substantially larger than a thickness of the hard mask layer  215 . 
     Referring to  FIGS. 1 and 8 , the method  100  proceeds to step  116  by removing a top portion of the gating surface of the gate stack  510  to expose a top portion of the core structure  220  with a third height h 3 . The top portion of the gating surface of the gate stack  510  may be removed by a selective dry etch, a selective wet etch, a combination thereof, or other suitable processes. The hard mask layer  215  is also removed at the same etch process or at an extra etch process. In one embodiment, the gating surface of the gate stack  510  above the second isolation dielectric layer  610  is removed. 
     Referring to  FIGS. 1 and 9 , the method  100  proceeds to step  118  by forming a source region  710  in the top portion of the core structure  220 . The source region  710  may be designed to have a polygon shape which is different than the shape of the middle portion of the core structure  220 . For example, the source region  710  is designed to have a H-shape as its cross-section. 
     In one embodiment, the source region  710  is formed by photolithography patterning and implantation, which is similar in many respects to those discussed above in association with the drain region  310  in  FIG. 4 . The source region  710  has a different dope type than the drain region  310 . In another embodiment, the core structure  220  is recessed first and then the source region  710  is formed as the top portion of the recessed core structure  220  by photolithography patterning and implantation. In yet another embodiment, a semiconductor material is epitaxially grown on the recessed core structure  220 . The semiconductor material layer includes element semiconductor material such as germanium (Ge) or silicon (Si); or compound semiconductor materials, such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs); or semiconductor alloy, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP). The epitaxial processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The S/D features may be formed by one or more epitaxy or epitaxial (epi) processes. The source region  710  may be in-situ doped during the epitaxy process. In one embodiment, the source region  710  is not in-situ doped, an implantation process (i.e., a junction implant process) is performed to dope the source region  710 . 
     A third isolation dielectric layer  810  is deposited over the second isolation dielectric layer  610 , including over the source region  710 . The third isolation dielectric layer  810  is similar in many respects to those discussed above in association with the first isolation dielectric layer  410  in  FIG. 3 . Additionally, a CMP process is performed to planarize the top surface of the third isolation dielectric layer  810 . 
     The TFET device  200  may undergo further CMOS or MOS technology processing to form various features and regions known in the art. For example, subsequent processing may form various contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate  210 , configured to connect the various features or structures of the TFET device  200 . For example, a multilayer interconnection includes vertical interconnects, such as conventional vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may implement various conductive materials including copper, tungsten, and/or silicide. 
     Additional steps can be provided before, during, and after the method  100 , and some of the steps described can be replaced, eliminated, or moved around for additional embodiments of the method  100 . 
     Based on the above, the present disclosure offers a TFET device with a frustoconical protrusion structure (a core structure) and methods of fabrication. With the frustoconical protrusion structure, a vertical TFET device is provided and its fabrication employs quite simple processes. 
     The present disclosure provides many different embodiments of TFET device that provide one or more improvements over other existing approaches. In one embodiment, the TFET device includes a substrate, a frustoconical protrusion structure with a first width disposed over the substrate and protruding out of the plane of substrate, a drain region with a second width disposed over the substrate adjacent to the frustoconical protrusion structure and extending to a bottom portion of the frustoconical protrusion structure as a raised drain region, a gate stack with a third width disposed over the substrate. The gate stack has a planar portion, which is parallel to the surface of substrate and a gating surface, which wraps around a middle portion of the frustoconical protrusion structure, including overlapping with the raised drain region. The TFET device also includes an isolation dielectric layer disposed between the planar portion of the gate stack and the drain region and a source region with the first width disposed as a top portion of the frustoconical protrusion structure, including overlapping with a top portion of the gating surface of the gate stack. 
     In another embodiment, a vertical TFET device includes a semiconductor substrate, a frustoconical protrusion cylinder with a first width disposed over the substrate and protruding out of the plane of semiconductor substrate, a source region as a top portion of the frustoconical protrusion cylinder, a high-k/metal gate (HK/MG) with a second width disposed over the semiconductor substrate. The HK/MG has a planar portion, which is parallel to the surface of semiconductor substrate and a gating surface, which wraps around a middle portion of the frustoconical protrusion cylinder, including overlapping with the source region, a drain region with a third width disposed over the semiconductor substrate adjacent to the frustoconical protrusion cylinder and extending to a bottom portion of the frustoconical protrusion cylinder as a raised drain region, an isolation dielectric layer disposed between the planar portion of the HK/MG and the drain region and an isolation feature disposed between the drain regions. 
     In yet another embodiment, a method of fabricating a semiconductor device includes providing a substrate, etching the substrate to form a protrusion on a surface of the substrate, doping a portion of the substrate adjacent to the protrusion to form a drain region, including extending to a lower portion of the protrusion to form a raised drain region, forming a first isolation dielectric layer over the drain region, forming gate stack with a planar portion over the drain region, which is parallel to the surface of substrate, and a gating surface, which wraps around a middle portion of the protrusion, including overlapping with the raised drain region, forming a second isolation dielectric layer over the planar portion of the gate stack and the drain region, recessing a portion of the gating surface of the gate stack to expose a top portion of the protrusion and forming a source region on the top portion of the protrusion, including overlapping with the gating surface of the gate stack. The source region is formed with a different dope type than the drain region. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and /or achieving the same advantages of the embodiments introduced herein. For example, source and drain regions are often swapped with an appropriate process modification/interchanging, depending on the transistor&#39;s eventual use and electrical configuration. Therefore, the terms “source” and “drain” are deemed to be interchangeable under such circumstances. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.