Patent Publication Number: US-11658007-B2

Title: Apparatus and method of generating a waveform

Description:
BACKGROUND 
     Producing high voltage pulses with fast rise times and/or fast fall times is challenging. For instance, to achieve a fast rise time and/or a fast fall time (e.g., less than about 50 ns) for a high voltage pulse (e.g., greater than about 5 kV), the slope of the pulse rise and/or fall must be incredibly steep (e.g., greater than 10 11  V/s). Such steep rise times and/or fall times are very difficult to produce especially in circuits driving a load with high capacitance. Such pulses may be especially difficult to produce using standard electrical components; and/or with pulses having variable pulse widths, voltages, and repetition rates; and/or within applications having capacitive loads such as, for example, a plasma. 
     SUMMARY 
     Some embodiments may include a high voltage waveform generator comprising: a generator inductor; a high voltage nanosecond pulser electrically and/or inductively coupled with the generator inductor, the high voltage nanosecond pulser configured to charge the generator inductor with: a first pulse burst comprising a first plurality of high voltage pulses, each pulse of the first plurality of pulses having a pulse width, the first pulse burst having a first burst period; and a second pulse burst comprising a second plurality of high voltage pulses, each pulse of the second plurality of pulses having a pulse width, the second pulse burst having a second burst period; and a plasma electrically coupled with the nanosecond pulser and the generator inductor, the voltage across the plasma varying according to: a first plasma pulse having a first output pulse width and a first output voltage, the first output pulse width being substantially equal to the first burst period and the first output voltage being substantially proportional to a pulse width of each of the pulses of the first plurality of pulses, and a second plasma pulse having a second output pulse width and a second output voltage, the second output pulse width being substantially equal to the second burst period and the second output voltage being substantially proportional to a pulse width of each of the pulses of the second plurality of pulses. 
     In some embodiments, either or both the first pulse burst and the second pulse burst has an amplitude greater than 500 V. In some embodiments, either or both the first plasma pulse and the second plasma pulse has an amplitude greater than 500 V. 
     In some embodiments, the second pulse burst has an amplitude that is different than the amplitude of the first pulse burst. In some embodiments, wherein the amplitude of one or more of the first plurality of high voltage pulses is different than amplitude of one or more of the other first plurality of high voltage pulses. In some embodiments, wherein the voltage of the first plasma pulse is different than the voltage of the second plasma pulse. 
     In some embodiments, the high voltage waveform generator may include a pulldown resistor electrically and/or inductively coupled with the generator inductor and the high voltage nanosecond pulser. In some embodiments, the high voltage waveform generator may include a transformer. 
     In some embodiments, the first burst period and/or the second burst period is less than about 50 ms. In some embodiments, either or both the first plasma pulse and the second plasma pulse establish a potential within the plasma. 
     In some embodiments, either or both the first plasma pulse and the second plasma pulse accelerate ions within the plasma. In some embodiments, either or both the first plurality of pulses and/or the second plurality of pulses have a frequency greater than about 50 kHz. In some embodiments, at least one pulse of the first plurality of pulses has a pulse width and/or at least one pulse of the second plurality of pulses has a pulse width less than 500 ns. 
     In some embodiments, the generator inductor comprises stray inductance. In some embodiments, the generator inductor has an inductance less than about 20 μH. In some embodiments, the peak output power is greater than 10 kW. In some embodiments, the plasma is substantially capacitive in nature. 
     Some embodiments may include a high voltage waveform generator comprising: a generator inductor; a generator capacitor electrically and/or inductively coupled with the generator inductor; a high voltage nanosecond pulser electrically or inductively coupled with the generator inductor and the generator capacitor, the high voltage nanosecond pulser configured to charge the generator inductor with a first pulse burst and a second pulse burst; and a load electrically and/or inductively coupled with the nanosecond pulser, the generator inductor, and the generator capacitor, the voltage across the load varying according to: a first load pulse and/or a second load pulse. In some embodiments, the first pulse burst comprises a plurality of high voltage pulses, each pulse of the plurality of pulses having a first pulse width and a voltage greater than 500 V, the first pulse burst having a first burst period; and/or the second pulse burst may comprise a plurality of high voltage pulses, each pulse of the plurality of pulses having a second pulse width and a voltage greater than 500 V, the second pulse burst having a second burst period. In some embodiments, the first load pulse may have a first output pulse width and a first output voltage, the first output pulse width being substantially equal to the first burst period and the first output voltage being proportional to the first pulse width, and the second load pulse may have a second output pulse width and a second output voltage, the second output pulse width being substantially equal to the second burst period and the second output voltage being proportional to the second pulse width. 
     In some embodiments, the first pulse output voltage is greater than 500 V, and the second pulse output voltage is greater than 500 V. In some embodiments, the first pulse output voltage is greater than the second pulse output voltage. In some embodiments, the load comprises a plasma. 
     In some embodiments, the high voltage waveform generator may include a pulldown resistor electrically and/or inductively coupled with the generator inductor and the high voltage nanosecond pulser. In some embodiments, the high voltage waveform generator may include a transformer. In some embodiments, the first burst period is less than about 1 microsecond, the first pulse width is less than about 200 nanoseconds, and the second pulse width is less than about 200 nanoseconds. 
     Some embodiments of the invention include a method for generating high voltage waveforms. In some embodiments, the method may include generating a first pulse burst comprising a plurality of high voltage pulses, each pulse of the plurality of pulses having a first pulse width and a voltage greater than 500 V, the first pulse burst having a first burst period; charging a generator inductor with the first pulse burst; outputting a first output pulse having a first output pulse width and a first output voltage, the first output pulse width being substantially equal to the first burst period and the first output voltage being proportional to the first pulse width; generating a second pulse burst comprising a plurality of high voltage pulses, each pulse of the plurality of pulses having a second pulse width and a voltage greater than 500 V, the second pulse burst having a second burst period; charging a generator inductor with the second pulse burst; and outputting a second output pulse having a first output pulse width and a second output voltage, the second output pulse width being substantially equal to the second burst period and the second output voltage being proportional to the second pulse width. 
     In some embodiments, the first pulse output voltage is greater than 500 V, and the second pulse output voltage is greater than 500 V. In some embodiments, the first pulse output voltage is greater than the second pulse output voltage. In some embodiments, the first output pulse and the second output pulse is provided to a plasma. In some embodiments, the first burst period is less than about 10 ms, the second burst period is less than about 10 ms, the first pulse width is less than 200 nanoseconds, and the second pulse width is less than 200 nanoseconds. 
     Some embodiments of the invention may include a high voltage waveform generator comprising: a generator inductor; a generator capacitor electrically and/or inductively coupled with the generator inductor; a high voltage nanosecond pulser electrically and/or inductively coupled with the generator inductor and the generator capacitor, the high voltage nanosecond pulser configured to charge the generator inductor with a first pulse burst and/or a second pulse burst; and a load electrically and/or inductively coupled with the nanosecond pulser, the generator inductor, and the generator capacitor, the voltage across the load varying according to a first load pulse and a second load pulse. 
     In some embodiments, the first pulse burst may comprise a plurality of high voltage pulses having a first voltage, each pulse of the plurality of pulses having a first pulse width and a voltage greater than 500 V, the first pulse burst having a first burst period. In some embodiments, the second pulse burst may comprise a plurality of high voltage pulses having a second voltage, each pulse of the plurality of pulses having a second pulse width and a voltage greater than 500 V, the second pulse burst having a second burst period. 
     In some embodiments the first load pulse may have a first output pulse width and a first output voltage, the first output pulse width being substantially equal to the first burst period and the first output voltage being a function of the first pulse width and/or the first voltage. In some embodiments, the second load pulse may have a second output pulse width and a second output voltage, the second output pulse width being substantially equal to the second burst period and the second output voltage being a function of the second pulse width and/or the second voltage. 
     In some embodiments, the load comprises a plasma. In some embodiments, the first burst period is less than about 10 ms, the second burst period is less than about 10 ms, the first pulse width is less than 200 nanoseconds, and the second pulse width is less than 200 nanoseconds. 
     Some embodiments of the invention include a high voltage waveform generator comprising a generator inductor; a generator capacitor electrically and/or inductively coupled with the generator inductor; a high voltage nanosecond pulser having one or more solid state switches electrically and/or inductively coupled with the generator inductor and the generator capacitor, the high voltage nanosecond pulser configured to produce a pulse burst having a burst period, the pulse burst comprising a plurality of pulses having different pulse widths; and a load electrically and/or inductively coupled with the high voltage nanosecond pulser, the generator inductor, and the generator capacitor, the voltage across the load having an output pulse with a pulse width substantially equal to the burst period and the voltage across the load varying in a manner that is substantially proportional with the pulse widths of the plurality of pulses. 
     In some embodiments, the load comprises a plasma. In some embodiments, at least a subset of the plurality of pulses have pulse widths with increasingly larger widths and the absolute value of the voltage across the load increases. In some embodiments, the pulse burst has an amplitude greater than about 500 V. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
       These and other features, aspects, and advantages of the present disclosure are better understood when the following Disclosure is read with reference to the accompanying drawings. 
         FIG.  1    is a block diagram of an example high voltage waveform generator according to some embodiments. 
         FIG.  2    is a block diagram of an example high voltage waveform generator according to some embodiments. 
         FIGS.  3 A and  3 B  are block diagrams of example high voltage waveform generators according to some embodiments. 
         FIGS.  4 A and  4 B  are block diagrams of example high voltage waveform generators according to some embodiments. 
         FIGS.  5 A and  5 B  are block diagrams of example high voltage waveform generators according to some embodiments. 
         FIG.  6    is a block diagram of an example high voltage waveform generator according to some embodiments. 
         FIG.  7    is a circuit diagrams of an example high voltage waveform generator according to some embodiments. 
         FIG.  8 A  illustrates an example pulser waveform and an example high voltage waveform generator output waveform according to some embodiments. 
         FIG.  8 B  illustrates an example high voltage waveform generator output waveform according to some embodiments. 
         FIG.  8 C  illustrates an example pulser waveform according to some embodiments. 
         FIG.  8 D  illustrates an example high voltage waveform generator output waveform according to some embodiments. 
         FIGS.  9 A and  9 B  illustrate an example pulser waveform and an example high voltage waveform generator output waveform according to some embodiments. 
         FIGS.  10 A and  10 B  illustrate an example pulser waveform and an example high voltage waveform generator output waveform according to some embodiments. 
         FIGS.  11 A and  11 B  illustrate an example pulser waveform and an example high voltage waveform generator output waveform according to some embodiments. 
         FIG.  12    illustrates example waveforms within various circuit elements of a high voltage waveform generator according to some embodiments. 
         FIG.  13    illustrates example waveforms within various circuit elements of a high voltage waveform generator according to some embodiments. 
         FIG.  14    illustrates example waveforms within various circuit elements of a high voltage waveform generator according to some embodiments. 
         FIG.  15 A  illustrates an example gate voltage waveform. 
         FIG.  15 B  illustrates an example illustrates example pulses produced by the pulser. 
         FIG.  15 C  illustrates an example output waveform. 
         FIG.  15 D  illustrates the voltage across the switch in the pulser. 
     
    
    
     DETAILED DESCRIPTION 
     Systems and methods are disclosed to generate high voltage waveforms with arbitrary pulse widths, voltages, and/or shapes. In some embodiments, a high voltage waveform generator may include a pulser (e.g., a nanosecond pulser) and a generator circuit. For example, a nanosecond pulser may produce a burst of high voltage pulses having a burst period T br  and each pulse of the burst of pulses having a pulse width T p . The generator circuit may produce an output pulse from the input burst of high voltage pulses. The output pulse, for example, may have a pulse width approximately the same as the burst period T br . The output pulse, for example, may have a voltage that is a function of (e.g., proportional to) the pulse width T p  of each pulse of the burst of pulses. The output pulse, for example, may have a voltage that is a function of (e.g., proportional to) the voltage V p  of the input pulses, or the frequency of the input pulses, f p . 
     In some embodiments, the peak power of the output pulses may be greater than about 1 kW, 10 kW, 100 kW, 1,000 kW, 10,000 kW, etc. 
     In some embodiments, the pulser may produce a burst train. Each burst train, for example, may include a plurality of bursts and each of the plurality of bursts may include a plurality of pulses. Each burst of the plurality of bursts (e.g., N bursts) may have a burst period (e.g., T brl , T br2 , T br3 , . . . T brN ). The resulting output of the high voltage waveform generator may include a plurality of pulse widths (e.g., PW br1 , PW br2 , PW br3 , . . . PW brN ) proportional (e.g., roughly equal) to each burst period. In some embodiments, the burst periods may vary resulting in variable output pulse widths. In some embodiments, the output voltage amplitude may be proportional to the pulse width of each pulse within a burst. The voltage of each output pulse may also be proportional to the voltage and frequency of the input pulse burst. 
       FIG.  1    is a block diagram of an example high voltage waveform generator  100  according to some embodiments. The high voltage waveform generator  100  may include a nanosecond pulser  105  and a load  110 . The nanosecond pulser  105  may be electrically and/or inductively coupled with the load  110  via the diode  125 , a generator inductor  115 , and/or a generator capacitor  120 . An additional inductor  116  may also be included. The shape of the waveform across the load  110  may be set by the pulse width of the nanosecond pulser  105  and/or the pulse frequency (or burst period) of the nanosecond pulser  105 , and/or the pulse voltage of the nanosecond pulser  105 . 
     In some embodiments, the additional inductor  116  may not be included. In some embodiments, the additional inductor  116  and the generator inductor  115  may not be included. 
     The nanosecond pulser  105 , for example, may include any device capable of producing pulses greater than 500 V, peak current greater than 10 Amps, and/or pulse widths of less than about 10,000 ns, 1,000 ns, 100 ns, 10 ns, etc. As another example, the nanosecond pulser  105  may produce pulses with an amplitude greater than 1 kV, 5 kV, 10 kV, 50 kV, 200 kV, etc. As another example, the nanosecond pulser  105  may also produces pulse with rise times less than about 5 ns, 50 ns, or 300 ns, etc. 
     The nanosecond pulser  105  may, for example, include any pulser described in U.S. patent application Ser. No. 14/542,487, titled “HIGH VOLTAGE NANOSECOND PULSER”, which is incorporated into this disclosure in its entirety for all purposes. 
     The nanosecond pulser  105  may, for example, include any pulser described in U.S. Pat. No. 9,601,283, titled “EFFICIENT IGBT SWITCHING”, which is incorporated into this disclosure in its entirety for all purposes. 
     The nanosecond pulser  105  may, for example, include any pulser described in U.S. patent application Ser. No. 15/365,094, titled “HIGH VOLTAGE TRANSFORMER”, which is incorporated into this disclosure in its entirety for all purposes. 
     The nanosecond pulser  105  may, for example, include a high voltage switch. For example, the nanosecond pulser  105  may, for example, include any switch described in U.S. Patent Application Ser. No. 62/717,637, filed Aug. 10, 2018, titled “HIGH VOLTAGE SWITCH WITH ISOLATED POWER”, which is incorporated into this disclosure in its entirety for all purposes. 
     In some embodiments, the nanosecond pulser  105  may include one or more solid state switches such as, for example, an IGBT, a MOSFET, a SiC MOSFET, SiC junction transistor, FETs, SiC switches, GaN switches, photoconductive switch, etc. 
     In some embodiments, the generator inductor  115 , for example, may include any inductor having an inductance less than about 3 μH. In some embodiments, the generator inductor  115  may represent stray inductance within the circuit such as, for example, within leads from the nanosecond pulser to other components in the circuit, or other circuit components. In some embodiments, the generator inductor  115  may have an inductance less than 1 μH, 0.1 μH, and 10 nH, 1 μH, 10 μH, 50 μH, etc. 
     In some embodiments, the additional inductor  116 , for example, may include any inductor having an inductance less than about 3 μH. In some embodiments, the additional inductor  116  may represent stray inductance within the circuit such as, for example, within leads from the nanosecond pulser to other components in the circuit, or other circuit components. In some embodiments, the additional inductor  116  may have an inductance less than 1 μH, 0.1 μH, 10 nH, 1 μH, 10 μH, 50 μH, etc. 
     The generator capacitor  120 , for example, may include any capacitor having a capacitance less than about 1 μF. For example, the generator capacitor  120  may have a capacitance be less than 1 μF, 10 μF, 100 nF, 100 pF, etc. The generator capacitor  120  may represent stray capacitance within the circuit such as, for example, within the leads, or between other generator circuit components, or it may represent capacitance contained within the load  110 . 
     In this example, when the nanosecond pulser  105  is turned on and produces a high voltage pulse (e.g., a pulse greater than about 500 V, 5 kV, 10 kV, 15 kV, etc.), energy from the pulse is injected into the generator inductor  115 . The energy from the generator inductor  115  can then charge the generator capacitor  120 . When the nanosecond pulser  105  is turned off, the energy in the generator inductor  115  can continue to charge the generator capacitor  120 . If the pulse width of the high voltage pulse is long enough to completely charge the generator capacitor  120 , the voltage across the generator capacitor  120  can be twice the voltage of the high voltage pulse. By varying the pulse width, the frequency, and/or the voltage of the high voltage pulses, the voltage across the generator capacitor  120  can be varied. For example, the voltage across the generator capacitor  120  may be proportional to the pulse width, frequency, and/or voltage of the high voltage pulse from the nanosecond pulser  105  as shown by the waveforms shown in  FIGS.  8 A,  8 B,  8 C , and  8 D. 
     In some embodiments, the phrase “charge the inductor” can be used to describe energy is passed through the inductor and/or energy is stored within the inductor. 
     In some embodiments, generator inductor  115  may not be used to regulate how much energy charges the generator capacitor  120 . Some energy from the nanosecond pulser  105  may end up in the generator inductor  115 , however, much of the energy will just pass through the generator inductor  115  into the generator capacitor  120 . Thus, in some embodiments, the generator inductor  115  and/or the additional inductor  116  may not be included. 
       FIG.  2    is a block diagram of an example high voltage waveform generator  200  according to some embodiments. In this example, the load is a plasma  111 . The inductors  115  and/or  116  may not be present, or may consist of just the stray circuit inductance. The capacitance  120  may be part of the plasma&#39;s capacitance. The plasma may have a number of unique characteristics, such as, for example, a capacitance, an electron mobility, and an ion mobility that differs from the electron mobility. In this example, output pulses of variable voltages may be applied to the plasma  111 . The plasma  111  may include any type of plasma that may include charged ions and/or charged radicals. In some embodiments, the plasma may be used in a semiconductor fabrication process. In some applications, the output pulse amplitude may be used to control the energy of the plasma ions. In some applications, the ions may be used to etch various materials. These materials may include wafers used in the manμFacture of semiconductors. In some embodiments, the high voltage waveform generator  200  can be used to control the voltage applied across a plasma  111  or a plasma sheath. 
       FIG.  3 A  is a block diagram of an example high voltage waveform generator  300  according to some embodiments. In this example, the high voltage waveform generator  300  may include a driving cable  124  such as, for example, a coax cable or a twin lead cable. 
     In some embodiments, the generator capacitor  120 , for example, may be in series with the load  110  as shown by circuit  350  in  FIG.  3 B . 
       FIG.  4 A  is a block diagram of an example high voltage waveform generator  400  according to some embodiments. In this example, the high voltage waveform generator  400  includes a transformer  121  between the nanosecond pulser  105  and the load  110 . Either the generator L and or C may be present, and/or C might be in series with the load  110 , for example. 
     In some embodiments, the pulse generator  105  may also contain a transformer that may galvanically isolate the pulser output from its input. 
     In some embodiments, the generator capacitor  120  may be in series with the load  110  as shown in circuit  450  as shown in  FIG.  4 B . 
       FIG.  5 A  is a block diagram of an example high voltage waveform generator  500  according to some embodiments. In this example, the high voltage waveform generator  500  includes a pulldown resistor  130 . A switch may also be included in series with the pulldown resistor  130 . The pulldown resistor  130  may, for example, include any embodiment described in U.S. patent application Ser. No. 15/941,731, titled “HIGH VOLTAGE PASSIVE OUTPUT STAGE CIRCUIT”, which is incorporated into this disclosure in its entirety for all purposes. 
     In some embodiments, the generator capacitor  120  may be in series with the load  110  as shown in circuit  550  in  FIG.  5 B . In some embodiments, the generator capacitor  120  may be part of the load  110  and/or include all or part of the capacitance of the load  110 . In some embodiments, the pull down resistor  130  may be placed before the generator capacitor  120 , the effective load capacitance  115 , and/or the diode  125 , i.e. placed closer to generator  105 . 
       FIG.  6    is a block diagram of an example high voltage waveform generator  600  according to some embodiments. In this example, the high voltage waveform generator  600  may include a load having an effective load capacitance  115 , an effective load current generator  140 , and/or an effective load diode  142  and an effective system inductance  115 . A plasma, for example, may be idealized by the effective current generator  140 , the effective load diode  142 , and the effective load capacitance  143 . In some embodiments, the effective current generator  140  can represent the plasma ion current. In some embodiments, the ion plasma current can flow fairly steadily between the input pulses, for around the duration of the output pulse. In some embodiments, the effective load capacitance  143  can represent the capacitance formed in the plasma. In some embodiments, effective load capacitance  115  can represent the capacitance across the material/item/component being treated by the plasma, for example a semiconductor wafer being etched. In some embodiments, the effective load diode  142  can represent the electron mobility within the plasma, and/or the flow of current through the plasma driven by the input nanosecond pulses, that occurs around the duration of the input pulse burst. 
       FIG.  7    shows another example high voltage waveform generator  700  according to some embodiments. The high voltage waveform generator  700  can be generalized into five stages (these stages could be broken down into other stages or generalized into fewer stages). The high voltage waveform generator  700  includes pulser and transformer stage  706 , a resistive output stage  707 , a lead stage  710 , a blocking capacitor and DC bias power supply stage  711 , and a load stage  110 . 
     In this example, the load stage  110  may represent an effective circuit for a plasma deposition system, plasma etch system, or plasma sputtering system. In some embodiments, the capacitance of capacitor C 1  and/or capacitor C 12  may be less than about 50 μF, 10 μF, 1μF, 100 nF, etc. The capacitor C 2  may represent the capacitance of the dielectric material upon which a wafer may sit. In some embodiments, the capacitor C 2  may be less than about 50 μF, 10 μF, 1 μF, 100 nF, etc. The capacitor C 3  may represent the sheath capacitance of the plasma to the wafer. In some embodiments, the capacitor C 3  may be less than about 50 μF, 10 μF, 1μF, 100 nF, etc. The capacitor C 9  may represent capacitance within the plasma between a chamber wall and the top surface of the wafer. The current source I 2  and the current source I 1  may represent the ion current through the sheath. 
     In this example, the resistive output stage  707  may include one or more inductive elements represented by inductor L 1  and/or inductor L 5 . The inductor L 5 , for example, may represent the stray inductance of the leads in the resistive output stage  707 . Inductor L 1  may be set to minimize the power that flows directly from the pulser and transformer stage  706  into resistor R 1 . In some embodiments, the resistance of resistor R 1  can be less than about 2,000 Ohms, 200 Ohms, 20 Ohms, 2 Ohms, etc. 
     In some embodiments, the inductor L 2 , inductor L 5 , and/or inductor L 6  may have an inductance less than about 100 μH, 10 μH, 1 μH, 100 nH, etc. 
     In some embodiments, the resistor R 1  may dissipate charge from the load  110 , for example, on fast time scales (e.g., 1 ns, 10 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc. time scales). The resistance of resistor R 1  may be low to ensure the pulse across the load  110  has a fast fall time t f . 
     In some embodiments, the resistor R 1  may include a plurality of resistors arranged in series and/or parallel. The capacitor C 11  may represent the stray capacitance of the resistor R 1  including the capacitance of the arrangement series and/or parallel resistors. The capacitance of stray capacitance C 11 , for example, may be less than 2000 pF, 500 pF, 250 pF, 100 pF, 50 pF, 10 pF, 1 pF, etc. The capacitance of stray capacitance C 11 , for example, may be less than the load capacitance such as, for example, less than the capacitance of C 2 , C 3 , and/or C 9 . 
     In some embodiments, a plurality of pulser and transformer stages  706  can be ganged up in parallel and coupled with the resistive output stage  707  across the inductor L 1  and/or the resistor R 1 . Each of the plurality of pulser and transformer stages  706  may each also include diode D 1  and/or diode D 6 . In some embodiments, the inductance of inductor L 1  can be less than about 1,000 μH, 100 μH, 10 μH, etc. 
     In some embodiments, the capacitor C 8  may represent the stray capacitance of the blocking diode D 1 . In some embodiments, the capacitor C 4  may represent the stray capacitance of the diode D 6 . 
     In some embodiments, the DC bias power supply stage  711  may include DC a voltage source V 1  that can be used to bias the output voltage either positively or negatively. In some embodiments, the capacitor C 12  isolates/separates the DC bias voltage from the resistive output stage and other circuit elements. The capacitor C 12  may be referenced as either a blocking capacitor and/or a bias capacitor. In some embodiments, capacitor C 12  may comprise a single capacitive element, or numerous capacitive elements combined. In some embodiments, capacitor C 12  may allow for a potential shift from one portion of the circuit to another. In some embodiments, the potential shift capacitor C 12  establishes may be used to hold a wafer in place using electrostatic forces. In some embodiments, the capacitance of capacitor C 12  may be less than about 1000 μF, 100 μF, 10 μF, 1μF, etc. 
     Resistance R 2  may protect/isolate the DC bias supply from the high voltage pulsed output from the pulser and transformer stage  706 . In some embodiments, the DC bias power supply stage may contain additional elements such as switches, diodes, and capacitors, to help keep the electrostatic forces holding a wafer in place fairly constant in time, as the output pulse cycles on and off such as, for example, U.S. Patent Application Ser. No. 62/711,406, filed Aug. 10, 2018, titled “NANOSECOND PULSER BIAS COMPENSATION”, which is incorporated into this disclosure in its entirety for all purposes. 
     In some embodiments, the pulser and transformer stage  706  may include a plurality of switches and a plurality of signal generators. A plurality of switches, for example, may allow the nanosecond pulser to produce higher frequency pulses. 
     In some embodiments, the voltage source V 2  provides a consistent DC voltage that is switched by switch S 1 . Switch S 1 , for example, may include one or more solid state switches such as, for example, an IGBT, a MOSFET, a SiC MOSFET, SiC junction transistor, FETs, SiC switches, GaN switches, photoconductive switch, etc. Switch S 1  may switch so fast that the switched voltage may never be at full voltage. For example, if voltage source V 2  provides a DC voltage of 500 V, then the switch S 1  may be turned on and turned off so quickly that the voltage across the switch is less than 500 V. In some embodiments, a gate resistor coupled with the switch S 1  may be set with short turn on pulses. 
       FIG.  8 A  illustrates an example pulser waveform and  FIG.  8 B  illustrates an example high voltage waveform generator output waveform according to some embodiments. In this example, the waveform produced by the pulser include two bursts: a first burst with a burst period B 1  with each pulse having a pulse width T 1 ; and a second burst with a burst period B 2  with each pulse having a pulse width T 2 . The waveform output is the output of the waveform generator based on the waveform produced by the pulser. In this example, the waveform generator outputs two pulses: a first pulse having a pulse width PW 1  and a voltage V 1 ; and a second pulse having a pulse width PW 2  and a voltage V 2 . In this example, the PW 1  is the same length as the burst period B 1  within 10%; and the first pulse voltage V 1  is a function of (e.g., proportional to) the pulse width T 1 . In addition, the PW 2  is the same length as the burst period B 2  within 10%; and the first pulse voltage V 2  is a function of (e.g., proportional to) the pulse width T 2 . PW 1  and PW 2  may have widths that deviate from B 1  and B 2  due to circuit phase delays, and the charging and discharging of various circuit elements. However, the input and output lengths are strongly correlated, with the input burst lengths being used to control the output pulse lengths. Load properties will also impact the exact correlation between the input burst width and the output pulse width. The flatness of the output pulses may also vary based on the circuit elements selected, and/or may show a natural oscillation/response to the input pulses that comprise the burst. 
     In some embodiments, the time between pulses can be any value. In some embodiments, the time between pulses can be on the order of the pulse width of an individual pulse. 
     In some embodiments, the frequency of the pulses within each burst may be greater than about 1 kHz, 10 kHz, 100 kHz, 1,000 kHz, etc. 
       FIG.  8 C  illustrates an example pulser waveform and  FIG.  8 D  illustrates an example high voltage waveform generator output waveform according to some embodiments. In this example, the input waveforms are inverted in comparison with those shown in  FIG.  8 A , resulting in inverted output waveforms shown in  FIG.  8 D . In this example, the pulse widths of the output pulses PW 1  and PW 2  are substantially similar to the burst period B 1  and B 2 . The waveforms shown in  FIGS.  9 ,  10 , and  11    can likewise be inverted.The flatness of the output pulses may also vary based on the circuit elements selected, and/or may show a natural oscillation/response to the input pulses that comprise the burst. 
       FIG.  9 A  illustrates an example waveform produced by the pulser and  FIG.  9 B  illustrates an example high voltage waveform generator output waveform according to some embodiments. In this example, the first two pulses of the first burst of the pulser output as shown in  FIG.  9 A  are shorter than the other pulses within the burst. This results in an output pulse that slowly ramps up to V 2  or V 1  as shown in  FIG.  9 B . This may be done to limit the peak output current and/or energy from the pulser. 
     The output waveforms shown in  FIGS.  8 B,  8 D, and  9 B  may be referred to as a form of ‘bi-level’ control, where the intent is to apply a series of 1 or more output pulses of one voltage alternating with a series of one or more output pulses with a different voltage. For example, this may allow high energy ions to interact with a surface/material, followed by low energy ions interacting with a surface/material. 
       FIG.  10 A  illustrates an example waveform produced by the pulser and  FIG.  10 B  illustrates an example high voltage waveform generator output waveform according to some embodiments. In this example, the pulse width of each pulse within a burst increases linearly as shown in  FIG.  10 A  resulting in an output waveform voltage that similarly decreases linearly as shown in  FIG.  10 B . 
       FIG.  11 A  illustrates an example waveform produced by the pulser and  FIG.  11 B  illustrates an example high voltage waveform generator output waveform according to some embodiments. In this example, three bursts having three different burst widths and the pulses within each burst have different pulse widths as shown in  FIG.  11 A . This results in three output pulses with three different pulse widths and different voltages as shown in  FIG.  11 B . 
     The shape of the output waveform can be dictated by the pulse width of each pulse within a burst and/or the burst width. Any shape of output waveform may be produced by varying these parameters. Such shapes may be repeated and interleaved with any other set of output pulse shapes, and may be done so in a repetitive manner. In some embodiments, the shape of the output waveform can be controlled/set by varying the voltage of the individual pulses. Varying the pulse width may vary the pulse voltage as well. 
     In some embodiments, multiple nanosecond pulsers may be phased together. For example, the nanosecond pulser  105  may include one or more pulsers phased together in parallel. This may, for example, generate output pulses from the waveform generator at higher frequencies. 
       FIG.  12    illustrates example waveforms within various circuit elements of a high voltage waveform generator according to some embodiments. The waveforms shown in  FIG.  12    relate to the components shown in  FIG.  7   . 
       FIG.  13    and  FIG.  14    illustrates example waveforms within various circuit elements of a high voltage waveform generator according to some embodiments. The waveforms shown in  FIG.  12    relate to the components shown in  FIG.  7   . 
     In some embodiments, a high voltage waveform generator may use real time feedback to adjust the output voltage of an output waveform. For example, a circuit can determine that the voltage of an output waveform is lower than expected, in response the pulse width of the nanosecond pulser may be adjusted to produce the desired output pulse. Alternatively, the number of pulses within a burst may be adjusted, and/or their frequency may be adjusted. 
     In some embodiments, a plurality of pulsers may be used in a high voltage waveform generator  750 . For example, a first pulser and a second pulser can be phased together with one or more switches. Linking together these pulses can be done to increase the frequency of the pulses provided to the load. In some embodiments, each of the pulsers may produce a different drive voltage. 
     In some embodiments, the resistor at the gate of one or more MOSFETs within the pulser may be selected to enable a working range between high levels and low levels in bi-level operation. In some embodiments, the resistor at the gate of one or more MOSFETs may provide short circuit protection. In some embodiments, different gate voltages may be applied to one or more MOSFETs within the pulser. 
     In some embodiments, the turn on time of one or more switches within the nanosecond pulser  105  may result in lower output voltage from the pulser when the pulse width is less than the rise time. This is illustrated in  FIG.  15 C . V 3 , for example, may be 5 kV or greater and V 4 , for example, may be greater than 200 volts. 
     A pulser may include a high voltage DC input and a low voltage DC waveform for controlling the solid-state switches or gate voltage. The waveform shown in  FIG.  15 A  shows the gate voltage with two bursts each having a burst period, B 1  and B 2 , and the pulses within each burst having a different pulse width. The waveform in  FIG.  15 B  shows example pulses produced by the pulser (e.g., the voltage across R 1  in  FIG.  7   ). The voltage of the pulses within the first burst are at V 1  and the pulses within the second burst are at V 2 . The pulse voltages in the second burst are lower because the gate voltage pulse widths are shorter. Specifically, the gate voltage pulses are sufficiently short that the pulser switches do not have time to fully turn on, (e.g., reach their peak output voltage) before the pulse switches are turned back off by the gate input pulse. The waveform in  FIG.  15 D  is the voltage across the switch in the pulser (e.g., switch S 1  in  FIG.  7   ). The switches are gated on for a sufficiently short period that the voltage across the switch is never able to fall to the low level that it would normally be for a switch fully turned on and in full conduction. The resulting output waveform shown in  FIG.  15 C  has two voltage levels. The second voltage level is a function of the pulse width of the gate voltage waveform ( FIG.  15 A ). Because the pulse widths of the second pulses are shorter than the switch rise time, or the switch turn-on time, or the switch time needed to reach full conduction, lower voltage pulses are produced by the pulser. The second voltage level in  FIG.  15 C  is a function of the pulse width and the voltage produced by the pulser shown in  FIG.  15 B . The gate resistance of one or more switches in the pulser may determine the rise time and voltage of the pulses provided by the pulser. 
     In some embodiments, the output voltage shown in  FIG.  15 C  is a function of single pulses shown in  FIG.  15 A . In some embodiments, output voltage control is provided using the switches to control output voltage. Some embodiments may enable very fast, nanosecond timescale, output voltage modulation, at bi-level voltage output. This can, for example, allow for fast voltage modulation (e.g., greater than 1 MHz). 
     Numerous specific details are set forth herein to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter may be practiced without these specific details. In other instances, methods, apparatuses or systems that would be known by one of ordinary skill have not been described in detail so as not to obscure claimed subject matter. 
     Some portions are presented in terms of algorithms or symbolic representations of operations on data bits or binary digital signals stored within a computing system memory, such as a computer memory. These algorithmic descriptions or representations are examples of techniques used by those of ordinary skill in the data processing arts to convey the substance of their work to others skilled in the art. An algorithm is a self-consistent sequence of operations or similar processing leading to a desired result. In this context, operations or processing involves physical manipulation of physical quantities. Typically, although not necessarily, such quantities may take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared or otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to such signals as bits, data, values, elements, symbols, characters, terms, numbers, numerals or the like. It should be understood, however, that all of these and similar terms are to be associated with appropriate physical quantities and are merely convenient labels. Unless specifically stated otherwise, it is appreciated that throughout this specification discussions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” and “identifying” or the like refer to actions or processes of a computing device, such as one or more computers or a similar electronic computing device or devices, that manipulate or transform data represented as physical electronic or magnetic quantities within memories, registers, or other information storage devices, transmission devices, or display devices of the computing platform. 
     The system or systems discussed herein are not limited to any particular hardware architecture or configuration. A computing device can include any suitable arrangement of components that provides a result conditioned on one or more inputs. Suitable computing devices include multipurpose microprocessor-based computer systems accessing stored software that programs or configures the computing system from a general purpose computing apparatus to a specialized computing apparatus implementing one or more embodiments of the present subject matter. Any suitable programming, scripting, or other type of language or combinations of languages may be used to implement the teachings contained herein in software to be used in programming or configuring a computing device. 
     Embodiments of the methods disclosed herein may be performed in the operation of such computing devices. The order of the blocks presented in the examples above can be varied—for example, blocks can be re-ordered, combined, and/or broken into sub-blocks. Certain blocks or processes can be performed in parallel. 
     The use of “adapted to” or “configured to” herein is meant as open and inclusive language that does not foreclose devices adapted to or configured to perform additional tasks or steps. Additionally, the use of “based on” is meant to be open and inclusive, in that a process, step, calculation, or other action “based on” one or more recited conditions or values may, in practice, be based on additional conditions or values beyond those recited. Headings, lists, and numbering included herein are for ease of explanation only and are not meant to be limiting. 
     The terms “first” and “second” are not necessarily used to identify the absolute or very first or second of sequence of items. Rather, these terms are used solely to label an item and a different or subsequent item unless the meaning is clear that the terms are meant to specify a specific order or absolute position. The order of the items labeled with “first” and “second” may or may not be the absolute order and/or may include other items in between. 
     While the present subject matter has been described in detail with respect to specific embodiments thereof, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily produce alterations to, variations of, and equivalents to such embodiments. Accordingly, it should be understood that the present disclosure has been presented for purposes of example rather than limitation, and does not preclude inclusion of such modifications, variations and/or additions to the present subject matter as would be readily apparent to one of ordinary skill in the art.